Abstract:
A differential switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough and preventing an unwanted momentary frequency shift and drift in the VCO output frequency when the switched capacitor circuit is shut off. A center switch element connects a positive side capacitance node with a negative side capacitance node depending on a first control signal. A positive side primary switch element and a negative side primary switch element connect the positive and negative side capacitance nodes depending on the first control signal. A positive side additional switch element and negative side additional switch element with control signals complementary to the first control signal cancel the clock feedthrough of the center switch and the positive and negative side primary switch elements at the positive and negative side capacitance nodes respectively.

Description:
BACKGROUND OF INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit for use in a voltage controlled oscillator (VGO) that eliminates the clock feedthrough effect thereby preventing a momentary VCO frequency shift and drift when the switched capacitor circuit is switched on or off.  
           [0003]    2. Description of the Prior Art  
           [0004]    A voltage controlled oscillator (VCO) is commonly used for frequency synthesis in wireless communication circuits. As Welland, et al. state in U.S. Pat. Nos. 6,226,506 and 6,147,567, wireless communication systems typically require frequency synthesis in both the receive path circuitry and the transmit path circuitry.  
           [0005]    [0005]FIG. 1 shows a VCO circuit with digital tuning according to the prior art. A VCO  10  used in a frequency synthesizer solution is typically based on a resonant structure. Ceramic resonators and LC tank circuits are common examples. While details in the implementation of LC tank oscillators differ, the basic resonant structure includes an inductor  12  connected between a first oscillator node OSC_P and a second oscillator node OSC_N. Connected in parallel with the inductor  12  is a continuously variable capacitor  14  as the varactor and a plurality of discretely variable capacitors  16 . The continuously variable capacitor  14  is used for fine-tuning the desired capacitance while the plurality of discretely variable capacitors  16  is used for coarse tuning. The resistive loss of the parallel combination of an inductor and capacitors is compensated by a negative resistance generator  18  to sustain the oscillation.  
           [0006]    Each discretely variable capacitor in the plurality of discretely variable capacitors  16  is made up of a switched capacitor circuit  20  and each switched capacitor circuit is controlled by an independent control signal  22 . Based on this control signal  22  the switched capacitor circuit  20  can selectively connect or disconnect a capacitance  24  to the resonator of the VCO  10 . Different on/off combinations of switched capacitor arrays result in a wider capacitance range of the LC type resonator and hence a wider VCO  10  oscillation frequency coverage.  
           [0007]    [0007]FIG. 2 shows a single ended switched capacitor circuit  30  according to the prior art. A capacitor  32  is connected between the first oscillator node OSC_P and a node A. A switch element  34  having an NMOS transistor selectively connects node A to the second oscillator node OSC_N that is connected to ground, and the switch element  34  is controlled by a control signal SW. When the switch element  34  is turned on, the capacitance associated with the capacitor  32  is added to the overall capacitance in the VCO  10  resonator. When the switch element  34  is turned off the capacitance looking into the first oscillator node OSC_P is the series combination of the capacitor  32  and the off state capacitance associated with the switch element  34 .  
           [0008]    [0008]FIG. 3 shows another prior art switched capacitor circuit  40 , which is a differential implementation without a center switch. Differential implementations have much greater common-mode noise rejection and are widely used in high-speed integrated circuit environments. In the differential without center switch switched capacitor circuit  40 , a positive side capacitor  42  is connected between the first oscillator node OSC_P and a node A. A positive side switch element  46  having an NMOS transistor selectively connects node A to ground. A negative side capacitor  44  is connected between the second oscillator node OSC_N and a node B. A negative side switch element  48  having an NMOS transistor selectively connects node B to ground. The two switch elements  46 ,  48  are controlled by the same control signal SW. When the switch elements are turned on, the capacitance associated with the series combination of the positive and negative side capacitors  42 ,  44  is added to the overall capacitance in the VCO  10  resonator. When the switch elements  46 ,  48  are turned off, the differential capacitance between the oscillator nodes OSC_P and OSC_N is the combination of the positive and negative side capacitors  42 ,  44  and the parasitic capacitance of the off state switch elements in the VCO  10  resonator.  
           [0009]    [0009]FIG. 4 shows a prior art switched capacitor circuit  60 , which is a differential implementation with a center switch. In the differential with center switch switched capacitor circuit  60 , a positive side capacitor  62  is connected between the first oscillator node OSC_P and a node A. A positive side switch element  68  having an NMOS transistor selectively connects node A to ground. A negative side capacitor  66  is connected between the second oscillator node OSC_N and a node B. A negative side switch element  70  having an NMOS transistor selectively connects node B to ground. There is also a center switch element  64  having an NMOS transistor used to lower the overall turn-on switch resistance connected between node A and node B. All three switch elements  64 ,  68 ,  70  are controlled by the same control signal SW. When the switch elements  64 ,  68 ,  70  are turned on, the capacitance associated with the series combination of the positive and negative side capacitors  62 ,  66  is added to the overall capacitance in the VCO  10  resonator. When the switch elements  64 ,  68 ,  70  are turned off, the differential capacitance between the oscillator nodes OSC_P and OSC_N is the combination of the positive and negative side capacitors  62 ,  66  and the parasitic capacitance of the off state switch elements in the VCO  10  resonator.  
           [0010]    [0010]FIG. 5 shows a prior art switched capacitor circuit  90 , which is a differential implementation with only a center switch. In the differential only center switch switched capacitor circuit  90 , a positive side capacitor  92  is connected between the first oscillator node OSC_P and a node A. A negative side capacitor  96  is connected between the second oscillator node OSC_N and a node B. There is a center switch element  94  having an NMOS transistor used to lower the turn-on switch resistance connected between the node A and node B. The switch element  94  is controlled by the control signal SW. When the switch element  94  is turned on, the capacitance associated with the series combination of the positive and negative side capacitors  92 ,  96  is added to the overall capacitance in the VCO  10  resonator. When the switch element  94  is turned off, the differential capacitance between the oscillator nodes OSC_P and OSC_N is the combination of the positive and negative side capacitors  92 ,  96  and the parasitic capacitance of the off state switch elements in the VCO  10  resonator.  
           [0011]    Regardless of whether the single ended implementation shown in FIG. 2 or the differential implementation shown in FIG. 3, FIG. 4 and FIG. 5 is used, when the switched capacitor circuit  30 ,  40 ,  60 , or  90  is turned off, a momentary voltage step occurs at node A (and in the case of the differential implementation shown in FIG. 3, FIG. 4 and FIG. 5 also at node B). The momentary voltage step causes an unwanted change in the overall capacitance that is contributed from switches and parasitic diodes of switches, and ultimately, an unwanted change in the VCO  10  frequency. This momentary voltage step could be a voltage drop or rise depending on whether the switch elements are turned off or on with a logic low signal or a logic high signal respectively.  
           [0012]    Using the single ended case shown in FIG. 2 as an example, when the switch element  34  is turned off, charge carriers are injected towards the impedances connected to the first terminal and the second terminal of the switch element  34 . The injection produces an undesired voltage step across the capacitive impedance and appears as a voltage step at node A. This effect is known as clock feedthrough effect (or simply called “clock feedthrough”) and appears as a feedthrough of the control signal SW from the control terminal of the switch element  34  to the first and second terminals of the switch element  34 . When the switch element  34  is turned on, node A is connected to ground so the feedthrough of the control signal SW is of no consequence. However, when the switch element  34  is turned off, the feedthrough of the control signal SW causes a voltage step, in the form of a voltage drop to appear at node A. Because of the dropped voltage at node A, the floating parasitic diode formed by the N+ diffusion of NMOS switch element  34  and the P type substrate in the off state will be slightly forward biased. The voltage level at node A will spike low and then recover to ground potential as the forward biased junction diode formed by the switch element  34  in the off state allows current to flow. The voltage step and recovery at node A changes the capacitance of the VCO  10  resonator and causes an unwanted momentarily shift and drift in the VCO  10  frequency.  
           [0013]    When the differential switched capacitor circuits  40 ,  60  and  90 , shown in FIG. 3, FIG. 4, and FIG. 5 respectively, switch off, they with the floating parasitic diodes suffer from the same clock feedthrough problem at node A and at node B. Using the differential with center switch switched capacitor circuit  60  shown in FIG. 4 as an example, the positive side node A has an unwanted voltage step caused by the clock feedthrough of both the positive side switch element  68  and the clock feedthrough of the center switch element  64 . Similarly, the negative side node B has an unwanted voltage step caused by the clock feedthrough of both the negative side switch element  70  and the clock feedthrough of the center switch element  64 . The voltage step and recovery at node A and node B changes the capacitance of the VCO  10  resonator and causes an unwanted momentary shift and drift in the VCO  10  frequency.  
         SUMMARY OF INVENTION  
         [0014]    It is therefore a primary objective of the present invention to provide a switched capacitor circuit capable of eliminating clock feedthrough by complementary control signals, to solve the above-mentioned problem for digital tuning VCOs.  
           [0015]    According to the present invention, a single-ended switched capacitor circuit capable of eliminating clock feedthrough by using a dummy switch that is specified of adequate size. A control signal generator generates a first control signal and a second control signal, wherein the second control signal is complementary to the first control signal. A switch element selectively connects a terminal node to a capacitance depending on the first control signal. A dummy switch element selectively connects to the terminal node depending on the second control signal.  
           [0016]    According to the present invention, a differential switched capacitor circuit capable of eliminating clock feedthrough by using dummy switches that are specified of adequate size. A control signal generator generates a first control signal and a second control signal, wherein the second control signal is complementary to the first control signal. A center switch element selectively connects a positive side capacitance to a negative side capacitance depending upon the first control signal. A positive side dummy switch element selectively connects to a positive side node of the center switch element depending upon the second control signal. A negative side dummy switch element selectively connects the to a negative side node of the center switch element depending on the second control signal.  
           [0017]    According to the present invention, a single-ended switched capacitor circuit capable of eliminating clock feedthrough by using a complementary switch that is specified of adequate size. A control signal generator generates a first control signal and a second control signal, wherein the second control signal is complementary to the first control signal. A switch element selectively connects a terminal node to a capacitance depending on the first control signal. A complementary switch element selectively connects to the terminal nodes of the switch element depending on the second control signal.  
           [0018]    According to the present invention, a differential switched capacitor circuit capable of eliminating clock feedthrough by using complementary switches that are specified of adequate size. A control signal generator generates a first control signal and a second control signal, wherein the second control signal is complementary to the first control signal. A center switch element selectively connects a positive side capacitance to a negative side capacitance depending upon the first control signal. A complementary switch element selectively connects to the terminal nodes of the center switch element depending upon the second control signal.  
           [0019]    It is an advantage of the present invention that the clock feedthrough produced at the capacitance node by the switch element is cancelled by the complementary clock feedthrough produced by the dummy switch element or the complementary switch element with a complementary control signal. A switched capacitor circuit of the present invention for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough by complementary control signals and preventing an unwanted momentary frequency shift and drift phenomenon in the VCO output frequency when the switched capacitor circuit is switched on or off.  
           [0020]    These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.  
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0021]    [0021]FIG. 1 is a schematic diagram of a typical Voltage Controlled Oscillator (VCO) circuit with switched capacitor circuits used in a frequency synthesizer according to the prior art.  
         [0022]    [0022]FIG. 2 shows a single ended switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.  
         [0023]    [0023]FIG. 3 shows a differential without center switch switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.  
         [0024]    [0024]FIG. 4 shows a differential with center switch switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.  
         [0025]    [0025]FIG. 5 shows a differential only center switch switched capacitor circuit used in the VCO of FIG. 1 according to the prior art.  
         [0026]    [0026]FIG. 6 shows the first embodiment of the present invention for a single ended switched capacitor circuit.  
         [0027]    [0027]FIG. 7 shows a signal diagram of the first control signal and the second control signal generated by the control signal generator in FIG. 6.  
         [0028]    [0028]FIG. 8 shows the first embodiment of the present invention for a differential without center switch switched capacitor circuit.  
         [0029]    [0029]FIG. 9 shows the first embodiment of the present invention for a differential with center switch switched capacitor circuit.  
         [0030]    [0030]FIG. 10 shows the first embodiment of the present invention for a differential only center switch switched capacitor circuit.  
         [0031]    [0031]FIG. 11 shows the second embodiment of the present invention for a single ended switched capacitor circuit.  
         [0032]    [0032]FIG. 12 shows the second embodiment of the present invention for a differential without center switch switched capacitor circuit.  
         [0033]    [0033]FIG. 13 shows the second embodiment of the present invention for a differential with center switch switched capacitor circuit.  
         [0034]    [0034]FIG. 14 shows the second embodiment of the present invention for a differential only center switch switched capacitor circuit.  
         [0035]    [0035]FIG. 15 shows the third embodiment of the present invention for a single ended switched capacitor circuit.  
         [0036]    [0036]FIG. 16 shows the first version of the third embodiment of the present invention for a differential without center switch switched capacitor circuit.  
         [0037]    [0037]FIG. 17 shows the second version of the third embodiment of the invention for a differential without center switch switched capacitor circuit.  
         [0038]    [0038]FIG. 18 shows the third version of the third embodiment of the present invention for a differential without center switch switched capacitor circuit.  
         [0039]    [0039]FIG. 19 shows the first version of the third embodiment of the present invention for a differential with center switch switched capacitor circuit.  
         [0040]    [0040]FIG. 20 shows the second version of the third embodiment of the invention for a differential with center switch switched capacitor circuit.  
         [0041]    [0041]FIG. 21 shows the third version of the third embodiment of the present invention for a differential with center switch switched capacitor circuit.  
         [0042]    [0042]FIG. 22 shows the first version of the third embodiment of the present invention for a differential only center switch switched capacitor circuit.  
         [0043]    [0043]FIG. 23 shows the second version of the third embodiment of the invention for a differential only center switch switched capacitor circuit.  
         [0044]    [0044]FIG. 24 shows the third version of the third embodiment of the present invention for a differential only center switch switched capacitor circuit.  
         [0045]    [0045]FIG. 24 shows the third version of the third embodiment of the present invention for a differential only center switch switched capacitor circuit. 
     
    
     DETAILED DESCRIPTION  
       [0046]    [0046]FIG. 6 shows a single ended switched capacitor circuit  130  according to the first embodiment of the present invention. In the first embodiment, the singled ended switched capacitor circuit  130  includes a capacitor  132 , a primary switch element  134  having an NMOS transistor, a dummy switch element  136  having an NMOS transistor, and a control signal generator  138 .  
         [0047]    [0047]FIG. 7 shows a signal diagram of a first control signal SW 1  and a second control signal SW 2  generated by the control signal generator  138 . The control signal generator  138  provides the first control signal SW 1  and the first control signal SW 2 , wherein the second control signal SW 2  is complementary to the first control signal SW 1 . At time t, the switched capacitor switch  130  is switched off and, as shown in FIG. 7, the second control signal SW 2  is complementary to the first control signal SW 1 .  
         [0048]    In FIG. 6, the capacitor  132  is connected between the first oscillator node OSC_P and a node A. The primary switch element  134  selectively connects node A to ground based on the first control signal SW 1 . The dummy switch element  136  has a first terminal connected to node A, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected.  
         [0049]    The clock feedthrough at node A has two sources: the clock feedthrough from the primary switch element  134  and the clock feedthrough from the dummy switch element  136 . Because the primary switch element  134  is controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to switch element  134  will be opposite in polarity to the clock feedthrough produced at node A due to the dummy switch element  136 , which is controlled by the second control signal SW 2 . One property of clock feedthrough is that the larger the switch element the larger the voltage step at the capacitance node when the switch element is switched to the off state. By properly sizing the dummy switch element  136  such that the voltage step caused by the switch element  136  is of equal magnitude (but opposite polarity) as the clock feedthrough caused by the switch element  134 , the unwanted voltage step at node A is eliminated.  
         [0050]    [0050]FIG. 8 shows a differential without center switch switched capacitor circuit  140  according to the first embodiment of the present invention. In the first embodiment, the differential without center switch switched capacitor circuit  140  includes a positive side capacitor  142 , a negative side capacitor  144 , a positive side primary switch element  146  having an NMOS transistor, a negative side primary switch element  148  having an NMOS transistor, a positive side dummy switch element  150  having an NMOS transistor, a negative side dummy switch element  152  having an NMOS transistor, and a control signal generator  154 .  
         [0051]    The positive side capacitor  142  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  144  is connected between the second oscillator node OSC_N and a node B. The control signal generator  154  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The positive side primary switch element  146  selectively connects node A to ground based on the first control signal SW 1  and the negative side primary switch element  148  selectively connects node B to ground based on the first control signal SW 1 . The positive side dummy switch element  150  has a first terminal connected to node A, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected. The negative side dummy switch element  152  has a first terminal connected to node B, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected.  
         [0052]    The clock feedthrough at node A has two sources: the clock feedthrough from the positive side primary switch element  146  and the clock feedthrough from the positive side dummy switch element  150 . Because the positive side primary switch element  146  is controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to the switch element  146  will be opposite in polarity to the clock feedthrough produced at node A due to the positive side dummy switch element  150 , which is controlled by the second control signal SW 2 . By properly sizing the positive side dummy switch element  150  such that the voltage step caused by the switch element  150  is of equal magnitude (but opposite polarity) as the clock feedthrough caused by the switch element  146 , the unwanted voltage step at node A is eliminated.  
         [0053]    Similarly, the clock feedthrough at node B has two sources: the clock feedthrough from the negative side primary switch element  148  and the clock feedthrough from the negative side dummy switch element  152 . Because the negative side primary switch element  148  is controlled by the first control signal SW 1 , the clock feedthrough produced at node B due to the switch element  148  will be opposite in polarity to the clock feedthrough produced at node B due to the negative side dummy switch element  152 , which is controlled by the second control signal SW 2 . By properly sizing the negative side dummy switch element  152  such that the voltage step caused by the switch element  152  is of equal magnitude (but opposite polarity) as the clock feedthrough caused by the switch element  148 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0054]    [0054]FIG. 9 shows a differential with center switch switched capacitor circuit  160  according to the first embodiment of the present invention. In the first embodiment, the differential with center switch switched capacitor circuit  160  includes a positive side capacitor  162 , a negative side capacitor  166 , a center switch element  164  having an NMOS transistor, a positive side primary switch element  168  having an NMOS transistor, a negative side primary switch element  170  having an NMOS transistor, a positive side dummy switch element  172  having an NMOS transistor, a negative side dummy switch element  174  having an NMOS transistor, and a control signal generator  176 .  
         [0055]    The positive side capacitor  162  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  166  is connected between the second oscillator node OSC_N and a node B. The control signal generator  176  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  164  selectively connects node A to node B depending on the first control signal SW 1 . The positive side primary switch element  168  selectively connects node A to ground based on the first control signal SW 1 , and the negative side primary switch element  170  selectively connects node B to ground based on the first control signal SW 1 . The positive side dummy switch element  172  has a first terminal connected to node A, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected. The negative side dummy switch element  174  has a first terminal connected to node B, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected.  
         [0056]    The clock feedthrough at node A has three sources: the clock feedthrough from the center switch element  164 , the clock feedthrough from the positive side primary switch element  168 , and the clock feedthrough from the positive side dummy switch element  172 . Because the center switch element  164  and the positive side primary switch element  168  are controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to these two switch elements  164 ,  168  will be opposite in polarity to the clock feedthrough produced at node A due to the positive side dummy switch element  172 , which is controlled by the second control signal SW 2 . By properly sizing the positive side dummy switch element  172  such that the voltage step caused by the switch element  172  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  164  and  168 , the unwanted voltage step at node A is eliminated.  
         [0057]    Similarly, the clock feedthrough at node B has three sources: the clock feedthrough from the center switch element  164 , the clock feedthrough from the negative side primary switch element  170 , and the clock feedthrough from the negative side dummy switch element  174 . Because the center switch element  164  and the negative side primary switch element  170  are controlled by the first control signal SW 1 , the clock feedthrough produced at node B due to these two switch elements  164 ,  170  will be opposite in polarity to the clock feedthrough produced at node B due to the negative side dummy switch element  174 , which is controlled by the second control signal SW 2 . By properly sizing the negative side dummy switch element  174  such that the voltage step caused by the switch element  174  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  164  and  170 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0058]    [0058]FIG. 10 shows a differential only center switch switched capacitor circuit  190  according to the first embodiment of the present invention. In the first embodiment, the differential only center switch switched capacitor circuit  190  includes a positive side capacitor  192 , a negative side capacitor  196 , a center switch element  194  having an NMOS transistor, a positive side dummy switch element  198  having an NMOS transistor, a negative side dummy switch element  200  having an NMOS transistor, and a control signal generator  202 .  
         [0059]    The positive side capacitor  192  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  196  is connected between the second oscillator node OSC_N and a node B. The control signal generator  202  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  194  selectively connects node A to node B depending on the first control signal SW 1 . The positive side dummy switch element  198  has a first terminal connected to node A, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected. The negative side dummy switch element  200  has a first terminal connected to node B, a control terminal connected to the second control signal SW 2 , and a second terminal left unconnected.  
         [0060]    The clock feedthrough at node A has two sources: the clock feedthrough from the center switch element  194  and the clock feedthrough from the positive side dummy switch element  198 . Because the center switch element  194  is controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to the switch element  194  will be opposite in polarity to the clock feedthrough produced at node A due to the positive side dummy switch element  198 , which is controlled by the second control signal SW 2 . By properly sizing the positive side dummy switch element  198  such that the voltage step caused by the switch element  198  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch element  194 , the unwanted voltage step at node A is eliminated.  
         [0061]    Similarly, the clock feedthrough at node B has two sources: the clock feedthrough from the center switch element  194  and the clock feedthrough from the negative side dummy switch element  200 . Because the center switch element  194  is controlled by the first control signal SW 1 , the clock feedthrough produced at node B due to the switch element  194  will be opposite in polarity to the clock feedthrough produced at node B due to the negative side dummy switch element  200 , which is controlled by the second control signal SW 2 . By properly sizing the negative side dummy switch element  200  such that the voltage step caused by the switch element  200  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch element  194 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0062]    [0062]FIG. 11 shows a single ended switched capacitor circuit  230  according to a second embodiment of the present invention. In the second embodiment, the single ended switched capacitor circuit  230  includes the same components and connections as the single ended switched capacitor circuit  130  shown in FIG. 6; however, the dummy switch element  136  has its first and second terminals both shorted to node A. The operational description and clock feedthrough cancellation are otherwise the same as that described for the first embodiment shown in FIG. 6.  
         [0063]    [0063]FIG. 12 shows a differential without center switch switched capacitor circuit  240  according to the second embodiment of the present invention. In the second embodiment, the differential without center switch switched capacitor circuit  240  includes the same components and connections as the differential without center switch switched capacitor circuit  140  shown in FIG. 8; however, in the second embodiment the positive side dummy switch element  136  has its first and second terminals both shorted to node A. Similarly, the negative side dummy switch element  152  has its first and second terminals both shorted to node B. The operational description and clock feedthrough cancellation are otherwise the same as that described for the first embodiment shown in FIG. 8.  
         [0064]    [0064]FIG. 13 shows a differential with center switch switched capacitor circuit  260  according to the second embodiment of the present invention. In the second embodiment, the differential with center switch switched capacitor circuit  260  includes the same components and connections as the differential with center switch switched capacitor circuit  160  shown in FIG. 9; however, in the second embodiment the positive side dummy switch element  172  has its first and second terminals both shorted to node A. Similarly, the negative side dummy switch element  274  has its first and second terminals both shorted to node B. The operational description and clock feedthrough cancellation are otherwise the same as that described for the first embodiment shown in FIG. 9.  
         [0065]    [0065]FIG. 14 shows a differential only center switch switched capacitor circuit  290  according to the second embodiment of the present invention. In the second embodiment, the differential only center switch switched capacitor circuit  290  includes the same components and connections as the differential only center switch switched capacitor circuit  190  shown in FIG. 10; however, in the second embodiment the positive side dummy switch element  198  has its first and second terminals both shorted to node A. Similarly, the negative side dummy switch element  300  has its first and second terminals both shorted to node B. The operational description and clock feedthrough cancellation are otherwise the same as that described for the first embodiment shown in FIG. 10.  
         [0066]    [0066]FIG. 15 shows a single ended switched capacitor circuit  330  according to a third embodiment of the present invention. In the third embodiment, the singled ended switched capacitor circuit  330  includes the same components and connections as the single ended switched capacitor circuit  130  shown in FIG. 6; however, the dummy switch  136  shown in FIG. 6 is replaced in FIG. 15 with a complementary switch  336  comprising a PMOS transistor having a control terminal connected to the second control signal SW 2 , a first terminal connected to node A, and a second terminal connected to ground. The operational description and clock feedthrough cancellation is otherwise the same as that described for the first embodiment shown in FIG. 6.  
         [0067]    [0067]FIG. 16 shows a first version of a differential without center switch switched capacitor circuit  340   a  according to the third embodiment of the present invention. In the first version of the third embodiment, the differential without center switch switched capacitor circuit  340   a  includes the same components and connections as the differential without center switch switched capacitor circuit  140  shown in FIG. 8; however, in the second embodiment the positive side dummy switch  150  shown in FIG. 8 is replaced in FIG. 16 with a complementary switch  350  including a PMOS transistor having a control terminal connected to the second control signal SW 2 , a first terminal connected to node A, and a second terminal connected to ground. Similarly, the negative side dummy switch element  152  is replaced in FIG. 16 with a dummy switch  352  including a PMOS transistor having a control terminal connected to the second control signal SW 2 , a first terminal connected to node B, and a second terminal connected to ground. The operational description and clock feedthrough cancellation are otherwise the same as that described for the first embodiment shown in FIG. 8.  
         [0068]    [0068]FIG. 17 shows a second version of a differential without center switch switched capacitor circuit  340   b  according to the third embodiment of the present invention. In the second version of the third embodiment, the differential without center switch switched capacitor circuit  340   b  includes a positive side capacitor  142 , a negative side capacitor  144 , a positive side primary switch element  146  having an NMOS transistor, a negative side primary switch element  148  having an NMOS transistor, a center switch element  356  having a PMOS transistor, and a control signal generator  154 .  
         [0069]    The positive side capacitor  142  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  144  is connected between the second oscillator node OSC_N and a node B. The control signal generator  154  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The positive side primary switch element  146  selectively connects node A to ground based on the first control signal SW 1 , and the negative side primary switch element  148  selectively connects node B to ground based on the first control signal SW 1 . The center switch element  356 , selectively connects node A to node B based on the second control signal SW 2 .  
         [0070]    The clock feedthrough at node A has two sources: the clock feedthrough from the positive side primary switch element  146  and the clock feedthrough from the center switch element  356 . Because the positive side primary switch element  146  is controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to the switch element  146  will be opposite in polarity to the clock feedthrough produced at node A due to the center switch element  356 , which is controlled by the second control signal SW 2 . By properly sizing the positive side primary switch element  146  such that the voltage step caused by the switch element  146  is of equal magnitude (but opposite polarity) as the clock feedthrough caused by the center switch element  356 , the unwanted voltage step at node A is eliminated.  
         [0071]    Similarly, the clock feedthrough at node B has two sources: the clock feedthrough from the negative side primary switch element  148  and the clock feedthrough from the center switch element  356 . Because the negative side primary switch element  148  is controlled by the first control signal SW 1 , the clock feedthrough produced at node B due to the switch element  148  will be opposite in polarity to the clock feedthrough produced at node B due to the center switch element  356 , which is controlled by the second control signal SW 2 . By properly sizing the negative side primary switch element  148  such that the voltage step caused by the switch element  148  is of equal magnitude (but opposite polarity) as the clock feedthrough caused by the center switch element  356 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0072]    [0072]FIG. 18 shows a third version of a differential without center switch switched capacitor circuit  340   c  according to the third embodiment of present invention. In the third version of the third embodiment, the differential without center switch switched capacitor circuit  340   c  includes a positive side capacitor  142 , a negative side capacitor  144 , a center switch element  356  having a PMOS transistor, a positive side primary switch element  146  having an NMOS transistor, a negative side primary switch element  148  having an NMOS transistor, a positive side complementary switch element  350  having a PMOS transistor, a negative side complementary switch element  352  having a PMOS transistor, and a control signal generator  154 .  
         [0073]    The positive side capacitor  142  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  144  is connected between the second oscillator node OSC_N and a node B. The control signal generator  154  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  356  selectively connects node A to node B depending on the second control signal SW 2 . The positive side primary switch element  146  selectively connects node A to ground based on the first control signal SW 1 , and the negative side primary switch element  148  selectively connects node B to ground based on the first control signal SW 1 . The positive side complementary switch element  350  selectively connects node A to ground based on the second control signal SW 2  and the negative side complementary switch element  352  selectively connects node B to ground based on the second control signal SW 2 .  
         [0074]    The clock feedthrough at node A has three sources: the clock feedthrough from the center switch element  356 , the clock feedthrough from the positive side primary switch element  146 , and the clock feedthrough from the positive side complementary switch element  350 . Because the center switch element  356  and the positive side complementary switch element  350  are controlled by the second control signal SW 2 , the clock feedthrough produced at node A due to these two switch elements  356 ,  150  will be opposite in polarity to the clock feedthrough produced at node A due to the positive side primary switch element  146 , which is controlled by the first control signal SW 1 . By properly sizing the positive side primary switch element  346   c  such that the voltage step caused by the switch element  146  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  350  and  356 , the unwanted voltage step at node A is eliminated.  
         [0075]    Similarly, the clock feedthrough at node B has three sources: the clock feedthrough from the center switch element  356 , the clock feedthrough from the negative side primary switch element  148 , and the clock feedthrough from the negative side complementary switch element  352 . Because the center switch element  356  and the negative side complementary switch element  352  are controlled by the second control signal SW 2 , the clock feedthrough produced at node B due to these two switch elements  352 ,  356  will be opposite in polarity to the clock feedthrough produced at node B due to the negative side primary switch element  148 , which is controlled by the first control signal SW 1 . By properly sizing the negative side primary switch element  148  such that the voltage step caused by the switch element  148  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  356  and  352 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0076]    [0076]FIG. 19 shows a first version of a differential with center switch switched capacitor circuit  360   a  according to the third embodiment of the present invention. In the first version of the third embodiment, the differential with center switch switched capacitor circuit  360   a  includes the same components and connections as the differential with center switch switched capacitor circuit  160  shown in FIG. 9; however, in the second embodiment the positive side dummy switch element  172  shown in FIG. 9 is replaced in FIG. 19 with a positive side complementary switch  372  having a PMOS transistor that selectively connects node A to ground based on the complement of the second control signal SW 2 . Similarly, the negative side dummy switch element  174  shown in FIG. 9 is replaced in FIG. 19 with a negative side complementary switch  374  comprising a PMOS transistor that selectively connects node B to ground based on the complement of the second control signal SW 2 . The operational description and clock feedthrough cancellation are otherwise exactly the same as that described for the first embodiment shown in FIG. 9.  
         [0077]    [0077]FIG. 20 shows a second version of the differential with center switch switched capacitor circuit  360   b  according to the third embodiment of the present invention. In the second version of the third embodiment, the differential with center switch switched capacitor circuit  360   b  includes a positive side capacitor  162 , a negative side capacitor  166 , a center switch element  164  having an NMOS transistor, a positive side primary switch element  168  having an NMOS transistor, a negative side primary switch element  170  having an NMOS transistor, a complementary center switch element  378  having a PMOS transistor, and a control signal generator  176 .  
         [0078]    The positive side capacitor  162  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  166  is connected between the second oscillator node OSC_N and a node B. The control signal generator  176  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  164  selectively connects node A to node B depending on the first control signal SW 1 . The complementary center switch element  378  selectively connects node A to node B depending on the complement of second control signal SW 2 . The positive side primary switch element  168  selectively connects node A to ground based on the first control signal SW 1 , and the negative side primary switch element  170  selectively connects node B to ground based on the first control signal SW 1 .  
         [0079]    The clock feedthrough at node A has three sources: the clock feedthrough from the center switch element  164 , the clock feedthrough from the positive side primary switch element  168 , and the clock feedthrough from the complementary center switch element  378 . Because the center switch element  164  and the positive side primary switch element  168  are controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to these two switch elements  164 ,  168  will be opposite in polarity to the clock feedthrough produced at node A due to the complementary center switch element  378 , which is controlled by the second control signal SW 2 . By properly sizing the complementary center switch element  378  such that the voltage step caused by the switch element  378  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  164  and  168 , the unwanted voltage step at node A is eliminated.  
         [0080]    Similarly, the clock feedthrough at node B has three sources: the clock feedthrough from the center switch element  164 , the clock feedthrough from the negative side primary switch element  170 , and the clock feedthrough from the complementary center switch element  378 . Because the center switch element  164  and the negative side primary switch element  170  are controlled by the first control signal SW 1 , the clock feedthrough produced at node B due to these two switch elements  164 ,  170  will be opposite in polarity to the clock feedthrough produced at node B due to the complementary center switch element  378 , which is controlled by the second control signal SW 2 . By properly sizing the complementary center switch element  378  such that the voltage step caused by the switch element  378  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  164  and  170 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0081]    [0081]FIG. 21 shows a third version of the differential with center switch switched capacitor circuit  360   c  according to the third embodiment of the present invention. In the third version of the third embodiment, the differential with center switch switched capacitor circuit  360   c  includes a positive side capacitor  162 , a negative side capacitor  166 , a center switch element  164  having an NMOS transistor, a positive side primary switch element  168  having an NMOS transistor, a negative side primary switch element  170  having an NMOS transistor, a positive side complementary switch element  172  having a PMOS transistor, a negative side complementary switch element  174  having a PMOS transistor, a complementary center switch element  378  having a PMOS transistor, and a control signal generator  176 .  
         [0082]    The positive side capacitor  162  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  166  is connected between the second oscillator node OSC_N and a node B. The control signal generator  176  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  164  selectively connects node A to node B depending on the first control signal SW 1 . The positive side primary switch element  168  selectively connects node A to ground based on the first control signal SW 1 , and the negative side primary switch element  170  selectively connects node B to ground based on the first control signal SW 1 . The positive side complementary switch element  372  selectively connects node A to ground based on the complement of the second control signal SW 2 . The negative side complementary switch element  374  selectively connects node B to ground based on the complement of the second control signal SW 2 .  
         [0083]    The clock feedthrough at node A has four sources: the clock feedthrough from the center switch element  164 , the clock feedthrough from the complementary center switch element  378 , the clock feedthrough from the positive side primary switch element  168 , and the clock feedthrough from the positive side complementary switch element  372 . Because the center switch element  164  and the positive side primary switch element  168  are controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to these two switch elements  164 ,  168  will be opposite in polarity to the clock feedthrough produced at node A due to the positive side complementary switch element  372  and the complementary center switch element  378 , which are controlled by the second control signal SW 2 . By properly sizing the positive side complementary switch element  372  and the complementary center switch element  378  such that the voltage step caused by the switch elements  372  and  378  are of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  164  and  168 , the unwanted voltage step at node A is eliminated.  
         [0084]    Similarly, the clock feedthrough at node B has four sources: the clock feedthrough from the center switch element  164 , the clock feedthrough from the complementary center switch element  378 , the clock feedthrough from the negative side primary switch element  170 , and the clock feedthrough from the negative side complementary switch element  374 . Because the center switch element  164  and the negative side primary switch element  170  are controlled by the first control signal SW 1 , the clock feedthrough produced at node B due to these two switch elements  164 ,  170  will be opposite in polarity to the clock feedthrough produced at node B due to the negative side complementary switch element  374  and the complementary center switch element  378 , which are controlled by the second control signal SW 2 . By properly sizing the negative side complementary switch element  374  and the complementary center switch element  378  such that the voltage step caused by the switch elements  374  and  378  are of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  164  and  170 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0085]    [0085]FIG. 22 shows a first version of a differential only center switch switched capacitor circuit  390   a  according to the third embodiment of the present invention. In the first version of the third embodiment, the differential only center switch switched capacitor circuit  390   a  comprises the same components and connections as the differential only center switch switched capacitor circuit  190  shown in FIG. 10; however, in the positive side dummy switch element  198  shown in FIG. 10 has been replaced in FIG. 22 with a positive side complementary switch element  398  including a PMOS transistor that selectively connects node A to ground based on the second control signal SW 2 . Similarly, the negative side dummy switch element  200  shown in FIG. 10 has been replaced in FIG. 22 with a negative side complementary switch element  400  that selectively connects node B to ground based on the second control signal SW 2 . The operational description and clock feedthrough cancellation are otherwise the same as that described for the first embodiment shown in FIG. 10.  
         [0086]    [0086]FIG. 23 shows a second version of the differential only center switch switched capacitor circuit  390   b  according to the third embodiment of the present invention. In the second version of the third embodiment, the differential only center switch switched capacitor circuit  390   b  includes a positive side capacitor  192 , a negative side capacitor  196 , a center switch element  194  having of an NMOS transistor, a complementary center switch element  404  having of a PMOS transistor, and a control signal generator  202 .  
         [0087]    The positive side capacitor  192  is connected between the first oscillator node OSC_P and a node A, and the negative side capacitor  196  is connected between the second oscillator node OSC_N and a node B. The control signal generator  202  provides a first control signal SW 1  a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  194  selectively connects node A to node B based on the first control signal SW 1 . The complementary center switch element  404  selectively connects node A to node B based on the complement of the second control signal SW 2 .  
         [0088]    The clock feedthrough at node A has two sources: the clock feedthrough from the center switch element  194  and the clock feedthrough from the complementary center switch element  404 . Because the center switch element  194  is controlled by the first control signal SW 1 , the clock feedthrough produced at node A due to the switch element  194  will be opposite in polarity to the clock feedthrough produced at node A due to the complementary center switch element  404 , which is controlled by the second control signal SW 2 . By properly sizing the complementary switch element  404  such that the voltage step caused by the switch element  404  is of equal magnitude (but opposite polarity) as the clock feedthrough caused by the center switch element  194 , the unwanted voltage step at node A is eliminated.  
         [0089]    Because the clock feedthrough at node B has the same sources, eliminating the clock feedthrough at node A will automatically eliminate the clock feedthrough at node B. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0090]    [0090]FIG. 24 shows a third version of the differential only center switch switched capacitor circuit  390   c  according to the third embodiment of present invention. In the third version of the third embodiment, the differential only center switch switched capacitor circuit  390   c  includes a positive side capacitor  192 , a negative side capacitor  196 , a center switch element  194  having an NMOS transistor, a positive side complementary switch element  398  having a PMOS transistor, a negative side complementary switch element  400  having a PMOS transistor, a complementary center switch element  404  having a PMOS transistor, and a control signal generator  202 .  
         [0091]    The positive side capacitor  192  is connected between the first oscillator node OSC_P and a node A and the negative side capacitor  196  is connected between the second oscillator node OSC_N and a node B. The control signal generator  202  provides a first control signal SW 1 , and a second control signal SW 2  that is complementary to the first control signal SW 1 . The signal diagram for the first control signal SW 1  and the second control signal SW 2  is the same as that shown in FIG. 7. The center switch element  194  selectively connects node A to node B depending on the first control signal SW 1 . The complementary center switch element  404  selectively connects node A to node B depending on the complement of second control signal SW 2 . The positive side complementary switch element  398  selectively connects node A to ground based on the second control signal SW 2 , and the negative side complementary switch element  400  selectively connects node B to ground based on the second control signal SW 2 .  
         [0092]    The clock feedthrough at node A has three sources: the clock feedthrough from the center switch element  194 , the clock feedthrough from the positive side complementary switch element  398 , and the clock feedthrough from the complementary center switch element  404 . Because the complementary center switch element  404  and the positive side complementary switch element  398  are controlled by the second control signal SW 2 , the clock feedthrough produced at node A due to these two switch elements  404 ,  398  will be opposite in polarity to the clock feedthrough produced at node A due to the center switch element  194 , which is controlled by the first control signal SW 1 . By properly sizing the center switch element  194  such that the voltage step caused by the switch element  194  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  398  and  404 , the unwanted voltage step at node A is eliminated.  
         [0093]    Similarly, the clock feedthrough at node B has three sources: the clock feedthrough from the center switch element  194 , the clock feedthrough from the negative side complementary switch element  400 , and the clock feedthrough from the complementary center switch element  404 . Because the complementary center switch element  404  and the negative side complementary switch element  400  are controlled by the second control signal SW 2 , the clock feedthrough produced at node B due to these two switch elements  404 ,  400  will be opposite in polarity with the clock feedthrough produced at node B due to the center switch element  194 , which is controlled by the first control signal SW 1 . By properly sizing the center switch element  194  such that the voltage step caused by the switch element  194  is of equal magnitude (but opposite polarity) as the combined clock feedthrough caused by the switch elements  404  and  400 , the unwanted voltage step at node B is eliminated. Because the clock feedthrough at node A and node B is eliminated, so is the unwanted momentary capacitance change and associated frequency shift and drift in the VCO  10 .  
         [0094]    In contrast to the prior art, the present invention uses either a complementary controlled dummy switch element or a complementary controlled complementary switch element to eliminate the clock feedthrough when switching off the switched capacitor circuit so that there is a much smaller unwanted momentary capacitance change and associated frequency shift and drift of the VCO. When switching off, the prior art implementations suffer from clock feedthrough that causes a voltage step to occur at a capacitance node of the VCO  10 . The voltage step change causes the floating parasitic junction diode formed by a switch element in the off state to be slightly forward biased until the dropped voltage returns to the ground potential. According to the present invention, the voltage step at the internal capacitance node is eliminated by the additional switches that have complementary control signals. When switching off, the present invention does not have a momentary change in the capacitance value or a momentary shift and drift in the VCO  10  frequency.  
         [0095]    Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, that above disclosure should be construed as limited only by the metes and bounds of the appended claims.