Abstract:
A method for reducing critical dimension is provided. An exposure process and a develop process are performed on a photoresist layer. An optical trim exposure process is performed between the exposure process and the development process or before the exposure process. The optical trim expsoure process is performed to expose the photoresit layer by using a fully open mask of which the transmission rate is greater than zero. Because of the performance of the optical trim exposure process, the critical dimension of the photoresist layer can be reduced without substantially changing the characteristics of the photoresist layer.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to semiconductor process. More particularly, the present invention relates to a method for reducing the critical dimension (CD).  
         [0003]     2. Description of Related Art  
         [0004]     To satisfy the constant demand for a higher integration of devices, the dimension of the entire circuit device is continually being reduced in each successive technology generation. However, a further scaling-down of a device&#39;s dimension is constrained by the existing photolithographic techniques.  
         [0005]     Limited by the yellow light process, the photolithographic process can not be improved to achieve a smaller critical dimension. Therefore, the industry has developed a photoresist trimming process, which includes a chemical trim process and a plasma trim process.  
         [0006]     The chemical trim process is achieved by submerging the patterned photoresist layer and the entire wafer thereunder in a basic or a neutral chemical solution. A portion of the photoresist layer is removed and the critical dimension is thereby reduced. However, the exact reduction of the critical dimension is difficult to control by this type process, and an over-trimming is easily occurred. In fact, the photoresist layer can be entirely removed. To prevent such a scenario from happening, the shrinkage volume must be carefully controlled. In other words, the reduction of the critical dimension can also be better controlled. Moreover, after the treatment with the chemical solution, the property of the sidewall of the photoresist changes, which in turns affects the etching resistance of the photoresist. In order to ensure the accuracy of the photolithography process, the photoresist layer is first being examined with a scanning electron microscope (SEM) or a similar type of apparatus before proceeding to the next process. However, the etching resistance of the sidewall of the photoresist layer is again affected after being subjected to the scanning with a SEM.  
         [0007]     In a plasma trim process, the wafer is exposed to an appropriate plasma etchant. Using ion bombardment, the photoresist layer on the wafer surface is trimmed to reduce the critical dimension. However, due to the nature of the plasma trim process, the trimming of a line-end is not desirable. A predetermined length of the line can not be maintained. Further, to prevent the entire line from being trimmed, the shrinkage volume must also be limited. Additionally, the longer the trimming process, the lower the yield of the lithographic process. Since the properties of the exposed photoresist layer may change after being bombarded by ions, the rework process cannot be continued. Consequently, more time is consumed and a high cost is resulted for re-depositing a photoresist layer.  
       SUMMARY OF THE INVENTION  
       [0008]     At least one object of the present invention is to provide a method for reducing the critical dimension, wherein the conventional chemical trim process and the plasma trim process can be replaced such that the cycle time for reducing critical dimension is reduced and the process is simplified.  
         [0009]     The present invention also provides a method for reducing the critical dimension, wherein alterations of the property of the photoresist layer due to the trimming process is prevented to facilitate the subsequent process.  
         [0010]     The present invention provides a method for reducing the critical dimension, which includes performing an exposure process and a development process on a photoresist layer, wherein an optical trim exposure process (OTP) is conducted between the exposure process and the development process. The optical trim exposure process includes performing an exposure on the photoresist layer using a fully open mask, wherein the transmission rate of a fully open mask is greater than 0.  
         [0011]     According to one embodiment of the present invention, the fully open mask includes an alternating phase shift mask (alt-PSM) or a half-tone mask.  
         [0012]     According to one embodiment of the invention, between the optical trim exposure process and the development process, a post exposure baking process is performed.  
         [0013]     The present invention provides another method for reducing the critical dimension, in which an exposure process and a development process are performed on the photoresist layer, wherein an optical trim exposure process is performed before the standard exposure process, and the optical trim exposure process is conducted using a fully open mask having a transmission rate greater than 0.  
         [0014]     According to one embodiment of the present invention, the fully open mask includes an alternating phase shift mask (alt-PSM) or a half-tone mask.  
         [0015]     According to one embodiment of the invention, between the optical trim exposure process and the development process, a post exposure baking process is performed.  
         [0016]     According to one embodiment of the present invention for reducing the critical dimension, the critical dimension of the photoresist layer can be reduced to within a range of about 4 nm to 100 nm.  
         [0017]     The optical trim exposure process of the present invention can replace the conventional chemical trim process or the plasma trim process to reduce the cycle time and to simply the process. Further, the present invention is not limited by shrinkage volume, and the critical dimension can be accurately reduced. Further, any alteration to the properties of the photoresist layer due to the trimming process can be obviated and the subsequent process can be facilitated.  
         [0018]     The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0020]      FIG. 1  is a flow chart of a fabrication process for reducing the critical dimension according to one embodiment of the invention.  
         [0021]      FIG. 2A  to  2 D are schematic, cross sectional views showing the steps of a method for reducing the critical dimension according to one embodiment of the invention.  
         [0022]      FIG. 3  is a flow chart of a fabrication process for reducing the critical dimension according to another embodiment of the invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]      FIG. 1  is a flow chart of a fabrication process for reducing the critical dimension according to one embodiment of the invention.  FIG. 2A  to  2 D are schematic, cross sectional views showing the steps of a method for reducing the critical dimension according to one embodiment of the invention.  
         [0024]     Referring to both  FIGS. 1 and 2 A, a wafer  200  (step  101 ) is provided. The wafer  200  is already formed with, for examples, transistors, memory or other semiconductor devices thereon or the wafer  200  does not have any devices formed thereon. The surface of the wafer  200  can include a dielectric layer, a conductive layer, a protective layer or any film layer that requires an etching process or a doping process, etc. A photoresist layer  201  (step  103 ) is then coated on the wafer  200 , wherein the coating method includes, but not limited to, spin coating. The photoresist layer  201  is, for example, a positive photoresist.  
         [0025]     Thereafter, as shown in  FIG. 2B , using a photomask  203 , an exposure process (step  105 ) is performed on the photoresist layer  201  to form a photoresist layer  201  a with a latent image. Since after an exposure process and before a development process, the changes on the photoresist layer  201  cannot be visually observed. A photoresist layer  201 , after it is being exposed but before being developed, is known as a photoresist layer  201  a with a latent image. The exposure light source  204  used in the exposure process includes, for example, krypton fluoride laser, argon fluoride or other types of deep ultraviolet light source.  
         [0026]     Continuing to  FIG. 2C , after the exposure process, an optic trim exposure process (step  107 ) is performed, wherein the optical trim exposure process employs a fully open mask  205 . A fully open mask  205  refers to a mask with no pattern thereon and the transmission rate of a fully open mask  205  is greater than 0. The fully open mask  205  includes an alternate phase shift mask or a halftone mask.  
         [0027]     In one embodiment, after the optical trim exposure process, a post exposure baking process (step  109 ) is performed. The post exposure baking process includes baking with a hot plate at about 110° C. to about 130° C. for about 10 seconds to 2 minutes.  
         [0028]     Referring to  FIG. 2D , a development process (step  111 ) is conducted to develop the latent image of the photoresist layer  201   b  to form a patterned photoresist layer  201   c.  The critical dimension of the patterned photoresist layer  201   c  is about 4 nm to about 100 nm.  
         [0029]     Also, the aforementioned optical trim exposure process can also be executed before the exposure process as shown in  FIG. 3 .  FIG. 3  is a flow chart of a fabrication process for reducing the critical dimension according to another embodiment of the invention.  
         [0030]     Referring to  FIG. 3 , a wafer (step  301 ) is provided. The wafer  200  is already formed with, for examples, transistors, memory or other semiconductor devices thereon or the wafer  200  not yet has any devices formed thereon. The surface of the wafer  200  can include a dielectric layer, a conductive layer, a protective layer or any film layer that requires an etching process or a doping process, etc. A photoresist layer  201  (step  103 ) is then coated on the wafer  200 , wherein the coating method includes, but not limited to, spin coating. The photoresist layer  201  is, for example, a positive photoresist.  
         [0031]     Thereafter, an optic trim exposure process (step  305 ) is performed to obtain a photoresist layer with a latent image, wherein the optical trim exposure process employs a fully open mask  205 ,and the transmission rate of the fully open mask  205  is greater than 0. The fully open mask  205  includes an alternate phase shift mask or a halftone mask, for example.  
         [0032]     After the optical trim exposure process, an exposure process (step  307 ) is performed on the photoresist layer using a photomask to obtain another photoresist layer with a latent image. The exposure light source  204  used in the exposure process includes, for example, krypton fluoride laser, argon fluoride or other deep ultraviolet light source.  
         [0033]     In one embodiment of the invention, after the exposure process, a post-exposure baking process (step  309 ) is performed. This post-exposure baking process includes baking with a hot plate at about 110° C. to about 130° C. for about 10 seconds to 2 minutes.  
         [0034]     Thereafter, a development process (step  311 ) is performed to develop the latent image of the photoresist layer to form a patterned photoresist layer. After the completion of step  311  as shown in  FIG. 2D , the critical dimension of the patterned photoresist layer is about 4 nm to about 100 nm, wherein the development process is accomplished by an acid-base neutralizing reaction.  
         [0035]     Accordingly, the present invention employs an optical trim exposure process to replace the conventional chemical trim or plasma trim process in order to be more time effective and to simplify the process.  
         [0036]     Moreover, in accordance of the present invention, the problems of negatively impacting the properties of photoresist layer as in other trimming processes can be obviated to facilitate the photoresist rework process. The etch resistance of the photoresist sidewall is also retained to ensure an accurate transferring of the patterns.  
         [0037]     The foregoing description of the preferred embodiment of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.