Abstract:
A method and a circuit may have an ability to provide constant currents of a certain set value, the rising and falling edges of which may be shorter than the design minimum on-phase. Essentially, these results may be obtained by keeping an operational amplifier that controls the output power switch in an active state during off-phases of an impulsive drive signal received by the current source circuit in order to maintain the output voltage of the operational amplifier at or just below the voltage to be applied to the control terminal of the output power switch during a successive on-phase of a received drive pulse signal.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates in general to fast switching current sources for driving electrical loads, and in particular, to fast switching current sources adapted to drive electrical loads without generating current spikes or significant overshoots. 
       BACKGROUND OF THE INVENTION 
       [0002]    There are many applications that use fast switching, overshoot free current sources, especially though not exclusively in communications and digital data transmission systems, full motion color display video applications, opto-isolators drivers, infrared light emitting diode (LED) communication devices operating at high data rate, general purpose LED drivers in devices with or without serial interface, and in display devices where the light intensity is current dependent. In view a prominent importance among the numerous applications of fast switching, overshoot free current sources, the ensuing description may exemplarily refer to the driving of an electrical load in the form of an LED, though other equivalent electrical loads may be similarly driven. 
         [0003]      FIG. 1  shows a basic LED driver circuit suitable for monolithic multi-channel drivers for LED panel displays, a partial block diagram of which is shown in  FIG. 2 . Light output is a function of current I OUT ; by changing I BIAS , which has a ratio K with I OUT , it is possible to modulate the intensity level. The “reference” and the “sensing” (feedback) resistors may be of the same-type and well-matched. 
         [0004]    In an integrated circuit (IC), the biasing current I BIAS  is usually the result of a processing/amplification (e.g.: 1:1) of an input current, generated by the user on an external resistor, coupled to a suitable pad and biased by a temperature and supply compensated voltage reference (typically a Band Gap reference). The output current is thus temperature and supply independent and a DMOS, if technologically available, is often employed as a power output element. 
         [0005]    The MOS M GSW  ( FIG. 1 ) acts as a switch and grounds the gate of the power element, thereby preventing it from remaining floating when the driver is disabled (ENABLE=0). In these conditions the op-amp has its input and output terminals to zero voltage. 
         [0006]    When the driver is enabled (ENABLE=1), supposing the positive input rises instantaneously, the op-amp has to raise its output (i.e. the gate of the power) from zero to at least the threshold voltage of the DMOS (in a worst scenario, up several hundreds mV, when operating at the internal supply voltage value). The op-amp negative input may be increased (usually from few tenths of mV to several hundreds mV) to the appropriate value: V SENS =V REF , for setting the output current to the design value. 
         [0007]    Passing from one situation to another, not in “small signal” conditions, the dynamic response of the system is basically conditioned by the slew-rate of the op-amp. Slew rate (SR) is related to the dominant pole of the open loop amplifier and to the charging current of the gate capacitance (including the Miller capacitance). The most general kind of operational amplifier is depicted in  FIG. 3  and by definition: 
         [0000]    
       
         
           
             
               SR 
               = 
               
                 
                   
                     [ 
                     
                       
                          
                         Vo 
                       
                       
                          
                         t 
                       
                     
                     ] 
                   
                   max 
                 
                 = 
                 
                   
                     I 
                     
                       O 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   
                     C 
                     C 
                   
                 
               
             
             , 
             and 
           
         
       
     
         [0000]    C C  is the capacitance needed to introduce a dominant pole to compensate the op-amp. Remembering that 
         [0000]    
       
         
           
             
               
                 f 
                 T 
               
               = 
               
                 
                   gm 
                    
                   
                       
                   
                    
                   1 
                 
                 
                   2 
                    
                   
                     πC 
                     C 
                   
                 
               
             
             , 
             
                 
             
              
             and 
           
         
       
       
         
           
             
               SR 
               = 
               
                 
                   
                     I 
                     
                       O 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   
                     gm 
                      
                     
                         
                     
                      
                     1 
                   
                 
                  
                 2 
                  
                 π 
                  
                 
                     
                 
                  
                 
                   f 
                   T 
                 
               
             
             ; 
           
         
       
     
         [0000]    slew rate can be increased by increasing the transition frequency f T  value and/or the saturation current of the first stage or by decreasing the g m1  of the same stage. 
         [0008]    Many drivers may be able to switch high currents (for example, 80 mA, 100 mA, 500 mA) and this usually calls for the use of large output transistors (Power-DMOS) that have large feedback parasitic capacitance (C GD ), which in turn appears multiplied by the gain of the output stage (gm*R L ) of the driver and increases with diminishing drain voltage, affecting the dynamic performances of the circuit. 
         [0009]    In LED panel displays applications, the LED brightness is usually controlled by adjusting the output constant current, set by mean of an external resistor; moreover “dimming” is often used and comprises switching ON/OFF the current at high rate (a switching frequency of few MHz may be used). If a 5 MHz dimming is implemented (with a 50% duty-cycle), the driver is used to have a rise time much shorter then the 100 ns half period. 
         [0010]    An output setup time, for example, less then 20 ns, may be needed at least to improve the performance of the system. If the simple architecture of  FIG. 1  is used, very high performance in terms of GBW and slew rate would be demanded of the Op-Amp in order to meet with the specifications. 
         [0011]    High slew-rate and bandwidth provides for high bias currents, a relatively complex design for the Op-Amp, high large power consumption and high silicon area consumption, especially in multi-channel devices (to be noted that 16 channels are very frequently used). It is also known to resort to additional support circuitry to improve the speed of the driver. 
         [0012]    As known, “one-shot” circuit may be used, as depicted in  FIG. 4 , for providing a suitable amount of current in a pulsed way; this may help in charging the gate of the power DMOS in a very short time. There remain several potential drawbacks and limitations in these known techniques for fast switching current driving of loads such as a LED: 1) The switching performance of known circuits are strongly dependent on: the output current level; the electrical characteristics of the load LED (i.e. its equivalent RC circuit); the size of the output power element (dictated by current capability specifications); and the bandwidth and slew rate characteristics of the Op-Amp. 2) Under the same output current (IOUT) conditions, if the circuit may drive LEDs of many different characteristics, a large spectrum of resistive loads may be considered in the equivalent circuit: by dimensioning the system to match the rise time specifications for the higher values of load resistance (worst case), it may exhibit unacceptable current spikes at lower load resistance values; and because of Miller&#39;s multiplication effect, the gate capacitance increases with the load resistance, moreover the C GD  increases with the consequent lower drain voltage. 
         [0013]    3) Under identical resistive load conditions, speed performance is greatly dependent on the output current level to be set. Because of the different levels of gate voltages that are requested at different currents, there may be a risk of not matching all the specifications because if the device may provide for a wide range of currents to be set, it is not simple to match the speed requirement at, for example, 80 mA and the current spikes constraint at 3 mA (as a matter of fact, the one-shot current could be “too low” in the first case and “too high” in the second one). The circuit would need additional circuitry to modulate and control the “energy” of the “one-shot” circuit on the basis of the set level of the output current. 
         [0014]    4) Under same resistive load and output current conditions, the rise time is dependent on the external supply voltage VLED. In fact, as it is well known, the parasitic capacitance C GD  is inversely proportional to the V DS  voltage value. For this reason, even if the charge current (energy) is modulated in dependence of the output current, the overshoot in the output current increases with VLED. 
         [0015]    The problem with the “one-shot” technique may be the difficulty to control the gate charging process in all load and I OUT −VLED conditions. Often the gate voltage and hence the output current exhibit high spikes that can reach 50% or even more of the final value of the set output current. On the other hand, expedients to reduce the spike (the quantity of current charging the gate and/or the duration of the pulse) may slow-down the device, risking not meeting the speed requirements. A difficult trade off is generally sought between speed and current spike issues. 
         [0016]    In U.S. Patent Application Publication No. 2008/0012507 to Nalbant, a variety of techniques for fast switching through high brightness and high current LEDs using current shunting devices are disclosed. The disclosed techniques may be burdensome to implement in multi-channel devices, e.g. 16 channels, because of large silicon area and power consumption in view of the fact that the shunting device may be sized to divert the full load current. 
         [0017]    U.S. Pat. No. 6,346,711 to Bray describes a technique to improve the response time that makes use of additional current feed components to the LED during its illumination phase. The additional large size switches and related control circuitry (all switches may carry the maximum design current) increase, significantly the silicon area and power consumption. 
         [0018]    U.S. Pat. No. 6,144,222 to Ho discloses a high speed programmable current driver used for infrared LED communication devices. Large area critical precision requirements in a multi channel device may be burdensome. U.S. Pat. No. 6,469,405 to Moya et al. discloses a technique to reduce overshoot issues. Also this technique uses additional switches in the output current path, which may be suitably sized for the maximum design current at minimum voltage drop condition. 
         [0019]    U.S. Pat. No. 6,734,875 to Tokimoto et al. and U.S. Pat. No. 6,288,696 to Holloman are other publications dealing with LED displays. In the latter, a technique is disclosed to control the current driving by an analog voltage set by an analog drive line including a sample and hold circuit. Drivers designed, for example, for full color full motion video applications, often use internal pulse width modulation (PWM) controls, which give the capability to increase the visual refresh rate and to reduce flickering effects, thereby improving fidelity. 
         [0020]    This, together with the need to suitably modulate the brightness of the LEDs, could make the driver output capable of being switched ON/OFF at high rates (according to this technique, the “ON” period can be scrambled into several short “ON” periods). Indeed, pulse widths as short as 30 ns could be requested and the driver circuit may be fast enough to set the current at a stable level within such pulses of extremely short width. 
         [0021]    In any case, it is always of paramount importance to reduce as much as possible and ideally prevent any switching spike produced by fast switching circuits such as drive current source circuits. This avoids damage to a driven load as a LED, power dissipation (specially in case of a multi-channel device simultaneously switching array LEDs) and EMI issues. Moreover, for securely dealing with very short pulses, it is important to control intensity and duration of the spike, in order to avoid appreciably varying the mean value of the current (e.g. the brightness within the illumination phase of a driven LED). 
       SUMMARY OF THE INVENTION 
       [0022]    There is a need for an effective, less burdensome and efficient way of providing short rise time spike-free output currents. 
         [0023]    An approach is a method and a circuit, a characteristic of which may be an ability to provide constant currents of a certain set value, the rising and falling edges of, which are much shorter then the design minimum on-phase. Essentially, these results may be obtained by keeping an operational amplifier that controls the output power switch, in an active state during off phases of an impulsive drive signal received by the current source circuit, in order to maintain the output voltage of the operational amplifier at or just below the voltage to be applied to the control terminal of the output power switch during a successive on phase of a received drive pulse signal. 
         [0024]    According to an embodiment, the current source circuit may receive drive pulses for an electrical load to be driven and may have a replica branch between a power supply node of the circuit and ground that includes scaled replicas of the output power switch and of the current sensing resistor that are connected in series to the load, for providing an inner scaled replica feedback loop nested to an outer or power feedback loop of a common operational amplifier (op-amp) that outputs the drive voltage level of the gate of the output power switch. 
         [0025]    During, off phases alternated to the drive pulses, the op-amp may be maintained in its active zone for keeping the gate of the scaled replica of the output power switch at the correct drive voltage while a grounding switch, connected to the gate of the output power switch, turns it off. A low impedance node may be “imposed” at the gate of the scaled replica switch of the inner replica feedback loop, which may make the gate node less sensitive to transients and reduce output current overshoots. 
         [0026]    Besides the results in terms of an almost complete elimination of overshoots under a broad range of current driving conditions, scalability of the components of the added replica branch for implementing an inner feedback loop may be possible. The three control switches and the inverter used for switching between an ON-phase configuration and an OFF-phase configuration of the circuit may be of small size, implying a relatively small area consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]      FIG. 1  shows a basic LED driver circuit, according to the prior art. 
           [0028]      FIG. 2  is a block diagram of a 16 channel LED display driver, according to the prior art. 
           [0029]      FIG. 3  shows a general scheme of an operational amplifier, according to the prior art. 
           [0030]      FIG. 4  shows a modified LED driving circuit for speed enhancement, according to the prior art. 
           [0031]      FIG. 5   a  is a basic functional diagram of the fast switching overshoot free current source circuit, according to the present invention. 
           [0032]      FIG. 5   b  shows an ideal Thevenin&#39;s equivalent circuit of the diagram of  FIG. 5   a.    
           [0033]      FIG. 6  is a basic circuit diagram of an embodiment of a current source in the form of a LED driver circuit, according to the present invention. 
           [0034]      FIG. 7  shows the configuration of the circuit of  FIG. 6  during off phases of a driven LED. 
           [0035]      FIG. 8  shows the configuration of the circuit of  FIG. 6  during on phases of the driven LED. 
           [0036]      FIG. 9  and  FIG. 10  show two alternative output stages for the operational amplifier, respectively, according to the present invention. 
           [0037]      FIG. 11  is a simplified equivalent circuit of the current source circuit of  FIG. 6 . 
           [0038]      FIG. 12  shows further reductions to equivalent circuits, according to the present invention. 
           [0039]      FIG. 13  is a diagram showing the gate, voltage variation characteristics for different resistive loads, according to the present invention. 
           [0040]      FIG. 14  shows enlarged parts of characteristics, just beyond the starting edge of the gate voltage variation, according to the present invention. 
           [0041]      FIG. 15  includes diagrams showing the change of load current and of gate voltage raising rate in dependence of the resistive load value, according to the present invention. 
           [0042]      FIG. 16  and  FIG. 17  are simulation waveforms describing the relationship between the replica-branch and the power-branch gate node voltages, at the transitions instant, at different values of load resistors, according to the present invention. 
           [0043]      FIGS. 18 ,  19  and  20  are simulation waveforms for different operation parameters/conditions of the current source circuit, according to the present invention. 
           [0044]      FIG. 21  includes simulation waveforms under critical conditions of current spikes generation, according to the present invention. 
           [0045]      FIG. 22  and  FIG. 23  describe the effect of the size of the scaled replica switch on the output current rise time, according to the present invention. 
       
    
    
       [0046]    The exemplary and non-limiting drawings discussed below and the various embodiments used to describe the principles of the present invention in this document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art may understand that the principles of the present invention may be implemented in current source circuit designed for other applications. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0047]    With reference to the diagram of  FIG. 5   a  that represents the principle of functioning of the current source circuit of this disclosure, the inner replica feedback loop includes an n time scaled down replica of the power switch (e.g. a DMOS of size W/n, where W is the size of the output power DMOS) and a sensing resistor of n time greater resistance (e.g. of resistance n*R 0  where R 0  is the resistance of the sensing resistor of the main or reference feedback loop). At the gate of the output power element, the ideal (Thevenin equivalent) situation is represented by the equivalent circuit of  FIG. 5   b.    
         [0048]    As may be immediately recognized by observing the circuits of  FIGS. 5   a  and  5   b : speed depends by the speed with which the control switches couple either the replica feedback loop (briefly designated with an added “M” notation, short for “mirror”) or the main reference feedback loop to the dedicated input of the op-amp; this dramatically shortens rise time and allows a good control of the “energy” that charges the gate of the output power switch at turning ON instants. 
         [0049]    In practice, as shown in  FIGS. 5   a  and  5   b , this invention provides for a substantially ideal voltage generator of practically null output impedance for biasing the gate of the output power device of a current drive circuit. The null impedance output node of the biasing voltage source renders this node insensitive to ringings. 
         [0050]    By way of example, a basic circuit diagram of an embodiment of a current source of this invention in the form of a LED driver is depicted in  FIG. 6 . The indicated LED load may be a single LED or a plurality of LEDs in series. In the present context, when referring to and illustrating a driven LED or the LED load of the current source circuit, it is intended either a single LED or a plurality of LEDs in series (a chain of LEDs) or any other electrical load to be driven of equivalent or similar electrical characteristics. The relevant electrical parameters remain in any case as the load resistance and the load capacitance as seen at the output node of the current source circuit of this invention. 
         [0051]    When the ENABLE signal, which represents the drive pulse signal that is input to the driver circuit, is LOW (zero output current during an OFF phase of current driving), the scaled replica DMOS of W/n size is in an active inner feedback replica loop configuration, depicted in  FIG. 7 , determined by the opening of the control switches sw 1  and sw 2  and the closing of sw 3 . 
         [0052]    The gate switch MGSW may be ON, forcing OFF the output power DMOS (no current flows through the driven LED) and the inner feedback replica loop is active. By considering the sizes of the devices that comprise the replica loop and the relationship among the signals of the circuit of  FIG. 6 , the inner feedback replica loop biases the scaled down replica DMOS at a current 
         [0000]        I   M   =I bias*( k/n )= I out/ n,    
         [0000]    and its gate is biased at a voltage level Vgate M  of value exactly equal to the one Vgate requested for the output power DMOS to sink the desired current from the LED load when the circuit configuration switches to that of  FIG. 8 , determined by the closing of the control switches sw 1  and sw 2  and the opening of sw 3 , upon a transition to HIGH of the ENABLE signal (for driving the desired output current through the LED). 
         [0053]    This accomplishes a kind of modulation of the “energy” that may charge the gate of the output power DMOS in function of the set output current level. Moreover, the op-amp is kept active also during OFF phases. 
         [0054]    As depicted in  FIG. 8 , when the ENABLE signal is HIGH, the gate switch MGSW may be OFF. The replica feedback loop is interrupted and the main feedback loop that includes the output branch of the output power DMOS and sensing resistor R 0  may close, biasing the source of the DMOS at V REF  and its gate at Vgate that forces an output current through the LED of value: 
         [0000]        I out/ Ro )= V   REF   /Ro.    
         [0000]    Preferably, during ON phases, the replica feedback loop is interrupted, for example, as shown in  FIG. 8 , by an additional switch sw 4  connected in series with the other components of the branch. Although the current flowing in the branch is very small, interrupting it avoids any undue current consumption in the particular case that the ENABLE be high (driver ON) and the output branch accidentally be an open circuit (for example, because the LED is damaged or an incorrect procedure has occurred in the application). Of course, any other suitable output power device, different from the DMOS of the exemplary embodiments of  FIGS. 6 ,  7  and  8 , can be used. 
         [0055]    Dynamic Characteristics of the Current Source Circuit 
         [0056]    By virtue of the fact that the op-amp is kept in its active zone, it does not need to rely on particularly enhanced slew rate characteristics when an ON phase starts. Speed is limited solely by the finite ON resistance of the circuit configuring control switches and by parasitic capacitances. Therefore, even an op-amp of modest gain-bandwidth characteristics can be satisfactorily used with consequent design bonuses in terms of reduced complexity and reduced area and power consumption. 
         [0057]    Advantageously, this makes the gate-source charging less dependent from the set output current level. In fact, if the op-amp had to rely on its slew rate characteristics to rise the gate voltage as in prior art circuits, the rise time would increase with the output current value, because a proportionately higher Vgate value would be requested. 
         [0058]    When the output power device is disabled (ENABLE=0), the scaled replica device is biased at a current given by: 
         [0000]        I   M   =I bias*( k/n )= I out/ n,    
         [0000]    and its gate is biased at a voltage level whose value corresponds exactly to the one requested for the output power to provide for the output current. This effectively responds to the need of modulating the gate charging “energy” on account of the set output current level. 
         [0059]    The use of an emitter follower ( FIG. 9 ) or a source follower ( FIG. 10 ) as output stage of the op-amp that drives the gate of the scaled replica device as well as of the output power device, or of any other equivalent low impedance output stage, for example, a class AB stage, should make the gate node a low impedance node (the impedance seen is 1/gm). Therefore, this critical node is not so sensitive to transitions, and the generation of current spikes is effectively reduced. 
         [0060]    This arrangement, besides providing for transient current charging of the gate node, because of the control of the biasing (the energy with which the charging process is done) carried out by the replica feedback loop during OFF phases, may be thought of as a kind of “well controlled” one-shot circuit. 
         [0061]    From the above considerations, it comes out that the circuit architecture attenuates the otherwise critical dependence of current rise time from the parameters of the equivalent RC circuit. By dimensioning the circuit to meet the specifications at the highest design value of a load resistor, much improved performances are obtained when selecting lower resistance values, without generating significant current spikes. Thus, under the same load resistance and output current conditions, by increasing the load supply voltage value V LED , dynamic performances can be enhanced without causing significant current spikes. 
         [0062]    A LED driver made according to this invention can be switched ON/OFF at remarkably high rates. Under certain conditions, rise times below 10 ns are achievable (suitable for implementing a high frequency PWM control and high speed data transmission). Under the same conditions of output current level and electrical characteristics of the LED load, it is possible to change/adjust the current rise time by acting on the size of the scaled replica DMOS (and also of the replica sensing resistor). For example, by increasing the size of the scaled replica DMOS, with respect to the reference design value Win (reference parameter) while keeping unchanged the current I M  flowing in the replica branch, the driver may be slowed, as may be described in more detail later. 
         [0063]    The ratio n between the currents in the output branch and in the replica branch may be chosen on the basis of power consumption considerations and/or of area occupancy constraints (a scaled replica DMOS can be of a small fractional area of the area of the output power DMOS). The architecture is particularly suited for integrated multi-channel systems and large volume productions. 
         [0064]    An Effective Quantitative Design Approach 
         [0065]    The behavior of a fast switching, overshoot-free current source circuit of this disclosure (e.g. the circuit of  FIG. 6 ) can be assessed by referring to the simplified equivalent circuit depicted in  FIG. 11 . Vsource and the resistor 1/gm represent a model operation (i.e. Thevenin&#39;s equivalent circuit) of the emitter/source follower in the inner replica feedback loop. 
         [0066]    The resistor R 0  serves as a negative feedback device, setting and limiting the output current. The load LED is notably modeled by an equivalent RC parallel. The circuit of  FIG. 11  effectively models the circuit of  FIG. 6 , Vsource being a perfect (ideal) zero impedance output node. At the gate of the output power DMOS, the equivalent circuit can be further reduced, as indicated in  FIG. 12 , to a simple RC circuit. Practically, CgateM is the overall capacitance of the gate node of the scaled replica DMOS (including the parasitic capacitances of the circuit configuring control switches), which can be neglected if compared to capacitance of gate node of the output power DMOS, for a significantly large scaling factor. 
         [0067]    The rise time of the gate voltage vgate, of the output power DMOS, can be approximated to: 
         [0000]    
       
         
           
             
               
                 t 
                 RISE 
               
                
               
                 ( 
                 gate 
                 ) 
               
             
             ≈ 
             
               2.2 
               * 
               
                 τ 
                 gate 
               
             
           
         
       
       
         
           where 
         
       
       
         
           
             
               
                 τ 
                 gate 
               
               = 
               
                 
                   ( 
                   
                     
                       1 
                       gm 
                     
                     + 
                     
                       R 
                       SW 
                     
                   
                   ) 
                 
                 * 
                 
                   C 
                   gate 
                 
               
             
             , 
           
         
       
     
         [0000]    and R SW  is the ON resistance of the MOS control switch SW 1  (which thus may be suitably dimensioned). The rise time of both the gate node voltage and the output current is strictly dependent (increasing with) from the value of the load resistance R L  in relation to the parasitic capacitance of the output power DMOS, in particular C GD , and hence on its size. 
         [0068]      FIGS. 13-14  show the gate voltage and the load current waveforms of the circuit of  FIG. 11 , without considering the effect of the load capacitance C L , after the instant (t0-100 ns) in which SW 1  is closed and SW 2  is opened. A 20V DMOS (0.35 um technology) has been used, with V LED =4.5V, R L  varying from 5 Ohm to 150 Ohm, (C L =10 pF). The DMOS size was W=4800 um, and the output current was 20 mA. 
         [0069]    As observed from  FIG. 13  and  FIG. 14 , until the output power DMOS is not significantly conducting (vgate about 0.8V), the rising edge of the gate is practically independent from the value of R L . Beyond this point, the C GD  of the output power device senses the effect of the increasing current and hence of the decreasing of the drain voltage with R L . If it may be possible in first approximation to use the MOS active zone equations, this would be as if the C GD  would experience a Miller&#39;s multiplication effect and an effective gate capacitance increase (basically C GD  increases because of a decreasing of the drain voltage with R D ). 
         [0070]    Two different time constants are involved in the rising of the gate voltage, by approximation and considering only the Miller&#39;s effect: 
         [0000]    
       
         
           
             
               
                 
                   
                     τ 
                      
                     
                         
                     
                      
                     
                       1 
                       gate 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           1 
                           gm 
                         
                         + 
                         
                           R 
                           SW 
                         
                       
                       ) 
                     
                     * 
                     C 
                      
                     
                         
                     
                      
                     
                       1 
                       gate 
                     
                   
                 
               
             
             
               
                 
                   
                     = 
                     
                       
                         ( 
                         
                           
                             1 
                             gm 
                           
                           + 
                           
                             R 
                             SW 
                           
                         
                         ) 
                       
                       * 
                       
                         ( 
                         
                           
                             C 
                             
                               GS 
                                
                               
                                 ( 
                                 PW 
                                 ) 
                               
                             
                           
                           + 
                           
                             C 
                             
                               GD 
                                
                               
                                 ( 
                                 PW 
                                 ) 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                   , 
                   and 
                 
               
             
           
         
       
       
         
           
             
               
                 
                   
                     τ2 
                     gate 
                   
                   = 
                   
                     
                       ( 
                       
                         
                           1 
                           gm 
                         
                         + 
                         
                           R 
                           SW 
                         
                       
                       ) 
                     
                     * 
                     C 
                      
                     
                         
                     
                      
                     
                       2 
                       gate 
                     
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         
                           1 
                           gm 
                         
                         + 
                         
                           R 
                           SW 
                         
                       
                       ) 
                     
                     * 
                     
                       [ 
                       
                         
                           C 
                           
                             GS 
                              
                             
                               ( 
                               PW 
                               ) 
                             
                           
                         
                         + 
                         
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   G 
                                   M 
                                 
                                 * 
                                 
                                   R 
                                   L 
                                 
                               
                             
                             ) 
                           
                           * 
                           
                             C 
                             
                               GD 
                                
                               
                                 ( 
                                 PW 
                                 ) 
                               
                             
                           
                         
                       
                       ] 
                     
                   
                 
               
             
           
         
       
       
         
           where 
         
       
       
         
           
             
               G 
               m 
             
             = 
             
               
                 
                   gm 
                   PW 
                 
                 
                   1 
                   + 
                   
                     
                       gm 
                       PW 
                     
                     * 
                     
                       R 
                       o 
                     
                   
                 
               
               . 
             
           
         
       
     
         [0071]    In an ideal case, if no parasitic elements (i.e. null C GD ) were present, the current waveform would track the gate voltage and the two rise times would be coincident (not considering any effect of the load capacitance C L ). The effect of C GD  on the load current is evident: just after the rising edge of the gate, C GD , which initially has 4.5V (=V LED ), in this example) at its terminals, cannot discharge instantaneously (in fact Vout goes to a certain extent above V LED ). In this way, the current waveform starts to deviate from that of the gate. 
         [0072]    For the same DMOS size (same C GD ) and output current conditions, the higher the R L  value, the higher the current rise time deviation from the gate rise time. From a load side point of view, if R L  increases, the parasitic capacitor senses a larger time constant (R L *C GD ), moreover the load line waveform flattens and the output node (together with C GD ) has to discharge a larger amount of stored energy (if I OUT =20 mA, V LED =4.5V, V OUT  drops from 4.5V to 1.5V, if R L =150 Ohm; while it drops from 4.5V to 4.4V, if R L =5 Ohm). 
         [0073]    For the exemplary circuit considered, the current rise time deviation from the gate rise time becomes appreciable for R L ≧20 Ohm, as shown in the diagrams of  FIG. 15 . The effect of the load capacitance C L  is to increase the time constants involved, in particular it may contribute about: 
         [0000]      τ L =( r   o   ∥R   L )* C   L , 
         [0000]    where r o  is the resistance seen on the output node. The major effect is on the current rise time, while it is not so relevant on the gate rise time. For the exemplary circuit considered, a load capacitance C L =10 pF has almost no influence on the rise times. 
       Further Simulation Results 
     Relationship of Gate and Gate m  Nodes 
       [0074]    The waveforms of  FIG. 16  provide an insight of the effects of parasitic elements in the real circuit of  FIG. 6  (that behaves differently from the simplified equivalent circuit of  FIG. 11 ). At the switching instant of the circuit (ENABLE=ON), the gatem node starts from a voltage level that corresponds to the steady state level of the gate node. The gateb node is one V GS  above the level of the nodes gate and gatem (i.e. of the steady state level for the set output current). The diagrams show the movement of gateb with gate in correspondence of the switching event. Considering the real circuit of  FIG. 6 , at the switching on instant t 2 , the capacitance Cb plays an important role as far as the gateb node is not a perfect (ideal) zero impedance node. Because the Cb capacitance cannot change its potential instantaneously, the gateb voltage exhibits an overshoot that is transferred to the gatem/gate nodes and hence to the output current. Nevertheless, the overshoot is well controlled because the gateb is a low impedance node ( FIG. 22  relative to critical current spike conditions). 
         [0075]    The movements of the voltages Vgatem and Vgate and therefore of Iout follow the movements of the node gateb. The smaller R L , the faster is the charging of the gate node and therefore the higher is the “ringing” of the gateb node around its steady state value. In the simulations, the supply voltage V LED  of the driven LED was adapted to the value of R L  in order to maintain a steady state voltage V OUT  on the output pad of 1.5V. The dynamic responses for the different conditions are illustrated in  FIGS. 18 ,  19 ,  20  and  21 . By increasing V OUT  above 1.5V, rising edges even shorter than 2 ns are achieved by the circuit. As expected and evident from the waveforms, the worst rise time figures are for the maximum tested R L  value of 150 Ohm. 
         [0076]    The longest settling time of overshoot as observed for the worst condition of R L =5 Ohm, was about 30 ns, the current remaining well within 2.5% of the final value. The behavior of the driver circuit under the most critical conditions for the generation of current spikes is illustrated in the waveform of  FIG. 21  for the tested maximum load supply voltage V LED =20V and minimum load resistance R L =5 Ohm. It is significant to note that rise time under same load conditions does not change significantly for the different values of the output current. This behavior may be useful in some applications. 
         [0077]    Effect of Increasing the Size of the Replica DMOS on the Current Rise Time 
         [0078]    Considering that as can be observed from the waveform diagrams, the gatem node starts from a lower voltage value then the steady state voltage value of the gate node, it is possible to increase by a remarkable amount the rise time for adapting it to eventual particular requests by simply increasing the size of the scaled replica DMOS from that given by design ratio W/n and/or the sensing resistance from that given by the design ratio DMOS of the replica feedback loop, because the scaled replica DMOS uses a lower V GS  value for the loop to set the same current. This is so because the feedback signal produced by the scaled replica loop starts from a lower level than that used at steady state by the output power device, therefore, at any ON instant, the power gate voltage starts from a lower value than the used steady state value and this difference may be recouped through the relatively poor output dynamic characteristics (slew rate) of the op amp, as already commented earlier. 
         [0079]    For the exemplary results illustrated in  FIG. 22  and  FIG. 23 , the size of the replica DMOS was changed from an initial W=6 μm value to W=200 μm and the current Im flowing in the replica branch and its ratios with Ibias and with Iout were kept constant (the power ratio changes from 1:800 to 1:24). 
         [0080]    The waveforms provide a comparison between the gate voltages before and after the switching and making evident the starting from a lower level. Some applications particularly sensitive to noise may benefit from such an effective way of implementing a more relaxed rise time when it is compatible with speed specification and desirable from a minimization of noise point of view. For example, this could be useful in display applications where neither a particularly high rate dimming or high PWM performances are requested and/or where the design of application boards is insufficiently optimized for noise and EMI immunity, because of cost reduction compromises and relatively smaller di/dt may be implemented.