Abstract:
A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver.

Description:
CROSS-REFERENCES TO RELATED PATENT APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. 119(a) to Korean Application No. 10-2008-0077692, filed on Aug. 8, 2008, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention described herein generally relates to a semiconductor memory apparatus, and more particularly, to a control circuit of a read operation for a semiconductor memory apparatus. 
         [0004]    2. Related Art 
         [0005]    Typical semiconductor memory apparatuses use a parallel input/output system for exchanging data with an external chipset using a single port having a plurality of input/output pins. The parallel input/output has an advantage of processing data at a high speed since the parallel input/output can simultaneously transmit several bits of data. 
         [0006]    However, the parallel input/output has a disadvantage in that the number of buses required for transmitting data increases and the more the data transmission distance increases, which results in an increased unit cost of the product. 
         [0007]    A SERDES (SERializer and DESeriallizer) has been used in the conventional art in order to supplement the disadvantages of the parallel input/output. In the SERDES, a semiconductor memory apparatus is provided with two or more ports with each port including a SERDES circuit. Each of the ports converts series signals that are externally inputted into parallel signals and transmits them to a memory bank, and also converts parallel signals that are inputted from the memory bank into series signals and outputs them to the outside. 
         [0008]    According to these operations, a SERDES type memory apparatus can reduce the number of bus lines required. 
         [0009]    In the SERDES, at least two write/read operations are executed for every one write/read command. Accordingly, in a SERDES type semiconductor memory apparatus having a CAS-to-CAS delay ‘tCCD’ of four clocks, one write/read operation should be executed within two clocks. 
         [0010]    Presently, the time interval for this operation is fixed. Accordingly, one time period for a write/read operation should be executed within 2 ns for a target frequency of 1 ns. That is, a column selection signal ‘YI’ for controlling the first write/read operation and a column selection signal ‘YI’ for controlling the second write/read operation should not be delayed by more than 2 ns. 
         [0011]    In addition, the time interval between the two column selection signals ‘YI’s is a fixed value corresponding to a high-frequency operation, without consideration to the operational speed of the semiconductor memory apparatus. Accordingly, the semiconductor memory apparatus always operates with the predetermined minimum margin. 
         [0012]      FIG. 1A  and  FIG. 1B  are circuit diagrams showing a procedure for a command process in a conventional SERDES semiconductor memory apparatus. 
         [0013]    First,  FIG. 1A  is a circuit diagram showing a write operation. 
         [0014]    First, a a write command ‘WT’ that is created by a command decoder (not shown) is enabled and supplied to a column decoder  101 . The column decoder  101  receives an address signal ‘ADD’ and the write command ‘WT’ and creates a first column selection signal ‘YI 1 ’ and a second column selection signal ‘YI 2 ’ synchronized with a clock signal ‘CLK’ supplied to the column decoder  101 . The second column selection signal ‘YI 2 ’ can be a signal that is delayed by a predetermined time interval, e.g., two periods of the clock signal, and in synchronization with the first column selection signal ‘YI 1 ’. 
         [0015]    Further, data input multiplexers ‘MUX 1 ’, ‘MUX 2 ’  103 ,  105  each receive the column selection signals ‘YI 1 ’, ‘YI 2 ’ and data ‘DIN’ such that the data can be transmitted to a memory bank. According to this configuration, the input data ‘DIN’ is inputted to a port after undergoing a predetermined process according to a data strobe signal ‘DQS’ from a data input pad ‘DQ’ and is parallelized. Then, the input data ‘DIN’ is transmitted to the data input multiplexers  103 ,  105  through a global input/output line ‘GIO’. 
         [0016]    A write driver  107  transmits the data received from the input multiplexers ‘MUX 1 ’ and ‘MUX 2 ’, which receive the input data through the global input/output line, to a memory bank block through a local input/output line ‘LIO/LIOb’. 
         [0017]    For example, when two write operations are executed for one write command, input data having 8 bits is parallelized to 4bits-by-4bits and sequentially inputted through the GIO to the input multiplexers ‘MUX 1 ’ and ‘MUX 2 ’. Further, the data input multiplexer ‘MUX 1 ’  103  transmits the first  4  bits of data to the local input/output line ‘LIO/LIOb’ via the write driver  107  according to the first column selection signal ‘YI 1 ’. Thereafter, the data input multiplexer ‘MUX 2 ’  105  transmits the second  4  bits of data to the local input/output line ‘LIO/LIOb’ via the write driver  107  according to the second column selection signal ‘YI 2 ’ that is outputted after a predetermined time interval (i.e., two clocks). 
         [0018]    As described above, it is possible to transmit the data inputted according to the data strobe signal to the memory bank at an exact time since the column selection signals ‘YI 1 ’ and ‘YI 2 ’ are created in synchronization with the clock signals during the write operation. 
         [0019]    Next,  FIG. 1B  is a circuit diagram showing a read operation. 
         [0020]    As a read command ‘RD’ is enabled, a column decoder  201  receives an address signal ‘ADD’ and the read command ‘RD’ and outputs a column selection signal ‘YI’. Accordingly, an input/output sense amplifier  205  receives data ‘DOUT’ stored in the memory bank block through the local input/output line ‘LIO/LIOb’ and subsequently amplifies and latches the data. 
         [0021]    In response to an output signal of a first delay unit  215 , the data amplified by the input/output sense amplifier  205  is transmitted to a pipe latch  213  through global input/output line drivers  207 ,  209  and a multiplexer  211 . In this configuration, the first delay unit  215  delays a sensing-enable signal ‘IOSTB’ outputted from a sensing-enable signal generator  203  for a predetermined amount of time and then outputs it. 
         [0022]    More specifically, a portion (a first data group) of the output signals from the input/output sense amplifier  205  is transmitted to the multiplexer  211  through a global input/output driver according to a first delay signal ‘MAO&lt; 1 &gt;’ outputted from the first delay unit  215 . The rest (a second data group) of the output signals from the input/output sense amplifier  205  are then transmitted to the multiplexer  211  through a global input/output driver according to a second delay signal ‘MAO&lt; 2 &gt;’ outputted from the first delay unit  215 . According to this configuration, the second delay signal ‘MAO&lt; 2 &gt;’ is a value obtained by delaying the first delay signal ‘MAO&lt; 1 &gt;’ by a predetermined time. 
         [0023]    The first data group is inputted to the multiplexer  211  and should be stored in the pipe latch  213  before the second data group is inputted to the multiplexer  211 . Therefore, first and second pipe latch control signals ‘PIN 1 ’, ‘PIN 2 ’ that are created by a second delay unit  217  should be designed so as to have the same delay values as the first and second delay signals ‘MAO&lt; 1 &gt;’, ‘MAO&lt; 2 &gt;’ that are outputted from the first delay unit  215 , respectively. 
         [0024]    As described above, the first delay unit  215  and the second delay unit  217  are designed to have a fixed delay time, regardless of the operational speed of a semiconductor memory apparatus. However, the positions of the first delay unit  215  and the second delay unit  217  are designed differently and therefore, there is difficulty in configuring the delay units  215 ,  217  to have the exact same delay values. As a result, a problem occurs where the data that has been transmitted to the global input/output line is not transmitted to the pipe latch  213  at the exact time. This problem can be exacerbated in a high-frequency operation and cause the semiconductor memory apparatus to malfunction. 
         [0025]    Further, since the delay times applied to the first delay unit  215  and the second delay unit  217  are values created by fixing the sensing-enable signal ‘IOSTB’ for a predetermined time, the first delay unit  215  and the second delay unit  217  operate according to the fixed value, even though the operational margin is sufficient in a low-frequency operation, such that the efficiency of the semiconductor memory apparatus is deteriorated. 
       SUMMARY 
       [0026]    A control circuit of a read operation capable of performing a read operation on the basis of a clock in a SERDES type semiconductor memory apparatus is provided. 
         [0027]    A control circuit of a read operation can ensure an operational margin by changing a data output time interval in synchronization with a clock in accordance with the operational frequency in a read operation in a SERDES type semiconductor memory apparatus. 
         [0028]    In one embodiment of the present invention, a control circuit of a read operation for semiconductor memory apparatus which is a control circuit of a read operation for a SERDES type semiconductor memory apparatus includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver. 
         [0029]    These and other features, aspects, and embodiments are described below in the section entitled “Detailed Description.” 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0031]      FIG. 1A  and  FIG. 1B  are circuit diagrams showing a procedure for a command process in a conventional SERDES type semiconductor memory apparatus; 
           [0032]      FIG. 2  is a diagram showing the configuration of a control circuit of a read operation according to an embodiment of the present invention; 
           [0033]      FIG. 3  is a diagram showing the configuration of the first delay unit shown in  FIG. 2 ; 
           [0034]      FIG. 4  is a diagram showing the configuration of the second delay unit shown in  FIG. 2 ; and 
           [0035]      FIG. 5  is a diagram showing the configuration of a control circuit of a read operation according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0036]    Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 
         [0037]      FIG. 2  is a diagram showing the configuration of a control circuit for a read operation according to an embodiment of the present invention. 
         [0038]    A control circuit for a read operation according to an embodiment of the present invention can include a first delay unit  315 , a second delay unit  317 , and a signal separating unit  319 . 
         [0039]    The first delay unit  315  receives an sensing-enable signal ‘IOSTB’ from a sensing-enable signal generator  303  and generates a first delay signal ‘MAO&lt; 1 &gt;’ that is provided to a first global input/output line driver  307 . The first delay unit  315  also generates a second delay signal ‘MAO&lt; 2 &gt;’ by delaying the sensing-enable signal ‘IOSTB’ in synchronization with a clock signal ‘CLK’ received at the first delay unit  315  and provides the second delay signal ‘MAO&lt; 2 &gt;’ to a second global input/output line driver  309 . 
         [0040]    A second delay unit  317  generates a pipe latch control signal ‘PIN’ in response to the first delay signal ‘MAO&lt; 1 &gt;’ and the second delay signal ‘MAO&lt; 2 &gt;’ outputted from the first delay unit  315 . 
         [0041]    A signal separating unit  319  generates first and second pipe latch control signals ‘PIN 1 ’, ‘PIN 2 ’ from the pipe latch control signal ‘PIN’ outputted from the second delay unit  317 . 
         [0042]    The read operation of a semiconductor memory apparatus including the above control circuit for a read operation is described in detail hereafter. 
         [0043]    As a read signal ‘RD’ is enabled, a column decoder  301  receives the read signal ‘RD’ and an address signal ‘ADD’ and outputs a column selection signal ‘YI’. An input/output sense amplifier  305  receives data ‘DOUT’ stored in a memory bank block through a local input/output line ‘LIO/LIOb’, and then amplifies and latches the data. 
         [0044]    After the sensing-enable signal ‘IOSTB’ is outputted from the sensing-enable signal generator  303 , the first delay unit  315  outputs the first delay signal ‘MAO&lt; 1 &gt;’ by delaying the sensing-enable signal ‘IOSTB’ for a predetermined time. Thereafter, a first data group is latched in the input/output sense amplifier  305  and is transmitted to a multiplexer  311  according to the first delay signal ‘MAO&lt; 1 &gt;’ through a first global input/output line driver  307 . 
         [0045]    The first data group that is inputted to the multiplexer  311  is stored in a pipe latch  313  in response to a first pipe latch control signal ‘PIN 1 ’ that is outputted from the signal separating unit  319 . 
         [0046]    A second data group is then latched in the input/output sense amplifier  305  and is transmitted to the multiplexer  311  through a second global input/output line driver  309  according to the second delay signal ‘MAO&lt; 2 &gt;’ that is generated in the first delay unit  315  by delaying the sensing-enable signal ‘IOSTB’ in synchronization with the clock ‘CLK’. 
         [0047]    Thereafter, the second data group is stored in the pipe latch  313  in response to a second pipe latch control signal ‘PIN 2 ’ that is outputted from the signal separating unit  319 . 
         [0048]    As described above, it is possible to ensure a margin between a low-frequency operation and the read operation since the second delay unit ‘MAO&lt; 2 &gt;’ is generated by delaying the sensing-enable signal ‘IOSTB’ in synchronization with the clock after the first delay signal ‘MAO&lt; 1 &gt;’ is outputted. 
         [0049]    The data that is stored in the multiplexer  311  is transmitted to the pipe latch  313  according to the pipe latch control signal ‘PIN 1 ’, ‘PIN 2 ’, which are generated according to the first delay signal ‘MAO&lt; 1 &gt;’ and the second delay signal ‘MAO&lt; 2 &gt;’. Accordingly, the point in time when data is transmitted to the multiplexer  311  and the point in time when the pipe latch  313  stores the data do not overlap. 
         [0050]      FIG. 3  is a diagram showing the configuration of the first delay unit  315  shown in  FIG. 2 . 
         [0051]    As shown in  FIG. 3 , the first delay unit  315  is configured to include a first delayer  401 , a latch  403 , and a second delayer  405 . 
         [0052]    The first delayer  401  outputs the first delay signal ‘MAO&lt; 1 &gt;’ by delaying the sensing-enable signal ‘IOSTB’ for a predetermined time. The latch  403  shifts the sensing-enable signal ‘IOSTB’ in synchronization with the clock ‘CLK’. The second delayer  405  then outputs the second delay signal ‘MAO&lt; 2 &gt;’ by delaying an output signal of the latch  403  for a predetermined time. 
         [0053]    According to this configuration, the latch  403  comprises a D-flipflop (not shown) that delays the sensing-enable signal ‘IOSTB’ by  2  bits in response to the clock ‘CLK’ signal. It is preferable that the delay amounts of the first delayer  401  and the second delayer  405  are configured to have the same value. 
         [0054]      FIG. 4  is a diagram showing the configuration of the second delay unit  317  shown in  FIG. 2 . 
         [0055]    In a preferred embodiment of the present invention, the second delay unit  317  comprises a logic element that receives the first delay signal ‘MAO&lt; 1 &gt;’ and the second delay signal ‘MAO&lt; 2 &gt;’ and generates a pulse every time one of the received signals is enabled. For example, the logic element can be formed by connecting a NOR gate with an inverter in a series in which the output pulse of the logic element is a pipe latch control signal ‘PIN’ as shown in  FIG. 4 . 
         [0056]    Though not shown, the signal separating unit  319  comprises a counter. In this configuration, a counting operation is performed every time a pulse is outputted from the second delay unit  317 . The counted values are used as the first and second pipe latch control signals ‘PIN 1 ’, ‘PIN 2 ’. 
         [0057]      FIG. 5  is a diagram showing the configuration of a control circuit for a read operation according to another embodiment of the present invention. 
         [0058]    In a control circuit for a read operation according to the embodiment of the present invention shown in  FIG. 5 , unlike the control circuit for a read operation shown in  FIG. 2 , a second delay unit  321  generates a first pipe latch control signal ‘PIN 1 ’ and a second pipe latch control signal ‘PIN 2 ’ using the sensing-enable signal ‘IOSTB’ and the clock ‘CLK’, respectively. For this operation, the second delay unit  321  is configured as shown in  FIG. 3 . 
         [0059]    That is, the second delay unit  321  can also include a first delayer outputting the first pipe latch control signal ‘PIN 1 ’ by delaying the sensing-enable signal ‘IOSTB’ for a predetermined time, a latch for shifting the sensing-enable signal ‘IOSTB’ in synchronization with the clock ‘CLK’, and a second delayer outputting the second pipe latch control signal ‘PIN 2 ’ by delaying an output signal of the latch for a predetermined time. 
         [0060]    In this circuit configuration, the clock ‘CLK’ that is inputted to the first delay unit  315  and the clock ‘CLK’ that is inputted to the second delay unit  321  should be controlled such that they do not have a time difference. 
         [0061]    In this embodiment, when data is transmitted to the multiplexer  311  and when the data stored in the multiplexer  311  is transmitted to the pipe latch  313 , delay signals are used that have been generated in the same manner, i.e., using the same signal inputs and the same circuit configuration for each delay unit. Therefore, the point in time when data is transmitted to the multiplexer  311  and a point in time when the pipe latch  313  stores the data do not overlap. 
         [0062]    While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the device and method described herein should not be limited based on the described embodiments. Rather, the devices and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above to description and accompanying drawings.