Abstract:
A semiconductor storage apparatus according to one embodiment of the present invention, comprising: a cell array including a plurality of memory cells, each being connected to bit lines and word lines arranged in a row direction and a column direction; and a sense amplifier which controls read-out of data stored in the memory cells, wherein the sense amplifier includes: a pair of sense nodes provided corresponding to a pair of the bit lines; a connection switching circuit connected between the pair of bit lines and the pair of sense nodes, which connects electrically the pair of bit lines and the pair of sense nodes when a write control signal is in a prescribed logic level; and a timing control circuit which sets the write control signal to the prescribed logic level substantially at the same time as a timing when a column selection signal selects a column to which the memory cell to be written is connected during data writing period for the memory cells, and holds the write control signal to the prescribed logic level during a first period regulated by the timing when the column selection signal selects the columns.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-253059, filed on Aug. 31, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor storage apparatus including cell arrays having a plurality of memory cells, and sense amplifiers.  
         [0004]     2. Related Art  
         [0005]     As for the conventional one transistor—one capacitor DRAM cell including a trench capacitor or a stacked capacitor, there is a concern that its fabrication may become difficult as it becomes finer. As a candidate for a future DRAM, a new memory cell FBC (Floating Body Cell) is proposed (see Japanese Patent Application Laid-Open Publication Nos. 2003-68877 and 2002-246571). In the FBC, majority carriers are stored in a floating body of an FET (Field Effect Transistor) formed on SOI (Silicon on Insulator) or the like, to store information.  
         [0006]     In such a memory cell, an element unit for storing one bit information is formed of only one MISFET (Metal Insulator Semiconductor Field Effect Transistor). Therefore, the occupation area of one cell is small, and storage elements having a large capacity can be formed in a limited silicon area. It is considered that such a memory cell can contribute to an increase of the storage capacity.  
         [0007]     The principle of writing and reading for an FBC can be described as follows by taking an N-type MISFET as an example. A state of “1” is defined as a state in which there are a larger number of holes. On the contrary, a state in which the number of holes is smaller is defined as “0.” 
         [0008]     The FBC includes an nFET formed on SOI. Its source is connected to GND (0 V) and its drain is connected to a bit line (BL), whereas its gate is connected to a word line (WL). Its body is electrically floating. For writing “1” into the FBC, the transistor is operated in the saturation state. For example, the word line WL is biased to 1.5 V and the bit line BL is biased to 1.5 V. In such a state, a large number of electron-hole pairs are generated near the drain by impact ionization. Among them, electrons are absorbed to the drain terminal. However, holes are stored in the body having a low potential. The body voltage arrives at a balanced state in which a current generating holes by impact ionization balances a forward current of a p-n junction between the body and the source. The body voltage is approximately 0.7 V.  
         [0009]     A method of writing data “0” will now be described. For writing “0,” the bit line BL is lowered to a negative voltage. For example, the bit line BL is lowered to −1.5 V. As a result of this operation, a p-region in the body and an n-region connected to the bit line BL are greatly forward-biased. Most of the holes stored in the body are emitted into the n-region. A resultant state in which the number of holes has decreased is the “0” state.  
         [0010]     As for the data reading, distinguishing between “1” and “0” is conducted by setting the word line WL to, for example, 1.5 V and the bit line BL to a voltage as low as, for example, 0.2 V, operating the transistor in a linear region, and detecting a current difference by use of an effect (body effect) that a threshold voltage (Vth) of the transistor differs depending upon a difference in the number of holes stored in the body. The reason why the bit line voltage is set to a voltage as low as 0.2 V in this example at the time of reading is as follows: if the bit line voltage is made high and the transistor is biased to the saturation state, then there is a concern that data that should be read as “0” may be regarded as “1” because of impact ionization and “0 ” may not be detected correctly.  
         [0011]     In order to read out data stored in the FBC, a sense amplifier for detecting a current difference between a “0” cell and a “1” cell is provided. The sense amplifier in the conventional FBC has a configuration in which one node is selected from plurality of bit lines BL and sense amplifiers are arranged for the selected nodes. The reason why such a configuration can be adopted is that nondestructive readout is supposed to be possible for the FBC. In other words, the FBC is thought to have a feature that data in cells that are not read are not destroyed even if the word line becomes active and the data continue to be retained as they are if the word line is restored to the retaining level.  
         [0012]     In subsequent characteristic evaluation of the FBC, however, it has been found that the FBC is not necessarily a non-destructive read-out cell. Because it has been found that the charge pumping phenomenon affects the characteristics of the cell. If the gate of the transistor is pumped a plurality of times and thereby the inversion state and the accumulation state on the silicon surface are repeated alternately, holes gradually disappear at an interface between the silicon surface and SiO 2 . This is the charge pumping phenomenon.  
         [0013]     The number of holes that disappear due to one state change between inversion and accumulation depends on a density Nit of interface states the Si—SiO 2  interface. For example, supposing that Nit=1×10 10  cm −2  and W (channel width)/L (channel length) of a cell transistor=0.1 μm/0.1 μm, the area of the Si—SiO 2  interface becomes 1.0×10 −1  cm 2  per cell and consequently the number of interface states per cell becomes approximately one on the average. The number of holes stored in one FBC has a difference of approximately 1,000 depending upon whether the data is “1” or “0”. If the word line WL is subjected to pumping approximately 1,000 times, therefore, data “1” completely changes to data “0”. Practically, if the word line WL is subjected to pumping approximately 500 times, then the readout margin for the data “1” is lost and the risk that a fail may occur becomes high.  
         [0014]     In this way, the FBC is neither a destructive read-out cell nor a complete non-destructive read-out cell. It is found that the FBC is so to speak a “quasi non-destructive read-out cell”.  
         [0015]     If the sense amplifier circuit of the conventional scheme is applied to such a case, data is not written back even when the word line is activated. If WL is activated during the refresh operation approximately 500 times, therefore, a fail in which data “1” changes to “0” occurs. Irrespective of whether the cell is selected for reading/writing, therefore, it becomes necessary to design a sense amplifier with some measure against the charge pumping phenomenon taken on all “1” data cells for which the word line WL is activated.  
         [0016]     Furthermore, such a sense amplifier circuit has a problem of a poor efficiency in the refresh operation as well. In other words, the number of cells that can be refreshed in one refresh cycle decreases to one eighth as compared with an ordinary DRAM in the case where the sense amplifier is connected to a node which are selected from eight BLs. If the refresh time is equal, therefore, it is necessary to conduct the refresh operation as frequently as eight times. By that amount, the proportion in which the ordinary read/write operation cannot be conducted increases.  
         [0017]     In addition, there is also a problem that the number of cells that can be accessed is limited when conducting fast column access. In other words, when using a sense amplifier circuit so as to increase the transfer rate of data by activating the word line, reading out cell data, latching the cell data in sense amplifiers, and accessing the data fast and continuously by means of only column address switching, the number of data that can be accessed decreases to one eighth as compared with the ordinary DRAM.  
         [0018]     If time required for FBC writing is longer than the cycle time when writing data by using fast column access, then a write fail occurs and this results in a problem that the column access cycle time cannot be made shorter than the FBC write time. Especially, writing FBC data “1” means charging capacitance of the body with holes generated by the impact ionization. If the number of holes generated by the impact ionization is small, therefore, the write time may become as long as approximately several nanoseconds (10 −9  second) or more in some cases.  
       SUMMARY OF THE INVENTION  
       [0019]     A semiconductor storage apparatus according to one embodiment of the present invention, comprising:  
         [0020]     a cell array including a plurality of memory cells connected to bit lines arranged in a column direction and word lines arranged in a row direction; and  
         [0021]     a sense amplifier which controls read-out of data stored in the memory cells,  
         [0022]     wherein the sense amplifier includes:  
         [0023]     a pair of sense nodes provided corresponding to a pair of the bit lines;  
         [0024]     a connection switching circuit which connects electrically the pair of bit lines and the pair of sense nodes when a write control signal is in a prescribed logic level; and  
         [0025]     a timing control circuit which sets the write control signal at the prescribed logic level at the same time when a column selection signal selects a column, and then holds the write control signal at the prescribed logic-level during a first period. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]      FIG. 1  is a block diagram showing a general configuration of a semiconductor storage apparatus according to an embodiment of the present invention.  
         [0027]      FIG. 2  is a circuit diagram showing an example of a detailed configuration of the cell array and the sense amplifiers.  
         [0028]      FIG. 3  is a circuit diagram showing an example of an internal configuration of a sense amplifier.  
         [0029]      FIG. 4  is a timing chart at the time of refresh operation.  
         [0030]      FIG. 5  is a circuit diagram showing an example of an internal configuration of the column decoder  7 .  
         [0031]      FIG. 6  is a circuit diagram showing an example of an internal configuration of the WCSL timer  10 .  
         [0032]      FIG. 7  is a timing diagram at the time when data is written into an FBC  21 .  
         [0033]      FIG. 8  is a timing diagram showing data reading from an FBC  21 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]     Hereafter, an embodiment of the present invention will be described with reference to the drawings.  
         [0035]      FIG. 1  is a block diagram showing a general configuration of a semiconductor storage apparatus according to an embodiment of the present invention. The semiconductor storage apparatus shown in  FIG. 1  includes a plurality of cell arrays  1  arranged in a row direction, sense amplifiers  2  disposed between these cell arrays  1 , DQ buffers  3  for conducting input/output for data line, row decoders  4 , a row address buffer  5 , a row address pre-decoder  6 , a column decoder  7 , a column address buffer  8 , a column address pre-decoder  9 , a WCSL timer  10  described later, a control circuit  11 , a RAS/CAS/WE buffer  12 , a Din buffer  13 , and an off-chip driver  14 .  
         [0036]      FIG. 2  is a circuit diagram showing an example of a detailed configuration of the cell array  1  and the sense amplifiers  2  (S/A 0  to S/A 1023 ). As shown in  FIG. 2 , 256 word lines LWL 0  to LWL 255 , a dummy word line LDWL, 256 word lines RWL 0  to RWL 255  and a dummy word line RDWL are arranged in a row direction on left and right sides of a plurality of sense amplifiers  2  arranged in the center, respectively. In a column direction, 1024 bit lines LBL 0  to LBL 1023  and 1024 bit lines RBL 0  to RBL  1023  are arranged on the left and right sides of the sense amplifiers  2 . FBCs  21  are disposed near intersections of the word lines and the bit lines, respectively. Dummy cells  22  are disposed near intersections of the dummy word lines and the bit lines, respectively.  
         [0037]     When conducting read out, one word line belonging to some cell array  1  selected by a row address A 9 R is activated (raised) and a dummy word line belonging to the cell array  1  located across the sense amplifiers  2  from the word line is activated (raised).  
         [0038]     A reference level of “1/2” is written in the dummy cells  22 , or “0” and “1” are alternately written into the dummy cells that are adjacent in the column direction. In the latter case, data in two adjacent dummy cells  22  are read out at the time of read operation and averaged to generate the reference level of “1/2”. And data read out from the FBC  21  selected by a word line is compared with the reference level of “1/2” from the dummy cells  22 . It is determined whether data stored in the FBC  21  is “0” or “1” depending upon whether a cell current flowing through the FBC  21  is larger or smaller than a current flowing through a dummy cell  22 .  
         [0039]      FIG. 3  is a circuit diagram showing an example of an internal configuration of a sense amplifier  2 . The sense amplifier  2  is shared by the left and right bit lines. Hereafter, an internal configuration of the sense amplifier  2  will be described along a path connected to the bit lines LBL 0  and RBL 0 .  
         [0040]     As shown in  FIG. 3 , the sense amplifier  2  includes a pair of sense nodes LSN 0  and RSN 0  corresponding to the bit lines LBL 0  and RBL 0 , a current load circuit  23  connected to the pair of the sense nodes LSN 0  and RSN 0 , dynamic latch circuits  24  and  25  connected to the pair of the sense nodes LSN 0  and RSN 0 , a read control transistor  26  for the FBC  21  or the dummy cell  22 , a transfer gate  27  for controlling to write data into the FBC  21 , a write control circuit  28  for controlling the transfer gate  27 , and a transistor  29  for controlling data input and output.  
         [0041]     The current load circuit  23  includes PMOS transistors  30  and  31  connected in series between a positive voltage VBLH and the sense node LSN 0 , and PMOS transistors  32  and  33  connected in series between the positive voltage VBLH and the sense node RSN 0 . The transistors  31  and  33  are short-circuited to each other at their gates to form a current mirror circuit. If a signal BLOADON becomes a low level, therefore, the current load circuit  23  lets currents of the same quantity flow through the pair of sense nodes LSN 0  and RSN 0 .  
         [0042]     Each of the dynamic latch circuits  24  and  25  includes PMOS transistors  34  and  35  cross-connected between the pair of sense nodes LSN 0  and RSN 0 . If a potential difference between the pair of sense nodes LSN 0  and RSN 0  becomes large, and a signal SAP connected between the transistors  34  and  35  and a signal BSAN respectively become a high level and a low level, then the dynamic latch circuits  24  and  25  amplify a potential difference obtained between the pair of sense nodes LSN 0  and RSN 0 .  
         [0043]     If a signal FITL becomes a high level, the read control transistor  26  short-circuits the bit line LBL 0  to the sense node LSN 0 . If a column selection signal CSL becomes a high level, the data input &amp; output control transistor  29  short-circuits a data line DQ 0  to the sense node LSN 0 , and short-circuits a data line BDQ 0  to the sense node RSN 0 . A write control circuit  28  controls opening/closing of the transfer gate  27  based on logic levels of a write control signal WCSL, a row address BA 9 R and a write back signal FB.  
         [0044]     In the present embodiment, refresh operation is conducted periodically as a countermeasure against the charge pumping phenomenon.  FIG. 4  shows a timing chart at the time of refresh operation. Hereafter, it is supposed that a FBC  21  connected to the bit line LBL 0  is to be refreshed. At time t 1 , the signal FITL and a signal FITR are at a high level and data in the FBC  21  to be refreshed is read out. If the signal BLOADON becomes a low level at the time t 1 , the potential difference between the pair of sense nodes LSN 0  and RSN 0  shown in  FIG. 3  gradually increases. At this time, the transistor  26  is in the on-state, and data stored in the FBC  21  to be refreshed is read out onto the sense node LSN 0 .  
         [0045]     If the signal SAP becomes a high level and the signal BSAN becomes a low level, the dynamic latch circuits  24  and  25  latch the potentials at the pair of sense nodes LSN 0  and RSN 0 .  
         [0046]     Subsequently, if the signal FB becomes a high level at time t 3 , then the transfer gate  27  opens and the potential at the sense node RSN 0  is written into the bit lines LBL 0  and RBL 0 .  
         [0047]     When conducting refreshing, the column selection line CSL remains at the low level and refresh operation is conducted on all columns specified by the row address A 9 R simultaneously in parallel.  
         [0048]     Writing data into an FBC  21  will now be described.  FIG. 5  is a circuit diagram showing an example of an internal configuration of the column decoder  7 . As shown in  FIG. 5 , the column decoder  7  includes a NAND circuit  41  for performing NAND computation on signals YAi (i=0 to 3), YBj (j=0 to 3) and YCk (k=0 to 3) generated by a pre-decoder, which is not illustrated, and an enable signal CENB, and an inverter  42  for inverting an output of the NAND circuit  41  and outputting the inverted output.  
         [0049]     The pre-decoder, which is not illustrated, generates YAi (i=0 to 3), YBj (j=0 to 3) and YCk (k=0 to 3) on the basis of column address signals Aic (i=0 to 5) and their inverted signals BAjc (j=0 to 5). The output of the NAND circuit  41  is BCSL, and the output of the inverter  42  is the column selection signal CSL.  
         [0050]      FIG. 6  is a circuit diagram showing an example of an internal configuration of the WCSL timer  10 . The WCSL timer  10  includes a flip-flop  43  formed of two NAND circuits, an OR circuit  44  for controlling to bring the flip-flop  43  into a set state, inverters  45  and  46  connected in cascade to the output of the flip-flop  43 , and a delay circuit  47  for exercising control so as to bring the flip-flop  43  into the reset state a predetermined time after an output WCSL of the inverter  46  has become its high level.  
         [0051]     The delay circuit  47  includes a PMOS transistor  48  and an NMOS transistor  49  connected in series and turned on/off simultaneously by the output WCSL of the inverter  46 , a resistor  50  connected between the PMOS transistor  48  and the NMOS transistor  49 , a capacitor  51  connected between the PMOS transistor  48  at its drain and a ground voltage, and cascaded inverters  52  and  53  connected between the drain of the PMOS transistor  48  and a reset terminal of the flip-flop  43 .  
         [0052]     Hereafter, operation of the WCSL timer shown in  FIG. 6  will be described. If the column selection signal becomes a high level during writing (BWRT is set low), then the signal BCSL becomes a low level and an output of the OR circuit  44  becomes a low level. As a result, the flip-flop  43  is set to a high level, and the write control signal WCSL becomes a high level. The capacitor  51  in the delay circuit  47  begins to discharge via the NMOS transistor  49 . Until charges in the capacitor  51  are fully discharged, the reset terminal of the flip-flop  43  does not become a low level. Even if the column selection signal becomes a low level, therefore, the write control signal WCSL maintains its high level for a while.  
         [0053]     The discharge time of the capacitor  51  is determined by a time constant, which depends on a resistance value of the resistor  50  and capacitance of the capacitance  51 . In the present embodiment, the time constant is determined so as to make an interval over which the write control signal WCSL is active (the high level) longer than an interval over which the column selection signal CSL is active. Specifically, the time constant is set so as to make it possible for the write control signal WCSL to maintain the high level as long as the time necessary to write data into a cell.  
         [0054]     The timer  10  in which charges stored in the capacitor  51  are discharged through the resistor  50  to prescribe the time as shown in  FIG. 6  is not affected by a change in power supply voltage, a temperature change and characteristics dispersion of elements such as transistors. Thus, accurate and stable time can be set.  
         [0055]     If the capacitor  51  is fully discharged after the column selection signal CSL has become the low level, then the output of the inverter  53  becomes the low level and consequently the flip-flop  43  is brought into the reset state and the write control signal WCSL becomes a low level.  
         [0056]      FIG. 7  is a timing diagram at the time when data is written into an FBC  21 . In an example shown in this timing diagram, refresh operation for supplying holes vanished by the charge pumping phenomenon is first conducted, and then 31st, 10th and 112th column selection lines are consecutively activated in order to write data amplified by sense amplifiers  2 .  
         [0057]     A time period ranging from time t 1  to t 4  is an interval for the refresh operation. In this interval, operation similar to that shown in  FIG. 4  is conducted, and data read out from an FBC  21  is written back to the FBC  21  beginning at time t 3  when a signal FB has become a high level. The signal FB rises only once at the time of first refresh, and thereafter the signal FB becomes inactive (a low level).  
         [0058]     Thereafter, data write operation is conducted after time t 5 . Specifically, writing is conducted for the 31st column in an interval ranging from time t 5  to t 7 , for the 10th column in an interval ranging from time t 6  to t 8 , and for the 112th column in an interval ranging from time t 7  to t 9 .  
         [0059]     As for data writing, only a transfer gate  27  corresponding to the activated (selected) column selection line CSL is opened and data are written into FBCs  21  in respective write cycles in order.  
         [0060]     Since transfer gates  27  corresponding to unselected columns are closed, corresponding bit lines are in the floating state and cell currents do not flow through the corresponding bit lines. As a result, power consumption can be reduced.  
         [0061]     The write control signal WCSL generated by the WCSL timer  10  shown in  FIG. 6  rises at the same timing as the column selection line CSL does. If it takes a longer time to write data in an FBC  21  than the selection interval for the column selection line CSL, therefore, the write control signal WCSL falls after the column selection line CSL has become unselected (the low level).  
         [0062]     If the selection interval for the column selection line CSL is longer than the time set in the WCSL timer  10 , the flip-flop  43  maintains its set state as long as the column selection line CSL is at the high level. When the column selection line CSL has become unselected, therefore, the flip-flop  43  is brought into its reset state and the write control signal WCSL becomes the low level at substantially the same timing as that of the column selection line CSL. Practically, as apparent from the circuit of  FIG. 6 , after the column selection line CSL becomes low level (i.e. the signal BCSL becomes high level), and the signal passes through the gate  44 , the flipflop  43  and the inverters  45  and  46 , the write control signal WCSL becomes low level.  
         [0063]      FIG. 8  is a timing diagram showing data reading from an FBC  21 . In the case shown in  FIG. 8  as well, refresh operation for supplying holes vanished by the charge pumping phenomenon is first conducted (time t 1  to t 4 ). After time t 5 , 31st, 10th and 112th column selection lines CSL are consecutively activated and data amplified by sense amplifiers  2  are read out onto data lines DQ and BDQ. Specifically, readout is conducted for the 31st column in an interval ranging from time t 5  to t 6 , for the 10th column in an interval ranging from time t 6  to t 7 , and for the 112th column in an interval ranging from time t 7  to t 8 .  
         [0064]     In the readout, only the column selection line rises, and the write control signal WCSL remains inactive (the low level). Therefore, data latched between a pair of sense nodes LSN and RSN is not written back to the cell side.  
         [0065]     Thus, if the selection interval for the column selection line CSL is shorter than the time taken to write data into an FBC  21 , then in the present embodiment the write control signal WCSL is maintained in the active state (the high level) for a predetermined time even after the column selection line CSL has become unselected. Even if it takes a longer time to write data in the FBC  21  than the CSL activation period, therefore, it is possible to write data into the FBC  21  normally. In addition, since the refresh operation for the FBC  21  is conducted before writing/reading data into/from the FBC  21  in order to cope with the charge pumping phenomenon in the FBC  21 , it is possible to certainly prevent the charge pumping phenomenon from destroying data in the FBC  21 .  
         [0066]     In the embodiment, an example in which the column selection lines CSL and the write control signals WCSL are provided respectively by taking a pair of sense nodes and a pair of bit lines as the unit has been described. The unit of sense nodes and bit lines controlled by one selection line CSL and the unit of sense nodes and bit lines controlled by one write control signal WCSL may be changed. For example, the column selection lines CSL may be provided by taking a pair of sense nodes and a pair of bit lines as the unit, and the write control signals WCSL may be provided by taking an integer times as many as the pair of sense nodes and the pair of bit lines as the unit.  
         [0067]     If the number of sense nodes and bit lines controlled by one write control signal WCSL is thus increased, then the number of the write control signals WCSL can be decreased accordingly and the chip area can be reduced. Since the current consumption flowing through the write control signal WCSL increases accordingly, however, it is desirable to set the control range of the write control signal WCSL by taking the tradeoff between the increase of the chip area and the increase of the power consumption into consideration.