Abstract:
An analog current sensing circuit is controlled by a current loop microprocessor. An integrator circuit stores charge which is the integral of armature current in a motor. The output is read by the microprocessor and divided by a time value to determine an average value of current. The microprocessor generates a pulse to discharge a capacitor in the integrator circuit to the same extent it was charged by a current feedback signal. At the same time the circuit may be sensing current for the next cycle. Leftover fractions of pulses are stored as charge on the capacitor and are included in values sensed in succeeding cycles. Both a method and a circuit are disclosed.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The field of the invention is electronic controls for controlling electrical equipment, such as electric motors, where an electrical current is sensed and then compared to a current command to arrive at a resulting signal to be applied to the motor. The invention may also have application to other types of controls in which current sensing is important. 
     2. Background Art 
     An example of an electronic control for a DC motor is shown and described in Berkopec et al., U. S. Pat. No. 4,549,122, issued Oct. 25, 1985. A basic function of the control is to regulate armature current by sensing the actual current fed to the armature and by determining the difference between this signal and a current command signal. The difference between these two signals becomes an error signal that is applied to the motor through an armature current regulating amplifier to reduce the error or difference between the two signals. 
     Current sensing in this type of motor control has typically been accomplished with some type of analog circuitry. The application of digital microprocessors to this type of motor control has offered advantages in fast response time in executing motor control loops. The use of such digital circuits, however, requires new digital techniques for sensing the voltages and currents present in electrical motors. 
     SUMMARY OF THE INVENTION 
     The invention relates to digital control of an analog sensing circuit in a current loop controller portion of a larger motor controller. 
     According to a method of the invention a signal proportional to a current being supplied to an electrical device is fed back to an integrator circuit that generates an analog output signal. The analog output signal is sensed over a sample time period and converted to a digital value. An average value of the current being supplied to the electrical device is calculated by dividing the digital value by the sample time period. 
     The integrator circuit is reset in response to the digital value by generating a reset signal that is proportional to the digital value, and by generating the reset signal for a time period necessary to discharge the integrator circuit by an equal amount to which it was charged to generate the analog output signal. 
     By repeating this sequence over several cycles, a fraction of the analog output signal that is not sensed during one cycle, due to the resolution of the A-to-D conversion, can be picked up in later cycles. 
     A circuit according to the invention includes: (1) an integrator circuit having an input for receiving a feedback signal that is proportional to the current being supplied to the electrical device, and also having an output; (2) circuitry for sensing an analog signal for a sample time period at the output of the integrator circuit and converting it to a digital current value; (3) circuitry for calculating the average value of the current supplied to the electrical device by dividing the digital value by the sampling time period; (4) circuitry for controlling the resetting of the integrator circuit by controlling application of a reset signal to the input of the integrator circuit for a time period necessary to discharge the integrator circuit by an equal amount to which it was charged to generate the analog signal; and (5) circuitry for operating the above-mentioned circuitry for successive cycles, thereby sensing a fraction of the analog output signal that is not sensed during a first cycle due to the resolution of the conversion of the analog output signal to a digital value. 
     One object of the invention is to provide a method of current sensing for a processor-based motor control which does not require extensive programming and which maintains the accuracy of the resulting current values. 
     Another object of the invention is to provide a circuit for improving the resolution of current sensing by a digital microprocessor. 
     Another object of the invention is to provide an analog sensing circuit that can be controlled by a programmed microprocessor to provide an accurate value of current being supplied to a motor or other electrical device. 
     These and other objects and advantages of the invention will become apparent from the following description in which reference is made to the accompanying drawings and to the appendix, which form a part hereof, and in which there is illustrated by way of example, a preferred embodiment of the invention. This example does not necessarily represent the full scope of the invention, however, and reference is made to the claims that follow the description for determining the various embodiments that come within the scope of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a system block diagram for an electronic control for a DC motor that incorporates the present invention; and 
     FIG. 2 is a schematic of a current processor portion of the control in FIG. 1 that incorporates the present invention. 
     FIG. 3 is a flow chart illustrating the different steps carried by the current loop microprocessor. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, the invention is illustrated in the context of an electronic control for a DC motor that is referred to by those skilled in the art as a DC motor &#34;drive&#34;. The drive is connected through +DC and -DC lines to the armature 10 of a DC motor. The motor also includes a field winding 12 for generating an electromagnetic field in the motor. Although it is not essential to a description of the invention, it should be understood that the drive includes circuitry for controlling current supplied to the field winding 12 and circuitry suitable for this purpose is known to those skilled in the art. 
     The present invention concerns the circuitry for controlling electrical signals to the armature 10. A 3-phase AC power source 13 is connected through a current sensing device 11 to supply power to an SCR bridge and firing circuitry indicated generally by element 14. This element 14 should be understood to include not only a 3-phase SCR bridge for AC-to-DC power conversion but also SCR firing control circuitry, and where desired, a group of pulse transformers connecting the firing control circuitry to the 3-phase SCR bridge as described in Berkopec et al., U. S. Pat. No. 4,549,122. The SCR firing circuitry 14 responds to an armature current error signal (I ERROR ) from an armature current regulator 15 to select a phase angle at which the SCR&#39;s in the bridge network are fired. This allows for control of both the magnitude and polarity of the DC current which is supplied to the armature 10. 
     A current processor portion 16 of the drive executes a current regulation loop by sensing a current feedback signal (I FB ) and algebraically summing it with a current command signal (I CMD ) received from a speed regulator circuit 17 to generate the current error signal. Besides some type of sensing device 11 in the AC supply lines, such as current transformers or a Hall device, a motor drive will typically include some additional current sensing circuitry 18 for converting the current feedback signal to a level and polarity suitable for processing in the current processor, and this circuitry is represented generally by element 18 in FIG. 1. The armature current regulator 15 includes an amplifier which multiplies the error by a gain factor K I . The armature current regulator 15 typically includes both a proportional gain circuit and an integral circuit, so that the gain factor includes both proportional and integral gain factors. 
     A velocity loop portion of the drive includes speed feedback circuitry 19, which is connected to receive a speed feedback signal from a tachometer 20 coupled to a rotating output shaft on the armature 10. The speed feedback circuitry 19 converts the speed feedback signal from the tachometer 20 to a signal of the appropriate range and polarity for processing by the other velocity loop circuitry This circuitry executes a speed regulation loop by sensing a speed feedback signal (S FB ) received from the speed feedback circuitry 19 and algebraically summing it with a speed command signal (S REF )--usually generated by a human operator through a manual control device--to generate a speed error signal which is also the current command signal (I CMD ). The speed regulator circuit 17 includes an amplifier which multiplies the speed error by a gain factor K S . The speed regulator circuit 17 may also include both a proportional gain circuit and an integral circuit, so that the gain factor includes both proportional and integral gain factors. 
     FIG. 2 shows the details of the current processor portion 16 of the drive which are employed in carrying out the present invention. This includes a current processor 16a, which in this example is an Intel 8097 Microcontroller available from Intel Corporation, Santa Clara, Calif. This description will include certain salient details concerning employment of this microelectronic processing device in the particular circuit shown in FIG. 2, however, for full details concerning the architecture, operation and programming of this device, reference is made to the commercial literature available from Intel Corporation on this subject. 
     The current processor 16a is connected through Port 3 and Port 4 and through address and data buses 21 to memory 22 including EPROM (erasable programmable read only memory) circuits for storing a program of instructions to direct the operations of the current processor 16a and also including RAM (random access memory circuits) for storing data and temporary results generated during execution of the program. The current processor 16a is also connected through control lines (not shown) to control read and write operations and to activate the other circuitry controlled by it. 
     Three terminals on the processor 16a are of particular interest. Input terminal P0.4 (pin 11) in Port 0 is connected to the output of a charge sampling circuit in the form of an integrator circuit 23. An analog signal received at this terminal is applied to a 10-bit analog-to-digital converter included within the processor 16a. A voltage reference (VREF) terminal (pin 37) is connected through a solid state switch 24, a shunt resistor 25, and two series resistors 26, 27 to an inverting (-) input on an operational amplifier 28 which has been connected to operate as an integrator. The noninverting (+) input of the operational amplifier 28 is connected through a resistor 29 to a signal ground to provide a reference voltage of zero volts. The HSO.0 (high speed output 0) output terminal is an enable terminal for enabling the reset of the integrator circuit 23, and this terminal is connected to an enable input on the solid state switch 24. In the preferred embodiment two such switches are used in parallel to obtain lower resistance, however, they may be represented functionally by a single such switch 24. 
     A capacitor 30 has a positive plate connected to the inverting (-) input of the operational amplifier 28 and a negative plate connected to the output of the operational amplifier 28 through a resistor 31. In the preferred embodiment two such capacitors are connected in parallel to obtain the desired capacitance with lower cost, lower tolerance components, however, they may be represented functionally by a single such capacitor 30. A zener diode 32 with a breakdown threshold of +8.2 volts has an anode connected to the output of the operational amplifier 28 and a cathode connected to the inverting (-) input to limit the output voltage on the operational amplifier 28 to +8.2 volts, thereby preventing the operational amplifier 28 from being driven into saturation. The output of the integrator circuit 23 is somewhat lower due to the drop across the resistor 31 and the output point is clamped to a maximum of approximately +5.6 volts by a first diode 33 and is clamped to a minimum of approximately -0.6 volts by a second diode 34. This clamped output point is connected to input terminal P0.4 on the current processor 16a as explained earlier. 
     A positive voltage proportional to armature current is fed to a voltage clamp and inverter circuit 35 seen at the upper right corner of FIG. 2. The signal is applied through a positive side resistor 36 to the inverting (-) input of an operational amplifier 37 connected to operate as an inverter. In this configuration, a resistor 38 is connected across the inverting (-) input and the output of the operational amplifier 34. The noninverting (+) input is connected through another resistor 39 to a signal ground. The range of signals applied to the inputs of the operational amplifier 37 is limited by a bridge of four diodes 40, 41, 42 and 43 and resistor 44 which are connected to the inputs of the operational amplifier 37 and to +12-volt and -12-volt sources as shown. This limits the voltage at each input of the operational amplifier 37 to a range of approximately +12.6 volts to -12.6 volts. 
     The inverter circuit 37-39 inverts the positive voltage representing armature current to a negative voltage which is applied through resistor 45 to the inverting (-) input of the operational amplifier 28 which is also a summing point. This negative voltage is inverted by the integrator circuit 23 in the manner known in the art. If a constant DC voltage of -5 volts were applied in this manner the capacitor 30 across the operational amplifier 28 would charge and the output of the integrator circuit 23 would be a positively increasing ramp function of constant slope until the output of the op amp 28 reached the maximum of +8.2 volts. The capacitor 30 across the operational amplifier 28 can then be discharged (assuming no armature current feedback signal) by applying the positive reference voltage (VREF) through switch 24 for a suitable time to cause the capacitor 30 to discharge, and this causes the output voltage of the integrator circuit 23 to decrease to zero when the capacitor is completely discharged. 
     It is, however, a discovery related to the invention that it is not necessary to block the armature feedback signal during times when the integrator circuit 23 is being reset. The integrator circuit 23 accumulates charge on its capacitor 30 for a succeeding measurement cycle at the same time it is being discharged for a previous measurement cycle, provided that the discharge is equated to the charge accumulated on the previous measurement cycle. 
     The A-to-D converter in the current processor is a 10-bit device that counts from 1 to 1024 (decimal). The reference voltage (VREF) is supplied within the processor 16a to the A-to-D converter to scale the range of the converter to a maximum of +5 volts at a digital value of &#34;1024&#34;. The digital value of the A-to-D conversion can therefore be expressed as follows: 
     
         Digital Value=V.sub.IN ×1024 / V.sub.REF 
    
     where V IN  is limited to a maximum of +5 volts ± some tolerance. 
     The use of the integrator circuit 23 is advantageous because it improves the resolution of the analog-to-digital conversion. For example, if a digital value, which represents the integral of current that is charging the capacitor, is read by the processor 16a, and a reset signal is equated to this value and applied to the integrator circuit 23, the capacitor 30 may not be fully discharged. This is due to the remainder or increment of charge that is smaller than the resolution of the A-to-D converter. However, this remainder or increment of charge will be included in the total charge on the capacitor 30 during the next sampling cycle. With this technique, the small remainders of charge will combine to produce an added value of one count in some sampling intervals, and the average of digital values over several sampling cycles will take these small increments of charge into account. 
     The sampling cycles for the integrator circuit 23 are determined and controlled by the current processor 16a under the direction of a program read from the EPROM portion of memory 22. The pertinent portion of this program is disclosed in Appendix A as a &#34;Current Reference Module&#34;. This program module is presented in a high level language for microprocessors known as PL/M. With a suitable compiler, which is commercially available for this language and the Intel 8097 microprocessor, this program module can be compiled to object code. The conversion of the PL/M source code instructions to the assembly language for the Intel 8097 microprocessor, and the conversion of the assembly language instructions to a binary code of &#34;1&#39;s&#34; and &#34;0&#39;s&#34; is accomplished in a fashion that is transparent to the source code programmer. 
     The current processor 16a executes a &#34;Current Reference Module&#34; portion of the program to execute the current regulation loop shown in FIG. 1 and to control the time at which the SCR&#39;s are fired. As shown and described in Berkopec et al., U. S. Pat. No. 4,549,122, a suitable SCR bridge may include six pairs of SCR&#39;s. The SCR&#39;s are fired to convert three alternating current (AC) signals to direct current (DC) signals. The AC signals may be represented by sine waves in which each cycle has a positive half cycle and a negative half cycle. The three sine wave signals (Phase A, Phase B and Phase C) repeat 60 times each second (60 Hz) and when represented graphically are staggered in relation to each other (120° phase difference). Assuming, for example, that the motor is to be operated in the forward direction of rotation, the SCR bridge chops up the sine wave signals and converts all negative phase signals to positive value signals (rectification). To do this, the six pairs of SCR&#39;s are fired in sequence during the time period of one cycle of the AC signals from the power source 13. One pair of SCR&#39;s is fired for each phased sine wave signal (3 pairs total) during its positive half cycle and one pair of SCR&#39;s is fired for each phased sine wave signal (3 more pairs) during its negative half cycle. The SCR firings generate a series of pulses, all positive in this example, and the average value of these pulses is seen by the motor as a direct current (DC) voltage which produces a direct current in the armature 10. The SCR&#39;s can also be controlled to produce a DC voltage of negative polarity with respect to the terminals designated DC and -DC in FIG. 1. 
     During steady-state operation the six pairs of SCR&#39;s are fired in time intervals which are 1/6 of the time (60° apart in phase) for one cycle of the 60-Hz supply signal. When it is desired to increase the rate of firing to produce more current, these time intervals can be shortened or &#34;phased back&#34; to shorter time intervals representing a smaller phase difference (e.g. 45°). 
     Assuming the current command I CMD  calls for current in the same direction as is currently being supplied to the motor, the Current Reference Module directs the current processor 16a to read and calculate current loop regulation values until there is insufficient time to complete another iteration before an SCR pair must be fired. The current processor 16a then fires the next SCR pair. The Current Reference Module also sets up a timed interrupt to recall itself in advance of the next firing. If, for example, the firing times were 60° apart in phase relative to the 60-Hz signal, the Current Reference Module would be re-entered at a time 30° in phase in advance of the next firing time. Until re-entry, a time--corresponding to 30° in phase in this example--is provided for execution of background routines in the program for the current processor 16a. 
     The firing time of each pair of SCR&#39;s should be based on a current reading from the integrator circuit 23 that is as &#34;fresh&#34; as possible. Therefore, after a current integral value is read from the integrator circuit 23 and a firing time is calculated, the current processor 16a will perform another sampling cycle if there is enough time before the firing time. 
     When the current integral is first read from the integrator circuit 23, the next firing time is checked. If there is not enough time to execute a reset of the integrator circuit 23, the program sets a SAT FLAG bit in memory 22, as a way of determining--on the next time through this particular part of the program--whether or not the integrator circuit 23 has been reset. 
     The current sampling sequence is seen in Appendix A in the portion labeled &#34;Sample current: &#34; . Steps of the sequence which are significant to the invention are also shown in FIG. 3. After the start of the sample current sequence represented by start block 50 the current processor 16a determines whether or not the integrator circuit 23 has been reset from the previous cycle, as represented by decision block 51. If the integrator has not been reset, as represented by the &#34;NO&#34; result branch from decision block 51, the current processor 16a executes a wait loop by re-executing decision block 51. Assuming the integrator 23 has been reset, as represented by the &#34;YES&#34; result branch from decision block 51, an instruction is executed to start the A-to-D as represented by process block 52. Next the 10-bit digital value is separated from certain status information related to the A-to-D conversion and is saved as a signed value in a memory location referred to as &#34;local tmp&#34; as represented by process block 53. 
     Then a section of the program referred to as &#34;Calculate phase:&#34; is executed to calculate the average value of I FB  by dividing the current integral value by a digital value for a sample period as represented by process block 55. The digital value for the sample period is calculated by subtracting a time for starting the A-to-D conversion (&#34;sample time&#34;) from an earlier sample time that has been saved as the quantity &#34;old time&#34;, as represented by process block 54. The &#34;Calculate phase:&#34; section also includes instructions which are executed to apply the gain K I  of the current regulator Circuit 15 to the current error (I ERROR ) to develop the DC voltage to be obtained by firing the SCR&#39;s. The execution of this part of the current regulation loop is represented by process block 56. This DC voltage demand value is checked to determine whether a current loop limit has been reached, and thereafter the resulting voltage demand is converted to phase angle firing commands for the SCR&#39;s. 
     Next, the current processor 16a executes a &#34;check end stop&#34; portion of the Current Reference Module. The &#34;end stop&#34; is a period timed by a software timer during execution of the Current Reference Module. If for some reason the program does not cause the next pair of SCR&#39;s to be fired within this &#34;end stop&#34; period, the &#34;end stop&#34; timer will time out generate and an interrupt to cause the next pair of SCR&#39;s to be fired. Assuming there is sufficient time left before the &#34;end stop&#34; time-out, the current processor, 16a executes a &#34;firing pulse&#34; section of the Current Reference Module (not illustrated in FIG. 3) to set up an interrupt to re-enter the background portion (referred to as the foreground portion in Appendix A) of the program for the current processor 16a. 
     As stated earlier herein, the firing time of each pair of SCR&#39;s should be based on a current reading from the integrator circuit 23 that is as &#34;fresh&#34; as possible. Therefore, after a current integral value is read from the integrator circuit 23 and a firing time is calculated, the current processor 16a will perform another sampling cycle if there is enough time before the firing time, as represented by decision block 57. 
     Next, the current processor 16a executes a &#34;reset integrator&#34; section of the Current Reference Module to reset, the integrator circuit 23, as represented by process block 58. Instructions are executed to generate a logic low enable signal to the solid state switch 24 in FIG. 1 at a time referred to as &#34;reset time&#34;. This is followed by execution of instructions to generate a logic high disable signal to the solid state switch 24 at a time calculated by adding the integral value that was read from the integrator circuit 23 to the reset time. Execution of these two groups of instructions applies the positive reference voltage (VREF) to the inverting input (-) of the op amp 28 to discharge the capacitor 30 by the amount of the integral value read from the output of the integrator circuit 23. While this is occurring, a negative voltage representing feedback current can still be received by the integrator circuit 23 through the current path through the resistor 45 to place additional charge on the capacitor 30 to be read in the next sampling period. After executing some miscellaneous functions seen in Appendix A, the current processor 16a then returns from the Current Reference Module to other programmed routines, as represented by terminal block 59. 
     The above description has covered the details of a preferred embodiment of the invention. It will be apparent to those skilled in the art that certain modifications might be made to the details of the above circuitry to arrive at other embodiments for carrying out the invention. Therefore, to apprise the public of the range of the embodiments coming within the scope of the invention the following claims are made. ##SPC1##