Abstract:
A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for GS clamp diodes and avalanche protection for GD clamp diodes.

Description:
FIELD OF THE INVENTION  
       [0001]    This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to an improved cell configuration and processes to manufacture trench MOSFET device with Schottky rectifier, Gate-Drain (GD) and Gate-Source (GS) diodes on single chip for device shrinkage and performance improvement. 
       BACKGROUND OF THE INVENTION 
       [0002]    As shown in  FIG. 1 , normally for high efficiency DC/DC application, a Schottky rectifier is externally added in parallel with a MOSFET device to prevent a parasitic P/N body diode in the MOSFET from turning on in order to achieve higher speed and efficiency. The requirement for the clamping effect is that the forward voltage of the Schottky rectifier Vf is less than the parasitic body PN diode (˜0.7V). Besides the Schottky rectifier, a Gate-Source clamp diode with a breakdown voltage lower than the gate oxide rupture voltage of the MOSFET are provided for gate oxide ESD (electrostatic discharge) protection. Moreover, a Gate-Drain clamp diode with a breakdown voltage lower than that of the MOSFET are provided for Drain-Source avalanche protection. However, assembly of those separately structures into single package with extra interconnection wires results in higher manufacturing cost, and poor performance due to increase in inductance from the extra interconnection wires. 
         [0003]    Accordingly, it would be desirable to provide more integrated trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source diodes on single chip for device shrinkage and performance improvement. 
       SUMMARY OF THE INVENTION 
       [0004]    It is therefore an aspect of the present invention to provide improved semiconductor power device configuration and manufacture processes for providing trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source diodes on single chip so that space occupied can be reduced, and performance improved. 
         [0005]    Another aspect of the present invention is to provide improved semiconductor power device configuration and manufacture processes for providing trench MOSFET devices with embedded Schottky rectifier on single chip. 
         [0006]    Another aspect of the present invention is to provide improved semiconductor power device configuration and manufacture processes for providing trench MOSFET devices with embedded Schottky rectifier, Gate-Source diode on single chip. 
         [0007]    Another aspect of the present invention is to provide improved semiconductor power device configuration and manufacture processes for providing trench MOSFET devices with embedded Schottky rectifier, Gate-Drain diode on single chip. 
         [0008]    Another aspect of the present invention is to provide improved semiconductor power device configuration and manufacture processes for providing trench MOSFET devices with embedded Gate-Drain and Gate-Source diodes on single chip. 
         [0009]    Briefly, in a preferred embodiment, the present invention discloses a semiconductor power device comprising a trenched MOSFET with a trenched junction barrier Schottky rectifier and two diodes on single chip. The trenched junction barrier Schottky rectifier with a lower forward voltage is connected in parallel to the MOSFET as a clamp diode to prevent the parasitic PN body diode from turning on. The first Zener diode connects between a gate metal and a drain metal of said semiconductor power device functioning as a Gate-Drain (GD) clamp diode. The GD clamp diode further includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device. The second Zener diode connects between a gate metal and a source metal of the said MOSFET device for functioning as a Gate-Source clamp diode, wherein the GS clamp diode further includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having a lower breakdown voltage than a gate oxide rupture voltage of the MOSFET device. In an exemplary embodiment, the structure disclosed is the same as the structure mentioned in the first embodiment except that there is a trench Schottky diode functioning as a clamp diode in parallel to the MOSFET device with the parasitic PN body diode instead of the junction barrier Schottky rectifier. 
         [0010]    These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a conventional application circuit of the MOSFET power device with integration of Schottky rectifier, GD and GS diodes in single package. 
           [0012]      FIG. 2A  is a cross-section of an integrated trench MOSFET with embedded junction barrier Schottky rectifier, GD and GS diodes structure of the first embodiment for the present invention. The cross section location is identified with A-B line of Top View in  FIG. 2C   
           [0013]      FIG. 2B  is another cross-section of an integrated trench MOSFET with embedded junction barrier Schottky rectifier, GD and GS diodes structure of the first embodiment for the present invention. The cross section location is identified with C-D line of Top View in  FIG. 2C   
           [0014]      FIG. 2C  is a top view of an integrated trench MOSFET with embedded Schottky rectifier, GD and GS diodes structure of the first embodiment for the present invention. 
           [0015]      FIG. 3  is a normalized measurement result of the relationship between breakdown voltage and metal width cross over filed plate termination. 
           [0016]      FIG. 4A  is a cross-section of an integrated trench MOSFET with embedded trench Schottky rectifier, GD and GS diodes structure of another embodiment for the present invention. The cross section location is identified with A-B line of Top View in  FIG. 2C   
           [0017]      FIG. 4B  is another cross-section of an integrated trench MOSFET with embedded trench Schottky rectifier, GD and GS diodes structure of the second embodiment for the present invention. The cross section location is identified with C-D line of Top View in  FIG. 2C   
           [0018]      FIGS. 5A to 5D  are a serial of side cross sectional views showing the processing steps for fabricating a MOSFET device as shown in  FIG. 4A  and  FIG. 4B  of this invention. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0019]    Please refer to  FIG. 2A to 2C  for a first preferred embodiment of this invention.  FIG. 2A  is a cross-section A-B in  FIG. 2C  of this embodiment which shows a trenched MOSFET device  100  implemented with junction barrier Schottky rectifier  101 , Gate-Source polysilicon Zener clamp diodes  102  and Gate-Drain polysilicon Zener clamp diodes  103  formed in an N epitaxial layer  200  above the a heavily N+ doped substrate  201  coated with back metal of Ti/Ni/Ag  202  on rear side as drain. A trenched gate  211  surrounded by a source region  212  encompassed in a body region  213 . An oxide layer  204  covering the trenched semiconductor power device with a source-body contact trench  215  opened through and extending into the source and body regions and filled with tungsten plugs therein. A layer of Al Alloys or Copper  203  serves as source metal on an oxide layer  204  deposited along the top surface of the insulation layer  214 . The region  216  is heavily P doped to reduce the resistance between said trench contact metal plug  215  and said body region. The junction barrier Schottky contact trench  217  is formed in said N epitaxial layer with other contact trench  218  formed in the P-well  219  adjacent to said junction barrier Schottky contact trench filled with Tungsten plug connected to said source metal serving as anode of said Schottky rectifier. In order to provide the Gate-Source polysilicon Zener clamp diodes  102  and Gate-Drain polysilicon Zener clamp diodes  103 , a polysilicon layer are formed on said oxide layer  204  and doped as alternating N+ and P+ regions adjacent to each other. The N+ doped polysilicon regions  102 N 1 ,  102 N 2  and the P+ doped polysilicon region  102 P constitute the GS polysilicon Zener clamp diodes  102  while the N+ doped regions  103 N 1 ,  103 N 2  and the P+ doped polysilicon region  103 P constitute the GD polysilicon Zener clamp diodes  103 . The contact trench  220  is formed to connect the source metal with the n+ doped polysilicon region  102 N 1  of the GS polysilicon Zener clamp diodes. The contact trench  221  is formed to connect the gate metal with the n+ doped polysilicon region  102 N 2  of the GS polysilicon Zener clamp diodes. The contact trench  222  is formed to connect the gate metal with the n+ doped polysilicon region  103 NI of the GD polysilicon Zener clamp diodes. And the contact trench  223  is formed to connect the drain metal with the n+ doped polysilicon region  103 N 2  of the GD polysilicon Zener clamp diodes. Trench gates are formed underneath the contact trench  220 ,  221   222  and  223  acting as a buffer layer to avoid the zener diodes shorting with the P-body  213 . 
         [0020]      FIG. 2B  is another cross-section C-D of the first embodiment as shown in  FIG. 2C . The only difference between  FIG. 2B  and  FIG. 2A  is that there is an open area  250  of the drain metal on the top of the termination. A conventional metal field plate in the termination is provided to sustain breakdown voltage. 
         [0021]      FIG. 2C  is a top view of the first embodiment which shows Gate-Drain diode across termination with the open areas  250  in  FIG. 2B  of the drain metal. These open areas allow electrical field penetrate through the oxides during avalanche, and thus make benefits to avoid avalanche degradation caused by the metal field plate cross over the termination as shown in  FIG. 2A . 
         [0022]      FIG. 3  is a normalized measurement result of the relationship between breakdown voltage and metal width cross over metal field plate termination, which shows that breakdown voltage will be degraded when metal width W is greater than Sum, It means that electrical field underneath the cross-over metal can not effectively goes through the open area  250  if the metal width is larger than 5 um. 
         [0023]      FIG. 4A  is the cross-section A-B of the second embodiment of the present invention. The only difference between the structure of  FIG. 4A  and  FIG. 2.A  is that the embedded Schottky rectifier is a trench Schottky rectifier instead of junction barrier Schottky rectifier. The trench Schottky contact trench  272  is formed in said N epitaxial layer and other contact trench  271  formed in the trench gate  270  adjacent to said contact trench. 
         [0024]      FIG. 4B  is another cross-section C-D of the second embodiment. The only difference between  FIG. 4B  and  FIG. 4A  is that there is an open area  251  of the drain metal on the top of the termination. 
         [0025]      FIGS. 5A to 5D  are a serial of exemplary steps that are performed to form the inventive device configuration of  FIG. 4A .  FIG. 5A  shows that an N doped epitaxial layer  200  is grown on an N+ doped substrate  201 . A trench mask (not shown) is applied to open a plurality of trenches by employing a dry silicon etch process. An oxidation process is then performed to form an oxide layer  280  covering the entire structure after a sacrificial oxide is grown and removed. After the formation of the gate oxide, a doped poly is filled into the trenches and then etched back, serving as the gate material. A P-body mask is employed in the P-body Ion Implantation and followed by diffusion process to form the body region  213 , and an oxide layer  214  is grown on the top of the entire structure. 
         [0026]    In  FIG. 5B , a layer of undoped poly is deposited on the surface of the structure, and a poly mask is applied in a dry silicon etch process to form GS polysilicon Zener clamp diodes  102  and GD polysilicon Zener clamp diodes  103  after a Blank Boron Ion Implantation. Next, an N+ source mask is employed in the N+ source Ion Implantation and followed by diffusion process to form the cathodes of said Zener clamp diodes, source region  212  and N+ region  240 . 
         [0027]    In  FIG. 5C , an oxide layer is deposited to cover the entire structure, and a contact mask is employed in a dry silicon etch process. After the formation of all the contact trenches, a BF2 mask is employed in the BF2 Ion Implantation to form the more heavily doped region  216  to reduce the resistance between said trench contact metal plug and said body region. 
         [0028]    In  FIG. 5D , a layer of Ti/TiN, Co/TiN or Mo/TiN (not shown) is deposited along the sidewall of each trench. To fill the contact trenches, tungsten is deposited serving as plug metal followed by a CMP process. Last, a metal mask is employed in the deposition process to form a layer of front metal of Al Alloys  203  above the entire structure. 
         [0029]    Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.