Abstract:
A semiconductor memory device includes a plurality of memory cell columns each having a plurality of memory cells, each memory cell including being a static type, a plurality of local bit lines connected to the memory cell columns, a global bit line connected to the local bit lines via a plurality of sense amplifiers, a measurement terminal to which a measurement voltage is applied in a cell current measurement mode, and a plurality of switching circuits provided to correspond to the local bit lines, and configured to electrically connect the measurement terminal and one of the local bit lines in the cell current measurement mode.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-324991, filed Nov. 30, 2006, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor memory device, e.g., a static random access memory (SRAM). 
         [0004]    2. Description of the Related Art 
         [0005]    In recent SRAMs, the scaling of the cell size is advancing with the development of the micropatterning technique, and a read current per memory cell is lowering accordingly. In addition, the variation in cell current amount is increasing due to the increase in memory capacity and processing variations. Consequently, a memory cell having the smallest cell current of all memory cells makes it difficult to increase the operating speed of the SRAM. Under the circumstances, the importance of a method of accurately measuring the cell current of a fabricated memory cell is increasing in order to analyze defects and manage production lines. 
         [0006]    On the other hand, an SRAM having a hierarchical bit line structure capable of data read with a small cell current has been developed. The hierarchical bit line structure is a circuit system in which a bit line comprises a local bit line and global bit line. The local bit line is connected to a local sense amplifier and local write driver. The global bit line is connected to a global sense amplifier and global write driver. 
         [0007]    More specifically, a plurality of local bit lines whose bit line capacitance is reduced by finely dividing a bit line are connected to a plurality of local sense amplifiers. The local sense amplifier amplifies data and sends the amplified data to the global bit line. The global sense amplifier connected to the global bit line determines the data. That is, cell data is read out by the two stages of bit lines/sense amplifiers. By thus hierarchizing the bit lines, the capacitance of each bit line can be reduced, and this makes it possible to reduce the cell current. 
         [0008]    In this hierarchical bit line type SRAM, a method that outputs the cell current to a pad by selecting a local bit line and global bit line by column switches is conventionally used as a method of directly measuring the cell current. In this method, however, a cell current flowing through only the local bit line is output outside via the global bit line and a few column switch stages. Therefore, the parasitic resistances and leakage noise of the global bit line and column switches interfere with accurate cell current measurement. 
         [0009]    As a related technique of this kind, a technique that suppresses the increase in chip size by using one cell current monitoring bus is disclosed (Jpn. Pat. Appln. KOKAI Publication No. 10-241400). 
       BRIEF SUMMARY OF THE INVENTION 
       [0010]    According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cell columns each having a plurality of memory cells, each memory cell including a plurality of MIS (Metal Insulator Semiconductor) transistors and being a static type; a plurality of local bit lines connected to the memory cell columns, respectively; a global bit line connected to the local bit lines via a plurality of sense amplifiers; a measurement terminal to which a measurement voltage is applied in a cell current measurement mode; and a plurality of switching circuits provided to correspond to the local bit lines, and configured to electrically connect the measurement terminal and one of the local bit lines in the cell current measurement mode. 
         [0011]    According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of blocks each having a plurality of memory cell columns, each memory cell column having a plurality of memory cells, and each memory cell including a plurality of MIS transistors and being a static type; a plurality of local bit lines connected to the memory cell columns, respectively; a plurality of intermediate lines provided to correspond to the blocks, each intermediate line being connected to the local bit lines via a plurality of column switches; a global bit line connected to the intermediate lines via a plurality of sense amplifiers; a measurement terminal to which a measurement voltage is applied in a cell current measurement mode; and a plurality of switching circuits provided to correspond to the intermediate lines, and configured to electrically connect the measurement terminal and one of the intermediate lines in the cell current measurement mode. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0012]      FIG. 1  is a schematic view illustrating the arrangement of an SRAM according to the first embodiment of the present invention; 
           [0013]      FIG. 2  is a circuit diagram mainly illustrating a pair of global bit lines GBL and /GBL and a pair of local bit lines LBL and /LBL corresponding to the global bit line pair in the SRAM shown in  FIG. 1 ; 
           [0014]      FIG. 3  is a schematic view illustrating the arrangement of an SRAM according to the second embodiment of the present invention; 
           [0015]      FIG. 4  is a circuit diagram mainly illustrating a pair of global bit lines GBL and /GBL and a plurality of pairs of local bit lines LBL and /LBL corresponding to the global bit line pair in the SRAM shown in  FIG. 3 ; 
           [0016]      FIG. 5  is a schematic view illustrating the arrangement of an SRAM according to the third embodiment of the present invention; 
           [0017]      FIG. 6  is a circuit diagram illustrating an example of a selection circuit  22  shown in  FIG. 5 ; 
           [0018]      FIG. 7  is a circuit diagram mainly illustrating a pair of global bit lines GBL and /GBL and a plurality of pairs of local bit lines LBL and /LBL corresponding to the global bit line pair in the SRAM shown in  FIG. 5 ; 
           [0019]      FIG. 8  is a circuit diagram illustrating an example of a signal generator A 1  shown in  FIG. 7 ; 
           [0020]      FIG. 9  is a circuit diagram illustrating an example of a signal generator A 2  shown in  FIG. 7 ; 
           [0021]      FIG. 10  is a circuit diagram illustrating an example of a signal generator B 1  shown in  FIG. 7 ; 
           [0022]      FIG. 11  is a circuit diagram illustrating an example of a signal generator B 2  shown in  FIG. 7 ; and 
           [0023]      FIG. 12  is a view illustrating a truth table of output signals OUT_A 1  to OUT_B 2 , a selection signal Mcellon, and a precharge signal /PRE_LBL. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0024]    Embodiments of the present invention will be explained below with reference to the accompanying drawing. Note that in the following explanation, the same reference numerals denote elements having the same functions and arrangements, and a repetitive explanation will be made only when necessary. 
       First Embodiment 
       [0025]      FIG. 1  is a schematic view illustrating the arrangement of an SRAM according to the first embodiment of the present invention. This SRAM comprises blocks BLK&lt; 0 &gt; to BLK&lt;j&gt;. The blocks BLK&lt; 0 &gt; to BLK&lt;j&gt; are sequentially arranged adjacent to each other in the column direction. Each block BLK includes subarrays  11 - 0  to  11 - i . The subarrays  11 - 0  to  11 - i  are sequentially arranged adjacent to each other in the row direction. Each subarray  11  includes static memory cells MC. 
         [0026]    The SRAM of this embodiment has a hierarchical bit line structure. Also, the SRAM of this embodiment is an example of the arrangement of an SRAM in which a global bit line GBL and a local bit line LBL connected to the global bit line GBL are “1:1” in each block BLK. 
         [0027]    More specifically, each subarray  11  has (h+1) pairs of global bit lines GBL&lt; 0 &gt; to GBL&lt;h&gt; and /GBL&lt; 0 &gt; to /GBL&lt;h&gt;. The blocks BLK&lt; 0 &gt; to BLK&lt;j&gt; share the pairs of global bit lines GBL&lt; 0 &gt; to GBL&lt;h&gt; and /GBL&lt; 0 &gt; to /GBL&lt;h&gt;. That is, (j+1) subarrays  11  adjacent to each other in the column direction have the (h+1) pairs of global bit lines GBL&lt; 0 &gt; to GBL&lt;h&gt; and /GBL&lt; 0 &gt; to /GBL&lt;h&gt; to be shared by these subarrays. 
         [0028]    In each block BLK, each pair of global bit lines GBL and /GBL are connected to a pair of local bit lines LBL and /LBL via a local sense amplifier (LSA)/local write driver (LWD)  12 . Also, each block BLK has word lines WL running in the row direction. The subarrays  11  included in the block BLK share the word lines WL. 
         [0029]    The global bit lines GBL&lt; 0 &gt; to GBL&lt;h&gt; are connected to a column switch  14  via column switches  13 . Similarly, the global bit lines /GBL&lt; 0 &gt; to /GBL&lt;h&gt; are connected to a column switch  14  via column switches  13 . Each column switch  14  is connected to a global sense amplifier (GSA)/global write driver (GWD)  15 . That is, the pairs of global bit lines GBL and /GBL formed in each subarray  11  of the block BLK are bundled by the column switches  14  and connected to the GSA/GWD  15 . This similarly applies to global bit lines formed on other subarrays. 
         [0030]    The GSA/GWD  15  is connected to an input/output terminal  16 . Externally input data is supplied to the GSA/GWD  15  via the input/output terminal (I/O)  16 . Output data is output outside via the input/output terminal (I/O)  16 . 
         [0031]    The GSA/GWD  15  (more specifically, the GWD) writes externally input data (corresponding to write data). Also, the GSA/GWD  15  (more specifically, the GSA) reads (senses and amplifies) data transferred from the pairs of bit lines LBL and /LBL. 
         [0032]    The LSA/LWD  12  (more specifically, the LWD) writes data transferred from the pair of bit lines GBL and /GBL. The LSA/LWD  12  (more specifically, the LSA) reads data transferred from the memory cells MC. 
         [0033]    The word lines WL are connected to a row decoder  17 . On the basis of an externally supplied row address signal, the row decoder  17  selects a corresponding one of the word lines WL. 
         [0034]    All the column switches  13  and  14  are connected to a column decoder  18 . On the basis of an externally supplied column address signal, the column decoder  18  controls ON/OFF of the column switches  13  and  14 . That is, on the basis of the column address signal, the column decoder  18  selects a corresponding one of the pairs of global bit lines GBL and /GBL. 
         [0035]    A main controller  19  controls the individual circuits in the SRAM. The main controller  19  receives clock signals, control signals, and the like from external circuits. On the basis of these control signals, the main controller  19  controls, e.g., a precharge operation, write operation, and read operation. 
         [0036]    The SRAM has a measurement terminal  20  as an external power supply terminal to which a measurement voltage Vm used to measure the cell current of a memory cell is supplied. The measurement terminal  20  is connected to each subarray  11  via a power line  21 . 
         [0037]    The SRAM includes a selection circuit  22  that generates a selection signal Mcellon for selecting a block BLK as an object of cell current measurement. A measurement mode signal Mcell for measuring the cell current is externally input to the selection circuit  22 . In addition, the main controller  19  supplies block selection signals SBLK&lt; 0 &gt; to SBLK&lt;j&gt; to the selection circuit  22 . The main controller  19  generates the block selection signal SBLK on the basis of a row address signal and column address signal input from the outside. 
         [0038]    The selection circuit  22  generates the selection signal Mcellon on the basis of the measurement mode signal Mcell and block selection signal SBLK. More specifically, the selection circuit  22  comprises NAND circuits  22 - 0  to  22 - j  corresponding to the (j+1) blocks BLK. Each of the NAND circuits  22 - 0  to  22 - j  receives a corresponding one of the block selection signals SBLK&lt; 0 &gt; to SBLK&lt;j&gt; at one input terminal. Each of the NAND circuits  22 - 0  to  22 - j  receives the measurement mode signal Mcell at the other input terminal. In a cell current measurement mode (when the measurement mode signal Mcell is at high level), therefore, the selection circuit  22  selects a block BLK as an object of cell current measurement. 
         [0039]      FIG. 2  is a circuit diagram mainly illustrating a pair of global bit lines GBL and /GBL and a pair of local bit lines LBL and /LBL corresponding to the global bit line pair. Assume that a given block BLK&lt;k&gt; includes the pair of local bit lines LBL and /LBL shown in  FIG. 2 . 
         [0040]    The pair of local bit lines LBL and /LBL are connected to the memory cells MC arranged in the column direction. Each memory cell MC includes a first inverter circuit INV 1  and second inverter circuit INV 2 . 
         [0041]    The first inverter circuit INV 1  comprises a p-channel MOS transistor (PMOS transistor) LD 1  as a load, and an n-channel MOS transistor (NMOS transistor) DV 1  for driving. Note that this embodiment uses a MOS (Metal Oxide Semiconductor) transistor that is a kind of a MIS (Metal Insulator Semiconductor) transistor. The PMOS transistor LD 1  and NMOS transistor DV 1  are connected in series between a power supply terminal to which a power supply voltage VDD is supplied, and a ground terminal to which a ground voltage VSS is supplied. 
         [0042]    The second inverter circuit INV 2  comprises a PMOS transistor LD 2  as a load and an NMOS transistor DV 2  for driving. The PMOS transistor LD 2  and NMOS transistor DV 2  are connected in series between the power supply terminal to which the power supply voltage VDD is supplied, and the ground terminal. 
         [0043]    More specifically, the source terminal of the PMOS transistor LD 1  is connected to the power supply terminal. The drain terminal of the PMOS transistor LD 1  is connected to the drain terminal of the NMOS transistor DV 1  via a memory node N 1 . The gate terminal of the PMOS transistor LD 1  is connected to the gate terminal of the NMOS transistor DV 1 . The source terminal of the NMOS transistor DV 1  is connected to the ground terminal. 
         [0044]    The source terminal of the PMOS transistor LD 2  is connected to the power supply terminal. The drain terminal of the PMOS transistor LD 2  is connected to the drain terminal of the NMOS transistor DV 2  via a memory node N 2 . The gate terminal of the PMOS transistor LD 2  is connected to the gate terminal of the NMOS transistor DV 2 . The source terminal of the NMOS transistor DV 2  is connected to the ground terminal. 
         [0045]    The gate terminal of the PMOS transistor LD 1  is connected to the memory node N 2 . The gate terminal of the PMOS transistor LD 2  is connected to the memory node N 1 . In other words, the first inverter circuit INV 1  and second inverter circuit INV 2  are connected by cross coupling. That is, the output terminal of the first inverter circuit INV 1  is connected to the input terminal of the second inverter circuit INV 2 , and the output terminal of the second inverter circuit INV 2  is connected to the input terminal of the first inverter circuit INV 1 . 
         [0046]    The memory node N 1  is connected to the local bit line LBL via a transfer gate XF 1  that is an NMOS transistor. The gate terminal of the transfer gate XF 1  is connected to the word line WL. 
         [0047]    The memory node N 2  is connected to the local bit line /LBL via a transfer gate XF 2  that is an NMOS transistor. The gate terminal of the transfer gate XF 2  is connected to the word line WL. The memory cell MC is constructed as described above. 
         [0048]    The pair of local bit lines LBL and /LBL are connected to a precharge circuit  31 . The precharge circuit  31  precharges the pair of local bit lines LBL and /LBL to a high-level voltage (e.g., the power supply voltage VDD) before read and write operations are executed. The precharge circuit  31  executes this precharge operation on the basis of a precharge signal /PRE supplied from the main controller  19 . That is, the precharge circuit  31  precharges the pair of local bit lines LBL and /LBL to the power supply voltage VDD when the precharge signal /PRE is activated (to low level), and cancels precharging when the precharge signal /PRE is deactivated (to high level). 
         [0049]    The precharge circuit  31  includes two PMOS transistors  31 A and  31 B. The source terminal of the PMOS transistor  31 A is connected to a power supply terminal to which the power supply voltage VDD is supplied. The drain terminal of the PMOS transistor  31 A is connected to the local bit line LBL. The precharge signal /PRE is supplied to the gate terminal of the PMOS transistor  31 A. 
         [0050]    The source terminal of the PMOS transistor  31 B is connected to a power supply terminal to which the power supply voltage VDD is supplied. The drain terminal of the PMOS transistor  31 B is connected to the local bit line /LBL. The precharge signal /PRE is supplied to the gate terminal of the PMOS transistor  31 B. The precharge circuit  31  is constructed as described above. 
         [0051]    Each of all the pairs of local bit lines LBL and /LBL is connected to a measurement switching circuit  32  used to measure the cell current. The measurement switching circuit  32  comprises four PMOS transistors  32 - 1  to  32 - 4 . The PMOS transistor  32 - 3  controlled by the selection signal Mcellon and the PMOS transistor  32 - 1  controlled by the potential of the global bit line GBL are connected in series, and this series circuit connects the local bit line LBL and power line  21 . Likewise, the PMOS transistor  32 - 4  controlled by the selection signal Mcellon and the PMOS transistor  32 - 2  controlled by the potential of the global bit line /GBL are connected in series, and this series circuit connects the local bit line /LBL and power line  21 . 
         [0052]    More specifically, the source terminal of the PMOS transistor  32 - 1  is connected to the power line  21 . The gate terminal of the PMOS transistor  32 - 1  is connected to the global bit line GBL. The drain terminal of the PMOS transistor  32 - 1  is connected to the source terminal of the PMOS transistor  32 - 3 . A selection signal Mcellon&lt;k&gt; is supplied to the gate terminal of the PMOS transistor  32 - 3 . The drain terminal of the PMOS transistor  32 - 3  is connected to the local bit line LBL. 
         [0053]    The source terminal of the PMOS transistor  32 - 2  is connected to the power line  21 . The gate terminal of the PMOS transistor  32 - 2  is connected to the global bit line /GBL. The drain terminal of the PMOS transistor  32 - 2  is connected to the source terminal of the PMOS transistor  32 - 4 . The selection signal Mcellon&lt;k&gt; is supplied to the gate terminal of the PMOS transistor  32 - 4 . The drain terminal of the PMOS transistor  32 - 4  is connected to the local bit line /LBL. 
         [0054]    The operation of the SRAM constructed as above will be explained below. In normal operations (read and write operations except for the cell current measurement mode) of the SRAM, the measurement mode signal Mcell is deactivated (to low level). Accordingly, the selection circuit  22  outputs high-level selection signals Mcellon&lt; 0 &gt; to Mcellon&lt;j&gt;. In this state, the PMOS transistors  32 - 3  and  32 - 4  included in all the measurement switching circuits  32  are turned off. This electrically disconnects the pairs of local bit lines LBL and /LBL from the power line  21 . Consequently, the measurement voltage Vm is not transmitted to the pairs of local bit lines LBL and /LBL regardless of the states of the pairs of global bit lines GBL and /GBL. Therefore, normal read and write operations can be performed in the normal operation mode. 
         [0055]    The cell current measurement mode for measuring the cell current of a given memory cell MC will now be explained. Assume that, in the memory cell MC (measurement cell) as an object of measurement, data “0” is written in the memory node N 1  on the side of the local bit line LBL, and data “1” is written in the memory node N 2  on the side of the local bit line /LBL. 
         [0056]    First, the measurement mode signal Mcell is activated (to high level). Subsequently, the block selection signal SBLK of the block BLK including the measurement cell is activated (to high level). Accordingly, the selection circuit  22  activates only the selection signal Mcellon of the selected block BLK (to low level). Simultaneously, data “0” is input to the global bit line GBL to which the measurement cell is connected (this global bit line is set at a low-level voltage), and data “1” is input to all the other global bit lines GBL and /GBL (these global bit lines are set at a high-level voltage). 
         [0057]    In this state, only the local bit line LBL connected to the measurement cell is connected to the power line  21 . When the word line WL connected to the measurement cell is activated in this state, a current path is formed from the power line  21  to the ground terminal via the measurement cell. A cell current corresponding to the measurement voltage Vm at that time is measured via the measurement terminal  20 . 
         [0058]    Note that when measuring the cell current of a measurement cell storing opposite data (a measurement cell in which data “1” is written in the memory node N 1  on the side of the local bit line LBL), opposite data need only be set in the global bit lines GBL and /GBL. 
         [0059]    In this embodiment as described in detail above, the current path formed from the power line  21  to the ground terminal via the measurement cell includes neither global bit lines nor column switches. Since this protects the measurement cell from the influence of the parasitic resistances and leakage noise of the global bit lines and column switches, the cell current can be measured with high accuracy. 
         [0060]    Also, the power line  21  can be formed above the memory cells MC by using a thick line in an upper layer. Since this makes it possible to reduce the parasitic resistance and leakage noise of the power line  21 , the cell current can be measured with high accuracy. 
         [0061]    Furthermore, in this embodiment, the increase in area caused by the addition of the measurement switching circuit  32  is about 3% when the local bit line length is 128 bits cell/LBL and the memory capacity is 1 Mbits. Accordingly, the increase in area of an SRAM can be decreased when this embodiment is applied. 
         [0062]    Note that it is not always necessary to newly form the measurement terminal  20 . That is, an external power supply terminal to which a bit line voltage VBL (more specifically, the high-level voltage of the local bit line LBL) is supplied may also be used as the measurement terminal  20 . In this case, the power line  21  is a VBL line. The embodiment can be similarly practiced even when constructed in this way. 
       Second Embodiment 
       [0063]    The second embodiment is an example of the arrangement of an SRAM in which a plurality of local bit lines LBL are connected to one global bit line GBL in each block BLK. 
         [0064]      FIG. 3  is a schematic view illustrating the arrangement of the SRAM according to the second embodiment. The SRAM comprises blocks BLK&lt; 0 &gt; to BLK&lt;j&gt;. The blocks BLK&lt; 0 &gt; to BLK&lt;j&gt; are sequentially arranged adjacent to each other in the column direction. Each block BLK includes subarrays  11 - 0  to  11 - i . The subarrays  11 - 0  to  11 - i  are sequentially arranged adjacent to each other in the row direction. 
         [0065]    The SRAM of this embodiment has a hierarchical bit line structure. Also, the SRAM of this embodiment is an example of the arrangement of an SRAM in which a global bit line GBL and local bit lines LBL connected to the global bit line GBL are “1:n (n is an integer of 2 or more)” in each block BLK. 
         [0066]    More specifically, each subarray  11  has (h+1) pairs of global bit lines GBL&lt; 0 &gt; to GBL&lt;h&gt; and /GBL&lt; 0 &gt; to /GBL&lt;h&gt;. The blocks BLK&lt; 0 &gt; to BLK&lt;j&gt; share the pairs of global bit lines GBL&lt; 0 &gt; to GBL&lt;h&gt; and /GBL&lt; 0 &gt; to /GBL&lt;h&gt;. In addition, (m+1) pairs of local bit lines LBL&lt; 0 &gt; to LBL&lt;m&gt; and /LBL&lt; 0 &gt; to /LBL&lt;m&gt; are connected to each pair of global bit lines GBL and /GBL via an LSA/LWD  12 . 
         [0067]    The (m+1) pairs of local bit lines LBL and /LBL are connected to the LSA/LWD  12  via column switches  41 . All the column switches  41  are connected to a column decoder  18 . The column decoder  18  controls ON/OFF of the column switches  41  on the basis of a column address signal. That is, on the basis of the column address signal, the column decoder  18  selects a corresponding one of the pairs of local bit lines LBL and /LBL. 
         [0068]      FIG. 4  is a circuit diagram mainly illustrating a pair of global bit lines GBL and /GBL and pairs of local bit lines LBL and /LBL corresponding to the global bit line pair. Assume that a given block BLK&lt;k&gt; includes the pairs of local bit lines LBL and /LBL shown in  FIG. 4 . 
         [0069]    The pair of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; are connected to memory cells MC arranged in the column direction. The arrangement of each memory cell MC is the same as in the first embodiment. The pair of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; are connected to a precharge circuit  31 - 0  for the pair of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt;. 
         [0070]    A main controller  19  supplies a precharge signal /PRE_LBL to the gate terminals of two PMOS transistors  31 A and  31 B forming the precharge circuit  31 - 0 . On the basis of the precharge signal /PRE_LBL, the precharge circuit  31 - 0  precharges the pair of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; to a high-level voltage (e.g., a power supply voltage VDD) before read and write operations are executed. The local bit lines LBL&lt; 1 &gt; to LBL&lt;m&gt; have the same arrangement as that of the pair of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt;. 
         [0071]    The pairs of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; to LBL&lt;m&gt; and /LBL&lt;m&gt; are connected to a pair of intermediate lines INL and /INL via the column switches  41 . The pair of intermediate lines INL and /INL are connected to the pair of global lines GBL and /GBL via the LSA/LWD  12 . When the column decoder  18  controls ON/OFF of the column switches  41  on the basis of the column address signal, one of the pairs of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; to LBL&lt;m&gt; and /LBL&lt;m&gt; is connected to the pair of global bit lines GBL and /GBL via the pair of intermediate lines INL and /INL. 
         [0072]    The pair of intermediate lines INL and /INL are connected to a precharge circuit  42  for a local sense amplifier (LSA). The precharge circuit  42  comprises two PMOS transistors  42 A and  42 B. The source terminals of the PMOS transistors  42 A and  42 B are connected to a power supply terminal to which the power supply voltage VDD is supplied. The drain terminals of the PMOS transistors  42 A and  42 B are respectively connected to the intermediate lines INL and /INL. The main controller  19  supplies a precharge signal /PRE_LSA to the gate terminals of the PMOS transistors  42 A and  42 B. On the basis of the precharge signal /PRE_LSA, the precharge circuit  42  precharges the pair of local bit lines LBL and /LBL to the high-level voltage (e.g., the power supply voltage VDD) before read and write operations are executed. 
         [0073]    Also, the pair of intermediate lines INL and /INL are connected to a measurement switching circuit  32  used to measure the cell current. The measurement switching circuit  32  comprises four PMOS transistors  32 - 1  to  32 - 4 . The PMOS transistor  32 - 3  controlled by a selection signal Mcellon and the PMOS transistor  32 - 1  controlled by the potential of the global bit line GBL are connected in series, and this series circuit connects the intermediate line INL and a power line  21 . Likewise, the PMOS transistor  32 - 4  controlled by the selection signal Mcellon and the PMOS transistor  32 - 2  controlled by the potential of the global bit line /GBL are connected in series, and this series circuit connects the intermediate line /INL and power line  21 . 
         [0074]    More specifically, the source terminal of the PMOS transistor  32 - 1  is connected to the power line  21 . The gate terminal of the PMOS transistor  32 - 1  is connected to the global bit line GBL. The drain terminal of the PMOS transistor  32 - 1  is connected to the source terminal of the PMOS transistor  32 - 3 . A selection signal Mcellon&lt;k&gt; is supplied to the gate terminal of the PMOS transistor  32 - 3 . The drain terminal of the PMOS transistor  32 - 3  is connected to the intermediate line INL. 
         [0075]    The source terminal of the PMOS transistor  32 - 2  is connected to the power line  21 . The gate terminal of the PMOS transistor  32 - 2  is connected to the global bit line /GBL. The drain terminal of the PMOS transistor  32 - 2  is connected to the source terminal of the PMOS transistor  32 - 4 . The selection signal Mcellon&lt;k&gt; is supplied to the gate terminal of the PMOS transistor  32 - 4 . The drain terminal of the PMOS transistor  32 - 4  is connected to the intermediate line /INL. 
         [0076]    The operation of the SRAM constructed as above will be explained below. In normal operations (read and write operations except for a cell current measurement mode) of the SRAM, a measurement mode signal Mcell is deactivated (to low level). Accordingly, a selection circuit  22  outputs high-level selection signals Mcellon&lt; 0 &gt; to Mcellon&lt;j&gt;. In this state, the PMOS transistors  32 - 3  and  32 - 4  included in all the measurement switching circuits  32  are turned off. This electrically disconnects the pair of intermediate lines INL and /INL from the power line  21 . Consequently, a measurement voltage Vm is not transmitted to the pair of intermediate lines INL and /INL regardless of the states of the pairs of global bit lines GBL and /GBL. Therefore, normal read and write operations can be performed in the normal operation mode. 
         [0077]    The cell current measurement mode for measuring the cell current of a given memory cell MC will now be explained. Assume that, in the memory cell MC (measurement cell) as an object of measurement, data “0” is written in a memory node N 1  on the side of the local bit line LBL, and data “1” is written in a memory node N 2  on the side of the local bit line /LBL. 
         [0078]    First, the measurement mode signal Mcell is activated (to high level). Subsequently, a block selection signal SBLK of the block BLK including the measurement cell is activated (to high level). Accordingly, the selection circuit  22  activates only the selection signal Mcellon of the selected block BLK (to low level). Simultaneously, data “0” is input to the global bit line GBL to which the measurement cell is connected (this global bit line is set at a low-level voltage), and data “1” is input to all the other global bit lines GBL and /GBL (these global bit lines are set at a high-level voltage). Consequently, only the intermediate line INL connected to the measurement cell is connected to the power line  21 . 
         [0079]    Subsequently, the column decoder  18  turns on two column switches  41  corresponding to the pair of local bit lines LBL and /LBL connected to the measurement cell. When a word line WL connected to the measurement cell is activated in this state, a current path is formed from the power line  21  to the ground terminal via the measurement cell. A cell current corresponding to the measurement voltage Vm at that time is measured via the measurement terminal  20 . 
         [0080]    Note that when measuring the cell current of a measurement cell storing opposite data (a measurement cell in which data “1” is written in the memory node N 1  on the side of the local bit line LBL), opposite data need only be set in the global bit lines GBL and /GBL. 
         [0081]    In the SRAM constructed as above, the pair of local bit lines LBL and /LBL connected to the measurement cell are connected to the intermediate lines INL and /INL via the column switches  41 . In the SRAM of this embodiment, therefore, the cell current of the measurement cell can be measured via the measurement terminal  20  by executing the cell current measurement operation explained in the first embodiment. 
         [0082]    Also, this embodiment can measure the cell current with high accuracy by using the measurement terminal  20  even when the SRAM is constructed such that a plurality of local bit lines LBL are connected to one global bit line GBL. 
         [0083]    Furthermore, one measurement switching circuit  32  need only be prepared for a plurality of pairs of local bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; to LBL&lt;m&gt; and /LBL&lt;m&gt;. This makes it possible to decrease the ratio occupied by the measurement switching circuits  32  in the area of the SRAM. 
       Third Embodiment 
       [0084]    The third embodiment measures the cell current with high accuracy by reducing the leakage current of an unselected local bit line LBL in cell current measurement. 
         [0085]      FIG. 5  is a schematic view illustrating the arrangement of an SRAM according to the third embodiment of the present invention. Similar to the second embodiment, the SRAM of this embodiment is an example of the arrangement of an SRAM in which a global bit line GBL and local bit lines LBL connected to the global bit line GBL are “1:n (n is an integer of 2 or more)” in each block BLK. 
         [0086]    The SRAM has a selection circuit  22 . The selection circuit  22  receives a measurement mode signal Mcell from the outside. The measurement mode signal Mcell is activated (to high level) in a cell current measurement mode, and deactivated (to low level) in normal operations. Also, a main controller  19  supplies a precharge signal PRE_LSA for a local sense amplifier (LSA) and block selection signals SBLK&lt; 0 &gt; to SBLK&lt;j&gt; to the selection circuit  22 . The precharge signal PRE_LSA is deactivated (to low level) in read and write operations, and activated (to high level) in operations except for read and write. 
         [0087]    By using the above signals, the selection circuit  22  supplies selection signals Mcellon&lt; 0 &gt; to Mcellon&lt;j&gt; and precharge signals PRE_LSA&lt; 0 &gt; to PRE_LSA&lt;j&gt; to blocks BLK&lt; 0 &gt; to BLK&lt;j&gt;, respectively.  FIG. 6  is a circuit diagram illustrating an example of the selection circuit  22 . Note that  FIG. 6  shows a circuit portion for generating a selection signal Mcellon&lt;k&gt; and precharge signal PRE_LSA&lt;k&gt; to be supplied to a given block BLK&lt;k&gt;. In practice, therefore, the selection circuit  22  includes circuit portions shown in  FIG. 6  equal in number to the blocks BLK&lt; 0 &gt; to BLK&lt;j&gt;. 
         [0088]    The selection circuit  22  comprises three NAND circuits  22 A to  22 C and three inverter circuits  22 D to  22 F. The NAND circuit  22 A receives the measurement mode signal Mcell at one input terminal. The NAND circuit  22 A receives a block selection signal SBLK&lt;k&gt; at the other input terminal. The output terminal of the NAND circuit  22 A is connected to the input terminal of the inverter circuit  22 D, and one input terminal of the NAND circuit  22 C. The inverter circuit  22 D outputs a selection signal Mcellon&lt;k&gt;. Accordingly, the selection signal Mcellon&lt;k&gt; is activated (to high level) when the cell current measurement mode is set (the measurement mode signal Mcell is at high level) and the block BLK&lt;k&gt; is selected (the block selection signal SBLK&lt;k&gt; is at high level). 
         [0089]    The NAND circuit  22 B receives the measurement mode signal Mcell at one input terminal via the inverter circuit  22 E. The NAND circuit  22 B receives the precharge signal PRE_LSA at the other input terminal. The output terminal of the NAND circuit  22 B is connected to the other input terminal of the NAND circuit  22 C via the inverter circuit  22 F. The NAND circuit  22 C outputs a precharge signal PRE_LSA&lt;k&gt;. Accordingly, the precharge signal PRE_LSA&lt;k&gt; is activated (to high level) when the precharge signal PRE_LSA is at high level and the selection signal Mcellon&lt;k&gt; is at low level (the block selection signal SBLK&lt;k&gt; is at low level). 
         [0090]      FIG. 7  is a circuit diagram mainly illustrating a pair of global bit lines GBL and /GBL and pairs of local bit lines LBL and /LBL connected to the pair of global bit lines GBL and /GBL. Assume that a given block BLK&lt;k&gt; includes the pairs of local bit lines LBL and /LBL shown in  FIG. 7 . 
         [0091]    A pair of intermediate lines INL and /INL are connected to a measurement switching circuit  32  to be used to measure the cell current. The measurement switching circuit  32  comprises two PMOS transistors  32 - 1  and  32 - 2  and two signal generators A 1  and A 2 . The PMOS transistor  32 - 1  is connected in series between the intermediate line INL and a power line  21 . The PMOS transistor  32 - 2  is connected in series between the intermediate line /INL and power line  21 . 
         [0092]      FIG. 8  is a circuit diagram illustrating an example of the signal generator A 1  shown in  FIG. 7 . The signal generator A 1  comprises a NOR circuit  51 B and two inverter circuits  51 A and  51 C. The NOR circuit  51 B receives the selection signal Mcellon&lt;k&gt; at one input terminal via the inverter circuit  51 A. The other input terminal of the NOR circuit  51 B is connected to the global bit line GBL. The output terminal of the NOR circuit  51 B is connected to the input terminal of the inverter circuit  51 A. The inverter circuit  51 A outputs an output signal OUT_A 1 . 
         [0093]      FIG. 9  is a circuit diagram illustrating an example of the signal generator A 2  shown in  FIG. 7 . The signal generator A 2  comprises a NOR circuit  52 B and two inverter circuits  52 A and  52 C. The NOR circuit  52 B receives the selection signal Mcellon&lt;k&gt; at one input terminal via the inverter circuit  52 A. The other input terminal of the NOR circuit  52 B is connected to the global bit line /GBL. The output terminal of the NOR circuit  52 B is connected to the input terminal of the inverter circuit  52 C. The inverter circuit  52 C outputs an output signal OUT_A 2 . 
         [0094]    Also, the pair of intermediate lines INL and /INL are connected to a precharge circuit  42  for a local sense amplifier (LSA). The precharge circuit  42  comprises two PMOS transistors  42 A and  42 B and two signal generators B 1  and B 2 . The PMOS transistor  42 A is connected in series between a power supply terminal to which a power supply voltage VDD is supplied and the intermediate line INL. The PMOS transistor  42 B is connected in series between a power supply terminal to which the power supply voltage VDD is supplied and the intermediate line /INL. 
         [0095]      FIG. 10  is a circuit diagram illustrating an example of the signal generator B 1  shown in  FIG. 7 . The signal generator B 1  comprises an inverter circuit  53 A and two NAND circuits  53 B and  53 C. The NAND circuit  53 B receives the selection signal Mcellon&lt;k&gt; at one input terminal. The other input terminal of the NAND circuit  53 B is connected to the global bit line GBL via the inverter circuit  53 A. The output terminal of the NAND circuit  53 B is connected to one input terminal of the NAND circuit  53 C. The NAND circuit  53 C receives the precharge signal PRE_LSA&lt;k&gt; at the other input terminal. The NAND circuit  53 C outputs an output signal OUT_B 1 . 
         [0096]      FIG. 11  is a circuit diagram illustrating an example of the signal generator B 2  shown in  FIG. 7 . The signal generator B 2  comprises an inverter circuit  54 A and two NAND circuits  54 B and  54 C. The NAND circuit  54 B receives the selection signal Mcellon&lt;k&gt; at one input terminal. The other input terminal of the NAND circuit  54 B is connected to the global bit line /GBL via the inverter circuit  54 A. The output terminal of the NAND circuit  54 B is connected to one input terminal of the NAND circuit  54 C. The NAND circuit  54 C receives the precharge signal PRE_LSA&lt;k&gt; at the other input terminal. The NAND circuit  54 C outputs an output signal OUT_B 2 . 
         [0097]    The operation of the SRAM constructed as above will be explained below.  FIG. 12  is a view illustrating a truth table of the output signals OUT_A 1  to OUT_B 2 , the selection signal Mcellon, and a precharge signal /PRE_LBL. Note that “Selected LSA” shown in  FIG. 12  indicates a local sense amplifier LSA included in a block selected by the block selection signal SBLK and connected to the pair of global bit lines GBL and /GBL selected by a column decoder  18 , and indicates the pair of intermediate lines INL and /INL connected to this LSA. “Unselected LSA” shown in  FIG. 12  indicates a local sense amplifier LSA except for the selected LSA (and the pair of intermediate lines INL and /INL connected to this LSA). 
         [0098]    In normal operations, the output signals OUT_A 1  and OUT_A 2  are at high level (H) and the PMOS transistors  32 - 1  and  32 - 2  for cell current measurement are OFF in both the selected LSA and unselected LSA. On the other hand, the PMOS transistors  42 A and  42 B for precharge controlled by the output signals OUT_B 1  and OUT_B 2  execute the operation of precharging the pair of local bit lines LBL and /LBL in accordance with the inverted signal /PRE_LSA of the precharge signal PRE_LSA. Similarly, the precharge circuit  31  executes the operation of precharging pairs of bit lines LBL&lt; 0 &gt; and /LBL&lt; 0 &gt; to LBL&lt;m&gt; and /LBL&lt;m&gt; in accordance with the precharge signal /PRE_LBL. 
         [0099]    The operation of the cell current measurement mode will now be explained. First, the main controller  19  deactivates the precharge signal /PRE_LBL (to high level). This turns off all the PMOS transistors of the precharge circuit  31 , and cancels precharging of the pair of local bit lines LBL and /LBL. 
         [0100]    Then, in the selected LSA, one of the output signals OUT_A 1  and OUT_A 2  changes to low level in accordance with the potential of the pair of global bit lines GBL and /GBL (this potential is set by the same operation as in the first embodiment), and a PMOS transistor corresponding to this low-level output signal is turned on. In this state, both the output signals OUT_B 1  and OUT_B 2  are at high level, and both the PMOS transistors  42 A and  42 B are OFF. Accordingly, a cell current corresponding to a measurement voltage Vm can be measured from a measurement terminal  20  via the PMOS transistor  32 - 1  or  32 - 2 . 
         [0101]    On the other hand, in the unselected LSA, both the output signals OUT_A 1  and OUT_A 2  change to high level, and both the PMOS transistors  32 - 1  and  32 - 2  are turned off. Also, both the output signals OUT_B 1  and OUT_B 2  change to low level, and both the PMOS transistors  42 A and  42 B are turned on. Accordingly, the unselected LSA is always precharged. 
         [0102]    Since, therefore, the high voltage (VDD) is applied to both the gate terminals and source terminals of the PMOS transistors  32 - 1  and  32 - 2  for cell current measurement connected to the unselected LSA, neither gate leakage nor off leakage occurs in these PMOS transistors. That is, it is possible to prevent a leakage current from flowing to the power line  21  via the PMOS transistors  32 - 1  and  32 - 2 . Accordingly, even when the memory capacity increases and the number of the PMOS transistors  32 - 1  and  32 - 2  for cell current measurement connected to the power line  21  increases, the cell current can be measured with high accuracy by using the measurement terminal  20 . 
         [0103]    It is also possible to reduce the number of PMOS transistor stages in the measurement switching circuit  32  to one. As a consequence, the cell current can be measured with higher accuracy. 
         [0104]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.