Abstract:
Printed wiring board testing apparatus comprising means for optically scanning a board to be tested in orthogonal X-Y axes, with each Y-direction scanning a narrow strip w in the X direction. Means for processing the signals provides signals representative of the characteristics of the board along the strip and for storing the signals. Control means causes the scanning means repeatedly to scan the board in Y direction and to step it a predetermined amount in X direction at each scan end until a required board area board has been scanned and the processing means has processed groups of signals. The processing means identifies common areas of each conductive track, so finally the storage means contains information representative of the co-ordinates of a plurality of datum areas and of the datum areas which are interconnected.

Description:
TECHNICAL FIELD  
         [0001]    This invention relates to a method and apparatus for inspecting pattern on a substrate such as a pattern on a printed wiring board.  
         BACKGROUND  
         [0002]    It is known from GB 2143944B to provide apparatus for testing a printed wiring board comprising means for optically scanning a board to be tested in two orthogonal, X-Y axes such that for each scan in the Y direction it scans a narrow strip of the board of predetermined width, w in the X direction, the scanning means being arranged to provide n.m discrete signals for each scan in the Y direction, wherein n is a predetermined number of signals representative of characteristics of the board across the width w of the strip and m is a number dependent upon the dimension of the scan in the Y direction, such that the n.m signals are representative of the characteristics of the board at the corresponding n.m positions along the strip, and processing means for processing the signals to provide signals representative of the characteristics of the board along said strip and means for storing said signals, control means arranged to cause the scanning means repeatedly to scan the board in the Y direction and to step it a predetermined amount in the X direction at the end of each scan until a required area of the board has been scanned and the processing means has processed a plurality of said groups of signals, the processing means being further arranged to identify common areas of each conductive track such that at the completion of a test, the storage means contains information representative of the X-Y co-ordinates of a plurality of datum areas and of the said datum areas which are interconnected.  
           [0003]    The board is scanned as a series of strips as shown in FIG. A.  
           [0004]    In that known technique, labelling is carried out by a data processor for the whole of each strip, the labels for the right hand column of a first strip are stored in RAM, and they are then read out while a second strip is scanned, and used to determine the labels for the left hand column of the second strip and so on. This has the disadvantage that only a single dataflow processor can be used, limiting the attainable speed of data processing.  
         STATEMENTS OF INVENTION  
         [0005]    In the present invention, a plurality of data processors are provided, each data processor being operative at a time to process data of a corresponding portion of a scanned strip, the scanned strip comprising a plurality of portions.  
           [0006]    In the preferred embodiments, there is an advantage of an increase in processing speed proportional to the number of data processors provided.  
           [0007]    Preferably each of the processors comprise interconnection analyser means arranged to determine which datum areas are connected together and to provide output information to a storage means, the output information being stored as a wiring list of datum areas interconnected by track, in which the wiring list is produced by integrating wiring lists for said portions of a strip by correlating data from the edge of a respective first portion and the adjacent edge of a respective second portion.  
           [0008]    Preferably the portions of a strip are parallel, and of substantially equal width in the X direction. Preferably, the portions are each of the same length as the strip.  
           [0009]    The datum areas preferably comprise terminations in the board such that at the end of a test the stored information is equivalent to a wiring list of interconnected datum areas.  
           [0010]    The terminations can comprise mounting pads for components, via-hole positions, points on power planes and/or points on ground planes, of a board.  
           [0011]    The processing means preferably comprise means for comparing the stored signals with a plurality of signals representative of the required interconnections for the board (the required wiring list) thereby to test the quality of the board.  
           [0012]    The apparatus preferably comprises track contraction means for processing preselected areas of each group of n1×m1 signals in such a manner as to determine whether the width of a conductor at any point along its length is less than a predetermined minimum width.  
           [0013]    The apparatus preferably further comprises track expansion means arranged to process the scanned signals in such a manner as to determine whether the spacing between adjacent conductors at any point along their length is less than a predetermined value.  
           [0014]    Further according to the invention there is provided a process for testing a printed wiring board comprising the steps of optically scanning a board to be tested in two orthogonal, X-Y axes such that for each scan in the Y-direction a narrow strip of predetermined width, w, in the X direction is scanned, deriving n.m discrete signals for each scan in the Y direction, wherein n is a predetermined number of signals representative of characteristics of the board across the width w of the strip and m is a number dependent upon the dimension of the scan in the Y direction such that the n.m signals are representative of the characteristics of the board at the corresponding n.m positions along the strip, and digitally processing the signals to provide signals representative of the characteristics of the board along said strip and storing said signals, scanning the board repeatedly in the Y direction and stepping it a predetermined amount in the X direction at the end of each scan until a required area of the board has been scanned and a plurality of said groups of signals has been processed, and identifying common areas of each conductive track such that at the completion of a test, information representative of the X-Y co-ordinates of a plurality of datum areas and of the said datum areas which are interconnected are stored as a wiring list, in which the digital processing comprises dividing data from a scanned strip into a plurality of groups of data each group corresponding to a portion of the scanned strip, and parallel-processing at least two of said groups of data. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0015]    Preferred embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:  
         [0016]    [0016]FIG. 1 is a block schematic diagram of an apparatus according to the invention for testing a printed wiring board,  
         [0017]    [0017]FIG. 1 a  is a block schematic diagram of a dataflow processor as shown in FIG. 1,  
         [0018]    [0018]FIG. 1 b  is a schematic illustration of scanning a board as a series of strips;  
         [0019]    [0019]FIG. 1 c  is a schematic illustration of data for each strip being processed as a number of narrower ribbons,  
         [0020]    [0020]FIG. 2 is a simplified, perspective view of a scanning means suitable for use with the apparatus of FIG. 1,  
         [0021]    [0021]FIG. 3 is a simplified view of an optical arrangement and an optical scanning device suitable for use with the FIGS. 1 and 2 apparatus,  
         [0022]    [0022]FIG. 4 is a simplified representation of a multiple delay circuit for use in the apparatus of FIG. 1,  
         [0023]    [0023]FIG. 5 is a part of a table showing the outputs of the circuits of FIG. 4,  
         [0024]    [0024]FIG. 6 is a simplified lock circuit diagram of a track contraction, or expansion, circuit of FIG. 1,  
         [0025]    [0025]FIG. 7 is a simplified drawing illustrating the processing of a group of n1×m1 signals by the circuit of FIG. 6,  
         [0026]    FIGS.  8  to  11  are tables for use in describing the operation of an interconnection analyser,  
         [0027]    [0027]FIGS. 12 and 13 are flow charts illustrating part of the operation of an interconnection analyser,  
         [0028]    [0028]FIG. 14 is a block diagram of a label allocation request generation circuit,  
         [0029]    [0029]FIG. 15 is a block circuit diagram of an interconnection analyser,  
         [0030]    [0030]FIGS. 16 and 17 are block diagrams of circuits for use in the circuit of FIG. 15,  
         [0031]    [0031]FIG. 18 is a block diagram of an edge transition detection circuit,  
         [0032]    [0032]FIG. 19 is a block diagram of the termination pulse generator shown in FIG. 1 a.   
     
    
       [0033]    Referring to the drawings, in FIG. 1 there is shown an apparatus  10  for testing the wiring of a printed wiring board  12  (FIGS. 2 and 3). The apparatus  10  includes two similar dataflow processors  11 , the internals of which are shown in FIG. 1 a . In other embodiments there are more than two such dataflow processors  11 .  
         [0034]    A printed circuit board being inspected is scanned as a series of strips as shown in FIG. 1 b . For processing data of each strip each strip is considered and is divided into two ‘ribbons’, as shown in FIG. 1 c , and data of each ribbon is labelled using a separate dataflow processor  11 . A ribbon is a portion of a strip such that the two or more ribbons constituting each strip are parallel, of equal width, and the same length as the strip. Because the second dataflow processor  11 ,  11   a  does not have access to the labels generated by the first dataflow processor  11 ,  11   b , and vice versa, the technique of storing the labels for the edge columns in RAM and reading them out again is not used. Rather, processing is achieved by labelling each ribbon as though it were isolated from the rest of the board, and then linking the resulting wiring lists together in software.  
         [0035]    This is illustrated in FIG. 1 c , where the strips of FIG. 1 b  are each split into two ribbons. The first dataflow processor  11   a  processes ribbons marked  1 ,  3 ,  5  &amp;  7 , and the second dataflow processor lib processes ribbons marked  2 ,  4 ,  6  &amp;  8 . The locations of transitions in the right hand column of ribbon  1  and the left hand column of ribbon  2  are used to determine how to link together the wiring lists for these two ribbons, and then the locations of transitions in the right hand column of ribbon  2  and the left hand column of ribbon  3  are used to determine how to link the wiring list for ribbon  3  to the composite wiring list for ribbons  1  &amp;  2  and so on, until the wiring list for the complete board is obtained.  
         [0036]    In alternative embodiments more than two dataflow processors  11  are provided, each strip being divided into a corresponding number of ribbons such that a data processor processes a corresponding ribbon.  
         [0037]    The apparatus  10  is controlled by a computer  14 , which also includes various storage elements such as random access memories (RAM&#39;s) for use in the operation of the apparatus and the storage of information for use in testing a board  12 .  
         [0038]    The apparatus  10  comprises an optical scanner  16  which is controlled by servo/stepper motors  18  to traverse backwards and forwards across the surface of the board  12  in the Y direction and after each traversal it is moved relative to the board a predetermined distance in the X direction.  
         [0039]    [0039]FIG. 2 shows a simple arrangement for such a scanner  16 , in which the optical scanning device  20  can be traversed backwards and forwards in the Y direction while the board  12  can be stepped a discrete distance in the X direction between each Y traversal. Other arrangements are of course possible, for example the board  12  could be moved on an X-Y table moveable in both orthogonal axes with the device  20  fixed in position or the board  12  could be mounted in a fixed position and the scanning device  20  mounted for movement in the X-Y directions.  
         [0040]    [0040]FIG. 3 shows a simplified side view of an optical scanning device  20 , utilising a charge coupled device (CCD) camera  22 .  
         [0041]    As shown in FIG. 3, light from a lamp  1  is focussed by a lens  2  onto a fibre optic cable  3 . The other end of the fibre optic cable  3  is formed so that the light emerges from a slit-shaped region. This region is imaged by two lenses  4 ,  5  through a partially silvered beamsplitter  6  on to a surface  7 . Light scattered by the surface  7  is reflected off the beamsplitter  6  and imaged by two lenses  8 ,  9  onto the CCD  22 .  
         [0042]    The surface  7  of the board  12  is imaged by the lenses  8 ,  9  on to the charge-coupled device  22 , which contains a linear array of photosites together with circuitry for reading out the light levels from each photosite.  
         [0043]    In this embodiment there are 4096 photosites arranged to scan a strip about 40 mm wide in the X direction as the board  12  is scanned in the Y direction, i.e. each photosite is responsive to a 10 micron×10 micron area (a pixel).  
         [0044]    Thus the linear array of photosites effectively produces a parallel output containing 4096 analogue pieces of information in the X direction. As the board is scanned in the Y direction the array continues to develop 4096 output signals at discrete position 10 microns apart for the complete scan in the Y direction.  
         [0045]    The 4096 signals from the CCD scanner device  16  representing a strip 40 mm long in the X direction and 10 microns wide in the Y direction are coupled serially to the input of a threshold circuit  34  having a threshold reference voltage input.  
         [0046]    The binary stream of information indicative of track (i.e. conductor) and non-track (i.e. insulating substrate) pixel areas appearing at output  34   b  is fed to a multiple delay circuit  36 . The circuit  36  is implemented using random access memories (RAM&#39;s) for low cost, but can be considered conceptually, and for ease of description, as a set of shift registers  38  each one of which feeds the next as shown in FIG. 4.  
         [0047]    Each shift register  38  is 4096 bits long so that at time t=4096 the first shift register  38   a  could be regarded as containing a full 4096 bits of information in one 40 mm wide strip of the area being scanned. At time t=8192 the first 4096 bits of information will have been shifted serially into shift register  38   b  and shift register  38   a  will contain the next succeeding 4096 bits of information and so on.  
         [0048]    As the delay through each shift register is equal to one scan line in the X direction the parallel outputs  39   a  to  39   m′  of the shift registers  38   a  to  38   m′  at any time can be regarded as m′ bits of information in a row in the Y direction of scan. Thus the outputs of the shift registers represent a parallel scan across the width of the scan, as shown in part in the table of FIG. 5.  
         [0049]    The parallel output signals from the multiple delay circuit  36 , that is the outputs  39   a  to  39   m′  are coupled in parallel to a pair of circuits  42 ,  52  whose function is to determine for each point in the scanned image whether it is within a preset distance of a track or non-track area. The circuit  42  is called a track contraction circuit and the circuit  52  a track expansion circuit; the track expansion circuit  52  is similar to the track contraction circuit  42  with the exception that its input and output signals are inverted. Any one of the outputs of the multiple delay circuit  36  (for preference the middle one of the  39   a  to  39   m′ ) is also f ed to the interconnection analyser  40 .  
         [0050]    The interconnection analyser  40 , to be described hereinafter, is coupled through a first-in, first-out buffer  120  to the computer  14 . Its function is to produce a set of signals to be stored which are a representation of a wiring diagram for the printed wiring board  12 , that is it provides a set of X-Y co-ordinate signals representative of terminations in the board and edge connector areas, if any, labelled to indicate which terminations are interconnected. A termination is a point on a circuit feature, such as the centre of a component mounting pad, a place on the printed circuit where a via-hole is intended to be drilled.  
         [0051]    The track contraction circuit  42  will now be described with reference to FIG. 6. The circuit  42  comprises a plurality of tapped shift registers  44   a  to  44   m ′ having inputs  45   a  to  45   m ′ coupled to the outputs  39   a  to  39   m ′ respectively of the shift registers  38 . Each circuit  44  has a programmable, tapped output  46   a  to  46   m ′ which is coupled to the preset input  47   a  to  47   m ′ of a presettable down counter  48   a  to  48   m ′ respectively. The taps on the shift registers  44  are under the control of the computer  14 .  
         [0052]    In a practical embodiment m′=40 so that there are forty shift registers  38  and  44  and the shift registers  44  are forty bits long (that is n′=40) so that the set of shift registers  44  at any one time contain information equivalent to an area 40×40 bits (or pixels) square, although it will be realised that, in operation, bits of information are being shifted in parallel through the various registers at clock rate. Thus at a given instant the information contained in the shift registers  44  can be regarded as a digital image of part of the board. The contraction circuit  42  is arranged to determine whether or not all of the bits in the shift registers  44  which would fit in a circle of radius R, where R is equal to half the minimum specified track width, are a binary ‘1’ to indicate track. The value of R is predetermined for the board  12  and its value is set into the computer by the operator. For example in the 40×40 matrix of shift registers  44 , the value of R could be made equal to 20 and it would be possible to look at the bits of the individual cells of the shift registers to determine their value. If each cell was provided with an output an individual AND gate could be coupled to various cells in a particular shift register and the outputs of the individual AND gates coupled to the inputs of another AND gate so that if, and only if, all of the individual cells contained a binary ‘1’ then the output of the final AND gate would be a ‘1’ to indicate a complete track in the area of radius R. However if only a single cell was set to ‘0’ then the output of the final AND gate would be zero indicating that the track was not entirely complete at the area being tested at that instant in time.  
         [0053]    In the example given using forty shift registers, each forty bits long the first and fortieth shift registers could be tapped at, say cells  20  and  21 , the middle twentieth and twenty first shift registers could have every cell tapped and connected to an associated input of two forty input AND gates. The shift registers two to nineteen would have progressively more cells tapped and the registers twenty-two to thirty-nine would have progressively fewer cells tapped so that the outputs from the tapped cells would approximate to a circle of radius R. However this arrangement would be expensive in AND gates and quite complex and somewhat difficult to vary in practice and the circuit of FIG. 6 was devised.  
         [0054]    In FIG. 6 the taps on the shift registers  44  can be set automatically by the computer  14  under the control of the operator and it will be seen that they are variable delays, the delay being a maximum (20 bits) for the first and fortieth shift registers  44  and a minimum (zero) for, say, the twentieth and twenty-first. The delays for shift registers  2  to  19  decrease progressively from 19 to 1 bits and for shift registers  22  to  39  increase progressively from 1 to 19 bits. The counters  48   a  to  48   m ′ can be preset to a count determined by its position, i.e. for the first and fortieth counters the preset count would be a minimum value (say 1 or 2) and for the twentieth and twenty-first counters to a maximum value (say 40). The other counters are preset to values increasing and decreasing in the same way as the delays through the shift registers  44  decrease and increase.  
         [0055]    [0055]FIG. 7 is a diagrammatic representation of a simplified circuit of FIG. 6 having nine preset shift registers  44  each nine bits long. At the instant shown in FIG. 7, the circuitry is determining whether there are any non-track areas within a distance R from the point P. Each circuit  44 ,  48  determines whether there are any non-track areas along a corresponding strip such as that marked XXXXXXX and the outputs of all of the counters  48  are combined in AND gate  50  to provide a single output; ‘b  1 ’ if all of the counter outputs indicate track; ‘0’ if any one or more of the counter outputs indicate the presence of a non-track area. In the example shown the seventh counter  48   g  would be preset to a count of seven whenever a non-track element is seen at position Q 7 . The counter is then counted down to zero so that if all of the elements marked X contain track, i.e. are at ‘1’ then the output of the counter will go to ‘1’. This disables further counting of the counter  48   g  via line  49   g  until the counter is preset again. The output of AND gate  50  will thus go high ‘1’ if and only if all of the elements within a distance R of P contain track. The output of the AND gate is thus a serial representation of an image similar to that arriving at the threshold circuit  34 , except that it has been delayed, and the track areas have been “thinned down” in accordance with the minimum track width settings. Thus, if the track is complete but does not meet the minimum track width requirements at any point along its length, for example if there is a nick or a flaw in it the output of AND gate  50  will go to zero at this point. This information will be processed in an interconnection analyser  54  and the output fed to the computer  14  via a FIFO buffer  114 .  
         [0056]    The track expansion circuit  52  is similar to the track contraction circuit  42  with the exception that the input to it and the output from it are inverted. It is thus caused to consider track as non-track and vice versa. In this case if the value R is made half the minimum allowable spacing between conductors then if the spacing is adequate the output of its AND gate (equivalent to AND gate  50 ) will be a series of ‘1’&#39;s but if the spacing at any position on the board is less than the minimum allowable the output of the AND gate will go to ‘0’. The information from the track expansion circuit will be processed in an interconnection analyser  56  and the output fed to the computer  14  via the FIFO buffer  122 .  
         [0057]    The above explanation has been considerably simplified as if the information is static but it should be realised that the information is being shifted through the shift registers at clock frequency and the testing is taking place continuously on the fly.  
         [0058]    Also it will be remembered that the image is 4096 bits wide in the X direction and although the delay shift registers  38  are 4096 bits long the shift registers  44  are only n′=40 bits long. Thus at say t=4096p where p is an integer the circuit  42  may be inspecting rows  1  to  40  in the X direction, at t=(4096 p+1 clock pulse) rows  2  to  41  and so on.  
         [0059]    As mentioned the train of output signals from the circuits  42 ,  52  are processed by interconnection analysers  54 ,  56  respectively.  
         [0060]    The function of the interconnection analyser is to determine which terminations are connected together to form a wiring list which is stored in the computer.  
         [0061]    For a good board the wiring lists compiled by the circuits  54 ,  56  i.e. the “thinned” and “fattened” images respectively, should be the same but if there are any narrow cuts, nicks, pinholes or inadequate spacing between conductors the two wiring lists will differ. They can also be compared with a wiring list obtained from the CAD data, for the board or from a known good board the CAD data being the information describing the desired configuration of the board, in machine readable format. Alternatively, or in addition they can be compared with a wiring list prepared from the interconnection analyser  40  which, in effect provides a basic list of the various complete interconnections but regardless of the presence of nicks, pinholes or the like, provided that the circuit is complete and regardless of the spacing between conductors provided that they do not actually touch.  
         [0062]    The interconnection analysers  54 ,  56  scan the data streams from the track contraction circuit  42  and the track expansion circuits  52  respectively and associate a “label” with each track area. These labels are binary numbers, which are allocated in sequence whenever a “new” piece of track is scanned. When a termination pulse occurs, the label of the corresponding piece of track is passed to the computer. When two pieces of track which have been given different labels converge, so that they are known to be connected together, the two labels concerned are passed to the computer with the information that they are interconnected. The edge of a band 4096 bits wide X m bits long is defined by the final, or 4096 th , bit in each 4096 bits across the width w of the band. The labelling process is carried out in three stages as illustrated in the tables of FIGS. 8, 9,  10  and  11 . In each of these figures, the lower line represents labels that have been determined for the previous scan line, and the upper line represents the labels that have been determined so far for the scan line that is currently being labelled. The data for this scan line is traversed three times before all the labels are correctly allocated. The first traversal is from right to left, and serves only to identify any region of track which does not touch any regions of track in the previous line, and which will therefore require a new label to be allocated to it.  
         [0063]    In the Figures individual areas of track are allocated a code, in which:  
         [0064]    O represents a non-track area.  
         [0065]    X represents a track area to which a label is to be allocated.  
         [0066]    A represents an area where a label request signal has been generated.  
         [0067]    A two digit number e.g. 27 represents a label which has been allocated to a track area.  
         [0068]    Referring to FIG. 8, as mentioned the lower line shows part of a scanned line which has been labelled and, reading from left to right, the first track areas have been labelled as track areas  27 , the next three areas are non-track, the next two areas have been labelled as track areas  35  and so on.  
         [0069]    The labels are allocated by a label allocation counter (FIG. 16) and are coupled as 16 bit words to the computer  14  when a termination pulse occurs or when a “collision” (to be defined hereinafter) occurs.  
         [0070]    The first label allocation traversal is from right to left as shown in FIG. 9 and, as mentioned, serves to identify areas of track which do not touch any areas of track in the lower, immediately proceeding scanned track.  
         [0071]    If it identifies such track it allocates a label allocation request A in the first non-track area that occurs after that particular piece of track. In FIG. 9 there are two such adjacent areas at positions  10  and  11  from the left. As the data is being traversed from right to left the first available non-track area is position  9  and this is allocated a label allocation request A as shown.  
         [0072]    A circuit for performing this function is shown in FIG. 14.  
         [0073]    Referring to FIG. 14, input data in serial form and representing the 4096 bits of information of a scanned line is coupled from the output of the track contraction circuit  42  to an input  70  of the interconnection analyser  54 . A similar circuit to that of FIG. 14 is used in the interconnection analysers  40  and  56  and so the operation in relation to these circuits will not be discussed in detail.  
         [0074]    The stream of data coupled to input  70  is coupled to an n-bit delay  72  (n=4096), a 1-bit delay  74 , an n bit data store  76 , to the inverting input  78   a  of an AND gate  78 , and to input  80   a  of an AND gate  80 .  
         [0075]    The output of the 4096 bit delay  72  and the AND gate  80  are coupled to reset and set inputs  82   a ,  82   b  of a bistable circuit  82 . Thus current data bits corresponding to the track/non-track areas in the upper row of FIG. 9 are coupled to the set input  82   b  of the bistable circuit  82  and the corresponding data from areas in the previous scan line are fed to the reset input  82   a  of the bistable circuit  82 . So long as the input data is representative of non-track i.e. ‘0’ the AND gate  80  has ‘0’ on input  80   a  and a ‘0’ on the line to input  80   b  due to the 1-bit delay through delay  74  which is inverted to present a ‘1’ input to the AND gate  80 . Thus as soon as a piece of track is encountered the corresponding ‘1’ bit on input  80   a  causes the AND gate  80  to provide a ‘1’ on the input  82   b  to set the bistable circuit  82 , which provides a ‘1’ at the output  82   c . If the next piece of input data is a ‘1’ representative of track the input at  80   a  is a ‘1’ but the previous ‘1’ input delayed 1-bit arrives at the input  80   b  is inverted and the output of AND gate  80  returns to “zero”.  
         [0076]    The effect of this is that as soon as a piece of track is encountered at input  70  the output of AND gate  80 , is at ‘1’ for one clock pulse duration.  
         [0077]    The delay circuit  72  being 4096 bits long is effectively providing information about the area of track immediately below the area currently being examined. If the area in the lower row is also track then a ‘1’ will be applied to the reset input of bistable  82  to reset its output to ‘0’. However if the output of the delay  72  is ‘1’ representing non-track then the bistable will remain set and a ‘1’ will be applied to input  84   a  of AND gate  84 . However, while the input  70  is receiving track signals the ‘1’ signals fed to inverting input  78   a  keep the output of AND gate  78  at ‘0’ and thus inhibit the AND gate  84 . As soon as the input reverts to non-track ‘0’ the output of AND gate  78  goes to ‘1’ and a ‘1’ is fed into the 4096 bit allocation request store  86 . This ‘1’ bit is fed into store in the first non-track area after the track to non-track transition. For example in FIG. 9 where scanning is taking place from right to left, track is located at position  11  from the left which is not adjacent to a piece of track in the previously scanned lower row and a label must be allocated to it. This ‘1’ coupled to input  80   a  and the ‘0’ from the 1-bit delay  74  will provide a ‘1’ on the output of AND gate  80  to set the bistable  82 . However the AND gate  84  will be inhibited by the corresponding ‘1’ on the inverting input of AND gate  78 . The next ‘1’ input at position  10  from the left will be coupled to AND gate  80  but its output will return to ‘0’ because the previous ‘1’ from position  11  delayed 1-bit in delay  74  will appear at inverting input  80   b . Thus bistable  82  remains set but can be reset if a ‘1’ appears at input  82   a . At position  9  from the left in FIG. 9 the input signal at  70  reverts to non-track ‘0’ and this coupled to inverting input  78   a  of AND gate  78  removes the inhibit signal from AND gate  84  and allows a ‘1’ into the label allocation request store  86 . This is shown as A in FIG. 9 and as aforementioned appears in the first non-track area after a piece of track to which a label has not been allocated.  
         [0078]    Thus the data store  76  contains the 4096 bits of information of the scanned line and the LAR store  86  contains a series of ‘0’ and a ‘1’ at the position immediately to the left of an isolated piece of track to which a label has not been allocated and which is not adjacent to a piece of track in the line previously scanned.  
         [0079]    The stores  76 ,  86  are bidirectional so that data can be read out from left to right during the next traversal (FIG. 10) so that at position  9  from the left a label allocation request is fed from store  86  to a label allocation counter (to be described in relation to FIGS. 12 and 16) which allocate a new label, in this case  57 , to the track areas  10  and  11  from the left and updates the label allocation counter to the next label to be allocated.  
         [0080]    Also during this traversal from left to right, the track areas are labelled up as far as possible by reference to the labels in adjacent elements. Some elements may be impossible to label at this stage, and they are identified by a special ‘Don&#39;t Know’ code, so that they can be resolved during the third traversal, for example the track at position  6  from the left in FIG. 10 because it is adjacent to an area of non-track in the previous line immediately below it. The labels for the previous scan line are held in a RAM  108  marked RAM′ in FIG. 15, and the ‘left-right traversal circuit’ uses these to generate a set of labels including ‘Don&#39;t Knows’ in the RAM  100  marked RAM  2  in FIG. 15. During the third traversal these values are transferred back to RAM  1  by the ‘right-left traversal circuit’ FIG. 17 which also replaces any ‘Don&#39;t Knows’ by the correct labels.  
         [0081]    The output from the 4096 bit data store  76 , being a series of ‘0’ and ‘1’ representing non-track and track, is coupled to a data input terminal  90  of circuit FIG. 16. Likewise, the output from the label allocation request (LAR) Store  86 , being a series of ‘0’ but containing a ‘1’ for each new label to be allocated is coupled to input terminal  92  of FIG. 16.  
         [0082]    The logic of the left-right traversal is shown in the flow chart of FIG. 12. Non-track elements are labelled with ‘non-track’ code. If a ‘label allocation request’ code is encountered, a new label is obtained from the label allocation counter (FIG. 16). Other elements are labelled by reference to the adjacent elements. In the situations shown below the element marked ? is a track element which is to be labelled, L 1  &amp; L 2  are differing labels and a 0 represents a non-track element. The various possibilities are as follows:  
                                                                                                     LABEL IS L1                                                     LABEL IS L2                                                     LABEL IS ′DON′T KNOW′                                                     LABEL IS L1                                                     LABEL IS L1. COLLISION BETWEEN L1 &amp; L2 MUST BE REPORTED TO THE MICROPROCESSOR                                                     LABEL IS L1. COLLISION BETWEEN L1 &amp; L2 HAS ALREADY BEEN REPORTED TO THE MICROPROCESSOR                      
 
         [0083]    The flowchart of FIG. 12 represents the logical paths, which must be followed to obtain these results, where the corresponding symbols are:  
                                                                                                            when               Q   is the name of the box to be filled in.           Q′   is the name of the box in the same scan line as               Q but 1 place to the left.           D   is the name of the box underneath Q. i.e. in the               last scan line.           D′   is the name of the box underneath Q′. i.e. in               the last scan line.                      
 
         [0084]    I/P is the input from the bidirectional shift registers in the Label Allocation Request Generator.  
         [0085]    NT is the code for ‘Non-Track’.  
         [0086]    LAR is the code for ‘Label Allocation Request’.  
         [0087]    DK is the code for ‘Don&#39;t Know’ 
         [0088]    LAC is the output of the Label Allocation Counter.  
         [0089]    Referring to FIGS. 16 and 12, data input is coupled to input  90  and label allocation request input is coupled to input  92  of a control logic circuit  94 .  
         [0090]    In FIG. 12 each bit of data is interrogated to enquire if it is track or non-track (NT); interrogation (A) if it is NT the action is allocate Q=NT and in FIG. 16 this is achieved by way of the control logic  94  which sets a five way data selector  96  to couple a 16-bit non-track code from circuit  98  to the input of RAM  100  (FIG. 15).  
         [0091]    If the input is track then it is interrogated (B) to determine whether there is also a label allocation request signal on input  92 . If there is, the logic circuit  94  couples the output of a label allocation counter  102  to the RAM  100 , and then increments the counter  102  to the next label address.  
         [0092]    If there is not a label allocation request the flow chart enquires whether Q′, the Q in the previously interrogated area is non-track (C) . If Q′ was track then Q is a continuation of the track and the label allocated to Q′ must also be allocated to Q. This is achieved by coupling the output of a delay register  104  which is holding Q′ to the RAM  100  by way of the data selector  96 . If Q′ was non-track, the interrogation is, was D non-track (D). If it was NT then it is not yet possible to allocate an address label to Q and it is therefore allocated a ‘Don&#39;t Know’ code from circuit  106 . As before the ‘Don&#39;t Know’ code is coupled to RAM  100  by way of data selector  96 . If D was track, then Q is allocated the same label as D (Q=D) and the appropriate D label is taken from RAM  108  by way of data selector  96  to RAM  100 .  
         [0093]    If Q is track and Q′ is track (interrogation C) and Q was made equal to Q′ then the next interrogation is, does Q=D (interrogation E) if it does then no further action is necessary (Q having been correctly labelled). If however Q is not equal to D then the next question (interrogation F) is, is D=NT (non-track) if it is then again no further action is necessary (Q having been correctly labelled). If however D is track and not equal to Q then there is a situation in which both Q and D are track elements which have been allocated different labels although they are in fact touching. This is termed a “collision” in this specification and is detected by comparator  113 . It is necessary to report this collision to the computer  14 . To save storage space in the computer it is only necessary to report the first instance of a collision and so the next interrogation (G) is, is D′=NT if it is then this must be the first instance of this collision and the control circuitry will then load the label Q and the label D to the microprocessor  14  via the FIFO store  114 . If D′ is equal to track then the collision must have been reported previously and therefore no further action is necessary. Such a collision is illustrated at position  19  from the left in FIG. 10 where labels  46  and  31  have been allocated to the same piece of track.  
         [0094]    During the third traversal FIG. 11, the labels are read out from RAM  100  and any ‘Don&#39;t Knows’ are set to the same label as the element on their right by the ‘right-left traversal circuit’ FIG. 17 before they are written back into RAM  108 , in accordance with the flow chart of FIG. 13. Such a ‘Don&#39;t Know’ was shown at position  6  from the left in FIG. 10 and in FIG. 11 it will be seen that it has been allocated label  35 . The corresponding symbols for this flowchart are reversed, so that Q 1 ′ is the name of the box in the same scan line as Q 1  but one place to the right.  
                         
 
         [0095]    The interconnection analysers  40  and  56  operate in a similar way to that of the analyser  54  but the data input in the case of analyser  56  is, in effect, the data after “track expansion” as hereinbefore described and in the case of analyser  40  it is unmodified data.  
         [0096]    An edge transition detection circuit (FIG. 18) is provided as part of the control logic  94  of each interconnection analyser. The inputs to this edge transition detection circuit are the input data to the respective interconnection analyser and a signal which is pulsed when the first pixel of each line is being fed to the respective interconnection analyser. A latch  13  is enabled by this pulse, so that its output changes on the trailing edge of the pulse to match the data on the input during that pulse. An ‘exclusive or’ gate  15  compares the output of the latch  13  with the input, and outputs a ‘1’ whenever they differ. This signal is gated with the timing pulse, so that an output pulse is generated whenever a pixel is found in the left hand column of the current row which differs from that in the left hand column of the preceding row. An identical circuit is used for the right hand column, but with the timing pulse occurring at T=4095. Whenever one of these signals occurs, the corresponding label is fed to the corresponding FIFO buffer, together with the Y co-ordinate of the row, and a bit indicating whether the event occurred at the left or right hand column.  
         [0097]    The termination pulse generator  35  is shown in more detail in FIG. 19 and is used to generate ‘termination’ pulses. When one of these pulses occurs, the current labels in the respective interconnection analysers  40  are fed to their FIFO buffers  120 ,  14 ,  122 , together with a bit indicating that the data corresponds to a termination. The timing of the termination pulses is arranged so that the termination pulses correspond to points in the image representing component mounting pads, places where via holes will be drilled etc. The information to determine these termination points is obtained from a CAD system, as the information is the same as that which would be required to, for example, build a fixture for a ‘bed of nails’ electrical tester, or to program an automatic drilling machine to drill the via holes in the board.  
         [0098]    The computer sorts the data into the order in which the (X, Y) co-ordinates will be encountered during scanning i.e. firstly by increasing Y (or decreasing Y if the strip is to be scanned in the reverse direction), and secondarily by increasing X. The sorted data is downloaded to the FIFOs  17 ,  19  from the computer. During scanning, the X counter  21  is incremented for each pixel and reset at the end of each line, and the Y counter  23  is incremented at the end of each line. Whenever the X and Y counts agree with those in the FIFO buffers  17 ,  19  a termination pulse  25  is output to the interconnection analysers  40 ,  54 ,  56  and the data of the next termination is shifted to the output of the next FIFO buffers  17 ,  19 .  
         [0099]    The information fed to the computer  14  from the interconnection analyser  40  via the FIFO buffer  120  is sufficient to enable a wiring list to be generated indicating which terminations are connected to which other terminations, and this can be compared with the wiring list obtained from a known good board so that differences between the two can be indicated to the operator in the same way as with a ‘bed-of-nails’ tester. The wiring lists obtained for the ‘thinned’ and ‘fattened’ images by way of analysers  54  and  56  and their respective FIFO buffers  114  and  122  can also be compared to determine the presence of partial breaks and shorts.  
         [0100]    The wiring list for the entire panel is determined from the data stored in the FIFO buffer  120  by the technique known as ‘linked list processing’, in which data is stored in the computer as records, each of which contains a data value and a pointer, which provides a link to another such record. Initially all links are cleared i.e. nil. As the data is read from the FIFO buffer  120  records are created for each label and termination. If the entry in the buffer  120  was caused by a termination pulse, a link is created between a termination record and the corresponding label record. If the entry in the buffer was caused by a ‘collision’, a link is created between two label records. If the entry in the buffer  120  was caused by a left-hand edge transition, a link is created between the label record and the label record for the corresponding edge pixel in the adjacent ribbon. If the entry in the buffer was caused by a right-hand edge transition, the data is used to update an array recording the labels in the right-hand column for use when the next ribbon is processed.  
         [0101]    Once all the links have been created, the records for the labels can be deleted from the linked lists, leaving only the records for the terminations. These can be compared against the linked lists obtained from the CAD data or a known good board as discrepancies between the two linked lists indicate a break or short circuit in the printed circuit board being inspected. Similarly the linked lists obtained from the interconnection analysers  54  and  56  can be compared against the linked list obtained from interconnection analyser  40  with discrepancies indicating partial breaks or near-shorts respectively.  
         [0102]    To explain this further, turning back to FIG. 1 c , whenever a new track area is found adjacent to the previously scanned ribbon, a label allocation request is generated.  
         [0103]    For each edge of the ribbon being processed, the data for each edge pixel is compared against the data of the previous column, and whenever a track-to-nontrack or nontrack-to-track transition occurs, a report is sent to the same FIFO buffer as the one used for collisions. This report contains the label of the pixel, the ‘Y’ position along the strip, the edge (left or right) where the transition occurred, and whether it was track-to-nontrack or non-track-to-track transition. This information is used to integrate the wiring lists for all the ribbons. The software determines the wiring list for each ribbon, and then uses the edge reports to merge the wiring list into a wiring list for the entire image. Since labels cannot propagate from one ribbon to another, the label allocation counters are reset at the start of each strip.