Abstract:
A resolution switch circuit for an image sensor uses a control unit to control a plurality of image gathering units to generate and store image signals. A resolution control unit controls a plurality of shift registers through the resolution control signals so that the shift registers control the image gathering units to output image signals. The signal combining unit is used to combine the image signals output from the image gathering units to achieve resolution change. Since the resolution switch circuit for the image sensor according to invention does not require additional resolution switch wiring, the affect of noise can be avoided and cost of the circuits can be reduced. The transmission of the image signals in the form of charges prevents any signal distortion due to resistance of wiring during transmission.

Description:
BACKGROUND OF THE PRESENT INVENTION 
       [0001]    1. Field of the Present Invention 
         [0002]    The present invention generally relates to a resolution switch circuit, and more particularly to a resolution switch circuit for a contact image sensor and a method of changing the resolution value for an image sensor. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  is a circuit graph of a conventional switch circuit for a contact image sensor. Referring to  FIG. 1 , the conventional switch circuit can change resolution. A control unit  11  uses the fourth control signals CON 1 -CON 4  to control the operation of a sensing element-terminal resolution switch circuit  12 , and uses the fourth control signals CON 5 , CON 6  to control the operation of the shift register-terminal resolution switch circuit  15 . Such a switch circuit produces a lot of noise, and thus suffers from signal uniformity, high production costs and a complex wiring structure. 
       SUMMARY OF THE INVENTION 
       [0005]    Therefore, the present invention provides a resolution switch circuit of an image sensor, which does not need additional resolution switch circuits such as a sensing element-terminal resolution switch wiring or a shift register-terminal resolution switch wiring, and thus avoids any negative affects of noise, increases the signal/noise ratio and lowers the cost of the circuit. Furthermore, the output of internal first image signals and second image signals is achieved by using a switch capacitor (SC) in which the signals are transmitted in form of charges. By means of avoiding generating any difference of resistance in the signal output wiring, the present invention prevents signal distortion during transmission and increases signal uniformity. The circuit of the present invention does not require the transistors used in the conventional optical signal converting unit, which results in reduced production costs. 
         [0006]    One object of the invention is to provide a resolution switch circuit of an image sensor, including a plurality of image gathering units respectively used to gather an image and to generate accordingly a first image signal and a second image signal based on the image. A signal combining unit is connected to the image gathering units to combine the first image signals and combine the second image signals. A control unit is connected to the image gathering units and the signal combining units to control the image gathering units and the signal combining unit. A plurality of shift registers, is connected to the image gathering units to control the transmission of the first image signals and combine the second image signals to the signal combining unit. Lastly, a resolution control unit is connected to the shift registers to generate at least one resolution control signal to control the shift registers for resolution changing. 
         [0007]    The invention further provides a method of changing a resolution value for an image sensor. A control unit controls a plurality of image gathering units to gather an image so that each of the image gathering unit generates a plurality of first image signals and a plurality of second image signals. Then a resolution control unit generates a corresponding resolution control signal according to desired resolution to control a plurality of shift registers. The shift registers respectively generate an output control signal according to the resolution control signal to control the image gathering units to output the first image signals and the second image signals to a signal combining unit. Finally, the signal combining unit combines the first image signals and combines the second image signals. 
         [0008]    To provide a further understanding of the present invention, the following detailed description illustrates embodiments and examples of the present invention, this detailed description being provided only for illustration of the present invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a diagram of a switch of a conventional contact image sensor. 
           [0010]      FIG. 2  is a block diagram of a resolution switch circuit for an image sensor according to one embodiment of the invention. 
           [0011]      FIG. 3  is a circuit diagram showing an image gathering unit of a resolution switch circuit for an image sensor according to one embodiment of the invention. 
           [0012]      FIG. 4A  is a circuit diagram showing a signal combining unit according to a first embodiment of the invention. 
           [0013]      FIG. 4B  is a circuit diagram of a signal combining unit according to a second embodiment of the invention. 
           [0014]      FIG. 5  is a timing diagram of a normal resolution signal of a resolution switch circuit for an image sensor according to one embodiment of the invention. 
           [0015]      FIG. 5A  is a block diagram of a resolution switch circuit for an image sensor under normal resolution conditions according to one embodiment of the invention. 
           [0016]      FIG. 6  is a timing diagram of a resolution switch circuit at ½ resolution according to another embodiment of the invention. 
           [0017]      FIG. 6A  is a block diagram of a resolution switch circuit at ½ resolution according to another embodiment of the invention. 
           [0018]      FIG. 7  is a timing diagram of a resolution switch circuit at ¼ resolution according to another embodiment of the invention. 
           [0019]      FIG. 7A  is a block diagram of a resolution switch circuit at ¼ resolution according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0020]    Wherever possible in the following description, like reference numerals will refer to like elements and parts unless otherwise illustrated. 
         [0021]      FIG. 2  is a block diagram of a resolution switch circuit for an image sensor according to one embodiment of the invention. Referring to  FIG. 2 , the resolution switch circuit for the image sensor according to the invention includes a control unit  21 , a plurality of image gathering units  231 - 23   n , a plurality of shift registers  241 - 24   n , a resolution control unit  25 , and a signal combining unit  27 . The control unit  21  sends out a first control signal RST, a second control signal SHR, and a third control signal SHS to control the image gathering and image signal storing of the first image gathering unit  231 , the second image gathering unit  232  . . . and the n th  image gathering unit  23   n . A fourth control signal CLK controls the signal combining unit  27  so that the signal combining unit  27  receives the image signals generated by the image gathering units  231 - 23   n  through a first image output wiring OUTP and a second image output wiring OUTN. The resolution control unit  25  outputs a plurality of resolution control signals CC 1 -CC 2   m−1  according to the change in resolution (wherein m is the number of resolution, and is an integral) to control the output of signals from the shift registers  241 - 24   n . The shift registers  241 - 24   n  output a plurality of output control signals TG 1 -TGn according to the resolution control signals CC 1 -CC 2   m−1  to control the output of the image signals gathered by the image gathering units  231 - 23   n  to the signal combining unit  27 . Under the timing control of the control signals (RST, SHR, SHS, CLK, TG 1 -TGm), the images can be gathered and transmitted according to the desired resolution value. The image gathering units  231 - 23   n  are arranged in line so as to gather the target images precisely. 
         [0022]    Below will follow the detailed description of controlling of the image gathering units  231 - 23   n  and the signal combining unit  27  via the respective signals RST, SHR, SHS, CLK, TG 1 -TGn. 
         [0023]    Taking the first image gathering unit  231  as an example, the first image gathering unit  231  receives the first control signal RST, the second control signal SHR, the third control signal SHS, and the shift register by the first control unit  21 , and receives the output control signal TG 1  generated by the shift register  241  to output a first image signal and a second image signal. The first image gathering unit  231  includes an optical signal converting unit  2311 , a second switch S 12 , a third switch S 13  and a fourth switch S 14 , a fifth switch S 15 , a first charge storage element C 11  and a second power storage element C 12 . The optical signal converting unit  2311  includes a reset voltage Vrst, a switch S 11 , an operational amplifier O 11 , and an image sensing element D 1 . The optical signal converting unit  2311  receives the first control signal RST to actuate the first switch S 11  and then reset the optical signal converting unit  2311  by the reset voltage Vrst so that the image sensing element D 1  senses an image which is then transmitted to the operational amplifier O 11  to amplify and to obtain a first image signal and a second image signal. The operational amplifier O 11  sends the first image signal to the first charge storage element C 11  for storage through the second switch S 12 , and sends the second image signal to the second power storage element C 12  for storage through the third switch S 13 . In one embodiment of the invention, the first image signal is a light signal and the second image signal is a dark signal. The second switch S 12  operates according to the second control signal SHR to store the first image signal in the first power storage element C 11 . The third switch S 13  operates according to the third control signal SHS to store the second image signal in the second power storage element C 12 . The fourth S 14  and the fifth switch S 15  receive the output control signal TG 1  from the shift register  241 , and output the first image signal stored in the first power storage element C 11  and the second image signal stored in the second power storage element C 12  respectively through the first image output wiring OUTP and the second image output wiring OUTN. 
         [0024]    Similarly, the second image gathering unit  232  receives the first control signal RST to control an internal optical signal converting unit (not shown). The second signal SHR and the third control signal SHS control an internal second switch and third switch (not shown) to store the first image signal and the second image signal. The output control signal TG 2  from the shift register  242  controls an internal fourth switch (not shown) and a fifth switch (not shown). The first image output wiring OUTP and the second image output wiring OUTN output the first image signal and the second image signal of the second image gathering unit  232 . Similarly, the n th  image gathering unit  23   n  receives the output control signal TGn to output the first image signal and the second image signal of the nth image gathering unit  23   n.    
         [0025]    In the signal combing unit  27 , the fourth control signal CLK from the control unit  21  and the first image signal and the second image signal from the image gathering units  231 - 23   n  are combined.  FIG. 4A  is a circuit diagram showing a signal combining unit according to a first embodiment of the invention. The signal combining unit  27 A includes a double-input/output operational amplifier O 27 , a sixth switch S 6 , a seventh switch S 7 , a capacitor C 271 , and a capacitor C 272 . The sixth switch S 6  connects to the capacitor C 271  in series, and further connects to the first signal receiving terminal IN 1  and a first output terminal OT 1  of the operational amplifier O 27 . The seventh switch S 7  connects to the capacitor C 272  in series, and further connects to a second signal receiving terminal IN 2  and a second output terminal OT 2  of the operational amplifier O  27 . The first signal receiving terminal IN 1  connects to the first image output wiring OUTP to receive the first image signal. The second output terminal OT 2  connects to the second image output wiring OUTN to receive the second image signal. The sixth switch S 6  and the seventh switch receive the fourth control signal to rest the first image output wiring OUTP and the second image output wiring OUTN. Meanwhile, the operational amplifier O 27  receives the first image signal and the second image signal, and then respectively generates a first combined signal and a second combined signal. The first output terminal OT 1  and the second output terminal OT 2  respectively output the first combined signal and the second combined signal, the difference between which, are then calculated. 
         [0026]      FIG. 4B  is a circuit diagram of a signal combining unit according to a second embodiment of the invention. The signal combining unit  27 B includes a first operational amplifier O 271 , a second operational amplifier O 272 , a eighth switch S 8 , a ninth switch S 9 , a capacitor C 273 , and a capacitor C 274 . The eighth switch S 8  connects to the capacitor C 273  in series, and further connects to the first signal receiving terminal IN  71  and the first output terminal OT 71  of the first operational amplifier O 271 . The ninth switch S 9  connects to the capacitor C 274  in series and further connects to the second signal receiving terminal IN 72  and the second output terminal OT 72  of the second operation amplifier O 272 . The first signal receiving terminal IN 71  connects to the first image output wiring OUTP to receive the first image signal. The second output terminal OT 72  connects to the second image output wiring OUTN to receive the second image signal. The first other terminals of the first operational amplifier O 271  and the second operational amplifier O 272  connect to a constant bias Vref. The eighth switch S 8  and the ninth switch S 9  respectively receive the fourth control signal to reset the first image output wiring OUTP and the second image output wiring OUTN. Meanwhile, the first operational amplifier O 271  and the second operational amplifier O 272  respectively receive the first image signal and the second image signal. The first operational amplifier O 271  generates the first combined signal based on the first image signal and then outputs the first combined signal through the first output terminal OT 71 . The second operational amplifier O 272  generates the second combined signal based on the second image signal and then outputs the second combined signal through the second output terminal OT 72 . 
         [0027]      FIG. 5  is a timing diagram of a normal resolution signal of a resolution switch circuit for an image sensor according to one embodiment of the invention.  FIG. 5A  is a block diagram of a resolution switch circuit for an image sensor under normal resolution conditions according to one embodiment of the invention. Although the invention is illustrated by exemplifying the resolution switch circuit of 1×8 in array, the size of the array used in the resolution switch circuit according to the invention is not limited to 1×8. 
         [0028]    When the resolution switch circuit is operating under normal resolution conditions, the control unit  21  sends out the first control signal RST, the second control signal SHR, and the third signal SHS. Each of the image gathering units  231 - 238  accordingly generates the first image signal and the second image signal which are then stored in the power storage element of corresponding image gathering units  231 - 238 . Since the resolution is under normal conditions (m=1), the resolution control unit  25  does need a resolution control signal for CC 1 , wherein the number of the resolution control signal is 2 m−1 . The shift registers  241 - 248  in turn generate output control signals TG 1 -TG 8 . By means of using the output control signals TG 1 -TG 8  to actuate the fourth switch and the fifth switch of respective image gathering units  231 - 238 , the image gathering units  231 - 238  in turn transmit the stored first image signal and the stored image signal to the signal combining unit  27  through the first image output wiring OUTP and the second image output wiring OUTN, as shown in  FIG. 3 . 
         [0029]      FIG. 6  is a timing diagram of a resolution switch circuit at ½ resolution according to another embodiment of the invention.  FIG. 6A  is a block diagram of a resolution switch circuit at ½ resolution according to another embodiment of the invention. In a case in which the resolution is lowered down to ½ of the normal resolution value, the control unit  21  sends out the first control signal RST, the second control signal SHR and the third control signal SHS so that each of the image gathering units  231 - 238  generates the first image signal and the second image signal which are then stored in the power storage element of the corresponding image gathering units  231 - 238 . The resolution control unit  25  needs two resolution control signals for CC 1  and CC 2  for the normal resolution condition and ½ resolution condition (m=2). Next, the shift registers  241 - 248  in tuni generate the output control signals TG 1 , TG 2 , the output signals TG 3 , TG 4 , the output control signal TG 5 , TG 6  and the output control signals TG 7 , TG 8 . The fourth switch and the fifth switch of the first image gathering unit  231  and the second image gathering unit  232  are actuated first. Then the fourth switch and the fifth switch of the third image gathering unit  233  and the fourth image gathering unit  234  are actuated. Then the fourth switch and fifth switch of the fifth image gathering unit  235  and the sixth image gathering unit  236  are actuated. The fourth switch and the fifth switch of the seventh image gathering unit  237  and the eighth image gathering unit  238  are actuated. In this way, the image gathering units  231 - 238  in turn transmit the stored first image signal and the second image signal to the signal combining unit  27  through the first image output wiring OUTP and the second image output wiring OUTN so as to lower the resolution value. 
         [0030]      FIG. 7  is a timing diagram of a resolution switch circuit at ¼ resolution according to another embodiment of the invention.  FIG. 7A  is a block diagram of a resolution switch circuit at ¼ resolution according to another embodiment of the invention. In the case that the resolution is lowered down to ¼ of normal resolution value, the control unit  21  sends out the first control signal RST, the second control signal SHR and the third control signal SHS so that each of the image gathering units  231 - 238  generate the first image signal and the second image signal which are then stored in the power storage element of the corresponding image gathering units  231 - 238 . The resolution control unit  25  needs four resolution control signals for CC 1 , CC 2 , CC 3  and CC 4  for the normal resolution condition, ½ resolution condition and ¼ resolution condition (m=3). Next, the shift registers  241 - 248  in turn generate the control signals TG 1 , TG 2 , TG 3 , TG 4 , and the output control signal TG 5 , TG 6 , TG 7 , TG 8 . The fourth switch and the fifth switch of the first image gathering unit  231 , the second image gathering unit  232 , the third image gathering unit  233 , and the fourth image gathering unit  234  are actuated first. Then the fourth switch and fifth switch of the fifth image gathering unit  235 , the sixth image gathering unit  236 , the seventh image gathering unit  237 , and the eighth image gathering unit  238  are actuated. In this way, the image gathering units  231 - 238  in turn transmit the stored first image signal and the second image signal to the signal combining unit  27  through the first image output wiring OUTP and the second image output wiring OUTN so as to lower the resolution value. 
         [0031]    It should be apparent to those skilled in the art that the above description is only illustrative of specific embodiments and examples of the present invention. The present invention should therefore cover various modifications and variations made to the herein-described structure and operations of the present invention, provided they fall within the scope of the present invention as defined in the following appended claims.