Abstract:
A CCD imager includes a plurality of photoresponsive elements producing signal charges in response to light, a plurality of scanning charge transfer elements, each having a gate electrode, for receiving signal charges from the photoresponsive elements and for transferring the signal charges, and a plurality of serially connected inverter circuits, the outputs of respective inverter circuits being connected to corresponding gate electrodes of the charge transfer elements. The charge transfer is completed within the delay times of the inverters so that the charge transfer for all scanning elements can be completed without the mixing of charges from potential wells beneath adjacent gate electrodes.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a CCD imager, and more particularly to a construction of a driving circuit therefor. 
     BACKGROUND OF THE INVENTION 
     A construction of a conventional CCD imager will be described with reference to FIGS. 5 to 7. FIG. 5 is a cross-sectional view showing a construction of a conventional CCD imager and FIG. 7 is a plan view showing the device of FIG. 5. 
     In FIGS. 5 and 6, the conventional CCD imager is constituted by a semiconductor substrate 1, a silicon dioxide film 2 produced on the semiconductor substrate 1, and polycrystalline silicon gates 3 produced on the silicon dioxide film 2. In the figure drawn in the semiconductor substrate 1, reference numeral 4 designates a potential barrier against electron flow and reference numeral 5 designates signal charges. In FIG. 7, reference numeral 3 designates a polycrystalline silicon gate and reference numeral 6 designates a photodiode. 
     As is understood from FIGS. 5 to 7, in order to transfer charges stored at the photodiode 6, the number of CCD transfer gates required for one photodiode is &#34;4&#34;. That is, when constructing an imager using a two-phase or four-phase driving system CCD, four gates are required to carry out the transfer of charges and if the number of gates is less than that, mixing of charges occurs. Also, in a three-phase driving system CCD, three gates are required to carry out the transfer of charges. The two-phase driving system is most generally used because only two kinds of input clocks are required. 
     In an imager, it is desirable that the density of pixels increase and it is preferred that the number of CCD transfer gates be reduced compared to the increase in the number of pixels. With these goals in mind, a new CCD driving system is proposed in an article by A. J. P. Theuwissen et al, &#34;The Accordion Imager: an Ultra High Density Frame Transfer CCD&#34;, IEDM 84, Lec.No.2.6, Prescripts pp. 40 to 43. 
     FIGS. 8(a)-8(n) show a structure and a manner driving of the accordion system CCD device described in that article. In FIGS. 8(b)-8(h), potentials at times t 1  to t 7 , respectively, are shown. At time t 1 , charges exist at all potential wells. That is, two gate electrodes are provided corresponding to signal charges stored at one photodiode and this structure is very advantageous for integration of photodiodes. When the transfer is started after time t 2 , charges successively move from the output side. 
     FIG. 9 shows clock inputs for realizing the operation shown in FIGS. 8(b)-8(n). In FIG. 9, high and low voltages are alternatingly applied to respective electrodes at time t 1   and in correspondence with the advance of time as t 2 , t 3 , . . . , the clocks applied to respective electrodes are successively inverted from the output side. Shift registers connected to respective electrodes include a circuit as shown in FIG. 10, that is, a CMOS inverter 14 including P and N channel transistors 15 and 16, respectively, and an N channel transistor 17 connected to the input terminal of the inverter 14. 
     FIG. 11(a) shows a circuit diagram in which the circuit of FIG. 10 is connected as is actually used. In FIG. 11(b) while in the stationary state where input clocks φ IN  do not change, the voltages on the electrodes after the input clock φ IN  are regularly and alternatingly high(H) or low(L), when the input clock φ IN  changes from H to L or from L to H, the change is transferred as a voltage change of the electrode after the clock φ 1  in synchronization with the two driving clocks φ A , φ B . It is possible to realize the potential distribution shown in FIGS. 8(b)-(n) by using these clock inputs. In FIG. 11(b), the L or H clock whose voltage is changed is surrounded by a circle (◯) in order to clarify the transfer of the voltage change. 
     The conventional CCD imager is constructed as described above, and clocks φ A , φ B  for driving the shift registers, the switching transistors and inverters corresponding to respective electrode gates are required, thereby complicating the circuit construction. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to solving the above-described problems and has for its object the provision of a CCD imager having a simplified circuit construction. 
     Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and the scope of the invention will become apparent to those skilled in the art from this detailed description. 
     In accordance with the present invention, a plurality of inverters are serially connected, output terminals of respective inverters are connected to the corresponding gate electrodes of the charge transfer device. Charge transfer is completed in the delay time of an inverter output after the input of the input signal thereto. Therefore, the charge transfer for all stages can be completed without mixing of charges in adjacent potential wells in a simple circuit construction. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1(a) is a diagram showing a construction and FIG. 1(b)-1(g) show operation waveforms of a CCD imager in accordance with an embodiment of the present invention; 
     FIG. 2(a) is a diagram showing a structure, and FIG. 2(b) is a step input signal and the output waveform of an inverter in response to the input signal of FIG. 2(b) used in a CCD imager according to an embodiment of the invention; 
     FIGS. 3, 4(a), and 4(b) are circuit diagrams showing inverters used in a CCD imager according to an embodiment of the invention; 
     FIG. 5 is a cross-sectional view showing a conventional four-phase driving system CCD imager; 
     FIG. 6 is a cross-sectional view showing a conventional two-phase driving system CCD imager; 
     FIG. 7 is a plan view of the CCD imager shown in FIG. 5; 
     FIG. 8(a) is a diagram showing a construction and FIGS. 8(b)-8(h) illustrate the manner driving of a conventional accordion CCD imager; 
     FIG. 9 is a diagram showing clock inputs for realizing the operation of the CCD shown in FIG. 9; 
     FIG. 10 is a diagram showing shift registers used in the conventional CCD imager; 
     FIG. 11(a) is a schematic diagram and FIG. 11(b) is a diagram of clock inputs for a conventional CCD imager; 
     FIG. 12 is a diagram showing a detailed construction of the CCD imager shown in FIG. 1; and 
     FIG. 13 is a circuit diagram showing a bipolar inverter used in a CCD imager according to an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will be described in detail with reference to the drawings. 
     FIG. 1(a) shows a construction of a CCD imager in accordance with a first embodiment of the present invention and FIG. 1(b)-1(g), shows an operation diagram thereof. The construction of the device will be described in detail with reference to FIG. 12. In FIG. 12, reference numeral 101 designates a photodiode and numeral 103 designates a CCD. A transfer gate 102 is provided between the photodiodes 101 and the CCDs 103 for storing and transferring signal charges generated by the photodiodes 101 to the CCDs 103. A reset gate 104 is provided at an end of the sequence of CCDs 103 and a floating diffusion amplifier 105 (hereinafter referred to as &#34;FDA&#34;) is connected to the end of the CCD sequence 103 between the CCD sequence 103 and the reset gate 104. A final gate 106 is provided at the end of the CCD sequence 103 before the reset gate 104 and the connection to the FDA 105. CMOS inverter circuits 107 are connected in series and respective nodes of connected input and output terminals of a pair of inverter circuits 107 are connected in parallel to respective CCDs in the sequence 103. Reference character V out  designates a signal output. Reference character V dd  designates a power supply input and reference character V ss  designates a ground input. Reference character V ga  designates a gate input to the FDA driving the transistors of the FDA. Reference character V r  designates a reset potential and reference character φ r  designates a reset input. Reference character φ in  designates an input clock and reference character V tg  designates an input to the transfer gate 102. 
     FIG. 2(a) shows a schematic diagram and FIG. 2(b) shows a delay operation waveform of an inverter used in the CCD imager of the first embodiment of the present invention. FIGS. 3, 4(a) and 4(b) show inverter circuits which are used in the embodiment. FIG. 3 shows a ratioless inverter 7 constituted by a P channel transistor 8 and an N channel transistor 9. FIG. 4(a) shows an N (or P) channel MOS ratio inverter constituted by a depletion N (or P) channel transistor 10 and an enhancement N (or P) channel transistor 11 and FIG. 4(b) shows an N (or P) MOS ratio inverter constituted by an enhancement N (or P) channel transistor 12 and an enhancement N (or P) channel transistor 13. In these figures, the same reference numerals as those in FIGS. 5 to 11(a) designate the same or corresponding portions. 
     Usually, the input/output characteristics of the inverter 7 has a time delay in the output relative to a step input. That is, as shown in FIG. 2, if time delays are represented by t d1 , t d2 , these time delays, t d1 , t d2  can be represented by charge/discharge characteristics of the load capacitance on the switching of MOS transistors. For example, in a case of ratioless inverter using the depletion transistor shown in FIG. 4(a), the time delays t d1 , t d2  are approximated as 
     
         t.sub.d1 =4 C.sub.L /β.sub.D V.sub.DD                 (1) 
    
     
         t.sub.d2 =4 C.sub.L /β.sub.L V.sub.DD                 (2) 
    
     (Reference: J. Meyber et al., translated by Takuo Sugano et al., &#34;Introduction of MOSLSI design&#34;, by Sangyo Tosho, 1984, pp. 58 to 65.). 
     Here, C L  designates the capacitance produced between the output terminal (OUT) and the ground terminal, β D  designates the gain of the enhancement type N (or P) channel transistor 11, and β L  designates the gain of the depletion type N (or P) channel transistor 10. 
     The above-described gains β D , β L  depend on the configuration of the channel of the transistor. When the channel length is L and the channel width is W, the gains respectively: 
     
         β.sub.D =μ.sub.N C.sub.o (W.sub.D /L.sub.D)        (3) 
    
     
         β.sub.L =μ.sub.N C.sub.o (W.sub.L /L.sub.L)        (4) 
    
     Here, the subscripts  D , L  of the gain β means driving transistor and load transistor, respectively. 
     In addition, μ N  and C o  designate the mobility of electrons in the inverted layer and the capacitance of the gate insulating film, respectively. In addition, W D  and W L  designate channel widths and L D  and L L  designate the channel lengths of the transistors 11 and 10, respectively. 
     When the time delays t d1 , t d2  are calculated by using typical values, the following are obtained: 
     
         μ.sub.N =8×10.sup.-2 m.sup.2 V.sup.-1 S.sup.-1 
    
     
         C.sub.O =8.5×10.sup.-4 Fm.sup.-2 
    
     
         C.sub.L =0.1×10.sup.-12 F 
    
     
         V.sub.DD =5V 
    
     When 
     W D  /L D  =1, W L  /L L  =1, 
     t d1  =2.9 [ns], t d2  =2.9 ns 
     When 
     W D  /L D  =1/5, W L  /L L  =1/5, 
     t d1  =14 [ns], t d2  =14 ns. 
     As described above, the time delays t d1 , t d2  can be controlled by the configuration of channels of the transistors used in the inverters. Further, that the time delays t d1 , t d2  be longer than the time required for the transfer of charges per stage is a condition required for the operation of the device of the present invention. 
     A description is given of the time required for the transfer of charges. 
     A Buried Channel CCD (hereinafter referred to as &#34;BCCD&#34;) is most widely used for transferring charges. In a BCCD, charge the transfer by a fringing electric field is the most important. In accordance with a reference by Tetsuo Tsukamoto, &#34;Fundamentals of CCD&#34;, Ohm-sha, Electronics Bunko, pp. 81, the time constant τ f  representing the degree of attenuation of charges below the gate in the transfer by a fringing electric field is represented by the following: 
     
         τ.sub.f =L.sup.3 /3.2μ. V·d 
    
     Here, L represents transfer gate length, μ designates electron mobility, V designates clock voltage, and d represents the thickness of the insulating film. 
     For example, when L, μ, V, and d are 7 μm, 400 cm 2  /v.19 sec, 10 V, and 1000 Å, respectively, in the above-described formula, τ f  becomes 2.7 ns. This value is about one-fifth of the result of calculation of t d1 , t d2  and it is possible to further increase this ratio (τ f  /t d1  (t d2 )) by optimizing the configurations of the transistors and the CCDs. 
     A description is given of the operation hereinafter. 
     It is apparent that the CCD imager of this embodiment can operate in a good manner from the above-described calculation. 
     That is, as shown in FIGS. 1(b)-1(g), at time t 0  before starting the charge transfer, low level and high level voltages alternatingly applied to the respective transfer gates and the charges to be transferred are present below the alternating transfer gates 3 which are at high level voltage. 
     At time t 1  when charge transfer starts, when the voltage level of the transfer gate A at the output side of the CCD register is switched to high level from low level, the charges stored below the gate B adjacent the transfer gate A start to move toward gate A and subsequently after a predetermined time t d1  which is determined by the circuit constant of the inverter 7, when the voltage level of gate B is switched from high level to low level, the movement of charges stored gate B to the adjacent gate A is completed. Then, the above described operation is repeated with the next delay time t d2 . 
     By switching the transfer voltage level on the inverter sequence with a predetermined delay time, charges are sequentially transferred to the adjacent gate from the CCD output side. 
     As described above, in this embodiment the inverters 7 lengthen the delay time by optimizing the structure of the transistor are connected in series. The CCDs 103 are also serially connected. The outputs of the respective serially connected inverters are connected to the corresponding electrodes of the CCDs. Therefore, the transfer clock is required to provide only one trigger for the charge transfer sequence and a switching transistor, like transistor 17 of FIGS. 10 and 11(a), is not required. Therefore, the circuit is simplified and a CCD imager of high pixel density is realized. 
     In the above-described embodiment a ratio-type inverter shown in FIG. 4(a) is used as an inverter, but a ratio-type inverter shown in FIG. 4(b) or a non-ratio type inverter shown in FIG. 3 or a bipolar type inverter, like inverter 18, shown in FIG. 13 can be used with the same effects. 
     In the above-described embodiments a buried type CCD is described but a surface channel type CCD can be also used in the present invention. 
     As is evident from the foregoing description, according to the present invention, a plurality of inverters are serially connected as delay circuits and are connected in parallel to the respective gate electrodes of the charge storage and transfer devices. The delay time of the inverter is longer than the time required for the transfer of charges per one stage. Therefore, switching transistors are dispensed with and only one driving clock is required. Therefore, the circuit construction is simplified and a CCD imager appropriate for high integration is obtained.