Abstract:
A clock generation system for deriving a second clock signal from a first clock signal with a predetermined clock frequency ratio, where the first clock frequency is divided by a first integer, the second clock signal is divided by a second integer, an error signal is generated by comparing the division results, a voltage-controlled oscillator is controlled in dependence on said error signal to generate the second clock signal, and a switch is provided for alternately switching each of the clock signals to a single frequency divider or for alternately switching one of the clock signals to one of two frequency dividers and simultaneously switching the other one of the clock signals to the other one of the two frequency dividers to eliminate errors that may result from processing the two clock signals in different circuit sections.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates clock generators and, more particularly, to a clock generation system for generating a first clock signal at a first clock frequency and a second clock signal at a second clock frequency with a predetermined ratio to said first clock frequency, where the system comprises a clock signal generator providing the first clock signal, a frequency divider device having at least one frequency divider for dividing the first clock frequency by a first integer to produce a first auxiliary signal and for dividing the second clock signal by a second integer to produce a second auxiliary signal, a phase/period comparator configured to generate an error signal by comparing the first and second auxiliary signals, and a voltage-controlled oscillator controlled in dependence on the error signal to generate the second clock signal. 
     2. Description of the Related Art 
     EP 2 207 263 A1 discloses two clock generator systems for generating second clock signals with slightly different frequency ratios to the first clock signal so that the second clock signals have slightly different frequencies. Given suitable selection of integer divisors of the clock system, a single such system may be used to generate the second clock signal with the desired slightly different frequency to the first clock signal. 
     In such a conventional system, the first and second clock signals are processed by different circuit sections before reaching the phase/period comparator. Therefore, any mismatch between the different circuit sections, such as different propagation delay times or offset voltages due to manufacturing tolerances, thermal drift or aging, may result in an error of the wanted frequency ratio between the first and second clock signals. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to overcome the prior art drawbacks and to provide two clock signals with a defined and stable frequency ratio. 
     This and other objects and advantages are achieved in accordance with the invention by providing a clock generation system with a switch for alternately switching each of the first and second clock signals to a single frequency divider or for alternately switching one of the first and second clock signals to one of two frequency dividers and simultaneously switching the other one of the first and second clock signals to the other one of the two frequency dividers, and a controller for controlling the at least one frequency divider to perform a division with the first integer when the first clock signal is provided and to perform the division with the second integer when the second clock signal, and a phase/period comparator that is configured to generate an error signal (ERR) from the comparison of first and second auxiliary signals obtained from two consecutive positions of the switch. 
     In accordance with the invention, the switch alternately and successively couples the first and second clock signals to the only signal path or, in case of different signal paths, to the different signal paths between the switch and the phase/period comparator. As a result, any error in the signal path or signal will affect both clock signals equally and will be compensated by the comparison in the phase/period comparator. 
     Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will be now further described by way of preferred example and with reference to the accompanying drawing, in which: 
         FIG. 1  shows an exemplary schematic block diagram of a clock generation system in accordance with the invention; 
         FIG. 2  shows an alternative exemplary schematic block diagram of a clock generation system in accordance with an embodiment of the invention; 
         FIG. 3  is an exemplary schematic block diagram of a phase/period comparator forming part of the clock generation system of  FIG. 1 ; 
         FIG. 4  is an alternative exemplary embodiment of a schematic block diagram of a phase/period comparator forming part of the clock generation system shown in  FIG. 1 ; and 
         FIG. 5  is an exemplary embodiment of a phase/period comparator forming part of the alternative exemplary clock generation system shown in  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1  shows a clock generation system in which a clock signal generator  1  provides a first clock signal CLK 1  at a clock frequency f 1 . The first clock signal CLK 1  is applied to a first input of a switch  2  that comprises a change-over switch or two-to-one multiplexer having two inputs and one output. The output of the switch  2  is connected to a frequency divider device  3  which comprises a single frequency divider  4  and the output of which is supplied to a phase/period comparator  5 . The phase/period comparator  5  generates an error signal ERR and controls a voltage-controlled oscillator (VCO)  6  to generate a second clock signal CLK 2  having a clock frequency f 2 . The voltage-controlled oscillator  6  is controlled such that the clock frequency f 2  is maintained constant when the error signal ERR is zero, while it is otherwise changed. The second clock signal CLK 2  is fed back to the second input of the switch  2 . The switch  2 , frequency divider  4 , phase/period comparator  5  and voltage-controlled oscillator  6  are controlled by a control signal CTRL of a controller  7 . 
     The controller  7  controls the switch  2  to alternately couple either the first clock signal CLK 1  or the second clock signal CLK 2  to the frequency divider  4 . 
     The controller  7  further controls the frequency divider  4  to perform a division with a first integer N when the first clock signals CLK 1  is provided and to perform a division with the second integer M when the second clock signal CLK 2  is provided. Accordingly, the divider alternately produces a first auxiliary signal CLK 11  at a frequency f 1 /N and a second auxiliary signal CLK 21  at a frequency f 2 /M. 
     The phase/period comparator  5  is configured and controlled to generate the error signal ERR by comparing the first and second auxiliary signals CLK 11  and CLK 21  obtained from two consecutive positions of the switch  2 . After every two measurements, one for CLK 11  and one for CLK 21 , the control voltage of the voltage-controlled oscillator  6  is adjusted by an amount proportional with ERR so that the control voltage changes from a previous value V i−1  to a next value V i , where V i =V i−1 −k·ERR. In this way, the voltage-controlled oscillator  6  is successively adjusted to bring and maintain the frequencies f 1  and f 2  in-line with the relation N/f 1 =M/f 2  or f 1 /f 2 =N/M. 
     If there is any error (e.g., error E) in the signal path between the switch  2  and the phase/period comparator  5  or, more precisely, the place of comparison within the phase/period comparator  5 , this error E will affect both auxiliary signals CLK 11  and CLK 21  equally and will be eliminated by the comparison: E·N/f 1 =E·M/f 2  or N/f 1 =M/f 2  or f 1 /f 2 =N/M. 
       FIG. 2  shows another clock generation system in which a clock signal generator  1  provides a first clock signal CLK 1  at a clock frequency f 1 . The first clock signal CLK 1  is applied to a first input of a switch  21  that is comprises a crossover switch having two inputs and two outputs. Each output of the switch  21  is connected to one of two frequency dividers  41  and  42  of a frequency divider device  3 , the outputs of which are supplied to a phase/period comparator  5 . The phase/period comparator  5  generates an error signal ERR and controls a voltage-controlled oscillator (VCO)  6  to generate a second clock signal CLK 2  having a clock frequency f 2 . The second clock signal CLK 2  is fed back to the second input of the switch  21 . The switch  21 , frequency dividers  41 ,  42 , phase/period comparator  5  and voltage-controlled oscillator  6  are controlled by a control signal CTRL of a controller  7 . 
     The controller  7  controls the switch  21  to alternately couple one of the first and second clock signals CLK 1 , CLK 2  to one of two frequency dividers  41 ,  42  and simultaneously switch the other one of the first and second clock signals CLK 1 , CLK 2  to the other one of the two frequency dividers  41 ,  42 . 
     The controller  7  further controls the frequency dividers  41  and  42  to perform a division with a first integer N where the first clock signals CLK 1  is provided and to perform a division with the second integer M where the second clock signal CLK 2  is provided. Accordingly, the divider  41  produces alternately a first auxiliary signal CLK 11  at a frequency f 1 /N and a second auxiliary signal CLK 21  at a frequency f 2 /M while the other divider  42  alternately produces the second auxiliary signal CLK 21  at the frequency f 2 /M and the first auxiliary signal CLK 11  at the frequency f 1 /N. 
     The phase/period comparator  5  is configured and controlled to generate the error signal ERR by comparing the first and second auxiliary signals CLK 11  and CLK 21  obtained from two consecutive positions of the switch  2 . For example, the phase/period information of the first auxiliary signal CLK 11  consecutively provided by the first and second dividers  41 ,  42  are added up. In the same way, the phase/period information of the second auxiliary signal CLK 21  consecutively provided by the second and first dividers  42 ,  41  are summed. The summed-up information of the first auxiliary signal CLK 11  and that of the second auxiliary signal CLK 21  are then compared to generate the error signal ERR. Consequently, after every two measurements, the control voltage of the voltage-controlled oscillator  6  is adjusted by an amount proportional with ERR so that the control voltage changes from a previous value V i−1  to a new value V i , where V i =V i−1 −k·ERR. In this way, the voltage-controlled oscillator  6  is successively adjusted to bring and maintain the frequencies fl and f 2  in-line with the relation N/f 1 =M/f 2  or f 1 /f 2 =N/M. 
     If there is any error, e.g. E 1 , in the signal path from the switch  2  via the first divider  41  to the phase/period comparator  5 , this error E 1  will affect both auxiliary signals CLK 11  and CLK 21  equally. In the same way, if there is any error, e.g. E 2 , in the signal path from the switch  2  via the second divider  42  to the phase/period comparator  5 , this error E 2  will affect both auxiliary signals CLK 11  and CLK 21  equally. Thus, the errors E 1 , E 2  will be compensated by the comparison:
 
( E 1· N/f 1)+( E 2· N/f 1)=( E 1· M/f 2)+( E 2· M/f 2) or  N/f 1= M/f 2 or  f 1/ f 2= N/M.  
 
     Whereas in the simplest case the phase/period comparator  5  is of digital type, it may be of any other type, digital only or digital and analog combined. For example, if a ratio f 1 /f 2 =N/M near but not equal to 1 is wanted, integer values N, M must be large, e.g. N=300000 and M=299997, which may result in a long response time for adjusting the frequency f 2  of the second clock signal CLK 2 . In such a case, it may be advantageous to individually weight the detected cycle durations or phasing of the first and second auxiliary signals CLK 11 , CLK 21  by analog factors G 1 , G 2  before they are compared to generate the error signal ERR. The voltage-controlled oscillator  6  then adjusts and maintains the relation G 1 ·N/f 1 =G 1 ·M/f 2  or f 1 /f 2 =G 1 /G 2 ·N/M. 
     Thus, the compensation of the error E in the clock generation system of  FIG. 1  results to:
 
 E·G 1· N/f 1= E·G 2· M/f 2 or  G 1· N/f 1= G 1· M/f 2 or  f 1/ f 2= G 1 / G 2· N/M.  
 
     The compensation of the errors E 1  and E 2  in the clock generation system of  FIG. 2  results to:
 
( E 1· G 1· N/f 1)+( E 2· G 1· N/f 1)=( E 1· G 2· M/f 2)+( E 2· G 2· M/f 2) or  G 1· N/f 1= G 1· M/f 2 or  f 1/ f 2= G 1/ G 2· N/M.  
 
       FIG. 3  shows an example of a mixed analog and digital design of the phase/period comparator  5  together with the input section of the voltage-controlled oscillator  6  of the clock generation system shown in  FIG. 1 . The phase/period comparator  5  comprises a time-to-voltage converter  8  which alternately in succession coverts the phase/period information of the first and second auxiliary signal CLK 11 , CLK 21  into a voltage. This may be done in a known way by charging a capacitor with a constant current during a time interval to be measured. A variable gain amplifier  9  alternately weights the voltage obtained from the first auxiliary signal CLK 11  by the factor G 1  and the voltage obtained from the second auxiliary signal CLK 21  by the factor G 2 . The weighted voltages are buffered in sample-and-hold circuits  10 ,  11  and provided to a first differential amplifier  12  which produces the error signal ERR. 
     The input section of the voltage-controlled oscillator  6  comprises a second differential amplifier  13  whose output is fed back through a sample-and-hold circuit  14  to its one input and which receives at the other input the error signal ERR. After every two measurements, the control voltage of the voltage-controlled oscillator  6  is adjusted by an amount proportional with ERR so that the control voltage changes from the previous value V i−1  to a new value NA, where V i =V i−1 −k·ERR. 
     The timing of the components  8 ,  9 ,  10 ,  11 ,  12 ,  13 ,  14  and the application of the gain factors G 1  and G 2  are controlled by the control signal CTRL. 
     Any error in the signal path between the switch  2  (see  FIG. 1 ) and the first differential amplifier  12  (see  FIG. 3 ) will be compensated as described above with reference to  FIG. 1 . 
       FIG. 4  shows an alternative exemplary schematic block diagram of the above-described mixed analog and digital phase/period comparator  5 , where the variable gain amplifier  9  and sample-and-hold circuits  10 ,  11  are replaced by an analog-to-digital converter  15  and where the differential amplifiers  12 ,  13  and sample-and-hold circuit  14  are replaced by a digital processor  16 . In all other respects, the phase/period comparator  5  works in a manner as described above. 
       FIG. 5  shows an exemplary schematic block diagram of a mixed analog and digital circuit of the phase/period comparator  5  of the clock generation system shown in  FIG. 2 . Here, the phase/period comparator  5  comprises a first time-to-voltage converter  81  connected to the output of the first frequency divider  41  (see  FIG. 2 ) and a second time-to-voltage converter  82  connected to the output of the second frequency divider  42 . The time-to-voltage converters  81  and  82  are connected to a differential amplifier  17  that has the variable gain functionality corresponding to that of the variable gain amplifier  9  of  FIG. 3 . The control voltage for the voltage controlled oscillator is adjusted the same way as described above for the phase/frequency comparator in  FIG. 3 . 
     Thus, while there have shown and described and pointed out fundamental novel features of the invention as applied to a preferred embodiment thereof, it will be understood that various omissions and substitutions and changes in the form and details of the devices illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit of the invention. For example, it is expressly intended that all combinations of those elements which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and/or elements and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.