Abstract:
A signal sampling apparatus for generating an output signal according to an input signal is disclosed. The signal sampling system includes a sample and hold circuit and a gain controller. The sample and hold circuit is used for sampling the input signal to generate a sample signal in a sample mode, and the sample and hold circuit includes an amplifier having a gain for generating the output signal according to the sample signal in a hold mode. The gain controller is coupled to the amplifier for adjusting the gain in the sample mode.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates to a signal sampling apparatus, and more particularly, to a signal sampling apparatus having a sample and hold circuit.  
         [0003]     2. Description of the Prior Art  
         [0004]     Sample and hold circuits have been utilized in many circuits. For example, a sample and hold circuit can be utilized in an analog to digital converter, placed inside an optical disk drive in order to detect amplitudes of reading signals, or placed in the transmitter of a communication device.  
         [0005]     Please refer to  FIG. 1 , which is a diagram of a sample and hold circuit  100  according to the prior art. As shown in  FIG. 1 , the sample and hold circuit  100  comprises an operational amplifier  110 , a plurality of switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 , and S 9 , a plurality of sampling capacitors Cs, and a plurality of feedback capacitors Cf. They are connected as shown in  FIG. 1 .  
         [0006]     In a sample mode, the switches S 1 , S 2 , S 5 , S 8 , and S 9  are turned on, and the switches S 3 , S 4 , S 6 , and S 7  are turned off. Please refer to  FIG. 2 , which is a diagram of the sample and hold circuit  100  in the sample mode. At this time, an input signal is inputted into the two input ends of the sample and hold circuit  100 . The input signal is then stored in the sampling capacitors Cs and the feedback capacitors Cf, where the two output ends are limited as differential zero because the switch S 9  is turned on.  
         [0007]     On the other hand, in a hold mode, the switches S 1 , S 2 , S 5 , S 8 , and S 9  are turned off, and the switches S 3 , S 4 , S 6 , and S 7  are turned on. Please refer to  FIG. 3 , which is a diagram of the sample and hold circuit  100  in the hold mode. As shown in  FIG. 3 , in the hold mode, the feedback capacitors form a negative feedback loop. As known by those skilled in the art, the charges stored in the sample mode are redistributed according to the capacitances of the sampling capacitors Cs and the feedback capacitors Cf. Assuming that the sampling capacitors Cs and the feedback capacitors Cf have the same capacitance, the two output ends output the signal sampled in the sample mode.  
         [0008]     Please refer to  FIG. 4 , which is a signal diagram of the sample and hold circuit  100  shown in  FIG. 1 . As shown in  FIG. 4 , a clock ph 1  and a clock ph 2  are respectively utilized to define the sampling mode and the hold mode. In other words, the above-mentioned switches S 1 -S 9  are turned on/off according to the clocks ph 1  and ph 2 . Therefore, at the rising edge of the clock ph 1 , when ph 1  is high and ph 2  is low, the sample and hold circuit  100  samples the input signal and outputs a ground signal (this means that the signal is differential zero) for the switch S 9  is turned on. On the other hand, at the rising edge of the clock ph 2 , when ph 1  is low and ph 2  is high, the sample and hold circuit  100  outputs the signal sampled in the sample mode.  
         [0009]     Generally speaking, in order to provide a high resolution, meaning that to provide an output signal having a large bit number, the operational amplifier  110  is designed to have a high gain. In the sample mode, however, the switch S 9  is utilized to limit the output of the operational amplifier  110  as a differential zero. Therefore, the switch S 9  needs more time to charge/discharge when the gain of the operational amplifier  110  is very large.  
         [0010]     In addition, if the charge/discharge time is more than half the period of the clock ph 1 , this represents that at the rising edge of the clock ph 2 , the output of the operational amplifier  110  is not back to differential zero. This result directly influences the circuit operation in the sample mode. In order to solve this problem, the switch S 9  can be designed to have a bigger size such that the switch S 9  can have a smaller turn-on resistor to reduce the charge/discharge time. This method also increases the chip area, however, and therefore raises costs because of this increased chip area.  
       SUMMARY OF THE INVENTION  
       [0011]     It is therefore one of the objectives of the claimed invention to provide a signal sampling circuit capable of adjusting gain such that the gain of the operational amplifier is appropriately controlled. This allows the signal sampling circuit to not only output a digital signal having a higher resolution, but also to solve the above-mentioned problem of long charge/discharge time due to the high gain.  
         [0012]     According to an exemplary embodiment of the claimed invention, a signal sampling apparatus for generating an output signal according to an input signal is disclosed. The signal sampling apparatus comprises: a sample and hold circuit (S/H circuit), for sampling the input signal in a sample mode to generate a sample signal, the sample and hold circuit comprising an amplifier having a gain for generating the output signal according to the sample signal in a hold mode; and a gain controller, coupled to the amplifier, for adjusting the gain.  
         [0013]     According to an exemplary embodiment of the claimed invention, a signal sampling method for generating an output signal according to an input signal is disclosed. The signal sampling method comprises: sampling the output signal in a sample mode in order to generate a sample signal; generating the output signal according to the sample signal and a gain in a hold mode; and adjusting the gain in the sample mode.  
         [0014]     According to an exemplary embodiment of the claimed invention, a signal sampling apparatus for sampling an input signal to generate an output signal is disclosed. The signal sampling apparatus comprises: a sample and hold unit for performing a sampling operation on the input signal in a sample mode and generating the output signal according to a result of the sampling operation in a hold mode, the sample and hold unit comprising a gain unit for providing a gain; and a gain adjusting unit, coupled to the gain unit, for generating a control signal to adjust the gain.  
         [0015]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a diagram of a sample and hold circuit according to the prior art.  
         [0017]      FIG. 2  is a diagram of the prior art sample and hold circuit in a sample mode.  
         [0018]      FIG. 3  is a diagram of the prior art sample and hold circuit in a hold mode.  
         [0019]      FIG. 4  is a signal diagram of the sample and hold circuit shown in  FIG. 1 .  
         [0020]      FIG. 5  is a functional block diagram of a signal sampling apparatus of an embodiment according to the present invention.  
         [0021]      FIG. 6  is a diagram of the operational amplifier shown in  FIG. 5  of an embodiment according to the present invention.  
         [0022]      FIG. 7  is a diagram of an operational amplifier and the gain controller of a first embodiment according to the present invention.  
         [0023]      FIG. 8  is a diagram of an operational amplifier and a gain controller of a second embodiment according to the present invention.  
         [0024]      FIG. 9  is a diagram of an operational amplifier and a gain controller of a third embodiment according to the present invention.  
         [0025]      FIG. 10  is a diagram of an operational amplifier and a gain controller of a fourth embodiment according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0026]     Please refer to  FIG. 5 , which is a functional block diagram of a signal sampling apparatus  500  of an embodiment according to the present invention. As shown in  FIG. 5 , the signal sampling apparatus  500  comprises a sample and hold circuit  510  and a gain controller  520 , coupled to the sample and hold circuit  510 . In this embodiment, the sample and hold circuit  510  comprises an operational amplifier  530 , a plurality of switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 , and S 9 , a plurality of sampling capacitors Cs, and a plurality of feedback capacitors Cf. As the functions and operations of the sample and hold circuit  510  have been illustrated in the above disclosure, they are omitted here. Please note that the sample and hold circuit  510  shown in  FIG. 5  is only utilized as an embodiment, not a limitation of the present invention.  
         [0027]     In this embodiment, the gain controller  520  is utilized to reduce the gain of the operational amplifier  530  in the sample mode. Therefore, the switch S 9  can successfully pull down the output of the operational amplifier  530  in a predetermined clock period. Furthermore, in the hold mode, the original high gain of the operational amplifier  530  can be recovered. Therefore, the above-mentioned gain controlling operation does not influence the predetermined resolution of the sample and hold circuit  510 . The detailed operations of the gain controller  520  are illustrated in the following disclosure.  
         [0028]     Please refer to  FIG. 6 , which is a diagram of the operational amplifier  530  shown in  FIG. 5  of an embodiment according to the present invention. As shown in  FIG. 6 , the operational amplifier  530  is a differential operational amplifier. The operational amplifier  530  comprises a first input stage  540 , a first gain stage  550 , a second input stage  560 , a second gain stage  570 , and a bias  580 , where the first input stage  540  comprises a transistor M 4 , the first gain stage  550  comprises three transistors M 1 , M 2 , M 3 , the second input stage  560  comprises a transistor M 8 , and second gain stage  570  comprises three transistors M 5 , M 6 , M 7 . The transistors M 1 -M 4  are symmetric to the transistors M 5 -M 8 , where the gates of the transistors M 4  and M 8  are input ends of the operational amplifier  530 , the gates of the transistors M 1 -M 3 , and M 5 -M 7  are respectively controlled by different biasing values. Please note that the node between the transistors M 2  and M 3  and the node between the transistors M 6  and M 7  are the output ends of the operational amplifier  530 . As the functions and the operations of the operational amplifier  530  are well known, they are omitted here.  
         [0029]     As mentioned previously, the gain controller  520  is utilized to adjust the gain of the operational amplifier  530 . Therefore, switches can be utilized to adjust the gain of the operational amplifier.  
         [0030]     Please refer to  FIG. 7 , which is a diagram of the operational amplifier  530  and the gain controller  520  of a first embodiment according to the present invention. As shown in  FIG. 7 , the source and drain of the transistor M 1  are coupled to each other through a switch S 10 , and the source and drain of the transistor M 5  are coupled to each other through a switch S 11 . The gain controller  520  is a control circuit to control the switches S 10  and S 11 , so that the switches S 10  and S 11  correspond to the clock ph 1 , which is utilized to control the above-mentioned switches S 1 , S 2 , S 5 , S 8 , and S 9 . Therefore, the switches S 10  and S 11  are turned on in the sample mode to couple the source and drain of the transistors M 1  and M 5 . This reduces the current gain of the operational amplifier  530  in the sample mode.  
         [0031]     Please refer to  FIG. 8 , which is a diagram of the operational amplifier  530  and the gain controller  520  of a second embodiment according to the present invention. As shown in  FIG. 8 , the source of the transistor M 3  is coupled to the source of the transistor M 7  through a switch S 12 . The switch S 12  also corresponds to the clock ph 1 . This means that the switch S 12  is turned on in the sample mode to couple the sources of the transistors M 3  and M 7 . Therefore, the switch S 12  can also reduce the gain of the operational amplifier  530  in the sample mode.  
         [0032]     Please refer to  FIG. 9 , which is a diagram of the operational amplifier  530  and the gain controller  520  of a third embodiment according to the present invention. As shown in  FIG. 9 , the drain of the transistor M 1  is coupled to the drain of the transistor M 5  through a switch S 13 . The switch S 13  also corresponds to the clock ph 1 . This means that the switch S 13  is turned on in the sample mode to couple the drains of the transistors M 1  and M 5 . Therefore, the switch S 13  can also reduce the gain of the operational amplifier  530  in the sample mode.  
         [0033]     Please refer to  FIG. 10 , which is a diagram of the operational amplifier  530  and the gain controller  520  of a fourth embodiment according to the present invention. In this embodiment, the gain controller  520  is coupled to the bias  580  of the operational amplifier  530 . Therefore, the biasing current, which is outputted by the bias  580 , can be adjusted by the gain controller  520  in the sample mode. This can also reduce the gain of the operational amplifier  530 . The adjustable bias  580  can be implemented through utilizing a plurality of parallel current sources in co-ordination with switches, or other circuits. For the circuit and operations of the adjustable bias are well known, they are omitted here.  
         [0034]     In the above disclosure, the circuits are all differential circuits. However, this is not a limitation of the present invention. In other words, single-ended circuits can also be utilized. Please refer to  FIG. 6  again, for example, the transistors M 1 -M 4  and the bias  580  can be regarded as a single-ended amplifier. Therefore, when the sample and hold circuit  510  is in the sample mode, a switch (not shown) can be utilized to couple the source and the drain of the transistor M 1  such that the gain of the single-ended amplifier can be reduced. On the other hand, the above-mentioned method of controlling the biasing currents can also be utilized to reduce the gain of the single-ended amplifier. This also obeys the spirit of the present invention.  
         [0035]     As known by those skilled in the art, the signal sampling apparatus and related signal sampling method can be utilized in the analog-to-digital converter fields or other fields.  
         [0036]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.