Abstract:
A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor structure further includes a recessed middle-of-line (MOL) oxide layer, and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is positioned over the one or more semiconductor devices and the MOL oxide layer. A nitride layer is positioned over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions. A silicide fills the trenches.

Description:
BACKGROUND 
       [0001]    Nitride stacks are formed by opening contact holes in nitride and oxide layers covering one or more semiconductor devices on a silicon wafer. In a conventional MOL process, the nitride layer is formed to a thickness (e.g., 40 nanometers (nm)) and a thinner oxide layer is formed over the nitride layer (e.g., 10 nm). The oxide and nitride layers are then patterned to open contact holes down to the source/drain regions (also referred to as “active regions”) of the semiconductor devices. In order to reduce the capacitance associated with the post gate (PG) nitride, a thinner nitride layer may be desirable. However, utilizing a thinner nitride layer in a conventional process flow is not feasible because gouging by a chemical mechanical planarization (CMP) process step may cause the semiconductor devices to be susceptible to short circuit failures. 
       SUMMARY 
       [0002]    One or more embodiments relate to semiconductor devices including middle-of-line (MOL) capacitance reduction with integration for self-aligned contact. In one embodiment, a semiconductor structure includes one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor includes a recessed MOL oxide layer and an air-gap oxide layer including one or more introduced air-gaps. The air-gap oxide layer is disposed over the one or more semiconductor devices and the MOL oxide layer. The semiconductor structure includes a nitride layer over the one or more semiconductor devices. Trenches are formed through the nitride layer down to the source/drain junctions, and a silicide fills the trenches. 
         [0003]    These and other features, aspects and advantages of the present invention will become understood with reference to the following description, appended claims and accompanying figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a cross-sectional view of an exemplary (nitride) structure formed on a substrate and shown after a conventional middle-of-line (MOL) process and W-contact chemical mechanical planarization/polishing (CMP); 
           [0005]      FIG. 2  is a cross-sectional view of a result of the exemplary structure of  FIG. 1  after selective recess of an oxide layer, according to an embodiment; 
           [0006]      FIG. 3  is a cross-sectional view of a result of the exemplary structure of  FIG. 2  after recess of the nitride to an oxide layer, according to an embodiment; 
           [0007]      FIG. 4  is a cross-sectional view of the result of the exemplary structure of  FIG. 3  after an optional selective metal cap deposition, according to an embodiment; 
           [0008]      FIG. 5  is a cross-sectional view of the result of the exemplary structure of  FIG. 4  after depositing oxide and introducing air-gap in fill, according to an embodiment; 
           [0009]      FIG. 6  is a cross-sectional view of the result of the exemplary structure of  FIG. 5  after CMP is performed on the oxide (stop on metal), according to an embodiment; 
           [0010]      FIG. 7A  is a top-down view of an exemplary semiconductor device (nitride) structure formed on a substrate and shown after a conventional MOL process and W-contact CMP; 
           [0011]      FIG. 7B  is a cross-sectional view of the semiconductor device in  FIG. 7A  along section line A-A′; 
           [0012]      FIG. 7C  is a cross-sectional view of the semiconductor device in  FIG. 7A  along section line B-B′; 
           [0013]      FIG. 8A  is a top-down view of the semiconductor device structure formed on a substrate of  FIG. 7A  and shown after depositing a mask of the contact area (CA), according to an embodiment; 
           [0014]      FIG. 8B  is a cross-sectional view of the semiconductor device in  FIG. 8A  along section line A-A′; 
           [0015]      FIG. 8C  is a cross-sectional view of the semiconductor device in  FIG. 8A  along section line B-B′; 
           [0016]      FIG. 9A  is a top-down view of the exemplary semiconductor device structure of  FIG. 8A  and shown after selective recess of an oxide layer, according to an embodiment; 
           [0017]      FIG. 9B  is a cross-sectional view of the semiconductor device in  FIG. 9A  along section line A-A′; 
           [0018]      FIG. 9C  is a cross-sectional view of the semiconductor device in  FIG. 9A  along section line B-B′; 
           [0019]      FIG. 10A  is a top-down view of the exemplary semiconductor device structure of  FIG. 9A  and shown after recess of W/TiN, according to an embodiment; 
           [0020]      FIG. 10B  is a cross-sectional view of the semiconductor device in  FIG. 10A  along section line A-A′; 
           [0021]      FIG. 10C  is a cross-sectional view of the semiconductor device in  FIG. 10A  along section line B-B′; 
           [0022]      FIG. 11A  is a top-down view of the exemplary semiconductor device structure of  FIG. 10A  and shown after etching of the nitride cap, according to an embodiment; 
           [0023]      FIG. 11B  is a cross-sectional view of the semiconductor device in  FIG. 11A  along section line A-A′; 
           [0024]      FIG. 11C  is a cross-sectional view of the semiconductor device in  FIG. 11A  along section line B-B′; 
           [0025]      FIG. 12A  is a top-down view of the exemplary semiconductor device structure of  FIG. 11A  and shown after an optional metal cap deposition, according to an embodiment; 
           [0026]      FIG. 12B  is a cross-sectional view of the semiconductor device in  FIG. 12A  along section line A-A′; 
           [0027]      FIG. 12C  is a cross-sectional view of the semiconductor device in  FIG. 12A  along section line B-B′; 
           [0028]      FIG. 13A  is a top-down view of the exemplary semiconductor device structure of  FIG. 12A  and shown after removing the CA mask and oxide fill forming air-gaps, according to an embodiment; 
           [0029]      FIG. 13B  is a cross-sectional view of the semiconductor device in  FIG. 13A  along section line A-A′; 
           [0030]      FIG. 13C  is a cross-sectional view of the semiconductor device in  FIG. 13A  along section line B-B′; 
           [0031]      FIG. 14A  is a top-down view of the exemplary semiconductor device structure of  FIG. 13A  and shown after oxide CMP stop on metals, according to an embodiment; 
           [0032]      FIG. 14B  is a cross-sectional view of the semiconductor device in  FIG. 14A  along section line A-A′; 
           [0033]      FIG. 14C  is a cross-sectional view of the semiconductor device in  FIG. 14A  along section line B-B′; and 
           [0034]      FIG. 15  illustrates a block diagram for a process for forming a semiconductor structure, according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0035]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 
         [0036]    As used herein, a “lengthwise” element is an element that extends along a corresponding lengthwise direction, and a “widthwise” element is an element that extends along a corresponding widthwise direction. 
         [0037]    One or more embodiments provide for an integration of semiconductor layers to minimize middle-of-line (MOL) capacitance by introducing air gaps within semiconductor structures. In one or more embodiments, the air gaps are introduced into voids formed in the semiconductor structures. In one embodiment, the formation of the voids are controlled due to the shape of the semiconductor structures. In one or more embodiments, the introduction of air-gaps into the semiconductor structures reduces the capacitance of a MOL oxide layer due to remaining MOL oxide layer reduction, introduced air-gaps and an air-gap oxide layer. 
         [0038]      FIG. 1  is a cross-sectional view of an exemplary (nitride) structure  100  formed on a substrate and shown after a conventional MOL process and W-contact chemical mechanical planarization (CMP). As shown, the nitride structure  100  on a substrate  110  includes an MOL oxide layer  130  and a nitride cap layer  153  that are formed over a metal gate (MG)  150  and interlayer dielectric (ILD)  151  surrounding the metal gate. Spacer material  154  and  155  (e.g., low-k spacer material) is on opposite sides of the MG  150  stack. In one embodiment, a low-k spacer is a spacer having a dielectric constant less than the dielectric constant of silicon nitride at room temperature, e.g., 7.0 or less, and preferably about, e.g., 5.0. Some examples of low-k materials may include, but are not limited to, hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), polyphenylene oligomer, methyl doped silica or SiOx(CH3)y, SiCxOyHy or SiOCH, organosilicate glass (SiCOH) and porous SiCOH, silicon oxide, boron nitride, silicon oxynitride, etc. Work function metal (WFM)  152  (e.g., TiN, TaN, TaAlN, etc.) is on the lower portion of the MG  150  stack. A silicide surrounded by nitride  145  is formed in the nitride structure  100  in trenches  140  (the silicide in the trenches  140  may be referred to as trench silicide (TS) hereinafter. The self-aligned contact areas (CA)  120  are formed in the MOL oxide layer  130  and surrounded by a nitride layer  125  (e.g., TiN, SiN, etc.). 
         [0039]    In one embodiment, the substrate  110  may be a semiconductor-on-insulator (SOI) substrate (e.g., fully-depleted SOI, partially depleted SOI, etc.). In other embodiments, the substrate  100  may be a bulk Fin field effect transistor (FinFET), SOI FinFET, strained SOI (SSOI), SiGe on-insulator (SGOI), Nanowire, etc. In one embodiment, an insulator layer  160  may include exemplary dielectric materials that, for example include, silicon oxide, silicon nitride, silicon oxynitride, and sapphire. 
         [0040]    In one embodiment, the gate dielectric of the MG  150  stack includes a high-k material having a dielectric constant greater than silicon oxide. Exemplary high-k materials include, but are not limited to, HfD 2 , Zr0 2 , La 2 0 3 , Al 2 0 3 , Ti0 2 , SrTi0 3 , LaAl0 3 , Y 2 0 3 , HfOxNy, ZrOY′ La 2 0xNy, Al 2 0xNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y 2 0xNy, SiON, SiNx, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. 
         [0041]    In one embodiment, the gate cavity formed with the multiple depositions, etc. to form the MG  150  stack may be filled with at least one conductive material, such as at least one metallic material and/or at least one doped semiconductor material. Examples of the conductive metal include, but are not limited to, Al, W, Cu, Pt, Ag, Au, Ru, Ir, Rh and Re, alloys of a conductive metal, e.g., Al—Cu, metal nitrides or carbides such as AN, TiN, TaN, TiC and TaC, silicides of a conductive metal, e.g., W silicide, and Pt silicide, and combinations thereof. The gate electrode of the MG  150  stack can be formed by depositing the conductive material utilizing a conventional deposition process such as, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), sputtering, plating, evaporation, ion beam deposition, electron beam deposition, laser assisted deposition, and chemical solution deposition. 
         [0042]      FIG. 2  is a cross-sectional view of the result  200  of exemplary structure  100  after selective recess of the oxide layer  130 , according to an embodiment. In one embodiment, the selective recess of the oxide layer  130  is selective to the CA  120  metal (e.g., W), nitride cap layer  153 , (e.g., SiN) and nitride layer  125 . In one embodiment, the recess may use dry etch, with or without block masking. 
         [0043]      FIG. 3  is a cross-sectional view of the result  300  of exemplary structure  200  ( FIG. 2 ) after selective recess of the nitride cap layer  153  to the remaining MOL oxide layer  130 , according to an embodiment. Etching may be used for selective recessing the nitride cap layer  153 . 
         [0044]      FIG. 4  is a cross-sectional view of the result  400  of exemplary structure  300  ( FIG. 3 ) after an optional selective metal cap  410  deposition, according to an embodiment. In one embodiment, the metal cap may be cobalt (Co), ruthenium (Ru), etc. In one embodiment, the selective metal cap formation may be performed by CVD, an electroless process, etc. In one embodiment, the optional metal caps  410  may be formed on top of the MG  150  stacks, and on top of the CAs  120  as shown. 
         [0045]      FIG. 5  is a cross-sectional view of the result  500  of the exemplary structure  400  ( FIG. 4 ) after depositing an air-gap oxide layer  510  and introducing air-gaps  520  in fill, according to an embodiment. In one embodiment, air-gaps are formed due to poor gap fill property of the oxide film deposited, artificially creating the void. In one embodiment, structures are regular, therefore the voids are controlled. In one embodiment, the introduction of the air-gaps reduces the capacitance of the MOL oxide layer  130  due to remaining MOL oxide layer  130  reduction, the air-gaps  520  and air-gap oxide layer  510 . 
         [0046]      FIG. 6  is a cross-sectional view of the resulting semiconductor device  600  of the exemplary structure  500  ( FIG. 5 ) after CMP is performed on the air-gap oxide layer  510  (stop on metal), according to an embodiment. It should be noted that if metal cap  410  deposition is not employed, the CMP or other known techniques may be used to reduce the air-gap oxide layer  510  to the CAs  120  and nitride layer  125 . In one embodiment, the resulting semiconductor device  600  is a semiconductor structure that may be employed in multiple different integrated circuit (IC) chips and products as described below. 
         [0047]    In one embodiment, the resulting semiconductor device  600  may have a height above the substrate of about 8 nm to 260 nm. In one embodiment, the height of the MG  150  stack is about 50 nm to 150 nm, with a width of less than 30 nm. In one embodiment, the CAs  120  have a height of about 30 nm to 100 nm, and a width of less than 40 nm. In one embodiment, the metal caps  410  have a height of about 1 nm to 10 nm and a width less than 30 nm. In one embodiment, the spacer material  154  and  155  each have a height of about 50 nm to 150 nm and a width of less than 15 nm. In one embodiment, the air-gap oxide layer  510  has a height of about 30 nm to 100 nm. In one embodiment, the height of the air-gap oxide layer  510  from the metal cap  410  to about the remaining MOL oxide layer  130  or to the top of the insulator layer  160  is about 15 nm to 50 nm; and has a height of about 15-50 nm from above the top of the insulator layer  160  to the top of the air-gap oxide layer  510 . In one embodiment, the height of the WFM  152  has a height of about 20 nm to 50 nm and a width of less than 30 nm. In one embodiment, the height of the MG  150  is about 30 nm to 199 nm and the width is less than 30 nm. 
         [0048]      FIG. 7A  is a top-down view of an exemplary semiconductor device structure  700  formed on a substrate  110  and shown after a conventional MOL process and W-contact CMP. It should be noted that the exemplary semiconductor device  700  may be similar or equivalent to the exemplary (nitride) structure  100  ( FIG. 1 ).  FIG. 7B  is a cross-sectional view of the semiconductor device  700  in  FIG. 7A  along section line A-A′.  FIG. 7C  is a cross-sectional view of the semiconductor device in  FIG. 7A  along section line B-B′. 
         [0049]      FIG. 8A  is a top-down view of the resulting exemplary semiconductor device  800  formed on a substrate  110  of  FIG. 7A  and shown after depositing a mask  820  on the CAs  120 , according to an embodiment. In one embodiment, the mask may be applied using lithography or any other known technique.  FIG. 8B  is a cross-sectional view of the semiconductor device  800  in  FIG. 8A  along section line A-A′.  FIG. 8C  is a cross-sectional view of the semiconductor device  800  in  FIG. 8A  along section line B-B′. 
         [0050]      FIG. 9A  is a top-down view of the resulting exemplary semiconductor device  900  formed on the substrate  110  of  FIG. 8A  and shown after selective recess of the MOL oxide layer  130 , according to an embodiment.  FIG. 9B  is a cross-sectional view of the semiconductor device  900  in  FIG. 9A  along section line A-A′.  FIG. 9C  is a cross-sectional view of the semiconductor device  900  in  FIG. 9A  along section line B-B′. As shown, the remaining MOL oxide layer  930  is reduced and the selective recess of the MOL oxide layer  130  is selective to the nitride (e.g., SiN) cap layer  153 . 
         [0051]      FIG. 10A  is a top-down view of the resulting exemplary semiconductor device  1000  formed on the substrate  110  of  FIG. 9A  and shown after recess of W/TiN, according to an embodiment. In one embodiment, etching is used to recess the W/TiN of the semiconductor device  1000 .  FIG. 10B  is a cross-sectional view of the semiconductor device  1000  in  FIG. 10A  along section line A-A′.  FIG. 10C  is a cross-sectional view of the semiconductor device in  FIG. 10A  along section line B-B′. 
         [0052]      FIG. 11A  is a top-down view of the resulting exemplary semiconductor device  1100  formed on the substrate  110  of  FIG. 10A  and shown after etching of the nitride cap  125 , according to an embodiment. In one embodiment, the nitride cap  125  (e.g., Sin Cap) is etched using reactive ion etching (RIE).  FIG. 11B  is a cross-sectional view of the semiconductor device  1100  in  FIG. 11A  along section line A-A′.  FIG. 11C  is a cross-sectional view of the semiconductor  1100  device in  FIG. 11A  along section line B-B′. 
         [0053]      FIG. 12A  is a top-down view of resulting exemplary semiconductor device  1200  formed on the substrate  110  of  FIG. 11A  and shown after an optional metal cap  1210  deposition, according to an embodiment. In one embodiment, Co or Ru may be used for the metal caps  1210 . In one embodiment, known deposition techniques may be used for the metal deposition.  FIG. 12B  is a cross-sectional view of the semiconductor device in  FIG. 12A  along section line A-A′.  FIG. 12C  is a cross-sectional view of the semiconductor device in  FIG. 12A  along section line B-B′. 
         [0054]      FIG. 13A  is a top-down view of the resulting exemplary semiconductor device  1300  formed on the substrate  110  of  FIG. 12A  and shown after removing the CA  120  mask  820  and oxide fill forming air-gaps  1320 , according to an embodiment. In one embodiment, the air-gaps  1210  are formed due to poor gap fill property of the oxide film  1310  deposited, artificially creating the void. In one embodiment, structures are regular, therefore the voids are controlled. In one embodiment, the introduction of the air-gaps  1320  reduces the capacitance of the MOL oxide layer  130  due to remaining MOL oxide layer  930  reduction, the air-gaps  1320  and air-gap oxide layer  1310 .  FIG. 13B  is a cross-sectional view of the semiconductor device in  FIG. 13A  along section line A-A′.  FIG. 13C  is a cross-sectional view of the semiconductor device in  FIG. 13A  along section line B-B′. 
         [0055]      FIG. 14A  is a top-down view of the resulting exemplary semiconductor device  1400  formed on the substrate  110  of  FIG. 13A  and shown after oxide layer  1310  CMP stop on metals  1210 , according to an embodiment.  FIG. 14B  is a cross-sectional view of the semiconductor device in  FIG. 14A  along section line A-A′.  FIG. 14C  is a cross-sectional view of the semiconductor device in  FIG. 14A  along section line B-B′. In one embodiment, the resulting semiconductor device  1400  is a semiconductor structure that may be employed in multiple different IC chips and products as described below. In one embodiment, the resulting exemplary semiconductor device  1400  has similar dimensions as described above for the resulting semiconductor device  600 . 
         [0056]      FIG. 15  illustrates a block diagram for a process  1500  for forming a semiconductor structure, according to one embodiment. In one embodiment, in block  1510  process  1500  selectively recesses an MOL oxide layer (e.g., MOL oxide layer  130 ,  FIGS. 1 and 7A -C) of the semiconductor structure (e.g., exemplary (nitride) structure  100 ,  FIG. 1 , semiconductor structure  700 ,  FIGS. 7A-C ) including a plurality of gate stacks formed on a substrate. In block  1520  a cap layer (e.g., nitride cap layer  125 ,  FIG. 1 , nitride cap layer  153 ,  FIG. 7B-C ) of the plurality of gate stacks. In block  1530  an air-gap oxide layer (e.g., air-gap oxide layer  510 ,  FIG. 5 , air-gap oxide layer  1310 ,  FIGS. 13B-C ) is deposited introducing one or more air-gaps (e.g., air-gaps  520 ,  FIG. 5 , air-gaps  1320 ,  FIGS. 13B-C ) in the deposited air-gap oxide layer. In block  1540  CMP is performed on the deposited air-gap oxide layer. 
         [0057]    In one embodiment, process  1500  may further include depositing metal caps (e.g., metal caps  410 ,  FIG. 4 , metal caps  1210 ,  FIGS. 12B-C ) to one or more CA elements (e.g., CAs  120 ,  FIG. 1 ) and W gate elements (e.g., MG  150 ,  FIG. 4  and  FIGS. 13B-C ), prior to depositing the air-gap oxide layer. In one embodiment, CMP on the deposited air-gap oxide layer stops on the metal caps. In one embodiment, process  1500  may further include masking CA elements of the semiconductor structure prior to selectively recessing the MOL oxide layer. In one embodiment, process  1500  may further include recessing W and TiN after selectively recessing the MOL oxide layer. In one embodiment, selectively recessing the cap layer of the multiple gate stacks includes etching the cap layer using RIE. 
         [0058]    In one embodiment, process  1500  may further include removing the mask from the CA elements and then performing the depositing of the air-gap oxide layer. In one embodiment, the one or more air-gaps reduces capacitance of the MOL oxide layer. 
         [0059]    The exemplary methods and techniques described herein may be used in the fabrication of IC chips. In one embodiment, the IC chips may be distributed by a fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged IC chips), as a bare die, or in a packaged form. In the latter case, the IC chip is mounted in a single IC chip package (e.g., a plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multi-IC chip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). The IC chip is then integrated with other IC chips, discrete circuit elements and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product, such as microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, toys and digital cameras, as non-limiting examples. One or more embodiments, may be applied in any of various highly integrated semiconductor devices. 
         [0060]    Unless described otherwise or in addition to that described herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited, including, but not limited to: CVD, LPCVD, PECVD, semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, PVD, ALD, chemical oxidation, MBE, plating or evaporation. Any references to “poly” or “poly silicon” should be understood to refer to polycrystalline silicon. 
         [0061]    References herein to terms such as “vertical”, “horizontal,” etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the substrate, regardless of the actual spatial orientation of the semiconductor substrate. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on,” “above,” “below,” “side” (as in “sidewall”), “higher,” “lower,” “over,” “beneath” and “under,” are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing one or more embodiments without departing from the spirit and scope of the one or more embodiments. 
         [0062]    References in the claims to an element in the singular is not intended to mean “one and only” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described exemplary embodiment that are currently known or later come to be known to those of ordinary skill in the art are intended to be encompassed by the present claims. No claim element herein is to be construed under the provisions of 35 U.S.C. section 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or “step for.” 
         [0063]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, materials, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, materials, components, and/or groups thereof. 
         [0064]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.