Abstract:
An ESD protection circuit is disclosed. The ESD protection circuit includes a stacked MOS circuit and a trigger current generating circuit. The trigger current generating circuit will generate trigger signal(s) to turn on the stacked MOS circuit under ESD stress condition. The ESD voltage can thus be discharged through the current path formed by the stacked MOS circuit. A lower trigger voltage is achieved by technologies disclosed, which will make an integrated circuit more sensitive to ESD.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an ESD (Electrostatic Discharge) protection circuit, and more particularly to an ESD protection circuit capable of bypassing electrostatic charges under ESD stress condition by using low-voltage-tolerant components. 
   2. Description of the Prior Art 
   Because of reduction in dimension as well as significant improvement in precision, advanced electronic devices, especially those tiny elements thereinside, are sensitive to ESD and need to be properly protected therefrom. Thus, most high precision electronic devices provide additional ESD protection circuits to guard internal components against accidental ESD damage which is caused from unexpected contact with some object around or a human body. 
     FIG. 1  shows the I-V (current-voltage) characteristic curve of a conventional stacked NMOS (Negative Metal Oxide Semiconductor) ESD protection circuit, where the X-axis represents the drain-to-source voltage and the Y-axis represents the drain current. As shown in  FIG. 1 , when the voltage across drain and source gradually accumulates, the drain current increases correspondingly. As soon as the drain-to-source voltage is going to exceed a trigger voltage, it starts to experience a snapback session due to the “punch through” effect. The snapback session goes on until the drain-to-source voltage reaches down to a holding voltage. After that, the drain-to-source voltage increases smoothly and so does the drain current. The difference between the trigger voltage level and the holding voltage level is known as the snap-back region. 
   As can be noted from above description, when the ESD voltage is greater than the trigger voltage, the stacked NMOS functioning as an ESD protection circuit will be activated, a current will thus flow through the stacked NMOS and the electrostatic charges will bypass therethrough to the ground. Internal components of electronic devices are therefore protected from being damaged by an ESD. A limitation of conventional stacked NMOS ESD protection circuit is, however, when the electrostatic voltage is under the trigger voltage, the ESD protection circuit will fail to be activated. The electrostatic charges will consequently be kept in the electronic device and become a potential damage source to the device. 
     FIG. 2  shows a conventional stacked NMOS ESD protection circuit embedded in an integrated circuit (or IC). The integrated circuit works under mixed-voltage sources, say Vdd and Vcc, internally such that interfacing of semiconductor chips and sub-systems operating in different internal voltage levels can be achieved. As shown in  FIG. 2 , an I/O pad is connected with the internal circuit and the drain of the first NMOS (NMOS 1 ). The gate and source of NMOS 1  are respectively coupled with the voltage input terminal Vdd and the source of the second NMOS (NMOS 2 ). The gate of NMOS 2  is coupled to another voltage input terminal Vcc and the source of NMOS 2  is grounded. 
   In  FIG. 2 , NMOS 1  and NMOS 2  are stacked in a cascade configuration such that a common diffusion region formed in the node between them. The structure of the stacked NMOS is equivalent to a parasite lateral bipolar junction transistor (hereinafter “LBJT”). When the electrostatic voltage is higher than a trigger voltage, the parasite LBJT will be activated and electrostatic charges inside will be discharged therethrough. As mentioned above, however, when the electrostatic voltage is not high enough, the LBJT will fail to be activated. As the bypassing path is still disabled, the electrostatic charges will keep residing in the integrated circuit and finally damage the MOS (Metal Oxide Semiconductor) gate oxide in the I/O buffer inside the I/O pad. Since the breakdown voltage of an MOS gate oxide will become lower in a mixed-voltage I/O circuit, the gate oxide is readily damaged by the accumulated electrostatic charges. 
   In view of above limitation in a conventional ESD protection circuit, there is a need to provide an ESD protection circuit which is more sensitive to electrostatic charges such that a lower trigger voltage can be achieved to have a better ESD protection for an integrated circuit. 
   SUMMARY OF THE INVENTION 
   In view of the foregoing, it is an object of the present invention to provide an ESD protection circuit which is more sensitive to electrostatic charges and is able to be activated by a lower electrostatic voltage. 
   Another object of the present invention is to provide an ESD protection circuit which is composed of low-voltage-tolerant electronic components and is capable of sustaining a higher ESD level. 
   According to above objects, the present invention provides an ESD protection circuit which is essentially composed of a number of ESD detection circuits, a trigger current generating circuit, and a stacked MOS circuit containing an equivalent LBJT. As soon as the electrostatic voltage exceeds some specific level, the trigger current generating circuit receives ESD detection signals generated from the ESD detection circuits and outputs a trigger signal. The trigger signal will then activate the stacked MOS circuit such that the ESD voltage can be discharged through the path formed thereby. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows the I-V characteristic curve of a conventional stacked NMOS circuit; 
       FIG. 2  shows the schematic diagram of a conventional stacked NMOS circuit; 
       FIG. 3  to  FIG. 7  are the schematic diagrams of the preferred embodiments of ESD protection circuits in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The detailed description of the present invention will be discussed in the following embodiments, which are not intended to limit the scope of the present invention, but can be adapted for other applications. 
   The present invention discloses an ESD protection circuit applicable to an integrated circuit using mixed-voltage internally. There are generally two different voltage sources in such kind of integrated circuit. The ESD protection circuit disclosed herein is to function as an ESD bypassing path between voltage sources and the ground. Under ESD stress condition, the ESD protection circuit will be activated and bypass the electrostatic charges to ground before the internal components of the integrated circuit is damaged. 
     FIG. 3  illustrates an embodiment of the ESD protection circuit in accordance with the present invention. It includes a first ESD detection circuit  10 , a second ESD detection circuit  20 , a trigger current generating circuit  30 , and a stacked MOS circuit  40  in which an equivalent LBJT is embedded. A common diffusion region is formed in the node between the two NMOS&#39;s in the stacked MOS circuit  40 , which can thus be treated as an LBJT. The stacked MOS circuit  40  includes a first NMOS (hereinafter “N 1 ”), a second NMOS (hereinafter “N 2 ”) and a first resistor R 1 . The drain of N 1  and thus the collector of the LBJT are coupled with a first voltage input terminal Vdd. The gate of N 1  is coupled with a terminal of the first resistor R 1 . The source of N 1  is coupled with the drain of N 2 . The source of N 2  and thus the emitter of the LBJT are grounded. The gate of N 2  and the base terminals of both N 1  and N 2  are also grounded. The other terminal of the first resistor R 1  is coupled to a second voltage input terminal Vcc. 
   The first ESD detection circuit  10  includes a second resistor R 2 , a first capacitor C 1 , and a second capacitor C 2 . The first terminal of the second resistor R 2  is coupled to the first voltage input terminal Vdd. The second terminal of the second resistor R 2  outputs a first ESD detection signal. C 1  and C 2  are connected serially between the second terminal of R 2  and the ground Vss as shown in  FIG. 3 . The second ESD detection circuit  20  includes a third resistor R 3  and a third capacitor C 3 . The first terminal of the third resistor R 3  is coupled to the second voltage input terminal Vcc. The other terminal of the third resistor R 3  outputs a second ESD detection signal. The third capacitor C 3  is connected between the other terminal of the third resistor R 3  and the ground Vss. 
   The trigger current generating circuit  30  includes a first PMOS (hereinafter “P 1 ”), a second PMOS (hereinafter “P 2 ”), and a third NMOS (hereinafter “N 3 ”). The drain of P 1  is coupled to the first voltage input terminal Vdd. The gate of P 1  receives the first ESD detection signal. The drain of P 2  and the source of P 1  are coupled together. The base terminals of P 1  and P 2  are coupled to the first voltage input terminal Vdd. The gates of N 3  and P 2  are coupled together to receive the second ESD detection signal. The drain of N 3  and the source of P 2  are coupled together and output a trigger signal. The base and source of N 3  are grounded to Vss. 
   As an ESD voltage is somehow coupled to the first voltage input terminal Vdd, nodes A and B respectively output the first ESD detection signal and the second ESD detection signal such that gates of P 1  and P 2  respectively receive the two ESD detection signals which are basically low voltage level. P 1  and P 2  are thus activated and a trigger current flows through the path formed by the series connection of P 1  and P 2 , which in turn causes a trigger signal to output to the base (i.e., node C) of the LBJT. The LBJT is activated and thus N 1  and N 2  are activated. Consequently, N 1  and N 2  form an ESD discharge path between the first voltage input terminal Vdd and the ground terminal Vss such that ESD voltage can be discharged therethrough and internal circuits are protected from damage during an ESD stress event. 
   Similar to  FIG. 3 ,  FIG. 4  shows another embodiment in accordance with the present invention. The only change in  FIG. 4  is the trigger current generating circuit  50  whose function is detailed in following paragraph. 
   The trigger current generating circuit  50  includes a third PMOS (hereinafter “P 3 ”), a fourth PMOS (hereinafter “P 4 ”), a fifth PMOS (hereinafter “P 5 ”), a fourth NMOS (hereinafter “N 4 ”), a fifth NMOS (hereinafter “N 5 ”), and a sixth NMOS (hereinafter “N 6 ”). The drain and base of P 3 , the base of P 4 , and the drain and base of P 5  are all coupled together to the first voltage input terminal Vdd. The gates of P 3  and P 5  are coupled together to receive the first ESD detection signal. The source of P 3  and the drain of P 4  are coupled together. Likewise, the source of P 5  and the drain of N 5  are also coupled together. The gates of P 4 , N 4 , and N 6  are coupled together to receive the second ESD detection signal. The source of P 4 , the drain of N 4 , and the gate of N 5  are coupled together. The source of N 5  and the drain of N 6  are coupled together and output a trigger signal. The base terminals of N 5  and N 6 , the source of N 6 , and the base and source of N 4  are all grounded to Vss. 
   As an ESD voltage is coupled to the first voltage input terminal Vdd, nodes A and B respectively output the first ESD detection signal and the second ESD detection signal such that P 3 , P 4 , and P 5  are all activated. The activation of P 3  and P 4  will cause a current flow to node D and thus N 5  will be activated. Since both P 5  and N 5  are activated now, a trigger current will flow through P 5  and N 5  to node E. The trigger current will activate the LBJT and thus N 1  and N 2  are both activated. Consequently, N 1  and N 2  form an ESD discharge path between the first voltage input terminal Vdd and the ground terminal Vss such that ESD voltage can be discharged therethrough and internal circuits are protected against unexpected damage. 
     FIG. 5  shows another embodiment of the ESD protection circuit in accordance with the present invention. It includes a first ESD detection circuit  60 , a second ESD detection circuit  70 , a gate driving circuit  90  and a stacked MOS circuit  80 . The stacked MOS circuit includes a seventh NMOS (hereinafter “N 7 ”) and an eighth NMOS (hereinafter “N 8 ”). The drain of N 7  is coupled to the first voltage input terminal Vdd. The gate of N 7  receives a first gate driving signal. The source of N 7  is coupled with the drain of N 8 . The source of N 8  is grounded to Vss. The gate of N 8  receives a second gate driving signal. The base terminals of N 7  and N 8  are grounded to Vss. 
   The first ESD detection circuit  60  includes a fourth resistor R 4 , a fourth capacitor C 4 , and a fifth capacitor C 5 . The first terminal of the fourth resistor R 4  is coupled to the first voltage input terminal Vdd; the second terminal of R 4  outputs a first ESD detection signal. C 4  and C 5  are connected serially between the second terminal of R 4  and the ground Vss as shown in  FIG. 5 . The second ESD detection circuit  70  includes a fifth resistor R 5  and a sixth capacitor C 6 . The first terminal of the fifth resistor R 5  is coupled to the second voltage input terminal Vcc. The other terminal of the fifth resistor R 5  outputs a second ESD detection signal. The sixth capacitor C 6  is connected between the other terminal of the fifth resistor R 5  and the ground Vss. 
   The gate driving circuit  90  includes a sixth PMOS hereinafter “P 6 ”), a seventh PMOS (hereinafter “P 7 ”), an eighth PMOS (hereinafter “P 8 ”), a sixth resistor R 6 , and a ninth NMOS (hereinafter “N 9 ”). The drain and base of P 6 , the drain and base of P 8 , and the base of P 7  are all coupled to the first voltage input terminal Vdd. The gates of P 6  and P 8  are coupled together to receive the first ESD detection signal. The source of P 6  is coupled with the drain of P 7 . The gates of P 7  and N 9 , and the first terminal of the sixth resistor R 6  are coupled together to receive the second ESD detection signal. The second terminal of R 6  is coupled to the source of P 8  and outputs the first gate driving signal. The source of P 7  and the drain of N 9  are coupled together to output the second gate driving signal. The base and source of N 9  are grounded to Vss. 
   As an ESD voltage is coupled to the first voltage input terminal Vdd, node F and G will respectively output the first ESD detection signal and the second ESD detection signal such that P 6 , P 8 , and P 7  are all activated. The series connection of P 6  and P 7  forms a path through which a current flows from the first voltage input terminal Vdd to node I, which functions as the second gate driving signal and activates N 8 . Moreover, P 8  is also activated and forms a path through which a current flows from the first voltage input terminal Vdd to node H, which functions as the first gate driving signal and activates N 7 . Thus, both N 7  and N 8  are activated and form an ESD discharge path between the first voltage input terminal Vdd and the ground terminal Vss such that the ESD voltage can be discharged through the path and internal circuits are thus guarded from ESD damage. 
   Similar to  FIG. 5 ,  FIG. 6  shows another embodiment in accordance with the present invention. The only change in  FIG. 6  is the gate driving circuit  100  whose function will be detailed in following paragraph. 
   The gate driving circuit  100  includes a ninth PMOS (hereinafter “P 9 ”), a tenth PMOS (hereinafter “P 10 ”), an eleventh PMOS (hereinafter “P 11 ”), a twelfth PMOS (hereinafter “P 12 ”), a seventh resistor R 7 , a tenth NMOS (hereinafter “N 10 ”), an eleventh NMOS (hereinafter “N 11 ”), and a twelfth NMOS (hereinafter “N 12 ”). The drain and base of P 9 , the base terminal of P 10 , the drain and base of P 11 , and the drain and base of P 12  are all coupled together to a first voltage input terminal Vdd. The gates of P 9 , P 11 , and P 12  are coupled together to receive the first ESD detection signal. The source of P 12  and the second terminal of the seventh resistor R 7  are coupled together to output the first gate driving signal. The first terminal of the seventh resistor R 7 , and the gates of P 10 , N 10 , and N 12  are coupled together to receive the second ESD detection signal. The source of P 10 , the drain of N 10 , and the gate of N 11  are coupled together. The source of N 11  and the drain of N 12  are coupled together to output the second gate driving signal. The source and base of N 10 , the source and base of N 12 , and the base terminal of N 11  are coupled together to the ground terminal Vss. The source of P 9  is coupled with the drain of P 10 . The source of P 11  is coupled with the drain of N 11 . 
   As an ESD voltage is coupled to the first voltage input terminal Vdd, node F and node G respectively output the first ESD detection signal and the second ESD detection signal which are both low voltage level, such that P 9 , P 10 , P 11 , and P 12  are all activated. The activation of P 12  forms a path through that a current flows from the first voltage input terminal Vdd to node J, which functions as the first gate driving signal and activates N 7 . The activation of P 9  and P 10  forms another path through that a current flows from the first voltage input terminal Vdd to node K, which in turn activates N 11 . The activation of P 11  and N 11  again forms another path through that a current flows from the first voltage input terminal to node L, which functions as the second gate driving signal and activates N 8 . Both N 7  and N 8  are now activated simultaneously and form an ESD path between Vdd and Vss, through that the ESD voltage can be discharged and IC internal components are protected. 
     FIG. 7  shows yet another embodiment in accordance with the present invention. Likewise,  FIG. 7  is similar to  FIG. 5  except that it provided a modified gate driving circuit  110  which is going to be described in following paragraph. 
   The gate driving circuit  110  includes a thirteenth PMOS (hereinafter “P 13 ”), a fourteenth PMOS (hereinafter “P 14 ”), a fifteenth PMOS (hereinafter “P 15 ”), an eighth resistor R 8 , a thirteenth NMOS (hereinafter “N 13 ”), a fourteenth NMOS hereinafter “N 14 ”), and a seventh capacitor C 7 . The drain and base of P 13 , the base terminal of P 14 , the drain and base of P 15 , and the first terminal of the eighth resistor R 8  are all coupled together to the first voltage input terminal Vdd. The gate of P 13  receives the first ESD detection signal. The gates of P 14  and N 13  are coupled together to receive the second ESD detection signal. The base and source of N 13  are coupled together to the ground terminal Vss. The source of P 14  and the drain of N 13  are coupled together to output the second gate driving signal. The source of P 13  is coupled with the drain of P 14 . The second terminal of the eighth resistor R 8 , the gates of P 15  and N 14 , and the first terminal of the seventh capacitor C 7  are coupled together. The base and source of N 14  and the second terminal of the seventh capacitor C 7  are coupled together to the second voltage input terminal Vcc. The source of P 15  and the drain of N 14  are coupled together to output the first gate driving signal. 
   As an ESD voltage is coupled to the first voltage input terminal Vdd, node F and node G respectively output the first ESD detection signal and the second ESD detection signal which are both low voltage level, such that P 13 , and P 14  are activated. Moreover, P 15  is also activated because of the low voltage level in node M. The activation of P 15  forms a path through that a current flows from the first voltage input terminal Vdd to node N, which functions as the first gate driving signal and activates N 7 . The activation of P 13  and  14  will form another path through that a current passed from the first voltage input terminal Vdd to node O, which functions as the second gate driving signal and activates N 8 . Both N 7  and N 8  are now activated simultaneously and form an ESD path between Vdd and Vss, through that the ESD voltage can be discharged and IC internal components are protected. 
   This example adopts a deep N well NMOS device for N 14  in the gate driving circuit  110  such that both the base and source of N 14  are connected to the second voltage input terminal Vcc instead of grounding the base to Vss. Such disposition will prevent the gate oxide of N 14  from potential damages due to an excessive voltage difference between the gate and the base. 
   Although only preferred embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.