Abstract:
A voltage divider circuit having divider resistors which are not precision resistors. A first oscillating signal is input into a first resistor and the complement of the first oscillating signal is input into a second resistor. The two resistors are connected together and to a filter. Other means, such as transistors, may be utilized in lieu of the resistors. The output at the filter is the D.C. level of the first oscillating signal which is one-half or other designated ratio of the input voltage. Buffers may be incorporated in the invention.

Description:
FIELD OF THE INVENTION 
     The present invention pertains to a voltage divider capable of dividing a known reference voltage in half. More particularly, it pertains to a voltage divider which is capable of precisely dividing a known reference voltage in half without the use of precision resistors. 
     BACKGROUND OF THE INVENTION 
     In the past, voltage dividers have commonly consisted of two resistors connected between a first reference voltage and a second reference voltage such as a ground. The two resistors were connected in series and the center terminal, where the two resistors were electrically connected, was used as the output. The output was the value of the resistor connected to ground times the value of the reference voltage divided by the summation of the values of the two resistors, as stated in the following formula. 
     
         Vout=Vref[R2/(R1+R2)] 
    
     This form of a voltage divider requires that the two resistors be substantially the same value, (for ##EQU1## the error being measured in their difference. Although this configuration is simple to use, the present invention is a configuration wherein the two resistors need not be of an equal value. This invention provides precise voltage division by 2 with resistors that may vary from each other by as much as fifty percent (50%) or more. 
     SUMMARY OF THE INVENTION 
     The precision voltage divider comprises a means for providing an oscillating signal and an electrical network. The means for providing the oscillating signal supplies a first oscillating signal having peak voltages as first and second reference voltage signals. Hereinafter, the first reference voltage shall be referred to as &#34;reference voltage&#34; and the second reference voltage as &#34;ground&#34; or &#34;zero volts&#34;. The means for providing the oscillating signals provides a signal which oscillates between the reference voltage and ground. The means for providing the oscillating signal further outputs a second oscillating signal. The second oscillating signal is the complement of the first oscillating signal. The oscillating signals are provided to an electrical network. The electrical network comprises a first resistive means connected between a first and third node, a second resistive means connected between a second node and the third node, and a filter means connected to the third node. The first oscillating signal is provided to the first node. The second oscillating signal is provided to the second node. Finally the filter means is connected to the second reference voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of the invention in its basic form. 
     FIG. 2a and 2b are schematic diagrams utilized to illustrate the operation of the invention in FIG. 1. 
     FIG. 3 is a more complex variation of the apparatus of FIG. 1 wherein the voltage reference need not be adapted to a CMOS voltage level. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Embodiment of FIG. 1 is voltage divider 10 with reference voltage (Vref) 105 that is to be divided, as the supply voltage to D flip-flop 120. By using Vref 105 as the supply voltage, the output of D flip-flop 120 will be Vref 105 when the logic level is a level 1. When the logic level of D flip-flop 120 is 0, the output of the D flip-flop 120 will be ground 115 or zero volts. By clocking D flip-flop 120, Q 125 and Q 127 alternate between Vref 105 and ground 115. The output signal of D flip-flop 120 is a square wave symmetrical about its average D.C. level. The D.C. level is one-half of Vref 105 with respect to ground 115. Further, the outputs of Q 125 and Q 127 are complementary or 180 degrees out of phase. 
     The means for providing the oscillating signal may be a CMOS flip-flop 120. The CMOS flip-flop 120 uses a clock pulse to trigger the flip-flop 120 continuously from a level 1 signal to a level 0 signal and, consequently, back to a level 1 signal. In this manner, the CMOS flip-flop 120 toggles the first and second resistive means 130 and 140 between the first reference voltage signal 105 and ground 115. The resistive means 130 and 140 need not be precision resistors as the toggling action along with filter means 150 averages any error toward zero. Thus, due to the characteristics of the toggling action and the use of the filter means 150, the effects of the flip-flop&#39;s 120 output transistors, on-resistances and any mismatch between the divider resistors 130 and 140 tends to average out; therefore, the major source of inaccuracy in this circuit is the asymmetry in the flip-flop&#39;s 120 time division. In the development of large scale integrated circuits (LSIC&#39;s), voltage division may be required. Through the use of the present invention, it is possible to accurately divide a reference voltage in half without the use of precision resistors. 
     The two outputs of D flip-flop 120 are connected to an electrical network with nodes 1, 2, and 3. Resistor R1 130 is connected between nodes 1 and 3 and resistor R2 140 is electrically connected between nodes 2 and 3. Further, node 1 is electrically connected to Q 125 output of D flip-flop 120. Node 2 is electrically connected which is the complementary output of Q 125. Capacitor Cl 150 is connected between node 3 and ground 115. Node 3 is the output terminal of the network. Resistors R1 130 and R2 140, being electrically connected across the outputs Q 125 and Q 127, divide the output voltages. 
     FIG. 2 is a simplified version of how the resistor network of FIG. 1 works. The resistor network of FIG. 2a and 2b has the same configuration as that of FIG. 1 but with resistors R1 230 and R2 240 in lieu of resistors R1 130 and R2 140, respectively. Therefore, in FIG. 2a, when the input voltage to node 1 is Vref 205 and the input to node 2 is ground 215 or zero volts, the voltage at node 3 is: 
     
         Vref(R2/(R1+R2)) 
    
     In FIG. 2b, the input to node 2 is Vref 205 and the input to node 1 is ground 215. In this instance, the output of node 3 is: 
     
         Vref(R1/(R1+R2)) 
    
     Since the terminals are constantly changing states between Vref 205 and ground 215, the output at node 3 becomes: 
     
         1/2Vref[(R/(R1/(R+R2))+(R2/(R1+R2))] 
    
     This simplifies to: 
     
         1/2(Vref) 
    
     As the inputs to R1 130 and R2 140 of FIG. 1 are constantly oscillating between Vref 105 and ground 115, and Cl 150 filters any ripple voltage which is caused by the mismatch in R1 130 and R2 140; the accuracy of R1 130 and R2 140 is no longer a factor in the accuracy of the voltage divider. This allows one to use nonprecision resistors for resistors R1 130 and R2 140. 
     The output of the resistor network is at node 3. As the output of the resistor network is load sensitive, it is helpful to input the signal on node 3 into buffer amplifier 160. Buffer amplifier 160 in FIG. 1 is a simple voltage follower. By adding the buffer amplifier the circuit is no longer load sensitive and thus retains its accuracy. 
     Embodiment 300 of the invention is shown in FIG. 3. Embodiment 300 incorporates MOSFET transistor circuit 370 which enables device 300 to utilize a variety of reference voltages without having to specifically adapt a reference voltage for flip-flop 320. In embodiment 300, D flip-flop 320 is powered through a separate source Vcc 307 and the outputs of Q 325 and Q 327 are input into voltage drivers 395 and 397. The outputs of drivers 395 and 397 are input into two MOSFET networks. The two MOSFET networks are similar to each other, wherein Vref 305 is connected to nodes 5 and 7 of the circuit. The source of n channel MOSFET 372 is connected to node 5. The source of n channel MOSFET 374 is connected to node 7. The drain of each n channel MOSFET, 372 and 374, is electrically connected to a separate node that is, nodes 6 and 8, respectively. Node 6 is connected to the drain of p channel MOSFET 376. Node 8 is connected to the drain of p channel MOSFET 378. The sources of p channel MOSFETS 376 and 378 are connected to ground 315. Node 6 is connected to node 1, and node 8 is connected to node 2. 
     The oscillating signal from flip-flop 32 is provided to the gates of the transistors 372, 374, 376 and 378. The gate of n channel transistor 372 and the gate of the first p channel transistor 376 are connected at node 9. The gate of n channel transistor 374 and the gate of p channel transistor 378 are Connected at node 10. Node 9 is then electrically connected to the output of driver 395. Similarly node 10 is connected to the output of driver 397. In this manner, outputs of the MOSFET network 370 are oscillated between Vref 305 and ground 315 like embodiment 10 in FIG. 1. The difference is that Vref 305 need not be the same voltage level as the voltage level of the power supply for D CMOS flip-flop 320.