Abstract:
Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.

Description:
BACKGROUND 
   1. Field of the Invention 
   This invention relates in general to the field of designing application specific integrated circuits (“ASICs”), and more specifically, to a hardware state machine for performing specific tasks that interfaces with a processor. 
   2. Background of the Invention 
   A state machine also called a “finite state machine,” is a computing device designed with operational states required to solve a specific problem. Hardware state machines can be tailored to perform complex task faster by synthesizing to an optimized circuitry. For example, chips in audio, video and imaging controllers are often designed as state machines, because they can provide faster performance at lower cost than a general-purpose processor. 
   A state machine is a model of behavior composed of states, transitions and actions. A state stores information about the past, i.e. it reflects the input changes from the system start to the present moment. A transition indicates a state change and is described by a condition that would need to be fulfilled to enable the transition. An action is a description of an activity that is to be performed at a given moment. 
   State machines are devices that are typically used in a larger ASIC. The process of designing an ASIC includes writing a specification; defining the architecture; designing the state machine in a hardware description language; synthesizing the design into a physical layout; manufacturing in a wafer fabrication facility; testing the functionality of the chip; and releasing the design to production. 
   Conventional hardware state machine/ASIC design approach has shortcomings. For example, when hardware state machines are fabricated, conventional processes do not provide flexibility to change state machine operations to either correct problems with the state machine, or to implement new algorithmic approaches without tedious re-design and re-fabrication efforts. The redesign and re-fabrication is expensive and time consuming, and hence undesirable. 
   Therefore, what is needed is a system and method to efficiently design ASICs/state machines without expensive re-design/re-fabrication steps. 
   SUMMARY OF THE INVENTION 
   In one aspect of the present invention, a method for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. 
   In another aspect of the present invention, an Application Specific Integrated Circuit (ASIC) is provided. The ASIC comprises, a state machine that has plural states and can execute plural tasks associated with the plural states; and a processor that runs in parallel with the state machine, wherein control is passed to the processor from the state machine after a breakpoint condition is encountered and the break point condition is pre-set for a state of the state machine and the processor performs a task which was meant to be performed by the state machine; and control is transferred to the state machine after the processor performs the task. 
   This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
       FIG. 1  shows a conventional process flow diagram for designing/fabricating ASICs and how the shortcomings are minimized, according to one aspect of the present invention; 
       FIG. 2  is a top-level system diagram of an ASIC with a state machine working in parallel with a processor, according to one aspect of the present invention; and 
       FIG. 3  is a process flow diagram showing interaction between a hardware state machine and a processor, according to yet another aspect of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   To facilitate an understanding of the preferred embodiment, the general process for designing an ASIC will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general description. 
     FIG. 1  illustrates the problem associated with designing a state machine according to a conventional process flow and how it is minimized, according to one aspect of the present invention. 
   The process starts in step S 100 , when the specification for the ASIC is defined. The design architecture is built in step S 101  and the register transfer logic (“RTL”) design is completed in step S 102 . Thereafter, The physical design is completed in step S 103  and the masks for actual fabrication is performed in step S 104 . 
   Wafer fabrication occurs in step S 105  and the chip assembly is tested in step S 106 . A functional laboratory test is performed in step S 107 . If the functional test is successful, then the chip is released for production in step S 110 . 
   In the conventional processes, if the functional test fails and any changes have to be made in the ASIC or state machines, the design process for the change is repeated from step S 102 . This iterative process continues until the chip is acceptable. This is expensive and tedious. 
   The present invention solves this problem by using a processor inside the ASIC to control the state machine, thereby, reaching the final goal of production quickly and inexpensively. In step S 109 , after the functional laboratory test, control is passed to a processor and the processor can be programmed to perform a function (typically the function that failed in the functional test) efficiently. Once the processor solves the functional problems, the chip is sent for production in step S 110 . Details regarding steps S 109  are provided below with respect to  FIGS. 2 and 3 . 
     FIG. 2  shows a system diagram of an ASIC  210  that includes a general-purpose state machine  200  operationally coupled to a processor  203  (via bus (or connection)  204 ). ASIC  210  also include a control register  207 , status register  208  and other components like random access memory  205  and logic  206 . 
   State machine  200  is a model of behavior composed of states, transitions and actions. A state  201  stores information about the past, i.e. it reflects the input changes from the system start to a present moment. A transition  202  indicates a state change and is described by a condition that would need to be fulfilled to enable the transition. An action is a description of an activity that is to be performed at a given moment. 
   Processor  203  is an embedded processor used for controlling the state machine  200 . Processor  203  can be custom designed for lower power and lower area or can be bought from companies like ARM®, Tensilica® and others. One skilled in the art would appreciate that processor  203  executes instructions from an image loaded into random access memory (RAM) (or any other type of memory)  205 . 
   Control register  207  is programmed with break point information for each state (for example, for State  1 , State  2  and State  3 ). When a breakpoint condition is encountered (or occurs) at any given time, control from the state machine  200  is passed to processor  203 . Status register  208  stores the status of each task for each state. Processor  203  then performs the task and after it completes the task it updates status register  208  and control is then passed back to state machine  200 . 
   Hence, when an ASIC  210  is being tested ( 107 ) and a problem is discovered with a particular task for a particular state of the state machine, then a break point condition can be set in control register  207 . When that “problem” state is reached, control is passed to processor  203 , which then performs the task. Hence, programming the control register instead alleviates the need for expensive re-design and re-fabrication of ASIC  210 . 
   It is noteworthy that although one state machine is shown in  FIG. 2 , plural state machines can be controlled by processor  203 , according to one aspect of the present invention. 
     FIG. 3  shows a flow chart where processor  203  controls the state machine  200  using the control and status registers ( 207  and  208 ), according to one aspect of the present invention. The process flow starts at step S 300  when the control register  207  is programmed with the breakpoint information for individual states of the state machine  200 . For example, state  1 , state  2  and state  3  can each have break point conditions and these are stored in control register  207 . The breakpoint information is accessible by the state machine  200  and processor  203 . 
   In step  302 , state machine  200  is in an idle state and in step  301 , processor  203  is in an idle state. Both steps S 301  and S 302  can occur simultaneously. 
   In step S 303 , the state machine  200  transitions from state  1  (idle state) to a current state. 
   In step  304 , a determination is made as to whether a breakpoint is set by reading a control register  207  bit for this state (i.e. the step S 303  state). State machine  200  checks control register  207  to see if a bit has been set for the current state. If the control register  207  bit is set, then in step  305 , control is transferred to processor  203  via the status register  208 . 
   In step S 306 , processor  203  performs the task that the state machine was intended to perform. After the task is completed, in step S 307 , processor  203  sets a status bit in status register  208 . Thereafter, in step S 308 , control is passed back to the state machine  200 . At this point, if there are no more states in the state machine, the process ends in step S 310 . 
   If a break point condition is not reached or set, then in step S 309 , the task is performed by state machine  200  in the current state and the state machine moves to the next state in step S 309 . This continues until the process ends in step S 310 . 
   As illustrated above, when an ASIC has problems, processor  203  performs certain functions to overcome the problems associated with certain state machine performed tasks. Hence, changes can be made to algorithms and any other chip functionality easily without expensive re-design/fabrication costs. 
   In one aspect, the present invention provides a method and apparatus for designing a hardware state machine to perform hardware tasks by using a processor to control the state machine, thereby providing flexibility to the state machine. 
   In another aspect, the present invention provides a mechanism to perform algorithms and changes after the state machine has been fabricated. 
   Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.