Abstract:
Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.

Description:
BACKGROUND 
       [0001]    The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to solder bump connections and methods for fabricating solder bump connections during back-end-of-line (BEOL) processing of semiconductor chips. 
         [0002]    A chip or die includes integrated circuits formed by front-end-of-line (FEOL) processing and metallization levels of an interconnect structure formed by back-end-of line (BEOL) processing. Chips are then packaged and mounted on a circuit board. Solder bumps are commonly utilized to provide mechanical and electrical connections between the last or top metallization level and the circuit board. A common type of solder bump is the controlled collapse chip connection (C4) solder bump. Controlled Collapse Chip Connection (C4) processes are well known in forming solder bumps in semiconductor fabrication. During assembly of the chip and circuit board, C4 solder bumps establish physical attachment and electrical contact between an array of C4 pads on the chip and a complementary array of C4 pads on the circuit board. 
         [0003]    Conventional solder bump connections rely on a group of metallic layers know as the Ball Limiting Metallurgy (BLM) to promote the attachment of the C4 solder bump to the chip. Among the functions of the BLM are to promote adhesion between the underlying dielectric passivation layer and the metal pad, to promote solder wetting, and to act as a solder diffusion barrier. 
         [0004]    Improved solder bump connections and fabrication methods are needed that improve on conventional solder bump connections and methods. 
       BRIEF SUMMARY 
       [0005]    In an embodiment of the invention, a method is provided for fabricating a solder bump connection. The method includes forming a layer stack containing a first conductive layer and a second conductive layer on the first layer, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. 
         [0006]    In an embodiment of the invention, a solder bump connection includes a first conductive layer, a second conductive layer on the first conductive layer, and a dielectric passivation layer on a top surface of the second conductive layer. The first and second conductive layers are respectively comprised of first and second conductors. A via opening extends through the dielectric passivation layer to the top surface of the second conductive layer. A conductive plug is disposed in the via opening. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]    The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. 
           [0008]      FIGS. 1-5  are cross-sectional views of a portion of a substrate at an initial fabrication stage of a processing method for fabricating a device structure in accordance with an embodiment of the invention. 
           [0009]      FIG. 6  is a cross-sectional view similar to  FIG. 5  in accordance with an alternative embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    With reference to  FIG. 1  and in accordance with an embodiment of the invention, a plurality of dielectric layers  10 ,  12 ,  14  and a metal line  16  embedded as metallization in one or more of the dielectric layers  10 ,  12 ,  14  represents features in a topmost level of a back-end-of-line (BEOL) interconnect structure. Typical constructions for the BEOL interconnect structure consist of about two (2) to about eight (8) metallization levels. The metallization levels of the BEOL interconnect structure are formed by known lithography and etching techniques characteristic of damascene processes conventionally associated with BEOL processing. 
         [0011]    Each of the dielectric layers  10 ,  12 ,  14  may comprise any suitable organic or inorganic dielectric material recognized by a person having ordinary skill in the art and at least dielectric layers  12  and  14  should be capable of withstanding high sheer stress. Candidate inorganic dielectric materials may include, but are not limited to, silicon dioxide, fluorine-doped silicon glass (FSG), and combinations of these dielectric materials. Alternatively, the dielectric material of one or more of the dielectric layers  10 ,  12 ,  14  may be characterized by a relative permittivity or dielectric constant smaller than the dielectric constant of silicon dioxide, which is about 3.9. Candidate low-k dielectric materials include, but are not limited to, porous and nonporous spun-on organic low-k dielectrics, such as spin-on aromatic thermoset polymer resins like polyarylenes, porous and nonporous inorganic low-k dielectrics like organosilicate glasses, hydrogen-enriched silicon oxycarbide (SiCOH), and carbon-doped oxides, and combinations of these and other organic and inorganic dielectrics. The dielectric layers  10 ,  12 ,  14  may be deposited by any number of well known conventional techniques such as sputtering, spin-on application, chemical vapor deposition (CVD) process or a PECVD process. 
         [0012]    The metal line  16  may be comprised of copper, aluminum, or an alloy of these materials, and may be formed by a damascene process in dielectric layers  12 ,  14 . The metal line  16  may be configured to limit current crowding with a set of metal-filled TV (terminal via) slots. 
         [0013]    The BEOL interconnect structure is carried on a die or chip (not shown) that has been processed by front-end-of-line (FEOL) processes to fabricate one or more integrated circuits that contain device structures. The chip may be formed from any suitable wafer of semiconductor material that a person having ordinary skill in the art would recognize as suitable for integrated circuit fabrication. 
         [0014]    A layer stack consisting of an adhesion layer  20  and a seed layer  22  is formed on a top surface  18  of dielectric layer  14 . A bottom surface  24  of seed layer  22  directly contacts a top surface  28  of adhesion layer  20  so that layers  20 ,  22  are in physical and electrical contact. A bottom surface  26  of adhesion layer  20  contacts, preferably directly, the top surface  18  of dielectric layer  14  and is in physical and electrical contact with the metal line  16 . In one embodiment, the thickness of adhesion layer  20  ranges between 0.1 μm and 0.3 μm in thickness, preferably about 0.2 μm, and the thickness of seed layer  22  ranges from 0.25 μm to 1.0 μm, preferably about 0.5 μm. 
         [0015]    The layers  20 ,  22  are components of Ball Limiting Metallurgy (BLM) or Under Bump Metallurgy (UBM) used in the construction of the solder bump connection  50  ( FIG. 5 ). The adhesion layer  20  may be comprised of a material that is thermally stable during BEOL processes and that adheres well with the subsequently-formed plug  40  ( FIG. 2 ) for strengthening the bond with the dielectric layer  14  and metal line  16 . The material of the adhesion layer  20  may also be capable of blocking the drift or diffusion of atoms from the material of plug  40  into the dielectric layer  14 . In one embodiment, the adhesion layer  20  may be comprised of an alloy of titanium and tungsten (TiW). In alternate embodiments, the adhesion layer  20  may include other materials, such as a conductive metal nitride selected from titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), a tungsten nitride (WN x ), or multilayer combination of these materials (e.g., a bilayer of TaN/Ta) as recognized by a person having ordinary skill in the art. In one embodiment, seed layer  22  may be comprised of copper, such as a thin layer of copper (Cu) or co-deposited chromium-copper (Cr—Cu). 
         [0016]    Layers  20 ,  22  of the layer stack may be serially deposited utilizing physical vapor deposition (PVD) techniques or other deposition techniques understood by a person having ordinary skill in the art. Prior to deposition of the adhesion layer  20 , the top surface  18  of dielectric layer  14  may be prepared by a degas process, precleaned with a plasma etch for, etc. 
         [0017]    A dielectric passivation layer  30  is formed on a top surface  29  of seed layer  22 . The dielectric passivation layer  30  may be comprised of an organic material, such as a polymer, that is optionally photosensitive. In one embodiment, the dielectric passivation layer  30  may be comprised of photosensitive polyimide (PSPI). The dielectric passivation layer  30  may be prepared by dissolving the polymer in a solvent to form a precursor, spreading the precursor with a spin coating process as a coating across seed layer  22 , and then drying the coating to remove solvents from the precursor coating and partially imidize the polymer. 
         [0018]    A final via (FV) opening  34  is formed in the dielectric passivation layer  30 . The FV opening  34  extends through the entire layer thickness of the dielectric passivation layer  30  to expose a portion of the top surface  29  of seed layer  22 . The location of the FV opening  34  defines the intended location on dielectric layer  14  for forming the solder bump connection  50 . If the dielectric passivation layer  32  is a non-photosensitive material, a photoresist (not shown) may be spun onto the dielectric passivation layer  32 , exposed using radiation projected through a photomask, and then developed to provide a pattern of islands of photoresist distributed across the top surface  29  of the seed layer  22  at intended locations for the solder bump connections. The island pattern is transferred from the photoresist into the dielectric passivation layer  30  with a wet chemical etch process. If the dielectric passivation layer  32  is a photosensitive material, the dielectric passivation layer  32  may be lithographically patterned by radiation exposure and development. The precursor coating is subsequently cured to imidize and crosslink the polymer. 
         [0019]    An annular island region  32  of the dielectric passivation layer  30  remains on the top surface  29  of seed layer  22 . The island region  32  includes an inner sidewall  35  that surrounds the FV opening  34 , an outer sidewall  36 , a bottom surface  33  at the base of the island region  32 , and a top surface  31  opposite to the bottom surface  33 . The island region  32  has a frustoconical shape in which the sidewalls  35 ,  36  are tapered from the bottom surface  33  toward the top surface  31 . Outside of the island region  32 , the top surface  29  of seed layer  22  is also revealed when the dielectric passivation layer  30  is patterned. In one embodiment, the thickness of the dielectric passivation layer  30  may be in a range of 10 μm to 15 μm. 
         [0020]    In the process flow, the layer stack of adhesion layer  20  and seed layer  22  are formed before the island region  32  in dielectric passivation layer  30 . As a result, the inner sidewall  35  of the island region  32  is not covered by the adhesion layer  20  and seed layer  22  and, hence, is free of the layer stack. The adhesion layer  20  and seed layer  22  are present between a bottom surface of the island region  32  and the top surface  18  of the dielectric layer  14 . Preferably, the bottom surface  33  of the dielectric passivation layer  30  is directly formed on the top surface  29  of seed layer  22 . At the bottom surface  33 , the width, w, of the island region  32  measured between the corners of the sidewalls  35 ,  36  may range from 5 μm to 100 μm. 
         [0021]    With reference to  FIG. 2  in which like reference numerals refer to like features in  FIG. 1  and at a subsequent fabrication stage, a conductive layer  38  comprised of a conductor is formed on top surface  29  of seed layer  22  in surface areas across which the dielectric passivation layer  30  is absent. A representative conductor for conductive layer  38  is comprised of copper (Cu), although other suitable low-resistivity materials like metals and metal alloys may be selected in alternative embodiments. The conductive layer  38  may be deposited by a conventional deposition process, such as an electrochemical plating process like electroplating. In an electrochemical plating process, the seed layer  22  operates as a catalyst to nucleate the formation of the conductor constituting layer  38 . The material in seed layer  22  may be subsumed during the deposition process, such that the seed layer  22  may become continuous with or blend into conductive layer  38 . A segment of the seed layer  22  remains disposed beneath the island region  32  of the dielectric passivation layer  30 . The dielectric passivation layer  30  may remain uncoated by the conductor in conductive layer  38 . 
         [0022]    Following deposition, a plug  40  comprised of the conductor resides inside the FV opening  34  and constitutes a component of the BLM. The plug  40  is surrounded or circumscribed by the inner sidewall  35  of the island region  32  of dielectric passivation layer  30  and the plug  40  directly contacts the inner sidewall  35  of the FV opening  34 . The plug  40  has a diameter approximately equal to the diameter of the FV opening  34  at any point along its height. The plug  40  has a tapered sidewall  43  that is in direct physical contact with the inner sidewall  35  of the island region  32  due to the absence of layers  20 ,  22  on the inner sidewall  35 . A bottom surface  41  of the plug  40  in is direct physical and electrical contact with the top surface  29  of the seed layer  22 . Alternatively, if the seed layer  22  is subsumed into the material of the plug  40 , the bottom surface  41  of the plug  40  and the top surface  28  of the adhesion layer  20  can be considered to be in physical and electrical contact. The plug  40  residing in the FV opening  34  and the dielectric passivation layer  30  have approximately equal thicknesses. The nominal diameter of the plug  40 , which is determined by the diameter of the FV opening  34 , may be selected contingent upon the solder bump connection design dimensions and, in some embodiments, the nominal width of the plug  40  measured at the bottom surface  41  may range from 10 μm to 500 μm. 
         [0023]    The plug  40  may be formed and have a thickness equal to the thickness of the dielectric passivation layer  30  without the need for a chemical mechanical polishing (CMP) process as required by conventional processes for forming pad constructions. In particular, the placement of the layers  20 ,  22  as a layer stack on the surface of the dielectric layer  14  and the formation of the layers  20 ,  22  before the dielectric passivation layer  30  is formed facilitates the elimination of the CMP process. The layer stack of layers  20 ,  22  is disposed between the dielectric passivation layer  30  and the dielectric layer  14 . In conventional process flows, the dielectric passivation layer is formed and the FV opening is defined before the BLM layer stack is formed. As a result, the conventional BLM layer stack must be removed with a CMP process from the top surface of the dielectric passivation layer after the plug is formed in the FV opening. 
         [0024]    With reference to  FIG. 3  in which like reference numerals refer to like features in  FIG. 2  and at a subsequent fabrication stage, a plating resist mask  44  is formed on the top surface  31  of the dielectric passivation layer  30  and a top surface  37  of conductive layer  38  by applying a resist layer, exposing the resist layer to radiation through a photomask, and developing the exposed resist layer to define an unmasked window  46  exposing a top surface  42  of the plug  40 . In one embodiment, the plating resist mask  44  is a photoactive polymer resist, such as RISTON® photopolymer resist that has an optimal exposure response to ultraviolet radiation in the 350 nm to 380 nm range and that can be developed in a carbonate-based solution. 
         [0025]    With reference to  FIG. 4  in which like reference numerals refer to like features in  FIG. 3  and at a subsequent fabrication stage, a barrier layer  48  of the BLM is applied to the top surface  42  of the plug  40  that is exposed through the window  46  in the plating resist mask  44  ( FIG. 3 ). Barrier layer  48  does not form on regions of the conductive layer  38  covered by the plating resist mask  44  and defines a cap on the plug  40 . In a representative embodiment, barrier layer  48  may be comprised of a metal formed by a deposition technique, such as nickel (Ni) or a Ni alloy (e.g., NiCo) formed by an electrochemical plating process (e.g., electroplating) to a thickness with a range of 0.5 μm to 4 μm and, preferably, to a thickness of 2 μm. The layer arrangement promotes the electroplating of the barrier layer  48  in contrast to the electroless deposition required in conventional solder bump connection fabrication processes. An optional layer (not shown) of a different material, such as about 1 μm of Cu, may be applied to a top surface  49  of the barrier layer  48 . The dimensions of the barrier layer  48  and the top surface  42  of the plug  40  match a specification for solder bumping and, in particular, may match the known C4 solder bumping specification. For example, the barrier layer  48  and the top surface  42  of the plug  40  may have a diameter on the order of the dimensions of the solder bump  52  ( FIG. 5 ) and, in particular, a diameter ranging from 20 μm to 500 μm. 
         [0026]    Because of the residence of the plug  40  in the FV opening  34  and the circumscription of the plug  40  by the island region  32  of dielectric passivation layer  30 , the process forming the barrier layer  48  is self-aligned with the top surface  42  of the plug  40 . The plug  40  and the barrier layer  48  are in direct physical and electrical contact. 
         [0027]    The plating resist mask  44  is then stripped from the top surfaces  31 ,  37  in a conventional manner. For example, if the plating resist mask  44  is comprised of a photoactive polymer resist, such as RISTON®, stripping may be executed using an aqueous stripping solution or a proprietary commercial stripping solution. 
         [0028]    Field regions of the conductive layer  38  and layer  22  between adjacent solder bump connections  50  ( FIG. 5 ) are removed from the top surface of adhesion layer  20 . In one embodiment in which the conductive layer  38  and seed layer  22  are comprised of Cu, the field regions of the conductive layer  38  may be removed by exposure to an isotropic wet chemical etchant, such as a solution of hydrogen peroxide and sulfuric acid. The wet chemical etchant removes the material of conductive layer  38  and seed layer  22  at a higher etch rate than the material of barrier layer  48  so that the plug  40  residing in the FV opening  34  and layer  48  are substantially unaffected by the wet chemical etchant. 
         [0029]    With reference to  FIG. 5  in which like reference numerals refer to like features in  FIG. 4  and at a subsequent fabrication stage, field regions of the adhesion layer  20  on the top surface  18  of dielectric layer  14  at locations not masked by the overlying dielectric passivation layer  30  and plug  40  are removed. In one embodiment, these regions of the adhesion layer  20  may be removed using an isotropic wet chemical etching process. For example, if the adhesion layer  20  is comprised of TiW, a representing wet etch process may use an etchant comprised of a hydrogen peroxide (H 2 O 2 ) chemistry with end-point detection control. The patterning of the adhesion layer  20  may complete the formation of an interconnect structure in the form of the solder bump connection  50 . During BEOL processing, the solder bump connection  50  is replicated across at least a portion of the surface area of the wafer. 
         [0030]    A solder ball or bump  52  is formed on the top surface  49  of the barrier layer  48 . The solder bump  52  may be comprised of solder having a conventional lead-free (Pb-free) composition, which may include tin (Sn) as the primary elemental component. In a representative embodiment, the solder bump  52  may be separately formed and transferred to the top surface  49  of the barrier layer  48  by a Controlled Collapse Chip Connection New Process (C4NP) technology, which promotes Pb-free wafer bumping. The solder bump  52  is included among an area array of injection-molded solder bumps that are formed using bulk Pb-free solder injected into cavities in a mold plate matching the locations of solder bump connections, including solder bump connection  50 , on the wafer. The molded bumps populating the cavities are transferred to the wafer by precisely aligning the bumps with the solder bump connections and executing a reflow transfer by heating in reducing gas atmosphere to a temperature that is 10° C. to 20° C. above the solder melting temperature. The reflow of the solder bump  52  tends to combine with the material of the barrier layer  48  to form a stable intermetallic composition. The optional layer applied to top surface  49  of the barrier layer  48 , as described above, may assist in driving the transfer of the solder bump  52  to the barrier layer  48 . 
         [0031]    The solder bump  52  protrudes vertically above the level of the top surfaces  31 ,  37  of the dielectric passivation layer  30  and the plug  40 . The height of the solder bump  52  may be on the order of 50 μm. The top surface  49  of the barrier layer  48  operates as a support pad for the solder bump  52 . The barrier layer  48 , plug  40 , and adhesion layer  20  provide a conductive path between the metal line  16  and the solder bump  52 . The barrier layer  48  protects the material (e.g., Cu) of the underlying plug  40  against consumption during reflow processes from reactions with the solder bump  52 . 
         [0032]    After the solder bump  52  is reflowed on the solder bump connection  50 , a flip-chip assembly process may be performed. The chip (not shown) is inverted and aligned relative to a laminate substrate (not shown). The solder bumps, including solder bump  52 , are bonded to the matching pads on the laminate substrate using a reflow process. The temperature of the reflow process is contingent upon solder composition but is typically in a range of 200° C. to 300° C. Eventually, the solder bump  52  and solder bump connection  50  are components contributing to pathways for transferring data from the chip to an external device, such as a computing system, and for powering the integrated circuits on the chip. 
         [0033]    With reference to  FIG. 6  in which like reference numerals refer to like features in  FIG. 3  and at a subsequent fabrication stage in accordance with an alternative embodiment, the process flow proceeds as described above to the stage shown in  FIG. 3 , including forming the barrier layer  48 . With the plating resist mask  44  still intact and prior to its removal, a solder bump  60  is formed on the barrier layer  48 . The window  46  in the plating resist mask  44  defines the lateral location of the solder bump  60 . The solder bump  60  may be deposited by a conventional deposition process, such as an electrochemical plating process like electroplating or electroless plating. As described above, the plating resist mask  44  is stripped from the top surface  31  of dielectric passivation layer  30  and the top surface  37  of conductive layer  38  in a conventional manner. The process flow continues by removing regions of conductive layer  38  not covered by the regions of adhesion layer  20  and removing regions of adhesion layer  20  that are not covered by the dielectric passivation layer  30  and plug  40 , as described above. In this alternative embodiment of the process flow, the solder bump  60  assists in masking the plug  40  during the wet etch process removing the field regions of conductive layer  38 . The solder bump  60  is reflowed using a conventional reflow process to form a spherical shape, which results in the final structure of the solder bump connection  50  depicted in  FIG. 5 . 
         [0034]    The process flow in accordance with the embodiments of the invention eliminates several steps from a conventional process flow. Specifically, the conventional process flow introduces a pedestal as an independent and distinct structure underlying a conventional plug and with a separate set of steps in the conventional process of record. In contrast, the plug  40  operates as an integral, one-piece pedestal/plug structure that can be formed with at least four fewer operations than in a conventional process flow. Specifically, though the process flow of the embodiments of the invention would not eliminate a masking step, the conventional process flow is simplified by eliminating at least two PVD processes used to form barrier and seed layers, a plating process to deposit the conductive material of the pedestal on the barrier and seed layers, and a CMP process to planarized the conductive material to shape the pedestal. In addition to eliminating the independent formation of a pedestal and a plug, the process flow introduces a common metal base layers  20 ,  22  under the relatively thick plug  40 , instead of multiple layers in a stack containing a separate pedestal and plug. 
         [0035]    The plug  40  is encapsulated by the dielectric passivation layer  30  and the barrier layer  48  to form a protective envelop. Specifically, the island region  32  of dielectric passivation layer  30  is laterally disposed between the plug  40  and the surrounding environment and the top surface  42  of the plug  40  is capped by layer  48 . As a result, the plug  40  is shielded and protected against thermal undercut during reflow because the molten solder does not contact the plug  40  and, as a result, the material of the plug  40 . The potential for thermal undercut, which is eliminated by the inventive construction, is particularly acute between Sn in Pb-free solders forming the solder bump  52  and any exposed Cu. 
         [0036]    The edges at the perimeter of the adhesion layer  20  are displaced laterally from the bottom surface  41  of the plug  40  by the width of the island region  32  of dielectric passivation layer  30 . When the adhesion layer  20  is wet etched, any recession of the peripheral edges of the adhesion layer  20  beneath the island region  32  of dielectric passivation layer  30  are displaced from the location at which the adhesion layer  20  underlies the plug  40 . When the seed layer  22  is wet etched, any recession of the peripheral edges of the seed layer  22  beneath the island region  32  of dielectric passivation layer  30  are displaced from the bottom surface  41  of the plug  40 . As a result, any recession of the layers  20 ,  22  during wet chemical etching does not penetrate beneath the dielectric passivation layer  30  along the top surface  18  of dielectric layer  14  to a location proximate to the bottom surface  41  of the plug  40 . In particular, the recession of layers  20 ,  22  may only penetrate inward from the outer sidewall  36  of the island region by a distance of 2 μm or 3 μm, which is less than the width, w, of the island region  32  at its bottom surface  33  (5 μm to 100 μm). Therefore, the plug  40  is not undercut during wet chemical etching and any undercutting of the island region  32  due to etching-induced recession of layers  20 ,  22  is displaced laterally from the plug  40 . 
         [0037]    The solder bump connection  50  of the embodiments of the invention physically separates the tensile base of the solder bump  52  from the locations of potential undercutting when the layers  20 ,  22  are wet etched. The physical separation may reduce the incidence of cracking resulting from chip-package interaction (CPI) during the flip-chip assembly process. During the cool-down phase of the thermal cycle in the flip-chip assembly process described above and subsequent reliability tests, module-level stresses develop because of mismatches in coefficients of thermal expansion (CTEs) between the materials of the chip and the laminate substrate. These stresses may be translated through a pad/bump assembly into the BEOL interconnect structure, which can drive crack initiation and propagation. The susceptibility of the BEOL interconnect structure to cracking may be exacerbated by the implementation of ultra low-k dielectrics and Pb-free solders. 
         [0038]    The use of the island mask in forming the dielectric passivation layer  30  promotes the dielectric passivation layer  30  to be thickened, all other factors such as bump height being unchanged, in comparison with dielectric passivation layers found in conventional constructions. Solder bumps normally provide a gap between the chip and the laminate substrate. The enhanced thickness of the dielectric passivation layer  30  and plug  40  operates to further elevate a bottom surface of the chip and to increase the height of the gap. As a result, underfill material may be more readily drawn by capillary action from dispense locations along the edges of the chip into the gap underneath the chip, which facilitates underfilling operations. 
         [0039]    The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
         [0040]    It will be understood that when an element is described as being “connected” or “coupled” to or with another element, it can be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. In contrast, when an element is described as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. When an element is described as being “indirectly connected” or “indirectly coupled” to another element, there is at least one intervening element present. 
         [0041]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0042]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.