Abstract:
There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This patent application claims priority from Korean Patent Application No. 10-2005-0012082, filed Feb. 14, 2005, the contents of which are hereby incorporated by reference in their entirety.  
       BACKGROUND OF INVENTION  
       [0002]     1. Technical Field  
         [0003]     The present invention relates to methods of fabricating a semiconductor device, and more particularly, to methods of fabricating a semiconductor device using a sacrificial layer.  
         [0004]     2. Discussion of the Related Art  
         [0005]     Recently, research is being carried out into increasing process margins in semiconductor fabrication processes on a semiconductor device in order to electrically connect discrete elements to one another on a semiconductor substrate, using interlayer insulating layers. One approach involves the use of a chemical mechanical polishing (CMP) process on the interlayer insulating layers. The semiconductor fabrication processes include a photolithography process, an etch process, and a deposition process. The interlayer insulating layers are formed on a semiconductor substrate to cover discrete elements and isolate them. In general, interlayer insulating layers have been used with excellent planarization characteristics through the CMP process for removing step height differences between discrete elements and the semiconductor substrate, and between the discrete elements. The planarization characteristics of the interlayer insulating layers may improve process margins of a photolithography process, an etch process, and a deposition process in a given design rule. However, thicknesses of the interlayer insulating layers on the overall surface of the semiconductor substrate cannot be maintained uniform by the CMP process. In addition to intrinsic step height differences of the discrete elements, additional step height differences are formed on predetermined regions of the semiconductor substrate due to intrinsic characteristics of a polishing equipment system used during performing the CMP process. The intrinsic characteristics depend on a pad, a carrier head, and lifetime of consumptive conditioners of the polishing equipment system. As such, the CMP process may reduce process margins of photolithography, etch and deposition processes.  
         [0006]     In one approach to these familiar problems, U.S. Pat. No. 6,599,838 to Tsu Shih, et. al (the &#39;838 patent), which is incorporated herein by reference, discloses a method for forming metal filled semiconductor features to improve a subsequent metal CMP process. According to the &#39;838 patent, the method includes preparing a semiconductor processing substrate on which first and second dielectric insulating layers are sequentially disposed. The first and second dielectric insulating layers have openings. The second dielectric insulating layer is formed to have a removal rate ½ or less than that of the first dielectric insulating layer in the CMP process. Metal is formed on the second dielectric insulating layer to fill the openings. Then, the CMP process is performed on the metal until the second dielectric insulating layer is exposed.  
         [0007]     However, the method cannot planarize the upper surface of the semiconductor substrate by using the second dielectric insulating layer. This is because the upper surface of the first dielectric insulating layer before performing the CMP process may not be planarized by the method. Further, a thickness of the second dielectric insulating layer on the overall surface of the semiconductor substrate may not be maintained uniform due to intrinsic characteristics of the polishing equipment system after performing the CMP process.  
       SUMMARY OF THE INVENTION  
       [0008]     Therefore, according to some embodiments of the present invention, there are provide methods of fabricating a semiconductor device using a sacrificial layer for planarizing an upper surface of a semiconductor substrate through a chemical mechanical polishing (CMP) process.  
         [0009]     According to one aspect, the present invention provides a method of fabricating a semiconductor device using a sacrificial layer. The method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer, a planarized interlayer insulating layer, and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. At least one via contact hole is formed in the etch stop layer, the pad interlayer insulating layer, and the pad layer. The via contact hole is formed under the trench. A diffusion barrier layer and a conductive layer are sequentially formed on the sacrificial layer to fill the trench and the via contact hole. A chemical mechanical polishing (CMP) process is performed at least one time on the conductive layer, the diffusion barrier layer, and the sacrificial layer. The CMP process is performed until the planarized interlayer insulating layer is exposed.  
         [0010]     According to another aspect, present invention is directed to a method of fabricating a semiconductor device using a sacrificial layer. The method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer, a planarized interlayer insulating layer, and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. At least one via contact hole is formed in the etch stop layer, the pad interlayer insulating layer, and the pad layer. The via contact hole is formed under the trench. A diffusion barrier layer and a conductive layer are sequentially formed on the sacrificial layer to fill the trench and the via contact hole. A CMP process is performed at least one time on the conductive layer, the diffusion barrier layer, and the sacrificial layer. The CMP process is performed until the planarized interlayer insulating layer is exposed. The sacrificial layer is formed using an insulating layer having a higher etching ratio than that of the planarized interlayer insulating layer.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The foregoing and other objects, features and advantages of the invention will be apparent from the more particular description of preferred aspects of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the drawings, the thickness of layers and regions are exaggerated for clarity.  
         [0012]      FIG. 1  is a plan view showing a semiconductor substrate according to the present invention.  
         [0013]      FIGS. 2 through 11  are cross-sectional views illustrating a method of fabricating a semiconductor device taken along line I-I′ of  FIG. 1 .  
         [0014]      FIG. 12  is a graph illustrating a thickness distribution on the overall surface of a semiconductor substrate taken along line I-I′ of  FIG. 1 .  
         [0015]      FIG. 13  is a graph illustrating a step height difference on a semiconductor substrate through chemical mechanical polishing (CMP) processes according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]      FIG. 1  is a plan view showing a semiconductor substrate according to the present invention, and  FIGS. 2 through 11  are cross-sectional views illustrating a method of fabricating a semiconductor device taken along line I-l′ of  FIG. 1 .  
         [0017]     Referring to  FIGS. 1 and 2 , a plurality of lower patterns  24  are formed on a semiconductor substrate  10 . The lower patterns  24  are formed on the overall surface of the semiconductor substrate  10 . The lower patterns  24  are preferably formed of copper (Cu). A buried interlayer insulating layer  28  and a pad layer  30  are sequentially formed on the semiconductor substrate  10  to cover the lower patterns  24 . A pad interlayer insulating layer  35  is formed on the pad layer  30 . The pad layer  30  is preferably formed using an insulating layer having an etching ratio different from those of the pad interlayer insulating layer  35  and the buried interlayer insulating layer  28 . The buried interlayer insulating layer  28  is preferably formed to have the same etching ratio as that of the pad interlayer insulating layer  35 .  
         [0018]     Referring to  FIGS. 1 and 3 , an etch stop layer  40  and a planarized interlayer insulating layer  45  are sequentially formed on the pad interlayer insulating layer  35 . Then, a sacrificial layer  50  is formed on the planarized interlayer insulating layer  45 . The planarized interlayer insulating layer  45  and the sacrificial layer  50  may be formed on the semiconductor substrate  10  as shown in  FIG. 1 . The sacrificial layer  50  is preferably formed of an insulating layer having an etching ratio different from that of the planarized interlayer insulating layer  45 . The planarized interlayer insulating layer  45  is preferably formed of an insulating layer having an etching ratio different from that of the etch stop layer  40 . The planarized interlayer insulating layer  45  is preferably formed of an insulating layer having the same etching ratio as that of the pad interlayer insulating layer  35 . At this time, the sacrificial layer  50  preferably has an etching ratio different from that of the etch stop layer  40 .  
         [0019]     According to the present invention, the sacrificial layer  50  is preferably formed using an insulating layer having a higher polishing rate or a higher polishing speed than that of the planarized interlayer insulating layer  45  via a chemical mechanical polishing (CMP) process. In a case in which the planarized interlayer insulating layer  45  is formed using fluorine-doped silicon glass (FSG), the sacrificial layer  50  is preferably formed using BPSG, SiON, or low-k material. The low-k material preferably uses black diamond, coral, aurora, or a material having a dielectric constant similar to those described above. Alternatively, in the case that the planarized interlayer insulating layer  45  is formed using black diamond, coral, aurora, or a material having a dielectric constant similar to those described above, the sacrificial layer  50  may use a lower-k material having a lower dielectric constant than that of the low-k material. The lower-k material preferably uses nanoporous silicate, BCB, flare, ALCAP or LKD.  
         [0020]     Referring to  FIGS. 1 and 4 , a photoresist layer  52  is formed on the sacrificial layer  50 . The photoresist layer  52  is formed to have openings  54  on the lower patterns  24 . Using the photoresist layer  52  as an etch mask, an etch process  56  is sequentially performed on the sacrificial layer  50 , the planarized interlayer insulating layer  45 , the etch stop layer  40 , the pad interlayer insulating layer  35 , and the pad layer  30  via the openings  54 . The etch process  56  forms via contact holes  58  in the pad layer  30 , the pad interlayer insulating layer  35 , the etch stop layer  40 , the planarized interlayer insulating layer  45 , and the sacrificial layer  50  to expose the lower pattern  24 .  
         [0021]     After the formation of the via contact holes  58 , the photoresist layer  52  is removed from the semiconductor substrate  10 .  
         [0022]     Referring to  FIGS. 1 and 5 , a photoresist layer  60  is formed on the sacrificial layer  50 . The photoresist layer  60  is formed to have openings  62  on the via contact holes  58  respectively. Using the photoresist layer  60  as an etch mask, an etch process  64  is sequentially performed on the sacrificial layer  50  and the planarized interlayer insulating layer  45  through the openings  62 . The etch process  64  forms trenches  66  on the via contact holes  58  respectively. At this time, the lower patterns  24  may be exposed through the trenches  66  and the via contact holes  58 . A width of the via contact hole  58  is preferably shorter than a width of the trench  66 .  
         [0023]     After the formation of the trenches  66 , the photoresist layer  60  is removed from the semiconductor substrate  10 .  
         [0024]     Referring to  FIGS. 1 , and  6  through  8 , a diffusion barrier layer  70  and a conductive layer  73  are sequentially formed on the sacrificial layer  50  to fill the via contact holes  58  and the trenches  66 . The diffusion barrier layer  70  is preferably formed to conformally cover the trenches  66  and the via contact holes  58 . The diffusion barrier layer  70  is preferably formed using tantalum nitride (TaN) and titanium (Ti), which are sequentially stacked. Alternatively, the diffusion barrier layer  70  may be formed using tantalum nitride (TaN) or titanium (Ti) individually. The conductive layer  73  is preferably formed using copper (Cu).  
         [0025]     A first CMP process  75  is performed on the conductive layer  73  until the diffusion barrier layer  70  is exposed. The first CMP process  75  forms upper patterns  79  as shown in  FIG. 7  to extend from the via contact holes  58  and fill the trenches  66  respectively. At this time, the first CMP process  75  is performed to expose the diffusion barrier layer  70  and the sacrificial layer  50  at edge regions A, C and a central region B of the semiconductor substrate  10  of  FIG. 1 . The diffusion barrier layer  70  of the boundary regions A, C of the semiconductor substrate  10  is illustrated in  FIG. 7 . The sacrificial layer  50  of the central region B of the semiconductor substrate  10  is illustrated in  FIG. 8 . However, a thickness of the sacrificial layer  50  may not be maintained uniform in  FIGS. 7 and 8  on the overall surface of the semiconductor substrate  10  because of distribution of the polishing process in the first CMP process  75 . Thus, the first CMP process  75  is performed such that the sacrificial layer  50  is maintained with a predetermined thickness T 1  on the edge regions A, C of the semiconductor substrate  10 . The first CMP process  75  is performed such that the sacrificial layer  50  is maintained with a predetermined thickness T 2  at the central portion B of the semiconductor substrate  10 . After the first CMP process  75  is performed, a thickness T 3  of the buried interlayer insulating layer  28  to the sacrificial layer  50  on the edge regions A, C of the semiconductor substrate  10  is different from a thickness T 4  of the buried interlayer insulating layer  28  to the sacrificial layer  50  at the central region B of the semiconductor substrate  10 .  
         [0026]     Referring to  FIG. 1  and FIGS.  9  to  11 , a second CMP process  77  is continuously performed such that the planarized interlayer insulating layer  45  is exposed on the edge regions A, C and the central region B of the semiconductor substrate  10 . The second CMP process  77  is preferably performed for a predetermined time to partially remove the planarized interlayer insulating layer  45 . The second CMP process  77  may be performed by employing abrasive for increasing an etching ratio of the sacrificial layer  50  as compared with an etching ratio of the planarized interlayer insulating layer  45 . The abrasive may use silica, alumina, or ceria.  
         [0027]     In the meantime, the second CMP process  77  may be performed to remove the diffusion barrier layer  70  and the sacrificial layer  50  on the edge regions A, C and the central region B of the semiconductor substrate  10 , and to expose the planarized interlayer insulating layers  45  on the horizontal lines D, E of  FIGS. 9 and 10 . The second CMP process  77  forms diffusion barrier layer patterns  72  and the upper patterns  79  to fill the via contact holes  58  and the trenches  66  sequentially on the edge regions A, C and the central region B of the semiconductor substrate  10 .  
         [0028]     After the performance of the second CMP process  77 , the buried interlayer insulating layer  28  to the planarized interlayer insulating layer  45  on the edge regions A, C and the central region B of the semiconductor substrate  10  is formed with a uniform thickness T 5  as shown in  FIG. 11 . The second CMP process  77  is performed to planarize the upper surface of the semiconductor substrate  10  is planarized, thereby fabricating a semiconductor device  80 .  
         [0029]      FIG. 12  is a graph illustrating a thickness distribution on the overall surface of a semiconductor substrate taken along line I-I′ of  FIG. 1 .  FIG. 13  is a graph illustrating a step height difference on a semiconductor substrate through chemical mechanical polishing (CMP) processes according to the present invention.  
         [0030]     Referring to  FIG. 1  and  FIGS. 12 and 13 , after the performance of the first and second CMP processes  75 ,  77 , thicknesses of the layers on the semiconductor substrate  10  are measured. The thickness measurement may be made with respect to the buried interlayer insulating layer  28  to the sacrificial layer  50  and the buried interlayer insulating layer  28  to the planarized interlayer insulating layer  45  on the edge regions A, C and the central region B of the semiconductor substrate  10 . Thus, the thickness distributions of the thickness measurement results on the overall surface of the semiconductor substrate  10  are illustrated by trend lines  84 ,  88  in  FIG. 12  after the performance of the first and second CMP processes  75 ,  77 .  
         [0031]     After the performance of the first CMP process  75 , one trench line  84  of the trend lines illustrates that the buried interlayer insulating layer  28  to the sacrificial layer  50  have different thicknesses on the edge regions A, C and the central region B of the semiconductor substrate  10 . That is, the buried interlayer insulating layer  28  to the sacrificial layer  50  on the edge regions A, C of the semiconductor substrate  10  have a predetermined thickness distribution in a range of T 3  through T 4 . The buried interlayer insulating layer  28  to the sacrificial layer  50  on the central region B of the semiconductor substrate  10  have thicknesses around a predetermined thickness T 4 . From the result, the upper surface of the semiconductor substrate  10  cannot be planarized through the performance of the first CMP process  75 .  
         [0032]     After the performance of the second CMP process  77 , the other one  88  of the trend lines illustrates that the buried interlayer insulating layer  28  to the sacrificial layer  50  have a uniform thickness distribution on the edge regions A, C and the central region B of the semiconductor substrate  10 . That is, the buried interlayer insulating layer  28  to the sacrificial layer  50  on the edge regions A, C and the central region B of the semiconductor substrate  10  have thicknesses around a predetermined thickness T 5 . Thus, the upper surface of the semiconductor substrate  10  is planarized through the performance of the second CMP process  77 .  
         [0033]     Trend lines  94 ,  98  of step height differences on the overall surface of the semiconductor substrate  10  according to the first and second CMP processes  75 ,  77  are illustrated in  FIG. 13  depending on use of the sacrificial layer  50 . An x-axis of  FIG. 13  represents a removal amount of the conductive layer  73 , the diffusion barrier layer  70 , the sacrificial layer  50 , and the planarized interlayer insulating layer  45 , which are removed from the semiconductor substrate  10  through the first and second CMP processes  75 ,  77 , in accordance with process times. A y-axis of  FIG. 13  represents differences between a maximum value and a minimum value of the layer thicknesses from a selective layer on the overall surface of the semiconductor substrate  10 , which are defined as step height differences, in accordance with process time. The first and second CMP processes  75 ,  77  are performed to have the other trend line  98  different from a trend line  94  shown in the case that the sacrificial layer  50  is not formed on the planarized interlayer insulating layer  45 . The trend lines  94 ,  98  have different slopes from each other in accordance with process times of the first and second CMP processes  75 ,  77 . As shown in the drawing, planarization characteristics on the overall surface of the semiconductor substrate  10  is more degraded in the case of not using the sacrificial layer  50  on the planarized interlayer insulating layer  45 . On the contrary, the first and second CMP processes  75 ,  77  according to the present invention planarize the upper surface of the semiconductor substrate  10  because of the existence of the sacrificial layer  50  on the planarized interlayer insulating layer  45 .  
         [0034]     As described above, the present invention provides a method of planarizing the upper surface of the semiconductor substrate by forming a sacrificial layer on a planarized interlayer insulating layer. Thus, the methods of fabricating semiconductor devices using the sacrificial layer increase process margins of semiconductor fabrication processes.  
         [0035]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.