Abstract:
A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2 n  where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.

Description:
REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of U.S. patent application Ser. No. 12/356,130, filed on Jan. 20, 2009, for a “High Frequency Digital Oscillator on Demand with Synchronization,” which is a continuation-in-part of U.S. patent application Ser. No. 11/843,267, filed on Aug. 22, 2007, for a “High Frequency Digital Oscillator on Demand with Synchronization,” which is a continuation of U.S. patent application Ser. No. 11/308,518, filed on Mar. 31, 2006, for a “High Speed Digital Oscillator-on-Demand with Synchronization,” which claims priority from U.S. Provisional Patent Application No. 60/666,603, filed on Mar. 31, 2005, for a “High Speed Digital Oscillator-on Demand with Synchronization,” and also from U.S. Provisional Patent Application No. 60/670,618, filed on Apr. 13, 2005, for “I/O Output to Clock Edge Synchronization.” 
    
    
     FIELD OF THE INVENTION 
     This invention relates to the field of semiconductor memories or other devices that have a need to synchronize and phase align data and other output signals to the phase of an applied input clock for purposes of delivering said signals to another device, such as a controller, in a reliable and predictable manner. Said invention also applies to other semiconductor devices such as CPU&#39;s and Controllers that have a need to exchange data and other signals between them and other devices in synchronized manner to an applied clock input. 
     This invention also applies to delivering to distant devices clock signals equal in frequency to the applied input clock and phase aligned to same. Such clock signals are known as zero delay clock signals. 
     DESCRIPTION RELATIVE TO THE PRIOR ART 
     In many applications where an output signal from a silicon chip has to maintain a certain relation to the phase of an applied clock, a synchronization mechanism is required. In prior art, such as SDRAM devises, a data bit output named DQ has to be valid within a range of time before and or after the rising edge of the applied clock to the SDRAM device. Such time is defined in the specification time tables of the device as tAC (tACCESS) time from clock. The tAC time is defined to be a quantity of time before or after the rising edge of the clock. Many designs have been implemented in today&#39;s SDRAM, SRAM and GSDRAM devices to accomplish the tAC timings. One such device is known as Delay Locked Loop (DLL). U.S. Pat. No. 5,796,673 by Richard C. Foss et al. describes such DLL method. In all of the designs known, a clock is applied to the device and delay means, such as Delay Locked Loop, are used to phase shift its rising edge, use comparator circuits to align the phases of both signals, clock input and delayed clock, so that the output of the data bit signal will be available at the output pin at a predefined time when clocked by this delayed clock signal. Other synchronization method used, besides DLL, is the Phase Locked Loop (PLL) method. Such methods use some form of analogue circuitry for comparison of phases and resolution of the delay to be adjusted and applied to the clock path and as such take a lot of cycles to synchronize. The delayed synchronization makes such methods undesirable where stopping/starting the operation of such circuitry to conserve power without loss of time for synchronization is required. 
     Existing analogue type synchronizations use an undesirable amount of power, and require many cycles to re-synchronize to the applied clock. In some cases it is not desirable to mix digital with analog circuits in the same manufacturing process. 
     The PLL technique is mainly used to duplicate an applied input clock and distribute single or multiple output copies to distant devices or to internal circuits of the same device with phase synchronization at the receiving device. Such devices are known as zero clock buffer devices. One such requirement is employed in memory module apparatus where multiple SDRAM devices are attached on a printed circuit board and they all require to have input clock signals phase synchronized and aligned to a system clock. To accomplish this, a separate silicon device is designed to accept an input clock and to generate multiple output copies to be distributed to the SDRAM devices. The generation of said signals and the propagation to the distant devices produces a considerable phase shift. To eliminate this phase shift within practical and acceptable measures, the PLL accomplishes that by utilizing a feedback loop that is adjusted to duplicate the delay path and loads from the output of the PLL driver to the SDRAM devices and to compare the phase of this feedback loop to the clock applied to the PLL device. The phases of the applied clock and of the feedback clock are compared and converted to voltage. The result of the comparator controls a Voltage Controlled Oscillator (VCO) that has the ability to advance or retard the output clocks so that the clocks at the SDRAM devices are in phase with the said applied clock to the PLL input within acceptable measures. 
     It is the object to describe methods and apparatus&#39; to accomplish similar results as prior art by use of digital methods and circuits with the added benefits of low power and stop/start feature without loss of time and synchronization and without mixing analog and digital design in the manufacturing processes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Better understanding of the invention will be obtained by reference to the drawings attached and which are described as follows. 
         FIG. 1  depicts block diagram of the gated digital ring oscillator and associated controls. 
         FIG. 2  depicts base ring oscillator frequency divider and phase shifter logic which produce phase shifted clocks every 45 degrees. 
         FIG. 3   a  depicts a timing diagram to show how periods of different clocks, including phase shifted clocks, relate to the ring oscillator base signal. 
         FIG. 3   b  depicts a period signal applied to a delay circuit. 
         FIG. 3   c  depicts a timing diagram of signals appearing in  FIG. 3   b.    
         FIG. 4   a  depicts the period signal applied to a basic delay circuit and to an AND circuit, thereby producing a timing signal for phase selection. 
         FIG. 4   b  is a timing diagram of signals appearing in  FIG. 4   a.    
         FIG. 5  depicts a digital logic implementation for phase clock selection. 
         FIG. 6  depicts a digital logic implementation for incremental delay determination and delay selection. 
         FIG. 7  depicts a timing diagram showing the incremental delay pulse generation. 
         FIG. 8   a  depicts a collection of Set/Rest latches to measure duration of the incremental delay pulse. 
         FIG. 8   b  depicts a timing diagram of the circuit of  FIG. 8   a.    
         FIG. 9  depicts a block diagram showing the details of the incremental delay section of  FIG. 6 . 
         FIG. 10  depicts a block diagram of clock paths for CLK IN and the clock driving an external device along with the feedback path for synchronization. 
         FIG. 10   a  depicts a timing diagram of the circuit of  FIG. 10 . 
         FIG. 11  depicts an overall block diagram of the preferred embodiment of this system. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The specification of U.S. patent application Ser. No. 12/356,130 filed on Jan. 20, 2009 for a “High Frequency Digital Oscillator on Demand with Synchronization” is incorporated herein by reference for the purpose of assisting in the understanding of the operation of the current device. 
     In the following description, the electronic elements are identified as follows: 
     CK=Latch 
     D=Driver 
     O=OR gate 
     R=receiver 
     Referring now to  FIG. 1 , it should first be noted that the oscillator  100  shown has been described in the parent application referenced above. This oscillator will have a maximum frequency four times or eight times higher than CLK IN  112 . For this embodiment the frequency will be considered to be four times higher than the frequency CLK IN  112  and is designated as 4×CLK  101 . 
     The Oscillator will be synchronized to the CLK IN rising edge and will have the ability to STOP/START without requiring many cycles to resynchronize. The relationship of the CLK IN frequency and the oscillator 4×CLK frequency is shown in  FIG. 3   a . The difference in phase of the 4×CLK  101  and the CLK IN  112  is shown graphically as yz in the diagram of  FIG. 3   a . The phase difference between the CLK IN  112  and the equivalent internal clock CLK  00   200  in  FIG. 3   a  is described in the block entitled DELAYX 1   108  in  FIG. 1 . It is equal to the delays caused by modules  103 ,  104 ,  105 ,  106 , and  107 . In practice, other, miscellaneous delays caused by parasitics, etc, will also be added to these totals in calculated the actual delay between the input of adder  106  and the output of inverter  105 . The delay DELAYX 1   108  will vary from one oscillator to another, due to normal variations in the manufacturing process and further due to voltage and temperature variations during operation. 
     Referring now to  FIG. 2 . The 4× oscillator frequency signal is digitally divided by 2 to generate the signal 2×CLK 00   212  and divided by 4 to generate the signal 1×CLK 00   200  and its signal INT PERIOD  208 . In continuation, the phase shifted clocks 1×CLK 45   201 , 1×CLK 90   202 , 1×CLK 135   203 , 1×CLK 180   204 , 1×CLK 225   205 , 1×CLK 270   206 , 1×CLK 315   207  are also generated every 45 degrees or ⅛ cycle of the 1×CLK 00   200  period. The 45 degree time from phase to phase will be different for each CLK IN frequency. One of the 1×CLK 00   200  phase shifted clocks, applied through delay adjustments, will be used to clock the output drivers for DQ OUT  301  synchronization, as shown in  FIG. 3   b , or to produce multiple copies of the CLK IN signal  112  to drive other distant devices and maintain phase synchronization with the CLK IN signal. 
     Referring now to  FIG. 3   a . The timing diagrams of the signals produced and shown in  FIG. 2  are shown herein for better understanding of the system operation. The portions of the waveforms identified by small alpha characters also appear in FIG. 
     In the first embodiment of the invention, the objective is to clock data drivers of a silicon device with a delayed phase of an applied input clock so that the data at the output pin of the device is in some specified phase relationship to the incoming clock phase. Small variations in these phase differences will be unavoidable due to manufacturing tolerances, and the effects of power supply and temperature variations. 
     Referring next to  FIG. 3   b , device  300  is shown in a simplified block diagram form. A CLK IN  112  is the base signal to which the output signals are synchronized. The signal flows from CLK IN  122  through path  303 , and into the OR gate which is the left-most element of the DRV  304  circuit. A delayed version of said signal is also input to the OR gate, via DELAYED CLK EN 2 . The output of the OR gate is input to the DRIVER, which also receives a signal input DQ  1 N  305  signal. 
     Referring now to  FIG. 3   c , an exemplary timing diagram of signals appearing in  FIG. 3   b  is shown. The output of the driver DQ OUT  301  must be in phase with the CLK IN  112  within acceptable tolerance. The propagation of the CLK IN  112  within a normal internal path  303  circuits will clock the driver and produce the DQ OUT  301  after delay DL 3 . The output will be out of phase with the incoming clock as shown in the timing diagram. When the DELAYED CLK SIG  302  is applied to the driver  304  after delay DL 1 , the DQ OUT  301  will be in phase with CLK IN  112 . The description of this operation may be better understood by referring next to  FIGS. 4   a  and  4   b.    
     The signal INT PERIOD  208  feeds two paths. One path is connected to one input of AND gate  403  and the other to a series of delay elements labeled DELAY X 1   108 , DELAY X 2   600  and DELAY X 3   402 . DELAY X 1   108  and DELAY X 3   402  account for the total propagation delay from the CLK IN  112  pin to the input of the driver gate  611  ( FIG. 6 ) at point  602  after the INCREMENTAL DELAY  607  has been selected. Initially, the INCREMENTAL DELAY  607  is assumed to be zero in order to select the proper phase clock. The produced output signal SELECT PHASE  401  of gate  403  is used to clock and latch the selected phase clock of  FIG. 5 . The selected phase clock must appear at the input of gate  611  at point  602  earlier than the expected DQ OUT  604  by an amount of time equal to the delay of the driver DELAY X 2   600 . The selection of incremental delay will fine adjust the phase clock to appear at the proper time at point  602 . 
     The rising edge of the SELECT PHASE  401  is used to clock the appropriate latch  500  of  FIG. 5 . The latch will be set if the data input to the latch is Hi level at the time the rising edge occurs. The data input to each latch is depended on the Boolean expression implemented in gates as shown. One such Boolean expression could be (c) (d/) shown for LATCH H  500  as it appears in  FIG. 5 . 
     Various algorithms are available for selecting a particular phase delay. For example using devices of the zero delay buffer type, an earlier phase may be compared to that of the synchronized data output. The selected clock phase must be such so that its propagation through the selection gates  502  and  503  of  FIG. 5  plus the delay  609  and selected incremental delay  607  of  FIG. 6  is such that the signal arrives at the input of gate  611  at a time ahead of the next rising edge of CLK IN  112  equal to the DELAY X 2   600 . 
     The selected phase accounts for the delay from CLK IN  112  to the selected phase rising edge. It tracks frequency changes and is not affected by logic gate delay changes because all phases of the generated clocks are based on the 4×CLK edges which are fixed for the selected frequency. 
     Referring now to  FIG. 6 . The signal having the selected clock phase selected will pass through selection gates  502 ,  503  and  609  will be ahead of the next rising edge of the CLK IN by an amount greater than the DELAY X 2   600  if there is no incremental delay added to the path. 
     The circuits shown in  FIG. 6  are used to determine the incremental delay required. Referring now to that figure, it is seen that the selected clock phase is used to produce the signal LATCH OUT  605 . This signal is run through a series of delays DELAY X 4   612 , DELAY X 1   108  and DELAY X 2   600  to produce the signal TOTAL DELAY OUT  606 . The AND function  612  of the LATCH OUT, the TOTAL DELAY OUT  606  and the inverted CLK IN deld  109  signals  613  will produce the pulse INCREMENTAL DELAY  603  pulse shown in  FIG. 7 . 
     The gates of  609  are identical to gates  607  and  608  to produce the delay required to generate the signal LATCH OUT  605 . 
     Referring now to  FIG. 8 , the next step is to quantize the width of the INCREMENTAL DELAY pulse in terms of time delay to be represented by gate delays. 
     The INCREMENTAL DELAY pulse  603  is applied to a series of SET/RESET latches  805 ,  806 ,  807  and  808  as shown. The number of latches required may be less or more than four, as shown in this figure. The time required to set each latch is dependent on the speed of the gates of the silicon process and internal wiring parasitics. Once the pulse is applied, each latch will be set in succession. Each setting of each latch resets the previous latch. At the end, there will only be one latch set. Each latch when set will be used to select a delay in the delay tree  902  shown in  FIG. 9 . 
     Referring now to  FIG. 9 . Each delay section  900  will represent a delay number based on the speed of the gates if it is implemented with gates. Delays could also be implemented in passive form. The selected delay will fine adjust the path so that the selected clock phase arrives at the input  602  of the driver gate  611 , as seen in  FIG. 6 , at the predetermined time so that the DQ OUT  604  rising edge aligns to the rising edge of the CLK IN  112 . The number of delay arrangements  900  depends on the number of latches implemented in  FIG. 8 . For example, latch output  803  will select the total delay string. The total selected delay consists of all the delay sections from the DELAY IN  601  input to the output of the OR gate  901 . The total delay is designed to meet requirements based on silicon process speed. There will be a nominal, a minimum and a maximum speed variation from device to device and from lot to lot manufactured. If the device is slow, each delay section in the tree  902  will produce a longer delay and each latch in  FIG. 8  will take longer to set, thus resulting in lower delay value. If the device is fast the corresponding opposite will occur. This phenomenon will keep the delay calibrated. 
     Second Embodiment 
     Referring now to  FIG. 10 , In a second embodiment of the invention, a silicon device  1000  takes the input CLK IN  112  and produces outputs (multiple copies) CLK OUT  1001  and a FB OUT  1006  for feedback. Outputs  1001  are fed to the input  1013  of devices, such as SDRAM, at distant points. 
     There is a delay DL 4   1012  from CLK OUT  1001  to the input of SDRAM at point  1013  due to wiring and printed circuit board parasitics. 
     The requirement is that the clock at the input of SDRAM at point  1013  and the CLK IN  112  be phase aligned. 
     The CLK OUT  1006  and the CLK IN  112  are, first, phase aligned according to the first embodiment and the methods and circuits described above. Then, the DELAYED CLK  1011  is further adjusted so that it appears earlier by an amount of time equal to the delay DL 4   1012 . To determine the value of DL 4   1012 , refer to the block diagram  FIG. 10  and timing diagram  FIG. 10A . 
     The delay DL 4   1012  from the CLK OUT  1006  to the SDRAM device input  1013  is duplicated and applied to the path from the FB CLK OUT  1007  to the input FB CLK IN  1008 . The receivers  1014  and the paths for CLK PERIOD  1002  and FB PERIOD  1003  are identical. When both period signals are ANDed, a FB DELAY  1004  pulse is created and is shown in  FIG. 10A  as d 4 . This pulse is converted to time delay by applying it to a circuit similar to the one shown in  FIG. 8  and by selection of the delay from the delay tree of  FIG. 9 . The number of elements in  FIG. 8  and  FIG. 9  will have to be increased in order to accommodate all the delay adjustments. The amount of delay determined will be subtracted from the delay originally selected to have the CLK OUT  1006  in phase with the CLK IN  112 . The delay selected is saved and always is applied as coarse delay adjustment for the feedback loop. After the initial coarse delay adjustment, there will be a shorter FB DELAY  1004  pulse created. This pulse is further applied to another circuit similar to the one in  FIG. 8  for further fine delay adjustment. Ideally, there shouldn&#39;t be any FB DELAY  1004  pulse created after all the adjustments. This will depend on the techniques used to resolve the FB DELAY  1004  pulse duration. The remaining pulse will represent the phase difference of the CLK IN  112  and the CLK OUT at  1013  of the SDRAM. This phase difference must be within acceptable measure. This fine delay adjustment may be dynamically tested every clock cycle to continuously synchronize the clocks or tested in time intervals. 
     The proposed synchronization methods can be applied to devices other than zero buffer type. Such devices include all of the memory devices Dynamic, Static or Flash and in memory controllers and CPU&#39;s. 
     Referring now to  FIG. 11 , the relationship between the signals in the individual drawings is shown. The numbers of the individual blocks in this drawing correspond to the figure numbers of the other drawings. For instance, the block entitled “ 1 . gated ring oscillator and associated controls” corresponds to  FIG. 1 . The reference numbers of the signals shown corresponds to the reference numbers in the other drawings. 
     It will be apparent that improvements and modifications may be made within the purview of the invention without departing from the scope of the invention defined in the appended claims.