Abstract:
An inverter comprising a low-side switching element in series with a first primary winding; a high-side switching element in series with a second primary winding, where the combination of the low-side switching element and first primary winding is connected in parallel with the combination of the high-side switching element and the second primary winding; and a clamping capacitor having one terminal connected to the first primary winding and having a second terminal connected to the second primary winding. Other embodiments are described and claimed.

Description:
PRIORITY CLAIM 
     This application is a continuation-in-part of U.S. patent application Ser. No. 11/419,354, filed on 19 May 2006, which is a continuation of U.S. patent application Ser. No. 10/850,351, filed 19 May 2004, issued into U.S. Pat. No. 7,161,305 B2 on 9 Jan. 2007. 
    
    
     FIELD 
     The present invention relates to power circuits, and more particularly, to inverter circuits for converting DC power to AC power. 
     BACKGROUND 
     Power inverter circuits convert DC power to AC power, and find widespread applications in many systems. For example, power inverters are often used to drive cold cathode fluorescent lamps in liquid crystal display monitors. 
     Two prior art power inverter circuits are illustrated in  FIGS. 11 and 12 , and their operations are well known in the art of power inverter circuits. Such circuits may experience voltage spike problems. For example, the push-pull inverter circuit of  FIG. 12  may experience voltage ringing of three to four times the input source voltage V IN . As a result, snubbers are often used to suppress ringing. But typically, such snubbers dissipate power. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an inverter according to an embodiment. 
         FIG. 2  illustrates an inverter according to an embodiment. 
         FIG. 3  illustrates an inverter according to an embodiment. 
         FIG. 4  illustrates gate voltage waveforms for the embodiment of  FIG. 3 . 
         FIG. 5  illustrates an inverter according to an embodiment. 
         FIG. 6  illustrates gate voltages, nodal voltages, and lamp current for the embodiment of  FIG. 5 . 
         FIG. 7  illustrates an inverter according to an embodiment. 
         FIG. 8  illustrates nodal and gate voltages for the embodiment of  FIG. 7 . 
         FIG. 9  illustrates an inverter according to an embodiment. 
         FIGS. 10 and 11  illustrate prior art inverters. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     In the description that follows, the scope of the term “some embodiments” is not to be so limited as to mean more than one embodiment, but rather, the scope may include one embodiment, more than one embodiment, or perhaps all embodiments. 
       FIG. 1  illustrates a power inverter circuit according to an embodiment. Voltage source  102  is a DC (Direct Current) voltage source. The output at node (port)  104  provides an AC (Alternating Current) voltage to discharge lamp  106 . Discharge lamp  106  may be a cold cathode fluorescent light (CCFL), for example. Embodiments are not necessarily limited to driving lamps, so that other types of loads may be driven. Furthermore, more than one load may be driven for some embodiments. 
     Windings T P1 , T P2 , and T S  are windings in a transformer. Windings T P1  and T P2  form a first primary winding and a second primary winding of the transformer, and winding T S  forms a secondary winding of the transformer. As is conventionally done in transformer symbols, the relative placement of the terminal dots as shown in  FIG. 1  indicate the relative algebraic signs of various voltage drops across the windings due to the mutual magnetic coupling among windings T P1 , T P2 , and T S . That is, let a first voltage difference be the voltage difference between the (dotted) terminal of T P1  directly connected to capacitor C D  and the terminal of T P1  directly connected to voltage source  102 , a second voltage difference be the voltage difference between the (dotted) terminal of T P2  directly connected to capacitor C D  and the terminal of T P2  directly connected to ground, and a third voltage be the voltage difference between the (dotted) terminal of T S  directly connected to inductor L 1  and the terminal of T S  directly connected to ground. Then, for the relative positions of the terminal dots as indicated in  FIG. 1 , these three voltage differences all have the same algebraic sign. 
     It should be appreciated that the placement of the terminal dots are relative to each other, so that all dots of the first and second primary windings as shown in  FIG. 1  may be moved to the other winding terminals simultaneously. Furthermore, it should be appreciated that the placement of the dot for secondary winding T S  may be on its other terminal. Stated more generally, the first and second voltage differences as defined in the previous paragraph have the same algebraic sign, but not necessarily the same algebraic sign as the third voltage difference. 
     For some embodiments, windings T P1  and T P2  are such that the first and second voltage differences as defined above are substantially equal to each other. For some embodiments, as discussed below with respect to  FIG. 2 , capacitor C D  and windings T P1  and T P2  may be designed so that the average voltage difference across capacitor C D  is substantially equal to the input source voltage V IN  (the voltage of voltage source  102 ) and the voltage drops across windings T P1  and T P2  are substantially equal to each other. For such embodiments, it is expected that the voltage drop across switches  108  and  110  do not exceed 2V IN . 
     By switching elements  108  and  1100 N and OFF at a frequency resonant with the frequency of the tank circuit formed by inductor L 1  and capacitor C 1 , DC power is provided by voltage source  102  and AC power is delivered to lamp  106 . 
       FIG. 2  illustrates an embodiment, where power nMOSFET  202  (n-Metal-Oxide-Semiconductor Field Effect Transistor) serves as switching element  108 , and diode  204  serves as switching element  110 . In  FIG. 2 , control circuit  112  does not directly control the action of diode  204 . Accordingly, the connections between control circuit  112  and switching elements  108  and  110  in  FIG. 1  do not necessarily imply that there are direct connections. 
     When nMOSFET  202  turns ON, secondary winding T S  receives energy from the input source and from the energy stored in capacitor C D . The drain-source current through nMOSFET  202  is the sum of the magnetizing inductance current of the transformer and the reflected resonant inductor current due to L 1 . In this situation diode  204  is OFF. 
     When nMOSFET  202  turns OFF, the reflected resonant inductor current due to inductor L 1  flows through diode  204  to continue its resonance. The drain voltage of nMOSFET  202  is then brought up to V IN +V C , where V C  is the voltage across capacitor C D . Capacitor C D  may be designed to be large enough so that V C  is substantially constant and substantially equal to V IN . Therefore, the maximum voltage stress on nMOSFET  202  is expected to be about 2V IN . 
     The current through diode  204  is the sum of the magnetizing current and the reflected resonant inductor current due to L 1 . Because the reflected resonant inductor current changes polarity, at times the net current through diode  204  will decrease to zero. The drain voltage of nMOSFET  202  may also decrease to V IN  and oscillate around this level. This oscillation may be caused by the leakage inductance between primary windings T P1  and T P2  and the parasitic capacitance of these primary windings, and nMOSFET  202 . 
     For high-power applications, the current through diode  204  may be large enough to overheat diode  204  due to its power loss. In this case, some embodiments may replace diode  204  with a low drain-to-source ON resistance (R DS (ON)) MOSFET.  FIG. 3  illustrates an embodiment in which switching element  108  comprises power nMOSFET  302 , and switching element  110  comprises power nMOSFET  304 . Their respective body diodes are shown in  FIG. 3 . For ease of illustration, instead of explicitly showing a control circuit connected to the gates of power nMOSFETs  302  and  304 , their gate voltages are indicated as V 1  and V 2 , respectively, which are provided by control circuit  112 . 
     For some embodiments, the ON time of power nMOSFET  304  (time for which power nMOSFET  304  is turned ON) is the same as that of power nMOSFET  302 , where the pulses driving the gates of power nMOSFETs  302  and  304  are time interleaved. Such an embodiment is expected to achieve essentially a symmetrical voltage and current drive for a resonant tank, similar to the symmetrical voltage and current drive provided by the prior art push-pull inverter of  FIG. 12 . However, it is expected that the voltage stress of power nMOSFETs  302  and  304  do not exceed 2V IN , so that a snubber is not required. 
     The gate voltage waveforms for power nMOSFETs  302  and  304  are illustrated in  FIG. 4  for some embodiments. From  FIG. 4 , it is seen that the period for waveform voltage V 1 , the gate voltage on power nMOSFET  302 , is shifted by 180° (π radians) relative to the waveform for voltage V 2 , the gate voltage on power nMOSFET  304 . Both waveforms have the same ON time. 
       FIG. 5  illustrates another embodiment, where as in the embodiment of FIG.  3  switching element  108  comprises a power nMOSFET, labeled  502  in  FIG. 5 , but where switching element  110  comprises power pMOSFET  504 . The gate voltage waveforms V 1  and V 2  for the embodiment of  FIG. 5  are illustrated in  FIG. 6 . Note that the ON time for the gate voltage of pMOSFET  504 , voltage V 2 , is larger than the ON time for the gate voltage of nMOSFET  502 , voltage V 1 . Because the source node of pMOSFET  504  is tied to the voltage V IN  (of voltage source  506 ), the integration of a gate driver circuit into a controller (e.g., control circuit  112 ) is expected to be feasible for some embodiments. The embodiment illustrated in  FIG. 5  may be of interest for low to medium power applications. Capacitor C D  is sometimes referred to as a clamping capacitor. 
     Assuming that the voltage on C D  is equal to V IN ,  FIG. 6  illustrates the steady state operation waveforms for an embodiment according to  FIG. 5 . In  FIG. 6 , “A” and “B” refer to the node voltages at nodes A and B in  FIG. 5 . Four operation stages are illustrated in one switching cycle. 
     During a first stage between times t 1  and t 2 , power pMOSFET  504  turns ON while power nMOSFET  502  turns OFF, so that the voltage at node B is equal to V IN . The voltage at node A is clamped roughly to 2V IN . Both primary windings T P1  and T P2  receive the positive driving voltage, V IN . Consequently, the lamp (load) current increases in the positive direction. 
     During a second stage between the times t 2  and t 4 , both power pMOSFET  504  and power nMOSFET  502  are OFF. Their body diodes conduct the leakage inductor currents. The voltage at node A is clamped to ground or 2V IN , and the voltage at node B is clamped to V IN  or −V IN . 
     During a third stage between the times t 4  and t 5 , power nMOSFET  502  turns ON and power pMOSFET  504  turns OFF. The voltage at node A is at ground potential and the voltage at node B is equal to −V IN . Both primary windings T P1  and T P2  receive the negative driving voltage, −V IN . The lamp current will increase in the negative direction. 
     During a fourth stage between times t 5  and t 7 , both power nMOSFET  502  and power nMOSFET  504  are OFF. The operation of this stage is the similar to that discussed above with respect to the second stage. 
     If V IN  is less than the maximum gate-to-source voltage allowed for power pMOSFET  504 , then a relatively simple circuit may be used to provide the gate voltages, as illustrated in the embodiment of  FIG. 7  where controller  702  is a conventional push-pull controller well known in the art of power inverter circuits. In  FIG. 7 , inverter circuit  704  and buffer stage  706  are used to provide the gate voltage of pMOSFET  708 . For simplicity of illustration, the circuit related to the load (e.g., discharge lamp  106  and tank circuit L 1  and C 1 ) is not shown. The waveform voltages associated with the voltages G 1 , G 2 , and G 3  indicated in  FIG. 7  are illustrated in  FIG. 8 . 
     A half-bridge controller, as is well known in the art of power inverter circuits, may also be used in some embodiments. For some embodiments in which switching element  110  is a power nMOSFET, a half-bridge controller may be used in a conventional fashion to directly drive the gate voltages. For some embodiments in which switching element  110  is realized by a power pMOSFET, some embodiments may utilize a conventional half-bridge controller as shown in the embodiment of  FIG. 9 . 
     It is expected that inverter circuits according to some of the embodiments discussed above are more efficient than some prior art inverter circuits, such as those illustrated in  FIGS. 10 and 11 , because they reduce current in the primary side power MOSFETs by half compared to these prior art circuits. Furthermore, it is expected that when compared to the push-pull inverter circuit of  FIG. 11 , some embodiments do not have the same degree of voltage spikes, and the maximum voltage stress on the power MOSFETs is expected to be clamped to two times the input voltage V IN , where as the push-pull inverter circuit of  FIG. 11  may experience voltage ringing of over three to four times V IN . 
     Although the subject matter has been described in language specific to structural features, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims. Accordingly, various modifications may be made to the described embodiments without departing from the scope of the invention as claimed below. 
     It is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected together by an interconnect (transmission line). In integrated circuit technology, the interconnect may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected together by polysilicon, or copper interconnect, where the length of the polysilicon, or copper interconnect, is comparable to the gate lengths. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON. 
     It is also to be understood in these letters patent that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B. 
     It is also to be understood in these letters patent that various circuit components and blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit components and blocks may still be considered connected to the larger circuit.