Abstract:
A method for determining duty-cycles of respective pulse width modulated (PWM), space vector modulated (SVM) control signals of an inverter, may include storing values of the duty-cycles as a function of a position of the multi-phase electric load in a look-up table. The method also may include determining a phasor angle representing applied sinusoidal voltages. The method also may include determining the duty-cycles as a function of the angle, and storing, in the look-up table, values of two pre-established waveforms relative to at least one duty-cycle as a function of the angle in at least two 60° degree angular sectors, by at least, identifying which of six 60° angular sectors the angle belongs, calculating a difference between the angle and an angular sector lower bound, and generating values as a function of the identified angular sector of the difference and the two pre-established waveforms stored in the look-up table.

Description:
FIELD OF THE INVENTION 
   This invention relates to control techniques of multi-phase electric loads. More particularly, the invention relates to a method and a device for establishing the duty-cycle of pulse width modulation (PWM) control signals according to a space vector modulation (SVM) mode controlling an inverter that drives a multi-phase electric load. 
   BACKGROUND OF THE INVENTION 
   Space Vector Modulation (SVM) is a modulation technique used for controlling induction, controlling brushless motors, and for generating sinusoidal phase voltages starting from a DC voltage source. This technique is widely used because it allows generation of large sinusoidal voltages with a total harmonic distortion (THD) smaller than classical PWM control techniques. 
     FIG. 1  depicts a control scheme of a common three-phase motor. By driving the switches of each half-bridge with respective PWM signals, the duty-cycle of which varies with time according to a modulating signal, a generally sinusoidal voltage is applied to each winding of the motor. Typically, the control block CONTROL UNIT includes a standard proportional-integral (PI) controller and a logic circuit that generates the driving signals for the desired control action commanded by the controller. The SVM technique is briefly illustrated hereinbelow. 
   Space Vector Modulation (SVM) may require a sinusoidal modulation of PWM signals for optimizing the switching pattern of the switches of the half-bridges of the inverter. This technique is characterized by a very good modulation ratio, that is the ratio between the rms value of the modulated wave and the mean value thereof. This technique controls the global behavior of the multi-phase system and not the behavior of each single winding. 
   The SVM technique has many advantages: 
   high performances in controlling motors at medium/high speed; high efficiency (about 86%); a good torque control; good performance at start-up of the motor; and regulation of the torque at a constant value with a reduced ripple. 
   For the case of a three-phase motor, referring to  FIG. 2 , suppose that in a modulation period a triplet of three-phase voltages is to be applied. This triplet may be represented by the vector  V S   , the module and phase of which are V and γ respectively, that is comprised between two generic configurations  V K    and  V K+1    of the six possible active configurations of the inverter that drives the motor. Application of the vector  V S    is done by applying the vector  V K    (that in  FIG. 2  is  V 1   ) for a time α, the vector  V K+1    (that in  FIG. 2  is  V 2   ) for a time β and a null vector  V 0    (000 or 111, are not depicted in  FIG. 2 ) for a time δ, such that in a PWM period the mean value of the voltage equals the vector  V S   . 
   The intervals during which the vectors  V   k ,  V   k+1  and  V   0  are applied are those that verify the following integral equation: 
                     ∫   0     Δ   ⁢           ⁢   T       ⁢         V   _     s     ⁢           ⁢     ⅆ   t         =         ∫   0   α     ⁢         V   _     k     ⁢           ⁢     ⅆ   t         +       ∫   0   β     ⁢         V   _       k   +   1       ⁢           ⁢     ⅆ   t         +       ∫   0   δ     ⁢         V   _     0     ⁢           ⁢     ⅆ   t                   (   1   )               
wherein ΔT is the PWM period and α, β and δ are the turn-on times of the upper switches of the inverter. This equation is solved considering that  V   k  and  V   k+1  are constant in a module for each of the six sectors, and  V   S  is constant within a PWM period. Equation (1) becomes:
     V     S   ·ΔT=  V     k   ·α+  V     k+1   ·β+  V     0 ·δ α+β+δ=Δ T   (2) 
Considering that  V   0 =0, it is:
 
                   β   =       2     3       ⁢       V   ⁢           ⁢   sin   ⁢     (     γ   -     γ   k       )         V   k       ⁢   Δ   ⁢           ⁢   T       ⁢     
     ⁢     α   =           V   ⁢           ⁢     cos   ⁡     (     γ   -     γ   k       )           V   k       ⁢   Δ   ⁢           ⁢   T     -     β   2         ⁢     
     ⁢     δ   =       Δ   ⁢           ⁢   T     -   α   -   β               (   3   )               
being γ the angle of the phasor  V S    that represents the triplet of voltages to be applied to the motor and γ k  is the angle of the phasor  V   k .
 
   After having calculated the conduction times, it is necessary to establish the strategy with which the vectors  V   k ,  V   k+1  and  V   0  are applied. The simplest way is to sequentially establish the conduction times α, β and γ in a period ΔT, as depicted in  FIG. 3 . 
   This approach has several drawbacks: uneven switching frequency of the electronic components; and the possibility of simultaneous switching of two half-bridges with a consequent increase of power losses. 
   The above problems are prevented by properly subdividing each conduction period according to a so-called seven states logic, illustrated in  FIG. 4 , that allows switching a half-bridge at the time. The same observation made for the first sector holds, with the respective differences having been considered, when the phase γ is in the second sector. Of course, in this case, α is not referred to  V 1    but to  V 2   . This implies that it may be necessary to take into account the sector to which the phase angle γ currently belongs for calculating the correct switching pattern, and thus for correctly carrying out the SVM algorithm. To determine the sector of pertinence, it is necessary to know the phase of the reference vector, that may be calculated with the following formula: 
                 γ   =     arctan   ⁡     (       ⁢   m   ⁢     (       V   _     s     )         ⁢     e   ⁡     (     V   s     )           )               (   4   )               
wherein the operators            m(.) and          e(.) produce the imaginary part and the real part of their argument.

   If α, β and δ are known, it is possible to calculate the respective duty-cycles t 1 , t 2 , t 3  of the high-side of each half-bridge of the inverter using a look-up table that implements the seven-states logic for each sector, as shown in the following table 1: 
   
     
       
             
             
             
             
             
           
         
             
                 
                 
             
           
           
             
                 
                 
               Sector 0 
               Sector 1 
               Sector 2 
             
             
                 
                 
             
             
                 
               t1 
               
                 
                   
                     
                       
                         δ 
                         4 
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           β 
                           2 
                         
                         + 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           ΔT 
                           2 
                         
                         - 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
             
             
                 
                 
             
             
                 
               t2 
               
                 
                   
                     
                       
                         
                           α 
                           2 
                         
                         + 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         δ 
                         4 
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         δ 
                         4 
                       
                       ΔT 
                     
                   
                 
               
             
             
                 
                 
             
             
                 
               t3 
               
                 
                   
                     
                       
                         
                           ΔT 
                           2 
                         
                         - 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           ΔT 
                           2 
                         
                         - 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           α 
                           2 
                         
                         + 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
             
             
                 
                 
             
             
                 
                 
               Sector 3 
               Sector 4 
               Sector 5 
             
             
                 
                 
             
             
                 
               t1 
               
                 
                   
                     
                       
                         
                           ΔT 
                           2 
                         
                         - 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           α 
                           2 
                         
                         + 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         δ 
                         4 
                       
                       ΔT 
                     
                   
                 
               
             
             
                 
                 
             
             
                 
               t2 
               
                 
                   
                     
                       
                         
                           β 
                           2 
                         
                         + 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           ΔT 
                           2 
                         
                         - 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           ΔT 
                           2 
                         
                         - 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
             
             
                 
                 
             
             
                 
               t3 
               
                 
                   
                     
                       
                         δ 
                         4 
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         δ 
                         4 
                       
                       ΔT 
                     
                   
                 
               
               
                 
                   
                     
                       
                         
                           β 
                           2 
                         
                         + 
                         
                           δ 
                           4 
                         
                       
                       ΔT 
                     
                   
                 
               
             
             
                 
                 
             
           
        
       
     
   
   By comparing ( FIG. 5 ), a triangular modulating signal with three thresholds ta, tb and tc, the six PWM driving signals a H , b H  and c H  and a L , b L  and c L , (H=high-side, L=low-side) that drive the inverter are obtained, as shown in  FIG. 5 , with respective duty-cycles t 1 , t 2 , t 3 . 
   The above described procedure implements a so-called PWM center aligned modulation, that implies a symmetry around the mid-point of the PWM period. This configuration produces in each period two pulses line-to-line with the modulating signal. Thus, the effective switching frequency is doubled, with the effect of reducing the ripple of current without the drawback of incrementing the dynamical power consumption of the switching devices of the inverter. 
   In  FIG. 5 , the letters a, b, c indicate the first, second and third branch of the inverter, the letter H indicates the high-side switches, and the letter L indicates the low-side switches.  FIG. 5  is only a basic scheme that does not accounts for the dead time, that is the time in which both switches must be off for preventing shorts between the supply and ground. The technique is illustrated in greater detail in Shinohara, “Comparison Between Space Vector Modulation and Subharmonic Methods for Current Harmonics of DSP-Based Permanent-Magnet AC Servo Motor Drive System”, Sun et al., “Optimized Space Vector Modulation and Regular-Sampled PWM”, Chen et al, “A New Space Vector Modulation Technique for Inverter Control”, and Zhou et al., “Relationship Between Space-Vector Modulation Technique for Inverter Control.” 
   The SVM technique described above is usually implemented via software by DSPs or microcontrollers equipped with dedicated peripherals. In Rathnakumar et al., “A New Software Implementation of Space Vector PWM”, classic software implementations using Matlab and Psim are described that show the great complexity of the calculations required for a correct implementation of the SVM. 
   In “Optimized Space Vector Modulation and Overmodulation with the XC866”, Infeon Application Note AP0803620, V 2.0, a software implementation with an 8-bit microcontroller is shown. In order to make the calculation of the SVM easier, the symmetry about angles of 60° intrinsic to the SVM are exploited, and the values of the sine and cosine functions are stored in a look-up table (LUT). A similar approach is presented also in Copeland, “Generate Advanced PWM Signals Using 8-bit mCs”. Also hardware implementations of the SVM are disclosed in the literature. A possible hardware implementation, particularly for implementing a PWM using a Time Processor Unit (TPU) of the microcontroller Motorola 68HC16 is illustrated in Ahmad et al., “Comparison of Space Vector Modulation Techniques Based on Performance Indexes and Hardware Implementation”. In Attaianese et al, “A Low Cost Digital SVM Modulator with Dead Time Compensation”, a hardware system input with the values of duty-cycles calculated by the microcontroller for carrying out the SVM and correctly driving the inverter, and even compensating the dead time, is described. 
   In Takahashi et al., “Implementation of Complete AC Servo Control in a Low Cost FPGA and Subsequent ASSP Conversion”, a hardware FPGA implementation of a complete control system implementing a so-called Field Oriented Control (FOC) technique is disclosed. The document also discloses a hardware implementation of SVM. This approach has been commercially implemented in two integrated circuits marketed by International Rectifier “High Performance Configurable Digital AC Servo Control IC”, International Rectifier DataSheet No. PD60224 Rev. B, and “High Performance Sensorless Motion Control IC”, International Rectifier DataSheet No. PD60225 Rev. B. 
   SUMMARY OF THE INVENTION 
   An efficient method of determining the three duty-cycles of the three PWM control signals of an inverter that drives a three-phase load in SVM mode and that may require a reduced number of steps has now been found. 
   The method may advantageously exploit the fact that the three duty-cycles may be modulated, as a function of the angle γ of the phasor that represents the triplet of voltages to be applied, according to modulating signals that may be reconstructed from only two waveforms using reflection and reversal operations. By storing these two waveforms in two look-up tables, it may be possible to reconstruct the modulating signals for each value of the angle γ, with a single memory access and an addition. 
   According to a preferred embodiment of the method, the values stored in the two look-up tables may be translated and scaled in the interval [−1; 1] before being eventually multiplied by a reference value  OUT PI. The reference value output  OUT PI is determined by a standard PI (proportional-integral) controller that may determine the module V of the vector  V S   , in order to avoid excessively loading only the switches of the high-side or of the low-side of the inverter. 
   The method may also be implemented by a circuit generating signals that represent three duty-cycles of three respective PWM control signals in SVM mode of an inverter. As an alternative, the method may be implemented through software executed by a microprocessor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  depicts a prior art control scheme of a three-phase motor through an inverter. 
       FIG. 2  illustrates a prior art phasor of a Space Vector Modulation. 
       FIG. 3  illustrates how the turn-on time of the switches of the inverter varies for obtaining the phasor depicted in  FIG. 2 . 
       FIG. 4  is a diagram similar to that of  FIG. 3  but with seven states. 
       FIG. 5  illustrates prior art sample PWM driving voltages of the high-side and of the low-side of a power stage. 
       FIG. 6  illustrates a phasor of Space Vector Modulation in sector  2  in accordance with the invention. 
       FIG. 7  illustrates how the look-up table of a SVM driving system of this invention. 
       FIG. 8  is a graph representation of the values that must be reconstructed by accessing the look-up table for obtaining the desired Space Vector Modulation in accordance with the invention. 
       FIG. 9  illustrates how to access a single look-up table for obtaining the desired Space Vector Modulation in accordance with the invention. 
       FIG. 10  is a graph representation that highlights the symmetries of the waveforms to be reconstructed by accessing a look-up table in accordance with the invention. 
       FIG. 11  depicts a generic block that generates driving signals of a final power stage for carrying out a Space Vector Modulation in accordance with the invention. 
       FIG. 12  illustrates a SVM waveform represented through digital values with 10 bits in accordance with the invention. 
       FIG. 13  illustrates a circuit according to the present invention for obtaining portions of the waveform of  FIG. 12  by accessing to two look-up tables each storing the respective values to a respective angular sector of 60 degrees. 
       FIG. 14  depicts how to generate a waveform that is a reflected replica of a waveform stored in a look-up table in accordance with the invention. 
       FIG. 15  depicts a waveform that is a reflected replica of a waveform relative to the second q 0  in accordance with the invention. 
       FIG. 16  depicts the waveform to be generated for the SVM driving scaled in a unitary range in accordance with the invention. 
       FIGS. 17   a  to  17   c  illustrate driving signals of the high-side and of the low-side of the final power stage for generating the waveform of  FIG. 12 . 
       FIG. 18  depicts the waveform of  FIG. 12  scaled in a range centered around zero. 
       FIG. 19  depicts a circuit for generating the waveform of  FIG. 12  thus making the final stage generate the output of  FIG. 18 . 
       FIG. 20  depicts the waveform of  FIG. 12  scaled between 0.15 and 0.35. 
       FIGS. 21   a  to  21   c  illustrate, respectively, how to generate from a modulation signal the respective PWM driving signals for the high-side and the low-side of the inverter, for generating the waveform of  FIG. 20 . 
       FIG. 22  depicts a waveform analogous to that of  FIG. 12  scaled in the range 0-0.5. 
       FIG. 23  depicts a circuit of this invention for generating a waveform similar to that of  FIG. 18 . 
       FIGS. 24   a  to  24   c  depict waveforms obtained with the circuit of  FIG. 23 . 
       FIG. 25  is a graph representation of the three waveforms to be generated in accordance with the invention. 
       FIG. 26  is a RTL description of a circuit of this invention for generating the waveforms of  FIG. 25 . 
       FIG. 27  is a RTL description of the upstream block depicted in  FIG. 26 . 
       FIG. 28  is a RTL description of the block LUTs represented in  FIG. 27 . 
       FIG. 29  is a RTL description of the block downstream depicted in  FIG. 27 . 
       FIGS. 30   a  to  30   c  are graph representation of comparisons of results of VHDL and Simulink simulations of the circuit of this invention. 
       FIGS. 31   a  to  31   c  are comparison graph representations of the results of the VHDL simulations of the circuits of this invention in the case in which the look-up table stores the value of two adjacent sectors of 60° or the values of two sectors of 30° in accordance with the invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Compared to a classic SVM technique, according to a first embodiment, a single look-up table is used by accessing the look-up table once for each winding during each PWM period, thus avoiding the otherwise complex calculations necessary for determining the three duty-cycles t 1 , t 2  and t 3  that, besides making the computations of the algorithm more onerous, generally require additional hardware resources. 
   By reformulating equations (3), the following relations are obtained: 
                   β   =         2     3       ·     V     V   K       ·     sin   ⁡     (     γ   -     γ   K       )       ·   Δ     ⁢           ⁢   T       ⁢     
     ⁢     a   =         V     V   K       ·     [       cos   ⁡     (     γ   -     γ   K       )       -       1     3       ·     sin   ⁡     (     γ   -     γ   K       )           ]     ·   Δ     ⁢           ⁢   T       ⁢     
     ⁢     δ   =       Δ   ⁢           ⁢   T     -   α   -   β               (   5   )               
(γ−γ K ) being the angle between  V S    and  V   K  ( FIG. 6 ). By substituting these equations in Table 1, it is noticed that t 1 , t 2 , t 3  are a function of the ratio
 
           V     V   K           
and of the angle (γ−γ K ), wherein V K  is the supply voltage of the inverter, V is the module of the control vector  V S   , γ is the angle between the phasor  V S    and the origin of the reference, and γ K  is the angle of the phasor  V   K  in respect to the origin of the reference.
 
   It is possible to normalize t 1 , t 2 , t 3  in respect to the module V of the vector  V S    thus obtaining the following equations: 
   
     
       
         
           
             
               
                 
                   
                     t 
                     1 
                     ′ 
                   
                   = 
                   
                     
                       
                         t 
                         1 
                       
                       V 
                     
                     = 
                     
                       
                         f 
                         1 
                       
                       ⁡ 
                       
                         ( 
                         
                           γ 
                           , 
                           
                             γ 
                             K 
                           
                         
                         ) 
                       
                     
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     t 
                     2 
                     ′ 
                   
                   = 
                   
                     
                       
                         t 
                         2 
                       
                       V 
                     
                     = 
                     
                       
                         f 
                         2 
                       
                       ⁡ 
                       
                         ( 
                         
                           γ 
                           , 
                           
                             γ 
                             K 
                           
                         
                         ) 
                       
                     
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     t 
                     3 
                     ′ 
                   
                   = 
                   
                     
                       
                         t 
                         3 
                       
                       V 
                     
                     = 
                     
                       
                         f 
                         3 
                       
                       ⁡ 
                       
                         ( 
                         
                           γ 
                           , 
                           
                             γ 
                             K 
                           
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
   
   In order to implement the look-up table it is necessary to vary the angle γ in the range [0°, 360°] modifying the angle γ K  at each 60°, according to Table 2. 
   
     
       
             
             
             
           
         
             
                 
               TABLE 2 
             
             
                 
                 
             
           
           
             
                 
               γ ∈ [0, 60°] 
               γ K  = 0° 
             
             
                 
               γ ∈ [60°, 120°] 
               γ K  = 60° 
             
             
                 
               γ ∈ [120°, 180°] 
               γ K  = 120° 
             
             
                 
               γ ∈ [180°, 240°] 
               γ K  = 180° 
             
             
                 
               γ ∈ [240°, 300°] 
               γ K  = 240° 
             
             
                 
               γ ∈ [300°, 360°] 
               γ K  = 300° 
             
             
                 
                 
             
           
        
       
     
   
   Therefore, three look-up tables that output the values t′ 1 , t′ 2 , t′ 3 , given the value of the angle γ, are established. With the relations, (6) the values t 1 , t 2 , t 3 , essential for driving the high-side of the inverter are calculated. The functioning principle of the algorithm is illustrated in  FIG. 7 . The angle γ as a function of the position of the rotor of the motor is determined by sensing it with dedicated sensors or by estimating it through algorithms. The relative look-up table (LUT) is accessed. 
     FIG. 8  illustrates the three graph representations of the duty-cycles t 1 , t 2 , and t 3  as a function of the position of the rotor: they are very similar to each other but for an outphasing of 120°. Instead of storing three distinct waveforms, it is convenient to store only one of them and properly modify the logic circuitry for accessing the look-up table. In this way, instead of three LUTs and a single access, there is only one look-up table that is accessed three times, adding 120° to the initial value of the input value at each access, as indicated in the basic scheme of  FIG. 9 . 
   Such an approach does not reduce hardware resources, but significantly reduces the computational load of the sinusoidal control algorithm. 
   LUT Optimized for Hardware Implementation 
   As an alternative to the technique for accessing the single LUT illustrated in  FIG. 9 , it is possible to apply a further reduction of data to be stored in an SVM system, at the cost of making the input logic circuitry more complex. 
   As illustrated in  FIG. 10 , the waveform to be recorded in the single LUT is symmetrical. The storage requirements may be reduced by storing only the values relative to the sectors  0  and  1 , thus obtaining the graph of the waveform for the other sectors by reflection or reversal. For example, the graph in sector  3  may be obtained by reflection of the graph in sector  0 , the graph in sector  2  is a replica of that in sector  1 , and the graph in sectors  4  and  5  is obtained by reversing the graph in sectors  1  and  2 . 
   Instead of a LUT that stores values of the duty-cycle relative to the whole SVM period, the circuit of this invention, according to a different embodiment ( FIG. 13 ), may include two smaller LUTs both storing values in the range [0°, 60°], that are accessed to read in the right order the stored data for reconstructing the output waveform of  FIG. 10 . 
   As stated before, the access logic circuitry to the two LUTs is more complicated because, given an input value γ, it is necessary to determine the sector to which the angle γ belongs. Moreover, it is to be re-scaled in a range [0°, 60°] for obtaining the value for accessing the two tables. The circuit comprises a logic circuitry for reversing and reflecting the outputs of the two LUTs, and a circuit block that assembles the graphs in the different sectors for obtaining the three waveforms of  FIG. 8 . 
   Being q 0  and q 1  are the outputs of the LUTs corresponding to sectors  0  and  1  of  FIG. 10 , the duty-cycles t′ 1 , t′ 2 , t′ 3 , are determined for the different sectors by the portions of graph indicated in Table 3. 
   
     
       
             
             
             
             
           
         
             
               TABLE 3 
             
             
                 
             
             
               Sector 
               t 1 * 
               t 2 * 
               t 3 * 
             
             
                 
             
           
           
             
               0 
               q1 
               q0 
               q1 reversed 
             
             
               1 
               q0 reflected 
               q1 
               q1 reversed 
             
             
               2 
               q1 reversed 
               q1 
               q0 
             
             
               3 
               q1 reversed 
               q0 reflected 
               q1 
             
             
               4 
               q0 
               q1 reversed 
               q1 
             
             
               5 
               q1 
               q1 reversed 
               q0 reflected 
             
             
                 
             
           
        
       
     
   
   In terms of a function of a certain input angle γ, the block of  FIG. 11  generates the three values that, once processed, determine the duty-cycles of the high-side of the inverter, according to the graphs depicted in  FIG. 8 . 
   Identification of the Sector 
   If the angular position is represented by unsigned integer numbers in the range [0, 768] corresponding to [0°, 360°], each sector corresponds to the range [0, 127]. It is particularly convenient to represent each angle γ in the interval [0, 768], that is with an unsigned string of ten bits, because with this expedient, a good resolution is attained and it is much easier to identify in which of the six angular sectors of 60° the angle of the phasor that represents the triplet of voltages to be applied is comprised. Considering the unsigned binary representation of the angle γ, depicted in Table 4, for any value of γ, the three most significant bits correspond exactly to the binary coding of the number of the sector to which the angle γ belongs, while the other seven bits correspond to the same angle scaled in a range [0°, 60°]. 
   
     
       
             
             
             
           
             
             
             
           
         
             
               TABLE 4 
             
             
                 
             
             
               Angle γ 
               Decimal 
               Binary 
             
             
               (degrees) 
               representation 
               representation 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               0 
               0 
               0000000000 
             
             
               60 
               128 
               0010000000 
             
             
               120 
               256 
               0100000000 
             
             
               180 
               384 
               0110000000 
             
             
               240 
               512 
               1000000000 
             
             
               300 
               640 
               1010000000 
             
             
                 
             
           
        
       
     
   
   Supposing that γ be equal to (448) 10  in decimal representation, it corresponds to 210° electrical degrees, thus, as depicted in  FIG. 12 , it is comprised in sector  3 . 
   By scaling the angle γ in sector  3 , it is 210°−180°=30°. 
   
     
       
             
             
             
             
             
           
         
             
                 
             
             
                 
                 
                 
               Rescaled 
               Relative 
             
             
               Position 
               Representation 
               Sector 
               angle 
               position 
             
             
                 
             
           
           
             
               210° 
               (448) 10  = 
               (011) 2  = 
               (1000000) 2  = 
               30° 
             
             
                 
               (0111000000) 2   
               (3) 10    
               (64) 10   
             
             
                 
             
           
        
       
     
   
   Representing the angle γ with an integer number comprised in the range [0, 768], the logic for recognizing the sector and the rescaled angle γ−γ k , implies an extremely small computational burden and relatively simple hardware resources. 
   Compression and Reconstruction 
   The outputs q 0  and q 1  of the two look-up tables relative to sectors  0  and  1  are represented with ten bits in a range t i ε[0,1023]. Thus, the stored values in the LUTs are those represented in  FIG. 12 . 
   The unsigned representation with ten bits of the waveforms q 0  and q 1  allows reversal of the waveforms with a minimum requisite of hardware resources. Having stored the curve in sector  1 , the desired waveform in sectors  4  and  5  is obtained by negating the output bits of the look-up table q 1 , as shown in Table 5: 
   
     
       
             
             
             
             
             
           
         
             
                 
               TABLE 5 
             
             
                 
                 
             
             
                 
               Decimal 
                 
               Decimal 
                 
             
             
                 
               value 
               Binary 
               value 
               Binary 
             
             
                 
               sector 1 
               representation 
               sector 4 
               representation 
             
             
                 
                 
             
           
           
             
                 
               68 
               0001000100 
               955 
               1110111011 
             
             
                 
               66 
               0001000010 
               957 
               1110110101 
             
             
                 
               64 
               0001000000 
               959 
               1110111111 
             
             
                 
               62 
               0000111110 
               961 
               1111000001 
             
             
                 
               60 
               0000111100 
               963 
               1111000011 
             
             
                 
                 
             
           
        
       
     
   
   A circuit diagram capable of executing this operation is illustrated in  FIG. 13 . By storing only the portions of curve in the sectors  0  and  1 , it is possible to obtain, with few simple operations, the waveforms in the other sectors. 
   A technique for reflecting the portion of the waveform q 0  stored in the LUT relative to sector  0  is presented hereinafter. This operation is necessary when, for example, given the waveform in sector  0 , it is necessary to obtain the waveform in sector  3 . 
   Looking at  FIG. 8 , it may be noted that, given the data stored in the LUT, q 0 , the output of the LUT itself must be delivered if the identification number of the sector is even, otherwise a reflected replica thereof must be output in the opposite case. 
   A circuit for implementing this operation is illustrated in  FIG. 14 . 
   If the number of the sector is even, then the LUT is accessed directly with the re-scaled angle. If the sector is odd, the LUT is accessed with the complement to 60° of the input angle. According to the representation used so far, this is obtained by subtracting the value 127 from the input integer number that represents the current angular position. 
     FIG. 15  depicts, from a graphical point of view, how a reflected replica of the waveform q 0  is obtained. With the illustrated example of implementation, each time the identification number of the sector associated to a certain input angle is odd, a reflection is performed not only on the waveform of the sector  0 , of  FIG. 10 , but also on the waveforms of the sectors  1  and  4 . 
   Moreover the latter waveforms are invariant by reflection. Thus, any additional control may not be necessary, and this contributes to the reduction of hardware resources required for realizing the SVM driving circuit. 
   Rescaling 
   The waveform of  FIG. 12  does not allow optimal control of the inverter because the triangular modulating signal oscillates between 0 and 0.5. In order to better understand this problem, the graph is scaled to a unitary value, the period of the PWM signals is considered equal to an arbitrary unit ( FIG. 16 ). 
   The threshold values to be compared with the triangular modulation signal, for generating the switching pattern to be applied to the high-side switches of the inverter, are obtained by multiplying the values assumed by the waveforms for a certain value such to control the motor in the desired manner (this algorithm relates to control techniques and is not part of this invention). With the configuration of  FIG. 16 , such a value ranges within [0, 0.5] because the triangular modulating signal varies between 0 and 0.5. Referring to the example of  FIG. 17   a , since the maximum value reached by the modulating signal is 0.5, if the output of the control was such that, when multiplied by the SVM, a value larger than 0.5 is obtained, and there would be no modulation at all. This is the so-called “overmodulation condition”. 
   The fact that the SVM of  FIG. 16  is not optimized may be better understood by considering the case in which the product between the output of the PI and of the SVM block is 0.1. In this case, as evident from  FIGS. 17   b  and  17   c , the high-side switches and the low-side switches are driven in a strongly asymmetrical manner, with the high-side switches turned on for 90% of the period and the low-side switches turned on for only 10% of the period. 
   This condition should be avoided because it overheats one switch of the inverter, with a consequent modification of the transfer characteristics and an asymmetric functioning of the inverter itself. Another problem, due to the fact that the high-side switches heat up more than the low-side ones, is that it is necessary to have a heat sink larger than would be sufficient should the switches of the inverter function symmetrically, because the heat sink must be dimensioned for the switches that heat up the most. 
   For solving this problem, it is convenient to shift down the waveform in  FIG. 12  to make it symmetrical about the zero, as depicted in  FIG. 18 . This is done by a dedicated logic circuit ( FIG. 19 ). The outputs of the SVM block are processed again as shown in  FIG. 19  for calculating the effective values t 1   e , t 2   e , and t 3   e  of the duty cycles of the high-side of the inverter. After having multiplied by the output value  OUT PI of the standard proportional-integral controller that determines the proportional-integral control action of the motor, the obtained values are divided by 512 to have values comprised between [−1, 1]. Then, a value equal to 0.25 times the PWM period is added. 
   The reason for dividing by the maximum of the adopted representation for the SVM after having multiplied by the output of the controller, is that the characteristic waveform of the SVM should be represented in the range [−1, 1]. However, in a binary representation, for not losing precision, it is preferable to associate the value −1 to the number 512 and the value +1 to the number 511. This is why it is advantageous to carry out the rescaling operation only after the multiplication, when all the decimal ciphers have been used for correctly calculating the result. 
   Supposing once again, normalizing all to a unitary value, considering the period of the PWM equal to 1 arbitrary unit, having the controller output  OUT PI equal to 0.1, by properly resealing the graph of  FIG. 18 , and eventually after having summed an offset value of 0.25 times the PWM period, the graph of  FIG. 20  is obtained. 
   Even if the same functioning conditions in which the pattern of  FIG. 17  has been obtained occur, by carrying out a resealing operation, a new driving configuration, depicted in  FIG. 21 , is obtained. It is evident that the high-side and the low-side of the inverter are used symmetrically. 
   It must be noticed that, through similar observations, it may be inferred that the overmodulation condition is avoided if the output of the controller is at most equal to ±0.25 times the PWM period. As shown in  FIG. 22 , in this case, the limit is reached because the peak of the curve is equal to the maximum value assumed by the carrier. 
   Further Compression Technique 
   By analyzing  FIG. 12  more carefully, it has been noticed that it is possible to further reduce the information to be stored. 
   There is a further symmetry that would allow storage of the values assumed by the curve only in two ranges of 30° each, instead of two ranges of 60°, thus halving, for the same resolution, the number of values to be stored. To achieve this, it is advantageous to modify the way with which the system manages the inputs and the outputs of the LUTs. 
   Instead of the circuit of  FIG. 13 , that contemplates a direct access to LUTs that store waveforms of [0°, 60°] sectors, according to the preferred embodiment of this invention, the circuit of  FIG. 23  is used. 
   In this circuit, the LUTs store the waveforms of just [0°, 30°] sectors and the input is modified before accessing the tables. If the angle γ, in the adopted representation, is smaller than or equal to the integer value 63, then the table is directly accessed, otherwise the input value is complemented to 127, and this value is used for accessing the table. 
   For the outputs q 1  and q 2  no post-processing of data is necessary. By contrast, for the output q 3  it is to discriminate between the case in which a direct access to the table has been made, and the case in which the input angle is larger than 30°. In the second case, for the representation that is being used in these examples, it is necessary to output the value 1016−q 3 . 
   The obtained results are compared in  FIG. 24  with those of the circuit of  FIG. 13 . The desired waveforms are tracked with good precision and the slight mismatch is tolerable and largely compensated by the reduction of required memory resources. 
   Hardware Implementation of the SVM 
   A VHDL embodiment of the hardware that implements the Space Vector Modulation is very similar to the Simulink embodiment illustrated hereinbefore, because it is substantially combinatory logic. In the RTL description of the hardware architecture, it is possible to notice how, with a single component, all three waveforms are realized, using their symmetries and analogies. 
   According to what has been stated hereinbefore, three waveforms with a representation comprised in the interval [0, 1023] are generated. Only in a second step a translation of the mean value for optimizing the power dissipation on the MOS of the inverter is executed. 
   Two LUTs and logic circuitry for modifying the input and output signals are used for realizing the three waveforms of  FIG. 25 . In the upstream block of  FIG. 26 , the input signal is conditioned for application of the compression algorithm by isolating the value of the sector to which the angle belongs, and by calculating the re-scaled replica in the range [0°, 60°]. The three output values from the LUTs are properly addressed on the three outputs of the block. Detailed Simulink representations of the circuit according to the preferred embodiment are depicted in  FIGS. 27 ,  28 , and  29 . 
   Of the 10 bits of the input angle, the three most significant bits (MSB) represent the sector, for which the effective angle with which the LUT is accessed. The effective angle varies in range [0, 127], and may be represented with 7 bits. There is a 7 bit input and three outputs with 10 bits. Thus 384 points are to be stored. As already noticed, the total number of points to be stored may be reduced to 256, because the output of the first LUT may be obtained by inverting each bit of the output of the second LUT. 
   The hardware stores 128 samples at 20 bits, and from these samples it generates the outputs (256 samples at 10 bits) by discriminating the 10 most significant bits (MSB) and the 10 least significant bits (LSB) of the stored data. The ROM has the following characteristics: 
   
     
       
             
             
             
           
         
             
                 
                 
             
           
           
             
                 
               Instance Size 
               128 
             
             
                 
               Instance Type 
               ROM 
             
             
                 
               Instance Width 
               20 
             
             
                 
                 
             
           
        
       
     
   
   The total dimension of the ROM, and thus the required storage capacity of the memory, is 
   
     
       
         
           
             
               Size 
               · 
               Width 
             
             8 
           
           = 
           
             
               
                 128 
                 · 
                 20 
               
               8 
             
             = 
             
               320 
               ⁢ 
               
                   
               
               ⁢ 
               
                 bytes 
                 . 
               
             
           
         
       
     
   
   After having generated the output signals from the LUTs, it is necessary to again assemble the various graphs according to the sequence in Table 6. 
   
     
       
             
             
             
             
           
         
             
               TABLE 6 
             
             
                 
             
             
               Sector 
               t 1 * 
               t 2 * 
               t 3 * 
             
             
                 
             
           
           
             
               0 
               q1 
               q0 
               q1 reversed 
             
             
               1 
               q0 reflected 
               q1 
               q1 reversed 
             
             
               2 
               q1 reversed 
               q1 
               q0 
             
             
               3 
               q2 reversed 
               q0 reflected 
               q1 
             
             
               4 
               q0 
               q1 reversed 
               q1 
             
             
               5 
               q1 
               q1 reversed 
               q0 reflected 
             
             
                 
             
           
        
       
     
   
   The device generates the waveforms depicted in  FIG. 29  through multiplexers, the selection signals of which correspond to the number of the sector. This hardware may be realized with 1377 equivalent gates.  FIG. 30  compares the output responses of the SVM blocks realized with Simulink and with a VHDL to a step input applied in a control system that uses the disclosed SVM technique. After a transient, the outputs correspond exactly to those generated in a Simulink simulation. 
   Optimization of the VHDL Compression 
   A first technique of reduction (compression) of the data to be stored in the LUTs contemplates direct access to the LUTs that store waveforms of two whole sectors. By reducing the number of values to be stored in the LUTs, as illustrated in the preferred embodiment of this invention, the ROM memory space of the hardware is halved, but the combinatory logic circuitry for managing the ROM is more complex. The trade-off is between a larger ROM on a more complex logic address circuit for accessing the memory. 
   In this second case, the used ROM has the following characteristics: 
                                               Instance   64           Size           Instance   ROM           Type           Instance   20           Width                        
The total storage capacity of the ROM is
 
   
     
       
         
           
             
               Size 
               · 
               Width 
             
             8 
           
           = 
           
             
               
                 64 
                 · 
                 20 
               
               8 
             
             = 
             
               160 
               ⁢ 
               
                   
               
               ⁢ 
               
                 bytes 
                 . 
               
             
           
         
       
     
   
   By looking at the following table of the used FPGA resources, it may be noticed that there is a reduction of logic resources. The former approach required 93 slices and 184 LUTs with 4 inputs, and thus, a total of 1377 equivalent gates. The latter approach 80 slices and 157 LUTs with 4 inputs, and thus, a total of 1101 equivalent gates. Therefore, the second technique for reducing the data to be stored is more advantageous.  FIG. 31  compares the waveforms obtained storing the data in a whole sector, with a ROM of 320 bytes obtained by storing only the data in half a sector, with ROMs of 160 bytes. The two waveforms practically coincide. 
   
     
       
             
           
             
             
             
             
           
             
             
             
             
           
             
           
             
             
             
             
           
         
             
                 
             
             
               Device Utilization Summary 
             
           
        
         
             
               Logic Utilization 
               Used 
               Available 
               Utilization 
             
             
                 
             
           
        
         
             
               Number of four input LUTs 
               157 
               1,536 
                10% 
             
           
        
         
             
               Logic Distribution 
             
           
        
         
             
               Number of occupied Slices 
               80 
               768 
                10% 
             
             
               Number of Slices containing 
               80 
               80 
               100% 
             
             
               only related logic 
             
             
               Number of Slices containing 
               0 
               80 
                0% 
             
             
               unrelated logic 
             
             
               Total number of four input 
               157 
               1,536 
                10% 
             
             
               LUTs 
             
             
               Number of bonded IOBs 
               40 
               92 
                43% 
             
             
               Total equivalent gate count 
               1,101 
             
             
               for design 
             
             
               Additional JTAG gate count 
               1,920 
             
             
               for IOBs 
             
             
                 
             
           
        
       
     
   
   Considering the results of the tests, it is possible to state the proposed algorithm, with a reduction (compression) of data to be stored, functions correctly, and its performances are very good, notwithstanding the sensible reduction of the complexity and the required hardware resources for implementing it. The methods and architectures of this invention have also the following advantages: reduction of requirements of hardware resources; possibility of a completely digital hardware implementation of a widely used modulation technique that is regarded as very onerous for a microcontroller or DSP; and excellent control of the inverter that allows to reach optimal performance both in terms of efficiency of the inverter and dynamic behavior of the controlled multi-phase electric machine.