Abstract:
A semiconductor memory device comprises a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate. The columnar portions are isolated from one another by a plurality of trenches, and these trenches have first and second bottoms that are different in depth. The semiconductor device comprises a plurality of cell transistors which include first diffusion layer regions formed in the first bottoms, which are shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to both the first and second diffusion layer regions and extend along at least one side-surface portions of the columnar portions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-198128, filed Jun. 29, 2001, the entire contents of which are incorporated herein by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a semiconductor memory device and a method for manufacturing the same. More specifically, the present invention relates to highly-integrating technology for memory cells of a dynamic random access memory (DRAM).  
           [0004]    2. Description of the Related Art  
           [0005]    In recent years, the miniaturization and high-integration of semiconductor memory devices, especially those of DRAMs, are making remarkable progress. In accordance with this, more and more memory cells with very limited areas have been developed.  
           [0006]    In the past, DRAMs have been miniaturized and integrated, without changing the planar structure of the cell transistors of memory cells. For this reason, the cell transistors have become very hard to design. To be more specific, planar type cell transistors must suppress a short channel effect and have an improved retention characteristic, but these two requirements are hard to satisfy simultaneously when they are miniaturized. In effect, further improvement cannot be expected on this matter. Nevertheless, there is a requirement that the cell areas be reduced further.  
           [0007]    [0007]FIGS. 16A and 16B show the cell structure of a conventional DRAM. FIG. 16A is a plan view showing the cell layout of an 8F2 type, for example, and FIG. 16B is a sectional view taken along line  16 B- 16 B of FIG. 16A.  
           [0008]    As shown in these Figures, the occupation area of one memory cell is determined by planar type cell transistor  101 , one bit line contact (CB)  103  shaped by two cells, and an element isolation region  105 . In FIGS. 16A and 16B, reference numeral  107  denotes an active area (AA), numeral  109  denotes a p-type silicon substrate, numeral  111  denotes a word line, numeral  113  denotes an SiN film, numeral  115  denotes an interlayer film, numeral  117  denotes a capacitor contact (storage node contact [CN]), and numeral  119  denotes a bit line (BL). Reference numeral  121  denotes a cell capacitor including a storage electrode (SN)  121   a , a capacitor dielectric film  121   b  and a plate electrode (PL)  121   c.    
           [0009]    Let us assume that a minimum working dimension is F and that a gate electrode (word line (WL))  101   a  and a diffusion layer  101   b  (which is to function as a source or drain) have sides that are designed based on F. In this case, the minimum occupation area of a memory cell is 8F 2  (the length is 2F, and the width is 4F). As can be seen from this, the miniaturization and integration of a DRAM wherein each memory cell includes one transistor and one capacitor have made progress based on the 8F 2  type cell layout.  
           [0010]    In the planar type cell transistor  101 , however, the gate length decreases in accordance with a decrease in the cell area, and the short channel effect is hard therefore to suppress. To effectively suppress the short channel effect, a leak between depletion layers  101   b  should be reduced, and this is attained by increasing the boron concentration of a channel section (in the case where a substrate  109  is a p-type). On the other hands, it is required that the retention characteristic be further improved since the retention characteristic plays an important role in determining the performance of a DRAM. To improve the retention characteristic, the junction leak at the capacitor side, which adversely affects the retention characteristic, must be reduced. This is attained by decreasing the boron concentration of the channel section in the neighborhood of the capacitor-side junction (in the case where the substrate is a p-type).  
           [0011]    As described above, in the DRAM, one requirement is attained by increasing the impurity concentration in the channel section of a cell, and another requirement is attained by decreasing the same impurity concentration. In other words, these requirements are in trade-off relationships in terms of the impurity concentration of the channel section. Moreover, the recent severe cost competition requires that the cell area be further reduced and the chips (DRAM) be further miniaturized and integrated. However, in the 8F2 type cell layout shown in FIG. 16A, the cell area is already that of the theoretical limitation (i.e., the cell area is none other than 8F 2 ). Under the circumstances, the required reduction in the cell areas cannot be attained, and the further miniaturization and integration of chips cannot be met.  
           [0012]    As described above, further reduction in the size of cell areas and further miniaturization and integration of chips are required in the conventional art. These requirements, however, cannot be met since the suppression of the short channel effect of a cell transistor and the improvement of the retention characteristic are hard to satisfy simultaneously in the case of the 8F 2  type cell layout.  
         BRIEF SUMMARY OF THE INVENTION  
         [0013]    A semiconductor memory device according to an embodiment of the present invention comprises: a plurality of columnar portions formed in memory cell array regions on a semiconductor substrate, the columnar portions being isolated by a plurality of trenches having first and second bottoms which are different in depth; a plurality of cell transistors including first diffusion layer regions formed in the first bottoms shallower than the second bottoms, second diffusion layer regions formed in surface portions of the columnar portions, and a plurality of gate electrodes which are adjacent to the first and second diffusion layer regions and extending along one side surface of each columnar portion; a plurality of word lines connected to the gate electrodes, respectively; a plurality of bit lines extending in a direction intersecting with the word lines and connected to the first diffusion layer regions, respectively; and a plurality of cell capacitors connected to the second diffusion layer regions, respectively.  
           [0014]    A semiconductor memory device-manufacturing method according to an embodiment of the present invention comprises: providing a plurality of columnar portions by forming a plurality of first trenches of a first depth in memory cell array regions of a semiconductor substrate; forming a plurality of first diffusion layer regions by forming first impurity layers in bottoms of the first trenches; filling the first trenches with a gate electrode material; selectively removing the gate electrode material from the first trenches by forming a plurality of second trenches of a second depth deeper than the first depth, such that a plurality of gate electrodes extend at least along one-side portions of the columnar portions; forming a plurality of element isolation regions by filling the second trenches with an insulating film; forming a plurality of word lines which are connected to the gate electrodes; forming a plurality of second diffusion layer regions by forming second impurity layers in surface portions of the columnar portions; forming a plurality of bit line contacts which are connected to the first diffusion layer regions; forming a plurality of bit lines which are connected to the bit line contacts; forming a plurality of capacitor contacts which are connected to the second diffusion layer regions; and forming a plurality of cell capacitors which are connected to the capacitor contacts. 
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0015]    [0015]FIG. 1 is a plan view showing the cell layout of a DRAM according to the first embodiment of the present invention.  
         [0016]    [0016]FIG. 2A is a sectional view showing how the cell structure of the DRAM is in the section taken along line  2 A- 2 A of FIG. 1, and FIG. 2B is a sectional view showing how the cell structure of the DRAM is in the section taken along line  2 B- 2 B of FIG. 1.  
         [0017]    [0017]FIGS. 3A to  3 C are sectional views which illustrate the method for manufacturing the DRAM shown in FIG. 1.  
         [0018]    [0018]FIGS. 4A to  4 C are sectional views which illustrate the method for manufacturing the DRAM shown in FIG. 1.  
         [0019]    [0019]FIGS. 5A to  5 C are sectional views which illustrate the method for manufacturing the DRAM shown in FIG. 1.  
         [0020]    [0020]FIGS. 6A to  6 C are sectional views which illustrate the method for manufacturing the DRAM shown in FIG. 1.  
         [0021]    [0021]FIGS. 7A to  7 C are sectional views which illustrate the method for manufacturing the DRAM shown in FIG. 1.  
         [0022]    [0022]FIG. 8 is a plan view showing the cell layout of a DRAM according to the second embodiment of the present invention.  
         [0023]    [0023]FIG. 9A is a sectional view showing how the cell structure of the DRAM is in the section taken along line  9 A- 9 A of FIG. 8, and FIG. 9B is a sectional view showing how the cell structure of the DRAM is in the section taken along line  9 B- 9 B of FIG. 8.  
         [0024]    [0024]FIG. 10 is a plan view showing the cell layout of a DRAM according to the third embodiment of the present invention.  
         [0025]    [0025]FIG. 11A is a sectional view showing how the cell structure of the DRAM is in the section taken along line  11 A- 11 A of FIG. 10, and FIG. 11B is a sectional view showing how the cell structure of the DRAM is in the section taken along line  11 B- 11 B of FIG. 10.  
         [0026]    [0026]FIG. 12 is a schematic diagram illustrating a multi-layered bit line system.  
         [0027]    [0027]FIG. 13 is a sectional view showing the cell structure of a DRAM according to the fourth embodiment of the present invention.  
         [0028]    [0028]FIG. 14 is a plan view showing the cell layout of a DRAM according to the fifth embodiment of the present invention.  
         [0029]    [0029]FIG. 15A is a sectional view showing how the cell structure of the DRAM is in the section taken along line  15 A- 15 A of FIG. 14, and FIG. 15B is a sectional view showing how the cell structure of the DRAM is in the section taken along line  15 B- 15 B of FIG. 14.  
         [0030]    [0030]FIG. 16A is a plan view showing a DRAM and illustrating the prior art and the related problems, and FIG. 16B is a sectional view taken along line  16 B- 16 B of FIG. 16A. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0031]    Embodiments of the present invention will now be described with reference to the accompanying drawings.  
         [0032]    (First Embodiment)  
         [0033]    [0033]FIG. 1 and FIGS. 2A and 2B show the cell structure of a DRAM according to the first embodiment of the present invention. FIG. 1 is a plan view showing the cell layout, and FIGS. 2A and 2B are sectional views taken along lines  2 A- 2 A and  2 B- 2 B of FIG. 1, respectively.  
         [0034]    As shown in FIGS. 2A and 2B, a plurality of trenches  12  are formed in the surface portion of a p-type silicon substrate (semiconductor substrate). The trenches  12  are provided in correspondence to respective memory cell array regions. Each trench includes a first trench  12   a  (which is a shallow trench) and a second trench  12   b  (which is a trench deeper than the first trench  12   a ). Silicon columns  13  are formed between the adjacent ones of the trenches  12 . As shown in FIG. 1, the silicon columns are laid out in a matrix pattern at intervals corresponding to the minimum design rule.  
         [0035]    As shown in FIG. 1, the first trenches  12   a  (shallow trenches) are shifted by half a pitch in each direction of the matrix pattern. As shown in FIGS. 2A and 2B, first and second diffusion regions  15   1  and  15   2  (which are n-type impurity layers) are formed separately from each other. The first diffusion regions  15   1  are located at silicon pedestals  14 , which correspond to the bottom portions of the shallow first trenches  12   a , and the second diffusion regions  15   2  are located in the surface portions of the silicon columns  13 . The diffusion regions  15   1  and  15   2  serve as sources and drains of cell transistors.  
         [0036]    A vertical type of gate electrode  16  is formed in each of the first trenches  12   a . As shown, for example, in FIG. 2A, the gate electrode  16  extends along one side surface  13   a  of the corresponding silicon column  13 , and a gate insulating film  17  is located between the gate electrode and the side surface  13   a . The gate electrode  16  is rectangular and looks like having a substantially “I”-shaped surface when viewed from above, as can be seen from FIG. 1. In conjunction with the diffusion regions  15   1  and  152  described above, the gate electrode  16  forms a vertical cell transistor, wherein the side surface  13   a  functions as a channel section. The gate electrode  16  is connected to a corresponding word line (WL)  18 .  
         [0037]    As shown in FIG. 2B, bit line contacts (CB)  19  are connected at one end to either diffusion layer regions  15   1  or  15   2 . They are connected to diffusion layer regions  15   1 , for example. At the other end, the bit line contacts  19  are connected to corresponding bit lines (BL)  20 . These bit lines  20  are arranged to be substantially orthogonal to the word lines  18 . The word lines  18  and the bit lines  20  have their upper surfaces covered with silicon nitride films  21  and have their side surfaces covered with silicon nitride films  22 . A silicon oxide (SiO 2 ) film  23  is formed in each trench  12 , thereby providing element isolation  23 ′.  
         [0038]    The diffusion layer regions  15   1  or  15   2  that are not connected to the bit line contacts  19 , for example diffusion layer regions  15   2 , are connected to one-end portions of capacitor contacts (storage node contacts CN). The capacitor contacts  24  are arranged utilizing the spaces between the word lines  18  and the bit lines  20 . The other-end portions of the capacitor contacts  24  are connected to cell capacitors  26  formed on interlayer films  25 . Each of the cell capacitors  26  includes a storage electrode (lower capacitor electrode)  26   a , a capacitor dielectric film  26   b , and a plate electrode (upper capacitor electrode PL)  26   c.    
         [0039]    In the first embodiment, memory cells are arranged at the intersections between the word lines  18  and the bit lines  20 , as shown in FIG. 1. In other words, the first embodiment provides a layout structure for cross-point type cells. Each memory cell includes a vertical cell transistor and a cell capacitor  26  (that is, a memory cell is made up of one transistor and one capacitor). Assuming that the minimum working dimension of the memory cells is F, the minimum occupation area is 4F 2  per cell (the pitch of the word lines  18  is 2F, and the pitch of the bit lines  20  is 2F).  
         [0040]    A description will now be given of a process for manufacturing the DRAM of the first embodiment, with reference to FIGS.  3 A- 3 C and FIGS.  7 A- 7 C. FIGS. 3A, 4A,  5 A,  6 A and  7 A are sectional views taken along line  2 A- 2 A of FIG. 1, FIGS. 3B, 4B,  5 B,  6 B and  7 B are sectional views taken along line  2 B- 2 B of FIG. 1, and FIGS. 3C, 4C, SC,  6 C and  7 C are sectional views showing peripheral regions (peripheral circuit regions) of array regions.  
         [0041]    As shown, for example, in FIGS. 3A and 3B, a Pad oxide film  31 , a Pad nitride film  32  and a second Pad oxide film  33  are sequentially deposited on the p-type silicon substrate  11  by CVD (Chemical Vapor Deposition) in the order mentioned. Subsequently, a resist pattern (not shown) used for forming silicon columns  13  is worked by photolithography. The second Pad oxide film  33 , the Pad nitride film  32  and the Pad oxide film  31  are sequentially worked by RIE (Reactive Ion Etching), using the resist pattern as a mask. After the resist pattern is removed, the silicon substrate  11  is etched by RIE, using the second Pad oxide film  33 , the Pad nitride film  32  and the Pad oxide film  31  as a mask. By this etching, shallow first trenches  12   a  are formed in the array regions, thereby forming the silicon columns  13  described above. Then, the side surfaces of the silicon columns  13  are oxidized, thereby forming oxide films  17   a , which serve as the gate insulating films  17 . Subsequently, the bottom portions (silicon pedestals  14 ) of the first trenches  12   a  are doped with ions by oblique ion implantation, thereby forming diffusion layer regions (first diffusion layers)  15   1 . If this ion implantation degrades the quality of the oxide films  17   a , these oxide films  17   a  are removed and new oxide films  17   a  are formed instead. Then, a polycrystalline silicon film  34  is deposited over the entire surface of the resultant structure. The polycrystalline silicon film  34  is recessed by CMP (Chemical Mechanical Polishing) in such a manner that it is left inside the shallow first trenches  12   a . At the time, the second Pad oxide film  33  is used as a stopper. Thereafter, as can be seen from the film structure shown in FIG. 3C, the second Pad oxide film  33  is selectively etched out in the peripheral regions of the array regions by photolithography and wet etch processing. As shown in FIGS. 3A to  3 C, a resist pattern (PR)  35  used for forming an active region is worked.  
         [0042]    As shown, for example, in FIG. 4C, the Pad nitride film  32  is patterned in the peripheral regions of the array regions. This patterning is executed under the SiN-RIE etching condition, using the resist pattern  35  as a mask. Subsequently, as shown in FIGS. 4A and 4B, the polycrystalline silicon film  34  is patterned in the array regions after the etching condition is changed to Poly-RIE. At the time, the resist pattern  35 , the second Pad oxide film  33  and the Pad oxide film  31  are used as a mask (critical mask). As a result, vertical-type gate electrodes  16 , whose lower portions are similar in shape to the bottom portions (silicon pedestals) of the first trenches  12   a , are formed on the bottom portions of the first trenches  12   a  (FIG. 4A). As shown in FIGS. 4B and 4C, the Pad oxide film  31  and the oxide films  17   a  are worked or removed by RIE. After the resist pattern  35  is removed, the silicon substrate  11  is etched under the Si-RIE etching condition in such a manner that second trenches  12   b  (which are deep and used for element isolation) and trenches  36  are formed, as shown in FIGS. 4A to  4 C. Then, as shown in FIGS. 1 and 4B, those portions of the gate electrodes  16  which would be adjacent to the bit line contacts  19  (i.e. portions other than the one-side surface portions  13   a ). A silicon oxide film  23  is deposited over the entire surface of the resultant structure by CVD, and is then recessed in such a manner that it is left only in the trenches  12   a ,  12   b  and  36 .  
         [0043]    As shown in FIGS. 5A to  5 C, element isolation  23 ′ is completed by removing the second Pad oxide film  33 , recessing the gate electrodes  16 , and removing the Pad nitride film  32 . What should be noted here is that element isolation  23 ′ is attained simultaneously in both the array regions and their peripheral regions and the steps required can be simplified, accordingly. As shown in FIG. 5C, an N-well region  37  and a P-well region  38  are formed in the peripheral regions of the array regions by executing ion implantation through the use of the Pad oxide film  31 . After the Pad oxide film  31  is removed, a gate insulating film  39 , which is an oxide film, is formed. Of this oxide film, those portions which are located on the gate electrodes  16  are removed by photolithography and wet etch processing. As shown in FIGS. 5A and 5C, a second polycrystalline film and a silicide film (or a metal film), which are to serve as word lines  18  in the array regions and gate electrodes (GC)  40  in the peripheral regions, are deposited by CVD. The resultant structure is overlaid with a silicon nitride film  21 , which are to serve as a cap) by CVD. Gates (word lines  18  and gate electrodes  40 ) are worked by photolithography and RIE. Subsequently, silicon nitride films  22 , serving as spacers, are deposited by CVD, and the deposited silicon nitride films  22  are worked by CVD in such a manner that their portions located on the side wall are left. Then, as shown in FIGS. 5A to  5 C, ion implantation is executed in such a manner that diffusion layer regions (second diffusion layers) are formed in the upper portions of the silicon columns  13  in the array regions, and that diffusion regions  41  and  42  serving as sources or drains of transistors are formed in the peripheral regions. In the array regions, therefore, the vertical-type gate electrodes  16  and the diffusion layer regions  15   1  and  15   2  define vertical-type cell transistors, wherein one-side portions of the silicon columns  13  function as channel sections.  
         [0044]    After an interlayer film  25   a  is formed, contact holes  19   a  for the bit line contacts  19  are formed in the array regions. The contact holes  19   a  reach the diffusion layer regions  15   1  formed in the silicon pedestals  14 , as shown in FIG. 6B. Then, in order to ensure reliable insulation between the bit line contacts  19  and the silicon columns  13  (or gate electrodes  16 ), spacers (not shown) made of silicon nitride films are formed inside the contact holes  19   a . A barrier metal film and a tungsten film are deposited over the resultant structure, and the bit contacts  19  are completed by working them by CMP. The bit line contacts  19  are formed in self-alignment with the word lines  18 . Next, a silicon nitride film  21 , which is later used as a bit line material and a cap, is deposited, for example, by CVD, and bit lines  20  are formed by working the deposited silicon nitride film  21  by photolithography and RIE. In addition, a silicon nitride film  22 , which is later used as spacers of the bit lines  20 , is deposited, for example, by CVD, and the deposited silicon nitride film  22  is worked by RIE in such a manner that it is left on the side wall portions. As shown, for example, in FIGS. 6A and 6B, an interlayer film  25   b  is deposited in the array regions, and contact holes  24   a  for the capacitor contacts  24  are formed. A barrier metal film and a tungsten film are further deposited, and the deposited films are worked by CMP, thereby completing the capacitor contacts  24 . The capacitor contacts  24  are formed in self-alignment with the word lines  18  and the bit lines  20 . Next, storage electrodes  26   a  having a cylinder structure, for example, are formed on the capacitor contacts  24 . The storage electrodes  26   a  need not be of cylinder structure; they may be of any structure including a concave structure or a pedestal structure. When the bit line contacts  19  and the bit lines  20  are formed (alternatively, before or after they are formed), contacts  43  leading to the diffusion layers  41  and  42 , wiring layers (MO)  44  leading to the contacts  43 , and caps  45  and spacers  46  for the wiring layers  44  are formed, as shown in FIG. 6C.  
         [0045]    In the array regions, a capacitor dielectric film  26   b  and a plate electrode  26   c , both for the cell capacitors  26 , are deposited and worked, as shown in FIGS. 7A and 7B. Thereafter, in the peripheral regions of the array regions, wiring layer-forming steps, such as the steps of forming wiring vias (C 1 )  47  and wiring layers (M 1 )  48 , are executed with respect to the interlayer film  25   c . In this manner, a DRAM (DRAM cell) having such a cell structure as shown in FIGS. 1, 2A and  2 B is completed.  
         [0046]    As described above, the DRAM of the above embodiment employs vertical-type cell transistors. In other words, the cell transistors are a vertical type in a layout structure for cross-point type cells. This structure enables controlling the boron concentration in the channel section and the boron concentration in the junction at the capacitor side independently of each other. Hence, the suppression of the short channel effect and the improvement of a retention characteristic are attained, and yet the cell layout can be determined based on 4F 2  type.  
         [0047]    In particular, the suppression of the short channel effect of a transistor and the improvement of the retention characteristic are attained at the same time, and the adoption of the vertical-type gate electrodes enables efficient use of the space. Hence, the cell area can be significantly reduced, and the life of the DRAM cells can be remarkably lengthened.  
         [0048]    It should be also noted that the cell capacitors can be formed using the conventionally known technology. This ensures a high degree of flatness of the bit lines, and a high manufacturing yield is attained.  
         [0049]    (Second Embodiment)  
         [0050]    [0050]FIG. 8 and FIGS. 9A and 9B show the cell structure of a DRAM according to the second embodiment of the present invention. FIG. 8 is a plan view showing the cell layout, and FIGS. 9A and 9B are sectional views taken along lines  9 A- 9 A and  9 B- 9 B of FIG. 8, respectively.  
         [0051]    As shown, for example, in FIGS. 8 and 9A and  9 B, according to the second embodiment, the vertical-type gate electrodes  16 ′ of the vertical cell transistors are formed in self-alignment with the silicon pedestals  14  (i.e., with the shallow first trenches  12   a ). In this point, the second embodiment differs greatly from the first embodiment.  
         [0052]    In the second embodiment, a polycrystalline silicon film  34  is worked by isotropic etching. This etching allows the vertical-type gate electrodes  16 ′ to be formed in self-alignment with the silicon pedestals  14 . That is, unlike the first embodiment, the second embodiment eliminates the need to employ such a mask (critical mask) as required for forming gates (FIGS. 3A to  3 C).  
         [0053]    As shown, for example, in FIG. 8, the pitch of bit lines  20  is increased from 2F to 3F (F: minimum working dimension) so as to ensure reliable insulation between bit line contacts  19  and the vertical-type gate electrodes  16 ′. The minimum occupation area is 6F 2  per cell (the pitch of word lines  18  is 2F).  
         [0054]    As shown, for example, in FIG. 8, each vertical-type gate electrode  16 ′ looks like having a substantially “L”-shaped surface when viewed from above. It extends along the adjoining side surfaces of one corner of a silicon column  13  and surrounds part of the silicon column  13 . In the section taken along line  9 B- 9 B of FIG. 8, however, the vertical-type gate electrode  16 ′ does not exist, as can be seen from FIG. 9B. This structure prevents the bit line contacts  19  from short-circuiting, and yet increases the gate width of each vertical-type cell transistor. As compared to the first embodiment, the vertical-type cell transistors of the second embodiment provide a high driving power and are therefore suitable for a high-speed operation.  
         [0055]    As described above, the second embodiment makes good use of corners of silicon columns so as to reduce the substrate bias effect of the vertical-type cell transistors. As a result, the vertical-type cell transistors are improved in the slope characteristic of sub-threshold leak and enable a high-speed operation on low voltage.  
         [0056]    To form vertical-type gate electrodes, shallow first trench  12   a  are filled with a polycrystalline silicon film  34  (see FIG. 3A), and side etching is executed by CDE (chemical dry etching), without the resist pattern  35  being removed. In this manner, the vertical-type gate electrodes  16 ′ are formed in self-alignment with the corresponding silicon pedestals  14 , as shown in FIGS. 9A and 9B. As compared to the vertical-type gate electrodes  16  of the first embodiment, the vertical-type gate electrodes  16 ′ of the second embodiment are slim. To be more specific, the gate electrodes  16 ′ of the second embodiment are reduced in terms of the thickness as measured in the section taken along line  9 A- 9 A of FIG. 8, and are smaller than the bottom portions of the first trenches  12   a . Thereafter, the Pad oxide film  31  and the oxide film  17   a  are removed by RIE. After the resist pattern  35  is removed, the silicon substrate  11  is etched under the Si-RIE etching condition. In this manner, deep second trenches  12   b  used for element isolation in the array regions and trenches  36  used for element isolation in the peripheral regions are formed. Then, a silicon oxide film  23  used for element isolation is deposited by CVD, and the deposited film is recessed by CMP, thereby providing element isolation  23 ′.  
         [0057]    By executing the subsequent steps, which are similar to those of the first embodiment, a DRAM shown in FIGS. 8, 9A and  9 B is completed.  
         [0058]    (Third Embodiment)  
         [0059]    [0059]FIG. 10 and FIGS. 11A and 11B show the cell structure of a DRAM according to the third embodiment of the present invention. FIG. 10 is a plan view showing the cell layout, and FIGS. 11A and 11B are sectional views taken along lines  11 A- 11 A and  11 B- 11 B of FIG. 10, respectively. The pitch of word lines  18  is 2F, and the pitch of bit lines  20 ′ is 1F. Hence, the minimum occupation area is 2F 2  per cell.  
         [0060]    In the case of the third embodiment, bit lines  20 ′ are linear wiring layers made of diffusion regions  15   1  formed in the bottoms of trenches  12  (in the embodiment, in the bottoms of shallow first trenches  12   a ), as shown in FIGS. 10, 11A and  11 B. In this point, the third embodiment differs greatly from the first and second embodiments. In other words, the bit lines  20  described above in relation to the first and second embodiments are diffusion layer regions  15   1  in the DRAM of the third embodiment.  
         [0061]    In the third embodiment, the contacts  19  between the bit lines  20  and the diffusion layer regions  15   1  need not be located inside cells. This being so, the silicon columns  13  and the vertical-type gate electrodes  16 ″ are prevented from short-circuiting to the bit line contacts  19 . It should be noted in particular that the position of the bit line contacts  19  is hard to control in the depth direction. If the bit line contacts  19  are at a too shallow or deep position, their contact performance may be adversely affected. Since this problem does not occur, the manufacturing yield is high, and the steps required can be simplified.  
         [0062]    In the third embodiment, each vertical-type gate electrode  16 ″ may be shaped substantially in the form of “L”, as in the second embodiment. Where each gate electrode  16 ″ is shaped in this manner, it extends along the adjoining side surfaces of one corner of a silicon column  13  and surrounds part of that silicon column  13 . This structure increases the gate width of each vertical-type cell transistor. As compared to the first embodiment, the vertical-type cell transistors of the third embodiment provide a high driving power and are therefore suitable for a high-speed operation. The third embodiment makes good use of corners of silicon columns  13  so as to reduce the substrate bias effect of the vertical-type cell transistors. As a result, the vertical-type cell transistors are improved in the slope characteristic of sub-threshold leak and enable a high-speed operation on low voltage.  
         [0063]    A description will be given as to how the bit lines  20 ′ are manufactured. First of all, the side surfaces of the silicon columns  13  are oxidized, so as to form oxide layers  17   a  functioning as gate insulating films  17  (see FIG. 3A). Subsequently, diffusion layer regions (first impurity layers)  15   1  are formed by vertical ion implantation (in place of oblique ion implantation). As a result, bit lines  20 ′, which serve as diffusion layer regions  15   1  as well, are formed in the bottom regions (silicon pedestals  14 ) of the shallow first trenches  12   a.    
         [0064]    In the above embodiments, those portions of the gate electrodes  16  which would be adjacent to the bit line contacts  19  (i.e. portions other than the one-side surface portion  13   a  of the silicon column  13 ) are removed by photolithography and Poly-RIE etching, as shown in FIG. 4B. This step is omitted in the case of the third embodiment. However, bit line contacts connected to sense amplifiers are formed in the peripheral regions of the array regions, by executing a step similar to that of the first embodiment (see FIG. 6B).  
         [0065]    By executing the subsequent steps, which are substantially similar to those of the first embodiment, a DRAM shown in FIGS. 10, 11A and  11 B is completed.  
         [0066]    Where a layout structure for cross-point type cells is adopted, the noise immunity may be adversely affected, lowering the margin of a sensing operation. A number of methods are available to prevent this problem (i.e., there are some measures that can be taken to reduce noise). By adopting such methods in combination with the present invention, a reliable operation is ensured.  
         [0067]    (Fourth Embodiment)  
         [0068]    [0068]FIG. 12 is a schematic diagram illustrating a multi-layered bit line system, which is an example of a noise-reducing measure. In the embodiment shown in FIG. 12, two wiring layers (e.g., bit lines BL and /BL) are twisted at a number of positions.  
         [0069]    As shown in FIG. 12, double-layered bit lines BL and /BL are formed, and they are twisted at one or more positions. This structure is effective in canceling noise.  
         [0070]    Since the DRAM of the fourth embodiment adopts the noise-reducing measure described above, a very stable operation is ensured.  
         [0071]    [0071]FIG. 13 shows a cell structure of the DRAM according to the fourth embodiment. FIG. 13 is a schematic cross sectional view of a DRAM and illustrates the case where the multi-layered bit line system shown in FIG. 12 is applied.  
         [0072]    As shown in FIG. 13, double-layered bit lines are formed in a section that expands along bit lines. To be more specific, the double-layered bit lines are made up of a wiring layer  20   a  formed of tungsten and a wiring layer  20   b  made of a diffusion layer region  15   1 . In practice, the wiring layers  20   a  and  20   b  have cross sections that are different in shape. The double-layered bit lines, namely the wiring patterns  20   a  and  20   b , are twisted effectively because of the provision of the bit line contacts  19 .  
         [0073]    The double-layered bit line system described above is only one example of a noise-reducing measure. Other noise-reducing measures are also known, such as a one-layer bit line system and a method wherein adjacent bit lines are shielded. These noise-reducing measures are also applicable to the DRAMs of the embodiments of the present invention without any problems.  
         [0074]    (Fifth Embodiment)  
         [0075]    [0075]FIGS. 14, 15A and  15 B show a cell structure of a DRAM according to the fifth embodiment of the present invention. FIG. 14 is a plan view showing a cell layout, and FIGS. 15A and 15B are sectional views taken along line  15 A- 15 A and line  15 B- 15 B of FIG. 14, respectively.  
         [0076]    In the first to third embodiments described above, the minimum working dimension is set at F, and the pitch of the word lines  18  is set at 2F. In this structure, however, the coupling due to potential fluctuations from an adjacent word line  18  may give rise to leakage or damage to storage data in an unselected cell.  
         [0077]    In the DRAM shown in FIGS. 14, 15A and  15 B, the pitch of the bit lines is increased from 2F to 3F, so as to prevent damage to the storage data. In the fifth embodiment, the minimum occupation area is 6F 2  per cell (the pitch of word lines  18  is 2F).  
         [0078]    As shown in FIGS. 14 and 15A, each silicon column  13  and the word lines corresponding to it are located close to each other. However, the word lines  18  corresponding to a given silicon column  13  are away from the adjacent silicon columns  13  by space X, which is nearly equal to minimum working dimension F. With this structure, the word lines  18  corresponding to the given silicon column  13  do not have any adverse effects on the vertical cell transistors formed by use of the adjacent cells. To be more specific, the vertical-type cell transistors are not undesirably turned on. Hence, the coupling due to potential fluctuations from an adjacent word line  18  does not give rise to damage to storage data in an unselected cell.  
         [0079]    In the case of the fifth embodiment, the intervals between the bit line contacts  19  and the vertical-type gate electrodes  16  can be increased. Where the intervals are increased, short-circuiting can be suppressed, and a high manufacturing yield is ensured.  
         [0080]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.