Abstract:
A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2010-0115679, filed on Nov. 19, 2010, which are incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a method for forming fine pattern of a semiconductor device by using spacer patterning technology. 
         [0004]    2. Description of the Related Art 
         [0005]    As the integration degree of semiconductor memory devices increases, the size of semiconductor devices becomes smaller and smaller. Accordingly, the sizes of the circuit patterns of the circuits that constitute a semiconductor device are reduced and are reaching physical limits in terms of exposure processes for forming a mask for transferring a pattern onto a semiconductor substrate or wafer. 
         [0006]    However, since upgrading a mask to overcome the limitations in optical definition increases equipment prices and production costs, methods that form fine pattern while addressing the above-discussed features in a conventional mask process are useful. 
         [0007]    An example of such a method is Spacer Patterning Technology (SPT) where spacers are formed over a semiconductor substrate and a patterning process is performed on a layer by using the spacers as a mask. Since pattern is formed to have a line width determined depending on the thickness of the spacers according to the spacer patterning technology, the limitation in optical definition is overcome using exposure equipment of argon fluoride (ArF) or krypton fluoride (KrF) and fine pattern, for example, patterns as fine as approximately 30 nm or less may be realized on a substrate. 
         [0008]    Here, the spacer patterning technology uses an additional mask process while not requiring an upgraded mask. 
         [0009]    In other words, since the spacers are typically formed on the sidewalls of pattern, a line-type partition, which is a sacrificial layer pattern for forming the spacers, is formed and also, since the spacers is formed with a rim shape on the sidewalls of the partition, the spacers are selectively removed and cut for isolation of the pattern, and the pattern is formed to have different line widths in a cell region and a peripheral circuit region. As such, a total of three masks are used: one mask for forming the partition, another mask for cutting the spacers, and the other mask for forming pattern in the peripheral region. 
         [0010]    When the mask for cutting the spacers and the mask for forming the pattern in the peripheral region are used separately, an etch equipment is additionally used other than mask equipment. Moreover, a hard mask has a higher etch selectivity than a pattern target layer. More specifically, the hard mask has a stacked structure to realize fine pattern of a desired line width. For example, when the fine pattern forms trenches for device isolation, the hard mask for forming the fine pattern of a desired line width has a stacked structure where a first amorphous carbon layer (ACL)  210  of approximately 1500 Å, a first silicon oxynitride (SION) layer  220  of approximately 300 Å, a polysilicon layer  230  of approximately 400 Å, a second amorphous carbon layer (ACL)  240  of approximately 1500 Å, a second silicon oxynitride (SiON) layer  250  of approximately 300 Å, and a bottom anti-reflection coating (BARC) layer  260  are sequentially stacked over a semiconductor substrate  200 . Subsequently, a partition-forming photoresist pattern  270  for forming spacers is formed as illustrated in  FIG. 1 . 
         [0011]    Here, although the first amorphous carbon layer  210  and the second amorphous carbon layer  240  are each have a higher etch selectivity than the pattern target layer, they can be costly to manufacture. Therefore, when two or more amorphous layers are formed, production costs increase. 
       SUMMARY 
       [0012]    An embodiment of the present invention is directed to a method that may minimize/reduce the number of masks needed when spacer patterning technology is applied to form fine pattern of a semiconductor device using the spacer patterning technology, minimize the use of an expensive hard mask layer, simplify the fabrication process, and reduce production costs. 
         [0013]    In accordance with an embodiment of the present invention, a method for forming fine pattern of a semiconductor device includes: sequentially forming a first thin film and a second thin film over a target layer for patterning; forming a partition over the second thin film; removing the partition after forming spacers on sidewalls of the partition; forming a first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers simultaneously; forming a second pattern of the second thin film having a finer line width than the first pattern by using the spacers as a mask and etching the first pattern of the second thin film in the first region; forming a first thin film pattern by using the first pattern and the second pattern of the second thin film as masks in the first and second regions and etching the first thin film; and etching the pattern target layer by using the first pattern and the second pattern of the second thin film as masks. 
         [0014]    The first region may be a cell region, and the second region may be a memory peripheral circuit region. 
         [0015]    The pattern target layer may be a semiconductor substrate, and trenches for device isolation may be formed by etching the pattern target layer. 
         [0016]    The first thin film may include an oxide layer, and the second thin film may include a polysilicon layer. 
         [0017]    The oxide layer may be formed to have a thickness of approximately 3500 Å or less. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a cross-sectional view illustrating a stacked structure that is used to form fine pattern of a semiconductor device according to conventional spacer patterning technology. 
           [0019]      FIGS. 2A to 2L  are cross-sectional views illustrating a method for forming fine pattern of a semiconductor device in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0021]    The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate. 
         [0022]      FIGS. 2A to 2L  are cross-sectional views illustrating a method for forming fine pattern of a semiconductor device in accordance with an embodiment of the present invention. In the present invention, a case where trenches for device isolation are formed as fine pattern is taken as an example and described. 
         [0023]    Referring to  FIG. 2A , a pad oxide layer  310 , a pad nitride layer  320 , an oxide layer  330 , a polysilicon layer  340 , an amorphous carbon layer (ACL)  350 , a silicon oxynitride (SiON) layer  360 , and a bottom anti-reflection coating (BARC) layer  370  are sequentially formed over a semiconductor substrate  300 . The semiconductor substrate  300  includes a cell region CELL where fine trenches are to be formed and a peripheral region PERI where large trenches are to be formed. 
         [0024]    Here, the thickness of the stacked layers may be set appropriately by taking into consideration the etch selectivity of an upper layer with respect to a lower layer. For example, the pad oxide layer  310  may be formed with a thickness of approximately 530 Å, and the pad nitride layer  320  may be formed with a thickness of approximately 600 Å: 
         [0025]    Also, the oxide layer  330  may be formed with a thickness of approximately 3500 Å or less. According to an embodiment, the oxide layer  330  may be formed with a thickness ranging from approximately 1500 Å to approximately 3500 Å. The polysilicon layer  340  may be formed with a thickness of approximately 3500 Å or less. According to an embodiment, the polysilicon layer  340  may be formed with a thickness ranging from approximately 800 Å to approximately 3500 Å. The amorphous carbon layer  350  may be formed with a thickness of approximately 3500 Å or less at a temperature of approximately 350° C. to 700° C. According to an embodiment, the amorphous carbon layer  350  may be formed with a thickness ranging from approximately 1500 Å to approximately 3500 Å. 
         [0026]    Also, the silicon oxynitride (SION) layer  360  may be formed with a thickness of approximately 200 Å or more. According to an embodiment, the silicon oxynitride (SiON) layer  360  may be formed with a thickness ranging from approximately 200 Å to approximately 300 Å. The bottom anti-reflection coating (BARC) layer  370  may be formed with a thickness of approximately 240 Å. 
         [0027]    Subsequently, a first photoresist layer pattern  380  for forming a partition for the formation of spacers is formed by coating the upper surface of the bottom anti-reflection coating (BARC) layer  370  with a first photoresist layer and exposing and developing the first photoresist layer through any reasonably suitable, well-known exposure process (or liquid immersion lithography process) using a photoresist for krypton fluoride (KrF) or argon fluoride (ArF). 
         [0028]    Here, the bottom anti-reflection coating (BARC) layer  370  functions as an anti-reflection layer that prevents the reflection of the surface of the substrate during the exposure process, and the silicon oxynitride (SiON) layer  360  functions as a buffer layer. 
         [0029]    Referring to  FIG. 2B , the exposed silicon oxynitride (SiON) layer  360 , the bottom anti-reflection coating (BARC) layer  370 , and the amorphous carbon layer  350  ( FIG. 2A ) are etched by using the first photoresist layer pattern  380  as a mask. 
         [0030]    Subsequently, a partition  350 A for forming spacers is formed by removing the first photoresist layer pattern  380  through a well-known photoresist stripping process, and removing the silicon oxynitride (SiON) layer  360  and the bottom anti-reflection coating (BARC) layer  370 . 
         [0031]    Referring to  FIG. 2C , spacers  390  are formed on the sidewalls of the partition  350 A by depositing a spacer-forming oxide layer over the polysilicon layer  340  including the partition  350 A formed therein at a thickness of a desired line width, for example, approximately 200 Å, and at a temperature of approximately 50° C., and etching the spacer-forming oxide layer to expose the upper surface of the partition  350 A and the surface of the polysilicon layer  340 . 
         [0032]    Referring to  FIG. 2D , the partition  350 A is removed to completely expose the spacers  390 . Here, when the spacers  390  are formed of an oxide layer, film lifting may be easier as compared with a case where the spacers  390  are formed of a nitride layer. 
         [0033]    Referring to  FIG. 2E , a spin-on carbon (SOC) layer  400  and a multi-function hard mask (MFHM) layer  410  are sequentially formed over the polysilicon layer  340  to cover the spacers  390  and the polysilicon layer  340 . 
         [0034]    Subsequently, a second photoresist layer pattern  420  is formed by forming a second photoresist layer, exposing the second photoresist layer through any reasonably suitable, well-known exposure process (or liquid immersion lithography process) using a photoresist for krypton fluoride (KrF) or argon fluoride (ArF). 
         [0035]    Here, the second photoresist layer pattern  420  includes an opening that exposes a portion of the multi-function hard mask (MFHM) layer  410 . The opening of the second photoresist layer pattern  420  includes a first opening  450 A that exposes a portion of the multi-function hard mask (MFHM) layer  410  in the peripheral circuit region PERT and a second opening  450 B that exposes a spacer cutting region of the cell region CELL. 
         [0036]    As described above, since the mask for the spacer cutting region of the cell region CELL and the mask for the peripheral circuit region PERT are not separately formed but formed together as the second photoresist layer pattern  420 , the number of mask processes may be decreased. Also, although a silicon oxynitride layer is not additionally formed under the spacers  390 , the polysilicon layer  340  may sufficiently serve the function of a buffer layer. Moreover, since a stacked layer of the spin-on carbon (SOC) layer  400  and the multi-function hard mask (MFHM) layer  410  is used as a hard mask instead of a more expensive amorphous carbon layer, production costs may be reduced. 
         [0037]    Referring to  FIG. 2F , the exposed multi-function hard mask (MFHM) layer  410  and the spin-on carbon (SOC) layer  400  are etched using the second photoresist layer pattern  420  as a mask so as to expose a portion of the polysilicon layer  340  in the peripheral circuit region PERI and the spacer cutting region of the cell region CELL. Hereinafter, the etched multi-function hard mask (MFHM) layer  410  is referred to as a multi-function hard mask (MFHM) layer pattern  410 A, and the etched spin-on carbon (SOC) layer  400  is referred to as a spin-on carbon (SOC) layer pattern  400 A. 
         [0038]    Subsequently, the second photoresist layer pattern  420  is removed through any reasonably suitable, well-known photoresist stripping process. 
         [0039]    Referring to  FIG. 2G , the spacers  390  are cut by using the multi-function hard mask (MFHM) layer pattern  410 A and the spin-on carbon (SOC) layer pattern  400 A as masks and removing the spacer cutting region that is exposed through the spacer cutting etch process. 
         [0040]    Here, the spacers  390  are cut to isolate the spacers  390  because when the spacers  390  are formed on the sidewalls of the partition  350 A, the spacers  390  are formed with the shape of rim enclosing the partition  350 A. 
         [0041]    Referring to  FIG. 2H , a first polysilicon layer pattern  340 A is formed by using the multi-function hard mask (MFHM) layer pattern  410 A and the spin-on carbon (SOC) layer pattern  400 A as masks and etching the exposed portion of the polysilicon layer  340  of the cell region CELL and the peripheral circuit region PERI. 
         [0042]    Here, the cutting of the spacers  390  and the formation of the first polysilicon layer pattern  340 A may be performed consecutively using the same etch equipment. 
         [0043]    Subsequently, the multi-function hard mask (MFHM) layer pattern  410 A and the spin-on carbon (SOC) layer pattern  400 A are removed. 
         [0044]    Referring to  FIG. 2I , a third photoresist layer pattern  430  that opens the cell region CELL and masks the peripheral circuit region PERI is formed. Here, the third photoresist layer pattern  430  may be formed through an exposure process using a photoresist for krypton fluoride (KrF) (e.g., using a photoresist of krypton fluoride or using a krypton fluoride laser) because the third photoresist layer pattern  430  does not have to be formed as fine pattern. Therefore, production costs may be saved as compared with a case where the third photoresist layer pattern  430  is formed through a liquid immersion lithography process or using an exposure mask for ArF. 
         [0045]    Referring to  FIG. 2J , a second polysilicon layer pattern  340 B having a finer line width than the line width of the first polysilicon layer pattern  340 A is formed in the cell region CELL that is open by the third photoresist layer pattern  430  by using the spacers  390  as an etch mask and etching the first polysilicon layer pattern  340 A, which is disposed under the spacers  390 . 
         [0046]    Referring to  FIG. 2K , an oxide layer pattern  330 A is formed in the cell region CELL and the peripheral circuit region PERT by removing the third photoresist layer pattern  430  through any reasonably suitable, well-known photoresist stripping process and using the first polysilicon layer pattern  340 A of the peripheral circuit region PERI and the second polysilicon layer pattern  340 B of the cell region CELL as masks and etching the oxide layer  330  disposed therebelow until the pad nitride layer  320  is exposed. 
         [0047]    Referring to  FIG. 2L , first trenches  440 A of a fine line width are formed in the cell region CELL and second trenches  440 B having a thicker line width than the first trenches  440 A are formed in the peripheral circuit region PERI by using the first polysilicon layer pattern  340 A, the second polysilicon layer pattern  3408 , and the oxide layer pattern  330 A as masks and etching the pad nitride layer  320 , the pad oxide layer  310 , and the semiconductor substrate  300 . 
         [0048]    Subsequently, the first polysilicon layer pattern  340 A, the second polysilicon layer pattern  340 B, and the oxide layer pattern  330 A are removed. Afterward, although not illustrated in the drawing, a subsequent process, such as a process of forming an isolation layer, is performed. 
         [0049]    As described above, according to the embodiment of the present invention, since the mask for the spacer cutting region in the cell region and the mask for the peripheral circuit region are not separately formed and formed as one mask pattern, the number of mask processes may be reduced. Also, although a silicon oxynitride layer is not additionally formed under the spacers, the polysilicon layer alone may sufficiently serve as a buffer layer. Moreover, since the stacked layer of the spin-on carbon layer and the multi-function hard mask layer are used as a hard mask layer, instead of an expensive amorphous carbon layer, production costs may be reduced. 
         [0050]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 
         [0051]    For example, although a case where the fine pattern of a semiconductor device forms trenches for device isolation is taken as an example and described, the fine pattern may form any other reasonably suitable structures including but not limited to gates. 
         [0052]    Also, the present embodiment illustrates a memory device including memory cells and peripheral circuits, but the exemplary embodiments of the present invention may be applied not only to the memory device but also to general semiconductor devices that include both fine trenches and larger trenches than the fine trenches at the same time.