Abstract:
A phase locked loop and an associated alignment method are provided. A disclosed phase locked loop receives a reference signal to provide a feedback signal. The phase locked loop is first opened. When the phase locked loop is open, a frequency range of an oscillating signal from a voltage-controlled oscillator is substantially selected. The feedback signal is provided according to the oscillation signal. After the frequency range is selected, the phase locked loop is kept open and the phases of the reference signal and the feedback signal are substantially aligned. The phase locked loop is then closed after the reference signal and the feedback signal are aligned.

Description:
[0001]    This application claims the benefit of Taiwan application Serial No. 100133816, filed Sep. 20, 2011, the subject matter of which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates in general to a control method for a phase locked loop and an associated apparatus, and more particularly to a control method for quickly locking a phase locked loop and an associated apparatus. 
         [0004]    2. Description of the Related Art 
         [0005]    A phase locked loop that can serve as a clock multiplier or a clock generator. For example, an input clock having a frequency of 10 MHz, can generate an output clock having a frequency of 1 GHz via a phase locked loop, with a predetermine alignment relationship existing between phases of the output clock and the input clock. 
         [0006]      FIG. 1  shows a conventional phase locked loop  10  comprising a frequency/phase detector  12 , a charge pump  14 , a loop filter  16 , a voltage-controlled oscillator (VCO)  20 , a multi-modulus divisor (MMD)  22 , a sigma-delta modulator (SDM)  24 , and a bank correction controller  26 . Via a step-up signal UP and a step-down signal DN, the frequency/phase detector  12  sends a relationship associated with frequencies and phases of a reference signal F REF  and a feedback signal F DIV . The charge pump  14  then provides a charging/discharging current according to the relationship. The loop filter  16  substantially collects results of the charging/discharging, and generates a control signal V CTRL  to control a high-frequency oscillation signal F VCO  outputted by the VCO  20 . The MMD  22  steps down the oscillation signal F VCO  to generate the feedback signal F DIV . The SDM  24  generates a current divisor signal P IN  according to a desired divisor consisted of an integral signal N INT  and a fraction signal N FRAC  to determine a frequency divisor N DIV  to be executed by the MMD  22 . With a signal loop provided by the frequency/phase divisor  12 , the charge pump  14 , the loop filter  16 , the VCO  20 , and the MMD  22 , the phase of the feedback signal F DIV  is enabled to substantially follow the phase of the reference signal F REF . 
         [0007]    To reduce noise generated by the phase locked loop, a voltage-to-frequency gain of the VCO  20  during operations is designed to be low. To improve a narrow lockable range resulted by the low gain, the VCO  20  is designed with several banks each providing a corresponding lockable range.  FIG. 2  shows an operation time sequence of the phase locked loop  10 . The bank correction controller initially fixes a voltage of the control signal V CTRL  at a voltage value V REF  to equivalently open the phase locked loop  10 , and then performs correction bank by bank in a bank correction  27 . During the bank correction  27 , the bank correction controller  26  checks a relationship between the oscillation signal F VCO  and the reference signal F REF , and selects a bank on which the VCO  20  operates according to a selection signal BS. 
         [0008]    After the banks for the VCO  20  are confirmed, the frequencies of the reference signal F REF  and the feedback signal F DIV  approximating each other, and a close loop locking  29  performed. The bank correction controller  26  disengages the control signal V CTRL  from the clamping of the voltage value V REF , such that the phase locked loop  10  becomes closed to allow the phase of the feedback signal F DIV  to follow the phase of the reference signal F REF  having an approximate frequency. A period from the phase locked loop being closed to being locked is defined as a lock time. 
         [0009]      FIG. 3  shows a conventional frequency/phase detector  12 . Although the frequencies of the reference signal F REF  and the feedback signal F DIV  already fall within approximate ranges after the banks within are confirmed, the phases of the reference signal F REF  and the feedback signal F DIV  may yet be quite different, with a maximum difference possibly being as large as 360 degrees.  FIG. 4  shows a possible signal timing diagram, in which from top to bottom are the reference signal F REF , the feedback signal F DIV , the step-up signal UP, and the step-down signal DN. In  FIG. 4 , the phase of the feedback signal F DIV  falls behind that of the reference signal F REF  by almost 360 degrees. Therefore, in a references cycle of the reference signal F REF , the step-up signal UP is at logic 1 most of the time. 
         [0010]    When a phase difference gets large, the large phase difference is inclined to cause an increased lock time despite that the frequencies of the reference signal F REF  and the feedback signal F DIV  approximate each other, such that the increased lock time may exceed a lock time limit demanded by a system.  FIG. 5  shows a corresponding control signal V CTRL  possibly generated in response to the signals in  FIG. 4 . Since the step-up signal UP is mostly at logic 1, the control signal V CTRL  quickly reaches a non-linear, saturated high point once the phase locked loop becomes closed and locked. At this point, the frequency of the feedback signal F DIV  is slightly higher than that of the reference signal F REF , and so a rising edge of the feedback signal F DIV  gradually approximates a rising edge of the reference signal F REF  until a delayed part in the phase is made up—such process is referred to as non-linear settling. The control signal V CTRL  then returns to linearity so that the frequency of the feedback signal F DIV  approximates that of the reference signal F REF —such a process is referred to as linear settling. In short, a locking time T LOCK  is a total time of a time T NON-LINEAR  required for non-linear settling and a time T LINEAR  required for linear settling. T NON-LINEAR  may be roughly calculated by an equation (1) below. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         
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         [0011]    In the equation (1), f REF  and f DIV  are respectively frequencies of the reference signal F REF  and the feedback signal F DIV , N DIV  is a divisor when the MMD  22  performs close loop locking, and Δf VCO  is a possible maximum frequency difference of the VCO  20  for a current bank. For example, when Δf VCO  is around 3.978 GHz, F REF  is around 26 MHz and Δf VCO  is around 1 MHz, T NON-LINEAR  equals (3978/26)/1, which is as high as 153 μs. The rather long period of the T NON-LINEAR  is likely to exceed a predetermined tolerance of a system that has a set limit for the lock time, in a way that the system may fail to meet standardized specifications. For example, for communication systems including Global System for Mobile Communications (GSM), Bluetooth, Wireless Fidelity (WiFi) implementing burst transmission that switches among channels, a limit of the lock time T LOCK  is defined, which means the above excessive T NON-LINEAR  required for non-linear settling is unacceptable. 
       SUMMARY OF THE INVENTION 
       [0012]    According to an aspect the present invention, a phase alignment method is provided. The method comprises: rendering a phase locked loop, the phase locked loop receiving a reference signal and providing a feedback signal; opening the phase locked loop; comparing phases of the reference signal and the feedback signal when the phase locked loop is open to generate a phase difference signal; and changing a frequency or the phase of either the reference signal or the feedback signal to allow the phase of the feedback signal to approximate that of the reference signal. After the frequency or the phase of the reference signal or the feedback signal is changed, the phase locked loop is closed to allow the frequency or the phase of the feedback signal to follow that of the reference signal. 
         [0013]    According to another aspect the present invention, a phase locked loop comprising an oscillator, a frequency divisor, a phase detector, and a phase controller is provided. The oscillator provides an oscillation signal. The frequency divisor generates a feedback signal according to the oscillation signal and a divisor control signal. The phase detector compares a reference signal with the feedback signal to generate a phase difference signal. The phase controller renders the oscillation signal to be independent from the phase difference signal, and modifies the divisor control signal according to the phase difference signal when the oscillation signal is independent from the phase difference signal. After at least one feedback period of the feedback signal subsequent to the phase controller modifies the divisor controller signal, the phase controller starts to associate the phase difference signal with the oscillation signal and restores the divisor control signal. 
         [0014]    According to another aspect the present invention, a phase locked loop comprising an oscillator, a frequency divisor, a phase detector, a phase selector, and a phase controller is provided. The oscillator provides an oscillation signal. The frequency divider generates a feedback signal according to the oscillation signal and a divisor control signal. The phase detector compares a reference signal with the feedback signal to generate a phase difference signal. The phase selector selects a phase of a pre-reference signal as the reference signal according to a phase selection signal. The phase controller renders the oscillation signal to be independent from the phase difference signal, and determines the phase selection signal according to the phase difference signal. The phase controller further renders the oscillation signal to be non-independent from the phase difference signal after determining the phase selection signal. 
         [0015]    According to another aspect the present invention, a control method for a phase locked loop is provided. The phase locked loop receives a reference signal and provides a feedback signal. The control method comprises: opening the phase locked loop; substantially selecting a frequency range of an oscillation signal outputted by an oscillator when the phase locked loop is open, with the feedback signal being generated according to the oscillation signal; keeping the phase locked loop open after the frequency range is selected, and substantially aligning phases of the reference signal and the feedback signal; and closing the phase locked loop when the phases of the reference signal and the feedback signal are substantially aligned. 
         [0016]    The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1  is a conventional phase locked loop. 
           [0018]      FIG. 2  is an operation time sequence of the phase locked loop in FIG.  1 . 
           [0019]      FIG. 3  is a conventional phase/frequency detector. 
           [0020]      FIG. 4  is a timing diagram of signals in  FIG. 1 . 
           [0021]      FIG. 5  is a possible control signal V CTRL  resulted from the signal timings in  FIG. 4 . 
           [0022]      FIG. 6  is an operation time sequence of a phase locked loop according to an embodiment of the present invention. 
           [0023]      FIG. 7  is a phase locked loop according to an embodiment of the present invention. 
           [0024]      FIG. 8  is an apparatus  66  implemented in a bank and correction controller in  FIG. 7 . 
           [0025]      FIG. 9  is a timing diagram of signals in  FIG. 7  and  FIG. 8 . 
           [0026]      FIGS. 10 to 13  are several phase locked loops according to different embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0027]      FIG. 6  shows an operation time sequence of a phase locked loop according to an embodiment of the present invention. Comparing  FIGS. 2  and  6 , at least one process of phase alignment  31  is added between the bank correction and the close loop locking in FIG.  6 ., and is performed when the phase locked loop is open. 
         [0028]    Referring to  FIG. 6 , in an embodiment of the present invention, a phase locked loop is opened, and a bank correction  27  is then performed to determine a bank of a VCO in the phase locked loop, which is in equivalence selecting a frequency range of an oscillation signal outputted by the VCO. Within a period, the phase alignment  31  is performed. In this embodiment, an approach for the phase alignment selects a frequency or a phase of a reference signal or a feedback signal when the phase locked loop is kept open, and then closes the phase clocked loop and locks the close loop when the phase of the reference signal or the reference signal is aligned to within a difference range after a period of time. Since the phase is aligned to within the difference range, a phase locking is quickly achieved during close loop locking  29 . In other words, a lock time is significantly reduced accordingly. 
         [0029]      FIG. 7  shows a phase locked loop  58  according to an embodiment of the present invention. The phase locked loop  58  comprises a frequency/phase detector  12 , a charge pump  14 , a loop filter  16 , a VCO  20 , an MMD  22 , an SDM  24 , an adder  64 , a counter  62 , and a bank correction and phase controller  60 . Identical components shown in  FIG. 7  and  FIG. 1  can be easily appreciated by a person skilled in the art, and shall not be further described for the sake of brevity. 
         [0030]    When performing the bank correction  27  and the phase alignment  31 , the bank correction and phase controller  60  clamps a control signal V CTRL  to a fixed voltage value V REF , i.e., the phase locked loop  58  is opened. 
         [0031]    During the bank correction, the counter  62  provides a frequency ratio within a difference between a current reference signal F REF  and an oscillation signal F VCO . The bank correction and phase controller  60  accordingly adjusts a selection signal BS until the frequency ratio reaches a predetermined value to complete the bank correction. The predetermined value is a current frequency divisor N DIV  to be executed by the MMD  22 . Taking a highest channel of an RX mode of the mobile phone PCS1900 for example, a reference frequency f REF  of the reference signal F REF  is around 26 MHz, and an oscillation frequency f VCO  of the oscillation signal F VCO  up to 9.978 GHz is desired. Therefore, the bank correction and phase controller  60  adjusts the selection signal BS to select the bank of the VCO  20 , until the counter  62  obtains through calculation that there are 3978/26(=153) oscillation periods of the oscillation signal F VCO  in each reference period of the reference signal F REF . In this embodiment, the oscillation signal F REF  serves as a clock for the counter  62  until a count of 153 within reference period is obtained. At this point, a divisor signal P IN  triggers the MMD  22  to perform the frequency dividing by the divisor N DIV  of 153, and so a feedback frequency f DIV  of a feedback signal F DIV  approximately equals the reference frequency f REF  of the reference signal F REF  to both be around 26 MHz. 
         [0032]    Since the control signal V CTRL  is clamped by the voltage value V REF , the phase locked loop  10  becomes closed, and the oscillation signal F VCO  is independent from a step-up signal UP and a step-down signal DN. 
         [0033]    After the bank correction  27  is completed, the bank correction and phase controller  60  performs the phase alignment  31 . 
         [0034]    The step-up signal UP and a step-down signal DN generated by the frequency/phase detector  12  provide a message of phase difference between the reference signal F REF  and the feedback signal F DIV , and may then be regarded as a phase difference signal.  FIG. 8  shows an apparatus  66  implemented in the bank correction and phase controller  60 . The apparatus  66  is for generating a phase counter enables signal Phase_Counter_En and a polarity signal POL_IN according to the step-up signal UP and the step-down signal DN. In short, rising edges of a step-up recording signal UPF and a step-down recording signal DNF respectively record appearing time points of a rising edge of the step-up signal UP and a rising edge of the step-down signal DN. When the phase counter enable signal Phase_Counter_En is at logic 1, it means the rising edge appears in either one of the step-up signal UP and the step-down signal DN while the rising edge of the other signal is not yet appeared. Therefore, a pulse width of the phase counter enable signal Phase_Counter_En at logic 1 represents a time difference between the rising edge of the step-up signal UP and the rising edge of the step-down signal DN. When the polarity signal POL_IN is at logic 1, it means the rising edge of the step-up signal UP appears ahead of the rising edge of the step-down signal DN. Vice versa, when the polarity signal POL_IN is at logic 0, it means the rising edge of the step-up signal UP appears behind the rising edge of the step-down signal DN. 
         [0035]      FIG. 9  showing a timing diagram of signals in  FIGS. 7 and 8  depicts, from top to bottom, the reference signal F REF , the feedback signal F DIV , the step-up signal UP, the step-down signal DN, the step-up recording signal UPF, the step-down recording signal DNF, the phase counter enable signal Phase_Counter_En, the polarity signal POL_IN, and the divisor N DIV  executed by the MMD  22 . In the embodiment of  FIG. 9 , after the bank correction is completed, the reference frequency f REF  and the feedback frequency f DIV  approximate 26 MHz, the oscillation frequency f VCO  is 3.978 GHz, the divisor is 153, and the phase of the feedback signal F DIV  however falls behind that of the reference signal F REF  by around 360 degrees. 
         [0036]    As shown in  FIG. 9 , the period of the phase alignment is divided into two time processes—a phase difference calculation  90  and a phase adjustment  92 . 
         [0037]    The phase difference calculation  90 , being about two feedback periods of the feedback signal F DIV  in duration, is utilized for obtaining a time of the phase difference between and polarities of the reference signal F REF  and the feedback signal F DIV . The oscillation signal F VCO  serves as the clock for the counter  62  at this point. The counter  62  counts along with the oscillation signal F VCO  when the phase counter enable signal Phase_Counter_En is at logic 1, and stops counting when the phase counter enable signal Phase_Counter_En is at logic 0. In  FIG. 9 , when the phase difference calculation ends, the count CNT of the counter  62  is 145 and the polarity signal POL_IN is 1, which means the feedback signal F DIV  falls behind the reference signal F REF  by about 145 oscillation periods of the oscillation signal F VCO . Therefore, the count CNT and the polarity signal POL_IN may be together regarded as a phase difference signal. 
         [0038]    During the phase adjustment  92 , the feedback frequency f DIV  of the feedback signal F DIV  is changed by modifying the divisor N DIV , such that the rising edge of the feedback signal F DIV  may quickly catch up with a part by which the feedback signal F DIV  falls behind the reference signal F REF . In  FIG. 9 , the phase adjustment  92  needs to advance the rising edge of the feedback signal F DIV  by 145 oscillation periods. Supposing the rising edge of the feedback signal F DIV  is advanced by CNT oscillation periods when the divisor N DIV  of the MMD  22  is subtracted by X, an equation (2) below is obtained: 
         [0000]        N   DIV   /f   VCO ( N   DIV   −X )/ f   VCO =CNT/ f   VCO   (2)
 
         [0039]    An equation (3) can be deduced: 
         [0000]        X =CNT  (3)
 
         [0040]    In other words, the count CNT of the counter  62  and the polarity signal POL_IN may be utilized as basis for modifying the divisor N DIV . During the phase adjustment period in  FIG. 9 , the bank correction and phase controller  60  first sets Cu to 64, such that the divisor N DIV  is modified to 153−64=89. The bank correction and phase controller  60  then sets Cu to 81(=145−64), such that divisor N DIV  is modified to 153−81=72. Therefore, after two feedback periods of the feedback signal F DIV , the rising edge of the feedback signal F DIV  is advanced by a total of 145 (=64+81) oscillation periods ahead of that of the feedback signal F DIV  when the divisor N DIV  is not adjusted. It can be expected that when the phase adjustment  92  ends, the rising edge of the feedback signal F DIV  is substantially aligned with the rising edge of the reference signal F REF  to achieve the object of phase alignment, as shown in  FIG. 9 . In other embodiments, the polarity signal POL_IN may be 0 and so the divisor N DIV  is increased according to the count of the counter  62  during the phase adjustment, so as to delay the time point at which the rising edge of the feedback signal F DIV  appears. 
         [0041]    In the embodiment of  FIG. 9 , the phase adjustment is completed by using around two feedback periods. In other embodiments, due to possible modifiable range limits of the divisor N DIV  of the MMD  22 , more or less feedback periods may be needed to complete the phase adjustment. For example, in another embodiment, the phase adjustment is completed by using 10 feedback periods, with the divisor N DIV  adopted by the feedback periods respectively being (153−16, . . . , 153−10, 153−9). 
         [0042]    The close loop locking  29  is performed after completing the phase adjustment  92 . The bank correction and phase controller  60  disengages the control signal VCTRL from the clamping of the voltage value VREF such that the phase locked loop  58  becomes a closed loop. The bank correction and phase controller  60  sets Cu to 0 so that the divisor N DIV  restores to the original value of 153. Since the phase locked loop  58  is closed at this point, the oscillation signal F VCO  begins to associate with the step-up signal UP and the step-down signal DN, and the phase of the feedback signal F DIV  starts to follow the phase of the reference signal F REF . The rising edge of the feedback signal F DIV  is already substantially aligned with the rising edge of the reference signal F REF  at the beginning of the close loop locking  29 , and therefore the time T NON-LINEAR  required by non-linear settling is very much close to 0. It can be expected that the lock time is close to the time T LINEAR  required by linear settling to be extremely short. 
         [0043]    With reference to  FIG. 9 , the phase difference calculation  90  is two feedback periods of the feedback signal F DIV  in duration, i.e., (2*153/3978) μs. The phase adjustment is also two feedback periods in duration, i.e., [(153−64)+(153−81)]/3978 μs. As a result, the time needed for the phase alignment  31  in the embodiment shown in  FIG. 9  is merely 0.117 μs, which is less than 1/100 of 153 μs as the time T NON-LINEAR  required by non-linear settling in the prior art. Therefore, the embodiment in  FIG. 9  significantly reduces the lock time. 
         [0044]      FIG. 10  shows a phase locked loop  58   a  according to another embodiment of the present invention. A difference from  FIG. 7  is that, the phase locked loop  58   a  replaces the adder  64  by a phase selector  68 . The phase selector  68  selects a phase of a pre-reference signal F PR     —     REF  as the reference signal F REF  according to a selection signal SEL. The selection signal SEL is determined by a bank correction and phase controller  60   a.    
         [0045]    Similar to the operation time sequence shown in  FIG. 6 , the phase locked loop  58   a  first clamps the control signal V CTRL  to a fixed voltage reference value V REF , i.e., the bank correction  27  and the phase alignment  31  are performed when the phase locked loop  58   a  is open. The control signal V CTRL  is unclamped from the voltage value V REF  to close the phase locked loop  58   a , and the close loop locking  29  is then performed. During the bank correction  27  and the close loop locking  29 , the selection signal SEL is kept substantially unchanged. 
         [0046]    During the phase alignment  31 , the bank correction and phase controller  60   a  in the phase locked loop  58   a  utilize the counter  62 , the step-up signal UP and the step-down signal DN to calculate the phase difference. According to the phase difference, he bank correction and phase controller  60   a  changes the selection signal SEL. For example, when performing the phase alignment  31 , the bank correction and phase controller  60   a  learns that the feedback signal F DIV  falls behind the reference signal F REF  by about 145 oscillation periods of the oscillation signal F VCO  and the divisor NDIV currently adopted by the MMD  22  is about 153. Thus, the bank correction and phase controller  60   a  changes the selection signal SEL, so that the phase selector  68  selects from the pre-reference signal F PR     —     REF  a phase currently behind by 145/153*360 degrees as the reference signal F REF . Consequently, the phases of the reference signal F REF  and the feedback signal F DIV  are substantially aligned. In other words, in this embodiment, the bank correction and phase controller  60   a  renders the oscillation signal to be independent from the phase difference signal, and modifies the divisor control signal according to the phase difference signal when the oscillation signal is independent from the phase difference signal. After at least one feedback period of the feedback signal subsequent to the phase controller modifies the divisor controller signal, the phase controller starts to associate the phase difference signal with the oscillation signal and restores the divisor control signal. 
         [0047]    After the phase alignment  31  is completed, the selection signal SEL is kept unchanged and the phase locked loop  58   a  starts the close loop locking  29 . The phase of the feedback signal F DIV  starts to follow the phase of the reference signal F REF . The rising edge of the feedback signal F DIV  is already substantially aligned with the rising edge of the reference signal F REF  at the beginning of the close loop locking  29 , and therefore it can be expected that the lock time is extremely short. 
         [0048]    In both embodiments shown in  FIGS. 7 and 10 , the phase difference between the phase of the reference signal F REF  and the feedback signal F DIV  is first obtained, followed by performing the phase adjustment. The phase locked loop  58  in  FIG. 7  temporarily modifies the divisor N DIV  of the MMD  22  to also temporarily change the frequency of the feedback signal F DIV , so as to greatly change the time point at which the rising edge of the feedback signal F DIV  appears to substantially align the phases. On the other hand, the phase locked loop  58   a  in  FIG. 10  permanently changes the phase of the reference signal F REF  after obtaining the phase difference, so as to directly force the rising edge of the reference signal F REF  to substantially align with the rising edge of the feedback signal F DIV  to complete the phase alignment. 
         [0049]      FIG. 11  shows a phase locked loop  58   b  according to another embodiment of the present invention. This embodiment is practiced based on the basis of the phase difference, which is substantially a type of time difference. By converting the time difference to a digital signal, the concept of the phase difference calculation may be executed by a time-to-digital converter (TDC). Further, the phase locked loop  58   b  replaces the phase locked loop  10  in  FIG. 1  by a TDC  70  and an adder  64 . Similar to the operation time sequence in  FIG. 6 , the phase locked loop  58   b  first performs the bank correction  27  and the phase alignment  31 , followed by performing the close loop locking  29 . During the phase alignment  31 , the TDC  70  obtains the phase difference between the feedback signal F DIV  and the reference signal F REF  according to the step-up signal UP and the step-down signal DN, and converts the phase difference to a digital modification signal CU to momentarily modify the divisor N DIV  of the MMD  22 . During the close loop locking  29 , the TDC  70  no longer affects the divisor N DIV  and the digital modification signal CU is maintained at 0, so that the divisor N DIV  of the MMD  22  returns to being controlled by the divisor control signal P IN  of the SDM  24 . The operation time sequence and principles of the phase locked loop  58   b  in  FIG. 11  can be appreciated with reference to the description on the phase locked look  58  in  FIG. 7 , and shall not be further described. 
         [0050]      FIG. 12  shows a phase locked loop  58   c  according to yet another embodiment of the present invention. A difference from the phase locked loop  10  in  FIG. 1  is that, the phase locked loop  58   c  comprises a TDC  70   a  and a phase selector  68   a . Similar to the operation time sequence in  FIG. 6 , the phase locked loop  58   c  first performs the bank correction  27  and the phase alignment  31 , followed by performing the close loop locking  29 . During the phase alignment  31 , the TDC  70   a  obtains the phase difference between the feedback signal F DIV  and the reference signal F REF  according to the step-up signal UP and the step-down signal DN, and converts the phase difference to a selection signal SEL to permanently change the phase of the reference signal F REF . The operation time sequence and principles of the phase locked loop  58   c  in  FIG. 12  can be appreciated with reference to the description on the phase locked look  58   a  in  FIG. 10 , and shall not be further described. 
         [0051]      FIG. 13  shows a phase locked loop  58   d  according to yet another embodiment of the present invention. The phase locked loop  58   d  in  FIG. 13  enters the close lock locking  29  after the bank of the VCO  20  is confirmed. At this point, a bank correction controller  26   a  sends a short pulse signal Reset at a first rising edge of the reference signal F REF  to reset an MMD  22   a  and a phase/frequency detector  12   a . For example, when the phase/frequency detector  12   a  is reset, the step-up signal UP and the step-down signal DN are forced to 0, and the feedback signal F DIV  outputted by the MMD  22   a  immediately starts from a rising edge. Because the short pulse signal Reset substantially synchronizes the rising edge of the feedback signal F DIV  with the rising edge of the reference signal F REF , and the step-up signal UP and the step-down signal DN both start from 0, a situation that the phase difference being as large as 360 degrees is completely avoided to noticeably improve the lock time. 
         [0052]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.