Abstract:
The present invention discloses a frequency synthesizer, including: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, for selecting a specific clock signal from the clock signals as an output clock signal, wherein a specific frequency locking circuit of the frequency locking circuits locks the specific clock signal; and a control circuit, for controlling the frequency locking circuits. The control circuit controls at least one of the frequency locking circuits apart from the specific frequency locking circuit to lock another clock signal according to another reference clock signal at the same time. A related method for frequency synthesizing is also disclosed.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a frequency synthesizer, and more particularly relates to a frequency synthesizer with a plurality of frequency locking circuits. 
   2. Description of the Prior Art 
   An electronic system or circuit always utilizes a frequency synthesizer to synchronize a system, where the frequency synthesizer always includes a frequency locking circuit such as a PLL to lock a specific signal to a specific frequency. As the system speed increases rapidly, the locking speed of the frequency locking circuit becomes more and more important. The locking speed of the frequency locking circuit is limited by the frequency of a reference clock signal, therefore, the application of this technology to a high speed hopping system is also limited. 
   SUMMARY OF THE INVENTION 
   Thus, one objective of the present invention is to provide a frequency synthesizer, which can enlarge the settling time of the frequency locking circuit and decrease power consumption by settling a plurality of frequency locking circuits in the mean time. 
   Another objective of the present invention is to provide a frequency synthesizer, which controls a plurality of frequency locking circuits to lock signals while decreasing power consumption and system loading. 
   Still another objective of the present invention is to provide a frequency synthesizer, which has frequency locking circuits corresponding to at least one reference clock signal to increase the flexibility of the system and decrease the circuit area. 
   The present invention discloses a frequency synthesizer, comprising: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, coupled to the frequency locking circuits, for selecting a specific clock signal from the clock signals as an output clock signal, wherein a specific frequency locking circuit of the frequency locking circuits locks the specific clock signal; and a control circuit, coupled to the frequency locking circuits for controlling the frequency locking circuits, wherein the control circuit controls at least one of the frequency locking circuits except for the specific frequency locking circuit to lock another clock signal according to another reference clock signal at the same time. Preferably, the number of the frequency locking circuits is less than the number of the reference clock signals. 
   The present invention also discloses a frequency synthesizer, comprising: a plurality of frequency locking circuits, for locking a plurality of clock signals to output the clock signals according to a plurality of reference clock signals respectively; a selecting circuit, coupled to the frequency locking circuits, for selecting a first clock signal from the clock signals as an output clock signal, wherein a first frequency locking circuit of the frequency locking circuits locks the first clock signal; and a control circuit, coupled to the frequency locking circuits for controlling the frequency locking circuits, wherein the control circuit controls at least one of the frequency locking circuits apart from the specific frequency locking circuit to lock another clock signal according to another reference clock signal during the selecting circuit selects the first clock signal as the output clock signal 
   The present invention further discloses a method for frequency synthesizing, comprising: locking a plurality of clock signals and outputting the clock signals according to a plurality of reference clock signals; selecting a specific clock signal from the clock signals as an output clock signal; and locking another clock signal according to another reference clock signal during the period of selecting the specific clock signal as the output clock signal. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a functional block diagram illustrating a frequency synthesizer according to a first embodiment of the present invention. 
       FIG. 2  is a functional block diagram illustrating a frequency synthesizer according to a second embodiment of the present invention. 
       FIG. 3  is a functional block diagram illustrating a frequency synthesizer according to a third embodiment of the present invention. 
       FIG. 4  is a functional block diagram illustrating a frequency synthesizer according to a fourth embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     FIG. 1  is a functional block diagram illustrating a frequency synthesizer  200  according to a first embodiment of the present invention. As shown in  FIG. 1 , the frequency synthesizer  200  includes a control circuit  202 , a first frequency locking circuit  204 , a second frequency locking circuit  206 , a third frequency locking circuit  208  and a selecting circuit  210 . The first frequency locking circuit  204  locks a first clock signal CS 1  and outputs the first clock signal CS 1  according to a first reference clock signal RCS 1 . The second frequency locking circuit  206  locks a second clock signal CS 2  and outputs the second clock signal CS 2  according to a second reference clock signal RCS 2 . And the third frequency locking circuit  208  locks a second clock signal CS 3  and outputs the third clock signal CS 3  according to a third reference clock signal RCS 3 . The selecting circuit  210  selects one of the clock signals CS 1 , CS 2  and CS 3  as an output clock signal OCS. The control circuit  202  controls the first frequency locking circuit  204 , the second frequency locking circuit  206 , and the third frequency locking circuit  208 . In this embodiment, the frequency locking circuits are implemented by frequency locking circuits  204 ,  206  and  208 , and the selecting circuit  210  is implemented by a multiplexer. It should be noted that persons skilled in the art can utilize other circuits to reach the same function, and such a modification also falls within the scope of the present invention. 
   The second frequency locking circuit  206  locks the second clock signal CS 2  to the second reference clock signal RCS 2  and the third frequency locking circuit  208  operates according to the third reference clock signal RCS 3  during the period of the selecting circuit  210  selecting the first clock signal CS 1  as the output clock signal OCS. Similarly, the third frequency locking circuit  208  locks the third clock signal CS 3  to the third reference clock signal RCS 3  during the period of the selecting circuit  210  selecting the second clock signal CS 2  as the output clock signal OCS. 
   Furthermore, each of the frequency locking circuits  204 ˜ 208  can correspond to more than one reference clock signal during the each locking period. For example, the control circuit  202  controls the second frequency locking circuit  206  to lock the second clock signal CS 2  to the second reference clock signal RCS 2  gradually while the first clock signal CS 1  is locked to the first reference clock signal RCS 1  and selected as the output signal OCS. Similarly, the control circuit  202  controls the third frequency locking circuit  208  to lock the third clock signal CS 3  to the third reference clock signal RCS 3  gradually while the second clock signal CS 2  is locked to the second reference clock signal RCS 2  and selected as the output signal OCS. After the third clock signal CS 3  is locked to the third reference clock signal RCS 3 , the third clock signal CS 3  is selected as the output signal OCS, and the control circuit  202  further controls the first frequency locking circuit  204  such that the first clock signal CS 1  is gradually locked to a fourth reference clock signal RCS 4  with a frequency different from that of the first reference clock signal RCS 1 . Thereby a clock signal can be locked to different reference clock signals by a single frequency locking circuit. Furthermore, unnecessary power consumption and loading can be reduced if the frequency locking circuit is turned on only when needed. 
   It should be noted that the above-mentioned description is not meant to limit the operation of the frequency synthesizer  200 . For example, the control circuit  202  can control the second frequency locking circuit  206  to lock the second clock signal CS 2  to the second reference clock signal RCS 2  gradually. Alternatively, the frequency synthesizer  200  can jointly control the second frequency locking circuit  206  and the third frequency locking circuit  208  to lock the second clock signal CS 2  and the third clock signal CS 3  to the second reference clock signal RCS 2  and the third reference clock signal RCS 3  gradually. In other words, the control circuit  202  can control at least one of the frequency locking circuits corresponding to the non-selected clock signals to gradually lock the clock signals to corresponding reference clock signals. The locking time and the number of the clock signals to be locked can be amended according to the demands of a system or a user. 
     FIG. 2  is a functional block diagram illustrating a frequency synthesizer  300  according to a second embodiment of the present invention. Similar to the frequency synthesizer  200 , the frequency synthesizer  300  also includes a control circuit  302 , a first frequency locking circuit  304 , a second frequency locking circuit  306 , a third frequency locking circuit  308  and a selecting circuit  310 . The difference is that the frequency synthesizer  300  further includes a reference clock generating module  312  for outputting M reference clock signals RCS 1 , RCS 2  . . . RCS M  (M&gt;3). In this embodiment, the control circuit  302  not only controls the operation of the first frequency locking circuit  304 , the second frequency locking circuit  306 , and the third frequency locking circuit  308 , but also selects a reference clock signal from M reference clock signals RCS 1 , RCS 2  . . . RCS M  to be outputted to the frequency locking circuits  304 ˜ 308 . The frequency synthesizers  200  and  300  are similar to each other besides the reference clock generating module  312 , and thus further description is omitted for brevity. It should be noted that the number of the frequency locking circuits is not limited to three. 
     FIG. 3  is a functional block diagram illustrating a frequency synthesizer  400  according to a third embodiment of the present invention. The frequency synthesizer  400  includes a control circuit  402 , N frequency locking circuits  404 ˜ 408  and a selecting circuit  410 . The operation of the control circuit  402 , the frequency locking circuits  404 ˜ 408  and the selecting circuit  410  is the same as that in the first and second embodiments. If the selecting circuit  410  selects one of the clock signals CS 1 , CS 2  . . . CS N  as the output clock signal OCS, the control circuit  402  will control at least one of the frequency locking circuits corresponding to the frequency of non-selected clock signals to gradually lock corresponding clock signals to corresponding reference clock signals. The locking time and the number of the clock signals to be locked can be amended according to requirements. 
     FIG. 4  is a functional block diagram illustrating a frequency synthesizer  500  according to a fourth embodiment of the present invention. Similar to the frequency synthesizer  400 , the frequency synthesizer  500  includes a control circuit  502 , N frequency locking circuits  504 ˜ 508  and a selecting circuit  510 . The difference is that the frequency synthesizer  500  further includes a reference clock generating module  512  for outputting M reference clock signals RCS 1 , RCS 2  . . . RCS M  (M&gt;N). In this embodiment, the control circuit  502  not only controls the operation of the frequency locking circuits  504 ˜ 508 , but also selects a reference clock signal from M reference clock signals RCS 1 , RCS 2  . . . RCS M  to be outputted to the frequency locking circuits  504 ˜ 508 . 
   If the retention period of each frequency is tp and the interval is ts, the settling time of the embodiment of the present invention can be enlarged to ts+(N−1) (tp+ts) via utilizing a plurality of frequency locking circuits for settling. Also, the embodiment of the present invention does not need numerous switches to switch the frequency locking circuit, thus the power consumption can be reduced. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.