Abstract:
An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    This invention relates to improved EPROM structures and the method of manufacturing the structures with CMOS and BICMOS technologies that utilize lightly doped drain extensions.  
           [0002]    The prior art CMOS and BICMOS device structures often consist of an N type lightly doped drain (Nldd) which is used to grade the drain to body doping. This grading is necessary for reliability purposes. Without the grading, the drain to body electric field is large enough to generate an abundance of hot electrons. Hot electrons eventually lead to threshold voltage shifts, drive current degradation, sub-threshold voltage degradation and transconductance degradation. Any or all of these parametric shifts may be sufficient to lead to circuit failures over the life of the circuit. Hence reliability is compromised.  
           [0003]    Attempts have been made to solve this problem. U.S. Pat. No. 4,970,565 dated Nov. 13, 1990, describes a method of building a sealed charged storage structure in a memory cell for an EPROM device which is totally sealed from ultraviolet a light by a conductive cover without openings therein for leads to the cell&#39;s drain, source and gate. Electrical communication with the source is provided by direct contact with the conductive cover. Access to the drain and floating gate is provided by buried N ++  implants, buried N +  layers or N wells crossing underneath the sides of the cover. The memory cell has a single poly floating gate rather than a stacked floating gate/control gate combination. The buried N +  implant or N well serves as the control gate and is capacitively coupled to the floating gate via a thin oxide layer in a coupling area.  
           [0004]    U.S. Pat. No. 5,307,312 dated Apr. 26, 1994 describes a process for obtaining an N channel single polysilicon level EPROM cell. The process provides for the simultaneous N +  type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.  
           [0005]    U.S. Pat. No. 5,470,771 dated Nov. 28, 1995, describes a method of manufacturing a floating gate memory device. A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.  
           [0006]    Finally, U.S. Pat. No. 5,479,367 dated Dec. 26, 1995 describes an N channel single polysilicon level EPROM cell. The process provides for the simultaneous N +  type implantation of areas of a semiconductor substrate of type P for the formation of a control gate and of highly doped regions of source and drain, defining a channel region. After oxide growth there is executed the deposition and the definition of a polysilicon layer, one region of which constitutes a floating gate above the control gate and the channel region and partially superimposed over the regions of source and drain.  
         SUMMARY OF INVENTION  
         [0007]    An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.  
           [0008]    In an unprogrammed state as fabricated, the NMOS transistor has a relatively low threshold voltage (the voltage necessary to turn “on” the transistor), typically less than 1.0 volts when referenced from the floating gate to ground. In the EPROM structure, there is no direct connection to the floating gate, so the threshold voltage must be referenced to the control gate. Because of capacitive voltage dividing, the threshold voltage is somewhat higher, but still typically less than 2.0 volts when referenced to the control gate. Ignoring parasitic capacitances, the relationship of control gate voltage to floating gate voltage is: 
             Vfg=Vcg*C 1/( C 1+ C 2) 
           [0009]    where:  
           [0010]    fg=floating gate  
           [0011]    cg=control gate  
           [0012]    C 1 =capacitance of the capacitor  
           [0013]    C 2 =gate capacitance of the NMOS transistor  
           [0014]    So, with the source and body grounded, the drain biased at some positive voltage (5.0 volts, for example), and the control gate biased greater than the threshold voltage (2.5 volts, for example), the NMOS transistor in an unprogrammed EPROM is in the “on” state and drain current flows.  
           [0015]    To program the EPROM, the bias conditions are set momentarily so that there is a substantial amount of drain current flowing and hot electrons are generated. Typical bias conditions might be 7.0 volts on the drain and 12.0 volts on the control gate. With these bias conditions, a tremendous amount of hot electrons are generated in a typical 5V, 0.5 micron NMOS transistor. With 12.0 volts on the control gate, there might be 10.0 volts or more across the NMOS gate oxide according to the equation given above. This gate oxide potential “assists” the injection of hot electrons (which already have an abundance of energy) through the gate oxide onto the polysilicon gate. Since the polysilicon gate is a floating gate without connections, these electrons are trapped here due to the oxide insulators which encapsulate the polysilicon once the programming event is complete. After ˜200 milliseconds (a typical duration of the programming event), the amount of electrons trapped on the floating gate is significant and sufficient to drastically impact the NMOS transistor characteristics. During such programming, it is possible to increase the NMOS transistor threshold voltage to 4.0-10.0 volts. Assuming this new, higher threshold voltage and the same operating bias conditions described above (5.0 volts on the drain and 2.5 volts on the control gate), the NMOS transistor of the EPROM is now in the “off” state (negligible drain current flowing). By selectively programming EPROMs on a circuit depending on the circuit behavior, the circuit can be trimmed or fine-tuned to enhance its performance. It should be noted at this time that 200 milliseconds to program a single EPROM can be very costly. On a complex circuit, it is possible that several programming iterations must be performed for each circuit which can significantly added to the probe/test cost. A faster programming EPROM could reduce probe/test cost significantly.  
           [0016]    5V CMOS technologies in the 0.5 micron regime generally utilize NMOS architectures which attempt to control hot electron generation. Most popular is the lightly doped drain (NLdd) combined with spacer technology. These precautions are necessary due to reliability concerns. Over the course of a circuit&#39;s active 10 year lifetime, hot electron are continuously being generated at a low level. These hot electrons will degrade the transistor performance (threshold voltage shifts, drive current degradation, sub-threshold slope degradation and transconductance degradation) which can eventually lead to circuit failure. Because of the reliability implications, the NMOS transistor architecture is optimized so that significant hot electron generation is eliminated.  
           [0017]    Here is the dilemma: special precautions have been taken to control hot electron generation in the standard NMOS transistor, but excessive hot electron generation is desired in the EPROM&#39;s NMOS transistor for fast, reliable programming. An improved EPROM semiconductor structure invention is formed by the addition of a P type region that augments a P well doping under a NMOS transistor gate. This-added P region under the gate is formed by an additional photolithography and an additional implantation process steps. Alternatively, this P region could be formed during other processing steps that are already in the process flow for other reasons (an NPN transistor P Base, for example). The addition of this new P region changes the dopant grading of the drain-body junction which allows for an increase in the generation of hot electrons in the EPROM NMOS transistor. Hence, the EPROM can be programmed faster and/or at a lower voltage. Only the NMOS transistor of the EPROM receives the added P region. The standard NMOS transistor in the remainder of the circuitry does not have the P region so its reliability is not compromised.  
           [0018]    The new P type regions do not intersect in the center of the NMOS transistor of the EPROM. This ensures that the threshold voltage in the center of an unprogrammed EPROM remains at a low value of less than 2.0 volts. The existence of the P region along the edges of the device will increase the threshold voltage in these regions.  
           [0019]    An enhancement to this design provides a better NMOS layout would have the Nldd regions removed along the edges of the transistor, but present in the center of the device. This would ensure an intersection of the new P type region with N +  and the associated high electric field region.  
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0020]    [0020]FIG. 1 is a schematic diagram of an EPROM cell ( 101 ) according to the invention.  
         [0021]    [0021]FIG. 2 illustrates a prior art device ( 100 ) showing a top view of a lightly doped drain NMOS transistor which is a portion of an EPROM structure;  
         [0022]    [0022]FIG. 3 illustrates a cross section of the prior art device ( 100 ) of FIG. 1; as seen from section lines III-III of FIG. 2;  
         [0023]    [0023]FIG. 4 illustrates a top down view of an NMOS transistor ( 101 ) according to the invention;  
         [0024]    [0024]FIG. 5 illustrates a cross section of the NMOS transistor ( 101 ) of FIG. 4; as seen from section lines V-V of FIG. 4;  
         [0025]    [0025]FIG. 6 is a top view of an alternative embodiment of the invention ( 110 ).  
         [0026]    [0026]FIGS. 7, 8 and  9  illustrate cross sectional views VII, VIII, and IX respectively of FIG. 6.  
         [0027]    [0027]FIGS. 10 a - 10   i  illustrate the steps used to fabricate an improved EPROM semiconductor structure by the addition of a P type region that augments the P well doping under the NMOS device gate.  
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0028]    Referring to FIG. 1, there is shown a schematic of an EPROM cell  101  according to the invention. The EPROM cell  101  includes a NMOS transistor  102  integrated with capacitor  104 . A control gate  105  is connected directly to one of the plates of a capacitor  104 . A floating gate  103  is located between the control gate  105  and the source and drain of transistor  102 .  
         [0029]    [0029]FIGS. 2 and 3 are a top view and a sectional view as seen from lines III-III of a prior art CMOS and BICMOS device structures  100  manufactured on a silicon substrate. The CMOS and BICMOS device structures  100  includes a poly gate  1 , a drain  2 , and a source  3 . The drain  2  and source  3  each include a N +  region  4  and  14  on the surface of a P well  6 . Oxide spacers  7  and  17  are located between the source  3  and drain  2  and around the poly gate  1 . Dopant grading is provided between the P well  6  and the N +  region  4  and  14  of the source  3  and drain  2  by lightly doped drains (Nldd)  5  and  15 .  
         [0030]    This grading is necessary for reliability purposes. Without the grading, the drain to body electric field is sufficiently large to generate an abundance of hot electrons. Hot electrons eventually lead to threshold voltage shifts, drive current degradation, sub-threshold voltage degradation and transconductance degradation. Any or all of these parametric shifts may be sufficient to lead to circuit failures over the life of the circuit. Hence reliability is compromised.  
         [0031]    An EPROM cell requires hot electron generation for programming but the process technology may utilize lightly doped drains and spacers to minimize hot electron generation. The result is an NMOS transistor  100  cell which cannot be programmed or which requires an inordinate amount of time to program. Complex circuits require a large number of EPROMS and thus a long programming time of 200 ms per EPROM could add a couple of seconds or more to the test time and thus increase the expense considering the millions of circuits which require testing.  
         [0032]    Referring to FIG. 4, there is illustrated a top down view of an NMOS transistor  101  suitable for use as an EPROM cell according to the invention. The NMOS transistor  101  includes a drain  2  and a source  3  of a N +  regions  4  and  14 . Additionally, there is a poly gate  1  with a P well  6  located beneath the poly gate  1  and the N +  regions  4  and  14 . Lightly doped drain (Nldd) regions  5  and  15  are located beneath the N +  regions  4  and  14  and extends into the channel region under the poly gate  1 . Oxide spacers  7  and  17  are located on the top surface of the substrate adjacent to the poly gate  1  and is used during the implanting of the N +  region  4  and  14  as a masked for the drain  2  and source  3 . Novel P regions  8  and  18  are located beneath the poly gate  1  and separated from the N +  regions  4  and  14  by the Nldd regions  5  and  15 , respectively. The P regions  8  and  18  extend into the P well  6  from the outer periphery  51  but are not present in the center  50  of the NMOS transistor  101 . In a pure CMOS process flow, the new P regions  8  and  18  and the P well  6  are positioned prior to the poly gate  1  formation.  
         [0033]    The P regions  8 -and  18  may or may not be completely counter dope to the Nldd region  5  and  15  and may or may not actually intersect with the N +  regions  4  and  14 . The purpose of the P regions  8  and  18  are to increase the electric field between the N +  region  4  and P well  6 . This increase in the electric field will increase the hot electron generation rate in programming an EPROM cell and thus will enable the NMOS transistor  101  to be programmed quicker and possibly at a lower voltage than the prior art devices.  
         [0034]    It should be noted that the N +  regions  4  and  14  are completely contained within Nldd regions  5  and  15 .  
         [0035]    In FIG. 5 there is illustrated a sectional view of the NMOS transistor  101  as seen from section lines V-V of FIG. 4 and suitable for use as an EPROM cell according to the invention. This embodiment solves the above described disadvantage of the prior art devices. The NMOS transistor  101  cell includes the body P well  6 , on which there is the poly gate  1 , drain  2 , and source  3 . The oxide spacers  7  and  17  are on the sides of the poly gate  1  which is over the channel that is bounded by the N +  regions  4  on one side and  14  on the other side. Located beneath the N +  regions  4  and  14  are the Nldd regions  5  and  15  with Nldd region  5  being completely under the N +  region  4  and Nldd region  15  being completely under the N′ region  14 . Both N +  regions  4  and  14  are not connected to the poly gate  1  in the channel region and are connected to a LOCOS region  49  that establishes the outer periphery  51 . The additional P regions  8  and  18  are present in the channel region beneath the poly gate  1  and connected to the Nldd regions  5  and  15 . Not shown is a thin oxide layer that separates the poly gate  1  from the channel and the Nldd regions  5  and  15 .  
         [0036]    Here again FIG. 5 illustrates the sectional view of the device of FIG. 4 as seen from the section lines V-V of FIG. 5. Because regions  8  and  18  are only located at the edges of the structure,. a view through section lines VI-VI through the device center would appear identical to FIG. 3.  
         [0037]    Referring to FIG. 6, there is shown a top view of NMOS transistor  110  which is an alternate embodiment of the invention and is suitable for use as an EPROM cell. As in the embodiment of FIG. 4, this embodiment includes drain  2  source  3  and poly gate  1 . However, the Nldd regions  5  and  15  are removed from along the edges of the NMOS transistor  101  except in the center of the device. This arrangement insures the intersection of the P regions  8  and  18  with the N +  regions  4  and  14  because of the associated high electric field, it is important that the P regions  8  and  18  intersect with the N +  drain regions  4  and  14 . However, using this alternate approach enables the P regions  8  and  18  to only be included as a design choice. In the embodiment of FIG. 6, the N +  regions  4  and  14  are not completely contained within Nldd regions  5  and  15 . Each of the Nldd regions  5  and  15  extend from the left and right edges of the active area towards the center of the poly gatel.  
         [0038]    [0038]FIG. 7 is a sectional view of the device  110  as seen from the sectional lines VII-VII of FIG. 6. This sectional view shows the P regions  8  or  18  as hidden lines and thus resembles the prior art device shown in FIG. 2.  
         [0039]    [0039]FIG. 8 is a sectional view of the device  110  as seen from section lines VIII-VIII of FIG. 6. As can be seen from the figure, the Nldd regions  5  and  15  are not presented at this position on the cell  110 .  
         [0040]    [0040]FIG. 9 is a sectional view of the EPROM cell  110  as seen from the sectional lines IX-IX of FIG. 6. As seen from the figures, the P region  8  is visible but the Nldd regions  5  and  15  are not presented at the section position.  
         [0041]    [0041]FIGS. 10 a - 10   i  provides an abbreviated process flow diagram sufficient to enable one skilled in the art to practice the invention without undue experimentation. Additionally, Table 1 provides a more detailed description of the process flow necessary to fabricate the invention.  
         [0042]    Beginning with FIG. 10 a , the process for the disclosed embodiments starts with an N type tub  43  that is pattern by a first reticle being implanted into the P type substrate  44 . A thin oxide layer  41  is then created at least on top of the N type tub  43 . The N tub  43  is not necessary with an N +  wafer and an N −  epitaxial layer.  
         [0043]    In FIG. 10 b , the growth of an epitaxial silicon layer  45  can be performed by the growing of the N type epitaxial silicon layer  45 .  
         [0044]    In FIG. 10 c , following the growth of the epitaxial layer  45 , an active area  52  is masked and an LOCOS operation is performed leaving a LOCOS oxide layer  49  around the mask that establishes an active area  52  having the outer periphery  51 .  
         [0045]    In FIG. 10 d , after preparation of the active area  52  using techniques known to those skilled in the art and using a second reticle, a P well  6  having a junction depth of approximately 1 micron, is implanted into the N type epitaxial layer  45  with a peak doping of approximately 3.0×10 17 /cm 3 . P base regions  8  and  18 , novel to the invention, are then implanted into the P well  6  using a third reticle at a junction depth approximately 0.60 microns and a peak doping of approximately 1.0×10 18 /cm 3 . The term “P base” is used to denote the step in which on different parts of the semiconductor chip of the disclosed embodiment,. the P base of an NPN transistor is simultaneously being fabricated. If no such P base operation exists in the process, extra dedicated operations could be added to the flow process to create regions  8  and  18 .  
         [0046]    In FIG. 10 e , the results of the steps used to create the poly gate  1  is disclosed. The steps include growing the gate oxide  53 , depositing a layer of polysilicon. After which there is an N +  doping performed unpatterned polysilicons. The layer of polysilicon is masked and etched to create the poly gate  1 . Then, using the pattern left by the second reticle and the poly gate  1  to define the Nldd regions  5  and  15  there is performed an Nldd implant at a junction depth of approximately 0.25 microns and a peak doping of approximately 3.0×10 18 /cm 3  as shown is FIG. 10 f.    
         [0047]    In FIG. 10 g , the oxide is deposited and etched to form the oxide spaces  7  and  17 .  
         [0048]    In FIG. 10 h , using the pattern left by the second reticle and the oxide spacers and the same reticle used for the Nldd implants, N +  regions  4  and  14  are implanted at a junction depth of approximately 0.2 microns and a peak doping of approximately 1.5×10 2 /cm 3  between the LOCOS area and the oxide spaces  7  and  17 .  
         [0049]    Finally, in FIG. 10 i , the circuit is completed according to common practices in the art including adding passivation layer  62 , metal connection, etc.  
                           TABLE 1                                   Step   Parameters                           P Substrate               Initial Oxidation   5300A           N Tub PR/Etch/Implant   (optional)           N Tub Drive           Oxide Strip           Epi   3.1-3.6 μm           Pad Oxidation   250A           Nitride Deposition   1550A           Nitride PR/Etch           Isolation Oxidation   6000A           Nitride Strip/Pad Oxide Strip           Sacrificial Oxidation   300A           P Well PR/Implant   B 11 , 4.0 × 10 12 /cm 2 , 30 KeV &amp;               B 11 , 1.2 × 10 13 /cm 2 , 284 KeV           P Base PR/Implant   B 11 , 3.0 × 10 13 /cm 2 , 50 KeV           Sacrificial Oxidation Strip   9:1 BHF 45 secs           Gate Oxidation   140A           Poly Deposition/Dope           Poly PR/Etch           Poly Oxidation   50A           N Ldd PR/Implant   P 31 , 4.0 × 10 13 /cm 2 , 80 KeV           Oxide Spacer Deposition   2000A           Oxide Spacer Etch           Screen Deposition   225A           N +  PR/Implant   AS 75  , 2.0 × 10 15 /cm 2 , 120 KeV           S/D RTA           Screen Etch           Platinum Sputter/Sinter/Strip           Field Dep/Planarization           Contacts PR/Etch           Triple Level Metal