Abstract:
A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request.

Description:
BACKGROUND 
   The invention relates to an arbitration circuit. More particularly, the invention relates to a preemptive round robin arbitration circuit. 
   When an asset or resource, such as a personal computer data bus, needs to be used by multiple requesters, such as a modem, a hard disk and/or a software program, some kind of allocation scheme needs to be provided. Hence, if no single asset or resource is in an extreme hurry, a round robin scheme may be used where, on a given clock cycle, one device request line is polled to ascertain whether or not that requester or device has a need for the asset. If there is a request, the request is granted for an appropriate amount of time. After that request is removed or finished, the system proceeds to the next requester in line. If a device far down the line of requesters in the round robin circuit has a request even though no one else has a request between the present arbitration logic circuit and the one connected to a requester requiring access to the asset, the circuit may still require one or more clocks to get to the requester having a present need to acquire the use of the asset. Therefore, overhead for the conventional round robin circuit may take more than one cycle when the service is granted from one request to another request. Furthermore, the circuit may not allow an interactive request to break in during a granted batch request if both batch request and interactive request are asserted resulting in the response time to the interactive request to become intolerable. The interactive request is an asynchronous request typically containing control information, whereas the batch request is a synchronous request typically involving sequentially accessed data. 
   In some cases, conventional resource allocation schemes use a priority interrupt technique where the requester with the most priority is always the next one to have access to the asset. However, with such a priority interrupt technique, a requester with low priority may have to wait an extremely long time before being granted access to an asset. 
   SUMMARY 
   In one aspect, a resource allocation arbitration system is disclosed. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the request stored in each storage device is almost empty. Furthermore, the mask bits enable preemption of one request by another request. 
   In another aspect, an arbitration method is described. The method includes storing requests for allocation of resources, indicating a condition in which the stored requests are almost empty, and arbitrating the allocation of resources by providing selection bits that operate in conjunction with the indicator to substantially reduce idle time between the requests. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. 
       FIG. 1  illustrates one embodiment of a modified round robin configuration. 
       FIG. 2  is an interface timing diagram of one embodiment of a modified round robin sequence. 
   

   DETAILED DESCRIPTION 
   In recognition of the above-stated problems associated with conventional resource allocation schemes, embodiments for a modified round robin approach are described. This modified round robin approach provides equal access opportunity to all resources while enabling a substantial decrease in time to perform the round robin cycle. Consequently, for purposes of illustration and not for purposes of limitation, the exemplary embodiments are described in a manner consistent with such use, though clearly the invention is not so limited. 
   A modified round robin configuration  100  according to an embodiment of the invention is illustrated in  FIG. 1 . Each request, in the round robin configuration  100 , whether interactive or batch, is queued to a first-in first-out (FIFO) buffer. In the illustrated embodiment, there are N requests, some of which are interactive requests (x) and others are batch requests (N-x). As long as the FIFO buffer is not empty, information in the buffer may indicate a request. 
   In the illustrated embodiment, to prevent the idle gap between granting of the next request and ending of the current request, each FIFO has an ALMOST-EMPTY flag to indicate that the FIFO buffer has only one item left in the request. Hence, when the ALMOST-EMPTY flag is on, granting of the request goes to the next available request in the round robin sequence by setting a grant selection register (GSR) for the next available request. Therefore, by granting the request one sequence in advance of the depletion of items in the current request FIFO buffer, the idle gap between requests may be prevented. Furthermore, this back-to-back granting-of-request mechanism requires substantially low overhead because an existing pointer for the FIFO buffer may be used as the ALMOST-EMPTY flag. In one embodiment, each of the ALMOST-EMPTY flags is coupled to a read/write pointer. 
   The above-described improved granting sequence is implemented using logic gates J, K, and L to set a grant bit in the corresponding grant selection register (GSR). Thus, logic NAND gate J asserts its output (a logical 1) when either the ALMOST_EMPTY flag is not set or the current grant bit is not set. Logic AND gate K is asserted when the request is initiated and the mask bit of the corresponding mask register (MR) is set while logic gate J is asserted. Finally, logic AND gate L sets the grant bit of the corresponding grant selection register when the logic gate K is asserted but logic gates corresponding to other grant bits are not asserted. Further, as soon as the grant bit is set, the SET_MASK flag for the batch requests is de-asserted. 
     FIG. 2  is an interface timing diagram of a modified round robin sequence according to an embodiment of the invention. The sequence has three resource allocation requests. The first two requests are batch requests A and B. The third request is an interactive request C having two items D and E. Signals GrantA and GrantB indicate that the service is granted to the batch request B right after the granted batch request A is completed. No idle gap is shown in the timing diagram. 
   Referring to  FIG. 1 , to allow the interactive requests to preempt the batch request, the mask bit of the currently granted batch request remains active until the request is emptied. Furthermore, the mask bit of the interactive request is implemented by permanently asserting the corresponding mask bit. Thus, the interactive request is made non-maskable. If an interactive request is made during the granted period of a batch request, the batch request is suspended until the interactive request is serviced. Once the interactive request has been serviced, the suspension of the batch request may be resumed. Therefore, the preemptive arbitration circuit not only generates a short response time but also allows the interrupted request to recover. 
   The above-described preemptive arbitration sequence is implemented using logic gates X and Y, and the mask register (MR). For this sequence, the mask bits of the corresponding interactive requests of the mask register (MR) are set to one. The mask bits of the corresponding batch requests are controlled as follows. Logic AND gate X is asserted when the request is initiated and the mask bit of the corresponding mask register (MR) is set. Logic OR gate Y is asserted when logic gate X is asserted or when SET_MASK flag is asserted. Assertion of logic gate Y sets the corresponding mask bit of the mask register (MR) to one and allows the batch request to resume the interrupted sequence, or sets the corresponding mask bit of the MR to zero when service for the current request is done. The mask bit plus the grant priority order flows right to left with respect to  FIG. 1 . 
   GrantC signal (corresponding to the interactive request) in the interface timing diagram of  FIG. 2  illustrates that the service is granted to interactive request C one cycle after item D in request C presented the request. When item D is removed, the suspended request B is resumed. When item E in request C is presented, the service is again granted to interactive request C. When item E is removed, the suspended request B is again resumed. 
   There has been disclosed herein embodiments for a modified round robin configuration which includes an improved granting sequence and a preemptive arbitration scheme. The improved granting sequence enables short response time to requests by substantially reducing any idle time between requests. This sequence uses an existing pointer to provide an indication of an “almost empty” buffer. The preemptive arbitration scheme allows interactive requests to preempt the batch request. Furthermore, the scheme also enables the batch request to recover from the interruption. 
   While specific embodiments of the invention have been illustrated and described, such descriptions have been for purposes of illustration only and not by way of limitation. Accordingly, throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the embodiments may be practiced without some of these specific details. For example, although the improved round robin configuration of  FIG. 1  uses logic gates to perform the above-described sequences, other comparable circuits and/or elements that perform similar functions may be used. In other instances, well-known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow.