Abstract:
A solid state oscillator circuit for operation at very high frequencies includes a field effect transistor having an input network connected between its gate and source electrodes and an output network connected between its drain and source electrodes, the input and output networks each including three discrete capacitors connected in a &#34;pi&#34; configuration, the input and output networks being connected in series with one another, and an inductor being connected in parallel with the series connected networks, the equivalent circuit impedance of the networks in series and the inductance determining the operating frequency of the oscillator circuit, and the relative ratio of impedance of the networks determining the amount of oscillator feedback.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to oscillator circuits, and more particularly, to a very high frequency oscillator circuit exhibiting improved stability. 
     The highest frequency of oscillation of a semiconductor oscillator is theoretically limited only by the characteristics of the semiconductor device that is used in the oscillator circuit. However, in practice, many other constraints apply. One such constraint is the inability to physically construct a circuit that can meet the circuit constants needed to support the desired frequency of oscillation. In many cases, it is impractical to fabricate the main inductive frequency determining element to a low enough value to satisfy the resonant frequency equations. Another problem concerns itself with minimizing the series inductance of the various capacitive and other circuit elements. If these unavoidable parasitic inductive elements are not small enough compared to the main frequency determining inductance, then unstable or unpredictable operation results. 
     Another problem with high frequency oscillator operation is that circuit capacitances must be reduced as the operating frequency is increased. The limiting case is usually when all capacitances are eliminated until only the semiconductor internal capacitances and the unavoidable stray capacitances remain. Under these conditions, the circuit is unstable with changes in temperature or/and supply voltage as no temperature compensating elements are present. It is improbable that device to circuit match or that feedback would be optimum. 
     It would be desirable then to have a high frequency oscillator circuit having a high enough frequency determining inductance to allow repeatable fabrication. It would further be desirable to have very high frequency oscillator characterized by a high ratio of main inductance to parasitic circuit inductance. It would also be desirable to have a very high frequency oscillator which enables compensation for temperature changes in circuit operation, and which is characterized by the capability of adjusting circuit feedback and circuit match to both the input and output ports of the active element of the oscillator circuit. 
     SUMMARY OF THE INVENTION 
     The present invention provides a solid state oscillator circuit for operation at very high frequencies, said oscillator circuit comprising an active element having an input port and an output port, bias means connected to a control electrode of said active element for establishing the operating point for said active element; an inductance; an input network coupling said inductance to said input port of said active semiconductor element; an output network coupling said inductance to said output port of said active element; said input and output networks each including a plurality of discrete capacitive elements, said input and output networks being connected in series with one another, and said inductance being connected in parallel with said series connected input and output networks, whereby the equivalent circuit impedance of said input and output networks in series and said inductance determine the operating frequency of the oscillator circuit, and the relative ratio of impedance of the input and output networks determining the amount of oscillator feedback. 
     In accordance with the invention, the use of a plurality of discrete capacitors enable selection of almost any desired degree of feedback match and ratio of circuit inductance to capacitance. Moreover, the temperature coefficients of the capacitors of the two networks are selected to compensate for individual input and output temperature characteristics of the active element. 
     In accordance with a further aspect of the invention, the circuit construction lends itself to improved physical construction providing for low series inductance of the matching frequency determining capacitances, for example. Moreover, the circuit is capable of operating with a high degree of stability at a very low voltage in the order of 3 volts with low frequency shift. Frequency shifts are in the order of or less than 1% at an operating range of over 400 MHz. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a data transmission system including a transponder which incorporates the high frequency oscillator circuit provided in accordance with the present invention; 
     FIG. 2 is a schematic circuit diagram of the high frequency oscillator circuit provided by the present invention; and 
     FIG. 3 is a simplified representation of a physical construction of the oscillator circuit. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, the oscillator circuit of the present invention is described with reference to an application in a data transponder in a data transmission system 10. In such system, a plurality of data transponders are provided, each associated with a different data source, such as transponder 11 for data source F1, transponder 12 for data source Fn, etc. The data transmission system provides automatic readout of data which is provided by the data sources F1, . . . Fn, which may be data indicating devices such as registers of utility meters, business machines, etc. 
     A radio link is established between the transponders 11, 12 and an interrogate source 13 which may be fixed or located within a mobile vehicle. The interrogate source 13 transmits an interrogate signal to the transponders, and each transponder responds to the interrogate signal to generate a reply signal representing, for example, the current reading of the register of its associated functional device and transmit the reply signal back to the interrogate source 13. The interrogate signal is coded to represent a unique serial number or address for each of the transponders to permit selected readout of the information registered by the associated functional device. 
     Each transponder, such as transponder 11, comprises a receiver 14 and a transmitter 15 both which are diplexed to an antenna 16. The transmitter 15 includes the oscillator 20 circuit provided by the present invention. The receiver 14 includes a bandpass filter 21 and a detector 22. The transponder also includes a processor 25 which interfaces the transmitter 15 and receiver 14 with an encoder 26 associated with the functional device F1, and the processor controls the operation of the transponder including verification of the incoming interrogate signal and enabling of the transmitter to operate in the transmission of the data provided by functional device F1. 
     In the transponder receiver 14, the bandpass filter 21 has its input connected to the antenna 16 and its output connected to the detector 22. The bandpass filter 21 defines the response frequency band for the receiver 16 which is centered at 451 MHz in the exemplary embodiment. The oscillator 20 of the transmitter is operated at a voltage controlled oscillator having a center frequency of 414 MHz in this example. This signal is FM modulated with a binary encoded FSK signal supplied over input 28 by the processor 25 as a modulating drive signal for the voltage controlled oscillator 20 representative of the data to be transmitted to the interrogate source 13. The processor 25 also activates the transmitter, extending a bias voltage B+ to input 29. 
     Briefly, in operation, each transponder is assigned a serial number or address which allows it to be uniquely addressed by the interrogate source 13. The interrogate source generates an interrogate signal by amplitude modulating the 451 MHz transmitter carrier with a digital code signal to represent the address of the transponder to be interrogated. The receiver 14 detects the incoming amplitude modulated signal, recovering the low frequency digital information. 
     The processor 25 processes the incoming digital signals and when a valid interrogate signal is received and the received serial number code corresponds to that assigned to the transponder, the processor 25 controls the transmitter 15 in transmitting the reading of the register associated with the data source F1. The transmitter 15 replies with a 414 MHz carrier modulated with a binary encoded FSK signal. Modulation frequencies of 45.45 kHz and 50.00 kHz are used to represent binary values of &#34;0&#34; and &#34;1&#34;, respectively, with each bit having a 360 microsecond duration. 
     Referring now to FIG. 2, the oscillator circuit 20 of the present invention will now be described. The oscillator circuit 20 includes an active element 31 embodied as a dual-gate MOSFET 31 having an associated bias network 32, an input network 33 and an output network 34. The oscillator circuit further includes a tuning stage 35 and a modulating input stage 36. The MOSFET 31 may be the type BF-960 double gate MOSFET, commercially available from Seimens. 
     The bias network 32, sets the operating point for the MOSFET 31 and includes resistors 41 and 42 which are connected in series between the DC power input B+ and a point of reference potential. In accordance with a feature of the invention, the DC bias voltage may be low level, 4 volts in this embodiment. The junction of the two resistors 41 and 42 is connected to the gate electrode G1 of the MOSFET 31 which has its other gate electrode G2 connected directly to receive bias B+ over input 29 when activated by the processor 25. The MOSFET 31 has its source electrode 55 connected to the point of reference potential and its drain electrode connected through high frequency choke inductor 43 to B+ input. Inductor 43 isolates the high frequency signals from the DC bias source. 
     Input network 33 comprises three capacitors 45, 46 and 47 which are connected as a &#34;pi-network&#34; between gate G1 of the MOSFET and point A. Capacitor 46 also prevents the application of the positive supply voltage directly to the gate G1. 
     The output network 34 comprises three capacitors 48, 49 and 50 which are connected as a &#34;pi-network&#34; between the drain electrode D of the MOSFET 31 and point B. An inductor 35 is connected between points A and B and is thus coupled to the input and output circuits of the MOSFET 31 through networks 33 and 34. 
     The equivalent circuit impedance of the input and output networks 33, 34, in series (point A to point B) in conjunction with inductor 35 determines the frequency of oscillation which is 414 MHz in the exemplary embodiment. 
     In addition, the values of capacitors 45-47 of the input network 33 are selected to effect the desired degree of match between the input of the MOSFET 31 and the tank inductance provided by inductor 35. Similarly, the values of capacitors 48-50 of the output network 35 are selected to effect the desired degree of match between the output of the MOSFET 31 and the tank inductance. Capacitor 45, which is connected between gate G1 and the point of reference potential, parallels the input capacitance (gate-to-source) of the MOSFET 31. Capacitor 48, which is connected between the drain D, the point of reference potential, parallels the output capacitance (drain-to-source) of the MOSFET 31. The input network 33 defines the feedback path for the oscillator circuit. 
     As indicated above, in operation, the 414 MHz base frequency is frequency modulated with a binary encoded signal using modulating frequencies of 45.45 kHz and 50.00 kHz to represent logic &#34;0&#34; and logic &#34;1&#34;, respectively. 
     The modulating circuit 36 includes a varactor diode 61, a capacitor 62 and a resistor 63. The varactor diode 61 may be the type BB105B, commercially available from Seimens. The varactor diode 61 is connected in series with capacitor 62 between the point of reference potential and the junction of inductor 35 and the output network 36 at point B, and through resistor 63 to the modulating drive input terminal 28, the source of modulating signals provided by the processor 25. 
     Capacitor 62 decouples the DC bias for the oscillator circuit from the varactor diode 61. In transmission operation, the processor 25 provides a serial pulse train to modulating drive input 28 and thus to varactor diode 61 varying the junction capacitance of the varactor diode 61 causing the oscillator frequency to vary, providing frequency modulation indicative of the data provided by the data source F1 via its encoder 26 and the processor 25 (FIG. 1). 
     The output of the oscillator circuit 20 is coupled to the antenna 16 through a coupling coil 71 which is connected to the antenna through a load coil 72. The coupling coil 71 also connects to a tap of the receiver input coil 73 which operates as an auto transformer, coupling the interrogate source 13 interrogate signals to the receiver. The output of the coil 73 is coupled to a detector coil 74 which couples the incoming signal to the input of diode detector 22. Capacitors 75 and 76 comprise a filter circuit for the antenna input circuit to the receiver. 
     In the oscillator circuit 20, the values of the six capacitances 45-50 can be selected to provide almost any desired degree of feedback, match, and L/C ratio. Also, of equal importance, the temperature coefficients of the six capacitances 45-50 can be selected to compensate for the individual input and output temperature characteristics of the MOSFET 31, the feedback versus temperature requirements of the oscillator circuit, and the temperature characteristics of the remaining circuit elements including inductor 35. 
     The value and temperature coefficient of capacitor 62 of the modulating network 36 is chosen to adjust the capacitance versus control voltage characteristic and the capacitance versus temperature characteristic of the network. Furthermore, the selection of capacitors 45-50 can be made to obtain the desired frequency versus temperature versus control voltage characteristics. The varactor diode network shown connected from point B to ground, could also be connected from point A to ground, or from point A to point B. 
     In one oscillator circuit constructed and operated in accordance with the present invention, the electrical elements had the following values: 
     capacitor 45: 4.7 picofarads 
     capacitor 46: 2.7 picofarads 
     capacitor 47: 4.7 picofarads 
     capacitor 48: 4.7 picofarads 
     capacitor 49: 4.7 picofarads 
     capacitor 50: 4.7 picofarads 
     capacitor 62: 2.2 picofarads 
     resistor 41: 47K ohms 
     resistor 42: 10K ohms 
     resistor 63: 10K ohms 
     inductor 35: 0.04 microhenries 
     inductor 43: 0.03 microhenries 
     In a realization of the oscillator circuit having the component values indicated above, operating at a center frequency of approximately 414 MHz, the following results were achieved: 
     
         ______________________________________           Low    Medium   High______________________________________Bias (vdc)        +3.0     +4.0     +4.5Center frequency (MHz)             413.947  414.085  414.13620 DB BW at 50 kHz (MHz)             .95      1        1.02CW output into 30 ohms (dbm)             -5       -1       1.02Mod. output into 30 ohms             -14      -9.5     -8(dbm)______________________________________ 
    
     The frequency drift was in the order of 100 kHz for a 75° temperature rise from the ambient level. The frequency as the result of variation in the bias supply in the range of 3 volts to 4.5 volts, was 189 kHz. 
     In accordance with a further feature of the invention, the described circuit lends itself to improved physical construction so that the above characteristics can be obtained in a practical manner. Referring to FIG. 3, capacitors 45, 47, 48 and 50 are metalized disc capacitors which are soldered directly to the upper surface 81 of a supporting metallic ground plane 80 and positioned at four corners of a rectangle. The MOSFET 31 is mounted on the ground plane 80 between capacitors 48 and 45 with its drain D and gate G1 leads connected to capacitors 48 and 45, respectively, its sources soldered to the ground plane and its gate G2 connected to a terminal 29&#39; on one side of shielded conductor 30 which extends through the ground plane locating bias input terminal 29 at the backside of the ground plane 80. Resistor 41 is connected between terminal 29&#39; and capacitor 45 and resistor 42 is connected between capacitor 45 and the ground plane. 
     Capacitors 46 and 49 are small disc type capacitors with their leads connected between respective capacitors 45 and 47 and 48 and 50. Inductor 35 is connected between points A and B, in parallel with capacitors 47 and 50, and the hf choke oil 43 is connected between capacitor 48 and terminal 29&#39;. Diode 61 has its anode soldered to the ground plane 80. Capacitor 62, which is a small disc capacitor, is connected between the cathode of varactor diode 61 and capacitor 50. Resistor 63 is connected between the cathode of varactor diode 61 and a terminal 28&#39; of shielded conductor 64 which extends through the ground plane and locates modulating drive input terminal 28 at the backside thereof. 
     This physical construction provides for very low series inductance of the matching and frequency determining capacitances as well as convenient physical mounting points for the MOSFET 31 and the inductor 35. In addition, this construction controls the location of capacitors 45, 47, 48 and 50 providing a circuit configuration characterized by repeatable fabrication.