Abstract:
Disclosed herein is a method for forming a semiconductor device that stacks an etched layer and a first hard mask layer on a semiconductor substrate, patterns the first hard mask layer in a high density region and a low density region, using a first exposure mask, forms a first spacer on a sidewall of the first hard mask layer in the high density region, forms a second spacer on a sidewall of the first hard mask layer in the low density region at the same time, etches an end with the first spacer connected thereto using a second exposure mask to thereby form a first spacer pattern, forms a planarized second hard mask layer that exposes the first spacer pattern and the second spacer, removes the first spacer pattern and the second spacer such that the second hard mask layer is left, and etches the etched layer using the second hard mask layer as an mask. This method makes it possible to easily form a micro pattern in the high density region and the low density region.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    Priority to Korean patent application No. 10-2008-0085301, filed on Aug. 28, 2008, the disclosure of which is incorporated herein by reference in its entirety, is claimed. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to a method for forming a semiconductor device, and more particularly, to a technique for forming a contact hole or a bar-type pattern in a high density region and a low density region in a memory device such as a DRAM and a flash memory device. 
         [0003]    In general, a lithography process, which is carried out in a process for forming a semiconductor device, uses a mask to form a circuit and design structure. Many problems occur due to a shrunk pattern size required for high integration of the semiconductor device. 
         [0004]    It is difficult to form a pattern in a size smaller than the resolution limit of a lithography device employed. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    Various embodiments of the invention are directed to provide a method for forming a semiconductor device to form a micro pattern capable of overcoming a resolution limit, using a Spacer Patterning Technique (SPT). 
         [0006]    According to an embodiment of the present invention, a method for forming a semiconductor device comprises: providing a target substrate a target substrate including a high density region and a low density region; forming an underlying layer and a first hard mask layer on the target substrate; patterning the first hard mask layer in the high density region and the low density region using a first exposure mask, the first exposure mask comprising a first exposure pattern formed in a first region corresponding to the high density region and a second exposure pattern formed in a second region corresponding to the low density region, the second exposure pattern and the first exposure pattern having different widths from each other; forming a first spacer on a sidewall of the first hard mask layer in the high density region and a second spacer on a sidewall of the first hard mask layer in the low density region at the same time; etching an end with the first spacer connected thereto using a second exposure mask to form a first spacer pattern; forming a planarized second hard mask layer that exposes the first spacer pattern and the second spacer; removing the first spacer pattern and the second spacer such that the second hard mask layer is left; and etching the underlying layer using the second hard mask layer as an etch mask. 
         [0007]    Preferably, the method further comprises forming an antireflection film over the first hard mask layer. 
         [0008]    Preferably, the first exposure pattern and the second exposure pattern may be contact hole patterns or bar patterns. 
         [0009]    Preferably, the contact hole patterns may have an elliptical shape. 
         [0010]    Preferably, a pitch of the second exposure pattern in the low density region may be less than that of the first exposure pattern in the high density region. 
         [0011]    Preferably, a first spacer may be formed on a sidewall of the contact hole in the high density region, and a second spacer fills the contact hole in the low density region. 
         [0012]    Preferably, the first spacer and the second spacer may be formed of insulating material or conductive material. 
         [0013]    Preferably, the first and the second exposure patterns on the first exposure mask may be light transmitting patterns. 
         [0014]    Preferably, the planarized second hard mask layer may be formed by a CMP process or an etchback process. 
         [0015]    Preferably, the first and second exposure masks may be a binary mask, a phase shift mask or a half tone phase shift mask. 
         [0016]    According to an embodiment of the present invention, a photomask for forming contact holes on a semiconductor device comprising: a first exposure mask comprising a first exposure pattern formed in a region corresponding to a high density region of the semiconductor substrate, and a second exposure pattern formed in a region corresponding to a low density region of the semiconductor substrate, the first exposure pattern and the second exposure pattern having different pitches from each other; and a second exposure mask comprising a third exposure pattern overlapping with at least some portion of the first exposure pattern, and a fourth exposure pattern substantially covering the low density region. 
         [0017]    Preferably, the pitch of the second exposure pattern in the low density region may be less than that of the first exposure pattern in the high density region. 
         [0018]    According to another embodiment of the present invention, a method for forming a semiconductor device comprises providing a target substrate including a high density region and a low density region; forming an underlying layer and a first hard mask layer over the high density region and the low density region of the target substrate; patterning the first hard mask layer over the target substrate to form a first hard mask pattern in the high density region and a second hard mask pattern in the low density region, the second hard mask pattern having a pitch that is less than a pitch of the first hard mask pattern; forming a second hard mask layer over the first hard mask pattern and the second hard mask pattern so that the second hard mask layer is filling an opening defined by the second hard mask pattern; patterning the second hard mask layer to form a first spacer on the sidewall of the first hard mask pattern and a second spacer filling in between neighboring second hard mask pattern; providing a third hard mask layer into an opening defined by the first spacers and an opening defined by the second spacers; removing the first spacer and the second spacer to obtain a third hard mask pattern in the high density region and a fourth hard mask pattern in the low density region; and patterning the underlying layer using the third and the fourth hard mask patterns to form a first contact hole in the high density region and a second contact hole in the low density region. 
         [0019]    Preferably the method further comprises tailoring the first spacer into a given shape and size using the second exposure mask. 
         [0020]    Preferably, the first hard mask pattern and the second hard mask pattern may be a contact hole pattern or a bar pattern. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIGS. 1 to 3  are plane views illustrating exposure masks used in a method for forming a semiconductor device according to a first embodiment of the present invention; 
           [0022]      FIGS. 4   a  to  4   m  are plane views and sectional views illustrating the method for forming the semiconductor device according to the first embodiment of the present invention; 
           [0023]      FIGS. 5 and 6  are plane views illustrating exposure masks used in a method for forming a semiconductor device according to a second embodiment of the present invention; and 
           [0024]      FIGS. 7   a  to  7   i  are sectional views illustrating the method for forming the semiconductor device according to the second embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0025]    Hereinafter, a method for forming a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented into different forms. These embodiments are provided only for illustrative purposes and for full understanding of the scope of the present invention by those skilled in the art. In the following description, same drawing reference numerals are used for the same elements. 
         [0026]      FIGS. 1 to 3  are plane views illustrating exposure masks used in a method for forming a semiconductor device according to a first embodiment of the present invention. 
         [0027]      FIG. 1  illustrates a first exposure mask  100  designed to form a contact hole in a high density region (numeral  1000  of  FIGS. 4   a  to  4   m ), where a light shielding region  110  and a light transmitting region  120  defining a contact hole are formed on a transparent substrate. 
         [0028]    Referring to  FIG. 1 , the first exposure mask  100  forms a light shielding pattern, e.g., a chrome pattern, in the light shielding region  110  on a quartz substrate which is a transparent substrate. 
         [0029]      FIG. 2  illustrates a second exposure mask  200  designed to form a contact hole in a low density region (numeral  2000  of  FIGS. 4   a  to  4   m ), where a light shielding region  210  and a light transmitting region  220  made of a transparent substrate are formed. 
         [0030]      FIG. 3  is a plane view illustrating a third exposure mask  300 , where a light shielding region  310  is configured to shield a specific portion of the contact hole in the high density region formed using the first exposure mask  100  and the contact hole in the low density region. 
         [0031]    Referring to  FIG. 3 , the light shielding region  310  is formed so as to shield the central portion of the contact hole positioned in the high density region. 
         [0032]    Accordingly, the light shielding region  310  is configured in a line pattern running across the center of the first contact hole formed in the high density region ( 1000  of  FIGS. 4   a  to  4   m ) and the entire low density region (numeral  2000  of  FIGS. 4   a  to  4   m ). 
         [0033]      FIGS. 4   a  to  4   m  illustrate the method for forming the semiconductor device according to the first embodiment of the present invention, where the lower figures are sectional views taken along line {circle around (a)}-{circle around (a)} of the top figures. In  FIG. 4   h,  the upper figure is a plane view, the middle figure is a sectional view taken along line {circle around (a)}-{circle around (a)} of the plane view, and the lower figure is a sectional view taken along line {circle around (b)}-{circle around (b)} of the plane view. A high density region  1000  and a low density region  2000  are shown in each figure. 
         [0034]    Referring to  FIG. 4   a,  an underlying layer  12 , a first hard mask layer  14 , an anti-reflection film  16  and a first photoresist film pattern  18  are formed on a semiconductor substrate  10 . Here, the first photoresist film pattern  18  is formed by an exposure and development process using the first exposure mask  100  of  FIG. 1  so as to form a contact hole in the high density region  1000 . 
         [0035]    Referring to  FIG. 4   b,  the anti-reflection film  16  and the first hard mask layer  14  are etched using the first photoresist film pattern  18  as a mask to form a first hard mask layer  14 , thereby exposing the etched layer  12 . Then, the first photoresist film pattern  18  and the anti-reflection film  16  are removed. 
         [0036]    Referring to  FIG. 4   c,  a spacer  20  is formed on a sidewall of the first hard mask layer  14 . Specifically, a thin film such as insulating material and conductive material is formed on the high density region  1000  and the low density region  2000 , and anisotropically etched to form the spacer  20 . The insulating film may include an oxide material, a nitride material, or a stack thereof. 
         [0037]    Referring to  FIG. 4   d,  the first hard mask layer  14  is removed. The spacer  20  remains on the underlying layer  12 . The spacer  20  is formed in the light transmitting region  120  of the first exposure mask  100  of  FIG. 1 . 
         [0038]    Referring to  FIG. 4   e,  a second photoresist film pattern  22  is formed on the high density region  1000  and the low density region  2000 . Here, the second photoresist film pattern  22  is formed by an exposure and development process using the second exposure mask  200  of  FIG. 2  so as to form a contact hole in the low density region  2000 . 
         [0039]    Referring to  FIG. 4   f,  the underlying layer  12  is etched using the second photoresist film pattern  22  as a mask to form the first contact hole  24  exposing the semiconductor substrate  10 . Here, the first contact hole  24  is formed in the low density region  2000 , i.e., an independent region. 
         [0040]    Referring to  FIG. 4   g,  the second photoresist film pattern  22  is removed. The spacer  20  still remains in an elliptical shape in the high density region. 
         [0041]    Referring to  FIG. 4   h,  a third photoresist film pattern  26  is formed on the high density region  1000  and the low density region  2000 . The third photoresist film pattern  26  is formed by an exposure and development process using the third exposure mask  300  of  FIG. 3  to shield the line region running across the center of the spacer  20  in the high density region  1000  and to shield the entire low density region  2000 . As a result, the spacer  20  in an elliptical shape is divided into two independent spacer  20 . 
         [0042]    Referring to  FIG. 4   i,  the third photoresist film pattern  26  is removed. 
         [0043]    Referring to  FIG. 4   j,  a second hard mask layer  28  is formed on the high density region  1000  and the low density region  2000 . Thereafter, the second hard mask layer  28  is subject to planarization process until the spacer  20  is exposed. The planarization process may be implemented with a CMP process or an etchback process. 
         [0044]    Referring to  FIG. 4   k,  the exposed spacer  20  is removed, thereby obtaining a second hard mask  28   
         [0045]    Referring to  FIG. 4   l,  the underlying layer  12  in the high density region  1000  is etched using the second hard mask  28  as a mask, thereby forming the second contact hole  30  exposing the semiconductor substrate  10 . 
         [0046]    Referring to  FIG. 4   m,  the second hard mask  28  is removed. The high density region  1000  is a region where the second contact holes  30  are provided densely, and the low density region  2000  is a region where the first contact hole  24  is provided less densely than in the high density region  1000 . 
         [0047]      FIGS. 5 and 6  are plan views illustrating exposure masks for forming a semiconductor device according to a second embodiment of the present invention. [ 0048 ]  FIG. 5  illustrates a first exposure mask  500  designed to form first contact holes in a high density region (numeral  3000  of  FIGS. 7   a  to  7   i ) on a target substrate and second contact holes in a low density region on the substrate (numeral  4000  of  FIGS. 7   a  to  7   i ). 
         [0048]    Referring to  FIG. 5 , a light shielding pattern  510 , e.g., a chrome pattern, is provided on a transparent quartz substrate to define a light transmitting pattern  520 . Here, the contact hole of the high density region is formed larger than the contact hole of the low density region, such that spacers formed on sidewalls of the first contact holes are spaced apart from each other, and spacers formed on sidewalls of the second contact holes are connected to each other to fill the second contact holes in a process forming a spacer which is a succeeding process. 
         [0049]      FIG. 6  illustrates a second exposure mask  600 , wherein a second light shielding pattern  610  is provided to shield the entire low density region (numeral  4000  of  FIGS. 7   a  to  7   i ) formed using the first exposure mask  500  and the entire low density region ( 4000  of  FIGS. 7   a  to  7   i ). 
         [0050]    Referring to  FIG. 6 , in the second exposure mask  600 , the light shielding pattern  610  is provided to remove the first spacer while leaving its center portion, as shown in  FIGS. 7   e  and  7   f.    
         [0051]      FIGS. 7   a  to  7   i  are sectional views illustrating the method for forming the semiconductor device according to the second embodiment of the present invention, where the figures on the top are plan views of a target substrate and the figures on the bottom are sectional views taken along lines {circle around (x)}-{circle around (x)} of the plan views. In  FIG. 7   e,  the figure on the top is a plan view of a target substrate, the figure in the middle is a sectional view taken along line {circle around (x)}-{circle around (x)} of the plan view, and the figure on the bottom is a sectional view taken along line {circle around (y)}-{circle around (y)} of the plan view. In addition, the high density region on the target substrate is denoted as numeral  3000  and the low density region on the target substrate is denoted as numeral  4000 . 
         [0052]    Referring to  FIG. 7   a,  an underlying layer  52 , a first hard mask layer  54 , an anti-reflection film  56  and a first photoresist film pattern  58  are formed on a semiconductor substrate  50 . Here, the first photoresist film pattern  58  is formed by an exposure and development process using the first exposure mask  500  of  FIG. 5   
         [0053]    Referring to  FIG. 7   b,  the anti-reflection film  56  and the first hard mask layer  54  are etched using the first photoresist film pattern  58  as a mask, thereby forming an anti-reflection film  56  and a first hard mask layer  54   
         [0054]    Referring to  FIG. 7   c,  the first photoresist film pattern  58  and the anti-reflection film  56  are removed. 
         [0055]    Referring to  FIG. 7   d,  a first spacer  60  is formed on a sidewall of the first hard mask layer  54  in the high density region  3000 , and a second spacer  61  filled in between neighboring first hard mask layer  54  in the low density region  4000  is formed. Specifically, a thin film of insulating material and conductive material is provided on the entire surface, and anisotropically etched to form the first and second spacers  60  and  61 . The first spacer  60  is formed on the sidewall of the first hard mask layer  54  in the high density region  3000  in an elliptical shape, and the second spacer  61  is provided to fill a gap between the first hard mask layer  54  in the low density region  4000 . Preferably, the insulating film is formed of an oxide material or a nitride material. 
         [0056]    Referring to  FIG. 7   e,  a second photoresist film pattern  62  is provided on the high density region  3000  and the low density region  4000 . Here, the second photoresist film pattern  62  is formed by an exposure and development process using the second exposure mask  600  of  FIG. 6  to cover the first spacer  60  in an elliptical short axis direction to cover an elliptical long axis direction central portion in the high density region  3000  and to cover the entire low density region  4000 . The first spacer  60  in the high density region  3000  is etched using the second photoresist film pattern  62  as a mask, thereby forming the first spacer  60 . 
         [0057]    Referring to  FIG. 7   f,  the second photoresist film pattern  62  and the first hard mask layer  54  are removed, thereby providing the first spacer  60  on the high density region  3000  and the second spacer  61  on the low density region  4000 . 
         [0058]    Referring to  FIG. 7   g,  a second hard mask layer  64  is formed on the entire surface including the first spacer  60  and the second spacer  61 . Thereafter, the second hard mask layer  64  is subject to planarization process to expose the first spacer  60  and the second spacer  61 . The planarization process is implemented using a CMP process or an etchback process. 
         [0059]    Referring to  FIG. 7   h,  the exposed first spacer  60  and second spacer  61  are removed, thereby obtaining the second hard mask layer  64  formed on the underlying layer  52   
         [0060]    Referring to  FIG. 7   i,  the underlying layer  52  of the high density region  3000  and the low density region  4000  is etched using the second hard mask layer  64  as a mask until the semiconductor substrate  50  is exposed, thereby forming a first contact hole  66  in the high density region  3000  and a second contact hole  68  in the low density region  4000 . 
         [0061]    As an another embodiment of the present invention is applied to a bar-type pattern formed in a high density region and a low density region, respectively. Also, it is possible to combine the second embodiment of the present invention with another embodiment. For example, a bar-type pattern is formed in a high density region and a contact hole is formed in a low density region, or vice versa. 
         [0062]    The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps described herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.