Abstract:
An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.

Description:
BACKGROUND 
       [0001]    The present invention relates to the field of integrated circuit manufacture; more specifically, it relates to an apparatus and a method for manufacture and repair of microelectronic circuits. 
         [0002]    Modern integrated circuits utilize microscopic wiring to interconnect semiconductor devices such as transistors into circuits. Often defects in the wires occur that render the integrated circuit non-functional or unreliable. Additionally, it is very expensive to customize integrated circuits because of the cost of masks. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove. 
       BRIEF SUMMARY 
       [0003]    A first aspect of the present invention is an apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector. 
         [0004]    A second aspect of the present invention is a method, comprising: (a) providing an apparatus including: a vacuum chamber containing a movable stage configured to hold a substrate, an inspection and analysis probe, a heat source; a gas injector and a gas manifold, the gas manifold connecting multiple gas sources to the gas injector; (b) loading a substrate onto the movable stage; (c) scanning the substrate for defects using the inspection and analysis probe; (d) if a defect is found determining if it is (i) a short or extension between wires, (ii) an open or notch in a wire, or (iii) a void in a dielectric layer between the wires; determining a chemical composition of the defect; selecting a gas from the multiple gas sources for repairing the defect; if the defect is a short or extension between wires either laser abating or plasma etching the defect using the selected gas; if the defect is an open or notch in a wire, depositing a conductive material to repair the defect using the selected gas; and if the defect is a void in a dielectric layer between wires, depositing a dielectric material to repair the defect using the selected gas; and (e) repeating steps (c) and (d) until no defects are found. 
         [0005]    A third aspect of the present invention is a method, comprising: (a) providing an apparatus including: a controller and a vacuum chamber, the vacuum chamber containing a movable stage configured to hold a substrate, an inspection and analysis probe, a heat source; a gas injector and a gas manifold, the gas manifold connecting multiple gas sources to the gas injector; (b) loading a substrate onto the movable stage; (c) loading a wiring scheme into the controller; (d) selecting a wiring instruction from the wiring scheme and determining if the instruction is to connect wires or cut wires and selecting a gas from the multiple gas sources; (e) if the instruction is to cut a wire, either laser abating or plasma etching the wire using the selected gas or if the instruction is to connect wires, depositing a conductive material between the wires to connect the wires; and (f) repeating steps (c) and (e) until no there are no further instructions. 
         [0006]    These and other aspects of the invention are described below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
           [0008]      FIG. 1  is a top view illustrating the ablation of a short between two wires according to embodiments of the present invention; 
           [0009]      FIG. 2  is a top view illustrating deposition to repair an open in a wire according to embodiments of the present invention; 
           [0010]      FIG. 3  is a top view illustrating fabrication of custom wiring according to embodiments of the present invention; 
           [0011]      FIG. 4  is a schematic diagram of a first fabrication and repair apparatus according to embodiments of the present invention; 
           [0012]      FIG. 5  is a schematic diagram of a second fabrication and repair apparatus according to embodiments of the present invention; 
           [0013]      FIG. 6  is a schematic cross-section of a nano plasma nozzle of  FIG. 5 ; 
           [0014]      FIG. 7  is a flowchart of a method of repairing an integrated circuit according to embodiments of the present invention; and 
           [0015]      FIG. 8  is a flowchart of a method of custom wiring of an integrated circuit according to embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    The embodiments of the present invention repair defects and form custom wiring having wire widths in the several hundreds of nanometers range using nano plasma deposition and nano ablation. 
         [0017]      FIG. 1  is a top view illustrating the ablation of a short between two wires according to embodiments of the present invention. On the left side of  FIG. 1 , three electrically wires  100 A,  100 B and  100 C are illustrated. A short defect  105  electrically connects wires  100 A and  100 B and an extension defect  106  protrudes from wire  100 C toward  100 B. Wire  100 A has a width W 1 , wire  110 B has a width W 2 , and wire  100 C has a width W 3 . Wire  100 A is spaced a distance S 1  from wire  100 B and wire  100 B is spaced a distance S 2  from wire  100 C. In one example, at least one of W 1 , W 2 , W 3 , S 1  and S 2  are less than one micron. In one example, at least one of W 1 , W 2 , W 3 , S 1  and S 2  are less than 500 nanometers. Wires  100 A,  100 B and  100 C may comprise copper, aluminum, tungsten, titanium, tungsten nitride, titanium nitride or combinations thereof. On the right side of  FIG. 1 , an ablation process has been performed to remove short defect  105  and extension defect  106  leaving behind respective repairs  105 A and  106 A. 
         [0018]      FIG. 2  is a top view illustrating deposition to repair an open in a wire according to embodiments of the present invention. On the left side of  FIG. 2 , three electrically wires  110 A,  110 B and  110 C are illustrated. An open defect  115  electrically breaks wire  110 B, a notch defect  116  exists in wire  110 C and a void defect  117  exists in the dielectric between wires  110 C and  110 B. Wire  110 A has a width W 1 , wire  110 B has a width W 2 , and wire  110 C has a width W 3 . Wire  110 A is spaced a distance S 1  from wire  110 B and wire  110 B is spaced a distance S 2  from wire  110 C. In one example, at least one of W 1 , W 2 , W 3 , S 1  and S 2  are less than one micron. In one example, at least one of W 1 , W 2 , W 3 , S 1  and S 2  are less than 500 nanometers. Wires  110 A,  110 B and  110 C may comprise copper, aluminum, tungsten, titanium, tungsten nitride, titanium nitride or combinations thereof. On the right side of  FIG. 2 , two deposition processes have been performed to form an electrically conductive repair  115 A on wire  110 B, an electrically conductive repair  116 A on wire  110 C and a dielectric repair  117 A between wires  110 C and  110 B. In one example, repairs  115 A and  116 A comprise aluminum, copper or tungsten. In one example, repair  117 A comprise a silicon oxide or silicon nitride. 
         [0019]      FIG. 3  is a top view illustrating fabrication of custom wiring according to embodiments of the present invention. On the left side of  FIG. 3 , three electrically wires  120 A,  120 B and  120 C are illustrated. Wire  120 A has a width W 1 , wire  110 B has a width W 2 , and wire  120 C has a width W 3 . Wire  120 A is spaced a distance S 1  from wire  120 B and wire  120 B is spaced a distance S 2  from wire  120 C. In one example, at least one of W 1 , W 2 , W 3 , S 1  and S 2  are less than one micron. In one example, at least one of W 1 , W 2 , W 3 , S 1  and S 2  are less than 500 nanometers. On the right side of  FIG. 2 , an ablation process has been performed to break wire  120 A into wires  120 A 1  and  120 A 2  and to break wire  120 B into wires  120 B 1  and  120 B 2  by forming openings  125 A and  125 B respectively. Also, a deposition process has been performed to form an electrically conductive connection  125 C between wires  120 A 1  and  120 B 1 , an electrically conductive connection  125 D between wires  120 A 2  and  120 B 2 , and an electrically conductive connection  125 E between wires  120 B 2  and  120 C. In one example, connections  125 C,  125 D and  125 E comprise aluminum, copper or tungsten. In effect, a custom wiring pattern has been formed from wires  120 A,  120 B and  120 C. 
         [0020]      FIG. 4  is a schematic diagram of a first fabrication and repair apparatus according to embodiments of the present invention. In  FIG. 4 , an apparatus  130  includes a vacuum chamber  135  having a vacuum port  135 A, and XYZ stage  140  within the vacuum chamber for holding substrate  145 , an inspection and analysis probe  150 , a gas injector  155  and a heat source  160 . In one example, heat source  160  is a micro-probe or a micro-plasma probe. In the case of a micro-plasma probe, a non-reactive gas source  185 D is supplied. In one example, substrate  145  is a semiconductor substrate (e.g., wafer) commonly used for the fabrication of integrated circuits. Apparatus  130  also includes a main controller  165 , an inspection and analysis controller  170 , a power supply  175 , a gas manifold  180  connected to gas source  185 A,  185 B and  185 C by respective solenoid valves  190 A,  190 B and  190 C. Manifold  180  is connected to gas injector  155 . Controller  165  is also connected to XYZ stage  140  and controls movement of the XYZ stage. The position of gas injector  155  and heat source  160  are adjusted (maybe fixed or movable) to converge the gas stream and laser spot or plasma to the same point on substrate  145 . 
         [0021]    Inspection and analysis probe  150  is connected to inspection and analysis controller  170  and comprises a real time inspection and analysis system configured to scan substrate  145 , recognize defects, and to chemically analyze the composition of any defect found. Inspection and analysis probe  150  comprises a scanning electron microscope (SEM) probe connected to an image recognition system within inspection and analysis controller  170  and an energy-dispersive X-ray (EDX) spectrophotometer probe connected to an EDX module within inspection and analysis controller  170 . By comparing a stored design pattern to the scanned pattern, opens and shorts and other defects (such as notches in wiring that reduce the cross-sectional area of the wire and wire extensions that reduce the space between adjacent wires) can be detected. Additionally, voids in the dielectric layer between wires may be detected. The defect can then be analyzed for chemical composition. Thus the type of defect, its location and its composition (or the composition surrounding the defect) is determined. 
         [0022]    Power supply  175  is connected between heat source  160  and controller  165 . Solenoid valves  190 A,  190 B and  190 C are also connected to controller  165 . When a defect is found by the inspection and analysis system, its type is determined (e. g., open, short, notch, extension, hole), its position is determined, and its composition is determined. For a short or extension, the composition of the defect is determined, for an open or notch, the composition of the wire is determined. Controller  165  then determines the power setting for power supply  175  and which gas to be supplied to gas injector  155  to affect a repair. For example, when heat source  160  is a micro-laser and the defect is a short or extension, the wattage of the laser (based on the size and composition of the defect) is set to ablate the defect. When the heat source is a micro-plasma probe, the radio frequency (RF) voltage, direct current (DC) bias, and inert gas and flow rate are set to sputter etch the defect. An etchant gas may also be supplied to gas injector  155  in which case the defect is plasma or reactive ion etched. When the heat source is a micro-laser and the defect is an open or notch or hole, not only is the wattage of the micro-laser set but also a deposition gas and flow rate is set (based on the size of the open or notch and composition of the wire containing the defect). 
         [0023]    Examples of inert gases include nitrogen, argon and neon. Examples of etchant gases include chloro and fluoro hydrocarbons, oxygen, and hydrogen. Examples of metal deposition gases include aluminum alkyls such as triisobutylaluminum (TIBA) and tri methyl aluminum (TMA), aluminum alkyl hydrides such as dimethylaluminum hydride (DMAH), copper beta-diketonates, copper (II) dialykldithiocarbamate complexes, and tungsten hexafluoride. Additionally, defects in the dielectric between wires may be repaired by deposition of a dielectric material from tetraethylorthosilicate, silane and nitrogen tetra fluoride. 
         [0024]      FIG. 5  is a schematic diagram of a second fabrication and repair apparatus according to embodiments of the present invention.  FIG. 5  is similar to  FIG. 4 , except apparatus  130 A utilizes the separate gas injector  155  and a heat source  160  of  FIG. 4  are replaced with a single micro-plasma nozzle  195  and inert gas source  185 D is connected to manifold  180  by solenoid valve  190 D. Also, power supply  170  of  FIG. 4  is replaced by power supply  175 A which is connected to micro-plasma nozzle  195 . Thus ablation and deposition are performed using only micro-plasma nozzle  195 . 
         [0025]      FIG. 6  is a schematic cross-section of a nano plasma nozzle  195  of  FIG. 5 . In  FIG. 6 , micro-plasma nozzle  195  includes a central axial electrode  200 , a coaxial insulator  205  and a coaxial outer electrode  210 . A coaxial gap  215  between coaxial insulator  205  and coaxial outer electrode  210  also a selected gas or gas mixture from manifold  180  of  FIG. 5  to pass through micro-plasma nozzle  195  to form a plasma  220  above substrate  145 . An RF source from power supply  175  (see  FIG. 5 ) is connected between central axial electrode  200  and coaxial outer electrode  210 . A DC power source  230  from power supply  175  (see  FIG. 5 ) is connected between XYZ stage  140  and coaxial outer electrode  210 . Thus micro-plasma nozzle  195  can perform plasma etching or reactive ion etching or plasma enhanced deposition. 
         [0026]      FIG. 7  is a flowchart of a method of repairing an integrated circuit according to embodiments of the present invention. In step  250 , a semiconductor substrate is loaded onto the stage of the apparatus illustrated in  FIG. 4  or  5  and described supra. In step  255 , the defect inspection scan is started. The wiring structure on the substrate is inspected and any defect found identified using an image recognition system. In step  260 , if a defect is found, the method proceeds to step  265 , otherwise the method proceeds to step  270 . In step  265 , the type of defect is identified, either a short/extension defect or open/notch/void defect. If the defect is a short/extension defect the method proceeds to step  275 . In step  275 , the gas and gas flow that will be used to repair the defect by laser ablation or plasma etching is selected as are the power settings for the laser/plasma heat source or micro-plasma nozzle. In step  280 , the defect is repaired by laser ablation or plasma etching. Next, in step  285 , it is determined if the defect scan is complete. If the scan is complete, the method proceeds to step  270  where the substrate is unloaded, otherwise the method loops back to step  255  and the scan is continued. Returning to step  265 , if the defect is open/notch/void the method proceeds to step  290 . In step  290 , the gas and gas flow that will be used to repair the defect by deposition is selected as are the power settings for the laser/plasma heat source or micro-plasma nozzle. In step  295 , the defect is repaired by deposition of material to bridge the open or fill the notch or void. The method then proceeds to step  285  described previously. 
         [0027]      FIG. 8  is a flowchart of a method of custom wiring of an integrated circuit according to embodiments of the present invention. In step  300 , a semiconductor substrate is loaded onto the stage of the apparatus illustrated in  FIG. 4  or  5  and described supra. In step  305 , the wiring scheme is loaded. Next, in step  310 , the first/next instruction is selected, the stage is moved to the location indicated by the instruction, and the method proceeds to step  315 . In step  315 , the type of instruction is identified, either a wiring connection or a wiring cut. If the instruction is to cut a wire then the method proceeds to step  320 . In step  320 , the gas and gas flow that will be used to cut the wire by laser ablation or plasma etching is selected as are the power settings for the laser/plasma heat source or micro-plasma nozzle. In step  325 , the wire is cut by laser ablation or plasma etching. Next, in step  330 , it is determined if there is another instruction. If there is another instruction, the method proceeds to step  310 , otherwise the method proceeds to step  335  where the substrate is unloaded. Returning to step  315 , if the instruction is to connect wires then the method proceeds to step  340 . In step  340 , the gas and gas flow that will be used to connect the wires by deposition is selected as are the power settings for the laser/plasma heat source or micro-plasma nozzle. In step  345 , the wires are connected by deposition of conductive material. The method then proceeds to step  330  described previously. 
         [0028]    When either the apparatus of  FIG. 4  or the apparatus of  FIG. 5  are used to generate wiring schemes, the inclusion of EDX capability in the apparatus is optional. 
         [0029]    Thus, the embodiments of the present invention provide an apparatus and method for repairing defects and forming custom wiring having wire widths in the several hundreds of nanometers range using nano plasma deposition and nano ablation. 
         [0030]    The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.