Abstract:
A method of forming via plugs in a semiconductor device, comprising the following steps. A semiconductor structure having an upper first oxide layer and at least two metal lines formed on the upper oxide layer are provided. The metal lines are spaced apart a predetermined distance and each having a lower barrier layer, a middle layer, and an upper etch stop layer. A second oxide layer is deposited over the first oxide layer and the pair of metal lines. An etch barrier layer is formed over the second oxide layer. The structure is planarized to form openings in the etch barrier layer over the metal lines. A third oxide layer is deposited and patterned over the planarized structure to form via openings through the etch barrier layer openings to the upper etch stop layers on the metal lines. Metal via plugs are formed in the via openings.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to forming via plugs in semiconductor devices, and more specifically to forming via plugs to borderless structure semiconductor devices. 
     BACKGROUND OF THE INVENTION 
     As the design rule for semiconductor devices constantly decreases, borderless structures, such as contacts, have been begun to be used to permit the further microminiaturization. However, the use of borderless structures requires a level and degree of accuracy in fabricating these devices that is not met to achieve acceptable yields. Misaligned via openings can create metal via plugs formed in contact with sidewalls of metal lines that degrade the electromigration of the metal via plugs. 
     U.S. Pat. No. 5,920,792 to Lin describes an etch stop over an HDP-CVD oxide layer. A first HDP-CVD oxide layer is formed over a metal wiring structure having a gap. A second HDP-CVD oxide layer is formed over the first HDP-CVD oxide layer. The second HDP-CVD oxide layer having lower etching/depositing component ratio, and thus a higher CMP removal rate, than the first HDP-CVD oxide layer. A thin CMP passive layer may be deposited over the second HDP-CVD oxide layer. The thin CMP passive layer having the same etching/depositing component ratio as the second HDP-CVD oxide layer. The structure is chemical-mechanically polished (CMP) wherein: the thin CMP passive layer minimizes dishing in the recessed areas and is removed; the second HDP-CVD oxide layer is polished and removed by CMP until the first HDP-CVD oxide stop layer is reached resulting in an essentially planar surface. 
     U.S. Pat. 5,904,569 to Kitch describes a process of forming self-aligned vias in multi-metal integrated circuits using self-aligned metal pillars to connect metal layers separated by a dielectric. The metal pillars comprise a first aluminum (Al) layer, a middle titanium nitride (TiN) layer that acts as an etch stop layer, and an upper Al layer. 
     U.S. Pat. No. 5,891,799 to Tsui describes a method for making stacked and borderless via structures on multilevel metal interconnections for integrated circuits. 
     U.S. Pat. No. 5,840,624 to Jang et al. describes a method for forming a borderless contact or via hole in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric (ILD) layer during the opening of the borderless contact or via hole in an overlying ILD layer. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures. 
     Another object of the present invention is to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures using etch stop layers over the borderless structures. 
     A further object of the present invention is to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures without the need to mask and etch the SiN etch stop layer. 
     Yet another object of the present invention is to provide a method of forming self-aligned via plugs to borderless structures in semiconductor structures using a self-aligned SiN etch barrier that prevents inter-metal shorts otherwise due to via over-etch. 
     Other objects will appear hereinafter. 
     It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having an upper first oxide layer and at least two metal lines formed on the upper oxide layer are provided. The metal lines are spaced apart a predetermined distance and each having a lower barrier layer, a middle layer, and an upper etch stop layer. A second oxide layer is deposited over the first oxide layer and the pair of metal lines. An etch barrier layer is formed over the second oxide layer. The structure is planarized to form openings in the etch barrier layer over the metal lines. A third oxide layer is deposited and patterned over the planarized structure to form via openings through the etch barrier layer openings to the upper etch stop layers on the metal lines. Metal via plugs are formed in the via openings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the method of forming an liquid crystal display lower substrate according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawing in which like reference numerals designate similar or corresponding elements, regions and in which: 
     FIG. 1 illustrates in cross-sectional representation conventional via plugs formed to a pair of borderless metal wires known to the inventor. 
     FIGS. 2 through 7 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Problem Solved by the Invention 
     FIG. 1 illustrates a conventional via plug structure to borderless metal wires known by the inventor (not to be considered as prior art and not the invention). 
     Semiconductor structure  110  includes an upper silicon oxide layer. Metal lines  112 ,  114  are formed over semiconductor structure  110  and include lower barrier layers  116 ,  118 , middle layers  117 ,  119 , and upper TiN layers  120 ,  122 , respectively. Metal lines  112 ,  114  are spaced apart distance  115  greater than or equal to 0.23 μm. 
     Metal line middle layers  117 ,  119  may be comprised of AlCu or AlSiCu. Lower barrier layers  116 ,  118  may be comprised of Ti, TiN, or Ti/TiN. Upper TiN or Ti/TiN layers  120 ,  122  function as etch stop layers. 
     A second oxide layer  124  is deposited and planarized over semiconductor structure  110  and metal lines  112 ,  114 . 
     A third oxide layer, or intermetal dielectric layer (IMD),  126  is deposited, planarized, and patterned over second oxide layer  124  to form via openings  128 ,  130 . A not uncommon problem is that etching of second oxide layer  124  to form via openings  128 ,  130  may etch through upper TiN layers  120 ,  122  and gouge into middle layers  117 ,  119  of metal lines  112 ,  114 , respectively (not shown) which degrades the electromigration (EM) of metal via plugs  134 ,  136 . This may be caused because variations in the thickness of IMD layer  126  can introduce over-etching during the etching of via openings  128 ,  130 . To reduce variations in via Rc (stopping TiN anti-reflective coating (ARC)  120 ,  122  will result in a higher Rc, more over-etch is introduced to ensure consistency. If oxide is left over the TiN, the via Rc increases. Even a thick TiN layer can increase Via Rc. If an overetch is used to remove all the oxide, the etch goes through the TiN and causes electromigration. 
     Further, as shown in FIG. 1, another problem occurs when, for example, via opening  128  is misaligned and second oxide layer  124  is partially etched exposing part of sidewall  132  of middle layer  117  of metal line  112 . When metal via plugs  134 ,  136  are formed within via openings  128 ,  130 , respectively, metal via plug  134  contacts sidewall  132  of middle layer  117  of metal line  112  which also degrades the EM of metal via plugs  134 . 
     Preferred Embodiment of the Invention 
     The inventor has discovered a process of forming via plugs in semiconductor devices that (1) prevents misaligned via openings from exposing a portion of the sidewalls of the underlying metal lines so that when metal via plugs are formed within the via openings a portion of the metal via plugs do not come into contact with the underlying metal line thus preventing degradation of the EM of the metal via plugs; and (2) permits defining an SiN etch barrier without masking and etching of the SiN etch barrier which greatly simplifies the process. 
     Accordingly as shown in FIG. 2, starting semiconductor structure  10  includes an upper oxide layer and is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer. Unless otherwise specified, all structures, layers, etc. may be formed or accomplished by conventional methods known in the prior art. 
     One or more two metal lines  12 ,  14  are formed over semiconductor structure  10 . If more than one line if formed, the lines are spaced apart a distance  15  greater than or equal to 0.23 μm, and more preferably about 0.3 μm at gap  13 . The upper surface of the semiconductor structure can be a dielectric layer (e.g., interlevel dielectric (ILD) or inter metal dielectric (IMD) layer) composed of an oxide, such as a doped oxide or oxynitride. Metal lines  12 ,  14  include lower barrier layers  16 ,  18 , middle layers  17 ,  19 , and upper etch stop layers  20 ,  22 , respectively. 
     It is obvious to one skilled in the art that even though metal line  12  is shown in FIG. 2 as having a width less than that of metal line  14 , the widths could be reversed, or both metal lines  12 ,  14  may have the same width—either equal to the width of metal line  12  or metal line  14 . 
     Middle layers  17 ,  19  are from about 4500 to 5500 Å thick, and more preferably about 5000 Å thick, and may be comprised of AlSiCu and are more preferably comprised of AlCu. 
     Lower barrier layers  16 ,  18  are from about 180 to 440 Å thick and more preferably from about 200 to 400 Å thick, and may be comprised of Ti or TiN, and more preferably Ti/TiN. Barrier layers  16 ,  18  serve to prevent diffusion of middle layers  17 ,  19  into the upper oxide layer of semiconductor structure  10 . 
     Upper etch stop layers  20 ,  22  are anti-reflective coatings from about 280 to 370 Å thick, and more preferably from about 300 to 350 Å thick, and may be comprised of Ti, Ti/TiN and more preferably a TiN anti-reflective coating. 
     As shown in FIG. 3, one key step of the present invention is that oxide layer  24  is deposited by a non-conformal, high density plasma (HDP) process to a depth just sufficient to fill gap  13  between metal lines  12 ,  14  and may be up to a depth of about 6000 Å. 
     It is critical that an HPD process be used to form the layer  24 . HPD processes include processing with low energy ions with a density equal to or greater than 1E12 cm −2 . HPD process that can be used to form layer  24  include ICP, DPS, electron cyclotron resonance (ECR), SiH 4 /O 2 /Ar, or SiH 4 /O 2 /Ar/SiFe processes. Since the HDP process is non-conformal, the width of peak portions  21 ,  23  of HDP-oxide layer  24  over metal lines  12 ,  14 , respectively, mirror the width of metal lines  12 ,  14 , and are self-aligned over metal lines  12 , 14 , respectively. The importance of which will become evident hereafter. 
     The HDP process may be conducted from about 320 to 370° C., and more preferably about 350° C., using silane and O 2 /Ar. 
     The HPD process is preferably preformed with a deposition to sputter ratio between about 2.0 and 3.0. 
     HDP-oxide layer  24  may comprise HDP-silicon oxide or doped versions thereof such as HDP-PSG or HDP-FSG. 
     As shown in FIG. 4, etch barrier layer  25  is deposited over HDP-oxide layer  24  to a thickness of from about 950 to 1050 Å, and more preferably 1000 Å. Etch barrier layer  25  may be comprised of H-rich silicon nitride or Si-rich silicon nitride and more preferably SiN. 
     SiN etch barrier layer includes lower, flat portions  25   a,  and raised peak portion  25   b  over HDP-oxide peak  21  over metal line  12 , and raised peak portion  25   c  over HDP-oxide peak  23  over metal line  14 . 
     As shown in FIG. 5, an oxide chemical-mechanical polishing (CMP) is then conducted to polish and remove SiN etch barrier layer peak portions  25   b,    25   c  and HDP-oxide peak portions  21 ,  23 , each over metal lines  12 ,  14 , respectively. 
     It is noted that since HDP-oxide peak portions  21 ,  23  are the same width as, and self-aligned over, the underlying metal lines  12 ,  14  openings  27 ,  29  formed by the oxide CMP in SiN etch barrier layer between flat portions  25   a  are also self-aligned over metal lines  12 ,  14 , respectively. The width of SiN etch barrier layer openings  27 ,  29  are slightly less than the width of metal lines  12 ,  14 , respectively, by more than about 5%, and more preferably from about 5 to 10%. 
     As shown in FIG. 6, cap oxide layer  26  is deposited and patterned over oxide layer  24  and SiN etch barrier layer flat portions  25   a  to form via openings  28 ,  30 . Via openings  28 ,  30  are designed to pass through SiN etch barrier layer openings  27 ,  29  and oxide layer  24  to expose TiN layers  20 ,  22  with TiN layers  20 ,  22  acting as etch stop layers. Via openings  28 ,  30  are etched through the cap oxide layer  26  and preferably stop in the TiN layer  22 . A photoresist layer (not shown) may be used to for the via openings. The SiN etch barrier layers  25   a  act as etch guides/stops. The etch preferably stops on the TiN layers  20   22  or within the TiN layers (removing some portion of the TiN layer, but not exposing the underlying metal layer.) 
     If a via opening is misaligned, such as, for example, via opening  28  as shown in FIG. 6, SiN etch barrier layer flat portion  25   a  at  31  is resistant to the via opening  28 ,  30  etch and is not etched. Since openings  27 ,  29  within SiN etch barrier layer are self-aligned over metal lines  12 ,  14  and have a width slightly less than the width of metal lines  12 ,  14  parts  31  of SiN etch barrier layer flat portions  25   a  shield the underlying edges  33  of metal lines  12 ,  14  and the portions of oxide layer  24  there between. 
     Thus the design and process of the present invention eliminates the possibility of a misaligned via opening  28 , for example, from exposing a portion of a sidewall of middle AlCu layer  17  of metal line  12 , for example. 
     As shown in FIG. 7, a metal layer (not shown) is deposited over oxide layer  26 , filling via openings  28 ,  30 , and planarized to form metal via plugs  34 ,  36 . Metal via plugs  34 ,  36  may be comprised of AlCu or Cu, and more preferably tungsten (W). 
     Since any misaligned via opening  28  for example as shown in FIGS. 6 and 7, is barred from penetrating parts  31  of SiN etch barrier layer flat portions  25   a,  metal via plug  34 , for example as shown in FIG. 7, does not contact any sidewall portion of middle AlCu layer  17  of metal line  12 . Thus the electromigration (EM) of W metal via plug  34  is not degraded. 
     In summary, the process of the present invention improves the electromigration of W metal via plugs  34 ,  36  by minimizing or eliminating direct contact between W metal via plugs  34 ,  36  and middle AlCu layer of metal lines  12 ,  14 . 
     While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.