Abstract:
An electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems is disclosed The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode wherein the drive current for the RF switch diode is the same as the current in the PMOS transistor. To compensate for undesirable variations in the RF switch diode, the driver circuitry is designed such that the current in the PMOS transistor is adjusted in an opposite direction to cancel the unwanted variations.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]    Attention is directed to copending application Attorney Reference Number D/A1730, filed herewith, entitled, “Process and Temperature Compensation Circuit for Integrated RF Switching.” The disclosure of this reference is hereby incorporated in its entirety. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    In most RF applications, discrete P-i-N diodes are used in RF switch arrays because they have the correct diode characteristics to operate correctly. However, using discrete P-i-N diodes increases both the size and the cost of the RF switch arrays. Another impact of using discrete P-i-N diodes is that a discrete RC circuit is needed to isolate the P-i-N diode from a driver chip that will be used to drive the P-i-N diode. Therefore, it would be preferable to use integrated diodes in building RF switch arrays but current technological limitations have prevented their use. This is because current CMOS integrated diodes are not capable of sustaining the performance requirements necessary for the RF switch array.  
           [0003]    To solve some of the above stated problems a technique has been found which allows for the fabrication of a CMOS integrated diode, such as that disclosed in U.S. Pat. No. 5,757,065 and assigned to the assignee of the present application. U.S. Pat. No. 5,757,065 entitled HIGH VOLTAGE INTEGRATED CIRCUIT DIODE WITH A CHARGE INJECTING NODE discloses using an injecting node in a CMOS integrated diode for producing diode characteristics more closely resembling the characteristics of a discrete P-i-N diode. Additionally, these integrated P-i-N diodes need electronic driver circuitry for biasing the injecting node for proper switching. The P-i-N diode characteristics, which in turn directly determine the efficiency of RF switching in Acoustic Ink Jet Printing (AIP) systems, are extremely sensitive to temperature and process parameters variations. Therefore what is needed is a design for the driver circuitry such that those inefficiencies due to process parameters and temperatures variations are compensated and canceled out.  
         SUMMARY OF THE INVENTION  
         [0004]    In accordance with the present invention, there is provided an electronic driver circuitry for an RF switch diode used in Acoustic Ink Jet Printing (AIP) systems that compensates and cancels out undesired variations and non-idealities. The electronic driver circuitry consists of a PMOS transistor and a poly resistor used to control the on/off states of the RF switch diode wherein the drive current for the RF switch diode is the same as the current in the PMOS transistor. To compensate for undesirable variations in the RF switch diode, the driver circuitry is designed such that the current in the PMOS transistor is adjusted in an opposite direction to cancel the unwanted variations. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    The objects, features and advantages of the invention will become apparent upon consideration of the following detailed disclosure of the invention, especially when it is taken in conjunction with the accompanying drawings wherein:  
         [0006]    [0006]FIG. 1 is top view of a CMOS integrated circuit diode;  
         [0007]    [0007]FIG. 2 is a cross-sectional view of the CMOS integrated circuit diode shown in FIG. 1 and taken through cross-section line  2 - 2 ; and  
         [0008]    [0008]FIG. 3 is an electrical schematic showing biasing circuitry for the CMOS integrated circuit diode that compensates and cancels out undesired variations and non-idealities according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0009]    Turning now to FIG. 1, a top view of a CMOS integrated circuit diode  8  for use as a RF switch diode in the present invention is shown. FIG. 2 shows a cross-sectional view of the CMOS integrated circuit diode  8  shown in FIG. 1 and taken through cross-section line  2 - 2 . RF switch diodes must have very low on-impedance and at the same time they must have very low capacitance for efficient and fast switching. However, these two parameters contradict each other in that by making the diodes&#39; on-resistance very low, the diode must have a very large area, which increases its capacitance drastically. Regular N+ or P+ integrated CMOS diodes have low breakdown voltages and high capacitance values.  
         [0010]    Referring to FIGS. 1 and 2, adding an injecting node  14  to the integrated diode  8  solves the problem. The RF switch diode  8  itself is a cylindrical device with centerline C. The RF switch diode  8  is constructed by implanting a ring to form an n-well cathode  12  in a substrate comprised of p+ substrate  26  and p− epi  18  leaving a p− epi anode  10  in the center. The n-well cathode  12  is connected to electrically by a n+ metal contact  20 . Using the n+ metal contact  20  the n-well cathode  12  can now be connected to using a metal line  22 . The p− epi anode  10  of the diode  8  created by the n-well cathode  12  is connected to ground via a topside p− epi anode contact  16  shown in FIG. 1. The p+ substrate  26  is connected to ground via a backside wafer contact (not shown). Decreasing the depth of the p− epi  18  increases the capacitance and off impedance, and decreases the breakdown voltage.  
         [0011]    The RF switch diode  8  defines a n+ injecting node  14  forming a broken ring outside of the n-well cathode  12  and separated from it by a portion of the p− epi  18  region. The distance the n+ injecting node  14  is located from the n-well cathode  12  vary depending on what breakdown voltage is desired. The n+ injecting node  14  alters the characteristics of the RF switch diode  8  by biasing the diode in either a forward biased mode or a reverse biased mode during operation of the RF switch diode  8 . When the n+ injecting node  14  is forward biased there is a negative bias on the n+ injecting node  14  as referenced against the p− epi anode  10  and the p− epi  18 . The forward bias on the injecting node  14  injects electrons into both the p− epi  18  and the p− epi anode  10 . The n-well cathode  12  then drops to a voltage of approximately negative 0.7 volts, or 0.7 volts below the p− epi anode  10  and the p− epi  18 , and the diode  8  remains turned on as long as there are electrons in the p− epi  18  and the p− epi anode  10 . The injected electrons from the forward biased n+ injecting node  14  reduce the on-impedance of the Rf switch diode  8 . This biasing and impedance setting feature allows the diode to handle a large RF voltage signal when the diode is turned off and to handle a large RF current signal when the RF switch diode  8  is turned on.  
         [0012]    Referring now to FIG. 3, there is shown electronic driver biasing circuitry for the RF switch diode  8 . The biasing circuitry compensates and cancels out undesired variations and non-idealities according to the present invention. In accordance with the present invention, the injection node contact  24  must be biased properly to turn the RF switch ON or OFF. For the ON situation, the injecting node contact  24  must be biased to a voltage approximately −0.7 volts with respect to the grounded substrate  26  to inject electrons into p− epi  18 . The injected minority carriers reduce the on-resistance more than if the injection node  14  was not available. To turn the diode  8  OFF, the injecting node  14  must be biased to a positive voltage with respect to grounded substrate  18 . Referring once again to FIG. 3, a digital signal is applied to node N 1   76  (ON/OFF control node) which determines the state of the integrated RF switch diode  8 . When this signal is “LOW”, the voltage of the node N 2   36  is positive and diode  8  is OFF. When this signal is “HIGH”, the voltage of node N 2   36  is about −0.7, so the minority carriers are injected into substrate and the integrated RF switch diode  8  is on.  
         [0013]    Turning once again to FIG. 3, the RF switch diode  8  is turned off when the PMOS FET&#39;s M 5   98  and M 6 ,  100  respectively are turned off, thereby allowing no current to flow to the injection node  24 . This is accomplished by applying a zero bias voltage on node N 1   76  which turns on the PMOS FET&#39;s M 2   80  with the NMOS FET M 1   78  in the ON state do to the bias voltage from VPOS  60 . By way of example but not of limitation, the voltage of VPOS  60  is 5 volts. With both M 1   78  and M 2   80  in the ON state, PMOS FET&#39;s M 7   92  and M 8   94  are turned on by the bias voltage supplied by VNEG  74 . With M 7   92  and M 8   94  in the ON state, voltage VHV  90  through resistor  102  allows power to be switched from the RF power source  30  to the transducer  34 . The zero voltage on none N 1   76  turns on M 4   96  providing a positive voltage on node N 3  which turns OFF M 6   100 . The voltage turns OFF the RF switch diode  8 .  
         [0014]    Likewise, the RF switch diode  8  is turned on when the PMOS FET M 6   100  is turned on, thereby allowing current to flow to the injection node  24 . This is accomplished by applying a positive bias voltage (typically 5 volts) on node N 1   76  which turns off the PMOS FET M 2   80 . With M 2   80  in the off state, PMOS FET&#39;s M 7   92  and M 8   94  are not turned on by the bias voltage supplied by VNEG  74 . With M 6   100  in the onON state, the RF switch diode  8  is closed creating a short circuit for the RF signal  30  a path from node  22  to the substrate  18  to ground allowing no power to the transducer  34 .  
         [0015]    Also the positive (5V) voltage on node N 1   76  turns off M 4   96  so there is no large current in resistor RP 184  due to M 4   96 . The small current in RP 1   84  is only provided by transistor M 3   82  such that the voltage of node N 3  is negative (by Vneg  74 ) allowing M 6   100  to be on to provide a current path for RF switch diode  8  which is turned on.  
         [0016]    Therefore, the on-impedance of the RF switch diode  8  can be varied by changing the amount of current injected into the n+ injecting node  14 . When there is no current, the RF switch diode  8  acts as a normal two-terminal diode because there are no injected electrons to reduce the on-impedance. However, as the current into the n+ injecting node  14  rises, more electrons are injected and the on-impedance is lowered. When the n+ injecting node  14  is reverse biased there is a positive bias on the n+ injecting node  14  as referenced against the p− epi  18 . When there is a forward bias on the n+ injecting node  14  no electrons are injected into the p− epi  18 . The RF switch diode  8  then behaves as it normally would, however with the n-well cathode  12  and p− epi  18  doping values the RF switch diode  8  has a low reversed biased capacitance.  
         [0017]    Turning once again to FIG. 3, in the described driver circuitry, a PMOS transistor M 6   100  and resistor RP 1   84  are provided such that when the RF switch diode  8  is on, the current in the RF switch diode  8  is the same as the current in transistor M 6   100 . In accordance with one embodiment of the present invention, the RF switch diode&#39;s  8  current is basically controlled by controlling the current in M 6   100 . The current in M 6   100  itself is controlled by the voltage Vgs (voltage between gate and source) of M 6   100  (which is proportional to the voltage drop across RP 1   84 ), K P  the gain factor and V T  the threshold voltage of PMOS transistor M 6   100 . RP 1   84  is a “Poly” resistor and the voltage drop across it is affected by the value of this resistor and the current through this resistor which is the same current in transistor M 3   82 .  
         [0018]    The values of RP 1   84 , K P  and V T  can vary from one fabricated lot to another and may also be changed due to temperature change and variations in power supply Vpos. These variations can change the current in different RF diode switches  8  and ultimately degrade the switch array uniformity. To compensate for these undesirable variations, the driver circuitry is designed such that the current in M 3   82  and therefore the Vgs voltage and current of M 6   100  (and therefore the current in the RF diode switch  8 ) is adjusted in an opposite direction to cancel the unwanted variations.  
         [0019]    Referring once again to FIG. 3, a second “poly” resistor RP 2   66  is added to compensate for variation in the value of the poly-resistor RP 1   84 . Although during fabrication of the driver circuitry the values of RP 1   84  and RP 2   66  may change drastically due to process or temperature variations. However, their ratio remains almost constant because their variation (increase or decrease) are in the same direction. Therefore, if value of RP 1   84  is increased due to process variations, the value of RP 2   66  will vary by the same rate since it is fabricated on the same wafer. The compensation for the resistance of RP 1   84  by RP 2   66  is due to the connection of PMOS transistor M 10   62  to the PMOS transistor M 3   82 . As shown in FIG. 3., the transistors M 10   62  and M 3   82  form a “Current Mirror” such that current in M 3   82  follows the current in M 10   62 . The transistor M 10   66  is connected to the resistor RP 2   66  through an NMOS transistor M 12   64 . Therefore, an increase in the resistance value of RP 2   66  will cause a decrease in the current i m10  at transistor M 10   62 . Since M 3  is acts as a current mirror, the current in i m3  will also decrease and compensate for an increase in the resistance RP 1   84 . Since the ratio between RP 1   82  and RP 2   66  are always approximately the same, the gate to source voltage Vgs of M 6   100  is always held constant and therefore the current in M 6   100  is constant and therefore the RF switch diode&#39;s  8  current is held constant.  
         [0020]    Turning once again to FIG. 3, a cascaded branch of PMOS transistors  50 ,  52 ,  54  are added to compensate for variations in K P  and V T  in the RF switch diode  8 . Once again during fabrication of the driver circuitry the values of K P  and V T  may change drastically for PMOS transistor M 6   100  due to process or temperature variations. However, cascaded PMOS transistors  50 ,  52 ,  54  will have the same K P  and V T  variations as the K P  and V T  values of M 6   100  due to process variations since they are all fabricated simultaneously on the same wafer. The compensation for the K P  and V T  values of M 6   100  by cascaded PMOS transistors  50 ,  52 ,  54  is due to the connection of PMOS transistor M 13   50  to the PMOS transistor M 11   56 . As shown in FIG. 3., the transistor M 13   50  and M 11   56  also form a “Current Mirror” such that current in M 11   50  follows the current in M 13   50 . If during fabrication, the K P  and V T  values of M 6   100  is increased or decreased, so are all the PMOS transistors  50 ,  52  and  54 . The PMOS transistors  50 ,  52  and  54  may be represented as a branch of resistances Rm in series. When K P  is increased, the Rm&#39;s are decreased resulting in less resistance in the branch and thus an increase in current i m13  at PMOS transistor M 13   50 . Since M 13   50  and M 11   56  act as a current mirror, the current in i m11  will also increase. As shown in FIG. 3, PMOS transistor M 11   56  is connected to PMOS transistor M 10   62  such that the value of the current i m10  is equal to the current i m12  in M 12   64  minus the current i m11  in M 11   62 . Therefore, if the current in i m11  increases, the current in i m10  decreases and as described above, the current i m10  is equal to the current i m3 . With an increase in K P  a resulting decrease in i m3  occurs resulting in a drop of the Vgs across transistor M 6   100  and i m6  once again remains constant and the current in the RF switch diode remains constant.  
         [0021]    Similarly, when V T  is increased, the Rm&#39;s are increased resulting in more resistance in the branch and thus a decrease in current i m13  in PMOS transistor M 13   50 . Current i m13  in M 11   56  will also be decreased resulting in larger current in M 10   62  and thus in M 3   82  which increases the gate voltage of M 6   100  and canceling the effect of increase in V T  such that the current in the RF switch diode  8  remains constant.  
         [0022]    To compensate for variations in the power supply Vpos  60 , a branch of cascaded NMOS transistors  44 ,  46 ,  48  are added to the circuit and connected to the NMOS transistor M 12   64 , as shown in FIG. 3. If the Vpos  60  voltage varies up or down, so does the voltage at node N 4 . The cascaded NMOS transistors  44 ,  46 ,  48  act as a voltage divider circuit such that an increase for example in Vpos  60  results in an increase in the voltage of N 4  and hence the current of transistor M 12   64 . Similarly an increase in current appears at the PMOS transistor M 11   56  due to cascaded PMOS transistors  50 ,  52  and  54  acting as a voltage divider. Since the current i m10  is equal to the current i m11  subtracted from the current im 12 , and the currents are always constant, the current at i m10  will remain constant. When the current at i m3  is constant, Vgs will also be constant and thus the current i m6  and the RF switch diode current will once again be constant.  
         [0023]    Lastly, to compensate for variations in the power supply Vneg  74 , RP 2   66  and M 12   64  play a role. Referring once again to FIG. 3., if the power supply Vneg  74  varies, its variations affects the voltage of node N 3  which changes the current in M 6   100  and thus the current in RF switch diode  8 . For example of the absolute value of the Vneg decreases the voltage of N 3  decreases as well. But the decrease in Vneg increases the current in RP 2  since it is connected to the same Vneg  74 . The increase in this current will increase i m3 , the current in M 3   82  such that the voltage of node N 3  remains constant making the current in M 6   100  and thus the current in RF switch  8  constant.  
         [0024]    As described, the biasing voltage of node N 2  is directly determined by various process parameters which can vary significantly in different process lots. Also, this voltage is affected by temperature and power supply variations. As a result the injecting current and RF diode characteristics are very sensitive to these variations which can drastically degrade the speed and efficiently of RF switching in AEP systems. Lastly, the described technique is applicable to both MOS and bipolar circuitry and to the complement of the circuitry illustrated.  
         [0025]    While there have been shown and described what are at present considered embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims. While the present invention will be described in connection with a preferred embodiment and method of use, it will be understood that it is not intended to it the invention to that embodiment or procedure. On the contrary, it is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.