Abstract:
An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates generally to packaged integrated electronic circuits. More particularly, this invention relates to reducing the number of calibration components required for packaged integrated electronic circuits.  
       BACKGROUND OF THE INVENTION  
       [0002]     External reference components are often used to calibrate the performance of an individual circuit on an integrated circuit (IC). These components include but are not limited to passive components such as resistors, capacitors, and inductors. These components also include but are not limited to active components such as op-amps, voltage regulators, and current regulators. The number of external reference components used to calibrate individual circuits on an IC add to the cost of producing ICs, components, electrical boards, and computer systems. One method used to reduce the cost of producing ICs is to reduce the number of external reference components used to calibrate or test ICs.  
         [0003]     There is a need in the art to reduce the number of components used to calibrate integrated circuits. An embodiment of this invention reduces the number of reference resistors required to calibrate optimal output impedance for off-chip drivers on an IC.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]      FIG. 1  is a drawing of an IC with four external components. Prior Art  
         [0005]      FIG. 2  is a drawing of an IC with eight external resistors. Prior Art  
         [0006]      FIG. 2A  is a schematic drawing of P-type and N-type PVT circuits. Prior Art  
         [0007]      FIG. 3  is a drawing of an example of an IC with one multiplexer and four circuits with one external component.  
         [0008]      FIG. 3A  is a timing diagram illustrating an example of how circuits are connected to an external component.  
         [0009]      FIG. 4  is a drawing of an example of an IC with two multiplexers, two pads, eight PVT circuits and one external resistor.  
         [0010]      FIG. 4A  is a timing diagram illustrating an example of how circuits are connected to an external component. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0011]      FIG. 1  is a drawing of an integrated circuit (IC),  100 , with four external components,  102 ,  104 ,  106 , and  108 . Reference component 1 ,  102 , is used to calibrate the circuit, CKT 1 ,  110  on the IC,  100 . Reference component 2 ,  106 , is used to calibrate the circuit, CKT 2 ,  114  on the IC,  100 . Reference component 3 ,  104 , is used to calibrate the circuit, CKT 3 ,  112  on the IC,  100 . Reference component 4 ,  108 , is used to calibrate the circuit, CKT 4 ,  116  on the IC,  100 . In this example each internal circuit has a separate external component used for calibration.  
         [0012]      FIG. 2  is a drawing of an IC,  200 , with eight external resistors, R 1 , R 2 , R 3 , R 4 , R 5 , R 6 , R 7 , and R 8 . The process-voltage-temperature circuits (PVT), PVT 1 ,  202 , PVT 2 ,  204 , PVT 3 ,  210 , PVT 4 ,  212 , PVT 5 ,  218 , PVT 6 ,  220 , PVT 7 ,  226 , and PVT 8 ,  228 , are described in  FIG. 2A . PVT 1 ,  202 , PVT 3 ,  210 , PVT 5 ,  218 , and PVT 7 ,  226  are N-type PVT circuits,  232 A. The output impedance of the N-type PVT circuit,  232 A, may be adjusted by selecting the appropriate combination of NFETs, MN 1 , MN 2 , and MN 3 . Usually, the desired combination of NFETs, MNl, MN 2 , and MN 3  result in a voltage on node  224 A of VDD/ 2 . When this configuration occurs, the output impedance of the N-type PVT circuit,  232 A, is approximately equal to the resistance of the external resistor, R 1 . One advantage of this configuration is that it helps reduce reflections due to impedance mismatch.  
         [0013]     PVT 2 ,  204 , PVT 4 ,  212 , PVT 6 ,  220 , and PVT 8 ,  228 , are P-type PVT circuits,  230 A. The output impedance of the P-type PVT circuit,  230 A, may be adjusted by selecting the appropriate combination of PFETs, MP 1 , MP 2 , and MP 3 . Usually, the desired combination of PFETs, MP 1 , MP 2 , and MP 3  result in a voltage on node  206 A of VDD/ 2 . When this configuration occurs, the output impedance of the P-type PVT circuit,  2062 A, is approximately equal to the resistance of the external resistor, R 2 . One advantage of this configuration is that it helps reduce reflections due to impedance mismatch.  
         [0014]     In  FIG. 2 , there are also eight pads, PAD 1 ,  206 , PAD 2 ,  208 , PAD 3 ,  214 , PAD 4 ,  216 , PAD 5 ,  222 , PAD 6 ,  224 , PAD 7 ,  230 , and PAD 8 ,  232 . PVT 1 ,  202 , is connected to PAD 1 ,  206 , and PAD 1 ,  206 , is connected to one end,  234 , of resistor, R 1 . PVT 2 ,  204 , is connected to PAD 2 ,  208 , and PAD 2 ,  208 , is connected to one end,  236 , of resistor, R 2 . PVT 3 ,  210 , is connected to PAD 3 ,  214 , and PAD 3 ,  214 , is connected to one end,  238 , of resistor, R 3 . PVT 4 ,  212 , is connected to PAD 4 ,  216 , and PAD 4 ,  216 , is connected to one end,  240 , of resistor, R 4 . PVT 5 ,  218 , is connected to PAD 5 ,  222 , and PAD 5 ,  222 , is connected to one end,  242 , of resistor, R 5 . PVT 6 ,  220 , is connected to PAD 6 ,  224 , and PAD 6 ,  224 , is connected to one end,  244 , of resistor, R 6 . PVT 7 ,  226 , is connected to PAD 7 ,  230 , and PAD 7 ,  230 , is connected to one end,  246 , of resistor, R 7 . PVT 8 ,  228 , is connected to PAD 8 ,  232 , and PAD 8 ,  232 , is connected to one end,  248 , of resistor, R 8 .  
         [0015]      FIG. 3  is a drawing of an integrated circuit (IC),  300 , with one external reference component,  320 . Reference component  1 ,  320 , is used to calibrate the circuits, CKT 1 ,  310 , CKT 2 ,  314 , CKT 3 ,  312 , and CKT 4 ,  316  on the IC,  300  using multiplexer,  318 . Control input,  330 , to the multiplexer,  318 , controls when each circuit is connected to the reference component,  320 .  FIG. 3A  is a timing diagram illustrating an example of how circuits are connected to an external component. In this example, circuit CKT 1  is connected to reference component  1 ,  320 , when control input,  330 , is 00. In this example, circuit CKT 2  is connected to reference component  1 ,  320 , when control input,  330 , is 01. In this example, circuit CKT 3  is connected to reference component  1 ,  320 , when control input,  330 , is 10. In this example, circuit CKT 4  is connected to reference component  1 ,  320 , when control input,  330 , is 11. This example illustrates how the number of external components used for calibration may be reduced. This example also illustrates how the number of pads on an IC may be reduced.  
         [0016]      FIG. 4  is a drawing of an example of an IC with two multiplexers, two pads, eight PVT circuits and one external resistor. The output,  430 , of PVT 1 ,  402 , is connected to an input,  430 , of MUX 1 ,  414 . The output,  432 , of PVT 2 ,  404 , is connected to an input,  432 , of MUX 1 ,  414 . The output,  444 , of PVT 3 ,  410 , is connected to an input,  444 , of MUX 1 ,  414 . The output,  442 , of PVT 4 ,  412 , is connected to an input,  442 , of MUX 1 ,  414 . The output,  434 , of PVT 5 ,  418 , is connected to an input,  434 , of MUX 1 ,  414 . The output,  436 , of PVT 6 ,  420 , is connected to an input,  436 , of MUX 1 ,  414 . The output,  438 , of PVT 7 ,  422 , is connected to an input,  438 , of MUX 1 ,  414 . The output,  440 , of PVT 8 ,  424 , is connected to an input,  440 , of MUX 1 ,  414 . The control input,  446 , selects which output is connected to PAD 1 ,  406 . PAD 1 ,  406 , is connected to an end,  426 , of a reference resistor, R 1 .  
         [0017]     One input of MUX 2 ,  416 , is connected to VDD and another input of MUX 2 ,  416  is connected to GND. Control input,  448 , selects either VDD or GND. The output,  408 , of MUX 2 ,  416 , is connected, to PAD 2 ,  408 . PAD 2 ,  408 , is connected to an end of resistor, R 1 . By selecting the proper combination of control inputs,  446  and  448 , to MUX 1 ,  414 , and MUX 2 ,  416 , a P-type PVT circuit may be calibrated using resistor R 1  connected to GND. By selecting the proper combination of control inputs,  446  and  448 , to MUX 1 ,  414 , and MUX 2 ,  416 , a N-type PVT circuit may be calibrated using resistor R 1  connected to VDD.  
         [0018]      FIG. 4A  is a timing diagram illustrating an example of how PVT circuits are connected to a single external resistor, R 1 . In this example, the output,  430 , of circuit N-type PVT 1 ,  402 , is connected to one end of resistor, R 1 ,  426 , when control input,  446 , is 000. The other end,  428 , of resistor, R 1 , is connected to VDD when control input,  448 , is 0. In this example, the output,  432 , of circuit P-type PVT 2 ,  404 , is connected to one end of resistor, R 1 ,  426 , when control input,  446 , is 001. The other end,  428 , of resistor, R 1 , is connected to GND when control input,  448 , is 1. In this example, the output,  434 , of circuit N-type PVT 5 ,  418 , is connected to one end of resistor, R 1 ,  426 , when control input,  446 , is 010. The other end,  428 , of resistor, R 1 , is connected to VDD when control input,  448 , is 0. In this example, the output,  436 , of circuit P-type PVT 6 ,  420 , is connected to one end of resistor, R 1 ,  426 , when control input,  446 , is 011. The other end,  428 , of resistor, R 1 , is connected to GND when control input,  448 , is 1. This example illustrates how the number of external components used for calibration may be reduced. This example also illustrates how the number of pads on an IC may be reduced.  
         [0019]     The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.