Abstract:
A method and circuits are provided for high speed powerup of an analog reference source, such as used in a direct access storage device (DASD). The high speed powerup circuits for the analog reference source include a biasing current source. Biasing circuitry is provided for establishing a first bias reference voltage level. An enable input is provided for disabling and for enabling powerup of the analog reference source. A transistor switch is coupled between the bias reference voltage level and the analog reference source. The transistor switch is operatively controlled by the enable input for driving the analog reference source and enabling fast powerup of the analog reference source.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the data processing field, and more particularly, relates to a method and circuits for high speed powerup of an analog reference source for use in a direct access storage device (DASD). 
     DESCRIPTION OF THE RELATED ART 
     As channel speeds increase, conventional arrangements of circuit functions can be a limiting factor in overall performance in a direct access storage device (DASD). In the design of new DASDs, the performance requirements are more demanding and faster operation generally is required. 
     A need exists for fast powerup of an analog reference voltage which can be used for generating gate voltages of current sources or base voltages of current sources. 
     SUMMARY OF THE INVENTION 
     A principal object of the present invention is to provide an improved method and circuits for high speed powerup of an analog reference source, such as used in a direct access storage device (DASD). 
     In brief, a method and circuits are provided for high speed powerup of an analog reference source, such as used in a direct access storage device (DASD). The high speed powerup circuits for the analog reference source include a biasing current source. Biasing circuitry is provided for establishing a first bias reference voltage level. An enable input is provided for disabling and for enabling powerup of the analog reference source. A transistor switch is coupled between the bias reference voltage level and the analog reference source. The transistor switch is operatively controlled by the enable input for driving the analog reference source and enabling fast powerup of the analog reference source. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: 
     FIG. 1 is a diagrammatic view of a direct access storage device (DASD) embodying the present invention; 
     FIG. 2 is a schematic diagram representation of a first circuit for high speed powerup of an analog reference source, for example, used in a direct access storage device (DASD) in accordance with the present invention; 
     FIG. 3 is a schematic diagram representation of a second circuit for high speed powerup of an analog reference source in accordance with the present invention; and 
     FIG. 4 is a schematic diagram representation of a third circuit for high speed powerup of an analog reference source in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Having reference now to the drawings, in FIG. 1 there is illustrated a direct access data storage device (DASD) generally designated as  100  including a stack  102  of disks  104  each having at least one magnetic surface  106 . The disks  104  are mounted parallel to one another for simultaneous rotation on and by an integrated spindle and motor assembly  108 . Information on each magnetic disk surface  106  is read from or written to the disk surface  106  by a corresponding transducer head assembly  110  movable in a path having a radial component across the rotating disk surface  106 . 
     Each transducer head assembly  110  is carried by an arm  112 . The arms  112  are ganged together for simultaneous pivotal movement by a voice coil motor (VCM) magnet assembly  114 . Drive signals applied to the VCM magnet assembly  114  cause the arms  112  to move in unison to position the transducer head assemblies  110  in registration with information storage tracks on the disk surfaces  106  where information is written or read. As shown in FIG. 1, an electronics card  116  is mounted together with a base support  118  of DASD  100 . The utility of the present invention is not restricted to the details of a particular DASD construction. 
     Referring now to FIG. 2, there is shown a first circuit for high speed powerup of an analog reference source, for example, used in the direct access storage device (DASD)  100 , generally designated by the reference character  200  and arranged in accordance with the present invention. In accordance with features of the invention, a capacitive loaded reference node labeled REFERENCE, is biased to a set reference voltage level by circuit  200 . The set reference voltage level is established to provide fast powerup of an ANALOG REFERENCE node when an ENABLE signal is invoked. 
     First high speed powerup circuit  200  includes a plurality of current source N-channel field effect transistors (NFETs) T 202 , T 204 . A gate input of each of the multiple current source NFETs T 202 , T 204  is connected to the drain of a N-channel field effect transistor NFET T 206 . The gate input of the NFET T 206  is connected to an enable input labeled ENABLE of the first high speed powerup circuit  200 . The NFET T 206  is operatively controlled by the enable input. The NFET T 206  is turned on with a high enable input and turned off with a low enable input. First high speed powerup circuit  200  includes a capacitor C 1  connected between the reference node labeled REFERENCE and ground for proper phase margin in the reference loop. In conventional arrangements this capacitor C 1  needed for loop stability, hinders the powerup rate of the current sources. 
     First high speed powerup circuit  200  includes a biasing circuitry for biasing the capacitive loaded REFERENCE node to the set reference voltage level. A biasing current source J 1  charges up the capacitor C 1  through the P-channel field effect transistor (PFET)  210 . PFET  210  is turned on with a low gate input indicated at a line POWERUP. The low POWERUP input is applied to the gate input of an NFET  212  that is connected between the REFERENCE node and ground. Biasing circuitry includes a first pair of series connected NFETs  214 ,  216  and a second pair of series connected transistors NFET  218  and a bipolar NPN transistor Q 220 . NFETs  214 ,  216  have a common series connected node connected to the gate of an NFET  218 . NFET  216  is connected to the gate of current source NFETs T 202  and T 204  and to the drain of NFET  206 . The ENABLE input is applied to the gate input of an NFET  214 . The ENABLE input is inverted by an inverter  1  and applied to the gate input of an NFET  216 . The bipolar NPN transistor Q 220  is connected between PFET  210  and NFET  218 . The high ENABLE input turns on NFET  214  with the inverted high ENABLE input holding off NFET  216 . The low ENABLE input holds off NFET  214  with the inverted low ENABLE input turning on NFET  216 . With the inverted low ENABLE input turning on NFET  216 , a feedback path is provided from the ANALOG REFERENCE node to the gate of NFET  218 . 
     The capacitor C 1  biased up to the set REFERENCE voltage level is connected to a source input of a PFET  222  having its gate connected to the ENABLE input. The low ENABLE input turns on the PFET  222  which is held off by the high ENABLE input. The drain of PFET  222  is connected to ground by an NFET  224  having the ENABLE input connected to its gate input. The HIGH enable input applied to the gates of NFETs  224  and  206  turns on the NFETs  224  and  206 . The low ENABLE input holds off the NFETs  224  and  206 . An NFET  226  having its gate connected to the gate of current source NFETs T 202 , T 204  is connected between a powerup helper bipolar NPN transistor  228  and ground. The base of the powerup helper bipolar NPN transistor  228  is connected to the drain of PFET T 222 . The emitter of the powerup helper bipolar NPN transistor  228  is connected to the gate of current source NFETs T 202 , T 204 . 
     NPN transistor Q 228  enables fast operation of the current source NFETs T 202 , T 204  with the capacitor C 1  already biased up and switchable via PFET  222  to the NPN transistor Q 228  to drive the reference gate voltage of current source NFETs T 202 , T 204  or ANALOG REFERENCE source. When the PFET T 222  is disabled or turned off, the biasing circuitry transistor T 214  is enabled, so that the stack of biasing circuitry transistors Q 220 , T 218  is biased up from the current source J 1 . The biasing circuitry transistor T 214  is connecting the drain of transistor T 218  to its gate. Transistor T 218  is connected as an NFET diode. The gate of T 218  is provided at a voltage compatible with the current supplied by current source J 1 . When the PFET T 222  is turned on, then the helper bipolar transistor Q 228  is turned on. The emitter of the helper transistor Q 228  is connected back to the biasing circuitry transistor T 218 , with transistor T 216  now turned on. The feedback bias loop is activated when the ENABLE signal is invoked. 
     FIG. 3 illustrates a second circuit for high speed powerup of an analog reference source generally designated by the reference character  300  and arranged in accordance with the present invention. In FIG. 3, the same reference numbers are used to illustrate identical components of the first and second high speed powerup circuits  200  and  300 . Second high speed powerup circuit  300  includes an NFET T 220  instead of the bipolar Q 220  in the biasing circuit for the REFERENCE node. Second high speed powerup circuit  300  includes an N-channel field effect transistor (NFET) T 228  instead of NPN transistor Q 228  to drive the reference gate voltage of current source NFETs T 202 , T 204 . 
     FIG. 4 illustrates a third circuit for high speed powerup of an analog reference source generally designated by the reference character  400  and arranged in accordance with the present invention. In FIG. 4, the same reference numbers are used to illustrate identical components of the first, second and third high speed powerup circuits  200 ,  300  and  400 . Third high speed powerup circuit  400  includes a plurality of bipolar NPN current source transistors Q 202 , Q 204  each including a respective biasing resistor R 0 , R 1  connected the emitter to ground instead of the NFETs T 202 , T 204  of first and second high speed powerup circuits  200 ,  300  of FIGS. 1 and 2. In the biasing circuitry, NFET  218  is replaced by a bipolar NPN current source transistor Q 218  with a biasing resistor R 2  connected between its emitter and ground. Similarly, the NFET  226  is replaced by a bipolar NPN current source transistor Q 226  with a biasing resistor R 3  connected between its emitter and ground. 
     While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.