Abstract:
A circuit for ensuring ultra-low power relay switching to control an AC load and extend a battery&#39;s lifetime. A control circuit may be designed to work where power is provides at very low duty cycle in that the on-time of applied voltage is quite short compared to its off-time. During the on-time, power such as that from a battery may be consumed to drive the circuit but overall such consumption of power is almost miniscule, for instance, a few microamperes or less from a three volt battery. An input FET may drive a pair switching FETs that provide pulses to a transformer which provides a ramp of voltage that remains above zero volts to a pair of AC switch FETs. An output of the AC switch may go to operate relays of a wire saver for operating one or more thermostats.

Description:
BACKGROUND 
       [0001]    The present disclosure pertains to control devices and particularly to devices consuming low amounts of power. 
       SUMMARY 
       [0002]    The disclosure reveals a circuit that may ensure ultra-low power relay switching to control an AC load and avoid much of a reduction of a battery&#39;s lifetime. A control circuit may be designed to work where power is provides at very low duty cycle in that the on-time of applied voltage is quite short compared to its off-time. During the on-time, power such as that from a battery may be consumed to drive the circuit but overall such consumption of power is almost miniscule, for instance, a few microamperes or less from a three volt battery. An input FET may drive a pair switching FETs that provide pulses to a transformer which provides a ramp of voltage that remains above zero volts to a pair of AC switch FETs. An output of the AC switch may go to operate relays of a wire saver for operating one or more thermostats. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0003]      FIG. 1  is a diagram of an AC switch circuit having low power consumption; 
           [0004]      FIG. 2  is a diagram of two AC switches for parallel operation; 
           [0005]      FIG. 3  is a diagram that shows a diagram of a circuit arrangement having two circuits for providing positive and negative portions of an AC waveform to a wire saver; 
           [0006]      FIG. 4  is a diagram revealing some details of the wire saver; and 
           [0007]      FIG. 5  is a diagram of several signals at certain points of the AC switch circuit. 
       
    
    
     DESCRIPTION 
       [0008]    The present system and approach may incorporate one or more processors, computers, controllers, user interfaces, wireless and/or wire connections, and/or the like, in an implementation described and/or shown herein. 
         [0009]    This description may provide one or more illustrative and specific examples or ways of implementing the present system and approach. There may be numerous other examples or ways of implementing the system and approach. 
         [0010]      FIG. 1  is a diagram of an AC switch circuit  10  having low power consumption. A second circuit  20  may also be utilized. A K circuit configuration  30  may use two circuits  10  and  20 , as shown in a diagram of  FIGS. 2 and 3 . Circuit  20  is virtually the same as circuit  10 . Circuit  10  may be regarded as a Y FET. Circuit  20  may be regarded as a G FET. 
         [0011]    Circuit  10 ,  20  may disconnect unused parts from battery power while a load is be turned on by a high side load FET  16  and a low side load FET  19 . As a result, an AC load  35  may be normally on while battery power is cut, and the entire circuit may consume just a few microamperes. 
         [0012]    Circuit  10 ,  20  may work at very low duty cycle, where the on-time is quite short compared to the off-time. During the on-time, battery power may be consumed but such consumption of power may be rather low since the duty cycle is low. During the off-time, a load  35  may be on but the battery power to the load can be cut-off by switch FETs  25  and  26  of package  37  (FDMC89521L), and the load may consume only leakage current, i.e., few microamperes. A supply voltage on conductor  18  for circuit  10  may operate in a range from 2.0 Vdc to 5.0 Vdc. FETs  16  and  19  of package  36  (FDC6321C) may be used as a load switch. A P-channel FET  16  may be placed in a high side of the load and an N-channel FET  19  may be placed in a low side of the load, respectively. FETs  16  and  19  may be controlled by an N-channel FET  14  (2N7002) and turned on and off simultaneously in less than 3.3 microseconds every 100 milliseconds by an input switching signal  38  ( FIG. 5 ). The switching signal to the FET  14  and consequently to FETs  16  and  19  may be provided by a micro-processor or timer. Two N-channel FETs  25  and  26  (FDMC89521L) may be placed in package  37  as an AC switch for AC load  35 . 
         [0013]    Both positive and negative AC waveforms may pass through AC switch FETs (FDC89521L) while package  36  (FDC6321C) is turned off. A 68 micro-henry dual power inductor (SDQ12-680-R) or transformer  21  may be used as a load. Inductor  21  may isolate the battery power and AC load  35 . Inductor  21  may work with a flyback switching topology. Total power consumption may be measured to be less than two microamperes while AC switch  37  (FDMC89521L) stays on. 
         [0014]    A “K” circuit  30  that uses field effect transistors (FETs)  43  and  44  may be noted. A thermostat wire saver  41  (i.e., a Honeywell™ THP9045A wiring module with K circuitry) may be used with a thermostat that needs a 24 volt common wire but does not have one. The thermostat may work with a multiplexer which consists of two relays and two diodes mounted on the thermostat. But a relay may switch off so slowly that the K circuitry switches stay on for about two seconds. After this, the load may run continuously after another load runs. The present circuit may use MOSFETS (FETs) which can handle large voltage and current much faster than a relay. The circuit may insure that when the switch circuit is off, the load stops virtually instantly. 
         [0015]    There may be a reliability increase with a MOSFET switching circuit used lieu of a relay circuit. The MOSFET circuit switching time appears to be much faster than that of a relay. When a FET is turned on, the load may run virtually instantly. When the FET is turned off, the load may stop virtually instantly. 
         [0016]      FIG. 2  is a diagram that shows separate circuits  10  and  20 .  FIG. 3  is a diagram that shows a diagram of a circuit arrangement  30  incorporating circuits  10  and  20 .  FIG. 4  is a diagram that illustrates a connection of wire saver  41  relative to circuits  10  and  20 . There may be one or more additional circuits that resemble circuits  10  and  20 , as shown in  FIGS. 1-4 . 
         [0017]    When a Y FET  10  is switched on, the following may occur. If an N-channel FET  43  (2N7002) is switched on, 24 VAC pulses may appear on the drain of FET  43 . However, the positive 24 VAC pulses may be blocked by diode  45  and just the negative 24 VAC pulses appear on a K line  47  of wire saver  41 . The pulses may enable a relay on the wire saver  41 , such as a K2 relay  51  may be enabled in that the contacts close. In the meanwhile, a K1 relay  52  may be disabled because the 24 VAC negative pulses are being blocked by a body diode of FET  44 . Also, the negative pulses may be blocked by diode  54 . Relays  51  and  52  of wire saver or circuit  41  are shown in a diagram of  FIG. 4 . 
         [0018]    When a G FET  20  is switched on, the following may occur. The N-channel FET  44  (2N7002) may be switched on and 24 VAC pulses may appear on the drain of FET  44 . But the negative 24 VAC may be blocked by diode  46  and just the positive 24 VAC pulses may appear on K line  47  of wire saver  41 . The positive pulses may enable a K1 relay  52  on the wire saver  41 , and the G relay may be enabled in that the contacts close. In the meanwhile, the K2 relay  51  may be disabled because the 24 VAC positive pulses are being blocked by the body diode of FET  43 . The positive pulses may also be blocked by diode  53 . 
         [0019]    When both Y FET  10  and G FET  20  are switched on, the following may occur. If FET  43  and FET  44  are switched on and 24 VAC pulses appear on the drains of FET  43  and FET  44 , and both positive and negative 24 VAC pulses appear on K line  47  of wire saver  41 , both K1 relay  52  and K2 relay  51  may be enabled in that both sets of contacts close. A K1 relay  52  may provide a G output. A K2 relay  51  may provide a Y output. 
         [0020]    When both Y FET  10  and G FET  20  are switched off, the following may occur. When both Y and G FETs  10  and  20  are switched off, then both FET  43  and FET  44  may be switched off, and no 24 VAC pulses will appear on K line  47  of wire saver  41 . Both K1 relay  52  and K2 relay  51  may be disabled in that both sets of contacts are open. 
         [0021]    When just FET  44  is on, then a waveform  55  may appear on line  47  and turn on relay  52  in wire saver  41 . When just FET  43  is on, then a waveform  56  may appear on line  47  and turn on relay  51 . When FET  44  and FET  43  are on, then a waveform  57  may appear on line  47  and turn on relay  52  and relay  51 . Waveforms  55 ,  56  and  57  are shown in  FIG. 4 . 
         [0022]    When wire saver  41  is not in use, there may be a 24 VAC load relay  51  output Y relative to circuit  10 . When wire saver  41  is not in use, there may be a 24 VAC load relay  52  output G relative to circuit  20 . 
         [0023]    Examples for relay out connections may be noted. As to “Relay out-G” from component  52  in  FIG. 4 , a blower relay in a furnace may be connected to G. Activating the blower relay may turn a blower on when 24 VAC appears at the relay out-G terminal. As to “Relay out-Y” from component  51 , a compressor/condenser fan relay in a furnace may be connected to Y. Activating a compressor relay may turn a compressor on when 24 VAC appears at the relay out-Y terminal. 
         [0024]    To reiterate,  FIG. 1  is a diagram of circuit  10 ,  20 . The present system may have two of these circuits which may be noted as  10  and  20  for Y and G channels, respectively, and referred to as Y FET and G FET, respectively, in  FIG. 3 . An input signal may go to a terminal  12 . An example of the input signal may be a signal  38  as shown in  FIG. 5 . Signal  38  may be a low duty cycle square wave signal having a 3.3 volt magnitude for a time width of 5 microseconds and a zero volt magnitude for 50 milliseconds per cycle period. A ground or reference  15  may be at zero volts. 
         [0025]    Signal  38  may proceed from terminal  12  through a 10 ohm resistor  13  and on to a gate of an N-channel FET  14 . A 100 k ohm resistor  15  may be connected between the gate of FET  14  and a ground  15 . The source of FET  14  may be connected to ground  15 . The drain of FET  14  may be connected a gate of a high side P-channel FET  16  and to a one end of a 2.26 k ohm resistor  17 . The other end of resistor  17  may be connected to conductor  18  for connection to a positive terminal of a battery. A negative terminal of the battery may be connected to ground  15 . There may be a 0.1 microfarad capacitor  48  connected from conductor  18  to ground  15  ( FIG. 3 ). The positive terminal of battery may be connected to a source of FET  16 . The gate of FET  14  may be connected to a gate of a low side N-channel FET  19 . A source of FET  19  may be connected to ground  15 . 
         [0026]    A drain of FET  16  may be connected to a dot-end of a first winding (i.e., primary side) of a transformer  21 . A drain of FET  19  may be connected to a non-dot end of the first winding of transformer  21 . A signal  39  shown in  FIG. 5  may appear across the first winding of transformer  21 . Signal  39  may begin at zero volts go to 3.3 volts when signal  38  goes from 3.3 volts to zero volts almost instantly. Signal  39  may stay at 3.3 volts for a short duration and then decline to zero volts over a period of time much before the next cycle begins. 
         [0027]    A non-dot end of a second winding (i.e., secondary side) of transformer  21  may be connected to an anode of a diode  22 . A 100 picofarad capacitor  23  may be connected across the terminals of diode  22 . A cathode of diode  22  may be connected to one end of a 15 ohm resistor  24 . The other end of resistor  24  may be connected to a gate of an N-channel FET  25  and a gate of an N-channel FET  26  via a gate conductor  29 . A signal  42  shown in  FIG. 5  may appear on gate conductor  29 . Signal  42  may begin at zero volts and then rise almost instantly to 8 volts at the beginning of the first rise of signal  39  to 3.3 volts. When signal  42  reaches 8 volts it may gradually decline down to 5 volts and then rise almost instantly to 8 volts when signal  39  again goes up to 3.3 volts. The pattern of signals  38 ,  39  and  42  may continue until drive signal  38  is removed from terminal  12 . 
         [0028]    A dot-end of the second winding of transformer  21  may be connected to sources of FET  25  and FET  26  along conductive line  49 . A 0.01 microfarad capacitor  27  may have one end connected to the gates of FETs  25  and  26  and the other end connected to the dot-end of the second winding of transformer  21 . A 10 mega ohm resistor  28  may have one end connected to the gates of FETs  25  and  26  and the other end connected to the dot-end of the second winding of transformer  21 . Two zener diodes  31  and  32  may have their cathodes connected to the gates of FETs  25  and  26  and their anodes connected to the dot-end of the second winding of transformer  21 . The windings of transformer  21  may have a one-to-one turn&#39;s ratio. A drain of FET  25  may be connected as an AC output  33  of AC load  35 . A drain of FET  26  may be connected to an AC input  34  of AC load  35 . 
         [0029]    FET  14  may be a 2N7002 N-Channel enhancement mode device. FETs  16  and  19  may be in a package  36  of dual N and P channel logic level enhancement mode FETs having a model no. FDC6321C. FETs  25  and  26  may be in a package  37  of a dual N-channel MOSFET having a model no. FDMC89521L. The noted FET products may be those of Fairchild Semiconductor Corporation. Transformer  21  may have a model no. SDQ12-680-R that is a Coiltronics™ product. Diode  22  may have a model no. 1N914BWS that is a product of Fairchild Semiconductor Corporation. 
         [0030]    To recap, a mechanism for low power consumption load switches, may incorporate a switch having an input terminal for a low duty cycle signal having a duty cycle of less than ten percent, and having an output terminal for connection to a voltage supply, a dual switch having a first input terminal connected to the output terminal of the single switch, a second input terminal connected to the input terminal of the single switch, and having first and second output terminals, respectively, a transformer having a first end of a primary winding connected to the second output terminal of the dual switch, a second end of the primary winding connected to the first output terminal of the dual switch, and having a first end and a second end of a secondary winding, and an AC switch having a first terminal connected to the first end of the secondary winding of the transformer, a second terminal connected to the second end of the secondary winding of the transformer, and having third and fourth terminals. The third and fourth terminals of the AC switch may be for connection to a load. 
         [0031]    The low duty cycle signal may incorporate a series of pulses. 
         [0032]    A signal appearing across the first and second ends of the primary winding of the transformer, may start at a trailing edge of each pulse of the low duty cycle signal, with an initial maximum magnitude and, within a period of time less than a width of a pulse of the low duty cycle signal, may ramp down to zero. 
         [0033]    A signal appearing at the first terminal of the AC switch may start at a leading edge of the signal appearing across the first and second ends of the primary winding of the transformer, then rise to a first voltage and then ramp down to a second voltage, where the signal at a next leading edge of the signal appearing across the first and second ends of the primary winding of the transformer, may then rise to the first voltage and then ramp down to the second voltage at a next leading edge of a next signal appearing across the first and second ends of the primary winding of the transformer, in a repetitive manner as long as the low duty cycle signal appears at the input of the signal switch and the voltage supply is provided at the output terminal of the single switch. 
         [0034]    An amount of current from the voltage supply may range from one-tenth microampere to one milliampere for a control current at the load greater than ten milliamperes. 
         [0035]    An approach for low power switching of a load, may incorporate providing an input FET for receiving a low duty cycle signal having a duty cycle of less than ten percent and for connection to a supply voltage, to be switched in accordance with the low duty cycle signal, connecting an input of a high side FET to an output of the input FET, connecting an input of a low side FET to a terminal for receiving the low duty cycle signal, connecting a first end of a primary winding of a transformer to an output of the low side FET, connecting a second end of the primary winding of the transformer to an output of the high side FET, connecting a first end of a secondary winding of the transformer to an input of a first AC switch FET and an input of a second AC switch FET, connecting a second end of the secondary winding of the transformer to a first terminal of the first AC switch FET and a first terminal of the second AC switch FET, and connecting a second terminal of the first AC switch FET and a second terminal of the second AC switch FET to an AC load. 
         [0036]    The input FET may incorporate a gate for receiving the low duty cycle signal. The input FET may incorporate a drain for connection to the supply voltage and as an output of the input FET. The high side FET may incorporate a gate as the input connected to the output of the input FET. The low side FET may incorporate a gate as the input connected to the terminal for receiving the low duty cycle signal. The low side FET may incorporate a drain as the output of the low side FET. The high side FET may incorporate a drain as the output of the high side FET. The first AC switch FET may incorporate a gate as the input of the first AC switch FET. The second AC switch FET may incorporate a gate as the input of the second AC switch FET. The first AC switch FET may incorporate a source as the first terminal of the first AC switch FET. The second AC switch FET may incorporate a source as the first terminal of the second AC switch FET. The first AC switch FET may incorporate a drain as the second terminal of the first AC switch FET. The second AC switch FET may incorporate a drain as the second terminal of the second AC switch FET. 
         [0037]    The input FET may be an N-channel device. The high side FET may be a P-channel device. The low side FET may be an N-channel device. The first AC switch FET may be an N-channel device. The second AC switch FET may be an N-channel device. 
         [0038]    The low duty cycle signal, incorporating pluses, may have a duty cycle less than five percent. A signal appearing across the first and second ends of the primary winding of the transformer, may begin at a trailing edge of each pulse of the low duty cycle signal, with an initial maximum magnitude and after a period of time less than a period of time of a width of pulse of the low duty cycle signal, ramp with a decline to a minimum magnitude. 
         [0039]    A signal appearing on an input of the first AC switch FET may start at a leading edge of the signal appearing across the first and second ends of the primary winding of the transformer, rise to first voltage and then decline to a second voltage, where a next leading edge of a signal appearing across the first and second ends of the primary winding may rise to the first voltage and then decline to the second voltage at a next signal appearing across the first and second ends of the primary winding, in a repetitive manner as long as the low duty cycle signal is being received by the input FET, and connection to the supply voltage is provided at the input FET. 
         [0040]    An amount of current from the supply voltage may range from one-tenth microampere to one milliampere for a control current of ten milliamperes or greater at the AC load. 
         [0041]    A load switch system may incorporate an input interface, a signal conditioner and driver connected to the input interface, an inductive load connected to the signal conditioner and driver, and an AC switch connected to the inductive load. A signal to the input interface may have a duty cycle less than ten percent. 
         [0042]    The input interface may incorporate a transistor having an input for receiving the signal. The signal conditioner and driver may incorporate a dual channel circuit. The inductive load may incorporate a transformer. The AC switch may incorporate a dual transistor AC switch. 
         [0043]    The dual channel circuit may have a first input connected to an output of the transistor, and a second input connected to the input of the transistor. The transformer may have a first end of a primary winding connected to a first output of the dual channel circuit and a second end of the primary winding connected to a second output of the dual channel circuit. The dual transistor AC switch may have a first common terminal connected to a first end of a secondary winding of the transformer, a second common terminal connected to a second end of the secondary winding of the transformer, and a first output and second output connected to an AC load. 
         [0044]    The input of the transistor may be for the signal having a duty cycle. The output of the transistor and the first input of the dual channel circuit may be for connection via a resistor to a battery voltage. A first common terminal of the dual channel circuit may be for connection to a battery voltage. A common terminal of the transistor and a second common terminal of the dual channel circuit may be for connection to a ground having a zero voltage reference. 
         [0045]    The duty cycle may be less than one-tenth percent. 
         [0046]    The transistor may be an N-channel FET. The dual channel circuit may incorporate a P-channel FET and an N-channel FET. The dual transistor AC switch may incorporate a first N-channel FET and a second N-channel FET. 
         [0047]    The input of the transistor may incorporate a gate of a FET. The output of the transistor may incorporate a drain of the FET. The first input of the dual channel circuit may incorporate a gate of a first FET. The first common terminal of the dual channel circuit may incorporate a source of the first FET. The common terminal of the transistor may incorporate a source of the FET. The second common terminal of the dual channel circuit may incorporate a source of a second FET. The first output of the dual channel circuit may incorporate a drain of the first FET. The second output of the dual channel circuit may incorporate a drain of the second FET. 
         [0048]    A load switch system may further incorporate a diode connected in series between the second common terminal of the dual transistor AC switch and the second end of the secondary winding of the transformer. 
         [0049]    The second common terminal of the dual transistor AC switch may incorporate first and second gates of a first FET and a second FET, respectively, of the dual transistor AC switch. The first common terminal of the dual transistor AC switch may incorporate a first source and second source of the first FET and the second FET, respectively, of the dual transistor AC switch. The first output and the second output connected to the AC load may incorporate a first drain and second drain of the first FET and the second FET, respectively, of the dual transistor AC switch. 
         [0050]    In the present specification, some of the matter may be of a hypothetical or prophetic nature although stated in another manner or tense. 
         [0051]    Although the present system and/or approach has been described with respect to at least one illustrative example, many variations and modifications will become apparent to those skilled in the art upon reading the specification. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the related art to include all such variations and modifications.