Abstract:
Synchronizing multiple-phase data converters by exchanging terminal count pulses via a bidirectional link. Multiple-phase data converters such as analog to digital converters (ADCs) or digital to analog converters (DACs) are synchronized to operate at the same phase by exchanging terminal count (TC) pulses and capturing counter state, representing a time offset from TC. Time offset and the symmetrical delay introduced by the link are used to solve for the delay introduced by the link and the off-set between devices. The offset information is used to align the devices. The process may be repeated to correct for drift.

Description:
TECHNICAL FIELD 
     Embodiments in accordance with the present invention relate to data converters, and more specifically, to synchronizing multiple-phase data converters. 
     BACKGROUND 
     High-speed data converters such as analog to digital converters (ADCs) and digital to analog converters (DACs) are the building blocks bridging analog and digital domains. 
     High speed ADC and DAC system often employ an architecture which decomposes the desired signal into N phases. Such a decomposition allows a converter to run at an overall clock frequency F c                 where each phase runs at a reduced frequency of F clk /N. Each of the N phases are appropriately interleaved to construct the desired fall rate (F c           signal.
     When multiple devices are used in a system, there is commonly a need to synchronize the multiple devices so that at any given time each device is operating at the same phase. Each of the devices may be separated by a significant distance, for example, 10 feet. Sending a synchronization signal to all devices is a possible solution, but suffers from transport delay effects. 
     What is needed is a way to synchronize multiple-phase data converters. 
     SUMMARY OF THE INVENTION 
     Synchronization of multiple-phase data converters is achieved by exchanging counter states between multiple devices across a bidirectional link. Terminal count conditions are signaled on the bidirectional link, and the other device captures its counter state, representing a time offset from the terminal count. Counter state information is exchanged and used to solve for the offset between devices and the delay introduced by the link. The offset information is used to align the clocks. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a first system diagram as known to die art, 
         FIG. 2  shows a second system diagram, 
         FIG. 3  shows a timing diagram, and 
         FIG. 4  shows a third system diagram. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1  is a system diagram showing multiple devices as known to the art. Synchronization source  100  sends a signal along cable  110  connecting devices  120  and  130 . Due to the propagation delay along cable  110 , the signal from source  100  arrives at device  120  at time T 1 , and arrives at device  130  at a later time T 2 . The difference between these times is attributable to signal propagation effects through cable  110 , and thwarts precise synchronization. 
     In an embodiment of the present invention as shown in  FIG. 2 , data converter  200  in a first device and data converter  300  in a second device are interconnected by a symmetrical bidirectional link  400 : symmetrical meaning that the delay between a signal transmitted by data converter  300  and reception of said signal by data converter  200  is identical to the delay between a signal transmitted by data converter  200  and reception of said signal by data converter  300 . Data converters  200  and  300  are multi-phase. The number of phases used in data converters  200  and  300  are the same, represented as N. Converters  200  and  300  each contain a divide-by-N counter to support the decomposition into N phases, shown as counters  210  and  310 . 
     According to an embodiment of the present invention, these counters are interconnected by a symmetrical bidirectional link  400 . When counter  210  reaches its terminal count condition (TC 1 ), it sends a pulse along link  400  to counter  310 . When counter  310  receives this pulse, it captures the state of its counter (C 2 ). 
     Similarly, when counter  310  reaches its terminal count (TC 2 ), it sends a pulse along link  400  to counter  210 . When counter  210  receives this pulse, it captures the state of its counter (C 1 ). 
     Link  400  may be an electrical link such as a circuit board trace, a wire, or a coaxial cable. It may also be an electro-optical link. While link  400  introduces a delay due to the length of the interconnect and propagation through interface elements such as line drivers and receivers, or electro-optical converters, since link  400  is symmetric the delay from counter  210  to counter  310  is the same as the delay from counter  310  to counter  210 , and is represented by TD. 
     When counter  310  captures the state of its counter, it transfers this data to counter  210  via link  410 . This transfer is unidirectional, and is not time-critical. The data representing the captured state of counter  310  may be transferred bit-serial, bit-parallel, or other appropriate method. Link  410  may be a separate unidirectional link such as a wire or optical fiber, or it may be an existing link between devices used to transfer data, such as an Ethernet link between devices, IEEE-1394 link, IEEE-1488 link, USB, or other connection. While link  410  is shown as a separate path, this data could be signaled unidirectional along link  400 . 
     The state of the each counter  210  and  310  can be considered an indication of time. If for example N=32, the divider states are 0, 1, 2, . . . , 31. 
     Define T c             =1/F c           . The counter states then represent times 0, T c           , 2T c            . . .
     According to the present invention, by exchanging TC pulses between counters  210  and  310  and capturing the states of the counters at these times, and transferring one of these captured values to the other counter, we know: 
     (1) TD plus the time offset between TC 1  and counter  310 , and 
     (2) TD minus the time offset between TC 2  and counter  210 . 
     While TD is not known, it introduces the same error into (1) and (2) above. We now have sufficient information to create two linear equations in two unknowns, TD the delay time introduced by link  400 , and TOFF, the offset between counters  210  and  310 . 
     This information is used to adjust the state of one of the two counters, for example, counter  210 , so that counters  210  and  310  are in phase alignment This process may be performed once, such as upon system startup, as part of a self-test or self-calibration sequence initiated on device startup, or by a user command. This process may be performed periodically, such as once per second or once per minute to compensate for device drift, or aperiodically in response to internal or external events or conditions, such as a command in a test script. 
     An example is shown in  FIG. 3 . Assume for example N=8, TOFF=2*T clk , and TD=1*T clk . Assume TC pulses are sent out on link  400  when the counter=0. Counter  210  reaches TC; at that time counter  210  is 0 and counter  310  is 6. The TC pulse from counter  210  reaches counter  310  TD=1 tick later, and counter  310  records C 2 =7. This value is sent via link  410  to counter  210 . When counter  310  reaches TC=0, counter  210  is 2. When the TC pulse from counter  310  reaches counter  210  TD=1 tick later, counter  210  records 3. 
     We now have the following two equations which may be solved at counter  210 :
 
 TD+T OFF= C 2 *T   c             (=7 T   c           
 
 TD−T OFF= C 1 *T   c           (=3 T   c           

     Subtracting the second equation from the first, TD cancels out, yielding:
 
2 *T OFF=4 *T   c              or  T OFF=2 *T   c           

     Counter  210  can now be adjusted by 2 clock periods to be in the same phase as clock  310 . In an alternate embodiment, counter  210  can send a message via link  410  to counter  310  commanding it to adjust its counter by 2 clock periods. 
     While the illustrated embodiment has both counters sampling at the same specified terminal count (TC) value, this is not required. Each counter  210  and  310  may send pulses at any predetermined counter state. If those counter states are not the same between counters  210  and  310 , then the clocks must record their own counter value when the pulse was sent as well as their counter value when the pulse is received. Following the example of  FIG. 3 , counter  310  sends not only its value when it received the pulse from counter  210 , but also its counter value when it sent a pulse to counter  210 . 
     While the present invention is shown operating between two converters, it may be extended to multiple converters by daisy-chaining data converters. Such daisy-chaining requires that each converter have two time-symmetric bidirectional ports. One such port represents a incoming link and the other an outgoing link. Inter-counter communication, link  410  of  FIG. 3 , could be a set of separate links, or a link interconnecting all counters, such as Ethernet, IEEE-1488, or similar data link. 
     An additional embodiment of the present invention is shown in  FIG. 4 . In this embodiment, counters  210  and  310  communicate via symmetric link  400 . In this embodiment, however, both counters send information to correction processor  500  via links  510  and  520 . Correction processor  500 , typically a microprocessor or FPGA, performs the computations outlined above, and sends correction data along link  510  or  520  to counter  210  or  310  to perform clock adjustment. Correction processor  500  must know the number of states N in counter  210  and  310 . This information may be preset in correction processor  500 , or may be transmitted to it via links  510  and  520 . Where both counters  210  and  310  use the same terminal count (TC) value for exchanging pulses, each counter  210  and  310  need only send along links  510  and  520  the value of its counter when the pulse arrived. If counters  210  and  310  do not use the same counter state to send pulses, then they must send this counter state information as well as counter values, as described previously, so that correction processor  500  has enough information to perform the offset calculation. While links  510  and  520  have been shown as separate paths, they may also be implemented as a common path, as an example, a shared Ethernet, IEEE-1488, or similar connection among clocks  210  and  310 , and correction processor  500 . 
     While the embodiments of the present invention have been illustrated in detail, it should be apparent that modifications and adaptations to these embodiments may occur to one skilled in the art without departing from the scope of the present invention as set forth in the following claims.