Abstract:
A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates generally to the processing of computer instructions. More particularly, this invention relates to hardware initiation of emulated instructions. 
       BACKGROUND OF THE INVENTION 
       [0002]    Ideally, computer instructions are executed by hardware resources, which are very fast. However, there are some circumstances in which hardware execution of computer instructions is not possible. For example, a software program may include a new instruction that is intended for a new version of a hardware resource. An old version of the same hardware resource does not implement the new instruction. Therefore, when the old version of the hardware resource tries to execute the new instruction, an exception is taken. In such an event, a software exception handler is invoked to implement the new instruction in software. To support this type of compatibility, the software exception handler must be updated with drivers to emulate new instructions. 
         [0003]    Another common circumstance in which hardware execution of a computer instruction is not possible is in connection with floating point operations. It is not uncommon for a floating point unit hardware designer to decide not to support obscure operations because they require so many hardware resources. Instead, the hardware designer may decide to support obscure operations in software. In such a case, the floating point unit throws an exception in response to a request for an obscure operation. The obscure operation is subsequently emulated in software. 
         [0004]    Another instance in which hardware execution of a computer instruction is not possible is in virtualized environment. Virtualization refers to the creation of a virtual, rather than an actual, version of something, such as a hardware platform, operating system, a storage device or a network resource. For example, a computer that is running Microsoft® Windows® may host a virtual machine that looks like a computer with an Apple® operating system. Subsequently, Apple® compliant software can be executed on the virtual machine. 
         [0005]    In hardware virtualization, the term host machine refers to the actual machine on which the virtualization takes place. The term guest machine refers to the virtual machine. The software or firmware that creates a virtual machine on the host machine is called a hypervisor. 
         [0006]    When an instruction of a guest machine is received by the host machine, an exception is thrown. This results in a call to the hypervisor. The hypervisor looks up the instruction in memory and then executes a software implementation of the function associated with the instruction. Thus, the instruction fault initiates a software call to the hypervisor, which subsequently initiates a memory call to look up the instruction. This sequence of calls is relatively time consuming. Since there are many such calls to a virtual machine, host machine processing is substantially strained. 
         [0007]    This problem of initiating a memory call to look up an unsupported instruction also occurs in the previously discussed examples of unsupported instructions processed by legacy hardware resources and unsupported instructions processed by a floating point unit. In each instance, the memory call consumes many processing cycles and therefore degrades system performance. 
         [0008]    Accordingly, it would be desirable to provide improved techniques for initiating the processing of instructions that are not executed in hardware. 
       SUMMARY OF THE INVENTION 
       [0009]    A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register. 
         [0010]    A machine includes a processor with a fault register to store a fault instruction. A memory is connected to the processor. The memory includes instructions executable by the processor to initiate a software emulated operation with an access to the fault instruction in the fault register. 
         [0011]    A processor includes a fault register to store a fault instruction. An exception handler invokes a software emulated operation utilizing the fault instruction from the fault register. 
         [0012]    A computer readable storage medium includes executable instructions to define a processor. A fault register stores a fault instruction. An exception handler invokes a software emulated operation utilizing the fault instruction from the fault register. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0013]    The invention is more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0014]      FIG. 1  illustrates a computer configured in accordance with an embodiment of the invention. 
           [0015]      FIG. 2  illustrates processing operations associated with an embodiment of the invention. 
       
    
    
       [0016]    Like reference numerals refer to corresponding parts throughout the several views of the drawings. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0017]      FIG. 1  illustrates a computer  100  implemented in accordance with an embodiment of the invention. The computer  100  is a host machine with a central processing unit  110 . The central processing unit  110  includes a configuration register (CR)  111 , a fault register (FR)  113  and an exception handler  115 . The configuration register  111  includes one or more bits to indicate that the computer  100  is configured to support hardware initiation of emulated instructions. For example, the configuration register  111  specifies the presence of the fault register  113 . 
         [0018]    The fault register  113  saves an instruction that has caused a fault. Thereafter, the exception handler  115  initiates a software emulation of operation corresponding to the instruction. This operation is initiated in hardware (e.g., by the fault register  113  and the exception handler  115 ), thus the instruction does not have to be looked up in memory, as is the case in prior art systems. This hardware based invocation of software emulated instructions accelerates processing. 
         [0019]    The computer  100  also includes input/output devices  112 , which are connected to the CPU  110  via a bus  114 . The input/output devices  112  may include a keyboard, mouse, display, printer and the like. A network interface circuit  116  is also connected to the bus  114 . The network interface circuit  116  allows the computer  100  to operate in a networked environment. 
         [0020]    A memory  120  is also connected to the bus  114 . The memory  120  stores a software emulator  122 . The software emulator may be a stand alone module or may be a segment of a larger program, such as a hypervisor, which may be used to implement a guest machine. 
         [0021]      FIG. 2  illustrates processing operations associated with an embodiment of the invention. The CPU  110  fetches an instruction  200 . The CPU  110  subsequently decodes the instruction  202 . It is then determined whether the instruction is implemented in hardware  204 . If so ( 204 —YES), it is determined whether the instruction is allowed in execution mode  206 . If so ( 206 —YES), the instruction is executed  208 . If a Boolean NO state occurs at block  204  or  206 , an exception is signaled  210 . The exception handler  115  then invokes the software emulator  212 . Observe that up to this point all operations are performed in hardware (e.g., by CPU  110 ). After this point, software (e.g., emulator  122 ) controls processing. 
         [0022]    The software emulator  122  reads the instruction from the fault register  214 . Thus, the software emulator  122  does not fetch the instruction from memory  120 , as is the case in the prior art. Instead, the software emulator  122  accesses a hardware resource—the fault register  113 . Therefore, even though the emulation operation is controlled by software (e.g., the emulator  122 ), processing is initiated with hardware—the value in the fault register  113 . This saves many processing cycles. 
         [0023]    The instruction retrieved from the fault register  113  is then decoded  216 . The emulator  122  then determines if emulation is possible  218 . If so ( 218 —YES), the instruction is emulated in software  220 . If not ( 218 -NO), the program is killed  222  or some other remedial action is taken. 
         [0024]    In one embodiment, the fault register  113  is a register that captures the most recent instruction which caused an instruction validity exception, an execution exception or an addressing exception. Example instruction validity exceptions include coprocessor unusable, reserved instruction, guest privileged sensitive instruction, guest field change and guest reserved instruction redirect. Example execution exceptions include integer overflow, trap, system call, breakpoint, floating point, coprocessor 2 exception and hypercall. Example addressing exceptions include address error, Translation Look-aside Buffer (TLB) refill, TLB invalid, TLB read inhibit, TLB execute inhibit and TLB modified. 
         [0025]    In one embodiment, the fault register is only set by exceptions which are synchronous to an instruction. Typically, the fault register is not set by interrupts, machine checks, bus errors, cache error exceptions or EJTAG exceptions. 
         [0026]    When a synchronous exception occurs for which there is no valid instruction word (e.g., TLB Refill—Instruction Fetch), the value stored in the fault register may be labeled UNPREDICTABLE. 
         [0027]    As previously indicated, the presence of the fault register  113  may be indicated by a bit in a configuration register  111 . In one embodiment, the fault register  113  is part of the virtualization support associated with the CPU  110 . In other embodiments the fault register  113  supports floating point unit operations and legacy compatibility with new software releases intended for new hardware resources. 
         [0028]    The fault register  113  may be implemented as a 32 bit value. Instruction words smaller than 32 bits may be placed in bits 15:0, with bits 31:16 containing zeroes. 
         [0029]    While various embodiments of the invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant computer arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in addition to using hardware (e.g., within or coupled to a Central Processing Unit (“CPU”), microprocessor, microcontroller, digital signal processor, processor core, System on chip (“SOC”), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code, and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modeling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, or optical disc (e.g., CD-ROM, DVD-ROM, etc.). 
         [0030]    It is understood that the apparatus and method described herein may be included in a semiconductor intellectual property core, such as a microprocessor core (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and methods described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.