Abstract:
A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.

Description:
BACKGROUND OF THE INVENTION 
     A variety of logic schemes have been devised for counting purposes in the prior art, each method oriented toward accomplishing specific goals relating to input format, output format and speed. Binary weighted counting is most commonly used since if offers high efficiency in terms of the number of count states, 2 b , that can be represented by a given number of bits or stages and construction is reasonably simple, however decoding individual count states is not particularly easy and most binary weighted counters exhibit discontinuities resulting from a combination of propagation delays and the frequent need for multiple bits to change simultaneously. 
     Discontinuities may be eliminated by use of a cyclic or Gray code in which only one bit changes state at a time, however this method tends to complicate both the counting scheme and the interpretation of its output. Another method of avoiding discontinuities is by use of a threshold format, which is not as efficient in terms of the number of count states, b+1, that can be represented by a given number of bits or stages, but offers simple output decoding and is suitable where a limited number of count states are needed. The threshold format is characterized by a linear series of outputs with all high logic states on one side of the threshold point and all low logic states on the opposite side and can progress one bit at a time from all low to all high as the threshold point advances. This format happens to be well suited to non-linear digital to analog conversion and various other applications. 
     Most counting schemes are designed to advance the output code only on half of the clock transitions, this poses a substantial limitation in certain applications where a higher resolution of the clock signal is needed. The resolution can be doubled by counting on both positive and negative transitions of the clock line, this is particularly useful with a symmetrical clock signal. 
     OBJECT AND SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a simple method of assembling digital logic elements in order to produce a threshold style counting array capable of incrementing by one bit, up or down, on each clock transition. 
     The concept includes a linear array of R/S latches and associated logic elements arranged in a manner such that each latch can be made to set when the next clock transition occurs after the preceding latch has set or to reset when the next clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable provisions may be used with any combination of direct set/reset inputs for purposes of count sequence modifications. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the fundamental logic relationships involved in the counting array. 
     FIG. 2 shows a preferred embodiment of the present invention incorporating clock phasing, count enable and direct set/reset options. 
     FIGS. 3,4,5 illustrate several of the possible logic forms which may be used to construct the counting elements or stages of FIG. 2. 
     FIG. 6 shows a logic assembly which may be used to adjust the clock phase in FIG. 2. 
     FIG. 7 is a timing diagram which demonstrates the operation of the counting array in FIG. 2. 
     FIG. 8 is a NAND/NOR implementation of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The logic theory and implementation of the present invention will be described in terms of positive logic with reference to FIGS. 1 through 8 and tables I and II. It should be recognized that the principles of this invention can also be achieved in negative logic or in a combination of positive and negative logic, depending on the fabrication technology to be implemented; for example, it can be advantageous to alternate logic polarity and alternate NAND and NOR type stages where CMOS technology is to be applied. 
     In describing the invention a number of signals will be referred to which are considered to be true during a high logic state and false during a low logic state. Boolean relationships among signals are indicated below each logic diagram in terms of these standard notations: 
     X=NOT X--complement of X 
     ·=AND 
     +=OR 
     ⊕=XOR--exclusive OR 
     FIG. 1 is a block diagram illustrating the primary signals involved in the present invention where: 
     Ci=Clock input to stages 
     Cp=Clock--phased 
     Re=Reset enable--clocked 
     Ro=Reset output 
     Se=Set enable--clocked 
     So=Set output 
     Up=Up count direction 
     Blocks 1, 2, 3 represent gated R/S latching stages each of which is supplied with signals indicating the status of the two adjacent stages, Se from the preceding stage and Re from the succeeding stage. Each counter stage may also be supplied with the Up signal which is used to select the direction in which counting is to occur where a high state selects count up or stage setting, or a low state selects count down or stage resetting. A clock signal Ci controls the time at which counting occurs where a high state permits setting and a low state permits resetting, so that a change in direction, Up, while the clock, Ci, is stable will not cause an immediate change in the state of the latching stage. In the counter array Ci is derived from Cp in a manner which effectively inverts the signal to alternate stages so that only one stage at a time can set or reset from a single clock transition. A combination of Up and Se and Ci will normally cause a stage to set So high and Ro low. A combination of Up and Re and Ci will normally cause a stage to reset Ro high and So low. Ro and So generally exhibit complementary latched logic states indicating the status of that counter stage. 
     The overall operation of the counter array in FIG. 1 may be better understood by tracing it from an initial condition of all latches in the reset state, that is all So=0 and all Ro=1. Assume that Up=1 and that a clock signal is applied. The portion of the array shown in the figure will remain in the reset state until the preceding stage sets causing Se1 to become 1. This enables the next clock transition, Cp high, to set So1 to 1 which in turn causes the Se2 input of the next stage to go to 1 which then enables the next clock transition, Cp low, to set So2 to 1 causing Se3 to enable the next Cp high to set So3 to 1. This process continues in an identical manner to the end of the array, advancing the set state by one stage on each clock transition as long as the up direction is in effect. The resulting output sequence is in a threshold format of set stages on one side of a threshold point and reset stages on the opposite side. 
     Counting down is accomplished by putting Up at 0 and applying a clock signal. Assume that the array shown in FIG. 1 is all in the set state, that is all So=1 and all Ro=0. The portion of the array shown in the figure will remain in the set state until the succeeding stage resets causing Re3 to become 1. This enables the next clock transition, Cp low, to reset Ro3 to 1 which in turn causes the Re2 input of the next stage to go to 1 which then enables the next clock transition, Cp high, to reset Ro2 to 1 causing Re1 to enable the next Cp low to reset Ro1 to 1. This process continues in an identical manner to the end of the array, advancing the reset state by one stage for each clock transition as long as the count down direction is in effect, again progressing in the threshold format. 
     FIG. 2 shows a preferred embodiment of the present invention will expands upon the basic concept of FIG. 1 and incorporates these additional logic signals: 
     Ce=Count enable 
     Ck=Clock--unphased 
     Pa=Phase `a` select--Cp low 
     Pb=Phase `b` select--Cp high 
     Ri=Reset input--direct 
     Rs=Resetting sequence enable 
     Si=Set input--direct 
     Ss=Setting sequence enable 
     The counting process for FIG. 2 is identical to that described for FIG. 1 provided that Ce is high and all Si and Ri are low. Each stage in the array is permitted to set when a Cp clock transition occurs after the preceding stage has set during count up, or to reset when a Cp clock transition occurs after the succeeding stage has reset during count down. Direction, Up, may be changed while the clock signal is stable and the change will not alter the array output code until the next clock transition occurs. Table I provides a summary of the normal counting sequences for the array of FIG. 2 where the indicated direction is selected prior to occurrence of the indicated clock state. 
     
                       TABLE I______________________________________UP/DOWN COUNTING SEQUENCESTime  0     1      2   3    4   5    6   7    8   9    10______________________________________Cp    0     1      0   1    0   1    0   1    0   1    0Up    0     1      1   1    1   1    0   0    0   0    0So5   0     0      0   0    0   1    0   0    0   0    0So4   0     0      0   0    1   1    1   0    0   0    0So3   0     0      0   1    1   1    1   1    0   0    0So2   0     0      1   1    1   1    1   1    1   0    0So1   0     1      1   1    1   1    1   1    1   1    0Count 0     1      2   3    4   5    4   3    2   1    0(Se1, Re5, and Ce = 1; all Si and Ri = 0)______________________________________ 
    
     The array of FIG. 2 includes input Ce, which enables counting in the high logic state and disables counting when it is put in the low state by blocking the generation of the setting or resetting sequence enable signals. While Ce is in its high state Ss is the complement of Rs so that setting or resetting can occur depending on the state of Up. These functions are provided by direction inverter 13 combined with AND gate 15 to produce Rs, and AND gate 14 directly produces Ss for application to the counting array. 
     Direct latch set, Si, and reset, Ri, inputs shown in FIG. 2 increase the flexibility of the counting array by making it possible for counting stages to be individually or collectively set or reset independent of clocking. This capability is particularly useful for clearing or presetting the array and can also be used in ripple configurations, as indicated in FIG. 2, to correct unwanted counter states which do not conform to the threshold format; for example if all stages of the counter are in a reset state and stage 4 receives a set, Si4, signal, the counter adopts an unacceptable output So sequence of 0,0,0,1,0 which can be corrected to the valid sequence of 1,1,1,1,0, by permitting each set stage to direct set the preceding stage. Correction could be performed in the opposite direction by permitting each reset stage to directly reset the succeeding stage, this would return the output sequence to 0,0,0,0,0. The ripple set and reset options do not interfere with normal counting procedure since they only serve to confirm the normal threshold format. In certain cases it may be desirable to provide multiple Si or Ri inputs to a counting stage, depending on the application. 
     The ability to directly set or reset individual stages within the counting array raises a potential problem in that the state of the clock signal might not be in agreement with the threshold position generated by an Si or Ri signal, therefore item 12 in FIG. 2 is provided as a clock phase control which may be used to correct the clock, Ck, to the proper clock phase Cp. A high signal on Pa causes Cp to go to a low phase or a high signal on Pb causes Cp to go to a high phase. When the phasing request signal is removed the clock, Cp, remains locked as either Ck or Ck. 
     FIGS. 3, 4, 5 illustrate several of the possible logic forms which may be used to construct individual counting stages, other configurations are possible including NAND type latching. Each of these figures offers a complete counting stage which is fully compatible with the signals provided for each stage in FIG. 2. These figures include additional signals: 
     Sc=Set--clocked 
     Rc=Reset--clocked 
     The counting stages in FIGS. 3, 4, 5 are accompanied by their Boolean equations, which initially appear to be quite different, but actually only differ in terms of response to conflicting input signals involving Ri and/or Si. The only difference between the three logic forms is in the origins of the output signals Ro and So, which can be chosen according to the desired priority of the direct set/reset inputs. Any number of Ri/Si inputs may be added and any unused signals may be deleted depending on the particular application. Each of the illustrated logic forms includes a conventional R/S latch consisting of gates 24 and 27 and inverters 25 and 28 as needed. Gate 24 normally causes the stage to set from either an Sc or Si signal and gage 27 normally causes the stage to reset from either an Rc or Ri signal. The clocked signals are supplied by gates 23 and 26 which prevent more than one of these signals from occurring at any time. Gate 23 generates Sc only when Ss, Se, and Ci are all high and gate 26 generates Rc only when Rs and Re are high and Ci is low. Once a stage has set Sc and Si no longer have any effect and once a stage has reset Rc and Ri no longer have an effect on the outputs. The desired counting array is produced by assembling these counter stages in a linear array with alternating clock polarity as shown in FIG. 2. 
     As an example of the purpose of the phase control, item 12 in FIG. 2, consider a case where stage 1 of the counter has just set during normal counting; this would occur, according to the conditions above, when Ss, Se, and Ci are all high. Now a direct reset, Ri1, signal is applied and a conflict arises because Ri1 is attempting to reset the stage while the clocked signal is still attempting to maintain the set condition, which should not now occur until the next clock transition. A solution to the problem is to invert the clock signal Cp to a nonconflicting state in cases where this type of conflict can arise. 
     FIG. 6 details a method of phase control, as in item 12 of FIG. 2, which is capable of reinterpreting clock Ck in order to produce either a high or a low phase on Cp in order to obtain clock phase compatibility with the threshold position resulting from any interruption in the normal counting sequence. The following additional logic signals apply: 
     Aa=Agreement `a` phase 
     Ab=Agreement `b` phase 
     Da=Disagreement `a` phase 
     Db=Disagreement `b` phase 
     Pi=Phase invert 
     The Pa and Pb phase selection inputs are normally maintained in a low state, producing low states on all A and D lines and therefore having no effect on the phase latch made up of gates 38 and 39. When a low phase is requested by putting Pa in a high state either Aa or Da will go to a high state depending on the current state of the clock Ck. If Ck is in a low state then gate 35 causes Aa to go high, which causes the phase latch to set Pi low. If Ck is in a high state then gate 34 puts Da high causing the phase latch to set Pi high. Gate 31 combines Ck and Pi in an exclusive OR to produce clock Cp in the low phase as requested by Pa. When a high phase is requested by putting Pb in a high state either Ab or Db will go high causing the phase latch to set Pi in a similar manner to the above, but resulting with Cp in the high phase. When a phase request signal is removed the phase latch maintains its condition, causing Cp to continue to appear as either Ck or Ck. A summary of the phasing operation is given in table II. 
     
                       TABLE II______________________________________CLOCK PHASE CONTROLTime 0      1     2   3    4   5   6    7   8   9    10                        11______________________________________Ck   0      1     0   1    0   1   0    1   0   1    0                        1                        Pa 1 0 0 1 0 0 0 0 0 0 0 0                        Pb 0 0 0 0 0 0 1 0 0 1 0 0                        Aa 1 0 0 0 0 0 0 0 0 0 0 0                        Ab 0 0 0 0 0 0 0 0 0 1 0 0                        Da 0 0 0 1 0 0 0 0 0 0 0 0                        Db 0 0 0 0 0 0 1 0 0 0 0 0                        Pi 0 0 0 1 1 1 1 1 1 0 0 0                        Cp 0 1 0 0 1 0 1 0 1 1 0 1______________________________________ 
    
     FIG. 7 is a timing diagram which demonstrates typical signal sequences encountered during operation of an array such as that of FIG. 2. It is worth noting some timing restrictions that should be observed; Up and Ce should change state only while the clock is stable, and Pa and Pb should be in a low state prior to a clock transition which is intended to produce a count. 
     In time period `A` the initial random condition of the array is cleared by applying Ri signals to all stages, this results in all stages being reset as shown for So1 to So5. A simultaneous phasing request Pa is also applied which phases Cp to a low state. 
     In time period `B` Si signals are applied to all stages, this results in all stages being set as shown for So1 to So5. A simultaneous phasing request Pb is also applied which phases Cp to a high state. 
     In time span `C` the count down direction is selected by putting Up low, the counter array is enabled by putting Ce high and the count down begins after Re5 goes high. Each consecutive stage goes to the reset state on the next clock transition after the succeeding stage has reset. 
     The direction, Up, is switched high in `D` to permit a count up, which begins after Se1 goes high. Each consecutive stage goes to the set state on the next clock transition after the preceding stage has set. 
     `E` shows the beginning of another counter down sequence which is quickly switched back to count up in `F`, demonstrating the ability to reverse count direction on the next clock transition. 
     FIG. 8 shows a NAND/NOR version of the counting array which takes advantage of alternating positive and negative logic within the array in order to minimize the component requirements for CMOS fabrication. The NAND/NOR arrangement operates in exactly the same way as the previous implementations with the understanding that some of the logic signals are of inverse polarity as indicated by the drawing, in view of this it will be realized that table I and FIG. 7 and all previous discussion apply equally well to the array of FIG. 8. 
     This particular configuration utilizes the ripple code correction option whereby each set stage directly sets the preceding stage. Therefore a high signal on Si5 will cause a setting ripple through the preceding stages which is useful for presetting the counter. 
     A high signal on Ri1 is also applied directly to Ri3 and Ri5 causing all NOR type latches to reset, these reset states are then passed to the succeeding NAND type latches causing them to also reset, this results in a semiparallel resetting capability which is useful for clearing the counter rapidly since there is no accumulated propagation delay as occurs in the ripple presetting discussed above. 
     The same clock signal polarity is applied to adjacent counting stages in FIG. 8 and is simply interpretted in alternating polarity by the alternating NAND/NOR stages, so during unidirectional counting the only limit on counting speed is the propagation delay to set or reset a single latch. 
     While the invention has been shown and described in terms of the preferred embodiments it will be understood that changes may be made in the details without departing from the spirit and scope of the invention.