Abstract:
A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor integrated circuits and more particularly to structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a conventional semiconductor integrated circuit, there exist parasitic capacitances between metal lines of the interconnect layers of the integrated circuit and other conductive elements in the chip both part of the circuit and otherwise. Therefore, there is a need for structures (and methods for forming the same) in which parasitic capacitances are lower than that of the prior art. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a semiconductor structure, comprising (a) a substrate including semiconductor devices; (b) a first ILD (inter-level dielectric) layer on top of the substrate; (c) N first actual metal lines in the first ILD layer, N being a positive integer, wherein the N first actual metal lines are electrically connected to the semiconductor devices; and (c) first trenches in the first ILD layer, wherein the first trenches are not completely filled with solid materials, wherein if the first trenches are completely filled with first dummy metal lines, then the first dummy metal lines are not electrically connected to any semiconductor device, and wherein if the first trenches are completely filled with the first dummy metal lines, then the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer. 
         [0004]    The present invention provides structures (and methods for forming the same) in which parasitic capacitances are lower than that of the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIGS. 1A-1F  show cross-section views used to illustrate a fabrication process of a structure, in accordance with embodiments of the present invention. 
           [0006]      FIGS. 2A-2H  show cross-section views used to illustrate a fabrication process of another structure, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0007]      FIGS. 1A-1F  show cross-section views used to illustrate a fabrication process of a structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the fabrication process of the structure  100  starts with a dielectric layer  110 . The dielectric layer  110  can comprise silicon dioxide. The dielectric layer  110  can be on top of N interconnect layers (not shown) of a chip (not shown), N being a positive integer. The N interconnect layers can be on top of a front-end-of-line (FEOL) layer (not shown) of the chip wherein the FEOL layer contains semiconductor devices such as transistors, resistors, capacitors, etc. (not shown) of the chip. Each of the N interconnect layers contains metal lines electrically connected to semiconductor devices in the underlying FEOL layer or metal lines in an underlying interconnect layer. 
         [0008]    Next, in one embodiment, actual diffusion barrier liners  112   a , dummy diffusion barrier liners  112   d , actual metal lines  114   a , dummy metal lines  114   d , and vias (not shown) are formed in the dielectric layer  110 . The actual diffusion barrier liners  112   a  and the dummy diffusion barrier liners  112   d  can comprise Ta, Ti, Ru, RuTa, TaN, TiN, or RuTaN. The actual metal lines  114   a  and the dummy metal lines  114   d  can comprise copper. The actual diffusion barrier liners  112   a  and the actual metal lines  114   a  are electrically connected to semiconductor devices in the underlying FEOL layer or metal lines of the underlying interconnect layer through the vias. In contrast, the dummy diffusion barrier liners  112   d  and the dummy metal lines  114   d  are not electrically connected to any device in the underlying FEOL layer or any metal line of the underlying interconnect layer. The dummy diffusion barrier liners  112   d  and the dummy metal lines  114   d  are formed to provide a uniform pattern density of diffusion barrier liners and metal lines across the dielectric layer  110 . The actual diffusion barrier liners  112   a , the dummy diffusion barrier liners  112   d , the actual metal lines  114   a , the dummy metal lines  114   d , and the vias can be formed by a conventional dual damascene process or a single damascene process. 
         [0009]    Next, with reference to  FIG. 1B , in one embodiment, a photoresist region  120  is formed on top of the actual metal lines  114   a  and the actual diffusion barrier liners  112   a  such that the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  are exposed to the surrounding ambient. The photoresist region  120  can be formed by a conventional lithographic process. 
         [0010]    Next, in one embodiment, the metal and liner material in the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  are removed resulting in empty trenches  111  of  FIG. 1C . The dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  can be removed by wet etching with the photoresist region  120  as a blocking mask. More specifically, the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  can be in turn removed by (i) wet etching the dummy metal lines  114   d  and then (ii) wet etching the dummy diffusion barrier liners  112   d . In an alternative embodiment, the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  are removed simultaneously by wet etching. 
         [0011]    Next, with reference to  FIG. 1C , in one embodiment, the photoresist region  120  is removed resulting in structure  100  of  FIG. 1D . The photoresist region  120  can be removed by wet etching. 
         [0012]    Next, with reference to  FIG. 1E , in one embodiment, a dielectric passivation layer  130  is formed on top of the structure  100  of  FIG. 1D  such that the dielectric passivation layer  130  covers but does not completely fill the trenches  111 . As a result, the dielectric passivation layer  130  and the dielectric layer  110  form enclosed empty spaces  115  in the trenches  111 . The enclosed empty spaces  115  may contain vacuum, gases such as inert gases, or vapors, but do not contain solid materials. The dielectric passivation layer  130  can comprise silicon nitride. The dielectric passivation layer  130  can be formed by CVD (Chemical Vapor Deposition) of silicon nitride on top of the structure  100  of  FIG. 1D  resulting in the dielectric passivation layer  130 . The passivation layer can also be other materials such as silicon carbide, organic based compounds, etc, and can be applied by a number of different techniques such as a spin-on or dip coat, PVD, etc. It should be noted that there is some silicon nitride on side walls and bottom walls of the trenches  111 , but the silicon nitride on side walls and bottom walls of the trenches  111  is not shown in  FIG. 1E  for simplicity. 
         [0013]    Next, with reference to  FIG. 1F , in one embodiment, a dielectric layer  140  is formed on top of the dielectric passivation layer  130 . The dielectric layer  140  can comprise silicon dioxide. The dielectric layer  140  can be formed by a CVD process. 
         [0014]    Next, in one embodiment, dummy and actual diffusion barrier liners, dummy and actual metal lines, and vias (not shown) are formed in the dielectric layer  140 . The dummy diffusion barrier liners and dummy metal lines in the dielectric layer  140  are similar to the dummy diffusion barrier liners  112   d  and dummy metal lines  114   d  ( FIG. 1A ) in the dielectric layer  110 , respectively. The actual diffusion barrier liners and actual metal lines in the dielectric layer  140  are similar to the actual diffusion barrier liners  112   a  and actual metal lines  114   a  ( FIG. 1A ) in the dielectric  110 , respectively. The actual diffusion barrier liners and actual metal lines in the dielectric layer  140  are electrically connected to the actual diffusion barrier liners  112   a  and actual metal lines  114   a  in the dielectric layer  110  through the vias in the dielectric layer  140 . The dummy and actual diffusion barrier liners, the dummy and actual metal lines, and the vias in the dielectric layer  140  can be formed by a conventional dual damascene process. 
         [0015]    In summary, on the one hand, with reference to  FIG. 1A , the dummy diffusion barrier liners  112   d  and the dummy metal lines  114   d  provide a uniform pattern density of diffusion barrier liners and metal lines across the dielectric layer  110  during the formation of the actual diffusion barrier liners  112   a  and the actual metal lines  114   a . On the other hand, with reference to  FIG. 1F , with the dummy diffusion barrier liners  112   d  and the dummy metal lines  114   d  ( FIG. 1A ) in the trenches  111  being removed, the parasitic capacitance caused by the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  is eliminated. In addition, the enclosed empty spaces  115  in the trenches  111  (that may contain vacuum, gases such as inert gases, or vapors) result in a lower effective dielectric constant for material around the actual diffusion barrier liners  112   a  and the actual metal lines  114   a.    
         [0016]      FIGS. 2A-2H  show cross-section views used to illustrate a fabrication process of a structure  200 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 2A , the fabrication process of the structure  200  starts with the structure  200  of  FIG. 2A . The structure  200  of  FIG. 2A  is similar to the structure  100  of  FIG. 1A . More specifically, the structure  200  comprises actual diffusion barrier liners  212   a , dummy diffusion barrier liners  212   d , actual metal lines  214   a , dummy metal lines  214   d  in a dielectric layer  210 . The actual diffusion barrier liners  212   a  and the actual metal lines  214   a  are electrically connected to semiconductor devices in the underlying FEOL layer or metal lines of the underlying interconnect layer through vias (not shown), whereas the dummy diffusion barrier liners  112   d  and the dummy metal lines  114   d  are not electrically connected to any device in the underlying FEOL layer or any metal line of the underlying interconnect layer. The formation of the structure  200  is similar to the formation of the structure  100  of  FIG. 1A . 
         [0017]    Next, with reference to  FIG. 2B , in one embodiment, a dielectric passivation layer  220  is formed on top of the structure  200  of  FIG. 2A . The dielectric passivation layer  220  can comprise silicon nitride, silicon carbide, some organic based compounds etc. The dielectric passivation layer  220  can be formed by CVD of silicon nitride on top of the structure  200  of  FIG. 2A . 
         [0018]    Next, with reference to  FIG. 2C , in one embodiment, a porous structure layer  230  is formed on top of the dielectric passivation layer  220 . The top surface  222  of the dielectric passivation layer  220  is exposed to the surrounding ambient through pores  235  of the porous structure layer  230 . The porous structure layer  230  can comprise a polymer material. The porous structure layer  230  can be formed by (i) spin-on a special material including, illustratively, two polymers on top of the dielectric passivation layer  220  and then (ii) baking the special material such that one of the two polymers evaporates, whereas the other polymer remains resulting in the porous structure layer  230 . 
         [0019]    Next, with reference to  FIG. 2D , in one embodiment, a photoresist region  240  is formed on top of the porous structure layer  230  such that the actual metal lines  214   a  and the actual diffusion barrier liners  212   a  are directly beneath the photoresist region  240  in a reference direction defined by an arrow  232  (also called a reference direction  232 ). In other words, the entire actual metal lines  214   a  and the entire actual diffusion barrier liners  212   a  overlap the photoresist region  240  in the reference direction  232 . The reference direction  232  is perpendicular to the top surface  213  of the dielectric layer  210 . In addition, the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  are not directly beneath the photoresist region  240  in the reference direction  232 . In other words, the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  do not overlap the photoresist region  240  in the reference direction  232 . The photoresist region  240  can be formed by a conventional lithographic process. 
         [0020]    Next, in one embodiment, the dielectric passivation layer  220  is anisotropically etched (in the reference direction  232 ) with the porous structure layer  230  and the photoresist region  240  as blocking masks resulting in the structure  200  of  FIG. 2E . As a result of the etching of the dielectric passivation layer  220 , the top surfaces of the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  are exposed to the surrounding ambient through the empty spaces of the removed portions of the dielectric passivation layer  220  and the pores  235  of the porous structure layer  230 . 
         [0021]    Next, in one embodiment, the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  are removed resulting in structure  200  of  FIG. 2F . The dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  can be removed by wet etching. More specifically, the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  can be in turn removed by (i) wet etching the dummy metal lines  214   d  and then (ii) wet etching the dummy diffusion barrier liners  212   d . In an alternative embodiment, the dummy metal lines  114   d  and the dummy diffusion barrier liners  112   d  are removed simultaneously by wet etching. This etching of the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  is essentially selective to the dielectric layer  210  and the dielectric passivation layer  220 . In other words, the chemistry of the recipe of the etching of the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  (e.g., chemicals used, temperature, pressure, ect.) is such that the dielectric layer  210  and the dielectric passivation layer  220  are essentially not affected by the etching of the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d.    
         [0022]    Next, with reference to  FIG. 2F , in one embodiment, the photoresist region  240  and the porous structure layer  230  are removed resulting in the structure  200  of  FIG. 2G . The photoresist region  240  and the porous structure layer  230  can be removed by wet etching or by a downstream plasma etch. 
         [0023]    Next, with reference to  FIG. 2H , in one embodiment, a dielectric layer  250  is formed on top of the dielectric passivation layer  220 . The dielectric layer  250  can comprise silicon dioxide. The dielectric layer  250  can be formed by a conventional CVD process. 
         [0024]    Next, in one embodiment, dummy and actual diffusion barrier liners, dummy and actual metal lines, and vias (not shown) are formed in the dielectric layer  250 . The dummy diffusion barrier liners and dummy metal lines in the dielectric layer  2500  are similar to the dummy diffusion barrier liners  212   d  and dummy metal lines  214   d  ( FIG. 2A ) in the dielectric layer  210 , respectively. The actual diffusion barrier liners and actual metal lines in the dielectric layer  250  are similar to the actual diffusion barrier liners  212   a  and actual metal lines  214   a  ( FIG. 2A ) in the dielectric  210 , respectively. The actual diffusion barrier liners and actual metal lines in the dielectric layer  250  are electrically connected to the actual diffusion barrier liners  212   a  and actual metal lines  214   a  in the dielectric layer  210  through the vias in the dielectric layer  250 . The dummy and actual diffusion barrier liners, the dummy and actual metal lines, and the vias in the dielectric layer  250  can be formed by a conventional dual damascene process. 
         [0025]    In summary, on the one hand, with reference to  FIG. 2A , the dummy diffusion barrier liners  212   d  and the dummy metal lines  214   d  provide a uniform pattern density of diffusion barrier liners and metal lines across the dielectric layer  210  during the formation of the actual diffusion barrier liners  212   a  and the actual metal lines  214   a . On the other hand, with reference to  FIG. 2H , with the dummy diffusion barrier liners  212   d  and the dummy metal lines  214   d  ( FIG. 2A ) in the trenches  211  being removed, the parasitic capacitance caused by the dummy metal lines  214   d  and the dummy diffusion barrier liners  212   d  is eliminated. In addition, the trenches  211  that are not completely filled with solid materials (i.e., the trenches  211  may contain vacuum, gases such as inert gases, or vapors) result in a lower effective dielectric constant for material around the actual diffusion barrier liners  212   a  and the actual metal lines  214   a.    
         [0026]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.