Abstract:
Techniques for removing ringing artifacts from video data. A deringing filter in accordance with the present invention preserves real image edges in a video frame, while smoothing out the interiors of objects. In one aspect, a 9-tap low-pass filter is applied to an adaptive processing window. The filter window is initialized with the values in a 3×3 mask centered on the position whose output is computed. Then all values that are very different from the central one are replaced with the central value. The deringing filter varies between 3×3 low-pass and identity, depending on how much the central value differs from its surrounding ones. A deblocking filter in accordance may also be suitably used in conjunction with the deringing filter.

Description:
[0001]    The present application claims the benefit of U.S. Provisional Application Serial No. 60/288,965 filed May 4, 2001, and entitled “Methods and Apparatus for Removing Compression Artifacts in Video Sequences” which is incorporated herein by reference in its entirety. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention relates generally to improvements in video processing. More specifically, the present invention relates to filters which provide for improved visual quality in video decoding.  
         BACKGROUND OF THE INVENTION  
         [0003]    In low bit rate video coding, the quantization of discrete cosine transform (DCT) coefficients produces well known artifacts in decoded images. The best known artifacts are the blocking effect and the ringing effect. Signal adaptive filters are generally used to remove these artifacts, while preserving details which belong to the image. Deblocking and deringing are two video post-processing techniques used to remove coding artifacts and improve the visual quality when rendering low bit rate coded video. The techniques used to achieve these tasks are computationally intensive and usually require high speed processors to be able to run in real time.  
           [0004]    The blocking effect is grid noise along block boundaries and is mainly visible in smooth areas with low motion. The blocking effect is produced by the quantization of direct current (DC) coefficients. Usually deblocking filters try to remove the unwanted boundaries between adjacent blocks by low-pass filtering pixels on both sides of the block borders. However, this type of filtering may introduce undesirable blurring effects when applied to pixels which belong to real image edges. The ringing effect shows along object borders and is primarily due to the quantization of alternating current (AC) coefficients.  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention advantageously provides methods and apparatus for removing ringing artifacts from video data. A deringing filter in accordance with the present invention preserves real image edges in a video frame, while smoothing out the interiors of objects. In one aspect, a 9-tap low-pass filter is applied to an adaptive processing window. The filter window is initialized with the values in a 3×3 mask centered on the position whose output is computed. Then, all values that are significantly different from the central value are replaced with the central value. The deringing filter varies between a 3×3 low-pass filter and an identity filter, depending on how much the central value differs from its surrounding values. The deringing method of the present invention detects image edges and applies a filter along these edges to eliminate the noise. The decision between edge and non-edge block borders relies on the assumption that real borders have a higher amplitude than edges produced by the quantization of DCT coefficients. A deblocking filter in accordance with the present invention may also be suitably used in conjunction with the deringing filter.  
           [0006]    A more complete understanding of the present invention, as well as further features and advantages of the invention, will be apparent from the following detailed description and the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 illustrates an exemplary ManArray DSP and DMA subsystem appropriate for use with this invention;  
         [0008]    [0008]FIG. 2 illustrates a processing mask and filter coefficients in accordance with the present invention;  
         [0009]    [0009]FIG. 3 shows a deringing method in accordance with the present invention;  
         [0010]    [0010]FIG. 4 shows a code sequence of a deringing filter in accordance with the present invention;  
         [0011]    [0011]FIG. 5 shows a diagram of a video window for deblocking in accordance with the present invention;  
         [0012]    [0012]FIG. 6 shows a flow chart of a deblocking method in accordance with the present invention;  
         [0013]    [0013]FIG. 7 shows a code sequence of a deblocking filter in accordance with the present invention;  
         [0014]    [0014]FIG. 8 illustrates a video block in accordance with the present invention;  
         [0015]    [0015]FIG. 9 shows a PE data memory map in accordance with the present invention;  
         [0016]    [0016]FIG. 10 shows a video frame in accordance with the present invention; and  
         [0017]    [0017]FIG. 11 shows a deblocking method in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0018]    The present invention now will be described more fully with reference to the accompanying drawings, in which several presently preferred embodiments of the invention are shown. This invention may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.  
         [0019]    Further details of a presently preferred ManArray core, architecture, and instructions for use in conjunction with the present invention are found in: U.S. patent application Ser. No. 08/885,310 filed Jun. 30, 1997, now U.S. Pat. No. 6,023,753; U.S. patent application Ser. No. 08/949,122 filed Oct. 10, 1997, now U.S. Pat. No. 6,167,502; U.S. patent application Ser. No. 09/169,256 filed Oct. 9, 1998, now U.S. Pat. No. 6,167,501; U.S. patent application Ser. No. 09/169,255 filed Oct. 9, 1998, now U.S. Pat. No. 6,343,356; U.S. patent application Ser. No. 09/169,072 filed Oct. 9, 1998, now U.S. Pat. No. 6,219,776; U.S. patent application Ser. No. 09/187,539 filed Nov. 6, 1998, now U.S. Pat. No. 6,151,668; U.S. patent application Ser. No. 09/205,558 filed Dec. 4, 1998, now U.S. Pat. No. 6,173,389; U.S. patent application Ser. No. 09/215,081 filed Dec. 18, 1998, now U.S. Pat. No. 6,101,592; U.S. patent application Ser. No. 09/228,374 filed Jan. 12, 1999, now U.S. Pat. No. 6,216,223; U.S. patent application Ser. No. 09/471,217 filed Dec. 23, 1999, now U.S. Pat. No. 6,260,082; U.S. patent application Ser. No. 09/472,372 filed Dec. 23, 1999, now U.S. Pat. No. 6,256,683; U.S. patent application Ser. No. 09/543,473 filed Apr. 5, 2000, now U.S. Pat. No. 6,321,322; U.S. patent application Ser. No. 09/350,191 now U.S. Pat. No. 6,356,994; U.S. patent application Ser. No. 09/238,446 now U.S. Pat. No. 6,366,999; U.S. patent application Ser. No. 09/267,570 filed Mar. 12, 1999; U.S. patent application Ser. No. 09/337,839 filed Jun. 22, 1999; U.S. patent application Ser. No. 09/422,015 filed Oct. 21, 1999; U.S. patent application Ser. No. 09/432,705 filed Nov. 2, 1999; U.S. patent application Ser. No. 09/596,103 filed Jun. 16, 2000; U.S. patent application Ser. No. 09/598,567 filed Jun. 21, 2000; U.S. patent application Ser. No. 09/598,564 filed Jun. 21, 2000; U.S. patent application Ser. No. 09/598,566 filed Jun. 21, 2000, U.S. patent application Ser. No. 09/598,558 filed Jun. 21, 2000; U.S. patent application Ser. No. 09/598,084 filed Jun. 21, 2000; U.S. patent application Ser. No. 09/599,980 filed Jun. 22, 2000; U.S. patent application Ser. No. 09/711,218 filed Nov. 9, 2000; U.S. patent application Ser. No. 09/747,056 filed Dec. 12, 2000; U.S. patent application Ser. No. 09/853,989 filed May 11, 2001; U.S. patent application Ser. No. 09/886,855 filed Jun. 21, 2001; U.S. patent application Ser. No. 09/791,940 filed Feb. 23, 2001; U.S. patent application Ser. No. 09/792,819 filed Feb. 23, 2001; U.S. patent application Ser. No. 09/792,256 filed Feb. 23, 2001; U.S. patent application Ser. No. 10/013,908 filed Oct. 19, 2001; U.S. application Ser. No. 10/004,010 filed Nov. 1, 2001; U.S. application Ser. No. 10/004,578 filed Dec. 4, 2001; U.S. application Ser. No. 10/116,221 filed Apr. 4, 2002; U.S. application Ser. No. 10/119,660 filed Apr. 10, 2002; U.S. application Ser. No. ______ entitled “Methods and Apparatus for Pipelined Bus” filed Apr. 25, 2002; Provisional Application Serial No. 60/288,965 filed May 4, 2001; Provisional Application Serial No. 60/298,624 filed Jun. 15, 2001; Provisional Application Serial No. 60/298,695 filed Jun. 15, 2001; Provisional Application Serial No. 60/298,696 filed Jun. 15, 2001; Provisional Application Serial No. 60/318,745 filed Sep. 11, 2001; Provisional Application Serial No. 60/340,620 filed Oct. 30, 2001; and Provisional Application Serial No. 60/335,159 filed Nov. 1, 2001; Provisional Application Serial No. 60/368,509 filed Mar. 29, 2002, all of which are assigned to the assignee of the present invention and incorporated by reference herein in their entirety.  
         [0020]    In a presently preferred embodiment of the present invention, a ManArray 2×2 iVLIW single instruction multiple data stream (SIMD) processor  100  as shown in FIG. 1 may be adapted as described further below for use in conjunction with the present invention. Processor  100  comprises a sequence processor (SP) controller combined with a processing element-0 (PE0) to form an SP/PE0 combined unit  101 , as described in further detail in U.S. patent application Ser. No. 09/169,072 entitled “Methods and Apparatus for Dynamically Merging an Array Controller with an Array Processing Element”. Three additional PEs  151 ,  153 , and  155  are also labeled with their matrix positions as shown in parentheses for PE0 (PE00)  101 , PE1 (PE01)  151 , PE2 (PE10)  153 , and PE3 (PE11)  155 . The SP/PE0  101  contains an instruction fetch (I-fetch) controller  103  to allow the fetching of “short” instruction words (SIW) or abbreviated-instruction words from a B-bit instruction memory  105 , where B is determined by the application instruction-abbreviation process to be a reduced number of bits representing ManArray native instructions and/or to contain two or more abbreviated instructions as described in the present invention. If an instruction abbreviation apparatus is not used then B is determined by the SIW format. The fetch controller  103  provides the typical functions needed in a programmable processor, such as a program counter (PC), a branch capability, eventpoint loop operations (see U.S. Provisional Application Serial No. 60/140,245 entitled “Methods and Apparatus for Generalized Event Detection and Action Specification in a Processor” filed Jun. 21, 1999 for further details), and support for interrupts. It also provides the instruction memory control which could include an instruction cache if needed by an application. In addition, the I-fetch controller  103  controls the dispatch of instruction words and instruction control information to the other PEs in the system by means of a D-bit instruction bus  102 . D is determined by the implementation, which for the exemplary ManArray coprocessor D=32-bits. The instruction bus  102  may include additional control signals as needed in an abbreviated-instruction translation apparatus.  
         [0021]    In this exemplary system  100 , common elements are used throughout to simplify the explanation, though actual implementations are not limited to this restriction. For example, the execution units  131  in the combined SP/PE0  101  can be separated into a set of execution units optimized for the control function; for example, fixed point execution units in the SP, and the PE0 as well as the other PEs can be optimized for a floating point application. For the purposes of this description, it is assumed that the execution units  131  are of the same type in the SP/PE0 and the PEs. In a similar manner, SP/PE0 and the other PEs use a five instruction slot iVLIW architecture which contains a VLIW instruction memory (VIM)  109  and an instruction decode and VIM controller functional unit  107  which receives instructions as dispatched from the SP/PE0&#39;s I-fetch unit  103  and generates VIM addresses and control signals  108  required to access the iVLIWs stored in the VIM. Referenced instruction types are identified by the letters SLAMD in VIM  109 , where the letters are matched up with instruction types as follows: Store (S), Load (L), ALU (A), MAU (M), and DSU (D).  
         [0022]    The basic concept of loading the iVLIWs is described in further detail in U.S. patent application Ser. No. 09/187,539 entitled “Methods and Apparatus for Efficient Synchronous MIMD Operations with iVLIW PE-to-PE Communication”. Also contained in the SP/PE0 and the other PEs is a common PE configurable register file  127  which is described in further detail in U.S. patent application Ser. No. 09/169,255 entitled “Method and Apparatus for Dynamic Instruction Controlled Reconfiguration Register File with Extended Precision”. Due to the combined nature of the SP/PE0, the data memory interface controller  125  must handle the data processing needs of both the SP controller, with SP data in memory  121 , and PE0, with PE0 data in memory  123 . The SP/PE0 controller  125  also is the controlling point of the data that is sent over the 32-bit or 64-bit broadcast data bus  126 . The other PEs,  151 ,  153 , and  155  contain common physical data memory units  123 ′,  123 ″, and  123 ′″ though the data stored in them is generally different as required by the local processing done on each PE. The interface to these PE data memories is also a common design in PEs 1, 2, and 3 and indicated by PE local memory and data bus interface logic  157 ,  157 ′ and  157 ″. Interconnecting the PEs for data transfer communications is the cluster switch  171  various aspects of which are described in greater detail in U.S. patent application Ser. No. 08/885,310 entitled “Manifold Array Processor”, now U.S. Pat. No. 6,023,753, and U.S. patent application Ser. No. 09/169,256 entitled “Methods and Apparatus for Manifold Array Processing”, and U.S. patent application Ser. No. 09/169,256 entitled “Methods and Apparatus for ManArray PE-to-PE Switch Control”. The interface to a host processor, other peripheral devices, and/or external memory can be done in many ways. For completeness, a primary interface mechanism is contained in a direct memory access (DMA) control unit  181  that provides a scalable ManArray data bus  183  that connects to devices and interface units external to the ManArray core. The DMA control unit  181  provides the data flow and bus arbitration mechanisms needed for these external devices to interface to the ManArray core memories via the multiplexed bus interface represented by line  185 . A high level view of a ManArray control bus (MCB)  191  is also shown in FIG. 1.  
         [0023]    The present invention includes techniques for a deringing adaptive filter to reduce ringing noise in video processing. A deringing filter in accordance with the present invention may be suitably implemented on a computer processor, such as the system  100  described above. The deringing filter includes filtering masks which should include only pixels which are on the same side of an edge that needs to be preserved in order to prevent undesired blurring of image details. In addition, the deringing filter of the present invention may be suitably implemented on parallel processors which may not allow the use of data dependent jumps or calls. The visual quality obtained using the present deringing filter on very low bit rate sequences may be superior to the visual quality obtained by the MPEG4 filter.  
         [0024]    [0024]FIG. 2 shows a diagram  200  including a processing mask  202  and filter coefficients  204  in accordance with one aspect of the present invention. For each pixel of an original image to be processed, the 3×3 mask  202  having pixels v 0 -v 8  is processed. Initially, the mask  202  includes a central pixel v 4  and eight neighboring pixels v 0 -v 3  and v 5 -v 8  from the original image. The absolute difference between the pixel v 4  and each of the pixel&#39;s eight neighbors is compared with a threshold value which is equal to a quantization parameter (QP). If the absolute difference is higher than the threshold value, the corresponding neighbor value of a pixel is replaced in the processing mask by the central value of pixel v 4 . In such a case, it is assumed that the neighboring pixel does not belong to the same side of an image edge as the central pixel. Finally, a low pass filter is applied to the values in the processing mask to yield the resulting image. By replacing the values in the processing mask, the deringing filter varies between a low pass filter in which no value is replaced because no image edge is present in the mask, and an identity filter in which all differences are larger than the threshold and all values are replaced by the central value. FIG. 2 also illustrates an example of how the full procedure works. The original image in a block, such as block  206 , is filtered with this procedure. For each pixel, at any position (i,j) within the image (i=1 . . . rows, j=1 . . . columns) the pixel&#39;s value and the values of its eight neighbors are extracted and fill the 3×3 processing mask. For the selected example, the 3×3 mask in block  208  is filled with the pixel&#39;s value (73), which is in v 4  position, and the values of its eight neighbors (83,100,78,187,91,177,200,92). Then the absolute difference between 73 and each of its eight neighbors is compared against a threshold (QP), which in this example is equal to 31, as illustrated by equation  210 . Whenever the absolute difference is higher than the threshold, the respective neighbor value is replaced with the central value, which is 73. For this example, values 187, 177 and 200 in block  208  are replaced with value 73 in block  212 . Expression  214  is used to calculate a resulting value. The variables in expression  214  v 0 -v 8  are instantiated with values from block  212  and it becomes expression  216 . The divide operation is an integer divide. The result of this expression  216  is 81, and this value is stored in the result image, block  218 , in the position (i,j) corresponding to the selected pixel from the original image  206 .  
         [0025]    [0025]FIG. 3 shows a deringing method  300  in accordance with the present invention. In step  302 , the filter input vector is calculated for each pixel x i,j  in the input image (i=1, . . . cols, j=1, . . . rows). In step  304 , the output y i,j  is calculated for each pixel x l,j  in the input image.  
         [0026]    In a preferred embodiment, the image to be processed is divided into rectangular slices and each slice is separately processed by PEs working in SIMD mode. The slices are selected such that they contain an integer number of macroblocks, in a similar fashion to a deblocking filter technique described below. Data transfer, partitioning and program flow are performed in the background of the computation.  
         [0027]    [0027]FIG. 4 illustrates a table  400  which shows an exemplary code segment for a deringing filter in accordance with the present invention. The filtering code is implemented in three nested loops in order to browse all vertical block borders and load the appropriate QP value for each border. An outer loop operates vertically on rows of blocks in the slice. A middle loop operates vertically on rows in a block (8 rows). As shown in table  400 , an inner loop operates horizontally on the blocks in a row. Additional code segments for executing a deringing filter in accordance with the present invention are included in Appendix A and Appendix B.  
         [0028]    For each PE, the input slices contain the additional bordering rows and columns needed in the computation. The present approach increases the amount of data transferred, but removes data dependencies between the PEs. The present approach may be suitably employed in such situations where the computation takes longer than the data transfer. The filtering may be advantageously achieved in a single pass. Eight output values are calculated on each PE in one pass through the inner computation loop. Packed data (8×8 bits or 4×16 bits data in 64 bits register pair) may be used. When the values of the input vector v are selected, the implementation may utilize instructions which are performed on packed 8×8 bit data. Additions, multiplies by 2 and shifts for division are used in the computation and the output is calculated as in the equation:  
           y =((( v   4 +2)*2 +v   1   +v   3   +v   5   +v   7 )*2 +v   0   +v   2   +v   6   +v   8 )/16  
         [0029]    The code may be optimized for use with VLIWs. In a preferred embodiment, the method of the present invention consumes 96 cycles in the sequential implementation and only 36 cycles in the optimized implementation, with the VLIW efficiency factor being 2.67.  
         [0030]    For an optimized implementation on each PE, the deringing filter loop takes 36 cycles for calculating eight output values. For one frame having horizontal and vertical dimensions H and V, the loop runs V*H/8 times for the deringing of luminance. The frame is divided and processed on four PEs, allowing the performance to scale linearly with the number of PEs utilized. If FPS denotes the frame rate, the theoretical lower bounds of the computation cycles for filtering the luminance on four PEs is ((V*H/8)*36*FPS)/4 cycles/sec, ignoring overhead such as DMA transfers and control flow instructions.  
         [0031]    The deringing filter of the present invention may be suitably utilized in a system including a deblocking filter. For an image to be processed, the deblocking filtering is performed on both horizontal and vertical block borders. As seen in a diagram  500  of FIG. 5, for vertical deblocking an 8-pixel decision window v 1 -v 8 , perpendicular to the border and including equal number of pixels on both border sides, is used to calculate local features and select the filter type and coefficients.  
         [0032]    The absolute differences between pairs of neighboring pixels are used to determine parameters, or feature values. The feature values are compared against thresholds based on the quantization parameter (QP). High values of the absolute differences indicate the presence of a real image edge which needs to be preserved. When a smooth region with no edges is indicated, a 7-tap low pass filter is used for calculating six values v 2 -v 7 , three on each side of the border, for strong smoothing. When an edge region is detected, but no abrupt change happens between the two neighboring pixels on each side of the border, a weak filter is applied, affecting only the two border pixels v 4  and v 5 . No filtering is performed when a high absolute difference between the two border pixels v 4  and v 5  indicate the presence of an edge on that border. Horizontal deblocking is performed in the same manner as vertical blocking. A flow chart  600  of the deblocking method is shown in FIG. 6, in which exemplary values of Thr1 and Thr2 being 2 and 6, respectively, may be used.  
         [0033]    In the deblocking method of the present invention, a frame is divided into rectangular slices, which are separately processed by the four PEs working in parallel. To unify all types of filters in a single procedure, values v 2 -v 7  are calculated for each processing window using different sets of coefficients. The coefficients are selected from a table where they are indexed by the decision value. In the case of “No filter” decision and for four of the values for “Weak filter”, an “Identity filter” is used.  
         [0034]    [0034]FIG. 7 shows a code sequence  700  suitable for performing the deblocking filter in accordance with the present invention. In each pass through the filtering loop the six output values for a position of the processing window on block borders are calculated. Packed data (8×8 bits or 4×16 bits data in 64 bits register pair) may be used for the computation. Values v 0 , . . . v 9  are loaded into three registers and are used to calculate the decision index. Using this index, a pointer to a table for the coefficients of the six output values is obtained. Filtering may be advantageously achieved using a sum2p instruction and a shift instruction for normalization. The code sequence is optimized using VLIWs, which enable the five execution units to perform parallel instructions in the same cycle. In a preferred embodiment, the computation time is reduced by a factor of 2.65, from 106 cycles required by a sequential implementation to 40 cycles needed in the optimized one. 21 cycles are used for the decision and coefficients selection, and 19 cycles for the actual computation of the ouput values.  
         [0035]    The filtering method of code sequence  700  is implemented in three nested loops in order to browse all vertical block borders and load for each border the appropriate QP value. An outer loop operates vertically on rows of blocks in the slice. A middle loop operates vertically on rows in a block (8 rows). An inner loop operates horizontally on the blocks in a raw.  
         [0036]    The horizontal and vertical deblocking is achieved in two subsequent passes through the filtering procedure. In the first pass, data is filtered for vertical deblocking and stored as transposed with respect to the original order. In the second pass, the data is again filtered for vertical deblocking on the transposed order, which is equivalent to horizontal deblocking on the original order. The result is again stored as transposed with respect to the input, yielding the original order.  
         [0037]    The image slices processed by PEs are selected such that the slices contain an integer number of blocks. The input slice should include four additional border pixels on each side to be used for the computation. The input slices are bounded by block borders. In an exemplary video block  800  shown in FIG. 8 each input slice includes 81 blocks  802  arranged in a 9×9 fashion, with each block  802  comprising 64 pixels arranged in a 8×8 fashion. The result is calculated for the inner block borders and corresponds to the 64×64 (pixel) cross-hatched section  804  shown in FIG. 8. Four pixels comprise a border on each side of section  804 .  
         [0038]    Initially, one slice of data is loaded into a PE data buffer, filtered for vertical deblocking and stored in transposed order in a second buffer. Then the second buffer is filtered and stored in transpose order back over the input. The result may then be transferred back to system memory, or SDRAM, and a new rectangular slice is loaded for processing. The techniques of the present invention enables overlap between data transfer to and from SDRAM and the computation. Three data buffers in PE data memory may used. Two of the data are used for loading input data and storing the result in an alternating fashion. The third buffer is used for the intermediate filtering result after the first pass through the deblocking filter. An exemplary PE data memory  900  is shown in FIG. 9. For deblocking one frame of luminance of SDTV size (704×480 bytes=88×60 blocks) the frame is divided in slices of 8×8 blocks. PE0, PE1 and PE2 process vertical areas of 3×8 slices, and the last PE processes an area of 2×8 slices, as shown in frame  1000  of FIG. 10.  
         [0039]    [0039]FIG. 11 shows a flow diagram of a deblocking method  1100  in accordance with the present invention. The design enables the data transfer between the SDRAM memory and a PE memory buffer (Buffer_Transfer) to take place while the computation is performed using two other buffers (Buffer_Proc and Buffer_Intermed). As described above, PE data memory is divided into three data buffers. Two of the buffers are alternately used for loading input data, and storing the result. The third buffer, denoted Buffer_Interm, is used for storing the intermediate filtering result after the first pass through the deblocking filter. One DMA channel is used for DMA output and input transfers, the data transfer time taking less than the actual processing. First the filtered data is transferred from Buffer_Transfer to SDRAM, then the buffer is filled with new data from the SDRAM. The only ‘wait’ states for the DMA to complete correspond to the first DMA transfer from SDRAM and the last DMA transfer to SDRAM. The data transferred from SDRAM into each PE memory include the rectangular slice and the additional boundary rows and columns needed in the computation. In the first pass, the bordering data needed for the second pass is also filtered.  
         [0040]    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the present invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.