Abstract:
A stable current mirror circuit that includes base current compensation is provided—i.e., a feedback loop in the current mirror circuit (used to perform base current compensation) does not have a tendency to oscillate. In addition, base current compensation is achieved in the current mirror circuit using a minimum number of circuit elements that can be easily scaled for reduced power consumption and size.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a continuation (and claims the benefit of priority under 35 USC 120) of U.S. application Ser. No. 10/792,485, filed Mar. 2, 2004, now U.S. Pat. No. 6,956,428. The disclosure of the prior application is considered part of (and is incorporated by reference in) the disclosure of this application. 

   BACKGROUND 
   The following disclosure relates to electrical circuits and methods for processing signals. 
   An often-used circuit applying a bipolar transistor is a current mirror circuit. A current mirror circuit generally serves as a current regulator (or current source), supplying a nearly constant current to one or more loads (or circuits). 
     FIG. 1  shows a conventional current mirror circuit  100 . Current mirror circuit  100  includes a reference current source I REF  and a master bipolar transistor Q i , and slave bipolar transistors Q 1 , Q 2 , . . . Q n . The bases of master bipolar transistor Q i  and slave bipolar transistors Q 1  Q 2 , . . . Q n  are commonly connected. Each slave bipolar transistor Q 1  Q 2 , . . . Q n  mirrors reference current I REF  (i.e., the collector current of master bipolar transistor Q i ) to produce output currents I 1 , I 2 , . . . I n , respectively. Output currents I 1 , I 2 , . . . I n , can be supplied to a variety of electrical circuits represented by circuits  102 - 1 ,  102 - 2 , . . .  102 -n. 
   Some current mirror circuits include base current compensation to reduce base current-related errors. Base current-related errors arise due to current loss from a reference current source (e.g., I REF ) being reflected at the commonly connected bases of the slave transistors in a current mirror circuit. As shown in  FIG. 1 , current mirror circuit  100  further includes a compensating bipolar transistor Q B  that performs base current compensation through a current feedback loop  104 . A common problem associated with a current feedback loop, such as current feedback loop  104 , is a tendency towards oscillation. To prevent oscillation, a current mirror circuit may include a current source (in addition to the reference current source), and one or more capacitors to stabilize the current feedback loop. For example, current mirror circuit  100  includes capacitors C A  and/or C B , and a relatively large current source I C  (that increases a gain of bipolar transistor Q B  and prevents oscillation in current feedback loop  104 ). 
   SUMMARY 
   In general, in one aspect, this specification describes a current mirror circuit. The current mirror circuit includes a reference current source and one or more slave bipolar transistors each configured to mirror the reference current source in accordance with a master bipolar transistor. The current mirror circuit further includes a compensation circuit configured to generate a compensating base current to the one or more slave bipolar transistors. A value of the compensating base current generated by the compensation circuit is substantially equal to (n+1)I B , in which n is equal to a total number of the one or more slave bipolar transistors, and I B  represents a base current flowing to the master bipolar transistor. 
   Particular implementations can include one or more of the following features. The compensation circuit can include a mirror circuit including a first transistor and a second transistor. The first transistor can be configured to receive a reference current equal to I B , and the second transistor can be configured to generate an output current having a value substantially equal to (n+1)I B . The first transistor and the second transistor can be sized differently. The first transistor and the second transistor can be MOSFET transistors having a width-to-length ratio of 1:(n+1), respectively. The first transistor and the second transistor can be bipolar transistors, in which the second transistor has an emitter area that is larger than an emitter area of the first transistor. The compensation circuit can further include a compensating bipolar transistor connected to the first transistor of the current mirror circuit and connected to the master bipolar transistor. The compensating bipolar transistor can be configured to supply the reference current equal to I B  to the first transistor of the current mirror circuit. 
   In general, in another aspect, this specification describes a current mirror circuit having a first transistor of a first conductive type, a second transistor of the first conductive type, a third transistor of the first conductive type, a fourth transistor having three terminals, a fifth transistor having three terminals, and a plurality of sixth transistors of the first conductive type. 
   The first transistor has a collector and a base each connected to a reference current source. The second transistor has a base that is connected to the base of the first transistor. The third transistor has an emitter connected to a collector of the second transistor. The fourth transistor has a first terminal connected to a power supply, and a second and third terminal each connected to a base of the third transistor. The fifth transistor has a first terminal connected to a power supply, a second terminal connected to the second terminal of the fourth transistor and connected to the third terminal of the fourth transistor, and a third terminal connected to a junction between the bases of the first transistor and the third transistor. Each of the plurality of sixth transistors have a base connected to the base of the first transistor. 
   Particular implementations can include one or more of the following features. The first conductivity type can be NPN or PNP. The fourth transistor and the fifth transistor can be p-type MOSFET transistors. The fourth transistor and the fifth transistor can have a different width-to-length size ratio. The width-to-length size ratio of the fourth transistor to the fifth transistor can be 1:(n+1), where n is the number of transistors having bases that are commonly connected to the base of the first transistor. The fourth transistor and the fifth transistor can be bipolar transistors. The bipolar transistors can have different emitter areas. 
   In general, in another aspect, this specification describes a disk drive system. The disk drive system includes a read head configured to sense changes in magnetic flux on a surface of a disk, and generate a corresponding analog read signal. The disk drive further includes a preamplifier configured to receive the analog read signal, and amplify the analog read signal using one or more current sources from a current mirror circuit; and a read channel configured to receive the amplified analog read signal and generate a digital read signal based on the amplified analog read signal. 
   The current mirror circuit includes a reference current source and one or more slave bipolar transistors each configured to mirror the reference current source in accordance with a master bipolar transistor, and supply an output current as a current source to the preamplifier. The current mirror circuit further includes a compensation circuit configured to generate a compensating base current to the one or more slave bipolar transistors, in which n is equal to a total number of the one or more slave bipolar transistors, and I B  represents a base current flowing to the master bipolar transistor. 
   In general, in another aspect, this specification describes a method for generating a compensating base current for a bipolar transistor current mirror circuit. The method includes generating a reference current source, mirroring the reference current source using one or more slave bipolar transistors in accordance with a master bipolar transistor, and generating a compensating base current that is supplied to the one or more slave bipolar transistors. A value of the compensating base current is substantially equal to (n+1)I B , in which n is equal to a total number of the one or more slave bipolar transistors, and I B  represents a base current flowing to the master bipolar transistor. 
   Implementations may include one or more of the following advantages. A stable current mirror circuit is provided—i.e., a current feedback loop in the current mirror circuit (used to perform base current compensation) is provided that does not have a tendency to oscillate. The current mirror circuit does not require additional capacitors to stabilize the current feedback loop. In addition, base current compensation is achieved in a current mirror circuit using a minimum number of circuit elements that can be easily scaled for reduced power consumption and size. In addition, the current mirror circuit requires minimum input headroom—i.e., the current mirror circuit can have an input voltage designed to be a few hundred millivolts above a base voltage associated with a compensating bipolar transistor. 
   The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. 

   
     DESCRIPTION OF DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional current mirror circuit. 
       FIG. 2  is a schematic diagram of a current mirror circuit. 
       FIG. 3  is a schematic block diagram of a hard disk drive system. 
   

   Like reference symbols in the various drawings indicate like elements. 
   DETAILED DESCRIPTION 
     FIG. 2  shows a current mirror circuit  200  with base current compensation that outputs a plurality of output currents I 1 , . . . I n , where n is an integer that is greater than zero. Output currents I 1 , . . . I n  can be supplied to a plurality of electrical circuits  202 - 1 , . . .  202 -n, respectively. Electrical circuits  202 - 1 , . . .  202 -n can be various types of electrical circuits that require a current source (or a bias current). In one implementation, current mirror circuit  200  includes a master (NPN) bipolar transistor Q i , and slave (NPN) bipolar transistors Q 1 , . . . Q n  having bases that are commonly connected. In one implementation, master bipolar transistor Q i  and slave bipolar transistors Q 1 , . . . Q n  have emitter areas of substantially a same size. 
   The emitters of master bipolar transistor Q i  and slave bipolar transistors Q 1 , . . . Q n  are connected to a power supply V SS  (e.g., ground) through corresponding resistors R i , R C , R 1 , . . . R n . The collector of master bipolar transistor Q i  is connected to a reference current source I REF . The collectors of slave bipolar transistors Q 2 , . . . Q n  are respectively connected to electrical circuits  202 - 1 , . . .  202 -n. The collector of slave bipolar transistor Q 1  is connected to the emitter of compensating (NPN) bipolar transistor Q C . The collector of compensating bipolar transistor Q C  is connected to a power supply V DD  (e.g., 5V), and the base of compensating bipolar transistor Q C  is connected to a drain of p-type MOSFET transistor M 2 . The source of MOSFET transistor M 2  is connected to power supply V DD . The gate of MOSFET transistor M 2  is connected to the drain of MOSFET transistor M 2 , and also connected to a gate of p-type MOSFET transistor M 1 . 
   MOSFET transistors M 1 , M 2  form a current mirror circuit  204  that uses a base current of compensating bipolar transistor Q C  as a reference current. In one implementation, the size ratio—i.e., the width-to-length ratio—of MOSFET transistor M 2  to MOSFET transistor M 1  is 1:(n+1), where n is equal to a number of slave transistors having bases that are commonly connected to master bipolar transistor Q i . The source of MOSFET transistor M 1  is connected to power supply V DD , and the drain of MOSFET transistor M 1  is connected to a junction between bases of master bipolar transistor Q i  and slave bipolar transistor Q 1 , referred to herein as node  206 . The drain of MOSFET transistor M 1  forms the output of current mirror circuit  204  which supplies an output current I SUM  to node  206 . 
   Base current-related errors in slave bipolar transistors Q 1 , . . . Q n  are compensated by a current feedback loop  208  formed by slave bipolar transistor Q 1 , compensating bipolar transistor Q C  and MOSFET transistors M 1 , M 2 . In an implementation where master bipolar transistor Q i  and slave bipolar transistors Q 1 , . . . Q n  have emitter areas of substantially a same size, base current-related errors are reduced (or eliminated) when an equal amount of base current flows to each of slave bipolar transistors Q 1 , . . . Q n  as flows to master bipolar transistor Q i . Operation of current feedback loop  208  will now be described. 
   Slave bipolar transistor Q 1  and compensating bipolar transistor Q C  each have a respective gain—i.e., current amplification factor β Q1 , β Qc —such that the base current flowing into compensating bipolar transistor Q C  is substantially equal to I B , where I B  represents the base current flowing into master bipolar transistor Q i . In one implementation, the base current I B  flowing into master bipolar transistor Q i  can be expressed by the following equation: 
                     I   B     =       I     R   ⁢           ⁢   E   ⁢           ⁢   F         β     Q   ⁢           ⁢   i           ,           (     eq   .           ⁢   1     )               
where β Qi , is the current amplification factor of master bipolar transistor Q i .
 
   As discussed above, the base current of compensating bipolar transistor Q C  serves as a reference current source for current mirror circuit  204 . In one implementation, the size ratio (i.e., the width-to-length ratio) of MOSFET transistor M 2  to MOSFET transistor M 1  is set to 1:(n+1) to attain an input/output current ratio (for current mirror circuit  204 ) of 1:(n+1), where n is the number of slave transistors having bases that are commonly connected to master bipolar transistor Q i . In one implementation, output current I SUM  of current mirror circuit  204  (through the drain of MOSFET transistor M 1  to node  206 ) can be expressed as follows:
 
 I   SUM =( n+ 1) I   B,   (eq. 2)
 
where I B  is as given above in equation 1, and n is equal to a number of slave transistors having bases that are commonly connected to master bipolar transistor Q i . At node  206 , output current I SUM  divides such that a current equal to I B  flows to the base of master bipolar transistor Q i  and a total current equal to n(I B ) flows to bases of slave transistors Q 1 , . . . Q n . Thus, an equal amount of base current substantially flows to each of slave bipolar transistors Q 1 , . . . Q n  as flows to master bipolar transistor Q i .
 
   Current mirror circuit  200  can be used in a wide range of applications. For example, current mirror  200  can be used with circuitry of a disk drive system  300 , as shown in  FIG. 3 . 
   In a read operation, an appropriate sector of a disk (not shown) is located and data that has been previously written to the disk is detected. A read/write head  302  senses changes in magnetic flux on a surface of the disk, and generates a corresponding analog read signal. Preamplifier  304  receives the analog read signal. In one implementation, current mirror circuit  200  supplies one or more reference current sources to preamplifier  302 , for amplifying the analog read signal. The amplified analog read signal is provided to read channel  306 . Read channel  306  conditions the amplified analog read signal and, in one implementation, detects “zeros” and “ones” from the signal to generate a digital read signal. Read channel  306  may condition the digital read signal by further amplifying the digital read signal to an appropriate level using, for example, automatic gain control (AGC) techniques. Read channel  306  may then filter the amplified digital read signal to eliminate unwanted high frequency noise, perform data recovery, and format the digital read signal. The digital read signal can be transferred from read channel  306  and stored in memory (not shown). 
   Various implementations have been described. Nevertheless, it will be understood that various modifications may be made. For example, the size ratio between MOSFET transistor M 2  to MOSFET transistor M 1  can be set to a ratio other than 1:(n+1) based on base current requirements of one or more of master bipolar transistor Q i  and slave bipolar transistors Q 1  . . . Q n . Furthermore,  FIG. 2  shows current mirror circuit  200  as a current sinking type that includes master NPN bipolar transistor Q i  and slave NPN bipolar transistors Q 1 , . . . Q n , however, current mirror circuit  200  can be implemented as a current sourcing type having PNP bipolar transistors. In addition, MOSFET transistors M 1 , M 2  can be substituted with bipolar transistors having different emitter areas. Accordingly, other implementations are within the scope of the following claims.