Abstract:
An improved method of preventing computer malfunction during a change of power consumption states is disclosed. The computer operates a microprocessor at a specified voltage during a normal operation. To offset the normal decrease in voltage due to an instantaneous increase in power requirements during a change of power consumption states, the specified voltage is increased prior to entering a higher power consumption state such that the voltage level remains within minimum operating limits.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to operating voltages during normal and lower power consumption states on circuit boards implementing semiconductor chips. 
     2. Background 
     Computers historically have operated at two power consumption states: OFF and ON. During the ON state, the computer operates at a maximum specified voltage levels and maximum power consumption. During the OFF state, the computer is not operational, the voltage levels are zero, and power consumption is zero. With the advent of laptop computers and energy efficient desktop computers, computer designers have introduced the concept of lower power consumption states during regular computer operation. To establish lower power consumption states, unused portions of circuitry are shut off or put into a standby state. In some low power consumption states, the computer microprocessor clock is slowed down or turned off. 
     The microprocessor is a large power consumer in a computer, consuming more power and drawing more current at higher speeds. The microprocessor typically can operate at various voltages, consuming more power at higher voltage levels. The microprocessor is very sensitive to voltage levels. The higher the voltage level, the faster the operating speed capability and the higher the power consumption. The lower the voltage level, the slower the operating speed capability and the lower the power consumption. At voltages below a certain level, the microprocessor malfunctions. Microprocessor manufacturers strive to lower power consumption by lowering operating voltage levels while optimizing the operating speed capability of microprocessors. 
     During the changing of a computer from one power consumption state to another, the power consumption changes instantaneously. Stopping or starting the microprocessor clock changes the power requirements on a computer circuit board instantaneously. Current draw from the microprocessor may change from as little as 0.3 amps to as much as 10 amps in one microprocessor clock cycle. The power supply cannot instantaneously increase or decrease power output and may take several microseconds to regulate the power output. As a result, after a change in power consumption state of the computer, the voltage level output from the power supply experiences large dips and rises due an increase or decrease of current draw. When the state of the computer changes from a higher to lower power consumption rate, the voltage level rises as the current draw from the computer decreases. The power supply decreases the power output and the voltage level returns to normal. When the state of the computer changes from a lower power consumption rate, the voltage level falls as the current draw from the computer increases. The power supply increases the power output and the voltage level returns to normal. At times, the voltage level may dip below the minimum operating voltage of the microprocessor, causing the computer to malfunction. When the voltage drops below the minimum operating voltage of the microprocessor, internal timing requirements may not be met causing incorrect data to be fetched from cache or other such errors. 
     To keep the voltage level within an operational range, computer designers have added large capacitors to computer circuit boards. The large capacitors are expensive and use valuable circuit board space, making them an undesirable solution. 
     SUMMARY OF THE INVENTION 
     A method of preventing computer malfunction during a change of power consumption states while reducing capacitor requirements is disclosed. Prior to a transition from a lower power consumption state to a higher power consumption state the voltage level supplied by the power supply is increased such that when the computer returns to the higher power consumption state, the voltage level remains within minimum operating limits. 
     A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     So that the manner in which the above recited advantages and features of the present invention, as well as others which will become apparent, are attained and can be understood in detail, a more particular description of the invention summarized above may be had by reference to the embodiment thereof which is illustrated in the appended drawings, which drawings form a part of this specification. It is to be noted, however, that the appended drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
     FIG. 1 is a block diagram of a typical circuit board implementation. 
     FIG. 2 is a graph showing the voltage level output from a typical power supply during state changes of the typical circuit board not implementing corrective capacitors. 
     FIG. 3 is a block diagram of the preferred embodiment of a circuit board implementing the present invention. 
     FIG. 4 is a graph showing the voltage level output from a typical power supply during state changes of the typical circuit board implementing a first embodiment of the present invention. 
     FIG. 5 is a graph showing the voltage level output from a typical power supply during state changes of the typical circuit board implementing a second embodiment of the present invention. 
     FIG. 6 is a preferred embodiment of a feedback circuit of the typical computer circuit board implementing the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 1 is a block diagram of a typical circuit board implementation. Power supply  10  supplies voltage VC 1  to load  20  and feedback circuit  30 . Power supply  10  is typically a linear or a switching power supply. Load  20  is a circuit containing, among other things, semiconductor chips such as a microprocessor and memory. Load  20  is capable of multiple power consumption states. Feedback circuit  30  monitors voltage VC 1 . Feedback signal FB 1  from feedback circuit  30  is sent to power supply  10  to indicate adjustments required in voltage levels. Power supply  10  adjusts the power output to maintain voltage VC 1  within desired levels. As the power requirements of load  20  change, the voltage VC 1  experiences dips and rises since power supply  10  cannot instantaneously regulate its power output level. 
     FIG. 2 is a graph showing the voltage level output from a typical power supply during state changes of the typical circuit board not implementing corrective capacitors. Two cycles of state changes from normal to low power consumption states are shown from left to right. VX 1  is the minimum operating voltage of load  20 . When the voltage drops below VX 1 , load  20  malfunctions. VY 1  is the typical operating voltage of load  20 . VZ 1  is an arbitrary voltage level above VY 1 . Full operation of load  20  still occurs at VZ 1 . During the state On 1 , voltage output of power supply  10  remains approximately VY 1 . State On 1  is a normal power consumption state of load  20 . During a normal power consumption state of load  20 , the computer is fully functional, operating at maximum speeds and voltage levels, and consuming maximum power. FIG. 2 does not show an off state, where VC 1  is zero volts, the computer is not functional and is consuming minimum power. 
     At time A, the state changes from state On 1  to state Low 1 . State Low 1  is a low power consumption state of load  20 . Due to the change in power consumption of load  20  and the inability of the power supply to instantaneously regulate power output, voltage VC 1  rises above VZ 1 . Voltage VC 1  slowly decreases back to VY 1  as power supply  10  adjusts the power and voltage levels. 
     At time B, the state of load  20  changes from state Low 1  to state On 2 . State On 2  is a normal power consumption state of load  20 . State Low 1  was of a short duration such that voltage VC 1  has not fully decreased and stabilized at VY 1 . Due to the increase in power consumption of load  20 , voltage VC 1  dips below VY 1 . Voltage VC 1  slowly increases back to VY 1  as power supply  10  adjusts the power and voltage levels. 
     At time C, the state of load  20  changes from state On 2  to state Low 2 . State Low 2  is a low power consumption state of load  20 . Due to the decrease in power consumption of load  20 , voltage VC 1  rises above VZ 1 . Voltage VC 1  slowly decreases back to VY 1  as power supply  10  adjusts the power and voltage levels. 
     At time D, the state of load  20  changes from state Low 2  to state On 3 . State On 3  is a normal power consumption state of load  20 . State Low 2  was of a long duration such that voltage VC 1  has fully decreased and stabilized at VY 1 . Due to the increase in power consumption of load  20 , voltage VC 1  dips below VX 1 , the minimum operating voltage of load  20 . When voltage VC 1  dips below VX 1 , the semiconductor chips in load  20  malfunction. 
     The malfunction of the semiconductor chips in load  20  can be prevented by adding expensive and bulky capacitors to load  20  to stabilize the voltage VC 1  around VY 1 . 
     FIG. 3 is a block diagram of the preferred embodiment of a circuit board implementing the present invention. Power supply  110  supplies voltage VC 2  to load  120  and feedback circuit  130 . Power supply  110  is typically a linear or a switching power supply. Load  120  is a circuit containing, among other things, semiconductor chips such as a microprocessor, memory and power consumption state logic. Load  120  is capable of operating at multiple power consumption states. The state signal ST 2 , sent from load  120  to feedback circuit  130 , communicates power consumption state information of load  120 . The state information communicated may indicate the current power consumption state at which load  120  is operating or indicate upcoming power consumption state change information. Feedback circuit  130  monitors voltage VC 2  and state signal ST 2  and generates feedback signal FB 2 . Feedback signal FB 2  from feedback circuit  130  is sent to power supply  110  to indicate adjustments required in voltage levels. Power supply  110  adjusts the power output to maintain voltage VC 2  within desired levels. 
     FIG. 4 is a graph showing the voltage level output from a typical power supply during state changes of the typical circuit board implementing a first embodiment of the present invention. In this first embodiment, state signal ST 2  of FIG. 3 indicates the current power consumption state of load  120 . During a lower power consumption state the voltage level VC 2  supplied by power supply  110  is increased such that when the computer returns to a higher power consumption state, the voltage level VC 2  remains within minimum operating limits. 
     Two cycles of state changes from normal to low power consumption states are shown from left to right. VX 2  is the minimum operating voltage of load  120 . When the voltage drops below VX 2 , load  120  malfunctions. VY 2  is the typical operating voltage of load  120 . VZ 2  is a voltage level above VY 2  such that a state change from a low power consumption state to a higher power consumption state will not cause voltage VC 2 , starting from VZ 2 , to dip below the minimum operating voltage VX 2 . During the State On 4 , the voltage output of power supply  110  remains at approximately VY 2 . State On 4  is a normal power consumption state of load  120 . During a normal power consumption state of load  120 , the computer is fully functional, operating at maximum speeds and voltage levels, and consuming maximum power. FIG. 4 does not show an off state, where VC 2  is zero volts, the computer is not functional and is consuming minimum power. 
     At time A, the state changes from State On 4  to State Low 4 . Low 4  is a low power consumption state of load  120 . At time A, state signal ST 2  also changes to indicate the change in power consumption states. The change in the state signal ST 2  causes feedback circuit  130  to cause feedback signal FB 2  to indicate to power supply  110  to drive output voltage VC 2  to VZ 2 . Due to the change in power consumption of load  120 , voltage VC 2  rises above VZ 2 . Voltage VC 2  slowly decreases back to VZ 2  as power supply  110  adjusts the power and voltage levels. 
     At time B, the state of load  120  changes from state Low 4  to state On 5 . State On 5  is a normal power consumption state of load  120 . At time B, state signal ST 2  also changes to indicate the change in power consumption states. The change in the state signal ST 2  causes feedback circuit  130  to cause feedback signal FB 2  to indicate to power supply  110  to drive output voltage VC 2  to VY 2 . State Low 4  was of a short duration such that voltage VC 2  has not fully decreased and stabilized at VZ 2 . Due to the increase in power consumption of load  120 , voltage VC 2  dips below VY 2 . Voltage VC 2  slowly increases back to VY 2  as power supply  110  adjusts the power and voltage levels. 
     At time C, the state of load  120  changes from state On 5  to state Low 5 . State Low 5  is a low power consumption state of load  120 . At time C, state signal ST 2  also changes to indicate the change in power consumption states. The change in the state signal ST 2  causes feedback circuit  130  to cause feedback signal FB 2  to indicate to power supply  110  to drive output voltage VC 2  to VZ 2 . Due to the decrease in power consumption of load  120 , voltage VC 2  rises above VZ 2 . Voltage VC 2  slowly decreases back to VZ 2  as power supply  110  adjusts the power and voltage levels. 
     At time D, the state of load  120  changes from state Low 5  to state On 6 . State On 6  is a normal power consumption state of load  20 . State Low 5  was of a long duration such that voltage VC 2  has fully decreased and stabilized at VZ 2 . Due to the increase in power consumption of load  120 , voltage VC 2  dips below VY 2 , but not below VX 2 . 
     The first embodiment of the present invention increases the average operating voltage during low power consumption states. During the change of states from lower to higher power consumption states, the voltage does not dip below non-functional levels. By only increasing the voltage VC 2  during low power consumption states, overall power consumption of load  120  is only nominally affected. The need for large, expensive capacitors on the circuit board is reduced. 
     FIG. 5 is a graph showing the voltage level output from a typical power supply during state changes of the typical circuit board implementing a second embodiment of the present invention. In this second embodiment, state signal ST 2  of FIG. 3 indicates an upcoming state change of load  120  from a lower to a higher power consumption state. A change in state signal ST 2  needs to precede a change in power consumption state of load  120  an amount of time sufficient for power supply  110  to increase the voltage level VC 2  to a level such that when load  120  changes states from a lower to a higher power consumption state the voltage VC 2  does not dip below operational levels of load  120 . 
     One cycle of state changes from normal to low power consumption states are shown from left to right. VX 2  is the minimum operating voltage of load  120 . When the voltage VC 2  drops below VX 2 , load  120  malfunctions. VY 2  is the typical operating voltage of load  120 . VZ 2  is a voltage level above VY 2  such that a state change from a low power consumption state to a higher power consumption state will not cause voltage VC 2 , starting from VZ 2 , to dip below the minimum operating voltage VX 2 . During the State On 7 , the voltage output of power supply  110  remains at approximately VY 2 . State On 7  is a normal power consumption state of load  120 . During a normal power consumption state of load  120 , the computer is fully functional, operating at maximum speeds and voltage levels, and consuming maximum power. FIG. 5 does not show an off state, where VC 2  is zero volts, the computer is not functional and is consuming minimum power. 
     At time A, the state changes from State On 7  to State Low 7 . Low 7  is a lower power consumption state of load  120 . Due to the change in power consumption of load  120 , voltage VC 2  rises above VZ 2 . Voltage VC 2  slowly decreases back to VZ 2  as power supply  110  adjusts the power and voltage levels. 
     Just prior to time B, state signal ST 2  changes to indicate an upcoming change in power consumption states. The change in the state signal ST 2  causes feedback circuit  130  to cause feedback signal FB 2  to indicate to power supply  110  to drive output voltage VC 2  to VZ 2 . State signal ST 2  always precedes a change in power consumption state of load  120  such that the voltage VC 2  is driven to and stabilized at VZ 2  prior to the change of power consumption state of load  120 . 
     At time B, voltage level VC 2  is VZ 2 , and the state of load  120  changes from state Low 7  to state On 8 . State On 8  is a normal power consumption state of load  120 . Due to the increase in power consumption of load  120 , voltage VC 2  dips below VY 2 , but not below VX 2 . 
     Some time after time B, state signal ST 2  also changes to indicate to the feedback circuit  130  to cause feedback signal FB 2  to indicate to power supply  110  to drive output voltage VC 2  to VY 2 . 
     The second embodiment of the present invention increases the average operating voltage just prior to a transition from a low power consumption state to a higher power consumption state. During the change of states of load  120  from lower to higher power consumption states, the voltage does not dip below non-functional levels. By only increasing the voltage VC 2  just prior to the transition from a lower power consumption state to a higher power consumption state, overall power consumption of load  120  is only nominally affected. The need for large, expensive capacitors on the circuit board is reduced. 
     FIG. 6 is a preferred embodiment of a feedback circuit of the typical computer circuit board implementing the present invention. Shown is a very simple feedback circuit. The addition of voltage requirements, power planes on the circuit board, multiple power consumption states, and various other features will increase the complexity of the feedback circuit. 
     Voltage level VC 2  is input to a first terminal of resistor R 1 . A second terminal of resistor R 1  is connected to a first terminal of resistor R 2 , a first terminal of resistor R 3  and is feedback signal FB 2 . A second terminal of resistor R 2  is connected to a ground signal, GRND. A second terminal of resistor R 3  is connected to a source terminal of FET F 4 . A drain terminal of FET F 4  is connected to the ground signal, GRND. A gate terminal of FET F 4  is connected to state signal ST 2 . 
     State signal ST 2  turns FET F 4  on and off. FET F 4  is off when state signal ST 2  is low, during the On States shown in FIG. 4 of the first embodiment of the present invention, and most of the On and Low states of FIG. 5 of the second embodiment of the present invention. The On States are normal power consumption states of load  120 , the computer is fully functional, operating at maximum speeds and voltage levels, and consuming maximum power. Resistors R 1  and R 2  are values such that when FET F 4  is off, feedback signal FB 2  indicates to power supply  110  to regulate voltage VC 2  to load  120  at voltage level VY 2 . 
     FET F 4  is on when state signal ST 2  is high, during the Low States shown in FIG. 4 of the first embodiment of the present invention, and just prior to and just after a change from lower to higher power consumption state of load  120  of FIG.  5 . The Low States are lower power consumption states of load  120 . Resistor R 3  is a value such that when FET F 4  is on, feedback signal FB 2  indicates to power supply  110  to regulate voltage VC 2  to load  120  at voltage level VZ 2 . 
     The present invention increases the average operating voltage during low power consumption states or just prior to a transition from a lower power consumption state to a higher power consumption state. During the change of states from lower to higher power consumption states, the voltage does not dip below non-functional levels. 
     The present invention corrects the problem of voltage dipping into non-functional levels by increasing the voltage output supplied by the power supply during the transition from lower to higher power consumption states. By only increasing the voltage during this time, overall power consumption is only nominally affected. The need for large, expensive capacitors on the circuit board is reduced. 
     Although the description above describes only two different power consumption states, the present invention can be extended to multiple power consumption states and multiple voltage levels. The multiple states may be achieved by assigning different states to different operating speeds of the microprocessor and different on, off and standby conditions of various computer peripherals. 
     Although the present invention has been fully described above with reference to specific embodiments, other alternative embodiments will be apparent to those of ordinary skill in the art. Therefore, the above description should not be taken as limiting the scope of the present invention which is defined by the appended claims.