Abstract:
Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM  300  requires less effort.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     This application claims the benefit of Korean Patent Application No. 10-2004-0072471, filed on Sep. 10, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor package, and more particularly, to a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC packages are mounted.  
         [0004]     2. Description of the Related Art  
         [0005]     The trend in the semiconductor industry is to make semiconductor products compact, thin, light, highly integrated, and highly densified. This trend is also applied to dual inline memory modules (hereinafter, referred to as DIMMs) on each of which semiconductor memory devices are mounted. Board-on-chip (BOC) packages are well known and used for, for example, high-speed dynamic random access memory (DRAM) or the like. Stacked BOC packages have been recognized as convenient and suitable for constructing a high-speed, high-capacity DIMM.  
         [0006]      FIG. 1  illustrates a conventional stacked BOC package  100 . In the conventional stacked BOC package  100 , a first substrate  110  having a cavity  113  in the center is attached to a first semiconductor chip  111 , and contact pads  112  of the first semiconductor chip  111  are bonded to electrode pads  115  of the first substrate  110  via a wire  114 . Similarly, electrode pads  125  of a second substrate  120  are bonded to contact pads  122  of a second semiconductor chip  121  via a wire  124 . The electrode pads  115  of the first substrate  110  are connected to electrode pads  126  on an upper surface of the second substrate  120  via solder bumps  130 . The electrode pads  126  on the upper surface of the second substrate  120  are connected to the electrode pads  125  on a lower surface of the second substrate  120  through via holes  127 , which are filled with metal. The electrode pads  125  on the lower surface of the second substrate  120  are attached to solder bolls  140 .  
         [0007]     In the conventional stacked BOC package  100  signal line load increases with an increase of a package parasitic component caused by the stacked structure. When DIMMs are constructed with a conventional stacked BOC package  100 , signal fidelity cannot be ensured because of the increased load of the signal line. The height of the solder bumps  130  restricts installation or wiring of components in the DIMM. Hence, it is not easy to apply an optimal topology to the DIMM. The DIMM stub is elongated due to the solder bumps  130 , so a signal transmitted to a corresponding solder bump  130  is reflected, thus reducing signal fidelity.  
         [0008]     In addition, when the conventional stacked BOC package  100  is used to construct a DIMM, a separate stacked BOC package must be manufactured so that pin arrangements on both surfaces of the DIMM are mirrored by each other. Developing an extra package increases costs.  
         [0009]     There remains a need for a stacked BOC package having a ball pad structure in which mirroring is achieved and a DIMM with a short stub that results from mounting the stacked BOC package thereon.  
       SUMMARY OF THE INVENTION  
       [0010]     Embodiments of the present invention provide a stacked board-on-chip (BOC) package having a mirroring structure.  
         [0011]     Embodiments of the present invention also provide a dual inline memory module (DIMM).  
         [0012]     According to an aspect of the present invention, a stacked board-on-chip package includes first and second packages, an interposer, and solder balls. The first package includes a first semiconductor chip installed on a first substrate. First electrode pads connected to first contact pads of the first semiconductor chip are connected to first via holes that penetrate the first substrate and are filled with metal. The second package includes a second semiconductor chip installed on a second substrate and is disposed so that a bottom of the second semiconductor chip faces a bottom surface of the first semiconductor chip. Second electrode pads connected to second contact pads of the second semiconductor chip are connected to second via holes that penetrate the second substrate and are filled with the metal. The interposer connects the first via holes to the second via holes. The solder balls are connected to the first electrode pads of the first package or the second electrode pads of the second package.  
         [0013]     According to another aspect of the present invention, a stacked board-on-chip package includes first and second packages, first and second interposers, a heat spread plate, and solder balls. The first package includes a first semiconductor chip installed on a first substrate. First electrode pads connected to first contact pads of the first semiconductor chip are connected to first via holes that penetrate the first substrate and are filled with metal. The first interposer includes a first conductive plug connected to the first via holes. The second package includes a second semiconductor chip installed on a second substrate and is disposed so that a bottom surface of the second semiconductor chip faces a bottom surface of the first semiconductor chip. Second electrode pads connected to second contact pads of the second semiconductor chip are connected to second via holes that penetrate the second substrate and are filled with the metal. The second interposer includes a second conductive plug connected to the second via holes. The heat spread plate is interposed between the first and second interposers, electrically connects the first and second conductive plugs to each other via third via holes filled with metal, and transmits heat away from the first and second semiconductor chips. The solder balls are connected to the first electrode pads of the first package or the second electrode pads of the second package.  
         [0014]     According to another aspect of the present invention, there is provided a dual inline memory module on which each of the above-described stacked board-on-chip packages is mounted. The dual inline memory module includes a printed circuit board, a bottom type stacked board-on-chip package, and a top type stacked board-on-chip package. In the bottom type stacked board-on-chip package, the solder balls are connected to the second electrode pads of the stacked board-on-chip package. In the top type stacked board-on-chip package, the solder balls are connected to the first electrode pads of the stacked board-on-chip package. The bottom type stacked board-on-chip package and the top type stacked board-on-chip package are installed on upper and lower surfaces of the printed circuit board, respectively, and electrically connected to each other. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:  
         [0016]      FIG. 1  illustrates a conventional stacked board-on-chip (BOC) package;  
         [0017]      FIG. 2  illustrates a stacked BOC package according to an exemplary embodiment of the present invention;  
         [0018]      FIG. 3  is an enlarged view with portions broken away of the first or second interposer, as shown in  FIG. 2 ;  
         [0019]      FIG. 4  illustrates another example of the first or second interposer of  FIG. 2  in a view similar to  FIG. 3 ;  
         [0020]      FIG. 5  illustrates a dual inline memory module (DIMM) made up of stacked BOC packages like those shown in  FIG. 2 ;  
         [0021]      FIG. 6  illustrates a multi-stacked BOC package according to another exemplary embodiment of the present invention; and  
         [0022]      FIG. 7  illustrates a stacked BOC package according to still another exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]     The attached drawings illustrating preferred embodiments of the present invention are referred to in order to gain a better understanding of the present invention, the merits thereof, and the objectives accomplished thereby.  
         [0024]     Hereinafter, the present invention will be described in detail by explaining preferred embodiments of the invention with reference to the attached drawings. Like reference numerals in the drawings denote like elements.  
         [0025]      FIG. 2  illustrates a stacked board-on-chip (BOC) package  200  having a mirroring structure, according to an exemplary embodiment of the present invention. Referring to  FIG. 2 , the stacked BOC package  200  is obtained by sequentially stacking a first package  210 , a first interposer  230 , a heat spread plate  240 , a second interposer  250 , and a second package  220 . As will be described, each of the first and second interposers  230  and  250  has a structure that permits the first and second packages  210  and  220  to be electrically connected to each other. The structure of the interposers  230 ,  250  will be described in detail with reference to  FIGS. 3 and 4 .  
         [0026]     First, in  FIG. 2 , the heat spread plate  240  transmits heat away from first and second semiconductor chips  213  and  223 . The heat spread plate  240  may be made of a nickel film, an iron film, an aluminum film, or a metal film which is formed by chemical vapor deposition (CVD). Alternatively, the heat spread plate  240  may be a composite film including one of the nickel film, the iron film, the aluminum film, and the CVDed metal film or an alloy film including two or more of nickel, iron, and aluminum. The heat spread plate  240  may be formed of any material that is preferably adhesive and has good heat conductivity. Although the heat spread plate  240  is interposed between the first and second packages  210  and  220  in the present embodiment, the first and second packages  210  and  220  may be directly stacked one on another without the heat spread plate  240  therebetween.  
         [0027]     The first package  210  includes a first substrate  211  having a first cavity  212 , and the first semiconductor chip  213  having a first pad mounting surface  215  on which a plurality of first contact pads  214  are arranged. The first semiconductor chip  213  is attached and bonded to the first substrate  211  so that the first contact pads  214  of the first pad mounting surface  215  can exist within the first cavity  212 . The first contact pads  214  are connected to first electrode pads  217  of the first substrate  211  via wires  216 . A first encapsulation layer  218 , which may be formed of epoxy resin, is provided to protect the wires  216  connected between the first contact pads  214  and the first electrode pads  217 . Although not visible in the cross-section of  FIG. 2 , at least some of the first electrode pads  217  are connected to first via holes  219 , which penetrate the first substrate  211  and are filled with metal.  
         [0028]     The second package  220  includes a second substrate  221  having a second cavity  222 , and a second semiconductor chip  223  having a second pad mounting surface  225  on which a plurality of second contact pads  224  are arranged. A second semiconductor chip  223  is attached and bonded to the second substrate  221  so that the second contact pads  224  of the second pad mounting surface  225  can exist within the second cavity  222 . The second contact pads  224  are connected to second electrode pads  227  of the second substrate  221  via wires  226 . A second encapsulation layer  228  formed of epoxy resin is provided to protect the wires  226 . The second electrode pads  227  are connected to second via holes  229 , which penetrate the second substrate  221  and are filled with metal.  
         [0029]     A surface opposite to the first pad mounting surface  215  of the first semiconductor chip  213  and a surface opposite to the second pad mounting surface  225  of the second semiconductor chip  223  may be attached to upper and lower surfaces, respectively, of a heat spread plate  240 . The first electrode pads  217  of the first package  210  and the second electrode pads  227  of the second package  220  are disposed to mirror each other centered on the heat spread plate  240 . The first via holes  219  connected to the first electrode pads  217  are electrically connected to the second via holes  229  connected to the second electrode pads  227 , via conductive plugs  232  and  252  within the first and second interposers  230  and  250  and third via holes  242 , which penetrate the heat spread plate  240 . The second electrode pads  227  are connected to solder balls  260 . Hence, the solder balls  260  are disposed in a lower part of the stacked BOC package  200 . Alternatively, the solder balls  260  may be disposed in an upper part of the stacked BOC package  200  to be connected to the first electrode pads  217 .  
         [0030]     Some of the first or second electrode pads  217  or  227  that are not connected to the solder balls  260  are covered with protective layers (not shown). The protective layers are usually photo solder resistors (PSRs) to prevent erosion of the first or second electrode pads  217  or  227 .  
         [0031]      FIG. 3  illustrates an example of the first or second interposer  230  or  250  of  FIG. 2 . Referring to  FIG. 3 , the first interposer  230 , for example, includes a resin base  231  on both sides of which copper plates  232   c  are patterned and formed. The copper plates  232   c  are connected to each other by a via hole  233 , which is formed of copper. Reference numerals  234   a,    234   b,  and  235  are all insulative resist layers for insulative laminating. The copper films  232   c  are electrically connected to upper and lower bonding pattern layers  232   b  and  232   d.  Upper and lower pad electrodes  232   a  and  232   e  are exposed through openings of the insulative resist layers  234   a  and  234   b  and are connected to the bonding pattern layers  232   b  and  232   d,  respectively. The upper and lower pad electrodes  232   a  and  232   e,  the upper and lower bonding pattern layers  232   b  and  232   d,  and the copper plates  232   c  serve as the conductive plug  232  (see  FIG. 2 ) of the first interposer  230 .  
         [0032]      FIG. 4  illustrates another example of the first or second interposer  230  or  250  of  FIG. 2 . Referring to  FIG. 4 , the second interposer  250 , for example, includes a base  251  on which upper and lower pad electrodes  252   a  and  252   c  are formed. The upper and lower pad electrodes  252   a  and  252   c  electrically contact a plug  252   b  with which a via hole  253  of the base  251  is filled. Upper and lower insulative resist layers  254   a  and  254   b  cover upper and lower surfaces of the base  251  while almost surrounding the upper and lower pad electrodes  252   a  and  252   c.  The upper pad electrode  252   a,  the plug  252   b,  and the lower pad electrode  252   c  serve as the conductive plug  252  (see  FIG. 2 ) of the second interposer  250 .  
         [0033]     A structure of a DIMM  300  using the stacked BOC package  200  is shown in  FIG. 5 . Referring to  FIG. 5 , the DIMM  300  is obtained by mounting a stacked BOC package having solder balls installed in its lower part (hereinafter, referred to as a bottom type stacked BOC package  200   b ) and a stacked BOC package having solder balls installed in its upper part (hereinafter, referred to as a top type stacked BOC package  200   t ) on upper and lower surfaces, respectively, of a printed circuit board (PCB)  310 . Due to the installation of the bottom type stacked BOC package  200   b  and the top type stacked BOC package  200   t  on the upper and lower surfaces of the DIMM 300, pin arrangements on both sides of the DIMM 300 are mirrored by each other. Since a height of the bottom type stacked BOC package  200   b  or the top type stacked BOC package  200   t  is greater than a height of the conventional stacked BOC package  100 , the DIMM 300 has a minimum stub length and an optimal topology. Hence, the DIMM 300 can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 is easy.  
         [0034]      FIG. 6  illustrates a multi-stacked BOC package  600  in which three or more stacked BOC packages  200  are stacked, according to another exemplary embodiment of the present invention. Referring to  FIG. 6 , the multi-stacked BOC package  600  is obtained by stacking a plurality of stacked BOC packages  200  while interposing heat spread plates  601 ,  602 ,  603 , and  604  therebetween. Electrode pads of a stacked BOC package  200  located at the bottommost position are connected to solder balls  610 . As described in  FIG. 2 , the heat spread plates  601 ,  602 ,  603 , and  604  are optional, and need not be used in the multi-stacked BOC package  600 .  
         [0035]      FIG. 7  illustrates a stacked BOC package  700  according to still another exemplary embodiment of the present invention. The stacked BOC package  700  is obtained by adding discrete devices  710  to the stacked BOC package  200  of  FIG. 2 . Each of the discrete devices  710  is connected between adjacent first electrode pads  217 . The discrete devices  710  may be each comprised of resistors, decoupling capacitors, or the like to improve electrical characteristics of the first and second semiconductor chips  213  and  223  or electrical characteristics of a DIMM on which the stacked BOC package  700  is to be installed.  
         [0036]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.