Abstract:
A voltage transform circuit transforms a transferred voltage to a desired magnitude of voltage. The voltage transform circuit includes: a first power supply unit for providing a digital voltage (Vdd- 1 ) of a first magnitude; a second power supply unit for providing an analog voltage (Vaa- 2 ) of a second magnitude; and a voltage transform unit formed with a plurality of MOS transistors, wherein the MOS transistors operate to transfer the digital voltage (Vdd- 1 ) from the first power supply unit, and output a digital voltage (Vdd- 3 ) of a third magnitude corresponding to the analog voltage (Vaa- 2 ) transferred from the second power supply unit. By using an analog voltage (Vaa- 2 ) that is higher than the digital voltage (Vdd- 1 ), it becomes possible to increase the magnitude of the output digital voltage (Vdd- 3 ). By supplying this high digital voltage (Vdd- 3 ) to a charge pump, the level of the charge pump is lowered.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims benefit under 35 U.S.C. § 119 from Korean Patent Application No. 2005-14398, filed on Feb. 22, 2005, the entire content of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     Apparatuses and methods consistent with the present invention relates in general to an ultra-low-power voltage transform circuit, and more specifically, to a voltage transform circuit constituted by CMOS elements.  
         [0004]     2. Description of the Related Art  
         [0005]     In some cases, a system needs to transform an external low voltage to a higher voltage. That is, in the case where a voltage required for driving a specific configuration of a circuit element is higher than an externally supplied voltage, it is necessary to transform the externally supplied voltage into the required driving voltage. For instance, a minimum voltage of 15V is required for driving a memory, whereas an externally supplied voltage is typically 1.5V. Therefore, in order to drive the memory, the externally supplied voltage 1.5V should be transformed to 15V.  
         [0006]      FIG. 1  illustrates a conventional voltage transform circuit for transforming an external low voltage to a higher voltage. The following description is based on this voltage transform circuit of  FIG. 1 .  
         [0007]     As shown in the drawing, the voltage transform circuit includes V in  receiving an externally supplied digital power, and V out  for outputting the transformed power. V in  and V out  satisfy the relationship shown in Equation 1 below.  
                 V   out       V   in       =   2           [     Equation   ⁢           ⁢   1     ]             
 
         [0008]     As shown in Equation 1, V out  is dependent on V in . That is, if V in  is small, V out  is also small. Thus, if V out  is used as an input voltage of a charge pump requiring a high voltage, the level of the charge pump is increased to transform V out  to a required voltage. As a result, the circuit efficiency is lowered. Therefore, there is a need to develop a voltage transform circuit capable of transforming a supplied voltage to a desired voltage magnitude.  
       SUMMARY OF THE INVENTION  
       [0009]     Illustrative, non-limiting embodiments of the present invention overcome the above disadvantages and other disadvantages not described above. Also, the present invention is not required to overcome the disadvantages described above, and an illustrative, non-limiting embodiment of the present invention may not overcome any of the problems described above Apparatuses and methods consistent with the present invention provide a voltage transform circuit which is capable of transforming a supplied voltage to a desired voltage magnitude.  
         [0010]     An aspect of an embodiment of the present invention is to provide a voltage transform circuit which is capable of increasing an input voltage to a charge pump, thereby improving the efficiency of the charge pump.  
         [0011]     Another aspect of an embodiment of the present invention is to provide a method for lowering the level of a charge pump by increasing the magnitude of an voltage input to the charge pump.  
         [0012]     In an illustrative, non-limiting embodiment of the present invention, there is provided a voltage transform circuit, including a first power supply unit for providing a digital voltage (Vdd- 1 ) of a first magnitude, a second power supply unit for providing an analog voltage (Vaa- 2 ) of a second magnitude, and a voltage transform unit formed with a plurality of MOS transistors, wherein an operation of each of the MOS transistors is controlled by transferring Vdd from the first power supply unit, and a digital voltage (Vdd- 3 ) of a third magnitude correspondingly to Vaa transferred from the second power supply unit is output.  
         [0013]     The magnitude of the digital voltage Vdd- 1  is smaller than that of the analog voltage (Vaa- 2 ).  
         [0014]     The magnitude of the output digital voltage (Vdd- 3 ) is greater than that of the analog voltage (Vaa- 2 ).  
         [0015]     The magnitude of the output digital voltage (Vdd- 3 ) is twice the analog voltage (Vaa- 2 ).  
         [0016]     If the Vdd- 1  is ‘high’, the output digital voltage (Vdd- 3 ) is ‘high’; and if the Vdd- 1  is ‘low’, the output digital voltage (Vdd- 3 ) is ‘low’.  
         [0017]     The voltage transform circuit comprises seven N-type MOS transistors, and seven P-type MOS transistors.  
         [0018]     Another illustrative non-limiting embodiment of the present invention provides a voltage transform circuit, including a first power supply unit for providing a digital voltage (Vdd- 1 ) of a first magnitude, a second power supply unit for providing an analog voltage (Vaa- 2 ) of a second magnitude, a voltage transform unit formed with a plurality of MOS transistors, wherein an operation of each of the MOS transistors is controlled by transferring Vdd from the first power supply unit, and a digital voltage (Vdd- 3 ) of a third magnitude correspondingly to Vaa transferred from the second power supply unit is output, and a charge pump for receiving the digital voltage (Vdd- 3 ).  
         [0019]     The magnitude of the digital voltage Vdd-1 is smaller than that of the analog voltage (Vaa- 2 ).  
         [0020]     The magnitude of the output digital voltage (Vdd- 3 ) is greater than that of the analog voltage (Vaa- 2 ).  
         [0021]     The magnitude of the output digital voltage (Vdd- 3 ) is twice the analog voltage (Vaa- 2 ).  
         [0022]     If the Vdd- 1  is ‘high’, the output digital voltage (Vdd- 3 ) is ‘high’; and if the Vdd- 1  is ‘low’, the output digital voltage (Vdd- 3 ) is ‘low’.  
         [0023]     The voltage transform circuit comprises seven N-type MOS transistors, and seven P-type MOS transistors.  
         [0024]     The charge pump boosts the transferred voltage Vdd- 3 . 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]     Aspects and features of the present invention will be more apparent by describing certain illustrative, non-limiting embodiments of the present invention with reference to the accompanying drawings, in which:  
         [0026]      FIG. 1  is a circuit diagram for transforming a low input voltage to a high voltage, according to a related art circuit;  
         [0027]      FIG. 2  illustrates an example of a Dickson charge-pump circuit;  
         [0028]      FIG. 3  illustrates the operation of the Dickson charge-pump circuit;  
         [0029]      FIG. 4  is a circuit diagram for transforming a low voltage to a high voltage, according to an embodiment of the present invention; and  
         [0030]      FIG. 5  is a voltage chart illustrating an input voltage and an output voltage to and from a voltage transform circuit of an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0031]     An illustrative non-limiting embodiment of the present invention is described below with reference to the accompanying drawings.  
         [0032]     In general, the voltage magnitude of an RF analog power supply used in an antenna for example is relatively higher than the voltage magnitude of an externally supplied digital power supply. The embodiments of the present invention described here provide methods for transforming a voltage (magnitude) using an analog power supply instead of a digital power supply. First, a charge pump is explained below. A charge pump is a circuit for temporarily supplying a voltage higher than a power supply voltage. Nowadays a semiconductor memory device tends to have a lower power level to reduce energy consumption. Especially, a flash memory device requires a charge pump generating a high voltage for use in erasing data and programs in the flash memory.  
         [0033]      FIG. 2  illustrates the Dickson charge pump as an example of a charge pump.  
         [0034]     The Dickson charge pump (circuit) includes a first MOS transistor M 1  to which an external power supply voltage V out  is applied, and second to fifth MOS transistors M 2 -M 5  to which pumping clock pulses VP 11 , VP 12  are applied. Pumping clock pulses VP 11  and VP 12  have different phases generated by an external oscillator (not shown) and are alternately applied through pump capacitors C 1 -C 4 . A charge storage capacitor Cf is connected to an output terminal of the fifth transistor M 5 .  
         [0035]     With reference to  FIG. 3 , the following describes the operation of the Dickson charge pump (circuit) shown in  FIG. 2 .  
         [0036]     The pump clock pulses VP 11 , VP 12 , each having a frequency of about 60 MHz, are supplied from the external oscillator and are set to the same magnitude as the external power supply voltage V out . These pump clock pulses have a phase difference of 180° from each other. The MOS transistors M 1 -M 5  function as diodes, hence, charge increases in only one direction.  
         [0037]     Those two pump clock pulses VP 11  and VP 12  passing through the pump capacitors C 1 -C 4 , which are coupling capacitors, apply charge in a direction such that the charge increases through the MOS transistors M 2 -M 5 .  
         [0038]     For instance, when the pump clock pulse VP 11  transitions from ‘low’ to ‘high’, and the pump clock pulse VP 12  transitions from ‘high’ to ‘low’, a voltage V 1  applied to a gate side of the MOS transistor M 2  is increased to Vs 1 +Δv as shown in  FIG. 3  by the pumping operation of the pump clock pulse VP 11  through the capacitor C 1 , and the voltage V 2  applied to a gate side of the MOS transistor M 3  is fixed at the value of Vs 2 .  
         [0039]     The voltage Vs 1  and the voltage Vs 2  indicate a steady-state voltage of the voltage V 1  and the voltage V 2 , respectively, and Δv indicates a very small voltage increment resulting from the pumping operation.  
         [0040]     In this case, the MOS transistors M 1 , M 3  are in a reverse bias state, and charge moves from the voltage V 1  state to the voltage V 2  state through MOS transistor M 2 . Here, the requirement for charge pumping is that Δv must be greater than a threshold voltage Vth of MOS transistor M 2 , as expressed below. 
 
Δv&gt;Vth   [Equation 2]
 
         [0041]     A pumping gain Gv 2  at the second level is defined as a difference between the voltage V 1  and the voltage V 2  as expressed below. 
 
 Gv 2 =V 2 −V 1 =Δv−Vth    [Equation 3]
 
         [0042]     However, in Equation 3, the pumping gain is higher than the frequency of a clock, so the voltage V 2  becomes smaller than an expected value.  
         [0043]     In like manner, when the pump clock pulse VP 11  transitions from ‘high’ to ‘low’, and the pump clock pulse VP 12  transitions from ‘low’ to ‘high’, charge moves from the voltage V 2  state to the voltage V 3  state through MOS transistor M 3 .  
         [0044]     The above-described operation is performed equally in the other MOS transistors M 3 -M 5 , so that the voltage V 5  present at a final terminal is higher than the applied power supply voltage V out .  
         [0045]     A desired voltage magnitude can be obtained by increasing the number of MOS transistors, or by increasing the magnitude of an applied power supply voltage. However, when the number of MOS transistors is increased, the efficiency of the charge pump (circuit), which consumes a large amount of current, is lowered. To overcome this drawback, a method is described here for increasing the magnitude of the power supply voltage applied to the charge pump (circuit).  
         [0046]      FIG. 4  is a circuit diagram illustrating a method for increasing the magnitude of a power supply voltage applied to the charge pump, in accordance with one embodiment of the present invention.  
         [0047]     A voltage transform unit shown in  FIG. 4  includes a plurality of CMOS transistors. The voltage transform unit receives power from an external power supply unit (not shown). That is, the external power supply unit provides the voltage transform unit with power signals BSP, CK, BSN, Vdd, Vss, Vaa, etc.  
         [0048]     BSP provides power to the gates of MP 1  and MP 4 , and BSN provides power to the gates of MN 2  and MN 5 . BSP and BSN are current limiting bias terminals which limit a current flowing to the upper and lower input terminals of an inverter to realize an ultra low power of nA. In other words, MP 2  and MN 1  operate as one inverter, and the MP 5  and the MN 4  operate as one inverter. Thus, MP 1 , which receives power from BSP, limits a current transferring to the inverter realized by MP 2  and MN 1 . Likewise, MP 4 , which receives power from BSP, limits a current transferring to the inverter realized by MP 5  and MN 4 . Similarly, MN 2 , which receives power from BSN, limits a current transferring to the inverter realized by MP 2  and MN 1 . Moreover, MN 5 , which receives power from BSN, limits a current transferring to the inverter realized by MP 5  and MN 4 .  
         [0049]     CK provides power to the upper and lower input terminals of the inverters to transform a low input voltage to a high voltage. When an input voltage to CK is ‘low’, an output voltage V out  of MMN 2  is also ‘low’. Also, when an input voltage to CK is ‘high’, the output voltage V out  of MMN 2  also is ‘high’. In this case, if an input voltage to CK is ‘high’, MP 2  and MP 5  are turned off, MMN 2  is turned off and MMP 2  is turned on. The magnitude of the output voltage V out  becomes the drain voltage Vdd of MMP 2 . Vdd of MMP 2  is a sum of a gate voltage and a source voltage Vaa at MMP 2 .  
         [0050]     The gate voltage at MMP 2  equals a drain voltage of MMP 1  and the drain voltage of MMP 1  is obtained by subtracting a voltage drop of a diode from the source voltage Vaa, i.e., ‘Vaa—voltage drop of diode’. Therefore, if the magnitude of the voltage drop of the diode is ignored, the drain voltage of MMP 1  becomes Vaa, and V out  equals to 2 Vaa.  
         [0051]      FIG. 5  is a voltage chart showing a relationship between the CK signal and output voltage V out  of the power supply voltage transform circuit of  FIG. 4  according to an embodiment of the present invention. As shown in  FIG. 5 , when the magnitude of CK is 1.5V, the output voltage V out  is 6V and the signals are in phase with one another. In the related art, when the magnitude of CK (Vdd) is 1.5V, the output voltage V out  was 3V. However, here, the output voltage V out  from the voltage transform circuit is 6V (=2 Vaa). In this manner, V out  is made to depend on Vaa, instead of making V out  depend on Vdd as in the related art. By using Vaa higher than Vdd, it becomes possible to increase the magnitude of a voltage applied to the charge pump, and reduce the level of the charge pump.  
         [0052]     As explained so far, by using Vaa in addition to Vdd, the voltage transform circuit is able to transform a low input voltage to a high voltage. Since the output voltage from the voltage transform circuit of  FIG. 4  is higher than that of the related art, the level of the charge pump can be reduced. This in turn reduces power consumption at the charge pump, and the efficiency of the charge pump can be improved.  
         [0053]     The foregoing embodiment and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. Also, the description of the embodiments of the present invention is intended to be illustrative, and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.