Abstract:
In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Description:
This application is a division of application Ser. No. 09/473,635, filed Dec. 28, 1999, which is now U.S. Pat. No. 6,251,773. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of semiconductor device testing; more specifically, it relates to a structure for visual and electrical test (probing/diagnostics) of semiconductor devices using fill shape patterns incorporated into wiring levels and methods for forming these structures. 
     BACKGROUND OF THE INVENTION 
     Advanced semiconductor devices increasingly require more complex wiring schemes to wire together individual elements into circuits. These schemes rely on multilevel structures formed from wiring levels containing conductive wires and interconnect levels containing conductive vias that connect conductive wires on two different wiring levels together. 
     Fabrication of such multilevel structures often requires the use of a fabrication technique called chemical-mechanical-polishing (CMP) of the wiring levels and the interconnect levels. However CMP can cause variations in the flatness of the top surface of semiconductor devices severe enough to effect the quality of the photolithographic process steps used to define the patterns of wires and vias in the wiring and interconnect levels. Variations in flatness occur most frequently on the wiring levels and are caused by differences in conductive wire densities from region to region on the surface semiconductor level being then fabricated. This creates differences in polish rate so more or less material is removed from one region than another. In an attempt to solve this problem, methods have been developed that distribute fill shapes, formed at the same time and of the same material as the conductive wires, in such a manner as to attempt to keep the density of conductive material and therefore the polishing rate, the same in all regions. Fill shapes are isolated from the conductive wires and do not carry electrical signals or power. Fill shapes are added to the design data during the design process. 
     FIG. 1 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes as presently practiced. Semiconductor device  1  is comprised of substrate  10  and via levels  20 ,  40 ,  60 ,  80 ,  100 , and  120  alternating with wiring levels  30 ,  50 ,  70 ,  90 ,  110 , and  130 . Passivation level  140  seals the device. Wiring levels  50 ,  70 ,  90 ,  110 , and  130 , in addition to having conductive wires also have fill shapes. Fill shapes are designated by the letter “F” in order to more easily distinguish them for the reader. Fill shapes are conductive as well. Conductive level  50  has conductive wire  50 A and fill shapes  52 A through  52 H. Conductive level  70  has conductive wires  70 A through  70 C and fill shapes  72 A and  72 B. Conductive level  90  has conductive wire  90 A and  90 B and fill shapes  92 A through  92 F. Conductive level  110  has conductive wire  110 A and  110 B and fill shapes  112 A through  112 C. Conductive level  130  has conductive wires  130 A and  130 B and fill shapes  132 A through  132 D. Via level  20  has vias  20 A through  20 C connecting conductive wire  30 A with substrate  10  and vias  20 D and  20 E connecting conductive wire  30 B with substrate  10 . Via level  40  has via  40 A connecting conductive wire  30 B with conductive wire  50 A. Via level  60  has via  60  A connecting conductive wire  50 A with conductive wire  70 C. Via level  80  has via  80 A connecting conductive wire  70 A with conductive wire  90 A. Via level  100  has via  100 A connecting conductive wire  90 A with conductive wire  110 A and via  100 B connecting conductive wire  90 B with conductive wire  110 B. Via level  120  has via  120 A connecting conductive wire  110 A with conductive wire  130 A and via  120 B connecting conductive wire  110 B with conductive wire  130 B. All the conductive wires, vias, and fill shapes are held in a matrix of insulator  15  which may be the same insulating material or a different insulating material level to level. 
     In general insulators are optically transparent or semitransparent while conductors are not in the thickness&#39; used in semiconductor devices. As may be readily seen from FIG. 1, the placement of fill shapes of each of the wiring levels has been done independent of any other level so that when doing a visual inspection fill shapes on higher levels can block line of sight views to the lower wiring and interconnect levels of the device, limiting the usefulness of visual inspection for cause of fail or reliability assessment. For example, in FIG. 1, only conductive wires  130 A,  130 B and  110 A are directly visible, fill shapes  112 A,  112 B,  112 C, and  92 F blocking the line of sight from the top surface. 
     Additionally, should electrical probing of lower levels be desired, the fill shapes block direct access to the lower levels either forcing removal of higher levels and subsequent loss of some or all of the device functionality or the milling of an access hole through the dielectric  15  and fill shapes in the path with the problematic differing etch/mill rates associated with the differing materials. For example, in, FIG. 1, if it was desired to contact conductive wire  70 C, levels  140 ,  130 ,  120 ,  110 ,  110 ,  90 , and  80  would need to be removed. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method for vertically aligning fill shapes in several wiring levels in order to provide for line of sight views to lower wiring levels of the device. 
     This object of the invention is accomplished in a first method, by placing fill shapes on different wiring levels relative to a universal virtual grid. In a second method, fill shape placement is first performed on the highest wiring level requiring fill, and each lower wiring level is successively filled by aligning its fill shapes to those in the next higher wiring level. 
     It is a another object of the present invention to provide a method of making electrical taps to lower level conductive wires so they may be accessible from the top or near the top level of the device without having to delayer the device or at least minimize the amount of delayering. 
     This object of the invention is accomplished by connecting selected aligned fill shapes in several wiring levels with vias over the conductive wire to be tapped thus forming a conductive vertical stack. This stack is connected to the conductive wire by a via as well. In a first method, adjacent locations along a conductive wire are examined in sequence to see if aligned fill shapes exist in all higher levels above that location and as soon as one is found, the vias added. A second method is similar to the first, but differs in that aligned fill shapes are required as a prerequisite. In a third method, linking wires are used to connect selected conductive wires to the vertical conductive stack. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes as presently practiced; 
     FIG. 2 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes according to the present invention; 
     FIG. 3 is a flowchart illustrating a first method of placing fill shapes according to the present invention; 
     FIG. 4 is a flowchart illustrating a second method of placing fill shapes according to the present invention; 
     FIG. 5 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes and interconnection of the fill shapes to each other and to certain conductive wires by conductive vias; 
     FIG. 6 is a flowchart illustrating a first method of inter-level connection of fill shapes according to the present invention; 
     FIG. 7 is a flowchart illustrating a second method of inter-level connection of fill shapes according to the present invention; 
     FIG. 8 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating inter-level and intra-level connection of fill shapes according to the present invention; 
     FIG. 9 is a flowchart illustrating a method of inter-level and intra-level connection of fill shapes according to the present invention; 
     FIG. 10 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating post device fabrication formed contacts to stacks of inter-level connected fill shapes according to the present invention; 
     FIG. 11 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating a post device fabrication formed interconnects of post device fabrication formed contacts to stacks of inter-level connected fill shapes according to the present invention; and 
     FIG. 12 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating a post device fabrication formed contact to a stack of inter-level connected fill shapes to according to the present invention illustrated in FIG.  8 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Network circuit (net) wiring is formed from wire segments which are pieces of conductive wires connected to other conductive wires on other levels by vias. There may be several wire segments of the same net on the same wiring level and there may be portions of the same net on several different wiring levels. Conductive wires are formed in wiring levels, and vias in interconnect levels. Fill shapes are formed in the wiring levels. The methods described below intended to be applied to the design shapes data of the semiconductor device which is used to fabricate the device mask set. Net information is contained in the shapes design data. 
     FIG. 2 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes according to the present invention. FIG. 2 may be profitably compared to FIG.  1 . It can be seen that from the highest wiring level to the lowest wiring level certain fill shapes have been vertically aligned to one another. For example fill shapes  52 C,  72 B,  92 A,  112 A, and  132 A in wiring levels  50 ,  70 ,  90 ,  110 , and  130  have been vertically aligned to provide line of sight view to conductive wire  30 A in wiring level  30 . Some other alignments present in FIG. 2 include  92 B,  112 B, and  132 B;  92 C,  112 C, and  132 C; and  92 D,  112 D and  132 D provide other lines of sight. It can also be seen in FIG. 2 that neither fill shapes  52 D or  52 E are aligned to fill shape  92 B or fill shape  52 F or  52 G are aligned to fill shape  92 D. This occurs when changing the size or spacing of fill shapes would violate density rules that the CMP process requires. 
     A first method of placing fill shapes is illustrated in FIG.  3  and described below. FIG. 3 is a flowchart illustrating a first method of placing fill shapes according to the present invention. In this embodiment, fill shapes are added to the wiring levels from lowest to highest. In step  200  a virtual grid reference point is set to the same reference as the semiconductor device die design reference. Next, in step  210 , an initial virtual grid pitch is set that is greater than or equal to the minimum design pitch of the highest wiring level. Preferably, one would initially set this pitch high to reduce the number of fill shapes. Then, in step  220  a test is performed to see if the virtual grid pitch is still greater than the current wiring level design pitch. This is necessary because subsequent steps may change this relationship. If the virtual pitch is not greater or equal to the current wiring level pitch, the virtual grid pitch is set to greater than or equal to the minimum design pitch of the next lower wiring level in step  230  and the process loops back to the test in step  220 . If the virtual pitch is greater or equal to the current wiring level pitch, the current wiring level is set to the lowest wiring level in step  240 . Next, in step  250  the fill shape size is set to the minimum width for the current wiring level. Then, in step  260  fill shapes are added to the design by snapping the centers of the fill shapes to the virtual grid. Next, in step  270  a test is performed to see if the metal density requirements for the current wiring level have been met. These are rules based on the CMP process used for fabricating the current wiring level. If the process requirements are met, a second test is performed to see if the if the current wiring level is the highest wiring level, if it is the process terminates in step  330  and the dataset with fill shapes added is complete. If the current wiring level is not the highest wiring level then the current wiring level is set to the next highest wiring step in step  290  and the process loops back to step  250 . 
     Returning to the test of step  270 , if the metal density of the current level is too low (not met), all fill shapes placed on the current wiring level are removed, and the fill shape size increased by the current wiring level design increment in step  330 . The design increment is the smallest value by which a dimension may be incremented. Then a test in step  310  is performed to determine if the new fill shape size plus the current wiring level minimum space is less than or equal to the virtual grid pitch. If it is, the process loops back to step  260 . If it is not, then the virtual pitch is decreased by the current wiring level design increment in step  320 , and the process loops back to the test in step  220 . 
     A second method of alignment of fill shapes is illustrated in FIG.  4  and described below. FIG. 4 is a flowchart illustrating a second method of placing fill shapes according to the present invention. In this embodiment fill shapes are added to the wiring levels from highest to lowest and no virtual grid is used. In the first step, step  350 , the current wiring level is set to the highest wiring level requiring the addition of fill shapes, and this level is filled using conventional fill methods. The location of fill shapes is independent of line of sight considerations. Next, in step  360 , the current wiring level is set to the next lowest wiring level, the fill shape size is set to the minimum width for the current level, and the current level divided into regions requiring fill. Regions may be determined by differing fill requirements, differing needs for line of sight views, for reduction in data process time, the existence of overlying fill shapes, or other reasons. Next in step  370  the next region requiring fill is selected and in step  380  a test performed to determine if fill shapes are present over the current region in any of the higher wiring levels. In step  380  a test performed to determine if fill shapes are present over the current region in any of the higher wiring levels. If there are overlying fill shapes then current level fill shapes are added and aligned to the overlying fill shapes in step  390  and the density test of step  410  performed. If there are no overlaying fill shapes then fill shapes are added to the current region conventionally, without regard to alignment of fill shapes, in step  400  and density test of step  410  performed. In step  410  a test is performed to see if the metal density requirements for the current wiring level have been met as was done in the first method above. If the result of the test is metal density met, then the test of step  420  is performed which is a check to see if all regions of the current wiring level have been filled. If not, then the process loops back to step  370 . If all regions have been filled then the test of step  430  is performed to see if any lower wiring levels remain to be filled. If yes, then the process loops to step  360 , if no wiring levels are left to be filled, the process terminates in step  440  and the dataset with fill shapes added is complete. 
     Returning to the density test of step  410 , if the metal density of the current level is not met, metal density is too low, then all the fill shapes added to the current region of the current level are removed, and the fill shape size incremented by the current wiring level design increment in step  450 . Next the test of step  460  is performed. If the current fill shape size when added to the current wiring level minimum space is less than or equal to the current design level pitch then the process loops to step  380 , otherwise the process loops to step  400 . 
     Turning now to FIG. 5, which is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes and interconnection of the fill shapes to each other and to certain conductive wires by conductive vias. Thus vertically conductive stacks are provided according to another aspect of the present invention. FIG. 5 may be profitably compared to FIG.  2 . It can be seen that from the highest wiring level to the lowest wiring level certain fill shapes have been vertically aligned to one another. For example fill shapes  52 C,  72 B,  92 A,  112 A, and  132 A in wiring levels  50 ,  70 ,  90 ,  110 , and  130  have been vertically aligned. Fill shapes are designated by the letter “F” in order to more easily distinguish them for the reader. Some other alignments present in FIG. 5 include  92 B,  112 B, and  132 B;  92 C,  112 C, and  132 C; and  92 D,  112 D and  132 D. Connecting wire  30 A to fill shape  52 C is a tapping via  42 A. Connecting fill shape  52 C to fill shape  72 B is tapping via  62 A. Connecting fill shape  72 B to fill shape  92 A is tapping via  82 A. Connecting fill shape  92 A to fill shape  112 A is tapping via  102 A. Connecting fill shape  112 A to fill shape  132 A is tapping via  122 A. The tapping vias are designated by the letter “T” in order to more easily distinguish them for the reader. This series of interconnected aligned fill shapes constitutes vertical conductive stack  142  which may be used to electrically tap wire  30 A without delayering device  1 . Wire  30 A may be thought of as a wire segment of a net. Also show in FIG. 5 is vertical conductive stack  144  formed from tapping via  82 B, fill shape  92 C, tapping via  102 B, fill shape  112 C, tapping via  122 B, and fill shape  132 C. This stack allows tapping of conductive wire  70 C which may also be thought of as a wire segment. 
     A first method of forming vertical conductive stacks is illustrated in FIG.  6  and described below. FIG. 6 is a flowchart illustrating a first method of inter-level connection of fill shapes according to the present invention. First in step  490  fill shapes are placed in each wiring level, either by presently practiced methods or using one of the two earlier presented methods. When one of the two earlier presented methods are used, the possibility for creation of a successful tap is greatly increased as many more fill shapes will be vertically aligned. Then, in step  500  the net to be tapped is selected. Next in step  510 , the current wiring level is set to the highest wiring level having a wire segment of the selected net. Then in step  520 , a wire segment of the current net is selected and in step  520  a location on one end of the wiring segment is selected. Next test  540  is performed to see if fill shapes exist in all levels above this location. If fill shapes do not exist then the test of step  550  is performed to see if there are additional locations on this segment, if there are, then the next adjacent location on the segment is selected in step  560  and the process loops to step  540 . If there are no additional locations on this segment then the test of step  570  is performed. This test determines if additional segments of the current net exist on the current wiring level. If there are additional segments the process loops to step  520 . If there are no additional segments on this level the test of step  580  is performed to determine if the current level is the lowest level on which a segment of the present net exists. If there are lower levels available the process loops to step  590  where the current wiring level is set to the next lower level having a wire segment of the current net and the process loops to step  520 . If there are no lower levels containing a wire segment of the current net, the net is flagged and “not tappable” in step  600  and it is determined in step  610  if additional nets are to be tapped. If yes, the process loops to step  500 . If not, the process terminates in step  620  and the dataset with fill shapes and “tapping vias” added is complete. 
     Returning to step  540 . If there are fill shapes in all wiring levels above the current location then tapping vias are added in step  630  and the process loops to step  610 . 
     A second method of forming vertical conductive stacks is illustrated in FIG.  7  and described below. FIG. 7 is a flowchart illustrating a second method of inter-level connection of fill shapes according to the present invention and is described below. In step  700  aligned fill shapes are added to all levels by using one of the two earlier presented methods or by other means that results in aligned fill shapes. Additional non-aligned fill shapes may be added afterwards, as well, and all wiring levels are overlaid. Next in step  710 , a net to be tapped is selected. Then in step  720  the current level is set to the highest wiring level having a segment of the selected net. Next in step  730 , all locations of all wire segments having fill patterns in all levels above any of the locations are identified. Next in step  740 , a test is performed to see if any such locations exist. If not, then the test in step  750  is performed to see if the current level is the lowest level. If it is not, then the current level is set to the next lowest level having a net segment of the selected net and the process loops to step  730 . If the current level is the lowest level having a segment then the net is flagged as “not tappable” in step  770  and the process loops to step  780 . 
     Returning to step  740 . If a location where at least one wire segment having fill patterns in all levels above exists then tapping vias are added in step  790  and the process loops to step  780 . Usually tapping vias are added over one location. In step  780  a test is performed to determine if additional nets are to be tapped. If yes, then the next net is selected in step  800  and the process loops to step  720 . If no further nets are to be tapped then the process terminates in step  810  and the dataset with fill shapes and “tapping vias” added is complete. 
     Turning to FIG.  8 . FIG. 8 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating inter-level and intra-level connection of fill shapes according to the present invention. In FIG. 8 vertical conductive stack  146  is formed from fill shapes  72 B,  92 A,  112 A, and  132 A connected by tapping vias  82 A,  102 A, and  122 A. Connection between conductive stack  146  and conductive wire  70 B has been made by conductive link wire  74  which has been marked with an “E.” Fill shape  72 B, link wire  74 , and conductive wire  70 B may be thought of as a wire segment. The method of placement of the tapping vias and the link wire is illustrated in FIG.  9  and described below. 
     FIG. 9 is a flowchart illustrating a method of inter-level and intra-level connection of fill shapes according to the present invention. First, in step  840 , aligned fill shapes added to all levels by using one of the two earlier presented methods or by another method forming aligned fill shapes. Then, in step  850 , a net to be tapped is selected. Next, in step  860 , all fill shapes adjacent to all net segments on all wiring levels are found, and ordered by highest wiring level. Then in step  870 , an adjacent fill shape is selected according to ordering hierarchy. Next in step  880  a test is performed to determine if there is a consecutive sequence of upper level aligned fill shapes. If there are not, the test in step  890  is performed to see if more adjacent fill shapes exist, if more exist then the process loops to step  870 , if not then step  900  is performed, which flags the net as “not tappable”, and the presence of additional nets determined in step  910 . If there are more nets to be tapped the process loops to step  850 , if there are no more nets to be tapped the process is terminated in step  920  and the dataset with link wire and “tapping vias” added is complete. 
     Returning to step  880 . If there are upper level aligned fill shapes the test in step  930  is performed which determines if a link wire can be placed between the fill shape and the net segment. If a link can not be placed then the process loops to step  890 , if a link can be placed then in step  940 , the link wire is placed and the tapping vias placed and the process loops to step  910 . 
     Turning to FIGS. 10 through 12. These figures are intended to illustrate methods of making electrical connection to the vertical conductive stacks previously described when the uppermost fill shape is not large enough to be contacted with a convention test probe directly. 
     FIG. 10 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating post device fabrication formed contacts to stacks of inter-level connected fill shapes according to the present invention. In FIG. 10, opening  150 A has been made in passivation  140  exposing fill shape  132 A which forms the topmost portion of vertical conductive stack  142  which is contacting conductive wire  30 A and probe pad  160 A has been formed. Similarly opening  150 B has been made in passivation  140  exposing fill shape  132 C which forms the topmost portion of vertical conductive stack  144  which is contacting conductive wire  70 C, and probe pad  160 B has been formed. Openings  150 A and  150 B and pads  160 A or  160 B may be formed using Focused Ion Beam (FIB) techniques, or evaporation or deposition and dry or wet etching techniques. 
     FIG. 11 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating a post device fabrication formed interconnects of post device fabrication formed contacts to stacks of inter-level connected fill shapes according to the present invention. In FIG. 11, opening  150 A has been made in passivation  140  exposing fill shape  132 A which forms the topmost portion of vertical conductive stack  142  which is contacting conductive wire  30 A. Similarly opening  150 B has been made in passivation  140  exposing fill shape  132 C which forms the topmost portion of vertical conductive stack  144  which is contacting conductive wire  70 C, and interconnection  160 C has been formed. Openings  150 A and  150 B and connection  160 C may be formed using FIB techniques, or evaporation or deposition and dry or wet etching techniques. 
     FIG. 12 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating a post device fabrication formed contact to a stack of inter-level connected fill shapes to according to the present invention illustrated in FIG.  8 . In FIG. 12, opening  150 A has been made in passivation  140  exposing fill shape  132 A which forms the topmost portion of vertical conductive stack  142  which terminates in fill shape  72 B, and probe pad  160 A has been formed. Link wire  74  connects fill shape  72 B to conductive wire  70 B. Opening  150 A and connection  160 A may be formed using FIB techniques, or evaporation or deposition and dry or wet etching techniques. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not to the particular embodiments described herein, but is capable of various modifications, rearrangements, combinations and substitutions will now become apparent to those skilled in the art without departing from the scope of the invention. For example, it should not be taken that aligned fill shapes must be symmetrically aligned, though they may be. It is sufficient that alignment be enough that a sight of view is created or that a via may be placed between the upper and lower fill shapes to be connected. Nor is it necessary that fill shapes be aligned in all levels. Alignment in some often will suffice to carry out the purposes of the present invention. 
     Therefore it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.