Abstract:
A system according to one embodiment includes input stage circuitry configured to receive input data; output stage circuitry configured to generate buffered output data based on said received input data, said output stage circuitry comprising a first switch and a second switch, wherein said first switch comprises a first gate configured to control said first switch through an inverted gate signal and said second switch comprises a second gate configured to control said second switch through a non-inverted gate signal; first feedback inverter circuitry configured to enable pull-up of said second gate based on an input to said first gate, said first feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-up enable; and second feedback inverter circuitry configured to enable pull-down of said first gate based on an input to said second gate, said second feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-down enable.

Description:
FIELD 
       [0001]    The present disclosure relates to an output buffer, and more particularly, to an output buffer having adjustable feedback to reduce crowbar current. 
       BACKGROUND 
       [0002]    Buffer circuits are widely used in many digital systems, and generally provide impedance matching, edge setting and level adjusting functions between an input signal and other circuitry, for example, other circuitry associated with an integrated circuit (IC). Output buffers may include one or more switching stages that switch in response to an input signal. Combinations of switches may sometimes be turned on simultaneously or for overlapping periods of time, resulting in crowbar currents through these switching paths directly between supply voltage and ground. The presence of crowbar currents in the buffer can unnecessarily increase the overall power draw of the circuit, which in turn, may cause power supply noise and droop, limit battery life and create thermal management issues. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    Features and advantages of embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals depict like parts, and in which: 
           [0004]      FIG. 1  illustrates a logic block diagram of one exemplary embodiment consistent with the present disclosure; 
           [0005]      FIG. 2  illustrates a truth table for an output buffer consistent with one exemplary embodiment of the present disclosure; 
           [0006]      FIG. 3  illustrates a circuit diagram of one exemplary embodiment consistent with the present disclosure; 
           [0007]      FIG. 4  illustrates a timing diagram for an output buffer consistent with one exemplary embodiment of the present disclosure; and 
           [0008]      FIG. 5  illustrates a flowchart of operations of one exemplary embodiment consistent with the present disclosure. 
       
    
    
       [0009]    Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. 
       DETAILED DESCRIPTION 
       [0010]    Generally, this disclosure provides output buffer systems and methods that employ adjustable feedback techniques to limit overlapping turn-on times of output buffer switches. This reduces crowbar current (ICCT) through the output switches resulting in reduced overall power draw of the circuit, reduced power supply noise and increased battery life. Advantageously, the output buffer systems of the present disclosure provide reduced ICCT without requiring fixed delay break-before-make techniques. Rather, the adjustable feedback techniques of the present disclosure enable the delay between gate switches to adjust and compensate for changing load conditions on the output switches that affect the output switch transition times. 
         [0011]      FIG. 1  illustrates a logic block diagram  100  of one exemplary embodiment consistent with the present disclosure. Logic block diagram  100  generally includes an input data path  104 , an output enable path  102  and an output pad  150  for the buffered output. Positive and negative power supply rail voltages VDD  160  and VSS  162 , respectively, are also shown. The state of the output pad  150  is controlled by output switches MPOUT  140  and MNOUT  142 , which in turn are controlled by input data  104  and output enable  102  as will be explained later. When MPOUT  140  is switched on and MNOUT  142  is switched off, the output pad  150  will be High (VDD  160 ) representing a logic 1 value. When MPOUT  140  is switched off and MNOUT  142  is switched on, the output pad  150  will be Low (VSS  162 ) representing a logic 0 value. If both switches  140 ,  142  are off, the output pad  150  will be in a high impedance state. If both switches  140 ,  142  are on, crowbar current (ICCT) will flow through the switches  140 ,  142  from VDD  160  to VSS  162 . It is generally desirable to reduce the length of time during which either of these last two conditions, high impedance and ICCT, may occur. Two feedback paths are provided, through inverters I_PFB  124  and I_NFB  130 , to accomplish this as will be explained below. 
         [0012]    Switch MPOUT  140  is controlled through an inverted version of gate signal  144 . Switch MNOUT  142  is controlled through (non-inverted) gate signal  146 . I_PFB  124  feeds back an inverted version of the MPOUT gate signal  144  to be used as an inverted pull-up enable  122  to gate signal  146  of switch MNOUT  142 . In other words, when MPOUT  140  is switched off, I_PFB  124  will transition to Low which will cause inverted pull-up enable  122  to pull-up gate signal  146  of switch MNOUT  142  turning it on. 
         [0013]    Similarly, I_NFB  130  feeds back an inverted version of the MNOUT gate signal  146  to be used as a pull-down enable  120  to gate signal  144  of switch MPOUT  140 . In other words, when MNOUT  142  is switched off, I_NFB  130  will transition to High which will cause pull-down enable  120  to pull-down gate signal  144  of switch MPOUT  140 . Since MPOUT  140  is controlled through an inverted version of gate signal  144 , this pull-down of gate signal  144  turns MPOUT  140  on. 
         [0014]    These feedback paths, through I_NFB  130  and I_PFB  124 , may therefore ensure that switches MPOUT  140  and MNOUT  142  are not simultaneously turned on resulting in unwanted ICCT. These feedback signals, however, do not change instantaneously. Generally, there are ramp up and ramp down times which may depend on circuit loading conditions. There are also voltage threshold switching points on these ramps that may be adjusted, for example based on the physical geometry of the devices. These factors may be used to determine and adjust relative delays between switching of output buffer switches MPOUT  140  and MNOUT  142  as will be explained in greater detail below. 
         [0015]    Also illustrated in  FIG. 1  are additional logic circuitry comprising NAND gate  110 , NOR gate  112 , and inverter  114 . This logic circuitry is provided to handle the output enable signal  102 . In some circumstances it may be useful to disable the buffering of the input data  104  to the output pad  150 , by holding the output pad  150  in a high impedance state. If output enable  102  goes Low, NAND gate  110  goes High and NOR gate  112  goes Low (due to the inversion of output enable  102  by inverter  114 ), regardless of the state of input data. With the output of NAND gate  110  being High, gate signal  144  of switch MPOUT  140  will be High and therefore, since MPOUT  140  is controlled through an inverted version of gate signal  144 , MPOUT  140  will be switched off. Additionally, with the output of NOR gate  112  being Low, gate signal  146  of switch MNOUT  142  will be Low and therefore MNOUT  142  will be switched off. With both switches MPOUT  140  and MNOUT  142  being off, output pad  150  will float in a high impedance state and input data  104  will not be reflected at the output of the buffer. 
         [0016]      FIG. 2  illustrates a truth table  200  for an output buffer consistent with one exemplary embodiment of the present disclosure. Truth table  200  summarizes the states of the key signals as described above with respect to logic block diagram  100 . The columns of truth table  200 , from left to right, list input data  202 , output enable,  204 , I_PFB  206 , I_NFB  208 , MPOUT  210 , MNOUT  212  and output pad  214 . As can be seen, when output enable  204  is Low, both MPOUT  210  and MNOUT  212  are switched off and the output pad  214  will be in a high impedance state. When output enable  204  is High, I_PFB  206  and I_NFB  208  achieve a state that matches the input data  202 . In this case, when input data  202  is Low, MPOUT  210  is switched off and MNOUT  212  is switched on, resulting in output pad  214  going Low which matches input data  202 . Similarly, when input data  202  is High, MPOUT  210  is switched on and MNOUT  212  is switched off, resulting in output pad  214  going High which matches input data  202 . 
         [0017]      FIG. 3  illustrates a circuit diagram  300  of one exemplary embodiment consistent with the present disclosure. The circuit  300  is a more detailed illustration of the logic block diagram of  FIG. 1 , where NAND gate  110  and NOR gate  112  have been expanded to detail the underlying PMOS and NMOS gates. 
         [0018]    NAND gate  110  is comprised of PMOS P 5   302 , PMOS P 4   304 , NMOS N 5   306 , NMOS N 4   308  and NMOS N 3   310 . Output enable  102  gates NMOS N 3   310  and PMOS P 4   304 . Input data  104  gates PMOS P 5   302  and NMOS N 4   308 . Feedback from I_NFB  130  provides a pull-down enable to NMOS N 5   306 . The output of the NAND gate  110  is tapped off the connection point between PMOS P 4   304  and NMOS N 5   306 . 
         [0019]    NOR gate  112  is comprised of PMOS P 3   320 , PMOS P 2   322 , PMOS P 1   324 , NMOS N 2   326  and NMOS N 1   328 . Output enable  102  goes through inverter  114  and then gates PMOS P 3   320  and NMOS N 1   328 . Input data  104  gates PMOS P 2   322  and NMOS N 2   326 . Feedback from I_PFB  124  provides a pull-up enable to inverted gate of PMOS P 1   324 . The output of the NOR  112  gate is tapped off the connection point between PMOS P 1   324  and NMOS N 1   328 . 
         [0020]      FIG. 4  illustrates a timing diagram  400  for an output buffer consistent with one exemplary embodiment of the present disclosure. The baseline for the timing diagram  400  is a plot of the output pad voltage  406  illustrating a High to Low transition  450  followed by a Low to High transition  452 . Plotted above this, are the PGATE voltage  402 , which represents the inverted version of gate signal  144  to MPOUT switch  140 , and the NGATE voltage  404  which represents the gate signal  146  to MNOUT switch  142 . 
         [0021]    When PGATE  402  is Low and NGATE  404  is Low, MPOUT switch  140  is on and MNOUT switch  142  is off which drives output pad  406  High. 
         [0022]    As PGATE  402  rises from Low to High  440 , it passes through a transition voltage V tP  at  420  where MPOUT  140  switches from on to off. Similarly as NGATE  404  rises from Low to High  442 , it passes through a transition voltage V tN  at  424  where MNOUT  142  switches from off to on. T OLHL    408  is the time interval during which MPOUT  140  and MNOUT  142  are both switched off and the output pad  406  will be in a high impedance state. If V tp  at  420  were shifted in time to the right of V tN  at  424 , then T OLHL .  408  would represent the time interval during which MPOUT  140  and MNOUT  142  are both switch on resulting in crowbar current ICCT flowing through MPOUT  140  and MNOUT  142 . Since neither of these conditions are desirable, T OLHL    408  may be reduced by shifting V tp  at  420  and V tN  at  424  as close as possible to an optimal common point  422  where V tN =V tP . This may be accomplished by adjusting the feedback transition thresholds of I_PFB  124  and I_NFB  130  to add or subtract delay to transition point  424  and  420  respectively. 
         [0023]    A similar situation exists during the transition of output pad  406  from Low to High  452 . As PGATE  402  falls from High to Low  446 , it passes through a transition voltage V tP  at  430  where MPOUT  140  switches from off to on. Similarly as NGATE  404  falls from High to Low  444 , it passes through a transition voltage V tN  at  426  where MNOUT  142  switches from on to off. T OLLH    410  is the time interval during which MPOUT  140  and MNOUT  142  are both switched off and the output pad  406  will be in a high impedance state. If V tP  at  430  were shifted in time to the left of V tN  at  426 , then T OLLH    410  would represent the time interval during which MPOUT  140  and MNOUT  142  are both switch on resulting in crowbar current ICCT flowing through MPOUT  140  and MNOUT  142 . Since neither of these conditions are desirable, T oLLH    410  may be reduced by shifting V tP  at  430  and V tN  at  426  as close as possible to an optimal common point  428  where V tN =V tP . This may be accomplished by adjusting the feedback transition thresholds of I_PFB  124  and I_NFB  130  to add or subtract delay to transition point  426  and  430  respectively. 
         [0024]      FIG. 5  illustrates a flowchart of operations  500  of one exemplary embodiment consistent with the present disclosure. At operation  510 , input data is received from input stage circuitry. At operation  520 , buffered output data is generated through output stage circuitry comprising a first switch controlled by a first inverted gate and a second switch controlled by a second non-inverted gate. At operation  530  a first feedback inverter circuit is configured to enable pull-up of the second gate based on an input to the first gate. At operation  540 , an adjustable transition threshold is provided for generation of the pull-up enable. At operation  550 , a second feedback inverter circuit is configured to enable pull-down of the first gate based on an input to the second gate. At operation  560 , an adjustable transition threshold is provided for generation of the pull-down enable. 
         [0025]    “Circuitry”, as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. 
         [0026]    The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.