Abstract:
Methods and apparatus of phase tracking are described. Decisions regarding phase location of an oversampled portion of a data signal are based on the content of the data signal. In one example, a phase decision threshold is dynamically variable based on whether a predetermined number of edges is detected in the data signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of copending U.S. application Ser. No. 10/351,590 filed Jan. 27, 2003 entitled “Dynamic Phase Tracking Using Edge Detection,” which is incorporated by reference herein. 
         [0002]    This application claims priority to U.S. Provisional Patent Application No. 60/351,999, filed Jan. 25, 2002 and entitled “DYNAMIC PHASE DECISION DIGITAL PLL”. 
     
    
     BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    This invention relates to signal processing. 
         [0005]    2. Background Information 
         [0006]    In an oversampling data receiver system, a digital phase-locked loop (DPLL) may be applied to the oversampled signal to select the sample that best represents each oversampled bit. In a three-times oversampling system, for example, a DPLL may be used in selecting one sample out of each consecutive series of three samples. The DPLL indicates the proper sample by determining the phase relationship between the data and the clock. 
         [0007]    It is desirable to improve the tracking behavior of such a system. It is also desirable to maintain noise rejection capability. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    A method of signal processing according to one embodiment of the invention includes detecting the presence of a predetermined number of edges in a segment of a data signal. The method also includes determining a relation between the number of occurrences of a predetermined phase transition condition in an oversampled portion of the data signal and a threshold value. In this method, the threshold value is selected according to the edge detecting. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  shows a block diagram for a DPLL  100  according to an embodiment of the invention. 
           [0010]      FIG. 2  shows a block diagram for an implementation  202  of sample selector  200 . 
           [0011]      FIG. 3  shows a block diagram for an implementation  302  of digital phase detector  300 . 
           [0012]      FIG. 4  shows a block diagram for an implementation  852  of voting circuit  850 . 
           [0013]      FIG. 5  shows a state diagram for a five-state implementation of loop filter  400 . 
           [0014]      FIG. 6  shows a state diagram for a nine-state implementation  402  of loop filter  400 . 
           [0015]      FIG. 7  shows a circuit diagram for loop filter  402 . 
           [0016]      FIG. 8  shows a state diagram for an implementation  502  of phase pointer  500 . 
           [0017]      FIG. 9  shows a circuit diagram for phase pointer  502 . 
           [0018]      FIG. 10  shows a block diagram for an implementation  602  of dynamic phase decision control  600 . 
           [0019]      FIG. 11  shows a block diagram for an implementation  102  of DPLL  100 . 
           [0020]      FIG. 12  shows a block diagram for an implementation  612  of dynamic phase decision control  600 . 
           [0021]      FIG. 13  shows a circuit diagram for control of a clock input. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]      FIG. 1  shows an example  100  of a DPLL according to an embodiment of the invention. 
         [0023]    DPLL  100  receives oversampled data (e.g. as provided by a data oversampler) and selects a set of samples d according to a detected phase. The oversampled data may be generated, for example, by sampling using multiphase clocks. In the example illustrated, DPLL  100  receives fourteen samples of a data signal that has been three-times oversampled and selects a set of twelve samples that represent four oversampled data bits. 
         [0024]      FIG. 2  shows an implementation  202  of sample selector  200  that includes a multiplexor  204 . In this example, multiplexer  204  receives the three consecutive sets of twelve samples of the fourteen-sample input signal. Based on the phase information ph&lt;2:0&gt;, multiplexer  204  passes one of the consecutive sets of twelve samples (representing four data bits, each oversampled three times) as data signal d&lt;11:0&gt;. This data signal is processed for skew detection as described below and may also be outputted to other processing circuitry (e.g. a downsampler). 
         [0025]    Digital phase detector  300  evaluates the selected sample pattern to detect skew errors within it. Based on this evaluation, detector  300  outputs skew detection signals uplk and dnlk that indicate whether a skew of the selected set has been detected, and if so, in which direction the set is skewed (i.e. early or late). 
         [0026]      FIG. 3  shows a block diagram of an implementation  302  of digital phase detector  300  that includes transition detectors  810   a - d  and a voting circuit  850 . Each transition detector  810  receives a set of samples and indicates whether a skew error is detected among the samples. For example, a transition detector  810  may receive a set of samples corresponding to one oversampled bit and may detect whether a data transition has occurred within the set. If a skew error is detected, transition detector  810  also indicates in which direction its set is skewed (e.g. by asserting the corresponding one of its up and down output signals). 
         [0027]    For example, in a set of three consecutive samples corresponding to one oversampled bit, in the absence of a skew error all three samples will have the same value. If the first sample is different than the other two, the set is skewed in one direction. If the last sample is different, then the set is skewed in the other direction. 
         [0028]    Voting circuit  850  receives the skew indications, determines whether the number of skew indications in either direction reaches (or exceeds) a threshold value, and outputs corresponding skew detection signals uplk and dnlk. In this particular example, voting circuit  850  makes one or more of its skew determinations based on a threshold that may vary based on the content of the data signal. 
         [0029]      FIG. 4  shows an implementation  852  of voting circuit  850  that includes count blocks  910   a,    910   b  and comparison blocks  920   a,    920   b.  One of count blocks  910  counts the number of early skew errors detected, and the other counts the number of late skew errors detected. Comparison blocks  920   a  and  920   b  compare these numbers to thresholds and output skew detection signals uplk and dnlk according to the comparisons. 
         [0030]    In one implementation of such a voting circuit, the threshold of one or both of the comparison blocks may be set to a fixed value (e.g. skew is decided if at least two corresponding transitions are detected). In another implementation, the thresholds of one or both comparison blocks may vary dynamically according to the content of the data signal. For example, each threshold may be set to a default value of two but dynamically changed to a value of one if only one edge is detected in the selected sample set. 
         [0031]    Loop filter  400  filters the skew detection signals uplk and dnlk (e.g. to reduce jitter). 
         [0032]    Loop filter  400  may be implemented in analog, e.g. as a charge-pump circuit. Alternatively, loop filter  400  may be implemented digitally.  FIG. 5  shows a state diagram for a five-state implementation of loop filter  400 , which implementation may be used for an application in which only one of the skew detection signals uplk and dnlk is asserted at one time.  FIG. 6  shows a state diagram for a nine-state implementation of loop filter  400 , which implementation may be used for an application in which both of the skew detection signals uplk and dnlk may be asserted at one time. In  FIGS. 5 and 6 , the state labels H, U, and D indicate that loop filter  400  asserts the corresponding one of phase adjustment signals hdnk, upnk, and dnnk when in that state.  FIG. 7  shows a circuit diagram for one nine-state implementation  402  of loop filter  400 . 
         [0033]    Phase pointer  500  indicates the center sample among the oversampled set. For example, phase pointer  500  may be implemented as a ring counter that circulates a single bit according to the phase adjustment signals upnk and dnnk.  FIG. 8  shows a state diagram for an implementation of phase pointer  500  as a ring counter, and  FIG. 9  shows a circuit diagram for one such implementation  502 . 
         [0034]      FIG. 10  shows a block diagram for an implementation  602  of dynamic phase decision control  600 . Edge detector  700  detects edges within the data signal. For example, edge detector  700  may be implemented to compare each consecutive pair of the selected set of samples (d&lt;0&gt;and d&lt;1&gt;, d&lt;1&gt;and d&lt;2&gt;, d&lt;2&gt;and d&lt;3&gt;, etc.). Such a detector may be implemented using a corresponding number of XOR gates. 
         [0035]    Edge counter  800  counts the number of detected edges. In the example of a set of twelve samples representing four data bits that are three-times oversampled, from zero to four edges may be present in such a set (actually, zero to five edges may be present if there is an error in the oversampling). In the example of  FIG. 10 , edge counter  800  outputs a binary-valued threshold control signal to digital phase detector  300  that indicates whether the presence of one and only one edge has been detected. Alternatively, edge counter  800  may be implemented to indicate the number of edges detected so that a module receiving such an indication (e.g. digital phase detector  300 ) may perform an appropriate operation (e.g. selection of an appropriate threshold). 
         [0036]      FIG. 11  shows a block diagram for an alternate implementation  102  of DPLL  100 . In this implementation, loop filter  400  is disabled (e.g. by holding its clock input low) in a case where no edges are detected in the data signal. An implementation  610  of dynamic phase decision control  600  outputs a binary-valued clock control signal that indicates whether a condition of zero edges in the selected sample has been detected.  FIG. 12  shows a block diagram for an implementation  612  of dynamic phase decision control  610  that includes an implementation  810  of edge counter  800 .  FIG. 13  shows one possible circuit arrangement for applying the clock control signal to loop filter  400 . 
         [0037]    In a further implementation of DPLL  100 , digital phase detector  300  may be configured to operate in a fixed manner (i.e. without dynamic threshold control), and dynamic phase decision control  600  may be implemented to dynamically control the clock signal to loop filter  400  (e.g. in response to an absence of edges in the data signal). 
         [0038]    The foregoing presentation of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well. 
         [0039]    For example, a number of DPLLs as described herein may be applied in parallel to process multi-value signals. In one such application, three DPLLs may be used to independently process the three components of a RGB video signal. 
         [0040]    A DPLL as described herein may be used to process nonoverlapping portions of a data signal. Alternatively, the oversampled portions consecutively inputted to such a DPLL may overlap by one or more data bits. 
         [0041]    The invention may also be implemented in part or in whole as a hard-wired circuit, as a circuit configuration fabricated into an application-specific integrated circuit, or as a firmware program loaded into non-volatile storage or a software program loaded from or into a data storage medium as machine-readable code, such code being instructions executable by an array of logic elements such as a microprocessor or other digital signal processing unit. Thus, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein.