Abstract:
A ball grid array resistor network has a substrate that has top and bottom surfaces. Resistors are disposed on the top surface. Conductors are disposed on the top surface, and each conductor is electrically connected to an end of each resistor. Vias extend through the substrate and are electrically connected to the conductors. Solder spheres are disposed on the bottom surface, and are electrically connected to the vias. A cover coat is disposed over the conductors and resistors. In an alternative embodiment, the vias are eliminated and the resistor network is formed on the bottom surface of the substrate. The resistor network provides a high density of resistors per unit area.

Description:
BACKGROUND OF THE PREFERRED EMBODIMENT(S) 
     1. Field of the Preferred Embodiment(s) 
     This invention generally relates to resistors for electronics. Specifically, the invention is a group of resistors mounted in a high density network or array package using spherical solder connections. 
     2. Description of the Related Art 
     Resistor networks are commonly used to terminate high speed digital signal lines to minimize unwanted reflections back through the transmission structure which is typically a printed circuit board. In most applications, the terminations are made by placing a resistor with a resistance matching the impedance of the transmission line, at the end of the transmission line. One end of the resistor is connected to a common termination voltage and the other end is connected to the signal line. For these applications, a bussed resistor network is a convenient solution, since one end of the termination is common to all signal lines. 
     The previous resistor network designs include surface mount, and through hole SIP and DIP versions. 
     Despite the advantages of each type of prior art resistor network, none have been easily or economically manufactured with a high density of interconnects per unit area on a printed circuit board. In particular, providing the electrical connections only on the periphery of the resistor network causes the electrical leads to be tightly spaced on the edge of the device, while the area in the interior of the device is unused for electrical interconnections. 
     Therefore, there is a current unmet and heretofore long felt need for a resistor network with higher density, low cross-talk noise and improved signal integrity. 
     DESCRIPTION OF RELATED ART 
     Examples of patents related to the present invention are as follows, and each patent is herein incorporated by reference for the supporting teachings: 
     U.S. Pat. No. 4,945,399, is an electronic package with integrated distributed decoupling capacitors. 
     U.S. Pat. No. 5,557,502, is a ball grid array package. 
     U.S. Pat. No. 4,300,115, is a multi-layer via resistor. 
     U.S. Pat. No. 4,658,234, is a resistor network. 
     U.S. Pat. No. 5,621,619, is an all ceramic surface mount sip and dip network having spacers and solder barriers. 
     U.S. Pat. No. 5,379,190, is a chip type composite electronic part. 
     U.S. Pat. No. 4,332,341, is a fabrication of circuit packages using solid phase solder bonding. 
     U.S. Pat. No. 5,539,186, is a temperature controlled multi-layer module. 
     U.S. Pat. No. 5,216,404, is a SIC thin film thermistor. 
     U.S. Pat. No. 4,654,628, is a network resistor unit. 
     U.S. Pat. No. 5,661,450, is a low inductance termination resistor array. 
     The foregoing patents reflect the state of the art of which the applicant is aware and are tendered with the view toward discharging applicant&#39;s acknowledged duty of candor in disclosing information that may be pertinent in the examination of this application. It is respectfully stipulated, however, that none of these patents teach or render obvious, singly or when considered in combination, applicant&#39;s claimed invention. 
     SUMMARY OF THE PREFERRED EMBODIMENT(S) 
     It is a feature of the invention to provide a ball grid array resistor network. Specifically, there is a substrate, several resistors, conductors, and vias arranged in a configuration. Solder spheres are used to connect the resistors to other electronic circuitry such as a printed circuit board. 
     It is a feature of the invention to provide a ball grid array resistor network including a substrate that has top and bottom surfaces. Resistors are disposed on the top surface. Conductors are disposed on the top surface, and each conductor is electrically connected to an end of each resistor. Vias extend through the substrate and are electrically connected to the conductors. Solder spheres are disposed on the bottom surface, and are electrically connected to the vias. A cover coat is disposed over the conductors and resistors. 
     It is a feature of the invention to provide a ball grid array resistor network which has a substrate with a bottom surface. Resistors are disposed on the bottom. Conductors are disposed on the bottom surface and each conductor is electrically connected to an end of each of the resistors. A glass cover coat having several apertures is disposed over the resistors, conductors and the bottom surface. The apertures are aligned with the conductors. Solder spheres are disposed at least partially in the apertures and are electrically connected to the conductors. 
     The invention resides not in any one of these features per se, but rather in the particular combination of all of them herein disclosed and claimed and it is distinguished from the prior art in this combination of all of its structures for the functions specified. 
     There has thus been outlined, rather broadly, the more important features of the invention so that the detailed description thereof that follows may be better understood, and so that the present contribution to the art may be better appreciated. There are, of course, additional features of the invention that will be described hereinafter and which will form the subject matter of the appended claims. Those skilled in the art will appreciate that the preferred embodiment may readily be used as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims are regarded as including such equivalent constructions since they do not depart from the spirit and scope of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an exploded view of a ball grid array resistor network. 
     FIG. 2 is a cross-sectional view of the resistor network of FIG. 1 in its assembled state. 
     FIG. 3 is an exploded view of an alternative embodiment of the ball grid array resistor network. 
     FIG. 4 is a cross-sectional view of the resistor network of FIG. 3 in its assembled state. 
    
    
     It is noted that the drawings of the invention are not to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. The invention will be described with additional specificity and detail through the accompanying drawings. The description of the invention may contain, for example, such descriptive terms as up, down, top, bottom, right or left. These terms are meant to provide a general orientation of the parts of the invention and are not meant to be limiting as to the scope of the invention. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIGS. 1 and 2, there is a ball grid array resistor network assembly  10 . In particular, resistor network assembly  10  has a planar substrate  11  having a top surface  12  and a bottom surface  13 . Substrate  11  is preferably made out of a ceramic material such as alumina oxide. Resistors  14  are disposed and trimmed on the top surface  12  by conventional thick film resistor processing techniques. Resistors  14  have a first end  15  and a second end  17 . Conductors  16  are disposed on the top surface  12  by conventional thick film conductor processing techniques. Conductors  16  are placed one on each end  15  and  17  of resistors  14  and are electrically connected to ends  15  and  17 . Conductors  16  and resistors  14  slightly overlap and sinter to form a mechanical and electrical bond during processing. 
     A pair of bottom conductors  23  is located on bottom surface  13 . Ceramic substrate  11  has cylindrical vias  18  formed therein and which extend through the substrate  11  and are filled with a conductive via fill material  19 . The via fill material  19  is a conventional thick film conductor that is screened into the vias and fired. The via fill material  19  electrically connects the top and bottom conductors  16  and  23 . Solder spheres  28  are mechanically and electrically attached to the bottom conductors  23 . Solder spheres may be 10% tin and 90% lead and are commercially available from Alpha Metals Corporation. The solder spheres can be other alloys such as 5-20% tin and 80-95% lead. Solder spheres  28  may be partially melted to attach to the conductors  23 , typically using a screened on solder paste. Solder sphere  28  typically connects to an external electrical circuit such as on a printed circuit board. A cover coat  26  is placed over the resistors  14  and the conductors  16  to protect from corrosion and abrasion. 
     Resistor network assembly  10  is assembled by the following process sequence: Via fill material  19  is screened into vias  18  of substrate  11  and fired in an oven. The conductors  16  are screened onto top surface  12  and fired in an oven. Conductors  23  are screened onto bottom surface  13  and fired in an oven. The resistors  14  are screened onto top surface  12  and fired in an oven. Next, the resistors  14  are laser trimmed to their proper resistance value and a cover coat  26  is screened on and cured. Solder paste is screened onto conductors  23 . Solder spheres  28  are placed onto conductors  23  and reflowed to bond to conductors  23 . Finally, the assembly  10  is tested. 
     FIG. 3 shows an exploded view of an alternative embodiment of the ball grid array resistor network. Referring to FIGS. 3 and 4, elements that are in common to FIGS. 1 and 2 are given the same reference designator. A resistor network assembly  30  has a substrate  11  to which conductors  16  are located on bottom surface  13 . Substrate  11  is preferably made out of a ceramic material such as alumina oxide. Resistors  14  are disposed and trimmed on the bottom surface  13  by conventional thick film resistor processing techniques. Resistors  14  have a first end  15  and a second end  17 . Conductors  16  are disposed on the bottom surface  13  by conventional thick film conductor processing techniques. Conductors  16  are located on each end  15  and  17  of resistors  14  and are electrically connected to ends  15  and  17 . Conductors  16  and resistors  14  slightly overlap and sinter to form a mechanical and electrical bond during processing. 
     A glass cover coat  32  is located over and covers the resistors  14 , conductors  16  and bottom surface  13 . The glass cover coat is deposited using conventional thick film processing techniques. An array of apertures  34  are located in the glass cover coat  32  below the conductors  16 . Solder spheres  28  are mechanically and electrically attached to the conductors  16 . Solder spheres  28  extend through the apertures  34  to attach with conductors  16 . Solder spheres  28  may be 10% tin and 90% lead and are commercially available from Alpha Metals Corporation. The solder composition could be other alloys such as from 5-20% tin and from 80-95% lead. The Solder spheres  28  may be partially melted to attach to the conductors  16 , typically using a screened on solder paste. Solder sphere  28  typically connects to an external electrical circuit such as on a printed circuit board (not shown). Glass cover coat  32  protects the resistors  14  and conductors  16  from corrosion and abrasion and acts as a solder dam when the solder spheres  28  are reflowed. Resistor network  30  avoids the use of a ceramic with vias and having to fill the vias with a conductive via fill. 
     Resistor network assembly  30  is assembled by the following process sequence: Conductors  16  are screened onto bottom surface  13  and fired in an oven. Resistors  14  are screened onto bottom surface  13  and fired in an oven. Next, resistors  14  are laser trimmed to their proper resistance value. A glass cover coat  32  is screened on over the resistors and conductors and fired in an oven. Solder paste is screened onto conductors  16 . Solder spheres  28  are placed onto conductors  16  and reflowed to bond to conductors  16 . Finally, the assembly  10  is tested. 
     VARIATIONS OF THE PREFERRED EMBODIMENTS(S) 
     One of ordinary skill in the art of making resistors, will realize that there are many different ways of accomplishing the preferred embodiment. For example, although it is contemplated to make substrate  14  out of ceramic, other suitable materials would work, like polyamide or FR4. These materials would require a different resistor system. Additionally, although only one group of  6  resistors was shown on substrate  11 , more or fewer resistors  14  could be placed. Additionally more or fewer rows of solder spheres could be used. 
     It is further possible to have other electrical connections through the substrate other than conductor filled vias. It is possible to use staked copper or metal pins in place of the via fill material  19 . 
     The specification has shown the resistor network assembly  10  with a cover coat  26 . It is contemplated, however, to omit the cover coat. 
     Another variation of the preferred embodiment is to use other types of solder preforms in place of solder spheres  28 . For example, solder donuts or wire or squares could be used. Further, the solder could be made from materials other than tin/lead. For example, a mixture of tin/indium or tin/bismuth could be used if a lower melting solder is desired. A mixture of tin/silver or tin/antimony could be used if a higher temperature solder is desired. 
     Further, the steps of processing sequence could be modified from that shown in the specification to produce the same end result. For example, resistors  14  could be placed before conductors  16  or the screening of bottom conductors  23  could be omitted and solder spheres  28  reflow soldered directly to via fill material  19 . 
     If desired, other electrical elements could be added to resistor network  10  or  30  such as capacitors or inductors to make a filter, for example. 
     While the invention has been taught with specific reference to these embodiments, someone skilled in the art will recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.