Abstract:
The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.

Description:
[0001]    This application is a National Phase application of, and claims priority to, PCT Application No. PCT/CN2011/082421, filed on Nov. 18, 2011, entitled “METHOD FOR MANUFACTURING SEMICONDUCTOR FIELD EFFECT TRANSISTOR”, which claimed priority to Chinese Application No. 201110172967.4, filed on Jun. 24, 2011. Both the PCT Application and Chinese Application are incorporated herein by reference in their entireties. 
       TECHNICAL FIELD 
       [0002]    The present disclosure pertains to the technical field of semiconductor. In particular, the present disclosure pertains to a method for manufacturing a bulk-silicon Fin Field Effect Transistor. 
       BACKGROUND 
       [0003]    With the integrated circuit industry developing in accordance with the Moore Rule, feature dimension of CMOS devices continuously decreases, which poses various challenges to planar bulk-silicon CMOS devices. Various devices with new structures have been developed to conquer these challenges. Among these new structure devices, Fin Field Effect Transistors (FinFETs) have been considered to be one of the most promising candidates to replace the planar bulk-silicon CMOS devices. The FinFETs become a research focus all over the world. 
         [0004]    Initially, the FinFET devices are mainly manufactured on SOI substrates, and their manufacturing process is simpler than that for bulk-silicon substrates. However, SOI FinFETs have drawbacks such as high manufacturing costs, inferior heat dissipation performance, floating-body effect, and bad compatibility with CMOS processes. In order to overcome the drawbacks of the SOI FinFETs, researches have been done on using bulk-silicon substrates in manufacturing the FinFET devices, which are called Bulk FinFETs. Products such as DRAM and SRAM based on the Bulk FinFETs have been put into use. However, typical Bulk FinFET devices have some drawbacks compared with SOI FinFET devices in that SCE suppressing effect is not ideal. Furthermore, leakage current is large due to leakage current paths in fins at channel bottom, and control of impurity profile is difficult. 
         [0005]    In view of the foregoing problems, more work needs to be done to expedite the application of the FinFET devices. This is of great importance to the application of the FinFET devices and development of the semiconductor industry. 
       SUMMARY 
       [0006]    The present disclosure provides, among other things, a novel method for manufacturing a bulk-silicon FinFET, which is easy to be integrated and has a good compatibility with planar COMS processes. 
         [0007]    According to the present disclosure, a method comprises: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. 
         [0008]    Optionally, forming the semiconductor substrate having the local Silicon-on-Insulator (SOI) structure, which comprises the local buried isolation dielectric layer, may comprise: forming a dielectric layer on the semiconductor substrate; forming a dielectric layer island by photolithograph and etching the dielectric layer; forming a layer of amorphous silicon material on the semiconductor substrate; converting the amorphous silicon material into a monocrystal material and polishing the monocrystal material by Chemical Mechanical Polishing (CMP), to form the semiconductor substrate having the local Silicon-on-Insulator (SOI) structure. 
         [0009]    Optionally, the dielectric layer may comprise any one of SiO 2 , TEOS, LTO, and Si 3 N 4 . Optionally, the dielectric layer may have a thickness of about 20-100 nm. Optionally, in forming the layer of amorphous silicon material on the semiconductor substrate, the amorphous silicon material may be formed by Low Pressure Chemical Vapor Deposition (LPCVD) or Ion Beam Sputtering, etc. The amorphous silicon material may have a thickness of about 200 nm-1000 nm. 
         [0010]    Optionally, in the step of converting the amorphous silicon material into the monocrystal material and polishing the monocrystal material by Chemical Mechanical Polishing (CMP), to form the semiconductor substrate having the local Silicon-on-Insulator (SOI) structure, the amorphous silicon material may be converted into the monocrystal material by any one of Lateral Solid Phase Epitaxy (LSPE), Laser Recrystallization, and Halogen Lamp or Stripe Heater Recrystallization, etc. 
         [0011]    Optionally, forming the fin on the silicon substrate above the local buried isolation dielectric layer may comprise: exposing positive resist by electron beam lithography; etching the silicon substrate above the local buried isolation dielectric layer in such a way that the etching stops at the local buried isolation dielectric layer to form at least two trenches in the semiconductor substrate, between which trenches the fin is formed. 
         [0012]    Optionally, the fin may have a thickness of about 10-60 nm. 
         [0013]    Optionally, forming the gate stack structure on the top and on the side faces of the fin may comprise: forming a gate dielectric layer and a gate electrode material on the top and the side faces of the fin; and forming the gate electrode stack structure by photolithograph and etching. 
         [0014]    Optionally, before forming the source/drain structures in the fin at both sides of the gate stack structure, the method may further comprise: forming source/drain extension regions or halo implantation regions in the fin by tilt angle ion implantation. 
         [0015]    Optionally, forming the source/drain structures in the fin at both sides of the gate stack structure may comprise: forming spacers at both sides of the fin; forming source/drain doping regions by ion implantation; and forming source/drain silicide. 
         [0016]    Optionally, the semiconductor substrate may be a bulk-silicon substrate. 
         [0017]    The present disclosure at least has the following beneficial effects. 
         [0018]    1. According to the method for manufacturing the semiconductor field effect transistor provided by the present disclosure, FinFET devices can be manufactured on the bulk-silicon substrate, so that self-heating effect and floating-body effect of SOI FinFET devices can be avoided and manufacturing cost can be reduced. 
         [0019]    2. According to the method for manufacturing the semiconductor field effect transistor provided by the present disclosure, it is easy to form the local SOI structure on the bulk-silicon substrate and manufacture the fin structure isolated from the substrate. Therefore, the difficulty for manufacturing Bulk FinFET devices can be greatly reduced. 
         [0020]    3. According to the method for manufacturing the semiconductor field effect transistor provided by the present disclosure, the manufacturing processes are simple and easy to be integrated, and have a good compatibility with planar CMOS processes. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The foregoing and other objects, features, and advantages of the present disclosure will become more apparent from the detailed description on embodiments of the present disclosure with reference to the drawings, wherein: 
           [0022]      FIGS. 1˜7  schematically show cross-sectional views of various structures in a process for manufacturing a semiconductor field effect transistor by a method according to embodiments of the present disclosure. 
       
    
    
     REFERENCE SIGNS 
       [0000]    
       
           101 : Si substrate;  102 : dielectric layer;  103 : amorphous silicon layer;  104 : STI isolation layer;  105 : trench structure;  106 : fin;  107 : gate dielectric layer; and  108 : gate electrode. 
       
     
         [0024]    It should be noted that the drawings are not drawn to scale and are only provided for purpose of illustration. The drawings therefore should not be interpreted as any limitation or restriction to the scope of the present disclosure. In the drawings similar parts are identified by similar reference signs. 
       DETAILED DESCRIPTION OF EMBODIMENTS 
       [0025]    Next, the present disclosure will be described by specific embodiments shown in the drawings. However, it should be understood that these descriptions are only exemplary rather than intending to limit the scope of the present disclosure. Further, in the following description, explanations on well-known structures and technologies are omitted, in order not to unnecessarily obscure the concept of the present disclosure. 
         [0026]    Schematic views of layer structures according to embodiments of the present disclosure are shown in the drawings. These drawings are not drawn to scale. Some details may be enlarged and some may be omitted for purpose of clarity. The respective regions, shapes of layers, as well as relative sizes and position relationships thereof are only exemplary, and may be varied due to manufacture tolerances or technique limitations in practice. Those skilled in the art may otherwise design region/layer having different shapes, sizes, or relative positions according to actual requirements. 
         [0027]      FIGS. 1˜7  schematically show cross-sectional views of various structures corresponding to respective steps for manufacturing a semiconductor device according to embodiments of the present disclosure in detail. The respective steps according to the embodiments of the present disclosure will be explained in detail with reference to the drawings. 
         [0028]    First, as shown in  FIG. 1 , a dielectric layer  102  is formed on a semiconductor substrate  101 . The dielectric layer  102  may comprise any one of SiO 2 , TEOS, LTO, and Si 3 N 4 , or other dielectric materials. According to an embodiment of the present disclosure, the dielectric layer  102  may comprise SiO 2  and is formed by thermal growth. Optionally, the dielectric layer  102  may have a thickness of about 20-100 nm. The semiconductor substrate  101  may comprise any substrate material regularly used in semiconductor manufacturing. According to an embodiment of the present disclosure, the semiconductor substrate  101  may be a bulk-silicon substrate. 
         [0029]    Next, as shown in  FIG. 2A  and  FIG. 2B , a dielectric layer island  102 ′ is formed on the semiconductor substrate  101 .  FIG. 2A  is a schematic top view of the semiconductor substrate  101 .  FIG. 2B  is a schematic cross-sectional view taken along an AA′ direction. The dielectric layer island  102 ′ may be formed by photolithograph or exposing resist by electron beam followed by Reaction Ion Etching. 
         [0030]      FIG. 3  schematically shows an amorphous silicon layer  103  being formed on the semiconductor substrate. The amorphous silicon layer  103  may be formed by Low Pressure Chemical Vapor Deposition (LPCVD) or Ion Beam Sputtering, etc. According to an embodiment of the present disclosure, the amorphous silicon layer  103  may be formed by LPCVD. The amorphous silicon layer  103  may have a thickness of about 200 nm-1000 nm. 
         [0031]    Next, as shown in  FIG. 4 , the amorphous silicon layer  103  is converted into a monocrystal silicon layer  103 ′. The monocrystal silicon layer  103 ′ is polished by Chemical Mechanical Polishing (CMP), to form a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer. The amorphous silicon layer  103  may be converted into the monocrystal layer  103 ′ by any one of: Lateral Solid Phase Epitaxy (LSPE), Laser Recrystallization, and Halogen Lamp or Stripe Heater Recrystallization, etc. According to an embodiment of the present disclosure, the amorphous silicon layer  103  may be converted into the monocrystal layer  103 ′ by Lateral Solid Phase Epitaxy (LSPE). In the LSPE process, the amorphous silicon layer  103  in direct contact with the semiconductor substrate  101  is subjected to Vertical Solid Phase Epitaxy in a vertical direction to be converted into the monocrystal silicon layer  103 ′. Then the amorphous silicon layer  103  covering the dielectric layer island  102 ′ is subjected to Lateral Solid Phase Epitaxy to be converted into the monocrystal silicon layer  103 ′. Finally, the total amorphous silicon layer  103  is converted into the monocrystal silicon layer  103 ′. 
         [0032]    Next, as shown in  FIG. 5 , an STI isolation structure  104  is formed on the semiconductor substrate  101 . 
         [0033]      FIG. 6A  is a schematic top view of the semiconductor substrate  101 .  FIG. 6B  and  FIG. 6C  are schematic cross-sectional views taken along an AA′ direction and a BB′ direction in  FIG. 6A , respectively. As shown in  FIG. 6B  and  FIG. 6C , the monocrystal silicon layer  103 ′ is etched to form trenches  105 . A fin  106  is formed between two adjacent trenches. The trenches  105  may be formed, e.g., by exposing positive resist with electron beam followed by Reaction Ion Etching, so as to form the steep trenches  105  having a width of about 200-400 nm. The shape of the trenches is only exemplary. The present disclosure is not limited thereto. The fin has a thickness of about 10-60 nm. 
         [0034]    Next, as shown in  FIGS. 7A ,  7 B, and  7 C, a gate dielectric layer material  107  and a gate electrode material  108  are formed on the whole substrate, which are then etched to form a gate electrode stack structure.  FIG. 7A  is a schematic top view of the semiconductor substrate  101 .  FIG. 7B  and  FIG. 7C  are schematic cross-sectional views taken along an AA′ direction and a BB′ direction in  FIG. 7A , respectively. The gate dielectric layer material  107  may be any common gate dielectric material, such as SiO 2 , or other high-K dielectric materials, such as any one of SiON, HfAlON, HfTaON, HfSiON, and Al 2 O 3 , etc. According to an embodiment of the present disclosure, the gate dielectric layer material  107  may be HfSiON formed by any one of Low Pressure Chemical Vapor Deposition, Metal Organic Chemical Vapor Deposition, and Atom Layer Deposition. The gate dielectric may have an equivalent oxide thickness of about 5-100 Å. The gate electrode material  108  may be any one of: refractory metals such as W, Ti, Ta, Mo; metal nitrides such as TiN, TaN, HfN, MoN, etc.; and other materials. The gate electrode material may be formed by any one of Low Pressure Chemical Vapor Deposition, Metal Organic Chemical Vapor Deposition, and Atom Layer Deposition, etc. The gate electrode material may have a thickness of about 2000-5000 Å. 
         [0035]    Optionally, after forming the gate stack structure, the method may further comprise: forming source/drain extension regions in the fin by tilt angle ion implantation; or forming halo implantation regions in the fin by tilt angle ion implantation. 
         [0036]    Next, gate spacers may be formed at sidewalls of the gate stack in accordance with regular methods. A detailed explanation thereof is omitted. 
         [0037]    Next, source/drain regions may be formed by ion implantation in the semiconductor substrate on both sides of the gate stack. Also, source/drain silicide is formed. 
         [0038]    Then, interconnection structures are formed by metallization in accordance with regular methods to elicit electrodes. A detailed explanation thereof is omitted. 
         [0039]    According to the present disclosure, FinFET devices can be manufactured on a bulk-silicon substrate. The method uses a conventional top-to-bottom process based on quasi-plane, which is simple and has a good compatibility with CMOS planar processes. The method is also easy to be integrated. 
         [0040]    In the above description, technique details such as patterning and etching of respective layers are not specifically explained. However, those skilled in the art will understand that the layers and regions, etc. having desired shapes may be formed by various approaches in the prior art. Further, those skilled in the art may design a method not completely the same as above to form a same structure. 
         [0041]    The present disclosure has been described with reference to embodiments thereof. However, these embodiments are only exemplary rather than limiting the scope of the present disclosure. The scope of the disclosure is limited by the attached claims and equivalents thereof. Those skilled in the art may make various substitutions and modifications without departing from the scope of the present disclosure. All these substitutions and modifications fall within the scope of the present disclosure.