Abstract:
A method of operating a chipset for saving power consumption is provided. Basic operating units, control units and input/output ports are used to simulate the operation inside the chipset. Any idling operating units are temporarily shut down, only to be activated again on demand. Ultimately, less power consumption is used and less heat is generated by the chipset.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
         [0001]    This application claims the priority benefit of Taiwan application serial no. 89123791, filed Nov. 10, 2000.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of Invention  
           [0003]    The present invention relates to the internal operation of a chipset. More particularly, the present invention relates to a power-saving module of a chipset.  
           [0004]    2. Description of Related Art  
           [0005]    In this technologically advance society; computer products have become an indispensable part of our lives. To increase portability of these computer products, light material and miniaturized component designs are often employed. However, batteries have to be deployed if the products are to be carried around. Battery is fundamentally a device that transforms chemical power into electrical power. There is a limitation to the extent of miniaturization of a battery before output power becomes too low. In fact, a small battery actually limits the operating time of portable equipment.  
         SUMMARY OF THE INVENTION  
         [0006]    Accordingly, one object of the present invention is to provide a method of operating a chipset that consumes less power. Hence, a longer operating period is possible for battery of a given size.  
           [0007]    To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of operating a chipset. The chipset includes basic operating units, control units and input/output ports. Each operating unit and input/output port has a control unit. The method of operating the chipset includes the following steps. The chipset signals to the control unit of the operating unit to disable the operating unit, thereby forcing the operating unit into an power-saving mode. On the other hand, when operating unit needs to operate, the control chipset triggers corresponding control unit of the operating unit to return the operating unit into an active mode.  
           [0008]    When the chipset activates the corresponding control unit of an operating unit to enable the particular operating unit, the enabled operating unit will temporary leave the power-saving mode. After leaving the power-saving mode, the operating unit will step into an active mode so that the operating unit can start whatever computation necessary. On completing the current computational work, the operating unit will return to the power-saving mode.  
           [0009]    As soon as a control unit disables a corresponding operating unit, the operation unit will be completely shut down to reduce power consumption. With this arrangement, wasteful conversion of electrical power into heat when the chipset is idling for jobs can be minimized.  
           [0010]    The invention also provides a method of operating a chipset so that power is saved. The chipset includes basic operating units, control units and input/output ports. Each operating unit and input/output port has a control unit. The method of operating the control units includes the following steps. When chipset no longer demands the operation of a particular operating unit, a signal will be sent to the control unit of the operating unit. The control unit then disables the operating unit so that the operating unit steps into an power-saving mode. On the contrary, when the chipset demands to use a particular operating unit, the chipset issues a signal to the corresponding control unit of the operating unit. The control unit then enables the required operating unit so that the operating unit returns to an active mode.  
           [0011]    It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,  
         [0013]    [0013]FIG. 1 is a block diagram showing the internal hardware of a chipset according to this invention;  
         [0014]    [0014]FIG. 2 is a flow chart showing the steps for operating the chipset according to this invention;  
         [0015]    [0015]FIG. 3A is a diagram showing the internal control circuit of a chipset according to one preferred embodiment of this invention; and  
         [0016]    [0016]FIG. 3B is a diagram showing the internal operating unit circuit within of a chipset according to one preferred embodiment of this invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]    Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0018]    [0018]FIG. 1 is a block diagram showing the internal hardware of a chipset according to this invention. As shown in FIG. 1, the chipset  10  includes a plurality of basic operating units  14 , a plurality of control units  12  and a plurality of input/output ports  16 . Each operating unit  14  and input/output port  16  has a control unit  12 . This arrangement is different from a conventional chipset because a conventional chipset normally includes only three-state control input/output ports.  
         [0019]    When the operating unit  14  is not required, the chipset  10  will activate the control unit  12  of the operating unit  14  so that the operating unit  14  is disabled and stepped into an power-saving mode. The operating unit  14  will be completely shut down to save power as soon as the control unit  12  issues a disable signal to the operating unit.  
         [0020]    When the operating unit  14  is demanded by the chipset  10 , the chipset  10  will signal to the control unit  12  of the operating unit  14  so that the operating unit  14  is enabled and stepped into an active mode. Enabling the operating unit  14  through the control unit  12  involves several steps described in more detail below.  
         [0021]    [0021]FIG. 2 is a flow chart showing the steps for operating the chipset according to this invention. As shown in FIGS. 1 and 2, the chipset  10  issues a chipset control signal  18  to the operating unit  14  asking the operating unit  14  to leave the power-saving mode  20 . After leaving the power-saving mode  20 , the operating unit  14  steps into an active mode  22 . After getting into the active mode  22 , the operating unit  14  starts to perform whatever computation  24  necessary. At the end of the computation  26 , the operating unit  14  leaves the active mode  28  and returns to the power-saving mode  30 .  
         [0022]    In the past, the basic units inside most chipset do not have tri-state control. One major aspect of this invention is that a large number of tri-state basic units are used inside the chipset. FIG. 3A is a diagram showing the internal control circuit of a chipset according to one preferred embodiment of this invention. In the embodiment of this invention, the control unit is a tri-state inverter. The tri-state inverter circuit includes P-type field effect transistors  32  and  34 , N-type field effect transistors  42  and  44  and an inverter  52 . An enable EN pin is the main control mechanism for enabling and disabling the tri-state inverter. The enable pin is connected to the P-type field effect transistor  34  and the N-type field effect transistor  42  after via the inverter  52 . The P-type field effect transistor  34  and the N-type field effect transistor  42  are the two main enable/disable devices in this circuit. When the enable lead sets these two transistors to conductive, the tri-state inverter is completely cut off from the power source. Hence, not only is the tri-state inverter disabled, no power is consumed as well.  
         [0023]    [0023]FIG. 3B is a diagram showing the internal operating unit circuit within of a chipset according to one preferred embodiment of this invention. The operating unit  14  is a tri-state NAND gate. The tri-state NAND gate includes P-type field effect transistors  36 ,  38 ,  40 , N-type field effect transistors  46 ,  48 ,  50 , and an inverter  54 . An enable EN pin is used to control enable/disable of the tri-state NAND gate. The enable EN pin is connected to the P-type field effect transistor  40  and the N-type field effect transistor  46  via the inverter  54 . Both the P-type field effect transistor  40  ad the N-type field effect transistor  46  are controlled by the enable EN pin. Detailed description of the enable/disable operation of the circuit is not repeated here.  
         [0024]    Accordingly, the circuit of this invention can be applied to build the North Bridge of a chipset. In general, the operating current and voltage of a North Bridge are 90 mA˜100 mA and 3.3V respectively. From the above consideration, a convention North Bridge will consume about 0.297 W˜0.3 W of power whether or not any computation is executed. In other words, a North Bridge fabricated according to the design of this invention can save up to 0.3 W by shutting the operating unit when the operating unit is not operating.  
         [0025]    Aside from saving power, the power-saving module of this invention also reduces heat generation and hence the chipset can operate in a more stable environment.  
         [0026]    It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.