Abstract:
A shift register including shift register units substantially cascaded is disclosed. Each shift register unit is controlled by first and second clock signals opposite to each other for generating an output signal. Each shift register unit includes first and second switch devices and first and second devices. The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device provides a first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of Taiwan application Serial No. 97110049 filed Mar. 21, 2008, the subject matter of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a shift register, and more particularly to a shift register unit providing an output signal which is not affected by shifting of threshold voltages of transistors in the shift register unit. 
     2. Description of the Related Art 
     In current liquid crystal display panels, gate drivers and drain drivers are arranged to provide scan signals and data signal. In order to decrease cost, a shift register which has the same function as a gate driver is arranged in a glass panel. Most shift registers are formed by amorphous silicon thin-film processes. When a display panel is lit, transistors of a shift register in the display panel are affected by stress, and the display panel thus operates irregularly. 
       FIG. 1  shows a conventional shift register unit of a shift register.  FIG. 2  is a timing chart of signals of the shift register unit in  FIG. 1 . Referring to  FIGS. 1 and 2 , a shift register unit  1  is controlled by clock signals CK and XCK opposite to each other, that is, the clock signals CK and XCK have inverse phases, and are coupled to a low voltage source Vss. The shift register unit  1  receives output signals S N−1  and S N+1  respectively from the previous shift register unit and the next shift register unit and generates an output signal S N . At a time point P 10 , the output signal S N−1  is activated, that is, the output signal S N−1  is at a high level, and a transistor T 10  is turned on. A voltage V N10  at a node N 10  is changed to a high level according to the output signal S N−1  to turn on transistors T 11  and T 12 . At this time, since the clock signal CK is at a low level and the transistor T 12  is turned on, a voltage V N11  at a node N 11  is at a low level to turn off a transistor T 13 . A transistor T 15  is turned on by the clock signal XCK with a high level, and the output signal S N  is de-activated, that is, the output signal S N  is at low level. 
     At a time point P 11 , the output signal S N−1  is de-activated, and the transistor T 10  is turned off. The clock signal CK is changed to a high level. In the period between the time points P 11  and P 12 , the clock signal CK with the high level couples to the node N 10  through a capacitor C 10  and the transistor T 13 , so that the voltage V N10  at the node N 10  is raised to a higher level according to the clock signal CK to turn on the transistors T 11  and T 12 . According to the low voltage source Vss and the turned-on transistor T 12 , the voltage V N11  at the node N 11  remains at the low level to turn off the transistor T 13 . The clock signal CK with the high level is transmitted to an output node N 12  through the turned-on transistor T 11  to serve as the output signal S N , in other words, the output signal S N  is activated. The clock signal XCK with a low level turns off a transistor T 15 , and the voltage V N11  with the low level turns off a transistor T 16 . Accordingly, the output signal S N  can stably remain in the activated state. 
     At a time point P 12 , the clock signal CK is changed to a low level, and the output signal S N+1  is activated to turn on the transistor T 14 . The voltage V N10  at the node N 10  is gradually decreased according to the low voltage source Vss to turn off the transistors T 11  and T 12 . At this time, the clock signal XCK with a high level turns on the transistor T 15 , so that the voltage of the low voltage source Vss is provided to the output node N 12  to serve as the output signal S N , in other words, the output signal S N  is de-activated. 
     At a time point P 13 , the clock signal CK is changed to a high level, and the voltage V N11  at the node N 11  is changed to a high level to turn on the transistor T 13 . Thus, the voltage N 10  remains at a low level. Moreover, the voltage V N11  with the high level turns on the transistor T 16 , so that the output signal S N  remains in the de-activated state. After the time point P 13 , the shift register unit  1  operates according to the clock signal CK and XCK. The voltage V N10  at the node N 11  is switched between a high level and a low level. 
     It is assumed that the high level and the low level of the clock signal CK is 15V and −9V respectively, and the voltage of the low voltage source Vss is −7V. When the clock signal CK is at the high level to turn on the transistor T 13 , the voltage difference between a gate and a source of the transistor T 13  is 22V. If the gate-source voltage Vgs of the transistor T 13  is in the positive base stress for a long period of time, the threshold voltage of the transistor T 13  shifts, and the voltages V N10  and V N11  are irregular, as shown by the dot line in V N10  and V N11  in  FIG. 2 . Thus, when the threshold voltages of the transistors in the shift register unit  1  shift, the shift register unit  1  operates irregularly and outputs an incorrect output signal S N . 
     BRIEF SUMMARY OF THE INVENTION 
     An exemplary embodiment of a shift register comprises a plurality of shift register units substantially cascaded. Each of the shift register units is controlled by a first clock signal and a second clock signal opposite to each other for generating an output signal. The output signal is activated periodically. Each of the shift register units comprises first and second switch devices and first and second driving devices. 
     The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device is coupled to a first voltage signal and provides the first voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. The second switch device is coupled to a second voltage signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal. 
     Another exemplary embodiment of a shift register comprises first, second, and third shift register units substantially cascaded. Each of the first, second, and third shift register unit is controlled by a first clock signal and a second clock signal opposite to each other for generating an output signal. The output signal is activated periodically. Each of the first, second, and third shift register units comprises first and second switch devices and first and second driving devices. 
     The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device is coupled to a first voltage signal and provides the first voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. The second switch device is coupled to a second voltage signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal. The output signal of the first shift register unit serves as the first input signal of the second shift register unit. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows a conventional shift register unit of a shift register; 
         FIG. 2  is a timing chart of signals of the shift register unit in  FIG. 1 ; 
         FIG. 3  shows an exemplary embodiment of a shift register; 
         FIG. 4  shows an exemplary embodiment of a shift register unit; 
         FIG. 5  is a timing chart of signals of the shift register unit in  FIG. 4 ; and 
         FIG. 6  shows element characteristic of the transistor T 13  in  FIG. 1  and the transistor T 41  in  FIG. 4  when they operate for a period of time. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     Shift registers are provided. In an exemplary embodiment of a shift register in  FIG. 3 , a shift register  3  comprises a plurality of shift register units  30   1 - 30   M  substantially cascaded. Each of the shift register units  30   1 - 30   M  is controlled by clock signals CK and XCK and coupled to a voltage source. The clock signals CK and XCK are opposite to each other, that is, the clock signals CK and XCK have inverse phases. Each of the shift register units  30   1 - 30   M  receives a first input signal and a second input signal and generates an output signal according to the clock signals CK and XCK. Output signals S 1 -S M  generated by the shift register are activated substantially, and each of the output signals S 1 -S M  is activated periodically. 
     Each ( 30   N ) of the shift register units  30   1 - 30   M  receives an output signal S N−1  generated by the previous shift register units  30   N−1  to serve as the first input signal and an output signal S N+1  generated by the next shift register units  30   N+1  to serve as the second input signal, wherein 1&lt;N&lt;M, and N is an integer. The output signals S N−1 , S N , and S N+1  are activated substantially. For example, the shift register units  30   2  receives the output signal S 1  generated by the previous shift register units  30   1  and the output signal S 3  generated by the next shift register units  30   3  and generates the output signal S 2 . The output signal S 2  generated by the shift register units  30   2  is received by the next shift register units  30   3 . 
     The shift register units  30   1 , which is the first stage of the shift register  3 , receives the output signal S 2  from the shift register units  30   2  to serve as the second input signal. The shift register units  30   1  further receives a driving signal S D  generated by an external or internal circuit to serve as the first input signal. The driving signal S D , the output signal S 1 , and the output signal S 2  are activated substantially. Similarly, the shift register units  30   M , which is the last stage of the shift register  3 , receives the output signal S M−1  from the shift register units  30   M−1  to serve as the first input signal. The shift register units  30   M−1  further receives a control signal S C  generated by an external or internal circuit to serve as the second input signal. The output signal S M−1 , the output signal S M , and the control signal S C  are activated substantially. 
       FIG. 4  shows an exemplary embodiment of a shift register unit. In the embodiment in  FIG. 4 , the shift register unit  30   2  of the shift register  3  is given as an example for description, and the other shift register units  30   1  and  30   3 - 30   M  have the same circuitry as the shift register units  30   2 . The shift register units  30   2  receives the output signal S 1  generated by the previous shift register units  30   1  to serve as the first input signal and the output signal S 3  generated by the next shift register units  30   3  to serve as the second input signal. 
     The shift register unit  30   2  comprises driving devices  40 - 42 , switch devices  43 - 46 , and a capacitor C 40 . In the embodiment, the driving devices  40 - 42  and the switch devices  43 - 46  are implemented respectively by NMOS transistors T 40 -T 42  and T 43 -T 46 . Sources of the transistors T 42  and T 44 -T 46  are coupled to a voltage source Vss 1 , and a source of the transistor T 41  is coupled to a voltage source Vss 2 . A level (VL 2 ) of a voltage signal provided by the voltage source Vss 2  is lower than a level (VL 1 ) of a voltage signal provided by the voltage source Vss 1 . In the following description, a state of a signal being at a high level indicates the signal is activated, while a state of a signal being at a low level indicates the signal is de-activated.  FIG. 5  is a timing chart of signals of the shift register unit in  FIG. 4 . The detailed operation of the shift register unit  30   2  is described in the following. 
     At a time point P 50 , the output signal S 1  is changed to a high level, and a transistor T 40  is turned on. A voltage V N40  at a node N 40  is changed to a high level according to the output signal S 1  to turn on transistors T 43  and T 44 . At this time, since the clock signal CK is at a low level and the transistor T 44  is turned on, a voltage V N41  at a node N 41  is at the low level to turn off a transistor T 41 . A transistor T 45  is turned on by the clock signal XCK with a high level, so that the output signal S 2  is at a low level, that is the output signal S 2  is de-activated. 
     At a time point P 51 , the output signal S 1  is changed to a low level, and the transistor T 40  is turned off. The clock signal CK is changed to a high level. In the period between the time points P 51  and P 52 , the clock signal CK with the high level couples to the node N 40  through a capacitor C 40  and the transistor T 41 , so that the voltage V N40  at the node N 40  is raised to a higher level according to the clock signal CK to turn on the transistors T 43  and T 44 . A low-level voltage signal provided by the voltage source Vss 1  is transmitted to the node N 41  to turn off the transistor T 41 , that is the transistor T 41  is disabled. The clock signal CK with the high level is transmitted to an output node N 42  through the turned-on transistor T 43  to serve as the output signal S 2 , in other words, the output signal S 1  is activated. The low-level voltage signal provided by the voltage source Vss 1  is transmitted to the node N 41 , and voltage V N41  remains at the low level to turn off the transistor T 46 . The clock signal XCK with a low level turns off the transistor T 45 . Accordingly, the output signal S 1  can stably remain in the activated state. 
     At a time point P 52 , the clock signal CK is changed to a low level, and the output signal S 3  is activated to turn on the transistor T 42 . The voltage V N40  at the node N 40  is gradually decreased according to the low-level voltage signal of the voltage source Vss 1  to turn off the transistors T 43  and T 44 , so that the transistor T 43  does not activate the output signal S 2 . At this time, the clock signal XCK with a high level turns on the transistor T 45 , so that the low-level voltage signal of the voltage source Vss 1  is provided to the output node N 42  to serve as the output signal S 2 , in other words, the output signal S 2  is de-activated. 
     At a time point P 53 , the clock signal CK is changed to a high level, and the voltage V N41  at the node N 41  is changed to a high level to turn on the transistor T 41 . The low-level voltage signal of the voltage source Vss 2  is coupled to the node N 40  through the turned-on transistor T 41 . Thus, the voltage V N40  at the node N 40  remains at a low level to turn off the transistor T 43 , so that the transistor T 43  does not activate the output signal S 2 . Moreover, the voltage V N41  with the high level turns on the transistor T 46 , and the low-level voltage signal of the voltage source Vss 1  is provided to the output node N 42  to serve as the output signal S 2 . Thus, the output signal S 2  remains in the de-activated state. After the time point P 53 , the shift register unit  30   2  operates according to the clock signal CK and XCK. The voltage V N41  at the node N 41  is switched between a high level and a low level. 
     It is assumed that the high level and the low level of the clock signal CK is 15V and −9V respectively, the voltage signal of the voltage source Vss 1  is −7V, and the voltage signal of the voltage source Vss 2  is −10V. When the clock signal CK is at a high level to turn on the transistor T 41 , the voltage difference between a gate and a source of the transistor T 41  is 25V. The gate-source voltage Vgs of the transistor T 41  is in the large positive base stress. Compared with the transistor T 13  in  FIG. 1 , since the gate-source voltage Vgs of the transistor T 41  is in a larger positive base stress than that of the gate-source voltage Vgs of the transistor T 13  (25V&gt;22V), a drain-source current Ids generated by the transistor T 41  is larger than that of a drain-source current Ids generated by the transistor T 13 .  FIG. 6  shows element characteristic of the transistor T 13  in  FIG. 1  and the transistor T 41  in  FIG. 4  when they operate for a period of time. Referring to  FIG. 6 , the drain-source current Ids corresponding to the 25V gate-source voltage Vgs is larger than the drain-source current Ids corresponding to the 22V gate-source voltage Vgs. If the positive gate stress induces the threshold voltage of the transistor T 41  shifting, the shift register unit  30   2  can operate regularly because the transistor T 41  generates a larger drain-source current Ids. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.