Abstract:
A dual sense non-differencing peak detector locates a peak without introducing unwanted noise components, and also corrects for signal asymmetries. This is accomplished by identifying two sequential sets of two successive samples each. The first set includes samples that fall on each side of a threshold voltage on the rising edge of the signal. The second set includes samples that fall on each side of the threshold on the falling edge of the signal. For each of the two sets of samples, the point at which the signal substantially equals the threshold is found by interpolation. The two threshold points, for a symmetrical signal, fall equidistant from the peak, and hence the peak is easily located as being equidistant therebetween.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to the field of peak detectors and more particularly, to a digital peak detector which determines dual threshold voltage crossing points by interpolation and estimates a peak position therefrom. 
     BACKGROUND OF THE INVENTION 
     Data processing systems rely upon stored information for manipulating data and performing applications that the data processing systems are required to perform. The stored information can include an application program which instructs the data processing system, for example, on how to manipulate data, or the information can be the data itself. In any event, in all but the smallest applications, it is usually necessary to move the information from a storage medium to the data processing system&#39;s internal memory before processing can proceed. There exists many different forms of storage media for storing the information needed in the data processing systems. 
     Three typical forms of storage media include magnetic disks, optical disks and magnetic tape. A common form of magnetic disk storage media is direct access storage devices (DASD). DASD offers high storage capacity while providing relatively fast access to the information stored thereon. Optical disks are capable of storing larger amounts of information than DASD but require more time to access the stored information. Magnetic tape presently has the ability to store the largest amount of information but data access is much slower than DASD or optical disks. Magnetic tape&#39;s combination of high storage capacity, slow access speed, and low cost make it well suited for information back-up purposes 
     Regardless of the storage medium used, the stored information must be read therefrom and converted into a form the data processing system can recognize. In the case of DASD and optical storage media, the information is stored on rigid discs that spin at a given speed while a read head, stationed just above the storage medium, recognizes the bits of 1&#39;s and 0&#39;s that make up the stored information and converts them into electrical signals. Magnetic tape is typically stored on a reel or cartridge and the tape is forced to travel across a tape read head at a given speed while the tape read head detects the information stored on the tape as it passes by the read head. When very large amounts of information are required to be retrieved from the storage medium, the time required to access that information is an important factor. The access time is a function of the speed at which the storage medium travels past the read head. However, increasing the storage medium speed generally results in increased read errors. 
     A common read error problem occurs as a result of timing failures. Each bit of information read from the storage medium must occur within a specified time window. If the position of the storage medium, for a given bit, is outside the expected time window, the data processing system will receive erroneous information. Hence, it is vital that the storage medium be synchronized to a data clock. Synchronization requires that the data clock be adjusted frequently by estimating a phase error between the bits of information read from the storage medium and the data clock. The phase error estimate is used to adjust the data clock. 
     The timing problem is further exacerbated since the data recovered from the storage medium is an analog signal requiring further processing to discriminate between binary ones and zeros. For example, a positive and/or negative pulse (above a predetermined threshold voltage) represents a binary one, and an absence of a pulse (below the threshold voltage) represents a binary zero. Conveniently, the peak of the pulse may be used to recover the timing information. Hence, each binary one recovered from the storage medium provides the opportunity to correct phase errors. The position of the peak for continuous-time signals (the analog signal) is the zero-crossing point of the signal&#39;s derivative. 
     The signal&#39;s derivative is input to a comparator and compared to a ground signal (zero volts). Thus, when the derivative equals zero, the comparator so indicates. Taking the derivative, however, poses at least two problems which cause errors resulting in clock jitter. First, taking the derivative introduces additional noise which is especially pronounced at low signal levels. Second, as the signal approaches zero volts, the noise causes many zero crossings. Garrett describes a circuit in U.S. Pat. No. 3,727,079 for reducing noise introduced by differentiation. Garret recognizes that the differentiated signal results in many false zero-crossings due to noise. Described by Garrett is a differential comparator for identifying zero-crossings, and associated latching circuitry to select a single zero-crossing while subsequent zero-crossings Cloke, in U.S. Pat. No. 4,697,098, describes a detecting circuit which also reduces errors. Cloke teaches using two threshold comparators for receiving a signal (a first comparator receives the signal after a delay, a second comparator receives the signal after differentiation). The differentiated signal is also input into a zero-crossing detector. Validation logic then determines, from the two comparators and the zero-crossing detector, which qualifies as the correct zero-crossing signal. An obvious drawback of the above approaches is the increased complexity, and hence increased cost, required. 
     The costs and reliability of systems can be improved by implementing prior analog circuits into digital systems. The digital systems can be fabricated in LSI (large scale integration) or VLSI (very large scale integration) circuits. In the discrete-time or digital systems, the continuous-time signal is represented by successive digital samples. Each digital sample consists of a predetermined number of bits, for example 4, wherein the bits are a binary representation of the magnitude of the continuous-time signal at the instant each sample is taken. Most often, the digital samples will not occur at a peak position and so the peak position must be estimated from the digital samples taken prior to and subsequent to the peak. A common method of predicting the peak position is by determining the zero-crossing point of the difference of two successive samples. This differencing operation, however, introduces noise, and fails to correct for peak asymmetry. Also, peaks that are not sharp are difficult to locate. 
     Thus what is needed is a digital peak detector that is able to accurately estimate peak locations, even though a signal may be asymmetrical, or the peak is relatively flat, without introducing noise. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide an improved digital peak detector. 
     Another object of the present invention is to provide a digital peak detector that estimates the location of a peak without using differentiation. 
     Yet another object of the present invention is to provide a digital peak detector that estimates the location of a peak without introducing noise components while correcting for signal asymmetries. 
     Still another object of the present invention is to provide a digital peak detector for locating a signal&#39;s peak by identifying samples on each side of the peak, interpolating to locate the points where the signal equals a predetermined threshold voltage, and locating the peak midway therebetween. 
     These and other objects of this invention are accomplished by a dual sense digital peak detector for determining the center point of a signal pulse based upon samples taken therefrom. The dual sense digital detector includes first and second comparator circuits for identifying two sequential events. A first event includes two successive samples, wherein a first of which has an absolute value less than a threshold, and a second of which has an absolute value greater than or equal to the threshold. The second event also includes two successive samples, wherein a first of which has an absolute value greater than or equal to the threshold and a second of which has an absolute value less than the threshold. The sample of the first event that has an absolute value greater than or equal to the threshold may be the same sample of the second event that has an absolute value greater than or equal to the threshold. This implies that a minimum of three samples are required for the first and second events to be detected. 
     An interpolation circuit, coupled to the first and second comparator circuits, determines, by interpolation, a first point located between the two samples of the first event, wherein the signal pulse is substantially equal to the threshold. The interpolation circuit also determines a second point, by interpolation, located between the two samples or the second event, wherein the signal is again substantially equal to the threshold. Having determined the first and second points where the signal is equal to the threshold, the peak is estimated by finding a point equidistant therebetween. 
     The digital peak detector does not depend upon taking the derivative of the signal (or the difference between successive samples) and does not introduce noise by the processing thereof. Relatively flat peaks do not pose problems since once the threshold points are found, an ideal peak would be located centered between the two. Additionally, asymmetric signal errors can be minimized by choosing the threshold appropriately. An exact estimate is made when the pulse is symmetric. 
     The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiment of the invention, as illustrated in the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1A is a signal diagram showing a signal pulse having a peak, the pulse crossing through a threshold. 
     FIG. 1B is a signal diagram showing a plurality of digital samples taken of the analog signal pulse shown in FIG. 1A. 
     FIG. 2 is a block diagram of the digital peak detector. 
     FIG. 3 is a schematic diagram of blocks 2, 3, and 4 as shown in FIG. 2. 
     FIG. 4 is a schematic diagram of blocks 5 and 6 as shown in FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1A depicts a pulse of a continuous-time signal, u(t), that represents a binary one. The test of whether a binary one is represented is simply whether the pulse exceeds a predetermined threshold voltage v t . Importantly, timing information is associated with the pulse, that is, the pulse must properly coincide with a system clock. More specifically, the peak of the pulse should, occur relative in time to the clock. If the peak occurs too far prior or subsequent to the clock, the pulse will be mistaken for another bit of data and errors will ensue. The pulse occurs at time t c , which is defined for a symmetrical signal by the equation: 
     
         t.sub.c =0.5*(t.sub.1 +t.sub.2).                           (1) 
    
     The peak position of u(t) does not always coincide exactly with t c  due to the asymmetry. However, since asymmetry is caused by distortion in a channel, t c  is closer to where the peak would have occurred in the absence of distortion. In analog systems, t c  is found by taking derivatives of the continuous-time signal. It is often advantageous to take digital samples of the continuous-time signal and process the samples digitally. Digital processing of signals is more accurate and independent of component variations. 
     FIG. 1B shows a plurality of digital samples, u{n}, taken from the continuous-time signal u(t), wherein n is an integer describing the nth digitized read pulse, and T s  is the sampling period. Each digital sample is represented by a plurality of bits, i.e., eight bits, wherein the number of bits determines the resolution of the sample. Generally, the samples will not occur at t 1  or t 2 , that is, when u(t) equals v t . Therefore, t 1  and t 2  will have to be computed from the digital samples prior to and subsequent to v t . In the preferred embodiment, t 1  and t 2  are found by linear interpolation: 
     
         t.sub.1 =(n.sub.0 +r)T.sub.s ;                             (2a) 
    
     
         t.sub.2 =(n.sub.0 +k-1+s)T.sub.s ;                         (2b) 
    
     wherein n 0  is an index of a digital sample just prior to v t  on the rising edge of the pulse; k is an integer representing a number of digital samples taken since n 0  and until {n} is again less than v t  ; and r and s are fractional values. 
     Using linear interpolation it is possible to determine the values of r and s: 
     
         r=(v.sub.t -u{n.sub.0 })/(u{n.sub.0 +1}); and              (3a) 
    
     
         s=(v.sub.t -u{n.sub.0 +k-1})/(u{n.sub.0 +k}-u{n.sub.0 +k-1} 
    
                                                                (3b) 
     An assumption can be made that t c  is located equidistant between t 1  and t 2 . This assumption is valid when: the pulse is symmetric; or the asymmetry in the pulse is caused by distortions, as in most cases, viz. optics, DASD, and tapes; and the threshold, v t , is chosen to minimize the effect of asymmetry. Using the assumption that t c  is located equidistant between t 1  and t 2 , t c  can then be calculated from equations (1), (2a, b), and (3a, b) as: 
     
         t.sub.c =(n.sub.0 +(k-1)/2+(r+s)/2)*T.sub.s.               (4a) 
    
     Equation (4a) is simplified, without loss of generality by allowing n 0  to equal 0, thus 
     
         t.sub.c =(k-1+r+s)/2.                                      (4b) 
    
     In equation (4b), r and s are continuous variables which, in an actual digital system must be implemented as discrete values representing fractions of the clock period, T s . Such a fractional value is conveniently represented by a gate delay, T G , such that: 
     
         T.sub.s =M*T.sub.G ;                                       (5) 
    
     wherein M is a positive integer. The fractional values r/2 and s/2 may then be replaced by non-negative integers, p r  and p s , respectively, wherein: 
     
         p.sub.r ={r*M/2}; and                                      (6a) 
    
     
         p.sub.s ={s*M/2};                                          (6b) 
    
     wherein {.} indicates the integer part of the argument. The peak position, t c , is now defined as: 
     
         t.sub.c ={(k-1+r+s)/2}*t.sub.s +p.sub.r *T.sub.G +p.sub.s *T.sub.G.(7) 
    
     Referring now to FIG. 2, a dual sense peak detector 1 is shown having an event detector 2, a peak estimator 3, a fixed delay 4, an integer delay 5, and a fractional delay 6. The event detector 2 receives digitized data samples of a data signal, for example, a data signal read from a storage medium. The event detector 2 determines when first and events occur. A first event, X 1 , occurs when two successive samples have magnitudes less than, and greater than or equal to the threshold voltage, v t , respectively. Similarly, a second event, X 2 , occurs when two other successive samples have magnitudes greater than or equal to, and less than the magnitude of v t , respectively. The event X 1  is input into the fixed delay 4 which provides a delay having a predetermined length, the delay being triggered by the event X 1 . The delay provides sufficient time for the peak to be estimated by the peak estimator 3. 
     The peak estimator 3 receives both the digitized data samples and the event signals X 1  and X 2 . The peak estimator 3 operates on successive samples to determine, when a pulse has been identified, where the peak is located. The peak location is referenced to X 1 , wherein the peak is located by an appropriate delay from X 1  which includes an integer and fractional component. The integer component, IC, is input into the integer delay 5, wherein the integer delay 5 provides a delay substantially equal to the calculated integer component. The fractional component, FC, is input into the fractional delay 6, wherein the fractional delay 6 provides a delay substantially equal to the calculated fractional component. The fixed delay 4 outputs a predetermined fixed delay, FD, which is connected to the integer delay 5. The output of the integer delay 5 is connected to an input of the fractional delay 6. The integer and fractional delays are added to the fixed delay, FD, such that the output of the fractional delay 6 is a data pulse that occurs at the time of the peak plus the fixed delay. 
     FIG. 3 is a schematic diagram of the event detector 2, the peak estimator 3, and the fixed delay 4. The event detector 2 includes a comparator 11, a comparator 12, and a register 13 for simultaneously comparing the magnitudes of two successive data samples to v t . If two successive samples meet the requirements necessary for the event X 1  to occur, logic gates 14-15 will cause a signal X&#39; 1  to go &#34;high&#34;. Similarly, if another two successive samples meet the requirements necessary for the event X 2  to occur, the logic gates 16-17 will cause a signal X&#39; 2  to go &#34;high&#34;. Each comparator 11 and 12 has v t  applied to an A input, and the comparator 11 has the data samples applied to a B input. The register 13 also has the data samples applied to an input and has an output connected to a B input of the comparator 12. A clock signal, CLOCK, is also connected to the register 13 for enabling a data sample to be loaded on each clock cycle. The comparators 11 and 12 each have the clock connected thereto for operating synchronously. Hence comparator 11 is comparing a current data sample, for example u{n 0  +1}, while the comparator 12 is comparing a previous data sample, for example u{n 0  }.In the present embodiment, each data sample is made up of eight data bits, m. The register 13 thus includes eight storage elements and the A and B inputs of the comparators 11 and 12 are eight bits wide. 
     The comparator 11 has an A&lt;B output and an A=B output connected to inputs of an OR gate 14, and the comparator 12 has an A&lt;B output and an A=B output connected to inputs of an OR gate 16. An output of each OR gate 14 and 16 is connected to an input of each AND gate 15 and 17, respectively. Also, an A&gt;B output of each comparator 11 and 12 is connected to another input of each AND gate 17 and 15, 21 respectively. The AND gate 15 provides the X&#39; 1  signal at an 22 output and the AND gate 17 provides the X&#39; 2  signal at an output. The outputs of the AND gates 15 and 17 are connected to an input of registers 18 and 19, respectively. Registers 18 and 19 are single bit registers, having a /RS1 input (active &#34;low&#34; reset) connected to a RS1 signal, and having a clock input connected to the clock signal. The event signals, X 1  and X 2 , are made available at the outputs of the registers 18 and 19, respectively. 
     The following example illustrates how events X 1  and X 2  are detected. Referring back to FIG. 1B. at time n 0 , data sample u{n 0  } is made available to the comparator 11 and data sample u{n 0  -1} has previously been loaded into the register 13. The comparisons made by the comparators 11 and 12 results in the A&lt;B and the A=B outputs of both comparators 11 and 12 to be &#34;low&#34; since the magnitudes of both u{n 0  -1} and u{n 0  } are less than magnitude of v t . The outputs of the OR gates 14 and 16 are also &#34;low&#34; thereby disabling the AND gates 15 and 17, respectively. Hence, neither event X 1  or X 2  has been detected. At time n 0  +1, the data sample u{n 0  } is stored in the register 13 and made available at the B input of the comparator 12, and the data sample u{n 0  +1} is made available at the B input of comparator 11. This time the A&lt;B output of the comparator 11 is &#34;high&#34; while the A&lt;B and the A=B outputs of the comparator 12 remain low (v t  is greater than u{n 0  }, and the A&gt;B output is high. The output of the OR gate 14 is high causing the output of the AND gate 15, X&#39; 1 , to go &#34;high&#34;. X&#39; 1  is loaded into the register 18 and X 1  is available one clock cycle later signifying the event X 1  has occurred. 
     Detecting event X 2  is similar, wherein the data sample u{n 0  +k} is made available to the comparator 11 and the data samples u{n 0  +k-1} is made available to the comparator 12 at time n 0  +k. This time the A&gt;B output of the comparator 11 is &#34;high&#34; (v t  is greater than u{n 0  +k}), and the A&lt;B output of the comparator 12 is &#34;high&#34; (v t  is less than u{n 0  +k-1}). The output of the OR gate 16 goes &#34;high&#34; and the output of the AND gate 17, X&#39; 2 , also goes &#34;high&#34;. X&#39; 2  is loaded into the register 19 and X 2  is available a clock cycle later signifying the event X 2  has occurred. 
     The fixed delay 4 is made up of registers 21-24, wherein each register has a clock input connected to the clock signal. The register 21 has an input connected to the of the register 18 (X 1 ), and the registers 21-24 are sequentially connected. In the preferred embodiment, the fixed delay is 15 clock cycles and hence, there are eleven additional registers coupled between the registers 23 and 24. When the event X 1  detected, a &#34;one&#34; is propagated through the registers 21-24 such that fifteen clock cycles later the FD signal at an output of the register 24 goes &#34;high&#34;. X 1  is thus a reference from which an additional calculated delay will be added for locating the peak. 
     The peak estimator 3 receives successive data samples that are delayed three clock cycles and two clock cycles, respectively, by registers 27 and 28, and 29 and 31, respectively. The register 27 has an input connected to the output of the register 13, and the register 29 has an input connected for directly receiving the data samples. The register 28 has an input connected to an output of the register 27, and the register 31 has an input connected to an output of the register 29. Each of the registers 27-29, and 31 are made up of m storage elements and each and are connected to the clock signal. The sampled data appears at the output of the register 31 delayed by two clock cycles, and at the output of the register 28 delayed by three clock cycles. The output of the register 28 is connected to a negative input of adders 32 and 33. The threshold voltage, v t , is applied to a positive input of the adder 32, and the output of the register 31 is connected to a positive input of the adder 33. Each adder 32 and 33 has the clock signal connected thereto. 
     The adder 33 determines the difference between successive data samples. Simultaneously, the adder 32 determines the difference between each data sample and v t . An output of the adder 32 is input into an A input of a divider 34. Likewise, an output of the adder 33 is input into a B input of the divider 34. The divider 34, being connected to the clock signal, divides the A input by the B input on each clock cycle. An output of the divider 34, being made up of n bits, is connected to an input of registers 35 and 36. A load input, /LD, of the register 35 is connected to an output of the register 22. As a result, the only time the register 35 is loaded with the division performed by the divider 34 is after an event X 1  has occurred (the division of the event X 1  occurs two clock cycles later and so loading the register 35 is delayed two clock cycles). By design, the outputs of the adders 32 and 33 are always non-zero with the same sign. Thus, problems associated with divide by zero or division by two arguments with dissimilar signs never occur when the events X 1  or X 2  are detected. Moreover, the output of the divider 34 is always positive. Two registers, 25 and 26, are sequentially connected to an output of the register 19 for receiving the event X 2  signal. An output of the register 26 is connected to a load input, /LD, of the register 36. Hence, the register 36 will store the results of a division performed by the divider 34 only after an event X 2  has been detected. Each register 35 and 36 is made up of n storage elements, each being connected to the clock signal. 
     Continuing with the previous example, after the event X 1  has been detected, the data sample u{n 0  } is made available at the negative input of the adders 32 and 33. Also, the data sample u{n 0  +1} is made available at the positive input of the adder 33. The adder 32 thus calculates v t  -u{n 0  }, and the adder 33 calculates u{n 0  +1}-u{n 0  }. On the next clock cycle, the divider 34 divides the A input by the B input, or (v t  -u{n 0} )/u{n 0  +1}-u{n 0  }) which is equal to r as shown in equation (3a). One clock cycle later, the result r is loaded into the register 35. In the preferred embodiment, r is represented by four bits, n. However, it will be appreciated by those skilled in the art that the number of bits n may vary depending upon the degree of accuracy desired. 
     Determining s is similar to determining r. After the event X 2  has been detected, the data sample u{n 0  +k-1} is made available at the negative inputs of the adders 32 and 33. Also, the data sample u{n 0  +k} is made available at the positive input of the adder 33. The adder 32 thus calculates v t  -u{n 0  +k-1}, and the adder 33 calculates u{n 0  +k}-u{n 0  +k-1}. On the next clock cycle, the divider 34 divides the A input by the B input, or (v t  -u{n 0  +k-1})/(u{n 0  +k{-u{n 0  +k-1} which is equal to s as shown in equation (3b). One clock cycle later, the result s is loaded into the register 36. 
     An output of the register 35, having n bits, is connected to an input of an adder 37. An output of the register 36, also having n bits, is connected to another input of the adder 37. The clock signal is connected to the adder 37, and a logical &#34;one&#34; is connected to a carry in input, C IN . The outputs of the adders 35 and 36, r and s, respectively, are added in the adder 37. A counter 38 has a signal X&#39;&#39; 1  connected to an enable input, EN, wherein X&#39;&#39; 1  is equivalent to X&#39; 1  delayed by one clock cycle. The signals X&#39;&#39; 1  and X&#39;&#39; 2  differ from X 1  and X 2 , respectively, in that X&#39;&#39; 1  and X&#39;&#39; 2  remain &#34;high&#34; until X&#39; 2  goes &#34;high&#34; while X&#39; 1  stays &#34;low&#34;. Another signal, X&#39;&#39; 2  is connected to a hold input, HLD, of the counter 38, wherein X&#39;&#39; 2  is equivalent to X&#39; 2  delayed by one clock cycle. The counter 38 has a clock input connected to the clock signal, and has another input, /RST, connected to a RESET signal. The counter 38 counts the number of data samples taken between the event X and the event X 2 , or k-1. 
     An output of the counter 38, having n bits, is connected to an input of an adder 39. A second input of the adder 39 is connected to a logical &#34;0000&#34; so that the data sample count is not changed by adding to it. A carry out, C OUT , of the adder 37 is connected to a C IN  input of the adder 39. The three most significant bits (MSBs) of an output of the adder 37, and the least significant bit (LSB) of an output of the adder 39, are connected to an input of a register 41. An output of the register 41 provides the signal FC which is connected to the fractional delay 6. The three MSBs of the output of the adder 39, and the C OUT  of the adder 39 are connected to an input of a register 42. An output of the register 42, IC, is connected to the integer delay 5. The counters 37 and 39 and the registers 41 and 42 are both connected to the clock signal. Each register 41 and 42 has a /LD input connected to a RS2 signal. 
     A shift right operation is effectively performed by connecting the three MSBs of the counter 37 and the LSB of the counter 39 to the register 41. The effect of shifting right is to divide the adder 37 and 39 results by two, hence the input to the register 41 is the fractional part of (k-1+r+s)/2. That is, the fractional delay is derived from equation (4b). Likewise, connecting the three MSBs and the C OUT  of the adder 39 to the register 42 provides the integer portion of (k-1+r+s)/2. That is, the integer delay is derived from equation (4b). Equation (4b) has effectively been calculated by the peak estimator 3 with the fraction and integer portions separated into registers 41 and 42, respectively. The fractional and integer delays are realized electronically by the fractional delay 6 and the integer delay 5, respectively. 
     Resetting the several registers shown in FIG. 3 is accomplished by a specific reset circuit. A NAND gate 43 has a /X&#39; 1  signal and the X&#39; 2  signal connected to its inputs and provides the RS1 signal at its output. A NAND gate 44 has the X&#39;&#39; 1  and the X&#39;&#39; 2  signals connected to its inputs and provides the RS2 signal at its output. An AND gate 45 has the RS1 and RS2 signals connected to two inputs, and additionally has a hard reset signal connected to another input. The RESET signal is provided at an output of the AND gate 45. 
     Referring now to FIG. 4, the integer delay 5 and the fractional delay 6 are shown in greater detail. The integer delay 5 includes a plurality of registers 51-54 sequentially connected, and each register 51-54 is connected to the clock signal. Each register 51-54 provides a delay of one (a data sample is taken on each clock cycle and each register is clocked on each clock cycle). A multiplexer 55 is also provided having 16 multiplexed inputs, the first input connected to the FD signal, and the remaining inputs each connected to an output of a register 51-54. In the preferred embodiment, fifteen registers are provided, wherein the number of registers to be included in the integer delay is determine by the IC signal which is made up of four bits. The IC signal is connected to a select input, SEL, of the multiplexer 55. The clock signal is also connected to the multiplexer 55. 
     The FD signal is also connected to the input of the register 51. As a result, after the event X 1  signal has propagated through the fixed delay 4, FD is delayed an additional number of clock signals according to IC (IC may equal zero in which case no additional delay is added). An output of the multiplexer 55 is connected to a first input of a multiplexer 61, and further connected to an input of a 28 buffer 56. Additional buffers 57-59 are serially connected with an output of each being connected to a respective input of the multiplexer 61. Each buffer 56-59 provides a fraction of a single integer delay as described by equations (5) and (6a,b). The FC signal is connected to a select input, SEL, of the multiplexer 61. In the preferred embodiment, the OP1 signal is four bits for selecting none or one to 15 buffers as are provided for creating the fractional delay portion. Whereas the multiplexer 55 is clocked and is therefore synchronous, and the multiplexer 56 has is not clocked and is therefore asynchronous. 
     An output of the multiplexer 61 provides a data pulse which represents the fixed delay plus the integer delay portion plus the fractional delay portion. The peak is thus located by adding the the integer delay portion and the fractional delay portion to the event X 1  The fixed delay has been introduced for allowing the calculation of the integer and fractional portions of the delay. Since all peak locations are shifted by a constant value equal to the fixed delay, the relative position of the peaks remain unchanged. Hence, the addition of a fixed delay has no effect on the peak locations. The peak has thus been determined without taking the derivative of the pulse and additional noise errors have not been introduced. 
     A small error may result from having a finite number of buffers in generating the fractional delay portion. This delay may be minimized by choosing the appropriate number of buffers (the number of buffers chosen are of course limited by the number of bits, n, used in determining the fractional delay). The multiplexor 61 may also introduce a very small error due to different data paths within the multiplexor 61 having different delays. Such differences are small in most integrated circuits and can usually be ignored. 
     While the invention has been particularly described with reference to particular embodiments thereof, it will be understood by those skilled in the art that various other changes in detail may be made therein without departing from the spirit, scope, and teaching of the invention. The invention has been described using a positive pulse as an example, but it will be understood by those skilled in the art that the invention applies equally to negative pulses. The invention is further applicable to other than data transfer functions, for example, the invention is applicable to image processing, wherein gray level information is carried on signal edges, and the edge locations are determined from the peak locations of the derivatives. 
     Accordingly, the invention herein disclosed is to be limited only as specified in the following claims.