Abstract:
An electronic camera is provided as a module that attaches to the signal bus of a PC-compatible computer. The camera includes a minimum of components, particularly an image sensor and an A/D converter, and a PC-compatible interface connector for mating with a bus extension connector on the computer. By directly presenting digitized data from the camera to the signal bus of the computer through the bus connector, the camera can be kept relatively simple and the computer can be relied upon to perform image processing, storage, and display.

Description:
FIELD OF INVENTION 
     This invention pertains to the field of electronic imaging and, more particularly, to an image acquisition peripheral operated as an input device to a portable computer. 
     BACKGROUND OF THE INVENTION 
     It is well known to use a video camera with a computer frame grabber. A typical system employs a video motion camera (such as the CCD 4000 RGB Flash-Sync Camera manufactured by Eastman Kodak Co., Rochester, N.Y.) and a frame grabber board (such as a TARGA.sup.(™) frame store board manufactured by True Vision, Inc., Indianapolis, Ind.) attached to the PC bus of a personal computer. The camera provides the timing to interface with the video frame store board by activating the frame acquire line of the frame store board whenever an external voltage input to the camera is dropped low (e.g., by dropping the &#34;Camera Acquire In&#34; line to the CCD 4000 camera). It is customary to design software to activate the camera&#39;s frame acquire line from the computer. To capture an image into the computer in such a customary application, the operator frames the subject while observing the live camera output on a video monitor, and then interacts with the computer keyboard at the proper moment. 
     Another approach to computer image acquisition is described in U.S. Ser. No. 805,220, entitled &#34;Hand-Manipulated Electronic Camera Tethered to a Personal Computer,&#34; which was filed Dec. 11, 1991 in the names of K. A. Parulski, R. H. Hamel, and J. J. Acello, and assigned to the assignee of the present application. In this system an electronic camera is coupled to a personal computer through a computer interface. In particular, a digital interface standard may be used, and images from the camera are input to the computer through a Small Computer System Interface (SCSI). The camera is preferably linked, or tethered, to the computer with a cable, thus allowing a certain amount of mobility for the camera independent of the computer. 
     Both of these known interfaces have drawbacks. The NTSC signal is an analog signal subject to noise, and additionally requires a special frame grabber card in the computer to decode and digitize the signal. The SCSI signal has a relatively low data rate and a complicated protocol, requiring an expensive SCSI interface integrated circuit in the camera. Notwithstanding such drawbacks, the system described in Ser. No. 805,220 provides a low cost electronic still camera which attaches to a personal computer that provides image processing, storage, and display. By relying on the computer to perform these tasks, the camera cost can be greatly reduced. 
     A customized high speed bus connection is described in U.S. Pat. No. 4,196,450 for transferring data between a scanner and a specialized processing system. A special architecture is required, including an interprocessor link between a low speed section, having a standard Intel 8080 microprocessor connected to a low speed data bus, and a high speed section having a high speed bus and high speed microprocessor for handling scan data from the scanner. As the scanner is moved across an image page, scan data is supplied to the high speed data bus. Communication between the high speed and the low speed sections is through the interprocessor link. The shortcoming of this arrangement is that a custom computer, including a non-compatible bus, must be built just to handle, process, and store images. 
     In all of these systems, there is need for a low cost means of digitally interfacing a small camera peripheral to a-portable computer at a rate higher than that provided by a SCSI interface or an RS-232 input, but without the attendant difficulties of either an analog frame grabbing process or a specialized, non-compatible computer architecture. 
     SUMMARY OF THE INVENTION 
     In accordance with the invention, an electronic camera operates in conjunction with a portable computer of the type having a plurality of digital devices, including a central processing unit (CPU) interconnected by a standardized, industry-compatible signal bus. The electronic camera includes an image sensor and means for digitizing image data output from the sensor. Means are provided for enabling attachment of the camera to the portable computer. The camera module further includes bus-compatible connection means for engaging the signal bus, and means for providing the digitized image data to the signal bus through the bus-compatible connection means when the camera is attached to the portable computer. In a preferred embodiment, the signal bus is a PC compatible bus and the connector means is a PC-compatible connector. 
     The advantage of the invention is that the camera can be designed as an inexpensive &#34;clip-on&#34; accessory that mates with a portable computer through its bus slot. The computer can be thus relied upon to perform image processing, storage, and display, and the cost of the camera may be accordingly reduced. The bus connection provides a high speed parallel interface for rapidly transferring image data from an image sensor to a memory device in the personal computer. In particular, by using an ISA (Industry Standard Architecture) bus, existing portable computer designs can be used, rather than requiring the development of a special computer incorporating a specialized bus architecture. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in relation to the drawings in which 
     FIG. 1 is an illustration showing an electronic still camera attached to the bus extension connector of a pen-based computer in accordance with the invention; 
     FIG. 2 is an illustration of the electronic still camera shown in FIG. 1; 
     FIG. 3 is an end elevation of the camera of FIG. 1 taken along the lines 3--3 of FIG. 2; 
     FIG. 4 is a block diagram of the major elements of the camera of FIG. 2; 
     FIG. 5 is a simplified block diagram of a typical PC-compatible computer; 
     FIG. 6 is the pin-out diagram of the bus connector for a PC-compatible PC/XT bus; 
     FIG. 7 shows the pin-out diagram of the bus connections which together with FIG. 6 make up a PC-compatible PC/AT bus; 
     FIG. 8 is a more detailed diagram of the signal processor subsystem shown in FIG. 4; 
     FIG. 9 shows a second embodiment of the signal processor subsystem shown in FIG. 4; and 
     FIG. 10 is a flow diagram of the image capture process. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Since electronic still cameras and computers, including pen-based computers, are well known, the present description will be directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with the present invention. Elements not specifically shown or described may be selected from those known in the art. 
     Referring to FIG. 1, a camera module 2 is shown attached to a bus connector 3 of a portable computer 4, which provides image processing, storage, and display. (The bus connector 3 is shown in broken line to indicate that it is hidden from view due to its location between the module 2 and the computer 4.) The invention is not limited to a particular computer, although a preferred computer is a small, battery operated IBM compatible personal computer (PC). One type of computer which is especially suitable is a &#34;pen-based&#34; computer, which is a small, portable unit that uses a pen-type stylus 6, rather than a keyboard and/or a &#34;mouse&#34; input device, for controlling the computer and inputting data. Menus are selected and data is entered using the stylus 6 to point to selections displayed on a pressure sensitive LCD display 8. 
     Appropriate pen-based computers that could be adapted for use with the invention include the NCR System 3000 Model 3125 NotePad computer manufactured by the NCR Corporation, Dayton, Ohio or the GridPad SL computer manufactured by Grid, a division of Tandy Corporation, Fort Worth, Tex. Both of these computers are compatible with the PC/AT bus (sometimes called the Industry Standard Architecture). The PC/AT bus uses a compatible enhancement of the original PC bus, the PC/XT bus. The NCR 3125 uses a CPU compatible with the Intel 386 microprocessor family, while the GridPad uses a CPU compatible with the Intel 8086  microprocessor family. Since the vast majority of personal computers in use today are compatible with the IBM PC/AT design, it is advantageous to design the camera module to connect to PC/AT compatible computers. 
     The computer system includes optional &#34;pod&#34; attachments, which include electronics for specific applications. In FIG. 1, a rechargeable battery pack 10 constitutes one pod, while the camera module 2 constitutes a second pod. In such a system, the camera module 2 can be attached when needed for a particular application. The camera captures images and stores the images in the memory contained within the pen-based computer. When not needed, other pods may be attached, such as an RF transmitter pod (not shown) for allowing data to be transferred between the computer 4 and a central receiver (not shown). An exemplary imaging application is the automobile claims process, where there is a need to record data, including pictorial data, on vehicle damage in order to provide a repair estimate. In such an application, the computer 4 would store a set of claim forms, and the camera module 2 would be attached to the computer 4 to obtain still images which can immediately be incorporated into the forms, thereby creating &#34;smart forms&#34; including both images and the data needed for a particular application. 
     Referring to FIGS. 2 and 3, a front 12 of the camera module 2 includes a lens 14, which is covered with a flip-up flash 16 when not in use to protect the lens 14. A back 18 of the camera module includes an optical viewfinder 20, which slides out of (or alternatively, flips away from) a recess 20a on the back 18 of the camera. The slide-out design for the viewfinder 20 is advantageous because it takes up little room inside the camera module 2, and requires only a few optical elements. The camera module 2 also includes a capture switch 22 (i.e., a &#34;shutter button&#34;) for taking the picture. The camera module 2 further includes an electrical interface connector 24 designed to mate with the bus connector 3 on the computer 4, thereby directly attaching the camera module 2 to the PC-compatible bus of the computer 4. This permits control of the camera module 2 from the computer 4, and provides a high speed parallel interface for rapidly transferring image data into the computer 4. In practice, it is desirable to physically attach the camera module 2 to the computer 4. Depending on the design chosen, the interface connector 24 may be sufficiently sturdy to provide mechanical as well as electrical attachment. Preferably, however, the camera module 2 would be secured to the computer by means of screws 26 secured through the holes 26a to threaded holes (not shown) on the computer 4. 
     FIG. 4 shows the subsystems of the camera module 2. An optical system 28 includes the lens 14, a diaphragm 34, a shutter 36, and an infrared blocking filter 38. To keep the system inexpensive, the lens 14 is fixed focus, and a close-up diopter lens 40 is optionally moved into the optical axis for close-up pictures. Image light is directed by the optical system 28 upon an image sensor 42, which is a charge-coupled device (CCD) sensor, such as the full frame sensor KAF-400 manufactured by Eastman Kodak Company, Rochester, N.Y. The timing of the read-out of the image sensor 42 through its horizontal read-out register 42a is controlled by a CCD clock driver circuit 44. 
     The sub-systems of the camera 20 are controlled by a microprocessor 46. In particular, the exposure conditions of the image are input to the microprocessor 46 from a photometer 48 and shutter release is initiated by the capture switch 22. Accordingly, the microprocessor 46 instructs a pair of stepper drivers 50 to set the diaphragm 34 and to operate the shutter 36, and, as needed, to fire the flash 16. The microprocessor 46 further interfaces with a signal processor 52, which controls the read-out clocking of the image sensor 42 and processes the image signal generated by the image sensor 42. The signal processor 52 provides the processed image signals to the computer 4 via the bus-compatible electrical interface connector 24. 
     A simplified block diagram of the computer 4, in particular, a PC-compatible computer, is shown in FIG. 5. The key component of the computer is the central processing unit, or CPU, 54. In a pen-based computer, the CPU can be, for example, a low power 16 bit CHMOS microprocessor such as the Intel 80C86A, manufactured by Intel Corp, Santa Clara, Calif. Alternatively, other processors, including CPUs compatible with the Intel 8088 CPU, Intel 80C286 CPU, or Intel 80386 or 80486 CPU families could be used. The CPU 54 connects to a standardized, industry-compatible bus 58, which is a set of shared lines exchange of three types of digital signals: data signals, address signals, and control signals. When an 8086 or 8088 compatible processor is used, the bus is known as the PC/XT bus, which utilizes 54 signal lines and 8 power/ground lines, including eight bits of data and twenty bits of address. When an 80286, 80386, or 80486 family CPU is used as the CPU in a &#34;PC compatible&#34; computer, the bus 58 is known as the PC/AT bus or ISA (Industry Standard Architecture) bus. The PC/AT bus is an enhancement of the PC/XT bus. An additional connector carries an extra eight bits of data, four bits of address, and extra control lines. FIG. 6 shows the 62 pin connector used in the PC/XT bus. The AT bus uses both the connector shown in FIG. 6 and the connector shown in FIG. 7. The connector pin names for the PC/XT bus are described in table 1, as follows. 
     
                       TABLE 1______________________________________IBM PC/XT BUS SIGNALSSIGNAL NAME      PIN #        FUNCTION______________________________________SA0-SA19   A31-A12      address (A0-A15 for I/O)SD0-SD7    A9-A2        dataIOR        B14          I/O read strobeIOW        B13          I/O write strobeSMEMR      B12          memory read strobeSMEMW      B11          memory write strobeAEN        A11          address enableIRQ2-IRQ7  B4, B25-B21  interrupt requestRESET      B2           power-on resetDRQ1-DRQ3  B18, B6, B16 DMA requestDACK0-DACK3      B19, B17, B26,                   DMA acknowledge      B15BALE       B28          address latch enableCLK        B20          CPU clockI/O CH CK  A1           I/O errorI/O CH RDY A10          pull LOW for wait statesOSC        B30          oscillator (3 × CPU clk)T/C        B27          DMA terminal countOWS        B8           Zero wait stateGND        B1, B10, B31 signal &amp; power gnd+5 V DC    B3, B29      +5 V supply+12 V DC   B9           +12 V supply-5 V DC    B5           -5 V supply-12 V DC   B7           -12 V supply______________________________________ 
    
     These pins include power pins, which allow the plug-in board, and therefore the camera module 2, to be powered by the power supply (not shown) of the computer 4. The PC/AT connector, besides additional data and address lines, includes additional interrupt request, direct memory access (DMA) request, DMA acknowledge, and other special lines for 16-bit control. Note that these standard connectors are not available on the outside of the case enclosing the computer 4. Instead, the case must be opened to insert the connector 24, which may be elongated for this purpose, into an empty slot in the computer bus 58. 
     In some CPUs, for example, the Intel 8086 CPU, the data and address signals are typically time multiplexed on the same microprocessor pins, and control lines indicate whether the signals on these pins contains an address or data. The control lines are used to latch the data and address signals onto the separate address and data bus lines of the signal bus 58. The control lines carry a group of &#34;interrupt request&#34; signals, which are used by peripherals when they need attention from the CPU 54. The address lines include two different address spaces known as memory address space and I/O address space. The most significant bit (MSB) address lines are typically used only for memory address space. Therefore, these MSBs can be used to represent different commands, when addressing a device using I/O address space. 
     The PC-compatible bus 58 is connected to both programmable read only memory (PROM) 60 and random access memory (RAM) 62. The PROM 60 stores the BIOS (Basic Input/Output System) portion of the PC operating system software. The BIOS includes the bootstrap loader, which is executed when the computer is first powered on. The rest of the PC operating system is normally stored on a hard disk drive 64, which is connected to the bus 58 via a hard drive controller 66. The hard drive 64 is also used to store application programs and data, including the digital images captured by the camera module 2. Portions of the disk operating system (DOS), application programs, and data are typically downloaded to the RAM memory 62 before program execution. Since the access time of the RAM memory 62 is generally much less than the time required to access the hard drive 64, this decreases the program execution time. A direct memory access (DMA) controller 68 is typically used to rapidly move data between the hard drive 64 and the RAM memory 62. The DMA controller 68 transfers data between the memory address space and the I/O address space. The computer system further includes the LCD display 8, which is normally connected to a display RAM memory 72 that is loaded by the CPU 54 via the bus 58, and at least one general purpose user input device 74, such as a keyboard, mouse, or the pen stylus 6. The user input device 74 is connected to the bus 58 via a user input interface 76, which may include a separate microprocessor. 
     The computer 4 includes the PC-compatible bus connector 3, which is accessible from the outside of the computer case. By attaching the camera module 2 to the connector 3, the camera module 2 is able to access the PC-compatible bus 58 in order to transfer image data from the CCD imager 42 to the computer 4, and in general to allow the camera module 2 to be controlled using the general purpose user input 74. PC-compatible computers ordinarily include internal &#34;slots&#34; with a standard bus connection, to allow users to purchase plug-in boards having additional memory, modems, etc., in order to expand the capabilities of their computer. This interface provides what is known as the &#34;I/O bus?, or &#34;I/O channel&#34;, using the standard connectors shown in FIGS. 6 and 7. In order to connect the camera module 2 to such computers, the interface connector 124 may include a plug-in extender board for inserting into the bus connection &#34;slot&#34; on the computer 4. (Although not specifically shown, the &#34;slot&#34; would enclose the connector 3 shown in FIG. 1.) 
     In one embodiment of the invention utilizing the PC/AT bus, the camera includes a 62 pin card edge connector and a 36 pin card edge connector, providing the connections shown in FIGS. 6 and 7, while the computer includes the appropriate female connectors accessible from the exterior of the case, to allow the camera module 2 to attach to the computer 4. As shown earlier, the camera module 2 is attached to the computer 4 using the screws 26. When the computer 4 is used without the camera module 2, a plate (not shown) is screwed into the computer, to prevent the connector 3 from being abused. In other embodiments, other types of physical connectors can be used. Furthermore, the connectors 3 and 24 may have fewer than 98 pins, since some of the bus signals may not be required by the camera. 
     Details of one embodiment of the signal processor 52 (FIG. 4) are shown in FIG. 8. A logic circuit 80 (such as Model EPS464 or Model EPM7096, integrated circuits manufactured by Altera Corp., San Jose, Calif.) provides the timing signals to control the image sensor 42 and the various parts of the signal processor 52. In particular the logic circuit 80 provides the horizontal and vertical clocking signals H1,H2,V1,V2 to read an image signal from the sensor 42 and the timing signal RESET to initiate each pixel read-out period. The output of the sensor 42 is initially processed by an analog signal processor 82 incorporating, e.g., a gain stage and a correlated double sampling circuit, and converted to a digital signal by an analog-to-digital (A/D) converter 84. The digitized signal is then processed by an EPROM look-up table (LUT) 86 that stores the white balance and gamma correction curveshapes, and information about the camera. 
     The LUT 86 can also store a camera serial number, location of sensor defects, the structure of a color filter array used on the sensor 42, color matrix coefficients optimized for a particular image sensor, etc. Moreover, the LUT 86 may also store the computer program which is used (by the computer) to operate the camera and to process the images from the sensor color filter array to obtain a full resolution, color corrected image. Such data is programmed into a portion of the EPROM memory 86, which is not used to provide the white balance and gamma correction look-up tables, when the camera module 2 is manufactured. The data is downloaded from the EPROM memory 86 in the camera module to the RAM memory 62 in the computer. To download the information, a multiplexer 85 is used to allow the computer to address the EPROM address least significant bit (LSB) lines which are normally provided by the A/D converter 84, while the timing logic 80 provides MSB address values which contain the required data, instead of the MSB values which provide the white balance and gamma correction curveshape tables. 
     The digitized signal processed by the LUT 86 is then provided to two sets of octal latches, 88a, 88b, and 90a, 90b. Each octal latch stores one pixel value. While one set (88a, 88b or 90a, 90b) of latches is being loaded, the pixel values stored in the other set from the previous two pixels are read into the computer 4 through the 16-bit data lines D0-D15 on the bus-compatible connector 24. The camera module 2 is controlled by signals generated by the computer 4 and applied to the address lines, which are decoded in an address decoder 92, and to the control lines of the bus 58. 
     The operation of the image capture system of FIGS. 4, 5 and 8 proceeds as shown in the flow chart of FIG. 10, in particular for a direct memory access (DMA) mode of operation. The user begins by connecting the camera module 2 to the computer 4 via the connectors 3 and 24, and turns on the computer 4. This activates an application program. The user then opens a &#34;camera&#34; application program by using the general purpose user input 74 and selects capture parameters from a menu displayed on the LCD display 8. A typical application might utilize an electronic &#34;smart form&#34;, which requires data to be entered via the LCD display 8 and the stylus 6, and which also requires a picture. The capture parameters may include color (8, 16, or 24 bit) or monochrome (1 or 8 bit), full resolution or subsampled, and store direct to disk, compress before storing, or convert to a standard metric before storing. Therefore, depending on the capture parameters selected, the data is either stored directly from RAM 62 to the hard disk 64 (or other non-volatile computer memory), compressed before storage using conventional methods, or converted before storage to a full resolution color image. 
     To take the picture, the user flips up the flash 16 and slides down the viewfinder 20. This closes a hidden switch (not shown) which powers up the camera. The camera, using the photometer 48, measures the ambient light level and charges the flash 16 if the ambient light level is low. The user frames the image using the optical viewfinder 20, and depresses the capture button 22. This begins a sequence which actuates the diaphragm 34, opens the shutter 36, fires the flash 16 if required, and closes the shutter 36. One line of the image is then transferred from the vertical register of the CCD imager 42 to the horizontal readout register 42a. Next, the timing logic 80 generates a &#34;line-ready&#34; interrupt of the computer&#39;s CPU using a PC I/O bus interrupt line. 
     In response to the interrupt, the CPU 54 instructs the DMA controller 68 to begin transfer of one line of data from the camera module 2 over the bus 58 to the computer&#39;s RAM memory 62. The DMA transfer is controlled by the control line signals on the bus 58. The data is provided from the camera in groups of two 8 bit pixels at a time, to rapidly transfer the image from the CCD imager 42 to the computer RAM memory 62. At the end of each line of the image (768 pixels for the Kodak KAF-0400 sensor), the timing logic 80 transfers another image line into the horizontal readout register 42a and then generates another &#34;line-ready&#34; interrupt. 
     In a second embodiment of the signal processor 52 shown in FIG. 9, the camera supplies data using only 8 bits out of the 16 data bits available on the PC/AT connector. In addition, a DRAM buffer memory 94, capable of storing one entire image from the CCD imager 42, is inserted between the EPROM 86 and the interface connector 24 to substitute for the four octal latches in FIG. 8. This substitution lets the data transfer to the computer occur at any time following the image capture, without being synchronized to the sensor-readout. Such an unsynchronized transfer is useful in situations where the DMA transfer occurs at a slow enough rate that the &#34;dark current&#34; noise build-up in the sensor 42 would be too large. It is also useful in situations where the CPU 54 is performing many other tasks while reading out the image, so that if the DRAM memory 94 were not used, the CCD horizontal shift register clocking would need to be interrupted, which could lead to noise in the image. In addition, a status register 96 is used instead of interrupt lines, to provide a status signal to the CPU 54 when an image has been captured and is ready to be transferred. This status register 96 is a latch, controlled by the camera module timing logic 80, which is multiplexed onto the same data lines of the bus 58 as the image data. In addition, the address decoder 92 directly passes the 2 LSBs of the PC bus address directly to the timing logic 80. These two LSBs provide various commands to the timing logic. For example, the computer can instruct the camera module to turn on the flash or to take a picture. 
     The invention has been described in detail with particular reference to a presently preferred embodiment, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention. For example, the picture-taking sequence could be initiated from the user input device 74 that is part of the computer 4, and the camera module 2 would then not require any user input device, such as the capture button 22. Moreover, the camera module 2 could be an integral part of the computer 4, i.e., the computer 4 would inherently include the capability of being a camera as well as a computer. In that case, the elements of the camera shown in FIG. 4, and the signal processor 52 shown further in FIGS. 8 and 9, would be additional parts of the PC-compatible computer shown in FIG. 5. The principal difference would be that the PC bus-compatible connectors 3 and 24 would be replaced by a direct connection of the signal processor 52 to the signal bus 58.