Abstract:
A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (SRAM) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to an interface circuitry of a memory cell. The present disclosure is particularly applicable to access gates of a static random access memory (SRAM) cell circuit. 
       BACKGROUND 
       [0002]    Generally, an electronic circuit of a memory cell may be associated with various interface elements and signals that provide access to the memory cell. For example, a processor in a computer may utilize the interface circuitry to read data that is stored in an SRAM memory cell or to write/store data in the SRAM memory cell. 
         [0003]      FIG. 1  schematically illustrates a traditional SRAM cell circuitry  100  utilized in an integrated circuit (IC) design. The SRAM memory cell includes interface circuitry for accessing the memory cell in order to read data stored therein or to write data in the memory cell. For example, the memory cell  100  includes a first access gate having a first transistor  101  and a second access gate having a second transistor  103  that provide access to memory cell inverter circuit  105 , which can store data (e.g., zeroes and ones.) Additionally, one or more interface signals on word-line (WL)  107 , a first bit-line (BL)  109 , and a second BL (BLX)  111  may be utilized to access the memory cell inverter circuit  105 , wherein various combinations of the interface signals can provide for various interactions/operations at the memory cell. For example, with the WL signal and pre-charged BL and BLX at a high voltage state (e.g., at logic 1), an operation of reading the memory cell content can be initiated. However, with technological advances in reduced IC node designs (e.g., scaling, smaller transistors) and lower supply voltages, the access gate transistors in a conventional SRAM design may be unable to function reliably or consistently. For instance, lower levels of supply voltage and current (i.e., ampere=I) at an SRAM cell can cause a failure of one or more functions/operations (e.g., read, write, retention, etc.) at the cell. A known approach to improve write ability is to include a write assist circuit. However write assist circuits take additional area on the chip. 
         [0004]    A need therefore exists for methodology and circuitry enabling additional current for access gates in a memory cell without increasing supply voltage or sacrificing SRAM array area. 
       SUMMARY 
       [0005]    An aspect of the present disclosure is a circuit to provide additional current for access gates in a memory cell without a higher supply voltage, assist circuits, or additional time consumption. 
         [0006]    Another aspect of the present disclosure is a method for implementing a circuit to provide additional current for access gates in a memory cell without a higher supply voltage, assist circuits, or additional time consumption. 
         [0007]    Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims. 
         [0008]    According to the present disclosure, some technical effects may be achieved in part by a circuit including: a six transistor SRAM cell that includes a first inverter cross-coupled to a second inverter, a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, and a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor. Some aspects further include a circuit where the first transistor and the second transistor include passgate n-type metal-oxide-semiconductor (NMOS) field-effect transistors (FETs). 
         [0009]    Further aspects include the plurality of bit-line sensing transistors having a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate; a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line; a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; and a sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line. Other aspects include a circuit where each of the third transistor and the fifth transistor includes a write p-type metal-oxide-semiconductor (PMOS) transistor. Another aspect includes a circuit where each of the fourth transistor and the sixth transistor includes a write NMOS transistor. An additional aspect includes a circuit where the third transistor is in an active state when the first drain, the second bit-line, and the word-line are at a high voltage state, and the first bit-line is at a low voltage state. 
         [0010]    Other aspects include the first inverter having a seventh transistor having a seventh source, a seventh drain, and a seventh gate, and an eighth transistor having an eighth source, an eighth drain, and an eighth gate; and the second inverter including a ninth transistor having a ninth source, a ninth drain, and a ninth gate, and a tenth transistor having a tenth source, a tenth drain, and a tenth gate, wherein the seventh source and the ninth source are coupled to a power rail, wherein the eighth source and the tenth source are coupled to a ground rail, wherein the seventh drain, the eighth drain, the ninth gate, and the tenth gate are coupled to the first drain, and wherein the ninth drain, the tenth drain, the seventh gate, and the eighth gate are coupled to the second source. 
         [0011]    In another aspect the third transistor in the active state sources a higher current level during a write operation when compared to one or more other current levels sourced during one or more other operations at the SRAM cell. 
         [0012]    An additional aspect of the present disclosure is a method including: providing a six transistor SRAM cell including providing a first inverter cross-coupled to a second inverter, providing a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line, and providing a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and providing a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor. In one aspect the first transistor and the second transistor include passgate NMOS transistors. 
         [0013]    Another aspect of the present disclosure for providing the plurality of bit-line sensing transistors includes providing a third transistor having a third source coupled to the first source, a third drain coupled to the first drain, and a third gate; providing a fourth transistor having a fourth drain coupled to the third gate, a fourth source coupled to the first bit-line, and a fourth gate coupled to the word-line; providing a fifth transistor having a fifth source coupled to the second source, a fifth drain coupled to the second drain, and a fifth gate; and providing a sixth transistor having a sixth source coupled to the second bit-line, a sixth drain coupled to the fifth gate, and a sixth gate coupled to the word-line. In an additional aspect of the present disclosure each of the third transistor and the fifth transistor includes a write PMOS transistor. In one aspect of the present disclosure each of the fourth transistor and the sixth transistor includes a write NMOS transistor. In a further aspect of the present disclosure the third transistor is in an active state when the first drain, the second bit-line, and the word-line are at a high voltage state, and the first bit-line is at a low voltage state. 
         [0014]    In some aspects of the present disclosure the method includes providing for the first inverter a seventh transistor having a seventh source, a seventh drain, and a seventh gate, and an eighth transistor having an eighth source, an eighth drain, and an eighth gate; providing for the second inverter a ninth transistor having a ninth source, a ninth drain, and a ninth gate, and a tenth transistor having a tenth source, a tenth drain, and a tenth gate; coupling the seventh source and the ninth source to a power rail; coupling the eighth source and the tenth source to a ground rail; coupling the seventh drain, the eighth drain, the ninth gate, and the tenth gate to the first drain; and coupling the ninth drain, the tenth drain, the seventh gate, and the eighth gate to the second source. 
         [0015]    Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which: 
           [0017]      FIG. 1  schematically illustrates a traditional memory cell circuit utilized in an SRAM design; 
           [0018]      FIG. 2  schematically illustrates an SRAM cell design including circuitry to provide additional current to one or more access gates, in accordance with an exemplary embodiment; and 
           [0019]      FIG. 3  illustrates a table of example combinations of access signals and related operations at an SRAM cell, in accordance with an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.” 
         [0021]    The present disclosure addresses and solves the problems of low supply current available to access gates of an SRAM memory cell and/or additional area requirements for a write assist circuit attendant upon reducing bitcell size for an SRAM memory cell. The present disclosure addresses and solves such problems, for instance, by, inter alia, providing more current to the access gates by utilizing additional transistors that can provide the additional current once some of the control signals of the memory cell are activated. 
         [0022]      FIG. 2  schematically illustrates an SRAM cell design including circuitry to provide additional current to one or more access gates, in accordance with an exemplary embodiment.  FIG. 2  schematically illustrates circuit  200  including the first access gate having the first transistor  101 , the second access gate having the second transistor  103 , the memory cell inverter circuit  105 , the WL  107 , the BL  109 , and the BLX  111 , as in a traditional SRAM cell design. However, the first access gate additionally includes two supplemental transistors, a third transistor  201  and a fourth transistor  203 , and the second access gate also includes two supplemental transistors, a fifth transistor  205  and a sixth transistor  207 . The memory cell inverter circuit  105  includes two inverters, each with two transistors, as in the traditional SRAM cell. Specifically, the first inverter includes a seventh transistor  209  and an eight transistor  211 , and the second inverter includes a ninth transistor  213  and a tenth transistor  215 . 
         [0023]    The first transistor  101  has a source  1 S coupled to the BL  109 , a drain  1 D coupled to the first inverter, and a gate  1 G coupled to the WL  107 . The second transistor  103  has a source  2 S coupled to the second inverter, a drain  2 D coupled to the BLX  111 , and a gate  2 G coupled to the WL  107 . The third transistor  201  has a source  3 S and a drain  3 D, coupled to the source  1 S and drain  1 D, respectively, of the first transistor, and a gate  3 G. The fourth transistor  203  has a drain  4 D coupled to the gate  3 G, a source  4 S coupled to the BL  109 , and a gate  4 G coupled to the WL  107 . Similar to the third transistor  201 , the fifth transistor  205  has a source  5 S and a drain  5 D, coupled to the source  2 S and drain  2 D, respectively, of the second transistor, and a gate  5 G. The sixth transistor  207  has a source  6 S coupled to the BLX  111 , a drain  6 D coupled to the gate  5 G, and a gate  6 G coupled to the WL  107 . 
         [0024]    Regarding the inverter circuit  105 , the source  7 S of transistor  209  and the source  9 S of transistor  213  are coupled to a power rail  217 , whereas the source  8 S of the transistor  211  and the source  10 S of the transistor  215  are coupled to a ground rail  219 . The drains  7 D and  8 D of transistors  209  and  211  and gates  9 G and  10 G of transistors  213  and  215  are coupled to the drain  1 D; and the drains  9 D and  10 D of transistors  213  and  215 , gate  7 G of transistor  209 , and the gate  8 G of transistor  211  are coupled to the source  2 S. 
         [0025]    Each of the third transistor  201  and the fifth transistor  205  include a PMOS transistor. Further, each of the fourth transistor  203  and the sixth transistor  207  may include an NMOS transistor. The third transistor may be in an active state when the drain  1 D, the BLX  111 , and the WL  107  are at a high voltage state, and the BL  109  is at a low voltage state. 
         [0026]    Advantages of the design of  FIG. 2  include improved write current levels for a more reliable write operation at the SRAM memory cell and without a need for a higher supply voltage (e.g., no change required to previous design), which could provide for a better yield of memory cells when considering a minimum voltage (Vmin) parameter at an IC. Further, no write assist circuit is required. 
         [0027]      FIG. 3  illustrates a table  300  of example combinations of access signals and related operations at an SRAM cell. In the table  300 , during a “read” operation  301 , when signals on the WL  107 , BL  109 , and BLX  111  are at a high voltage state, then the first transistor  101 , the second transistor  103 , the fourth transistor  203 , and the sixth transistor  207  are in active states while the third transistor  201  and the fifth transistor  205  are in an inactive state, which would result in no increase in the “read” mode current. Further, during a “write” operation  303 , when signals on the WL  107  and the BLX  111  are at a high voltage state, and the BL  109  is at a low voltage state, then the first transistor  101 , the second transistor  103 , the third transistor  201 , the fourth transistor  203 , and the sixth transistor  207  are in active states while the fifth transistor  205  is in an inactive state, which would result an increase in the “write” mode current. Furthermore, during a “disturb” operation  305  (e.g., half selected cell for a read operation after a write operation), when signals on the WL  107 , BL  109 , and BLX  111  are at a high voltage state, then the first transistor  101 , the second transistor  103 , the fourth transistor  203 , and the sixth transistor  207  are in active states while the third transistor  201  and the fifth transistor  205  are in inactive states, which would result in no degradation of the disturb margin. 
         [0028]    The embodiments of the present disclosure can achieve several technical effects, including improved current levels during a write operation at an SRAM memory cell in an IC device without sacrificing space for a write assist circuit. Further, the embodiments enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, digital cameras, or other devices utilizing logic or high-voltage technology nodes. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, including devices that use SRAM memory cells (e.g., liquid crystal display (LCD) drivers, synchronous random access memories (SRAM), digital processors, etc.) 
         [0029]    In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.