Abstract:
A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a regulator system with automatically switching pulse skipping mode, and more particularly relates to a pulse width modulation regulator system with automatically switching pulse skipping mode.  
         [0003]     2. Description of the Prior Art  
         [0004]     In the switching mode regulator, the pulse width modulation (PWM) is extensively used in the method of voltage transformation. When the circuit is needed to provide voltage during the heavy load, the inductor current of the circuit is maintained in the Continuous Conduction Mode (CCM). And the switching speed of PWM is high enough to provide higher power density for heavy load. However, when the circuit is only needed to provide voltage during light load, the inductor current of the circuit is maintained in the Discontinuous Conduction Mode (DCM). And the switching speed of PWM is low enough to provide lower power density for light load.  
         [0005]     In the prior art, the PWM regulator is only needed to provide low voltage for light load. In order to reduce the power switching loss, the solution of the prior art is to use pulse skipping mode (PSM) to reduce the number of times to turn on or off the switch in the circuit and achieve the power saving. The PWM regulator with PSM in the prior art, when the circuit is operated in the Continuous Conduction Mode, the output voltage will come with bigger pulse because of the PSM and the phase is not stable.  
         [0006]     The traditional asynchronous step-down converter with PSM is shown in  FIG. 1 . The circuit comprises an error amplifier  100 , a comparator  103 , a ramp generator  106 , a pulse generator with minimum-on-time  109 , an OR gate  112 , an activator  115 , a switch SW 1 , a diode D 1 , an inductor L 1  and a capacitance C 1 . In the traditional circuit of  FIG. 1 , the circuit is added a pulse generator  109  with minimum-on-time to have the pulse skipping mode and save the power. And the inductor current of the circuit can be in the Continuous Conduction Mode (CCM) or the Discontinuous Conduction Mode (DCM). Because the Continuous Conduction Mode (CCM) is not exited in the traditional circuit and the circuit will be adaptively turned off the pulse skipping mode, the switching ratio of the input voltage and the output voltage is very high in the circuit. And the output voltage will be big because of the PSM and the phase will be not stable.  
         [0007]      FIG. 2  is a traditional Asynchronous step-up converter with pulse skipping mode (PSM). The circuit comprises an error amplifier  200 , a comparator  203 , a ramp generator  206 , a pulse generator  209  with minimum-on-time, an OR gate  212 , an activator  215 , a switch SW 2 , a diode D 2 , an inductor L 2 , and a capacitance C 2 . In the traditional circuit of  FIG. 2 , the circuit is also added a pulse generator  209  with minimum-on-time in order to have the PSM and save the power. And the inductor current of the circuit can be Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM). Because the Continuous Conduction Mode (CCM) is not exited in the traditional circuit and the circuit will be adaptively turned off the pulse skipping mode, the switching ratio of the input voltage and the output voltage is very high in the circuit. And the pulse of the output voltage will be big because of the PSM and the phase will be not stable.  
         [0008]     Because of the reason described above, the circuit can be operated in Discontinuous Conduction Mode (DCM) to save the power because of the pulse skipping mode (PSM). However, when the circuit is operated in the Continuous Conduction Mode (CCM), the pulse of the output voltage is too big and the phase is not stable. It is necessary to provide a method or system with an operative mode to enable or disable the pulse skipping mode.  
       SUMMARY OF THE INVENTION  
       [0009]     According to the prior art described above, there are many drawbacks in the traditional pulse width modulation (PWM) regulator system with pulse skipping mode (PSM). The purpose of the present invention is to provide a pulse width modulation (PWM) regulator system with automatically switching the pulse skipping mode (PSM). The circuit can be adaptively enable or disable the pulse skipping mode (PSM) according to the operative mode of the circuit.  
         [0010]     The other purpose of the present invention is to provide a pulse width modulation regulator system with automatically switching the pulse skipping mode to reduce the pulse of the output voltage, to steady the phase of the output voltage and to remove the inductor current accumulated when the circuit is operated in the Continuous Conduction Mode.  
         [0011]     According to the purposes described above, a pulse width modulation regulator system with automatically switching PSM is provided herein. The circuit comprises a pulse width modulation regulator (such as synchronous step-down converter, asynchronous step-down converter, synchronous step-up converter, or asynchronous step-up converter), which is used to convert the input voltage to output voltage by the pulse width modulation. A pulse skipping mode switch module is used to detect the inductor current of the converter and decide to turn on or turn off the pulse skipping mode. When the pulse skipping mode switch module decides to turn on the pulse skipping mode, the pulse generator generates a pulse signal to let the converter work in the pulse skipping mode. However, when the pulse skipping mode switch module decides to turn off the pulse skipping mode, the pulse generator stops to generate the pulse signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0013]      FIG. 1  is a traditional pulse width modulation (PWM) asynchronous step-up converter with pulse skipping mode (PSM).  
         [0014]      FIG. 2  is a traditional pulse width modulation (PWM) asynchronous step-down converter with pulse skipping mode (PSM).  
         [0015]      FIG. 3  is a traditional pulse width modulation (PWM) synchronous step-down converter with pulse skipping mode (PSM) in a preferred embodiment of the present invention.  
         [0016]      FIG. 4  is a pulse width modulation (PWM) asynchronous step-down converter with pulse skipping mode (PSM) in a preferred embodiment of the present invention.  
         [0017]      FIG. 5  is a pulse width modulation (PWM) synchronous step-up converter with pulse skipping mode (PSM) in a preferred embodiment of the present invention.  
         [0018]      FIG. 6  is a pulse width modulation (PWM) asynchronous step-up converter with pulse skipping mode (PSM) in a preferred embodiment of the present invention.  
         [0019]      FIG. 7  is a pulse skipping mode (PSM) switch module in a preferred embodiment of the present invention.  
         [0020]      FIG. 8  is an oscillogram of the end point according to  FIG. 3 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0021]     The detailed description of the present invention will be discussed in the following embodiments, which are not intended to limit the scope of the present invention, but can be adapted for other applications. While drawings are illustrated in details, it is appreciated that the quantity of the disclosed components may be greater or less than that disclosed, except expressly restricting the amount of the components.  
         [0022]     A pulse width modulation (PWM) regulator system with automatically switching pulse skipping mode (PSM) is disclosed in the present invention. The pulse width modulation (PWM) regulator system comprises a synchronous step-up converter, an asynchronous step-up converter, a synchronous step-down converter, and an asynchronous step-down converter. In addition, The pulse width modulation (PWM) regulator system can enable or disable the pulse skipping mode (PSM) as the operative mode is Continuous Conduction Mode (CCM) or Discontinuous Conduction Mode (DCM).  
         [0023]      FIG. 3  is an embodiment of the present invention. A synchronous step-down converter with automatically switching pulse skipping mode (PSM) comprises an error amplifier  300 , a pulse width modulation generator  303 , an OR gate  306 , a pulse generator  309 , an AND gate  312 , a SR latch  315 , a continuous conduction mode detector  318 , SR latch  321 , a zero current detector  324 , a NOR gate  327 , a switch SW 3 , a switch SW 4 , an inductor L 3 , a capacitance C 3 , a resistance R 1 , and a resistance R 2 .  
         [0024]     The negative input of the error amplifier  300  in the  FIG. 3  is received a feedback signal from the output divided voltage signal. And the positive input is received a reference voltage (Vref). After comparing these two signals, the error amplifier outputs an error signal to the PWM generator  303 . The outputs of the PWM generator  303  are connected to the input of the OR gate  306 , the input of the AND gate  312 , one of the inputs of the Continuous Conduction Mode (CCM) detector  318 , and the R end of the SR latch  321 . The other output of the OR gate is connected to the output of the pulse generator  309 . And the output of the OR gate  306  is connected to the one of the inputs of the NOR gate  327  and the switch SW 3 .  
         [0025]     The other input of the NOR gate  327  is connected to the Q end of the SR latch  321  and one input of the Continuous Conduction Mode (CCM) detector  318 . The output of the NOR gate  327  is connected to the switch SW 4 . The two ends of the switch SW 4  are respectively connected to two inputs of the zero detector  324 . The output of the zero detector  324  is connected to the S end of the SR latch  321  and the SR latch  315 . The R end of the SR latch  315  is connected to the output of the Continuous Conduction Mode detector  318 . And the Q end of the SR latch  315  is connected to the other input of the AND gate  312 .  
         [0026]     Still referring to  FIG. 3 , one end of the switch SW 3  is connected to the input voltage Vin and the other end of which is connected to the switch SW 4 . The other end of the switch SW 4  is connected to the ground. An inductor L 3  is connected between two switches SW 3  and SW 4 . And the other end of the inductor L 3  is connected to a capacitance C 3  and a resistance R 1 . The voltage of the resistance R 1  is the output voltage Vout. In addition, the other end of the capacitance C 3  is connected to the ground and the other end of the resistance R 1  is connected to the resistance R 2 . And the other end of the resistance R 2  is connected to the ground.  
         [0027]     In the embodiment of  FIG. 3 , the switches SW 3  and SW 4  are in the continuous mode. When one of the switches is conductive, the other one is not. The input voltage Vin provides the voltage for the output, when two switches SW 3  and SW 4  save the power at the inductor L 3  and the capacitance C 3 . The output voltage will be divided by the resistance R 1  and the resistance R 2  to provide a feedback voltage for the error amplifier  300 . The error amplifier  300  output the error signal, which is compared by the feedback voltage and the reference voltage, to the PWM generator  303 . At the moment, the zero current detector  324  detects whether the inductor current of the circuit is zero and outputs a control signal to the SR latch  321  and the SR latch  315 .  
         [0028]     According to the control signal of the zero current detector and the signal of the PWM generator  303 , the SR latch  321  is able to control the NOR gate  327 . The Continuous Conduction Mode (CCM) detector  318  detects the circuit is in the CCM or Discontinuous Conduction Mode (DCM) by the output signal of the SR latch  321  and the signal of the PWM generator  303 . The SR latch  315  outputs a signal to control the AND gate  312  by the control signal of the zero current detector  324  and the output signal of the CCM detector  318 . The AND gate decides to enable or disable the pulse generator  309  by the signal of the PWM generator  303  and the signal of the SR latch  315 . If the pulse generator  309  were enabled, the circuit was in the discontinuous conduction mode. On the other hand, if the pulse generator  309  were disabled, the circuit was in the continuous conduction mode. And because the PSM is disabled, the pulse of the output voltage is smaller and the phase is stable.  
         [0029]     Now referring to  FIG. 4 , this embodiment of the present invention illustrates an asynchronous step-down converter with automatically switching PSM. The converter comprises an error amplifier  400 , a PWM generator  403 , an OR gate  406 , a pulse generator  409 , an AND gate  412 , a SR latch  415 , a CCM detector  418 , a rising edge detector  421 , a switch SW 5 , a diode D 3 , an inductor L 4 , a capacitor C 4 , a resistance R 3 , and a resistance R 4 .  
         [0030]     The negative input of the error amplifier  400  in  FIG. 4  is received a feedback voltage from the output divided voltage signal. The positive input of the error amplifier  400  is received a reference voltage Vref. According to signals of the feedback voltage and the reference voltage, the error amplifier  400  outputs an error signal to the PWM generator  403 . The output of the PWM generator  403  is connected to the input of the OR gate  406 , the input of the AND gate  412 , the input of the CCM detector  418  and one input of the rising edge detector  421 . The other input of the OR gate  406  is connected to the output of the pulse generator  409 . And the output of the OR gate  406  is connected to the switch SW 5 .  
         [0031]     One end of the switch SW 5  is connected to the input voltage Vin and the other end is connected to the diode D 3 . And the other end of the diode D 3  is connected to the ground. An inductor L 4  is connected between the switch SW 5  and the diode D 3 . And the one end of the rising edge detector  421  is connected between the diode D 3  and the inductor L 4 . The other end of the inductor L 4  is connected to the capacitance C 4  and the resistance R 3 . In addition, the voltage between the capacitance C 4  and the resistance R 3  is the output voltage Vout. The other end of the capacitance C 4  is connected to the ground. One end of the resistance R 3  is connected to the resistance R 4  and the other end is connected to the ground. The output of the rising edge detector  421  is connected to the S end of the SR latch  415  and the other input of the CCM detector  418 . The output of the CCM detector  418  is connected to the R end of the SR latch  415  and the Q end of the SR latch  415  is connected to the other input of the AND gate  412 . The output of the AND gate  412  is connected to the input of the pulse generator  409 .  
         [0032]      FIG. 4  is another embodiment of the present invention. The input voltage Vin provides the output voltage, when the switch SW 5  is operated to save and release the power in the inductor L 4  and the capacitance C 4 . The output voltage is divided by the resistance R 3  and the resistance R 4  to provide a feedback voltage for the error amplifier  400 . The error amplifier  400  outputs an error signal, which is obtained by comparing the feedback voltage and the reference voltage, for the PWM generator  403 . At the moment, the rising edge detector  421  detects whether the rising edge pulse is existed between the ends of the switch SW 5  and the diode D 3 . The rising edge detector  421  outputs a control signal to the CCM detector  418  and the S end of the SR latch  415  according to the rising edge pulse and the signal of the PWM generator  403 .  
         [0033]     According to the output signal of the CCM detector  418  and the signal of the PWM generator  403 , the CCM detector  418  detects whether the circuit is in the CCM or the DCM. The SR latch  415  outputs a signal to control the AND gate  412  according to the control signal of the rising edge detector  421  and the output signal of the CCM detector  418 . The AND gate  412  decides to enable or disable the pulse generator  409  by the output signal of the PWM generator  403  and the Q end of the SR latch  415 . If the pulse generator were enabled, the circuit was in the DCM and saved the power. If the pulse generator were disabled, the circuit was in the CCM and the pulse of the output voltage is small and the phase is stable.  
         [0034]     The synchronous step-up converter with automatically switching PSM is shown in one embodiment of the present invention of  FIG. 5 . The converter comprises an error amplifier  500 , a PWM generator  503 , an OR gate  503 , a pulse generator  509 , an AND gate  512 , a SR latch  515 , a CCM detector  518 , a SR latch  521 , a zero current detector  524 , a NOR gate  527 , a switch SW 6 , a switch SW 7 , an inductor L 5 , a capacitor C 5 , a resistance R 5 , and a resistance R 6 .  
         [0035]     The negative input of the error amplifier  500  is received a feedback signal from the divided input voltage in  FIG. 5 . The positive input of the error amplifier  500  is received a reference voltage Vref. And after comparing the feedback signal and the reference voltage Vref, the error amplifier  500  outputs an error signal to the PWM generator  503 . The output of the PWM generator  503  is connected to the input of the OR gate  506 , the input of the AND gate  512 , the input of the CCM detector  518 , and the R end of the SR latch  521 . The other input of the OR gate  506  is connected to the output of the pulse generator  509 . The output of the OR gate  506  is connected to the input of the NOR gate  527  and the switch SW 6 .  
         [0036]     The other input of the NOR gate  527  is connected to the Q end of the SR latch  521  and the other input of the CCM detector  518 . The output of the NOR gate  527  is connected to the switch SW 7 . The two ends of the switch SW 7  are respectively connected to the two inputs of the zero current detector  524 . The output of the zero current detector  524  is connected to the S end of the SR latch  521  and the S end of the SR latch  515 . The R end of the SR latch  515  is connected to the output of the CCM detector  518 . The Q end of the SR latch  515  is connected to the other input of the AND gate  512 .  
         [0037]     The one end of the inductor L 5  is connected to the input voltage Vin, and the other end is connected to the switch SW 6 . The other end of the switch SW 6  is connected to the ground. The switch SW 7  is connected between the inductor L 5  and the switch SW 6 . The other end of the switch SW 7  is connected to the capacitor C 5  and the resistance R 5 . The voltage between the capacitor C 5  and the resistance R 5  is the output voltage Vout. The other end of the capacitor C 5  is connected to the ground. The other end of the resistance R 5  is connected to the resistance R 6 . And the other end of the resistance R 6  is connected to the ground. The operation of the circuit in this embodiment can automatically detect whether the circuit is in the CCM or the DCM is the same as the embodiment in  FIG. 3 . It is not necessary to describe again. The purpose of this embodiment is to provide a structure in the synchronous step-up converter to have the automatically switching pulse skipping mode.  
         [0038]     The asynchronous step-up converter with automatically switching is shown in one embodiment of the present invention of  FIG. 6 . The converter comprises an error amplifier  600 , a PWM generator  603 , an OR gate  606 , a pulse generator  609 , an AND gate  612 , a SR latch  615 , a CCM detector  618 , a falling edge detector  621 , a switch SW 8 , a diode D 4 , an inductor L 6 , a capacitor C 6 , a resistance R 7  and a resistance R 8 .  
         [0039]     The negative input of the error amplifier  600  in  FIG. 6  is received a feedback signal from the input divided voltage. The positive input of the error amplifier  600  is received a reference voltage Vref. After comparing the feedback signal and the reference voltage Vref, the error amplifier  600  outputs an error signal to the PWM generator  603 . The output of the PWM generator  603  is connected to the input of the OR gate  606 , the input of the AND gate  612 , and the input of the CCM detector  618 . The other input of the OR gate  606  is connected to the output of the pulse generator  609 . The output of the OR gate  606  is connected to the switch SW 8 .  
         [0040]     The one end of the inductor L 6  is connected to the input voltage Vin, and the other end is connected to the diode D 4  and the switch SW 8 . And the other end of the switch SW 8  is connected to the ground. The diode D 4  is connected between the switch SW 8  and the inductor L 6  and also connected to the other input of the falling edge detector  621 . The other end of the diode D 4  is connected to the capacitor C 6  and the resistance R 7 . In addition, the voltage between the capacitor C 6  and the resistance R 7  is the output voltage Vout. The other end of the capacitor C 6  is connected to the ground and the other end of the resistance R 7  is also connected to the ground. The output of the falling edge detector  621  is connected to the S end of the SR latch  615  and the other input of the CCM detector  618 . And the output of the PWM detector  618  is connected to the R end of the SR latch  615 . The Q end of the SR latch  615  is connected to the other input of the AND gate  612 . And the output of the AND gate  612  is connected to the input of the pulse generator  609  and the other input of the falling edge detector  621 . The operation of the circuit in this embodiment can automatically detect whether the circuit is in the CCM or the DCM is the same as the embodiment in  FIG. 4 . It is not necessary to describe again. The purpose of this embodiment is to provide a structure in the asynchronous step-up converter to have the automatically switching pulse skipping mode.  
         [0041]     The circuit of the pulse skipping mode switch module is disclosed in the embodiment of  FIG. 7 . The module is applied to adaptively enable or disable the pulse generator in the embodiments of  FIG. 3  and  FIG. 5  and achieve the goal of enabling or disabling the PSM in the circuit. In this circuit, the zero current detector  700  outputs a signal to the S end of the SR latch  706  to know if the current in the inductor current of the circuit is zero or not. The Q end of the SR latch  706  will convert the signal according to the signal of the S end and the R end of the SR latch  706 , and then output it to the input of the CCM detector  721 . The other input of the CCM detector  721  is received the signal from the PWM generator  703 . After the CCM detector  703  comparing the signal from two inputs, the CCM detector  703  outputs a signal to know if the circuit is in the CCM and the signal is transferred to the R end of the SR latch  724 . The Q end of the SR latch  724  outputs a signal to the input of the AND gate  727  according to the S end&#39;s signal, which is received from the zero current detector  700  and the signal of R end. The AND gate  727  outputs a control signal to enable or disable the pulse generator (not shown) according to the signal of the Q end of the SR latch  724  and the signal from the pulse width modulation generator  703 .  
         [0042]     The CCM detector  721  comprises a falling edge detector  709 , an inverter  712 , a SR latch  715 , and a AND gate  718 . The falling edge detector  709  detects if the signal, which is received from the Q end of the SR latch  706 , has pulse falling edge and transfers the signal to the S end of the SR latch  715 . The inverter  712  inverts the signal of the PWM generator  703  and transfers the signal to the R end of the SR latch  715 . According to the signal of the S end and the R end of the SR latch  715 , the Q end of the SR latch  715  outputs a signal to the input of the OR gate  718 . The AND gate  718  outputs a control signal to the R end of the SR latch  724  according to the signal of the PWM generator  703  and the signal in the Q end of the latch  715  and knows if the circuit is operated in the CCM.  
         [0043]      FIG. 8  is an oscillogragh illustrating how the signal in each end of the circuit to control the converter of  FIG. 3  in the embodiment of the present invention. There are three steps, from left to right, showing in the inductor current of  FIG. 8  according to the CCM or DCM. The circuit is in the CCM because the lowest value of the inductor current is not zero. Therefore, the output of the zero current detector  324  is the zero current detective pulse. Before the period of t 1 , there is no pulse generated. The second step is in the CCM because the inductor current is zero during the time between t 1  and t 2 . The zero current detector  324  outputs a zero current detective pulse. At this time, there is a pulse signal generated and the front edge of the signal is in the AND gate  312 . The pulse generator activates the signal from low logic voltage to high logic voltage. The time after t 3  is the third step, the inductor current is not zero and the circuit is operated in the CCM. The zero current detector  324  outputs a zero current detective pulse. There is no pulse signal generated after t 3 , the pulse generator activates the signal from high logic voltage to low logic voltage.  
         [0044]     During the time between t 1  and t 2 , the pulse generator activates the signal in high logic voltage; the pulse front edge generated by the PWM generator  303  will activate the pulse generator  309  and output a working period signal of the pulse generator with a specific working period. The working period signal of the pulse generator let the circuit be in the pulse skipping mode. The period after the t 3 , the working period signal of the pulse generator is in the low logic voltage and the circuit will automatically disable the PSM.  
         [0045]     Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.