Abstract:
A semiconductor structure includes: a substrate with at least a trench therein, wherein the trench is filled with an insulation layer; a first polysilicon layer disposed on the insulation layer and covering at least two opposite borders of a top surface of the insulation layer; a second polysilicon layer disposed above the first polysilicon layer and the substrate; and a dielectric layer disposed between the first and second polysilicon layers, wherein the first and second polysilicon layers are respectively shaped as first and second strips.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of U.S. application Ser. No. 12/058,183, filed Mar. 28, 2008, and incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a semiconductor manufacturing process. More particularly, the present invention relates to a method of forming a shallow trench isolation structure and the structure thereof. 
     2. Description of the Prior Art 
     Shallow trench isolation (STI) technique has been developed to avoid a bird&#39;s beak encroachment of a local oxidation of silicon (LOCOS) technique. The shallow trench isolation structure has been widely used to provide effective isolation for fabricating semiconductor devices with sub-micron or less critical dimension. 
     For a conventional STI process, a pad oxide layer is formed on a substrate and then a silicon nitride layer is formed on the pad oxide layer. After forming a patterned photoresist layer to define the STI region, the silicon nitride layer, the pad oxide layer and the substrate are sequentially etched to form trenches in the substrate. A silicon oxide layer is deposited over the substrate to fill the trench and followed by a planarization process to form STI structures. 
     However, divots or oxide loss can easily occur near the top corners of the STI structure during the subsequent etching and cleaning process steps. Charges may accumulate at the divot and result in a sub-threshold leakage current of the device in the integrated circuits. The divot or oxide loss problem becomes more serious for an embedded memory process such as embedded flash (e-flash) process due to extra etching and cleaning process steps compared to a typical logic process. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention provides a method of forming a STI structure that can avoid the generation of the divot or oxide loss near the top corner of the trench. According to the method of this invention, the top corner of the trench is protected during the subsequent etching and cleaning process steps so that the formation of the divot is avoided. 
     The present invention also provides a method of forming an isolation structure and the isolation structure thereof. The isolation structure having a poly cap thereon is able to offer better isolation capability by reducing the leakage current of the device. 
     The invention provides a method of forming a STI structure. A substrate with a first region and a second region is provided. A pad oxide layer and a masking layer are formed in sequence over the substrate. A patterned photoresist layer on the masking layer is formed. A plurality of trenches in the substrate is formed by performing an etching process using the patterned photoresist layer as a mask. An insulation layer is formed over the substrate to fill the trenches in the substrate. A first planarization process is performed on the insulation layer until a surface of the masking layer is exposed. An etching back process is performed on the insulation layer until a surface of the insulation layer is lower than the surface of the masking layer. A polysilicon layer is formed over the substrate to cover the masking layer and the insulation layer. A second planarization process is performed on the polysilicon layer until the surface of the masking layer is exposed, so that a poly cap is formed covering a whole surface of the insulation layer in each trench and the shallow trench isolation structures according to this invention are obtained. 
     The poly cap formed on the insulation layer of the trench serves as a protective layer and thereby prevents occurrence of the divot or oxide loss during the subsequent etching and cleaning steps. Thus, the isolation capability of the STI structure is improved and the device performance is enhanced. 
     This invention also provides a semiconductor structure, including a substrate having at least a trench therein, an insulation layer filled in the trench and a first polysilicon layer disposed on the insulation layer covering at least two opposite borders of the top surface of the insulation layer. The semiconductor structure may further include a second polysilicon layer disposed above the first polysilicon layer and the substrate, and a dielectric layer disposed between the first and second polysilicon layers. The first and second polysilicon layers are respectively shaped as first and second strips, and the first and second strips are paralleled to each other. 
     In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1F  are schematic cross-sectional views illustrating the process steps of forming a shallow trench isolation structure according to an embodiment of this invention. 
         FIGS. 1G-1H  are schematic cross-sectional views illustrating the exemplary process steps of forming an intermediate memory structure in the memory region according to an embodiment of this invention. 
       FIG.  1 H′ schematically illustrates a top layout view of the intermediate memory structure based on the exemplary process step of  FIG. 1H  according to an embodiment of this invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
       FIGS. 1A-1F  are schematic cross-sectional views illustrating the process steps of forming a shallow trench isolation structure according to an embodiment of this invention. 
     Referring to  FIG. 1A , a substrate  100  with a first region  102   a  and a second region  102   b  is provided. The first region  102   a  and the second region  102   b  are used for fabricating different devices, for example. In this embodiment, the first region  102   a  is a memory region for memory devices and the second region  102   b  is a logic region for logic devices. A pad oxide layer  104  is formed over the substrate  100  by, for example, a thermal oxidation process. A masking layer  106  is formed over the pad oxide layer  104  using, for example, a chemical vaporization deposition (CVD) process. The material of the masking layer  106  may include silicon nitride. A patterned photoresist layer (not shown) is formed on the making layer  106 . An etching process is performed using the patterned photoresist layer as a mask to form a plurality of trenches  108  in the substrate  100 . The etching process for forming the trenches  108  is, for example, reactive ion etching (RIE). 
     Referring to  FIG. 1B , an optional liner layer  110  is formed in the trenches  108  by, for example, a thermal oxidation process. The material of the liner layer  110  may include silicon oxide. An insulation layer  112  is formed over the substrate  100 , filling in the trenches  108  and covering the liner layer  110 . For example, the insulation layer  112  may be a silicon oxide layer formed by high-density plasma chemical vapor deposition (HDP-CVD). A planarization process, such as chemical mechanical polishing (CMP), is performed until the surface of the masking layer  106  is exposed. 
     Referring to  FIG. 1C , an etching back process is performed until the surface of the insulation layer  112  is lower than that of the masking layer  106 . The etching back process may include a dry etching process such as RIE. The dry etching process may be operated, for example, under a time control mode (i.e. etching for a fixed period of time until a desired depth is etched). The surface of the remaining insulation layer  112  within the trenches  108  is at least coplanar with or even higher than the substrate surface. 
     Referring to  FIG. 1D , a polysilicon layer  114  is formed over the substrate  100 , covering the masking layer  106  and the remaining insulation layer  112 . The method of forming the polysilicon layer  114  is, for example, a CVD process. Referring to  FIG. 1E , a planarization process, such as CMP, is performed to the polysilicon layer  114  until the surface of the masking layer  106  is exposed. The remaining portion of the polysilicon layer  114  forms a poly cap  116  to cover the whole surface of insulation layer  112  within each trench  108 . The poly cap has a thickness of about 300 angstroms to 500 angstroms, for example. 
     Referring to  FIG. 1F , the masking layer  106  is removed by a wet etching process using hot phosphoric acid as an etchant, for example. The shallow trench isolation structure  117  includes the liner layer  110 , the insulation layer  112  in the trench  108  and the poly cap  116  on the insulation layer  112 . 
     The poly cap  116  can avoid the occurrence of a divot or oxide loss near the top corner of the trench  108  during the subsequent etching and cleaning process steps. For example, the poly cap  116  covers the surface of the insulation layer  112  of the trench  108  and thus protects the insulation layer  112  during the following etching and cleaning process steps for removing the pad oxide layer. In this case, as the corners of the trench  108  is protected by the poly cap  116 , the divot issue around the top corner of the trench  108  is resolved and the leakage current or even the shortage of the device can be avoided. 
     Moreover, the method of the invention does not need any extra mask. Two simple process steps, depositing a polysilicon layer and performing a planarization process on the polysilicon layer, are enough to form a shallow trench structure with a poly cap thereon. In other words, the poly cap  116  of the STI structure is formed in a self-aligned way to cover at least the top corners of the STI structure. 
     Further, due to the etching back process performed to the insulation layer  112 , the surface of the insulation layer  112  is lower than that of the masking layer  106 . Therefore, the later-formed poly cap will not seriously change the topography of the STI region or area. Actually, the topography of the STI area in this invention is pretty smooth when compared with the conventional STI structure, which is beneficial for the embedded memory manufacturing process. 
     In this embodiment, the first region  102   a  is for memory devices and the second region  102   b  is for logic devices. According to the method described in this invention, the intermediate structure in the memory region (e.g. first region  102   a ) is illustrated in the below process steps. 
       FIGS. 1G-1H  are schematic cross-sectional views illustrating the exemplary process steps of forming an intermediate memory structure in the memory region according to an embodiment of this invention. 
     Referring to  FIG. 1G , in the first region  102   a , the pad oxide layer  104  ( FIG. 1F ) is removed, for example, by a wet etching process using fluoric acid as an etchant. A dielectric layer  118  is then conformally formed over the substrate  100  and covers the poly cap  116 . The dielectric layer may be a silicon oxide layer formed by thermal oxidation, for example. A polysilicon layer  120  is formed over the substrate to cover the dielectric layer  118 . The polysilicon layer  120  is formed by, for example, a CVD process. 
     Referring to  FIG. 1H , using the floating gate mask (the mask for defining the floating gate pattern in the memory manufacturing process) as a mask, the photolithography and etching process is performed to the polysilicon layer  120  to define floating gates  120   a . Using the same mask, the underlying dielectric layer  118  and the poly cap  116  are etched until the surface of the insulation layer  112  in the trench  108  is exposed, so as to form the patterned poly cap  116   a  and the patterned dielectric layer  118   a.    
     FIG.  1 H′ schematically illustrates a top layout view of the intermediate memory structure based on the exemplary process step of  FIG. 1H  according to an embodiment of this invention, while  FIG. 1H  shows the intermediate memory structure taken along the line A-A′ of FIG.  1 H′. 
     Referring to FIGS.  1 H and  1 H′, the poly cap  116   a  is disposed on the insulation layer  112 , covering at least two opposite borders of the top surface of the insulation layer  112 . The floating gate  120   a  is disposed right above the patterned poly cap  116   a  with the patterned dielectric layer  118   a  located between the poly cap  116   a  and the floating gate  120   a . The patterned poly cap  116   a  and the floating gate  122   a  are respectively shaped as strips paralleled to each other. 
     The following memory processes in the first region  102   a  and the logic processes in the second region  102   b  will not be described in details as these process steps are known to persons skilled in the arts. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.