Abstract:
A circuit for correcting the offset of an amplification and filtering chain having a predetermined gain and cut-off frequency depending on the value of at least one capacitor, comprising: a correction means for subtracting from the chain input a correction signal depending on the value of a programmable digital word; a digital automaton for, in a setting phase, searching, then memorizing one of two consecutive values of the digital word between which the output signal of the chain switches sign, the input signal being canceled during a setting phase; and comprising a means for, during the setting phase, reducing the value of said at least one capacitor with respect to its normal operating value.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to the correction of the offset of an amplification chain, and in particular of the offset of an amplification and low-pass filtering chain.  
           [0003]    2. Description of the Related Art  
           [0004]    An amplification and filtering chain is for example used at the output of an antenna block of a mobile phone to amplify and filter a noisy signal received with a low amplitude. Amplifiers used in such a chain frequently exhibit an offset to which the signals received by the amplifiers add. This offset reduces the maximum value of the signals that can be received by the amplifiers without for the amplifiers to be saturated, which reduces the chain performances. The offset of an amplification chain is generally corrected by subtracting from the signal received at the chain input a correction signal substantially equal to the chain offset.  
           [0005]    [0005]FIG. 1 very schematically shows an amplification and filtering chain  2  provided with an offset correction circuit  4 . Chain  2  and correction circuit  4  are integrated on a same chip. Chain  2  comprises an input terminal I receiving a signal from an antenna block not shown and an output terminal O. Terminal I is connected to the input of an amplifier  6 . The output of amplifier  6  is filtered by a low-pass filter  8  having a cut-off frequency Fc 8  before being provided to an amplifier  10 . The output of amplifier  10  is filtered by a low-pass filter  12  having a cut-off frequency Fc 12  before being provided to output terminal O. Correction circuit  4  comprises a digital automaton  14  having an input terminal connected to output terminal O of the chain. Automaton  14  provides over a bus  16  a control word COM to a digital-to-analog converter (DAC)  18 . The output of converter  18  is connected to input terminal I of chain  2 . Correction circuit  4  further comprises a switch  20  enabling cancellation of the signal provided by the antenna block to input terminal I. Automaton  14  and switch  20  are controlled by a means not shown.  
           [0006]    It is considered hereafter that terminal I receives from the antenna block an input signal Si and signals at higher frequency, and that terminal O provides as a response an output signal SO. If the signals at higher frequency are totally suppressed by the filters of chain  2 ; if G is the gain of chain  2  and Δ is the offset of chain  2 ; and if δ is a correction signal, positive or negative, permanently provided on input terminal I by converter  18  as a response to word COM, one has, in normal operation of the chain: SO=G.(Δ+δ+SI).  
           [0007]    The value of correction signal δ is determined in a setting phase to minimize sum Δ+δ. In the setting phase, switch  20  is off. Output O then provides an output signal SO=G(Δ+δ). At the beginning of the setting phase, automaton  14  provides a control word COM such that converter  18  generates a zero correction signal  6 , after which it measures the sign of signal SO. Automaton  14  then modifies the value of word COM to any one of two consecutive values between which signal SO=G(Δ+δ) switches sign. This value of word COM, for which sum Δ+δ is minimum, is then memorized and permanently provided to converter  18 . The setting phase is over, switch  20  is on, and the chain can operate normally. According to an alternative, the automaton may at the beginning of the setting phase provide a control word COM for which it is provided that sum Δ+δ is zero, then adjust the value of signal δ.  
           [0008]    The above correction circuit operates satisfactorily but it requires a setting phase which may be too long. Indeed, in certain systems such as mobile phones, signal SI is received in the form of packets separated by idle periods. To limit the system consumption, amplification chain  2  is only activated to receive each packet and powered off for idle periods. Now, the offset of amplification chain  2  may vary from one activation of the chain to the other, for example, due to a change in temperature or in supply voltage. Thus, the setting phase of the offset correction circuit may be implemented after each activation of chain  2 . The longer the setting phase, the longer chain  2  must be powered on before the packet reception, which increases the system consumption.  
           [0009]    It has been seen that the setting of correction circuit  4  comprises a modification of the bits of word COM by digital automaton  14 . Each time digital automaton  14  modifies a bit of word COM, and thereby signal  6  provided at the chain input, it must wait for a predetermined duration t to be sure that the chain has effectively transmitted the modification to its output SO before measuring the sign of signal SO. In practice, if the chain exhibits a cut-off frequency Fc (the smallest of cut-off frequencies Fc 8  and Fc 12  of filters  8  and  12 ), predetermined duration t depends on 1/Fc. If word COM comprises n bits, the setting phase lasts for n times duration t. To reduce the duration of the setting phase, the number of bits of word COM thus has to be reduced, which reduces the accuracy of offset Δ.  
           [0010]    A solution to this problem consists of not using the above correction circuit  4 , and of using an analog correction circuit which requires no setting phase and subtracts from signal SI the D.C. portion of a feedback signal equal to the division of output signal SO by gain G of the chain. However, such a correction circuit is expensive since it imposes using a large capacitor to extract the D.C. portion of the feedback signal.  
         BRIEF SUMMARY OF THE INVENTION  
         [0011]    An embodiment of the present invention provides an inexpensive and easy-to-set offset correction circuit.  
           [0012]    Another embodiment of the present invention provides an inexpensive and fast-to-implement offset correction method.  
           [0013]    Generally, an embodiment of the present invention comprises shortening the duration of the setting phase by increasing the cut-off frequency of the chain. For this purpose, the embodiment provides, in the setting phase, increasing the cut-off frequency of each low-pass filter of the chain by reducing the value of the capacitors used in each filter.  
           [0014]    More specifically, one embodiment of the present invention provides a circuit for correcting an offset of an amplification and low-pass filtering chain having a predetermined gain and a predetermined cut-off frequency depending on a value of at least one capacitor, comprising a correction means for subtracting from an input signal of the chain a correction signal depending on the value of a programmable digital word, a digital automaton for, in a setting phase, searching, then memorizing one of two consecutive values of the digital word between which an output signal of the chain switches sign, the input signal being canceled during the setting phase, and comprising a means for, during the setting phase, reducing the value of said at least one capacitor with respect to its normal operating value.  
           [0015]    According to an embodiment of the present invention, the chain has a predetermined cut-off frequency depending on the value of several capacitors, and the circuit for correction the chain offset comprises a means for, during the setting phase, reducing the value of each capacitor with respect to its normal operating value.  
           [0016]    According to an embodiment of the present invention, the means for reducing the value of said at least one capacitor consists in a means for switching said at least one capacitor with a capacitor of value smaller than the normal operating value of said at least one capacitor.  
           [0017]    According to an embodiment of the present invention, said at least one capacitor is formed of a capacitor of small value connected in parallel to a plurality of small capacitors, each series-connected to a respective programmable switch, and the means for reducing the value of said at least one capacitor is capable of controlling the turning-off of the programmable switches.  
           [0018]    One embodiment of the present invention also aims at a method for correcting the offset of a chain of amplification and low-pass filtering of an input signal, having a predetermined gain and a predetermined cut-off frequency depending on the value of at least one capacitor, comprising:  
           [0019]    a) canceling the input signal of the chain;  
           [0020]    b) subtracting from the input signal of the chain a correction signal depending on a value of a digital word and modifying said value from a predetermined initial value to any one of two consecutive values between which an output signal of the chain switches sign; and  
           [0021]    c) memorizing the value of the digital word;  
           [0022]    the value of said at least one capacitor being during the implementation of b) reduced with respect to its normal operating value to increase the cut-off frequency.  
           [0023]    The foregoing features of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    [0024]FIG. 1, previously described, schematically shows an amplification and filtering chain provided with a conventional offset-correction circuit;  
         [0025]    [0025]FIG. 2 schematically shows an amplification and filtering chain provided with an offset-correction circuit according to one embodiment of the present invention;  
         [0026]    [0026]FIG. 3 schematically shows a first example of a filter provided with a setting element according to one embodiment of the present invention to increase its cut-off frequency;  
         [0027]    [0027]FIG. 4 schematically shows a second example of a filter provided with a setting element according to one embodiment of the present invention to increase its cut-off frequency; and  
         [0028]    [0028]FIG. 5 illustrates the structure of a settable capacitor used according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0029]    Embodiments of a method and circuit for correcting the offset of an amplification chain are described herein. In the following description, numerous specific details are given to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.  
         [0030]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.  
         [0031]    Same elements have been designated with same reference numerals in FIG. 1 and in the next drawings. Only those elements necessary to the understanding of embodiments of the present invention have been shown.  
         [0032]    [0032]FIG. 2 schematically shows an amplification and filtering chain  2  provided with an offset-correction circuit according to one embodiment of the present invention. Chain  2  has the same structure as in FIG. 1. In addition to automaton  14 , to digital-to-analog converter  18 , and to switch  20 , the circuit according to this embodiment of the present invention comprises setting elements  22  and  24 , described hereafter that, when activated, increase the cut-off frequencies of filters  8  and  12 .  
         [0033]    Setting elements  22  and  24  are activated in the setting phase. The cut-off frequency of chain  2  then increases from Fc to Fc′. In the setting phase, the waiting time between each modification of a bit of word COM and the measurement of the sign of signal SO corresponding to this modification decreases from t to t′. t′ being smaller than t, more tests can be carried out within a given time and thus a word COM comprising a large number of bits can be used, and the accuracy of the chain offset correction can be increased.  
         [0034]    As an example, if cut-off frequency Fc of the chain is 100 kHz and if cut-off frequency Fc′ modified according to one embodiment of the present invention is 300 kHz, number n′ of bits of the word COM of an embodiment of a correction circuit can be 3 times greater than the number of bits n of the same word in a conventional correction circuit. If duration T available for the setting phase is 14 μs and if t=0.35/Fc=3.5 μs and t′=0.35/Fc′=1.16 μs, n is equal to 4 and n′to 12. If Δ can vary between −0.5 and +0.5 volt, correction signal δ has an accuracy of 62.5 millivolts if it is generated by digital-to-analog converter  18  as a response to a word COM of n=4 bits, and an accuracy of 244 microvolts if it is generated according to one embodiment of the present invention as a response to a word COM of n′=12 bits.  
         [0035]    [0035]FIG. 3 shows an embodiment of filter  8  of FIG. 2 and of setting element  22  according to the present invention coupled to the filter  8  to increase the cut-off frequency of filter  8 . Filter  12  and setting element  24  according to one embodiment of the present invention may respectively have the same structure as filter  8  and element  22 . Filter  8  comprises an input terminal  25  and an output terminal  26  connected by a resistor R. A capacitor C has a first terminal connected to the output terminal of filter  8  and a second terminal connected to a common-mode voltage, here, the ground. Setting element  22  comprises a capacitor C′ of smaller value than capacitor C, having a terminal connected to the output of filter  8  and having another terminal connected to ground via a switch SW′. Element  22  further comprises a switch SW interposed between the second terminal of capacitor C and the ground.  
         [0036]    In normal operation, switches SW and SW′ are respectively on and off and the cut-off frequency of filter  8  is Fc=½πRC. In the setting phase, element  22  is controlled for switches SW and SW′ to be respectively off and on. The cut-off frequency of filter  8  then is Fc′=½πRC′&gt;Fc. The choice of the value of capacitor C′ enables determining cut-off frequency Fc′. Setting element  22  is particularly simple and inexpensive to implement, which is an additional advantage of one embodiment of the present invention.  
         [0037]    one embodiment of the present invention has been described in relation with an amplification chain referenced to a common-mode voltage and having a single input terminal I and a single output terminal O, but those skilled in the art will easily adapt the embodiment to a differential amplification chain having two differential input terminals and two differential output terminals. Such a chain will use differential filters. Such a differential filter may for example be formed of two filters  8  such as in FIG. 3 having their common modes interconnected. Those skilled in the art should note that an imbalance between resistors R of the two filters  8  forming a differential filters also introduces an offset in the chain using this filter. Those skilled in the art should also note that the increase in the cut-off frequency of the filter according to one embodiment of the present invention by reduction of the value of the filter capacitors does not modify the offset introduced by the filter in the chain. This enables accurate setting of the offset-correction signal of the chain and is an additional advantage of the embodiment.  
         [0038]    An embodiment of the present invention has been described in relation with an amplification and filtering chain using filters having a voltage input and a voltage output, but the present invention also applies to a chain using other types of filters, for example, filters having a current input and a voltage output such as a Ranch filter.  
         [0039]    [0039]FIG. 4 shows an example of a filter  27  having a current input  28  and a voltage output  29  usable in an amplification and filtering chain. Input terminal  28  of filter  27  is connected to the input terminal of a transresistance amplifier  30 . The output terminal of amplifier  30  is connected to the input terminal of an integrator assembly formed of an amplifier  32  of infinite gain and of a capacitor C 1  connected in parallel. The output terminal of amplifier  32  is connected to output terminal  29  of filter  27 . A capacitor C 2  and a resistor R 2  are connected in parallel between the input and output terminals of filter  27 . The input terminal of filter  27  is further connected to a supply voltage Vcc by a capacitor C 3  and a resistor R 3  connected in parallel. An embodiment of the present invention provides adding to filter  27  setting elements  34 ,  36 , and  38  respectively enabling replacement of capacitors C 1 , C 2 , and C 3  with capacitors of smaller value C 1 ′, C 2 ′, C 3 ′ in the setting phase.  
         [0040]    In practice, if filter  27  is integrated on a chip, each capacitor C (C 1 , C 2 , C 3 ) is formed of a capacitor of small value Cr connected in parallel to a plurality of small capacitors Cr′, Cr″, each series-connected to a respective programmable switch SWr′, SWr″.  
         [0041]    [0041]FIG. 5 illustrates such a structure, which enables adjusting the values of capacitors C to compensate for possible drifts due to a fluctuation of the chip manufacturing process. For this purpose, after manufacturing of the chip, a calibration means is provided to program the turning-on of the appropriate number of switches SWr′, SWr″ for capacitors C to have the desired value. According to a particularly advantageous embodiment of the present invention, the elements for setting the correction circuit enable temporarily turning off switches SWr′, SWr″ in the correction circuit setting phase, to give capacitors C a minimum value. Two setting capacitors Cr′, Cr″ have been shown but, in practice, a larger number of setting capacitors will be used.  
         [0042]    It should be noted by those skilled in the art that means according to embodiments of the present invention for increasing the cut-off frequency of an amplification and filtering chain by reducing the value of the capacitors of the low-pass filters of the chain are usable whatever the structure of the low-pass filters. This is an additional advantage of the embodiment(s).  
         [0043]    Of course, the present invention is likely to have various alterations, modifications, and improvement which will readily occur to those skilled in the art. In particular, an embodiment has been described in relation with an amplification/filtering correction circuit comprising two amplifiers and two filters, but those skilled in the art will easily adapt embodiments to the correction circuit of any amplification/filtering chain comprising at least one low-pass filtering, the cut-off frequency of which depends on the value of at least one capacitor.  
         [0044]    An embodiment has been described in relation with an amplification/filtering chain providing a zero output signal as a response to a zero input signal when the offset is corrected, but those skilled in the art will easily adapt the embodiments to an amplification/filtering chain providing a non-zero output signal as a response to a zero input signal when the offset is corrected.  
         [0045]    An embodiment has been described in relation with a correction circuit enabling correcting the offset with a great accuracy within a given setting duration, but those skilled in the art will easily adapt embodiments to a correction circuit enabling correction of the offset with no accuracy improvement but within a reduced setting duration, or by making a compromise between the offset correction accuracy and the duration of the setting phase.  
         [0046]    An embodiment has been described in relation with a correction circuit, the setting phase of which has not been detailed, but those skilled in the art will easily adapt embodiments to any appropriate correction circuit setting phase. For example, the setting phase may comprise, from a median value of the control word, of modifying bit after bit of the value of the control word, starting from the most significant bit, and to the least significant bit.  
         [0047]    Such alterations, modifications, and-improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.  
         [0048]    All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.