Abstract:
A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

Description:
FIELD OF THE INVENTION 
       [0001]    This invention relates to packages for multiple semiconductor chips, and more particularly to packages with multiple semiconductor chips that is formed from two or more pre-molded packages. 
       BACKGROUND OF THE INVENTION 
       [0002]    There is a need for low cost, reliable packages with a standard footprint for interconnecting two or more semiconductor chips. Such packages must be able to be modified easily for specialized applications having limited projected sales as well as for mass market sales. Thus the packaging process must be able to interconnect two or more semiconductor chips selected from a wide range of semiconductor chips available now or in the future. 
         [0003]    The generally preferred method of making vertically stacked multiple die package uses wire bonds to connect a leadframe to the die. However, as compared to flip chip, wire bonds are not considered to be as good as flip-chip attachment of die to a leadframe in both electrical and thermal performances. In addition, the flip-chip attachment on a pre-molded leadframe is also a economical method to package a semiconductor die. 
       SUMMARY OF THE INVENTION 
       [0004]    The invention comprises, in one form thereof, a multiple semiconductor die module comprising a first pre-molded package comprising a first semiconductor die having solder bump interconnects on a first side thereof which is flip-chip attached to a leadframe in the first pre-molded package, a second pre-molded package comprising a second semiconductor die having solder bump interconnects on a first side thereof which is flip-chip attached to a leadframe in the second pre-molded package, and a plurality of interconnections between the first and second pre-molded packages, wherein the first and second pre-molded packages are attached such that a second side of the first semiconductor die opposite to the first side of the first semiconductor die is proximate and parallel to a second side of the second semiconductor die opposite to the first side of the second semiconductor die. 
         [0005]    In another form, the invention includes a method for forming a multiple semiconductor die module. The method comprises the steps of encapsulating a first and a second leadframe, flip-chip attaching semiconductor dice having connections on a first side thereof to each of the first and second leadframes to form separate first and second pre-molded packages, and interconnecting the first and second pre-molded packages such that a second side of the first semiconductor die opposite to the first side of the first semiconductor die is proximate and parallel to a second side of the second semiconductor die opposite to the first side of the second semiconductor die. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    The aforementioned and other features, characteristics, advantages, and the invention in general will be better understood from the following more detailed description taken in conjunction with the accompanying drawings, in which: 
           [0007]      FIG. 1  is a schematic diagram of an interface between an USB connector and either an audio codec or a USB controller which includes circuitry in an embedded die package on package (POP) with pre-molded leadframe according to the present invention; 
           [0008]      FIG. 2  is a perspective view of an embedded die POP with pre-molded leadframe according to an embodiment the present invention; 
           [0009]      FIGS. 3A ,  3 B,  3 C,  3 D, and  3 E are respective top, bottom, side views of the package shown in  FIG. 2 , and perspective views of the respective bottom and top pre-molded packages which are components of the package shown in  FIG. 2 ; 
           [0010]      FIGS. 4A and 4B  are semiconductor die contained in the POP package shown in  FIG. 1 ; 
           [0011]      FIGS. 5A and 5B  are a top perspective view and a bottom view, respectively, of the package shown in  FIG. 2 ; 
           [0012]      FIGS. 6A ,  6 C, and  6 E are bottom views of the leadframe, molding and semiconductor die in the top pre-molded package in the package shown in  FIG. 2 ; 
           [0013]      FIGS. 6B ,  6 D, and  6 F are top views of the leadframe, molding and semiconductor die in the bottom pre-molded package in the package shown in  FIG. 2 ; 
           [0014]      FIGS. 7A ,  7 B,  7 C,  7 D,  7 E, and  7 F are perspective views showing the steps used to form the top pre-molded package in the package shown in  FIG. 2 ; 
           [0015]      FIGS. 8A ,  8 B,  8 C,  8 D,  8 E,  8 F, and  7 G are perspective views showing the steps used to form the bottom. pre-molded package and the attachment of the top pre-molded package to the bottom pre-molded package to form the package shown in  FIG. 2 ; 
           [0016]      FIG. 9  is a perspective view of an embedded die POP with pre-molded leadframe according to another embodiment the present invention; 
           [0017]      FIGS. 10A and 10B  are a top perspective view of the top pre-molded package shown in  FIG. 9  and a side view of the package shown in  FIG. 9 ; 
           [0018]      FIGS. 11A ,  11 B, and  11 C are bottom views of the lead frame, molding and semiconductor die in the top pre-molded package in the package shown in  FIG. 9 ; and 
           [0019]      FIGS. 12A ,  12 B,  12 C,  12 D,  12 E, and  12 F are perspective views showing the steps used to form the top pre-molded package in the package shown in  FIG. 9 . 
       
    
    
       [0020]    It will be appreciated that for purposes of clarity and where deemed appropriate, reference numerals have been repeated in the figures to indicate corresponding features. Also, the relative size of various objects in the drawings has in some cases been distorted to more clearly show the invention. 
       DETAILED DESCRIPTION 
       [0021]      FIG. 1  is a schematic diagram showing an example of an application of one embodiment  30  of an embedded die package on package (POP) with pre-molded leadframe module according to the present invention. The module  30 , containing two semiconductor die, a load management switch  32  and an audio/digital switch  34 , is coupled between a USB connector  36  and two different device types, an audio codec  38  which communicates with analog signals having positive and negative voltage swings and a USB controller  40  which communicates with digital signals. The module  30  receives power from the USB Vbus and receives a control signal from Vaudio. When Vaudio is present, the module  30  passes the left and right analog signals between the USB connector  36  and the audio codec  38 , and when Vaudio is not present, the module  30  passes digital data between the USB connector  36  and the USB controller  40 . 
         [0022]    In one example of the module  30  the load management switch  32  is an FPF2125, and the audio/digital switch  34  is a FSA221, both of which are made by Fairchild Semiconductor Corp. A first resistor  42  connects the Vbus line to the “on” input terminal of the FPP2125 to enable the load management switch  32 , and a second resistor  44  connected between “Iset” and ground sets the maximum current allowed to pass from the load management switch  32  to the audio/digital switch  34 . 
         [0023]      FIG. 2  is a perspective view the embedded die package on package (POP) with pre-molded leadframe module  30 . The module  30  includes a top pre-molded package  50  and a bottom pre-molded package  52  connected together by solder bumps  54 . 
         [0024]      FIGS. 3A ,  3 B, and  3 C show respective top, bottom, and side views of the module  30 .  FIG. 3D  is a top perspective view of the bottom pre-molded package  52 , and  FIG. 3E  is a bottom perspective view of the top pre-molded package  50 . As can be seen in  FIG. 3B  the module  30  has lands  56  exposed on the bottom of the module  30  for external connections such as to a printed circuit board. 
         [0025]      FIGS. 4A and 4B  are bond site drawings of the FSA221 die  34  and the FPF2125 die  32 , respectively, showing the solder bump locations for the various connections to the dice. The two dice are not the same size, the FPF2125 die being longer and wider than the FSA221 die. Both dice have the same thickness. 
         [0026]      FIG. 5A  is a top perspective view of a module  30  with the top and bottom molded packages connected together with the molding of the top pre-molded package  50  shown in outline.  FIG. 5A  also indicates the assigned land numbers along with their respective signals.  FIG. 5B  is the bottom view of  FIG. 3B  with the lands  56  numbered and their respective signals identified. 
         [0027]      FIGS. 6A and 6B  are top views of an unencapsulated leadframes  58  and  60  used in the top pre-molded package  50  and the bottom pre-molded package  52 , respectively, for the module  30 . The present invention is not limited to the particular leadframes  58  and  60 , but can use other leadframes for other POP pre-molded package modules appropriate for other module applications. Peripheral leadframe segments  62  have arms  63  which extend into the inner region of the leadframes  58  and  60 , and other peripheral leadframe segments  64  are without such arms. The outer portions of all of the leadframe segments, except one corner portion  66 , have the same shape. The one corner portion is distinctive to enable identification of the land pin numbers. The outer portions of all of the leadframe segments have two unencapsulated surfaces, one of which is used for electrically connecting the two pre-molded packages  50  and  52 . 
         [0028]      FIGS. 6C and 6D  show the leadframes  58  and  60  after molding operations to form molded leadframes  68  and  70 , respectively, with the molds shown in outline. The thicker regions  71  on the ends of the leadframe arms  63  are exposed and lie at the bottom of cavities  72  and  74  in the molded leadframes  68  and  70 , respectively. 
         [0029]      FIGS. 6E and 6F  show the molded leadframes  68  and  70  after the semiconductor dice  32  and  34  have been flip-chip attached to the arms of the leadframes  58  and  60 , respectively, and underfill  76  has been injected into the cavities  72 ,  74  . Thus, the solder bumps or gold stud bumps on the semiconductor dice  32 ,  34  are facing away from the interface of the two pre-molded leadframes  68 ,  70  after they are connected together by the solder bumps  54 . 
         [0030]      FIGS. 7A-F  are perspective views showing the top package assembly process.  FIG. 7A  is a bottom perspective of the top molded leadframe  68  with the molding shown in outline.  FIG. 7B  is a top perspective view of the FPF2125 die  32  (that is, the view is a top view with respect to the module  30  shown in  FIG. 2 ).  FIG. 7C  is  FIG. 7A  with the molding shown normally. The FPF2125 die is flip-chip bonded to the leadframe inside the cavity  72  of the molded top leadframe subassembly  68  as shown in  FIG. 7D . Underfill  80  is injected into the cavity  72  to enclose all but the back side of the FPF2125 as shown in  FIG. 7E .  FIG. 7F  shows the completed bottom pre-molded package which has had solder bumps  54  added using a standard solder ball bumping process. 
         [0031]      FIGS. 8A-H  are perspective views showing the bottom package assembly process and the attachment of the top pre-molded package  50  onto the bottom package.  FIGS. 8A ,  8 B,  8 C,  8 D and  8 E are analogous to  FIGS. 7A-7E  except that top perspective views are shown with the exception of  FIG. 8B  which is a bottom perspective view of the FSA221 die  34 .  FIG. 8F  shows the bottom pre-molded package  52  after solder paste  78  has been screened onto the sites for the solder balls  54  attached to the top pre-molded package  50  which is shown in  FIG. 8G . After the top and bottom packages are placed together, a solder reflow operation completes the assembly process to produce the module  30  shown in  FIG. 2 . 
         [0032]      FIG. 9  is an alternative embodiment 90 of the module  30 . The bottom pre-molded package  52  is the same as the bottom package shown in  FIGS. 2-8 , but the top pre-molded package  92  is different than the top pre-molded package  50  shown in  FIGS. 2-8 . 
         [0033]    Top and bottom views of the module  90  are the same as the top and bottom views of the module  30  shown in  FIGS. 3A ,  3 B, and  5 B.  FIG. 10A  is a bottom perspective view of the top pre-molded package  92  showing the FPF2125 die  32  positioned on top of the top molded leadframe  94 , and  FIG. 10B  is a side view of the module  90 . 
         [0034]      FIG. 11A  is a top view of an unencapsulated leadframe  96  used in the top pre-molded package  92 . The peripheral leadframe segments  98  are the same as the peripheral leadframe segments  62  and  64  shown in  FIG. 6A  except that the segments  98  are shorter vertically than the segments  62 ,  64  shown in  FIG. 6A .  FIG. 11B  shows the leadframe  96  after molding operations to form the top molded leadframe  100  with the molding shown in outline. The leadframe arms are encapsulated except for the thicker regions at the ends of the arms which are exposed on the underside the top molded leadframe  100 . There is no cavity in the molded leadframe  100 .  FIG. 11C  shows the top molded leadframe  100  after the semiconductor die  32  has been flip-chip attached to the arms of the top molded leadframe  100  to form the top pre-molded package  92 . Thus, the solder bumps or gold stud bumps on the semiconductor die  32  are facing away from the interface of the two pre-molded packages  92 ,  52  after they are connected together by the solder bumps  54 . 
         [0035]      FIGS. 12A-F  are perspective views showing the assembly process of the top pre-molded package  92 .  FIG. 12A  is a bottom perspective of the top molded leadframe  100  with the molding shown in outline.  FIG. 12B  is  FIG. 12A  with the molding shown normally.  FIG. 12C  is a top perspective view of the FPF2125 die  32  (that is, the view is a top view with respect to the module  90  shown in  FIG. 9 ). The FPF2125 die  32  is flip-chip bonded to the molded leadframe  100  after solder paste  102  has been screen printed onto the as shown in  FIG. 12D  to form the top pre-molded package  92  shown in  FIG. 12E .  FIG. 12F  shows the completed top pre-molded package  92  after solder bumps  54  have been attached added using a standard solder ball bumping process. 
         [0036]    The bottom package assembly and attachment of the top pre-molded package  92  to the bottom pre-molded package  52  is the same as shown in  FIGS. 8A-H . 
         [0037]    The package and method of packaging according to the present invention provides a relatively thick protective molding around most of the semiconductor die, and the semiconductor die is not bonded to a leadframe during the molding operation. In addition the separate top and bottom pre-molded packages can be tested prior to joining the two pre-molded packages. 
         [0038]    While the invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the scope of the invention. 
         [0039]    Therefore, it is intended that the invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope and spirit of the appended claims.