Abstract:
The invention concerns a circuit comprising: a first transistor ( 102 ) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit ( 108 ) coupled to a further node of said first transistor; and a control circuit ( 110 ) adapted to control said biasing circuit to apply a first control voltage (V CTRL ) to said further node to adjust the timing of at least one of said transitions.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the priority benefit of French Patent Application number 13/55253, filed on Jun. 7, 2013, entitled “Circuit et procédéde correction de décalage temporel”, the contents of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. 
       FIELD 
       [0002]    The present application relates to a circuit and method for skew correction. 
       BACKGROUND 
       [0003]    In the fields of signal sampling and other high frequency applications, timing signals of up to 10 GHz or more are often used to control switches or other circuit elements. In such applications, it is generally desirable to avoid any skew, in other words timing mismatch, between the timing signals, which can result in the addition of unacceptable spurs. 
         [0004]    One example is sampling circuitry, such as track and hold circuits, of a time-interleaved analog to digital converter (ADC). In such an ADC, a number of ADC cores are arranged in parallel, each having an input coupled to a corresponding track and hold circuit controlled by a clock signal to store an input signal at a given time instant. The clock signal of each track and hold circuit is offset with respect to the others such that the overall sampling rate applied to the input signal is higher than that of each clock signal. 
         [0005]    In some applications the presence of skew between clock signals can be detected and corrected by feedback circuitry. 
         [0006]    However, a problem with existing solutions for correcting skew is that they tend to add noise in the form of jitter to the clock signal, which is undesirable. There is thus a need in the art for a solution without such a problem. 
       SUMMARY 
       [0007]    It is an aim of embodiments of the present disclosure to at least partially address one or more needs in the prior art. 
         [0008]    According to one aspect, there is provided a circuit comprising: a first transistor having first and second main current nodes, and a gate node adapted to receive a first timing signal for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit coupled to a further node of said first transistor; and a control circuit adapted to control said biasing circuit to apply a first control voltage to said further node to adjust the timing of at least one of said transitions. 
         [0009]    According to one embodiment, the first transistor has an SOI structure, and wherein said further node is coupled to a back gate of said first transistor. 
         [0010]    According to one embodiment, the first transistor comprises a semiconductor layer isolated from said back gate by a layer of insulator. 
         [0011]    According to one embodiment, the first transistor is a bulk transistor and said further node is a bulk node. 
         [0012]    According to one embodiment, the first transistor forms part of a track and hold circuit further comprising a capacitor, the first transistor having a first main current node coupled to an input node of the track and hold circuit, and a second main current node coupled to said capacitor. 
         [0013]    According to one embodiment, the circuit further comprises a second transistor having first and second main current nodes, and a gate node adapted to receive a second timing signal for causing the second transistor to transition between conducting and non-conducting states, wherein the first and second timing signals are differential signals, and wherein said biasing circuit is further coupled to a further node of said second transistor, and wherein said control circuit is further adapted to control said biasing circuit to apply a second control voltage to said further node of said second transistor to adjust the timing of at least one of the transitions of the second transistor. 
         [0014]    According to one embodiment, the first main current nodes of said first and second transistors are coupled to a current source, and the circuit further comprises a third transistor having a first main current node coupled to a second main current node of the first transistor and a control node coupled to a second main current node of the second transistor, the control node of said third transistor further receiving an input signal to be sampled. 
         [0015]    According to one embodiment, the circuit further comprises: a fourth transistor having a first main current node coupled to a first voltage signal, a control node coupled to a second voltage signal and a second main current node coupled to an output node of the circuit; a fifth transistor having a first main current node coupled to a third voltage signal, a control node coupled to a fourth voltage signal and a second main current node coupled to said output node of the circuit; and circuitry comprising said first and second transistors adapted to generate said first and second voltage signals, wherein said first and second voltage signals are both referenced to a first supply voltage and wherein said third and fourth voltage signals are both referenced to a second supply voltage. 
         [0016]    According to one embodiment, the circuitry is adapted to: generate said first voltage signal by offsetting said first supply voltage by an amount determined by relative levels of first and second timing signals; and generate said second voltage signal by offsetting said first supply voltage by an amount determined by the relative levels of said first and second timing signals. 
         [0017]    According to one embodiment, the circuitry comprises: a first branch generating said first voltage signal and comprising a resistor coupled to said first supply voltage and in series with said first transistor; and a second branch generating said second voltage signal and comprising a resistor coupled to said first supply voltage and in series with said second transistor. 
         [0018]    According to one embodiment, each of said first and second timing signals has a voltage swing of less than 0.6 V. 
         [0019]    According to one embodiment, each of said first and second timing signals has a first voltage swing, and wherein an output signal generated at said output node has a second voltage swing higher than said first voltage swing. 
         [0020]    According to a further aspect, there is provided a time-interleaved analog to digital converter comprising a plurality of track and hold circuits each comprising the above circuit, and a plurality of converter blocks. 
         [0021]    According to one embodiment, the time-interleaved analog to digital converter further comprises a skew estimation block adapted to receive digital values from said plurality of converter blocks and to generate said first control voltage of each track and hold circuit based on an analysis of said digital values. 
         [0022]    According to a further aspect, there is provided a method of modifying the timing of at least one of transitions between conducting and non-conducting states of a first transistor having first and second main current nodes, a gate node, and a further node, the method comprising: applying to the gate node of said first transistor a first timing signal for causing the first transistor to transition between conducting and non-conducting states; and controlling, by a control circuit, a biasing circuit to apply a first control voltage to said further node to adjust the timing of at least one of said transitions of the first transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    The foregoing and other features and benefits will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: 
           [0024]      FIG. 1A  schematically illustrates a circuit according to an example embodiment of the present disclosure; 
           [0025]      FIG. 1B  schematically illustrates a track and hold circuit according to a further example embodiment of the present disclosure; 
           [0026]      FIG. 2  is a graph showing an example of a signal transition in the circuit of  FIG. 1A  or  1 B; 
           [0027]      FIG. 3A  schematically illustrates a circuit according to a further example embodiment of the present disclosure; 
           [0028]      FIG. 3B  is a graph showing an example of a signal transition in the circuit of  FIG. 3A ; 
           [0029]      FIG. 4  schematically illustrates a circuit according to a further example embodiment of the present disclosure; 
           [0030]      FIG. 5  is a timing diagram showing signals in the embodiment of  FIG. 4  according to an example embodiment; 
           [0031]      FIG. 6  schematically illustrates a time-interleaved analog to digital converter according to an embodiment of the present disclosure; and 
           [0032]      FIG. 7  is a cross-section view of a transistor according to an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    The US patent application U.S. Pat. No. 7,808,408 describes a method of skew correction in which a master clock signal is corrected by a skew adjustment block based on a feedback signal generated by a correction estimator. 
         [0034]    The publication entitled “A 2.8GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS”, Dusan Stepanovic et al., describes a technique in which a least-mean-square algorithm is used to estimate, among other things, timing mismatches, which can then be corrected by an analog part. 
         [0035]    In order to perform skew adjustment of a clock signal, both of the above solutions rely on intercepting and adjusting the timing signal before it reaches the circuitry to be controlled. However, doing so risks adding noise in the form of jitter to the clock signal, which is undesirable. 
         [0036]      FIG. 1A  illustrates a circuit  100  comprising a transistor  102 , which in this example is an NMOS transistor, but which in alternative embodiments could be a PMOS transistor or another type of transistor. 
         [0037]    The transistor  102  has main current nodes, for example source and drain nodes, coupled to nodes  104  and  106  of the circuit. The circuitry coupled to these nodes  104  and  106  is not illustrated in  FIG. 1A , but certain examples of such circuitry will be described herein after. A gate node of transistor  102  receives a timing signal CLK. As is well-known in the art, the timing signal CLK alternates between two voltage levels, one of which activates transistor  102  to provide a conduction path between the nodes  104  and  106 , and the other of which renders the transistor  102  non-conducting, such that node  106  is disconnected from node  104 . 
         [0038]    Transistor  102  also comprises a further node  107 , which receives a control voltage V CTRL . For example, transistor  102  has a bulk structure and the further node  107  is a bulk node. Alternatively, transistor  102  has an SOI (semiconductor on insulator) structure, and the further node  107  is a back gate of the transistor  102 . 
         [0039]    The control voltage V CTRL  is for example generated by a voltage generation block  108 , based on a control signal from a control block  110 . For example, the voltage generation block  108  comprises means for biasing the further node  107  of transistor  102 , which may include a digital to analog converter, charge pump and/or other circuitry suitable for generating the control voltage. 
         [0040]    The control block  110  for example comprises a memory storing one or more values indicating the control voltage V CTRL  to be applied to the further node  107  of transistor  102 . The control block  110  may additionally or alternatively receive one or more input signals, such as a feedback signal, based on which the control signal to the voltage generation block  108  is generated. For example, in some embodiments the control block  110  is implemented in a similar fashion to the correction estimator described in U.S. Pat. No. 7,808,408, and the contents of that application is hereby incorporated by reference in its entirety to the extent allowable by the law. Alternatively, the control block  110  is implemented in a similar fashion to the timing least-mean-square block described in the above-mentioned publication by Dusan Stepanovic, the contents of which is also hereby incorporated by reference in its entirety to the extent allowable by the law. 
         [0041]      FIG. 1B  illustrates the circuit  100  in the particular case that the circuit is a track and hold circuit, the node  104  receiving an input voltage V IN , and the node  106  being coupled to ground via a capacitor  112 . 
         [0042]    Operation of the circuit  100  of  FIGS. 1A and 1B  will now be described with reference to  FIG. 2 . 
         [0043]      FIG. 2  is a graph illustrating a transition of the timing signal CLK of  FIGS. 1A and 1B  from a high state V H  to a low state V L . For example, the high state V H  corresponds to a voltage level at or close to the supply voltage VDD, and is for example at between 0.8 and 2.5 V. The low state V L  for example corresponds to a voltage level at or close to the ground voltage GND, and is for example at between 0 and 0.2 V. 
         [0044]    For example, such a clock transition has the effect of rendering the transistor  102  non-conducting. In the case of the track and hold circuit of  FIG. 1B , such a transition is for example used to isolate the voltage stored on capacitor from the input node  104 , such that the input voltage signal V IN  is sampled at this time instant and held on the capacitor  112 . 
         [0045]    As illustrated in  FIG. 2 , during the falling edge of the timing signal CLK, the voltage at the gate of transistor  102  for example falls relatively linearly with time until it reaches the low voltage level V L . The transistor  102  is rendered non-conductive at the moment that a threshold level V TH , shown by a line  202 , is passed. The threshold level V TH  is for example at a level of between 0.2 and 0.8, depending on the particular transistor technology applied. As shown by a dashed line  204  in  FIG. 2 , the time instant that the signal CLK falls below the threshold voltage V TH  corresponds to a sampling time instant t s  at which the transistor becomes non-conducting. 
         [0046]    Furthermore, by modifying the voltage applied to the further node  107  of transistor  102 , the threshold voltage can also be adjusted. 
         [0047]    In one example, the transistor  102  is an NMOS transistor, for example with a bulk or SOI structure, and the threshold voltage V TH  is at 0.5 V corresponding to a control signal V CTRL  of 0 V. By reducing this control voltage, the threshold voltage can be increased. For example, if the control signal V CTRL  is reduced to a level of −1 V, the threshold voltage is for example increased to a level of V TH ′ shown in  FIG. 1 , which is for example at 0.6 V, and thus the new sampling time becomes t s ′, which is earlier than t s . Alternatively, by increasing the control signal V CTRL , the threshold voltage can be decreased. For example, if the control signal V CTRL  is increased to a level of 1 V, the threshold voltage is for example reduced to a level of V TH ″ shown in  FIG. 1 , which is for example at 0.4 V, and thus the new sampling time becomes t s ″, which is later than t s . 
         [0048]    In another example, the transistor  102  is a PMOS transistor, for example with a bulk or SOI structure, and the threshold voltage can be increased or decreased by the opposite adjustments to the control voltage described above. 
         [0049]    The time shift for a given change in the control voltage V CTRL  will depend on various factors, such as the type and dimensions of the transistor  102  and the slope of the falling or rising edge of the timing signal CLK. 
         [0050]    In one example, a period of the timing signal CLK is of around 100 ps, the rise time and fall time of the clock edges are around 10 ps, and the voltage adjustment at the further node  107  permits a time shift of the time t s  by up to ±1 ps. 
         [0051]      FIG. 3A  schematically illustrates a track and hold circuit  300  according to an example embodiment. The circuit  300  is a differential implementation in which a differential value of input signals INP and INM is sampled. A left-hand circuit portion in  FIG. 3A  comprises a pair of transistors  302 A,  304 A, each of which is for example an NMOS transistor. Transistor  302 A has its gate coupled to receive a track signal TRK, and transistor  304 A has its gate coupled to receive a hold signal HLD. One of the main current nodes of transistors  302 A and  304 A, for example their source node, is connected to a node  306 A, which is in turn coupled to ground via a current source  308 A. A second main current node of transistor  302 A, for example its drain, is coupled to a node  310 A, which is in turn coupled to the supply voltage VDD via the main current nodes of a transistor  312 A, which is for example an NMOS transistor. Node  310 A is further coupled to ground via a capacitor  314 A, and provides one of the output signals OUTM of the track and hold circuit. The gate of transistor  312 A and the second main current node of transistor  304 A, for example its drain, are coupled to a node  316 A. Node  316 A is coupled to the supply voltage VDD via a resistor  318 A, and to a further node  322  via the main current nodes of a transistor  320 A, which is for example an NMOS transistor receiving the input signal INP at its gate node. The node  322  is for example coupled to ground via a current source  324 . 
         [0052]    The right-hand circuit portion in  FIG. 3  is for example identical to the left-hand portion, and its components are referenced with the same reference numerals, except that the letter A is replaced by a B. The transistors  302 B,  304 B for example receive the same track and hold signals TRK, HLD as the corresponding transistors  302 A,  304 A in the left-hand portion. The node  310 B provides an output signal OUTP of the track and hold circuit. 
         [0053]    The transistors  302 A and  302 B each have a further node, which could be a bulk node or a back gate node, connected to a positive output of a differential amplifier  326  for receiving a control voltage V CTRLp . The transistors  304 A and  304 B each have a further node, which could be a bulk node or a back gate node, connected to a negative output of the differential amplifier  326  for receiving a control voltage V CTRLM . The differential amplifier  326  for example generates the differential control voltages V CTRLP  and V CTRLM  based on a control voltage V CTRL  applied across its positive and negative input terminals. While not illustrated in  FIG. 3A , the control voltage V CTRL  is for example generated by circuitry similar to the voltage generation circuitry  108  and control block  110  of  FIGS. 1A and 1B . 
         [0054]    In operation, the nodes  316 A and  316 B have voltage signals based on the relative levels of the differential input signals INP and INM. In particular, the amount of the current of the current source  324  that is directed through the branch of transistor  320 A and resistor  318 A, and the amount that is directed through the branch of transistor  320 B and resistor  318 B, is a function of the relative levels of INP and INM, and the size of the transistors  320 A,  320 B. The voltage across the resistors  318 A and  318 B will depend on these current levels. Furthermore, the track and hold signals TRK, HLD are differential timing signals. When the track signal TCK is high and the hold signal HLD low, the current of current sources  308 A,  308 B is directed through the transistors  302 A,  312 A and  302 B,  312 B respectively. Thus the voltages at nodes  310 A,  310 B seen by capacitors  314 A and  314 B follow the voltages at nodes  316 A and  316 B respectively. When the track signal TCK goes low and the hold signal HLD goes high, the current of current sources  308 A,  308 B will be directed through transistors  304 A and  304 B respectively. The gate source voltages VGS of transistors  312 A and  312 B thus become negative such that the voltages at nodes  310 A,  310 B no longer follow the voltages at nodes  316 A,  316 B, and the capacitors  314 A,  314 B hold their voltage levels. 
         [0055]    The sampling time of the circuit  300  is thus determined by the crossing point of the track and hold signals, and this time can be adjusted by the control voltages V CTRLP  and V CTRLM , as will now be described with reference to  FIG. 3B . 
         [0056]      FIG. 3B  is a graph illustrating, with a solid line  350 , the current generated through the transistors  302 A and  302 B during a falling edge of the track signal TRK, and by another solid line  352 , the current generated through transistors  304 A and  304 B during a rising edge of the hold signal HLD. As illustrated, the crossing point between a falling edge of line  350  and the rising edge of line  352  determines the sampling time t s . 
         [0057]    Furthermore, the graph in  FIG. 3B  illustrates, with a dotted line  354 , the current generated through the transistors  302 A and  302 B during a falling edge of the track signal TRK when a positive control voltage VCTRLP is applied to the further node of these transistors.  FIG. 3B  also illustrates, with another dotted line  356 , the current generated through transistors  304 A and  304 B during a rising edge of the hold signal HLD when a negative control voltage V CTRLM  is applied to the further node of these transistors. 
         [0058]    The control voltages V CTRLP  and V CTRLM  in the example of  FIG. 3B  have the effect of lowering the threshold voltage of transistors  302 A,  302 B and raising the threshold voltage of transistors  304 A,  304 B, such that the new crossing point between the current levels is at a time t s ′ later than the time t s . It will be apparent to those skilled in the art that the sampling time could equally be brought forward by a negative value of the control voltage V CTRLP  and a positive value of the control voltage V CTRLM . 
         [0059]    Rather than the differential implementation of  FIG. 3A , a single-ended implementation could be based on the same track and hold circuit of  FIG. 3A , for example using only the transistors  302 A,  304 A,  312 A, current source  308 A, capacitor  314 A, resistance  318 A and differential amplifier  326 . In such an implementation, the signal to be sampled is for example applied as a current directly to the node  316 A. 
         [0060]      FIG. 4  schematically illustrates a circuit  400  according to a further embodiment. As will be described in more detail below, circuit  400  converts a pair of differential input signals CP, CN into a single-ended timing signal CLK, and in particular converts a voltage swing of each of the differential signals, which is for example relatively low, into a voltage swing adapted to the transistors to be controlled. For example, the differential signals CP, CN are low noise signals each having a voltage swing equal to 0.6 V or less. A typical voltage swing of these signals would be around 0.4 V, but in some cases it could be as low as 0.15 V. Such signals are for example provided by CML (current mode logic) elements, which enable high frequency signals, for example of up to 10 GHz or more, to be transmitted across an integrated circuit. A circuit similar to the circuit of  FIG. 4  is described in another French patent application entitled “Circuit and method for signal conversion” (Attorney reference B12565) filed on the same day as the present application in the name of the same applicants and having the same inventors as the present case, the contents of which is hereby incorporated by reference in its entirety to the extent allowable by the law. 
         [0061]    The circuit  400  comprises an upper portion comprising transistors  402 A,  404 A, each for example being an NMOS transistor, and which receive the input timing signals CP and CN respectively at their control nodes. 
         [0062]    Transistor  402 A is coupled in series with a resistor  406 A between the supply voltage VDD and a node  408 A. Transistor  404 A is coupled in series with a resistor  410 A between the supply voltage VDD and the node  408 A. The node  408 A is for example coupled to ground via a current source  412 A. A node  414 A between transistor  402 A and resistor  406 A provides a voltage signal CN VDD  referenced to the supply voltage VDD. A node  416 A between transistor  404 A and resistor  410 A provides a voltage signal CP VDD  referenced to the supply voltage VDD. 
         [0063]    The circuit  400  further comprises a lower portion comprising transistors  402 B,  404 B, each for example being a PMOS transistor, and which receive the input timing signals CP and CN respectively at their control nodes. 
         [0064]    Transistor  402 B is coupled in series with a resistor  406 B between the ground voltage GND and a node  408 B. Transistor  404 B is coupled in series with a resistor  410 B between the ground voltage and the node  408 B. The node  408 B is for example coupled to the supply voltage VDD via a current source  412 B. A node  414 B between transistor  402 B and resistor  406 B provides a voltage signal CN GND  referenced to the ground voltage GND. A node  416 B between transistor  404 B and resistor  410 B provides a voltage signal CP GND  referenced to the ground voltage GND. 
         [0065]    The circuit  400  further comprises a transistor  418 , which is for example a PMOS transistor, coupled in series with a further transistor  420 , which is for example an NMOS transistor. Transistors  418  and  420  each for example have one of their main current nodes, for example their drains, coupled together to an output node  422 . The other main current node of transistor  418 , for example its source, is coupled to receive the voltage signal CN VDD  from node  414 A. The control node of transistor  418  is coupled to receive the voltage signal CP VDD  from node  416 A. The other main current node of transistor  420 , for example its source, is coupled to receive the voltage signal CN GND  from node  414 B. The control node of transistor  420  is coupled to receive the voltage signal CP GND  from node  416 B. 
         [0066]    The output node  422  provides an output timing signal CLK, which in the example of  FIG. 4  is used to control a track and hold circuit, but in alternative embodiments could be used to control other types of circuits such as a mixer. The track and hold circuit comprises a transistor  424 , for example an NMOS transistor, coupled between an input node  426  and an output node  428  of the track and hold circuit. The input node  426  receives an input voltage \T IN  to be sampled. The output node  428  is coupled to ground via a capacitor  430 , and provides an output voltage V OUT . 
         [0067]    The transistors  402 A and  404 B each have a further node, which could be a bulk node or a back gate node, connected to a positive output of a differential amplifier  432  for receiving a control voltage V CTRLP . The transistors  404 A and  402 B each have a further node, which could be a bulk node or a back gate node, connected to a negative output of the differential amplifier  432  for receiving a control voltage V CTRLM . The differential amplifier  432  for example generates the differential control voltages V CTRLP  and V CTRLM  based on a control voltage V CTRL  applied across its positive and negative input terminals. While not illustrated in  FIG. 4 , the control voltage V CTRL  is for example generated by circuitry similar to the voltage generation circuitry  108  and control block  110  of  FIGS. 1A and 1B . 
         [0068]    Operation of the circuit  400  will now be described in more detail with reference to  FIG. 5 . 
         [0069]      FIG. 5  illustrates a timing diagram  502  representing an example of the signals CN (shown by a solid line) and CP (shown by a dashed line). In the example of  FIG. 5 , the signal CN is initially at a high level V H , while the signal CP is at a low level V L . At a sampling time t s , the signal CN goes from the level V H  to the level V L , the signal CP goes from the level V L  to the level V H . The difference between the levels V L  and V H  corresponds to the voltage swing of each of the differential input signals CP and CN. The common mode value of these signals is for example at a level halfway between the supply voltage VDD and ground voltage, for example at VDD/ 2 . 
         [0070]      FIG. 5  illustrates a further timing diagram  504  showing examples of the signals CN VDD , CN GND , CP VDD  and CP GND . 
         [0071]    While the signal CN is high and the signal CP low, the signal CN VDD  is for example at or close to the supply voltage VDD, and the signal CP GND  is for example at or close to the ground voltage. The signal CP VDD  is offset with respect to the supply voltage V DD  by an offset value V A . Similarly, the signal CN GND  is offset with respect to the ground voltage GND by an offset value V B . Indeed, while the input signal CP is low and the input signal CN is high, a relatively high proportion of the current of the current source  412 A will be directed through the resistor  410 A, and a relatively low proportion of the current of the current source  412 A will be directed through resistor  406 A. Similarly, a relatively high proportion of the current of the current source  412 B will be directed through the resistor  406 B, and a relatively low proportion of the current of the current source  412 B will be directed through resistor  410 B. Therefore, the voltage signal CN VDD  will be at substantially the supply voltage level V DD  and the voltage signal CP GND  will be at substantially the ground voltage level. The voltage at node  416 A will however be equal to the supply voltage VDD minus the voltage drop across the resistor  410 A. Assuming that resistor  410 A has a resistance R, the voltage at node  416 A will therefore be equal to VDD-RI A , where I A  is the current flowing through transistor  404 A as a function of the current of current source  412 A and the relative levels of the differential signals CP, CN. Similarly, the voltage at node  414 B will be equal to the ground voltage GND plus the voltage drop across the resistor  406 B. Assuming that resistor  406 B also has a resistance R, the voltage at node  414 B will therefore be equal to GND+RI B , where I B  is the current flowing through transistor  402 B as a function of the current of current source  412 B and the relative levels of the differential signals CP, CN. 
         [0072]    Thus, while the signal CP is low and the signal CN is high, the transistor  418  will see a gate source voltage V GS  of −VA, and will therefore be conducting. The transistor  420  on the other hand will see a V GS  voltage of −V B , and will thus be non-conducting. The voltage at the output node  422  will therefore be at substantially the level of CN VDD , in other words at substantially the supply voltage VDD. 
         [0073]    At the sampling time t s  when the signal CN goes low and the signal CP goes high, the signal CP VDD  changes to a level at or close to the supply voltage VDD, and the signal CN GND  changes to a value at or close to the ground voltage GND. The signal CN VDD  changes to a level offset with respect to the supply voltage V DD  by the offset value V A . Similarly, the signal CP GND  changes to a level offset with respect to the ground voltage GND by the offset value V B . Indeed, while the input signal CP is high and the input signal CN is low, a relatively high portion of the current of the current source  412 A will be directed through the resistor  406 A, and a relatively low proportion of the current of the current source  412 A will be directed through resistor  410 A. Similarly, a relatively high portion of the current of the current source  412 B will be directed through the resistor  410 B, and a relatively low proportion of the current of the current source  412 B will be directed through resistor  406 B. Therefore, the voltage signal CP VDD  will be at substantially the supply voltage level VDD and the voltage signal CN GND  will be at substantially the ground voltage level. The voltage at node  414 A will however be equal to the supply voltage VDD minus the voltage drop across the resistor  406 A. Assuming that resistor  406 A has a resistance R, the voltage at node  414 A will therefore be equal to VDD-RI A , where I A  is now the current flowing through transistor  402 A as a function of the current of the current source  412 A and the relative levels of the differential signals CP, CN. Similarly, the voltage at node  416 B will be equal to the ground voltage GND plus the voltage drop across the resistor  410 B. Assuming that resistor  410 B also has a resistance R, the voltage at node  416 B will therefore be equal to GND+RI B , where I B  is now the current flowing through transistor  404 B as a function of the current of the current source  412 B and the relative levels of the differential signals CP, CN. 
         [0074]    Thus, while the signal CP is high and the signal CN is low, the transistor  418  will see a V GS  voltage of V A , and will therefore be non-conducting. The transistor  420  on the other hand will see a V GS  voltage of V B , and will thus be conducting. Thus the voltage at the output node  422  will be at substantially the level of CN GND , in other words at substantially the ground voltage GND. 
         [0075]    As it will be apparent to those skilled in the art, the level of current provided by the current sources  412 A,  412 B, and the resistance values of resistors  406 A,  410 A,  406 B and  410 B can be chosen to provide a differential gain of the differential signals CP VDD , CN VDD  and CP GND , CN GND  with respect to the differential signals CP, CN. 
         [0076]    The resistance value R of each of the resistors  406 A,  410 A,  406 B and  410 B is for example in the range 100 to 1 k ohms. 
         [0077]    Each of the offset values V A  and V B  is for example equal to between 0.4 V and 0.6 V. 
         [0078]    The sampling time t s  indicated in  FIG. 5  can be time shifted by appropriate values of the control voltages V CTRLP , V CTRLM , in a similar manner to the other embodiments described above. 
         [0079]      FIG. 6  illustrates an analog-to-digital converter (ADC) device  600  comprising circuitry as described in the embodiments above. In particular, the ADC device  600  is a time-interleaved ADC comprising four track and hold circuits TH 1  to TH 4 , each for example comprising the circuitry of  FIG. 1A ,  1 B,  3 A or  4  described above. All of the circuits TH 1  to TH 4  receive a same input voltage signal V IN  to be sampled, for example via an amplifier  602 . Furthermore, each circuit TH 1  to TH 4  receives a corresponding timing signal CLK 1  to CLK 4  from a clock generation circuit  604 . Each timing signal CLK 1  to CLK 4  may correspond to a single clock signal, or a pair of differential timing signals CP and CN. Each of these timing signals has a phase offset with respect to the others, such that the input voltage signal V IN  is sampled at four times the sampling frequency of each circuit TH 1  to TH 4 . 
         [0080]    The output of each circuit TH 1  to THN is coupled to a corresponding analog-to-digital converter ADC 1  to ADC 4 , which also receive the corresponding timing signals CLK 1  to CLK 4 . The digital outputs of these ADCs are coupled to a skew estimation block  606 , which analyses the digital signals and generates a control voltage on lines  608  to be applied to the bulk node or back gate node of one or more transistors in each of the track and hold circuits TH 1  to TH 4 . 
         [0081]    The skew estimation block  606  for example comprises circuitry similar to the blocks  108  and  110  of  FIGS. 1A and 1B  described above. In some embodiments, the control voltages are generated by a digital analysis of the digital signals generated by the converters ADC 1  to ADC 4  to detect the skew, while in other embodiments, the control voltages are generated by first converting the digital signals into analog signals, and then performing an analog analysis of the signals to detect the skew. 
         [0082]    While the example circuit of  FIG. 6  comprises four track and hold circuits TH 1  to TH 4  and four converters ADC 1  to ADC 4 , it will be apparent to those skilled in the art that in alternative embodiments there could be any number. 
         [0083]      FIG. 7  is a cross-section view of an NMOS transistor that is for example used to implement the transistor  102  of  FIGS. 1A and 1B , the transistors  302 A,  302 B,  304 A and/or  304 B of  FIG. 3A , and the transistors  402 A,  404 A,  402 B and/or  404 B of  FIG. 4 . It will be apparent to those skilled in art how the structure could be adapted to a PMOS implementation. 
         [0084]    In the example of  FIG. 7 , the transistor has a fully-depleted silicon on insulator (FDSOI) structure. In particular, the transistor comprises a gate stack  702  formed over a thin film of silicon bordered on each side by isolation regions  704 ,  706 , which are for example shallow trench isolations (STI). The silicon film for example has a thickness of between 5 and 10 nm. The silicon film comprises a central silicon region  708  directly under the gate stack  702  and forming a channel region, and heavily doped n-type regions  710  and  712  on each side of the region  708  forming the source and drain of the transistor. A layer of insulator  714  is formed under the silicon film and extends to the isolation regions  704 ,  706  on each side. Insulator layer  714  is for example a BOX (buried oxide) layer formed of SiO 2 , and which for example has a thickness of between 20 and 30 nm. 
         [0085]    A p-type well (PWELL)  716  is for example formed under the insulator layer  714 , and provides a back gate of the device. A heavily doped p-type region  718  is for example formed adjacent to the isolation region  706  and contacts the PWELL  716 . The region  718  forms the further node of the device that allows the PWELL  716  to be biased by the control voltage V CTRL , or the voltage V CTRLP  or V CTRLM  in the case of the differential implementation of  FIG. 3A  or  4 . It will be apparent to those skilled in the art that in alternative embodiments, the PWELL  716  and P+ region  718  could be replaced by an NWELL and an N+ region in either an NMOS or PMOS implementation. 
         [0086]    An advantage of the FDSOI structure of  FIG. 7  is that a relatively broad range of levels of the control voltage V CTRL  can be applied to the transistor. Indeed, while a more classical MOS transistor with a bulk structure and without the insulator layer  714  would have a limited range of biasing voltages that could be applied to its bulk node, for example typically of around ±0.3 V in the case of an NMOS device, a structure having an insulator layer under the channel region can be biased by up to ±2VDD, in other words up to twice the supply voltage VDD. Thus a greater threshold voltage variation can be applied as compared to the case of a more classical MOS device. 
         [0087]    An advantage of the embodiments described herein is that skew correction can be applied to a transistor in a simple fashion without modifying the timing signal applied to the gate of the transistor, and therefore without the risk of introducing jitter on the timing signal. 
         [0088]    Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. 
         [0089]    For example, while in the circuits represented in the various figures, the high and low supply voltages are at VDD and ground, it will be apparent that any suitable voltages could be used, which may depend on the transistor technology. 
         [0090]    Furthermore, it will be apparent to those skilled in the art that the transistors represented as p-channel MOS transistors could be replaced in alternative embodiments by re-channel MOS transistors, and vice versa. Furthermore, the various transistors could be implemented in alternative transistor technologies rather than MOS, such as bipolar. 
         [0091]    Furthermore, it will be apparent to those skilled in the art that the various features of the embodiments described herein could be recombined, in alternative embodiments, in any combination.