Abstract:
An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of U.S. patent applicant Ser. No. 12/021,241, filed Jan. 28, 2008, titled, “Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus,” which in turn is a continuation-in-part of U.S. patent application Ser. No. 11/262,079, filed Oct. 27, 2005, titled “System and Method for Digital Memorized Predistortion for Wireless Communication” and also claims the benefit of U.S. Provisional Patent Application No. 60/897,746, filed Jan. 26, 2007, titled “Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus,” and U.S. Provisional Patent Application No. 60/898,312, filed Jan. 29, 2007, titled “Power Amplifier Time-Delay Invariant Predistortion Methods and Apparatus,” the continuation-in-part No. Ser. 11/262/079 of which in turn is a continuation of U.S. patent application Ser. No. 10/137,556, filed May 1, 2002, now U.S. Pat. No. 6,985,704, issued Jan. 10, 2006 titled “System and Method for Digital Memorized Predistortion for Wireless Communication,” all of which are incorporated herein by reference. This application also incorporates by reference U.S. patent application Ser. No. 11/799,239, filed Apr. 30, 2007 and its parent U.S. Provisional Patent Application No. 60/795,820, filed Apr. 28, 2006, titled “High Efficiency Linearization Power Amplifier For Wireless Communication”; related non provisional U.S. patent application Ser. No. 11/962,025, filed Dec. 20, 2007, titled “Power Amplifier Predistortion Methods and Apparatus; ” and its parent U.S. Provisional Patent Application No. 60/876,640, filed Dec. 22, 2006, titled “Power Amplifier Predistortion Methods and Apparatus.” 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates systems and methods for using predistortion to linearize the output of a power amplifier (PA), such as those used in wireless transmission systems. More particularly, the present invention uses an adaptive time-delay adjusting methodology to correct the PA&#39;s nonlinearity. More particularly, the invention relates to systems and methods which use a time-delay invariant predistortion architecture to linearize the output of a power amplifier (PA) in wireless transmission systems. 
       BACKGROUND OF THE INVENTION 
       [0003]    In a typical prior art predistortion system for the linearization of power amplifiers, the system typically contains multiple signal transmission paths, such as a reference path and a feedback path. In a predistortion linearization system, when a signal passes through different signal transmission paths, such as a reference path and a feedback path, the occurrence of a timing difference caused by the distinct signal paths is inevitable. This difference, usually referred to as a time delay, presents significant problems with respect to the accuracy of the predistortion correction. These problems are made worse by the fact that the time delay can vary with environmental conditions including temperature, system conditions including signal power level, system aging, and so on. Therefore, it is difficult to measure in a laboratory such an intrinsic time delay parameter, and, moreover, a parameter for correcting the time-delay cannot be designed as a constant. Many efforts have been made in the prior art to compensate for, reduce or eliminate this time-delay. Traditionally, two methods have been used in prior art predistortion circuits to solve the problem created by the time-delay. 
         [0004]    The first is to make a special time-delay cable by measuring and calculating the difference of the same signal passing through different transmission paths so as to compensate the time-delay effect, such as the processing in analog feed-forward predistortion systems. This approach suffers the limitation that the time-delay cable imposes a fixed time-delay that cannot be adjusted despite changes in the signal and environment which naturally occur during the operation of practical systems. 
         [0005]    The second is to use a special digital signal processing (DSP) algorithm and circuitry to calculate and adjust adaptively the time difference of the same signal passing through different transmission paths, and then use the resulting time-delay information to correct the non-linearity of power amplifier. This approach is usually implemented in a digital feedback approach and a wireless environment. However, an extra circuit, typically a latch, and an associated algorithm are needed, and the accuracy of the time-delay calculation is also related to the convergence rate of the algorithm. 
       SUMMARY OF THE INVENTION 
       [0006]    Next-generation wireless communication systems will demand improved transmitted signal quality and improved overall RF transmitter system performance for a variety of broadband and multimedia services. These demands upon advanced RF transmitter systems will be satisfied, at least in part, by power amplifiers with higher power efficiency and higher spectrum efficiency than is currently available. In order to get a better predistortion result, the present invention evaluates the time-delay parameter as a variable that is estimated and calculated by a special algorithm and circuitry. 
         [0007]    More particularly, the present invention uses, in one implementation, one combined predistortion and time-delay lookup table structure to provide correction factors for both the PA&#39;s non-linear distortion and the system&#39;s time-delay. This permits the system and method of the present invention to be a self-calibrating solution for performance improvement and nonlinear correction in wireless RF transmitter systems. 
         [0008]    This design can be conveniently implemented by an elegantly simple circuit structure and can be used for almost all wireless radio frequency (RF) transmission systems to improve both power efficiency and spectrum efficiency. Examples of some applicable RF transmission systems include wireless base-stations, access points, mobile handsets including but not limited to cellular and GPRS protocols, mobile wireless terminals, portable wireless devices, and other wireless communication systems such as microwave and satellite communications. 
         [0009]    The new time-delay invariant method presented herein uses a combination of (i) an adaptive time-delay adjusting methodology to process the PA&#39;s nonlinearity, and, at the same time, (ii) time-delay compensation without the additional circuitry and/or an algorithm tailored for the special time-delay adjustment. This novel algorithm-based methodology can be implemented by a predistortion processing unit that includes a time-delay addressing lookup table that can store and memorize the PA&#39;s non-linearity, time-delay information and other interference in the system such as noise. 
         [0010]    These and other features of the present invention can be better appreciated from the following detailed description, taken in conjunction with the accompanying Figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  illustrates a system and apparatus in accordance with the present invention. 
           [0012]      FIG. 2  illustrates in simplified form one implementation for serial addressing of the lookup table as well as the entry of the accumulated history into the lookup table. 
           [0013]      FIG. 3  illustrates in simplified form an implementation of parallel addressing of the lookup table, which is otherwise as shown in  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0014]    In one implementation of the invention, the entries for the lookup table are developed in accordance with the techniques described in pending U.S. patent application Ser. No. 11/262,079, filed Oct. 27, 2005, and U.S. patent application Ser. No. 11/799,239, filed Apr. 30, 2007, both of which are incorporated herein by reference. It will be appreciated by those skilled in the art that the range of errors which occur in a real-world system are bounded; that is, there is a range which has a minimum value and a maximum value, and in all but rare circumstances the correction factor applicable at the time of any given sample will fall within that range. By selecting a lookup table of appropriate size, and populating the lookup table with appropriate values as determined by the methods in the above-mentioned patent, which are selected over the entire operating spectrum of the PA and associated system, the correction factor which is appropriate for each sampling of the input signal will be one of the values already in the lookup table. Thus, once the lookup table has been fully populated, the correction factors of the present invention do not vary with time; that is, they are time-invariant. Although the size of the lookup table can vary significantly with the particular implementation, and could for some systems be as small as sixteen entries, for more complex implementations such as those appropriate for wireless RF transmission systems the table will have on the order of 2 12  entries or more, and may have significantly more entries depending on the permissible power consumption, cost, and related system factors. For certain implementations, a table size between 2 12  and 2 14  entries has been found to be acceptable. 
         [0015]    In one implementation, the lookup table of the predistortion processing unit, or predistorter, is addressed by a set of time-related addresses that can be structured by a shift register, although parallel addressing may be implemented in some schemes, as discussed in greater detail hereinafter. For present purposes, the shift register technique will be used for illustration. The addressing of the lookup table is based upon a stored-compensation or memory compensation principle that stores information at different time by a vector form and maps the input vector into one of the entries in the lookup table. The set of addressed entries in the lookup table will result in an output signal that is a mapping function of the corresponding input vector. 
         [0016]    Due to the input address vector comprising different time signals, the output signal of the lookup table is actually related to the different time information, including the current signal and previous N transmitted signals, where N&gt;1 and N is an integer. As a result, the signal stored in each entry of the lookup table can be considered as a combination of all past transmitted signals rather than the sole response of the current input signal. Typically, the bit length of the address vector in the lookup table determines the duration of time-delay signal to be covered. 
         [0017]    In order to correct for the PA&#39;s non-linearity in the time-delay environment with a lookup table unit according to the invention, without the use of a latch or other secondary correction circuit, the predistortion algorithm utilizes a function to incorporate the time-delay signal combination. The lookup table stores the non-linear information derived from the PA together with a time-delay factor that is caused by the different signal transmission paths. By appropriately addressing the lookup table in response to a sample, the lookup table provides a correction factor which includes both the appropriate predistortion correction and the appropriate time delay compensation. The output of the lookup table is then combined with the original input signal to provide an input to the PA that results in a linearized output, with substantially no time delay error. 
         [0018]    Due to the memory and store function of the lookup table, the non-linear characteristics of the PA that are to be corrected by the lookup table are not limited by the time-based data. The time-independent feature of the lookup table&#39;s adaptive processing is one benefit of at least some implementations of the addressing arrangement of the lookup table. The addressing of the lookup table is implemented by a set of N-bit vector data that comprises the current input signal as well as the previous N input signals. Therefore, the address of the lookup table is a combination of series of input sequences with the length of N. The longer the address of the lookup table (and therefore the larger the lookup table), the wider the range of time-delay information that the system can accommodate, i.e. the longer duration of time-delay effects that the system can tolerate. However, while a larger table may permit storage of more information, at some point the entries become repetitive, such that a larger table offers diminishing marginal returns, wastes memory resources, and unnecessarily increases power consumption. 
         [0019]    The lookup table of the predistortion processor is based upon the stored-compensation principle that maps a set of input vectors to a real signal output. Since the address of lookup table contains the input information stored from different time, each output signal generated by the lookup table is closely related to the transmitted multi-signals combination. Therefore, based upon the arrangement of the lookup table, the table update entries are also closely related to the combination information of input signals stored from different time points. 
         [0020]    Referring next to  FIG. 1 , an embodiment of the present invention may be appreciated in greater detail. More particularly, the illustrated embodiment includes an Analog Multiplier  11  which receives a modulated RF signal V RF  from the RF modulator portion  10  of the base station, and also receives a predistortion correction signal V p  from a lookup table and related components which can be generally described as a predistortion processor, discussed in greater detail below. In general, the predistortion processor can be thought of as all of the components between the ADC&#39;s  21  and  25  and the DAC  30 . The output of the analog multiplier  11  is provided as the input V in  to the power amplifier (PA)  12 , which in turn transmits an output signal V o  to an Antenna  13 . The RF modulator  10  is typically although not necessarily a quadrature modulator or an orthogonal modulator. It will be appreciated that multiplier  11  can be implemented as multiple multipliers, each associated with one or more quadrature signals. 
         [0021]    An input down-converter circuit  20  receives an idealized reference signal V RF  from modulator in base station, and is biased by a local oscillator  40 , such that it provides an output V d  to an analog-to-digital converter  21 . The ADC  21  converts the signal V d  to digital form (as I and Q signals), whereupon it is provided as one input pair to the Digital Predistortion Processor, and more specifically to variables  221  and  22 Q, respectively. 
         [0022]    A feedback down-converter circuit  26 , also biased by a local oscillator  40 , receives a raw feedback signal V o (t) from the output of the PA, and provides a feedback signal V f  to an feedback ADC  25 . The digital output of the ADC  25  then provides a second input, i.e. feedback signal, to the Digital Predistortion Processor, and more particularly to variables  241  and  240 . The Digital Predistortion, discussed in greater detail below, provides a digital output signal V f  to a DAC  30 , which converts the digital signal to an analog form, where it is combined with the modulated RF signal in the multiplier  11 . 
         [0023]    As shown in  FIG. 1 , address data formers  32 I- 32 Q receive inputs from the ADC  21  I/Q, and are designed to generate the required signal format for a lookup table  33  I/Q. The data formers  32  I/Q address memory units within the lookup tables  33  I/Q, where the lookup table provides separate I and Q outputs to an adder  31 . It will be appreciated that the lookup table  33  can be implemented as one or more lookup tables. The address provided by the address formers  32 I- 32 Q can be considered a lookup-table key or address. 
         [0024]    The predistortion controller lookup tables  33 I- 33 Q are designed memory units to store the predistortion signal for high power amplifier linearization. The predistortion signals in the tables are based on the error generated by a comparison of the ideal signal v d  and the feedback signal v r  and the presented adaptive algorithm. The data stored in the tables  33  I/Q can be updated by adaptive iteration as described hereinafter, and forms digitally indexed data reflecting the nonlinear characteristics of the power amplifier. 
         [0025]    By comparison of AM-AM and AM-PM information between the idealized signal V RF (t) and the feedback signal V o (t), the Digital Predistortion Processor calculates the error in the amplitude and phase components of the output signal V o (t) caused by the non-linear transmission characteristics of the high power amplifier  12 . 
         [0026]    Based on the error information obtained by the foregoing comparison, the predistortion processor, based on the lookup table algorithm disclosed in U.S. Pat. No. 6,985,704, calculates and generates adaptively a compensation signal that is of inverse characteristics with the transform function of the PA  12  to pre-distort the AM-AM and AM-PM distortion caused by the PA  12 . 
         [0027]    The outputs v p  of the predistortion lookup table  33 I- 33 Q are fed to multiplier  11 , after an adder  31  and a digit-to-analog converter  30 , to modify the modulated RF signal from modulator  10 . The output of the multiplier is the required predistortion signal V in (k) that is of an inverse non-linearity with that of the power amplifier  12  to yield a pre-compensation to the input of high power amplifier. 
         [0028]    It will be appreciated by those skilled in the art that there can be a signal difference between two signals, ideal signal V RF  and feedback signal, V o (t), when they arrive at the predistortion controller. The time difference results from the time-delay differences between the two signals, which is caused by the different paths each travels in arriving at the controller. This signal time-delay can vary randomly based on the parameters of the circuits and parts, as well as other environmental factors. The result is that it is difficult to estimate, calculate and adjust for such signal differences in the field application environment. To overcome this issue, the present invention adaptively adjusts for this time-delay through the use of an algorithm taught by the previously cited U.S. Pat. No. 6,985,704. 
         [0029]    The use of the look-up tables  33  permits a memory function to be introduced into at least some embodiments of the present invention. The lookup table of the predistortion controller is based on a stored compensation principle that maps a set of input data into a digital output, and updated adaptively. Based on the stored function, each output signal of lookup table is actually related to both the current and the previously transmitted signal, and therefore has a memory function which compensate not only for the non-linearity of the PA, but also avoids the need for a special time-delay compensation circuit such as typically used in the prior art. 
         [0030]    Based on the predistortion architecture shown in  FIG. 1 , the non-linearity of power amplifier is corrected by the output signal v p  of predistortion processor. The signal v p  is multiplied with the modulated RF signal to generate the predistorted signal as the input of power amplifier. Actually, the input signal of power amplifier is a complex gain signal that can be controllable in the amplitude/envelope and be adjustable in phase. The relation of the input and output can be described as the following complex gain expression 
         [0000]        v   in   =v   RF   v   p   =v   RF   F ( V )   (1)
 
         [0000]    where v p  is the output of predistortion processor generated by a mapping function F of lookup table. Usually, the mapping function F is unknown and is difficult to express mathematically. However, F may be determined adaptively by updating the entries in the lookup table in accordance with the adaptive algorithm to realize all possible mapping that corresponds to the relations with 
         [0000]      {0,1} N →v p .
 
         [0031]    The lookup table therefore maps each set of N-bit input address vector V to a real output V. In fact, the N-dimensional address vector represents the transmitted signal sequences going through power amplifier from the current time though previous N time, expressed by 
         [0000]        V ( k )=( d   1 ( k ), d 2 ( k ), . . . ,  d   N ( k )) T    (2)
 
         [0000]    where each data d i  in above vector V is either 1 or 0, expressed as 
         [0000]        d   i (k)=0 or 1 for 1 ≦i≦N    (3)
 
         [0032]    In one implementation, shown in  FIG. 2 , the address of the lookup table  200  is formed by a serial shift register  205  that addresses each corresponding entry of the lookup table during the predistortion processes. Due to the addressed information being related to the current and previous N transmitted signal, the output signal  210  of the lookup table can be considered as a function of the last N transmitted data, and therefore incorporates a time delay correction element. The lookup table is adaptively updated by combining the adaptive error  215  and a table update  220  in combiner  225 . The arrangement of the lookup table, configured as a predistortion processor, can systematically utilize the combined correction signal for the processing of both non-linearity correction of PA and time-delay compensation, even if time-delay effects are present when the same signal passes through different transmission paths. 
         [0033]    The technique of using a lookup table having combined predistortion and time-delay correction makes unnecessary the use of additional time-delay processing and related circuitries. 
         [0034]    Since the address of the lookup table contains the current and previous transmitted correction information, each output signal from the lookup table is inherently a multi-time information combination that contains rich signal components from the current time to the previous N-time. As a result, the predistortion algorithm has a built-in mechanism to compensate for signal-delay effects. This results in a predistortion processing structure that is significantly simpler, and more effective than traditional solutions. 
         [0035]    In a predistortion architecture with the lookup table as shown in  FIGS. 1 and 2 , the memory table is addressed by its address register. The bit-number length of shift register determines the size of lookup table and therefore the covered time-delay range, i.e., the maximum limit of time-delay effects. Each set of data stored in a lookup table entry has a unique address index. This address index of a data set corresponds to the data set&#39;s sampled time point of the input signal. The address indices are then utilized as time stamps for time calibration purpose of PA&#39;s non-linear error correction calculations. In other words, at each predistortion calculation time point, the predistortion algorithm selects only one set of data from a specific addressed entry as the output of the lookup table for further PA&#39;s non-linearity error correction processing. If the selected output signal is only related to the current-time transmitted signal without any relation with other transmitted signal, then the time-delay, caused by the current transmitted signal passing through different transmission paths, must be considered during the predistortion processing in order to provide an accurate signal matching between the reference and feedback signal. 
         [0036]    The time-delay range to be covered by lookup table is related to the bit number of the address register. For a lookup table with an N-bit address register, the size of lookup table entries is M=2 N−1 . This means that there are M entries in the lookup table, and all the data stored in the entries are the functions of address vectors that cover the current time k to previous k−M+1 time. The set of input address vectors, A, can be expressed as 
         [0000]        A={V ( k ), V ( k− 1), . . . , V ( k−M +1)}  (4)
 
         [0000]    where V(k) is an input address vector at time k, which records M possible predistorted information to PA nonlinearity and each information recoded the current transmitted signal and the time-delay signal components. 
         [0037]    Based on the memory-compensation principle, the combined time-delay lookup table structure involves simple logic operations and signal processing to capture the time-delay of signal passing through different transmission paths. More specifically, due to the time-delay invariant characteristic, this predistortion architecture can process and correct PA non-linearities in a wider dynamic range and without the needs of additional circuitries and algorithms. 
         [0038]    It will also be appreciated by those skilled in the art that, for some embodiments, typically those with larger lookup tables and relatively high sampling rates, a parallel addressing scheme can be used, such as that shown in  FIG. 3 , which is essentially identical to  FIG. 2  except for the use of a parallel input  300  to the lookup table. If the sampled data points are taken close together (i.e., a comparatively fast sampling rate) so that the correction factors for sample t and sample t+1 effectively become identical, then we can use the parallel addressing approach to address the lookup table. In some embodiments, if the size of the lookup table is sufficiently large, and computing power and other device issues are satisfied, then the parallel addressing approach can offer better performance over a serial addressing approach in environments which use a very fast sampling rate. 
         [0039]    Having fully described the invention in detail in detail, including several embodiments and alternatives, those skilled in the art will appreciate that numerous other alternatives and equivalents exist which are within the scope of the present invention. Therefore the invention is intended not to be limited by the above description, but rather only by the appended claims.