Abstract:
Diode strings and electrostatic discharge circuits characterized by low current leakage. Each diode region provides a diode and has first and second regions. The first region is of a first conductive type and formed on a substrate, acting as a first electrode of a diode. The second region is of a second conductive type opposite to the first conductive type, formed in the first region and acting as a second electrode of a corresponding diode. The diodes are forward connected in series to form major anode and cathode of the diode string. An isolation region is of the second conductive type to isolate those diode regions. A bias resistor is connected between the isolation region and a first power line. During normal operation, the voltage of the first power line is not within the range between the voltages of the major anode and cathode.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is a continuation in part of U.S. patent application Ser. No. 11/004,348 filed on Dec. 3, 2004. 
     
    
     BACKGROUND  
       [0002]     The present invention relates in general to diode strings and relevant ESD protection circuits. More particularly, it relates to diode strings and ESD protection circuits characterized by low current leakage during normal operation.  
         [0003]     Among ESD protection devices, proper forward biasing of a diode during an ESD event allows only a small silicon area to be required for effective ESD protection.  
         [0004]     A conventional diode string consists of several diodes connected in series. When coupled between high-voltage and low-voltage power lines, the conventional diode string acts as an ESD protection circuit, clamping the voltage across the power lines and protecting devices from high voltage stress. Nevertheless, a parasitic Darlington amplifier may be formed in the diode string by series-connected parasitic bipolar junction transistors (BJTs), resulting in constant substrate current leakage forward to a substrate. This substrate current leakage becomes more severe as operating temperature or diode count in the diode string increases.  
         [0005]     Conventional solutions to the leakage problem include adding extra circuitry to reduce the current gain of the Darlington amplifier, or physically elimination of the Darlington amplifier.  
       SUMMARY  
       [0006]     An object of the present invention is to reduce current leakage of a diode string during normal operation.  
         [0007]     Another object of the present invention is to provide a diode string and a relevant ESD protection circuit characterized by low current leakage during normal operation.  
         [0008]     A diode string is provided, comprising diode regions, a separation region and a bias resistor. Each diode region provides at least one diode and has first and second polarity regions. The first polarity region is of a first conductivity type on a substrate, acting as a first electrode of a corresponding diode. The second polarity region is of a second conductivity type opposite to the first conductivity type, in the first polarity region, acting as a second electrode of the corresponding diode. The diodes are connected in series to provide a major anode and a major cathode of the diode string. The separation region is of the second conductivity type, separating the diode regions from each other. The bias resistor is connected between the separation region and a first power line. During normal operation the voltage of the first power line is not within the range between the voltages on the major anode and cathode.  
         [0009]     Another diode string characterized by low current leakage is further provided, comprising bipolar junction transistors (BJTs) and a bias resistor. Each BJT has a collector, an emitter and a base. The emitter of a BJT is connected to the base of the following BJT, and the base of the first BJT and the emitter of the last BJT act as two major electrodes of the diode string. The collectors of all the BJTs are coupled to a first power line through the bias resistor. During normal operation the voltage of the first power line is not within the range between the voltages of the major electrodes.  
         [0010]     The bias resistor decreases the collector current in a parasitic Darlington amplifier, thereby depressing the current leakage during normal operation. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0011]     For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which:  
         [0012]      FIG. 1   a  is a cross section of a diode string according to an embodiment of the present invention;  
         [0013]      FIG. 1   b  shows an equivalent circuit for the diode string in  FIG. 1   a  and a newly-defined symbol for a diode string embodying the present invention;  
         [0014]      FIG. 2  shows a circuit with electrostatic discharge (ESD) protection circuits according to the present invention;  
         [0015]      FIGS. 3   a  and  3   b  show two ESD protection circuits, each having an ESD protection trigger circuit according to the invention and connected between power lines VCC and GND; and  
         [0016]     FIGS.  4  to  6  show cross sections of three diode strings embodying the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]      FIG. 1   a  is a cross section of a diode string according to an embodiment of the present invention. In  FIG. 1   a , a diode string  100  is formed on a P-type substrate  102  of a chip, fabricated by, but not limited to, triple-well CMOS process.  
         [0018]     Diode string  100  has diode regions  104 , each providing at least one diode and having a P well  106  and a heavily-doped N region  108 . P well  106  and heavily-doped N region  108  respectively act as an anode and a cathode of a diode. N well  100  surrounds diode regions  104 . Deep N well  112  is deeper than N well  100  and contacts the bottoms of diode regions  104 . N well  100  and deep N well  112  act as a separation region to electrically isolate P wells  106  not only from each other but also from P substrate  102 .  
         [0019]     To form effective electrical contacts, P wells  106  have heavily-doped P regions  114 , N well  100  a heavily-doped N region  116 , and P substrate  102  a heavily-doped P region  118 . The count of these heavily-doped regions is not fixed, depending on how little contact resistance is required by the circuit design. Depending upon the technology of the manufacturing process, heavily-doped regions can optionally be formed with silicide material on their surface to reduce sheet resistance. Isolation material can be formed on the surface of the chip to electrically isolate heavily-doped regions. In the embodiment of  FIG. 1   b , the isolation material is formed and positioned by, but not limited to, shallow trench isolation. Other process, such as local oxidation, can also be applied to form and position isolation material.  
         [0020]     Interconnection on a chip, generally comprising metal wires, contacts and vias, provides connections for devices. Through interconnection, the diodes are forward connected, whereby a cathode of a diode is connected to an anode of a following diode and the anode of the first diode and the cathode of the last diode respectively act as the major anode and cathode of the diode string  100 . The count of the diodes connected in series depends upon the desired threshold voltage of the diode string. If the desired threshold voltage of the diode string is at least 4v and each diode can contribute 0.7v for the threshold voltage, the diode count in the diode string must not be less than 6, since 0.7×6=4.2&gt;4.  
         [0021]     Through interconnection, P substrate  102  is coupled to power line GND. Deep N well  112  and N well  100  are connected to a bias resistor Rb and then coupled to power line VCC. Bias resistor Rb can be, but is not limited to, a poly-silicon resistor or a well resistor.  
         [0022]     During normal operation, when no ESD occurs and the chip is properly powered, the voltage of power line VCC cannot be less than that on the major anode, to maintain junction reverse biasing of a PN between deep N well  112  and P well  106 . In the embodiment of  FIG. 1   a , the voltages of power lines VCC and GND can be the highest and lowest voltage on the chip, respectively.  
         [0023]     The left portion of  FIG. 1   b  shows an equivalent circuit for the diode string in  FIG. 1   a  and the right portion a newly-defined symbol for a diode string embodying the present invention.  
         [0024]     Comparing the equivalent circuit of  FIG. 1   b  with the device structure in  FIG. 1   a , the collector of each NPN BJT is deep N well  112  or N well  110 , the base a P well  106 , and the emitter a heavily-doped N region  108 . Due to the forward connection, the emitter of a BJT is connected to the base of the next BJT. The base of the first BJT acts as the major anode of the diode string  100 , and the emitter of the last BJT as the major cathode of the diode string  100 . All collectors are connected and then coupled to power line VCC through bias resistor Rb.  
         [0025]     The connection of the BJTs in  FIG. 1   b  shows a Darlington amplifier with bias resistor Rb suppressing the collector current through the Darlington amplifier, thereby decreasing current leakage during normal operation. In another aspect, there is no resistor loaded on the current path from the major anode and the major cathode. Therefore, when the voltage difference between the major anode and the major cathode exceeds the threshold voltage of the diode string, the diode string is turned on and effectively conducts current to quickly release voltage stress or trigger another circuit.  
         [0026]     The newly-defined symbol in the right portion of  FIG. 1   b  will be used later to show in circuits possible locations for the diode string according to the invention.  
         [0027]      FIG. 2  shows a circuit with electrostatic discharge (ESD) protection circuits according to the present invention. Diode strings can function alone or cooperate with other ESD protection devices to provide further protection.  FIG. 2  exemplifies, but does not limit, the locations where diode strings are positioned. Diode string S 1  is between a power line VH 1  and an input/output (I/O) pad and diode string S 2  is between a power line VL 1  and the input/output (I/O) pad, both protecting circuitry connected to the I/O pad from ESD damage. Each of the diode strings S 3 -S 6  is connected between two power lines to clamp the voltage difference therebetween, thereby protecting circuitry coupled across two power lines from ESD damage.  
         [0028]     During normal operation, if the voltage supplied to the power line VH 1  exceeds that supplied to the power line VH 0 , and the voltage supplied to the power line VL 1  is lower than that supplied to the power line VL 0 , diode strings S 1 -S 6  are closed. As a result, diode string S 4  is reverse biased while diode strings S 1 -S 3  and S 5 -S 6  are forward biased during normal operation. Based upon the supply voltage arrangement, power line VH 1  can be the same as power line VCC.  
         [0029]     A diode string can function with an ESD protection trigger circuit in an ESD protection circuit.  FIGS. 3   a  and  3   b  show two ESD protection circuits, each having an ESD protection trigger circuit according to the invention and connected between power lines VCC and GND. As shown in  FIGS. 3   a  and  3   b , diode string S 7  connects with resistor R 0  to form an ESD protection trigger circuit connected between power lines VCC and GND. The connection node between diode string S 7  and resistor R 0  can be connected to a trigger node of a primary ESD protection device. The primary ESD protection device is not limited to the bipolar junction transistor (BJT) B 0  shown in  FIG. 3   a , or a field effect transistor such as the metal-oxide-semiconductor transistor (MOS) M 0  shown in  FIG. 3   b . In  FIG. 3   a , the trigger node is the base of BJT B 0 , and, in  FIG. 3   b , the trigger node is the gate of MOS M 0 . When a pulse relatively positive to power line GND occurs on power line VCC, the voltage at the trigger node temporarily rises to trigger the primary ESD protection device and release ESD stress.  
         [0030]     Depending on process technology and layout arrangement, a diode string according to the present invention may differ from the embodiment shown in  FIG. 1   a . FIGS.  4  to  6  show cross sections of three diode strings further embodying the present invention.  
         [0031]     The diode string in  FIG. 4  can be fabricated by triple-well CMOS process. Unlike to the single deep N-well  112  in  FIG. 1   a , there are several deep N-wells  112  together with N-wells  110 . N-wells  110  and deep N-wells  112  have substantially the same voltage since they electrically couple to each other through interconnect and heavily-doped N regions  116 .  
         [0032]     The diode string in  FIG. 5  can be fabricated by bipolarity complimentary metal oxide semiconductor (BICMOS) process that provides shallow and deep trench isolation. In  FIG. 5 , heavily-doped N sinkers  120  and a heavily-doped N buried layer  120  together become a separation region to isolate P-wells  106 . Heavily-doped N sinkers  120  in  FIG. 5  can be interchanged with normal N-wells. Around the separation region has a deep trench  124  and a shallow trench  126 , as shown in  FIG. 5 , to separate N buried layer  120  from other N buried layers. Deep trench  124  and shallow trench  126  are made of isolating material.  
         [0033]     Unlike  FIG. 5 , the diode string in  FIG. 6  has several heavily-doped N buried layers  120  coupled to each other through interconnection and heavily-doped N regions  116 , providing substantially equal voltage.  
         [0034]     The power line connecting to resistor Rb in the embodiments need not have the highest voltage in a chip, but is required to have a voltage not less than that on the major anode.  
         [0035]     While embodiments shown comprise a p substrate, the disclosure is not limited thereto. Those skilled in the art, after comprehending the above embodiments, can easily further derive embodiments with an N substrate and with changes in power supply accordingly. Embodiments with an N substrate are therefore omitted here for lucidity.  
         [0036]     While the invention has been described by way of examples and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto, nor is the invention is limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.