Abstract:
A device for driving a capacitive load, comprising a first switching element responsive to an external control signal for selectively conducting a charge current therethrough to the load, a second switching element responsive to the external control signal for conducting a discharge current from the load and a generator for generating from the discharge current a cutoff signal to be applied to the first switching element to ensure turn-off of the latter.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a device for driving a capactive load. 
     An example of such a capacitive load is a piezoelectric element employed in the printing head of an ink-jet printer. The piezoelectric element in the printing head is supplied with an input pulse signal so that the element is driven for compression and expansion to compress and expand in ink container or chamber containing ink to emit ink droplets in accordance with the input signal. For actuation of the piezoelectric element, a voltage is applied to the element to deform the latter and then the applied voltage is removed or restored to 0 V to take out charges accumulated in the element applied thereto so that the element resumes its original state. The voltage is reapplied to the element and removed therefrom to repeat this cycle. Electrically, this cycle for the compression/expansion drive of the piezoelectric element is accompanied with the charge/discharge operation of the element. 
     Thus, reference will be made to the case where the capacitive load to be driven is, for example, a piezoelectric element. 
     A piezoelectric element can be regarded to be equivalent to a capacitor inasmuch as it is a capactive element, and, for the purpose of driving such an element, a charging circuit and a discharging circuit are required for controlling the timing of charging and discharging the element. FIG. 1 shows, by way of example, the basic structure of a driving device of this kind. Referring to FIG. 1, the driving device may include a control circuit 1, a charging switch S 1 , a discharging switch S 2 , a resistor R L , a capacitive load or piezoelectric element C L , and a power source V cc . In response to the application of a first control signal from the control circuit 1, the charging switch S 1  is turned on, and the piezoelectric element C L  is charged by the power source V cc . For discharging the piezoelectric element C L , on the other hand, the control circuit 1 applies a second control signal for turning off the charging switch S 1  and turning on the discharging switch S 2 . 
     FIG. 2 shows the structure of a practical form of the device in which transistors Q 1  and Q 2  connected at their bases with a driver 2 are used as the charging and discharging switches S 1  and S 2 , respectively. In the strucure shown in FIG. 2, the NPN transistor Q 1  is turned on to charge the piezoelectric element C L , while, the PNP transistor Q 2  is turned on (with simultaneous turn-off of the transistor Q 1 ) to discharge the piezoelectric element C L . The resistor R L  in FIGS. 1 and 2 serves to determine along with the element C L  the time constant for charging and discharging operations of the element. 
     When the transistors Q 1  and Q 2  are used to drive the piezoelectric element C L  in the manner shown in FIG. 2, the base current must be continuously supplied to the transistor Q 1  or Q 2  throughout the period of charging or discharging the piezoelectric element C L  driven by the driving signal applied from the driver 2. Consider now, for example, the transistor Q 1 . When the transistor Q 1  is turned on the start charging of the load C L , the emitter potential V o  of the transistor Q 1  rises sharply up to about the level of V cc  due to the turn-on of the transistor Q 1 . On the other hand, the charge current flows, attenuating according to the time constant determined by the combination of C L  and R L . The transistor Q 1  must be kept turned on until this charge current ceases to flow. Although the base current must be continuously supplied to maintain the on-state of the transistor Q 1 , this base current is now supplied from the power source V cc  due to the rise of the emitter potential V o  up to about the level of V cc . Thus, when the transistors are driven with a TTL level signal, a path is necessarily formed through which the driving current flows from the power source V cc  toward the ground. Such an example is shown in FIG. 3 which illustrates the charging section only. 
     Referring to FIG. 3, there are provided a PNP transistor Q 3  for driving the transistor Q 1  and an NPN transistor Q 4  for driving the transistor Q 3 . The transistor Q 4  operates in response to an input signal IN (of TTL level) and acts as a constant-current circuit so as to limit the current supplied from the power source V cc . The base current I D  of the transistor Q 3  is supplied from the power source V cc  to the ground for turning on the transistor Q 1 . The value of this current I D  must be sufficient to permit operation of the transistor Q 1  in its saturation region. Since the transistor Q 4  operates in the active region, and the voltage value of the power source V cc  is usually as large as about 100 V to 300 V. The power loss at the transistor Q 4  becomes a serious problem especially when, for example, the operating frequency is high or the on-duration is long. Even when the transistor Q 1  is replaced by a PNP transistor, a problem similar to that described above still remains unsolved insofar as such a transistor is included in the device. 
     With a view to obviate the problem pointed out above, a proposal, as, for example, disclosed in Japanese Patent Application Laid-open No. 221517/83, laid-open on Dec. 23, 1983 has been made and already known, in which the transistor Q 1  shown in FIG. 3 is replaced by a thyristor. FIG. 4 shows a structure of a device which employs a thyristor SCR 1  in place of the transistor Q 1 . Employment of the thristor SCR 1  is advantageous in that the power consumption can be reduced since the minimum firing current I gt  of the thyristor is small (or usually in the order of 0.1 mA), and the driving current need not be continuously supplied once the thyristor SCR 1  is fired or turned on. In this case, however, it is necessary to turn on the discharging transistor Q 2  after the charging thyristor SCR 1  has completed a charging operation and turn-off of the thyristor has been detected. This is because, otherwise, the thyristor SCR 1  would be continuously turned on. Therefore, when a thyristor is used as the charging switch, the upper limit of the operating frequency is determined by the time constant of the load current and the turn-off time of the thyristor. Also, the device cannot be operated in such a way as to permit starting of discharge midway of charging. 
     SUMMARY OF THE INVENTION 
     It is a primary object of the present invention to provide a device for driving a capacitive load, in which power consumption can be reduced without requiring a complex circuit structure and the capacitive load can be charged and discharged at a high speed. 
     The present invention is featured by the fact that a switching element is provided in a charging path charging a capacitive load, while, in a discharging path discharging the capacitive load, a switch is provided together with a cutoff circuit generating a cutoff signal to be applied to the switching element to ensure turn-off of the switching element, so that the capacitive load can be driven at a high speed without the necessity for provision of an extra circuit such as a detection circuit detecting turn-off of the switching element. 
     The driving apparatus of the present invention may be used not only with the above-mentioned piezoelectric element, but also with any aother capacitive loads that should be driven at a high speed for charge/discharge operations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram illustrating the principle of operation of a capactitive load driving apparatus. 
     FIGS. 2 to 4 are circuit diagrams of prior art driving apparatus. 
     FIG. 5A is a circuit diagram showing the structure of an embodiment of the present invention. 
     FIG. 5B is a characteristic curve of the thyristor used in the embodiment of FIG. 5A. 
     FIG. 5C shows waveforms of the input signal and the terminal voltage of the capacitive load. 
     FIG. 6 is a circuit diagram showing the structure of another embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 5A shows an embodiment of the device according to the present invention. Referring to FIG. 5A, a unidirectional tetrode thyristor SCR 2  is provided for charging a piezoelectric element C L  and is connected at its anode with a power source V cc  and at its cathode with the piezoelectric element C L , which is a capacitive load, through a resistor R L . The thyristor SCR 2  may have, for example, such a current vs. voltage characteristic as shown in FIG. 5B. The voltage to be applied to the load C L  rises and falls depending upon the time constant R L .C L . Without the resistor R L , the rise and fall of the voltage would be determined by the switching speed of the thyristor SCR 2 . Another resistor R G1  is connected across the cathode gate and the cathode of the thyristor SCR 2  for setting or defining the minimum firing current I gt  and maintaining the withstand-voltage reliability. A diode D 1  is also connected across the cathode gate and the cathode of the thyristor SCR 2  for forming a discharge path for the piezoelectric element C L , and a discharging NPN transistor Q 6  is connected with the cathode gate of the thyristor SCR 2  . In order that the thyristor SCR 2  can be easily triggered even when the cathode potential V K  of the thyristor SCR 2  is not dripped to the ground potential level, the thyristor SCR 2  is arranged for the anode-gate drive, and an NPN transistor Q 5  amplifying an external control pulse signal IN is connected with the anode gate of the thyristor SCR 2  for driving the anode gate with a constant current. The discharging transistor Q 6  operates in response to an output of an inverter 4 which inverts the control signal IN. 
     The operation of the embodiment shown in FIG. 5A will now be described with reference to FIGS. 5A to 5C. 
     In FIG. 5A, when the transistor Q 5  is non-conductive with the control signal IN being at a low level, the thyristor SCR 2  is non-conductive since no gate current is supplied to the cathode gate. Hence, the thyristor SCR 2  is operative along curve C 1 , blocking the voltage V cc  as shown in FIG. 5B. The control signal IN is now made to be at a high level in order to charge the piezoelectric element C L . The transistor Q 5  is turned on with the transistor Q 6  being turned off, so that a current is taken out from the anode gate of the thyristor SCR 2  to turn it on. Thus, the thyristor SCR 2  is now operative along curve C 2  (FIG. 5B), allowing a charge current to flow from the power source V cc  to the element C L  through the thyristor SCR 2 . While the drive current flows continuously throughout the on-duration of the charging thyristor SCR 2 , the value of this drive current need not be large and is such that it is merely larger than that of the minimum firing current I gt  of the thyristor SCR 2 . Thus, the power consumption is low. 
     For the purpose of discharging the piezoelectric element C L , the external control signal IN is returned to its low level thereby turning on the transistor Q 6  with the transistor Q 5  being turned off. Since the transistor Q 6  is operating in its saturation mode at this time, a discharge current flows from the piezoelectric element C L  through the route of C L  →R L  →D 1  →Q 6 , and, at the same time, the cathode gate potential V G  of the thyristor SCR 2  drops substantially to the level of the ground potential. At this time, a forward voltage drop providing a cutoff signal occurs across the diode D 1 , and the cathode potential V K  of the thyristor SCR 2  becomes higher than the cathode gate potential V G  by the amount corresponding to about the forward voltage drop across the diode D 1 , resulting in such a state that the cathode gate and cathode of the thyristor SCR 2  are reverse biased. Consequently, even if the thyristor SCR 2  might be maintained in its on state to continue to supply the charge current, the current flowing through the thyristor SCR 2  is taken out through the cathode gate to be operative along the curve C 1  (FIG. 5B), finally causing turn-off of the thyristor SCR 2 . 
     It will be seen that, according to the embodiment shown in FIG. 5A, it is possible to drive the load at an increased speed and to reduce the power consumption without complicating the structure of the circuit. 
     FIG. 5C shows an example of an external control input pulse signal IN and the terminal voltage V CL  of the load C L . The dotted curve shows a case in which the load C L  is discharged before being charged to V cc . 
     FIG. 6 shows another embodiment of the device according to the present invention. The embodiment shown in FIG. 6 is a partial modification of that shown in FIG. 5A in that the discharging tasnsistor Q 6  in the latter is replaced by a unidirectional triode thyristor SCR 3 . An NPN transistor Q 7  is provided for triggering the thyristor SCR 3 . 
     With the external control input pulse signal at a high level applied to the transistor Q 5 , charging of the piezoelectric element is carried out in a manner similar to what has been described with respect to FIG. 5A embodiment. At this time the transistor Q 7  is conductive to short-circuit the gate of the thyristor SCR 3  to its cathode with a result that the thyristor is caused to remain non-conductive. Now, the control signal is made to be at a low level to turn off the transistors Q 5  and Q 7 , so that a gate current is supplied from the power sourve V B  to the gate of the thyristor SCR 3  to turn it on. This turn-on of the thyristor SCR 3  allows discharge of the piezoelectric load through the diode D 1  and causes a forward voltage drop thereacross, which will be a reverse bias making the potential of the cathode of the thyristor SCR 2  higher than that of the cathode gate. As a result, even if the thyristor SCR 2  remained conductive to pass some current therethrough, such current would be taken out through the cathode gate to the thyristor SCR 3  to finally turn off the thyristor SCR 2 . Turn-off of the thyristor SCR 3  is effected by attenuation of the discharge current or by making the transistor Q 7  conductive. While the thyristor SCR 3  is in its on state, the cathode gate of the thyristor SCR 2  is biased at about the ground potential. Therefore, application of a triggering input to the thyristor SCR 2  would not turn on the thyristor SCR 2 , which prevents undesirable flow of a short-circuit current through the route of V cc  →SCR 2  →SCR 3 . In the embodiment shown in FIG. 5A, a drive current of a value enough to cause operation of the discharging transistor Q 6  in its saturation mode is required. In contrast, in the case of the embodiment shown in FIG. 6, a current of a value equal to about the minimum firing current I gt  of the SCR 3  is merely required for turning on the thyristor SCR 3 , and, thus, the power consumption is made lower than in the case of FIG. 5A. In FIG. 6, a resistor R G2  is connected across the cathode gate and the cathode of the thyristor SCR 2  for setting or defining the minimum firing current I gt  of the thyristor SCR 2 . 
     Although the power source V cc  employed in the aforementioned embodiments of the present invention is a positive voltage source, a negative power source may be employed along with a negative external control input pulse signal for driving the capacitive load. In such a case, it is apparent that the polarity of the transistors Q 5 , Q 6  and Q 7  be reversed, the negative power source V cc  and the load C L  be connected with the cathode and anode of the SCR 3 , respectively, and the diode D 1  be connected between the anode gate and the anode of the SCR 2 , with the collector of the transistor Q 5  connected with the cathode gate of the thyristor SCR 2 .