Abstract:
In order to probe digital signals within a Printed Circuit Board (PCB) a sensor apparatus is implemented adjacent to a signal trace. The sensor apparatus receives crosstalk signalling from the signal trace and is coupled to a probing node capable of being probed by a test apparatus. Hence, in essence, the signal trace itself can be probed via the sensor apparatus and the probing node. The probing node can be implemented on the same layer of the PCB as its corresponding sensor apparatus or on a different layer that is more convenient for probing purposes. Further, the sensor apparatus could be implemented on the same layer within the PCB as its corresponding signal trace or alternatively could be implemented on an adjacent layer that still allows the sensor apparatus to receive crosstalk signalling from the signal trace. With the use of the sensor apparatus in combination with the probing node, it is possible to achieve accurate measurements of signals traversing the signal trace without significantly affecting the signal integrity of the signals traversing the signal trace. This is especially important in high speed designs.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates generally to probing digital signals and more specifically to probing digital signals within Printed Circuit Boards (PCBs).  
         BACKGROUND OF THE INVENTION  
         [0002]    PCBs comprise a number of microelectronic components that are interconnected in order to perform a particular function or set of functions. Examples of components that could be integrated within a PCB include memory devices, Application Specific Integrated Circuits (ASICs) and processing devices such as Digital Signal Processors (DSPs). The components within a PCB communicate with each other via signal traces from a plurality of drivers to a plurality of receivers. As defined herein below, a driver is an apparatus which outputs a signal while a receiver is an apparatus that receives a signal. It should be understood that normally a microelectronic component within a PCB would comprise one or more drivers along with one or more receivers.  
           [0003]    One critical aspect of a PCB design procedure is the testing of the functionality and connectivity of the various signals being transmitted from one microelectronic component to another. The testing of individual signals within the PCB can allow the designer to ensure that the components are operating properly and that all interconnections between specific drivers and receivers are correct. Further, in the case that components are not operating properly, the testing of the signals within the PCB can allow a designer to isolate the problems.  
           [0004]    One technique for testing the signals within a PCB, as illustrated in FIG. 1A, is the use of internal testing circuitry within the components. Within FIG. 1A, a first component  30  comprises functional mode and test mode circuitry  32 ,  34  that are each coupled to a driver  36 . The driver  36  is coupled, via a signal trace  38  to a second component  40  that comprises a receiver  42  coupled to the signal trace  38  and detector circuitry  44  coupled to the receiver  42 . In this case, the first component  30  can operate either in functional mode with functional mode circuitry  32  or in test mode with test mode circuitry  34 , the component  30  selecting between the two modes with the use of a test signal that can be dictated by a test engineer. If operating in test mode, the driver  36  outputs a test sequence as dictated by the test mode circuitry  34  which is received at the receiver  42  and monitored with the use of the detector circuitry  44 . The test mode circuitry could include such testing procedures as Design For Test (DFT) and Built In Self Test (BIST).  
           [0005]    One problem with using internal testing circuitry within the components to test the operation of the PCB is that it is relatively complicated for the test engineer to modify the test software and/or the test parameters within the test mode circuitry  34 . Further, this test mode circuitry  34  requires considerable silicon space which increases the costs of the components and hence the overall PCB. Yet further, since the test mode circuitry  34  is distinct from the functional mode circuitry  32 , it is not possible for the rest engineer to test the components within operation using this technique.  
           [0006]    Another technique for testing the signals within a PCB, as illustrated in FIG. 1B, is the use of probing with a test apparatus. In this case, a driver  50  within a first component  52  is coupled, via a signal trace  54 , to a receiver  56  within a second component  58 , the signal trace  54  further being probed relatively close to the receiver  54  by a test apparatus  60 . With the use of probes on the signal trace  54 , the test apparatus  60  receives a version of the signal being transmitted on the signal trace  54 , thus allowing the designer to monitor the signal during the functional mode of operation. Further, this technique does not require any circuitry modifications within the actual components.  
           [0007]    Unfortunately, there are a number of problems with this technique for testing the signals within a PCB as depicted in FIG. 1B. For one, the signal trace  54  behaves as a transmission line and so when a high speed signal traversing the signal trace  54  is probed with a low capacitance probe from the test apparatus  60 , the probe itself is equivalent to a stub which can cause severe signal integrity problems, such as reflections, on the signal trace  54 . Further, the test apparatus  60  being coupled to the signal trace  54  can result in a significant additional load being added to the signal trace  54 . These problems may result in alterations of the signal traversing the signal trace  54 , thus degrading the signal during testing and not providing accurate results of the signal during normal operating parameters. These problems increase in importance as the signal on the signal trace  54  increases in speed.  
           [0008]    Yet further, the probing of signal traces within a PCB are becoming increasingly difficult, if not impossible. The width of a typical signal trace is decreasing while the distance between signal traces is also decreasing, resulting in an increasingly dense array of signal traces within the PCB that is difficult to probe with currently available couplers. An example of a typical dense array of signal traces is illustrated in FIG. 2 between first and second components  70 ,  72 . In this example, the signal traces are 5 mil (a mil being equal to {fraction (1/1000)} of an inch) in width while the distance between adjacent signal traces is approximately 5 mil. Using currently available couplers, the test apparatus  60  would not be able to probe the signal traces.  
           [0009]    Another difficulty with the probing of signal traces within current PCB designs is the plurality of layers that comprise a PCB. These layers typically include one or more signalling layers as well as a plurality ground layers that surround the signalling layers. This type of design for the PCB can prevent the test engineer from accessing any of the signals that are routed on signal traces inaccessible to the top or bottom of the PCB. To demonstrate this problem, FIGS. 3A and 3B illustrate a sample layer structure for a portion of a PCB (no components illustrated). Within FIG. 3A, the PCB comprises first and second signalling layers  80 ,  82  and first and second ground layers  84 ,  86 . The first ground layer  84  in this example is on top of the first signalling layer  80  while the second ground layer  86  is beneath the second signalling layer  82 . FIG. 3B illustrates the signalling layers  80 ,  82  of FIG. 3A with the layers separated for easier viewing of the signal traces. In this case, it can be seen that none of the signals traversing signal traces within signalling layers  80 ,  82  are accessible at the top or bottom layer of the PCB, these layers being the only layers to which a test engineer can attach coupler for the test apparatus  60 .  
           [0010]    To overcome the above described problem of signal traces that are too narrow to attach probes, it has been well-known to attach small resistors to signal traces so that the test apparatus couplers are able to tap onto the resistors and hence the signal traces. Unfortunately, this solution does not overcome any of the other problems discussed above with reference to probing the signal traces with a test apparatus. For instance, the use of small resistors does not overcome the problem of degrading the signal within the signal trace or the inaccessibility of some signal traces for the test engineer. Additionally, this solution is not practical in high density databus since it would not be possible to implement a resistor for each of the signal traces.  
           [0011]    Hence, there is a need for a new technique for testing signals traversing signal traces of a PCB. Preferably, this technique would not significantly deteriorate the signal traversing the signal traces and would be able to be implemented within dense arrays of signal traces.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention is directed to an apparatus and method for probing digital signals within a PCB. In the present invention, a sensor apparatus is implemented adjacent to a signal trace in order to receive crosstalk signalling from the signal trace. This sensor apparatus is coupled to a node that can be probed by a test apparatus so that, in essence, the signal trace itself can be probed. This node, hereinafter being referred to as a probing node, can be implemented on the same layer of the PCB as its corresponding sensor apparatus or on a different layer that is more convenient for probing purposes. Further, the sensor apparatus could be implemented on the same layer within the PCB as its corresponding signal trace or alternatively could be implemented on an adjacent layer that still allows the sensor apparatus to receive crosstalk signalling from the signal trace.  
           [0013]    One important advantage of the present invention is the ability to achieve accurate measurements of signals traversing signal traces within a PCB without significantly affecting the signal integrity of the signals traversing the signal trace; this being especially important in high speed designs. This is done through the use of crosstalk signalling between the signal trace and the sensor apparatus, the sensor apparatus generating weak pulses equivalent to those on the signal trace that can be probed by a test apparatus. Another advantage of some implementations of the present invention is the ability to probe signals that would normally not be able to be probed due to the density of the signal trace array or due to the multiple layer implementation of the PCB.  
           [0014]    In a first broad aspect, the present invention is an arrangement including a primary signal trace, a victim signal trace local to the primary signal trace and a probing node coupled to the victim signal trace. In this aspect, the primary signal trace operates to communicate signals between first and second components, the victim signal trace operates to receive crosstalk signalling from the primary signal trace; and the probing node is adapted for probing by a test apparatus.  
           [0015]    The present invention, according to a second broad aspect, is an arrangement including first and second differential signal traces, at least one victim signal trace local to one of the first and second differential signal traces and at least one probing node coupled to the at least one victim signal trace. According to this aspect, the first and second differential signal traces operate to communicate signals between first and second components, the victim signal trace operates to receive crosstalk signalling from the differential signal trace that is local and the at least one probing node is adapted for probing by a test apparatus.  
           [0016]    In other aspects, the present invention is a Printed Circuit Board (PCB) incorporating one of the arrangements of the first and second aspects. In one case, the PCB comprises a single layer that includes the primary signal trace (the differential signal traces in the second aspect), the victim signal trace and the probing node. In another case, the PCB comprises at least first and second layers, the first layer including the primary signal trace (the differential signal traces in the second aspect) and the victim signal trace and the second layer including the probing node. In this situation, the second layer is one of primary and secondary layers within the PCB and the probing node is coupled to the victim signal trace through a via coupling the first and second layers. In yet a further case, the PCB comprises at least first and second adjacent layers, the first layer including the primary signal trace (the differential signal traces in the second aspect) and the second layer including the victim signal trace. In this aspect, the victim signal trace is approximately located within the second layer at the same location as the primary signal trace (the one of the differential signal traces in the second aspect) is located within the adjacent first layer.  
           [0017]    According to a third broad aspect, the present invention is a method of probing a signal trace that operates to communicate signals between first and second components. The method includes receiving crosstalk signalling from the primary signal trace and routing the crosstalk signalling to a node that is adapted for probing by a test apparatus.  
           [0018]    According to a fourth broad aspect, the present invention is an arrangement including means for communicating signals between first and second components, means for receiving crosstalk signalling from the means for communicating signals, the crosstalk signalling corresponding to the signals being communicated, and means for probing the crosstalk signalling by a test apparatus.  
           [0019]    Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]    The invention will now be described with reference to the following figures, in which:  
         [0021]    [0021]FIGS. 1A and 1B illustrate block diagrams of well-known testing techniques within a PCB;  
         [0022]    [0022]FIG. 2 illustrates a simple example of a PCB with a dense array of signal traces;  
         [0023]    [0023]FIGS. 3A and 3B illustrates an overall view and a more detailed view respectively of a sample multi-layer PCB;  
         [0024]    [0024]FIG. 4 illustrates a possible implementation of the present invention within a PCB;  
         [0025]    [0025]FIG. 5 illustrates an equivalent circuit for two transmission lines in parallel;  
         [0026]    [0026]FIGS. 6A and 6B illustrate possible implementations of the present invention within multi-layer PCBs;  
         [0027]    [0027]FIGS. 7A, 7B and  7 C illustrate possible implementations of the present invention within multi-layer PCBs in which a sensor apparatus is on a separate layer to its corresponding signal trace;  
         [0028]    [0028]FIGS. 8A and 9B illustrate alternative embodiments for the sensor apparatus of any one of FIGS. 4, 6A,  6 B,  7 A,  7 B and  7 C; and  
         [0029]    [0029]FIG. 9 illustrates a possible implementation of the present invention within a PCB utilizing differential signals. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0030]    Embodiments of the present invention are directed to probing techniques within PCBs. As will be described herein below, the designs of PCBs according to the present invention utilize sensor apparatus to detect signals traversing signal traces within a PCB and further connect the sensor apparatus to corresponding probing nodes that allow a test apparatus to monitor these detected signals. These designs, in essence, allow a test apparatus, such as a Hewlett Packard (HP) high speed tester, to probe the actual signal traces within the PCB.  
         [0031]    [0031]FIG. 4 illustrates a possible implementation of the present invention within a PCB. In this implementation, the PCB comprises a signalling layer  90  which includes a databus  92  of four signal traces, one of the signal traces being signal trace  94 . As depicted within FIG. 4, each of the signal traces of the databus  92  has a corresponding sensor apparatus  96  adjacent to it, the sensor apparatus  96  of signal trace  94  having a higher scaled view  98  also depicted. As shown in this higher scaled view  98 , the sensor apparatus  96  of FIG. 4 comprises a victim signal trace  100  that is in parallel with the signal trace of interest, signal trace  94  in this case, and a node  102  coupled to the victim signal trace  100 . The victim signal trace  100  receives crosstalk signalling from the corresponding signal trace of the databus  92 , this crosstalk signalling in ideally designed circumstances being a relatively accurate approximation of the digital signals traversing the signal trace  94 . A more detailed description of the crosstalk signalling will be described herein below with reference to FIG. 5.  
         [0032]    The node  102  of FIG. 4 can be utilized in a number of different manners depending upon the circumstances. In one implementation, the node  102  could be a probing node with which a test apparatus can attach a coupler in order to monitor the signals detected with the victim signal trace  100 , these signals hereinafter being referred to as victim signals. In this case, the PCB of FIG. 4 must not have any further layers implemented with the signalling layer  90  that cover the node  102 , the dimensions of node  102  must be sufficient for a coupler from the test apparatus to be connected and the distance between signal traces of the databus  92  must be sufficient to fit the required dimensions of the nodes  102  along with appropriate isolation of the nodes  102  from the other signal traces. In another implementation in which the PCB of FIG. 4 is a multi-layer PCB, the node  102  could be a via node to which a via couples the sensor apparatus  96  to a probing node on another layer of the PCB as will be described in detail herein below with reference to FIGS. 6A and 6B. This situation is necessary if a test apparatus does not have access to layer  90  since it is not the primary or secondary layers (i.e. the top or bottom layers). Further, it might be necessary if the distance between the signal traces is not sufficient to implement the nodes  102  as probing nodes.  
         [0033]    In the particular implementation illustrated within FIG. 4, the widths of the signal traces of the databus and the victim signal traces  100  are 5 mil while the distance between the signal traces of the databus  92  and their corresponding victim signal traces  100  is also approximately 5 mil. These are approximately the minimum dimensions that are currently achievable within PCBs.  
         [0034]    [0034]FIG. 5 illustrates an equivalent circuit for portions of two transmission lines in parallel, this circuit representing the coupling relationship between the signal trace  94  and the corresponding victim signal trace  100  of FIG. 4. As illustrated in FIG. 5, a driver  110  is coupled to a receiver  112  via a first transmission line  114  while a second transmission line  116  is in parallel with the first transmission line  114 . To represent portions of the first and second transmission lines  114 ,  116 , the equivalent circuit of FIG. 5 comprises a first transmission line inductor  118  and a first transmission line resistor  120  coupled in series between first and second nodes  122 ,  124  respectively within the first transmission line  114 ; a first transmission line grounding resistor  126  coupled between the second node  124  and ground; a second transmission line inductor  128  coupled in series with a second transmission line resistor  130  between first and second nodes  132 ,  134  respectively within the second transmission line  116 ; a grounding resistor  136  coupled between the second node  134  and ground; and a crosstalk capacitor  138  coupled between the second nodes  124 ,  134  within the first and second transmission lines respectively.  
         [0035]    As illustrated in FIG. 5, the inductance of the inductors  118 ,  128  are represented by L 11 Δz and L 22 Δz respectively, where L 11 , L 22  are the inductance of the segments of the transmission lines  114 , 116  being represented and Δz is the length of the segments of the transmission lines  114 ,  116  being represented. The resistance of resisters  120 ,  130  are represented by R 11 Δz and R 22 Δz respectively, where R 11 , R 22  are the self-resistance of the segments of the transmission lines  114 ,  116  being represented. The resistance of resisters  126 ,  136  are represented by G 11 Δz and G 22 Δz respectively, where G 11 , G 22  are the admittance of the segments of the transmission lines  114 ,  116 . The capacitance of capacitor  138  is represented by C m Δz, where C m  is the mutual capacitance between the two transmission lines  114 ,  116 . The mutual inductance between the two transmission lines  114 ,  116  can be seen to be the combination of the inductance of inductors  118 ,  128 , represented on FIG. 5 as L m Δz.  
         [0036]    The second transmission line  116  within FIG. 5 can receive both forward and reverse crosstalk signals from the first transmission line  114  while signals are traversing the first transmission line  114 . Herein below is a description of the mathematical approximations of the voltage levels within the second transmission line  116  that result from forward and reverse crosstalk signalling while signals traverse a first transmission line  114 .  
         [0037]    For the forward crosstalk signals, the resulting voltage on the second transmission line  116  can be approximated using the following formula:  
               V   F     =       K   F     ·   l   ·            V   inc            t                 (   1   )                               
 
         [0038]    where V F  is the voltage on the second transmission line  116  due to the forward crosstalk, 1 is the length of the entire second transmission line  116 , V inc  is the incident voltage level on the first transmission line  114  and K F  is a forward crosstalk coefficient that can be approximated with the following formula:  
               K   F     =     -     [         L   m       2   ·     Z   0         -         C   m     ·     Z   0       2       ]               (   2   )                               
 
         [0039]    where Z 0  is the characteristic impedance. Looking at formulae (1) and (2), it can be seen that the voltage on the second transmission line  116  as a result of forward crosstalk signalling will be approximately equal to the change in the voltage on the first transmission line  114  multiplied by the length of the second transmission line  116  and further multiplied by the factor K F  that is based upon the mutual inductance and capacitance between the transmission lines  114 ,  116 . It is noted that since the inductance and capacitance portions of this factor K F  are differential, it is possible to minimize this factor K F  by adjusting these mutual inductance and capacitance levels, thus minimizing the forward crosstalk signalling detected by the second transmission line  116 .  
         [0040]    For the reverse crosstalk signals, the resulting voltage on the second transmission line  116  can be approximated using the following formula: 
           V   R   =K   R   ·V   inc   (3) 
         [0041]    where V R  is the voltage on the second transmission line  116  due to the reverse crosstalk, V inc  is the incident voltage level on the first transmission line  114  and K R  is a reverse crosstalk coefficient that can be approximated with the following formula:  
               K   R     =       1     2   ·     T   prop         ·     [         L   m       2   ·     Z   0         +         C   m     ·     Z   0       2       ]               (   4   )                               
 
         [0042]    where T prop  is the unit transmission line delay time of propagation of the voltage V inc  on the first transmission line  114 . Looking at formulae (3) and (4), it can be seen that the voltage on the second transmission line  116  as a result of reverse crosstalk signalling will be approximately equal to the voltage on the first transmission line  114  multiplied by the factor K R  that is based upon the mutual inductance and capacitance between the transmission lines  114 , 116  and the time of propagation of the voltage V inc  on the first transmission line  114 . It is noted that, the inductance and capacitance levels within the factor K R  are additive and this factor K R  is directly proportional to the level of combined inductance and capacitance between the transmission lines  114 , 116  and is inversely proportional to the time of propagation of the signal traversing the first transmission line  114 .  
         [0043]    Now referring back to the possible implementation of the present invention depicted within FIG. 4, it should be understood that the crosstalk signalling detected at the victim signal trace  100  due to signals traversing the signal trace  94  is comparative to the crosstalk signalling detected at the second transmission line  116  due to signals traversing the first transmission line  114 . In ideal cases, the designer would eliminate the forward crosstalk signalling detected on the victim signal trace  100  by adjusting the mutual inductance and capacitance between the signal trace  94  and the victim signal trace  100 . With this elimination, the crosstalk signalling detected at the victim signal trace  100  would be an approximate representation of the signals traversing the signal trace  94 .  
         [0044]    There are numerous factors that influence the effectiveness of the victim signal trace  100  to detect an accurate representation of the signals traversing the signal trace  94 . For one, the length of the victim signal trace and the distance between the signal trace  94  and victim signal trace  100  can improve the strength of the reverse crosstalk signalling and hence increase the accuracy of detection for the signals traversing the signal trace  94 . Through the lengthening of the victim signal trace  100  and the decreasing of space between the signal trace  94  and the victim signal trace  100 , one could increase the mutual inductance and capacitance between the signal traces  94 , 100  and therefore allow for stronger reverse crosstalk signalling. It is noted that the increase in strength of the reverse crosstalk signalling due to lengthening the victim signal trace  100  can be saturated such that the lengthening of the victim signal trace  100  after a threshold point, does not increase the strength of the reverse crosstalk signalling significantly. Further, it is noted the minimum possible distance between the signal trace  94  and the victim signal trace  100  is defined by PCB manufacturers&#39; limitations. Currently, this limitation is approximately 4.5-5 mil.  
         [0045]    Other factors that influence the effectiveness of the victim signal trace  100  to accurately detect signals traversing the signal trace  94  are the rise time at the edge of digital signals and the strength of the driver that is used to generate the signals traversing the signal trace  94 . Both of these factors are not controlled by the PCB designer, but must be considered when designing the sensor apparatus of the present invention. For instance, a relatively slow rise time at the edge of digital signals may require an increase in the length of the victim signal trace  100  and/or a decrease in the distance between the signal traces  94 ,  100  to compensate. Further, the use of a strong voltage driver, such as a CMOS driver, or a weaker current driver, such as an LVDS driver, could force a PCB designer to adjust the sensor apparatus  96  of the present invention accordingly.  
         [0046]    Essentially, an increase in the length of the victim signal trace  100  a decrease in the distance between the signal traces  94 ,  100 , an increase in the rise time of the signals traversing the signal trace  94  and an increase in the strength of the driver all will lead to an increase in reverse crosstalk signalling and, hence should lead to an increased accuracy at the victim signal trace  100  of the signals traversing the signal trace  94 .  
         [0047]    Although a possible design of a PCB according to the present invention was described herein above with reference to FIG. 4, the present invention should not be limited to this embodiment. In particular, implementations are possible within multi-layer PCB designs as will be described herein below with reference to FIGS. 6A and 6B; modifications with respect to the location of the sensor apparatus  96  relative to the signal trace  94  are possible as will be described herein below with reference to FIGS. 7A through 7C; modifications with respect to the design of the victim signal trace  100  are possible as will be described with reference to FIGS. 8A and 8B; and further alternative embodiments of the present invention are possible, one of which will be described herein below with reference to FIG. 9 for differential signal designs.  
         [0048]    [0048]FIG. 6A illustrates a possible implementation of the present invention within a multi-layer PCB. As described above, the node  102  of the sensor apparatus could be a via node that is coupled through a via to another layer in a multi-layer PCB, the other layer being either the primary or secondary layer of the PCB and further having sufficient space to place a probing node of sufficient dimensions for a test apparatus. As depicted in FIG. 6A, the layer  90  previously described above with databus  92  and sensor apparatus  96  is a signalling layer within a multi-layer PCB that further comprises a first grounding layer  140  implemented below the layer  90 , a second grounding layer  142  implemented above the layer  90  and a test probe layer  144  implemented above the second grounding layer  142  as the primary layer for the PCB. As depicted in FIG. 6A, the test probe layer  144  comprises a plurality of test probe apparatus  146  that are coupled to the sensor apparatus  96  with vias that run between layers  90  and  146  through layer  142 . Also illustrated in FIG. 6A is a higher scale view  148  of the test probe apparatus  146 , each of the cest probe apparatus  146  comprising a via node  150  that is coupled to the respective via node  102  within the respective sensor apparatus  96  and a probing node  152  that is coupled to the via node  150 . In this embodiment, each of the probing nodes  152  are of sufficient dimensions to allow a test apparatus to probe the node with the use of a coupler. With the implementation of FIG. 6A, victim signals detected at any of the victim signal traces  100  can be monitored by a test apparatus that attaches couplers to the probing nodes  152 .  
         [0049]    It should be noted that the present invention should not be limited to the multi-layer implementation of FIG. 6A. The layer structure of the PCB could be considerably different from that illustrated in FIG. 6A while still utilizing the present invention. For one, the test probe layer  144  could be a separate layer utilized exclusively for test probe apparatus or, alternatively, could be a layer utilized for other purposes, such as signalling, but that is accessible to couplers of a test apparatus. Further, additional layers could be added within the PCB and those layers that are depicted could be removed. In one alternative, one or more additional signalling layers could be implemented between the signalling layer  90  and the test probe layer  144 . In this case, it might not be possible to route the victim signals directly from the sensor apparatus  96  to the test probe apparatus  146  due to the interference of other signal traces. In this case, it would be necessary to route the victim signals from the sensor apparatus to another signalling layer and across the other signalling layer to a point where the victim signals can be routed to the test probe layer  144  through vias. In other cases, it might be necessary to do routing on more than one other signalling layer in order to route the victim signals to the test probe layer  144 .  
         [0050]    [0050]FIG. 6B illustrates another possible implementation of the present invention within a multi-layer PCB. In this implementation, the test probe apparatus  146  are replaced with test probe apparatus  160  which, as illustrated in a higher scale view  162 , comprise the via node  150 , the test probe node  152  and an amplifier/Pulse Recovery (PR) unit  164  coupled between the nodes  150 , 152 . In this case, the victim signals have an amplification and pulse recovery operation performed on them prior to being probed by the test apparatus. The pulse recovery operation can be utilized to generate proper digital signals corresponding to the victim signals that are detected. In particular, this might be necessary if the forward crosstalk signalling is not significantly mitigated since unmitigated forward crosstalk signalling will result in the victim signals comprising a series of pulses rather than a relatively accurate approximation of the signals traversing the corresponding signal trace. It should be noted that this amplifier/PR unit  164  could be implemented in many different manners, such as within an FPGA, ASIC, DSP or other circuitry. Further, it should be noted this unit  164  could be implemented as two separate devices and/or further operations could also be included within the unit  164  in some alternative embodiments.  
         [0051]    [0051]FIGS. 7A, 7B and  7 C illustrate possible implementations of the present invention within multi-layer PCBs in which the sensor apparatus  96  is on a separate layer to its corresponding signal trace  94 . This might be required in cases in which the distance between signal traces within a databus are not sufficient for the implementing of sensor apparatus between the signal traces. Within FIG. 7A, the PCB comprises the signalling layer  90  and a sensor apparatus layer  170  implemented above the layer  90 . In this case, as depicted within a higher scale view  172  of the sensor apparatus  96  within layer  170  and the signal trace  94 , the victim signal trace  100  is adjacent to the signal trace  94  within the vertical plane, hereinafter referred to as broadside coupling. The victim signal trace  100 , similar to the description above for the implementation of FIG. 4, receives crosstalk signalling from the signal trace  94 , this crosstalk signalling allowing the sensor apparatus  96  to generate an approximation of the actual signals traversing through the signal trace  94 .  
         [0052]    It should be noted that the sensor apparatus layer  170  could be a layer exclusively used for sensor apparatus or could alternatively be used for other functions as well. For instance, the implementation of FIG. 7B replaces the sensor apparatus layer  170  with a second signalling layer  174 , layer  174  comprising signal traces  176  along with at least one sensor apparatus  96 . In another alternative, the implementation of FIG. 7C replaces the sensor apparatus layer  170  of FIG. 7A with a grounding layer  178 . In this case, the sensor apparatus  96 , as illustrated within a higher scale view  182 , is surrounded by an isolation region  180  which isolates the sensor apparatus  96  from the ground plane of the grounding layer  178 .  
         [0053]    It should be further noted that any of the implementations of FIGS. 7A through 7C could be implemented as described previously with reference to FIG. 4 in which the node  102  is a probing node or alternatively, as described previously with reference to FIGS. 6A and 6B, in which the node  102  is a via node which is coupled to a probing apparatus on one of the primary or secondary layers.  
         [0054]    [0054]FIGS. 8A and 8B illustrate alternative embodiments for the sensor apparatus depicted within the implementations of FIGS. 4, 6A,  6 B,  7 A,  7 B and  7 C. These two alternative implementations of the sensor apparatus illustrate two possible modifications within the sensor apparatus in order to ensure impedance matching. Impedance matching is advantageous since reflections could be generated on the victim signal trace  100  if there is impedance mismatching, these reflections being transferred to the corresponding signal trace  94  and thus deteriorating any signals traversing this signal trace. As depicted in FIG. 8A, the sensor apparatus comprises the victim signal trace  100  with the node  102  coupled to one end and a termination device  190  coupled to the other end. As depicted in FIG. 8B, the sensor apparatus comprises the victim signal trace  100  with a first termination device  192  coupled to one end and a second termination device  194  coupled to the other end, the node  102  further being coupled to the victim signal trace  100 . In the cases depicted in FIGS. 8A and 8B, the termination devices are resistors, though it should be recognized that alternative devices that would result in impedance matching could be utilized.  
         [0055]    Although a number of implementation of the present invention have been described herein above, these specific implementations should not limit the scope of the present invention. For example, rather than utilizing single ended signal traces, many current PCBs utilize differential signal traces. The use of differential signal traces becomes increasingly necessary as the speed of the signals increases, though it should be noted that the use of differential signal traces significantly increases the required distance (currently approx. 25 mil) that is used to separate the individual differential signal traces. FIG. 9 illustrates a possible implementation of the present invention within a PCB utilizing differential signals. Within FIG. 9, the PCB comprises a signalling layer  200  that includes differential signal traces  202 ,  204 . The differential signal traces  202 ,  204  each have a sensor apparatus  96  adjacent to them. This is illustrated in detail within a higher scale view  206  of the sensor apparatus  96  within FIG. 9.  
         [0056]    It should be understood that alternative implementations to the PCB of FIG. 9 are possible. For instance, only a single sensor apparatus  96  could be used rather than two as described with reference to FIG. 9. This implementation is possible if the common noise from the signal traces  202 , 204  is within the designer&#39;s acceptable range. In the case of two sensor apparatus  96  being utilized as depicted in FIG. 9, the differential sensor apparatus allow the test apparatus to cancel the common noise. Further, alternatives as described with reference to FIGS. 6A, 6B,  7 A through  7 C,  8 A and BB can also be made in circumstances in which differential signal traces are utilized.  
         [0057]    There are numerous advantages of the present invention over previous techniques for testing signals within a PCB. For one, the use of implementations of the present invention can reduce the load being added to the signal traces. The present invention does not eliminate the loading on the signal traces that are being probed but can significantly reduce such loading compared to traditional probing techniques in which the couplers of the test apparatus are directly coupled to the signal traces of interest. This reduces within the present invention the decline in signal integrity caused by the probing of signal traces within a PCB compared to previous probing techniques.  
         [0058]    Further, as described above, some implementations of the present invention can be implemented within PCB designs that have an extremely high dense array of signal traces. Yet further, embodiments of the present invention allow for vias that are not exposed on the primary or secondary layers, commonly referred to as micro-vias, to be probed and allow buried signal traces that cannot be traced by traditional methods to be probed.  
         [0059]    Persons skilled in the art will appreciate that there are alternative implementations and modifications possible to use an apparatus similar to that described above to reduce peak power periods within data signals, and that the above implementation is only an illustration of this embodiment of the invention. The scope of the invention, therefore, is only to be limited by the claims appended hereto.