Abstract:
A bias circuit for preventing excessive emission from light emitting diodes includes a switch connected to power. A light emitting diode connects to the switch output. Two bias current legs, electrically connected in parallel, interpose the light emitting diode and ground. A fault comparator connects to the bias current legs and a logic OR gate. Four fault comparators can be implemented, each detecting a unique fault condition. The logic OR gate has an output connected to the input of the switch.

Description:
FIELD OF THE INVENTION  
         [0001]    The invention is directed towards the field of light emitting diodes, particularly towards biasing circuits for light emitting diodes.  
         BACKGROUND  
         [0002]    Products containing light emitting diodes (LED) which emit light in the visible or infrared range must conform to eye safety requirements, IEC 60825-1. If the optical flux that can impinge on a user&#39;s eye exceeds the standard, the device must be labeled an eye safety hazard, which is undesirable. This requirement applies not only during normal operation of the circuit but when single faults occur in the circuit.  
           [0003]    [0003]FIG. 1 illustrates a prior art eye safety circuit. This simple circuit uses a fuse. When the bias current exceeds the eye safety requirement, the fuse blows.  
           [0004]    [0004]FIG. 2 illustrates another prior art eye safety circuit. This circuit is a retriggerable transistor circuit that shunts current away from the LED when the current exceeds a design threshold.  
           [0005]    The prior art circuits detect when the LED current is higher than some preset current. However, the circuit in FIG. 1 cannot detect a fault in which the LED cathode is connected to GROUND, and the fuse cannot be readily integrated onto an integrated circuit. The circuit in FIG. 2 can detect a fault where the LED cathode is shorted to Ground, but this circuit would be difficult to implement on a standard CMOS integrated circuit process.  
         SUMMARY  
         [0006]    A bias circuit for light emitting diodes includes a switch connected to power. A light emitting diode connects to the switch output. Two bias current legs, electrically connected in parallel, interpose the light emitting diode and ground. A fault comparator is connected to the bias current legs and a logic OR gate. Four fault comparators can be implemented, each detecting a unique fault condition. The logic OR gate having an output connects to the input of the switch.  
           [0007]    A first fault comparator has a negative input connected to the output of the bias current legs node VL, and a positive input receives a voltage signal VL−. This detects a short circuit from node VL to ground.  
           [0008]    A second fault comparator has a positive input connected to one of the two bias current legs and a negative input connected to the other of the two bias current legs. This differentially compares the current between the two bias current legs.  
           [0009]    To detect additional fault conditions, a bias resistor interposes the two bias current legs and ground. An amplifier has a positive input receiving a voltage reference signal, a negative input connected to the bias resistor, and an output connected to both bias current legs. A third comparator has a negative input receiving a voltage signal VREF+, having a positive input connected to the bias resistor. The third comparator detects when a high voltage on VB occurs. A fourth comparator has a negative input connected to the bias resistor and a positive input receiving a voltage signal VREF−. The fourth comparator detects when a low voltage on VB occurs.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 illustrates a prior art eye safety circuit.  
         [0011]    [0011]FIG. 2 illustrates another prior art eye safety circuit.  
         [0012]    [0012]FIG. 3 illustrates an embodiment of the present invention.  
         [0013]    [0013]FIG. 4 illustrates an alternate embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0014]    [0014]FIG. 3 illustrates an embodiment of the present invention  10 . A digital circuit  12  receives the output from two comparators  14 ,  16 . Each comparator  14 ,  16  tests for a different fault. A switch  18 , e.g. a field effect transistor, interposes VDD and a light emitting diode (LED)  20 . The input of the switch  18  receives the output of the digital circuit  12 . Two bias current legs  22 ,  24 , connected in parallel, connect between the LED  20  and Ground potential. Each bias current circuit  22 ,  24  contains a current sensing resistor  22 B,  24 B and a current magnifying circuit  22 A,  24 A connected in series.  
         [0015]    The negative input of comparator  14  is connected to node VL (the cathode of the LED  20 ), while the positive input of  14  is connected to a DC voltage source, VL−. The positive input of comparator  16  is connected to the negative end of current sensing resistor  24 B, while the negative input of  16  is connected to the negative end of current sensing resistor  22 B.  
         [0016]    Under normal conditions, the circuit operates in the following manner. When the voltage at node VL is higher than voltage VL−, the output of comparator  14  is LOW. The bias current legs  22 ,  24  are designed so that the current in bias leg  22  is much greater than the current in bias leg  24 . The current in the LED  20  will be the sum of these two currents,  
           I   LED   =I   A   +I   B , where  I   A   &gt;&gt;I   B   Equation 1  
         [0017]    The values of current-sensing resistors  22 B,  24 B are chosen so that the voltage across current sensing resistor  22 B (VR 1 ) is slightly smaller than voltage across current sensing resistor  24 B (VR 2 ). Since I A &gt;&gt;I B , the value of current sensing resistor  24 B must be much larger than the value of current sensing resistor  22 B to meet this requirement. With VR 1 &lt;VR 2 , the output of comparator  16  is LOW. With the output of both comparators LOW, the output of the digital circuit, which has an OR function, will also be low. Therefore, switch  18  will be ON, and current will flow through the LED  20 . Note that provisions have to be made in the digital circuit  12  to assure that the circuit biases up in the correct state when power is first applied to the circuit.  
         [0018]    The circuit  10  is designed to detect single faults that would cause the current flowing through the LED  20  to increase by a significant amount over the intended value. There are two single fault conditions that this embodiment detects. If the current magnifying circuit  22 A fails in such a manner that its output current increases significantly, voltage VR 1  will be larger than voltage VR 2 , the output of comparator  16  will go high, the output of the digital circuit  12  will go high, and the switch  18  will be turned off. If current magnifying circuit  24 A fails in such a manner that its output current increases significantly, the additional voltage drop across current sensing resistor  24 B will limit the additional current so that the resulting increase in the total LED current is small enough so that the eye safety limit is not exceeded. If voltage at node VL is much lower than expected (lower than VL−) such as could occur if node VL were shorted to ground, the output of comparator  14  will go high, the output of the digital circuit will go high, and the switch will be turned off.  
         [0019]    [0019]FIG. 4 illustrates an alternative embodiment of the present invention  11 . A digital circuit receives the output from four comparators  14 ,  16 ,  26 ,  28 . Each comparator tests for a different fault condition. A switch  18 , e.g. a field effect transistor, interposes VDD and a light emitting diode (LED)  20 . The input of the switch  18  receives the output of the digital circuit. Two bias current legs  22 ,  24 , connected in parallel, connect between the LED  20  and a bias resistor  30 . The opposing end of bias resistor  30  is connected to ground. The bias current legs  22 ,  24  are connected to each of the comparators  14 ,  16 ,  26 ,  28 . For comparator  14 , the negative input is connected to the output of the bias current legs  22 ,  24  and the positive input receives DC voltage VL−. For comparator  16 , the positive and negative inputs are connected differentially to nodes within the bias current legs  22 ,  24 . For comparator  26 , the negative input receives a DC voltage VREF+, while the positive input is connected to node VB. For comparator  28 , the negative input is connected to the input of the bias current legs  22 ,  24  and the positive input receives DC voltage source VREF−. The positive input of amplifier  32  receives DC voltage source VREF. The output of amplifier  32  is connected to the bias current legs  22 ,  24  while the negative input is connected to node VB.  
         [0020]    Each bias current leg  22 ,  24  includes a current-sensing resistor  22 B,  24 B interposing the LED  20  and a current magnifying circuit  22 A,  24 A. A transistor  22 C,  24 C, e.g. a field effect transistor, has a drain connected to the current magnifying circuit, a gate connected to the amplifier output, and a source connected to the bias resistor (RB)  30 .  
         [0021]    All components were implemented as an integrated circuit except for the LED  20  and the bias resistor  30 . The digital circuit  12  has the functional logic corresponding to a four-input OR gate.  
         [0022]    During normal operation (no fault), the amplifier  32  and the transistors  22 C,  24 C form a feedback loop that forces node VB to be at the same voltage as the reference voltage signal VREF. Thus, the combined current through these transistors will be I=VREF/RB, where RB is the value of the bias resistor  30 . If the transistors are of the same size, then their currents, I 1  and I 2 , will be the same.  
         [0023]    Currents I 1  and I 2  are scaled up by the current magnifying circuits  22 A,  24 A so that the output currents I A  and I B  are in the ratio of M:N, where M&gt;&gt;N. These bias currents flow through the current-sensing resistors  22 B,  24 B and the combined current flows through the LED  20  and the switch  18 . The current through the LED  20  (and hence its light output) is set by selecting the value of the bias resistor (RB)  30  and the value of VREF. Equation 2 describes the value of the current flowing through the LED  20  for the case where transistors  22 C,  24 C are the same size:  
           I   LED =( VREF/RB )( M+N )/2  Equation 2  
         [0024]    The circuit is designed to detect single faults that would cause the current flowing through the LED to increase by a significant amount over the intended value. There are four single fault conditions that this embodiment detects. First, when voltage at node VB is much lower than intended, this can occur when the bias resistor RB  30  is a short circuit to ground. Second, when voltage at node VB is much higher than intended, this can occur when the voltage signal VREF is higher than expected. Third, when the ratio of currents I A  and I B  is much larger than intended, this can occur when the current magnifying circuit  22 A malfunctions and has a higher current multiplication factor than intended. Fourth, when voltage VL is much lower than expected, this can occur when node VL is shorted to ground potential.  
         [0025]    Each of these faults is detected by one of the comparators. The comparators  14 ,  16 ,  26 ,  28  drive the digital circuit  12 . The digital circuit  12  is designed to turn off the switch  18  if a fault is detected, e.g. a comparator indicates a logic HIGH output. Turning off switch  18  turns off the LED current. Fault detection occurs as follows. The positive input of comparator  14  is biased at a voltage VL− that is lower than voltage signal VL such that when a low voltage on VL occurs, the output of comparator  14  goes HIGH. The negative input of comparator  26  is biased at a voltage VREF+ that is higher than VREF such that when a high voltage on node VB occurs, the output of comparator  26  goes HIGH. The positive input of comparator  28  is biased at a voltage VREF− which is slightly lower than the voltage VREF such that a short circuit from node VB to ground will cause the output of comparator  28  to go HIGH. The values of current sensing resistors  22 B,  24 B are chosen such that for normal operation, the voltage at node V 1  is slightly higher than the voltage at node V 2 . Because current I A  is much larger than I B , the value of current sensing resistor  24 B will be much larger than the value of current sensing resistor  22 B.  
         [0026]    When current magnifying circuit  22 A has a fault that causes its output current to be too high, the voltage at node V 1  will be lower than the voltage at node V 2 , and the output of comparator  16  goes HIGH. When current magnifying circuit  24 A has a fault that causes its output current to be higher than the desired value, the increase in current will be limited by the relatively high value of current sensing resistor  24 B. Hence, the incremental increase in the LED current will be small and the eye safety limit will not be exceeded.