Abstract:
A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present application relates generally to a control mechanism within an electronic circuit device, and more particular the present application relates to a control mechanism for modifying the frequency of a digital circuit clock signal in such a way that mitigates noise signals such as power supply noise. 
         [0003]    2. Description of the Related Art 
         [0004]    It is often desirable to change the frequency of the clock driving a digital circuit in response to software load variations, power and temperature constraints, etc. Typically, this is done by stopping the activity in the processor, changing the clock frequency, and then restarting the activity in the processor. Processor activity is stopped prior to the frequency change because large, sudden changes in that frequency typically cause a very large instantaneous variation in the current consumed by the processor. This large instantaneous current variation in turn typically creates a large perturbation in the power supply of the processor, a perturbation that can be fatal to the operation of the digital circuit. 
         [0005]    It would thus be desirable to provide a mechanism for changing the frequency of the clock provided to a large digital circuit (such as a processor) while limiting the maximum amount of current variation (di/dt) associated with the clock frequency change. 
       SUMMARY 
       [0006]    The current invention provides a mechanism for changing the frequency of the clock provided to a large digital circuit (such as a processor) while limiting the maximum amount of current variation (di/dt) associated with the clock frequency change. This invention thus enables controlled frequency changes in large digital circuits while creating a limited amount of frequency change-induced noise on the digital circuit power supply. The current invention is thus directed to a technique to mitigate noise spikes in an electronic circuit when modifying the operating frequency of such circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneous changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal. The frequency filter receives a desired frequency as a digital word at an input of the filter. The desired frequency word and the current frequency word are compared to generate a boolean result indicating that the new desired word is greater than the current word, matches the current word, or is less than the current word. This result is weighted by the proportional and integral filter coefficients, Kp and Ki, respectively, and is then combined with the current frequency word to create a new frequency output word. This new frequency output word is applied to the synthesizer at the feedback portion of the DPLL as a new divide ratio request so that the feedback path is a smooth ramp instead of a series of non-continuous, discrete signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The novel features believed characteristic of the illustrative embodiments are set forth in the appended claims. The illustrative embodiments themselves, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of the illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
           [0008]      FIG. 1  depicts a digital phase-locked loop (digital PLL or DPLL) architecture with fractional-N frequency synthesis. 
           [0009]      FIG. 2  depicts a filter capable of generating frequency ramps. 
           [0010]      FIG. 3  depicts use of a feedback ramp control signal used to vary the clock frequency generated by a digital PLL in a non-discreet, substantially linear fashion such that di/dt induced noise is mitigated during frequency adjustment/variation. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0011]    The current invention provides a mechanism for changing the frequency of the clock provided to a large digital circuit (such as a processor) while limiting the maximum amount of current variation (di/dt) associated with the clock frequency change. This invention thus enables controlled frequency changes in large digital circuits while creating a limited amount of frequency change-induced noise on the digital circuit power supply. The current invention is thus directed to a technique to mitigate noise spikes in an electronic circuit when modifying the operating frequency of such circuit. The primary components of the invention are as follows:
       digital circuit to be driven: large, clocked digital circuit (such as a processor)   frequency synthesizer: a device that synthesizes a frequency given a control input (digital phase locked loop, or DPLL)   frequency filter: a device that generates a control input for the frequency synthesizer with desirable characteristics       
 
         [0015]      FIG. 1  shows a block diagram of a digital PLL  100  (DPLL). This circuit synthesizes an output frequency  110  that is an integer or fractional multiple of its input reference clock frequency  120 . This output frequency  110  is the clock signal for an electronic circuit (not shown). The main elements of the DPLL circuit  100  are a phase and frequency detector (PFD)  130 , a loop filter  140 , a digitally controlled oscillator (DCO)  150 , a forward sigma-delta modulator  160 , a fractional-N sigma-delta modulator  170 , and a feedback divider  180 . The circuit operates by using the PFD  130  to compare arriving reference clock edges to feedback clock edges, where the reference clock edges are provided by a stable external source at  120  and the feedback clock edges are derived from the output DCO frequency  190 , typically after that frequency has been passed through the divider  180  to form feedback clock  200 . The phase relationship (leading or lagging) between the reference clock  120  and the feedback clock  200  is processed in the loop filter  140 , producing a control word that is applied to the DCO  150 . Because it is impractical to realize a DCO with sufficient bits of precision to enable the full control word to be applied directly to the DCO  150 , the least significant control bits (LSB) are applied as a dithered, fractional sub-word  210  to the DCO  150 , where the forward sigma-delta modulator  160  is used to create the appropriate dithering sequence to represent that sub-word. If a non-integer multiple of the reference clock frequency is desired as the output, the feedback divider can be modulated using the fractional-N delta sigma modulator block  170 , creating an effective non-integer feedback divide ratio. 
         [0016]    The operating frequency of the DPLL can be changed in several ways: the reference clock frequency could be changed; the feedback divide ratio could be changed; or a new digital word could be applied to the DCO itself. In each of these scenarios, the PLL would typically unlock and then re-establish lock. The more significant the frequency change that is initiated, the greater the induced power supply noise will be. 
         [0000]    Furthermore, the dynamics of re-acquiring lock will generally not be well-controlled. 
         [0017]    The fundamental behavior that is leveraged in the frequency filter (described below) is the ability to create a digitally controlled frequency trajectory. The active current in the system (i) is proportional to the system capacitance (c), voltage (v), and operating frequency (f): 
         [0018]    i αcvf 
       Therefore, 
       [0019]    di/dt α cv df/dt 
         [0000]    Because di/dt is proportional to df/dt, managing df/dt enables the management of di/dt. 
         [0020]      FIG. 2  shows the frequency filter  200 , the device that generates a control input for the frequency synthesizer  100  of  FIG. 1  such that the rate of change of output frequency  110  can be limited, thereby enabling far more predictable and stable power supply behavior for the digital circuit driven by the synthesizer. In operation, the desired frequency is applied as a digital word to the input  210  of the frequency filter  200 . The desired frequency word  210  and the current frequency word  220  are compared at  230  and a 2-bit result is generated, indicating that the new word is greater than the current word, matches the current word, or is less than the current word. This result is weighted by the proportional and integral filter coefficients, Kp and Ki, respectively, at  240  and  250  and is then combined at  260  with the current frequency word  220  to create a new output frequency word. This output word is applied to the synthesizer as a new divide ratio request that is presented as the 16-bit division ratio value that is input to fractional-N delta sigma modulation block  170  previously described with respect to  FIG. 1 . An intervening saturation logic block  275  is provided to enforce minimum and maximum frequency control words that can be applied to the divider controls. As long as the control word  270  is between the externally supplied minimum and maximum frequency limits  280 , the saturation logic control word at the output  285  of the saturation logic block  275  is the same as the control word  270 . Once either of those limits has been reached, however, the output frequency control word  220  is held at the relevant limit such that hardware constraints on the system clock are maintained. 
         [0021]    Once this new frequency request  220  is applied to the DPLL  100  of  FIG. 1 , the DPLL will lock to the new frequency subject to the time constant of the DPLL itself. With sufficiently small steps in changes made to the frequency control word (controllable by setting the Kp and Ki coefficients of the frequency filter  200 ) and sufficiently slow update rates, the action of the frequency filter will dominate the dynamics of synthesizer behavior, thus enabling the management of di/dt (and hence induced power supply) associated with frequency change requests. 
         [0022]    In this filter, Ki represents the integration constant of the filter and it indicates how quickly the filter can ramp from one frequency to another. Kp is the proportional constant of the filter, and for normal operation it can be set to 0, but it also can be used as a damping factor for the response of the frequency filter. 
         [0023]    Thus, the frequency filter  200  creates a frequency request ramp that is used as the feedback path signal for the DPLL (which advantageously eliminates use of discrete, stair-stepped frequency requests in such feedback path) to thus provide a relatively constant di/dt when the frequency is being changed in response to a requested frequency change. This relatively constant di/dt directly results in reduced/mitigated noise spikes that would otherwise be generated using a discreet, stepped feedback signal. 
         [0024]      FIG. 3  shows the response of a system including a DPLL and a frequency filter to frequency ramp requests. An initial frequency speed-up request is issued at the end of area A; this results in the output frequency (ff_freqout) request word  310  changing from constant to steadily slewing upward (area B). Simultaneously, the period of the output clock as depicted at  320  steadily shrinks in a well-controlled manner. Once the new frequency is achieved, the PLL operates with no further changes, and the ff_freqout indicator word  310  is stable (area C). At the end of this plateau in the ff_freqout word  310 , a request to reduce the clock frequency is received and the DPLL again smoothly increases its clock period to achieve the new target (area D), then is stable once more (area E). Because the frequency slew is smooth, the induced di/dt (and hence power supply dv/dt) due to the frequency change will be small, making the minimum cycle time produced by the synthesizer predictable; this enables the synthesizer to be used to clock the attached digital circuit safely throughout the frequency change event. The ramp is effectively implemented by generating a succession of closely spaced digital words that are used as frequency multipliers. The illusion of a smooth frequency ramp is achieved when the relevant bandwidth of the frequency synthesizer is such that the frequency stepping falls out of the system bandwidth. In other words, the output frequency is not allowed to move under the dynamics of the DPLL, but instead will follow the closely spaced digital input words, and interpolate the frequencies between those words. If the spacing is too large, interpolation will not be smooth and result in a staircase effect on the output frequency, with the corresponding increase in undesirable di/dt. 
         [0025]    The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
         [0026]    The description of the illustrative embodiments have been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the illustrative embodiments in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the illustrative embodiments, the practical application, and to enable others of ordinary skill in the art to understand the illustrative embodiments for various embodiments with various modifications as are suited to the particular use contemplated.