Abstract:
A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to semiconductor fabrication process, and more particularly relates to a semiconductor fabrication process that eliminates undesired stringer formations. 
       BACKGROUND OF THE INVENTION 
       [0002]    As the trend of miniaturization in the field of semiconductor manufacturing continues, new challenges arise in maintaining acceptable productions yields. In particular, many semiconductor devices such as SRAM devices rely on complimentary components, that is, components that must be processed (e.g. doped) separately within a device. One such example would be nFET and pFET transistors, which are implanted with different species during the semiconductor fabrication process. The nFET and pFET devices are typically separated by a shallow trench isolation (STI) region. For the purposes of improving the circuit density, it is desirable to minimize the width of the STI region. However, as the width of the STI region decreases, there is a greater chance for an unintended polysilicon stringer to form above the STI region, thereby electrically shorting the components on each side of the STI region, and causing a fatal defect within the semiconductor device. Therefore, what is needed is a semiconductor fabrication process overcomes these issues, while not requiring an increase in the width of the STI region. 
       SUMMARY OF THE INVENTION 
       [0003]    According to the present invention, a method is provided for processing complimentary components within a semiconductor device, wherein the complimentary components are comprised of a first component and a second component, comprising the steps of: applying a first mask layer over polysilicon on the first component; 
         [0000]    processing the second component;
 
applying a complimentary mask layer over the second component;
 
removing the first mask layer; removing the polysilicon over the first component; processing the first component; and
 
removing the complimentary mask layer, thereby processing the first and second components without the formation of a stringer.
 
         [0004]    Additionally, according to the present invention, a method is provided wherein the step of applying a complimentary mask layer comprises the step of performing a deposition process followed by the step of performing a planarizing process. 
         [0005]    Still further, according to the present invention, a method is provided wherein the step of performing the deposition process comprises Chemical Vapor Deposition. 
         [0006]    Still further, according to the present invention, a method is provided wherein the step of performing the deposition process comprises Physical Vapor Deposition. 
         [0007]    Still further, according to the present invention, a method is provided wherein the step of performing the deposition process comprises Atomic Layer Deposition. 
         [0008]    Still further, according to the present invention, a method is provided wherein the step of performing the deposition process comprises electroless plating. 
         [0009]    Still further, according to the present invention, a method is provided wherein the step of performing the deposition process comprises electrochemical plating. 
         [0010]    Still further, according to the present invention, a method is provided wherein the step of performing the planarizing process comprises a technique selected from the group consisting of reflow, spincoating, and planarizing. 
         [0011]    Still further, according to the present invention, a method is provided wherein the step of removing the complimentary mask layer comprises performing a solvent strip process. 
         [0012]    Still further, according to the present invention, a method is provided wherein the step of removing the complimentary mask layer comprises performing a plasma etch process. 
         [0013]    Additionally, according to the present invention, a method is provided wherein the step of removing the complimentary mask layer comprises performing a chemical etch process. 
         [0014]    Additionally, according to the present invention, a method is provided wherein the step of removing the complimentary mask layer comprises performing a thermal degradation process. 
         [0015]    Additionally, according to the present invention, a method is provided wherein the step of applying a first mask layer comprising applying a mask layer comprised of resist, and the step of applying a complimentary mask layer comprises applying a mask layer comprised of a material selected from the group consisting of methyl vinyl ketone (MVK), poly-methacrylic acid (PMAA), silsesqioxane (SSQ), polyallylamine (PAA), and hexafluoroalcohol (HFA). 
         [0016]    Still further, according to the present invention, a method is provided wherein the step of applying a first mask layer comprising applying a mask layer comprised of resist, and the step of applying a complimentary mask layer comprises applying a mask layer comprised of a material selected from the group consisting of carbosiline and polyborane. 
         [0017]    Also according to the present invention, a method is provided for processing a complimentary transistor pair, wherein the complimentary transistor pair comprises an nFET and a pFET, the nFET and the pFET being separated by a shallow trench isolation region, comprising the steps of: 
         [0000]    applying a first mask layer over polysilicon on the nFET, such that the first mask layer overlaps a portion of the shallow trench isolation region;
 
implanting the pFET;
 
applying a complimentary mask layer over the pFET, such that the complimentary mask layer is self aligned with the first mask layer;
 
removing the first mask layer;
 
removing the polysilicon over the nFET;
 
implanting the nFET; and
 
removing the complimentary mask layer, thereby processing the complimentary transistor pair without the formation of a stringer.
 
         [0018]    Additionally, according to the present invention, a method is provided wherein the step of applying a complimentary mask layer comprises applying a mask layer comprised of a material selected from the group consisting of methyl vinyl ketone (MVK), poly-methacrylic acid (PMAA), silsesqioxane (SSQ), polyallylamine (PAA), and hexafluoroalcohol (HFA). 
         [0019]    Additionally, according to the present invention, a method is provided wherein the step of removing the first mask layer comprises performing a chemical etch process. 
         [0020]    Additionally, according to the present invention, a method is provided wherein the step of applying a complimentary mask layer over the pFET comprises Physical Vapor Deposition. 
         [0021]    Additionally, according to the present invention, a method is provided wherein the step of applying a complimentary mask layer over the pFET comprises Chemical Vapor Deposition. 
         [0022]    Additionally, according to the present invention, a method is provided wherein the step of removing the complimentary mask layer over the pFET comprises performing a plasma etch process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    The structure, operation, and advantages of the present invention will become further apparent upon consideration of the following description taken in conjunction with the accompanying figures (FIGs.). The figures are intended to be illustrative, not limiting. 
           [0024]    Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. Block diagrams may not illustrate certain connections that are not critical to the implementation or operation of the present invention, for illustrative clarity. 
           [0025]    In the drawings accompanying the description that follows, often both reference numerals and legends (labels, text descriptions) may be used to identify elements. If legends are provided, they are intended merely as an aid to the reader, and should not in any way be interpreted as limiting. 
           [0026]    Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG). 
           [0027]      FIGS. 1A-1F  illustrate prior art semiconductor fabrication steps. 
           [0028]      FIGS. 2A-2D  illustrate semiconductor fabrication steps of the present invention. 
           [0029]      FIG. 3  is a flowchart indicating process steps of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    For the purposes of providing background, the relevant prior art semiconductor fabrication steps will be briefly described in  FIGS. 1A-1F . Note that some layers in these cross-sectional views may be omitted for clarity, if they are not pertinent to the present invention. 
         [0031]    Referring now to  FIG. 1A , a portion of a semiconductor device  100  is shown. Semiconductor device  100  comprises a silicon substrate  102 . The substrate  102  comprises an nFET region  104  (corresponding to an nFET component) and a pFET region  108  (corresponding to a pFET component), that are separated from each other by a shallow trench isolation (STI) region  108 . The STI region  108  is filled with a deposited dielectric. Above the substrate  102  is a layer of polysilicon  110 . Note that in practice, there may be multiple layers between substrate  102  and polysilicon layer  110 , such as metal layers, gate oxides, and additional polysilicon layers. These layers are known in the art, but are eliminated from these drawings for the sake of clarity. Above polysilicon layer  110  is a hardmask layer  112 . Above the hardmask layer, two resist images  114 A and  114 B are shown. Resist images  114 A and  114 B may be formed via well-known lithographic methods. 
         [0032]      FIG. 1B  shows semiconductor device  100  after the process steps of removing the hardmask  112 , typically via an etch process. The hardmask only remains where it was protected by the resist images ( 114 A and  114 B of  FIG. 1A ). Once the hardmask is removed, the resist images are also removed, leaving two hardmask areas  112 A and  112 B. 
         [0033]      FIG. 1C  shows semiconductor device  100  after the process steps of applying mask layer  118  over the polysilicon  110 , removing the mask layer  118  from the area above the pFET region  106  (via lithography) and removing the polysilicon  110  from the area above the pFET region  106 , leaving only polysilicon portion  110 C (which was protected by hardmask  112 B) above the pFET region  106 , as part of the so-called “gate stack” for the pFET. This step also leaves the polysilicon portion  110 A intact, above the nFET region  104 . At this point in the fabrication process, the pFET region  106  is typically implanted with the desired species, while the nFET is protected by mask layer  118 . 
         [0034]      FIG. 1D  shows semiconductor device  100  after the process steps of removing mask layer  118 , in preparation for processing the nFET region  104 . However, before processing the nFET region  104 , the pFET region  106  must be protected by applying pFET mask  122  over the pFET via lithographic methods, as is shown in  FIG. 1E . 
         [0035]    Still referring to  FIG. 1E , it is shown that pFET mask  112  may unintentionally overlap polysilicon region  110 A, as is highlighted by region  124 . Overlap  124  is undesirable, because when polysilicon region  110 A is removed, a stringer is formed in the area below the overlap  124 . 
         [0036]      FIG. 1F  shows semiconductor device  100  after the process step of removing the polysilicon layer  110 A, leaving only polysilicon area  10 B, which forms part of the nFET “gate stack”, and polysilicon portion  128 , which is known in the industry as a “stringer.” The stringer  128  is formed because it was protected by the pFET mask during the polysilicon removal process. This is followed by the process step of removing the pFET mask  122 . Due to the overlap ( 124  of  FIG. 1E ), a polysilicon stringer  128  was formed over the STI region  108 . The polysilicon stringer serves to electrically short the nFET and pFET devices of the finished semiconductor product, often rendering a fatal defect in it. 
         [0037]    Having now described the prior art process, and illustrating the problem of stringer formation that is inherent with it, the present invention will now be described in the following figures. 
         [0038]      FIGS. 2A-2D  illustrate semiconductor fabrication steps of the present invention. 
         [0039]    Referring now to  FIG. 2A , a portion of a semiconductor device  200  is shown. Note that similar elements may be referred to by similar numbers in which case, typically the last two significant digits may be the same. For example, silicon substrate  202  of  FIG. 2A  is similar to silicon substrate  102  of  FIG. 1A . 
         [0040]      FIG. 2A  starts after  FIG. 1C  of the prior art process that was described previously. In  FIG. 2A , a complimentary mask  232  is applied above pFET region  206  prior to removal of mask layer  218 , serving to protect pFET region  206 . This is in contrast to the prior art process illustrated in  FIG. 1D , where the mask layer  118  is removed prior to protection the pFET region  106 . 
         [0041]    Because the polysilicon layer  210 A and mask layer  218  are both present when the complimentary mask  232  is applied, the complimentary mask  232  “self aligns” to the nFET layers ( 210 A and  218 ) and the possibility of overlap (see  124  of  FIG. 1E ) is eliminated. The complimentary mask preferably has good planarizing characteristics such that it can be applied, and then planarized to be flush with the nFET layers ( 210 A and  218 ) as is shown in  FIG. 2A . The planarizing of the complimentary mask  232  can be accomplished with various techniques, including, but not limited to, reflow, controlled deposition, and spincoating. 
         [0042]    There are various suitable techniques for applying the complimentary mask, including, but not limited to, CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), iPVD (Ionized Physical Vapor Deposition), plating (electroless, electrochemical), spincoating, and evaporation. ALD (Atomic Layer Deposition) may also be used. 
         [0043]      FIG. 2B  shows semiconductor device  200  after the process step of removing mask layer  218 , in preparation for processing the nFET region  204 . Protection of pFET region  206  is already in place via complimentary mask  232 . 
         [0044]      FIG. 2C  shows semiconductor device  200  after the process steps of removing the polysilicon layer  210 A, leaving only polysilicon region  210 B, as part of the nFET “gate stack,” shown as reference  213 . The nFET region  204  may then be implanted with the desired species while the pFET region  206  is protected by complimentary mask  232 . 
         [0045]      FIG. 2D  shows semiconductor device  200  after the process step of removing complimentary mask  232 . Various methods may be used to remove complimentary mask  232 , including, but not limited to, solvent strip, plasma etch, wet chemical etch, thermal degradation, UV degradation, or combinations thereof. The present invention achieves the desired result of having no stringer over the STI region  208  (compare with  128  of  FIG. 1F ). 
         [0046]    There is a relationship between complimentary mask  232  and mask layer  218  that is preferable for use with the present invention. The mask layer  218  is chosen to be selectively etched with respect to complimentary mask  232 . Selective etch techniques are well known in the art. The selectivity of removal between mask layer  218  and complimentary mask  232  is preferably of a ratio ranging from 1:2 to 1:10. With these selectivity ratios, the mask layer  218  is able to be etched at a much faster rate than the complimentary mask  232 . This allows the mask layer  218  to be removed without removing the complimentary mask  232 . The complimentary mask  232  preferably has the property of being strippable without impacting the gate profile or gate oxide layer of the device it is protecting. 
         [0047]    There are a variety of possible combinations of materials that may be used to achieve the desired selectivity. Selective etching is known in the art, and techniques for selective etching are disclosed in various references, such as U.S. Pat. No. 4,869,777, which is incorporated by reference herein. In an exemplary embodiment, the mask layer  218  may be organic, and the complimentary mask can be chosen as silicon based. In this case, a chemical etch can be used to remove the organic material at a much faster rate than the inorganic (silicon based) materials. 
         [0048]    For example, considering the case of a mask  218  comprised of an organic resist, and an inorganic complimentary mask  232  which is comprised of SSQ, polyborane, or silane derivatives. In one embodiment of the present invention, the organic resist is etched in O2 and H2 plasmas, selective solvents, or thermally degraded relative to the complimentary mask  232  comprised of the inorganic material (SSQ, polyborane, or silane derivatives). 
         [0049]    Materials that can be used for the mask  218  or complimentary mask  232  include, but are not limited to, methyl vinyl ketone (MVK), poly-methacrylic acid (PMAA), silsesqioxane (SSQ), polyallylamine (PAA), and hexafluoroalcohol (HFA). Resists may also be used to form the mask  218 . Resists typically contain aliphatic and/or aromatic resins (dependent on the wavelength), photoactive compounds such as chromophores, photoacids, and quenchers. Other components such as surfactants and plasticizers are also common. 
         [0050]    The table below illustrates some combinations that may be used. The table below is intended to be exemplary, and not intended to be limiting. Other materials may be used, so long as they exhibit the desired selectivity properties. 
         [0000]    
       
         
               
               
               
               
             
           
               
                   
               
               
                 mask 
                 Complimentary 
                   
                   
               
               
                 material 
                 mask material 
               
               
                 (218) 
                 (232) 
                 Selectivity 
                 Chemistries 
               
               
                   
               
             
             
               
                 Organic 
                 Inorganic 
                 H2, O2 plasma, 
                 Resist/SSQ, 
               
               
                   
                   
                 solvent strip, 
                 Carbosilane, 
               
               
                   
                   
                 thermal 
                 polyborane, silane 
               
               
                   
                   
                   
                 derivative 
               
               
                 Organic 
                 Organic 
                 Solvent, 
                 Resist/ 
               
               
                   
                   
                 thermal, UV 
                 P(a-Methyl 
               
               
                   
                   
                   
                 styrene), 
               
               
                   
                   
                   
                 PMMA-MVK, 
               
               
                   
                   
                   
                 PMAA, PAA, 
               
               
                   
                   
                   
                 HFA-derivate 
               
               
                   
                   
                   
                 (alcohol 
               
               
                   
                   
                   
                 soluable). 
               
               
                 Inorganic 
                 Organic 
                 H2, O2 plasma, 
                 SSQ/planarizing 
               
               
                   
                   
                 solvent strip, 
                 organic ARC 
               
               
                   
                   
                 thermal, UV 
               
               
                 Inorganic 
                 Inorganic 
                 Solvent, 
                 Alcohol soluable 
               
               
                   
                   
                 Acid/Base 
                 (SSQ)/alcohol 
               
               
                   
                   
                   
                 insoluable 
               
               
                   
                   
                   
                 (polycarbosilane) 
               
               
                   
               
             
          
         
       
     
         [0051]      FIG. 3  is a flowchart indicating process steps of the present invention. In process step  362 , a first mask layer is deposited on the semiconductor device. This corresponds to the deposition of mask layer  218  in  FIG. 2A . In process step  364 , a complimentary mask layer is deposited. This corresponds to the deposition of complimentary mask layer  232  in  FIG. 2A . In process step  366 , the first mask layer is removed. This results in the semiconductor device shown in  FIG. 2B  (note the absence of layer  218 ). In process step  368 , the polysilicon is removed from the first region. This results in the semiconductor device shown in  FIG. 2C  (note the absence of layer  210 A). Finally, in step  370 , the complimentary mask layer is removed. This results in the semiconductor device shown in  FIG. 2D  (note the absence of layer  232 ), wherein no stringer is formed over the STI region ( 208  of  FIG. 2D ). 
         [0052]    As can be seen from the aforementioned description, the present invention provides an improved method for patterning in a semiconductor fabrication process, and serves to promote continued high reliability for semiconductor devices and circuits. 
         [0053]    It will be understood that the present invention may have various other embodiments. Furthermore, while the form of the invention herein shown and described constitutes a preferred embodiment of the invention, it is not intended to illustrate all possible forms thereof. It will also be understood that the words used are words of description rather than limitation, and that various changes may be made without departing from the spirit and scope of the invention disclosed. Thus, the scope of the invention should be determined by the appended claims and their legal equivalents, rather than solely by the examples given.