Abstract:
A device including an input to receive a differential waveform pair from a transmission line, the differential waveform pair including a first waveform and a second waveform. The device also includes a repeater to generate a refreshed first output waveform and a refreshed second output waveform. The refreshed first output waveform is substantially similar to an inverted copy of the first waveform and is generated after a signal transition of the first waveform and after a complementary signal transition of the second waveform. The refreshed second output waveform is substantially similar to an inverted copy of the second waveform and is generated substantially simultaneously with generation of the first output waveform.

Description:
BACKGROUND  
         [0001]    Noise sensitive signals are usually transmitted as a differential pair. The two signals of the differential pair are affected substantially in the same manner by noise and, therefore, taking the difference between the two signals at their destination may cancel a significant portion of the noise added to the signals during transmission.  
           [0002]    If the differential pair signals are transmitted over long transmission lines, the signals may degrade due to noise caused by the parasitic series resistance, inductance, and coupling capacitance in the transmission lines. These parasitic elements attenuate high-frequency signal components more than low-frequency signal components and thereby cause a “smearing” or degradation of the waveform of the signals. If the transmission lines are sufficiently long, the degradation may cause the signals to be completely indecipherable by the time they reach the end of the transmission lines.  
           [0003]    To overcome this degradation, repeaters may be inserted along the transmission line at regular intervals. FIG. 1 shows multiple differential repeaters  100  used to propagate differential inputs INA and INB along a differential transmission line  105 . A termination block  110  is connected to the end of the transmission line  105  and may be optionally used to the end of the transmission line  105  and may be optionally used for interfacing the received differential signal with a receiving circuit (not shown).  
           [0004]    [0004]FIG. 2 shows an example of a differential amplifier  200  that may be used as a differential repeater (e.g.,  100  in transmission line  105 ). The differential amplifier  200  includes a DC current source  205 , two output resistors  210 , and two n-type transistors  215 . The differential inputs, INA and INB, are amplified by the differential amplifier  200  which outputs them at OUTA and OUTB. However, the use of the differential amplifier  200  as a repeater suffers from several drawbacks.  
           [0005]    First, the differential amplifier  200  exhibits high power dissipation caused by the constant current consumption of the DC current source  205 . When multiple differential amplifiers  200  are used to drive transmission lines the resulting power dissipation worsens and may become intolerable.  
           [0006]    Second, the differential amplifier  200  exhibits low-drive capability caused by the two output resistors  210  forming a low-pass filter with the transmission line capacitance. The attenuation of high-frequency signal components caused by the low pass filter may be lessened by decreasing the resistance of the output resistors  210 . However, decreasing the resistance of resistors  210  requires a proportionate increase in the DC current source  205  that results in increased power consumption.  
           [0007]    Third, skew between the two differential inputs INA and INB of the differential amplifier  200  may result. Skew may build between the inputs INA and INB because of a physical mismatch between the two transmission lines on which the signals travel. The skew distorts waveforms and progressively worsens as the differential signal propagates along the transmission line.  
           [0008]    [0008]FIG. 3 shows an example of the distortion effect of skew on a differential signal A-B. The distortion effect progressively worsens as skew between the signals A and B increases as the differential signal travels along a transmission line. For example, no skew is evident when the signals are at the signal source  300 . Some skew is apparent when the signals have traveled to the middle of the transmission line  305 , and significant skew and distortion are shown when the signals have reached their destination  310 . In addition, as skew builds, noise affects the two signals A and B unequally, thereby resulting in increased noise interference in the form of jitter.  
       
    
    
     DESCRIPTION OF DRAWINGS  
       [0009]    [0009]FIG. 1 is a block diagram of a conventional transmission line with repeaters inserted at regular intervals.  
         [0010]    [0010]FIG. 2 is a differential amplifier used as a differential repeater.  
         [0011]    [0011]FIG. 3 is a diagram illustrating skew build-up as a signal propagates along a transmission line.  
         [0012]    [0012]FIG. 4 is an exemplary block diagram of a transmission line with differential deskewing repeaters (DDRs) inserted at regular intervals.  
         [0013]    [0013]FIG. 5 is an exemplary circuit diagram of a DDR.  
         [0014]    FIGS.  6 - 8  are circuit diagrams of the DDR of FIG. 5 with input and output signals shown.  
         [0015]    [0015]FIG. 9 is an exemplary block diagram of a clock transmission circuit using a DDR of FIG. 5.  
         [0016]    Like reference symbols in the various drawings indicate like elements. 
     
    
     DETAILED DESCRIPTION  
       [0017]    [0017]FIG. 4 shows a transmission line  405  including two inputs at a source and two outputs at a destination. One or more differential deskewing repeaters (DDRs)  400  may be inserted along a transmission line  405  at predetermined intervals. A termination block  410  may be connected to the end of the transmission line  405  and may be optionally used for interfacing the received differential pair signal with a receiving circuit (not shown).  
         [0018]    The DDRs serve to both refresh the differential pair signal (i.e., shorten signal transition times and restore the signal levels to levels substantially close to their original levels prior to signal propagation) and deskew the differential pair signal (i.e., eliminate any time delay between the two signals forming the differential pair) that travels along the transmission line  405 . FIG. 5 shows an example of a differential deskewing repeater (DDR)  500  that includes eight transistors  525 - 560 . As shown, transistors  525 ,  530 ,  555 , and  560  are n-type transistors and transistors  535 ,  540 ,  545  and  550  are p-type transistors. Other implementations may employ different numbers of n-type and p-type transistors.  
         [0019]    The DDR circuit  500  receives differential inputs INA  505  and INB  510 . In general, the differential inputs INA  505  and INB  510  are complementary and switch between the supply rail voltages (i.e., between VSS and VCC). Outputs OUTA  515  and OUTB  520  are complementary to inputs INA  505  and INB  510  (i.e., after switching is complete, OUTA  515  is the inverse of INA  505  and OUTB  520  is the inverse of INB  510 ).  
         [0020]    The input INA  505  is coupled to the gate of the n-type transistor  525  and the gate of the p-type transistor  540 . The input INB  510  is coupled to the gate of the n-type transistor  560  and the gate of the p-type transistor  545 .  
         [0021]    A supply rail voltage VSS  565  is coupled to the source of n-type transistor  525  and the source of n-type transistor  560 . A supply rail voltage VCC  570  is coupled to the source of the p-type transistor  540  and the source of the p-type transistor  545 .  
         [0022]    As shown in FIG. 5, the drain of the n-type transistor  525  is coupled to the source of the n-type transistor  530  and the gate of the p-type transistor  550 . The gate of the n-type transistor  530  is coupled to the drain of the p-type transistor  545  and the source of the p-type transistor  550 . The drain of the n-type transistor  530  is coupled to the output OUTA  515  and the drain of the p-type transistor  535 . The gate of the p-type transistor  535  is coupled to the drain of the n-type transistor  560  and the source of the n-type transistor  555 . The source of the p-type transistor  535  is coupled to the drain of the p-type transistor  540  and the gate of the n-type transistor  555 . The drain of the n-type transistor  555  is coupled to the drain of the p-type transistor  550  and the output OUTB  520 .  
         [0023]    The DDR circuit  500  may eliminate skew between the differential inputs INA  505  and INB  510  by switching OUTA  515  and OUTB  520  only when both INA  505  and INB  510  switch. For example, if INA  505  switches before INB  510  switches, the outputs OUTA  515  and OUTB  520  do not switch until INB  510  switches. Likewise, if INB  510  switches before INA  505  switches, the outputs OUTA  515  and OUTB  520  do not switch until input INA  505  switches. Therefore, if any skew has occurred in the differential pair signal applied to the inputs INA  505  and INB  510 , the DDR circuit  500  ensures that no skew propagates to the differential pair signal outputs OUTA  515  and OUTB  520 . Furthermore, the DDR circuit  500  refreshes the differential pair signal by driving the outputs OUTA  515  and OUTB  520  with VSS  565  and VCC  570  using the combination of transistors that are turned on. The operation of DDR circuit  500  may be illustrated using the examples shown in FIGS.  6 - 8 .  
         [0024]    As shown in FIG. 6, INA  505  receives a low input and INB  510  receives a high input. The low input to INA  505  turns off the n-type transistor  525  and turns on the p-type transistor  540 , which results in a high potential at the drain of the p-type transistor  540  to turn on n-type transistor  555 . Similarly, the high input to INB  510  turns off the p-type transistor  545  and turns on the n-type transistor  560 , which pulls the drain of the n-type transistor  560  to a low potential to turn on the p-type transistor  535 . Because both p-type transistors  535  and  540  are turned on, a high potential results on the output OUTA  515 . Likewise, the turned on n-type transistors  555  and  560  cause a low potential on the output OUTB  520 .  
         [0025]    Ideally, the differential pair signals are complementary such that a transition in one of the signals (e.g., INA  505 ) results in a simultaneous and opposite transition in the other signal (e.g., INB  510 ). However, under actual operating conditions skew results from a delay between the transition of one signal and the transition of the other due to the physical mismatch between the two transmission lines on which the signal travels.  
         [0026]    [0026]FIG. 7 shows the operation of the DDR circuit  500  when there is some skew between the differential pair. As shown in FIG. 7, INA  505  transitions to a high potential before INB  510  transitions to a low level potential. When INA  505  transitions to a high potential, the n-type transistor  525  turns on, pulling its drain voltage low, which turns on the p-type transistor  550 . However, the potential at OUTB  520  remains low because the p-type transistor  545  remains off and the n-type transistors  555  and  560  remain on. The transition of INA  505  to a high potential also turns off the p-type transistor  540 . However, the output voltage OUTA  515  is not affected because the n-type transistor  530  remains turned off, and, therefore, the output voltage OUTA  515  is not pulled low by VSS  565 . Thus, the output voltages OUTA  515  and OUTB  520  remain unchanged despite the transition of the input voltage INA  505 .  
         [0027]    [0027]FIG. 8 shows the operation of the DDR circuit  500  when the input voltage INB  510  transitions to a low potential sometime after the input voltage INA  505  has already transitioned to a high potential, for example, as previously described with regard to FIG. 7. The transition of INB  510  to a low potential turns on the p-type transistor  545  and turns off the n-type transistor  560 . Turning on transistor  545  pulls the drain voltage of transistor  545  to a high potential, which turns on the n-type transistor  530  and also pulls OUTB  520  to a high potential. Turning on transistor  530  allows transistors  525  and  530  to pull OUTA  515  to a low potential.  
         [0028]    As shown by the preceding examples, the outputs OUTA  515  and OUTB  520  transition substantially simultaneously only upon the transition of the later in time of the two differential pair inputs. The differential outputs OUTA  515  and OUTB  520  provide a differential pair signal that is a refreshed complementary copy of the differential pair signal input to the DDR circuit  500 . Any skew present in the input signal is eliminated.  
         [0029]    The transistor device sizes for the DDR circuit  500  may be selected using simulations approximating actual device conditions. Specifically, the device sizes may be chosen to cause outputs OUTA  515  and OUTB  520  to cross-over at the voltage midpoint between VCC  570  and VSS  565  when they transition between high and low potentials.  
         [0030]    The DDR circuit  500  dissipates very little power because the circuit consumes current only during switching. The switching current is composed of current that charges up parasitic capacitances and a rush-through current that travels through the transistors when a momentary low-resistance path from VCC  570  to VSS  565  is established during switching. Therefore, the DDR circuit  500  current consumption is, for example, on the order of a CMOS logic gate having similar transistor sizes. As a result, the DDR circuit  500  consumes less current and dissipate less power than repeaters that use a DC current source and constantly consume current.  
         [0031]    The drive capability of the DDR circuit  500  also eliminates the need for a pair of resistors at the output of the repeater, which may degrade the output because of the combination of the output resistance in parallel with the transmission line capacitance (e.g., acting as a low-pass filter that attenuates high-frequency signal components.) The power consumption of the DDR circuit  500  is lower than repeaters which require a higher DC current source to offset the high output resistance. The repeater circuit  500  also provides relatively low output resistance and good drive capability, which is particularly suited to driving high frequency differential pair clock signals.  
         [0032]    [0032]FIG. 9 shows a clock transmission circuit  900  that includes a clock generation circuit  905  connected to a clock termination circuit  910  through a transmission line  915 . DDRs  920  are inserted along the transmission line  915  at regular intervals.  
         [0033]    The clock generation circuit  905  may generate a high frequency clock signal. A high frequency clock signal is usually transmitted as a differential pair to minimize the effects of noise. Because both signals of the differential pair are affected roughly in the same manner by noise, the noise can be canceled out between the pair of clock signals.  
         [0034]    The clock generation circuit  905  includes a circuit that generates the differential-pair clock signals. This circuit may include an oscillator circuit (not shown) to generate a clock signal at a particular frequency in conjunction with a phase-locked loop circuit (not shown) to adjust the frequency of the clock signal.  
         [0035]    The clock termination circuit  910  includes a circuit that uses the clock signals for timing. This circuit may convert the differential-pair clock signals to single-ended clock signals depending on the application of the clock signals in the circuit.  
         [0036]    The distance that clock-differential pair signals may travel may be limited significantly by noise, skew, and signal strength. Higher frequency clock signals (e.g., 1 GHz and higher) attenuate faster due to the parasitic resistance, inductance, and capacitance of the transmission lines. As a result, higher frequency clock signals are sensitive to noise and skew. Therefore, these signals may be refreshed and deskewed more often than lower frequency signals.  
         [0037]    In the exemplary circuit shown in FIG. 9, a differential clock signal may travel a long distance via transmission line  915  with the use of DDRs  920 . The spacing between DDRs  920  will vary depending on the frequency of the repeated signal and the noise characteristics of the environment in any specific implementation.  
         [0038]    The DDRs  920  refresh the differential pair clock signal and deskew the differential pair clock signal. The regular refreshing and deskewing of the differential pair clock signal by the DDRs  920  ensures that the signal reaches the clock termination circuit  910  with sufficient strength and signal integrity to be properly used for timing purposes.  
         [0039]    Other implementations are within the scope of the following claims.