Abstract:
Disclosed is a shift circuit capable of reducing current consumption and circuit area and increasing the operation speed. The shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to a semiconductor memory device and, more particularly, to a shift circuit capable of reducing an area and current with a high-speed operation in a semiconductor memory device. 
       BACKGROUND 
       [0002]    Generally, a shift circuit performs an operation to shift data, which are input in synchronization with a clock signal, and this shift circuit is widely used in a semiconductor memory device. For example, the shift circuit is used as a parallel-serial converter to convert parallel data to serial data and as a delay circuit to delay a signal. 
         [0003]    Further, the shift circuit is also used in a synchronous semiconductor memory device because an internal operation timing is determined based on a clock signal. 
         [0004]      FIG. 1  is a circuit diagram illustrating a conventional shift circuit and  FIG. 2  is a circuit diagram illustrating a feedback inverter employed in the shift circuit of  FIG. 1 . 
         [0005]    As shown in  FIG. 1 , the conventional shift circuit includes a transfer gate T 10  to transfer input data D_IN to a node nd 10  in response to a clock signal CLK, a first latch  10  to latch the data transferred to the node nd 10 , a transfer gate T 12  to transfer the input data D_IN on a node nd 11  to a node nd 12  in response to the clock signal CLK, and a second latch  12  to latch the data transferred to the node nd 12 . 
         [0006]    The first latch  10  includes an inverter IV 12  to invert the data on the node nd 10  and output the inverted data to the node nd 11  and an inverter IV 14  to invert the data on the node nd 11  and output the inverted data to the node nd 10 . The second latch  12  includes an inverter IV 16  to invert the data on the node nd 12  and output the inverted data to the node nd 13  and an inverter IV 18  to invert the data on the node nd 13  and output the inverted data to the node nd 12 . 
         [0007]    In the above-mentioned shift circuit, when the clock signal CLK is at a low level, the input data D_IN is transferred to the node nd 10  and the first latch  10  latches the data on the node nd 10 . 
         [0008]    Next, when the clock signal CLK is transited from a low level to a high level, the latched data in the first latch  10  are transferred to the node nd 12  and the second latch  12  latches and stores the data on the node nd 12 . The data stored in the second latch  12  are output as output data D_OUT. 
         [0009]    As mentioned above, if the clock signal CLK is at a high level, the shift circuit outputs, as the output data D_OUT, the input data D_IN which are input when the clock signal CLK is at a low level. That is, the output data D_OUT are output by shifting the input data D_IN by a half period of the clock signal. This shift circuit is called “half clock shift circuit.” 
         [0010]    As shown in  FIG. 2 , the inverter IV 14  induced in the first latch  10  and the inverter IV 18  induced in the second latch  12  (hereinafter referred to as “feedback inverters”) are made up of PMOS transistors P 10  and P 12 , which are connected in series to each other between a supply voltage VCC and an output terminal OUT, and NMOS transistor N 10  and N 12 , which are connected in series to each other between the output terminal OUT and a ground voltage. The reason why the feedback inverter is made up of the PMOS transistor P 10  and P 12 , which are connected in series to each other, and the NMOS transistor N 10  and N 12 , which are connected in series to each other, is that the data are sufficiently latched in the first and second latches  10  and  12  by the increased drivability of the feedback inverters. 
       BRIEF SUMMARY 
       [0011]    In an aspect of the present disclosure, a shift circuit is provided that is capable of reducing current consumption and circuit area and increasing operation speed. 
         [0012]    In an embodiment, a shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal. 
         [0013]    In another embodiment, a shift circuit includes a buffer unit for buffering input data in response to a clock signal, and a latch unit for latching the buffered data from the buffer unit in response to a clock signal. 
         [0014]    In another embodiment, a shift circuit includes a transfer buffer for buffering a signal on a first node and transferring the buffered signal to a second node, a feedback buffer for feeding back the buffered signal on the second node to the first node, and a feedback determination unit for determining an operation of the feedback buffer in response to a clock signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0016]      FIG. 1  is a circuit diagram illustrating a conventional shift circuit; 
           [0017]      FIG. 2  is a circuit diagram illustrating a feedback inverter employed in the shift circuit of  FIG. 1 . 
           [0018]      FIG. 3  is a circuit diagram illustrating an example of a structure of a shift circuit according to an embodiment of the present disclosure; 
           [0019]      FIG. 4  is a circuit diagram illustrating an example of a structure of a feedback inverter that can be employed in the shift circuit of  FIG. 3 ; and 
           [0020]      FIG. 5  is a circuit diagram illustrating an example of a structure of a shift circuit according to another embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0021]    Hereinafter, examples and embodiments of the present disclosure will be described with reference to accompanying drawings. However, the examples and embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. 
         [0022]    First,  FIG. 3  is a circuit diagram illustrating an example of a structure of a shift circuit according to an embodiment of the present disclosure and  FIG. 4  is a circuit diagram illustrating an example of a structure of a feedback inverter that can be employed in the shift circuit of  FIG. 3 . 
         [0023]    As shown in  FIG. 3 , the shift circuit according to an embodiment of the present disclosure includes a first transfer gate T 20  configured to transfer input data D_IN to a node nd 20  in response to a clock signal CLK, a first latch unit  20  configured to latch the data on the node nd 20  in response to the clock signal CLK, a second transfer gate T 22  configured to transfer the data on a node nd 21  to a node nd 22  in response to a clock signal CLK, and a second latch unit  22  configured to latch the data on the node nd 22  in response to the clock signal CLK. 
         [0024]    The first latch unit  20  includes an inverter IV 22  configured to invert the data on the node nd 20  and output the inverted data to the node nd 21 , an inverter IV 24  configured to invert the data on the node nd 21  and output the inverted data, and a NMOS transistor N 20  configured to transfer an output signal of the inverter IV 24  to the node nd 20  in response to the clock signal CLK. 
         [0025]    The second latch unit  22  includes an inverter IV 26  configured to invert the data on the node nd 22  and output the inverted data to a node nd 23 , an inverter IV 28  configured to invert the data on the node nd 23  and output the inverted data, and a NMOS transistor N 22  configured to transfer an output signal of the inverter IV 28  to the node nd 22  in response to the clock signal CLK. 
         [0026]    The inverters IV 24  and IV 28  can be defined as feedback inverters. A feedback inverter, as shown in  FIG. 4 , includes a PMOS transistor P 24 , which is disposed between an external supply voltage VCC and an output terminal OUT and performs a pull-up operation at the output terminal OUT in response to an input signal IN, and a NMOS transistor N 24 , which is disposed between the output terminal OUT and a ground voltage VSS and performs a pull-down operation at the output terminal OUT in response to an input signal IN. As mentioned above, in the feedback inverter according to an embodiment of the present disclosure, the PMOS transistors or NMOS transistors are not connected to each other in series. Since it is not necessary to store the data in the first latch unit  20  and the second latch unit  22  when the data are transferred to another node, the drivability of the first and second latch units  20  and  22  can be sufficiently obtained. 
         [0027]    The operation of the above-mentioned shift circuit will be described in detail. 
         [0028]    First, when the clock signal CLK is at a low level, the first transfer gate T 20  is turned on and then the input data D_IN is transferred to the node nd 20 . The inverter IV 22  inverts the data on the node nd 20  and then outputs the inverted data to the node nd 21 . At this time, the NMOS transistor N 20  is turned off and the drivability of the feedback inverter (inverter IV 24 ) is stopped from carrying out the latch operation. 
         [0029]    Next, when the clock signal CLK is transited to a high level, the first transfer gate T 20  is turned off and the second transfer gate T 22  is turned on. Accordingly, the data on the node nd 20  are transferred to the node nd 22  and the inverter IV 26  inverts the data on the node nd 22  and outputs the inverted data as the output data D_OUT. At this time, the NMOS transistor N 20  is turned on so that the first latch unit  20  latches the data on the node nd 20 . In this case, the NMOS transistor N 22  is turned off so that the inverter IV 28 , which is used as the feedback inverter, is not connected to the node nd 22 . 
         [0030]    As mentioned above, the shift circuit according to the present disclosure outputs the output data D_OUT by shifting the input data D_IN by a half period of the clock signal and the drivability of the feedback inverter is terminated while the data are transferred to the node. That is, when the input data D_IN are transferred to the node nd 20  by the clock signal CLK of a low level, the feedback inverter IV 24  does not carry out the driving operation and, when the input data on the node nd 21  are transferred to the node nd 22  by the clock signal CLK of a high level, the feedback inverter IV 28  does not carry out the driving operation. As mentioned above, the drivability of the inverters IV 24  and IV 28  can be improved, by stopping the driving of the feedback inverters (inverters IV 24  and IV 28 ) when the data are transferred in the first and second latch units  20  and  22 . Accordingly, since the feedback inverters (inverters IV 24  and IV 28 ) are driven whenever the data are stored, the structure of the feedback inverter, according to the present disclosure, can be simplified as shown in  FIG. 4 . As a result, the area and current consumption of the shift circuit can be reduced and in addition an operation speed can be improved. 
         [0031]      FIG. 5  is a circuit diagram illustrating an example of a structure of a shift circuit according to another embodiment of the present disclosure. 
         [0032]    As shown in  FIG. 5 , the shift circuit according to another embodiment of the present disclosure includes a first buffer unit  30  configured to buffer input data D_IN in response to a clock signal CLK, a third latch unit  32  configured to latch the data on a node nd 31  in response to a clock signal CLK, a second buffer unit  34  configured to buffer the data D_IN on a node nd 33  in response to a clock signal CLK, and a fourth latch unit  36  configured to latch the data on a node nd 35  in response to a clock signal CLK. 
         [0033]    The first buffer unit  30  includes a first buffer  300 , a PMOS transistor P 32 , and a NMOS transistor N 32 . The first buffer  300  includes a PMOS transistor P 30 , which is disposed between a node nd 30  and the node nd 31  and performs a pull-up operation at the node nd 31  in response to the input data D_IN, and a NMOS transistor N 30 , which is disposed between the node nd 31  and a node nd 32  and performs a pull-down operation at the node nd 31  in response to the input data D_IN. The PMOS transistor P 32  is disposed between a supply voltage VCC and the node nd 30  and is turned on in response to a clock signal CLK. The NMOS transistor N 32  is disposed between the node nd 32  and a ground voltage VSS and is turned on in response to an inverted clock signal CLKB. 
         [0034]    The third latch unit  32  includes an inverter IV 30  configured to invert the data on the node nd 31  and output the inverted data to the node nd 33 , an inverter IV 32  configured to invert the data on the node nd 33  and output the inverted data, and a NMOS transistor N 33  configured to transfer an output signal of the inverter IV 32  to the node nd 31  in response to the clock signal CLK. 
         [0035]    The buffer unit  34  includes a second buffer  340 , a PMOS transistor P 36 , and a NMOS transistor N 36 . The second buffer  340  includes a PMOS transistor P 34 , which is disposed between a node nd 34  and the node nd 35  and performs a pull-up operation at the node nd 35  in response to the data D_IN on the node nd 33 , and a NMOS transistor N 34 , which is disposed between the node nd 35  and a node nd 36  and performs a pull-down operation at the node nd 35  in response to the data D_IN on the node nd 33 . The PMOS transistor P 36  is disposed between the supply voltage VCC and the node nd 34  and is turned on in response to the inverted clock signal CLKB. The NMOS transistor N 36  is disposed between the node nd 36  and a ground voltage VSS and is turned on in response to the clock signal CLK. 
         [0036]    The fourth latch unit  36  includes an inverter IV 34  configured to invert the data on the node nd 35  and output the inverted data to a node nd 37 , an inverter IV 36  configured to invert the data on the node nd 37  and output the inverted data, and a NMOS transistor N 37  configured to transfer an output signal of the inverter IV 36  to the node nd 35  in response to the clock signal CLK. 
         [0037]    In  FIG. 5 , the inverters IV 32  and IV 36  can be defined as feedback inverters. The feedback inverter, as shown in  FIG. 4 , includes a PMOS transistor P 24 , which is disposed between an external supply voltage VCC and an output terminal OUT and performs a pull-up operation at the output terminal OUT in response to an input signal IN, and a NMOS transistor N 24 , which is disposed between the output terminal OUT and a ground voltage VSS and performs a pull-down operation at the output terminal OUT in response to an input signal IN. As mentioned above, in the feedback inverter according to an embodiment of the present disclosure, the PMOS transistors or NMOS transistors are not connected to each other in series. Since it is not necessary to store the data in the third latch unit  32  and the fourth latch unit  36  when the data are transferred to another node, the drivability of the third and fourth latch units  32  and  36  can be sufficiently obtained. 
         [0038]    The operation of the above-mentioned shift circuit will be described in detail. 
         [0039]    First, when the clock signal CLK is at a low level, the PMOS transistor P 32  and the NMOS transistor N 32  are turned on and then the first buffer  300  inverts the input data D_IN and transfers the inverted data to the node nd 31 . The inverter IV 30  inverts the data on the node nd 31  and outputs the inverted data to the node nd 33 . At this time, the NMOS transistor N 33  is turned off and the drivability of the feedback inverter (inverter IV 32 ) is stopped from carrying out the latch operation. 
         [0040]    Next, when the clock signal CLK is transited to a high level, the PMOS transistor P 32  and the NMOS transistor N 32  are turned off and the first buffer  300  stops buffering the data. On the other hand, the PMOS transistor P 36  and the NMOS transistor N 36  are turned on and the second buffer  340  transfers the data on the node nd 33  to the node nd 35 . The data which are transferred to the node nd 35  are inverted by the inverter IV 34  and the output data D_OUT are output through the node nd 37 . At this time, the NMOS transistor N 33  is turned on, the third latch unit  32  latches and stores the data on the node nd 31 , and then the NMOS transistor N 37  is turned off. Accordingly, the drivability of the feedback inverter (inverter IV 36 ) is stopped from carrying out the latch operation. 
         [0041]    As mentioned above, the shift circuit according to the present disclosure outputs the output data D_OUT by shifting the input data D_IN by a half period of the clock signal and the drivability of the feedback inverter is terminated while the data are transferred to the node. That is, when the input data D_IN are transferred to the node nd 31  by the clock signal CLK of a low level, the feedback inverter IV 32  does not carry out the driving operation and, when the input data on the node nd 21  are transferred to the node nd 35  by the clock signal CLK of a high level, the feedback inverter IV 36  does not carry out the driving operation. As mentioned above, the drivability of the inverters IV 32  ad IV 36  can be improved, by stopping the driving of the feedback inverters (inverters IV 32  and IV 36 ) when the data are transferred in the third and fourth latch units  32  and  36 . Accordingly, since the feedback inverters (inverters IV 32  and IV 36 ) are driven whenever the data are stored, the structure of the feedback inverter, according to the present disclosure, can be simplified as shown in  FIG. 4 . As a result, the area and current consumption of the shift circuit can be reduced and in addition an operation speed can be improved. 
         [0042]    Although examples and embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the accompanying claims. 
         [0043]    The present disclosure claims priority to Korean application number 10-2008-0006365, filed on Jan. 21, 2008, the entire contents of which are incorporated herein by reference.