Abstract:
A semiconductor memory circuit includes first and second bit lines making a first pair, third and fourth bit lines making a second pair, a memory cell having a first inverter coupled between the first pair, a second inverter coupled between the second pair, a third inverter coupled between first and third bit lines and a fourth inverter coupled between second and fourth bit lines. The memory cell further includes a first access switch inserted between first bit line and the first inverter, second access switch inserted between second bit line and the second inverter, third access switch inserted between third bit line and the third inverter and fourth access switch inserted between fourth bit line and the fourth inverter.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a semiconductor memory device, and more particularly, to a multi-port semiconductor memory device. 
         [0003]    2. Description of Related Art 
         [0004]      FIG. 5  is a schematic view for explaining a memory cell of a dual-port RAM having eight transistors per memory cell. With reference to  FIG. 5 , the memory cell includes inverters INV 1  and INV 2 . The input of the inverter INV 1  is connected to the output of the inverter INV 2 , while the output of the inverter INV 1  is connected to the input of the inverter INV 2 . Additionally, the memory cell includes access transistors  111  and  112  for a port A and access transistors  113  and  114  for a port B between connection nodes N 1  and N 2  and bit lines DTA/DBA and DTB/DBB, respectively. This memory cell is a memory cell of an SRAM (a static RAM) which can be simultaneously accessed through the port A and the port B. When a word line WLA is activated, data write or data read from the bit line pair DTA and DBA can be carried out. When a word line WLB is activated, data write or data read from the bit line pair DTB and DBB can be carried out. Data stored in the memory cell is latched by the inverters INV 1  and INV 2 . In order to store data in the memory cell through the port A when the voltage on the bit line DTA is high level and the voltage on the bit line DBA is low level, the word line WLA is activated and output voltages of the inverters INV 1  and INV 2  are the low level and the high level, respectively. After that, when the memory cell stores inverted data through the port A or through the port B, the two inverters invert the stored data. For example, when output voltage of the inverters INV 1  and INV 2  are the low level and the high level, respectively, and the word line WLA is activated and data expressed by the low level on DTA and the high level on DBA is written, output voltages of the inverters INV 1  and INV 2  are the high level and the low level, respectively. 
         [0005]      FIG. 6  is a view for explaining a structure and operation of the memory cell of  FIG. 5 .  FIG. 6  shows a PMOS transistor PM 1  a source of which is connected to a power supply, an NMOS transistor NM 1  a source of which is connected to GND and a drain of which is connected to a drain of the PMOS transistor PM 1 , a PMOS transistor PM 2  a source of which is connected to the power supply, and an NMOS transistor NM 2  a source of which is connected to GND and a drain of which is connected to a drain of the PMOS transistor PM 2 . A common gate of the PMOS transistor PM 1  and the NMOS transistor NM 1  is connected to a common drain of the PMOS transistor PM 2  and the NMOS transistor NM 2 , while a common drain of the PMOS transistor PM 1  and the NMOS transistor NM 1  is connected to a common gate of the PMOS transistor PM 2  and the NMOS transistor NM 2 . The common drain of the PMOS transistor PM 1  and the NMOS transistor NM 1  is connected to the bit lines DTA and DTB through access transistors  111  and  113  gates of which are connected to the word lines WLA and WLB, respectively. The common drain of the PMOS transistor PM 2  and the NMOS transistor NM 2  is connected to the bit lines DBA and DBB through access transistors  112  and  114  gates of which are connected to the word lines WLA and WLB, respectively. 
         [0006]      FIG. 6  schematically illustrates a state where the word lines WLA and WLB are activated to be high, the access transistors  111 - 114  are turned on, and the bit lines DTA and DTB precharged to the high level is discharged through the NMOS transistor NM 1 . Cell currents Icell_A and Icell_B flow through the access transistor (port A access Tr)  111  and the access transistor (port B access Tr)  113 , respectively, into the drain and ultimately into the source of the NMOS transistor NM 1 . 
         [0007]    With regard to the structure of a dual-port RAM or a multi-port RAM, please also refer to, for example, Japanese Patent Application Laid-open No. Hei 5-299621 and Japanese Patent Application Laid-open No. 2005-346837. Japanese Patent Application Laid-open No. Hei 5-299621 discloses a dual-port RAM where, in order to increase the integration degree, the access transistors are formed of PMOS transistors. Japanese Patent Application Laid-open No. 2005-346837 discloses a dual-port RAM where, in reading operation, when it is detected that row addresses of first and second ports match each other, only a word line of the first port is activated, a column switch connects a bit line pair of the first port selected according to a column address of the first port to a data line pair of the first port and connects a bit line pair of the first port selected according to a column address of the second port to a data line pair of the second port. 
         [0008]    The present inventor has recognized that, in the dual-port RAM of  FIG. 5 , when simultaneous access where word lines WLA and WLB are simultaneously activated is made, bit line potential changes at a lower speed than that in a case where access is made only through one of the ports. Then the access time is increased or malfunction is caused. The following is a study made by the present inventor. 
         [0009]    In the dual-port RAM of  FIGS. 5 and 6 , both of the access transistors provided correspondingly to the bit lines of the two ports, respectively, are connected to an output of one inverter. Therefore, when the word lines WLA and WLB are simultaneously activated, current flowing through one access transistor is decreased. Further, depending on variations in current driving ability of the access transistors or the like, the amount of current flowing through an access transistor is, for example, on the order of ⅓ to 1/10 of that when simultaneous access is not made. Therefore, amplitude of the bit line potential when the port A and the port B are simultaneously accessed is decreased. 
         [0010]    Further, with the progress of miniaturization of semiconductor devices, random variations in the cell currents Icell_A and Icell_B of the port A and the port B in one memory cell increases accordingly.  FIG. 7B  illustrates an equivalent circuit of  FIG. 7A  including access transistors  111  and  113  and an NMOS transistor NM 1 . 
         [0011]    In  FIG. 7A , variations in the cell currents Icell_A and Icell_B is variations in currents IAccA and IAccB in the equivalent circuit in  FIG. 7B . RAccA and RAccB are on-resistances of the access transistors of the port A and the port B, and RDRV is on-resistance of the NMOS transistor NM 1  (driver transistor) of an inverter in the memory cell. 
         [0012]    IAccA+IAccB=IDRV, and therefore, when the current IAccA flowing through one access transistor increases, the current IAccB flowing through the other access transistor decreases. This current difference causes the difference in discharging rate of the bit lines. More specifically, variations in the cell currents Icell_A and Icell_B are found to be variations in discharge ability based on current driving ability of the access transistors. When the difference in discharging rate is remarkable, potential difference between a pair of bit lines of one port is decreased, which may cause malfunction. In order to prevent such malfunction, it is necessary to enhance current driving ability of the driver transistor. However, enhancing the current driving ability of the driver transistor increases the memory cell area. 
         [0013]      FIG. 8  is a waveform chart schematically illustrating relationship between presence and absence of variations in the access transistors of the port A and the port B and data on the bit lines. Variations in current driving ability of the access transistors drastically decrease current flowing through the access transistor with the lower current driving ability. Therefore, potential difference between a bit line pair (in  FIG. 8 , the bit line pair DTA/DBA) is decreased. 
         [0014]    As a result, there is a problem that variations in access transistors between ports decrease potential difference between a bit line pair, which causes unstable operation of a sense amplifier to cause false sensing. 
       SUMMARY 
       [0015]    The present invention seeks to solve one or more of the above problems, or to improve upon those problems at least in part. 
         [0016]    In one embodiment of the present invention, a semiconductor memory circuit includes a plurality of bit line pairs, a plurality of memory cells connected between each of the bit line pairs, each of the memory cells being accessible by the bit line pairs from a plurality of ports. Each of the memory cells includes a plurality of access transistors and a latch circuit. The access transistors each connected to an associated one bit line of the bit line pairs. The latch circuit has a plurality of inverter circuits which are connected in ring shape. Each of the inverter circuits includes an output terminal which is connected to an associated one of the access transistors. 
         [0017]    As described above, because one access transistor is connected to one driver transistor of the inverter circuit, even when there are variations in access transistors between ports, compared with a case where a plurality of access transistors share one driver transistor, extreme decrease in current flowing through the respective access transistors is not caused even when the word lines WLA and WLB are simultaneously activated. Therefore, a sense amplifier of a semiconductor memory having the memory cell operates stably and false sensing can be avoided. 
         [0018]    In another embodiment of the present invention, a semiconductor memory circuit comprises first and second bit lines making a first pair, third and fourth bit lines making a second pair, a first inverter coupled between the first and second bit lines, a second inverter coupled between the third and fourth bit lines, a third inverter coupled between the first and third bit lines, and a fourth inverter coupled between the second and fourth bit lines. 
         [0019]    In the other embodiment of the present invention, a semiconductor memory circuit comprises first and second bit lines making a first pair, third and fourth bit lines making a second pair, and a memory cell having first, second, third and fourth nodes, the first node being the same in logic level as the third node, the second node being the same in logic level as the fourth node and different in logic level from the first node, the first bit line being operatively coupled to the first node of the memory cell, the second bit line being operatively coupled to the second node of the memory cell, the third bit line being operatively coupled to the third node of the memory cell, and the fourth bit line being operatively coupled to the fourth node of the memory cell. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0021]      FIG. 1  illustrates a structure of a memory cell according to an embodiment of the present invention; 
           [0022]      FIG. 2  is a view for explaining a structure and operation of the memory cell according to the embodiment of the present invention; 
           [0023]      FIG. 3  illustrates a structure of a memory cell array according to the embodiment of the present invention; 
           [0024]      FIGS. 4A to 4C  illustrate structures of memory cells according to other embodiments of the present invention; 
           [0025]      FIG. 5  illustrates a typical structure of a cell of a dual-port RAM; 
           [0026]      FIG. 6  illustrates an operation of the dual-port RAM of  FIG. 5 ; 
           [0027]      FIG. 7A  illustrates current paths through access transistors of the dual-port RAM; 
           [0028]      FIG. 7B  is an equivalent circuit of  FIG. 7A ; and 
           [0029]      FIG. 8  is a waveform chart illustrating relationship between presence and absence of variations in current driving ability of the access transistors and data on bit lines. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0030]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
         [0031]    Referring now to  FIG. 1 , a memory cell according to a first embodiment of the present invention includes access transistors  111  to  114 , and the inverters INV 3  and INV 4  in addition to the inverters INV 1  and INV 2 . The access transistor (access switch)  111  has a source-drain path connected between a bit line DTA and output of the inverter INV 1  and a gate connected to a word line WLA. The access transistor (access switch)  112  has a source-drain path connected between a bit line DBA and output of the inverter INV 2  and a gate connected to the word line WLA. The access transistor (access switch)  113  has a source-drain path connected between a bit line DTB and output of the inverter INV 3  and a gate connected to a word line WLB. The access transistor (access switch)  114  has a source-drain path connected between a bit line DBB and output of the inverter INV 4  and a gate connected to the word line WLB. The inverter INV 1  has an input connected to a node N 1  and an output connected to a node N 2 . The inverter INV 2  has an input connected to a node N 3  and an output connected to a node N 4 . The inverter INV 3  has an input connected to a node N 2  and an output connected to a node N 3 . The inverter INV 4  has an input connected to a node N 4  and an output connected to a node N 1 . The memory cell according to the present invention of  FIG. 1  is an SRAM memory cell which has two ports and which can be simultaneously accessed through the two ports. 
         [0032]    In the memory cell of  FIG. 1 , when the word line WLA is activated, the access transistors  111  and  112  are turned on, and data write or data read is carried out through the bit line pair DTA and DBA. On the other hand, when the word line WLB is activated, the access transistors  113  and  114  are turned on, and data write or data read is carried out through the bit line pair DTB and DBB. 
         [0033]    Data written in the memory cell is latched by the inverters INV 1 , INV 2 , INV 3 , and INV 4  in cascade connection (in a ring shape). When inverted data of the latched data is written through any one of the ports, outputs of the four inverters are inverted, respectively, and the held data is inverted. For example, when the node N 1  is at the high level, the nodes N 2 , N 3 , and N 4  are at the low level, at the high level, and at the low level, respectively. In this case, when data at the low level is written in the node N 1 , the nodes N 2 , N 3 , and N 4  are changed to be at the high level, at the low level, and at the high level, respectively. When data at the high level is written in the node N 2 , the nodes N 3 , N 4 , and N 1  are changed to be at the low level, at the high level, and at the low level, respectively. 
         [0034]    In this embodiment mode of  FIG. 1 , even when the word lines WLA and WLB are simultaneously activated and simultaneous access is made, the rate at which bit line potential changes is not lower than that in a case where access is made only through one of the ports. Because output of one inverter is connected to an access transistor provided correspondingly to one bit line, and thus, current through each access transistor is not decreased. 
         [0035]    When the word lines WLA and WLB are simultaneously activated with the input and the output of the inverter INV 4  being at the high level and at the low level, respectively, drive current from the inverter INV 4  (discharge current to GND) flows through the access transistor  111  to the bit line DTA. On the other hand, drive current from the inverter INV 3  (discharge current to GND) flows through the access transistor  113  to the bit line DTB. In this case, since the outputs of the inverters INV 2  and INV 4  are at the high level, the bit lines DBA and DBB are held at the high level which is precharge potential. Embodiments are described in the following. 
         [0036]      FIG. 2  illustrates an embodiment of a structure of the memory cell according to the present invention of  FIG. 1 . The SRAM memory cell of  FIG. 2  has the four inverters INV 1  to INV 4 . The inverter INV 1  has a PMOS transistor PM 1  and an NMOS transistor NM 1  connected in series between a power supply and GND. A gate of the PMOS transistor PM 1  and a gate of the NMOS transistor NM 1  are commonly connected to the node N 1 , and a connection point between a drain of the PMOS transistor PM 1  and a drain of the NMOS transistor NM 1  is the node N 2 . 
         [0037]    Similarly, the inverter INV 2  has a PMOS transistor PM 2  and an NMOS transistor NM 2  which are connected in series between a power supply and GND. A gate of the PMOS transistor PM 2  and a gate of the NMOS transistor NM 2  are commonly connected to the node N 3 , and a connection point between a drain of the PMOS transistor PM 2  and a drain of the NMOS transistor NM 2  is the node N 4 . 
         [0038]    The inverter INV 3  has a PMOS transistor PM 3  and an NMOS transistor NM 3  which are connected in series between a power supply and GND. A gate of the PMOS transistor PM 3  and a gate of the NMOS transistor NM 3  are commonly connected to the node N 2 , and a connection point between a drain of the PMOS transistor PM 3  and a drain of the NMOS transistor NM 3  is the node N 3 . 
         [0039]    The inverter INV 4  has a PMOS transistor PM 4  and an NMOS transistor NM 4  which are connected in series between a power supply and GND. A gate of the PMOS transistor PM 4  and a gate of the NMOS transistor NM 4  are commonly connected to the node N 4 , and a connection point between a drain of the PMOS transistor PM 4  and a drain of the NMOS transistor NM 4  is the node N 1 . 
         [0040]    In this embodiment, one driver transistor is connected to one access transistor of one port. In other words, one driver transistor is not shared by a plurality of access transistors. Therefore, even when the word lines WLA and WLB are simultaneously activated, current flowing through an access transistor of one port is not affected by an access transistor of the other port. Further, potential difference between a bit line pair is not narrowed compared with a case where a plurality of access transistors shares one driver transistor. Therefore, false sensing can be avoided. 
         [0041]    In  FIG. 2 , discharge paths of cell current Icell_A (True) and Icell_B (True) are illustrated. The bit lines DTA and DTB are discharged by the NMOS transistors NM 4  and NM 3  of the inverters INV 4  and INV 3  through the access transistors  111  and  113 , respectively. In  FIG. 2 , discharge paths of cell current Icell_A (Bar) and Icell_B (Bar) are also illustrated. The bit lines DBA and DBB are discharged by the NMOS transistors NM 1  and NM 2  of the inverters INV 1  and INV 2  through the access transistors  112  and  114 , respectively. In  FIG. 2 , when the word lines WLA and WLB are simultaneously activated, based on data held by the memory cell, cell current flows through any one of the pairs of Icell_A (True) and Icell_B (True) and of Icell_A (Bar) and Icell_B (Bar). It is to be noted that the bit line pair DTA and DBA and the bit line pair DTB and DBB are precharged, for example, before reading/writing operation to precharge potential (high level). In reading operation, one of precharged bit line pairs is discharged by the driver transistors (NM 1 , NM 2 , NM 3 , and NM 4  of  FIG. 2 ) of the inverters, based on data held by the memory cell. 
         [0042]      FIG. 3  illustrates a structure of a memory cell array having the memory cell of this embodiment. The memory cell array has memory cells  10  which are equivalent to the memory cell of  FIGS. 1 and 2 , a sense amplifier (SA)/writing driver (WD)  11  for a port A connected to the bit line pair DTA and DBA, a sense amplifier (SA)/writing driver (WD)  12  for a port B connected to the bit line pair DTB and DBB, a row decoder  13  for the port A for selectively driving the word line WLA of the port A, and a row decoder  14  for the port B for selectively driving the word line WLB of the port B. The sense amplifier (SA)/writing driver (WD)  11  for the port A inputs/outputs data DIA/DOA of the port A while the sense amplifier (SA)/writing driver (WD)  12  for the port B inputs/outputs data DIB/DOB of the port B. 
         [0043]    The above description is with regard to a 2-port RAM, but the present invention is not limited thereto, and applicable to multi-port RAMs having an arbitrary number of ports. 
         [0044]      FIGS. 4A ,  4 B, and  4 C illustrate exemplary structures of memory cells of 3-port RAMs as other embodiments. The 3-port RAM of  FIG. 4A  is a memory cell having 18 transistors. Two inverters and two access transistors are provided for each port. 
         [0045]    The memory cell of  FIG. 4A  has access transistors  111 ,  112 ,  113 ,  114 ,  115 , and  116  one ends of which are connected to bit lines DTA, DBA, DTB, DBB, DTC, and DBC and the other ends of which are connected to nodes N 1 , N 2 , N 3 , N 4 , N 5 , and N 6 , respectively, an inverter INV 1  an input and an output of which are connected to the nodes N 1  and N 2 , respectively, an inverter INV 2  an input and an output of which are connected to the nodes N 2  and N 3 , respectively, an inverter INV 3  an input and an output of which are connected to the nodes N 3  and N 4 , respectively, an inverter INV 4  an input and an output of which are connected to the nodes N 4  and N 5 , respectively, an inverter INV 5  an input and an output of which are connected to the nodes N 5  and N 6 , respectively, and an inverter INV 6  an input and an output of which are connected to the nodes N 6  and N 1 , respectively. 
         [0046]      FIGS. 4B and 4C  illustrate variations of a memory cell of a 3-port RAM. The memory cells of  FIGS. 4B and 4C  have combinations of connections of access transistors and bit lines connected to access transistors, the combinations being different from that in the memory cell of  FIG. 4A . The memory cells are similar to the memory cell of  FIG. 4A  in that one inverter is connected to one access transistor. 
         [0047]    A memory cell having four or more ports may also be formed in a similar way such that each port has two inverters and two access transistors. In other words, what is necessary is that an output of one inverter is connected to one access transistor. 
         [0048]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.