Abstract:
A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access interval to the main memory, a second acquiring device to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device, a determining device to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information, and a management device to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of U.S. patent application Ser. No. 11/151,344, filed on Jun. 14, 2005, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-194372, filed Jun. 30, 2004, the entire contents each of which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a computer system, a preload controller and method for controlling a preload access of data to a temporary memory, and a program. 
         [0004]    2. Description of the Related Art 
         [0005]    The performance of a processor that makes arithmetic processes has been rapidly improving along with the advance of the internal structure of pipeline processes, and the advance of the semiconductor techniques. By contrast, the improvement of the performance of a main memory that stores data used in the arithmetic processes falls behind that of the processor in terms of the data supply speed, and the data supply speed to the processor has not caught up with the arithmetic processing speed. For this reason, many computer systems normally comprise a temporary memory of data called a “cache” so as to absorb the speed difference between the processor and main memory device. 
         [0006]    The cache is a device which requires higher manufacturing cost per circuit scale than the main memory, but has a higher data supply speed than that of the main memory and is indispensable to bring out the arithmetic processing performance of the processor. 
         [0007]    When an access (read request) to data stored in the main memory device occurs, the cache is referred to in place of the main memory device. At this time, if requested data is cached, the data is read out from the cache and is sent to the processor. On the other hand, if the requested data is not cached, the requested data is transferred from the main memory to the cache via a system bus, and is then supplied to the processor. The reason why the data is transferred to the cache first is to prepare for the next access to identical data. A ratio indicating if data is cached when an access to the data stored in the main memory occurs is called a cache hit ratio. The cache hit ratio is one of the parameters that reflect the performance of the cache. 
         [0008]    In recent years, requirements for the cache performance become stricter. Especially, such trend is conspicuous in the application fields that process data in large quantities at high speed such as science technology calculations, multimedia processes, and the like. As described above, since the cache requires high cost, the storage size of the cache must be reduced in terms of cost. Inevitably, the use of the cache is limited to temporary storage of data. Therefore, the required data is not always cached. For example, if data associated with an access request is not always cached, i.e., if the cache hit ratio is too low, the data supply speed lowers to the same level as that when no cache is provided. 
         [0009]    Conventionally, the cache performance is improved by adding a new scheme for making a so-called “preload” process for reading out data required for a process onto the cache in advance. Some implementation methods of the preload process are known; for example, (1) a method that uses a prefetch command, and (2) a method that predicts access patterns. 
         [0010]    In the former method that uses a prefetch command, a prefetch command that specifies the address of data to be accessed is inserted onto a program. The prefetch command is a command for reading out data of the designated address onto the cache in advance. When the prefetch command is executed ahead of a command that uses data, the data is prefetched before the data is used actually, and is prepared on the cache in advance. 
         [0011]    In the latter method that predicts access patterns, a future access pattern is predicted on the basis of past data access patterns (history), thus executing a preload process. When data accesses are continuously made on addresses (e.g., accesses to sequence data), the addresses of data to be accessed are monitored, thus predicting the address of next data to be accessed. According to this prediction result, the preload process of data which will be required in the future is executed. In the same manner as in the former method, when data is to be used actually, the data is prepared on the cache and is temporarily stored. 
         [0012]    As described above, the performance can be improved by applying the preload scheme to the temporary storage, but the following problems are posed. 
         [0013]    In the above described method (1) that inserts a prefetch command in a program, it is not practical to adjust and provide a program to cope with different performance levels of individual computer systems. Hence, a program must be inevitably optimized with reference to a given performance value. As a result, the performance difference among computer systems cannot be taken into consideration, and the degree of improvement in performance varies depending on the performance of computer systems. 
         [0014]    In the above described method (2) based on prediction of access patterns, prediction has a limitation. For example, information such as which data access is important for a computation process, how many times that data access continues, and so forth cannot be predicted. In other words, there is an obvious bottleneck in regions other than access patterns that can be easily predicted. 
       BRIEF SUMMARY OF THE INVENTION 
       [0015]    The present invention is directed to provide a preload controller and method for controlling a preload access of data to a temporary memory in a computer system, and a program, so as to contribute to stable and effective performance improvement. 
         [0016]    According to one aspect of the present invention, there is provided a preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the read out data to a temporary memory. The controller comprises a first acquiring device configured to acquire access hint information which represents a data access interval to the main memory; a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of data via the bus by the bus access device; a determining device configured to determine a preload unit count based on the data access interval represented by the access hint information and the transfer delay time represented by the system information; and a management device configured to instruct the bus access device to read out data for the preload unit count from the main memory and to transfer the readout data to the temporary memory ahead of a data access of the data. 
         [0017]    A preload controller according to another aspect of the present invention is a preload controller for controlling an address translation device which is connected to a main memory via a bus, reads out address translation information from the main memory via the bus, and transfers the readout address translation information to a temporary memory. The controller comprises a first acquiring device configured to acquire access hint information which represents a data access interval to the main memory; a second acquiring device configured to acquire system information which represents a transfer delay time in transfer of address translation information via the bus by the address translation device; a determining device configured to determine a preload unit count on the basis of the data access interval represented by the access hint information and the transfer delay time represented by the system information; and a management device configured to instruct the address translation device to read out address translation information for the preload unit count from the main memory and to transfer the readout address translation information to the temporary memory ahead of address translation using the address translation information. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         [0018]      FIG. 1  is a block diagram showing a computer system according to the first embodiment of the present invention; 
           [0019]      FIG. 2  is a block diagram of a preload controller shown in  FIG. 1 ; 
           [0020]      FIG. 3  shows an example of access hint information received from a processor; 
           [0021]      FIG. 4  shows an example of an access hint information table; 
           [0022]      FIG. 5  shows an example of a data preload state table; 
           [0023]      FIG. 6  is a flowchart showing the overall procedure of a data preload process according to the first embodiment of the present invention; 
           [0024]      FIG. 7  is a flowchart pertaining to a pre-process of the data preload process in  FIG. 6 ; 
           [0025]      FIG. 8  is a flowchart pertaining to a continuous process of the data preload process in  FIG. 6 ; 
           [0026]      FIG. 9  is a block diagram showing a computer system according to the second embodiment of the present invention; 
           [0027]      FIG. 10  is a block diagram showing another computer system according to the second embodiment of the present invention; 
           [0028]      FIG. 11  is a block diagram of a preload controller shown in  FIG. 9 ; 
           [0029]      FIG. 12  shows an example of an address translation information preload state table; 
           [0030]      FIG. 13  is a flowchart showing the overall procedure of an address translation information preload process according to the second embodiment of the present invention; 
           [0031]      FIG. 14  is a flowchart pertaining to a pre-process of the address translation information preload process shown in  FIG. 13 ; 
           [0032]      FIG. 15  is a flowchart pertaining to a continuous process of the address translation information preload process shown in  FIG. 13 ; 
           [0033]      FIG. 16  is a block diagram showing a preload controller according to the third embodiment of the present invention; and 
           [0034]      FIG. 17  is a block diagram showing a computer system according to the fourth embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     First Embodiment 
       [0035]      FIG. 1  is a block diagram showing a computer system according to the first embodiment of the present invention. A computer system  101  includes a processor  102 , cache  103 , bus access unit  104 , bus  105 , main memory  106 , and preload controller  107 . The processor  102  accesses the cache  103  to fetch data used in an arithmetic process. If required data is not cached, the cache  103  instructs the bus access unit  104  to transfer data. The bus access unit  104  transfers the designated data from the main memory  106  via the bus  105 . The preload controller  107  controls a preload process on the basis of access hint information and system information obtained from the processor  102 , and instructs the bus access unit  104  to transfer required data. The access hint information and system information will be described later. 
         [0036]    Note that the bus access unit  104  may comprise a DMA controller for performing continuous data transfer. 
         [0037]    A local memory, which has no data transfer function between the cache and main memory, may be used in place of the cache  103 . The local memory is a high-speed memory as the cache  103 , and its data supply speed is higher than that of the main memory. Since the local memory has no automatic data transfer function with the main memory, the circuit scale can be suppressed accordingly. However, ahead of a data access on the main memory, data transfer between the local memory and main memory must explicitly be instructed. 
         [0038]    When the local memory is used in place of the cache  103 , data transfer between the local memory and main memory  106  is done by the bus access unit  104  on the basis of an instruction from the processor  102  or preload controller  107 . 
         [0039]      FIG. 2  is a block diagram of the preload controller  107  shown in  FIG. 1 . The preload controller  107  has a preload management unit  201 , access hint information table  202 , data preload state table  203 , and system information  204 . 
         [0040]    The preload management unit  201  executes a process for acquiring access hint information from the processor  102  and storing it in the access hint information table  202 , and a process for acquiring the system information  204 , and then executes a data preload process by identifying the start and end of an access to data. The access hint information table  202  stores access hint information. The data preload state table  203  stores information associated with a data preload process, which is in progress. 
         [0041]    The preload controller  107  may be implemented as software that executes a specific procedure by a processor different from the processor  102 . Note that the preload controller  107  may be implemented as software that runs on the processor  102  in place of another processor. 
         [0042]      FIG. 3  shows an example of access hint information received from the processor  102 . Access hint information  301  includes an ID (identifier), start address, access unit, stride, access interval, and access data count in this embodiment. The ID is used to identify the access hint information. The start address represents an address at which access starts. The access unit represents the size of data to be accessed together per data access. The stride denotes an address interval between a given access unit and the next access unit. For example, if the start address is 0x4000 and the stride is 8, the first data is located at 0x4000, the next data is located at 0x4008, and the second next data is located at 0x4010. When a negative value is designated as the stride, an access is made in a decreasing direction of addresses from the start address. The access interval represents a time interval between a given access unit and the next access unit. As a unit of time, the access hint information  301  uses a clock count, but a time may be designated directly. The access data count represents the number of data accesses associated with this access hint information. 
         [0043]      FIG. 4  shows an example of the access hint information table. The access hint information table stores a plurality of pieces of access hint information received from the processor  102 . Each of entries  401 ,  402 , and the like of the access hint information table  202  indicates individual access hint information, whose items are the same as those in the access hint information  301 . 
         [0044]      FIG. 5  shows an example of the data preload state table. The data preload state table  203  includes an ID, preload target address, access unit, stride, preload unit count, and remaining preload data count. An entry  501  of the data preload state table corresponds to the entry  401  of the access hint information table, and an entry  502  of the data preload state table corresponds to the entry  402  of the access hint information table. The entry  501  of the data preload state table indicates a state after eight preload accesses are completed, and the entry  502  of the data preload state table indicates a state after  512  preload accesses are completed. 
         [0045]    The ID, access unit, and stride are copied from the corresponding entry of the access hint information table. Note that the access unit and stride may not be copied to the data preload state table. For example, the entry of the access hint information table may be retrieved using the ID, and the access unit and stride stored in that entry may be used. 
         [0046]    The preload target address represents an address of data which is to undergo the next preload process. Since the entry  501  of the data preload state table indicates a state after eight preload accesses are completed, it gets ahead of the start address in the entry  401  of the access hint information table by 128 bytes (0x80 in hex) as the product of 16 bytes (stride) and 8. Likewise, the entry  502  of the data preload state table gets ahead of the start address of the entry  402  by 8192 bytes (0x2000 in hex). 
         [0047]    The preload unit count is calculated by the preload management unit  201  on the basis of the corresponding access hint information and system information. 
         [0048]    The remaining preload data count represents the remaining number of data which are to undergo a preload process. Since the entry  501  of the data preload state table indicates a state after eight preload accesses are completed, the remaining preload data count assumes a value obtained by decreasing  8  from the data access count in the entry  401  of the access hint information table. Likewise, the remaining preload data count in the entry  502  of the data preload state table assumes a value obtained by decreasing  512  from the data access count in the entry  402 . 
         [0049]    As for the system information, in the first embodiment of the present invention, the system information  204  indicates clocks of the processor  102  and a data transfer delay time of the bus access unit  104 , and is used to compute the preload unit count (to be described later). The system information  204  reflects the performance of this computer system, and may be directly acquired from the processor  102 , bus access unit  104 , or the like, or may be acquired via an operating system or the like. 
         [0050]      FIG. 6  is a flowchart showing the overall procedure of a data preload process according to the first embodiment of the present invention. The processor  102  notifies the preload controller  107  of the access hint information  301  in advance (step S 601 ). In this case, the preload controller  107  receives the access hint information  301  and stores it in the access hint information table  202 . Also, the preload controller  107  acquires the system information  204 . 
         [0051]    Next, a pre-process of the preload process is executed (step S 602 ). In the pre-process of the preload process, identification of the start of the preload process, an entry addition process to the data preload state table  203 , and the like are made. 
         [0052]    After that, a continuous process of the preload process is executed (step S 603 ). In the continuous process of the preload process, the end of a data access is identified, and the remaining data preload process is continued on the basis of the entry added to the data preload state table  203  prepared by the pre-process. 
         [0053]      FIG. 7  is a flowchart pertaining to the pre-process of the preload process shown in  FIG. 6 . Initially, the start of a data access corresponding to information stored in the access hint information table  202  is identified (step S 701 ). To identify the data access start, the processor  102  may notify the preload controller  107  of access start information appended with the ID or start address of the access hint information. Alternatively, a data transfer instruction to the bus access unit  104  may be monitored, and when that address is equal to the start address of the access hint information table  202 , it may be identified that the corresponding access has started. 
         [0054]    Corresponding access hint information is read out from the access hint information  202  (step S 702 ). The preload unit count is determined on the basis of clocks of the processor  102  and the data transfer delay time of the bus access unit  104  (step S 703 ). After the preload unit count is determined, a data acquisition instruction for the preload unit count from the start address is issued to the bus access unit  104  (step S 704 ). 
         [0055]    The preload target address is calculated from the start address and stride of the corresponding access hint information in accordance with the preload unit count, and the remaining preload data count is calculated from the data access count (step S 705 ). It is checked if the remaining preload data count is zero (step S 706 ). If the remaining preload data count is not zero, a new entry is added to the data preload state table  203  on the basis of the calculated preload start address, preload unit count, and remaining preload data count, and the access unit and stride of the corresponding access hint information (step S 707 ). 
         [0056]    Note that a practical calculation example of the preload unit count will be described. The preload unit count is given, for example, by: 
         [0000]    
       
         
           
             
               
                 
                   
                     Preload 
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                        
                       transfer 
                        
                       
                           
                       
                        
                       delay 
                        
                       
                           
                       
                        
                       time 
                     
                     
                       Data 
                        
                       
                           
                       
                        
                       access 
                        
                       
                           
                       
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                       time 
                     
                   
                 
               
               
                 
                   ( 
                   1 
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         [0057]    As the data transfer delay time, that of the bus access unit  104  can be used. As the data access time, a value obtained by dividing the access interval of the access hint information by clocks of the processor  102  can be used. In addition, as the data access time, a method of obtaining the behavior of the processor  102  from a command sequence to be executed during a data access, and estimating a processing time, a method of estimating by multiplying the number of commands included in a command sequence and the average processing time, or the like may be used. 
         [0058]    If a new entry is added to the data preload state table  203  in step S 707  in the pre-process of the data preload process shown in  FIG. 7 , the continuous process of the data preload process is executed. 
         [0059]      FIG. 8  is a flowchart pertaining to the continuous process of the data preload process in  FIG. 6 . 
         [0060]    Initially, the end of a data access corresponding to the entry of the data preload state table is identified (step S 801 ). To identify the data access end, the processor  102  may notify the preload controller  107  of access end information appended with the address of data, the access of which has ended. Alternatively, a data transfer instruction from the cache  103  to the bus access unit  104  may be monitored, and when that address is equal to the address of the preload instruction, it may be identified that the corresponding access has ended. 
         [0061]    The corresponding entry of the data preload state table is read out (step S 802 ), and data acquisition instructions for the data access end count from the preload target address of that entry are issued to the bus access unit  104  (step S 803 ). Subsequently, the preload target address and remaining preload data count are updated in accordance with the number of preload instructions in step S 803  (step S 804 ). It is checked if the remaining preload data count becomes zero as a result of updating (step S 805 ). If the remaining preload data count is not zero, the processes from step S 801  are repeated; otherwise, the corresponding entry of the data preload state table  203  is deleted (step S 806 ). 
         [0062]    According to the first embodiment of the present invention described above, the preload controller performs a data preload process on the basis of the access hint information of data and system information, which are provided in advance, in consideration of the system performance and the like, and can allocate data required by the processor on the temporary memory (cache) in advance. 
         [0063]    That is, since information associated with continuous data accesses in place of each individual data access is provided as the access hint information, the performance can be effectively improved by the preload process. Also, since the performance of the computer system is considered as the system information, such performance improvement is stable and has high flexibility. 
       Second Embodiment 
       [0064]    The second embodiment of the present invention relates to preload access of address translation information. The present invention can be similarly applied to an address translation scheme in addition to temporary storage (cache) of data described in the first embodiment. 
         [0065]    An overview of the address translation scheme will be explained first. In a multi-process method that simultaneously executes a plurality of programs on a computer system, a method of providing an identical address space to respective processes is normally used to facilitate development of programs used for respective processes. In this case, a virtual address space is provided to respective processes, and can be used as if a given process were occupying that address space. In a computer system that provides such function, an address translation unit such as a Memory Management Unit (MMU) is equipped to realize the virtual address space, and performs a translation process between the virtual address space and an actual (physical) address space of the computer system. This is called an “address translation process”. 
         [0066]    In the address translation process, address translation information indicating the relationship between the virtual address and actual (physical) address is used. It is a common practice to prepare the address translation information for each address translation unit such as a page size or the like. In this address translation unit, address translation is done using single address translation information. 
         [0067]    Since the computer system uses address information in large quantities, such information may be stored on the main memory. All data accesses require address translation, and address translation information is required every access. However, the data access performance deteriorates if the address translation information is read out from the main memory for each access. Hence, address translation information is temporarily stored on a high-speed address translation information cache such as a Translation Look-aside Buffer (TLB) or the like, and the cached address translation information is used, thus implementing high-speed address translation. 
         [0068]    The address translation information cache requires high cost per unit circuit area or the like as in the cache used for data compared to the main memory, but its data supply speed is higher than that of the main memory. Hence, the address translation information cache is indispensable to bring out the data access performance, and the arithmetic processing power of the processor depending on that performance. 
         [0069]    In the second embodiment, a preload controller controls a preload process that considers the system performance and the like on the basis of access hint information of data and system information, which are provided in advance, so as to allocate address translation information required for the address translation unit on a temporary memory (address translation information cache) in advance. 
         [0070]      FIG. 9  is a block diagram showing a computer system according to the second embodiment of the present invention. 
         [0071]    A computer system  901  includes a processor  902 , cache  903 , bus access unit  904 , bus  905 , main memory  906 , preload controller  907 , address translation unit  908 , and address translation information cache  909 . 
         [0072]    The processor  902  accesses the cache  903  to fetch data used in an arithmetic process. If required data is not cached, the cache  903  instructs the bus access unit  904  to transfer data. The bus access unit  904  instructs the address translation unit  908  to translate the address of the designated data. The address translation unit  908  translates the address on the basis of information on the address translation information cache  909 , and returns the result to the bus access unit  904 . The bus access unit  904  transfers data from the main memory  906  via the bus  905  using the translated address. The preload controller  907  controls a preload process on the basis of access hint information and system information obtained from the processor  902 , and instructs the address translation unit  908  to transfer required data. 
         [0073]    Note that the bus access unit  904  may comprise a DMA controller for performing continuous data transfer. 
         [0074]    A local memory which has no data transfer function between the cache and main memory may be used in place of the cache  903 . In this case, data transfer between the local memory and main memory is done by the bus access unit  904  on the basis of an instruction from the processor  902  or preload controller  907 . 
         [0075]    In the computer system  901 , the bus access unit  904  and preload controller  907  are connected, but they need not be connected. 
         [0076]      FIG. 10  is a block diagram showing another computer system according to the second embodiment of the present invention. Unlike in the computer system shown in  FIG. 9 , the address translation information cache is inserted between the processor and cache. 
         [0077]    A computer system  1001  includes a processor  1002 , cache  1003 , bus access unit  1004 , bus  1005 , main memory  1006 , preload controller  1007 , address translation unit  1008 , and address translation information cache  1009 . 
         [0078]    The processor  1002  instructs the address translation unit  1008  to acquire data used in an arithmetic process. The address translation unit  1008  translates the address of the data using information on the address translation information cache  1009 , and accesses the cache  1003  using the translated address. If required data is not cached, the cache  1003  instructs the bus access unit  1004  to transfer data. The bus access unit  1004  transfers data from the main memory  1006  via the bus  1005 . The preload controller  1007  controls a preload process on the basis of access hint information and system information obtained from the processor  1002  and instructs transfer of address translation information required for the address translation unit  1008 . 
         [0079]    Note that the bus access unit  1004  may comprise a DMA controller for performing continuous data transfer. 
         [0080]    A local memory which has no data transfer function between the cache and main memory may be used in place of the cache  1003 . In this case, data transfer between the local memory and main memory is done by the bus access unit  1004  on the basis of an instruction from the processor  1002  or preload controller  1007 . 
         [0081]    In the computer system  1001 , the bus access unit  1004  and preload controller  1007  are connected, but they need not be connected. 
         [0082]    The address translation information preload processes using the computer systems  901  and  1001  have the same processing contents, and the preload controllers  907  and  1007  also have the same arrangement and processing contents. Hence, the following description will be given using the computer system  901 . 
         [0083]      FIG. 11  is a block diagram of the preload controller shown in  FIG. 9 . The preload controller  907  has a preload management unit  1101 , access hint information table  1102 , address translation information preload state table  1103 , and system information  1105 . The preload management unit  1101  executes a process for receiving access hint information from the processor  902  and storing it in the access hint information table  1102 , and an address translation information preload process by identifying the start and end of an access to data. The access hint information table  1102  has the same configuration as the access hint information table  202 , and stores access hint information. The address translation information preload state table  1103  stores information associated with an address translation information preload process, which is in progress. 
         [0084]    The processing method of the preload controller  907  may be implemented as software by a processor different from the processor  902 . Alternatively, the preload controller  907  may be implemented as software that runs on the processor  902 . 
         [0085]    The access hint information and access hint information table  1102  used in this embodiment use the access hint information and access hint information table  202  explained in the first embodiment. 
         [0086]      FIG. 12  shows an example of the address translation information preload state table. The address translation information preload state table includes an ID, preload target address, stride, preload unit count, and remaining preload information count. 
         [0087]    An entry  1201  of the address translation information preload state table of this embodiment corresponds to the entry  401  of the access hint information table, and an entry  1202  of the address translation information preload state table corresponds to the entry  402  of the access hint information table. The entry  1201  of the address translation information preload state table indicates a state after one preload access is completed, and the entry  1202  of the address translation information preload state table indicates a state after two preload accesses are completed. 
         [0088]    The preload target address represents a pre-translation address of address translation information which is to undergo the next preload process. Since the entry  1201  of the address translation information preload state table indicates a state after one preload access is complete, it gets ahead of the start address in the entry  401  of the access hint information table by 0x1000 bytes as the product of 0x1000 bytes (stride) and 1. Likewise, the entry  1202  of the address translation information preload state table gets ahead of the start address of the entry  402  by 0x2000 bytes. 
         [0089]    The stride and preload unit count are calculated by the preload management unit  1101  on the basis of the corresponding access hint information and system information. 
         [0090]    The remaining preload information count represents the remaining number of pieces of address translation information, which are to undergo a preload process. 
         [0091]    As for the system information, in the second embodiment of the present invention, the system information  1105  indicates an address translation unit, clocks of the processor  902 , and a data transfer delay time of the bus access unit  904 , and is used to compute the stride and preload unit count (to be described later). The system information  1105  reflects the performance of this computer system, and may be directly acquired from the processor  902 , bus access unit  904 , or the like, or may be acquired via an operating system or the like. 
         [0092]      FIG. 13  is a flowchart showing the overall procedure of an address translation information preload process according to the second embodiment of the present invention. The processor  902  notifies the preload controller  907  of the access hint information  301  in advance (step S 1301 ). In this case, the preload management unit  1101  in the preload controller  907  receives the access hint information  301  and stores it in the access hint information table  1102 . Also, the preload controller  907  acquires the system information  1105 . 
         [0093]    Next, a pre-process of the preload process is executed (step S 1302 ). In the pre-process of the preload process, identification of the start of the preload process, an entry addition process to the address translation information preload state table  1103 , and the like are made. 
         [0094]    After that, a continuous process of the preload process is executed (step S 1303 ). In the continuous process of the preload process, the end of a data access is identified, and the remaining address translation information preload process is continued on the basis of the entry added to the address translation information preload state table  1103  prepared by the pre-process. 
         [0095]      FIG. 14  is a flowchart pertaining to the pre-process of the address translation information preload process shown in  FIG. 13 . Initially, the start of a data access corresponding to information stored in the access hint information table  1102  is identified (step S 1401 ). To identify the data access start, the processor  902  may notify the preload controller  907  of the ID of access start information appended with the ID or start address of the access hint information. Alternatively, a data transfer instruction to the bus access unit  904  may be monitored, and when that address is equal to the start address of the access hint information table  1102 , it may be identified that the corresponding access has started. 
         [0096]    Corresponding access hint information is read out from the access hint information  1102  (step S 1402 ). The stride and preload unit count are determined on the basis of the address translation unit, clocks of the processor  902  and the data transfer delay time of the bus access unit  904  as the system information  1105  (step S 1403 ). After the preload unit count is determined, an address translation information acquisition instruction for the preload unit count from the start address is issued to the address translation unit  908  (step S 1404 ). 
         [0097]    The preload target address is calculated from the start address and stride of the corresponding access hint information in accordance with the preload unit count, and the remaining preload information count is calculated from the data access count and address translation unit (step S 1405 ). It is checked if the remaining preload information count is zero (step S 1406 ). If the remaining preload data count is not zero, a new entry is added to the address translation information preload state table  1103  on the basis of the calculated preload start address, stride, preload unit count, and remaining preload information count (step S 1407 ). 
         [0098]    Note that a practical calculation example of the stride and preload unit count will be described. 
         [0099]    The stride is given, e.g., by: 
         [0000]    
       
         
           
             
               
                 
                   Stride 
                   = 
                   
                     
                       
                         ⌈ 
                         
                           
                             Stride 
                              
                             
                                 
                             
                              
                             of 
                              
                             
                                 
                             
                              
                             a 
                              
                             
                                 
                             
                              
                             data 
                              
                             
                                 
                             
                              
                             access 
                           
                           
                             Address 
                              
                             
                                 
                             
                              
                             translation 
                              
                             
                                 
                             
                              
                             unit 
                           
                         
                         ⌉ 
                       
                       · 
                       Address 
                     
                      
                     
                         
                     
                      
                     translation 
                      
                     
                         
                     
                      
                     unit 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0100]    When the stride of a data access is smaller than the address translation unit, identical address translation information can be used in a plurality of data accesses in some cases. Hence, an interval of use of address translation information often becomes longer than the data access interval. For this purpose, an address translation information use interval is calculated. 
         [0101]    The address translation information use interval is given, e.g., by: 
         [0000]    
       
         
           
             
               
                 
                   
                     Address 
                      
                     
                         
                     
                      
                     translation 
                      
                     
                         
                     
                      
                     information 
                      
                     
                         
                     
                      
                     use 
                      
                     
                         
                     
                      
                     interval 
                   
                   = 
                   
                     
                       
                         ⌊ 
                         
                           
                             Address 
                              
                             
                                 
                             
                              
                             translation 
                              
                             
                                 
                             
                              
                             unit 
                           
                           
                             Stride 
                              
                             
                                 
                             
                              
                             of 
                              
                             
                                 
                             
                              
                             a 
                              
                             
                                 
                             
                              
                             data 
                              
                             
                                 
                             
                              
                             access 
                           
                         
                         ⌋ 
                       
                       · 
                       Data 
                     
                      
                     
                         
                     
                      
                     access 
                      
                     
                         
                     
                      
                     interval 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0102]    Using the calculated value of the address translation information use interval, the preload unit count of address translation information is given, e.g., by: 
         [0000]    
       
         
           
             
               
                 
                   
                     Preload 
                      
                     
                         
                     
                      
                     unit 
                      
                     
                         
                     
                      
                     count 
                   
                   = 
                   
                     
                       Data 
                        
                       
                           
                       
                        
                       transfer 
                        
                       
                           
                       
                        
                       delay 
                        
                       
                           
                       
                        
                       time 
                     
                     
                       Address 
                        
                       
                           
                       
                        
                       translation 
                        
                       
                           
                       
                        
                       information 
                        
                       
                           
                       
                        
                       use 
                        
                       
                           
                       
                        
                       time 
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0103]    As the data transfer delay time, that of the bus access unit  904  can be used. As an address translation information use time, a value obtained by dividing the address translation information use interval by clocks of the processor  902  can be used. 
         [0104]    If a new entry is added to the address translation information preload state table  1103  in step S 1407  in the pre-process of the address translation information preload process shown in  FIG. 14 , the continuous process of the address translation information preload process is executed. 
         [0105]      FIG. 15  is a flowchart pertaining to the continuous process of the address translation information preload process in  FIG. 13 . Initially, the end of a data access corresponding to the entry of the address translation information preload state table is identified (step S 1501 ). 
         [0106]    To identify the data access end, the processor  902  may notify the preload controller  907  of access end information appended with the address of data, the access of which ends. Alternatively, a data transfer instruction from the cache  903  to the bus access unit  904  may be monitored, and when that address is equal to the address of the preload instruction, it may be identified that the corresponding access has ended. 
         [0107]    The corresponding entry of the address translation information preload state table is read out (step S 1502 ), and address translation information acquisition instructions for the data access end count from the preload target address of that entry are issued to the address translation unit  908  (step S 1503 ). Subsequently, the preload target address and remaining preload information count are updated in accordance with the number of preload instructions in step S 1503  (step S 1504 ). It is checked if the remaining preload information count becomes zero as a result of updating (step S 1505 ). If the remaining preload information count is not zero, the processes from step S 1501  are repeated; otherwise, the corresponding entry of the address translation information preload state table  1103  is deleted (step S 1506 ). 
         [0108]    A practical method of calculating the number of preload instructions of required address translation information from the data access end count will be explained. The number of pieces of address translation information which are to undergo the preload process uses the number of pieces of address translation information which are used after the end of data accesses. The number of preload instructions of address translation information is given, e.g., by: 
         [0000]    
       
         
           
             
               
                 
                   
                     Address 
                      
                     
                         
                     
                      
                     translation 
                      
                     
                         
                     
                      
                     information 
                      
                     
                         
                     
                      
                     preload 
                      
                     
                         
                     
                      
                     instruction 
                      
                     
                         
                     
                      
                     count 
                   
                   = 
                   
                     ⌊ 
                     
                       
                         Data 
                          
                         
                             
                         
                          
                         access 
                          
                         
                             
                         
                          
                         end 
                          
                         
                             
                         
                          
                         
                           count 
                           · 
                           Stride 
                         
                       
                       
                         Address 
                          
                         
                             
                         
                          
                         translation 
                          
                         
                             
                         
                          
                         unit 
                       
                     
                     ⌋ 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0109]    In place of every data access end count, a used address translation information count may be calculated from the total of all the data end counts, and a value obtained by subtracting the used address translation information count from the preload instructed address translation information count may be used as a preload instructed address translation information count. If that count is smaller than the preload unit count, a value obtained by subtracting the preload instructed address translation information count from the preload unit count may be used as the address translation information preload instruction count. 
         [0110]    According to the second embodiment of the present invention described above, the preload controller performs an address translation information preload process on the basis of the access hint information of data and system information, which are provided in advance, in consideration of the system performance and the like, and can allocate address translation information required by the address translation unit on the temporary memory (address translation information cache) in advance. 
       Third Embodiment 
       [0111]      FIG. 16  is a block diagram showing a preload controller according to the third embodiment of the present invention. 
         [0112]    The computer systems shown in  FIGS. 9 and 10  can execute the data preload process simultaneously with the address translation information preload process. The third embodiment shows an example of the internal arrangement of the preload controller  907  ( 1007 ) applied in such case. 
         [0113]    As shown in  FIG. 16 , both a data preload state table  1103  and address translation information preload state table  1104  are provided to a preload management unit  1101 . As access hint information and an access hint information table  1102 , the same ones as the access hint information  301  and access hint information table  202  described in the first embodiment are used. 
         [0114]    When the preload controller is as configured as shown in  FIG. 16 , the data preload process described in the first embodiment and the address translation information preload process described in the second embodiment can be simultaneously implemented. 
       Fourth Embodiment 
       [0115]      FIG. 17  is a block diagram showing a computer system according to the fourth embodiment of the present invention. As shown in  FIG. 17 , the computer system according to this embodiment has a plurality of processor units  901   a ,  901   b ,  901   c , . . . connected to a main memory  906  via a bus  905 . In  FIG. 17 , each processor unit has the same arrangement as the computer system  901  described in the second embodiment. Also, an arrangement which does not include an address translation unit and the like but includes only a data cache is available. 
         [0116]    According to the computer system of the fourth embodiment, the present invention can be independently embodied for each processor unit, and the advantage of the present invention is enhanced with increasing the number of processor units. 
         [0117]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.