Abstract:
A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Description:
[0001]    This Application is a division of U.S. patent application Ser. No. 12,983,477 filed on Jan. 3, 2011 which is a division of U.S. patent application Ser. No. 11/690,258 filed on Mar. 23, 2007, now U.S. Pat. No. 7,892,928 issued Feb. 22, 2011. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the field of method of forming asymmetric spacers; more specifically, it relates to forming spacers of different widths on opposite sides of a raised line, methods of fabricating semiconductor devices using asymmetric spacers and semiconductor having asymmetrical source/drain structures. 
       BACKGROUND OF THE INVENTION 
       [0003]    Asymmetric devices have drawn increasing attention as a method to suppress short channel effects in metal-oxide-silicon field effect transistors (MOSFETS). However, current technology forms asymmetrical devices by adding additional photolithographic process steps to existing methods. Additional photolithographic processes require additional photomasks and exposure tools and add additional time to the fabrication process, making such processes more costly and adversely effecting yield. Therefore, there is a need for a method of fabricating asymmetrical structures, including MOSFETs that do not require photolithographic steps to generate asymmetrical spacers. 
       SUMMARY OF THE INVENTION 
       [0004]    A first aspect of the present invention is a method, comprising: (a) forming on a top surface of a substrate, a structure comprising a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls and to the top surface of the substrate; after (a), (b) forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; after (b), (c) tilting the substrate about an axis parallel to the longitudinal axis relative to a flux of reactive ions directed toward the top surface of the substrate, the flux of reactive ions striking the conformal layer at an angle less than 90° and greater than zero degrees relative to the top surface of the substrate; and after (c), (d) exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate by the flux of reactive ions except in regions of the top surface of the substrate immediately adjacent to the sidewalls of the structure, the exposing leaving a first spacer on the first sidewall and a second spacer on the second sidewall. 
         [0005]    A second aspect of the present invention is a structure, comprising: a silicon layer having a top surface; a gate stack comprising a gate dielectric layer on the top surface of the silicon layer and an electrically conductive gate electrode on a top surface of the gate electrode or comprises the gate electrode on the gate dielectric layer, the gate dielectric layer extending along the top surface of the silicon layer on either side of the gate stack; a first spacer on a first sidewall of the gate stack and a second spacer on a second and opposite sidewall of the gate stack, a first width of the first spacer measured from the first sidewall in a first direction perpendicular to the first sidewall is less than a second width of the second spacer measured from the second sidewall in a second direction perpendicular to the second sidewall, the first and second spacers decreasing in width from a bottom surface of the gate stack to a top surface of the gate stack; a first source/drain extension in the silicon layer under the first spacer and a second source/drain extension in the silicon layer under the second spacer, the first and second source/drain extensions separated by a channel region in the layer under the gate stack; a first source/drain in the silicon layer abutting the first source/drain extension and extending away from the channel region and a second source/drain in the silicon layer abutting the second source/drain extension and extending away from the channel region, the first source/drain and the second source/drain both comprising silicon germanium or both comprising carbon-doped silicon. 
         [0006]    A third aspect of the present invention is a structure, comprising: a silicon layer having a top surface; a gate stack comprising a gate dielectric layer on the top surface of the silicon layer and an electrically conductive gate electrode on a top surface of the gate electrode or comprises the gate electrode on the gate dielectric layer, the gate dielectric layer extending along the top surface of the silicon layer on either side of the gate stack; a first spacer on a first sidewall of the gate stack and a second spacer on a second and opposite sidewall of the gate stack, a first width of the first spacer measured from the first sidewall in a first direction perpendicular to the first sidewall equal to a second width of the second spacer measured from the second sidewall in a second direction perpendicular to the second sidewall, the first and second spacers decreasing in width from a bottom surface of the gate stack to a top surface of the gate stack; a first source/drain extension in the silicon layer under the first spacer and a second source/drain extension in the silicon layer under the second spacer, the first and second source/drain extensions separated by a channel region in the layer under the gate stack; a first diffused-source/drain in the silicon layer abutting the first source/drain extension and extending away from the channel region and a second diffused-source/drain in the silicon layer abutting the second source/drain extension and extending away from the channel region; and a first hetero-source/drain in the silicon layer, abutting the first source/drain extension and extending away from the channel region and a second hetero-source/drain in the silicon layer separated from the second source/drain extension by the second diffused-source/drain and extending away from the channel region, the first hetero-source/drain and the second hetero-source/drain both comprising silicon germanium or both comprising carbon-doped silicon. 
         [0007]    A fourth aspect of the present invention is a structure, comprising: a silicon layer having a top surface; a gate stack comprising a gate dielectric layer on the top surface of the silicon layer and an electrically conductive gate electrode on a top surface of the gate electrode or comprises the gate electrode on the gate dielectric layer, the gate dielectric layer extending along the top surface of the silicon layer on either side of the gate stack; a first spacer on a first sidewall of the gate stack, a second spacer on a second and opposite sidewall of the gate stack and a third spacer on the second spacer, a first width of the first spacer measured from the first sidewall in a first direction perpendicular to the first sidewall equal to a second width of the second spacer measured from the second sidewall in a second direction perpendicular to the second sidewall, the first, second and third spacers decreasing in width from a bottom surface of the gate stack to a top surface of the gate stack; a first source/drain extension in the silicon layer under the first spacer and a second source/drain extension in the silicon layer under the second and third spacers, the first and second source/drain extensions separated by a channel region in the layer under the gate stack; a first source/drain in the silicon layer abutting the first source/drain extension and extending away from the channel region and a second source/drain in the silicon layer abutting the second source/drain extension and extending away from the channel region, a first distance between the first source/drain and the channel region measured through the first source/drain extension region less than a second distance between the second source/drain and the channel region measured through the second source/drain extension region. 
         [0008]    A fifth aspect of the present invention is an apparatus, comprising: a chamber having a gas inlet and an exhaust port connected to a vacuum pump; a magnetic filter positioned between means for generating an electron/reactive gas ion plasma from a gas supplied through the gas inlet and means for holding a substrate at a pre-selected angle between 0° and 90° relative to a plane defined by the magnetic filter; and means for applying a bias voltage to the means for holding the substrate. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0010]      FIGS. 1A and 1B  illustrate fabrication of asymmetrical spacers according to embodiments of the present invention; 
           [0011]      FIG. 2A  is a schematic representation of an exemplary apparatus for fabricating asymmetrical spacers according to embodiments of the present invention; 
           [0012]      FIG. 2B  is a diagram illustrating the method of keeping incident species normal to a wafer being etched in the exemplary apparatus of  FIG. 2B ; 
           [0013]      FIGS. 3A through 3E  are cross-sectional drawings illustrating fabrication of a first MOSFET device according to embodiments of the present invention; 
           [0014]      FIGS. 3F through 3H  are cross-sectional drawings illustrating additional steps for fabricating a second MOSFET according to embodiments of the present invention; 
           [0015]      FIGS. 4A through 4C  are cross-sectional drawings illustrating fabrication of a third MOSFET device according to embodiments of the present invention; 
           [0016]      FIG. 5  is a cross-sectional drawing of the first MOSFET device fabricated on a silicon-on-insulator (SOI) substrate; 
           [0017]      FIG. 6  is a cross-sectional drawing of the second MOSFET device fabricated on an SOI substrate; and 
           [0018]      FIG. 7  is a cross-sectional drawing of the third MOSFET device fabricated on a 
           [0019]    SOI substrate. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]      FIGS. 1A and 1B  illustrate fabrication of asymmetrical spacers according to embodiments of the present invention. In  FIG. 1 , formed on a substrate  100  is a gate stack  110  comprising a dielectric layer  115  on a top surface  105  of the substrate, an electrically conductive gate electrode  120  on top of the dielectric layer and an optional dielectric capping layer  125  on top of the gate electrode. Formed on top surface  105  and sidewalls and a top surface of gate stack  110  is a conformal dielectric layer  130 . A conformal layer is usually formed by a blanket deposition of a material to form a coating that follows the contours of the surface(s) being coated as opposed to a non-conformal layer where low spots in the surface being coated are filled in to give a flat or quasi-flat surface to the deposited layer. In one example, a conformal layer covers horizontal (e.g. top surface  105  defining the horizontal plane) and vertical surfaces (e.g. sidewalls of gate stack  110 ) to about the same thickness. The thickness of the layer may be less or greater on vertical surfaces than on horizontal surfaces. Substrate  100  is positioned in a flux of reactive ions  138  (i.e. reactive with conformal layer  130 ) with top surface  105  of substrate  100  forming an acute (less than 90°) angle θ to the direction of the reactive ion flux, which etches conformal layer  130 . 
         [0021]    In  FIG. 1B , after reactive ion etch (RIE) of conformal layer  130  (see  FIG. 1A ), asymmetrical sidewall spacers  135 A and  135 B have been formed on opposite sidewalls of gate stack  110 . Spacer  135 A has been formed on the gate stack  110  sidewall that was closest to the reactive ion flux and spacer  135 B has been formed on the gate stack  110  sidewall that was furthest from the reactive ion flux. Spacer  135 A extends along top surface  105  of substrate  100  a distance D 1  from gate stack  110  and spacer  135 B extends along top surface  105  of substrate  100  a distance D 2  from gate stack  110 . D 2  is greater than D 1 . 
         [0022]    In one example, substrate  100  is a single-crystal bulk silicon wafer or an SOI wafer (wafers are generally flat circular disks.) In one example, gate dielectric layer  115  comprises silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon carbide (Si:C), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), organosilicate glass (Si:COH), plasma-enhanced silicon nitride (PSiN x ) or NBLok (Si:C(N,H)). In one example gate dielectric layer  115  is a high K (dielectric constant) material, examples of which include but are not limited to metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3 , or metal silicates such as HfSi x O y  or HfSi x O y N z  or combinations of layers thereof. A high K dielectric material has a relative permittivity above about 10. In one example, gate dielectric layer  115  is about 0.5 nm to about 20 nm thick. In one example, gate electrode  120  comprises polysilicon, doped polysilicon, metal, metal silicide or combinations thereof. In one example, capping layer  125  comprises SiO 2 , Si 3 N 4 , Si:C, SiON, SiOC, Si:COH, PSiN x  or Si:C(N,H). In one example, capping layer  125  is about 5 nm to about 200 nm thick. In one example, spacers  135 A and  135 B comprise SiO 2  or Si 3 N 4 . 
         [0023]    While gate dielectric layer  115  is illustrated in  FIGS. 1A and 1B  as extending only under gate electrode  120 , alternatively, gate dielectric layer  115  may extend over the entire top surface  105  and particularly under spacers  135 A and  135 B. With gate dielectric layer  115  covering top surface  105 , substrate  100  is protected from attack by the reactive ion flux during the RIE and exposed gate dielectric layer may be removed at any appropriate step after formation of spacers  135 A and  135 B. 
         [0024]    It should be understood that the present invention is not limited to forming asymmetrical spacers on a gate stack, but can be applied to forming asymmetrical spacers on any mesa-like structure having a top surface and two opposing sidewalls. 
         [0025]      FIG. 2A  is a schematic representation of an exemplary apparatus for fabricating asymmetrical spacers according to embodiments of the present invention. In  FIG. 2A , an RIE tool  140  includes a process chamber  145 , a gas inlet  150  (or inlets) and exhaust port  155 , inductive coils  160  (coupled to a plasma power supply, not shown), a tiltable stage  165  and an array of magnetic filter cores  170 . In operation, substrate  100  is placed on stage  165  and the stage tilted at an angle of (90-θ)° (θ was defined supra) and a non-equilibrium high density plasma (e.g. about 10 12  to about 10 13  ions/cm 3 ) is struck. Reactive ions formed in the plasma are drawn toward stage  165 , passing between magnetic filter cores  170 , by a biasing voltage applied to stage  165 . A fixed stage (i.e. θ is fixed) may be substituted for tiltable stage  165 . A flux of reactive ions then passes through magnetic filter cores  170  and strike wafer  100  at an angle θ relative to the top surface of the substrate. Magnetic filter cores  170  are spaced apart a distance S 1 , which is less than half the gyroradius of an electron at the magnetic field strength generated by the magnetic filter cores. In one example, a magnetic field of about 5G to about 500G is generated by magnetic filter cores  170 . A typical etchant gas for SiO 2  or Si 3 N 4  is CH x F 4-x . Alternatively, the plasma may be capacitively coupled to the plasmas generating power supply instead of being inductively coupled to the power supply. 
         [0026]      FIG. 2B  is a diagram illustrating the method of keeping incident species normal to a wafer being etched in the exemplary apparatus of  FIG. 2B . Lines  175  represent the magnetic field B. The path of electrons (e−), positive ions (n+), and negative ions (n−) are illustrated. Electrons do not pass through the magnetic field while ions pass through perpendicular to the field. The gyroradius r g  defines the radius of circular motion of a charged particle in the presence of a uniform magnetic field and is given by equation (1): 
         [0000]    
       
         
           
             
               
                 
                   
                     r 
                     g 
                   
                   = 
                   
                     
                       mv 
                       ⊥ 
                     
                     
                       
                          
                         q 
                          
                       
                        
                       B 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where:
   m is the mass of the charged particle,   ν ⊥ is the velocity component perpendicular to the direction of the magnetic field,   q is the charge on the particle, and   B is the constant magnetic field.
 
For a typical electron at less than 20 eV, its gyroradius under a 50 G applied magnetic field is approximately 0.5 cm. By setting S 1  to less than 1 cm, all electrons with electron temperature less than 20 eV will be excluded from the region below magnetic filter cores  170  (see  FIG. 2A ), whereas less mobile ions (positive or negative) will not. This results in a flux of charged ions only through the magnetic filter region, and a consequent build-up of ion-ion plasma between the magnetic filter and the substrate. Since the formation of a sheath just above the surface of a substrate in a plasma environment requires a differential mobility between charged species in gaseous plasma (e.g. electrons and ions), there is no sheath formed above substrate  100  in the inventive method because electrons have been excluded from the region just above the substrate by magnetic filter cores  170  and a self-bias is generated in the direction normal to the wafer surface. Reactive neutral species are still present above the wafer. With appropriate chemistry selection etching will proceed preferentially on the spacer sidewall titled toward the incident ion flux.
   
 
         [0031]      FIGS. 3A through 3E  are cross-sectional drawings illustrating fabrication of a first MOSFET device according to embodiments of the present invention. In  FIG. 3A , formed on substrate  100  is gate stack  110  comprising dielectric layer  115  on top surface  105  of the substrate, electrically conductive gate electrode  120  on top of the dielectric layer and optional dielectric capping layer  125  on top of the gate electrode. A source/drain extensions  180  have been formed on opposite sides of gate stack  110  by, for example, ion implantation of a dopant species such as arsenic, phosphorus or boron using the gate stack as an ion implantation mask. A trench isolation  185  is formed in substrate  100  abutting source/drain extensions  180 . 
         [0032]    In one example, trench isolation is formed prior to formation of gate stack  110 . Trench isolation  185  extends from top surface  105  of substrate  100  into the substrate. Trench isolation  185  may be formed by etching a trench into substrate  100 , depositing a dielectric layer over substrate  100  to completely fill the trenches and then performing a chemical-mechanical polish to coplanarize top surface  105  of substrate  100  and a top surface of trench isolation  185 . In one example, trench isolation comprises high-density plasma (HDP) silicon oxide or chemical-vapor-deposition (CVD) tetraethoxysilane (TEOS) oxide. In one example, trench isolation  185  comprises a dielectric liner, such as SiO 2  and a polysilicon core. 
         [0033]    In  FIG. 3B , formed on top surface  105  and on sidewalls and the top surface of gate stack  110  is conformal dielectric layer  130 . 
         [0034]    In  FIG. 3C , a tilted RIE process as illustrated in  FIGS. 1A ,  1 B,  2 A and  2 B and described supra has been performed to form asymmetrical spacers  135 A and  135 B. Spacers  135 A and  135 B extend over source/drain extensions  180  toward trench isolation and do not completely cover the source/drain extensions. 
         [0035]    In  FIG. 3D , trenches  190  are etched through source/drain extensions  180  into substrate  100  to form a first source/drain extensions  180 A under spacer  135 A and a second source/drain extensions  180 B under spacer  135 B, where the source/drain extensions  180  (see  FIG. 3C ) was not protected by spacers  135 A and  135 B. Trenches  190  are bounded by trench isolation  185  on one side as shown and on opposite ends not shown, see discussion infra. 
         [0036]    In  FIG. 3E , a first hetero-source/drain  195 A and a second hetero-source/drain  195 B of an FET  205 A are formed by epitaxially growing silicon germanium (SiGe) if FET  205 A is a p-channel FET (PFET) or carbon-doped silicon (Si:C) if FET  205 A is an n-channel FET (NFET), in trenches  190  (see  FIG. 2D ). If FET  205 A is a PFET, first and second source/drain extensions  180 A and  180 B are doped P-type and substrate  100  is doped N-type) or the region of substrate  100  illustrated in  FIG. 3E  is doped N-type (i.e. is an N-well). If FET  205 A is a NFET, first and second hetero-source/drains  195 A and  195 B, first and second source/drain extensions  180 A and  180 B are doped N-type and substrate  100  is doped P-type) or the region of substrate  100  illustrated in  FIG. 3E  is doped P-type (i.e. is a P-well). First source/drain extension  180 A has length L 1  and second source/drain extension  180 B has a length L 2 , with L 2  greater than L 1 . It should be understood, that the cross-sections of  FIGS. 1A ,  1 B,  3 A,  3 B,  3 C,  3 D,  3 E,  3 F,  3 G,  3 H,  4 A,  4 B,  4 C,  5 ,  6  and  7  are in a lengthwise direction, with a widthwise direction running into and out of the plane of the drawing, the lengthwise direction and widthwise direction being perpendicular and lying in a plane parallel to a plane defined by top surface  105  of substrate  100 . Trench isolation  185  surrounds FET  205 A along the entire perimeter of FET  205 A. From an end view of FET  205 A (also FET  205 D of  FIG. 5 ), trench isolation  185  would abut first and second hetero-source/drains  195 A and  195 B, first and second source/drain extensions  180 A and  180 B and channel region  200  laterally isolating the FET. 
         [0037]    Because of the SiGe or Si:C source/drains, a channel region  200  between the first source/drain extensions  180 A and the second source/drain extensions  180 B under gate  120  is under compressive or tensile stress, so FET  205 A is a strained FET. Further, because L 1  is not equal to L 2 , FET is also an asymmetrical FET. First and second hetero-source/drains  195 A and  195 B may be doped in-situ during epitaxial growth (to form a self-aligned source/drains) or doped afterwards by ion implantation other suitable techniques such as plasma doping. 
         [0038]      FIGS. 3F through 3H  are cross-sectional drawings illustrating additional steps for fabricating a second MOSFET according to embodiments of the present invention. In  FIG. 3F , first and second spacers  180 A and  180 B of  FIG. 3E  are removed by wet or dry etching. 
         [0039]    In  FIG. 3G , conventional symmetrical spacers  210 A and  210 B are formed on opposite sidewalls of gate stack  110 . Conventional spacers are formed depositing a conformal layer followed by RIE etching the conformal layer with the substrate top surface perpendicular to the direction of the reactive ion flux (e.g. θ=90°). Both spacers  210 A and  210 B extend along top surface  105  of substrate  100  a distance D 3  from gate stack  110  toward trench isolation  185 . A portion  212  of second source/drain extensions  180 B is not covered by spacer  210 B, while all of spacer  180 A is covered by spacer  210 A. 
         [0040]    In  FIG. 3H , an FET  205 B is completed by forming first and second diffused-source/drains  215 A and  215 B in substrate  100  by ion implantation or plasma doping (of a P-type dopant if FET  205 B is a PFET and an N-type dopant if FET  205 B is an NFET) where the substrate is not protected by gate stack  110 , spacers  210 A and  210 B or trench isolation  185 . From an end view of FET  205 B (also FET  205 E of  FIG. 6 ), trench isolation  185  would abut first and second hetero-source/drains  195 A and  195 B, first and second diffused-source/drains  215 A and  215 B, first and second source/drain extensions  180 A and  180 B and channel region  200  laterally isolating the FET. 
         [0041]      FIGS. 4A through 4C  are cross-sectional drawings illustrating fabrication of a third MOSFET device according to embodiments of the present invention. In  FIG. 4A , formed on substrate  100  is gate stack  110  comprising dielectric layer  115  on top surface  105  of the substrate, electrically conductive gate electrode  120  on top of the dielectric layer and optional dielectric capping layer  125  on top of the gate electrode. Source/drain extensions  180  have been formed on opposite sides of gate stack  110 . Trench isolation  185  has been formed in substrate  100  abutting source/drain extensions  180 . And conventional symmetrical spacers  220 A and  220 B have been formed on opposite sidewalls of gate stack  110 . Both spacers  220 A and  220 B extend along top surface  105  of substrate  100  a distance D 4  from gate stack  110  toward trench isolation  185 . 
         [0042]    In  FIG. 4B , a spacer  225 B is formed over spacer  220 B. Spacers  220 A and  220 B are a different material than the material of spacer  220 B. Spacer  225 B is formed by performing a tilted RIE process as described supra, at a sufficient angle and length of time so as to remove any spacer that might be formed on spacer  220 A. Alternatively, by adjustment of angle and time, a spacer  225 A (dashed lines) will be formed simultaneously with spacer  225 B. Spacer  225 A will have a smaller width than that of spacer  225 B (see for example,  FIG. 1B ). 
         [0043]    In  FIG. 4C , an FET  205 C is completed by forming source/drains  215 A and  215 B in substrate  100  by ion implantation (of a P-type dopant if FET  205 B is a PFET and an N-type dopant if FET  205 B is an NFET) where the substrate is not protected by gate stack  110 , spacers  210 A,  210 B and  220 B and trench isolation  185 . In  FIG. 4C , a first source/drain extensions  180 C has length L 3  and second source/drain extensions  180 D has a length L 4 , with L 4  greater than L 3 . In one example, spacers  220 A and  220 B are SiO 2  and spacers  225 B (and  225 A, if present) are Si 3 N 4 . From an end view of FET  205 C (also FET  205 F of  FIG. 7 ), trench isolation  185  would abut first and second diffused source/drains  215 A and  215 B, first and second source/drain extensions  180 A and  180 B and channel region  200  laterally isolating the FET. 
         [0044]    In order to fabricate a fourth MOSFET device according to the present invention, it is necessary to return to  FIG. 4B . At this point in the process, trenches  190 A may be formed in substrate  100  where the substrate is not protected by gate stack  110 , spacers  220 A,  220 B and  225 B (and  225 A if present) and trench isolation  185  and then filled with either SiGe or Si:C as described supra, in which case source/drains  215 A and  215 B of  FIG. 4C  would both include SiGe or Si:C. 
         [0045]      FIG. 5  is a cross-sectional drawing of the first MOSFET device fabricated on a SOI substrate. In  FIG. 5 , an FET  205 D is similar to FET  205 A of  FIG. 3E  except, trench isolation  185 , hetero-source/drains  195 A and  195 B, source/drain extensions  180 A and  180 B and channel region  200  are formed in a single-crystal silicon layer  230  separated from substrate  100  by a buried insulating layer such as buried oxide layer (BOX)  235 . Trench isolation abuts BOX  235 . In one embodiment, hetero-source/drains  195 A and  195 B also abut BOX  235 . 
         [0046]      FIG. 6  is a cross-sectional drawing of the second MOSFET device fabricated on an SOI substrate. In  FIG. 6 , an FET  205 E is similar to FET  205 B of  FIG. 3H  except, trench isolation 185, hetero-source/drains  195 A and  195 B, diffused source/drains  205 A,  205 B source/drain extensions  180 A and  180 B and channel region  200  are formed in a single-crystal silicon layer 230 separated from substrate  100  by BOX  235 . Trench isolation abuts BOX  235 . In one embodiment, diffused source/drains  205 A and  205 B also abut BOX  235 . 
         [0047]      FIG. 7  is a cross-sectional drawing of the third MOSFET device fabricated on a SOI substrate. In  FIG. 7 , an FET  205 F is similar to FET  205 C of  FIG. 4C  except, trench isolation  185 , diffused source/drains  215 A and  215 B,  205 B source/drain extensions  180 A and  180 B and channel region  200  are formed in a single-crystal silicon layer  230  separated from substrate  100  by BOX 235. Trench isolation  185  abuts BOX  235 . In one embodiment, diffused source/drains  215 A and  215 B also abut BOX  235 . 
         [0048]    Thus the present invention provides a method of fabricating asymmetrical spacers and asymmetrical MOSFETs without defining the asymmetrical elements with photolithographic steps. 
         [0049]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.