Abstract:
A system and method is described for fabricating microcomponents onto pre-existing integrated electronics. One embodiment of the present invention provides additional process steps after completion of all electronics fabrication that may etch trough the oxide of any passivation layer that may be there to the single crystal silicon (SCS) of a silicon on insulator (SOI) integrated circuit. Once at the SCS level of the existing wafer, any number of microcomponents, such as connectors, receptacles, handles, tethers, and the like may preferably be fabricated onto the chip using relatively low temperature and inexpensive processing; thus, preferably preserving the integrity of the preexisting electronics.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to commonly assigned U.S. patent application Ser. No. 09/570,170, filed May 11, 2000, entitled “SYSTEM AND METHOD FOR COUPLING MICRO-COMPONENTS”; U.S. Pat. No. 6,398,280, issued Jun. 4, 2002, entitled “GRIPPER AND COMPLEMENTARY HANDLE FOR USE WITH MICROCOMPONENTS”; Ser. No. 09/616,500, filed Jul. 14, 2000, entitled “SYSTEM AND METHOD FOR CONSTRAINING TOTALLY RELEASED MICROCOMPONENTS”; Ser. No. 09/643,011, filed Aug. 21, 2000, entitled “SYSTEM AND METHOD FOR COUPLING MICROCOMPONENTS UTILIZING A PRESSURE FITTING RECEPTACLE”; and Ser. No. 10/071,772, filed Feb. 7, 2002, entitled “SYSTEM AND METHOD FOR LATCHING A MICRO-STRUCTURE AND A PROCESS FOR FABRICATING A MICRO-LATCHING STRUCTURE,” the disclosures of which are hereby incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present application relates in general to sub-millimeter devices, and more particularly, to a system and method for fabricating Microelectromechanical (MEM) devices into pre-existing integrated circuits. 
     BACKGROUND OF THE INVENTION 
     MEM devices have many applications for forming any variety of microsensors, microactuators, and other microcomponents. The term “microcomponent” is used herein generically to encompass sub-millimeter electronic components, sub-millimeter mechanical components, as well as MEM devices and MEM Systems (MEMS) components. The monolithic integration of MEM devices with electronic circuitry has been suggested to increase performance, functionality, and reliability of such microcomponents, in addition to significantly reducing the size and cost of the components. Such electronic circuitry may comprise simple electronic components, such as amplifiers having only a few transistors, to complex electronics, such as microprocessors or microcontrollers. The microcomponents typically act as the sensor that relates information to the electronics for processing in some fashion. Typically, because of the incompatibilities between integrated circuit fabrication techniques and MEM device fabrication techniques, methods for integrating electronic circuits and MEM devices have been suggested which either require complex interleaving of fabrication steps or requiring the fabrication of the MEM device first followed by the electronic circuitry. 
     U.S. Pat. No. 5,326,726 issued to Tsang, et al., discloses such an interleaved or merged process for fabricating a monolithic chip integrating both electronic circuitry with microstructures. In Tsang, et al., the process described fabricating both the electronic circuitry and the microstructure transducer wherein the steps of fabricating the microstructure transducer are generally interleaved among the steps for fabricating the BIMOS circuitry. 
     U.S. Pat. No. 5,963,788 issued to Barron, et al., discloses another process that fabricates a high quality MEM device before fabrication of the electronic circuitry. The high quality MEM device of Barron, et al., is produced in a mesa (i.e., a cavity etched within the substrate). The processes described in Barron, et al., for fabricating the MEM device typically involve an annealing step that generally raises the temperature to approximately 1100° centigrade for around an hour. Such a high temperature would generally destroy any pre-fabricated electronic circuitry. Thus, the Barron, et at, process requires that the MEMs device be fabricated first. 
     The problem with the current systems and methods for monolithically fabricating integrating electronic circuitry with MEMs devices is that fabrication processes for the electronics are typically connected or tied in some way to the fabrication of the MEMs device. Therefore, a microcomponent could not be added to existing electronic circuitry. For example, if an integrated circuit chip design includes all of the favorable processing for a certain system, no microcomponents could be added, as they are developed, in order to improve the application of the system. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to a system and method for fabricating microcomponents onto pre-existing/pre-fabricated integrated electronics. One embodiment of the present invention provides additional process steps after completion of all electronics fabrication that etches through the oxide of the passivation layer to the single crystal silicon (SCS) layer of a silicon on insulator (SOI) integrated circuit (IC). Once at the SCS layer of the existing wafer, any number of microcomponents, such as connectors, receptacles, handles, tethers, fasteners, clasps, latches, probes, actuator arms, and the like may be fabricated onto the chip using relatively low temperature and inexpensive processing; thus, preserving the pre-existing electronics. 
     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which: 
     FIG. 1 is a cross-sectional view of a typical, prior art SOI integrated circuit with pre-fabricated electronics; 
     FIG. 2A is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including a patterned layer of resist; 
     FIG. 2B is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including openings etched through a passivation layer; 
     FIG. 2C is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including openings etched through an SCS layer; 
     FIG. 2D is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including a patterned sacrificial layer; 
     FIG. 2E is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including openings etched through the passivation layer, 
     FIG. 2F is across-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including a layer of tether material; 
     FIG. 2G is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including the etched tether material; 
     FIG. 2H is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including an opening etched in the backside of the SOI wafer; 
     FIG. 21 is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention including a patterned and etched layer of resist spun onto the pre-fabricated electronics; 
     FIG. 2J is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention after the exposed oxide layers are removed; 
     FIG. 2K is a cross-sectional view of a SOI integrated circuit according to the teachings of an embodiment of the present invention after removing the remaining photoresist layers; and 
     FIG. 3 is an isometric view of a MEMs device configured and fabricated according to the teachings of an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a cross-sectional diagram of a typical electronic component integrated onto an SOI integrated circuit. An SOI integrated circuit typically comprises SCS layer  100 , buried oxide layer  101  (BOx), and handle layer  102 , generally comprising a silicon substrate. A passivation or scratch layer may be included on SCS  100  comprising field oxide  103  in some embodiments. The electronic circuitry component of SOI chip  10  is generally found within the area marked by dotted line  104 . Electronics island  104  is illustrated as a single transistor including electrical contacts  105 ,  106 , and  107 . 
     One embodiment of the present invention provides a system and method for adding microcomponents to pre-fabricated SOI chip  10  of FIG.  1 . The steps of the inventive method are depicted in FIGS. 2A through 2K FIG. 2A is a cross-sectional diagram of SOI chip  10  preferably including an additional layer of resist  200 . Resist layer  200  may comprise any number of the different, known negative or positive photoresist chemicals applied to SOI chip  10 . Resist layer  200  also preferably includes pattern etches at openings  201 ,  202 , and  203 . Pattern openings  201 ,  202 , and  203  allow the etching process to reach field oxide layer  103 . Openings in field oxide layer  103  maybe etched to expose SCS layer  100 . FIG. 2B illustrates SOI chip  10  after etching through resist layer  200  exposing the substrate. The SOI chip depicted in FIG. 2B illustrates the etched openings in the field oxide layer  103  at openings  204 ,  205 , and  206 . With the openings of field oxide layer  103 , SCS layer  100  is now exposed and ready for further processing. 
     FIG. 2C is a cross-sectional diagram of processed SOI chip  10  illustrating the etched paths  207 ,  208 , and  209  that have been etched through SCS layer  100 . The process of etching through SCS layer  100  allows the fabrication of any number or variety of different micromechanical components. For example, connectors, receptacles, handles, tethers, fasteners, clasps, latches, probes, actuators, and the like may be fabricated onto the chip allowing for further processing by other microcomponents. Embodiments of such technology that incorporate connectors, receptacles, handles, and tethers have been demonstrated in commonly-owned, co-pending patent applications commonly assigned U.S. patent application Ser. No. 09/570,170, filed May 11, 2000, entitled “SYSTEM AND METHOD FOR COUPLING MICRO-COMPONENTS”; U.S. Pat. No. 6,398,280 issued Jun. 4, 2002, entitled “GRIPPER AND COMPLEMENTARY HANDLE FOR USE WITH MICROCOMPONENTS”; Ser. No. 09/616,500, filed Jul. 14, 2000, entitled “SYSTEM AND METHOD FOR CONSTRAINING TOTALLY RELEASED MICROCOMPONENTS”; Ser. No. 09/643,011, filed Aug. 21, 2000, entitled “SYSTEM AND METHOD FOR COUPLING MICROCOMPONENTS UTILIZING A PRESSURE FITTING RECEPTACLE”; and Ser. No. 10/071,772, filed Feb. 7, 2002, entitled “SYSTEM AND METHOD FOR LATCHING A MICRO-STRUCTURE AND A PROCESS FOR FABRICATING A MICRO-LATCHING STRUCTURE,” the disclosures of which are hereby incorporated herein by reference. Using such technology the micromechanical components may preferably be fabricated directly onto the preexisting integrated circuit chip. 
     In the example shown in FIG. 2C, etched openings  207 ,  208 , and  209  represent the edge of the part of the receptacle or handle and another edge of the part. Specifically a part edge is shown as space  207 ; the receptacle or handle is shown as opening  208 ; and the other part edge is shown as opening  209 ; thus, forming part edges  207  and  209  and receptacle or handle  208 . It should be noted that many different kinds of microcomponents may be etched into SCS layer  100  in addition to the microcomponents listed above. 
     In the final process of fabricating the integrated electronics and micromechanical components, the oxide layers shown as BOx  101  may be released through a hydroflourine (HF) or other oxide-removing bath. As shown in the device of FIG. 2C, if BOx layer  101  were to be etched away, electronics island  104  and any of the micromechanical parts, such as a handle for receptacle  208  would be typically released from the substrate through part edges  207  and  209 . Without any device to restrain the part, the part may simply float away. It is therefore desirable to fabricate restraining devices such as tethers, constraints, or the like onto the integrated system. 
     The first step to establishing a tether or constraint onto the system is to preferably lay a sacrificial layer across the top of the device. The sacrificial layer essentially provide spacing that will preferably be exposed later in the process. FIG. 2D is a cross-sectional diagram illustrating SOI chip  10  from FIG. 2C which includes a new layer of resist, sacrificial layer  210 , laid across the top of the device. As can be seen in FIG. 2D, sacrificial layer  210  preferably fills the openings of part edges  207  and  209  and receptacle or handle  208 . Sacrificial layer  210 , illustrated in FIG. 2D, also shows pattern openings at opening  211 ,  212 , and  213 . The pattern openings, preferably allow etching away additional parts of field oxide layer  103 , thus, exposing SCS layer  100  for further processing. FIG. 2E is a cross-sectional diagram illustrating SOI chip  10  which has now been etched to produced openings  214 ,  215 , and  216  in field oxide layer  103 . Openings  214 ,  215 , and  216  reveal SCS layer  100  for the processing of the tether layer. 
     The next step in fabricating a tether or constraint preferably comprises layering tether material  217  onto the top of SOI chip  10 , as illustrated in FIG.  2 F. Tether material  217  preferably creates a layer on top of SOI chip  10  and fills in openings  214 ,  215 , and  216  down to SCS layer  100 . The next step in forming a tether on SOI chip  10  involves laying another layer of photo resist on top of SOI chip  10  preferably exposing a pattern in that layer of photo resist and further allowing etching the tether material  217  to remove the unwanted material. FIG. 2G illustrates a cross-sectional diagram of SOI chip  10  after the pattern and etching processes have been performed on tether material  217 . As seen in FIG. 2G, resist material  218  remains on top of tether material  217  and has formed, through the etching process, tethers  219 ,  220 , and  22   1 . Because FIG. 2G is a cross-sectional view of chip SOI chip  10 , tethers  220  and  221  appear to connect. However, as illustrated by dotted line  20 , dotted line  20  represents the edge of tether  220  that is positioned behind tether  221 , thus, tether  220  and  221  are completely separate. 
     In order to release the integrated circuit and microcomponent, BOx layer  101  would typically be removed or etched away to preferably remove any physical contact of the integrated component with handle layer  102 . To facilitate removal of BOx layer  101 , an access point must be provided. FIG. 2H is a cross-sectional diagram of SOI chip  10  including cavity  223  which has been etched out of handle layer  102 . Resist layer  222  is shown remaining on the intact portions of handle layer  102  revealing cavity  223 . Cavity  223  provides not only an access point to BOx layer  101 , but also preferably assists in restricting the movement of the released MEM device. 
     In additional embodiments of the present invention the side walls of cavity  223  may have a larger opening at the bottom of handle layer  102  and a smaller opening at BOx layer  101 . An etching process that may accomplishes such a geometry would generally use an isotropic wet etchant, such as potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or the like, to form one or more cavities that can be, for example, between 2 to 20 micrometers or more deep with a substantially planar bottom surface and the sloping innersidewalls. The sloping innersidewalls are usually formed by the selective etching along preferred (111) crystallographic plains as is common with isotropic wet etchants, such as KOH. Other types of etchants or etching means may also be used to form such a shaped cavity. 
     It should be noted that additional embodiments of the present invention may be fabricated using standard, non-SOI silicon wafers. In such embodiments the integrated circuit and microcomponent may be released from the silicon substrate by etching a canal around and underneath the IC and microcomponent. The canal would remove any physical contact between the released MEM device and the underlying silicon substrate. 
     To protect electronics  104  during the HF release cycle, a layer of resist is preferably spun onto the top of SOI chip  10 . After spinning the resist layer onto the top of SOI chip  10 , it is preferably patterned to reveal the layers to be etched. It is also generally patterned with openings  225 ,  226 , and  227 , as shown in FIG. 2I to provide electrical contact points to electronic contacts  105 ,  106 , and  107 . FIG. 2I is a cross-sectional diagram of SOI chip  10  that has been processed to preferably include spin resist layer  224  with openings  225 ,  226 , and  227 , and has preferably been etched to expose the remaining oxide layers of the system. 
     FIG. 2J is a cross-sectional diagram of SOI chip  10  with sacrificial layer  210  and all remaining oxides removed. The removal of these oxides preferably frees the system from the remainder of the substrate. The system includes the MEM device now formed by the integrated circuit and the micromechanical component which remain physically coupled together. Additionally, it completes the formation of tethers  219 ,  220 , and  221 . Integrated unit  231 , as shown on FIG. 2J, represents the integration of the electronic circuitry  104  and the micromechanical components of receptacle or handle  208 , tethers  219 ,  220  and  221 , and even part edges  207  and  209 . 
     Spin resist layer  224  is then preferably removed from integrated unit  231 . FIG. 2K is a cross-sectional diagram of SOI chip  10  that now preferably includes integrated unit  231  without spin resist layer  224 . In order to prevent integrated unit  231  from flying off of SOI chip  10 , tethers  219 ,  220 , and  221  preferably restrict the movement of integrated unit  231 . In operation, if integrated unit  231  begins to rise above handle layer  102 , tether  221  preferably restricts integrated unit  231  from traveling above the tether. Conversely, if integrated  231  begins to drop down towards handle layer  102 , tethers  219  and  220  preferably restrict integrated unit  231  from passing below the reach of tethers  219  and  220 . Thus, integrated unit  231  remains in place on SOI chip  10 , awaiting further processing from other microcomponents or micromechanical devices. 
     It should be noted that in additional embodiments of the present invention, only one tether may be necessary to adequately restrict the movement of the MEM device. In such single tether embodiments, the process of fabricating the device would preferably include the formation of a cavity on the bottom side of the wafer, as shown by cavity  223  in FIGS. 2H-K Thus, the present invention should not be considered as limited to just two or more tethers, but may incorporate any desirable number from one to many. 
     FIG. 3 is an isometric view of pre-fabricated electronic circuitry retrofitted with micromechanical devices fabricated according to one embodiment of the present invention. Integrated device  300  is preferably separated from substrate  30 , being held in place by tether  305 . Tether  304  is attached to integrated unit  300  and preferably prevents integrated unit  300  from moving off of substrate  30 . Electronics island  31  is the area on integrated unit  300  that contains all of the electronics and electronic circuitry of integrated unit  300 . Openings  32  within electronics island  31  preferably provide access or contact points to the electrical connections of the electronics within electronics island  31 . Receptacle or handles  301 , the micromechanical retrofits, preferably provide access points for other microcomponents to grab or grip integrated unit  300  and remove the unit from substrate  30 . Integrated unit  300  also includes connectors  302  and  303  positioned on each side of integrated unit  300  that allow integrated unit  300  to be positioned or placed in any different number of other microcomponents or MEMs devices. 
     Using an integrated electronics and micromechanical device as shown in integrated unit  300  of FIG. 3, additional microcomponents such as microgrippers or other micro tools or any other tools capable of handling sub-millimeter components may preferably grip integrated unit  300 , remove integrated unit  300  from substrate  30 , and assemble integrated unit  300  into an existing MEMs device or other electrical or micromechanical or microelectrical component or device. Using this embodiment of the present invention preferably allows for the assembly of more complex microelectromechanical devices or other integrations of sub-millimeter MEMs/NEMs devices and electronics. This embodiment of the present invention also preferably allows for the complete separation of fabrication between electronics and sub-millimeter electronic devices, such as MEMs devices, and other sub-millimeter mechanical devices or microcomponents. 
     An example of the use of such an integrated unit as shown in FIG. 3, a microgripper may preferably grab integrated unit  300  at any one or more of handle receptacles  301 s and remove integrated unit  300  from substrate  30  by bending, breaking off, or in any other way deflecting tether  304 . An existing MEMs device may be fabricated with edge contacts capable of forming an electrical connection with the electrical connectors within electronics island  31  through openings  32 . Thus, in order to assemble the MEM machine, the microgripper or microtool may place integrated unit  300  into specifically built receptacles that may hold anchors  302  or latches  303  into place against the existing MEMs device in such a manner that the edge connectors from the MEMs device will fit within the openings  32  to make connection with the electrical devices within electronics island  31 , thus, forming a complete electromechanical microelectromechanical system. 
     It should be noted that the tethers or constraints described in embodiments of the present invention are preferably fabricated from material that allows the restriction function to be defeated. By applying an external force or stimulus to the micromechanical elements the MEM device may be removed from the underlying IC by breaking or deflecting the tethers. Stimuli such as electric charge, current, or potential, magnetic fields, thermal, physical, or fluidic forces may be used to remove the MEMs. As long as the external stimuli are one or more of physical, electrical, magnetic, fluidic, or thermal in nature, the MEM element may be removed. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.