Abstract:
An apparatus for impedance matching circuit is disclosed. The impedance matching apparatus has an output driver for outputting an output signal and includes an output data generator, for generating an output data signal; an output stage, for generating the output signal according to the output data signal, and receiving a first control signal to adjust an impendence of the output stage; an impendence unit, electrically coupled to the output stage, for receiving a second control signal to adjust an impedance of the impedance unit; and a calibration circuit electrically coupled to the output stage and the impedance unit, for outputting the first control signal and the second control signal to respectively control the output stage and the impedance unit such that a sum of impedances of the output stage and the impedance unit is adjusted to compensate an environment factor of the chip.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to impedance matching, and more particularly to an apparatus of impedance matching.  
       BACKGROUND OF THE INVENTION  
       [0002]     In a data transmission system, the quality of transmitting and receiving data will be affected by an impedance matching, particularly for the increasingly faster speed of data transmissions.  
         [0003]     Referring to  FIG. 1  for a schematic circuit diagram of performing an impedance matching in accordance with a prior art, an external resistor is used for impedance matching, and the conventional method is simple, easy and direct, but it still has the following drawbacks: 
    (1) The conventional method requires external cascade resistors and incurs a higher system cost.     (2) Since the impedance seen by the reflection waves is the sum of the internal output driver impedance and the impedance of external cascade resistors, and the internal output driver impedance varies with an environment factor of a chip such as at least one of manufacture process, operational voltage, and temperature (P.V.T.), the conventional method cannot be used to achieve a better impedance matching.    
 
         [0006]     Referring to  FIG. 2  for a schematic circuit diagram of performing impedance matching by a self-calibrated resistor matrix in a chip in accordance with a prior art, the resistor matrix is adopted in the chip, and the self-calibration mechanism is adopted for the impedance matching. This conventional method integrates the resistor matrix into the chip to lower the system cost, wherein the resistor matrix is comprised of a plurality of resistors and a plurality of switches, but its drawback resides on that the resistor matrix used in the chip occupies a larger area and incurs a higher die cost.  
       SUMMARY OF THE INVENTION  
       [0007]     Therefore, a primary object of the present invention is to provide an impedance matching circuit to solve the aforementioned problem.  
         [0008]     To achieve the foregoing object, the present invention provides an output driver located in a chip, for outputting an output signal, and the output driver comprises: an output data generator, for generating an output data signal; an output stage, electrically coupled to the output data generator, for generating the output signal according to the output data signal, and receiving a first control signal to adjust an impedance of the output stage; an impedance unit, electrically coupled to the output stage, for receiving a second control signal to adjust an impedance of the impedance unit; and a calibration circuit, electrically coupled to the output stage and the impedance unit, for outputting the first control signal and the second control signal to respectively control the output stage and the impedance unit such that a sum of impedances of the output stage and the impedance unit is adjusted to compensate an environment factor of the chip.  
         [0009]     A second object of present invention is to provide another output driver for outputting an output signal, and the output driver comprises: an output data generator, for generating an output data signal; an output stage, electrically coupled to the output data generator, for generating the output signal according to the output data signal, and receiving a control signal to adjust an impedance of the output stage; an impedance unit, electrically coupled to the output stage, for receiving the control signal to adjust an impedance of the impedance unit; and a calibration circuit, electrically coupled to the output stage and the impedance unit, for outputting the control signal to adjust the impedances of the output stage and the impedance unit. A sum of the impedances of the output stage and the impedance unit is adjusted according to the control signal to achieve a predetermined impedance.  
         [0010]     A third object of the present invention is to provide a method for impedance matching, and the method comprises: generating a control signal by a calibration circuit according to a resistance of a reference resistor; receiving an output data signal; adjusting impedances of an output stage and an impedance unit according to the control signal such that the impedances of the output stage and the impedance unit correspond to the resistance of the reference resistor; generating an output signal according to the output data signal by the output stage; and outputting the output signal through the impedance unit.  
         [0011]     To make it easier for our examiner to understand the objective of the invention, its structure, innovative features, and performance, we use a preferred embodiment together with the attached drawings for the detailed description of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, both as to device and method of operation, together with features and advantages thereof may best be understood by reference to the following detailed description with the accompanying drawings in which:  
         [0013]      FIG. 1  is a schematic circuit diagram of the structure of an external resistor performing an impedance matching in accordance with a prior art;  
         [0014]      FIG. 2  is a schematic circuit diagram of the structure of another external resistor performing an impedance matching in accordance with a prior art;  
         [0015]      FIG. 3  is a schematic circuit diagram of an impedance matching apparatus in accordance with the present invention; and  
         [0016]      FIG. 4  is a schematic circuit diagram of the structure of a calibration circuit of an impedance matching apparatus in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0017]     The present invention relates to an impedance matching apparatus. While the specifications describe at least one embodiment of the invention considered best modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented.  
         [0018]     Referring to  FIG. 3  for a schematic circuit diagram of an impedance matching apparatus in accordance with a preferred embodiment of the present invention, the impedance matching apparatus  300  comprises: a pre-driver  301 , an output driver stage  303 , an impedance unit  305 , and a calibration circuit  307 . In an application with a low amplitude output (such as 0.7V) as illustrated in this embodiment, the output driver stage  303  adopts a structure of cascade N-type metal oxide semiconductor (NMOS) transistors  310 ,  311  and the impedance unit  305  adopts a plurality of NMOS transistors connected in parallel. It is noteworthy to point out that the NMOS transistors are used for illustration only and not intended to limit the scope of the invention.  
         [0019]     In a preferred embodiment, the pre-driver  301  adopts a high voltage HV (such as 3.3V), and the output of the pre-driver  301  is used as a gate voltage of the NMOS transistor  310 ,  311  in the output driver stage  303 , and a drain of the NMOS transistor  310  of the output driver stage  303  is connected to a low voltage LV (such as 0.7V). The low voltage LV is used to set the amplitude of an output signal of an output end PAD and supplied by the external power source or produced by a voltage regulator circuit (not shown in the figure) in the chip. The calibration circuit  307  includes two groups of control signals D[M-1:0] and C[N-1:0], wherein D[M-1:0] is used for controlling the output of an impedance at the NMOS transistor  310  of the output driver stage  303 , and C[N-1:0] is used for controlling the impedance of an adjustable impedance unit  305  (such as a plurality of NMOS transistors connected in parallel) which is coupled between the output driver stage  303  and the output end PAD. In an embodiment, the output driver stage  303  further includes a plurality of logic elements (such as AND gates), for receiving control signals D[M-1:0] to control the number of electrically connected NMOS transistors  310  and NMOS transistors  311  and adjust the impedance of the output driver stage  303 .  
         [0020]     Referring to  FIG. 4  for a schematic circuit diagram of the structure of a calibration circuit of an impedance matching apparatus in accordance with the present invention, the calibration circuit  307  comprises: a control logic  401 , a comparator  403 , a current source  405 , a calibrating resistor unit  406 , and a resistor  409 . The calibrating resistor unit  406  is used for tracking a change of impedance of the output driver stage  303  or the impedance unit  305 , or both. In other words, the calibrating resistor unit  406  is made with the same material by the same process of the output driver stage  303  or the impedance unit  305  or both. The resistor  409  is a component not easily affected by process, voltage and temperature (P.V.T.) and can be an external resistor installed outside the chip. In an embodiment, the transistor  402  of the calibrating resistor unit  406  is very similar to the NMOS transistor  310  of the output driver stage  303 , and the total resistance is controlled by D[M-1:0]. The transistor  407  of the calibrating resistor unit  406  is very similar to the transistor of the impedance unit  305 , and the total resistance is controlled by C[N-1:0]. In an embodiment, the control logic  401  comprises a up/down counter for receiving the output of the comparator  403  and increasing or decreasing the first control signal D[M-1,0] and the second control signal C[N-1,0] according to the output of the comparator  403 .  
         [0021]     The following is derived from the principle of an embodiment according to the present invention:  
         [0022]     The current source  405  generates currents IBN and IBR separately with a specific ratio such as:
 
 IBR =M× IBN   Equation (1)
 
         [0023]     The calibrating resistor unit  406  includes a plurality of NMOS transistors  402  and a plurality of NMOS transistors  407 .  
         [0024]     It is assumed that the resistor Rmirror (Sum of cascade resistors of NMOS transistors  402  and NMOS transistors  407 ) of the calibrating resistor unit  406  is equal to the sum of resistance of the NMOS transistor  310  of the output driver stage  303  and the impedance unit (NMOS transistor)  305  multiplied by N.
 
R mirror   =N ×(R n1 +R n2 )  Equation (2)
 
         [0025]     Where, R mirror  is the sum of cascade resistors of mirror NMOS  402 ,  407 , and R n1  is the impedance of the NMOS transistor  310  of the output driver stage  303 , and R n2  is the impedance of the impedance unit (NMOS transistor)  305 .  
         [0026]     The current IBN of the current source  405  flows into the calibrating resistor unit  406 , and the produced voltage is given below:
 
 VIN=IBN ×(R mirror )= IBN ×N×(R n1 +R n2 )  Equation (3)
 
         [0027]     Another current IBR of the current source  405  flows into an external resistor R_ext  409 , and the produced voltage is given below:
 
 VIP=IBR ×R_ext  Equation (4)
 
         [0028]     The inputs of the comparator  403  are VIN and VIP, and a compare result is outputted and sent to the digital control circuit  401 . The digital control circuit  401  adjusts the output signals C[N-1:0] and D[M-1:0] by a negative feedback according to the compare result. In the meantime, the output signal C[N-1:0] adjusts the impedance of the NMOS transistor  407  and the impedance of the NMOS transistor  305 . The output signal D[M-1:0] adjusts the impedance of the mirror NMOS transistor  402  and the impedance of the NMOS transistor  310  of the output driver stage  303  to maintain a ratio of their impedances to N.  
         [0029]     After several times of comparisons, VIN gradually approaches VIP, and finally VIN and VIP are substantially equal (its deviation depends on the minimum resolution of the resistor of the NMOS transistor).
 
 IBN ×R mirror   =IBN×N ×(R n1 +R n2 )= IBR ×R_ext  Equation (5)
 
         [0030]     Equations (1) and (5) are combined to obtain
 
 N×(R   n1 +R n2 )=M/ N ×R_ext  Equation (6)
 
(R n1 +R n2 )=M/ N ×R_ext  Equation (7)
 
         [0031]     Since R_ext  409  is an external resistor which will not be affected by P.V.T, therefore the sum of impedances of R n1  and R n2  will not be related to P.V.T.  
         [0032]     The effect of process, voltage and temperature (P.V.T.) on the impedance of the output driver stage  303  or the impedance unit  305  or both can be overcome by comparing the voltages outputted by the calibrating resistor unit  406  and the resistor  409  by the calibration circuit  307  to output C[N-1:0] and D[M-1:0] to adjust the output driver stage  303 , or the impedance unit  305  or both. In a  10  preferred embodiment, the sum of impedances of the transistor  402  and cascade transistors  407  is compared with the resistor  409 , and the control circuit  401  adjusts the impedances of the output driver stage  303  and the impedance unit  305 , such that the sum of cascade resistors corresponds to the impedance of the resistor  409  to compensate the effect of P.V.T. on the impedance.  
         [0033]     In a preferred embodiment, the value of a gate voltage (Vg) of the transistor  310  and cascade transistors  305  is higher than the value of their source voltage (Vs) such as Vs=0.7 V, Vg=3.3 V, and the maximum value of a drain voltage of these transistors is the amplitude of the output signal (such as 0.7V), and thus the condition Vds&lt;Vgs can be satisfied, and both can be operated in a linear region. By adjusting the dimensions (i.e., aspect ratio) of the transistor, a smaller area can be achieved for a matching resistor of 50 ohms. Since the amplitude of the output signal is smaller (that is, a change of source voltage at the NMOS transistor  310  and the NMOS transistor  305  is small), therefore the change of a gate-source voltage difference (Vgs) of the transistors  310 ,  305  is also small, and the change of impedance of the transistors  310 ,  305  will be negligible.  
         [0034]     In summation of the description above, an application with low amplitude of an output signal (such as 0.7 V, LVDS (Low Voltage Differential Signaling) or RSDS (Reduced Swing Differential Signaling) standard) ) can adopt a small change of output impedance of the transistors  310 ,  305  and the feature of occupying a small area for a better impedance matching. By adjusting the impedance of the output driver stage  303  or the impedance unit  305  or both made by the calibration circuit  307 , the overall output impedance of the circuit will be equal to the impedance of a transmission line outside the chip, so as to achieve the impedance matching.  
         [0035]     While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.