Abstract:
A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Technical Field  
         [0002]     The present invention relates to semiconductor device fabrication, and more specifically, to implantation of gate regions in semiconductor device fabrication.  
         [0003]     2. Related Art  
         [0004]     A conventional semiconductor device fabrication process usually starts out with the formation of shallow trench device isolation (STI) followed by a gate dielectric formation on a semiconductor layer. Next, poly-silicon gate regions are formed on the gate dielectric layer. These poly-silicon gate regions are formed thick so that later source/drain and halo implantations cannot pass through them into the channel regions. The poly-silicon gate is doped by the same source/drain implants. The dose and the energy of the implants are optimized for the shallow source/drain diffusions and thus the doping concentration of the poly-silicon gate is not sufficient to reduce the poly-silicon depletion effect, and as a result, the effective electrical thickness of gate dielectric is significantly thicker than the physical gate dielectric thickness. Reducing the effective electrical thickness is one of the key factors to improve performance of poly-silicon gate field effect transistor (FET) device. Reducing the poly-silicon depletion thickness is essential to improve device performance. Therefore, it is highly beneficial to have a method to increase the concentration of doping of the poly-silicon without disturbing the optimized source/drain diffusion doping profile. One prior art method of optimizing both source/drain doping and poly-silicon gate doping is described by Dokumaci et al. in the US patent application publication, US2002/0197839A1. In this prior art, a spin-applied resist layer is formed on the entire structure and then etched back until the poly-silicon gate regions are exposed to the atmosphere. Next, gate regions implantation is performed to dope the gate regions. It is desirable that the spin-applied resist layer after being etched back is still thick enough to prevent the gate regions implantation from implanting regions of the semiconductor layer where source/drain regions will be later formed. However, the spin-applied resist layer, when formed, tends to be thicker where gate regions concentration is higher and tends to be thinner where gate regions concentration is lower. Therefore, after being etched back to expose the gate regions to the atmosphere, the spin-applied resist layer may be too thin where the pattern density of gate regions is lower to protect the semiconductor layer from the gate regions implantation.  
         [0005]     As a result, there is a need for a structure (and method for forming the same), in which gate regions implantation essentially does not implant regions of the semiconductor layer where source/drain regions will be later formed.  
       SUMMARY OF THE INVENTION  
       [0006]     The present invention provides a semiconductor structure fabrication method, comprising the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer, and (iv) a proton-generating region on the gate region wherein the proton-generating region comprises free protons; (b) forming a resist layer on the gate dielectric layer and the proton-generating region; and (c) thermally diffusing free protons from the proton-generating region into the resist layer.  
         [0007]     The present invention also provides a semiconductor structure fabrication method, comprising the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer directly above the gate region essentially in a direction perpendicular to an interfacial surface between the semiconductor layer and the gate dielectric layer; and (d) implanting the gate region essentially without implanting regions of the semiconductor layer.  
         [0008]     The present invention also provides a semiconductor structure fabrication method, comprising the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing the resist layer except a cap portion of the resist layer directly above the gate region essentially in a direction perpendicular to an interfacial surface between the semiconductor layer and the gate dielectric layer; (d) forming source/drain (S/D) protection regions on side walls of the gate region and the cap portion of the resist layer; (e) removing the cap portion of the resist layer; and (f) implanting the gate region through the space of the removed cap portion essentially without implanting regions of the semiconductor layer through the S/D protection regions.  
         [0009]     The present invention also provides a structure (and method for forming the same), in which gate regions implantation essentially does not implant regions of the semiconductor layer where source/drain regions will be later formed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]      FIGS. 1-8  illustrate a first fabrication method for forming a semiconductor structure  100 , in accordance with embodiments of the present invention.  
         [0011]      FIGS. 9-13  illustrate a second fabrication method for forming another semiconductor structure  200 , in accordance with embodiments of the present invention.  
         [0012]      FIGS. 14A-14B  illustrate a third fabrication method, in accordance with embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]      FIGS. 1-8  illustrate a first fabrication method for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , the first fabrication method for forming the semiconductor structure  100  can start out with a semiconductor (e.g., silicon, germanium, etc.) layer  110 . Next, a gate dielectric layer  120  can be formed on top of the semiconductor layer  110 . The gate dielectric layer  120  can comprise an oxide material (e.g., silicon dioxide) and can be formed on top of the semiconductor layer  110  by, illustratively, thermal oxidation. The gate dielectric may comprise a high k material (k is the dielectric constant) such as silicon nitride, silicon oxynitride, hafnium oxide, hafnium oxynitride, or other known dielectrics. Next, a gate layer  130  can be formed on top of the gate dielectric layer  120 . The gate layer  130  can comprise poly-silicon and can be formed on top of the gate dielectric layer  120  by, illustratively, CVD (chemical vapor deposition).  
         [0014]     Next, a proton-generating layer  140  can be formed on top of the gate layer  130 . The proton-generating layer  140  can comprise a material that, when going through a chemical process, will generate free protons. In one embodiment, the proton-generating layer  140  can comprise a polymer that contains C—H (carbon-hydrogen) bond in which the H atom is replaceable. To generate free protons, the polymer can go through a chemical process called gas phase sulfonation during which the polymer chemically reacts with gaseous sulfur trioxide (SO 3 ) in a dry gas such as air, nitrogen, helium, carbon dioxide, or sulfur dioxide.  FIG. 1B  illustrates the sulfonation of polyethylene (a polymer) that yields sulfonic acid as a product (to the right of the arrow). With reference to  FIG. 1B , the H atom  170  is relatively free and can break free from the sulfonic acid molecule to become a free proton. This free proton, when placed in an electric field (not shown), will move in the same direction as that of the electric field. In one embodiment, the sulfonation of the polymer can be carried out at ambient conditions (i.e., 1 Atm pressure and 24° C. temperature) using a mixture of SO 3  and nitrogen (with SO 3  at 1% by volume).  
         [0015]     Next, a cap layer  150  can be formed on top of the proton-generating layer  140 . The cap layer  150  can comprise an oxide (e.g., silicon dioxide) or a nitride (e.g., silicon nitride). Next, a patterned resist layer  160  can be formed on top of the cap layer  150 .  
         [0016]     Next, the patterned resist layer  160  can be used as a mask to etch through the cap layer  150 , the proton-generating layer  140 , and the poly-silicon gate layer  130  in that order. Then, the patterned resist layer  160  can be removed. The resulting structure  100  after the patterned resist layer  160  is removed is shown in  FIG. 2 . Also, as a result of the etching process above, the cap layer  150 , the proton-generating layer  140 , and the poly-silicon gate layer  130  are reduced to the cap region  150 ′, the proton-generating region (PGR)  140 ′, and the poly-silicon gate region  130 ′ respectively.  
         [0017]     Next, with reference to  FIG. 2 , the cap region  150 ′ can be removed. The resulting structure  100  after the cap region  150 ′ is removed is shown in  FIG. 3 .  
         [0018]     Next, with reference to  FIG. 3 , the proton-generating region  140 ′ can be exposed to a chemical (not shown) so that free protons  142  are generated in the proton-generating region  140 ′. As described earlier, if the proton-generating region  140 ′ comprises the organic polymer, then the proton-generating region  140 ′ can be exposed to SO 3  so as to create the free protons  142  in the proton-generating region  140 ′.  
         [0019]     Next, with reference to  FIG. 4 , a resist layer  410  can be formed on top of the entire structure  100  of  FIG. 3 . The resist layer  410  can comprise a first material that, after being passed through by protons, becomes a second material such that there exists at least a first etching process that can etch away the second material essentially without etching the first material. The inventors of the present invention have found that most conventional positive photoresist materials can be used as the first material mentioned above because after being passed through by protons, these photoresist materials change characteristic (turning into the second material) and become soluble in a specific solvent (called developer). This developer can be used in the first etching process. This process is similar to a photolithography process except that no mask is used and a drift of protons is used instead of the radiation of light.  
         [0020]     Next, with reference to  FIG. 5 , the structure  100  of  FIG. 4  can be positioned in an electric field represented by an arrow  510  whose direction also indicates the direction of the electric field. Hereafter, the electric field can be referred to as the electric field  510 . In one embodiment, the electric field  510  can be perpendicular to an interface surface  112  between the semiconductor layer  110  and the gate dielectric layer  120  and can point from the semiconductor layer  110  to the gate dielectric layer  120  as shown.  
         [0021]     Placed in the electric field  510 , the free protons  142  in the proton-generating region  140 ′ move from the proton-generating region  140 ′ through a cap portion  410 ′ of the resist layer  410 . The movements of the protons  142  are represented by arrows  520  whose directions also indicate the directions of the proton movements. As a result, if the resist layer  410  comprises the first material, then the cap portion  410 ′ comprises the second material. In one embodiment, the electric field  510  can be provided by placing the structure  100  between cathode  500   a  and anode  500   b  as shown.  
         [0022]     Next, the first etching process that can etch away the second material essentially without etching the first material can be performed to remove the cap portion  410 ′ of the resist layer  410  essentially without removing the remainder of the resist layer  410 . Next, the proton-generating region  140 ′ can be removed. The resulting structure  100  is shown in  FIG. 6 . Alternatively, the proton-generating region  140 ′ can be left in place because it does not significantly affects the ensuing doping of the gate region  130 ′.  
         [0023]     Next, with reference to  FIG. 6 , a gate region implantation process can be performed to dope the gate region  130 ′, but not the region of the semiconductor layer  110  directly beneath the gate region  130 ′. The gate region implantation process can be represented by arrow  610  whose direction also indicates the direction of gate region implantation ion bombardment. It should be noted that the remainder of the resist layer  410  (after the cap portion  410 ′ of  FIG. 5  is removed) is used as a blocking mask that prevents the gate region implantation ion bombardment of the gate region implantation process  610  from reaching regions of the semiconductor layer  110  directly beneath the remainder of the resist layer  410  (where source/drain regions will be formed).  
         [0024]     Next, with reference to  FIG. 7 , the remainder of the resist layer  410  can be removed. Then, two thin gate spacers  710   a  and  710   b  can be formed on side walls of the gate region  130 ′. The gate spacers  710   a  and  710   b  can comprise an oxide (e.g., silicon dioxide). Next, the gate region  130 ′ and the gate spacers  710   a  and  710   b  can be used as a mask to implant the extension regions  714   a  and  714   b , and then halo regions  716   a  and  716   b , using any conventional method.  
         [0025]     Next, with reference to  FIG. 8 , two fat gate spacers  810   a  and  810   b  can be formed on side walls of the gate region  130 ′. In one embodiment, the gate spacers  810   a  and  810   b  can be formed by first depositing a conformal nitride layer (not shown) on top of the structure  100  of  FIG. 7  and then removing the nitride from the horizontal surface by a directional etch. Alternatively, as can be seen in  FIG. 8 , the gate spacers  810   a  and  810   b  can be formed by first removing the gate spacers  710   a  and  710   b  of  FIG. 7 . Then, the gate spacers  810   a  and  810   b  can be formed by depositing a conformal nitride layer (not shown) on top of the structure  100  of  FIG. 7  (with the gate spacers  710   a  and  710   b  having been removed) and then etching directionally the deposited nitride layer so as to form the gate spacers  810   a  and  810   b . Next, the gate region  130 ′ and the gate spacers  810   a  and  810   b  can be used as a mask to implant source/drain (S/D) regions  812   a  and  812   b.    
         [0026]      FIGS. 9-13  illustrate a second fabrication method for forming another semiconductor structure  200 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 9 , the second fabrication method for forming the semiconductor structure  200  can start out with a structure similar to the structure  100  of  FIG. 5  except that the resist layer  910  can comprise a third material that, after being passed through by protons  142 , becomes a fourth material such that there exists at least a second etching process that can etch away the third material essentially without etching the fourth material. As a result after being passed through by protons  142 , the cap portion  910 ′ of the resist layer  910  essentially comprises the fourth material. The inventors of the present invention have found that most conventional negative photoresist materials can be used as the third material mentioned above because after being passed through by protons, these photoresist materials change characteristic (turning into the fourth material) and become insoluble in a specific solvent (called developer). This developer can be used in the second etching process. This process is similar to a photolithography process except that no mask is used and a drift of protons is used instead of the radiation of light.  
         [0027]     Next, the second etching process, that can etch away the third material essentially without etching the fourth material, can be used to etch away the resist layer  910  except the cap portion  910 ′ of the resist layer  910 .  
         [0028]     Next, with reference to  FIG. 10 , S/D protection spacers  1010   a  and  1010   b  can be formed on side walls of the gate stack  130 ′, 140 ′, 910 ′ comprising the cap portion  910 ′, the proton-generating region  140 ′, and the gate region  130 ′. The S/D protection spacers  1010   a  and  1010   b  can be formed by plasma assisted deposition of a conformal nitride (e.g., silicon nitride) or oxide (e.g., silicon dioxide) followed by directional etching of nitride or oxide. Next, the cap portion  910 ′ and then the proton-generating region  140 ′ can be in turn removed. The resulting structure  200  is shown in  FIG. 11 . Alternatively, the proton-generating region  140 ′ can be left in place because it does not significantly affects the ensuing doping of the gate region  130 ′.  
         [0029]     Next, with reference to  FIG. 11 , a gate region implantation process can be performed to dope the gate region  130 ′, but not the region of the semiconductor layer  110  directly beneath the gate region  130 ′. The gate region implantation process can be represented by arrow  1110  whose direction also indicates the direction of gate region implantation ion bombardment. It should be noted that the S/D protection spacers  1010   a  and  1010   b  can be used as a blocking mask that prevents the gate region implantation ion bombardment  1110  from reaching regions of the semiconductor layer  110  directly beneath the S/D protection spacers  1010   a  and  1010   b  (where source/drain regions will be formed).  
         [0030]     Regions  1120   a  and  1120   b  of the semiconductor layer  110  are inadvertently doped by the gate region implantation process  1110 . However, as can be seen later, the doped regions  1120   a  and  1120   b  do not adversely affect the operation of the final device  200  of  FIG. 13 .  
         [0031]     Next, with reference to  FIG. 12 , the S/D protection spacers  1010   a  and  1010   b  ( FIG. 11 ) can be removed. Then, two thin gate spacers  1210   a  and  1210   b  can be formed on side walls of the gate region  130 ′. The gate spacers  1210   a  and  1210   b  can comprise an oxide (e.g., silicon dioxide). Next, the gate region  130 ′ and the gate spacers  1210   a  and  1210   b  can be used as a mask to implant the extension regions  1214   a  and  1214   b , and then halo regions  1216   a  and  1216   b , using any conventional method.  
         [0032]     Next, with reference to  FIG. 13 , two thicker gate spacers  1310   a  and  1310   b  can be formed on side walls of the gate region  130 ′. In one embodiment, the gate spacers  1310   a  and  1310   b  can be formed by first depositing a conformal nitride layer (not shown) on top of the structure  200  of  FIG. 12  and then removing the nitride from the horizontal surface by a directional etch. Alternatively, as can be seen in  FIG. 13 , the gate spacers  1310   a  and  1310   b  can be formed by first removing the thin gate spacers  1210   a  and  1210   b  of  FIG. 12 . Then, the thick gate spacers  1310   a  and  1310   b  can be formed by depositing a conformal nitride layer (not shown) on top of the structure  200  of  FIG. 12  (with the thin gate spacers  1210   a  and  1210   b  having been removed) and then etching directionally the deposited nitride layer so as to form the thick gate spacers  1310   a  and  1310   b.    
         [0033]     Then, the gate region  130 ′ and the gate spacers  1310   a  and  1310   b  can be used as a mask to implant source/drain (S/D) regions  1312   a  and  1312   b.    
         [0034]     In summary, the first and second methods of the present invention form S/D protection regions directly above the regions of the semiconductor layer  110  where S/D regions will be later formed, while exposing the poly-silicon gate regions to the atmosphere. As a result, the gate regions implantation process can be tailored to dope the gate regions essentially without doping the regions of the semiconductor layer  110  where S/D regions will be later formed.  
         [0035]      FIGS. 14A-14B  illustrate a third fabrication method for forming the semiconductor structure  300 , in accordance with embodiments of the present invention. The third fabrication method is similar to the first fabrication method (illustrated in  FIGS. 1-8 ). With reference to FIG.  14 A, after the resist layer  410  is formed on top of the entire structure  300 , the structure  300  is similar to the structure  100  of  FIG. 4 . Next, the PGR region  140 ′ is subjected to heat that diffuses the free protons  142  of the PGR region  140 ′ into in the resist layer  410  to form the cap portion  410 ′. The thermal proton diffusion is represented by arrows  1420  whose directions also indicate the directions of the proton diffusion into the resist layer  410 . As a result, while the cap portion  410 ′ of  FIG. 5  (the first fabrication method) is only directly above the PGR region  140 ′, the cap portion  410 ′ of  FIG. 14A  is not only directly above but also surrounds the PGR region  140 ′. Next, the cap portion  410 ′ can be removed (by etching) essentially without removing the remainder of the resist layer  410 . Next, the proton-generating region  140 ′ can be removed. The resulting structure  300  is shown in  FIG. 14B . Alternatively, the proton-generating region  140 ′ can be left in place because it does not significantly affects the ensuing doping of the gate region  130 ′.  
         [0036]     Next, with reference to  FIG. 14B , the third fabrication method proceeds with a gate region implantation process to dope the gate region  130 ′, but not the region of the semiconductor layer  110  directly beneath the gate region  130 ′. The gate region implantation process can be represented by arrow  1430  whose direction also indicates the direction of gate region implantation ion bombardment. It should be noted that the remainder of the resist layer  410  (after the cap portion  410 ′ of  FIG. 14A  is removed) is used as a blocking mask that prevents the gate region implantation ion bombardment of the gate region implantation process  1430  from reaching regions of the semiconductor layer  110  directly beneath the remainder of the resist layer  410  (where source/drain regions will be formed). After this gate region implantation process, the third fabrication method is similar to the first fabrication method.  
         [0037]     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.