Abstract:
This invention is used in a real time system that includes a host processor, interface hardware and an external device controlled by the interface hardware. To maintain system real-time performance, handshake protocol between the external device and the interface hardware is automatic during command execution. This invention moves control of the external device to the host processor if a command doesn&#39;t finish before a host processor specified time limit. If command execution exceeds the time limit, the host processor controls the handshake protocols directly and sequentially. This prevents system breakdown caused by trouble at the external device. This invention is useful to prevent failure due to defective media in a consumer DVD recorder.

Description:
[0001]     This application claims priority under 35 U.S.C. §119(e)(1) from U.S. Provisional Application No. 60/517,613 filed Nov. 4, 2003. 
     
    
     TECHNICAL FIELD OF THE INVENTION  
       [0002]     The technical field of this invention is real time computer control of a remote device.  
       BACKGROUND OF THE INVENTION  
       [0003]     This invention is applicable in a real time system including an external device, interface hardware that automatically controls handshake protocol with the external device and a host processor. In this real time system the external device control protocol is mainly handled by the interface hardware because high speed is needed to provide real-time performance. The interface hardware access is much faster than access by a software program driving the host processor. Thus the host processor is not effective for controlling the handshake protocol due to wait sequences for the external device.  
         [0004]     This system may breakdown once the handshake protocol stops due to trouble with the external device. Once this breakdown occurs, it may take 10 to 20 seconds recover. Such system breakdown causes problems.  
       SUMMARY OF THE INVENTION  
       [0005]     In systems employing this invention, control of the external device is moved from the interface hardware to the host processor when a command doesn&#39;t finish execution before a limit time. The host processor specifies this time limit. This invention employs time division multiplexing of the control of the external device between the interface hardware and the host processor. This invention is advantageous because it enables reduced size of the interface hardware and avoids system breakdown.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]     These and other aspects of this invention are illustrated in the drawings, in which:  
         [0007]      FIG. 1  illustrates a block diagram of a video system to which this invention is applicable;  
         [0008]      FIG. 2  illustrates a block diagram of a system employing this invention;  
         [0009]      FIG. 3  illustrates the control sequence for the external device during normal operation according to the prior art;  
         [0010]      FIG. 4  illustrates the control sequence for the external device during a fault according to the prior art;  
         [0011]      FIG. 5  illustrates a flow chart of host processor operation according to the prior art;  
         [0012]      FIG. 6  illustrates the control sequence for the external device during normal operation according to this invention;  
         [0013]      FIG. 7  illustrates the control sequence for the external device during a fault according to this invention; and  
         [0014]      FIG. 8  illustrates a flow chart of host processor operation according to this invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0015]      FIG. 1  illustrates a consumer DVD/HDD hybrid recording system, the type system to which the invention is applicable. The heart of the system is MPEG codec LSI (large scale integrated circuit)  100 . MPEG codec LSI  100  receives an input from a television signal source such as antenna  110  and receiver  115  for capturing a broadcast signal. MPEP encoder  120  encodes this input signal. The encoded signal is temporarily stored in track buffer  131 . In the example illustrated in  FIG. 1 , track buffer  131  serves as a write buffer for first storage device  141 . The example of  FIG. 1  illustrates reading second storage device  145  with track buffer  135  serving as a read buffer. The read data, which has been previously MPEG encoded is decoded by MPEG decoder  140 . The decoded signal is displayed via display  150 . In the typical consumer DVD/HDD hybrid recording system, first storage device  141  is a read/write magnetic fixed memory drive (HDD) and second storage device  147  is a read/write optical disk drive (DVD)  
         [0016]      FIG. 2  illustrates a block diagram view of a system to which this invention is applicable. Host processor  201  exchanges driver and interrupt signals with interface hardware  210 . Interface hardware  210  exchanges handshake protocol signals  215  with external drive  220 . External drive  220  could be either first storage device  141  or second storage device  147 .  
         [0017]     Especially in consumer video and audio recorder systems with plural storage devices such as the DVD/HDD hybrid recorder illustrated in  FIG. 1 , the interface hardware  210  automatically carries out the handshake protocols  215  with the external storage device  220  during a command execution. Host processor  201  specifies the command execution for the interface hardware  210 .  
         [0018]      FIG. 3  illustrates normal command execution. Reference number  300  is the time line of host processor  201  operation. Reference  310  is the time line of interface hardware  210  operation. Reference  320  is the time line of external device  220  operation. Before time t 1 , host processor  201  prepares interface hardware  210  for command execution. Host processor  201  transmits GO flag  301  to interface hardware  210  to start command execution. During the time between t 1  and t 2 , interface hardware  210  exchanges protocol signals  302  with external device  220 . Command execution finishes at time t 2  following the time  303  of command execution. Handshake protocol  302  stops and interface hardware  210  asserts an interrupt flag  304  (Done signal) to host processor  201 . Interrupt flag  304  indicates that command execution is complete. After time t 2 , interface hardware  210  and external device  220  are idle in preparation for the next command.  
         [0019]      FIG. 4  illustrates the case of an external device  220  fault. Reference number  400  is the time line of host processor operation. Reference  410  is the time line of interface hardware  210  operation. Reference  420  is the time line of external device  220  operation. Before time t 1 , host processor  201  prepares interface hardware  210  for command execution. Host processor  201  transmits GO flag  401  to interface hardware  210  to start command execution. During the time between t 1  and t 1 , interface hardware  210  exchanges protocol signals  402  with external device  220 . In this case command execution continues due to a device fault and interface hardware  210  never generates the interrupt flag. Interface hardware  210  and external device  220  continue handshake protocols  402  and are not prepared for the next command execution. This case may occur when the external storage device  220  fails to access the media due to a fatal defect of the media. Once this occurs, it takes 10 to 20 seconds for a prior art system to finish the command execution in worst case. Interface hardware  210  in prior art has no capability to abort command execution. This is because of the low occurrence of such faults. This functionality is generally omitted from a low cost system. Considering the real time system characteristics, this amount of time for execution of one command may cause system broke down. This may occur even if host processor  201  has a large buffer memory that can store the amount of data corresponding to the command execution time. This invention is proposed to avoid such a breakdown.  
         [0020]      FIG. 5  illustrates a flow chart of the processes on host processor  201 . Following command assertion (processing block  501 ), host processor  201  tests for completion of command execution (decision block  502 ). This occurs while interface hardware  201  controls external device  220 . If the command completes (yes at decision block  502 ), then host processor  201  asserts the next command (processing block  501 ). If the command does not complete (no at decision block  502 ), then host processor  201  continues to test for command completion (decision block  502 ). Thus host processor  201  remains in a loop upon a device fault preventing command completion.  
         [0021]     In this invention, control of the external device  220  is moved from interface hardware  210  to host processor  201  if command execution doesn&#39;t finish before a time limit set by host processor  201 . Handshake protocols between interface hardware  210  and external device  220  is automatic during normal command execution. If command execution doesn&#39;t complete within the time limit, control of external device  220  moves to host processor  201 . Thus, host processor  201  controls the handshake protocols with external device  220  directly and sequentially.  
         [0022]      FIG. 6  illustrates operation of this invention in the normal case. Reference number  600  is the time line of host processor  201  operation. Reference  610  is the time line of interface hardware  210  operation. Reference  620  is the time line of external device  220  operation. Before time t 1 , host processor  201  prepares interface hardware  210  for command execution. Host processor  201  transmits GO flag  601  to interface hardware  210  to start command execution. During the time between t 1  and t 2 , interface hardware  210  exchanges protocol signals  602  with external device  220 . Command execution finishes at time t 2  following the time  603  of command execution. Handshake protocol  602  stops and interface hardware  210  asserts an interrupt flag  604  (Done signal) to host processor  201 . Interrupt flag  604  indicates that command execution is complete. After time t 2 , interface hardware  210  and external device  220  are idle in preparation for the next command. In this example, command completion and generation of done signal  604  occurs before the end of the timeout limitation  605  at t 3 .  FIG. 6  illustrates a second normal sequence beginning at time t 4  and ending at time t 5 .  
         [0023]      FIG. 7  illustrates operation of this invention in the abnormal case. Before time t 1 , host processor  201  prepares interface hardware  210  for command execution. Host processor  201  transmits GO flag  601  to interface hardware  210  to start command execution. During the time between t 1  and t 3 , interface hardware  210  exchanges protocol signals  602  with external device  220 . If command execution does not finish before the end of the timeout limitation  605  at time t 3 , interface hardware  210  asserts a time out interrupt flag  604  to host processor  201 . This includes a status flag that indicates the asserted command is to be continued without any error. Thereafter interface hardware  210  stops further handshake protocols with external device  220 .  
         [0024]     Control of external device  220  is moved to host processor  201 . Command execution continues with host processor  201  controlling further handshake protocols  606  by direct and sequential control of interface hardware  210  and external device  220 . Host processor  201  controls each such handshake. This continues until the command completes or an additional time expires. At time t 6  and the end of this additional time host processor  201  causes command execution to terminate. In this example, this termination takes place via device reset signal  607 .  
         [0025]     In a consumer DVD recorder a typical command execution time is one second. The time limit should be set more than this time interval. A time limit of 3 seconds is suitable for consumer DVD recorder applications. This time limit may be predetermined upon manufacture and permanently set in interface hardware  210 . Alternatively, the time limit may be set by host processor  201  writing data into a register reserved for this purpose in interface hardware  210 .  
         [0026]      FIG. 8  illustrates a flow chart of the processes on host processor  201 . Following command assertion (processing block  801 ), host processor  201  tests for completion of command execution (decision block  502 ). This occurs while interface hardware  201  controls external device  220 . If the command completes within the time limit (yes at decision block  802 ), then host processor  201  asserts the next command (processing block  801 ). If the command does not complete within the time limit (no at decision block  802 ), then host processor  201  takes control of the handshake protocol with external device  220  (processing blocks  803  and  804 ). Host processor  201  tests to determine if the command completes or aborts (decision block  805 ). If neither event occurs (no at decision block  805 ), then host processor  201  continues to direct the handshake protocol (processing block  804 ). If the command completes or aborts (yes at decision block  805 ), then host processor  201  executes a command finish routine (processing block  806 ). Control returns to processing block  801  for the next command.  
         [0027]     This invention is effective in real-time systems such as video and audio recording systems with storage devices. Using this invention, the host processor can actively control the external storage device by specifying a time limit for command execution.