Abstract:
A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having vias generated formed in sections. 
     BACKGROUND OF THE INVENTION 
     Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. 
     Semiconductor dies are typically packaged in a semiconductor package that includes terminals for electrically and often mechanically connecting the semiconductor package to an external device, such as a printed circuit board. A substrate typically provides connections from electrical connections of the semiconductor die (via wire-bonding to pads or ball-attach) to the terminals by providing a circuit pattern in or on the surfaces of one or more dielectric layers. When multiple layers are incorporated in the substrate, vias provide connections between layers. 
     As semiconductor die circuit complexity has increased, the number of electrical connections has generally increased, causing a need for increasingly dense terminal arrays. The substrate circuit density generally limits the terminal density, as the line width, inter-line spacing and via size of the substrate circuit pattern dictate the density of the terminal pattern. With techniques such as laminated circuit patterns, and dielectric-embedded circuit patterns, substrate conductor density can be increased dramatically. However, the minimum via diameter still provides a limitation on either the number of terminals (due to deletion of terminals in via areas) or the terminal spacing (due to the presence of vias between terminals). The minimum via diameter is dictated by several factors, including registration between layer circuit patterns, plating or etching tolerances and photo-mask tolerance and alignment limitations. 
     In particular, a via will not plate properly when the circuit pattern is large compared to the via. Because the height of the via requires substantial upward plating, the via must be of sufficient diameter to permit the growth of the via, while providing an efficient plating process for the balance of the circuit pattern. Further, when a via is formed through the substrate dielectric material, the material is laser-ablated or otherwise drilled through to provide the via hole. The depth of the via hole dictates the process time required to laser-ablate the hole. 
     Therefore, it would be desirable to provide substrates having reduced via diameter in light of the above-listed limitations and while providing a desirable plating aspect ratio. It would further be desirable to provide a method of manufacturing the substrates having decreased via diameter with low incremental cost. It would also be desirable to reduce the time required to generate via holes in a dielectric material. 
     SUMMARY OF THE INVENTION 
     The above objectives of reducing via diameter in a semiconductor package substrate while maintaining plating aspect ratios and decreasing via hole formation time are provided in a substrate and method for manufacturing a substrate. 
     The substrate and resulting semiconductor substrate include vias that are formed in two parts: a first tier section that is plated to a metal circuit pattern, and a second half-via that is added atop the tier section through a hole produced in a dielectric that is deposited over the substrate. The method includes the steps of plating the first tier section onto the circuit pattern, adding dielectric over the substrate, ablating the substrate to produce a void through to the tier and then adding metal in the void to produce a via from the conductive pattern to the surface of the dielectric. The tier and the half-via have differing diameter to provide registration tolerance, but the half-via may be of larger or smaller diameter than the tier. A tin plating may be used above the circuit material and/or above the tier to provide plating control in accordance with an alternative method for providing the multi-level vias. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A–1H  are pictorial diagrams depicting a cross-sectional view of stages of preparation of a substrate in accordance with an embodiment of the present invention; 
         FIG. 2  is a pictorial diagram depicting a cross-section of a substrate in accordance with an embodiment of the present invention; 
         FIGS. 3A and 3B  are pictorial diagrams depicting a perspective view of a via metal structure as present in embodiments of the present invention; 
         FIGS. 4A and 4B  are pictorial diagrams depicting semiconductor packages circuits in accordance with embodiments of the present invention; 
         FIGS. 5A–5H  are pictorial diagrams depicting a cross-sectional view of stages of preparation of a substrate in accordance with another embodiment of the present invention; and 
         FIG. 6  is a pictorial diagram depicting a via metal structure as present in another embodiment of the present invention. 
     
    
    
     The invention, as well as a preferred mode of use and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like parts throughout. 
     DETAILED DESCRIPTION 
     Referring now to the figures and in particular to  FIGS. 1A–1H , a cross-sectional view of stages of preparation of a substrate in accordance with an embodiment of the present invention is shown. 
       FIG. 1A  shows a first stage  10 A in preparation of a substrate. A metal covered dielectric  16 A may be formed by depositing or laminating a metal, generally copper, and planarizing/reducing the metal to yield a very thin metal layer  12 A that will be plated over and then un-plated areas will be etched away in subsequent process steps. A resist mask  14 A is applied over metal layer  12 A, generally by a dry-film photo-masking process. The mask is a negative image of circuit patterns to be generated on substrate  10 A in a plate-up process. 
       FIG. 1B  shows a next state of preparation of substrate stage  10 B. Metal, also generally copper, is plated over the exposed regions between plating resist  14 A patterns to form circuit patterns  18 A and  18 B. Next, as shown in  FIG. 1C , a second resist mask  20 A is applied to form substrate stage  10 C. Holes  21 A in resist mask provide support for plating up portions of vias in accordance with embodiments of the present invention. 
     In  FIG. 1D , a next stage  10 D of substrate preparation is illustrated. Metal, again generally copper, is plated into holes  21 A to form a portion of a via  22 A, referred to as a “tier” or stub. Generally, the portion has the height of half of the final via, but the height may be varied depending on plating requirements generally dictated by the size of the via vs. the size of the conductive circuit patterns. 
     Once tier  22 A has been fabricated on circuit pattern  18 B, the resist layers ( 20 A,  14 A) are stripped and the completely metalized dielectric layer  16 A is exposed in substrate stage  10 E of  FIG. 1E . Substrate stage  10 E is etched to remove the metal  12 A bridging circuit patterns  18 A,  18 B that was present to support the plating operations. The resulting substrate stage  10 F of  FIG. 1F  includes circuit patterns formed from original metal layer  12 B and plated up circuit pattern areas  18 A and  18 B, along with via tiers such as via tier  22 A. 
     Next, circuit patterns  18 A and  18 B along with via tier  22 A are covered by a second dielectric layer  16 B that encloses the circuit patterns forming substrate stage  10 G, as shown in  FIG. 1G . Holes  24  are laser-ablated or formed by machining or other means through dielectric layer  16 B above via tiers  22 A to form substrate stage  10 H as shown in  FIG. 1H . 
     Finally, as shown in  FIG. 2 , metal is applied in holes  24  to complete the vias by either plating or application of conductive paste. The metal forms a half via portion  26  that completes an electrical path from circuit pattern  18 B to the top of second dielectric layer  16 B. The above-described process permits plating of much smaller vias than is possible with a plating process that plates the entire height of a via. Structural differences are present in the vias of the present invention, as the diameter of tier  22 A differs from that of half-via  26 , so that one or the other can be registered within the periphery of the other. 
     Referring now to  FIG. 3A , half-via portion  26  atop tier  22 A having a larger diameter is illustrated. Only the metallic portion of the via is shown along with circuit pattern  18 B to which the via has been added.  FIG. 3B  shows a reversal in relative diameters with a larger diameter half-via portion  26 A added atop a smaller diameter tier  22 B that has been plated on a circuit pattern  18 C.  FIGS. 3A and 3B  are provided to illustrate in detail the via structures (inter-dielectric) of the present invention as produced by the above-described process. An encapsulation may be added over semiconductor die  36 A and substrate  30 A to provide a complete semiconductor package that is sealed against environmental conditions. 
     Referring now to  FIG. 4A , a semiconductor package in accordance with an embodiment of the present invention is shown. 
     Substrate  30 A is a substrate prepared according to the above-described process and having vias  32 A and  32 B formed in accordance with the above-described structures, one via  32 A having a larger diameter tier near the top of substrate  30 A as depicted and one via  32 B having a smaller diameter tier near the top of substrate  30 A as depicted. A semiconductor die  36 A is attached to substrate  30 A by an adhesive (not shown) and electrically connected by wires  38  to the circuit patterns of substrate  30 A. Solder ball  34 A terminals for forming a ball grid array (BGA) attach pattern are attached to plated areas formed on vias  32 A and  32 B. An encapsulation may be added over semiconductor die  36 A and substrate  30 A to provide a complete semiconductor package that is sealed against environmental conditions. 
     Referring now to  FIG. 4B , a semiconductor package in accordance with another embodiment of the present invention is shown. Substrate  30 B is a substrate prepared according to the above-described process and having vias  32 C and  32 D formed in accordance with the above-described structures, one via  32 C having a larger diameter tier near the top of substrate  30 B as depicted and one via  32 D having a smaller diameter tier near the top of substrate  30 B as depicted. A semiconductor die  36 B in the form of a flip-chip die is mechanically and electrically connected to substrate  30 B by solder balls  39  attached to the circuit patterns of substrate  30 B. Solder ball  34 B terminals for forming a ball grid array (BGA) attach pattern are attached to plated areas formed on vias  32 C and  32 D. An encapsulation may be added over semiconductor die  36 B and substrate  30 B to provide a complete semiconductor package that is sealed against environmental conditions. 
     Referring now to  FIGS. 5A–5H , a cross-sectional view of stages of preparation of a substrate in accordance with another embodiment of the present invention is shown. 
       FIG. 5A  shows a first stage  40 A in preparation of the substrate. A metal covered dielectric  46 A may be formed by depositing or laminating a metal, generally copper, and planarizing/reducing the metal to yield a very thin metal layer  42 A that will be plated over and then un-plated areas will be etched away in subsequent process steps. A resist mask  44 A is applied over metal layer  42 A, generally by a dry-film photo-masking process. The mask is a negative image of circuit patterns to be generated on substrate  40 A in a plate-up process. 
       FIG. 5B  shows a next state of preparation of substrate stage  40 B. A metal unaffected by the etchant, generally tin, is plated over the exposed regions between plating resist  44 A patterns to form circuit patterns  48 A and  48 B. Next, as shown in  FIG. 5C , a second resist mask  50 A is applied to form substrate stage  40 C. Holes  41 A in resist mask provide support for plating up portions of vias in accordance with embodiments of the present invention. 
     In  FIG. 5D , a next stage  40 D of substrate preparation is illustrated. Metal, generally copper, is plated into holes  41 A to form a tier portion  52 A of via. Then, tin (or other metal unaffected by the etchant) is plated to form a plating layer  45 A over tier  52 A to form substrate stage  40 E of  FIG. 5E . 
     Once tier  52 A with plating layer  45 A has been fabricated on circuit pattern  48 B, the resist layers ( 50 A,  44 A) are stripped and the completely metalized dielectric layer  46 A is exposed in substrate stage  40 F of  FIG. 5F . Substrate stage  40 F is etched to remove the portions of metal layer  42 A that were bridging circuit patterns  48 A,  48 B and was present to support the plating operations. The resulting substrate stage  40 G of  FIG. 5G  includes circuit patterns formed from original metal layer portions  42 B and plated up circuit pattern areas  48 A and  48 B (of differing metal type), along with via tiers such as via tier  52 A. 
     Next, circuit patterns  48 A and  48 B along with via tier  52 A are covered by a second dielectric layer forming an enclosed dielectric  46 B that encloses the circuit patterns. Holes  54  are laser-ablated or formed by machining or other means through dielectric layer  46 B above via tiers  52 A to form substrate stage  40 G. 
     Finally, metal is applied in holes  54  to complete the vias by either plating or application of conductive paste. The metal forms a half via portion  56  that completes an electrical path from circuit pattern  48 B to the top of second dielectric layer  46 B. The above-described process permits plating of much smaller vias than is possible with a plating process that plates the entire height of a via as described above for the other embodiments of the invention. Structural differences are present in the vias of the present embodiment, as a plating layer  45 A of metal not susceptible to the etchant (e.g., tin) is present between the top half-via portion  56  and tier  52 A and circuit pattern  48 B is formed from a non-susceptible metal atop a like-shaped portion of the original metal layer portions  42 B. 
       FIG. 6  depicts the structure of the via showing only the metal portions of the via and circuit patterns. Half-via portion  56 A is shown atop plating layer  45 A deposited on tier  52 A. The relative diameter of tier to plating layer  45 A and tier  52 A can be reversed, as for the embodiment depicted in  FIG. 3B .  FIG. 6  also shows plating layer forming circuit pattern  48 B atop the portion of original circuit material  42 B on which tier  52 A was plated. 
     The above description of embodiments of the invention is intended to be illustrative and not limiting. Other embodiments of this invention will be obvious to those skilled in the art in view of the above disclosure and fall within the scope of the present invention.