Abstract:
An apparatus includes a hardware unit having an interface to a clock generator, an interface to a power supply and an interface to a software unit. The interface to the software unit is configurable to receive a request from the software unit that identifies at least one operating point for the apparatus. The hardware unit is operable to control at least one of the clock generator and the power supply so as to achieve the requested operating point.

Description:
TECHNICAL FIELD 
       [0001]    The exemplary and non-limiting embodiments of this invention relate generally to energy/power management and system control methods and apparatus and, more specifically, relate to techniques to control system performance and to achieve power management when the system is implemented in an integrated circuit format, such as in an ASIC. 
       BACKGROUND 
       [0002]    Various abbreviations that appear in the specification and/or in the drawing figures are defined as follows: 
         [0003]    DFS dynamic frequency scaling 
         [0004]    DVS dynamic voltage scaling 
         [0005]    DVFS dynamic voltage and frequency scaling 
         [0006]    HW hardware 
         [0007]    OP operating point 
         [0008]    PM power management 
         [0009]    PPD peripheral power domain 
         [0010]    PSS processor subsystem 
         [0011]    SC system control 
         [0012]    SW software 
         [0013]    The OP may be considered as some particular functional performance point for a system or subsystem, and may be considered to represent a combination of clock frequencies and operating voltages that are in use. 
         [0014]    In some current ASIC design architectures the various subsystem and/or system performance control methods are embodied in SW layers, while the HW simply provides a mechanism to control the system performance in frequency, i.e., clock frequency, and voltage. For example, to achieve frequency and voltage control the SW may be responsible for determining a level of desired performance and for mapping the determined level of system performance into different subsystem performance states. The result of this processing by the SW is then passed to the HW to effect the indicated changes in the clock frequency and/or power supply output voltage levels. 
         [0015]    It should be noted that the frequency and/or voltage control function may need to be accomplished during runtime, and thus should ideally be accomplished with minimal latency. However, this may be difficult to accomplish if the system SW is engaged in other runtime-related tasks. 
         [0016]    WO 2005/050425 A1 describes a device for regulating a voltage supply to a semiconductor device. The device has memory for storing a plurality of performance ranges, where respective performance ranges are associated with a respective supply voltage. The device also includes a measurement unit for measuring the performance of the semiconductor device and a regulator for modifying the supply voltage to the semiconductor device if the measured performance of the semiconductor device is not within a predetermined portion of the performance range associated with the voltage supplied to the semiconductor device. A set of reference circuit count values is stored in a look-up table, where each set of reference circuit count values is associated with a respective supply voltage. 
         [0017]    What is needed is a technique to enable accurate, simple and low latency control of frequency and voltage in an integrated circuit environment. 
       SUMMARY OF THE EXEMPLARY EMBODIMENTS 
       [0018]    The foregoing and other problems are overcome, and other advantages are realized, in accordance with the non-limiting and exemplary embodiments of this invention. 
         [0019]    In a first aspect thereof the exemplary embodiments of this invention provide a method that comprises, receiving a request from a software unit that identifies at least one operating point for a subsystem of an integrated circuit; and in response to the received request, controlling at least one of a clock generator and a power supply of the integrated circuit so as to achieve the requested operating point. 
         [0020]    In another aspect thereof the exemplary embodiments of this invention provide a computer-readable memory that stores computer program instructions, execution of which result in performance of operations that comprise, in response to receiving at a hardware unit a request from a software unit that identifies at least one operating point for a subsystem of an integrated circuit, controlling at least one of a clock generator and a power supply of the integrated circuit so as to achieve the requested operating point; and sending a status indication to the software unit to indicate at least when the requested operating point has been established. 
         [0021]    In another aspect thereof the exemplary embodiments of this invention provide an apparatus that includes a hardware unit having an interface to a clock generator, an interface to a power supply and an interface to a software unit. The interface to the software unit is configurable to receive a request from the software unit that identifies at least one operating point of a subsystem of the apparatus. The hardware unit is operable to control at least one of the clock generator and the power supply so as to achieve the requested operating point. 
         [0022]    In a further aspect thereof the exemplary embodiments of this invention provide an apparatus that comprises means for receiving a request from a software unit that identifies at least one operating point for a subsystem of an integrated circuit; means, responsive to the received request, for controlling at least one of a clock generator and a power supply of the integrated circuit so as to achieve the requested operating point; and means for sending a status indication to the software unit to indicate at least when the requested operating point has been established, where a requested performance, voltage, frequency or a combination of these may be indicated by the status. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]    The foregoing and other aspects of the teachings of this invention are made more evident in the following Detailed Description, when read in conjunction with the attached Drawing Figures, wherein: 
           [0024]      FIG. 1  is a simplified high level block diagram of an integrated circuit that is constructed and operated in accordance with the exemplary embodiments of this invention. 
           [0025]      FIG. 2  is an example of peripheral clock request handling in HW. 
           [0026]      FIG. 3  depicts an exemplary control interface,  FIG. 4  depicts an exemplary status interface,  FIG. 5A  depicts an exemplary clock configuration interface and  FIG. 5B  depicts an exemplary voltage configuration interface that together form a part of a HW/SW interface shown in  FIG. 1 . 
           [0027]      FIGS. 6A and 6B , collectively referred to as  FIG. 6 , depict process flow between the system HW and two exemplary subsystem SW units shown in  FIG. 1 . 
           [0028]      FIG. 7  is a block diagram that illustrates the operation of the system HW in accordance with the exemplary embodiments of this invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    The exemplary embodiments of this invention provide enhanced energy/power management and system control, as well as overall power consumption optimization for use in, for example, an embedded system (HW and SW), such as an ASIC. The exemplary embodiments of this invention provide methods and apparatus to partition the HW and SW to implement a dynamic voltage and frequency scaling feature. The use of the exemplary embodiments of this invention enables more optimal HW and SW partitioning for a variety of data processor, system and subsystem embodiments wherein processing performance scaling is desirable. The phrase “more optimal” in this context implies at least a facilitation of HW and SW integration and enhanced and straightforward runtime performance control. In general, overall system performance, in at least a power efficiency sense, is improved by providing a more efficient method for controlling subsystem performance, without sacrificing overall configurability and the flexibility of subsystem performance control. 
         [0030]      FIG. 1  is a simplified high level block diagram of an integrated circuit (IC)  10 , which may be embodied in an ASIC, that is constructed and operated in accordance with the exemplary embodiments of this invention. The IC  10  includes a plurality of subsystems  12  which can take any suitable form depending on the purpose and overall functionality of the IC  10 . As one non-limiting example, and assuming that the IC  10  is intended for use in a communications device such as a cellular phone, the various subsystems  12  (subsystem 1 , subsystem 2 , . . . , subsystem n ) may implement radio frequency reception and demodulation functions, radio frequency modulation and transmission functions, and/or baseband functions such as encoding, decoding, analog to digital conversion and digital to analog conversion. Each subsystem  12  may embody a separate processor subsystem, and each processor subsystem may have associated SW  20  (collectively referred to below as the SW  20 ). The IC  10  may also include a plurality of peripheral units  13 . The peripheral units  13  may embody interfaces to other systems, such as a camera, a display, a USB port, and/or they may embody independent modules that may comprise computing algorithms and memories, as non-limiting examples. Note that each subsystem may access a plurality of the peripheral units  13 , and each subsystem  12  may access the same peripheral units  13 . The subsystems  12  and peripheral units  13  are assumed to be supplied with suitable clock signals and power supply operating (and possibly bias) voltages from a clock generator  14  and a power supply  16 , respectively. In practice, there may be a plurality of clock generators  14  and a plurality of power supplies  16  present, and the use of the exemplary embodiments is compatible with providing control over multiple clock generators and multiple power supplies. Thus, any subsequent references herein to the clock generator  14  and to the power supply  16  should not be viewed as limiting the numbers of these units that may be present. An IC HW block  18  is coupled via a control bus  19  to the clock generator  14  and to the power supply  16  for exerting overall control over clock frequencies and power supply voltage levels, in accordance with the exemplary embodiments of this invention. In practice separate control buses may be used between the HW block  18  and the clock generator  14  and the power supply  16 . A plurality of interfaces (I/Fs)  22 A,  22 B are assumed to be present, such as an I/F  22 A between the SW/subsystems/peripherals  12 ,  13  and the HW block  18 . The control bus  19  may also be assumed to be associated with an I/F  22 B. 
         [0031]    The SW block(s) or unit(s)  20  may include appropriate operating software for the respective subsystem  12 . In some situations it may be desirable that the HW  12 -SW  20  is operating system (OS)-independent. 
         [0032]    In general, a PSS subsystem clock domain control I/F contains basically the HW register(s)  18 A containing clock generator  14  phase lock loop (PLL) setup, clock divider and clock source selection bits (e.g., see also  FIG. 2 ). In a similar manner, at least one HW register  18 B stores bits for accomplishing control over the power supply  16 . 
         [0033]    It should be noted that the HW block  18  may be implemented solely as HW components such as registers, logic gates, state machines and the like, or it may be implemented solely as a microcontrol unit that operates using a program stored in a local (e.g., on-chip) memory (firmware), or it may be implemented as a combination of HW components and firmware. 
         [0034]    In the exemplary embodiments of this invention the configurability (non-runtime control of the system  10 ) may be implemented by the SW  20 , while the runtime control is handled in the HW  18 . 
         [0035]    Described below are details for the HW-SW interface  22 A and the functional partitioning between the HW  18  and the system SW  20 , and the use of the control bus  19  interface  22 C by the HW block  18 . As will be apparent, the use of these embodiments enhances the overall runtime performance of the system  10  (e.g., enhances the processing performance and power efficiency), while decreasing the HW and SW integration time and resource needs. 
         [0036]    In general, in first embodiments of voltage management and frequency management (also referred to as option  1 ) the actual voltage/clock domain partitioning is hidden from the SW  20 , and the SW  20  is responsible only for providing general control instructions to the HW  18 , such as a request to change one or both of the voltage/frequency settings, or to request that voltages/clocks be turned on based on the needs of the SW  20 . In second embodiments of voltage management and frequency management (also referred to as option  2 ) the SW  20  need not request voltage/frequency at all when starting to use a certain subsystem  12  (or peripheral). Instead, a first access to the particular subsystem/peripheral may automatically generate a voltage/clock request to the HW  18  which responds by automatically turning on the required voltage/clock. Subsequently turning off the voltages/clocks may also be accomplished in an automatic fashion, such as by expiration of a HW timer that is set to expire at some time t after a last SW access to the subsystem/peripheral. The value of t may be fixed, or it may be programmable and settable based on configuration information (latency requirement time) received at the HW block  18  via the I/F  22 A. 
         [0037]      FIG. 2  presents a non-limiting example of peripheral  13  clock request handling by the HW  18 . The clock generator  14  is assumed to include a clock source  14 A (e.g., a crystal oscillator (XO)), a PLL  14 B, a plurality of programmable dividers (DIV)  14 C and a plurality of gates  14 D for gating on and off generated clock signals to individual ones of the peripherals  13 . A feature of this embodiment is that the SW  20  does not need to have knowledge of the clock chain at all, instead it simply requests a clock for a certain HW peripheral  13  that the SW  20  needs to use, and the HW  18  handles the actual setup and control of the clock generation. For example, the SW  20  turns on a request bit for peripheral  1  (step 1) and this request propagates through the clock chain (step 2) in the system ASIC and baseband modules without SW interaction. The SW  20  then waits for an indication (e.g., such as by polling a status bit, or by receiving an interrupt) that the clock is available at the peripheral device (steps 3 and 4). 
         [0038]    Note that the clock request chain is presented as it is in  FIG. 2  simply to emphasize that in this topology the clock request goes only to a next level of clock control in the chain in order to make the clock gating as efficient as possible. For example, the divider  14 C may have internal clock gating which is controlled by all clock branches that originate at the divider. Similarly, the PLL  14 B may handle PLL startup and shutdown based on requests made for it. The PLL  14 B may also ensure that acknowledge signaling back towards the requestor(s) is given only when the PLL  14 B is locked and stable. The same applies for control of the clock source  14 A. This may imply the use of an XO settling time counter or similar type of mechanism to indicate when the XO is stable. 
         [0039]    In order to provide additional enhancements for the peripheral clock control there may be a clock request interval time also provided for the HW  18 . In this case the HW  18  may combine all such intervals together and select a smallest interval value for use in the PLL  14 B and clock source  14 A control. The PLL  14 B and clock source  14 A may have programmable settling time values which in effect set limits for PLL and clock source shutdown in the HW  18 . Alternatively, this can be handled by the SW  20 . 
         [0040]    In a first embodiment of runtime DFS control, the dynamic frequency scaling process assumes that the SW  20  handles in a centralized manner a determination of a need to change the PSS performance, while the HW  18  is responsible for the actual control operations to make the PSS performance change. In practice this may imply that the SW  20  simply informs the HW  18  of what system performance is needed in a range of, for example, 0 to 100. 
         [0041]    As one example, the HW-SW interface  22 A may support three states for accomplishing the PSS performance control from the SW  20  perspective with regard to clock management. The first state ( 0 ) indicates SW  20  controlled clock tree handling, the second state ( 1 ) indicates HW  18  controlled clock tree handling, and the third state ( 2 ) indicates HW  18  controlled clock request and clock tree handling. 
         [0042]      FIG. 3  depicts an exemplary control interface,  FIG. 4  depicts an exemplary status interface,  FIG. 5A  depicts an exemplary clock configuration interface and  FIG. 5B  depicts an exemplary voltage configuration interface that together form a part of the HW/SW I/F  22 A for a first runtime DFS option. The selection between SW or HW controlled OP handling is done from the configuration interface (SW controlled OP handling=Option # 2 , HW controlled OP handling=Option # 1 ). The configuration interfaces depicted in  FIGS. 5A and 5B  are valid for both Option # 1  and Option # 2 . In these Figures any listed State ranges and Default State should be considered exemplary and non-limiting. In  FIG. 3  the SW  20  instructs the HW  18  of the PSS performance request and operating point, and provides a processing interval. In  FIG. 4  the HW  18  indicates to the SW  20  the currently available performance level, the target performance level, the currently available operating point and the target operating point. 
         [0043]      FIGS. 6A and 6B , collectively referred to as  FIG. 6 , depict process flow between the system HW  18  and two exemplary subsystem  12  SW units  20  shown in  FIG. 1  (also referred to here as PSS 1  and PSS 2 ).  FIG. 6  is useful in gaining a greater understanding of  FIGS. 3 ,  4 ,  5 A and  5 B. 
         [0044]      FIG. 6  depicts the operation of the system  10  during a system startup (configuration phase) and then during system runtime flow. During the startup phase each SW unit  20  makes a write to a respective (PSS 1 , PSS 2 ) frequency operation parameter (OP) register and voltage OP configuration register to configure respective clock(s) and the corresponding voltage(s). In the illustrated example it is assumed the PSS 1  and PSS 2  share the same power supply 16 voltage supply, but use separate clocks. 
         [0045]    At runtime the HW  18  initializes corresponding PSS 1  and PSS 2  OP requests and frequency and voltage status registers. The subsequent blocks show PSS 1  and PSS 2  both making a request to the HW  18  for more performance by making a write to corresponding system HW PSS 1  (PSS 2 ) OP request registers, and the response of the HW  18  by performing voltage scaling and frequency scaling according to the values previously stored during the configuration phase in the respective PSS 1  and PSS 2  configuration registers. The HW  18  initiates an interrupt to the SW  20  when the requested performance is available (e.g., after the required settling times of the power supply  16  and/or clock generator  14 ). 
         [0046]    Note that  FIG. 6B  also shows a request made by PSS 1  for a reduction in performance. In response the HW  18  performs the scaling of the associated clock, and checks the highest requested operating point requirement for the voltage supply (power supply  16 ). In this case the HW  18  determines that the voltage scaling (reduction) should not be performed, as it would result in a voltage less than the voltage needed to support the operating performance previously requested for this same voltage supply by PSS 2 . The HW  18  then initiates an interrupt to the SW  20  of PSS 1  when the requested (reduction in) performance is available. 
         [0047]    With regard to the SW-HW interactions and sequences, a basic principle is to hide the actual clock frequency control from the SW  20 . Preferably, the SW  20  simply instructs the HW  18  of the processing power requirement(s) and the HW  18  handles then the actual clock frequency control. As a requested performance level may not be available immediately (e.g., due to some HW dependency or voltage control requirement), a mechanism is also provided to inform the SW  20  when the targeted performance level has been achieved. This may be accomplished by generating a dedicated interrupt for the SW  20 , or by setting an appropriate status bit that can be periodically polled by the SW  20 . A goal of this procedure is to make the runtime control of the system of the IC  10  as simple as possible from the SW  20  perspective. 
         [0048]    The second option referred to (Option # 2 ) also moves the performance reasoning (performance logic or algorithm) into the HW  18 . In this case there need not be any runtime type of interface control provided for the SW  20 . 
         [0049]    Note, however, that the configuration of the HW  18  may still be performed if desired by the SW  20 . 
         [0050]    As another example, the HW-SW interface  22 A may support three states for accomplishing the PSS performance control from the SW  20  perspective with regard to operating point (OP) management. The first state ( 0 ) indicates SW  20  OP handling, the second state ( 1 ) indicates partial HW  18  controlled OP handling (Option # 1 ), and the third state ( 2 ) indicates full HW  18  controlled OP handling (Option # 2 ). 
         [0051]    Discussed now are SW-HW interactions and sequences with respect to  FIG. 7 . The discussion assumes that the operating point definition option (Option # 2 ) for the HW-SW interface is used. In this example the HW  18  collects predefined (SW  20  configured) operating point requests together from several processor subsystems  12  that reside in the common voltage domain. 
         [0052]    The PSS SW  20  selects a required operating point based on need by using the operating point request HW interface. The HW  18  collects all of the processor subsystem  12  requests (Step 1) and selects a maximum operating point (Step 2). This step can be accomplished using a lookup table (LUT)  18 C shown in  FIG. 1 . The HW  18  then fetches the predefined voltage value from the configuration IF for the selected operating point. This voltage value is then combined as data with a predefined PM IF header (Step 3) which is then delivered through the control bus  19  to the power supply  16  (steps 4, 5, 6 and 7). The HW  18  may, for example, use a SW programmable timer for voltage settling time if the power supply  16  and the PM IF bus do not provide this information. After the voltage settling time has expired the HW  18  informs the SW  20  using the status IF that the OP has changed (Step 4), and thus informs the SW  20  that it may continue and use the new operating point. 
         [0053]    Note that the various blocks shown in  FIG. 7  may be viewed as method steps, and/or as operations that result from operation of computer program code, and/or as a plurality of coupled logic circuit elements constructed to carry out the associated function(s). 
         [0054]    As was noted above, the various exemplary embodiments may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the exemplary embodiments of this invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof. 
         [0055]    As such, it should be appreciated that at least some aspects of the exemplary embodiments of the inventions may be practiced in various components such as integrated circuit chips and modules. The design of integrated circuits is by and large a highly automated process. Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be fabricated on a semiconductor substrate. Such software tools can automatically route conductors and locate components on a semiconductor substrate using well established rules of design, as well as libraries of pre-stored design modules. Once the design for a semiconductor circuit has been completed, the resultant design, in a standardized electronic format (e.g., Opus, GDSII, or the like) may be transmitted to a semiconductor fabrication facility for fabrication as one or more integrated circuit devices. 
         [0056]    Various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. As but one example, the use of other similar or equivalent fields in the various interface messaging shown in  FIGS. 3-8  may be attempted by those skilled in the art. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention. 
         [0057]    Further, it should be appreciated that the exemplary embodiments of this invention are not limited for use with any one particular type of wireless communication system, and that they may be used to advantage in many different types of wireless communication systems, such as when embodied in apparatus used in wireless communication handsets. It should be noted that the terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements, and may encompass the presence of one or more intermediate elements between two elements that are “connected” or “coupled” together. The coupling or connection between the elements can be physical, logical, or a combination thereof. As employed herein two elements may be considered to be “connected” or “coupled” together by the use of one or more wires, cables and/or printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as several non-limiting and non-exhaustive examples. 
         [0058]    Furthermore, some of the features of the examples of this invention may be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples and exemplary embodiments of this invention, and not in limitation thereof.