Abstract:
An output stage for an LED driver is provided. In particular, a low voltage clamp, which uses several cascode circuits, is provided to protect low voltage switching transistors in the range of two times higher voltage application under both normal and fault conditions. Additionally, a circuit for regulating the bias voltage applied to each of the cascode circuits is provided to prevent damage during startup, while an internal voltage regulator is settling.

Description:
TECHNICAL FIELD 
       [0001]    The invention relates generally to an output stage for a light emitting diode (LED) driver and, more particularly, to a clamp circuit for an output stage. 
       BACKGROUND 
       [0002]    Referring to  FIG. 1  of the drawings, the reference numeral  100  generally designates a conventional output stage for a LED driver. In operation, a voltage of about 6.5V is applied through voltage rail  102  to LEDs  104  and  106 . These LEDs  104  and  106  are coupled to pins or terminal  108  and  110  of the outputs stage  100  through resistors R 1  and R 2 . The output stage  100  employs cascodes to switch LEDs  104  and  106  “on” and “off” as desired. In particular, transistors Q 1  and Q 3  (which are preferably both NMOS transistors) operate as the “turn on” transistors or switches for LEDs  104  and  106 , receiving enable signals EN 1  and EN 2 . Transistor Q 2  (which is also generally an NMOS transistor) receives a bias voltage BIAS at its gate (or control electrode). Additionally, each of transistors Q 1 , Q 2 , and Q 3  has a parasitic diode D 1 , D 2 , and D 3  (respectively) between its drain and body. Each of the enable signals EN 1  and EN 2 , though, are generally about 3.3V, which is much lower than the 6.5V on rail  102 . Thus, to function properly, the voltage rating of transistors Q 1  and Q 3  is much greater than 6.5V, which is costly in terms of area. 
       SUMMARY 
       [0003]    A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a plurality of terminals; a clamp circuit including: a voltage divider; a voltage regulator; an inverter having a power terminal, an input terminal, and an output terminal, wherein the power input terminal is coupled to the voltage regulator, and receives an actuation signal at its input terminal; a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the voltage regulator, and wherein the control electrode of the first transistor is coupled to the output terminal of the inverter, and the second passive electrode of the first transistor is coupled to a bias node; and a plurality of cascode circuits, wherein each terminal is coupled to at least one cascode circuit, and wherein each cascode circuit is coupled to the bias node; a back-to-back switch is coupled between the voltage divider and the bias node; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the second transistor receives a first enable signal; a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the third transistor receives a second enable signal; and a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the second passive electrodes of the second and third transistors, and wherein the control electrode of the fourth transistor receives a bias voltage. 
         [0004]    In accordance with a preferred embodiment of the present invention, each of the cascode circuits further comprises: a PMOS transistor having a first parasitic diode between its drain and its body; and an NMOS transistor having a second parasitic diode between its drain and its body, wherein the gate of the NMOS transistor is coupled to the gate of the PMOS transistor. 
         [0005]    In accordance with a preferred embodiment of the present invention, the second, third, and fourth transistors are each an NMOS transistor having a parasitic diodes between its drain and its body. 
         [0006]    In accordance with a preferred embodiment of the present invention, the clamp circuit further comprises a resistor that is coupled between the voltage regulator and the first passive electrode of the first transistor. 
         [0007]    In accordance with a preferred embodiment of the present invention, the first transistor is a PMOS transistor having its source and its body coupled to the voltage regulator. 
         [0008]    In accordance with a preferred embodiment of the present invention, the voltage divider further comprises a plurality of resistors coupled in series with one another. 
         [0009]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a voltage rail; a first terminal; a second terminal; a clamp circuit including: a voltage divider that is coupled between the voltage rail and ground; a voltage regulator that is coupled to the voltage rail; an inverter having a power terminal, an input terminal, and an output terminal, wherein the power input terminal is coupled to the voltage regulator, and receives an actuation signal at its input terminal; a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the voltage regulator, and wherein the control electrode of the first transistor is coupled to the output terminal of the inverter, and the second passive electrode of the first transistor is coupled to a bias node; a back-to-back switch that is coupled between the voltage divider and the bias node; a first cascode circuit that is coupled to the first terminal and to the bias node; and a second cascode circuit that is coupled to the second terminal and to the bias node; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the second transistor receives a first enable signal; a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to at least one of the cascode circuits, and wherein the control electrode of the third transistor receives a second enable signal; and a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the second passive electrodes of the second and third transistors, and wherein the control electrode of the fourth transistor receives a bias voltage. 
         [0010]    In accordance with a preferred embodiment of the present invention, the back-to-back switch further comprises: a first PMOS transistor that is coupled to the voltage divider at its source and that is coupled to the input terminal of the inverter at its gate; and a second PMOS transistor that is coupled to the drain of the first PMOS transistor at its drain, that is coupled to the bias node at its source, and that is coupled to the input terminal of the inverter at its gate. 
         [0011]    In accordance with a preferred embodiment of the present invention, the voltage on the voltage rail is about 6.5V. 
         [0012]    In accordance with a preferred embodiment of the present invention, the voltage output from the voltage regulator is about 3.3V. 
         [0013]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a voltage rail; a first terminal; a second terminal; a clamp circuit including: a first resistor that is coupled to the voltage rail; a second resistor that is coupled between the first resistor and ground; a voltage regulator that is coupled to the voltage rail; an inverter having a power terminal, an input terminal, and an output terminal, wherein the power input terminal is coupled to the voltage regulator, and receives an actuation signal at its input terminal; a third resistor that is coupled to the voltage regulator; a first PMOS transistor that is coupled to the third resistor at its source, that is coupled to the voltage regulator at its body, and that is coupled to a bias node at its drain; a second PMOS transistor that is coupled to the node between the first and second resistors at its source and that is coupled to the input terminal of the inverter at its gate; a third PMOS transistor that is coupled to the drain of the second PMOS transistor at its drain, that is coupled to the input terminal of the inverter at its gate, and that is coupled to the bias node at its source; a first NMOS transistor that is coupled to the first terminal at its drain and that is coupled to the bias node at its gate; a fourth PMOS transistor that is coupled to the bias node at its gate and its source and that is coupled to the source of the first NMOS transistor at its drain; a second NMOS transistor that is coupled to the second terminal at its drain and that is coupled to the bias node at its gate; and a fifth PMOS transistor that is coupled to the bias node at its gate and its source and that is coupled to the source of the second NMOS transistor at its drain; a third NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and that receives a first enable signal at its gate; a fourth NMOS transistor that is coupled to the source of the second NMOS transistor at its drain and that receives a second enable signal at its gate; and a fifth NMOS transistor that is coupled to the sources of the third and fourth NMOS transistors at its drain, that receives a bias voltage at its gate, and that is coupled to ground at its source. 
         [0014]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0016]      FIG. 1  is an example of a convention output stage for an LED driver; and 
           [0017]      FIG. 2  is an example of an output stage for an LED driver in accordance with a preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0019]    Referring to  FIG. 2  of the drawings, the reference numeral  200  generally designates an example of an output stage for an LED driver in accordance with a preferred embodiment of the present invention. Similar to stage  100 , stage  200  includes transistors Q 1 , Q 2 , and Q 3 , but stage  200  also includes clamp circuit  202  that is coupled between the pins or terminals of stage  200  and transistors Q 1  and Q 3 . Clamp circuit  202  generally comprises back-to-back switch  206 , cascode circuits  208  and  210 , inverter  204 , resistor R 3 , voltage regulator  212 , and a voltage divider (R 4  and R 5 ). 
         [0020]    In particular, each of transistors Q 1  and Q 3  has a cascode circuit  208  and  210  coupled between its pin or terminal  108  and  110  and its drain to operate as a “protection cascode.” Cascode circuit  208  is coupled between pin  108  and the drain of transistor Q 1  and generally comprises transistors Q 6  and Q 7  (which are preferably a PMOS transistor and an NMOS transistor, respectively). Transistor Q 6  includes a parasitic diode D 4  between its drain (or passive electrode) and body, and transistor Q 6  is coupled to bias node N 1  at its gate (or control electrode) and source (or passive electrode), while its drain is coupled to the drain of transistor Q 1 . Transistor Q 7  includes a parasitic diode D 5  between its drain and body, and transistor Q 6  is coupled to the bias electrode at its gate, pin  108  at its drain, and the drain of transistor Q 1  at its source. Additionally, cascode circuit  210  is coupled between pin  110  and the drain of transistor Q 3 , having the same general configuration as cascode circuit  208  (with transistors Q 4  and Q 5  and parasitic diodes D 6  and D 7  corresponding generally to transistors Q 6  and Q 7  and parasitic diodes D 4  and D 5 , respectively). 
         [0021]    In operation, instead of being switched “on” and “off,” transistors Q 7  and Q 5  are biased with a generally constant voltage (preferably about 3.3V) from bias node N 1 , regardless of channel conditions (enable or disable). The middle point (about 3.3V) of pin voltage (about 6.5V) is chosen to be this generally constant voltage. When either is enabled (enable signals EN 1  and/or EN 2  are logic high), the voltages at the node N 2  and/or N 3  relative to ground is about 3.3V minus the gate-source voltage drop across transistors Q 7  and/or Q 5 . When the channel is disabled (enable signals EN 1  and/or EN 2  are logic low), the voltage at the node N 2  and/or N 3  relative to ground is about 3.3V plus/minus the voltage drop across one diode (D 4 /D 5  and/or D 6 /D 7 ). If pin  108  and/or  110  is faulted to ground, transistors Q 6  and Q 7  and/or Q 4  and Q 5  prevent current from flowing from nodes N 2  and/or N 3  to pins  108  and/or  110 . 
         [0022]    Proper regulation of the voltage on bias node N 1  is also important. Regulation of the voltage at node N 1  is accomplished through the use of regulator  212 , inverter  204 , back-to-back switch  206 , transistor Q 10 , and resistor R 3 . During startup the voltage at bias node N 1  is provided by voltage divider (resistors R 4  and R 5  which are coupled in series with one another between voltage rail  102  and ground) through transistors Q 8  and Q 9  (which are preferably PMOS transistors with parasitic diodes D 8  and D 9 , respectively, between their respective drains and bodies). Once regulator  212  has stabilized to a desired voltage (preferably about 3.3V), signal nPUC transitions to logic high, turning off transistors Q 8  and Q 9  and turning on transistor Q 10  (which is preferably a PMOS transistor) via inverter  204 . Once activated, the bias voltage at node N 1  is provided through resistor R 3  and transistor Q 10 . 
         [0023]    By implementing stage  200 , there are several advantages. For example, by using 26V Drain Extended MOS (DEMOS) transistors with stage  100 , a layout would have and area of about 432,361 μm 2 , but by using stage  200 , the layout would have an area of about 159,716 μm 2 , which is a savings of about 63%. Additionally, for example, because of the clamp  202 , lower voltages can be tolerated, allowing lower voltages at pins  108  and/or  110 , while achieving better output current accuracy. For the same previous example, by using 26V DEMOS transistors with stage  100 , minimum voltage at pins  108  and/or  110  is 1.1V with 20% accuracy. But by using stage  200 , it was made possible to lower minimum voltage at pins  108  and/or  110  to 0.5V while achieving 10% accuracy. 
         [0024]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.