Abstract:
In a method for reducing electromagnetic interference in a clocked circuit, the clock circuit includes at least a first clock signal and a second clock signal. The method detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal. The second clock signal is delayed by a predetermined amount of time when the first transition is substantially aligned with the second transition.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to digital circuits and, more specifically, to a circuit that controls multiple clocking signals to reduce electromagnetic interference. 
     2. Description of the Prior Art 
     The peripheral component interconnect (PCI) standard specifies a computer bus for attaching peripheral devices to a computer motherboard. These devices can take the form of integrated circuits fitted onto the motherboard itself (called planar devices in the PCI specification) or expansion cards that fit in sockets. The PCI bus is common in modern PCs, but it also appears in many other computer types. The PCI specification covers the physical size of the bus (including wire spacing), electrical characteristics, bus timing, and protocols. 
     Most digital circuits employ some sort of clocking circuit to generate a series of clock pulses that activate latches throughout the circuit. When a clock pulse is asserted, a latch is enabled to acquire and store a data value from a logic unit. By asserting clock pulses periodically, data values are able to propagate through the circuit in an orderly manner, thereby ensuring that any given data unit is correctly paired with a corresponding data unit at the beginning of a logical operation. 
     More complex digital circuits often employ several different clocks, sometimes operating at different frequencies. Also, in some circuits many latches may need to be activated simultaneously, but a single clock circuit may lack sufficient power to drive all of the latches. Therefore, it is common to regenerate clock signals through the use of a “clock tree.” Essentially, a clock tree includes a plurality of drivers that receive a clock signal and replicate it with power restored to the original level, to several different clock signal lines. 
     Some clock signals are received by circuits that employ phase locked loops (PLLs) that sense when a given clock pulse is slightly out of phase with sequential pulses in a clock signal and correct a pulse when such an out of phase relationship is detected. Thus, a slight delay in a received clock pulse will not interfere with the normal timing of operations in a synchronous circuit. 
     Each clock signal generates some electromagnetic radiation when being asserted. Typically, this electromagnetic radiation is insignificant in simple circuits, but in more complex circuits it is referred to as electromagnetic interference (EMI). When several different clock signals are asserted coherently, the combined EMI from the clock signals can be enough to interfere with the normal operation of the circuit. This problem may be especially critical in high density circuits, such as those employed in PCI applications. 
     In a representative timing diagram  10  of a prior art system, shown in  FIG. 1 , (showing only relative amounts and not corresponding to any actual units of measurement) a first clock signal  12 , a second clock signal  14  and a third clock signal  16  each include a plurality of periodic transitions, such a rising edges and falling edges. An indication of EMI level  20  demonstrates that when transitions of two of the clock signals are substantially aligned, then the EMI level  20  increases and when transitions of all three clock signals are aligned, then the EMI level  20  is at its maximum. 
     Multiple clock signals in a complex circuit can generate EMI spikes that can have a severe disruptive effect on various parts of the circuit. Because the EMI effect occurs in a transient manner (only when several signals are in alignment), the effect of the EMI spikes can be particularly hard to debug. 
     EMI is not only a concern for interoperability but it is also limited by regulatory agencies. For example, FCC regulations limit the amount of EMI that may be given off by a machine. Also, CISPR country requirements limit EMI in order to ship machines to member countries. While a machine might be perfectly operable, it cannot be sold if its EMI level exceeds regulatory limits. 
     Therefore, there is a need for a system that reduces electromagnetic interference in a circuit due to coherent clock pulses from different clock signals. 
     SUMMARY OF THE INVENTION 
     The disadvantages of the prior art are overcome by the present invention which, in one aspect, is a method for reducing electromagnetic interference in a clocked circuit, including at least a first clock signal and a second clock signal. The method detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal. The second clock signal is delayed by a predetermined amount of time when the first transition is substantially aligned with the second transition. 
     In another aspect, the invention is a method of reducing electromagnetic interference in a circuit between a first clock signal and a second clock signal, in which a selected one of the first clock signal and the second clock signal is delayed when the first clock signal exhibits a first transition that is substantially aligned with a second transition exhibited by the second clock signal. The selected one of the first clock signal and the second clock signal is allowed to propagate normally when the first transition is not substantially aligned with the second transition. 
     In yet another aspect, the invention is a clock management circuit, for managing at least a first clock signal and a second clock signal. A first detector detects a first transition of the first clock signal. A second detector detects a second transition of the second clock signal. A first comparison circuit compares the first transition to the second transition and asserts a delay second signal when the first transition is in substantial alignment with the second transition. A first delay circuit delays the second clock signal when the first delay signal is asserted. 
     These and other aspects of the invention will become apparent from the following description of the preferred embodiments taken in conjunction with the following drawings. As would be obvious to one skilled in the art, many variations and modifications of the invention may be effected without departing from the spirit and scope of the novel concepts of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES OF THE DRAWINGS 
         FIG. 1  is a timing diagram corresponding to a prior art system. 
         FIG. 2  is a timing diagram corresponding to one illustrative embodiment of the invention. 
         FIG. 3  is a block diagram of a device that may be used evaluate clock signal slope and modify clock signal timing in response thereto. 
         FIG. 4  is a frequency diagram showing a frequency spectrum comparison of EMI resulting from a circuit employing a representative embodiment of the invention to EMI resulting from a circuit not employing the invention. 
         FIG. 5  is a first embodiment of a delay stage that may be employed with the invention. 
         FIG. 6  is a second embodiment of a delay stage that may be employed with the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A preferred embodiment of the invention is now described in detail. Referring to the drawings, like numbers indicate like parts throughout the views. As used in the description herein and throughout the claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise: the meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” 
     Emissions from coherently driven clocks can be reduced if the rising edges of the clocks do not occur in phase. One embodiment of the invention detects simultaneous transitions between a plurality of clock signals. When a simultaneous transition occurs, one of the clock signals is delayed, thereby inhibiting simultaneous transitions. For example, as shown in the diagram  100  of  FIG. 2 , in a representative three clock signal system, when the first clock signal  112 , the second clock signal  114  and the third clock signal  116  are manipulated to prevent simultaneous transitions, the maximum EMI level  120  output by the clocks is reduced. 
     In one embodiment, an EMI prevention system detects when a first transition of the first clock signal is substantially aligned with a corresponding second transition of the second clock signal (which may be done by comparing the slope and the direction of the first transition to the slope and direction of the second transition). If the first transition is substantially aligned with the second transition, then the system delays the second clock signal by a predetermined amount of time. 
     In one physical embodiment, as shown in  FIG. 3 , the detection and delay can be accomplished on a clocking system that regenerates a clock signal from a base clocking circuit  130  through a first direct digital synthesizer (DDS)  132  that generates a first output  160 , a second DDS  134  that generates a second output  162  and a third DDS  136  that generates a third output  164 . The output of the first DDS  132  is compared to the output of the second DDS  134  with a first slope and direction detect and compare (SDDC) circuit  140 . The SDDC could, for example, include a phase detector. A first selective delay circuit  150  allows the output of the second DDS  134  to propagate directly to the second output  162  if the first SDDC circuit  140  indicates that the two signals do not have simultaneous transitions. Otherwise, first selective delay circuit  150  delays the output by a predetermined amount of time prior to propagating to the second output  162 . Similarly, the output of the first DDS  132  is compared to the output of the third DDS  136  with a second SDDC  142  and a second selective delay circuit  152  delays the output of the third DDS  136  if the second SDDC  142  detects a simultaneous transition. Otherwise the output is allowed to propagate past the second selective delay circuit  152  without delay. Once through the second selective delay circuit  152  the output of the third DDS  136  is compared to the output of the second DDS  134  (after it has passed through the first s elective delay circuit  150 ) with a third SDDC  144 . If there are no simultaneous transitions at this stage, a third selective delay circuit  154  allows the signal to pass directly to the third output  164 , otherwise it is delayed by a predetermined amount of time and then allowed to propagate. In this embodiment, the signal from the third DDS  136  has a lower frequency than the signal from both the first DDS  132  and the second DDS  134 . Similarly, the signal from the second DDS  134  has a lower frequency than the signal from the first DDS  132 . 
     If these clock signals are used in an asynchronous system, then the slight added delay will be of little or no consequence. However, in a synchronous system, the clock signals can be re-synchronized (e.g., through use of a phase locked loop) once they are received by their respective outputs. 
     In one representative prototype, a system according to the invention included a main clock chip used to derive several sub clocks coherently. Before the clocks were output, the system ensured that the phase of the clocks (i.e., rise time versus rise time) did not occur simultaneously. In one example, as applied to peripheral component interconnect (PCI) clocks, a 133 MHz clock was run and redriven to three sets of slots because the drivers could not handle the fan out required for all the slots. The output frequencies were close to each other (about 120 kHz apart) and yet were still within specifications while ensuring that the clock phases did not occur at the same time. This was done by delaying the clock pulses within the system. Driven to phase locked loops the driven PCI cards synchronized themselves up to the main clock and handled any single delay in the pulse train. 
     While redriving is important, clock redriver chips can include multiplication and division. In many such applications, these redriven clocks need not be driven in-phase and thus EMI can be reduced by delaying the clocks with respect to each other. 
     The system uses a typical DDS (direct digital synthesizer) block but determines the exact slope and direction of the signal rise and fall. If the rise (or fall) of one signal was set to occur with the rise (or fall) of another signal, the slower clock of the two is delayed. The slower clock typically should be delayed since it represents a smaller percentage change of the overall period of the slower clock and thus introduces less error. 
     The overall system handles the delays that occur in the time domain to reduce EMI in the frequency domain. By preventing simultaneous transitions of the clock signals, the EMI of the system may have more frequency component spikes, but the intensity of those spikes is reduced. As shown in  FIG. 4 , a frequency component graph  182  of EMI from a circuit employing the invention would have smaller frequency component peaks than a comparable chart  180  for prior art circuits. While frequency component graph  182  does exhibit more low-level frequency component peaks (e.g., item  184 ), these low-level peaks are not likely to interfere with other circuits because of their low intensity. However, the reduction in intensity of the maximum peaks (e.g., item  186 ) results in fewer harmful EMI effects to other circuits. 
     A first embodiment of a selective delay circuit  210  is shown in  FIG. 5 . In this embodiment, the outputs of the first DDS  132  and the second DDS  134  are both fed into an SDDC  140 , which controls a switch  212 . The switch  212  can selectively connect the output of the second DDS  134  either directly to output  162  or force it to pass through a delay line  214 . In a second embodiment of a selective delay circuit  220 , as shown in  FIG. 6 , a delay gate  224  (such as a driver or other solid-state circuit) may be used as a delay element. 
     While the above embodiments show only three clock signals for the sake of simplicity, the process may be expanded to a multitude of driven clock signals. The output of each DDS module is compared to the following (slower) modules to check slopes and directions. If they are the same, then the slower clock is delayed. That signal is then passed onto the next comparison block, and so on. If the slopes and directions are not equal then the signal is not delayed but is passed onto the next block or output. One alternate embodiment brings the slope/direction detect and compare signal back to the DDS module and in effect adds a number to the internal phase accumulator which will change the phase starting point of the clock signal. 
     The above described embodiments, while including the preferred embodiment and the best mode of the invention known to the inventor at the time of filing, are given as illustrative examples only. It will be readily appreciated that many deviations may be made from the specific embodiments disclosed in this specification without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be determined by the claims below rather than being limited to the specifically described embodiments above.