Abstract:
A diode implemented in a junction isolated process protected from minority carrier substrate injection is disclosed. In a preferred embodiment, a diode includes an N+ cathode region and a P+ anode region formed in a P epitaxial region, and an N+ isolation region enclosing the epitaxial region. A CMOS inverter connected to the cathode region shorts the isolation region to either the cathode or the grounded substrate, depending on the voltage at the cathode, and thereby prevents minority carrier injection into the substrate in all conditions.

Description:
FIELD OF THE INVENTION 
     This invention relates to a PN junction diode formed on a semiconductor substrate, and in particular to a floating PN junction diode which is implemented in a junction-isolated process and protected against minority carrier injection into the substrate. 
     BACKGROUND OF THE INVENTION 
     In integrated circuit technology, it is known to form devices in a semiconductor substrate or epitaxial layer because those formed on polysilicon films have poor characteristics. When a PN junction is formed directly in the substrate material it shares one terminal with other devices (generally referred to as ground) and cannot have both anode and cathode connected to arbitrary voltages. It is also known to form an &#34;isolation region&#34; around an integrated circuit device, in order to isolate the device electrically from other devices in the same substrate. The isolation region consists essentially of a &#34;tub&#34; shaped region of opposite conductivity to the substrate. Such a structure is shown in U.S. Pat. No. 5,156,989 to Williams et al. (see FIG. 10). When a diode is enclosed within an isolation region, depending on the voltage applied to the anode and cathode, a junction between the isolation region and the substrate may become forward-biased. This may cause minority carriers to be injected into the substrate, resulting in latch-up, excessive heating and other undesirable effects. It may also have parasitic bipolar transistors with high current gain, leading to large substrate current. In this sense, prior art diodes formed in a substrate cannot freely float. 
     SUMMARY OF THE INVENTION 
     Accordingly, one object of the present invention is to provide a PN junction diode implemented in a junction isolation process and protected from minority carrier injection into the substrate regardless of the voltages applied to the terminals of the diode. 
     Another object of the present invention is to provide a diode which is capable of forward or reverse operation at voltages above or below a grounded P-type substrate without the use of oxide or dielectric isolation. 
     In accordance with this invention, a diode formed in a semiconductor substrate includes an anode region and a cathode region, and an isolation region enclosing the anode and cathode. The isolation region has a conductivity opposite to that of the substrate. A first switching device connects the isolation region to the cathode region when the voltage at the cathode exceeds a first predetermined level; and a second switching device connects the isolation region to the substrate when the voltage at the cathode falls below a second predetermined level. 
     In the preferred embodiment, the first and second switching devices take the form of a CMOS inverter, with the cathode of the diode being connected to the gate of each device. For a P-type substrate, the switching device linking the cathode with the isolation region is an N-channel MOS transistor and the device linking the isolation region with the substrate is a P-channel MOS transistor. 
     In an alternative embodiment, the switch which connects the isolation region to the substrate is constructed in the form of a high-voltage lateral DMOS device. In a second alternative embodiment, the entire diode is structured to handle high voltages. 
     The above and other objects, features and advantages of this invention will be apparent from the following detailed description of the invention in conjunction with the drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a cross-sectional view of a floating/ode in accordance with the present invention. 
     FIG. 2 illustrates an equivalent circuit diagram of the diode device shown in FIG. 1. 
     FIG. 3A illustrates the operation of the diode when it is reverse-biased and when its anode and cathode are above ground; FIG. 3B illustrates an equivalent circuit diagram of the diode in the situation shown in FIG. 3A. 
     FIG. 4 illustrates the operation of the diode when it is forward-biased and when its anode and cathode are above ground; FIG. 4B illustrates an equivalent circuit diagram of the diode in the situation shown in FIG. 4A. 
     FIG. 5A illustrates the operation of the diode when it is reverse-biased and when its anode and cathode are below ground; FIG. 5B illustrates an equivalent circuit diagram of the diode in the situation shown in FIG. 5A. 
     FIG. 6A illustrates the operation of the diode when it is forward-biased and when its anode and cathode are below ground; FIG. 6B illustrates an equivalent circuit diagram of the diode in the situation shown in FIG. 6A. 
     FIG. 7 illustrates a modification to the diode device wherein the PMOS transistor is in the form of a high voltage lateral DMOS device. 
     FIG. 8 illustrates another embodiment of the present invention wherein the entire diode device is made capable of handling high voltages. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a cross-sectional view of a diode 10 constructed in accordance with the present invention. Diode 10 includes a P+ anode 11 and an N+ cathode 12, both of which are formed in an enclosed region 13P of a P epitaxial (epi) region 13, overlying a P substrate 14. Anode 11 and cathode 12 may also be formed in a P-body region which is in turn formed in a P epitaxial region. Enclosed region 13P is surrounded by an N+ isolation region 15. Isolation region 15 includes a buried layer 15A and a wraparound region 15B, which together form a &#34;tub&#34; around enclosed region 13P. An inner junction 15I separates enclosed region 13P from isolation region 15, and an outer junction 15X separates P substrate 14 from isolation region 15. Isolation region 15 is preferably formed in the manner described in U.S. Pat. No. 5,156,989 to Williams et al., which is incorporated herein by reference in its entirety. 
     An N-channel MOS transistor 16 is formed in enclosed region 13P, including cathode 12, an N+ region 32 and a gate 18. A P-channel MOS transistor 19 is formed in an N-well 13N, which is also formed in P epi region 13 and is isolated from P epi region 13 by an N+ isolation region 20. P-channel transistor 19 includes a P+ region 21, a P+ region 22, and a gate 23. The insulation layers separating gates 18 and 23 from enclosed region 13P and N-well 13N, respectively, are made thick enough to withstand significant positive or negative gate voltages. 
     As further shown in FIG. 1, anode 11 contacts an electrode 24, and cathode 12 and gate 18 contact a common electrode 25. A P+ region 26 outside isolation regions 15 and 20 forms a connection between P substrate 14 and an electrode 27, which is also connected to P+ region 22. An electrode 28 links P+ region 21 to isolation region 15 via an N+ region 29. An electrode 30 contacts gate 23 and is coupled to electrode 25 by a conductive interconnection 31. The N+ isolation regions 15 and 20 are in the shape of a &#34;figure 8&#34; to isolate enclosed regions 13P and N-well 13N from each other and from the substrate. Optionally, NMOS transistor 16 may be annular, surrounding anode 11. Likewise PMOS transistor 19 may be annular, centered on P+ region 22. 
     FIG. 2 illustrates an equivalent circuit diagram of diode 10. As shown, anode 11, cathode 12 and isolation region 15 form a parasitic NPN transistor 32. The gain of parasitic transistor 32 may be minimized by the doping of P epi region 13, by the formation of a P-body region around the cathode 12, or by the formation of a P-type buried layer above the N-type buried layer. Substrate 14 is grounded (that is, referenced to a potential which is arbitrarily referred to as 0 volts and to which other components may be referenced), a voltage V A  is applied to anode 11, and a voltage V K  is applied to cathode 12. 
     The operation of diode 10 in the following situations will now be described: 
     1. V A  and V K  are above ground and diode 10 is reverse-biased (V K  &gt;V A  &gt;0). 
     2. V A  and V K  are above ground and diode 10 is forward-biased (V A  &gt;V K  &gt;0). 
     3. V A  and V K  are below ground and diode 10 is reverse-biased (V A  &lt;V K  &lt;0). 
     4. V A  and V K  are below ground and diode 10 is forward-biased (V K  &lt;V A  &lt;0). 
     In the first situation (V K  &gt;V A  &gt;0), illustrated in FIGS. 3A and 3B, the junction between cathode 12 and enclosed region 13P is reverse-biased and diode 10 therefore blocks the flow of current. However, voltage V K  is also applied to gate 18 of N-channel transistor 16 and gate 23 of P-channel transistor 19. Since V K  is positive, N-channel transistor 16 shorts isolation region 15 to cathode 12, and P-channel transistor 19 is turned off. Isolation region 15 is therefore at a voltage which is very close to V K , and the outer junction 15X between isolation region 15 and P substrate 14 is reverse-biased. Thus, with outer junction 15X reverse-biased, no minority carrier injection into P substrate 14 occurs. FIG. 3A is a schematic diagram of this situation, with diode 33 representing the reverse-biased junction 15X. As seen from the equivalent circuit of FIG. 3B, the emitter-base and collector-base junctions of the parasitic transistor 32 are reverse-biased, and the emitter and collector are shorted by N-channel transistor 16. Reverse-biased diode 33 is connected between the collector and ground. 
     In the second situation, illustrated in FIGS. 4.A and 4B, diode 10 is forward-biased, and the anode and cathode potentials are above ground (V A  &gt;V K  &gt;0). Diode 10 therefore conducts and V K  =V A  -0.7 V, where 0.7 V represents the forward voltage drop of the junction between cathode 12 and enclosed region 13P. Again, V K  is applied to gate 18 of N-channel transistor 16, turning it on and shorting isolation region 15 to cathode 12. Isolation region 15 therefore has a voltage of about V A  -0.7 V. P-channel transistor 19 is turned off. Junction 15X between isolation region 15 and P substrate 14, i.e., diode 33 in FIGS. 4A and 4B, is therefore reverse-biased. With outer junction 15X reverse-biased, no minority carriers are injected into P substrate 14. Most of the current flows from anode 11 to cathode 12 because of the higher resistance of the path through isolation region 15 and N-channel transistor 16. 
     The equivalent circuit is shown in FIG. 4B. The emitter-base junction of parasitic transistor 32 is forward-biased, and the emitter and collector are shorted. 
     In the third situation, illustrated in FIGS. 5A and 5B, diode 10 is reverse-biased, and the cathode and anode potentials are below ground (V A  &lt;V K  &lt;0). Diode 10 is therefore nonconductive. The negative cathode voltage V K  is applied to gate 23 of P-channel transistor 19, turning it on and shorting P+ region 22 to isolation region 15. Thus isolation region 15 is tied to grounded substrate 14 via electrode 27 and P+ region 26. Inner junction 15I between enclosed region 13P and isolation region 15 is reverse-biased. Because V K  is negative, N-channel transistor 16 is turned off. 
     The equivalent circuit is shown in FIG. 5B. The emitter-base and collector-base junctions of parasitic transistor 32 are reverse-biased, and the collector and ground are shorted around diode 33. Again, since junction 15I is reverse-biased and junction 15X is zero biased, no minority carrier injection into P substrate 14 occurs. 
     In the fourth and final situation, illustrated in FIGS. 6A and 6B, diode 10 is forward-biased and the cathode and anode potentials are below ground (V K  &lt;V A  0). The junction between cathode 12 and enclosed region 13P is forward-biased. P-channel transistor 19 is turned on and shorts isolation region 15 to the grounded substrate 14. Inner junction 15I between enclosed region 13P and isolation region 15 is reverse-biased. Referring to FIG. 6B, the parasitic transistor 32 is in its forward conduction mode, with its emitter-base junction forward biased and its collector-base junction reverse-biased. The current flowing through parasitic transistor 32 may be limited by the high impedance of N-channel transistor 16. If the current gain (β) of parasitic transistor 32 is low, this unwanted current can be neglected. Otherwise, the aforementioned current limiting technique or additional series resistance is required. Regardless of the current in diode 10 and in N-channel transistor 16, junction 15X is zero-biased. 
     Thus, in all four situations an essential condition is preserved, namely, that no PN junction is ever forward-biased onto the substrate. This unique result is achieved by using switching transistors 16 and 19, which together constitute a CMOS inverter, to bias the isolation region 15 correctly. Minority carrier injection into the substrate is avoided. Since the voltages of the cathode and anode are essentially equal when the diode is forward biased, they will both be either above or below ground. When the cathode is below ground and the diode is reverse-biased, the anode must also be below ground, since it must be more negative than the cathode. The only case where the anode and cathode have voltages on opposite sides of zero is when V K  &gt;0&gt;V A . This case is identical to the operation shown in FIGS. 3A and 3B. 
     The diode of this invention is useful in protecting a load from a reversed voltage condition, particularly the integrated circuit devices in a motor vehicle from a reverse-connected battery. This application of the invention is disclosed in U.S. application Ser. No. 08/067,373, which is assigned to the assignee of the present application and which is incorporated herein by reference. 
     FIG. 7 illustrates another embodiment of the diode of this invention, where a modified P-channel device 70 is a lateral double diffused MOS (DMOS) device which has a higher breakdown voltage and does not require special processing steps to achieve higher breakdown. An N-well 71, formed next to an N+ isolation region 72, has a junction with enclosed region 13P. A gate 73 is positioned over the channel region between P+ region 21 and P epi region 13. P epi region 13 is connected to substrate 14. 
     FIG. 8 illustrates another embodiment of the diode in accordance with the present invention. An annular lightly doped drift region 80 is formed on the inside of a cathode 81 of the diode, which surrounds a central anode 85. A second annular lightly doped drift region 82 is formed next to an isolation region 83. An N-well 84 is formed outside of isolation region 83. Isolation region 83 includes a buried layer 83B, an annular up isolation region 83U, and an annular down isolation region 83D, as described in FIGS. 25A-25P of U.S. Pat. No. 5,156,989 to Williams et al. This structure is capable of handling high voltages because of the lightly doped drift regions. 
     The foregoing embodiments are intended to be illustrative and not limiting. Many additional embodiments in accordance with this invention will be apparent to those skilled in the art. All such additional embodiments are intended to be within the broad principles of this invention, as defined in the following claims.