Abstract:
An inrush current control circuit having an input terminal connected to a DC power supply and an output terminal connected to a load capacitor limits the inrush current that charges up the load capacitor during power up of a system. When the DC power supply applies a DC voltage to the input terminal, the inrush current control circuit produces a voltage ramp at the load capacitor instead of an abrupt DC voltage. The voltage ramp results in a constant low level current to charge up the load capacitor, greatly reducing the current drain on the DC power supply.

Description:
ORIGIN OF THE INVENTION 
     The invention described herein was made in performance for work under NASA contract, and is subject to the provisions of Public Law 96-517 (35 U.S.C. § 202) in which the Contractor has elected not to retain title. 
    
    
     TECHNICAL FIELD 
     The present invention generally relates to inrush current protection circuits and more particularly, pertains to an inrush current control circuit for limiting the inrush current from a DC voltage supply to a load capacitor. 
     BACKGROUND ART 
     Many flight instruments and military equipment commonly employ capacitors on a power buss to filter out current spikes and noise that would otherwise be impressed on the power buss. During power-up, these capacitors initially require large amounts of current to charge up, resulting in a large inrush current drain on the power buss. This can cause disruption of other instruments and equipment connected to the power buss. 
     For example, aircraft that distribute DC power from a generator to on-board systems protect the generator from excessive current loading with a circuit breaker. During power-up of an on-board system, capacitors in the on-board system draw large amounts of current to charge up. If the capacitors of the on-board system attempt to draw more current from the generator than that allowed by the circuit breaker, then the circuit breaker will activate and terminate DC power to all the on-board systems connected to the generator. 
     Also, spacecraft in earth orbit use solar cells to provide power to internal systems. The amount of current provided by the solar cells is limited by the amount of light falling on the cells. If the capacitors of an internal system attempt to draw more current from the solar cells than they can supply, then the output voltage of the solar cells will drop sharply. The sharp drop in the output voltage can cause disruption of other systems drawing power from the solar cells. 
     Therefore, there is a need to protect against large current drains on a power source during system power-up and the disruption of other systems connected to the power source. Specifically, a protection circuit is needed between the power source and each system with a capacitive load drawing power from the power source to limit the inrush current during system power-up. 
     STATEMENT OF THE INVENTION 
     The inrush current control circuit of the present invention addresses the above problem by limiting the inrush current drawn from a DC power source during system power-up. An input terminal of the inrush current control circuit is connected to a DC power supply and an output terminal is connected to the load capacitor of a system. When the DC power supply applies a DC voltage to the input terminal, the inrush current control circuit of the present invention produces a voltage ramp at the load capacitor instead of an abrupt DC voltage. The voltage ramp results in a constant low level current to charge up the load capacitor compared to an abrupt DC voltage which can result in a high level current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The exact nature of this invention will be readily apparent from consideration of the following detailed description in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a schematic diagram of the inrush current control circuit of the present invention. 
     FIGS. 2 a ,  2   b ,  2   c , and  2   d  are graphs showing four potentials of the inrush current control circuit versus time when a DC voltage is applied to the input terminal. 
     FIG. 3 is a block diagram of a power distribution network utilizing the inrush current control circuit of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor of carrying out his invention. 
     The inrush current control circuit of the preferred embodiment of the invention is shown in FIG.  1 . The inrush current control circuit includes an input terminal A connected to a DC voltage power supply (not shown) and an output terminal D connected to a load capacitor (not shown). A P-type field effect transistor (PFET) Q 2  connected between the positive lead of the input terminal A and output terminal D limits the current flow between the input and output terminal. A gate control circuit  12  connected between a gate terminal G of PFET Q 2  and the positive lead of the output terminal D controls the gate G potential of PFET Q 2 . The gate control circuit  12  consist of a capacitor C 2  and a resistor R 5  connected in series. A voltage divider  14  connected between the positive and negative lead of the input terminal A and to the gate G of the PFET Q 2  sets the steady state gate G potential of PFET Q 2 . The voltage divider  14  consist of two resistors R 3  and R 4  connected in series. A charging circuit  16  connected between the positive and negative lead of the input terminal A and to the gate G of PFET Q 2  charges up capacitor C 2  when a DC voltage is applied to the input terminal A. The charging circuit  16  includes a transistor Q 1  and a resistor-capacitor (RC) circuit consisting of two resistors R 1  and R 2  and a capacitor C 1 . The resistor R 1  is coupled between the positive lead and a junction formed by the union of one side of the capacitor C 1  and one side of the resistor R 2 . The second side of the capacitor C 1  is coupled to the negative lead while the second side of the resistor R 2  is coupled to the base terminal of the transistor Q 1 . 
     The operation of the inrush current control circuit will now be described. FIGS. 2 a ,  2   b ,  2   c  and  2   d  shows four potentials of the inrush current control circuit versus time when a DC voltage is applied to the input terminal A. FIG. 2 a  shows the input terminal A potential, FIG. 2 b  shows a base terminal B potential of transistor Q 1 , FIG. 2 c  shows the gate G potential of PFET Q 2 , and FIG. 2 d  shows the output terminal D potential. All potentials are with respect to ground. It is assumed that all capacitors are initially discharged. When an input DC voltage Vin is applied to the input terminal A at time t 1 , the input terminal A potential abruptly rises to Vin and transistor Q 1  turns on, providing a conduction path between the positive lead of the input terminal A and capacitor C 2  to quickly charge up capacitor C 2 . As capacitor C 2  charges up, the gate G potential of PFET Q 2  quickly rises to a level close to Vin turning PFET Q 2  off. At time t 2 , capacitor C 1  has charged up, raising the base B potential to a level close to Vin. This causes transistor Q 1  to turn off, allowing capacitor C 2  to slowly discharge. As capacitor C 2  discharges, the gate potential of PFET Q 2  drops. At time t 3 , the gate to source turn-on potential of PFET Q 2  is reached and current begins to flow through PFET Q 2 . At this point, the output terminal potential D begins to rise in a linear ramp. Between times t 3  and t 4 , the gate G potential of PFET Q 2  remains almost constant as capacitor C 2  continues to discharge and the output D potential rises in a linear ramp. The rate of voltage rise at the output D is limited by the discharge rate of capacitor C 2  through R 4 , R 5  and the load resistance (typically very small). The inrush current is limited by the rate of rise of the voltage at the output D and the value of the load capacitance. The value of the inrush current, I, during this period can be determined by the formula: 
     
       
         I=C dV/dT 
       
     
     where C is the load capacitance and dV is the change in voltage at the output D in volts per second (dT). At time t 4 , the voltage ramp reaches the input potential minus the voltage drop across the PFET Q 2 . This potential is the full-on potential. After the full-on potential is reached, capacitor C 2  continues to discharge until the gate G potential drops to a steady state level determined by the voltage divider  14  formed by R 3  and R 4 . The primary function of R 5  is to suppress oscillations in PFET Q 2 . 
     Component values and part numbers for an inrush current control circuit according to the present invention are as follows: 
     
       
         
               
               
             
               
               
               
               
               
               
               
             
               
               
             
               
               
               
               
               
             
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
             
             
               
                   
                 Resistor Values 
               
             
          
           
               
                   
                 R1: 
                 47 KΩ 
                 R2: 
                  33 KΩ 
                 R3: 
                 47 KΩ 
               
               
                   
                 R4: 
                 33 KΩ 
                 R5: 
                 470 Ω 
               
             
          
           
               
                   
                 Capacitor Values 
               
             
          
           
               
                   
                 C1: 
                 0.1 μf 
                 C2: 
                 0.1 μf 
               
             
          
           
               
                   
                 Part Numbers 
               
             
          
           
               
                   
                 Q1: 
                 2N3251A 
                 Q2: 
                 IRFP9130 
               
               
                   
                   
               
             
          
         
       
     
     The above inrush current control circuit is connected to a DC voltage supply of 24V and charges a load capacitance of a few hundred thousand microfarads in a ramp time of a few tens of microseconds. 
     The inrush current control circuit can be used in a power distribution system having various systems connected to a common power source, such as on-board aircraft systems connected to a common generator. In this case, each system requiring inrush current protection is connected to the common power source through its own inrush current control circuit. FIG. 3 shows an example of a power distribution network  20  having two systems  24 ,  26  connected to a common power source  22 . Each system is connected to the common power source  22  through a switch  28 ,  30  and an inrush current control circuit  32 ,  34  according to the present invention. The system  24 ,  26  is turned on by closing the switch  28 ,  30  connecting the system to the common power source  22 . 
     Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiment of the invention can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.