Abstract:
A digital-to-analogue converting circuit includes a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements is a variable resistor, and a code level changing unit for outputting a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code is produced by converting a level of the digital code.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2007-89893, filed on Sep. 5, 2007, in the Korean Patent Office, the contents of which are incorporated by reference in their entirety as if set forth in full. 
       BACKGROUND 
       [0002]    I. Technical Field 
         [0003]    The embodiments described herein relate to semiconductor design technology and, more particularly, to a digital-to-analog converter and an apparatus for on-die termination using the same. 
         [0004]    II. Related Art 
         [0005]    A conventional digital-to-analog converter can be classified into two types, a first type which converts PCODE (a kind of digital code) into an analog voltage signal and a second type which converts two kinds of digital codes PCODE and NCODE into an analog voltage signal. 
         [0006]    As shown in  FIG. 1 , the first type of digital-to-analog converter includes a plurality of circuit sets, each of which has a NAND gate (ND 10 ), and a driver leg  10  to be connected to external resistor (ZQ). When an enable signal “EN” is activated to a high level, a digital code PCODE&lt;i&gt; (i=0 to N) is input to a gate of the transistor (M 10 ) in the driver leg  10 . When the digital code PCODE&lt;i&gt; is activated to a low level, the corresponding driver leg  10  is selected. 
         [0007]    An analog voltage signal “Vpcode” is output by dividing a power supply voltage (VDDQ) in proportion to the voltage division ratio which is conducted by resistance elements consisting of the resistor (R 10 ) and the fully turned-on transistor (M 10 ) in the driver leg  10  and the external resistor (ZQ). 
         [0008]    As shown in  FIG. 2 , the second type of digital-to-analog converter includes a plurality of circuit sets, each of which has a NAND gate (ND 20 ) and a driver leg  20 . 
         [0009]    When an enable signal “EN” is activated to a high level, the digital code PCODE&lt;i&gt; is input to a gate of the transistor (M 20 ) in the driver leg  20 . The digital code NCODE&lt;i&gt; is input to a gate of the transistor (M 21 ) in the driver leg  20  regardless of the enable signal “EN.” 
         [0010]    When the digital codes PCODE&lt;i&gt; and NCODE&lt;i&gt; are respectively activated to low and high levels, an analogue voltage signal (Vpcode) is output by dividing a power supply voltage (VDDQ) in a proportion to the voltage division ratio which is conducted by resistance elements consisting of resistors (R 20 ) and (R 21 ) and the fully turned-on transistors (M 20 ) and (M 21 ) in the driver leg  10 . 
         [0011]    In an on-die termination apparatus, the configuration shown in  FIG. 2  can be used for calibrating another digital code NCODE based on the calibrated digital code PCODE of the calibration that is executed in the digital-to-analog converter. 
         [0012]    However, according to the conventional on-die termination apparatus, since digital codes PCODE&lt;i&gt; and NCODE&lt;i&gt; are in a voltage level of the power supply voltage or a ground voltage level, the transistors (M 10 ), (M 20 ) and (M 21 ) in the driver legs  10  and  20  cannot be finely controlled. These transistors are controlled only in full turn-on/off operations. The resistance can be disregarded when transistors (M 10 ), (M 20 ) and (M 21 ) are fully turned on. Accordingly, since the resistance values in driver legs  10  and  20  are determined only by the passive elements (resistors (R 10 ), (R 20 ) and (R 21 )), it is not possible to finely control the resistance values and the resistance values are limited to a narrow adjustment range. Furthermore, since the resistance values in the driver legs  10  and  20  are limited to a narrow adjustment range, the number of driver legs  10  and  20  is increased in order to enlarge the adjustment range of the resistance values and the increased number of the driver legs causes an increase in the chip area of the semiconductor device. 
       SUMMARY 
       [0013]    A digital-to-analogue (D/A) converter and an apparatus for on-die termination, using the same, capable of finely controlling resistance values without increasing of the number of driver legs, and enlarging an adjustment range of the resistance values are disclosed herein. 
         [0014]    According to one aspect, a digital-to-analog converting circuit that can include a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein at least one of the plurality of resistance elements can be a variable resistor; and a code level changing unit that can be configured to output a level-changed code to a control terminal of the variable resistor based on an activation of a digital code, wherein the level-changed code can be produced by converting a level of the digital code is disclosed. 
         [0015]    According to another aspect, a digital-to-analog converting circuit that can include a driver leg having a plurality of resistance elements between a power supply voltage terminal and a ground voltage terminal, wherein two of the plurality of resistance elements can be variable resistors; a first code level changing unit that can be configured to output a first level-changed code of a first variable voltage to a control terminal of one of the two variable resistors based on an activation of a first digital code, wherein the first level-changed code can be produced by converting a level of the first digital code; and a second code level changing unit that can be configured to output a second level-changed code of a second variable voltage to a control terminal of the other of the two variable resistors based on an activation of a second digital code, wherein the second level-changed code can be produced by converting a level of the second digital code is disclosed. 
         [0016]    According to still another aspect, an apparatus for on-die termination can include a D/A converting unit that can be configured to change a resistance value of an internal circuit based on a level changing signal to have a variable voltage level in response to a digital code and output analog voltage by dividing a power supply voltage through the internal circuit; a comparison unit that can be configured to compare a reference voltage with an analog signal output from the D/A converting unit and output a comparison signal; and a counter that can be configured to up- and down-count the digital code based on the comparison signal is disclosed. 
         [0017]    The embodiments described above can enlarge an adjustment range of a resistance value of a driver leg to more than a predetermined range of a conventional digital code but also finely control the resistance value. 
         [0018]    Also, since the adjustment range of the resistance value can be enlarged, an on-die termination apparatus can have various on-die termination resistance values using a small number of driver legs. 
         [0019]    These and other features, aspects, and embodiments are described below in the section entitled “Detailed Description.” 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    Aspects, features and embodiments are described in conjunction with the accompanying drawings, in which: 
           [0021]      FIG. 1  is a circuit diagram illustrating a conventional D/A converter; 
           [0022]      FIG. 2  is a circuit diagram illustrating another conventional D/A converter 
           [0023]      FIG. 3  is a circuit diagram illustrating a D/A converter, in accordance with one embodiment; 
           [0024]      FIG. 4  is a circuit diagram illustrating a code level changing unit of  FIG. 3 , in accordance with one embodiment; 
           [0025]      FIG. 5  is a circuit diagram illustrating a D/A converter, in accordance with one embodiment; 
           [0026]      FIG. 6  is a circuit diagram illustrating a second code level changing unit of  FIG. 5 , in accordance with one embodiment; and 
           [0027]      FIG. 7  is a circuit diagram illustrating an apparatus for on-die termination, in accordance with one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    As shown in  FIG. 3 , a D/A converter can include a plurality of circuit sets, each of which can have a NAND gate (ND 30 ), a code level changing unit  30  and a driver leg  10 ′. 
         [0029]    The NAND gate ND 30  can be configured to transfer a first digital code PCODE&lt;i&gt; in response to an enable signal “EN.” Therefore, other logic devices can be substituted for the NAND gate (ND 30 ) based on the logic level of the enable signal “EN.” 
         [0030]    The driver leg  10 ′ can have the same configuration as that mentioned in  FIG. 1 . However, a transistor (M 10 ′) in the driver leg  10 ′ can be configured to not be fully turned on/off, therefore, differentiating it from the transistors described in  FIG. 1 . That is, the transistor (M 10 ′) in the present invention can be a variable resistor. 
         [0031]    Referring to  FIG. 4 , the code level changing unit  30  can include an inverter (IV 31 ), a first pass gate (PG 31 ) and a second pass gate (PG 32 ). The first pass gate (PG 31 ) can be configured to receive the first digital code PCODE&lt;i&gt;. A first variable voltage (Vbias_P) can be applied to an input terminal of the first pass gate (PG 31 ) and the first digital code PCODE&lt;i&gt; can be applied to a first control terminal of the first pass gate (PG 31 ). An output of the inverter (IV 31 ) can be applied to a second control terminal of the first pass gate (PG 31 ). A power supply voltage (VDDQ) can be applied to an input terminal of the second pass gate (PG 32 ) and the output of the inverter (IV 31 ) can be applied to a first control terminal of the second pass gate (PG 32 ). The first digital code PCODE&lt;i&gt; can be applied to a second control terminal of the second pass gate (PG 32 ). An output terminal of the first pass gate (PG 31 ) can be commonly connected to an output terminal of the second pass gate (PG 32 ). 
         [0032]    The operation of the D/A converter, according one embodiment, will be described in detail below. 
         [0033]    When the enable signal “EN” is inactivated to a low level, a high level signal can be input into the code level changing unit  30  regardless of the logic level of the first digital code PCODE&lt;i&gt;. On the contrary, when the enable signal “EN” is activated to a high level, the first digital code PCODE&lt;i&gt; can be transferred to the code level changing unit  30 . The transferred signal can be one of the first digital code signals “PCODE&lt;0:N&gt;” and the number of the bits of the first digital code PCODE&lt;i&gt; can be determined by the number of the driver legs. 
         [0034]    The code level changing unit  30  of  FIG. 4  can be configured to output the power supply voltage (VDDQ) as a first level-changed code PCODE&lt;i&gt;_T when the first digital code PCODE&lt;i&gt; is activated to a high level. 
         [0035]    The first level-changed code PCODE&lt;i&gt;_T can be input into the transistor (M 10 ′) in the driver leg  10 ′. 
         [0036]    The transistor (M 10 ′) in the driver leg  10 ′ can be fully turned off because the gate voltage level is correspondent to the power supply voltage (VDDQ). That is, the driver leg  10 ′ which receives the inactivated digital code PCODE&lt;i&gt; does not perform the D/A conversion. 
         [0037]    On the other hand, the code level changing unit  30  of  FIG. 4  can be configured to convert the first variable voltage (Vbias_P) into the first level-changed code PCODE&lt;i&gt;_T when the first digital code PCODE&lt;i&gt; is activated to a low level. The first level-changed code PCODE&lt;i&gt;_T can be input into the transistor (M 10 ′) in the driver leg  10 ′. 
         [0038]    The first variable voltage (Vbias_P) can be selectively varied in a range of a turn-on starting voltage level to a full turn-on voltage level of the transistor (M 10 ′), i.e., VDDQ-Vtp (threshold voltage of PMOS) to 0V. The first variable voltage (Vbias_P) can be produced by a voltage generator which can be provided within a D/A converting circuit or from the outside (a semiconductor memory chip having a D/A converting circuit or an individual memory controller to control the semiconductor memory chip). Such a voltage generator can be configured to produce the first variable voltage (Vbias_P) according to a test mode signal or a mode register set signal. 
         [0039]    The resistance value of the transistor (M 10 ′) in the driver leg  10 ′ can be adjusted based on the voltage level of the first variable voltage (Vbias_P). The resistance of the transistor (M 10 ′) can be varied according to the voltage level of the first variable voltage (Vbias_P), being different from the conventional D/A converter in which the resistance of the transistor can be disregarded due to the full turn-on voltage or the full turn-off voltage to have an infinite quantity of resistance. 
         [0040]    The driver leg  10 ′, which can be selected by the first level-changed code PCODE&lt;i&gt;_T, can be configured to output a first analog voltage (Vpcode) by dividing the power supply voltage (VDDQ) based on the proportion of the resistance values of the transistor (M 10 ′) to function as a variable transistor, the resistor (R 10 ′) and the external resistor (ZQ). 
         [0041]    As shown in  FIG. 5 , a D/A converter can include a plurality of circuit sets, each of which can have a NAND gate (ND 50 ), a first code level changing unit  51 , a second code level changing unit  52  and a driver leg  20 ′. 
         [0042]    The NAND gate (ND 50 ) can be configured to transfer a first digital code PCODE&lt;i&gt; in response to an enable signal “EN.” Therefore, other logic devices can be substituted for the NAND gate (ND 50 ) based on the logic level of the enable signal “EN.” 
         [0043]    The driver leg  20 ′ can have the same configuration as that mentioned in  FIG. 2 . However, transistors (M 20 ′) and (M 21 ′) in the driver leg  20 ′ are not fully turned on/off, therefore differentiating it from the transistors described in  FIG. 2 . That is, the transistors (M 20 ′) and (M 21 ′) can be variable resistors. 
         [0044]    The first code level changing unit  51  can have the same configuration as the code level changing unit in  FIG. 4 . The second code level changing unit  52 , as shown in  FIG. 6 , can include an inverter (IV 51 ), a first pass gate (PG 51 ) and a second pass gate (PG 52 ). 
         [0045]    The inverter (IV 51 ) can be configured to receive the second digital code NCODE&lt;i&gt;. A first pass gate (PG 51 ) can be configured to receive a second variable voltage (Vbias_N). That is, the second variable voltage (Vbias_N) can be applied to an input terminal of the first pass gate (PG 51 ), an output of the inverter (IV 51 ) can be applied to a first control terminal of the first pass gate (PG 51 ), and the second digital code NCODE&lt;i&gt; can be applied to a second control terminal of the first pass gate (PG 51 ). A ground voltage (VSSQ) can be applied to an input terminal of the second pass gate (PG 52 ) and the second digital code NCODE&lt;i&gt; can be applied to a first control terminal of the first pass gate (PG 52 ). The output of the inverter (IV 51 ) can be applied to a second control terminal of the second pass gate (PG 52 ). An output terminal of the first pass gate (PG 51 ) can be commonly connected to an output terminal of the second pass gate (PG 52 ). 
         [0046]    The operation of the D/A converter in accordance with another embodiment will be described in detail below. 
         [0047]    When an enable signal “EN” is inactivated to a low level, a high level signal can be input into the first code level changing unit  51  regardless of the logic level of the first digital code PCODE&lt;i&gt;. On the contrary, when the enable signal “EN” is activated to a high level, the first digital code PCODE&lt;i&gt; can be transferred to the first code level changing unit  51 . 
         [0048]    The first code level changing unit  51  can be configured to perform the same operation as the code level changing unit  30  of  FIG. 3 . That is, when the first digital code PCODE&lt;i&gt; is inactivated, a first level-changed code PCODE&lt;i&gt;_T can be output in a voltage level of the power supply voltage (VDDQ). When the first digital code PCODE&lt;i&gt; is activated, the first level-changed code PCODE&lt;i&gt;_T can be output in a voltage level of a first variable voltage (Vbias_P). 
         [0049]    When the first level-changed code PCODE&lt;i&gt;_T having a voltage level of the power supply voltage (VDDQ) is output, the transistor (M 20 ′) in the driver leg  20 ′ is fully turned off. Also, when the first level-changed code PCODE&lt;i&gt;_T having a voltage level of the first variable voltage (Vbias_P) is output, the transistor (M 20 ′) in the driver leg  20 ′ is turned on to an extent which the first variable voltage (Vbias_P) has the voltage level such that the resistance value of the transistor (M 20 ′) is also adjusted. 
         [0050]    In the second code level changing unit  52  of  FIG. 6 , when the second digital code NCODE&lt;i&gt; is inactivated to a low level, the second level-changed code NCODE&lt;i&gt;_T can be output in a voltage level of the ground voltage (VSSQ). The second level-changed code NCODE&lt;i&gt;_T can be input into the transistor (M 21 ′) in the driver leg  20 ′. 
         [0051]    The transistor (M 21 ′) in the driver leg  20 ′ can be fully turned off because the gate level is in the voltage level of the ground voltage (VSSQ). That is, the driver leg  20 ′ which receives the inactivation signal of the second digital code NCODE&lt;i&gt; is not selected and does not carry out the D/A conversion. 
         [0052]    On the other hand, the code level changing unit  52  of  FIG. 6  can be configured to output the second variable voltage (Vbias_N) as the second level-changed code NCODE&lt;i&gt;_T when the second digital code NCODE&lt;i&gt; is activated to a high level. The second level-changed code NCODE&lt;i&gt;_T can be input into the transistor (M 21 ′) in the driver leg  20 ′. 
         [0053]    The second variable voltage (Vbias_N) can be selectively varied in a range of a turn-on starting voltage level to a full turn-on voltage level of the transistor (M 10 ′), i.e., Vtn (threshold voltage of NMOS) to (VDDQ). The second variable voltage (Vbias_N) can be produced by a voltage generator which can be provided within a D/A converting circuit or provided from the outside (a semiconductor memory chip having a D/A converting circuit or an individual memory controller to control the semiconductor memory chip). Such a voltage generator can be configured to produce the second variable voltage (Vbias_N) according to a test mode signal or a mode register set signal. 
         [0054]    The resistance value of the transistor (M 21 ′) in the driver leg  20 ′ can be adjusted based on the voltage level of the second variable voltage (Vbias_N) and the resistance value can also be adjusted. That is, the resistance of the transistor (M 21 ′) can be varied according to the voltage level of the second variable voltage (Vbias_N), being different from the conventional D/A converter in which the resistance value of the transistor can be disregarded due to the full turn-on voltage or the full turn-off voltage to have an infinite quantity of resistance. 
         [0055]    The driver leg  20 ′ which is selected by the first level-changed code PCODE&lt;i&gt;_T and the second level-changed code NCODE&lt;i&gt;_T can be configured to output a second analog voltage (Vncode) by dividing the power supply voltage (VDDQ) based on the proportion of resistance values of the transistors (M 20 ′) and (M 21 ′) to function as a variable transistor and the resistors (R 20 ′) and (R 21 ′). 
         [0056]    An apparatus for on-die termination can use the D/A converter described above in  FIGS. 3 to 6  and is shown in  FIG. 7 . Referring to  FIG. 7 , the on-die termination apparatus can include a first D/A converting unit  100 , a first comparison unit  200 , a first counter  300 , a second D/A converting unit  400 , a second comparison unit  500 , a second counter  600 , a timing control unit  700 , a first register  800 , a second register  900  and a variable voltage generating unit  1000 . The first D/A converting unit  100  can have the same configuration as the D/A converting unit described in  FIG. 3  and the second D/A converting unit  400  can have the same configuration as the D/A converting unit described in  FIG. 5 . 
         [0057]    The first comparison unit  200  can be configured to compare the first analog voltage (Vpcode) with a reference voltage (VREF) in response to pulse signals CPOUTP 1  and CPOUTP 2  and output a first comparison signal “COMP_OUTP.” 
         [0058]    The second comparison unit  500  can be configured to compare the second analog voltage (Vncode) with the reference voltage (VREF) in response to pulse signals “CPOUTN 1 ” and “CPOUTN 2 ” and output a second comparison signal “COMP_OUTN.” 
         [0059]    The first counter  300  can be configured to perform the up and down counting operation for a value stored therein in response to a pulse signal “PCOUNT” and the first comparison signal “COMP_OUTP” and output the counting value as the first digital code PCODE&lt;i&gt;. 
         [0060]    Similar to the first counter  300 , the second counter  600  can be configured to perform an up and down counting operation for a value stored therein in response to a pulse signal “NCOUNT” and the second comparison signal “COMP_OUTN” and output the counting value as the second digital code NCODE&lt;i&gt;. 
         [0061]    In the case of a 5-bit signal, the first and second digital codes PCODE&lt;i&gt; and NCODE&lt;i&gt; can be expressed as PCODE&lt;0:4&gt; and NCODE&lt;0:4&gt;, respectively. For convenience in illustration, the first and second digital codes are expressed as PCODE&lt;i&gt; and NCODE&lt;i&gt;, respectively. 
         [0062]    The timing control unit  700  can be implemented by a pulse generating circuit. The timing control unit  700  can be configured to produce the pulse signals “EN,” “CPOUTP 1 ,” “CPOUTP 2 ,” “CPOUTN 1 ,” “CPOUTN 2 ,” “PCOUNT” and “NCOUNT” in order to control the operation start timing of the first D/A converting unit  100 , the first comparison unit  200 , the first counter  300 , the second D/A converting unit  400 , the second comparison unit  500  and the a second counter  600 . 
         [0063]    The first register  800  can be configured to update and store the first digital code PCODE&lt;i&gt; which can be counted by the first counter  300  and output the stored digital code PCODE&lt;i&gt; to outside of the on-die termination apparatus in response to an enable bar signal “ENB.” Similar to the first register  800 , the second register  900  can be configured to update and store the second digital code NCODE&lt;i&gt; which can be counted by the second counter  600  and output the stored digital code NCODE&lt;i&gt; to outside of the on-die termination apparatus in response to an enable bar signal “ENB.” 
         [0064]    The variable voltage generating unit  1000  can be configured to individually control the first variable voltage (Vbias_P) and the second variable voltage (Vbias_N) based on test mode signals “TM 1 ” and “TM 2 ” or a mode register set signal “MRS.” As shown in  FIG. 7 , the variable voltage generating unit  1000  can be provided to the on-die termination apparatus or one of the first and second D/A converting units  100  and  400 . Furthermore, the variable voltage generating unit  1000  can be provided to all the first and second D/A converting units  100  and  400  in order that the first variable voltage (Vbias_P) and the second variable voltage (Vbias_N) can be separately produced. Also, the variable voltage generating unit  1000  can be provided to an external circuit (a system having the on-die termination apparatus, for example, a memory chip or a memory controller to control the memory chip). Here, the enable bar signal “ENB” can have a logic level opposite to the enable signal “EN” and this can be produced by inverting the enable signal “EN.” 
         [0065]    The detailed operation of the on-die termination apparatus in accordance with one embodiment will be described below. 
         [0066]    The timing control unit  700  can be configured to produce the pulse signals “EN,” “CPOUTP 1 ,” “CPOUTP 2 ,” “CPOUTN 1 ,” “CPOUTN 2 ,” “PCOUNT” and “NCOUNT” each of which can have a time difference there between. The variable voltage generating unit  1000  can be configured to individually produce the first variable voltage (Vbias_P) and the second variable voltage (Vbias_N) based on test mode signals “TM 1 ” and “TM 2 ” or a mode register set signal “MRS” and output them to the first and second D/A converting units  100  and  400 . 
         [0067]    When the enable signal “EN” is activated, the first D/A converting unit  100  can be configured to output the first analog signal “Vpcode” based on the first level-changed code PCODE&lt;i&gt;_T which can be internally converted using the first digital code PCODE&lt;i&gt;. The first comparison unit  200  can be configured to compare the first analog signal “Vpcode” with the reference voltage (VREF) in response to the pulse signal “CPOUTP 1 ” and “CPOUTP 2 ” and then output the first comparison signal “COMP_OUTP.” The first digital code (PCODE&lt;i&gt;) which can be counted by the first counter  300  in response to the first comparison signal “COMP_OUTP” can be fed back to the first D/A converting unit  100  and the first digital code (PCODE&lt;i&gt;) can be repeatedly calibrated by this feedback loop. 
         [0068]    When the enable signal “EN” is activated, the second D/A converting unit  400  can be configured to output the second analog signal “Vncode” based on the first and second level-changed codes PCODE&lt;i&gt;_T and NCODE&lt;i&gt;_T which are internally and respectively converted using the first and second digital codes PCODE&lt;i&gt; and NCODE&lt;i&gt;. 
         [0069]    The second comparison unit  500  can be configured to compare the second analog signal“Vncode” with the reference voltage (VREF) in response to pulse signal “CPOUTN 1 ” and “CPOUTN 2 ” and then output the second comparison signal “COMP_OUTN.” The second digital code NCODE&lt;i&gt; which is counted by the second counter  600  in response to the second comparison signal “COMP_OUTN” can be fed back to the second D/A converting unit  400  and the second digital code (NCODE&lt;i&gt;) can be repeatedly calibrated by this feedback loop. 
         [0070]    The on-die termination calibration can be finally completed by repeating adjustment for predetermined times of the first and second digital codes PCODE&lt;i&gt; and NCODE&lt;i&gt;) through the feedback loop. Thereafter, when the enable bar signal “ENB” is activated, the first and second registers  800  and  900  can be configured to output the finally updated digital codes PCODE_OUT&lt;i&gt; and NCODE_OUT&lt;i&gt;, respectively. 
         [0071]    As apparent from the above, the on-die termination apparatus can enlarge the adjustment range of the analog voltage signal and make it possible to finely control the analog voltage signal, by using the D/A converter in which the transistor to select the driver leg has a variable resistance. Also, the on-die termination apparatus can minutely control the calibration code and reduce the number of the driver legs resulting in area efficiency. 
         [0072]    While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the apparatus and methods described herein should not be limited based on the described embodiments. Rather, the apparatus and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.