Abstract:
Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates generally to semiconductor memories and, in particular, in one or more embodiments, the present disclosure relates to non-volatile memory devices. 
       BACKGROUND 
       [0002]    Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. 
         [0003]    Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand. 
         [0004]    Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices.  FIG. 1  illustrates a NAND type flash memory array architecture  100  wherein the floating gate memory cells  102  of the memory array are logically arranged in an array of rows and columns. In a conventional NAND Flash architecture, “rows” refers to memory cells having commonly coupled control gates, while “columns” refers to memory cells coupled as one or more NAND strings of memory cells  108 , for example. The memory cells  102  of the array are arranged together in strings (e.g., NAND strings), typically of 8, 16, 32, or more each. Memory cells of a string are connected together in series, source to drain, between a source line  114  and a data line  116 , often referred to as a bit line. Each series string of memory cells is coupled to source line  114  by a source select gate such as select gate  110  and to an individual bit line  116  by a drain select gate  104 , for example. The source select gates, such as  110 , are controlled by a source select gate (SGS) control line  112  coupled to their control gates. The drain select gates, such as  104 , are controlled by a drain select gate (SGD) control line  106 . The one or more strings of memory cells are also typically arranged in groups (e.g., blocks) in which the one or more strings coupled to multiple bit lines of a particular group are formed in a common semiconductor material (e.g., common semiconductor well, such as a common p-well)  138  formed in the substrate of the memory device. Due to this commonality of the p-well  138  between the one or more strings of memory cells, each p-well region near each of the memory cell strings has the same potential, such as 0V, or might be biased to a high voltage as part of an erase operation, for example. 
         [0005]    The memory array is accessed by a string driver (not shown) configured to activate a logical row of memory cells by selecting a particular access line, often referred to as a word line, such as WL 7 -WL 0   118   7-0 , for example. Each word line  118  is coupled to the control gates of a row of memory cells  120 . Bit lines BL 1 -BL 4   116   1 - 116   4  can be driven high or low depending on the type of operation being performed on the array. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in  FIG. 1 . 
         [0006]    Memory cells  102  can be configured as what are known in the art as Single Level Memory Cells (SLC) or Multilevel Memory Cells (MLC). SLC and MLC memory cells assign a data state (e.g., as represented by one or more bits) to a specific range of threshold voltages (Vt) stored on the memory cells. Single level memory cells (SLC) permit the storage of a single binary digit (e.g., bit) of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more binary digits per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of Vt ranges assigned to the cell and the stability of the assigned Vt ranges during the lifetime operation of the memory cell. By way of example, one bit (e.g., 1 or 0) may be represented by two Vt ranges, two bits by four ranges, three bits by eight ranges, etc. 
         [0007]    Programming typically involves applying one or more programming pulses to a selected word line and thus to the control gate of each memory cell coupled to the selected word line. Typical programming pulses start at or near 15V and tend to increase in magnitude during each programming pulse application. While the program voltage (e.g., programming pulse) is applied to the selected word line, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, resulting in a charge transfer from the channel to the floating gates of memory cells targeted for programming. More specifically, the floating gates are typically charged through direct injection or Fowler-Nordheim tunneling of electrons from the channel to the floating gate, resulting in a Vt typically greater than zero in a programmed state, for example. In addition, an inhibit voltage is typically applied to bit lines not coupled to a NAND string containing a memory cell that is targeted for programming. 
         [0008]    Memory cells  102  of a selected block are typically erased by first pre-programming all the memory cells of a selected block to bring the memory cells of the selected block to a more uniform state and to help reduce the possibility of overerasure. The memory cells are erased by driving the p-well  138 , and thus the channel regions of the selected block, to an erase voltage, such as 25V, for example. The word lines  118  coupled to the block of memory cells are then typically driven to a lower voltage, such as 1.5V, for example. This applies an erase field across the memory cells sufficient to cause carriers stored in the floating gates and/or charge trapping layers to be removed and the memory cells placed in an erased state with an erased threshold level. 
         [0009]      FIG. 2  shows a side view of a single string of memory cells  208 , such as string  108  shown in  FIG. 1 , formed in a p-well  238  during an erase operation performed upon the string of memory cells. The control gates of each memory cell are shown coupled to the word lines  218   0-7 , such as word lines  118   0-7  as shown in  FIG. 1 . A source select gate  210  and drain select gate  204  are also illustrated. 
         [0010]    During a typical erase operation the p-well  238  is biased to a particular erase voltage, such as 25V, for example, to bias the channel regions of the memory cells. The word lines  218  are also biased to a particular bias level, such as 1.5V. The source select 212 and drain select 206 gate control lines are then left floating in order to disable the source select gate  210  and the drain select gate  204 . Resulting from the 25V bias imposed on the p-well  238 , the bit line  216  and the source line  214  associated with the NAND string  208  are also biased up to approximately 25V. The proximity of the floating SGS control line  212  to the source line  214  causes the floating SGS control signal line to be coupled up to a potential of approximately 20V, for example. A similar 20V bias condition exists on the floating SGD control line  206  as a result of the proximity to the bit line  216  biased to 25V. This 20V bias condition on the SGS control signal line  212  can cause a higher bias condition (e.g., 3V) to occur on the word line  218   0  adjacent to the SGS control signal line. A similar effect occurs on the word line  218   7  adjacent the SGD control signal line  206 . The higher bias condition on word lines  218   0  and  218   7  (e.g., 3V versus 1.5V as shown in  FIG. 2 ) can cause the memory cells coupled to those word lines to erase slower then word lines  218   2-6 , for example. This can result in a particular NAND string of memory cells requiring additional time to complete an erase operation. 
         [0011]    For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present disclosure, there is a need in the art for alternate erase operations for memory devices. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  shows a schematic representation of an array of NAND configured memory cells. 
           [0013]      FIG. 2  shows an alternate schematic representation of a string of NAND configured memory cells during an erase operation. 
           [0014]      FIG. 3  shows a schematic representation of a plurality of NAND strings of memory cells and associated string driver circuitry. 
           [0015]      FIG. 4  shows an alternative schematic representation of a string of NAND configured memory cells. 
           [0016]      FIG. 5  shows a single NAND string of memory cells and string driver circuitry. 
           [0017]      FIG. 6  illustrates a waveform plot of bias potentials during an erase operation according to an embodiment of the present disclosure. 
           [0018]      FIG. 7  shows a table of bias conditions corresponding to an erase operation according to an embodiment of the present disclosure. 
           [0019]      FIG. 8  shows a flowchart illustrating an erase operation according to an embodiment of the present disclosure. 
           [0020]      FIG. 9  illustrates a waveform plot of bias potentials during an erase operation according to an embodiment of the present disclosure. 
           [0021]      FIG. 10  shows a table of bias conditions corresponding to an erase operation according to an embodiment of the present disclosure. 
           [0022]      FIG. 11  shows a flowchart illustrating an erase operation according to an embodiment of the present disclosure. 
           [0023]      FIG. 12  illustrates a schematic representation of a plurality of NAND strings of memory cells and string driver circuitry according to an embodiment of the present disclosure. 
           [0024]      FIG. 13  shows a single NAND string of memory cells and string driver circuitry according to an embodiment of the present disclosure. 
           [0025]      FIG. 14  illustrates a waveform plot of bias potentials during an erase operation according to an embodiment of the present disclosure. 
           [0026]      FIG. 15  shows a table of bias conditions corresponding to an erase operation according to an embodiment of the present disclosure. 
           [0027]      FIG. 16  shows a flowchart illustrating an erase operation according to an embodiment of the present disclosure. 
           [0028]      FIG. 17  illustrates a functional block diagram of a system according to an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense. 
         [0030]      FIG. 3  illustrates a schematic representation of a plurality of NAND strings of memory cells  308  coupled to local control signals SGS/SGD  312 ,  306  and local word lines  318 . Global control signals GSGS/GSGD  324 ,  322  are also illustrated. These global signals are coupled to their respective local signals by string drivers  326 . String drivers  326  are controlled by the block enable signals BLK_EN 1   330   1  and BLK_EN 2   330   2 . Typically, when one block enable signal is active, such as BLK_EN 1   330   1 , the adjacent block enable signal  330   2  is not active so as to deactivate the string drivers  326   2  coupled to it. This prevents having multiple NAND strings coupled to a common bit line from being active at the same time, for example. Signals GSGD  322 , GWL 7 -GWL 0   342  and GSGS  324  are referred to as global signals in that these signals are coupled to multiple blocks of memory cells. For example, NAND string  308   1  might be part of a first block of memory and NAND string  308   2  might be part of a second block of memory. Signals SGS  312 , WL 7 -WL 0   318  and SGD  306  are referred to as local signals in that these signals are coupled to a single block of memory cells, for example. Thus, the local signals are coupled to the global signals by the string drivers  326 . Each NAND string of memory cells  308  is coupled at a first end to a bit line  316  by a drain select gate  304  and is further coupled at the second end of the string to a source line  314  by a source select gate  310  such as discussed above with respect to  FIG. 1 . 
         [0031]    As discussed above with respect to  FIG. 2 , during a typical erase operation of a selected string of memory cells the SGS  312  and SGD  306  control signals are floating and the word lines  318  are biased to a particular voltage, such as 1.5V, for example. Thus, the string driver transistors  326  coupled to the SGS/SGD signals  312 ,  306  need to be disabled (e.g., deactivated) and the string driver transistors  326  coupled to the word lines  318  need to be enabled (e.g., activated.) Disabling the string drivers leaves the local signal line in a high impedance (e.g., floating) state. However, the gates of each transistor of a particular group of string drivers  326  are coupled together by a common block enable signal  330 . Thus, the bias conditions imposed on each of the global signals are adjusted in order to bias a particular string driver transistor activated or deactivated. For example, BLK_EN 1   330   1  might be biased to 3V thus biasing the gate of each string driver transistor  326   1  to 3V. The global signals GSGD  322  and GSGS  324  are also biased to 3V in this example. Thus, the string driver transistors coupled to the block enable signal BLK_EN 1   330   1  and the GSGS/GSGD signals are disabled. The global word line signals  342  are biased to 1.5V. This results in the string driver transistors coupled to BLK_EN 1  and the global word line signals to be enabled. However, as described above, biasing the p-well with an erase voltage and floating the SGS and SGD control signals can cause high voltage coupling to adjacent word lines and affect performance of the erase operation. 
         [0032]      FIG. 4  illustrates an alternate select gate circuit to those shown in  FIGS. 2 and 3 . Specifically, the source select gate  310  and drain select gate  304  of  FIG. 3 , can each be implemented with a charge storage node cell, such as a charge trap or floating gate cell as shown in  FIG. 4 . Thus, the charge storage cell  410  can act as a source select gate and the charge storage cell  404  can act as a drain select gate. The threshold voltages of both charge storage node cells  410  and  404  acting as select gates would be adjusted to a programmed state and are not erased during erase operations performed on the NAND string of memory cells. 
         [0033]    Various embodiments of the present disclosure will be discussed by way of reference to  FIG. 5 .  FIG. 5  shows a single NAND string of memory cells  508  coupled to both local signal lines (e.g., SGS line  512 , WL 0 -WL 129   518 , SGD line  506 ) and global signal lines (e.g., GSGS  524 , GWL 0 -GWL 129   520 , GSGD  522 ) by string driver transistors  528 . The gates of the string driver transistors  528  are connected by a common block enable signal BLK_EN  530 . The NAND string  508  is coupled to a bit line  516  through a drain select gate  504  and is also coupled to a source line  514  by a source select gate  510 . According to one or more embodiments of the present disclosure, edge word lines WL 0   518   0  and WL 129   518   129  act as “dummy” word lines in that the memory cells coupled to these word lines are not used for data storage. Instead, these dummy word lines are allowed to float during at least a portion of an erase operation performed on the NAND string  508  according to one or more embodiments of the present disclosure. It should be noted that various embodiments of the present disclosure might utilize different numbers of word lines, including different numbers of dummy word lines, per NAND string and are not limited to having word lines WL 0 -WL 129   518  shown in  FIG. 5 , for example. 
         [0034]      FIG. 6  illustrates a plot of bias voltages  600  applied to the NAND string  508  during an erase operation according to one or more embodiments of the present disclosure. The waveform plot of  FIG. 6  is shown divided up into multiple time ranges, such as times T 1 -T 5 . These time ranges are not meant to be limiting but are shown to aid in describing biasing conditions occurring during an erase operation according to one or more embodiments of the present disclosure. The absolute and/or relative biasing magnitude of the waveforms shown are also not intended to be limiting but again are intended to aid in the understanding of various embodiments according to the present disclosure. Waveforms of  FIG. 6  having dashed line segments are intended to indicate a floating bias level of the particular waveform during that particular segment.  FIG. 7  shows a table of bias conditions arranged by time ranges (e.g., T 1 -T 5 ) and signal names corresponding to those illustrated by the waveforms of  FIG. 6 . 
         [0035]      FIG. 8  illustrates a flowchart of an erase operation according to one or more embodiments of the present disclosure and corresponding to the waveforms illustrated in  FIG. 6 , the biasing conditions shown by way of example in the table of  FIG. 7  and imposed on the NAND string  508  of  FIG. 5 . The erase operation begins  802  by applying a ramped (e.g., increasing) bias voltage on the p-well  538  of the NAND string of memory cells  508 , as illustrated during time T 2  of  FIG. 6 , for example. The initial bias potential of the increasing bias potential might be 0V, for example. Additional signals are biased to particular levels during step  802  as illustrated by  FIG. 6  and the table of  FIG. 7 . For example, the SGS line  512 , SGD line  506  and the edge word lines (e.g., dummy word lines)  518   0 ,  518   129  are biased to 0V. Inner word lines  518   1  and  518   128  are biased to 0.5V. Remaining inner word lines, such as  518   2-127 , are biased to a level of 1.5V, for example. These initial biasing operations  802  might occur concurrently with the start of the ramped bias potential placed on the well in which the memory cells are formed, or might occur prior to applying the ramped well bias, for example. 
         [0036]    As the p-well bias ramp continues to increase from its initial bias potential, the SGS line  512  and SGD line  506  are allowed to float  804  in response to the p-well bias reaching a first particular release bias potential, such as 5V, for example.  FIG. 7  during time T 3  shows that the BLK_EN signal  530  is biased at 3V. By driving the GSGS line  524  and GSGD line  522  bias levels to 3V as shown in  FIG. 7 , the associated string driver transistors  528  are deactivated. This results in a high impedance (e.g., floating) condition of the select gate SGS line  512  and SGD line  506 . The string drivers coupled to the local word lines WL 0 -WL 129   518  remain in an activated state. 
         [0037]    Following the release of the SGS and SGD lines to a floating state and during the continued increase of the p-well bias, the edge word lines WL 0 /WL 129   518   0,129  are also allowed to float  806 . The release of the edge word lines may occur in response to the p-well reaching a second release bias potential, such as 15V, for example. According to various embodiments of the present disclosure, the first and second release potentials have levels below which stored charge would begin to be removed from a memory cell (e.g., experiencing an erase effect), for example. As shown in  FIG. 7 , during time T 4  the BLK_EN signal  530  continues to be biased at 3V. By driving the GWL 0  and GWL 129  global word lines  518   0,129  from 0V to 3V, their associated string driver transistors are also disabled. This results in the high impedance state of the edge (e.g., dummy) local word lines WL 0   518   0  and WL 129   518   129 . Thus, the various string driver transistors  528  shown in  FIG. 5  can be controlled (e.g., enabled, disabled) by selectively biasing their control gates and/or their associated global signal lines according to various embodiments of the present disclosure, for example. The high impedance (e.g., floating) state of the local SGS/SGD lines and the local edge (e.g., dummy) word lines WL 0 /WL 129  cause these floating lines to be coupled up to a potential nearer the 25V present on the source line  514  and the bit line  516  at the completion of the p-well ramp  808 . For example, the floating lines might be coupled up to a potential of 20V on the SGS/SGD line and 10V on the edge word lines WL 0 /WL 129 . Thus, the potential difference between the word line coupled to the first utilized memory cell (e.g., memory cells coupled to word lines WL 1 /WL 127 ) and the adjacent dummy word line has been reduced from what occurs such as discussed above with respect to  FIG. 2 , for example. The final ramped p-well bias potential (e.g., target bias potential of the increasing bias potential) may vary from 25V according to one or more embodiments of the present disclosure. According to one or more embodiments, the target bias potential of the increasing bias potential is a potential which can cause charge to be removed from a memory cell, such as causing a memory cell to be erased as discussed above, for example. 
         [0038]    Following the erase operation  802  through  808  shown in  FIG. 8 , a verify operation  812  can be performed to determine if the selected memory cells have been successfully erased. If the selected memory cells have passed the erase verify operation  814 , the erase operation is complete  824 . If one or more selected memory cells have not been successfully erased  816 , a check is performed  818  to determine if a maximum number of erase operations have been performed on the selected memory cells. If a particular maximum number of erase operations have not been completed  822 , then additional erase operations are performed. If a maximum number of erase operations have been performed  820 , a failure of one or more of the selected memory cells may be assumed and the memory cells may be marked as defective, for example. 
         [0039]      FIGS. 9 ,  10  and  11  along with reference to  FIG. 5  illustrate an alternate erase operation according to one or more embodiments of the present disclosure.  FIG. 9  illustrates a plot of bias voltages  900  applied to the NAND string  508  during an erase operation according to one or more embodiments of the present disclosure. The waveform plot of  FIG. 9  is shown divided up into multiple time ranges, such as times T 1 -T 4 . These time ranges are not meant to be limiting but are shown to aid in describing biasing conditions occurring during an erase operation according to various embodiments of the present disclosure. The absolute and/or relative biasing magnitude of the waveforms shown are also not intended to be limiting but again are intended to aid in the understanding of various embodiments according to the present disclosure. Waveforms of  FIG. 9  having dashed lines are intended to indicate a floating bias level of the particular waveform.  FIG. 10  shows a table of bias conditions arranged by time ranges (e.g., T 1 -T 4 ) and signal names corresponding to those illustrated by the waveforms of  FIG. 9 . 
         [0040]      FIG. 11  illustrates a flowchart of an erase operation according to one or more embodiments of the present disclosure and corresponding to the waveforms illustrated in  FIG. 9 , the biasing conditions shown in the table of  FIG. 10  and imposed on the NAND string  508  of  FIG. 5 . The erase operation begins  1102  by applying a ramped (e.g., increasing) bias voltage to the p-well  538  of the NAND string of memory cells  508 , as illustrated during time T 2  of  FIG. 9 , for example. Additional signals are also biased to particular levels during step  1102  as illustrated by  FIG. 9  and the table of  FIG. 10 . For example, the SGS line  512 , SGD line  506  and the edge word lines (e.g., dummy word lines)  518   0 ,  518   129  are biased to 0V. Inner word lines  518   1  and  518   128  are biased to 0.5V. Remaining inner word lines, such as  518   2-127 , are biased to a level of 1.5V. These initial biasing conditions might occur concurrently with the start of the ramped bias potential placed on the substrate or might occur prior to applying the ramped well bias, for example. 
         [0041]    According to one or more embodiments as illustrated by  FIGS. 9 ,  10  and  11 , as the p-well bias ramp continues to be driven higher towards its target bias potential, the SGS line  512 , SGD line  506 , and the edge word lines WL 0 /WL 129   518   0,129  are allowed to float  1104 . For example, as shown in  FIG. 10 , during time T 2  the BLK_EN signal  530  is biased at 15V, the GSGS/GSGD lines are biased at 10V and the GWL 0 /GWL 129  word lines are biased to 5V. This bias condition results in the string drivers coupled to the local SGS/SGD and local edge word lines WL 0 /WL 129  to be activated. Thus, the local SGS/SGD lines are driven to 10V and the local edge word lines WL 0 /WL 129  to be driven to 5V as shown in the table of  FIG. 10  during time T 2 . In order to float the SGS/SGD and WL 0 /WL 129  lines as shown in step  1104 , the BLK_EN line bias is adjusted (e.g., reduced) as shown during time T 3  of  FIG. 10 , for example. By reducing the BLK_EN bias level from 15V to 5V the string drivers coupled to the SGS/SGD and WL 0 /WL 129  are deactivated leaving the SGS/SGD and WL 0 /WL 129  lines to float in a high impedance state. Thus, according to the one or more embodiments represented by  FIGS. 9 ,  10  and  11 , the SGS/SGD lines and the edge word lines WL 0 /WL 129  are floated substantially simultaneously during the application of the increasing well bias potential. For example, the SGS/SGD and WL 0 /WL 129  lines might be released (e.g., floated) when the ramped well bias potential reaches a particular bias release potential, for example. As discussed above with respect to  FIG. 8 , the particular release potential is less than an erase potential according to one or more embodiments of the present disclosure. 
         [0042]    The high impedance (e.g., floating) state of the local SGS/SGD lines and the local edge (e.g., dummy) word lines WL 0 /WL 129  cause these floating lines to be coupled up to a potential nearer the final 25V target bias potential present on the source  514  and bit line  516  at the completion of the p-well ramp  1108 . For example, the floating lines might be coupled up to a potential of 20V on the SGS/SGD line and 15V on the edge word lines WL 0 /WL 129  at the completion of the well bias ramp  1108 . Thus, the potential difference between the word lines coupled to the first utilized memory cells (e.g., memory cells coupled to word lines WL 1 /WL 127 ) and the adjacent dummy word line WL 0 /WL 129 , respectively, have been reduced from what occurs such as discussed above with respect to  FIG. 2 , for example. 
         [0043]    Following the erase operation  1102  through  1108  shown in  FIG. 11 , a verify operation  1112  may be performed to determine if the selected memory cells have been successfully erased. If the selected memory cells pass the erase verify operation  1114 , the erase operation is complete  1124 . If one or more selected memory cells have not been successfully erased  1116 , a check is performed  1118  to determine if a maximum number of erase operations have been performed on the selected memory cells. If a particular maximum number of erase operations have not been performed  1122 , additional erase operations such as  1102  through  1108  are repeated. If a maximum number of erase operations have been performed  1120 , a failure of one or more of the selected memory cells may be assumed and the memory cells may be marked as defective, for example. 
         [0044]      FIG. 12  illustrates a schematic representation of a plurality of NAND strings of memory cells  1208  coupled to local control signals SGS/SGD  1212 ,  1206  and local word lines  1218  according to one or more embodiments of the present disclosure. Global control signals GSGS/GSGD  1224 ,  1222  and global word lines GWL 0 -GWL 7   1242  are also illustrated. The global signals GSGS/GSGD are coupled to their respective local signals SGS/SGD by string drivers  1228 . Global word lines GWL 0 -GWL 7   1242  are coupled to their respective local word lines WL 0 -WL 7   1218  by a different set of string drivers  1226 . This allows for independent control of the string drivers coupled to the local SGS/SGD lines and the string drivers coupled to the local word lines WL 0 -WL 7   1218 . String drivers  1226  are controlled by the block enable signals such as BLK_EN 1   1230   1  and BLK_EN 2   1230   2 . Typically, when one block enable signal is active, such as BLK_EN 1   1230   1 , the adjacent block enable signal  1230   2  is not active and vice versa. For example, NAND string  1208   1  might be part of a first block of memory and  308   2  might be part of a different block of memory. String drivers  1228  are controlled by the block enable select gate signals such as BLK_EN_SG 1   1232   1  and BLK_EN_SG 2   1232   2 . Again, when one block enable signal is active, such as BLK_EN_SG 1   1232   1 , the adjacent block enable signal  1232   2  is not active and vice versa. Signals GSGD  1222 , GWL 7 -GWL 0   1242  and GSGS  1224  are referred to as global signals in that these signals are coupled to multiple blocks of memory cells. Signals SGS  1212 , WL 7 -WL 0   1218  and SGD  1206  are referred to as local signals in that these signals are coupled to a single block of memory cells, for example. Thus, the local signals SGS/SGD  1212 ,  1206  are coupled to their respective global signals GSGS/GSGD  1224 ,  1222  by the string drivers  1228  and local word line signals  1218  are coupled to their respective global word line signals  1242  by string drivers  1226 . According to one or more embodiments, the source select gate  1210  and the drain select gate  1204  might be implemented using charge storage node cells, such as charge trap or floating gate memory cells, such as discussed with respect to  FIG. 4 , where the charge storage node memory cells have a permanently programmed state. 
         [0045]    Additional embodiments of the present disclosure will be discussed by way of reference to  FIG. 13  which illustrates the multiple block enable signal structure, such as shown in  FIG. 12 , for example.  FIG. 13  shows a single NAND string of memory cells  1308  coupled to both local signal lines (e.g., SGS line  1312 , WL 0 -WL 129   1318 , SGD line  1306 ) and global signal lines (e.g., GSGS  1324 , GWL 0 -GWL 129   1320 , GSGD  1322 ). The global signals GSGS/GSGD are coupled to their respective local SGS/SGD signals by string drivers  1328 . Global word lines GWL 0 -GWL 129   1320  are coupled to their respective local word lines WL 0 -WL 129   1318  by a separate set of string drivers  1326 . This configuration allows for a block enable select gate signal  1332  to control the string drivers coupled to the global and local source/drain signals, such as GSGS/GSGD and SGS/SGD. A separate block enable signal  1330  is then utilized to control string drivers  1326  coupled to word lines, such as the global and local word lines GWL 0 -GWL 129  and WL 0 -WL 129 . 
         [0046]    According to one or more embodiments of the present disclosure, word lines WL 0   1318   0  and WL 129   1318   129  are edge word lines that act as “dummy” word lines in that the memory cells coupled to these edge word lines are not used for storage. Instead, these dummy word lines are biased and/or are allowed to float during a portion of an erase operation performed on the NAND string according to one or more embodiments of the present disclosure. Again, various embodiments of the present disclosure might utilize different numbers of word lines, including different numbers of dummy word lines, per NAND string and are not limited to having word lines WL 0 -WL 129   1318  shown in  FIG. 13 , for example. 
         [0047]      FIGS. 14 ,  15  and  16  along with reference to  FIG. 13  illustrate an additional alternate erase operation according to one or more embodiments of the present disclosure.  FIG. 14  illustrates a plot of bias voltages  14  applied to the NAND string  1308  during an erase operation according to one or more embodiments of the present disclosure. The waveform plot of  FIG. 14  is shown divided up into multiple time ranges, such as times T 1 -T 3 . These time ranges are not meant to be limiting but are shown to aid in describing biasing conditions occurring during an erase operation according to various embodiments of the present disclosure. The absolute and/or relative biasing magnitude of the waveforms shown are also not intended to be limiting but again are intended to aid in the understanding of various embodiments according to the present disclosure. Waveforms of  FIG. 14  having dashed lines are intended to indicate a floating bias level of the particular waveform.  FIG. 15  shows a table of bias conditions arranged by time ranges (e.g., T 1 -T 3 ) and signal names corresponding to those illustrated by the waveforms of  FIG. 14 . 
         [0048]      FIG. 16  illustrates a flowchart of an erase operation according to one or more embodiments of the present disclosure and corresponding to the waveforms illustrated in  FIG. 14 , the biasing conditions shown in the table of  FIG. 15  and imposed on the NAND string  1308  of  FIG. 13 . The erase operation begins  1602  by applying a ramped (e.g., increasing) bias voltage on the p-well  1338  of the NAND string of memory cells  1308 , as illustrated during time T 2  of  FIG. 14 , for example. Additional signals are also biased to particular levels during step  1602  as illustrated by  FIG. 14  and the table of  FIG. 15 . For example, the SGS line  1312  and SGD line  1306  are biased to 10V. The edge word lines (e.g., dummy word lines) WL 0 /WL 129   1318   0 ,  1318   129  are also biased to 0V. Inner word lines WL 1 /WL 128   1318   1 ,  1318   128  are biased to 0.5V. The remaining inner word lines, such as WL 2 -WL 127   1318   2-127 , are biased to a level of 1.5V. These initial biasing conditions might occur concurrently with the start of the ramped bias potential placed on the well in which the memory cells are formed, or might occur prior to applying the ramped bias, for example. 
         [0049]    According to one or more embodiments as illustrated by  FIGS. 14 ,  15  and  16 , as the p-well bias ramp continues to be driven higher, such as during time T 2  of  FIG. 14 , the SGS line  1312  and SGD line  1306  are allowed to float  1606 . For example, as shown in the table of  FIG. 15 , during time T 2  the BLK_EN_SG signal  530  is biased at 3V, the GSGS and GSGD lines, originally biased to 0V are then biased to 3V. This bias condition results in the string drivers  1328  coupled to the global GSGS/GSGD and local SGS/SGD lines to be deactivated. Thus, the local SGS/SGD lines are put into a high impedance (e.g., floating) state. The release of the local SGS/SGD lines (e.g., change to high impedance state) might occur when the ramped well bias potential reaches or exceeds a particular bias release potential, for example. According to at least one embodiment, the particular bias release potential should be less than the bias potential needed to cause a memory cell to begin to erase. 
         [0050]    The high impedance (e.g., floating) state of the local SGS/SGD lines cause these floating lines to be coupled up to a potential nearer to the final 25V erase potential present on the source  1314  and the bit line  1316  at the completion of the p-well ramp  1608 . For example, the floating lines SGS/SGD lines might be coupled up to a potential of 20V. The edge word lines WL 0 /WL 129  are biased to a potential of 10V as shown in  FIGS. 14 and 15 . Thus, the potential difference between the word line coupled to the first utilized memory cell (e.g., memory cells coupled to word lines WL 1 /WL 127 ) and the adjacent dummy word line WL 0 /WL 129 , respectively, have been reduced from what occurs such as discussed above with respect to  FIG. 2 , for example. In addition, the potential difference between the dummy word lines (e.g., WL 0 /WL 129 ) and the floating SGS/SGD lines have also been reduced. 
         [0051]    Following the erase operation steps  1602  through  1608  shown in  FIG. 11 , a verify operation  1612  is performed to determine if the memory cells selected to be erased have been successfully erased. If the selected memory cells have passed the erase verify operation  1614 , the erase operation is complete  1624 . If one or more selected memory cells have not been successfully erased  1616 , a check is performed  1618  to determine if a maximum number of erase operations have been performed. If a particular maximum number of erase operations have not been completed  1622 , additional erase operations such as  1602  through  1608  are repeated. If a maximum number of erase operations have been performed  1620 , a failure of one or more of the selected memory cells may be assumed and the memory cells may be marked as defective, for example. 
         [0052]      FIG. 17  is a functional block diagram of an electronic system having at least one memory device according to one or more embodiments of the present disclosure. The memory device  1700  illustrated in  FIG. 17  is coupled to a host such as a processor  1710 . The processor  1710  may be a microprocessor or some other type of controlling circuitry. The memory device  1700  and the processor  1710  form part of an electronic system  1720 . The memory device  1700  has been simplified to focus on features of the memory device that are helpful in understanding various embodiments of the present disclosure. 
         [0053]    The memory device  1700  includes one or more arrays of memory cells  1730  that can be logically arranged in banks of rows and columns. Memory array  1730  may comprise SLC and/or MLC memory, for example. According to one or more embodiments, the memory cells of memory array  1730  are flash memory cells. The memory array  1730  might include multiple banks and blocks of memory cells residing on a single or multiple die as part of the memory device  1700 . The memory cells of the memory array  1730  may also be adaptable to store varying densities (e.g., MLC (four level) and MLC (eight level)) of data in each cell, for example. 
         [0054]    An address buffer circuit  1740  is provided to latch address signals provided on address input connections A 0 -Ax  1742 . Address signals are received and decoded by a row decoder  1744  and a column decoder  1746  to access the memory array  1730 . The row decoder circuitry  1744  might also incorporate the string driver control circuitry discussed above according to various embodiments of the present disclosure, for example. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections  1742  depends on the density and architecture of the memory array  1730 . That is, the number of address digits increases with both increased memory cell counts and increased bank and block counts, for example. 
         [0055]    The memory device  1700  reads data in the memory array  1730  by sensing voltage or current changes in the memory array columns using sense/data cache circuitry  1750 . The sense/data cache circuitry  1750 , in at least one embodiment, is coupled to read and latch a row of data from the memory array  1730 . Sense devices such as sense devices  130  discussed with respect to  FIG. 1  can also comprise the sense/data cache circuitry  1750 , for example. Data input and output buffer circuitry  1760  is included for bi-directional data communication over a plurality of data connections  1762  with the processor  1710 . Write/erase circuitry  1755  is provided to write data to or to erase data from the memory array  1730 . Well bias circuitry  1752  is coupled to the array  1730  and facilitates biasing of one or more wells (e.g., p-wells) of the memory array  1730  according to various embodiments of the present disclosure. For example, well bias circuitry  1352  can generate the ramped well bias potential discussed according to various embodiments of the present disclosure. 
         [0056]    Control circuitry  1770  is configured at least in part to implement various embodiments of the present disclosure, such as facilitating the methods discussed above with respect to  FIGS. 5-16 , for example. In at least one embodiment, the control circuitry  1770  may utilize a state machine. Control signals and commands can be sent by the processor  1710  to the memory device  1700  over the command bus  1772 . The command bus  1772  may be a discrete signal or may be comprised of multiple signals, for example. These command signals  1772  are used to control the operations on the memory array  1730 , including data read, data write (e.g., program), and erase operations. The command bus  1772 , address bus  1742  and data bus  1762  may all be combined or may be combined in part to form a number of standard interfaces  1778 . For example, the interface  1778  between the memory device  1700  and the processor  1710  may be a Universal Serial Bus (USB) interface. The interface  1778  may also be a standard interface used with many hard disk drives (e.g., SATA, PATA) as are known to those skilled in the art. 
         [0057]    The electronic system illustrated in  FIG. 17  has been simplified to facilitate a basic understanding of the features of the memory and is for purposes of illustration only. A more detailed understanding of internal circuitry and functions of non-volatile memories are known to those skilled in the art. 
       CONCLUSION 
       [0058]    In summary, one or more embodiments of the present disclosure provide methods of managing signal lines during an erase operation. These methods facilitate a reduction in the electric field between particular control signals, such as local and global select gate control signals and local and global word line signals which are coupled to a string of memory cells undergoing an erase operation. 
         [0059]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the disclosure will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the disclosure.