Abstract:
A disk drive system including a write circuit for controlling current through a magnetic write head includes an H-switch circuit and a pulse-mode power supply circuit. The H-switch circuit controls direction of current through the magnetic write head. The pulse-mode power supply circuit is connected to the H-switch circuit for providing a higher voltage pulse at a beginning of a switching event of the H-switch circuit to accelerate a change in direction of current through the write head, followed by a lower voltage until a next switching event.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a magnetizing current control circuit which operates with a magnetic write head in a magnetic data storage and retrieval system. In particular, the present invention relates to a magnetizing current control circuit having a higher switching rate and reduced power consumption. 
     In magnetic data storage and retrieval systems, a magnetic write head records two-logic-state data in a magnetic data storage medium such as a magnetic tape or magnetic disc. The magnetic write head has an inductive coil with currents provided therethrough in alternate directions, representing the data, to impart a series of alternate magnetic field patterns over time to the magnetic medium moving by it. Producing alternate magnetic field patterns over time entails switching the electric current through the inductive coil between forward and reverse directions therethrough to correspond to the data. Current in the inductive coil generates a magnetic field oriented in a direction corresponding to the direction of flow through the coil; thus, reversing the direction of current reverses the orientation of the magnetic field. The magnetic fields generated by the inductive coil currents intersect the magnetic medium to polarize adjacent magnetic medium regions which in effect serve as data symbol storage positions on the medium, and so form magnetic patterns along a corresponding one of more or less concentric tracks in the medium from which an information signal can be retrieved. 
     Controlling the directions and magnitudes of currents through the inductive coil is the purpose of a magnetizing current control circuit. A typical magnetizing current control circuit includes a switching network. The switching network is connected to the ends of the inductive coil in the magnetic write head at first and second head nodes, and includes four switching transistors arranged as pairs with each pair member connected to a corresponding one of these head nodes. One pair is switched on directing current flow in one direction through the inductive coil with the other pair switched off and, alternatively, this latter pair is switched on to direct current flow through the inductive coil in the opposite direction with the first pair being switched off. More specifically, the switching transistors are connected to the inductive coil such that a first switching transistor is connected between a first voltage source node and the first head node, a second switching transistor is connected between the first voltage source node and the second head node, a third switching transistor is connected between the first head node and a second voltage source node, and a fourth switching transistor is connected between the second head node and the second voltage source node. 
     One principal concern in the performance of magnetizing current control circuits is the duration of time needed to complete a switching of current direction through the inductive coil which directly affects the switching rate. Switching rate, a measure of how often the magnetizing current control circuit can reverse current direction through the inductive coil per unit of time, determines the maximum linear spatial density of data along a track in the magnetic medium. Ultimately, a higher switching rate yields denser data storage and thus greater total data capacity for a magnetic medium. 
     A key determinant of the current reversal switching time duration is the head swing voltage, i.e. the voltage difference between the head nodes of the magnetizing current control circuit. The larger the voltage drop applied in the opposite direction across the inductive coil after a switching to reverse the current therethrough, the quicker the change in direction of current through the inductive coil. This is because the voltage-current characteristic of an inductive coil is determined by V=Ldi/dt+R L I, where V is the voltage across the inductive coil, di/dt is the rate of change of current over time through the inductive coil, L is the inductance of the inductive coil, R L  is the resistance of the inductive coil, and I is the current through the inductive coil. Because the inductance of the inductive coil is constant and the resistance of the inductive coil is relatively small, there is a direct relationship between the voltage impressed across the inductive coil after switching and the rate of change of current over time through the inductive coil. 
     In typical magnetizing current control circuits, the head swing voltage is equal to the voltage difference between the emitters of the first and second switching transistors. In order to create a large voltage difference between the emitters of the first and second switching transistors after a switching to reverse the current through the inductive coil, a similarly large voltage difference is applied to the bases of the first and second switching transistors. This, however, typically requires the magnetizing current control circuit to be operated by a continuous high supply voltage, which in turn causes the circuit to have high power consumption. 
     Accordingly, there is a need for a magnetizing current control circuit that maximizes the head swing voltage while minimizing the power consumption of the circuit. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is a disk drive system including a write circuit for controlling current through a magnetic write head. An H-switch circuit controls direction of current through the magnetic write head. A pulse-mode power supply circuit is connected to the H-switch circuit for providing a higher voltage pulse at a beginning of a switching event of the H-switch circuit to accelerate a change in direction of current through the write head, followed by a lower voltage until a next switching event. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit schematic diagram of a prior art magnetic write circuit. 
     FIG. 2 shows a circuit schematic diagram of a first embodiment of a magnetic write circuit of the present invention. 
     FIG. 3 shows a circuit schematic diagram of a second embodiment of a magnetic write circuit of the present invention. 
     FIG. 4 shows a circuit schematic diagram of a third embodiment of a magnetic write circuit of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a circuit schematic diagram of a prior art magnetic write circuit  10 . Prior art magnetic write circuit  10  is part of a disk drive system and controls the magnitude and direction of current through a magnetic write head  11  represented in the diagram as an inductive coil L H . Prior art magnetic write circuit  10  includes switching transistors Q 1 , Q 2 , M 1 , and M 2 , current generators I 1  and I 2 , input signal circuit nodes WDX and WDY, circuit head nodes H 1  and H 2 , and voltage source nodes V 1  and GND. 
     Switching transistors Q 1  and Q 2  are npn bipolar junction transistors each having a base, a collector, and an emitter. Switching transistors M 1  and M 2  are NMOS transistors each having a gate, a drain, and a source. Current generators I 1  and I 2  are each portions of a current mirror circuit used to generate a reference current Iw. Input signal circuit node WDX is connected to the base of switching transistor Q 1  and the gate of switching transistor M 2 , and input signal circuit node WDY is connected to the base of switching transistor Q 2  and the gate of switching transistor M 1 . The collectors of switching transistors Q 1  and Q 2  are each connected to voltage source node V 1 , and the emitters of switching transistors Q 1  and Q 2  are connected respectively to circuit head nodes H 1  and H 2 . Current generator I 1  is connected between circuit head node H 1  and the drain of switching transistor M 1 , and current generator I 2  is connected between circuit head node H 2  and the drain of switching transistor M 2 . The sources of switching transistors M 1  and M 2  are each connected to voltage source node GND. 
     In an initial input signal situation chosen for purposes of description, input signal node WDX has a high voltage (V 1 ) and input signal node WDY has a low voltage (GND), for example. In the steady state in this situation, switching transistors Q 1  and M 2  are turned on and switching transistors Q 2  and M 1  are turned off. The voltages at circuit head nodes H 1  and H 2  are approximately V 1 −VBE, as the resistance of inductive coil L H  is low (where VBE is the voltage drop across the base-emitter pn junction of transistor Q 1 ). Current Iw is drawn from voltage source node V 1 , through the collector and emitter of switching transistor Q 1 , through magnetic write head  11  from head node H 1  to H 2 , through current generator I 2 , through the drain and source of switching transistor M 2 , and into voltage source node GND. 
     When the input signal on nodes WDX and WDY is subsequently changed to then have a high voltage (V 1 ) at input signal node WDY and a low voltage (GND) at input signal node WDX, switching transistor M 1  is turned on and switching transistor M 2  is turned off. In addition, the low voltage at input signal node WDX (which is equal to the voltage at the base of switching transistor Q 1 ) causes the voltage at the emitter of switching transistor Q 1  to initially drop to approximately −VBE, and the high voltage at input signal node WDY (which is equal to the base of switching transistor Q 2 ) turns on switching transistor Q 2  and causes the voltage at the emitter of switching transistor Q 2  to rise to approximately V 1 −VBE. 
     Because the voltage at head node H 1  (which is equal to the voltage at the emitter of switching transistor Q 1 ) is approximately −VBE and the voltage at head node H 2  (which is equal to the voltage at the emitter of switching transistor Q 2 ) is approximately V 1 −VBE, a voltage drop of approximately V 1  volts is initially created across inductive coil L H  from head node H 2  to H 1 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 1  to H 2 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 2  to H 1 . 
     After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 2  to H 1 , the voltage at head node H 1  will begin to rise to nearly the voltage at head node H 2 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 2  is held approximately constant because the voltage drop VBE across the base-emitter pn junction of switching transistor Q 2  (which is turned on) is approximately constant. This decreasing voltage across inductive coil L H  causes switching transistor Q 1  to turn off because the voltage at the emitter of switching transistor Q 1  (which is equal to the voltage at head node H 1 ) is no longer a VBE lower than the voltage at its base (which is held at approximately GND). 
     Therefore, because switching transistors Q 2  and M 1  are turned on and switching transistors Q 1  and M 2  are turned off with a high voltage at node WDY and a low voltage at node WDX, a current approximately equal to Iw is drawn from voltage source node V 1 , through the collector and emitter of switching transistor Q 2 , through magnetic write head  11  from head node H 2  to H 1 , through the drain and source of switching transistor M 1 , and into voltage source node GND. As described above, a maximum voltage drop of approximately V 1  volts is created across inductive coil L H  from head node H 2  to H 1  at the beginning of the input situation to reverse the direction of current through inductive coil L H . 
     When the input signal on nodes WDX and WDY is subsequently changed to again have a high voltage (V 1 ) at input signal node WDX and a low voltage (GND) at input signal node WDY as in the initial input signal steady state situation described above, switching transistor M 2  is turned on and switching transistor M 1  is turned off. In addition, the low voltage at input signal node WDY (which is equal to the voltage at the base of switching transistor Q 2 ) causes the voltage at the emitter of switching transistor Q 2  to initially drop to approximately −VBE, and the high voltage at input signal node WDX (which is equal to the base of switching transistor Q 1 ) turns on switching transistor Q 1  and causes the voltage at the emitter of switching transistor Q 1  to rise to approximately V 1 −VBE. 
     Because the voltage at head node H 2  (which is equal to the voltage at the emitter of switching transistor Q 2 ) is approximately −VBE and the voltage at head node H 1  (which is equal to the voltage at the emitter of switching transistor Q 1 ) is approximately V 1 −VBE, a voltage drop of approximately V 1  volts is initially created across inductive coil L H  from head node H 1  to H 2 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 2  to H 1 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 1  to H 2 . 
     After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 1  to H 2 , the voltage at head node H 2  will begin to rise to nearly the voltage at head node H 1 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 1  is held approximately constant because the voltage drop VBE across the base-emitter pn junction of switching transistor Q 1  (which is turned on) is approximately constant. This decreasing voltage across inductive coil L H  causes switching transistor Q 2  to turn off because the voltage at the emitter of switching transistor Q 2  (which is equal to the voltage at head node H 2 ) is no longer a VBE lower than the voltage at its base (which is held at approximately GND). 
     Therefore, because switching transistors Q 1  and M 2  are turned on and switching transistors Q 2  and M 1  are turned off with a high voltage at node WDX and a low voltage at node WDY, a current approximately equal to Iw is drawn from voltage source node V 1 , through the collector and emitter of switching transistor Q 1 , through magnetic write head  11  from head node H 1  to H 2 , through the drain and source of switching transistor M 2 , and into voltage source node GND. As described above, a maximum voltage drop of approximately V 1  volts is created across inductive coil L H  from head node H 1  to H 2  at the beginning of the input situation to reverse the direction of current through inductive coil L H . 
     FIG. 2 shows a circuit schematic diagram of a first embodiment of a magnetic write circuit  20  of the present invention. Magnetic write circuit  20  is part of a disk drive system and controls the magnitude and direction of current through a magnetic write head  21  represented in the diagram as an inductive coil L H . Magnetic write head  21 , which is coupled into the remainder of the circuit between circuit head nodes H 1  and H 2 , includes inductive coil L H  along with magnetic material positioned in magnetic fields generated by current therethrough. Magnetic write circuit  20  includes writer circuit  22 , power supply circuit  24 , input signal circuit nodes WDX and WDY, the circuit head nodes H 1  and H 2  previously mentioned, and voltage source nodes V 1 , V 2 , and GND (where a significantly higher voltage is provided at voltage source node V 2  than at voltage source node V 1 ). Magnetic write circuit  20  is preferably fabricated in an integrated circuit. 
     Writer circuit  22  includes switching transistors Q 1 , Q 2 , M 1  and M 2 , current generators I 1  and I 2 , and amplifiers A 1 -A 4 . Switching transistors Q 1  and Q 2  are npn bipolar junction transistors each having a base, a collector, and an emitter. Switching transistors M 1  and M 2  are NMOS transistors each having a gate, a drain, and a source. Current generators I 1  and I 2  are each portions of a current mirror circuit used to generate a reference current Iw. Amplifiers A 1 -A 4  each have an input node, an output node, and first and second supply nodes, where the voltages at the first and second supply nodes are respectively the upper and lower limits of the voltage at the output node. Amplifiers A 1  and A 2  each exhibit a gain of V 2 /V 1 , while amplifiers A 3  and A 4  each do not exhibit any gain but are important for timing considerations. Input signal circuit node WDX is connected to the input nodes of amplifiers A 1  and A 3 , and input signal node WDY is connected to the input nodes of amplifiers A 2  and A 4 . The output node of amplifier A 1  is connected to the base of switching transistor Q 1 , and the first and second supply nodes of amplifier A 1  are connected respectively to the collector of switching transistor Q 1  and voltage source node GND. The output node of amplifier A 2  is connected to the base of switching transistor Q 2 , and the first and second supply nodes of amplifier A 2  are connected respectively to the collector of switching transistor Q 2  and voltage source node GND. The output node of amplifier A 3  is connected to the gate of switching transistor M 2 , and the first and second supply nodes of amplifier A 3  are connected respectively to voltage source nodes V 1  and GND. The output node of amplifier A 4  is connected to the gate of switching transistor M 1 , and the first and second supply nodes of amplifier A 4  are connected respectively to voltage source nodes V 1  and GND. The emitters of switching transistors Q 1  and Q 2  are connected respectively to circuit head nodes H 1  and H 2 . Current generator I 1  is connected between circuit head node H 1  and the drain of switching transistor M 1 , and current generator I 2  is connected between circuit head node H 2  and the drain of switching transistor M 2 . The sources of switching transistors M 1  and M 2  are each connected to voltage source node GND. 
     Power supply circuit  24  includes transistors Q 3  and Q 4 , diodes D 1  and D 2 , time delay devices TD 1  and TD 2 , and amplifiers A 5  and A 6 . Transistors Q 3  and Q 4  are npn bipolar junction transistors each having a base, a collector, and an emitter. Diodes D 1  and D 2  are Schottky diodes each having an anode and a cathode. Time delay devices TD 1  and TD 2  each have an input node and an output node, and provide a time delay of about 100 ps to about 500 ps between the input node and the output node. Amplifiers A 5  and A 6  each have an input node, an output node, and first and second supply nodes, where the voltages at the first and second supply nodes are respectively the upper and lower limits of the voltage at the output node. Amplifiers A 5  and A 6  each exhibit a gain of V 2 /V 1 . Input signal circuit node WDX is connected to the input node of time delay device TD 2 , and input signal circuit node WDY is connected to the input node of time delay device TD 1 . The output nodes of time delay devices TD 1  and TD 2  are connected respectively to the input nodes of amplifiers A 5  and A 6 . The output node of amplifier A 5  is connected to the base of transistor Q 3 , and the first and second supply nodes of amplifier A 5  are connected respectively to voltage source nodes V 2  and GND. The output node of amplifier A 6  is connected to the base of transistor Q 4 , and the first and second supply nodes of amplifier A 6  are connected respectively to voltage source nodes V 2  and GND. The collectors of transistors Q 3  and Q 4  are each connected to voltage source node V 2 , and the emitters of transistors Q 3  and Q 4  are connected respectively to the collectors of switching transistors Q 1  and Q 2 . Diode D 1  has its anode connected to voltage source node V 1  and its cathode connected to the collector of switching transistor Q 1 , and diode D 2  has its anode connected to voltage source node V 1  and its cathode connected to the collector of switching transistor Q 2 . 
     In an initial input signal situation chosen for purposes of description, input signal node WDX has a high voltage (V 1 ) and input signal node WDY has a low voltage (GND), for example. In the steady state in this situation, switching transistors Q 1  and M 2  in writer circuit  22  are turned on, switching transistors Q 2  and M 1  in writer circuit  22  are turned off, diode D 1  in power supply circuit  24  is turned on, and diode D 2  in power supply circuit  24  is turned off. The voltages at circuit head nodes H 1  and H 2  are approximately V 1 −VD−VBE, as the resistance of inductive coil L H  is low (where VD is the voltage drop across diode D 1  when turned on, and VBE is the voltage drop across the base-emitter pn junction of transistor Q 1 ). Current Iw is drawn from voltage source node V 1 , through diode D 1 , through the collector and emitter of switching transistor Q 1 , through magnetic write head  21  from head node H 1  to H 2 , through current generator I 2 , through the drain and source of switching transistor M 2 , and into voltage source node GND. In addition, transistor Q 4  in power supply circuit  24  is turned on, and transistor Q 3  in power supply circuit  24  is turned off. As a result, the voltage at the collector of switching transistor Q 2  (which is equal to the voltage at the emitter of transistor Q 4 ) is approximately V 2 −VBE, and the voltage at the collector of switching transistor Q 1  (which is equal to the voltage at the emitter of transistor Q 3 ) is approximately V 1 −VD (where VBE is the voltage drop across the base-emitter pn junction of transistor Q 4 , and VD is the voltage drop across diode D 1  when turned on). 
     When the input signal on nodes WDX and WDY is subsequently changed to then have a high voltage (V 1 ) at input signal node WDY and a low voltage (GND) at input signal node WDX, amplifiers A 3  and A 4  pass this change therethrough to turn on switching transistor M 1  in writer circuit  22  and turn off switching transistor M 2  in writer circuit  22 . In addition, in this circumstance, time delay device TD 1  of power supply circuit  24  receives a high voltage signal at its input node, and time delay device TD 2  of power supply circuit  24  receives a low voltage signal at its input node. Because time delay devices TD 1  and TD 2  each provide a time delay of about 100 ps to about 500 ps, transistor Q 3  of power supply circuit  24  remains initially still turned off and transistor Q 4  of power supply circuit  24  remains initially still turned on. As a result, the voltage at the collector of switching transistor Q 1  remains initially V 1 −VD and the voltage at the collector of switching transistor Q 2  remains initially V 2 −VBE. Furthermore, in this circumstance, amplifier A 1  passes the low voltage at input signal node WDX therethrough to cause the voltage at the base of switching transistor Q 1  to initially drop to approximately GND, and amplifier A 2  passes the high voltage at input signal node WDY therethrough to turn on switching transistor Q 2  and cause the voltage at the base of switching transistor Q 2  to initially rise to approximately V 2 −VBE. This is because amplifier A 2  has a gain of V 2 /V 1  and its first supply node is connected to the collector of switching transistor Q 2  (which has a voltage of V 2 −VBE). 
     Because the voltage at head node H 1  (which is equal to the voltage at the emitter of switching transistor Q 1 ) is approximately −VBE and the voltage at head node H 2  (which is equal to the voltage at the emitter of switching transistor Q 2 ) is approximately V 2 − 2 VBE, a voltage drop of approximately V 2 −VBE volts is initially created across inductive coil L H  from head node H 2  to H 1 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 1  to H 2 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 2  to H 1 . 
     After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 2  to H 1 , the voltage at head node H 1  will begin to rise to nearly the voltage at head node H 2 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 2  is held approximately constant during the time delay of time delay devices TD 1  and TD 2  because the voltage drop VBE across the base-emitter pn junction of switching transistor Q 2  (which is turned on) is approximately constant. This decreasing voltage across inductive coil L H  causes switching transistor Q 1  to turn off because the voltage at the emitter of switching transistor Q 1  (which is equal to the voltage at head node H 1 ) is no longer a VBE lower than the voltage at its base (which is held at approximately GND). 
     After the time delay (about 100 ps to about 500 ps) of time delay devices TD 1  and TD 2 , amplifier A 5  receives a high voltage signal at its input node from the output node of time delay device TD 1 , and amplifier A 6  receives a low voltage signal at its input node from the output node of time delay device TD 2 . Amplifier A 5  passes the high voltage signal therethrough to turn on transistor Q 3  and cause the voltage at the base of transistor Q 3  to rise to approximately V 2 . This is because amplifier A 5  has a gain of V 2 /V 1  and its first supply node is connected to voltage source node V 2 . In addition, amplifier A 6  passes the low voltage signal therethrough to turn off transistor Q 4  and cause the voltage at the base of transistor Q 4  to drop to approximately GND. 
     At this time, diode D 1  is turned off because the voltage at the emitter of transistor Q 3  is higher than V 1 −VD, and diode D 2  is turned on because the voltage at the emitter of transistor Q 4  is no longer higher than V 1 −VD. As a result, the voltage at the collector of switching transistor Q 2  is reduced to approximately V 1 −VD now that current is being drawn through diode D 2 . This in turn causes the voltage at the base of switching transistor Q 2  to be approximately V 1 −VD and the voltages at head nodes H 1  and H 2  to be approximately V 1 −VD−VBE. In addition, the voltage at the collector of switching transistor Q 1  (which is equal to the voltage at the emitter of transistor Q 3 ) is increased to approximately V 2 −VBE. 
     Therefore, because switching transistors Q 2  and M 1  are turned on and switching transistors Q 1  and M 2  are turned off with a high voltage at node WDY and a low voltage at node WDX, a current approximately equal to Iw is drawn from voltage source node V 1 , through diode D 2 , through the collector and emitter of switching transistor Q 2 , through magnetic write head  21  from head node H 2  to H 1 , through the drain and source of switching transistor M 1 , and into voltage source node GND. As described above, a maximum voltage drop of approximately V 2 −VBE volts is initially created across inductive coil L H  from head node H 2  to H 1  at the beginning of the input situation to reverse the direction of current through inductive coil L H  as quickly as possible. Then, after the time delay of time delay devices TD 1  and TD 2 , current Iw is drawn from voltage source node V 1  instead of voltage source node V 2  to reduce the voltages at head nodes H 1  and H 2  and thus the power consumption of magnetic write circuit  20 . 
     When the input signal on nodes WDX and WDY is subsequently changed to again have a high voltage (V 1 ) at input signal node WDX and a low voltage (GND) at input signal node WDY as in the initial input signal steady state situation described above, amplifiers A 3  and A 4  pass this change therethrough to turn on switching transistor M 2  in writer circuit  22  and turn off switching transistor M 1  in writer circuit  22 . In addition, in this circumstance, time delay device TD 2  of power supply circuit  24  receives a high voltage signal at its input node, and time delay device TD 1  of power supply circuit  24  receives a low voltage signal at its input node. Because time delay devices TD 1  and TD 2  each provide a time delay of about 100 ps to about 500 ps, transistor Q 4  of power supply circuit  24  remains initially still turned off and transistor Q 3  of power supply circuit  24  remains initially still turned on. As a result, the voltage at the collector of switching transistor Q 2  remains initially V 1 −VD and the voltage at the collector of switching transistor Q 2  remains initially V 2 −VBE. Furthermore, in this circumstance, amplifier A 2  passes the low voltage at input signal node WDY therethrough to cause the voltage at the base of switching transistor Q 2  to initially drop to approximately GND, and amplifier A 1  passes the high voltage at input signal node WDX therethrough to turn on switching transistor Q 1  and cause the voltage at the base of switching transistor Q 1  to initially rise to approximately V 2 −VBE. This is because amplifier A 1  has a gain of V 2 /V 1  and its first supply node is connected to the collector of switching transistor Q 1  (which has a voltage of V 2 −VBE). 
     Because the voltage at head node H 2  (which is equal to the voltage at the emitter of switching transistor Q 2 ) is approximately −VBE and the voltage at head node H 1  (which is equal to the voltage at the emitter of switching transistor Q 1 ) is approximately V 2 − 2 VBE, a voltage drop of approximately V 2 −VBE volts is initially created across inductive coil L H  from head node H 1  to H 2 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 2  to H 1 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 1  to H 2 . 
     After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 1  to H 2 , the voltage at head node H 2  will begin to rise to nearly the voltage at head node H 1 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 1  is held approximately constant during the time delay of time delay devices TD 1  and TD 2  because the voltage drop VBE across the base-emitter pn junction of switching transistor Q 1  (which is turned on) is approximately constant. This decreasing voltage across inductive coil L H  causes switching transistor Q 2  to turn off because the voltage at the emitter of switching transistor Q 2  (which is equal to the voltage at head node H 1 ) is no longer a VBE lower than the voltage at its base (which is held at approximately GND). 
     After the time delay (about 100 ps to about 500 ps) of time delay devices TD 1  and TD 2 , amplifier A 6  receives a high voltage signal at its input node from the output node of time delay device TD 2 , and amplifier A 5  receives a low voltage signal at its input node from the output node of time delay device TD 1 . Amplifier A 6  passes the high voltage signal therethrough to turn on transistor Q 4  and cause the voltage at the base of transistor Q 4  to rise to approximately V 2 . This is because amplifier A 6  has a gain of V 2 /V 1  and its first supply node is connected to voltage source node V 2 . In addition, amplifier A 5  passes the low voltage signal therethrough to turn off transistor Q 3  and cause the voltage at the base of transistor Q 3  to drop to approximately GND. 
     At this time, diode D 2  is turned off because the voltage at the emitter of transistor Q 4  is higher than V 1 −VD, and diode D 1  is turned on because the voltage at the emitter of transistor Q 3  is no longer higher than V 1 −VD. As a result, the voltage at the collector of switching transistor Q 1  is reduced to approximately V 1 −VD now that current is being drawn through diode D 1 . This in turn causes the voltage at the base of switching transistor Q 1  to be approximately V 1 −VD and the voltages at head nodes H 1  and H 2  to be approximately V 1 −VD−VBE. In addition, the voltage at the collector of switching transistor Q 2  (which is equal to the voltage at the emitter of transistor Q 4 ) is increased to approximately V 2 −VBE. 
     Therefore, because switching transistors Q 1  and M 2  are turned on and switching transistors Q 2  and M 1  are turned off with a high voltage at node WDX and a low voltage at node WDY, a current approximately equal to Iw is drawn from voltage source node V 1 , through diode D 1 , through the collector and emitter of switching transistor Q 1 , through magnetic write head  21  from head node H 1  to H 2 , through the drain and source of switching transistor M 2 , and into voltage source node GND. As described above, a maximum voltage drop of approximately V 2 −VBE volts is initially created across inductive coil L H  from head node H 1  to H 2  at the beginning of the input situation to reverse the direction of current through inductive coil L H  as quickly as possible. Then, after the time delay of time delay devices TD 1  and TD 2 , current Iw is drawn from voltage source node V 1  instead of voltage source node V 2  to reduce the voltage at head nodes H 1  and H 2  and thus the power consumption of magnetic write circuit  20 . 
     The actual power savings of magnetic write circuit  20  is frequency dependent and is shown in Table 1. 
     
       
         
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
             
             
               
                   
                 Power Consumption 
                 Power Consumption 
                   
               
               
                   
                 w/continuous 12 V 
                 w/pulse mode 
               
               
                 Data Rate 
                 power supply 
                 power supply 
                 Power Savings 
               
               
                   
               
               
                 1 MB/sec 
                  867 mW 
                 243 mW 
                 72% 
               
               
                 1 GB/sec 
                 1067 mW 
                 732 mW 
                 30% 
               
               
                   
               
             
          
         
       
     
     FIG. 3 shows a circuit schematic diagram of a second embodiment of a magnetic write circuit  30  of the present invention. Magnetic write circuit  30  is part of a disk drive system and controls the magnitude and direction of current through a magnetic write head  31  represented in the diagram as an inductive coil L H . Magnetic write head  31 , which is coupled into the remainder of the circuit between circuit head nodes H 1  and H 2 , includes inductive coil L H  along with magnetic material positioned in magnetic fields generated by current therethrough. Magnetic write circuit  30  includes writer circuit  32 , power supply circuit  34 , input signal circuit nodes WDX and WDY, the circuit head nodes H 1  and H 2  previously mentioned, and voltage source nodes V 1 , V 2 , and GND (where a significantly higher voltage is provided at voltage source node V 2  than at voltage source node V 1 ). Magnetic write circuit  30  is preferably fabricated in an integrated circuit. 
     Writer circuit  32  is identical to writer circuit  22  of magnetic write circuit  20 . Power supply circuit  34 , however, differs from power supply circuit  24  of magnetic write circuit  20  in that transistors Q 3  and Q 4  in power supply circuit  34  are pnp bipolar junction transistors (each having a base, an emitter, and a collector) instead of the npn bipolar junction transistors used in power supply circuit  24 . Unlike npn bipolar junction transistors that use a high voltage at the base to turn the transistor on and a low voltage at the base to turn the transistor off, pnp bipolar junction transistors use a low voltage at the base to turn the transistor on and a high voltage at the base to turn the transistor off. For this reason, input signal circuit node WDX is connected to the input node of time delay device TD 1  instead of time delay device TD 2 , and input signal circuit node WDY is connected to the input node of time delay device TD 2  instead of time delay device TD 1 . Amplifier A 5  has its output node connected to the base of transistor Q 3 , and its first and second supply nodes connected respectively to voltage source nodes V 2  and V 1 . Amplifier A 6  has its output node connected to the base of transistor Q 4 , and its first and second supply nodes connected respectively to voltage source nodes V 2  and V 1 . Transistor Q 3  has its emitter connected to voltage source node V 2  and its collector connected to the collector of switching transistor Q 1 . Transistor Q 4  has its emitter connected to voltage source node V 2  and its collector connected to the collector of switching transistor Q 2 . 
     When transistor Q 3  is turned on, the voltage at the collector of switching transistor Q 1  (which is equal to the voltage at the collector of transistor Q 3 ) is approximately V 2 −VEB (where VEB is the voltage drop across the emitter-base pn junction of transistor Q 3 ). When transistor Q 3  is turned off, the voltage at the collector of switching transistor Q 1  is approximately V 1 −VD (where VD is the voltage drop across diode D 1  when turned on). Similarly, when transistor Q 4  is turned on, the voltage at the collector of switching transistor Q 2  (which is equal to the voltage at the collector of transistor Q 4 ) is approximately V 2 −VEB (where VEB is the voltage drop across the emitter-base pn junction of transistor Q 4 ). When transistor Q 4  is turned off, the voltage at the collector of switching transistor Q 2  is approximately V 1 −VD (where VD is the voltage drop across diode D 2  when turned on). Therefore, magnetic write circuit  30  creates a maximum voltage drop of approximately V 2 −VEB volts across inductive coil L H  at the beginning of an input situation to reverse the direction of current through inductive coil L H  as quickly as possible. Then, after the time delay of time delay devices TD 1  and TD 2 , current Iw is drawn from voltage source node V 1  instead of voltage source node V 2  to reduce the voltages at head nodes H 1  and H 2  and thus the power consumption of magnetic write circuit  30 . 
     FIG. 4 shows a circuit schematic diagram of a third embodiment of a magnetic write circuit  40  of the present invention. Magnetic write circuit  40  is part of a disk drive system and controls the magnitude and direction of current through a magnetic write head  41  represented in the diagram as an inductive coil L H . Magnetic write head  41 , which is coupled into the remainder of the circuit between circuit head nodes H 1  and H 2 , includes inductive coil L H  along with magnetic material positioned in magnetic fields generated by current therethrough. Magnetic write circuit  40  includes writer circuit  42 , power supply circuit  44 , input signal circuit nodes WDX and WDY, the circuit head nodes H 1  and H 2  previously mentioned, and voltage source nodes V 1 , V 2 , and GND (where a significantly higher voltage is provided at voltage source node V 2  than at voltage source node V 1 ). Magnetic write circuit  40  is preferably fabricated in an integrated circuit. 
     Writer circuit  42  is identical to writer circuit  32  of magnetic write circuit  30 . Power supply circuit  44 , however, differs from power supply circuit  34  of magnetic write circuit  30  in that transistors Q 3  and Q 4  are replaced by transistors M 3  and M 4 . Transistors M 3  and M 4  are PMOS transistors each having a gate, a source, and a drain. Similar to the pnp bipolar junction transistors of power supply circuit  34  that use a low voltage at the base to turn the transistor on and a high voltage at the base to turn the transistor off, the PMOS transistors of power supply circuit  44  use a low voltage at the gate to turn the transistor on and a high voltage at the gate to turn the transistor off. Transistor M 3  has its source connected to voltage source node V 2 , its gate connected to the output node of amplifier A 5 , and its drain connected to the collector of switching transistor Q 1 . Transistor M 4  has its source connected to voltage source node V 2 , its gate connected to the output node of amplifier A 6 , and its drain connected to the collector of switching transistor Q 2 . 
     When transistor M 3  is turned on, the voltage at the collector of switching transistor Q 1  (which is equal to the voltage at the drain of transistor M 3 ) is approximately V 2 −VSD (where VSD is the voltage drop across the source-drain junction of transistor M 3 ). When transistor M 3  is turned off, the voltage at the collector of switching transistor Q 1  is approximately V 1 −VD (where VD is the voltage drop across diode D 1  when turned on). Similarly, when transistor M 4  is turned on, the voltage at the collector of switching transistor Q 2  (which is equal to the voltage at the drain of transistor M 4 ) is approximately V 2 −VSD (where VSD is the voltage drop across the source-drain junction of transistor M 4 ). When transistor M 4  is turned off, the voltage at the collector of switching transistor Q 2  is approximately V 1 −VD (where VD is the voltage drop across diode D 2  when turned on). Therefore, magnetic write circuit  40  creates a maximum voltage drop of approximately V 2 −VSD volts across inductive coil L H  at the beginning of an input situation to reverse the direction of current through inductive coil L H  as quickly as possible. Then, after the time delay of time delay devices TD 1  and TD 2 , current Iw is drawn from voltage source node V 1  instead of voltage source node V 2  to reduce the voltages at head nodes H 1  and H 2  and thus the power consumption of magnetic write circuit  40 . 
     In summary, the present invention introduces a magnetic write circuit that maximizes the head swing voltage while minimizing the power consumption of the circuit. By utilizing a pulse-mode power supply circuit, the magnetic write circuit takes advantage of a higher supply voltage source to maximize the head swing voltage at the beginning of an input situation, and then draws current from a lower supply voltage source for the remainder of the input situation to minimize the power consumption of the circuit. 
     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.