Abstract:
A method for operating a memory, which includes analog memory cells, includes encoding data with an Error Correction Code (ECC) that is representable by a plurality of equations. The encoded data is stored in a group of the analog memory cells by writing respective input storage values to the memory cells in the group. Multiple sets of output storage values are read from the memory cells in the group using one or more different, respective read parameters for each set. Numbers of the equations, which are satisfied by the respective sets of the output storage values, are determined. A preferred setting of the read parameters is identified responsively to the respective numbers of the satisfied equations. The memory is operated on using the preferred setting of the read parameters.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Patent Application 61/026,150, filed Feb. 5, 2008, whose disclosure is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to memory devices, and particularly to methods and systems for adjusting parameters that are used for reading data from analog memory cells. 
     BACKGROUND OF THE INVENTION 
     Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits. 
     Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states. 
     Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells. 
     Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24 th  International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference. 
     Data is typically read from a group of memory cells by comparing the storage values of the cells to one or more read thresholds. Various methods and systems for setting the values of read thresholds are known in the art. For example, U.S. Patent Application Publication 2007/0091677, whose disclosure is incorporated herein by reference, describes methods for reading data from one or more Flash memory cells and for recovering from read errors. In some embodiments, in the event of an error correction failure by an error detection and correction module, the Flash memory cells are re-read at least once using one or more modified reference voltages, until successful error correction may be carried out. In some embodiments, after successful error correction, a subsequent read request is handled without re-writing data to the Flash memory cells in the interim 
     U.S. Pat. No. 6,963,505, whose disclosure is incorporated herein by reference, describes methods for determining a reference voltage. In some embodiments, a set of operating reference cells is established to be used in operating cells in a Non-Volatile Memory (NVM) block or array. At least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other. For each set of test reference cells, a read error rate may be determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating other cells, outside the subset of cells, in the NVM block or array. 
     SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a method for operating a memory that includes analog memory cells, the method including: 
     encoding data with an Error Correction Code (ECC), which is representable by a plurality of equations; 
     storing the encoded data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group; 
     reading from the memory cells in the group multiple sets of output storage values using one or more different, respective read parameters for each set; 
     determining respective numbers of the equations that are satisfied by the sets of the output storage values; 
     identifying a preferred setting of the read parameters responsively to the respective numbers of the satisfied equations; and 
     operating on the memory using the preferred setting of the read parameters. 
     In some embodiments, the read parameters include read thresholds, and operating on the memory cells includes reading the memory cells using the preferred setting of the read thresholds. Additionally or alternatively, the read parameters include cross-coupling coefficients, and operating on the memory includes canceling cross-coupling interference in the output storage values using the preferred setting of the cross-coupling coefficients. In a disclosed embodiment, the ECC includes a binary ECC and the equations include Boolean equations. In an embodiment, the ECC includes a linear ECC and the equations include parity check equations. 
     In an embodiment, identifying the preferred setting includes selecting the one or more read parameters that correspond to a set of the output storage values that satisfies a maximum number of the equations. Operating on the memory may include processing a set of the output storage values read using the preferred setting of the read parameters so as to decode the ECC. In some embodiments, a number of the satisfied equations at the preferred setting of the read parameters is less than a total number of the equations in the plurality. In an alternative embodiment, identifying the preferred setting includes selecting the setting of the read parameters at which all of the equations in the plurality are satisfied. 
     In some embodiments, reading the sets of the output storage values includes attempting to decode the ECC responsively to each of the sets of the output storage values. In an embodiment, identifying the preferred setting includes selecting the setting of the read parameters at which the ECC is decoded successfully. In another embodiment, attempting to decode the ECC includes modifying the sets of the output storage values to produce respective modified sets of the output storage values, and identifying the preferred setting includes selecting the preferred setting responsively to respective modified numbers of the equations that are satisfied by the modified sets of the output storage values. In yet another embodiment, attempting to decode the ECC includes attempting to decode the ECC responsively to a given set of the output storage values only when a number of the equations satisfied by the output storage values in the given set is less than a predefined value. 
     In a disclosed embodiment, reading the sets of the output storage values includes reading a first set of the output storage values using a given setting of the read parameters, adjusting at least one of the read parameters in a given direction, reading a second set of the output storage values using the adjusted read parameters, making a comparison between a first number of the equations satisfied by the first set of the output storage values and a second number of the equations satisfied by the second set of the output storage values, and, responsively to the comparison, determining whether to reverse the given direction for reading at least one subsequent set of the output storage values. 
     In another embodiment, reading the output storage values includes determining soft metrics for at least some of the read output storage values, determining the numbers of the satisfied equations includes computing, based on the soft metrics, respective reliability measures of the equations with respect to each of the sets of the output storage values, and identifying the preferred setting of the read parameters includes selecting the preferred setting based on the reliability measures of the equations. 
     In yet another embodiment, reading the output storage values includes determining Log Likelihood Ratios (LLRs) for at least some of the read output storage values, determining the numbers of the satisfied equations includes substituting respective signs of the LLRs into the equations, and identifying the preferred setting of the read parameters includes selecting the preferred setting based on the numbers of the equations that are satisfied when the signs of the LLRs are substituted therein. In some embodiments, the reading parameters include a time that elapsed since the encoded data was stored in the group of the memory cells and/or a statistical property of a noise that distorts the output storage values. 
     In some embodiments, the memory cells are included in a memory device, and the preferred setting is identified at a controller that is separate from the memory device. Identifying the preferred setting may include sending from the controller to the memory device a command to apply the preferred setting. In an embodiment, identifying the preferred setting includes sending from the controller to the memory device a notification related to a given set of the output storage values, so as to cause the memory device to read another set of the output storage values. Sending the notification may include indicating to the memory device a failure to decode the ECC based on the given set of the output storage values. 
     There is additionally provided, in accordance with an embodiment of the present invention, apparatus for operating a memory that includes analog memory cells, the apparatus including: 
     an Error Correction Code (ECC) module, which is operative to encode data with an ECC, which is representable by a plurality of equations; and 
     circuitry, which is coupled to store the encoded data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group, to read from the memory cells in the group multiple sets of output storage values using one or more different, respective read parameters for each set, to determine respective numbers of the equations that are satisfied by the sets of the output storage values, to identify a preferred setting of the read parameters responsively to the respective numbers of the satisfied equations, and to operate on the memory using the preferred setting of the read parameters. 
     There is also provided, in accordance with an embodiment of the present invention, apparatus, including: 
     a memory, including multiple analog memory cells; and 
     circuitry, which is operative to encode data with an Error Correction Code (ECC), which is representable by a plurality of equations, to store the encoded data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group, to read from the memory cells in the group multiple sets of output storage values using one or more different, respective read parameters for each set, to determine respective numbers of the equations that are satisfied by the sets of the output storage values, to identify a preferred setting of the read parameters responsively to the respective numbers of the satisfied equations, and to operate on the memory using the preferred setting of the read parameters. 
     The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram that schematically illustrates a memory system, in accordance with an embodiment of the present invention; 
         FIG. 2  is a graph showing a dependence of the number of satisfied parity check equations on read threshold position, in accordance with an embodiment of the present invention; 
         FIG. 3  is a flow chart that schematically illustrates a method for adjusting read thresholds, in accordance with an embodiment of the present invention; and 
         FIG. 4  is a graph showing storage value distributions and read thresholds, in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Overview 
     Analog memory cell devices often read data from the memory cells by setting certain reading parameters, and then reading the memory cells using these parameters. Reading parameters may comprise, for example, read thresholds to which the storage values of the memory cells are compared. Accurate setting of the read threshold values is important for achieving high performance, particularly in Multi-Level Cell (MLC) devices that store multiple bits per cell. The read threshold positions typically have a strong effect on the number of read errors that occur. Other sorts of reading parameters may comprise, for example, cross-coupling coefficients that are used for canceling cross-coupling interference between memory cells. 
     In many analog memory cell devices, the data stored in the memory cells is encoded with an Error Correction Code (ECC). Typically, a block of k data bits is encoded to produce an ECC code word having n encoded bits, n&gt;k. The encoded bits are then stored in a group of analog memory cells by writing storage values to the cells. The code word is retrieved from memory by comparing the storage values of the analog memory cells in the group to one or more read thresholds. In practice, some of the retrieved bits in the code word may be erroneous due to various impairments. The ECC may or may not be able to correct these errors, depending on the number of erroneous bits in the code word. In many practical cases, the number of erroneous bits per code word depends on the reading parameters used for reading the memory cells. Therefore, it is important to set and maintain the reading parameters at the appropriate values. 
     Embodiments of the present invention provide improved methods and systems for determining and setting reading parameters (such as read thresholds or cross-coupling coefficients) in analog memory cells that store ECC-encoded data. The disclosed methods and systems use a representation of the ECC as a set of logical equations, such that a vector of n bits is considered a valid code word if and only if it satisfies the entire equation set. When the ECC comprises a linear code, the equations typically comprise parity check equations, i.e., exclusive OR (XOR) operations applied to selected subsets of encoded bits. When a given code word is read from the analog memory cells using a certain set of read thresholds, the methods and systems described herein use the number of the equations that are satisfied by the retrieved code word as a measure of the distance of the reading parameters from their optimal values. 
     In some embodiments, a given code word is read from the analog memory cells using different settings of the reading parameters. For each setting of the reading parameters being evaluated, the retrieved encoded bits satisfy a certain number of equations. A preferred setting of the reading parameters is identified and used for subsequent operations on the memory cells. Typically, the preferred setting maximizes the number of satisfied Boolean equations. In some embodiments, the preferred setting is determined in an iterative process that adjusts the reading parameters and attempts to gradually increase the number of satisfied equations. 
     The number of satisfied equations is a sensitive and powerful indication, as opposed to the mere success or failure of ECC decoding. One important benefit of using this indication is that the disclosed methods do not rely on successful decoding of the ECC. The number of satisfied equations can be determined and maximized without ever converging to a valid code word or even reaching a correctable number of erroneous bits. Unlike some known methods that adjust the reading parameters until the ECC is decoded successfully, the methods and systems described herein are able to determine the preferred setting of the reading parameters even if the resulting code word is not decodable at these positions. As such, the disclosed methods and systems are particularly effective in high-distortion conditions. 
     In some embodiments, full ECC decoding is not attempted for each evaluated setting of the reading parameters. For example, the memory controller may count the number of satisfied equations at each setting being evaluated, and perform full decoding of the ECC code word only at the preferred setting. Refraining from performing full ECC decoding for each setting reduces the time, computational complexity and current consumption of the reading process. 
     System Description 
       FIG. 1  is a block diagram that schematically illustrates a memory system  20 , in accordance with an embodiment of the present invention. System  20  can be used in various host systems and devices, such as in computing devices, cellular phones or other communication terminals, removable memory modules (“disk-on-key” devices), Solid State Disks (SSD), digital cameras, music and other media players and/or any other system or device in which data is stored and retrieved. 
     System  20  comprises a memory controller  24 , which stores data in a memory device  28  comprising a memory cell array  32 . The memory controller and memory device communicate over a suitable interface, such as a bus interface. The memory cell array comprises multiple analog memory cells  36 , in which the data is stored. In the context of the present patent application and in the claims, the term “analog memory cell” is used to describe any memory cell that holds a continuous, analog value of a physical parameter, such as an electrical voltage or charge. Array  28  may comprise analog memory cells of any kind, such as, for example, NAND, NOR and CTF Flash cells, PCM, NROM, FRAM, MRAM and DRAM cells. Memory cells  36  may comprise Single-Level Cells (SLC) or Multi-Level Cells (MLC, also referred to as multi-bit cells). 
     The charge levels stored in the cells and/or the analog voltages or currents written into and read out of the cells are referred to herein collectively as analog values or storage values. Although the embodiments described herein mainly address threshold voltages, the methods and systems described herein may be used with any other suitable kind of storage values. 
     System  20  stores data in the analog memory cells by programming the cells to assume respective memory states, which are also referred to as programming levels. The programming levels are selected from a finite set of possible levels, and each level corresponds to a certain nominal storage value. For example, a 2 bit/cell MLC can be programmed to assume one of four possible programming levels by writing one of four possible nominal storage values to the cell. 
     Memory device  28  comprises a reading/writing (R/W) unit  40 , which converts data for storage in the memory device to storage values and writes them into memory cells  36 . In alternative embodiments, the R/W unit does not perform the conversion, but is provided with voltage samples, i.e., with the storage values for storage in the cells. The R/W unit typically (although not necessarily) programs the cells using an iterative Program and Verify (P&amp;V) process, as is known in the art. When reading data out of array  32 , R/W unit  40  converts the storage values of memory cells  36  into digital samples having a resolution of one or more bits. Data is typically written to and read from the memory cells in groups that are referred to as pages. 
     Memory controller  24  comprises an ECC encoder/decoder  48 , which encodes the data with an Error Correction Code (ECC) before sending the data to device  28  for storage, and decodes the ECC when retrieving data from device  28 . Encoder/decoder  48  may apply any suitable type of ECC. The description that follows sometimes refers separately to an ECC encoder and/or to an ECC decoder, regardless of whether the encoder and decoder are implemented in a single unit or in separate units. The ECC applied by encoder/decoder  48  is represented by a set of logical equations, such as parity check equations. Methods and systems that are described below use these equations to estimate and adjust various reading parameters, such as read thresholds or cross-coupling coefficients, for reading memory cells  36 . 
     The memory controller further comprises a processor  52 , which controls the storage and retrieval of data in device  28 . In particular, processor  52  controls ECC encoder/decoder  48  and R/W unit  40 . Memory controller  24  communicates with a host  30 , for accepting data for storage in the memory device and for outputting data retrieved from the memory device. The different elements of controller  24  may be implemented in hardware. Alternatively, the memory controller may comprise a microprocessor that runs suitable software, or a combination of hardware and software elements. 
     The configuration of  FIG. 1  is an exemplary system configuration, which is shown purely for the sake of conceptual clarity. Any other suitable memory system configuration can also be used. Elements that are not necessary for understanding the principles of the present invention, such as various interfaces, addressing circuits, timing and sequencing circuits and debugging circuits, have been omitted from the figure for clarity. 
     In the exemplary system configuration shown in  FIG. 1 , memory device  28  and memory controller  24  are implemented as two separate Integrated Circuits (ICs). In alternative embodiments, however, the memory device and the memory controller may be integrated on separate semiconductor dies in a single Multi-Chip Package (MCP) or System on Chip (SoC). Further alternatively, some or all of the memory controller&#39;s circuitry may reside on the same die on which the memory array is disposed. Further alternatively, some or all of the functionality of the memory controller can be implemented in software and carried out by a processor or other element of the host system. In some implementations, a single memory controller  24  may be connected to multiple memory devices  28 . In yet another embodiment, some or all of the memory controller&#39;s functionality may be carried out by a separate unit, referred to as a memory extension, which acts as a slave of memory device  28 . 
     Typically, processor  52  comprises a general-purpose processor, which is programmed in software to carry out the functions described herein. The software may be downloaded to the processor in electronic form, over a network, for example, or it may, alternatively or additionally, be provided and/or stored on tangible media, such as magnetic, optical, or electronic memory. 
     Memory cells  36  of array  32  are typically arranged in a grid having multiple rows and columns, commonly referred to as word lines and bit lines, respectively. The array is typically divided into multiple pages, i.e., groups of memory cells that are programmed and read simultaneously. Cells are typically erased in groups of word lines that are referred to as erasure blocks. 
     Using Parity Check Equations for Setting Reading Parameters 
     Memory controller  24  encodes the data to be stored in memory device  28  with an ECC. In a typical flow, encoder/decoder  48  encodes blocks of k data bits to produce respective ECC code words having n encoded bits each, n&gt;k. The encoded bits are then stored in the analog memory cells of device  28  by writing the appropriate storage values to the cells. Typically although not necessarily, each ECC code word corresponds to a memory page stored in the memory device. When retrieving data from the memory device, the storage values corresponding to a given code word are read from the cells using a certain setting of reading parameters. The description that follows initially addresses read thresholds. Other kinds of reading parameters are addressed further below. 
     The read storage values correspond to the respective encoded bits of the code word. In practice, however, some of the read storage values may differ from the corresponding written storage values due to various impairments. In other words, some of the encoded bits read from the memory device may be erroneous. Encoder/decoder  48  decodes each ECC code word, so as to reconstruct the data bits. A given ECC usually has a certain correction capability, i.e., a maximum number of erroneous encoded bits per code word that can be corrected by the code. If the number of erroneous encoded bits in a given code word does not exceed the correction capability of the ECC, the code word can be decoded successfully. Otherwise, the decoding operation may fail. 
     The ECC applied by encoder/decoder  48  is represented by a set of Boolean equations. Each Boolean equation is defined over a subset of the encoded bits in the code word. The encoded bits of a valid code word satisfy all the equations in the set, and vice versa (i.e., if at least one equation in the set is not satisfied, the code word is not valid). 
     When the ECC comprises a linear ECC, the Boolean equations comprise linear equations that are commonly referred to as parity check equations. Typically, each parity check equation defines an exclusive OR (XOR) operation among a selected subset of the encoded bits in the code word. The equation is satisfied if and only if the XOR result is “0”. The parity check equations are commonly arranged in a matrix, which is referred to as a parity check matrix. Parity check matrices are described, for example, by Blahut in “Theory and Practice of Error Control Codes,” Addison-Wesley, May, 1984, section 3.2, pages 47-48, which is incorporated herein by reference. 
     Although the description that follows focuses on linear codes and on parity check equations, the methods and systems described herein are similarly applicable to any other suitable type of ECC and any other suitable type of Boolean equations. A linear ECC that is represented by a set of parity check equations may comprise, for example, a Low Density Parity Check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Reed-Solomon (RS) code or a Hamming code. Although the embodiments described herein refer to codes that are represented by sets of Boolean equations, the principles of the present invention can also be used with codes that are defined over non-binary symbols, and which are represented by logical equations that are not necessarily Boolean. For example, a Reed-Solomon code can be defined over 8-bit symbols having 256 possible values. Code words of this code, which comprise multiple 8-bit symbols, satisfy linear equations over a finite field. The methods and systems described herein can also be used with these sorts of codes, e.g., to adjust read thresholds based on the number of non-Boolean logical equations that are satisfied by a given non-binary code word. 
     As noted above, when the storage values read from memory cells  36  are distorted by various impairments, some of the encoded bits in a given retrieved code word may be erroneous. In such cases, not all of the parity check equations that represent the ECC are satisfied by the code word. Nevertheless, in some cases a certain number of parity check equations may still be satisfied, even though the code word contains erroneous encoded bits. This scenario is especially likely to occur in codes having sparse parity check equations, i.e., equations that are defined over relatively small subsets of the encoded bits. LDPC is a typical example of an ECC having sparse parity check equations. 
     In some cases, errors in the encoded bits retrieved from memory cells  36  may be caused by non-optimal positioning of the read thresholds that are used to read the cells. An example of read thresholds that are used for reading a group of analog memory cells is shown in  FIG. 4  below. It can be shown that the number of parity check equations that are satisfied by a given retrieved code word is often indicative of the distance of the read thresholds used to read the cells from their optimal values. This relationship holds especially for small offsets from the optimal threshold positions, although it may hold to some extent for large deviations, as well. 
     Some embodiments of the present invention provide methods and systems for adjusting or selecting read threshold values based on counting the number of satisfied parity check equations. Typically, the methods and systems described herein identify preferred threshold positions, which maximize the number of satisfied equations. 
       FIG. 2  is a graph showing a dependence of the number of satisfied parity check equations on read threshold position, in accordance with an embodiment of the present invention. The graph of  FIG. 2  considers a certain ECC code word that is stored in cells  36 , and is read using different read thresholds. For each read threshold position, the retrieved code word will satisfy a certain number of parity check equations. A plot  60  shows the number of satisfied parity check equations as a function of the read threshold position. As can be seen in the figure, the number of satisfied equations reaches a maximum denoted N_MAX when the read threshold is positioned at an optimal value denoted TH_OPT. When the read threshold deviates from its optimal position in either direction, the number of satisfied parity check equations decreases monotonically. This monotonic relationship holds at least within a certain interval around the optimal threshold position. 
     Note that in some cases N_MAX may still be less than the total number of parity check equations. In other words, the read operation may sometimes produce erroneous encoded bits even if the read threshold position is optimal. Encoder/decoder  48  may or may not be able to correct these errors, depending on whether their number exceeds the correction capability of the ECC. The methods and systems described herein thus enable the memory controller to adjust the read thresholds to their preferred positions even though the code words retrieved using these read thresholds may not be decodable. 
     The description above referred to the use of a single read threshold, such as being used in 1 bit/cell SLC devices. This choice was made, however, purely for the sake of conceptual clarity. The methods and systems described herein can similarly be used for retrieving data using a set of multiple read thresholds, such as in MLC devices. 
       FIG. 3  is a flow chart that schematically illustrates a method for adjusting read thresholds, in accordance with an embodiment of the present invention. The method begins with system  20  initializing the read thresholds that are used for reading data from memory cells  36  to certain initial values, at an initialization step  70 . Memory controller  24  reads a memory page from memory device  28 , at a reading step  74 . In the present example, the page holds the encoded bits of a certain ECC code word that was stored previously. When instructed by processor  52  of the memory controller, R/W unit  40  reads the memory cells using the initial read thresholds. 
     Processor  52  counts the number of parity check equations that are satisfied by the encoded bits read using the initial read thresholds, at an equation counting step  78 . The processor checks whether the number of satisfied equations indicates that the read thresholds are at their preferred values, at a threshold optimum checking step  82 . If processor  52  determines that the read thresholds are positioned at the preferred positions, the method terminates, at a termination step  86 . 
     Otherwise, the processor adjusts the read thresholds by a certain increment in a certain direction, at a threshold adjustment step  90 . The initial direction of the threshold adjustment may be arbitrary or predefined. Processor  52  then instructs the memory device to re-read the memory page (the code word) using the adjusted read thresholds, at a re-reading step  94 . The processor re-counts the number of satisfied parity check equations, at an equation re-counting step  98 . The re-counted number of parity check equations corresponds to the adjusted positions of the read thresholds. 
     Processor  52  now checks whether the number of satisfied parity check equations has increased as a result of the read threshold adjustment, at an increase checking step  102 . If the number increased, the processor concludes that the direction in which the read thresholds were adjusted is correct, and the method loops back to step  82  above. The adjustment process continues in the same direction until the read thresholds reach their preferred values. 
     If, on the other hand, increase checking step  102  shows that the number of satisfied equations has decreased as a result of the read threshold adjustment, processor  52  concludes that the direction in which the read thresholds were adjusted is incorrect. The processor therefore reverses the direction of threshold adjustment, at a direction reversal step  106 . The method loops back to step  82  above, and the adjustment process proceeds in the opposite direction. The method terminates at step  86  when the read thresholds converge to the preferred positions, which maximize the number of satisfied parity check equations. 
     In some embodiments, the adjustment increment from one threshold position to the next (the increment applied at step  90 ) is constant. In alternative embodiments, the increment may be variable. For example, the increment may depend on the difference in the number of satisfied equations between previous iterations. In other words, if the number of satisfied equations increased considerably in the previous iteration, then the processor may apply a large increment in the next iteration, and vice versa. Alternatively, the increment size may be adapted in accordance with any other suitable logic. 
     When multiple read thresholds are used (e.g., in MLC devices), the method of  FIG. 3  can be applied jointly to all the read thresholds, to a selected subset of the read thresholds, or to each read threshold individually. 
     In the embodiment of  FIG. 3 , the read threshold position is adjusted incrementally in order to maximize the number of satisfied equations. In an alternative embodiment, system  20  may use a number (e.g., 4) of predefined sets of read thresholds, which cover the expected range of read threshold positions. Memory controller  24  and/or R/W unit  40  may attempt to read the page with each of the predefined threshold sets, and choose the set corresponding to the largest number of satisfied equations. As in the iterative process of  FIG. 3 , the system may choose the first attempted set that produces a tolerable number of satisfied equations (e.g., the first set for which ECC decoding is successful) or it may scan all sets and choose the set that maximizes the number of satisfied equations. 
     In some embodiments, such as in LDPC codes, evaluation of the parity check equations is an integral part of the decoding process performed by encoder/decoder  48  in the memory controller. In such embodiments, the methods and systems described herein can be implemented without incurring additional hardware and the associated cost and size. 
     In some embodiments, the memory controller decodes the ECC code word at each iteration, i.e., for each evaluated read threshold position, and the method terminates when ECC decoding is successful. The success or failure in decoding the code word can be used as the termination criterion at step  82  above. 
     In alternative embodiments, the memory controller does not decode the ECC code word for each evaluated read threshold position, but only at step  86 , upon reaching the threshold position that maximizes the number of satisfied parity check equations. This technique reduces the computational complexity and power consumption of the threshold adjustment process considerably. 
     Further alternatively, the memory controller may attempt to decode the ECC code word according to various other conditions, such as when the number of satisfied parity check equations falls below a certain value. In these embodiments, as long as the number of satisfied equations is above a certain number, ECC decoding is not attempted. In other words, the number of satisfied equations can be used to predict, before attempting to decode the code word, whether or not the ECC decoding process is likely to succeed. If the number of satisfied equations is relatively small, then ECC decoding may not be attempted, thus saving time and other resources. If ECC decoding is predicted to fail, other measures can be taken, such as adjusting the read thresholds or re-reading the page. 
     In some embodiments, the decoding process performed by encoder/decoder  48  comprises an iterative process, which begins with the encoded bits retrieved from cells  36  and attempts to modify them in order to gradually increase the number of satisfied parity check equations. Such iterative decoding processes are used, for example, in LDPC decoders. In these embodiments, the method of  FIG. 3  can be applied to the number of satisfied equations at the end of the iterative decoding process. 
     In other words, encoder/decoder  48  may attempt to decode the ECC code word for each evaluated read threshold position using the iterative decoding process. For each evaluated read threshold position, processor  52  may count the number of parity check equations that are satisfied at the end of the iterative decoding process. The read threshold position at which this number of satisfied equations is maximized is regarded as the optimum position, irrespective of whether the code word is decoded successfully or not. 
     Moreover, the methods described herein can be applied to the number of satisfied equations following the decoding process, whether or not the decoding process is iterative or not. In other words, encoder/decoder  48  may attempt to decode the ECC for each evaluated threshold position using any suitable ECC decoding process. These attempts will generally reduce the number of erroneous bits, although ECC decoding may not always succeed. Processor  52  may select the appropriate read threshold position based on the number of satisfied parity check equations after ECC decoding. 
     In some embodiments, the threshold setting methods described herein can be combined with other threshold setting processes, so as to adjust the read thresholds based on the number of satisfied parity check equations and on other criteria. Some threshold setting methods that can be used for this purpose are described, for example, in PCT International Publications WO/2008/053472 and WO/2008/111058, whose disclosures are incorporated herein by reference. Combining multiple threshold setting criteria may provide higher accuracy and/or a smaller number of iterations. 
     In some embodiments, encoder/decoder  48  receives soft metrics that correspond to the encoded bits, and uses these metrics in decoding the code word. The soft metric of a given encoded bit is typically indicative of the confidence level associated with this bit, or the likelihood of this bit to be erroneous. Soft metrics may comprise, for example, Log Likelihood Ratios (LLRs) of the encoded bits. In these embodiments, each parity check equation may be assigned a reliability measure, which depends on the soft metrics of the encoded bits that appear in the equation. The reliability measure of a given equation is indicative of the likelihood that this equation is satisfied. 
     The method of  FIG. 3  can be used to find the read threshold position that maximizes the sum of soft reliability measures over the different parity check equations. In other words, for each evaluated read threshold position, processor  52  computes the sum of the soft reliability measures of the different parity check equations. The read threshold position at which the cumulative reliability measure is maximized is regarded as the optimum position. 
     When using LLRs, the sign of an LLR of a given bit can be used as an interim hard decision. In some embodiments, processor  52  may substitute the signs of the LLRs of the encoded bits into the parity check equations, and count the number of satisfied equations by the LLR signs. 
     In the description above, the preferred read thresholds determined for a given group of memory cells are used for reading data from the same group of cells. In alternative embodiments, however, the preferred read thresholds can be used for reading data from a different group of memory cells, such as cells in a different word line or block. 
       FIG. 4  is a graph showing storage value distributions and read thresholds, in accordance with an embodiment of the present invention. The example of  FIG. 4  shows three storage value distributions  110 , which correspond to three programming levels. Each programming level represents a data value stored in the memory cells. In order to read the data stored in the memory cells, read thresholds  114  are positioned between adjacent distributions. If the read thresholds are positioned properly, the probability of a read storage value falling on the wrong side of a threshold (and thus causing a read error) is small. Note that in the example of  FIG. 4 , adjacent distributions have a certain overlap. In such cases, some read errors will occur. Assuming the number of read errors is sufficiently small, the errors can be corrected by the ECC. 
     Alternative Reading Parameters 
     The description above focused on the setting of read thresholds based on the number of satisfied Boolean equations. In alternative embodiments, the methods and systems described herein can be used to adjust or set various other sorts of parameters that are related to reading data from memory cells  36 . 
     For example, the memory controller may adjust cross-coupling coefficients, which are used for canceling cross-coupling interference in the storage values read from memory cells  36 , based on the number of satisfied parity check equations. In some cases the storage values stored in memory cells  36  are distorted by cross-coupling interference from other memory cells. In some embodiments, memory controller  24  applies an interference cancellation process for canceling the cross-coupling interference in the storage values read from memory cells  36 . The memory controller may use any suitable interference cancellation method. Several examples of interference cancellation methods are described in PCT International Publications WO 2007/132453, WO 2007/132457 and WO 2008/026203, whose disclosures are incorporated herein by reference. 
     In some cross-coupling cancellation methods, the memory controller estimates the cross-coupling coefficients, i.e., the coupling ratios between memory cells, and then estimates and cancels the interference in a given cell based on the storage values of the other cells and on the estimated cross-coupling coefficients. As can be appreciated, accurate estimation of the cross-coupling coefficients is important for effectively cancelling the cross-coupling interference. 
     In particular, when the memory controller applies interference cancellation to a certain read code word prior to ECC decoding, the number of satisfied parity check equations may depend on the accuracy of the cross-coupling coefficients used in the cancellation process. Thus, the number of satisfied equations can be used as an indication of the accuracy of the cross-coupling coefficient. In some embodiments, the memory controller applies a process, similar to the method of  FIG. 3  above, for adjusting the cross-coupling coefficient values based on the number of satisfied equations. Typically, the process attempts to find the cross-coupling coefficient values that maximize the number of satisfied equations. 
     In some embodiments, the memory controller adjusts certain reading parameters that are related to the positions of the read thresholds, rather than adjusting the read thresholds directly. For example, when multiple read thresholds are used, the optimal position of each read threshold may shift over time in accordance with a certain known behavior. Different read thresholds may exhibit different shifts as a function of time. In such cases, the memory controller may regard the time that elapsed since the memory cells were programmed as a reading parameter, and track its value based on the number of satisfied parity check equations. Once the elapsed time period is estimated, the different read thresholds can be positioned accordingly. 
     Yet another example of reading parameters that can be estimated based on the parity check equations involves estimating the statistical properties of noise that distorts the encoded bits read from the memory. When the noise can be assumed or approximated to be Gaussian, the estimated statistical property may comprise a variance or standard deviation of the noise. Estimates of the noise standard deviation is used, for example, as part of the LLR calculation in soft decoding of LDPC codes, as well as other types of ECC. In some embodiments, processor  52  can estimate the Gaussian noise standard deviation by counting the number of unsatisfied equations. When the code word is read using the optimal read threshold positions, the number of unsatisfied equations is indicative of the noise amplitude. In some embodiments, the processor may hold a predefined look-up table that provides the noise variance (or standard deviation) as a function of the number of unsatisfied equations. During operation, the number of unsatisfied equations can be counted, and the noise standard deviation can be estimated by querying the lookup table. Alternatively, the processor may estimate any other suitable statistical property of the noise that distorts the read encoded bits based on the number of satisfied equations. 
     In some embodiments, the memory controller and the memory device support a command interface, which comprises at least one command for carrying out the parameter setting (e.g., threshold adjustment) processes described herein. For example, the command interface may comprise a command from the memory controller to the memory device, instructing the memory device to shift one or more read thresholds (or other reading parameters) or to set their values. As another example, the interface may comprise a command in which the memory controller reports to the memory device that ECC decoding has failed, or that the number of satisfied equations is not yet high enough. In response to such a command, the memory device may shift one or more read thresholds and re-read the code word. 
     Although the embodiments described herein mainly address data storage applications, the principles of the present invention can also be used in communication systems. For example, a communication receiver may receive a modulated signal, which carries ECC code words. The signal may be modulated using any suitable modulation, such as Pulse Amplitude Modulation (PAM) or Quadrature Amplitude Modulation (QAM). The receiver may receive the signal using a certain adaptive loop, such as a carrier recovery (phase recovery) loop, a timing recovery loop or an Automatic Frequency Control (AFC) loop. The receiver may receive a given code word, count the number of satisfied parity check equations, and adapt the loop using feedback that is derived from the number of satisfied equations. 
     It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.