Abstract:
The present invention provides an energy recovering driver that includes a pull-up control, a pull-down control and a transmission gate. The pull up control is responsive to a pull-up control signal and a clock signal to turn the transmission gate ON and OFF and predetermined positions of the clock signal. The pull-down control is responsive to a pull-down control signal and the clock signal to turn the transmission gate ON and OFF at other predetermined locations of the clock signal. The transmission gate transmits the clock signal when at an ON condition and does not transmit the clock signal when in an OFF condition.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims priority based on U.S. Provisional Patent Application No. 60/370,901, filed Apr. 4, 2002, the entirety of which is incorporated herein by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention generally relates to a low power driver, and more particularly, the present invention relates to a low power driver with energy recovery characteristics.  
         BACKGROUND OF THE INVENTION  
         [0003]    Conventional SRAM architecture is used for on-chip quick memory access, such as with cache memories. Bit line drivers drive bit lines and word line drivers drive word lines connected to cells in the SRAM to read and write information from and to memory cells in the SRAM. When effectuating a read in such a system, a word line is energized to allow the bit lines access to connected memory cells. A pair of bit lines is pre-charged before energizing the word line. Subsequently, a voltage across the pair of bit lines, representative of the stored value, is read by a sense amplifier to effectuate the read operation. A latching circuit latches the amplified voltage and holds it available for devices to read. The word line is again charged to allow access to the desired cell in the array. Here, one bit line is charged while the other is not to effectuate the write to a cell.  
           [0004]    In such architectures, managing power dissipation has become an increasingly important goal. To this end, some computing systems have begun to use recovery or adiabatic clock circuits to recycle the clock signal pulse that is sent across the bit lines and word lines, via the bit line drivers and the word line drivers, in an attempt to reduce power consumption. While this does effectuate energy savings, some drawbacks currently exist with the present state of this technology. Specifically, such systems are commonly complex and yield clock signal waveforms that either fail to provide energy recovery characteristics, such as an abrupt or square wave, or fail to provide needed switching capabilities. The present invention was developed in light of these and other drawbacks.  
         BRIEF SUMMARY OF THE INVENTION  
         [0005]    The present invention provides an energy recovering driver that includes a pull-up control, a pull-down control and a transmission gate. The pull up control is responsive to a pull-up control signal and a clock signal to turn the transmission gate ON and OFF at predetermined positions on a cyclical clock signal. The pull-down control is responsive to a pull-down control signal and the clock signal to turn the transmission gate ON and OFF at other predetermined locations on the cyclical clock signal. The transmission gate transmits the clock signal when in an ON condition and does not transmit the clock signal when in an OFF condition. Other aspects of the invention will be apparent to those skilled in the art after reviewing the drawings and the detailed description below. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]    The present invention will now be described, by way of example, with reference to the accompanying drawings, in which:  
         [0007]    [0007]FIG. 1 is a schematic view of one aspect of an SRAM architecture according to the present invention;  
         [0008]    [0008]FIG. 2 is a schematic view of an energy recovering driver according to an aspect of the present invention;  
         [0009]    [0009]FIG. 3A is a graphic view of a wave form according to an aspect of the present invention;  
         [0010]    [0010]FIG. 3B is a graphic view of a wave form according to an aspect of the present invention;  
         [0011]    [0011]FIG. 3C is a graphic view of a wave form according to the present invention;  
         [0012]    [0012]FIG. 4A is a schematic view of an aspect of a pull-up control according to the present invention;  
         [0013]    [0013]FIG. 4B is a graphical view of the operation of the pull-up control according to the present invention;  
         [0014]    [0014]FIG. 5A is a schematic view of a pull-down control according to the present invention;  
         [0015]    [0015]FIG. 5B is a graphical view of the operation of a pull-down control according to the present invention;  
         [0016]    [0016]FIG. 6 is a graphical view of an output of an energy recovering driver according to the present invention;  
         [0017]    [0017]FIG. 7 is a graphical view of read and write operations of an SRAM architecture according to the present invention;  
         [0018]    [0018]FIG. 8 is a schematic view of a sense amplifier according to an aspect of the present invention;  
         [0019]    [0019]FIG. 9 is a schematic view of an energy recovering driver according to the present invention; and  
         [0020]    [0020]FIG. 10 is a schematic view of an energy recovering driver according to the present invention;  
         [0021]    [0021]FIG. 11 is a graphic view of a waveform according to the present invention; and  
         [0022]    [0022]FIG. 12 is a schematic view of an energy recovery memory with power clock generator according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0023]    It is to be understood that the present invention may be embodied in other specific forms without departing from its essential characteristics. The illustrated and described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.  
         [0024]    Referring now to FIG. 1, a SRAM architecture  10  according to the present invention is shown and described. SRAM architecture  10  generally includes cell array  12  having a plurality of memory cells, bit line driver  14  that drives a plurality of bit lines, sense amplifier  16 , and word line driver  18  that drives a plurality of word lines. The word line driver  18  activates or deactivates specific memory cells in the cell array  12  via energization of respective word lines, such that bit line driver  14  can effectuate read or write operations to or from any of the cells therein via respective bit lines. Sense amplifier  16  amplifies the read value on the bit lines and outputs the value to requesting external devices.  
         [0025]    Referring now to FIG. 2, an energy recovering driver  20  is shown and described. Energy recovering driver  20  can be used for bit line driver  14  or word line driver  18  in FIG. 1. The energy recovering driver generates a desired wave form along the respective word line or bit line to effectuate the operations as described above. To accomplish its desired features, energy recovering driver  20  generally includes pull-up control  22 , pull-down control  24  and transmission gate  26 . Pull-up control  22  receives pull-up control signal ch and clock signal PC. Pull-down control  24  receives pull-down control signal dch as well as clock signal PC. Transmission gate  26  includes a PMOS transistor connected to the output of the pull-up control  22  and an NMOS transistor connected to the pull-down control  24 . Of course, other arrangements are possible besides those described herein.  
         [0026]    The clock signal PC is a cyclical signal generated from a clock signal generator, and preferably is a sinusoidal or ramped clock signal. Control signals ch and dch respectively activate the pull-up control and pull-down control to turn the transmission gate  26  ON and OFF in conjunction with the clock signal PC. Pull-up control  22  outputs a zero voltage to the PMOS portion of transmission gate  26  to turn the transmission gate  26  ON and allow clock signal PC to be output to the driven load  32 , which may be the bit lines BLT (bit line true), BLF (bit line false) or the word lines WL of cell array  12 . Likewise, pull-down control  24  generates a positive voltage to the gate of NMOS transistor portion of transmission gate  26  to turn the transmission gate  26  ON to allow the clock signal PC to be output to the driven load  32 . Similar to pull-up control  22 , pull-down control  24  is dependent on clock signal PC and pull-down control signal dch.  
         [0027]    Referring now to FIGS.  3 A- 3 C, the output to load  32  is described in greater detail. FIG. 3A illustrates a situation of maximum energy recovery. Here, the sinusoidal wave transmitted to WL or BLT, BLF provide maximum energy recovery features. The driver output results when the transmission gate  26  is turned ON for the entire power clock signal PC, allowing the output to track the gradually changing power clock wave form. This approach yields high energy efficiency, since driver output changes smoothly throughout. It, however, results in the lowest operating frequency due to the short stay of the driver output at the peak value. In FIG. 3C, the output of transmission gate  26  is turned ON only at positive and negative peaks of the power clock signal PC. This yields maximum speed, since the driver output stays at its peak value for about half the clock cycle. It also results in the lowest energy efficiency due to the abruptness of the output transmissions. FIG. 3B provides an example of a preferred wave form according to the present invention. In FIG. 3B, partial gradual transitions are used to result in both high efficiency and high speed. Another advantage of this output wave form is that the driver output does not need to be pulled down to the V SS  after each operation. Therefore, energy is not dissipated during consecutive operations of the same kind.  
         [0028]    Referring now to FIGS. 4A and 4B, an embodiment of pull-up control  22  is described that, in conjunction with the later described pull-down control, results in the desired wave form of FIG. 3B. In FIG. 4A, pull-up control  22  includes invertor  34   a  and inverter  34   b . Each inverter  34   a  and  34   b  includes complimentary PMOS and NMOS transistors  36   a  and  36   b  respectively. In operation, invertor  34   a  and  34   b  are tuned to stop control signal ch from passing to the pull-up control out or output  30  when clock signal PC reaches mid-point  38  (See FIG. 3B). This zero voltage is supplied to the PMOS transistor of transmission gate  26  to turn transmission gate  26  ON and allow clock signal PC to be provided to driven load  32  such as bit lines BLT or BLF or word line WL. This effectively pulls the output  30  up to the current clock value and continues with a sloped clock signal. When clock signal PC reaches peak value  40 , invertors  34   a  and  34   b  allow control signal ch to be provided to pull-up control out or output  30  to turn the PMOS transistor of transmission gate  26  OFF. This, in turn, prohibits the clock signal PC from being provided to output load  32 . Due to the parasitic capacitance in the output load, such as in bit lines BLT, BLF or word lines WL, depending what the driver is being used for, the system voltage remains at the peak value until the pull down control  24  is turned ON, as will be described in greater detail. With reference to FIG. 4B, the pull-up control out or output  30  is shown in connection with clock signal PC. As can be seen, pull up control out or output  30  is turned OFF when midpoint  38  is reached and then turned back ON when peak value  40  is reached.  
         [0029]    Referring now to FIGS. 5A and 5B, the pull-down control  24  is described in greater detail. Pull-down control  24  includes invertors  42 A and  42 B which each have complimentary PMOS and NMOS transistors  44 A and  44 B respectively. Like before, invertors  42 A and  42 B are tuned such that, as shown in FIG. 5B, pull-down control out or output  31  is turned ON to allow control signal dch to be provided to the gate of the NMOS transistor of transmission gate  26  when downward midpoint  46  of clock signal PC is reached. Likewise, invertors  42 A and  42 B are tuned such that control signal dch is not provided through PMOS transistor  44 A and to pull-down control out or output  31  when peak minimum value  48  is reached. As such, between points  46  and  48 , transmission gate  26  is ON to allow the sloped power clock signal PC to be provided to output load  32 . Once the peak minimum value  48  is reached, then invertors  42 A and  42 B stop providing control signal dch to pull down control out or output  31 . As such, the parasitic capacitance of the system maintains the system voltage at this minimum peak value.  
         [0030]    As will be further noted, pull-up control signal ch and pull-down control dch can be provided to pull up control  22  and pull-down control  24  respectively to selectively turn transmission gate  26  ON and OFF depending on the read or write operations being conducted with the cell array  12 .  
         [0031]    The control circuitry of FIGS. 4 and 5 are similar to Schmidt triggers which return sharp transmissions from slow power clock transitions. The transition point with respect to the power clock and the pulse width can be controlled by ratioing the transistors of the first invertors  34   a  and  42 A and the stand alone PMOS  50  or NMOS  52  in a way similar to CMOS Schmidt triggers. The control signal ch and dch selectively enable the control circuitry to minimize idle power dissipation. This structure ensures correct operation of the SRAM architecture  10  for a broad range of supply voltages and operating frequencies.  
         [0032]    As the supply voltage changes, the delay through different paths changes nonlinearly causing variance in timing of the control signals. Since the PMOS and NMOS control signals of transmission gate  26  must stay in synchrony with the clock signal PC despite changes in the supply voltage, the control signal must be tolerant to the variance in the timing of the driver control signals. As shown in FIG. 6, the timing of the driver control signal ch and dch for correct driver operation are illustrated. Due to the construction of the circuitry in FIGS. 4A and 5A, the control signal dch ideally is maintained between points  54 A and  54 B while control signal ch is maintained between preferably  56 A and  56 B. This allows a wide latitude for providing the control signals for proper operation of the pull-out control  22  and pull-down control  24 . Additionally, control signals dch and ch can be operated even up to points  54 C and  54 D for dch and  56 C and  56 D for ch.  
         [0033]    Referring now to FIG. 7, application of energy recovering drivers  20  as bit line driver  14  and word line driver  18  respectively and the operation thereof is described. In the SRAM architecture according to the present invention, the clock signal PC is preferably a single phase clock signal. Write operations occur in a manner similar to conventional SRAMs. First, bit line BLF 0  storing “0” is pulled down. Then, both the word line WL 0  and the bit line BLT 0  storing “1” are pulled up storing data into one of the cells of cell array  12 .  
         [0034]    For every memory access, only one selected word line is pulled up, and all other word lines are pulled down. In conventional SRAMs, pulling down the unselected word line is not dissipative, since the V SS  level is always available. In the SRAM architecture  10  according to the present invention, however, this operation dissipates power. Since the pull down starts when the clock signal PC is above V SS , the word lines are actually pulled up above V SS  and then pulled down. Hence, in the energy recovering SRAM according to the present invention, the selected word line is preferably pulled down explicitly after each access.  
         [0035]    In read operations, since pre-charge must precede the assertion of a word line, all bit line pairs must be pre-charged low for the read to occur in a single cycle. In FIG. 7, BLT 0  and BLF 0  are set low before WL 0  is set high. After precharge, the word line WL is charged and the cell nodes of a cell in cell array  12  cause a voltage difference between each pair of bit lines BL. Pre-charging low is more energy efficient than precharging high in the present invention, since the charge pumped from the cell to the bit line BL can be recovered through the bit line driver  14 . Preferably, the sense amplifier  16  is modified to make it more sensitive for the voltage difference near V SS  as opposed to V dd .  
         [0036]    With reference to FIG. 8, the sense amplifier  16  is shown that provides the increased sensitivity for sensing voltage differences near V SS  as opposed to V dd . Specifically, in FIG. 8, sense amplifier  16  is shown including three stacked amplifiers  60   a ,  60   b  and  60   c . Amplifier  60   a  is preferably a cross-coupled sense amplifier while amplifier  60   b  and  60   c  are preferably current mirror amplifiers. Of course, it is understood that many different arrangements can be provided for sense amplifier  16  and the present invention is not limited to that disclosed herein. In FIG. 8, cross coupled sense amplifier  60   a  includes PMOS transistors  62 A and  62 B which have gates connected to bit line BLT and bit line BLF of FIG. 7. The voltages of BLT and BLF, approaching V SS  during read operations, operate the PMOS transistors to allow amplifier  60   a ,  60   b  and  60   c  to amplify the voltage difference between BLT and BLF. Latch circuit  63  latches this amplified voltage difference and outputs it for respective read operations.  
         [0037]    The energy recovering driver  20  according to the embodiments of the invention are preferably used in conjunction with a energy recovering power clock. With reference to FIG. 12, energy recovering power clock  901  is shown in conjunction with energy recovering driver  20  and storage device  903 . The storage device can be a SRAM, DRAM, NVM or display device. Such an energy recovering power clock  901  can be according to co-pending patent application entitled CLOCK SIGNAL GENERATING CIRCUIT, assigned to the assignee of the present invention and hereby incorporated by reference. The storage device supplies the clock signal PC to the driver  20 , without supplementation by power clock  901  until such a point that the signal needs additional energy. Control signal wr can be any control signal described herein including ch, dch or in, or any combination therefrom, for instructing the power clock  901  to supplement additional energy to the system as well as providing control signals to the driver  20 .  
         [0038]    Referring now to FIG. 9, another embodiment of the energy recovering driver is shown and described. In FIG. 9, an energy recovering driver  20   a  is shown which includes generally pull-up control  22 , pull-down control  24  and the transmission gate  26  as described in the previous embodiments. As before, the pull-up control  22 , the pull-down control  24  and transmission gate  26  operate to generate a clock wave form as shown in FIG. 3B. However, in addition to these components, energy recovering driver  20   a  also includes multiplexers  64   a  and  64   b  as well as feedback lines  66   a  and  66   b . In a present embodiment, the energy recovering driver  20   a  generates an output that stays at peak value for longer periods of time, making it suitable for high speed SRAM applications. Moreover, the energy recovering driver  20   a  does not switch its load unnecessarily during consecutive operations of the same kind, since its output does not need to be pulled down after each operation. Specifically, when the output  70  of energy recovering driver  20   a  is high and the pull up control  22  issues an output  30  to turn the transmission gate  26  ON, the multiplexer receives feedback via feedback line  66   a  and, based on this feedback, the multiplexer does not allow output  30  to turn transmission gate  26  ON. Therefore, the transmission gate does not pass the clock signal to the output. Likewise, when output  70  is low, transmission line  66   b  passes this value to multiplexer  64   b . As such, if output  31  of pull down control  24  is outputting a voltage to turn transmission gate  26  ON, then the multiplexer  64   b  does not allow this output  31  to pass to the transmission gate  26 .  
         [0039]    Referring now to FIG. 10, another embodiment of the energy recovering driver according to the present invention is shown and described. In FIG. 10, energy recovering driver  20   b  includes a pair of low driving pass transistors  90  and  92 , two evaluation transistors  94  and  96 , two pairs of driver activation blocks controlled by feedback from the driver output (PMOS transistor  98 , NMOS transistor  100 , NMOS transistor  102 , PMOS transistor  104 ), and a pair of invertors  106  and  108  that drive the low driving pass transistors  90  and  92 .  
         [0040]    The activation block, including transistors  98 ,  100 ,  102  and  104 , allow the energy recovering driver  20   b  output to track the clock signal PC while preventing unnecessary switching. Since the energy recovering driver  20   b  is powered by an oscillating power clock, the output of the driver also oscillates even when the driver input remains unchanged. This prevents idle switching and increases driver efficiency.  
         [0041]    Energy recovering driver  20   b  has two modes of operation depending on the level of the output of energy recovering driver  20   b . If out  110  and clock signal PC are low, the transistor  90  is turned ON to charge the driver output  110 . Since transistor  100  is turned OFF, and transistor  98  is turned ON, assuming input IN is low, a pull up path is formed from V dd  to X 1 . Thus, through invertor  106 , transistor  90  is turned ON to charge the load in an energy recovery manner. As clock signal PC and out  110  reaches full rail, transistor  98  is turned OFF and transistor  100  is turned ON pulling down X 1  to Gnd, thereby turning transistor  90  OFF. If out  110  is at high level, transistor  90  remains turned OFF regardless of IN to prevent unnecessary swing of driver output. Since transistor  98  is turned OFF and transistor  100  is turned ON, X 1  is clamped down causing transistor  90  to remain turned OFF.  
         [0042]    The driver discharge path is a dual of the driver charge path and has two modes of operation depending on the level of the driver output  110 . If out  110  and clock signal PC is high, transistor  92  is turned ON to discharge the driver  20   b  until clock signal PC and out  110  reaches its lowest peak value, assuming IN is high. If out  110  is low, transistor  92  remains turned OFF regardless of IN, preventing unnecessary dissipation.  
         [0043]    The output of the drivers, which is generally governed by overdriving transistor  90  and transistor  92  with additional voltage levels supplied into invertors  106  and  108  respectively achieves more efficient switching by providing full gradual swing of both transistors  90  and  92  at each peak of the power clock wave form PC.  
         [0044]    Referring to FIG. 11, the timing of the energy recovery driver  20   b  is shown and described. In FIG. 11, transistor  90  is turned ON at position  801  to pull the output  110  up in a fashion following the sinusoidal clock signal PC. Likewise, transistor  92  is turned OFF. Next, at position  803 , when output  110  reaches its peak, transistor  90  is turned OFF and transistor  92  is turned ON. This begins to pull the output  110  down with the clock signal PC. Then, when the output  110  reaches its minimum at  805 , transistor  92  is turned OFF and transistor  90  is turned ON to repeat the cycle.  
         [0045]    It should be noted that although the driver described in the present invention is described with use for an SRAM device, it can also be used for driving DRAM, busses, NVM (non-volatile memories), displays such as flat panel displays, or any other device in need of a driver.  
         [0046]    While the present invention has been particularly shown and described with reference to the foregoing preferred and alternative embodiments, it should be understood by those skilled in the art that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention without departing from the spirit and scope of the invention as defined in the following claims. It is intended that the following claims define the scope of the invention and that the method and apparatus within the scope of these claims and their equivalents be covered thereby. This description of the invention should be understood to include all novel and non-obvious combinations of elements described herein, and claims may be presented in this or a later application to any novel and non-obvious combination of these elements. The foregoing embodiments are illustrative, and no single feature or element is essential to all possible combinations that may be claimed in this or a later application. Where the claims recite “a” or “a first” element of the equivalent thereof, such claims should be understood to include incorporation of one or more such elements, neither requiring nor excluding two or more such elements.