Abstract:
An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means.

Description:
BACKGROUND 
     A memory cell may be a flash memory cell made of field effect transistors (FETs) that each include a select gate, a floating gate, a drain, and a source. Each memory cell may be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to the select gate, the cell can be switched “on” and “off.” Each memory cell in an array of memory cells store a “1” or a “0.” Multilevel cells can store more than a single bit of data. 
     Programming a cell includes trapping excess electrons in the floating gate to increase the voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed when the cell current is less than a reference current and the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied. 
     A memory array may include multiple pages that are individually accessible. For example, a memory array may contain 64 pages and each page may contain 1 KB of memory cells. Each memory cell may be accessed by making the page that contains the memory cell the active memory page, then accessing the memory cell by selecting the row and column in the memory page that corresponds to the memory cell. The latency of making a memory page active is generally much larger than the access time of a memory cell. For example the page latency may be 3 microseconds while the cell access time may be only 50 nanoseconds. 
     An error may occur in a memory cell due to internal defects, normal use over a long period of time, non-use for a long period of time, or other factors. Two of the primary data reliability issues for memory cells are the “data retention” effect and “read disturb” effect. The “data retention” effect is a shift in the stored voltage level toward the erase state that results from the normal passage of time. The “read disturb” effect is a shift in the stored voltage level that results from reading the memory cell. For the read disturb effect to be appreciable, many reads must occur. When the stored voltage level shifts too far in either direction, it will be interpreted as representing the next higher or lower voltage level and thus the data will be misread. 
     An error checking and correction (ECC) circuit detects and optionally corrects errors in a memory array. An ECC circuit typically partitions a memory page into groups of memory cells and checks each group of memory cells independently and then generates a syndrome that indicates which memory cells had errors in each group. For example, a page of memory with 1 KB of memory cells may have 64 groups each containing 16 bytes of memory cells. Based on the algorithm of the ECC circuit and the size of the group, the memory cells in the group can be corrected if the total number of errors in the group is below a threshold. An ECC circuit typically generates a syndrome for each group that indicates which memory cells have errors. A syndrome that contains all zeros indicates that no errors were detected. If the number of errors in a group exceeds the threshold, none of the errors can be repaired. For example, the maximum number of errors that can be corrected in a memory array may be: 
     
       
         Max # of errors=# of pages*# of groups*bits/group   Eqn. 1 
       
     
     Where: 
     Max # of errors is the maximum number of errors that can be corrected in the memory array. 
     # of pages is the number of pages in the memory array. 
     # of groups is the number of groups per page. 
     bits/group is the number of bits that can be repaired per group. 
     For the above example: 
     
       
         Max # of errors=64*64*16 
       
     
     
       
         =1KB  Eqn. 2 
       
     
     The reliability of a memory array is dependent on many factors, some of which are process-dependent. Therefore, it is desirable to periodically test memory arrays to ensure that the manufacturing processes is functioning properly. Currently, complex and expensive test equipment must be connected with the memory array to test the reliability of the memory array. Also, the external test equipment typically cause delays during testing. These delays significantly lengthen the testing period for tests such as “read disturb” tests. 
     BRIEF SUMMARY 
     An integrated memory self-tester that tests an entire memory array reduces the need for sophisticated external test equipment and reduces the duration of the test. A read test of the memory array can check the memory cells. Optional programmable registers may store the results of the tests. The results may be transmitted from the memory device. The integrated memory self-tester may be initiated via a test signal, be self initiated periodically, or be initiated by other means. The memory array may be tested using one or more of a variety of patterns including all ones, all zeros, or a pattern, such as a checkerboard pattern. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is described with reference to the accompanying figures. In the figures, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. 
     FIG. 1 is a block diagram of a memory device that includes a self-tester; and 
     FIG. 2 is a flow diagram of a method of self-testing a memory device. 
    
    
     DETAILED DESCRIPTION 
     In order to reduce the complexity of external test equipment and speed up memory testing, it is desirable to have an integrated mechanism to automatically test a memory array. Because the memory array is unavailable for use during a test, it is important to complete the test as quickly as possible. Therefore an improved memory device has a built-in self-tester. A read test, which reads each memory cell and verifies the data in each memory cell is one of the quickest tests. 
     FIG. 1 is a block diagram of a memory device  100  that includes a memory array  102  and a self-tester  104 . The memory array  102  may include flash memory cells, DRAM memory cells, SRAM memory cells, or other types of memory cells. In an embodiment, the memory array  102  is divided into pages of memory cells. 
     The self-tester  104  is an integrated and automated test controller that may include an ECC circuit  106 , a self-test circuit  108  and optional registers  110 . The self-tester  104  tests the entire memory array  102  and reports if any errors were detected. The self-tester  104  may optionally correct the detected error(s). Optionally, the self-tester  104  may test the memory array by perform a test on each memory cell one time or multiple times. For example, the self-tester  104  may test the memory array  102  by performing a read test on the memory cells sequentially then repeating the read test or the self-tester  104  may test each group of memory cells twice before testing the next group of memory cells. A loop count or cycle count can be programmed into the registers  110  indicating the number of loops to be performed. The number of test loops actually performed may also be stored in the registers  110 , such that when an error is detected the number of test loops that have been performed can easily be determined. The test may optionally skip memory cells, groups, pages that are known to have a defect. When an error is detected, the test may be terminated or continued. If the test continues after an error is detected, an error count may be calculated and stored in a register  110  or transmitted from the self-tester  104 . Since the self-tester  104  performs the tests autonomously, the self-tester  104  is preferably internally clocked and requires no interaction with devices external to the memory device  100 . In one embodiment, the internal clock rate can be greater than the clock rate used for external reads or writes. 
     It is preferred that the test be a quick test that can be performed on the memory array  102  while the memory array  102  contains data and that the data is not lost due to the testing, such as a read test. Alternatively, a write-read test, a read-write-read test, or other test may be performed. The self-tester  104  may optionally disable external access to the memory array  102  during the test. In one embodiment, the self-tester  104  accesses the memory array  102  using a wider data path to increase the speed of the test. In another embodiment, the self-tester  104  accesses the memory array  102  using a clock that is faster than the external clock that is used for normal memory reads and writes. 
     The ECC circuit  106  checks the memory array for errors and optionally repairs any detected error. The ECC circuit  106  may operate autonomously or under the control of the self-test circuit  108 . The ECC circuit  106  preferably checks the memory array  102  on a group-by-group basis where the memory array  102  is divided into memory pages that are subdivided into groups. The ECC circuit  102  may use one or more error detection methods to determine if an error has occurred. For example, a cyclic redundancy check (CRC) using a Reed-Solomon algorithm may be used. 
     In one embodiment, the memory array  102  is tested sequentially one group at a time. Alternative, the memory array  102  may be tested following a non-sequential pattern such as a random or pseudorandom pattern. Other testing patterns can also be used such as testing each group sequentially but running the test several times on each group before proceeding to the next group. Once an error is detected, that memory cell or group can optionally be omitted from subsequent testing. Other variations and combinations of tests can also be used to test the memory array  102 . 
     The self-test circuit  108  optionally counts the number of errors detected by the ECC circuit  106  and stores the error count in one of the registers  110 . The self-test circuit  108  may control the ECC circuit  106  such that the self-test circuit  108  initiates and terminates the testing. The self-test circuit  108  and ECC circuit  106  may be a single integrated device. 
     The self-tester  104  may have various external interfaces, for example, “Test,” “Interrupt,” and “Error” signals are received at optional interface nodes  112 ,  114 , and  116 , respectively. In one embodiment, the interfaces nodes  112  and  114  are connected with the self-test circuit  108 . The “Test” signal may be an input signal that initiates a memory test and/or the “Test” signal may be an output signal that indicates the memory test is completed. Alternatively, the self-tester  104  may be initiated after a threshold number of memory accesses have occurred. For example, the self-tester  104  may be initiated after a million memory cells in the memory array  102  have been read or written. In other alternatives, the self-tester  104  may be initiated periodically, after a timer times out, after the memory array is powered-on, after the memory array is reset, or any combination of the initiation mechanisms. 
     The Ready/Busy signal, also called the “Ready” signal, is an output signal that indicates when the memory is available, “Ready,” and when the memory array is unavailable, “Busy.” The self-tester  104  can lower the Ready/Busy signal to indicate a test is in progress then raise the signal once the test has terminated. In an embodiment that includes such a Ready/Busy signal, the Ready/Busy signal may be used to measure the duration of the test. 
     The optional “Interrupt” signal is received at interface nodes  114  and may interrupt the self-tester  104  during a memory test. The “Interrupt” signal can be used as a timeout mechanism to stop a memory test. In another embodiment, the Test, Interrupt, and Ready/Busy signals are received and transmitted at a single interface node. A timeout mechanism can be used in conjunction with or in place of the Interrupt signal. The timeout mechanism would terminate the testing after a timeout threshold is reached. 
     FIG. 2 is a flow diagram of a method  200  of testing a memory device. In  202 , the self-tester initiates a test of the entire memory array. 
     In  204 , each memory cell in the memory array  102  (FIG. 1) is tested. One such test is the read test that is performed sequentially across the entire memory array. The test may be performed by an ECC circuit  106  (FIG.  1 ). The test may be terminated if an error is detected or the entire memory array may be tested regardless if an error is detected. 
     In  206 , an error indicator is generated. The number of errors detected may be counted or an error flag can be set to indicate that at least one error was detected. Optionally, the detected errors may be corrected. 
     In  208 , an indication that an error was detected optionally can be provided external to the memory device via an error signal. Alternatively, the error indication may be stored in an internal register  110  for later access by external test equipment. 
     While preferred embodiments have been shown and described, it will be understood that they are not intended to limit the disclosure, but rather it is intended to cover all modifications and alternative methods and apparatuses falling within the spirit and scope of the invention as defined in the appended claims or their equivalents.