Abstract:
To reduce current consumption in a sense amplifier circuit in a semiconductor integrated-circuit device, in particular, in a semiconductor integrated-circuit having a non-volatile memory as a memory element thereof. A Switching element for cutting off a direct current at the end of data reading from a memory is arranged in a path through which the direct current flows. In this way, the switching element cuts off the direct current at the moment of completion of the data reading from the memory, thereby substantially reducing current consumption.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor integrated-circuit device including a sense amplifier formed on a semiconductor substrate. 
     2. Related Art 
     One known sense amplifier of a non-volatile memory such as a flash memory is a single-ended sense amplifier disclosed in Japanese Unexamined Patent Application Publication No. 8-63984. 
     In the conventional art, the above construction allows a direct current to flow between a memory cell transistor and a load transistor, thereby increasing a consumption current. 
     The present invention has been developed in view of the above problem, and one advantage of the present invention is to reduce the power consumption in a semiconductor integrated-circuit device having a sense amplifier 
     SUMMARY OF THE INVENTION 
     To solve the problem described above, a semiconductor integrated-circuit device in accordance with one embodiment of the present invention having a memory element and a sense amplifier circuit, includes an inverter amplifier including an inverter circuit and a first N-type, MOS transistor for receiving, at a gate thereof, an output signal from the inverter circuit, with a drain of the first N-type MOS transistor connected to an input of the inverter circuit, reference current generator means, a first P-type MOS transistor for receiving a signal from the reference current generator means, a second P-type MOS transistor which is connected in series with the first P-type MOS transistor and receives an output of the inverter amplifier at the input gate thereof, a third P-type MOS transistor connected in parallel with the first and second P-MOS transistors, and a second N-type MOS transistor for opening a current path to ground potential during a precharge operation. 
     In the above semiconductor integrated-circuit device, the memory element includes a non-volatile memory. 
     In the semiconductor integrated-circuit device a direct current required in a read operation from a memory element during precharging is cut off by the N-type MOS transistor, and a direct current during a read operation from a memory cell is cut off by the P-type MOS transistor. The direct current is cut off at the end of the read operation, and a duration of time during which the current flows remains constant. When an operation frequency drops, the direct current, which conventionally flows during an active period of the sense amplifier, is substantially reduced, thereby greatly lowering current consumption. 
     In accordance with a second embodiment of the present invention, a semiconductor integrated-circuit device having a memory element and a sense amplifier circuit includes reference current generator means, a first P-type MOS transistor for receiving a signal from the reference current generator means, a second P-type MOS transistor connected in series with the first P-type MOS transistor, a third P-type MOS transistor for precharging, connected in parallel with the first and second P-type MOS transistors, and an inverter circuit to which drains of the second and third P-type MOS transistors are connected, wherein an output of the inverter circuit is fed to a gate of the second P-type MOS transistor. 
     In the semiconductor integrated-circuit device, the memory element includes a non-volatile memory. 
     In the semiconductor integrated-circuit device a direct current in a read operation from a memory element is cut off by the P-type MOS transistor. The direct current is cut off at the end of the read operation, and a duration of time during which the current flows remains constant. When an operation frequency drops, the direct current, which conventionally flows during an active period of the sense amplifier, is substantially reduced, thereby greatly lowering current consumption. 
     In accordance with a third embodiment of the present invention, a semiconductor integrated-circuit device having a memory element and a sense amplifier circuit, includes an inverter amplifier including an inverter circuit and a first N-type MOS transistor for receiving, at a gate thereof, an output signal from the inverter circuit, with a drain of the first N-type MOS transistor connected to an input of the inverter circuit, a second N-type MOS transistor which is connected in series with a source of the first N-type MOS transistor with the source thereof connected to a ground line, and a first P-type MOS transistor for precharging, wherein the second N-type MOS transistor receives, at a gate thereof, a signal identical to a gate input signal to the first P-type MOS transistor. 
     In the semiconductor integrated-circuit device, the memory element includes a non-volatile memory. 
     In the semiconductor integrated-circuit device a direct current required in a read operation from a memory element during precharging is cut off by the N-type MOS transistor, and the current consumption is substantially reduced. 
     In accordance with a fourth embodiment of the present invention, a semiconductor integrated-circuit device of the present invention having a memory element and a sense amplifier circuit includes an inverter amplifier including an inverter circuit and a first N-type MOS transistor for receiving, at a gate thereof, an output signal from the inverter circuit, with a drain of the first N-type MOS transistor connected to an input of the inverter circuit, reference current generator means, a first P-type MOS transistor for receiving a signal from the reference current generator means, a second P-type MOS transistor for precharging, connected in parallel with the first P-type MOS transistor, and a second N-type MOS transistor connected in series with a source of the first N-type MOS transistor, wherein a source of the second N-type MOS transistor is connected to a ground line and the second N-type MOS transistor receives, at a gate thereof, a signal identical to a gate input signal to the second P-type MOS transistor. 
     In the semiconductor integrated-circuit device, the memory element includes a non-volatile memory. 
     In the semiconductor integrated-circuit device a direct current required in a read operation from a memory element during precharging is cut off by the N-type MOS transistor, and the current consumption is substantially reduced, 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other features and advantages of the invention will be apparent from the following drawings that illustrate, by way of example, various features of embodiments of the present invention. 
     FIG. 1 is a circuit diagram of a sense amplifier of a semiconductor integrated-circuit device according to one embodiment of the present invention; 
     FIG. 2 is a circuit diagram of a reference current generator according to one embodiment of the present invention; 
     FIG. 3 is a timing diagram showing the operation of the sense amplifier of the semiconductor integrated-circuit device according to one embodiment of the present invention; 
     FIG. 4 is a timing diagram showing the operation of the sense amplifier of the semiconductor integrated-circuit device according to one embodiment of the present invention; 
     FIG. 5 is a current diagram showing a sense amplifier circuit of the semiconductor integrated-circuit device according to one embodiment of the present invention; 
     FIG. 6 is a circuit diagram showing a sense amplifier circuit of the semiconductor integrated-circuit device according to one embodiment of the present invention; 
     FIG. 7 is a circuit diagram showing a sense amplifier circuit of the semiconductor integrated-circuit device according to one embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 is a circuit diagram showing a sense amplifier circuit in a semiconductor integrated-circuit device according to one embodiment of the present invention. The sense amplifier circuit includes a P-type MOS transistor MP 11  which receives, at a gate thereof, an output signal SENREF of a reference current generator circuit with a source thereof connected to a power source, a P-type MOS transistor MP 12  connected in series with the P-type MOS transistor MP 11 , a P-type MOS transistor MP 13  which receives, at a gate thereof, a precharge signal PRCG, an inverter circuit INV 11  with an input thereof connected to a node n 11  of the P-type MOS transistor MP 12  and the MP 13 , an N-type MOS transistor MN 11  which receives, at the P-type MOS transistor gate thereof, an output SOUT of the inventor circuit INV 11 , and an N-type MOS transistor MN 12  which opens a path to VSS during a precharge operation, and receives, at a gate thereof, the precharge signal PRCG with a source thereof connected to a ground line Vss. 
     The inverter circuit INV 11  and the N-type MOS transistor MN 11  constitute an inverter amplifier. When the precharge signal PRCG is transitioned to a low level, the P-type transistor MP 13  turns on, and the N-type MOS transistor MN 12  turns off, thereby causing the node n 11  to rise to a VDD level. 
     The sense amplifier circuit and an IO node I 01  are isolated from each other by an N-type MOS transistor MN 13 . The N-type MOS transistor MN 13  prevents the voltages of the IO node and bit lines BL 1 , BL 2 , and BL 3  from excessively rising during a precharge operation. The output of an NOR gate NOR 11  is fed to the N-type MOS transistor MN 13 . The NOR gate NOR 11  has input gates, one receiving an enable signal S 1  (with the active-low level thereof) and the other connected to the IO node I 01 . 
     Non-volatile memory transistors MF 1 -MF 16 , MF 17 -MF 22 , and MF 23 -MF 28  are respectively connected to bit lines BL 1 , BL 2 , and BL 3 . Connected to memory transistors are word line and a source line between every two word lines, across the bit lines. When an address signal is input, one word line designated by the address signal is selected from among word lines WL 1  through WLn. Similarly, one is selected from bit line selection signals YSEL 1  through YSELn, and one of the memory transistors MF 1 -MF 28  is thus selected. 
     When the selected memory transistor is in an erased state, a current as high as 120 μA is permitted to flow from a drain-bit line to the ground line VSS with a power source voltage VDD of 5 V. In a programmed state, a current permitted to flow is almost zero with a power source voltage VDD of 5 V. 
     FIG. 2 is a circuit diagram showing a reference current generator circuit. A signal SAACT enables the sense amplifier and the reference current generator circuit, and is input to an inverter circuit INV 8 . An output signal S 1  of the inverter circuit INV 8  is input to an input of a NOR gate NOR 1  while being input to the NOR gate NOR 11  of the sense amplifier circuit. The S 1  signal is also input to a delay circuit composed of inverter circuits INV 9 , INV 1 , INV 2 , INV 3 , and INV 4 , and then the inverter circuit INV 4  gives the output thereof as the output signal PRCG, which is the precharge signal PRCG of the sense amplifier circuit. 
     An output signal S 2  of the inverter circuit INV 9  is input to the gate of a P-type MOS transistor MP 1  for pulling up the SENREF signal. The output of the NOR gate NOR 1  is fed to a gate of an N-type MOS transistor MN 1 . The N-type MOS transistor MN 1  and the NOR gate NOR 1  are included to form a circuit arrangement equivalent to that of the sense amplifier circuit, and no problem will be presented if the source and the drain of the MN 1  are directly connected to each other. 
     A memory transistor MF 1  and an N-type MOS transistor MN 5 , and a memory transistor MF 2  and an N-type MOS transistor MN 8  respectively constitute dummy memory cells, and an address signal XAD 0  selects which of them to use. This selection is associated with the selection of the two word lines with the source line therebetween in the already-discussed sense amplifier circuit. 
     An n:1 current mirror circuit includes P-type MOS transistors MP 2 , MP 3 , MP 4 , and MPn, and the P-type MOS transistor MF 11  in the sense amplifier circuit. A current permitted to flow into a node n 11  of the sense amplifier circuit is a 1/n of the current flowing into the dummy memory cell circuit through the node SENREF of the reference voltage generator circuit and node n 2 . 
     FIGS.  3 ( a ) and  3 ( b ) are timing diagrams showing the operation of the semiconductor integrated-circuit device according to one embodiment of the present invention when the memory transistor in the sense amplifier circuit is in an erased state. Designated S 1  is an active-low signal, which is an inverted signal of the enable signal SAACT of the sense amplifier. Prior to activating the sense amplifier, one of the bit line selection signals YSEL 1 -YESLn and one of the word lines WL 1 -WLn are selected, thereby selecting one of the memory transistors MF 1 -MF 28 . The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 11 , and IO, and the bit line are precharged by the P-type MOS transistor MP 13 . With the precharge signal PRCG transitioned to a low level, the N-type MOS transistor MN 12  turns off, blocking a precharge current from flowing into the inverter amplifier. Since the selected memory transistor discharges the charge for precharging in its erased state, the current drive capability of the P-type MOS transistor MP 13  for precharging needs to be sufficiently greater than that of the memory transistor. In response to a rise in the voltage of the IO node I 01 , the output voltage of the NOR gate NOR 11  drops, and the drive capability of the N-type MOS transistor MN 13  also drops along therewith, and the precharging to the bit line thus ends. Since the precharging is performed during the low period of the signal PRCG, the node n 11  rises in voltage above that of the IO node I 01  and the bit line, and nearly reaches the VDD level. 
     When the precharging ends with the precharge signal PRCG transitioned to a high level, the charge stored in the bit line flows to the ground line VSS in the erased state of the selected memory transistor, thereby lowering the voltage of the bit line. The output of the NOR gate NOR 11  rises to the VDD level, the drive capability of the N-type MOS transistor MN 13  increases, and the voltage at the node n 11  is lowered. With the voltage at the node n 11  lowered, the voltage of the output SOUT of the inverter circuit INV 11  rises, the current drive capability of the N-type MOS transistor MN 11  increases, the nodes n 11  and IO and the bit line are more rapidly lowered in voltage to the VSS level, because the charge at the IO node I 01  and the bit line is discharged along with the memory transistor. Since the current flowing through the memory transistor and the serially connected transistors of the P-type MOS transistor MP 11  and the P-type MOS transistor MP 12 , is allowed to be larger than the current passing through the serially connected transistors of the P-type MOS transistor MP 11  and the P-type MOS transistor MP 12  and determined by the reference signal SENREF, the nodes n 11  and IO and the bit line drop in voltage to the VSS level. When the voltage of the node n 11  drops, the voltage of the output SOUT of the inverter circuit INV 11  rises, reaches the VDD level, and is read as a high level. With the SOUT at a high level, the P-type MOS transistor MP 12  turns off, and the current flowing into the memory transistor is cut off. Therefore, at the moment the output data of the sense amplifier is determined, the P-type MOS transistor MP 12  turns off, and the direct current is automatically cut off. The enable signal SAACT of the sense amplifier remains active. 
     FIGS.  4 ( a ) and  4 ( b ) are timing diagrams showing the operation of semiconductor integrated-circuit device according to one embodiment of the present intention when the memory transistor in the sense amplifier is in a programmed state. In the same manner as in the erased state, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are activated, thereby selecting one of the memory transistors MF 1 -MF 28 . The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 11  and IO, and the bit line are precharged by the P-type MOS transistor MP 13 . With the precharge signal PRCG transitioned to a low level, the N-type MOS transistor MN 12  turns off, blocking a precharge current from flowing into the inverter amplifier. With the selected memory transistor in the programmed state thereof, the charge stored therein is not discharged. The output voltage at the NOR gate NOR 11  remains lowered, and the current drive capability of the N-type MOS transistor MN 13  remains low. The node n 11  is maintained at a high level, the output SOUT of the inverter circuit INV 11  is kept to the VSS level, the N-type MOS transistor MN 11  turns off, and direct current flows to nowhere. 
     FIG. 5 is a circuit diagram of a second embodiment of the sense amplifier of the semiconductor integrated-circuit device of the present invention. The sense amplifier circuit includes a P-type MOS transistor MP 21  which receives, at a gate thereof, an output signal SENREF of a reference current generator circuit with a source thereof connected to a power source, a P-type MOS transistor MP 22  connected in series with the MP 21 , a P-type MOS transistor MP 23  which receives, at a gate thereof, a precharge signal PRCG, and an inverter circuit INV 21  with an input thereof connected to a node n 21  of the P-type MOS transistor MP 22  and the P-type MOS transistor MP 23 . The output SOUT of the inverter circuit INV 21  is connected to the gate of the P-type MOS transistor MP 22 . The IO node and the bit line remain unchanged in construction from those shown in FIG.  1 . 
     Designated S 1  is an active-low signal, which is an inverted signal of the enable signal SAACT of the sense amplifier. Prior to activating the sense amplifier, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are selected, thereby selecting one of the memory transistors MF 31 -MF 48 . The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 21  and I 011 , and the bit line are precharged by the P-type MOS transistor MP 23 . Since the precharged charge is discharged with the selected memory transistor in an erased state, the current drive capability of the P-type MOS transistor MP 23  for precharging needs to be set greater than that of the memory transistor. In response to a rise in the voltage of the IO node IO 11 , the output voltage of the NOR gate NOR 21  drops, and the drive capability of the N-type MOS transistor MN 23  also drops along therewith, and the precharging to the bit line thus ends. Since the precharging is performed during the low period of the signal PRCG, the node n 21  rises in voltage above that of the IO node IO 11  and the bit line, and nearly reaches the VDD level. 
     When the precharging ends with the precharge signal PRCG transitioned to a high level, the charge stored in the bit line flows to the ground line VSS in the erased state of the selected memory transistor, thereby lowering the voltage of the bit line. The output of the NOR gate NOR 21  rises to the VDD level, the drive capability of the N-type MOS transistor MN 23  increases, and the voltage at the node n 21  is lowered. Since the memory transistor permits to flow a current larger than the current passing through the serially connected transistors of the P-type MOS transistor MP 21  and the P-type MOS transistor MP 22  and determined by the reference signal SENREF, the nodes n 21  and IO and the bit line drop in voltage to the VSS level. With the voltage at the node n 21  lowered, the voltage of the output SOUT of the inverter circuit INV 21  rises, reaches the VDD level, and is read as a high level. With the SOUT at a high level, the P-type MOS transistor MP 22  turns off, and the current flowing into the memory transistor is cut off. Therefore, at the moment the output data of the sense amplifier is determined, the P-type MOS transistor MP 22  turns off, and the direct current is automatically cut off. The enable signal SAACT of the sense amplifier remains active. 
     In the same manner as in the erased state, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are activated, thereby selecting one of the memory transistors MP 31 -MF 48  with the selected memory transistor in a programmed state. The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 21  and IO 11 , and the bit line are precharged by the P-type MOS transistor MP 23 . With the selected memory transistor in the programmed state thereof, the charge stored in the bit line is not discharged. The output voltage at the NOR gate NOR 21  remains lowered, and the current drive capability of the N-type MOS transistor MN 23  remains low. The node n 21  is maintained at a high level, and the output SOUT of the inverter circuit INV 21  is kept to the VSS level. 
     FIG. 6 is a circuit diagram of a third embodiment of the sense amplifier of the semiconductor integrated-circuit device of the present invention. The sense amplifier circuit includes a P-type MOS transistor MP 33  which receives, at a gate thereof, a precharge signal PRCG, an inverter circuit INV 31  with an input thereof connected to a node n 31  to which the MP 33  is connected, an N-type MOS transistor MN 31  which receives, at a gate thereof, an output SOUT of the INV 31 , and an N-type MOS transistor MN 32  which opens a path to VSS during a precharge operation, and receives, at a gate thereof, the precharge signal PRCG with a source thereof connected to a ground line Vss. The inverter circuit INV 31  and the N-type MOS transistor MN 31  constitute an inverter amplifier. The IO node and bit line remain unchanged in construction from those shown in FIG.  1 . 
     Designated S 1  is an active-low signal, which is an inverted signal of the enable signal SAACT of the sense amplifier. Prior to activating the sense amplifier, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are selected, thereby selecting one of the memory transistors MF 51 -MF 68 . The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 31 , and IO 21 , and the bit line are precharged by the P-type MOS transistor MP 33 . Since the selected memory transistor discharges the charge for precharging in its erased state, the current drive capability of the P-type MOS transistor MP 33  for precharging needs to be sufficiently greater than that of the memory transistor. In response to a rise in the voltage of the IO node IO 21 , the output voltage of the NOR gate NOR 31  drops, and the drive capability of the N-type MOS transistor MN 33  also drops along therewith, and the precharging to the bit line thus ends. Since the precharging is performed during the low period of the signal PRCG, the node n 31  rises in voltage above that of the IO node IO 21  and the bit line, and nearly reaches the VDD level. 
     When the precharging ends with the precharge signal PRCG transitioned to a high level, the charge stored in the bit line flows to the ground line VSS in the erased state of the selected memory transistor, thereby lowering the voltage of the bit line. The output of the NOR gate NOR 31  rises to the VDD level, the drive capability of the N-type MOS transistor MN 33  increases, and the voltage at the node n 31  is lowered. With the voltage at the node n 31  lowered, the voltage of the output SOUT of the inverter circuit INV 31  rises, the current drive capability of the N-type MOS transistor MN 31  increases, the nodes n 31  and IO and the bit line are more rapidly lowered in voltage to the VSS level, because the charge at the IO node IO 21  and the bit line is discharged along with the memory transistor. When the voltage of the node n 31  drops, the voltage of the output SOUT of the inverter circuit INV 31  rises, reaches the VDD level, and is read as a high level. 
     In the same manner as in the erased state, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are activated, thereby selecting one of the memory transistors MF 51 -MF 68  with the selected memory transistor in a programmed state. The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 31  and IO 21 , and the bit line are precharged by the P-type MOS transistor MP 33 . With the selected memory transistor in its programmed state, the charge stored in the bit line is not discharged. The output voltage at the NOR gate NOR 31  remains lowered, and the current drive capability of the N-type MOS transistor MN 33  remains low. The node n 31  is maintained at a high level, and the output SOUT of the inverter circuit INV 31  is kept to the VSS level. 
     FIG. 7 is a circuit diagram showing a fourth embodiment of the sense amplifier circuit in the semiconductor integrated-circuit device of this invention. The sense amplifier circuit includes a P-type MOS transistor MP 41  which receives, at a gate thereof, an output signal SENREF of a reference current generator circuit with a source thereof connected to a power source, a P-type MOS transistor MP 43  which receives, at a gate thereof, a precharge signal PRCG, an inverter circuit INV 41  with an input thereof connected to a node n 41  of the P-type MOS transistor MP 41  and the P-type MOS transistor MP 43 , an N-type MOS transistor MN 41  which receives, at a gate thereof, an output SOUT of the inverter circuit INV 41 , and an N-type MOS transistor MN 42  which opens a path to VSS during a precharge operation, and receives, at a gate thereof, the precharge signal PRCG with a source thereof connected to a ground line Vss. 
     Designated S 1  is an active-low signal, which is an inverted signal of the enable signal SAACT of the sense amplifier. Prior to activating the sense amplifier, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are selected, thereby selecting one of the memory transistors MF 71 -MF 88 . The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 41 , IO 31 , and the bit line are precharged by the P-type MOS transistor MP 43 . Since the selected memory transistor discharges the charge for precharging in its erased state, the current drive capability of the P-type MOS transistor MP 43  for precharging needs to be sufficiently greater than that of the memory transistor. In response to a rise in the voltage of the IO node IO 31 , the output voltage of the NOR gate NOR 41  drops, and the drive capability of the N-type MOS transistor MN 43  also drops along therewith, and the precharging to the bit line thus ends. Since the precharging is performed during the low period of the signal PRCG, the node n 41  rises in voltage above that of the IO node IO 31  and the bit line, and nearly reaches the VDD level. 
     When the precharging ends with the precharge signal PRCG transitioned to a high level, the charge stored in the bit line flows to the ground line VSS in the erased state of the selected memory transistor, thereby lowering the voltage of the bit line. The output of the NOR gate NOR 41  rises to the VDD level, the drive capability of the N-type MOS transistor MN 43  increases, and the voltage at the node n 41  is lowered. Since the memory transistor allows to flow a current larger than the current passing through the P-type MOS transistor MP 41  and determined by the reference signal SENREF, the nodes n 41  and IO and the bit line drop in voltage to the VSS level. With the voltage at the node n 41  lowered, the voltage of the output SOUT of the inverter circuit INV 41  rises, the current drive capability of the N-type MOS transistor MN 41  increases, and the nodes n 41  and IO and the bit line are more rapidly lowered in voltage to the VSS level, because the charge at the IO node IO 31  and the bit line is discharged along with the memory transistor. Since the memory transistor and the serially connected transistors of the P-type MOS transistor MP 41  and the P-type MOS transistor MP 42  permit to flow a current larger than the current passing through the serially connected transistors of the P-type MOS transistor MP 41  and determined by the reference signal SENREF, the nodes n 41  and IO and the bit line drop in voltage to the VSS level. When the voltage of the node n 41  drops, the voltage of the output SOUT of the inverter circuit INV 41  rises, reaches the VDD level, and is read as a high level. 
     In the same manner as in the erased state, one of the bit line selection signals YSEL 1 -YSELn and one of the word lines WL 1 -WLn are activated, thereby selecting one of the memory transistors MF 71 -MF 88  with the selected memory transistor in the programmed state thereof. The sense enable signal S 1  is transitioned to a low level, the precharge signal PRCG is transitioned to a low level with a delay time that is determined by the delay circuit, and the nodes n 41  and IO 31 , and the bit line are precharged by the P-type MOS transistor MP 43 . With the selected memory transistor in the programmed state thereof, the charge stored in the bit line is not discharged. The output voltage at the NOR gate NOR 41  remains lowered, and the current drive capability of the N-type MOS transistor MN 43  remains low. The node n 41  is maintained at a high level, and the output SOUT of the inverter circuit INV 41  is kept to the VSS level.