Abstract:
In an exemplary application, an apparatus according to a disclosed embodiment receives a radio frequency signal and outputs an intermediate frequency signal. Rejection of image components in the intermediate frequency signal is obtained without the need to preprocess the radio frequency signal with an image reject filter. Such an apparatus may also exhibit an image rejection performance that is robust to frequency deviation of a local oscillator.

Description:
RELATED APPLICATIONS 
   This application claims benefit of U.S. Provisional Patent Application No. 60/245,230, entitled “QUADRATURE GENERATOR WITH IMAGE REJECT MIXER,” filed Nov. 3, 2000. 

   BACKGROUND 
   1. Field of the Invention 
   This invention relates to the conversion of radio frequency (RF) signals. 
   2. Background Information 
   In general, wireless communications comprises the modulation of one or more baseband information signals onto one or more carrier signals, transmission of the resulting bandpass signal(s), and demodulation at a receiver to recover one or more of the information signals. Modern receivers typically employ the heterodyne technique, which involves either down-converting or up-converting an input RF signal to some convenient intermediate frequency (IF) and then demodulating the IF signal by using an appropriate detector. Heterodyne receivers are easily tunable and offer high stability. The difference between the input and output frequencies of such a receiver also provides a high degree of immunity from self-oscillation due to stray coupling. Additionally, adjacent channel rejection may be obtained by using high-Q filters only in the IF stage, which may operate at a fixed frequency much lower than the carrier frequency. 
   A basic heterodyne conversion circuit as shown in  FIG. 1  may be used to convert all types of modulated RF signals to IF, including broadcast-band AM, FM and television signals; network communication signals as in a cellular telephone or wireless local area network; satellite communications or ranging signals; and radar signals. In such a circuit, the mixer receives the RF signal S 10  (for example, as outputted from a RF amplifier) and multiplies it with a signal S 20  from a local oscillator  5  to produce an IF signal. 
   We define the carrier frequency of RF signal S 10  to be ω c , the frequency of local oscillator signal S 20  to be ω LO , and the desired frequency of the IF signal to be ω IF  (all in radians/second). Therefore, we may express RF signal S 10  as cos ω c t, local oscillator signal S 20  as cos ω LO t, and the desired IF signal as ω i t (with t in seconds). With reference to the trigonometric identity
 
cos  a  cos  b =(½)[ cos( a+b )+cos( a−b )],
 
we can see that the output of the mixer will include a downconverted signal cos (ω LO −ω c )t and an upconverted signal cos (ω LO +ω c )t. The IF filter is a bandpass filter that receives the output of the mixer and selects either the up-conversion result or the down-conversion result, whichever is chosen by the receiver designer.
 
     FIGS. 2A and 2B  are graphical illustrations of heterodyne conversion operations using low-side injection and high-side injection, respectively. In these operations, we assume that downconversion is desired [i.e. ω IF =|(ω LO −ω c )|]. Now consider a case in which RF signal S 10  contains not only the desired component at ω c , but also an undesired image component at a frequency ω i =2ω LO −ω c . In both examples, the image component will also downconvert to corrupt the desired IF signal at ω IF . These figures illustrate a major weakness of the basic heterodyne design: its susceptibility to image interference. In order to prevent such a situation, heterodyne designs usually include an image reject filter upstream of the mixer (e.g. as shown in  FIG. 3 ) in order to attenuate any image components before mixing. 
   Unfortunately, the need for an image reject filter may greatly increase the size and cost of devices such as wireless communication apparatus. Depending on the design requirements of the filter, it may be physically large and very expensive. A need to implement the filter at RF frequencies rather than IF frequencies may compound the difficulty of obtaining a component that is suitable in terms of cost, size, and performance. Additionally, such a filter will typically be supplied as an off-chip component, thereby increasing fabrication costs, necessitating extra pins on the RF/IF chip, and consuming board space. Such requirements are contrary to the increasing need to reduce the size and cost of wireless communications devices, especially in the field of cellular telephony. 
     FIG. 4  shows a block diagram of a Hartley image reject mixer  100 . Such a mixer may be used in a heterodyne conversion circuit (e.g. as shown in  FIG. 5 ) as a smaller and less expensive alternative to an image reject filter. Unfortunately, the rejection performance of this approach is highly dependent on very close matching between the two signal paths in terms of both gain and phase. Moreover, even under careful manufacturing conditions, such an image reject mixer achieves good results only over a limited frequency band. Shortcomings such as these make the configuration of  FIG. 5  unsuitable for applications that require high levels of image rejection (e.g. greater than 35–40 dB). 
   SUMMARY 
   A converter according to one embodiment of the invention includes an image reject mixer and a quadrature signal generator. The quadrature signal generator receives first and second oscillator signals and outputs a quadrature signal pair. The image reject mixer produces an output signal based on the quadrature signal pair and an input signal. In at least some implementations of such a converter, a phase relation between the quadrature signal pair is robust to changes in the frequency of at least one of the oscillator signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a circuit for heterodyne conversion; 
       FIG. 2A  is a diagram showing representative frequencies of a low-side injection downconversion; 
       FIG. 2B  is a diagram showing representative frequencies of a high-side injection downconversion; 
       FIG. 3  is a block diagram of a circuit for heterodyne conversion that includes an image reject filter; 
       FIG. 4  is a block diagram of an image reject mixer  100 ; 
       FIG. 5  is a block diagram of a circuit for heterodyne conversion that includes the image reject mixer  100 ; 
       FIG. 6  is a block diagram of a converter  300  according to an embodiment of the invention; 
       FIG. 7  is a block diagram of an implementation  200   a  of image reject mixer  200 ; 
       FIG. 8  is a schematic diagram of a phase shifter; 
       FIG. 9  is a schematic diagram of another phase shifter; 
       FIG. 10  is a block diagram of an alternate implementation  200   b  of image reject mixer  200 ; 
       FIG. 11  is a block diagram of an alternate implementation  200   c  of image reject mixer  200 ; 
       FIG. 12  is a block diagram of an alternate implementation  200   d  of image reject mixer  200 ; 
       FIG. 13  is a block diagram of an alternate implementation  200   e  of image reject mixer  200 ; 
       FIG. 14  is a block diagram of an alternate implementation  200   f  of image reject mixer  200 ; 
       FIG. 15  is a block diagram of a converter  310  according to an alternate embodiment of the invention; 
       FIG. 16  is a block diagram of a quadrature signal generator  600   a  suitable for use in a converter according to an embodiment of the invention; 
       FIG. 17  is a block diagram of a quadrature signal generator  600   b  suitable for use in a converter according to an embodiment of the invention; and 
       FIG. 18  is a block diagram of a converter  320  according to an embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   While the conversion circuit shown in  FIG. 5  may be a smaller and less expensive alternative to one that includes an image reject filter, it suffers from a susceptibility to changes in the frequency of local oscillator  5 . This susceptibility is a consequence of the nonideal behavior of phase shifter  20  with respect to changes in the frequency of the signal that drives it. Specifically, as the frequency of local oscillator signal S 20  drifts away from ω LO  (e.g. because of local heating, changes in ambient temperature, electromagnetic interference, component aging, etc.), the shift performed by phase shifter  20  may deviate from 90 degrees. Variances during circuit fabrication may also cause a frequency error in the output of the local oscillator, producing a similar deviation of this phase relation from the expected value. 
   As explained elsewhere (e.g., by Behzad Razavi in  RF Microelectronics , Prentice Hall PTR, Upper Saddle River, N.J., 1998, ISBN 0-13-887571-5 at Chapter 5, section 5.2), an error in the output of phase shifter  20  may prevent image reject mixer  100  from canceling the unwanted image components, thereby allowing them to corrupt IF signal S 30 . Even in the absence of an image component in RF signal S 10 , the error may cause distortion (e.g. phase distortion) in IF signal S 30 . It is desirable to obtain a heterodyne conversion operation that is more tolerant of local oscillator frequency drift and deviation. 
     FIG. 6  shows a block diagram of a converter  300  according to an embodiment of the invention that is configured and arranged to receive a RF signal S 10  and output an IF signal S 130 . Converter  300  includes an image reject mixer  200  and a quadrature generator  400  that supplies in-phase and quadrature generator signals S 140  and S 150  (both signals having a frequency ω g ) to image reject mixer  200 . 
     FIG. 7  shows a block diagram of an implementation  200   a  of image reject mixer  200 . In this circuit, phase shifter  110  receives RF signal S 110  and outputs I and Q signals as indicated. These I and Q signals have the same frequency as RF signal S 110 , have the same amplitude as each other, and are ninety degrees out-of-phase (in this example, the phase angle of the Q signal is ninety degrees (π/2 radians) less than the phase angle of the I signal). 
     FIG. 8  shows one possible implementation for phase shifter  110 , where the values of resistance R and capacitance C are based at least in part on the frequency of the input signal applied to the phase shifter. A polyphase filter constructed from resistive and capacitive components may also be used as a phase shifter. For example,  FIG. 9  shows a two-stage sequence asymmetric polyphase filter. Factors that may guide a choice of phase shifter configuration for a particular application include insertion loss, effect of frequency shift on phase error, and robustness of the circuit to variations in component or material parameters (e.g. sheet resistance) that may be encountered during fabrication. 
   Mixer  30  receives the I signal outputted by phase shifter  110 , and mixer  40  receives the corresponding Q signal. These mixers may be fabricated using Gilbert cell multipliers, diode or MOSFET passive mixers, and/or other circuits suitable for use as mixers at the desired frequencies. As shown in  FIG. 7 , mixers  30  and  40  also receive in-phase and quadrature generator signals S 140  and S 150 , respectively. These two generator signals have the same amplitude and frequency as each other, but are ninety degrees out-of-phase (in this example, the phase angle of quadrature generator signal S 150  is ninety degrees (π/2 radians) less than the phase angle of in-phase generator signal S 140 ). 
   Combiner  50  performs an additive combination of the mixer output signals to produce IF signal S 130 . For low-side injection and with the polarities of combiner  50  as shown in  FIG. 7 , converter  300  produces an IF signal having the frequency ω IF =ω c −ω g . In other implementations, the direction of the 90-degree relation between the outputs of phase shifter  110 , the direction of the 90-degree relation between generator signals S 140  and S 150 , and/or one or both of the polarities of combiner  50  may be reversed (e.g. to choose an upconversion result instead). 
     FIG. 10  shows a block diagram for another implementation  200   b  of image reject mixer  200 . Phase shifter  120  receives the signals outputted by mixers  30  and  40  at its I and Q inputs, respectively, and induces a ninety-degree phase shift between them. In this example, phase shifter  120  performs a ninety-degree phase delay on the Q input signal in relation to the I input signal. Phase shifter  120  may be implemented using techniques similar to those described above with respect to phase shifter  110 . For example, the phase shifter of  FIG. 8  may be used, with terminals V oI  and V oQ  as inputs and V i  as output. 
   Several other forms of image reject mixer  200  are possible, and a particular configuration may be selected based upon such considerations as circuit topology and component proximity to radiating elements.  FIG. 11  shows a block diagram for another implementation  200   c  of image reject mixer  200  that includes a phase shifter  130 . In this example, phase shifter  130  (which may be implemented using techniques similar to those described above with respect to phase shifter  110 ) performs a ninety-degree phase delay. To obtain the downconversion result in this case, one polarity of combiner  52  is inverted (e.g. as indicated in the figure).  FIG. 12  shows a block diagram for a similar implementation  200   d  of image reject mixer  200  wherein phase shifter  310  receives a signal outputted by mixer  40 . 
     FIG. 13  shows an alternative implementation  200   e  of image reject mixer  200 . In this example, phase shifter  130   a  performs a forty-five-degree (π/4 radians) phase shift on a signal outputted by mixer  30 , while phase shifter  130   b  performs a one-hundred-thirty-five-degree (5×π/4 radians) phase shift on a signal outputted by mixer  40 . In another implementation, a different phase relation between the phase-shifted signals may be obtained by configuring one or both phase shifters to produce a different phase shift. Phase shifters  130   a  and  130   b  may each be implemented using techniques similar to those described above with respect to phase shifter  110 .  FIG. 14  shows a block diagram for a similar implementation  200   f  of image reject mixer  200  wherein phase shifters  130   a  and  130   b  precede mixers  30  and  40  in their respective signal paths. 
   One advantage that may be realized by using two phase shifters in an image reject mixer  200  (e.g. as shown in  FIGS. 13 and 14 ) is that the performances of the phase shifters may track each other over variations that occur during fabrication and/or during operation. Process variations encountered during fabrication, for example, may cause an absolute error of up to ten degrees in a fabricated phase shifter. By constructing the mixer to include two phase shifters instead of only one, this absolute error may be compensated to some extent, and a more accurate result may be obtained as a phase relation between the outputs of the two phase shifters. 
   It may be desirable to design a phase shifter to have an optimal phase-shifting performance over a particular frequency range. In such a case, it may be desirable to design a phase shifter for use in image reject mixer  200  to have an optimal phase-shifting performance at the frequency to be rejected rather than at the frequency to be selected. In a low-side injection application of  FIG. 11 , for example, it may be desirable to design phase shifter  130  for optimal operation at ω c +ω g  (i.e. the frequency to be canceled in combiner  52 ) rather than at the selected intermediate frequency. Such a design choice may represent a tradeoff between a reduced signal amplitude on one hand and the presence of image interference on the other hand. 
     FIG. 15  shows a block diagram of a converter  310  according to another embodiment of the invention. In this example, image reject mixer  200  (e.g. according to an implementation as described above) receives generator signals S 140  and S 150  from quadrature signal generator  600 . In addition to quadrature signal generator  600 , an implementation  400   a  of quadrature generator  400  includes an upper frequency oscillator  520  and a lower frequency oscillator  530 . Upper frequency oscillator  520  outputs an upper frequency oscillator signal S 160  whose angular frequency is expressed herein as ω U  radians/second, and lower frequency oscillator  530  outputs a lower frequency oscillator signal S 170  whose angular frequency is expressed herein as ω L  radians/second. Quadrature signal generator  600  receives the two oscillator signals S 160  and S 170  and outputs the generator signals S 140  and S 150 . 
     FIG. 16  shows a block diagram of a quadrature signal generator (specifically, a single-sideband quadrature signal generator)  600   a  suitable for use in converter  310 . Phase shifters  210  and  220  (which may be constructed in the same fashion as phase shifter  110 ) receive upper frequency oscillator signal S 160  and lower frequency oscillator signal S 170 , respectively, and present quadrature pairs to mixers  230 – 260  (which may also be constructed as described above). With the polarities as shown in  FIG. 16  at the inputs to combiners  270  and  280 , the frequency of in-phase generator signal S 140  and quadrature generator signal S 150  (designated above as ω g ) may be expressed as (ω U −ω L ).  FIG. 17  shows an alternate structure for a quadrature signal generator  600   b  wherein the frequency of in-phase generator signal S 140  and quadrature generator signal S 150  may be expressed as (ω U +ω L ). Several other structures for the quadrature signal generator are possible. 
   One advantage that the use of a quadrature signal generator (e.g. as shown in  FIG. 16  or  17 ) may provide to a converter  310  is that the phase relation between in-phase generator signal S 140  and quadrature generator signal S 150  remains substantially constant even in situations where the frequency of upper frequency oscillator signal S 160  and/or lower frequency oscillator signal S 170  drifts. This constancy may allow converter  310  to maintain a high level of image rejection performance even as such frequency drifts occur (due, for example, to changes in ambient temperature, localized heating, component aging, and/or variations in supply voltage). As a consequence, a structure that is less ideal in terms of frequency drift but is preferred in terms of other design criteria (such as cost or chip area consumed) may be used for one or both of oscillators  520  and  530  to obtain a desired conversion performance in a converter according to an embodiment of the invention. 
     FIG. 18  shows a block diagram of a system that includes a converter  320  according to an embodiment of the invention and two oscillators: upper frequency oscillator  550  and lower frequency oscillator  560 . This configuration may be used in an application where one or more oscillators are already available. In a receiver that processes other RF signals in addition to RF signal S 10 , for example, one or more local oscillators may already be available for use as upper frequency oscillator  550  or lower frequency oscillator  560 . 
   In an exemplary application of converter  320 , RF signal S 10  is a Global Positioning Satellite (GPS) signal having a carrier frequency of 1.57542 GHz, upper frequency oscillator  550  is a UHF local oscillator used in the reception of cellular telephone signals, and lower frequency oscillator  560  is a voltage-controlled oscillator (VCO). Upper frequency oscillator  550  may have a frequency in the approximate range 800–1200 MHz for cellular band applications or in the approximate range 1600–2200 MHz for PCS (Personal Communications System) applications. A frequency of lower frequency oscillator  560  may be selected based on such factors as the desired GPS IF frequency (e.g. 120–200 MHz), the desired frequency of in-phase and quadrature generator signals S 140  and S 150 , and the particular configuration used for image reject mixer  200 . In a case where the frequency of upper frequency oscillator  550  may change (e.g. to switch between cellular and PCS applications), an output frequency of lower frequency oscillator  560  may also be switchable (e.g. in conjunction with that of upper frequency oscillator  550 ). 
   The foregoing presentation of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well. For example, an embodiment of the invention may be implemented in part or in whole as a hard-wired circuit or as a circuit configuration fabricated into an application-specific integrated circuit, alone or in combination with other analog and/or digital circuitry. Likewise, other embodiments may be implemented in part or in whole as a firmware program loaded into non-volatile storage or a software program loaded from or into a data storage medium as machine-readable code, such code being instructions executable by an array of logic elements such as a microprocessor or other digital signal processing unit. 
   Additionally, while receiving applications are discussed, embodiments of the invention may be used in transmitting applications as well. Moreover, the embodiments of the invention are not limited to any particular construction technique or frequencies that may be mentioned in a description of an exemplary implementation. For example, an image reject mixer as used in a converter according to an embodiment of the invention may also include one or more lowpass, highpass, or bandpass filters to attenuate undesired components. Likewise, each among the various different configurations of a mixer coupled to a phase shifter that may be implemented in a signal path of an image reject mixer (e.g. as illustrated in  FIGS. 7  [phase shifter  110  and mixer  30  or  40 ],  10  [phase shifter  120  and mixer  30  or  40 ],  11  [mixer  30  and phase shifter  130 ], and  14  [e.g. phase shifter  130   a  and mixer  30 ]) may be characterized generically as a mixer/phase shifter combination that produces an output component signal. Thus, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein.