Abstract:
A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to flood mode testing of SRAM cells, and more particularly, to flood mode testing of SRAM cells, which use a continuous bitline approach to read/write the cells. 
   DESCRIPTION OF THE RELATED ART 
   Flood mode testing is used to weed out marginal Static Random Access Memory (SRAM) cells in an array. Marginal SRAM cells are memory cells that are weak and unstable. These unstable cells can cause inaccurate reads and/or writes of the specific array. Flood mode testing involves stressing the cell to a condition that is worse than what could be found in normal test operations. This makes the marginal cells easy to detect. Once the marginal cells are found, then the functional cells can be mapped to the spare or redundant cells in the array. This testing eliminates potential failures in the design; downstream in the manufacturing flow, or worse yet, in the consumer product. 
   SRAM cells are used to store bits of data. A bit once written in a SRAM cell stays there until rewritten or until the power of the cell is turned off. Referring to  FIG. 1  of the drawings, the reference numeral  100  generally designates a conventional SRAM cell. The wordline  102  is connected to the gates of two N-Channel Field Effect Transistors (nFET)  108  and  118 . The drain of nFET  118  is the bitline true  104 , while the source is connected to node  132 . The nFET  118  is the transmission device  136 , which when activated by wordline  102  transmits the value of node  132  onto the bitline true  104  in read mode, and transmits the value of bitline true  104  to node  132  in write mode. The drain of another nFET  116  is connected to the node  132 . The source of nFET  116  goes to ground  120 , and the gate of nFET  116  is connected to the gate of a P-Channel Field Effect Transistor (pFET)  114 . The drain of this pFET  114  goes to power supply Vdd  126 . The source of pFET  114  is connected to the node  132 , also. This makes up one half of the SRAM cell. 
   The source of nFET  108  is the bitline complement  106 . The drain of nFET  108  is connected to node  134 . The nFET  108  is the transmission device  138 , which when activated by wordline  102  transmits the value of node  134  onto the bitline complement  106  in read mode, and transmits the value of bitline complement  106  to node  134  in write mode. Another nFET  112  has its source connected to node  134 . The drain of nFET  112  goes to ground  120 , and the gate of nFET  112  is connected to the gate of a pFET transistor  110 . The source of pFET  110  is connected to power supply Vdd  124 , and the drain of pFET  110  is connected to the node  134 . One line of wire  130  connects node  134  to the gates of nFET  116  and pFET  114 . Alternatively, another wire  128  connects node  132  to the gates of nFET  112  and pFET  110 . 
   An SRAM cell can be used to read bits from the cell or write bits into the cell. After a flood mode cycle, the read operation is used to detect the marginal cells. However, the read operation is not used to induce the flood mode cycle, so it will not be described in this disclosure. The write operation is integral to flood mode testing and must be understood. Referring to  FIG. 2  of the drawings, the reference numeral  200  depicts a timing diagram illustrating the write operation in a conventional SRAM cell. The process begins with precharging the bitline true  104  to a level, typically the high supply. On the timing diagram  200 , the bitline true  104  begins at the high supply and the bitline complement  106  begins at the low supply. After the bitlines  104  and  106  are precharged the write driver is activated, which forces bitline true  104  to the low supply and the bitline complement  106  to the high supply. This is indicated in the timing diagram  200  by the change in levels. Next the wordline  102  pass devices and a driver are activated to force new data into the SRAM cell. This step is depicted in the timing diagram  200  by the rise of the wordline  102  to the high supply. Directly after that with a small time delay, the true and complement nodes in the SRAM cell are potentially forced to new levels. The true and complement lines illustrate the switching of the internal nodes of the SRAM cell. The next step in the process involves turning off the wordline  102  pass devices and driver, which moves the wordline to the low supply. The last step in the write operation is powering on the bitline precharge devices again to prepare for another write operation. Overall, when the write is activated, the bitlines  104  and  106  engage to write the SRAM cell to either a “1” or a “0”, thus updating the value of the SRAM cell. 
   Conventional methods of flood mode testing use the write operation to induce flood mode, which stresses the marginal cells. SRAM cells that are properly functioning do not show this stressed condition. As previously described, this flood mode testing insures a stress condition of the marginal cells that is more easily detected than under normal test operations. This makes it simple to weed out the marginal cells. Once the marginal cells are weeded out, then they can be mapped to spare or redundant cells in the array. 
   SUMMARY OF THE INVENTION 
   The present invention provides a method, an apparatus, and a computer program product for flood mode implementation for SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing consists of stressing the SRAM cells of an array so that the marginal SRAM cells can be easily detected. With the new implementation of the continuous bitline in local evaluation circuits a new method of flood mode testing is needed. 
   This invention achieves flood mode testing by beginning with a normal write operation for the specific SRAM cells. After the write operation has forced new data values into the SRAM cells, the write signal is chopped off. A delay block is used to keep the wordline signal high after the write signal is chopped off, which initiates flood mode. The SRAM cells become stressed and marginal SRAM cells with a low data value try to return to the high supply. The marginal SRAM cells are easy to detect at this juncture and can later be mapped to redundant cells. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a conventional Static Random Access Memory (SRAM) cell; 
       FIG. 2  is a timing diagram illustrating a write operation in an SRAM cell; 
       FIG. 3  is a block diagram illustrating the continuous bitline approach in local evaluation circuit design; 
       FIG. 4  is a timing diagram illustrating a modified flood mode stress operation in an SRAM cell, which uses a continuous bitline approach to read/write to the cell; 
       FIG. 5  schematically depicts a circuit that is designed to induce the flood mode stress operation in an SRAM cell; and 
       FIG. 6  is a flow chart illustrating the process of forcing an SRAM cell into flood mode. 
   

   DETAILED DESCRIPTION 
   In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electromagnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art. 
   Flood mode testing recognizes that an SRAM cell designed in Silicon On Insulator (SOI) technology is in its least stable condition immediately after a write operation. If a memory cell has been in a state for a while, the body voltages go to values consistent with that state. Thus, the cell favors the previous state for a number of cycles after it has been written to another state. Processing defects can affect the symmetry of the cell and cause one state to be favored over the other. These defects may be such that the cell disruption is only possible when the cell is in the “just written” condition. Further, the time that the cell is affected by the defect induce asymmetry will have frequency dependency. In many cases the test operation is required to be run at very high frequency, which may be difficult for wafer type testers. Because of this phenomenon, conventional testing alone may not be able to detect these marginal cells. 
   A continuous bitline local evaluation circuit was designed to evaluate a group of SRAM cells in an array. The previous flood mode testing was done with SRAM cells that did not incorporate a continuous bitline. The continuous bitline approach is an SRAM cell design that replaced the two bitlines (bitline true  104  and bitline complement  106 ) with one bitline true and a continuous bitline. The continuous bitline is wired to a group of the SRAM cells in an array and only connects to one side of the SRAM cells. The advantages of the continuous bitline approach are less wiring, higher performance, and less noise. Due to the new continuous bitline approach, a new method of flood mode testing was needed to weed out marginal cells. Previous methods of flood mode testing were not effective at implementing this, because they did not take into account the continuous bitline in a dynamic bitline approach. 
   Referring to  FIG. 3  of the drawings, reference numeral  300  depicts a block diagram illustrating the continuous bitline approach in local evaluation circuit design. SRAM Cell 0   304  and SRAM Cell 1   322  are memory cells that exist in an array. These SRAM cells  304  and  322  correspond to reference numeral  100  in  FIG. 1 , but with the bitline true  104  and the bitline complement  106  combined into one bitline (bitline true 0   310  or bitline true 1   320 ) and a continuous bitline  306 . The local evaluation circuit  308  is designed to write or read data to or from the SRAM cells  304  and  322 . The continuous bitline  306  is connected to the local evaluation circuit  308  and all of the other SRAM cells in an array.  FIG. 3  illustrates that the continuous bitline  306  is connected to SRAM cells  304  and  322 . The continuous bitline  306  is used to pull down the bitline signals  310  and  320  from the SRAM cells. The bitline true 0   310  is connected to the local evaluation circuit  308  and provides the data value of SRAM cell 0   304 . The bitline true 1   320  is connected to the local evaluation circuit  308  and provides the data value of SRAM cell 1   322 . Wordline 0   302  provides the signal that controls the read and write operations of SRAM Cell 0   304 . Wordline 1   324  provides the signal that controls the read and write operations of SRAM Cell 1   322 . These wordlines  302  and  324  correspond to reference numeral  102  in  FIG. 1 . The local evaluation circuit  308  must have a precharge signal  312  and a write signal  316  as inputs. The precharge signal  312  is used to precharge the bitlines before a read or write operation. The write signal  316  is used to read or write to the particular SRAM cells  304  and  322 . 
   Referring to  FIG. 4  of the drawings, reference numeral  400  is a timing diagram illustrating a modified flood mode stress operation in an SRAM cell, which uses a continuous bitline approach to read/write to the cell. This flood mode cycle is accomplished by starting with a write mode operation  200 , and then chopping off the write signal  316 -before the wordline  302  or  324  returns to the low supply. This modified stress operation begins with the write signal  316  going to the high supply. This forces the bitline true  310  or  320  to go to the low supply. Subsequently, the wordline signal  302  or  324  is forced to the high supply. This forces new data values into the SRAM cells  304  or  322 , just like a normal write operation ( FIG. 2 ). This is depicted by the true and complement lines switching data values. Then, the write signal  316  is chopped off, which forces the bitline true  310  or  320  to the high supply. The wordline  302  or  324  remains at the high supply, which causes flood mode of the SRAM cell. The SRAM cell is flooded with charge at the time the body voltages are at their absolute worst case values. The stress point is shown in  FIG. 4  as the true line (value of the SRAM cell) tries to return to the high supply. If a marginal SRAM cell has a data value of “0,” then it will show this stress condition. This stress condition is caused because the marginal SRAM cells want to go to the high supply due to the charge of the cell. In turn, marginal cells can be detected by this stress condition, and removed from the device. This stress condition of the weakened cells is worse then what could be found in normal test operations. 
   Conventional flood mode testing uses a sense amp design, consisting of two bitlines used to read, and sense the array. Two bitlines were needed because there is a bitline true signal and a bitline complement signal. This modified flood mode testing uses a sense amp design, consisting of one continuous bitline  306 , and an additional write bitline signal  316 . 
   Referring to  FIG. 5  of the drawings, reference numeral  500  generally designates the circuit that is designed to induce the flood mode stress operation in an SRAM cell. This circuit  500  consists of two smaller circuits. One circuit is designed to delay the wordline signal  302  or  324  and produce the flood mode cycle. This delay circuit is connected to a write circuit  550  that controls the read and write operations of the SRAM cells. A flood enable signal  502  that enables the flood mode cycle is input into the circuit  500 . The flood enable signal  502  and a clock signal  504  are inputs of a NAND gate  506 . The output of NAND gate  506  feeds an inverter  508 . Eight inverters  508 ,  510 ,  512 ,  514 ,  516 ,  518 ,  520 , and  522 , connected in series make up the delay block  560 , which causes the delay that produces the flood mode cycle. The time delay of these inverters causes the wordline  302  or  324  to remain high for a period of time after the write signal  316  is chopped off. The delay block  560  can consist of any number of logical gates. If more inverters are added to the delay block  560 , then the wordline  302  or  324  remains high for a longer period of time. The delay block  560  is used to control the length of the flood mode. The output of inverter  522  is the flood mode write signal  530 . 
   The flood mode write signal  530  is then fed into the write circuit  550  having two, three-input NAND gates  536  and  538 . The inputs to NAND gate  536  are the clock signal  504 , a data in signal  532 , and the flood mode write signal  530 . The inputs to NAND gate  538  are the clock signal  504 , the complement of the data in signal  532 , and the flood mode write signal  530 . An inverter  534  is connected to the data in signal  532  to provide the complement of the data in signal  532 . The output of NAND gate  536  is fed into an inverter  540 . This inverter  540  is connected to another inverter  542 . The output of inverter  542  is the continuous bitline signal  546 , which corresponds to reference numeral  306  of  FIG. 3 . The output of NAND gate  538  is fed into inverter  544 . The output of inverter  544  is the write signal  548 , which corresponds to reference numeral  316  of  FIG. 3 . 
   Overall, when this circuit  500  is put into flood mode, it executes a normal write operation, and then at a time determined by delay block  560  forces off the write operation. The wordline  302  or  324  remains high, forcing the array into flood mode. During the flood mode cycle the flood mode write signal  530  inputs a “0” into the NAND gates  536  and  538 , which turns these NAND gates off. When the NAND gates are turned off, the continuous bitline  546  goes to Vdd and the write signal  548  goes to ground, and the flood mode cycle begins. 
   Referring to  FIG. 6 , reference numeral  600  is a flow chart illustrating the process of forcing an SRAM cell into flood mode. The process begins in step  602  by forcing the write signal to the high supply. After the write signal goes to the high supply in step  602 , the bitline true goes to the low supply in step  604 . Subsequently, the wordline signal is forced to the high supply in step  606 . When the wordline signal goes to the high supply in step  606 , new data values are forced into the SRAM cells in step  608 . Then, in step  610 , the write signal gets chopped off and the wordline remains at the high supply. The delay block  560  is implemented to keep the wordline high. This forces the bitline true to the high supply and flood mode begins in step  612 . In flood mode the marginal SRAM cells in the array show stress in step  614 . When the marginal SRAM cells show stress in step  614 , it is easy to test for the marginal SRAM cells in step  616 . After the marginal cells are detected, they can be mapped to redundant cells in the array. 
   This process is needed to detect marginal SRAM cells. If marginal cells are not are not detected at test time, then the specific device does not produce a reasonable yield. Due to a new continuous bitline approach to local evaluation circuits, a new flood mode testing method was needed, and this invention provides exactly that. 
   It is understood that the present invention can take many forms and embodiments. Accordingly, several variations of the present design may be made without departing from the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying concepts on which these programming models can be built. 
   Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.