Abstract:
A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

Description:
FIELD OF THE INVENTION 
     This invention relates to semiconductor device fabrication, in particular, simultaneous fabrication of nanocrystal and non-nanocrystal devices. 
     BACKGROUND OF THE INVENTION 
     Nanocrystals are known to effectively store small amounts of electric charge in microscopic metal or semiconductor particles involving only a few atoms. Nanocrystal devices may be exceedingly small since the charge storage structures have nanometer size. 
     Fabrication of nanocrystal devices usually requires that the thermal temperature of processing or annealing steps be as low as possible since high temperatures may cause increased dopant diffusion that adversely affects the performance of the fabricated device. Therefore, it would be advantageous to provide a fabrication flow for simultaneous fabrication of nanocrystal devices and non-nanocrystal devices where the subsequent thermal treatment will not alter properties of nanocrystals. 
     SUMMARY OF THE INVENTION 
     In one embodiment of the invention, a method of simultaneously fabricating two semiconductor devices, at least one of which is a nanocrystal device and at least one of which is a non-nanocrystal device, comprises forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated, removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated, forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate, providing doping in selected areas of the substrate to form source and drain regions for the at least two semiconductor devices being fabricated, thermally treating the substrate following the doping, the thermal treatment not limiting a thermal budget of the fabrication process. A CMOS transistor may be formed in this fashion in one embodiment of the invention. 
     In another embodiment of the invention, method for simultaneously fabricating two semiconductor devices, at least one of which is a nanocrystal device and at least one of which is a non-nanocrystal device, comprises forming a first thermal oxide layer for at least two semiconductor devices being fabricated on at least two portions of a surface of a substrate, forming a nanocrystal layer over the oxide layer of the at least two semiconductor devices being fabricated, masking at least one portion of the substrate associated with the at least one nanocrystal device being fabricated to protect underlying layers while performing fabrication processes for the at least non-nanocrystal device being fabricated, said fabrication processes including removing with an etching process the nanocrystal layer from the at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated, forming a polycrystalline gate for each of the at least two semiconductor devices being fabricated, the exposed nanocrystals not covered by the gate on the at least one portion of the substrate associated with the at least one nanocrystal device consumed by a thermal oxidation process, the thermal oxidation process producing a second thermal oxide, a remaining plurality of nanocrystals forming a floating gate, providing doping in selected areas of the substrate to form source and drain regions for the at least two semiconductor devices being fabricated, and thermally treating the substrate following the doping, the thermal treatment not limiting a thermal budget of the fabrication process. A CMOS transistor may be formed in one embodiment of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1   a  and  1   b  are cross sections of a semiconductor wafer at a starting point of an embodiment of the invention. 
         FIGS. 2   a – 22   a  are cross sections of semiconductor peripheral device structures at selected processing stages according to an embodiment of the invention. 
         FIGS. 2   b – 22   b  are cross sections of semiconductor memory device structures at selected processing stages according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A process for simultaneously fabricating a semiconductor device, such as a memory cell, containing a nanocrystal layer as well as a peripheral semiconductor device (in one embodiment, forming CMOS transistor) that does not contain a nanocyrstal layer is described below. With reference to  FIGS. 1   a – 22   a , exemplary process steps provide detail for fabrication of a peripheral device that does not contain nanocrystals while  FIGS. 1   b – 22   b  provide detail for an exemplary fabrication of a memory cell containing nanocyrstals. 
     In  FIGS. 1   a  and  1   b , a semicondcutor substrate, for example, p-type silicon, is provided. Assuming two semiconductor devices, a peripheral semiconductor device without nanocyrstals ( FIG. 1   a ) and a memory cell with nanocrystals ( FIG. 1   b ) are to be fabricated simultaneously on the substrate, both a portion  10  of the substrate  24  corresponding to the to-be fabricated peripheral device and a portion  12  of the substrate  26  corresponding to the memory cell with nanocyrstals are doped in the usual way for formation of a MOS or CMOS EEPROM device. Shallow trench isolation (“STI”) regions  14 ,  54 ,  56 , and  58 , well known in the art, are implanted within the relevant portions  24 ,  26  of the substrate to define the active area of the devices. Other isolation methods may be employed in other embodiments. Before layers are formed on the substrate, the surface of the substrate is prepared in the usual way by, for example, a chemical mechanical planarization (“CMP”) polishing. 
     In  FIGS. 2   a  and  2   b , a layer of thermal oxide  16  (such as tunnel or gate oxide) having a target thickness of about 60 Å is deposited. Before a nanocrystal layer is deposited, oxide surface hydroxylation is performed after the oxide surface is etched to less than 20 Å by exposing the oxide to 0.05% hydrofluoric acid for 300 seconds. 
     The nanocrystal layer  18  with nanocrystals approximately 40 Å in diameter is then formed. In one embodiment, the nanocrystal layer is formed by CVD deposition of an insulating layer such as oxide, nitride, or oxynitride. Silicon atoms may be implanted into this dielectric material. This layer is annealed to further improve properties of silicon nanocrystals. This thermal processing step does not limit the thermal budget of further fabrication processes because other semiconductor devices which are usually compromised by dopant diffusion are not in place. (Other methods of nanocrystal formation known in the art may also be used.) 
     After the nanocrystal layer  18  has been formed, a layer of control dielectric  20  is formed on top of the nanocrystal layer. In one embodiment, the layer of control dielectric  20  is formed by the deposition of one layer of oxide, one layer of nitride, and one layer of oxynitride (i.e., an ONO layer), where each of these layers is 40 Å thick. 
     In  FIG. 3   b , a first photoresist layer  22  is formed over the to-be-fabricated memory cell array  12  to protect the underlying layers  16 ,  18 ,  20  from fabrication steps carried out on the portion of the substrate  24  corresponding to the to-be-fabricated peripheral semiconductor device without nanocrystals. The mask layer is removed from the portion  24  of the to-be-fabricated peripheral semiconductor device  10  without nanocrystals shown in  FIG. 3   a.    
     In  FIG. 4   a , the control dielectric and nanocrystal layers are removed from the section  10  of the substrate  24  corresponding to the to-be-fabricated peripheral semiconductor device without nanocrystals. For example, a wet/dry etch removes the control dielectric and a wet etch removes the nanocrystal layer. In other embodiments, other processes known to those skilled in the art may be used to remove the dielectric and nanocrystal layers. 
     In  FIG. 5   b , the photo resistive mask layer is stripped. The underlying layers are cleaned using a known cleaning process such as SCI or SC 2  and the gate oxide shown in  FIGS. 5A and 5   b  is subject to a standard furnace treatment. After this step, the nanocrystal gate should have a targeted thickness of 50 Å (the targeted thickness may vary in other embodiments). (The original thickness of the control dielectric layer  20  will also increase and needs to be accounted for.) 
     In  FIGS. 6   a  and  6   b , a layer of polysilicon  28  is deposited over both portions  10 ,  12  of the substrate  24 ,  26 . In  FIGS. 7   a  and  7   b , a second layer of photoresist  30  is applied to mask the portion of the substrate  24  corresponding to the to-be-fabricated peripheral semiconductor device  10  and part of the portion  12  of the substrate  26  associated with the to-be-fabricated memory cell, specifically, the cell transistor. 
     In  FIG. 8   b , the polysilicon layer  28  not protected by the photoresist layer  30  is etched away by a standard dry etch. In  FIG. 8   a , the polysilicon layer  28  is unaffected since it is protected by the second photoresist layer  30 . 
     In  FIG. 9   b , the portion of the control dielectric layer  20  not protected by the second photoresist layer  30  is removed by a wet (dry) etch or a dry/wet etch. This exposes the underlying nanocrystal layer  18 . In  FIG. 9   a , the portion  10  of the substrate  24  associated with the to-be-fabricated peripheral semiconductor device is unaffected due to the second photoresist layer  30 . 
     In  FIGS. 10   a  and  10   b , the second photoresist layer is removed. In  FIG. 11   b , a second thermal oxide layer  32  is grown, consuming the exposed nanocrystals. Mechanisms for thermal oxide growth are well understood. About 44% of underlying silicon is consumed to form a thermal silicon dioxide. At standard ambient temperatures (e.g., 68° C.), thermal oxide will grow to about 1 nm (10 Å, known as “native oxide”), consuming about 0.44 nm (4.4 Å) of underlying silicon. By elevating a processing temperature, for example, in a rapid thermal processor or diffusion furnace, the exposed nanocrystals are entirely consumed. In one specific embodiment, an Applied Materials ISSG diluted wet oxidation oxide chamber is used with a temperature of about 800° C.–900° C. for 10–30 seconds. Therefore, the second thermal oxide  32  is comprised of consumed nanocrystals. In  FIGS. 12   a  and  12   b , an oxide etch completely removes the layer of oxide from the surface of areas where the source and drain will be formed. 
     In  FIG. 13   a , a third layer of photoresist  60  is applied to mask the area  10  of the substrate  24  corresponding to the peripheral semiconductor device to be manufactured. In  FIG. 13   b , the third layer of photoresist  60  is applied over the entire area  12  of the substrate  24  associated with the to-be-manufactured memory cell. In  FIG. 14   a , the gate polysilicon  28  and tunnel oxide  16  are etched away except for the gate region protected by the photoresist  60 . In  FIG. 14   b , the etching process has no effect due to the presence of the third photoresist layer  60 . In  FIGS. 15   a  and  15   b , the third photoresist layer  60  is stripped. 
     A temporary oxide spacer  34  is deposited in  FIGS. 16   a  and  16   b  (by CVD or PECVD). In  FIGS. 17   a  and  17   b , the temporary spacer is removed by a dry etch process, leaving only a portion of the oxide spacer  34  on the sides of the peripheral device  10  and memory cell  12  being fabricated. 
     In  FIGS. 18   a  and  18   b , the source and drain regions  42 ,  36 ,  44 , and  46  of the to-be-fabricated peripheral devices  10  and the to-be-fabricated memory cells  12 , respectively, are formed by ion implantation (or diffusion in other embodiments). If dopants are implanted, a thermal annealing process is performed after implantation, in one embodiment, at 900° C.–1100° C. for typically 10 sec—several minutes. The temporary spacers are removed by a standard wet etch process in  FIGS. 19   a  and  19   b.    
     In  FIGS. 20   a  and  20   b , source/drain extensions  48 ,  38 ,  50 ,  52  (so called LDD) are implanted. 
     In  FIGS. 21   a  and  21   b , a nitride layer  40  is deposited. In  FIGS. 22   a  and  22   b , the nitride layer  40  is dry etched using a standard dry etch such that spacers  40  are formed on the sides of the gate stacks of both the peripheral device and memory cell structures  10 ,  12 . 
     In the foregoing specification, the present invention has been described with reference to specific embodiments. It will, however, be evident to a skilled artisan that various changes and modifications can be made to these embodiments without departing from the broader spirit and scope of the present invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.