Abstract:
A high speed multiplier, such as for video signals features cascaded ROMs. Each ROM is divided into pages, and each page contains different multiplying coefficients. Different significant bits of a control signal are applied to each ROM to select a page for processing the video signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to digital signal processing, and more particularly, to multiplication of digital video signals. 
     Multiplication is a common signal processing function for video signals. Increasingly, video signals are in digital form, typically with 8-bit (256 grey scale levels) resolution. If it is desired to multiply an 8-bit digital signal by an 8-bit control signal (which can be another video signal, a shading signal, etc.), the resulting product signal has 16 bits (65,536 grey levels). Since a 16-bit signal cannot be transmitted through an 8-bit system, some of the output bits of the multiplier must be discarded. In particular, the 8 least significant bits would be discarded, leaving the 8 most significant bits to represent the product signal. Since the multiplier is capable of a 16-bit product signal, this discarding makes poor utilization of the relatively expensive multiplier. 
     One way of making a digital multiplier is to construct a look up table using a ROM (read only memory). The 8-bits each input and control signals can be considered as a single 16-bit address word, which word can &#34;look up&#34; 65,536 locations of data. But, again, if the product signal is restricted to an 8-bit word, then there are more locations of data than there are unique data words. 
     Another way of multiplying a signal is to use a microprocessor controlled RAM (random access memory) such as shown in U.S. patent application Ser. No. 286,264, filed July 23, 1981, in the name of R. A. Dischert and assigned to the assignee of the present application. In this system, the RAM is loaded with transfer coefficients (such as a multiplier) by the microprocessor (or, in an alternate embodiment, a hardwired circuit) during the vertical blanking interval or during several horizontal blanking intervals. Such a system may not be fast enough to do multiplication of a video signal where the multiplier signal is changing during a horizontal line, such as when the multiplier signal is a shading signal or another video signal. 
     It is therefore desirable to multiply large bandwidth signals in an inexpensive manner that makes full use of the circuits employed to do so. 
     SUMMARY OF THE INVENTION 
     Method and apparatus for processing a digital input signal in accordance with a digital control signal, comprising multiplying said input signal by a factor determined by at least one first bit of said control signal and having a given significance to form a first product signal, and thereafter multiplying said first product signal by a factor determined by at least one second bit of said digital control signal and having a significance other than said given significance to form a second product signal. 
    
    
     DESCRIPTION OF THE DRAWING 
     The sole FIGURE is a block diagram of the invention. 
    
    
     DETAILED DESCRIPTION 
     The FIGURE shows an 8-bit (8 input terminals, one for each bit of input signal) input terminal 11 that receives an 8-bit digital video signal. The input signal can be derived from a television camera, video tape recorder, etc., which signal has been digitized (sampled and then quantized) by an analog to digital converter (not shown) as is known in the art. The digital video signal is applied to 8-bits of a 10-bit address input of a 1K by 8 (1024 memory locations of 8 bits each) ROM 12. Such a ROM is type 93451 manufactured by Fairchild Co. and others. The circuit of the invention also has an 8-bit control signal input 10 comprising input terminals 10a, 10b, 10c, 10d, 10e, 10f, 10g, and 10h that respectively receive the MSB (most significant bit) to the LSB (least significant bit) of a multiplier control signal. This control signal can be derived from thumb wheel switches (not shown), a shaft encoder (not shown) that is coupled to knob, an analog to digital converter coupled to a potentiometer (not shown), or can comprise another digital video signal derived in manner stated with respect to the signal at input terminal 11. The two most significant bits are applied to the remaining two address inputs of ROM 12 for control of the attenuation of the signal derived from input terminal 11 in a manner described below. 
     The 8-bit output signal from ROM 12 is applied to 8-bits of the 10-bit address input of 1K by 8 ROM 14, the remaining two bits of the address inputs receiving the next two lower most significant bits of the control signal from input terminals 10c and 10d. In similar manner, the 8-bit output signal from ROM 14 is applied to the address inputs of 1K by 8 ROM 16, the remaining two address inputs receiving the control signal from input terminals 10e and 10f. Finally, the 8-bit output signal from ROM 16 is applied to the address inputs of 1K by 8 ROM 18, the remaining two address inputs receiving the next to least significant bit and LSB of the control signal from inputs 10g and 10h respectively. The digital video output signal from ROM 18 is available at 8-bit output terminal 20 for further processing or for conversion to an analog signal by a digital to analog converter (not shown). 
     Each of the ROMs 12, 14, 16 and 18 can be thought of as being made of 4 smaller ROMs, each of 256×8 size, each smaller ROM being called page 1, 2, 3, and 4 respectively. Page 1 of all ROMs is selected by having the binary signal 11 on the particular pair of control lines at terminal 10 for that particular ROM. It is desired to have no attenuation as a choice. Therefore, on page 1 of all ROMs a value is stored (in binary form) in its own address location. For example: page 1, address 1, value 1; page 1, address 2, value 2, etc. 
     For video signals, it is desired to adjust gain in increments that correspond to the smallest perceivable change in amplitude, which change is about 0.5 percent or 0.05 db. This change equals a multiplier of 0.995 and corresponds to a change that is 1 part in 200 or 46 db down from peak video amplitude. Consider now ROM 18, page 2, which is accessed by having binary 10 at inputs 10g and 10h respectively. The decimal numbers 0 through 255 multiplied by 0.995 are stored in binary from in the same relative locations as for page 1. In page 3 of ROM 18 (binary control signal 01) the decimal numbers 0 through 255 multiplied by 0.995 2  are stored, again in the same relative locations. In page 4 of ROM 18 (control signal 00) the decimal numbers 0 through 255 multiplied by 0.995 3  are stored, again in the same relative locations. 
     Now consider ROM 16. Pages 1, 2, 3 and 4 thereof have multiplying coefficients of 0.995 0 , 0.995 4 , 0.995 8 , and 0.995 12  respectively. (The coefficient for page 1 of 0.995 12  equals one, as discussed above). These coefficients are again multiplied by the decimal numbers 0 through 255, and also the pages are selected using the same binary control signals but now at inputs 10e and 10f. In a similar manner, the pages of ROM 14 have coefficients of 0.995 0 , 0.995 16 , 0.995 32 , and 0.995 48  respectively, the pages being selected by signals at inputs 10c and 10d, while the pages of ROM 12 have respective coefficients of 0.995 0 , 0.995 64 , 0.995 128 , and 0.995 192 , the pages being selected by signals at inputs 10a and 10b. 
     It should be noted that a rounding rule is adopted in order to generate the values stored in the ROMs. This rounding will be applied to the video signal outputs of the ROMs. If the signal at output 20 is to be further processed, it is desirable to carry additional bits and 9-bit word length ROMs may be used. 
     The maximum attenuation for all four ROMs 12, 14, 16, and 18 is equal to 0.995 raised to the power (3+12+48+192)=255 or 0.28 which equals -11 db. Thus, with the above described embodiment, there is an attenuation range of 11 db in 0.05 db steps, which is adequate for the adjustment of transmission levels in a television studio. This is accomplished with a memory or storage of only 4K (1K in each ROM) by comparison with 64K memory which would be required for straight 8-bit by 8-bit multiplication. Of course, the scale factor could be any number that gives the desired level setting resolution e.g., a choice of 0.99 corresponds to approximately 0.1 db steps and gives a control range of about 22 db. Another modification is to add a fifth ROM that precedes ROM 12 and requires two more bits of control (the control word is now 10 bits wide). Using a 0.995 scale factor, a gain control with a 44 db dynamic range and 0.05 db resolution is achieved. If instead of linear gain control (constant db steps) linear amplitude control is desired, a ROM having an exponential transfer function can be placed in the control lines 10. 
     The look-up table multiplier of the present invention can literally multiply one video-bandwidth signal by another video-bandwidth signal, making it possible to control gain pixel-by-pixel, should that be a requirement, such as for shading. Since shading requires only a limited dynamic range (6 to 10 db is adequate), the number of stages can be reduced from the form shown in the drawing. 
     The drawing illustrates a hardware system based on a 1K×8 ROM. Further hardware reduction is certainly possible as higher-density fast-access ROMs become available. Consider a 4K×8 ROM. There are 16 pages of 256×8 in this device and only two such devices would be required to implement this system with the same amount of total attenuation and resolution. 
     In an actual embodiment, latches are provided between the ROMs.