Abstract:
A semiconductor device embodiment may include a plurality of cells each including a transistor therein, the cells also each including a first capacitor electrode therein, the first capacitor electrodes being positioned on an insulating layer, the first capacitor electrodes in adjacent cells being separated from each other. The device may also include partitioning members on the insulation layer, wherein the partitioning members are positioned to separate the cells from one another, and the partitioning members include an upper surface thereon. The device also may include an organic layer on the first capacitor electrodes between the partitioning members, wherein the organic layer is not positioned in contact with the upper surface of the partitioning members. The device may also include a continuous second capacitor electrode on the organic layer, the second capacitor electrode layer formed to be a common electrode for cells. In another aspect, the organic layer may be capable of a polarization inversion by exposure to an electric field. In another aspect, the partitioning members may include first and second layers, the first layer being formed from a material having an affinity for an organic solution used to form the organic layer, the second layer being formed from a material having a non-affinity for the organic solution used to form the organic layer.

Description:
[0001]    This application is a Divisional of U.S. application Ser. No. 09/695,565, filed Oct. 24, 2000, which is hereby incorporated by reference in its entirety. 
     
    
     
       TECHNICAL FIELD  
         [0002]    The present invention relates to devices and techniques for manufacturing devices such as non-volatile memory devices.  
         RELATED ART  
         [0003]    [0003]FIG. 8 shows a cross-sectional structure of a 1T1C (1 transistor+1 capacitor) type non-volatile ferroelectric memory device with a stacked type cell structure. Referring to the figure, a semiconductor substrate  1  is formed with a cell transistor  17  that is mainly composed of a gate electrode  2 , a source region  3  and a drain region  4 , and a device element isolation insulation film  5 . The cell transistor  17  that forms each memory cell is connected to a ferroelectric capacitor  18  through an interlayer insulation film  6 . The ferroelectric capacitor  18  is composed of a lower electrode  7 , a ferroelectric film  19  and an upper electrode  9 , wherein the ferroelectric film  19  is formed from a PZT ferroelectric material, a SBT ferroelectric material or the like. The lower electrode  7  connects to the drain region  4  through a contact hole that is opened in the interlayer insulation film  6 , and the upper electrode  9  connects to a plate line  20  through a contact hole that is opened in an interlayer insulation film  21 . Also, the gate electrode  2  connects to a word line, and the source region  3  connects to a bit line.  
           [0004]    When the non-volatile ferroelectric memory device having the structure describe above is manufactured, for example, as described in Japanese laid-open patent application HEI 7-335840 and Japanese laid-open patent application HEI 11-214626, the cell transistor  17  is formed on the semiconductor substrate  1  using a semiconductor process, and then the ferroelectric capacitor  18  to be connected to the cell transistor  17  is formed using a ferroelectric process such as the Sol-Gel method. A film forming method for the ferroelectric film  19  using the Sol-Gel method is described in detail in  Ferroelectrics , Vol. 116, pp. 79-93, “Recent Result on Switching, Fatigue and Electrical Characterization of Sol-Gel based PZT Capacitors”.  
           [0005]    It is noted that, in the present specification, a ferroelectric process refers to a process for forming a capacitor insulation film composed of, for example, a PZT or SBT ferroelectric material and the like that is used for a ferroelectric capacitor, as well as a film such as an organic thin film that can undergo a polarization inversion by an external electric field.  
           [0006]    However, when the non-volatile ferroelectric memory device having a multiple-layered structure is manufactured by the above-described method, the cell transistor  17  is formed in a lower layer, and then the ferroelectric capacitor  18  is formed above in an upper layer. Accordingly, a problem has been pointed out that the ferroelectric film  19  that is formed from an oxide develops an oxygen deficiency by a reducing atmosphere, and therefore deterioration of its characteristics occurs.  
           [0007]    The characteristic deterioration due to the oxygen deficiency of the ferroelectric capacitor  18  can be restored by a heat treatment conducted under an oxygen atmosphere at temperatures of 550° C.˜600° C. However, a heat treatment cannot be conducted after a process of wiring a low melting-point metal such as aluminum. Furthermore, although PZT based materials are often used for ferroelectric films, non-volatile memory devices may preferably be manufactured with a material that does not contain zinc, in consideration of the pollution of the process line by diffusion of zinc in the manufacturing process.  
           [0008]    Accordingly, it is an object of certain embodiments of the present invention to provide devices and methods for manufacturing a non-volatile memory device with a ferroelectric process that conforms with a semiconductor process for forming cell transistors.  
         SUMMARY  
         [0009]    To solve the problems described above, in accordance with certain embodiments of the present invention, when a non-volatile memory device having a ferroelectric capacitor that is formed from an organic thin film capable of a polarization inversion by an external electric field provided between a lower electrode and an upper electrode is manufactured, a material solution for the organic thin film is coated on the lower electrode, and is solidified to thereby form an organic thin film. According to such embodiments, the film forming temperature of the organic thin film is lower than 150° C.˜200° C., which does not cause damage to cell transistors, and therefore a ferroelectric process that conforms with a semiconductor process is provided.  
           [0010]    The material solution for the organic thin film may preferably include, for example, a material solution containing a copolymer of vinylidene fluoride and trifluoroethylene dissolved in a solvent. An ink jet type recording head may be used to coat the material solution for the organic thin film on the lower electrode, with the result that a highly accurate patterning can be performed.  
           [0011]    Also, in accordance with certain embodiments of the present invention, a material solution that contains fine particles of the upper electrode may be coated on the organic thin film and solidified to thereby form an upper electrode. In this case, an ink jet type recording head may be used to coat the material solution for the upper electrode, with the result that patterning and film formation of the upper electrode can be simultaneously conducted with a high level of precision.  
           [0012]    Also, in accordance with certain embodiments of the present invention, partitioning members to partition lower electrodes provided in respective memory cells may be formed, and the material solution for the organic thin film may be filled over the lower electrodes that are partitioned by the partitioning members and solidified to thereby form the organic thin film. In accordance with such embodiments, cross talk between the memory cells accompanied with a higher integration of memory devices can be prevented.  
           [0013]    In certain embodiments described above, an upper layer of the partitioning member may preferably be formed with a material that does not have an affinity for the material solution for the organic thin film. By such a structure, the material solution for the organic thin film can be readily coated. The material with non-affinity may preferably include, for example, polyimide, amorphous silicon, polysilicon or an organic compound including fluorine.  
           [0014]    A preferred device embodiment includes a non-volatile memory device comprising a ferroelectric capacitor that is formed from an organic thin film capable of a polarization inversion by an external electric field and provided between a first electrode and a second electrode. The device also includes partitioning members formed to mutually partition the organic thin film, wherein the partitioning members are formed to include a first insulation layer and a second insulating layer that repels an organic thin film solution used to form the organic thin film.  
           [0015]    Another preferred device embodiment includes a semiconductor device including a ferroelectric capacitor that is provided between a lower electrode and an upper electrode, the semiconductor device comprising a semiconductor substrate including a transistor and an insulation layer on the transistor. A lower electrode is positioned on the insulation layer, wherein the lower electrode is in electrical contact with a part of the transistor. Partitioning members are positioned on the insulation layer, the partitioning members adapted to separate the lower electrode from other lower electrodes, the partitioning members including an upper surface. The device also includes a solid organic layer on the lower electrode that is partitioned from other lower electrodes by the partitioning members, wherein the solid organic layer is not positioned on the upper surface of the partitioning members.  
           [0016]    Another preferred device embodiment includes a semiconductor device, comprising a plurality of cells each including a transistor therein, the cells also each including a first capacitor electrode therein, the first capacitor electrodes being positioned on an insulating layer, the first capacitor electrodes in adjacent cells being separated from each other. The device also includes partitioning members on the insulation layer, wherein the partitioning members are positioned to separate the cells from one another, the partitioning members including an upper surface. The device also includes an organic layer on the first capacitor electrodes between the partitioning members, wherein the organic layer is not positioned in contact with the upper surface of the partitioning members. The device also includes a continuous second capacitor electrode on the organic layer, the second capacitor electrode layer formed to be a common electrode for the cells. 
       
    
    
     BRIEF DESCRIPTOIN OF THE DRAWINGS  
       [0017]    [0017]FIG. 1 shows a cross-sectional view of a non-volatile memory device in accordance with a first embodiment of the present invention.  
         [0018]    [0018]FIG. 2 shows a plan view of the non-volatile memory device in accordance with the first embodiment of the present invention.  
         [0019]    [0019]FIG. 3 shows cross-sectional views of the non-volatile memory device in a manufacturing process in accordance with the first embodiment of the present invention.  
         [0020]    [0020]FIG. 4 shows a cross-sectional view of a non-volatile memory device in accordance with a second embodiment of the present invention.  
         [0021]    [0021]FIG. 5 shows a plan view of the non-volatile memory device in accordance with the second embodiment of the present invention.  
         [0022]    [0022]FIG. 6 shows cross-sectional views of the non-volatile memory device in a manufacturing process in accordance with the second embodiment of the present invention.  
         [0023]    [0023]FIG. 7 shows cross-sectional views of the non-volatile memory device in a manufacturing process in accordance with the second embodiment of the present invention.  
         [0024]    [0024]FIG. 8 shows a cross-sectional view of a conventional non-volatile memory device.  
         [0025]    [0025] 1  . . . Semiconductor substrate  
         [0026]    [0026] 17  . . . Cell transistor  
         [0027]    [0027] 7  . . . Lower electrode  
         [0028]    [0028] 8  . . . Organic thin film  
         [0029]    [0029] 9  . . . Upper electrode  
         [0030]    [0030] 10  . . . Memory cell array  
         [0031]    [0031] 15  . . . Ink jet type recording head  
         [0032]    [0032] 18  . . . Ferroelectric capacitor  
     
    
     DETAILED DESCRIPTION  
       [0033]    Hereunder, a first embodiment of the present invention is described with reference to FIGS. 1 through 3.  
         [0034]    [0034]FIG. 1 shows a cell cross-sectional structure of a non-volatile memory device in accordance with the present embodiment. The non-volatile memory device shown in the figure has a stacked type cell structure, in which a cell transistor  17  formed from a gate electrode  2 , a source region  3  and a drain region  4  and an element isolation insulation film  5  are formed over a semiconductor substrate  1 , and a ferroelectric capacitor  18  is formed above in an upper layer through an interlayer insulation film  6 . The ferroelectric capacitor  18  is composed of a lower electrode  7 , an organic thin film  8  and an upper electrode  9 . The organic thin film  8  is formed from an organic material having a spontaneous polarization, and can undergo a polarization inversion in response to a voltage applied to the organic thin film  8  by the upper electrode  9  and the lower electrode  7 . By utilizing the polarization characteristic, data reading/writing can be conducted.  
         [0035]    A copolymer of vinylidene fluoride and trifluoroethylene, described in PCT publication WO99/12170, for example, can be used as an organic material that forms the organic thin film  8 . The mixing ratio of the two may be changed to adjust the characteristic of the organic thin film  8 , and the above-described copolymer has a smaller anti-electric filed than a polymer of vinylidene fluoride and a more squared hysteresis loop.  
         [0036]    [0036]FIG. 2 shows a plan view of the non-volatile memory device described above. A memory cell array  10  has a plurality of the lower electrodes  7  disposed in an array form in a specified region (a memory cell assembly section), that are etched in a specified configuration. Also, an upper electrode  9  is formed in a manner to cover the plurality of the lower electrodes  7  across the entire surface of the memory cell assembly section. In this structure, the upper electrode  9  plays a role of an electrode (a common electrode) commonly shared by all of the memory cells.  
         [0037]    Also, a variety of connection terminals  11  such as address terminals for peripheral circuits such as drivers to access respective memory cells, data input/output terminals and the like are provided in a peripheral section of the memory cell array  10 .  
         [0038]    Next, a process of manufacturing a non-volatile memory device is described with reference to FIG. 3. As shown in (A) of the same figure, by utilizing a known semiconductor process, a silicon oxide film is formed over a semiconductor substrate  1 , impurity ions are implanted, and a polycrystal silicon film containing phosphorous is formed and patterned to thereby form a gate electrode  2 , a source region  3 , a drain region  4  and the like to form a cell transistor  17 , an element isolation insulation film  5  and an interlayer insulation film  6 . Furthermore, contact holes that communicate with the drain region  4  are opened in the interlayer insulation film  6 , and an aluminum film is formed by a sputtering method over the interlayer insulation film  6  and thereafter patterned in an array configuration to form a plurality of lower electrodes  7  in a memory cell assembly section.  
         [0039]    Then, organic materials having the above-described spontaneous polarization are dissolved in a specified solvent to make an organic thin film material solution  80 , which is then coated over the entire surface of the memory cell assembly section over the lower electrodes  7  by using an ink jet type recording head  15  ((B) of the same figure). The organic thin film material solution  80  acts as a precursor material to obtain an organic thin film  8  in succeeding steps. A solvent to dissolve the organic materials includes PGMEA, cyclohexane, carbitol acetate and the like. Glycerin, diethylene glycol, ethylene glycol and the like may be added as a wetting agent or a binder as required. To eject the organic thin film material solution  80  through the ink jet type recording head  15 , its viscosity may preferably be lower than several centipoise and its surface tension is in a range between 20 dyn/cm˜70 dyn/cm.  
         [0040]    Since an area to be coated with the organic thin film material solution  80 , in other words, an area of the memory cell assembly section, is greater than an area occupied by each memory cell, patterning and coating thereof by an ink jet type recording head are possible. By the patterning process that is conducted with the ink jet type recording head, the organic thin film material precursor material  80  can be coated at any specified location and with any specified thickness on a pattern forming surface with a low cost facility. The ink jet type recording head can be of a piezo-jet type in which required fluid is ejected by changing the volume of a piezoelectric element, or of a bubble jet type in which required fluid is ejected by rapidly generating vapor by an application of heat. The organic thin film material solution  80  is coated on the respective lower electrodes  7  that are disposed in an array, and then is dried by a heat treatment at temperatures of 150° C.˜200° C. As a result of this treatment, the solvent composition of the organic thin film material solution  80  evaporates and solidifies to become an organic thin film  8  ((C) of the same figure).  
         [0041]    Then, fine particles of metal that composes an upper electrode, such as, for example, fine particles of aluminum are dissolved in an appropriate solvent to make an upper electrode material solution  90 , which is coated over the organic thin film  8  using the ink jet type recording head  15  ((D) of the same figure). The upper electrode material solution  90  acts as a precursor material to form an upper electrode  9  in succeeding steps. A solvent to dissolve the aluminum particles includes butyl carbitol acetate, 3-dimethyl-2-imidazolyzen, BMA and the like. Then, the upper electrode material solution  90  coated over the organic thin film  8  is heat-treated to evaporate the solvent composition to thereby form the upper electrode  9  ((E) of the same figure).  
         [0042]    It is noted that a metal that composes the upper electrode  9  includes, in addition to aluminum, RuO 2 , Pt, IrO 2 , OsO 2 , MoO 2 , ReO 2 , WO 2 , YBa 2 Cu 3 O 7 -x, Au, Ag, In, In—Ga alloy, Ga, solder and the like.  
         [0043]    The connecting terminals  11  of the memory cell array  10  obtained in the above-described manufacturing process are connected to peripheral circuits such as drivers, and further sealed by a resin to complete a non-volatile memory device.  
         [0044]    In accordance with the manufacturing method described above, since the organic thin film  8  can be formed and patterned by the ink jet type recording head  15 , the film forming temperature of the organic thin film  8  can be set at lower than 150° C.˜200° C. Therefore, damage that may be inflicted on the cell transistor  17  can be substantially suppressed, compared to the conventional manufacturing method in which a ferroelectric capacitor  18  is formed by the Sol-Gel method that requires a heat treatment at temperatures above 650° C. As a result, since the patterning process for the organic thin film  8  by the ink jet type recording head  15  conforms with the semiconductor process for forming the cell transistor, the problems of the conventional technique described above can be solved.  
         [0045]    Also, in the ferroelectric process using the conventional Sol-Gel method, a process for patterning a ferroelectric film  19  by a lithography method is required. However, in accordance with the present manufacturing method, the organic thin film  8  can be coated and patterned by the ink jet type recording head  15 , and therefore, a lithography process can be omitted. As a result, the manufacturing process can be simplified.  
         [0046]    Also, in the conventional lithography process, steps of coating, exposing and developing a resist are required, such that a large facility investment and a great maintenance cost are required. Furthermore, since the material once coated is removed in an etching step, there is a problem in that a large amount of the material is wasted. However, in accordance with the present manufacturing method, since the film formation and patterning of the organic thin film  8  can be simultaneously conducted by the ink jet type recording head  15 , a large-scale facility such as a factory may not be required, and the manufacturing cost can be substantially lowered because the waste of the material does not occur.  
         [0047]    Also, since the resolution of the ink jet type recording head  15  is very fine, for example, at 400 dpi, any desired patterning and coating can be conducted with a precision on the order of μm. Therefore, minute patterning of the organic thin film  8  is possible, which accommodates a higher integration of memory devices.  
         [0048]    It is noted that, in accordance with the certain embodiments of the present invention, in addition to the ink jet type recording head  15  that is used as a means to coat the organic thin film material solution  80 , a variety of printing methods, a spin-coating method, a spray-coating method and the like can also be used.  
         [0049]    Also, when compared with the conventional technique in which a PZT based material is used for the ferroelectric film  19 , the organic thin film  8  does not contain zinc, and therefore, pollution of the manufacturing process line by diffusion of zinc can be prevented.  
         [0050]    Hereunder, a second device embodiment of the present invention will be described with reference to FIGS. 4 through 7.  
         [0051]    [0051]FIG. 4 shows a cell cross-sectional structure of a non-volatile memory device in accordance with the present embodiment. The non-volatile memory device shown in the figure has a structure basically similar to that of the first device embodiment. Accordingly, the same elements are denoted by the same reference numbers, and their detailed description is omitted.  
         [0052]    The non-volatile memory device of the present embodiment is different from the first embodiment in that partitioning members  14  are formed to mutually partition ferroelectric capacitors  18  formed in respective memory cells one from the other. The partitioning members  14  are provided to prevent cross talk between the memory cells, which may occur with a higher integration of memory devices.  
         [0053]    The partitioning member  14  has a two-layer structure having an interlayer insulation film  12  and a repelling liquid layer  13  disposed thereon. The repelling liquid layer  13  is a thin film that has a property of a large contact angle with respect to the organic thin film material solution  80 , and has a non-affinity for the organic thin film material solution  80 . Since an upper layer of the partitioning member  14  is formed with a material that has a non-affinity for the organic thin film material solution  80 , when the organic thin film material solution  80  is filled in a recessed portion defined by the partitioning members, it is prevented from leaking from the recessed portion to adjacent recessed portions. The repelling liquid layer  13  may preferably be formed from a material, such as, for example, polyimide, amorphous silicon, polysilicon, and an organic compound including fluorine. Also, when a silicon oxide film or a silicon nitride film is used as the interlayer insulation film  12 , because these materials have an affinity for the organic thin film material solution  80 , the organic thin film material solution  80  can be filled well in a recessed portion defined by the partitioning members  14 . Also, when the lower electrode  7  is formed from aluminum, since the organic thin film material solution  80  has an affinity for the lower electrode  7 , it can fill the recessed portions much better.  
         [0054]    [0054]FIG. 5 shows a plan view of the above-described non-volatile memory device. The plurality of lower electrodes  7  that are partitioned in an array configuration by the partitioning members  14  are disposed in a specified region (a memory assembly section) of the memory cell array  10 . An upper electrode  9  is formed in a manner to cover the lower electrodes  7  across the entire surface of the memory cell assembly section. In this structure, the upper electrode  9  plays a role of an electrode (common electrode) commonly shared by all of the memory cells. Also, a variety of connection terminals  11  such as address terminals for peripheral circuits including drivers and the like to access the respective memory cells, data input/output terminals and the like are formed in a peripheral section of the memory cell array  10 .  
         [0055]    Next, another process of manufacturing a non-volatile memory device is described with reference to FIG. 6 and FIG. 7. As shown in FIG. 6(A), by utilizing a known semiconductor process, a gate electrode  2 , a source region  3 , a drain region  4  and the like are formed over a semiconductor substrate  1  to form a cell transistor  17 , and an element isolation insulation film  5  and an interlayer insulation film  6  are formed. Furthermore, contact holes that communicate with the drain region  4  are opened in the interlayer insulation film  6 , and an aluminum film is formed by a sputtering method over the interlayer insulation film  6  and thereafter is patterned in an array configuration to form lower electrodes  7 .  
         [0056]    Then, an interlayer insulation film  12  and a repelling liquid layer  13  are successively deposited over the interlayer insulation film  6  including the lower electrodes  7 , and portions corresponding to the lower electrodes  7  are selectively etched to expose surfaces of the lower electrodes  7  ((B) of the same figure). By this process, partitioning members  14  are formed in a memory cell assembly section. For example, when a silicon oxide film is formed as the interlayer insulation film  12 , such a film can be formed by a plasma CVD method using an organic silane (TEOS) and oxygen as reactive gases, and when a silicon nitride film is formed, such a film can be formed by a plasma CVD method using a silane based gas and nitrogen as reactive gases.  
         [0057]    When polyimide is formed in a film for the repelling liquid layer  13 , an appropriate method such as a lithography method, a printing method or the like can be selected. When a lithography method is used, an organic material may be coated by an appropriate method such as a spin coating, spray coating, roll coating, dye coating, dip coating or the like.  
         [0058]    Subsequently, an organic thin film material solution  80  is filled over the lower electrodes  7  that are partitioned by the partitioning members  14  ((C) of the same figure), and heat-treated to evaporate a solvent composition thereof to form an organic thin film  8  (FIG. 7 (D)). The organic thin film material solution  80  is filled by coating each of the memory cells in an amount that does not flow over the partition members  14 . Then, an upper electrode material solution  90  is coated over each of the memory cells ((E) of the same figure), and heat-treated to evaporate a solvent composition thereof to form an upper electrode  9  ((F) of the same figure). By conducting the steps described above, a memory cell array  10  is formed.  
         [0059]    In accordance with the manufacturing method described above, the partition members  14  are provided to partition the memory cells, such that cross talk between the adjacent memory cells, which may occur with a higher memory device integration, can be effectively inhibited or prevented. Therefore, higher memory device integration becomes possible. Also, since the repelling liquid layer  13  is formed in an upper layer of the partitioning member  14 , the organic thin film material solution  80  can be readily filled over the lower electrodes  7  that are partitioned by the partitioning members  14 .  
         [0060]    In accordance with certain embodiments of the present invention, the film forming temperature for an organic thin film having a spontaneous polarization can be set below 150° C.˜200° C. Therefore, damage that may be inflicted on the cell transistor can be substantially suppressed, compared to the conventional manufacturing method in which a ferroelectric capacitor is formed by the Sol-Gel method that requires a heat treatment at temperatures above 650° C. As a result, the ferroelectric process of the present invention conforms to a semiconductor process for forming cell transistors.  
         [0061]    Also, by the ferroelectric process using an ink jet type recording head, a lithography step can be omitted, with the result that the manufacturing process is simplified and the manufacturing cost is lowered.  
         [0062]    Furthermore, since certain embodiments of the present invention provides a structure in which partition members are provided to partition memory cells, cross talks between the adjacent memory cells, which accompany with a higher memory device integration, can be effectively prevented. Therefore, higher memory device integration becomes possible.  
         [0063]    The present invention is not limited to the embodiments described above, and modifications can be made within the scope of the subject matter of the invention.