Abstract:
A shift register includes a signal input unit for receiving and providing an input signal, a signal output unit for controlling whether outputting a clock signal according to the input signal provided by the signal input unit, and a plurality of stable modules. Each of the stable modules is electrically coupled to an output terminal of the signal input unit, an output terminal of the signal output unit, and a default potential. Each of the stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, such that both the output terminal of the signal input unit and the output terminal of the signal output unit are electrically coupled to the default potential when the input signal is disabled. Before one of the stable modules is disabled, another of the stable modules has already been enabled.

Description:
TECHNICAL FIELD 
     The disclosure relates to shift register circuits, and more particularly to a shift register using a plurality of electronic connections to stabilize signal levels at predetermined times and a driving method thereof. 
     BACKGROUND 
     A shift register circuit for flat panel displays (e.g., liquid crystal displays, LCD) generally includes a plurality of shift registers electrically coupled together by means of cascading. These shift registers orderly generate a plurality of gate driving pulse signals for driving gate wires of LCD. 
     Each class of these shift registers generally includes two complementary stable modules for stabilizing signals output by a signal input unit and a signal output unit of the shift register circuit. Each of the two stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, and thus the stable module is controlled to work. Generally, the operations pulses of the two stable modules are set to be complementary. That is, when the operation signal of one of the two stable modules changes from a logic high level thereof to a logic low level thereof, the operation signal of the other of the two stable modules changes from a logic low level thereof to a logic high level thereof. Thus, when one of the two stable modules works, the other of the two stable modules does not work; and when the not working stable module begins to work, the working stable module stops working. The two stable modules alternately work to stabilize signals output by the signal input unit and the signal output unit. 
     However, since signal delays and Thin Film Transistor (TFT) charging time delays may be generated in the shift register circuit, when an operation signal of either one of the two stable modules changes from the logic low level thereof to the logic high level thereof, a TFT of the stable module that is used to perform potential pull-down and stabilizing operations may not be immediately switched on. That is, when one of the two stable modules stops working, the other of the two stable modules may not immediately begin to work. On the contrary, when the two stable modules are switched, a time during which both the two stable modules do not work may occur. Thus, stability of the shift register circuit may be adversely affected. 
     SUMMARY 
     One embodiment in the disclosure provides a shift register that includes a signal input unit, a signal output unit, and a plurality of stable modules. The signal input unit receives and provides an input signal, and the signal output unit controls whether outputting a clock signal according to the input signal provided by the signal input unit. Each of the stable modules is electrically coupled to an output terminal of the signal input unit, an output terminal of the signal output unit, and a default potential. Each of the stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, such that both the output terminal of the signal input unit and the output terminal of the signal output unit are electrically coupled to the default potential when the input signal is disabled. Before one of the stable modules is disabled, another of the stable modules has already been enabled. 
     Another embodiment in the disclosure further provides a shift register driving method for controlling a potential provided by an output terminal of a shift register. The shifter register includes a signal output unit and a plurality of stable modules. The signal output unit controls whether outputting a clock signal from the output terminal of the shift register according to an input signal. Each of the stable modules is electrically coupled to the output terminal of the shift register and a default potential. The shift register driving method comprises: providing a first operation signal to a first stable module, when the first operation signal is enabled, the first operation signal enabling the output terminal of the shift register to be electrically coupled to the default potential through the first stable module when the input signal is disabled; and providing a second operation signal to a second stable module, when the second operation signal is enabled, the second operation signal enabling the output terminal of the shift register to be electrically coupled to the default potential through the second stable module when the input signal is disabled. The second operation signal is enabled before the first operation signal is disabled, and the second operation signal is disabled after the first operation signal is enabled. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIG. 1  is a block diagram of a shift register according to an exemplary embodiment. 
         FIG. 2  is a circuit diagram of the shift register shown in  FIG. 1 . 
         FIG. 3  is a timing diagram of some signals used in the stable modules of the shift register shown in  FIG. 1  and  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
     Referring to  FIG. 1  and  FIG. 2 , wherein  FIG. 1  is a block diagram of a shift register  100 , according to an exemplary embodiment, and  FIG. 2  is a circuit diagram of the shift register  100  shown in  FIG. 1 . As shown in  FIGS. 1-2 , the shift register  100  includes a signal input unit  110 , a signal output unit  120 , a first stable module  130 , a second stable module  140 , and a discharge unit  150 . 
     The signal input unit  110  is used to generate an input signal Q(n). The signal input unit  110  is electrically coupled to the signal output unit  120 , and thus the signal output unit  120  can generate a first clock signal G(n) according to the input signal Q(n) generated by the signal input unit  110 . Particularly, the signal input unit  110  includes two transistors T 11 , T 12 . The gate of the transistor T 11  is electrically coupled to a previous input signal Q(n−1) generated by a signal input unit of a shift register (not shown) of a previous class. One of the source terminal and the drain terminal of the transistor T 11  is electrically coupled to a previous pulse reference signal HC(m−1), and the other is electrically coupled to the gate of the transistor T 12 . One of the source terminal and the drain terminal of the transistor T 12  is electrically coupled to the a previous first clock signal G(n−1) generated by the signal input unit of the shift register of the previous class, and the other is used as an output terminal of the signal input unit  110  to output the input signal Q(n) generated by the signal input unit  110 . The signal output unit  120  includes a transistor T 2 . The gate of the transistor T 2  is electrically coupled to the output terminal of the signal input unit  110 , one of the source terminal and the drain terminal of the transistor T 2  is electrically coupled to a corresponding pulse reference signal HC(m) thereof, and the other is used as an output terminal of the signal output unit  120  to output the first clock signal G(n) correspondingly generated by the signal output unit  120 . 
     Both the first stable module  130  and the second stable module  140  are electrically coupled to the output terminal of the signal input unit  110 , the signal output unit  120 , and a default potential VSS. The default potential VSS can be set to be a logic low level. The first stable module  130  and the second stable module  140  respectively receives their corresponding first operation signal LC 1  and second operation signal LC 2  such that the first stable module  130  and the second stable module  140  is respectively enabled during working periods of the first operation signal LC 1  and second operation signal LC 2 . Thus, when the input signal Q(n) generated by the signal input unit  110  is disabled, the output terminal of the signal input unit  110  and the output terminal of the signal output unit  120  are electrically coupled to the default potential VSS while the signal output unit  110  or  120  being correspondingly enabled by the first operation signal LC 1  or second operation signal LC 2 . That is, the first stable module  130  and the second stable module  140  can be respectively used as pull-down circuits of the shift register circuit  100 . When the first stable module  130  and the second stable module  140  work (being enabled), they respectively pull potentials of the input signal Q(n) generated by the signal input unit  110  and the first clock signal G(n) generated by the signal output unit  120  down to the default potential VSS (i.e., the logic low level). 
     In the present invention, circuits of the first stable module  130  and the second stable module  140  are substantially similar to each other. A main difference between the first stable module  130  and the second stable module  140  is that the first stable module  130  receives the first operation signal LC 1 , and the second stable module  140  receives the second operation signal LC 2 . 
     Particularly, the first stable module  130  includes transistors T 31 , T 32 , T 33 , T 34 , T 35 , and T 36 . The gate of the transistor T 31  is electrically coupled to the first operation signal LC 1 , one of the source terminal and the drain terminal of the transistor T 31  is also electrically coupled to the first operation signal LC 1 , and the other is electrically coupled to one of the source terminal and the drain terminal of the transistor T 32 . The gate of the transistor T 32  receives the input signal Q(n) generated by the signal input unit  110 , and the other of the source terminal and the drain terminal of the transistor T 32  is electrically coupled to the default potential VSS. The gate of the transistor T 33  is electrically coupled to an electric connection point between the one of the source terminal and the drain terminal of the transistor T 31  and the one of source terminal and the drain terminal of the transistor T 32  that are electrically coupled to each other. One of the source terminal and the drain terminal of the transistor T 33  is electrically coupled to the first operation signal LC 1 , and the other is electrically coupled to one of the source terminal and the drain terminal of the transistor T 34 . The gate of the transistor T 34  also receives the input signal Q(n) generated by the signal input unit  110 , and the other of the source terminal and the drain terminal of the transistor T 34  is electrically coupled to the default potential VSS. Both the gates of the transistors T 35 , T 36  are electrically coupled to an electric connection point P(n) between the one of the source terminal and the drain terminal of the transistor T 33  and the one of source terminal and the drain terminal of the transistor T 34  that are electrically coupled to each other. One of the source terminal and the drain terminal of the transistor T 35  is electrically coupled to the output terminal of the signal input unit  110 , and the other receives the first clock signal G(n) generated by the signal output unit  120 . One of the source terminal and the drain terminal of the transistor T 36  is electrically coupled to the output terminal of the signal output unit  120 , and the other is electrically coupled to the default potential VSS. 
     The second stable module  140  includes transistors T 41 , T 42 , T 43 , T 44 , T 45 , and T 46 . The gate of the transistor T 31  is electrically coupled to the second operation signal LC 2 , one of the source terminal and the drain terminal of the transistor T 41  is also electrically coupled to the second operation signal LC 2 , and the other is electrically coupled to one of the source terminal and the drain terminal of the transistor T 42 . The gate of the transistor T 42  receives the input signal Q(n) generated by the signal input unit  110 , and the other of the source terminal and the drain terminal of the transistor T 42  is electrically coupled to the default potential VSS. The gate of the transistor T 43  is electrically coupled to an electric connection point between the one of the source terminal and the drain terminal of the transistor T 41  and the one of source terminal and the drain terminal of the transistor T 42  that are electrically coupled to each other. One of the source terminal and the drain terminal of the transistor T 43  is electrically coupled to the second operation signal LC 2 , and the other is electrically coupled to one of the source terminal and the drain terminal of the transistor T 44 . The gate of the transistor T 44  also receives the input signal Q(n) generated by the signal input unit  110 , and the other of the source terminal and the drain terminal of the transistor T 44  is electrically coupled to the default potential VSS. Both the gates of the transistors T 45 , T 46  are electrically coupled to an electric connection point K(n) between the one of the source terminal and the drain terminal of the transistor T 43  and the one of source terminal and the drain terminal of the transistor T 44  that are electrically coupled to each other. One of the source terminal and the drain terminal of the transistor T 45  is electrically coupled to the output terminal of the signal input unit  110 , and the other receives the first clock signal G(n) generated by the signal output unit  120 . One of the source terminal and the drain terminal of the transistor T 46  is electrically coupled to the output terminal of the signal output unit  120 , and the other is electrically coupled to the default potential VSS. 
     The discharge unit  150  is electrically coupled to the output terminal of the signal input unit  110 , the output terminal of the signal output unit  120 , and the default potential VSS, and thus determines if it needs to discharge to the input signal Q(n) generated by the signal input unit  110  and the first clock signal G(n) generated by the signal output unit  120  according to control signals. Particularly, the discharge unit  150  includes two transistors T 51 , T 52 . Both the gates of the transistors T 51 , T 52  are electrically coupled to control signals, for example, a first clock signal G(n+2) generated by a signal input unit of a shift register (not shown) of a second following class. One of the source terminal and the drain terminal of the transistor T 51  is electrically coupled to the output terminal of the signal input unit  110 , and the other is electrically coupled to the default potential VSS. One of the source terminal and the drain terminal of the transistor T 52  is electrically coupled to the output terminal of the signal output unit  120 , and the other is electrically coupled to the default potential VSS. 
     Referring to  FIG. 3 , which is a timing diagram of the signals LC 1 , LC 2 , P(n), and K(n) used in the first and second stable modules  130 ,  140  of the shift register  100 . As shown in  FIGS. 1-3 , when the first operation signal LC 1  received by the first stable module  130  begins to change from the logic high level thereof to the logic low level thereof, the second operation signal LC 2  received by the second stable module  140  has already changed from the logic low level thereof to the logic high level thereof. That is, before the first stable module  130  is disabled, the second stable module  140  has already been enabled. Similarly, when the second operation signal LC 2  received by the second stable module  140  begins to change from the logic high level thereof to the logic low level thereof, the first operation signal LC 1  received by the first stable module  130  has already changed from the logic low level thereof to the logic high level thereof. That is, before the second stable module  140  is disabled, the first stable module  130  has already been enabled. 
     In this embodiment, duties of the first operation signal LC 1  received by the first stable module  130  and the second operation signal LC 2  received by the second stable module  140  are respectively larger than 50% of periods of the first operation signal LC 1  and the second operation signal LC 2 . Furthermore, the operation signal (e.g., LC 1 /LC 2 ) received by each stable module (e.g.,  130 / 140 ) can be a low-frequency pulse signal. Preferably, a period of the operation signal (e.g., LC 1 /LC 2 ) received by each stable module (e.g.,  130 / 140 ) is between time for displaying 0.1 frames of images and time for displaying 200 frames of images. Of course, it is understandable to ones of ordinary skill in the art, the operation signal (e.g., LC 1 /LC 2 ) received by each stable module (e.g.,  130 / 140 ) can also be a pulse signal with a higher frequency. 
     As shown in  FIG. 3 , when the first operation signal LC 1  received by the first stable module  130  begins to change from the logic high level thereof to the logic low level thereof (i.e., when the first stable module  130  needs to stop working under control of the first operation signal LC), because RC delay may be generated in the circuit of the first stable module  130  and the transistors (i.e., T 31 , T 32 , T 33 , T 34 , T 35 , T 36 ) need some time to discharge, potential on the electric connection point P(n) between the transistor T 33  and the transistor T 34  is still the logic high level thereof at this moment, and needs some time to entirely discharge and become the logic low level thereof. Therefore, due to effect of the logic high level on the electric connection point P(n), the transistor T 35  and the transistor T 36  keep being in on-states for a predetermined time, such that the first stable module  130  keeps working to stabilize the input signal Q(n) generated by the signal input unit  110  and the first clock signal G(n) generated by the signal output unit  120 . Until the potential on the electric connection point P(n) is pulled down to be not high enough to switch the transistor T 35  and the transistor T 36  on, the first stable module  130  stops working. 
     Furthermore, before the first operation signal LC 1  received by the first stable module  130  changes from the logic high level thereof to the logic low level thereof, the second operation signal LC 2  received by the second stable module  140  has already changed from the logic low level thereof to the logic high level thereof. Thus, potential on the electric connection point K(n) of the second stable module  140  has already pulled up by charging. In this way, it can be ensured that before the potential on the electric connection point P(n) is pulled down to be not high enough to switch the transistor T 35  and the transistor T 36  on by discharging (i.e., before the first stable module  130  stops working), the potential on the electric connection point K(n) of the second stable module  140  has already been pulled up to be high enough to switch the transistor T 45  and the transistor T 46  on by charging, and thus the second stable module  140  works. 
     In conclusion, the present invention (e.g., the shift register  100 ) corrects operation signals (e.g., LC 1 , LC 2 ) corresponding to the stable modules thereof (e.g.,  130 ,  140 ) to ensure that one stable module thereof has already been enabled before another stable module thereof is disabled. Thus, the present invention ensures at least one stable module thereof is working when the stable modules thereof are switched, such that stability of the shift register  100  is assured. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.