Abstract:
An interrupt controller circuit arrangement is used for encoding and storing &#34;interrupt&#34; signals indicating random (asynchronous) occurrence of corresponding events and for delivering corresponding &#34;interrupt&#34; (alarm command) signals to a (synchronous) microprocessor corresponding to the events as they occur. The events are divided into two (or more) sets in order to reduce the required number of latches and to increase the speed of operation. One (or more) of these sets consists of events which never can occur &#34;simultaneously&#34; (i.e., which are mutually exclusive in the sense that (within each of such sets) not more than a single one of the events can occur--and can occur only once--within a prescribed amount of time); the remaining set consists of the remaining events--i.e., those which can occur &#34;simultaneously&#34; or can occur simultaneously with one or more of those in the other set(s). In this way only the interrupt signals indicating the occurrence of events in the remaining set need be individually latched in separate latches each of which is devoted to a separate one of the events in that set.

Description:
FIELD OF THE INVENTION 
     This invention relates to an electronic data processing system and more particularly to a data processing system in which a multiplicity of different interrupt signals are generated asynchronously, each such interrupt signal being generated in response to an occurrence of an event corresponding to the interrupt signal. The purpose and function of each such interrupt signal is, for example, to cause a target synchronous data processing machine, such as a microprocessor, to execute a preselected computer-type instruction corresponding to the event--each such event occurring, typically at random, in parts of the system external to the target synchronous machine. 
     BACKGROUND OF THE INVENTION 
     In a variety of data processing contexts a number of different interrupt signals I 1 , I 2 , . . . are generated at various times during operation, the generation of each interrupt signal signifying an occurrence of the event corresponding to the interrupt signal. Thus, if and when, say, the i&#39;the event occurs, then the i&#39;th interrupt signal I i  is generated. Each event can in general occur at random (asynchronously), and when each such event occurs it signifies that certain computer-type action should be taken corresponding to the event, i.e., signifies that a corresponding computer-type instruction should be executed, as by a synchronous microprocessor. Typically, the microprocessor is integrated in a signle semiconductor circuit chip, and the interrupt signals are generated in other circuit chips. 
     In such data processing systems, more than a single event can occur essentially simultaneously, and hence more than a single interrupt signal can be generated at once. Moreover, on occasion the events occur so rapidly one after the other that the corresponding interrupt signals are generated so rapidly that, if the interrupt signals are delivered directly to the target machine, then the target synchronous machine cannot execute the corresponding instructions fast enough to keep up with the events. Therefore, it becomes necessary to have an interrupt controller arrangement, i.e, means for temporarily storing, as by queuing, the different incoming interrupt signals before delivering them to the target synchronous machine (typically a microprocessor). 
     In prior art, an interrupt controller arrangement, for thus temporarily storing the interrupt signals I 1 , I 2 , I 3 , . . . , typically involves the use of an array of latches L 1 , L 2 , L 3 , . . . . The arrival of interrupt signal I i  sets the corresponding latch L i  to logic &#34;high&#34;, i.e., to binary digital &#34;1&#34;, for recording and storing the information as to the arrival of the interrupt signal. Each such latch is reset to &#34;0&#34; immediately after readout of the latch. Each of the latches thus temporarily stores a single bit B 1 , B 2 , B 3 , . . . corresponding to whether or not the corresponding interrupt signal I 1 , I 2 , I 3 , . . . has been generated since the previous time the latch had been accessed for readout. Thus, for example, when the i&#39;th event occurs, the i&#39;th interrupt signal I i  is generated and arrives at the i&#39;th latch L i , whereby the i&#39; th latch is set--i.e., the state of the i&#39;th bit B i  becomes a binary digital &#34;1&#34;; and when the i&#39;th latch L i  is accessed for readout, it is reset to &#34;0&#34;--i.e., the i&#39;th bit B i  becomes &#34;0&#34;. The array of latches is scanned periodically, e.g., once during every time period T, so that each of the latches is accessed for readout, one after another in sequence, and is immediately thereafter reset to &#34;0&#34;, once and only once during every such period. This period T, the scanning period, typically is selected to be sufficiently short so that no event occurs twice during any period. Alternatively, the second occurrence of an event during a given period is not considered meaningful, because it is not effective in changing the state of the corresponding latch (and hence it ultimately is not effective in commanding the target synchronous machine to execute the corresponding instructions a corresponding second time). Accordingly, it will be assumed that the period T is selected to be short enough that no event occurs twice within any such period, or that the second occurrence of the event is considered as not meaningful. As a further alternative, a second latch can be supplied for an event that can occur twice within any period T. In any case, when a given latch L i  is accessed for readout, the latch L i  enables or does not enable--depending upon whether it is then set (to &#34;1&#34;) or reset (to &#34;0&#34;)--a memory stack to be written with an encoded interrupt word (string of bits) W i  corresponding to the latch L i  and hence corresponding to the i&#39;th event. Thus different encoded words W i  are written or not written in the memory stack depending upon whether the bit B i  is then a &#34;1&#34; or a &#34;0&#34;. Typically the memory stack is a FIFO (first in, first out) memory stack. In any case, after each latch is thus accessed for readout it is reset to &#34;0&#34;, the stored bit B i  therein is &#34;0&#34;, and the latch L.sub. i retains this &#34;0&#34; until the corresponding interrupt signal I i  once again is generated and arrives at this latch. Finally, the memory stack stores in a queue each of the encoded interrupt words W i  thus written into it and delivers each of these words W i  in sequence--typically first in, first out--to the target synchronous machine, one word for each synchronous timing cycle of the machine. Note that each machine cycle and each scanning period T in general are independent of each other, i.e., have no correlation. 
     A serious problem that arises in using such an interrupt controller arrangement is the requirement of a separate latch for each interrupt signal, i.e., a separate latch for recording and temporarily storing the occurrences of each event. Thus if there are n different events, typically as many as 50 or more, there are n different interrupt signals I i , and hence there must be n different latches L i  and n separate access time intervals constituting each scanning period T. Thus, for an access time t, the period T must be as long as at least nt in duration. It would therefore be desirable to have an arrangement in which the required number of latches are significantly reduced, whereby the scanning period T can be correspondingly reduced. 
     SUMMARY TO THE INVENTION 
     In order to reduce the number of latches in an electronic data processing system, as well as to increase the operating speed, in one embodiment of the invention an interrupt controller is designed to handle interrupt signals that are divided into two separate sets, one of the sets consisting of mutually exclusive interrupt signals generated by mutually exclusive events, M in number, and the other of the sets containing the remaining interrupt signals generated by the remaining events, N in number, for a total of n=(M+N) possible different events. By &#34;a set of mutually exclusive events&#34; it is meant that all the occurrences of all the events within this set are mutually separated in time by at least a prescribed minimum amount of time s. The set of &#34;remaining events&#34; thus in general include &#34;coincident&#34; events--i.e., events which may occur within the same time interval s as one or more of the events in the set of mutually exclusive events, or which are not guaranteed to be mutually spaced apart in time by the prescribed amount of time s, or both. For convenience, if any event in a set is thus coincident with any other, then all events in the set are considered to be &#34;coincident&#34;. Whenever any one of the mutually exclusive or any one of the remaining events occurs, a corresponding interrupt signal is generated, a different such interrupt for each different event. Thus the interrupt signals generated by the events are similarly divided into two sets: one set consisting of M mutually exclusive interrupt signals E 1 , E 2 , . . . E M  --i.e., interrupt signals characterized in that at most only one of them can be generated, and can be generated only once, within any time interval of a prescribed length s--the remaining set consisting of N non-mutually exclusive (&#34;co-incident&#34;) interrupt signals C 1 , C 2 , . . . C N  --i.e., interrupt signals characterized in that more than one of them may be generated within a time interval of the prescribed length s, or in that one or more of them may be generated within the same time interval s as one or more of them interrupt signals in the mutually exclusive set, although the same signal in this remaining set may not be generated more than once within any time interval equal to Ns or less. 
     The interrupt controller arrangement itself includes a first encoder, such as a ROM (read only memory) array or a PLA (programmed logic array), suitable for encoding each of the mutually exclusive interrupt signals E 1 , E 2 , . . . E M  into a separate corresponding encoded interrupt word W 1 , W 2 , . . . W M  --a different word for each of the mutually exclusive events. This first encoder is connected for receiving the mutually exclusive interrupt signals E 1 , E 2 , . . . E M  and thus encoding them into the interrupt words W 1 , W 2 , . . . W M . A multiplexer is connected for periodically receiving (&#34;sampling&#34;) from this first encoder whatever word is there encoded--one such word thereby being received during each period t, where t is selected to be less than or equal to s. 
     The interrupt controller arrangement further includes a second encoder for encoding the remaining set, of non-mutually exclusive interrupt signals, C 1 , C 2 , . . . C N , into encoded words w 1 , w 2 , . . . W N , and for delivering each of these words, one after the other in sequence, to the multiplexer, one such word per time period t, as determined by a ring counter. Thus it takes a time interval equal to Nt for all words in this remaining set to be delivered once to the multiplexer. 
     The multiplexer is arranged to receive (&#34;sample&#34;) and deliver per period t one word from the first encoder plus one word from the second encoder to a memory stack, such as a FIFO memory stack. However, not all words being received by the multiplexer are to be written into the memory stack, because some of these words may not have been received since the last time each of such words were written into the stack. For example, the mutually exclusive word W i  that is in the first encoder and is being delivered to the multiplexer during the present period t may have been retained by the encoder from a previous period t when the corresponding interrupt signal E i  was generated, but no new mutually exclusive interrupt signal has been generated since that time and hence the present word W i  is spurious. Moreover, the non-mutually exclusive words, in one embodiment, are delivered to the multiplexer in sequence regardless of whether or not the corresponding interrupt signals have been generated. Thus, a write logic unit--including an array of N latches L 1 , L 2 , . . . L N  for recording the occurrences of the non-mutually exclusive interrupt signals C 1 , C 2 , . . . C N  --is advantageously connected into the interrupt controller arrangement in order to enable the writing into the memory stack of each word as it is being received if and only if the corresponding interrupt signal has actually been generated since the last occasion on which the same interrupt signal (corresponding to that same word) was generated and hence when such word was written into the memory stack. This memory stack is arranged to deliver to a target synchronous machine, such as a synchronous microprocessor, just one word per synchronous machine cycle. 
     Notice that since there are only N latches that are required in the write logic unit, rather than N+M latches as in prior art, there is a saving of M latches in this embodiment. Moreover the scanning period T is thus equal to only Nt, instead of (N+M)t as in prior art. 
     In other embodiments of the invention, the events are further subdivided such that there is more than a single set of mutually exclusive events, now in the sense that not more than a single event within each set can occur (and then only once) per scanning period T, whereby the number of non-mutually exclusive (coincident) events, and hence the number of corresponding different coincident interrupt signals, can be reduced by transferring some of them out of the coincident set and placing each of them into one or another of the mutually exclusive sets where each of these interrupt signals is mutually exclusive with respect to the others in the set into which it is transferred. In such cases--i.e., of multiple sets of mutually exclusive events--the encoded words corresponding to the occurrences of the mutually exclusive events may not be valid long enough while waiting to be received by the multiplexer and therefore these words are advantageously temporarily stored in registers--only one such register being required per set of mutually exclusive events. In such an embodiment of multiple sets of mutually exclusive events, the multiplexer is arranged, for example, to receive (to &#34;sample&#34;) in succession all words in the coincident set, a single word from a first set of mutually exclusive interrupt signals, and a single word from a second set of mutually exclusive interrupt signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     This invention together with its features, advantages, and characteristics may be better understood from the following detailed description when read in conjunction with the drawing in which 
     FIG. 1 is a diagram of an interrupt controller arrangement in accordance with a specific embodiment of the invention; and 
     FIG. 2 is a diagram of an interrupt controller arrangement in accordance with another specific embodiment of the invention, with portions thereof that are similar to those depicted in FIG. 1 having been omitted as indicated by dotted line interconnections. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows an interrupt controller arrangement 1000 in a data processing system (not shown) for controlling delivery of mutually exclusive interrupt signals E 1 , E 2 , . . . E M  and of coincident interrupt signals C 1 , C 2 , . . . C N  to a microprocessor 100. The signals E 1 , E 2 , . . . E N  and C 1 , C 2 , . . . C N  are generated by other parts (not shown) of the data processing system. 
     The controller arrangement includes a modulo-N ring counter 20, a first encoder 60, a second encoder 11, an array 10 of R-S latches (L 1 , L 2 , . . . L N ), a multiplexer 70, a FIFO Control Unit 40, a FIFO Stack 80, a FIFO Write Logic Unit 200, and an interrupt register 90. The modulo-N ring counter 20 contains N stages labeled (1), (2), . . . (N) and is timed by master and slave clock pulse sequences φ MS  and φ SL , each having a periodicity equal to t. This counter 20 is connected for delivering its respective (sequential) outputs of stages (1), (2), . . . (N) to the encoder 11 as well as to the respective terminals R of the R-S latches L 1 , L 2 , . . . L N  via AND gates 121, 122, . . . respectively. Each of these AND gates 121, 122, . . . is also connected for receiving a master clock pulse sequence φ MS  in order to gate the counter with the master sequence. That is, if and only if the master clock is &#34;high&#34; (logic &#34;1&#34;) and at the same time the i&#39;th stage of the counter 20 is also &#34;high&#34;, then the i&#39;th latch L i  in the array 10 is reset (Q=0) by the ring counter via the corresponding one of these AND gates. As known in the art, one and only one stage of the ring counter 20 delivers a &#34;high&#34; logic level at a time, one stage after the other; hence the latches L 1 , L 2 , . . . L N  are successively reset, one after the other, during successive &#34;high&#34; phases of the master clock φ MS . 
     The FIFO Write Logic 200 is connected for delivering its output along a datum line 31 to the FIFO Control Unit 40. This Write Logic 200 comprises an array 10 of R-S latches L 1 , L 2 , . . . L N  connected for receiving, at their respective Set terminals S, the coincident interrupt signals C 1 , C 2 , . . . C N , respectively, via AND gates 111, 112, . . . respectively. Each of these AND gates 111, 112, . . . is also connected for receiving a slave clock pulse sequence φ SL . As known in the art, whenever the master clock goes &#34;high&#34; the slave is &#34;low&#34;, and whenever the slave goes &#34;high&#34; the master is &#34;low&#34;, so that only during a slave phase (when the slave clock is &#34;high&#34;) can the latches L 1 , L 2 , . . . L N  be set (Q=1) by a corresponding signal C 1 , C 2 , . . . C N  delivered through the corresponding AND gate 111, 112, . . . to the corresponding Set terminal S of L i . 
     The write logic 200 further comprises an M-input OR gate 140 connected for receiving the exclusive interrupt signals E 1 , E 2 , . . . E M  and for delivering its output to the OR gate 30 via an AND gate 141. It is important that each of these signals E 1 , E 2 , . . . E M  is valid during the master phase of the clock, i.e., when the master clock φ MS  is &#34;high&#34;, and more particularly at the corresponding moment during each such master phase when the multiplexer 70 samples the data arriving on data bus 63 from the first encoder 60, as described more fully below. This AND gate 141 is also connected for receiving the master clock pulse sequence φ MS , in order to ensure proper timing of the delivery of any of the exclusive interrupt signals (as output of the OR gate 140) to the OR gate 30 relative to the timing of the delivery of the corresponding encoded words from the encoder 60 to the FIFO Stack 80 via the multiplexer 70, as described more fully below. 
     The write logic 200 still further comprises an (N+1)-input OR gate 30 connected for receiving all the outputs Q of the R-S latches L 1 , L 2 , . . . L N  via AND gates 131, 132, 133, . . . , respectively. This OR gate 30 is further connected for delivering its output along an interconnecting line 31 to the FIFO Control Unit 40, in particular to a Write Control terminal W of the FIFO Control Unit 40. 
     The other encoder 60 is connected for receiving the mutually exclusive interrupt signals E 1 , E 2 , . . . E M . The encoders 11 and 60 are connected so as to deliver their respective output words along data buses 12 and 63, respectively, to the multiplexer 70. 
     The multiplexer 70 is connected so as to deliver its output along a data bus 71 to the FIFO Stack 80. The multiplexer 70 is controlled by the master and the slave clock sequences φ MS  and φ SL , and it alternately samples the data in the bus 12 and the data in the bus 63, whereby its output delivered to the data bus 71 is selected alternately to be the data in the data bus 12 during a pre-selected time slot or edge (as the case may be) within each &#34;high&#34; phase of the slave clock sequence φ SL  and the data in the data bus 63 during a pre-selected time slot or edge within each &#34;high&#34; phase of the master clock sequence φ MS . The data bus 71 is arranged to carry not only the data alternately from the buses 12 and 63 but also carries an added bit of data signifying whether the data in each word stem from data bus 12 or data bus 63. For example, the added bit can simply be a &#34;1&#34; if the master clock is high, and a &#34;0&#34; if the slave clock is high, whereby when the multiplexer 70 selects and delivers a word from the data bus 12 to the data bus 71 it also delivers an added &#34;1&#34; bit thereto and when the multiplexer selects and delivers a word from the data bus 63 to the data bus 71 it also delivers an added &#34;0&#34; bit thereto. Accordingly, upon delivery to the FIFO Stack 80, encoded words corresponding to coincident interrupts C 1 , C 2 , . . . C N  are tagged with an added &#34;1&#34; bit whereas encoded words corresponding to exclusive interrupts E 1 , E 2 , . . . E M  are tagged with an added &#34;0&#34; bit. 
     The writing vs. not writing into the FIFO Stack 80 of each word instantaneously present (one word at a time) in the data bus 71 must be controlled as to timing. Thus, for instance, if no new mutually exclusive interrupt signal has arrived since the last one, then the data in bus 71 will nevertheless repeatedly carry, during every &#34;high&#34; phase of the master-slave clock, the encoded word corresponding to the last mutually exclusive interrupt because of inherent memory of the encoder 60. (Similarly for the encoder 11.) Accordingly, to avoid spurious repeated writing of such words into the Stack, the Write Control terminal W of the FIFO Control Unit 40 is arranged to enable writing into the Stack 80 of the data instantaneously present in the bus 71 if but only if the output of the OR gate 30 is &#34;high&#34;, i.e., if and only if the OR gate 30 is then sending a &#34;1&#34; bit on its output line 31 to this control unit 40. Thus, for control over writing of words W 1 , W 2 , . . . W M  corresponding to the mutually exclusive interrupt signals E 1 , E 2 , . . . E M  into the FIFO Stack 80, the FIFO Control Unit 40 is arranged to send a separate write signal on FIFO Write line 41 to the FIFO Stack 80 once during each above-mentioned pre-selected time slot or edge within each &#34;high&#34; phase of the master clock sequence φ MS  provided that the signal bit on line 31 is then high (&#34;1&#34;), i.e., is then indicating the generation of a fresh mutually exclusive interrupt signal. Thus it is important that the mutually exclusive interrupt signals E 1 , E 2 , . . . E M  are valid during every such pre-selected time slot or edge (corrected for delays in propagation to the multiplexer 70 and to the FIFO Control Unit 40). Moreover, for control over writing of words w 1 , w 2 , . . . w N  corresponding to the non-mutually exclusive interrupt signals C 1 , C 2 , . . . C N , the FIFO Control Unit is arranged to send a separate write signal on FIFO Write line 41 to the FIFO Stack 80 once during each above-mentioned pre-selected time slot or edge within each &#34;high&#34; phase of the slave clock sequence φ SL  provided that the signal bit on line 31 is then high (&#34;1&#34;), i.e., is then indicating the presence of a fresh non-mutually exclusive interrupt signal, as described more fully below. 
     During operation, all cells (1), (2), . . . (N) in the ring counter 20 contain and deliver a &#34;0&#34; bit except for a single cell that momentarily contains a &#34;1&#34; bit, which is shifted by one cell at the beginning of each period t--e.g., is shifted from the (i-1)&#39;th to the i&#39;th cell--regardless of the set (Q=1) vs. reset (Q=0) conditions of the R-S latches L 1 , L 2 , . . . L N . That is, each shift from, say, cell (i-1) to cell (i) occurs regardless of the arrivals of the coincident interrupt signals C 1 , C 2 , . . . C N  during the immediately past period of time T=Nt prior to each such shift of the &#34;1&#34; bit in the ring counter, as is known in the ring counter art. Thus, the ring counter 20 enables the encoder 11 to deliver a new encoded word, say w i , to the data bus 12 and hence to the multiplexer 70 during each slave phase (φ.sub. SL =1) when the multiplexer samples the data bus 12. 
     Note that the &#34;1&#34; signal is delivered in sequence from successive ones of the cells (1), (2), . . . N of the ring counter 20 via AND gates 121, 122, . . . during successive master phases (φ MS  =1) to the Reset terminals of corresponding ones of the R-S latches L 1 , L 2 , . . . N. Therefore, in response to a &#34;1&#34; signal from the i&#39;th cell of the ring counter, during slave phases the Write Logic 200 enables writing into the FIFO Stack 80 of the corresponding word w i  by virtue of a &#34;1&#34; signal on the control line 31 only if the corresponding latch L i  is then in the set condition (Q=1) and hence delivers a &#34;1&#34; signal to the OR gate 30 through the i&#39;th one of the AND gates 131, 132, . . . , which is then being enabled by the &#34;1&#34; signal from the ring counter 20, and through the i&#39;th one of the AND gates 151, 152, . . . , which is then being enabled by a high signal from the slave clock sequence (φ SL  =1)--i.e., only if the corresponding one of the coincident interrupt signals C 1 , C 2 , . . . C N  has arrived via AND gates 111, 112, . . . and thereby has set (Q=1) the corresponding latch since the last occasion on which the latch was reset (Q=0) on a master phase (φ MS  =1) by the &#34;1&#34; signal from the ring counter 20. Otherwise, in the absence of such generation of the corresponding one of the coincident interrupt signals, the Write Logic Unit receives a &#34;0&#34; bit along line 31 and hence does not enable the writing of the corresponding word w i  into the FIFO Stack 80. Thus the word w i  is written into the Stack 80 if and only if the corresponding coincident interrupt signal C i  has arrived during the immediately preceding time interval T=Nt, as is desired for proper operation. 
     The Read control terminal R of FIFO Stack 80 is connected to cause the stack to deliver words thus stored in it to an interrupt register 90 via data bus 81, and the interrupt register is connected to deliver each of these words to a target synchronous microprocessor 100 via data bus 91, as more fully described below. To this end, the Read control terminal R of the FIFO Control Unit 40 is connected for delivering a read signal on FIFO read line 42 to the FIFO Stack 80. In addition, the FIFO Stack 80 is connected for delivering an overflow signal via datum line 82 to an added overflow latch OVF located in the interrupt register 90 in cases of overflow in the stack--i.e., in cases where so many words have been delivered into the Stack 80 in excess of words delivered by the Stack to the microprocessor that the storage capacity of the Stack is exceeded. If an overflow occurs, then on the very next machine interrupt &#34;read&#34; command signal, delivered on a control line 105 by microprocessor 100 to the FIFO Control Unit 40, the microprocessor 100 will thus be able to detect the occurrence of the overflow, as more fully described below. 
     The FIFO Stack 80 is connected so as to be able to deliver its contents, one word at a time, via a data bus 81 to an interrupt register 90, as well as to deliver the overflow signal via a datum line 82 to the added overflow latch OVF located in the register 90, as more fully described below. The interrupt register 90 is connected so as to be able to deliver its (one-word) contents via a data bus 91 to the target synchronous microprocessor 100, as well as to deliver the (one-bit) contents of the overflow latch OVF via a datum line 92 to the microprocessor 100, as more fully described below. The data bus 91 and the datum line 92 can, of course, be physically incorporated into a single bus, as known in the art. 
     The microprocessor 100 is operated synchronously in response to a machine clock pulse sequency ψ, as known in the art. If an overflow occurs in the Stack 80--i.e., if so many words have been delivered into the Stack in excess of the number of words delivered by the Stack to the interrupt register 90 that the storage capacity of the Stack is exceeded--then the overflow latch receives a one-bit signal on the line 82 from the Stack 80 (or alternatively from the Control Unit 40) indicating such overflow; hence the microprocessor 100 will thus be able to detect such an overflow by virtue of the overflow latch OVF, via datum lines 82 and 92, in response to the &#34;read&#34; command signal on line 105 from the microprocessor, as described more fully below. 
     The FIFO Control Unit 40 is connected to deliver &#34;read&#34; control signals to the FIFO Stack 80 and to the interrupt register 90, respectively, via control lines 42 and 44. The FIFO Control Unit 40 is also connected to deliver an interrupt signal INTR to the microprocessor 100 via line 43: when line 43 carries an INTR signal that is low (logic level &#34;0&#34;), it signifies an outstanding interrupt word in the FIFO Stack which has not yet been processed by the microprocessor. Moreover, the FIFO Control Unit 40 is further connected to receive a &#34;read&#34; command signal, via control line 105, from (and generated by) the microprocessor 100. More specifically, the microprocessor 100 is connected via the control line 105 to deliver the &#34;read&#34; command signal to the FIFO Control Unit 40 whenever the microprocessor is ready to receive a new interrupt word. In response thereto, if the Stack is not empty (as sensed by the FIFO Control Unit, as known in the art), then the FIFO Control Unit 40 generates and the Stack 80 receives a &#34;read&#34; signal on line 42, and the interrupt register 90 receives a first control signal on a control line 44 from the FIFO Control Unit 40, whereby the interrupt register is enabled to receive a fresh word from the Stack 80 via data bus 81 and to deliver this fresh word to the microprocessor 100 via data bus 91. At the same time, the overflow latch OVF delivers its own (one-bit) contents to microprocessor. On the other hand, the interrupt register 90 is designed so that, if the Stack 80 is empty, then the interrupt register receives a second control signal (different from the first control signal) on the control line 44 from the FIFO Control Unit 40, which causes the interrupt register 90 to generate and to deliver to the microprocessor 100 a unique code word w 0 , pre-selected so as to be different from all the other interrupt words, via the data bus 91; and further, if the Stack is empty, the FIFO Control Unit 40 sets the INTR signal (interrupt signal absent) on the control line 43 to a high logic level (INTR=1). Accordingly, if the microprocessor attempts to read the interrupt register in the presence of the INTR signal on the control line 43, the unique word w 0  will be delivered via the bus 91 from the interrupt register to the microprocessor indicating that the Stack is empty. Thus the word w 0  indicates to the microprocessor that all outstanding interrupt words have been processed by the microprocessor and thus can supply a &#34;sanity&#34; check on the validity of the INTR signal on the control line 93, as more fully described below. 
     At least two different modes of operation of the microprocessor are thus enabled by the use of the unique word w 0  signifying an empty Stack. In a first mode of operation, the microprocessor periodically reads the interrupt register by periodically sending a command signal via line 105 to the FIFO Control Unit, the INTR signal on the line 43 being disregarded by the microprocessor, or alternatively the line 43 itself being removed or discarded from the arrangement entirely. In a second mode of operation, the microprocessor sends a command signal on line 105 to the FIFO Control Unit if and only if the microprocessor is ready to receive a fresh interrupt word for processing and at the same time the INTR signal on the control line 43 is absent (i.e., Stack is not empty), whereby the delivery of the unique word w 0  thus serves as a &#34;sanity&#34; check on the correctness of the INTR signal on the line 43--i.e., serves as a check in case the signal on the line 43 is spuriously absent (low), spuriously indicating a non-empty Stack, or in case the microprocessor incorrectly interpreted (decoded) the INTR  signal on the line 43 as being absent (low) and hence spuriously attempted to read the Stack. 
     Although the invention has been discussed in detail in terms of a specific embodiment, various modifications are possible without departing from the scope of the invention. For example, as indicated in FIG. 2, some of the incoming coincident interrupt signals may be taken out of the coincident set and placed into an added, third set whereby this third set contains mutually exclusive interrupt signal within itself (although not necessarily mutually exclusive when considered together with the signals of the original set of mutually exclusive signals), whereby in general there are two sets of mutually exclusive interrupt signals, one consisting of J interrupt signals E 1 , E 2 , . . . E J , and the other consisting of K interrupt signals E J+1 , E J+2 , . . . E J+K  ; and thus the number of coincident signals is correspondingly reduced. It should be noted that in FIG. 2 the dotted interconnection lines indicate connections to portions (not shown) of the arrangement that are similar to those depicted in FIG. 1. In such a case, furthermore, the ring counter 120 is arranged to count modulo P+2, where P (with P&lt;N) is the number of remaining coincident signals, and the number of latches array of R-S latches for these coincident signals is reduced from N to P. In such a case, moreover, an extra encoder 160, together with its data bus 163, is added for encoding the interrupt signals of the added set and for delivering the resulting encoded words to a multiplexer 170 (FIG. 2) which is a modified form of the multiplexer 70 (FIG. 1), in order to multiplex incoming data from the three data buses 12, 63 and 163 onto data bus 171 for delivery to the FIFO Stack 80. For this purpose this multiplexer 170 is connected (not shown) to the ring counter 120 so that, for example, for each P+2 successive periods each of duration equal to t, the following happens: during the first P periods t the data bus 12 is sampled by the multiplexer 170 once during each of the corresponding P slave phases, during the (P+1)st period t the data bus 63 is sampled by the multiplexer 170 once during the slave phase, and during the (P+2)nd period the data bus 163 is sampled by the multiplexer 170 during the slave phase. Also, the Write Logic Unit 200 (FIG. 1) is modified as indicated in FIG. 2, essentially by adding latches L P+1  and L P+2  for recording the occurrences of interrupt signals E 1 , E 2 , . . . E J  and E J+1 , E J+2 , . . . E J+K  respectively, in the two sets of mutually exclusive signals, and by adding AND gate 241. Thus the multiplexer 170 cooperates with the Write Logic Unit, to deliver the interrupt words via the data bus 171 to the FIFO Stack 80 and to deliver a control signal through line 31 to the FIFO Control Unit 40 corresponding to the generation vs. no generation of the corresponding interrupt signal. Note that in this way the interrupt signals E 1 , E 2 , . . . E J , E J+1 , E J+2  . . . E J+K  in the mutually exclusive sets are advantageously valid during the slave phases in order to set the corresponding latch L P+1  or L P+2  whenever such signals are generated (i.e., go high), and each such interrupt signal should be mutually exclusive with respect to itself and all the others in its own set over every time interval of duration equal to the scanning period T=(P+2)t. 
     Alternatively, the ring counter can be designed so as to send its high signal to the latches in the following order of sequence: L 1 , L P+1 , L P+2 , L 2 , L P+1 , L P+2 , etc., and correspondingly the multiplexer 170 is designed to sample in succession: one word from the data bus 12, one word from the data bus 63, one word from the data bus 163, another word from the data bus 12, one word from the data bus 63, one word from the data bus 163, etc. In this way, the minimum allowed time between generations of successive interrupt signals in a given mutually exclusive set is reduced to 3t at the expense of a somewhat longer minimum time between allowed successive generations of a given interrupt signal in the coincident set. Such an arrangement thus assigns equal priority to all the interrupt signals of the mutually exclusive sets. Other priority arrangements can be implemented for the mutually exclusive sets whereby certain sets are thus accessed more often by the ring counter than others. 
     Further subdivision of the interrupt signals into still more sets, by taking still more of the signals from the coincident set and placing them into still more mutually exclusive sets may also be feasible for some interrupt signals depending upon their mutual exclusivity relationships. In this way, the scanning period T can be still further reduced. Finally, each of the encoders is typically a read only memory (ROM), but instead of ROM a PLA can be used especially in case the incoming signals already have been encoded (though not encoded in the way that is ultimately desired for delivery to the microprocessor). Here PLA means a programmed logic array containing an AND plane (Decoder) and an OR plane (ROM). Such a ROM or PLA may well have an output register (array of latches) for temporarily storing its encoded output words, but the number of latches that such a register requires is equal to only about log 2  M where M now denotes the number of independent (perhaps already encoded) incoming interrupt signals to the ROM or PLA, as known in the binary encoding art.