Abstract:
A current-mode controlled switching regulator and control method therefor. The switching regulator includes input and output terminals, a switching device to switch in accordance with a control signal, an inductor to store charge from an input voltage at the input terminal based on the switching device, a rectifying device to discharge the charge stored in the inductor, an error amplifier to amplify a voltage difference between a divided voltage generated by dividing an output voltage at the output terminal and a predetermined reference voltage, a slope voltage generator to generate and output a slope voltage having a slope angle corresponding to the input voltage, and a switching controller to compare a voltage output from the error amplifier with the slope voltage, generate a pulse signal with a duty cycle corresponding to a comparison result, and control the switching of the switching device according to the pulse signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This patent specification is based on and claims priority from Japanese Patent Application No. 2006-349020 filed on Dec. 26, 2006 in the Japan Patent Office, the entire contents of which are hereby incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a current-mode controlled switching regulator and a control method therefor. 
         [0004]    2. Description of the Related Art 
         [0005]    Until recently, a switching regulator has generally employed a voltage-mode control system, in which a switching device is controlled by PWM (pulse width modulation) control based on the voltage difference between an output voltage and a reference voltage to stabilize the output voltage. However, since such a voltage-mode controlled switching regulator detects a feedback signal from the output voltage, response to fluctuation in the output voltage is slow. Further, phase compensation for an error amplifier that amplifies the voltage difference between the output voltage and the reference voltage becomes complicated. 
         [0006]    To overcome these drawbacks, a current-mode controlled switching regulator is increasingly used. However, it is known that subharmonic oscillation may occur using the current-mode controlled switching regulator and the current-mode controlled switching regulator may become uncontrollable when a pulse width modulated signal has a duty cycle of more than 50%. The subharmonic oscillation is generally avoided by adding slope compensation to the PWM control. 
         [0007]      FIG. 1  is a diagram illustrating example circuitry of a current-mode controlled switching regulator with a slope compensation circuit, which is a step-down switching regulator having an input terminal IN to which an input voltage V in  is applied and an output terminal OUT from which an output voltage V out  is output. 
         [0008]    In  FIG. 1 , when a switching transistor  105  is turned on, power is supplied to an inductor  104 , a smoothing capacitor  102 , and a load  101 . When the switching transistor  105  is turned off, the energy stored in the inductor  104  and the smoothing capacitor  102  is supplied to the load  101 . A current-to-voltage converter  106  has an impedance R sense  for converting a current iL flowing through the inductor  104  into a converted voltage V sense , or R sense ×iL. 
         [0009]    An oscillator  110  generates and outputs a reference clock signal CLK and a sawtooth voltage signal V ramp . An adder  108  adds the sawtooth voltage signal V ramp  to the converted voltage V sense  for slope compensation and outputs a slope voltage V s  to a non-inverted input terminal of a PWM comparator  107 . An error amplifier  115  amplifies the voltage difference between a divided voltage V fb  generated by dividing the output voltage V out  and a reference voltage V ref  and generates and outputs an error voltage V e  to an inverted input terminal of the PWM comparator  107 . The PWM comparator  107  compares the error voltage V e  with the slope voltage V s . When the error voltage V e  exceeds the slope voltage V s , the PWM comparator  107  resets an RS latch circuit  112  and turns off the switching transistor  105 . Accordingly, the peak current value of the inductor current iL depends on the error voltage V e . 
         [0010]    The output voltage V out  is controlled as follows. When the divided voltage V fb  is higher than the reference voltage V ref , the error voltage V e  is lowered to lower the output voltage V out . When the divided voltage V fb  is lower than the reference voltage V ref , the error voltage V e  is increased to increase the output voltage V out . 
         [0011]    To avoid subharmonic oscillation by slope compensation, it is desirable that the slope angle of the slope voltage V s  be not less than half the slope angle of the inductor current iL flowing when the switching transistor  105  is off. 
         [0012]    Specifically, the slope diL/dt of the inductor current iL flowing in the current-mode controlled switching regulator of  FIG. 1  is expressed by the following formula (a) when the switching transistor  105  is on, and expressed by the following formula (b) when the switching transistor  105  is off: 
         [0000]        diL/dt =( V   in   −V   out )/ L   (a) 
         [0000]        diL/dt=−V   out   /L   (b), 
         [0013]    where L is the inductance of the inductor  104 . 
         [0014]    The slope angle of the sawtooth voltage signal V ramp , which is referred to as a slope compensation value I ramp , is expressed by the following formula (c): 
         [0000]        I   ramp   &gt;V   out /2 /L×R   sense   (c) 
         [0015]    The following formulas (d), (e), and (f) can be provided for a step-up switching regulator, corresponding to the formulas (a), (b), and (c), respectively. 
         [0000]        diL/dt=V   in   /L   (d) 
         [0000]        diL/dt =−( V   out   −V   in )/ L   (e) 
         [0000]        I   ramp &gt;( V   out   −V   in )/ L/ 2 ×R   sense   (f) 
         [0016]    The slope compensation value I ramp  is expressed by using the input voltage V in  and the output voltage V out  without problem when the input voltage V in  and the output voltage V out  are fixed. However, the input voltage V in  and the output voltage V out  generally fluctuate in a wide range. When the slope compensation value I ramp  is fixed, it is necessary that the slope compensation value I ramp  is set to be a value that is a maximum value in the estimated fluctuation range of the input voltage V in  and the output voltage V out . By performing excessive slope compensation like this case, subharmonic oscillation can be avoided. However, the effect of current feedback decreases and the operation becomes similar to the operation of the voltage-mode control system. Consequently, controllability decreases. Therefore, to perform adequate slope compensation in a wide input/output voltage range, the amount of slope compensation is determined based on input and output voltage levels. 
         [0017]    However, in this case, since the amount of slope compensation is changed according to the input and output voltages, the circuitry is complicated. In addition, a general-purpose IC for a switching regulator generally uses an external resistor to generate a divided voltage by dividing the output voltage, which may prevent monitoring of the output voltage and thereby prevent slope compensation in accordance with the output voltage. 
       SUMMARY 
       [0018]    This patent specification describes a novel current-mode controlled step-down switching regulator that includes an input terminal, an output terminal, a switching device to switch in accordance with a control signal, an inductor to store charge from an input voltage at the input terminal based on the switching device, a rectifying device to discharge the charge stored in the inductor, an error amplifier to amplify a voltage difference between a divided voltage generated by dividing an output voltage at the output terminal and a predetermined reference voltage, a slope voltage generator to generate and output a slope voltage having a slope angle corresponding to the input voltage, and a switching controller to compare a voltage output from the error amplifier with the slope voltage, generate a pulse signal with a duty cycle corresponding to a comparison result, and control the switching of the switching device according to the pulse signal. 
         [0019]    This patent specification further describes a novel current-mode controlled step-up switching regulator that includes an input terminal, an output terminal, a switching device to switch in accordance with a control signal, an inductor to store charge from an input voltage at the input terminal based on the switching device, a rectifying device to discharge the charge stored in the inductor, an error amplifier to amplify a voltage difference between a divided voltage generated by dividing an output voltage at the output terminal and a predetermined reference voltage, a slope voltage generator to generate and output a slope voltage having a slope angle corresponding to the output voltage, and a switching controller to compare a voltage output from the error amplifier with the slope voltage, generate a pulse signal with a duty cycle corresponding to a comparison result, and control the switching of the switching device according to the pulse signal. 
         [0020]    In addition, this patent specification describes a novel control method for controlling the current-mode controlled step-down switching regulator including generating a slope voltage and changing a slope angle of the slope voltage according to the input voltage to generate a pulse signal for controlling the switching of the switching device. 
         [0021]    This patent specification further describes a novel control method for controlling the current-mode controlled step-up switching regulator including generating a slope voltage and changing a slope angle of the slope voltage according to the output voltage to generate a pulse signal for controlling the switching of the switching device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0022]    A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
           [0023]      FIG. 1  is a diagram illustrating example circuitry of a background current-mode controlled switching regulator; 
           [0024]      FIG. 2  is a diagram illustrating example circuitry of a current-mode controlled switching regulator according to a first embodiment of the present invention; 
           [0025]      FIG. 3  is a timing chart illustrating example waveforms in the current-mode controlled switching regulator of  FIG. 2 ; 
           [0026]      FIG. 4  is a diagram illustrating example circuitry of a voltage-to-current converter of  FIG. 2 ; 
           [0027]      FIG. 5  is a diagram illustrating example circuitry of a current-mode controlled switching regulator according to a second embodiment of the present invention; 
           [0028]      FIG. 6  is a timing chart illustrating example waveforms in the current-mode controlled switching regulator of  FIG. 5 ; and 
           [0029]      FIG. 7  is a diagram illustrating example circuitry of a voltage-to-current converter of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0030]    In describing exemplary embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected, and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner and achieve a similar result. 
         [0031]    Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views thereof, and in the first instance to  FIG. 2 , current-mode controlled switching regulators according to exemplary embodiments of the present invention are described. 
         [0032]      FIG. 2  is a diagram illustrating example circuitry of a current-mode controlled switching regulator according to a first embodiment. 
         [0033]    A current-mode controlled switching regulator (hereinafter referred to as a switching regulator)  1  of  FIG. 2  forms a step-down switching regulator that converts an input voltage V in  applied from a DC (direct current) power supply  20  to an input terminal IN into a lower voltage than the input voltage V in  and outputs an output voltage V out  from an output terminal OUT to a load  21 . 
         [0034]    The switching regulator  1  includes a PMOS switching transistor M 1  that controls output of a current flowing from the input terminal IN, a rectifying diode D 1 , an inductor L 1 , a smoothing capacitor C 1 , and output voltage detecting resistors  2  and  3  that divide the output voltage V out  output from the output terminal OUT, and generate and output a divided voltage V fb . 
         [0035]    The switching regulator  1  also includes a reference voltage generator  4  that generates and outputs a reference voltage V ref , an error amplifier  5  that compares the divided voltage V fb  with the reference voltage V ref , amplifies the resulting voltage difference therebetween, and generates and outputs an error voltage V e , and a slope voltage generator  6  that generates and outputs a slope voltage V s . 
         [0036]    The switching regulator  1  further includes a PWM comparator  7  that compares the error voltage V e  from the error amplifier  5  with the slope voltage V s  and generates and outputs a pulse signal Spw having a pulse width corresponding to the error voltage V e  to perform PWM control, an oscillator  8  that generates and outputs a clock signal CLK, a Reset-Set (RS) flip-flop circuit  9  having a set input terminal S that receives the clock signal CLK from the oscillator  8 , a reset input terminal R that receives the pulse signal Spw from the PWM comparator  7 , and an output terminal Q that outputs an output signal Sq, and an inverter  10  that generates a control signal to control switching of the switching transistor M 1  by driving the switching transistor M 1  according to the output signal Sq from the RS flip-flop circuit  9 . 
         [0037]    The slope voltage generator  6  includes an inverter  11 , a voltage-to-current converter  12 , a resistor  13 , PMOS transistors  14  and  15 , and a capacitor  16 . The switching transistor M 1  forms a switching device. The diode D 1  forms a rectifying device. The resistors  2  and  3 , the reference voltage generator  4 , and the error amplifier  5  form an error amplifier. The slope voltage generator  6  forms a slope voltage generator. The PWM comparator  7 , the oscillator  8 , the RS flip-flop circuit  9 , and the inverter  10  form a switching controller. The PWM comparator  7  forms a voltage comparator. The RS flip-flop circuit  9  forms a control circuit. The voltage-to-current converter  12  forms a current source. The PMOS transistor  14  forms a voltage supplier. The PMOS transistor  15  forms a discharge circuit. Each circuit included in the switching regulator  1  of  FIG. 2 , excluding the inductor L 1 , the diode D 1 , the capacitor C 1 , and the resistors  2  and  3 , is integrated on an integrated circuit (IC). 
         [0038]    The switching transistor M 1  is connected between the input voltage V in  and the cathode of the diode D 1 . The anode of the diode D 1  is connected to ground. The inductor L 1  is connected between the drain of the switching transistor M 1  and the output terminal OUT. The resistors  2  and  3 , which are connected in series, and the capacitor C 1  are connected in parallel between the output terminal OUT and ground. In the error amplifier  5 , the divided voltage V fb , which is the voltage at the connection node of the resistors  2  and  3 , is applied to the non-inverted input terminal and the reference voltage V ref  is applied to the inverted input terminal. In the PWM comparator  7 , the error voltage V e  from the error amplifier  5  is applied to the non-inverted input terminal and the slope voltage V s  is applied to the inverted input terminal. The output signal Sq from the RS flip-flop circuit  9  is inverted by the inverter  10  and the inverted signal is input to the gate of the switching transistor M 1 . 
         [0039]    In the slope voltage generator  6 , the PMOS transistor  14  and the resistor  13  are connected in series between the drain of the switching transistor M 1  and the inverted input terminal of the PWM comparator  7 . The voltage-to-current converter  12  is connected between the inverted input terminal of the PWM comparator  7  and ground. In the voltage-to-current converter  12 , the input voltage V in  is applied to an input terminal that receives a control signal. The voltage-to-current converter  12  allows a current i slope  corresponding to the input voltage V in  to flow from the resistor  13  to ground. The connection node of the resistor  13  and the voltage-to-current converter  12  forms the output terminal of the slope voltage generator  6  and the slope voltage V s  is output therefrom. The inverter  11  inverts the clock signal CLK and outputs the inverted clock signal to the gate of the PMOS transistor  14 . The PMOS transistor  15  and the capacitor  16  are connected in parallel between the input terminal IN and the drain of the PMOS transistor  14 . The output signal Sq from the RS flip-flop circuit  9  is input to the gate of the PMOS transistor  15 . 
         [0040]    In the above-described configuration, when the error voltage V e  is lower than the slope voltage V s , the PWM comparator  7  outputs a low level signal, the RS flip-flop circuit  9  outputs a high level signal while the clock signal CLK is high, and the inverter  10  turns the switching transistor M 1  on for conduction. When the switching transistor M 1  is on, power is supplied to the inductor L 1 , the smoothing capacitor C 1 , and the load  21 . When the switching transistor M 1  is off, the energy stored in the inductor L 1  and the smoothing capacitor C 1  is supplied to the load  21 . 
         [0041]    The error amplifier  5  amplifies the voltage difference between the divided voltage V fb  generated by dividing the output voltage V out  and the reference voltage V ref  to generate and output the error voltage V e  to the non-inverted input terminal of the PWM comparator  7 . The PWM comparator  7  compares the error voltage V e  with the slope voltage V s  from the slope voltage generator  6 . When the error voltage V e  is higher than the slope voltage V s , the PWM comparator  7  resets the RS flip-flop circuit  9  to turn off the switching transistor M 1 . Accordingly, the peak current value of an inductor current iL flowing through the inductor L 1  depends on the error voltage V e . 
         [0042]    The output voltage V out  is controlled as follows. When the divided voltage V fb  is higher than the reference voltage V ref , the output voltage V out  is lowered by increasing the error voltage V e . When the divided voltage V fb  is lower than the reference voltage V ref , the output voltage V out  is increased by lowering the error voltage V e . 
         [0043]      FIG. 3  is a timing chart illustrating example waveforms in the switching regulator  1  of  FIG. 2 . Operation of the slope voltage generator  6  of  FIG. 2  is described referring to  FIG. 3 . 
         [0044]    The voltage-to-current converter  12  generates and outputs the current i slope  corresponding to the input voltage V in . The current i slope  is expressed by A×V in , where A is a given value. An offset voltage V offset  added to the input voltage V in  by the resistor  13  is expressed by the following formula (1): 
         [0000]        V   offset   =V   in   −i   slope   ×R   offset   (1), 
         [0045]    where R offset  is the resistance value of the resistor  13 . 
         [0046]    The input voltage V in  is applied to one end of the capacitor  16 . When the clock signal CLK is high and the PMOS transistor  14  is on, a drain voltage VA of the switching transistor M 1  is applied to the other end of the capacitor  16  through the PMOS transistor  14 . As a result, a voltage difference is generated across the capacitor  16 , thereby charging the capacitor  16 . When the switching transistor M 1  is on, the drain voltage VA of the switching transistor M 1  is equal to V in −R on ×iL valley , where R on  is the on-resistance of the switching transistor M 1 , and iL valley  is the current value of the inductor current iL while the switching transistor M 1  is on. 
         [0047]    When the PMOS transistor  14  is off, the charge stored in the capacitor  16  is discharged by the voltage-to-current converter  12 . The slope angle of the voltage of the capacitor  16  becomes −A×V in /Cvs, where Cvs is the capacitance of the capacitor  16 . 
         [0048]    Therefore, when the switching transistor M 1  is on, the slope voltage V s  is expressed by the following formula (2): 
         [0000]        V   s   =V   in   −A×V   in   ×R   offset   −R   on   ×iL   valley   −A×V   in   /Cvs×t   (2), 
         [0049]    where t is the time elapsed since the switching transistor M 1  is turned on. 
         [0000]      When  A/Cvs=R   on   /L   (3), 
         [0050]    where L is the inductance of the inductor L 1 , the following formula (4) is obtained from the formula (2): 
         [0000]        dV   s   /dt=−R   on   ×V   in   /L   (4) 
         [0051]    When the output signal Sq from the RS flip-flop circuit  9  is low, the switching transistor M 1  is off and the PMOS transistor  15  is on, thereby discharging the charge stored in the capacitor  16 , and the capacitor  16  is reset. 
         [0052]    While the formula (3) is obtained by assuming that the on-resistance R on  is a constant value, and the current i slope  generated by the voltage-to-current converter  12  that forms a current source is expressed by A×V in , the on-resistance R on  generally fluctuates with respect to the temperature of the switching transistor M 1  and the gate voltage thereof during the on state. 
         [0053]    Considering the fluctuation in the on-resistance R on , the following formula (5) is obtained from the formula (2) by expressing the current i slope  by B×R on ×V in , where B is a given value: 
         [0000]        V   s   =V   in   −B×R   on   ×V   in   ×R   offset   −R   on   ×iL   valley   −B×R   on   ×V   in   /Cvs×t   (5) 
         [0000]      When  B/Cvs= 1 /L   (6), 
         [0054]    the following formula (7) is obtained from the formula (5): 
         [0000]        dV   s   /dt=−R   on   ×V   in   /L   (7) 
         [0055]    As can be seen from the formula (7), the slope angle dV s /dt of the slope voltage V s  fluctuates in accordance with fluctuation of the input voltage V in . Therefore, the slope voltage generator  6  increases the slope angle of the slope voltage V s  to have a larger slope angle than a slope angle of half the inductor current iL in a shut-down state in which the switching transistor M 1  is turned off. 
         [0056]      FIG. 4  is a diagram illustrating example circuitry of the voltage-to-current converter  12 . 
         [0057]    In  FIG. 4 , the voltage-to-current converter  12  forms a current source that generates the current i slope  corresponding to the input voltage V in  and includes error amplifiers  31  and  32 , PMOS transistors  33  and  34 , NMOS transistors  35 ,  36 , and  37 , and resistors  38  and  39 . 
         [0058]    The PMOS transistor  33 , the NMOS transistor  35 , and the resistor  38  are connected in series between the input voltage V in  and ground. The gate of the PMOS transistor  33  is connected to ground and the gate of the NMOS transistor  35  is connected to the output terminal of the error amplifier  31 . In the error amplifier  31 , the input voltage V in  is applied to the non-inverted input terminal and the inverted input terminal is connected to the connection node of the NMOS transistor  35  and the resistor  38 . 
         [0059]    The resistor  39 , the PMOS transistor  34 , and the NMOS transistor  36  are connected in series between the input voltage V in  and ground. The gate of the PMOS transistor  34  is connected to the output terminal of the error amplifier  32 . In the error amplifier  32 , the non-inverted input terminal is connected to the connection node of the PMOS transistor  33  and the NMOS transistor  35  and the inverted input terminal is connected to the connection node of the resistor  39  and the PMOS transistor  34 . The NMOS transistors  36  and  37  form a current mirror circuit. The gates of the NMOS transistors  36  and  37  are connected to each other and the connection node thereof is connected to the drain of the NMOS transistor  36 . The sources of the NMOS transistors  36  and  37  are connected to ground and the current i slope  flows from the drain of the NMOS transistor  37  to ground. 
         [0060]    The error amplifier  31  controls the current flowing through the NMOS transistor  35  by controlling the NMOS transistor  35  so that the voltage applied to its inverted input terminal becomes equal to the input voltage V in , which is applied to its non-inverted input terminal. The resistors  38  and  39  have resistance values R 38  and R 39 , respectively, neither of which fluctuates. In this example embodiment, the PMOS transistor  33  is formed by the same process as the switching transistor M 1 . A voltage that turns the switching transistor M 1  on is applied to the gate of the PMOS transistor  33 . The PMOS transistor  33  has the size of 1/n of the switching transistor M 1  and the on-resistance of n×R on . 
         [0061]    The current of V in /R 38  flows through the resistor  38  and the PMOS transistor  33 . Therefore, the voltage difference across the PMOS transistor  33  is equal to n×R on ×(V in /R 38 ). The error amplifier  32  controls the PMOS transistor  34  so that the voltage difference across the resistor  39  becomes equal to n×R on ×(V in /R 38 ). Therefore, the current of R on ×n×V in /R 38 /R 39  flows through the resistor  39 . The drain current of the NMOS transistor  37  that forms the current mirror circuit is equal to R on ×n×V in /R 38 /R 39 . The current i slope  is expressed by the following formula (8): 
         [0000]        i   slope   =B×R   on   ×V   in   (8), 
         [0062]    where B=n/R 38 /R 39 . 
         [0063]    It should be noted that although the on-resistance of the switching transistor M 1  is used to convert a current into a voltage when the switching transistor M 1  is on in the above-described example circuit, alternatively, a sense resistor that detects the output current of the switching transistor M 1  may be connected in series to the inductor L 1  to convert a current into a voltage when the switching transistor M 1  is on. In this case, the PMOS transistor  33  in the voltage-to-current converter  12  of  FIG. 4  may be replaced by a resistor having the same temperature characteristics as the sense resistor. 
         [0064]    The current-mode controlled switching regulator according to the first embodiment provides an appropriate slope compensation in a wide input/output voltage range with simple circuitry by changing the slope angle of the slope voltage V s  according to fluctuation in the input voltage V in . As a result, subharmonic oscillation can be avoided. 
         [0065]    It should be noted that although a step-down switching regulator is described as an example of the first embodiment, the present invention is not limited thereto but is also applicable to a step-up switching regulator, which is now described as a second embodiment. 
         [0066]      FIG. 5  is a diagram illustrating example circuitry of a current-mode controlled switching regulator according to the second embodiment. In  FIG. 5 , the same or similar components to those illustrated in  FIG. 2  are referred to by the same reference numerals. 
         [0067]    A switching regulator  1   a  of  FIG. 5  forms a step-up switching regulator that converts an input voltage V in  applied from a DC power supply  20  to an input terminal IN into a higher voltage than the input voltage V in  and outputs an output voltage V out  from an output terminal OUT to a load  21 . 
         [0068]    The switching regulator  1   a  includes a NMOS switching transistor M 11 , a rectifying diode D 11 , an inductor L 1 , a smoothing capacitor C 1 , and output voltage detecting resistors  2  and  3  that divide the output voltage V out  output from the output terminal OUT and generate and output a divided voltage V fb . 
         [0069]    The switching regulator  1   a  also includes a reference voltage generator  4  that generates and outputs a reference voltage V ref , an error amplifier  5  that compares the divided voltage V fb  with the reference voltage V ref , amplifies the resulting voltage difference therebetween, and generates and outputs an error voltage V e , and a slope voltage generator  6   a  that generates and outputs a slope voltage V s . 
         [0070]    The switching regulator  1   a  further includes a PWM comparator  7  that compares the error voltage V e  from the error amplifier  5  with the slope voltage V s  and generates and outputs a pulse signal Spw having a pulse width corresponding to the error voltage V e  to perform PWM control, an oscillator  8  that generates and outputs a clock signal CLK, an RS flip-flop circuit  9  having a set input terminal S that receives the clock signal CLK from the oscillator  8 , a reset input terminal R that receives the pulse signal Spw from the PWM comparator  7 , and an output terminal Q that outputs an output signal Sq. 
         [0071]    The slope voltage generator  6   a  includes an inverter  51 , a voltage-to-current converter  52 , a resistor  53 , NMOS transistors  54 ,  55  and  57 , and capacitors  56  and  58 . The switching transistor M 11  forms a switching device. The diode D 11  forms a rectifying device. The slope voltage generator  6   a  forms a slope voltage generator. The PWM comparator  7 , the oscillator  8 , and the RS flip-flop circuit  9  form a switching controller. The voltage-to-current converter  52  forms a current source. The NMOS transistor  54  forms a voltage supplier. The NMOS transistor  55  forms a discharge circuit. Each circuit included in the switching regulator  1   a  of  FIG. 5 , excluding the inductor L 1 , the diode D 11 , the capacitor C 1 , and the resistors  2  and  3 , is integrated on an IC. 
         [0072]    The inductor L 1  is connected between the input voltage V in  and the drain of the switching transistor M 11 . As for the diode D 11 , the anode is connected to the drain of the switching transistor M 11  and the cathode is connected to the output terminal OUT. The resistors  2  and  3 , which are connected in series, and the capacitor C 1  are connected in parallel between the output terminal OUT and ground. In the error amplifier  5 , the divided voltage V fb , which is the voltage at the connection node of the resistors  2  and  3 , is applied to the inverted input terminal and the reference voltage V ref  is applied to the non-inverted input terminal. In the PWM comparator  7 , the error voltage V e  from the error amplifier  5  is applied to the inverted input terminal and the slope voltage V s  is applied to the non-inverted input terminal. The output signal Sq from the RS flip-flop circuit  9  is input to the gate of the switching transistor M 11 . The output signal Sq is also input to the gates of the NMOS transistors  55  and  57  after being inverted by the inverter  51 . 
         [0073]    In the slope voltage generator  6   a , the voltage-to-current converter  52 , the resistor  53 , and the capacitor  56  are connected in series between the input voltage V in  and ground. The NMOS transistor  55  is connected parallel to the capacitor  56 . The NMOS transistor  54  is connected between the connection node of the resistor  53  and the capacitor  56  and the drain of the switching transistor M 11 . The clock signal CLK is input to the gate of the NMOS transistor  54 . The NMOS transistor  57  and the capacitor  58  are connected in series between the drain of the switching transistor M 11  and ground. The voltage-to-current converter  52  includes an input terminal that receives a control signal and is connected to the connection node of the NMOS transistor  57  and the capacitor  58 . The slope voltage V s  is output from the connection node of the voltage-to-current converter  52  and the resistor  53  to the non-inverted input terminal of the PWM comparator  7 . 
         [0074]    In the above-described configuration, when the switching transistor M 11  is on for conduction, power is supplied from the DC power supply  20  to the inductor L 1 . When the switching transistor M 11  is off, the energy stored in the inductor L 1  is added to the input voltage V in  and output from the output terminal OUT. When the clock signal CLK is high, the RS flip-flop circuit  9  is set and outputs a high level output signal Sq to turn the switching transistor M 11  on for conduction. The error amplifier  5  outputs the error voltage V e  so that the divided voltage V fb  is equal to the reference voltage V ref . The PWM comparator  7  compares the slope voltage V s  with the error voltage V e . When the slope voltage V s  is higher than the error voltage V e , the PWM comparator  7  resets the RS flip-flop circuit  9  to turn the switching transistor M 11  off. 
         [0075]      FIG. 6  is a timing chart illustrating example waveforms in the switching regulator  1   a  of  FIG. 5 . Generation of the slope voltage V s  by the slope voltage generator  6   a  is described referring to  FIG. 6 . 
         [0076]    The voltage at the connection node of the NMOS transistor  57  and the capacitor  58  is equal to the output voltage V out , and therefore the voltage-to-current converter  52  generates and outputs a current i slope  corresponding to the output voltage V out . The current i slope  is expressed by D×V out , where D is a given value. An offset voltage V offset  added by the resistor  53  to have an offset voltage to ground voltage GND and is expressed by the following formula (9): 
         [0000]        V   offset   =i   slope   ×R   offset   (9) , 
         [0077]    where R offset  is the resistance value of the resistor  53 . 
         [0078]    The output voltage V out  is equal to a drain voltage VB of the switching transistor M 11  when the switching transistor M 11  is off. By turning the NMOS transistor  57  on when the switching transistor M 11  is off, the voltage across the capacitor  58  is held at the output voltage V out  and therefore i slope =D×V out . 
         [0079]    The NMOS transistor  54  performs sampling with the drain voltage VB of the switching transistor M 11  across the capacitor  56  during when the clock signal CLK from the oscillator  8  is high. After the sampling, the drain voltage VB of the switching transistor M 11  is equal to R on ×iL valley , where R on  is the on-resistance of the switching transistor M 11 , and iL valley  is the current value of an inductor current iL flowing through the inductor L 1  while the switching transistor M 11  is on. 
         [0080]    When the NMOS transistor  54  is off, the capacitor  56  is charged by the voltage-to-current converter  52  that forms a current source. The slope angle of the voltage of the capacitor  56  is equal to D×V out /Cvs, where Cvs is the capacitance of the capacitor  56 . Therefore, when the switching transistor M 11  is on, the slope voltage V s  is expressed by the following formula (10): 
         [0000]        V   s   =D×V   out   ×R   offset   +R   on   ×iL   valley   +D×V   out   /Cvs×t   (10), 
         [0081]    where t is the time elapsed since the switching transistor M 11  is turned on. 
         [0000]      When  D/Cvs=R   on   /L   (11), 
         [0082]    where L is the inductance of the inductor L 1 , the following formula (12) is obtained from the formula (10): 
         [0000]        dV   s   /dt=R   on   ×V   out   /L   (12) 
         [0083]    When the switching transistor M 11  is off, the NMOS transistor  55  is on and the charge stored in the capacitor  56  is discharged, thereby resetting the voltage of the capacitor  56  to ground. 
         [0084]    While the formula (11) is obtained by assuming that the on-resistance R on  is a constant value, and the current i slope  generated by the voltage-to-current converter  52  that forms a current source is expressed by D×V out , the on-resistance R on  generally fluctuates with respect to the temperature of the switching transistor M 11  and the gate voltage thereof during the on state. 
         [0085]    Considering the fluctuation in the on-resistance R on , the following formula (13) is obtained from the formula (10) by expressing the current i slope  by E×R on ×V out , where E is a given value: 
         [0000]        V   s   =E×R   on   ×V   out   ×R   offset   +R   on   ×iL   valley   +E×R   on   ×V   out   /Cvs×t   (13) 
         [0000]      When  E/Cvs= 1 /L   (14), 
         [0086]    the following formula (15) is obtained from the formula (13): 
         [0000]        dV   s   /dt=R   on   ×V   out   /L   (15) 
         [0087]    As can be seen from the formula (15), the slope angle dV 5 /dt of the slope voltage V s  fluctuates in accordance with fluctuation of the output voltage V out . Therefore, the slope voltage generator  6   a  increases the slope angle of the slope voltage V s  to have a larger slope angle than a slope angle of half the inductor current iL in a shut-down state in which the switching transistor M 11  is turned off. 
         [0088]      FIG. 7  is a diagram illustrating example circuitry of the voltage-to-current converter  52 . 
         [0089]    In  FIG. 7 , the voltage-to-current converter  52  forms a current source that generates the current i slope  corresponding to the output voltage V out  and includes error amplifiers  61  and  62 , PMOS transistors  63 ,  64 ,  65 , and  66 , NMOS transistors  67 ,  68 , and  69 , and resistors  70  and  71 . 
         [0090]    The PMOS transistors  63  and  64  form a current mirror circuit. The sources of the PMOS transistors  63  and  64  are connected to the input voltage V in , the gates thereof are connected with each other, and the connection node thereof is connected to the drain of the PMOS transistor  63 . The NMOS transistor  67  and the resistor  70  are connected in series between the drain of the PMOS transistor  63  and ground and the connection node thereof is connected the inverted input terminal of the error amplifier  61 . In the error amplifier  61 , a voltage equal to the output voltage V out  is applied to the non-inverted input terminal and the output terminal is connected to the gate of the NMOS transistor  67 . Although a voltage equal to the output voltage V out  is applied to the non-inverted input terminal of the error amplifier  61 , a description is given below of an example in which the output voltage V out  is applied to the non-inverted input terminal of the error amplifier  61 . 
         [0091]    The NMOS transistor  68  is connected between the drain of the PMOS transistor  64  and ground. The input voltage V in  is applied to the gate of the NMOS transistor  68 . 
         [0092]    The PMOS transistors  65  and  66  form a current mirror circuit. The sources of the PMOS transistors  65  and  66  are connected to the input voltage V in , the gates thereof are connected to each other, and the connection node thereof is connected to the drain of the PMOS transistor  65 . The NMOS transistor  69  and the resistor  71  are connected in series between the drain of the PMOS transistor  65  and ground and the connection node thereof is connected the inverted input terminal of the error amplifier  62 . In the error amplifier  62 , the non-inverted input terminal is connected to the connection node of the PMOS transistor  64  and the NMOS transistor  68  and the output terminal is connected to the gate of the NMOS transistor  69 . The current i slope  is output from the drain of the PMOS transistor  66 . 
         [0093]    In the above-described configuration, the error amplifier  61  controls the NMOS transistor  67  so that the same voltage is applied between its non-inverted input terminal and inverted input terminal. The resistors  70  and  71  are constant resistors with resistance values R 70  and R 71 , respectively, neither of which fluctuates. The NMOS transistor  68  is formed by the same process as the switching transistor M 11 . The input voltage V in  is applied to the gate of the NMOS transistor  68 . The NMOS transistor  68  has the size of 1/n of the switching transistor M 11  and the on-resistance of R on ×n. 
         [0094]    The output voltage V out  is applied to the non-inverted input terminal of the error amplifier  61  and the voltage across the resistor  70  is equal to the output voltage V out . Accordingly, the current of V out /R 70  flows through the resistor  70  and the NMOS transistor  68  via the current mirror circuit of the PMOS transistors  63  and  64 . Therefore, the voltage across the NMOS transistor  68  is equal to R on ×n×V out /R 70 . The error amplifier  62  controls the NMOS transistor  69  so that the voltage across the resistor  71  is equal to R on ×n×V out /R 70 . Therefore, the current of R on ×n×V out /R 70 /R 71  flows through the resistor  71 . The current i slope  is expressed by the following formula (16): 
         [0000]        i   slope   =E×R   on   ×V   out   (16), 
         [0095]    where E=n/R 70 /R 71 . 
         [0096]    The current-mode controlled switching regulator according to the second embodiment provides an appropriate slope compensation in a wide input/output voltage range with simple circuitry by changing the slope angle of the slope voltage V s  according to fluctuation in the output voltage V out . Therefore, subharmonic oscillation can be avoided. 
         [0097]    It should be noted that although the on-resistance of the switching transistor is used to convert a current into a voltage when the switching transistor is on in each of the above-described first and second embodiments, alternatively, a sense resistor may be connected in series to the inductor L 1 . In addition, the rectifying diode can be replaced by a synchronous rectification system using a synchronous rectification transistor that performs switching opposite to the switching of the switching transistor with the same effect. 
         [0098]    As can be understood by those skilled in the art, numerous additional modifications and variations are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the disclosure of this patent specification may be practiced otherwise than as specifically described herein. 
         [0099]    Further, elements and/or features of different example embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure and appended claims. 
         [0100]    Still further, any one of the above-described and other example features of the present invention may be embodied in the form of an apparatus, method, system, computer program or computer program product. For example, the aforementioned methods may be embodied in the form of a system or device, including, but not limited to, any of the structures for performing the methodology illustrated in the drawings. 
         [0101]    Example embodiments being thus described, it will be apparent that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.