Abstract:
A method and apparatus for determining the operational status of a photographic film processor, particularly an X-ray film processor. A photographic film is exposed to a test pattern including at least three areas to produce, upon development of said test film, a light (medium density) area, a dark (high density) area and an unexposed (base fog) area. The test film is then developed, and densitometer readings made of the resultant film densities in the test areas. These densitometer readings are used as inputs to digital logic circuitry to produce a series of diagnostic indications of the processor&#39;s operational status.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to photographic film processors and more particularly to a method and apparatus for automatically determining the operational status of the processor. In developing photographic films, it is important to closely monitor a number of critical parameters, such as for example, the temperature and strength of the chemical developers employed, to insure that the proper film densities are achieved. It is sometimes possible to determine that one or more of these parameters is not correct by inspection of a normally developed film, but without more information, identification of the specific cause of improper processing is difficult. 
     Manual comparison of a developed film (produced from calibrated exposure of sections of the film) to predetermined density standards and analysis of the results of this comparison (sometimes requiring trial and error adjustments of the processor) is presently relied upon to determine the operational status of X-ray film processors in some hospitals. The general object of the present invention is to provide a method and apparatus for performing this function automatically. 
     This invention allows an operator to isolate the specific cause of improper development of a test film strip, by automatically measuring the densities of the film at three specific test areas, and then using the results of these measurements to determine the operational status of the processor. The operator can then make any required adjustments to the processor and proceed to develop other films without resorting to the usual trial and error approach to identify which parameters should be changed. This saves time and material and since the necessary adjustments are automatically indicated, this invention reduces the skill levels required of the personnel operating the film processor. 
     SUMMARY OF THE INVENTION 
     A photographic film is exposed to a test pattern including at least three areas to produce, upon development of said test film, a light (medium density) area, a dark (high density) area and an unexposed (base fog) area. The test film is then processed and the developed film is inserted into the apparatus of this invention between a constant light source means (three light emitting diodes in the embodiment of the invention described and illustrated) and a photodetector means (three phototransistors in the illustrated embodiment). The density of this film in three test areas (high and medium density areas and the unexposed base fog area of the film) is sensed by the photodetector means which produces output signals indicative of high density (dark) area above or below a first preselected density limit, medium area above, within or above second and third preselected density limits, and base fog area above or below a fourth preselected density limit. These signals are then operated upon by digital logic to generate automatically status indications indicative of the operational status of the processor used to process the test film. 
     Accordingly, it is a primary object of this invention to provide a method of automatically detecting the operational status of a film processor. 
     It is another object of the invention to provide an apparatus capable of automatically inspecting a test film to produce output indications relative to the operational status of the film processor used to process the test film. 
     These and other objects and advantages will become more fully apparent to those skilled in the art from the following description, taken in conjunction with the accompanying drawings, in which like reference numerals designate like parts. 
    
    
     BRIEF DESCRIPTION OF THE INVENTION 
     FIG. 1 is a functional block diagram depicting an embodiment of the invention; 
     FIG. 2a is a schematic diagram of the densitometer and attendant light intensity control and timer circuitry of an apparatus embodying the invention; and 
     FIG. 2b is a schematic diagram of the digital logic circuitry embodying the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a representation of the overall operation of the preferred embodiment of the present invention. First, the density of various portions of a test film is measured by interposing the test film between light emitting diodes (LED), and phototransistors, and comparing the measured voltage output of the phototransistors with preset voltages to derive an output indicative of the density of the test film. The outputs are then operated upon logically to produce status indications relative to the developing process employed to develop the test strip. 
     An area of the test film which has been exposed with a test pattern and developed to produce one area of medium density (hereinafter referred to as the Medium Area) is illuminated by LED I 1 . The output is measured by a detector PT 1  and then applied to two voltage comparators, C 1  and C 2  to generate three different conditions -- too light, too dark or acceptable. Similarly, an area of the test film which has been &#34;maximally&#34; exposed and developed to produce a dark area is scanned to determine if the density is too light or acceptable. An area of the developed test film upon which no test pattern has been exposed (hereinafter referred to as the Base Fog Area) is scanned to determine if the density is too dark or acceptable. 
     These seven outputs, and outputs from a clock and multivibrator, are then acted upon logically to activate the various possible LED&#39;s labelled as shown in FIG. 1. The possible outputs of the film measuring circuit can be best summarized by the following Truth Table when the output states are defined as follows: 
     Base Fog Area (B) acceptable -- 1; too dark -- 0 
     Dark Area (D) acceptable -- 1; too light -- 0 
     Medium Area (M L ) acceptable -- 1; too light -- 0 
     Medium Area (M D ) acceptable -- 1; too dark -- 0 
     
                       TABLE 1______________________________________B      D        M.sub.L  M.sub.D                           Condition______________________________________0      0        0        0      --0      0        0        1      F0      0        1        0      E0      0        1        1      --0      1        0        0      --0      1        0        1      --0      1        1        0      E0      1        1        1      --1      0        0        0      --1      0        0        1      C1      0        1        0      --1      0        1        1      --1      1        0        0      --1      1        0        1      B1      1        1        0      D1      1        1        1      A______________________________________ 
    
     The indicator LED&#39;s which are used to indicate the status of the film processor are as follows: 
     
         ______________________________________LED No.     Condition______________________________________D.sub.1     AcceptableD.sub.2     Developer UnderreplenishedD.sub.3     Developer Temperature Too LowD.sub.4     Developer OverreplenishedD.sub.5     Developer Temperature Too HighD.sub.6     Developer Contaminated______________________________________ 
    
     When the conditions, as defined in Table 1, exist, the following LED&#39;s are illuminated: 
     
         ______________________________________Condition    Output______________________________________None of A-E  D.sub.1 blinksA            D.sub.1 steadyB            D.sub.2 steadyC            D.sub.2 blinks, D.sub.3 steadyD            D.sub.4 steadyE            D.sub.4 blinks; D.sub.5 steady; D.sub.6 steadyF            D.sub.6 blinks______________________________________ 
    
     The test film is inserted between three light emitting diodes (I 1 , I 2 , I 3 ) and their associated phototransistors (PT 1 , PT 2 , PT 3 ). By comparing the output of each phototransistor with preset voltage levels, it is possible to determine whether the density of the test film falls within certain limits. Specifically, when the test film has been inserted into the reading position, and off/on switch S 1  is placed in the &#34;on&#34; position, a voltage, the value of which is controlled by the light intensity control section in a manner to be described below, is applied through respective resistors R 1 , R 2 , R 3  and R 4  to light emitting diodes I 1 , I 2 , I 3 , and I 4 . LED I 1  illuminates the Medium Area of the test film. The amount of light which passes through the test film, and impinges upon phototransistor PT 1  is a function of the density of the film. The voltage, V 1 , is thus a function of the density of the Medium Area of the film. V.sub. 1 can be varied by changing the setting of potentiometer R 5  when initially calibrating the system. V 1   is applied to one leg of voltage comparator C 1 . A reference voltage V 2 , determined by the adjustment of potentiometer R 6 , is applied to the other leg of voltage comparator C 1 . When V 1  is less than V 2 , the output of C 1  is 5 volts (or high). When V 1  is more than V 2 , the output of C 2  is 0 volts (or low). 
     The output of C 1  is continuously applied to latch L 1 . Latch L 1  &#39;s output follows its input until a low appears on the timer input line at which time the output is &#34;latched&#34; to the value present on the input line. 
     V 1  is also applied to one leg of voltage comparator C 2 . A reference voltage V 3 , determined by the adjustment of potentiometer R 7  is applied to the other leg of C 2 . When V 1  is less than V 3 , the output of C 2  is low. The output of C 2  is applied to latch L 2  which functions similarly to latch L 4 . 
     Latch L 1  will have a high output if the Medium Area is too light, as indicated in FIG. 2a. 
     Latch L 2  will have a high output if the Medium Area is too dark, as indicated in FIG. 2a. 
     The output of NOR gate G 7  is high only when both inputs from latches L 1  and L 2  are low, i.e., when the Medium Area density is neither too high nor too low, as indicated in FIG. 2a. 
     Similar circuits are used to measure the density of the Medium Area and Base Fog Area. The resistance ranges of potentiometers R 5 , R 8  and R 9  are different, being chosen with a resistance range appropriate to the density range of the area of the test film being measured. 
     The output of latch L 3  is high when the Dark Area is too light, and low when the Dark Area is acceptable, as indicated in FIG. 2a. 
     Latch L 4  has two outputs (normal and inverted) so no inverter is necessary. As indicated in FIG. 2a, the outputs relative to the Base Fog Area are either acceptable or too dark. 
     Before discussing the logic circuitry which operates upon the detector outputs, the Light Intensity Control and Timer will be briefly discussed. 
     The Light Intensity Control is comprised of LED I 4  ; phototransistor PT 4  ; resistances R 4 , R 10 , R 11 , R 12 , R 13  and transistors T 1  and T 2 . The purpose of this circuit is to monitor the output of I 4  to hold its light intensity constant. If the light intensity from I 4  varies, PT 4  in conjunction with power transistor T 1  and control transistor T 2  varies the voltage to I 1 , I 2 , I 3 , and I 4 , to stabilize their intensity at a constant level. 
     The timing circuit consists of a conventional timer activated by microswitch S 2  when the film is inserted. Approximately five seconds after the film is inserted (assuming that S 1  is in the on position), the output of the timer goes from low to high, as shown in the output waveform sketch in FIG. 2a. This output is applied to NAND gates G 1  through G 6  and, through inverter G 9 , to latches L 1 , L 2 , L 3 , L 4 . 
     This concludes the description of the densitometer section of the invention. Once the device has been turned on, the film inserted, and the 5 second time period has elapsed, the following high inputs to NAND gates G 1  through G 6  are possible. 
     
         ______________________________________  NAND Gate G.sub.1______________________________________  Middle Area - Acceptable  Base Fog Area - Acceptable  Dark Area - Acceptable  Timer______________________________________ 
    
     When all high inputs are applied to gate G 1 , a low is applied to AND gate G 14  then outputs a low, lighting LED D 1 , indicating &#34;acceptable.&#34; 
     
         ______________________________________  NAND Gate G.sub.2______________________________________  Base Fog Area - Acceptable  Dark Area - Acceptable  Middle Area - Too Light  Timer______________________________________ 
    
     When all high inputs are applied to NAND gate G 2 , a low input is applied to AND gate G 15 , lighting LED D 2 , indicating &#34;Developer Underreplenished.&#34; 
     
         ______________________________________  NAND Gate G.sub.3______________________________________  Base Fog Area - Acceptable  Dark Area - Too Light  Middle Area - Too Light  Timer______________________________________ 
    
     When all high inputs are applied to NAND gate G 3 , a low output causes LED D 3  to illuminate, indicating &#34;Developer Temperature Too Low.&#34; 
     
         ______________________________________  NAND Gate G.sub.4______________________________________  Base Fog Area - Acceptable  Dark Area - Acceptable  Middle Area - Too Dark  Timer______________________________________ 
    
     When all high inputs are applied to NAND gate G 4 , a low input is applied to AND gate G 16  causing LED D 4  to illuminate indicating &#34;Developer Overreplenished.&#34; 
     
         ______________________________________  NAND Gate G.sub.5______________________________________  Base Fog Area - Too Dark  Middle Area - Too Dark  Timer______________________________________ 
    
     When the three inputs applied to NAND gate G 5  are high, NAND gate G 5  goes low, illuminating LED D 5  indicating &#34;Developer Temperature Too High.&#34; 
     
         ______________________________________  NAND Gate G.sub.6______________________________________  Multivibrator  Timer  Middle Area - Too Light  Dark Area - Too Light  Base Fog Area - Too Dark______________________________________ 
    
     When all of the inputs to NAND gate G 6  are high, G 6  goes low. This output, applied to AND gate G 17 , illuminated LED D 6  indicating &#34;Developer Contaminated.&#34; Since one of the inputs to NAND gate G 6  is from a conventional multivibrator, MV, shown in FIG. 2a, the LED will blink at the frequency of the multivibrator whose output alternates between 0 and 5 volts, as shown. 
     As described above, NAND gates G 1  through G 6  have a low output when six possible sets of inputs (covering all possible film conditions of interest) appear. NAND gate G 10  has as inputs the output lines from each NAND gate G 1  through G 6  and an input from the timer and multivibrator. When all of these inputs are high, the output of gate G 10  is low. This low is input to AND gate G 14 , lighting LED D 1 . Since one of the inputs to G 10  is the multivibrator, the LED will blink. 
     The output of NAND gate G 3  is applied to the OR gate G 11 , as is the multivibrator output. Accordingly, when gate G 3  is low, a pulsing low signal to AND gate G 15 , blinking LED D 2 . 
     When NAND gate G 5  goes low, a low input is applied to OR gate G 12 , which causes LED D 1  to blink. This input is also applied to AND gate G 13  so that LED D 6  burns steadily. 
     Use of this invention obviously depends upon a test film developed in the processor to be evaluated or controlled. The test film must first be exposed under conditions to produce the so-called &#34;Dark Area,&#34; &#34;Medium Area&#34; and the unexposed Base Fog Area. Moreover, the exposure must be calibrated, taking into account the exposure characteristics of the film used so that the density in the three test areas will be within preselected density limits if the film is developed in a processor operating under proper conditions of temperature, developer replenishment and development purity. Representative exposure parameters, in conjunction with equipment and film specifications for producing a test film compatible with the test instruments heretofore described are as follows. Kodak RPL X-ray film, having known developed density to exposure characteristic, is exposed in a preselected Dark Area and Medium Area, respectively, using a density wedge (a strip having a multiplicity of gradations of grey tones ranging from white to black) and a Kodak sensitometer, such that the film, when properly developed has a base fog density in the unexposed area of below 0.23 density units (density units = 1/log transmissivity), a density in the Medium Area of from 1.0 to 1.3 density units and a density in the Dark Area of above 3.4 density units. 
     In the signalling set up represented by light emitting diodes D 2  -D 6 , a blinking signal is used to indicate an irreversible type of processor dysfunction, i.e., a problem which can not be rectified by adjustment of the processor operating conditions but rather requires a complete change, such as complete developer replacement. 
     While the inventive methods and apparatus have been described with sufficient detail to enable one skilled in the art to practice the teachings contained herein, it is anticipated that many structural variations, as well as electronic circuit equivalents, may be developed by those skilled in the art. 
     For example, it may be preferable to substitute photo-voltaic cells, with integral temperature compensation circuitry including amplifiers, for the phototransistors PT 1 , PT 2 , PT 3  and PT 4  in order to avoid certain problems which have been encountered due to the temperature sensitive drift of the phototransistors shown in the illustrated embodiment of this invention. 
     Similarly, the light intensity control circuit, comprised of LED I 4  and associated components in the illustrated embodiment may be omitted and a separate photodetector with appropriate feed back circuitry may be associated with the actual light sources I 1 , I 2  and I 3 , or any one of these (of which the preferred single for this purpose would be the high density area light source I 2 ) to maintain relatively constant output intensity of each of light sources I 1 , I 2  and I 3 . 
     Associated elements would of course be included with each such additional photodetector, either to stabilize the intensity of the particular light source sensed or of all of the light sources. The additional photodetector used in such alternative light intensity control would of course be placed to sense light received directly from LED I 1 , I 2  and/or I 3  without passing through the film otherwise inserted between the respective LED&#39;s and associated photodetectors used in the density sensing function of the apparatus of this invention. 
     In optimizing the device disclosed and illustrated herein, it is expected that a second timer and latch combination will be included in the circuit to turn off all circuitry after a preselected delay, nominally six seconds, following the output reading indicated by the actuation of one or more of LED&#39;s D 1 , D 2 , D 3 , D 4 , D 5  and/or D 6 . The purpose of this second timer and latch means is to prevent overheating of the circuitry and particularly the light sources and photodetectors in the event the operator neglects to switch the device off. 
     As will be apparent to those skilled in the art, output signals from gates G 1 , G 2 , G 3 , G 4 , G 5  and G 6  may be used directly to control automatically temperature and developer replenishment rate in an associated film processor. Such direct control may be in addition to the logic circuit and output indicators shown in the illustrated embodiment of the invention, or it may obviate the need for such logic circuit and indicators. 
     In consideration of all of these factors, the appended claims are intended to be interpreted to cover all such variations and modifications which may be made without departing from the true spirit and scope of this invention.