Abstract:
Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.

Description:
TECHNICAL FIELD 
       [0001]    Embodiments of the invention relate to memory systems in electronic devices. More particularly, embodiments of the invention relate to hybrid memory architectures that may be utilized in electronic devices. 
       BACKGROUND 
       [0002]      FIG. 1  is a block diagram of a current processing system having dual data rate (DDR) memory modules and non-volatile memory. Example computer system  100  includes one or more processor cores  110  that are coupled to memory. Processor core(s)  110  may be coupled to multiple dual-inline memory modules (DIMMs)  130  via DDR channels  120 . Computer system  100  includes two DDR channels, but additional links may also be included. 
         [0003]    Processor core(s)  110  may also be coupled to non-volatile memory  160  via link  150 . The non-volatile memory may include, for example, flash memory (NAND or NOR), phase change memory, etc. In these systems memory bandwidth is dependent on DDR technology scaling and the number of DDR channels in the system. 
         [0004]    Beyond certain frequencies, scaling of DDR channels becomes increasingly expensive and complex. Thus, increasing memory bandwidth my adding DDR channels and/or increasing channel frequency can drastically increase the cost of the system. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements. 
           [0006]      FIG. 1  is a block diagram of a current processing system having dual data rate (DDR) memory modules and non-volatile memory. 
           [0007]      FIG. 2  is a block diagram of one embodiment of a processing system having a hybrid memory module. 
           [0008]      FIG. 3  is a flow diagram of one embodiment of a technique for retrieving requested data from memory in a system having a hybrid memory module. 
           [0009]      FIG. 4  is a block diagram of one embodiment of a user-upgradable memory module that may allow modification of a system with a hybrid memory module architecture. 
           [0010]      FIG. 5  is a block diagram of one embodiment of a processing system having a user-upgradable hybrid memory module. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    In the following description, numerous specific details are set forth. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. 
         [0012]      FIG. 2  is a block diagram of one embodiment of a processing system having a hybrid memory module. The example embodiment of  FIG. 2  is processing system  200  that includes processor core(s)  210 . Processing system  200  may be any type of processing system, for example, a laptop computer system, a desktop computer system, a server, etc. 
         [0013]    Processing system  200  includes processor complex  290 , which further includes processor core(s)  210 . Processor core(s)  210  may include any number of processor cores in any configuration known in the art. In one embodiment, processor complex  290  includes multiple components within a single integrated circuit package. In alternate embodiments, multiple integrated circuit packages may be used. 
         [0014]    Processor core(s)  210  are coupled with DIMMs  230  via DDR channel  220 . In one embodiment, processing system  200  includes only a single DDR channel. In alternate embodiments, multiple DDR channels may be supported. As described in greater detail below, at least one DDR channel may be replaced by a hybrid memory structure that is included in processor complex  290 . 
         [0015]    In one embodiment, processor complex  290  includes a hybrid memory module coupled with processor core(s)  210 . The hybrid memory module partially or completely offsets the memory capacity and memory bandwidth lost by absence of the deleted DDR channel. In one embodiment, the bandwidth loss is offset by use of high density memory (HDM) compatible with logic process  260  (e.g. embedded DRAM, Resistive-RAM, Thyristor-RAM, Ferroelectric-RAM) that is included in processor complex  290  and coupled with processor core(s)  210 . In one embodiment, flash memory (e.g., NAND memory)  250  is included in the hybrid memory module to function as a disk cache to offset loss of the DIMMs from the lost DDR channel. In an alternate embodiment, the hybrid memory module may include standard DRAM and NAND flash memory. Other combinations can also be supported. 
         [0016]    In some applications, the combination of one DDR channel with the hybrid memory module may provide better performance than a two DDR channel system. In one embodiment, HDM  260  is an eDRAM last level hardware managed cache memory with misses serviced by the DDR memory. In other embodiments HDM is resistive-RAM, Thyristor-RAM, or Ferroelectric-RAM). Flash memory  250  may act as a disk cache and buffer against slow hard disk accesses. 
         [0017]    In one embodiment, processor complex  290  may be coupled with an external memory other than through the DDR channel. For example, processor complex  290  may be coupled with phase change memory (PCM)  280  via memory link  270 . 
         [0018]      FIG. 3  is a flow diagram of one embodiment of a technique for retrieving requested data from memory in a system having a hybrid memory module. During the course of execution of instructions a processor core will be required to retrieve data from some memory storage element. The processor core may include one or more levels of cache memory. Use of cache multiple levels of cache memory in a processor core is known, and any appropriate cache memory structure may be utilized. 
         [0019]    A memory request is generated by the processor core,  310 . In response to the memory request the processor core may search one or more levels of cache memory,  320 . If the requested data is found in the cache memory included in the processor core, a cache hit condition exists,  330 , and the requested data is used by the processor core,  370 . 
         [0020]    If the data is not found in the cache memory included in the processor core, a cache miss condition exists,  330 , and the hybrid memory module is searched for the requested data,  340 . In one embodiment, the hybrid memory module is included in a processor complex, but is not included in the processor core. In another embodiment, the hybrid memory module may be external to the processor core and a processor complex, or there may be no processor complex and the hybrid memory module may be external to the processor core package. 
         [0021]    In one embodiment, the hybrid memory module functions as a last-level hardware managed cache with misses serviced by external memory, for example, the DDR system memory. In one embodiment, the last-level hardware cache functionality is provided by eDRAM in the hybrid memory module. If the requested data is found in the hybrid memory module, a cache hit condition exists,  350 , and the requested data is used by the processor core,  370 . In other embodiments the last-level hard cache functionality is provided by resistive-RAM, Thyristor-RAM, or Ferroelectric-RAM. 
         [0022]    If the data is not found in the hybrid memory module, a cache miss condition exists,  350 , and the external memory is searched for the requested data,  360 . In one embodiment, the external memory includes at least the DDR system memory (e.g., DIMMs  230  in  FIG. 2 ). In one embodiment, the external memory may also include phase change memory (PCM), for example, PCM  280  in  FIG. 2 . In one embodiment, the hybrid memory module and/or PCM can operate as a disk cache to provide buffering against a slower hard disk drive or other mass storage device. 
         [0023]    The hybrid memory module architecture described herein may be particularly beneficial for certain types of computing tasks. For example, in gaming or graphical design workloads, the bandwidth provided by the HDM is generally greater than the bandwidth provided by a two-channel DDR system memory, which provides improved performance for graphical tasks. 
         [0024]      FIG. 4  is a block diagram of one embodiment of a user-upgradeable memory module that may allow modification of a system with a hybrid memory module architecture. By varying the HDM and non-volatile memory sizes, platform performance segmentation can be created. In one embodiment, a NAND controller is part of the module and can use processor core processing power and memory for NAND management. 
         [0025]    Processor complex  410  can include any number of processor cores (e.g.,  420 ,  425 ).  FIG. 4  provides an example illustration with two processor cores for reasons of simplicity of description only. Any number may be supported. Processor complex  410  may be coupled with hybrid memory module  450  via interconnect  440 . Interconnect may be a rigid or a flexible connection mechanism that may allow a user to connect and disconnect hybrid memory module  450 . 
         [0026]    Hybrid memory module  450  includes HDM  460  and non-volatile memory  470 . In one embodiment, hybrid memory module  450  includes a fixed amount of eDRAM and non-volatile memory, for example, in a single package. In an alternate embodiment, eDRAM  460  and/or non-volatile memory  470  may be user removable and upgradeable. In other embodiments the HDM is resistive-RAM, Thyristor-RAM, or Ferroelectric-RAM. 
         [0027]      FIG. 5  is a block diagram of one embodiment of a processing system having a user-upgradeable hybrid memory module. The example embodiment of  FIG. 5  is processing system  500  that includes processor core(s)  510 . Processing system  500  may be any type of processing system, for example, a laptop computer system, a desktop computer system, a server, etc. 
         [0028]    Processor core(s)  510  may include any number of processor cores in any configuration known in the art. In one embodiment, processor core(s)  510  may be multiple components within a single integrated circuit package. In alternate embodiments, multiple integrated circuit packages may be used. 
         [0029]    Processor core(s)  510  are coupled with DIMMs  530  via DDR channel  520 . In one embodiment, processing system  500  includes only a single DDR channel. In alternate embodiments, multiple DDR channels may be supported. As described in greater detail below, at least one DDR channel may be replaced by a hybrid memory  590 . In the example of  FIG. 5 , processor core(s)  510  may be coupled with hybrid memory  590  via an interconnect as described above with respect to  FIG. 4 . 
         [0030]    In one embodiment, hybrid memory module  590  is coupled with processor core(s)  510 . Hybrid memory module  590  partially or completely offsets the memory capacity and memory bandwidth lost by absence of the deleted DDR channel. In one embodiment, the bandwidth loss is offset by use of high density memory (HDM) compatible with logic process  560  (e.g. embedded DRAM, Resistive-RAM, Thyristor-RAM, Ferroelectric-RAM) coupled with processor core(s)  510 . In one embodiment, flash memory (e.g., NAND memory)  550  is included in the hybrid memory module to function as a disk cache to offset loss of the DIMMs from the lost DDR channel. In an alternate embodiment, the hybrid memory module may include standard DRAM and NAND flash memory. Other combinations can also be supported. 
         [0031]    In some applications, the combination of one DDR channel with the hybrid memory module may provide better performance than a two DDR channel system. In one embodiment, HDM  560  is an eDRAM last level hardware managed cache memory with misses serviced by the DDR memory. In other embodiments HDM is resistive-RAM, Thyristor-RAM, or Ferroelectric-RAM). Flash memory  550  may act as a disk cache and buffer against slow hard disk accesses. 
         [0032]    In one embodiment, processor core(s)  510  may be coupled with an external memory other than through the DDR channel. For example, processor core(s)  510  may be coupled with phase change memory (PCM)  580  via memory link  570 . 
         [0033]    Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. 
         [0034]    While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.