Abstract:
Disclosed are a switch mode power amplifier and a field effect transistor especially suitable for use in a switch mode power amplifier. The transistor is preferably a compound high electron mobility transistor (HEMT) having a source terminal and a drain terminal with a gate terminal therebetween and positioned on a dielectric material. A field plate extends from the gate terminal over at least two layers of dielectric material towards the drain. The dielectric layers preferably comprise silicon oxide and silicon nitride. A third layer of silicon oxide can be provided with the layer of silicon nitride being positioned between layers of silicon oxide. Etch selectivity is utilized in etching recesses for the gate terminal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of co-pending application Ser. No. 11/187,171 filed Jul. 21, 2005 which is related to co-pending application Ser. No. 11/132,619, assigned to the present assignee, which is incorporated herein by reference for all purposes. This application is related to the following co-pending applications: U.S. Patent Publication No. US20050051796A1, entitled “WIDE BANDGAP TRANSISTOR DEVICES WITH FIELD PLATES”; U.S. Patent Publication No. US20050051800A1, entitled “CASCODE AMPLIFIER STRUCTURES INCLUDING WIDE BAND GAP FIELD EFFECT TRANSISTOR WITH FIELD PLATE”; U.S. patent application Ser. No. 10/958,970, filed Oct. 4, 2004, entitled “WIDE BAND GAP FIELD EFFECT TRANSISTORS WITH FIELD PLATES”; U.S. patent application Ser. No. 10/976,422, filed Oct. 29, 2004, entitled “WIDE BAND GAP FIELD EFFECT TRANSISTOR WITH DUAL FIELD PLATES”; U.S. patent application Ser. No. 10/958,945, filed Oct. 4, 2004, entitled “WIDE BAND GAP FIELD EFFECT TRANSISTORS WITH SOURCE CONNECTED FIELD PLATES”; and U.S. patent application Ser. No. 11/078,265, filed Mar. 11, 2005, entitled “WIDE BAND GAP FIELD EFFECT TRANSISTORS WITH GATE-SOURCE FIELD PLATES”, all of which are incorporated herein by reference for all purposes. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    This invention relates generally to power amplifiers, and more particularly the invention relates to switch-mode power amplifiers and transistors useful therein. 
         [0003]    Switch mode power amplifiers have attracted a significant amount of interest for use in applications requiring highly efficient power amplification of high frequency signals. Examples of applications of such devices include power amplifiers for wireless communications systems, satellite communications systems, and advanced radar systems. In particular, high power, high frequency power amplifiers are needed for digital communication systems such as 3G and 4G PCS systems, WiFi, WiMax and digital video broadcast systems. For applications requiring high output power, the power amplifier accounts for a significant portion of the overall power consumed by the system. Thus, it is desirable to maximize the efficiency of the power amplifier circuit in a communication system. 
         [0004]    Co-pending application Ser. No. 11/132,619, supra, discloses a single-stage switch mode amplifier circuit which includes an active device switch transistor configured to operate in either an ON state or an OFF state depending on the signal level of an input signal. The switch transistor has an output connected to a load network which filters the signal output from the switch transistor to provide a narrow-bandwidth output signal to a load impedance. Energy rejected by the load network is stored in a switch capacitor which continues to drive the output signal while the switch transistor is in the OFF state. Drain voltage to the switch transistor is provided through a drain inductor which prevents instantaneous changes in source current. In some embodiments, the amplifier operates in Class E mode. 
         [0005]    In some embodiments, a switch mode amplifier circuit includes an input matching stage, an active stage and an output matching stage. The active stage includes an active device switch transistor in parallel with a switch capacitor. The switch transistor has an output connected to a load network and a load impedance. The output of the device, which comprises the voltage across the load impedance, is supplied to the output matching stage, which transforms the output impedance of the active stage to the desired output impedance of the circuit. In other embodiments, multiple active transistor stages and matching networks may be used to provide additional amplifier gain (e.g. 2-stage amplifiers, etc.) 
         [0006]    The switch transistor can comprise a wide bandgap MESFET transistor capable of sustaining high drain voltages and/or high current levels while operating at frequencies in excess of 1.0 GHz. In some embodiments, the switch transistor comprises a gallium nitride (GaN) based high electron mobility transistor (HEMT). In some embodiments, the switch transistor comprises a GaN based HEMT having a total gate periphery of about 3.6 mm. In some embodiments, the switch transistor comprises a GaN MESFET. In other embodiments, the switch transistor comprises a different wide bandgap high frequency transistor, such as a SiC MESFET, SiC LDMOS, SiC bipolar transistor, or GaN MOSFET device. 
         [0007]    Switch mode operation of field effect transistors in an amplifier requires robust operation at microwave frequencies under high compression. In practice, this is difficult to realize due to the very large forward currents that flow from gate to source under high input drive as needed for switch mode operation. 
       SUMMARY OF THE INVENTION 
       [0008]    The invention is directed to a field effect transistor which can be used in a switch mode power amplifier with more robust operation under high compression. 
         [0009]    More particularly, the transistor is a high electron mobility transistor (HEMT) which includes a gate dielectric to limit forward conduction from gate to source under high input drive and suppress gate leakage during high-voltage, high-temperature operation. 
         [0010]    Further, a gate field plate extension can be provided to shape the peak electric field with minimum impact on added gate capacitance. Two or more dielectric layers can be employed under the field plate and provide a thicker dielectric to minimize impact on gate capacitance. 
         [0011]    In accordance with a feature of the invention, etch selectivity between the two different insulators can be employed in fabricating the gate electrode. 
         [0012]    The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a schematic of one embodiment of a switch mode power amplifier in accordance with the invention. 
           [0014]      FIG. 2  is a functional block diagram of a switch mode power amplifier in accordance with the invention. 
           [0015]      FIG. 3  is a section view of a high electron mobility transistor (HEMT) useful in the switch mode power amplifier in accordance with an embodiment of the invention. 
           [0016]      FIG. 4  is a section view of a HEMT useful in the switch mode power amplifier in accordance with another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    Referring now to  FIG. 1 , a single-stage switch mode power amplifier circuit model  10  in accordance with an embodiment of the invention is illustrated. Amplifier  10  includes a metal-insulator-semiconductor transistor  12  comprising a wide bandgap transistor which functions as an on/off switch. The use of an insulator separating the gate from the semiconductor body limits forward conduction from gate to source under high stress drive, in some embodiments. The transistor  12  comprises a GaN HEMT. Transistor  12  may alternatively comprise a different wide bandgap high-frequency transistor, such as a SiC MESFET, GaN MESFET, SiC LDMOS, SiC bipolar transistor, or GaN MOSHFET device. 
         [0018]    An input voltage signal vi is applied to the gate of transistor  12 , which controls the state of the transistor  12 . The input voltage signal vi is biased close to the pinch-off voltage of the transistor  12 . The drain of the transistor  12  is coupled to an output node S, and the source of transistor  12  is coupled to ground. A supply voltage VDD is coupled to output node S via an inductor LDS. The voltage at output node S is applied to a series resonant circuit  14  which comprises an inductor L o  and a capacitor C o  In some applications, the series resonant circuit  14  may be a bandpass circuit tuned to pass a narrow range of frequencies centered on the desired output frequency f o  of the amplifier circuit  10 . In other applications such as radar applications, the series resonant circuit may be tuned to pass a broader range of frequencies. At the output frequency, the transistor output is presented with a load equal to R+jX, where X is the reactance of the resonant circuit seen at the output. 
         [0019]    When the transistor  12  is in the on state (i.e. the transistor is saturated), the device acts as a short circuit to ground, pulling the voltage at node S to zero. Current through the inductor L DS  then increases linearly. When the transistor is turned off, the current through L DS  is steered into the drain-source capacitance C DS , causing the voltage at node S to rise until it reaches a maximum, at which point the voltage at node S begins to decrease as the drain-source capacitance C DS  begins to source current back to the load. The resonant circuit  14  is tuned such that in steady state, the voltage at node S returns to approximately zero before the transistor is turned on again. 
         [0020]    The resonant circuit  14  ideally passes only the fundamental frequency of the voltage at node S. The input voltage v i  may carry modulated frequency or phase information that is present in the amplified output signal. 
         [0021]    As illustrated in  FIG. 2 , an amplifier circuit  20  may include a Class E amplifier  10  having an input  10 A and an output  10 B. An input matching network  22  is coupled to the input  10 A and an output matching network  24  is coupled to the output  10 B of the amplifier  10 . The input matching network  22  matches the impedance seen by the input signal v i  to the input impedance of the amplifier  10 , while the output matching network  24  transforms the output impedance of the amplifier  10  to a desired output impedance, e.g. 50 ohms. 
         [0022]    Referring now to  FIGS. 3 and 4 , two embodiments of field effect transistors in accordance with the invention are illustrated in cross section. 
         [0023]    In  FIG. 3 , the transistor includes a structure which can be similar to the structure described in application Ser. No. 11/132,619, supra. For example. substrate  30  can be silicon carbide, buffer or nucleation layer  32  can be AlGaN or GaN, channel layer  34  can be InAlGaN, GaN or AlGaN, and barrier layer  36  can be a group III nitride. As described in application Ser. No. 11/132,619, buffer layer  32  on the substrate  30  provides an appropriate crystalline transition between the substrate  30  and the remainder of the device. Buffer layer  32  may include one or more layers of InAlGaN. In particular embodiments, buffer layer  32  may include GaN, AlN or AlGaN. Silicon carbide has a much closer crystal lattice match to Group III nitrides than does sapphire (Al 2 O 3 ), which is a very common substrate material for Group III nitride devices. The closer lattice match may result in Group III nitride films of higher quality than those generally available on sapphire. Silicon carbide also has a very high thermal conductivity so that the total output power of Group III nitride devices on silicon carbide is, typically, not as limited by thermal dissipation of the substrate as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating silicon carbide substrates may provide for device isolation and reduced parasitic capacitance. Exemplary HEMT structures are illustrated in U.S. Pat. Nos. 6,316,793, 6,586,781 6,548,333 5,192,987 and 5,296,395 and U.S. Published Patent Application Nos. 2002/0167023 and 2003/0020092 each of which is incorporated by reference as though fully set forth herein. 
         [0024]    Although semi-insulating silicon carbide is the preferred substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In addition, the substrate may be conductive, semi-insulating or highly resistive. In embodiments comprising a MMIC, it is desirable to use a semi-insulating or highly resistive substrate. In some embodiments, an appropriate buffer layer also may be formed. 
         [0025]    Provided on barrier layer  36  is a first dielectric layer  38  with a second dielectric layer  40  on dielectric layer  38 . Contact holes are etched through layers  38 ,  40  for a source contact  42  and a drain contact  44 . A preferential etchant can be used to etch only dielectric  40  with a gate contact  46  formed on gate dielectric  38 . For example, dielectric  38  can be silicon oxide and dielectric  40  can be silicon nitride. Alternatively, the two dielectric layers can be the same material which is deposited or formed at different times in the process to form two layers. Other known barrier layer materials can be employed, also. 
         [0026]    In accordance with a feature of the invention, gate contact  46  can be extended over dielectric layer  40  towards the drain, as shown at  46 ′ to form a field plate extension. The field plate extension of the gate electrode towards the drain over the thicker dielectric can be designed to shape the peak electric field with minimum impact on increased gate capacitance. The use of a field plate in other applications is known. 
         [0027]      FIG. 4  illustrates in cross-section another embodiment of a field effect transistor in accordance with the invention. Here, the substrate  30  and layers  32 - 36  can be the same as in  FIG. 3 . However, in this embodiment three dielectric layers are employed including layers  38  and  40  as in  FIG. 3  along with a third dielectric layer  48 . Here the gate contact opening is etched through both dielectric layers  38 ,  40  and then the third dielectric is deposited in the gate opening. Gate metallization is then deposited on the stacked dielectric to form gate electrode  46 , which can have a shorter gate length, L G , and lower capacitance than other structures. 
         [0028]    In  FIGS. 3 and 4 , dielectric  38  has a thickness d 1 , dielectric  40  has a thickness d 2 , and dielectric  48  has a thickness, d 3 . The thicknesses, d 1 , d 2 , and d 3  are optimized to reliably support V GD , maintain frequency response, and minimize C gd  and C gs . Gate length, L G , is tuned for the operational frequency of interest. In  FIG. 4  dielectrics  38  and  40  can be SiO 2  and SiN or the same material, as in  FIG. 3 , and dielectric layer  48  can be SiO 2 . For maximum benefit, the top and bottom dielectrics should be of higher bandgap than the middle dielectric. 
         [0029]    Novel use of this device in a switch-mode amplifier enables reliable operation because it avoids large detrimental forward gate current during the part of the cycle that the transistor is on. 
         [0030]    Published U.S. 2003/0020092A1 discloses metal contacts and insulating gate structures that can be employed in practicing the invention. Thus, while the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true scope and spirit of the invention as defined by the appended claims.