Abstract:
A circuit and method are provided for a power converter to select one from a plurality of current limit signals as a final current limit signal according to the present duty ratio of a power switch for the pulse width modulation of the next cycle, so that the duty ratio of the power switch in the next cycle is prevented from acute variation to eliminate sub-harmonic which otherwise may happen.

Description:
FIELD OF THE INVENTION 
     The present invention is related generally to a power converter and, more particularly, to a circuit and method for sub-harmonic elimination of a power converter. 
     BACKGROUND OF THE INVENTION 
     Taking a typical flyback power converter for example, referring to  FIG. 1 , a rectifier circuit  10  is used to rectify an alternating-current (AC) input voltage VAC, a capacitor Cbulk is connected to the output of the rectifier circuit  10  to stabilize the direct-current (DC) input voltage Vbulk produced by the rectifier circuit  10  to apply to the primary coil Lp of a transformer  12 , a controller  14  provides a control signal GATE to switch a power switch M 1  connected in series with the primary coil Lp to convert the voltage Vbulk into a DC output voltage Vo, a current sense resistor Rcs is connected in series with the power switch M 1  to produce a current sense signal Vcs related to the current Ip of the power switch M 1 , the controller  14  has a pin COMP receiving a feedback signal derived from the DC output voltage Vo for performing negative feedback control, and the controller  14  determines the control signal GATE according to the current sense signal Vcs and a preset current limit signal. Recently, for making products more competitive, lowering costs has become one of the requirements for product development, and therefore selection of components is increasingly strict while the capacitor Cbulk is increasingly downsized. However, for systems of a same rating, when having low input voltage, the system using a smaller capacitor Cbulk will have shorter hold up time for the voltage Vbulk, so the voltage Vbulk at the primary side of the transformer  12  varies significantly, which may cause serious sub-harmonic problem when the system escapes from soft-start or becomes overloaded. Such serious sub-harmonic problem may cause the system, when fully loaded, unable to start-up with a low input voltage or lead to a significant difference between a high input voltage over current protection and a low input voltage over current protection. 
       FIG. 2  illustrates the addressed sub-harmonic problem in the conventional flyback power converter, in which waveform  20  represents an internal clock CLK of the controller  14 , waveform  22  represents a leading-edge blanking signal LEB, waveform  24  represents the control signal GATE, waveform  26  represents the current limit signal, and waveform  28  represents the current sense signal Vcs. The clock CLK serves to determine the cycle of the control signal GATE, the leading-edge blanking signal LEB is used to blank spikes of the current sense signal Vcs when the power switch M 1  turns on, and the control signal GATE turns to low to turn off the power switch M 1  once the current sense signal Vcs becomes higher than the current limit signal. Under a low input voltage, the power switch M 1  has a longer on time, such as from time t 1  to time t 2 , to obtain adequate energy, and thus has a shorter off time since the power switch M 1  has a constant cycle, thereby causing incomplete release of energy. As a result, when the power switch M 1  turns on again, as shown at time t 3 , the initial level of the current sense signal Vcs will be higher than the previous one, so the current sense signal Vcs will sooner become higher than the current limit signal, as shown at time t 4 , and the on time of the power switch M 1  is shortened accordingly. The acute variation of the on time of the power switch M 1  may cause serious sub-harmonic problem to the flyback power converter. 
     SUMMARY OF THE INVENTION 
     An objective of the present invention is to provide a circuit for sub-harmonic elimination of a power converter. 
     Another objective of the present invention is to provide a method for sub-harmonic elimination of a power converter. 
     According to the present invention, a circuit for sub-harmonic elimination of a power converter includes a current limit signal controller to generate a switch signal according to the duty ratio of a power switch, and responsive to the switch signal, a selector selecting a final current limit signal from two current limit signals provided by two current limit signal generators, to limit the maximum value of the current of the power switch. When the duty ratio is smaller than a preset threshold value, the selector selects one of the two current limit signals as the final current limit signal, and when the duty ratio is larger than the preset threshold value, the selector selects the other of the two current limit signals as the final current limit signal. 
     According to the present invention, a method for sub-harmonic elimination of a power converter includes the steps of providing two current limit signals, detecting the duty ratio of the power switch, selecting the first current limit signal as the final current limit signal to limit the maximum value of the current of the power switch when the duty ratio is not larger than a preset threshold value, and selecting the second current limit signal as the final current limit signal when the duty ratio is larger than the preset threshold value. 
     According to the present invention, a circuit for sub-harmonic elimination of a power converter includes a current limit signal controller to generate a switch signal according to the duty ratio of a power switch, and responsive to the switch signal, a selector selecting one from a plurality of current limit signals provided by a plurality of current limit signal generators as a final current limit signal to limit the maximum value of the current of the power switch. When the duty ratio is smaller than a preset threshold value, the selector selects a first one of the plurality of current limit signals as the final current limit signal, and when the duty ratio is larger than the threshold value, the selector selects one from the others of the plurality of current limit signals in an order as the final current limit signal, and if the others of the plurality of current limit signals are all selected once in the order, selects the first current limit signal again as the final current limit signal. 
     According to the present invention, a method for sub-harmonic elimination of a power converter includes the steps of providing a plurality of current limit signals, detecting the duty ratio of a power switch, remaining a first one of the plurality of current limit signals as a final current limit signal to limit the maximum value of the current of the power switch when the duty ratio is not larger than a preset threshold value, and when the duty ratio is larger than the preset threshold value, selecting one from the others of the plurality of current limit signals in an order as the final current limit signal, and if the others of the plurality of current limit signals are all selected once in the order, selecting the first current limit signal again as the final current limit signal. 
     By selecting the final current limit signal according to the duty ratio of the power switch, an appropriate final current limit signal may be selected for the next cycle once the duty ratio becomes excessively large, and thus the duty ratio is prevented from acute variation which otherwise causes sub-harmonic problem. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objectives, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a circuit diagram of a typical flyback power converter; 
         FIG. 2  is a waveform diagram of the flyback power converter shown in  FIG. 1  to illustrate sub-harmonic problem thereof; 
         FIG. 3  is a circuit diagram of a flyback power converter according to the present invention; 
         FIG. 4  is a circuit diagram of an embodiment for the current limit signal controller shown in  FIG. 3 ; 
         FIG. 5  is a waveform diagram of the flyback power converter shown in  FIG. 3  using the current limit signal controller shown in  FIG. 4 ; 
         FIG. 6  is a circuit diagram of another embodiment according to the present invention; and 
         FIG. 7  is a waveform diagram of a flyback power converter using the circuit shown in  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 3 , the same as that of  FIG. 1 , a flyback power converter includes the transformer  12 , the power switch M 1  connected in series with the primary coil Lp of the transformer  12 , the current sense resistor Rcs connected in series with the power switch M 1  to produce the current sense signal Vcs derived from the current Ip of the power switch M 1 , and the controller  14  to receive a feedback signal through the pin COMP for negative feedback control and provide the control signal GATE to switch the power switch M 1  to convert the input DC voltage Vin into the output DC voltage Vo. According to the present invention, however, the controller  14  includes an oscillator  20  for providing a clock CLK and a ramp signal Vosc synchronous to the clock CLK, an SR flip-flop  22  for triggering the control signal GATE responsive to the clock CLK, a comparator  24  for generating a signal S 1  to reset the SR flip-flop  22  according to the current sense signal Vcs and a final current limit signal Vclf, and a sub-harmonic eliminate circuit  26  for detecting the duty ratio of the control signal GATE and changing the final current limit signal Vclf according to the duty ratio of the control signal GATE. When the duty ratio of the control signal GATE is larger than a preset threshold value, the sub-harmonic eliminate circuit  26  changes the final current limit signal Vclf to prevent the duty ratio of the control signal GATE from acutely changing at the next cycle, thereby eliminating sub-harmonic which otherwise may happen. 
     The sub-harmonic eliminate circuit  26  includes a current limit signal controller  28 , a selector  30  and two current limit signal generators  32  and  34  to provide a ramp current limit signal Vcl 1  and a constant value current limit signal Vcl 2  for the selector  30  to select therebetween under control of the current limit signal controller  28 . Using a current limit signal generator to generate a ramp current limit signal is a prior art, for example, see U.S. Pat. No. 6,674,656, so the detailed explanation thereof is eliminated herein. The selector  30  includes a switch SW 1  connected between the current limit signal generator  32  and the output terminal Vclf of the sub-harmonic eliminate circuit  26 , and a switch SW 2  connected between the current limit signal generator  34  and the output terminal Vclf of the sub-harmonic eliminate circuit  26 . The current limit signal controller  28  detects the duty ratio of the control signal GATE to generate a switch signal CCL for controlling the switches SW 1  and SW 2 , and thereby selecting the ramp current limit signal Vcl 1  or the constant value current limit signal Vcl 2  as the final current limit signal Vclf. 
       FIG. 4  is a circuit diagram of an embodiment for the current limit signal controller  28 , which includes a comparator  40  for comparing the ramp signal Vosc to a reference voltage Vref to generate a signal DX that has a constant duty ratio, an inverter  42  for inverting the signal DX to generate a signal DX′, a D-type flip-flop  44  for generating a signal S 2  according to the control signal GATE applied to its data input terminal D and the signal DX′ applied to its clock terminal clk, and a D-type flip-flop  46  for generating the switch signal CCL according to the signal S 2  applied to its data input terminal D and the control signal GATE applied to its clock terminal clk. 
       FIG. 5  is a waveform diagram of the controller  14  using the circuit of  FIG. 4  as the current limit signal controller  28 , in which waveform  50  represents the final current limit signal Vclf. The ramp current limit signal Vcl 1  is preset as the final current limit signal Vclf under normal operation. Referring to  FIGS. 3-5 , during a cycle T 1 , the duty ratio of the control signal GATE is larger than a preset threshold value, so when the signal DX turns to low, the control signal GATE still remains at high, as shown at time t 5  of  FIG. 5 , and thus the D-type flip-flop  44  will remain the signal S 2  at high. Then, during the next cycle T 2 , as shown at time t 6  of  FIG. 5 , since the signal S 2  is high when the control signal GATE turns to high, the D-type flip-flop  46  will pull the switch signal CCL to high and thus signal the selector  30  to select the current limit signal Vcl 2  as the final current limit signal Vclf, as shown by waveform  50 , which will prevent the on time of the power switch M 1  from changing acutely, thereby eliminating sub-harmonic which otherwise may happen. Since the duty ratio of the control signal GATE in the cycle T 2  is no longer larger than the preset threshold value, when the signal DX turns to low, as shown at time t 7 , the signal S 2  will also turn to low, and thus, during the next cycle T 3 , when the control signal GATE turns to high, as shown at time t 8 , the switch signal CCL will turn to low and thus signal the selector  30  to select the current limit signal Vcl 1  again as the final current limit signal Vclf. On the contrary, during the cycle T 2 , if the duty ratio of the control signal GATE remains larger than the preset threshold value, the selector  30  will remain the current limit signal Vcl 2  as the final current limit signal Vclf. In other embodiments, the current limit signal Vcl 1  may not be limited to have a ramp waveform, and the current limit signal Vcl 2  may have another waveform instead of a constant value. 
     Alternatively, when detecting the duty ratio of the control signal GATE larger than the preset threshold value during the cycle T 1 , the sub-harmonic eliminate circuit  26  of  FIG. 3  may select the current limit signal Vcl 2  as the final current limit signal Vclf for the next cycle T 2 , and afterward, no matter whether the duty ratio of the control signal GATE is larger than the preset threshold value during the next cycle T 2 , the sub-harmonic eliminate circuit  26  will select the current limit signal Vcl 1  again as the final current limit signal Vclf for the next cycle T 3 . 
       FIG. 6  is a circuit diagram of another embodiment for the sub-harmonic eliminate circuit  26  of  FIG. 3 . In addition to the current limit signal controller  28 , the selector  30  and the current limit signal generators  32  and  34  similar to those in the circuit of  FIG. 3 , there is further a current limit signal generator  36  for providing a constant value current limit signal Vcl 3 . Besides the switches SW 1  and SW 2 , the selector  30  further has a switch SW 3  connected between the current limit signal generator  36  and the output terminal Vclf of the sub-harmonic eliminate circuit  26 .  FIG. 7  is a waveform diagram of the circuit shown in  FIG. 6 , in which waveform  52  represents the final current limit signal Vclf. Referring to  FIGS. 6 and 7 , the current limit signal Vcl 1  is preset as the final current limit signal Vclf under normal operation, and when the current limit signal controller  28  detects the duty ratio of the control signal GATE not larger than a preset threshold value, it will remain the final current limit signal Vclf=Vcl 1 . If the current limit signal controller  28  detects the duty ratio of the control signal GATE larger than the preset threshold value during the cycle T 1 , the current limit signal controller  28  will signal the selector  30  by the switch signal CCL to select the current limit signal Vcl 2  as the final current limit signal Vclf for the next cycle T 2 , as shown by waveform  52 . Then, no matter whether the control signal GATE is larger than the preset threshold value in the cycle T 2 , the selector  30  always selects the current limit signal Vcl 3  as the final current limit signal Vclf for the next cycle T 3 . Similarly, no matter whether the control signal GATE is larger than the preset threshold value in the cycle T 3 , the selector  30  will select the current limit signal Vcl 1  again as the final current limit signal Vclf for the next cycle. In other embodiments, the current limit signal Vcl 1  may not be limited to have a ramp waveform, and the other current limit signals Vcl 2  and Vcl 3  may have other waveforms instead of constant values. 
     While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.