Abstract:
A more robust mechanical connection is provided between a semiconductor device and the device package by adding one or more bumps to the gate connection without adding more gate pad area. A nonconductive layer covers the area around the gate pad and extends over the source area. One or more bumps fabricated on the nonconductive layer provide mechanical strength and support to the gate pad connection. The added bumps are not electrically connected to either the gate or the source. The package connections must be altered, both to fit the added bumps on the control gate, and to connect with fewer bumps on the source.

Description:
FIELD OF INVENTION 
     This invention relates to semiconductor fabrication, and more specifically to power MOSFET contact fabrication. 
     DEFINITIONS 
     UBM: under-bump metal, the conductive metal used to connect a source or gate contact to an external circuit via a surface solder bump. 
     DISCUSSION OF PRIOR ART 
     Conductive bumps provide an interconnect between an active semiconductor device and a package which then is placed into an application. Discrete Field Effect Transistors (FETs) usually have at least 3 connections: (1) a control gate; (2) a drain; and (3) a source. The drain is usually the back side of a die and the entire back side of the die is mechanically and electrically connected to the package. The source is usually on the front side of the die and has several bumps, which provide mechanical and electrical contact to the package. The control gate traditionally has only a single bump connected to the contact of the package on the front side of the die. The use of a single bump for the gate connection creates a significant probability of gate connection failure due to mechanical stress. This contrasts with a lower probability of such failure for a source connection, which has multiple bumps that continue to operate if any one of them fails. To put more bumps on a gate pad would reduce the likelihood of gate connection failure, but it would require a larger gate pad and therefore more area for the total die, increasing the cost of manufacturing the device. 
     See FIG. 1, showing a cross section of the gate area of a prior art device. Gate bump  10  is fabricated directly above gate metallization  50 , gate contact  51 , and under bump metal  52  and  53 , to make an external contact between gate metallization  50  of wafer  7  and package control gate connection  5 , via connection point  54 . Source bumps  11 ,  12  are fabricated directly above source metallization  60 , source contact  61 , and under bump metal  62  and  63 , to make an external contact between source metallization  60  of wafer  7  and package source connection  6 , via connection points  64 . An insulating layer  40  provides electrical isolation between gate and source circuitry. A second insulating layer  90  provides added isolation and external protection. 
     FIG. 2 shows the prior art approach in plan view. To simplify FIG. 2 without omitting essentials of the invention, the SiO or SiN passivating layers over gate and source metallizations are not shown in the figure. The single package control gate connection  5  connects at contact point  54  over bump  10 , with no additional mechanical support for the gate connection. 
     The single gate bump  10  represents a single point of failure for the entire device. Gate bump  10  is the sole point of contact for package control gate connection  5 , at connection point  54 . If mechanical stress causes delamination of under bump metal  52  or  53 , the gate connection will fail. Some means of reducing the mechanical stresses on the gate bump connection is needed. 
     SUMMARY 
     The invention provides a more robust mechanical connection between a semiconductor device and the device package by adding one or more bumps to the gate connection without adding more gate pad area. The invention first provides a nonconductive layer covering the area around the gate pad and extending over the source area. The invention adds one or more bumps on the nonconductive layer to provide mechanical strength and support to the gate pad connection. The added bumps are not electrically connected to either the gate or the source. The package connections must be altered, both to fit the added bumps on the control gate, and to connect with fewer bumps on the source. 
    
    
     DESCRIPTION OF DRAWINGS 
     FIG. 1 shows a cross-sectional view of a device manufactured according to the prior art. 
     FIG. 2 shows a plan view of the prior art approach to gate bump connection design. 
     FIG. 3 a  shows a cross-sectional view of a device manufactured according to a first embodiment of the invention. 
     FIG. 3 b  shows a cross-sectional view of a device manufactured according to a second embodiment of the invention. 
     FIG. 4 shows a plan view of the invention&#39;s approach to supporting gate bump connection design. 
     FIG. 5 shows a plan view of an alternate embodiment of the invention&#39;s approach to supporting gate bump connection design. 
     FIG. 6 shows a cutaway view of the invention&#39;s approach to supporting gate bump connection design. 
     FIGS. 7 and 8 show the initial fabrication steps for the invention. 
     FIGS. 9 a ,  10   a ,  11   a ,  12   a ,  13   a ,  14   a ,  15   a , and  16   a  show further fabrication steps for a first embodiment of the invention. 
     FIGS. 9 b ,  10   b ,  11   b ,  12   b ,  13   b ,  14   b ,  15   b , and  16   b  show further fabrication steps for a second embodiment of the invention. 
    
    
     For convenience, a legend for the figures is shown on the drawing sheet with FIG.  1 . To simplify FIGS. 2,  4 , and  5 , the SiO or SiN passivating layers over gate and source metallizations are not shown in these figures. 
     DETAILED DESCRIPTION OF INVENTION 
     This invention improves the strength and durability of the mechanical connection between a semiconductor device and the device package by adding contact bumps to the gate connection without adding more gate pad area to the device. This is accomplished by providing a nonconductive layer covering the area around the gate pad and extending the nonconductive layer over the source area. The invention adds one or more bumps on this nonconductive layer to provide mechanical strength to the gate pad connection. The added bumps are not electrically connected to the gate or the source. 
     See FIG. 3 a , showing a cross section of the gate contact area. Gate bump  10  is fabricated directly above gate metallization  50 , gate contact  51 , and under bump metal  52 ,  53 , to make an external contact between gate metallization  50  of wafer  7  and package control gate connection  5 , via gate connection point  54 . In contrast to the prior art device, however, the invention fabricates one or more unconnected support bumps  13 ,  14 , with under bump metal  72 ,  73  over insulating layer  40 , source passivation layer  65 , and source metallization  60 . Under bump metal  72  anchors to insulating layer  40 . Insulating layer  40  and source passivation layer  65  isolate support bumps  13 ,  14  and under bump metal  72 ,  73  from source metallization  60  and the source circuitry. Support bumps  13 ,  14  have no electrical connection either to gate metallization  50  or to source metallization  60 . Support bumps  13 ,  14  provide mechanical support for package control gate connection  5  at contact points  74 , partially relieving gate connection point  54  of excess pressure during package assembly and later use. Insulating layer  40  provides electrical isolation between gate and source circuitry. 
     In a second embodiment, shown in FIG. 3 b , insulating layer  40  is fabricated via its mask layout with openings through which under bump metal  72  is partially or completely anchored to source passivation layer  65 . Since bumps adhere well either to an insulating layer such as BCB or a passivating layer such as oxinitride, the choice of support bump embodiments may be based on the results of bump shear tests. 
     FIG. 4 shows the invention&#39;s approach in plan view. To simplify FIG. 4 without omitting essentials of the invention, the SiO or SiN passivating layers over gate and source metallizations are not shown. Package control gate connection  5  connects at contact point  54  to bump  10 , but here support bumps  13 ,  14  supply mechanical support for the control gate connection at contact points  74 . Support bumps  13 ,  14  do not make electrical contact with either the gate or the source circuitry. In an alternate embodiment, shown in FIG. 5, the invention&#39;s approach uses a set of support bumps  13 ,  14 ,  15  closely surrounding gate bump  10  to provide mechanical support at contact points  74  for the package control gate connection. Support bumps  13 ,  14 ,  15  make no electrical contact with either the gate or the source circuitry. 
     FIG. 6 shows in cutaway detail the difference between the layers underlying gate bump  10  and a neighboring support bump  13  used for mechanical support for package control gate connection  5 . Bump  10 &#39;s electrical contact is made through metallization layer  50 , gate contact  51 , under bump metal  52 ,  53 , and package control gate connection contact point  54 . Support bump  13  makes no electrical contact. Insulating layer  40  isolates support bump  13  and under bump metal  72 ,  73  from source metallization  60 . Through contact point  74 , support bump  13  provides mechanical support for package control gate connection  5 . 
     The invention&#39;s fabrication process is as follows. See FIG.  7 . Gate contact Al metallization  50  and source contact Al metallization  60  are layered on semiconductor wafer  7 . FIG. 7 shows a silicon oxide or silicon nitride passivation  55  layered over gate metal to provide physical protection, with an opening  56  fabricated in passivation layer  55  to expose gate contact  51 . Silicon oxide or silicon nitride passivation layer  65  is layered over source metallization  60  to provide protection for the metal layer. Source contacts  61  are exposed by openings  66  in source passivation layer  65 . 
     A BCB layer  40  is coated and baked on the wafer as shown in FIG.  8 . BCB layer  40  is exposed and developed to define the exposed gate contact  51  and exposed source contacts  61  as shown in FIGS. 9 a  and  9   b . See FIG. 9 a . In a first embodiment, in area  79 , BCB layer  40  is left intact with source passivation layer  65  to act as support and insulation for an eventual gate support bump. In FIG. 9 b , showing a second embodiment, BCB layer  40  is removed to expose gate contact  51  and source contacts  61 , and in area  79  to expose only source passivation layer  65 . In the second embodiment, source passivation layer  65  acts directly as anchor and insulation for an eventual gate support bump. 
     In the remaining figures showing the fabrication process, FIGS. 9 a ,  10   a ,  11   a ,  12   a ,  13   a ,  14   a ,  15   a , and  16   a  show the process for the first embodiment, and FIGS. 9 b ,  10   b ,  11   b ,  12   b ,  13   b ,  14   b ,  15   b , and  16   b  show the process for the second embodiment. 
     See FIG. 10 a . An under bump metal  52 , such as Ti followed by Cu, is then sputtered onto BCB layer  40 , gate contact  51  and source contacts  61 . As shown in FIG. 10 b , the second embodiment&#39;s opening in BCB layer  40  in area  79  brings under bump metal  52  into contact with source passivation layer  65 . A thick photoresist coating  100  is added, UV-exposed and developed to expose UBM areas  59 ,  69 ,  79  (FIGS. 11 a  and  11   b ) where Cu  53  is to be plated onto exposed UBM  52 . Cu  53 ,  63 ,  73  is plated onto exposed under bump metal  52 , as shown in FIGS. 12 a  and  12   b , to ensure retention of bulk copper interconnect after the soldering process, since part of the copper is consumed with the formation of intermetallics with adjacent metal layers. 
     Gate solder bump  101 , gate support solder bumps  111 , and source solder bumps  121  are plated onto Cu  53 ,  73 , and  63  respectively (FIGS. 13 a  and  13   b ), with photoresist  100  supporting the edges of the bumps around Cu  53 ,  73 , and  63 . Photoresist  100  is stripped (FIGS. 14 a  and  14   b ) to expose UBM  52 . UBM  52  is etched to define final UBM  52 ,  72 ,  62  (FIGS. 15 a  and  15   b ) and plated solder bumps  101 ,  111 ,  121  are reflowed (FIGS. 16 a  and  16   b ) to form final solder bumps. 
     For all embodiments, the device package connections must be altered to accommodate the extra bumps on the control gate and the smaller number of bumps used for the source. 
     Conclusion, Ramifications, and Scope of Invention 
     From the above descriptions, figures and narratives, the invention&#39;s advantages in providing mechanically reliable, durable, and economical MOSFET gate contacts should be clear. 
     Although the description, operation and illustrative material above contain many specificities, these specificities should not be construed as limiting the scope of the invention but as merely providing illustrations and examples of some of the preferred embodiments of this invention. 
     Thus the scope of the invention should be determined by the appended claims and their legal equivalents, rather than by the examples given above.