Abstract:
A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This is a divisional application of U.S. application Ser. No. 13/213211, filed on Aug. 19, 2011, which is currently pending. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a fabricating method of a shallow trench isolation structure, and more particularly to a fabricating method of a shallow trench isolation structure in the manufacture of a semiconductor device. 
     BACKGROUND OF THE INVENTION 
     Nowadays, in the mainstream of integrated circuit production, a low voltage logic circuit and a high voltage semiconductor device are implemented on the same integrated circuit chip. For providing effective isolation between adjacent electronic components, in the low voltage logic circuit and a high voltage semiconductor device, an isolation structure is usually formed in the integrated circuit chip to separate adjacent electronic components from each other. As known, a shallow trench isolation (STI) structure is one of the most popular isolation structures. Moreover, the shallow trench isolation structures of the low voltage logic circuit and the high voltage semiconductor device are simultaneously produced in the same fabricating process. 
     As the device size of the low voltage logic circuit is gradually developed toward miniaturization because of the process progress, the width and the depth of the shallow trench isolation structure are reduced. If the dimension of the shallow trench isolation structure of the high voltage semiconductor device is identical to the dimension of the shallow trench isolation structure of the low voltage logic circuit, the isolation efficacy of the high voltage semiconductor device is unsatisfied. Therefore, there is a need of providing an improved fabricating method of a shallow trench isolation structure. 
     SUMMARY OF THE INVENTION 
     Therefore, the object of the present invention is to provide a fabricating method of a shallow trench isolation structure in order to achieve effective isolation. 
     In accordance with an aspect, the present invention provides a fabricating method of a shallow trench isolation structure. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure. 
     In an embodiment, a low voltage device area is further defined in the substrate, and a second shallow trench is further formed in the low voltage device area by the second etching process. The first shallow trench is deeper than the second shallow trench. 
     In an embodiment, an inclination angle of a sidewall of the preliminary shallow trench is from 105 to 135 degrees, so that the first shallow trench has a shoulder part with a gentle slope. 
     In an embodiment, after the first shallow trench isolation structure is formed, the fabricating method further includes the following steps. A pre-clean process is performed to treat the shallow trench isolation structure, so that a top surface of the shallow trench isolation structure is shrunk to a location below the shoulder part. Then, a high voltage gate dielectric layer is formed on the shallow trench isolation structure and a surface of the substrate. 
     In an embodiment, after the preliminary shallow trench is formed, the fabricating method further includes a step of forming a spacer on a sidewall of the preliminary shallow trench, wherein the spacer is made of the same material as the dielectric material. 
     In an embodiment, after the preliminary shallow trench is formed and before the second etching process is done, the fabricating method further includes a step of performing an ion implantation process to dope the high voltage device area of the substrate with a dopant, so that a high voltage well region is formed in the high voltage device area. 
     In an embodiment, the step of filling the dielectric material in the first shallow trench includes sub-steps of performing a high density plasma chemical vapor deposition process to deposit the dielectric material, and performing a chemical mechanical polishing process to flatten the dielectric material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
         FIGS. 1A-1J  are schematic cross-sectional views illustrating a process of fabricating a shallow trench isolation (STI) structure according to an embodiment of the present invention; and 
         FIG. 2  is a schematic cross-sectional view illustrating a symmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention; and 
         FIG. 3  is a schematic cross-sectional view illustrating an asymmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
       FIGS. 1A-1J  are schematic cross-sectional views illustrating a process of fabricating a shallow trench isolation (STI) structure according to an embodiment of the present invention. 
     Firstly, as shown in  FIG. 1A , a silicon substrate  1  is provided. 
     A pad oxide layer  10  is formed on a surface of the silicon substrate  1 . In addition, the silicon substrate  1  is divided into two areas, i.e. a high voltage device area  11  and a low voltage device area  12 . 
     Then, a zero-etch process is performed by using a photolithography and etching process to define an alignment mark (not shown) on the silicon substrate  1 . Especially, for performing the zero-etch process, a pattern for defining a shallow trench isolation structure of the high voltage device area  11  should be previously created in the photo mask. After the zero-etch process is performed, a preliminary shallow trench  110  is formed in the high voltage device area  11  (see  FIG. 1B ). The preliminary shallow trench  110  has a first depth. Since the device density of the high voltage device area  11  is relatively lower, there is a sufficient space for providing a tapered preliminary shallow trench  110 . That is, the sidewall of the preliminary shallow trench  110  is not upright. By adjusting the etching conditions, the sidewall of the preliminary shallow trench  110  has a gentle slope. In an embodiment, the sidewall of the preliminary shallow trench  110  has an inclination angle in a range from 105 to 135 degrees. 
     Then, as shown in  FIG. 1C , an ion implantation process (as is indicated by the arrow) is performed to dope the high voltage device area  11  with a dopant. Consequently, a high voltage well region  119  is formed in the high voltage device area  11 . 
     Then, as shown in  FIG. 1D , a spacer  111  is formed on the sidewall of the preliminary shallow trench  110 . For example, the spacer  111  is made of silicon oxide. In this embodiment, an anisotropic etching process is performed to remove the excess silicon oxide and the pad oxide layer  10  while remaining the spacer  111 . By the spacer  111 , the possibility of forming a residual (e.g. silicon nitride) on the sidewall of the preliminary shallow trench  110  in the subsequent process will be minimized. In other words, the spacer  111  is effective to improve the profile of the isolation structure in the subsequent process. 
     Then, as shown in  FIG. 1E , a pad oxide layer  13  and a silicon nitride layer  14  are sequentially formed on the surface of the silicon substrate  1 . 
     Then, a shallow trench etching process is performed to simultaneously form a plurality of first shallow trenches  15  and a plurality of second shallow trenches  16  in the high voltage device area  11  and the low voltage device area  12 , respectively. The depth of the first shallow trench  15  in the high voltage device area  11  is greater than the depth of the second shallow trench  16  in the low voltage device area  12  (see  FIG. 1F ). Since the preliminary shallow trench  110  formed by the zero-etch process contributes to an upper portion of the first shallow trench  15 , the first shallow trench  15  with the upper portion and a lower portion becomes deeper than the second shallow trench  16 . Under this circumstance, the isolation efficacy is enhanced. In other words, the depth of the first shallow trench  15  can be adjusted through the preliminary shallow trench  110 . Since the method of the present invention is capable of adjusting the depth of the shallow trench in the high voltage device area, the conventional problem will be obviated. 
     However, a defect is possibly formed on the silicon substrate  1  after the shallow trench etching process is performed. For repairing the defect, the silicon substrate having the shallow trenches may be treated by a high temperature furnace process (at about 100° C.). Consequently, a silicon oxide repair linear layer (not shown) is formed on the sidewalls of the shallow trenches for repairing the defect and rounding the shape corners. Under this circumstance, the electrical isolation efficacy is enhanced. 
     Then, a high density plasma chemical vapor deposition (HDP-CVD) process is performed, and thus a silicon oxide layer  17  is filled within the first shallow trenches  15  and the second shallow trenches  16  and formed on the silicon nitride layer  14 . Then, a chemical mechanical polishing process is performed to remove the silicon oxide layer  17  overlying the silicon nitride layer  14 , the top surface of the silicon oxide layer  17  is substantially at the same level as the topside of the silicon nitride layer  14  (see  FIG. 1G ). 
     Then, as shown in  FIG. 1H , an etch-back process and a nitride oxide removing process are performed to remove the silicon nitride layer  14 . Consequently, a plurality of shallow trench isolation structures  180  and  181  made of silicon oxide are formed and partially exposed. The shallow trench isolation structures  180  are located at the high voltage device area  11 . The shallow trench isolation structures  181  are located at the low voltage device area  12 . The shallow trench isolation structure  180  is deeper than the shallow trench isolation structure  181 . Moreover, the shallow trench isolation structure  180  has a shoulder part  1801  with a gentle slope. 
     Then, as shown in  FIG. 1I , another ion implantation process is performed to produce other parts of the high voltage device, for example the high voltage field (HV field) region (see  FIG. 2 ). 
     Then, as shown in  FIG. 1J , one or more pre-clean processes are performed to treat the shallow trench isolation structure  180 . Inevitably, the shallow trench isolation structure  180  is shrunk from the top surface to a location at a level near the shoulder part  1801 . Then, a thermal oxidation process is performed, and thus a high voltage gate dielectric layer  191  is grown on the surface of the substrate  1  and the shallow trench isolation structure  180 . Then, a high voltage gate conductor layer  192  is formed on the top surfaces of the high voltage gate dielectric layer  191  and the shallow trench isolation structure  180 . In this embodiment, the high voltage gate dielectric layer  191  is produced by a high temperature furnace oxidation process. Moreover, the high voltage gate dielectric layer  191  is made of the same material as the shallow trench isolation structure  180 . For example, the high voltage gate dielectric layer  191  is made of silicon oxide. Since the shallow trench isolation structure  180  has a shoulder part  1801  with a gentle slope, the thickness of the high voltage gate dielectric layer  191  over the shallow trench isolation structure  180  is distributed more uniformly. For example, the thickness d 1  of the high voltage gate dielectric layer  191  overlying the channel region  199  is about 950 angstroms, and the thickness d 2  of the high voltage gate dielectric layer  191  at the edge of the channel region  199  is about 700 angstroms. Since the ratio of d 2  to d 1  is maintained at a ratio greater than 0.7, the high voltage device area has enhanced insulation efficacy and is suitable to be operated in the high voltage condition. 
       FIG. 2  is a schematic cross-sectional view illustrating a symmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention. Take NMOS as an example. As shown in  FIG. 2 , a high voltage P-well region  20  is formed in a substrate  2 . A high voltage N-field region  24  and a high voltage P-field region  25  are formed in the high voltage P-well region  20 . A heavily P-doped region  220  and a heavily N-doped region  210  are formed served as a body contact region and a source/drain region, respectively. Moreover, the shallow trench isolation structures  200 ,  201  and  202  are produced by the fabricating method of the present invention. Consequently, the metal-oxide-semiconductor field-effect transistor has enhanced insulation efficacy and is suitable to be operated in the high voltage condition. Moreover, since the thickness distribution of the high voltage gate dielectric layer  21  is more uniform, if only the single-side shoulder parts  2000  and  2010  of the shallow trench isolation structures  200  and  201  in the channel region  23  under the high voltage gate dielectric layer  21  and the high voltage gate conductor layer  22  are created, the above benefits are also achievable. Of course, if all of the shallow trench isolation structures have the shoulder parts, the benefits will become more evident. 
       FIG. 3  is a schematic cross-sectional view illustrating an asymmetric metal-oxide-semiconductor field-effect transistor with the shallow trench isolation structure produced by the method of the present invention. In comparison with the symmetric metal-oxide-semiconductor field-effect transistor of  FIG. 2 , the shallow trench isolation structures  201 ,  202 , the high voltage N-field region  24 , the high voltage P-field region  25  and the heavily P-doped region  220  are not included in a side of the asymmetric metal-oxide-semiconductor field-effect transistor of  FIG. 3 . That is, only the heavily N-doped region  210  serving as the source/drain contact region and the outermost shallow trench isolation structure  30  are retained. 
     While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.