Abstract:
Input/output (I/O) line driving circuits are provided. The circuit includes a first I/O line driver and a second I/O line driver. The first I/O line driver receives a first input signal in response to an enable signal to generate a first control signal and drives a first I/O line in response to a second control signal. The second I/O line driver receives a second input signal in response to the enable signal to generate the second control signal and drives a second I/O line in response to the first control signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present application claims priority under 35 U.S.C 119(a) to Korean Application No. 10-2013-0041195, filed on Apr. 15, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     Simultaneous switching noises (SSN) are typically generated due to inductive components of conductive lines (e.g., interconnection lines) included in electronic circuits when the electronic circuits operate with high frequency signals. These simultaneous switching noises are subject to Faraday&#39;s law of induction. According to Faraday&#39;s law of induction, a counter electromotive force (e.g., a voltage drop) may be generated between both ends of a conductive line (e.g., a conductive coil) when an alternating current (e.g., an instantaneous current) flows through the conductive line to change a magnetic field around the conductive line. In such a case, the counter electromotive force may increase as the amount of the instantaneous current, the variation rate of the instantaneous current, or the inductance of the conductive line increases. The counter electromotive force generated by the instantaneous current may cause a voltage fluctuation of a power line and/or a ground line of an electronic circuit including the conductive line, and the voltage fluctuation may generate noises which are referred to as the simultaneous switching noises. The counter electromotive force (Vnoise) may be expressed by the following equation.
 
 V noise=− L ( di/dt )
 
     where, “L” denotes an inductance value of the conductive line. 
     Accordingly, if a number of circuit elements are simultaneously switched on/off, instantaneous changes in current across the power line and the ground line may occur. As a result, inductive voltage drops may occur to increase the simultaneous switching noises in the electronic circuits, for example, semiconductor systems. The simultaneous switching noises may cause signal delays to degrade the reliability of the semiconductor systems. 
     Each of the semiconductor systems may include various internal circuits, and each of the internal circuits may be configured to include a number of MOS transistors. The MOS transistors may be used as switches to operate the internal circuits. Recently, as the semiconductor systems become more highly integrated, a number of signals and data may be simultaneously transmitted through a number of signal lines or a number of input/output (I/O) lines. If a number of signals and data are simultaneously transmitted, a number of MOS transistors may also be simultaneously switched on/off to cause a number of simultaneous switching noises. 
     SUMMARY 
     Various embodiments are directed to I/O line driving circuits. 
     According to an embodiment, an I/O line driving circuit includes a first I/O line driver and a second I/O line driver. The first I/O line driver receives a first input signal in response to an enable signal to generate a first control signal and drives a first I/O line in response to a second control signal. The second I/O line driver receives a second input signal in response to the enable signal to generate the second control signal and drives a second I/O line in response to the first control signal. 
     According to an embodiment, an I/O line driving circuit includes a first I/O line driver configured to drive a first I/O line and a second I/O line driver configured to drive a second I/O line adjacent to the first I/O line. The first I/O line driver buffers a first input signal in response to an enable signal to generate a first pull-up signal, uses the first pull-up signal to generates a first control signal, and includes a first pull-up element and a second pull-up element that pull up a level of the first I/O line in response to the first pull-up signal. An operation that the second pull-up element pulls up the level of the first I/O line is controlled by a second control signal generated from a second input signal which is applied to the second I/O line driver to drive the second I/O line. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments concept will become more apparent in view of the attached drawings and accompanying detailed description, in which: 
         FIG. 1  is a block diagram illustrating a input/output line driving circuit according to an embodiment; 
         FIG. 2  is a circuit diagram illustrating an example of a first input/output line driver included in the input/output line driving circuit shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram illustrating an example of a second input/output line driver included in the input/output line driving circuit shown in  FIG. 1 ; 
         FIGS. 4A to 4D  are tables illustrating an operation of the first and second input/output line drivers shown in  FIGS. 2 and 3 ; 
         FIG. 5  is a circuit diagram illustrating another example of a first input/output line driver included in the input/output line driving circuit shown in  FIG. 1 ; 
         FIG. 6  is a circuit diagram illustrating another example of a second input/output line driver included in the input/output line driving circuit shown in  FIG. 1 ; and 
         FIGS. 7A to 7D  are tables illustrating an operation of the first and second input/output line drivers shown in  FIGS. 5 and 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Example embodiments of the inventive concept will be described hereinafter with reference to the accompanying drawings. However, the example embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the inventive concept. 
     Referring to  FIG. 1 , an input/output (hereinafter referred to as “I/O”) line driver circuit according to an embodiment may be configured to include a first I/O line driver GIO_DRV 1  and a second I/O line driver GIO_DRV 2 . The first I/O line driver GIO_DRV 1  may generate a first control signal CNT 1  in response to a first input signal IN 1  and an enable signal EN. In an embodiment, the first I/O line driver GIO_DRV 1  may receive the first input signal IN 1  in response to the enable signal EN to generate the first control signal CNT 1 . The first I/O line driver GIO_DRV 1  may also drive a first I/O line GIO 1  in response to a second control signal CNT 2 . The second I/O line driver GIO_DRV 2  may generate the second control signal CNT 2  in response to a second input signal IN 2  and the enable signal EN. In an embodiment, the second I/O line driver GIO_DRV 2  may receive the second input signal IN 2  in response to the enable signal EN to generate the second control signal CNT 2 . The second I/O line driver GIO_DRV 2  may also drive a second I/O line GIO 2  in response to the first control signal CNT 1 . The first and second control signals CNT 1  and CNT 2  may control pull-up drive operations of the first and second I/O lines GIO 1  and GIO 2  when the levels of the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up. Further, the first and second control signals CNT 1  and CNT 2  may control pull-down drive operations of the first and second I/O lines GIO 1  and GIO 2  when the levels of the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled down. 
     Referring to  FIG. 2 , the first I/O line driver GIO_DRV 1  may be configured to include a first buffer ND 11 , a first inversion buffer IV 11 , a first buffer unit  11 , a first pull-up element P 11 , a second pull-up element P 12 , a first pull-up drive control element P 13 , a first pull-down element N 11 , a second pull-down element N 12  and a first pull-down drive control element N 13 . 
     The first buffer ND 11  may generate a first pull-up signal PU 1  in response to the first input signal IN 1  when an enable signal EN applied to the first buffer ND 11  is enabled to have a logic “high” level. For example, the first buffer ND 11  may generate the first pull-up signal PU 1  by inverting the first input signal IN 1 . The first inversion buffer IV 11  may generate the first control signal CNT 1  in response to the first pull-up signal PU 1 . For example, the first inversion buffer IV 11  may generate the first control signal CNT 1  by inverting the first pull-up signal PU 1 . The first buffer unit  11  may generate a first pull-down signal PD 1  in response to a first inverted input signal IN 1 B when the enable signal EN applied to the first buffer unit  11  is enabled to have a logic “high” level. For example, the first buffer unit  11  may generate the first pull-down signal PD 1  by buffering the first inverted input signal IN 1 B. The first inverted input signal IN 1 B may be a complementary signal of the first input signal IN 1 . In an embodiment, the first pull-up element P 11  may be a PMOS transistor. If the first pull-up element P 11  is a PMOS transistor, a source electrode of the first pull-up element P 11  may be electrically connected to a power supply terminal VDD and a drain electrode of the first pull-up element P 11  may be electrically connected to the first I/O line GIO 1 . In such a case, if the first pull-up signal PU 1  enabled to have, for example, a logic “low” level is applied to a gate electrode of the first pull-up element P 11 , the first pull-up element P 11  may be turned on to pull up a level of the first I/O line GIO 1 . In an embodiment, the second pull-up element P 12  may be a PMOS transistor. If the second pull-up element P 12  is a PMOS transistor, a source electrode of the second pull-up element P 12  may be electrically connected to the power supply terminal VDD and a drain electrode of the second pull-up element P 12  may be electrically connected to a node ND 11 . In such a case, if the first pull-up signal PU 1  enabled to have, for example, a logic “low” level is applied to a gate electrode of the second pull-up element P 12 , the second pull-up element P 12  may be turned on to pull up a level of the node ND 11 . In an embodiment, the first pull-up drive control element P 13  may be a PMOS transistor. If the first pull-up drive control element P 13  is a PMOS transistor, a source electrode of the first pull-up drive control element P 13  may be electrically connected to the node ND 11  and a drain electrode of the first pull-up drive control element P 13  may be electrically connected to the first I/O line GIO 1 . In such a case, the first pull-up drive control element P 13  may control a pull-up drive operation of the second pull-up element P 12  in response to the second control signal CNT 2 . For example, when the second control signal CNT 2 , having a logic “low” level, is applied to a gate electrode of the first pull-up drive control element P 13  to turn on the first pull-up drive control element P 13  and the first pull-up signal PU 1  is enabled to have, for example, a logic “low” level, the second pull-up element P 12  may be turned on to pull up a level of the first I/O line GIO 1 . 
     The first pull-down element N 11  may be an NMOS transistor. In such a case, a drain electrode of the first pull-down element N 11  may be electrically connected to the first I/O line GIO 1  and a source electrode of the first pull-down element N 11  may be electrically connected to a ground terminal VSS. Thus, when the first pull-down signal PD 1  enabled to have, for example, a logic “high” level is applied to a gate electrode of the first pull-down element N 11 , the first pull-down element N 11  may be turned on to pull down a level of the first I/O line GIO 1 . In an embodiment, the second pull-down element N 12  may be an NMOS transistor. If the second pull-down element N 12  is an NMOS transistor, a source electrode of the second pull-down element N 12  may be electrically connected to the ground terminal VSS and a drain electrode of the second pull-down element N 12  may be electrically connected to a node ND 12 . In such a case, if the first pull-down signal PD 1  enabled to have, for example, a logic “high” level is applied to a gate electrode of the second pull-down element N 12 , the second pull-down element N 12  may be turned on to pull down a level of the node ND 12 . In an embodiment, the first pull-down drive control element N 13  may be an NMOS transistor. If the first pull-down drive control element N 13  is an NMOS transistor, a source electrode of the first pull-down drive control element N 13  may be electrically connected to the node ND 12  and a drain electrode of the first pull-down drive control element N 13  may be electrically connected to the first I/O line GIO 1 . In such a case, the first pull-down drive control element N 13  may control a pull-down drive operation of the second pull-down element N 12  in response to the second control signal CNT 2 . For example, when the second control signal CNT 2 , having a logic “high” level, is applied to a gate electrode of the first pull-down drive control element N 13  to turn on the first pull-down drive control element N 13  and the first pull-down signal PD 1  is enabled to have, for example, a logic “high” level, the second pull-down element N 12  may be turned on to pull down a level of the first I/O line GIO 1 . 
     Referring to  FIG. 3 , the second I/O line driver GIO_DRV 2  may be configured to include a second buffer ND 21 , a second inversion buffer IV 21 , a second buffer unit  21 , a third pull-up element P 21 , a fourth pull-up element P 22 , a second pull-up drive control element P 23 , a third pull-down element N 21 , a fourth pull-down element N 22  and a second pull-down drive control element N 23 . 
     The second buffer ND 21  may generate a second pull-up signal PU 2  in response to the second input signal IN 2  when an enable signal EN applied to the second buffer ND 21  is enabled to have a logic “high” level. For example, the second buffer ND 21  may generate the second pull-up signal PU 2  by inverting the second input signal IN 2 . The second inversion buffer IV 21  may generate the second control signal CNT 2  in response the second pull-up signal PU 2 . For example, the second inversion buffer IV 21  may generate the second control signal CNT 2  by inverting the second pull-up signal PU 2 . The second buffer unit  21  may generate a second pull-down signal PD 2  in response to a second inverted input signal IN 2 B when the enable signal EN applied to the second buffer unit  21  is enabled to have a logic “high” level. For example, the second buffer unit  21  may generate the second pull-down signal PD 2  by buffering the second inverted input signal IN 2 B. The second inverted input signal IN 2 B may be a complementary signal of the second input signal IN 2 . In an embodiment, the third pull-up element P 21  may be a PMOS transistor. If the third pull-up element P 21  is a PMOS transistor, a source electrode of the third pull-up element P 21  may be electrically connected to the power supply terminal VDD and a drain electrode of the third pull-up element P 21  may be electrically connected to the second I/O line GIO 2 . In such a case, if the second pull-up signal PU 2  enabled to have, for example, a logic “low” level is applied to a gate electrode of the third pull-up element P 21 , the third pull-up element P 21  may be turned on to pull up a level of the second I/O line GIO 2 . In an embodiment, the fourth pull-up element P 22  may be a PMOS transistor. If the fourth pull-up element P 22  is a PMOS transistor, a source electrode of the fourth pull-up element P 22  may be electrically connected to the power supply terminal VDD and a drain electrode of the fourth pull-up element P 22  may be electrically connected to a node ND 21 . In such a case, if the second pull-up signal PU 2  enabled to have, for example, a logic “low” level is applied to a gate electrode of the fourth pull-up element P 22 , the fourth pull-up element P 22  may be turned on to pull up a level of the node ND 21 . In an embodiment, the second pull-up drive control element P 23  may be a PMOS transistor. If the second pull-up drive control element P 23  is a PMOS transistor, a source electrode of the second pull-up drive control element P 23  may be electrically connected to the node ND 21  and a drain electrode of the second pull-up drive control element P 23  may be electrically connected to the second I/O line GIO 2 . In such a case, the second pull-up drive control element P 23  may control a pull-up drive operation of the fourth pull-up element P 22  in response to the first control signal CNT 1 . For example, when the first control signal CNT 1 , having a logic “low” level, is applied to a gate electrode of the second pull-up drive control element P 23  to turn on the second pull-up drive control element P 23  and the second pull-up signal PU 2  is enabled to have, for example, a logic “low” level, the fourth pull-up element P 22  may be turned on to pull up a level of the second I/O line GIO 2 . 
     In an embodiment, the third pull-down element N 21  may be an NMOS transistor. In such a case, a drain electrode of the third pull-down element N 21  may be electrically connected to the second I/O line GIO 2  and a source electrode of the third pull-down element N 21  may be electrically connected to the ground terminal VSS. Thus, when the second pull-down signal PD 2  enabled to have, for example, a logic “high” level is applied to a gate electrode of the third pull-down element N 21 , the third pull-down element N 21  may be turned on to pull down a level of the second I/O line GIO 2 . In an embodiment, the fourth pull-down element N 22  may be an NMOS transistor. If the fourth pull-down element N 22  is an NMOS transistor, a source electrode of the fourth pull-down element N 22  may be electrically connected to the ground terminal VSS and a drain electrode of the fourth pull-down element N 22  may be electrically connected to a node ND 22 . In such a case, if the second pull-down signal PD 2  enabled to have, for example, a logic “high” level is applied to a gate electrode of the fourth pull-down element N 22 , the fourth pull-down element N 22  may be turned on to pull down a level of the node ND 22 . In an embodiment, the second pull-down drive control element N 23  may be an NMOS transistor. If the second pull-down drive control element N 23  is an NMOS transistor, a source electrode of the second pull-down drive control element N 23  may be electrically connected to the node ND 22  and a drain electrode of the second pull-down drive control element N 23  may be electrically connected to the second I/O line GIO 2 . In such a case, the second pull-down drive control element N 23  may control a pull-down drive operation of the fourth pull-down element N 22  in response to the first control signal CNT 1 . For example, when the first control signal CNT 1 , having a logic “high” level, is applied to a gate electrode of the second pull-down drive control element N 23  to turn on the second pull-down drive control element N 23  and the second pull-down signal PD 2  is enabled to have, for example, a logic “high” level, the fourth pull-down element N 22  may be turned on to pull down a level of the second I/O line GIO 2 . 
     Hereinafter, operations of the first and second I/O line drivers GIO_DRV 1  and GIO_DRV 2  shown in  FIGS. 2 and 3  will be described with reference to the tables of  FIGS. 4A to 4D . 
     Referring to  FIG. 4A , if the first input signal IN 1  has a logic “high” level, the first inverted input signal IN 1 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the first pull-up signal PU 1  may be enabled to have a logic “low” level and the first pull-down signal PD 1  may be disabled to have a logic “low” level. In such a case, the first control signal CNT 1  may be generated to have a logic “high” level since the first pull-up signal PU 1  is enabled to have a logic “low” level. If the second input signal IN 2  has a logic “high” level, the second inverted input signal IN 2 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the second pull-up signal PU 2  may be enabled to have a logic “low” level and the second pull-down signal PD 2  may be disabled to have a logic “low” level. In such a case, the second control signal CNT 2  may be generated to have a logic “high” level since the second pull-up signal PU 2  is enabled to have a logic “low” level. Although both the first and second pull-up elements P 11  and P 12  are turned on by the first pull-up signal PU 1  enabled to have a logic “low” level, the first pull-up drive control element P 13  may be turned off by the second control signal CNT 2  having a logic “high” level. Thus, the second pull-up element P 12  cannot pull up a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1 . Further, although both the third and fourth pull-up elements P 21  and P 22  are turned on by the second pull-up signal PU 2  enabled to have a logic “low” level, the second pull-up drive control element P 23  may be turned off by the first control signal CNT 1  having a logic “high” level. Thus, the fourth pull-up element P 22  cannot pull up a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2 . That is, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up, the first I/O line GIO 1  can be pulled up only by the first pull-up element P 11  and the second I/O line GIO 2  can be pulled up only by the third pull-up element P 21 . 
     Referring to  FIG. 4B , if the first input signal IN 1  has a logic “high” level, the first inverted input signal IN 1 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the first pull-up signal PU 1  may be enabled to have a logic “low” level and the first pull-down signal PD 1  may be disabled to have a logic “low” level. In such a case, the first control signal CNT 1  may be generated to have a logic “high” level since the first pull-up signal PU 1  is enabled to have a logic “low” level. If the second input signal IN 2  has a logic “low” level, the second inverted input signal IN 2 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the second pull-up signal PU 2  may be disabled to have a logic “high” level and the second pull-down signal PD 2  may be enabled to have a logic “high” level. In such a case, the second control signal CNT 2  may be generated to have a logic “low” level since the second pull-up signal PU 2  is disabled to have a logic “high” level. Thus, since both the first and second pull-up elements P 11  and P 12  are turned on by the first pull-up signal PU 1  enabled to have a logic “low” level and the first pull-up drive control element P 13  is also turned on by the second control signal CNT 2  having a logic “low” level, a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1  may be pulled up by the first and second pull-up elements P 11  and P 12 . Further, since both the third and fourth pull-down elements N 21  and N 22  are turned on by the second pull-down signal PD 2  enabled to have a logic “high” level and the second pull-down drive control element N 23  is also turned on by the first control signal CNT 1  having a logic “high” level, a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2  may be pulled down by the third and fourth pull-down elements N 21  and N 22 . 
     Referring to  FIG. 4C , if the first input signal IN 1  has a logic “low” level, the first inverted input signal IN 1 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the first pull-up signal PU 1  may be disabled to have a logic “high” level and the first pull-down signal PD 1  may be enabled to have a logic “high” level. In such a case, the first control signal CNT 1  may be generated to have a logic “low” level since the first pull-up signal PU 1  is disabled to have a logic “high” level. If the second input signal IN 2  has a logic “high” level, the second inverted input signal IN 2 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the second pull-up signal PU 2  may be enabled to have a logic “low” level and the second pull-down signal PD 2  may be disabled to have a logic “low” level. In such a case, the second control signal CNT 2  may be generated to have a logic “high” level since the second pull-up signal PU 2  is enabled to have a logic “low” level. Thus, since both the first and second pull-down elements N 11  and N 12  are turned on by the first pull-down signal PD 1  enabled to have a logic “high” level and the first pull-down drive control element N 13  is also turned on by the second control signal CNT 2  having a logic “high” level, a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1  may be pulled down by the first and second pull-down elements N 11  and N 12 . Further, since both the third and fourth pull-up elements P 21  and P 22  are turned on by the second pull-up signal PU 2  enabled to have a logic “low” level and the second pull-up drive control element P 23  is also turned on by the first control signal CNT 1  having a logic “low” level, a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2  may be pulled up by the third and fourth pull-up elements P 21  and P 22 . 
     Referring to  FIG. 4D , if the first input signal IN 1  has a logic “low” level, the first inverted input signal IN 1 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the first pull-up signal PU 1  may be disabled to have a logic “high” level and the first pull-down signal PD 1  may be enabled to have a logic “high” level. In such a case, the first control signal CNT 1  may be generated to have a logic “low” level since the first pull-up signal PU 1  is disabled to have a logic “high” level. If the second input signal IN 2  has a logic “low” level, the second inverted input signal IN 2 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the second pull-up signal PU 2  may be disabled to have a logic “high” level and the second pull-down signal PD 2  may be enabled to have a logic “high” level. In such a case, the second control signal CNT 2  may be generated to have a logic “low” level since the second pull-up signal PU 2  is disabled to have a logic “high” level. Although both the first and second pull-down elements N 11  and N 12  are turned on by the first pull-down signal PD 1  enabled to have a logic “high” level, the first pull-down drive control element N 13  may be turned off by the second control signal CNT 2  having a logic “low” level. Thus, the second pull-down element N 12  cannot pull down a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1 . Further, although both the third and fourth pull-down elements N 21  and N 22  are turned on by the second pull-down signal PD 2  enabled to have a logic “high” level, the second pull-down drive control element N 23  may be turned off by the first control signal CNT 1  having a logic “low” level. Thus, the fourth pull-down element N 22  cannot pull down a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2 . That is, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled down, the first I/O line GIO 1  can be pulled down only by the first pull-down element N 11  and the second I/O line GIO 2  can be pulled down only by the third pull-down element N 21 . 
     As a result, a drivability of the circuit for driving the first and second I/O lines GIO 1  and GIO 2  shown in  FIGS. 2 and 3  may be reduced when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up or pulled down. That is, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up, the first I/O line GIO 1  can be pulled up only by the first pull-up element P 11  and the second I/O line GIO 2  can be pulled up only by the third pull-up element P 21 . Further, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled down, the first I/O line GIO 1  can be pulled down only by the first pull-down element N 11  and the second I/O line GIO 2  can be pulled down only by the third pull-down element N 21 . Accordingly, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously driven to the same level, the number of elements which are simultaneously turned on can be reduced to decrease the simultaneous switching noises. Hence, the reliability of semiconductor systems including the I/O line driving circuit according to an embodiment may be improved. 
     Referring to  FIG. 5 , another example of the first I/O line driver GIO_DRV 1  may be configured to include a third buffer ND 12 , a fourth buffer ND 13 , a third inversion buffer IV 12 , a fifth pull-up element P 14 , a sixth pull-up element P 15 , a third pull-up drive control element P 16 , a fifth pull-down element N 14 , a sixth pull-down element N 15  and a third pull-down drive control element N 16 . 
     The third buffer ND 12  may generate a third pull-up signal PU 3  in response to a first input signal IN 1  when an enable signal EN applied to the third buffer ND 12  is enabled to have a logic “high” level. For example, the third buffer ND 12  may generate the third pull-up signal PU 3  by inverting the first input signal IN 1 . The fourth buffer ND 13  may generate a third control signal CNT 3  in response to a first inverted input signal IN 1 B when the enable signal EN applied to the fourth buffer ND 13  is enabled to have a logic “high” level. For example, the fourth buffer ND 13  may generate the third control signal CNT 3  by inverting the first inverted input signal IN 1 B. The third inversion buffer IV 12  may generate a third pull-down signal PD 3  in response to the third control signal CNT 3 . For example, the third inversion buffer IV 12  may generate the third pull-down signal PD 3  by buffering the third control signal CNT 3 . The fifth pull-up element P 14  may be a PMOS transistor. If the fifth pull-up element P 14  is a PMOS transistor, a source electrode of the fifth pull-up element P 14  may be electrically connected to the power supply terminal VDD and a drain electrode of the fifth pull-up element P 14  may be electrically connected to the first I/O line GIO 1 . In such a case, if the third pull-up signal PU 3  enabled to have, for example, a logic “low” level is applied to a gate electrode of the fifth pull-up element P 14 , the fifth pull-up element P 14  may be turned on to pull up a level of the first I/O line GIO 1 . In an embodiment, the sixth pull-up element P 15  and the third pull-up drive control element P 16  may be PMOS transistors. If the sixth pull-up element P 15  and the third pull-up drive control element P 16  are PMOS transistors, the sixth pull-up element P 15  and the third pull-up drive control element P 16  may be connected in series. Further, a source electrode of the sixth pull-up element P 15  may be electrically connected to the power supply terminal VDD and a drain electrode of the third pull-up drive control element P 16  may be electrically connected to the first I/O line GIO 1 . In such a case, if the third pull-up signal PU 3  enabled to have, for example, a logic “low” level is applied to a gate electrode of the sixth pull-up element P 15 , the sixth pull-up element P 15  may be turned on to pull up a level of a source electrode of the third pull-up drive control element P 16 . In addition, the third pull-up drive control element P 16  may control a pull-up drive operation of the sixth pull-up element P 15  in response to a fourth control signal CNT 4 . For example, when the fourth control signal CNT 4  having a logic “low” level is applied to a gate electrode of the third pull-up drive control element P 16  to turn on the third pull-up drive control element P 16  and the third pull-up signal PU 3  is enabled to have a logic “low” level, the sixth pull-up element P 15  may be turned on to pull up a level of the first I/O line GIO 1 . 
     The fifth pull-down element N 14  may be an NMOS transistor. In such a case, a drain electrode of the fifth pull-down element N 14  may be electrically connected to the first I/O line GIO 1  and a source electrode of the fifth pull-down element N 14  may be electrically connected to the ground terminal VSS. Thus, when the third pull-down signal PD 3  enabled to have, for example, a logic “high” level is applied to a gate electrode of the fifth pull-down element N 14 , the fifth pull-down element N 14  may be turned on to pull down a level of the first I/O line GIO 1 . In an embodiment, the sixth pull-down element N 15  and the third pull-down drive control element N 16  may be NMOS transistors. If the sixth pull-down element N 15  and the third pull-down drive control element N 16  are NMOS transistors, the sixth pull-down element N 15  and the third pull-down drive control element N 16  may be connected in series. Further, a source electrode of the sixth pull-down element N 15  may be electrically connected to the ground terminal VSS and a drain electrode of the sixth pull-down drive control element N 16  may be electrically connected to the first I/O line GIO 1 . In such a case, if the third pull-down signal PD 3  enabled to have, for example, a logic “high” level is applied to a gate electrode of the sixth pull-down element N 15 , the sixth pull-down element N 15  may be turned on to pull down a level of a source electrode of the third pull-down drive control element N 16 . In addition, the third pull-down drive control element N 16  may control a pull-down drive operation of the sixth pull-down element N 15  in response to the fourth control signal CNT 4 . For example, when the fourth control signal CNT 4  having a logic “high” level is applied to a gate electrode of the third pull-down drive control element N 16  to turn on the third pull-down drive control element N 16  and the third pull-down signal PD 3  is enabled to have a logic “high” level, the sixth pull-down element N 15  may be turned on to pull down a level of the first I/O line GIO 1 . 
     Referring to  FIG. 6 , another example of the second I/O line driver GIO_DRV 2  may be configured to include a fifth buffer ND 22 , a sixth buffer ND 23 , a fourth inversion buffer IV 22 , a seventh pull-up element P 24 , an eighth pull-up element P 25 , a fourth pull-up drive control element P 26 , a seventh pull-down element N 24 , an eighth pull-down element N 25  and a fourth pull-down drive control element N 26 . 
     The fifth buffer ND 22  may generate a fourth pull-up signal PU 4  in response to a second input signal IN 2  when an enable signal EN is enabled to have a logic “high” level. For example, the fifth buffer ND 22  may generate the fourth pull-up signal PU 4  by inverting the second input signal IN 2 . The sixth buffer ND 23  may generate the fourth control signal CNT 4  in response to the second inverted input signal IN 2 B when the enable signal EN applied to the sixth buffer ND 23  is enabled to have a logic “high” level. For example, the sixth buffer ND 23  may generate the fourth control signal CNT 4  by inverting the second inverted input signal IN 2 B. The fourth inversion buffer IV 22  may generate a fourth pull-down signal PD 4  in response to the fourth control signal CNT 4 . For example, the fourth inversion buffer IV 22  may generate the fourth pull-down signal PD 4  by inverting the fourth control signal CNT 4 . In an embodiment, the seventh pull-up element P 24  may be a PMOS transistor. If the seventh pull-up element P 24  is a PMOS transistor, a source electrode of the seventh pull-up element P 24  may be electrically connected to the power supply terminal VDD and a drain electrode of the seventh pull-up element P 24  may be electrically connected to the second I/O line GIO 2 . In such a case, if the fourth pull-up signal PU 4  enabled to have, for example, a logic “low” level is applied to a gate electrode of the seventh pull-up element P 24 , the seventh pull-up element P 24  may be turned on to pull up a level of the second I/O line GIO 2 . In an embodiment, the eighth pull-up element P 25  and the fourth pull-up drive control element P 26  may be PMOS transistors. If the eighth pull-up element P 25  and the fourth pull-up drive control element P 26  are PMOS transistors, the eighth pull-up element P 25  and the fourth pull-up drive control element P 26  may be connected in series. Further, a source electrode of the eighth pull-up element P 25  may be electrically connected to the power supply terminal VDD and a drain electrode of the fourth pull-up drive control element P 26  may be electrically connected to the second I/O line GIO 2 . In such a case, if the fourth pull-up signal PU 4  enabled to have, for example, a logic “low” level is applied to a gate electrode of the eighth pull-up element P 25 , the eighth pull-up element P 25  may be turned on to pull up a level of a source electrode of the fourth pull-up drive control element P 26 . In addition, the fourth pull-up drive control element P 26  may control a pull-up drive operation of the eighth pull-up element P 25  in response to the third control signal CNT 3 . For example, when the third control signal CNT 3  having a logic “low” level is applied to a gate electrode of the fourth pull-up drive control element P 26  to turn on the fourth pull-up drive control element P 26  and the fourth pull-up signal PU 4  is enabled to have a logic “low” level, the eighth pull-up element P 25  may be turned on to pull up a level of the second I/O line GIO 2 . 
     In an embodiment, the seventh pull-down element N 24  may be an NMOS transistor. In such a case, a drain electrode of the seventh pull-down element N 24  may be electrically connected to the second I/O line GIO 2  and a source electrode of the seventh pull-down element N 24  may be electrically connected to the ground terminal VSS. Thus, when the fourth pull-down signal PD 4  enabled to have, for example, a logic “high” level is applied to a gate electrode of the seventh pull-down element N 24 , the seventh pull-down element N 24  may be turned on to pull down a level of the second I/O line GIO 2 . In an embodiment, the eighth pull-down element N 25  and the fourth pull-down drive control element N 26  may be NMOS transistors. If the eighth pull-down element N 25  and the fourth pull-down drive control element N 26  are NMOS transistors, the eighth pull-down element N 25  and the fourth pull-down drive control element N 26  may be connected in series. Further, a source electrode of the eighth pull-down element N 25  may be electrically connected to the ground terminal VSS and a drain electrode of the fourth pull-down drive control element N 26  may be electrically connected to the second I/O line GIO 2 . In such a case, if the fourth pull-down signal PD 4  enabled to have, for example, a logic “high” level is applied to a gate electrode of the eighth pull-down element N 25 , the eighth pull-down element N 25  may be turned on to pull down a level of a source electrode of the fourth pull-down drive control element N 26 . In addition, the fourth pull-down drive control element N 26  may control a pull-down drive operation of the eighth pull-down element N 25  in response to the third control signal CNT 3 . For example, when the third control signal CNT 3  having a logic “high” level is applied to a gate electrode of the fourth pull-down drive control element N 26  to turn on the fourth pull-down drive control element N 26  and the fourth pull-down signal PD 4  is enabled to have a logic “high” level, the eighth pull-down element N 25  may be turned on to pull down a level of the second I/O line GIO 2 . 
     Hereinafter, operations of the first and second I/O line drivers GIO_DRV 1  and GIO_DRV 2  shown in  FIGS. 5 and 6  will be described with reference to the tables of  FIGS. 7A to 7D . 
     Referring to  FIG. 7A , if the first input signal IN 1  has a logic “high” level, the first inverted input signal IN 1 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the third pull-up signal PU 3  may be enabled to have a logic “low” level and the third control signal CNT 3  may be generated to have a logic “high” level since the first inverted input signal IN 1 B has a logic “low” level. The third pull-down signal PD 3  may be disabled to have a logic “low” level since the third control signal CNT 3  has a logic “high” level. If the second input signal IN 2  has a logic “high” level, the second inverted input signal IN 2 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the fourth pull-up signal PU 4  may be enabled to have a logic “low” level and the fourth control signal CNT 4  may be generated to have a logic “high” level in response to the second inverted input signal IN 2 B having a logic “low” level. The fourth pull-down signal PD 4  may be disabled to have a logic “low” level since the fourth control signal CNT 4  has a logic “high” level. Although both the fifth and sixth pull-up elements P 14  and P 15  are turned on by the third pull-up signal PU 3  enabled to have a logic “low” level, the third pull-up drive control element P 16  may be turned off by the fourth control signal CNT 4  having a logic “high” level. Thus, the sixth pull-up element P 15  cannot pull up a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1 . Further, although both the seventh and eighth pull-up elements P 24  and P 25  are turned on by the fourth pull-up signal PU 4  enabled to have a logic “low” level, the fourth pull-up drive control element P 26  may be turned off by the third control signal CNT 3  having a logic “high” level. Thus, the eighth pull-up element P 25  cannot pull up a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2 . That is, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up, the first I/O line GIO 1  can be pulled up only by the fifth pull-up element P 14  and the second I/O line GIO 2  can be pulled up only by the seventh pull-up element P 24 . 
     Referring to  FIG. 7B , if the first input signal IN 1  has a logic “high” level, the first inverted input signal IN 1 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the third pull-up signal PU 3  may be enabled to have a logic “low” level and the third control signal CNT 3  may be generated to have a logic “high” level since the first inverted input signal IN 1 B has a logic “low” level. The third pull-down signal PD 3  may be disabled to have a logic “low” level since the third control signal CNT 3  has a logic “high” level. If the second input signal IN 2  has a logic “low” level, the second inverted input signal IN 2 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the fourth pull-up signal PU 4  may be disabled to have a logic “high” level and the fourth control signal CNT 4  may be generated to have a logic “low” level since the second inverted input signal IN 2 B has a logic “high” level. The fourth pull-down signal PD 4  may be enabled to have a logic “high” level since the fourth control signal CNT 4  has a logic “low” level. Thus, because both the fifth and sixth pull-up elements P 14  and P 15  are turned on by the third pull-up signal PU 3  enabled to have a logic “low” level and the third pull-up drive control element P 16  is also turned on by the fourth control signal CNT 4  having a logic “low” level, a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1  may be pulled up by the fifth and sixth pull-up elements P 14  and P 15 . Further, since both the seventh and eighth pull-down elements N 24  and N 25  are turned on by the fourth pull-down signal PD 4  enabled to have a logic “high” level and the fourth pull-down drive control element N 26  is also turned on by the third control signal CNT 3  having a logic “high” level, a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2  may be pulled down by the seventh and eighth pull-down elements N 24  and N 25 . 
     Referring to  FIG. 7C , if the first input signal IN 1  has a logic “low” level, the first inverted input signal IN 1 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the third pull-up signal PU 3  may be disabled to have a logic “high” level and the third control signal CNT 3  may be generated to have a logic “low” level since the first inverted input signal IN 1 B has a logic “high” level. The third pull-down signal PD 3  may be enabled to have a logic “high” level since the third control signal CNT 3  has a logic “low” level. If the second input signal IN 2  has a logic “high” level, the second inverted input signal IN 2 B has a logic “low” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the fourth pull-up signal PU 4  may be enabled to have a logic “low” level and the fourth control signal CNT 4  may be generated to have a logic “high” level since the second inverted input signal IN 2 B has a logic “low” level. The fourth pull-down signal PD 4  may be enabled to have a logic “low” level since the fourth control signal CNT 4  has a logic “high” level. Thus, because both the fifth and sixth pull-down elements N 14  and N 15  are turned on by the third pull-down signal PD 3  enabled to have a logic “high” level and the third pull-down drive control element N 16  is also turned on by the fourth control signal CNT 4  having a logic “high” level, a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1  may be pulled down by the fifth and sixth pull-down elements N 14  and N 15 . Further, since both the seventh and eighth pull-up elements P 24  and P 25  are turned on by the fourth pull-up signal PU 4  enabled to have a logic “low” level and the fourth pull-up drive control element P 26  is also turned on by the third control signal CNT 3  having a logic “low” level, a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2  may be pulled up by the seventh and eighth pull-up elements P 24  and P 25 . 
     Referring to  FIG. 7D , if the first input signal IN 1  has a logic “low” level, the first inverted input signal IN 1 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the third pull-up signal PU 3  may be disabled to have a logic “high” level and the third control signal CNT 3  may be generated to have a logic “low” level since the first inverted input signal IN 1 B has a logic “high” level. The third pull-down signal PD 3  may be enabled to have a logic “high” level since the third control signal CNT 3  has a logic “low” level. If the second input signal IN 2  has a logic “low” level, the second inverted input signal IN 2 B has a logic “high” level. Accordingly, when the enable signal EN is enabled to have a logic “high” level, the fourth pull-up signal PU 4  may be disabled to have a logic “high” level and the fourth control signal CNT 4  may be generated to have a logic “low” level since the second inverted input signal IN 2 B having a logic “high” level. The fourth pull-down signal PD 4  may be enabled to have a logic “high” level since the fourth control signal CNT 4  has a logic “low” level. Although both the fifth and sixth pull-down elements N 14  and N 15  are turned on by the third pull-down signal PD 3  enabled to have a logic “high” level, the third pull-down drive control element N 16  may be turned off by the fourth control signal CNT 4  having a logic “low” level. Thus, the sixth pull-down element N 15  cannot pull down a level of the first I/O line GIO 1  of the first I/O line driver GIO_DRV 1 . Further, although both the seventh and eighth pull-down elements N 24  and N 25  are turned on by the fourth pull-down signal PD 4  enabled to have a logic “high” level, the fourth pull-down drive control element N 26  may be turned off by the third control signal CNT 3  having a logic “low” level. Thus, the eighth pull-down element N 25  cannot pull down a level of the second I/O line GIO 2  of the second I/O line driver GIO_DRV 2 . That is, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled down, the first I/O line GIO 1  can be pulled down only by the fifth pull-down element N 14  and the second I/O line GIO 2  can be pulled down only by the seventh pull-down element N 24 . 
     As a result, a drivability of the circuit for driving the first and second I/O lines GIO 1  and GIO 2  shown in  FIGS. 5 and 6  may be reduced when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up or pulled down. That is, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled up, the first I/O line GIO 1  can be pulled up only by the fifth pull-up element P 14  and the second I/O line GIO 2  can be pulled up only by the seventh pull-up element P 24 . Further, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously pulled down, the first I/O line GIO 1  can be pulled down only by the fifth pull-down element N 14  and the second I/O line GIO 2  can be pulled down only by the seventh pull-down element N 24 . Accordingly, when both the first and second I/O lines GIO 1  and GIO 2  are simultaneously driven to the same level, the number of elements which are simultaneously turned on can be reduced to decrease the simultaneous switching noises. Hence, the reliability of semiconductor systems including the I/O line driving circuit according to an embodiment may be improved. 
     The example embodiments of the inventive concept have been disclosed above for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the inventive concept as disclosed in the accompanying claims.