Abstract:
A method and system for routing fiber channel frames using a fiber channel switch element is provided. The switch element includes logic for comparing a credit counter value with a first threshold value to enable a credit limiting feature; and a first counter that receives a signal after a frame has departed from a transmit segment and maintains a maximum value for a certain duration that is based on the first threshold value. The method includes enabling a credit limiting feature, wherein frame transmission from a certain source is delayed when the credit limiting feature is enabled. The first counter is incremented every time a frame departs and holds its maximum value based on the threshold value. When the first counter is at the maximum value, a credit-limiting signal is used to enable the credit limiting feature by setting a control bit in a control register.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C.§119(e)(1) to the following Provisional Patent Applications: 
     Filed on Sep. 19, 2003, Ser. No. 60/503,812, entitled “Method and System for Fibre Channel Switches”; 
     Filed on Jan. 21, 2004, Ser. No. 60/537,933 entitled “Method And System For Routing And Filtering Network Data Packets In Fibre Channel Systems”; 
     Filed on Jul. 21, 2003, Ser. No. 60/488,757, entitled “Method and System for Selecting Virtual Lanes in Fibre Channel Switches”; 
     Filed on Dec. 29, 2003, Ser. No. 60/532,965, entitled “Programmable Pseudo Virtual Lanes for Fibre Channel Systems”; 
     Filed on Sep. 19, 2003, Ser. No. 60/504,038, entitled “Method and System for Reducing Latency and Congestion in Fibre Channel Switches; 
     Filed on Aug. 14, 2003, Ser. No. 60/495,212, entitled “Method and System for Detecting Congestion and Over Subscription in a Fibre channel Network”; 
     Filed on Aug. 14, 2003, Ser. No. 60/495, 165, entitled “LUN Based Hard Zoning in Fibre Channel Switches”; 
     Filed on Sep. 19, 2003, Ser. No. 60/503,809, entitled “Multi Speed Cut Through Operation in Fibre Channel Switches”; 
     Filed on Sep. 23, 2003, Ser. No. 60/505,381, entitled “Method and System for Improving bandwidth and reducing Idles in Fibre Channel Switches”; 
     Filed on Sep. 23, 2003, Ser. No. 60/505,195, entitled “Method and System for Keeping a Fibre Channel Arbitrated Loop Open During Frame Gaps”; 
     Filed on Mar. 30, 2004, Ser. No. 60/557,613, entitled “Method and System for Congestion Control based on Optimum Bandwidth Allocation in a Fibre Channel Switch”; 
     Filed on Sep. 23, 2003, Ser. No. 60/505,075, entitled “Method and System for Programmable Data Dependent Network Routing”; 
     Filed on Sep. 19, 2003, Ser. No. 60/504,950, entitled “Method and System for Power Control of Fibre Channel Switches”; 
     Filed on Dec. 29, 2003, Ser. No. 60/532,967, entitled “Method and System for Buffer to Buffer Credit recovery in Fibre Channel Systems Using Virtual and/or Pseudo Virtual Lane”; 
     Filed on Dec. 29, 2003, Ser. No. 60/532,966, entitled “Method And System For Using Extended Fabric Features With Fibre Channel Switch Elements”; 
     Filed on Mar. 4, 2004, Ser. No. 60/550,250, entitled “Method And System for Programmable Data Dependent Network Routing”; 
     Filed on May 7, 2004, Ser. No. 60/569,436, entitled “Method And System For Congestion Control In A Fibre Channel Switch”; 
     Filed on May 18, 2004, Ser. No. 60/572,197, entitled “Method and System for Configuring Fibre Channel Ports” and 
     Filed on Dec. 29, 2003, Ser. No. 60/532,963 entitled “Method and System for Managing Traffic in Fibre Channel Switches”. 
     The disclosure of the foregoing applications is incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to fibre channel systems, and more particularly, to congestion control by using a credit-limiting feature for frame transmission in a fibre channel switch. 
     2. Background of the Invention 
     Fibre channel is a set of American National Standard Institute (ANSI) standards, which provide a serial transmission protocol for storage and network protocols such as HIPPI, SCSI, IP, ATM and others. Fibre channel provides an input/output interface to meet the requirements of both channel and network users. 
     Fibre channel supports three different topologies: point-to-point, arbitrated loop and fibre channel fabric. The point-to-point topology attaches two devices directly. The arbitrated loop topology attaches devices in a loop. The fibre channel fabric topology attaches host systems directly to a fabric, which are then connected to multiple devices. The fibre channel fabric topology allows several media types to be interconnected. 
     Fibre channel is a closed system that relies on multiple ports to exchange information on attributes and characteristics to determine if the ports can operate together. If the ports can work together, they define the criteria under which they communicate. 
     In fibre channel, a path is established between two nodes where the path&#39;s primary task is to transport data from one point to another at high speed with low latency, performing only simple error detection in hardware. 
     Fibre channel fabric devices include a node port or “N_Port” that manages fabric connections. The N_port establishes a connection to a fabric element (e.g., a switch) having a fabric port or F_port. Fabric elements include the intelligence to handle routing, error detection, recovery, and similar management functions. 
     A fibre channel switch is a multi-port device where each port manages a simple point-to-point connection between itself and its attached system. Each port can be attached to a server, peripheral, I/O subsystem, bridge, hub, router, or even another switch. A switch receives messages from one port and automatically routes it to another port. Multiple calls or data transfers happen concurrently through the multi-port fibre channel switch. 
     Fibre channel switches use memory buffers to hold frames received and sent across a network. Associated with these buffers are credits, which are the number of frames that a buffer can hold per fabric port. 
     Fibre Channel switch fabrics can have arbitrary topologies and a mixture of frame traffic where frame source (s) and destinations operate at different speeds. Quality of service and congestion management is desirable to optimize switch performance. 
     In Fibre Channel, buffer-to-buffer credit mechanism is used to control frame flow on a Fibre Channel link to prevent the inability to deliver any frames because of lost R_RDYs or lost frames. The R_RDY primitive is used to indicate whether a receive port has credit to receive frames. 
       FIG. 2  illustrates the congestion problem in conventional fibre channel switches. In  FIG. 2 , Host  201  sends data to target  207  and host  202  sends data to target  208 , via switches  203  and  206  having ports  204  and  205 . Target  208  link operates at 1 gigabit/second and all other links operate at higher rates (for example, 2 Gb/S, 4 Gb/S, 8 Gb/S or 10 Gb/s. 
     If both host  201  and  202  send data as fast as they can, then eventually all receive buffers in port  205  will get filled up with frames destined for target  208 , which in this example operates at the slowest speed compared to the other links. Hence port  204  will not be able to transmit at its bandwidth and cause congestion in the overall system. 
     The present fibre channel switches and standard do not provide a mechanism where “available credit” can be used for congestion control and for managing frame flow within a Fabric. Therefore, there is a need for a system and method that allows congestion control based on available credit or “credit limitations”. 
     SUMMARY OF THE PRESENT INVENTION 
     In one aspect of the present invention, a method for routing fibre channel frames using a fibre channel switch element is provided. The method includes enabling a credit limiting feature, wherein frame transmission from a certain source is delayed when the credit limiting feature is enabled. 
     A credit counter value is compared to a threshold value and the comparison is used to enable the credit-limiting feature. A counter is incremented every time a frame departs and holds its maximum value based on the threshold value. When the counter is at the maximum value, a credit-limiting signal is used to enable the credit limiting feature by setting a control bit in a control register. 
     In another aspect of the present invention, a method for routing fibre channel frames using a fibre channel switch element is provided. The method includes, determining if a credit limiting feature is enabled; incrementing (increasing) a counter value after a R_RDY is received when a frame departs; comparing the counter value with a threshold value; and blocking frame transmission from a particular source based on the comparison between the counter value and the threshold value. 
     A control bit from a control register enables the credit limiting feature. The counter value increments if a VC_RDY is received. Also, the threshold value is programmed in a register. 
     In another aspect of the present invention, a fibre channel switch element for routing fibre channel frames. The switch element includes logic for comparing a credit counter value with a first threshold value to enable a credit limiting feature; and a first counter that receives a signal after a frame has departed from a transmit segment and maintains a maximum value for a certain duration that is based on the first threshold value. 
     The switch element further includes logic for generating a credit limiting signal to set a control bit value that enables the credit limiting feature; a blocking counter that maintains a count for a number of R-RDYs that are received after a frame has departed; and logic for comparing the blocking counter value with a second threshold value and generating a signal for blocking frame transmission from a particular source port based on the comparison. 
     This brief summary has been provided so that the nature of the invention may be understood quickly. A more complete understanding of the invention can be obtained by reference to the following detailed description of the preferred embodiments thereof concerning the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing features and other features of the present invention will now be described with reference to the drawings of a preferred embodiment. In the drawings, the same components have the same reference numerals. The illustrated embodiment is intended to illustrate, but not to limit the invention. The drawings include the following Figures: 
         FIG. 1A  shows an example of a Fibre Channel network system; 
         FIG. 1B  shows an example of a Fibre Channel switch element, according to one aspect of the present invention; 
         FIG. 1C  shows a block diagram of a 20-channel switch chassis, according to one aspect of the present invention; 
         FIG. 1D  shows a block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10 G ports, according to one aspect of the present invention; 
       FIGS.  1 E- 1 / 1 E- 2  (jointly referred to as  FIG. 1E ) show another block diagram of a Fibre Channel switch element with sixteen GL_Ports and four 10 G ports, according to one aspect of the present invention; 
         FIG. 2  shows an example of an architecture, which can use the credit-limiting feature, according to one aspect of the present invention; 
       FIGS.  3 A/ 3 B (jointly referred to as  FIG. 3 ) show a block diagram of a GL_Port, according to one aspect of the present invention; 
       FIGS.  4 A/ 4 B (jointly referred to as  FIG. 3 ) show a block diagram of XG_Port (10 G) port, according to one aspect of the present invention; 
         FIG. 5  shows a schematic for generating and using the credit limiting feature, according to one aspect of the present invention; and 
         FIG. 6  shows a flow diagram of executable steps for routing frames using the credit-limiting feature, according to one aspect of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Definitions: 
     The following definitions are provided as they are typically (but not exclusively) used in the fibre channel environment, implementing the various adaptive aspects of the present invention. 
     “E-Port”: A fabric expansion port that attaches to another Interconnect port to create an Inter-Switch Link. 
     “F_Port”: A port to which non-loop N_Ports are attached to a fabric and does not include FL_ports. 
     “Fibre channel ANSI Standard”: The standard, incorporated herein by reference in its entirety, describes the physical interface, transmission and signaling protocol of a high performance serial link for support of other high level protocols associated with IPI, SCSI, IP, ATM and others. 
     “FC-1”: Fibre channel transmission protocol, which includes serial encoding, decoding and error control. 
     “FC-2”: Fibre channel signaling protocol that includes frame structure and byte sequences. 
     “FC-3”: Defines a set of fibre channel services that are common across plural ports of a node. 
     “FC-4”: Provides mapping between lower levels of fibre channel, IPI and SCSI command sets, HIPPI data framing, IP and other upper level protocols. 
     “Fabric”: The structure or organization of a group of switches, target and host devices (NL_Port, N_ports etc.). 
     “Fabric Topology”: This is a topology where a device is directly attached to a fibre channel fabric that uses destination identifiers embedded in frame headers to route frames through a fibre channel fabric to a desired destination. 
     “FL_Port”: A L_Port that is able to perform the function of a F_Port, attached via a link to one or more NL_Ports in an Arbitrated Loop topology. 
     “Inter-Switch Link”: A Link directly connecting the E_port of one switch to the E_port of another switch. 
     Port: A general reference to N. Sub.—Port or F.Sub.—Port. 
     “L_Port”: A port that contains Arbitrated Loop functions associated with the Arbitrated Loop topology. 
     “N-Port”: A direct fabric attached port. 
     “NL_Port”: A L_Port that can perform the function of a N_Port. 
     “R_RDY”: Flow control primitive signal used for establishing credit. Receiving an R_RDY frame increases credit, while sending a R_RDY frame decreases credit. 
     “Switch”: A fabric element conforming to the Fibre Channel Switch standards. 
     “VL” (Virtual Lane (or Channel)): A dedicated portion of the data path between a source and destination port each having independent buffer to buffer flow control. 
     “VC_RDY”: Primitive for establishing credit if the switch uses virtual lanes. 
     Fibre Channel System: 
     To facilitate an understanding of the preferred embodiment, the general architecture and operation of a fibre channel system will be described. The specific architecture and operation of the preferred embodiment will then be described with reference to the general architecture of the fibre channel system. 
       FIG. 1A  is a block diagram of a fibre channel system  100  implementing the methods and systems in accordance with the adaptive aspects of the present invention. System  100  includes plural devices that are interconnected. Each device includes one or more ports, classified as node ports (N_Ports), fabric ports (F_Ports), and expansion ports (E_Ports). Node ports may be located in a node device, e.g. server  103 , disk array  105  and storage device  104 . Fabric ports are located in fabric devices such as switch  101  and  102 . Arbitrated loop  106  may be operationally coupled to switch  101  using arbitrated loop ports (FL_Ports). 
     The devices of  FIG. 1A  are operationally coupled via “links” or “paths”. A path may be established between two N_ports, e.g. between server  103  and storage  104 . A packet-switched path may be established using multiple links, e.g. an N-Port in server  103  may establish a path with disk array  105  through switch  102 . 
     Fabric Switch Element 
       FIG. 1B  is a block diagram of a 20-port ASIC fabric element according to one aspect of the present invention.  FIG. 1B  provides the general architecture of a 20-channel switch chassis using the 20-port fabric element. Fabric element includes ASIC  20  with non-blocking fibre channel class 2 (connectionless, acknowledged) and class 3 (connectionless, unacknowledged) service between any ports. It is noteworthy that ASIC  20  may also be designed for class 1 (connection-oriented) service, within the scope and operation of the present invention as described herein. 
     The fabric element of the present invention is presently implemented as a single CMOS ASIC, and for this reason the term “fabric element” and ASIC are used interchangeably to refer to the preferred embodiments in this specification. Although  FIG. 1B  shows  20  ports, the present invention is not limited to any particular number of ports. 
     ASIC  20  has 20 ports numbered in  FIG. 1B  as GL 0  through GL 19 . These ports are generic to common Fibre Channel port types, for example, F_Port, FL_Port and E-Port. In other words, depending upon what it is attached to, each GL port can function as any type of port. Also, the GL port may function as a special port useful in fabric element linking, as described below. 
     For illustration purposes only, all GL ports are drawn on the same side of ASIC  20  in  FIG. 1B . However, the ports may be located on both sides of ASIC  20  as shown in other figures. This does not imply any difference in port or ASIC design. Actual physical layout of the ports will depend on the physical layout of the ASIC. 
     Each port GL 0 -GL 19  has transmit and receive connections to switch crossbar  50 . One connection is through receive buffer  52 , which functions to receive and temporarily hold a frame during a routing operation. The other connection is through a transmit buffer  54 . 
     Switch crossbar  50  includes a number of switch crossbars for handling specific types of data and data flow control information. For illustration purposes only, switch crossbar  50  is shown as a single crossbar. Switch crossbar  50  is a connectionless crossbar (packet switch) of known conventional design, sized to connect 21×21 paths. This is to accommodate 20 GL ports plus a port for connection to a fabric controller, which may be external to ASIC  20 . 
     In the preferred embodiments of switch chassis described herein, the fabric controller is a firmware-programmed microprocessor, also referred to as the input/out processor (“IOP”). IOP  66  is shown in  FIG. 1C  as a part of a switch chassis utilizing one or more of ASIC  20 . As seen in  FIG. 1B , bi-directional connection to IOP  66  is routed through port  67 , which connects internally to a control bus  60 . Transmit buffer  56 , receive buffer  58 , control register  62  and Status register  64  connect to bus  60 . Transmit buffer  56  and receive buffer  58  connect the internal connectionless switch crossbar  50  to IOP  66  so that it can source or sink frames. 
     Control register  62  receives and holds control information from IOP  66 , so that IOP  66  can change characteristics or operating configuration of ASIC  20  by placing certain control words in register  62 . IOP  66  can read status of ASIC  20  by monitoring various codes that are placed in status register  64  by monitoring circuits (not shown). 
       FIG. 1C  shows a 20-channel switch chassis S 2  using ASIC  20  and IOP  66 . S 2  will also include other elements, for example, a power supply (not shown). The 20 GL ports correspond to channel C 0 -C 19 . Each GL port has a serial/deserializer (SERDES) designated as S 0 -S 19 . Ideally, the SERDES functions are implemented on ASIC  20  for efficiency, but may alternatively be external to each GL port. 
     Each GL port has an optical-electric converter, designated as OE 0 -OE 19  connected with its SERDES through serial lines, for providing fibre optic input/output connections, as is well known in the high performance switch design. The converters connect to switch channels C 0 -C 19 . It is noteworthy that the ports can connect through copper paths or other means instead of optical-electric converters. 
       FIG. 1D  shows a block diagram of ASIC  20  with sixteen GL ports and four 10 G (Gigabyte) port control modules designated as XG 0 -XG 3  for four 10 G ports designated as XGP 0 -XGP 3 . ASIC  20  include a control port  62 A that is coupled to IOP  66  through a PCI connection  66 A. 
     FIG.  1 E- 1 / 1 E- 2  (jointly referred to as  FIG. 1E ) show yet another block diagram of ASIC  20  with sixteen GL and four XG port control modules. Each GL port control module has a Receive port (RPORT)  69  with a receive buffer (RBUF)  69 A and a transmit port  70  with a transmit buffer (TBUF)  70 A, as described below in detail. GL and XG port control modules are coupled to physical media devices (“PMD”)  76  and  75  respectively. 
     Control port module  62 A includes control buffers  62 B and  62 D for transmit and receive sides, respectively. Module  62 A also includes a PCI interface module  62 C that allows interface with IOP  66  via a PCI bus  66 A. 
     XG_Port (for example 74B) includes RPORT  72  with RBUF  71  similar to RPORT  69  and RBUF  69 A and a TBUF and TPORT similar to TBUF  70 A and TPORT  70 . Protocol module  73  interfaces with SERDES to handle protocol based functionality. 
     GL Port: 
       FIGS. 3A-3B  (referred to as  FIG. 3 ) show a detailed block diagram of a GL port as used in ASIC  20 . GL port  300  is shown in three segments, namely, receive segment (RPORT)  310 , transmit segment (TPORT)  312  and common segment  311 . 
     Receive Segment of GL Port: 
     Frames enter through link  301  and SERDES  302  converts data into 10-bit parallel data to fibre channel characters, which are then sent to receive pipe (“Rpipe” (may also be shown as “Rpipe1” or “Rpipe2”))  303 A via a de-multiplexer (DEMUX)  303 . Rpipe  303 A includes, parity module  305  and decoder  304 . Decoder  304  decodes 10B data to 8B and parity module  305  adds a parity bit. Rpipe  303 A also performs various Fibre Channel standard functions such as detecting a start of frame (SOF), end-of frame (EOF), Idles, R_RDYs (fibre channel standard primitive) and the like, which are not described since they are standard functions. 
     Rpipe  303 A connects to smoothing FIFO (SMF) module  306  that performs smoothing functions to accommodate clock frequency variations between remote transmitting and local receiving devices. 
     Frames received by RPORT  310  are stored in receive buffer (RBUF)  69 A, (except for certain Fibre Channel Arbitrated Loop (AL) frames). Path  309  shows the frame entry path, and all frames entering path  309  are written to RBUF  69 A as opposed to the AL path  308 . 
     Cyclic redundancy code (CRC) module  313  further processes frames that enter GL port  300  by checking CRC and processing errors according to FC_PH rules. The frames are subsequently passed to RBUF  69 A where they are steered to an appropriate output link. RBUF  69 A is a link receive buffer and can hold multiple frames. 
     Reading from and writing to RBUF  69 A are controlled by RBUF read control logic (“RRD”)  319  and RBUF write control logic (“RWT”)  307 , respectively. RWT  307  specifies which empty RBUF  69 A slot will be written into when a frame arrives through the data link via multiplexer (“Mux”)  313 B, CRC generate module  313 A and EF (external proprietary format) module  314 . EF_module  314  encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel 8B codes. Mux  313 B receives input from Rx Spoof module  314 A, which encodes frames to an proprietary format (if enabled). RWT  307  controls RBUF  69 A write addresses and provides the slot number to tag writer (“TWT”)  317 . 
     RRD  319  processes frame transfer requests from RBUF  69 A. Frames may be read out in any order and multiple destinations may get copies of the frames. 
     Steering state machine (SSM)  316  receives frames and determines the destination for forwarding the frame. SSM  316  produces a destination mask, where there is one bit for each destination. Any bit set to a certain value, for example, 1, specifies a legal destination, and there can be multiple bits set, if there are multiple destinations for the same frame (multicast or broadcast). 
     SSM  316  makes this determination using information from alias cache  315 , steering registers  316 A, control register  326  values and frame contents. IOP  66  writes all tables so that correct exit path is selected for the intended destination port addresses. 
     The destination mask from SSM  316  is sent to TWT  317  and a RBUF tag register (RTAG)  318 . TWT  317  writes tags to all destinations specified in the destination mask from SSM  316 . Each tag identifies its corresponding frame by containing an RBUF  69 A slot number where the frame resides, and an indication that the tag is valid. 
     Each slot in RBUF  69 A has an associated set of tags, which are used to control the availability of the slot. The primary tags are a copy of the destination mask generated by SSM  316 . As each destination receives a copy of the frame, the destination mask in RTAG  318  is cleared. When all the mask bits are cleared, it indicates that all destinations have received a copy of the frame and that the corresponding frame slot in RBUF  69 A is empty and available for a new frame. 
     RTAG  318  also has frame content information that is passed to a requesting destination to pre-condition the destination for the frame transfer. These tags are transferred to the destination via a read multiplexer (RMUX) (not shown). 
     Transmit Segment of GL Port: 
     Transmit segment (“TPORT”)  312  performs various transmit functions. Transmit tag register (TTAG)  330  provides a list of all frames that are to be transmitted. Tag Writer  317  or common segment  311  write TTAG  330  information. The frames are provided to arbitration module (“transmit arbiter” (“TARB”))  331 , which is then free to choose which source to process and which frame from that source to be processed next. 
     TTAG  330  includes a collection of buffers (for example, buffers based on a first-in first out (“FIFO”) scheme) for each frame source. TTAG  330  writes a tag for a source and TARB  331  then reads the tag. For any given source, there are as many entries in TTAG  330  as there are credits in RBUF  69 A. 
     TARB  331  is activated anytime there are one or more valid frame tags in TTAG  330 . TARB  331  preconditions its controls for a frame and then waits for the frame to be written into TBUF  70 A. After the transfer is complete, TARB  331  may request another frame from the same source or choose to service another source. 
     TBUF  70 A is the path to the link transmitter. Typically, frames don&#39;t land in TBUF  70 A in their entirety. Mostly, frames simply pass through TBUF  70 A to reach output pins, if there is a clear path. 
     Switch Mux  332  is also provided to receive output from crossbar  50 . Switch Mux  332  receives input from plural RBUFs (shown as RBUF 00 to RBUF 19), and input from CPORT  62 A shown as CBUF 1 frame/status. TARB  331  determines the frame source that is selected and the selected source provides the appropriate slot number. The output from Switch Mux  332  is sent to ALUT  323  for S_ID spoofing and the result is fed into TBUF Tags  333 . 
     TMUX (“TxMux”)  339  chooses which data path to connect to the transmitter. The sources are: primitive sequences specified by IOP  66  via control registers  326  (shown as primitive  339 A), and signals as specified by Transmit state machine (“TSM”)  346 , frames following the loop path, or steered frames exiting the fabric via TBUF  70 A. 
     TSM  346  chooses the data to be sent to the link transmitter, and enforces all fibre Channel rules for transmission. TSM  346  receives requests to transmit from loop state machine  320 , TBUF  70 A (shown as TARB request  346 A) and from various other IOP  66  functions via control registers  326  (shown as IBUF Request  345 A). TSM  346  also handles all credit management functions, so that Fibre Channel connectionless frames are transmitted only when there is link credit to do so. 
     Loop state machine (“LPSM”)  320  controls transmit and receive functions when GL_Port is in a loop mode. LPSM  320  operates to support loop functions as specified by FC-AL-2. 
     IOP buffer (“IBUF”)  345  provides IOP  66  the means for transmitting frames for special purposes. 
     Frame multiplexer (“Frame Mux”)  336  chooses the frame source, while logic (TX spoof  334 ) converts D_ID and S_ID from public to private addresses. Frame Mux  336  receives input from Tx Spoof module  334 , TBUF tags  333 , and Mux  335  to select a frame source for transmission. 
     EF module  338  encodes proprietary (i.e. non-standard) format frames to standard Fibre Channel 8B codes and CRC module  337  generates CRC data for the outgoing frames. 
     Modules  340 - 343  put a selected transmission source into proper format for transmission on an output link  344 . Parity  340  checks for parity errors, when frames are encoded from 8B to 10B by encoder  341 , marking frames “invalid”, according to Fibre Channel rules, if there was a parity error. Phase FIFO  342 A receives frames from encode module  341  and the frame is selected by Mux  342  and passed to SERDES  343 . SERDES  343  converts parallel transmission data to serial before passing the data to the link media. SERDES  343  may be internal or external to ASIC  20 . 
     Common Segment of GL Port: 
     As discussed above, ASIC  20  include common segment  311  comprising of various modules. LPSM  320  has been described above and controls the general behavior of TPORT  312  and RPORT  310 . 
     A loop look up table (“LLUT”)  322  and an address look up table (“ALUT”)  323  is used for private loop proxy addressing and hard zoning managed by firmware. 
     Common segment  311  also includes control register  326  that controls bits associated with a GL_Port, status register  324  that contains status bits that can be used to trigger interrupts, and interrupt mask register  325  that contains masks to determine the status bits that will generate an interrupt to IOP  66 . Common segment  311  also includes AL control and status register  328  and statistics register  327  that provide accounting information for FC management information base (“MIB”). 
     Output from status register  324  may be used to generate a Fp Peek function. This allows a status register  324  bit to be viewed and sent to the CPORT. 
     Output from control register  326 , statistics register  327  and register  328  (as well as  328 A for an X_Port, shown in  FIG. 4 ) is sent to Mux  329  that generates an output signal (FP Port Reg Out). 
     Output from Interrupt register  325  and status register  324  is sent to logic  335  to generate a port interrupt signal (FP Port Interrupt). 
     BIST module  321  is used for conducting embedded memory testing. 
     XG Port 
       FIGS. 4A-4B  (referred to as  FIG. 4 ) show a block diagram of a 10 G Fibre Channel port control module (XG FPORT)  400  used in ASIC  20 . Various components of XG FPORT  400  are similar to GL port control module  300  that are described above. For example, RPORT  310  and  310 A, Common Port  311  and  311 A, and TPORT  312  and  312 A have common modules as shown in  FIGS. 3 and 4  with similar functionality. 
     RPORT  310 A can receive frames from links (or lanes)  301 A- 301 D and transmit frames to lanes  344 A- 344 D. Each link has a SERDES ( 302 A- 302 D), a de-skew module, a decode module ( 303 B- 303 E) and parity module ( 304 A- 304 D). Each lane also has a smoothing FIFO (SMF) module  305 A- 305 D that performs smoothing functions to accommodate clock frequency variations. Parity errors are checked by module  403 , while CRC errors are checked by module  404 . 
     RPORT  310 A uses a virtual lane (“VL”) cache  402  that stores plural vector values that are used for virtual lane assignment. In one aspect of the present invention, VL Cache  402  may have 32 entries and two vectors per entry. IOP  66  is able to read or write VL cache  402  entries during frame traffic. State machine  401  controls credit that is received. On the transmit side, credit state machine  347  controls frame transmission based on credit availability. State machine  347  interfaces with credit counters  328 A. 
     Also on the transmit side, modules  340 - 343  are used for each lane  344 A- 344 D, i.e., each lane can have its own module  340 - 343 . Parity module  340  checks for parity errors and encode module  341  encodes 8-bit data to 10 bit data. Mux  342 B sends the 10-bit data to a smoothing FIFO (“TxSMF”) module  342  that handles clock variation on the transmit side. SERDES  343  then sends the data out to the link. 
     Credit Limiting Feature: 
     In one aspect of the present invention, a transmit queue in TTAG  330  (in TPORT  311 A and/or  311 ) uses a Quality of Service (QOS) register  512  ( FIG. 5 ) that can be programmed by IOP  66  to enable frame transmission based on the innovative credit limiting feature of the present invention. When used for credit limiting, QOS register  512  can be programmed with the number of R_RDY signals each queue has to wait to be received after transmitting two frames. 
       FIG. 5  shows a schematic of logic  500  that is used for using credit limitation as a parameter to avoid frame congestion in a fibre channel switch. Logic  500  is to illustrate the adaptive aspects of the present invention and not to limit the present invention to the logic scheme of  FIG. 5 . 
     Credit counter  328 A counts the number of credits that are outstanding without receiving a corresponding R_RDY  510 . The value of credit counter  328 A at a given time is compared by logic  501 A to threshold value  501 , for example, “0003”. If the counter  328 A value is greater than or equal to the threshold value  501 , then the result is used to enable the “credit limiting” feature of the present invention. This feature may be cleared by using signal  507  at a pre-determined time interval, for example, 10 milli-seconds, as shown in  FIG. 5 . It is noteworthy that the present invention is not limited to any particular time interval. 
     Routing frames using the credit-limiting feature is enabled by setting a bit  508  in control register  326  and using a start counter  503  that counts when a frame departs based on input  502 . The start counter  503  increments to its maximum value, and hold this maximum value for as long as the threshold value  501  comparison permits. With the start counter at the maximum value, logic  504  and  505  are used to generate a “Credit_Limiting_State” signal  506  that enables the use of “credit limiting” for frame transmission. Based on signal  506 , the credit_limiting bit  508  is set in control register  326 , which enables logic  515  to block frame transmission at a port, based on available credit (i.e. “credit limiting” feature). Logic  515  exists for each source FIFO in TTAG  330 . 
     Blocking counter  511  receives bit  508  from control register  326 , frame depart signal  502  and counts the number of R_RDYs  510  or VC_RDYs  509  that are received by the port, since the last frame that was sent by the port. Counter  511  increments when a R_RDY  510  (or VC_RDY  509 ) is received (unless the counter is at its maximum value) and cleared based on input  502 /and when the counter is at its maximum value. 
     QOS register  512  can be programmed with a particular threshold value  512 A. This threshold value  512 A includes the number of R_RDYs  510  a port should receive after sending a frame from that source FIFO, before the next frame can be sent from the same FIFO. Threshold value  512 A is compared by logic  513  with counter value  511 A. If counter value  511 A is greater than or equal to QOS register value  512 A, then the frame is sent. If the counter value  511 A is less than QOS register value  512 A then a “block TTAG” signal  514  is generated that blocks frame transmission from that source FIFO. 
     It is noteworthy that counter  511  is not limited to being an incrementing counter with a “reset”. Counter  511  may be set to QOS register value  512 A when a frame is sent and is decremented when an R_RDY is received, unless the counter value  511 A is zero. In this case frames can be sent when counter  511  is at zero (i.e. transmit credit is at its maximum). 
     It is noteworthy that if virtual lanes are used, then VC_RDYs  509  are processed the same way as R_RDY  510 . 
     Process Flow: 
       FIG. 6  shows a process flow diagram by using the credit-limiting feature to reduce congestion in a Fibre Channel system. Turning in detail to  FIG. 6 , in step S 600 , the process enables the “credit-limiting” feature. As discussed above, this may be achieved by setting a bit  508  in control register  326 . This feature is enabled when congestion is detected at a port. 
     In step S 601 , the process compares received R_RDY  510  (or VC_RDY  509 ) value ( 511 A) with a programmed threshold value  512 A. If the counter value is equal or greater than threshold value  512 A, then in step S 602 , the frames are transmitted, or otherwise the frames are blocked. 
     As discussed above, the process for handling R_RDYs and VC_RDYs is the same. 
     Turning back to the example in  FIG. 2 , credit-limiting feature can be used for port  204  to improve performance. QOS register  512  in port  204  for source port  202  can be set to 7, while the QOS register  512  at port  204  from source port  201  can be set to zero. This will result in twice as many frames being sent from host  201  as from host  202  (with the slow destination, target  208 ). Hence frames for target  208  will arrive at port  205  at a slow enough rate that they can be sent to the destination as fast as they arrive. This will allow link  209  to operate at full speed. 
     Although the present invention has been described with reference to specific embodiments, these embodiments are illustrative only and not limiting. Many other applications and embodiments of the present invention will be apparent in light of this disclosure and the following claims.