Abstract:
The invention provides voltage potential differences for selectively discharging cells in a plasma display device, with greater brightness and reduced power consumption. The plasma display device has orthogonally related electrodes sealed in an atmosphere of neon gas. When a predetermined potential is applied between two intersecting electrodes, the neon gas glows at the intersection. The predetermined potential is achieved by applying two pulse trains which have opposite phases and therefore oppositely going voltage polarities. The difference in the oppositely going peak voltages of the two pulse trains provides a firing potential at the selected intersection. To decrease the voltage causing an erroneous discharge, a short period of an extinction mode is introduced before an address mode. In another embodiment, to reduce power consumption, the cell at the intersection is fired at a high potential during an address mode and thereafter held in a glowing state by a greatly reduced voltage. Another embodiment produces a similar result by changing the frequency of driving pulses in the firing and the holding modes.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a plasma display apparatus and more particulary to a drive of AC refresh-type plasma display panel. 
     A typical example of a conventional AC refresh-type plasma display panel (PDP) to be used in the present invention includes two glass plates having electrode groups which are coated with a dielectric layer. The two glass plates are arranged in a manner which makes electrodes of respective glass plates opposed to each other. Electrodes on each glass plate intersect each other perpendicularly to form a matrix display type. The glass plates are sealed air-tightly with glass frits. Neon gas is filled in the sealed space so as to exist between the glass plates. 
     When the driving circuit applies a pulsed voltage to electrodes on only one glass plate while maintaining the electrodes on the other glass plate at potential zero, discharge occurs between electrodes to display an image. The voltage discharged at the cell which is the most easy to discharge within the PDP is defined as the minimum unilateral discharge voltage (VDmin). The voltage discharged at the cell which is the most unlikely to discharge within the PDP is defined as the maximum unilateral discharge voltage (VDmax). If electrodes on one glass plate of the PDP have a first pulse train applied thereto with a high voltage (V0) which is higher than VDmin but lower than VDmax while the electrodes on the other glass plate have a second pulse train applied thereto with a low voltage (V1) which has a phase same as or opposite to the first pulse train, the discharge does not occur when the relation holds; VDmin&gt;|V0|-|V1|and discharge occurs when the relation holds; VDmax &lt;|V0|+|V1|. 
     U.S. Pat. No. 3,869,644 issued on Mar. 4, 1975 discloses a phase-select method using the above condition as one example of the prior art AC refresh-type driving circuits for plasma display panels (PDP). In this prior art driving circuit, a first pulse train of high voltage is applied to scanning electrodes on one glass plate in a time division mode. A second pulse train of low voltage, having the phase opposite to the phase of the first pulse train, is applied to selected data electrodes of selected cells, on the other glass plate. In addition, a third pulse train of low voltage having the phase which is the same as the phase of the first pulse train is applied to remaining data electrodes of non-selected cells so as not to discharge the non-selected cells, thereby securing a stable operation. 
     In this prior art driving circuit, however, driving circuits are electrically connected via stray capacities between adjacent data electrodes provided on the substrate of PDP. When the adjacent data electrodes are driven for discharging and non-discharging concurrently, the power consumption of the driving circuits for the adjacent data electrodes becomes maximum. Although the brightness of an AC refresh-type PDP is determined by the number of pulses contained in a unit time, the larger the number of pulses becomes, the larger the power consumption of the driving circuits becomes. Thus the restrictions on the driving frequency present a formidable obstacle in obtaining sufficient brightness. 
     The prior art driving circuit is further detrimental in that if there is a mismatch in time on high frequency pulses between voltages applied to the scanning electrodes and the data electrodes, the range of the driving voltage becomes narrow. 
     Moreover, if transparent electrodes are used for data electrodes, a distributed constant circuit is formed via stray capacity between the transparent electrodes. As the waveforms and voltages at a tip end of the transparent electrodes differ from the waveforms and voltages at an input end, the brightness fluctuates unevenly. This also causes a delay in time and changes in voltage between the first pulse train for the scanning side and the second and third pulse trains for the data side. The range of driving voltage inconveniently becomes narrower. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of this invention to provide a plasma display apparatus which display an image with a high level of brightness, small power consumption and a larger operating range. 
     It is another object of this invention to provide a driving method of plasma display panels for obtaining an improved brightness, power consumption and operating range. 
     According to this invention, the driving pulses applied to either selected cells or non-selected cells during one scanning cycle includes a period of an address mode pulses and a period of an extinction mode pulses before the address mode pulse period. In the address mode period, a potential difference larger than VD max  is applied by the address mode pulses to discharge the selected cells while a potential difference smaller than VD min  is applied to not discharge the non-selected cells. In the extinction mode period, on the other hand, the potential difference smaller than VD min  is applied by the extinction mode pulses not to discharge both the selected cells and non-selected cells. In another embodiment, the one scanning cycle further includes a period of a hold mode period after the address mode period. In this hold mode period, the potential difference applied to both the selected cells and the non-selected cells is reduced, but the potential difference has the same amplitude which is such that the selected cells can continue in the discharge stage while the non-selected cells requires enough time to start a discharge. 
     The time delay may vary depending on the amplitude of the potential difference, but generally becmes 5 micro sec. or more in the AC refresh-type method. The response to a discharge is extremely fast, once it is started, an is less than 100 nano sec. due to ions and electrons filled in the selected cells. The present invention uses this phenomenon of discharge jitter. More particularly, the address mode can be obtained by applying pulse train of low voltage to a data electrode with the phase opposite to or identical with the pulse train of high voltage applied to a scanning electrode. The extinction mode can be obtained by applying several pulses of low voltage to all data electrodes with the phase identical with the pulse train of the high voltage applied to the scanning electrode. The hold mode can be obtained by applying a DC voltage to the data electrode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A to 1E are waveform diagrams showing a relationship between the voltages applied to a scanning electrode and data electrodes, according to a first preferred embodiment of this invention. 
     FIGS. 2A to 2E are waveform diagrams showing a pulse train applied at scanning electrodes in a time-division mode. 
     FIGS. 3A to 3E are waveform diagrams showing a relationship between the voltage applied to a scanning electrode and data electrodes, according to a second preferred embodiment of this invention. 
     FIGS. 4A to 4E are waveform diagrams showing a relationship between the voltages applied to a scanning electrode and data electrodes, according to a third preferred embodiment of this invention. 
     FIG. 5 is a block diagram of a driving circuit for a plasma display panel according to the first preferred embodiment of this invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 1, while a first pulse train of peak voltage V 0  is applied to the first scanning or row electrode for one scanning period Th, as shown in FIG. 1A, a second pulse train of peak voltage V 1  is applied to the mth data or column electrode for a period Ta which is shorter than the period Th as shown in FIG. 1B. Following the pulse train for the period Ta, a direct current voltage is applied to the mth column electrode for a period Tb as shown in FIG. 1B. Preceding the pulse train for the period Ta, a third pulse train peak voltage V 1  is applied to the mth column electrode for a period Tc which is shorter than the period Ta as shown in FIG. 1B. The period represented by the letter T BL  in FIG. 1 is a blanking period. Thus the sum of the periods, Ta+Tb+Tc+T BL , indicates the one scanning period Th. 
     As is shown in FIG. 1B, the second pulse train has a phase which is opposite to the phase of the first pulse train so as to produce a first pulsing potential difference shown in FIG. 1D. This first potential difference is larger than the firing voltage of the selected cell which is formed at the intersection of the first row electrode and the mth column electrode. The third pulse train has a phase which is identical with the phase of the first pulse train, as shown in FIG. 1B, so as to produce a second pulsing potential difference shown in FIG. 1D. This second potential difference is smaller than a holding voltage of a selected cell which is formed at the intersection of the first row electrode and the mth column electrode. When the nth column electrode is associated with a non-selected cell which is not to be discharged, a fourth pulse train of peak voltage V 1  is applied to the nth column electrode for the periods Ta and Tc with a phase which is identical with the phase of the first pulse train as shown in FIG. 1C. During the period Tb, the nth columnm electrode also has a direct current voltage applied thereto. FIG. 1E shows the potential difference applied to a non-selected cell formed at the intersection of the first row electrode with the nth column electrode. 
     The operation during the period Ta, in the one scanning period Th, is identical to the operation disclosed in the aforementioned U.S. Pat. No. 3,869,644. The period Ta is defined herein as an address mode. The potential difference V 0 , which is applied to the selected cells and non-selected cells during the period Tb in the one scanning period Th, are completely identical to each other, as shown in FIGS. 1D and 1E. This period is referred herein as a hold mode. 
     At the address mode, if the relations set forth below hold, the selected cells which are to glow are discharged and the non-selected cells which are not to glow are not discharged; 
     
         VDmax&lt;|V1|+|V0|        (1) 
    
     
         VDmin&gt;|V0|-|V1|        (2) 
    
     In the hold mode, the potential difference V 0  is applied irrespective of whether the cells are to glow or not to glow. The cells maintain the state which is created at the address mode which preceded the hold mode. 
     More particularly, as the selected cell is discharged at the period Ta, the selected cell is filled with charged particles generated by the discharge; thus, the following discharge is easily actuated even in the hold mode where the potential difference which is applied is lower than the potential difference which is applied in the address mode. 
     Since the non-selected cell is not discharged in the address mode period Ta, the non-selected cell is not filled with charged particles. Therefore, it takes a certain time before the non-selected cell starts to discharge in the subsequent period Tb, with the potential difference V 0 . Accordingly, if a suitable period is selected, for instance, at 20 micro second or less for the period Tb, it is possible to determine the voltage which will not start a discharge at the hold mode. 
     Next, the explanation will be given on the period Tc in FIG. 1. This period Tc is referred herein as an extinction mode. Since the same pulse is applied to all the column electrodes in this period, the influences of the stray capacitance between the colunm electrodes can be neglected. And thus the difference between voltage and waveform at the output of the driving circuit and voltages and waveform at the tip portions of the electrodes become small. Furthermore, since all the discharge cells stop discharge in this period Tc, pick-up of discharge from the adjacent cells is eliminated. After all, when compared with the conventional driving system, the cells which should discharge in the address mode in the period Ta, an initial discharge is a little bit difficult to occur due to the extinction mode of the period Tc. However, since discharge stops completely in the period Tc, the non-selected cells do not pick up discharge from the adjacent selected cells. In other words, the voltage which causes erroneous discharge becomes higher in the aspect of display so that a driving voltage can be made higher. Generally, when the pulse frequency is increased, it becomes more difficult to eliminate the time deviation between the pulse voltages applied to row and column electrodes due to the speed of the switching operation generating the output state of the driving voltage, and the voltage causing the erroneous discharge becomes lower. In accordance with the present invention, however, although a voltage for the erroneous discharge becomes higher due to the existance of the extinction mode for the period Tc and thus display brightness can be improved. 
     Needless to say, in order to drive a conventional plasma display panel, the scanning electrode group is selected for the period T h  with the horizontal synchronizing signals shown in FIG. 2E. The first electrodes have a pulse train applied thereto with the peal value of V 0  shown in FIG. 2A. After a certain period (blanking period), the second scanning electrode is selected. The pulse voltage having the peak value of V 0  is applied to the second scanning electrode only for the period T h . (Refer to FIG. 2B.) The third scanning electrode has a pulsed voltage applied thereto after a pulsed voltage is applied to the second scanning electrode. This operation is repeated sequentially until the time when vertical snychronizing signal arrives or for the period T v . The circuit then returns to the state which allows a selection of the first scanning electrode when the vertical synchronizing signal arrives. 
     According to this invention, each of the scanning electrodes is sequentially scanned with horizontal synchronizing signals. The circuit is returned to the initial state with a vertical synchronizing signal which is inputted after all the scanning electrodes are scanned. The vertical synchronizing signal is coincidental to the refresh frequency in display and generally is determined as being 55 cycles or higher. 
     An example will be described below for the case wherein a plasma display panel having display cells of 640 ×400 dots is driven by the aforementioned driving method. 
     The applied voltage V 0  shown in FIG. 1A was set at 180 V, its frequency at 800 KHz. the applied voltage V 1  in FIGS. 1B, and 1C were set at 30 V, their frequency at 800 KHz, the period Ta at 20 micro sec., and the period T b  at 10 micro sec. The period T c  contains several pulses. The plasma display panel shows stable performance without erroneous discharge to obtain the following results: 
     
         ______________________________________     Prior art   This invention     Phase-select method                 method______________________________________Power       40 W          28 WBrightness  10 fL         9.4 fL______________________________________ 
    
     When the address mode at the period T a  and the hold mode at the period T b  have the same frequency, the power consumption will be decreased by an increase of the period T b , but this inevitably entails a decrease in brightness. It is, therefore, preferable to design the period T b  shorter than the period T a  in view of brightness. 
     A description will now be given of an example which can reduce the power consumption and still increase the brightness. 
     FIG. 3 shows arrangement of pulse trains of the second embodiment. 
     FIG. 3A shows a pulse trains of peak voltage V 0  applied on the scanning electrodes at the Nth row in a plasma display panel. 
     FIG. 3B shows a pulse train of peak voltage V 1  applied on the data electrodes of the mth colunm. FIG. 3C shows the pulse train of peak voltage V 1  applied on the data electrodes of the nth column. 
     FIG 3D shows the pulsed potential difference applied on the selected (the Nth row, the mth column) cells defined at the intersections of the Nth row electrodes and the mth electrodes. FIG. 3E shows the pulsed potential difference applied on the non-selected (Nth row, the nth column) cells formed at the intersections of the Nth row electrodes and the nth colunm electrodes. 
     In the drawings, the period represented by the letter T BL  is the blanking time while the period represented by the letter T a  is the time when a display is made in the address mode. The period represented by the letter T b  is the time when a display is made in the hold mode. The period represented by the letter T c  is the time when a display is made extinct. The sum of the periods, T a  +T b  +T c  +T BL , indicates one scanning time T h  where one scanning electrode is being selected. 
     An example where a plasma display panel having the display points of 640×400 dots is driven with the pulsed voltages shown in FIG. 3 is described below. 
     When the voltage V 0  shown in FIG. 3A was set at 170 V, the frequency in the address mode and the extinction mode at 500 KHz, the frequency in the hold mode at 2 MHZ, the voltage V 1  shown in FIGS. 3B and 3C at 30 V, its frequency in the address mode and the extinction mode at 500 KHz, and the frequency in the hold mode in DC, the panel showed a stable operation. 
     The following table shows the comparison of the power consumption and brightness of the plasma display panel driven by this invention method under the above conditions, and the plasma display panel driven by the prior art phase-select method (driven by 800 KHz). 
     
         ______________________________________        Power consumption                     Brightness______________________________________Phase-select method          40 W           10 fLThis invention method          15 W           12 fL______________________________________ 
    
     The power consumption and brightness changed in proportion to the ratio between the time period T a  in address mode and the period T b  in hold mode in FIG. 3. The ratio was set at 1:2 in the above example. 
     In the second example, the power consumption can be reduced. At the same time, the brightness can be increased by increasing the frequency in the hold mode. The frequency during the periods T a  and T c  may be selected from the range of 400 KHz to 600 KHz. The frequency for the period T b  may be selected from the range of 1.5 MHz to 3 MHz. It is preferable that the duration of the period T b  is 1 to 2.5 times the duration of the period T a . The period T c  should be smaller than the periods T a  and T b  such that the period T c  contains only several pulses so as not to disturb a display quality. Only one pulse for the extinction mode can work and it is desired that the period T c  is less than half of the period T a . 
     While the brightness can be improved by increasing the frequency in the hold mode, it is possible to apply a waveform which is substantially the same as the output waveform of the circuit to an entire region of the panel by further reducing the frequency in the periods T a  and T c  to be lower than the time constant formed by the stray capacitance between the column electrodes. Thus, there is obtained the effect that the operation gets stabilized. Although pulses having a smaller width are depicted in FIG. 3B after the extinction pulse, this is irrelevant to the present intension, and there is obtained the result that the driving voltage is within the same range irrespective of the existence of such narrow pulses. 
     FIG. 4A to FIG. 4E are a timing chart showing the voltage arrangement of the third embodiment of the present invention. This embodiment is the same as the first and second embodiments except that the hold mode is eliminated. FIG. 4A to FIG. 4E show the pulse train of peak voltage V 0  applied to the scanning electrode in the 1st row for one scanning period T h . As shown in the drawing, the period T a  is an address mode, and the period T c  a extinction mode, and the period T BL  a blanking mode. As described with reference to the first and second embodiments, since the range of the driving voltage can be expanded and enhanced in this embodiment, plasma displays that have conventionally been rejected as defective products because the initial discharge voltage of certain dots is higher than that of others by one to two volts due to variance of plasma display panels can now be used. Therefore, the production yield can be improved. 
     FIG. 5 is a block diagram showing a plasma display system according to the present invention. The plasma display system comprises a matrix display type of plasma display panel 1, a driving circuit for the row electrode group 2, a driving circuit for the column electrode group 3, a latch circuit 4 for storing data, a shift register 5 for storing data temporarily, and a shift register 6 for sequentially shifting row electrodes. 
     The pulse train of peak voltage V 0  which is to be applied at row electrodes is generated by a complementary inverter circuit at the last stage of the driving circuit 2 and has the peak value of V 0 . The input signals of this circuit 2 are the output from the shift register 6 and the high frequency pulse signal 10 which is inputted from the outside and which are mixed at an AND gate. The output signal of the AND gate is amplified upto the value of high voltage source V 0  by the inverter circuit. Thus, the high frequency pulse signal which is inputted from outside and the output from the driving circuit 2, at the last stage, have the same frequency of opposite phases. The shift register 6 receives scanning data signal 11 and scanning clock signal 12 as input. The scanning data signal 11 is sequentially transferred by the scanning clock signal 12 to the AND gate in the driving circuit 2. 
     The column electrodes driving circuit 3 comprises a complementary inverter circuit which receives the output from an exclusive OR circuit as an input which is to be inverted at the driving circuit. The data inputted at the shift register 5 via the dot data input 17 and the data shift clock signal 18 are transmitted to the latch circuit 4 by a latch pulse signal 16. Each latch output is inputted to an AND circuit in the driving circuit 3 and is mixed with a blanking signal 19 on the data side that is inputted from outside. This blanking signal is normally at a high level but when this signal is switched to a low level, the output of the NAND circuit can be fixed to the high level in the same way as when the data does not exist, irrespective of the existence of the output of the latch 4. The output of this NAND circuit is further inputted at the exclusive OR circuit in the driving circuit 3 to be mixed with the high frequency pulse signal 15 which is inputted from outside. If there is not output from the latch circuit 4, the output from the exclusive OR circuit has a phase which is opposite to the phase of the high frequency pulse signal 15 which is inputted from outside. The high frequency pulse 15 is then amplified up to the value of voltage source V 1 , by the inverter circuit. Thus, the pulse train obtained from the column electrodes driving circuit 3 has a phase which is the same as the phase of the high frequency pulse signal 15. Conversely, if there is an output from the latch circuit 4, the output from the exclusive OR circuit has a phase which is identical to the phase of the high frequency pulse signal 15, inputted from outside. The pulse train in the output circuit has the phase opposite thereto. 
     The DC voltage needed for a hold mode can be obtained by converting the high frequency pulse signal 15 to a DC signal. The conversion in frequency which is necessary for the hold mode, as in the second preferred embodiment, may be conducted by switching the frequency of the high frequency pulse signal 10 that is inputted from outside. 
     According to the present invention, since all the discharge cells stop discharge in the short period T C  of the extinction mode, pick up of discharge from the adjacent cells is eliminated, and thus the voltage which causes erroneous discharge becomes higher. Moreover, the power consumed is remarkably reduced in the period while the voltage is entirely irrelevant to the waveform applied to the scanning electrodes or while the direct current voltage is applied to the data electrodes. This reduction occurs because the power consumed between adjacent data electrodes becomes negligible. 
     Further the driving becomes stable with a smaller power consumption in this inventive circuit by lowering driving frequency for the period of driving which is similar to the phase-select method, and by increasing the frequency of the period when DC voltage is being applied to data electrodes. In the foregoing description, the extinction mode is separated from the blanking period, but the extinction mode may be located in the blanking period.