Abstract:
In a signal determining apparatus including an amplifier circuit adapted to receive and amplify an input signal to generate an output voltage, and a comparator adapted to compare the output voltage of the amplifier circuit with a reference voltage to generate an output signal, the amplifier circuit has variable response speed characteristics so that a response speed of the amplifier circuit is controlled during its amplifying operation.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a signal determining apparatus for receiving and amplifying an input signal such as a photocurrent signal and comparing the amplified input signal with a reference voltage.  
         [0003]     2. Description of the Related Art  
         [0004]     Generally, in a signal determining apparatus, an amplifier circuit is provided to receive and amplify an input signal such as a photocurrent signal to generate an output voltage, and a comparator is provided to compare the output voltage of the amplifier circuit with a reference voltage to generate an output signal. In this case, a response speed of the amplifier is constant (see: JP-2003-139608-A). This will be explained later in detail.  
         [0005]     In the above-described prior art signal determining apparatus, when the response speed is relatively low, since a so-called ringing phenomenon such as an overshoot phenomenon or an undershoot phenomenon hardly occurs in the output voltage of the amplifier circuit, spurious waveforms would not appear in the output voltage of the comparator. However, when the response speed is relatively high, since a so-called ringing phenomenon such as an overshoot phenomenon or an undershoot phenomenon occurs in the output voltage of the amplifier circuit, spurious waveforms would appear in the output voltage of the comparator. This would invite a malfunction.  
       SUMMARY OF THE INVENTION  
       [0006]     It is an object of the present invention to provide a signal determining apparatus including an amplifier circuit operable at high response speed, capable of suppressing the generation of spurious waveforms.  
         [0007]     According to the present invention, in a signal determining apparatus including an amplifier circuit adapted to receive and amplify an input signal to generate an output voltage, and a comparator adapted to compare the output voltage of the amplifier circuit with a reference voltage to generate an output signal, the amplifier circuit has variable response speed characteristics so that a response speed of the amplifier circuit is changed during its amplifying operation. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0009]      FIG. 1  is a circuit diagram illustrating a prior art signal determining apparatus;  
         [0010]      FIG. 2  is a detailed circuit diagram of the amplifier of  FIG. 1 ;  
         [0011]      FIGS. 3A, 3B  and  3 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 1  where the response speed is relatively low and the reference voltage is relatively low;  
         [0012]      FIGS. 4A, 4B  and  4 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 1  where the response speed is relatively low and the reference voltage is relatively high;  
         [0013]      FIGS. 5A, 5B  and  5 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 1  where the response speed is relatively high and the reference voltage is relatively low;  
         [0014]      FIGS. 6A, 6B  and  6 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 1  where the response speed is relatively high and the reference voltage is relatively high;  
         [0015]      FIG. 7  is a circuit diagram illustrating a first embodiment of the signal determining apparatus according to the present invention;  
         [0016]      FIGS. 8A, 8B  and  8 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 7 ;  
         [0017]      FIG. 9  is a circuit diagram illustrating a second embodiment of the signal determining apparatus according to the present invention;  
         [0018]      FIGS. 10A, 10B  and  10 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 9 ;  
         [0019]      FIGS. 11 and 12  are circuit diagrams illustrating modifications of the signal determining apparatuses of  FIGS. 7 and 9 , respectively;  
         [0020]      FIGS. 13 and 14  are circuit diagrams illustrating other modifications of the signal determining apparatuses of  FIGS. 7 and 9 , respectively;  
         [0021]      FIG. 15  is a circuit diagram illustrating a third embodiment of the signal determining apparatus according to the present invention;  
         [0022]      FIGS. 16A, 16B  and  16 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 15 ;  
         [0023]      FIG. 17  is a circuit diagram illustrating a fourth embodiment of the signal determining apparatus according to the present invention;  
         [0024]      FIGS. 18A, 18B  and  18 C are timing diagrams for explaining the operation of the signal determining apparatus of  FIG. 17 ; and  
         [0025]      FIG. 19  is a circuit diagram illustrating a modification of the amplifier of  FIGS. 7, 9 ,  11 ,  12 ,  13 ,  14 ,  15  and  17 . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]     Before the description of the preferred embodiments, a prior art signal determining apparatus will be explained with reference to  FIGS. 1, 2 ,  3 A,  3 B,  3 C,  4 A,  4 B,  4 C,  5 A,  5 B,  5 C,  6 A,  6 B and  6 C (see: JP-2003-139608-A).  
         [0027]     In  FIG. 1 , which illustrates a prior art signal determining apparatus, a photocoupler  1  is constructed by a light emitting diode (LED)  11  and a photodiode  12 . That is, when an input current I in  is supplied to the LED  11 , the LED  11  generates a light signal indicated by an arrow, so that the photodiode  12  receives the light signal so that a photocurrent I pd  flows therethrough in response to the input current I in .  
         [0028]     The photocurrent I pd  is amplified by an amplifier  3  with a negative feedback resistor  3   a  connected between the output and input thereof. The input of the amplifier  3  is connected to the cathode of the photodiode  121 . The amplifier  3  generates an output voltage V a  in response to the photocurrent I pd . Note that the amplifier  3  generates a definite voltage V 0  when no photocurrent I pd  flows.  
         [0029]     The amplifier  3  and the feedback resistor  3   a  form an amplifier circuit.  
         [0030]     On the other hand, a reference voltage generating circuit  4  generates a reference voltage V ref , In this case, V ref &gt;V 0 , and V ref &lt;V a  when the photocurrent I pd  flows. The output voltage V a  of the amplifier  3  and the reference voltage V ref  of the reference voltage generating circuit  4  are supplied to inverting and non-inverting inputs, respectively, of a comparator  5 . Therefore, when V a ≦V ref , the output signal V out  of the comparator is high (=“1”). On the other hand, when V a &gt;V ref , the output signal V out  of the comparator is low (−“0”).  
         [0031]     In  FIG. 2 , which is a detailed circuit diagram of the amplifier  3  of  FIG. 1 , first, second and third amplifier stages are serially-connected. That is, the first amplifier stage is constructed by an N-channel MOS transistor  31  with a grounded source and a gate connected to the cathode of the photodiode  12 , and a current source  32  connected between the drain of the MOS transistor  31  and a power supply terminal V DD . In this case, a node N 1  between the drain of the MOS transistor  31  and the current source  32  serves as an output node of the first amplifier stage. Also, the second amplifier stage is constructed by an N-channel MOS transistor  33  with a grounded source and a gate connected to the node N 1 , and a current source  34  connected between the drain of the MOS transistor  33  and the power supply terminal V DD . In this case, a node N 2  between the drain of the MOS transistor  33  and the current source  34  serves as an output node of the second amplifier stage. Further, the third amplifier stage is constructed by an N-channel MOS transistor  33  with a grounded source and a gate connected to the node N 2 , and a current source  36  connected between the drain of the MOS transistor  35  and the power supply terminal V DD . In this case, a node N 3  between the drain of the MOS transistor  35  and the current source  36  serves as an output node of the third amplifier stage, i.e., the output of the amplifier  3 .  
         [0032]     Note that the above-mentioned definite voltage V 0  is determined by a threshold voltage of the MOS transistor  31 .  
         [0033]     In  FIG. 1 , when there is no input current I in , there is no photocurrent I pd . As a result, the output voltage V a  of the amplifier  3  is made to be V 0 , so that V a =V 0 &lt;V ref . Therefore, the output voltage V out  of the comparator  5  is made to be high (=“1”). On the other hand, when an input current I in , i.e., a photocurrent I pd  flows, the output voltage V a  of the amplifier  3  is made to be higher than V ref , i.e., 
 
 V   a   =V   0   +I   pd   ·R   f   &gt;V   ref  
        where R f  is a resistance value of the feedback resistor  3   a , the output voltage V out  of the comparator  5  is made to be low (=“0”).        
 
         [0035]     Thus, the output signal V out  of the comparator  5  is “1” or “0” in accordance with the photocurrent I pd , i.e. the input current I in .  
         [0036]     The operation of the signal determining apparatus of  FIG. 1 , where the response speed is relatively low and the reference voltage V ref  is relatively low (V ref ≈V 0 ), will be explained next with reference to  FIGS. 3A, 3B  and  3 C.  
         [0037]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 3A , the output voltage V a  of the amplifier  3  is gradually changed as illustrated in  FIG. 3B . As a result, the output voltage V out  of the comparator  5  is changed with delay times Δt 1  and Δt 2  as illustrated in  FIG. 3C . In this case, since V ref  is relatively low, Δt 1 &lt;Δt 2 .  
         [0038]     The operation of the signal determining apparatus of  FIG. 1 , where the response speed is relatively low and the reference voltage V ref  is relatively high (V ref &gt;&gt;V 0 ), will be explained next with reference to  FIGS. 4A, 4B  and  4 C.  
         [0039]     When the input current in (or the photocurrent I pd ) is changed as illustrated in  FIG. 4A , the output voltage V a  of the amplifier  3  is gradually changed as illustrated in  FIG. 4B . As a result, the output voltage V out  of the comparator  5  is changed with delay times Δt 1  and Δt 2  as illustrated in  FIG. 4C . In this case, since V ref  is relatively high, Δt 1 &gt;Δt 2 .  
         [0040]     In  FIGS. 3A, 3B  and  3 C and  FIGS. 4A, 4B  and  4 C, since a so-called ringing phenomenon such as an overshoot phenomenon or an undershoot phenomenon hardly occurs in the output voltage V a  of the amplifier  3 , spurious waveforms would not appear in the output voltage V out  of the comparator  5 .  
         [0041]     The operation of the signal determining apparatus of  FIG. 1 , where the response speed is relatively high and the reference voltage V ref  is relatively low (V ref ≈V 0 ), will be explained next with reference to  FIGS. 5A, 5B  and  5 C.  
         [0042]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 5A , the output voltage V a  of the amplifier  3  is rapidly changed as illustrated in  FIG. 5B . As a result, when the output voltage V a  of the amplifier  3  rises, an overshoot phenomenon as indicated by X 1  in  FIG. 5B  appears therein. Similarly, when the output voltage V a  of the amplifier  3  falls, an undershoot phenomenon as indicated by X 2  in  FIG. 5B  appears therein. Therefore, since the reference voltage V ref  is relatively low, the output signal V out  of the comparator  5  is hardly affected by the overshoot phenomenon X 1 ; however, the output signal V out  of the comparator  5  is strongly affected by the undershoot phenomenon X 2 , so that the output signal V out  of the comparator  5  chatters to generate spurious waveforms as indicated by Y 2  in  FIG. 5C .  
         [0043]     The operation of the signal determining apparatus of  FIG. 1 , where the response speed is relatively high and the reference voltage V ref  is relatively high, will be explained next with reference to  FIGS. 6A, 6B  and  6 C.  
         [0044]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 6A , the output voltage V a  of the amplifier  3  is rapidly changed as illustrated in  FIG. 6B . As a result, when the output voltage V a  of the amplifier  3  rises, an overshoot phenomenon as indicated by X 1  in  FIG. 6B  appears therein. Similarly, when the output voltage V a  of the amplifier  3  falls, an undershoot phenomenon as indicated by X 2  in  FIG. 6B  appears therein. Therefore, since the reference voltage V ref  is relatively high, the output signal V out  of the comparator  5  is hardly affected by the undershoot phenomenon X 2 ; however, the output signal V out  of the comparator  5  is strongly affected by the overshoot phenomenon X 1 , so that the output signal V out  of the comparator  5  chatters to generate spurious waveforms as indicated by Y 1  in  FIG. 6C .  
         [0045]     In  FIGS. 5A, 5B  and  5 C and  FIGS. 6A, 6B  and  6 C, since a so-called ringing phenomenon such as an overshoot phenomenon or an undershoot phenomenon occurs in the output voltage V a  of the amplifier  3 , spurious waveforms would appear in the output voltage V out  of the comparator  5 .  
         [0046]     In  FIG. 7 , which illustrates a first embodiment of the signal determining apparatus according to the present invention, a drain-to-gate connected N-channel MOS transistor  3   b  serving as a load and an N-channel MOS transistor  3   c  serving as a switching element controlled by the output voltage V out  of the comparator  5  are connected in series between the output of the amplifier  3  and the ground terminal GND. That is, when the output voltage V out  of the comparator  5  is low (=“0”), the switching MOS transistor  3   c  is turned OFF to disconnect the load MOS transistor  3   b  from the amplifier  3 , so that the amplifier  3  can operate at a high response speed. On the other hand, when the output voltage V out  of the comparator  5  is high (=“1”), the switching MOS transistor  3   c  is turned ON to connect the load MOS transistor  3   b  to the amplifier  3 , so that the amplifier  3  can operate at a low response speed.  
         [0047]     The amplifier  3 , the feedback resistor  3   a , the load MOS transistor  3   b  and the switching MOS transistor  3   c  form an amplifier circuit.  
         [0048]     In  FIG. 7 , assume that the reference voltage V ref  is relatively low, i.e., V ref ≈V 0 .  
         [0049]     The operation of the signal determining apparatus of  FIG. 7  will be explained next with reference to  FIGS. 8A, 8B  and  8 C.  
         [0050]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 8A , the output voltage V a  of the amplifier  3  is changed as illustrated in  FIG. 8B , and the output voltage V out  of the comparator  5  is changed as illustrated in  FIG. 8C .  
         [0051]     In more detail, before time t 1 , the input current I in  (the photocurrent I pd ) is zero, so that the output voltage V a  of the amplifier  3  is V 0 . In this case, the output voltage V out  of the comparator  5  is high (=“1”), so that the switching MOS transistor  3   c  is turned ON. Therefore, the amplifier  3  with the load MOS transistor  3   b  can operate at a low response speed.  
         [0052]     At time t 1 , the input current I in  (the photocurrent I pd ) rises to increase the output voltage V a  of the amplifier  3 .  
         [0053]     Next, at time t 2 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from high (=“1”) to low (=“0”). As a result, the switching MOS transistor  3   c  is turned OFF, so that the amplifier  3  without the load MOS transistor  3   b  can operate at a high response speed. In this case, although an overshoot phenomenon as indicated by X 1  in  FIG. 8B  in the same way as in  FIG. 5B  appears in the output voltage V a  of the amplifier  3 , this overshoot phenomenon X 1  does not affect the output voltage V out  of the comparator  5  due to the low reference voltage V ref .  
         [0054]     Next, at time t 3 , the input current I in  (the photocurrent I pd ) falls to decrease the output voltage V a  of the amplifier  3 .  
         [0055]     Next, at time t 4 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from low (=“0”) to high (=“1”). As a result, the switching MOS transistor  3   c  is turned ON, so that the amplifier  3  with the load MOS transistor  3   b  can operate at a low response speed. Even in this case, an undershoot phenomenon as indicated by X 2 ′ appears in the output voltage V a  of the amplifier  3 ; however, this undershoot phenomenon X 2 ′ is milder than the undershoot phenomenon X 2  in  FIG. 5B  due to the low response speed of the amplifier  3 . Therefore, this undershoot phenomenon X 2 ′ in  FIG. 8B  does not affect the output voltage V out  of the comparator  5 .  
         [0056]     In  FIG. 9 , which illustrates a second embodiment of the signal determining apparatus according to the present invention, an inverter  3   d  is connected between the output of the comparator  5  and the gate of the switching MOS transistor  3   c  of  FIG. 7 . That is, when the output voltage V out  of the comparator  5  is high (=“1”), the switching MOS transistor  3   c  is turned OFF to disconnect the load MOS transistor  3   b  from the amplifier  3 , so that the amplifier  3  without the load MOS transistor  3   b  can operate at a high response speed. On the other hand, when the output voltage V out  of the comparator  5  is low (=“0”), the switching MOS transistor  3   c  is turned ON to connect the load MOS transistor  3   b  to the amplifier  3 , so that the amplifier  3  with the load MOS transistor  3   b  can operate at a low response speed.  
         [0057]     In  FIG. 9 , assume that the reference voltage V ref  is relatively high, i.e., V ref &gt;&gt;V 0 .  
         [0058]     The operation of the signal determining apparatus of  FIG. 9  will be explained next with reference to  FIGS. 10A, 10B  and  10 C.  
         [0059]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 10A , the output voltage V a  of the amplifier  3  is changed as illustrated in  FIG. 10B , and the output voltage V out  of the comparator  5  is changed as illustrated in  FIG. 10C .  
         [0060]     In more detail, before time t 1 , the input current I in  (the photocurrent I pd ) is zero, so that the output voltage V a  of the amplifier  3  is V 0 . In this case, the output voltage V out  of the comparator  5  is high (=“1”), so that the switching MOS transistor  3   c  is turned OFF. Therefore, the amplifier  3  without the load MOS transistor  3   b  can operate at a high response speed.  
         [0061]     At time t 1 , the input current I in  (the photocurrent I pd ) rises to increase the output voltage V a  of the amplifier  3 .  
         [0062]     Next, at time t 2 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from high (=“1”) to low (=“0”). As a result, the switching MOS transistor  3   c  is turned ON, so that Fi the amplifier  3  with the load MOS transistor  3   b  can operate at a low response speed. Even in this case, although an overshoot phenomenon as indicated by X 1 ′ in  FIG. 10B  appears in the output voltage V a  of the amplifier  3 , this overshoot phenomenon X 1 ′ is milder than the overshoot phenomenon X 1  in  FIG. 6B  due to the low response speed of the amplifier  3 . Therefore, this overshoot phenomenon X 1 ′ does not affect the output voltage V out  of the comparator  5 .  
         [0063]     Next, at time t 3 , the input current I in  (the photocurrent I pd ) falls to decrease the output voltage V a  of the amplifier  3 .  
         [0064]     Next, at time t 4 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from low (=“0”) to high (=“1”). As a result, the switching MOS transistor  3   c  is turned OFF, so that the amplifier  3  without the load MOS transistor  3   b  can operate at a high response speed. In this case, although an undershoot phenomenon as indicated by X 2  in  FIG. 10B  in the same way as in  FIG. 6B  appears in the output voltage V a  of the amplifier  3 , this undershoot phenomenon X 2  does not affect the output voltage V out  of the comparator  5  due to the high reference voltage V ref .  
         [0065]     The signal determining apparatuses of  FIGS. 7 and 9  can be modified to those of  FIGS. 11 and 12 , respectively. In  FIGS. 11 and 12 , the feedback resistor  3   a  of  FIGS. 7 and 9  is replaced by a series of two resistors  3   a - 1  and  3   a - 2 , and the load MOS transistor  3   b  of  FIGS. 7 and 9  is replaced by a series of a resistor  3   b - 1  and a capacitor  3   b - 2 . Also, the series of the resistor  3   b - 1  and the capacitor  3   b - 2  is connected to a node between the resistors  3   a - 1  and  3   a - 2 . In  FIGS. 11 and 12 , a DC component never flows through the series of the resistor  3   b - 1  and the capacitor  3   b - 2 , which would decrease the power consumption as compared with the signal determining apparatuses of  FIGS. 7 and 9 .  
         [0066]     Note that the location of the node between the resistors  3   a - 1  and  3   a - 2  can be adjusted in consideration of a ringing phenomenon such as an overshoot phenomenon and an undershoot phenomenon in the output voltage V 8  of the amplifier  3 .  
         [0067]     Additionally, the signal determining apparatuses of  FIGS. 7 and 9  can be modified to those of  FIGS. 13 and 14 , respectively. In  FIGS. 13 and 14 , the input polarities of the comparator  5  are opposite to those of  FIGS. 7 and 9 . In  FIG. 13 , the inverter  3   d  is added to the elements of the signal determining apparatus of  FIG. 7 . On the other hand, in  FIG. 14 , the inverter  3   d  is deleted from the elements of the signal determining apparatus of  FIG. 9 .  
         [0068]     In  FIG. 15 , which illustrates a third embodiment of the signal determining apparatus according to the present invention, the power supply voltage VDD and the ground voltage GND of  FIG. 7  are interchanged with each other. In this case, the load N-channel MOS transistor  3   b  and the switching N-channel MOS transistor  3   c  of  FIG. 7  are replaced by a load P-channel MOS transistor  3   b ′ and a switching P-channel MOS transistor  3   c ′, respectively. In this case, the amplifier  3  is constructed by P-channel MOS transistors instead of the N-channel MOS transistors  31 ,  33  and  35  of  FIG. 2  (see:  FIG. 7  of JP-2003-139608-A).  
         [0069]     In  FIG. 15 , assume that the reference voltage V ref  is relatively high, i.e., V ref ≈V 0 .  
         [0070]     The operation of the signal determining apparatus of  FIG. 15  will be explained next with reference to  FIGS. 16A, 16B  and  16 C.  
         [0071]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 16A , the output voltage V a  of the amplifier  3  is changed as illustrated in  FIG. 16B , and the output voltage V out  of the comparator  5  is changed as illustrated in  FIG. 16C .  
         [0072]     In more detail, before time t 1 , the input current I in  (the photocurrent I pd ) is zero, so that the output voltage V a  of the amplifier  3  is V 0 . In this case, the output voltage V out  of the comparator  5  is low (=“0”), so that the switching MOS transistor  3   c ′ is turned ON. Therefore, the amplifier  3  with the load MOS transistor  3   b ′ can operate at a low response speed.  
         [0073]     At time t 1 , the input current I in  (the photocurrent I pd ) rises to increase the output voltage V a  of the amplifier  3 .  
         [0074]     Next, at time t 2 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from low (=“0”) to high (=“1”). As a result, the switching MOS transistor  3   c ′ is turned OFF, so that the amplifier  3  without the load MOS transistor  3   b ′ can operate at a high response speed. In this case, although an undershoot phenomenon as indicated by Z 1  in  FIG. 16B  appears in the output voltage V a  of the amplifier  3 , this undershoot phenomenon Z 1  does not affect the output voltage V out  of the comparator  5  due to the high reference voltage V ref .  
         [0075]     Next, at time t 3 , the input current I in  (the photocurrent I pd ) falls to decrease the output voltage V a  of the amplifier  3 .  
         [0076]     Next, at time t 4 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from high (=“1”) to low (=“0”). As a result, the switching MOS transistor  3   c ′ is turned ON, so that the amplifier  3  with the load MOS transistor  3   b ′ can operate at a low response speed. Even in this case, an overshoot phenomenon as indicated by Z 2 ′ appears in the output voltage V a  of the amplifier  3 ; however, this overshoot phenomenon Z 2 ′ is milder due to the low response speed of the amplifier  3 . Therefore, this overshoot phenomenon Z 2 ′ in  FIG. 16B  does not affect the output voltage V out  of the comparator  5 .  
         [0077]     In  FIG. 17 , which illustrates a fourth embodiment of the signal determining apparatus according to the present invention, an inverter  3   d  is connected between the output of the comparator  5  and the gate of the switching MOS transistor  3   c ′ of  FIG. 15 . That is, when the output voltage V out  of the comparator  5  is low (=“0”), the switching MOS transistor  3   c ′ is turned OFF to disconnect the load MOS transistor  3   b ′ from the amplifier  3 , so that the amplifier  3  with the load MOS transistor  3   b ′ can operate at a high response speed. On the other hand, when the output voltage V out  of the comparator  5  is high (=“1”), the switching MOS transistor  3   c ′ is turned ON to connect the load MOS transistor  3   b ′ to the amplifier  3 , so that the amplifier  3  with the load MOS transistor  3   b ′ can operate at a low response speed.  
         [0078]     In  FIG. 17 , assume that the reference voltage V ref  is relatively low, i.e., V ref &lt;&lt;V 0 .  
         [0079]     The operation of the signal determining apparatus of  FIG. 17  will be explained next with reference to  FIGS. 18A, 18B  and  18 C.  
         [0080]     When the input current I in  (or the photocurrent I pd ) is changed as illustrated in  FIG. 18A , the output voltage V a  of the amplifier  3  is changed as illustrated in  FIG. 18B , and the output voltage V out  of the comparator  5  is changed as illustrated in  FIG. 18C .  
         [0081]     In more detail, before time t 1 , the input current I in  (the photocurrent I pd ) is zero, so that the output voltage V a  of the amplifier  3  is V 0 . In this case, the output voltage V out  of the comparator  5  is low (=“0”), so that the switching MOS transistor  3   c ′ is turned OFF. Therefore, the amplifier  3  without the load MOS transistor  3   b ′ can operate at a high response speed.  
         [0082]     At time t 1 , the input current I in  (the photocurrent I pd ) rises to increase the output voltage V a  of the amplifier  3 .  
         [0083]     Next, at time t 2 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from low (=“0”) to high (=“1”). As a result, the switching MOS transistor  3   c ′ is turned ON, so that the amplifier  3  with the load MOS transistor  3   b ′ can operate at a low response speed. In this case, although an undershoot phenomenon as indicated by Z 1 ′ in  FIG. 18B  appears in the output voltage V a  of the amplifier  3 , this undershoot phenomenon Z 1 ′ is milder due to the low response speed of the amplifier  3 . Therefore, this undershoot phenomenon Z 1 ′ does not affect the output voltage V out  of the comparator  5 .  
         [0084]     Next, at time t 3 , the input current I in  (the photocurrent I pd ) falls to decrease the output voltage V a  of the amplifier  3 .  
         [0085]     Next, at time t 4 , the output voltage V a  of the amplifier  3  reaches the reference voltage V ref , so that the output voltage V out  of the comparator  5  is switched from high (=“1”) to low (=“0”). As a result, the switching MOS transistor  3   c ′ is turned OFF, so that the amplifier  3  without the load MOS transistor  3   b ′ can operate at a high response speed. Even in this case, although an overshoot phenomenon as indicated by Z 2  in  FIG. 18B  appears in the output voltage V a  of the amplifier  3 , this overshoot phenomenon Z 2  does not affect the output voltage V out  of the comparator  5  due to the low reference voltage V ref . Even in  FIGS. 15 and 17 , the same modifications as illustrated in  FIGS. 11 and 12  can be applied. That is, the feedback resistor  3   a  can be replaced by a series of two resistors, and the load MOS transistor  3   b ′ can be replaced by a series of resistor and a capacitor connected between a node of the above-mentioned resistors and the switching MOS transistor.  
         [0086]     Further, in  FIGS. 15 and 17 , the same modifications as illustrated in  FIGS. 13 and 14  can be applied.  
         [0087]     Also, the amplifier  3  can be constructed by an operational amplifier  3 ′ as illustrated in  FIG. 19  where the definite voltage V 0  is applied to a non-inverting input.  
         [0088]     Note that the present invention can be applied to other signal determining apparatuses for inputting differential signals other than photocurrent signals.  
         [0089]     As explained hereinabove, according to the present invention, the generation of spurious waveforms can be suppressed, which can prevent inviting a malfunction.