Abstract:
An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Description:
BACKGROUND 
       [0001]    This disclosure relates generally to the field of semiconductor chip reliability monitoring. 
         [0002]    Semiconductor chips are used in a wide variety of industries and applications, such as military equipment or satellites, under diverse operating conditions. The circuitry comprising a semiconductor chip degrades over the lifetime of the semiconductor chip, ultimately resulting in chip failure. Circuit degradation in a semiconductor chip is influenced by the operating conditions of the chip, including voltage bias, current density, and temperature. Circuit degradation may be accelerated by defective chips or abnormal operating conditions, such as power surges or unexpected temperature shifts. Chip failure may cause catastrophic failure of a larger system incorporating the chip. Reliability monitoring of semiconductor chips may prevent unforeseen chip failure, allowing a potentially failing chip to be made redundant or flagged for replacement or repair before catastrophic failure occurs. 
       SUMMARY 
       [0003]    An exemplary embodiment of an accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. 
         [0004]    An exemplary embodiment of a method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. 
         [0005]    An exemplary embodiment of an electronics package comprising a semiconductor chip comprising an accelerated failure indicator includes a heat spreader, the heat spreader being connected to the semiconductor chip via a heat conducting compound; and a gap in the heat conducting compound located in an area corresponding to a location of the accelerated failure indicator on the semiconductor chip, wherein the accelerated failure indicator comprises: an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. 
         [0006]    Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0007]    Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
           [0008]      FIG. 1  illustrates a top view of an embodiment of an accelerated failure indicator (AFI). 
           [0009]      FIG. 2  illustrates a cross section of an embodiment of an AFI. 
           [0010]      FIG. 3  illustrates an embodiment of a semiconductor chip comprising a plurality of temperature sensors and an AFI. 
           [0011]      FIG. 4  illustrates an embodiment of a semiconductor chip comprising a plurality of AFIs. 
           [0012]      FIG. 5  illustrates a cross section of an embodiment of an electronics package comprising an AFI. 
           [0013]      FIG. 6  illustrates an embodiment of a method of operating an AFI. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Embodiments of systems and methods for an on-chip accelerated failure indicator (AFI) are provided, with exemplary embodiments being discussed below in detail. The AFI may be embedded in the semiconductor chip, and may act as a reliability monitor for the chip. Applying a stress condition comprising an elevated temperature to a circuit located in the AFI accelerates degradation of the AFI circuit, allowing for determination of a worst-case scenario for chip failure based on the degradation of the AFI circuit, and preventing catastrophic failure of a larger system incorporating the chip. 
         [0015]      FIG. 1  illustrates a top view of an embodiment of an AFI  100 . AFI  100  is embedded in silicon substrate  107 , which is part of a semiconductor chip. The AFI  100  comprises a heater  101  that is connected to a heating element  105 . The heating element  105  heats circuit  103  and degradation of circuit  103  is monitored by reliability sensor  102 . In some embodiments, heating element  105  heats circuit  103  to a temperature that is about 5° C. to 10° C. higher than an operating temperature of critical circuitry in the semiconductor chip. Thermal isolation region  106  protects the semiconductor chip from the heat generated by heating element  105 , and may comprise a shallow-trench-isolation (STI) region. Thermal isolation region  106  comprises a material having a thermal conductivity that is lower than the thermal conductivity of silicon substrate  107 . In some embodiments, thermal isolation region  106  may comprise silicon oxide, which has a thermal conductivity of about 1.4 W/m*° C.; in comparison, silicon substrate  107  has a thermal conductivity of about 130 W/m*° C. In other embodiments, thermal isolation region  106  may be filled with air. Heating element  105  may comprise, but is not limited to, polysilicon resistor wires, diffusion resistor strips, or back-end-of-line (BEOL) TaN resistors. The temperature inside the region enclosed by thermal isolation  106  may be monitored by optional temperature sensor  104  in some embodiments; the temperature sensor may provide feedback to heater  101 . Heater  101  and reliability monitor  102  are located outside of thermal isolation region  106 , ensuring that that the performance of heater  101  and reliability monitor  102  are not impacted by the elevated temperature within thermal isolation region  106 . Heater  101  may comprise a constant current source, inducing Joule heating in the heating element  105 . 
         [0016]    Circuit  103  may comprise any appropriate circuit components, including but not limited to metal interconnects or MOSFET devices; the circuit components that comprise circuit  103  may mimic any critical or power-hungry devices in the semiconductor chip. The bias condition of the components of circuit  103  may be identical to the bias condition of components in the semiconductor chip, so an extra power supply is not needed. Various characteristics of circuit  103  may be monitored by reliability monitor  102  to determine degradation in circuit  103 . Characteristics of circuit  103  that may be monitored by reliability monitor  102  to determine degradation include but are not limited to electromigration (EM) or resistance of metal interconnects, leakage current, or threshold voltage or bias-temperature-instability (BTI) of MOSFET devices. Degradation may occur at a higher rate in circuit  103  than in the semiconductor chip due to the elevated temperature inside thermal isolation region  106 . An alarm may be triggered by reliability monitor  102  when the degradation of circuit  103  exceeds a predetermined threshold, so as to enable redundancy or flag the semiconductor chip for repair or replacement. 
         [0017]      FIG. 2  illustrates a cross section of an embodiment of an AFI  200 . AFI  200  is embedded on silicon substrate  206 , which is part of a semiconductor chip (not shown), and comprises heating element  204   a  and  204   a  surrounding circuit  203 . Thermal isolation region  207   a  and  207   b  protects the semiconductor chip from the heat produced by heating element  204   a  and  204   b . Thermal isolation region  207   a  and  207   b  may comprise oxide or air gaps in some embodiments. Regions  208   a  and  208   b  may comprise inter-level dielectrics (ILD), a polymer, or air gaps in some embodiments. Region  201  may comprise ILD in some embodiments. Optional buried oxide (BOX) layer  205  may isolate silicon substrate  206  from the heat produced by heating element  204   a  and  204   b  in some embodiments. Optional temperature sensor  202  may monitor the temperature inside AFI  200  in some embodiments. 
         [0018]      FIG. 3  illustrates an embodiment of a semiconductor chip  300  comprising a plurality of temperature sensors  302   a - 302   p . Temperature sensors  302   a - 302   p  are shown for illustrative purposes only; a semiconductor chip  300  may comprise any appropriate number of temperature sensors. Temperature sensors  302   a - 302   p  are distributed over a critical circuitry area  303  of chip  300 . AFI  301  receives temperature data from temperature sensors  302   a - 302   p , and operates at a temperature higher than the highest temperature determined in critical circuitry area  303  by temperature sensors  302   a - 302   p . AFI  301  comprises a circuit that may mimic circuitry in critical circuitry area  303 ; the AFI circuit is monitored for degradation. 
         [0019]      FIG. 4  illustrates an embodiment of a semiconductor chip  400  comprising a plurality of AFIs  401   a - 401   i . AFIs  401   a - 401   i  are shown for illustrative purposes only; semiconductor chip  400  may comprise any appropriate number of AFIs. AFIs  401   a - 401   i  are distributed over critical circuitry area  402  of semiconductor chip  400  to capture the highest temperature within critical circuitry area  402 . AFIs  401   a - 401   i  operate at a temperature higher than the highest temperature present in critical circuitry area  402 . AFIs  401   a - 401   i  comprise a respective plurality of circuits that may mimic circuitry in critical circuitry area  402 ; the plurality of circuits in AFIs  401   a - 401   i  are monitored for degradation. 
         [0020]      FIG. 5  illustrates an embodiment of an electronics package  500  comprising an AFI  501 . Heat spreader  505  dissipates heat generated by semiconductor chip  502  via thermal conducting compound  503 . AFI  501  is located on semiconductor chip  502 . Thermal conducting compound  503  is removed from void region  504  above AFI  501 , allowing for improved thermal isolation of AFI  501 . AFI  501  is shown for illustrative purposes only, and it may be placed at any location in semiconductor chip  502 . Embodiments of semiconductor chip  502  may comprise any appropriate number of AFIs 
         [0021]      FIG. 6  illustrates en embodiment of a method  600  of operating an AFI. In block  601 , an operating temperature of critical circuitry in a semiconductor chip is determined. The operating temperature may be determined in real time. In block  602 , a thermally insulated region inside the AFI is operated at a temperature higher than the determined operating temperature of the critical circuitry. The AFI operating temperature may be about 5° C. to 10° C. higher than the determined operating temperature in some embodiments. In block  603 , a circuit located inside the thermally insulated region of the AFI is monitored for degradation. The circuit may mimic the critical circuitry of the semiconductor chip. In block  604 , when the degradation of the circuit exceeds a predetermined threshold, an alarm is triggered, allowing the semiconductor chip to be flagged for repair or replacement before failure of the semiconductor chip occurs. 
         [0022]    In an exemplary embodiment of an AFI, a 5° C. heat increase over the operating temperature of the semiconductor chip (from 100° C. to 105° C.) inside the thermally isolated region of an AFI may produce an acceleration factor of about 1.5 in electromigration of copper interconnects, and an acceleration factor of about 1.3 in electromigration of aluminum interconnects. Negative bias temperature instability (NBTI) in PMOSFET devices may be accelerated by an acceleration factor of about 1.1. Higher degradation acceleration may be obtained by raising the heat increase inside the AFI. 
         [0023]    The technical effects and benefits of exemplary embodiments include prevention of catastrophic failure of electrical systems comprising semiconductor chips. 
         [0024]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0025]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.