Abstract:
An input stage for a video receiver includes a variable gain amplifier, an analog-to-digital converter for sampling a video signal and a digital processing unit for processing digital samples of the video signal. An analog regulating circuit sets an input potential at an input of the variable gain amplifier. A differential architecture is used for the variable gain amplifier and the digital analog converter. A conversion circuit between an input coupling capacitor and the variable gain amplifier allows generating the video signal on two channels in antiphase, which are centered on the common mode voltage. Such differential architecture allows reducing the amplitude of analog signals, which is particularly advantageous in the case of a low voltage supply delivering a few volts. In addition, linearity of the video signal processing is enhanced.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]    This application is based upon and claims priority from prior French Patent Application No. 01 14921, filed on Nov. 19, 2001, the entire disclosure of which is herein incorporated by reference. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to input stages for video processing, and more particularly to a calibration device for an input stage for processing a video signal.  
           [0004]    2. Description of the Related Art  
           [0005]    Input stages for processing video signals typically comprise a calibration circuit for calibrating downstream-located circuits in the receiver and for avoiding any saturation of these circuits.  
           [0006]    A reference signal—corresponding to the coding of blacks—is used right after the line synchronization signal of the video signal, and the receiving circuit uses this reference to calibrate its internal circuits in order to avoid any saturation.  
           [0007]    The performances required by video signal input circuits, together with the miniaturization of the latter and the reducing of supply voltage, enhance the weaknesses of known input stages.  
           [0008]    [0008]FIG. 1 shows a traditional architecture of an input stage equipped with a so-called &lt;&lt;I-8I&gt;&gt; calibration circuit. FIG. 1 shows a coupling capacitor  102  that carries out continuous decoupling of line  101 . Coupling capacitor  102  makes it possible to remove the continuous component from the input signal and can be charged and discharged by two power sources  104  and  105  which are controlled by two control signals (UP) and (Down) conveyed by lines  109  and  110 , respectively. Downstream from the coupling capacitor, the video signal is amplified by a VGA amplifier  106  providing an output signal that is then digitally converted by means of an analog to digital ADC converter  107 . ADC converter  107  provides samples of the video signal that are n-bit coded at the rhythm of a sampling clock. Digital samples are then suitably processed by means of a digital processing unit  108 , which processing includes in particular calculating the gain of VGA amplifier  106  and clamp setting amplifier  106 .  
           [0009]    Generally, at reception of the reference signal corresponding to blacks, an average coding equal to 0 (on n-bit) is sought so as to benefit from all the dynamics of the coding system and to avoid any saturation. To this end, in the so called &lt;&lt;I-8I&gt;&gt; system, the digital processing carried out by the digital processing unit  108  provides a control signal, either UP on control line  109  or DOWN on control line  110  to control power source  104  or power source  105 , respectively.  
           [0010]    Although this known system provides satisfactory results for designing the input stages of conventional video receivers, it is not the case for modern architectures of video receivers due to the following reasons.  
           [0011]    First, the &lt;&lt;I-8I&gt;&gt; system does not—and this is a known fact—allow to perfectly correct calibration error. It is noted that control from any of the control circuits—either UP or DOWN—always results in maintaining a variation between the perfect reference voltage and the ADC converter output code. Today, such lack of accuracy is crippling when compared with the performances required for modern video receivers.  
           [0012]    Secondly, miniaturization of video circuits results in a continuous increase of the number of electronic components in semiconductor circuits. The size of elementary components, in particular MOS transistors, is reduced which then constrains to reducing supply voltages. This phenomenon is further aggravated by the development of portable or on board electronics, supplied with increasingly lower supply voltages.  
           [0013]    It is not rare to feed video circuits with supply voltages that do not exceed 2 volts.  
           [0014]    When supply voltage is reduced, it is clear that any calibration error of the video receiver input stage would reduce the remaining range for digital coding of the video signal thus increasing risks that the receiver saturates. Moreover, reducing the supply voltage also reduces the amplitude of signals that the circuits of the receiver can process. If amplification circuits known as &lt;&lt;track to track amplification circuits&gt;&gt; are used, linearity is affected and a crippling rate of distortion is introduced.  
           [0015]    Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.  
         SUMMARY OF THE INVENTION  
         [0016]    It is an object of the present invention to provide architecture of an input stage for a video receiver that allows an accurate and effective calibration.  
           [0017]    It is another object of the present invention to realize a video receiver input stage that is adapted for use of low supply voltages.  
           [0018]    A third object of the present invention is to realize an input stage for a video receiver that makes it possible to maintain a particularly low distortion rate.  
           [0019]    The invention achieves these objects by means of an input stage for a video receiver comprising an amplifier with variable gain, an analog to digital converter for taking samples of the video signal and a digital processing unit for processing digital samples of this video signal. The input stage is wherein an analog regulating circuit sets the input potential at the input of the variable gain amplifier.  
           [0020]    Thus, true regulation of this potential can be achieved, and without limitations inherent to the &lt;&lt;all or nothing&gt;&gt; system of circuit I-8I.  
           [0021]    In a preferred embodiment, the variable gain amplifier and the digital analog converter have a differential architecture. For this purpose a conversion circuit is interposed between the coupling capacitor and the variable gain amplifier, this conversion circuit allows to generate the video signal on two channels in antiphase, which are centered on the common mode voltage. Differential architecture makes it possible to reduce the amplitude of the analog signals, which is particularly advantageous in the case of a low supply voltage delivering just a few volts. In addition, the differential structure suppresses even harmonics, which substantially improves linearity of the video signal processing.  
           [0022]    It can be observed that differential structures are particularly adapted since DC can be achieved on both channels of the differential structure.  
           [0023]    In a preferred embodiment, analog regulation of the input potential is carried out by means of a voltage-current converter having a first input taking the potential on one of the differential outputs of the variable gain amplifier and a second input receiving a desired voltage, CVR, from the digital processing circuit. The voltage/current converter then provides a current that is used to charge or to discharge the coupling capacitor in order to adjust the potential input to the differential converter. A control input, PDN, enables blockage of the voltage/current converter when the video signal does not transmit the voltage reference of blacks.  
           [0024]    As it can be seen, the input stage precisely controls the charging current of the coupling capacitor, contrary to the &lt;&lt;all or nothing&gt;&gt; structure of conventional circuit &lt;&lt;I-8I&gt;&gt;, and is particularly adapted for realizing receivers operating at low supply voltages. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]    The above as well as other features, objects and advantages of the invention will become apparent in the following description when read in conjunction with the accompanying drawings, given by way of nonrestrictive examples, wherein:  
         [0026]    [0026]FIG. 1 illustrates a conventional architecture of a video receiver input stage comprising a calibration circuit &lt;&lt;I-8I&gt;&gt;.  
         [0027]    [0027]FIG. 2 represents the architecture of an input stage according to the present invention.  
         [0028]    The FIG. 3 a  represents a first embodiment of differential converter  106 .  
         [0029]    The FIG. 3 b  illustrates a second embodiment of differential converter  106  with higher performances.  
         [0030]    [0030]FIG. 4 shows details of an embodiment of the differential converter  106  of FIG. 3 b.   
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]    A preferred embodiment of the invention, particularly adapted to the constitution of an input stage for a battery-supplied video circuit will now be described. Naturally, it is only an exemplary embodiment and use of this circuit can be considered for other applications.  
         [0032]    [0032]FIG. 2 illustrates the architecture of a preferred embodiment of the receiver input stage. Video signal is transmitted through line  101  towards coupling capacitor  102 , which removes the continuous component from the video signal. Upstream from the coupling capacitor, signal is transmitted to a differential conversion circuit  106  enabling the generation of two output signals, respectively OUT 1  and OUT 2  in FIG. 2, these signals are in opposition of phase and are both centered on the common mode potential VCM. Both differential signals OUT 1  and OUT 2  are then transmitted to a differential variable gain amplifier (known as VGA)  206 , the gain of this amplifier being set by a potential (not represented) and a digital processing unit  260  controls the amplifier. Differential variable gain amplifier  206  provides two output signals—OUT P and OUT N, respectively—that are transmitted to an analog to digital (ADC) converter  207  having a differential structure, which allows to sample the differential signal at a preset rhythm; the samples are n-bit coded and then transmitted to the digital processing unit  260 .  
         [0033]    The differential amplifier  206  and the ADC converter  207  with a differential structure are well-known circuits by people qualified in the art and therefore, they will not be further detailed. We will only say that the differential structure that is readily adopted in this architecture allows to reduce the amplitude of analog signals processed for a given video signal. Thus, for a video signal having a peak-to-peak amplitude of 1 volt, it is observed that the video signal can be analogically processed with amplitudes having a level that does not exceed 250 millivolts, which is particularly useful with very low voltage supply. By means of this differential structure, a great linearity can be achieved for analog processing by reducing the even harmonic rate and total harmonic distortion is maintained at a very low rate.  
         [0034]    In a particular embodiment, one of the analog signals—for example signal OUT P—is transmitted to a first input  240  of a voltage/current converter  220  having a second input  230  receiving a Clamp Voltage Reference (CVR). The voltage/current converter is also known as an “operational transconductance to amplify” (OTA) circuit. Such a circuit converts the potential difference between inputs  230  and  240  into a current that is conveyed by a circuit  250  for, according to the case, charging or discharging coupling capacitor  102 . The voltage/current converter  220  is inhibited by a control signal transmitted to a PDN input via a control line  211  for stopping any loss of charging or discharging current of the capacitor apart from the reception of the reference signal of blacks.  
         [0035]    Thus, it is observed that direct analog control of the input voltage can be achieved by means of the voltage/current converter that charges or discharges capacitor  102 . This input voltage can thus be very quickly and very precisely adjusted with the voltage CVR provided by the digital processing system that lies before the input stage.  
         [0036]    Thus, with this device it is possible to calibrate the input stage of the receiver such as to ensure &lt;&lt;0&gt;&gt; coding at the output of converter  207  upon reception of the reference signal corresponding to calibration “blacks”.  
         [0037]    [0037]FIG. 3 a  shows a very simple realization of the differential converter  106  based on the use of operational amplifiers. A first operational amplifier (op amp)  350  is assembled as a tracker and receives the input signal IN that carries the video signal on its positive input. The op amp&#39;s negative input is connected to the output. Amplifier  350  then drives an inverter assembly based on a second operational amplifier  360  associated with a first resistor  361  connected between the output of op amp  350  and the negative input of op amp  360 , this same negative input being connected to the output of op amp  360  via a second resistor  362 . A reference voltage Vref is transmitted to the positive input of op amp  360  and is used to set the common mode voltage on which both differential ways thus generated are centered, respectively at the output of op amp  350  (OUT P on a terminal  302 ) and at the output of op amp  360  (OUT N on terminal  303 ).  
         [0038]    It is observed that performances of the circuit of FIG. 3 a  are limited, in particular when a low rate of distortion and a high input rate are wanted. In this case, it can be advantageous to use the circuit of FIG. 3 b,  based on a differential structure containing Metal Oxide Silicon-type transistors, which allows higher performances in particular in terms of linearity and input rates.  
         [0039]    The converter of FIG. 3 b  comprises a differential structure with a differential amplifier  310 , based for example on an architecture composed of Metal Oxide Silicon (MOS) transistors. The positive input  301  of op amp  310  receives the video signal as an input. The differential amplifier provides outputs two signals, respectively OUT P on terminal  302  and OUT N on terminal  303 . The output signal OUT-P is connected to the negative input of the differential amplifier, so that this OUT-P signal is driven by the input signal IN existing on terminal  301 .  
         [0040]    A resistor bridge, comprised of resistors  330  and  340 , of equal values, serially connected between terminals  302  (OUT P) and  303  (OUT N), is inserted and this resistive bridge midpoint is connected to a negative input of a second differential amplifier  320 —known as a common mode amplifier—the positive input of amplifier  320  receives the common mode reference voltage VCM. Common mode amplifier  320  and differential amplifier  310  interact such that operation of the differential amplifier  310  is controlled by generation of two signals OUT P and OUT N that are in opposition of phase and perfectly centered on the common mode voltage VCM existing on the positive input of amplifier  320 .  
         [0041]    [0041]FIG. 4 shows an example of realization of the differential converter  106  of FIG. 3 b  (known as a single to differential converter); it is realized by means of a differential structure based on a pair of NMOS-type transistors  401  and  402 . Although the preferred embodiment will describe the use of NMOS-type transistors to compose the differential pair, it is clear that people qualified in the art will be able to readily adapt the structure to an architecture in which the differential pair will be based on PMOS-type transistors. The amplifier is fed by supply source that delivers a voltage Vdd. The source electrode of NMOS transistors  401  and  402  is connected to a power source  403  having its other end connected to ground. Each transistor of the differential pair  401 - 402  is supplied via its drain electrode by a power source, respectively based on a PMOS transistor  404  and a PMOS transistor  406  that are mounted in current mirror. The source and drain of transistor  404  (respectively transistor  406 ) are respectively connected to the supply terminal of Vdd and the drain of transistor  401  (respectively transistor  402 ).  
         [0042]    Transistors  404  and  406  are mounted in current mirror and cooperate with a common mode manager stage that comprises a second differential pair associated with a power source  412  and two PMOS-type transistors, respectively  408  and  409 . More particularly, the second differential pair comprises two transistors  410  and  411  that have sources connected to a power source  412  having another end connected to ground. The drain of transistor  410  (respectively transistor  411 ) is connected to the drain of transistor  408  (respectively transistor  409 ) that has its source is connected to the supply terminal Vdd. The grid of transistor  410  is connected to the midpoint of a resistive bridge comprising both resistors  340  and  330  of identical values, their ends are respectively connected to the differential structure outputs OUT N (terminal  303 ) and OUT P (terminal  302 ). The resistive bridge  340 - 330  is used to obtain, on its midpoint MC, a potential representative of the common mode value of outputs OUT P and OUT N of the differential amplifier. The grid of transistor  411  receives a desired voltage—Vcm—that is used to regulate the polarization level of the stage in common mode and that is controlled by the digital processing unit in order to output a code &lt;&lt;0&gt;&gt; from ADC converter  207 .  
         [0043]    The grid electrodes of transistors  408 ,  404  and  406  are all connected together and the grid of transistor  408  is connected to the drain of transistor  408 , thus ensuring it operates within the square zone of its characteristic I (V GS ). Thus the transistors are mounted in current mirror and a same drain current flows through them since, as they are substantially identical, they undergo the same variations of grid-source voltage V GS .  
         [0044]    The differential pair made of transistors  401  and  402  is a first stage for a second gain stage, a Miller-type stage, which is composed of a pair of PMOS-type transistors  405  and  407  that are assembled as a common source. More precisely, the drain of transistor  401  (respectively  402 ) is connected to the grid of transistor  405  (respectively  407 ), and its source is connected to supply terminal Vdd. The drain of transistor  405  (respectively  407 ) is connected to a power source  413  (respectively  414 ) that is in turn connected to ground at its other end. The drain of transistor  405  is also connected to the output electrode  303  OUT-N of the converter. Similarly, the drain of transistor  407  will be connected to the output electrode  302  OUT P of the differential converter.  
         [0045]    The diagram of FIG. 4 only represents a particular embodiment. In some cases it will be possible to associate a capacitor (not represented) to the Miller stage, in order to fix the gain-band product of the differential structure, as is known by people qualified in the art.  
         [0046]    While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those of ordinary skill in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention.  
         [0047]    Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.