Abstract:
A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

Description:
TECHNICAL FIELD 
     The present invention relates to CMOS (Complementary Metal Oxide Semiconductor) devices, and more specifically, to CMOS devices having different metals in gate electrodes. 
     RELATED ART 
     In a typical CMOS device, there are an n-channel transistor and a p-channel transistor electrically coupled together. To enhance the performance of the CMOS device, there is a need to scale the equivalent oxide thickness (EOT) to 1 nm, the scaling of the gate oxide will require high-k oxide materials and metals to replace N-poly and P-poly. Therefore, there is a need for a structure (and a method of forming the same) in which the gate electrodes of the two transistors have a lower resistance than those of the prior act. 
     SUMMARY OF THE INVENTION 
     The present invention provides a semiconductor structure, comprising (a) a semiconductor substrate; (b) a gate dielectric layer on top of the semiconductor substrate; (c) a first metal containing region on top of the gate dielectric layer; (d) a second metal containing region on top of the gate dielectric layer, wherein the first and second metal containing regions are in direct physical contact with each other; (e) a gate electrode layer (i) on top of both the first and second metal containing regions and (ii) in direct physical contact with both the first and second metal containing regions; and (f) a patterned photoresist layer on top of the gate electrode layer. 
     The present invention provides a semiconductor structure fabrication method, comprising providing a semiconductor structure which includes (a) a semiconductor substrate, (b) a gate dielectric layer on top of the semiconductor substrate, (c) a first metal containing region on top of the gate dielectric layer, and (d) a first patterned mask layer on top of the first metal containing region; and forming a second metal containing layer on top of and in direct physical contact with both the first metal containing region and the first patterned mask layer. 
     The present invention provides a structure (and a method of forming the same) in which the gate electrodes of the transistors have a two metals, one metal for NMOS and one for PMOS and lower resistance than those of the prior art. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-11  illustrate a fabrication process for forming a semiconductor structure, in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIGS. 1-11  illustrate a fabrication process for forming a semiconductor structure  100 , in accordance with embodiments of the present invention. 
     More specifically, in one embodiment, with reference to  FIG. 1 , the fabrication process starts with a semiconductor (e.g., silicon, germanium, etc.) substrate  110 . 
     Next, a gate dielectric layer  120  is formed on top of the semiconductor substrate  110 . Illustratively, the gate dielectric layer  120  comprises a high-K dielectric material, wherein K is dielectric constant and is higher than 3.9 (e.g., HfO 2 ). In one embodiment, the gate dielectric layer  120  is formed by CVD (Chemical Vapor Deposition) or ALD (atomic layer deposition). 
     Next, in one embodiment, a first metal containing layer  130  is formed on top of the gate dielectric layer  120 . Illustratively, the first metal containing layer  130  comprises a pure metal (e.g., tungsten), a metal silicide (e.g., NiSi), or a metal nitride (e.g., TaN or TiN). In one embodiment, the first metal containing layer  130  is formed by CVD, ALD (Atomic Layer Deposition), or any other deposition techniques. 
     Next, in one embodiment, with reference to  FIG. 2 , a first patterned mask layer  210  is formed on top of the first metal containing layer  130 . Illustratively, the first patterned mask layer  210  comprises a low-K dielectric material (e.g., SiLK material from DOW chemical corporation). In one embodiment, the first patterned mask layer  210  is formed by a spin-on process (this process may involve curing at, illustratively, 100° C.-200° C. to evaporate all solvent) followed by a lithographic and etching step. 
     Next, in one embodiment, the first patterned mask layer  210  is used as a mask for directionally and selectively etching the first metal containing layer  130  stopping at the gate dielectric layer  120 . As a result, portions of the first metal containing layer  130  which are not covered by the first patterned mask layer  210 , are removed, resulting in the structure  100  of  FIG. 3  In one embodiment, the directional and selective etching of the first metal containing layer  130  also etches the first patterned mask layer  210 , resulting in the first patterned mask layer  210  becoming thinner. 
     With reference to  FIG. 3 , as a result of the directional and selective etching of the first metal containing layer  130  of  FIG. 2 , what remains of the first metal containing layer  130  of  FIG. 2  is a first metal containing region  130 ′. 
     Next, in one embodiment, with reference to  FIG. 4 , a second metal containing layer  410  is formed on top of the structure  100  of  FIG. 3 . Illustratively, the second metal containing layer  410  comprises a pure metal (e.g., tungsten), a metal silicide (e.g., NiSi) or a metal nitride (e.g., TaN or TiN). In one embodiment, the material of the first metal containing region  130 ′ is different from the material of the second metal containing layer  410 . Illustratively, the work function of the material of the first metal containing region  130 ′ is different from the work function of the material of the second metal containing layers  410 . In one embodiment, the second metal containing layer  410  is formed by CVD or ALD, or any other deposition techniques. 
     Next, with reference to  FIG. 5 , a second patterned mask layer  510  is formed on top of the second metal containing layer  410 , but not directly above the first metal containing region  130 ′ (i.e., not overlapping the first metal containing region  130 ′). Illustratively, the second patterned mask layer  510  comprises a low-K dielectric material (e.g., SiLK material from DOW chemical corporation). In one embodiment, the second patterned mask layer  510  is formed by a spin-on process (this process may involve curing at, illustratively, 100° C.-200° C. to evaporate all solvent) followed by a lithographic and etching step. 
     Next, in one embodiment, the second patterned mask layer  510  is used as a mask for directionally and selectively etching the second containing metal layer  410  stopping at the gate dielectric layer  210 . As a result, portions of the metal containing layer  410  which are not covered by the second mask layer  510  are removed, resulting in the structure  100  of  FIG. 6 . In one embodiment, the directional and selective etching of the second metal containing layer  410  also etches the first and the second patterned mask layer  210  and  510 , resulting in the first and the second patterned mask layers  210  and  510  becoming thinner. 
     With reference to  FIG. 6 , as a result of the directional and selective etching of the second metal containing layer  410  of  FIG. 5 , what remains of the second metal containing layer  410  of  FIG. 5  is a second metal containing region  410 ′. 
     Next, in one embodiment, the first patterned mask layer  210  and the second patterned mask layer  510  are removed by wet etching, resulting in the structure  100  of  FIG. 7 . 
     Next, in one embodiment, a CMP (Chemical Mechanical Polishing) process is performed to make the top surfaces of the first metal containing region  130 ′ and the second metal containing region  410 ′ essentially coplanar, resulting in the structure  100  of  FIG. 8 . 
     Next, with reference to  FIG. 9 , in one embodiment, a gate electrode layer  910  is formed on top of the structure  100  of  FIG. 8 . Illustratively, the gate electrode layer  910  comprises polysilicon. In one embodiment, the gate electrode layer  910  is formed by CVD. 
     Next, in one embodiment, a patterned photoresist layer  920  is formed on top of the gate electrode layer  910 . Illustratively, the patterned photo resist layer  920  comprises two photoresist regions  920 A and  920 B which overlap the first and the second metal containing regions  130 ′ and  410 ′, respectively. In one embodiment, the patterned photoresist layer  920  is formed by a conventional lithographic process. 
     Next, in one embodiment, the patterned photo resist layer  920  is used as a mask for directionally and selectively etching the gate electrode layer  910  and the first and the second metal containing regions  130 ′ and  410 ′. This etching process stops at the high-K gate dielectric layer  120 , resulting in the structure  100  of  FIG. 10 . 
     Next, with reference to  FIG. 10 , what remains of the first metal containing region  130 ′ is a first metal containing region  130 ″ and what remains of the second metal containing region  140 ′ is a second metal containing region  140 ″. Next, in one embodiment, the two regions  920 A and  920 B of the patterned photo resist layer  920  are removed by a wet etching step, resulting in the structure  100  of  FIG. 11 . 
     Next, with reference to  FIG. 1 , in one embodiment, the two gate stacks  1110 A and  1110 B can be used as two blocking masks in a fabrication process which is performed to fabricate two transistors in the silicon substrate  110 . It should be noted that, one of the two fabricated transistors can be an n-channel transistor and the other can be a p-channel transistor. In one embodiment, the work function of the material of the first metal containing region  130 ″ (corresponding to the p-channel transistor) should be higher than the work function of the material of the second metal containing region  140 ″ (corresponding to the n-channel transistor). Illustratively, the work function of the material of the first metal containing region  130 ″ may be 5 keV and the work function of the material of the second metal containing region  140 ″ may be 4 keV. In one embodiment, the two transistors can be connected to form a CMOS (Complementary Metal Oxide Semiconductor) device. 
     In summary, with reference to  FIG. 2 , the first patterned mask layer  210  is used as a mask to etch the first metal containing layer  130 . Because the first patterned mask layer  210  comprises a low-K material and is formed by spin-on process at a low temperature, therefore, the etching of the first metal containing layer  130  stop at the high-K gate dielectric layer  120  without damage to the high-K gate dielectric layer  120 . With reference to  FIG. 5 , the second patterned mask layer  510  is used as a mask to etch the second metal containing layer  410 . With reference to  FIG. 9 , the patterned photo resist layer  920  is used as a mask to form the two gate stacks  1110 A and  1110 B. With reference to  FIG. 11 , the two gate stacks  1110 A and  1110 B are 
     used as two blocking masks to form two transistors in the silicon substrate  110 . The two transistors can be connected to form a CMOS device. 
     While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.