Abstract:
A semiconductor integrated circuit disclosed herein, comprises a first core which realizes a predetermined function; a second core which is different from the first core and realizes a predetermined function; a power supply circuit which is capable of supplying, to the first core, a power supply voltage different from that supplied to the second core; and a clock generating circuit which supplies a clock signal to each of the first core and the second core, the clock generating circuit including a clock skew reducing circuit which reduces clock skew occurring between the clock signal in the first core and the clock signal in the second core.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims benefit of priority under 35 U.S.C.§119 to Japanese Patent Application No. 2003-335561, filed on Sep. 26, 2003, the entire contents of which are incorporated by reference herein.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit which includes a clock supply system to reduce clock skew when multiple power supplies are used inside.  
         [0004]     2. Related Background Art  
         [0005]     Hitherto, the power supply voltages of sequential circuits and combinational circuits in one semiconductor chip have a fixed value. In some cases, however, to reduce power consumption, the power supply voltage of some block (hereinafter referred to as a core) is decreased. Moreover, the power supply voltage of the core may be changed depending on applications executed by this core. When the power supply voltage of the core is changed, the propagation delay of a clock supplied to the core is also changed, which leads to an increase in the clock skew of the entire one semiconductor chip.  
         [0006]      FIG. 1  is a block diagram showing the connection relationship of a related semiconductor integrated circuit in a semiconductor chip. In the example in  FIG. 1 , the semiconductor integrated circuit includes a clock generating circuit  1 , a core A, and a core B. The clock generating circuit  1  generates a clock signal and supplies the clock signal to the core A and the core B.  
         [0007]     The core A and the core B are constituted by sequential circuits and combinational circuits, and it is assumed that data is delivered between the core A and the core B. Namely, the core means a constitutional unit to realize a predetermined function.  
         [0008]      FIG. 2  is a block diagram showing the internal configuration of the clock generating circuit  1 ,  FIG. 3  is a block diagram showing a clock supply system inside the core A, and  FIG. 4  is a block diagram showing a clock supply system inside the core B.  
         [0009]     An oscillation clock signal is outputted from a PLL circuit  10  included in the clock generating signal  1  in  FIG. 2 , and this clock signal is supplied to flip-flop circuits A 11  and A 12  of the core A through buffers A 1  to A 5  and supplied to flip-flop circuits B 11  and B 12  of the core B through buffers C 1  and B 1  to B 5 .  
         [0010]     As can be seen from  FIG. 1  to  FIG. 4 , hitherto, the power supply voltage is fixed in the semiconductor chip, and hence, propagation delays of the clock signal from the PLL circuit  10  to the flip-flop circuits A 11 , A 12 , B 11 , and B 12  which are sequential circuits are also fixed. In other words, since delay values of the buffers A 1  to A 5  and B 1  to B 5  which are delay elements included in a clock system are fixed, a reduction in clock skew is realized by designing a clock signal supply system with consideration given to the propagation delays of the clock signal from the PLL circuit  10  to the flip-flop circuits A 11 , A 12 , B 11  and B 12  which are the sequential circuits.  
         [0011]     When the power supply voltage of the core A is made variable, however, the delay values of the buffers A 1  to A 5  change, and accordingly the propagation delays of the clock signal to the flip-flop circuits A 11  and A 12  which are the sequential circuits change. This causes a problem that the propagation delays of the clock signal to the flip-flop circuits A 11  and A 12  and the propagation delays of the clock signal to the flip-flop circuits B 11  and B 12  cannot match.  
       SUMMARY OF THE INVENTION  
       [0012]     In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor integrated circuit, comprises: 
        a first core which realizes a predetermined function;     a second core which is different from the first core and realizes a predetermined function;     a power supply circuit which is capable of supplying, to the first core, a power supply voltage different from that supplied to the second core; and     a clock generating circuit which supplies a clock signal to each of the first core and the second core, the clock generating circuit including a clock skew reducing circuit which reduces clock skew occurring between the clock signal in the first core and the clock signal in the second core.       
 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]      FIG. 1  is a block diagram showing the circuit configuration of a related semiconductor integrated circuit;  
         [0018]      FIG. 2  is a block diagram showing the configuration of a clock generating circuit in the related semiconductor integrated circuit;  
         [0019]      FIG. 3  is a block diagram showing a clock supply system inside one core in the related semiconductor integrated circuit;  
         [0020]      FIG. 4  is a block diagram showing a clock supply system inside another core in the related semiconductor integrated circuit;  
         [0021]      FIG. 5  is a block diagram showing the configuration of a semiconductor integrated circuit according to a first embodiment;  
         [0022]      FIG. 6  is a block diagram showing the configuration of a clock generating circuit in the semiconductor integrated circuit in  FIG. 5 ;  
         [0023]      FIG. 7  is a block diagram showing the configuration of a semiconductor integrated circuit according to a second embodiment;  
         [0024]      FIG. 8  is a block diagram showing the configuration of a clock generating circuit in the semiconductor integrated circuit in  FIG. 7 ;  
         [0025]      FIG. 9  is a block diagram showing a clock supply system inside one core in the semiconductor integrated circuit in  FIG. 7 ; and  
         [0026]      FIG. 10  is a block diagram showing a clock supply system inside another core in the semiconductor integrated circuit in  FIG. 7 .  
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
     First Embodiment  
       [0027]     A semiconductor integrated circuit according to this embodiment is designed in such a manner that when the power supply voltage of a part of cores is changed, clock skew between the core whose power supply voltage is changed and the core whose power supply voltage is not changed is reduced by changing the propagation delay of a clock signal simultaneously. Further details will be given below.  
         [0028]      FIG. 5  is a block diagram showing the configuration of the semiconductor integrated circuit according to this embodiment. In the example in  FIG. 5 , the semiconductor integrated circuit includes a clock generating circuit  2 , a power supply circuit  20 , a core A, and a core B. These core A and core B are each a constitutional unit which realizes a predetermined function. Although  FIG. 5  shows two separate cores, plural cores more than two may be provided.  
         [0029]     The clock generating circuit  2  generates a clock signal and supplies the clock signal to the core A and the core B. Namely, a high-frequency signal is inputted to an input terminal INCLK of the clock generating circuit  2 , for example, from a quartz oscillator, while the clock signal is outputted from an output terminal ACLK and inputted to an input terminal A 1 CLK of the core A. The clock signal is also outputted from an output terminal BCLK of the clock generating circuit  2  and inputted to an input terminal B 1 CLK of the core B. Incidentally, the internal configurations of the core A and the core B are the same as those in  FIG. 3  and  FIG. 4  described above.  
         [0030]     An output terminal OUTA of the core A is connected to an input terminal INB of the core B, and an output terminal OUTB of the core B is connected to an input terminal INA of the core A. Thereby, data is delivered between the core A and the core B.  
         [0031]     A power supply voltage PW is supplied to this semiconductor integrated circuit, for example, from the outside, and this power supply voltage is supplied as it is to the clock generating circuit  2 , the power supply circuit  20 , and the core B. The power supply circuit  20  can select whether to supply the power supply voltage PW as it is to the core A or to transform the power supply voltage PW and then supply the transformed power supply voltage to the core A. This selection is performed by a control signal CTL inputted to an input terminal ACTNL 2 . The power supply voltage from the power supply circuit  20  is supplied to the core A via an output terminal AVDD.  
         [0032]     In this embodiment, the power supply voltage PW is 1.25 V, and the power supply voltage transformed by the power supply circuit  20  is 1.00 V. As is known from the above, the core B operates at 1.25 V, whereas the core A operates at either 1.25 V or 1.00 V. The control signal CTL inputted to the input terminal ACNTL 2  of the power supply circuit  20  controls which of power supply voltages is supplied from the power supply circuit  20  to the core A.  
         [0033]      FIG. 6  is a block diagram showing the internal configuration of the clock generating circuit  2 . As shown in  FIG. 6 , the clock generating circuit  2  according to this embodiment includes a PLL (Phase Locked Loop) circuit  10 , buffers C 20  and C 21 , and a selector C 22 . Out of these elements, the buffers C 20  and C 21  and the selector C 22  constitute a clock skew reducing circuit in this embodiment.  
         [0034]     The clock signal outputted from the PLL circuit  10  is inputted as it is to the selector C 22  and simultaneously inputted to the selector C 22  via the buffer C 20 . The control signal CTL is also inputted to the selector C 22  via an input terminal ACNTL. Therefore, either the clock signal inputted as it is or the clock signal inputted via the buffer C 20  is outputted from the selector C 22  according to whether the control signal CTL is “0” or “1”. The clock signal outputted from the selector C 22  is supplied to the core A via the output terminal ACLK. On the other hand, the clock signal outputted from the PLL circuit  10  is also supplied from the output terminal BCLK to the core B via the buffer C 21 .  
         [0035]     In the semiconductor integrated circuit thus configured, the following operation is performed. For example, when the core A is operated at 1.00 V, the control signal CTL is set to “0”. In this case, the selector C 22  outputs the clock signal outputted directly from the PLL circuit  10 . Hence, a clock signal system is designed so that the propagation delay of the clock signal before it arrives at flip-flop circuits A 11  and A 12  from the PLL circuit  10  through the selector C 22  and the propagation delay of the clock signal before it arrives at flip-flop circuits B 11  and B 12  from the PLL circuit  10  through the buffer C 21  become equal to each other.  
         [0036]     In contrast, when the core A is operated at 1.25 V, the control signal CTL is set to “1”. In this case, the selector C 22  outputs the clock signal outputted from the buffer C 20 . Hence, the clock signal system is designed so that the propagation delay of the clock signal before it arrives at the flip-flop circuits A 11  and A 12  from the PLL circuit  10  through the buffer C 20  and the selector C 22  and the propagation delay of the clock signal before it arrives at the flip-flop circuits B 11  and B 12  from the PLL circuit  10  through the buffer C 21  become equal to each other.  
         [0037]     Namely, the design is worked out so that a propagation delay difference of the clock signal when the power supply voltage of the core A changes from 1.00 V to 1.25 V and a delay value of the buffer C 20  become equal. In other words, the buffer C 21  is set in such a manner that the propagation delay of the clock signal in the core A when the clock signal whose delay time before the clock signal arrives at the selector C 22  is the shortest is selected and the propagation delay of the clock signal when it arrives at the core B through the buffer C 21  match.  
         [0038]     Thanks to the aforementioned design, even if either a power supply voltage of 1.25 V or a power supply voltage of 1.00 V is supplied to the core A, the occurrence of clock skew between the flip-flop circuits A 11  and A 12  and the flip-flop circuits B 11  and B 12  can be suppressed by switching the control signal CTL.  
         [0039]     As a result, even when the power supply voltage to be supplied to a part of cores in the semiconductor integrated circuit is decreased to reduce power consumption, the occurrence of clock skew can be suppressed. Consequently, setup time/hold time violations which occur between a core whose voltage is decreased and a core whose voltage is not decreased can be reduced.  
       Second Embodiment  
       [0040]     In the aforementioned first embodiment, the core A is designed in an alternative manner so as to operate at either 1.25 V or 1.00 V. However, in some cases, there are many power supply voltages to be supplied to the core A, and in other cases, the power supply voltage cannot be determined at the time of designing. Hence, in this embodiment, by providing a DLL circuit in the clock generating circuit and automatically adjusting a difference between an edge of the clock signal in the core A and an edge of the clock signal in the core B, it becomes unnecessary to determine the power supply voltage when the semiconductor integrated circuit is designed. Further details will be given below.  
         [0041]      FIG. 7  is a block diagram showing the configuration of a semiconductor integrated circuit according to this embodiment. In the example in  FIG. 7 , the semiconductor integrated circuit includes a clock generating circuit  3 , a power supply circuit  30 , a core A, and a core B.  
         [0042]     The clock generating circuit  3  generates a clock signal and supplies the clock signal to the core A and the core B. Namely, a high-frequency signal is inputted to an input terminal INCLK of the clock generating circuit  3 , for example, from a quartz oscillator, while the clock signal is outputted from an output terminal ACLK and inputted to an input terminal A 1 CLK of the core A. The clock signal is also outputted from an output terminal BCLK of the clock generating circuit  3  and inputted to an input terminal B 1 CLK of the core B.  
         [0043]     An output terminal OUTA of the core A is connected to an input terminal INB of the core B, and an output terminal OUTB of the core B is connected to an input terminal INA of the core A. Thereby, data is delivered between the core A and the core B.  
         [0044]     Moreover, a feedback clock signal of the core A is outputted from an output terminal G 1 CLK of the core A and inputted to an input terminal GCLK of the clock generating circuit  3 . A feedback clock signal of the core B is outputted from an output terminal F 1 CLK of the core B and inputted to an input terminal FCLK of the clock generating circuit  3 .  
         [0045]     A power supply voltage PW is supplied to this semiconductor integrated circuit, for example, from the outside, and this power supply voltage is supplied as it is to the clock generating circuit  3 , the power supply circuit  30 , and the core B. A control signal CTL is inputted to an input terminal ACNTL  3  of the power supply circuit  30 . This control signal CTL controls the value of the power supply voltage to be supplied to the core A, and in this embodiment, the value of the power supply voltage which the power supply circuit  30  supplies to the core A changes steplessly according to the control signal CTL. In other words, by using the power supply circuit  30 , it becomes possible to supply any given power supply voltage to the core A according to the control signal CTL.  
         [0046]      FIG. 8  is a block diagram showing the internal configuration of the clock generating circuit  3 ,  FIG. 9  is a block diagram showing a clock supply system inside the core A, and  FIG. 10  is a block diagram showing a clock supply system inside the core B.  
         [0047]     As shown in  FIG. 8 , the clock generating circuit  3  according to this embodiment includes a PLL (Phase Locked Loop) circuit  10 , a buffer C 30 , and a DLL (Delay Locked Loop) circuit  32 . Out of these elements, the DLL circuit  32  constitutes a clock skew reducing circuit in this embodiment.  
         [0048]     As shown in  FIG. 9 , the clock signal inputted from the input terminal A 1 CLK is inputted to a flip-flop circuit A 11  via buffers A 1 , A 2 , and A 4 , and simultaneously inputted to a flip-flop circuit A 12  via buffers A 1 , A 3 , and A 5 . Moreover, immediately before being inputted to the flip-flop circuit A 12 , the clock signal is outputted as the feedback clock signal from the output terminal G 1 CLK and inputted to the input terminal GCLK of the clock generating circuit  3  in  FIG. 8 .  
         [0049]     As shown in  FIG. 10 , the clock signal inputted from the input terminal B 1 CLK is inputted to a flip-flop circuit B 11  via buffers B 1 , B 2 , and B 4 , and simultaneously inputted to a flip-flop circuit B 12  via buffers B 1 , B 3 , and B 5 . Moreover, immediately before being inputted to the flip-flop circuit B 12 , the clock signal is outputted as the feedback clock signal from the output terminal F 1 CLK and inputted to the input terminal FCLK of the clock generating circuit  3  in  FIG. 8 .  
         [0050]     As shown in  FIG. 8 , the feedback clock signals inputted from the input terminal FCLK and the input terminal GCLK are both inputted to the DLL circuit  32 . The DLL circuit  32  automatically adjusts edges of these two feedback clock signals. Namely, a clock signal to be outputted from the DLL circuit  32  is adjusted in such a manner that edges of a clock signal which is outputted from the PLL circuit  10  via the buffer C 30  and arrives at the flip-flop circuit B 12  and a clock signal which is outputted from the DLL circuit  32  and arrives at the flip-flop circuit A 12  are synchronized. Therefore, no matter what value the power supply voltage supplied from the power supply circuit  30  to the core A changes to, the DLL circuit  32  automatically reduces the clock skew between the core A and the core B.  
         [0051]     It should be mentioned that the present invention is not limited to the aforementioned embodiments, and various changes may be made therein. For example, in the aforementioned first embodiment, the power supply circuit  20  generates two kinds of power supply voltages and supplies them to the core A, but it may generate and supply more than two kinds of power supply voltages. Namely, the power supply circuit  20  may change the previously set power supply voltage stepwise and supply the stepwise changed power supply voltage.  
         [0052]     In this case, the selector C 22  is required to select one clock signal from plural clock signals and output it according to the change performed by the power supply circuit  20 . For this purpose, plural clock signals with different propagation delays need to be inputted to the selector C 22 . Delay times of the clock signals before they are inputted to the selector C 22  need to be designed properly so that the clock skew between the core A and the core B is reduced.  
         [0053]     The buffers used in the aforementioned respective embodiments are an example of delay elements for the clock signal and can be realized also by other elements which have a comparable function.