Abstract:
The present invention provides an improved shared amplifier circuitry and method of operation which minimizes offset and column to column fixed pattern noise during a read out operation. The circuit improves the consistency of the pixel to pixel output of the pixel array and increases the dynamic range of the pixel output and saves chip area. This is accomplished by simultaneously sampling and storing charge accumulated signals from a first and a second desired pixel from a respective first and second column. The circuit amplifies the first charge signal and then samples and amplifies the reset signal of the first desired pixel and subsequently outputs the amplified first charge signal and the reset signal. Then the circuit amplifies the second charge signal and the reset signal of the first desired pixel and subsequently outputs the amplified first charge signal and the reset signal.

Description:
FIELD OF THE INVENTION  
         [0001]    The invention relates generally to improved semiconductor imaging devices and in particular to an imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to a CMOS active pixel sensor (APS) imager having an array of pixel cells and to the column circuitry for reading the cells.  
         BACKGROUND OF THE INVENTION  
         [0002]    There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. An exemplary pixel circuit of a CMOS active pixel sensor (APS) is described below with reference to FIG. 1. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors. The FIG. 1 circuit  100  exemplary pixel cell  150  is a 3T APS, where the 3T is commonly used in the art to designate use of three transistors to operate the pixel. A 3T pixel has a photodiode  162 , a reset transistor  184 , a source follower transistor  186 , and a row select transistor  188 . It should be understood that while FIG. 1 shows the circuitry for operation of a single pixel, and that in practical use there will be an M times N array of identical pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.  
           [0003]    The photodiode  162  converts incident photons to electrons which collect at node A. A source follower transistor  186  has its gate connected to node A and thus amplifies the signal appearing at Node A. When a particular row containing cell  150  is selected by a row selection transistor  188 , the signal amplified by transistor  186  is passed on a column line  170  to the readout circuitry. The photodiode  162  accumulates a photo-generated charge in a doped region of the substrate. It should be understood that the CMOS imager might include a photogate or other photoconversion device, in lieu of a photodiode, for producing photo-generated charge.  
           [0004]    A reset voltage source Vrst is selectively coupled through reset transistor  184  to node A. The gate of reset transistor  184  is coupled to a reset control line  190  which serves to control the reset operation in which Vrst is connected to node A. Vrst may be Vdd. The row select control line  160  is coupled to all of the pixels of the same row of the array. Voltage source Vdd is coupled to a source following transistor  186  and its output is selectively coupled to a column line  170  through row select transistor  188 . Although not shown in FIG. 1, column line  170  is coupled to all of the pixels of the same column of the array and typically has a current sink at its lower end. The gate of row select transistor  188  is coupled to row select control line  160 .  
           [0005]    As know in the art, a value is read from pixel  150  in a two step process. During a charge integration period the photodiode  162  converts photons to electrons which collect at the node A. The charges at node A are amplified by source follower transistor  186  and selectively passed to column line  170  by row access transistor  188 . During a reset period, node A is reset by turning on reset transistor  184  and the reset voltage is applied to node A and read out to column line  170  by the source follower transistor  186  through the activated row select transistor  188 . As a result, the two different values—the reset voltage Vrst and the image signal voltage Vsig—are readout from the pixel and sent by the column line  170  to the readout circuitry where each is sampled and held for further processing as known in the art.  
           [0006]    All pixels in a row are read out simultaneously onto respective column lines  170  and the column lines are activated in sequence for reset and signal voltage read out. The rows of pixels are also read out in sequence onto the respective column lines.  
           [0007]    [0007]FIG. 2 shows a CMOS active pixel sensor integrated circuit chip that includes an array of pixels  230  and a controller  232  which provides timing and control signals to enable reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M times N pixels, with the size of the array  230  depending on a particular application. The imager is read out a row at a time using a column parallel readout architecture. The controller  232  selects a particular row of pixels in the array  230  by controlling the operation of row addressing circuit  234  and row drivers  240 . Charge signals stored in the selected row of pixels are provided on the column lines  170  (FIG. 1) to a readout circuit  242  in the manner described above. The pixel signal read from each of the columns then can be read out sequentially using a column addressing circuit  244 . Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated charge signal are provided as respective outputs Vout 1 , Vout 2  of the readout circuit  242 .  
           [0008]    [0008]FIG. 3 more clearly shows the rows and columns  349  of pixels  350 . Each column includes multiple rows of pixels  350 . Signals from the pixels  350  in a particular column can be read out to a readout circuit  351  associated with that column. The read out circuit  351  includes sample and hold circuitry for acquiring the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in the readout circuits  351  then can be read sequentially column-by-column to an output stage  354  which is common to the entire array of pixels  330 . The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals are each supplied to the analog-to-digital converter.  
           [0009]    [0009]FIG. 4 more clearly shows the column readout circuit  351  that includes a sample and hold read out circuit  401  and an amplifier  434 . The FIG. 4 circuit is capable of sampling and holding and then amplifying the Vsig and Vrst values for subsequent use by an output stage  354  (FIG. 3).  
           [0010]    For example, a Vsig from a desired pixel (“Vsig 1 ”) coupled to column line  402  is stored on C 1  capacitor  418  and a Vrst from the desired pixel (“Vrst 1 ”) is stored on capacitor  420 . Then the Vsig 1  stored on C 1  capacitor  418  is transferred and amplified by amplifier  434  to capacitor  462 . Then Vrst 1  is transferred and amplified by amplifier  434  to capacitor  460 , at which point the Vrst and Vsig signals for the desired pixel are readout to an output stage  354 . (FIG. 3).  
           [0011]    As seen in FIG. 4, a first column line  402  is switchably coupled through SH 1  switch  410  to the front side of C 1  capacitor  418 . The backside of C 1  capacitor  418  is coupled to ground. The front side of C 1  capacitor  418  is also switchably coupled through SH 3  switch  414  through a buffer  430  to the front side of capacitor  438 . The backside of capacitor  438  is coupled to a first input line to an amplifier  434 . Vref is coupled to the second input line to amplifier  434 . The first input line to the amplifier  434  is switchably coupled through Amp Rst switch  436  to the output of amplifier  434 . The first input line to the amplifier  434  is also coupled through Amp Rst switch  436  to the output of amplifier  434 . The output of amplifier  434  is switchably coupled through SHR 1  switch  472  to a frontside of capacitor  460 . The backside of capacitor  460  is coupled to ground. The frontside of capacitor  460  is switchably coupled through SHR 2  switch  476  to a first input to output stage  354 . The output of amplifier  434  is also switchably coupled through SHS 1  switch  474  to a frontside of capacitor  462 . The backside of capacitor  462  is coupled to ground. The frontside of capacitor  462  is switchably coupled through SHR 2  switch  478  to a second input to output stage  354 .  
           [0012]    The operation of the FIG. 4 circuit is now described with reference to the simplified signal timing diagram of FIG. 5 (assuming a readout from a 3T pixel). To store Vsig 1  on C 1  capacitor  418  while the pixel is in the signal sampling phase, a pulse signal SH 1  is applied which temporarily closes the SH 1  switch  410  and couples the desired pixel with the front side of capacitor  418  through the column line  402 . Thus, Vsig 1  is stored on C 1  capacitor  418 . After the desired pixel is pulsed by a pixel reset signal, the pixel is in reset signal sampling phase. To store Vrst 1  on capacitor  420  pulse signal SH 2  is applied which temporarily closes the SH 2  switch  412  and couples the desired pixel with the front side of capacitor  420  through the column line  402 . Thus, Vrst 1  is stored on C 2  capacitor  420 .  
           [0013]    To transfer Vsig 1  through the amplifier  434 , pulse signals Amp Rst, SH 3 , and SHS 1  are applied which temporarily closes SH 3 , Amp Rst, and SHS 1  switches  414 ,  436 , and  474  and forces the signal stored on the front side of capacitor  418  and carried on line  402  through amplifier  434  after going through a buffer  430  and a capacitor  438 . The signal output from amplifier  434  is stored on capacitor  462 . Thus, the amplified Vsig 1  signal is stored on capacitor  462 .  
           [0014]    To transfer Vrst 1  through the amplifier  434 , pulse signals SH 4  and SHR 1  are applied which temporarily closes SH 4  and SHR 1  switches  416  and  472  and forces the signal stored on the front side of capacitor  420  and carried on line  402  through amplifier  434  after going through a buffer  430  and a capacitor  438 . The signal output from amplifier  434  is stored on capacitor  460 . Thus, the amplified Vrst 1  signal is stored on capacitor  460 . Vsig 1  and Vrst 1  signals are transferred to output stage  354  by applying pulses SHR 2 , SHS 2  enabling and closing respective SHR 2 , SHS 2  switches  476 ,  478 .  
           [0015]    In pixels arrays, where real estate is precious it would be desirable to shared the column readout circuitry among a plurality of column lines.  
         BRIEF SUMMARY OF THE INVENTION  
         [0016]    The present invention provides an shared amplifier circuitry and method of operation. The circuit eliminates circuitry and improves the consistency of the pixel to pixel output of the pixel array and reducing readout noise, thereby increasing the dynamic range of the pixel output. This is accomplished by sampling and storing both charge signals from a first and a second desired pixel. Then the circuit samples and stores both reset signals from the first and the second desired pixels. The circuit then amplifies the charge and reset signals from the first desired pixel and transfers both signals to a downstream circuit. Subsequently, the circuit then amplifies the charge and reset signals from the second desired pixel and transfers both signals to a downstream circuit.  
           [0017]    In an additional embodiment, a shared amplifier circuitry is accomplished by sampling and storing both charge signals from the first and the second desired pixels. The circuit transfers and amplifies the charge signal from the first desired pixel to a second storage area. The circuit then samples and stores the reset signal of the first desired pixel and subsequently transfers and amplifies the reset signal to a third storage area. The amplified charge and reset signals of the first desired pixel are readout. Subsequently the circuit transfers and amplifies the charge signal from the second desired pixel to the second storage area and transfers and amplifies the reset signal of the first desired pixel to a third storage area. The amplified charge signal of the second desired pixel and the amplified reset signal of the first desired pixel can then be readout. Respective buffer circuits are provided for each of the column lines to reduce column to column fixed pattern noise.  
           [0018]    These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]    [0019]FIG. 1 is a prior art active pixel;  
         [0020]    [0020]FIG. 2 is a block diagram of a prior art CMOS active sensor chip;  
         [0021]    [0021]FIG. 3 is a block diagram of a prior art array of active pixels and an associated readout circuit;  
         [0022]    [0022]FIG. 4 is a prior art column readout circuit;  
         [0023]    [0023]FIG. 5 is a simplified timing diagram associated with the circuitry of FIG. 4;  
         [0024]    [0024]FIG. 6 is a block diagram of an array of active pixels and an associated readout circuit;  
         [0025]    [0025]FIG. 7 is a two column shared amplifier readout circuitry in accordance with an exemplary embodiment of the invention;  
         [0026]    [0026]FIG. 8 is a simplified timing diagram associated with the circuitry of FIG. 7;  
         [0027]    [0027]FIG. 9 is a two column shared amplifier readout circuitry in accordance with another exemplary embodiment of the invention;  
         [0028]    [0028]FIG. 10 is a simplified timing diagram associated with the circuitry of FIG. 9; and  
         [0029]    [0029]FIG. 11 is a block diagram representation of a processor-based system incorporating a CMOS imaging device in accordance with an exemplary embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0030]    In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or other changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention.  
         [0031]    To minimize die space, signal level loss, and column to column noise, the present invention utilizes a shared column amplifier circuit using two pixels from two columns, a first desired pixel from a first column and a second desired pixel from a second column as the sources of input to a shared amplifier.  
         [0032]    A first embodiment of the invention in which a readout circuit is shared between two column lines is shown and described with reference to FIGS.  6 - 8 . As shown in FIG. 6, each readout circuit  652  is shared by two columns  349  of pixels  350 . The read out circuit  652  includes sample and hold circuitry for acquiring the pixel reset (Vrst) and integrated charge signals (Vsig). Signals stored in the readout circuits  652  then can be read sequentially column-by-column to an output stage  354  which is common to the entire array of pixels  330 . The analog output signals can then be sent, for example, to a differential analog circuit and which subtracts the reset and integrated charge signals and sends them to an analog-to-digital converter (ADC), or the reset and integrated charge signals are each supplied to the analog-to-digital converter.  
         [0033]    [0033]FIG. 7 more clearly illustrates the construction of readout circuit  652  of FIG. 6. The column readout circuit  652  includes sample and hold read out circuits  701 ,  703  with a shared amplifier  434  for two columns, shown as column lines  702 ,  704 . The FIG. 7 circuit is capable of simultaneously sampling and holding and then amplifying the Vrst and Vsig values for two pixels coupled to column lines,  702 ,  704  for subsequent use by the output stage  354 . The two column lines  702 ,  704  may be, but need not be, from adjacent columns of pixels.  
         [0034]    A Vsig from a first desired pixel (“Vsig 1 ”) coupled to column line  702  is stored on C 1  capacitor  718  at the same time that a Vsig from a second desired pixel (“Vsig 2 ”) coupled to a second column line  704  is stored on C 3  capacitor  719 . Then a Vrst from the first desired pixel (“Vrst 1 ”) is stored on C 2  capacitor  720  at the same time that a Vrst from the second desired pixel (“Vrst 2 ”) is stored on C 4  capacitor  721 . Then the Vsig 1  stored on C 1  capacitor  718  is transferred and amplified by amplifier  434  to capacitor  462 . Then Vrst 1  stored on C 2  capacitor  720  is transferred and amplified by amplifier  434  to capacitor  460 , at which point the Vrst and Vsig signals for the first desired pixel are readout to an output stage  354 . After the signal from the first desired pixel are read out, the Vsig 2  stored on C 3  capacitor  719  is transferred and amplified by amplifier  434  to capacitor  462 . Then Vrst 2  stored on C 4  capacitor  721  is transferred and amplified by amplifier  434  to capacitor  460 , at which point the Vrst and Vsig signals for the second desired pixel are readout to an output stage  354 .  
         [0035]    As seen in FIG. 7, a first column line  702  is switchably coupled through SH 1  switch  710  to the front side of C 1  capacitor  718 . The backside of C 1  capacitor  718  is coupled to ground. The front side of C 1  capacitor  718  is also switchably coupled through SH 3  switch  714  through a buffer  430  to the front side of capacitor  438 . The first column line  702  is also switchably coupled through SH 2  switch  712  to the front side of C 2  capacitor  720 . The backside of C 2  capacitor  720  is coupled to ground. The front side of C 2  capacitor  720  is also switchably coupled through SH 4  switch  716  through a buffer  430  to the front side of capacitor  438 .  
         [0036]    A second column line  704  is switchably coupled through SH 5  switch  711  to the front side of C 3  capacitor  719 . The backside of C 3  capacitor  719  is coupled to ground. The front side of C 3  capacitor  719  is also switchably coupled through SH 7  switch  715  through a buffer  430  to the front side of capacitor  438 . The second column line  704  is also switchably coupled through SH 6  switch  713  to the front side of C 4  capacitor  721 . The backside of C 4  capacitor  721  is coupled to ground. The front side of C 4  capacitor  721  is also switchably coupled through SH 8  switch  717  through a buffer  430  to the front side of capacitor  438 .  
         [0037]    The backside of capacitor  438  is coupled to a first input line to an amplifier  434 . Vref is coupled to the second input line to amplifier  434 . The first input line to the amplifier  434  is switchably coupled through Amp Rst switch  436  to the output of amplifier  434 . The first input line to the amplifier  434  is also coupled through Amp Rst switch  436  to the output of amplifier  434 . The output of amplifier  434  is switchably coupled through SHR 1  switch  472  to a frontside of capacitor  460 . The backside of capacitor  460  is coupled to ground. The frontside of capacitor  460  is switchably coupled through SHR 2  switch  476  to a first input to output stage  354 . The output of amplifier  434  is also switchably coupled through SHS 1  switch  474  to a frontside of capacitor  462 . The backside of capacitor  462  is coupled to ground. The frontside of capacitor  462  is switchably coupled through SHR 2  switch  478  to a second input to output stage  354 .  
         [0038]    The operation of the FIG. 7 circuit is now described with reference to the simplified signal timing diagram of FIG. 8 (assuming a readout from a 3T pixel). To store Vsig 1  on C 1  capacitor  718  and at the same time store Vsig 2  on C 3  capacitor  719  while the pixels are in the signal sampling phase, pulse signals SH 1 , SH 5  are applied which temporarily closes the SH 1 , SH 5  switch  710 ,  711  which respectively couples the first desired pixel with the front side of C 1  capacitor  718  through the column line  702  and the second desired pixel with the front side of C 3  capacitor  719  through the column line  704 . Thus, Vsig 1  is stored on C 1  capacitor  718  and Vsig 2  is stored on C 3  capacitor  719 . After the desired pixels are pulsed by a pixel reset signal, the pixels are in reset signal sampling phase. To store Vrst 1  on C 2  capacitor  720  a pulse signal SH 2  is applied which temporarily closes the SH 2  switch  712  and couples the first desired pixel with the front side of C 2  capacitor  720  through the column line  702 . To store Vrst 2  on C 4  capacitor  721  at the same time that Vrst 1  is stored, a pulse signal SH 6  is applied which temporarily closes the SH 6  switch  713  and couples the second desired pixel with the front side of C 4  capacitor  721  through the column line  704 . Thus, Vrst 1  is stored on C 2  capacitor  720  and Vrst 2  is stored on C 4  capacitor  721 .  
         [0039]    To transfer Vsig 1  through the amplifier  434 , pulse signals Amp Rst, SH 3 , and SHS 1  are applied which temporarily closes SH 3 , Amp Rst, and SHS 1  switches  436 ,  714 , and  474  and forces the signal stored on the front side of C 1  capacitor  718  and carried on line  702  through amplifier  434  after going through a buffer  430  and a capacitor  438 . The signal output from amplifier  434  is stored on capacitor  462 . Thus, the amplified Vsig 1  signal is stored on capacitor  462 . To transfer Vrst 1  through the amplifier  434 , pulse signals SH 4  and SHR 1  are applied which temporarily closes SH 4  and SHR 1  switches  716  and  472  and forces the signal stored on the front side of C 2  capacitor  720  and carried on line  702  through amplifier  434  after going through a buffer  430  and a capacitor  438 . The signal output from amplifier  434  is stored on capacitor  460 . Thus, the amplified Vrst 1  signal is stored on capacitor  460 . Vsig 1  and Vrst 1  signals are transferred to output stage  354  by applying pulses SHR 2 , SHS 2  enabling and closing respective SHR 2 , SHS 2  switches  476 ,  478 .  
         [0040]    To transfer Vsig 2  through the amplifier  434 , pulse signals Amp Rst, SH 7 , and SHS 1  are applied which temporarily closes SH 7 , Amp Rst, and SHS 1  switches  436 ,  715 , and  474  and forces the signal stored on the front side of C 3  capacitor  719  and carried on line  704  through amplifier  434  after going through a buffer  430  and a capacitor  438 . The signal output from amplifier  434  is stored on capacitor  462 . Thus, the amplified Vsig 2  signal is stored on capacitor  462 . To transfer Vrst 2  through the amplifier  434 , pulse signals SH 8  and SHR 1  are applied which temporarily closes SH 8  and SHR 1  switches  717  and  472  and forces the signal stored on the front side of C 4  capacitor  721  and carried on line  704  through amplifier  434  after going through a buffer  430  and a capacitor  438 . The signal output from amplifier  434  is stored on capacitor  460 . Thus, the amplified Vrst 2  signal is stored on capacitor  460 . Vsig 2  and Vrst 2  signals are transferred to output stage  354  by applying pulses SHR 2 , SHS 2  enabling and closing respective SHR 2 , SHS 2  switches  476 ,  478 .  
         [0041]    Therefore, column readout circuit  652  uses a shared column amplifier and reads out Vrst and Vsig signals values from two pixels and delivers them to downstream circuit  354 .  
         [0042]    [0042]FIG. 9 illustrates a shared column amplifier  652  (FIG. 6) in accordance with another embodiment of the present invention. This embodiment has an initial storage area, capacitors  918 ,  920 , which is capable of receiving and storing two simultaneously received signals from column lines  902 ,  904 , a shared amplifier  434 , and a secondary storage area, capacitors  460 ,  462 , for storing the amplified sample and the reset signals. Since Vrst of the first pixel and Vrst of the second desired pixel are substantially equivalent, Vrst of the first desired pixel coupled to column line  902  can be used for the Vrst of the second desired pixel coupled to column line  904  and visa versa.  
         [0043]    As seen in FIG. 9, first column line  902  is coupled to the front side of C 1  capacitor  918 . The backside of C 1  capacitor  918  is switchably coupled through SH 1  switch  914  to a first input line of an amplifier  434 . Vref is coupled to the second input line to amplifier  434 . A second column line  904  is coupled to the front side of C 2  capacitor  920 . The backside of C 2  capacitor  920  is switchably coupled through SH 2  switch  916  to a first input line of an amplifier  434 .  
         [0044]    The first input line to the amplifier  434  is switchably coupled through Amp Rst switch  436  to the output of amplifier  434 . The output of amplifier  434  is switchably coupled through SHR 1  switch  472  to a frontside of capacitor  460 . The backside of capacitor  460  is coupled to ground. The frontside of capacitor  460  is switchably coupled through SHR 2  switch  476  to a first input to output stage  354 . The output of amplifier  434  is also switchably coupled through SHS 1  switch  474  to a frontside of capacitor  462 . The backside of capacitor  462  is coupled to ground. The frontside of capacitor  462  is switchably coupled through SHR 2  switch  478  to a second input to output stage  354 .  
         [0045]    The operation of the FIG. 9 circuit is now described with reference to the simplified signal timing diagram of FIG. 10 (assuming a readout from a 3T pixel). The C 1 , C 2  capacitors  918 ,  920  and the amplifier  434  are precharged by applying Amp Rst, SH 1 , and SH 2  pulses, which temporarily closes Amp Rst, SH 1 , and SH 2  switch  436 ,  914 ,  916 .  
         [0046]    To simultaneously store Vsig 1  on C 1  capacitor  918  and Vsig 2  on C 2  capacitor  920  while the pixels are in the signal sampling phase, the first desired pixel is coupled with the front side of capacitor  918  through the column line  902  and the second desired pixel is coupled with the front side of capacitor  920  through the column line  904 . Thus, Vsig 1  is stored on C 1  capacitor  918  and Vsig 2  is stored on C 2  capacitor  920 . The Vsig 1  signal stored on C 1  capacitor  918  is carried through to the secondary storage area by applying pulse signals SH 1 , SHS 1  which temporarily closes the SH 1  switch  914  and the SHS 1  switch  474 , and couples capacitor  462  with C 1  capacitor  918  through amplifier  434 . Thus the Vsig 1  is stored on capacitor  462 .  
         [0047]    After the first and second desired pixels are pulsed by a pixel reset signal, the pixels are in reset signal sampling phase. C 1  capacitor  918  couples with the first desired pixel through the first column line  902  thereby storing Vrst 1  on C 1  capacitor  918 . The Vrst 1  signal stored on C 1  capacitor  918  is carried through to the secondary storage area by applying pulse signals SH 1 , SHR 1  which temporarily closes the SH 1  switch  914  and the SHR 1  switch  472 , and couples capacitor  460  with C 1  capacitor  918  through amplifier  434 . Thus the Vrst 1  is stored on capacitor  460 . Vrst 1  and Vsig 1  signals are transferred to output stage  354  by applying pulses SHR 2 , SHS 2  enabling and closing respective SHR 2 , SHS 2  switches  476 ,  478 .  
         [0048]    After the Vrst 1  and Vsig 1  signals of the first desired pixel are amplified and transferred to the output stage  354 , the Vrst 1  signal of the first desired pixel and Vsig 2  signal of the second desired pixel are amplified and transferred to the output stage  354 .  
         [0049]    The C 1  capacitor  918  and the amplifier  434  are precharged by applying Amp Rst, SH 1  pulses which temporarily closes Amp Rst, SH 1  switch  436 ,  914 . C 1  capacitor  918  couples with the first desired pixel through the first column line  902  thereby storing Vrst 1  on C 1  capacitor  918 . The Vrst 1  signal stored on C 1  capacitor  918  is carried through to the secondary storage area by applying pulse signals SH 1 , SHS 1  which temporarily closes the SH 1  switch  914  and the SHS 1  switch  474 , and couples capacitor  462  with C 1  capacitor  918  through amplifier  434 . Thus the Vrst 1  is stored on capacitor  462 . The Vsig 2  signal stored on C 2  capacitor  920  is carried through to the secondary storage area by applying pulse signals SH 2 , SHR 1  which temporarily closes the SH 2  switch  916  and the SHR 1  switch  472 , and couples capacitor  460  with C 2  capacitor  920  through amplifier  434 . Thus the Vsig 2  is stored on capacitor  460 . Vrst 1  and Vsig 2  signals are transferred to output stage  354  by applying pulses SHR 2 , SHS 2  enabling and closing respective SHR 2 , SHS 2  switches  476 ,  478 . Thus, the Vrst 1  of the first desired pixel and the Vsig 2  of the second desired pixel are amplified and transferred to the output stage  354 . Although described in terms of reading out Vrst 1  twice, once with Vsig 1  and once with Vsig 2 , the invention is not so limited and may transfer Vsig 2  from C 2  capacitor  920  and store in capacitor  460 , and then sample Vrst 2  which is amplified and stored in capacitor  462 .  
         [0050]    Although shown as variable capacitors, capacitors  418 ,  420  may be fixed capacitors. The variable capacitors allow different gains to be applied to the signals stored in the C 1 , C 3  capacitors  418 ,  420  for use in different situations.  
         [0051]    Thus, a column circuit readout with a shared amplifier between columns is provided that reduces column to column noise, signal loss and die area.  
         [0052]    The method and apparatus aspects of the invention are embodied in an image device  1140  shown in FIG. 11 which provides an image output signal. The image output signal can also be used in a processor system  1100 , also illustrated in FIG. 11. A processor based system, such as a computer system, for example, generally comprises a central processing unit (CPU)  1110 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices  1150  over one or more buses  1170 . The CPU  1110  also exchanges data with random access memory (RAM)  1160  over the one or more buses  1170 , typically through a memory controller. The processor system may also include peripheral devices such as a floppy disk drive  1120  and a compact disk (CD) ROM drive  1130  which also communicate with CPU  1110  over one or more buses  1170 .  
         [0053]    While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. Although the embodiments discussed above describe specific numbers of transistors, photodiodes, conductive lines, or pixel type (e.g., 3T, 4T), etc. the present invention is not so limited. Furthermore, many of the above embodiments described are shown with respect to the operation of the shared amplifier between two adjacent columns, the spirit of the invention is not so limited. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the claims.