Abstract:
An interconnect structure is disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The current application is related in some aspects to co-pending United States patent application Ser. No. 11/307,642, with corresponding publication No. US 2008/0012142A1 (filed on Feb. 15, 2006), which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     The subject matter disclosed herein relates to a semiconductor interconnect structure and methods of forming the same. 
     BRIEF DESCRIPTION OF THE INVENTION 
     An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer. 
     A first aspect of the disclosure provides an interconnect structure comprising: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer. 
     A second aspect of the disclosure provides a method comprising: a method comprising: forming a via opening in both a dielectric barrier layer and an inter-level dielectric layer over the dielectric barrier layer; forming a recess in a first metal layer located below the dielectric barrier layer; selectively depositing a diffusion barrier layer in the recess; forming a liner layer over the diffusion barrier layer, the dielectric barrier layer, and the inter-level dielectric layer; and forming a second metal layer over the liner layer. 
     A third aspect of the disclosure provides a method of forming an interconnect structure using a dual damascene process, the method comprising: forming a first trench in a substrate; forming a liner layer within the trench; forming a first metal layer over the liner layer; forming a dielectric barrier layer over the substrate, the liner layer, and the first metal layer; forming an inter-level dielectric layer over the dielectric barrier layer; forming a via opening and a second trench in the inter-level dielectric layer, the via opening extending between the first metal layer, the dielectric barrier layer, and the substrate; forming a diffusion barrier layer within the via opening, the diffusion barrier layer located over the first metal layer; forming a via liner layer over the diffusion barrier layer, the dielectric barrier layer and the inter-level dielectric layer; and forming a second metal layer over the via liner layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which: 
         FIGS. 1-4  show cross-sectional views of processing steps in forming an interconnect structure of an embodiment of the invention. 
     
    
    
     It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     As used herein, the term “deposition” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. 
     Turning to the drawings,  FIG. 1  shows an interconnect structure  100  which may include a substrate  110 , a dielectric barrier layer  120  over substrate  110 , and an inter-level dielectric layer  130  over dielectric barrier layer  120 . Various methods may be employed to create interconnect structure  100 , however, one conventional method may include providing substrate  110  including first trench  140 . First trench  140  may be formed using any conventional techniques known in integrated circuit fabrication. Optionally, an additional trench  140  (shown in phantom) may be formed in substrate  110 , using similar techniques to forming of first trench  140 . Further, the method may include depositing a first liner layer  150  within first trenches  140  and depositing a first metal layer  160  over first liner layer  150 . First metal layer  160  may be formed of, for example, copper and/or copper alloys such as CuAl and CuMn. The method may further include providing dielectric barrier layer  120  over substrate  110 , first liner layer  150  and first metal layer  160 . Dielectric barrier layer  120  may be deposited using conventional techniques described herein and/or those known in the art. Additionally, the method may include forming inter-level dielectric layer  130  over dielectric barrier layer  120 . As with dielectric barrier layer  120 , inter-level dielectric layer  130  may be deposited using conventional techniques described herein and/or those known in the art. Further, this method may include forming a via opening  170  and a second trench  180 . Via opening  170  and second trench  180  may be formed, for example, using conventional dual damascene techniques, or those detailed in co-pending United States patent application number US 2008/0012142A1 and U.S. Pat. No. 7,064,064. For example, via opening  170  and second trench  180  may be formed by reactive ion etching (RIE). Optionally, additional via opening  170  may be formed (shown in phantom) using similar techniques to forming of via opening  170 . Also, optional inter-level trench  190  may be formed in inter-level dielectric layer  130  according to conventional techniques and/or those described herein. 
     Turning to  FIG. 2 , interconnect structure  100  of  FIG. 1  is shown after formation of a recess  175  in first metal layer  160  located below dielectric barrier layer  120 . Recess  175  may be formed, for example, using a chemical recess etch of first metal layer  160 . In the case where first metal layer  160  includes copper, the chemical recess etch may be any etching technique capable of forming recess  175  in copper. 
     Turning to  FIG. 3 , interconnect structure  100  of  FIG. 2  is shown after forming of a diffusion barrier layer  210  within recess  175 . Diffusion barrier layer  210  may be deposited after the chemical recess etch of first metal layer  160 , described with reference to  FIG. 2 . Diffusion barrier layer  210  may be formed over first metal layer  160 . In one embodiment, diffusion barrier layer  210  may be selectively deposited over first metal layer  160 . Diffusion barrier layer  210  may be formed of, for example, cobalt tungsten-phosphide (CoWP), cobalt tungsten-boride (CoWB), or ruthenium (Ru). However, diffusion barrier layer  210  may be formed of any metal capable of preventing or retarding (slowing down) copper diffusion. Using CoWP, CoWB, or Ru as diffusion barrier layer  210  may allow for depositing of diffusion barrier layer  210  only over exposed portions of first metal layer  160 . As shown in  FIG. 3 , recess  175  is located below dielectric barrier layer  120 , causing a portion of diffusion barrier layer  210  to be located below dielectric barrier layer  120 . In one embodiment, diffusion barrier layer  210  may be entirely located below dielectric barrier layer  120 . In any case, diffusion barrier layer  210  prevents or retards exposure of first metal layer  160  to via opening  170 . 
     Turning to  FIG. 4 , interconnect structure  100  of  FIG. 3  is shown after forming of a second liner layer  220  and second metal layer  230 . After forming of diffusion barrier layer  210 , second liner layer  220  may be formed over diffusion barrier layer  210 , dielectric barrier layer  120  and inter-level dielectric layer  130 . Second liner layer  220  may be formed of, for example, tantalum nitride (TaN), tantalum (Ta), and/or ruthenium (Ru). However, second liner layer  220  may be formed of other materials that are thermodynamically stable with copper (Cu). Second liner layer  220  may be deposited using, for example, chemical vapor deposition (CVD) or other conventional methods. After deposition of second liner layer  220 , second metal layer  230  may be formed over second liner layer  220 . Second metal layer  230  may be formed of, for example copper. However, second metal layer  230  may also be formed of other electrically conductive materials conventionally used in integrated circuits. In one embodiment, second metal layer  230  may be formed of copper, and may be deposited via dual damascene metallization over second liner layer  220 , thereby filling via opening  170  and second trench  180  ( FIG. 2 ). In this case, second metal layer  230  may be deposited by electrodeposition in via opening  170  and second trench  180 , thereby requiring removal of an undesired portion of second metal layer  230 . This may be accomplished, for example, by depositing a thin film (plating) and using chemical mechanical planarization (CMP) to remove the undesired portion of second metal layer  230 . Plating and CMP may be performed in any conventional manner used in integrated circuit fabrication. Also shown in  FIG. 3  are third liner layer  240  and third metal layer  250  formed within inter-level trench  190 . Third liner layer  240  and third metal layer  250  may be formed of substantially similar materials as second liner layer  220  and second metal layer  230 , and may be formed in a similar fashion. Further, third liner layer  240  and second liner layer  220  may be formed substantially simultaneously, while third metal layer  250  and second metal layer  230  may be formed substantially simultaneously. 
     The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     The foregoing description of various aspects of the disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the disclosure as defined by the accompanying claims.