Abstract:
A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This patent application is a divisional application of and claims priority to U.S. patent application Ser. No. 13/070,483, filed on Mar. 24, 2011, and entitled “metal-gate CMOS device” the entire contents of which are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates generally to semiconductor device and fabrication method thereof. More particularly, the present invention relates to a dual work-function metal-gate CMOS device and fabrication method thereof. 
         [0004]    2. Description of the Prior Art 
         [0005]    The continued scaling of CMOS devices into sub-40 nm technology will rely on a fundamental change in transistor gate stack materials. Over the past few years, research in this area has focused on identifying candidate materials to replace polysilicon and SiO 2  as the gate electrode and gate dielectric, respectively. Critical requirements for novel gate electrode materials include thermal stability with the gate dielectric and suitable values for the interfacial work function. The latter requirement of obtaining complementary gate work functions on a single wafer is being perceived as a major process integration challenge. 
         [0006]    Metal-gate electrodes bring about several advantages compared to traditional polysilicon gates as CMOS technology continues to scale beyond the 40 nm node. These include reduction in poly-depletion effect, reduction in sheet resistance, and potentially better thermal stability on high-K gate dielectrics. The main challenge is that, unlike with polysilicon, one would have to use two metallic materials (bi-layer metal) with different work functions in order to achieve the right threshold voltages for both NMOS and PMOS. 
         [0007]    The conventional dual metal gate methods are categorized into the gate-first process and the gate-last process. Among the two main approaches, the gate-last process is able to avoid processes of high thermal budget and to provide wider material choices for the high-K gate dielectric layer and the metal gate, and thus gradually replaces the gate-first process. In a conventional gate-last process, a dummy gate (or “replacement gate”) is formed on a substrate and followed by steps of forming a conventional MOS transistor and forming an inter-layer dielectric (ILD) layer. Subsequently, the dummy gate is removed to form a gate trench. Thereafter, the gate trench is filled with metal layers required for different conductivity types. 
         [0008]    It is well known in the art that the degree of difficulty for fabricating a well-controlled double work function metal is immense as the process often involves complicated integration between NMOS device and PMOS device. The difficulty increases even more as the thickness and materials used in double work function metal gates requires a much more strict demand. Hence, how to successfully integrate the fabrication of a conventional double work function metal gate transistor so as to reduce its complexity to the standard CMOS process flow has become an important study in the field. 
       SUMMARY OF THE INVENTION 
       [0009]    It is one objective of the invention to provide an improved method for fabricating a dual work-function metal-gate CMOS device, which integrates embedded SiGe/SiC epitaxial processes and is capable of simplifying the CMOS fabrication steps and complexity, thereby reducing manufacture cost. 
         [0010]    According to one aspect of the invention, a method for fabricating a metal-gate CMOS device is provided. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first lightly doped drain (LDD) is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure. 
         [0011]    After forming the second embedded epitaxial layer, a first contact hole etch stop layer (CESL) on the substrate is deposited in a blanket manner to cover the first and second regions. A first dielectric layer is then formed on the first CESL. A chemical mechanical polishing (CMP) process is performed to remove a portion of the first dielectric layer and a portion of the first CESL to expose the first and second dummy gate structures. The first and second dummy gate structures is then removed to thereby form a first gate trench and a second gate trench. A first gate dielectric layer and a first metal gate are formed in the first gate trench. A second dielectric layer and a second metal gate are formed in the second gate trench. 
         [0012]    After forming the first and second metal gates, a second dielectric layer is formed on the substrate. The first and second dielectric layers, the first CESL and the seal layer in the first region are etched to form a first contact hole, and the first and second dielectric layers and the first CESL in the second region are etched to form a second contact hole. A silicide layer is then formed at a bottom of each of the first and second contact holes. The first and second contact holes are filled with a metal layer to thereby form a first contact plug and a second contact plug. 
         [0013]    According to another embodiment of the invention, after forming the second embedded epitaxial layer, the first dielectric layer, the first CESL and the seal layer are removed. A stressed second CESL is deposited. A third dielectric layer is then deposited on the stressed second CESL. The third dielectric layer and the stressed second CESL in the first region are etched to form a first contact hole, and the third dielectric layer and the stressed second CESL in the second region are etched to form a second contact hole. A silicide layer is formed at a bottom of each of the first and second contact holes. The first and second contact holes are filled with a metal layer to thereby form a first contact plug and a second contact plug. 
         [0014]    In one aspect, the present invention provides a metal-gate CMOS device including a substrate having a PMOS region and an NMOS region; a PMOS transistor in the PMOS region of the substrate; an NMOS transistor in the NMOS region of the substrate; a seal layer only masking the PMOS transistor within the PMOS region; and a contact hole etch stop layer (CESL) covering the seal layer within the PMOS region and covering the NMOS transistor within the NMOS region. The PMOS transistor comprises a first metal gate and a first gate dielectric layer. The first gate dielectric layer comprises metal oxide including hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), or hafnium zirconium oxide (HfZrO 2 ). The PMOS transistor further comprises an embedded SiGe epitaxial layer in a source/drain region of the PMOS transistor and an embedded SiC epitaxial layer in a source/drain region of the NMOS transistor. 
         [0015]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  to  FIG. 14  are schematic, cross-sectional diagrams showing a method for fabricating a dual work-function CMOS device in accordance with one preferred embodiment of this invention. 
           [0017]      FIG. 15  to  FIG. 16  are schematic, cross-sectional diagrams showing a method for fabricating a dual work-function CMOS device in accordance with another preferred embodiment of this invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Please refer to  FIG. 1  to  FIG. 14 .  FIG. 1  to  FIG. 14  are schematic, cross-sectional diagrams showing a method for fabricating a dual work-function CMOS device in accordance with one preferred embodiment of this invention. As shown in  FIG. 1 , a substrate  10  such as silicon substrate, silicon-containing substrate, silicon-on-insulator (SOI) substrate or epitaxial substrate is provided. A plurality of shallow trench isolation (STI) structures  12  are provided in the main surface of the substrate  10  to electrically isolate at least one PMOS region  101  and at least one NMOS region  102 . Subsequently, a dummy gate structure  21  and a dummy gate structure  22  are formed on the substrate  10  within the PMOS region  101  and the NMOS region  102  respectively. The dummy gate structure  21  may comprise a gate oxide layer  21   a,  a polysilicon layer  21   b,  a cap layer  21   c  and a sidewall oxide layer  21   d.  The dummy gate structure  22  may comprise a gate oxide layer  22   a,  a polysilicon layer  22   b,  a cap layer  22   c  and a sidewall oxide layer  22   d.  The cap layer  21   c  or the cap layer  22   c  may comprise silicon nitride. After the formation of the dummy gate structures  21  and  22 , a patterned photoresist layer  30  is used to mask the PMOS region  101 . The NMOS region  102  is exposed by the opening  30   a  in the patterned photoresist layer  30 . An LDD ion implantation  130  is carried out to form LDD regions  220  in the substrate  10  next to the dummy gate structure  22  within the NMOS region  102 . 
         [0019]    As shown in  FIG. 2 , after the LDD ion implantation  130 , the patterned photoresist layer  30  is stripped off. Another patterned photoresist layer  40  is used to mask the NMOS region  102 . The PMOS region  101  is exposed by the opening  40   a  in the patterned photoresist layer  40 . An LDD ion implantation  140  is then carried out to form LDD regions  210  in the substrate  10  next to the dummy gate structure  21  within the PMOS region  101 . Thereafter, the patterned photoresist layer  40  is stripped off. Of course, it is to be understood that the LDD step in  FIG. 1  and the LDD step in  FIG. 2  are interchangeable. For example, the LDD regions  210  in the PMOS region  101  may be formed prior to the formation of the LDD regions  220  in the NMOS region  102 . 
         [0020]    As shown in  FIG. 3 , a spacer material layer  50  is deposited over the substrate  10  in a blanket manner. The spacer material layer  50  covers the PMOS region  101  and the NMOS region  102 . According to the preferred embodiment of the invention, the spacer material layer  50  is carbon-doped silicon nitride layer with its dielectric constant that is higher than the dielectric constant of the undoped silicon nitride. As shown in  FIG. 4 , subsequently, an anisotropic dry etching process is performed to etch the spacer material layer to thereby form a pair of spacers  51  on the sidewalls of the dummy gate structure  21  and a pair of spacers  52  on the sidewalls of the dummy gate structure  22 . It is noteworthy that one technical feature of this invention is that the gate sidewall spacers are formed after the LDD implant. 
         [0021]    Subsequently, as shown in  FIG. 5 , a sacrificial silicon nitride layer  54  is deposited over the substrate  10  in a blanket manner. The sacrificial silicon nitride layer  54  covers the PMOS region  101  and the NMOS region  102 . According to the preferred embodiment of this invention, the sacrificial silicon nitride layer  54  may be undoped silicon nitride layer as long as significant etching selectivity is present between the spacer material layer  50  and the sacrificial silicon nitride layer  54 . More specifically, the etching rate of the sacrificial silicon nitride layer  54  is much higher than the etching rate of the spacer material layer  50 . 
         [0022]    As shown in  FIG. 6 , a patterned photoresist layer  60  is used to mask the NMOS region  102 . The PMOS region  101  is exposed by the opening  60   a  in the patterned photoresist layer  60 . Subsequently, a self-aligned etching process is performed to form a sigma-shaped recess  71  in the substrate  10  on each side of the dummy gate structure  21  within the PMOS region  101 . After the formation of the sigma-shaped recess  71 , the patterned photoresist layer  60  is stripped off. As shown in  FIG. 7 , a SiGe epitaxial process is carried out in the PMOS region  101  to grow SiGe epitaxial layer  81  in the sigma-shaped recess  71 . According to the preferred embodiment of this invention, the SiGe epitaxial layer  81  is in-situ doped with P type dopants to thereby form a P +  embedded SiGe epitaxial layer  81 . By doing so, the subsequent source/drain (S/D) ion implantation step for the PMOS and the corresponding P +  S/D photo mask can be spared. 
         [0023]    As shown in  FIG. 8 , an etching process is performed to selectively remove the remaining sacrificial silicon nitride layer  54  from the NMOS region  102 . In other embodiments, however, this etching process may be omitted. Subsequently, a deposition process is performed, for example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, to deposit a silicon nitride seal layer  56  over the substrate  10  in a blanket manner. The silicon nitride seal layer  56  may have a thickness of about 50-200 angstroms. 
         [0024]    As shown in  FIG. 9 , a patterned photoresist layer  80  is used to mask the PMOS region  101 . The NMOS region  102  is exposed by the opening  80   a  in the patterned photoresist layer  80 . Subsequently, an etching process is performed to form a sigma-shaped recess  72  in the substrate  10  on each side of the dummy gate structure  22  within the NMOS region  102 . After the formation of the sigma-shaped recess  72 , the patterned photoresist layer  80  is stripped off. As shown in  FIG. 10 , a SiC epitaxial process is carried out in the NMOS region  102  to grow SiC epitaxial layer  82  in the sigma-shaped recess  72 . According to the preferred embodiment of this invention, the SiC epitaxial layer  82  is in-situ doped with N type dopants to thereby form an N +  embedded SiC epitaxial layer  82 . By doing so, the subsequent source/drain (S/D) ion implantation step for the NMOS and the corresponding N +  S/D photo mask can be spared. It is understood that the embedded SiGe epitaxial steps for PMOS region in  FIGS. 6-7  and the embedded SiC epitaxial for NMOS region in  FIGS. 9-10  are interchangeable. For example, the embedded SiC epitaxial for NMOS region may be carried out prior to the embedded SiGe epitaxial steps for PMOS region in other cases. 
         [0025]    As shown in  FIG. 11 , a contact hole etch stop layer (CESL)  90  such as a silicon nitride layer is deposited over the substrate  10  in a blanket manner. The CESL  90  may have a thickness of about 100-150 angstroms. According to the preferred embodiment of this invention, the CESL  90  does not contain stress. Subsequently, a dielectric layer  91  such as silicon oxide or low-k material is deposited onto the CESL  90 . 
         [0026]    As shown in  FIG. 12 , an upper portion of the dielectric layer  91 , a portion of the CESL  90 , the cap layer  21   c  of the dummy gate structure  21  and the cap layer  22   c  of the dummy gate structure  22  are removed by CMP (chemical mechanical polishing), thereby exposing the polysilicon layer  21   b  of the dummy gate structure  21  and the polysilicon layer  22   b  of the dummy gate structure  22 . Subsequently, the remaining dummy gate structure  21  including the polysilicon layer  21   b  and the gate oxide layer  21   a  and the remaining dummy gate structure  22  including the polysilicon layer  22   b  and the gate oxide layer  22   a  are completely removed by etching methods, thereby forming gate trench  321  and gate trench  322 , which expose the PMOS channel region  121  and the NMOS channel region  122  respectively. 
         [0027]    As shown in  FIG. 13 , a high-k gate dielectric layer  421   a  and a metal gate  421   b  are formed inside the gate trench  321 , and a high-k gate dielectric layer  422   a  and a metal gate  422   b  are formed inside the gate trench  322 . According to the preferred embodiment of this invention, the high-k gate dielectric layers  421   a  and  422   a  may include but not limited to silicon nitride, silicon oxynitride or metal oxide. For example, the aforesaid metal oxide may include but not limited to hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), or hafnium zirconium oxide (HfZrO 2 ). The metal gates  422   a  and  422   b  may include but not limited to titanium nitride, aluminum nitride, tantalum nitride, aluminum or work-function metals. The metal gates  421   b  and  422   b  may be single-layered or composite layer. The high-k gate dielectric layers  421   a  and  422   a  may be formed by CVD methods or ALD methods, for example. The metal gates  421   b  and  422   b  may be formed by CVD methods, PVD methods or sputtering methods. The excess metal layers outside the gate trenches  321  and  322  may be removed by CMP. 
         [0028]    As shown in  FIG. 14 , after the high-k/metal gate (HK/MG) processes, a dielectric layer  92  may be deposited over the substrate in a blanket manner. Subsequently, a contact hole/contact plug forming process is carried out. A dry etching process is performed to etch the dielectric layers  92  and  91 , the CESL  90  and the silicon nitride seal layer  56  within the PMOS region  101  to form the contact holes  92   a  exposing source/drain regions of the PMOS transistor, and etch the dielectric layers  92  and  91 , and the CESL  90  within the NMOS region  102  to form the contact holes  92   b  exposing the source/drain regions of the NMOS transistor. Thereafter, a self-aligned silicidation process is performed to form salicide layers  171  and  172  such as nickel silicide (NiSi) or NiPt at the bottom of the contact hole  92   a  and the bottom of the contact hole  92   b  respectively. Thereafter, metal adhesion layer such as titanium, titanium nitride or tungsten is deposited to fill the contact holes  92   a  and  92   b  thereby forming contact plugs  192   a  and  192   b.  As can be seen in  FIG. 14 , one of the technical features of the invention is that the PMOS region  101  is covered by silicon nitride seal layer  56  and the CESL  90  while the NMOS region  102  is covered by CESL  90 . 
         [0029]      FIG. 15  to  FIG. 16  demonstrate an alternative method for fabricating the dual work-function metal-gate CMOS device in accordance with another embodiment of this invention, wherein  FIG. 15  follows the step as shown in  FIG. 13 . As shown in  FIG. 15 , after the HK/MG process as set forth in  FIG. 13 , the remaining dielectric layer  91 , the CESL  90  and the silicon nitride seal layer  56  are removed. Another CESL  93  and another dielectric layer  94  are deposited onto the substrate  10 . According to the preferred embodiment of this invention, the CESL  93  is a stressed CESL, for example, tensile-stressed or compressive-stressed. The stressed CESL  93  is used to improve the device performance. 
         [0030]    Subsequently, as shown in  FIG. 16 , a contact hole/contact plug forming process is carried out. A dry etching process is performed to etch the dielectric layers  94  and the CESL  93  within the PMOS region  101  to form the contact holes  94   a  exposing source/drain regions of the PMOS transistor, and etch the dielectric layers  94  and the CESL  93  within the NMOS region  102  to form the contact holes  94   b  exposing the source/drain regions of the NMOS transistor. A self-aligned silicidation process is then performed to form salicide layers  271  and  272  such as nickel silicide at the bottom of the contact hole  94   a  and the bottom of the contact hole  94   b  respectively. Thereafter, metal adhesion layer such as titanium, titanium nitride or tungsten is deposited to fill the contact holes  94   a  and  94   b  thereby forming contact plugs  194   a  and  194   b.    
         [0031]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.