Abstract:
Various embodiments of the present invention provide systems and methods for signal equalization, and in some cases analog to digital conversion. For example, an analog to digital converter is disclosed that includes a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for equalizing signals. 
         [0002]    High speed serial communication has become popular and essential in current communication devices. Serializer/deserializer transceivers have been developed to serialize a number (P) of parallel signals each of a given bit rate (B) into a single serial signal with a rate of P*B. The single signal may then be transmitted to a receiver and subsequently deserialized into an output corresponding to the original P parallel signals with the original bit rate B. Common serializer/deserializer transceivers can transmit serial signals up to approximately 10 Gbps. At such high frequencies, channel distortion and attenuation, such as Inter Symbol Interference (ISI), crosstalk, noise, jitter, and the like becomes significant. 
         [0003]    In some cases, signal degradation due to one or more of the aforementioned conditions has been partially mitigated in the transmitter portion of a transmitter/receiver system. For example, a common mitigation technique is to pre-emphasize high frequency components of the transmitted signal, or alternatively to de-emphasize low frequency components of the transmitted signal. In some cases, however, such an approach may increase various noise components resulting in an undesirable decrease in signal to noise ratio. Further, such emphasis/de-emphasis approaches may not be sufficient in many systems and channels to permit the receiver to recover the bit sequence. 
         [0004]    Channel equalization is used in many systems to determine a correct bit sequence from a received transmission. To determine the correct bit value for a given bit period or a received signal, equalization processes are used to modify a current sampled value of the transmitted signal by a function of the values determined during some number of earlier and/or later bit periods. Thus, data dependencies in the transmitted signal can be used to modify a bit value for a given bit period. Alternatively, or in addition, maximum likelihood detectors may be used to determine the correct bit value during a given bit period by calculating the maximum likelihood of the bit value (e.g., either logic-0 or logic-1) based on the values determined during some number of earlier and/or later bit periods. While such maximum likelihood detectors can be very effective in determining a correct bit sequence, they typically require a great deal of semiconductor area to implement and introduce considerable latency to a data receiving process. 
         [0005]    In some cases, analog decision feedback equalizers (analog DFEs) have been utilized in serializer/deserializer transceivers to determine the correct logic value of a sample of a analog input signal for a given bit period in the presence of inter symbol interference. Such analog DFEs are capable of high bandwidth operation, but are typically expensive in terms of both power dissipation and semiconductor area. Equivalent digital circuits are often less power and space intensive. However, existing digital equivalents offer lower bandwidth due to a variety of mathematical operations being accomplished in the digital signal domain. At least in part because of this, many high bandwidth serializer/deserializer transceivers utilize analog DFEs at the cost of higher power dissipation and semiconductor area. In some cases, such a cost is unacceptable. 
         [0006]    Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for signal equalization. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for equalizing signals. 
         [0008]    Various embodiments of the present invention provide decision feedback equalizer circuits that include a comparator, two adjustment calculation circuits, and a selector circuit. The comparator compares an input with a selected adjustment value corresponding to a first bit period, and provides a decision output based at least in part on the comparison of the input with the selected adjustment value. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit that is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. The selector circuit selects the first adjustment feedback as the selected adjustment value when the decision output is the first logic level, and selects the second adjustment feedback as the selected adjustment value when the decision output is the second logic level. 
         [0009]    In some instances of the aforementioned embodiments, the first adjustment calculation circuit and the second adjustment calculation circuit are driven by a storage device. The storage device stores a prior output of the comparator, and the first adjustment feedback value is calculated based at least in part on the prior output of the comparator. In some such instances, the first adjustment feedback value includes the prior output multiplied by an inter symbol interference value corresponding to a bit period of the prior output. In particular cases, the bit period precedes a bit period of the decision output. In some cases, the second adjustment feedback value is calculated by the second adjustment calculation circuit in substantially the same manner as the first adjustment calculation circuit, except that the decision output is speculated to be the second logic level. 
         [0010]    Other embodiments of the present invention provide analog to digital converters that include a comparator bank that receives a reference indicator and is operable to provide a decision output based at least in part on a comparison of an analog input with a reference threshold corresponding to the reference indicator. A range selection filter is included that has a first adjustment calculation circuit and a second adjustment calculation circuit. The first adjustment calculation circuit is operable to calculate a first adjustment feedback value based at least in part on a speculation that the decision output is a first logic level, and the second adjustment calculation circuit is operable to calculate a second adjustment feedback value based at least in part on a speculation that the decision output is a second logic level. A selector circuit selects the first adjustment feedback to generate the reference indicator when the decision output is the first logic level, and selects the second adjustment feedback to generate the reference indicator when the decision output is the second logic level. In some instances of the aforementioned embodiments, the comparator bank includes a single comparator, the reference indicator is a voltage offset, and the reference threshold is a reference voltage plus the voltage offset. 
         [0011]    Yet other embodiments of the present invention provide communication systems that include speculative digital decision feedback equalizers. As used herein, the phrase “communication system” is used in its broadest sense to mean and system whereby information is transferred from one element to another via a medium. In some cases, the speculative digital decision feedback equalizer is incorporated as a range filter in a dynamic analog to digital converter. Such communication systems may be, but are not limited to, storage systems and wireless communication systems. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of communication systems that may utilize decision feedback equalizers and/or dynamic analog to digital converters in accordance with different embodiments of the present invention. 
         [0012]    This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. 
           [0014]      FIG. 1  depicts an exemplary pulse applied to a channel, and a channel response including inter symbol interference to that pulse; 
           [0015]      FIG. 2   a  depicts a speculative digital DFE in accordance with various embodiments of the present invention; 
           [0016]      FIG. 2   b  is a timing diagram depicting an exemplary operation of the speculative digital DFE depicted in  FIG. 2   a;    
           [0017]      FIG. 3   a  depicts a speculative digital DFE incorporated into a dynamic range analog to digital converter in accordance with various embodiments of the present invention; 
           [0018]      FIG. 3   b  is a timing diagram depicting an exemplary operation of the speculative digital DFE depicted in  FIG. 3   a;    
           [0019]      FIG. 4   a  depicts a speculative digital DFE incorporated into a dynamic range analog to digital converter in accordance with other embodiments of the present invention; 
           [0020]      FIG. 4   b  is a timing diagram depicting an exemplary operation of the speculative digital DFE depicted in  FIG. 4   a ; and 
           [0021]      FIG. 5  depicts a data transfer system including a speculative digital DFE in accordance with one or more embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0022]    The present inventions are related to systems and methods for processing digital signals, and more particularly to systems and methods for equalizing signals. 
         [0023]    Turning to  FIG. 1 , an exemplary pulse  101  applied to a channel, and a channel response  102  thereto are depicted. C(i) indicates the magnitude of the impulse response (i.e., cursor); C(i−1) indicates the pre-cursor inter symbol interference at a bit period i−1; and C(i+1), C(i+2) and C(i+3) indicate post-cursor inter symbol interference at bit periods i+1, i+2 and i+3, respectively. From this, it is understood that an analog input signal representing a bit value during bit period i will interfere with the analog input signal during the previous bit period i−1, and during subsequent bit periods i+1, i+2 and i+3. Accordingly, the analog input signal during bit periods i−1, i+1, i+2 and i+3 bit periods will interfere with the analog input signal during bit period i. Thus, to compensate for inter symbol interference, inter symbol interference values corresponding to the aforementioned bit periods can be summed and subtracted from the analog input signal during bit period i. The sum of the relevant inter symbol interference values is referred to herein as an adjustment factor or adjustment feedback. In general, the adjustment factor can be found by multiplying the sampled bit value (logic ‘0’ or logic ‘1’) determined during relevant bit periods with the respective coefficient found from the impulse response. The adjusted analog input signal is then be sampled using a comparator. This process may be used to determine the correct logic value of a sample of an analog input signal in the presence of inter symbol interference. 
         [0024]    Turning to  FIG. 2   a , a speculative digital DFE circuit  200  is shown in accordance with various embodiments of the present invention. Speculative DFE circuit  200  is operable to reduce inter symbol interference such as that described above in  FIG. 1  without the timing constraints exhibited by existing DFE circuits. In particular, speculative digital DFE circuit  200  operates to pre-calculate two competing adjustment feedback values—one based on a speculation that the result from processing the succeeding bit (i.e., a decision output) will be logic ‘1’ and the other based on a speculation that the result from processing the succeeding bit will be logic ‘0’. Once the result from the succeeding bit is available, the pre-calculated adjustment feedback value corresponding to the correctly speculated output value can be immediately selected to process the following input bits. In this way, latency between determination of a succeeding bit and providing a data dependent input for processing a following bit can be greatly reduced as the time required to perform adjustment calculations is effectively eliminated from the latency. 
         [0025]    Speculative DFE circuit  200  receives an input  205  (i.e., input[m . . . 0]) at a digital comparator  210 . Digital comparator  210  also receives an adjustment input  225  (i.e., adjust[p . . . 0]) that was derived from previously received inputs  205 . Digital comparator  210  compares input  205  with adjustment input  225  and provides a single bit decision output  270  in accordance with the following pseudocode: 
         [0000]                                            If ((input[m..0] − adjust[p..0]) &lt;= 0)           {               Output Bit = 0           }           Else If ((input[m..0] − adjust[p..0]) &gt; 0)           {               Output Bit = 1           }                        
Output bit  270  is fed to a shift register including a number (j) of flip-flops  250   a ,  250   b ,  250   c . In particular, flip-flop  250   a  receives output bit  390  from a preceding bit period synchronized to a clock signal (not shown) and flip-flop  250   b  receives the output of flip-flop  250   a  synchronized to the same clock signal. The output of flip-flop  350   b  is provided to a succeeding flip-flop, and flip-flop  250   c  receives the output of a preceding flip-flop synchronized to the same clock signal. The outputs of flip-flops  250  are used to generate respective speculative feedback  242 ,  244 . In particular, an adjustment calculation circuit  240   a  performs an adjustment calculation based on a speculated logic ‘1’ input  260  and the outputs of flip-flops  250  to yield speculative feedback  242 ; and an adjustment calculation circuit  240   b  performs the same adjustment calculation based on a speculated logic ‘0’ input  262  and the outputs of flip-flops  250  to yield speculative feedback  244 .
 
         [0026]    Adjustment calculation circuit  240   a  may perform a standard DFE mathematical equation where the output of flip-flop  250   a  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+2, the output of flip-flop  250   b  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+3, and the output of flip-flop  250   c  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+x. The product of each of the aforementioned multiplications may then be summed together and added to an n-bit digital representation of the inter symbol interference value corresponding to bit time i+1. The result of the summation is provided as speculative feedback  242 . It should be noted that the multiplication and summation processes may be performed using pre-computed values retrieved from a lookup table, through use of dedicated multiplication and summation circuitry, or some combination thereof. By adding the inter symbol interference value corresponding to bit time i+1, speculative feedback  242  represents the calculated feedback where decision output  270  is found to be a logic ‘1’. 
         [0027]    Similarly, adjustment calculation circuit  240   b  may perform a standard DFE mathematical equation where the output of flip-flop  250   a  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+2, the output of flip-flop  250   b  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+3, and the output of flip-flop  250   c  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+x. The product of each of the aforementioned multiplications may then be summed together. The result of the summation is provided as speculative feedback  244 . Again, it should be noted that the multiplication and summation processes may be performed using pre-computed values retrieved from a lookup table, through use of dedicated multiplication and summation circuitry, or some combination thereof. By not adding the inter symbol interference value corresponding to bit time i+1, speculative feedback  244  represents the calculated feedback where decision output  270  is found to be a logic ‘0’ 
         [0028]    Once decision output  270  is available from digital comparator  210 , either speculative feedback  242  or speculative feedback  244  is selected to be stored in an input register  220 . In particular, if decision output  270  is found to be a logic ‘1’ speculative feedback  242  is selected by a multiplexer  230 . If decision output  270  is found to be a logic ‘0’ speculative feedback  244  is selected by a multiplexer  230 . An adjustment output  235  is provided as an input to register  220 . Input register  220  may be any register or memory element that is capable of synchronizing a received input to a desired timing of a corresponding output. Input register  220  is used to assure that adjustment output  235  is provided to digital comparator  210  only after the next clock edge indicating the next bit period, and assures that adjustment output  235  is not applied to comparator  210  in such a way that an asynchronous feedback loop exists. 
         [0029]    Turning to  FIG. 2   b , a timing diagram  201  depicts an exemplary operation of speculative digital DFE  200 . Following timing diagram  201 , processes are synchronized to a clock  241  with a clock period  221 . An input  205  is received (i.e., input (i)). Prior to receiving input  205 , an adjustment input  225  (i.e., adjustment input(i)) is registered and stable based on a previously determined decision output  270  (i.e., output (i−1)). Adjustment input  225  is selected to be one of speculative feedback  242  (i.e., speculative feedback (i)) or speculative feedback  244  (i.e., speculative feedback (i)) depending upon decision output  270 . Adjustment input  225  is registered based on clock  241 . A timing margin  231  provides a non-negative time period where both input (i) and adjustment input (i) are stable for comparison. The comparison results in output (i) which can then be used to select which of speculative feedback  242  or speculative feedback  244  is used on the succeeding rising edge of clock  241  to latch adjustment input  225  (i.e., adjustment input (i+1)). As input  205  (i.e., input (i)) is being compared with adjustment input  225  (i.e., adjustment input (i)), the succeeding speculative feedback values  242 ,  244  are being calculated. Using this approach to pre-calculating the adjustment values based on speculative decision making, the latency from when decision output  270  is available until adjustment input  225  is registered (i.e., until an adjustment value is ready for comparison with input  205 ) is greatly reduced. This allows for higher bandwidth operation of the DFE, and in some cases allows for using speculative DFE circuit  200  in place of an analog DFE. 
         [0030]    As more fully described in U.S. patent application Ser. No. 12/134,488 entitled “Systems and Methods for Analog to Digital Conversion” and filed on a date even herewith by Chmelar, a digital DFE may be combined with a dynamic analog to digital converter in such a way that the comparison function (e.g., digital comparator  210 ) of the DFE is eliminated. The entirety of the aforementioned reference is incorporated herein by reference for all purposes. Elimination of the comparison function allows the DFE to operate at even faster speeds as another layer of logic is eliminated from the critical timing path. 
         [0031]    Turning to  FIG. 3   a , a speculative digital DFE circuit is used as a range selection filter  301  and incorporated into a dynamic analog to digital converter  300  in accordance with various embodiments of the present invention. Dynamic analog to digital converter  300  includes range selection filter  301  (shown in dashed lines) that is implemented as a speculative digital DFE. Dynamic analog to digital converter  300  includes a number of comparators  331 ,  329 ,  327  that each receive a respective voltage reference  349 ,  351 ,  353  distributed across an input range of dynamic analog to digital comparator  300 . When enabled, comparators  331 ,  329 ,  327  each compare their respective voltage reference with an analog input  305 . A particular subset of comparators  331 ,  329 ,  327  is enabled during a given bit period by a respective one of bit enables  343 ,  345 ,  347 . Bit enables  343 ,  345 ,  347  are asserted for a period of a clock signal  341  by logically ANDing enable signals  367 ,  365 ,  363  provided from a 1-hot encoder circuit  361  with clock  341 . 1-hot encoder circuit  361  asserts only one of enables  367 ,  365 ,  363  during any bit period, and thereby selects only a single comparator of comparators  331 ,  329 ,  327 . By selectively asserting bit enables  343 ,  345 ,  347 , a particular input range for dynamic analog to digital converter  300  may be selected. The non-selected comparators remain in an idle state allowing for the conservation of power. In addition, bit enables  343 ,  345 ,  347  are provided to a multiplexer  395  that provides a decision output  370  to be driven by the selected comparator. It should be noted that while  FIG. 3   a  depicts three comparators and associated circuits and signals, that any number of comparators and associated circuits and signals are possible in accordance with different embodiments of the present invention. 
         [0032]    Range selection filter  301  includes a shift register formed of a number of flip-flops  350   a ,  350   b ,  350   c . In particular, flip-flop  350   a  receives decision output  370  from a preceding bit period synchronized to a clock signal (not shown) and flip-flop  350   b  receives the output of flip-flop  350   a  synchronized to the same clock signal. The output of flip-flop  350   b  is provided to a succeeding flip-flop, and flip-flop  350   c  receives the output of a preceding flip-flop synchronized to the same clock signal. The outputs of flip-flops  350  are used to generate respective speculative feedback  342 ,  344 . In particular, an adjustment calculation circuit  340   a  performs an adjustment calculation based on a speculated logic ‘1’ input  360  and the outputs of flip-flops  350  to yield speculative feedback  342 ; and an adjustment calculation circuit  340   b  performs the same adjustment calculation based on a speculated logic ‘0’ input  362  and the outputs of flip-flops  350  to yield speculative feedback  344 . 
         [0033]    Adjustment calculation circuit  340   a  may perform a standard DFE mathematical equation where the output of flip-flop  350   a  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+2, the output of flip-flop  350   b  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+3, and the output of flip-flop  350   c  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+x. The product of each of the aforementioned multiplications may then be summed together and added to an n-bit digital representation of the inter symbol interference value corresponding to bit time i+1. The result of the summation is provided as speculative feedback  342 . It should be noted that the multiplication and summation processes may be performed using pre-computed values retrieved from a lookup table, through use of dedicated multiplication and summation circuitry, or some combination thereof. By adding the inter symbol interference value corresponding to bit time i+1, speculative feedback  342  represents the calculated feedback where decision output  370  is found to be a logic ‘1’. 
         [0034]    Similarly, adjustment calculation circuit  340   b  may perform a standard DFE mathematical equation where the output of flip-flop  350   a  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+2, the output of flip-flop  350   b  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+3, and the output of flip-flop  350   c  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+x. The product of each of the aforementioned multiplications may then be summed together. The result of the summation is provided as speculative feedback  344 . Again, it should be noted that the multiplication and summation processes may be performed using pre-computed values retrieved from a lookup table, through use of dedicated multiplication and summation circuitry, or some combination thereof. By not adding the inter symbol interference value corresponding to bit time i+1, speculative feedback  344  represents the calculated feedback where decision output  370  is found to be a logic ‘0’. 
         [0035]    Once decision output  370  is available from multiplexer  395 , either speculative feedback  342  or speculative feedback  344  is selected as adjustment output  335  using a multiplexer  330 . In particular, if decision output  370  is found to be a logic ‘1’ speculative feedback  342  is selected by a multiplexer  330 . If decision output  370  is found to be a logic ‘0’ speculative feedback  344  is selected by a multiplexer  330 . Adjustment output  335  may be used directly by 1-hot encoder  361  to determine the range of dynamic analog to digital converter  300  that will be used during a subsequent bit period. Said another way, adjustment output  335  may be used directly to select which subset of comparators  331 ,  329 ,  327  are to be activated during a subsequent bit period. This circumvents the need for digital comparator  210  and reduces adjustment calculation circuits  340  to a set of digital multiplier circuits that multiply the outputs of flip-flops  350   a ,  350   b ,  350   c  by their respective inter symbol interference values, and a set of digital adder circuits. The output of the aforementioned digital adder circuits can be used as the respective speculative feedback outputs  342 ,  244 . It should be noted that in some cases, the aforementioned digital multiplier circuits and digital adder circuits may be eliminated through the use of well known methods of pre-computing the products and summation via a look-up table. This further enhances the speed of range selection filter  301 . 
         [0036]    Turning to  FIG. 3   b , a timing diagram  301  depicts an exemplary operation of dynamic analog to digital converter  300 . Following timing diagram  301 , processes are synchronized to a clock  341  with a clock period  321 . As shown, bit enables  343 ,  345 ,  347  for the succeeding comparison become stable shortly after a rising edge of clock  341 . Bit enables  343 ,  345 ,  347  are based on prior outputs  367 ,  365 ,  363  from 1-hot encoded  361 . Based on bit enables  343 ,  345 ,  347 , decision output  370  resolves some delay period later. In parallel with the resolution of decision output  370 , flip-flops  350  are clocked using the rising edge of clock  341  and allowing for speculative feedback  342  and speculative feedback  344  to be resolved. Once decision output  370  is resolved, one or the other of speculative output  342  or speculative output  344  is selected. The selected speculative output is then used to drive the appropriate adjustment input  335  to create encoder outputs  367 ,  365 ,  363 . 
         [0037]    It may be desirable to achieve even greater timing margin and thereby to increase the operational bandwidth of dynamic analog to digital converter  300  of  FIG. 3   a .  FIG. 4   a , depicts a dynamic analog to digital converter  400  that provides for additional timing margin when compared with dynamic analog to digital converter  300 . In particular, dynamic digital to analog converter  400  includes a speculative digital DFE circuit used as a range selection filter  410  (shown in dashed lines) in accordance with various embodiments of the present invention. Dynamic analog to digital converter  400  includes a number of comparators  431 ,  429 ,  427  that each receive a respective voltage reference  449 ,  451 ,  453  distributed across an input range of dynamic analog to digital comparator  400 . When enabled, comparators  431 ,  429 ,  427  each compare their respective voltage reference with an analog input  405 . A particular subset of comparators  431 ,  429 ,  427  is enabled during a given bit period by a respective one of bit enables  443 ,  445 ,  447 . Bit enables  443 ,  445 ,  447  are asserted for a period of a clock signal  441  by logically ANDing enable signals  467 ,  465 ,  463  provided from respective multiplexers  483 ,  485 ,  487 . Each of multiplexers  483 ,  485 ,  487  receives a respective one of speculative encoder outputs  491 ,  493 ,  495  and a corresponding respective one of speculative encoder outputs  492 ,  494 ,  496 . Multiplexers  483 ,  485 ,  487  select between the respective speculative encoder outputs based on a decision output  470  from a multiplexer  495 . 
         [0038]    A 1-hot encoder  499  asserts only one of speculative encoder outputs  491 ,  493 ,  495  based on a speculative feedback  442  and a speculation that decision output  470  is a logic ‘1’; and a 1-hot encoder  499  asserts only one of speculative encoder outputs  492 ,  494 ,  496  based on a speculative feedback  444  and a speculation that decision output  470  is a logic ‘0’. Thus, only one of speculative encoder outputs  491 ,  493 ,  495  and only one of speculative encoder outputs  492 ,  494 ,  496  are asserted during any bit period. One of the asserted speculative encoder outputs is selected by multiplexers  483 ,  485 ,  487  such that only a single comparator of comparators  431 ,  429 ,  427  is enabled for comparison on the subsequent bit period. By selectively asserting bit enables  443 ,  445 ,  447 , a particular input range for dynamic analog to digital converter  400  may be selected. The non-selected comparators remain in an idle state allowing for the conservation of power. In addition, bit enables  443 ,  445 ,  447  are provided to multiplexer  495  to generate decision output  470 . It should be noted that while  FIG. 4   a  depicts three comparators and associated circuits and signals, that any number of comparators and associated circuits and signals are possible in accordance with different embodiments of the present invention. 
         [0039]    Range selection filter  401  includes a shift register formed of a number of flip-flops  450   a ,  450   b ,  450   c . In particular, flip-flop  450   a  receives decision output  470  from a preceding bit period synchronized to a clock signal (not shown) and flip-flop  450   b  receives the output of flip-flop  450   a  synchronized to the same clock signal. The output of flip-flop  450   b  is provided to a succeeding flip-flop, and flip-flop  450   c  receives the output of a preceding flip-flop synchronized to the same clock signal. The outputs of flip-flops  450  are used to generate respective speculative feedback  442 ,  444 . In particular, an adjustment calculation circuit  440   a  performs an adjustment calculation based on a speculated logic ‘1’ input  460  and the outputs of flip-flops  450  to yield speculative feedback  442 ; and an adjustment calculation circuit  440   b  performs the same adjustment calculation based on a speculated logic ‘0’ input  462  and the outputs of flip-flops  450  to yield speculative feedback  444 . 
         [0040]    Adjustment calculation circuit  440   a  may perform a standard DFE mathematical equation where the output of flip-flop  450   a  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+2, the output of flip-flop  450   b  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+3, and the output of flip-flop  450   c  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+x. The product of each of the aforementioned multiplications may then be summed together and added to an n-bit digital representation of the inter symbol interference value corresponding to bit time i+1. The result of the summation is provided as speculative feedback  442 . It should be noted that the multiplication and summation processes may be performed using pre-computed values retrieved from a lookup table, through use of dedicated multiplication and summation circuitry, or some combination thereof. By adding the inter symbol interference value corresponding to bit time i+1, speculative feedback  442  represents the calculated feedback where decision output  470  is found to be a logic ‘1’. 
         [0041]    Similarly, adjustment calculation circuit  440   b  may perform a standard DFE mathematical equation where the output of flip-flop  450   a  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+2, the output of flip-flop  450   b  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+3, and the output of flip-flop  450   c  is multiplied by an n-bit digital representation of the inter symbol interference value corresponding to bit time i+x. The product of each of the aforementioned multiplications may then be summed together. The result of the summation is provided as speculative feedback  444 . Again, it should be noted that the multiplication and summation processes may be performed using pre-computed values retrieved from a lookup table, through use of dedicated multiplication and summation circuitry, or some combination thereof. By not adding the inter symbol interference value corresponding to bit time i+1, speculative feedback  444  represents the calculated feedback where output  370  is found to be a logic ‘0’. As discussed above, speculative feedback  442  is provided to 1-hot encoder  499  that asserts only one of speculative encoder outputs  491 ,  493 ,  495 . Similarly, speculative feedback  444  is provided to 1-hot encoder  498  that asserts only one of speculative encoder outputs  492 ,  494 ,  496 . By providing two 1-hot encoders  498 ,  499  and two adjustment calculation circuits  440 , the process of speculation may be continued closer to comparators  431 ,  429 ,  427  allowing a larger time for decision output  470  to stabilize. 
         [0042]    Once decision output  470  is available from multiplexer  495 , either one of speculative encoder outputs  491 ,  493 ,  495  (depending upon the assertion level of speculative feedback  442 ) or one of speculative encoder outputs  492 ,  494 ,  496  (depending upon the assertion level of speculative feedback  444 ) is selected using multiplexers  483 ,  485 ,  487 . In particular, if decision output  470  is found to be a logic ‘1’, one of speculative encoder outputs  491 ,  493 ,  495  is selected depending upon the assertion level of speculative feedback  442 . Alternatively, if decision output  470  is found to be a logic ‘0’, one of speculative encoder outputs  492 ,  494 ,  496  is selected depending upon the assertion level of speculative feedback  444 . Thus, the output of adjustment calculation circuits  440  in combination with the resolved value of decision output  470  determine the range of dynamic analog to digital converter  400  that will be used during a subsequent bit period. 
         [0043]    Turning to  FIG. 4   b , a timing diagram  401  depicts an exemplary operation of dynamic analog to digital converter  400 . Following timing diagram  401 , processes are synchronized to clock  441  with a clock period  421 . As shown, bit enables  443 ,  445 ,  447  for the succeeding comparison become stable shortly after a rising edge of clock  441 . Bit enables  443 ,  445 ,  447  control which comparator  431 ,  429 ,  427  will drive decision output  470  via multiplexer  495 . Bit enables  443 ,  445 ,  447  are based on the selection between speculative encoder outputs  491 ,  492 ,  493 ,  494 ,  495 ,  496  by application of decision output  470  to multiplexers  483 ,  485 ,  487 . Speculative encoder outputs  491 ,  492 ,  493 ,  494 ,  495 ,  496  are driven by 1-hot encoders  498 ,  499  and become stable shortly after the respective transitions of speculative feedback  442 ,  444 . Speculative feedback  442 ,  444  are updated after each rising edge of clock  441  causes decision output  470  to be stored in flip-flop  350   a.    
         [0044]    Turning to  FIG. 5 , a communication system  500  including a receiver  520  with a speculative digital DFE is shown in accordance with some embodiments of the present invention. Communication system  500  includes a transmitter  510  that transmits a signal representing a data set to receiver  520  via a transfer medium  530 . Transfer medium  530  may be, but is not limited to, a wireless transfer medium, a electrically wired transfer medium, a magnetic storage medium, or an optical transfer medium. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of transfer media that may be used in relation to different embodiments of the present invention. Receiver  520  includes a speculative digital DFE circuit similar to those described above in relation to  FIG. 2   a ,  FIG. 3   a  or  FIG. 4   a . In some cases, communication system  500  may be a cellular telephone system with transmitter  510  and receiver  520  being cell phones and/or cell towers. Alternatively, communication system  500  may be a magnetic storage medium with transmitter  510  being a write function, transfer medium  530  being a magnetic storage medium, and receiver  520  being a read function. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of other systems that may be represented as communication system  500  in accordance with different embodiments of the present invention. 
         [0045]    In conclusion, the invention provides novel systems, devices, methods and arrangements for equalizing signals. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. For example, while different embodiments of the present invention have been depicted with a particular number of bits of speculation, it will be understood that an arbitrary number of bits of speculation may be supported in accordance with different embodiments of the present invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.