Abstract:
An equalization circuit with switched capacitor filters, each having variable filter characteristics, that is adapted to provide power equalization on digital transmission lines that are subject to power losses for high frequency signals. The power equalization is provided automatically by switching in or out of a filter one or more of its capacitors in response to detected variations in line power levels. Identical filters are connected in parallel and alternatively applied within the equalizer circuit, the capacitor switching occurring only in a filter circuit that is not actively applied within the equalizer circuit.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a switched-capacitor filter (SCF) including switches, capacitors and an operational amplifier or amplifiers and, more particularly, to a variable switched-capacitor filter (VSCF) capable of changing the filter characteristic thereof. 
     A typical application of a VSCF is to an automatic line equalizer installed on a digital transmission path. There the power equalizer, commonly designated as a &#34;√f equalizer&#34; because transmission loss increases dramatically as the frequency increases, is designed to minimize intersymbol interference by the application of a variable switched-capacitor filter circuit or &#34;√f filter&#34;. Such a VSCF can readily be manufactured in a large-scale integrated circuit configuration so that the automatic line equalizer using the VSCF can be provided in desirably small dimensions. An example of such automatic line equalizers implemented by conventional VSCFs is disclosed in a paper entitled &#34;A CMOS Switched-Capacitor Variable Line Equalizer&#34;, by T. Suzuki et al in the IEEE Journal of Solid-State Circuit, Vol. SC-18, No. 6, December 1983, pages 700 to 706. The disclosed conventional VSCF, however, has disadvantages that substantial waveform distortions take place at the time of selective capacitor switching because the variable filter characteristic of the VSCF is discrete. The distortions result in an undesirable error rate in the transmitted data. In a two-wire communication system, for example, a transmitting mode and a receiving mode must be set up alternately with each other so that level detection is effected during the receiving mode operation and selective capacitor switching in each capacitor group is effected during the transmitting mode operation (in which a √f equalizer implemented by an SCF is not used). This frees the equalizer output from the influence of the waveform distortions attributable to the selective capacitor switching. In a four-wire communication system, however, the transmitting mode and the receiving mode occur simultaneously so that the SCF √f equalizer is always in operation. As a result, the equalizer output inevitably has the waveform distortions due to the selective capacitor switching. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is, therefore, to provide a variable SCF free from the above-mentioned disadvantages of the prior art VSCF. According to one aspect of the invention, there is provided a switched-capacitor filter which comprises: an input terminal; an output terminal; and first and second variable switched-capacitor filter means, each having a plurality of capacitors at least one of which is selected responsive to a control signal the filter characteristic of the filter being based on the selected capacitor or capacitors. The first and second filter means are connected to a single input terminal and are adapted to receive an input signal. First switching means is provided which, during a first state, delivers a first output signal from the first variable switched-capacitor filter means to the output terminal either directly or via a sample and hold circuit and, during a second state, prohibits the first output signal from reaching the output terminal. Second switching means is provided which, during the second state, delivers a second output signal from the second variable switched-capacitor filter means to the output terminal directly or via the sample and hold circuit and, during the first state, prohibits the second output signal from reaching the output terminal. The selection of at least one capacitor in the first variable switched-capacitor filter means is performed during the second state, while the selection of at least one capacitor in the second variable switched-capacitor filter means is performed during the first state. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects, features and advantages of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a first embodimeht of the present invention; 
     FIGS. 2A and 2B show waveforms of signals φ A  and φ B , respectively; 
     FIG. 3 is a circuit diagram of a VSCF block; 
     FIGS. 4A and 4B show waveforms of signals φ 1  and φ 2 , respectively; 
     FIG. 5 shows curves representative of a frequency-to-gain characteristic of the VSCF block; 
     FIG. 6A is a circuit diagram of a second embodiment of the present invention; 
     FIG. 6B is a circuit diagram of a signal generator; 
     FIG. 7 is a block diagram of a line equalizer to which the present invention is applied; 
     FIG. 8 is a circuit diagram of a prefilter; 
     FIG. 9 is a circuit diagram of a roll-off filter; 
     FIG. 10 is a circuit diagram of a peak detector or a data detector; 
     FIG. 11 is a block diagram of a control signal generator; and 
     FIG. 12 shows a timing chart demonstrating the operation of the line equalizer shown in FIG. 7. 
    
    
     In the drawings, the same structural elements are represented by the same reference numerals. 
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a first embodiment of the present invention comprises input terminals 101, 105, 106, 107 and 108, a signal output terminal 104, a first VSCF block 102, and a second VSCF block 103. The terminal 101 is connected to the blocks 102 and 103, the terminal 105 to the block 102, and the terminal 106 to the block 103. In each of the blocks 102 and 103, at least one of a plurality of capacitors is selected responsive to a control signal S 105  or S 106  applied thereto through the terminal 105 or 106, for setting up a specific filter characteristic. Meanwhile, an input signal is applied to both the blocks 102 and 103 via the terminal 101. The block 102 is connected to a switch section S A  which, during a first state, passes an output signal of the block 102 therethrough to the terminal 104 and, during a second state, does not pass it. On the other hand, the block 103 is connected to a switch section S B  which, during the second state, passes an output signal of the block 103 therethrough to the terminal 104 and, during the first state, does not pass it. In the embodiment, the sections S A   and S B  each may be constructed by simple switch elements. 
     Referring to FIG. 3, the block 102 is made up of an operational amplifier (op amp) 1, a capacitor 2, a first capacitor group 3, a second capacitor group 4, a third capacitor group 5, and switches S 1  and S 2 . The capacitor group 3 has the construction in which four capacitors 31, 32, 33 and 34, whose both ends are connected to switches S 11 , S 12 , S 13  and S 14 , respectively, are connected in parallel to one other. The other capacitor groups are constructed in the same manner as the capacitor group 3. Specifically, in the capacitor group 4, capacitors 41, 42, 43 and 44 are connected in parallel, while switches S 11 , S 12 , S 13  and S 14  are connected to opposite ends of the capacitors 41, 42, 43 and 44, respectively in the capacitor group 5, capacitors 51, 52, 53 and 54 are connected in parallel, while switches S 11 , S 12 , S 13  and S 14  are connected to opposite ends of the capacitors 51, 52, 53 and 54, respectively. The switches S 1  are opened and closed in response to a clock signal φ 1  shown in FIG. 4A, and the switches S 2  are opened and closed in response to a clock signal φ 2  shown in FIG. 4B. Each switch is closed when the associated clock signal φ 1  or φ 2  is a higher voltage and is opened when it is a lower voltage. The clock signals φ 1  and φ 2  have the same clock frequency and period t 1 , but their higher voltage periods do not overlap each other. The switches S 11  to S 14  are adapted to select their associated capacitors. Selection of any of the capacitors is effected by applying a selection signal having a higher voltage to the switches associated with the desired capacitor. The other block 103 has exactly the same construction as the block 102. 
     Assuming that the capacitor 2 has a capacitance C 2 , the capacitors 31 to 34 have capacitances C 31  to C 34 , respectively, the capacitors 41 to 44 have capacitances C 41  to C 44 , respectively, and the capacitors 51 to 54 have capacitances C 51  to C 54 , respectively, then the transfer function H(Z) (where Z equals e j ωT, ω represents an angular frequency, and T represents a sampling period) is expressed as: ##EQU1## 
     A specific example of the frequency-to-gain characteristic of the VSCF block is shown in FIG. 5. In FIG. 5, curves #1, #2, #3 and #4 represent characteristics which result from closing of the switches S 11  to S 14 , respectively. Labeled f N  (=1/T) in FIG. 5 is the Nyquist frequency. 
     Referring again to FIG. 1, the sections S A  and S B  are supplied with signals φ A  and φ B  shown in FIGS. 2A and 2B, respectively. When the signals φ A  and φ B  the higher voltage and the lower voltage, respectively, the above-mentioned first state occurs. Contrary to this, in the case where the signals φ A  and φ B  are the lower voltage and the higher voltage, respectively, the above-mentioned second state occurs. The signals φ A  and φ B  have the same clock period t 2  which is longer than the clock period t 1  of the signals φ 1  and φ 2 . The selection of the capacitor or capacitors in the block 102, i.e., the specific filter characteristics, is carried out during the second state. Likewise, the selection in the block 103 is carried out during the first state. It will therefore be seen that a transitional phenomenon due to switching of the capacitors inside the block 102 or 103 does not appear at the terminal 104. 
     Referring to FIG. 6A, a second embodiment comprises sections S A  and S B  and a sample and hold circuit 113. The rest of the construction shown in FIG. 6A is identical with the first embodiment. As shown, the section S A  comprises a capacitor 400, and switches S 111  and S 121 , while the section S B  comprises a capacitor 401, and switches S 112  and S 122 . Referring to FIG. 6B, a signal generator 115 is for generating signals to control the switches. The generator 115, to which the signals φ 1 , φ 2 , φ A  and φ B  shown in FIGS. 2 and 4 are applied, produces a signal φ 111  from an OR gate 200, a signal φ 112  from an OR gate 201, a signal φ 121  from an AND gate 300, and a signal φ 122  from an AND gate 301. Specifically, when the signal φ A  is the higher voltage and the signal φ B  is the lower one, there holds a condition wherein φ 111  =φ 1 , φ 121  =φ 2 , and φ 112  are the higher voltage and φ 122  is the lower voltage. When the signal φ A  is the lower voltage and the signal φ B  is the higher voltage, there holds a condition wherein φ 112  =φ 1 , φ 122  =φ 2 , and φ 111  are the high voltage and φ 121  is the lower voltage. The switches S 1 , S 2 , S 111 , S 112 , S 121 , and S 122  are opened and closed in response to the signals φ 1 , φ 2 , φ 111 , φ 112 , φ 121  and φ 122 , respectively. In this construction, when the signal φ A  is the higher voltage, the output of the block 102 is sampled in the circuit 113, while the output of the block 103 is simply stored in the capacitor 401. This relationship will be reversed when the signal φ B  is the higher voltage. 
     Referring to FIG. 7, an automatic line equalizer, to which the present invention is applied, is comprises a prefilter 109 for removing a fold over noise, automatic equalizer sections 702 and 703 (identical in construction with the blocks 102 and 103) each for equalizing a line loss, the switch sections S A  and S B , the sample and hold circuit 113, a rolloff filter 114 for reducing intersymbol interference of data by wave-shaping, a peak detector 111, a control signal generator 112, and a data detector 116. 
     Referring to FIG. 8, the prefilter 109 is made up of resistors 1091 and 1092 having resistance values R 1  and R 2 , respectively, capacitors 1093 and 1094 having capacitance values C 1093  and C 1094 , respectively, and an op amp 1095. The transfer function H(S) of the filter 109 (where S=jω) may be produced by: ##EQU2## 
     Referring next to FIG. 9, the filter 114 is composed of an ordinary second-order low-pass SCF. Assuming that capacitors 1141 to 1148 in FIG. 9 have capacitance values C 1141  to C 1148 , respectively, the transfer function H(Z) of the filter 114 may be expressed as: ##EQU3## 
     Referring to FIG. 10, each of the detector 116 and the detector 111 comprises a comparator 1111 for comparing an input signal applied to a terminal 1114 with a reference voltage applied to a terminal 1113, and a flip-flop 1112 for producing a predetermined signal in response to an output of the comparator 1111 in synchronism with a sampling clock, which is applied to a terminal 1115. 
     Referring to FIG. 11, the generator 112 includes an inverter 1121, an up-down counter 1122, and a decoder 1123. 
     The equalizer shown in FIG. 7 changes its characteristic as will be described with reference to FIG. 12 as well. The detector 116 determines that an output of the filter 114 is a logical &#34;1&#34; or a logical &#34;0&#34; (hereunder referred to simply as &#34;1&#34; and &#34;0&#34;, respectively.) Specifically, the comparator 1111 of the detector 116 compares an output V 114  of the filter 114 applied to the terminal 1114 with a threshold voltage V T  and, if V T  &lt;V 114 , produces &#34;1&#34; and, if V T  &gt;V 114 , produces &#34;0&#34;. The output of the comparator 1111 is sampled by the flip-flop 1112 at predetermined sampling timings. The sampling timings may be obtained from timing pulses provided by applying an output of the filter 114 to a tank circuit or like timing extractor means (not shown). The timing pulses have a period t 3  which is longer than the above-mentioned period t 1 . The output V 114  of the filter 114 is also routed to the detector 111 and compared thereby with a reference voltage V ref . The reference voltage V ref  is adapted to provide a reference level. The output of the detector 111 is applied to the generator 112. In the generator 112, the counter 1122 is decremented by one if the output of the detector 111 is &#34;1&#34; and incremented by one if it is &#34;0&#34;, in synchronism with the data detection output from the detector 116 coming in through a terminal 1125. Counts &#34;1&#34; through &#34;4&#34;, which are the contents of the counter 1122, correspond in one-to-one relation with the characteristic curves #1 through #4 of FIG. 5. The decoder 1123, decoding an output of the counter 1122, selects any of switches in the section 702 if the signal φ B  is high voltage and any of switches in the equalizer section 703 if the signal φ A  is the higher voltage. That is, the decoder 1123 delivers a signal for closing one of the switches S 11  through S 14  over one of signal lines 1124-1 through 1124-4. In this manner, automatic line equalization is accomplished without being affected by waveform distortions which result from switching of filter characteristic. 
     While this invention has thus for been described in conjunction with the preferred embodiment thereof, it will now readily be possible for those skilled in the art to put this invention into practice in various other manners.