Abstract:
A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate and determining an etch ratio. The least one device trench and at least one monitor trench are simultaneously formed in the first main surface of the semiconductor material layer. The at least one monitor trench is monitored to detect when it extends to a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 61/028,321, filed Feb. 13, 2008, entitled “Trench Depth Monitor for Semiconductor Manufacturing,” the entire contents of which are incorporated by reference herein. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    An embodiment of the present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device by monitoring trench depth during processing. 
         [0003]    Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated by reference herein. 
         [0004]    Trench-type superjunction devices are expected to replace multi-epi superjunction devices because of the potential lower processing cost.  FIG. 1A  illustrates an enlarged partial cross-sectional view of a wafer  10  having a first main surface  2  and a second main surface  4 . The wafer  10  includes a semiconductor substrate region  3  with an upper surface  6 . A semiconductor material layer  5  is disposed adjacent the upper surface  6  of the substrate region  3 . A layer of dielectric material or oxide  14  is disposed on the first main surface  2 . A trench  12  is formed in the semiconductor material layer  5  extending to a depth D from the first main surface  2  toward the substrate region  3 , exposing a portion of the upper surface  6 . 
         [0005]    In superjunction metal-oxide semiconductor field-effect-transistor (MOSFET) manufacturing, typically the trenches  12  are etched, sidewalls of the trenches  12  are doped to form columns of n or p type (not shown), and the trenches  12  are refilled. The depth of the trenches  12  is critical to performance and reliability of the end devices derived from the wafer  10 . The depth D preferably penetrates the semiconductor material layer  5  to expose the upper surface  6  of the substrate region  3 . For example,  FIG. 1B  illustrates a wafer  10  wherein a trench  12   s  has been formed in the semiconductor material layer  5 , but the depth D s  is too shallow and does not reach the upper surface  6  of the substrate region  3 . Conversely,  FIG. 1C  illustrates a wafer  10  wherein a trench  12   d  has been formed in the semiconductor material layer  5 , but the depth D d  is too deep and penetrates the upper surface  6 , extending partially into the substrate region  3 . In either of the examples of  FIGS. 1B and 1C , sidewall doping will be affected, thereby resulting in decreased performance and reliability. 
         [0006]    The depth of relatively larger trenches  12  may be measured using non-contact metrology. For example, the depth of a trench  12  having a width of  10  micrometers (μm) may be assessed using an optical profiler. However, as the trenches  12  become narrower, at a width of 4 μm for example, the depth can only be measured via destructive analysis techniques, such as the use of a scanning electron microscope (SEM). By destroying a portion of the wafer  10 , the yield is thereby decreased. 
         [0007]    In addition to superjunction devices, the development of microelectromechanical systems (MEMS) technology has provided the ability to combine microelectronic circuits and mechanical parts, such as cantilevers, membranes, holes, and the like, onto a single chip. MEMS chips may be developed to provide, for example, inertia sensors (e.g., for use in an accelerometer), radio frequency (RF) switches, and pressure sensors, and may also be used in optics applications, such as for digital light processing (DLP) televisions. The depth of trenches formed on MEMS chips is therefore also critical for proper functionality. 
         [0008]    It is desirable to provide a method of manufacturing trench-type superjunction devices and MEMS whereby the trench depth may be accurately monitored without unnecessary destructive measurement analysis, thereby increasing wafer yield. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    Briefly stated, embodiments of the present invention comprise a method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position. The method includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate. An etch ratio is determined. The at least one device trench and at least one monitor trench are simultaneously formed from the first main surface of the semiconductor material layer. The method further includes detecting whether the at least one monitor trench extends to a second depth position. A ratio of the first depth position to the second depth position is generally proportional to the etch ratio. Preferably, a ratio of the first depth position to the second depth position is generally equal to the etch ratio. 
         [0010]    Another embodiment of the present invention comprises a method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position. The method includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate. An etch ratio is determined. The at least one device trench and at least one monitor trench are simultaneously formed from the first main surface of the semiconductor material layer. A depth of the at least one monitor trench is monitored. Formation of the at least one device trench and the at least one monitor trench ceases upon attainment by the at least one monitor trench of a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio. 
         [0011]    A still further embodiment of the present invention comprises a semiconductor wafer including a semiconductor substrate having first and second main surfaces opposite to each other. A semiconductor material layer having first and second main surfaces opposite to each other is disposed on the first main surface of the semiconductor substrate. At least one device trench extends from the first main surface of the semiconductor layer to a first depth position. At least one monitor trench extends from the first main surface of the semiconductor layer to a second depth position. A ratio of the first depth position to the second depth position is predetermined such that a depth of the at least one device trench is determined by measuring a depth of the at least one monitor trench. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The foregoing summary, as well as the following detailed description of preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustration, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown. 
           [0013]    In the drawings: 
           [0014]      FIG. 1A  is an enlarged partial cross-sectional elevational view of a prior art semiconductor wafer following formation of a trench therein; 
           [0015]      FIG. 1B  is an enlarged partial cross-sectional elevational view of a prior art semiconductor wafer having a trench formed therein that is shallower than desired; 
           [0016]      FIG. 1C  is an enlarged partial cross-sectional elevational view of a prior art semiconductor wafer having a trench formed therein that is deeper than desired; 
           [0017]      FIG. 2  is an enlarged partial cross-sectional elevational view of a prior art semiconductor wafer during a reactive ion etching process showing different sized trenches; 
           [0018]      FIG. 3  is a top plan view of a pattern for use on a test wafer for determining an etch ratio; 
           [0019]      FIG. 4  is an enlarged partial cross-sectional elevational view of a test wafer in accordance with a preferred embodiment of the present invention; 
           [0020]      FIG. 5A  is a top plan view of a wafer having a die layout in accordance with a preferred embodiment of the present invention; 
           [0021]      FIG. 5B  is an enlarged top plan view of a die from the wafer of  FIG. 5A  in accordance with a preferred embodiment of the present invention; and 
           [0022]      FIG. 5C  is an enlarged top plan view of a process control module (PCM) from the wafer of  FIG. 5A  in accordance with a preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    Certain terminology is used in the following description for convenience only and is not limiting. The words “right”, “left”, “lower”, and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the device and designated parts thereof. The terminology includes the above-listed words, derivatives thereof, and words of similar import. Additionally, the words “a” and “an”, as used in the claims and in the corresponding portions of the specification, mean “at least one.” 
         [0024]    As used herein, reference to conductivity will be limited to the embodiment described. However, those skilled in the art know that p-type conductivity can be switched with n-type conductivity and the device would still be functionally correct (i.e., a first or a second conductivity type). Therefore, where used herein, reference to n or p can also mean either n or p or p and n can be substituted therefor. 
         [0025]    Furthermore, n +  and p +  refer to heavily doped n and p regions, respectively; n ++  and p ++  refer to very heavily doped n and p regions, respectively; n −  and p −  refer to lightly doped n and p regions, respectively; and n −  and p −  refer to very lightly doped n and p regions, respectively. However, such relative doping terms should not be construed as limiting. 
         [0026]    Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout, there is shown in  FIG. 5A  a top plan view of a wafer  510  manufactured in accordance with preferred embodiments of the present invention. A cross-section of the wafer  510  exhibits the same layer structure as shown in  FIG. 1A , including first and second main surfaces  2 ,  4 , a semiconductor substrate  3  with upper surface  6 , a semiconductor material layer  5  deposited on the upper surface  6 , and an oxide layer  14 . At least one device trench  512  ( FIG. 5B ) and at least one monitor trench  530  ( FIG. 5C ) are formed in the semiconductor material layer  5  extending from the first main surface  2 . Both the device trench  512  and the monitor trench  530  are preferably formed using reactive ion etching (RIE), and more preferably, using deep RIE techniques.  FIGS. 5A-5C  will be described in more detail below. 
         [0027]      FIG. 2  illustrates a typical RIE process. RIE utilizes an ionized gas, or plasma, to remove material  215  from the wafer  210 . High energy ions  222  of plasma bombard the wafer  210  and react with the material  215 . A layer of photoresistive material  220 , which protects portions of the wafer  210  during the RIE process, is deposited over the material  215  to form the pattern to be etched onto the wafer  210 . Typically, the wafer  210  is placed in a chamber with an apparatus for generating a strong radio frequency (RF) electromagnetic field. A gas is passed into the chamber at a low pressure and is then ionized by the RF field. An inductively coupled plasma (ICP) is preferably used for the deep RIE process described herein. The ICP is generated using an RF powered magnetic field. The gas selection and amount varies depending on the material  215  to be etched. For example, sulfur hexafluoride SF 6  may be used to etch silicon. Etch by-product  223  may also be generated. 
         [0028]    An etch rate during deep RIE is generally affected by several variables. Etch chemistry and process conditions have a large impact on the etch rate. The reaction between the material  215  and the ions  222  of the ICP determines how quickly a trench  212  may be formed and, therefore, selection of the appropriate gas and material  215  is essential. Similarly, the power supplied to the RF field, the pressure in the chamber, the gas flow, or like processes impact the speed of the etchant. The pattern density on the wafer  210  and the feature aspect ratio also affect the etch rate. A higher density of features, such as the trenches  212 ,  230  results in a smaller etch rate. The feature aspect ratio is a ratio of the length of the feature to the width of the feature. Trenches  212  with lower aspect ratios etch faster than trenches  230  with higher aspect ratios. 
         [0029]    Finally, the etch rate is affected by the feature size, or in the example of  FIG. 2 , the widths W 1 , W 2  of the respective trenches  212 ,  230 . As a general rule, smaller trenches  212  etch at a slower rate than larger trenches  230  because more etchant can access the larger trench  230 . This phenomenon is referred to as RIE lag. For example, the trench  230  reaches a depth of D 2  in the same amount of time it takes the trench  212  to reach a depth of D 1 . Using the principle of RIE lag, a larger trench  230  (i.e., having a width W 2  greater than W 1 ) can be used to calibrate a smaller trench  212  if an etch ratio can be determined. The etch ratio is generally determined by a ratio of the width D 1  of the smaller trench  212  to the width D 2  of the larger trench  230 . 
         [0030]    Referring to  FIG. 3 , an exemplary pattern  350  is illustrated for use on a test wafer ( FIG. 4 ) prior to batch production. The pattern  350  includes three trench sets  351 ,  352 ,  353  for calculating an etch ratio. The first trench set  351  includes two trenches of 3 μm width spaced at 40 and 80 μm. The second trench set  352  includes five individual trenches of 4, 5, 6, 8, and 10 μm spaced at 20 μm each. The third trench set  353  includes groups of trenches of 1.0, 1.5, 2.0, 2.5, and 3.0 μm, each group having variable spacing at 20, 10, 5, 3, 5, and 20 μm. One skilled in the art will recognize that any number of trenches or other features of various widths and orientations may be implemented in the pattern  350  for etch ratio determination. 
         [0031]    Referring to  FIG. 4 , trenches are etched into the test wafer  410   t  according to the pattern  350  and the depths of the various trenches on the test wafer  410   t  are then determined by excising a cross-sectional portion of the test wafer  410   t  for SEM analysis.  FIG. 4  shows two trenches  412   t,    430   t  having widths of 4 μm and 10 μm respectively, which are chosen, for purposes of example, to correspond to the widths of the trenches  512 ,  530  in the device wafer  510 . The width for use in a monitor trench  530  is preferably selected such that non-destructive analysis, such as by an optical profiler, may be used to measure depth. A width for use in a device trench  512  may also be determined by the test wafer. The respective depths on the test wafer  410   t  are compared to determine the etch ratio. 
         [0032]    For example, in  FIG. 4 , the 10 μm trench  430   t  extends from the first main surface  402   t  of the semiconductor material layer  405   t  to a depth of X (μm). The 4 μm trench  412   t  is similarly formed on the test wafer  410   t.  The depth of the 4 μm trench  412   t  is measured as 0.8×. The depth measurements of the trenches  412   t,    430   t  on the test wafer  410   t  may be made by SEM analysis. The etch ratio is thus determined to be 0.8 and may be applied to similarly formed trenches  512 ,  530  on the device wafer  510 . Thus, if the desired depth of the device trench  512  is D, then the monitor trench  530  depth is generally equal to D/0.8. As described earlier with respect to  FIG. 1A , it is preferable that the device trench  512  extend from the first main surface  2  of the wafer  510  to the upper surface  6  of the semiconductor substrate  3 . 
         [0033]    The wafer  510  shown in  FIGS. 5A-5C  as being manufactured in accordance with a preferred embodiment of the present invention preferably includes a plurality of dies  560 . Each die  560  may be intended for use in a superjunction device, (e.g., a superjunction field-effect-transistor (FET)), MEMS, or other semiconductor device. A number of devices may also be included in each die area  560 . The dies  560  therefore include the device trenches  512 . In addition, one or more process control modules (PCMs)  561  are distributed on the wafer  510 . A PCM  561  is an area set aside on the wafer  510  for testing and detecting flaws that may affect nearby dies  560 . One or more monitor trenches  530  are located in each PCM  561  to avoid wasting usable space of the die  560 . In an alternative arrangement, the PCM  561  may be located in a dicing path (the space between dies  560  for allowing each die to be cut away individually). The monitor trench  530  may also be placed in the dicing path PCM  561 . 
         [0034]    During processing of the wafer  510 , the monitor trench  530  may be utilized in a number of ways to ensure proper depth of the device trench  512 . In one preferred embodiment, the trenches  512 ,  530  are simultaneously etched. Once etching is complete, the monitor trench  530  is assessed by way of, for example, an optical profiler, as described above. If the depth of the monitor trench  530  indicates, based on the predetermined etch ratio, that the device trench  512  is at the proper depth, processing continues. If the depth of the monitor trench  530  indicates, based on the predetermined etch ratio, that the device trench  512  is at a depth less than the desired depth, the wafer  510  is replaced for further etching. 
         [0035]    Alternatively, the monitor trench  530  may be continuously measured during the etching process such that etching ceases upon attainment of a depth by the monitor trench  530  that indicates, based on the etch ratio, that the device trench  512  is at the proper depth. Endpoint detection of the monitor trench  530  may be carried out, for example, using one or more laser sources located in the chamber. Laser light reflected off the bottom of the trench  530  and the first main surface  2  are compared to determine the relative trench  530  depth via, for example, interferometry, polarimetry, or the like. Other techniques for determining the trench monitor  530  depth, either by continuous or discrete measurements, may be used without departing from embodiments of the present invention. 
         [0036]    The trench  512 ,  530  designs are not limited to rectangles. Many other trench shapes such as ovals, circles, polygons, non-geometric shapes, dog-bones, rectangles with rounded ends, or crosses are also possible. The trench shapes and orientations may be changed so as to fit a process specifically designed for superjunction devices, MEMS, or other semiconductor devices. However, the number and locations of the trenches  512  may affect overall device efficiency. Additionally, the width of the monitor trench  530  may be increased or decreased depending on the equipment available for accurate depth measurement by non-destructive methods. 
         [0037]    The monitor trench  530  may also be used to conveniently determine a depth of other trenches  512  that are identically sized to the monitor trench  530  or have larger widths and/or depths than the monitor trench  530 . For example, a very wide trench  512  may be etched on the wafer  510 . Rather than reposition the wafer  510  or measuring instrument (not shown) for determining the depth of the very wide trench  512 , the depth of the monitor trench  530  may be measured, provided the etch ratio of the two trenches  512 ,  530  is known. Consequently, a wafer  510  may include a number of trenches  512  with greatly varying widths and/or depths, and the monitor trench  530  may be used to determine the depth of each trench  512 , provided that the etch ratio for each trench  512  is known. 
         [0038]    It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that the invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.