Abstract:
A charge monitoring device is described for monitoring charging effect during semiconductor manufacturing. In a first aspect of the invention, a charge storage MOS memory structure comprises a substrate body, an oxide-nitride-oxide structure that overlays a top surface of the substrate and extends above the edges between a source region and a drain region, and a polygate formed over the oxide-nitride-oxide structure. When a charging source, such as UV light or plasma, is projected onto the charge storage device, the polygate of the charge storage device protects the nitride layer from charging effect The light source charges side walls of the oxide-nitride-oxide structure.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to electrically programmable and erasable memory and more particularly to charge storage devices for monitoring charging effect. 
         [0003]    2. Description of Related Art 
         [0004]    Electrically programmable and erasable nonvolatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modem applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a nonvolatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier. 
         [0005]    A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by N-bit memory. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer. 
         [0006]    N-bit devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about  5  to  9  nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an N-bit flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious as the technology continues scaling down. 
         [0007]    A traditional floating gate device stores 1 bit of charge in a conductive floating gate. N-bit devices has a plurality of cells where each N-bit cell provides two bits of flash cells that store charge in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of an N-bit memory cell, a nitride layer is used as a trapping material positioned between a top oxide layer and a bottom oxide layer. The ONO layer structure effectively replaces the gate dielectric in floating gate devices. The charge in the ONO dielectric with a nitrite layer may be either trapped on the left side or the right side of an N-bit cell. 
         [0008]    It is desirable to design simpler charge storage structures for monitoring charging effect in charge trapping memories as well as providing direction effect for the charge storage structures. 
       SUMMARY OF THE INVENTION 
       [0009]    The present invention describes a charge monitoring device for monitoring charging effect during semiconductor manufacturing. In a first aspect of the invention, a charge storage MOS (CS-MOS) memory structure comprises a substrate body, an oxide-nitride-oxide structure that overlays a top surface of the substrate and extending above the edges between a source region and a drain region, and a polygate formed over the oxide-nitride-oxide structure. When a charging source, such as UV light or plasma, is projected onto the charge storage device, the polygate of the charge storage device protects the nitride layer from charging effect. The light source charges side walls of the oxide-nitride-oxide structure. In a corresponding layout structure, a source/drain strip extends substantially in a first direction, while a polygate strip extends substantially in a second direction that is approximately orthogonal with the source/drain strip in the first direction. The polygate strip having a length Lg measured from the width of the polygate strip, and a width Wg measured from the width of the source/drain strip. 
         [0010]    In a second aspect of the invention, a charge storage virtual ground (CS-VG) memory structure comprises a substrate body, an oxide-nitride-oxide structure that overlays a top surface of the substrate body, and a polygate formed over the oxide-nitride-oxide structure. When a light source is projected onto the charge storage device, a top surface of the polygate blocks light from penetrating the polygate. The light source charges side walls of the oxide-nitride-oxide structure. In a corresponding layout structure, a source strip extends substantially in a first direction, a drain strip extends substantially in the first direction, while a polygate strip extends substantially in a second direction that is approximately orthogonal with the source and drain strips in the first direction. The polygate strip has a length Lg measured from a gap between the source strip and the drain strip, and a width Wg measured from the width of the polygate strip. 
         [0011]    Broadly stated, a charging monitor device comprises a substrate body having a channel separating a first region and a second region; a charging trapping structure overlying a top surface of the channel in the substrate body, the charging trapping structure having sides; and a polygate overlying a top surface of the charge trapping structure, the polygate having a top surface and sides that align with the sides of the charge trapping structure; wherein a charging source projects charges onto the top surface of the polygate, the sides of the polygate and the sides of the charge trapping structure, the top surface of the polygate substantially blocks the charges from penetrating the top surface of the polygate, and the charging source provides charges to the sides of the charge trapping structure. 
         [0012]    Advantageously, the present invention provides simpler charge storage device structures for monitoring charging effect. The present invention also advantageously provides different device structures for controlling the sensibility of the charging effect. 
         [0013]    The structures and methods of the present invention are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims. These and other embodiments, features, aspects, and advantages of the invention will become better understood when read in conjunction with the following description, appended claims and accompanying drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The invention will be described with respect to specific embodiments thereof, and reference will be made to the drawings, in which: 
           [0015]      FIG. 1A  is a process diagram illustrating a cross-sectional view of a charge storage MOS memory structure in accordance with the present invention. 
           [0016]      FIG. 1B  is a layout diagram illustrating a top view of the charge storage MOS memory structure in accordance with the present invention. 
           [0017]      FIG. 2A  is a process diagram illustrating a cross-sectional view of a charge storage virtual ground memory structure in accordance with the present invention. 
           [0018]      FIG. 2B  is a layout diagram illustrating a top view of a charge storage virtual ground memory structure in accordance with the present invention. 
           [0019]      FIG. 3A  is a process diagram illustrating a cross-sectional view of the charge storage MOS memory structure showing charging locations and a device current path in accordance with the present invention. 
           [0020]      FIG. 3B  is a process diagram illustrating a top view of the charge storage MOS memory structure showing charging locations and a device current path in accordance with the present invention. 
           [0021]      FIG. 4  is a graphical diagram illustrating an experimental result of an IV curve of the charge storage MOS memory structure in accordance with the present invention. 
           [0022]      FIG. 5A  is a process diagram illustrating a cross-sectional view of the charge storage virtual ground memory structure showing charging locations and a device current path in accordance with the present invention. 
           [0023]      FIG. 5B  is a process diagram illustrating a top view of the charge storage virtual ground memory structure showing charging locations and a device current path in accordance with the present invention. 
           [0024]      FIG. 6  is a graphical diagram illustrating an experimental result of the charge storage virtual ground memory structure in accordance with the present invention. 
           [0025]      FIGS. 7A-7D  are layout diagrams illustrating various directions for monitoring charging effect in the charge storage MOS memory structure in accordance with the present invention. 
           [0026]      FIGS. 8A-8D  are layout diagrams illustrating various directions for monitoring charging effect in the charge storage virtual ground memory structure in accordance with the present invention. 
           [0027]      FIG. 9  is a block diagram illustrating a silicon wafer with placement of various charge monitor structures in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    A description of structural embodiments and methods of the present invention is provided with reference to  FIGS. 1-9 . It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments, but that the invention may be practiced using other features, elements, methods and embodiments. Like elements in various embodiments are commonly referred to with like reference numerals. 
         [0029]      FIG. 1A  is a process diagram illustrating a cross-sectional view of a CS-MOS memory structure  100 . The CS-MOS memory structure  100  comprises a p-substrate  110  with n+ doped regions  120  and  122 , and a p-doped region between the n+ doped regions  120  and  122 . A channel width X  112  of the p-substrate  1   10  is positioned between the n+ doped region  120  on the left end and the n+ doped region  122  on the right end. A bottom dielectric structure  130  (bottom oxide) overlays a top surface of the channel width X  112  of the substrate  110 ; a charge trapping structure  132  (e.g. silicon nitride layer) overlays the bottom dielectric structure  130 ; a top dielectric structure (top oxide)  134  overlays the charge trapping structure  132 ; and an n+ polygate  140  overlays the top dielectric structure  134 . The combination of the bottom dielectric structure  130 , the charge trapping structure  132 , and the top dielectric structure  134  is commonly referred as an ONO (oxide-nitride-oxide) structure. The width of the ONO structure aligns with the channel width X  112  of the p-substrate  110 . Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials including for example Al 2 O 3 . Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al 2 O 3 , HfO 2 , CeO 2 , and others. The charge trapping structure may be a discontinuous set of pockets or particles of charge trapping material, or a continuous layer as shown in the drawing. 
         [0030]    Bias voltages can be applied to the CS-MOS memory structure  100  to measure electrical characteristics. A collection of different measured data, including I-V curve, Vt shift, and Gm variation, can be used to check the charging effect. For example, a drain voltage  150  VD is applied with 1.6V to the n+ doped region  122  and a source voltage VS  152  is applied with 0 volts to the n+ doped region  120 , and the sweeping of a gate voltage Vg  154  from 0 volts to 6 volts for checking the flow of an electrical current. Alternatively, the gate voltage Vg  154  remains at a constant value at 6 volts. A substrate voltage Vsub  156  is connected to the p-substrate  10 . A higher charged MOS memory structure  100  causes smaller current as well as high Vt level. 
         [0031]    The memory cell for N-bit -like cells has, for example, a bottom oxide with a thickness ranging from 3 nanometers to 10 nanometers, a charge trapping layer with a thickness ranging from 3 nanometers to 9 nanometers, and a top oxide with a thickness ranging from 5 nanometers to 10 nanometers. The memory cell for SONOS-like cells has, for example, a bottom oxide with a thickness ranging from 1 nanometer to 3 nanometers, a charge trapping layer with a thickness ranging from 3 nanometers to 9 nanometers, and a top oxide with a thickness ranging from 3 nanometers to 10 nanometers. 
         [0032]    As generally used herein, programming refers to raising the threshold voltage of a memory cell and erasing refers to lowering the threshold voltage of a memory cell. However, the invention encompasses both products and methods where programming refers to raising the threshold voltage of a memory cell and erasing refers to lowering the threshold voltage of a memory cell, and products and methods where programming refers to lowering the threshold voltage of a memory cell and erase refers to raising the threshold voltage of a memory cell. 
         [0033]      FIG. 1B  is a layout diagram  160  illustrating a top view of the CS-MOS memory structure  100  with layers of a p-substrate  110 , the n+ doped region  120  operating as a source, the n+ doped region  122  operating as a drain and the polygate  140 . The memory structure has a channel length denoted by the symbol Lg  170  and a channel width denoted by the symbol Wg  180 . The channel length Lg  170  is defined by the length in the horizontal direction of the polygate  140 , as indicated by the double-ended arrow  172 . The channel width Wg  180  is defined by the length in the horizontal direction of the source  120  and the drain  122 , as indicated by the double-ended arrow  182 . 
         [0034]      FIG. 2A  is a process diagram illustrating a cross-sectional view of a CS-VG memory structure  200 . The charge storage virtual ground memory structure  200  comprises a p-substrate  210  with n+ doped regions  220  and  222 , and a p-doped region between the n+ doped regions  220  and  222 . A channel width Y  212  of the p-substrate  210  is positioned between the n+ doped region  220  on the left end and the n+ doped region  222  on the right end. A bottom dielectric structure  230  overlays across top surfaces of the n+ doped region  220 , the channel width Y  212 , and the n+ doped region  220 . A charge trapping structure  232  overlays the bottom dielectric structure  230 , and a top dielectric structure  234  overlays the charge trapping structure  232 , and a polygate  240  overlays the top dielectric structure  234 . The combination of the bottom dielectric structure  230 , the charge trapping structure  232 , and the top dielectric structure  234  is commonly referred as an ONO structure. The width of the ONO structure aligns with the entire width measured by the n+ doped region  220 , the channel width Y  212 , and the n+ doped region  220 . 
         [0035]      FIG. 2B  is a layout diagram  250  illustrating a top view of CS-VG memory structure  200  with layers of the p-substrate  210 , the source strip  220 , the drain strip  222  and the polygate  240 . The memory structure has a channel length denoted by the symbol Lg  270  and a channel width denoted by the symbol Wg  280 . The channel length Lg  270  is defined by a gap between the source strip  220  and the drain strip  222 , as indicated by the double-ended arrow  272 . The channel width Wg  280  is defined by the length in the vertical direction of the polygate  240 , as indicated by the double-ended arrow  282 . 
         [0036]      FIG. 3A  is a process diagram illustrating a cross-sectional view of the CS-MOS memory structure  100  showing charging locations and a device current path. A charging source such as a UV light emits lights in different directions including projecting light  310   a  from the top, projecting light  310   b  from the left side, and projecting light  310   c  from the right side. The polygate  140  blocks entirely or substantially the projected light  310   a  from entering the polygate  140  and the charge trapping structure  132 . The light  310   b  from the left side charges a left sidewall  320  of the charge trapping structure  132 . The light  310   c  from the right side charges a right sidewall  322  of the charge trapping structure  132 . 
         [0037]      FIG. 3B  is a process diagram illustrating a top view of the CS-MOS memory structure  100  showing charging locations and a device current path. Because the polygate  140  blocks charges from the projected light  310   a  from entering the polygate  140 , a plurality of charges  350  gather along the left sidewall  320  and a plurality of charges  352  gather along the right sidewall  322  of the charge trapping structure  132 . A device current path  360  flows bidirectionally between the source  120  and the drain  122 . 
         [0038]      FIG. 4  is a graphical diagram  400  illustrating an experimental result of an IV (Id-Vg) curve of the CS-MOS memory structure  100 . The graphical diagram  400  shows a first curve  410  before the application of UV light, a second curve  420  with the application of UV 1  light, a third curve  430  with the application of UV 2  light, and a fourth curve  440  with the application of UV 3  light. A threshold voltage Vt  450  is used to monitor the charge behavior of the CS-MOS memory structure  100 . The voltage level of the Vt shift  450  increases with the increase in the amount of charge time of UV light so that the effect of UV charging effect can be monitored. 
         [0039]      FIG. 5A  is a process diagram illustrating a cross-sectional view of the CS-VG memory structure  200  showing charging locations and a device current path. A charging source  510  such as a UV light emits light in the direction of a polygate  240 . The polygate  240  blocks entirely or substantially the projected light  510  from entering the polygate  240  and the charge trapping structure  232 . However, the light projected by the charging source  510  charges side walls of a gate region of the polygate  240 , as indicated by charges  520  in the charge trapping structure  232 . 
         [0040]      FIG. 5B  is a layout diagram illustrating a top view of the CS-VG memory structure showing charging locations and a device current path. Although the polygate  240  blocks charges from the projected light  510  from entering the polygate  240 , the charging source  510  also projects light near the side walls  522  and  524  of the gate region as to inject a plurality of charges  520  into the charge trapping structure  232 . A device current path  530  flows bidirectionally along the length of the polygate  240 . While the charges gather vertically along sides of the polygate  140  in the layout diagram of  FIG. 3B , the charges gather horizontally along sides of the polygate  240  in the layout diagram of  FIG. 5B . 
         [0041]      FIG. 6  is a graphical diagram  600  illustrating an experimental result of an IV (Id-Vg) curve of the CS-VG memory structure  200 . The graphical diagram  600  shows a first curve  610  before the application of UV light, a second curve  620  with the application of UV 1  light, a third curve  630  with the application of UV 2  light, and a fourth curve  640  with the application of UV 3  light. A threshold voltage Vt  650  is used to monitor the charge behavior of a memory cell. The voltage shift level of the Vt  650  increases with the increase in the amount of charge time of UV light so that the effect of UV charging effect can be monitored. 
         [0042]      FIGS. 7A-7D  are layout diagrams  710 ,  720 ,  730 ,  740 , illustrating various directions for monitoring charging effect in a CS-MOS memory structure. Each layout in the layout diagrams  710 ,  720 ,  730 ,  740  shows a different direction flow of the CS-MOS memory structure  100  for use with monitoring a different charging behavior. In the layout diagram  710 , the polygate  140  is placed in the north direction  712  with a direction effect in a north direction and an electrical current flow toward the west direction  714 . In the layout diagram  720 , the polygate  140  is placed in the west direction  722  with a direction effect in a west direction and an electrical current flow toward the south direction  724 . In the layout diagram  730 , the polygate  140  is placed in the south direction  732  with a direction effect in a south direction and an electrical current flow toward the east direction  734 . In the layout diagram  740 , the polygate  140  is placed in the north direction  742  with a direction effect in an east direction and an electrical current flow toward the west direction  744 . 
         [0043]      FIGS. 8A-8D  are layout diagrams illustrating various directions for monitoring charging effect in the CS-VG memory structure  200 . Each layout in the layout diagrams  810 ,  820 ,  830 ,  840  shows a different direction flow of a CS-MOS memory structure for use with monitoring a different charging behavior. In the layout diagram  810 , the polygate  240  is placed in the west direction  812  with a direction effect in an cast direction and an electrical current flow toward the west direction  814 . In the layout diagram  820 , the polygate  240  is placed in the south direction  822  with a direction effect in a south direction and an electrical current flow toward the south direction  824 . In the layout diagram  830 , the polygate  240  is placed in the east direction  832  with a direction effect on an east direction and an electrical current flow toward the east direction  834 . In the layout diagram  840 , the polygate  840  is placed in the north direction  842  with a direction effect on a north direction and an electrical current flow toward the north direction  844 . 
         [0044]      FIG. 9  is a block diagram illustrating a silicon wafer  900  with placement of various charge monitor structures  910 ,  911 ,  912 ,  913  and  914  to sense charging effect on a single wafer. Each of the charge monitor structures  910 - 914  includes a CS-MOS memory structure and a CS-VG memory structure. The various charge monitor structures  910 - 914  can be placed at any position on the silicon wafer  900  to monitor the charging behavior in a particular area of the silicon wafer  900 . 
         [0045]    The invention has been described with reference to specific exemplary embodiments. For example, the charge storage structures in the present invention are applicable to any type or variations of a charge trapping memory including both n-channel and p-channel SONOS type of devices and floating gate memory. Accordingly, the specification and drawings are to be regarded as illustrative of the principles of this invention rather than restrictive, the invention is defined by the following appended claims.