Abstract:
A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to local-oscillator signal path or clock signal path and more particularly to a method and system for synchronizing the phase of output signals of a plurality of divider circuits. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a multiple-input multiple-output (MIMO) system where there are multiple transceivers, and each transceiver uses its own divider circuits to generate the desired local-oscillator (LO) frequency. The first time the divider circuits are enabled, the phase ambiguity needs to be calibrated by a loopback mechanism at the expense of time and power consumption. It is known that the enabling and disabling of the divider circuits can cause their phase to be unsynchronized with each other when they are enabled. 
         [0003]    This problem has been conventionally addressed by the divider circuits being enabled all the time (without disabling them) at the expense of higher power consumption. Accordingly, what is needed is a system and method to address these issues. 
         [0004]    Accordingly, the present invention addresses such a need. 
       SUMMARY OF THE INVENTION 
       [0005]    A method and system for synchronizing the phase of output signals of a plurality of frequency divider circuits in a local-oscillator signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a local-oscillator (LO) buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding a predetermined offset voltage to each of the plurality of frequency divider circuits; and enabling the plurality of frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the plurality of frequency divider circuits after the plurality of frequency divider circuits have been enabled. When the LO signal drives each of the plurality of frequency divider circuits, each of the plurality of frequency divider circuits starts a frequency division operation. Finally the method and system comprise removing the predetermined offset voltage from each of the plurality of frequency divider circuits to allow the plurality of frequency divider circuits to effectively drive other circuits. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  is a block diagram that illustrates a local-oscillator (LO) path within a MIMO system where a LO source drives a predetermined number (N) of frequency divider circuits through a LO buffer. 
           [0007]      FIG. 2  is a flow chart that illustrates a synchronization procedure for the divider circuits in accordance with the present invention. 
           [0008]      FIG. 3  illustrates an implementation of a differential divide-by-2 (divider number is 2) divider using a differential edge-triggered D flip-flop. 
           [0009]      FIG. 4  illustrates an implementation of a differential D flip-flop using two differential gated D latches, arranged in a master-slave configuration. 
           [0010]      FIG. 5  illustrates a differential divide-by-4 divider which can be implemented by 2 differential D flip-flops as shown. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    The present invention relates generally to local-oscillator signal path or clock signal path and more particularly to a method and system for synchronizing the phase of output signals from a plurality of divider circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. 
         [0012]      FIG. 1  is a block diagram that illustrates a local-oscillator (LO) path  100  within a MIMO system where a LO source  102  drives a predetermined number (N) of frequency divider circuits  106   a - 106   n  through a LO buffer  104 . Each divider circuit  106   a - 106   n  may have a different division number. For example, a divide-by-2 divider circuit divides the input frequency into half. Each time when the divider circuits  106   a - 106   n  are enabled from a disable (or power down) mode, the phase difference among the divider circuits  106   a - 106   n  may change since they are not synchronized with each other. This creates a problem in applications where phase synchronization among the divider output signals is important. 
         [0013]    A method and system in accordance with the present invention synchronizes these output signals without requiring that the divider circuits  106   a - 106   n  be enabled continuously. This is accomplished by providing offset voltages to the divider circuits  106   a - 106   n  prior to enabling the divider circuits  106   a - 106   n  and then enabling the divider circuits  106   a - 106   n.  Thereafter, the LO buffer  104  is enabled to provide LO signals to the plurality of divider circuits  106   a - 106   n.  The LO signals initiate each divider circuit  106   a - 106   n  frequency division operation. Thereafter, the offset voltages are removed and the output signals from divider circuits  106   a - 106   n  can be utilized to drive other circuits. To describe the features of the present invention in more detail refer now to the following description in conjunction with the accompanying Figures. 
         [0014]    A system that utilizes a synchronization procedure in accordance with the present invention can take the form of an entirely hardware implementation, an entirely software implementation, or an implementation containing both hardware and software elements. In one implementation, this synchronization procedure is implemented in software, which includes, but is not limited to, application software, firmware, resident software, microcode, etc. 
         [0015]    Furthermore, the synchronization procedure can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. 
         [0016]    The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and an optical disk. Current examples of optical disks include DVD, compact disk-read-only memory (CD-ROM), and compact disk-read/write (CD-R/W). To describe the features of the present invention in more detail, refer now to the following description in conjunction with the accompanying Figures. 
         [0017]      FIG. 2  is a flow chart that illustrates a synchronization procedure for the divider circuits in accordance with the present invention. Referring to  FIGS. 1 and 2  together, offset voltages are first added to the inputs of the divider circuits  106   a - 106   n  when they are in the disable mode, via step  202 . Next, the divider circuits  106   a - 106   n  are enabled with certain pre-defined states while the LO buffer  104  is still turned off, via step  204 . 
         [0018]    Typically, the divider circuits  106   a - 106   n  are implemented by differential current-mode logic (CML) circuits. These types of circuits have a positive-feedback loop which causes oscillation, if they are not driven by a strong differential LO signal at their clock inputs. To prevent oscillation in the divider circuits  106   a - 106   n,  a predetermined input offset voltage is introduced to break the positive-feedback loop. The predetermined offset voltage can be implemented at the output of the LO buffer  104  if the output of the LO buffer  104  is DC coupled to the input of the divider circuits  106   a - 106   n.  On the other hand, if the output of the LO buffer  104  is AC-coupled to the inputs of the divider circuits  106   a - 106   n,  the offset voltages need to be introduced at the inputs of the divider circuits  106   a - 106   n.  When the divider circuits  106   a  - 106   n  are enabled, pre-defined states need to be set to avoid random states.  FIGS. 3-5  illustrate different types of divider circuits that can be utilized in the synchronization procedure of  FIG. 2 . 
         [0019]      FIG. 3  shows an implementation of a differential divide-by-2 (divider number is 2) divider using a differential edge-triggered D flip-flop  300 . The D flip-flop  300  is a fully differential circuit where the output Q+  302 , the data input D+  306  and the clock input CLK+  310  are complementary to Q−  304 , D−  308  and CLK−  312  respectively. To implement the division-by-2 operation, the differential output signals Q+  302  and Q−  304  are connected to the differential data inputs D−  308  and D+  306  respectively in a crossed configuration, and the differential CLK+  310  and CLK−  312  are connected to the LO signal (not shown). If the differential clock inputs CLK+  310  and CLK−  312  are balanced when the LO buffer is disabled, the D flip-flop  300  may oscillate because this configuration forms a positive feedback loop. To prevent oscillation, the differential clock inputs need to be unbalanced by adding offset voltage. The offset voltage can added at the differential CLK inputs (CLK+  310  and CLK−  312 ) or at the differential LO buffer  104  outputs. 
         [0020]      FIG. 4  shows an implementation of the differential D flip-flop  400  using two differential gated D latches  402  and  404 , arranged in a master-slave configuration. In this configuration, the offset voltage can be added to the differential CLK inputs (CLK+  406  and CLK−  408 ). Alternately, the offset voltage can be added to one or both of the differential clk inputs (clk  422  and clk−  424 ; clk+  410  and clk−  412 ) of the D latches  402  and  404  respectively. Configured as a divider-by-2 divider as in  FIG. 3 , the differential output signals I+  414  and I−  416  have the same output frequency as the differential output signals Q+  426  and Q−  428 , and the phase difference between these two differential signals is 90 degrees. These in-phase (I) and quadrature-phase (Q) signals can be used to drive I and Q mixers in a RF transceiver. 
         [0021]    A differential divide-by-4 divider  500  can be implemented by 2 differential D flip-flops  502  and  504  as shown in  FIG. 5 . To prevent oscillation, the offset voltage can be added to one or both of the differential CLK inputs  506 - 508 ,  510 - 512  of the differential D flip-flops  502  and  504  respectively. Alternately, the offset voltage can be added to one of the 4 latches within the 2 flip-flops  502  and  504 . 
         [0022]    Referring back to  FIGS. 1 and 2 , next the LO buffer  104  is enabled to drive the divider circuits, via step  206 . When the divider circuits  106   a - 106   n  receive the LO signal from the LO buffer  104 , the frequency division operation of the divider circuits  106   a - 106   n  will be started if the LO signal swing is large enough to overcome the offset voltages. In other words, the offset voltage added cannot be so large that they prevent the LO signal from driving the divider circuits  106   a - 106   n  to perform the frequency division operations. For example, if the offset voltage is 50 mV, the LO signals should be at least larger than 50 mV, but preferably larger than 100 mV. Since all the divider circuits  106   a - 106   n  receive the LO signal at the same time, their output phases are synchronized with each other. Lastly, the offset voltages need to be removed so that they do not degrade the signal quality of each of the divider circuits  106   a - 106   n,  such as phase noise and phase accuracy, of the divider outputs, via step  208 . Before the outputs of the divider circuits  106   a - 106   n  are used to drive other circuits, the DC offsets need to be removed to prevent the offset voltages from degrading the performance of the divider circuits and the divider output signal qualities. In the case of the divide-by-2 divider  300  of  FIG. 3 , the offset voltage would degrade the output signal phase noise and the phase difference between the differential I and Q output signals. At this point, the divider outputs are ready to be used to drive other circuits, via step  210 . 
         [0023]    A method and system in accordance with the present invention synchronizes output signals of the frequency divider without requiring that the divider circuits be enabled continuously. This is accomplished by providing offset voltages to the divider circuits prior to enablement and then enabling the divider circuits. Thereafter, an LO buffer is enabled to provide LO buffer signals to the plurality of divider circuits. The LO buffer signal is such that each of the divider circuit&#39;s frequency division operation can then be initiated. In doing so, the LO path can be turned off when not in use without affecting the phase difference among the divider output signals when they are turned on. 
         [0024]    Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.