Abstract:
The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semi-conductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value. This process includes growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, wherein a first end surface, being the most outward surface of the diffusion barrier structure and being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state.

Description:
BACKGROUND ART  
       [0001]    The present invention relates to a process for realising a connecting structure in a semiconductor substrate and a semiconductor system including a semiconductor substrate in which such a connecting structure has been realised. 
         [0002]    As standard semiconductor manufacturing techniques are pushed towards shorter gate length, they approach the manufacturing limit of classic semiconductor technology. In order to further improve performances, reduce power consumption and packaging costs, integration techniques, such as 3D integration are becoming more and more common. 
         [0003]    3D integration consists in connecting at least two modules such as a semiconductor die, an optical module, a heat dissipation module, a biological module, and a memory, by stacking them one upon each other. Such an approach has several advantages. PCB-requirements are more relaxed since the integration is performed on a vertical direction. Power consumption of the input/output interfaces as well as signal quality are improved by connecting the modules to each other without making usage of long connecting cables or lines. Costs are reduced since a single package is required instead of a multitude of packages. Such integration technique allows miniaturisation of a high complexity system within a single package. 
         [0004]    Various techniques for connecting the multitude of modules stacked one upon the other have been developed. In order to connect at least two modules one upon each other, one possible technique consists in direct bonding. In such a technique, two modules, for instance, two semiconductor dies, are placed one upon each other and pressed against each other at a relatively low temperature, so that electrical contacts at the interface between the two dies can be created. 
         [0005]    For instance, as can be seen in  FIG. 8A , a first semiconductor die  8000  having a first surface  8100  might include a connecting structure  8200  composed by a conductive layer  8220  surrounded by a diffusion barrier layer  8211 . At the same time, a second semiconductor die  8700  might have a first surface  8710  and might incorporate a connecting structure  8200  including a conductive layer  8220  and a diffusion barrier layer  8211 . The connecting structure  8200  of the first semiconductor die  8000  and the connecting structure  8200  of the second semiconductor die  8700  might be substantially similar. 
         [0006]    3D integration might be performed by pressing the second semiconductor die  8700  on top of the first semiconductor die  8000  such that the first surface  8710  of the second semiconductor die  8700  presses against the first surface  8100  of the first semiconductor die  8000 . During such a procedure, the first semiconductor die  8000  and the second semiconductor die  8700  should be aligned, at least along a direction  1900 , so that the connecting structure  8200  of the first semiconductor die  8000  is aligned with the substantially similar connecting structure  8200  of the second semiconductor die  8700 . This is illustrated in  FIG. 8B  and patent document U.S. Pat. No. 6,962,835. 
         [0007]    Due to technological limits, however, a perfect alignment as shown in  FIG. 8B  can be hard to achieve. Practically, a small misalignment can be present, at least in one direction. As an example, in direction  1900 , as illustrated by the misalignment value M in  FIG. 8A . When such a 3D integration is performed subjected to the misalignment value M, a result as illustrated in  FIG. 8C  can be obtained. 
         [0008]    As can be seen in  FIG. 8C , the connecting structure  8200  of the first semiconductor die  8000  might not be aligned with the connecting structure  8200  of the second semiconductor die  8700 . A mismatch region  8500  can therefore be present, in which the conductive layer  8220  of the connecting structure  8200  of the second semiconductor die  8700  is placed above the diffusion barrier layer  8211  of the connecting structure  8200  of the first semiconductor die  8000  as well as being placed over a region of the semiconductor die  8000  not including the connecting structure  8200  of the first semiconductor die  8000 . 
         [0009]    In such a case, if, for example, the conductive layer  8220  of the connecting structure  8200  of the second semiconductor die  8700  is realised with copper, and the first semiconductor die is, for example, a silicon semiconductor die, there might be the possibly of the copper diffusing into the part of the first semiconductor die  8000  not corresponding to the connecting structure  8200  of the first semiconductor die  8000  through region  8500 . 
         [0010]    This problem is present in current 3D integration techniques and can therefore prevent or limit the application of such techniques in industrial manufacturing of integrated systems. Thus, improvements in this area are needed. 
       SUMMARY OF THE INVENTION 
       [0011]    Accordingly, the present invention now provides a connecting structure to be used in a semiconductor substrate subjected to 3D integration such that diffusion of the metal composing the connecting structure is prevented, even in the presence of a misalignment during the 3D integration process. 
         [0012]    In particular, the present invention relates to a process for realizing a connecting structure in a semiconductor substrate, according to an embodiment of the present invention, the semiconductor substrate having at least a first surface, and being foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value (M), can include the step of growing a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure can have a length, in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length of the diffusion barrier structure is chosen such that in a 3D integrated structure a diffusion of elements out of a conductive layer of the second substrate is prevented in the integrated state. 
         [0013]    By carrying out such process, it is possible to realize a connecting structure which can be aligned during a 3D integration process, to a corresponding connecting structure on the first integrated substrate, even in the presence of a misalignment during the 3D integration. By taking into account the misalignment value, the diffusion barrier structure can be sized so as to compensate for the misalignment and prevent diffusion of a conductive element. 
         [0014]    In some embodiments, the length can be at least as long as the lateral misalignment value. 
         [0015]    By choosing the length of the diffusion barrier structure so that it is as least the misalignment value, even in the case of maximum misalignment, prevention of diffusion of the conductive element can be ensured. 
         [0016]    In some embodiments, the length can be at least as long as a length of the conductive layer of the second substrate along the direction of the misalignment. 
         [0017]    By choosing the length of the diffusion barrier structure so that it is as least as long as a length of the conductive layer of the second substrate along the direction of the misalignment, prevention of diffusion of the conductive element can be ensured whenever a contact between the conductive layers of the first and second substrate is achieved. 
         [0018]    In some embodiments, the process for realizing a connecting structure can further include a step of growing, after having grown the diffusion barrier structure, at least a conductive layer so that the conductive layer is separated from the semiconductor substrate by at least the diffusion barrier structure. 
         [0019]    By growing a conductive element after having grown the diffusion barrier structure, it is possible to realize a diffusion barrier structure having a length of the first end surface corresponding to the thickness of the diffusion barrier structure, and then deposit the conductive element directly on top of the diffusion barrier structure. In such way, only two deposits, the diffusion barrier structure and the conductive element, are needed. 
         [0020]    In some embodiments, the process for realizing a connecting structure can further include a step of growing, before growing the diffusion barrier structure, at least a conductive layer. 
         [0021]    By growing a conductive element before growing the diffusion barrier structure, it is possible to realize a diffusion barrier structure having the required length, only in specific zones with respect to the position of the already grown conductive element. 
         [0022]    In some embodiments, the step of growing the diffusion barrier structure can include a step of growing a diffusion barrier layer. 
         [0023]    By using a diffusion barrier layer as a diffusion barrier structure, the process of growing a diffusion barrier structure could be precisely controlled. Moreover, by using the diffusion barrier layer as a diffusion barrier structure, only a single manufacturing step might be needed in order to grow the diffusion barrier structure. 
         [0024]    In some embodiments, the step of growing the diffusion barrier structure can further comprise a step of growing a second layer on the diffusion barrier layer having a growing rate higher than the diffusion barrier layer. 
         [0025]    By using two layers for growing the diffusion barrier structure, it is possible to employ one thinner diffusion barrier layer, having a low growth rate, and a second layer having a faster grow ratio. In such a case, it could be possible to deposit both layers using the same set of mask. However, thanks to the faster growing rate of the second layer, a quicker production could be obtained. 
         [0026]    In some embodiments, the step of growing the diffusion barrier layer can comprise growing a layer of at least one of Tantalum (Ta), Tantalum nitride (TaN), Silicon nitride (Si3N4). 
         [0027]    By choosing the diffusion barrier layer between those elements, an optimal effect of preventing the diffusion of conductive material can be achieved. 
         [0028]    In some embodiments, the length of the diffusion barrier structure can be between 20 nm and 1 μm. 
         [0029]    By growing the diffusion barrier structure with a length that is substantially longer than the usual length of a standard diffusion barrier layer, the advantage of preventing conductive element diffusion, even in the case of misalignment, can be achieved. 
         [0030]    A process for realizing a 3D integration of at least two semiconductor substrates, according to a further embodiment of the present invention, can include the steps of: realizing a connecting structure in at least one preferably each one of the two semiconductor substrates according to the process for realizing a connecting structure in a semiconductor substrate, according to an embodiment of the present invention as described above; attaching the two semiconductor substrates along the first surface of each of the two semiconductor substrates. 
         [0031]    By realizing the 3D integration using two substrates obtained by the process for realizing a connecting structure in a semiconductor substrate, according to an embodiment of the present invention, it is possible to realize a connection between the two substrates, capable of preventing undesired diffusion of conductive material even in the presence of misalignment during the 3D integration process. 
         [0032]    In some embodiments, the step of attaching the two semiconductor substrates can include a step of attaching, in particular by bonding, the two semiconductor substrates to each other. 
         [0033]    By bonding the two substrates to each other, a stable connection can be ensured, and a further misalignment of the connection regions can be prevented. 
         [0034]    A semiconductor system, according to a further embodiment of the present invention, can include at least a first substrate and a second substrate, at least the first substrate including a connecting structure, wherein the first substrate has at least a first surface, and is 3D integrated with the second substrate along the first surface, wherein the 3D integration has a lateral misalignment in at least one dimension having a misalignment value (M); and the connecting structure includes a diffusion barrier structure for preventing diffusion of elements out of a conductive layer into the material of the substrate, characterized in that, the diffusion barrier structure is configured so that a first end surface, being the most outward surface of the diffusion barrier structure being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure has a length (L), in the direction of the lateral misalignment, the length being dependent on the misalignment value, wherein the length (L) of the diffusion barrier structure is chosen such that a diffusion of elements out of a conductive layer of the second substrate is prevented. 
         [0035]    By realizing a semiconductor system in such a manner, it is possible to realize a stable electrical connection during a 3D integration process, between corresponding connecting structures on the first and second substrates, even in the presence of a misalignment during the 3D integration. By taking into account the misalignment value, the diffusion barrier structure can be sized so as to compensate for the misalignment and prevent diffusion of a conductive element. 
         [0036]    In some embodiments, the length can be at least as long as the lateral misalignment value. 
         [0037]    By choosing the length of the diffusion barrier structure so that it is as least the misalignment value, even in the case of maximum misalignment, prevention of diffusion of the conductive element can be ensured. 
         [0038]    In some embodiments, the length can be at least as long as a length of the conductive layer of the second substrate along the direction of the misalignment. 
         [0039]    By choosing the length of the diffusion barrier structure so that it is as least as long as a length of the conductive layer of the second substrate along the direction of the misalignment, prevention of diffusion of the conductive element can be ensured whenever a contact between the conductive layers of the first and second substrate is achieved. 
         [0040]    In some embodiments, the connecting structure can further include at least a conductive layer so that the conductive layer is separated from the first substrate by at least the diffusion barrier structure. 
         [0041]    By separating the conductive element from the substrate by means of the diffusion barrier structure, it could be possible to use the diffusion barrier structure both in order to prevent the diffusion of the conductive element of the connecting structure of the first substrate into the first substrate as well as preventing the diffusion of the conductive element of the connecting structure of the second substrate into the first substrate. 
         [0042]    In some embodiments, the diffusion barrier structure can include a diffusion barrier layer. 
         [0043]    By using a diffusion barrier layer as a diffusion barrier structure, the process of growing a diffusion barrier structure could be precisely controlled. Moreover, by using the diffusion barrier layer as a diffusion barrier structure, only a single manufacturing step might be needed in order to grow the diffusion barrier structure. 
         [0044]    In some embodiments, the diffusion barrier structure can include a diffusion barrier layer and a second layer on the diffusion barrier layer having a growing rate higher than the diffusion barrier layer. 
         [0045]    By using two layers for growing the diffusion barrier structure, it is possible to employ one thinner diffusion barrier layer, having a low growth rate, and a second layer having a faster grow ratio. In such a case, it could be possible to deposit both layers using the same set of mask. However, thanks to the faster growing rate of the second layer, a quicker production could be obtained. 
         [0046]    In some embodiments, the diffusion barrier layer can be any of tantalum (Ta), tantalum nitride (TaN), or silicon nitride (Si3N4). 
         [0047]    Preferably, the connecting structure is defined by a hole in the substrate, the diffusion barrier being provided in the hole on the sidewall and bottom thereof, and conductive material is provided in the hole on the diffusion barrier, wherein the diffusion barrier has a thickness on the hole sidewall that is at least the same as the misalignment value. 
         [0048]    By choosing the diffusion barrier layer between those elements, an optimal effect of preventing the diffusion of conductive material can be achieved. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0049]    The accompanying drawings are incorporated into and form a part of a specification to illustrate several embodiments of the present invention. These drawings together with the description serve to explain the features, advantages and principles of the invention. The drawings are only for the purpose of illustrating preferred and alternative examples of how the invention can be made and used, and are not to be construed as limiting the invention to only the illustrated and described embodiments. Further features and advantage will become apparent from the following and more particular description of the various embodiments of the invention, as illustrated in the accompanying drawings, in which like reference prefer to like elements and wherein: 
           [0050]      FIG. 1  is a schematic drawing illustrating two substrates for 3D integration, used in embodiments of the present invention; 
           [0051]      FIG. 2  is a schematic drawing illustrating a process for realising a connecting structure according to a first embodiment of the present invention; 
           [0052]      FIG. 3A  is a schematic drawing illustrating two substrates undergoing a process of 3D integration according to an embodiment of the present invention; 
           [0053]      FIG. 3B  is a schematic drawing illustrating the result of 3D integration of two substrates according to an embodiment of the present invention; 
           [0054]      FIG. 4  is a schematic drawing illustrating a process for realising a connecting structure according to a second embodiment of the present invention; 
           [0055]      FIG. 5  is a schematic drawing illustrating a process for realising a connecting structure according to a third embodiment of the present invention; 
           [0056]      FIGS. 6A ,  6 B are a schematic drawings illustrating a process for realising a connecting structure according to a fourth embodiment of the present invention; 
           [0057]      FIGS. 7A ,  7 B are schematic drawings illustrating a 3D system including two substrates according to a fifth embodiment of the present invention; 
           [0058]      FIG. 8A  is a schematic drawing illustrating two substrates undergoing a process of 3D integration according to the state of the art; 
           [0059]      FIG. 8B  is a schematic drawing illustrating the result of 3D integration of two substrates according to the state of the art, in absence of an integration misalignment; 
           [0060]      FIG. 8C  is a schematic drawing illustrating the result of 3D integration of two substrates according to the state of the art, in presence of an integration misalignment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0061]    In the following description, for explanatory purposes, specific details are set forth in order to provide a thorough understanding thereof. It may be evident, however, that the present invention can be practised without these specific details. 
         [0062]    As can be seen in  FIG. 8 , the shape of the conductive layer  8220  and the diffusion barrier layer  8211  of the connecting structure  8200  of the first semiconductor die  8000 , along the surface corresponding to the first surface  8100 , might be substantially the same of the shape of the conductive layer  8220  and the diffusion barrier layer  8211  of the connecting structure  8200  of the second semiconductor die  8700 , along the surface corresponding to the first surface  8710 . 
         [0063]    The conductive layer  8220  might be used in order to carry an electric signal and might be realized with a material having electrical properties adapted to the propagation of such a signal. The diffusion barrier layer might be used in order to prevent the material of the conductive layer  8220  from diffusing into the first semiconductor die  8000  or into the second semiconductor die  8700 . 
         [0064]    By aligning, it is meant that the first semiconductor die  8000  might be placed along direction  1900  in such a way that the surface of the conductive layer  8220  of the connecting structure  8200  of the first semiconductor die  8000  and the surface of the conductive layer  8220  of the connecting structure  8200  of the second semiconductor die  8700  substantially occupy the same area along a plane including direction  1900  and perpendicular to direction  1800 . At the same time, by aligning it is meant that the first semiconductor die  8000  might be placed along direction  1900  in such a way that the surface of the diffusion barrier layer  8211  of the connecting structure  8200  of the first semiconductor die  8000  and the surface of the diffusion barrier layer  8211  of the connecting structure  8200  of the second semiconductor die  8700  substantially occupy the same area along the plane including direction  1900  and perpendicular to direction  1800 . Such a situation is illustrated in  FIG. 8B . 
         [0065]    Since the situation illustrated in  FIG. 8B  might not be achieved due to technological limits, however, a structure must be realized such that, even in the presence of misalignment, diffusion of conducting material in the semiconductor substrates is prevented. 
         [0066]      FIG. 1  illustrates a first semiconductor substrate  1000  and a second semiconductor substrate  1700  undergoing a 3D integration. The 3D integration might comprise a bonding process. 
         [0067]    The first semiconductor substrate  1000  has at least a first surface  1100  and the second semiconductor substrate  1700  has at least a first surface  1710 . Both semiconductor substrates  1000  and  1700  might include a plurality of circuitry, such as transistor, diodes, capacitors, metal lines and vias, identified by reference numerals  1600 . Both the first semiconductor substrate  1000  and the second semiconductor substrate  1700  might additionally include further modules, e.g. optical modules, biological modules, memories, and/or power modules not illustrated in  FIG. 1 . Furthermore, either or both of the first semiconductor substrate  1000  and the second semiconductor substrate  1700  could comprise any of a silicon wafer, a silicon on insulator wafer, a glass substrate, or more generally a substrate. 
         [0068]    The first semiconductor substrate  1000  and the second semiconductor substrate  1700  might be integrated by bonding them along a surface corresponding to the first surface  1100  and the first surface  1710  by approaching them to each other along direction  1800  and by applying a predetermined amount of pressure at a predetermined temperature, in a predetermined environment as indicated by arrows  1150 . 
         [0069]    The bonding may correspond in particular to the technique disclosed in U.S. Pat. No. 6,962,835 or, more preferably, to the technique disclosed in “Enabling 3D Interconnects with Metal Direct Bonding” from Di Cioccio and Al (IITC 2009). It could also be other technique like external thermo compression bonding. 
         [0070]    Moreover, both the first semiconductor substrate  1000  and the second semiconductor substrate  1700  include connecting structures  1200  placed at substantially similar positions along a plane, including direction  1900  and perpendicular to direction  1800 , such that, when the two semiconductor substrates are approached to each other along direction  1800 , connecting structures  1200  of the first semiconductor substrate  1000  enter in contact with corresponding connecting structures  1200  of the second semiconductor substrate  1700 . For instance, connecting structure  1201  of the first semiconductor substrate  1000  shall contact connecting structure  1202  of the second semiconductor substrate  1700 . Although in  FIG. 1  only two connecting structures are illustrated, of course, there could be and usually is many more connecting structures. Furthermore, in this invention, the diffusion barrier structure surrounds the conductive material and provides a barrier Between it and the substrate. 
         [0071]      FIG. 2  is a schematic drawing illustrating a process for realising a connecting structure according to a first embodiment of the present invention. More specifically,  FIG. 2  illustrates a process of realising a connecting structure  2200  such as, for instance, connecting structure  1201  of the first semiconductor substrate  1000 , and/or connecting structure  1202  of the second semiconductor substrate  1700 , and/or any of connecting structures  1200  of  FIG. 1 . 
         [0072]    A semiconductor substrate  2000 A includes a hole  2300 , as can be seen in  FIG. 2 . The hole  2300  might be realised starting from a semiconductor substrate through step S 20 , by carrying out, for instance, photolithography and etching. The size, shape, depth and position of hole  2300  might be controlled in a manner known in the art of semiconductor manufacturing. 
         [0073]    By carrying out a deposition and/or growing step S 21 , a diffusion barrier layer  2211  is realised on top of semiconductor substrate  2000 A so as to obtain semiconductor substrate  2000 B. The realisation of the diffusion barrier layer  2211  could be performed in a known semiconductor substrate manufacturing process, such as deposition and/or growing, including, for instance, Chemical Vapour Deposition (CVD), Physical Vapour Deposition (PVD), Epitaxy or other techniques. The diffusion barrier layer might be a layer of material having the property of blocking the diffusion of metal atoms such as, for instance, tantalum (TA), tantalum nitride (TAN), or silicon nitride (SI3N4). 
         [0074]    Subsequently, through a step S 22 A, might consists of a seed deposition of a conductive layer  2221 , the semiconductor substrate  2000 C is obtained. The seed deposition process could be performed with techniques known in the art such as PVD seed or CVD seed. The conductive layer  2221  might be, for instance, copper, silver, gold or any other material having electrical conductivity. 
         [0075]    Subsequently, through a step S 22 B which consists of a deposition of a conductive layer  2222 , the semiconductor substrate  2000 D is obtained. The step S 22 B might consist of electrochemical deposition (ECD). The conductive layer  2222  might be the same material as the conductive layer  2221 , which might facilitate the adhesion of the conductive layer  2222  on conductive layer  2221 . Alternatively, the conductive layer  2222  might be a material differing from the conductive layer  2221 , which might speed up the growing process, or might provide a better electrical conductivity, or might reduce production costs. 
         [0076]    Subsequently, the semiconductor substrate  2000 D could be subjected to a step S 23  consisting in a chemical mechanical polishing (CMP) so as to obtain semiconductor substrate  2000 E. 
         [0077]    Thanks to this process, a connecting structure  2200  such as the one illustrated in the semiconductor substrate  2000 E is obtained. 
         [0078]    The connecting structure  2200  includes a diffusion barrier layer  2211  and a conductive layer  2220 . Moreover, the diffusion barrier layer  2211  has a surface  2230  substantially parallel to the first surface  2100  of the semiconductor substrate  2000 E. The size of the end surface  2230  in this embodiment is substantially determined by the thickness d of the material forming the diffusion barrier layer  2211  deposited during step S 21 . Accordingly, it might be possible to control the length L of the end surface  2230 , along at least direction  1900 , by controlling the amount of deposited material during step S 21 . 
         [0079]    In semiconductor substrate  2000 E, the surface  2230  of diffusion barrier layer  2211  can act as a diffusion barrier structure, thereby preventing the diffusion of elements out of a conductive layer of a second semiconductor substrate, into semiconductor substrate  2000 E, even in the presence of misalignment. 
         [0080]      FIG. 3A  is a schematic drawing illustrating two substrates undergoing a process of 3D integration according to the first embodiment of the present invention: More specifically,  FIG. 3A  illustrates a first semiconductor substrate  1000  and a second semiconductor substrate  1700  undergoing 3D integration along the direction  1800 . 
         [0081]    As can be seen in  FIG. 3A , the first semiconductor substrate  1000  might have a lateral misalignment along direction  1900  with respect to the second semiconductor substrate  1700 . The lateral misalignment along direction  1900  might have a value M, for instance, in the order of approximately 20 nm to approximately 1 μm, or, for instance, even more than 1 μm. Both the first semiconductor substrate  1000  and the second semiconductor substrate  1700  include a connecting structure  2200  as obtained by the process described in  FIG. 2 . The connecting structure  2200  thus has a surface  2230  having a length, in direction  1900  corresponding to a value L typically in the order of 20 nm to 1 μm, acting as a diffusion barrier structure. 
         [0082]      FIG. 3B  is a schematic drawing illustrating the result of 3D integration of two substrates according to an embodiment of the present invention. More specifically,  FIG. 3B  illustrates a semiconductor system obtained by the 3D integration of the first semiconductor substrate  1000  and the second semiconductor substrate  1700 . 
         [0083]    In one alternative embodiment, the length L of surface  2230  of the first semiconductor substrate  1000  might be longer than the length of the conductive layer  2220  of the second semiconductor substrate  1700  along direction  1900 . By choosing the length L in such a manner, it is possible to ensure that diffusion is prevented, whenever a contact between the conductive layer  2220  of the first semiconductor substrate  1000  and the conductive layer  2220  of the second semiconductor substrate  1700  is realized. 
         [0084]    As can be seen in  FIG. 3B , the connecting structure  2200  of the first semiconductor substrate  1000  are misaligned with respect to the connecting structure  2200  of the second semiconductor substrate  1700 . However, the conductive layer  2220  of the connecting structure  2200  of the second semiconductor substrate  1700  can be prevented from diffusing into the first semiconductor substrate  1000  thanks to the diffusion barrier layer  2211  of the connecting structure  2200  of the first semiconductor substrate  1000 . Therefore, unlike in the prior art as illustrated in  FIG. 8C  where conductive material could diffuse through a region  8500 , conductive layer  2200  of the second semiconductor substrate  1700  is always placed over a region including conductive layer  2200  of the first semiconductor substrate  1000  or over a region including conductive layer  2200  and surface  2230  of the first semiconductor substrate. In such a way, diffusion of the material composing conductive layer  2200  into the semiconductor substrate  1000  can be prevented. 
         [0085]    More specifically, as can be seen in  FIG. 3A , the diffusion barrier layer  2211  of the connecting structure  2200  of the first semiconductor substrate  1000  could have an end surface  2230  having a length L in the direction  1900  of the misalignment. By choosing the length value L so as to be at least as big as the misalignment value M, the result illustrated in  FIG. 3B  can be obtained. More specifically, by choosing the length L in the direction  1900  of the surface  2230  so as to be at least corresponding to the misalignment value M in the direction  1900 , it is ensured that the conductive layer  2220  of connecting structure  2200  of the second semiconductor substrate  1700  is only placed over the conductive layer  2220  of the connecting structure  2200  of the first semiconductor substrate  1000  or the surface  2230  of the diffusion barrier layer  2211  of the connecting structure  2200  of the first semiconductor substrate  1000 . In other words, by choosing a length L of the surface  2230  so as to be at least as big as a misalignment value M, the diffusion of the electrically conductive material  2220  of the connecting structure  2200  of the second semiconductor substrate  1700  into the first semiconductor substrate  1000  can be prevented. 
         [0086]    Alternatively, or in addition, the length L of the surface  2230  could be set as a function of, for instance, a maximum misalignment value M in consecutive 3D integrations, or an average misalignment value M in consecutive 3D integrations. In this manner, it can be insured that, in absolute terms, or on average, the misalignment will not cause a diffusion of conductive material  2200  in the semiconductor substrates  1000  and/or  1700 . 
         [0087]    Alternatively, or in addition, the length L of the surface  2230  in the first semiconductor substrate  1000  could be set so as to be at least as big as the length of the conductive material  2200  of the connecting structure of the second semiconductor substrate  1700 . In this manner, it is guaranteed that, whenever a contact between the conductive material  2200  of the first semiconductor substrate  1000  and of the second semiconductor substrate  1700  is achieved, diffusion will be prevented. This is advantageous in cases where the value of the misalignment is not known, whereas the length of the conductive material  2200  of the connecting structure of the second semiconductor substrate  1700  is known. 
         [0088]    Moreover, the misalignment value M could be different for different locations of the semiconductor substrate  1000 . For instance, in addition to a misalignment due to a tolerance of a manufacturing or a handling machine, there could be a misalignment due to pressure being exerted on the semiconductor substrate, or due to a temperature gradient across the substrate. In the cases were the misalignment value M is not constant across the wafer, this could be taken into account when choosing the value L of the surface  2230  for different connecting structures  2200  located in different parts of the wafer. 
         [0089]      FIG. 4  is a schematic drawing illustrating a process for realising a connecting structure  4200  according to a second embodiment of the present invention. More specifically,  FIG. 4  illustrates a process of realising a connecting structure  4200  such as, for instance, connecting structure  1201  of the first semiconductor substrate  1000 , and/or connecting structure  1202  of the second semiconductor substrate  1700 , and/or any of connecting structures  1200  of  FIG. 1 . 
         [0090]    As can be seen in  FIG. 4 , a semiconductor substrate  4000 A having a first hole  4320  and a second hole  4310  encircling the first hole towards the surface  4100  could be obtained by a step S 40 . The first hole  4320  might be realised starting from a semiconductor substrate through step S 40 , by carrying out, for instance, photolithography and etching. The size, shape, depth and position of first hole  4320  might be controlled in a manner known in the art of semiconductor manufacturing. Similarly, the second hole  4310  might be realised starting from a bulk semiconductor substrate through step S 40 , by carrying out, for instance, the well-known processes of photolithography and etching. The size, shape, depth and position of second holes  4310  might be controlled in a manner known in the art of semiconductor manufacturing. Alternatively, or in addition both the first hole  4320  and the second holes  4310  could be realized in a single photolithographic step. 
         [0091]    The length of the second holes  4310 , in at least the direction  1900 , could be chosen so as to correspond to a desired length L. 
         [0092]    Subsequently, a diffusion barrier layer  4211  is deposited on semiconductor substrate  4000 A so as to obtain semiconductor substrate  4000 B via step S 41 . Techniques for carrying out step S 41  could be substantially similar to techniques for carrying out step S 21  in  FIG. 2 . Moreover, the diffusion barrier layer  4211  could be substantially similar to the diffusion barrier layer  2211  in  FIG. 2 . 
         [0093]    Subsequently, a conductive layer  4221  and a conductive layer  4222  are deposited on the semiconductor substrate  4000 B so as to obtain, respectively, semiconductor substrates  4000 C and  4000 D via steps S 42 A and S 42 B. Steps S 42 A and S 42 B could be substantially similar to step S 22 A and S 22 B in  FIG. 2 . Moreover, conductive layers  4221  and conductive layer  4222  could be substantially similar to conductive layer  2221  and conductive layer  2222  in  FIG. 2 , respectively. 
         [0094]    Finally, via a step S 43 , semiconductor substrate  4000 E is obtained. Step S 43  could be substantially similar to step S 23  in  FIG. 2 . Following the step S 43 , the material of the diffusion barrier layer  4211  remaining in the second holes  4310  has a length, in at least direction  1900 , corresponding to the desired value L, in at least a surface region  4230  of the surface  4100 , thus acting as a diffusion barrier structure in a 3D structure, even in the presence of misalignment. 
         [0095]    Thanks to the process outlined in  FIG. 4 , a connecting structure  4200  could be obtained, including a conductive element  4220  and a diffusion barrier layer  4211 . The conductive element  4220  could be substantially the same as the conductive element  2220  in  FIG. 2 . On the other hand, thanks to the second holes  4310 , the diffusion barrier layer  4211  could be substantially thinner in the bulk than the diffusion barrier layer  2211  of  FIG. 2 . Although being thinner, the diffusion barrier layer  4211 , deposited in the holes  4310 , still provides a surface  4230  substantially similar to the surface  2230  of the  FIG. 2 . Accordingly, the same advantages obtained by the connecting structure  2200  of  FIG. 2  could be obtained by the connecting structure  4200  of  FIG. 4 . Moreover, since growing of a diffusion barrier layer  4211  in step S 41  could be a relatively long operation, the possibility of growing a thinner layer  4211  while still realising a large surface  4230  having a desired length L, could be advantageous both in terms of reduced costs and in terms of reduced processing time. 
         [0096]    In semiconductor substrate  4000 E, the surface  4230  of diffusion barrier layer  4211  can act as a diffusion barrier structure, thereby preventing the diffusion of elements out of a conductive layer of a second semiconductor substrate, into semiconductor substrate  4000 E, even in the presence of misalignment. 
         [0097]      FIG. 5  is a schematic drawing illustrating a process for realising a connecting structure  5200  according to a third embodiment of the present invention. More specifically,  FIG. 5  illustrates a process of realising a connecting structure  5200  such as, for instance, connecting structure  1201  of the first semiconductor substrate  1000 , and/or connecting structure  1202  of the second semiconductor substrate  1700 , and/or any of connecting structures  1200  of  FIG. 1 . 
         [0098]      FIG. 5  illustrates a semiconductor substrate  5000 A with a conductive layer  5220  and a diffusion barrier layer  5212  achieved by a step S 52 . Techniques for carrying out step S 52  could be substantially similar to techniques for carrying out steps S 22 A and S 22 B in  FIG. 2 . 
         [0099]    Subsequently, a semiconductor substrate  5000 B having a hole  5310  on the diffusion barrier layer  5212  surrounding the conductive layer  5220  or near the surface  5100  is obtained by a step S 50 . The size, shape, depth and position of hole  5310  might be controlled in a manner known in the art of semiconductor manufacturing. Techniques for carrying out step S 50  could be substantially similar to techniques for carrying out step S 20  in  FIG. 2 . 
         [0100]    Subsequently, a diffusion barrier layer  5211  is deposited on semiconductor substrate  5000 B so as to obtain semiconductor substrate  5000 C via step S 51 . Techniques for carrying out step S 51  could be substantially similar to techniques for carrying out step S 21  in  FIG. 2 . Moreover, the diffusion barrier layer  5211  could be substantially similar to the diffusion barrier layer  2211  in  FIG. 2 . During this step, at least the hole  5310  is filled with the barrier layer material. 
         [0101]    Finally, via a step S 53 , semiconductor substrate  5000 D is obtained. Step S 53  could be a CMP substantially similar to step S 23  in  FIG. 2  to remove excessive material. Following the step S 43 , the material of diffusion barrier layer  5211  remaining in the holes  5310  could have a length, in at least direction  1900 , corresponding to the desired value L, in at least a surface  5230 , acting as a diffusion barrier structure. 
         [0102]    By carrying out the process described in  FIG. 5 , it is possible to realize a diffusion barrier layer  5211  after a conductive material has already been deposited. Moreover, it is possible to realize a surface  5230  having a desired length L, with a relatively thin barrier diffusion layer  5211 . This could have the advantage of increasing manufacturing speed and therefore reducing costs. 
         [0103]    In semiconductor substrate  5000 D, the surface  5230  of diffusion barrier layer  5211  can act as a diffusion barrier structure, thereby preventing the diffusion of elements out of a conductive layer of a second semiconductor substrate, into semiconductor substrate  5000 D, even in the presence of misalignment. 
         [0104]      FIGS. 6A and 6B  are schematic drawings illustrating a process for realising a connecting structure  6200  according to a fourth embodiment of the present invention. More specifically,  FIGS. 6A and 6B  illustrates a process of realising a connecting structure  6200  such as, for instance, connecting structure  1201  of the first semiconductor substrate  1000 , and/or connecting structure  1202  of the second semiconductor substrate  1700 , and/or any of connecting structures  1200  of  FIG. 1 . 
         [0105]    As can be seen in  FIG. 6A , a semiconductor substrate  6000 A having a first hole  6320  is obtained by a step S 40 . The first hole  6320  might be realised starting from a bulk semiconductor substrate through step S 60 . Techniques for carrying out step S 60  could be substantially similar to techniques for carrying out step S 20  in  FIG. 2 . 
         [0106]    Subsequently, a diffusion barrier layer  6211  is deposited on semiconductor substrate  6000 A so as to obtain semiconductor substrate  6000 B via step S 61 A. Techniques for carrying out step S 61 A could be substantially similar to techniques for carrying out step S 21  in  FIG. 2 . Moreover, the diffusion barrier layer  6211  could be substantially similar to the diffusion barrier layer  2211  in  FIG. 2 . 
         [0107]    Subsequently, a second layer  6213  is deposited on semiconductor substrate  6000 B so as to obtain semiconductor substrate  6000 C via step S 61 B. The second layer  6213  is deposited onto diffusion barrier layer  6211 . The second layer  6213  is also acting as a diffusion barrier layer and could be, for instance, TiN, and has a growth rate higher than the diffusion barrier layer  6211 . 
         [0108]    Second layer  6213  can have a faster growth rate than diffusion barrier layer  6211  thanks to the working conditions in which it is deposited. That is, the growth rate of diffusion barrier layer  6211  can be influenced by the fact that diffusion barrier layer  6211  is deposited on semiconductor substrate  6000 A, while the growth rate of second layer  6213  could be faster, due to the fact that second layer  6213  can be deposited on the diffusion barrier layer  6211 . In other words, due to the constraint of realizing a deposition of diffusion barrier layer  6211 , on semiconductor substrate  6000 A, which has good characteristics and no holes, the deposition of diffusion barrier layer  6211  could be slow. On the other hand, second layer  6213  could be deposited with a faster growth rate by being deposited on diffusion barrier layer  6211  instead of on semiconductor substrate  6000 A. 
         [0109]    Alternatively, second layer  6213  and diffusion barrier layer  6211  could be realized with the same material, among the materials described for second layer  6213  and diffusion barrier layer  6211 , and only the growth rate of the material could be increased during the deposition so as to realize a higher quality layer in a first part of the deposition, by using a slower growth rate, and a faster growing layer in a second part of the deposition, by using a quicker growth rate. 
         [0110]    Subsequently, a conductive layer  6221  and a conductive layer  6222  are deposited on the second layer  6213  of semiconductor substrate  6000 C so as to obtain, respectively, semiconductor substrates  6000 D and  6000 E via steps S 62 A and S 62 B. Steps S 62 A and S 62 B could be substantially similar to step S 22 A and S 22 B in  FIG. 2 . Moreover, conductive layers  6221  and conductive layer  6222  could be substantially similar to conductive layer  6221  and conductive layer  6222  in  FIG. 2 , respectively. 
         [0111]    In this embodiment, as well as the previous embodiments, the seed conductive layer  6221  might not be necessary and a single deposition of a conductive layer  6222  could be performed instead of a deposition of a conductive layer  6221  and a conductive layer  6222 . 
         [0112]    Finally, via a step S 63 , semiconductor substrate  6000 F is obtained. Step S 63  to remove material could be a CMP process substantially similar to step S 23  in  FIG. 2 . Following the step S 63 , the combined diffusion barrier layers  6211  and  6123  present a surface  6230 , acting as a diffusion barrier structure. 
         [0113]    By carrying out the process outlined in  FIGS. 6A and 6B , a diffusion barrier structure is realized with a surface  6230 , having a length L in at least a direction  1900 , in a time relatively shorter than a time required for realizing a diffusion barrier layer, having a comparable length in the direction  1900 . In such a manner, a diffusion barrier structure  6211 , 6213 , having a surface  6230 , could take less time to perform than, for instance, step S 21  of  FIG. 2 , in which a thicker diffusion barrier layer  2211  could be deposited. Accordingly, manufacturing costs could be reduced. 
         [0114]    In semiconductor substrate  6000 F, the surface  6230  of diffusion barrier layers  6211  and  6213  can act as a diffusion barrier structure, thereby preventing the diffusion of elements out of a conductive layer of a second semiconductor substrate, into semiconductor substrate  6000 F, even in the presence of misalignment. 
         [0115]      FIGS. 7A and 7B  illustrate a semiconductor system  7000  in accordance with a fifth embodiment of the present invention.  FIG. 7A  is a section view of the system, taken along a plane perpendicular to the two semiconductor substrates.  FIG. 7B  is a top view of the system, taken along a plane perpendicular to the plane of  FIG. 7A . The semiconductor system  7000  is obtained by integrating, via a 3D integration, a first semiconductor substrate  1000  and a second semiconductor substrate  1700 . Both the first  1000  and second  17000  semiconductor substrate include ad least one connecting structure  2200 . The connecting structure  2200  could be realized with any of the processes defined by the previous embodiments. Reference  2211 A indicates the diffusion barrier of the first semiconductor substrate  1000 , while reference  2211 B indicates the diffusion barrier of the second semiconductor substrate  1700 . 
         [0116]    Moreover, as can be seen in top view of  FIG. 7B , the first semiconductor substrate  1000  could be misaligned with respect to the second semiconductor substrate  1700  both along direction  1800  and along direction  1900 . The misalignment values along those two directions are M 1800  and M 1900  respectively. In such a case, the dimensions  7810 ,  7820 ,  7910 ,  7920  of the diffusion barrier  2211 A could be chosen so as follows: 
         [0117]    dimension  7810 , along direction  1800  could be of any value, preferably at least a value which can be manufactured; 
         [0118]    dimension  7910 , along direction  1900  could be of any value, preferably at least a value which can be manufactured; 
         [0119]    dimension  7820 , along direction  1800  could be chosen so as to correct for the misalignment M 1800  in the manner described in the previous embodiments. For instance, it could be chosen to correspond to at least the misalignment value M 1800 ; 
         [0120]    dimension  7920 , along direction  1900  could be chosen so as to correct for the misalignment M 1900  in the manner described in the previous embodiments. For instance, it could be chosen to correspond to at least the misalignment value M 1900 . 
         [0121]    Alternatively, or in addition, dimension  7810  could be chosen so as to correspond to dimension  7820 , alternatively, or in addition, dimension  7910  could be chosen so as to correspond to dimension  7920  so as to simplify the design and the manufacturing. 
         [0122]    Alternatively, or in addition, assuming the M 1800  is larger than M 1900 , dimensions  7810 ,  7910 ,  7920  could be chosen so as to correspond to dimension  7820 , so as to further simplify the design process. 
         [0123]    By realizing the semiconductor system  7000  as described above, conductive region  2220 A of the first semiconductor substrate  1000  and conductive region  2220 B of the second semiconductor substrate  1700  would overlap at least partially and conductive region  2220 B would only overlap a region including conductive region  2220 A and the diffusion barrier  2211 A of the first semiconductor substrate  1000 . In such a manner, diffusion of the conductive element of and conductive region  2220 B into the first semiconductor substrate  1000  could be prevented. 
         [0124]    Although in some of the previous embodiments, reference has been made to the process for realizing, and the dimensions of, the connecting structure of the first semiconductor substrate  1000  only, the same teaching could, of course, be applied to the second semiconductor substrate  1700  as well. 
         [0125]    In some embodiments of the present invention, the semiconductor substrate integrating the connecting structure, such as, for instance, semiconductor substrates  1000 ,  1700 ,  2000 E,  4000 E,  5000 D,  6000 F, including, for instance, connecting structures  100 ,  1201 ,  1202 ,  4200 ,  5200 ,  6200 , could undergo a layer transfer process of transferring a layer structure along a plane substantially parallel to the surface containing direction  1900  and perpendicular to direction  1800 . The transfer process could be performed by implantation of the substrate by means of ions to form a predetermined weakening layer inside, and could include a step of heating of the substrate so as to detach the to be transferred layer along the weakening layer in which ions have been implanted. Detachment can also be realized by a mechanical action. Alternatively, the transfer process could be performed by grinding and/or etching the material in excess of the transferred layer. The transfer process could be carried out before the realization of the connecting structure, or after. Moreover, the transfer process could be carried out before the 3D integration process, or after. 
         [0126]    In some embodiments of the present invention, the semiconductor substrate integrating the connecting structure, such as, for instance, semiconductor substrates  1000 ,  1700 ,  2000 E,  4000 E,  5000 D,  6000 F, could be any kind of semiconductor wafer, such as, for instance, a Silicon (Si) wafer, a Gallium Arsenide (GaAs) wafer, a Silicon on Insulator (SOI) wafer, a Germanium (Ge) wafer. 
         [0127]    The invention has been presented in the context of two substrates undergoing a process of 3D integration. The term substrate may correspond to a semiconductor wafer, as for example a 200 mm or 300 mm silicon or SOI wafer. It may also correspond to a die, i.e., a piece of a wafer after it has been diced into individual components. In other terms, the inventive concept is applicable to 3D integration performed at the wafer or at the die level. 
         [0128]    In the above description, the terms growing, depositing, realizing are used interchangeably to indicate known techniques in the field of semiconductor manufacturing such as, for instance, any of Chemical Vapour Deposition (CVD), Epitaxy, Physical Vapour Deposition (PVD), Sputter deposition, printing techniques.