Abstract:
Systems and techniques for converting an analog input signal to a digital code are described. A system includes a differential stage to produce a sign bit indicative of a sign of the analog input signal and to generate a first analog signal that is approximately equal to an absolute value of the analog input signal. The system also includes an analog-to-digital converter (ADC) to convert the first analog signal to a second digital code representing a magnitude of the analog input signal and a controller to combine the second digital code and the sign bit to produce a first digital code.

Description:
TECHNICAL FIELD  
       [0001]     This patent application relates to improving the performance of an analog-to-digital converter, and more particularly to improving its accuracy and dynamic range.  
       BACKGROUND  
       [0002]     A bipolar analog-to-digital converter (ADC) converts an analog input signal to a digital output code that can represent both positive and negative values. Although there are different ways to represent a negative number as a digital code, most representations use the most significant bit (MSB) of the code to signify whether the represented value is positive or negative. The MSB is sometimes referred to as a “sign bit”. Examples of binary representations of negative numbers include a one&#39;s complement representation and a two&#39;s complement representation.  
         [0003]     The transfer function of an ADC is a plot of the code generated at the ADC output as function of the input signal value. Such a plot is not continuous but is a plot of 2 N  steps, where N the number of bits in the digital output. For an ideal ADC, a single straight line can be drawn through the points at each code-transition boundary, beginning at the origin of the plot.  
         [0004]      FIG. 1  shows a plot  2  of an ideal transfer function  4  for a 3-bit ADC with reference points at code transition boundaries. The ADC in this example produces a total of eight steps that each represents a value of the analog input signal as a two&#39;s complement binary code. In this case, the MSB (i.e., the first bit of each code) signifies whether the code represents a negative or a positive value. For example, all of the digital codes having an MSB equal to “1” represent negative values, and all of the digital codes having an MSB equal to “0” represent either a positive value or zero. The transition occurs at one code width, which is equal to a least significant bit (LSB). The actual value of an LSB is equal to V ref /2 (N−1) , where V ref  is the reference voltage that determines the full-scale range of the ADC (i.e., the range of analog input values that ADC can convert to digital values). The resolution of the ADC, which determines the best accuracy to which the ADC can represent an analog input value, is equal to the value of the LSB. In the example shown in  FIG. 1 , the resolution is V ref /4.  
       SUMMARY  
       [0005]     The invention provides methods and systems, including computer program products, for converting an analog input signal to a digital code.  
         [0006]     In general, in one aspect, the invention features a system that includes a differential stage to produce a sign bit indicative of a sign of the analog input signal and to generate a first analog signal that is approximately equal to an absolute value of the analog input signal. The system also includes an analog-to-digital converter (ADC) to convert the first analog signal to a second digital code representing a magnitude of the analog input signal and a controller to combine the second digital code and the sign bit to produce a first digital code.  
         [0007]     In general, in another aspect, the invention features a method for converting an analog input signal to a first digital code. Using a differential stage, a sign bit indicative of the sign of the analog input signal is produced and a first analog signal that is approximately equal to the absolute value of the analog input signal is generated. Using an analog-to-digital converter (ADC) the first analog signal is converted to a second digital code representing the magnitude of the analog input signal. Using a controller coupled to the differential stage and the ADC, the second digital code and the sign bit are combined to produce the first digital code.  
         [0008]     Embodiments may include one or more of the following. The sign bit may be a most significant bit of the first digital code, and the first digital code can represent both positive and negative values of the analog input signal. For example, the first digital code may be one of a one&#39;s complement representation and a two&#39;s complement representation. A voltage buffer coupled between the differential stage and the ADC, in which the voltage buffer is configured to provide an output impedance that is less than an input impedance of the ADC, may be provided.  
         [0009]     The differential stage may include a differential pair that includes a first transistor and a second transistor. A first applied voltage that is substantially equal to the analog input signal may be applied to the base of the first transistor and a second applied voltage that is substantially equal in magnitude and opposite in sign to the analog input signal may be applied to the base of the second transistor. The collectors of the first and second transistor may be configured to conduct current when the first and second applied voltage are greater than a threshold voltage (e.g., zero) and the sum of currents conducted by the collectors of the first and second transistors is constant. The differential stage may also include a differential to single-ended converter to select a value of the sign bit in response to detecting a current flowing through one of the collectors of the first and second transistors. For example, the differential to single-ended converter may be configured to select the value of the sign bit to indicate that the analog input signal is positive in response to detecting a current flowing through the collector of the first transistor and select the value of the sign bit to indicate that the analog input signal is negative in response to detecting a current flowing through the collector of the second transistor.  
         [0010]     The emitters of the first and second transistor may produce voltages that follow the first and second applied voltages, respectively, when the collectors of the first and second transistor conduct current. The emitters of the first and second transistors may also be connected at a node that carries the first analog signal that is approximately equal to the absolute value of the analog input signal and that includes voltages produced at the emitters of the first and second transistors. A current source (e.g., a current mirror) may be coupled to the emitters of the first and second transistors.  
         [0011]     Third and fourth transistors configured to reduce a Miller effect of a parasitic capacitance between the base and the collector of the first and second transistors, respectively, may be provided. For example, the third and fourth transistors may receive fixed voltages at their bases, and their collectors may be coupled to a voltage supply. The emitter of the third transistor may be connected to the collector of the first transistor, and the emitter of the fourth transistor may be connected to the collector of the second transistor.  
         [0012]     The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 
     
    
     DESCRIPTION OF DRAWINGS  
       [0013]      FIG. 1  shows a plot of an ideal transfer function of an analog-to-digital converter (ADC) that represents negative and positive values as two&#39;s complement binary codes;  FIG. 2  shows a schematic diagram of a composite ADC that includes an external differential stage for providing a sign bit;  
         [0014]      FIG. 3  shows a plot of waveform generated at an output of the external differential stage shown in  FIG. 2 ;  
         [0015]      FIG. 4  shows a plot of an exemplary ideal transfer function of the composite ADC shown in  FIG. 2 ; and  
         [0016]      FIG. 5  shows another exemplary ideal transfer function of the composite ADC shown in  FIG. 2 . 
     
    
     DETAILED DESCRIPTION  
       [0017]     Testing equipment for characterizing the performance of various electronic devices often includes one or more ADCs. For testing some state-of-the-art devices, the best available ADCs at the time the testing equipment is designed may not have sufficient resolution and dynamic range. Replacing the ADCs with those having improved resolution and dynamic range may be prohibitively expensive and/or require modifications to other parts of the testing equipment.  
         [0018]      FIG. 2  shows a composite ADC  10  that can improve resolution and dynamic range of an N-bit ADC  14  by adding an extra bit to the output of an existing ADC  14  to produce an overall output having N+1 bits. In addition to the ADC  14 , the composite ADC  10  includes an external differential stage  12  coupled to the ADC  14 , and a processor  26  coupled to the ADC  14  and the differential stage  12 . A differential to single-ended converter  32  within the differential stage  12  produces a sign bit indicative of the sign of an analog input signal received at an input pin  30   a . The input pin  30   a  is connected to the positive terminal of an analog voltage source and the input pin  30   b  is connected to the negative terminal of the source and therefore receives a negated version of the analog input signal. At output pins  34   a - b , the differential stage  12  produces an analog signal that is equal to the absolute value of the analog input signal. This signal is received from output pin  34   a  by the ADC  14 , which in turn converts the absolute value to a digital code. The processor  26  then combines the sign bit generated by the differential to single-ended converter  32  and the digital code produced by the ADC  14  to yield an overall N+1-bit output code that represents the analog input. The sign bit is the MSB of the overall output code. The overall output code may conform to any format that can represent both negative and positive values. Examples of formats include one&#39;s complement and two&#39;s complement representations. As will be discussed in more detail below, because the ADC  14  converts only positive analog values, the codes that a conventional ADC would have used to represent negative numbers are used by the ADC  14  to represent positive values. As a result, the resolution of the composite ADC  10  is doubled without reducing its dynamic range below that of the conventional ADC. Alternatively, the dynamic range of the ADC  14  can be half of that of a conventional ADC yet the composite ADC  10  will still exhibit the same dynamic range as the conventional ADC because the differential stage  12  supplies an extra bit.  
         [0019]     In addition to the input pins  30   a - b , to the differential to single-ended converter  32 , and to the output pins  34   a - b , the differential stage  12  includes a differential pair  16  that extracts the sign of the input analog signal; voltage followers  18 ,  20 , and  22 ; multiple current sources  28   a - d  (referred to collectively as “current sources  28 ”), a dc power supply  38 , and ground pins  36  connected to ground. All of the transistors shown in  FIG. 2  are bipolar-junction transistors (BJTs). It is possible to replace the BJTs in this application by field effect transistors (FET).  
         [0020]     The differential pair  16  has two functions: it extracts the sign of the analog input signal  40  and produces the absolute value of the analog input  40  as an input to the ADC  14 . It includes a pair of telescopic cascodes. The first telescopic cascode includes two npn transistors T 1  and T 3  and a resistor R 1 , and the second telescopic cascode includes two npn bipolar transistors T 2  and T 4  and a resistor R 2 . The input pins  30   a  and  30   b  are connected to opposite polarities of an analog voltage source and to the respective bases of transistors T 1  and T 2 . The positive polarity of the analog source  40 , which generates the analog input signal, is received at the base of transistor T 1  and the negative polarity of the source, which generates a signal that is equal in magnitude but opposite in sign to the analog input signal, is received at the base of transistor T 2 . The voltages at the bases of transistors T 3  and T 4  are fixed to a DC bias circuit (not shown) that are derived from the dc power supply  38 .  
         [0021]     The circuit that includes transistors T 1  and T 2  is a trans-impedance linear amplifier. So the current will change smoothly. When the input voltage varies, the base current of both transistors T 1  and T 2  vary. The base current variation is proportional to voltage variation. As a result, the collector currents of the transistors T 1  and T 2  will also vary proportionally to the input voltage variation. The output current variation is β times the input current variation. Therefore, the voltage gain is β times the ratio of the load impedance to the input impedance. The sum of the two collector currents is almost constant due to the current source. The differential to single-ended converter thus also acts as an amplifier.  
         [0022]     When the total gain is high enough and the output of either transistors T 1  and T 2  is saturated, the differential pair  16  could be approximate to a sign detector. At values greater than zero, the analog input signal received at the base of transistor T 1  is large enough to cause the voltage between the base and emitter of the transistor T 1  to exceed a threshold voltage, causing current to flow through the collector of the transistor T 1 . A positive analog input value causes a negative voltage to be applied to the base of the transistor T 2 . When the input voltage to transistor T 2  falls below the threshold voltage, the transistor T 2  is in the cutoff mode, and no current flows through the transistor T 2  or through the transistor T 4 . If, however, the analog input value is negative, the transistor T 1  is in the cutoff mode (i.e., no current flows through the transistors T 1  and T 3 ), and a positive voltage is applied to the base of the transistor T 2 . If the positive voltage exceeds the threshold voltage of the transistor T 2 , a current flows through the collectors of the transistors T 2  and T 4 . At any given time, the current flowing through the transistors T 1  and T 3  may be larger than that flowing through the transistors T 2  and T 4  or vice versa. Thus a flow of current through the transistors T 1  and T 3  that is greater than a flow of current through the transistors T 2  and T 4  indicates a positive analog input voltage, and a flow of current through the transistors T 2  and T 4  that is greater than a flow of current through the transistors T 1  and T 3  indicates a negative analog input voltage. The differential to single-ended comparator  32  determines whether more current is flowing through transistors T 1  and T 3  or through the transistors T 2  and T 4  and selects the value of the sign bit to be either “1” or “0” based on the determination. For example, if the differential to single-ended converter detects more current flowing through the transistors T 1  and T 3 , it produces a sign bit of “0” to signify that the analog input is positive. Conversely, if the differential to single-ended comparator  32  detects more current flowing through the transistors T 2  and T 4 , it produces a sign bit equal to “1” to signify that the analog input is negative. In some embodiments, the differential to single-ended comparator  32  determines whether a voltage drop has occurred across the resistor R 1  (caused by current flowing through transistors T 1  and T 3 ) or across the resistor R 2  (caused by current flowing through transistors T 2  and T 4 ). In some embodiments, the differential to single-ended comparator  32  produces a sign bit of “0” to represent a negative analog input and a sign bit of “1” to represent a positive analog input.  
         [0023]     The magnitude of the analog input is controlled at output pin  34   a  by the  10  transistors T 1  and T 2  and at output pin  34   b  by the transistors T 5  and T 6 . The transistors T 7  and T 8  buffer the signals before they are transmitted through the output pins  34   a  and  34   b . The signals produced at the output pins  34   a  and  34   b  are complementary signals that are out of phase by 180 degrees. The transistors T 1 , T 2 , T 5 , and T 6  are each arranged in a configuration referred to as an “emitter follower” configuration. In an emitter follower configuration, the input signal is applied to the base and the output signal is taken from the emitter. The ratio of the voltage at the emitter to the voltage at the base closely approaches unity, which means that the signal at the emitter closely follows that at the base. The process by which the magnitude of the analog input is generated by the transistors T 1  and T 2  at the output pin  34   a  and by the transistors T 5  and T 6  at the output pin  34   b  is described in further detail with respect to  FIG. 3 .  
         [0024]     The transistors T 1  and T 2  are biased with a constant-current source  28   b  having a high output impedance. An optional resistor R 3  is provided to introduce a DC offset if needed. The value of R 3  is usually small compared with the current source so the signal loss is negligible. The collector currents of the transistors T 1  and T 2  are received at the emitters of T 3  and T 4 , respectively. The current at each of the collectors of the transistors T 1  and T 2  are approximately equal to the current at each of their respective bases multiplied by a gain factor β which is approximately between 100 and 300. The load resistances seen by the transistors T 1  and T 2  are the input resistances at the emitters of transistors T 3  and T 4 . The low load resistance seen by the transistors T 1  and T 2  considerably reduces the Miller effect (also referred to as the Muller effect) of parasitic capacitances between their bases and collectors. The Miller effect is defined below.  
         [0025]     The following discusses in further detail how the transistors T 3  and T 4  reduce the Miller effect in the transistors T 1  and T 2 . If, for example, the transistor T 3  were omitted from the differential pair  16 , the collector of the transistor T 1  would be connected directly to the resistor R 1 . When the voltage at the base of the transistor T 1  increases, the current through the base is amplified in proportion to the base current by gain factor β, as discussed above. As the collector current through the transistor T 1  increases with the base current, the voltage drop across the resistor R 1 , which is equal to the collector current multiplied by the resistance value of R 1 , also increases. Because there is a parasitic capacitance between the collector and base of the transistor T 1 , a change in voltage across the resistor R 1  causes the voltage at the base of the transistor T 1  to change as well. Namely, a drop in voltage across the resistor R 1  causes the voltage at the base of the transistor T 1  to drop. Because the voltages at either side of the parasitic capacitance are in a ratio approximately equal to the gain factor β, the parasitic capacitance is effectively increased by the gain factor β as well. This phenomena is referred to as the Miller effect. Higher signal frequencies increase the effect of the parasitic capacitance, causing an effective short circuit between the base and the collector. This in turn degrades the accuracy with which the emitter voltage of transistor T 1  follows the base voltage, which ultimately leads to poor performance of the differential pair  16 . Similarly, if transistor T 4  were omitted from the differential pair  16 , the performance of transistor T 2  at high frequencies would be impaired due to the Miller effect.  
         [0026]     The addition of the transistor T 3  between the transistor T 1  and the resistor R 1 , and, similarly, the addition of the transistor T 4  between the transistor T 2  and the resistor R 2  prevents a voltage drop across the resistors R 1  and R 2  from affecting the base voltages of the transistors T 1  and T 2 , respectively. Because the base voltages of the transistors T 3  and T 4  are fixed, neither of those transistors experiences the Miller effect. The transistors T 3  and T 4  essentially act as current buffers that isolate the voltage changes across the resistors R 1  and R 2 . The transistors T 3  and T 4  pass the signal current to the differential to single-ended comparator  32 , while presenting low load resistances to the amplifying transistors T 1  and T 2 . The collectors of the transistors T 3  and T 4  carry currents that are almost equal to the currents at the collectors of the transistors T 1  and T 2 , respectively.  
         [0027]     The voltage followers  18  and  20  are coupled, respectively, to the output pins  34   a  and  34   b . The signals produced at the output pints  34   a  and  34   b  are complementary signals that are out of phase by 180 degrees. Voltage followers  18  and  20  are implemented by the transistors T 8  and T 7 , respectively, both arranged in an emitter-follower configuration. These two transistors provide a differential output if both are used or a single-ended output if one of them is used. Although the transistor T 8  is pnp and the transistor T 7  is npn, their functions are essentially the same. The voltage followers  18  and  20  exhibit a voltage gain that is smaller but close to unity, a high input resistance, and a low output resistance. The voltage followers  18  and  20  are included as the last stages of the differential stage  12  to provide a low output resistance. A low output impedance enables sufficient current to be provided to the ADC  14 , also referred to as the “load”.  
         [0028]     The current sources  28  may be implemented using a variety of known circuits that include, for example, BJT transistors, MOS (metal-oxide semiconductor) transistors, operational amplifiers, diodes, and resistors. Examples of circuits for implementing the current sources  28  may include, but are not limited to, basic current mirrors, cascode current mirrors, Wilson current mirrors, and any combination thereof.  
         [0029]      FIG. 3  shows plots  50   a - d  of the signals produced at key points in the differential stage  12 . Plots  50   b - c  shows the signals at the emitters of the transistors T 1  and T 2  given a sinusoidal analog input shown in the plot  50   a . The plot  50   d  shows the signal at the output pins  34   a - b  that is received by the ADC  14 .  
         [0030]     As seen in the plots  50   a - c , when the analog input voltage is positive, the voltage at the emitter of the transistor T 1  (labeled V E1  in  FIG. 3 ) follows the voltage applied to its base (i.e., the analog input voltage a signal level greater than a predetermined threshold over V i ). The transistor T 2 , however, is in the cutoff mode when the input voltage is positive, and therefore the voltage at the emitter of transistor T 2  (labeled V E2  in  FIG. 3 ) is zero. Conversely, when the analog input voltage is negative, a voltage that is equal and opposite to the analog input voltage is applied to the base of the transistor T 2 , and the voltage V E2  follows that voltage. The transistor T 1  is in the cutoff mode when the analog input voltage is negative, and thus the voltage V E1  is zero. As the input signal switches between positive and negative voltages, the transistors T 1  and T 2  switch between active and cutoff modes such that the transistor T 1  is in the active mode when the transistor T 2  is in cutoff and vice versa. Voltage change is performed quickly without interfering with base voltages at the transistors T 1  and T 2 . As soon as the input voltage changes from positive to negative, or vice versa, the voltages at the emitters of the transistors T 1  and T 2  change quickly due to the current source  28   b . Because the emitters of the transistors T 1  and T 2  are tied together, the currents flowing through the transistors T 1  and T 2  share the same path. Therefore, the signal received by the ADC  14 , after passing through the voltage buffer  18 , is equal to the sum of the voltages V E1  and V E2 . A comparison of the plots  50   a  and  50   d  reveals that the input to the ADC  14  (labeled “V at pins  34   a - b ” in  FIG. 3 ) is approximately equal to the absolute value of the input voltage.  
         [0031]     The transistors T 5  and T 6  of voltage buffer stage  22  are essentially the same as the transistors T 1  and T 2  except that because they are pnp, rather than npn. Therefore, the voltage polarities and current flow of the transistors T 5  and T 6  in the active mode are the reverse of that for the transistors T 1  and T 2 . Similar to the resistor R 3 , the resistor R 4  may optionally be used to increase the input resistance of the transistors T 5  and T 6  and to adjust the overall voltage gain between the collector and the base of each of the transistors T 5  and T 6 . The signals produced at the emitters of the transistors T 5  and T 6  in relation to a sinusoidal input voltages are essentially the same as those shown in plots  50   b  and  50   c  in relation to transistors T 1  and T 2 . Furthermore, the signal produced at output pin  34   b , after passing though the voltage buffer  20  is approximately equal to the absolute value of the input voltage and exhibits a waveform akin to that shown in plot  50   d , except for that it is out of phase by 180 degrees.  
         [0032]      FIG. 4  shows a plot  60  of an ideal transfer function  62  of the composite ADC  10  that has the same dynamic range and resolution of a conventional ADC whose ideal transfer function  4  is shown in  FIG. 1 . Because the differential stage  12  provides the sign bit, the dynamic range of the ADC  14  can be half of that of the conventional ADC yet the composite ADC  10  will still exhibit the same dynamic range as that of the conventional ADC. In the example shown in  FIG. 4 , the code width of ADC  14  has been reduced from three bits to two bits.  
         [0033]      FIG. 5  shows a plot  70  of an ideal transfer function  72  of the composite ADC  10  having a dynamic range that is the same as that of a conventional ADC whose ideal transfer function  4  is shown in  FIG. 1 . However, the composite ADC  10  has twice the resolution of the conventional ADC. The code-width of the ADC  14  is the same as that of the conventional ADC, but because the ADC  14  converts only positive values, the codes that the conventional ADC uses to represent negative numbers can now be used in the ADC  14  to improve the resolution with which it represents positive values. In the example shown in  FIG. 5 , the resolution of the composite ADC  10  is V ref /8, which is twice that of the conventional ADC, which has a resolution of V ref /4 (see  FIG. 1 ).  
         [0034]     The circuitry described herein, including the differential pair  16 , the voltage followers  22 ,  18 , and  20 , the ADC  14 , differential to single-ended comparator  32 , processor  26 , and/or portions thereof, may be implemented as part of composite ADC  10  or as separate circuitry for use in conjunction with composite ADC  10 .  
         [0035]     A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, another differential stage, similar to the differential stage  12  could be coupled to the input ADC  10 , which includes the differential stage  12  coupled to the input of ADC  14 . Similarly, any number of differential stages  12  could be cascaded together and coupled to the input of the ADC  10 . The ADC  10  could have a unipolar output or bipolar outputs.  
         [0036]     In some embodiments, some or all of the BJT transistors could be replaced with metal-oxide-semiconductor (MOS) transistors or other types of transistors. Any number of bypass capacitors and other biasing circuitry could be included in the differential stage  12 . The transistors T 1  and T 3  could be arranged in a folded cascade configuration. Likewise, transistors T 2  and T 4  could be arranged in a folded cascade configuration. One or more of the resistors R 1 , R 2 , R 3 , and R 4  could be replaced with transistors configured to operate as resistors.  
         [0037]     The conversion process performed by the composite ADC  10  is not limited to use with the hardware described herein. The conversion process can be implemented, at least in part, in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations thereof.  
         [0038]     The conversion process can be implemented, at least in part, via a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device or in a propagated signal, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.  
         [0039]     Method steps associated with implementing the conversion process can be performed by one or more programmable processors executing one or more computer programs to perform the functions of the processes. All or part of the conversion process can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) and/or an ASIC (application-specific integrated circuit).  
         [0040]     Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer include a processor for executing instructions and one or more memory devices for storing instructions and data.  
         [0041]     Accordingly, other embodiments are within the scope of the following claims.