Abstract:
A circuit that includes a data input circuit for outputting data in response to a first signal, a logic circuit for generating a second signal in response to the first signal, a latch circuit for latching the data in response to the second signal, and a decoder for decoding an output signal of the latch circuit and for generating a code. A method includes outputting a mode register set (MRS) code based upon data received by a circuit implemented in a semiconductor device, where the data is unrelated to register data.

Description:
[0001]    This application claims priority of Korean Patent Application No. 02-64251, filed Oct. 10, 2002, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention generally relates to a semiconductor memory device, and more particularly, to a circuit and a method for generating a mode register set (MRS) code in a synchronous semiconductor memory device.  
           [0004]    2. Description of the Related Art  
           [0005]    A mode register and a mode register set (MRS) may be used in a synchronous semiconductor memory device. The mode register may program and store data for controlling various operational modes of a synchronous semiconductor memory device.  
           [0006]    In a conventional memory device, operational modes and/or characteristics of a semiconductor memory device may be dictated by input signals. However, in a synchronous semiconductor memory device, an operational mode, i.e., a column address strobe (CAS) latency mode or a burst length mode, is normally determined beforehand, and thereafter the semiconductor memory device may be accessed. The operation mode is typically set and stored in the mode register as units of bits, and a group of such mode registers may be referred to as the MRS. Therefore, a series of codes indicating a mode of the semiconductor memory device may be set in the mode register set. These codes are often referred to as the MRS codes.  
           [0007]    Conventionally, the MRS codes may be generated by combining addresses. The operation mode of the semiconductor memory device may be determined according to the generated MRS codes. The MRS codes are typically standard Joint Electron Device Engineering Council (JEDEC) codes.  
           [0008]    An MRS code used to test a semiconductor memory device during design of the semiconductor memory device may be referred to as a test MRS code. The test MRS codes may be generated by combining addresses. However, test MRS codes are not standardized MRS codes; therefore, they are normally generated by combining certain addresses, while excluding other addresses. Accordingly, a limited number of test MRS codes may be generated.  
         SUMMARY OF THE INVENTION  
         [0009]    An exemplary embodiment of the present invention may provides an MRS code generating circuit capable of generating various test MRS codes. The test MRS codes may be generated without excluding certain address.  
           [0010]    An exemplary embodiment of the present invention may provides a method of generating various test MRS codes. The test MRS codes may be generated without excluding certain address.  
           [0011]    Moreover, an exemplary embodiment of the present invention provides a circuit that includes a data input circuit for outputting data in response to a first signal, a logic circuit for generating a second signal in response to the first signal, a latch circuit for latching the data in response to the second signal, and a decoder for decoding an output signal of the latch circuit and for generating a code.  
           [0012]    Yet another exemplary embodiment of the present invention provides a method for generating a code that includes outputting data in response to a first signal, generating a second signal in response to the first synchronizing signal, latching the data in response to the second signal, and decoding the latched data and generating the code.  
           [0013]    Moreover, another exemplary embodiment of the present invention provides a circuit that includes a device for outputting a mode register set (MRS) code based on data received by the circuit, where the data is unrelated to register data.  
           [0014]    Another exemplary embodiment of the present invention provides a method that includes outputting a mode register set (MRS) code based upon data received by a circuit implemented in a semiconductor device, where the data is unrelated to register data.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    Exemplary embodiments of the present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:  
         [0016]    [0016]FIG. 1 illustrates an MRS code generating circuit of a semiconductor memory device according to an exemplary embodiment of the present invention;  
         [0017]    [0017]FIG. 2 illustrates a data input circuit of FIG. 1.  
         [0018]    [0018]FIG. 3 illustrates a logic circuit of FIG. 1.  
         [0019]    [0019]FIG. 4 illustrates a timing diagram showing waveforms at each node in the logic circuit of FIG. 3.  
         [0020]    [0020]FIG. 5 illustrates a timing diagram providing an operational example of the MRS code generating circuit of FIG. 1. 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0021]    Exemplary embodiments of the present invention now will be described more fully with reference to the accompanying drawings. In the drawings, like reference numerals are used to refer to like elements throughout.  
         [0022]    [0022]FIG. 1 illustrates an MRS code generating circuit of a semiconductor memory device according to an exemplary embodiment of the present invention. An MRS code generating circuit  100  of FIG. 1 may include a data input circuit  110 , a logic circuit  120 , a latch circuit  130  and a decoder  140 .  
         [0023]    The data input circuit  110  may receive data DATA and may output the input data DATA in response to a first synchronizing signal MRS_COMP. The logic circuit  120  may generate a second synchronizing signal MRS_PULSE capable of latching an output signal of the data input circuit  110  in response to the first synchronizing signal MRS_COMP.  
         [0024]    The latch circuit  130  may receive an output signal of the data input circuit  110  and is capable of latching the output signal of the data input circuit  110  in response to the second synchronizing signal MRS_PULSE. The decoder  140  may receive an output signal of the latch circuit  130 . The decoder  140  is capable of decoding the output signal of the latch circuit  130  and generating an MRS code of the semiconductor memory device.  
         [0025]    [0025]FIG. 2 illustrates the data input circuit  110  of FIG. 1. The data input circuit  110  shown in FIG. 2 may include a NAND gate  210  and an inversion circuit  220 . The NAND gate  210  may receive the data DATA and the first synchronizing signal MRS_COMP. The NAND gate  210  may perform a NAND operation on the input signals and output a resultant NAND signal. The inversion circuit  220  may receive the output signal of the NAND gate  210 , invert the output signal of the NAND gate  210 , and is capable of inverting the output signal as an output signal OUT.  
         [0026]    [0026]FIG. 3 illustrates the logic circuit  120  of FIG. 1. The logic circuit  120  shown in FIG. 3 may include a plurality of inversion circuits  31 ,  32 ,  33 ,  34 ,  35 ,  36 ,  37 ,  38 ,  40 ,  41  and a NOR gate  39 .  
         [0027]    The inversion circuit  31  may receive the first synchronous signal MRS_COMP, invert the first synchronous signal MRS_COMP and is capable of outputting an inverted first synchronous signal MRS_COMP as an output signal MRS_PULSE. The inversion circuits  32 ,  33 ,  34 ,  35 ,  36 ,  37 ,  38  may be connected in series, and the output node N 2  of the inversion circuit  38  may be connected to an input node of the NOR gate  39 . The NOR gate  39  is capable of receiving an output signal of the inversion circuit  31  and an output signal of the inversion circuit  38 . In such a case, the NOR gate  39  is capable of performing a NOR operation on the signals received thereby. The inversion circuit  40  may receive the output signal of the NOR gate  39 , and is capable of outputting an inverted signal thereof. The inversion circuit  41  may receive the output signal of the inversion circuit  40 , and is capable of outputting an inverted signal thereof. As was indicated, the logic circuit  120  is capable of outputting the output signal MRS_PULSE.  
         [0028]    [0028]FIG. 4 illustrates a timing diagram showing waveforms at each node in the logic circuit  120  of FIG. 3. As is illustrated, in one exemplary embodiment of the present invention, if a waveform of the first synchronizing signal MRS_COMP is at a logic low level, a signal at a node N 1  is at a logic high level. Conversely, if a waveform of the first synchronizing signal MRS_COMP is at a logic high level, a signal at the node N 1  is at a logic low level. The signals observed at the node N 1  are output from the inversion circuit  31 . In addition, as is illustrated in FIG. 4, a waveform at a node N 2  may be generated by inverting a waveform at the node N 1 . As is illustrated, a signal at the node N 2  is delayed by an amount of time. This delay is caused by the inversion circuits  32 ,  33 ,  34 ,  35 ,  36 ,  37 ,  38 .  
         [0029]    The number of inversion circuits in FIG. 4 is shown by way of example only. If a greater delay is desired, then a number of inversion circuits may be increased. Alternatively, if less delay is desired, the number of inversion circuits may be decreased.  
         [0030]    In order to generate the second synchronizing signal MRS_PULSE, it may be beneficial if a number of the inversion circuits between the nodes N 1  and N 2  is an odd number.  
         [0031]    An inverted signal of the first synchronizing signal MRS_COMP may be output to the first node N 1 . The signal at the first node N 1  may be inverted and delayed by way of the various inversion circuits  32 - 38 . An output of the various inversion circuits  32 - 38  is received at the second node N 2 . The third node N 3  receives the output of the inversion circuit  41 , which is illustrated in FIG. 4 as the second synchronizing signal MRS_PULSE.  
         [0032]    [0032]FIG. 5 illustrates a timing diagram providing an operational example of the MRS code generating circuit of FIG. 1. Hereinafter, the operation of the MRS code generating circuit  100  according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 through 5.  
         [0033]    Data DATA may be input to the data input circuit  110  in response to a data read command, for example, of a semiconductor memory device. In one exemplary embodiment of the present invention, data of  1111  are input to the data input circuit  110 . Partly in response to the input data, an MRS enable signal MRS_ENB capable of activating an MRS mode is produced. The MRS enable signal may cause the generation of the first synchronizing signal MRS_COMP. The MRS mode may represent a mode for generating an MRS code in the semiconductor memory device. The MRS mode may be enabled by the MRS enable signal MRS_ENB.  
         [0034]    The data input circuit  110  may receive the data DATA and output the data DATA in response to the first synchronizing signal MRS_COMP, which is activateable in response to the MRS enable signal MRS_ENB. An output signal of the data input circuit  110  may be received by the latch circuit  120 .  
         [0035]    In response to the first synchronizing signal MRS_COMP, the logic circuit  120  may generate the second synchronizing signal MRS_PULSE for latching the output signal of the data input circuit  110 . The latch circuit  130  may receive the output signal OUT of the data input circuit  110  and latch the output signal of the data input circuit  110  in response to the second synchronizing signal MRS_PULSE. The output signal OUT of the data input circuit  110  may be latched when the second synchronizing signal MRS_PULSE is at a logic level high. An example of when the second synchronizing signal MRS_PULSE is at a logic high is illustrated in FIG. 5.  
         [0036]    The decoder  140  may decode the data latched by the latch circuit  130  and output decoded data. The output signal of the decoder  140  may be the MRS code of the semiconductor memory device. In an exemplary embodiment of the present invention, different MRS codes may be generated in response to the input data DATA; moreover, the input data DATA may be used as the MRS code generated in the decoder  140 .  
         [0037]    In accordance with an exemplary embodiment of the present invention, it is possible to generate a variety of MRS codes, by setting and storing the operation modes of one or more semiconductor memory devices. This may be achieved by generating MRS codes by using inputted data, as described above. For example, if 16 of data streams are inputted in the semiconductor memory device, 2 16 , i.e., 65535 of MRS codes may be generated. In addition, according to an exemplary embodiment of the present invention, a designer of a semiconductor memory device can initiate tests thereon.  
         [0038]    Hereinafter, a method of generating MRS codes according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 through 5. The data input circuit  110  of FIG. 1 may receive the data DATA and output the data DATA in response to the first synchronizing signal MRS_COMP.  
         [0039]    The logic circuit  120  may generate the second synchronizing signal MRS_PULSE for latching the output data in response to the first synchronizing signal MRS_COMP. The latch circuit  130  may latch the output data in response to the second synchronizing signal MRS_PULSE, and the decoder  140  may decode the latched data and generate the MRS code.  
         [0040]    The circuit elements illustrated in FIGS. 2 and 3 are given by way of example only. In particular, those of skill in the art appreciate various other implementations of the data input and logic circuits  110  and  120 , respectively, are also possible. Moreover, those of skill in the art understand the present invention is not limited to hardware implementation. In particular, the exemplary embodiments of the present invention may also be realized in software and implemented as such, or programmed on a hardware device.  
         [0041]    A method of generating the MRS code according to an exemplary embodiment of the present invention may include generating the MRS code by using input data in contrast to a conventional method of generating the MRS code. Therefore, various MRS codes may be generated.  
         [0042]    As described herein, a circuit and a method according to an exemplary embodiment of the present invention provide for the generation of an MRS code using input data. This reduces the need to combine addresses to produce an MRS code. Therefore, according to an exemplary embodiment of the present invention, a wide variety of MRS codes may be generated.  
         [0043]    In addition, during a design process of a semiconductor memory device, a test MRS code may be generated from various MRS codes. Therefore, a semiconductor memory device may be effectively designed by using such a test MRS code.  
         [0044]    While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as defined by the claims.