Abstract:
A card reader with power-saving function is used for being inserted with a memory card so that a computer can access the memory card through the card reader. When the memory card is inserted in the card reader, the card reader is enabled to operate. On the other hand, when the memory card is not inserted in the card reader, the card reader enters to a power-down mode for saving power.

Description:
BACKGROUND OF THE INVENTION  
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a host device, and more particularly, to a host device with power-saving function. 
         [0003]    2. Description of the Prior Art 
         [0004]    Nowadays either desktop computers or laptop computers are equipped with card readers for allowing users to insert memory cards so as to access data. When a memory card is inserted into the card reader, the card reader accesses the data of the memory card according to the commands from the computer. When the memory card is not inserted into the card reader, the conventional card reader still operates. In this way, the card reader still consumes power, causing power wasting. Take the laptop computer as an example, when the power source for the laptop computer is the battery, the efficiency of the power consumption of the laptop computer becomes much more important. However, the conventional card reader cannot save power when the conventional card reader is not inserted with the memory card, causing the reduction of the efficiency of the power consumption of the laptop computer, and consequently the usable time of the laptop computer is reduced as well, which is inconvenient. 
       SUMMARY OF THE INVENTION  
       [0005]    The present invention provides a host device with power-saving function. The host device comprises a first interface for coupling to an external device and accordingly generating a first signal; a second interface for coupling to a corresponding first port of a south bridge chip of a chip set of a host and receiving a second signal transmitted from the south bridge chip; a third interface for coupling to a corresponding second port of the south bridge chip of the chip set of the host; a logic gate coupled to the first interface and the second interface for generating a third signal according to the first signal and the second signal; a physical layer processing device coupled to the third interface and the logic gate for processing signals received on the third interface according to the third signal; a digital logic processing device coupled to the first interface and the logic gate for processing signals received on the first interface according to the third signal; and a controller coupled to the second interface and the logic gate for transmitting a fourth signal to the south bridge chip of the chip set of the host according to the third signal. 
         [0006]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0007]      FIG. 1  is a diagram illustrating a host device with power-saving function according to the present invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0008]    Please refer to  FIG. 1 .  FIG. 1  is a diagram illustrating a host device  100  with power-saving function according to the present invention. The host device  100  can be disposed in a laptop computer or a desktop computer (hereinafter “host”). As shown in  FIG. 1 , in the host, the mother board comprises a host device  100 , a central processing unit CPU, and a chip set  200 . The chip set  200  comprises a south bridge chip SB and a north bridge chip NB. The south bridge chip SB comprises two interfaces P 2  and P 3  for communicating with the devices of the mother board. The interface P 2  can be a general purpose input/output port, or the like. The interface P 3  can be Peripheral Component Interface (PCI), Peripheral Component Interface Express (PCIe), Universal Serial Bus (USB), or any other interface. The host device  100  is coupled to the south bridge chip SB of the chip set  200  and communicates with the central processing unit CPU through the interfaces P 2  and P 3 . The host device  100  is disposed for coupling to an external device  300 . For example, when the host device  100  is a card reader, the external device  300  is accordingly to be a memory card. When the external device  300  is coupled to the host device  100 , the host device  100  provides the central processing unit CPU to access the data stored in the external device  300 . 
         [0009]    The host device  100  comprises three interfaces P 1 , P 2 , and P 3 , a digital logic processing device  110 , a physical layer processing device  120 , a logic gate  130 , and a controller  140 . 
         [0010]    The interface P 1  of the host device  100  is disposed for coupling to the external device  300 . The interface P 2  of the host device  100  is disposed for coupling to the corresponding interface P 2  of the south bridge chip SB. The interface P 3  of the host device  100  is disposed for coupling to the corresponding interface P 3  of the south bridge chip SB. 
         [0011]    The logic gate  130  can be an OR gate, which comprises two input ends  11  and  12 , and an output end O. The two input ends of the logic gate  130  are coupled to the interfaces P 1  and P 2  of the host device  100 , respectively, for receiving the signal S 1  transmitted from the external device  300  and the signal S 2  transmitted from the south bridge chip SB. Thus, the logic gate  130  can execute operation on the signals S 1  and S 2  (OR operation) and output the calculation result as the signal S 3  through the output end O of the logic gate  130 . More particularly, either the south bridge chip SB transmits the signal S 2  through the interface P 2  or the external device  300  couples to the interface P 1  of the host device  100  for transmitting the signal S 1 , the logic gate  130  outputs the signal S 3 . 
         [0012]    The physical layer processing device  120  is coupled to the interface P 3  of the host device  100 , the digital logic processing device  110 , and the output end O of the logic gate  130 . The physical layer processing device  120  processes the signals of the physical layer on the interface P 3  of the south bridge chip SB for allowing the digital logic processing device  110  to execute the following procedures. When the physical layer processing device  120  receives the signal S 3 , the physical layer processing device  120  enables the execution for physical layer signal processing. On the other hand, when the physical layer processing device  120  does not receive the signal S 3 , the physical layer processing device  120  stops the execution for physical layer signal processing, which means the physical layer processing device  120  does not function. In this way, the power consumed by the physical layer processing device  120  can be saved. 
         [0013]    The digital logic processing device  110  is coupled to the interface P 1  of the host device  100 , the physical layer processing device  120 , and the output end O of the logic gate  130 , for processing the logic signals processed by the physical layer processing device  120  and accessing the data of the external device  300 . The digital logic processing device  110  further receives a clock signal CLK for synchronization with the interface P 3  of the south bridge chip SB. When the digital logic processing device  110  receives the signal S 3 , the digital logic processing device  110  starts the operation according to the clock signal CLK. On the other hand, when the digital processing device  110  does not receive the signal S 3 , the digital logic processing device  110  ignores the clock signal CLK and consequently stops the operation of the digital logic processing device  110 . In this way, the power consumed by the digital logic processing device  110  can be saved. According to the equation for power consumption of the digital processing device  110 : W=f×V 2 , wherein W represents the power consumption of the digital processing device  110 , f represents the frequency of the clock signal CLK, and V represents the voltage, it is known that the power consumption of the digital logic processing device  110  relates to the frequency of the received clock signal CLK. Therefore, when the digital logic processing device  110  ignores the clock signal CLK, the power consumption of the digital logic processing device  110  can be reduced to the lowest level. In this way, when the digital logic processing device  110  does not receive the signal S 3 , the power consumption of the digital logic processing device  110  can be reduced. 
         [0014]    The controller  140  is coupled to the output end O of the logic gate  130  and the interface P 2  of the host device  100  for transmitting a signal S 4  to the interface P 2  of the south bridge chip SB according to the signal S 3 . That is, when the host device  100  is activated (the signal S 3  is generated), the controller  140  transmits the signal S 4  to the interface P 2  of the south bridge chip SB for informing the central processing unit CPU that the host device  100  starts to operate; on the other hand, when the host device  100  is not activated (the signal S 3  is not generated), the controller  140  stops transmitting the signal S 4  to the interface P 2  of the south bridge chip SB for informing the central processing unit CPU that the host device  100  is currently in the sleep mode. 
         [0015]    The feature of the host device  100  of the present invention is: when the external device  300  is coupled to the host device  100  (the signal S 1  is generated), the host device  100  of the present invention starts to operate; on the other hand, when the external device  300  is not coupled to the host device  100  of the present invention (the signal S 1  is not generated), the host device  100  enters sleep mode for reducing power consumption (the digital logic processing device  110  stops receiving the clock signal CLK, and the physical layer processing device  120  stops processing the physical layer signals of the interface P 3 ). For example, when the host device  100  is in the operation mode, the power consumption is about 60 milli-amperes; when the host device  100  is in the sleep mode, the power consumption is about 1 milli-ampere, which is reduced greatly. Thus, when the power source of the host is only a battery, the limited power provided by the battery can be efficiently utilized by the host device  100  of the present invention, providing longer useable time for users. 
         [0016]    Furthermore, the central processing unit CPU transmits the signal S 2  to activate the host device  100  through the interface P 2  of the south bridge chip SB. For example, when the power source of the host is an AC/DC converter instead of a batter, which means the power consumption is not an issue, the central processing unit CPU can continuously transmits the signal S 2  through the interface P 2  of the south bridge chip SB to the host device  100  for keeping the host device  100  in the operation mode, which provides greater flexibility to users. 
         [0017]    Additionally, in the present invention, when the signals S 1 , S 2 , S 3 , and S 4  are generated, it means the voltages of the signals S 1 , S 2 , S 3 , and S 4  are at high voltage levels; on the other hand, when the signals S 1 , S 2 , S 3 , and S 4  are not generated, it means the voltages of the signals S 1 , S 2 , S 3 , and S 4  are at low voltage levels. The way of the generating of the signals and the determination for the voltage level in the present invention is only disclosed as an exemplary embodiment while other kinds of designs can be applicable as desired. 
         [0018]    To sum up, the host device of the present invention reduces the power consumption when the external device is not coupled to the host device of the present invention, providing greater convenience. 
         [0019]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.