Abstract:
A display substrate provides more reliable operation comprising a gate driver having groups of stages each connected to one end of each gate conductor of a respective group of gate conductors and groups of sub-gate drivers connected to the other end of the gate conductors of the respective groups of gate conductors, the gate drivers deliver driving signals to one end of the gate conductors of one group while the sub-gate drivers pull the other end of each of the gate conductors of the other group to a predetermined voltage.

Description:
REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority by virtue of Korean Patent Application No. 2006-011757, filed on Feb. 7, 2006 and all the benefits accruing therefrom under 35 U.S.C. §119, the contents of which are hereby incorporated by reference.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to a display substrate and a display device having the same, and more particularly, to a display substrate for improving the reliability of driving the display device.  
       DESCRIPTION OF THE RELATED ART  
       [0003]     Generally, a liquid crystal display (LCD) device includes an LCD panel and a driving device that delivers drive signals to the LCD panel. The LCD panel includes a thin film transistor (TFT) array substrate provided with a plurality of TFTs and a color filter (CF) substrate coupled with the TFT array substrate. The driving device includes a source circuit board, a data driving portion having a data driving chip and a gate driving portion for driving the plurality of gate lines formed in the TFT array substrate. Recently, the gate driving chip has been incorporated into the LCD panel resulting in enhanced productivity and as well as reducing the size of the LCD panel. It would be of great advantage to improve the reliability of the gate driving operation.  
       SUMMARY OF THE INVENTION  
       [0004]     In accordance with the present invention a display substrate includes a gate driver arrangement having greater reliability. The gate driver comprises a plurality of stages electrically connected to one end of the plurality of gate conductors, each of the even-numbered stages providing a gate signal to a corresponding one of the even-numbered gate conductors in response to a first clock signal and each of the odd-numbered stages providing a gate signals to a corresponding one of the odd-numbered gate conductors in response to a second clock signal which, advantageously, may be 180° out of phase with the first clock signal. When the even-numbered stages output their corresponding gate signals, respectively, in response to the second clock signal, each of the odd-numbered sub-gate drivers pulls down the level of the odd-numbered gate conductors, thus assuring that only the desired group of gate conductors are effectively energized and making the driving arrangement more reliable than in the prior art. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     The above and other features and advantage points of the present invention will become more apparent from the ensuing description when read together with the drawing, in which:  
         [0006]      FIG. 1  shows a plane view of a display device in accordance with an exemplary embodiment of the present invention;  
         [0007]      FIG. 2  shows a plane view of a display device in accordance with another exemplary embodiment of the present invention;  
         [0008]      FIG. 3  shows a block diagram illustrating the gate drivers and a sub-gate driver of a thin film transistor (TFT) array substrate of  FIG. 1 ;  
         [0009]      FIG. 4  shows a circuit diagram of one stage among a plurality of stages formed in the gate driver and the sub-gate driver of  FIG. 3 ;  
         [0010]      FIG. 5  shows a timing diagram illustrating an operation of the gate driver and the sub-gate driver of  FIG. 4 ; and  
         [0011]      FIG. 6  shows a timing diagram illustrating an operation of the sub-gate driver of  FIG. 4 . 
     
    
     DESCRIPTION OF THE INVENTION  
       [0012]     Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings. In the drawings, some of the features may be exaggerated or an excessive number of certain features may not be shown for clarity. Like numerals refer to like elements throughout.  
         [0013]      FIG. 1  shows a plane view of a display device in accordance with an exemplary embodiment of the present invention. The display device comprises a display panel  100 , a source circuit board  200 , and a plurality of data drivers  310 ,  320 ,  330 ,  340 ,  350 , and  360 . Display panel  100  comprises a TFT array substrate  110 , a color filter substrate  190 , and a liquid crystal layer (not shown) disposed between TFT array substrate  110  and CF substrate  190 . Substrate  110  has a plurality of gate conductors GL (just one gate conductor shown in  FIG. 1 ) arranged in a first direction and a plurality of source conductors DL (just one source conductor shown in  FIG. 1 ) arranged in a second direction substantially perpendicular to the first direction.  
         [0014]     Substrate  110  further comprises a display area DA and first, second, and third peripheral areas PA 1 , PA 2 , and PA 3  surrounding display area DA. Display area DA has gate conductors GL and source conductors DL intersecting gate conductors GL, and pixel areas P (just one pixel shown in  FIG. 1 ) are defined by gate conductors GL and source conductors DL. Each of pixel areas P comprises a switching element, such as TFT, a pixel electrode, and a storage capacitor CST.  
         [0015]     The first peripheral area PA 1  comprises gate drivers  130  each stage of which is electrically connected to one end of gate conductors GL and delivers a gate signal corresponding to each of gate conductors GL. Gate driver  130  outputs the gate signal to display panel  100  based on a first gate driving signal delivered through a first connecting conductor  140 .  
         [0016]     The second peripheral area PA 2  comprises a sub-gate driver  150  which is electrically connected to the other end of gate conductors GL and pulls down to a predetermined low-level voltage, e.g., 0 volts, the gate signal applied to gate conductors GL. Sub-gate driver  150  pulls gate conductors GL down to the predetermined low-level-voltage the gate signal based on a second gate driving signal delivered through conductor  160 .  
         [0017]     Third peripheral area PA 3  comprises pads (not shown) with a data source driving chip  311  mounted thereon. Data source driving chip  311  is formed on the first, second, third, fourth, fifth, and sixth data drivers, respectively, and outputs a data signal to each of data source conductors DL. In other words, the pads are electrically connected with an output terminal of each of data drivers  310 ,  320 ,  330 ,  340 ,  350 , and  360 .  
         [0018]     Data source circuit board  200  is affixed to one end of display panel  100  and has a driving circuit  210 . Driving circuit  210  outputs a driving signal for operating display panel  100  in response to an external signal externally provided. In other words, driving circuit  210  outputs the first gate driving signal provided to gate driver  130  and the second gate driving signal provided to sub-gate driver  150  to display panel  100 . Further, driving circuit  210  outputs a data signal and a source driving signal to each of data drivers  310 ,  320 ,  330 ,  340 ,  350 , and  360 . Herein, the data signal represents R, G, B image data, for example and the source driving signal generally represents DE (data enable) signal, TP (data load) signal, STH signal, REV (reversal of polarity) signal, etc.  
         [0019]     Data source circuit board  200  comprises a first signal conductor  220 , a second signal conductor  230 , and a signal conductor  240 . Signal conductor  240  electrically connects driving circuit  210  with source driving chip  311  and comprises first, second, third, fourth, fifth, and sixth conductors  241 ,  242 ,  243 ,  244 ,  245 , and  246 .  
         [0020]     First conductor  241  delivers a first data signal and a source driving signal to source driving chip  311  formed on data driver  330 ; the second conductor  242  delivers a second data signal and the source driving signal to the source driving chip  311  formed on data driver  320  through source driving chip  311  formed on data driver  330 ; and third conductor  243  delivers a third data signal and the source driving signal to source driving chip  311  formed on data driver  310  through source driving chips  311  formed on data drivers  320  and  330 . fourth conductor  244  delivers a fourth data signal and the source driving signal to source driving chip  311  formed on data driver  340 ; fifth conductor  245  delivers a fifth data signal and the source driving signal to source driving chip  311  formed on data driver  350  through source driving chip  311  formed on data driver  340 ; and sixth conductor  246  delivers a sixth data signal and the source driving signal to source driving chip  311  formed on data driver  360  through source driving chips  311  formed on data drivers  340  and  350 .  
         [0021]     First signal conductor  220  delivers the first gate driving signal from driving circuit  210  to gate driver  130  through data driver  310 . Second signal conductor  230  delivers the second gate driving signal from driving circuit  210  to sub-gate driver  150  through data driver  360 . Herein, the first gate driving signal comprises a STV signal, a low-level voltage Vss, a first clock signal CK, a second clock signal CKB, for example and the second gate driving signal comprises the low-level voltage Vss, the first clock signal CK, and the second clock signal CKB, for example. It should be noted that data drivers  310 ,  320 ,  330 ,  340 ,  350 , and  360  may be various types of a Tape Carrier Package (TCP), a Chip On Film (COF), and so on, for example.  
         [0022]     A display device according to another exemplary embodiment of the present invention will be now described with reference to  FIG. 2 . which has the same configuration as that of the display device of  FIG. 1 , except that signal conductor  250  is different from the signal conductor  240  of  FIG. 1 . Signal conductor  250  transmits a data signal and a source driving signal provided from the driving circuit  210  to the data drivers  310 ,  320 ,  330 ,  340 ,  350 , and  360  through first and second common conductors  251 ,  252 . In other words, the driving circuit  210  transmits first, second, and third data signal each corresponding to the first, second, and third data drivers  310 ,  320 , and  330  through the first common conductor  251 , and also transmits fourth, fifth, and sixth data signal each corresponding to the fourth, fifth, and sixth data drivers  340 ,  350 , and  360  through the second common conductor  252 . The first and second common conductors  251 ,  252  have a multi-drop structure, which means that the first, second, third, fourth, fifth, and sixth data signals and the source driving signal provided from the driving circuit  210  are sent to each of the data drivers  310 ,  320 ,  330 ,  340 ,  350  and  360  through the first and second common conductors  251 ,  252 . Herein, although the first, second, third, fourth, fifth, and sixth data drivers are described, it should be noted that the data drivers are not limited to the number of the above data drivers but it is just for purpose of description.  
         [0023]     The configuration of the TFT array substrate  100  will be now described in more detail with reference to  FIG. 3  which comprises gate driver  130  and the first connecting conductor  140  formed in the PA 1 , and the sub-gate driver  150  and the second connecting conductor  160  formed in the PA 2 .  
         [0024]     Gate driver  130  comprises first, second, third, . . . , nth stages SRC 1 , SRC 2 , SRC 3 , . . . , SRCn corresponding to a plurality of the gate conductors GL 1 , GL 2 , . . . , GLn, respectively, and a dummy stage SRCd. The first, second, third, . . . , nth stages SRC 1 , SRC 2 , SRC 3 , . . . , SRCn and the dummy stage SRCd are electrically connected to one another. In other words, the second stage SRC 2  has input terminals (e.g. 5 input terminals), and an output terminal. The input terminals of the second stage SRC 2  comprise a first input terminal IN 1  receiving an output signal of a previous stage (i.e. the first stage SRC 1 ), a second input terminal IN 2  receiving an output signal of a next stage (i.e. the third stage SRC 3 ), a second clock terminal CK 2  receiving a first clock signal CK, a first clock terminal CK 1  receiving a second clock signal CKB, and a voltage terminal VSS receiving the low-level voltage Vss (i.e. a ground voltage). The output terminal OUT of the second stage SRC 2  is electrically connected to a second gate conductor GL 2  and delivers the gate signal to the second gate conductor GL 2  formed in the display panel  100 .  
         [0025]     The remaining stages SRC 3 , . . . , SRCn have substantially the same configuration as that of the second stage SRC 2  and thus a detailed description thereof will be omitted to avoid a duplication description.  
         [0026]     Like the second, third, . . . , nth stages SRC 2 , SRC 3 , . . . , SRCn, the first stage SRC 1  has input terminals (e.g. 5 input terminals) and an output terminal. The input terminals of the first stage SRC 1  comprise a first input terminal IN 1  receiving a STV signal, a second input terminal IN 2  receiving an output signal of a next stage (i.e. the second stage SRC 2 ), a second clock terminal CK 2  receiving the second clock signal CKB, a first clock terminal CK 1  receiving the first clock signal CK, and a voltage terminal VSS receiving the low-level voltage Vss (i.e. a ground voltage). The output terminal OUT of the first stage SRC 1  is electrically connected to a first gate conductor GL 1  and delivers the gate signal to the first gate conductor GL 1  formed in the display panel  100 .  
         [0027]     The dummy stage SRCd has input terminals (e.g. 5 input terminals) and an output terminal. The input terminals of the dummy stage SRCd comprise a first input terminal IN 1  receiving an output signal of a previous stage (i.e. the nth stage SRCn), a second input terminal IN 2  receiving the STV signal, a second clock terminal CK 2  receiving the second clock signal CKB, a first clock terminal CK 1  receiving the first clock signal CK, and a voltage terminal VSS receiving the low-level voltage Vss (i.e. a ground voltage). The output terminal OUT of the dummy stage SRCd delivers substantially the same output signal as that of the first to nth stages SRC 1  to SRCn to the input terminal IN 2  of the previous stage (i.e. the nth stage SRCn).  
         [0028]     The first connecting conductor  140  delivers the first gate driving signal to the input terminals, for example, the first input terminal CK 1 , the second input terminal CK 2 , and the voltage terminal VSS of each of the first, second, . . . , nth stages SRC 1 , SRC 2 , SRC 3 , . . . , SRCn. The first connecting conductor  140  comprises a first conductor  141 , a first voltage conductor  142 , a first clock conductor  143 , and a second clock conductor  144 .  
         [0029]     First conductor  141  delivers the STV signal to the first input terminal IN 1  of the first stage SRC 1  and the second input terminal IN 2  of the dummy stage SRCd, respectively. The first voltage conductor  142  delivers the low-level voltage Vss to the voltage terminal VSS of each of the first, second, third, . . . , nth stages SRC 1 , SRC 2 , SRC 3 , . . . , SRCn, and the dummy stage SRCd.  
         [0030]     The first clock conductor  143  delivers the first clock signal CK to the first clock terminal CK 1  of each of the odd-numbered stages SRC 1 , SRC 3 , . . . SRCn−1, the dummy stage SRCd, and the second clock terminal CK 2  of each of the even-numbered stages SRC 2 , SRC 4 , . . . , SRCn.  
         [0031]     The second clock conductor  144  delivers the second clock signal CKB to the first clock terminal CK 1  of each of the even-numbered stage SRC 2 , SRC 4 , . . . , SRCn, the second clock terminal CK 2  of each of the odd-numbered stages SRC 1 , SRC 3 , . . . , SRCn−1 and the dummy stage SRCd.  
         [0032]     The sub-gate driver  150  comprises first, second, third, . . . , nth discharge elements TR 1 , TR 2 , TR 3 , . . . , TRn electrically connected to first, second, third, . . . , nth gate conductors GL 1 , GL 2 , . . . , GLn, respectively.  
         [0033]     The first discharge element TR 1  comprises a gate electrode Ge receiving the second clock signal CKB, a source electrode Se receiving the output signal of the first stage SRC 1 , and a drain electrode De receiving a ground voltage Vss. Herein, the first stage SRC 1  outputs its gate signal in response to the first clock signal CK, and the second stage SRC 2  outputs its gate signal in response to the second clock signal CKB. Specifically, the odd-numbered stages SRC 1 , SRC 3 , . . . , SRCn−1 output their corresponding gate signals, respectively, in response to the first clock signal CK.  
         [0034]     When the even-numbered stages SRC 2 , SRC 4 , . . . , SRCn output their corresponding gate signals, respectively, in response to the second clock signal CKB, each of the odd-numbered discharge elements TR 1 , TR 3 , TRn−1 pulls down the level of its gate signal delivered from each of the odd-numbered gate conductors GL 1 , GL 3 , . . . , GLn−1 in response to the second clock signal CKB.  
         [0035]     Each of the even-numbered discharge elements TR 2 , TR 4 , . . . , TRn also pulls down the level of its gate signal delivered from each of the even-numbered gate conductors GL 2 , GL 4 , . . . , GLn in response to the first clock signal CK.  
         [0036]     The second connecting conductor  160  comprises a second voltage conductor  162 , a third clock conductor  163 , and a fourth clock conductor  164 . The second voltage conductor  162  delivers the ground voltage Vss to the drain electrode De of each of the discharge elements TR 1 , TR 2 , . . . , TRn. The third clock conductor  163  delivers the first clock signal CK to the gate electrode Ge of each of the even-numbered discharge elements TR 2 , TR 4 , . . . , TRn. The fourth clock conductor  164  delivers the second clock signal CKB to the gate electrode Ge of each of the odd-numbered discharge elements TR 1 , TR 3 , . . . , TRn−1. Herein, it should be noted that the first and second clock signals CK and CKB may be in turn applied to the first and second input terminals CK 1  and CK 2 .  
         [0037]     The operation of the nth stage SRCn will be now described in more detail with reference to  FIGS. 4 and 5 .  FIG. 4  shows a circuit diagram of one stage among a plurality of stages formed in the gate driver and the sub-gate driver of  FIG. 3 , and  FIG. 5  shows a timing diagram illustrating the operation of the gate driver and the sub-gate driver of  FIG. 4 .  
         [0038]     Referring to  FIG. 4 , the nth stage SRCn comprises a pull-up  131  pulling up the output signal GLn in response to the first clock signal CK, and a pull-down  132  pulling down the output signal GLn in response to the output signal G(n+1) of a (n+1)th stage.  
         [0039]     The pull-up  131  comprises a first transistor TFT 1  with a gate electrode electrically connected to a first node N 1 , a source electrode electrically connected to the first clock terminal CK 1 , and a drain electrode electrically connected to the output terminal OUT. The pull-down  132  comprises a second transistor TFT 2  with a gate electrode electrically connected to the second input terminal IN 2  of the (n+1)th stage, a drain electrode electrically connected to the output terminal OUT, and a source electrode electrically connected to a ground voltage Vss.  
         [0040]     The nth stage SRCn further comprises a pull-up driver which turns on the pull-up  131  in response to the output signal G(n−1) of a previous stage (i.e. the (n−1)th stage SRC(n−1)) and turns off the pull-up  131  in response to the output signal G(n+1) of the next stage (i.e. the (n+1)th stage SRC(n+1)). The pull-up driver comprises a buffer  133 , a charging  134 , and a first discharging  135 .  
         [0041]     The buffer  133  comprises a fourth transistor TFT 4  with a gate electrode and a drain electrode electrically connected to the first input terminal IN 1  in common, and a source electrode electrically connected to the first node N 1 . The charging  134  comprises a first capacitor C 1  with a first electrode electrically connected to the first node N 1  and a second electrode electrically connected to the second node N 2 . The first discharging  135  comprises a ninth transistor TFT 9  with a gate electrode electrically connected to the second input terminal IN 2  of the (n+1)th stage SRC(n+1), a drain electrode electrically connected to the first node N 1 , and a source electrode electrically connected to the voltage terminal VSS.  
         [0042]     The nth stage SRCn further comprises a holding  136  holding the output signal Gn to the ground voltage Vss, and a switching  137  controlling an operation of the holding  136 . The holding  136  comprises a third transistor TFT 3  with a gate electrode electrically connected to the third node N 3 , a drain electrode electrically connected to the second node N 2 , and a source electrode electrically connected to the voltage terminal VSS. The switching  137  comprises seventh, eighth, twelfth, and thirteenth transistors TFT 7 , TFT 8 , TFT 12 , and TFT 13 , and second and third capacitors C 2 , C 3 .  
         [0043]     The gate and drain electrodes of the twelfth transistor TFT 12  are electrically connected to the first clock terminal CK 1  altogether and the source electrode of the twelfth transistor TFT 12  is electrically connected to the third node N 3 . The drain electrode of the seventh transistor TFT 7  is electrically connected to the first clock terminal CK 1 ; the gate electrode of the seventh transistor TFT 7  is electrically connected to the first clock terminal CK 1  through the second capacitor C 2 ; and the source electrode of the seventh transistor TFT 7  is electrically connected to the third node N 3  through a third capacitor C 3 . The third capacitor C 3  is disposed between the gate electrode and the source electrode of the seventh transistor TFT 7 .  
         [0044]     The gate electrode of the thirteenth transistor TFT 13  is electrically connected to the second node N 2 ; the drain electrode of the thirteenth transistor TFT 13  is electrically connected to the source electrode of the twelfth transistor TFT 12 ; and the source electrode of the twelfth transistor TFT 12  is electrically connected to the voltage terminal VSS. The gate electrode of the eighth transistor TFT 8  is electrically connected to the second node N 2 ; the drain electrode of the eighth transistor TFT 8  is electrically connected to the drain electrode of the seventh transistor TFT 7 ; and the source electrode of the eighth transistor TFT 8  is electrically connected to the voltage terminal VSS.  
         [0045]     The nth stage SRCn further comprises a ripple prevention  138  and a reset  139 . The ripple prevention  138  comprises tenth and eleventh transistors TFT 10 , TFT 11 . The gate electrode of the tenth transistor TFT 10  is electrically connected to the first clock terminal CK 1 ; the drain electrode of the tenth transistor TFT 10  is electrically connected to the source electrode of the eleventh transistor TFT 11 ; and the source electrode of the tenth transistor TFT 10  is electrically connected to the second node N 2 . The gate electrode of the eleventh transistor TFT 11  is electrically connected to the second clock terminal CK 2  and receives the second clock signal CKB.  
         [0046]     The reset  139  comprises a sixth transistor TFT 6  with a gate electrode electrically connected to the reset terminal RS receiving the output signal Gn of the nth stage SRCn, a drain electrode electrically connected to the first node N 1 , and a source electrode electrically connected to the voltage terminal VSS.  
         [0047]     The nth discharging element TRn comprises a fourteenth transistor TFT 14  with a gate electrode receiving the second clock signal CKB; the source electrode electrically connected to the nth gate conductor GLn; and the drain electrode electrically connected to the voltage terminal VSS.  
         [0048]     When the nth stage SRCn outputs the output signal Gn to the nth gate conductor GLn in response to the first clock signal CK, the fourteenth transistor TFT 14  discharges the output signal Gn delivered to the nth gate conductor GLn to the ground voltage Vss in response to the second clock signal CKB.  
         [0049]     A display area (DA) represents an equivalent circuit of the LCD panel  100  (see  FIG. 1 ). In other words, the display area (DA) comprises a plurality of resistors R 1 , . . . , Rm and a plurality of capacitors Cl 1 , . . . , Clm considering a plurality of elements (not shown) formed in the LCD panel  100 .  
         [0050]     Referring to  FIG. 5 , the nth stage SRCn outputs the nth gate signal Gn in response to the first clock signal CK. The nth gate signal Gn is applied to the nth gate conductor GLn and activates the liquid crystal capacitors Cl 1 , . . . , Clm (see  FIG. 4 ) so as to charge a desired pixel voltage therein.  
         [0051]     The nth gate signal Gn is applied to the source electrode of the nth discharging element TRn. Meanwhile, the gate electrode of the nth discharging element TRn receives the second clock signal CKB different from the phase of the first clock signal CK, such as, but not limited to, a 180° phase difference between the first and second clock signals CK, CKB. The nth discharging element TRn discharges the nth gate signal Gn applied to the source electrode to the ground voltage Vss in response to the second clock signal CKB. In other words, since the second clock signal CKB is a clock signal of a constant period, the nth discharging element TRn continues to discharge a voltage left in the nth gate conductor GLn to the ground voltage Vss and thus improves stability of the operation of the liquid crystal capacitors Cl 1 , . . . , Clm electrically connected to the nth gate conductor GLn.  
         [0052]     Meanwhile, the (n+1) th stage SRC(n+1) outputs a (n+1)th gate signal G(n+1) in response to the second clock signal CKB. The (n+1) th gate signal G(n+1) is applied to the gate conductor GL(n+1) and activates the liquid crystal capacitors Cl 1 , . . . , Clm so as to charge a desired pixel voltage therein.  
         [0053]     Then, the (n+1)th gate signal G(n+1) is applied to the source electrode of the (n+1)th discharging element TR(n+1). Meanwhile, the gate electrode of the (n+1)th discharging element TR(n+1) receives the first clock signal CK different from the phase of the second clock signal CKB, such as, but not limited to, a 180° phase difference between the first and second clock signals CK, CKB. In this configuration, the (n+1)th discharging element TR(n+1) discharges the (n+1)th gate signal G(n+1) applied to the source electrode to the ground voltage Vss in response to the first clock signal CK. In other words, since the first clock signal CK is a clock signal of a constant period, the nth discharging element TRn continues to discharge a voltage left in the (n+1)th gate conductor GL(n+1) to the ground voltage Vss and thus improves stability of the operation of the liquid crystal capacitors Cl 1 , . . . , Clm electrically connected to the (n+1)th gate conductor GL(n+1).  
         [0054]      FIG. 6  shows a timing diagram illustrating the operation of the sub-gate driver  160  of  FIG. 4 . Referring to  FIG. 6 , a Kth discharging element TRK comprises a gate electrode electrically connected to a (K+1)th gate conductor, a drain electrode electrically connected to a Kth gate conductor, and a source electrode electrically connected to the voltage terminal VSS. The Kth discharging element TRK discharges the Kth gate signal GK to the ground voltage Vss in response to the (K+1)th gate signal delivered through the (K+1)th gate conductor.  
         [0055]     Since the (K+1)th gate signal applied to the gate electrode of the Kth discharging element TRK is delivered through the (K+1)th gate conductor, resistance and capacitance of the (K+1)th gate conductor cause deterioration of the (K+1)th gate signal. The Kth discharging element TRK generates a leakage current by the (K+1)th gate signal G(K+1) and thus a signal noise is introduced in the Kth gate signal GK. As a result, the liquid crystal capacitor driven by the Kth gate signal GK with the signal noise may be unstably operated.  
         [0056]     According to the exemplary embodiments of the present invention, the first or second clock signals CK or CKB of the gate driver  130  generate the gate signal each corresponding to the gate conductors without any signal noise. Further, the gate driver  130  and the sub-gate driver  160  improve reliability of the gate signal each corresponding to the gate conductors. In other words, a control signal not influenced by resistance and capacitance of each of the gate conductors may stably generate the gate signal each corresponding to the gate conductors.  
         [0057]     What has been described is illustrative of the principles of the invention, various modifications may be apparent to those skilled in the art and may be made without, however, departing from the spirit and scope of thereof.