Abstract:
A comparator for an analog-to-digital converter comprises an input stage (in + , in − , M 1 , M 2 ) for receiving an input signal; a bipolar latch stage (Q 1 , Q 2 ; Q 1   a - b , Q 2   a - b ) coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output (V a , V b ) to a level suitable for CMOS circuitry; and an output (out + , out − ). The means for amplifying includes at least one tapping transistor (Q 3 , Q 4 ) coupled to the latch stage for, depending on the latch decision, tapping a collector current (I c2 ; I c1 ) from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain (β) of the latch stage can be used to amplify a latch bias current (I a , I b ) of the latch stage to thereby provide for the amplification.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]    This application is a continuation of copending International Application No. PCT/SE02/00694 filed Apr. 9, 2002, and claiming a priority date of Apr. 11, 2001, which designates the United States. 
     
    
     
       TECHNICAL FIELD OF THE INVENTION  
         [0002]    The present invention generally relates to field of analog-to-digital conversion, and more specifically, to a comparator for an analog-to-digital converter, and to a method of operating a comparator circuit.  
           [0003]    High speed or low latency analog-to-digital converters (ADC&#39;s) need a fast comparator design. In many cases this means that a comparator using a bipolar latch would be advantageous. However, the circuits receiving the comparator output are often implemented in CMOS and hence CMOS output levels of the comparator are desired. Using circuit techniques known today for implementing a level shift from the bipolar latch signal swing of about 0.7 volt to the full power supply signal swing of CMOS with only an insignificant additional delay will require a large power consumption. Such large power consumption can usually not be tolerated or is not desired.  
           [0004]    Feeding the 0.7 voltage swing directly to a CMOS buffer will cause two problems to arise. Firstly, the matching of the common mode voltage of the bipolar output to the threshold of the CMOS inverter will depend on absolute values of the different components and will not give a reliable matching. Secondly, the input drive of the CMOS inverter will only be in the order of 0.7/2 volts, which due to the poor MOS transistor transconductance will cause the inverter to only deliver a smaller output current and hence the delay will be undesirably large.  
           [0005]    To overcome such problems various comparator circuits have been proposed. In FIG. 1 is shown an example of such a comparator circuit. The FIG. 1 circuit provides CMOS output levels and has the potential of operating at high speed due to the short time constant of the regenerative bipolar latch formed by transistors Q 1  and Q 2 . The nMOS transistors M 1  and M 2  form an input suitable for switched capacitor circuits. Resistors R 1  and R 2  comprise a load for the input stage in the preamplification phase when clock Φ is low, and for the bipolar latch during comparison phase starting when Φ goes high. The bipolar latch is buffered by emitter followers Q 3  and Q 4  to not degrade the regeneration time constant by the load of the differential stage Q 5  and Q 6 , which would slow down the response. The differential stage steers the current 2×I 3  to either the current mirror M 5 , M 6  or to the current mirror M 7 , M 8  depending on the latch decision. Consequently, the node voltages a +  and a −  will go in opposite direction to high and low levels depending on the current steering. The desired drive capability is then supplied by buffers B 1  and B 2 .  
           [0006]    The comparator in FIG. 1 represents a frequently used technique, wherein the common mode voltage of the bipolar latch output will be of less concern since it is interfaced by the differential stage Q 5  and Q 6 . Also, due to the use of bipolar transistors, even the low ±0.7 volt differential swing will be adequate to fully direct the 2×I 3  current. The delay to nodes a ±  is then dependent on the ratio between the parasitic capacitors C ±  and the bias current I 3 , which can be chosen arbitrarily within certain ranges. Thus, an increased speed is obtained at the cost of increased power consumption. The slew rate also improves with low load capacitance, which means that the buffers should have a small input capacitance. Consequently, an increased number of buffer stages may be necessary to provide sufficient drive, but which indeed add further delay to the comparator.  
         SUMMARY OF THE INVENTION  
         [0007]    Accordingly, it is an object of the present invention to provide a comparator circuit for an analog-to-digital converter, which uses a bipolar latch to obtain an adequate speed, and which provides an output suitable to be used in CMOS circuitry.  
           [0008]    In this respect there is a particular object of the invention to provide such a comparator circuit, which provides for a fast level shift at an insignificant increase in power consumption.  
           [0009]    A further object of the present invention is to provide such a comparator circuit with high drive capability, which reduces the amount of output buffering needed.  
           [0010]    Still a further object of the present invention is to provide such a comparator circuit, which is accurate, precise, efficient, simple, and of low cost.  
           [0011]    These objects among others are attained by a comparator circuit comprising an input stage, preferably a differential stage, for receiving an input signal; a bipolar latch stage, preferably consisting of a pair of bipolar transistors, coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output to a level suitable for CMOS circuitry; and an output, possibly a differential output. According to the invention the means for amplifying includes at least one and preferably two tapping transistors, preferably bipolar transistors, coupled to the latch stage for, depending on the latch decision, tapping a collector current from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain of the latch stage can be used to amplify a latch bias current of the latch stage to thereby provide for the amplification.  
           [0012]    By amplifying the latch bias current to a considerably larger current, which current is used to toggle the state of the output, a higher voltage swing than the swing of the latch stage itself, is provided.  
           [0013]    An inventive analog-to-digital converter comprises a plurality of the above described comparator circuit.  
           [0014]    Still a further object of the present invention is to provide a method of operating a comparator for an analog-to-digital converter, which provides an output suitable to be used in CMOS circuitry, and which provides for a fast comparison at low power consumption.  
           [0015]    These objects among others are attained by a method wherein:  
           [0016]    (i) an input signal, preferably a differential signal, is fed to a differential input stage;  
           [0017]    (ii) a latch decision is performed based on the input signal in a bipolar latch stage coupled to the input stage, and an output signal, preferably a differential output signal, depending on the decision is output therefrom;  
           [0018]    (iii) the output signal is amplified to a level suitable to be input to CMOS circuitry; and  
           [0019]    (iv) the amplified output signal is output through an output.  
           [0020]    The method comprises the inventive features that depending on the latch decision a collector current is tapped from the latch stage, while the latch decision thereof is left unaffected, by means of a tapping or level shift transistor coupled to the bipolar latch stage; and a current gain of said bipolar latch stage is used to amplify a latch bias current of the bipolar latch stage to thereby provide for the amplification of the output signal.  
           [0021]    The present invention uses the excessive drive capability of the bipolar latch stage to discharge level shifting nodes located at the output side of the tapping or level shift transistor and thus a large output swing is achieved with low delays and low power consumption. The output swing is readily matched to the full power supply signal swing of CMOS circuitry.  
           [0022]    Further characteristics of the invention and advantages thereof will be evident from the detailed description of preferred embodiments of the present invention given hereinafter and the accompanying FIGS.  1 - 8 , which are given by way of illustration only, and thus are not limitative of the present invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]    Throughout the Figures the following abbreviations are used: Q denotes a bipolar transistor; M denotes a MOS transistor; Φ denotes a clock, R denotes a resistor; C denotes a parasitic capacitance or a capacitor; B denotes a buffer; V denotes a voltage; I denotes a current; INV denotes an inverter, and lower-case letters generally denote various nodes in the respective circuits.  
         [0024]    [0024]FIG. 1 illustrates a typical prior art comparator circuit.  
         [0025]    [0025]FIG. 2 a  illustrates a comparator circuit according to a first preferred embodiment of the present invention.  
         [0026]    [0026]FIG. 2 b  illustrates a bias generation circuitry to be used with the comparator circuit of FIG. 2 a.    
         [0027]    [0027]FIGS. 3 a - c  are diagrams illustrating typical node voltages in the comparator circuit of FIG. 2 a  during a clock cycle; FIG. 3 a  shows clock voltages, FIG. 3 b  shows voltages at nodes a and b, and FIG. 3 c  shows voltages at nodes c, d, e and q.  
         [0028]    [0028]FIG. 4 illustrates the fundamental structure of the comparator circuit of FIG. 2 a  including a bipolar latch and common base transistor circuitry.  
         [0029]    [0029]FIG. 5 illustrates a comparator circuit according to a second preferred embodiment of the present invention.  
         [0030]    [0030]FIGS. 6 a - c  are diagrams illustrating typical node voltages in the comparator circuit of FIG. 5 during a clock cycle; FIG. 6 a  shows clock voltages, FIG. 6 b  shows voltages at nodes a and b, and FIG. 6 c  shows voltages at nodes d and e.  
         [0031]    [0031]FIGS. 7 a - b  illustrate schematically a respective latch configuration with current gain equal to the square of the transistor current gain to be used in a comparator circuit according to a respective third and fourth preferred embodiment of the present invention.  
         [0032]    [0032]FIG. 8 illustrates a comparator circuit according to a fifth preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0033]    In the following description, for purposes of explanation and not limitation, specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other versions that depart from these specific details.  
         [0034]    The present description is divided into ten sections, the first of which briefly overviews the key points of the present invention. Then a first preferred inventive circuit example is presented, followed by three sections regarding a circuit analysis of the first preferred inventive example: analysis in reset phase, analysis in comparison phase, and conclusion. Next, bias considerations for the first circuit example will be given. Thereafter a second preferred inventive circuit example is given, and the following section briefly presents the outlines of a third and a fourth preferred inventive circuit example. Finally, a fifth preferred circuit example is briefly set out followed by a short section of advantages of the present invention.  
         [0035]    Key Point of the Invention  
         [0036]    The basic idea is to utilize the current gain of the transistors in a bipolar latch to amplify a latch bias current to a considerably larger current, which then is used to toggle the state of a node, which will provide a higher voltage swing than the latch itself. This or these node(s) will hereafter be referred to as level shifting node(s).  
         [0037]    The large drive capability will be present when the latch has made its decision and started to toggle. Then one of the two transistors will be turned off so that the whole bias current into that transistor instead will have to go into the base of the other transistor. This means that the collector current of the other transistor will be the bias current (base current) amplified by its current gain, which usually is above 50 times. Additionally, bipolar latches intended for high-speed operation usually have a significant bias level to start with.  
         [0038]    To utilize this property the collector current has to be tapped from the latch in such a way that normal latch operation is not disturbed and so that most of the current drive can be used. The tapping of the bipolar latch current can be made in different ways but is preferably implemented using bipolar transistors to fully utilize the bipolar latch drive capability. For best performance the tapped current should be directly lead to the level shifting nodes, which due to the large current levels will evaluate at high speed.  
         [0039]    By the use of this feature, very fast comparators can be formed. The biasing of the tapping transistors, hereafter called the level shift transistors if they are directly connected to the level shifting nodes, can be made in various manners by the man skilled in the art.  
         [0040]    First Preferred Embodiment (FIGS. 2 a - b  and  3   a - c )  
         [0041]    An implementation of the described idea is shown in FIGS. 2 a - b , which provides a solution to the speed and power consumption trade-off dilemma of today&#39;s comparators. The first part is an ordinary bipolar latch comprising two bipolar transistors Q 1  and Q 2  with a reset transistor M 4  and a differential MOS input stage M 1 , M 2 .  
         [0042]    The present invention concerns the manner of how the latch decision is converted to CMOS levels. In this embodiment the conversion is primary made by the use of a pair of bipolar transistors Q 3  and Q 4  in common base configuration. However, a key to make this arrangement reliable and with low power consumption is to provide a proper biasing of the base voltage of transistors Q 3  and Q 4 . MOS transistors M 7 , M 8 , M 9 , M 10  and the bias circuit of FIG. 2 b  supply this biasing, but to rapidly get an understanding of the fundamental operation, the base bias considerations will be left aside for a while.  
         [0043]    A typical diagram of the node voltages during a cycle of operation for the comparator in FIGS. 2 a - b  is provided in FIGS. 3 a - c . In FIG. 3 a  is shown the node voltage for clock F; in FIG. 3 b  are shown V a  and V b , i.e. the voltages at nodes a and b, respectively; and in FIG. 3 c  are shown V c , V d , V e , and V q , i.e. the voltages at nodes c, d, e, and q, respectively.  
         [0044]    A cycle of operation includes reset and comparison phases as indicated at the top of FIG. 3 a . Different modes, i.e. reset, decision, level shift, discharge, settled and resetting modes, of operation during reset and comparison phases are indicated at the bottom of FIG. 3 c . The following operation description will refer to these modes.  
         [0045]    At the beginning of the reset phase the clock signal Φ goes low and consequently transistors M 4 -M 7  are turned on during the initial reset phase (the resetting mode), so that the latch Q 1 , Q 2  is reset and nodes d, e, q become pre-charged.  
         [0046]    This pre-charged state is kept during the rest of the reset phase (the reset mode).  
         [0047]    Then, at the beginning of the comparison phase the clock signal Φ goes high and transistors M 4 -M 7  will turn off. The latch will then start to evaluate due to imbalance in the currents to the latch from any input voltage (the decision mode). Depending on the decision, one of the nodes a and b will start to discharge towards V ss  (node b in FIG. 3 b ).  
         [0048]    Assuming correct base bias of transistors Q 3  and Q 4 , the transistor connected to the discharging node will turn on and hold this voltage and instead start to discharge the pre-charged node at its collector (the level shift mode).  
         [0049]    This discharging is continued (the discharge mode) and finally the node is fully discharged and a steady-state is reached (the settled mode), which complete the operation cycle, see further the section of base bias considerations.  
         [0050]    When the pre-charged node has discharged to below the threshold level of the output inverter INV 1 , INV 2  coupled to the node (INV 2  coupled to node b via transistor Q 4 ), the comparator output will finally evaluate. This is probably performed during the level shift mode.  
         [0051]    As will be seen from the following detailed analysis, the current available to discharge the pre-charged nodes d and e will be very large compared to the bias levels. The analysis will refer to the annotations in FIG. 4, which shows the bipolar latch and the common base transistor circuitry extracted from FIG. 2 a.    
         [0052]    Analysis of the First Preferred Embodiment in Reset Phase (FIG. 4)  
         [0053]    At reset phase the a and b node voltages, V a  and V b , respectively, are forced to approximately equal voltages by means of transistor M 4 . Denote the base-emitter voltage of the bipolar transistors during normal forward biasing as V BEfw , which in normal cases is roughly 0.6-0.9 volts. Further, denote the collector-emitter voltage under which the bipolar transistor goes in to saturation and the collector current start to decrease as V CEsat . Now assume that the base bias voltage V c  is set at a safe distance from the lower and upper limits so that:  
           V   BEfw   +V   CEsat   &lt;V   c &lt;2 V   BEfw   (1)  
         [0054]    is satisfied at all normal operating conditions. Since transistors Q 1  and Q 2  together drop the differential stage current, I bias , the voltages V a  and V b  will both be near V BEfw . The base-emitter voltages of transistors Q 3  and Q 4  will then become less than V BEfw  so that:  
         I e3 ≈0 and I e4 ≈0  (2)  
         [0055]    The level shifting transistors Q 3  and Q 4  do thus not affect the reset phase except for the additional capacitive load. The capacitive load will, however, be considerably less than the load introduced by the transistors Q 1  and Q 2  themselves since the base-emitter diodes of transistors Q 3  and Q 4  are not strongly forward biased.  
         [0056]    Analysis of the First Preferred Embodiment in Comparison Phase  
         [0057]    During the comparison phase the I a  and I b  currents may be described as:  
           I   a   =I   bias (½+ε)  
           I   b   =I   bias (½−ε), −½≦ε≦½  (3)  
         [0058]    Since the circuit is symmetric it is sufficient to analyze only the input condition where the latch evaluates so that V b  will drop while V a  slightly rises, i.e. when:  
         ε&gt;0  (4)  
         [0059]    Due to the exponential I-V relationship of the bipolar base-emitter diode the V b  drop during latch evaluation will rapidly cause transistor Q 1  to turn off during the decision mode and soon approach:  
         I b1 ≈0  (5)  
         [0060]    Defining the bipolar current gain as β this will result in:  
           I   c1   =βI   b1 ≈0  (6)  
         [0061]    Since the strongly forward biased base-emitter diode of the transistor Q 2  prevents V a  to rise much further above the initial V BEfw  voltage, the charging of C a  will be negligible and thus:  
         I pa ≈0  (7)  
         [0062]    so that  
           I   b2   =I   a   +I   c3   −I   c1   −I   pa   ≈I   a   =I   bias (½+ε)  (8)  
         [0063]    This gives the collector current of transistor Q 2 :  
           I   c2   =βI   b2   ≈I   bias (½+ε)  (9)  
         [0064]    Until transistor Q 4  turns on the discharge current in C b  will be:  
           I   pb   =I   b   +I   e4   −I   c2   −I   b1   ≈I   b   −I   c2   =I   bias (½−ε)−β I   bias (½+ε)  (10)  
         [0065]    At normal conditions: β&gt;&gt;1, and therefore:  
           I   pb   ≈−βI   bias (½+ε)  (11)  
         [0066]    As is understood from eq. (11) the discharge current is large compared to the bias current and the discharge of node b will be rapid as expected from a bipolar latch. When V b  after a short while has discharged down to V c −V BEfw  then transistor Q 4  will turn on and start to hold this voltage level at a constant value, which defines the level shift mode. The discharge current is therefore instead deflected via transistor Q 4  so that now:  
         I pb ≈0  
           I   c4   ≈I   e4   ≈βI   bias (½+ε)  (12)  
         [0067]    again assuming a large β. Using the boundaries of ε and the condition under which V b  will drop, we get that the discharge current to the level shifting node will be within the range:  
           βI   bias /2≦ I   c4   ≦βI   bias   (13)  
         [0068]    Conclusion of the Analysis of the First Preferred Embodiment  
         [0069]    To get a discharge current in the prior art circuit in FIG. 1, which is comparable to the discharge current indicated by eq. (13) resulting from the proposed technique, the bias current of the second differential stage has to be β times the bias current of the input stage. Usually, β is above 50 and hence considerably power consumption savings or performance improvements can be made using the suggested approach. This holds especially true when the demands for a short delay in the level shifting stage is stringent.  
         [0070]    Also, since the discharge current is of that magnitude, the need of a low load capacitance is considerably reduced. Therefore the output buffer can in most cases be reduced to a single inverter and hence the delays of extra buffer stages are avoided.  
         [0071]    Base Bias Considerations  
         [0072]    When the level shifting node has been discharged so that the level shift transistor goes into saturation, the voltage V c  should no longer be held constant since the latch would in such cases continue to drive the large current but now via the level shift transistor base. This current would then have to be supplied by the power supply resulting in unnecessary power consumption.  
         [0073]    To allow V c  to drop when either V d  or V e  has been discharged a MOS transistor M 8  arranged in a source follower configuration is used to regulate the V c  voltage. Its drain is connected to another pre-charged node q and therefore, when node d or e has been discharged the current flow will instead start to discharge node q via the level shift transistor base and transistor M 8 , which defines the discharge mode.  
         [0074]    The need of charge storage capacity at node q is only 1/β times the charge storage capacity at nodes d or e due to the current gain in the level shift transistors. This is easily accomplished by the small parasitic capacitors inherent to transistor M 8  and its pre-charge transistor M 7 . The node q will therefore rapidly be discharged and transistor M 8  will no longer be able to hold the V c  voltage, so this voltage will now drop. When V b  approaches V ss  the current flow ceases and unnecessary power consumption is avoided. The comparator is now fully settled (settled mode) since its output is already evaluated at this stage.  
         [0075]    The power consumption of the level shift operation will not appear until the reset phase starts since no extra current will be drawn from the supply during the comparison phase because transistors M 5 -M 7  are off. At the first moments of the reset phase, nodes d, e and q will be pre-charged again and the small charge from the power supply to pre-charge these nodes is the only power consumption cost that will be required for the level shift operation besides the minor bias current in transistor M 10  during the reset phase. The bias current of transistor M 10  is only needed to keep the V c  voltage difference between reset and comparison phase negligible by drawing at least a minor current in transistor M 8  during the two phases. Otherwise there will be a mismatch since a level shift transistor will draw base current through transistor M 8  in the comparison phase but not in the reset phase. Transistor M 10  is switched of in the comparison phase by transistor M 9 . The current compensation of transistors M 9 -M 10  is not compulsory.  
         [0076]    The choice of V c  level deserves some comments. The closer V c  is to the upper voltage limit, the faster the comparator response will be since the latch does not have to toggle as much before the level shifting transistors turn on. But if V c  would equal or go above the upper limit there will be a large static current during the reset phase increasing the power consumption to start with, and beyond that, the comparator will fail to work primarily due to that the nodes d and e newer will pre-charge to high. On the other hand, if V c  goes below the lower voltage limit, the comparator will rapidly get slower as the latch transistors saturates when trying to supply current to the level shift transistors. Eventually, the level shift transistors will not turn on at all and the circuit fails to work. Simulations has shown a useful range of at least 0.6 volt for the V c , which should be easy to maintain for example by using the bias circuit arrangement in FIG. 2 b  assuming that the transistor ratios are correctly adjusted.  
         [0077]    Second Preferred Embodiment (FIGS. 5 and 6 a - c )  
         [0078]    Another circuit example making use of the suggested principle is shown in FIG. 5. By a quick look at this circuit we can see that in the reset phase and prior to a valid decision, the discharge current to d and e is only the small base currents of transistors Q 1  and Q 2 . As soon as a decision is made either Q 1  or Q 2  will turn off so that the corresponding level shift transistor Q 3  or Q 4  will get the whole I a  or I b  current into its base. This current will be amplified by the transistor current gain and thus the level shift current will, as for the first circuit example, be rather large.  
         [0079]    However, this circuit cannot discharge a level shift voltage lower than V BEfw  since the discharge paths are in series with the forward base-emitter diodes of either transistor Q 1  or transistor Q 2 . In contrast thereto, the first circuit example will discharge to a voltage close to V ss  even though the discharge rate of the last tenth of volts will be slow. Simulations also shows that this second comparator is slower. But instead, the need of extra bias arrangements are completely eliminated.  
         [0080]    Clock pulse voltages and node voltages at nodes a, b, d and e during an operation cycle of this comparator circuit embodiment are shown in FIGS. 6 a - c . As before the reset and comparison phases are indicated at the top of FIG. 6 a , whereas the reset, decision, level shift, discharge, settled and resetting modes are indicated at the bottom of FIG. 6 c.    
         [0081]    Third and Fourth Preferred Embodiments (FIGS. 7 a - b )  
         [0082]    The use of Darlington-like coupled transistors in the latch stage opens up for a few alternative configurations.  
         [0083]    According to a third preferred embodiment circuit of the present invention the comparator comprises a latch including four bipolar transistors Q 1   a , Q 1   b , Q 2   a , Q 2   b  arranged in a Darlington-coupled state as shown in FIG. 7 a . As regards other components and features this embodiment does not differ from the first preferred embodiment of the invention illustrated in FIG. 2 a.    
         [0084]    The effective current gain will increase to β 2  using this third embodiment, which results in a considerably higher current drive capability. The bias3 voltage (see FIG. 2 a ) now has to be about 0.7 volt higher due to one additional forward biased diode voltage drop in the latch. Also the d and e node voltages will only drop to about 0.7 volt due to this additional diode voltage drop.  
         [0085]    Next, according to a fourth preferred embodiment circuit of the present invention the comparator comprises a latch including four bipolar transistors Q 1   a , Q 1   b , Q 2   a , Q 2   b  arranged in a Darlington-like coupled state. The collectors of transistors Q 1   b  and Q 2   b  are as indicated in FIG. 7 b  connected to V dd  via RC circuitry R 1 , C 1 , and the emitters of transistors Q 1   a  and Q 2   a  are connected to V SS . Nodes a and b are as before coupled to a differential input stage. As regards other components and features this embodiment does not differ from the first preferred embodiment of the invention illustrated in FIG. 2 a.    
         [0086]    Using such a comparator design the high current gain advantage of the Darlington transistors is obtained, while still having a current drive down to the low V ss  potential.  
         [0087]    This comparator design also makes the biasing network of the tapping transistors as shown in FIG. 2 b  less critical since the latch voltage swing will be equal to two diode junction voltages or about 1.4 volts. The resistor R 1  shall have a value low enough to provide adequate bias to transistors Q 1   a  and Q 1   b  and discharge of capacitor C 1  during reset phase, but also have a resistance high enough to limit static power consumption during comparison phase. The function of C 1  is to temporarily maintain a high collector voltage of transistors Q 1   a  and Q 1   b  during the level shifting to get full current amplification in transistors Q 1   a  and Q 1   b . The value of C 1  has to be large enough to keep transistors Q 1   a  and Q 1   b  active until the level shift nodes have evaluated.  
         [0088]    Fifth Preferred Embodiment (FIG. 8)  
         [0089]    In applications that require only a single-ended comparator output it is possible to omit some of the comparator components compared to the embodiments using differential signals. An example hereof is illustrated in FIG. 8, which is a single-ended embodiment version corresponding to the comparator of FIGS. 2 a - b . In FIG. 8 the negative input is replaced by a reference voltage input leaving only a single-ended input. The purpose of the Q 4  transistor is only to add the same amount of parasitic capacitance as tapping transistor Q 3  adds, so that the parasitic capacitance on nodes a and b are matched. This will minimize systematic offsets but Q 4  can be removed if such offsets are not important.  
         [0090]    Advantages of the Present Invention  
         [0091]    The invention will improve the delay and power consumption product of most comparators whenever a BiCMOS process is available and CMOS output levels, i.e. levels corresponding to the full power supply signal swing of CMOS circuitry, are needed. Such comparators are widely used in high performance A/D-converters and are in many cases limiting factors in system performance. Therefore the present invention will raise the performance of such systems and fulfil strict requirements as regards both speed and power consumption.