Abstract:
An embodiment includes a tie-off circuit includes multiple field effect transistors (FETs), and a node isolation circuit that is connected to a first output node and a second output node of the tie-off circuit. The node isolation circuit consists of a first FET with a third output node and a second FET with a fourth output node. The second output node includes a logical LO node and is coupled to a gate of the first FET and generates a TIE HI output.

Description:
GOVERNMENT RIGHTS 
       [0001]    This invention was made with United States Government support under HR0011-09-C-0002 awarded by Defense Advanced Research Projects Agency (DARPA). The government has certain rights in this invention. 
     
    
     BACKGROUND 
       [0002]    ESD events may create extremely high voltages/currents that have the potential to destroy integrated circuits (ICs) by driving current into (or drawing current from) the decoupling/parasitic capacitance in the IC chip. ESD protection structures are used to protect Field Effect Transistor (FET) gate oxide and source/drain diffusions that are directly connected to a pad in the Input/Output (I/O) circuits by absorbing/shunting the majority of the ESD pulse. 
         [0003]    Technology scaling has enabled performance improvement, density increase and energy reduction, but it has also resulted in degradation of device ESD tolerance. The FET gate oxide breakdown voltage has been steadily decreasing due to reduction in oxide thickness, and the FET source/drain diffusion breakdown voltage has also been decreasing due to higher substrate doping density. Although I/O circuits may use slightly thicker FET gate oxide and lower substrate doping density to mitigate this ESD tolerance degradation, internal circuits use increasingly thinner gate oxide and higher substrate doping density to reap the benefits of technology scaling. Both the FET gate oxide and source/drain diffusion breakdown voltage of internal circuits have decreased. 
       SUMMARY 
       [0004]    Embodiments relate to electrostatic discharge (ESD) protection. One embodiment includes a tie-off circuit includes multiple field effect transistors (FETs), and a node isolation circuit that is connected to a first output node and a second output node of the tie-off circuit. The node isolation circuit consists of a first FET with a third output node and a second FET with a fourth output node. The second output node includes a logical LO node and is coupled to a gate of the first FET and generates a TIE HI output. 
         [0005]    These and other features, aspects and advantages of the embodiments will become understood with reference to the following description, appended claims and accompanying figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  illustrates a schematic diagram of a tie-off circuit; 
           [0007]      FIG. 2  illustrates a schematic diagram of a tie-off circuit according to one embodiment; 
           [0008]      FIG. 3  illustrates a schematic diagram of another tie-off circuit; 
           [0009]      FIG. 4  illustrates a schematic diagram of another tie-off circuit according to one embodiment; 
           [0010]      FIG. 5  illustrates a schematic diagram of a tie-off circuit including cascaded output stages according to one embodiment; and 
           [0011]      FIG. 6  illustrates a schematic diagram of a tie-off circuit including stages between wires according to one embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]    The following description is made for the purpose of illustrating the general principles of the embodiments and is not meant to limit the inventive concepts claimed herein. Further, particular features described herein can be used in combination with other described features in each of the various possible combinations and permutations. 
         [0013]    Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including meanings implied from the specification as well as meanings understood by those skilled in the art and/or as defined in dictionaries, treatises, etc. 
         [0014]    Embodiments relate to electrostatic discharge (ESD) protection. One or more embodiments improve upon conventional tie-off circuits by using one or two additional FETs to electrically isolate the internal HI or/and LO signals from the loaded outputs. In one embodiment, the additional FETs provides additional stability over conventional tie-off circuits by allowing the circuit&#39;s internal nodes to stabilize quickly even if the outputs are heavily/asymmetrical loaded or heavily coupled. In one example embodiment, compared to adding inverters to the conventional design for added stability and drive strength, which would require adding four additional FETs, the one or more embodiments achieves the same using only one or two additional FETs, thus reducing the additional silicon area necessary by half. 
         [0015]    In one embodiment, a modified tie-off circuit incorporates additional cascaded stages to provide additional immunity against heavy/asymmetrical loads. In instances where the tie-off circuit drives long connecting wires, one embodiment provides a variation by inserting the modified tie-off embodiment inserted at regular intervals along the connecting wire to mitigate capacitance coupling. In one or more embodiments, the benefits are achieved using half as many FETs as if inverters were used to achieve the same. 
         [0016]      FIG. 1  illustrates a schematic view of a tie-off circuit  100 . Tie-off circuit  100  includes three FETs consisting of a positive channel FET (PFET) P 0   110  and two negative channel FETs (NFETs) N 0   120  and N 1   125 . The hi node  140  is tied to TIEHI  130  and the lo node  145  is tied to TIELO  135 . In the worst case, the circuit  100  is initialized with TIEHI  130  node low (ground, (GND)) and TIELO  135  node high (power, voltage drain, drain (VDD)). In that event, both P 0   110  and N 1   125  are initially “off,” but N 0   120  turns on to bring its drain voltage (TIELO  135 ) down from VDD to Vt (Threshold Voltage). This weakly turns on P 0   110 , causing P 0   110  to pull up the gate of N 1   125  (TIEHI  130 ), which in turn causes N 1   125  to turn “on” and pull its drain voltage (TIELO  135 ) to GND. This consequently turns P 0   110  on fully and establishes regenerative feedback in which P 0   110  pulls up TIEHI  130  to keep N 1   125  on, while N 1   125  pulls down TIELO  135  to keep P 0   110  on. In this state, N 0   120  is off and only turns on if TIELO  135  becomes momentarily high or unstable. In this conventional circuit  100 , TIEHI  130  and TIELO  135  are simultaneously internal nodes and outputs, so any heavy/asymmetrical loading or heavy coupling may cause slow stabilization of the circuit nodes or instability. That is, for the conventional tie-off circuit  100 , the internal hi-node  140  and the output node TIEHI  130  are electrically coupled forming a first single node, and the internal lo-node node  145  and the output node TIELO  135  are electrically coupled forming a second single node. 
         [0017]    Even with the use of ESD protection structures, such as circuit  100 , any remaining high ESD currents/voltages propagate through the power/ground supply grid and may potentially damage any devices connected into the power/ground grid. While IC devices typically have drains/sources tied to the supply grid, tying a device&#39;s gate directly to power/ground is especially risky, since an FET&#39;s gate oxide breakdown voltage is roughly half of its source/drain breakdown voltage. Therefore, a tie-off circuit  100  is necessary to provide logical HI and logical LO voltage levels that may be used in place of power/ground to safely tie-off the gates of devices. In the conventional tie-off circuit  100 , P 0   110 , N 0   120  and N 1   125  are used to provide stable logical HI and logical LO levels using regenerative feedback, with no gates directly connected to power/ground. This configuration offers added ESD protection with minimal silicon area requirement (only 3 FETs), but the outputs may take a long time to stabilize if heavily loaded. Additionally, the outputs may become unstable if the HI and LO outputs are asymmetrically loaded or heavily coupled. 
         [0018]      FIG. 2  illustrates a schematic diagram of a tie-off circuit  200  according to one embodiment. In one embodiment, a stage  250  comprising two FETs including a PFET (P 2   210 ) and NFET (N 2   220 ) are added to the circuit  100  to isolate the internal nodes (hi  140  and lo  145 ) from the outputs (which in circuit  200  are TIEHI  230  and TIELO  235 ). In one embodiment, the lo node  145  is connected to the gate of P 2   210 , which generates the output TIEHI  230 , while the hi node  140  is connected to the gate of N 2   220 , which generates the output TIELO  235 . In one or more embodiments, since the outputs are electrically isolated from the internal feedback nodes by the addition of FETs P 2   210  and N 2   220 , heavy/asymmetrical loading or heavily coupled outputs will not prevent fast stabilization or jeopardize the stability of the internal nodes. 
         [0019]    In one embodiment, the output of TIEHI  230  is connected to a first input of an integrated circuit (IC)  260  and the output of TIELO  235  is connected to a second input of the IC  260 . In one embodiment, the IC  260  may comprise any type of IC for which protection from ESD is desired (e.g., an application specific IC (ASIC), memory device, processor, etc.). In one embodiment, the inputs of the IC  260  may comprise pads in an I/O circuit connected to the IC  260 , where the circuit  200  provides ESD protection by absorbing/shunting the majority of an ESD pulse. 
         [0020]      FIG. 3  illustrates a schematic diagram of another conventional tie-off circuit  300 . Tie-off circuit  300  is an alternative configuration for the conventional tie-off circuit  100  ( FIG. 1 ). Tie-off circuit  300  is configured using two PFETs (P 0   310  and P 1   325 ) and one NFET (N 0   320 ). In circuit  300 , P 0   310  and N 0   320  offer regenerative feedback to keep TIEHI  330  at VDD and TIELO  335  at GND, using the same principles as with circuit  100 . P 1   325  is turned off in typical operation and only turns on in the event that TIEHI  330  becomes low or unstable, in which case P 1   325  turns on to re-establish the desired output voltages. 
         [0021]      FIG. 4  illustrates a schematic diagram of another tie-off circuit  400  according to one embodiment. In this embodiment, circuit  400  includes a stage  450  including the addition of two FETs (PFET P 2   210  and NFET N 2   220 ) to the outputs of the conventional circuit  300  for electrically isolating the internal nodes (hi  340  and lo  345 ) from the outputs (TIEHI  430  and TIELO  435 ). In one embodiment, the addition of P 2   210  and N 2   220  improves upon the conventional design of circuit  300  by making the circuit  400  more robust and less susceptible to slow stabilization or instability that may result from heavy/asymmetrical loading or heavy coupling. 
         [0022]    The embodiments including circuits  200  and  400  provide added stability to the conventional tie-off circuits  100  ( FIG. 1 ) and  300  ( FIG. 3 ) by the additional two FETs in each circuit (stage  250  and stage  450 ), whereas simply adding inverters to the outputs of the conventional tie-off circuit (e.g., tie-off circuits  100  and  300 ) would require four (4) additional FETs and thus, twice as much additional silicon area. 
         [0023]    In one embodiment, the output of TIEHI  430  is connected to a first input of an IC  260  and the output of TIELO  435  is connected to a second input of the IC  260 . In one embodiment, the circuit  400  provides ESD protection for the IC  260 . In one embodiment, the inputs of the IC  260  may comprises pads in an I/O circuit connected to the IC  260 , where the circuit  400  provides ESD protection by absorbing/shunting the majority of an ESD pulse. 
         [0024]      FIG. 5  illustrates a schematic diagram of a tie-off circuit  500  including cascaded output stages  550  and  551  according to one embodiment. In the event that the tie-off circuit (e.g., circuit  100  ( FIG. 1 ) or  300  ( FIG. 3 )) load is extremely heavy or asymmetrical, adding one stage (e.g., stage  250 ,  FIG. 2 , or stage  450 ,  FIG. 4 ) to the conventional tie-off circuit may not be sufficient to maintain circuit stability. In that case, in one embodiment additional cascaded stage  550  (with hi 2  node  541 ) and stage  551  (with lo 2  node  546 ) may be added to the outputs of circuits  200  ( FIG. 2 ) and  400  ( FIG. 4 ) to provide additional drive strength and added electrical isolation of the internal feedback nodes (e.g., hi 1   141  and lo 1   146 ). 
         [0025]    In one embodiment, the output of TIELO  530  is connected to a first input of an IC  260  and the output of TIEHI  535  is connected to a second input of the IC  260 . In one embodiment, the circuit  500  provides ESD protection for the IC  260 . In one embodiment, the inputs of the IC  260  may comprise pads in an I/O circuit connected to the IC  260 , where the circuit  500  provides ESD protection by absorbing/shunting the majority of an ESD pulse. 
         [0026]    In one embodiment, the tie-off circuit  500  with two cascaded output stages  550  and  551  is shown as an example embodiment, but other embodiments may include additional cascaded output stages as necessary to drive the output load with sufficient strength and stability. In one or more embodiments, the stages  550  and  551  add only two additional FETs (NFET N 2   510  and PFET P 2   520 ) per cascaded stage, compared to four FETs per stage if a designer added inverters to the outputs of the conventional tie-off circuit  100 , thus reducing the additional silicon area needed by half. Since the states of the TIEHI  130  and TIELO  135  ( FIG. 1 ) outputs of the conventional tie-off circuit  100  are known and reinforced by positive feedback, adding full inverters to the outputs to provide additional stability and drive strength would be inefficient, whereas the embodiments use minimum additional silicon area to achieve desired results. 
         [0027]      FIG. 6  illustrates a schematic diagram of a tie-off circuit  600  including stages  650  and  655  between connecting wires  640 / 641  and  645 / 646  according to one embodiment. In one embodiment, in the event that the tie-off circuit (e.g., tie-off circuit  100 ) is loaded by long (e.g., 1-5 mm) wires  640 / 641  and  645 / 646  that are heavily (e.g., 0.2-1 pF) capacitive coupled, 1 PFET P 2   610  and 1 NFET N 2   620  are inserted in stage  650 , and 1 PFET P 2   611  and 1 NFET N 2   621  are inserted in stage  655 , at regular intervals along the wires  640 / 641  and  645 / 646 . In one embodiment, the output of TIELO 1   635  is connected to the wire  645  and the output of TIEHI 1   630  is connected to the wire  640 , and the output of TIELO 2   636  is connected to the wire  641  and the output of TIEHI 2   631  is connected to the wire  646 . 
         [0028]    In one embodiment, the added FETs in stages  650  and  655  provide protection against capacitive coupling as well as improved current drive along the length of each wire  640 / 641  and  645 / 646 , and require only two FETs per stage (e.g., P 2   610  and N 2   620  in stage  650 , and P 2   611  and N 2   621  in stage  655 ). If inverters were used as repeaters along the length of the wire instead, four FETs per stage would be necessary, requiring twice as much silicon area as the embodiment of circuit  600 . In one embodiment, the tie-off circuit  600  with two stages  650  and  655  inserted between the wires  640 / 641  and  645 / 646  is shown as an example embodiment, but other embodiments may include additional stages between additional wires as necessary to drive the output load with sufficient strength and stability. 
         [0029]    In one embodiment, the connection wire  641  is connected to a first input of an IC  260  and the wire  646  is connected to a second input of the IC  260 . In one embodiment, the circuit  600  provides ESD protection for the IC  260 . In one embodiment, the inputs of the IC  260  may comprises pads in an I/O circuit connected to the IC  260 , where the stages  650  and  655  coupled to the tie-off circuit  100  provides ESD protection by absorbing/shunting the majority of an ESD pulse. 
         [0030]    It will be clear that the various features of the foregoing methodologies may be combined in any way, creating a plurality of combinations from the descriptions presented above. 
         [0031]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof 
         [0032]    It should be emphasized that the above-described embodiments, particularly, any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the embodiments. 
         [0033]    Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the spirit and principles of the embodiments. All such modifications and variations are intended to be included herein within the scope of this disclosure and the embodiments and protected by the following claims.