Abstract:
A voltage reference generation circuit having switch pairs coupled to systematically commutate a flying capacitor among adjacent pairs of voltage rail outputs. The circuit requires only a single flying capacitor, N+1 switch pairs, and N storage capacitors, to generate N intermediate voltage references between VDD and GND. A signal generator produces N+1 non-overlapping switch enable signals to systematically enable the switch pairs and commutate the single flying capacitor between the rail pairs. The flying capacitor remains charged to VDD/(N+1). The N storage capacitors hold their respective reference outputs at VDD*N/(N+1), VDD*(N−1)/(N+1), VDD*(N−2)/(N+1), and so forth.

Description:
RELATED APPLICATION 
       [0001]    The present application claims benefit under 35 USC 119(e) of U.S. provisional Application No. 60/784,638, filed on Mar. 21, 2006, entitled “Adaptive Biasing Based on Volume Control Setting,” the content of which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field of the Invention 
         [0003]    This invention relates generally to circuits for generating voltage rails, and more specifically to an improved charge pump for generating voltage rails. 
         [0004]    2. Background Art 
         [0005]      FIG. 1  illustrates a charge pump circuit  10  which is known in analog and power semiconductor design. The charge pump is built around a flying capacitor CF, four controllable switches S 1  to S 4 , and capacitor CP. The capacitor CP can be referred to as a storage or bypass capacitor. A first switch SA and a third switch SC are coupled to a first terminal of the flying capacitor, and a second switch SB and a fourth switch SD are coupled to a second terminal of the flying capacitor. The first and second switches are operated together by a first phase control signal PHI 1 , and the third and fourth switches are operated together by a second phase control signal PHI 2 . The phase control signals are typically operated as binary clock signals 180° out of phase, and can be a clock signal and an inverted version of that clock signal with the addition of some dead time at each transition, when no switch is on. The dead time is important, to ensure that SB and SD do not produce a short between  50 P and GND, and to ensure that SA and SC do not produce a short between VDD and  50 P. 
         [0006]    The first switch un/couples the first terminal of the flying capacitor from/to the VDD voltage reference supply. The fourth switch un/couples the second terminal of the flying capacitor from/to the ground (GND) voltage reference supply. The second switch un/couples the second terminal of the flying capacitor from/to an output terminal  50 P at which the charge pump generates VDD/2. And the third switch un/couples the first terminal from/to the output terminal. The storage capacitor CP is coupled between the output terminal and the ground voltage reference supply in order to store the charge packets delivered by CF and to smooth the voltage at  50 P. 
         [0007]      FIGS. 2 and 3  show the two charge pump states (during assertion of PHI 1 , and assertion of PHI 2 , respectively) of the charge pump of  FIG. 1 . During PHI 1 , the flying capacitor is effectively coupled between VDD and the output node. During PHI 2 , the flying capacitor is effectively coupled between the output node and GND. 
         [0008]      FIG. 4  illustrates a voltage rail generation circuit  20  according to the prior art. In addition to the voltage reference inputs VDD and GND, the voltage rail generation circuit uses three of the  FIG. 1  charge pumps CP 50 , CP 75 , and CP 25  to generate three intermediate voltage rails: VDD*0.50 at terminal  50 P, VDD*0.75 at terminal  75 P, and VDD*0.25 at terminal  25 P, respectively. The primary charge pump CP 50  is coupled to VDD and GND, and generates an output voltage equal to (VDD+GND)/2. The second charge pump CP 75  is coupled to VDD and CP 50 , and generates an output voltage equal to (VDD+CP 50 )/2. The third charge pump CP 25  is coupled to CP 50  and GND, and generates an output voltage equal to (CP 50 +GND)/2. 
         [0009]    Unfortunately, each of the charge pumps requires its own, dedicated flying capacitor (CF 50 , CF 75 , and CF 25 ) and its own storage capacitor (C 50 P, C 75 P, and C 25 P). What is needed is an improved voltage rail generation circuit which does not require a dedicated flying capacitor for every voltage rail generated, while still maintaining the high efficiencies that charge pumps can obtain. It is desirable to minimize the flying capacitors, because they tend to have tighter ESR requirements than the storage capacitors and when integrated into an integrated circuit each flying capacitor requires two added pins which increases the cost of the integrated circuit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0010]      FIG. 1  shows a charge pump according to the prior art, for generating a VDD/2 voltage rail. 
           [0011]      FIGS. 2 and 3  show the two states of the charge pump of  FIG. 1 . 
           [0012]      FIG. 4  shows a circuit for generating VDD*0.75, VDD*0.50, and VDD*0.25 voltage rails, according to the prior art. 
           [0013]      FIG. 5  shows an improved voltage rail generation circuit according to one embodiment of this invention. 
           [0014]      FIGS. 6-9  show the four states of the circuit of  FIG. 5 . 
           [0015]      FIG. 10  shows results of a power efficiency simulation of the circuit of  FIG. 5 . 
           [0016]      FIGS. 11 and 12  show results of output impedance simulations of the circuit of  FIG. 5 . 
           [0017]      FIG. 13  shows a generalized voltage rail generation circuit according to one embodiment of this invention. 
           [0018]      FIG. 14  shows a voltage rail generation circuit according to yet another embodiment of this invention. 
       
    
    
     DETAILED DESCRIPTION  
       [0019]    The invention will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the invention which, however, should not be taken to limit the invention to the specific embodiments described, but are for explanation and understanding only. 
         [0020]      FIG. 5  shows a voltage rail generation circuit  30  according to one embodiment of this invention. The circuit includes a single flying capacitor FC, eight switches S 1  to S 8 , and three storage capacitors SC 75 , SC 50 , and SC 25 . The first switch S 1 , third switch S 3 , fifth switch S 5 , and seventh switch S 7  are coupled to a first terminal of the flying capacitor, and the second switch S 2 , fourth switch S 4 , sixth switch S 6 , and eighth switch S 8  are coupled to a second terminal of the flying capacitor. 
         [0021]    The first switch un/couples the first flying capacitor from/to a VDD voltage reference input terminal. The second switch un/couples the flying capacitor from/to a first voltage rail output terminal  75 P at which the circuit generates VDD*0.75. The third switch un/couples the flying capacitor from/to the first voltage rail terminal. The fourth switch un/couples the flying capacitor from/to a second voltage rail output terminal  50 P at which the circuit generates VDD*0.50. The fifth switch un/couples the flying capacitor from/to the second voltage rail output terminal. The sixth switch un/couples the flying capacitor from/to a third voltage rail output terminal  25 P at which the circuit generates VDD*0.25. The seventh switch un/couples the flying capacitor from/to the third voltage rail output terminal. And the eighth switch un/couples the flying capacitor from/to a ground voltage reference input terminal GND. 
         [0022]    A first storage capacitor SC 75  is coupled between the first voltage rail output terminal and ground. A second storage capacitor SC 50  is coupled between the second voltage rail output terminal and ground. And a third storage capacitor SC 25  is coupled between the third voltage rail output terminal and ground. These storage capacitors store the charge packets delivered by CF 1  and smooth the voltage at each respective supply voltage. 
         [0023]      FIGS. 6 through 9  illustrate the four states of the circuit of  FIG. 5 . During PHI 1 , the flying capacitor is coupled between VDD and the  75 P output terminal. During PHI 2 , the flying capacitor is coupled between the  75 P output terminal and the  50 P output terminal. During PHI 3 , the flying capacitor is coupled between the  50 P output terminal and the  25 P output terminal. And during PHI 4 , the flying capacitor is coupled between the  25 P output terminal and GND. Thus, at any moment in time, the flying capacitor carries a potential of VDD*0.25. The switches move this reference voltage around among the output terminals. 
         [0024]    The new circuit uses only a single flying capacitor, whereas the prior art required three flying capacitors to generate this same set of voltage rails. The new circuit generates N−1 supply rails, where N is the number of states (or switched positions) of the flying capacitor. Adding another voltage rail requires simply adding an additional pair of switches, an additional phase signal, and an additional storage capacitor. The single flying capacitor may, in some embodiments, be implemented as two or more smaller capacitors coupled in parallel, which is well known to be the functional equivalent of a single larger capacitor. In this context, “single” really means that the switches are all commonly coupled to the same one or more parallel flying capacitor(s). 
         [0025]    The prior art technique can be used to generate 2 M −1 voltage rails (in addition to the VDD and GND input reference voltages), where M is a positive integer, and requires 2 M −1 flying capacitors, 4*2 M −1 switches, 2 M −1 storage capacitors, and 2 switch control signals (which can be 1 non/inverted clock signal with dead time control). 
         [0026]    The technique of the present invention can be used to generate N voltage rails (in addition to the VDD and GND input reference voltages), where N is a positive integer greater than 2, and requires only 1 flying capacitor, 2*(N+1) switches, and N storage capacitors. It does, however, require N+1 switch control signals, because N+1 is the number of states (or switched positions) of the single flying capacitor. Fortunately, control signals are easy to add because they are done with small digital gates. The savings on the power switches is very important because the die area saved helps overall product cost. Also, the fact that fewer flying capacitors are used saves on pin count and external capacitor count which is also important for overall cost. 
         [0027]      FIG. 10  is a chart illustrating the results of a power efficiency simulation of the circuit of  FIG. 5 . The chart shows power efficiency (vertical axis) versus resistive load (horizontal axis), with the load driven by a 1.5v voltage rail generated at the  50 P terminal, and VDD set at 3.0v. The impedance of each switch was modeled as 0.25Ω. 
         [0028]    An additional benefit of this invention is the lowering of output impedance when the load is applied across two of the generated rails (rather than across one of the generated rails and GND). 
         [0029]      FIG. 11  is a chart showing the DC output impedance of the  75 P rail when the load is connected between an ideal 1.5v VDD and the  75 P terminal (at 2.25v). The simulation shows an impedance of ˜1.56Ω. 
         [0030]      FIG. 12  is a chart showing the DC output impedance of the  75 P rail when the resistive load is connected from the  75 P rail (at 2.25v) to the  25 P rail (at 0.75v). This simulation shows an output impedance of ˜1.07Ω, which is a 31.4% reduction versus the ˜1.56Ω impedance of  FIG. 11 . 
         [0031]    Pulse skipping techniques can be used in conjunction with the circuit of  FIG. 5 , equally as well as they can be used in conjunction with the prior art circuit of  FIG. 1 . 
         [0032]      FIG. 13  illustrates the extension of the technique of this invention to an arbitrary number N of generated voltage rails (in addition to the VDD and GND input reference voltages), where N is a positive integer greater than 2. The circuit  40  requires only 1 flying capacitor, 2*(N+1) switches, N storage capacitors, and N+1 switch control signals. 
         [0033]      FIG. 14  illustrates a rail generation system  50  according to yet another embodiment of this invention. The system includes five pairs of switches S 1 /S 2 , S 3 /S 4 , S 5 /S 6 , S 7 /S 8 , and S 9 /S 10 . A switch signal generator provides five non-overlapping switch enable signals SE 1  through SE 5 , each enabling a respective pair of the switches. The switch signal generator may be implemented as any suitable circuit, state machine, or other mechanism, which generates non-overlapping switch enable signals. 
         [0034]    The first switch of each pair couples the single, common flying capacitor to a unique high voltage rail, and the second switch of each pair couples the single, common flying capacitor to a unique low voltage rail. 
         [0035]    The low voltage rail generated by one switch pair serves as the high voltage rail for the next lower switch pair. The first switch pair receives VDD and generates lower rail R 1 . The second switch pair receives rail R 1  and generates lower rail R 2 . The third switch pair receives rail R 2  and generates lower rail R 3 . The fourth switch pair receives rail R 3  and generates lower rail R 4 . And the fifth switch pair receives rail R 4  and GND. In the illustrated case where there are five switch pairs, the generated rails are on VDD/5 spacing intervals, such that R 1 =VDD*0.8, R 2 =VDD*0.6, R 3 =VDD*0.4, and R 4 =VDD*0.2. 
         [0036]    Each switch pair, except the final one which is coupled to GND, has the output of its second switch coupled to GND through a dedicated storage capacitor SC 1  to SC 4 . 
       CONCLUSION 
       [0037]    Although the various embodiments of the invention have been discussed with respect to methodologies in which the switch enable signals are generated sequentially and serially and, therefore, the flying capacitor is jumped among the rail pairs in round robin fashion, in other embodiments (which may equally well be practiced using the circuitry shown in the drawings), the flying capacitor is jumped among the rail pairs in other manners. The switch enable signals need not necessarily be issued strictly in serial, sequential fashion, but may be issued in other orders, or randomly. The switch enable signals need not necessarily have the same duty cycle, nor the same frequency of issuance. 
         [0038]    When one component is said to be “adjacent” another component, it should not be interpreted to mean that there is absolutely nothing between the two components, only that they are in the order indicated. 
         [0039]    The various features illustrated in the figures may be combined in many ways, and should not be interpreted as though limited to the specific embodiments in which they were explained and shown. 
         [0040]    Although in various drawings there are specific numbers of rails actually illustrated, the invention may be practiced with any number of rails, each having their own load and their own storage capacitor. 
         [0041]    Those skilled in the art, having the benefit of this disclosure, will appreciate that many other variations from the foregoing description and drawings may be made within the scope of the present invention. Indeed, the invention is not limited to the details described above. Rather, it is the following claims including any amendments thereto that define the scope of the invention.