Abstract:
An integrated circuit voltage reference (V REF ) for MOS circuit utilization is supplied by the weighted difference amplification (30) of the voltages (V 1 , V 1  &#39;) developed by a pair of separate similar networks (10, 10&#39; or 100, 100&#39;) each of which comprises a base-emitter junction of a bipolar semiconductor transistor (T 1 ) whose emitter is connected to a first clocked voltage source (C 1 , C 2 , M 1 , M 2 ) in a feedback loop of a difference amplifier (A 1 ) and whose collector is connected to receive output of a second clocked voltage source (C 3 , C 4 , M 3 , M 4 ) and to deliver output to a first input terminal of the difference amplifier (A 1 ). In a preferred embodiment, a second input terminal of the difference amplifier (A 1 ) is supplied by the output voltage of an auxiliary voltage source (C 5 , C 6 , M 6 , M 7 , M 8 , M 9 ) which is in another feedback loop of this amplifier (A 1 ).

Description:
FIELD OF THE INVENTION 
     This invention relates to the field of semiconductor apparatus, and more particularly to MOS (metal oxide semiconductor) circuits for providing a voltage reference. 
     BACKGROUND OF THE INVENTION 
     Semiconductor integrated circuits often require a voltage supply or voltage reference circuit for providing a predetermined voltage level. The actual voltage level, however, as furnished by such a reference circuit undesirably tends to fluctuate during operation because of temperature variations in an underlying semiconductor body in which the circuit is integrated and because of voltage fluctuations in the power supply for the circuit. On the other hand, in the semiconductor art of analog-to-digital and digital-to-analog converter circuits, for example, a voltage reference is desirable which does not fluctuate in voltage level by more than typically about 0.005 volts or less. Therefore, steps must be taken to stabilize the reference circuit against temperature and power supply fluctuations. 
     In order to obtain a stable reference in either bipolar or complementary MOS (C-MOS) technology, the industry generally uses voltage references utilizing either the voltages associated with reverse breakdown phenomena in Zener diodes or the voltages provided by bandgap reference circuits. Such bandgap reference circuits are described, for example, in Analysis and Design of Analog Integrated Circuits, Paul R. Gray and Robert G. Meyer, at pp. 249-261. In N-MOS (or N-channel) technology (which uses a P-type semiconductor substrate) none of the above-mentioned voltage references is feasible. More specifically, Zener diode reverse breakdown phenomena cannot easily be used because all PN junctions are designed to withstand the highest possible reverse voltage available on the semiconductor chip in which the circuits are all integrated; hence these junctions cannot readily be driven into reverse breakdown. Moreover, known bandgap reference circuits cannot easily be used since they require constantly forward biased junctions which are not easily obtainable because the P-type substrate of an N-MOS integrated circuit is connected to the most negative potential in the system, and thus the requisite constantly forward biased junctions cannot easily be obtained. Accordingly, to implement either reverse breakdown Zener or bandgap reference circuits in N-MOS technology would require additional costly fabrication steps, which would impair the economic advantage in N-MOS technology. 
     It would therefore be desirable to have a voltage reference circuit which can readily be fabricated in N-MOS technology. 
     SUMMARY OF THE INVENTION 
     According to the invention, a voltage reference (V REF ) is furnished by weighted difference amplification (30) (FIG. 3) of the voltages (V 1 , V 1  &#39;) developed at the output terminals (11, 11&#39;) of difference amplifiers, (e.g., A 1 ) in a pair of separate networks (10, 10&#39; in FIG. 1; 100, 100&#39; in FIG. 4), each of said networks (e.g., 10 or 100) comprising a base-emitter PN junction of a semiconductor transistor device (T 1 ) whose emitter is connected to receive output of a first clocked voltage source (C 1 , C 2 , M 1 , M 2 , M 5 ) and whose collector is connected both to receive output of a second clocked voltage source (C 3 , C 4 , M 3 , M 4 ) and to deliver output of said transistor (T 1 ) to a first input terminal (+) of a difference amplifier (A 1 ), and the output terminal (12) of the difference amplifier (A 1 ) being connected to an input terminal (18) of the first clocked voltage source in order that voltage be supplied to said first clocked source by said difference amplifier (A 1 ). In a preferred embodiment (100), which isolates V REF  from the voltage supply V DD , a second input terminal (-) of said difference amplifier (A 1 ), of opposite polarity from said first input terminal (+) thereof, is connected to receive output of a third voltage source (C 5 , C 6 , M 6 , M 7 , M 8 , M 9 ) which is also supplied voltage by said difference amplifier (A 1 ). By properly selecting the weighting factors of the weighted amplification (30), the resulting voltage reference (V REF ) can also be made to be relatively stable against temperature fluctuations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     This invention may be better understood from the following detailed description when read in conjunction with the drawing in which: 
     FIG. 1 is a schematic circuit diagram of an electrical network for producing a first voltage (V 1 ) useful in a specific embodiment of the invention; 
     FIG. 2 illustrates a sequence of phases of clock voltages useful in the operation of the network of FIG. 1; 
     FIG. 3 is a diagram of a circuit for producing a voltage reference in accordance with the invention; and 
     FIG. 4 is a schematic circuit diagram of an electrical network for producing the first voltage (V 1 ) useful in a preferred specific embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a first network 10 which produces a first voltage V 1  at a first node 11. A second network 10&#39;, which is identical to the first network 10 except for the selection of different parameters for some or all of the various elements as described in more detail below, produces a second voltage V 1  &#39; at a second node 11&#39; (FIG. 3). These first and second nodes 11 and 11&#39; serve as input nodes of a weighted difference amplifier 30 (FIG. 3) in a voltage reference circuit 40 to produce, in accordance with the invention, the desired voltage reference V REF . This weighted difference amplifier 30 is typically formed by an operational amplifier A F , in combination with weighting capacitors C 7 , C 8 , C 9 , and C 10 , All these capacitors can advantageously be MOS capacitors. 
     As further shown in FIG. 1, MOSFET switching device elements M 1 , M 3 , and M 5  are controlled by a first clock pulse sequence φ 1  (FIG. 2) which periodically turns these devices &#34;on&#34; during repeated positive voltage pulse phases (N-MOS) technology); and MOSFET switching devices M 2  and M 4  are controlled by a second clock pulse sequence φ 2  which periodically turns these latter switching devices &#34;on&#34; during complementary (non-overlapping with φ 1 ) phases when the first sequence φ 1  turns &#34;off&#34; the devices M 1 , M 3  and M 5 . A bipolar transistor T 1 , whose base is grounded (&#34;zero&#34; substrate bias potential level), has its high current collector-emitter path connected between nodes 15 and 14. Node 15 serves as an output terminal of a first clocked voltage pulse source formed by C 1 , C 2 , M 1 , M 2  ; whereas node 14 serves as an output terminal of a second clocked pulse source formed by C 3 , C 4 , M 3  and M 4 . This transistor T 1  will be &#34;on&#34; and will pass emitter-collector current only when the base-emitter voltage V BE  exceeds a threshold V BE .th ; that is, when the emitter is more negative than about -0.6 volt in the usual case of silicon semiconductor. A positive polarity input terminal (+) of a difference amplifier A 1  is connected to node 14 while an output terminal of this amplifier A 1  is connected to the node 11. 
     Advantageously, the amplifier A 1  is an operational type amplifier, that is, of very high input impedance, and very high gain β: a voltage gain factor in the range of typically about 5 to 20 or more. An output terminal 13 of a voltage divider resistor R supplies an input voltage V R , a predetermined fraction of a supply voltage V DD , as input to a negative polarity input terminal (-) of the difference amplifier A 1 . 
     Typically, the amplifier A 1  is a MOSFET source follower amplifier; so that the MOSFET device of this amplifier together with the MOSFET devices M 1  . . . M 5 , the bipolar transistor T 1 , and the MOS capacitor C 1  . . . C 8  can be advantageously integrated in a single crystal semiconductor body as known in the art of integrated circuits. For proper operation, C 4  is selected to be much larger than C 3 , advantageously by a factor of 100 or more. 
     During a phase of operation when transistor devices M 1 , M 3  and M 5  controlled by the first clock sequence φ 1  are &#34;on&#34; and hence devices M 2  and M 4  controlled by the second clock sequence φ 2  are &#34;off&#34;, the top plate of capacitor C 1  (connected to node 17 between M 1  and M 2 ) is at potential V 1  and its bottom plate grounded. The top and bottom plates of C 1  then carry charges equal to ±C 1  V 1 , respectively, while both the plates of capacitor C 2  are grounded, so that these plates are thus completely uncharged. Thus the top plate of capacitor C 3  is then at potential V DD  while the top plate of C 4  (connected to node 14) is electrically floating because the base-emitter potential of the bipolar transistor T 1  then is zero and hence T 1  is then &#34;off&#34;. The top plate of C 3  will thus be charged to a value q 3  = C 3  V DD . During this phase also, the potential V 14  at node 14 is not significantly different from the potential V R  at node 13 because of the high gain β of the difference amplifier A 1  which will not allow V 14  to differ very much from V R . 
     During the next succeeding phase, the first clock φ 1  turns &#34;off&#34; the devices M 1 , M 3  and M 5 , while the second clock φ 2  turns &#34;on&#34; the devices M 2  and M 4 . Accordingly, node 17 between M 2  and M 1  is grounded while the top plate of C 2  (connected to nodes 15 and 16) is disconnected by M 5  from ground. Accordingly, the charge C 1  V 1  initially on C 1  distributes itself such that the charge on the top plate of C 2  becomes equal to q 2  where: 
     
         q.sub.2 V.sub.1 C.sub.1 C.sub.2 /(C.sub.1 +C.sub.2).       (1) 
    
     Thus, the potential V 16  at node 16 (between C 1  and C 2 ) becomes equal to V 16  =q 2  /C 2  or: 
     
         V.sub.16 =-V.sub.1 C.sub.1 /(C.sub.1 +C.sub.2).            (2) 
    
     Accordingly, a positive charge q 1  will flow through the transistor T 1  if V 12  is then more negative than V BE .th, the base-emitter threshold of T 1 . This charge q 1  will flow from the emitter of T 1  to the node 16, and hence a charge αq 1  will be transferred from the top plate of C 4  at node 14 to the collector of T 1 , where α denotes the collection efficiency of T 1  and ordinarily is nearly equal to unity. This charge αq 1  will thus be equal to 
     
         αq.sub.1 =(V.sub.BE.th -V.sub.16)(C.sub.1 +C.sub.2)  (3) 
    
     so long as V 16  is more negative than V BE .th (because during this &#34;on&#34; phase of φ 2  the capacitors C 1  and C 2  are thus also in parallel, looking from node 16 to ground). Meanwhile, another charge q 4  is transferred into C 4  from C 3  through M 4 , this charge being approximately of magnitude q 4  =C 3  (V CC  -V 14 ) since C 3  is much smaller than C 4 . The voltage of node 14 is substantially equal to V R  because of the high gain of the amplifier A 1  and because of a resulting overall negative feedback through C 1  and T 1  back to A 1  ; therefore this charge q 3  is substantially equal to: 
     
         q.sub.4 =C.sub.3 (V.sub.DD -V.sub.R).                      (4) 
    
     At equilibrium the voltage at node 14 remains unaffected by the transfer of charges αq 1  and q 4 , so that αq 1  =q 4  ; that is, at equilibrium: 
     
         α(V.sub.BE.th -V.sub.16)(C.sub.1 +C.sub.2)=C.sub.3 (V.sub.CC -V.sub.R).                                                (5) 
    
     Replacing V 16  by its value given by Equation 2: 
     
         αV.sub.1 C.sub.1 +αV.sub.BE.th (C.sub.1 +C.sub.2)=C.sub.3 (V.sub.DD -V.sub.R),                                      (6) 
    
     at equilibrium. Solving for V 1 , at equilibrium: 
     V 1  =V BE .th (C 1  +C 2 )/C 1  +(V DD  -V R )C 3  /αC 1 .                                          (7) 
     Thus, the first voltage V 1  produced by the first network 10 tends to the equilibrium value given by Equation 7. On the other hand, the second voltage V 1  &#39; (FIG. 3) produced by the second network 10&#39; (similar to the first network 10 except for different values of some or all respective parameters) will tend to: 
     
         V.sub.1 &#39;=V.sub.BE.th &#39;(C.sub.1 &#39;+C.sub.2 &#39;)/C.sub.1 &#39;+(V.sub.DD -V.sub.R &#39;)C.sub.3 &#39;/α&#39;C.sub.1 &#39;                             (8) 
    
     where the primed quantities denote elements in the second network 10&#39; similarly situated and interconnected, respectively, as corresponding unprinted elements in the first network 10. The weighted difference amplifier 30 (FIG. 3) thus is provided, after equilibrium is established in both networks 10 and 10&#39;, with an input of V 1  at node 11 given by Equation 7 and an input of V 1  &#39; at node 11&#39; given by Equation 8. 
     Clocked transistors M 10  and M 11  periodically discharged C 8  and C 9 , respectively, in order to reset periodically the amplifier A F . The desired reference V REF  is provided at the output terminal of the amplifier A F  in accordance with the relationship: 
     
         V.sub.REF =aV.sub.1 -bV.sub.1 &#39;-V.sub.os                   (9) 
    
     where V os  is an offset voltage of the amplifier A F , and where 
     
         a=C.sub.7 (C.sub.9 +C.sub.10)/C.sub.10 (C.sub.7 +C.sub.8)  (10) 
    
     and 
     
         b=C.sub.9 /C.sub.10.                                       (11) 
    
     The offset V os  can be removed, if desired, by a variety of known offset cancellation techniques, such as charging an auxiliary capacitor to V os  during the &#34;on&#34; phases of transistor M 10  and M 11 , and then connecting this capacitor in series between node 22 (between C 7  and C 8 ) and the positive input terminal of the amplifier A F . 
     It should be understood that the value of the parameters of the various elements in the first network 10 (FIG. 1) will, in general, be different from the corresponding elements in the network 10&#39;; in particular, the base-emitter voltage of the bipolar transistor T 1  &#39; in the second network 10&#39; should be at least slightly different from that of its counterpart bipolar transistor T 1  in the first network 10, as discussed more fully below. Of course, the various switching transistor device elements M 1  . . . M 5 , and M 1  &#39; . . . M 5  &#39; can all have the same parameters. It should also be understood that the desired value of V REF  is present at the output terminal of the amplifier A F  only when the transistors M 10  and M 11  are &#34;off&#34;, the output of A F  being equal to zero when these transistors are &#34;on&#34;; thus, for a steady (DC) output of V REF  known sample and hold techniques should be employed. 
     FIG. 4 shows a network 100 of the kind which can be used as an alternative to the network 10 or 10&#39; (or preferably both) in the circuits of FIG. 3. This network 100 is similar to the network 10 except for added elements C 5 , C 6 , C SM , M 6 , M 7 , M 8  and M 9  and an added resistor 43--all instead of the voltage divider R in network 10--for supplying V R  to the negative input terminal (-) of the difference amplifier A 1 . Accordingly, in the preferred embodiment, the network 100 replaces the network 10 in the circuit 30, while a network 100&#39;, constructed similarly to the network 100 except for the values of the parameters, likewise replaces the network 10&#39;. The added elements C 5 , C 6 , C SM , M 6 , M 7 , M 8  and M 9  form a third voltage souce means in the network 100, in order to provide the voltage V R  to the negative input terminal of the amplifier A 1  independently of the value of V DD  and hence to avoid the dependence of the ultimate output V REF  (FIG. 3) upon the instantaneous value of V DD . An added resistor device 43 provides a convenient current from the V DD  supply to the node 14, in order to provide an initial (&#34;start-up&#34;) voltage typically of the order of one-tenth microampere, eventually to provide an initial voltage at this the node 14, typically an initial voltage of about one volt or more, depending on the value of V 1  and the parameter of the circuit. In any event, the resistance of the device 43 is selected such that this device delivers a current equal to about only a few percent of the collector current of the transistor T 1  during operation. 
     The capacitor C SM  is placed in the network 100 for smoothing the input voltage V R  developed at an output terminal 42 of the third voltage means C 5 , C 6 , M 6 , M 7 , M 8  and M 9 . This voltage V R  is supplied by charge division and hence voltage division (of V 1 ) by capacitors C 5  and C 6 . More specifically, when φ 2  turns &#34;on&#34; the transistor M 6 , the capacitor C 5  is charged to V 1  while the capacitor C 6  is discharged through the transistor M 9  to ground. Subsequently, when φ 1  turns &#34;on&#34; the transistors M 7  and M 8 , the capacitors C 5  and C 6  are connected in parallel between ground and the negative input terminal of the difference amplifier A 1 . Consequently, the voltage V R  supplied to this negative input terminal of A 1  is equal to: 
     
         V.sub.R =V.sub.1 C.sub.5 /(C.sub.5 +C.sub.6).              (12) 
    
     In all other respects, i.e., except for the way in which V R  is generated, the network 100 operates in the same manner as discussed above in connection with the network 10. In the network 100, however, the voltage V 1  is given by the following variant of Equation 7 above: 
     
         V.sub.1 =V.sub.BE.th (C.sub.1 +C.sub.2)/C.sub.1 +(V.sub.1 -V.sub.R)C.sub.3 /αC.sub.1.                                          (13) 
    
     Now, using the value of V R  found in Equation 12: 
     
         V.sub.1 =V.sub.BE.th (C.sub.1 +C.sub.2)/C.sub.1 +V.sub.1 C.sub.6 C.sub.3 /αC.sub.1 (C.sub.5 +C.sub.6) 
    
     or: 
     
         V.sub.1 =mV.sub.BE.th                                      (14) 
    
     with: ##EQU1## Similarly, for the network 10&#39;; 
     
         V.sub.1 &#39;=m&#39;V.sub.BE.th &#39;                                  (16) 
    
     with: ##EQU2## 
     On the other hand, V 1  and V 1  &#39; are functions of temperature, since the corresponding base-emitter threshold voltages V BE .th and V BE .th &#39; (in T 1  and T 1  &#39;, in the networks 100 and 100&#39;) are themselves dependent on temperature. These base-emitter voltages are the same as the forward diode voltage drops of the respective base-emitter junctions and depend upon the respective current densities J and J&#39;, respectively, in the bipolar transistors T 1  and T 1  &#39;. Accordingly, the calculations of the patent application Ser. No. 262,461, filed on May 11, 1981 by Y. P. Tsividis (Case 2) entitled &#34;Temperature Stabilized Voltage Reference Circuit,&#34; Now U.S. Pat. No. 4,384,217, are applicable for selecting suitable parameters, particularly of the capacitances C 7 , C 8 , C 9  and C 10  for weighting the amplifier 30 (FIG. 3); except that (neglecting V os ) in the present case: 
     
         V.sub.REF =aV.sub.1 -bV.sub.1 &#39;=amV.sub.BE.th -bm&#39;V.sub.BE.th &#39;(18) 
    
     where a and b are the weighting factors given by Equations 10 and 11 above. 
     Now, the base-emitter thresholds V BE .th and V BE .th &#39; are functions of temperature and their values at room (operating) temperature are to be used in Equation 18. Accordingly, the conditions on am and bm&#39; can be found in a similar manner as in the above-mentioned Tsividis patent application: ##EQU3## with: 
     
         V.sub.REF =hV.sub.xo                                       (21) 
    
     where V xo  is the linearly extrapolated value from room temperature to absolute zero of V Be .th, and also that of V Be .th &#39; , which is the same extrapolated value as that of V Be .th. For silicon V xo  is equal to about 1.2 volts, although it may not be exactly the same to two decimal places as in the aforementioned Tsividis patent application, owing to the temperature-dependent current source therein. As further noted in that patent application, in order to achieve reasonable matching and semiconductor area economy, a and b should both be less than about a hundred. 
     As explained in the aforementioned Tsividis patent application, V BE .th and V Be .th &#39; are functions of temperature, V BE .th (T) and V BE .th &#39; (T). Extrapolating linearly the values of BE.th (T) and V BE .th &#39; (T) from T=T x  (with say, T x  =room temperature) to T=0° K., it is found that these linearly extrapolated values are equal to the same value denoted by V xo . The difference (V BE .th -V BE .th &#39;) of the base-emitter voltages at room temperature of the transistors T 1  and T 1  &#39; in the networks 100 and 100&#39; is obtained by using different current densities in those transistors T 1  and T 1  &#39;: the higher the current density, the higher the base-emitter voltage in accordance with the relationship: 
     
         V.sub.BE.th -V.sub.BE.th &#39;=(kT/q) ln(J/J&#39;).                (22) 
    
     These current densities, J and J&#39;, are proportional to the collector-base charge transfer q 4  given by Equation 4 above for the network 10. For the network 100, this collector-base charge q 4  is given by: 
     
         q.sub.4 =C.sub.3 (V.sub.1 -V.sub.R)=C.sub.3 V.sub.1 /(1+C.sub.5 /C.sub.6). (23) 
    
     Since the current density J in the transistor T 1  is proportional to q 4  and inversely proportional to the base-emitter junction area A in the transistor T 1 , the base-emitter thresholds V BE .th and V BE .th &#39; can be made to differ, in accordance with Equation 22, by as much as a tenth of a volt or so, while further selecting C 1  =C 1  &#39;, C 4=C   4  &#39;, C 5  =C 5  &#39;, and C 6  =C 6  &#39;, and while making the ratio (A&#39;/A) of base-emitter junction areas of T 1  and T 1  &#39; significantly different from unity (but not more than about a hundred for reasonable device areas). Conversely, instead of this ratio for A/A&#39;, select A/A&#39; equal to unity, and select suitable ratios for the capacitances or preferably select suitable values simultaneously for both junction area ratio and capacitance ratios to obtain minimum overall device area. 
     On the other hand, since V 1  is inherently less than V DD  (FIG. 1, and implicitly in FIG. 4 also), it follows from Equation 14 that m should be selected to be less than V DD  /V BE .th. Moreover, since V DD  is ordinarily equal to about 5 volts and V BE .th is equal to about 0.6 volts (to within about 0.1 volt at room temperature for reasonable current densities), it thus follows that m should be selected to be less than about 5/0.6=8. Similarly, m&#39; should likewise be selected to be less than about 8. Setting m and m&#39; to be equal to some convenient value (less than 8) imposes a condition (Equation 15) among the capacitors C 1 , C 2 , C 3 , C 5  and C 6  and a condition (Equation 17) among C 1  &#39;, C 2  &#39;, C 3  &#39;, C 5  &#39; and C 6  &#39;; both of these conditions are easily satisfied, for example, by choosing the capacitors C 1  =C 2  =C 3  =C 5  =C 6  and C 1  &#39;=C 2  &#39;=C 3  &#39;=C 5  &#39;=C 6  &#39;, in which case it follows from Equations 15 and 17 that m=4α/(2α-1) and that m&#39;=4α&#39;/(2α&#39;-1), where α and α&#39; (of transistors T 1  and T 1  &#39;) are both approximately equal to unity; so that m and m&#39; are then both approximately equal to 4. 
     As an illustrative example, to obtain a voltage reference V REF  of about 1.2 volts (less an offset V os , if any), according to Equation 21, we have h=1 since V xo  is also about 1.2 volts in silicon technology. Since both V BE .th and V BE .th &#39; are approximately 0.6 volt (to within about 0.1 for reasonable base-emitter junction areas in silicon), from the conditions that a should be less than about 100 and that m is equal to about 4, it follows from Equations 19 and 20 that V BE .th -V BE .th &#39; should be greater than about 0.6/4×100 or 0.0015 volt. Hence, ln(J/J&#39;) from Equation 22 should be greater than about 0.0015/0.026=0.06 at room temperature (about 300° K.); hence the base-emitter current density ratio itself (J/J&#39;) should be greater than about exp (0.06) or about 1.06 at room temperature. The required values of am and bm&#39; can then be calculated from Equations 19 and 20; and finally a and b can be calculated for the given choice of m=m&#39;=4. 
     Similarly, for a reference V REF  of about 6 volts, i.e., for the base h=5, the quantity (V BE .th -V   BE .th &#39;) should be greater than about 5×0.6/4×100=0.0075, and ln(J/J&#39;) greater than about 0.0075/0.026=0.29 at room temperature; and hence (J/J&#39;) should be greater than about e 0 .29 or about 1.33 at room temperature. 
     All of the MOSFETs in the networks 10 or 100 and 30 can be N-channel transistor devices or alternatively P-channel devices. The entire voltage reference circuit 40 can thus be integrated in a single silicon body in accordance with ordinary semiconductor integrated circuit techniques. 
     Although the invention has been described in detail with respect to specific embodiments, various modifications can be made without departing from the scope of the invention. For example, φ 1  and φ 2  controlling M 3  and M 4  (FIGS. 1 or 4) can be interchanged and likewise M 7  and M 8  (FIG. 4) can be controlled by φ 2  while M 6  and M 9  are controlled by φ 1  ; also M 1  and M 11  can be controlled by φ 2  (or some other suitable periodic clock) instead of φ 1 .