Abstract:
A digital imaging system generates a composite video signal and the carrier frequency of a desired television channel is generated internal to the imager integrated circuit. The carrier frequency is then amplitude modulated with the composite video signal by either digital or analog means located on-chip. Thus, a radio frequency signal that can be picked up by conventional television receivers is directly synthesized on-chip to provide a wireless video link.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The subject invention relates generally to signal transmission and more particularly to a method and apparatus for in-chip synthesis of a radio frequency (RF) video signal for transmission to remote sources. 
     2. Description of Related Art 
     It has appeared desirable to the inventor to provide a wireless video link to permit the signal generated by video imaging circuitry to be picked up by television receivers at remote locations. This can be useful when the convenience of wireless connection is desired, or the video imaging circuitry (camera) itself is at a remote location such as at the top of a power pole or deep inside a piece of machinery. 
     SUMMARY OF THE INVENTION 
     According to the invention, a digital imaging system generates a composite video signal and the carrier frequency of the desired television channel is generated internal to the imager integrated circuit (ASIC). The carrier frequency is then amplitude modulated with the composite video signal by either digital or analog means located on-chip. Thus, a radio frequency signal that can be picked up by conventional television receivers is directly synthesized on-chip to provide a wireless video link. If desired, the carrier frequency may also be employed to clock the digital imaging system. 
     The invention thus provides a monolithic solution admirably suited for VLSI implementation, which eliminates what would normally be a cumbersome multipackage design. The invention can provide even further system simplification in certain embodiments only one oscillator need be used. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The present invention, both as to its organization and manner of operation, together with further objects and advantages, may best be understood by reference to the following description of a preferred embodiment thereof taken in connection with the accompanying drawings, of which: 
     FIG. 1 is a circuit block diagram illustrating a first embodiment according to the invention; 
     FIG. 2 is a circuit block diagram illustrating a second embodiment according to the invention; 
     FIG. 3 illustrates a first balanced modulator usable in the embodiment of FIG. 2; and 
     FIG. 4 illustrates a second balanced modulator usable in the embodiment of FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor of carrying out his invention. Various modifications, however, will remain readily apparent to those skilled in the art. 
     An illustrative embodiment of the invention is shown in FIG.  1 . According to the circuit of FIG. 1, an imager circuit  15  outputs a composite video signal on a line  19  to a digital multiplier  21 . A system clock  17  supplies a master clock frequency ω RF  on a line  16  to the imager circuit and on a line  18  to the multiplier  21  and to a digital-to-analog converter (DAC) circuit  25 . The system master clock frequency ω RF  is set at the desired carrier frequency for a radio transmission of the composite video signal. Thus, the frequency ω RF  on line  18  is amplitude modulated by the composite video signal on signal line  19 , and the amplitude modulated signal is supplied over line  20  to the digital analog converter  25 . The digital analog converter  25  outputs an analog RF signal on line  24  comprising the composite video signal at the carrier frequency. 
     According to the embodiment of FIG. 1, all of the circuitry  15 ,  17 ,  21 ,  25  is located within the boundary  11  of a single integrated circuit. The integrated circuit is preferably fabricated according to VLSI techniques, for example, implemented in CMOS. The imager circuit  15  would typically include an array of photo detectors and suitable buffering and multiplexing circuitry, as known in the art. Thus, according to the embodiment of FIG. 1, a system clock at the carrier frequency is amplitude modulated by digital means using a digital multiplier feeding a high speed DAC. 
     According to the embodiment of FIG. 2, the composite video signal on the signal line  19  is applied to one input of a balanced modulator  29 , while the radio frequency clock signal on line  18  is applied to a second input of the modulator  29 . In this manner, the carrier frequency ω RF  is amplitude modulated by analog means, using balanced modulator  29 . Again, all of the circuitry  15 ,  17 ,  19  is located within the boundary  13  of a single integrated circuit. Again, the integrated circuit may be fabricated using VLSI CMOS technology. 
     FIG. 3 illustrates one embodiment of a balanced modulator  29  particularly adapted to be implemented in VLSI CMOS. The balanced modulator circuit per se is known in the art and is referred to as a Gilbert Cell. As is shown in FIG. 3, the base band signal BB is applied to respective nodes  35 ,  37 , which constitute the respective gates of transistors Q 5  and Q 6 . Respective lower legs (sources) of the transistors Q 5 , Q 6  are joined together and connected to ground, while their respective opposite upper legs (drains) are connected to respective junction points of the lower legs of respective pairs of transistors Q 1 , Q 2 ; Q 3 , Q 4 . The gate of the transistor Q 1  receives the carrier frequency ω RF  while the gate of the transistor of Q 4  receives the carrier frequency 180° out of phase, i.e., {overscore (ω)} RF . The upper legs of the transistors Q 2  and Q 3  are cross-connected to the upper legs of the transistors Q 4  and Q 1 . The gates of the transistors Q 2  and Q 3  are connected together. The circuit of FIG. 3 is differential in nature, and provides a differential output to the antenna indicated as R, R respectively, where R is the antenna impedance at the carrier frequency which may be, for example, 200 ohms. The antenna per se is located external to the chip. 
     FIG. 4 illustrates a second embodiment of the balanced modulator  29 , which is again per se a conventional alternative embodiment balanced modulator for CMOS VLSI implementation. In this embodiment, transistors Q 7  and Q 8  are serially connected, as are transistors Q 9  and Q  10 . The lower legs of the transistors Q 8  and Q  10  are connected together and receive one side of the baseband input BB, i.e., the composite video signal. The upper legs of the transistors Q 7  and Q 9  are connected together and receive the opposite side of the baseband composite video signal input BB. The gates of the transistors Q 7  and Q 10  receive the carrier frequency input ω RF  while the gates of the transistors Q 8  and Q 9  receive the carrier frequency shifted in phase by  180 , i.e., {overscore (ω)} RF . The output to the antenna appears at terminals  40 ,  41 . Terminal  40  is the junction of the upper leg of the transistor Q 8  with the lower leg of the transistor Q 7 , while terminal  41  is the juncture of the upper leg of the transistor Q 10  with the lower leg of the transistor Q 9 . 
     FIGS. 1 and 2 show the same system clock  17  supplying the frequency ω RF  to the imager circuit  15 . In other embodiments a separate clock circuit could be used to clock the imager circuit  15 . The clock ω RF  can also be subdivided for that purpose. Those skilled in the art will appreciate that clock circuit  17  comprises only that clock circuitry suitable for CMOS VSLI fabrication with a suitable crystal and tank circuit typically located off-chip. 
     Those skilled in the art will appreciate that various adaptations and modifications of the just-described preferred embodiment can be configured without departing from the scope and spirit of the invention. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein.