Abstract:
A system on chip (SoC) includes a control circuit configured to determine whether a requested operating mode is one of a functional mode and a monitoring mode. The control circuit is configured to provide a request signal to at least one clock circuit to request at least one clock signal and selectively output one of the at least one clock signal in response to at least one acknowledgment signal received from the at least one clock circuit, when the requested operating mode is the functional mode. The control circuit is configured to selectively output one of the at least one clock signal without providing the request signal, when the requested operating mode is the monitoring mode.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/286,873 filed on Jan. 25, 2016, U.S. Provisional Patent Application No. 62/286,860 filed on Jan. 25, 2016 in the United States Patent and Trademark Office, Korean Patent Application No. 10-2017-0010945 filed on Jan. 24, 2017 in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2017-0010943 filed on Jan. 24, 2017 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference in their entireties herein. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to a semiconductor device, a semiconductor system, and a method of operating the semiconductor device. 
         [0004]    2. Discussion of Related Art 
         [0005]    A system-on-chip (SoC) may include one or more intellectual property (IP) blocks, a clock management unit (CMU), and a power management unit (PMU). The CMU may provide clock signals to one or more of the IP blocks, and may stop providing clock signals to the IP blocks that are not running, thereby reducing unnecessary waste of resources in a system employing the SoC. 
         [0006]    To adjust the provision of clock signals, various clock sources included in the CMU may be controlled by software using a special function register (SFR). However, the response speed may be poor when the provisioning of clock signals is performed using software. Thus, there is a need for a hardware device and a method of controlling such a hardware device that can be used to provisional clock signals. 
       SUMMARY 
       [0007]    According to an exemplary embodiment of the inventive concept, a system on chip (SoC) includes a control circuit configured to determine whether a requested operating mode is one of a functional mode and a monitoring mode. The control circuit is configured to provide a request signal to at least one clock circuit to request at least one clock signal and selectively output one of the at least one clock signal in response to at least one acknowledgment signal received from the at least one clock circuit, when the requested operating mode is the functional mode. The control circuit is configured to selectively output one of the at least one clock signal without providing the request signal, when the requested operating mode is the monitoring mode. 
         [0008]    According to an exemplary embodiment of the inventive concept, a clock signal output circuit includes a clock multiplexing circuit configured to receive a plurality of clock signals from a plurality of clock components and a logic circuit. The logic circuit outputs a first request signal to the clock multiplexing circuit when a current mode is set to a functional mode. The clock multiplexing circuit outputs a second request signal to the clock components in response to the first request signal, and outputs one of the clock signals after receiving at least one acknowledgement signal from at least one of the clock components. The clock multiplexer outputs one of the clock signals without providing the second request signal when the current mode is set to a monitoring mode. 
         [0009]    According to an exemplary embodiment of the inventive concept, a clock signal output circuit includes a clock dividing circuit configured to perform a dividing operation on a clock signal output by a clock component to generate a divided clock signal and a logic circuit. The logic circuit outputs a first request signal to the clock dividing circuit when a current mode is set to a functional mode. The clock dividing circuit outputs a second request signal to the clock component in response to the first request signal, and outputs the divided clock signal after receiving an acknowledgement signal from the clock component. The clock dividing circuit outputs the divided clock signal without providing the second request signal when the current mode is set to a monitoring mode. 
         [0010]    According to an exemplary embodiment of the inventive concept, a method of operating a system on chip (SoC) includes: determining, by a control circuit of the SoC, whether to operate in one of a functional mode and a monitoring mode; when the control circuit determines to operate in the functional mode, providing, by the control circuit, a request signal to at least one clock circuit of the SoC; and outputting, by the control circuit, one of a plurality of clock signals output by the at least one clock circuit after receiving at least one acknowledgement signal from the at least one clock circuit, when the control circuit determines to operate in the monitoring mode, outputting, by the control circuit, one of the plurality of clock signals without providing the request signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which: 
           [0012]      FIG. 1  is a schematic diagram of a semiconductor device according to an exemplary embodiment of the present inventive concept; 
           [0013]      FIG. 2  is a schematic diagram of a clock signal output circuit according to an exemplary embodiment of the present inventive concept; 
           [0014]      FIG. 3  is a schematic diagram illustrating a method of operating the clock signal output circuit according to an exemplary embodiment of the present inventive concept; 
           [0015]      FIG. 4  is a schematic diagram illustrating a method of operating the clock signal output circuit according to an exemplary embodiment of the present inventive concept; 
           [0016]      FIG. 5  is a schematic diagram illustrating a method of operating the clock signal output circuit according to an exemplary embodiment of the present inventive concept; 
           [0017]      FIG. 6  is a schematic diagram illustrating a method of operating the clock signal output circuit of according to another embodiment of the present disclosure; and 
           [0018]      FIG. 7  is a block diagram of a semiconductor system to which a semiconductor device and a method of operating the semiconductor device according to embodiments of the present inventive concept can be applied. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]      FIG. 1  is a schematic diagram of a semiconductor device  1  according to an exemplary embodiment of the present inventive concept. 
         [0020]    Referring to  FIG. 1 , the semiconductor device  1  according to the present embodiment includes a clock management unit (CMU)  100 , intellectual property (IP) blocks  200  and  210 , and a power management unit (PMU)  300 . In an embodiment, an IP block is an IP core or reusable unit of logic or chip layout that is the intellectual property of one party. In an embodiment, each of the IP blocks include a processor, a graphic processor, a memory controller, and input and output interface block, etc. 
         [0021]    The PMU  300  controls a power supply to the semiconductor device. For example, when the semiconductor device enters a standby mode, the PMU  300  cuts off power supply to the SoC by turning off a power control circuit. Here, the PMU  300  continuously consumes power. However, since the power consumed by the PMU  300  is far smaller than that consumed by the entire semiconductor device, the power consumption of the semiconductor device is significantly reduced in the standby mode. The PMU  300  may cut off power supply to the CMU  100  if none of the IP blocks  200  and  210  have made a request for a clock signal within a pre-defined period of time. The semiconductor device  1  may be implemented as a system-on-chip (SoC) in various embodiments of the present disclosure, but the present inventive concept is not limited thereto. 
         [0022]    The CMU  100  provides clock signals to the IP blocks  200  and  210 . In the present embodiment, the CMU  100  includes clock components  120   a ,  120   b ,  120   c ,  120   d ,  120   e ,  120   f ,  120   g , channel management circuits  130  and  132 , and a CMU controller  110 . The clock components  120   a  through  120   g  generate clock signals that are to be provided to the IP blocks  200  and  210 , and the channel management circuits CM  130  and  132  are disposed between the clock components  120   f  and  120   g  and the IP blocks  200  and  210  to provide communication channels CH between the CMU  100  and the IP blocks  200  and  210 . The CMU controller  110  provides clock signals to the IP blocks  200  and  210  using the clock components  120   a  through  120   g.    
         [0023]    In an embodiment of the present inventive concept, the communication channels CH provided by the channel management circuits  130  and  132  are implemented to follow Low Power Interface (LPI), Q-Channel Interface or P-Channel Interface of ARM Ltd. However, the present inventive concept is not limited thereto, and the communication channels CH can also be implemented to follow a different communication protocol. 
         [0024]    The clock components  120   a  through  120   g  include clock sources (CS)  124   a ,  124   b ,  124   c ,  124   d ,  124   e ,  124   f ,  124   g  and clock control circuits (CC)  122   a ,  122   b ,  122   c ,  122   d ,  122   e ,  122   f ,  122   g  which control the clock sources  124   a  through  124   g , respectively. The clock sources  124   a  through  124   g  may include, for example, a multiplexer (MUX) circuit, a clock dividing circuit, a shortstop circuit, and a clock gating circuit. 
         [0025]    The clock components  120   a  through  120   g  form a parent-child relationship with each other. In the present embodiment, the clock component  120   a  is a parent of the clock component  120   b , and the clock component  120   b  is a child of the clock component  120   a  and a parent of the clock component  120   c . In addition, the clock component  120   e  is a parent of two clock components  120   f  and  120   g , and the clock components  120   f  and  120   g  are children of the clock component  120   e . In the present embodiment, the clock component  120   a  located closest to a phase locked loop (PLL) is a root clock component, and the clock components  120   f  and  120   g  located closest to the IP blocks  200  and  210  are leaf clock components. The parent-child relationship is also, inevitably, formed between the clock control circuits  122   a  through  122   g  and between the clock sources  124   a  through  124   g  according to the parent-child relationship between the clock components  120   a  through  120   g.    
         [0026]    The clock control circuits  122   a  through  122   g  exchange a clock request REQ and an acknowledgement ACK for the clock request REQ between a parent and a child and provide clock signals to the IP blocks  200  and  210 . The first clock control circuit  122   a  (i.e., the root clock component), which receives a clock request REQ having an activated level (e.g., second logic level) from the clock control circuit  122   b  enables the first clock source  124   a  and transmits an acknowledgement ACK to the second clock control circuit  122   b . The second clock control circuit  122   b  enables the second clock source  124   b  in response to receipt of the ACK from the first clock control circuit  122   a , and transmits an ACK to the third clock control circuit  122   c . The process repeats with the third, fourth, and fifth clock control circuits  122   c - 122   e.    
         [0027]    If the IP block  200  does not need a clock signal, for example, if the IP block  200  needs to be in a sleep state, the CMU  100  stops providing the clock signal to the IP block  200 . 
         [0028]    Specifically, the channel management circuit  130  transmits to the IP block  200  a first signal indicating that it will stop providing a clock signal under the control of the CMU  100  or the CMU controller  110 . The IP block  200  which receives the first signal transmits to the channel management circuit  130  a second signal indicating that the provision of the clock signal can be stopped after the completion of an operation being processed. The channel management circuit  130  which receives the second signal from the IP block  200  requests the clock component  120   f , i.e., its parent to stop providing the clock signal. 
         [0029]    In an example, if the communication channel CH provided by the channel management circuit  130  follows Q-Channel Interface, the channel management circuit  130  transmits a QREQn signal having a first logic value (e.g., logic low, hereinafter indicated by reference character “L”) to the IP block  200  as the first signal. Then, when receiving a QACCEPTn signal having the first logic value from the IP block  200  as the second signal, the channel management circuit  130  transmits a clock request REQ having the first logic value to the clock component  120   f . In this case, the clock request REQ having the first logic value is a “clock provision stop request.” 
         [0030]    The clock control circuit  122   f  which receives the clock request REQ (i.e., the clock provision stop request) having the first logic value from the channel management circuit  130  stops providing a clock signal by disabling the clock source  124   f  (e.g., the clock gating circuit). Accordingly, the IP block  200  can enter a sleep mode. In this process, the clock control circuit  122   f  may provide an acknowledgement ACK having the first logic value to the channel management circuit  130 . However, it should be noted that even if the channel management circuit  130  receives the acknowledgement ACK having the first logic value after transmitting the clock provision stop request having the first logic value, it does not guarantee the stoppage of clock provision by the clock source  124   f . The acknowledgement ACK merely means the clock control circuit  122   f  is aware of the fact that the clock component  120   f  (i.e., a parent of the channel management circuit  130 ) no longer needs to provide a clock signal to the channel management circuit  130 . 
         [0031]    Meanwhile, the clock control circuit  122   f  of the clock component  120   f  transmits a clock request REQ having the first logic value to the clock control circuit  122   e  of the clock component  120   e  which is its parent. If the IP block  210  also does not need a clock signal, for example, if the clock control circuit  122   e  receives the clock provision stop request from the clock control circuit  122   g , the clock control circuit  122   e  stops providing the clock signal by disabling the clock source  124   e  (e.g., the clock dividing circuit). Accordingly, the IP blocks  200  and  210  can enter the sleep mode. 
         [0032]    The above operation may be performed in the same way for other clock control circuits  122   a  through  122   d.    
         [0033]    Although the clock control circuit  122   f  of the clock component  120   f  transmits the clock request REQ having the first logic value to the clock control circuit  122   e  of the clock component  120   e  which is its parent, if the IP block  210  is running, the clock control circuit  122   e  cannot disable the clock source  124   e . Only when the IP block  210  no longer needs a clock signal, can the clock control circuit  122   e  disable the clock source  124   e  and transmit a clock request REQ having the first logic value to the clock control circuit  120   d  which is its parent. That is, the clock control circuit  122   e  can disable the clock source  124   e  only when receiving the clock provision stop request from both of the clock control circuits  122   f  and  122   g.    
         [0034]    When the IP blocks  200  and  210  are in the sleep state, all of the clock sources  124   a  through  124   f  may be disabled. Then, when the IP block  200  enters the running state, the CMU  100  resumes providing clock signals to the IP blocks  200  and  210 . 
         [0035]    The channel management circuit  130  transmits a clock request REQ having a second logic value (e.g., logic high, hereinafter indicated by reference character “H”) to the clock control circuit  122   f  of the clock component  120   f  which is its parent and waits for an acknowledgement ACK from the clock control circuit  122   f . Here, the clock request REQ having the second logic value is a “clock provision request,” and the acknowledgement ACK for the clock provision request indicates that clock provision by the clock source  124   f  has been resumed. The clock control circuit  122   f  cannot immediately enable the clock source  124   f  (e.g., the clock gating circuit) but waits for the provision of a clock signal by its parent. 
         [0036]    Then, the clock control circuit  122   f  transmits a clock request REQ (i.e., the clock provision request) having the second logic value to the clock control circuit  122   e  which is its parent and waits for an acknowledgement ACK from the clock control circuit  122   e . This operation may be performed in the same way for the clock control circuits  122   a  through  122   d.    
         [0037]    The clock control circuit  122   a , i.e., the root clock component which receives a clock request REQ having the second logic value from the clock control circuit  122   b  enables the clock source  124   a  (e.g., the MUX circuit) and transmits an acknowledgement ACK to the clock control circuit  122   b . After the clock sources  124   b  through  124   e  are enabled sequentially in this way, the clock control circuit  122   e  finally transmits to the clock control circuit  122   f  an acknowledgement ACK notifying that the clock provision by the clock source  124   e  has been resumed. The clock control circuit  122   f  which receives the acknowledgement ACK provides a clock signal to the IP block  200  by enabling the clock source  124   f  and provides an acknowledgement ACK to the channel management circuit  130 . 
         [0038]    The clock control circuits  122   a  through  122   g  operate in a full handshake way (e.g., synchronous handshaking) in which a clock request REQ and an acknowledgement ACK for the clock request REQ are exchanged between a parent and a child. Accordingly, the clock control circuits  122   a  through  122   g  can control clock signals provided to the IP blocks  200  and  210  by controlling the clock sources  124   a  through  124   g  in a hardware-wise manner. 
         [0039]    The clock control circuits  122   a  through  122   g  may transmit a clock request REQ to their parents or control the clock sources  124   a  through  124   g  by operating on their own or under the control of the CMU controller  110 . In an embodiment of the present inventive concept, the clock control circuits  122   a  through  122   g  respectively include finite state machines (FSMs) which control the clock sources  124   a  through  124   g  according to a clock request REQ exchanged between a parent and a child. 
         [0040]    In the present embodiment, the semiconductor device  1  further includes a clock signal output circuit  140  and an output pin  150 . The clock signal output circuit (CO)  140  receives a plurality of clock signals CLK from the clock sources  124   a  through  124   f  and outputs any one clock output signal CLK_OUT of the clock signals CLK to the output pin  150 . The clock output signal CLK_OUT output from the output pin (I/ 0 )  150  may be used to monitor the clock signals CLK or may be functionally used to drive a device provided outside the semiconductor device  1 . The clock signal output circuit  140  may either monitor the clock signals CLK or output a particular one of the clock signals CLK according to the state of an input operating mode control signal MS. In an embodiment, the clock output circuit  140  is driven by a reference clock signal of a different clock domain than the clock signals it receives to output. In an embodiment, the components within the clock output circuit  140  are driven by the reference clock signal. 
         [0041]    While  FIG. 1  shows a tree of clock components including a cascade of five clock components and two leaf clock components, the inventive concept is not limited thereto. In alternative embodiments, one or more of these clock components may be omitted. In a first embodiment, only the first clock component  120   a  and the first leaf clock component  120   f  are present, the second-fifth clock components  120   b - 120   e  are omitted, and the second leaf clock component  120   g  is omitted. In a second embodiment, only the second clock component  120   b  and the first leaf clock component  120   f  are present, the first clock component  120   a  is omitted, the third-fifth clock components  120   c - 120   e  are omitted, and the second leaf clock component  120   g  is omitted. In a third embodiment, only the third clock component  120   c  and the first leaf clock component  120   f  are present, the first-second clock components  120   a - b  are omitted, the fourth-fifth clock components  120   d - e  are omitted, and the second leaf clock component  120   g  is omitted. In a fourth embodiment, only the fourth clock component  120   d  and the first leaf clock component  120   f  are present, the first-third clock components  120   a - c  are omitted, the fifth clock component  120   e  is omitted, and the second leaf component  120   g  is omitted. In a fifth embodiment, only the fifth clock component  120   e  and the first leaf clock component  120   f  are present, the first-fourth clock components  120   a - 120   d  are omitted, and the second leaf clock component  120   g  is omitted. These embodiments may be varied further with various other combinations. For example, in a sixth embodiment, the first-second clock components  120   a - 120   b  are present, the first leaf clock component clock  120   f  is present, the third-fifth clock components  120   b - e  are omitted, and the second leaf clock component  120   g  is omitted. 
         [0042]    In an exemplary embodiment, the clock component  120   a  is a PLL controller that receives a constant or variable frequency signal from an oscillator OSC or a PLL signal output by a PLL, and outputs one of the two received signals based on a certain condition. In an embodiment, when the PLL is powered down, the first clock component  120   a  switches from the PLL to the OSC. When the components need the PLL signal, the PLL controller outputs the PLL signal. When the components need the oscillator signal, the PLL controller outputs the oscillator signal. When a component using an output of the PLL is not present, in an embodiment of the inventive concept, the PLL controller turns off the PLL. In an alternate embodiment, when the component using the output of the PLL is not present, the PLL controller automatically controls the PLL to enter a bypass mode. In another alternate embodiment, when the component using the output of the PLL is not present, the PLL controller does not affect the operation of the PLL at all. 
         [0043]    In an exemplary embodiment of the inventive concept, the clock component  120   b  is a clock multiplexer (MUX) unit that receives a first clock signal CLK 1  output from clock component  120   a  and a second clock signal CLK 2  that may be provided from an external source such as an external CMU. 
         [0044]    In an exemplary embodiment, the clock component  120   c  is a clock dividing unit such as a clock divider circuit (e.g., a frequency dividing circuit). The clock divider circuit takes an input signal of an input frequency and generates an output signal with an output frequency of the input frequency divided by a clock division ratio. For example, the division ratio may be an integer greater than 1. 
         [0045]    In an exemplary embodiment, the clock component  120   d  is a shortstop unit (e.g., shortstop circuit). In an embodiment, the shortstop unit provides a clock signal with a plurality of pulses during a first period, stops these pulses during a second period after the first period, and resumes the pulses during third period after the second period. 
         [0046]    In an exemplary embodiment of the inventive concept, each of the leaf clock components  120   f  and  120   g  is a clock gating unit. In an embodiment where the leaf clock components  120   f  and  120   g  are clock gating units, each component includes a clock gate circuit. 
         [0047]      FIG. 2  is a schematic diagram of a clock signal output circuit  140  according to an exemplary embodiment of the present inventive concept. 
         [0048]    Referring to  FIG. 2 , the clock signal output circuit  140  according to the present embodiment includes first and second clock components  141   a  and  141   b , an FSM  143 , and a clock gating circuit  145 . The FSM  143  may be implemented by one or more logic circuits. In an embodiment, either the first clock component  141   a  or the second clock component  141   b  is omitted. When the first clock component  141   a  is omitted, clock source  144   b  only receives a single clock signal. In an embodiment, the first clock component  141   a  is driven by a reference clock signal having a different clock domain (e.g., different frequency) than the clock signals it receives (i.e., CLK[n: 0 ]). In an embodiment, the second clock component  141   b  is driven by a reference clock signal having a different clock domain than the clock signal it receives from clock source  144   a.    
         [0049]    The first clock component  141   a  includes a clock control circuit (CC)  142   a  and a clock source (CS)  144   a . Here, the clock source  144   a  includes a multiplexer MUX circuit which receives a plurality of clock signals CLK[n: 0 ] and selects one of the clock signals CLK[n: 0 ]. The clock control circuit  142   a  controls the clock source  144   a  in a hardware-wise manner, transmits one or more clock requests REQ[n: 0 ] to the clock control circuits  122   a  through  122   g , and receives one or more acknowledgements ACK[n: 0 ] from the clock control circuits  122   a  through  122   g . The clock control circuit  142   a  may control the clock source  144   a  in a hardware-wise manner by sending a control signal to the clock source  144   a  to select which of the input clock signals CLK[n: 0 ] to output. 
         [0050]    The second clock component  141   b  includes a clock control circuit (CC)  142   b  and a clock source  144   b . Here, the clock source  144   b  includes a clock dividing (CD) circuit which divides a clock signal output from the clock source  144   a  by a dividing ratio. The dividing ratio may be an integer greater than 1 as an example. Since the clock signal output from the clock source  144   a  can have a high frequency which may be difficult for the output pin  150  of the semiconductor device  1  to operate with, the clock source  144   b  may be used to lower the frequency of the clock signal output from the clock source  144   a . The clock control circuit  142   b  controls the clock source  144   b  in a hardware-wise manner, transmits a clock request to the clock control circuit  142   a , and receives an acknowledgement from the clock control circuit  142   a . The clock control circuit  142   b  may control the clock source  144   b  in a hardware-wise manner by sending a control signal to the clock source  144   b  that enables the clock source  144   b  to perform a dividing operation. The clock request transmitted to the clock control circuit  142   a  may indicate that the second clock component  141   b  needs a clock signal. The acknowledgement received by the clock control circuit  142   b  may indicate that the first clock component  141   a  has begun outputting the clock signal or that the first clock component  141   a  is aware that the second clock component  141   b  needs the clock signal. 
         [0051]    The FSM  143  determines an operating state (mode) of the clock signal output circuit  140  according to an operating mode control signal MS. The clock signal output circuit  140  may operate in a “monitoring mode” for monitoring any one of a plurality of clock signals output from the clock sources  124   a  through  124   g  or in a “functional mode” for transmitting the any one of the clock signals to a device provided outside the semiconductor device  1 . For example, the clock signal output circuit  140  operates in the monitoring mode when the operating mode control signal MS is at a first logic level and operates in the functional mode when the operating mode control signal MS is at a second logic level different from the first logic level. In an embodiment, the FSM  143  does not change its mode until it receives an acknowledgement signal. For example, if the current mode of the FSM  143  is the monitoring mode, and it receives an operating mode control signal MS indicating it should change to the functional mode, the FSM  143  may output a request signal to cause clock signals to be output by the clock components (e.g.,  120   a - 120   g ), and then upon receiving at least one acknowledgement signal from these clock components, the FSM  143  can change its mode to the functional mode. If the FSM  143  does not receive the at least one acknowledgement signal within a certain time period, the FSM  143  can either remain in the monitoring mode or re-send the request signal. In an embodiment, the second clock component  141   b  communicates with the first clock component  141   a  and the FSM  143  using synchronous handshaking (i.e., using requests and acknowledges). 
         [0052]    The clock gating circuit  145  gates a clock signal CLK_OUT output from the clock signal output circuit  140  according to an enable signal EN, thereby preventing an unnecessary clock signal from being output when the clock signal output circuit  140  is not used. 
         [0053]    In an exemplary embodiment of the present inventive concept, the operating mode control signal MS and the enable signal EN are provided by software using a special function register (SFR). However, the present inventive concept is not limited thereto, and a control circuit which generates the operating mode control signal MS and the enable signal EN can also be implemented in the semiconductor device  1 . 
         [0054]      FIG. 3  is a schematic diagram illustrating a method of operating the clock signal output circuit  140  according to an exemplary embodiment of the present inventive concept. 
         [0055]    Referring to  FIG. 3 , the clock signal output circuit  140  is depicted as operating in the functional mode. When the clock signal output circuit  140  is operating in the functional mode to provide a clock signal for driving a device outside the semiconductor device  1 , the clock signal output circuit  140  operates as a clock component described above with reference to  FIG. 1 . 
         [0056]    Specifically, in the functional mode, the clock signal output circuit  140  may transmit a clock request REQ[ 3 : 0 ] to its parent clock components  120   b  through  120   e  and receive an acknowledgement ACK[ 3 : 0 ] in response to the clock request REQ[ 3 : 0 ]. That is, to drive a device provided outside the semiconductor device  1 , the clock signal output circuit  140  may transmit the clock request REQ[ 3 : 0 ] to each of the parent clock components  120   b  through  120   e.    
         [0057]    The clock request REQ[ 3 : 0 ] transmitted from the clock signal output circuit  140  may be forwarded to each of the parent clock components  120   b  through  120   e . For example, the clock request REQ[ 3 ] may be forwarded to the parent clock component  120   b  and the clock request REQ[ 2 ] may be forwarded to the parent clock component  120   c . The acknowledgement ACK[ 3 : 0 ] transmitted from each of the parent clock components  120   b  through  120   e  may be forwarded to the clock signal output circuit  140 . For example, the acknowledgement ACK[ 3 ] from the parent clock component  120   b  and the acknowledgement ACK[ 2 ] from the parent clock component  120   c  may be forwarded to the clock signal output circuit  140 . 
         [0058]    The clock signal output circuit  140  selects any one of clock signals CLK[ 0 ] through CLK[ 3 ] received from the parent clock components  120   b  through  120   e  and outputs the selected clock signal to the output pin  150 . 
         [0059]      FIG. 4  is a schematic diagram illustrating a method of operating the clock signal output circuit  140  according to an exemplary embodiment of the present inventive concept. 
         [0060]    Referring to  FIG. 4 , the clock signal output circuit  140  is depicted as operating in the monitoring mode. When the clock signal output circuit  140  is operating in the monitoring mode to monitor clock signals inside the semiconductor device  1 , the clock signal output circuit  140  does not transmit any clock request to its parent clock components  120   b  through  120   e . This is because when the clock signal output circuit  140  transmits a clock request to any one of the parent clock components  120   b  through  120   e , the configuration for clock signals inside the semiconductor device  1  is changed, which may prevent accurate monitoring. 
         [0061]    The clock signal output circuit  140  selects any one of clock signals CLK[ 0 ] through CLK[ 3 ] received from the parent clock components  120   b  through  120   e  and outputs the selected clock signal to the output pin  150 . 
         [0062]      FIG. 5  is a schematic diagram illustrating a method of operating the clock signal output circuit  140  according to an exemplary embodiment of the present inventive concept. 
         [0063]    Referring to  FIG. 5 , the clock source  144   a  of the clock signal output circuit  140  includes the MUX circuit. Therefore, the clock source  144   a  selects any one of a plurality of inputs, i.e., a plurality of clock signals CLK[n: 0 ] according to a select signal SEL provided by the clock control circuit  142   a.    
         [0064]    When the clock control circuit  142   a  of the clock signal output circuit  140  needs to change a value of the select signal SEL during the operation of the semiconductor device  1 , the clock control circuit  142   a  transmits a clock request REQ to its parent clock control circuits. To this end, the clock control circuit  142   a  of the clock signal output circuit  140  may generate, on its own, the clock request REQ that is to be transmitted to the parent clock control circuits. 
         [0065]    Specifically, if parents of the clock signal output circuit  140  include a first parent (P 1 )  170  which is currently providing a clock signal to the clock source  144   a  and a second parent (P 2 )  172  which desires to provide a clock signal to the clock source  144   a , the clock control circuit  142   a  transmits the clock request REQ to both of the parents  170  and  172  to deselect the clock signal being provided by the first parent (P 1 )  170  and to select the clock signal that is to be provided by the second parent (P 2 )  172  by changing the value of the select signal SEL. Accordingly, when it is guaranteed that the clock signals are being provided to the clock source  144   a  from both of the parents  170  and  172 , the clock control circuit  142   a  of the clock signal output circuit  140  then provides the select signal SEL having the changed value to the clock source  144   a.    
         [0066]    The fact that the clock signals are being provided to the clock source  144   a  from both of the parents  170  and  172  can be ascertained from an acknowledgement ACK received from a clock control circuit of each of the parents  170  and  172 . That is, after the clock control circuit  142   a  receives the acknowledgement ACK for the clock request REQ from the clock control circuit of each of the parents  170  and  172 , the clock source  144   a  can change its selection according to the changed select signal SEL. For example, if the MUX  144   a  is currently outputting a first clock signal CLK 1  due to the select signal SEL being set to a first logic level, and the clock control circuit  142   a  needs to cause output of the second clock signal CLK 2 , the clock control circuit  142   a  outputs the clock request REQ to both of the parents  170  and  172 , and then changes the select signal SEL to a second logic level only after receiving an acknowledgement ACK from both parents  170  and  172 . 
         [0067]      FIG. 6  is a schematic diagram illustrating a method of operating the clock signal output circuit  140  according to an exemplary embodiment of the present inventive concept. 
         [0068]    Referring to  FIG. 6 , the clock source  144   b  of the clock signal output circuit  140  includes the clock dividing circuit. Therefore, the clock source  144   b  may generate a divided clock signal D CLK by dividing a clock signal CLK output from the clock source  144   a  based on a division ratio D VAL provided by the clock control circuit  142   b . 
         [0069]    When the clock control circuit  142   b  of the clock signal output circuit  140  needs to change a value of the division ratio D_VAL during the operation of the semiconductor device  1 , the clock control circuit  142   b  transmits a clock request REQ to the clock control circuit  142   a . To this end, the clock control circuit  142   b  of the clock signal output circuit  140  may generate, on its own, the clock request REQ that is to be transmitted to the clock control circuit  142   a.    
         [0070]    Accordingly, when it is guaranteed that the clock signal CLK is being provided to the clock source  144   b  from the clock source  144   a , the clock control circuit  142   b  of the clock signal output circuit  140  may transmit the division ratio D_VAL having the changed value to the clock source  144   b.    
         [0071]    The fact that the clock signal CLK is being provided to the clock source  144   b  from the clock source  144   a  can be ascertained from an acknowledgement ACK received from the clock control circuit  142   a . That is, after the clock control circuit  142   b  receives the acknowledgement ACK for the clock request REQ from the clock control circuit  142   a , the clock source  144   b  can divide the clock signal CLK according to the changed division ratio D_VAL. For example, if the clock dividing circuit  144   b  previously or is currently outputting a divided clock signal D_CLK that was generated as a result of dividing an input clock signal CLK by a division ratio D_VAL of a first value, and the clock control circuit  142   b  needs to change the value of the division ratio D_VAL to a second other value, the clock control circuit  142   b  outputs a clock request REQ to the clock control circuit  142   a , and then changes the division ratio D_VAL to the second value only after receiving an acknowledgement ACK from the clock control circuit  142   a.    
         [0072]      FIG. 7  is a block diagram of a semiconductor system to which a semiconductor device and a method of operating the semiconductor device according to embodiments of the present inventive concept can be applied. 
         [0073]    Referring to  FIG. 7 , the semiconductor system to which the semiconductor device and the method of operating the semiconductor device according to the embodiments of the present inventive concept can be applied includes an SoC  1  having the above-described features, a processor  10 , a memory  20 , a display  30 , a network device  40 , a storage device  50 , and an input/output (I/O) device  60 . The SoC  1 , the processor  10 , the memory  20 , the display  30 , the network device  40 , the storage device  50 , and the I/O device  60  can exchange data with each other through a bus  70 . 
         [0074]    IP blocks of the SoC  1  which have been mentioned in various embodiments of the present disclosure may include at least one of a memory controller which controls the memory  20 , a display controller which controls the display  30 , a network controller which controls the network device  40 , a storage controller which controls the storage device  50 , and an input/output (I/O) controller which controls the I/O device  60 . The semiconductor system may further include an additional processor  10  which controls these devices. 
         [0075]    While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present inventive concept.