Abstract:
Methods and systems for analog to digital converter and systems incorporating the same are provided. Specifically, an analog sampler that has a reduced input current is disclosed. According to the present teaching, an apparatus for sampling an input voltage includes a first switch having its first terminal connected to an input voltage, and a first pre-charging circuit, coupled to a second terminal of the first switch, that provides a first pre-charged voltage that is substantially equal to the input voltage. The first pre-charged voltage is provided at the first terminal of the first switch before the first switch is turned on. The apparatus further includes a second pre-charging circuit coupled to both the first pre-charging circuit and the second terminal of the first switch, where the second pre-charging circuit charges the first pre-charged voltage prior to the first switch being turned on.

Description:
BACKGROUND 
     1. Technical Field 
     The present teaching relates generally to methods and systems for analog circuits. More specifically, the present teaching relates to methods and systems for analog to digital converter and systems incorporating the same. 
     2. Discussion of Technical Background 
     An analog to digital converter (ADC) is a widely used technology. In a circuit implementing an ADC, the analog input voltage is typically sampled and the quality of an ADC depends on the quality of voltage sampling at the input of the ADC.  FIG. 1  shows a typical measurement of V S  ( 110 ) using an ADC  140 . A source resistance R S    120  usually accompanies V S  and can be deliberately large in many situations. For example, such an ADC can be measuring the voltage in a Wheatstone bridge, and the resistors in the bridge can have large values. As another example, in certain applications, it may be desired to filter out the high-frequency components into the ADC by introducing an RC filter at the ADC input. 
     When I IN  exists, it causes a voltage drop ΔV  130  across the source resistor  120 . In this case, the voltage measured by the ADC will be V S −ΔV rather than V S . Thus, the input current I IN  introduces an error into the measurement of the source voltage. 
     Efforts have been made to reduce such problem. For example, some prior solution introduced a buffer before an ADC and made the buffer&#39;s input impedance extremely high. There are several disadvantages to this approach, however. First, a buffer is an extra component, adding cost, size and power dissipation. Second, since no electronic device is perfect, the buffer inevitably introduces noise and distortion into the signal. Third, a buffer only works correctly in a limited voltage range. While the ADC can be designed for input voltages all the way to the supply rails, the introduction of a buffer either limits the input voltage range or requires an additional power supply for the buffer. 
     Other embedded approaches have been adopted to minimize the input current. To understand how such approaches work, one needs to understand the basic mechanism causing ADC input current. This is shown in  FIG. 2  (PRIOR ART). The first part of an ADC  200  performs a function called sample-and-hold, which samples the input voltage  200  to obtain V 1  ( 240 ) and then stores the sampled voltage V 1  ( 240 ) on a capacitor C 1    250 . The sampling is done by turning switch S 1   230  on, and the charge is held by closing switch S 1   230 . If the sampled voltage V 1  ( 240 ) on capacitor C 1    250  is different from V S , there is an associated charge transferred from the input to the ADC, which is C 1 (V S −V 1 ). If this charge transfer happens with a frequency f, the average input current is f*C 1 (V S −V 1 ). 
     Traditionally, the input current can be minimized by pre-charging V 1  to V IN  before switch S 1  is turned on. Different approaches have been used to pre-charge C 1  to V IN . One example method, as shown in  FIG. 3  (PRIOR ART), is that an ADC  310  uses a unity-gain buffer  320  at the input to charge C 1    360 . Before S 1   330  is turned on, S 2   340  is turned on first and then turned off, pre-charging C 1    360  so that V 1  ( 350 )=V IN . The unity-gain buffer  320  can be designed to have a high input impedance. Unfortunately, when the input is close to the supply rails, the unity-gain buffer  320  can not accurately reproduce V IN  at the output of the buffer. Because of this, when it is close to the supply rails, input current still exists. 
     Another approach of pre-charging is disclosed in U.S. Pat. No. 7,088,280. This approach is described in  FIG. 4  (PRIOR ART). With this approach, feedback from a 1-bit ADC is adopted to keep V 1  ( 470 ), on average, equal to V IN  ( 430 ). If V IN =f*V REF+ , and assuming an accurate ADC, then for a fraction f of the total samples C 1  ( 480 ) is pre-charged to V REF+  by turning on switch S 2   450 , while the remainder (1−f) of the time C 1    480  is pre-charged to V REF− =0 by turning on switch S 3   460 . In this case, on average, C 1    480  is charged to f*V REF+ . When the voltage on C 1  ( 480 ) is pre-charged to an average of V IN , switch S 1   440  can be turned on. At that time, because on average V 1 =V IN , there will be no input current. 
     Although this input current cancellation scheme works all the way to the supply rails, due to non-idealities in the switches, the method described in U.S. Pat. No. 7,088,280 does not completely cancel out the undesirable input current. Switches S 1   440 , S 2   450 , and S 3   460  are typically composed of MOS transistors. It is well known that these transistors suffer from device capacitances and charge injection. Both charge injection and device capacitance are nonlinear functions of the voltage on the MOS terminals. Furthermore, charge injection is very difficult to model correctly. There is no guarantee that the average input current generated under these effects can be canceled out. Therefore, there is a need for a method and system that can pre-charge C 1  to a voltage level substantially close to V IN  before S 1  is turned on, while allowing a full rail-to-rail operation in an ADC circuit. 
     SUMMARY OF THE PRESENT TEACHING 
     The present teaching relates to methods and systems for analog to digital converter and systems incorporating the same. Specifically, the present teaching discloses an analog sampler that has a reduced input current. According to one aspect of the present teaching, an apparatus for sampling an input voltage includes a first switch having its first terminal connected to an input voltage, and a first pre-charging circuit, coupled to a second terminal of the first switch, to provide a first pre-charged voltage that is substantially equal to the input voltage. The first pre-charged voltage is provided at the first terminal of the first switch before the first switch is turned on. The apparatus further includes a second pre-charging circuit coupled to both the first pre-charging circuit and the second terminal of the first switch, where the second pre-charging circuit charges the first pre-charged voltage prior to the first switch being turned on. 
     In accordance with another aspect of the present teaching, an apparatus for sampling an input voltage includes a first switch having its first terminal connected to an input voltage and a first pre-charging circuit coupled to a second terminal of the first switch to provide a first pre-charged voltage, substantially equal to the input voltage. The first pre-charged voltage is provided at the first terminal of the first switch before the first switch is turned on. The apparatus also includes a second pre-charging circuit coupled to both the first pre-charging circuit and the second terminal of the first switch, where the second pre-charging circuit is supplied with a second pre-charged voltage by a third pre-charge circuit prior to being pre-charged. The second pre-charging circuit pre-charges after the second pre-charged voltage is supplied and while the first pre-charging circuit is being pre-charged. Furthermore, the first switch remains being turned off until the first pre-charged voltage reaches a level substantially equal to the input voltage. 
     In yet another aspect of the present teaching, an apparatus for sampling an input voltage includes an analog to digital converter (ADC) configured to sample an input voltage. The ADC comprises a first switch having its first terminal to the input voltage and a second switch having its first terminal coupled to a second terminal of the first switch. The apparatus also includes a first capacitor that couples its first terminal to the first terminal of the second switch and its second terminal to a first voltage. Additionally, the apparatus further includes a filter having an output coupled to a second terminal of the second switch and a digital to analog converter (DAC) having an output coupled to an input of the filter and an input coupled to an output of a quantizer. According to the present teaching, the quantizer generates an output based on an input coupled to the first terminal of the first capacitor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The inventions claimed and/or described herein are further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein: 
         FIG. 1  depicts a typical circuit for sampling voltage in association with an analog to digital converter (ADC); 
         FIG. 2  (PRIOR ART) depicts a circuit for sampling voltage that incorporates an input switch; 
         FIG. 3  (PRIOR ART) depicts a circuit for sampling voltage via pre-charging a capacitor to a desired level by employing a unit-gain buffer and a plurality of switches; 
         FIG. 4  (PRIOR ART) depicts a circuit for sampling voltage via pre-charging a capacitor to a desired level based on a plurality of switches; 
         FIG. 5  depicts an exemplary circuit for sampling voltage by pre-charging two capacitors to a desired voltage level based on a plurality of switches; 
         FIG. 6(   a ) shows a plot of pre-charged voltages over time; 
         FIG. 6(   b ) shows a plot of the time required to pre-charge voltage to a certain level, according to an embodiment of the present teaching; 
         FIG. 7  depicts an exemplary circuit for sampling voltage by pre-charging two capacitors to a desired voltage level with one of the capacitors being pre-charged based on an additional circuit, according to another embodiment of the present teaching; 
         FIG. 8  depicts an exemplary generalized circuit for reducing input current, according to an embodiment of the present teaching; and 
         FIG. 9  shows yet another embodiment for sampling an input voltage according to the present teaching. 
     
    
    
     DETAILED DESCRIPTION 
     The present teaching relates to voltage sampling in an ADC circuit. Specifically, the disclosed systems and methods achieves more accurate voltage sampling by more robustly pre-charging the voltage in the ADC circuit to an input voltage level based on DAC feedback and employing a filtering technique prior to sampling the input voltage. The disclosed methods and systems enable a reduction of input current ten times when compared with what can be achieved using prior art technologies. 
       FIG. 5  depicts an exemplary circuit  500  for sampling voltage in an ADC  560 , according to an embodiment of the present teaching. In  FIG. 5 , the ADC has an input voltage V IN    560 , which is connected to a switch S 1  ( 525 ). In this illustrated embodiment, a voltage pre-charge circuit comprises switch S 2  ( 535 ), switch S 3  ( 540 ), switch S 4  ( 530 ), capacitor C 1  ( 550 ), and capacitor C 2  ( 515 ). Switch S 2  is connected to a voltage supply V REF+  on one end and the other end is connected to switch S 3   540 . The other end of S 3   540  is connected to a different voltage supply V REF− . Without loss of generality, V REF+  is tied to the ground in the following figures for ease of presentation of the present teaching. 
     In general, the pre-charge circuit is designed to pre-charge V 1  ( 545 ) and/or V 2  ( 520 ) to, e.g., the level of V IN    560 . When this is achieved, S 1  can then be closed (or turned on). Since at this point, the voltages on both sides of S 1  are almost equal, there will be no or minimum current between V IN  and V 1  and hence, causing minimal voltage drop across R s    510 . This makes the charge injection and nonlinear device capacitance effects on S 1  significantly reduced and, hence, enables more accurate voltage sampling. 
     The pre-charge process is described as follows. Switch S 2   535  and switch S 3   540  can be turned on and off alternately. For example, switch S 2  may be turned on 30% of the time and S 3  may be turned on 70% of the time. Thus, based on the output of the feedback DAC, capacitor C 1  ( 550 ), i.e., V 1 , is charged to V REF+  30% of the time and V REF−  70% of the time. After switches S 2  and S 3  are closed, when switch S 4  ( 530 ) is turned on, the voltages on capacitor C 2  ( 515 ) and C 1  can be equalized. If C 2  is pre-charged to V N  and if C 2 &gt;&gt;C 1 , then the voltage charged on C 1  can be closely approximated to V IN . When C 1  is charged, switch S 4  is turned off and switch S 1  is turned on. Since the voltage levels at both sides of switch S 1  are almost equal, the amount of input current flowing through resistor R s  is kept at minimum or near zero when switch S 1  is turned on or closed. 
     Simulation was performed with a standard 5V CMOS process. The feedback DAC switched to V REF+  30% of the time and V REF−  70% of the time. In the simulation, V REF−  was chosen to be ground and V REF+  was 5V. C 2  was pre-charged to 1.5V. The input current varied widely depending on the DAC switching. To average the effects, an opened capacitor C IN , pre-charged to 1.5V, was placed at the input of the switching arrangement. Current coming in and out of the capacitor increases or decreases the capacitor voltage. By looking at the longer-term change in capacitor voltage, we can deduce the average input current from I=C IN *dV IN /dt. 
     The simulation result is shown in  FIG. 6(   a ), where C 1  is set to be 0.3 pF (plus capacitance from device parasitics) and C 2  is set to be 1 nF. In the simulation, C IN =1 nF. The input current is measured with respect to both the circuit arrangement as described in the U.S. Pat. No. 7,088,280 and the circuit arrangement as disclosed herein. As can be seen in  FIG. 6(   a ), the input current as measured with time from the prior art circuit arrangement is averaged at about 27 nA (see the dotted curve). It can also be seen that the input current measured from the circuit arrangement as disclosed herein is averaged at a level of about 2.7 nA, which represents a substantial reduction of the input current. 
     One issue related to the present teaching is how to re-charge C 2 . While a unity-gain buffer can be used for that purpose, C 2  can be, asymptotically, be pre-charged to C IN , with a rail-to-rail range, using the switching arrangement in  FIG. 5 . This can be mathematically proven as formulated below. Since switch S 1  does not affect the voltage V 2 , the action of switch S 1  can be ignored. The timing of switching is the following. After S 1  is turned on (closed) and before S 4  is turned off (open), S 2  or S 3  have been turned off (opened). This is after the circuit pre-charges C 1  to either GND or V REF+ . 
     Let the charge on C 1  before time nT (before S 4  is turned on) be V 1 (n−1). Let the charge on C 2  at time nT (after S 4  is turned on) as V 2 (n). From conservation of charge, it is known that: 
                 V   2     ⁡     (   n   )       =           C   2     ⁢       V   2     ⁡     (     n   -   1     )         +       C   1     ⁢       V   1     ⁡     (     n   -   1     )               C   2     +     C   1               
That is, the voltage pre-charged on C 2  is influenced by both the voltage levels V 1  and V 2  measured at a previous time instance. This equation can be re-written as:
 
                 V   2     ⁡     (   n   )       =           C   2         C   2     +     C   1         ⁢       V   2     ⁡     (     n   -   1     )         +         C   1         C   2     +     C   1         ⁢       V   1     ⁡     (     n   -   1     )                 
Through this re-written form, it is clear that V 2 (n) can be solved iteratively. Let the initial value of V 2  at nT=0 be V 2 (0). Also, to simplify the equations, let
 
α= C   2 /( C   1   −C   2 )  (1)
 
Then,
 
                             V   2     ⁡     (   1   )       =       α   ⁢           ⁢       V   2     ⁡     (   0   )         +       (     1   -   α     )     ⁢       V   1     ⁡     (   0   )                           V   2     ⁡     (   2   )       =       α   ⁢           ⁢       V   2     ⁡     (   1   )         +       (     1   -   α     )     ⁢       V   1     ⁡     (   1   )                       =       α   ⁡     (       α   ⁢           ⁢       V   2     ⁡     (   0   )         +       (     1   -   α     )     ⁢       V   1     ⁡     (   0   )           )       +       (     1   -   α     )     ⁢       V   1     ⁡     (   1   )                       =         α   2     ⁢       V   2     ⁡     (   0   )         +       α   ⁡     (     1   -   α     )       ⁢       V   1     ⁡     (   0   )         +       (     1   -   α     )     ⁢       V   1     ⁡     (   1   )       ⁢           ⁢   and                       V   2     ⁡     (   3   )       =       α   ⁢           ⁢       V   2     ⁡     (   2   )         +       (     1   -   α     )     ⁢       V   1     ⁡     (   2   )                       =       α   ⁡     (         α   2     ⁢       V   2     ⁡     (   0   )         +       α   ⁡     (     1   -   α     )       ⁢       V   1     ⁡     (   0   )         +       (     1   -   α     )     ⁢       V   1     ⁡     (   1   )           )       +                 =       (     1   -   α     )     ⁢       V   1     ⁡     (   2   )                     =         α   3     ⁢       V   2     ⁡     (   0   )         +         α   2     ⁡     (     1   -   α     )       ⁢       V   1     ⁡     (   0   )         +       α   ⁡     (     1   -   α     )       ⁢     V   1     ⁢     (   1   )       +                 =       (     1   -   α     )     ⁢       V   1     ⁡     (   2   )                             (   2   )                                                               (   3   )                                     
We can then extrapolate from Equations (2) and (3) to obtain a generalized equation for V 2  as follows:
 
                       V   2     ⁡     (   n   )       =         α   n     ⁢       V   2     ⁡     (   0   )         +       ∑     j   =   0       n   -   1       ⁢           ⁢         α   j     ⁡     (     1   -   α     )       ⁢       V   1     ⁡     (     n   -   1   -   j     )                     (   4   )               
Since α&lt;1 (see Equation (1)), then, at n=∞, the first item vanishes so that we have:
 
                       V   2     ⁡     (   ∞   )       =       (     1   -   α     )     ⁢       ∑     j   =   0     ∞     ⁢           ⁢       α   j     ⁢       V   1     ⁡     (     n   -   1   -   j     )                     (   5   )               
Thus, when the time t approaches infinity (∞), the voltage on C 2  is asymptotically becoming completely independent of its own initial condition V 2 (0). When this happens, the pre-charged voltage V 2  on C 2  is a weighted average of the V 1  measurements made previously, with the most recent measured voltages mattering the most. To see this, if we assume V 1  always equals V IN , we have:
 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       2 
                     
                     ⁡ 
                     
                       ( 
                       ∞ 
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                   = 
                   
                     
                       
                         ( 
                         
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                       ⁢ 
                       
                         V 
                         1 
                       
                       ⁢ 
                       
                         
                           ∑ 
                           
                             j 
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                           α 
                           j 
                         
                       
                     
                     = 
                     
                       
                         
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                             1 
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                           V 
                           IN 
                         
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                           1 
                           
                             1 
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                             α 
                           
                         
                       
                       = 
                       
                         
                           V 
                           IN 
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     There is then a trade-off in the value of α. With smaller values of α, the pre-charged V 2  depends less on the initial conditions and, thus, a faster pre-charge time. When larger values of α are used, the pre-charged V 2  is less susceptible to the current value of V 1 , leading to a more stable pre-charged voltage.  FIG. 6(   b ) shows some simulation result, in which capacitor C 2  is pre-charged to 1.5V, with V REF+ =5V, S 2  is turned on 30% of the time, and S 3  is turned on 70% of the time. 
     As seen in  FIG. 6(   b ), it can take some time to pre-charge C 2  to the level of V 11 . During this interim period, there potentially can be substantial input current. In addition, from this plot, it can be seen that the choice of a has an impact as to the time required to pre-charge C 2  to a desired level. That is, the choice of a can influence both the time required to pre-charge C 2  and how quickly the input current can be dissipated. 
     Such interim input current may also be reduced, particularly when such interim input current is not acceptable in some applications. An additional circuit may be added to the circuit shown in  FIG. 5  to reduce the interim input current. One exemplary circuit for that purpose is shown in  FIG. 7 , in which an optional circuit  770  is introduced to additionally connect with the rest of the circuit, which is described with respect to  FIG. 5 . Specifically, similar to  FIG. 5 , the ADC circuit  700  in  FIG. 7  comprises switches  710 ,  715 ,  720 , and  725  and two capacitors, C 1    780  and C 2    735 . The circuit is designed to pre-charge C 2  to V 2  ( 730 ) and C 1  to V 1  ( 775 ) and ideally V 2 =V 1 =V IN  ( 705 ). 
     In the exemplary optional circuit  770 , as depicted in  FIG. 7 , switches S 5  ( 745 ), S 6  ( 750 ), and S 7  ( 760 ) are introduced and they are connected to a new capacitor C 3  ( 765 ). Switches S 6  and S 7  are also connected to a 1-bit feedback DAC. In some embodiments, S 6   750  and S 7   760  are connected to the same signals controlling S 2  and S 3 , respectively. That is, V REF+  and V REF− , respectively. In the illustrated exemplary optional circuit  770 , switch S 5   745  is connected to one end of switch S 4 . In some embodiments, switch S 5  can also be connected to the other end of switch S 4 . 
     The sequence of switching events can be described as follows. With the optional circuit  770 , voltage V 2  can be pre-charged prior to opening S 4 . To do so, switch S 4  may be first made inactive for a certain amount of time. During this period, switches S 5 , S 6  and S 7  are turned on and off in accordance with the description presented herein with respect to S 2 , S 3 , and S 4 . For example, S 6  may be switched on 30% of the time and S 7  70% of the time to pre-charge C 2 . During that time, switch S 4  may be turned off (open) until the pre-charge of C 2  is complete. At that time, switch S 4  may be turned on so that V 1 =V 2 . When S 4 , S 2 , and S 3  are turned on and off in accordance with the description herein to pre-charge both V 2  and V 1 , the fact that C 2  is pre-charged to V 3  prior to pre-charge C 2  makes the time required to pre-charge C 2  shorter and a bigger reduction in terms of input current. 
     When C 2  is being pre-charged, in some embodiments, the optional circuit  770  may be inactivated by switching off S 5  and switch S 4  may be activated. Alternately, one could also keep the optional circuit  770  active after S 4  is activated. 
     To implement the optional circuit  770 , one may create C 3  out of smaller capacitors connected together by switches. When implemented this way, C 3  may not have a constant value and can be made larger during the initial pre-charge and have a reduced capacitance once the voltage on C 2  approaches the input voltage. 
     The systems and methods described herein may be generalized, as depicted in  FIG. 8 . This generalized circuit comprises an A/D converter  800 , a D/A converter  870 , and a filter  860  used to reproduce an input signal, which is then used to pre-charge, once switch S 4   830  is turned on, the input capacitor C 1  ( 840 ) to the input voltage V 1  ( 810 ) before the input switch S 1   820  is turned on. 
     The filter  860  in this exemplary embodiment may be a low-pass filter, which produces a weighted average of the input signal from the D/A converter  870 . If the input signal has a known frequency profile, the filter  860  may be modified, for example, to be a band-pass filter. Such a filter can also be appropriately used for a higher-frequency input signal. For extremely high frequencies, a load on the ADC may be deployed to eliminate reflections. Similarly, in such a generalized circuit, one can also introduce the optional circuit  770  as discussed with respect to  FIG. 7 . 
       FIG. 9  shows yet another exemplary circuit for sampling an input voltage according to the present teaching. In this exemplary circuit  900 , capacitor C 2   915  is used to sample the input voltage V IN    955 . Therefore, capacitor C 2  is pre-charged to reach a level substantially equal to V IN  prior to sampling V IN . Switches S 1 , S 2 , S 3 , and S 4  ( 925 ,  935 ,  940 , and  930 ) play similar role as corresponding switches in  FIG. 5 . Switch S 5   945  is optional and is designed to isolate C 1  from C 2  when C 2  is used to sample the input voltage when switches S 1  and S 4  are open. Switch S 5  can be implemented either on the right (as shown) or on the left (not shown) of the S 2 /S 3  switches. 
     To pre-charge C 1 , it can be done by first open S 2   935  and S 3   940  based on the same approach as described earlier with respect to  FIG. 5  by opening switches S 4   930  and S 5   945 . If S 5  is on the right of S 2 /S 3 , S 5  is also open in order to pre-charge C 1 . Once C 1  is pre-charged, S 2  and S 3  can be closed and then S 4  and S 5  are open to equalize V 1  and V 2 . When V 1  and V 2  are equal, C 2  is used to sample the input voltage V IN  by opening S 1  and S 4  and with S 5  closed so that C 1  is isolated and its capacitance will not contribute to the input current to interfere the sampling. 
     While the inventions have been described with reference to the certain illustrated embodiments, the words that have been used herein are words of description, rather than words of limitation. Changes may be made, within the purview of the appended claims, without departing from the scope and spirit of the invention in its aspects. Although the inventions have been described herein with reference to particular structures, acts, and materials, the invention is not to be limited to the particulars disclosed, but rather can be embodied in a wide variety of forms, some of which may be quite different from those of the disclosed embodiments, and extends to all equivalent structures, acts, and, materials, such as are within the scope of the appended claims.