Abstract:
A secure electronic chip including a plurality of biased semiconductor wells and a well biasing current detection circuit. Each of the wells includes a transistor and a bias contact electrically isolated from the transistor. The detection circuit is electrically coupled to each bias contact and is configured to detect a bias current passing through the bias contact that is indicative of an attempt to tamper with the electronic chip.

Description:
[0001]    This application claims the priority benefit of French Patent application number 15/60089, filed on Oct. 22, 2015, the contents of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. 
       BACKGROUND 
       [0002]    Technical Field 
         [0003]    The present application relates to electronic chips, particularly to electronic chips protected against attacks. 
         [0004]    Description of the Related Art 
         [0005]    Electronic chips containing confidential data, such as bank card chips, may undergo attacks from hackers aiming at determining the operation of the chip and at extracting the confidential information therefrom. An attack may be carried out on the chip in operation connected between the terminals of a power source. A way to carry out such an attack is for a hacker to scan the chip surface with a pulsed laser beam which disturbs the chip operation. The observation of the consequences of such disturbances, sometimes called faults, enables the hacker to carry out the attack. To disturb the chip operation, the hacker may also form contacts on the chip surface and apply voltages thereto. The hacker may also arrange a coil close to the chip surface to emit electromagnetic disturbances. 
         [0006]    It is desirable to have electronic chips protected against this type of attack, called fault injection attack, known devices having various disadvantages and implementation issues. 
       BRIEF SUMMARY 
       [0007]    Thus, an embodiment provides a secure electronic chip comprising a plurality of biased semiconductor wells and a well biasing current detection circuit. 
         [0008]    According to an embodiment, the detection circuit is capable of generating an alert signal when the bias current is greater, in absolute value, than a threshold. 
         [0009]    According to an embodiment, the detection circuit comprises a resistive element conducting the bias current, the detection circuit being capable of detecting a voltage across the resistive element. 
         [0010]    According to an embodiment, the resistive element has a resistance in the range from 1 to 100Ω. 
         [0011]    According to an embodiment, the secure electronic chip comprises a power supply circuit capable of providing a potential for biasing said wells, the detection circuit being capable of detecting a variation of a potential regulating the bias potential. 
         [0012]    According to an embodiment, the power supply circuit comprises an operational amplifier having its output coupled to the gate of a first MOS transistor and the detection circuit comprises a second MOS transistor forming a current mirror with the first MOS transistor, an input of the operational amplifier and the drain of the first MOS transistor being coupled to said wells, and the detection circuit being capable of detecting a variation of the current in the second transistor. 
         [0013]    According to an embodiment, the plurality of wells comprises first wells of a first conductivity type and second wells of a second conductivity type, the detection circuit comprising on the one hand a first circuit detecting the bias current of the first wells and on the other hand a second circuit detecting the bias current of the second wells. 
         [0014]    According to an embodiment, the first wells are formed in the upper portion of a semiconductor substrate of the second conductivity type and the second wells are upper portions of the substrate comprised between the first wells. 
         [0015]    According to an embodiment, the first wells and the second wells extend on a doped buried layer of the first conductivity type covering a substrate of the second conductivity type. 
         [0016]    Another embodiment provides a method of protecting an electronic chip comprising a plurality of biased semiconductor wells, comprising a step of detecting the well biasing current. 
         [0017]    According to an embodiment, the chip contains confidential data, the method comprising, when the detected bias current is greater than a threshold, a step of destroying the confidential data. 
         [0018]    According to an embodiment, the method comprises, when the detected bias current is greater than a threshold, a step of stopping the activity of the chip. 
         [0019]    The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0020]      FIG. 1  is a simplified partial cross-section view of an electronic chip of a first type; 
           [0021]      FIG. 2  is a simplified partial cross-section view of an electronic chip of a second type; 
           [0022]      FIG. 3  shows an embodiment of an electronic chip of the first type protected against attacks; 
           [0023]      FIG. 4  shows an embodiment of an electronic chip of the second type protected against attacks; and 
           [0024]      FIGS. 5A and 5B  detail embodiments of power supply and detection circuits. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    The same elements have been designated with the same reference numerals in the different drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. 
         [0026]    In the following description, when reference is made to terms qualifying the relative position, such as term “upper”, reference is made to the orientation of the concerned element in the drawings. 
         [0027]    In the present description, term “connected” designates a direct electric connected between two elements, while term “coupled” designates an electric connection between two elements which may be direct or via one or a plurality of other passive or active components, such as resistors, capacitors, inductances, diodes, transistors, etc.  FIG. 1  is a partial simplified cross-section view of an electronic chip  1  of a first type comprising N-type doped semiconductor wells  3  formed in the upper portion of a P-type doped semiconductor substrate  5 . For clarity, only a well and a portion of another well are shown in  FIG. 1 . 
         [0028]    N-channel MOS transistors  6  are formed inside and on top of the substrate portions located between wells  3  and comprise gates  7  and drain and source areas  9  and  11 . P-channel MOS transistors  12  are formed inside and on top of wells  3  and comprise gates  13  and drain and source areas  15  and  17 . The transistors are coupled together to form circuits, for example, digital circuits. As an illustration, an inverting logic circuit between nodes  19  and  21  is shown. The digital circuits comprise power supply nodes  23  and  25 . In the shown example, power supply nodes  23  and  25  are respectively coupled to sources  11  and  17  of transistors  6  and  12 . 
         [0029]    N-type doped wells  3 , or N wells, are provided with bias contacts  27 , and the substrate is provided with bias contacts  29 . The transistors and the bias contacts are separated by trench isolations  31 . 
         [0030]    A reference potential GND, for example, the ground, is applied both on power supply nodes  23  and on bias contacts  29  of the P wells. A power supply circuit, not shown, comprised in the chip, provides a potential VDD applied both to power supply node  25  and to bias contacts  27  of the N wells. 
         [0031]    In the following description, in an electronic chip of the first type, the upper portions  33  of the substrate comprised between N wells will be called P wells. 
         [0032]      FIG. 2  is a simplified partial cross-section view of an electronic chip  40  of a second type comprising N wells  3  and P wells  33  extending on an N-type doped buried layer  42  covering a P-type substrate  5 . 
         [0033]    Wells  3  and  33  correspond to wells  3  and  33  of previously-described chip  1 , that is, they comprise bias contacts  27  and  29  and digital circuits formed by transistors  6 ,  12  formed inside and on top of the wells. The digital circuits are provided with power supply nodes  23  and  25 . 
         [0034]    The digital circuits are powered between ground GND and a potential VDD respectively applied to nodes  23  and  25 . Bias potentials VPW and VNW, which may be different from potentials GND and VDD, are respectively applied to bias contacts  29  and  27 , and are provided by power supply circuits, not shown, comprised in the chip. 
         [0035]    As indicated as a preamble, for circuits containing confidential data, a pirate is capable of carrying out a fault injection analysis. Modes of detection of such attacks are described hereafter. 
         [0036]      FIG. 3  shows an embodiment of an electronic chip  50  of the first type protected against attacks.  FIG. 3  comprises a partial cross-section view of chip  50  and a representation of circuits comprised in this chip. 
         [0037]    Chip  50  comprises the elements of chip  1  described in relation with  FIG. 1  and particularly N wells  3  and P wells  33 . Circuits, for example, digital circuits, comprise transistors  6  formed inside and on top of P wells  33  and transistors  12  formed inside and on top of N wells  3 . The digital circuits have power supply nodes  23  and  25  and wells  3  and  33  are provided with respective bias contacts  27  and  29 . The bias contacts and the transistors are separated by trench insulators  31 . 
         [0038]    Power supply nodes  23  of the circuits are coupled to ground. Further, chip  50  comprises a power supply circuit  52  (VDD) which provides a potential VDD applied to power supply nodes  25 . Power supply circuit  52  is itself powered with a positive potential VCC and a ground potential GND provided by a power supply source, not shown, external to chip  50 . 
         [0039]    Bias contacts  29  of the P wells are not directly grounded, but are coupled to ground by a resistive element  54  comprised in the chip. The voltage across resistive element  54  is compared with a threshold by a comparator circuit  56  capable of generating an alert signal AP when this voltage is greater than the threshold. Resistive element  54  and comparator circuit  56  thus form a detection circuit  57  that detects the bias current of wells  33 . 
         [0040]    Bias contacts  27  of the N wells are coupled to power supply circuit  52  by a resistive element  58 . The voltage across resistive element  58  is compared with a threshold by a comparator circuit  60  capable of generating an alert signal AN when this voltage is greater than the threshold. Resistive element  58  and comparator circuit  60  thus form a detection circuit  61  that detects the bias current of wells  3 . 
         [0041]    In normal operation, the junctions between the N wells and the substrate are reverse biased, and no significant bias current flows through resistive elements  54  and  58 . The above-mentioned thresholds can thus be very low. 
         [0042]    During an attempt of fault injection attack on the chip, for example, at the time when a pirate bombards the chip with a laser beam, currents I 1 N and I 1 P appear between bias contacts  27  of N wells  3  and bias contacts  29  of P wells  33 . Bias currents I 1 N and I 1 P are detected by detection circuits  57  or  61  and cause the transmission of alert signals AN or AP. The signal is used by the chip to take countermeasures such as suspending or stopping its activity or destroying confidential data that it contains. 
         [0043]    During an attempt of attack by a pirate, currents I 1 P and I 1 N resulting from a disturbance of the chip operation are analyzed by the chip to detect the attack. Bias currents I 1 N and I 1 P used to detect the attack directly correspond to the currents resulting from the disturbance. Thus, the chip detects an injected power much lower than the minimum fault injection power. Thereby, chip  1  is advantageously protected against any fault injection attack, whatever the location of the attack on the chip surface. 
         [0044]    As an example, resistors  54  and  58  may be in the range from 1 to 100Ω. As a variation, resistive elements  54  and  58  may be components or portions of the chip, for example, well portions, capable of generating a voltage when conducting current. 
         [0045]      FIG. 4  shows an embodiment of an electronic chip  70  of the second type protected against attacks.  FIG. 4  schematically comprises a partial cross-section view of chip  70  and a representation of circuits comprised in this chip. 
         [0046]    Chip  70  comprises elements of chip  40  described in relation with  FIG. 2  and particularly of N wells  3  and P wells  33  extending on an N-type doped buried layer  42  covering a P-type doped substrate  5 . Circuits, for example digital circuits, formed inside and on top of the wells, have power supply nodes  23  and  25 . N wells  3  are provided with bias contacts  27  and P wells  33  are provided with bias contacts  29 . 
         [0047]    Power supply nodes  23  of the digital circuits are coupled to ground. Further, chip  70  comprises a power supply circuit  52  which provides a potential VDD applied to power supply nodes  25 . 
         [0048]    Bias contacts  29  of the P wells are coupled to a power supply circuit  72  which generates a potential VPW. Power supply circuit  72  comprises a circuit  73  (DETP) for detecting the bias current provided to the P wells. Detection circuit  73  is capable of generating a signal AP when the bias current is greater, in absolute value, than a threshold. 
         [0049]    Bias contacts  27  of the N wells are coupled to a power supply circuit  74  which generates a potential VNW. Power supply circuit  74  comprises a circuit  75  (DETN) for detecting the bias current provided to the N wells. Detection circuit  75  is capable of generating a signal AN when the bias current is greater, in absolute value, than a threshold. 
         [0050]    Power supply circuits  52 ,  72 , and  74  are powered between potentials VCC and GND provided by a power supply device, not shown, external to the chip. 
         [0051]    In case of a fault injection attack, the detection by chip  70  is similar to the detection by chip  50  of  FIG. 3 . Bias currents I 1  detected by the chip are separated from power supply currents I 2  of the normal chip activity. In the embodiment of chip  70 , bias potentials VNW and VPW may be different from power supply potentials VDD and GND, for example, to accelerate the chip operation, or to decrease its power consumption. 
         [0052]      FIG. 5A  details an embodiment of a power supply circuit  74  coupled to a bias contact  27  of an N well. Power supply circuit  74  comprises an operational amplifier  80  having its output coupled to gate G 1  of a P-channel MOS transistor PM 1 . Two series-connected resistors R 1  and R 2  couple drain D 1  of transistor PM 1  to ground, the common node between the resistors being coupled to the positive input of amplifier  80 . A regulated potential V 0  is applied to the negative input of amplifier  80 . Amplifier  80  is powered between ground GND and a node of application of a potential VCC provided by an external power supply device. Source S 1  of transistor PM 1  is coupled to potential VCC. Bias contacts  27  are coupled to drain D 1 . 
         [0053]    Detection circuit  75  of power supply circuit  74  comprises two P-channel MOS transistors PM 2  and PM 3 , forming current mirrors with transistor PM 1 , that is, having its gates G 2  and G 3  coupled to gate G 1  and its sources D 2  and D 3  coupled to source S 1 . Drain D 2  of transistor PM 2  is coupled to ground by a current source which samples a current I 3 + from drain D 2 . Drain D 3  of transistor PM 3  is coupled to ground by a current source which samples a current I 3 − from drain D 3 , current I 3 − being lower than current I 3 +. An inverter  82  couples drain D 3  to an input of an OR gate  84  having its other input coupled to drain D 2 . The activation of the output of gate  84  generates signal AN. 
         [0054]    When circuit  74  operates, a current I 3  flows through resistors R 1  and R 2 , current I 3  being selected to be between currents I 3 + and I 3 −. This current adds to bias current I 1  in transistor PM 1 , and a current I 5  equal to I 1 +I 3  flows through each of transistors PM 2  and PM 3 . 
         [0055]    In normal operation, current I 5  is between currents I 3 − and I 3 +, and output AN is deactivated. 
         [0056]    In case of an attack attempt, as soon as current I 5  comes out of the interval from I 3 − to I 3 +, the potential of drain D 2  increases or the potential of drain D 3  decreases, and output AN is activated. In other words, the appearing of a current I 1  causes a variation of the potential provided by amplifier  80  which regulates the voltage provided by power supply circuit  74 , and detection circuit  75  detects this variation to detect current I 1 . As a variation, detection circuit  75  may be replaced with any circuit capable of detecting a variation of a power supply circuit regulation potential. 
         [0057]    The difference between currents I 3  and I 3 − corresponds to the threshold of detection of a current I 1  originating from bias contact  27  and the difference between currents I 3  and I 3 + corresponds to the threshold of detection of a current I 1  flowing towards bias contact  27 . As an example, the detection thresholds are in the range from 0.2 to 2 mA. 
         [0058]      FIG. 5B  details an embodiment of a power supply circuit  72  coupled to a bias contact  29  of an N well. 
         [0059]    Power supply circuit  72  corresponds to power supply circuit  74  of  FIG. 5A , resistors R 1  and R 2  being replaced with series-connected resistors R 3  and R 4  coupling drain D 1  to a power supply circuit  86 , the common node between resistors R 3  and R 4  being coupled to the positive input of amplifier  80 . As an example, detection circuits  73  and  75  are similar. 
         [0060]    Power supply circuit  86  provides a potential lower than the ground potential, based on potential VCC and on the ground potential. Circuit  86  may be a charge pump circuit synchronized by a clock (CLK). As a variation, detection circuit  73  may be replaced with a detection circuit capable of detecting a variation of a regulation potential of circuit  86 . 
         [0061]    Specific embodiments have been described. Various alterations, modifications, and improvements will readily occur to those skilled in the art. In particular, although in the described embodiments, the bias currents of P wells  33  and the bias currents of N wells  3  are simultaneously monitored by two detection circuits, variations are possible where the bias current of wells of a single conductivity type is monitored by a single detection circuit. 
         [0062]    Further, although, in the described embodiments, the secure chips comprise digital circuits comprising MOS transistors  6  and  12 , identically protected chips may also comprise analog circuits, for example, comprising components such as bipolar transistors, resistors, or diodes, the important point being that the chip comprises biased wells. 
         [0063]    Further, although, in the described embodiments, a P-type doped substrate  5  has been provided, variations are possible where substrate  5  is replaced with an N-type doped substrate or with a support of silicon-on-insulator type, or also with a support made of another semiconductor. 
         [0064]    Further, although specific detection circuits have been detailed in the described embodiments, other detection circuits capable of detecting a bias current are possible. 
         [0065]    Various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step. In particular, each of detection circuits  73  and  75  of the embodiment of a secure chip of the second type may replace one or the other of detection circuits  57  and  61  of the embodiment of a secure chip of the first type. 
         [0066]    Further, embodiments adapted to integrated circuits of a first type and of a second type have been described. What has been described of course applies to other types of integrated circuit technologies, comprising various types of wells. 
         [0067]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. 
         [0068]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.