Abstract:
A capacitive transducer and a readout circuit for processing a signal from a capacitive transducer. The readout circuit includes a high gain circuit element, two summing amplifiers and two feedback path. The high gain circuit element generates an amplified transducer signal, and the summing amplifiers sum the amplified transducer signal with a positive reference voltage and the negative reference voltage, respectively, to generate a first summation signal and a second summation signal. The feedback paths feed back the summation signals to the transducer. Output circuitry generates an output signal based on the summation signals. The high gain circuit element can be a switched capacitor integrator. The output circuitry can generates the output signal based on the first and second summation signals.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 13/220,306, filed on Aug. 29, 2011, entitled “Readout Circuit for Self-Balancing Capacitor Bridge,” which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     This patent relates to capacitive transducers, and more particularly to techniques for attenuation of unwanted disturbances in capacitive transducers. 
     Transducers convert a general physical quantity (for example, acceleration, pressure, etc.) to quantities that can be processed by electronic circuits. In particular, capacitive transducers produce a change of capacitance, corresponding to the magnitude of the measured input signal. Readout circuits for capacitive transducers transform the capacitance change produced by the transducer to an electrical signal. In the process, the circuits apply voltage waveforms to the transducer electrodes. 
     A capacitive accelerometer, a capacitive transducer for measuring acceleration, includes a mechanical sensing element and a readout circuit.  FIG. 1  illustrates an exemplary embodiment of a mechanical sensing element  100  of a capacitive accelerometer. In this embodiment, the mechanical sensing element  100  includes a mass  102  suspended between a first spring  104  and a second spring  106 , a first electrode  110  and a second electrode  112 . A proximal end of the mass  102  is coupled to the first spring  104  and a distal end of the mass  102  is coupled to the second spring  106 . The first spring  104  has two ends; a first end coupled to the proximal end of the mass  102  and a second end coupled to a substrate. The second spring  106  has two ends; a first end coupled to the distal end of the mass  102  and a second end coupled to the substrate. A common electrode  108  is coupled to the mass  102  and moves with the mass  102  relative to the substrate. The first and second electrodes  110 ,  112  are stationary relative to the substrate. In this embodiment a positive reference voltage V S  is applied to the first electrode  110  and the negative reference voltage −V S  is applied to the second electrode  112 . A first variable capacitor C 1  is formed between the first electrode  110  and the common electrode  108 , and a second variable capacitor C 2  is formed between the second electrode  112  and the common electrode  108 . 
     In this embodiment, when the system is at rest, there is a substantially equal nominal gap g 0  between the first electrode  110  and the common electrode  108  and between the second electrode  112  and the common electrode  108 , creating substantially equal capacitances in the first variable capacitor C 1  and the second variable capacitor C 2 . An input acceleration moves the mass  102  relative to the substrate which varies the gaps between the electrodes and varies the capacitance of the variable capacitors C 1 , C 2 . Acceleration in the direction of arrow  120  deflects the mass  102  a distance Δx that is proportional to the input acceleration. This movement of the mass  102  increases the distance between the first electrode  110  and the common electrode  108  to g 0 +Δx, and decreases the distance between the second electrode  112  and the common electrode  108  to g 0 −Δx, which changes the capacitance of capacitors C 1  and C 2 . The capacitance C of variable capacitors C 1  and C 2  can be determined by: 
                     C     1   /   2       =         ɛ   0     ⁢   A         g   0     ±     Δ   ⁢           ⁢   x                 (   1   )               
where ∈ 0  is dielectric permittivity, A is the area of the capacitive plates (which extend into the paper), g 0  is the nominal gap and Δx is the displacement due to the acceleration. The readout circuit determines the value of Δx based on the capacitance change in capacitors C 1  and C 2 .
 
       FIG. 2  is a schematic of an exemplary embodiment of a self-balancing capacitive bridge  200 . The switched-capacitor implementation shown in  FIG. 2  has the advantage of straightforward DC biasing of the input without the need for a high resistance path, as well as a stable and well-defined transfer function over process and temperature. It also provides a discrete-time output signal, which can be digitized directly by an analog-to-digital converter (ADC).  FIG. 2  shows a single-ended embodiment of a self-balancing bridge. 
     The self-balancing bridge  200  includes a sensor core  210  with two variable capacitors, C 1  and C 2 , and a readout or interface circuit  220 . The sensor core  210  represents a capacitive sensor element, for example the sensing element  100  shown in  FIG. 1  or one of various other capacitive sensor elements known in the art. 
     The readout circuit  220  includes a forward path that passes the output of the sensor core  210  through an integrator  222 , which provides gain, to the output V 0 . In this embodiment, the integrator  222  includes an amplifier  224  with an integrating capacitor C i . The inverting input of the amplifier  224  is coupled to the common node M between the variable capacitors C 1  and C 2 , the non-inverting input of the amplifier  224  is coupled to ground, and the output of the amplifier  224  provides the output voltage V o . The integrating capacitor C i  couples the inverting input of the amplifier  224  to the output of the amplifier  224 . 
     The self-balancing bridge  200  also includes a first feedback path  230  and a second feedback path  240  that feedback the output voltage V o  to the sensor core  210 . The first feedback path  230  feeds back the output voltage V o  through a first inverting amplifier  232  to a first summing node  234 . The first summing node  234  sums the inverted output voltage −V 0  and inverted reference voltage −V S , and outputs the resulting voltage −V S −V 0  to the first variable sensor capacitor C 1 . The second feedback path  240  feeds back the output voltage V o  through a second inverting amplifier  242  to a second summing node  244 . The second summing node  244  sums the inverted output voltage −V 0  and reference voltage V S , and outputs the resulting voltage V S −V 0  to the second variable sensor capacitor C 2 . 
     The self-balancing bridge  200  tries to equalize the absolute charge on the two sensor capacitors, C 1  and C 2 . Under these conditions the output voltage is proportional to the ratio between the difference and the sum of the measured capacitors: 
                     V   o     =       -     V   S       ⁢         C   1     -     C   2           C   1     +     C   2                   (   2   )               
Measuring the above ratio is of interest for a variety of applications, acceleration sensors being only one particular example.
 
     In addition to producing the result in Eq. (2), equalizing the absolute charge on the transducer capacitors has the advantage of creating equal electrostatic forces, acting on the moving plates of the variable capacitors, C 1  and C 2 , in opposite directions. The net force on the transducer is reduced; hence the interface circuit does not disturb the measurement by inducing spurious deflection of the capacitor plates. In order for this condition to be fulfilled, however, the absolute charge on the transducer capacitors must be maintained equal at any given point of time. Implementing the summing nodes to simply equalize the time-average charge on the transducer capacitors does not maintain equal charge at all times during operation. Applying the same absolute voltage to the sensor capacitors results in different absolute charges, and therefore different electrostatic forces when C 1  and C 2  are different. The charge balance is achieved only on average, which does not result in zero net force. Using active summing circuits for the summing amplifiers  234 ,  244  helps maintain the correct voltage for equalizing the charge on C 1  and C 2 . 
     However, it is well known that amplifiers introduce disturbances, such as noise and offset, to the signals they process. While switched-capacitor techniques such as Correlated Double-Sampling (CDS) can eliminate low-frequency noise and offset, the broad-band noise, which is aliased near DC by the sampling process, cannot be rejected. Furthermore, CDS roughly doubles the amount of broad-band noise, which appears near DC. It would be desirable to attenuate these unwanted disturbances so that they have reduced impact on the output measurement of the circuit. 
     SUMMARY OF THE INVENTION 
     A readout circuit is disclosed for processing a transducer signal from a capacitive transducer and producing a circuit output signal. The readout circuit includes a high gain circuit element, two summing amplifiers implemented by active circuitry, two feedback paths and output circuitry. The high gain circuit element receives the transducer signal and generates an amplified transducer signal. The first summing amplifier sums the amplified transducer signal with a positive reference voltage and generates a first summation signal. The second summing amplifier sums the amplified transducer signal with a negative reference voltage and generates a second summation signal. The negative reference voltage has substantially the same magnitude but opposite polarity of the positive reference voltage. The first feedback path feeds back the first summation signal to the capacitive transducer, and the second feedback path feeds back the second summation signal to the capacitive transducer. The output circuitry generates the circuit output signal based on the first summation signal and the second summation signal. The high gain circuit element can be a switched capacitor integrator. Each of the first and second summing amplifiers can include an operational amplifier, and the input signals to the summing amplifier can be coupled to the inverting input of the respective operational amplifier. The readout circuit can also include an inverting amplifier that inverts the amplified transducer signal. The output circuitry can generate the circuit output signal as the average of the first summation signal and the second summation signal. 
     A readout circuit is disclosed for processing a transducer signal from a capacitive transducer and producing a circuit output signal, where the readout circuit includes a forward path and two feedback paths. The forward path includes a high gain circuit element and two summing amplifiers. The high gain circuit element receives the transducer signal and generates an amplified transducer signal. The summing amplifier sums the amplified transducer signal with a reference voltage and generates a summation signal. The first summing amplifier sums the amplified transducer signal with a positive reference voltage and generates a first summation signal. The second summing amplifier sums the amplified transducer signal with a negative reference voltage and generates a second summation signal. The negative reference voltage has substantially the same magnitude but opposite polarity of the positive reference voltage. The first feedback path feeds back the first summation signal to the capacitive transducer, and the second feedback path feeds back the second summation signal to the capacitive transducer. Output circuitry generates the circuit output signal based on the summation signals. The high gain circuit element can be a switched capacitor integrator. The summing amplifier can include an operational amplifier. At least one of the summing amplifiers can be implemented by active circuitry. The readout circuit can also include an inverting amplifier that inverts the amplified transducer signal. The output circuitry can generate the circuit output signal as the average of the first and second summation signals. 
     A capacitive transducer system is disclosed that includes a capacitive sensing element, a high gain circuit element, first and second summing amplifiers, first and second feedback paths and output circuitry. The capacitive sensing element generates a transducer signal based on a physical quantity. The high gain circuit element receives the transducer signal and generates an amplified transducer signal. The first summing amplifier, implemented by active circuitry, sums the amplified transducer signal with a reference voltage and generates a first summation signal. The second summing amplifier, implemented by active circuitry, sums the amplified transducer signal with a negative reference voltage and generates a second summation signal. The negative reference voltage has substantially the same magnitude but opposite polarity of the reference voltage. The first feedback path feeds back the first summation signal to the capacitive sensing element. The second feedback path feeds back the second summation signal to the capacitive sensing element. The output circuitry generates a circuit output signal based on the first summation signal and the second summation signal. The high gain circuit element can be a switched capacitor integrator. The system can also include an inverting amplifier that inverts the amplified transducer signal. The output circuitry can generate the circuit output signal as the average of the first and second summation signals. The capacitive sensing element can include a sensor core including a first variable capacitor having a first movable capacitive plate and a second variable capacitor having a second movable capacitive plate, where the first movable capacitive plate is coupled to the second movable capacitive plate. 
     The capacitive transducer system can be a fully differential system where the capacitive sensing element includes first and second capacitive cores, and differential signals are generated. The transducer signal includes a first transducer signal generated by the first capacitive core and a second transducer signal generated by the second capacitive core. The amplified transducer signal is based on the first and second transducer signals. The first feedback path feeds back the first summation signal to the first capacitive core and to the second capacitive core. The second feedback path feeds back the second summation signal to the first capacitive core and to the second capacitive core. The capacitors of the first and second capacitive cores can be tuned to react substantially identically. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above mentioned and other features and objects of this invention, and the manner of attaining them, will become more apparent and the invention itself will be better understood by reference to the following description of embodiments of the invention taken in conjunction with the accompanying drawings, wherein: 
         FIG. 1  illustrates an exemplary embodiment of a mechanical sensing element of a capacitive transducer; 
         FIG. 2  is a schematic of an exemplary embodiment of a self-balancing capacitive bridge; 
         FIG. 3  is a schematic of an exemplary implementation of a summing amplifier implemented by an active circuit; 
         FIG. 4  is a schematic of an exemplary capacitive transducer system and illustrates the introduction of a disturbance V n1  from one of the summing amplifiers; 
         FIG. 5  shows a simplified feedback system corresponding to the system of  FIG. 4 ; 
         FIG. 6  shows a feedback system with a first input signal S A  that is amplified by forward-path gain block “a” and a second input signal S B  that is introduced in the forward path after the gain block “a”; 
         FIG. 7  is a schematic of an exemplary capacitive transducer system in which the summing amplifiers are located in the forward path of the system after the high gain of the switched-capacitor integrator; and 
         FIG. 8  is a schematic of an exemplary fully-differential capacitive feedback system in which the summing amplifiers are located in the forward path of the system after the high gain block. 
     
    
    
     Corresponding reference characters indicate corresponding parts throughout the several views. Although the exemplification set out herein illustrates embodiments of the invention, in several forms, the embodiments disclosed below are not intended to be exhaustive or to be construed as limiting the scope of the invention to the precise forms disclosed. 
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Using active circuits to implement the summing nodes in  FIG. 2  provides better equalization of the absolute charge on the transducer capacitors C 1  and C 2 , which reduces the impact of the readout or interface circuit on the sensor. However, using active amplifiers for implementing the summing nodes introduces unwanted disturbances, noise and offset, to the signals they process. Attenuating the disturbances introduced by the active amplifiers reduces the impact of these disturbances on the output signal. 
       FIG. 3  shows an exemplary implementation of a summing amplifier  300  implemented by an active circuit that accepts input signals V S  and V 0  and produces an output signal V X . In this case, V S  is the system reference voltage and V 0  is the system output voltage. The summing amplifier  300  also introduces an unwanted disturbance signal V n  that is included in the output signal V X . The offset cancellation has been omitted for simplicity. Conventional analysis of switched-capacitor amplifiers shows that the input signals V S  and V 0  experience a gain “α” to the output, while the disturbance V n  is amplified by (1+2α)/α. 
       FIG. 4  shows an exemplary capacitive transducer system  400  and illustrates the introduction of a disturbance V n1  from one of the summing amplifiers. The system  400  includes a sensing element  402 , a forward path  410  and two feedback paths  420 ,  430 . The forward path  410  takes the output signal from the sensing element  402 , passes it through a switched-capacitor integrator  412  and provides it as an output signal V 0 . The integrator  412  can provide high gain to the signals passing through it in the forward path  410 . Each of the feedback paths takes the output signal V 0  and feeds it back to the sensor element  402 . The first feedback path  420  takes the output signal V 0 , passes it through an inverting amplifier  422 , and a summing amplifier  424 . The summing amplifier  424  sums a negative reference voltage −V S  with the inverted output signal −V 0  and introduces an unwanted disturbance signal V n1 , and outputs a first combined signal with the disturbance V n1 . The second feedback path  430  takes the output signal V 0 , passes it through an inverting amplifier  432 , and a summing amplifier  434 . The summing amplifier  434  sums the positive reference voltage V S  with the inverted output signal −V 0  and introduces another unwanted disturbance signal V n2 , and outputs a second combined signal with the disturbance V n2 . The transfer function of the system  400  for the reference voltage V S  and the first disturbance V n1  (ignoring the second disturbance V n2 ) can be calculated as: 
                     V   o     =         -     V   S       ⁢         C   1     -     C   2           C   1     +     C   2           +         (     1   +     2   ⁢   α       )     α     ⁢     V     n   ⁢           ⁢   1       ⁢       C   1         C   1     +     C   2                     (   3   )               
For the particular case of α=1 and small displacements (C 1 ≈C 2 ), the reference voltage V S  disappears and the disturbance V n1  appears at the output with a gain of 3/2. Thus, this configuration of the summing amplifier does not provide the desired attenuation of the unwanted disturbances V n .
 
       FIG. 5  shows a simplified feedback system  500  corresponding to the system  400  of  FIG. 4 . The system  500  has forward-path gain “a” and feedback coefficient “f”. The feedback system  500  has two inputs, S A  and S B , and an output S 0 . The input signal S B  is introduced in the feedback path, and both input signals S A  and S B  are amplified by the high-gain block “a”. The transfer function for system  500  is: 
                     S   o     =         -     a     1   +   af         ⁢     S   A       -       af     1   +   af       ⁢     S   B                 (   4   )               
In a typical feedback system a&gt;&gt;1 and f&lt;=1. For the case of f=1, the transfer function for the system  500  simplifies to:
 
 S   0   ≈−S   A   −S   B   (5)
 
We see that in the system  500  both S A  and S B  appear at the output with equal weight. If S A  is the signal we are interested in and S B  is an unwanted disturbance, then we are not achieving the desired attenuation of the unwanted disturbance S B  in the feedback system  500 .
 
       FIG. 6  shows another feedback system  600  that has forward-path gain “a” and feedback coefficient “f”. The system  600  also has two inputs, S A  and S B , and an output S 0 . However in the system  600 , unlike the system  500 , the input signal S B  is introduced in the forward path after the high-gain block “a”. The transfer function of the system  600  is: 
                     S   o     =         -     a     1   +   af         ⁢     S   A       +       1     1   +   af       ⁢     S   B                 (   6   )               
Again assuming a&gt;&gt;1 and f=1, the transfer function of the system  600  simplifies to:
 
 S   0   ≈S   A +(1/ a ) S   B   (7)
 
Eq. (7) shows that the signal S A , introduced before the high-gain block “a”, appears directly at the output, while the signal S B , introduced after the high-gain block, is highly attenuated. Thus, it would be desirable to attenuate the disturbances introduced by the summing amplifiers of the measurement circuit before they reach the output, like the signal S B , instead of allowing these disturbances to reach the output largely unattenuated, like the signal S A , to reduce the impact of these disturbances on the measurements of the system.
 
     Comparing equations (5) and (7) we see that in the system  500  the unwanted signal S B  will appear directly at the output with the same attenuation as the useful signal S A , while in the system  600  the unwanted signal S B  will be attenuated by a&gt;&gt;1 without attenuation of the useful signal S A . Therefore, it would be desirable to implement a system that attenuates the unwanted disturbances like the system  600 . 
     In the feedback systems of  FIGS. 2 and 4 , the summing amplifiers appear in the feedback path. Therefore, the disturbance V n  introduced by the summing amplifiers behaves similarly to S B  in  FIG. 5  and is amplified by the high gain in the forward path. The feedback system of  FIG. 4  can be redesigned in a way that makes the disturbance V n , behave similarly to S B  of  FIG. 6 , and therefore does not amplify the disturbance V n  by the high gain in the forward path. This can be achieved by placing the summing amplifiers in the forward path of the feedback system after the high gain block. 
       FIG. 7  shows an exemplary system  700  in which the summing amplifiers are located in the forward path of the system after the high gain of the switched-capacitor integrator. The system  700  includes a sensing element  702 , a forward path  710  and two feedback paths  720 ,  730 . The forward path  710  takes the output signal from the sensing element  702 , passes it through a switched-capacitor integrator  712  and an inverting amplifier  714  and produces an intermediate output signal V 0 ′, then the forward path  710  splits into a first branch  740  and a second branch  750 . The first branch  740  takes the intermediate output signal V 0 ′ and passes it to a summing amplifier  742 . The summing amplifier  742  sums a negative reference voltage −V S  with the intermediate output signal V 0 ′ and introduces an unwanted disturbance signal V n1 , and outputs a first combined signal V 0 ′−V S  which includes the disturbance V n1 . The second branch  750  takes the intermediate output signal V 0 ′ and passes it to a summing amplifier  752 . The summing amplifier  752  sums the positive reference voltage V S  with the intermediate output signal V 0 ′ and introduces an unwanted disturbance signal V n2 , and outputs a second combined signal V 0 ′+V S  which includes the disturbance V n2 . The output signals of the first branch  740  and the second branch  750  are combined and halved to provide an output signal V 0 . The first feedback path  720  takes the output signal V 0 ′−V S  from the first branch  740  and feeds it back to the sensor element  702 . The second feedback path  730  takes the output signal V 0 ′+V S  from the second branch  750  and feeds it back to the sensor element  702 . The first and second branches  740 ,  750  of the forward path  710  also show a summing amplifier gain α. 
     The integrator  712  can provide high gain to the signals passing through it in the forward path  710 . Like the feedback system  600 , the unwanted disturbances are introduced in the forward path  710  after the integrator  712 . The transfer function for the signal and first branch disturbance in the system  700  is: 
     
       
         
           
             
               
                 
                   
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     After normalizing the output of the systems in  FIGS. 4 and 7  to the same signal level (first terms in Eq. (3) and Eq. (8)), the relative contribution of the disturbance V n1  (second term in Eq. (3) and Eq. (8)) to the output of the two systems can be calculated. as: 
     
       
         
           
             
               
                 
                   
                     
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     The following numerical example shows the additional attenuation of the disturbance in the system  700  of  FIG. 7  versus the system  400  of  FIG. 4 . A parallel-plate transducer (for example, an accelerometer) can have a typical maximum signal level of (C 1 −C 2 )/(C 1 +C 2 )=0.2. This relationship can be rearranged to yield C 1 =(3/2)C 2 , and substituting this into Eq. (9) yields V 0     —     n1     —     new/ V 0     —     n1     —     old =⅙. Thus, the system  700  attenuates the contribution of the summing amplifier disturbance V n1  by a factor of 6 relative to the system  400 . This analysis naturally applies to the disturbances introduced by both summing amplifiers. 
     Placement of summing amplifiers in the forward path of a capacitive feedback system after a high gain block can also be done in a fully-differential system, such as the exemplary system  800  shown in  FIG. 8 . The system  800  includes a sensing element  802 , a dual forward path  810  and two dual feedback paths  820 ,  830 . In the system  800 , the transducer  802  is implemented as two separate cores. A first core C 1  includes variable capacitors C 1A  and C 1B , a second core C 2  includes variable capacitors C 2A  and C 2B . The corresponding capacitors of the two cores react to the input signal in a substantially identical way (i.e., C 1A =C 1B  and C 2A =C 2B ). However, the electrical signals processed by the two cores have opposite polarity. 
     The forward path  810  takes the output signals from the cores of the sensing element  802 , passes them through a capacitor integrator  812  and produces intermediate output signals, then the forward path  810  splits into a first branch  840  and a second branch  850 . Unlike the switched-capacitor integrator  712  depicted in  FIG. 7  wherein the integrator  712  is a single-ended amplifier, the capacitor integrator  812  depicted in  FIG. 8  is a fully differential amplifier. Thus, the capacitor integrator  812  does not require a separate inverting amplifier. The first branch  840  takes a first intermediate output signal and passes it to a summing amplifier  842 . The summing amplifier  842  sums a positive reference voltage V S  with the first intermediate output signal and introduces unwanted disturbances V n1 , and outputs a first combined signal −V 0 +V S  which includes the disturbances V n1 . The second branch  850  takes an intermediate output signal and passes it to a summing amplifier  852 . The summing amplifier  852  sums the inverted reference voltage −V S  with the intermediate output signal and introduces unwanted disturbances V n2 , and outputs a second combined signal −V 0 −V S  which includes the disturbances V n2 . The output signals of the first branch  840  and the second branch  850  are combined and halved to provide an output signal V 0 . The first feedback path  820  takes the output signal −V 0 +V S  from the first branch  840  and feeds it back to the sensor element  802 . The second feedback path  830  takes the output signal −V 0 −V S  from the second branch  850  and feeds it back to the sensor element  802 . The system  800  assumes summing amplifier gain α=1 for simplicity, however the principle applies to the general case as well. 
     Like the system  700 , the output signals from the cores of the sensing element  802  pass through the integrator  812  which can provide high gain, but the unwanted disturbances from the summing amplifiers  842 ,  852  do not pass through the integrator  812  in the forward path  810 . Thus the unwanted disturbances from the summing amplifiers are highly attenuated. 
     While this invention has been described as having an exemplary design, the present invention may be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles.