Abstract:
A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to the field of systems on-chip, and specifically to a method and apparatus for providing a modular system on-chip device. 
     2. Background Information 
     A system on-chip device may include a core unit, designed by a first vendor, to interface to a number of different, and possibly proprietary, bus architectures. In this type of system, the core unit must include a specific logic circuit to interface to each bus architecture. Thus, each time a core unit of a first vendor is implemented in a system having a bus architecture of a second vendor, the core unit must implement the appropriate interface logic. This, however, is an inefficient solution for vendors because a core system has to be modified each time it has to interface to a different bus architecture. The present invention solves this problem by providing a modular on-chip interface device. 
     The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block diagram of a system on-chip (SoC) device, according to an example of the present invention. 
     FIG. 2 illustrates a block diagram of the system interface (SI) block, according to an example of the present invention. 
     FIG. 3 illustrates a block diagram of a system on-chip device, according to an example of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 illustrates a block diagram of a system on-chip (SoC) device  100 , according to the present invention. Referring to FIG. 1, the SoC device  100  includes one or more cores  105   1 - 105   A , where “A” is a positive whole number, having respective core systems  110   1 - 110   A  ( 110 ) and standard interfaces  115   1 - 115   A . The core systems may be any type of systems including proprietary (IP) systems. For example, the core systems  110   1 - 110   A  may include a central processing unit (e.g., microprocessor, microcontroller, digital signal processor, reduced instruction set computer processor, etc.), memory (e.g., random access memory, read only memory, etc.), peripheral devices (e.g., network card, serial bus and interface, input/output devices, etc.), direct memory access, and combinations thereof. 
     In addition, the SoC device  100  includes system interface (“SI”) blocks  125   1 - 125   A  each having first and second interfaces. The first interfaces of SI blocks  125   1 - 125   A  include standard interfaces  120   1 - 120   A  which interface to standard interfaces  115   1 - 115   A  of cores  120   1 - 105   A . For example, one standard interface is a VC interface such as the On-Chip Bus Virtual Component Interface Standard (Version 1.0 (OCB VCI 2 1.0) promulgated by the Virtual Socket Interface Alliance (VSIA). 
     The second interfaces of SI blocks  125   1 - 125   A  interface to a system bus  140 . The system  140  includes a bus arbiter  145  which provides arbitration among devices on the system bus  140 . The SI blocks  125   1 - 125   A  allow the core systems  110   1 - 110   A , which may be proprietary systems, to communicate with the system bus  140  over a standard interface. That is, the core systems  110   1 - 110   A , which may comprise a number of different architectures and protocols, can communicate with a single bus (i.e., system bus  140 ) by interfacing to a standard interface. The system bus  140  may be of any type including, but not limited or restricted to, a peripheral component interconnect (PCI) bus, a proprietary bus such as, for example, an SIP bus developed by Phoenix Technologies, Ltd., of San Jose, Calif., (now known as InSilicon Corporation, and the like. 
     The system bus  140  is coupled to a first interface of a system bus bridge  150 . The system bus bridge  150  includes a second interface which is a standard interface  155  and is coupled to an on-chip bus (“OCB”) bridge  160 . The OCB bridge  160  also includes a standard interface  165  for interfacing to the system bus bridge  150  by way of the standard interface  155 . The OCB bridge  160  is in turn coupled to an on-chip bus  170 . The system bus bridge  150  and OCB bridge  160  provide a master/slave interface between the system bus  140  and the OCB  170 . The OCB  170  may be of any bus architecture including, but not limited or restricted to, a PCI bus, an ARM advanced microcontroller bus architecture (“AMBA”), etc. 
     By providing system bus bridge  150  and OCB bridge  160 , the present invention allows vendors, using their own proprietary on-chip bus  170 , to communicate to core systems  110   1 - 110   A  by way of the system bus  140 , by simply interfacing to a standard interface. This simplifies the design and provides a modular approach for vendors. That is, vendors can communicate with processing elements within the device  100  (e.g., core system  110 ) by simply interfacing to the standard interface, without the need to interface to the core system directly, to give a standard plug and play effect. In one example, the standard interface is a VC interface such as the On-Chip Bus Virtual Component Interface Standard (Version 1.0 (OCB VCI 2 1.0) is the most recent version available) promulgated by the Virtual Socket Interface Alliance (VSIA). Of course, other standard interfaces could be used. 
     FIG. 2 illustrates a block diagram of the SI block  125 , according to one embodiment of the present invention. Referring to FIG. 2, the SI block  125  includes signal lines  210  which interface to the standard interface  120 , and signal lines  215  for interfacing to the system bus  140 . The SI block  125  includes an address translation logic  220 , an address decoder  225 , and address/data first-in, first-out devices (“FIFOs”)  230 . The address translation logic  220  performs address conversion, translating a first address on a first bus to a second address on a second bus, and vice versa. The address decoder  225  determines whether an incoming address on the first bus is targeted to a device on the second bus. The address decoder  225  includes one or more registers which contain valid address ranges of the first and second buses. If an incoming address on the first bus falls within the address range, the SI block  125  generates the necessary signals for initiating a transaction on the second bus, otherwise, the SI block  125  ignores the address. The address/data FIFOs  230  include a plurality of FIFOs which provide temporary buffering of address and data in both directions. 
     The SI block  125  further includes a system bus interface block  235  which interfaces with the system bus  140 . For example, if the system bus  140  is a proprietary bus, the SI block  235  will generate and receive signals according to the proprietary bus specifications. In particular, the system bus interface block  235  is responsible for monitoring requests on the system bus targeted to the SI block  235 , for initiating and completing accesses to the system bus  140 , and generating and/or passing through all control signals of the system bus  140 . In one embodiment, the SI block  235  interfaces with the bus arbiter  145  via request and grant lines. 
     The system bus bridge  150  is substantially similar to the SI block  125 . That is, the system bus bridge  150  includes the address translation logic  220 , address decoder  225 , and system bus interface  235  as shown in FIG.  2 . The system bus bridge  150  may or may not include the address/data FIFOs  230  of FIG. 2 depending on a number of factors. For example, if the on-chip bus  170  is faster than the system bus  140 , then FIFOs from the system bus  140  the on-chip bus  170  are not needed since a device on the on-chip bus can drain data faster than a device on the system bus  140  can source data. 
     FIG. 3 illustrates a block diagram of a system on-chip device  300 , according to another embodiment of the present invention. Referring to FIG. 3, the device  300  includes a universal serial bus (“USB”) core system  305 , a 1394 serial bus core system  310 , and an Ethernet core system  315 , all of which include input/output (“I/O”) ports, designated by numeral  320 , for access off-chip. Core systems  305 ,  310 , and  315  are coupled to a proprietary bus  340  through respective SI blocks  325 ,  330 , and  335 . In this embodiment, the proprietary bus  340  is a system IP (“SIP”) bus, owned by the assignee of the present invention. Each of the core systems  305 ,  310 , and  315  include a VC interface which interfaces to the VC interface of the respective SI blocks  325 ,  330 , and  335 . Each of the SI blocks includes logic which interfaces with the SIP bus  340 . This allows, the core systems  305 ,  310 , and  315 , which may be manufactured by three separate entities, to interface to the VC interface, without consideration for the type of proprietary bus  340  used. 
     The SIP bus  340  is coupled to a SIP bridge  345  which has a first SIP interface. The SIP bridge  345  has a second VC interface that is coupled to a first VC interface of an AMBA bridge  350 . In turn, the AMBA bridge  350  includes a second, AMBA interface which interfaces to an AMBA bus  355 . An ARM processor  360  and a number of AMBA devices  365  and  370  are coupled to the AMBA bus  355 . The AMBA bus  355  also has access external to the device  300  for coupling to external AMBA devices  355 . This implementation further allows a vendor, having its own bus architecture (e.g., AMBA bus architecture) to interface to the SIP bus  340 , and thus the core systems  305 ,  310 , and  315  by simply providing a bridge that interfaces between the AMBA bus  355  and the VC interface. The vendor only needs to know the address map of the core systems  305 ,  310 , and  315  in order to interface to the same. 
     Embodiments of the present invention offer a unique interface which allows any vendor, customer, etc. to use their own proprietary bus to interface to the core systems by simply designing a bridge that interfaces between their proprietary bus and the standard interface (e.g., VC interface). The advantages include simpler design efforts, plug-and-play capability, fully integrated system environment on a chip, while maintaining system on-chip performance and bandwidth. 
     While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.