Abstract:
A Static Random Access Memory (SRAM) cell is provided with an improved robustness to radiation induced soft errors. The SRAM cell comprises the following elements. First and second storage nodes are configured to store complementary voltages. Access transistors are configured to selectively couple the first and second storage nodes to a corresponding bit line. Drive transistors are configured to selectively couple one of the first and second storage nodes to ground. Load transistors are configured to selectively couple the other one of the first and second storage nodes to a power supply. At least one stabilizer transistor is configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes. The redundant storage node is capable of restoring the first or second storage nodes in case of a soft error.

Description:
[0001]    The present invention relates generally to Static Random Access Memory (SRAM) cells and specifically to SRAM cells that limit the effect of radiation induced soft errors. The present application claims priority from U.S. Provisional Application No. 60/853,034, filed Oct. 20, 2006. 
     
     BACKGROUND 
       [0002]    SRAM cells are one of the most popular ways to store data in electronic systems. Further, embedded SRAM cells are a vital building block in integrated circuits. SRAM cells are typically preferred because of higher speed, robust design, and ease of integration. However, SRAM cells, in general, occupy a significantly large portion of a chip&#39;s die area, making it an important block in terms of yield, reliability and power consumption. With increasing demand for highly integrated System on Chip (SoC) design, improving various aspects of embedded SRAM cells has received significant interest. 
         [0003]    Specifically, nano-metric semiconductor technologies are becoming highly sensitive to transients induced by ionizing radiation consisting of energetic cosmic neutrons and alpha particles. These particles generate a large number of electron hole pairs, which may be collected by sensitive nodes resulting in data upset, also known as soft errors (SE). Accordingly, a number of solutions have been proposed to improve the robustness of the SRAM cell. 
         [0004]    For example, referring to  FIG. 2 , a schematic diagram of an SRAM cell having improved robustness to radiation induced soft errors is shown. In the proposed solution, the SRAM includes a coupling capacitor. The coupling capacitor significantly increases the critical charge (Qc), which is the minimum charge required to cause an soft error. However, adding a large, area efficient coupling capacitor requires a special semiconductor manufacturing process. Therefore the proposed SRAM cell is not easily integrated with common Complementary metal-oxide-semiconductor (CMOS) digital circuits. As a consequence, for Application Specific Integrated Circuits (ASICs) where embedded SRAM cells are widely realized using standard CMOS process, it is rather difficult to implement. 
         [0005]    Referring to  FIG. 3 , a schematic diagram of an alternate SRAM cell having improved robustness to soft errors is shown. In the proposed solution, a soft error robust data latch is implemented. The latch is immune to single node upsets. However, implementing the solution as an SRAM cell with differential ports requires additional transistors making it expensive. 
         [0006]    Technology scaling is making SRAM cells susceptible to radiation induced soft errors. Therefore, building a soft error robust SRAM cell is becoming a high priority. Further, it is desirable to improve the cell immunity against soft errors while limiting the number of extra transistors. Reducing the number of transistors allows the SRAM cell to occupy less space, which permits higher cell density. 
       SUMMARY OF THE INVENTION 
       [0007]    In accordance with an aspect of the present invention there is provided a Static Random Access Memory (SRAM) cell comprising: first and second storage nodes configured to store complementary voltages; access transistors configured to selectively couple the first and second storage nodes to a corresponding bit line; drive transistors configured to selectively couple one of the first and second storage nodes to ground; load transistors configured to selectively couple the other one of the first and second storage nodes to a power supply; and at least one stabilizer transistor configured to provide a corresponding redundant storage node and limit feedback between the first and second storage nodes, the redundant storage node being capable of restoring the first or second storage nodes in case of a soft error. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    Embodiments of the present invention will now be described by way of example only with reference to the following drawings in which: 
           [0009]      FIG. 1  is a schematic drawing of a standard SRAM cell (prior art); 
           [0010]      FIG. 2  is a schematic drawing of a proposed SRAM having improved robustness to radiation induced soft errors (prior art); 
           [0011]      FIG. 3  is a schematic drawing of an alternate proposed SRAM having improved robustness to radiation induced soft errors (prior art); 
           [0012]      FIG. 4  is a schematic drawing of a soft error robust (SER) SRAM cell in accordance with one embodiment; 
           [0013]      FIG. 5  is a schematic drawing of a SER SRAM cell in accordance with an alternate embodiment; 
           [0014]      FIG. 6  is a schematic drawing of a SER SRAM cell in accordance with yet an alternate embodiment; and 
           [0015]      FIG. 7  is a schematic drawing of a SER SRAM cell in accordance with yet an alternate embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0016]    For convenience, like numerals in the description refer to like structures in the drawings. Referring to  FIG. 1 , a standard six-transistor SRAM cell is illustrated generally by numeral  100 . The SRAM cell  100  comprises a pair of n-type drive transistors N 1  and N 2  and a pair of p-type load transistors P 1  and P 2  in a cross-coupled configuration. A further pair of n-type access transistors N 3  and N 4  couples the cell  100  to a complementary bit-line pair BL and BLB. The sources of the drive transistors N 1  and N 2  are coupled to ground, and the sources of the load transistors P 1  and P 2  are coupled to a supply voltage V DD . 
         [0017]    The SRAM cell  100  is coupled to the bit-line pair BL and BLB in a response to a word-line control signal WL from a row decoder (not shown). Accordingly, when the word-line control signal WL is active, the SRAM cell  100  is electrically connected to the bit-line pair BL and BL. 
         [0018]    Referring to  FIG. 4 , a soft error robust (SER) SRAM cell in accordance with an embodiment of the invention is illustrated generally by numeral  400 . The SER SRAM cell  400  is similar to SRAM cell illustrated in  FIG. 1 . For ease of description, the node at the junction of the drain of load transistor P 1  and the source of drive transistor N 1  will be referred to as storage node A. Similarly, the node at the junction of the drain of load transistor P 2  and the source of drive transistor N 2  will be referred to as storage node B. The nodes A and B are referred to as storage node because they store respective voltages when the access transistors N 3  and N 4  are turned off, as is known in the art. 
         [0019]    However, in the present embodiment, the drive transistors N 1  and N 2  are designed to be stronger than their corresponding load transistors P 1  and P 2 , respectively. Further, the cell comprises an additional two n-type stabilizer transistors N 5  and N 6 . Stabilizer transistor N 5  is coupled between the gate of load transistor P 1  and the gate of drive transistor N 1 . Stabilizer transistor N 6  is coupled between the gate of load transistor P 2  and the gate of drive transistor N 2 . The gates of the stabilizer transistors N 5  and N 6  are connected to the word line WL. For ease of description, the node at the gate of stabilizer transistor N 5  will be referred to as storage node C and the node at the gate of stabilizer transistor N 6  will be referred to as storage node D. Storage nodes C and D are provide redundant storage. 
         [0020]    The SER SRAM cell  400  is able to hold two states when the access transistors N 3  and N 4  are turned off. The states are associated with a binary one and a binary zero. Accordingly, when the access transistors N 3  and N 4  are turned off storage nodes A and B store voltages for a corresponding binary number. 
         [0021]    From the description above as well as from  FIG. 4 , it will be appreciated that the stabilizer transistors N 5  and N 6  break the inherent positive feedback between the storages nodes A and B and provide additional storage nodes C and D. That is, the gates of the stabilizer transistors N 5  and N 6  are controlled by the word line WL so that the feedback mechanism only works when the word line WL goes high. Further, the stabilizer transistors N 5  and N 6  are designed to have a very low threshold voltage, and hence a higher leakage. This feature helps achieve almost full swing at the storage nodes C and D. Alternatively, the word line WL may be overdriven to achieve full swing signal at the storage nodes C and D. 
         [0022]    It will be appreciated that breaking the inherent feedback of the cross-coupled drive and load transistors N 1 , N 2 , P 1 , and P 2 , respectively, and providing additional storages nodes improves the robustness of an SRAM cell significantly. 
         [0023]    For example, consider the case when storage nodes A and D store a logic 1 while storage nodes B and C store a logic 0. If the voltage at storage node A becomes logic 0 due to a soft error, such as cosmic radiation, the load transistor P 2  turns on. However, drive transistor N 2  is also on because storage node D stores a logic 1. 
         [0024]    Since drive transistor N 2  is designed to be stronger than load transistor P 2 , storage node B will retain its original logic value of 0. This will, in turn, keep load transistor P 1  turned on. Since load transistor P 1  remains on, it will ensure the storage node A recovers its original logic value of 1. Similarly, a radiation incident on storage node B will not also result in a data upset. 
         [0025]    Referring to  FIG. 5 , a SER SRAM cell in accordance with an alternate embodiment is illustrated generally by numeral  500 . The SER SRAM cell  500  of the present embodiment is similar to the SER SRAM  400  as described with reference to  FIG. 4 . However, in the present embodiment, the SER SRAM cell  500  includes only one stabilizer transistor N 5 . 
         [0026]    Referring to  FIG. 6 , a SER SRAM cell in accordance with yet an alternate embodiment is illustrated generally by numeral  600 . The SER SRAM cell  600  of the present embodiment is similar to the SER SRAM  400  as described with reference to  FIG. 4 . However, in the present embodiment, the SER SRAM cell  600  includes supply transistors P 3  and P 4 . As shown, the supply transistor P 3  is coupled between the power supply V DD  and storage node C, and is gated by the voltage stored on storage node A. Similarly, the supply transistor P 4  is coupled between the power supply V DD  and storage node D, and is gated by the voltage stored on storage node B. 
         [0027]    Although the SER SRAM cell  600  operates in a similar manner to the SER SRAM cell  400  described with reference to  FIG. 4 , the two supply transistors P 3  and P 4  are added to provide more stable complementary voltages at storage nodes C and D, respectively. 
         [0028]    Referring to  FIG. 7 , a SER SRAM cell in accordance with yet an alternate embodiment is illustrated generally by numeral  700 . Load transistors P 1  and P 2  are coupled at the source to the power supply V DD. The drain of load transistor P 1  is coupled to storage node A. The drain of load transistor P 2  is coupled to storage node B. Load transistor P 2  is gated by storage node A and load transistor P 1  is gated by storage node B. 
         [0029]    The drain of drive transistor N 2  is coupled to storage node B. The drain of drive transistor N 1  is coupled to storage node A. Both drive transistors N 1  and N 2  are coupled at the source to ground. Drive transistor N 1  is driven by storage node C and drive transistor N 2  is driven by storage node D. 
         [0030]    Stabilizer transistor P 4  is coupled between the power supply and storage node D, and is driven by storage node B. Stabilizer transistor N 6  is coupled between storage node D and ground, and is driven by storage node C. 
         [0031]    Stabilizer transistor P 3  is coupled between the power supply and storage node C, and is driven by storage node A. Stabilizer transistor N 5  is coupled between storage node C and ground, and is driven by storage node D. 
         [0032]    Storage nodes A and B are coupled to bit-line pair BL and BLB by access transistors N 3  and N 4 , respectively. 
         [0033]    Similar to the previously described embodiments, the gates of the drive transistors N 1  and N 2  are driven by the storage nodes C and D. However, in the present embodiment, the complementary logic voltages at the internal nodes are held very strongly either at logic 1 or logic 0 by cross-coupled stabilizer transistors P 3 , P 4 , N 5  and N 6 . Accordingly, the load transistors P 1  and P 2  and the drive transistors N 1  and N 2  are effectively cross coupled via the cross-coupled stabilizer transistors P 3 , P 4 , N 5  and N 6 . 
         [0034]    Such an arrangement provides two strong redundant storage nodes C and D. Consequently, in the event of a particle strike at one of the nodes A, B, C or D, there are three unaffected nodes that can restore the logic state of the affected node. Thus, the SER SRAM cell greatly reduces the likelihood of a SRAM cell experiencing a soft error. 
         [0035]    Accordingly, it will be appreciated by a person of ordinary skill in the art that the present invention provides improved robustness for SRAM cells in the face of soft errors. Further, although the invention has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art without departing from the scope of the invention as defined by the appended claims.