Abstract:
A multiple output comparator compares a first input signal and a second input signal. An output mirror circuit receives the comparison and sets an output signal at a first output terminal of the multiple output comparator to a digital state indicating that the magnitude of the is greater than or lesser than the second signal. An offset generator creates an offset signal for adjusting a threshold signal level at the output mirror circuit such that the difference of the and the second signal is combined with the offset signal. The output mirror circuit transfers provides a digital state to another output terminal indicating that the is greater than or lesser than the second signal as adjusted by the adjustment signal.

Description:
TECHNICAL FIELD 
     This disclosure relates generally to a semiconductor integrated circuit. In particular, this disclosure relates to a multiple output offset comparator circuit suitable for the semiconductor integrated circuit. More particularly, this disclosure relates to a multiple output offset comparator circuit for use in a buck DC-to-DC converter. 
     BACKGROUND 
     In applications where a single voltage signal is to be compared with multiple thresholds, (i.e. an “n-bit” analog-to-digital converter), the input signal is applied to multiple operational amplifiers structured as comparator circuits. Each of the operational amplifiers has a separate threshold voltage applied to the input of the operational amplifiers. 
     Another application for using a signal voltage signal compared with two threshold values is in a buck DC-to-DC converter. The comparator compares the output voltage of the buck DC-to-DC converter with a reference voltage and determines if additional current needs to be applied to an inductor in the circuit as is known in the art. The switching frequency of the current to the inductor or from the inductor are generally fixed with the duty cycle of the switching frequency being adjusted or pulse width modulated to determine the amount of current flowing into the inductor and thus to the load circuit connected the output terminal of the DC-to-DC converter. 
     Generally, buck DC-to-DC converters operate in one of two different modes, a continuous mode and a discontinuous mode. When the buck DC-to-DC converter is operating at light load (a small load current), the current supplied from the supply voltage source is not supplied on each cycle and the current then supplied from the collapsing field of the inductor. Instead of being a pulse width modulated (PWM) conversion process in the continuous mode, the conversion in now based on a pulse frequency modulation (PFM) in the discontinuous mode. Often the discontinuous mode is used in portable electronics such as smart cellular telephone, tablet computers, digital readers, etc. as a “sleep mode”. The only current required by the system in these applications is monitoring current for system maintenance (i.e. system clocking and timers, cellular network monitoring, wireless network monitoring). 
     In the sleep mode, there are two different operating states. In the first state, the basic sleep state, a sleep comparator determines when the output voltage level of the buck DC-to-DC converter falls below a reference voltage level provided for the sleep comparator. When the output voltage level of the buck DC-to-DC converter has fallen below the reference voltage level, a PMOS transistor is activated to allow current to pass to an inductor of the buck DC-to-DC converter to increase the output voltage level appropriately. 
     In a second state of the sleep mode, a panic state, a panic comparator determines if the output voltage level of the buck DC-to-DC converter falls by a predetermine level below the reference voltage level (i.e. 10 mV). The panic comparator activates a panic signal and the panic comparator acts to change the drive scheme of the buck DC-to-DC converter to support a larger load current. 
     The sleep comparator is triggered regularly as part of the normal operation of the buck DC-to-DC converter. However, the buck DC-to-DC converter should only “panic” if the output voltage continues to fall. It is clearly important that these thresholds for the sleep comparator and the panic comparator are accurate, but it is more important that the gap between the thresholds is well controlled. 
     This situation occurs in many applications, where a lower threshold is used to trigger a corrective action, and a higher threshold is used as part of the normal operation. In these applications, the exact threshold of the comparators is less important than the difference between the two thresholds of the comparators. 
     SUMMARY 
     An object of this disclosure is to provide a comparator circuit that compares an input signal with multiple reference signal levels that are accurately offset from one another. 
     An object of this disclosure is to provide an integrated circuit that receives a feedback signal that is compared with multiple offset threshold signal levels to determine a level within a range of the offset threshold levels of the feedback signal. 
     To accomplish at least one of these objects, a multiple output comparator has a difference circuit that receives a first signal and a second signal to determine when a magnitude of the first signal is greater than or lesser than the second signal. The difference circuit provides an in-phase output signal and an out-of-phase output signal that are indicative that the magnitude of the first signal is greater than or lesser than the second signal. 
     The multiple output comparator has an output mirror circuit that receives the in-phase output signal and an out-of-phase output signal from the difference circuit to capture the indication that the magnitude of the first signal is greater than or lesser than the second signal and sets an output signal at a first output terminal of the multiple output comparator to a digital state indicating that the magnitude of the first signal is greater than or lesser than the second signal. The output mirror circuit includes an offset generator that creates an adjustment signal for adjusting a threshold signal level of the difference circuit such that the magnitude of the first signal is greater than or lesser than the second signal with an offset signal level added to or subtracted from a difference of the first signal and the second signal. The output mirror circuit transfers at least one output signal to at least one second output terminal of the multiple output comparator to a digital state indicating that the magnitude of the first signal is greater than or lesser than the second signal as adjusted by the adjustment signal. 
     The in-phase output signal from difference circuit is connected to a first mirror driver. The first mirror driver has a first mirror reference leg for developing an in-phase reference signal. The out-of-phase output signal from the difference signal is connected to a second mirror driver. The second mirror driver has a second mirror reference for developing an out-of-phase reference signal. The first mirror reference leg is connected to at least one in-phase mirror leg such that each in-phase mirror leg generates a mirrored in-phase signal. The second mirror reference leg is connected to at least one out-of-phase mirror leg such that each out-of-phase mirror leg generates a mirrored out-of-phase signal. 
     The first mirror driver and the second mirror driver is connected to a transfer mirror for transferring the mirrored in-phase signal to the second mirror driver for combining with the at least one mirrored out-of-phase signal for determining the digital state of the at least one out-of-phase mirror leg that is to be transferred to the at least one second output terminal of the multiple output comparator. 
     The transfer mirror has at least one transfer mirror reference leg connected to receive the at least one mirrored in-phase signal. The transfer mirror has at least one mirror transfer leg connected to an associated transfer mirror leg to transfer an at least one second mirrored in-phase signal to an associated out-of-phase mirror leg to be combined with the mirrored out-of-phase signal to determine the digital state at the at least one second output terminal of the multiple output comparator. The combination of the at least one second mirrored in-phase signal and the associated mirrored out-of-phase signal allows a dominant of the mirrored in-phase output signal and mirrored out-of-phase output signal to generate the digital state indicating that the magnitude of the first signal is greater than or lesser than the second signal. The digital state being applied the second output terminal of the comparator. The offset generator is selectively connected to the in-phase mirror legs and/or the out-of-phase mirror legs to modify the threshold of the comparison of the first input signal and the second input signal such that the magnitude of the first signal is greater than or lesser than the second signal additively combined with the offset signal. 
     In various embodiments of this disclosure the difference circuit has a pair of transistors of a first conductivity type connected as a differential amplifier. In embodiments where the transistors are metal oxide semiconductor (MOS) transistors, the sources are commonly connected together and to a first terminal of a current source. The second terminal of the current source is connected to reference supply voltage source. The first signal and the second signal are each connected to a gate of one of the pair of MOS transistors. The drains of the pair of MOS transistors of the first conductivity type are connected to form the output terminals of the difference circuit and are connected as the inputs to the output mirror circuit. The first mirror reference leg and second mirror reference leg are each formed of a diode connected MOS transistor of a second conductivity type with their gates and drains commonly connected through the output terminals of the difference circuit to the drains of the pair of transistors of the differential amplifier. The sources of the two diode connected MOS transistors are connected to a power supply voltage source. 
     The at least one in-phase mirror leg has a first MOS mirroring transistor for generating the mirrored in-phase output signal and the at least one out-of-phase mirror leg has a second MOS mirroring transistor for generating at least one mirrored out-of-phase output signal. 
     The transfer mirror reference leg within the at least one in-phase mirror leg has a diode connected MOS transistor of the first conductivity type having a gate and drain commonly connected with the source of the first MOS mirroring transistor and a source connected to the reference supply voltage source for transferring the mirrored in-phase output signal to the transfer mirror leg. The transfer mirror leg of the has a third MOS mirroring transistor having a gate connected to the gate and drain of the diode connected MOS transistor of the associated transfer mirror reference leg. A source of the third MOS mirroring transistor is connected to the reference supply voltage source. The drain of the third MOS mirroring transistor is connected with the source of the second MOS mirroring transistor for transferring the mirrored in-phase output signal to the associated out-of-phase mirror leg. The junction of the connection of the drain of the third MOS mirroring transistor and the second MOS mirroring transistor is a second output terminal of the comparator for transferring of the digital state to external circuitry. 
     In various embodiments, the offset generator is a current source that is selectively connected to the associated in-phase mirror legs and/or the out-of-phase mirror legs to modify the threshold of the comparison of the first input signal and the second input signal such that the magnitude of the first signal is greater than or lesser than the second signal additively combined with the offset signal. The injected current of the current source is proportional to the current through the pair of transistors of the differential amplifier to make the added offset very accurately controlled. 
     In some embodiments, the offset generator is connected in parallel with the out-of-phase mirroring leg. In other embodiments, the offset generator is connected in parallel with the transfer mirror leg. In still other embodiments, the offset generator is connected in parallel with the in-phase mirror leg. And in still other embodiment, the offset generator is connected in parallel with the transfer mirror reference leg. The current source of the offset generator may be programmable to adjust the threshold offset of the comparator a selected output. The current source is structured to be scalable to provide the adjustment of the threshold offset of the comparator at the selected second output terminal. 
     When the first signal is greater than the second signal, the at least one in-phase mirror legs of the mirror driver generates a larger output signal than the at least one out-of-phase mirror legs. Thus, the in-phase output signal of the difference circuit is larger than the out-of-phase output signal. The mirrored larger in-phase output signal is transferred to the at least one in-phase mirror legs and the mirrored smaller out-of-phase output signal is transferred to the at least one out-of-phase mirror legs. The larger in-phase output signal is transferred to the at least one out-of-phase mirror legs through the mirror transfer leg where it is combined with the smaller out-of-phase output signal and dominates the smaller out-of-phase output signal to cause the output of the comparator to assume the digital state representing that the first signal is greater than the second signal. 
     When the first signal is less than the second signal, the at least one in-phase mirror legs of the mirror driver generates a smaller output signal than the at least one out-of-phase mirror legs. Thus, the in-phase output signal of the difference circuit is less than the out-of-phase output circuit. The mirrored larger in-phase output signal is transferred to the at least one in-phase mirror legs and the mirrored smaller out-of-phase output signal is transferred to the at least one out-of-phase mirror legs. The smaller in-phase output signal is transferred to the at least one out-of-phase mirror legs through the mirror transfer leg where it is combined with the larger out-of-phase output signal where the larger out-of-phase output signal dominates to cause the output of the comparator to assume the digital state representing that the first signal is less than the second signal. 
     In various embodiments, the mirror driver includes a plurality of in-phase mirror legs and a plurality of out-of-phase mirror legs. Each of the in-phase mirror legs is coupled to one of the of the out-of-phase mirror legs. Each out-of-phase mirror leg providing an output terminal for the comparator providing multiple output signals. Each of the in-phase mirror legs and/or the out-of-phase mirror legs may selectively have one of the offset generator to adjust the threshold voltage of the comparator for the digital state present at the output of the out-of-phase mirror leg. 
     In various other embodiments, the mirror driver includes one in-phase mirror legs and a plurality of out-of-phase mirror legs. The in-phase mirror leg is coupled to each of the of the out-of-phase mirror legs. Each out-of-phase mirror leg providing an output terminal for the comparator providing multiple output signals. 
     In some embodiments, the mirror driver includes one in-phase mirror leg and one out-of-phase mirror leg. The in-phase mirror leg is coupled to one of the of the out-of-phase mirror leg. The out-of-phase mirror leg providing multiple output terminals for the comparator providing multiple output signals. Each output terminal is connected to a first terminal of a switch. A second terminal of the switch is connected to an input terminal of a buffer circuit. The output terminal of the buffer circuit is connected to one output of the comparator circuit. Each switch is activated successively to provide the digital state of the comparator to one of the output terminals. 
     The out-of-phase mirror leg has multiple offset generators to adjust the threshold voltage of the comparator for the digital state present at the output of the out-of-phase mirror leg. A first offset generator has a switch with a first terminal connected to the junction of the transfer mirror leg and the out-of-phase mirror leg. The remaining multiple offset generators have switches that are connected in series with the switch of the preceding offset generator. The second terminal of each switch of the multiple offset generators is connected to the current source of the offset generator. As each of the output terminals are selected, an additional current source of one of the offset generators is added to modify the threshold offset of the comparator to provide different threshold offsets for each of the output terminals of the comparator. 
     In various embodiments, at least one of the objects of this disclosure is accomplished by an integrated circuit such as a buck DC-to-DC converter that has multiple output comparator. The multiple output comparator is structured and functions as above. In the embodiments of the buck DC-to-DC converter, the comparator is structured to combine the functions of a sleep comparator and a panic comparator. The sleep comparator determines if a feedback signal indicating an output voltage level of the buck DC-to-DC converter is less than a reference signal. If feedback signal is less than the reference signal, the comparator sleep output is triggered. The panic comparator determines if the feedback signal is less than a panic threshold level of approximately 10 mV. When the feedback signal is greater than the panic threshold level of the reference signal, the panic output of the comparator is triggered. In various embodiments of this comparator for the buck DC-to-DC converter, the mirror driver of the comparator has an in-phase sleep mirror leg, an out-of-phase sleep mirror leg, an in-phase panic mirror leg, and an out-of-phase panic mirror leg. The offset generator current source is connected in parallel with the second out-of-phase MOS mirroring transistor to set the offset voltage level to be the panic threshold voltage level. In other embodiments, the mirror driver there is one in-phase mirror leg coupled to an out-of-phase sleep mirror leg and an out-of-phase panic mirror leg. In these embodiments, the offset generator current source is connected in parallel with the transfer mirror leg to set the offset voltage level to be the panic threshold voltage level. In still other embodiments, the mirror driver includes one in-phase mirror leg and one out-of-phase mirror leg. The in-phase mirror leg is coupled to one of the of the out-of-phase mirror leg. The out-of-phase mirror leg has a sleep output terminal and a panic output terminal. Each output terminal is connected to a first terminal of a switch. A second terminal of the switch is connected to an input terminal of a buffer circuit. The output terminal of the buffer circuit is connected to one output of the comparator circuit. Each switch is activated successively to provide the digital state of the comparator to one of the output terminals. 
     The out-of-phase mirror leg has an offset generator to adjust the threshold voltage of the comparator for the digital panic state present at the panic output terminal of the out-of-phase mirror leg. The offset generator has a switch with a first terminal connected to the junction of the transfer mirror leg and the out-of-phase mirror leg. The second terminal of the switch the offset generators is connected to a current source of the offset generator. As each of the first output terminal is selected, there is no offset for the threshold voltage of the comparator. When the second output terminal is selected, the current source of the offset generator is added to modify the threshold offset of the comparator to provide panic threshold offset level for the panic output terminal of the comparator. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of a multiple output offset comparator embodying the principles of this disclosure. 
         FIG. 2  is a schematic diagram of a first implementation of a multiple output offset comparator embodying the principles of this disclosure. 
         FIG. 3  is a schematic diagram of a second implementation of a multiple output offset comparator embodying the principles of this disclosure. 
         FIG. 4  is a schematic diagram of a third implementation of a multiple output offset comparator embodying the principles of this disclosure. 
         FIG. 5  is a schematic diagram of a buck DC-to-DC converter employing a multiple output offset comparator embodying the principles of this disclosure. 
         FIG. 6  is a schematic diagram of a first implementation of the multiple output offset comparator embodying the principles of this disclosure of the buck DC-to-DC converter of  FIG. 5 . 
         FIG. 7  is a schematic diagram of a second implementation of a multiple output offset comparator embodying the principles of this disclosure of the buck DC-to-DC converter of  FIG. 5 . 
         FIG. 8  is a schematic diagram of a third implementation of a multiple output offset comparator embodying the principles of this disclosure of the buck DC-to-DC converter of  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION 
     In applications of the prior art such as the buck DC-to-DC converters described above, the comparators are implemented as separate blocks within the system. Each comparator therefore has a spread of threshold dominated by the mismatching of the characteristics of the input pair of transistors connected as a differential amplifier. In order to control how much variation in threshold occurs the comparators must be very carefully designed. In applications where a comparator is used to determine the existence of a fault condition, the mismatch in the input pair of transistors of the differential amplifiers of related comparators is greater than the separation in their thresholds, a problem may not be determined in time to provide necessary corrective action to prevent the fault from having a deleterious effect on the system. 
     In some circumstances, one signal is being measured by multiple comparators to determine when a potential issue is developing and needs to have attention from the system or to determine when a fault has occurred and corrective action is to be taken. The separation between the two thresholds of the two discrete comparators has to be set greater than would be ideal, because the mismatch in the comparators is too large. The mismatch is a result of the differences in the transistors resulting from tolerances in the processing. These tolerances effect the currents through the transistors and thus the differences in threshold voltages between the comparators. The offset voltage is proportional to the differences in the offset current and inversely proportional to the transconductance of the input differential pair of transistors of the comparators. This negatively impacts the operation of a system such as the buck DC-to-DC converter by affecting such parameters as the transient load regulation. In situations such as this, the exact threshold of each comparator is less important than the difference between the two thresholds. 
       FIG. 1  is a functional block diagram of a multiple output offset comparator  5 . The multiple output offset comparator includes a difference circuit  10  that receives a first input signal IN 1  and a second input signal IN 2 . The difference circuit generates an out-of-phase signal  17  and in-phase signal  18  that has an amplitude that represents a difference in the magnitude of the first input signal IN 1  and a second input signal IN 2 . The out-of-phase signal  17  is applied to an out-of-phase current mirror  50   a . The out-of-phase current mirror  50  has out-of-phase reference leg  20   a  that generates an out-of-phase reference signal RS OP  based on the amplitude of the out-of-phase signal  17 . The in-phase signal  18  is applied to an in-phase current mirror  50   b . The in-phase current mirror  50   b  has in-phase reference leg  20   b  that generates an in-phase reference signal RS IP  based on the amplitude of the in-phase signal  18 . 
     The in-phase reference signal RS IP  is applied to at least one in-phase mirror legs  25   a  . . .  25   n  of the in-phase current mirror  50   b  and the out-of-phase reference signal RS OP  is applied to at least one out-of-phase mirror legs  30   a  . . .  30   n  of the out-of-phase current mirror  50   a . Each of the at least one in-phase mirror legs  25   a  . . .  25   n  generates an in-phase mirror signal MSIP 1 , . . . , MSIPn and each of the at least one out-of-phase mirror legs  30   a  . . .  30   n  generates an out-of-phase mirror signal MSOP 1 , . . . , MSOPn. The in-phase mirror signal MSIP 1 , . . . , MSIPn is transferred to transferred to the transfer current mirror  55 . The transfer current mirror  55  has at least one in-phase transfer mirror  35   a , . . . ,  35   n . The output of each at least one in-phase transfer mirror  35   a , . . . ,  35   n  is an at least one mirrored in-phase reference signal MRS IP1  , . . . , MRS IPn  that is applied to the output of the at least one out-of-phase mirror legs  30   a  . . .  30   n  of the out-of-phase current mirror  50   a  to be combined with the out-of-phase mirror signal MSOP 1 , . . . , MSOPn to form the multiple digital output signals OUT 1 , . . . , OUTn. The out-of-phase mirror legs  30   a  . . .  30   n  optionally have an offset circuit  40   a , . . . ,  40   n  that injects or extracts an offset signal  42   a , . . . ,  42   n  to each of the out-of-phase mirror legs  30   a  . . .  30   n . The offset signal  42   a , . . . ,  42   n  is injected or extracted from the out-of-phase mirror signal MSOP 1 , . . . , MSOPn to adjust the apparent threshold of the comparator. The modified out-of-phase mirror signal MSOP 1 , . . . , MSOPn as combined with the mirrored in-phase reference signal MRS IP1 , . . . , MRS IPn  forms a first digital output signal OUT 1 , . . . , OUTn of the multiple digital output signals OUT 1 , . . . , OUTn that indicates the digital state signifying whether the first input signal IN 1  is greater than or lesser than the second input signal IN 2  and forms a second digital output signal OUT 1 , . . . , OUTn of the multiple digital output signals OUT 1 , . . . , OUTn that indicates the Digital state signifying whether the first input signal (IN 1 ) is greather than or lesser than The second input signal (IN 2 ) as adjusted by the offset signal  42   a , . . . ,  42   n.    
     The difference circuit  10  is formed using a traditional input pair of transistors of a differential amplifier with biasing. The current mirror driver  15  is the primary output stage that is formed by folding the output of the input pair of transistors of the difference circuit  10  to a pair of current mirrors (the out-of-phase current mirror  50   a  and the in-phase current mirror  50   b ), which compares the current in each arm to determine which input is higher. 
     In various embodiments, the difference circuit  10  is formed of an operational transconductance amplifier that is implemented using NMOS transistors, PMOS transistors, or with NPN or PNP bipolar transistors. In some embodiments, the difference circuit  10  is formed by current steering (folded cascode) type of amplifier. Still other embodiments may include other forms of the difference circuit  10  and be in keeping with the intent of this disclosure. The important feature is that the offset voltage generated by the by the voltage mismatch of the input stage of the difference circuit  10  is compensated for in the second (or subsequent) stages of the current mirror driver  15  so that the main source of mis-match (the input stage) is shared between the different threshold outputs. The offset circuits  40   a , . . . ,  40   n  injects or extracts an offset signal  42   a , . . . ,  42   n  to each of the out-of-phase mirror legs  30   a  . . .  30   n  force the sharing of the offset signal among the different thresholds of the at least one digital output signals OUT 1 , . . . , OUTn. 
     A second current mirror (the out-of-phase current mirror  50   a ) is formed to create an identical replica of the main output stage (the in-phase current mirror  50   b ). A current is injected into the second current mirror to offset the threshold. 
     The input pair of transistors of the differential amplifier of the difference circuit  10  is typically the greatest source of mismatch in a comparator. As the input pair of transistors of the differential amplifier is shared between current mirrors (the out-of-phase current mirror  50   a  and the in-phase current mirror  50   b ) of the two output stages, the two thresholds track each other as long as the offset threshold level is greater than the much smaller, mismatch of the later stages, the thresholds will not cross. The threshold offset is therefore well controlled. The injected current is proportional to the current in the input pair of transistors of the differential amplifier to make the added offset very accurately controlled. 
       FIG. 2  is a schematic diagram of a first implementation of a multiple output offset comparator  5 . The multiple output offset comparator  5  has a difference circuit  10  that has two input terminals  4  and  6  to receive the two input signals IN 1  and IN 2 . The two input terminals  4  and  6  are connected to the gates of the input pair of transistors N 1  and N 2 . The sources of the input pair of transistors N 1  and N 2  are commonly connected and connected to a first terminal of a biasing current source  8 . The second terminal of the biasing current source  8  is connected to a ground reference voltage source. The drains of the input pair of transistors N 1  and N 2  provide the output terminals  17  and  18  of the difference circuit  10 . 
     The output terminals  17  and  18  are the input terminals of the current mirror driver  15 . The mirror driver  15  includes the out-of-phase current mirror  50   a , the in-phase current mirror  50   b , the transfer current mirror  55 , and the at least one offset circuit  40   n . The output terminal  17  is connected to the out-of-phase mirror reference leg  20   a  of the out-of-phase current mirror  50   a  and the output terminal  18  is connected to the in-phase mirror reference leg  20   b  of the in-phase current mirror  50   b . The out-of-phase reference leg  20   a  is formed of a first diode connected PMOS transistor P 1 . The gate and drain of the first diode connected PMOS transistor P 1  are connected to the drain of the first NMOS transistor N 2  of the input pair of transistors N 1  and N 2  of the difference circuit  10 . The in-phase reference leg  20   b  is formed of a second diode connected PMOS transistor P 2 . The gate and drain of the second diode connected PMOS transistor P 2  are connected to the drain of the second NMOS transistor N 2  of the input pair of transistors N 1  and N 2 . As is known in the art, the biasing current I BIAS  as generated by the biasing current source  8  is equal to the sum of the two mirror reference currents I OP  and I IP  and form the output signals of the difference circuit  10 . 
     The out-of-phase reference leg  20   a  is combined with at least one out-of-phase mirror leg  30   a , . . . ,  30   n  to form a out-of-phase current mirror  50   a . The in-phase reference leg  20   b  is combined with at least one in-phase mirror leg  25   a , . . . ,  25   n  to form a in-phase current mirror  50   b . The gate and drain of the first diode connected PMOS transistor P 1  of the out-of-phase reference leg  20   a  is connected to the gates of the PMOS mirror transistors P 4   a , . . . , P 4   n . The gate and drain of the second diode connected PMOS transistor P 2  of the in-phase reference leg  20   b  is connected to the gates of the PMOS mirror transistors P 3   a , . . . , P 3   n . The sources of the PMOS mirror transistors P 3   a , . . . , P 3   n  and the PMOS mirror transistors P 4   a , . . . , P 4   n  are connected to the power supply voltage source. The drain of the PMOS mirror transistor P 3   a , . . . , P 3   n  of each of the in-phase mirror legs  30   a , . . . ,  30   n  provide the in-phase mirrored current I IPMa , . . . , I IPMn . The drain of the PMOS mirror transistor P 4   a , P 4   n  of each of the out-of-phase mirror legs  30   a , . . . ,  30   n  provide the out-of-phase mirrored current I OPMa , . . . , I OPMn . 
     The transfer current mirror  55  of the current mirror driver  15  has at least one current transfer mirror  35   a , . . . ,  35   n  One current transfer mirror  35   a , . . . ,  35   n  is coupled to each in-phase mirror leg  25   a , . . . ,  25   n  and each associated out-of-phase mirror leg  30   a , . . . ,  30   n . Each current transfer mirror  35   a , . . . ,  35   n  has a diode connected NMOS reference transistor N 3   a , . . . , N 3   n . The gate and drain of the diode connected NMOS transistor N 3   a , . . . , N 3   n  is connected to the drain of the PMOS mirror transistor P 3   a , . . . , P 3   n  to form a transfer reference current leg of the current transfer mirror  35   a , . . . ,  35   n . The gate and drain of the diode connected NMOS reference transistor N 3   a , . . . , N 3   n  is connected to a gate of a NMOS mirror transistor N 4   a , . . . , N 4   n . The drain of the NMOS mirror transistor N 4   a , . . . , N 4   n  is connected to the drain of the PMOS mirror transistor P 4   a , . . . , P 4   n  of each of the out-of-phase mirror leg  30   a , . . . ,  30   n  to transfer a second mirrored in-phase reference current I IPM2a , . . . , I IPM2n  to be combined with the mirrored out-of-phase current I OPM2  to determine the digital output state at the output terminal OUT 1 , . . . , OUTn. The sources of the diode connected NMOS reference transistor N 3   a , . . . , N 3   n  and the NMOS mirror transistor N 4   a , . . . , N 4   n  are connected to the ground reference voltage source. 
     In  FIG. 1  the out-of-phase mirror leg  30   a  is shown having an offset circuit offset circuit  40   a , but in  FIG. 2 , the out-of-phase mirror leg  30   a  is shown having no offset circuit. Eliminating the offset circuit  40   a  indicates that the out-of-phase mirror leg  30   a  has no offset and is a comparator indicating whether the input signal IN 1  is greater than or lesser than the input signal IN 2 . The offset generated by the offset circuit  40   n  allows the comparator circuit to have a threshold value that is accurately offset from the equality value of the out-of-phase mirror leg  30   a  having no offset. 
       FIG. 3  is a schematic diagram of a second implementation of a multiple output offset comparator  5 . The multiple output offset comparator  5  has a difference circuit  10  that is structured and functions as described above in  FIG. 2 . The out-of-phase current mirror  50   a  current mirror driver  15  has an out-of-phase reference leg  20   a  and the in-phase current mirror  50   b  current mirror driver  15  an in-phase reference leg  20   b  that is also, structured and functions as described in  FIG. 2 . The out-of-phase reference leg  20   a  is combined with at least one out-of-phase mirror leg  30   a , . . . ,  30   n  to form a out-of-phase current mirror  50   a . The gate and drain of the first diode connected PMOS transistor P 1  of the out-of-phase reference leg  20   a  is connected to the gates of the PMOS mirror transistors P 4   a , . . . , P 4   n . The sources of the PMOS mirror transistors P 4   a , . . . , P 4   n  are connected to the power supply voltage source. The drain of the PMOS mirror transistor P 4   a , . . . , P 4   n  of each of the out-of-phase mirror legs  30   a , . . . ,  30   n  provide the out-of-phase mirrored currents I OPMa , . . . , I OPMn . 
     The in-phase reference leg  20   b  is combined with the in-phase mirror leg  25  to form a in-phase current mirror  50   b . The gate and drain of the second diode connected PMOS transistor P 2  of the in-phase reference leg  20   b  is connected to the gate of the PMOS mirror transistor P 3 . The source of the PMOS mirror transistor P 3  is connected to the power supply voltage source. The drain of the PMOS mirror transistor P 3  provides the in-phase mirror current I IPM . 
     The current mirror driver  15  has a current transfer mirror  35 . The current transfer mirror  35  is coupled to the in-phase mirror leg  25  and each out-of-phase mirror leg  30   a , . . . ,  30   n . The current transfer mirror  35  has a diode connected NMOS reference transistor N 3 . The gate and drain of the diode connected NMOS transistor N 3  is connected to the drain of the PMOS mirror transistor P 3  to form a transfer reference current leg of the current transfer mirror  35 . The gate and drain of the diode connected NMOS reference transistor N 3  is connected to a gate of a NMOS mirror transistors N 4   a , . . . , N 4   n . The drain of each of the NMOS mirror transistors N 4   a , . . . , N 4   n  is connected to the drain of one of the PMOS mirror transistors P 4   a , . . . , P 4   n  of each of the out-of-phase mirror legs  30   a , . . . ,  30   n  to transfer a second mirrored in-phase reference current I IPM2a , . . . , I IPM2n  to each out-of-phase mirror leg  30   a , . . . ,  30   n  to be combined with the out-of-phase mirrored currents I OPMa , . . . , I OPMn  to determine the digital output state at the output terminal OUT 1 , . . . , OUTn. The sources of the diode connected NMOS reference transistors N 3   a , . . . , N 3   n  and the NMOS mirror transistor N 4   a , . . . , N 4   n  are connected to the ground reference voltage source. 
     As in  FIG. 2 , the out-of-phase mirror leg  30   a  of  FIG. 3  is shown having no offset circuit. Eliminating the offset circuit  40   a  indicates that the out-of-phase mirror leg  30   a  has no offset and is a comparator indicating whether the input signal IN 1  is greater than or lesser than the input signal IN 2 . The offset generated by the offset circuit  40   n  allows the comparator circuit to have a threshold value that is accurately offset from the equality value of the out-of-phase mirror leg  30   a  having no offset. 
     The common connections of the drains of the NMOS mirror transistors N 4   a , . . . , N 4   n  and the drains of the PMOS mirror transistors P 4   a , . . . , P 4   n  are connected to the inputs of the buffer circuits B 1 , . . . , Bn. The buffer circuits B 1 , . . . , Bn receive the digital states for each of the comparator signals for the multiple offsets of the multiple output offset comparator  5  for conditioning and transferring as the digital output signal OUT 1 , . . . , OUTn to external circuitry. 
       FIG. 4  is a schematic diagram of a third implementation of a multiple output offset comparator  5 . The multiple output offset comparator  5  has a difference circuit  10  that is structured and functions as described above in  FIG. 2 . Similarly, the current mirror driver  15  has an out-of-phase current mirror  50   a  with an out-of-phase reference leg  20   a  and an in-phase current mirror  50   b  with an in-phase reference leg  20   b  that is also, structured and functions as described in  FIG. 2 . The out-of-phase reference leg  20   a  is combined with an out-of-phase mirror leg  30  to form a out-of-phase current mirror  50   a . The gate and drain of the first diode connected PMOS transistor P 1  of the out-of-phase reference leg  20   a  are connected to the gate of the PMOS mirror transistor P 4 . The source of the PMOS mirror transistor P 4  is connected to the power supply voltage source. The drain of the PMOS mirror transistor P 4  of each of the out-of-phase mirror legs  30  provide the out-of-phase mirrored current I OPM , I OPM . 
     The in-phase reference leg  20   b  is combined with the in-phase mirror leg  25  to form a in-phase current mirror  50   b . The gate and drain of the second diode connected PMOS transistor P 2  of the in-phase reference leg  20   b  are connected to the gate of the PMOS mirror transistor P 3 . The source of the PMOS mirror transistor P 3  is connected to the power supply voltage source. The drain of the PMOS mirror transistor P 3  provides the in-phase mirror current I IPM . 
     The current mirror driver  15  has a current transfer mirror  35 . The current transfer mirror  35  is coupled to the in-phase mirror leg  25  and the out-of-phase mirror leg  30 . The current transfer mirror  35  has a diode connected NMOS reference transistor N 3 . The gate and drain of the diode connected NMOS transistor N 3  is connected to the drain of the PMOS mirror transistor P 3  to form a transfer reference current leg of the current transfer mirror  35 . The gate and drain of the diode connected NMOS reference transistor N 3  is connected to a gate of a NMOS mirror transistor N 4 . The drain of the NMOS mirror transistors N 4  is connected to the drain of the PMOS mirror transistor P 4  of the out-of-phase mirror leg  30  to transfer a second mirrored in-phase reference current I IPM2  to the out-of-phase mirror leg  30  to be combined with the out-of-phase mirrored currents I OPM  to determine the digital output state at the output terminals OUT 1 , . . . , OUTn. The sources of the diode connected NMOS reference transistor N 3  and the NMOS mirror transistor N 4  are connected to the ground reference voltage source. 
     In the third implementation of a multiple output offset comparator  5  of  FIG. 4 , the digital states of the comparator  5  are time multiplexed to be determined at various times during operation. The common connection between drain of the PMOS transistor P 4  of the out-of-phase mirror leg  30  and the drain of the NMOS transistor N 4  of the current transfer mirror  35  is connected to a first terminal of each of the output multiplexing switches S 0 , S 1 , . . . , Sn. The second terminals of the terminal of each of the output multiplexing switches S 0 , S 1 , . . . , Sn are each connected to the input of one of the buffer circuits B 1 , . . . , Bn. The buffer circuits B 1 , . . . , Bn receive the digital states for each of the comparator signals for the multiple offsets of the multiple output offset comparator  5  for conditioning and transferring as the digital output signal OUT 1 , . . . , OUTn to external circuitry. 
     The threshold offset value is generated by the offset circuits  45   a , . . . ,  45   n  that allows the comparator circuit to have multiple threshold values that are accurately offset from the equality value of the out-of-phase mirror leg  30  having no offset (switch SW 0  being activated with no offset circuit). The in-phase mirror current I IPM2P  is combined with the out-of-phase mirror current I OPM . To create the offset threshold voltage required to determine the digital logic states for the plurality of offset threshold voltages, multiple offset circuits  45   a , . . . ,  45   n  are connected to be in parallel with the mirror NMOS transistor N 4  to generate the selected offset current I 1   a , . . . , I 1   n  that is extracted in this instance (and may be injected in other embodiments) to be combined with the in-phase mirror current I IPM2  and the out-of-phase mirror current I OPM  to determine the digital state of the output signals OUT 0 , . . . , OUTn. Each of the offset circuits  40   a , . . . ,  40   n  has a current source that generates the desired offset current I 1   a , . . . , I 1   n . Further, each of the offset circuits  40   a , . . . ,  40   n  has a switch SWI 1 , . . . , SWIn. In this implementations, the switches SWI 1 , . . . , SWIn are connected in series with the switch SWI 1  having its first terminal connected to the junction between the drain of the PMOS transistor P 4  and the NMOS transistor N 4  and the remaining switches . . . , SWIn having their first terminals connected to the second terminal of the previous switch SWI 1 , . . . , SWIn. The second terminals of each switch SWI 1 , . . . , SWIn is connected to the current source that generates the desired offset current I 1   a , . . . , I 1   n . In this implementations the current sources are selectively placed in parallel such that the desired offset current I 1   a , . . . , I 1   n  are additively combined. In other implementations the switches SWI 1 , . . . , SWIn may be in parallel and each of the current sources that generates the desired offset current I 1   a , . . . , I 1   n  generate a singular current for the offset current. 
     An external control circuit (not shown) provides a select signal to an activation terminal of the switches SW 0 , . . . , SWn and the switches SWI 1 , . . . , SWIn for providing the necessary timing for interleaving for providing the digital output states indicating the state of the comparator for each of the offset threshold values. 
       FIG. 5  is a schematic diagram of a buck DC-to-DC converter employing a multiple output offset comparator embodying the principles of this disclosure. The power switching section  110  of the power stage  105  has a control circuit  125  that generates control signals that are applied to a positive input of a driver circuit  130   a  and a negative input of a driver circuit  130   b . The output of the driver circuit  130   a  is applied to the gate of the PMOS transistor MP 1  and the output of the driver circuit  130   b  is applied to the gate of the NMOS transistor MN 1 . The source of the PMOS transistor MP 1  is connected to the power supply voltage source VDD and the source of the NMOS transistor MN 1  is connected to the substrate supply voltage source VSS. The substrate supply voltage source VSS is often the ground reference voltage source, but in some applications is a negative voltage level. The commonly connected drains of the PMOS transistor MP 1  and the NMOS transistor MN 1  are connected to an input terminal of the filter section  115 . The input terminal is a first terminal of an inductor L 1 . The control circuit determines that during the continuous mode or pulse width modulation mode the control signals are applied to the driver circuit  130   a  and the driver circuit  130   b  such that the PMOS transistor MP 1  is turned on and the NMOS transistor MN 1  is turned off, a current from the power supply voltage source VDD from the first terminal of the inductor L 1  out the second terminal of the inductor L 1  into the first terminal of the output capacitor C OUT  and to the substrate supply voltage source VSS. The output voltage V OUT  is present at the junction of the second terminal of the inductor L 1  and the output capacitor C OUT . 
     It is known in the art, that the voltage (V L1 ) across the inductor L 1  is determined by the formula: 
     
       
         
           
             
               V 
               
                 L 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 1 
               
             
             = 
             
               L 
               ⁢ 
               
                 
                   ⅆ 
                   
                     I 
                     L 
                   
                 
                 
                   ⅆ 
                   t 
                 
               
             
           
         
       
     
     The output voltage V OUT  is equal to the difference of the power supply voltage source VDD and the voltage V L1  across the inductor L 1  in the on state and equal to the negative of the voltage −V L1  across the inductor L 1  in the off state. The duty cycle of the buck DC-to-DC converter determines the on state time and the off state time. It can be shown that the output voltage V OUT  is equal to the duty cycle of the buck DC-to-DC converter multiplied by the voltage level of the power supply voltage source VDD. 
     The feedback section  140  has three inputs. The first input  107  is the feedback voltage V FB , that is developed from the output voltage V OUT  at common connection of the second terminal of the inductor L 1  and the first terminal of the output capacitor C OUT . The second and third inputs are the first and second reference voltages V REF1  and V REF2  generated by the switch control circuit  120 . The switch control circuit has a digital-to-analog converter  135  that receives a reference control word  122  and an offset control word  124 . The digital-to-analog converter  140  converts the reference control word  136  to the first reference voltage V REF1  and the offset control word  124  to the second reference voltage V REF2 . The first reference voltage V REF1  and the second reference voltage V REF2  are the second and third inputs to the feedback section  140 . The feedback control stage  140  has a multiple output offset comparator  145  for providing a sleep control signal  147  and a panic control signal  149 . The sleep control signal  147  indicates that the buck DC-to-DC converter is operating in the discontinuous mode or pulse frequency modulation mode (PFM). When sleep control signal  147  is active, the control circuit  125  activates the driver circuit  130   a  to turn on the PMOS transistor MP 1  to allow current to be passed from the power supply voltage source VDD through the PMOS transistor MP 1  to the inductor L 1 . When the sleep control signal  147  is inactive the output current I OUT  to a load circuit is transferred from the inductor L 1  and the output capacitor C OUT . The panic control signal  149  indicates that the output voltage level of the buck DC-to-DC converter has fallen by the predetermine level below the reference voltage level (i.e. 10 mV). The control circuit  125  activates the driver circuit  130   a  and the driver circuit  130   b  to drive the PMOS transistor MP 1  and the NMOS transistor MN 1  to support a larger load current I OUT . 
     The structure of the comparator circuit  145  is variously as described in  FIGS. 6-8  dependent upon the desired implementation. The first reference voltage V REF1  is applied to one of the inputs  4  or  6  of the input differential pair of transistors N 1  and N 2  of the difference circuit  10 . The second reference voltage V REF2  is applied to the panic offset circuit  30  for generating the offset current I 1 P that is injected or extracted from the out-of-phase mirror leg  25  as described generally above. 
       FIG. 6  is a schematic diagram of the first implementation of the multiple output offset comparator  145  as implemented in the buck DC-to-DC converter of  FIG. 5 . The structure and function of the difference circuit  10  is identical to that of the difference circuit of  FIG. 2 . The first reference voltage V REF1  is applied to the first input terminal  4  and thus connected to the gate of the NMOS transistor N 1  of the input differential pair of transistors N 1  and N 2 . The feedback voltage V FB  is applied to the second input terminal  6  and thus connected to the gate of the NMOS transistor N 2  of the input differential pair of transistors N 1  and N 2 . The drains of the input differential pair of transistors N 1  and N 2  are connected respectively to the out-of-phase reference leg  20   a  and the in-phase reference  20   b  of the current mirror driver  150 . As in  FIG. 2 , the out-of-phase reference leg  20   a  and the in-phase reference  20   b  of the current mirror driver  150  are formed respectively of the diode connected PMOS transistor P 1  and P 2 . The gain of the input differential pair of transistors N 1  and N 2  is sufficiently large that the out-of-phase reference current I OP  or the in-phase reference current I IP  is approximately equal to the biasing current I Bias . The commonly connected gate and drain of the PMOS transistor P 1  of the out-of-phase reference leg  20   a  is connected to the gate of the PMOS transistor P 4 S of the sleep out-of-phase mirror leg  30   s  and connected to the gate of the PMOS transistor P 4 P of the panic out-of-phase mirror leg  30   p . The commonly connected gate and drain of the PMOS transistor P 2  of the in-phase reference leg  20   b  is connected to the gate of the PMOS transistor P 3 S of the sleep in-phase mirror leg  25   s  and connected to the gate of the PMOS transistor P 3 P of the panic in-phase mirror leg  25   p.    
     The sleep in-phase mirror leg  25   s  and the sleep out-of-phase mirror leg  30   s  are connected to the sleep current transfer mirror  35   s . Similarly, the panic in-phase mirror leg  25   p  and the panic out-of-phase mirror leg  30   s  are connected to the panic current transfer mirror  35   p . As described in  FIG. 2 , the sleep in-phase mirror current I IPMS  is the reference current for the sleep current transfer mirror  35   s  as applied to the diode connected NMOS transistor N 3 S. The gate and drain of the diode connected NMOS transistor N 3 S is connected to the gate of the mirror NMOS transistor N 4 S such that the second sleep in-phase mirror current I IPM2S  is generated. The second sleep in-phase mirror current I IPM2S  is combined with the sleep out-of-phase mirror current I OPMS  to determine the digital state of the sleep signal OUTS at the output terminal  147 . 
     Again as described in  FIG. 2 , the panic in-phase mirror current I IPMP  is the reference current for the panic current transfer mirror  35   p  as applied to the diode connected NMOS transistor N 3 P. The gate and drain of the diode connected NMOS transistor N 3 P is connected to the gate of the mirror NMOS transistor N 4 P such that the second panic in-phase mirror current I IPM2P  is generated. The second panic in-phase mirror current I IPM2P  is combined with the panic out-of-phase mirror current I OPMP . To create the offset threshold voltage required to determine the panic condition, the offset circuit  40   p  generates the panic offset current I 1 P that is injected in this instance (and may be extracted in other embodiments) to be combined with the second panic in-phase mirror current I IPM2P  and the panic out-of-phase mirror current I OPMP  to determine the digital state of the panic signal OUTP at the output terminal  149 . The second voltage reference V REF2  is applied to the current source that generates the panic offset current I 1 P for providing the ability to program the current source to adjust the offset threshold value as required to insure correct operation of the buck DC-to-DC converter of  FIG. 5 . 
     The input differential pair of transistors N 1  and N 2  is typically the greatest source of mismatch threshold offset in a comparator. As the input differential pair of transistors N 1  and N 2  is shared between both output stages formed by the out-of-phase mirror legs  30   s  and  30   p , the sleep threshold and the panic threshold will track each other. Further, so long as the offset threshold is greater than the much smaller mismatch caused by the differences in the transistors of the current mirror driver, the offset thresholds will not cross and the offset threshold is therefore well controlled. The injected current is designed to be proportional to the input differential pair of transistors N 1  and N 2 , it is possible to make the added offset very accurately controlled. 
       FIG. 7  is a schematic diagram of the second implementation of the multiple output offset comparator  145  as implemented in the buck DC-to-DC converter of  FIG. 5 . The structure and function of the difference circuit  10  is identical to that of the difference circuit of  FIG. 2  and is connected to the first reference voltage V REF1  and the feedback voltage V FB . The drains of the input differential pair of transistors N 1  and N 2  are connected respectively to the out-of-phase reference leg  20   a  and the in-phase reference  20   b  of the current mirror driver  150 . As in  FIG. 6 , the out-of-phase reference leg  20   a  and the in-phase reference  20   b  of the current mirror driver  150  are formed respectively of the diode connected PMOS transistor P 1  and P 2 . The gain of the input differential pair of transistors N 1  and N 2  is sufficiently large that the out-of-phase reference current I OP  or the in-phase reference current I IP  is approximately equal to the biasing current I Bias . The commonly connected gate and drain of the PMOS transistor P 1  of the out-of-phase reference leg  20   a  is connected to the gate of the PMOS transistor P 4 S of the sleep out-of-phase mirror leg  30   s  and connected to the gate of the PMOS transistor P 4 P of the panic out-of-phase mirror leg  30   p . The commonly connected gate and drain of the PMOS transistor P 2  of the in-phase reference leg  20   b  is connected to the gate of the PMOS transistor P 3  of the in-phase mirror leg  25 . There is now a single in-phase mirror leg as shown in  FIG. 3 . 
     The in-phase mirror leg  25  and the sleep out-of-phase mirror leg  30   s  and the panic out-of-phase mirror leg  30   s  are connected to the current transfer mirror  35 . As described in  FIG. 3 , the in-phase mirror current I IPM  is the reference current for the current transfer mirror  35  as applied to the diode connected NMOS transistor N 3 . The gate and drain of the diode connected NMOS transistor N 3  is connected to the gate of the mirror NMOS transistor N 4 S such that the second sleep in-phase mirror current I IPM2S  is generated. The second sleep in-phase mirror current I IPM2S  is combined with the sleep out-of-phase mirror current I OPMS  to determine the digital state of the sleep signal OUTS at the output terminal  147 . Again as described in  FIG. 3 , the gate and drain of the diode connected NMOS transistor N 3  is connected to the gate of the mirror NMOS transistor N 4 P such that the second panic in-phase mirror current I IPM2P  is generated. The second panic in-phase mirror current I IPM2P  is combined with the panic out-of-phase mirror current I OPMP . To create the offset threshold voltage required to determine the panic condition, the offset circuit  40   p  is connected to be in parallel with the mirror NMOS transistor N 4 P and generates the panic offset current I 1 P that is extracted in this instance (and may be injected in other embodiments) to be combined with the second panic in-phase mirror current I IPM2P  and the panic out-of-phase mirror current I OPMP  to determine the digital state of the panic signal OUTP at the output terminal  149 . The second voltage reference V REF2  is applied to the current source that generates the panic offset current I 1 P for providing the ability to program the current source to adjust the offset threshold value as required to insure correct operation of the buck DC-to-DC converter of  FIG. 5 . 
     The common connection between drain of the PMOS transistor P 4 S of the sleep out-of-phase mirror leg  30   s  and the drain of the NMOS transistor N 4 S of the current transfer mirror  35  is connected to the input of the buffer circuit B 0 . The common connection between drain of the PMOS transistor P 4 P of the panic out-of-phase mirror leg  30   p  and the drain of the NMOS transistor N 4 P of the current transfer mirror  35  is connected to the input of the buffer circuit B 2 . The buffer circuits B 0  and B 2  receive the digital states for the sleep and panic comparator signals for the equal threshold value and the offset threshold value of the multiple output offset comparator  5  for conditioning and transferring as the digital output signal OUTS and OUTP to external circuitry through the terminals  147  and  149 . 
     As described above, the input differential pair of transistors N 1  and N 2  is typically the greatest source of mismatch threshold offset in a comparator. As the input differential pair of transistors N 1  and N 2  is shared between both output stages formed by the out-of-phase mirror legs  30   s  and  30   p , the sleep threshold and the panic threshold will track each other. In this implementation, the common reference legs  20   a  and  20   b  and the common in-phase mirror leg  25  further, reduce the device mismatches in the offset current to insure that the offset thresholds will not cross and the offset threshold is therefore well controlled. 
       FIG. 8  is a schematic diagram of a third implementation of a multiple output offset comparator  145  as implemented in the buck DC-to-DC converter of  FIG. 5 . In the third implementation, the digital states of the comparator  5  are time multiplexed to be determined at various times during operation. The structure and function of the difference circuit  10  is identical to that of the difference circuit of  FIG. 2  and is connected to the first reference voltage V REF1  and the feedback voltage V FB . The drains of the input differential pair of transistors N 1  and N 2  are connected respectively to the out-of-phase reference leg  20   a  and the in-phase reference  20   b  of the current mirror driver  150 . As in  FIGS. 6 and 7 , the out-of-phase reference leg  20   a  and the in-phase reference  20   b  of the current mirror driver  150  are formed respectively of the diode connected PMOS transistor P 1  and P 2 . The gain of the input differential pair of transistors N 1  and N 2  is sufficiently large that the out-of-phase reference current I OP  or the in-phase reference current I IP  is approximately equal to the biasing current I Bias . The commonly connected gate and drain of the PMOS transistor P 1  of the out-of-phase reference leg  20   a  is connected to the gate of the PMOS transistor P 4  of the out-of-phase mirror leg  30 . The commonly connected gate and drain of the PMOS transistor P 2  of the in-phase reference leg  20   b  is connected to the gate of the PMOS transistor P 3  of the in-phase mirror leg  25 . There being a single in-phase mirror leg  25  and a single out-of-phase mirror leg  30  as shown in  FIG. 4 . 
     The in-phase mirror leg  25  and the out-of-phase mirror leg  30  are connected to the current transfer mirror  35 . As described in  FIG. 4 , the in-phase mirror current I IPM  is the reference current for the current transfer mirror  35  as applied to the diode connected NMOS transistor N 3 . The gate and drain of the diode connected NMOS transistor N 3  is connected to the gate of the mirror NMOS transistor N 4  such that the second in-phase mirror current I IPM2  is generated. The second in-phase mirror current I IPM2  is combined with the out-of-phase mirror current I OPM  to determine the digital state of the sleep signal OUTS at the output terminal  147 . Again as described in  FIG. 4 , the gate and drain of the diode connected NMOS transistor N 3  is connected to the gate of the mirror NMOS transistor N 4  such that the second in-phase mirror current I IPM2  is generated. 
     The common connection between drain of the PMOS transistor P 4  of the out-of-phase mirror leg  30  and the drain of the NMOS transistor N 4  of the current transfer mirror  35  is connected a first terminal of each of the output multiplexing sleep and panic switches SWS and SWP. The output multiplexing sleep and panic switches SWS and SWP are each connected to the input of one of the buffer circuits B 0  and B 1 . The buffer circuits B 0  and B 1  receive the digital states for the sleep and panic comparator signals for the equal threshold value and the offset threshold value of the multiple output offset comparator  5  for conditioning and transferring as the digital output signal OUTS and OUTP to external circuitry through the terminals  147  and  149 . 
     The panic threshold offset value is generated by the offset circuit  45 , . . . ,  45   n  that allows the comparator circuit  145  to have multiple threshold values that are accurately offset from the equality value of the out-of-phase mirror leg  30  having no offset (switch SWS being activated with no offset circuit). The in-phase mirror current I IPM2  is combined with the out-of-phase mirror current I OPM . To create the offset threshold voltage required to determine the digital logic states for the panic offset threshold voltage, panic offset circuit  45  is connected to be in parallel with the mirror NMOS transistor N 4  to generate the panic offset current I 1 P that is extracted in this instance (and may be injected in other embodiments) to be combined with the in-phase mirror current I IPM2  and the out-of-phase mirror current I OPM  to determine the digital state of the panic output signal OUTP. The panic offset circuit  45  has a current source that generates the panic offset current I 1 P. Further, the panic offset circuit  45  has a switch SWIP. The second terminal of each switch SWIP is connected to the current source that generates the panic offset current I 1 P. 
     The second voltage reference V REF2  is applied to the current source that generates the panic offset current I 1 P for providing the ability to program the current source to adjust the offset threshold value as required to insure correct operation of the buck DC-to-DC converter of  FIG. 5 . 
     An external control circuit (not shown) provides a select signal SELS and SELP to an activation terminal of the switches SWS and SWP and the switch SWIP, . . . , SWIn for providing the necessary timing for interleaving to provide the digital output states indicating the sleep state and the panic state of the comparator for each of the threshold values. As described above, the input differential pair of transistors N 1  and N 2  is typically the greatest source of mismatch threshold offset in a comparator. As the input differential pair of transistors N 1  and N 2  is shared between both output stages formed by the out-of-phase mirror leg  30 , the sleep threshold and the panic threshold will track each other. In this implementation, the common reference legs  20   a  and  20   b , the common in-phase mirror leg  25  and the out-of-phase mirror leg  30  further, reduce the device mismatches in the offset current to insure that the offset thresholds will not cross and the offset threshold is therefore well controlled. 
     While this disclosure has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the disclosure. For instance, it is known in the art that bipolar junction transistors may be exchanged for the MOS transistors and still is in keeping with the intent of the principles of this disclosure. Further, the NMOS transistors may be replaced with PMOS transistors and the PMOS transistors replaced with NMOS transistors and still is in keeping with the intent of the principles of this disclosure.