Abstract:
An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Description:
[0001]     This application is a continuation of application Ser. No. 10/955,383, entitled Power Management Integrated Circuit, and claims priority therefrom. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to computer systems; more particularly, the present invention relates to delivering power to a central processing unit (CPU).  
       BACKGROUND  
       [0003]     The magnitude of power generated at CPUs is becoming an increasing concern as processing speeds increase. Thus, current power management schemes take advantage of reduced CPU activity to manage the magnitude of power consumed. However, power management circuitry is typically located at a remote location, such as on the CPU motherboard. Managing CPU power from the motherboard typically does not provide for a sufficiently fast response.  
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0004]     The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:  
         [0005]      FIG. 1  is a block diagram of one embodiment of a computer system;  
         [0006]      FIG. 2  illustrates one embodiment of a CPU die;  
         [0007]      FIG. 3  illustrates one embodiment of a power management die; and  
         [0008]      FIG. 4  illustrates one embodiment of a CPU.  
     
    
     DETAILED DESCRIPTION  
       [0009]     According to one embodiment, a power management system for a CPU is described. In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.  
         [0010]     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.  
         [0011]      FIG. 1  is a block diagram of one embodiment of a computer system  100 . Computer system  100  includes a central processing unit (CPU)  102  coupled to bus  105 . In one embodiment, CPU  102  is a processor in the Pentium® family of processors including the Pentium® II processor family, Pentium® III processors, and Pentium® IV processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used.  
         [0012]     A chipset  107  is also coupled to bus  105 . Chipset  107  includes a memory control hub (MCH)  110 . MCH  110  may include a memory controller  112  that is coupled to a main system memory  115 . Main system memory  115  stores data and sequences of instructions that are executed by CPU  102  or any other device included in system  100 . In one embodiment, main system memory  115  includes dynamic random access memory (DRAM); however, main system memory  115  may be implemented using other memory types. Additional devices may also be coupled to bus  105 , such as multiple CPUs and/or multiple system memories.  
         [0013]     Chipset  107  also includes an input/output control hub (ICH)  140  coupled to MCH  110  to via a hub interface. ICH  140  provides an interface to input/output (I/O) devices within computer system  100 . For instance, ICH  140  may be coupled to a Peripheral Component Interconnect bus adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oreg.  
         [0014]      FIG. 2  illustrates one embodiment of a CPU  102  die  200 . Die  200  includes four CPU processing cores (core  1 -core  4 )  210 . In addition, die  200  includes cache  220  and I/O circuitry  230 . In one embodiment, cache  220  is a L 2 /L 3  cache. I/O circuitry  230  is placed on the periphery (e.g., north, south, east, and west boundaries) to enable efficient vertical current delivery to cores  210   
         [0015]     As discussed above, circuitry situated on the motherboard does not provide a sufficient response for power management of a CPU die. In particular, the temperature and activity factor of CPUs change over time during operation due to varying workloads of applications. In addition, on-die Vcc values change due to noises induced by current transients.  
         [0016]     Typically CPU frequency is set based on worst-case Vcc and temperature. As the activity factor and temperature change, energy efficiency of the CPU degrades since the optimal Vcc/Vt ratio at constant frequency is a function of activity and temperature. Off-chip VRMs and body bias generators have very large response times and thus their usefulness for dynamic control is limited.  
         [0017]     According to one embodiment, a power management die is bonded to CPU die  200 .  FIG. 3  illustrates one embodiment of a power management die  300 . Die  300  includes VRM  310 , body bias generators  320 , temperature sensor  330 , voltage sensor  335  and control circuits  340 .  
         [0018]     In one embodiment, VRM die  310  provides a regulated voltage supply to components within CPU die  200 . For instance VRM  310  supplies Vcc voltages to Core  1 -Core  4 , cache  220  and I/O components  230 . Body bias generators  320  adjust the body bias voltages of transistors on die  200 . Particularly, a non-zero body to source bias is generated to modulate the threshold voltage of the die  200  transistors to control leakage and frequency.  
         [0019]     Temperature sensor  330  measures the temperature of die  200 , while voltage sensor  335  measures the operating voltage. Control circuits  340  controls the transistors on die  200 . In addition, control circuits  340  dynamically determine the optimum body voltage for the die  200  transistors. In a further embodiment, die  300  may include a clock sensor  360 , a current sensor  370  and a power sensor  380 .  
         [0020]     According to one embodiment, if the workload is known ahead of time, the Vcc, Vbs and frequency of die  200  can be set to the optimal value to maximize energy efficiency for the workload. Moreover, the time to change Vcc and Vbs should be made is small since having components such as VRM  310  and body bias generators  320  bonded to die  200  provides a fast response time.  
         [0021]     According to one embodiment, die  300  is flipped and bonded (metal-side to metal-side), thus bringing the various power management components as close to the CPU die  200  as possible. In a further embodiment, VRM die  300  is in a three dimensional (3D) packaging configuration with die  200 .  
         [0022]      FIG. 4  illustrates one embodiment of CPU  102 . CPU  102  includes the multi-Vcc VRM die  300  sandwiched between CPU die  200  and a package substrate  400 . According to one embodiment, VRM die  300  is pad matched to CPU die  200  and package substrate  400  so that die  300  can be an option sandwiched die. Thus, package  400  and CPU  200  design does not need any changes. In addition,  FIG. 4  shows the I/O connections between die  200  and  300 , as well as the die/die bonding. A heat spreader and heat sink (not shown) may be coupled to CPU die  200 .  
         [0023]     Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.