Abstract:
A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a divisional application of U.S. Ser. No. 13/358,840, filed Jan. 26, 2012, which application claims the benefit of priority of Japanese Patent Application No. 2011-40674, filed Feb. 25, 2011, the entire contents of which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    Embodiments disclosed herein relate to semiconductor apparatuses, methods for manufacturing semiconductor apparatuses and an electric device. 
       BACKGROUND 
       [0003]    Since Nitride semiconductors have characteristics including high electron saturation velocity and a wide band gap, they may be applied to high-breakdown voltage, high-power semiconductor devices GaN, an example of a nitride semiconductor, has a wider band gap than silicon (1.1 eV) and GaAs (1.4 eV), for example, 3.4 eV; therefore, it has high breakdown field strength. Therefore, GaN may be used as a material for power devices that operate at high voltage and output high voltage for power supply applications. 
         [0004]    The related art is disclosed in Japanese Laid-open Patent Publication Nos. 62-71301 and 5-121589 and Japanese Patent No. 3127895. 
       SUMMARY 
       [0005]    According to one aspect of the embodiments, a semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device. 
         [0006]    Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]      FIG. 1  illustrates an exemplary semiconductor package manufacturing process; 
           [0008]      FIGS. 2A to 2F  illustrate an exemplary semiconductor device manufacturing process; 
           [0009]      FIG. 3  illustrates an exemplary compound semiconductor device; 
           [0010]      FIGS. 4A and 4B  illustrate an exemplary semiconductor package; 
           [0011]      FIG. 5  illustrates an exemplary semiconductor package; 
           [0012]      FIGS. 6A and 6B  illustrate an exemplary semiconductor package; 
           [0013]      FIGS. 7A and 7B  illustrate an exemplary semiconductor package; 
           [0014]      FIGS. 8A and 8B  illustrate an exemplary semiconductor package; 
           [0015]      FIGS. 9A and 9B  illustrate an exemplary semiconductor package; 
           [0016]      FIG. 10  illustrates an exemplary semiconductor package; 
           [0017]      FIG. 11  illustrates an exemplary semiconductor package; 
           [0018]      FIG. 12  illustrates an exemplary semiconductor package manufacturing process; 
           [0019]      FIGS. 13A to 13C  illustrate an exemplary dicing; 
           [0020]      FIGS. 14A and 14B  illustrate an exemplary semiconductor package; 
           [0021]      FIGS. 15A and 15B  illustrate an exemplary semiconductor package; 
           [0022]      FIG. 16  illustrates an exemplary power supply device; and 
           [0023]      FIG. 17  illustrates an exemplary high-frequency amplifier. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0024]    Low-resistance transmission may be taken into account for power devices through which a large current flows. High heat dissipation may be taken into account for power devices that radiate large amounts of heat. For example, if a semiconductor device is mounted face-up on a flat circuit board by a low-cost wire bonding method, the wires may be made shorter or thicker for a low-resistance-transmission package. 
         [0025]    For the sake of convenience, the accurate sizes and accurate thicknesses may not be depicted in the drawings below. 
         [0026]      FIG. 1  illustrates an exemplary semiconductor package manufacturing process.  FIGS. 2A to 2F  illustrate an exemplary a semiconductor device manufacturing process. AlGaN/GaN high electron mobility transistors (HEMTs) may be manufactured by the semiconductor device manufacturing process illustrated in  FIGS. 2A to 2F . Compound semiconductor devices are manufactured through Operations S 1  and S 2  in  FIG. 1 , and semiconductor packages are manufactured through Operations S 3  to S 6  in  FIG. 1 . 
         [0027]    In the operation S 1  in  FIG. 1 , semiconductor devices for mounting on resin circuit boards, for example, compound semiconductor devices having an HEMT structure, are manufactured. For example, AlGaN/GaN HEMTs, which are nitride semiconductor devices, may be manufactured. Alternatively, for example, InAlN/GaN HEMTs or InAlGaN/GaN HEMTs may be manufactured. Nitride semiconductor devices other than HEMTs, compound semiconductor devices other than nitride semiconductor devices, semiconductor memories, or other semiconductor devices may also be manufactured. 
         [0028]    Referring to  FIG. 2A , a layered compound semiconductor structure  2  is formed on a growth substrate, for example, a silicon substrate  1 . For example, a silicon substrate, a SiC substrate, a sapphire substrate, a GaAs substrate, or a GaN substrate may be used as the growth substrate. The substrate may be a semi-insulating or conductive substrate. The layered compound semiconductor structure  2  may include a buffer layer  2   a , an electron transit layer  2   b , an intermediate layer  2   c , an electron supply layer  2   d , and a capping layer  2   e.    
         [0029]    In an operation of the AlGaN/GaN HEMT, the AlGaN/GaN HEMT generates a two-dimensional electron gas (2DEG) near the interface between the electron transit layer  2   b  and the electron supply layer  2   d , for example, the interface between the electron transit layer  2   b  and the intermediate layer  2   c . The 2DEG may be generated based on the difference between the lattice constant of the compound semiconductor of the electron transit layer  2   b , for example, GaN, and the lattice constant of the compound semiconductor of the electron supply layer  2   d , for example, AlGaN. 
         [0030]    Sequentially formed on the silicon substrate  1  are an AlN layer having a thickness of about 0.1 μm, an intentionally undoped GaN (i-GaN) layer having a thickness of about 3 μm, an i-AlGaN layer having a thickness of about 5 nm, an n-AlGaN layer having a thickness of about 30 nm, and an n-GaN layer having a thickness of about 10 nm. These compound semiconductors are formed by, for example, metal-organic vapor phase epitaxy (MOVPE). Instead of MOVPE, for example, molecular beam epitaxy (MBE) may be used. Thus, the buffer layer  2   a , the electron transit layer  2   b , the intermediate layer  2   c , the electron supply layer  2   d , and the capping layer  2   e  are formed. 
         [0031]    As the growth conditions of AlN, GaN, AlGaN, and GaN, a mixture of trimethylaluminum gas, trimethylgallium gas, and ammonia gas may be used as the source gas. The presence or absence of a supply of trimethylaluminum gas, which is an aluminum source, and a supply of trimethylgallium gas, which is a gallium source, and the flow rates thereof may be determined depending on the compound semiconductor layers grown. The flow rate of ammonia gas, which is a common source gas, may be about 100 ccm to 10 Lm. The growth pressure may be about 50 to 300 Torr. The growth temperature may be about 1,000° C. to 1,200° C. 
         [0032]    When forming n-type GaN and AlGaN, for example, SiH 4  gas including silicon serving as an n-type impurity is added to the source gas at a certain flow rate to dope GaN and AlGaN with silicon. The silicon doping concentration may be about 1×10 18 /cm 3  to 1×10 20 /cm 3 , for example, about 5×10 18 /cm 3 . 
         [0033]    Referring to  FIG. 2B , isolation structures  3  are formed. In  FIGS. 2C to 2F , the isolation structures  3  may be omitted. For example, argon (Ar) is implanted into the isolation regions of the layered compound semiconductor structure  2 . The isolation structures  3  are formed in the layered compound semiconductor structure  2  and the surface region of the silicon substrate  1 . The isolation structures  3  define active regions in the layered compound semiconductor structure  2 . Instead of implantation, the isolation structures  3  may be formed by, for example, shallow trench isolation (STI). For dry etching of the layered compound semiconductor structure  2 , for example, a chlorine-containing etching gas may be used. 
         [0034]    Referring to  FIG. 2C , a source electrode  4  and a drain electrode  5  are formed. Electrode recesses  2 A and  2 B are formed at the positions where the source electrode  4  and the drain electrode  5  are to be formed, for example, electrode formation positions, on the surface of the layered compound semiconductor structure  2 . The surface of the layered compound semiconductor structure  2  is applied with a resist. The resist is then processed by lithography to form openings which expose the surface of the layered compound semiconductor structure  2  corresponding to the electrode formation positions. Thus, a resist mask having openings are formed. 
         [0035]    Using the resist mask, the capping layer  2   e  is removed from the electrode formation positions by dry etching until the surface of the electron supply layer  2   d  is exposed. Thus, the electrode recesses  2 A and  2 B are formed at the electrode formation positions, where the surface of the electron supply layer  2   d  is exposed. The etching gas used may be an inert gas such as argon and a chlorine-containing gas such as Cl.sub.2. As the etching conditions, for example, the flow rate of Cl.sub.2 is set to 30 sccm, the pressure is set to 2 Pa, and the RF input power is set to 20 W. The electrode recesses  2 A and  2 B may be formed by terminating etching somewhere in the capping layer  2   e  or by continuing etching to the electron supply layer  2   d  or the underlying layers. The resist mask is removed by, for example, ashing. 
         [0036]    A resist mask for forming the source electrode  4  and the drain electrode  5  is formed. For example, an overhanging double-layer resist suitable for evaporation and a lift-off process may be used. The overhanging double-layer resist is applied to the layered compound semiconductor structure  2 , and openings where the electrode recesses  2 A and  2 B are exposed are formed. Thus, a resist mask having openings is formed. Using the resist mask, an electrode material, for example, tantalum and aluminum, is deposited over the resist mask, including the openings where the electrode recesses  2 A and  2 B are exposed, by, for example, evaporation. Tantalum may be deposited to a thickness of about 20 nm, and aluminum may be deposited to a thickness of about 200 nm. The resist mask and the tantalum and aluminum deposited thereon are removed by a lift-off process. The silicon substrate  1  is annealed at 400° C. to 1,000° C., for example, about 600° C., for example, in a nitrogen atmosphere, so that the remaining tantalum and aluminum form an ohmic contact with the electron supply layer  2   d . An ohmic contact may be formed without annealing. Thus, the electrode recesses  2 A and  2 B are filled with part of the electrode material, thereby forming the source electrode  4  and the drain electrode  5 . 
         [0037]    Referring to  FIG. 2D , an electrode recess  2 C for a gate electrode is formed on the layered compound semiconductor structure  2 . The surface of the layered compound semiconductor structure  2  is applied with a resist. The resist is then processed by lithography to form an opening in which the surface of the layered compound semiconductor structure  2  corresponding to the position where the gate electrode is to be formed, for example, an electrode formation position is exposed. Thus, a resist mask having an opening is formed. 
         [0038]    Using the resist mask, the capping layer  2   e  and part of the electron supply layer  2   d  are removed from the electrode formation position by dry etching. Thus, the electrode recess  2 C is formed, which extends through the capping layer  2   e  and part of the electron supply layer  2   d . An inert gas such as argon and a chlorine-containing gas such as Cl 2  may be used as the etching gas. As the etching conditions, for example, the flow rate of Cl 2  is set to 30 sccm, the pressure is set to 2 Pa, and the RF input power is set to 20 W. The electrode recess  2 C may be formed by terminating etching somewhere in the capping layer  2   e  or by continuing etching to a deeper position in the electron supply layer  2   d . The resist mask is removed by, for example, ashing. 
         [0039]    Referring to  FIG. 2E , a gate insulator  6  is formed. An insulating material, for example, Al 2 O 3 , is deposited on the layered compound semiconductor structure  2  so as to cover the inner wall surfaces of the electrode recess  2 C. For example, an Al 2 O 3  layer having a thickness of about 2 to 200 nm, for example, about 10 nm, is formed by atomic layer deposition (ALD). Thus, the gate insulator  6  is formed. 
         [0040]    Instead of ALD, Al 2 O 3  may be deposited by, for example, plasma-enhanced chemical vapor deposition (CVD) or sputtering. Instead of Al 2 O 3 , the gate insulator  6  may be formed of aluminum nitride or oxynitride. Alternatively, an oxide, nitride, or oxynitride of silicon, hafnium, zirconium, titanium, tantalum, or tungsten, or a multilayer structure of materials selected from these materials, may be used. 
         [0041]    Referring to  FIG. 2F , a gate electrode  7  is formed. A resist mask for forming the gate electrode  7  and a field plate electrode is formed. For example, an overhanging double-layer resist suitable for evaporation and a lift-off process is used. The overhanging double-layer resist is applied to the gate insulator  6 , and an opening where the portion of the gate insulator  6  facing the electrode recess  2 C is exposed is formed. Thus, a resist mask having an opening is formed. 
         [0042]    Using the resist mask, an electrode material, for example, nickel and gold, is deposited over the resist mask, including the opening where the portion of the gate insulator  6  facing the electrode recess  2 C is exposed, by, for example, evaporation. Nickel may be deposited to a thickness of about 30 nm, and gold may be deposited to a thickness of about 400 nm. The resist mask and the nickel and gold deposited thereon are removed by a lift-off process. Thus, the electrode recess  2 C is filled with part of the electrode material with the gate insulator  6  therebetween, thereby forming the gate electrode  7 . 
         [0043]    An interlayer insulator, interconnects coupled to the source electrode  4 , the drain electrode  5 , or the gate electrode  7 , an upper protective layer, and connection electrodes exposed in the outermost surface are formed. Thus, AlGaN/GaN HEMTs are formed. 
         [0044]    Metal-insulator-semiconductor (MIS) AlGaN/GaN HEMTs having the gate insulator  6  may be formed. Alternatively, Schottky AlGaN/GaN HEMTs that do not have the gate insulator  6 , with the gate electrode  7  in direct contact with the layered compound semiconductor structure  2 , may be formed. The gate recess structure in which the gate electrode  7  is formed in the electrode recess  2 C may not be used, and the gate electrode  7  may be formed on a layered compound semiconductor structure  2  having no recess, directly or with the gate insulator  6  therebetween. 
         [0045]    In the operation S 2 , the silicon substrate  1  having the AlGaN/GaN HEMTs formed in the operation S 1  is cut into individual compound semiconductor devices, for example, individual compound semiconductor chips. The silicon substrate  1  is cut into individual compound semiconductor devices by dicing along dicing lines formed thereon using, for example, a certain laser. 
         [0046]      FIG. 3  illustrates an exemplary compound semiconductor device. The compound semiconductor device illustrated in  FIG. 3  may be manufactured by the manufacturing process illustrated in  FIGS. 2A to 2F . A compound semiconductor device  10  has connection electrodes  11  for external connection arranged in a line along three of the four sides of the rectangular periphery thereof. The connection electrodes  11  are coupled to, for example, source electrodes, drain electrodes, or gate electrodes through, for example, underlying interconnects. 
         [0047]      FIGS. 4A and 4B  illustrate an exemplary semiconductor package.  FIG. 4A  indicates a sectional view, and  FIG. 4B  indicates a plan view. In the operation S 3  in  FIG. 1 , as illustrated in  FIGS. 4A and 4B , a recess  21 , for example, a countersink or cavity  21 , is formed on the front surface of a resin circuit board  20 . The resin circuit board  20  has copper (Cu) interconnects  23  formed on the front and back surfaces of a resin  22 . The copper interconnects  23  are coupled to each other through vias  24 . A metal core  25  including a heat-dissipating metal, for example, copper, is disposed in the resin  22 . Instead of copper, the metal core  25  may include at least one metal selected from gold (Au), nickel (Ni), aluminum (Al), titanium (Ti), and palladium (Pd). The front and back surfaces of the resin  22  are covered with solder resists  26  and  27 , respectively. The solder resist  26  on the front surface of the resin  22  has openings  26   a  and  26   b  where parts of the front surface of the resin  22  are exposed. Connection electrodes  28   a  to be coupled to the connection electrodes  11  of the compound semiconductor device  10  are formed at certain positions in the opening  26   a . Connection electrodes  28   b  for external connection are formed in the openings  26   b . The solder resist  27  on the back surface of the resin  22  has openings  27   a  and  27   b  where parts of the back surface of the resin  22  are exposed. Connection electrodes  29   a  and  29   b  for external connection are formed in the openings  27   a  and  27   b , respectively. In  FIGS. 4A and 4B , the resin circuit board  20  has through-holes. 
         [0048]      FIG. 5  illustrates an exemplary semiconductor package. The structure of the resin circuit board  20  illustrated in  FIG. 5  is substantially the same as or similar to the structure illustrated in  FIGS. 4A and 4B  as in  FIG. 5 , the resin circuit board  20  may not have through-holes. The resin circuit board  20  illustrated in  FIG. 4A  has through-holes extending through the resin  22 , for example, through-holes  31   a  and  31   b . Copper is deposited on the inner wall surfaces of the through-holes  31   a  and  31   b . The connection electrodes  28   a  on the front surface of the resin  22  and the connection electrodes  29   a  on the back surface of the resin  22  are coupled together through the through-holes  31   a . The connection electrodes  28   b  on the front surface of the resin  22 , the metal core  25 , and the connection electrodes  29   b  on the back surface of the resin  22  are coupled together through the through-holes  31   b . In the resin circuit board  20  illustrated in  FIG. 5 , the connection electrodes  28   b  on the front surface of the resin  22 , the metal core  25 , and the connection electrodes  29   b  on the back surface of the resin  22  are coupled together through the copper interconnects  23  and the vias  24 . 
         [0049]    The recess  21 , where part of the surface of the metal core  25  is exposed, is formed at a certain position on the surface of the resin  22  and the solder resist  26  by laser process or router process. The recess  21  has a landscape-oriented rectangular shape larger than the compound semiconductor device  10 , with three of the four sides of the periphery of the recess  21  extending along the connection electrodes  28   a  arranged in a line. After resin scattered during the process of the resin  22  is removed, the surfaces of the connection electrodes  28   a  and  29   a  exposed in the front surface and the surface of the metal core  25  exposed in the bottom surface of the recess  21  are plated with, for example, nickel and then gold. Although the metal core  25  exposed in the bottom surface of the recess  21  has a higher heat dissipation as its area fraction in the front surface of the resin circuit board  20  increases, the metal core  25  may optionally be patterned. 
         [0050]      FIGS. 6A and 6B  illustrate an exemplary semiconductor package.  FIG. 6A  indicates a sectional view, and  FIG. 6B  indicates a plan view. In  FIGS. 6A and 6B , the resin circuit board  20  has the through-holes  31   a  and  31   b . In the operation S 4  in  FIG. 1 , as illustrated in  FIGS. 6A and 6B , a dummy device  30  is disposed in the recess  21 , and an adhesive material with high heat dissipation (heat-dissipating adhesive material), for example, a metal material  32 , is supplied to the recess  21 . For example, a dummy device  30  having substantially the same shape and size as the compound semiconductor device  10  is disposed at a position where the compound semiconductor device  10  is to be fixed in the recess  21 . The dummy device  30  may include, for example, silicon, glass, or ceramic. The fixing position may be on the bottom surface of the recess  21 . Three sides of the dummy device  30 , for example, the sides corresponding to the three sides of the compound semiconductor device  10  where the connection electrodes  11  are formed, may be separated from the periphery of the recess  21  by about 0.01 to 0.1 mm, for example, about 0.05 mm. The remaining side of the dummy device  30 , for example, the side corresponding to the side of the compound semiconductor device  10  where the connection electrodes  11  are not formed, may be separated from the periphery of the recess  21  by about 4 mm or more, for example, about 10.05 mm. 
         [0051]    The dummy device  30  is disposed at the position where the compound semiconductor device  10  is to be fixed, and the metal material  32 , for example, a silver (Ag) sintering paste, is supplied to the recess  21  so as to have a thickness for at least partially covering the side surfaces of the dummy device  30 . The thickness may be a certain thickness. The certain thickness, for example, the thickness of the sintering paste, may be larger than or equal to half the height of the side surfaces of the dummy device  30  (middle position), for example, larger than or equal to half the thickness of the compound semiconductor device  10  (middle position). 
         [0052]    Instead of a silver sintering paste, the metal material  32  may be, for example, at least one material selected from gold and copper sintering pastes. Instead of a metal material, the heat-dissipating adhesive material may be an insulating material such as a BN or AlN paste. A conductive paste including diamond (C) may also be used. 
         [0053]      FIGS. 7A and 7B  illustrate an exemplary semiconductor package.  FIG. 7A  indicates a sectional view, and  FIG. 7B  indicates a plan view. In  FIGS. 7A and 7B , the resin circuit board  20  has the through-holes  31   a  and  31   b . In the operation S 5  in  FIG. 1 , as illustrated in  FIGS. 7A and 7B , the dummy device  30  is removed. After the dummy device  30  is removed, the metal material  32  having the certain thickness is left on the entire surface in the recess  21  excluding the position where the compound semiconductor device  10  is to be fixed. The fixing position defined in the recess  21  by the metal material  32  may be a fixing position  32   a.    
         [0054]      FIGS. 8A and 8B  illustrate an exemplary semiconductor package.  FIG. 8A  indicates a sectional view, and  FIG. 8B  indicates a plan view. In  FIGS. 8A and 8B , the resin circuit board  20  has the through-holes  31   a  and  31   b . In the operation S 6  in  FIG. 1 , as illustrated in  FIGS. 8A and 8B , the compound semiconductor device  10  with a metal material  33  on its back surface is bonded in the recess  21  of the resin circuit board  20 . The metal material  33  is applied to the back surface of the semiconductor device  10  with a certain thickness, for example, a thickness smaller than that of the metal material  32 . A silver sintering paste that is substantially the same as the metal material  32  may be used as the metal material  33  or a different metal, for example, at least one material selected from gold and copper sintering pastes may be used. The compound semiconductor device  10  having the metal material  33  applied to the back surface thereof is provisionally fixed to the fixing position  32   a  face-up in the recess  21 . The compound semiconductor device  10  may be provisionally fixed under a pressure of, for example, about 2 kgf. The metal materials  32  and  33  are hardened at about 150° C. to 250° C., for example, about 200° C. under atmospheric pressure for about one hour. Thus, the compound semiconductor device  10  is bonded to the fixing position  32   a  in the recess  21 . 
         [0055]    The metal material  33  is applied to the back surface of the compound semiconductor device  10 . Alternatively, a metal material may be applied to the surface of the metal core  25  at the fixing position  32   a  in the recess  21  with substantially the same thickness, and the compound semiconductor device  10  may be disposed on the metal material. In this case, provisional fixing and hardening may be carried out under substantially the same conditions as above. 
         [0056]    Because the metal material  32  is formed using the dummy device  30 , the metal material  32  has a certain thickness so as to cover the side surfaces of the compound semiconductor device  10 . The metal material  32  covers the side surfaces of the compound semiconductor device  10  between the sides of the compound semiconductor device  10  where the connection electrodes  11  are formed and the periphery of the recess  21 . For example, the distance between the sides of the compound semiconductor device  10  where the connection electrodes  11  are formed and the periphery of the recess  21  may reduce or be in contact for shorter in order to short metal wires. The metal material  32  may not be in the distance. Because the heat dissipation effect of the metal material  32  is proportional to its size, for example, its surface area, the metal material  32  may not be in the distance. The compound semiconductor device  10  may be bonded with a metal material without using the dummy device  30 . 
         [0057]      FIGS. 9A and 9B  illustrate an exemplary semiconductor package.  FIG. 9A  indicates a sectional view, and  FIG. 9B  indicates a plan view, In  FIGS. 9A and 9B , the resin circuit board  20  has the through-holes  31   a  and  31   b . In the operation S 7  in  FIG. 1 , as illustrated in  FIGS. 9A and 9B , the connection electrodes  11  of the compound semiconductor device  10  and the connection electrodes  28   a  of the resin circuit board  20  are coupled together by wire bonding. Metal wires  34  are used to couple the facing connection electrodes  11  and  28   a  on the three sides of the compound semiconductor device  10  and the three sides of the resin circuit board  20 . For example, aluminum wires having a diameter of about 100 to 2,500 μm, for example, about 100 μm, and a length of, for example, about 0.1 mm is used as the metal wires  34 . Instead of aluminum wires, metal wires selected from gold, copper, and palladium wires is used as the metal wires  34 . Thus, a semiconductor package is fabricated. 
         [0058]    The compound semiconductor device  10  is fixed in the recess  21  formed on the resin circuit board  20  with the metal materials  32  and  33 . The compound semiconductor device  10  may be disposed at a certain position on the bottom surface of the recess  21 . The compound semiconductor device  10  may be disposed such that the three sides of the periphery of the compound semiconductor device  10  where the connection electrodes  11  are disposed are separated from the periphery of the recess  21  by a smaller distance, whereas the side where the connection electrodes  11  are not disposed is separated from the periphery of the recess  21  by a larger distance. In the wide region corresponding to the larger distance between the periphery of the compound semiconductor device  10  and the periphery of the recess  21 , the metal material  32  is applied so as to have a thickness to cover the side surface of the compound semiconductor device  10  to a certain position. Heat is efficiently dissipated through the metal materials  32  and  33  from the bottom and side surfaces of the compound semiconductor device  10 , for example, from the portion covered with the metal material  32 . Heat dissipation may be improved because the metal material  32  occupies a large area. In the narrow regions corresponding to the smaller distance between the periphery of the compound semiconductor device  10  and the periphery of the recess  21 , the metal wires  34  couple the facing connection electrodes  11  and  28   a . Low-resistance transmission is performed because the metal wires  34  become shorter. 
         [0059]    Thus, provided is a low-cost semiconductor package of the compound semiconductor device  10  that allows low-resistance transmission and high heat dissipation with a simple structure. 
         [0060]      FIG. 10  illustrates an exemplary semiconductor package. The semiconductor package illustrated in  FIG. 10  may correspond to the semiconductor package illustrated in  FIG. 9B . In  FIG. 10 , the elements that are substantially the same as or similar to those of the semiconductor package illustrated in  FIG. 9B  may be denoted by the same reference numerals, and a description thereof may be omitted or reduced. The semiconductor package may be fabricated through the operations S 1  to S 7  in  FIG. 1 . Referring to  FIG. 10 , a compound semiconductor device  40  has connection electrodes  11  for external connection arranged in a line along facing two of the four sides of the rectangular periphery thereof. The resin circuit board  20  has a recess  41  where part of the surface of the metal core is exposed. The recess  41  has a landscape-oriented rectangular shape larger than the compound semiconductor device  40 , with two facing sides of the periphery of the recess  41  extending along the connection electrodes  28   a  arranged in a line. 
         [0061]    In the recess  41 , the side surfaces of the compound semiconductor device  40  are fixed with the metal material  32 , and the bottom surface is fixed with the metal material  33 . The two facing sides where the connection electrodes  11  are formed are separated from the periphery of the recess  41  by about 0.01 to 0.1 mm, for example, about 0.05 mm. The two facing sides where the connection electrodes  11  are not formed are separated from the periphery of the recess  41  by about 4 mm or more, for example, about 6.5 mm. 
         [0062]    The compound semiconductor device  40  is fixed in the recess  41  formed on the resin circuit board  20  with the metal materials  32  and  33 . The compound semiconductor device  40  may be disposed at a certain position on the bottom surface of the recess  41 . The compound semiconductor device  40  may be disposed such that the two sides of the periphery of the compound semiconductor device  40  where the connection electrodes  11  are disposed are separated from the periphery of the recess  41  by a smaller distance, whereas the two sides where the connection electrodes  11  are not disposed are separated from the periphery of the recess  41  by a larger distance. In the wide regions corresponding to the larger distance between the periphery of the compound semiconductor device  40  and the periphery of the recess  41 , the metal material  32  is applied so as to have a thickness to cover the side surfaces of the compound semiconductor device  40  to a certain position. Heat is efficiently dissipated through the metal materials  32  and  33  from the bottom and side surfaces of the compound semiconductor device  40 , for example, from the portion covered with the metal material  32 . Heat dissipation may be improved because the metal material  32  occupies a large area. In the narrow regions corresponding to the smaller distance between the periphery of the compound semiconductor device  40  and the periphery of the recess  41 , the metal wires  34  couple the facing connection electrodes  11  and  28   a . Low-resistance transmission is performed because the metal wires  34  become shorter. 
         [0063]    Thus, provided is a low-cost semiconductor package of the compound semiconductor device  40  that allows low-resistance transmission and high heat dissipation with a simple structure. 
         [0064]      FIG. 11  illustrates an exemplary semiconductor package. The semiconductor package illustrated in  FIG. 11  may correspond to the semiconductor package illustrated in  FIG. 9B . In  FIG. 11 , the elements that are substantially the same as or similar to those of the semiconductor package illustrated in  FIG. 9B  may be denoted by the same reference numerals, and a description thereof may be omitted reduced. The semiconductor package may be fabricated through the operations S 1  to S 7  in  FIG. 1 . Referring to  FIG. 11 , a compound semiconductor device  50  has connection electrodes  11  for external connection arranged in a line along one of the four sides of the rectangular periphery thereof. The resin circuit board  20  has a recess  51  where part of the surface of the metal core is exposed. The recess  51  has a landscape-oriented rectangular shape larger than the compound semiconductor device  50 , with one side of the periphery of the recess  51  extending along the connection electrodes  28   a  arranged in a line. 
         [0065]    In the recess  51 , the side surfaces of the compound semiconductor device  50  are fixed with the metal material  32 , and the bottom surface is fixed with the metal material  33 . The side of the compound semiconductor device  50  where the connection electrodes  11  are formed is separated from the periphery of the recess  51  by about 0.01 to 0.1 mm, for example, about 0.05 mm. The three sides where the connection electrodes  11  are not formed are separated from the periphery of the recess  51  by about 4 mm or more, for example, about 10.05 mm. 
         [0066]    The compound semiconductor device  50  is fixed in the recess  51  formed on the resin circuit board  20  with the metal materials  32  and  33 . The compound semiconductor device  50  may be disposed at a certain position on the bottom surface of the recess  51 . The compound semiconductor device  50  may be disposed such that three sides of the periphery of the compound semiconductor device  50  are separated from the periphery of the recess  51  by a smaller distance, whereas the remaining side is separated from the periphery of the recess  51  by a larger distance. In the wide region corresponding to the larger distance between the periphery of the compound semiconductor device  50  and the periphery of the recess  51 , the metal material  32  is applied so as to have a thickness to cover the side surface of the compound semiconductor device  50  to a certain position. Heat is efficiently dissipated through the metal materials  32  and  33  from the bottom and side surfaces of the compound semiconductor device  50 , for example, from the portion covered with the metal material  32 . Heat dissipation may be improved because the metal material  32  occupies a large area. In the narrow regions corresponding to the smaller distance between the periphery of the compound semiconductor device  50  and the periphery of the recess  51 , the metal wires  34  couple the opposing facing electrodes  11  and  28   a . Low-resistance transmission is performed because the metal wires  34  become shorter. 
         [0067]    Thus, provided is a low-cost semiconductor package of the compound semiconductor device  50  that allows low-resistance transmission and high heat dissipation with a simple structure. 
         [0068]      FIG. 12  illustrates an exemplary semiconductor package manufacturing process. In an operation S 11  in  FIG. 12 , AlGaN/GaN HEMTs are fabricated similarly to the operation S 1  illustrated in  FIG. 1 . 
         [0069]    In an operation S 12  in  FIG. 12 , as illustrated in  FIG. 13A , the silicon substrate  1  having the AlGaN/GaN HEMTs fabricated in the operation S 11  is incompletely diced. For example, the silicon substrate  1  is incompletely diced from the back surface  1   b  (opposite the front surface  1   a ) thereof along dicing lines DL formed thereon using, for example, a certain blade or laser (laser dicing). The dicing may be incomplete when terminated. For example, the dicing may be terminated when grooves  1 A that appear in dicing becomes the depth corresponding to the height to which molten metal material is to cover the side surfaces of the compound semiconductor devices. The depth of the grooves  1 A may be larger than or equal to half the thickness of the compound semiconductor devices (middle position). 
         [0070]      FIGS. 13A to 13C  illustrate an exemplary dicing. In an operation S 13 , as illustrated in  FIG. 13B , a metal thin film  61  for improving wettability to molten metal material is formed on the back surface  1   b  of the silicon substrate  1  so as to cover the inner wall surfaces of the grooves  1 A. For example, a metal having the property of improving wettability to molten metal material, for example, a multilayer film of titanium, nickel, and gold, is formed by, for example, sputtering, vacuum deposition, or plasma-enhanced CVD. Thus, the metal thin film  61  is formed. Instead of a multilayer film of titanium, nickel, and gold, a multilayer film of one or more metals selected from gold, copper, nickel, aluminum, titanium, and palladium may be used as the metal thin film  61 . 
         [0071]    In an operation S 14 , as illustrated in  FIG. 13C , the silicon substrate  1  is cut into individual compound semiconductor devices  60  by laser dicing along the dicing lines DL on the bottom surface  1   b  of the silicon substrate  1 . The metal thin film  61 , which covers the compound semiconductor device  60  from the entire bottom surface  1   b  to a certain height along the side surfaces, are formed in Each compound semiconductor device  60 . As with the compound semiconductor device  10  illustrated in  FIG. 3 , a plurality of connection electrodes  11  are arranged in a line along three of the four sides of the rectangular periphery of the compound semiconductor device  60 . 
         [0072]    In an operation S 15 , a recess is formed on the front surface of a resin circuit board similarly to the operation S 3  in  FIGS. 4A and 4B . 
         [0073]      FIGS. 14A and 14B  illustrate an exemplary semiconductor package. In an operation S 16 , as illustrated in  FIGS. 14A and 14B , the compound semiconductor device  60  is bonded in the recess  21  of the resin circuit board  20 . For example, the compound semiconductor device  60  is bonded to a predetermined position on the bottom surface of the recess  21  of the resin circuit board  20  with a molten metal material  62 , for example, tin-silver (Sn—Ag). Instead of tin-silver, for example, tin-silver-bismuth (Sn—Ag—Bi), or a plurality of metals selected from tin, lead (Pb), silver, indium (In), bismuth, zinc (Zn), antimony (Sb), and copper may be used as the molten metal material  62 . For example, the three sides of the compound semiconductor device  60  where the connection electrodes  11  are formed may be separated from the periphery of the recess  21  by about 0.01 to 0.1 mm, for example, about 0.05 mm. The side where the connection electrodes  11  are not formed may be separated from the periphery of the recess  21  by about 4 mm or more, for example, about 10.05 mm. 
         [0074]    The metal thin film  61  for improving wettability to the molten metal material  62  is formed so as to cover the compound semiconductor device  60  from the entire bottom surface  1   b  to a certain height along the side surfaces. The molten metal material  62  contacts the compound semiconductor device  60  in the region where the metal thin film  61  is formed on the compound semiconductor device  60 , for example, from the entire bottom surface  1   b  of the compound semiconductor device  60  to a certain height along the side surfaces. The portion of the molten metal material  62  that contacts one of the side surfaces of the compound semiconductor device  60  forms a gently convex surface  62   a  whose height decreases gradually from the side surface toward the sidewall of the recess  21  under the surface tension of the molten metal. The convex surface may have a larger surface area than a flat surface area of uniform height. The molten metal material  62  may maintain its shape after being solidified by cooling. 
         [0075]    The metal material  62  covers the side surfaces of the compound semiconductor device  60  between the sides of the compound semiconductor device  60  where the connection electrodes  11  are formed and the periphery of the recess  21 . For example, the sides of the compound semiconductor device  60  where the connection electrodes  11  are formed and the periphery of the recess  21  may be separated by a smaller distance or be in contact in order to short metal wires. The metal material  62  may not be in the small distance. Because the heat dissipation effect of the metal material  62  is proportional to its size, for example, its surface area, the metal material  62  may be in the narrow regions. 
         [0076]      FIGS. 15A and 15B  illustrate an exemplary semiconductor package. As illustrated in  FIGS. 15A and 15B , in an operation S 17  in  FIG. 12 , the connection electrodes  11  of the compound semiconductor device  60  and the connection electrodes  28   a  of the resin circuit board  20  are coupled together by wire bonding similarly to the operation S 7  in  FIG. 1 . Thus, a semiconductor package is fabricated. 
         [0077]    The compound semiconductor device  60  is fixed in the recess  21  formed on the resin circuit board  20  with the solidified metal material  62 . The compound semiconductor device  60  may be disposed at a certain position on the bottom surface of the recess  21 . The compound semiconductor device  60  may be disposed such that the three sides of the periphery of the compound semiconductor device  60  where the connection electrodes  11  are disposed are separated from the periphery of the recess  21  by a smaller distance, whereas the side where the connection electrodes  11  are not disposed is separated from the periphery of the recess  21  by a larger distance. In the wide region corresponding to the larger distance between the periphery of the compound semiconductor device  60  and the periphery of the recess  21 , the molten metal material  62  is applied so as to have a thickness to cover the side surface of the compound semiconductor device  60  to a certain position. Heat is efficiently dissipated through the molten metal material  62  from the bottom and side surfaces of the compound semiconductor device  60 , for example, from the portion covered with the molten metal material  62 . Heat dissipation may be improved because the molten metal material  62  occupies a large area. The molten metal material  62  may form the gently convex surface  62   a  whose height decreases gradually from the side surface toward the sidewall of the recess  21 . The convex surface  62   a  has a larger surface area and therefore dissipates a larger amount of heat than a flat surface area of uniform height. In the narrow regions corresponding to the smaller distance between the periphery of the compound semiconductor device  60  and the periphery of the recess  21 , the metal wires  34  couple the facing connection electrodes  11  and  28   a . Low-resistance transmission is performed because the metal wires  34  become shorter. 
         [0078]    Thus, provided is a low-cost semiconductor package of the compound semiconductor device  60  that allows low-resistance transmission and high heat dissipation with a simple structure. 
         [0079]    As in the semiconductor packages illustrated in  FIGS. 10 and 11 , a compound semiconductor device having the connection electrodes  11  formed along one or two sides thereof may be fixed in a recess of a resin circuit board with a molten metal material. A metal thin film for improving wettability to molten metal material may be formed on the compound semiconductor device through the operations S 12  to S 14  in  FIG. 12 . 
         [0080]      FIG. 16  illustrates an exemplary power supply device. The power supply device illustrated in  FIG. 16  may include a semiconductor package manufactured by the manufacturing process illustrated in  FIG. 1  or  12 . 
         [0081]    The power supply device includes a high-voltage primary circuit  71 , a low-voltage secondary circuit  72 , and a transformer  73  disposed between the primary circuit  71  and the secondary circuit  72 . The primary circuit  71  includes an alternating-current power supply  74 , a bridge rectifier circuit  75 , and a plurality of switching devices, for example, four switching devices  76   a ,  76   b ,  76   c , and  76   d . The bridge rectifier circuit  75  includes a switching device  76   e . The secondary circuit  72  includes a plurality of switching devices, for example, three switching devices  77   a ,  77   b , and  77   c.    
         [0082]    The switching devices  76   a ,  76   b ,  76   c ,  76   d , and  76   e  of the primary circuit  71  may be compound semiconductor devices, for example, AlGaN/GaN HEMTs, fabricated in the operation S 1  in  FIG. 1 . The switching devices  77   a ,  77   b , and  77   c  of the secondary circuit  72  may be metal-insulator-semiconductor field-effect transistors (MISFETs) including silicon. 
         [0083]    Thus, a low-cost semiconductor package of a compound semiconductor device that allows low-resistance transmission and high heat dissipation with a simple structure is applied to a high-voltage circuit. 
         [0084]      FIG. 17  illustrates an exemplary high-frequency amplifier. The high-frequency amplifier illustrated in  FIG. 17  may include a semiconductor package manufactured by the manufacturing process illustrated in  FIG. 1  or  12 . 
         [0085]    The high-frequency amplifier includes a digital predistortion circuit  81 , mixers  82   a  and  82   b , and a power amplifier  83 . The digital predistortion circuit  81  compensates for nonlinear distortion in an input signal. The mixer  82   a  mixes the input signal whose nonlinear distortion has been compensated for with an alternating-current signal. The power amplifier  83  amplifies the input signal mixed with the alternating-current signal. The power amplifier  83  includes a compound semiconductor device, for example, AlGaN/GaN HEMT, fabricated in the operation S 1  in  FIG. 1 . For example, based on switching, the mixer  82   b  mixes the signal on the output side with an alternating-current signal and outputs the mixed signal to the digital predistortion circuit  81 . 
         [0086]    Thus, a low-cost semiconductor package of a compound semiconductor device that allows low-resistance transmission and high heat dissipation with a simple structure is applied to a high-voltage circuit. 
         [0087]    Example embodiments of the present invention have now been described in accordance with the above advantages. It will be appreciated that these examples are merely illustrative of the invention. Many variations and modifications will be apparent to those skilled in the art.