Abstract:
A charge packet differencer is implemented in a charge coupled device in such a manner that a first charge packet may be subtracted from a second charge packet thus giving a resultant charge packet equal to the difference between the first and second charge packets. The charge coupled device differencer comprises a semiconductor substrate in which there is formed first and second charge transfer devices, first and second charge substraction mechanisms, and a charge reservoir cooperating to produce a charge packet output representative of the difference between two input charge packets using a gate charge subtraction technique.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to charge coupled devices (CCD) and in particular to the use of such devices for creating a charge packet which is equal to the difference of two input charge packets. 
     2. Background Art 
     In the technology of charge coupled devices various techniques have been used to do the arithmetic operation of subtraction. One such example of CCD subtraction is disclosed in U.S. Pat. No. 4,085,441 entitled &#34;Monolithic Implementation of a Fast Fourier Transform&#34; issued Apr. 18, 1978 to John L. Fagan on an application filed Nov. 24, 1976 and assigned to Westinghouse Electric Corporation. The patent issued to Fagan describes a CCD subtractor structure where two input signal voltages are subtracted one from the other using a charge-skimming technique. The resulting charge packet is representative of the difference between the two input voltages and is then converted into an output voltage. However, this structure utilizes input voltages and would not be compatible where discrete input charge packet subtraction is required. 
     In applications where discrete charge packets are to be subtracted, the most common technique requires the discrete charge packets to be converted into voltages so that the subtraction operation may be performed. An example of the technique of converting charge packets into voltages for subtracting is disclosed in U.S. Pat. No. 4,104,543 entitled &#34;Multichannel CCD Signal Subtraction System&#34; issued Aug. 1, 1978 to Dale G. Maeding on an application filed Feb. 22, 1977 and assigned to Hughes Aircraft Company. The patent issued to Maeding discloses a multichannel CCD structure which permits input signal charge packets to be subtracted one from another by alternately passing them under a common, periodically clamped floating electrode. The voltage assumed by the unclamped floating electrode is the difference between the charges. Hence, an output voltage represents the difference in the quantity of charge in two inputs signal charge packets. To obtain an output signal charge packet representative of the difference between the two input signal charge packets, the output voltage must be reconverted back into a charge packet. 
     For computationally intensive applications, such as that which might be employed in a focal plane imaging device for image preprocessing, a premium is placed on computing accuracy and real estate consumption. For such applications, the approaches described above for charge packet differencing are cumbersome and undesirable. 
     In many applications it is preferrable to directly subtract a first input charge packet from a second input charge packet with a resultant charge packet being the difference between the two input charge packets. An example of such a CCD subtractor is disclosed in U.S. Pat. No. 4,239,983 entitled &#34;Non-Destructive Charge Transfer Device Differencing Circuit&#34; issued Dec. 16, 1980 to Edwards et al on an application filed Mar. 9, 1979 and assigned to International Business Machines Corporation. The patent issued to Edwards et al discloses a CCD subtractor circuit wherein input charge packets are substracted using a floating gate electrode structure connected to a common node and diffusion. The input charge packets are represented as a separate pair of spatially separate charge packets which in turn represent positive and negative algebraic values using charge carriers of the same polarity. A disadvantage of such a subtractor circuit is that discrete charge packets must be broken into spatially separate charge packets. Directly inputting two charge packets would result in an output charge packet that would be the addition of the two input charge packets and not the difference. 
     It is therefore, an objective of the present invention to provide a CCD device for precise differencing of charge packets by using a gate charge subtraction technique which enhances the accuracy and linearity of the resultant charge packet. 
     It is another objective of the present invention to provide a CCD device which in addition to being a charge subtractor can be used as a charge packet replicator. 
     A further objective of the present invention is to provide a CCD device which can be used as a charge packet amplifier (or attenuator), individually, or in combination with the subtractor or replicator functions. 
     SUMMARY OF THE INVENTION 
     In the present invention, a charge packet differencer is implemented in a charge coupled device structure such that an input charge packet may be subtracted from another input charge packet giving a resultant charge packet equal to the difference between the input charge packets. 
     The charge coupled device differencer of the present invention comprises a semiconductor substrate in which there is formed a first charge transfer means for receiving and transferring a first charge packet and a second charge transfer means for receiving and transferring a second charge packet. A first charge subtraction means is provided such that a first potential well is formed in the substrate in proportion to the first charge packet. A second charge subtraction means is provided such that a second potential well is formed in the substrate in proportion to the second charge packet. A charge reservoir means is provided for injecting a third charge packet into the formed first and second potential wells and for removing a fourth charge packet from the potential wells. 
     The removed fourth charge packet is less than the third charge packet when the first charge packet is greater than the second charge packet. The difference between the third and fourth charge packets remains in the second potential well and represents the difference between the first and second charge packets. However, the fourth charge packet equals the third charge packet when the first charge packet is less than or equal to the second charge packet. Therefore there is no difference charge packet which remains in the second potential well. 
     The present invention comprises a circuit which utilizes vertical charge-coupling between the electrodes and semiconductor surface in addition to the usual lateral charge-coupling to perform the differencing operation. The input charge packets are coupled to precharged electrodes through a gate charge subtraction cycle. Using the charge on the electrode, an output charge packet is formed through surface potential equilibration, though not in the electrode voltage mode normally associated with this charge setting method. 
     The charge-coupled device differencer of the present invention is useful as a prime functional building block of an array of charge-coupled computers located on a single semiconductor chip. Such a charge coupled device differencer would also find application in focal plane array for processing of image data or in a robot vision system. The present invention having a reduced number of electrodes, occupies less chip real estate, thereby allowing for a reduction in volume and complexity of the image processing system. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic illustration of a charge coupled device differencer. 
     FIG. 2 illustrates the waveform of voltages applied to the charge coupled device differencer illustrated in FIG. 1. 
     FIG. 3a is a simplified schematic illustration of the charge coupled device differencer of FIG. 1 while FIGS. 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3i, and 3j illustrate the voltage potential profiles showing the location of charge propagated through the simplified schematic of FIG. 3a, when charge packet Q A  is greater than charge packet Q B . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention comprises a novel charge coupled device differencer. The following detailed description of the preferred embodiment of the invention is provided to enable any person skilled in the art to make and use the present invention. 
     The charge coupled device differencer of the present invention as illustrated in FIG. 1 is formed on a semiconductor substrate 10. Substrate 10 can be either a p-type or n-type doped semiconductor material, such as silicon. The following description will describe a device having a n-channel configuration using a p-type silicon substrate. However, it is readily apparent to one skilled in the art that a p-channel configuration using a n-type substrate may be constructed from the teaching of the n-channel configuration. 
     A first charge transfer means is formed on substrate 10 for receiving and transferring a first quantity of charge carriers. The first charge transfer means comprises electrodes 12 and 16 overlying substrate 10. Electrodes 12 and 16 are insulated from substrate 10 by a thin insulating layer 20, which is preferrably a layer of SiO 2  perhaps 600 Angstroms thick. Electrodes 12 and 16 may for example be aluminum deposited on top of insulating layer 20 as shown in FIG. 1 or may be heavily doped polysilicon on layer 20. Electrodes 12 and 16 are located adjacent each other above first charge flow channel 22 to permit charge packet transfer between potential wells created below electrodes 12 and 16 in substrate 10. Electrode 12 is coupled to clock signal V A  by lead 14 while electrode 16 is coupled to clock signal V X  by lead 18. 
     A second charge transfer means is formed on substrate 10 for receiving and transferring a second quantity of charge carriers. The second charge transfer means comprises electrodes 24 and 28 overlying substrate 10. Electrodes 24 and 28 are insulated from substrate 10 by insulating layer 20. Electrodes 24 and 28 are located adjacent each other above second charge flow channel 32. Charge flow channel 32 is structurally separate from charge flow channel 22. Charge carriers, in the form of charge packets, are injected into either one of charge flow channels 22 and 32 and flow respectively therein. Electrode 24 is coupled to clock signal V B  by lead 26. Electrode 28 is connected to electrode 16 by leads 30 and 18, which effectively couples electrode 28 to clock signal V X . 
     A first charge subtraction means formed on substrate 10 comprises diffusion 34 coupled to electrode 36. Diffusion 34 is located in substrate 10 adjacent the area below electrode 16 thus being adjacent charge flow channel 22. Diffusion 34 is a n +  -type diffusion in p-type substrate 10. Diffusion 34 is connected to electrode 36 by lead 38. 
     Electrode 36 is insulated from substrate 10 by layer 20 and may be of the same composition as electrodes 12, 16, 24 and 28. Electrode 36 has a surface area defined as A 1 . Electrode 36 is coupled by lead 40 to a first precharge means 50. The first precharge means controls the placing of a charge on electrode 36 from a voltage source (not shown in FIG. 1). This voltage source has an output voltage, V 0 . 
     A second charge subtraction means formed on substrate 10 comprises diffusion 42 coupled to electrode 44. Diffusion 42 is located in substrate 10 adjacent the area below electrode 28, thus being adjacent charge flow channel 32. Diffusion 42, like diffusion 34, is an n +  -type diffusion in p-type substrate 10. Diffusion 42 is connected to electrode 44 by lead 46. 
     Electrode 44 is insulated from substrate 10 by layer 20 and may be of the same composition as electrodes 12, 16, 24, 28 and 36. Electrode 44 has a surface area defined as A 2 . Electrode 44 is coupled by lead 48 to a second precharge means 60. This second precharge means controls the placing of a charge on electrode 44 from a voltage source (not shown in FIG. 1). This voltage source can be the same voltage source which supplies the voltage, V 0 , to the first precharge means. 
     Electrodes 36 and 44 are situated on substrate 10 such that a charge flow channel 78 is formed beneath electrodes 36 and 44. 
     First and second precharge means (50 and 60 respectively) are comprised of electrical switches, preferably field effect transistors. FET switch 50 has its drain 52 connected to the voltage source which supplies voltage V 0 , while source 54 is connnected to electrode 36 by lead 40. FET switch 50 has gate 56 coupled to receive a clock signal V pc . FET switch 60 has drain 62 also connected to the voltage source supplying voltage V 0  , while source 64 is connected to electrode 44 by lead 48. FET switch 60 has gate 66 also coupled to receive clock signal V pc . 
     A third charge transfer means is formed on substrate 10 adjacent electrode 44. This third charge transfer means comprises electrodes 70 and 74. Electrodes 70 and 74 are insulated from substrate 10 by layer 20 and may be of the same construction as electrode 12, 16, 24, 28, 36 and 44. Electrode 70 is located on substrate 10 between and adjacent electrodes 44 and 74 above charge flow channel 78. Electrode 70 is coupled by lead 72 to receive clock signal V XO  while electrode 74 is coupled by lead 76 to receive clock signal V S . 
     Referring to FIGS. 2 and 3, the operation of the present invention is described for subtraction of a smaller charge packet Q B  from a larger charge packet Q A . 
     At a time prior to t o , clock signals V A  and V B  are clocked &#34;high,&#34; thus applying positive voltages to input electrodes 12 and 24. The applied voltages cause input potential wells 116 and 118 to form beneath electrodes 12 and 24 in substrate 10. Charge packets Q A  and Q B  are then respectively shifted into input potential wells 116 and 118 by means well known to those skilled in the art. 
     During the time period t o  to t 1 , as shown in FIG. 3b, charge packet Q A  resides in input potential well 116 beneath electrode 12 while charge packet Q B  resides in input potential well 118 beneath electrode 24. FIG. 3c illustrates the time period t 1  to t 2  as clock signal V pc  is applied to switches 50 and 60. Upon clock signal V pc  going from &#34;low&#34; to &#34;high,&#34; i.e., zero to a higher potential, switches 50 and 60 change from the non conducting to the conducting state. With switches 50 and 60 in the conducting state, voltage V 0  from an external voltage source (not shown) is placed on charge subtraction electrodes 36 and 44. This application of voltage V 0  to electrodes 36 and 44 places a charge on electrodes 36 and 44. The charge on electrodes 36 and 44 causes the formation of charge subtractor potential wells 128 and 130 (illustrated by arrows A and B in FIG. 3c), respectively, beneath electrodes 36 and 44 in substrate 10 in proportion to voltage V 0 . 
     FIG. 3d illustrates the time period from t 2  to t 3 . At time t 2 , clock signal V pc  goes &#34;low&#34;, thus placing switches 50 and 60 in the non-conducting state with a charge remaining on electrodes 36 and 44. Potential wells 128 and 130 exist beneath electrodes 36 and 44 even after the removal of voltage V 0  from electrodes 36 and 44 because of the charge that remains on electrodes 36 and 44. Electrodes 36 and 44 are constructed such that the surface area of electrode 36 is represented by A 1  while that of electrode 44 is represented by A 2 . The charge on electrode 36, Q E1 , is given by the following relationship: ##EQU1## where θ=2 q  N A  E S  and 
     E S  =dielectric constant of silicon 
     ψ S1  =surface potential under electrode 36. 
     Similarly, the charge on electrode 44, Q E2 , is given by the following relationship: ##EQU2## ψ S2  =surface potential under electrode 44. 
     Since the surface potential under electrodes 36 and 44 is the same for ψ S1  =ψ S2 , equations (1) and (2) can be reduced to the following equation: ##EQU3## 
     During the time period t 3  to t 4  of FIG. 2 and FIG. 3e, V X , applied to charge transfer electrodes 16 and 28, goes from &#34;low&#34; to &#34;high&#34;. In FIG. 3e the &#34;high&#34; V X  clock signal applied to electrodes 16 and 28 causes charge transfer potential wells 136 and 138 to be formed respectively under electrodes 16 and 28. Diffusion 34, located in substrate 10 adjacent potential well 136, is electrically connected to electrode 36 which has charge Q E1  thereupon. Diffusion 42, located in substrate 10 adjacent potential well 138, is electrically connected to electrode 44 which has charge Q E2  thereupon. As potential wells 136 and 138 are being formed, charge packets Q A  and Q B  begin to spill respectively into potential wells 136 and 138. 
     As charge packet Q A  spills into potential well 136, the minority charge carriers comprising charge packet Q A  are attracted into diffusion 34 (illustrated by arrow C in FIG. 3e). Since diffusion 34 is electrically connected to electrode 36, the minority charge carriers of charge packet Q A  begin to recombine with the charge on electrode 36, Q E1 . Similarly, the minority charge carriers of charge packet Q B  spill into potential well 138 and are attracted into diffusion 42 (illustrated by arrow D in FIG. 3e). Since diffusion 42 is electrically connected to electrode 44, the minority charge carriers of charge packet Q B  begin to recombine with the charge on electrode 44, Q E2 . The recombination of minority charge carriers with the charge on electrodes 36 and 44 causes a reduction in charge thereupon equal to the quantity of minority charge carriers present in charge packets Q A  and Q B . The reduced charge on electrode 36, Q E1  &#39;, is given by the following equation: 
     
         Q.sub.E1 &#39;=Q.sub.E1 -Q.sub.A                               (4) 
    
     and the reduced charge on electrode 44, Q E2  &#39; is given by the following equation: 
     
         Q.sub.E2 &#39;=Q.sub.E2 -Q.sub.B                               (5) 
    
     Hence, the reduction of charge on electrode 36 and 44 reduces the level of potential wells 128 and 130 (illustrated by arrows E and F in FIG. 3e) from the initial precharge level. The charge on electrode 36 reduces more than the charge on electrode 44 since Q A  was greater than Q B , thus Q E1  &#39; is less than Q E2  &#39;. 
     During the time period t 4  to t 5 , clock signals V A  and V B  go from &#34;high&#34; to &#34;low&#34; thus eliminating potential wells 116 and 118 below electrodes 12 and 24 (illustrated in FIG. 3f). Clock signal V X  also goes from &#34;high&#34; to &#34;low&#34; thus eliminating potential wells 136 and 138 below electrodes 16 and 28 (also illustrated in FIG. 3f). Electrode 36 has charge Q E1  &#39; on it with a proportional potential well beneath it as does electrode 44 with charge Q E2  &#39; thereupon. 
     During time period t 5  to t 6 , in FIG. 2, clock signal V FS , which has been held &#34;high&#34; throughout the time period t 0  to t 5 , goes &#34;low&#34;. Clock signal V FS  is applied to diffusion 144 (a reservoir of charge) which is located in substrate 10 adjacent potential well 128. By holding V FS  &#34;high&#34;, charge carriers are attracted into diffusion 144. When V FS  goes &#34;low&#34; at t 5 , charge carriers flow from diffusion 144 into potential wells 128 and 130 (illustrated in FIG. 3g by arrow G). 
     During time period t 6  to t 7  in FIG. 2, clock signal V FS  returns &#34;high&#34; thereby making diffusion 144 attractive to charge carriers in potential wells 128 and 130. Charge carriers in potential wells 128 and 130 flow back into diffusion 144 (illustrated by arrow H in FIG. 3h). However, since potential well 128 was reduced more than potential well 130, a portion of the charge carriers are trapped in potential well 130 by a barrier created by potential well 128. The charge carriers trapped in potential well 130 form charge packet Q C . Charge packet Q C  represents the algebraic difference of Q A  -Q B . In addition, the amount of charge carriers trapped in potential well 130 is exactly the amount causing ψ S1  &#39;=ψ S2  &#39;. The following equations illustrate the above result: ##EQU4## 
     Also during the time period t 6  to t 7  clock signal V S  which was previously held &#34;low&#34;, goes &#34;high.&#34; Clock signal V S , applied to electrode 74, goes &#34;high&#34; thus causing output potential well 148 to be formed in substrate 10 beneath electrode 74 (illustrated by arrow I in FIG. 3h). 
     During time period t 7  to t 8 , clock signal V XO  which was previously held &#34;low&#34; goes &#34;high.&#34; Clock signal V XO , applied to electrode 70, going &#34;high&#34; causes output potential well 152 to be formed in substrate 10 beneath electrode 70. Electrode 70 is located between electrode 44 and 74. The formation of potential well 152 enables charge packet Q C  to flow from potential well 130 into potential well 148 (as shown in FIG. 3i). 
     At time period t 8 , clock signal V XO  returns to a &#34;low&#34; potential, thus eliminating potential well 152 beneath electrode 70. However, V S  remains &#34;high&#34; with charge packet Q C  held in potential well 148. Charge packet Q C  may then be shifted beneath other electrodes, by means known, for further processing. 
     Returning to equations (10) and (11), it can be seen that if the primary electrode areas A 1  =A 2  then Q C  =Q A  -Q B . However, if A 2  is greater than A 1  then the value of the resultant charge packet Q C  would reflect the amplification factor of A 2  /A 1  to Q A . Thus, the present invention may function as a charge packet replicator with with an amplification factor of A 2  /A 1  if charge packet Q B  equals zero, i.e., no charge packet. Furthermore, if potential well 148 is not emptied after successive cycles of charge packet subtraction, an output charge packet from potential well 148 would represent the sum of succesive charge packet subtractions, i.e.: ##EQU5## where x=number of successive cycles. 
     The previous operational description was based on the fact that charge packet Q A  was greater than charge packet Q B . If charge packet Q B  were greater than charge packet Q A , there would be no resultant output charge packet, i.e., Q C  =0. The operation of the present invention with charge packet Q B  subtracted from a smaller charge packet Q A , using the clocking signals of FIG. 2, is briefly explained. The difference in operation occurs during the period t 3  to t 4  where charge packets Q A  and Q B  minority carriers respectively recombine with the charge on electrode 36 or 44. Since charge packet Q B  is greater than charge packet Q A , the level of potential well 130 reduces more than the level of potential well 128. When diffusion 144 receives the &#34;low&#34; clock signal V FS , charge carriers flow into potential wells 128 and 130 as previously described. During the time period t 6  to t 7 , when diffusion 144 receives the &#34;high&#34; clock signal V FS , all charge carriers return to diffusion 144. Potential well 128 is not a barrier to trap charge carriers in potential well 130 since potential well 128 is reduced more than potential well 130. Thus no charge packet remains in potential wells 128 and 130 to represent the difference between charge packets Q A  and Q B . 
     The preferred embodiment of the present invention, comprising a novel charge coupled device differencer, has been disclosed. Various modifications to this embodiment will readily be apparent to those skilled in the art without exercise of the inventive faculty, and the generic principles defined herein may be applied to other embodiments. For example, it is apparent that the present invention could also be fabricated using a buried channel GaAs substrate. Thus, the present invention is not intended to be limited to the embodiment illustrated herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.