Abstract:
A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another.

Description:
BACKGROUND 
       [0001]    The control of multiple, accurately-spaced clock phases operating at one frequency is important to the design of many high-performance, high-speed chip-to-chip interconnect systems. While some interconnect systems use just two phases, e.g., the rising and falling edges of a single very high-speed clock, there are drawbacks to that approach, such as the difficulty of accurately controlling the duty-cycle of such a high-speed clock, as well as the necessity and difficulty of operating the high speed clock at a high frequency equal to ½ the data rate. The use of multiple clock signals with accurately spaced clock phases overcomes the disadvantages of a single clock approach. For example, because there are more clock phases, the frequency of these multi-phase clocks can be a fraction of the data rate, such as ½, ¼, ⅛, or 1/10. However, with multiple clock signals, problems can develop if the phase relationship among the various clock signals is not properly and accurately maintained. 
       SUMMARY 
       [0002]    The present invention is directed to a multi-phase correction circuit that can adjust the phase relationship among multiple clock signals having rising edges that are nominally spaced equidistant in time from one another, yet may have substantial errors in this spacing, such that these spacing errors are substantially reduced. In one embodiment, each of four input clock signals operating at the same frequency and nominally spaced equidistant in time from one another, yet with spacing errors, are buffered so as to generate output clock signals whose rising edges are equidistant in time from one another and have substantially reduced spacing errors. In particular, the circuit measures the relative time-position of the rising edges of each of the output clock signals and adjusts their time positions such that the rising edge of each successive clock signal trails the rising edge of the preceding clock signal by the same amount. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The foregoing summary and the following detailed description are better understood when read in conjunction with the appended drawings. For the purpose of illustrating the multi-phase correction circuit, there is shown in the drawings exemplary embodiments of various aspects of the circuit; however, the invention is not limited to the specific circuitry, methods and instrumentalities disclosed. In the drawings: 
           [0004]      FIG. 1  is a diagram illustrating the adjustment of the phases of a set of clock signals in accordance with an embodiment of the present invention; 
           [0005]      FIG. 2  is a circuit diagram illustrating one embodiment of a multi-phase correction circuit; 
           [0006]      FIG. 3  is a circuit diagram illustrating one embodiment of a multi-phase measurement circuit which is used in the multi-phase correction circuit; 
           [0007]      FIG. 4  is a circuit diagram illustrating one embodiment of a delay measurement subcircuit which is used in the multi-phase measurement circuit; 
           [0008]      FIG. 5  is a circuit diagram illustrating one embodiment of a delay circuit which is used in the multi-phase correction circuit; and 
           [0009]      FIG. 6  is a circuit diagram illustrating one embodiment of bias generators which are used in connection with the multi-phase correction circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0010]      FIG. 1  is a diagram illustrating the adjustment of the phases of a set of clock signals in accordance with an embodiment of the present invention. In the example shown, four input signals, IN 0 , IN 1 , IN 2  and IN 3 , each have substantially the same frequency. The respective rising edges  102 ,  104 ,  106  and  108  of these input signals are not, however, equally spaced. The multi-phase correction circuit of the present invention, one embodiment of which is illustrated in the following figures, generates output clock signals OUT 0 , OUT 1 , OUT 2 , and OUT 3  from input signals IN 0 , IN 1 , IN 2 , and IN 3  and having respective rising edges  112 ,  114 ,  116  and  118  that are substantially equidistant in time from one another. 
         [0011]    As one example, each of the four input clock signals IN 0 , IN 1 , IN 2  and IN 3  may switch at 2.7 GHz (period=370 ps). The multi-phase correction circuit of  FIG. 2  may buffer the input signals to generate the output clock signals OUT 0 , OUT 1 , OUT 2  and OUT 3 . A portion of the multi-phase correction circuit may measure a relative time-position of the rising edges of each of the output clock signals and, by means of negative feedback, adjust the relative time positions such that the rising edge of OUT 1  trails the rising edge of OUT 0  by 370/4=92.5 ps, the rising edge of OUT 2  trails the rising edge of OUT 1  by 370/4=92.5 ps, the rising edge of OUT 3  trails the rising edge of OUT 2  by 370/4=92.5 ps, and the next rising edge of OUT 0  trails the rising edge of CLK 3  by 370/4=92.5 ps. 
         [0012]      FIG. 2  is a circuit diagram illustrating one embodiment of the multi-phase correction circuit. In this embodiment, voltage-controlled delay circuits  220 ,  221 ,  222 , and  223  each accept two of four multi-phase input signals IN 0 , IN 1 , IN 2 , and IN 3  and generate multi-phase output signals OUT 0 , OUT 1 , OUT 2 , and OUT 3 . Signal delay through each delay circuit from IN and /IN to OUT is controlled by a respective one of four delay control bias voltages BIASP 0 , BIASP 1 , BIASP 2 , and BIASP 3 . A multi-phase measurement circuit  210  generates the delay control bias voltages in response to measured phase relationships between the output signals. The combined action of the delay circuits and the multi-phase measurement circuit forms four phase control loops having negative feedback, substantial open-loop gain, a loop frequency response compensated with capacitors C 0 , C 1 , C 2 , and C 3 , and results in substantially lower phase errors in the output signals, compared to those which may exist in the input signals. 
         [0013]      FIG. 3  illustrates further details of one embodiment  300  of the multi-phase measurement circuit  210  of  FIG. 2 . In this circuit, delay measurement subcircuit  301 , transistors M 2 , M 3 , and M 4 , and inverter  311  work together to draw a current from BIASP 0  which is inversely proportional to the time between a rising edge of OUT 3  and a rising edge of OUT 0 . Similarly, delay measurement subcircuit  302 , transistors M 6 , M 7 , and M 8 , and inverter  312  work together to draw a current from BIASP 0  which is inversely proportional to the time between a rising edge of OUT 0  and a rising edge of OUT 1 , delay measurement subcircuit  303 , transistors M 10 , M 11 , and M 12 , and inverter  313  work together to draw a current from BIASP 0  which is inversely proportional to the time between a rising edge of OUT 1  and a rising edge of OUT 2 , and delay measurement subcircuit  304 , transistors M 14 , M 15 , and M 16 , and inverter  314  work together to draw a current from BIASP 0  which is inversely proportional to the time between a rising edge of OUT 2  and a rising edge of OUT 3 . 
         [0014]    To cause an average voltage of BIASP 0 , BIASP 1 , BIASP 2 , and BIASP 3  to be substantially equal to a common mode reference voltage CMREF, transistors M 1 , M 5 , M 9 , and M 13  each source a substantially equal current onto BIASP 0 , BIASP 1 , BIASP 2 , and BIASP 3 , respectively, whereas a magnitude of the equal current is set by a common-mode feedback voltage CMFB. The CMFB voltage is set by combined action of delay measurement subcircuits  301 ,  302 ,  303 , and  304 . 
         [0015]    When the multi-phase measurement circuit  300  is coupled to four delay circuits as illustrated in  FIG. 2 , four control loops result, each of which has negative feedback and substantial open-loop gain. Appropriately sized loop filter capacitors C 0 , C 1 , C 2 , and C 3  of the phase correction circuit in  FIG. 2  integrate current from four instances of transistor M 31  of  FIG. 4  (see below) and transistors M 1 , M 5 , M 9 , and M 13  of  FIG. 3  (see below) that are coupled to BIASP 0 , BIASP 1 , BIASP 2 , and BIASP 3 , respectively, and also provide for control loop stability. In one embodiment, each loop filter capacitor comprises a p-type field effect transistor (PFET) having a gate coupled to the respective BIASPn node [n=0,1,2,3] and a source and drain coupled to a first power supply terminal VDD. 
         [0016]      FIG. 4  is a circuit diagram illustrating one embodiment  400  of the delay measurement subcircuit, four instances of which are used in the multi-phase measurement circuit of  FIG. 3  at  301 ,  302 ,  303 , and  304 . Common-gate transistors M 30  and M 31  are configured to operate as switched current sources which conduct when input IN is shorted to a second power supply terminal VSS by transistors in the multi-phase measurement circuit. Transistors M 32 , M 33 , M 34 , M 35 , and M 36  work together to generate a voltage on common-mode feedback control node CMFB such that the average voltage of BIASP 0 , BIASP 1 , BIASP 2 , and BIASP 3  of the phase measurement circuit is substantially equal to the voltage of CMREF. In a preferred embodiment, all transistors of  FIG. 4  but M 37  have a width and length substantially larger than the minimum allowed by the technology so as to provide for good matching. By asserting RESET high, transistor M 37 , having a gate coupled to RESET, a source coupled to power supply terminal VSS and a drain coupled to BIASP, provides a means to exit an invalid yet potentially stable control loop state in which the voltage at BIASP is substantially equal to power supply voltage VDD. 
         [0017]      FIG. 5  is a circuit diagram illustrating one embodiment  500  of the voltage-controlled delay circuit, four instances of which are placed in  FIG. 2  at  220 ,  221 ,  222  and  223 . The delay circuit operates as a buffer having complementary signal inputs IN and /IN, a single-ended signal output OUT, a controllable insertion delay defined as a delay from a transition on the complementary inputs to a transition on the output, a third input BIASP to control the insertion delay, and a static fourth input CMREF to set the maximum insertion delay. PFET transistors M 41  and M 43  each control a current conducted to PFET switches M 42  and M 44 , respectively, and the sum of these currents is mirrored to /OUT as a pull-down current by n-type field effect transistors (NFETs) M 49  and M 50 . Similarly, PFET transistors M 45  and M 47  each control a current conducted to PFET switches M 46  and M 48 , respectively, and the sum of these currents form a pull-up current on /OUT. Through adjustment of the voltage of BIASP, the pull-up and pull-down currents are adjusted proportionately, thereby also adjusting the rise and fall time of /OUT, and ultimately, the insertion delay. Static input CMREF and PFETS M 43 , M 44 , M 47 , and M 48  are optional, and when used, set a maximum insertion delay and a maximum phase control open loop gain so as to assist in the stability of the phase control loops of the phase correction circuit. 
         [0018]      FIG. 6  is a circuit diagram illustrating one embodiment of the bias generators used to generate a voltage at BIASN and a voltage at CMREF in  FIG. 2 . Each generator comprises a diode-connected transistor and a resistor. Those skilled in the art will recognize the operation of these circuits, and will further recognize the appropriate choice of resistor value and transistor size. In a preferred embodiment, and to provide for good transistor matching and bandwidth, a resistance value of R 1  and a transistor size of M 1  are chosen so as to provide for a substantial gate bias above threshold of transistors M 30  and M 31  of  FIG. 4 . Further, in the preferred embodiment, and to provide for good transistor matching, a resistance value of R 2  and a transistor size of M 2  are chosen so as to provide for a substantial gate bias above threshold of transistors M 1 , M 5 , M 9 , and M 13  of  FIG. 3 , and of transistors M 33 , M 34 , M 35 , and M 36  of  FIG. 4 . Finally, in the preferred embodiment, a resistance value of R 2  and a transistor size of M 2  are chosen so as to provide for a voltage at CMREF being neither too close to power supply voltage VSS nor too close to power supply voltage VDD, thereby providing for an appropriate control voltage range at BIASPn [n=0,1,2,3] and an appropriate range of insertion delay control for delay circuits  220 ,  221 ,  222 , and  223  of  FIG. 2 . 
         [0019]    While circuitry has been described and illustrated with reference to specific embodiments, those skilled in the art will recognize that modification and variations may be made without departing from the principles described above and set forth in the following claims. For example, although in the embodiments described above, four clock signals are processed, the circuitry disclosed above may be scaled to process any even number of fewer or more clock signals. For example, the circuitry may be scaled to process as few as two clock signals or may be scaled to process any even number of clock signals more than four. Accordingly, reference should be made to the following claims as describing the scope of the present invention.