Abstract:
According to the present invention, there is provided a semiconductor storage device having a memory cell, comprising: a buried electrode formed on a semiconductor substrate; a semiconductor layer formed on said buried electrode via a buried insulating film; a surface electrode formed on said semiconductor layer via an insulating film; a source region and drain region formed in the semiconductor layer on both sides of said surface electrode with a predetermined spacing therebetween; and a floating body formed between said source region and drain region, and which stores data in accordance with whether holes are stored in said floating body, wherein said buried electrode serves as a gate electrode, and said surface electrode serves as a plate electrode.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2004-356868, filed on Dec. 9, 2004, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a semiconductor storage device.  
         [0003]     Recently, an FBC (Floating Body Cell) memory is developed as a semiconductor memory which replaces a DRAM. In this FBC memory, a transistor is formed on an SOI (Silicon On Insulator) substrate. Data “1” is stored by storing holes in a floating body of the formed transistor, and data “0” is stored by discharging holes from the floating body.  
         [0004]     More specifically, to write data “1” in the FBC, the electric potential of the gate electrode is set at, e.g., 1.5 V and the electric potential of the drain region is set at 1.5 V to cause the FBC to perform a so-called pentode operation, thereby storing holes generated by impact ionization into the floating body.  
         [0005]     To write data “0” in the FBC, the electric potential of the gate electrode is set at, e.g., 1.5 V and the electric potential of the drain region is set at −1.5 V to bias the p-n junction between the floating body and drain region in the forward direction, thereby discharging holes stored in the floating body onto a bit line.  
         [0006]     Accordingly, when data “1” is written in the FBC and holes are stored in the floating body, the electric potential of the floating body is high, so the gate threshold voltage is low. On the other hand, when data “0” is written in the FBC and no holes are stored in the floating body, the electric potential of the floating body is low, so the gate threshold voltage is high.  
         [0007]     To read out data from the FBC, therefore, the electric potential of the gate electrode is set at, e.g., 1.5 V and the electric potential of the drain region is set at 0.2 V to cause the FBC to perform a so-called triode operation, so as not to destroy the data.  
         [0008]     If data “1” is written in the FBC and holes are stored in the floating body, the gate threshold voltage is low, so the drain current (cell current) is large. On the other hand, if data “0” is written in the FBC and no holes are stored in the floating body, the gate threshold voltage is high, so the drain current (cell current) is small.  
         [0009]     Accordingly, whether data “1” or “0” is written in the FBC as data to be read out from it is determined by checking whether the cell current is large or small on the basis of the gate threshold voltage difference.  
         [0010]     If the gate threshold voltage difference is increased, the cell current difference also increases, so data to be read out from the FBC can be accurately determined. As a method of increasing the gate threshold voltage difference, the capacity of the floating body can be increased.  
         [0011]     That is, when the capacity of the floating body is increased, it is possible to decrease the reduction with time of holes stored in the floating body. This suppresses the decrease in gate threshold voltage difference with time. Consequently, the gate threshold voltage difference becomes larger than that when the capacity of the floating body is small.  
         [0012]     The capacity of the floating body is inversely proportional to the film thickness of a buried insulating film, and proportional to the contact area between the floating body and buried insulating film. As a method of increasing the capacity of the floating body, therefore, it is possible to decrease the film thickness of the buried insulating film, or increase the contact area between the floating body and buried insulating film.  
         [0013]     In the method of decreasing the film thickness of the buried insulating film, however, if the buried insulating film is evenly thinned over the entire surface of the SOI substrate, a logic gate transistor to be formed in a region except for a prospective FBC region becomes difficult to design. In addition, if the film thickness of the buried insulating film in the prospective FBC region is changed from that in the other region, the fabrication process is complicated.  
         [0014]     Furthermore, in the method of increasing the contact area between the floating body and buried insulating film, increasing the size of the FBC makes high integration difficult. In addition, if a plate electrode is also formed on the side surfaces of the floating body via the buried insulating film, the process is complicated, and the yield decreases.  
         [0015]     A reference pertaining to the FBC memory is as follows.  
         [0016]     Japanese Patent Laid-Open No. 2004-111643.  
       SUMMARY OF THE INVENTION  
       [0017]     According to one aspect of the invention, there is provided a semiconductor storage device having a memory cell, comprising:  
         [0018]     a buried electrode formed on a semiconductor substrate;  
         [0019]     a semiconductor layer formed on said buried electrode via a buried insulating film;  
         [0020]     a surface electrode formed on said semiconductor layer via an insulating film;  
         [0021]     a source region and drain region formed in the semiconductor layer on both sides of said surface electrode with a predetermined spacing therebetween; and  
         [0022]     a floating body formed between said source region and drain region, and which stores data in accordance with whether holes are stored in said floating body, wherein said buried electrode serves as a gate electrode, and said surface electrode serves as a plate electrode. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIG. 1  is a longitudinal sectional view showing the sectional structure of an FBC according to an embodiment of the present invention;  
         [0024]      FIG. 2  is a block diagram showing the arrangement of an FBC memory according to the embodiment; and  
         [0025]      FIG. 3  is a longitudinal sectional view showing the sectional structure of an FBC according to another embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Embodiments of the present invention will be described below with reference to the accompanying drawings.  
         [0027]      FIG. 1  shows the arrangement of an FBC  10  as a memory cell used in an FBC memory according to an embodiment of the present invention. A buried electrode  30  is formed on a semiconductor substrate  20 , and a semiconductor layer  45  is formed on the buried electrode  30  via a buried insulating film  40 . A surface electrode  70  is formed on the semiconductor layer  45  via an insulating film  60 .  
         [0028]     A source region  80  and drain region  90  are formed in the two end portions of the semiconductor layer  45 . A floating body  50  which is in an electrically floating state is formed between the source region  80  and drain region  90 . Also, contact plugs  100  and  110  are formed on the source region  80  and drain region  90 , respectively.  
         [0029]     In this embodiment, the buried electrode  30  equivalent to the conventional plate electrode serves as a gate electrode, and the surface electrode  70  equivalent to the conventional gate electrode serves as a plate electrode. Therefore, the capacity of the floating body  50  is inversely proportional to the film thickness of the insulating film  60  equivalent to the conventional gate insulating film, rather than the film thickness of the buried insulating film  40 .  
         [0030]     Accordingly, if the film thickness of the insulating film  60  is decreased to, e.g., 40 to 45 Å, the capacity of the floating body  50  can be increased without decreasing the film thickness of the buried insulating film  40 . This makes it possible to increase the gate threshold voltage difference, and accurately determine data to be read out from the FBC  10 .  
         [0031]     Also, in this embodiment, after the electric potentials of the surface electrode  70  which serves as a plate electrode and the buried electrode  30  which serves as a gate electrode are respectively fixed at predetermined electric potentials, the electric potentials of the source region  80  and drain region  90  are respectively changed to desired electric potentials. That is, in this embodiment, data read and write operations are executed by changing the electric potential difference between the source region  80  and buried electrode  30  and the electric potential difference between the source region  80  and drain region  90 .  
         [0032]     More specifically, the power supply voltage is set at, e.g., 3 V, the electric potential of the surface electrode  70  which serves as a plate electrode is fixed to 1.5 V, and the electric potential of the buried electrode  30  which serves as a gate electrode is fixed to 0 V. To write data “1” in the FBC  10 , the electric potential of the source region  80  is set at, e.g., 0.75 V and the electric potential of the drain region  90  is set at 3V to supply an electric current to the channel region, thereby storing holes in the floating body  50 , and raising the electric potential of the floating body  50  to about 1.5 V.  
         [0033]     On the other hand, to write data “0” in the FBC  10 , the electric potentials of both the source region  80  and drain region  90  are set at, e.g., 3 V to neutralize the floating body  50 , thereby extinguishing holes stored in the floating body  50 , and lowering the electric potential of the floating body  50  to about −0.5 V.  
         [0034]     Accordingly, when data “1” is written in the FBC  10  and holes are stored in the floating body  50 , the electric potential of the floating body  50  is high, so the gate threshold voltage is low. On the other hand, when data “0” is written in the FBC  10  and no holes are stored in the floating body  50 , the electric potential of the floating body  50  is low, so the gate threshold voltage is high.  
         [0035]     Note that to hold data written in the FBC  10 , the electric potentials of both the source region  80  and drain region  90  are set at 1.5 V.  
         [0036]     To read out data from the FBC  10 , the electric potential of the source region  80  is set at, e.g., 1.5 V and the electric potential of the drain region  90  is set at 0.75 V or 0 V to suppress the generation of hot carriers, and cause the FBC  10  to perform a so-called pentode operation, so as not to destroy the data.  
         [0037]     If data “1” is written in the FBC  10  and holes are stored in the floating body  50 , the gate threshold voltage is low, so the drain current (cell current) is large. On the other hand, if data “0” is written in the FBC  10  and no holes are stored in the floating body  50 , the gate threshold voltage is high, so the drain current (cell current) is small.  
         [0038]     Accordingly, whether data “1” or “0” is written in the FBC  10  as data to be read out from it is determined by checking whether the cell current is large or small on the basis of the gate threshold voltage difference.  
         [0039]     In this embodiment, the gate threshold voltage difference is increased by increasing the capacity of the floating body  50 , so the cell current difference is large. This allows accurate determination of data to be read out from the FBC  10 .  
         [0040]     Also, to read or write data in this embodiment, the electric potential of the surface electrode  70  which serves as a plate electrode and the electric potential of the buried electrode  30  which serves as a gate electrode are respectively fixed to predetermined electric potentials. After that, the electric potential of the source region  80  is changed by 2.25 V within the range of 0.75 to 3 V, and the electric potential of the drain region  90  is changed by 2.25 V within the range of 0.75 to 3 V.  
         [0041]     By contrast, in the conventional device, after the electric potentials of the buried electrode which serves as a plate electrode and the source region are fixed, the electric potential of the surface electrode which serves as a gate electrode is changed by 3 V within the range of −1.5 to 1.5 V, and the electric potential of the drain region is changed by 3 V within the range of −1.5 to 1.5 V.  
         [0042]     As described above, the voltage width oscillated by a peripheral circuit for oscillating the voltage in this embodiment is smaller than that in the conventional device. This makes it possible to improve the reliability of the peripheral circuit, and reduce the power consumption.  
         [0043]      FIG. 2  shows the arrangement of an FBC memory  200  to which the FBC  10  is applied as a memory cell. A memory cell array  210  of the FBC memory  200  is formed by arranging the FBCs  10  in a matrix.  
         [0044]     The surface electrodes  70  of the FBCs  10  are connected to word lines WL running along the row direction. The source electrodes  80  are connected to source lines SL running alternately with the word lines WL in the row direction. The drain regions  90  of the FBCs  10  are connected to bit lines BL running along the column direction.  
         [0045]     A fixed potential supply circuit  220  is connected to the word lines WL, and fixes the electric potential of the surface electrode  70 , which serves as a plate electrode of the FBC  10 , to 1.5 V. A fixed potential supply circuit  230  is connected to the buried electrode  30  which serves as a gate electrode of the FBC  10 , and fixes the electric potential of the buried electrode  30  to 0 V.  
         [0046]     A row decoder  240  selects a desired source line SL on the basis of an externally supplied row address. A source line driver  250  sets the electric potential of the selected source line SL at 0.75, 3, and 1.5 V when data “1” is to be written, data “0” is to be written, and data is to be read out, respectively.  
         [0047]     A column decoder  260  selects a desired bit line BL on the basis of an externally supplied column address. A sense amplifier  270  sets the electric potential of the selected bit line BL at 3 and 0 V when data is to be written and data is to be read out, respectively, thereby reading out data from or writing data in the selected FBC  10 .  
         [0048]     The semiconductor storage device of the above embodiment makes it possible to accurately determine data to be read out from a memory cell, and reduce the power consumption.  
         [0049]     Note that the above embodiment is merely an example, and does not limit the present invention. For example, as shown in  FIG. 3 , to increase the capacity of a floating body  310 , it is also possible to form a source region  320  and drain region  330  having a shape which increases the contact area between the floating body  310  and an insulating film  60 .  
         [0050]     In this case, when the acceleration energy as one ion implantation condition is raised to, e.g., 15 keV, an impurity such as phosphorus (P) can be deeply ion-implanted to the vicinity of the surface of a buried insulating film  40 . This makes it possible to form the source region  320  and drain region  330  having a shape which increases the contact area between the floating body  310  and insulating film  60 . Note that the same reference numerals as in  FIG. 1  denote the same elements in  FIG. 3 , and an explanation thereof will be omitted.