Abstract:
A flicker-reduced liquid crystal display panel diminishing resistance-capacitance phenomena includes a plurality of parallel scanning lines and a plurality of parallel data lines, all lines intersecting with each other at the crosses. The liquid crystal display panel further includes a pulse control circuit and a gate driver. The pulse control circuit receives a pulse signal and reduces the time of the pulse signal under control of a control signal, the control signal controlling the start and finish of the time reduction. A reduced pulse signal is output. The gate driver receives the pulse signal which is output and issues scanning signals to the plurality of scanning lines.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to Chinese Patent Application No. 201510538200.7 filed on Aug. 28, 2015 in the China Intellectual Property Office, the contents of which are incorporated by reference herein. 
       FIELD 
       [0002]    The subject matter herein generally relates to a liquid crystal displays. 
       BACKGROUND 
       [0003]    A liquid crystal display panel can include a gate driver and a plurality of thin film transistors. The gate driver outputs gate driving signals to control the plurality of thin film transistors via a plurality of scanning lines. However, a parasitic capacitance and resistance (RC) of the scanning lines may cause an RC delay. The RC delay makes for picture flicker. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]    Implementations of the present technology will now be described, by way of example only, with reference to the attached figures, wherein: 
           [0005]      FIG. 1  is a block diagram of a liquid crystal display panel including a gate pulse control circuit according to a first embodiment of the present disclosure. 
           [0006]      FIG. 2  is a circuit diagram of the gate pulse control circuit of the liquid crystal display panel of  FIG. 1 . 
           [0007]      FIG. 3  is a waveform diagram of the gate pulse control circuit of  FIG. 2 . 
           [0008]      FIG. 4  is a block diagram of the liquid crystal display panel including a gate pulse control circuit according to a second embodiment of the present disclosure. 
           [0009]      FIG. 5  is a circuit diagram of the gate pulse control circuit of the liquid crystal display panel of  FIG. 4 . 
           [0010]      FIG. 6  is a waveform diagram of the gate pulse control circuit of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiment described herein can be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the embodiments described herein. 
         [0012]    Several definitions that apply throughout this disclosure will now be presented. 
         [0013]    The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. 
         [0014]      FIG. 1  illustrates a liquid crystal display panel  10  of a first embodiment. The liquid crystal display panel  10  can include a thin film transistor array  110 , a gate driver  112 , a data driver  114 , and a time controller  116 . The liquid crystal display panel  10  can further include a plurality of scanning lines S 1 -Sn and a plurality of data lines D 1 -Dm. The scanning lines S 1 -Sn are parallel to each other. The data lines D 1 -Dm are parallel to each other, and each one intersects with the scanning lines S 1 -Sn. The data lines D 1 -Dm and the scanning lines S 1 -Sn define multiple intersections where the data lines D 1 -Dm cross the scanning lines S 1 -Sn. Each thin film transistor of the thin film transistor array  110  is arranged at one intersection of the data lines D 1 -Dm and the scanning lines S 1 -Sn. In the illustrated embodiment, the liquid crystal display panel  10  can be an In-Plane Switching panel or Fringe Field Switching panel. 
         [0015]      FIGS. 2-3  illustrate the pulse control circuit  116  receiving a pulse signal CKV and chamfering the pulse signal CKV, based on a control signal CKVB, to output a pulse signal OCKV. The control signal CKVB controls a time period of diminution of the pulse signal CKV. The gate driver  112  receives the pulse signal OCKV and outputs a plurality of scanning signals to the plurality of scanning lines S 1 -Sn. 
         [0016]    The pulse control circuit  116  can include a first transistor T 1 . The first transistor T 1  can include a control terminal T 1   g , a first conductive terminal T 11 , and a second conductive terminal T 12 . The control terminal T 1   g  receives the control signal CKVB. The first conductive terminal T 11  receives a chamfering signal VEE 1 . The second conductive terminal T 12  receives the pulse signal CKV and outputs the pulse signal OCKV. In the illustrated embodiment, the pulse signal CKV may be square wave or half square wave and have a first high level magnitude and a first low level magnitude. The voltage of the first high level magnitude is 18V, and the voltage of the first low level magnitude is −8V. The chamfering signal VEE 1  pulls down the pulse signal CKV and outputs a diminished or time-reduced signal. 
         [0017]    During a first time period TP 1 , the control signal CKVB is logic-low, which causes the first transistor T 1  to be turned off. A waveform of the pulse output signal OCKV is same as that of a waveform of the pulse signal CKV. During a second time period TP 2 , the control signal CKVB is logic-high, which causes the first transistor T 1  to be turned on. The chamfering signal VEE 1  pulls down the pulse signal CKV to form the pulse signal OCKV. In the illustrated embodiment, a duration of the first time period TP 1  is greater than a duration of the second time period TP 2 . The control signal CKV is logic-high throughout the first and second time periods TP 1  and TP 2 . In the illustrated embodiment, when the control signal CKVB converts to logic-low from logic-high, the pulse signal CKV converts simultaneously to logic-low from logic-high. Therefore, picture flicker of the liquid crystal display panel is reduced. 
         [0018]      FIG. 4  illustrates a liquid crystal display panel  20  of a second embodiment. The liquid crystal display panel  20  can include a thin film transistor array  210 , a gate driver  212 , a data driver  214 , and a time controller  216 . The liquid crystal display panel  20  can further include a plurality of scanning lines S 1 -Sn and a plurality of data lines D 1 -Dm. The scanning lines S 1 -Sn are parallel to each other. The data lines D 1 -Dm are parallel to each other, and each one intersects with the scanning lines S 1 -Sn. The data lines D 1 -Dm and the scanning lines S 1 -Sn define multiple intersections where the data lines D 1 -Dm cross the scanning lines S 1 -Sn. A thin film transistor of the thin film transistor array  210  is arranged at each intersection of the data lines D 1 -Dm and the scanning lines S 1 -Sn. In the illustrated embodiment, the liquid crystal display panel  20  can be an In-Plane Switching panel or Fringe Field Switching panel. 
         [0019]      FIGS. 5-6  illustrate the pulse control circuit  216  receiving a pulse signal CKV and chamfering the pulse signal CKV under control of a control signal CKVB, to output a pulse signal OCKV. The control signal CKVB controls a time period of diminution of the pulse signal CKV. The gate driver  212  receives the pulse signal OCKV and outputs a plurality of scanning signals to the plurality of scanning lines S 1 -Sn. 
         [0020]    The pulse control circuit  216  can include a second transistor T 2  and a third transistor T 3 . The second transistor T 2  can include a control terminal T 2   g , a first conductive terminal T 21 , and a second conductive terminal T 22 . The third transistor T 3  can include a control terminal T 3   g , a first conductive terminal T 31 , and a second conductive terminal T 32 . The control terminal T 2   g  of the second transistor T 2  receives the control signal CKVB. The first conductive terminal T 21  of the second transistor T 2  receives a diminution signal VEE. The second conductive terminal T 22  is electrically coupled to the first conductive terminal T 31  of the third transistor T 3 . The second conductive terminal T 32  of the third transistor T 3  receives pulse signal CKV. The control terminal T 3   g  of the third transistor T 3  receives a second control signal VDD. A node between the second conductive terminal T 22  of the second transistor T 2  and the first conductive terminal T 31  of the third transistor T 3  outputs the pulse signal OCKV. In the illustrated embodiment, the pulse signal CKV may be full or half square wave and have a first high level logic and a first low level logic. The voltage of the first high level is 18V, and the voltage of the first low level is −8V. The diminution signal VEE is −10V and pulls down the pulse signal CKV. 
         [0021]    During a first time period P 1 , the control signal CKVB is at logic-low, which causes the second transistor T 2  to be turned off. The second control signal VDD is at logic-high, which causes the third transistor T 3  to be turned on. A waveform of the pulse signal OCKV is same as that of a waveform of the pulse signal CKV. During a second time period P 1 , the control signal CKVB is at logic-high, which causes the second transistor T 2  to be turned on. The second control signal VDD is at logic-high, which causes the third transistor T 3  to be turned on. The chamfering signal VEE pulls down the pulse signal CKV to form the pulse signal OCKV. Therefore, picture flicker of the liquid crystal display panel is reduced. 
         [0022]    It is to be understood that even though numerous characteristics and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only; and changes may be in detail, especially in the matter of arrangement of parts within the principles of the embodiments, to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.