Abstract:
An isolated step-up converter having first and second stages is described herein. The second stage can provide either DC or AC output based on the various topologies described. Resonance inductors and capacitors are used and tuned to a commutation frequency in some embodiments. Capacitors and inductors are also used in the first stage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. provisional application No. 62/326,893, filed Apr. 25, 2016, the contents of which are hereby incorporated by reference. 
    
    
     FIELD 
     The present invention relates generally to voltage converter systems and specifically to systems adapted to convert low direct-current (DC) input voltages to high DC or AC output voltages. 
     BACKGROUND &amp; SUMMARY 
     The biggest challenge in designing step-up DC-DC converters relates to the ratio between output voltage and input voltage. The complexity of a DC-DC converter is inversely proportional to Vin/Iin. There is an even bigger problem when power in the range of 2-4 kW and higher with input voltage in the range of 10-12 VDC are required. As depicted in  FIG. 15 , when the ratio between input voltage and input current (Vin/Iin) is above 1, the problem will be smaller. i.e. The higher the number, the smaller the problem. 
     When the ratio is below 1, the problem increases as the ratio drops. For example, 10 VDC and 1000 ADC is problematic. The requirement for DC-DC isolation conversion with power in the range of 20-30 kW for automotive application is not rare. A common requirement is 24 VDC to 400 VDC and 48 VDC to 400 VDC. In this case, engineers typically connect a number of power stages in parallel. This works somewhat, but it has a big disadvantage: there are too many active switches and transformers, which require complex control, higher costs, and reduced reliability. 
     One key advantage of the present invention is reduction in complexity of the power transformer. The voltage across the low voltage side of transformer is, on average, twice higher than the input voltage, so the current via the low voltage side of the transformer will have an average value of half of the input current. This results in a reduction in the turns ratio of the transformer and as a result the design and the construction of the transformer will be easier, the efficiency of the transformer will increase, and the cost will be reduced. Additional objects and advantages are achieved because the topology of the present invention does not require a big block capacitor and has a relatively small ripple current on low voltage side—because of input inductors. 
       FIG. 1  depicts one embodiment of the present invention.  FIGS. 1A &amp; 1B  depict a schematic diagram of a simplified/representative view of  FIG. 1 , used in some cases for ease of discussion. The regulation of output voltage is accomplished by changing the duty cycle of switches S 1  and S 3 . The switching of S 2  and S 4  is complementary to the switching of S 1  and S 3  (i.e. S 1  &amp; S 4  open when S 2  &amp; S 3  closed, and vice versa). 
     The power stage has 3 modes of operation: Duty cycle of 50% wherein “on” time of S 1  and S 3  is half of commutation frequency, duty cycle of less than 50% wherein “on” time is less than half of the commutation frequency, and duty cycle of greater than 50% wherein “on” time is more than half of the commutation frequency. The selection of a mode will be determined by how much gain is required. In other words, the ratio between input and output voltage. Capacitors C 1  and C 2  will charge to an average voltage following this formula. 
     In one preferred embodiment, capacitors C 1  and C 2  are big enough so that we can ignore the ripple voltage, inductors L 1  and L 2  are big enough so that we can ignore ripple current, and the resonant frequency of resonant circuit Lr and Cr is equal to the commutation frequency. 
       FIGS. 5A-6B  show operational characteristics for a 50% duty cycle. Starting at time t 0 , Capacitors C 1  and C 2  are charged with a polarity as shown in  FIG. 5B . At time t 0  S 1  is turned-on and current from source V 1  flows via inductor L 1  and S 1 . At the same time (t 0 ) S 4  is turned-on and completes a circuit to discharge C 1  via the resonant circuit Lr and Cr through the load. The current in this circuit starts from zero, will be sinusoidal in waveform, and reaches zero at time t 1 . At the same time S 4  completes a circuit to charge C 2  through inductor L 2 , since S 3  is turned-off this time. The switch S 4  has to be bidirectional because current flows through it in both directions. The current via S 4  starts equal with the current in inductor L 2  and decays because the current from capacitor C 1  is in the opposite direction, and when current in capacitor C 1  reaches maximum the current via switch S 4  will have reversed direction. When the current in C 1  reaches zero (time t 1 ) the current via S 4  will be the same as at time t 0 . At time t 1  S 1  and S 4  are turned-off, S 3  and S 2  are turned-on, and new half cycle (t 1 -t 2 ) starts, similar to period t 041 , but the current flowing via resonant circuit will be in the opposite direction to that during the period t 041 . 
       FIGS. 7A-10B  show operational characteristics for an approximately 40% duty cycle. Starting at time t 0 , switch S 4  is ON. The current via S 1  begins with the same value as the current in L 1 , and discharges capacitor C 1  via resonant circuit. The current via S 4  at time t 0  is equal to the current via L 2  and will be reduced by the current from C 1  because it flows in the opposite direction to the current from L 2 . At time t 1  S 1  is turned-off, interrupting the current which will be the summary of the current in L 1  and the current flowing through C 1  and resonant circuit. Also at time t 1 , S 2  turns on and current flows via S 2  matching the current which was interrupted by S 1 . The current via resonant circuit at t 1  starts to decay and at time t 2  it will be zero. Between t 2  and t 3  currents flow via S 2  and S 4  and matching the currents via L 1  and L 2 . At time t 3 , S 3  turns on and S 4  turns off beginning a new conduction period (t 3 -t 4 ), similar to time period t 0 -t 3 . 
       FIGS. 11A-14B  show operational characteristics for an approximately 60% duty cycle. Starting at time t 0 , S 1  is staying “on” conducting current via inductor L 1 . Also at time t 0 , S 3  turns-off and S 4  turns-on. This commutation completes a circuit to discharge C 1  via resonant circuit. This current is starting from zero and rising sinusoidally. At time t 1  switch S 4  turns-off and S 3  turns-on. This commutation event provides a path for current to flow via resonant circuit to C 2  and S 3 . So, switch S 3  carries the summary of two currents, one from L 2  and another one from resonant circuit, but they are in opposite directions. The current via resonant circuit will linearly decay, and at time t 2  it reaches zero. In time period t 2 -t 3 , current will flow only via S 1  and S 3 , and will be equal to the currents in L 1  and L 2 , respectively. At time t 3 , switch S 1  turns-off and S 2  turns-on and a new period begins (t 3 -t 4 ), similar to period t 0 -t 3 . 
     Other configurations may be used with resonant capacitors. In one embodiment, capacitors C 1  and C 2  are the resonant Capacitors, Switches S 1  and S 3  turn-off purely ZVS (Zero Voltage Switched) under full load. When capacitors C 1  and C 2  are of small value, the resonant capacitance will be determined by the combination of capacitors C 1 , C 2  and the capacitor which is connected in series with resonant inductor Lr. In this case, the ripple voltage on capacitors C 1  and C 2  can be high under full load. 
     When capacitors C 1  and C 2  are the resonant capacitors, the ripple voltage on C 1  and C 2  can reach 100% under full load conditions and switches S 1  and S 4  will turn-off under purely ZVS. It should be noted that in practical implementation, switches S 1  and S 3  turn-on under ZCS (Zero Current Switched) conditions, because practically there will always be a small inductor which is connected in series with capacitors C 1  and C 2 . All this helps to significantly reduce switching losses. This topology has many varieties of behavior which depend on value of capacitors C 1  and C 2 . It should also be noted that RMS current via these capacitors is almost equal to RMS current via the primary transformer winding. The foregoing considerations necessitate that attention should be paid to the selection of value and type of these capacitors. 
       FIGS. 17A through 17C  depict 50%, 40%, 60% duty cycles, respectively, wherein Ch 1 =gate S 1 , Ch 2 =S 1 , Ch 3 =S 2 , &amp; Ch 4 =current via low voltage side of transformer; 80 A/div. The following table shows the measured results. 
     
       
         
               
             
               
               
               
               
               
             
           
               
                 TABLE 
               
             
             
               
                   
               
               
                 measured results (FIGS. 17A through 17C) 
               
             
          
           
               
                   
                 Vin 
                 Vout 
                 Pout W 
                 Eff 
               
               
                   
                   
               
               
                   
                   10.5 
                 170 
                 1600 
                 0.935 
               
               
                   
                 15 
                 170 
                 2100 
                 0.94  
               
               
                   
                 22 
                 380 
                 3100 
                 0.945 
               
               
                   
                 27 
                 380 
                 3100 
                 0.944 
               
               
                   
                 30 
                 380 
                 3100 
                 0.941 
               
               
                   
                 52 
                 380 
                 11000  
                 0.94  
               
               
                   
                 60 
                 380 
                 10000  
                 0.945 
               
               
                   
                 80 
                 380 
                 11000  
                 0.94  
               
               
                   
                   
               
             
          
         
       
     
       FIG. 2  depicts a DC-AC converter without a DC-link. The following table shows the practical results from this DC-AC converter. In this case the converter can operate as a bidirectional converter and operate as a charger. 
     
       
         
               
             
               
               
               
               
               
             
           
               
                 TABLE 
               
             
             
               
                   
               
               
                 (DC-AC converter of FIG. 2) 
               
             
          
           
               
                   
                 Vin 
                 Vout 
                 PoutW 
                 Eff 
               
               
                   
                   
               
               
                   
                 11 
                 120 
                 1000 
                 0.921 
               
               
                   
                 12 
                 120 
                 1200 
                 0.927 
               
               
                   
                 14 
                 120 
                 1200 
                 0.931 
               
               
                   
                   
               
             
          
         
       
     
     In this case, the converter can operate as a bidirectional converter. For step-up DC-DC isolation converters with input voltage below 100 VDC, it is reasonable to use paralleling when the input current is over 600-700 A. The cost of paralleling below this current will be at least twice as high as a single stage under the same conditions (Vin, Pout, efficiency, and commutation frequency). 
     The following tables show comparisons of real implementations of these topologies. The cost of the proposed topology is smaller than that of others and it has a wider application area. The proposed topology has better results as far as cost and application area by Vin, but it is limited by capacitors C 1  and C 2 . In other words, more attention should be paid to the selection of these parts. Power transformer characteristics are improved by reduction of turn ratio. Additionally, it is very reasonable to use this topology for DC-AC converter without DC-link, when input ripple current is not desired. The paralleling input power stages have minimum twice higher cost and are not competitive. In other words, the proposed topology is a better solution for higher power at low voltage than parallel input stages. 
     The technical aspects and cost characteristics of the proposed topology ( FIG. 1 ) is compared to the topologies depicted in  FIGS. 3 &amp; 4 . The comparison of cost per kW was made according to the following norms: Vin, Vout, Pout and efficiency are the same for each topology. The following table shows a comparison of the proposed topology of the present invention (“Prop”) vs N 1  ( FIG. 3 ), N 2  ( FIG. 4 ), &amp; DAB (Double Active Bridge). The latter having received a lot of attention. 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 
               
               
                   
               
               
                   
                   
                   
                   
                   
                   
                   
                   
                 Block 
                 Cost 
               
               
                   
                 Max 
                 Vin 
                 Vout 
                 Comm 
                 Limit by 
                 Sw 
                 Ind 
                 C 
                 1 kW 
               
               
                   
               
             
             
               
                 DAB 
                 150 A 
                 10-100 
                 0-1000 
                  50 kHz 
                 Turn-off 
                 8 
                 no 
                 Huge 
                 1.3-1.5 
               
               
                 N1 
                 200 A 
                 30-100 
                 0-1000 
                 100 kHz 
                 Turn-off 
                 4 
                 2 
                 no 
                 1.2-1.4 
               
               
                 N2 
                 600 A 
                 10-40 
                 Vmax/Vmin = 2 
                 300 kHz 
                 X-form 
                 6 
                 no 
                 1 
                 1.1-1.2 
               
               
                 Prop 
                 600 A 
                 10-100 
                 0-1000 
                 200 kHz 
                 C1 &amp; C2 
                 4 
                 2 
                 no 
                 1.0 
               
               
                   
               
             
          
         
       
     
     The following table shows comparisons of implementations of the aforementioned topologies. As can be seen, the cost of the proposed topology is lower than that of others and it has a wider application area. Also, it is very reasonable to use this topology for a DC-AC converter without a DC-link, when low input ripple current is desired. Finally, the proposed topology is a better solution for higher power at low voltage than parallel input stages. 
     
       
         
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 
               
               
                   
                   
               
               
                   
                   
                 Pout 
                 Vin 
                 Vout 
                 Comm 
                 Eff 
               
               
                   
                   
               
             
             
               
                   
                 DAB 
                 1.7 kW 
                 10-14 
                 360 
                  20 kHz 
                 92.0 
               
               
                   
                 DAB 
                 2.4 kW 
                 30 
                 750 
                  40 kHz 
                 94.5 
               
               
                   
                 N1 
                 1.0 kW 
                 20-50 
                 350 
                  50 kHz 
                 95.8 
               
               
                   
                 N1 
                 1.4 kW 
                 12 
                 300 
                  20 kHz 
                 92.0 
               
               
                   
                 N1 
                 1.6 kW 
                 12 
                 300 
                  20 kHz 
                 88.0 
               
               
                   
                 N2 
                 3.5 kW 
                 10.5-16   
                 360 
                 150 kHz 
                 93.5 
               
               
                   
                 N2 
                 7.5 kW 
                 20-30 
                 600 
                 120 kHz 
                 94.0 
               
               
                   
                 Prop 
                 1.7 kW 
                 10.5-15   
                 170 
                 120 kHz 
                 93.5 
               
               
                   
                 Prop 
                 3.1 kW 
                 22-30 
                 380 
                 120 kHz 
                 94.5 
               
               
                   
                 Prop 
                 7.0 kW 
                 42-72 
                 380 
                 100 kHz 
                 96.5 
               
               
                   
                   
               
             
          
         
       
     
     Table 
     Examples of component values for different resonance configurations for a sample converter with 12V input, 360V output at 2.8 kW: 
     
       
         
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
               
               
                   
                 Primary side 
                 Secondary side 
                 Combined  
               
               
                 Component 
                 resonance 
                 resonance 
                 Resonance 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 C1/C2 
                 10 
                 uF 
                 400 
                 uF 
                 24 
                 uF 
               
               
                 C3/C5 
                 10 
                 uF 
                 0.1 
                 uF 
                 0.1 
                 uF 
               
               
                 L3 
                 6.5 
                 uH 
                 6 
                 uH 
                 8.5 
                 uH 
               
               
                   
               
             
          
         
       
     
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Further features of the inventive embodiments will become apparent to those skilled in the art to which the embodiments relate from reading the specification and claims with reference to the accompanying drawings, in which: 
         FIG. 1  depicts a schematic diagram of one embodiment of the present invention; 
         FIG. 1A  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 2  depicts a schematic diagram of one embodiment of the present invention; 
         FIG. 3  depicts a schematic diagram of a prior art topology (Topology N 1 ); 
         FIG. 4  depicts a schematic diagram of a prior art topology (Topology N 2 ); 
         FIG. 6A  depicts a waveform diagram for time t 1  to t 2  (50% duty cycle); 
         FIG. 6B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 5A  depicts a waveform diagram for time t 0  to t 1  (50% duty cycle); 
         FIG. 5B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 7A  depicts a waveform diagram for time t 0  to t 1  (40% duty cycle); 
         FIG. 7B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 8A  depicts a waveform diagram for time t 1  to t 2  (40% duty cycle); 
         FIG. 8B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 9A  depicts a waveform diagram for time t 2  to t 3  (40% duty cycle); 
         FIG. 9B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 10A  depicts a waveform diagram for time t 3  to t 4  (40% duty cycle); 
         FIG. 10B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 11A  depicts a waveform diagram for time t 0  to t 1  (60% duty cycle); 
         FIG. 11B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 12A  depicts a waveform diagram for time t 1  to t 2  (60% duty cycle); 
         FIG. 12B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 13A  depicts a waveform diagram for time t 2  to t 3  (60% duty cycle); 
         FIG. 13B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 14A  depicts a waveform diagram for time t 3  to t 4  (60% duty cycle); 
         FIG. 14B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 15  depicts a graph showing the complexity of DC-DC converter is inversely proportional to Vin/Iin; 
         FIG. 1B  depicts a schematic diagram of a simplified/representative view of  FIG. 1 ; 
         FIG. 16A  depicts a waveform diagram for an alternative embodiment; 
         FIG. 16B  depicts a schematic diagram of a simplified/representative view of  FIG. 16A ; 
         FIG. 17A  depicts a waveform diagram (50% duty cycle); 
         FIG. 17B  depicts a waveform diagram (40% duty cycle); and 
         FIG. 17C  depicts a waveform diagram (60% duty cycle). 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  depicts one embodiment of the invention wherein a step-up converter  100  has first and second isolated stages,  101 ,  102 , the first isolated stage comprises, a DC power source V 1 ; a first inductor L 1  having a first terminal  103  connected to the DC power source and a second terminal  104  connected to a first terminal  105  of a first capacitor C 1 ; a second terminal  106  of the first capacitor C 1  connected to a first terminal  119  of a primary stage  131  of a transformer Tr; a second inductor L 2  having a first terminal  111  connected to the DC power source V 1  and a second terminal  112  connected to a first terminal  113  of a second capacitor C 2 ; a second terminal  114  of the second capacitor C 2  connected to a second terminal  120  of the primary stage  131  of the transformer Tr; a first switch S 1  having a first terminal  107  connected to the second terminal  104  of the first inductor L 1  and to the first terminal  105  of the first capacitor C 1 , the first switch S 1  having a second terminal  108  connected to ground; a second switch S 2  having a first terminal  109  connected to the second terminal  106  of the first capacitor C 1  and to the first terminal  119  of the primary stage  131  of the transformer Tr, the second switch S 2  having a second terminal  110  connected to ground; a third switch S 3  having a first terminal  115  connected to the second terminal  112  of the second inductor L 2  and to the first terminal  113  of the second capacitor C 2 , the third switch S 3  having a second terminal  116  connected to ground; and a fourth switch S 4  having a first terminal  117  connected to the second terminal  114  of the second capacitor C 2  and to the second terminal  120  of the primary stage  131  of the transformer Tr, the fourth switch S 4  having a second terminal  118  connected to ground. In one embodiment, step-up converter  100  comprises at least one of the first, second, third, or fourth switches, S 1 , S 2 , S 3 , S 4  respectively, being bidirectional. In one embodiment, step-up converter  100  comprises the fourth switch S 4  being bidirectional. 
       FIG. 1  depicts one embodiment of the invention wherein the second isolated stage  102  comprises a first diode  133  having a first terminal  122  connected to a first node  135 , and a second terminal  121  connected to a second node  136 ; a second diode  134  having a first terminal  138  connected to the second node  136 , and a second terminal  139  connected to a third node  137 ; a secondary transformer stage  132  having a first terminal  123  connected to the second node  136 , and a second terminal  124  connected to a first terminal  125  of a resonant inductor Lr; a second terminal  126  of the resonant inductor Lr connected to a second terminal  128  of a first resonant capacitor Cr 1 , and to a first terminal  129  of a second resonant capacitor Cr 2 ; a first terminal  127  of the first resonant capacitor Cr 1  connected to the first node  135 ; and a second terminal  130  of the second resonant capacitor Cr 2  connected to the third node  137 ; whereby a load RL can be connected between the first and third nodes  135 ,  137 . The second isolated stage  101  of  FIG. 1  provides a DC voltage. 
     In one embodiment, the second isolated stage  102  comprises, the resonant inductor Lr and first and second resonant capacitors Cr 1 , Cr 2 , having a resonant frequency equal to a commutation frequency.  FIG. 2  depicts one embodiment of the invention wherein the second isolated stage  200  comprises, a fifth switch S 5  having a first terminal  204  connected to a first node  205 , and a second terminal  203  connected a first terminal  202  of a sixth switch S 6 ; the second terminal  201  of the sixth switch S 6  connected to a second node  224 ; a seventh switch S 7  having a first terminal  219  connected to the second node  224 , and a second terminal  220  connected to a first terminal  221  of an eighth switch S 8 ; a second terminal  222  of the eighth switch S 8  connected to a third node  218 ; a secondary transformer stage  211  having a first terminal  210  connected to the second node  224 , and a second terminal  212  connected to a first terminal  213  of a resonant inductor  225 ; a second terminal  214  of the resonant inductor  225  connected to a second terminal  207  of a first resonant capacitor Cr 1 ′, and to a first terminal  216  of a second resonant capacitor Cr 2 ′; a first terminal  206  of the first resonant capacitor connected to the first node  205 ; a second terminal  217  of the second resonant capacitor connected to the third node  218 ; and a third capacitor  215  connected between the first and third nodes  205 ,  218 ; whereby a load RL can be connected between the first and third nodes  205 ,  218 . The second isolated stage  200  of  FIG. 2  has an AC output across the load whereas the second isolated stage  101  of  FIG. 1  provides a DC voltage. 
     While this invention has been shown and described with respect to detailed embodiments thereof, it will be understood by those skilled in the art that changes in form and detail thereof may be made without departing from the scope of the claims of the invention.