Abstract:
In one embodiment, semiconductor device  10  comprises a diode which uses isolation regions ( 34, 16 , and  13 ) and a plurality of dopant concentrations ( 30, 20, 24 , and  26 ) which may be used to limit the parasitic current that is injected into the semiconductor substrate ( 12 ). Various biases on the isolation regions ( 34, 16 , and  13 ) may be used to affect the behavior of semiconductor device ( 10 ). In addition, a conductive layer ( 28 ) may be formed overlying the junction between anode ( 42 ) and cathode ( 40 ). This conductive layer ( 28 ) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode ( 40 ).

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates generally to semiconductors, and more particularly to a semiconductor device and method of forming the same.  
       RELATED ART  
       [0002]     For integrated circuits, it is often important to limit the current which is injected by a semiconductor device into its semiconductor substrate. This is particularly important for power integrated circuits which operate at higher voltages and currents. Also, it is desirable to increase the maximum voltage that may be used with a power integrated circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0003]     The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:  
         [0004]      FIG. 1  illustrates, in cross-sectional view, a semiconductor device in accordance with one embodiment of the present invention; and  
         [0005]      FIG. 2  illustrates, in graphical form, a current versus voltage (cathode to anode voltage) graph illustrating cathode current and substrate current produced by the semiconductor device of  FIG. 1 . 
     
    
       [0006]     Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.  
       DETAILED DESCRIPTION  
       [0007]     The rapid evolution of SMARTMOS technologies to integrate power devices along with analog and CMOS (complementary metal oxide semiconductor) on the same chip has created the opportunity for systems-on-a-chip solutions. Power management in automotive, portable, and computer peripheral applications drive the need for a versatile smart power technology capable of operating from lower battery voltages all the way up to high voltages in the tens of volts. However, some conventional semiconductor devices, such as diodes, may suffer from the problem of parasitic substrate injection in certain situations. Integration of a high voltage isolated diode device into a smart power technology for the purpose of suppressing substrate injection requires a new structure and method of forming.  
         [0008]      FIG. 1  illustrates, in cross-sectional view, a semiconductor device in accordance with one embodiment of the present invention. As used in  FIG. 1 , “P−, P, P+, and P++” will represent semiconductor material having P-type conductivity, wherein the dopant concentrations vary from lowest dopant concentrations for P−, higher dopant concentration for P, even higher dopant concentration for P+, and the highest dopant concentration for P++. Similarly, “N, N+, and N++” will represent semiconductor material having N-type conductivity, wherein the dopant concentrations vary from lowest dopant concentrations for N, higher dopant concentration for N+, and the highest dopant concentration for N++.  
         [0009]     In the embodiment of the present invention illustrated in  FIG. 1 , the semiconductor device  10  is a diode, where the anode  42  is formed from P++ region  30 , P+ region  20 , P− region  24 , and P region  26 , and the cathode  40  is formed from N++ region  32  and N region  22 . P region  12  is a semiconductor substrate and N+ region  13  may be a buried layer, or alternately may be an N+ layer formed in any manner. N+ region  16  may be implemented as a conductive sinker. N+ region  16 , in combination with N+ layer  13 , forms a conductive isolation tub or conductive isolation feature which may be used to conductively isolate diode  10  from the rest of the integrated circuit. Dielectric layer  14  may be used to surround diode  10 . Dielectric layer  14  forms an electrical isolation barrier which may be used to electrically isolate diode  10  from the rest of the integrated circuit. Note that dielectric layer  14  may be formed of any dielectric material. Oxide is just one possible dielectric material that may be used. Any other appropriate material may be used, such as, for example, oxide and polysilicon combinations.  
         [0010]     Anode  42  includes P++ region  30 , cathode  40  includes N++ region  32 , and isolation region  16  includes N++ region  34 . These regions  30 ,  32 , and  34  are all heavily doped in order to allow for good ohmic contact, and thus may be called ohmic regions herein. In some embodiments of the present invention, metal contacts (not shown) may be formed overlying regions  30 ,  32 , and  34  respectively.  
         [0011]     In the illustrated embodiment of the present invention, a dielectric layer  27  is formed overlying the junction between the anode  42  and the cathode  40 . Note that dielectric layer  27  may be formed of any dielectric material. In one embodiment, a thin oxide layer is used to form dielectric layer  27 . A conductive layer  28  is formed overlying the dielectric layer  27 . Note that the conductive layer  28  may be formed of any conductive or semi-conductive material. In one embodiment, a polysilicon layer is used to form conductive layer  28 . Note also that each of dielectric layer  27  and conductive layer  28  may be formed using a plurality of layers.  
         [0012]     In the illustrated embodiment of the present invention, a dielectric layer  19  is formed between the anode  42  and N+ region  16 . Note that dielectric layer  19  may be formed of any dielectric material. In one embodiment, a field oxide layer is used to form dielectric layer  19 . Oxide is just one possible dielectric material that may be used. Any other appropriate dielectric material may be used.  
         [0013]     In the illustrated embodiment of the present invention, a dielectric layer  18  is formed as a ring around the N++ region  32 . Note that dielectric layer  18  may be formed of any dielectric material. In some embodiments, a field oxide layer is used to form dielectric layer  18 . Oxide is just one possible dielectric material that may be used. Any other appropriate dielectric material may be used. In some embodiments, dielectric layer  18  may be a shallow trench isolation region. One purpose for dielectric layer  18  is to support a higher voltage difference between N++ region  32  and conductive layer or conductive plate  28 . Alternate embodiments of the present invention may not use dielectric layer  18  and may instead allow the other regions to extend up to the surface plane (i.e. the surface plane adjacent to the bottom surface of layer  27 ).  
         [0014]     In one embodiment of the present invention, anode  42  is electrically coupled to conductive layer  28  by way of conductive layer  44 . Conductive layer  44  has not been illustrated with any specific topology to make clear that any desired topology may be used. Conductive layer  44  may be formed using any conductive material that can be formed on a semiconductor device  10 .  
         [0015]     Alternate embodiments of the present invention may electrically bias the N isolation region formed by N++ region  34 , N+ region  16 , and N+ region  13  in order to reduce the parasitic current injected into substrate  12  from the vertical parasitic NPN and PNP devices. Note that in the illustrated embodiment, the vertical parasitic NPN transistor has a first N region formed from regions  32  and  22 , has a P region formed from regions  30 ,  20 ,  24 , and  26 , and has a second N region formed from region  13 . Similarly, the vertical parasitic PNP transistor has a first P region formed from regions  30 ,  20 ,  24 , and  26 , has an N region formed from region  13 , and has a second P region formed from region  12 .  
         [0016]     If the N++ region  34  is electrically coupled (e.g. shorted) to anode  42 , the emitter and base of the vertical parasitic PNP transistor are at approximately the same voltage, and thus there is no emitter/base bias. Consequently, the vertical parasitic PNP transistor produces very little collector current which is injected into P substrate  12 . Also, if the N++ region  34  is electrically coupled (e.g. shorted) to anode  42 , the base and collector of the vertical parasitic NPN transistor are at approximately the same voltage; and thus there is no way for the collector voltage to drop below ground to a negative voltage. If the collector was allowed to drop to a negative voltage, then the junction between the N+ region  13  and the P substrate  12  may form a conducting diode junction, thus injecting current into substrate  12 .  
         [0017]     If the N++ region  34  is electrically coupled (e.g. shorted) to cathode  40 , it will be possible to support a higher voltage on cathode  40 . Electrically coupling N++ region  34  and cathode  40  produces a negative bias on the junction between N region  22  and P region  26 , and also on the junction between P region  26  and N+ region  13 . These two reverse bias junctions together reduce the electrical field in N region  22 , particularly those portions of N region  22  which are closest to P− region  24  and closest to dielectric layer  18 . This reduced electric field allows a higher maximum voltage to be supported on cathode  40 .  
         [0018]     If the N++ region  34  is not electrically coupled to either anode  42  or cathode  40  and is allowed to electrically float, it will be possible to support an even higher voltage on cathode  40 . If the voltage of N+ region  13  is allowed to float, then the maximum voltage supported on cathode  40  will not be limited by the physical distance between P+ region  20  and N+ region  13 , but will be limited by other characteristics of device  10  (e.g. doping concentrations of regions N+ region  13  and P region  12 ).  
         [0019]     In one embodiment of the present invention, anode  42  includes a plurality of dopant concentrations. In one embodiment, P++ region  30  has a dopant concentration on the order of 1E20, P+ region  20  has a dopant concentration in the range of 2E17 to 4E17, P− region  24  has a dopant concentration in the range of 1E15 to 5E15, and P region  26  has a dopant concentration in the range of 2E16 to 5E16. These dopant concentrations are given just for illustrative purposes only. Alternate embodiments of the present invention may use any appropriate dopant concentrations. Note that the heavy dopant concentration in P++ region  30  is for the purpose of forming a good ohmic contact with an overlying conductive layer (not shown). Thus P++ region  30  may be called an ohmic region herein. Note that for some embodiments of the present invention, there is at least an order of magnitude (i.e. one power of ten) difference between the lowest P-type dopant concentration used in anode  42  and the highest P-type dopant concentration used in anode  42 . Alternate embodiments of the present invention may have at least two orders of magnitude (i.e. two powers of ten, or 100 times) difference between the lowest P-type dopant concentration used in anode  42  and the highest P-type dopant concentration used in anode  42 . Note that alternate embodiments of the present invention may designate the difference between the lowest and the highest dopant concentrations at any desired point between 0 (i.e. no difference) and the maximum difference allowed by integrated circuit fabricating technology.  
         [0020]     In one embodiment of the present invention, cathode  40  includes a plurality of dopant concentrations. In one embodiment, N++ region  32  has a dopant concentration on the order of 5E20, N region  22  has a dopant concentration in the range of 3E16 to 6E16. These dopant concentrations are given just for illustrative purposes only. Alternate embodiments of the present invention may use any appropriate dopant concentrations. Note that the heavy dopant concentration in N++ region  32  is for the purpose of forming a good ohmic contact with an overlying conductive layer (not shown). Thus N++ region  32  may be called an ohmic region herein. Interface  49  forms an anode/cathode junction interface between anode  42  and cathode  40 .  
         [0021]     In one embodiment of the present invention, the isolation region ( 34 ,  16 ,  13 ) includes a plurality of dopant concentrations. In one embodiment, N++ region  34  has a dopant concentration on the order of 5E20, N+ region  16  has a dopant concentration in the range of 5E17 to 8E17, and N+ region  13  has a dopant concentration in the range of 1E18 to 5E18. These dopant concentrations are given just for illustrative purposes only. Alternate embodiments of the present invention may use any appropriate dopant concentrations. Note that the heavy dopant concentration in N++ region  34  is for the purpose of forming a good ohmic contact with an overlying conductive layer (not shown). Thus N++ region  34  may be called an ohmic region herein.  
         [0022]     For alternate embodiments of the present invention, P substrate  12  may be doped to form a P+ substrate  12 . In an alternate embodiment of the present invention, substrate  12  may be a P++ substrate having an overlying P-type epitaxial layer formed thereon. Then implantation and diffusion may be used to form an N-type buried layer which serves a similar function as the N+ region  13  illustrated in  FIG. 1 . Then a second P-type epitaxial layer may be deposited overlying the N-type buried layer. This second P-type epitaxial layer may serve a similar function as the P− region  24  illustrated in  FIG. 1 . Then implantation may be used to form the P region  26  and the N region  22 . Note that for some embodiments, the same implantation mask may be used to form regions  26  and  22 . Next, etching and oxide deposition may be performed to form layers  14 ,  18 , and  19 . Then implantation may be used to form the P+ region  20 , and a separate implantation may be used to form N+ region  16 . Alternate embodiments of the present invention may use a plurality of implant steps and masks for forming N+ region  16 . Next, oxide deposition may be performed to form layer  27 , and polysilicon deposition may be performed to form layer  28 . Then implantation may be used to form the N++ regions  32  and  34 , and a separate implantation may be used to form P++ region  30 . Alternate embodiments of the present invention may use any appropriate alternate processing steps, in any appropriate order, to form various embodiments of semiconductor device  10 .  
         [0023]      FIG. 2  illustrates, in graphical form, a current versus voltage (cathode to anode voltage) graph illustrating cathode current (Icathode  50 ) and substrate current (Isubstrate  52 ) produced by the semiconductor device  10  of  FIG. 1 . Note that the parasitic current (Isubstrate  52 ) injected into substrate  12  (see  FIG. 1 ) is approximately six orders of magnitude less than the cathode current (Icathode  50 ).  FIG. 2  assumes that N++ region  34  (the isolation region) has been shorted to the anode  42  and both are approximately 0 Volts, the voltage of cathode  40  is pulled below 0 Volts, substrate  12  is biased to −10 volts, and the temperature of semiconductor device  10  is approximately 150 degrees Celsius. Increasing the width of N+ region  16  beyond 10 micrometers may further reduce the cathode current injected into substrate  12 ; however, a trade-off often must be made between the amount of semiconductor area required to form semiconductor device  10  and the electrical performance of semiconductor device  10 . Note that for conventional non-isolated diodes, the parasitic current injected into the substrate is approximately 10% of the cathode current. Thus a conventional non-isolated diode injects a very large amount of parasitic current into the substrate, causing potential malfunctions of adjacent circuitry formed on the same integrated circuit.  
         [0024]     Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed. Also, the semiconductor materials used to form the various portions of semiconductor device  10  may be any appropriate material. For example, substrate  12  may be silicon or any another appropriate semiconductor material. Also, semiconductor device  10  may be incorporated into a power integrated circuit which is operable for high voltages and high currents.  
         [0025]     In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.  
         [0026]     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.