Abstract:
A semiconductor memory device includes a memory cell block, gate lines and branch lines. The memory cell block includes memory cells connected in series. Each of memory cells has a cell transistor having a source and a drain and a ferroelectric capacitor inbetween the source and the drain. The gate lines are connected to the gates of the cell transistors of the memory cell block. The gate lines have a predetermined width and are arranged at regular intervals. The branch lines are formed of a layer different from that of the gate lines, arranged parallel to the gate lines, and each connected thereto. The branch lines have a predetermined width and are arranged at regular intervals. The sum of the width of the branch lines and the interval between adjacent branch lines differing from the sum of the width of the gate lines and the interval between adjacent gate lines.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-097887, filed Mar. 29, 2002, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory using a ferroelectric capacitor. 
     2. Description of the Related Art 
     Semiconductor memories are now being used everywhere such as for the main storages of large-sized computers, personal computers, household electrical appliances, portable telephones, etc. Semiconductor memories on the market include volatile DRAMs (Dynamic RAMs) and SRAMs (Static RAMs), and nonvolatile MROMs (Mask ROMs), Flash EEPROMs and ferroelectric memories, etc. 
     Ferroelectric memories utilize a hysteresis characteristic that is one of the characteristics of a ferroelectric, i.e., utilizes the difference between the two residual polarization amounts of each ferroelectric capacitor, thereby storing binary data in a nonvolatile state. In general, each of the memory cells that provide a conventional ferroelectric memory is formed by connecting a capacitor (ferroelectric capacitor) to a transistor in series, as in a DRAM. 
     However, unlike DRAMs, it is necessary in ferroelectric memories to drive a plate line in order to read a signal charge to a bit line, since data is stored using a residual polarization amount difference. To this end, ferroelectric memories require a plate line driving circuit for driving a plate line. Further, since conventional ferroelectric memories have the same structure as DRAMs, plate line driving circuits are provided for respective plate lines. Accordingly, the plate line driving circuits occupy a large part of a memory circuit forming area. 
     On the other hand, a cell array method for use in ferroelectric memories has been proposed which can reduce the area required for the plate line driving circuits (D. Takashima et al., “High-density chain Ferroelectric random memory (CFeRAM)” in proc. VLSI Symp. June 1997, pp 83-84). In this case, the source and drain of a cell transistor (T) are connected to the opposite ends of a ferroelectric capacitor (C), thereby forming a unit cell (memory cell) MC. A plurality of such unit cells are connected in series, thereby forming a memory cell block. The thus-constructed ferroelectric memory will hereinafter be referred to as a “series connected TC unit type ferroelectric memory”. 
     In the series connected TC unit type ferroelectric memory, eight unit cells, for example, can commonly use one plate line driving circuit. Therefore, the memory cell array formed of a plurality of memory cell blocks can be highly integrated. 
     FIG. 1A is a circuit diagram illustrating a memory cell array employed in the series connected TC unit type ferroelectric memory. FIG. 1B is a plan view illustrating the layout of the memory cell array. 
     Each unit cell MC is formed of the cell transistor T and ferroelectric capacitor C connected in parallel. In the case of FIG. 1A, eight unit cells MC are connected in series, thereby forming a memory cell block MCB 0  (or MCB 1 ). The memory cell blocks MCB 0  and MCB 1  are connected to a pair of bit lines BL and /BL, respectively. 
     One end of the memory cell block MCB 0  is connected to the bit line BL via a block selection transistor BST 0 , and the other end is connected to a plate line PL. Similarly, one end of the memory cell block MCB 0  is connected to the bit line /BL via a block selection transistor BST 1 , and the other end is connected to a plate line /PL. 
     Word lines WL 0 -WL 7  are connected to the respective gates of the cell transistors of each of the memory cell blocks MCB 0  and MCB 1 . Block selection signal lines BS 0  and BS 1  are connected to the gates of the block selection transistors BST 0  and BST 1 , respectively. 
     As seen from FIG. 1B, the plate lines PL and /PL, word lines WL 0 -WL 7 , and block selection signal lines BS 0  and BS 1  extend perpendicular to the cell arrangement of the memory cell blocks MCB 0  and MCB 1 . Accordingly, the memory cell blocks MCB 0  and MCB 1  can commonly use the lines. 
     As described above, in the series connected TC unit type ferroelectric memory shown in FIG. 1A, a plurality of memory cell blocks commonly use the plate lines PL and /PL, word lines WL 0 -WL 7 , block selection signal lines BS 0  and BS 1 , and control circuits for the respective signals. The chip size of the ferroelectric memory can be reduced by increasing the number of memory cell blocks connected to the plate lines PL and /PL, word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 . However, the larger the number of memory cell blocks commonly connected to those lines, the greater the signal delay in the lines. 
     To solve this problem, a method is employed, in which a branch line is formed of a layer different from that of a trunk line having a large delay or a large amount of current flown therethrough, and is arranged parallel thereto such that the lines are connected to each other at regular intervals. 
     A description will now be given of a series connected TC unit type ferroelectric memory having such trunk and branch lines as the above. 
     FIG. 2A is a circuit diagram illustrating a memory cell array employed in a conventional series connected TC unit type ferroelectric memory. FIG. 1B is a sectional view illustrating a memory cell array in which a branch line is formed by a conventional method. 
     The sectional view schematically illustrates source/drain diffusion layers  101 , gate lines  102 , a plate line  103 , contact plugs  104 , and branch lines  105  for the gate lines  102 . The plate line  103  and branch lines  105  are formed of a single layer. The gate lines  102  correspond to the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1  shown in FIG.  1 A. The sectional structure of each ferroelectric capacitor is not shown. 
     In the prior art, the branch lines  105  for the gate lines  102  are formed of a line layer provided on the gate line layer  102 , as is shown in FIG.  2 B. In this method, to enable the gate lines  102  to be connected to the branch lines  105  by contact plugs, the pitch (line width+line interval) of the branch lines  105  needs to be made identical to the pitch of the gate lines  102 . In other words, the line width of the branch lines  105  cannot be changed in accordance with a current flowing through the gate lines  102 . 
     Furthermore, if the line width of the plate line  103  formed of the same layer as the branch lines  105  is increased to avoid problems involving a signal delay in line or electronic migration due to resistors and capacitors, the memory block size is inevitably increased. 
     BRIEF SUMMARY OF THE INVENTION 
     According to an aspect of the invention, there is provided a semiconductor memory device comprising: a memory cell block which includes series connected memory cells each having a cell transistor having a source and a drain and a ferroelectric capacitor inbetween the source and the drain; a plurality of gate lines connected to gates of the cell transistors of the memory cell block, the gate lines having a predetermined width and being arranged at regular intervals; and a plurality of branch lines formed of a layer different from a layer of the gate lines, arranged parallel to the gate lines, and each connected to a corresponding one of the gate lines, the branch lines having a predetermined width and being arranged at regular intervals, a sum of the predetermined width of the branch lines and an interval between adjacent ones of the branch lines differing from a sum of the predetermined width of the gate lines and an interval between adjacent ones of the gate lines. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
     FIG. 1A is a circuit diagram illustrating memory cell blocks employed in a conventional series connected TC unit type ferroelectric memory; 
     FIG. 1B is a plan view illustrating the layout of the memory cell blocks; 
     FIG. 2A is a circuit diagram illustrating a memory cell block employed in another conventional series connected TC unit type ferroelectric memory; 
     FIG. 2B is a sectional view illustrating the memory cell block in which branch lines are formed by a conventional method; 
     FIG. 3 is a plan view illustrating the layout of memory cell blocks employed in a series connected TC unit type ferroelectric memory according to a first embodiment of the invention; 
     FIG. 4A is a sectional view taken along line  4 A— 4 A in FIG. 3; 
     FIG. 4B is a sectional view taken along line  4 B— 4 B in FIG. 3; 
     FIG. 5A is a plan view illustrating a part of the layout of the memory cell blocks shown in FIG. 3; 
     FIG. 5B is a plan view illustrating third lines M 3  employed in the memory blocks; 
     FIG. 5C is a plan view illustrating the gate lines (word lines, block selection signal lines) of the memory cell blocks; 
     FIG. 6A is a sectional view taken along line  6 A— 6 A in FIG. 3; 
     FIG. 6B is a sectional view illustrating the structure between memory cell blocks obtained when the plate lines are composed of lines M 1  that are made of a first layer; 
     FIG. 7 is a sectional view illustrating memory cell blocks employed in a series connected TC unit type ferroelectric memory according to a second embodiment of the invention; 
     FIG. 8 is a plan view illustrating the layout of the memory cell blocks employed in the ferroelectric memory of the second embodiment; and 
     FIG. 9 is a sectional view illustrating memory cell blocks employed in a series connected TC unit type ferroelectric memory according to a third embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to ferroelectric memories as semiconductor memories according to embodiments of the invention, as illustrated in the accompanying drawings, in which like reference characters designate like or corresponding parts throughout the several drawings. 
     First Embodiment 
     Firstly, a series connected TC unit type ferroelectric memory according to a first embodiment of the invention will be described. In this series connected TC unit type ferroelectric memory, the source and drain of a cell transistor (T) are connected to the opposite ends of a ferroelectric capacitor (C) to form a unit cell (memory cell), and a plurality of such unit cells are connected in series to form a memory cell block. 
     FIG. 3 is a plan view illustrating the layout of memory cell blocks employed in the series connected TC unit type ferroelectric memory according to the first embodiment of the invention. In this case, eight unit cells are connected in series, and the cell transistor of each unit cell is connected to word lines (gate lines) WL 0 -WL 7 . 
     As seen from FIG. 3, in each memory block, the word lines WL 0  (GC)-WL 7  (GC) formed on a gate insulation film are arranged in this order from the right. Block selection signal lines BS 0 (GC) and BS 1 (GC), which are the gate lines of block selection transistors, are provided at the right side of the word line WL 0 . 
     Branch lines WL 0 (M 3 )-WL 7 (M 3 ) and BS 0 (M 3 ) and BS 1 (M 3 ), which are composed of lines M 3  that are made of a third layer, are provided on the word lines WL 0 (GC)-WL 7 (GC) and block selection signal lines BS 0 (GC) and BS 1 (GC). A plate line PL(M 3 ) is provided at the left side of the branch line WL 7 (M 3 ). Further, bit lines BL and/BL are provided in a direction perpendicular to the direction of the word lines WL 0 (GC)-WL 7  (GC). A ferroelectric capacitor C is formed between each of the word lines WL 0 (GC)-WL 7 (GC) and a corresponding one of the branch lines WL 0 (M 3 )-WL 7 (M 3 ). 
     A description will be given of the sectional structure of each memory block. 
     FIG. 4A is a sectional view taken along line  4 A— 4 A in FIG.  3 . 
     As shown in FIG. 4A, a plurality of source/drain regions  12  are formed in the surface of a semiconductor substrate  11 . The word lines (gate lines) WL 0 -WL 7  of cell transistors and the block selection signal lines BS 0  and BS 1  of block selection transistors are formed on the substrate  11  via a gate insulation film (not shown) between each pair of adjacent source/drain regions  12 . 
     Lines M 1  formed of a first layer that is made of, for example, a metal are provided on the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 , with an interlayer insulation film  13  interposed therebetween. A ferroelectric capacitor C is formed between each line M 1  and a corresponding source/drain region  12 . A plate line PL formed of a line M 1  of the first layer is provided at the left side of the word line WL 7 . 
     A contact plug P 1  is formed between the source/drain region  12  of a block selection transistor and a corresponding line M 1 . A contact plug P 2  is formed between the source/drain region  12  of each cell transistor and a corresponding line M 1 . Further, a contact plug P 3  is formed between the source/drain region  12  of the leftmost cell transistor and a plate line PL (line M 1 ). 
     Furthermore, a line M 2  formed of a second layer that is made of, for example, a metal is provided above the lines M 1 . The line M 2  serves as a bit line BL and is connected, via a contact plug P 4 , the line M 1  that is connected to the source/drain region  12  of the block selection transistor. Yet further, lines M 3  formed of a third layer that is made of, for example, a metal are provided above the line M 2 . The lines M 3  are connected to the block selection signal line BS 1 , signal line MBS, block selection signal line BS 0 , word lines WL 0 -WL 7  and plate line PL in this order from the right, and serve as branch lines. The signal line MBS is connected to a control circuit (not shown) for controlling the block selection transistors, and is interposed between the block selection signal lines BS 0  and BS 1 . 
     FIG. 4B is a sectional view taken along line  4 B— 4 B in FIG.  3 . FIG. 4B shows the three lines M 1 , M 2  and M 3  and contact plugs formed of layers that differ from the layers of the gate lines (word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 ). 
     As seen from FIG. 4B, a plurality of source/drain regions  12  are formed in the surface of the semiconductor substrate  11  as described above. The word lines WL 0 -WL 7  of the cell transistors, and the block selection signal lines BS 0  and BS 1  of the block selection transistors are formed on the substrate  11  via the aforementioned gate insulation film between each pair of adjacent source/drain regions  12 . The word lines WL 0 -WL 7  are arranged with substantially the same pitch (first pitch). 
     The lines M 1 , M 2  and M 3  are provided, in this order from the bottom, on the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1  via the interlayer insulation film  13 . 
     Contact plugs P 5  are provided between the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 , and the lines M 1 , thereby connecting them. The contact plugs P 5  are arranged with substantially the aforementioned first pitch so that they can be aligned with the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 . 
     Contact plugs P 6  are provided between the lines M 1  and M 2 , thereby connecting them. The contact plugs P 6 , which are connected to the word lines WL 3  and WL 4  located at a central portion of the memory cell block, are located just above the word lines WL 3  and WL 4 . 
     The contact plug P 6  located at the right side of the word line WL 3  is located at a shorter distance from the plug P 6  located just above the word line WL 3  than the aforementioned first pitch. Similarly, the contact plug P 6  located at the left side of the word line WL 4  is located at a shorter distance from the plug P 6  located just above the word line WL 4  than the first pitch. 
     Contact plugs P 7  are provided between the lines M 2  and M 3 , thereby connecting them. The contact plugs P 7 , which are connected to the word lines WL 3  and WL 4  located at a central portion of the memory cell block, are located just above the word lines WL 3  and WL 4 . The contact plugs P 7  that are not connected to the word line WL 3  or WL 4  are arranged with a narrower pitch than the first pitch, so that they can be located closer to the plugs P 7  connected to the word lines WL 3  and WL 4 . As a result, the lines M 3  connected to the plugs P 7  are arranged with a second pitch narrower than the first pitch. The lines M 3  are connected to the block selection signal line BS 1 , signal line MBS, block selection signal line BS 0 , word lines WL 0 -WL 7  and plate line PL, in this order from the right. 
     By virtue of the above-described structure, branch lines arranged with a narrower pitch than that of the word lines (gate lines) WL 0 -WL 7  can be realized using the lines M 3 . 
     In the first embodiment, the lines M 3  formed of the uppermost layer extend parallel to the gate lines, and perpendicular to the line of each memory cell block. Further, the lines M 3  are connected to the gate lines, as shown in FIG. 4B, between each pair of adjacent memory cell blocks. The lines M 1  and M 2  located between the gate lines and uppermost lines M 3  are used as relay lines for connecting the lines M 3  to the gate lines as shown in FIG.  4 B. This structure enables the pitch (line width+line interval) of the lines M 3  to be made different from that of the gate lines. In the embodiment, the pitch of the lines M 3  is made narrower than that of the gate lines. Thus, the width of the branch lines M 3  can be set with a higher degree of freedom. This enables a space to be secured for forming other lines. 
     Further, as shown in FIG. 4B, the signal line MBS connected to a control circuit (not shown) for controlling the block selection transistors can be located between the block selection signal lines BS 0  and BS 1  by making the pitch of the lines M 3  narrower than that of the gate lines. 
     FIG. 5A is a plan view illustrating a part of the layout of the memory cell blocks shown in FIG.  3 . FIG. 5B is a plan view illustrating the third lines M 3  employed in the memory blocks. FIG. 5C is a plan view illustrating the gate lines (word lines, block selection signal lines) of the memory cell blocks. 
     From these figures, it is understood that the pitch Y of the lines M 3  is narrower than the pitch X of the gate lines GC. Further, as shown in FIG. 5B, the plate line PL as one of the lines M 3  can be made thick by making the pitch Y of the branch lines M 3  for the gate lines GC narrower than the pitch X of the gate lines GC. 
     A description will now be given of the sectional structure of a portion between adjacent memory cell blocks in the ferroelectric memory. 
     FIG. 6A is a sectional view taken along line  6 A— 6 A in FIG. 3, illustrating the cross section of a portion between adjacent memory cell blocks. 
     As seen from FIG. 6A, the source/drain regions  12  are formed in the surface of the semiconductor substrate  11 . Each of the word lines WL 7  and WL 15  is formed on the substrate via a gate insulation film (not shown) between adjacent source/drain regions  12 . The word line WL 7  is dedicated to one of a pair of memory cell blocks, and the other word line WL  15  to the other memory cell block. 
     Ferroelectric capacitors C 1  and C 2  are formed on the word lines WL 7  and WL 15 , respectively, via the interlayer insulation film  13 . The lines M 1 , M 2  and M 3  are formed, in this order from the bottom, on the capacitors C 1  and C 2  via the interlayer insulation film  13 . The plate lines PL and /PL are composed of two of the lines M 3  that are made of the third layer. 
     FIG. 6B is a sectional view illustrating the structure between adjacent memory cell blocks obtained when the plate lines are composed of two of the lines M 1  that are made of the first layer. As shown, when the plate lines PL are composed of the two lines M 1 , they are located between the other two lines M 1  connected to the ferroelectric capacitors C 1  and C 2 , and hence the distance between the adjacent capacitors C 1  and C 2  is longer than in the structure shown in FIG.  6 A. 
     As is understood from FIGS. 6A and 6B, if the plate lines PL are composed of two of the lines M 3  and located on the corresponding cell transistors, the distance between the adjacent memory cell blocks can be reduced without thinning the width of the plate lines. As a result, the memory cell array in which a plurality of memory cell blocks are arranged can be made compact. 
     As described above, in the first embodiment, the amount of current flowing through the gate lines and/or the width of the branch lines M 3  can be adjusted, so as to compensate a signal delay in the gate lines, by making the pitch of the branch lines M 3  different from that of the gate lines. In addition, lines other than the branch lines can be provided in the same wiring layer as the branch lines, i.e., without increasing the number of wiring layers. 
     Second Embodiment 
     A series connected TC unit type ferroelectric memory according to a second embodiment of the invention will be described. In the first embodiment, when the branch lines are composed of lines M 3 , they are arranged centered on the central word lines WL 3  and WL 4 . On the other hand, in the second embodiment, branch lines formed of lines M 3  are arranged centered on the rightmost word line WL 0 . 
     FIG. 7 is a sectional view illustrating memory cell blocks employed in the series connected TC unit type ferroelectric memory of the second embodiment of the invention. It shows a cross section taken along line  4 A— 4 A in FIG.  3 . 
     As seen from FIG. 7, a plurality of source/drain regions  12  are formed in the surface of the semiconductor substrate  11 , as in the first embodiment. Between the adjacent source/drain regions  12 , the word lines (gate lines) WL 0 -WL 7  of cell transistors, and the block selection signal lines (gate lines) BS 0  and BS 1  of block selection transistors are formed on the substrate  11  with a gate insulation film (not shown) interposed therebetween. The word lines WL 0 -WL 7  are arranged with substantially the same pitch (first pitch). 
     Lines M 1 , M 2  and M 3  are provided, in this order from the bottom, on the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1  via the interlayer insulation film  13 . 
     Contact plugs P 5  are provided between the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 , and the lines M 1 , thereby connecting them. The contact plugs P 5  are arranged with substantially the aforementioned first pitch so that they can be aligned with the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 . 
     Contact plugs P 6  are provided between the lines M 1  and M 2 , thereby connecting them. The contact plug P 6 , which is connected to the rightmost word line WL 0 , is located just above the word line WL 0 . The other contact plugs P 6  are arranged with a narrower pitch than the first pitch so that they can be located closer to the word line WL 0 . 
     Contact plugs P 7  are provided between the lines M 2  and M 3 , thereby connecting them. The contact plug P 7 , which is connected to the rightmost word line WL 0 , is located just above the word line WL 0 . The other contact plugs P 7  are arranged with a narrower pitch than the first pitch so that they can be located closer to the word line WL 0 . Thus, the lines M 3  are arranged with a second pitch narrower than the first pitch of the word lines WL 0 -WL 7 . The lines M 3  are connected to the block selection signal lines BS 1  and BS 0 , word lines WL 0 -WL 7  and plate line PL, in this order from the right. 
     By virtue of the above-described structure, branch lines arranged with a narrower pitch than that of the word lines (gate lines) WL 0 -WL 7  can be realized using the lines M 3 . In this case, the width of the plat line PL can be thickened by changing the pitch of the lines M 3 . 
     In the second embodiment, the lines M 3  formed of the uppermost layer extend parallel to the gate lines. Further, as shown in FIG. 7A, the gate lines are connected to the lines M 3  via the lines M 1  and M 2  and contact plugs. This structure enables the pitch (line width+line interval) of the lines M 3  to be made different from that of the gate lines. In the embodiment, the pitch of the lines M 3  is made narrower than that of the gate lines. Thus, the width of the branch lines M 3  can be set with a higher degree of freedom. This enables a space to be secured for forming other lines. 
     FIG. 8 is a plan view illustrating the layout of memory cell blocks employed in the ferroelectric memory of the second embodiment. 
     As shown in FIG. 8, the block selection signal lines BS 1  and BS 0 , and word lines WL 0 -WL 7 , which are gate lines, are arranged in this order from the right. Further, the block selection signal lines BS 1  and BS 0 , word lines WL 0 -WL 7  and plate line PL, which are formed of the lines M 3 , are arranged in this order from the right. 
     It is understood from FIG. 8 that the pitch of the lines M 3  is narrower than that of the gate lines. Further, the plate line PL as one of the lines M 3  can be made thick by making the pitch of the branch lines narrower than that of the gate lines. 
     As described above, in the second embodiment, the amount of current flowing through the gate lines and/or the width of the branch lines M 3  can be adjusted, so as to compensate a signal delay in the gate lines, by making the pitch of the branch lines M 3  different from that of the gate lines. In addition, lines other than the branch lines can be provided in the same wiring layer as the branch lines, i.e., without increasing the number of wiring layers. 
     Third Embodiment 
     A series connected TC unit type ferroelectric memory according to a third embodiment of the invention will be described. In the first embodiment, the branch lines are formed of the lines M 3  of the third layer, while in the third embodiment, the branch lines are formed of lines M 2  made of the second layer. 
     FIG. 9 is a sectional view illustrating memory cell blocks employed in the series connected TC unit type ferroelectric memory according to the third embodiment. It shows a cross section taken along line  4 A— 4 A in FIG.  3 . 
     In the first embodiment, the branch lines are formed by connecting the gate lines to the uppermost lines M 3  between the different types of lines M 1 , M 2  and M 3 . On the other hand, in the third embodiment, the branch lines are formed by connecting the intermediate lines M 2  provided below the uppermost lines M 3 . 
     As seen from FIG. 9, a plurality of source/drain regions  12  are formed in the surface of the semiconductor substrate  11 , as in the first or second embodiment. Between the adjacent source/drain regions  12 , the word lines WL 0 -WL 7  of cell transistors, and the block selection signal lines BS 0  and BS 1  of block selection transistors are formed on the substrate  11  with a gate insulation film (not shown) interposed therebetween. The word lines WL 0 -WL 7  are arranged with substantially the same pitch (first pitch). 
     The lines M 1 , M 2  and M 3  are provided, in this order from the bottom, on the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1  via the interlayer insulation film  13 . 
     Contact plugs P 5  are provided between the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 , and the lines M 1 , thereby connecting them. The contact plugs P 5  are arranged with substantially the aforementioned first pitch so that they can be aligned with the word lines WL 0 -WL 7  and block selection signal lines BS 0  and BS 1 . 
     Contact plugs P 6  are provided between the lines M 1  and M 2 , thereby connecting them. The contact plug P 6 , which is connected to the word line WL 4  located at a central portion of the memory cell block, is located just above the word line WL 4 . 
     The contact plugs P 6  located at the right side of the word line WL 4  are arranged with a narrower pitch than the first pitch, so that they can be located closer to the plug P 6  located just above the word line WL 4 . Similarly, the contact plugs P 6  located at the left side of the word line WL 4  are arranged with a narrower pitch than the first pitch, so that they can be located closer to the plug P 6  located just above the word line WL 4 . Further, the lines M 2  connected to the contact plugs P 6  are arranged with a narrower pitch than the first pitch of the word lines WL 0 -WL 7 , as is shown in FIG.  9 . 
     By virtue of the above-described structure, branch lines arranged with a narrower pitch than that of the word lines (gate lines) WL 0 -WL 7  can be realized using the lines M 2 . 
     In the third embodiment, the lines M 2  formed of the second layer extend parallel to the gate lines and perpendicular to the line of each memory cell block. Further, the lines M 2  are connected to the gate lines, as shown in FIG. 9, between each pair of adjacent memory cell blocks. The lines M 1  located between the gate lines and lines M 2  are used as relay lines for connecting the lines M 2  to the gate lines. This structure enables the pitch (line width+line interval) of the lines M 2  to be made different from that of the gate lines. In the embodiment, the pitch of the lines M 2  is made narrower than that of the gate lines. Thus, the width of the branch lines M 2  can be set with a higher degree of freedom. This enables a space to be secured for forming other lines. 
     Further, the signal line MBS connected to a control circuit (not shown) for controlling the block selection transistors can be located between the block selection signal lines BS 0  and BS 1  by changing the pitch of the lines M 2 . 
     As described above, in the third embodiment, the amount of current flowing through the gate lines and/or the width of the branch lines M 2  can be adjusted, so as to compensate a signal delay in the gate lines, by making the pitch of the branch lines M 2  different from that of the gate lines. In addition, lines other than the branch lines can be provided in the same wiring layer as the branch lines, i.e., without increasing the number of wiring layers. 
     Further, the above-described embodiments can be carried out, individually or in combination. 
     In addition, the above-described embodiments contain inventions of various stages, and these inventions can be extracted by appropriately combining the structural elements employed in the embodiments. 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.