Abstract:
Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority to U.S. Provisional Application Ser. No. 61/483,920, entitled CMOS IMAGE SENSOR WITH MULTISAMPLING ADC USING SAR (SUCCESSIVE APPROXIMATION REGISTER) AND MULTIPLE RAMP, filed May 9, 2011, the contents of which are incorporated fully herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    Embodiments described herein relate generally to semiconductors and more particularly to analog to digital conversion methods, systems, and apparatus. 
       BACKGROUND OF THE INVENTION 
       [0003]    Many portable electronic devices, such as cameras, cellular telephones, Personal Digital Assistants (PDAs), MP3 players, computers, and other devices include a semiconductor (e.g., complementary metal-oxide-semiconductor; CMOS) imaging device for capturing images using an array of pixels.  FIG. 1  depicts an imaging device  100  that includes an array  102  of pixels  104  and a timing and control circuit  106 . The timing and control circuit  106  provides timing and control signals for enabling the reading out of signals from pixels  104  of the pixel array  102  in a manner commonly known to those skilled in the art. Although one pixel  104  is illustrated, the pixel array  102  has dimensions of Y rows by X columns of pixels  104 , with the size of the pixel array  102  depending on the application. 
         [0004]    Signals from the imaging device  100  are typically read out a row at a time using a column parallel readout architecture. The timing and control circuit  106  selects a particular row of pixels in the pixel array  102  by controlling the operation of a row addressing circuit  108  and row drivers  110 . Signals stored in the selected row of pixels are provided to a readout circuit  112  in the manner described above. The signals are read twice from each of the columns and then read out sequentially or in parallel using a column addressing circuit  114 . The pixel signals (Vrst, Vsig) corresponding to a pixel reset signal and an pixel image signal are provided as outputs of the readout circuit  112 , and are typically subtracted by a differential amplifier  116  in a correlated double sampling (CDS) operation and the result digitized by an analog to digital converter (ADC)  118  to provide a digital pixel signal represent an image captured by pixel array  102  for processing by an image processing circuit  120 . 
         [0005]    Pixel values are read out as tiny voltages, on the order of microvolts per electron. Those voltages are passed to the ADC  118  for conversion into a digital pixel value.  FIG. 2  depicts a prior art ADC  200  known as a ramp ADC. Vin is the analog input voltage and Dn through D 0  are multiple bit digital outputs (eight output bits are illustrated). A counter  202  starts counting when an analog input voltage is to be converted. The counter supplies a digital counter value to a digital to analog converter  204 , which generates a comparison voltage level at a comparator  206 . As the counter  202  increases, the comparison voltage incrementally increases for comparison with the analog input voltage. Once the comparison voltage exceeds the analog input voltage, the counter  202  ends with the end value representing the multiple bit digital output of the analog input voltage. An ADC such as ADC utilize up to 2̂n−1 clock cycles to convert each analog voltage sample. Thus, for an 8-bit ADC, it take up to 255 clock cycles to convert a single sample. For a 16-bit ADC it would take up to 65,535 clock cycles to convert one sample. 
         [0006]      FIG. 3  depicts another prior art ADC  300  known as a successive approximation register (SAR) ADC. Vin is the analog input and Dn through DO are the multiple bit digital outputs. A SAR  302  supplies a digital value to a digital to analog converter  304 , which generates a comparison voltage level at a comparator  306 . A controller  308  sets the SAR  302  and monitors the comparator  306  to identify the multiple bit digital output one bit at a time from the most significant bit (MSB) to the least significant bit (LSB). A buffer  310  stores each bit of the multiple bit digital output so the digital data remains available while the ADC  300  is processing the next sample of the analog input voltage. 
         [0007]    In operation, the SAR  302  initially supplies to the DAC  304  a “1” in the MSB position and “0”s in the remaining positions. If the input voltage is greater than the comparison voltage level, a “1” is stored for the MSB and the ADC  300  proceeds with the MSB and the next MSB set to “1.” If the input voltage is less than the comparison voltage level, a “0” is stored for the MSB and the ADC  300  proceeds with the MSB set to “0” and the next MSB set to “1.” The ADC  300  proceeds until all bits of the multiple bit digital output are determined. Thus, the ADC  300  is able to find the correct digital value for the analog input voltage in n clock cycles, where n is the number of bits in the multiple bit digital output. For an 8-bit ADC  300 , the digital value for each sample can be found in up to eight clock cycles (compared to 255 for ADC  200  (FIG.  2 )), and for a 16-bit ADC the digital value for each sample can be found in up to 16 clock cycles (compared to 65,535 for ADC  200  ( FIG. 2 )). 
         [0008]    Noise is an important factor in the design of imaging devices. Noise may result from many of the operations performed during the capture and digitization of an image, both uncorrelated, random noise and periodic noise. Low frequency noise is minimized by CDS, but CDS increases temporal noise. Multisampling is one known technique for reducing low and high frequency noise. Known multisampling techniques, however, are difficult to commercially implement due to frame rate and silicon area limitations. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The invention is best understood from the following detailed description when read in connection with the accompanying drawings, with like elements having the same reference numerals. When a plurality of similar elements are present, a single reference numeral may be assigned to the plurality of similar elements with a small letter designation referring to specific elements. When referring to the elements collectively or to a non-specific one or more of the elements, the small letter designation may be dropped. The letters “m,” “n,” “M,” “N,” “X,” and “Y” may represent a non-specific number of elements. Also, lines without arrows connecting components may represent a bi-directional exchange between these components. This emphasizes that according to common practice, the various features of the drawings are not drawn to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawings are the following figures: 
           [0010]      FIG. 1  is a block diagram of a prior art imaging device. 
           [0011]      FIG. 2  is a block diagram of a prior art ADC; 
           [0012]      FIG. 3  is a block diagram of another prior art ADC; 
           [0013]      FIG. 4  is a block diagram partially in circuit diagram form of an example ADC in accordance with an aspect of the present invention; 
           [0014]      FIG. 4A  is a graph of a voltage ramp generated by a ramp generator of the ADC of  FIG. 4 ; 
           [0015]      FIG. 4B  is an illustration of the voltage values generated by the SAR conversion circuitry and the ramp conversion circuitry of the ADC of  FIG. 4 ; 
           [0016]      FIG. 5  is a block diagram partially in circuit diagram form of an alternative example SAR Control for use in the ADC of  FIG. 4 ; 
           [0017]      FIG. 6  is a flow chart of an example analog to digital conversion method in accordance with an aspect of the present invention; 
           [0018]      FIG. 6A  is a flow chart for generating bits of a digital value using SAR conversion for use in the method of  FIG. 6 ; and 
           [0019]      FIG. 6B  is a flow chart for generating bits of a digital value using ramp conversion for use in the method of  FIG. 6 . 
           [0020]      FIG. 6C  is a flow chart for obtaining bits based on a counter for use in the method of  FIG. 6B . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]      FIG. 4  depicts an ADC  400  that converts an analog voltage signal into a multiple bit digital value in accordance with aspects of the present invention. The ADC  400  includes SAR conversion circuitry  402  and ramp conversion circuitry  404 . The multiple bit digital value includes a bit string of several bits with each bit representing a different voltage level. In accordance with typical terminology, the leftmost bit in the bit string is associated with the largest voltage level and is referred to as the most significant bit (MSB), the rightmost bit in the bit stream is associated with the smallest voltage level and is referred to as the least significant bit (LSB), and the bits in between from the LSB to the MSB are associated with incrementally larger voltage levels. In use and as will be described in further detail below, the SAR conversion circuitry  402  generates the most significant bit(s) in the bit stream (including at least the MSB) and the ramp conversion circuitry  404  generates the least significant bit(s) in the bit stream (including at least the LSB). For example, for a 12 bit multiple bit digital value, the SAR conversion circuitry  402  may generate the first 6 bits in the bit stream during a SAR conversion process and the ramp conversion circuitry  404  may generate the last 6 bits in the bit stream during a ramp conversion process. 
         [0022]    The SAR conversion circuitry  402  includes a comparator  412  that compares the analog voltage signal (ADC Input) to comparison voltages including a series of reference voltages. The comparator  412  includes an input port  413   a  that receives the analog voltage signal and another input port  413   b  that receives the comparison voltages. As described below, the comparison voltages are initially generated by a DAC  408  under control of a SAR control  414  during a SAR conversion process and, then, are generated by a ramp voltage, Vramp, generated by a ramp generator  402  of the ramp conversion circuitry  404  in combination with the DAC  408  under control of a SAR control  414  during a ramp conversion process. 
         [0023]    The comparator  412  produces an output signal indicative of the comparison between the analog voltage signal and the comparison voltages at an output port  413   c,  which is captured by a latch  416 . Although the comparator  412  is illustrated as having the analog voltage signal coupled to a positive (+) input port  413   a  of the comparator  412  and the comparison voltages coupled to a negative (−) input port  413   b  of the comparator  412 , suitable modification to the ADC  400  in order for these inputs  413   a,  b to be exchanged will be understood by one of skill in the art. The SAR conversion circuitry  402  may be implemented using conventional CMOS fabrication techniques. The comparator  412  may be combined with switched capacitor circuits for auto-zeroing, e.g., to remove offsets and low frequency noise. The design of suitable comparators and latches for use with the present invention (including the use of capacitors and switches within the comparator  412  for offset cancellation) will be understood by one of skill in the art from the description herein. 
         [0024]    The SAR conversion circuitry  402  additionally includes a SAR and an associated memory. In the illustrated embodiment, the memory is incorporated into the SAR to create a memory SAR  406  that functions as a SAR and an output buffer of a conventional SAR ADC. The memory SAR  406  is configured to store bits of the multiple bit digital value in the memory as the bits are determined by the SAR conversion circuitry  402  during the SAR conversion process. Additionally, the SAR control  414  may retrieve the stored bits from the memory during the ramp conversion process in order to configure the DAC  418  to produce a SAR voltage level for combination with the ramp voltage. Although illustrated as a single component, it will be understood by one of skill in the art that the SAR and memory of memory SAR  406  may be formed as separate components. 
         [0025]    The SAR control  414  is coupled to the output port  413   c  of the comparator  412  via the latch  416  and is also coupled to the memory SAR  406  and the DAC  418 . The SAR control  414  receives information from and controls the memory SAR  406 , receives information from the comparator  412  via the latch  416 , and sets the DAC  418  to produce the comparison voltage at the input port  413   b  of the comparator  412  based on information received from the comparator  412  and the memory SAR  406 . The SAR controller  414  adjusts the DAC  418  to generate the comparison voltage (SAR comparison voltage) at the input port  413   b  of the comparator  412  during the SAR conversion process. Additionally, the SAR controller determines a SAR voltage level associated with the at least one bit of the multiple bit digital value being determined using the SAR conversion process, and present the SAR voltage level at the input port  413   b  of the comparator  412  for use during the ramp conversion process. 
         [0026]    The DAC  418 , under control of the SAR control  414 , produces the SAR comparison voltage during the ramp conversion process and produces the SAR voltage level during the ramp conversion process. The DAC  418  includes at least one switched capacitor circuit  410 . Each switched capacitor circuit  410  is associated with a voltage level. The SAR control  414  switches the switched capacitor circuits  410  to generate the desired comparison voltage at the comparator  412 . In an embodiment, there is a switched capacitor circuit  410  for each bit of the multiple bit digital output being generated during the SAR conversion process. For example, if M bits of the multiple bit digital value are generated using the SAR conversion circuitry  402 , there will be M capacitor circuits  410 -(M),  410 -(M- 1 ), . . . ,  410 - 1 . Thus, if 6 bits are to be determined using the SAR conversion circuitry  402  there would be at least  6  capacitor circuits  410 . 
         [0027]    The ramp conversion circuitry  404  includes the comparator  412 , a ramp generator  420 , and a counter  422 . The ramp conversion circuitry  404  additionally includes a controller (not shown) which may be implemented within the SAR control  414 . The ramp generator  420  is coupled to the input port  413   b  of the comparator  412  via a capacitor  421  and generates a ramp  454  ( FIG. 4A ) of voltage level steps during each conversion of a sample of the analog voltage signal. The ramp generator  420  may generate the ramp using conventional techniques such as through the use of a DAC coupled to a counter or the use of an integrator. 
         [0028]    As illustrated in  FIG. 4A , the ramp generator  420  may generate a ramp  454  including multiple ramp portions, e.g., to effectively multi-sample the analog input. The multiple ramp portions may include at least one ramp with increasing voltage level steps, such as ramp portions  452   a, c,  and at least one ramp portion with decreasing voltage level steps, such as ramps  452   b, d.  In the illustrated embodiment, there are an equal number of increasing voltage level ramp portions and decreasing voltage level ramp portions. 
         [0029]    Referring back to  FIG. 4 , a counter  422  is coupled to the output port  413   c  of the comparator  412  via the latch  416 . The counter  422  is configured to selectively increment during comparison of the analog voltage signal to the comparison voltages generated by the DAC  418  and the ramp generator  420 . In one embodiment, in which multiple ramp portions that alternate between increasing voltage level steps and decreasing voltage level steps, the counter  422  increments for each step of the increasing voltage level ramp until the voltage level of the analog voltage signal exceeds the comparison voltage during the ramp conversion process generated by the DAC  418  and the current step of the ramp. The counter  422  then begins incrementing again for each step of a decreasing voltage level ramp once the voltage level of the analog voltage signal exceeds the comparison voltage during the ramp conversion process generated by the DAC  418  and the current step of the ramp. 
         [0030]    The process is repeated until the desired number of ramp portions have been applied. In an embodiment, the counter  422  includes a bit for each bit of the multiple bit digital output generated using the ramp conversion circuitry. The number of bits, N, may be determined as N=log 2 K+log 2 L, wherein K is the number of steps in each ramp and L is the number of ramps. For example, if there are 4 ramps and each ramp has 16 steps (e.g, 0-15), then N would be 6. It will be understood by one of skill in the art from the description herein that the counted value as described herein represents the average value of the analog voltage signal (less the SAR voltage level) being converted. 
         [0031]      FIG. 4B  depicts a graph  470  illustrating the voltages being generated by the SAR conversion circuitry  402  and by the ramp conversion circuitry  404 . The SAR conversion circuitry  402  produces the SAR comparison voltages illustrated in a first portion  472  of the graph  470  and the ramp conversion circuitry  404  produces the ramp voltages illustrated in the second portion of the graph. As illustrated, the SAR conversion circuitry  402  produces relatively large voltage levels when compared to the voltage levels produced by the ramp conversion circuitry  404 . This enables relatively course voltage determinations to be made during the SAR conversion process that can be refined during the ramp conversion process. Additionally, the use of multiple ramp portions by the ramp conversion circuitry effectively implements multisampling during the refinement to reduce noise introduced during the amplification and conversion of analog voltage signal samples. 
         [0032]      FIG. 5  depicts an alternative embodiment of a portion of the SAR control  414 . In this embodiment, a storage device  500  is incorporated into the SAR control  414  to store SAR bit levels from the SAR memory for configuring the DAC  418 . Once stored in storage device  500 , the stored values can be quickly retrieved for configuring the DAC  418  when needed. The storage device  500  may include circuitry for each bit of the multiple bit value determined using the SAR conversion circuitry  402 . For example, a value stored in each bit of the illustrated storage device  500  may be used to set a respective capacitor in the illustrated switched capacitor circuit  410 -(M). Each bit of the storage device  500  may be implemented with a pair of CMOS inverters  502   a,    502   b  connected in a ring. Additional details regarding SAR ADCs can be found in U.S. Pat. No. 7,567,196 to Christian Boemler, entitled Method of Controlling Digital-to-Analog Conversion, the contents of which are incorporated fully herein by reference. 
         [0033]    In an embodiment, the ADC  400  may be used in an imaging system such as a camera including a pixel array of active pixels where each pixel produces an analog voltage image signal. The ADC  400  may be coupled to the active pixel to produce a multiple bit digital image value from the analog voltage image signal. 
         [0034]      FIG. 6  depicts a flow chart  600  of steps for converting an analog voltage signal into a multiple bit digital value in accordance with aspects of the invention. The method will be described with reference to the components illustrated in  FIGS. 2 ,  3 ,  4 ,  4 A, and  4 B to facilitate description. Other suitable components for implementing the method will be understood by one of skill in the art from the description herein. 
         [0035]    At step  602 , an analog voltage signal is received. The analog voltage signal may be received from an active pixel within a CMOS pixel array of an imaging system such as a camera. 
         [0036]    At step  604 , described in further detail below with reference to  FIG. 6A , one ore more most significant bits of the multiple bit digital value are generated by performing a successive approximation register (SAR) conversion on the analog voltage signal. In an embodiment, the SAR conversion circuitry  402  compares a sample of the analog voltage signal to comparison voltages (e.g., SAR comparison voltages with one SAR comparison voltage for each bit of the multiple bit digital value being determined using the SAR conversion process) to generate the bits, which corresponds to a SAR voltage level. 
         [0037]    At step  606 , described in further detail below with reference to  FIG. 6B , one or more least significant bits of the multiple bit digital value are generated by performing a ramp conversion on the analog voltage signal. In an embodiment, the ramp conversion circuitry  404  compares the analog voltage signal to at least one ramp of voltage levels that is based on the SAR voltage level, e.g., ramp voltage levels are added to the SAR voltage level to produce the comparison voltages. 
         [0038]      FIG. 6A  depicts a flow chart for performing the SAR generation step  604  ( FIG. 6 ). In an embodiment, the steps of  FIG. 6A  are performed for each bit of the multiple bit digital value being determined using the SAR conversion circuitry  402 , e.g., once to determine the MSB and subsequently to determine successive bits adjacent to the MSB. For example, if the multiple bit digital value is 12 bits and 6 bits are being determined using the SAR conversion circuitry, the steps of  FIG. 6A  would be performed 6 times. 
         [0039]    At step  610 , a SAR comparison voltage is generated. In an embodiment, the SAR comparison voltage is associated with one or more bit positions of the multiple bit digital value, e.g., the MSB and adjacent bits. For example, the first time the steps of  FIG. 6A  are performed the SAR comparison voltage is associated with the MSB position, the second time the steps of  FIG. 6A  are performed the SAR comparison voltage is associated with the MSB position and the bit positions adjacent the MSB, etc . . . . The SAR comparison voltage may be generated by the DAC  418  under control of the SAR control  414 . 
         [0040]    At step  612 , the analog voltage signal is compared to the generated SAR comparison voltage (e.g., by the SAR conversion circuitry  402 ) to determine a SAR voltage level. The SAR voltage level is effectively an approximation of the analog voltage signal that will be refined through repeated passes through the SAR conversion process (e.g., six times total if 6 bits are being determined) and, then, using the ramp conversion process. 
         [0041]    At step  614 , bit(s) are obtained, e.g., by the SAR conversion circuitry  402 , based on the SAR voltage level determination. In an embodiment, when obtaining the MSB, the MSB position is set to “1” if the analog voltage signal is greater than the SAR comparison voltage and the MSB position is set to “0” if the analog voltage signal is less than the SAR comparison voltage. When obtaining subsequent bit positions, the bit position being determined is set to “1” if the analog voltage signal is greater than the SAR comparison voltage and the bit position being determined is set to “0” if the analog voltage signal is less than the SAR comparison voltage. The set bit positions may be stored by SAR control  414  in the memory SAR  406 , e.g., for retrieval and use during subsequent passes through the SAR conversion process and for use during the ramp conversion process. If additional bit positions of the multiple bit digital value are to be determined using the SAR conversion process, processing proceeds at step  610  with the generation of a more refined comparison voltage. Otherwise, ramp conversion may be performed to determine the remaining bits of the multiple bit digital value. 
         [0042]      FIG. 6B  depicts a flow chart for performing the ramp conversion step  606 . In an embodiment, the ramp conversion process is performed to determine the remaining bits (i.e., one or more least significant bits) of the multiple bit digital value after the SAR conversion process. For example, if the multiple bit digital value is 12 bits and 6 bits are determined using the SAR conversion circuitry, the remaining 6 bits would be determined using the steps of  FIG. 6B . 
         [0043]    At step  620 , a voltage level ramp is generated such as voltage level ramp  454  ( FIG. 4A ). The voltage level ramp may be generated by ramp generator  420 . In an embodiment, during the SAR conversion process, Vramp is set to a zero voltage level by ramp generator  420 . 
         [0044]    At step  622 , a combined voltage level ramp is generated based on the SAR voltage level determined in steps  610 - 614  ( FIG. 6A ) and the voltage level ramp generated in step  622 . In an embodiment, SAR control  414  reads the bits obtained during the SAR conversion process from memory SAR  406  and sets the DAC  418  based on the determined bits to produce the SAR voltage level, which is combined with Vramp in a known manner to produce the combined voltage level ramp at the input  413   b  of the comparator  412  for comparison to the sample of the analog voltage signal. In an embodiment, the SAR control  414  may set the SAR voltage level as produced by the SAR conversion circuitry  402  prior to the first ramp portion within ramp  454 , which is then stored. Thereafter, the stored SAR voltage level may be used as a SAR preset at block  628  to preset the SAR voltage level prior to subsequent ramp portions. 
         [0045]    In one embodiment, the SAR control  414  reads the bits obtained during the SAR conversion process from memory and sets the DAC  418  prior to each positive and/or negative ramp within ramp  454 . In another embodiment, the SAR control  414  reads the bits obtained during the SAR conversion process from memory and sets the DAC  418  prior to the first ramp within ramp  454 , but not for subsequent ramps, to improve processing speed. 
         [0046]    At step  624 , the analog voltage signal is compared to the combined voltage level ramp, e.g., by comparator  412 . 
         [0047]    At step  626 , one or more least significant bits of the multiple bit digital value are obtained based on the comparison of the analog voltage signal to the combined voltage level. 
         [0048]      FIG. 6C  depicts a flow chart of steps for obtaining the least significant bits (step  626  of  FIG. 6B ). At step  630 , a counter value is generated, e.g., by counter  422 . Counter  422  may generate a counter value by selectively incrementing a counter output value. 
         [0049]    If ramp  454  includes a single increasing voltage level ramp, e.g., ramp  452   a,  the counter value of the counter  422  may increment for each step of the increasing voltage level ramp until the analog input is greater than the combined voltage level ramp. If ramp  454  includes a single decreasing voltage level ramp, e.g., ramp  452   b,  the counter value of the counter  422  may increment for each step of the decreasing voltage level ramp after the analog input is greater than the combined voltage level ramp. If the ramp  454  includes at least one increasing voltage level ramp and at least one decreasing voltage level ramp, the counter value of the counter  422  may increment for each step of the increasing voltage level ramp(s) until the analog input is greater than the combined voltage level ramp and for each step of the decreasing voltage level ramp(s) after the analog input is greater than the combined voltage level ramp. 
         [0050]    At step  632 , the least significant bits are obtained based on the generated counter value. In one embodiment, the least significant bits are the generated counter value. In accordance with this embodiment, the number of least significant bits may be equal to log 2 K plus log 2 L in which K is the number of steps in each ramp and L is the number of ramps. For example, if there are 16 steps in each ramp and there are four ramps, there would be 6 other bits determined using the generated counter value. (i.e., 4+2=6). Thus, this process yields additional bits (i.e., 2 extra bits in the illustrated example) for inclusion in the multiple bit digital value beyond the number of bits of resolution available based on simply the number of steps in each ramp. In another embodiment, the least significant bits are the generated counter value divided by the number of increasing and decreasing voltage level ramps within the ramp  454 . 
         [0051]    In one embodiment, the voltage level ramp includes at least one increasing voltage level ramp portion and at least one decreasing voltage level ramp portions and the SAR voltage level is set prior to a first of the increasing and decreasing voltage level ramp portions and is reset prior to subsequent ones of the increasing and decreasing voltage level ramp portions. In another embodiment, the SAR voltage level is set prior to a first of the increasing and decreasing voltage level ramp portions, but is not reset prior to subsequent ones of the increasing and decreasing voltage level ramp portions. This results in higher speed operation, but may not be as effective at reducing noise. Additionally, the analog voltage signal may be sampled/resampled prior to each increasing/decreasing voltage level ramp portion for improved noise characteristics or may be sampled prior to only the first voltage level ramp portion for improved speed characteristics. 
         [0052]    Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details without departing from the invention. For example, it is contemplated that other processes may be employed to determine other bits of the multiple bit digital value. In this case, the MSB and most significant bit(s) described herein will refer to the most significant bits determined using a SAR conversion process and the LSB and least significant bits described herein will refer to the least significant bit(s) determined using a ramp conversion process.