Abstract:
Disclosed herein is a video processing apparatus for performing video processing compatible with a dual link progressive scheme, said video processing apparatus including: two video processing circuits; and a control section.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a video processing apparatus and a video processing method for carrying out video processing compatible with the dual link progressive scheme. 
         [0003]    2. Description of the Related Art 
         [0004]    Heretofore, the video compositing equipment called effect switchers has been used by TV broadcasting stations and video editing studios to obtain a special effect called keying. Keying is a process whereby a key fill signal (i.e., a video signal superposed as a foreground onto a background image) is superposed onto the area designated by a key source signal (a video signal for designating the area on which to superpose the image, the area being one whose signal level is at least a predetermined threshold value) in the background image (a major video signal constituting the screen). 
         [0005]    Video processing including wipes is carried out by waveform generating means such as wipe key generators or pattern generators generating key signals. The key signals may be used to cut out two images inversely before compositing the two. In another example, no input image is cut out. Instead, internally generated signals (monochrome or multicolor) may be clipped using signal generated by the waveform generating means for use as images. 
         [0006]    The standard for the physical layer of 3G-SDI covering such requirements as signal amplitude and signal rise/fall time is defined by SMPTE (Society of Motion Picture and Television Engineers) 424M. The data formats and mapping requirements of 3G-SDI are standardized by SMPTE 425M. 
         [0007]    The data formats and mapping requirements defined by SMPTE 425M include a double speed scheme based on HD-SDI (1080p50/59.94/60), the scheme to convert 12-bit transmissions and dual link HD-SDI into 3G-SDI, and the scheme to convert dual HD-SDI arrangements into 3G-SDI. SMPTE 424M defines the electrical specifications of serial transmissions, as well as the requirements for arranging two data streams into a single data stream. As with SD-SDI and HD-SDI, the standardized items cover signal amplitude, rise/fall times, rise/fall time differences, DC offsets, and return losses. Some of the above-described aspects of the standards are discussed illustratively in Japanese Patent Laid-open Nos. 2000-197072 and 2007-13466. 
       SUMMARY OF THE INVENTION 
       [0008]    There are limits to the speed for the processing of signals by the devices making up circuitry. It may happen that a still higher speed of signal processing is either unavailable or is possible but with more costly devices (e.g., at least twice as expensive as ordinary types). This bottleneck may be bypassed by the dual link arrangement involving two sets of inexpensive devices amounting to a more economical solution. 
         [0009]    High-speed circuits have been known to pose problems specific to high-frequency circuits. As a result, these circuits have been difficult to implement in a circuit board setup. If the circuit board is designed with circuits operating at half the target speed, then the overall result is an appreciably inexpensive circuit board arrangement. 
         [0010]    For video signals, the interlace and progressive schemes exist as two standard signal formats. Where circuits that process the interlace format video signal are operated on a dual link connection, these circuits may be arranged also to process the progressive format video signal. This means that the same equipment and the same circuit boards can be used in two different signal formats depending on purpose, which translates into a significant savings in cost. 
         [0011]    It follows that circuit boards of one type need only be manufactured to deal with the two signal formats. Volume production of the circuit boards is helpful in reducing unit costs and attaining a further economy. 
         [0012]    In the past, two sets of the waveform processing means were needed to carry out video processing such as wipes in the dual link setup. That was because the waveform processing means constitute part of the above-mentioned processing circuit. 
         [0013]    As part of the dual link setup, the two waveform processing means were controlled exactly in the same manner to generate the same waveform. Consequently, one type of video processing performed on the interlace signal as shown in  FIG. 9A  was also carried out on the progressive signal. The video output that ultimately resulted turned out to be different from one frame to another, as illustrated in  FIG. 9B . 
         [0014]    That is, the video processing in keeping with the ordinary dual link arrangement involve two streams of exactly the same processing. That means the generated waveform has half the resolution in the vertical direction, which constitutes a significant detriment to image quality. 
         [0015]    The present invention has been made in view of the above circumstances and provides arrangements for implementing high-quality video processing such as wipes in the dual link setup. 
         [0016]    In carrying out the present invention and according to one embodiment thereof, there is provided a video processing apparatus for performing video processing compatible with a dual link progressive scheme, the video processing apparatus including: two video processing circuits configured to have waveform generating means each; and control means for controlling the two video processing circuits in operation; wherein, upon video processing of a given frame under a progressive scheme, the control means causes one of the two video processing circuits to operate at settings such that the waveform generating means thereof operates on a first field under an interlace scheme while causing the other video processing circuit to operate at settings such that the waveform generating means thereof operates on a second field under the interlace scheme. 
         [0017]    Preferably, upon video processing of an odd-numbered frame under the progressive scheme, the control means may cause one of the two video processing circuits to operate at settings such that the waveform generating means thereof operates on the first field under the interlace scheme while causing the other video processing circuit to operate at settings such that the waveform generating means thereof operates on the second field under the interlace scheme; and wherein, upon video processing of an even-numbered frame under the progressive scheme, the control means may cause one of the two video processing circuits to operate at settings such that the waveform generating means thereof operates on the second field under the interlace scheme while causing the other video processing circuit to operate at settings such that the waveform generating means thereof operates on the first field under the interlace scheme. 
         [0018]    According to another embodiment of the present invention, there is provided a video processing method for performing video processing compatible with a dual link progressive scheme, the video processing method including the steps of: controlling in operation two video processing circuits configured to have waveform generating means each; upon video processing of a given frame under a progressive scheme, causing one of the two video processing circuits to operate at settings such that the waveform generating means thereof operates on a first field under an interlace scheme; and causing the other video processing circuit to operate at settings such that the waveform generating means thereof operates on a second field under the interlace scheme. 
         [0019]    According to the present invention, as outlined above, video processing compatible with the dual link progressive scheme is provided. In operation, two video processing circuits having waveform generating means each are controlled. Upon video processing of a given frame under a progressive scheme, one of the two video processing circuits is operated at settings such that its waveform generation means operates on a first field under an interlace scheme. At the same time, the other video processing circuit is operated at settings such that its waveform generation means operates on a second field under the interlace scheme. The embodiment of the invention thus provides internally generated high-quality signals for the dual link setup and brings about high-quality video processing such as wipes. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The above and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the invention in conjunction with the accompanying drawings, in which: 
           [0021]      FIG. 1  is a block diagram showing a typical configuration of a dual link video processing system including an effect switcher according to an embodiment of the present invention; 
           [0022]      FIG. 2  is a block diagram showing a typical structure of the effect switcher; 
           [0023]      FIG. 3  is a schematic view showing how the generation of wipe waveforms is related to field signals; 
           [0024]      FIG. 4  is a schematic view showing a typical data structure of a dual link progressive (60P) scheme; 
           [0025]      FIG. 5  is a schematic view showing wipe signals needed on links A and B for accomplishing a diagonal wipe; 
           [0026]      FIGS. 6A ,  6 B and  6 C are schematic views showing how a first and a second field typically appear on links A and B when a diamond-shaped pattern is output on the screen; 
           [0027]      FIGS. 7A ,  7 B and  7 C are schematic views showing how the first and the second fields typically appear on links A and B when an image is generated with its diamond-shaped pattern protruding slightly from the angle of view; 
           [0028]      FIG. 8  is a schematic view showing a typical video output resulting ultimately from dual link-compatible video processing performed by the effect switcher on progressive signals; and 
           [0029]      FIGS. 9A and 9B  are schematic views showing a typical video output resulting ultimately from the dual link-compatible video processing carried out ordinarily on interlace signals. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0030]    The preferred embodiments of the present invention will now be described in reference to the accompanying drawings. Although the description below will contain many specificities, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. Many alternatives, modifications and variations will become apparent to those skilled in the art in light of the ensuing description, without departing from the scope of the invention. 
         [0031]    As shown in  FIG. 1 , the present invention is applied illustratively to an effect switcher  100  as part of a video processing system  5  which gets a first video processor  20 A and a second video processor  20 B to perform a wipe process on the video signals supplied on a dual link connection from a video reproducing apparatus  1  or from an imaging apparatus  2 , the processed video signals being output on the dual link connection to monitors  3  and  4 . 
         [0032]    In  FIG. 1 , reference characters CH 1  and CH 2  stand for digital special effect sections. These sections have circuits that receive input video signals and write the received signals to a memory. The written signals are subject to coordinate transformation and other processes with regard to the input screen before being formed into an image to be output. The processes involved include such special effects as enlarging, contracting, and deforming of images. As such, the digital special effect sections are not directly related to the structures or functions characterizing the present invention. Although this invention may be applied to an internal waveform generation circuit arrangement, the structures and the workings of such an arrangement are the same as those of the effect switcher to be described below. For that reason, the digital special effect sections will not be discussed further in this specification. 
         [0033]    As shown schematically in  FIG. 1 , input/output connections are arranged in such a manner that the first video processor  20 A performs processing on the side of link A and the second video processor  20 B effects processing on the side of link B. The second video processor  20 B is controlled in linkage with the workings of the first video processor  20 A, as shown by arrowed links. 
         [0034]    The effect switcher  100 , as shown in  FIG. 2 , includes a main unit  40  and a selection input section  60 . The main unit  40  contains: a matrix switcher  10  for selecting input video signals on input lines L 1  through L 9 ; the first video processor  20 A supplied with the video signals input on the input lines L 1  through L 9  through the matrix switcher  10 ; the second video processor  20 B fed with the video signals on the input lines L 1  through L 9  via the matrix switcher  10 ; and a controller  30  for controlling these components. The selection input section  60  is connected to the controller  40  of the main unit  40  by way of a communication channel  50 . 
         [0035]    In the effect switcher  100 , the video signals input on the input lines L 1  through L 9  include a key source signal and a key fill signal. 
         [0036]    The matrix switcher  10  is furnished with a key source intersection array  12 A made of switches connected to a key source signal selection input bus  11 A that supplies the first video processor  20 A with one of the video signals on the input lines L 1  through L 9  as a key source signal. The matrix switcher  10  is further provided with a key fill intersection array  14 A made of switches connected to a key fill signal selection input bus  13 A that supplies the first video processor  20 A with one of the video signals on the input lines L 1  through L 9  as a key fill signal. The matrix switcher  10  is also furnished with a first background intersection array  16 A made of switches connected to a first background signal selection input bus  15 A that supplies the first video processor  20 A with one of the video signals on the input lines L 1  through L 9  as a first background signal. The matrix switcher  10  is further provided with a second background intersection array  18 A made of switches connected to a second background signal selection input bus  17 A that supplies the first video processor  20 A with one of the video signals on the input lines L 1  through L 9  as a second background signal. The matrix switcher  10  is also furnished with a key source intersection array  12 B made of switches connected to a key source signal selection input bus  11 B that supplies the second video processor  20 B with one of the video signals on the input lines L 1  through L 9  as the key source signal. The matrix switcher  10  is further provided with a key fill intersection array  14 B made of switches connected to a key fill signal selection input bus  13 B that supplies the second video processor  20 B with one of the video signals on the input lines L 1  through L 9  as the key fill signal. The matrix switcher  10  is also furnished with a first background intersection array  16 B made of switches connected to a first background signal selection input bus  15 B that supplies the second video processor  20 B with one of the video signals on the input lines L 1  through L 9  as the first background signal. The matrix switcher  10  is further provided with a second background intersection array  18 B made of switches connected to a second background signal selection input bus  17 B that supplies the second video processor  20 B with one of the video signals on the input lines L 1  through L 9  as the second background signal. 
         [0037]    The first video processor  20 A is constituted by a key processing circuit  21 A and a compositing circuit  22 A. The key processing circuit  21 A is connected to the key source signal selection input bus  11 A and to the key fill signal selection input bus  13 A. The key source signal and the key fill signal selected from the video signals on the input lines L 1  through L 9  are input to the key processing circuit  21 A via the key source signal selection input bus  11 A and key fill signal selection input bus  13 A, respectively. The key processing circuit  21 A proceeds to generate a key signal reflecting control signals from the controller  30 , using the input key source signal or by means of an internal waveform generation circuit (i.e., wipe pattern generation circuit). The key processing circuit  21 A then feeds the generated key signal and the key fill signal to the compositing circuit  22 A. 
         [0038]    The compositing circuit  22 A is connected to the key processing circuit  21 A as well as to the first background signal selection input bus  15 A and second background signal selection input bus  17 A. The key signal and key fill signal are input to the compositing circuit  22 A from the key processing circuit  21 A. The first and the second background signals selected from the video signals on the input lines L 1  through L 9  are input to the compositing circuit  22 A via the first background signal selection input bus  15 A and second background signal selection input bus  17 A, respectively. The compositing circuit  22 A performs a keying process whereby the area designated by the key signal fed by the key processing circuit  21 A is replaced with the first or the second background signal in order to composite the key fill signal. 
         [0039]    The second video processor  20 B is constituted by a key processing circuit  21 B and a compositing circuit  22 B. The key processing circuit  21 B is connected to the key source signal selection input bus  11 B and to the key fill signal selection input bus  13 B. The key source signal and the key fill signal selected from the video signals on the input lines L 1  through L 9  are input to the key processing circuit  21 B via the key source signal selection input bus  11 B and key fill signal selection input bus  13 B, respectively. The key processing circuit  21 B proceeds to generate a key signal reflecting control signals from the controller  30 , using the input key source signal or by means of an internal waveform generation circuit (i.e., wipe pattern generation circuit). The key processing circuit  21 B then feeds the generated key signal and the key fill signal to the compositing circuit  22 B. 
         [0040]    The compositing circuit  22 B is connected to the key processing circuit  21 B as well as to the first background signal selection input bus  15 B and second background signal selection input bus  17 B. The key signal and the key fill signal are input to the compositing circuit  22 B from the key processing circuit  21 B. The first and the second background signals selected from the video signals on the input lines L 1  through L 9  are input to the compositing circuit  22 B via the first background signal selection input bus  15 B and second background signal selection input bus  17 B, respectively. The compositing circuit  22 B performs a keying process whereby the area designated by the key signal from the key processing circuit  21 B is replaced with the first or the second background signal in order to composite the key fill signal. 
         [0041]    In the foregoing paragraphs, the key signal was explained as a binary signal designating either the background signal or the key fill signal. More specifically, the key signal is not a binary signal representing two values but a multivalued signal denoting degrees of density. As such, the key signal designates one of the multiple degrees of density with which to superpose the key fill signal onto the background signal. This permits execution of a video process whereby the key signal appears to constitute a semitransparent area against a visible background. 
         [0042]    The controller  30  is composed of a microcomputer. In operation, the controller  30  generates control signals reflecting the selection input signals supplied by the selection input section  60  via the communication channel  50 . The control signals thus generated are sent through control lines  35  to the matrix switcher  10 , first video processor  20 A, and second video processor  20 B for operation control purposes. 
         [0043]    The selection input section  60  is made up of a microcomputer  65  connected with a button array section  61 , a keyboard  62 , a pointing device  63  such as a mouse, and a graphical display  64 . When buttons of the button array section  61  are operated for input selection, the matrix switcher  10  of the main unit works to select the paired inputs for sides A and B. For example, suppose that the input lines L 1  and L 2  carry the first video signal for links A and B respectively and that keys are operated to select the first video signal against the first background. In that case, the input line L 1  is selected on the first background intersection array  16 A and the input line L 2  is selected on the second background intersection array  16 B. The same operations are performed on the other paired inputs and intersection arrays. If the same apparatus is used to handle images under the interlace scheme, there is no need to switch the paired links; the switching need only be executed on a one-to-one basis with the operations that have been made. 
         [0044]    In the effect switcher  100 , the selection input section  60  gives instructions to carry out various processes by communicating with the controller  30  of the main unit  40  through the communication channel  50 . 
         [0045]    The compositing circuit  22 A has the background signals input from the first background signal selection input bus  15 A and second background signal selection input bus  17 A. Given an instruction from the selection input section  60 , the compositing circuit  22 A either uses the background signal from one of the two buses, or makes the two background signals composited in accordance with a compositing method designating a composite ratio, thereby generating a composited background signal for use in the keying process. The composite ratio may be designated manually by operation of a fader lever on the selection input section  60 . In the case of an automatic transition (automatic progression) operation, controls are exercised so that one background signal is replaced over time by the other background signal. For the effect of a mix, the compositing method above illustratively involves adding the two background signals to each pixel, with the signals weighted to reflect the above-mentioned ratio (e.g., if the ratio is 30%, then the first background signal multiplied by 0.3 and the second background signal multiplied by 0.7 are added up). An alternative compositing method for the effect of a wipe may involve superposing the second background signal onto the first background signal in a keying process using a wipe key signal supplied by a wipe key waveform generation circuit (WKG: wipe key generator)  26 A in  FIG. 2 . The key signal generated by the wipe key waveform generation circuit  6  varies with the above-mentioned ratio. In the case of automatic transition, the time “t” for progression is used as the input parameter in determining the boundary for the wipe. Where automatic transition is not in effect, the parameter “t” is replaced by a suitably designated ratio. The above-described workings also apply to the compositing circuit  22 B. 
         [0046]    In the foregoing paragraphs, two examples of waveform generation were explained: one taking place inside the key processing circuits  21 A and  21 B, and the other inside the WKG (i.e., inside the compositing circuits  22 A and  22 B). The relation between the field signal and the control over waveform generation is the same in the two examples, which is one characteristic of the embodiment of the invention. For this reason, the generated waveforms will be regarded as the wipe waveforms in the ensuing description. Either case of waveform generation can be executed in a manner compatible with the dual link progressive scheme (i.e., one of the effects of the embodiment of the present invention), as will be explained below. 
         [0047]      FIG. 3  schematically shows how the generation of wipe waveforms is related to field signals. Given an instruction to perform a wipe process from the selection input section  60 , the controller  30  of the main unit  40  upon video processing of a given frame under the progressive scheme causes the first video processing circuit  20 A to operate at settings such that the waveform generation section thereof (i.e., key processing circuit  21 A) operates on a first field under the interlace scheme while causing the second video processing circuit  20 B to operate at settings such that the waveform generation section thereof (i.e., key processing circuit  20 B) operates on a second field under the interlace scheme, whereby the wipe process compatible with the dual link progressive scheme is carried out. 
         [0048]    Under a typical dual link progressive (60P) scheme, of which a typical data structure is shown in  FIG. 4 , the array of signals (lines) sent through the second field (F=1) is different from that through the first field. This complicates dual stream processing. For example, if a diagonal wipe such as one shown in  FIG. 5  is desired to be performed, it is necessary to adjust the wipe signal on each of links A and B. Filed adjustment is further needed on link B. 
         [0049]    Suppose that a diamond-shaped pattern (wipe or key) is output on the screen as shown in  FIG. 6A . In this case, as shown in  FIGS. 6B and 6C  giving enlarged views of an apex of the diamond-shaped pattern, what appears in the first and the second fields for link A looks different from that for link B. In the first field, the image of link A precedes that of link B so that on the same line, the pattern width of link A is less than that of link B. In the second field, by contrast, the image of link B precedes that of link A so that the pattern width of link A is greater than that of link B on the same line. 
         [0050]    Suppose now that a diamond-shaped pattern protruding slightly from the angle of view is generated as shown in  FIG. 7A . In this case, as shown in  FIGS. 7B and 7C  giving enlarged views of an apex of the diamond-shaped pattern, the pattern subsequent to line  21  in the first field constitutes a video data area for both links A and B; the pattern on and before line  20  is invisible. In the second field, the data on link B constitutes a video data area from line  20  on. That means the pattern on line  20  remains visible. 
         [0051]    In the above-mentioned wipe process, the following hardware-based controls are exercised on the initial value “Pattern_Ramp_Init(slope_v)” of a RAMP waveform:
       Link A: field  2 =field  1 +(half the increment value)   Link B: field  1 =field  2 +(half the increment value)       
 
         [0054]    A Field Odd/Even (FLOE) signal is used for field recognition. In terms of hardware, the FLOE signal on the side of link B is inverted for field recognition purposes. The FLOE signal is a signal that specifies whether a given field is odd or even and is generated by a synchronizing signal generator inside the main unit  40 . The synchronizing signal generator supplies a VD signal and the FLOE signals ( FIG. 3 ) to the components involved. During progressive scheme processing, the FLOE signal is inverted per frame. Given the FLOE signal that is either inverted or not inverted, the same video processor is switched between two modes of operation, working on either the first field or the second field under the interlace scheme. Where the same apparatus is used to handle images under the interlace scheme, the inverting of the FLOE signal need only be halted. The blanking interval on the side of link B is enlarged by one line. 
         [0055]    Since the pattern is found protruding upward (line  20 ) in the example above, line  20  is subjected to a blank mask to truncate the protrusion. More specifically, since the wipe intrudes into the blanking area by one line in the second field on link B, the blinking area is enlarged by one line before being masked. This arrangement blocks the video signal from passing through, thereby removing the intruding signal. When the output video signal is fed to an apparatus that uses the blanking area for transmitting something other than images, the inventive arrangement protects the apparatus from getting adversely affected by the intruding signal. Compositing is accomplished without extraneous intrusions when the blanking area is applied before the waveforms are used inside the compositing circuits  22 A and  22 B for diverse composite processing or key signal generation. 
         [0056]    Where the wipe does not progress, the same first and second fields are repeated. Where the wipe progresses, the wipe boundary is defined simply as 
         [0000]    
       
      
       y=ax+b  
      
     
         [0000]    and that the boundary moves in keeping with time “t” in the relation defined as 
         [0000]    
       
      
       b=k−rt  
      
     
         [0057]    Because wipe progression is also controlled in units of fields under the interlace scheme, the wipe boundary is positioned by one of the two video processing circuits (on link A or B) using the expression 
         [0000]        x =( y−b )/ a    
         [0000]    which is obtained by inverting the expression 
         [0000]    
       
      
       y=ax+b  
      
     
         [0000]    where, 
         [0058]    y=0, 2, 4, 6, etc., (even-numbered lines) for the first field, and 
         [0059]    y=1, 3, 5, 7, etc., (odd-numbered lines) for the second field. 
         [0060]    In the dual link setup, the outputs from the two video processing circuits are composited to obtain an output image in which all lines (i.e., even-numbered and odd-numbered lines) have been suitably processed. At a given time “t,” the wipe boundary is acquired in such a manner that the relations defined as 
         [0000]    
       
      
       b=k−rt  
      
     
         [0000]    
       
      
       y=ax+b  
      
     
         [0000]    hold on all lines. 
         [0061]    If the wipe waveform is generated from the same value “t” (i.e., fader value) in the first and the second fields, the progression may be reduced by half or the even-numbered and odd-numbered lines may become misaligned. This bottleneck is circumvented by having the value “t” controlled in units of fields (in units of frames under the progressive scheme). Where the fader lever is manually operated, the value “t” to be used is not the same as the current time itself but a value proportional to the position of the fader lever. The transmission of the value from the fader lever is effected uninterruptedly in units of fields (in units of frames under the progressive scheme). 
         [0062]    With the effect switcher  100 , the above timing adjustments are carried out to provide video processing compatible with the dual link progressive scheme as shown illustratively in  FIG. 8 . This makes it possible to perform high-quality video processing such as wipes without changing the processed content of each frame. 
         [0063]    In the effect switcher  100 , upon video processing of an odd-numbered frame under the progressive scheme, the controller  30  may cause the first video processor  20 A to operate at settings such that the waveform generating means thereof (i.e., key processing circuit  21 A) operates on the first field under the interlace scheme while causing the second video processor  20 B to operate at settings such that the waveform generating means thereof (i.e., key processing circuit  21 B) operates on the second field under the interlace scheme. Also upon video processing of an even-numbered frame under the progressive scheme, the controller  30  may cause the first video processor  20 A to operate at settings such that the waveform generating means thereof (key processing circuit  21 A) operates on the second field under the interlace scheme while causing the second video processor  20 B to operate at settings such that the waveform generating means thereof (key processing circuit  21 B) operates on the first field under the interlace scheme. In this manner, the wipe processing compatible with the dual link progressive scheme is carried out. 
         [0064]    The inventive arrangements above eliminate the quality-related problems experienced in the past when the first video processor  20 A and the second video processor  20 B were controlled exactly in the same manner. The traditional control method caused the signals with their waveforms generated internally to affect the even-numbered and odd-numbered lines exactly the same way, leading to image quality degradation. According to the embodiment of the invention, by contrast, the signals whose waveforms are internally generated are arranged to affect the lines in a manner corresponding to the number of scanning lines inherent in the progressive scheme, whereby high-quality, value-added images are output. 
         [0065]    Furthermore, the blanking area may be subjected to appropriate mask controls so as to protect the area in question from quality deterioration. This makes it possible for the video signal to be used without hindrance by other apparatuses. 
         [0066]    In addition, the circuits of the interlace-scheme video processing apparatus may be partially supplemented, with few modifications, by adding circuits and controls to handle processes under the dual link progressive scheme as well. When a single apparatus can thus be switched between uses under the interlace scheme and under the dual link progressive scheme, the resulting cost savings can be significant. 
         [0067]    In the foregoing examples, the present invention was explained using a pair of video processors. Alternatively, the invention can also be applied advantageously to a plurality of pairs of video processors (i.e., the total processor count is an even number) established to handle complicated processes. 
         [0068]    The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2008-095447 filed in the Japan Patent Office on Apr. 1, 2008, the entire contents of which is hereby incorporated by reference. 
         [0069]    It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof.