Abstract:
An improved capacitor coupled floating gate drive circuit is revealed that provides an effective drive mechanism for a floating or high side switch without the use of level shifting circuits or magnetic coupling. The capacitor coupled floating gate drive circuit is an improvement over prior art capacitor coupled floating gate drive circuits in that the new circuit uses a positive current feedback mechanism to reject slowly changing voltage variations that cause unintentional switch state changes in prior art capacitor coupled floating gate drive circuits.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This is a continuation of application Ser. No. 11/684,754, filed 2007 Mar. 12, now abandoned, which was a division of application Ser. No. 10/944,588, filed 2004 Sep. 18, now abandoned. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The subject invention generally pertains to electronic power conversion circuits, and more specifically to high frequency, switched mode electronic power converters. 
   2. Description of Related Art 
     FIG. 1  illustrates a ZVS coupled inductor buck converter employing a simple capacitor coupled floating drive circuit for driving a high side power mosfet switch, M AUX . The floating drive circuit is powered by a floating bootstrap capacitor, C BOOT , that is charged through D BOOT  during the on time of the main switch, M MAIN . When the PWM drive signal for the main switch M MAIN  goes low the main switch turns off and the same PWM drive signal that turns off the main switch is transmitted via C AUX  to the input of the inverting gate driver IC, U AUX , forcing the output of the inverting gate driver IC, U AUX , to go high, turning on the auxiliary switch, M AUX . During this transition the source voltage of the auxiliary switch M AUX  is rising quickly, which forces the input to U AUX  low relative to the floating ground reference terminal of U AUX , due to the coupling capacitor C AUX  which, absent any change in the PWM drive signal, tries to hold the input terminal of U AUX  fixed with respect to primary circuit ground. The input signal to U AUX  is held low during the switching transition as a result of the voltage rise of the source of M AUX  during the switching transition after U AUX  initially changes state as a result of the drive signal provided to turn off the main switch. The clamp diodes at the input to U AUX  prevent the input voltage to U AUX  from exceeding the supply voltage rails of U AUX  and the resistor R AUX  limits the current in the clamp diodes to a current less than their maximum current rating during the switching transitions. 
   When the PWM drive signal to the main switch goes high, this same PWM gate drive signal is transmitted to the input of U AUX  by C AUX , which results in the output of U AUX  going low which turns off M AUX  at the same instant that M MAIN  is turned on. During the subsequent switching transition the source voltage of U AUX  falls rapidly, which forces the input to U AUX  high, relative to the floating ground reference terminal of U AUX , due to the coupling capacitor, C AUX , which, absent any changes in the PWM drive signal, tries to hold the input to U AUX  fixed with respect to the primary circuit ground. A high input signal to U AUX  results from the voltage fall of the source of M AUX  during the switching transition after U AUX  initially changes state as a result of the drive signal provided to turn on the main switch. The capacitor coupled floating drive circuit of  FIG. 1  works well when the source voltage of M AUX  does not change during the on time of M AUX . A drop in voltage at the source of M AUX  during the on time of M AUX  can turn off M AUX , which would be an undesirable result. 
     FIG. 1  illustrates a ZVS coupled inductor buck converter employing a simple floating drive circuit based on capacitor coupling to an inverting driver integrated circuit (IC), U AUX . This floating drive circuit works well where the input source voltage is invariant, but the circuit can change state if there are voltage variations of the input source during the time that the switch M AUX  is turned on causing erratic operation, power losses, and, in some cases, component failure. What is needed is a similar simple floating drive circuit that is tolerant of voltage variations of the input source. 
   OBJECTS AND ADVANTAGES 
   An object of the subject invention is to reveal a simple capacitor coupled gate drive circuit that is tolerant of voltage variations at the source terminal of the high side switch during the on time of the high side switch. 
   Further objects and advantages of my invention will become apparent from a consideration of the drawings and ensuing description. 
   These and other objects of the invention are provided by a novel simple capacitor coupled floating drive circuit that is tolerant of voltage variations at the terminals of the high side switch. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is illustrated by reference to the drawings. 
       FIG. 1  illustrates a ZVS coupled inductor buck converter with a capacitor coupled floating drive circuit according to the prior art. 
       FIG. 2  illustrates a ZVS active clamp flyback converter employing a capacitor coupled floating drive circuit according to the subject invention. 
       FIG. 3(   a ) illustrates a timing wave form for the main switch of the  FIG. 2  circuit according to the subject invention. 
       FIG. 3(   b ) illustrates a timing wave form for the auxiliary switch of the  FIG. 2  circuit according to the subject invention. 
       FIG. 3(   c ) illustrates a voltage wave form for the reset capacitor of the  FIG. 2  circuit according to the subject invention. 
       FIG. 3(   d ) illustrates a voltage wave form of the floating drive coupling capacitor of the  FIG. 2  circuit according to the subject invention. 
       FIG. 3(   e ) illustrates a current wave form of the floating drive coupling capacitor of the  FIG. 2  circuit according to the subject invention. 
       FIG. 4  illustrates a variation of the capacitor coupled floating drive circuit of  FIG. 2  according to the subject invention. 
       FIG. 5  illustrates a second variation of the capacitor coupled floating drive circuit of  FIG. 2  according to the subject invention. 
       FIG. 6  illustrates a dc transformer circuit employing a quarter bridge primary network together with three of the capacitor coupled floating drive circuits of the subject invention used to drive the three high side switches of the quarter bridge circuit. 
   

   SUMMARY 
   The subject invention reveals an improved capacitor coupled floating high side gate drive circuit for driving a high side transistor switch that is tolerant of variations in the reference voltage of the high side switch. 
   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 2  is a ZVS active clamp flyback converter employing an improved capacitor coupled floating digital logic and drive circuit, which adds a non-inverting buffer U AUX2  and a positive current feedback resistor R FB  to the capacitor coupled floating drive circuit of  FIG. 1 . The improved capacitor coupled floating drive circuit is powered by a bootstrap capacitor C BOOT  which is charged through a bootstrap diode D BOOT  during the on time of the main switch M MAIN . Although it may not be necessary, it is preferred that the input to U AUX2  be a Schmitt trigger input. A Schmitt trigger input is an input with a variable threshold voltage incorporating hysteresis, so that, when the input is high, the threshold voltage for a change of state is lower than the threshold voltage for a change of state when the input is low. The use of a Schmitt trigger input is typically without cost since these are readily available and no more expensive than standard input logic integrated circuits.  FIG. 3(   a ) illustrates the switch timing of the main switch M MAIN  in  FIG. 2  and  FIG. 3(   b ) illustrates the switch timing for the auxiliary switch M AUX  of  FIG. 2 . A turn off transition of the main switch M MAIN  begins when the PWM drive signal, a digital voltage source, changes from a high state to a low state. The same PWM drive signal for the main switch M MAIN  is transmitted to the input of U AUX2  through C AUX  and R AUX , which causes the output of U AUX2  to go low and the output of U AUX1  to go high, which turns on the auxiliary switch M AUX . When the auxiliary switch M AUX  is turned on, current at first flows into the capacitor, C RESET , through M AUX . After the switch M AUX  is turned on, the current in C RESET  drops until the current reaches zero and reverses direction and increases to a current equal in magnitude, but opposite in direction, to the C RESET  current at the beginning of the on time of M AUX . As a result of the current in C RESET , the voltage of C RESET  changes, as illustrated in  FIG. 3(   c ). As a result of the changing voltage in C RESET  the voltage at the source terminal of M AUX , during the on time of M AUX , also changes with the C RESET  voltage. There is a corresponding change in C AUX  voltage during the on time of M AUX , as illustrated in  FIG. 3(   d ), which creates a corresponding current in C AUX , as illustrated in  FIG. 3(   e ). The current in C AUX  also flows in R AUX  and R FB . Some of the C AUX  current flows in R AUX  and D CLAMP2 , as the C RESET  and C AUX  voltages rise during the on time of M AUX . During this time some of the current also flows in R FB , but there is no change of state of U AUX2  during this time period because both the input and output of U AUX2  remain in the low state. The current in C AUX  forces the input of U AUX2  lower, thereby forward biasing D CLAMP2 . Eventually the current in M AUX  and C RESET  reaches zero and reverses, at which time the current flowing in C AUX  also reverses and significant current no longer flows in R AUX , since the input impedance of U AUX2  is very high and current in R AUX  reverse biases D CLAMP2 . For a typical integrated circuit buffer the input resistance is in the range of teraohms (10 12  ohms) so that the current in R AUX  is zero, for all practical purposes, after the current in C RESET  reverses direction. The C AUX  current will flow in R FB  and the U AUX2  input voltage will rise due to the IR drop of R FB  after the current in C RESET  reverses direction. For a typical active clamp flyback converter the voltage change of the reset capacitor is larger, usually much larger, than the logic supply voltage, so that, without R FB , the voltage change of C RESET  and C AUX , when the switch M AUX  is on and the voltage of C RESET  and C AUX  are decreasing, is more than sufficient to cause U AUX2  to change state, which would result in the unintentional turn off of M AUX . With R FB  in place the current in C AUX  creates a rise in U AUX2  input voltage, but the rise in U AUX2  input voltage will be insufficient to cause a change of state in U AUX2 , unless the value of R FB  is too large. U AUX2  will change state if the U AUX2  input voltage reaches a threshold voltage, V Threshold . For a Schmitt input buffer with +5 volt logic supply voltage a typical minimum threshold voltage, V Threshold , is about 2.5 volts. The current in C AUX , I CAUX , depends on the rate of voltage change of C AUX , 
               ⅆ     V   CAUX         ⅆ   t       ,         
and is given by
 
               I   CAUX     =       C   AUX     *       ⅆ     V   CAUX         ⅆ   t           ,         
where C AUX  is the capacitance value of C AUX . The rate of voltage change of C AUX ,
 
               ⅆ     V   CAUX         ⅆ   t       ,         
is related to the rate of voltage change of C RESET ,
 
                 ⅆ     V   CRESET         ⅆ   t       ·       ⅆ     V   CAUX         ⅆ   t         ≤       ⅆ     V   CRESET         ⅆ   t             
and the equality applies when R FB =0, so that, in general
 
               ⅆ     V   CAUX         ⅆ   t       &lt;         ⅆ     V   CRESET         ⅆ   t       .           
The current in C RESET  is given by
 
               I   CRESET     =       C   RESET     *       ⅆ     V   CRESET         ⅆ   t           ,         
where IC RESET  is the current in C RESET  and C RESET  is the capacitance value of C RESET . The maximum rate of change of voltage for C RESET  and C AUX  will occur at maximum load and minimum line voltage and results in the maximum peak current, I PEAK , in M MAIN  and L ZVS , which can be determined from circuit component values, the maximum load, and the minimum line voltage. A maximum value for
 
             ⅆ     V   CRESET         ⅆ   t           
and
 
             ⅆ     V   CAUX         ⅆ   t           
can be determined based on I PEAK  and is given by
 
               ⅆ     V   CAUX         ⅆ   t       &lt;       ⅆ     V   CRESET         ⅆ   t       ≤         I   PEAK       C   RESET       .           
If the voltage drop in R FB  is always less than the U AUX2  input threshold voltage, V Threshold , then unintentional state changes of U AUX2  can be prevented. The voltage of R FB  is given by
 
               V   RFB     =         I   CAUX     *     R   FB       =         R   FB     *     C   AUX     *       ⅆ     V   CAUX         ⅆ   t         ≤       R   FB     *     C   AUX     *       ⅆ     V   CRESET         ⅆ   t         ≤         R   FB     *     C   AUX     *     I   PEAK         C   RESET             ,         
where V RFB  is the voltage of R FB  and R FB  is the resistance value of R FB . If R FB  were equal to zero then there could be no changes of state to U AUX2 , but this is undesirable since it is desired to change the state of M AUX , which requires that U AUX2  also change state. R FB  needs to be sufficiently small to reject U AUX2  changes of state due to C RESET  voltage drops during the on time of M AUX , but sufficiently large to enable intentional state changes of U AUX2  when the PWM drive source, which is a digital voltage source, changes state. During the on time of M AUX , in order to avoid unintentional turn off of M AUX , we must have V RFB &lt;V Threshold  which can be achieved if
 
             R   FB     &lt;           V   Threshold     *     C   RESET           I   PEAK     *     C   AUX         .           
As a numerical example, for a 150 watt off line active clamp flyback converter under development at the time of this writing, V Threshod =2.5 volts, I PEAK =3 amperes, C AUX =5 picofarads, and C RESET =220 nanofarads, so that R FB  must be less than 36 kiloohms. In the circuit under development R FB  must be larger than 3 kiloohms in order to provide a change of voltage greater than the threshold voltage at the U AUX2  input in response to a change of state of the PWM drive source. In the current example a R FB  value near the geometric mean of the minimum and maximum acceptable values can be chosen and reliable operation can be expected with ample margins. If the range of acceptable values of R FB  is too narrow or non-existent then the situation can be most easily remedied by increasing C RESET . Alternate remedies are increasing V Threshold  and reducing I PEAK , but both of the alternate remedies involve other consequences to the circuit operation and cost that may be unacceptable or much more difficult to achieve. Decreasing C AUX  increases both the minimum acceptable value of R FB  and increases the maximum acceptable value of R FB , so that decreasing C AUX  has no benefit to the problem of insufficient range of acceptable R FB  values.
 
   A turn on transition of the main switch M MAIN  begins when the PWM drive signal changes from a low state to a high state. The PWM drive signal is transmitted to the U AUX2  input via C AUX , which forces the output of U AUX2  to a high state and forces the output of U AUX1  to a low state, thereby turning off M AUX . During the turn on transition of M MAIN  the source voltage of M AUX  falls rapidly, which has the result of forcing the input of U AUX2  high, discharging C AUX  through R AUX  and D CLAMP3 , and reinforcing the change initiated by the change in state of the PWM drive signal. During the on time of M MAIN , the source voltage of M AUX  is held at the primary ground potential or zero volts for the duration of the on time of M MAIN . During the on time of M MAIN , there is no change in the M AUX  source voltage and no mechanism in play to cause an unintentional change of state in M AUX . 
     FIG. 4  illustrates an alternate arrangement of the capacitor coupled floating drive circuit of the subject invention wherein two inverting gates are used to provide the positive current feedback via R FB  and a non-inverting gate driver IC is used in place of the inverting gate driver IC of  FIG. 2 . Another alternate arrangement is illustrated in  FIG. 5 . In the  FIG. 5  arrangement two inverters are used with an inverting gate driver IC to achieve the same results achieved in the  FIG. 2  and  FIG. 4  circuits, except that the propagation delay of the  FIG. 5  circuit will be larger since there are three gates connected in series in  FIG. 5  versus two in series for  FIGS. 2 and 4 . 
     FIG. 6  illustrates the use of the capacitor coupled floating drive circuit in a quarter bridge dc transformer circuit, according to the subject invention. The capacitor coupled floating drive circuit revealed in  FIG. 2  is applied to the three high side switches in the quarter bridge primary switching network. The drive signal for the single low side switch M 2B  is used to provide the input for the M 1A  and M 1B  switches. An inverted low side drive source must be added, as shown, to provide the input drive signal for the M 2A  high side switch. The use of the capacitor coupled floating drive circuits of the subject invention in the quarter bridge primary switching network provides an inexpensive and reliable gate drive solution that is insensitive to voltage variations resulting from the charging and discharging of the circuits capacitors. 
   CONCLUSION, RAMIFICATIONS, AND SCOPE OF INVENTION 
   Thus the reader will see that an improved capacitor coupled floating drive circuit can be formed by providing a novel positive current feedback mechanism that results in the rejection of slowly varying currents that could otherwise cause an unintentional change in state of a high side switch. 
   While my above description contains many specificities, these should not be construed as limitations on the scope of the invention, but rather, as exemplifications or preferred embodiments thereof. Many other variations are possible. For example, many other digital networks that provide a similar positive current feedback mechanism for a capacitor coupled floating drive circuit are possible. 
   Accordingly, the scope of the invention should be determined not by the embodiments illustrated, but by the appended claims and their legal equivalents.