Abstract:
The present disclosure provides a method and apparatus for parallel filtering. The apparatus comprises: a multi-granularity memory, a data cache device, a coefficient buffer broadcast device, a vector operation device and a command queue device. The multi-granularity memory is configured to store data to be filtered, filter coefficients and filtering result data. The data cache device is configured to cache, read and update the data to be filtered. The coefficient buffer broadcast device is configured to cache and broadcast the read filter coefficients. The command queue device is configured to store and output a queue of operation commands for the parallel filtering operation. The vector operation device is configured to perform a vector operation based on the data to be filtered and the output coefficient data, and write an operation result into the multi-granularity filtering result storage unit. The apparatus and method have a fast filtering speed, a smaller number of accesses, an improved usage efficiency, a reduced power consumption and a wide application scope.

Description:
TECHNICAL FIELD 
       [0001]    The present disclosure relates to signal processing technology, and more particular to a method for parallel filtering and a circuit implementation thereof in integrated circuit design. 
       BACKGROUND 
       [0002]    Image filtering is indispensable for images having low signal to noise ratio obtained in signal processing systems such as image processing systems. 
         [0003]    Currently there are mainly two types of filtering methods. The first type of methods use programmable devices such as FPGA, CPLD and the like, and design filters specific to different application scenarios. Such methods provide some level of real time capability, but cannot achieve a high dominant frequency or have diversified functions due to inherent weakness of the programmable devices. As an example, the patent document (application No. 200310105132) discusses how to implement two-dimensional (2D) filtering using CPLD and single chip microcomputer. This method is based on a 5*5 filtering template, and can be executed in real time. However, when the size of the filtering template is changes, the overall structure has to be redesigned. This method is not flexible or modular. Further, the operating frequency 10M is low. 
         [0004]    The second type of methods use specific DSP or ASIC chips. An image is stored in the form of data array in a memory, and the chips filter the image by processing the data array in the memory. Such methods incur heavy access overhead and are inefficient in filtering operation, because conventional signal processors require repeated loading of data to be filtered. 
         [0005]    In the scope of the second type of methods, the present disclosure provide an optimized parallel filtering method and designs a structure for filtering operation by using vector operational components according to the method. 
       SUMMARY 
       [0006]    To address one or more problems with the above conventional technology, the present disclosure provides a method and apparatus for parallel filtering. The present disclosure is applicable to various filtering operations, and enables sufficient parallelization of filtering operation by combining “data cache and coefficient broadcast” mechanism and a parallel operational component having diversified operational modes. 
         [0007]    In an aspect of the present disclosure, an apparatus for parallel filtering is provided. The apparatus comprises: a multi-granularity memory  10 , a data cache device  20 , a coefficient buffer broadcast device  30 , a vector operation device  40  and a command queue device  50 . 
         [0008]    The multi-granularity memory  10  is configured to store data to be filtered and filter coefficients, which are read from a matrix of data to be filtered and a matrix of filter coefficients, respectively, for parallel filtering operation, and filtering result data obtained after the filtering operation. The multi-granularity memory  10  comprises a multi-granularity to-be-filtered data storage unit  101 , a multi-granularity filter coefficient storage unit  102  and a multi-granularity filtering result storage unit  103 . 
         [0009]    The multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filter coefficient storage unit  102  each have a read/write bit width, denoted as BS, identical to an operational size of the vector operation device  40 . 
         [0010]    The data cache device  20  is configured to cache the data to be filtered as read from the multi-granularity to-be-filtered data storage unit  101 , and read and update the cached data. The data cache device  20  comprising a data cache body  201  and a data buffer control unit  202 . 
         [0011]    The coefficient buffer broadcast device  30  is configured to cache the filter coefficients as read from the multi-granularity filter coefficient storage unit  102 , and broadcast the cached data by duplicating the cached data into BS copies to obtain output coefficient data  3001  having a width of BS data elements. The coefficient buffer broadcast device  30  comprises a coefficient buffer entity  301  and a plurality of coefficient buffer control units: a read control logic unit  302 , an initialization logic unit  303  and an update logic unit  304 . 
         [0012]    The command queue device  50  is configured to store and output to the vector operation device  40  a queue of operation commands for the parallel filtering operation. 
         [0013]    The vector operation device  40  is configured to perform a vector operation based on the data to be filtered as read from the data cache device  20  and the output coefficient data  3001  as read from the coefficient buffer broadcast device  30 , and write an operation result into the multi-granularity filtering result storage unit  103 . 
         [0014]    In another aspect of the present disclosure, a method for parallel filtering is provided. The method comprises: 
         [0015]    Step  1 ): reading a number, BS, of data to be filtered from a data cache device  20  and a number, BS, of output coefficient data from a coefficient buffer broadcast device  30 , the BS data to be filtered being first data of first BS rows in a matrix of data to be filtered, while, in a signal set  4004  for a vector multiplier and accumulator device  40 , a read data buffer enabling signal is valid, a column number in a read data buffer column number signal corresponds to a column number of the read data and a read data buffer in-column offset signal is valid, a read coefficient buffer enabling signal  4007  is valid, and a data to be filtered  4001  and output coefficients  4002  are read at an input terminal of the vector multiplier and accumulator device  40 ; 
         [0016]    Step  2 ): multiplying, at a vector multiplier unit  401 , the read output coefficients with the data to be filtered, respectively; 
         [0017]    Step  3 - 1 ): adding a multiplication result obtained in Step  2 ) to a current value in a vector accumulating register unit  403  and then proceeding with Step  4 ); 
         [0018]    Step  3 - 2 ): determining, while performing Step  3 - 1 ), whether the output coefficient data currently read from the coefficient buffer broadcast device  30  is the last output coefficient or not, and if so, updating the coefficient buffer broadcast device  30  and then proceeding with Step  4 ); otherwise proceeding with Step  4 ) directly; 
         [0019]    Step  4 ): determining whether a current number of operations equals to a size of a matrix of filter coefficients, and if so, proceeding with Step  6 ); otherwise proceeding with Step  5 ); 
         [0020]    Step  5 ): incrementing a counter of a number of times the data cache device  20  or the coefficient buffer broadcast device  30  has been read by 1 and returning to Step  1 ); 
         [0021]    Step  6 ): writing, by an operation control logic unit  404  of the vector multiplier and accumulator device  40 , BS filtering, results currently obtained back into a multi-granularity filtering result storage unit  103  and transmitting a shift signal to the coefficient buffer broadcast device  30 ; 
         [0022]    Step  7 ): processing other data in the first BS rows in the matrix of data to be filtered similarly in accordance with Steps  1 )- 6 ); and 
         [0023]    Step  8 ): initializing the data cache device  20  and the coefficient buffer broadcast device  30 , and processing other data in the matrix of data to be filtered similarly in accordance with Steps  1 )- 7 ), until all the data in the matrix of data to be filtered have been processed. 
         [0024]    With the present disclosure, the parallelism size of the operations required in the filtering algorithm can be increased since BS operations can be performed simultaneously. That is, one filter coefficient is used each time and, after coefficient broadcast, participates in the operation with BS data to be filtered. After K*K operations, BS filtering results can be obtained according to the present disclosure. In contrast, only one filtering result can be obtained in this case when the conventional method is applied. 
         [0025]    Further, the present disclosure has the following advantageous effects: 
         [0026]    1): Fast filtering speed. Since the vector multiplier and accumulator device  40  having an operational size of BS is adopted, for every K 2  operations, BS 2D matrices of filtering result data can be obtained. That is BS times faster than the conventional implementation. 
         [0027]    2): Reduced number of accesses and improved data usage efficiency. According to the present disclosure, the data cache device  20  and the coefficient buffer broadcast device  30  cache the data read from the multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filtering result storage unit  102 , so as to reduce the number of storage accesses, reduce the power consumption and improve the data usage efficiency. 
         [0028]    3): Wide application scope. By extending the functionality of the vector multiplier and accumulator device  40 , various filtering odes can be supported, so as to extend the application scope of the present disclosure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0029]      FIG. 1  is a schematic diagram showing a principle of a 2 filtering algorithm; 
           [0030]      FIG. 2  shows an apparatus for parallel filtering according to an embodiment of the present disclosure; 
           [0031]      FIG. 3  is a schematic diagram showing data distribution of a matrix D of data to be filtered in a multi-granularity to-be-filtered data storage unit  101  according to an embodiment of the present disclosure; 
           [0032]      FIG. 4  is a schematic diagram showing data distribution of a matrix T of filter coefficients in a multi-granularity filter coefficient storage unit  102  according to an embodiment of the present disclosure; 
           [0033]      FIG. 5  is a block diagram showing a structure of a coefficient buffer broadcast device  30  according to an embodiment of the present disclosure, as well as data distribution of filter coefficients in a buffer entity  301 ; 
           [0034]      FIG. 6  is a schematic diagram showing data distribution of some elements of a matrix D of data to be filtered in a data cache device according to an embodiment of the present disclosure; 
           [0035]      FIG. 7  is a block diagram showing a structure of a vector multiplier and accumulator device  40  according to an embodiment of the present disclosure; and 
           [0036]      FIG. 8  is a flowcharting illustrating a process for calculating BS filtering results according an embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0037]    In the following, the present disclosure will be further explained with reference to the figures and specific embodiments so that the objects, solutions and advantages of the present disclosure become more apparent. 
         [0038]    First of all, the fundamental theory of the filtering operation according to an embodiment of the present disclosure will be introduced with reference to an example of 2D filtering. 
         [0039]    In a 2D filtering operation, it is generally assumed that a filter template matrix is H having a size of K*K, where K=2a+1. For an input matrix X having a size of M*N, each element Y(i, j) in the operation result matrix can be calculated according to the following equation: 
         [0000]        Y ( i,j )=Σ s=−a   a Σ t=−a   a   H ( s,t ) X ( i+s,j+t )  (1)
 
         [0040]    where a has a typical value of 1, 2 or 5, i.e., the size of the filter template matrix is 3*3, 5*5 or 7*7. 
         [0041]      FIG. 1  is a schematic diagram showing a principle of a 2D filtering algorithm. As shown in  FIG. 1 , in order to obtain a particular point in the operation result matrix Y, a matrix consisting of a point at the corresponding position in the input matrix X and the points surrounding it is multiplied with the respective points in the filter template matrix H and then accumulated. 
         [0042]    The amount of calculation in the  2   t  filtering varies for different filter templates. Generally, for a K*K filter template, K 2  multiplications and K 2  additions plus an M*N input matrix are required to calculate each filtering result. Accordingly, the amount of calculation required for the entire filtering algorithm is 2MNK 2 . That is, the 2D filtering is a calculation intensive algorithm. 
         [0043]      FIG. 2  shows an apparatus for parallel filtering according to an embodiment of the present disclosure. As shown in  FIG. 2 , the apparatus for parallel filtering includes a multi-granularity memory  10 , a data cache device  20 , a coefficient buffer broadcast device  30 , a vector operation device  40  and a command queue device  50 . 
         [0044]    The multi-granularity memory  10  is configured to store data to be filtered and filter coefficients, which are read from a matrix of data to be filtered and a matrix of filter coefficients, respectively, for parallel filtering operation, and filtering result data obtained after the filtering operation. Here, the multi-granularity memory  10  generally includes a multi-granularity to-be-filtered data storage unit  101 , a multi-granularity filter coefficient storage unit  102  and a multi-granularity filtering result storage unit  103 . 
         [0045]    The multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filter coefficient storage unit  102  each have a read/write bit width, denoted as BS, identical to an operational size of the vector operation device  40 . 
         [0046]    The multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filter coefficient storage unit  102  are existing memories capable of supporting multi-granularity parallel reading/writing. For their detailed descriptions, reference can be made to Chinese Patent Application No. 201110459453.7, entitled “Multi-granularity Parallel Storage System”, and Chinese Patent Application No. 201110460585.1, entitled “Multi-granularity Parallel Storage System and Memory”. 
         [0047]    The data cache device  20  is configured to cache the data to be filtered as read from the multi-granularity to-be-filtered data storage unit  101 , and read and update the cached data. Here, the data cache device  20  includes a data cache body  201  and a data buffer control unit  202 . 
         [0048]    The data cache device  20  is an existing cache device. For details regarding the structure of this cache device, reference can be made to Chinese Patent Application No. 201110443425.6, entitled “Apparatus for Providing Data to Be Filtered”. 
         [0049]    The coefficient buffer broadcast device  30  is configured to cache the filter coefficients as read from the multi-granularity filter coefficient storage unit  102 , and broadcast the cached data by duplicating the cached data into BS=4 copies to obtain output coefficient data  3001  having a width of 4 data elements. Here, the coefficient buffer broadcast device  30  includes a coefficient buffer entity  301  and a plurality of coefficient buffer control units: a read control logic unit  302 , an initialization logic unit  303  and an update logic unit  304 . 
         [0050]    The command queue device  50  is configured to store and output to the vector operation device  40  a queue of operation commands for the parallel filtering operation. 
         [0051]    The vector operation device  40  is configured to perform a vector operation based on the data to be filtered as read from the data cache device  20  and the output coefficient data  3001  as read from the coefficient buffer broadcast device  30 , and write an operation result into the multi-granularity filtering result storage unit  103 . The vector operation device  40  is capable of performing one or more vector operations simultaneously. 
         [0052]    In operation, the apparatus for parallel filtering first reads the data to be filtered in the matrix of data to be filtered from the multi-granularity to-be-filtered data storage unit  101  in columns and caches it in the data cache device  20 , while reading the filter coefficients in the matrix of filter coefficients from the mufti-granularity filter coefficient storage unit  102  in columns and caching them in the coefficient buffer broadcast device  30 . After the above data loading, the vector operation device  40  starts to operate. It reads the data to be filtered from the data cache device  20 , reads the output coefficient data  3001  that has been broadcasted from the coefficient buffer broadcast device  30 , and then performs the filtering operation on the read data based on the operation commands from the command queue device  50  and writes the operation result into the multi-granularity filtering result storage unit  103 . 
         [0053]    As described above, the operational size of the vector operation device  40  is identical to the read/write bit width of the multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filter coefficient storage unit  102 . That is, the vector operation device  40  can perform S operations concurrently and can write BS operation results into the multi-granularity filtering result storage unit  103  at a time. In fact, the BS operation results are filtering operations for the first elements in the first BS rows of the matrix of data to be filtered. Similarly, the other elements of the first BS rows can be processed in pipeline. Then, the data cache device  20  and the coefficient buffer broadcast device  30  can be re-initialized to obtain the filtering results for elements in other rows of the matrix of data to be filtered, and write them back into the multi-granularity filtering result storage unit  103 . 
         [0054]    In an embodiment of the present disclosure, the filtering operation is 2D filtering. In this case, the vector operation device  40  is a vector multiplier and accumulator device. The read/write bit width of the multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filtering result storage unit  103 , or the operational size of the vector multiplier and accumulator device  40 , is S=4. The matrix of data to be filtered is a 17*9 matrix and the matrix T of filter coefficients is a 3*3 matrix, as follows: 
         [0000]    
       
         
           
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         [0055]      FIGS. 3 and 4  show data distribution of the matrix D of data to be filtered in the multi-granularity to-be-filtered data storage unit  101  and data distribution of the matrix T of filter coefficients in the multi-granularity filter coefficient storage unit  102 , respectively. Here, the multi-granularity to-be-filtered data storage unit  101  and the multi-granularity filter coefficient storage unit  102  each have a read/write granularity parameter g=1 and a read/write bit width W=4. That is, the storage unit can read/write 4 data each time. As can be seen in  FIG. 3 , the data in every four rows of the matrix D of data to be filtered are placed to the respective storage block of the multi-granularity to-be-filtered data storage unit  101  in sequence, such that every BS=4 rows of data can be read out in columns. Also, as can be seen in  FIG. 4 , the matrix T of filter coefficients is stored in the multi-granularity filter coefficient storage unit  102  in columns, such that all the data in the matrix T of filter coefficients can be obtained by reading the multi-granularity filter coefficient storage unit  102  in columns for three times. 
         [0056]    Before explaining the distribution of the filter coefficients in the coefficient buffer broadcast device  30 , the respective components of the coefficient buffer broadcast device  30  will be introduced first. As shown in  FIG. 5 , the coefficient buffer broadcast device  30  includes a coefficient buffer entity  301  and a plurality of coefficient buffer control units: a read control logic unit  302 , an initialization logic unit  303  and an update logic unit  304 . 
         [0057]    Here, the coefficient buffer entity  301  is configured to cache the filter coefficients in the matrix T of filter coefficients. It has a size of 2BS data elements. When BS=4, the size of the coefficient buffer entity  301  is 8 data elements. 
         [0058]    The read control logic unit  302  is configured to control an operation to read the coefficient buffer entity  301 . 
         [0059]    The initialization logic unit  303  is configured to initialize the coefficient buffer entity  301 , i.e., to read the respective filter coefficients from the multi-granularity filter coefficient storage unit  102  and store them in the coefficient buffer entity  301 , when an initialization start signal  3007 , which is an input signal to the coefficient buffer broadcast device  30 , becomes valid. 
         [0060]    The update logic unit  304  is configured to read, when the coefficient buffer entity  301  is not sufficient for holding all the filter coefficients in the multi-granularity filter coefficient storage unit  102 , excessive filter coefficients from the multi-granularity filter coefficient storage unit  102  and store them in the coefficient buffer entity  301 . 
         [0061]    The input signal to the coefficient buffer broadcast device  30  includes: a read enabling signal  3002 , a filter coefficient number indicator signal  3003 , the data  3005  read from the multi-granularity to-be-filtered data storage unit  101  by the initialization logic unit  303  or the update logic unit  304 , an update signal  3006  transmitted from the vector multiplier and accumulator device  40  to the coefficient buffer broadcast device  30 , and the initialization start signal  3007 . The output signal includes: a read request, read granularity and read address signal  3004  from the initialization logic unit  303  or the update logic unit  304  to the multi-granularity to-be-filtered data storage unit  101 , and the output coefficient data  3001  obtained by broadcasting the data read from the coefficient buffer entity  301 , i.e., by duplicating it into BS=4 copies, by the read control logic unit  302 . The output coefficient data  3001  has a width of four data elements. 
         [0062]    With the above components, the coefficient buffer broadcast device  30  achieves the following functions: 
         [0063]    1): Each time the coefficient buffer broadcast device  30  is read, a broadcast result for one data element can be obtained (i.e., the data element is duplicated into BS copies) and transmitted to the operation device. 
         [0064]    2) The coefficient buffer broadcast device  30  can be read multiple times at periods equal to the number of filter coefficients, so as to return data elements periodically. 
         [0065]    3) When the buffer entity  301  is not sufficient for holding all the filter coefficients, the update logic unit  304  can update the values of the buffer entity  301  for the filtering operation by the vector multiplier and accumulator device  40 . 
         [0066]      FIG. 5  also shows data distribution of the filter coefficients in the buffer entity  301  when the coefficient buffer broadcast device  30  has been initialized. As shown in  FIG. 5 , the coefficient buffer broadcast device  30  has a size of 8 data elements, and the number of data elements included in the matrix T of filter coefficients is 9. Hence, in operation, the vector multiplier and accumulator device  40  needs to transmit the update signal to the coefficient buffer broadcast device  30  to update the coefficient buffer broadcast device  30  and then read the remaining filter coefficients for storing in the buffer entity  301  of the coefficient buffer broadcast device  30 . 
         [0067]      FIG. 6  shows data distribution of some elements of the matrix D of data to be filtered in the data cache device  20  when the initialization for the data cache device  20  to load the data in rows 1˜4 of the matrix D of data to be filtered has completed according to an embodiment of the present disclosure. As can be seen in  FIG. 6 , in the data cache device  20 , the data cache body includes an upper region  211 , a lower region  213  and a main region  212 . The data to be filtered is distributed over columns 2˜5 of the main region  212 . The first columns of the upper region  211 , the lower region  213  and the main region  212  are boarder elements required for filtering a particular point in the filtering operation. 
         [0068]      FIG. 7  is a block diagram showing the structure of the vector multiplier and accumulator device  40  according to an embodiment of the present disclosure. As shown in  FIG. 7 , the vector multiplier and accumulator device  40  includes a vector multiplier unit  401 , a vector adder unit  402 , a vector accumulating register unit  403  and an operation control logic unit  404 . 
         [0069]    The vector multiplier unit  401  and the vector adder unit  402  each have an operational size of BS=4 data elements and the vector accumulating register unit  403  can store BS=4 result values. 
         [0070]    The input signal to the vector multiplier and accumulator device  40  includes: the data to be filtered  4001  as read from the data cache device  20  and the output coefficient data  4002  (i.e., the output coefficient data  3001  as mentioned above) as read from the coefficient buffer broadcast device  30 , each having a width of BS=4 data elements. 
         [0071]    The operation control logic unit  404  is configured to transmit to the data cache device  20  an initialization start signal  4003  comprising a signal set  4004 , including a read data buffer enabling signal, a read data buffer column number signal and a read data buffer in-column offset signal, and a column shift signal  4005 , transmit to the coefficient buffer broadcast device  30  an initialization start signal  4006  (i.e., the initialization start signal  3007  as mentioned above), a read coefficient buffer enabling signal  4007  and an update signal  4008  (i.e., the update signal  3006  as mentioned above), and write the filtering result back into the multi-granularity filtering result storage unit  103 . Further, the signal  4009  is a signal set indicating a granularity signal, data and address at which the filtering result is written into the multi-granularity filtering result storage unit  103 . 
         [0072]    The vector multiplier and accumulator device  40  operates as follows. 
         [0073]    First, it reads the data from the data cache device  20  and the coefficient buffer broadcast device  30  as operands for multiplying operation by the vector multiplier unit  401 . 
         [0074]    Then, it adds an operation result at the vector multiplier unit  401  to a current value at the vector accumulating register unit  403  by using the vector adder unit  402 . 
         [0075]    Finally, it generates and writes every BS=4 filtering results back into the multi-granularity filtering result storage unit  103  under control of the operation control logic unit  404 . 
         [0076]      FIG. 8  is a flowcharting illustrating a process for calculating BS filtering results according an embodiment of the present disclosure. The transition to each branch in the flowchart is controlled by the operation control logic unit  404 . As can be seen in  FIG. 8 , the process for calculating BS filtering results includes the following steps. 
         [0077]    Step  1 ): A number, BS, of data to be filtered are read from a data cache device  20  and a number, BS, of output coefficient data are read from a coefficient buffer broadcast device  30 . The BS data to be filtered are the first data of first BS rows in a matrix of data to be filtered. 
         [0078]    Here, BS=4 data to be filtered can be read from the data cache device  20  and 4 identical output coefficient data, obtained by broadcasting one filter coefficient, can be read from the coefficient buffer broadcast device  30 . 
         [0079]    Referring to  FIG. 7 , meanwhile the vector multiplier and accumulator device  40  operates such that: in a signal set  4004 , a read data buffer enabling signal is valid, a column number in a read data buffer column number signal corresponds to a column number of the read data and a read data buffer in-column offset signal is valid, and a read coefficient buffer enabling signal  4007  is valid. A data to be filtered  4001  and output coefficients  4002  are read at an input terminal of the vector multiplier and accumulator device  40 . 
         [0080]    Step  2 ): At a vector multiplier unit  401 , the read output coefficients are multiplied with the BS=4 data to be filtered, respectively. 
         [0081]    Step  3 - 1 ): A multiplication result obtained in Step  2 ) is added to a current value in a vector accumulating register unit  403 . Then the process proceeds with Step  4 ). 
         [0082]    Step  3 - 2 ): While performing Step  3 - 1 ), it is determined whether the output coefficient data currently read from the coefficient buffer broadcast device  30  is the last output coefficient in the coefficient buffer broadcast device  30  or not, i.e., whether i=8. If so, the coefficient buffer broadcast device  30  is updated, i.e., the update signal  4008  is controlled to be valid by the operation control logic unit  404  and then the process proceeds with Step  4 ). Otherwise, i.e., when it proceeds with Step  4 ) directly. 
         [0083]    Step  4 ): It is determined whether a current number of operations equals to a size of a matrix of filter coefficients. If so, all the filter coefficients have been to multiplied with the respective data to be filtered and BS=4 filtering results have been obtained, and then the process proceeds with Step  6 ). When the current number of operations does not equal to the size of the matrix of filter coefficients, the process proceeds with Step  5 ). 
         [0084]    Step  5 ): A counter of a number of times the data cache device  20  or the is coefficient buffer broadcast device  30  has been read is incremented by 1 and the process returns to Step  1 ). 
         [0085]    Step  6 ): In this case, the output terminal of the vector multiplier and accumulator device  40  operates such that: the operation control logic unit  404  writes BS filtering results currently obtained back into a multi-granularity filtering result storage unit  103  and transmits a shift signal to the coefficient buffer broadcast device  30  to cause the column shift signal  4005  to be valid. 
         [0086]    With the above steps, the present disclosure can obtain the first data in the first BS=4 rows of the matrix of filtering results and write the to the specified addresses. Then, the other data in the first BS=4 rows can be processed in a pipeline. 
         [0087]    Step  7 ): The other data in the first BS rows in the matrix of data to be filtered are processed similarly in accordance with Steps  1 )- 6 ). 
         [0088]    The rows 1˜4 in the matrix of data to be filtered have been filtered above. Then, the data cache device  20  and the coefficient buffer broadcast device  30  need to be re-initialized to process the rows 5˜8 and other rows in the matrix of data to be filtered according to the process shown in  FIG. 8  as described above, until all the data in the matrix of data to be filtered have been processed. That is: 
         [0089]    Step  8 ): The data cache device  20  and the coefficient buffer broadcast device  30  are initialized to process other data in the matrix of data to be filtered similarly in accordance with Steps  1 )- 7 ), until all the data in the matrix of data to be filtered have been processed. 
         [0090]    In the above process, it is assumed that BS=4 as an example. However, it can be appreciated by those skilled in the art that the present disclosure is not limited to the scenario where BS=4. Accordingly, the present disclosure also applies to other 2D filtering methods and apparatuses in which the respective widths of the multi-granularity memory, the vector multiplier and accumulator device, the coefficient buffer broadcast device and the data cache device vary synchronously. 
         [0091]    Further, the present disclosure is not limited to 2D filtering, but also applies to operations having the following features: 
         [0092]    1. The objects of the operation are an input signal matrix and an input coefficient matrix. Here the input coefficient matrix is typically represented in a regular structure, such as a rectangular window or a cross window. 
         [0093]    2. The operation has such a feature that an output result for each point is an operation result obtained by operating the input coefficient matrix window and the corresponding part of the input signal matrix. Then the operation is applied to the input matrix on a per point basis, until the entire operation result matrix is obtained. 
         [0094]    3. There can be various forms of operations for the input coefficient matrix window and the corresponding part of the input signal matrix. For example, in a 2D filtering structure, the form of operation can be such that corresponding elements in the input matrix window are multiplied with each other and then the respective multiplication results are accumulated to obtain a filtering result for one point. In a Sum of Absolute Difference (SAD) operation in image processing, the form of operation can be such that a difference between corresponding elements in the input matrix window is calculated, then the absolute value of the difference is obtained, and finally the respective absolute values are summed to obtain a filtering result for one point. 
         [0095]    The foregoing description of the embodiments illustrates the objects, solutions and advantages of the present disclosure. It will be appreciated that the foregoing description refers to specific embodiments of the present disclosure, and should not be construed as limiting the present disclosure. Any changes, substitutions, modifications and the like within the spirit and principle of the present disclosure shall fall into the scope of the present disclosure.