Abstract:
Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a transfer device controlled by a pre-read signal. In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable. By shifting the bitline voltage before the wordline is turned on, the accessed cell is relieved from the stress which would have otherwise caused cell stability problems.

Description:
FIELD OF THE INVENTION 
   This invention relates generally to static random access memory devices. More particularly, embodiments of the present invention relate to a method and apparatus for avoiding cell data destruction caused by stability problems in SRAM cells. 
   BACKGROUND OF THE INVENTION 
   A static random access memory (SRAM) typically includes an array of memory cells and peripheral circuits. Each cell generally comprises at least 6 transistors, a word line, and two bit lines. An SRAM is generally driven by low power and operates at reasonably high speeds. As the complementary metal oxide semiconductor (CMOS) technology continues to scale down in the submicron range, designing SRAM devices faces many complex challenges. Among these challenges, cell stability is one that must be addressed. 
   Cell stability relates to the ability of a cell to resist accidental overwrites during various operating conditions (e.g., noise due to transistor mismatch, threshold variations, etc.). In an SRAM array, cells can suffer from problems related to cell stability during Read/Write operations. Smaller current requires more time to develop a signal, making it harder to write into cell  100 . On the other hand, when cell  100  is operating under a scenario in which both bitlines are near the supply voltage (Vdd) state and the wordline is on, data stored in the cell may be flipped unexpectedly. 
     FIG. 1  is a schematic representation of an exemplary CMOS six-transistor (6T) SRAM cell  100 . Cell  100  uses six transistors (P 0 , P 1 , N 0 , N 1 , N 2 , N 3 ) to store and access one bit. The four transistors in the center form two cross-coupled inverters (tru, cmp). For the sake of discussion, assuming that wordline wl switches on when the voltage of “tru” (Vtru) is high, the voltage of “cmp” (Vcmp) is low, and the voltage of bitlines (Vblt and Vblc) are high. When wl is off, P 0  and N 1  are on, and P 1  and N 0  are off. When wl is on, Vcmp is raised because Vblc is high. The amount raised is decided by the conductance ratio of transfer gate N 3  and pull down device N 1 . If the amount is high enough to turn N 0  on and turn P 0  off, Vtru goes down slightly. This causes N 1  turns slightly off and P 1  turns slightly on, which enhances Vcmp (i.e., goes up) which, in turn, turns N 0  on stronger than before. With this positive feedback mechanism, Vtru eventually settles to low and Vcmp eventually settles to high. As long as wl is kept low, cell  100  is disconnected from the bitlines and the inverters can keep feeding themselves, allowing cell  100  to store its current value. However, as described above, when cell  100  is exposed to a situation where wl is on and both bit and blc are near the Vdd state, the state of cell  100  may be flipped unexpectedly, destroying data stored therein. 
   In the SRAM array, cells can suffer from the aforementioned cell stability problems during both Read and Write operations, causing undesirable cell data destruction. In some cases, these cell stability problems may be addressed by modifying cell size, array structure (single column or multi-column), and/or access pattern (i.e., during Read or Write operation). Some prior attempts are described below with reference to  FIG. 2-FIG .  8 . 
     FIG. 2  is a schematic representation of an exemplary 6T SRAM array  200  having a single-column structure. In this structure, each column has an input, a Read Circuit, a Write Circuit, and an output. 
   An exemplary Read operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge device is turned off and the wordline is turned on. Each memory cell pulls either of the bitlines down, depending upon whether “0” or “1” had been stored inside the cell. Read Circuit senses the voltage on the bitline and outputs the data. Then, the wordline shuts off. In some cases, in a Read operation, SRAM cell  100  may be exposed to a state where both bitline voltages are near the power supply voltage (Vdd) right after the wordline is turned on, causing a cell stability problem as described above. 
   An exemplary Write operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge devices are turned off and the wordline is turned on. Write Circuit pulls either of the bitlines down. The voltage on the bitline is transferred to a memory cell through its transfer gate. The state of the flip-flop in the memory cell settles. Then, the wordline shuts off. Because an activated cell is eventually written (i.e., overpowered) by Write Circuit in 6T SRAM array  200 , cell stability is not a cause for concern during the Write operation. 
     FIG. 3  is a schematic representation of an exemplary 6T SRAM array  300  having a multi-column structure. In this structure, there are m columns and an m-to-1 multiplexer (m:1 MUX) is used to select a column. The Read and Write operations can be performed in basically the same manner as described above with reference to  FIG. 2 . One difference is that, when a certain column is accessed, all the other columns would be affected by the cell stability problem in both the Read and Write operations. For example, assume that a Write happens to column  1  (col_ 1 ). First, the bitlines for columns are precharged to high. Then, the precharge device is turned off and the wordline is turned on. Write Circuit pulls either of the bitlines of col_ 1  down. At this moment, the voltage of the bitlines of all neighboring columns (col_ 2  to col_m) are all near Vdd and the wordline is on, which means that they have a cell stability problem. Similarly, in a Read operation, not only the accessed column but also the unselected columns will have this cell stability problem. 
   Some have tried to use 8T and 10T SRAM cells to address the cell stability problem in the Read operation.  FIG. 4  is a schematic representation of an exemplary 8T SRAM cell  400 .  FIG. 5  is a schematic representation of an exemplary 10T SRAM cell  500 . In both cases, wwl is used for the Write operation, and rwl is used for the Read operation. When rwl is on, the voltage of node “tru_r” is raised, but this does not propagate to node “cmp”. This means that the positive feedback mechanism, which causes a 6T SRAM cell to be unstable as described above, is absent in 8T and 10T SRAM cells during the Read operation. 
     FIG. 6  is a schematic representation of an exemplary 8T SRAM array  600  having a single-column structure. An exemplary Read operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge device is turned off and the read wordline (rwl) is turned on. Each bitline is pulled down or stays high according to cell data stored therein. Read Circuit senses the voltage on the bitline and outputs the data. Then, the wordline shuts off. As described above, each 8T SRAM cell in array  600  can avoid the cell stability problem in the Read operation. An exemplary Write operation can be performed as follows. First, the bitlines are precharged to high. Then, the precharge device is turned off and the wordline is turned on. Write Circuit pulls either of the bitlines down. The voltage on the bitline is transferred to a memory cell through its transfer gate, and the state of the flip-flop in the memory cell settles. Then, the wordline shuts off. Because an activated cell is eventually written by Write Circuit, cell stability is not a cause for concern for 8T SRAM array  600  during the Write operation. 
     FIG. 7  is a schematic representation of an exemplary 8T SRAM array  700  having a multi-column structure. In this structure, there are m columns and an m-to-1 multiplexer (m:1 MUX) is used to select a column (e.g., via colsel). The Read and Write operations can be performed in basically the same manner as described above with reference to  FIG. 6 . One difference is that, when a certain column is accessed, all the other columns would be affected by the cell stability problem in the Write operation. For example, assume that a Write happens to column  1  (col_ 1 ). First, the bitlines for columns are precharged to high via a precharge device (pc). Then, pc is turned off and the wordline is turned on. Write Circuit pulls either of the bitlines of col_ 1  down. At this moment, the voltage of bitlines of the other columns (col_ 2  to col_m) are all near Vdd and the wordline is on, indicating a cell stability problem. As described above, in a Read operation, all columns of 8T SRAM cells are free from the cell stability problem. 
     FIG. 8  is a schematic representation of an exemplary 10T SRAM array  800  having a multi-column structure. 10T SRAM array  800  comprises an array of 10T SRAM cells and operates basically in the same manner as 8T SRAM array  700 . Each  10 T SRAM cell can be similarly structured to perform like cell  500  described above with reference to  FIG. 5 . 
   To summarize, cell stability remains problematic in at least the following scenarios: during the Read operation in 6T SRAM arrays having a single-column structure; during the Read and Write operations in 6T SRAM arrays having a multi-column structure; and during the Write operation in 8T and 10T SRAM arrays having a multi-column structure. There is a need in the art to solve the cell stability problems represented in these scenarios. Embodiments of the present invention can address this need and more. 
   SUMMARY OF THE INVENTION 
   Embodiments of the present invention provide a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) devices. Embodiments of the invention can perform safe Read/Write operations on SRAM cells without affecting cell stability. More specifically, embodiments of the invention can transfer data inside of a cell to an appropriate bitline in advance of an actual Read/Write operation. 
   Such an advance or “preemptive” data transfer to the bitline can be done regardless of the column structure employed by the underlying SRAM array. In one embodiment, data inside of a cell is transferred, via a transfer device controlled by a pre-read signal, to the bitline before the wordline is turned on. By shifting the bitline voltage which reflects the cell data before the wordline is turned on, the accessed cell is thus relieved from the stress which would have otherwise caused cell stability problems in a conventional SRAM cell. 
   In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable, advantageously avoiding flipping the cell unexpectedly. 
   Other objects and advantages of the present invention will become apparent to one skilled in the art upon reading and understanding the detailed description of the preferred embodiments described herein with reference to the following drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete understanding of the present invention and the advantages thereof may be acquired by referring to the following description, taken in conjunction with the accompanying drawings in which like reference numbers indicate like features. 
       FIG. 1  is a schematic representation of an exemplary CMOS 6T SRAM cell. 
       FIG. 2  is a schematic representation of an exemplary 6T SRAM array having single-column structure. 
       FIG. 3  is a schematic representation of an exemplary 6T SRAM array having a multi-column structure. 
       FIG. 4  is a schematic representation of an exemplary 8T SRAM cell. 
       FIG. 5  is a schematic representation of an exemplary 10T SRAM cell. 
       FIG. 6  is a schematic representation of an exemplary 8T SRAM array having a single-column structure. 
       FIG. 7  is a schematic representation of an exemplary 8T SRAM array having a multi-column structure 
       FIG. 8  is a schematic representation of an exemplary 10T SRAM array having a multi-column structure. 
       FIG. 9  is a schematic representation of a 6T SRAM cell according to one embodiment of the invention. 
       FIG. 10  is a diagrammatic representation of how signals can be controlled in accessing a 6T SRAM cell, according to one embodiment of the invention. 
       FIG. 11  is a diagrammatic representation of how signals can be controlled in accessing a 6T SRAM cell, according to another embodiment of the invention. 
       FIG. 12  schematically depicts a cell circuit with a plurality of wordlines and a corresponding waveform, according to one embodiment of the invention. 
       FIG. 13  schematically depicts a cell circuit with one wordline and a plurality of delay elements for generating a plurality of wordline signals inside the cell circuit, according to another embodiment of the invention. 
       FIG. 14  is a schematic representation of a 10T SRAM array having a multi-column structure with a transfer device controlled by a pre-read signal, according to one embodiment of the invention. 
       FIG. 15  is a diagram depicting a waveform illustrating the Read and Write operations of the 10T SRAM array of  FIG. 14 , according to one embodiment of the invention. 
       FIG. 16  is a schematic representation of a 10T SRAM array having a multi-column structure with shared read and write bitlines, according to one embodiment of the invention. 
       FIG. 17  is a schematic representation of an 8T SRAM array having a multi-column structure with a transfer device controlled by a pre-read signal, according to one embodiment of the invention. 
       FIG. 18  diagrammatically depicts two waveforms of the 8T SRAM array of  FIG. 17 , according to one embodiment of the invention. 
       FIG. 19  is a schematic representation of an 8T SRAM array having a multi-column structure with shared read and write bitlines, according to one embodiment of the invention. 
       FIG. 20  diagrammatically depicts two waveforms of the 8T SRAM array of  FIG. 19 , according to one embodiment of the invention. 
   

   DETAILED DESCRIPTION 
   The present invention and various features and advantageous details thereof will now be described with reference to the exemplary, and therefore non-limiting, embodiments that are illustrated in the accompanying drawings. Descriptions of known programming techniques, computer software, hardware, network communications, operating platforms and protocols may be omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only and not by way of limitation. Various possible substitutions, modifications, additions and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those skilled in the art from this disclosure. 
     FIG. 9  is a schematic representation of a 6T SRAM cell  900  according to one embodiment of the invention. Structurally, cell  900  comprises two more transfer gates than a conventional 6T SRAM cell (e.g., cell  100  of  FIG. 1 ). As depicted in  FIG. 9 , transfer gates N 2  and N 3  are controlled by a first wordline (wl_ 1 ) and transfer gates N 4  and N 5  are controlled by a second wordline (wl_ 2 ). The widths of transfer gates N 2  and N 4  are chosen in a manner such that their total cell current becomes the same as that of N 2  in  FIG. 1 . Similarly, the widths of transfer gates N 3  and N 5  are chosen in a way so as to allow the total cell current becomes the same as that of N 3  in  FIG. 1 . As one skilled in the art can appreciate, the current and supply voltage of an SRAM cell can vary depending upon a variety of factors (e.g., the number of cells on a bitline, the CMOS technology used in manufacturing the cell and/or the SRAM array, etc.). As an example, if the length of the polysilicon layer (L poly ) is 90 nm (known as the “L poly =90 nm” generation of process technology), the current of an SRAM cell should be 60 μA, the number of the cells on a bitline should be 64, the supply voltage should be 1.0 V, and the bitline voltage should be below 800 mV. As an example, when writing data to cell  900 , the first wordline gate opens and data stored inside cell  900  is transferred to the bitlines. Then, the second wordline gate opens. As the bitline voltage is shifted to a state which reflects the cell data in advance, the state of cell  900  can become difficult to flip, in part due to the reduced power supply voltage. 
     FIG. 10  is a diagrammatic representation of how signals can be controlled in accessing cell  900 , according to one embodiment of the invention. Signal control method  1000  can be applied in a Read operation or a Write operation. First, the bitlines are precharged to high. Then, the precharge device is turned off and the first wordline (wl_ 1 ) is turned on. Since the width of N 2  or N 3  is small (i.e., reduced by about half or more from a typical transfer gate in a conventional 6T SRAM cell), the conductance ratio of N 2 /N 0  or N 3 /N 1  is correspondingly small. The low power design can facilitate cell stability. While wl_ 1  is on, depending upon whether data stored in cell  900  is “0” or “1”, the voltage on either of the bitlines is lowered. When the bitline voltage drops to a threshold level, the second wordline (wl_ 2 ) is turned on. Following the above example with the “L poly =90 nm” generation of process technology, precharge time for reading from/writing to the bitline(s) would be about 100 ps. The threshold of the bitline voltage could be set at 800 mA, below which wl_ 2  is turned on. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, by the time wl_ 2  is turned on, the state of cell  900  is unlikely to flip unexpectedly. This addresses one of the aforementioned cell stability problems in which the state of a conventional SRAM cell may flip unexpectedly when both of the bitline voltages are high (i.e., near the power supply voltage Vdd). 
     FIG. 11  is a diagrammatic representation of how signals can be controlled in accessing cell  900 , according to another embodiment of the invention. In signal control method  1100 , only wl_ 1  is turned on in the Read operation, while both wl_ 1  and wl_ 2  are turned on in the Write operation. One advantage of method  1100  is that it does not require a delay control circuit and consumes less power in the Read operation. A tradeoff could be that reading out is somewhat slower, making it less suitable for use in a multi-column structure. 
   Although two wordlines are utilized in the above-described embodiments, the number of wordlines can be increased to more than two.  FIG. 12  schematically depicts a cell circuit  1200   a  with n wordlines (wl_ 1  . . . wl_n) and a corresponding waveform  1200   b  which illustrates one example of how wl_ 1  . . . wl_n may operate. As illustrated in  FIG. 13 , it is possible for cell  1300  to receive one wordline and create the rest of the wordline signals inside, utilizing delay elements. 
     FIG. 14  is a schematic representation of a 10T SRAM array  1400  having a multi-column structure, according to one embodiment of the invention. Array  1400  may utilize 10T SRAM cells with a conventional configuration (e.g., cell  500 ). In the exemplary embodiment shown in  FIG. 14 , array  1400  may comprise a plurality of columns (col_ 1  . . . col_m) of 10T SRAM cells with a plurality of read wordlines (rwl_ 1  . . . rwl_n) and write wordlines (wwl_ 1  . . . wwl_n). As an example, in col_ 1 , a transfer NMOS  1401  is added between a read bitline (rblt) and a write bitline (wblt). In this example, transfer device  1401  is controlled by a pre-read signal (pr). Similar to array  700  and array  800  described above with reference to  FIGS. 7 and 8 , array  1400  utilizes a multiplexer to select a column via colsel. 
   In the example shown in  FIG. 14 , the Read operation can be done in just about the same way as described above with reference to  FIGS. 7 and 8  regarding 8T/10T SRAM arrays. The Write operation can be done as follows. First, the read bitlines and write bitlines are precharged to high via a precharge device (pc). Then, pc is turned off, and rwl and pr open, which turns on transfer device  1401 . As transfer device  1401  is turned on, the voltage of one of write bitlines (wblt or wblc) is lowered in accordance with cell data stored therein. After this, write wordline (wwl) opens. As the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells is sufficiently stable and thus difficult to flip. As an example, if L poly =90 nm, the current of an SRAM cell in this embodiment should be 60 μA, the number of the cells on a bitline should be 64, the supply voltage should be 1.0 V, and the bitline voltage should be below 800 mV. Precharge time for reading from/writing to the bitline(s) would be 100 ps. 
   The design shown in  FIG. 14  enables array  1400  to effectively avoid a cell stability problem which is common to a typical 10T SRAM array having a conventional multi-column structure where bitline voltages tend to reach the high state at the same time.  FIG. 15  is a diagram depicting a waveform  1500  illustrating the Read and Write operations of array  1400 . As can be seen in the example shown in  FIG. 15 , rblc is lowered during the Read operation and wblc is lowered during the Write operation. In the Read operation, a cell of array  1400  does not suffer from stability problems as no feedback is formed. The Write operation can be done as follows. First, the read bitlines and write bitlines are precharged to high via a precharge device (pc). Then, pc is turned off, and rwl open, which turns on transfer device  1401 . As transfer device  1401  is turned on, the voltage of one of write bitlines (wblt or wblc) is lowered in accordance with cell data stored therein. After this, write wordline, (wwl) opens. As the bitline voltage has already been changed to the state which reflects the cell data in advance, the cell is sufficiently stable and thus difficult to flip. 
   As one skilled in the art can appreciate, array  1400  may be modified without departing from the spirit of the invention. As an example, a variation of array  1400  is shown in  FIG. 16 .  FIG. 16  is a schematic representation of a 10T SRAM array  1600  having a multi-column structure, according to one embodiment of the invention. In this example, the read and write bitlines are shared and the transfer device and pr are not needed. The rest of the signals can be controlled in just about the same way as described above. In embodiments described above, the delay of write wordlines (wwl) would be around 80 ps. 
     FIG. 17  is a schematic representation of an 8T SRAM array  1700  having a multi-column structure, according to one embodiment of the invention. Array  1700  may utilize 8T SRAM cells with a conventional configuration (e.g., cell  400 ). In the exemplary embodiment shown in  FIG. 17 , array  1700  may comprise a plurality of columns (col_ 1  . . . col_m) of 8T SRAM cells with a plurality of read wordlines (rwl_ 1  . . . rwl_n) and write wordlines (wwl_ 1  . . . wwl_n). As an example, in col_ 1 , a transfer NMOS  1701  is added between a read bitline (rblt) and a write bitline (wblt). In this example, transfer device  1701  is controlled by a pre-read signal (pr). Similar to array  700  and array  800  described above with reference to  FIGS. 7 and 8 , array  1700  utilizes a multiplexer to select a column via colsel. 
   In the example shown in  FIG. 17 , the Read operation can be done in just about the same way as described above with reference to  FIGS. 7 and 8  regarding 8T/10T SRAM arrays. The Write operation can be done as follows. The Write operation can be done in the following manner. First, the read and write bitlines are precharged to high via a precharge device (pc). Then, pc is turned off, and read worline (rwl) opens. After some delay, pr opens. When the cell data is “1”, the read bitline stays high. Therefore, wblt stays high and wblc is pulled down. On the other hand, when the cell data is “0”, the read bitline is pulled down. Therefore, wblt is pulled down and wblc stays high. After this, write wordline (wwl) opens. As the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable and thus can be difficult to flip. As one skilled in the art can appreciate, specific operating parameters, including delays, can vary depending upon a variety of factors (e.g., the CMOS technology used in manufacturing the cell and/or the SRAM array, the supply voltage, the current of the cell, the number of cells on a bitline, etc.). As an example, if L poly =90 nm, the current of an SRAM cell in this embodiment should be 60 μA, the number of the cells on a bitline should be 64, the supply voltage should be 1.0 V, and the bitline voltage should be below 200 mV. Precharge time for reading from/writing to the bitline(s) would be 100 ps. The delay of pr would be around 80 ps and the delay of wwl would be around 160 ps. 
   Like array  1400 , array  1700  can avoid a cell stability problem by controlling how bitline voltages reach the high state.  FIG. 18  diagrammatically depicts two waveforms  1800   a  and  1800   b  of array  1700 . Waveform  1800   a  illustrates a scenario in which cell data is “1”. Waveform  1800   b  illustrates a scenario in which cell data is “0”. As exemplified in  FIG. 18 , wblc is lowered if cell data is “1” (waveform  1800   a ) and wblt is lowered if cell data is “0” (waveform  1800   b ). 
   Like array  1400 , array  1700  may be modified without departing from the spirit of the invention. As an example, a variation of array  1700  is shown in  FIG. 19 .  FIG. 19  is a schematic representation of an 8T SRAM array  1900  having a multi-column structure, according to one embodiment of the invention. In this example, the read and write bitlines are shared. The rest of the signals, including pr, can be controlled in just about the same way as described above with reference to  FIG. 17 . The delay of pr would be around 320 ps and the delay of wwl would be around 400 ps. 
     FIG. 20  diagrammatically depicts two waveforms  2000   a  and  2000   b  of array  1900 . Waveform  2000   a  illustrates a scenario in which cell data is “1”. Waveform  2000   b  illustrates a scenario in which cell data is “0”. As exemplified in  FIG. 20 , the shared blc is lowered if cell data is “1” (waveform  2000   a ) and the shared bit is lowered if cell data is “0” (waveform  2000   b ). 
   In all embodiments of the invention, the bitline voltage is shifted before the wordline is activated and the voltage shifts in accordance with the data stored in the cell. Embodiments of the invention disclosed herein can relieve stress on accessed SRAM cells and thus facilitate cell stability while minimizing the increase in cell size. 
   Although the present invention has been described in detail herein with reference to the illustrative embodiments, it should be understood that the description is by way of example only and is not to be construed in a limiting sense. It is to be further understood, therefore, that numerous changes in the details of the embodiments of this invention and additional embodiments of this invention will be apparent to, and may be made by, persons of ordinary skill in the art having reference to this description. Accordingly, the scope of the invention should be determined by the following claims and their legal equivalents.