Abstract:
An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 12/089,711, filed Apr. 10, 2008 now U.S. Pat. No. 8,008,731 entitled “IGFET Device Having a RF Capability,” which is a National Stage Application with a 371( c ) date of Apr. 10, 2008 claiming priority of PCT/IB2005/003029 with an International Filing Date of Oct. 12, 2005. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to insulated gate field-effect transistors (IGFETs). 
     2. Description of the Prior Art 
     Herbert et al., U.S. Pat. No. 5,912,490, discloses a FET structure having a reduced drain to gate capacitance by providing a buried shield plate underlying the gate and between the gate and drain of the transistor. Use of a buried shield between the gate and drain of a field effect transistor can reduce gate to drain capacitance and maximizes the frequency response of the IGFETs. 
     As a result of this improvement in frequency response, the breakdown voltage of drain to substrate is lowered. 
     It appears that a compromise needs to be made between the reduction of gate to drain capacitance to increase the frequency response and the breakdown voltage of drain to substrate. 
     The goal of the invention is directed to a MOSFET structure having higher operation voltage and higher breakdown capability, while keeping a high frequency behaviour and a high density. 
     SUMMARY 
     In accordance with the invention, an IGFET device comprises: a semiconductor body having a major surface, a source region of first conductivity type abutting said surface, a drain region of said first conductivity-type abutting said surface and spaced from said source region with a channel therefrom, an active gate overlying said channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, a dummy gate is positioned between said active gate and said drain and is insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and is insulated from the drain region by said gate oxide, wherein the active gate and the dummy gate are forming the electrodes of said capacitance substantially perpendicular to said surface. 
     According to an aspect of the invention, the dummy gate and the active gate comprise a stack of multiple metal layers in parallel forming electrode of said capacitance. 
     Pursuant of another aspect of the invention said stack is connected to a polysilicon layer and the stack can be disposed on top of the polysilicon layer. 
     Advantageously, the invention can be applied to MOSFET and LDMOS transistors. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a section view of a LDMOS in accordance with an embodiment of the invention; 
         FIG. 2  is the equivalent electrical circuit of the LDMOS of  FIG. 1 ; 
         FIG. 3  is the equivalent electrical circuit of the LDMOS of  FIG. 1 , 
         FIGS. 4 and 5  are the equivalent electrical circuits of the LDMOS of  FIG. 1  in two different modes of conduction; 
         FIGS. 6 to 9  are the section view of the LDMOS of  FIG. 1  during different steps of processing; 
         FIG. 10  is the section view of a MOS in accordance with another embodiment of the invention; and 
         FIG. 11  is a perspective view of an IGFET in accordance with another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The  FIG. 1  is a section view of a lateral double-diffused field effect transistor, or LDMOS, in accordance with one embodiment of the invention. Field oxide  1  defines a device region in the surface of a P +  substrate  2 . A N +  source region  3  is formed in a P +  base region  4  by double-diffusion processing with base region  4  having a P −  doped extension  5  which defines a channel region of the transistor. N −  doped region  6  and N +  doped region  7  define the drain of the transistor. An active gate  8  is formed over channel  5  with a gate oxide  9  electrically separating the active gate  8  from channel  5  and substrate  2 . 
     In accordance with the invention, a dummy gate  10  is provided between active gate  8  and the N +  doped region  7  of the drain, on top of the N −  region  6 . The gate oxide  9  is electrically isolating the dummy gate  10  from the N −  region  6 . 
     The active gate  8  and the dummy gate  10  are composed of a stack having a first layer of polysilicon  11 ,  12 . On top of this polysilicon layer, metal contacts  13 ,  14 ,  15 ,  16  and metal layers  17 ,  18 ,  19 ,  20  are alternatively disposed. 
     Dielectric material  21  (e.g., silicon-nitride) is provided on the surface of the device with openings there through for forming a source contact  22 , a gate contact  23  and a drain contact  24 . 
     Superimposed on the section view of the structure, the equivalent electrical circuit is represented in  FIG. 2 . The equivalent electrical circuit of this structure is composed of the transistor  30  with its source S, gate G and drain D. By providing the dummy gate  10  between the active gate  8  and the N +  doped region  7  of the drain, i.e. on top of the drain region  6 , the dummy gate  10  and the active gate  8  form a capacitance  31 . Therefore, the dummy gate  10  is being electrically connected to the active gate  8  through this capacitance  31 . The dummy gate  10  and the N −  region  6  are forming a second capacitance  32  with the gate oxide  9  forming the dielectric part of the capacitance  32 . 
     The N −  region  6  is equivalent,  FIG. 2  or  3 , to a variable resistor  33  controlled by the capacitance  32  as it is explained below. 
     In an IGFET, the electrical conduction is normally from drain to source, in a conduction direction which is transverse to the direction of elongation of the gate conductor  8 . Therefore, in a LDMOS such as the one described here, the source voltage is always at the lowest voltage, generally at GROUND level and the drain voltage is, in DC mode, at the supply voltage V cc . 
     In a static view of operation of this transistor, two modes can be distinguished: a first mode where the voltage V G  applied to the active gate  8  is higher than the threshold voltage V T  of the transistor and a second mode where the voltage V G  applied to the active gate  8  is below this threshold voltage V T . 
     In the first mode,  FIG. 4 , the channel region is electrically conducting. Due to the capacitive coupling between the capacitors  31  and  32 , the voltage applied to the N −  region  6  by the dummy gate  10  is of the same order of magnitude as the drain voltage V d . Therefore, the dummy gate  10  has almost no effect on the electrical conduction of the N −  region  6 . 
     In the second mode,  FIG. 5 , the channel region  5  is electrically open. The voltage applied to the N −  region  6  by the dummy gate  10  is roughly at GROUND level and substantially different to the drain voltage V d . This voltage difference induces an increase of the depleted area  40  of the N −  region  6 . Consequently the electrical sectional area of this N −  region  6 , in which conduction takes place, is reduced and the resistance is increased. 
     Advantageously, the resistance of the N −  region  6  is varying with the gate voltage: the resistance is low when the gate voltage V g  is above the threshold voltage V t  and the transistor is conducting and the resistance is high when the gate voltage V g  is below the threshold voltage V t  and the transistor is open. 
     A classical LDMOS structure is described, for instance, in M. D. Pocha, A. G. Gonzales, and R. W. Dutton, IEEE Trans. on Electron Devices, ED-21, 778 (1974). Compared to this structure, the variable resistance of the above described transistor boasts high-frequency operation as the transistor has a low resistance between drain and source when it is conducting. At the same time, the transistor has a high drain-breakdown voltage as the resistance is high when the transistor is open. 
     Fabrication of the device of  FIG. 1  requires no complex or costly processing and is based on standard MOSFET technology. 
     The  FIG. 6  is a section view of the device with the basic transistor structures already implemented. Conventional polysilicon fabrication processes are used to obtain this structure. 
     The first layer  12  of the dummy gate and first layer  11  of the active gate are made simultaneously of polysilicon. 
     The  FIG. 7  is a section view of the device at the next step of the manufacturing process. Metal contacts  13 , 15  are formed on top of the layers  11 ,  12  after the deposition and planarization of a dielectric material  21 . 
     Then a metal layer is deposited and etched,  FIG. 8 , to form the first level of metal interconnection as well as a first metal stack  17 ,  19  on the metal contacts  13 ,  15 . 
     A dielectric material  21  is deposited,  FIG. 9 , and planarized to protect the underlying structure and prepare the structure to receive a new metal interconnection level. 
     Depending on the technology used, more than 2 metal interconnection layers are commonly manufactured. 
     From the description here above, the person skilled in the art understands that any standard MOS technology with two or more conductive interconnection layers such as aluminum, copper or polysilicon layers and the like, can be used to implement the invention. 
     The choice of technology defines the number of metal layers which can be stacked as well as the distance between the layers of the active gate and the layers of the dummy gate. These two parameters and the characteristics of the dielectric material define the value of the capacitance formed by the active gate and the dummy gate and, consequently, the behavior of the transistor. 
     For instance, a 0.18 μm technology sees an improvement of the breakdown capability in RF from 7 Volts to over 12 Volts. For a 0.13 μm, an improvement is from 3 or 4 Volts to 8 Volts. 
     The description of this embodiment of the invention is based on a LDMOS transistor. However, the invention is not limited to this type of Field-Effect transistors but is useful in all types of IGFET. 
     For instance, another embodiment of this invention is illustrated in  FIG. 10  with a MOSFET in which the dummy gate  10  is implemented along the drain region  7 , where the N-region is realized with the Nwell implantation. 
     For illustrative purposes, the stack of contacts and metal layers has been represented on top of each other above the transistor active area. However, some design rules for specific technologies forbid the implementation of a contact, or a via, directly above the polysilicon gate. The person skilled in the art understands that the shift of the contacts used to create the active and dummy gates outside the active area will not modify the operation of the transistor. Such an implementation is illustrated in  FIG. 11 . In the  FIG. 11 , only the polysilicon layers  11 ,  12  and the first contacts  13 ,  15  on top of the gate oxide  9  and the field oxide  1  are shown with an objective of clarity. 
     The person skilled in the art understands that the figures were drawn to illustrate the different embodiments and are not representative of the real dimension of the transistors or of the specificity of a particular technology. For instance, the gate oxide  9  of  FIG. 1  could be limited to the area under the gate polysilicon without modifying the operation of the transistor. 
     The description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the invention as defined in the claims.