Abstract:
An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims the benefit of priority under 35 U.S.C Section 119 from U.S. Provisional Application Ser. No. 60/653,162, filed Feb. 15, 2005, entitled, “Wireless RF Circuitry Optimized for 3D Packaging Technologies.” 

   BACKGROUND OF THE INVENTION 
   Packaging technology for Power Amplifier modules and Front Ends, particularly those employed in modern wireless communication networks, is moving towards a more compact and low cost packaging technology, and hence wireless circuitry must be modified and designed around the strengths of this technology. 
   Often circuitry, in particular, but not limited to, wireless circuitry, occupies relatively large and expensive real estate on a module board. Thus, there is a strong for technologies with improved designs which can reduce the size and thus the cost of these module boards. 
   SUMMARY OF THE INVENTION 
   An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit may be placed on a first substrate and a second portion of the integrated circuit may be placed on a second substrate stacked adjacent the first substrate and wherein the first portion and the second portion of the integrated circuit may be interconnected. The first substrate may be comprised of low dielectric material and the distance between the first and the second substrate may be sufficiently large to facilitate high impedance functions and components. In an embodiment of the present invention, the integrated circuit may further comprise printing inductors on the first substrate thereby enabling them to be high Q inductors and printed spiral arms may be stacked vertically on both the top and bottom surface of the first substrate thereby creating high Q inductors. 
   Another embodiment of the present invention provides a method, comprising placing a first portion of an integrated circuit on a first substrate, placing a second portion of an integrated circuit on a second substrate that stacked adjacent the first substrate, and interconnecting the first portion and the second portion of the integrated circuit. The present method may further comprise placing the first and the second substrate at a predetermined distance that enables high impedance functions and components and stacking printed spiral arms vertically on both the top and bottom surface of the first substrate thereby creating high Q inductors. The present method may also comprise placing critical and difficult to design RF functions and building blocks on the first substrate due to ease of access and using distinct dielectric constants with different heights from a ground plane by the first and the second substrates associated with the first and second portions of the circuit. 
   Another embodiment of the present invention further provides an integrated circuit, comprising a first portion including at least one output match connected to at least one harmonic filter on a first substrate, a second portion on a second substrate positioned adjacent the first substrate and including at least one power amplifier connected to at least one bias and power controller which is further connected to an antenna switch and wherein the first and second substrates further comprise at least one interconnect connecting the first portion and the second portion. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. 
       FIG. 1  illustrates a circuit block diagram for the bottom tier of the 3D stackable substrate of one embodiment of the present invention; 
       FIG. 2  illustrates an alternative circuit block diagram for the bottom tier of the 3D stackable substrate of one embodiment of the present invention; 
       FIG. 3  illustrates a circuit block diagram for the top tier of the 3D stackable substrate of one embodiment of the present invention; 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Although the present invention is not limited to only RF circuits, current design approaches for RF circuits designed for markets such as wireless products all use a single substrate onto which all components and traces are placed on. Although the substrates may have multi-layers of conductors, there is only one layer available to place components during the creation of a multi-chip module (MCM). This not only limits the size reduction, but RF performance is limited due to the sharing of one common substrate. Some components and functions work best on high impedance substrates that are thick, low dielectric constant and low loss. Other components prefer low impedance substrates that are thin and high dielectric. 
   Further, on conventional 2D package designs, it is extremely difficult to print high Q inductors. In an embodiment of the present invention, the multiple levels of the present 3D approach allows the construction of inductors with spirals above each other in a stacked fashion, which increases Q substantially. 
   Although methods for designing wireless RF circuitry on the 3D packaging technologies are described herein, it is understood that the present invention is not limited to any particular circuit (such as RF) or any particular packaging structure. Often wireless circuitry occupies relatively large and expensive real estate on the module board. By applying certain design topologies on the 3D packages such as stackable substrates, we can efficiently reduce the size and thus the cost of these modules. The 3D approach for circuit design has many advantages; it reduces the area that a typical circuit occupies by simplifying the routing and the tuning of the circuits as illustrated herein. More specifically, but not by way of limitation, it is critical to strategically partition the circuit in regards to what is placed on a lower substrate and what is placed on an upper substrate(s). Careful selection of the functions and components on each level allows the minimization of the number of interconnects needed in the z-axis between levels. Minimization of z-axis connections/routing saves board space (each connection utilizes a finite area), minimizes loss (interconnects typically have greater loss (due to dissimilar materials, discontinuities and impedance variations) as compared to x- or y-axis connections that can be made with simple printed traces on the substrate) and reduces cost (smaller boards required, less interconnect hardware such as solder balls or SMD components). The 3D stackable substrate also provides additional levels for the dies and other components to be mounted on as well. 
   The 3D stackable approach for RF circuitry has many RF advantages; it permits the lower substrate to be very thin, and hence provides a better thermal dissipation and better thermal stability for the Power Amplifiers, as well as a better RF ground. This is only possible since the upper levels of the 3D stackable substrates can be utilized for the matching networks, filters and other passive networks that are sensitive to the substrate thickness and prefer high impedance/low dielectric substrates. Although not limited in this respect, one potential stacking of substrates and partitioning of circuits is as follows:
     1. Thin bottom substrate with high dielectric constant   2. Air gap, later filled with low dielectric overmold compound when the multi-chip 3D module is encapsulated in the packaging process   3. Thin top substrate with low dielectric constant (components on the top substrate and the substrate itself will later also be covered with low dielectric overmold compound when the multi-chip 3D module is encapsulated in the packaging process   

   An embodiment of the present invention provides that the partitioning between the top and bottom substrate for a mobile phone radio transmitter may be as follows: The bottom substrate may contain two power amplifiers, (one for both high bands and one for both low bands) a CMOS Power and Bias Controller, and a single pole six throw antenna switch. The top substrate may contain two output matching networks, two couplers, and harmonic filters. The major advantages of this partitioning strategy are as follows:
     1. This partitioning minimizes the number of connections in the z-axis between the two stacked substrates, thus saving space, reducing part count (interconnect components), reducing cost and increasing reliability.   2. Most components and functions requiring a high impedance substrate are placed on the top substrate. The top substrate can not only be chosen to be a low dielectric material (for high impedance), but the air gap (later in the process filled with a very low dielectric overmold material, typically a plastic material) may be very low in dielectric constant so the overall effective dielectric of the top substrate may be very low, and its height may be relatively large, also facilitating high impedance functions and components.   3. High Q inductors may be realized by printing inductors on the top substrate. Even higher Q inductors are possible by printing spiral arms stacked vertically, on both top and bottom surface of the top substrate, or on 3 surfaces—both surfaces of the top substrate and the top surface of the bottom substrate. The construction of high Q inductors allows the design of amplifiers and filters with significantly improved performance, especially when designing to maximize output power and efficiency (minimize loss).   4. Critical or hard to design RF functions and building blocks such as the power amplifier output match network may be located on the top substrate. This enables simple and rapid tuning of these circuits as design engineers iteratively and empirically “tune” their designs to optimize performance. If these functions were placed in the lower layers, access would be impossible once the stacked substrates were assembled. The entire output matching network does not need to be placed on the top substrate—if desired, only the portion that is critical and will likely need to be tuned can be placed on the top substrate, although the present invention is not limited in this respect. Also, other 2D packaging technologies such as lead-frame are equally difficult to tune, although lead-frame is one of the lowest cost options for substrates and packaging. As an additional embodiment, one could use a lead-frame based substrate for the lower substrate to reduce cost, and still have the flexibility to tune circuits and components by stacking a rigid or flex substrate as the second substrate on top of the bottom lead-frame substrate.   

   Although detailed descriptions of one partitioning is given in the next section, it is understood that this is merely an illustrative embodiment and is only one of numerous partitioning techniques to give these RF benefits as other divisions of functions and components may also capitalize on the high impedance (low dielectric/increased height) of the top substrate(s) and low impedance (high dielectric/decreased height) of the lower substrate(s). 
   Turning now to the figures,  FIG. 1  illustrates an example block diagram of wireless circuitry that can be utilized in the bottom tier of the 3D Stackable Substrate of an embodiment of the present invention. Although the present invention is not limited in this respect,  FIG. 1  shows an RF block diagram made up of two Power Amplifiers  109  and  117 , that are connected to the top tier of the 3D Stackable Substrate (shown in  FIG. 3 ) through PIN  1  ( 110  of  FIG. 1 and 340  of  FIG. 3 ) and PIN  2  ( 118  of  FIG. 1 and 346  of  FIG. 3 ) respectively, the bottom tier has a CMOS Power and Bias Controller  111  which receives its coupled input power from the top tier shown in  FIG. 3  through PIN  5  ( 112  of  FIG. 1 and 345  of  FIG. 3 ).  FIG. 1  may also include a single pole six throw antenna switch  119  with four receive outputs  121 ,  122 ,  123  and  124  that receives Tx signals  107  and  115  through match  108  and  116  from the top substrate shown on  FIG. 3  via PIN  3  ( 113  of  FIG. 1 and 344  of  FIG. 3 ) and PIN  4  ( 114  of  FIG. 1 and 350  of  FIG. 3 ) respectively. The antenna port of the switch may go directly to the external antenna  247 . In an embodiment of the present invention, the bottom tier thickness may not be restricted to any height since most of the tuning networks are on the top tier of the 3D Stackable Substrate shown in  FIG. 3 . 
   Turning now to  FIG. 2  is an illustration of an alternative circuit block diagram of wireless circuitry that can be utilized in the bottom tier of the 3D Stackable Substrate of one embodiment of the present invention.  FIG. 2  shows an RF block diagram made up of two Power Amplifiers  232  and  238 , that are connected to the top tier of the 3D Stackable Substrate shown in  FIG. 3  through PIN  1  ( 233  of  FIG. 2 and 340  of  FIG. 3 ) and PIN  2  ( 239  of  FIG. 2 and 346  of  FIG. 3 ) respectively, the bottom tier may have a CMOS Power and Bias Controller  234  which receives its coupled input power from the top tier shown in  FIG. 3  through PIN  5  ( 235  if  FIG. 2 and 345  of  FIG. 3 ).  FIG. 2  also includes, in an embodiment of the present invention, two single pole three throw switches  242  and  243  with four receive outputs  245 ,  246 ,  248  and  249  that receives Tx signals  230  and  236  via match  231  and  237  from the top substrate shown on  FIG. 3  via PIN  3  ( 240  of  FIG. 2 and 344  of  FIG. 3 ) and PIN  4  ( 241  of  FIG. 2 and 350  of  FIG. 3 ) respectively. The Antenna ports of the switches may go through the diplexer  244  to the external antenna port  247 . The bottom tier thickness is not restricted to any height since most of the tuning networks are on the top tier of the 3D Stackable Substrate shown in  FIG. 3 . 
     FIG. 3  demonstrates a circuit block diagram of wireless circuitry that can be utilized in the top tier of the 3D Stackable Substrate in an embodiment of the present invention.  FIG. 3  shows two output matching networks  341  and  347  that are connected to the lower tier via PIN  6   340  and PIN  7   346  respectively. The  FIG. 3  circuit block diagram may also include two couplers  342  and  348  that are connected to the lower tier via PIN  8   345 . The harmonic filters  343  and  349  may be connected to the lower tier through  344  and  350  respectively. 
   While the present invention has been described in terms of what are at present believed to be its preferred embodiments, those skilled in the art will recognize that various modifications to the disclose embodiments can be made without departing from the scope of the invention as defined by the following claims.