Abstract:
CCD imagers with a novel replicated-line-imager architecture are abutted to form an extended line sensor. The sensor is preceded by optics having a slit aperture and having an optical beam splitter or astigmatic lens for projecting multiple line images through an optical color-discriminating stripe filter to the CCD imagers. A very high resolution camera suitable for use in a satellite, for example, is thus provided. The replicated-line architecture of the imager comprises an area-array CCD, successive rows of which are illuminated by replications of the same line segment, as transmitted by respective color filter stripes. The charge packets formed by accumulation of photoresponsive charge in the area-array CCD are read out row by row. Each successive row of charge packets is then converted from parallel to serial format in a CCD line register and its amplitude sensed to generate a line of output signal.

Description:
The invention described herein was made in performance of work under NASA Contract No. NAS 5-27505 and is subject to the provisions of Section 305 of the National Aeronautics and Space Act of 1958 (72 Stat. 435; 42 U.S.C. 2457). 
    
    
     FIELD OF INVENTION 
     Our invention relates to CCD television cameras of the type incorporating a CCD line imager for line scanning and deriving transversal scanning of a field of view by optical displacement of the image field relative to the CCD line imager. 
     BACKGROUND OF THE INVENTION 
     Such a camera may use a mechanically scanned optical slit system. The particular application we concerned ourselves with is a camera to be used in a satellite orbiting a celestial body to be observed. The satellite camera has to provide as high resolution of image as feasible and has to have color-discriminating capability. Red (R), green (G), blue (B) and near infrared (NIR) responses to image are separated. 
     A CCD field imager, imaging an entire field at any time rather than just a slit or line in that field as a CCD line imager does, has to have an area array of photosensing sites. (In this document &#34;photosensing site&#34; refers to the location of a photosensing element, supposing photosensing not to be done within a CCD charge channel, or to the location at which charge carriers are collected in a CCD charge transfer channel, but supposing photosensing to be done in the semiconductive material in which the charge transfer channel is formed.) These sites are arranged in a field imager of field transfer type along each of parallelled charge transfer channels defining the columns of the array and are further arranged to be in rows. Each row is formed by the alignment of respective charge transfer stages in each charge transfer channel. So resolution in the direction transverse to line scan (and to rows of the array) is limited in a CCD field imager of field transfer type by the reciprocal of the minimum length of the charge transfer stage. A slight improvement is possible by staggering alternate charge transfer sites in the rows of the array. A problem is encountered in attempting to design a high-resolution field imager, as one seeks manyfold increase in the number of picture elements across the field in the direction transverse to line scan, particularly an increase beyond the number of minimum length charge transfer stages that will fit into each one of paralleled charge transfer channels extending across a semiconductor die of reasonable size. It appears to us to be difficult to extend column lengths in the array over adjoining semiconductor dies, while (as will be discussed later in this document) we were able to arrange for extending row lengths in a CCD imager by designing semiconductor dies that could be abutted with others of their like. Further, problems appear in the long-column arrays because of charge transport factor limitations. But, with transversal scanning being done by optical displacement of the image field relative to a line CCD imager, the minimum length of a charge transfer stage no longer imposes a limitation on resolution in the direction transverse to line scan. As we will reveal, this becomes important in arranging for color discrimination by the CCD imager. 
     Color discrimination properties have been provided many ways in the prior art to CCD field imagers, because of the interest in developing cameras for color television broadcasting or simpler color television cameras for home use. In broadcast cameras a color-discriminating optical beam splitter has been used to separate incoming radiation into spectral components for application to separate CCD field imagers. These imagers generate video signals responsive to the spectral components they respectively receive. This approach involves close optical registration of the photosensing sites on the various imagers to preserve image resolution, so it seemed best to us to avoid this approach in the high-resolution satellite camera. 
     CCD field imagers have also been used in conjunction with color-pattern optical filters, either of a contact type or of a type using relay optics. This practice of using color pattern filters with imaging devices arose during the development of single-tube color cameras, which used color-pattern optical filters to place stripes of differing colors on their targets in superposition with scan lines. The various color responses in electric signal from radiation received by the camera were subsequently sorted out by line selecting means following the camera tube. Color stripe filters with stripes parallel to line scan have not been used in CCD field imagers to our knowledge. In part this may be because the minimum length of charge transfer stages readily contructed on a semiconductor die of reasonable size, using current silicon-device design rules, just about fulfills the vertical resolution requirements of broadcast television standards, so the loss of vertical resolution incurred with a horizontal color stripe filter would complicate device design. A more important reason, perhaps, is to obtain superposed picture element samples for the various color responses one must resort to transversal low-pass spatial filtering involving the use of time delays of substantial length (i. e. of line scan time length). In any case, the color-pattern optical filters employed with CCD field imagers employ color patterns more complex than simple color stripes or employ color stripes in the direction transverse to line scan. The superposing of picture element samples in the various color responses by low-pass spatial filtering in the line scan direction, which is required with this latter type of color stripe filter, does not need long time delays. 
     If one attempts to perform patterned-color filtering with a line imager analogous to the filtering provided for one row of the CCD field imagers with patterned-color filters, the photosensing sites in the line imager receive radiation selectively spectrally filtered line segment by line segment. That is, the pattern of filtering corresponds to that provided by a color-stripe filter having stripes in the direction transverse to line scan. The color-pattern filtering, or color-stripe filtering transverse to direction of line scan, undesirably reduces the resolution of the imager in direction of line scan. Attempting to magnify the image optically before projecting it into a lengthened line imager, as a way of maintaining spatial resolution despite line image segmentation by the color filter, is unattractive to do. Even though buttable linear arrays on respective semiconductor dies can be used to accommodate lengthening of the line array, the increased capacitance associated with the gate electrodes of the line imager undesirably cuts down the speed with which charge samples can be moved in the imager and converted to output voltage samples. 
     We provide for color discrimination in our CCD line imager in a surprising way. We use an area array of photosensing sites--rather than a linear array--and we use a color-stripe filter with the color stripes running in the row direction of the CCD imager,--and in the direction of line scan, in the line imager output signal. In the direction transverse to line scan the line image passing through an optical slit filter is beam split or defocussed in the transverse direction, before passage through the color-stripe filter. That is, the same line image is replicated for application to each row of charge sensing sites in the area array, that application being made through respective stripes of the color-stripe filters. Each row of photosensing sites in the array receives a different spectral response stripe, but each different spectral response is to one of the replications of the same line image. An area array of rows of photosensing sites in which successive rows of the sites receive response to the same line image, rather than to successive line images in an area image, we term a &#34;replicated line imager&#34;. Resolution in the direction of line scan is not compromised by such filtering. 
     The resolution in the transverse direction is determined by the optical slit filter, not by the imager, because we operate the area array as a replicated line imager. Scanning in the direction transverse to line scan still is accomplished by optical line selection. So we continue to avoid the limitation on resolution in this transverse direction imposed by the minimum length of a charge transfer stage in a field imager. 
     As noted above, the array of photosensing sites (i.e., the image, or A register) is arranged so the spectrally-filtered line images lie along the rows of the array, which are of extended length to provide high resolution in the direction of line scan. The columns of the array defined by the CCD charge transfer channels are short, facilitating the rapid transfer of line segment portions of the charge samples from the adjacent columns of the array into corresponding columns of a few-row field storage, or, B, register during relatively short transfer intervals between relatively long image integration times. After each transfer interval the charge samples can be advanced a row at a time in the field storage register with the row transferred out of the B register transferred in parallel into an output CCD line (or C) register for subsequent serial read-out to a charge sensing stage. This mode of operation is in many respects analogous to the field transfer method of charge sample extraction in field imagers first described by P. K. Weimer in U.S. Pat. No. 3,763,480 issued Oct. 2, 1973 and entitled &#34;DIGITAL AND ANALOG DATA HANDLING DEVICES&#34;. 
     The very few rows and short columns in our replicated line imager area array make the charge sample extraction behave differently from a field imager with 1:1 or 3:4 height-to-width aspect ratio, where the Weimer charge sample extraction scheme is commonly employed. A single row advance transfers a number of charge samples in parallel that is a significantly larger fraction of the total number of charge samples transferred from the image register to the field storage register(s) in the field transfer interval. This permits a shorter field transfer interval relative to image integration interval, which reduces the need for interrupting the projection of image into the imager during field transfer in order to avoid transfer smear. Transfer smear is an unwanted source of crosstalk between the lines of charge samples that adversely affects the purity of the different color responses. Similarly, the time for transfer from the field storage register(s) to the output register(s) can be a substantially smaller fraction of the time between field transfer intervals. The proportion of time scan lines can be serially read out of the image output register(s) to the time they cannot is significantly higher than with a field imager, and this helps to keep the clocking rate of the output registers lower. Also the short columns of the image and field storage registers, despite the high resolution of the imager in the direction transverse to line scan, avoids the introduction of problems that would be associated with many signal charge transfers through those CCD registers. 
     Having solved the problem of providing high resolution in the direction transverse to line scan, the remaining problems with regard to a high-resolution CCD imager mostly concern obtaining the desired high resolution in the direction of line scan. The limitation on this resolution is imposed chiefly by the minimum length of the charge transfer stages in the output line (or C) register(s). Dividing this length (as determined by current silicon device design rules) into the distance between opposing parallel edges of a reasonable-size (by current standards) semiconductor die, we determined that the satellite camera would require a number of abutted such dies to obtain the number of picture elements per scan line required. The close abutting of photosensing elements on adjacent dies, required to maintain high resolution in the line scan direction, necessitate new layout techniques for situating the imager on the die. 
     Using abutted semiconductor dies with component line imagers, to provide a composite line image capable of sensing a longer line image at given resolution or of providing greater resolution for given line image length, means output registers on the dies need not operate at the high rate required of a single, long output register. That is, time-division-multiplexing of the output registers on the semiconductor dies can be eschewed in favor of spatial-multiplexing to cut the clocking rate required of the registers. In spatial multiplexing the imager output registers are read out in parallel at the same time. 
     Spatial-multiplexing can be carried further using a plurality of parallelly clocked output registers on the same semiconductor die for the component line imager. Then, too, the number of stages in each output (or C) register becomes of concern with regard to charge transfer efficiency being less than perfect and giving rise to transfer inefficiency noise. With the semiconductor die size we contemplated using, we decided that half the charge transfer channels used for transfer storage should be served by one output (or C) register; and the remaining half, by another output register. 
     Our initial concept of the layout of the replicated line imager on the semiconductor die, so abutting component line imagers to form a composite line imager would be facilitated was as follows. The rows of an image (or A) register would extend between the opposing edges of the die at least one of which would abut an adjoining die. The rows of a field storage (or B) register would also stretch between the edges, and its columns would continue from respective columns of the A register. The final charge transfer stages in the charge transfer channels making up the columns in a half of the B register closest to one edge of the die would connect by a fan-in structure to respective ones of the successive charge transfer stages in one of the two output (C) registers, and the other output register would have the final charge transfer stages in the other charge transfer channels of the B register connected to it analogously. 
     We conceived using a common electrometer, or charge sensing stage, centrally located between the opposing abuttable edges of the die, for both output registers, which output registers would be clocked for charge transfer in opposite directions towards the electrometer. The electrometer was to be a field effect transistor with gate connection to floating diffusions in each of the output registers. The central location of the electrometer would tend to keep elements away from the edges of the die that were adapted for abutting an adjoining die and reduce the amount of fan-in between the field storage register halves and their corresponsing output registers. Using a common electrometer for the two output registers, rather than separate ones, we believed would avoid congestion in the central portion of the semiconductor die. 
     While this concept of using plural output registers which charge transfer away from the opposing abuttable edges and towards charge sensing circuitry well within the confines of the semiconductor die top-surface boundary was retained in our subsequent camera development, we found a number of practical problems with our initial lay-out conception that tended to adversely affect the fabrication yield of the imager dies. Using a common electrometer stage for the two output registers on each die involved 90° turns within 15 microns at the ends of those registers, which gave trouble. The busses carrying clocking signals to gate electrodes of the A and B registers had to cross the C registers, so avoiding clocking cross-talk was difficult. Bus routing problems were so severe that we could find no way to use anti-blooming drains, owing to the difficulty of making connections to the drains. 
     We found these problems could be avoided with a layout of the following type. The image (or A) register still extends from a first edge of the semiconductor die to a second opposing edge, but is divided into halves along a boundary midway between the first and second edges of the die. The A1 and A2 registers that are the respective halves of the A register are arranged for charge transfer in opposing directions to respective B1 and B2 field storage registers during charge transfer intervals. During subsequent image integration times when clocking is halted in the A1 and A2 registers, charge samples are clocked out of the B1 and B2 registers in the same directions as they were clocked in, being clocked in parallel into respective C1 and C2 output registers for conversion to serial format. Charge samples are serially clocked from the C1 and C2 registers towards the center of the die to be sensed in separate charge sensing circuits. 
     SUMMARY OF THE INVENTION 
     A primary aspect of the invention is a television camera using a replicated line imager architecture in a CCD imager, means for acquiring radiation defining a line image and a spectrum-discriminating striped optical filter system receptive of the line image for projecting selectively filtered response stripes to respective line imager portions of the CCD imager. Further aspects of the invention concerns replicated line imager architectures and line imager architectures which facilitate abutting of imager segments on adjoining semiconductor dies to obtain extended line imager length. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of how edge-abutted CCD imagers of the sort embodying the invention are arranged to receive color-discriminated line images; 
     FIG. 2 is a diagram showing the general architecture of the VIS/NIR sensor which embodies our invention and is used as a component segment of the linear imager in the satellite camera; 
     FIG. 3 is a diagram showing in circular inset a detail of the FIG. 2 architecture; 
     FIG. 4 is a cross-sectional view of the VIS/NIR sensor image register; and 
     FIG. 5 is a simplified plan view of the VIS/NIR sensor, shown with reduced length in the left/right direction for ease of illustration. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1 an imager 1 and an imager 2 are edge-abutted at an interface 3 running in a transverse direction respective to the line direction, in which line direction extend the line images supplied to photosensing sites on the imagers 1, 2. These photosensing sites (not specifically shown) are arranged in rows underlying the color-selective stripes of a contact type color-stripe filter 4. A strip 5 of an image field 6 is selected by optics 7 for line image scanning. Optics 7 projects a multiple line image through the respective stripes of color-stripe filter 4 to respective rows of photosensing sites on both imager 1 and imager 2, or projects a line image astigmatic in the transverse direction through all the stripes of color-stripe filter 4. 
     Color-stripe filter 4, shown as being a contact type disposed directly on surfaces of imager 1 and imager 2 aligned in a plane, alternatively may be located in the focal plane of relay optics between optics 7 and the imagers 1, 2. To avoid needing transparent gate electrodes, imagers 1 and 2 in our satellite camera were CCD imagers of the back-illuminated type. In these, radiant energy enters the CCD imager through the surface of the semiconductor die opposite its surface on which the gate electrodes of the charge transfer devices are disposed. Silicon semiconductor dies on which back-illuminated CCD imagers are constructed are thinned to facilitate the penetration of radiation, particularly at the blue end of the visible spectrum, and then are mounted on a glass plate transparent to the visible and near infrared (NIR) spectrum. Alternatively, front-illuminated CCD imagers can be used with the invention. With any of these variants the surfaces of imagers 1 and 2 upward in FIG. 1 are provided with masks 8, 9 (shown in stipple in FIG. 1). These masks are opaque to incident radiation, except for those portions of the imager surfaces through which line images selectively filtered by color-strip filter 4 are projected. 
     Optics 7 are for the most part conventional in design. They will include a spatial filter with slit aperture running in line direction and usually will make use of cylindric lens for increased light collection. Where the television camera does not translate respective to image field 6 in the transverse direction, as was the case with our satellite camera, optics 7 may include an oscillating mirror for scanning in the transverse direction. The most significant departure from conventional optics design for CCD line imagers is the inclusion of a beam splitter to provide for parallel component line images, or the inclusion of lens to introduce astigmatism in the transverse direction so the line image spreads out in that direction to cover parallel rows of photosensing sites. 
     FIG. 2 is a diagram (similar to one used in a NASA design review) of the architecture of the portion of the replicated line imager that appears on one monolithic die of our camera; this portion of the imager is referred to as the &#34;VIS/NIR sensor&#34; since it is used to sense both the visible and near infrared components of wide-spectrum light reflection from an illuminated object. Its image or A register is a composite register that stretches across the middle of FIG. 2, being composed of a component A 1  register on the left and a component A 2  register on the right. 
     The A 1  register and a following first transfer storage, or B 1 , register each comprise 2 9  parallelled charge transfer channels, or columns, those of the B 1  register being connected in cascade after respective ones of the A 1  register. The 2 9  charge transfer channels of the B 1  register then connect to respective ones of the successive charge transfer stages in a first output line, or C 1 , register. The 2 9  parallelled charge transfer channels in the A 1  and B 1  registers and the 2 9  serial charge transfer stages of the C 1  registers cannot be drawn on a normal size sheet, and the dimensioning in this direction is represented in abstract form by the initial and final ordinal numbers &#34;1&#34; and &#34;512&#34; of these structures at the bottom of FIG. 2. 
     The A 2  register and a following second storage, or B 2 , register each comprise 2 9  paralleled charge transfer channels, or columns, those of the B 2  register being connected in cascade after respective ones of the A 2  register. The 2 9  charge transfer channels of the B 2  register then connect to respective ones of the successive charge transfer stages in a further output line, or C 2 , register. The 2 9  parallelled charge transfer channels in the A 2  and B 2  registers and the associated charge transfer stages in the C 2  register are ordinally numbered &#34;513&#34; through &#34;1024,&#34; as indicated by these numbers appearing at the top of FIG. 2. C 1  and C 2  registers are shown each with a few further stages at their ends. 
     The columns of the A 1  and A 2  registers may have blooming drains between them. These blooming drains are the &#34;teeth&#34; of one of two &#34;comb&#34; structures BD 1  and BD 2 , each drain being connected at one of its ends to one of two drain buses forming the &#34;backs&#34; of the &#34;comb&#34; structures BD 1  and BD 2 , which buses have respective connections for accessing from off-die. The accessibility of the blooming drain structures BD 1  and BD 2  for off-die connection is a feature of the FIG. 2 imager architecture. 
     Dashed lines in the A 1  and A 2  registers indicate the locations of rows of charge storage stages in bands respectively associated with the red (R) stripe, the blue (B) stripe, the green (G) stripe and the near infrared (NIR) stripe of the color-stripe filter 4 of FIG. 1. In FIG. 2 each row indicated by dashed line is to be viewed as being associated with a respective charge transfer stage in each of the 2 10  charge transfer channels of the A 1  and A 2  registers. That is, each of these charge transfer channels consists of four charge transfer stages in series; and, during image integration times when A 1  and A 2  register clocking is halted, these four charge transfer stages collect charge carriers generated respectively by photoresponse to R, G, B and NIR components of a line image segment. 
     During each replicated-line-image-transfer time interval, interspersed among image integration intervals, the clocking of the A 1  and A 2  component image registers is resumed. The ones of the successive charge transfer stages in each charge transfer channel (or column) of a CCD register which align in the direction orthogonal to the column are considered as forming a row in that register. The charge packets accumulated in the four rows of the A 1  register during an image integration time are transferred to corresponding rows of the B 1  register by clocking these A 1  and B 1  registers synchronously during the ensuing replicated-line-image transfer interval; and the charge packets accumulated in the four rows of the A 2  register are transferred to corresponding rows of the B 2  register by clocking these registers synchronously. The B 1  and B 2  registers are provided with more rows than the A 1  and A 2  registers, and the synchronous clocking of these registers is continued after charge packets descriptive of line image have been clocked out of the A 1  and A 2  registers into the B.sub. 1 and B 2  registers, respectively. This transfers a row of smear charge samples into each of the B 1  and B 2  registers behind their respective rows of IR, B, G and R samples. The CCD replicated line imager is like the field transfer type of CCD area imager in that: when operated open-shutter during transfer from image register, or when operated shutterless, the imager is subject to transfer smear. The generation of transfer smear has been described in detail by P. A. Levine in his U.S. Pat. No. 4,010,319 issued Mar. 1, 1977 and entitled &#34;SMEAR REDUCTION IN CCD IMAGERS&#34;. The collection of smear charge samples by empty-well clocking, as is done in the NASA satellite camera herein described, is described in detail in P. A. Levine&#39;s U.S. patent application Ser. No. 554,085 filed Nov. 21, 1983, now U.S. Pat. No. 4,567,524, entitled &#34;SMEAR REDUCTION IN CCD IMAGERS USING EMPTY WELL CLOCKING&#34;, and assigned to RCA Corporation. 
     In the ensuing image integration time, when A 1  and A 2  register clocking is again halted, B 1  and B 2  register forward clocking continues intermittently to advance lines of charge packets in parallel from one row to the next in each of the B 1  and B 2  registers. The lines of charge packets advanced out of the B 1  and B 2  registers are parallelly loaded respectively into the charge transfer stages of the C 1  register and into the charge transfer stages of the C 2  register, while C 1  and C 2  clocking is halted. B 1  and B 2  register clocking is at relatively low rate and after each line advance, with the stages of the C 1  and C 2  registers having been parallelly loaded with charge packets, the C 1  and C 2  registers are clocked at relatively high rate to transfer these charge packets in shift register operation. This operation supplies charge packets from registers C 1  and C 2  serially to an electrometer stage E 1  and to an electrometer stage E 2 , respectively. Electrometer stages E 1  and E 2  are floating-diffusion output stages in the NASA satellite camera. 
     FIG. 3 is a diagram (similar to one used in NASA design review), which shows at top a stylized representation of the FIG. 2 architecture with a circular area at the adjoining edges of the A 1  and A 2  registers being indicated by stippling, and which shows in circular inset at bottom an expanded detail view of gate electrode structure in the indicated circular area. FIG. 3 is useful in understanding how the A 1  and A 2  registers are clocked for charge transfer in opposing directions. Each of the first-layer polysilicon gate electrodes φ 1A , shown in heavy stipple and receptive of a first phase Φ 1A  of three-phase A register clocking signal, extend straight across both A 1  and A 2  component registers of the complete A register. The second-layer polysilicon gate electrodes φ 2A , shown in crosshatch and receptive of a second phase Φ 2A  of three-phase A register clocking signal, overlap the bottom edges of the first-layer polysilicon gate electrodes in the A 1  register shown at the left of the FIG. 3 blown-up inset; but they overlap the top edges of the first-layer polysilicon gate electrodes in the A 2  register shown at the right of the FIG. 3 blown-up inset. A third-layer of polysilicon is a sheet electrode φ 3A  which extends over the entire gate electrode structure thusfar described and receives a third phase Φ 3A  of three-phase A register clocking signal. So, during image transfer times three-phase A register clocking signals are in progressive succession Φ A1 , Φ A2 , Φ A3  to transfer charge packets in the forwarded direction from top to bottom in the A 1  register and from bottom to top in the A 2  register. During image integration times the buried CCD in n-type silicon bulk has its second- and third-layer polysilicon gate electrodes held relatively negative and has its first-layer polysilicon gate electrodes held relatively positive. Consequently, charge carriers generated by photoconversion are collected under the first-layer polysilicon gate electrodes. 
     FIG. 4 is a cross-section of the laminated CCD imager and color-stripe filter assembly, in the image register region. The cross-section is taken transverse to the gate electrode structure. The thinned CCD imager 10 per se is connected by a layer 11 of epoxy to a relatively thick glass support plate 12 shown in broken-view. CCD imager 10 is formed in a silicon substrate 13 of p-type silicon; and the CCD structures are made to be of buried type, for which purpose a thin region 14 of n-type silicon overlies substrate 13. (The bottom surface of the p-type silicon substrate 13 is made p+to provide a drift field into the substrate to avoid back surface recombination noise; this detail is not shown in FIG. 4.) 
     A three polysilicon layer gate electrode structure overlies region 14. A passivated silicon dioxide structure 15 extending over the surface of region 14 has disposed therein a succession of storage gate electrodes 16-1, 16-2, 16-3 located in the first polysilicon layer and overlapped at their trailing edges by the leading edges of respective one of transfer gate electrodes 17-1, 17-2 located in the second polysilicon layer. The third layer 18 of polysilicon forms a sheet electrode providing transfer gates between each transfer gate electrode 17-1, 17-2 in the second polysilicon layer and the succeeding storage gate electrode 16-2, 16-3 in the first polysilicon layer. The effective length of the storage gates is 25 μm; the effective lengths of the transfer gates following them are 20 μm and 15 μm; and the silicon substrate 13 is thinned to 12 μm thickness. The methods for thinning substrate 13 and for making the gate structure are well-known in the art. 
     The storage gate electrodes 16-1, 16-2, 16-3 in the first layer of polysilicon have Φ 1A  clocking voltage applied to them; the transfer gate electrodes 17-1, 17-2 in the second layer of polysilicon have Φ A2  clocking voltage applied to them; and the transfer gate &#34;electrodes&#34; provided by the sheet electrode 18 in the third layer of polysilicon have Φ 3A  clocking voltage applied thereto. Integration of charge carriers generated by photoconversion is done in substrate 13 in potential wells induced under the storage gates 16-1, 16-2, 16-3 in the first layer of polysilicon. Light, as indicated by wavy arrows, enters silicon substrate 13 from the &#34;back&#34; surface (i. e. the bottom surface as shown in FIG. 4 and as considered by a semiconductor die designer), coming through slits (shown in cross section) in a metal mask 19 evaporated on the surface of glass support plate 12 cemented to substrate 13. These slits are centered under the storage gate electrodes 16-1, 16-2, 16-3 providing a 15 μm aperture. Color-selective stripe filters (e.g. 20, 21) are laid down over these slits and epoxy flows around these filters in forming the otherwise-three-micrometer thick layer 11 when substrate 13 is cemented to glass support plate 12. Support plate 12 is transparent to visible light and near-IR which enters at the surface appearing at the bottom of FIG. 4, which surface is provided per convention with an anti-reflective coating (not shown in FIG. 4). 
     FIG. 5 shows the front surface of a back-illuminated CCD imager viewed through the thinned semiconductor die and opposite back surface. Three-phase clocking is used in the FIG. 5 imager, which is of the type CCD imagers 1 and 2 of FIG. 1 are in our satellite camera. The first and second layers of polysilicon gate electrodes are shown in stipple and in cross-hatch, respectively. The third layer of polysilicon electrodes comprises area electrodes each covering a complete CCD register, and the visible portions of these area electrodes are shown without stipple or cross-hatch. 
     The composite image register comprises component image registers respectively denominated A 1  and A 2 . The gate electrodes in first layer of polysilicon are continuous across both the A 1  and A 2  registers, and during image integration times the collection of charge carriers generated by photoconversion takes place in the potential energy wells induced by relatively positive voltages in these gate electrodes. The gate electrodes in the second layer of polysilicon jog in position at the juncture between A 1  and A 2  registers, in effect changing the order in these registers of these second-layer gate electrodes with the portions of the area electrode in the third layer of polysilicon not electrostatically shielded against by the second-layer gate electrodes. This arranges the A 1  and A 2  registers for charge transfer in opposing directions during field transfer times when normal three-phase clocking resumes, (rather than clocking being halted as during image integration, with the first-layer gate electrodes being maintained relatively positive and the second-layer and third-layer gate electrodes being maintained relatively negative). 
     There are four first-layer gate electrodes and 2 9  columns in each of the A 1  and A 2  component image registers. So there are four rows of 2 10  photosensing sites in the composite image register. The large number of photosensing sites per row makes it impractical to show separately each column of the A 1  and B 1  registers and of the A 2  and B 2  registers, or to show each charge transfer stage of the C 1  and C 2  registers arranged to be sideloaded respectively from the B 1  and B 2  registers. So, there is considerable foreshortening in FIG. 5 of the extent of the VIS/NIR sensor from left to right. The further charge transfer stages in the C 1  register, not explicitly shown, are implicitly indicated by the arrow specifying charge transfer in the righthand direction during serial read-out to electrometer stage E 1  ; and, similarly, the further charge transfer stages in the C 2  register, by the arrow specifying charge transfer in the lefthand direction during serial read-out of register C 2  to output electrometer stage E 2 . 
     During field transfer intervals the A 1  image register transfers charge packets through the charge transfer channels forming its respective columns into charge transfer channels forming the columns of a transfer storage B 1  register. And the A 2  image register transfers charge packets through the charge transfer channels forming its respective columns into charge transfer channels forming the columns of a transfer storage B 2  register. There is synchronous three-phase clocking of the A 1  and B 1  registers and of the A 2  and B 2  registers during field transfer intervals, and this synchronous clocking continues for one row advance after the rows of the A 1  and A 2  registers are cleared of charge packets descriptive of picture element samples. The B 1  and B 2  registers have five rows apiece; and at the conclusion of field transfer a row of transfer smear response samples in each of these registers together with a row of R response samples, a row of G response samples, a row of B response samples and a row of NIR response samples. The generation of transfer smear samples by clocking a phantom row of charge samples across an image register, and the ways in which such transfer smear samples are used to improve CCD imager output signals are explained in detail by P. A. Levine in his U.S. Pat. No. 4,567,524. 
     During each image integration interval subsequent to a respective field, transfer clocking is halted in the A 1  and A 2  registers with Φ 2A  and Φ 3A  phases which are held low, or relatively negative in potential. Charge carriers generated by photoconversion in the silicon substrate called under the gate electrode which is receptive of Φ 1A  phase held high and is nearest to the site of their generation. The lines of charge packets transferred to the B 1  and B 2  registers are clocked to advance lines of charge packets in ranks from one row to the next at selected times within the image integration interval, with the last lines transferred out of the B 1  and B 2  registers side-loaded in parallel into the charge transfer stages of the C 1  and C 2  registers, respectively. During this side-loading process clocking is halted in the C 1  and C 2  registers to condition their respective charge transfer stages to accept charge packets transferred from respective columns of the B 1  and B 2  registers. After the C.sub. 1 and C 2  registers are side-loaded in parallel with lines of charge packets, C 1  is clocked to transfer the charge packets therein serially to electrometer output stage E; and C 2  is clocked to transfer the charge packets therein serially to electrometer output stage E 2 . Best modulation transfer factor (MTF) is obtained at lower C 1  and C 2  clocking rates, so it is advantageous to forward clock C 1  and C 2  registers in parallel using spatial division multiplexing of the E 1  and E 2  outputs. But one of the C 1  and C 2  registers may be forward clocked to transfer all image samples out of it, then the other one forward clocked to transfer all image samples out of it, in a time division multiplexing alternative mode of operation. 
     One skilled in the art of CCD imager design will notice the similarities of the charge transfer operations in th replicated line imager to the charge transfer operations in area imagers of field transfer type. FIG. 5 is of primary interest in discussing in more detail the layout advantage of the replicated line imager architecture shown in more abstract form in FIG. 2, particularly with regard to the solution of the problems with the routing of clocking voltage buses. 
     The first and second straight-line edge boundaries 31, 32 of the monolithic die top surface which may abut corresponding second and first boundaries of the top surfaces of adjoining similar monolithic dies are related to the FIG. 5 plan view as follows. The left ends of the A 1  and B 1  registers and the left end of the C 1  register align along the first straight-line edge boundary 31 of the monolithic die top surface. The right ends of the A 2  and B 2  registers and the right end of the C 2  register align along the second straight-line edge boundary 32 of the monolithic die top surface. 
     The more important bond pads for connection of the CCD imager die to its package pin-out are shown in FIG. 5 as little boxes, each surrounding the designation of the signal to flow there through which may also be considered as &#34;identification numeral&#34; for the bond pad. The bond pads for the imager are on the top surface of the die along third and fourth boundaries 33, 34 of the surface respectively at bottom and top of FIG. 5 and both perpendicular to the first and second boundaries of the surface; this is done to facilitate the abutting of monolithic dies to obtain the lengthened replicated line imager. The output connections of the electrometer output stages E 1  and E 2  are actually closer to the center of the monolithic die than appears in FIG. 5, which is illustrated with reduced length in the left/right direction. These connections are to bond pads located centrally along the third and fourth boundaries, 33, 34 respectively, of the imager front-side surface. Clockwise (as viewed from the backside of the imager per FIG. 5) along the third boundary 33 from the V 1  bond pad to which E.sub. 1 output connection is made are positioned Φ 1C1 , Φ 2C1 , Φ 3C1  bond pads to which buses for the clocking voltages of C 1  register connect; and clockwise along the fourth boundary 34 from the V 2  bond pad to which E 2  output connection is made are positione φ 1C2 , φ 2C2 , φ 3C2  bond pads to which buses for the clocking voltages of the C 2  register connect. 
     The C 1  and C 2  registers have &#34;fat zero&#34; (FZ) bias charges sideloaded into charge transfer stages at their left and right ends, respectively, by charge injection circuitry F 1  and F 2 , respectively, at the bottom and at the top of FIG. 5 near the third and fourth boundaries of the front surface of the imager. These fat zero charges are clocked through the C 1  and C 2  registers to occupy their charge transfer stages as they are emptied of charge packets descriptive of image samples. Bond pads for application of voltages to control &#34;fat zero&#34; level, if used, would be located in a far left position along the third boundary 33 and in a far right position along the fourth boundary 34. 
     The φ 1B1  and φ 2B1  and gate electrodes of register B 1  and the φ 1B2  and φ 2B2  electrodes of register B 2  are the &#34;teeth&#34; of four &#34;comb&#34; structures having their backs near die center. The backs of the comb structures providing φ 1B1  and φ 2B1  gate electrodes and the sheet electrode providing φ 3B1  gate electrodes are ohmically contacted at their right edges by metal buses connecting to φ 3B1 , φ 2B1 , φ 1B1  bond pads located counter-clockwise (as viewed from the side of the imager shown in FIG. 5) from the electrometer output stage E 1  output bond pad V 1 . The backs of the comb structures providing φ 1B2  and φ 2B2  gate electrodes and the sheet electrode providing φ 3B2  gate electrodes are ohmically contacted at their left edges by metal buses connecting to φ 3B2 , φ 2B2 , φ 1B2  bond pads located counter-clockwise (as viewed from the side of the imager shown in FIG. 5) from the electrometer output stage E 2  output bond pad V 2 . 
     Note the clocking voltage buses to the C 1  and C 2  registers do not run over any clocking voltage buses of the other registers. Nor do the clocking voltage buses to the B 1  and B 2  registers run over the clocking voltage buses to the A 1  or A 2  registers. So, the likelihood of the magnitudes of charge packets in the CCD registers being perturbed by clock noise is substantially de minimus. 
     The gate electrode structures in register A 1  receptive of the Φ 3A1 , Φ 2A1  and Φ 1A1  clocking signals ohomically contacted by metal buses connecting to φ 3A1 , φ 2A1 , φ 1A1  bond pads located in the leftmost positions along the top boundary 34 of the imager front-side surface. The gate electrode structures in register A 2  receptive of Φ 1A2 , Φ 2A2 , and Φ 3A2  clocking signals are ohmically contacted by metal buses connecting to φ 1A2 , φ 2A2 , φ 3A2  bond pads located in the rightmost positions along the bottom boundary 33 of the imager front-side surface. 
     Bond pads for drain voltages and substrate drain voltages (not shown) are suitably interspersed between sets of the bond pads thusfar described. The foregoing description should make clear that the FIG. 2 architecture for the replicated line imager provides straightforward accessibility of the various areas of the chip for metal bus connection to bond pads along the top and bottom edges of the dies without need for cross-unders or tunnels. 
     In the color-discriminating replicated line imager used in the satellite camera, the maintenance of color purity in the lines of charge packets responsive to different filterings of light energy is a primary concern, and transfer smear degrades color purity. To reduce transfer smear insofar as possible, the transfers of charge packets from A 1  to B 1  register and from A 2  to B 2  register are made as fast as possible. The fast clocking thus necessitated and the extreme width of the gate electrodes in the A 1 , B 1 , A 2  and B 2  registers makes low-pass filtering of clocking voltages, as imposed by the distributed resistances of the polysilicon gate electrodes and their distributed capacitances, a considerable problem. The connection through from A 1  register to A 2  register of similarly clocked polysilicon gate electrodes, together with the imposition of clocking voltages at both ends of the composite A register thus provided, helps reduce this problem in the center of the composite A register by parallelling two distributed resistances back from the distributed capacitance to clock voltage drive sources. 
     This problem is further reduced by exploiting the per-unit-length resistivity of top aluminization busses being lower than that of polysilicon gate electrodes. The A register gate electrodes of like phasing have interconnection by top aluminization not only at their ends, but at two locations along their lengths. These interconnections are then parallelled by top aluminization bus connections superposed over certain of the gate electrodes clocked by the very clocking voltages the bus connections carry. This further reduces the effective distributed resistances of the φ 1A1 , φ 2A1 , φ 3A1 , φ 1A2 , φ 2A2 , and φ 3A2  gate electrodes at most points along their lengths to permit faster A register clocking during image transfer intervals. For similar reasons the B 1  and B 2  registers have interconnections of like-phase gate electrodes at their ends and midway along their lengths, to which clocking voltages are applied by top aluminization bus connections superposed over certain of the gate electrodes clocked by the very clocking voltages the bus connections carry. The running of the clocking voltage top aluminization bus connections over polysilicon gate electrodes, to which are applied the voltages the bus connections carry, avoids undesirable clocking voltage cross-talk to the gate electrodes. 
     As the technology of making imperfection-free momolithic semiconductor devices improves, so longer die sizes become more practical, more complex CCD imager architectures which utilize the teachings of our invention may become attractive to use. The image sensing sites in these CCD line imagers may be apportioned into 2N image registers, where N is a positive integer larger than one, with a corresponding number of transfer storage registers disposed on alternate sides of the composite image register, with a corresponding number of output registers for performing parallel-to-series conversion, and with electrometer stages disposed away from the edges of the die for sensing the charge packets serially supplied from the output registers. In other words architectures where a plurality N of architectures per FIGS. 2 and 5 are disposed side by side on a single monolithic semiconductor die, with image register rows in alignment, are possible. The apportionment of image sensing sites among 2N component image registers will still be desirable for avoiding the problem of transfer efficiency introducing line shading in a very long line imager. There is additional flexibility in these extended architectures with regard to the positioning of the electrometer output stages with respect to the ends of output line (C) registers not at the edges of the die; the electrometer stages can be at either end of one of these output line (C) registers. Furthermore, certain of these architectures with 2N image registers, N being greater than one, can be modified to archtectures with 2N-1 image registers by lopping off one of the end component image (A) registers and its associated transfer storage (B) and output line (C) registers. 
     Our teaching with regard to dividing a line imager image register to supply ranks of charge packets to a plurality of output registers alternatively placed on opposite sides of the image register is applicable to certain simpler CCD imager architectures. A line imager with a single row image register and no transfer storage register may, for example, use two or more output registers alternately placed on opposite sides of the image register. 
     Such a line imager with two output registers is configured on a monolithic die so as to be abuttable with other line imagers to form an extended line imager, in an alternative satellite camera to the embodiment just described. Four extended line imagers are used, the image register of each irradiated with a line image of a different one of the R, G, B and NIR spectral components. In this alternative satellite camera, which is more complex than the camera we have described in detail, the problem of transfer smear is avoided in the imagers themselves. 
     The scope of the claims which follow should be construed taking into consideration such alternative embodiments of our invention.