Abstract:
In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Description:
[0001]     This application is a divisional of U.S. application Ser. No. 11/301,854, filed on Dec. 13, 2005, which relies for priority upon Korean Patent Application No. 10-2005-0015041, filed on Feb. 23, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a split gate flash memory device having a self-aligned control gate and a method of manufacturing the same.  
         [0004]     2. Description of the Related Art  
         [0005]     Non-volatile semiconductor devices electrically store and erase data and can retain data even when power is turned off. Accordingly, non-volatile semiconductor devices enjoy widespread use in various fields, including portable electronics.  
         [0006]     As one type of non-volatile memory device, a split gate flash memory device includes a floating gate (or a storage node) and a control gate that are separated from each other. The floating gate is electrically isolated from the external environment, and stores information using the characteristic that the current of a memory cell varies according to electron injection (writing) to the floating gate and electron removal from the floating gate (deleting). For example, electron injection to the floating gate is conducted by channel-hot electron injection (HEI), and electron removal from the floating gate is conducted by Fowler-Nordheim (F-N) tunneling through an inter-gate insulating layer that is present between the floating gate and the control gate.  
         [0007]     Referring to  FIG. 1 , a conventional split gate flash memory device includes a floating gate  15  and a control gate  20 , which are disposed between a source region  25   a  and a drain region  25   b . The control gate  20  and the floating gate  15  share a portion of a substrate  10 , that is, a channel region between the source and drain regions  25   a  and  25   b , respectively, and the control gate  20  surrounds a sidewall and lies on a portion of a top surface of the floating gate  15 .  
         [0008]     By forming the control gate  20  in this manner, an electric field between the floating gate  15  and the control gate  20  is enhanced, and the problem of punch-through between the source and drain regions  25   a  and  25   b  can be solved. Such a split gate flash memory device is disclosed in U.S. Pat. No. 5,067,108.  
         [0009]     In the split gate flash memory device, as the control gate  20  is formed by an individual patterning process, an overlap area between the control gate  20  and the channel region varies from chip to chip, lot to lot, or wafer to wafer. Accordingly, cell threshold voltage and device characteristics vary from chip to chip, lot to lot, or wafer to wafer.  
         [0010]     Further, since the control gate  20  and the floating gate  15  are formed on the same plane to share the channel region, the cell size of the split gate flash memory device is about 50% larger than that of a stack type flash memory device. Accordingly, it is more difficult to scale down the split gate flash memory device as compared to the stacked flash memory device.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention provides a flash memory device that can maintain an enhanced electric field between a control gate and a storage node (floating gate) while reducing the cell size.  
         [0012]     The present invention further provides a flash memory device which can reduce the cell size and maintain a uniform overlap length between a channel region and each of a control gate and a storage node (floating gate).  
         [0013]     The present invention also provides a method of manufacturing such a flash memory device.  
         [0014]     According to an aspect of the present invention, there is provided a flash memory device comprising: a semiconductor substrate having a source region and a drain region that are spaced apart from each other; a spacer-shaped control gate formed between the source region and the drain region of the semiconductor substrate; and a storage node formed on a region between the control gate and the semiconductor substrate.  
         [0015]     In one embodiment, a bottom surface of the control gate includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node.  
         [0016]     In another embodiment, the device further comprises an insulating layer between the storage node and the control gate and between the storage node and the semiconductor substrate. In another embodiment, the device further comprises an insulating layer between the first region of the control gate and the semiconductor substrate. In another embodiment, the device further comprises silicide layers formed on the control gate and the source and drain regions.  
         [0017]     In another embodiment, the control gate comprises: a first conductive spacer disposed on the storage node; and a second conductive spacer disposed on a sidewall of the first conductive spacer. In another embodiment, the device further comprises an insulating layer interposed between the first conductive spacer and the second conductive spacer. In another embodiment, the device further comprises a silicide layer formed on the control gate to connect the first conductive spacer and the second conductive spacer.  
         [0018]     In another embodiment, the control gate comprises: a first conductive spacer disposed on the storage node; and second conductive spacers disposed on both sidewalls of the first conductive spacer. In another embodiment, the device further comprises an insulating layer interposed between the first conductive spacer and each of the second conductive spacers that are disposed on both sidewalls of the first conductive spacer. In another embodiment, the device further comprises a silicide layer formed on the control gate to connect the first conductive spacer and the second conductive spacers.  
         [0019]     In another embodiment, the storage node is closer to the source region than to the drain region.  
         [0020]     In another embodiment, the storage node comprises a material selected from the group consisting of silicon nitride, polysilicon, silicon dot, silicon germanium, and nano crystal.  
         [0021]     According to another aspect of the present invention, there is provided a flash memory device comprising: a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions; a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions; and a storage node formed in a predetermined portion between each control gate and the semiconductor substrate, wherein a bottom surface of each control gate includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node, wherein the pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.  
         [0022]     In one embodiment, the flash memory device may further comprise an insulating layer interposed between the storage node and the control gate and between the storage node and the semiconductor substrate. The flash memory device may further comprise an insulating layer between the first region of the control gate and the semiconductor substrate.  
         [0023]     In another embodiment, each of the control gates may comprise: a first conductive spacer disposed on the storage node; and a second conductive spacer disposed on a sidewall of the first spacer. The flash memory device may further comprise an insulating layer interposed between the first conductive spacer and the second conductive spacer. The flash memory device may further comprise a silicide layer formed on the control gate to connect the first conductive spacer and the second conductive spacer.  
         [0024]     In another embodiment, each of the control gates may comprise: a first conductive spacer disposed on the storage node; and second conductive spacers disposed on both sidewalls of the first conductive spacer. The flash memory device may further comprise an insulating layer between the first conductive spacer and each of the second conductive spacers that are disposed on both the sidewalls of the first conductive spacer. The flash memory device may further comprise a silicide layer formed on the control gate to connect the first conductive spacer and the second conductive spacers.  
         [0025]     In another embodiment, each storage node may be closer to the source region than to the corresponding drain region.  
         [0026]     According to still another aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method comprising: forming a storage node layer on a semiconductor substrate; forming a dummy layer within the storage node layer to separate the storage node layer into at least two storage nodes; and forming spacer-shaped control gates on both sidewalls of the dummy layer so that each control gate covers a sidewall and a top surface of a corresponding storage node.  
         [0027]     In one embodiment, a semiconductor tunnel oxide layer, a storage node layer, a first gate insulating layer, and a damascene molding layer are sequentially stacked. A dummy layer is formed using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer and the tunnel oxide layer. Dummy spacers are formed on both sidewalls of the dummy layer. The gate insulating layer, the storage node layer, and the tunnel oxide layer are etched using the dummy spacers as masks, thereby defining the storage node. The dummy spacers are removed. A second gate insulating layer is formed on the resultant semiconductor substrate. Conductive spacers are formed on the sidewalls of the dummy layer and the storage node, thereby forming control gates. The dummy layer is removed. A lightly doped impurity and a pocket impurity are implanted into exposed portions of the semiconductor substrate, and insulating spacers are formed on both sides of the second conductive spacers. A heavily doped impurity is implanted into the semiconductor substrate outside the insulating spacers, thereby forming source and drain regions.  
         [0028]     In another embodiment, a semiconductor tunnel oxide layer, a storage node layer, a first gate insulating layer, and a damascene molding layer are sequentially stacked. A dummy layer is formed using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer. First conductive spacers are formed on sidewalls of the dummy layer. The gate insulating layer, the storage node layer, and, the tunnel oxide layer are etched using the first conductive spacers as masks, thereby defining the storage node. A second gate insulating layer is formed on the resultant semiconductor substrate. Second conductive spacers are formed on the sidewalls of the first conductive spacers and the storage node, thereby forming control gates. The dummy layer is removed. A lightly doped impurity and a pocket impurity are implanted into exposed portions of the semiconductor substrate, and insulating spacers are formed on both sides of the second conductive spacers. A heavily doped impurity is implanted into the semiconductor substrate outside the insulating spacers, thereby forming source and drain regions. First silicide layers are formed to electrically connect the first and second conductive spacers, and at the same time second silicide layers are formed on the source and drain regions.  
         [0029]     In another embodiment, a semiconductor tunnel oxide layer, a storage node layer, a first gate insulating layer, and a damascene molding layer are sequentially stacked. A dummy layer is formed using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer. First conductive spacers are formed on sidewalls of the dummy layer. The gate insulating layer, the storage node layer, and the tunnel oxide layer are etched using the first conductive spacers as masks, thereby defining the storage node. The dummy layer is removed. A second gate insulating layer is formed on the resultant semiconductor substrate. Second conductive spacers are formed on both sidewalls of the first conductive spacers and the storage node, thereby forming control gates. The dummy layer is removed. A lightly doped impurity and a pocket impurity are implanted into exposed portions of the semiconductor substrate, and insulating spacers are formed on both sides of the second conductive spacers. A heavily doped impurity is implanted into the semiconductor substrate outside the insulating spacers, thereby forming source and drain regions. First silicide layers are formed to electrically connect the first and second conductive spacers, and at the same time second silicide layers are formed on the source and drain regions. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0030]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0031]      FIG. 1  is a cross-sectional view of a conventional split gate flash memory device;  
         [0032]      FIGS. 2A through 2E  are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention;  
         [0033]      FIGS. 3A through 3C  are cross-sectional views illustrating a method of manufacturing a flash memory device according to another embodiment of the present invention; and  
         [0034]      FIGS. 4A through 4E  are cross-sectional views illustrating a method of manufacturing a flash memory device according to still another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0035]     The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. In the drawings, the thicknesses of layers and regions and the sizes of components may be exaggerated for clarity, and the same elements are given the same reference numerals throughout the drawings.  
         [0036]      FIGS. 2A through 2E  are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention.  
         [0037]     Referring to  FIG. 2A , a tunnel oxide layer  105 , a storage node  110 , and a first gate insulating layer  115  are sequentially deposited on a semiconductor substrate  100 . The semiconductor substrate  100  comprises, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The tunnel oxide layer  105  and the first gate insulating layer  115  comprise, for example, silicon oxide layers. The storage node  110  may be a silicon nitride layer, a polysilicon layer, a silicon dot layer, a silicon germanium (SiGe) layer, or a nano crystal layer, and operates as a floating gate. A damascene molding layer  120  is deposited on the gate insulating layer  115 . Thereafter, the damascene molding layer  120 , the first gate insulating layer  115 , the storage node  110 , and the tunnel oxide layer  105  are partially etched to form a hole. A dummy layer  125  is deposited on the damascene molding layer  120  to fill the hole, and then the dummy layer  125  is buried in the hole using a planarization process, such as a chemical mechanical polishing process or an etch back process, to expose a surface of the damascene molding layer  120 . The damascene molding layer  120  and the dummy layer  125  can have a different etching selectivity, and the dummy layer  125  is easily selectively removed by wet etching. The damascene molding layer  120  of the present embodiment comprise, for example, a silicon nitride layer, and the dummy layer  125  may be a silicon oxide layer.  
         [0038]     Referring to  FIG. 2B , the damascene molding layer  120  is selectively removed, and a conductive layer  130  is deposited to a predetermined thickness on the first gate insulating layer  115  and the dummy layer  125 .  
         [0039]     Referring to  FIG. 2C , the conductive layer  130  is anisotropically etched to expose a top surface of the damascene molding layer  125 , thereby forming first conductive spacers  132  on both sidewalls of the patterned dummy layer  125 . Next, the gate insulating layer  115 , the storage node  110 , and the tunnel oxide layer  105  are etched using the first conductive spacers  132  as masks to separate the storage node  110  into discrete portions.  
         [0040]     Referring to  FIG. 2D , the first conductive spacers  132  are removed using conventional removal techniques, and then a second gate insulating layer  135  is deposited on the resultant semiconductor substrate  100 . The second gate insulating layer  135  may comprise, for example, the same material as that of the first gate insulating layer  115 .  
         [0041]     Referring to  FIG. 2E , a conductive layer for a gate electrode is deposited on the second gate insulating layer  135  and the dummy layer  125 . The conductive layer for gate electrode may be a doped polysilicon layer or a transition metal silicide layer. Next, the conductive layer for the gate electrode is anisotropically etched to expose a surface of the dummy layer  125 , thereby forming second conductive spacers  140  on sidewalls of the dummy layer  125  coated with the second gate insulating layer  135 . The second conductive spacers  140  of the present embodiment function as control gates. As the second conductive spacers  140  are formed on both the sidewalls of the patterned dummy layer  125  using a spacer-etching method, the second conductive spacers  140  are self-aligned without an additional photolithography process. Thereafter, the dummy layer  125  is removed. Here, the dummy layer  125  may be selectively removed using wet etching.  
         [0042]     Referring to  FIG. 2F , a lightly doped impurity and a pocket impurity opposite in conductivity to the semiconductor substrate  100  are implanted into portions of the semiconductor substrate  100  using the second conductive spacers  140  as a mask. Next, insulating spacers  145  are formed on both sidewalls of the second conductive spacers  140  using a well-known method, and then a heavily doped impurity is implanted into exposed portions of the semiconductor substrate  100 . Consequentially, drain regions  150   b  and a source region  150   a  are formed, each of which includes a lightly doped impurity region  144 , a pocket impurity region (not shown), and a heavily doped impurity region  147 .  
         [0043]     Referring to  FIG. 2G , a transition metal layer (not shown) is deposited on the resultant semiconductor substrate  100 , and then the transition metal layer is annealed to form silicide layers  155 , which operate as ohmic contacts, on the second spacers  140  and the source and drain regions  150   a  and  150   b , respectively. The silicide layers  155  are optional.  
         [0044]     According to the present embodiment illustrated in  FIGS. 2A through 2G , the second conductive spacers  140 , that is, control gates, are formed on both the sidewalls of the dummy layer  125  using a spacer-etching method such that the second conductive spacers  140  are self-aligned. As a result, an overlap area between each of the control gates  140  and the channel region is constant from chip to chip, lot to lot, and wafer to wafer.  
         [0045]     Furthermore, since each of the spacer-shaped control gates  140  is formed to surround a top surface and a sidewall of each storage node (floating gate)  110  similar to that of a conventional split gate structure, an enhanced electric field and a source side injection (SSI), which leads to charge injection into the storage node at the source side, can be maintained.  
         [0046]      FIGS. 3A through 3C  are cross-sectional views illustrating a method of manufacturing a flash memory device according to another embodiment of the present invention. The embodiment illustrated in  FIGS. 3A through 3C  undergoes the same operations as shown in  FIGS. 2A, 2B , and  2 C, and thus to eliminate redundancy, operations thereafter will now be explained below.  
         [0047]     In the present embodiment illustrated in  FIGS. 3A through 3C , the first conductive spacers  132  are used as control gates. In detail, referring to  FIG. 3A , a second gate insulating layer  135  and a conductive layer for a gate electrode are deposited on the resultant semiconductor substrate  100  on which the first conductive spacers  132  are formed. Each of the first conductive spacers  132  and the conductive layer for the gate electrode comprises, for example a doped polysilicon layer, a transition metal silicide layer or a transition metal layer. Next, the conductive layer for gate electrode and the second gate insulating layer  135  are anisotropically etched to expose the dummy layer  125 , thereby forming second conductive spacers  141  on sidewalls of the first conductive spacers  132 .  
         [0048]     Referring to  FIG. 3B , the dummy layer  125  is removed using a well-known method. Next, a lightly doped impurity and a pocket impurity are implanted into portions of the semiconductor substrate  100  outside the first and second conductive spacers  132  and  141 , respectively. Next, insulating spacers  145  are formed using well-known techniques on sidewalls of the first conductive spacers  132  and the second conductive spacers  141 . Thereafter, a heavily doped impurity is implanted into exposed portions of the semiconductor substrate  100  to form source and drain regions  150   a  and  150   b , respectively, each of which includes a light doped impurity region  144 , a pocket impurity region (not shown), and a heavily doped impurity region  147 .  
         [0049]     Next, to operate the respective first and second conductive spacers  132  and  141  as one control gate, a transition metal layer (not shown) is deposited on the resultant semiconductor substrate  100 . Next, the transition metal layer is annealed. Referring to  FIG. 3C , first transition metal silicide layers  155   a , which connect the first and second conductive spacers  132  and  141 , and second transition metal silicide layers  155   b , which are formed on the source and drain regions  150   a  and  150   b , respectively, are formed, and remaining transition metal layers are removed. Here, although a gate insulating layer  135  is interposed between the first conductive spacer  132  and the second conductive spacer  141 , the gate insulating layer  135  is relatively thin and the first and second conductive spacers  132  and  141 , respectively, electrically communicate with each other due to the first transition metal silicide layer  155   a , such that the same voltage is applied to the first and second conductive spacers  132 ,  141 .  
         [0050]      FIGS. 4A through 4E  are cross-sectional views illustrating a method of manufacturing a flash memory device according to still another embodiment of the present invention. Since the present embodiment illustrated in  FIGS. 4A through 4E  undergoes the same operations as those in  FIGS. 2A through 2C , operations thereafter will now be explained.  
         [0051]     Referring to  FIG. 4A , the storage node  110  is divided into discrete regions by patterning using the first conductive spacers  132  as masks. Thereafter, an impurity opposite in conductivity to that of source and drain regions, which are to be formed later, is implanted into exposed portions of the semiconductor substrate  100 , which are to be drain and channel regions, to form counter doping layers  133 . The counter doping layers  133  in the drain regions prevent lateral diffusion of the impurity for the drain region, and the counter doping layer  133  in the source region induces lateral diffusion of the impurity for the source region. The counter doping layers  133  implant charge into the storage node  110  at the source region side. The counter doping layers  133  may be selectively formed after the operation of  FIG. 2C  in the above embodiments.  
         [0052]     Referring to  FIG. 4B , the patterned dummy layer  125  is removed, and then a second gate insulating layer  135  is deposited on a surface of the resultant structure.  
         [0053]     Referring to  FIG. 4C , a conductive layer for a gate electrode is deposited on the second gate insulating layer  135 . Next, the conductive layer for the gate electrode and the second gate insulating layer  135  are anisotropically etched to expose top surfaces of the first conductive spacers  132 , thereby forming second conductive spacers  142  on both sidewalls of the first conductive spacers  132 . Thereafter, a lightly doped impurity is implanted into an exposed portion of the semiconductor substrate  100  outside the second conductive spacers  142  to form a light doped impurity region  144 . Here, the lightly doped impurity region  144  of the source region can overlap with the storage node  110 .  
         [0054]     Referring to  FIG. 4D , an insulating layer is deposited on the resultant semiconductor substrate  100  in which the lightly doped impurity region  144  is formed, and the insulating layer is anisotropically etched to form insulating spacers  145  on sidewalls of the second conductive spacers  142 . Subsequently, a heavily doped impurity is injected into exposed portions of the semiconductor substrate  100  to form a heavily doped impurity region  147  and define source and drain regions  150   a  and  150   b.    
         [0055]     Next, a transition metal layer (not shown) is deposited on the resultant semiconductor substrate  100  to electrically connect the first conductive spacer  132  and the second conductive spacers  142  disposed on both the sidewalls of the first conductive spacer  132  so that the first and second conductive spacers  132  and  142  can form one control gate. After that, the transition metal layer is annealed. Referring to  FIG. 4E , first metal silicide layers  155  connecting the respective first and second conductive spacers  132  and  142  and second transition metal silicide layers  155   b  formed on the source and drain regions  150   a  and  150   b , respectively, are formed and remaining transition metal layers are removed.  
         [0056]     Since the control gates of the present embodiment surround a top surface and both sides of the storage node, an electric field applied to the control gates can be enhanced.  
         [0057]     As described above, according to the present invention, a patterned dummy layer is formed using a damascene method and control gates are formed using a spacer-etching method on both sides of the dummy layer. Accordingly, the control gates can be self-aligned, and thus a uniform channel overlap area from chip to chip, lot to lot, and wafer to wafer can be achieved.  
         [0058]     Since the control gates cover a top surface and a sidewall of a storage node similar to a conventional split gate structure, an enhanced electric field and SSI effect can be maintained.  
         [0059]     In addition, since the storage node is defined by the dummy layer, and the spacer-shaped control gates are formed on the top surface and at least one sidewall of the storage node, the cell size can be smaller than that of the conventional split gate structure, and high scalability can be achieved.  
         [0060]     Moreover, since the size of the storage node is adjusted according to the thickness of conductive spacers, high scalability can be achieved. Since the flash memory device of the present invention allows two gates to share one a common source, integration density can be increased and the device is further applicable as a NOR flash memory device.  
         [0061]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made herein without departing from the spirit and scope of the present invention as defined by the following claims.