Abstract:
A power source voltage monitoring circuit for monitoring self power source voltage comprises a reference voltage circuit which is supplied with a power source voltage, and generates and outputs a reference voltage in accordance with the power source voltage, a comparator which is supplied with an output voltage output from the reference voltage circuit and a voltage varying with the power source voltage, compares the voltages, and outputs a result of the comparison, and a control circuit which prevents the voltage in accordance with the power source voltage from being input to the comparator before the voltage output from the reference voltage circuit reaches a predetermined reference voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a power source voltage monitoring circuit having a comparator which monitors its power source voltage. 
     2. Description of Related Art 
     The configuration of the conventional power source voltage monitoring circuit is explained by referring to  FIG. 5 . The power source voltage monitoring circuit  200  monitors the potential of the power source, that is, the power source voltage Vcc, detects whether or not the power source voltage Vcc decreases under a predetermined value, and outputs the result of the detection. The power source voltage monitoring circuit  200  has a reference voltage circuit  1 . The reference voltage circuit  1  generates a reference voltage, and supplies it to one of the input terminals of a comparator  2 . The reference voltage Vcc is divided by sense resistors R 1  and R 2 . The divided voltage is supplied to the other input terminal of the comparator  2 . 
     When the power source voltage Vcc is increased from 0V, the changes of the voltage at nodes a, b and c in  FIG. 5  are explained by referring to  FIG. 6 . At t 0 , the power source voltage Vcc starts increasing from 0V. The power source voltage Vcc increases proportionally to time. The increase of the power source voltage Vcc allows the reference voltage circuit  1  to start initiating. Then, the voltage Va, which represents the output at node a, increases proportionally to time. At t 1 , the power source voltage Vcc reaches the startup voltage of the reference voltage circuit  1 , allowing the voltage Va to surge and then maintain itself at a constant reference voltage value. 
     Vb is the voltage at node b between the sense resistors R 1  and R 2  which divide the power source voltage Vcc. The increase of the power source voltage Vcc allows the voltage Vb to increase proportionally to time. The inclination of the voltage Vb is larger than the initial inclination of the voltage Va output from the reference voltage circuit  1 . 
     Vc at node c is the output voltage of the comparator  2 . In the initial phase, although the voltage Vb is lower than the reference voltage, the voltage Vc represents the same value as the power source voltage Vcc, because the voltage Vb is higher than the voltage Va. 
     Since the inclination of the output voltage Va becomes larger than the inclination of the voltage Vb after t 1 , the output voltage Va exceeds the voltage Vb at t 2 . When the voltage Va exceeds the voltage Vb, both of which are supplied to the comparator  2 , the output voltage of the comparator  2 , Vc, is 0V. 
     After t 2 , the output voltage Va from the reference voltage circuit  1  reaches a predetermined reference voltage and then becomes constant. The voltage Vb at node b continuously increases proportional to the increase of the power source voltage Vcc, so that the voltage Vb exceeds the voltage Va again at t 3 . When the voltage Vb exceeds the voltage Va, the output voltage of the comparator  2 , Vc, recovers from 0V to the same voltage as Vcc. 
     Subsequently, the voltage Vb proportionally increases similarly to the case of Vcc before t 4  that is the time when the power source voltage Vcc reaches the desired voltage. In addition, the voltage Va still maintains itself at the reference voltage. After t 4 , the power source voltage Vcc reaches the desired voltage and becomes constant, similarly, the voltage Vb that is the voltage at node b dividing the power source voltage Vcc becomes constant. After t 4 , the output voltage of the comparator  2 , Vc, becomes the same voltage as the power source voltage Vcc. 
     Assuming that the power source voltage Vcc decreases at t 5 , the divided voltage Vb also decreases and may decrease under the reference voltage Va. In this case, the voltage Vc, which represents the result of the comparison, becomes 0V after t 6  if the voltage Vb is lower than the reference voltage Va. In this example, the voltage Vc is 0V during t 6  to t 7 , then, the voltage Vc may start following Vcc again at t 7  that is the time when the voltage Vb is higher than the voltage Va. During t 6  to t 7 , it is a normal operation that the comparator  2  outputs 0V, accordingly, such the operation enables the power source voltage to be monitored. 
     In power on reset circuits (Japanese Unexamined Patent Application Publication No. H9-135157), the circuit for detecting the power source voltage is employed. This configuration of the power source voltage monitoring circuit, however, is not for detecting the decrease of the power source voltage, but for detecting that the power source voltage reaches a predetermined value and resetting the circuit. 
     In the conventional power source voltage monitoring circuit, during t 0  to t 2 , the output voltage of the comparator  2 , Vc, is the same voltage as the power source voltage Vcc, which is high level, while the voltage Vb is lower than the reference voltage, which causes a misoperation. The misoperation of the comparator  2  causes the misoperation of other circuits which operate depending on the output of the comparator  2 . 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, there is provided a power source voltage monitoring circuit for monitoring self power source voltage comprising a reference voltage circuit which is supplied with a power source voltage, and generates and outputs a reference voltage in accordance with the power source voltage, a comparator which is supplied with an output voltage output from the reference voltage circuit and a voltage varying with the power source voltage, compares the voltages, and outputs a result of the comparison, and a control circuit which prevents the voltage in accordance with the power source voltage from being input to the comparator before the voltage output from the reference voltage circuit reaches a predetermined reference voltage. 
     According to another aspect of the present invention, there is provided a power source voltage monitoring circuit for monitoring self power source voltage comprising a reference voltage circuit which is supplied with a power source voltage, and generates and outputs a reference voltage in accordance with the power source voltage, a first switch which controls conduction between the power source and the comparator, and a second switch which is supplied with the output voltage output from the reference voltage circuit and controls the first switch in accordance with the output voltage, wherein the second switch controls the first switch so that the voltage in accordance with the power source voltage is not supplied to the comparator before the output voltage output from the reference voltage circuit reaches a predetermined reference voltage. 
     In the power source voltage monitoring circuit according to the present invention, before the voltage output from the reference voltage circuit reaches the predetermined value, for example, 0V is supplied to the comparator. After the voltage output from the reference voltage circuit reaches the predetermined value, the voltage in accordance with the power source voltage is supplied to the comparator, allowing the operation for comparison. Thus, the misoperation which would otherwise occur during the increase of the power source voltage is prevented. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  shows a circuit block diagram of the power source voltage monitoring circuit according to the present invention; 
         FIG. 2  is a circuit diagram showing one example of the reference voltage circuit of the power source voltage monitoring circuit according to the present invention; 
         FIG. 3  shows waveforms showing the voltages at respective nodes of the power source voltage monitoring circuit according to the present invention; 
         FIG. 4  shows another circuit block diagram of the power source voltage monitoring circuit according to the present invention; 
         FIG. 5  shows a conventional circuit block diagram of the power source voltage monitoring circuit; 
         FIG. 6  shows waveforms showing the voltages at respective nodes of the conventional power source voltage monitoring circuit. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed. 
     The configuration of the power source voltage monitoring circuit according to the embodiment of the present invention is explained by referring to  FIG. 1 . The power source voltage monitoring circuit  100  monitors the potential of the power source, that is, the power source voltage Vcc, detects whether or not the power source voltage Vcc decreases under a predetermined value, and outputs the result of the detection. 
     The power source voltage monitoring circuit  100  has a reference voltage circuit  1 . The reference voltage circuit  1  is connected to the power source voltage Vcc, and generates the reference voltage based on the power source voltage Vcc. The output terminal of the reference voltage circuit  1  is connected to one of the input terminals of the comparator  2  and supplies the reference voltage thereto. Also, the output terminal of the reference voltage circuit  1  is connected to the gate of the N-channel Metal Oxide Semiconductor (MOS) transistor N 1  and supplies the reference voltage thereto. 
     The current source  3  and N-channel MOS transistor N 1  are connected in series between the power source voltage Vcc and the ground. The current of the current source  3  is generated in the reference voltage circuit  1 . Specifically, the current source  3  is arranged with, for example, a current mirror circuit in the reference voltage circuit  1 . The current source  3  is connected to the gate of the P-channel MOS transistor P 1  and the drain of the N-channel MOS transistor N 1 . Such the current source  3  can ensure the switching operation of the P-channel MOS transistor P 1 . 
     In addition, the P-channel MOS transistor P 1  and sense resistors R 1  and R 2  are connected in series between the power source voltage Vcc and the ground. The source of the P-channel MOS transistor P 1  is connected to the power source voltage Vcc, and the drain is connected to the sense resistor R 1 . The gate of the P-channel MOS transistor P 1  is connected to the power source voltage Vcc via the capacitor C 1 . This prevents the gate of the P-channel MOS transistor P 1  from floating. The gate of the P-channel MOS transistor P 1  is connected to the output terminal of the current source  3  and the drain of the N-channel transistor N 1 . The source of the N-channel transistor N 1  is grounded. 
     The connection node b of the sense resistors R 1  and R 2  is connected to the other input terminal of the comparator  2 . Then, the voltage divided by the sense resistors R 1  and R 2  is supplied to the other input terminal of the comparator  2 . 
     The comparator  2  is connected to the power source voltage Vcc, and its output terminal is connected to the pull-down resistor R 3  and pulled down thereby. 
     Here, an example of the configuration of the reference voltage circuit  1  is explained by referring to  FIG. 2 . As shown in  FIG. 2 , a series circuit, in which the P-channel MOS transistor P 13  and the N-channel MOS transistor N 11  are connected in series, is inserted between the power source voltage Vcc and the ground GND. Further, another series circuit, in which the P-channel MOS transistor P 14 , the N-channel MOS transistor N 12  and the resistor R 12  are connected in series, is inserted. 
     The gate of the P-channel MOS transistor P 13  and the gate and drain of the P-channel MOS transistor P 14  are connected together. The gate and the drain of the N-channel MOS transistor N 11  and the gate of the N-channel MOS transistor N 12  are connected. The connection node of the gates of the P-channel MOS transistors P 13  and P 14  and the drain of the P-channel MOS transistor P 14  is connected to the current source  3  and the gate of the P-channel MOS transistor P 15 . The P-channel MOS transistor P 15 , the resistor R 13 , and the diode D 11  which has the anode connected to the resistor R 13  are connected in series and inserted between the power source voltage Vcc and the ground GND. The voltage of the connection node of the P-channel MOS transistor P 15  and register R 13  is supplied to the N-channel MOS transistor N 1  shown in  FIG. 1 . 
     In addition, the P-channel MOS transistors P 12  and P 13  are connected in parallel, the gate of the transistor P 12  is connected the drain of the P-channel MOS transistor P 11 . The P-channel MOS transistor P 11  and the resistor R 11  are connected in series and inserted between the power source voltage Vcc and the ground GND. The drain of the P-channel MOS transistor P 11  is grounded via the capacitor C 11 . 
     The reference voltage circuit  1  generates the reference voltage employing such the configuration above. 
     Next, when the power source voltage Vcc is increased from 0V, the changes of the voltage at nodes a, b and c of  FIG. 1  are explained by referring to  FIG. 3 . At t 0 , the power source voltage Vcc starts increasing from 0V. The power source voltage Vcc increases proportionally to time. 
     Following the increase of the power source voltage Vcc, the reference voltage circuit  1  starts up, and then, the voltage Va, which represents the output at node a, increases proportionally to time. At t 1 , the power source voltage Vcc reaches the startup voltage of the reference voltage circuit  1 , allowing the voltage Va to surge and then maintain itself at a constant reference voltage value. 
     Here, the N-channel transistor N 1  is in OFF state before the voltage Va output from the reference voltage circuit  1  reaches a predetermined reference voltage. Thus, the gate of the P-channel transistor P 1 , which is connected to the drain of the N-channel transistor N 1 , is supplied with current from the current source  3 , allowing the gate voltage to be in high level, so that the P-channel transistor P 1  is in OFF state. Thus, the power source voltage Vcc and node b are open, so that the other input voltage of the comparator  2  is 0V. 
     When the voltage Va increases and reaches the predetermined reference voltage, the N-channel transistor N 1  turns on. Upon the N-channel transistor N 1  turning on, the gate voltage of the P-channel transistor P 1  decreases and the transistor P 1  turns on. Then, the power source voltage Vcc is divided by the sense resistors R 1  and R 2  through the P-channel transistor P 1 . At t 3 , the divided voltage Vb exceeds the reference voltage Va, allowing the voltage Vc output from the comparator  2  to become equal to the power source voltage Vcc. 
     Then, at t 4 , when the power source voltage Vcc reaches the desired voltage and become constant, the output voltage of the comparator  2 , Vc, also becomes constant. After that, the operation is the same as in the conventional circuit, thus, its explanation is omitted. 
     In this manner, in the power source voltage monitoring circuit  100 , in accordance with the embodiment of the present invention, before the voltage output from the reference voltage circuit  1  reaches the predetermined value, 0V is supplied to the comparator  2 . After the voltage output from the reference voltage circuit  1  reaches the predetermined value, the voltage in accordance with the power source voltage Vcc is supplied to the comparator  2 , allowing the operation for comparison. Thus, the misoperation which would otherwise occur during the increase of the power source voltage is prevented. 
     While the current source  3  is employed in the embodiment of  FIG. 1 , the current source  3  can be substituted by the resistor R 4  as shown in  FIG. 4 . It is preferable that the resistor R 4  is of high resistance in view of reducing the increase of power consumption. 
     In addition, while the capacitor C 1  is connected in the embodiments in  FIGS. 1 and 4 , the capacitor C 1  is not necessarily required. The capacitor C 1  can be removed if there is no possibility of the floating gate of the P-channel transistor P 1  during t 0  to t 1  as is the case of the circuit shown in  FIG. 4 . 
     It is apparent that the present invention is not limited to the above embodiment and it may be modified and changed without departing from the scope and spirit of the invention.