Abstract:
An apparatus is provided to test a device, i.e. an interface card to a computer system or an IC chip. The apparatus communicates with the computer system via a first bus and communicates with the device via a second bus. The first and second buses are standard bus such as ISA bus, EISA bus, PCI bus, and AGP bus, etc. In the apparatus, three switch circuits respectively making connection of data/address lines, power lines and a reset line of the first bus to the second bus are provided. A test program executed in the computer generates a plurality of control signal to the apparatus. A control circuit, responsive to the plurality of control signals, controls individually and selectively the turn-on of three switch circuits. By test program running in the computer system, the function test of the device can be accomplished automatically without time-consuming power-off and re-initialization of the computer system.

Description:
FIELD OF INVENTION 
     The present invention relates to an apparatus and method for testing a device, i.e. an add-on device of a computer system or an integrated circuit chip. 
     BACKGROUND OF INVENTION 
     After being manufactured, the functions of device, for instance, an add-on device of a computer system or an IC chip, is usually tested by a predetermined manner. The add-on device include the well known interface card. 
     A conventional approach to test an interface card is to install the interface card into a dedicated interface slot and to test whether the interface card operates as designed. However, to remove an interface card from the slot or insert an interface card into the slot of computer system, the operator must turn off the power to the computer system and the interface card first. After each interface card to be tested is inserted into the interface slot, the operator re-powers on the computer system. Afterwards, the computer system spends some times to do initialization. When a large amount of devices are required to test, it is evident that time-consuming power-on and initialization procedures of the computer system are involved in this conventional approach. 
     A test apparatus, illustrated in FIG. 1, was developed by Leap Corporation which allows the replacement of an interface card under continuous power-on condition of the computer system. The test apparatus  12  is attached to a first slot  11  on the computer system  10 . The test apparatus  12  includes a slot  17  for insertion of the interface card  18  to be tested and the slot  17  transmits the data/address lines  131 , the power lines  141 , and the reset line  151  of the second bus  171 . The test apparatus  12  further includes switch circuits  13 ,  14 , and  15  each of which are respectively electrically connected to the slot  17  by the data/address lines  131 , the power lines  141 , and the reset line  151 . The switch circuits  13 ,  14 , and  15  are respectively electrically connected to the first slot  11  by the data/address lines  112 , the power lines  113 , and the reset line  114  of the first bus  111 . As the switch circuit  13  is turned on by the control signal  191  from the switch button  161 , the data/address lines  112  on the first bus  111  make connection to the data/address lines  131  on the second bus  171 . As the switch circuit  14  is turned on by the control signal  192  from the switch button  162 , the power supplies on power lines  113  are applied to the power lines  141  of the second bus  171 . As the switch circuit  15  is turned on by the control signal  193  from the switch button  163 , the reset signal on the reset line  114  is transmitted to the reset line  151  of the second bus. On the contrary, as the switch circuit  13  is turned off, the data/address lines  112  on the first bus  111  are isolated from the data/address lines  131  on the second bus  171 . As the switch circuit  14  is turned off, the power lines  141  of the second bus  171  are cut off from the power supplies. As the switch circuit  15  is turned off, the reset signal does not appear on the reset line  151  of the second bus. In general, the first bus  111  and the second bus  171  are standard bus, such as ISA, EISA, PCI, and AGP, respectively. 
     The test can be accomplished with the assistance of three manually operated switch buttons  161 ,  162 ,  163 . During initial power-on, all switch buttons  161 ,  162 ,  163  are activated. When replacement of the interface card  18  under the test environment shown in FIG. 1 is required, three manually operated switch buttons  161 ,  162 ,  163  are utilized to individually control the connection of the data/address signals, the power supplies and the reset signal. Therefore, in most conditions, the test apparatus provided by LEAP Corporation performs the function test efficiently. However, when the bus  111 ,  171  involved are the PCI or AGP bus, the test apparatus  12  shown in FIG. 1 is still inconvenient due to following reason. Different from an add-on device employing the EISA or ISA bus, an add-on device employing a PCI bus or AGP bus must be configured by the BIOS of the computer system  10  rather than the physical setup. Therefore, each time to test a PCI-type or AGP-type add-on device under the test environment shown in FIG. 1, the computer system  10  needs to reset and to re-configure the PCI-type or AGP-type add-on device. Besides, it is evident that the test procedures involved in the test apparatus  12  of FIG. 1 cannot be automated due to the manually operated switch buttons  161 ,  162 ,  163  in the test apparatus  12 . 
     Accordingly, it is main objective of the invention to provide an apparatus and method for testing an add-on device or integrated circuit chip in an efficient way. The concept of this present invention is equally applicable to the test of an add-on device employing EISA, ISA, PCI, or AGP bus, etc. 
     SUMMARY OF INVENTION 
     The invention provides an apparatus for testing function of a device. The device includes the add-on device of a computer system, i.e. an interface card, and the IC chip. The apparatus communicates with the computer system via a first bus and communicates with the device via a second bus. The first and second buses are standard bus, e.g. EISA, ISA, PCI and AGP bus, etc. 
     According to the invention, the transmission of data/address signals, power signals and reset signal between the computer system and the device are enabled selectively and individually. Thereby, the test of the device can be accomplished without the time-consuming power on/off operation and re-initialization of the computer system. By a test program running in the computer system, the test of the device can also be accomplished automatically. 
     The first bus includes a multiple of data/address lines, power lines, and a reset line. The computer system includes an output port and a control program is executed in the computer system generating a plurality of control signals to the output port. The test apparatus includes a connection device, a first switch, a second switch, a third switch, a register and a control device. 
     The connection device makes connection of the second bus to the test apparatus. The first switch makes connection of the data/address lines of the first bus to the second bus while the first switch is switched on. The second switch makes connection of the power lines of the first bus to the second bus while the second switch is switched on. The third switch makes connection of the reset line of the first bus to the second bus while the third switch is switched on. The register is electrically connected to the output port for storing and outputting the plurality of control signals. The control circuit, responsive to the plurality of control signals, individually and selectively switches on the first, second and third switch. 
     According to the invention, an apparatus is provided for testing a device. The apparatus communicates with a computer system via a first bus which comprises a multiple of data/address lines, power lines, and a reset line. The apparatus communicates with the device via a second bus. The computer system comprises an output port, and a control program is executed in the computer system for generating a plurality of control signals to the output port. The apparatus comprises a connection device, a first switch circuit, a second switch circuit, a third switch circuit, a register, and a control circuit. The connection device functions to make connection of the second bus to the apparatus. The first switch circuit makes connection of the data/address lines of the first bus to the second bus while the first switch circuit is switched on. The second switch circuit makes connection of the power lines of the first bus to the second bus while the second switch circuit is switched on. The third switch circuit makes connection of the reset line of the first bus to the second bus while the third switch circuit is switched on. The register is electrically connected to the output port for storing and outputting the plurality of control signals. The control circuit, responsive to the plurality of control signals, functions to individually and selectively switch on the first, second and third switch circuits. Consequently, various testing conditions of the device, such as replacement, initialization, and function test, can be automatically accomplished by means of the control program executed in the computer system and the data/address lines, power lines, and reset line of the first bus, according to the control signals, capable of connecting to the second bus individually and selectively without the time-consuming power on/off operation and re-initialization of the computer system. 
    
    
     BRIEF DESCRIPTION OF THE APPENDED DRAWINGS 
     FIG. 1 illustrates the configuration of one prior art test apparatus. 
     FIG. 2 shows the embodiment of the invention testing an interface card. 
     FIG. 3 is a circuit diagram schematically showing the details of output port  22 , register  24 , and control circuit  25  in the test apparatus of FIG.  2 . 
     FIG. 4 shows how the invention tests an IC chip. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 2, the embodiment of the invention is illustrated. As shown in FIG. 2, the test apparatus  23  provided by the invention includes a register  24 , the switch circuits  26 ,  27 ,  28 , a control circuit  25  and a slot  29  for inserting the interface card  30  to be tested. The test apparatus  23  is attached to a first slot  21  of the computer system  20  via the first bus  211  on one hand. On the other hand, the test apparatus  23  is attached to the interface card  30  via the second bus  291 . The slot  29 , which transmits the data/address lines  261 , the power lines  271 , and the reset line  281  of the second bus  291 , receives the interface card  30  to be tested. The switch circuits  26 ,  27 , and  28  each respectively are electrically connected to the slot  29  by the data/address lines  261 , the power lines  271 , and the reset line  281 . The switch circuits  26 ,  27 , and  28  respectively are electrically connected to the first slot  21  by the data/address lines  212 , the power lines  213 , and the reset line  214  of the first bus  211 . As the switch circuit  26  is turned on by a first control signal  251  from the control circuit  25 , the data/address lines  212  on the first bus  211  make connection to the data/address lines  261  on the second bus  291 . As the switch circuit  27  is turned on by a second control signal  252  from the control circuit  25 , the power supplies on power lines  213  are applied to the power lines  271  of the second bus  291 . As the switch circuit  28  is turned on by a third control signal  253  from the control circuit  25 , the reset signal on the reset line  214  is transmitted to the reset line  281  of the second bus  291 . On the contrary, as the switch circuit  26  is turned off, the data/address lines  212  on the first bus  211  are isolated from the data/address lines  261  on the second bus  291 . As the switch circuit  27  is turned off, the power lines  271  of the second bus  291  are cut off from the power supplies. As the switch circuit  28  is turned off, the reset signal does not appear on the reset line  281  of the second bus  291 . In general, the first bus  211  and the second bus  291  are standard bus, such as ISA, EISA, PCI, and AGP respectively. The signal lines  221  are used to transmit the data from the output port  22  of computer system  20  to the register  24 . The data stored within the register  24  are transmitted, via signal lines  241 , to the control circuit  25  to selectively activate the first, second and third control signals ( 251 ,  252  and  253 ) respectively. During the test, a test program (not shown) executing within the computer system  20  outputs three control data to the registers  24  through the output port  22 . 
     When the interface card  30  tested employing a PCI-type or AGP-type bus, the computer system  20  configures the interface card  30  via the BIOS within the computer system  20 . Each time a new device  30  is inserted, re-initialization of the new device  30  is performed, without resetting the computer system  20 , by the test program executing in the computer system  20 . 
     With the embodiment of FIG. 2, the method, provided by the invention, of removing power supplies from the device (interface card  30 ) includes the following steps. 
     1. Reading a configuration data of the device through the data/address lines  261  of the second bus  291  and the data/address lines  212  of the first bus  211 . 
     2. Saving the configuration data of the device into the computer system  20 . 
     3. De-activating the first control signal  251  for isolating the data/address lines  212  of the first bus  211  from the second bus  291 . 
     4. De-activating the second control signal  252  to switch off the second switch  27  such that the power supplies of the first bus  211  are not applied to the second bus  291 . 
     With the embodiment of FIG. 2, the method, provided by the invention, of replacing a first device (first interface card  30 ) by a second device (second interface card  30 ) includes the following steps. 
     1. Removing power supplies from the first device already connected to the test apparatus  23 . 
     2. Removing the first device from the test apparatus  23 . 
     3. Inserting the second device into the test apparatus  23 . 
     4. Adding power supplies to the second device. 
     5. Initializing the second device. 
     From the above recitation, it is evident that the invention results in convenience during the test of interface card or integrated circuit chip. Especially, since no reset operation of computer system and re-initialization operation are involved, this invention provides significant enhancement of efficiency. 
     The invention may be understood by referring to a further details shown in FIG.  3 . In FIG. 3, we use the standard printer port as an example of the output port  22  in FIG.  2 . However, it is noted that other ports, i.e. COM  1  or COM 2  of the computer system  20 , may alternatively be used. The well known latch device 74LS273 is selected as the register  24  in FIG.  2 . The control circuit  25  mainly includes three sets of relay device U 1 , U 2 , U 3 . The operation details of control circuit  25  will be reiterated hereinafter. 
     The d 0 , d 1 , d 2 , d 3  signals from the pins p 2 , p 3 , p 4 , p 5  of the printer port  22  are respectively input to the input terminals D 1 , D 2 , D 3 , CLK of the latch  24 . And the corresponding latch outputs  241  are generated at the output terminals Q 1 , Q 2 , Q 3  respectively. The d 3  signal is a positive edge trigger clock which latches the d 0 , d 1 , d 2  signals into the output terminals Q 1 , Q 2 , Q 3  of the latch  24  respectively. The Reset signal from the computer system  20  is used to clear the latch device  24 . The signal  241  to the inverter U 5  controls the operation of relay U 1 . The signal  241  to the inverter U 6  controls the operation of relay U 2 . The signal  241  to the inverter U 7  controls the operation of relay U 3 . 
     As d 0 =1 is latched, the output Q 1  of the latch  24  is logic 1. The U 5  outputs logic 0. At this time, a current flows from pin  1  to pin  10  of U 1  which activates action of U 1 . In other words, the S 1  signal is outputted to the pin  2 . Under this condition of control signal  251 , the switch circuit  26  is turned on to make connection of the data/address lines. As d 0 =0 is latched, the output Q 1  of the latch  24  is logic 0. The U 5  outputs logic 1. At this time, no current flows from pin  1  to pin  10  of U 1  which de-activates action of U 1 . In other words, the S 1  signal is outputted to the pin  4 . Under this condition of control signal  251 , the switch circuit  26  is turned off to isolate the data/address lines. A diode disposed between the terminals of pin  1  and pin  10  of U 1  is used to prevent the bouncing phenomenon during on-off action of the relay which may instabilize the relay. The S 1  signal is the signal which turns on the switch circuit  26  and the S 1  signal may be generated individually within a circuit (not shown) of the test apparatus  23 . 
     As d 1 =1 is latched, the output Q 2  of the latch  24  is logic 1. The U 6  outputs logic 0. At this time, a current flows from pin  1  to pin  10  of U 2  which activates action of U 2 . In other words, the S 2 (GND), S 2 (power) signals are respectively outputted to the pins  2 ,  9 . Under this condition of control signals  252 , the power switch circuit  27  is turned on to transmit the power supplies. As d 1 =0 is latched, the output Q 2  of the latch  24  is logic 0. The U 6  outputs logic 1. At this time, no current flows from pin  1  to pin  10  of U 2  which de-activates action of U 2 . In other words, the S 2 (GND), S 2 (power) signals are respectively outputted to the pins  4 ,  7 . Under this condition of control signals  252 , the power switch circuit  27  is turned off to disconnect the power supplies from the power lines  271 . A diode disposed between the terminals of pin  1  and pin  10  of U 2  is used to prevent the bouncing phenomenon during on-off action of the relay which may instabilize the relay. The S 2 (GND) signal is the signal which makes the GND power supply applying to the power lines  271  and the S 2 (GND) signal may be generated individually within a circuit (not shown) of the test apparatus  23 . The S 2 (power) signal is the signal which makes the a power supply, i.e. +5V, applying to the power lines  271  and the S 2 (power) signal may be generated individually within a circuit (not shown) of the test apparatus  23 . 
     As d 2 =1 is latched, the output Q 3  of the latch  24  is logic 1. The U 7  outputs logic 0. At this time, a current flows from pin  1  to pin  10  of U 3  which activates action of U 3 . In other words, the S 3  signal is outputted to the pin  4 . Under this condition of control signal  253 , the switch circuit  28  is turned on to make connection of the reset line. As d 2 =0 is latched, the output Q 3  of the latch  24  is logic 0. The U 7  outputs logic 1. At this time, no current flows from pin  1  to pin  10  of U 3  which de-activates action of U 3 . In other words, the S 3  signal is outputted to the pin  2 . Under this condition of control signal  253 , the switch circuit  28  is turned off to isolate the reset line. A diode disposed between the terminals of pin  1  and pin  10  of U 3  is used to prevent the bouncing phenomenon during on-off action of the relay which may instabilize the relay. The S 3  signal is the signal which turns on the switch circuit  28  and the S 3  signal may be generated individually within a circuit (not shown) of the test apparatus  23 . 
     Referring to FIG. 4, the invention is also applicable to test an IC chip  41  when a corresponding socket  40  for the IC chip is provided. In FIG. 4, the element having same numeral notations at that in FIG. 2 performs the same function as recited with regard to FIG.  2 . The socket  40  is a socket for insertion of a corresponding IC chip  41 .