Abstract:
A method of, and frame synchronizing device for, synchronizing systems having a digital interface. The systems are synchronized by extracting frame time information from a signal transferred from an external source through a digital interface, generating a frame reset signal, delayed by predetermined time based on the extracted frame time information, and resetting the entire systems based on the generated frame reset signal. Also, the color burst signal is free-oscillated during the digital interface mode in order to accommodate to the frame reset signal, which has a variable period.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a method of, and frame synchronizing device for, synchronizing systems having a digital interface in audio/video (A/V) apparatuses. 
     As almost all A/V apparatuses becomes digitized, one apparatus can be controlled by another using a digital interface. When moving picture data is received, the picture cannot be properly restored unless the apparatuses having the digital interface are synchronized. A device that performs this task is referred to as a frame synchronizing device. 
     FIG. 1 is a block diagram of a conventional frame synchronizing device. A digital interface (DIF)  110  synchronizes external equipment (a master system) which transfers the transport packet, with a digital recording and reproducing apparatus (a slave system), using a cycle timer  113 , a time stamp extractor  114  and a comparator  115 . The digital interface  110  extracts a time stamp from a transport packet received during a digital interface mode, operates a PLL circuit  120  according to a frame pulse (frame_dif) extracted from frame starting time information in the time stamp, divides a clock signal generated in the PLL circuit  120  by using a divider  130 , applies a frame reset pulse (frp) synchronized with the divided clock signal to a channel encoder  140  and a source decoder  150 , and applies a horizontal synchronizing signal (H_sync) synchronized with the divided clock signal and a field signal (field) to a video encoder  160 . The digital recording and reproducing apparatus, which has an inner bus margin, represents digital video cassette recorder and all digital video camera (DVC) systems such as digital camcorders. The digital recording and reproducing apparatus includes a recording system, constructed of a source encoder (not shown), and a channel encoder  140 . It also includes a reproducing system, constructed of a channel decoder (not shown), a source decoder  150  and a video encoder  160 . The PLL circuit  120  shown in FIG. 1 also includes a phase discriminator (PD)  121 , a low pass filter (LPF)  122  and a voltage controlled crystal oscillator (VCXO)  123 . 
     When a synchronizing signal is required for a system, for example, the channel encoder  140 , the source decoder  150 , and the video encoder  160 , it is generated in the divider  130 . Then data is read from a FIFO memory  112  and transferred to the channel encoder  140  and the source decoder  150  through an AV_bus. The data is read according to a control signal (CON), generated during fixed timing on the basis of the frame reset pulse (frp), which is generated in the divider  130 . At this time, a color burst signal is generated by being frame-locked inside the video encoder  160  for receiving as input the horizontal synchronizing signal (H_sync) and the field signal (field). The system maintains a four field sequence or an eight field sequence. When receiving color and mono broadcasts in an NTSC broadcasting system, picture quality of the color burst signal deteriorates unless the four field sequence is maintained, because the phase is identical every four fields because a phase difference of 180° exists between lines. In the color burst signal of a PAL broadcasting system, an eight field sequence should be maintained, because the phase is identical every eight fields because a phase difference of 270° exists between lines. 
     FIG. 2 is a detailed block diagram of the divider  130  shown in FIG.  1 . The divider  130  includes: 
     a) a first line counter  131  for receiving a frequency signal of 18 MHz from the PLL circuit  120  and counting lines; 
     b) a first pixel counter  132  for counting pixels; 
     c) a system frame reset pulse generator  133  for receiving the outputs of the first line counter and the first pixel counter and generating the frame reset pulse (frp); 
     d) a second line counter  134  for receiving a frequency signal of 13.5 MHz from the PLL circuit  120  and counting lines; 
     e) a second pixel counter  135  for counting pixels; and 
     f) a video encoder synchronism generator  136  for receiving the outputs of the second line counter and the second pixel counter and generating a horizontal synchronizing signal (H-sync) and a field signal (field). 
     During a digital interface mode, the PLL circuit  120  locks a clock signal oscillating at 54 MHz to a frame pulse (frame_dif) of 15 Hz generated in the digital interface  110 , and provides the clock signal to the divider  130  as system clock. The divider  130  divides the system clock and generates a synchronizing signal required for the channel encoder  140 , the source decoder  150 , and the video encoder  160 . When a synchronizing signal, synchronized with the frame pulse of a master system, is generated from a slave system during the digital interface mode, the data stored in the digital interface  110 , which is transferred from the master system, is read and transferred to the slave system. 
     However, the performance of the above-mentioned frame synchronizing device deteriorates because the clock signal generated in the PLL circuit  120  cannot be used unless an extremely precise voltage controlled oscillator is designed. This is because a 54 MHz clock is locked using the frame pulse (frame_dif) input with a frequency of only 15 Hz. Therefore, in a conventional frame synchronizing device, high-priced components, such as a voltage controlled crystal oscillator, must be used because the PLL is locked by a low frame frequency. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a frame synchronizing device for synchronizing systems, by generating a frame reset signal based on frame time information of external equipment output through a digital interface, and resetting the entire system according to the frame reset signal. 
     It is another object of the present invention to provide in a recording and reproducing apparatus having a digital interface, a frame synchronizing device for synchronizing systems, by free-oscillating a color signal during a digital interface mode in order to accommodate a frame reset signal having a variable period, when a system is reset by the frame reset signal generated based on external frame time information. 
     It is still another object of the present invention to provide a frame synchronizing method for synchronizing systems, by generating a frame reset signal based on frame time information of external equipment output through a digital interface, and resetting the entire system by the frame reset signal. 
     It is still further another object of the present invention to provide a frame synchronizing method for synchronizing systems, by free-oscillating a color signal during a digital interface mode in order to accommodate a frame reset signal having a variable period, when a system is reset by the frame reset signal generated based on external frame time information. 
     To achieve the above objects, a frame synchronizing device for synchronizing systems is provided which has a digital interface for extracting frame time information included in a received signal from an external source, and a generator for generating a frame reset signal based on the frame time information and synchronizing signals required by the systems, wherein the system is reset by the frame reset signal. The frame synchronizing device according to the present invention further comprises a signal processor for free-oscillating a color burst signal during a digital interface mode when the received signal is source-decoded and then encoded into a display signal and for resetting the color burst signal according to the synchronizing signals during a normal mode. 
     A frame synchronizing method for synchronizing systems having a digital interface comprises the steps of extracting frame time information included in a received signal from an external source during a digital interface mode and generating a frame reset signal based on the frame time information and synchronizing signals required by the systems and resetting the systems by the frame reset signal. 
     Also, the frame synchronizing method according to the present invention further comprises the steps of free-oscillating a color burst signal during a digital interface mode and resetting the color burst signal at a period of a predetermined number of fields according to the horizontal synchronizing signal and the field signal during a normal mode. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a conventional frame synchronizing device; 
     FIG. 2 is a detailed block diagram of a divider shown in FIG. 1; 
     FIG. 3 is a block diagram of a frame synchronizing device according to an embodiment of the present invention; 
     FIG. 4 is a detailed block diagram of a divider shown in FIG. 3; 
     FIG. 5 is a timing diagram of input and output signals of the divider shown in FIG. 4; and 
     FIG. 6 is a detailed circuit diagram of a color signal processor of a video encoder shown in FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Hereinafter, a method and apparatus for synchronizing frames according to the present invention, will be described with reference to the figures. 
     In FIG. 3, a receiving unit  211 , of a digital interface  210 , receives data transferred from external equipment in the form of a transport packet, removes an extra header of the transport packet, and writes data without the extra header in a first-in first-out (FIFO) memory  212 . A time stamp extractor  214  extracts a time stamp from the transport packet output from the receiving unit  211 . The time stamp includes frame starting time information. A cycle timer  213  counts based on a reference clock included in the transport packet, outputs a count value, and renews the counted value in every cycle start packet. A comparator  215  compares the count value of the cycle timer  213  with the frame time information of the time stamp extracted from the time stamp extractor  214  and generates a frame pulse (frame_dif). 
     The digital interface  210  can be IEEE  1394 , which is a high speed data transfer standard defined by the IEEE that is used as an interface for connecting digital A/V apparatuses. If the digital interface  210  is IEEE 1394, the receiving unit  211  corresponds to a link layer and the FIFO memory  212 , through the comparator  215 , corresponds to an application layer, in view of a protocol architecture. 
     A divider  220  receives the frame pulse (frame_dif) output from the digital interface  210  as a reset signal, and generates the frame reset pulse (frp), the horizontal synchronizing signal (H_sync), and the field signal (field), according to a system clock (18 MHz and 13.5 MHz) generated by the clock generator  230 . The frame reset pulse (frp) is output to the channel encoder  240  and the source decoder  250 . The horizontal synchronizing signal (H_sync) and the field signal (field), are output to the video encoder  260 . 
     The frame reset pulse (frp) is generated in the divider  220  based on the frame pulse (frame-dif) output from the digital interface  210 , delayed for a predetermined time. This time is less than the margin time of an inner bus or corresponds to the time for filling data into the FIFO memory  212 . At this time, the inner system clock of the channel encoder  240 , and that of the source decoder  250 , free-oscillate and are not synchronized, and a color burst signal generated by the video encoder  260  is also not frame-locked. Also, at this time, the horizontal synchronizing signal (H_sync) and the field signal (field), are generated in the divider  220  based on the system clock from the clock generator  230 . Therefore, the period of the horizontal synchronizing signal (H_sync) is not uniform, however, the number of the horizontal synchronizing signals is constant in frame units. 
     Meanwhile, data in the FIFO memory  212  is read and transferred to the channel encoder  240  and the source decoder  250  through the AV_bus. The data is read based on a control signal (CON), generated in the source decoder  250  at a predetermined time immediately after the frame reset pulse (frp) is generated in the divider  220 . 
     The channel encoder  240  is reset by the frame reset pulse (frp) output from the divider  220  during the digital interface mode and receives data read from the FIFO memory  212  through the AV_bus. During a normal mode, the channel encoder  240  channel-encodes data, which is source-encoded by a source encoder (not shown), and records it on a recording medium such as a tape. The channel encoder  240  includes an error correction encoder (not shown), for correcting the source-encoded data, and a modulator (not shown), for modulating error-correction encoded data and recording it on a recording medium. 
     The source decoder  250  is reset by the frame reset pulse (frp) output from the divider  220  during the digital interface mode and receives data read from the FIFO memory  212  through the AV_bus. During the normal mode, the source decoder  250  source-decodes channel-decoded data output from a channel decoder (not shown), and outputs the data to the video encoder  260 . The source decoder  250  includes a data decompressor (not shown), for decompressing error correction decoded data, and a deshuffler (not shown), for deshuffling the decompressed data. 
     The video encoder  260  receives the horizontal synchronizing signal (H_sync) and the field signal (field), output from the divider  220  during a normal mode, based on a digital interface/normal mode signal (DIF/NORMAL). The video encoder  260  resets the color burst signal at a period of a predetermined number of fields, and encodes source decoded data, output from the source decoder  250 , as an appropriate signal for display. The video encoder  260  free-oscillates a color burst signal with respect to the color signal during the digital interface mode. 
     FIG. 4 is a detailed block diagram of the divider shown in FIG.  3 . The divider  220  includes first and second edge detectors  221  and  225 , first and second line counters  222  and  226 , first and second pixel counters  223  and  227 , a system frame reset pulse generator  224 , and a video encoder synchronism (sync) generator  228 . The first edge detector  221 , which is reset by the frame pulse (frame_dif) output from the digital interface  210 , counts based on the 18 MHz clock signal generated in the clock generator  230 , detects the edge of the frame pulse (frame_dif), and outputs a first reset signal (rst 1 ). The first line counter  222  and the first pixel counter  223 , which are reset by the first reset signal (rst 1 ) output from the first edge detector  221 , count lines and pixels, respectively, based on the 18 MHz clock output from the clock signal generator  230 . The system frame reset pulse generator  224  generates the frame reset pulse (frp), based on the outputs of the first line counter  222  and the first pixel counter  223 , and outputs the frame reset pulse (frp) to the channel encoder  240  and the source decoder  250 . 
     The second edge detector  225 , which is reset by the frame pulse (frame_dif) output from the digital interface  210 , counts based on the 13.5 MHz clock signal generated in the clock generator  230 , detects the edge of the frame pulse (frame_dif) and outputs a second reset signal (rst 2 ). The second line counter  226  and second pixel counter  227 , which are reset by the second reset signal (rst 2 ), count lines and pixels, respectively, according to the 13.5 MHz clock signal generated by the clock generator  230 . The video encoder sync generator  228  outputs the horizontal synchronizing signal (H_sync) and the field signal (field) to the video encoder  260 , based on the outputs of the second line counter  226  and the second pixel counter  227 . 
     When the frame pulse (frame_dif) shown in FIG. 5A is output from the digital interface  210 , the first edge detector  221  detects the edge of the frame pulse (frame_dif) based on the 18 MHz clock signal generated by the clock generator  230 , counts the 18 MHz clock signal for as much time (here, marked “a”) as is required by the digital interface  210 , generates a first reset signal (rst 1 ) shown in FIG. 5B, and resets the first line counter  222  and the first pixel counter  223  to a pre-designated value. The system frame reset pulse generator  224  generates the frame reset pulse (frp) shown in FIG. 5C after delaying for a predetermined time after the first line counter  222  and the first pixel counter  223  are reset by the first reset signal (rst 1 ). The period of the frame pulse can vary because the frame reset pulse (frp) of the present invention is generated in response to the edge of the frame pulse (frame_dif). 
     The second edge detector  225  detects the edge of the frame pulse (frame_dif) shown in FIG. 5A, based on the 13.5 MHz clock signal generated by the clock generator  230 , counts the 13.5 MHz clock signal for as much time (here, marked “a&#39;”) as is required by the digital interface  210 , generates the second reset signal (rst 2 ) shown in FIG. 5D, and resets the second line counter  226  and the second pixel counter  227  to a pre-designated value. The video encoder sync generator  228  generates the horizontal synchronizing signal (H_sync) shown in FIG.  5 E and the field signal (field) shown in FIG. 5F, based on the count values of the second line counter  226  and the second pixel counter  227 . The horizontal period of the last line (the 525th line in the case of NTSC) as shown in FIG. 5E can vary. The field signal (field) shown in FIG. 5F is generated in synchronization with a fourth horizontal synchronizing signal, and operates as a field discriminating signal or a field synchronizing signal. 
     The counters  222 ,  223 ,  226 , and  227  are reset in the pixel count value in the middle of the last line (the 525th line in the case of NTSC) in which data is not processed in the system. When the counters are reset in this way, the video signal processing of one frame is identical to that of a conventional system, and the length of one frame can be longer or shorter than that of the conventional system. The length of one frame varying can be solved by free-oscillating the color burst signal in the video encoder  260 . 
     FIG. 6 is a detailed circuit diagram of a color signal processor of the video encoder  260  shown in FIG.  3 . An interpolator  261 , including an up-sampler  262  and a first low pass filter  263 , separates color data from the data output from the source decoder  250  shown in FIG. 3, interpolates the color data, and outputs the interpolated color data. At this time, the color data input to the interpolator  261  is the color data output from the source decoder  250 . An adder  264  adds the interpolated color data to the color burst signal generated by the color burst generator  265 , and outputs the result to a mixer  267  via a second low pass filter. The second low pass filter  266  restricts the band of the color signal before it is modulated by the output signal of a color subcarrier (f sc ) generator  268 . The mixer  267 , which includes a multiplier, mixes the color data, including the color burst signal output from the second low pass filter  266 , with a color subcarrier, and outputs the mixed result to a digital/analog converter (DAC)  269 . The color subcarrier (f sc ) is generated by the color subcarrier generator  268 , based on the horizontal synchronizing signal (H_sync) and the field signal (field) output from the divider  220  of FIG.  3 . The DAC  269  outputs an analog color signal. 
     The color burst generator  265  and the color subcarrier generator  268 , which can be constructed out of a memory such as a ROM, reset the color burst signal in order to maintain a color frame sequence in a normal mode. The color burst signal is reset based on the horizontal synchronizing signal (H_sync) and the field signal (field) input to the color burst generator  265 , every four fields in the case of the NTSC system and every eight fields in the case of the PAL system. The color burst generator  265  resets the color burst signal in a normal mode, based on the digital interface/normal mode signal (DIF/NORMAL). Therefore, the variability of the period of the frame reset pulse is solved by performing color encoding without reset, thereby maintaining the varying frame length. Thus, the frame synchronization of the four or eight field sequence is not performed, but the picture can still be displayed. 
     In the frame synchronizing device of the present invention, it is possible to save design costs and to widen the precision range of the external signal, which is required by equipment operated as a slave, because a high precision voltage controlled oscillator is not necessary.