Abstract:
A memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current of the memory cell; and a sense amplifier coupled to the current mirror for generating an output voltage according to the differential current.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/522,177, filed Aug. 26, 2004, entitled “SENSE AMPLIFIER WITH SENSING CURRENT STABILIZATION” and included herein by reference. 
     
    
     BACKGROUND OF INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention provides a memory unit with sensing current stabilization, and more particularly, a memory unit with a current mirror for maintaining an input current of a sense amplifier.  
         [0004]     2. Description of the Prior Art  
         [0005]     A memory is a vital component in electronic products. The memory includes a memory cell array including memory units each for storing a bit of digital data and performing programming, erasing, and reading according to control signals transmitted from a word line, a bit line, and et al. A sense amplifier in a memory unit is usually provided for sensing digital data stored in a memory cell of the memory unit and generating an output signal corresponding to the digital data when the memory is reading the memory cell.  
         [0006]     Please refer to  FIG. 1 , which illustrates a block diagram of a prior art memory unit  10  in a memory. The memory unit  10 , including a memory cell  12  and a sense amplifier  14 , stores a digital data. The sense amplifier  14  senses an output signal of the memory cell  12  through a bit line  16  and outputs a signal SAOUT accordingly. The output signal of the memory cell  12  is low for programming or high for erasing, for example. Considering high-speed operations, the current of the low-level output signal of the memory cell  12  is set to be greater than 40 μA, while the current of the high-level output signal is set to be smaller than 5 μA. Although the current of the low-level output signal of the memory cell  12  is over eight times the current of the high-level output signal, the difference between the currents is still small (&lt;1 mA). As a result, the sense amplifier  14  may mistake in determining the output signal of the memory cell  12  in different process, voltage and temperature conditions, which may cause the current of the output signal of the memory cell  12  drifting unexpectedly.  
       SUMMARY OF INVENTION  
       [0007]     It is therefore a primary objective of the claimed invention to provide a memory unit with sensing current stabilization.  
         [0008]     According to the claimed invention, a memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current of the memory cell; and a sense amplifier coupled to the current mirror for generating an output voltage according to the differential current.  
         [0009]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0010]      FIG. 1  illustrates a block diagram of a prior art memory unit in a memory.  
         [0011]      FIG. 2  illustrates a schematic diagram of a memory unit of a memory in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0012]     Please refer to  FIG. 2 , which illustrates a schematic diagram of a memory unit  20  of a memory in accordance with the present invention. The memory unit  20  includes a reference cell  22 , a memory cell  24 , a current mirror  26 , a sense amplifier  28 , and transistors  30 ,  32 ,  34 , and  36 . The transistors  30 &amp; 32 , and  34 &amp; 36  triggered by signals V b1  and V b2  are bias and switch circuits. The current mirror  26  includes transistors  38  and  40 , where the drains of the transistor  38  and  40  are coupled to the drains of the transistor  32  and  36 .  
         [0013]     In  FIG. 2 , the reference cell  22  provides a reference current I ref  through the transistors  30  and  32  to the transistor  38  of the current mirror  26 , while the memory cell  24  provides a cell current I cell  through the transistors  34  and  36  to the transistor  40  of the current mirror  26 . As those skilled in the art recognize, the current mirror  26  provides same-direction and almost same-degree currents in the drains of the transistors  38  and  40 . Therefore, a current I div  in the drain of the transistor  40  almost equals the current I ref , so an input current I sense  of the sense amplifier  28  is the difference between the current I cell  and the current I div , or I sense =I cell −I div ≈I cell −I ref . With the current I ref  provided by the reference cell  22 , the input current I sense  of the sense amplifier  28  can resist current drifting of the memory cell  24 .  
         [0014]     For example, if the reference current I ref  of the reference cell  22  is set to equal a low-level output current (5 μA) of the memory cell  24 , the current I div  also closes to the low-level current (5 μA). When the memory is reading a high-level digital data, such as logic  1 , stored in the memory cell  24 , the memory cell  24  outputs the low-level current (5 μA) I cell . As mentioned above, the current I sense  equals the differential current between the currents I cell  and I ref , so in this case, the current I sense  is almost 0 (I sense =I cell −I div =5 μA−5 μA=0), and the sense amplifier  28  outputs the corresponding output SAO.  
         [0015]     In some situations, such as in different operating temperature, pressure, voltage, etc., the output current I cell  of the memory cell  24  may drift in different ranges. However, in the present invention, both the memory cell  24  and the reference cell  22  suffer the same situation. That is, even if the current I cell  drifts owing to the memory cell  24  operating in an unideal condition, the current I ref  also drifts in the same range. Therefore, the current I sense  maintains almost 0 if the output current I cell  of the memory cell  24  is low.  
         [0016]     On the other hand, if the memory cell  24  stores a low-level digital data, such as logic  0 , when the memory is reading the low-level digital data, the memory cell  24  outputs the high-level current (40 μA) I cell  to the transistor  40  of the current mirror  26 , and the current I sense  becomes 35 μA (40 μA−5 μA). As mentioned above, if the high-level current I cell  drifts to 45 μA, the current I ref  drifts with the same range to 10 μA. Therefore, the current I sense  is still 35 μA.  
         [0017]     In short, the present invention memory unit prevents the sense amplifier from mistaking in determining high or low of the currents I cell . That is, even if the difference between the high-level and the low-level currents I cell  is small, or if the current I cell  drifts in different conditions, the present invention can maintain the input current I sense  of the sense amplifier. In addition, other than setting the reference current I ref  as the low-level current I cell , the present invention can sets the reference current I ref  equaling the high-level current I cell  as long as the sense amplifier changes the determining standard. Besides, the current mirror of the present invention in  FIG. 2  is just an embodiment. As those skilled in the art recognize, there are other kinds of current mirrors, which can provide same currents in inputs and outputs.  
         [0018]     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.