Abstract:
A method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide.

Description:
BACKGROUND OF THE INVENTION 
   The invention relates to a semiconductor device having gate oxides of different thicknesses. 
   As the size of semiconductor devices, i.e., the channel length of integrated circuit devices, are scaled down, the thickness of the gate oxide layer is also decreased correspondingly. Semiconductor technology has advanced to a point where some devices have very thin gate oxides, e.g., about 60 Angstroms, where high density VLSI circuits are required. 
   Within such devices, the transistors with very thin gate oxides need to be operated with low voltage, e.g., about 3 volts or less, in order to prevent damages to the gate oxides. This low voltage limitation may not adequate for the input/output (I/O) requirements of the integrated circuit. 
   Many MOS devices external to the high density integrated circuit operate in a 5 volt regime. In fact, some semiconductor devices requires an even higher voltage, e.g., about 21 volts or more, as a power source or for operation of peripheral circuits. These MOS devices are provided with a longer channel length and thicker gate oxide layer for optimal performance. Accordingly, an effective method of providing gate oxides of different thicknesses is needed for semiconductor devices that are configured to handle two or more voltage levels. 
   BRIEF SUMMARY OF THE INVENTION 
   In one embodiment, a method of manufacturing a semiconductor device includes defining a first voltage region, a second voltage region, and a third voltage region on a substrate. The first, second, and third voltage regions are configured to handle first, second, and third voltage levels, respectively, that are different from each other. A nitride layer overlying the first, second, and third voltage regions are formed. An oxide layer overlying the nitride layer is formed. The oxide layer is patterned to expose a portion of the nitride layer overlying the first voltage region. The exposed portion of the nitride layer is removed using a wet etch process. A first gate oxide layer overlying the first voltage region is formed. Portions of the oxide layer and the nitride layer overlying the second and third voltage regions are removed. Impurities are selectively implanted into the third voltage region while preventing the impurities from being provided in the second voltage region. A second gate oxide overlying the second voltage region and a third gate oxide overlying the third voltage region are formed simultaneously. The second gate oxide is thicker than the third gate oxide. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1-7  illustrate a method of forming multiple gate oxides on a substrate using impurities provided in a given voltage region according to embodiments of the present invention. 
       FIGS. 8-14  illustrate a method of forming multiple gate oxides on a substrate by selectively forming gate oxides at high, medium, and low voltage regions according to embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The embodiments of the present invention relates to fabricating a semiconductor device configured to handle a plurality of different voltages, e.g., three different voltage levels. 
     FIG. 1  illustrates a semiconductor substrate  100  having a high voltage area  102 , a medium voltage area  104 , and a low voltage area  106  according to one embodiment of the present invention. A semiconductor device having multiple gate oxides is fabricated using the substrate  100 . The substrate  100  is a silicon substrate in the present embodiment. The areas or regions  102 - 106  are separated by a plurality of isolation structures  108 , e.g., a shallow trench isolations. 
   In one embodiment, the high voltage area  102  is configured to handle about 21 volts or more, and the medium voltage area  104  is configured to handle about 5 volts, and the low voltage area  106  is configured to handle about 2.5 volts or 3.3 volts. Accordingly, the high voltage region  102  is provided with a thick gate oxide layer (also referred to as “a first gate oxide”); the medium voltage region  104  is provided with a medium gate oxide (also referred to as “a second gate oxide”); the low voltage region  106  is provided with a thin gate oxide (also referred to as “a third gate oxide”). The terms “first gate oxide,” “second gate oxide,” and “third gate oxide” are used to refer to the high voltage region, medium voltage region, and low voltage region for purposes of illustrating the present embodiment in the detailed description, and should not be used for interpreting the scope of the invention. 
   Referring to  FIG. 2 , a pad oxide layer  110  is formed overlying the silicon substrate  100 . The pad oxide layer may be formed by thermal oxidation, rapid thermal oxidation (“RTO”), or by chemical vapor deposition (“CVD”). The pad oxide layer protects the surface of the silicon substrate from being damaged during the subsequent processing steps for forming the gate oxides of different thicknesses. The pad oxide layer  110  is preferably formed as thin as possible for easy removal subsequently, e.g., using a simple pre-gate clean (diluted HF). The oxide layer  110  is formed to a thickness of between about 40 angstroms and 140 angstroms. 
   A silicon nitride layer  112  is deposited overlying the pad oxide layer  110 . The nitride layer  112  is used as a hard mask to etch the pad oxide layer  110  in a subsequent process step. In one embodiment, the silicon nitride layer  112  is deposited by a low-pressure chemical vapor deposition (“LPCVD”) process to a thickness of between about 250 angstroms and 450 angstroms. 
   An oxide layer  114  is deposited overlying the silicon nitride layer  112 . The oxide layer  114  is used to provide a hard mask for etching the silicon nitride layer  112  in a subsequent step. The oxide layer  114  is preferably composed of silicon dioxide deposited by LPCVD using a tetraethoxysilane source. The oxide layer  114  is preferably deposited to a thickness of between about 200 angstroms and 400 angstroms. 
   A photoresist layer  116  is deposited overlying the oxide layer  114 . The photoresist layer  116  is patterned to uncover a portion of the oxide layer  114  that is overlying the high voltage region  102 . 
   Referring to  FIG. 3 , the uncovered portion of the oxide layer  114  is patterned to expose a portion of the nitride layer  114  overlying the high voltage region  102 . The oxide layer may be patterned using a wet or dry process. In the present embodiment, the oxide layer is patterned by using a wet etch process, e.g., using HF solvent, to avoid residues that may result from a dry etch process. The nitride layer  112  protects the pad oxide layer and the silicon substrate from the wet etch process. Accordingly, the pad oxide layer may be kept to a minimum thickness for easy removal by use of the nitride layer. 
   The photoresist layer  116  is stripped away using either a plasma strip (ashing) or a chemical wet strip. The silicon nitride layer  112  protects the pad oxide layer  110  and the silicon substrate  100  during the photoresist stripping process. 
   The exposed portion of the silicon nitride layer  112  is etched using a wet etch process to prevent formation of etch residues as a result of a dry etch process according to one embodiment of the present invention. For example, a phosphoric acid (H 3 PO 4 ). The phosphoric acid has a high etch selectivity, i.e., etches the silicon nitride layer at a much higher rate than the oxide layer. The phosphoric acid accordingly exposes a portion of the pad oxide layer overlying the high voltage region  102 . 
   Referring to  FIG. 4 , the exposed pad oxide layer  110  and the oxide layer  114  are etched away simultaneously according to one embodiment of the present invention. That is, a pre-gate clean process is used to remove both the pad oxide layer  110  and the masking oxide layer  114 . 
   A first gate oxide  118  is grown overlying the silicon substrate  110  in the high voltage region  102 . The first gate oxide layer is a high quality oxide. In one embodiment, the thick gate oxide layer  118  is grown to a thickness of between about 600 angstroms and 1200 angstroms. The first gate oxide may be configured to handle about 21 volts, about 32 volts, or about 40 volts according to the present embodiment. 
   The silicon nitride layer  112  remaining on the medium and low voltage regions  104  and  106  are etched away using a wet etch process. For example, a phosphoric acid is used to selectively remove the remaining silicon nitride layer without etching the first gate oxide  118 . 
   Referring to  FIG. 5 , a photoresist layer  120  is formed overlying the silicon substrate  110 . The photoresist layer  120  is patterned to expose a portion of the pad oxide layer  110  overlying the low voltage region  106 . 
   In one embodiment, nitrogen is implanted into the low voltage region  102 . The low voltage region  102  is provided with nitrogen concentration of about 10 14 /cm 2 . The nitrogen concentration may be about 10 14 /cm 2  to about 3.5×10 14 /cm 2 . The nitrogen is provided in the low voltage region to slow the oxide growth, as will be explained later. In one embodiment, a desired nitrogen concentration is obtained by driving the nitrogen ions into the substrate using a low energy, e.g., about 25 KeV. 
   Referring  FIG. 6 , the photoresist layer  120  is stripped by ashing or wet process. The pad oxide layer  110  overlying the medium and low voltage regions  104  and  106  is etched away. 
   Referring to  FIG. 7 , an oxide growth step is performed to form a second gate oxide  122  overlying the medium voltage region  104  and a third gate oxide  124  overlying the low voltage region  106 . The nitrogen implanted in the low voltage region  106  lowers the oxide growth rate at the low voltage region  106 . Accordingly, the third gate oxide  124  is provided to be about 20-30 angstroms less in thickness than the second gate oxide  122 . In one embodiment, the second gate oxide is about 34 angstroms to about 60 angstroms, and the third gate oxide is about 50 angstroms to about 100 angstroms. 
   A polysilicon layer  126  is formed overlying the first, second, and third gate oxides  120 ,  122 , and  124  according to one embodiment of the present invention. The polysilicon is used as gate electrodes for the high, medium, and low voltage regions. Accordingly, the silicon substrate  100  is provided with multiple gate oxides, i.e., the first, second, and third gate oxides, having different thicknesses. A semiconductor device manufactured using the substrate  100  is thereby configured to effectively handles at least three different voltage levels. 
     FIG. 8  illustrates a semiconductor substrate  200  having a high voltage area  202 , a medium voltage area  204 , and a low voltage area  106  according to another embodiment of the present invention. A semiconductor device having multiple gate oxides is fabricated using the substrate  200 . The substrate  200  is a silicon substrate in the present embodiment. The areas or regions  202 - 206  are separated by a plurality of isolation structures  208 , e.g., a shallow trench isolations. 
   In one embodiment, the high voltage area  202  is configured to handle about 21 volts or more, and the medium voltage area  204  is configured to handle about 5 volts, and the low voltage area  206  is configured to handle about 2.5 volts or 3.3 volts. Accordingly, the high voltage region  202  is provided with a thick gate oxide layer (also referred to as “a first gate oxide”); the medium voltage region  104  is provided with a medium gate oxide (also referred to as “a second gate oxide”); the low voltage region  106  is provided with a thin gate oxide (also referred to as “a third gate oxide”). 
   Referring to  FIG. 9 , a pad oxide layer  210  is formed overlying the silicon substrate  200 . The pad oxide layer may be formed by thermal oxidation, or by rapid thermal oxidation (“RTO”). The pad oxide layer protects the surface of the silicon substrate from being damaged during the subsequent processing steps for forming the gate oxides of different thicknesses. The pad oxide layer  210  is preferably formed as thin as possible for easy removal subsequently, e.g., using a simple pre-gate clean (diluted HF). The oxide layer  210  is formed to a thickness of between about 40 angstroms and 140 angstroms. 
   A silicon nitride layer  212  is deposited overlying the pad oxide layer  210 . The nitride layer  212  is used as a hard mask to etch the pad oxide layer  210  in a subsequent process step. In one embodiment, the silicon nitride layer is deposited by a low-pressure chemical vapor deposition (“LPCVD”) process to a thickness of between about 250 angstroms and 450 angstroms. 
   An oxide layer  214  is deposited overlying the silicon nitride layer  212 . The oxide layer  214  is used to provide a hard mask for etching the silicon nitride layer  212  in a subsequent step. The oxide layer  214  is preferably composed of silicon dioxide deposited by LPCVD using a tetraethoxysilane source. The oxide layer  214  is preferably deposited to a thickness of between about 200 angstroms and 400 angstroms. 
   A photoresist layer  216  is deposited overlying the oxide layer  214 . The photoresist layer  216  is patterned to uncover a portion of the oxide layer  214  that is overlying the high voltage region  202 . 
   Referring to  FIG. 10 , the uncovered portion of the oxide layer  214  is patterned to expose a portion of the nitride layer  214  overlying the high voltage region  202 . The oxide layer may be patterned using a wet or dry process. In the present embodiment, the oxide layer is patterned by using a wet etch process, e.g., using HF solvent, to avoid residues that may result from a dry etch process. The nitride layer  212  protects the pad oxide layer and the silicon substrate from the wet etch process. Accordingly, the pad oxide layer may be kept to a minimum thickness for easy removal by using the nitride layer. 
   The photoresist layer  216  is stripped away using either a plasma strip (ashing) or a chemical wet strip. The silicon nitride layer  212  protects the pad oxide layer  210  and the silicon substrate  200  during the photoresist stripping process. 
   The exposed portion of the silicon nitride layer  212  is etched using a wet etch process to prevent formation of etch residues as a result of a dry etch process according to one embodiment of the present invention. For example, a phosphoric acid (H 3 PO 4 ). The phosphoric acid has a high etch selectivity, i.e., etches the silicon nitride layer at a much higher rate than the oxide layer. The phosphoric acid accordingly exposes a portion of the pad oxide layer overlying the high voltage region  202 . 
   Referring to  FIG. 11 , the exposed pad oxide layer  210  and the oxide layer  214  are etched away simultaneously according to one embodiment of the present invention. That is, a pre-gate clean process is used to remove both the pad oxide layer  210  and the masking oxide layer  214 . 
   A first gate oxide  218  is grown overlying the silicon substrate  200  in the high voltage region  202 . The first gate oxide layer is a high quality oxide. In one embodiment, the thick gate oxide layer  218  is grown to a thickness of between about 600 angstroms and 1200 angstroms. 
   The silicon nitride layer  212  remaining on the medium and low voltage regions  204  and  206  are etched away using a wet etch process. For example, a phosphoric acid is used to selectively remove the remaining silicon nitride layer without etching the first gate oxide  218 . 
   Referring to  FIG. 12 , the removal of the silicon nitride layer  212  exposes the pad oxide layer  210  remaining over the medium and low voltage regions  204  and  206 . This pad oxide is removed using a pre-gate clean process to expose the underlying silicon substrate. An oxide layer  221  is grown overlying the medium and low voltage regions  204  and  206  to a thickness suitable for handling a medium voltage level, e.g., about 5 volts. In one embodiment, the oxide layer  221  is provided with a thickness of about 70 angstroms to about 110 angstroms. Alternatively, the oxide layer may be grown to a thickness suitable for handling a low voltage level, e.g., about 3 volts. 
   Referring to  FIG. 13 , a photoresist layer  223  is formed overlying the silicon substrate  200 . The photoresist layer  223  is patterned to expose the low voltage region  206  to expose a portion of the oxide layer  221  overlying the low voltage region  206 . The exposed portion of the oxide layer  221  is removed using a wet etch process. A HF solvent is used for this purpose according to one embodiment. A dry etching preferably is not used in order to prevent residue problems and damages to the silicon substrate that may result from dry etch processes. 
   Referring to  FIG. 14 , the photoresist layer  223  is stripped. The pre-gate oxidation cleaning is performed on the exposed silicon substrate in the low voltage region  206 . Thereafter, a third gate oxide  224  is grown in the low voltage region  206  to a suitable thickness to handle a low voltage level. In one embodiment, the third gate oxide is provided with a thickness of about 34 angstroms to about 60 angstroms. The oxide layer  221  in medium voltage region  204  is increased to 100˜120 A and is a second gate oxide. A polysilicon layer  226  is formed overlying the high, medium, and low voltage regions  202 - 206  to serve as a gate electrode. Accordingly, the substrate  200  is provided with three different gate oxides, each with different thicknesses suitable for handling corresponding different voltage levels. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.