Abstract:
A power allocating apparatus has a plurality of power supply modules coupled to a plurality of loads via a plurality of power lines, respectively. The power allocating apparatus includes a first switch element and a control device. The first switch element has a first connecting terminal and a second connecting terminal coupled to an output terminal of a power supply module with a relatively high power conversion rate and an output terminal of a power supply module with a second power conversion rate, respectively, and selectively allocates a power generated by the power supply module with the relatively high power conversion rate to a predetermined number of loadings simultaneously according to on or off states of the first switch element. The control device is coupled to the first switch element to control the first switch element to enter an on state or an off state.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a power allocating apparatus, and more particularly, to a power allocating apparatus that allocates power of a plurality of power supply modules. 
         [0003]    2. Description of the Prior Art 
         [0004]    Energy saving is a prescient topic. To conserve energy, all electronic equipments have respective standard power conversion rates according to the regulations given by the U.S. environment protection agency (EPA). For example, the power conversion rate of the power supply of a personal computer sold in the U.S. has to be higher than 80 percent. In a conventional computer system, the configuration of a switching power supply includes a main power supply and an auxiliary power supply as shown in  FIG. 1 .  FIG. 1  is a diagram illustrating the configuration of a conventional switching power supply  100 . The conventional switching power supply  100  comprises a main power device  102  and an auxiliary power device  104 , wherein the main power device  102  is utilized for providing a first current I o1  and a first voltage V o1  for a main power load  106 , and the auxiliary power device  104  is utilized for providing a second current I o2  and a second voltage V o2  for an auxiliary power load  108 . When the computer system is under a normal operation mode, the main power device  102  provides the first current I o1  and the first voltage V o1  to the main power load  106 , while the auxiliary power device  104  provides the second current I o2  and the second voltage V o2  to the auxiliary power load  108 ; when the computer is under a sleep mode, the main power device  102  does not provide the first current lo, and the first voltage V o1  to the main power load  106 , while the auxiliary power device  104  continues to provide the second current I o2  and the second voltage V o2  to the auxiliary power load  108  to maintain the basic operation of the computer system. In other words, the auxiliary power device  104  is always on. However, in comparison with the output power of the main power device  102 , the auxiliary power device  104  has a relatively low output power (i.e., the second current I o2  and the second voltage V o2 ). For example, the output power of the auxiliary power device  104  may only be 10-20 W (watt). Therefore, for the purpose of saving costs, the conventional auxiliary power device  104  is always implemented by a power supply having a relatively low power conversion rate. For example, when the conventional auxiliary power device  104  operates under a heavy load, the power conversion rate is merely 78 percent. Since the main power consumed by the power system is provided by the main power device  102 , the conventional main power device  102  is implemented by the power supply having a relatively high power conversion rate. Furthermore, when the conventional computer system operates under the normal operation mode, the main power device  102  and the auxiliary power device  104  provide power to, respectively, the main power load  106  and the auxiliary power load  108  at the same time, therefore the entire power conversion rate of the switching power supply may be affected by the auxiliary power device  104  having the relatively low power conversion rate. In other words, the entire power conversion rate of the switching power supply may be decreased as a result of the low power conversion rate of the auxiliary power device  104 . Consequently, the power conversion rate of the conventional switching power supply may not conform to the specifications regulated by the EPA under the normal operation mode (higher than 80 percent). Therefore, to increase the power conversion rate of the power supply device of the computer is an urgent problem in the field of power supply. 
       SUMMARY OF THE INVENTION 
       [0005]    One of the objectives of the present invention is therefore to provide a power allocating apparatus that allocates power of a plurality of power supply modules. 
         [0006]    According to an embodiment of the present invention, a power allocating apparatus applied in a plurality of power supply modules is disclosed, wherein the plurality of power supply modules are coupled to a plurality of loads via a plurality of power lines, respectively. The power allocating apparatus comprises a first switch element, and a control device. The first switch element has a first connecting terminal and a second connecting terminal coupled to an output terminal of a power supply module with a relatively high power conversion rate and an output terminal of a power supply module with a relatively low power conversion rate, respectively, and selectively allocates a power generated by the power supply module with a relatively high power conversion rate to a predetermined number of loadings simultaneously according to on or off states of the first switch element. The control device is coupled to the first switch element for generating the control signal to control the first switch element to enter an on state or an off state. 
         [0007]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a diagram illustrating the configuration of a conventional switching power supply. 
           [0009]      FIG. 2  is a diagram illustrating a power allocating apparatus according to an embodiment of the present invention. 
           [0010]      FIG. 3  is a timing diagram illustrating an output signal, an output voltage, a control voltage, and an output current of the power allocating apparatus as shown in  FIG. 2 . 
           [0011]      FIG. 4  is a diagram illustrating the power allocating apparatus according to a second embodiment of the present invention. 
           [0012]      FIG. 5  is a diagram illustrating the power allocating apparatus according to a third embodiment of the present invention. 
           [0013]      FIG. 6  is a diagram illustrating the power allocating apparatus according to a fourth embodiment of the present invention. 
           [0014]      FIG. 7  is a diagram illustrating a total power comparing table of the first embodiment power allocating apparatus and the above-mentioned conventional switching power supply operated under the normal operation mode. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0016]    Please refer to  FIG. 2 .  FIG. 2  is a diagram illustrating a power allocating apparatus  200  according to an embodiment of the present invention. The power allocating apparatus  200  comprises a main power supply module  202 , an auxiliary power supply module  204 , a first switching element  206  installed between the main power supply module  202  and the auxiliary power supply module  204 , a controlling device  208  for controlling the first switching element  206 , and a second switching element  210  installed between the auxiliary power supply module  204  and an auxiliary power loading  214 . 
         [0017]    A first power line  2022  is electrically coupled between the main power supply module  202  and a main power loading  212  for transferring power, while a second power line  2042  is electrically coupled between the auxiliary power supply module  204  and an auxiliary power supply loading  214  for transferring power. 
         [0018]    The second switching element  210  is coupled between an output terminal N 1  of the auxiliary power supply module  204  and a terminal N 2  for selectively switching off the supplying power of the auxiliary power supply module  204  to the auxiliary power loading  214  (i.e., opening the path between the auxiliary power supply module  204  and the auxiliary power loading  214 ). Furthermore, in order to selectively allocate an output current Io 1  of the main power supply module  202  to the main power loading  212  and the auxiliary power supply loading  214  at the same time, an additional third power line  2026  is installed between an output terminal N 3  of the first power line  2022  and the terminal N 2  of the second power line  2042 , and the first switching element  206  is further installed on the third power line  2026 . 
         [0019]    When the first switching element  206  is turned on (i.e., shorted), the second switching element  210  is turned off (i.e., opened) for generating a current having a unitary direction between the output terminal N 1  and the terminal N 2 . In other words, the second switching element  210  is an unidirectional switch and may be implemented by a diode in one of the embodiments of the present invention as shown in  FIG. 2 , in which a diode D 1  is applied as the second switching element  210 . The diode D 1  has an anode coupled to the output terminal N 1  of the auxiliary power supply module  204  and a cathode coupled to the terminal N 2  of the first switching element  206 . 
         [0020]    The first switching element  206  is a bidirectional switch, which is implemented by an N type field effect transistor Q 1  in this embodiment. The N type field effect transistor Q 1  has a source terminal coupled to an output terminal N 3  of the main power supply module  202 , a source terminal coupled to the cathode (i.e., terminal N 2 ) of the diode D 1 , and a gate terminal N 4  coupled to the controlling device  208 , where the controlling device  208  outputs a control voltage Vd to the gate terminal N 4  to selectively allocate the output current Io 1  of the main power supply module  202  to the main power loading  212  and the auxiliary power loading  214  at the same time. Please note that, although the first switching element  206  is implemented by the N type field effect transistor Q 1  in this embodiment, this is not meant to be a limitation of the present invention. In other words, any switching elements having the characteristic of selectively shorting or opening the path between the output terminal N 3  and the terminal N 2  belong within the scope of the present invention. For example, in another embodiment of the present invention, the first switching element  206  may be implemented by a P type field effect transistor, a bipolar junction transistor (BJT) or a relay, etc. 
         [0021]    The main power supply module  202  outputs an output voltage Vo 1 , and the auxiliary power supply module  204  outputs an output voltage Vo 2 , wherein the output voltage Vo 1  is designed to be higher than the output voltage Vo 2  for turning on the N type field effect transistor Q 1 . Accordingly, when the N type field effect transistor Q 1  is turned on, an output current Io 2  may be divided from the output current Io 1  of the main power supply module  202  and the output current Io 2  may replace an output current Io 3  generated by the auxiliary power supply module  204 . Furthermore, the characteristic of unitary direction of the diode D 1  allows the output current Io 3  generated by the auxiliary power supply module  204  to be supplied to the auxiliary power loading  214  during a power off mode, and prevents the output current Io 2  from flowing back to the auxiliary power supply module  204  during a normal mode. Meanwhile, during the power off mode, in order to prevent the output current Io 3  generated by the auxiliary power supply module  204  from flowing to the main power supply module  202 , the body terminal of the N type field effect transistor Q 1  is coupled to its source terminal such that the N type field effect transistor Q 1  is equivalently a body diode D 4 . Therefore, when the power allocating apparatus  200  operates under the power off mode, the equivalent body diode D 4  prevents the output current  103  outputted from the auxiliary power supply module  204  from flowing to the main power supply module  202 . If the output current Io 3  flows back to the main power supply module  202  during the power off mode, it may lower the total power conversion rate of the power allocating apparatus  200 , or generate an error operation of the power allocating apparatus  200 . 
         [0022]    Please refer to  FIG. 2  again. The control device  208  of the power allocating apparatus  200  comprises a driving circuit  2082 , a timing control circuit  2084 , and a detecting circuit  2086 . One of the purposes of the driving circuit  2082  is to generate the control voltage Vd, which is higher than the output voltage Vo 1 , to turn on the N type field effect transistor Q 1 , and any other driving circuits capable of generating the control voltage Vd that is higher than the output voltage Vo 1  also belong within the scope of the present invention. For example, the driving circuit  2082  can be implemented as a boost driving circuit, a buck-boost driving circuit, or a flyback driving circuit. In the embodiment, the driving circuit  2082  comprises a transformer L 1 , a diode D 3 , and a capacitor C, wherein the transformer L 1 , which includes a power inductor, generates the control voltage Vd according to the duty-cycle of a pulse-width modulation (PWM) signal Vref. Since the operation of the driving circuit  2082  is well-known to those skilled in this art, further description is omitted here for brevity. 
         [0023]    The timing control circuit  2084  is coupled to the driving circuit  2082  in this embodiment for controlling the driving circuit  2082 . More specifically, the timing control circuit  2084  selectively outputs the control signal Vd generated by the driving circuit  2082  according to an output signal PGO generated by a power protection circuit, such as a house keeping IC, wherein the output signal PGO is a power good output signal. Please note that those skilled in this art may also use a power fault output signal generated by the house keeping IC to control the timing control circuit  2084  after some modifications are performed to the embodiment, and these modifications also belong within the scope of the present invention. The timing control circuit  2084  comprises a bipolar junction transistor Q 2 , a resistive element R 2 , a field effect transistor Q 3 , and a resistive element R 3 , wherein an emitter terminal of the bipolar junction transistor Q 2  is coupled to an output terminal N 5  of the driving circuit  2082 , the resistive element R 2  is coupled between the emitter terminal and a base terminal of the bipolar junction transistor Q 2 , the field effect transistor Q 3  comprises a source terminal coupled to a ground voltage Vgnd, a gate terminal of the field effect transistor Q 3  receives the output signal PGO, and the resistive element R 3  is coupled between the base terminal of the bipolar junction transistor Q 2  and a drain terminal of the field effect transistor Q 3 . 
         [0024]    Furthermore, the detecting circuit  2086  comprises a bipolar junction transistor Q 4 , a resistive element R 4 , a bipolar junction transistor Q 5 , a resistive R 5 , a resistive R 6 , and a zener diode D 2 . The detecting circuit  2086  detects the output power of the main power supply module  202  to selectively output the control signal Vd outputted by the timing control circuit  2084  to the first switching element  206 . The bipolar junction transistor Q 4  has an emitter terminal coupled to an output terminal N 6  of the timing control circuit  2084 , the resistive element R 4  is coupled between the emitter terminal (i.e., output terminal N 6 ) and a base terminal of the bipolar junction transistor Q 4 , the bipolar junction transistor Q 5  has an emitter terminal coupled to the ground voltage Vgnd, the resistive element R 5  is coupled between a base terminal of the bipolar junction transistor Q 4  and a collector terminal of the bipolar junction transistor Q 5 , a terminal of the resistive element R 6  is coupled to a base terminal of the bipolar junction transistor Q 5 , and the zener diode D 2  has an anode coupled to the other terminal of the resistive R 6 , and a cathode coupled to the output terminal N 3  of the main power supply module  202 . 
         [0025]    Please refer to  FIG. 3 .  FIG. 3  is a timing diagram illustrating the output signal PGO, the output voltage Vo 1  the control voltage Vd, the output voltage Vo 2 , the output current Io 1 , the output current Io 2 , and the output current Io 3  of the power allocating apparatus  200  as shown in  FIG. 2 . Please note that, in order to describe the spirit of the present invention more clearly, it is assumed that the voltage drop between the collector terminal and the emitter terminal of the bipolar junction transistor Q 2  is approximately zero when the bipolar junction transistor Q 2  is turned on in this embodiment as well as the bipolar junction transistor Q 4 . In order to describe the spirit of the present invention more clearly, the normal operation mode of the power allocating apparatus  200  is set between time T 1  and time T 2 , while the power off mode is beyond time T 1  and time T 2  as shown in  FIG. 3 . Furthermore, in the time intervals beyond time T 1  and time T 2 , the auxiliary power supply module  204  of the embodiment provides the output voltage Vo 2  having a voltage level of v o2  to the auxiliary power loading  214 . 
         [0026]    When the power allocating apparatus  200  operates under the normal operation mode, the main power supply module  202  generates the output voltage Vo 1  having a voltage level of v o1  to the main power loading  212 . As shown in  FIG. 3 , when the output signal PGO turns on the field effect transistor Q 3  at time T 1 , the bipolar junction transistor Q 2  is also turned on as the resistive element R 2  induces a voltage drop when a current is passed through the resistive element R 2 . Accordingly, the control voltage Vd generated by the driving circuit  2082  is passed to the output terminal N 6 . Under the normal operation mode, if the voltage level (i.e., voltage level of v o1 ) of the output voltage Vo 1  generated by the main power supply module  202  is high enough to break down the zener diode D 2 , i.e., the voltage drop of the zener diode D 2  is higher than its break down voltage Vz, then the bipolar junction transistor Q 5  may be turned on. Accordingly, the bipolar junction transistor Q 4  can also be turned on as the resistive element R 4  induces a voltage drop when a current is passed through the resistive element R 4 . Then, the control voltage Vd at the output terminal N 6  is transmitted to the gate terminal N 4  of the N type field effect transistor Q 1 . According to the embodiment of the present invention, the control voltage Vd generated by the driving circuit  2082  is higher than the voltage level v o1  of the output voltage Vo 1  and a resistive element R 1  is installed between the gate terminal N 4  and the output terminal N 3  for inducing a current I 1  to flow through the resistive element R 1  under the normal operation mode in order to turn on the N type field effect transistor Q 1  properly. Accordingly, the voltage drop of the resistive element R 1  generated by the current I 1  may turn on the N type field effect transistor Q 1  at time T 1 , while the second switching element  210  is turned off (i.e., open). Therefore, the voltage level v o2  of the output voltage Vo 2  is increased to the same voltage level as the output voltage Vo 1 , i.e., the voltage level of v o1 , at time T 1  as shown in  FIG. 3 . Please note that, in order to describe the spirit of the present invention more clearly, it is assumed that the transmitting time to transmit the control voltage Vd from the bipolar junction transistor Q 2  to the gate terminal N 4  via the bipolar junction transistor Q 4  is approximately zero in the embodiment. 
         [0027]    Since the voltage level v o1  of the output voltage Vo 1  is higher than the voltage level v o2  of the output voltage Vo 2 , the current i o1  of the output current Io 1  generated by the main power supply module  202  is provided to the main power loading  212  and the auxiliary power loading  214  at the same time under the normal operation mode. Therefore, the output current Io 3 , which has the current of i o3 , generated by the auxiliary power supply module  204  may be replaced by the output current Io 2  such that the output current Io 3  outputted from the auxiliary power supply module  204  can be reduced to approximately zero while the current of the output current Io 2  is increased to approximate i o3 , as shown in time T 1  of  FIG. 3 . 
         [0028]    Please refer to  FIG. 3  again. When the output signal PGO generated by the house keeping IC is switched to a low level voltage at time T 2 , the power allocating apparatus  200  enters the power off mode, while the main power allocating apparatus  202  stops outputting the output voltage Vo 1  having the voltage level of v o1  to the main power loading  212 . When the output signal PGO turns off the field effect transistor Q 3  at time T 2 , and when the voltage level of the output voltage Vo 1  is not higher than the break down voltage Vz of the zener diode D 2 , the bipolar junction transistor Q 2  and the bipolar junction transistor Q 4  are off such that the control voltage Vd is switched to a low voltage level and turns off the N type field effect transistor Q 1 . Therefore, the path between the output terminal N 3  and the terminal N 2  is open (i.e., non-conductive), the current i o2  of the output current Io 2  is changed to zero, and then the auxiliary power supply module  204  outputs the output voltage Vo 2  having the voltage level of v o2  and the output current Io 3  having the current of i o3  to the auxiliary power loading  214  under the power off mode, as shown at time T 2  in  FIG. 3 . 
         [0029]    To sum up, when the power allocating apparatus  200  operates under the normal operation mode, the powers supplied to the main power loading  212  and the auxiliary power loading  214  are provided by the main power supply module  202  having a relatively higher power conversion rate, while the auxiliary power supply module  204  having a relatively lower power conversion rate does not provide power. Therefore, the auxiliary power supply module  204  does not consume power during the normal operation mode. Compared to the above-mentioned conventional method, when the power allocating apparatus  200  of the present invention operates under the normal operation mode, the main power supply module  202  and the auxiliary power supply module  204  do not provide power to the main power loading  212  and the auxiliary power loading  214  at the same time, and only the powers required by the main power loading  212  and the auxiliary power loading  214  are provided by the main power supply module  202  at the same time. Furthermore, since the auxiliary power supply module  204  has the relatively low power conversion rate, the power off of the auxiliary power supply module  204  during the normal operation mode further improves the whole power conversion rate of the power allocating apparatus  200 . When the power allocating apparatus  200  operates under the power off mode, the main power supply module  202  having the relatively high power conversion rate does not provide power, and the power required by the auxiliary power loading  214  can then be provided by the auxiliary power supply module  202  having the relatively low power conversion rate. 
         [0030]    Accordingly, the whole power conversion rate of the power allocating apparatus  200  can be increased and is not affected by the auxiliary power supply module  204  having the relatively low power conversion rate. Please note that those skilled in this art will readily understand that the relatively high power conversion of the main power supply module  202  corresponds to the power conversion rate of a relatively high power, i.e., the relatively high power conversion is measured when the main power supply module  202  outputs the relatively high power. However, the power conversion rate of the main power supply module  202  is not maintained at a constant high conversion rate, especially when the main power supply module  202  outputs a relatively low power. Furthermore, since the power required by the auxiliary power loading  214  is much lower than that required by the main power loading  212 , the auxiliary power supply module  204  of the power allocating apparatus  200  of the present invention resumes supplying power to the auxiliary power loading  214  during the power off mode but does not utilize the main power supply module  202  to generate a relatively low power for the auxiliary power loading  214 . 
         [0031]    According to the embodiment shown in  FIG. 2 , the timing control circuit  2084  of the control device  208  has the purpose of selectively outputting the control signal Vd generated by the driving circuit  2082 , and the detecting circuit  2086  has the purpose of detecting the power outputted from the main power supply module  202  to selectively output the control signal Vd outputted from the timing control circuit  2084  to the first switching element  206 , therefore the timing control circuit  2084  and the detecting circuit  2086  in the controlling device  208  may be selectively eliminated according to practical requirements, which also belongs within the scope of the present invention. In other words, in another configuration where only the driving circuit  2082  is retained in the controlling device  208 , the characteristics of supplying power to the main power loading  212  and the auxiliary power loading  214  by using the main power supply module  202  having the relatively high power conversion rate are still provided, as shown in  FIG. 4 .  FIG. 4  is a diagram illustrating a power allocating apparatus  400  according to a second embodiment of the present invention. Compared to the power allocating apparatus  200  shown in  FIG. 2 , the second embodiment power allocating apparatus  400  does not comprise the timing control circuit  2084  and the detecting circuit  2086 , while the controlling device  408  of the power allocating apparatus  400  is implemented as a driving circuit as shown in  FIG. 4 . 
         [0032]    The power allocating apparatus  400  comprises a main power supply module  402 , an auxiliary power supply module  404 , a first switching element  406 , a controlling device  408 , and a second switching element  410 , wherein the main power supply module  402  is coupled to a main power loading  412 , and the auxiliary power supply module  404  is coupled to an auxiliary power loading  414 . The second switching element  410  is an unidirectional switch and coupled between an output terminal N 1 ′ of the auxiliary power supply module  404  and a terminal N 2 ′. The first switching element  406  is a bidirectional switch and implemented as an N type field effect transistor Q 1 ′, wherein its source terminal is coupled to an output terminal N 3 ′ of the main power supply module  402 , and a drain terminal is coupled to the cathode (i.e., terminal N 2 ′) of the diode D 1 ′, and a gate terminal N 4 ′ is coupled to the controlling device  408 . Therefore, an output current Io 1 ′ generated by the main power supply module  402  can be selectively allocated to the main power loading  412  and the auxiliary power loading  414  at the same time according to a control voltage Vd′ generated by the controlling device  408 . In other words, the timing of control voltage Vd′ can be adjusted through the on/off operation of the controlling device  408  in this embodiment, where another detecting device may be utilized for detecting the output power of the main power supply module  402  to turn on/off the controlling device  408 . More specifically, the operation of the power allocating apparatus  400  will be obvious to those skilled in this art after reading the disclosed operation relating to the power allocating apparatus  200  of  FIG. 2 , thus further description is omitted here for brevity. 
         [0033]    Compared to the above-mentioned conventional method, when the power allocating apparatus  400  of the present invention operates under the normal operation mode, the main power supply module  402  and the auxiliary power supply module  404  do not provide power to the main power loading  412  and the auxiliary power loading  414  respectively at the same time, but the power required by the main power loading  412  and the auxiliary power loading  414  is only provided by the main power supply module  402  at the same time. Furthermore, since the auxiliary power supply module  404  has the relatively low power conversion rate, the power off of the auxiliary power supply module  404  during the normal operation mode further improves the whole power conversion rate of the power allocating apparatus  400 . Accordingly, the whole power conversion rate of the power allocating apparatus  400  can be increased and is not be affected by the auxiliary power supply module  404  having the relatively low power conversion rate. 
         [0034]    Please refer to  FIG. 5 .  FIG. 5  is a diagram illustrating a power allocating apparatus  500  according to a third embodiment of the present invention. Compared to the power allocating apparatus  200  as shown in  FIG. 2 , the third embodiment power allocating apparatus  500  does not comprise the timing control circuit  2084 , and the controlling device  508  of the power allocating apparatus  500  comprises a driving circuit  5082  and a detecting circuit  5086 , as shown in  FIG. 5 . Similar to the embodiment power allocating apparatus  200  shown in  FIG. 2 , one purpose of the driving circuit  5082  is to provide a control voltage Vd″ that is higher than the output voltage Vo 1 ″ for turning on the N type field effect transistor Q 1 ″. Furthermore, the main power supply module  502  generates an output voltage Vo 1 ″, the auxiliary power supply module  504  generates an output voltage Vo 2 ″, and the output voltage Vo 1 ″ is higher than the output voltage Vo 2 ″. Accordingly, when the N type field effect transistor Q 1 ″ is turned on, an output current Io 2 ″ may be divided from the output current Io 1 ″ of the main power supply module  502  and the output current Io 2 ″ may replace an output current Io 3 ″ generated by the auxiliary power supply module  504 . A purpose of the detecting circuit  5086  is to detect the power outputted from the main power supply module  502  to selectively output the control signal Vd″ outputted from the timing control circuit  5084  to the first switching element  506 , which is a bidirectional switch. 
         [0035]    The power allocating apparatus  500  comprises a main power supply module  502 , an auxiliary power supply module  504 , a first switching element  506 , a controlling device  508 , and a second switching element  510 , wherein the main power supply module  502  is coupled to a main power loading  512 , and the auxiliary power supply module  504  is coupled to an auxiliary power loading  514 . The second switching element  510  is an unidirectional switch and coupled between an output terminal N 1 ″ of the auxiliary power supply module  504  and a terminal N 2 ″. 
         [0036]    Furthermore, the timing of the control voltage Vd″ can be adjusted through the on/off operation of the controlling device  5082  in this embodiment. More specifically, the operation of the power allocating apparatus  500  will be obvious to those skilled in this art after reading the disclosed operation relating to the power allocating apparatus  200  of  FIG. 2 , thus further description is omitted here for brevity. 
         [0037]    Compared to the above-mentioned conventional method, when the power allocating apparatus  500  of the present invention operates under the normal operation mode, the main power supply module  502  and the auxiliary power supply module  504  do not provide power to the main power loading  512  and the auxiliary power loading  514  at the same time, and the power required by the main power loading  512  and the auxiliary power loading  514  is only provided by the main power supply module  502 . Furthermore, since the auxiliary power supply module  504  has the relatively low power conversion rate, the power off of the auxiliary power supply module  504  during the normal operation mode further improves the whole power conversion rate of the power allocating apparatus  500 . Accordingly, the whole power conversion rate of the power allocating apparatus  500  can be increased and is not affected by the auxiliary power supply module  504  having the relatively low power conversion rate. 
         [0038]    Please refer to  FIG. 6 .  FIG. 6  is a diagram illustrating a power allocating apparatus  600  according to a third embodiment of the present invention. Compared to the power allocating apparatus  200  as shown in  FIG. 2 , the third embodiment power allocating apparatus  600  does not comprise the detecting circuit  2086 , and the controlling device  608  of the power allocating apparatus  600  comprises a driving circuit  6082  and a detecting circuit  6084 , as shown in  FIG. 6 . Similar to the embodiment power allocating apparatus  200  as shown in  FIG. 2 , one purpose of the driving circuit  6082  is to provide a control voltage Vd′″ that is higher than the output voltage Vo 1 ′″ for turning on the N type field effect transistor Q 1 ′″. Furthermore, the main power supply module  602  generates an output voltage Vo 1 ′″, the auxiliary power supply module  604  generates an output voltage Vo 2 ′″, and the output voltage Vo 1 ′″ is higher than the output voltage Vo 2 ′″. Accordingly, when the N type field effect transistor Q 1 ′″ is turned on, an output current Io 2 ′″ may be divided from the output current Io 1 ′″ of the main power supply module  602  and the output current Io 2 ′″ may replace an output current Io 3 ′″ generated by the auxiliary power supply module  604 . 
         [0039]    The power allocating apparatus  600  comprises a main power supply module  602 , an auxiliary power supply module  604 , a first switching element  606 , a controlling device  608 , and a second switching element  610 , wherein the main power supply module  602  is coupled to a main power loading  612 , and the auxiliary power supply module  604  is coupled to an auxiliary power loading  614 . The second switching element  610  is an unidirectional switch and coupled between an output terminal N 1 ′″ of the auxiliary power supply module  604  and a terminal N 2 ′″. Please note that, the first switching element  606  is a bidirectional switch. 
         [0040]    Furthermore, another detecting device may be utilized for detecting the output power of the main power supply module  602  to turn on/off the controlling device  6082 . More specifically, the operation of the power allocating apparatus  600  will be obvious to those skilled in this art after reading the disclosed operation relating to the power allocating apparatus  200  of  FIG. 2 , thus further description is omitted here for brevity. 
         [0041]    Compared to the above-mentioned conventional method, when the power allocating apparatus  600  of the present invention operates under the normal operation mode, the main power supply module  602  and the auxiliary power supply module  604  do not provide power to the main power loading  612  and the auxiliary power loading  614  respectively at the same time, and the power required by the main power loading  612  and the auxiliary power loading  614  is only provided by the main power supply module  602  Furthermore, since the auxiliary power supply module  604  has the relatively low power conversion rate, the power off of the auxiliary power supply module  604  during the normal operation mode further improves the whole power conversion rate of the power allocating apparatus  600 . Accordingly, the whole power conversion rate of the power allocating apparatus  600  can be increased and is not affected by the auxiliary power supply module  604  having the relatively low power conversion rate. 
         [0042]    Please refer to  FIG. 7 .  FIG. 7  is a diagram illustrating a total power comparing table of the first embodiment power allocating apparatus  200  and the above-mentioned conventional switching power supply  100  operating under the normal operation mode. Please note that the main power supply module  202  has a total output power of 320 W (Watt) and auxiliary power supply module  204  has an output power of 15 W, and the total power comparing table is measured under the testing condition of 115 Vac/60 Hz. Accordingly, compared with the conventional switching power supply  100 , the power allocating apparatus  200  of the present invention saves power of 0.6 W, 0.8 W, and 1.33 W when the loading conditions of the main power loading  212  are 20%, 50%, and 100%, respectively. 
         [0043]    Please note that, although the configuration of the above-mentioned embodiments is constructed by a main power supply module in combination with a main power loading, and an auxiliary power supply module in combination with an auxiliary power loading, this is not meant to be a limitation of the present invention. After reading the description of the disclosed embodiments, those skilled in this art may utilize a plurality of power supply modules to implement the power allocating apparatus of the present invention through some appropriate modifications upon the disclosed embodiments as shown in  FIG. 2 ,  FIG. 4 ,  FIG. 5 , and FIG.  6 ., and this also belongs to the scope of the present invention. 
         [0044]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.