Abstract:
A method of producing a semiconductor device having an SOI transistor and a multi-layer wiring, including: preparing a silicon substrate having a front face and a back face; forming an inter-layer insulation layer on the front face of the silicon substrate; forming a multi-layer wiring in the inter-layer insulation layer; fixing a substrate on the inter-layer insulation layer; thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and forming a channel layer and a gate electrode on a back of the channel layer in the SOI layer, and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    A related patent application is a commonly assigned Japanese Patent Application No. 2001-301180 filed on Sep. 28, 2001, which is incorporated by reference into the present patent application.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a method of producing a semiconductor device having multi-layer wiring structure and the structure of such a semiconductor device, and more particularly, to a method adopting damascene process for producing a semiconductor device having a multi-layer wiring and the structure of such a semiconductor device.  
           [0004]    2. Description of the Related Art  
           [0005]    [0005]FIG. 10 shows a semiconductor device having conventional multi-layer wiring structure indicated in its entirety by  600 . In the semiconductor device  600 , there is an insulation layer  102  of silicon oxide disposed on a silicon substrate  101 . Formed on the insulation layer  102  is an SOI (Silicon On Insulator) transistor (thin film transistor) indicated in its entirety by  110 . The SOI transistor  110  includes a channel layer  113  located between a source  111  and a drain  112 , a gate electrode  114  disposed on the channel layer  113 , and a side wall  115 . An inter-layer insulation layer  103  and a multi-layer wiring  120  are formed on the SOI transistor  110 . The multi-layer wiring  120  consists of contact plugs  121  connected to the source  111  or the drain  112  of the SOI transistor  110  and a wiring layer  122  which connects the contact plugs  121  to each other.  
           [0006]    When the inter-layer insulation layer  103  is deposited on the SOI transistor  110 , asperities owing to the gate electrode and the like cause differences in level to be created on the surface of the inter-layer insulation layer  103  as shown in FIG. 11. This makes it difficult to create a focus margin for a lithography step of forming the contact plugs  121  and the like in the inter-layer insulation layer  103 , and especially, to form the contact plugs  121  and the like when the contact plugs  121  and the like are to be formed in minute patterns. While an alternative approach is planarization of the surface of the inter-layer insulation layer  103  by the CMP method, since such planarization has a limitation, it is difficult to ensure that the surface is sufficiently flat to form the contact plugs and the like as minute patterns.  
           [0007]    In addition, there is a limit to improvement in density of wiring even by means of a multi-layer wiring structure as that shown in FIG. 10.  
         SUMMARY OF THE INVENTION  
         [0008]    The present invention aims at providing a method of producing a semiconductor device having a multi-layer wiring structure of minute definition and high density as well as the structure of such a semiconductor device.  
           [0009]    The present invention is directed to a producing method of producing a semiconductor device including an SOI transistor and a multi-layer wiring. The method includes a step of preparing a silicon substrate having a front face and a back face; an inter-layer insulation layer forming step of forming an inter-layer insulation layer on the front face of the silicon substrate; a wiring step of forming a multi-layer wiring in the inter-layer insulation layer; a substrate fixing step of fixing a substrate on the inter-layer insulation layer; an SOI layer forming step of thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and a transistor forming step of forming a channel layer and a gate electrode on a back face of the formed channel layer, in the SOI layer and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.  
           [0010]    The present invention is also directed to a semiconductor device having an SOI transistor and a multi-layer wiring. The device includes a substrate; an inter-layer insulation layer disposed on the substrate; and on the inter-layer insulation layer disposed an SOI transistor including a gate electrode on the opposite side to the substrate. A multi-layer wiring connected with the SOI transistor is provided within the inter-layer insulation layer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a cross sectional view of the semiconductor device according to the first preferred embodiment of the present invention;  
         [0012]    FIGS.  2 A- 2 J show the steps of producing the semiconductor device according to the first preferred embodiment of the present invention;  
         [0013]    [0013]FIG. 3 is a cross sectional view of the semiconductor device according to the second preferred embodiment of the present invention;  
         [0014]    FIGS.  4 A- 4 E show the steps of producing the semiconductor device according to the second preferred embodiment of the present invention;  
         [0015]    [0015]FIG. 5 is a cross sectional view of the semiconductor device according to the third preferred embodiment of the present invention;  
         [0016]    FIGS.  6 A- 6 H show the steps of producing the semiconductor device according to the third preferred embodiment of the present invention;  
         [0017]    [0017]FIG. 7 is a cross sectional view of the semiconductor device according to the fourth preferred embodiment of the present invention;  
         [0018]    FIGS.  8 A- 8 C show the steps of producing the semiconductor device according to the fourth preferred embodiment of the present invention;  
         [0019]    [0019]FIG. 9 is a cross sectional view of the semiconductor device according to the fifth preferred embodiment of the present invention;  
         [0020]    [0020]FIG. 10 is a cross sectional view of the conventional semiconductor device; and  
         [0021]    [0021]FIG. 11 is a cross sectional view of the conventional semiconductor device as it is being produced. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    First Preferred Embodiment  
         [0023]    [0023]FIG. 1 is a cross sectional view of a semiconductor device according to a first preferred embodiment, indicated in its entirety by  100 , having a multi-layer wiring structure.  
         [0024]    The semiconductor device  100  includes a substrate  1  of silicon for instance. An insulation layer  2  of silicon oxide for example is disposed on the substrate  1 . An inter-layer insulation layer  3  is disposed on the insulation layer  2 , and a multi-layer wiring consisting of a wiring layer  11  and contact plugs  12  is formed in the inter-layer insulation layer  3 . An SOI transistor (thin film transistor)  20  is formed on the inter-layer insulation layer  3 . The SOI transistor  20  includes a source  21 , a drain  22 , a channel layer  23  located between the source  21  and the drain  22 , and a gate electrode  24  and a side wall  25  both formed on the channel layer  23 . A protection film  4  of silicon oxide for example is disposed on the SOI transistor  20 .  
         [0025]    A method of producing the semiconductor device  100  according to the first preferred embodiment will now be described with reference to FIGS. 2A to  2 J. The producing method includes the steps 1 through 10 described below. In this producing method, a multi-layer wiring is formed using single damascene process (Steps 2 through 5).  
         [0026]    Step 1: As shown in FIG. 2A, a substrate  26  of silicon for instance is prepared.  
         [0027]    Step 2: As shown in FIG. 2B, the inter-layer insulation layer  3  of silicon oxide for example is deposited about 400 nm in thickness on the substrate  26 . The CVD method for instance is used at the deposition step. Following this, contact holes  13  are formed with generally used lithographic and etching techniques.  
         [0028]    During these steps, since the element underlying the inter-layer insulation layer  3  is the flat substrate  26 , the surface of the inter-layer insulation layer  3  is also flat.  
         [0029]    Step 3: As shown in FIG. 2C, a barrier metal film consisting of a TiN film of 10 nm and a Ti film of 10 nm for example, and a W film of 300 nm for instance are formed such that the contact holes  13  are filled up with these films. The CVD method for instance is used at this step. Following this, the W film and the barrier metal film on the inter-layer insulation layer  3  are removed by the CMP method, whereby the contact plugs  12  filling the opening portions are obtained.  
         [0030]    Step 4: As shown in FIG. 2D, the inter-layer insulation layer  3  is further deposited and then patterned, thereby forming wiring trenches  28 .  
         [0031]    Step 5: As shown in FIG. 2E, a barrier metal film of a Ta film is formed by sputtering, and further a Cu film is formed by electrolytic plating. Following this, the barrier metal film and the Cu film formed on the inter-layer insulation layer  3  are removed by the CMP method, whereby the wiring layer  11  filling the wiring trenches  28  is obtained. Thus, a multi-layer wiring  10  consisting of the contact plugs  12  and the wiring layer  11  is formed.  
         [0032]    Step 6: As shown in FIG. 2F, the insulation layer  2  of silicon oxide of 1 μm for example is formed on the inter-layer insulation layer  3  by CVD method.  
         [0033]    Step 7: As shown in FIG. 2G, the substrate  1  of silicon or the like prepared separately is bonded onto the insulation layer  2 . The substrate  1  to be placed on the insulation layer  2  is bonded by heating under pressure.  
         [0034]    Step 8: As shown in FIG. 2H, using a mechanical polishing method for instance, the substrate  26  is thinned down to 500 nm or less, or preferably down to about 100 nm. Thus thinned substrate  26  becomes an SOI layer for a SOI transistor creation therein.  
         [0035]    Note that the top and the bottom sides in FIG. 2H and the subsequent drawings are shown vertically opposite to those in FIG. 2G and the preceding drawings.  
         [0036]    Step 9: As shown in FIG. 2I, the substrate (SOI layer)  26  is etched to realize element isolation (mesa isolation). This is followed by ion implantation (channel implantation) in order to make the entire substrate  26  obtain necessary concentration for a channel layer.  
         [0037]    Step 10: As shown in FIG. 2J, after forming a gate oxide film of silicon oxide of about 3 nm for example on the substrate  26 , a polycrystalline silicon film for instance is deposited over the entire surface. The polycrystalline silicon film is then patterned, whereby the gate electrode  24  is defined. Following this, after depositing a silicon oxide film for instance by the CVD method over the entire surface, a side wall  25  is formed on side surfaces of the gate electrode  24  by etching. Ion implantation is thereafter performed using the gate electrode  24  and the side wall  25  as a mask, so that the source  21  and the drain  22  are respectively formed on the sides of the gate electrode  24 . At last, the protection film  4  of silicon oxide for example is disposed over the entire surface by the CVD method.  
         [0038]    Through these steps, the semiconductor device  100  having the multi-layer wiring structure shown in FIG. 1 is completed.  
         [0039]    Thus, with the method of producing the semiconductor device  100  according to the first preferred embodiment, before forming the SOI transistor  20 , the multi-layer wiring  10  is formed below the SOI transistor  20  whose surface has differences in level. This improves the flatness of the top surface of the inter-layer insulation layer  3 , enables to lithographically form minute patterns such as the contact plugs  12 , and permits to form the multi-layer wiring  10  providing minuteness. This also increases the flexibility of wiring and makes it possible to fabricate a highly integrated semiconductor device.  
         [0040]    Second Preferred Embodiment  
         [0041]    [0041]FIG. 3 shows a semiconductor device according to a second preferred embodiment, indicated in its entirety by  200  having multi-layer wiring structure. In FIG. 3, the same reference numerals as those used in FIG. 1 denote identical or corresponding portions.  
         [0042]    In this semiconductor device  200 , the wiring layer  11  of the multi-layer wiring  10  and the contact plugs  12  are formed simultaneously by the dual damascene process.  
         [0043]    A method of producing the semiconductor device  200  according to the second preferred embodiment will now be briefly described with reference to FIGS.  4 A- 4 E. First, the substrate  26  of silicon for instance is prepared as shown in FIG. 4A, and the inter-layer insulation layer  3  of silicon oxide for example is thereafter deposited as shown in FIG. 4B, whereby contact holes  13  are formed.  
         [0044]    Next, as shown in FIG. 4C, the wiring trenches  28  are formed by etching.  
         [0045]    Next, as shown in FIG. 4D, a barrier metal film of a Ta film is formed by sputtering, and further a Cu film is formed by sputtering and electrolytic plating. Following this, the barrier metal film and the Cu film which are on the inter-layer insulation layer  3  are removed by the CMP method, and then the wiring layer  11  filling the wiring trenches  28  and the contact plugs  12  filling the contact holes  13  are formed simultaneously (dual damascene process). As a result, the multi-layer wiring  10  consisting of the contact plugs  12  and the wiring layer  11  is formed.  
         [0046]    Next, as shown in FIG. 4E, the steps 7 through 10 according to the first preferred embodiment described above (FIGS.  2 G- 2 J) are executed after forming the insulation layer  2  of silicon oxide for example, thereby completing the semiconductor device  200 .  
         [0047]    As described above, the SOI transistor  20  is formed on the multi-layer wiring  10  as required by the method of producing the semiconductor device  200  according to the second preferred embodiment, and therefore, it is possible to easily form multi-layer wiring structure of high minuteness and integration. Use of the dual damascene process in particular enables to simplify the producing steps.  
         [0048]    Third Preferred Embodiment  
         [0049]    [0049]FIG. 5 shows a semiconductor device according to a third preferred embodiment, indicated in its entirety by  300 , having multi-layer wiring structure. In FIG. 5, the same reference numerals as those used in FIG. 1 denote identical or corresponding portions.  
         [0050]    The semiconductor device  300  further includes multi-layer wirings  30  and  40  disposed in a lower layer portion of the semiconductor device  200  described earlier.  
         [0051]    A method of producing the semiconductor device  300  according to the third preferred embodiment will now be described with reference to FIGS.  6 A- 6 H. The steps shown in FIGS.  6 A- 6 D are similar to the steps shown in FIGS.  4 A- 4 D which represents the second preferred embodiment.  
         [0052]    Following these steps, as shown in FIG. 6E, a second inter-layer insulation layer  33  of silicon oxide for example is deposited on the inter-layer insulation layer  3  where the multi-layer wiring  10  is formed.  
         [0053]    Next, as shown in FIG. 6F, by the same dual damascene process as that at the step of forming the multi-layer wiring  10 , the multi-layer wiring  30  is formed in the second inter-layer insulation layer  33 .  
         [0054]    A third inter-layer insulation layer  43  of silicon oxide for example is then deposited on the second inter-layer insulation layer  33 . Following this, by the same dual damascene process as that at the step of forming the multi-layer wiring  30 , the multi-layer wiring  40  are formed in the third inter-layer insulation layer  43 .  
         [0055]    The insulation layer  2  of silicon oxide for example is further deposited on the third inter-layer insulation layer  43 .  
         [0056]    Next, the steps 7 through 10 according to the first preferred embodiment described above (FIGS.  2 G- 2 J) are executed, whereby the semiconductor device  300  is completed.  
         [0057]    Since the SOI transistor  20  is formed after forming the multi-layer wiring structures  10 ,  30  and  40  in the method of producing the semiconductor device  300  according to the third preferred embodiment, the multi-layer wiring structure can be fabricated while the underlying elements are flat. This allows to easily form even multi-layer wiring of a micro-fabricated structure. Particularly since the multi-layer wiring structures are formed by the dual damascene process promising high planarization on its surface, it is possible to stack minute multi-layer wiring one atop the other.  
         [0058]    Although the foregoing has described the third preferred embodiment in relation to an example wherein the dual damascene process is used, the single damascene process may be used as that according to the first preferred embodiment.  
         [0059]    Fourth Preferred Embodiment  
         [0060]    [0060]FIG. 7 shows a semiconductor device according to a fourth preferred embodiment, indicated in its entirety by  400 , having multi-layer wiring structure. In FIG. 7, the same reference numerals as those used in FIG. 1 denote identical or corresponding portions.  
         [0061]    In the semiconductor device  400 , the multi-layer wiring  10  is disposed below the SOI transistor  20 , while a multi-layer wiring  50  is disposed above the SOI transistor  20 .  
         [0062]    With respect to use of such a semiconductor device  400 , the flexibility of wiring is more improved than the case that the multi-layer wiring is formed only above or below the SOI transistor  20 . And eventually it is suitable for integration of the semiconductor device  400 .  
         [0063]    A method of producing the semiconductor device  400  according to the fourth preferred embodiment will now be described with reference to FIGS.  8 A- 8 C.  
         [0064]    First, as shown in FIG. 8A, through steps similar to those used in the second preferred embodiment, the SOI transistor  20  is formed on the inter-layer insulation layer  3  in which the multi-layer wiring  10  is formed.  
         [0065]    Next, as shown in FIG. 8B, a fourth inter-layer insulation layer  53  of silicon oxide for example is deposited.  
         [0066]    Then, as shown in FIG. 8C, the multi-layer wiring  50  is formed by the dual damascene process. Since the multi-layer wiring  50  is formed above the SOI transistor  20 , the surface of the fourth inter-layer insulation layer  53  is less planar than the surface of the inter-layer insulation layer  3 . Hence, the multi-layer wiring  50  can not be formed as minute as the multi-layer wiring  10  in some cases.  
         [0067]    Further, the single damascene process as that according to the first preferred embodiment may be applied to form the multi-layer wiring  10  and  50 .  
         [0068]    Thus, the method of producing the semiconductor device  400  according to the fourth preferred embodiment ensures that the multi-layer wiring below the SOI transistor  20  is minutely defined.  
         [0069]    In addition, use of such a structure improves the flexibility of wiring in the semiconductor device and accordingly enables to realize integration of the semiconductor device.  
         [0070]    Fifth Preferred Embodiment  
         [0071]    [0071]FIG. 11 shows a semiconductor device according to a fifth preferred embodiment, indicated in its entirety by  500 , having multi-layer wiring structure. In FIG. 11, the same reference symbols as those used in FIG. 1 denote identical or corresponding portions.  
         [0072]    In the semiconductor device  500 , as in the semiconductor device  300 , the multi-layer wirings  10 ,  30  and  40  are disposed below the SOI transistor  20 . Further, the multi-layer wiring  50  is disposed above the SOI transistor  20 .  
         [0073]    Use of such a structure further improves the flexibility of the semiconductor device. And eventually it is suitable for integration of the semiconductor device.  
         [0074]    After forming the multi-layer wirings  10 ,  30  and  40  through the producing steps according to the third preferred embodiment, the semiconductor device  500  is fabricated by forming the multi-layer wiring  50  above the SOI transistor  20  as in the fourth preferred embodiment.  
         [0075]    Wiring layers may be further stacked both below and above the SOI transistor  20 . In addition, any one of the damascene process and the dual damascene process may be used to form the multi-layer wirings.