Abstract:
An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator, and simulation method. 
     A simulator comprises: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model; and an interface board that connects the hardware section and software section.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a simulator and simulation method for verifying plural products with common hardware configuration and, more particularly, to a simulator in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator. 
         [0003]    2. Description of the Related Art 
         [0004]    In verifying the operation of a target product to be marketed, it is desirable to product the target product itself and verify it. However, in terms of production cost and product man-hour, the operation verification is often made using a simulator of the target product. In order to perform the verification of the operation of a target product at low cost, there is known a simulator constituted by a hardware emulator for emulating part of hardware configuration of the target product and a software simulator for simulating other hardware configuration of the target product. 
         [0005]    Further, there is known a hardware acceleration system that writes hardware logic to be simulated into an FPGA (Field Programmable Gate Array) so as to allow the hardware logic to be executed on the FPGA (refer to, e.g., Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2003-223476). 
         [0006]    However, in the simulator constituted by the hardware emulator and software simulator, the hardware emulator needs to be changed whenever the hardware configuration of a target product is changed, so that the hardware emulator cannot be reused and therefore effective low cost goal cannot be achieved. 
         [0007]    Further, also in the hardware acceleration system of Patent Document 1, all hardware logic in the hardware configuration thereof need to be written into the FPGA whenever the hardware configuration of a target product is changed. 
       SUMMARY OF THE INVENTION 
       [0008]    The present invention has been made to solve the above problems and an object thereof is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by hardware and other peripheral hardware is constituted by software simulator, and simulation method. 
         [0009]    To solve the above problems, according to an aspect of the present invention, there is provided a simulator including: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model; and an interface board that connects the hardware section and software section. 
         [0010]    In the above simulator, the interface board is connected via a PCI bus to the software section. 
         [0011]    Further, in the above simulator, the interface board is connected via a bus to the hardware section. 
         [0012]    Further, to solve the above problems, according to another aspect of the present invention, there is provided a simulation method performing simulation by connecting: a hardware section that includes a peripheral hardware configuration with a structure required for a CPU and OS to operate alone; and a software section that simulates the operation of peripheral hardware other than hardware constituting the hardware section as a peripheral hardware model via an interface board. 
         [0013]    Further, in the above simulation method, the interface board is connected via a PCI bus to the software section. 
         [0014]    Further, in the above simulation method, the interface board is connected via a bus to the hardware section. 
         [0015]    According to the present invention, by constituting peripheral hardware that can be reused by hardware and constituting other peripheral hardware by software simulator for verifying plural products with common hardware configuration, thereby performing simulation at low cost. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a view showing a configuration of a simulator in an embodiment of the present invention; 
           [0017]      FIG. 2  is a view showing assigned function of registers and correspondence between registers; and 
           [0018]      FIG. 3  is a view showing a processing sequence in the embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    An embodiment of the present invention will be described below with reference to the accompanying drawings. The present embodiment assumes a simulator that applies JPEG compression to uncompressed image data. 
         [0020]    A configuration diagram of the simulator according to the present embodiment is shown in  FIG. 1 . 
         [0021]    A simulator  5  includes a CPU board  10  (hardware section), a PCI board  20  serving as an interface board, and a PC  30  (PC: Personal Computer (software section)) serving as a peripheral hardware simulator for simulating the operation of peripheral hardware. 
         [0022]    The CPU board  10  is a board provided at least with a CPU on a printed-circuit board. The CPU board in the present embodiment includes, as a minimal configuration, a CPU  101 , a memory  102  (RAM, ROM), a timer controller  104  for performing time management, an interruption controller  103  for generating an interruption request signal to the CPU  101 , a PLL which is a phase synchronization circuit, and an RSET which is a reset circuit. 
         [0023]    The PCI board  1  is an interface board for connecting the CPU board and PC  30  so as to serve as an intermediate buffer therebetween. The PCI board  1  includes a dual-port memory  20  accessible from both the CPU board  10  and PC  30 . The dual-port memory  20  includes a register  201 , a control circuit  202 , a DMAC  203 , and a transmitting/receiving buffer  204 . 
         [0024]    The PC  30  includes a peripheral hardware model  301  (represented as “H/W model” in  FIG. 1 ) and configuration file  303  for applying JPEG compression to image data, the set (represented as “peripheral H/W A, peripheral H/W B, . . . ” in  FIG. 1 ) of which is simulated as peripheral hardware. The PC  30  further includes a device driver  302  that controls input/output of data of all the simulated hardware and operation of the PCI board  20 . 
         [0025]    The register  201  in the present embodiment functions both as an interruption event generating register and an interruption/WAIT event generating register. In the following, the operation performed in the case when the functions of the register are accessed will be described. 
         [0026]    When an access is made to an address within a predetermined address range to which the function as the interruption event generating register  201  is assigned, the PCI board  1  notifies the peripheral hardware model  301  of generation of an interruption. The initial value of a value set in the address range to which the function as the interruption event generating register is assigned is set to 0, which represents that no interruption is generated. 
         [0027]    When an access is made to an address within a predetermined address range to which the function as the interruption/WAIT event generating register of the register  201  is assigned, the PCI board  1  notifies the peripheral hardware model  301  of generation of an interruption. At the same time, the CPU  101  is put in a “WAIT” state until an instruction of the release of the WAIT mode is issued from the peripheral hardware model  301 . The initial value of a value set in the address range to which the function as the interruption/WAIT event generating register is assigned is set to 0, which represents that no interruption and no “WAIT” are generated. 
         [0028]    The function assignment of the register  201  for performing JPEG compression processing in the present embodiment is shown in  FIG. 2 . 
         [0029]    A profile data register, a transfer source address/size register, and transfer destination address/size register store configuration information for performing the JPEG compression processing, which is sent from the CPU  101  to the peripheral hardware model  301 . In the present embodiment, JPEG compression rate data is stored in the profile data register. 
         [0030]    The control register is a register for controlling JPEG compression processing such as starting conversion operation. An operation status register is a register for storing the processing state of the peripheral hardware model  301 , such as processing state during operation and conversion error. 
         [0031]    As shown in the “function assignment of register” of  FIG. 2 , in the present embodiment, the start address of the profile data register is “ 100 ”, and the start addresses of the transfer source address/size register and transfer destination address/size register are “ 104 ” and “ 108 ”, respectively. The start address of the control register is “ 10 C”, and that of the operation status register is “ 110 ”. 
         [0032]    Further, as shown in “correspondence between registers”, the interruption event generating register is assigned to “ 10 C” to “ 10 F”, and interruption/WAIT event generating register is assigned to “ 110 ” to “ 113 ”. As a result, when the control register (whose starting address is “ 10 C”) is accessed, an interruption event is generated for the peripheral hardware model  301 ; while when the operation status register (whose starting address is “ 110 ”) is accessed, an interruption event is generated for the peripheral hardware model  301 , as well as a WAIT event is generated for the CPU  101 . 
         [0033]    The JPEG compression processing in the present embodiment will next be described with reference to  FIG. 3 . 
         [0034]    First, the PCI board  1  previously loads information of the configuration file  303  into the control section  202  (step  51 ). The configuration file  303  stores the information shown in  FIG. 2 . 
         [0035]    The CPU board  10  sets profile data, transfer source address, and transfer destination address in the profile data register, transfer source address/size register, and transfer destination address/size register of the register  201  (step S 2 ). 
         [0036]    In order to cause the peripheral hardware model  301  to start the JPEG conversion, the CPU  101  sets a value for starting the JPEG conversion in the control register of the register  201  (step S 3 ). 
         [0037]    Since an access has been made from the CPU  101  to the control register assigned as the interruption event generating register, the PCI board  1  issues an interruption notification to the peripheral hardware model  301  via the device driver  302  (step S 4 ). 
         [0038]    Upon reception of the interruption notification, the peripheral hardware model  301  confirms the content set in the control register of the register  201 . When the data indicates a value for starting the JPEG conversion, the peripheral hardware model  301  reads out the profile data, transfer source address/size, and transfer destination address/size from the profile data register, transfer source address/size register, and transfer destination address/size register of the register  201  (step S 5 ). 
         [0039]    Thereafter, the peripheral hardware model  301  issues a DMA (Direct Memory Access) request to the DMAC (Direct Memory Access Controller)  203  of the PCI board  1 . Upon receiving the request, the DMAC  203  loads uncompressed image data from the memory  102  of the CPU board  10  via the transmitting/receiving buffer of the PCI board  1  into a memory on the PC  30  where the peripheral hardware model  301  performs the JPEG compression processing. 
         [0040]    The peripheral hardware model  301  then starts a compression operation and sets the previously assigned value in the operation status register of the register  201  (step S 6 ). 
         [0041]    As a value to be written in the operation status register, a value indicating whether or not the current processing needs to be synchronized with the CPU  101  is previously provided in addition to a value indicating the processing state (processing state during operation and conversion error, etc.) of the peripheral hardware model  301 . In step S 6 , a value indicating the current processing needs to be synchronized with the CPU  101  is assumed to be set. 
         [0042]    In order to read out the operation status, the CPU  101  accesses the operation status register of the register  201  (step S 7 ). 
         [0043]    Since an access has been made to the operation status register assigned to the interruption/WAIT event generating register and value indicating that synchronization is required has been set, the PCI board  1  issues an interruption notification to the peripheral hardware model  301  via the device driver  302  and causes the CPU  101  to enter the WAIT state (step S 8 ). 
         [0044]    After the processing that needs to be synchronized with the CPU  101  has been completed, the peripheral hardware model  301  writes the operation status (value indicating that synchronization with the CPU  101  is not required) in the operation status register and issues a WAIT release command (step S 9 ). 
         [0045]    Upon reception of the WAIT release command, the PCI board  1  performs the release of the WAIT state for the CPU  101  (step S 10 ). The CPU  101  releases the WAIT sate based on the WAIT release command issued from the peripheral hardware model  301  and starts reading out the operation status that the peripheral hardware model  301  has written. 
         [0046]    The release of the WAIT state of the CPU  101  by the PCI board  1  may be performed as follows: a WAIT release register is additionally provided in the register  201 , and the WAIT release command issued from the peripheral hardware model  301  accesses the WAIT release register. 
         [0047]    After completion of the JPEG compression operation, the peripheral hardware model  301  reads out the abovementioned transfer destination address/size and issues a DMA request to the DMAC  203  of the PCI board  1 . Upon reception of the DMA request, the DMAC  203  loads JPEG compressed image data from a memory on the PC  30  where the peripheral hardware model  301  performs the JPEG compression processing via the transmitting/receiving buffer of the PCI board  1  into the memory  102  of the CPU board  10 . 
         [0048]    The peripheral hardware model  301  writes operation status (value indicating that synchronization with the CPU  101  is not required) indicating that operation has normally been completed in the operation status register of the register  201  and issues an interruption request command to the CPU  101  (step S 11 ). 
         [0049]    A configuration may be adopted in which the memory area of the dual-port memory  20  is divided into a plurality of areas for each peripheral hardware (peripheral H/N A, peripheral H/A B, . . . ) operating on the PC  30 , and the WAIT instruction for the CPU  101  and interruption notification for the peripheral hardware model are issued in units of each divided area. With this configuration, it is possible to establish synchronization between a plurality of peripheral hardware and CPU  101 , thereby enabling a target product including a plurality of peripheral hardware to be verified in a comprehensive manner. 
         [0050]    As described above, by allowing the hardware and hardware model to cooperate with each other through an interface, in a simulator for verifying plural products with common hardware configuration, peripheral hardware that can be reused can be constituted by hardware and other peripheral hardware can be constituted by software simulation, whereby cost and labor hour savings can be realized.