Abstract:
A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface.

Description:
[0001]    This invention was made with Government support under Contract No.: H98230-08-C-1468 awarded by Department of Defense. The Government has certain rights in this invention. 
     
    
     BACKGROUND 
       [0002]    The present invention relates generally to volumetric integrated circuits and manufacturing methods therefore and, more specifically, to volumetric integrated circuits including hermetically passivated metallization. 
         [0003]    Volumetric integrated circuit assembly processes involves the turning of chips sideways and the bonding of the chips together with a high-temperature adhesive in controlled-spacing chip-chip gaps. Further processing includes the metallization of the new top and bottom surfaces of the resulting assembly and the joining of a top chip and a bottom substrate (or package or circuit board) to the resulting assembly at the top and bottom surface metallization by way of flip-chip joining processes (e.g., with micro-solder bumps). Recently, however, it has been found that the metallizations of the new top and bottom surfaces require hermetic passivation, which leads to passivation cracking as the passivation crosses over the chip-chip gaps, and gap crossing wiring that presents thermal mismatch issues with the adhesive and causes adhesive outgassing. 
       SUMMARY 
       [0004]    According to one embodiment of the present invention, a volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface. 
         [0005]    According to another embodiment of the present invention, a volumetric integrated circuit manufacturing method is provided and includes forming a plurality of elongate chips, each comprising opposite major faces, two pairs of opposite minor faces and a wiring layer disposed on one of the major faces, assembling the plurality of elongate chips into a slab element such that each elongate chip is disposed with at least one major face adhered to a major face of an adjacent elongate chip and such that the slab element comprises opposite major faces, exposing a wiring layer between adjacent elongate chips at one of the major faces of the slab element, metallizing a surface of the one of the major faces of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface. 
         [0006]    According to yet another embodiment of the present invention, a volumetric integrated circuit is provided and includes a plurality of elongate chips, each comprising opposite major faces, two pairs of opposite minor faces and a wiring layer disposed on one of the major faces and each being disposed with at least one major face adhered to a major face of an adjacent elongate chip and metallization of at least one of the opposite minor faces of at least one of the two pairs of opposite minor faces of each elongate chip, the metallization comprising a metal layer in contact with the corresponding wiring layer and hermetic passivation at least partially surrounding the metal layer. 
         [0007]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects are described in detail herein and are considered a part of the claimed invention. For a better understanding, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0008]    The forgoing and other features, and advantages of the embodiments are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0009]      FIG. 1  is a perspective view of a elongate chip; 
           [0010]      FIG. 2  is a perspective view of a slab element formed of a plurality of elongate chips; 
           [0011]      FIG. 3  is a side view of an initial stage of a formation of hermetically passivated metallization in accordance with embodiments; 
           [0012]      FIG. 4  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with embodiments; 
           [0013]      FIG. 5  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with embodiments; 
           [0014]      FIG. 6  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with embodiments 
           [0015]      FIG. 7  is a side view of a final stage of a formation of hermetically passivated metallization in accordance with embodiments; 
           [0016]      FIG. 8  is a side view of an initial stage of a formation of hermetically passivated metallization in accordance with alternative embodiments; 
           [0017]      FIG. 9  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with alternative embodiments; 
           [0018]      FIG. 10  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with alternative embodiments; 
           [0019]      FIG. 11  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with alternative embodiments; 
           [0020]      FIG. 12  is a side view of an intermediate stage of a formation of hermetically passivated metallization in accordance with alternative embodiments; 
           [0021]      FIG. 13  is a side view of a final stage of a formation of hermetically passivated metallization in accordance with alternative embodiments; 
           [0022]      FIG. 14  is a side view of further processing of hermetically passivated metallization; 
           [0023]      FIG. 15  is a side view of further processing of hermetically passivated metallization; 
           [0024]      FIG. 16  is a side view of further processing of hermetically passivated metallization; and 
           [0025]      FIG. 17  is a side view of further processing of hermetically passivated metallization. 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    The disclosure provided below relates to volumetric or multi-dimensional integrated circuit manufacturing processes. In general, volumetric integrated circuits are formed from a plurality of elongate chips that may be known good die (KGD) application specific integrated circuits (ASICs), which are originally provided on a wafer. The wafer may include several dozen or several hundred of such elongate chips that are diced and formed into a slab of elongate chips. 
         [0027]    With reference to  FIG. 1 , each elongate chip  1  may be a long and narrow integrated circuit and includes a substrate body  2  having two opposite major faces  3 , a first pair of opposite minor faces  4 , which correspond to their diced edges, and a second pair of opposite minor faces  5 . The elongate chips  1  may be rectangular such that the major faces  3  are rectangular and the minor faces  4  are longer than the minor faces  5 . Each elongate chip  1  further includes a passivated wiring layer  6  operably disposed on one of the major faces  3 . The wiring layer  6  includes multiple back end of line (BEOL) wiring levels (or features) in a central portion of the major face  3  as well as interconnections  7  that extend from the central portion to at least an edge portion  8  of the major face  3 , which is defined along the longer minor faces  4 . Each elongate chip  1  may further include crack-stop features  9 , which may be disposed at the edge portion  8  below the interconnections  7 . The crack-stop features  9  prevent moisture ingress and crack propagation of the substrate body  2  from the edge portion  8  toward the central portion. 
         [0028]    With reference to  FIGS. 1 and 2 , the elongate chips  1  are assembled into a slab  10  of elongate chips  1 . In accordance with embodiments, sixty-four elongate chips  1  may be assembled into the slab  10 . Within the slab  10 , each of the interior facing major faces  3  of each bookending elongate chip  1  is adhered to an opposite major face  3  of an adjacent elongate chip  1 . That is, the elongate chips  1  are stacked with one another horizontally. For the interior elongate chips  1 , each major face  3  is adhered to an opposite major face  3 . The adhesive (e.g. polymer) is cured and the slab  10  is framed to form a slab element  13 , which is representative of a full stack of elongate chips  1  and framing. 
         [0029]    The slab element  13  has a top surface  14 , which is formed of the longer minor faces  4  of each of the elongate chips  1  and the adhesive, and a bottom surface  15 , which is formed of the opposite minor faces  4  of each of the elongate chips  1  and the adhesive. A top chip  16  and a bottom substrate (or package or circuit board)  17  are each operably coupled to the top surface  14  and the bottom surface  15  by way of controlled collapse chip connection (C4) grids  18  and LGAs  19  disposed between the minor faces  4  and the top chip  16  and the bottom chip  17  and hermetically passivated metallization to form a volumetric integrated circuit  130 . 
         [0030]    The hermetically passivated metallization is formed by way of the processes described below with reference to  FIGS. 3-7  or  FIGS. 8-13  and, additionally,  FIGS. 14-17 . 
         [0031]    With reference to  FIGS. 3-7 , an initial stage in the formation of the hermetically passivated metallization is that the slab  10  or slab element  13  (hereinafter referred to as the “slab element  13 ”) of  FIG. 2  is placed at rest on its bottom surface  15  so that the top surface  14  faces upwardly. As shown in  FIG. 3 , the top surface  14  is ground and polished so that the top surface  14  is substantially planarized with the wiring layers  6  exposed (only 1 is shown for clarity and brevity). The ground and polished top surface  14  is passivated to form a top surface passivation layer  20  as shown in  FIG. 4 . The top surface passivation layer  20  may be formed by plasma-enhanced chemical vapor deposition (PECVD) and may include interleaved silicon nitride and silicon oxide layers. A lower-most layer of the top surface passivation layer  20  may be a silicon nitride layer that is adjacent to the ground and polished top surface  14 . 
         [0032]    As shown in  FIG. 5 , a lithographic process is executed to generate a laser-written vertical corner contact via  21 , which is patterned and etched through the top surface passivation layer  20  at and around the wiring layers  6 . This laser-written vertical corner contact via  21  extends laterally from the crack-stop features  9 , across the wiring layer  6  and to the adhesive  11  between adjacent elongate chips  1 . Exposed surfaces of the laser-written vertical corner contact via  21  are then cleaned by a reactive ion etch (RIE) process, a stripping process and/or an application of a dilute acid (DHF). 
         [0033]    As shown in  FIG. 6 , a top surface metallization layer  22  is formed at and around the cleaned laser-written vertical corner contact via  21  to define a corner contact region. In accordance with various embodiments, the top surface metallization layer  22  may be formed by plasma vapor deposition (PVD) of argon along with one or more of titanium, titanium nitride, aluminum, copper or aluminum-copper alloy and by additional lithographic or etching processes. The top surface metallization layer  22  may be substantially uniformly thick so that a shape of a top surface of the top surface metallization layer  22  is reflective of a shape of the laser-written vertical corner contact via  21 . 
         [0034]    As shown in  FIG. 7 , a final stage in the process includes the formation of an uppermost passivation layer  23  over the top surface passivation layer  20  and portions of the top surface metallization layer  22 . As with the top surface passivation layer  20 , the uppermost passivation layer  23  may be formed by PECVD and may include interleaved silicon nitride and silicon oxide layers. An upper-most layer of the uppermost passivation layer  23  may be a silicon nitride layer such that silicon nitride layers bookend the top surface and uppermost passivation layers  20  and  23 . Following formation of the uppermost passivation layer  23 , the uppermost passivation layer  23  may be subject to lithographic (e.g., photosensitive polyimide (PSPI) deposition/exposure/curing) and etching processes for cleaning purposes. The uppermost passivation layer  23  may be formed to define an uppermost via  24  that is electrically communicative with the corresponding C4 grid  18 . 
         [0035]    With reference to  FIGS. 8-13 , an initial stage in the formation of the hermetically passivated metallization is again that the slab element  13  of  FIG. 2  is placed at rest on the bottom surface  15  so that the top surface  14  faces upwardly. As shown in  FIG. 8 , the top surface  14  is ground and polished so that the top surface  14  is substantially planarized with the wiring layers  6  exposed (only 1 is shown for clarity and brevity). The ground and polished top surface  14  is uniformly etched by way of RIE and DHF processes to expose a top portion  30  of each of the wiring layers  6 , as shown in  FIG. 9 . The ground, polished and etched top surface  14  and the top portion  30  of each of the wiring layers  6  are then passivated to form a top surface passivation layer  31  as shown in  FIG. 10 . The top surface passivation layer  31  may be formed by plasma-enhanced chemical vapor deposition (PECVD) and may include interleaved silicon nitride and silicon oxide layers. A lower-most layer of the top surface passivation layer  31  may be a silicon nitride layer that is adjacent to the ground, polished and etched top surface  14 . 
         [0036]    As shown in  FIG. 11 , the top surface passivation layer  31  is subjected to chemical mechanical polishing processes to re-expose the top portion  30  of each of the wiring layers  6  and cleaned. At this point, as shown in  FIG. 12 , a top surface metallization layer  32  is formed at and around the re-exposed top portions  30 . In accordance with various embodiments, the top surface metallization layer  32  may be formed by plasma vapor deposition (PVD) of argon along with one or more of titanium, titanium nitride, aluminum, copper or aluminum-copper alloy and by additional lithographic or etching processes. The top surface metallization layer  32  may be substantially uniformly thick so that a shape of a top surface of the top surface metallization layer  32  is reflective of a shape of the top surface passivation layer  31  and the top portions  30 . 
         [0037]    As shown in  FIG. 13 , a final stage in the process includes the formation of an uppermost passivation layer  33  over the top surface passivation layer  31  and portions of the top surface metallization layer  32 . As with the top surface passivation layer  31 , the uppermost passivation layer  33  may be formed by PECVD and may include interleaved silicon nitride and silicon oxide layers. An upper-most layer of the uppermost passivation layer  33  may be a silicon nitride layer such that silicon nitride layers bookend the top surface and uppermost passivation layers  31  and  33 . Following formation of the uppermost passivation layer  33 , the uppermost passivation layer  33  may be subject to lithographic (e.g., photosensitive polyimide (PSPI) deposition/exposure/curing) and etching processes for cleaning purposes. The uppermost passivation layer  33  may be formed to define an uppermost via  34  that is electrically communicative with the corresponding C4 grid  18 . 
         [0038]    With reference to  FIGS. 14-17 , further processing of hermetically passivated metallization may be conducted and may be equally applicable to the embodiments of  FIGS. 3-7  or  FIGS. 8-13 . For purposes of clarity and brevity, however,  FIGS. 14-17  are provided and relate to embodiments of the further processing that are applied to the embodiments of  FIGS. 3-7 . 
         [0039]    With reference to  FIG. 14 , each elongate chip  1  in the slab element  13  of  FIG. 2  includes a silicon substrate layer  40 , a BEOL stack  41  and a wiring layer  42  disposed within the BEOL stack  41 . An additional layer of adhesive  43 , such as an organic thermoset material, is disposed between the BEOL stack  41  and the silicon substrate layer  40  of adjacent elongate chips  1 . The uppermost passivation layer  23  and the top surface passivation layer  20  are provided along the top surface  14  along with the top surface metallization layer  22 , which is disposed in electrical contact with the wiring layer  42  to form a corner contact that is planarized and hermetically sealed by the dielectric materials of the uppermost passivation layer  23  and the top surface passivation layer  20 . The top surface metallization layer  22  is further electrically connected to ball limiting metallurgy (BLM) and a C4 connection of the corresponding grid  18 . 
         [0040]    As shown in  FIG. 14 , the uppermost passivation layer  23  and the top surface passivation layer  20  may be formed to extend across and over the layer of adhesive  43 . In this case, the top surface metallization layer  22  terminates at the edge of the BEOL stack  41  such that no portion of the top surface metallization layer  22  extends over the layer of adhesive  43 . 
         [0041]    With reference to  FIGS. 15-17 , further processes toward additional embodiments exist. These include the definition and formation of ventilation and stress/strain relief slots  50  through the uppermost passivation layer  23  and the top surface passivation layer  20  over the layer of adhesive  43 , as shown in  FIG. 15 , the disposition of a cap  60  in each of the ventilation and stress/strain relief slots  50 , as shown in  FIG. 16 , and the formation of a cap passivation layer  70  over each of the caps  60 . The caps  60  may be formed of metal or metallic alloys and are disposed to add mechanical support to the uppermost passivation layer  23  and the top surface passivation layer  20 . 
         [0042]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0043]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments. The embodiments were chosen and described in order to best explain principles and practical application, and to enable others of ordinary skill in the art to understand the embodiments for various embodiments with various modifications as are suited to the particular use contemplated. 
         [0044]    While the embodiments have been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the embodiments first described.