Abstract:
Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:  
     A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and  
     B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to the field of semiconductor device fabrication. In one aspect, the invention relates to the manufacture of a wordline stack while in another aspect, the invention relates to forming an insulating layer on the top surface of the stack. In yet another aspect, the invention relates to depositing the insulating layer on the wordline stack through the use of sputtering technology.  
         BACKGROUND OF THE INVENTION  
         [0002]    Dynamic random access memory (DRAM) devices comprise, among other things, a large plurality of wordline stacks, also known as gate electrode stacks. The function of these stacks is to store a charge and when used in combination with a bit or digit line, provide an “address” for a discrete memory cell. The typical wordline stack is a layered composite of various materials, the top layer of which is typically a silicate glass, e.g., borophosphosilicate glass (BPSG).  
           [0003]    The preparation of a DRAM device involves one or more heat annealing steps in which the temperature is such that the dopants, e.g., boron, phosphorus, arsenic, etc., of a doped material, e.g., BPSG, will migrate (or out-gas) from the doped material into the environment (i.e., into the chamber in which the heat annealing step is conducted) and into one or more adjacent layers or other components, e.g., the substrate, of the device. Since the purpose of a dopant is to enhance the conductivity of a material, migration of a dopant into a dielectric material will decrease the insulating properties of that material. If enough dopant migrates into a dielectric material, then the insulating properties of the material will be reduced to the point that a short circuit can develop between the conductive layers separated by the dielectric layer. This, of course, means that a wordline stack can lose its charge inadvertently and this, in turn, can result in a malfunction of the memory device.  
           [0004]    To address this problem, a relatively thick, e.g., 150-300 angstroms, layer of an insulating material (also a dielectric and also known as a liner) is usually deposited adjacent to a layer of doped material. Tetraethylorthosilicate (TEOS) is a commonly used liner for this purpose. Achieving a relatively thick layer of this insulating material using conventional chemical vapor deposition (CVD) techniques is not difficult for top-level stack surfaces, but it can be problematic for the surfaces between two stacks. If the aspect ratio, i.e., the height of the stacks (the height of all of the stacks is, for all intent and purpose, essentially the same at the time a blanketing layer of insulating material is deposited) over the distance between the stacks, is relatively low, e.g., less than 3, then conventional CVD techniques will deposit a layer of insulating material of substantially the same thickness between two stacks as is deposited on the top of the stacks. However, as this aspect ratio increases, i.e., the distance between the stacks narrows, the thickness of the insulating layer deposited by conventional CVD between two stacks decreases relative to the thickness of the insulating surface deposited on the top layer of the stacks. At some point, insufficient insulating material is deposited between the two stacks to provide an effective block against the migration of do pants from a material overlying the insulating layer to a material underlying the insulating layer.  
           [0005]    As the density of wordline stacks increase on a substrate, the space between individual stacks will inevitably decrease. As this space decreases, the need for cleaner production methods increases, including the need to block the migration of dopants from a doped material to a dielectric material during the heat annealing steps of the memory device. This increases the need for adequate deposition of liners between wordline stacks during the preparation of semiconductor memory devices and other integrated circuits.  
         SUMMARY OF TILE INVENTION  
         [0006]    According to this invention, a liner that is an effective block against the migration of a dopant from a doped material to a dielectric material is positioned between the two materials by sputtering. In one embodiment of this invention, an insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:  
           [0007]    A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and  
           [0008]    B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.  
           [0009]    In another embodiment of this invention, an insulating material is deposited onto a gate dielectric surface separating two wordline stacks, each wordline stack having a top surface, the insulating material deposited as a layer onto the dielectric surface at a thickness that is substantially the same as the thickness of the insulating layer that is deposited as a layer onto the top of the stacks, the method comprising the steps of:  
           [0010]    A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and  
           [0011]    B. Depositing by sputtering the insulating material as a layer onto the top of the two stacks and the open surface of the gate dielectric separating the two wordline stacks.  
           [0012]    In still another embodiment of this invention, an insulating material is deposited onto a gate dielectric surface separating two wordline stacks, each wordline stack having a top surface and at least one side wall, the insulating material deposited as a layer onto the dielectric surface (i) at a thickness that is substantially the same as the thickness of the insulating layer that is deposited as a layer onto the top of the stacks, and (ii) without any substantial deposition of the insulating material onto the side walls of the stacks, the method comprising the steps of:  
           [0013]    A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and  
           [0014]    B. Depositing by sputtering the insulating layer onto the top of the two stacks and the open surface of the gate dielectric separating the two wordline stacks without any substantial deposition of the insulating material onto the side walls of the stacks. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. In the figures like numerals are employed to designate like parts throughout the same.  
         [0016]    [0016]FIG. 1A is a diagrammatic cross-sectional view of a semiconductor wafer fragment bearing two adjacent but separated wordline stacks (prior art).  
         [0017]    [0017]FIG. 1B is the diagrammatic cross-sectional view of the semiconductor wafer fragment of FIG. 1 but covered with a continuous TEOS layer deposited by LPCVD (prior art).  
         [0018]    [0018]FIG. 1C is the diagrammatic cross-sectional view of a semiconductor wafer fragment of FIG. 1B but covered with a continuous BPSG layer (prior art).  
         [0019]    [0019]FIG. 2A is the diagrammatic cross-sectional view of the semiconductor wafer fragment of FIG. 1A but covered with a discontinuous silicon dioxide layer deposited by sputtering, according to an embodiment of the method of the invention.  
         [0020]    [0020]FIG. 2B is the diagrammatic cross-sectional view of the semiconductor wafer fragment of FIG. 2A but covered with a continuous BPSG layer.  
         [0021]    [0021]FIG. 2C is the diagrammatic cross-sectional view of the semiconductor wafer fragment of FIG. 2B after a select portion of the BPSG and silicon dioxide layers are removed by an anisotropic etch. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0022]    [0022]FIG. 1A is a diagrammatic cross-sectional view of a semiconductor wafer fragment  10  bearing two adjacent but separated wordline stacks  11   a  and  11   b . Semiconductor substrate  12  typically comprises monocrystalline silicon with regions  13   a - d  sufficiently doped with boron, phosphorus, arsenic or other dopant to operate efficiently as sources and drains for the stacks. Each stack is separated from substrate  12  by gate dielectric  14 , which is typically formed by oxidation of substrate  12 . Gate dielectric  14  covers essentially all of substrate  12 , and is thus common or shared by both wordline stacks.  
         [0023]    The wordline stacks  11   a ,  11   b  comprise polysilicon layers  15   a - b , conductive barrier layers  16   a - b , metal layers  17   a - b , silicon dioxide layers  18   a - b , nitride cap layers  19   a - b , and spacer (i.e., side wall) nitride layers  20   a - d , respectively. Barrier layers  16   a - b  are essentially impermeable to silicon and metal atoms under manufacturing and operating conditions, and can include tungsten or titanium nitride. Metal layers  17   a - b  are typically a metal or alloy of aluminum, copper, tungsten, titanium, platinum, palladium, cobalt, molybdenum, nickel, rhodium and/or iridium. The cap and spacer nitride layers typically comprise silicon nitride.  
         [0024]    The wordline stacks are constructed using conventional techniques. Typically, the materials for the polysilicon layer, the barrier layer, the metal layer, the silicon dioxide and nitride layers are alternatively deposited as blanket layers and etched to form the stacks. The wordline stacks have a height h and the open surface on the gate dielectric between the stacks has a width w, the height h and width w defining an aspect ratio of h/w of at least about 2, preferably at least about 2.5 and more preferably at least about 3. Since nitride spacers are usually components of a wordline stack, width w is usually measured from the external surface of one nitride spacer to the external surface of an opposing nitride spacer, e.g., from the external surface of  20   b  to the external surface of  20   c . Height h is usually measured from the exposed surface of the gate dielectric to the exposed surface of the top layer of a stack, e.g., from the exposed surface of gate dielectric  14  to the top surface of nitride cap layer  19   a  or  19   b.    
         [0025]    Word line stacks  11   a  and  11   b  are designed as components for a semiconductor memory device and in this regard, are ultimately coated with a doped oxide insulator layer, typically BPSG. Because boron and phosphorus will migrate from the BPSG layer to the layers underlying it (e.g., dielectric gate  14  and/or substrate  12 ) during the heat annealing steps of the memory device manufacture, an insulation layer, typically oxide formed using TEOS, is placed between the doped oxide layer and the underlying layers. This conventional practice is illustrated in FIGS. 1B and 1C.  
         [0026]    TEOS insulation layer or liner  21  is typically deposited upon the exposed surfaces of the semiconductor wafer of FIG. 1A such that it overlays nitride layers  19   a - b , nitride spacers  20   a - d  and dielectric gate  14 . The TEOS is typically deposited by low pressure chemical vapor deposition (LPCVD) but due to the nature of LPCVD deposition and the presence of the spacer nitride on the stack side walls, the amount of TEOS deposited on the surface of dielectric gate  14  between the stacks is less than the amount of TEOS deposited upon the exposed surfaces of nitride layers  19   a - b . Referring to FIG. 1B, in terms of layer thickness, thickness t 2 &lt;thickness t 1 , typically much less. If the thickness of the TEOS layer over the dielectric gate is inadequate, e.g., less than 150 angstroms, then the TEOS layer is likely to allow some migration of dopant from the BPSG layer into the dielectric gate layer.  
         [0027]    Referring to FIG. 2A, insulating layers  23   a - e  are deposited onto the exposed surfaces of dielectric gate  14  and nitride layers  19   a - b  by any conventional sputtering technique, e.g., high density plasma (HDP) or collimated. These and other sputtering techniques (also known as physical vapor deposition) are well known in the art. Wolf and Tauber,  Silicon Processing for the VLSI Era , Vol. 1, Chpt. 11, (Lattice Press 2000); Zant, Microchip Fabrication, pp.411-16 (McGraw-Hill 2000); and Aronson, “Fundamentals of Sputtering”,  Microelectronics Manufacturing and Testing , January 1987. An exemplary conventional sputtering process is the sputtering of aluminum for metal interconnects.  
         [0028]    Sputtering allows for the deposition of insulating layers  23   a - e  with little, if any, deposition of insulating material on the sidewalls of the stacks. This, in turn, allows for the deposition of a layer with a more uniform thickness across the exposed surfaces of the wordline stacks and their supporting dielectric gate. As shown in FIG. 2A, thickness t 4  is substantially equal to thickness t 3 , i.e., t 4 =t 3 . Of course, the higher the aspect ratio of the space between the stacks, the more t 4  is likely to be less than t 3 . Preferably, the aspect ratio of space between the stacks is less than about 4, more preferably less than about 3.75, and most preferably less than about 3.5.  
         [0029]    In one preferred embodiment of this invention, insulating layers  23   a - e  are one of silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ). Other insulators of interest include boron nitride (BN), tungsten nitride (WN), and aluminum oxide (Al 2 O 3 ). The temperature during formation of the insulting layer is sufficiently low so that little or none of the barrier and metal layers of the wordline stacks is converted to an oxide. For example, if the barrier layer comprises tungsten nitride and the metal layer comprises tungsten, then the insulating layer can be formed at a temperature in range of about 30 to about 650C.  
         [0030]    After insulating layers  23   a - e  are applied, a doped oxide insulating layer  22 , e.g., BPSG, is applied to all the exposed surfaces of wafer  10  (FIG. 2B), and then the wafer is subjected to a standard photolithographic mask and etch process to remove insulating layers  23   a - c -e, doped oxide insulating layer  22  (except from the surface of nitride layers  19   a - b  (FIG. 2C)), and the portion of gate dielectric  14  between stacks  11   a  and  11   b . Subsequently, a contact (not shown) is made on substrate  12  at surface  12   a  (i.e., the surface between stacks  11   a  and  11   b ).  
         [0031]    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents. Other embodiments of this invention are within the scope of the following claims.