Abstract:
A filter circuit is disclosed which comprises a differential amplifier and a switch-capacitor circuit. The invention attains the goals of reducing the power consumption and the circuit size by sharing an amplifier with other related circuits to reduce the number of amplifiers.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the invention 
         [0002]    The invention relates to a filter circuit, and more particularly, to a filter circuit that shares a differential amplifier. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  is a block diagram of a receiver for a conventional network transceiver. The receiver  100  includes a front-end receiver  110 , a feedforward equalizer  120 , a noise canceller  130 , a timing recovery device  140  and a decoder  150 . The front-end receiver  110  may include an analog auto-gain controller  111 , a low-pass filter  112 , a sample-and-hold circuit  113 , an inverse partial response (IPR) filter  114  and an analog to digital converter (ADC) 115 . 
         [0005]    The analog auto-gain controller  111  receives an input signal sent by a transmitter of a remote transceiver and then adjusts the amplitude of the input signal to fit the pre-defined operating range of the low-pass filter  112 . The low-pass filter  112  receives the output of the analog auto-gain controller  111  and then attenuates the high-frequency noise. The sample-and-hold circuit  113  subsequently samples and holds the output of the low-pass filter. Then, the IPR filter  114  compensates inter-symbol interference introduced by the transmitter of the remote transceiver in order to reduce a peak-to-average ratio of the signal to be fed into the ADC  115 . Meanwhile, the IPR filter  114  reduces the magnitude of the quantized noise and increases the signal-to-noise ratio for further signal processing. The IPR filter  114  is an infinite impulse response filter with a transfer function H(z)=1/(1+Kz −1 ), where K is a positive real number that is less than one. The ADC  115  coupled to the IPR filter  114  converts the output of the IPR filter  114  into a digital signal by analog to digital conversion. 
         [0006]    It is common to have two fully-differential amplifiers respectively installed in both the IPR filter  114  and the ADC  115  of the conventional receiver  100 . Nevertheless, the excessive power consumption and ever-increasing manufacturing cost are inducing a trend of providing a low-price, high-efficiency, power-saving and compact circuit design for the next generation of chip industry. Hence, a need exists for a new filter that reduces the number of amplifiers so as to save power consumption and die area as well. 
       SUMMARY OF THE INVENTION 
       [0007]    In view of the above-mentioned problems, an object of the invention is to provide a filter circuit in order to reduce the number of amplifiers by sharing a common amplifier with other related circuits, thereby saving the power consumption and reducing the circuit size. 
         [0008]    To achieve the above-mentioned object, the filter circuit capable of sharing a differential amplifier comprises: a differential amplifier for receiving an input signal and generating an output signal; and, a switch-capacitor circuit for storing charges generated by both the input signal and the output signal and coupling with the differential amplifier during at least one of a plurality of state periods; wherein the input signal and the output signal generate the same transfer function during each of the plurality of state periods. Wherein, the filter is an IPR filter and the differential amplifier is a fully-differential amplifier. 
         [0009]    Another objective of the invention is to provide a method of filtering, applied to a circuit that shares a differential amplifier, comprising: receiving an input signal and generating an output signal by using a differential amplifier; storing charges generated by the input signal and the output signal by using a switch-capacitor circuit; and, coupling the switch-capacitor circuit with the differential amplifier during at least one of a plurality of state periods; wherein the input signal and the output signal generate the same transfer function during each of the plurality of state periods. 
         [0010]    Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein: 
           [0012]      FIG. 1  is a block diagram of a receiver for a conventional network transceiver. 
           [0013]      FIG. 2  is a block diagram of an IPR filter according to an embodiment of the invention. 
           [0014]      FIG. 3  is a diagram showing the relationship between system clock cycles and four states. 
           [0015]      FIG. 4A  is a circuit diagram of the IPR filter in state one according to the embodiment of the invention. 
           [0016]      FIG. 4B  is a circuit diagram of the IPR filter in state two according to the embodiment of the invention. 
           [0017]      FIG. 4C  is a circuit diagram of the IPR filter in state three according to the embodiment of the invention. 
           [0018]      FIG. 4D  is a circuit diagram of the IPR filter in state four according to the embodiment of the invention. 
           [0019]      FIG. 4E  is a circuit diagram of the IPR filter that returns to state one according to the embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The filter circuit of the invention and method thereof will be described with reference to the accompanying drawings. 
         [0021]      FIG. 2  is a block diagram of an IPR filter illustrated according to an embodiment of the invention. According to the embodiment, a switch-capacitor circuit structure is provided to share a common amplifier. An IPR filter  200  of the invention receives two input signals XP, XN and a front-end common-mode output voltage VOCM 1  to generate two output signals YP, YN. The IPR filter  200  includes a fully-differential amplifier  210  and a switch-capacitor circuit including three switch modules  220 ,  230 ,  240  and six capacitors C 1P , C 1N , C 2P , C 2N , C 3P , C 3N . 
         [0022]      FIG. 3  is a diagram showing the relationship between system clock cycles and the four states. While the IPR filter  200  is in operation, it takes two system clock cycles to complete the IPR filtering operation. In other words, the entire filtering operation of the IPR filter  200  can be divided into four states (or stages): state one, state two, state three and state four. The IPR filter  200  operates repeatedly according to the numerical order of the four states, i.e. state one, state two, state three, state four, and so on. 
         [0023]    Please refer to  FIGS. 2 and 3 . The IPR filter  200  is in a hold mode in state one and in state three, whereas the IPR filter  200  is in a sample mode in state two and in state four. In addition, the three switch modules  220 ,  230 ,  240  have different connecting configurations in different states. The IPR filter  200  enables sharing of a common amplifier (i.e. the fully-differential amplifier  210  in this embodiment) with another circuit by setting itself in the hold mode during the falling edge A of the system clock and in the sample mode during the rising edge B of the system clock. The fully-differential amplifier  210  is only necessary during the falling edge A. In order to achieve the purpose of sharing a common amplifier, the capacitance of the capacitors C 1P , C 1N  is designed to be three times that of the capacitors C 2P , C 2N  and the capacitance of the capacitors C 3P , C 3N  is designed to be two times that of the capacitors C 2P , C 2N . 
         [0024]    Suppose that the IPR filter  200  shares a common fully-differential amplifier  210  with a multiply-digital-to-analog converter (MDAC 1 )  480 A, which is a first stage circuit of the ADC  115 . Referring to  FIG. 2 , let the capacitance of the capacitors C 1P , C 1N  be equal to 3C, the capacitance of the capacitors C 2P , C 2N  be equal to C and the capacitance of the capacitors C 3P , C 3N  be equal to 2C. Hereinafter, four states of the IPR filter  200  will be described in detail according to the charge conservation law. 
         [0025]    State One: referring to  FIGS. 3 and 4A , state one begins with a first falling edge A and is hereinafter called the hold mode one. Suppose that the current time is Time=t[n−1]. The IPR filter  200 A uses the fully-differential amplifier  210  for operations, which is therefore represented in solid lines. In the meantime, the MDAC 1  circuit  480 A operates without the fully-differential amplifier  210  that is represented in dotted lines. During the period of state one, the output signals YP[n−1], YN[n−1] of the fully-differential amplifier  210  are the output signals of the IPR filter  200 A. The switch module  220   a  simultaneously feeds the front-end common-mode output voltage VOCM 1  into the capacitors C 1P , C 1N . The positive (negative) input terminal of the fully-differential amplifier  210  and one terminal of each of the three capacitors C 1P , C 2P , C 3P  (C 1N , C 2N , C 3N ) are shorted together in the switch module  230   a.  The negative (positive) output terminal of the fully-differential amplifier  210  and two capacitors C 2P , C 3P  (C 2N , C 3N ) are shorted together in the switch module  240   a.  According to the formula Q=C×V (where Q denotes the amount of charge, C denotes the capacitance and V denotes the voltage), the amount of charge in the capacitor C 2P  is Q 2P [n−1]=C×YP[n−1] while the amount of charge in the capacitor C 2N  is Q 2N [n−1]=C×YN[n−1]. Since the output signals have opposite polarities, i.e., YP[n−1]=−YN[n−1], the two capacitors C 2P , C 2N  will store the same amount of charge but with opposite polarities, i.e., Q 2P [n−1]=−Q 2N [n−1]. 
         [0026]    State Two: referring to  FIGS. 3 and 4B , state two begins with a first rising edge B and is hereinafter called the sample mode. Suppose that the current time is Time=t[n−0.5]. The IPR filter  200 A samples the input signals XP[n−0.5], XN[n−0.5] without the fully-differential amplifier  210 , which is therefore represented in dotted lines. In the meantime, the MDAC 1  circuit  480 B uses the fully-differential amplifier  210  for operations, which is therefore represented in solid lines. During the period of state two, the output signals YP[n−0.5], YN[n−0.5] of the fully-differential amplifier  210  are the output signals of the IPR filter  200 B. The input signals XP[n−0.5], XN[n−0.5] are fed respectively into the capacitors C 1P , C 1N , and the capacitors C 2P , C 2N  are floating. One terminal of each of the four capacitors C 1P , C 1N , C 3P , C 3N  are shorted together in the switch module  230   b  and is provided with a common-mode input voltage VICM. A common-mode output voltage VOCM 2  is provided for the other terminal of the capacitors C 3P , C 3N  in the switch module  240   b.    
         [0027]    Since the capacitors C 2P , C 2N  are floating, the charge stored in the capacitors C 2P , C 2N  during the period of state two are respectively equal to those during the period of state one according to the charge conservation law. That is, the amount of charge in the capacitor C 2P  is Q 2P [n−0.5]=Q 2P [n−1]=C×YP[n−1] and the amount of charge in the capacitor C 2N  is Q 2N [n−0.5]=Q 2N [n−1]=C×YN[n−1]. Based on the small-signal model analysis, the voltages VICM, VOCM 2  can be regarded as being grounded; therefore, Q 3P [n−0.5]=0 and Q 3N [n−0.5]=0. Apparently, the amount of charge in the capacitor C 1P  is Q 1P [n−0.5]=3C×XP[n−0.5] and the amount of charge in the capacitor C 1N  is Q 1N [n−0.5]=3C×XN[n−0.5]. Each of the six input terminals of the MDAC 1  circuit  480 B selects one of the three voltages VRP, VOCM 2 , VRN as their input according to a decision strategy mechanism and the output signals YP[n−0.5], YN[n−0.5] are thus generated. 
         [0028]    State Three: referring now to  FIGS. 3 and 4C , state three begins with a second falling edge A and is hereinafter called the hold mode three. Suppose that the current time is Time=t[n]. The IPR filter  200 A uses the fully-differential amplifier  210  for operations, which is therefore represented in solid lines. In the meantime, the MDAC 1  circuit  480 C operates without the fully-differential amplifier  210  that is represented in dotted lines. During the period of state three, the output signals YP[n], YN[n] of the fully-differential amplifier  210  are the output signals of the IPR filter  200 C. The switch module  220   c  simultaneously feeds the front-end common-mode output voltage VOCM 1  into the capacitors C 1P , C 1N . The positive (negative) input terminal of the fully-differential amplifier  210  and one terminal of each of the three capacitors C 1P , C 2N , C 3P  (C 1N , C 2N , C 3N ) are shorted together in the switch module  230   c.  The negative (positive) output terminal of the fully-differential amplifier  210  and two capacitors C 2N , C 3P  (C 2N , C 3N ) are shorted together in the switch module  240   c.  Please note that while operating in a differential mode, two halves of the fully-differential amplifier  210  are symmetrical, which allows us to use either of the two halves as the half-circuit. According to the charge conservation law, while Time=t[n−0.5] or Time=t[n], the amount of charge in a node F of the IPR filter  200   c  remains constant. Then, Q 1P [n−0.5]+Q 3P [n−0.5]+Q 2N [n−0.5]=Q 1P [n]+Q 3P [n]+Q 2N [n]           3C×XP[n−0.5]+0+C×YN[n−1]=0+2C×YP[n]+C×YP[n]           3C×XP[n−0.5]+0−C×YP[n−1]=0+2C×YP[n]+C×YP[n]           YP[n]=XP[n−0.5]−(⅓) YP[n−1]. 
         [0029]    Thus, the derived transfer function is 
         [0000]    
       
         
           
             
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         [0030]    State Four: referring to  FIGS. 3 and 4D , state four begins with a second rising edge B and is hereinafter called the sample mode. Suppose that the current time is Time=t[n+0.5]. The operations of the IPR filter  200 D and the MDAC 1  circuit  480 D are the same as those of the IPR filter  200 B and the MDAC 1  circuit  480 B during the period of state two, such that further description is therefore omitted herein. Since the capacitors C 2P , C 2N  are floating for the time being, the capacitors C 2P , C 2N  should have the same amount of charge as those during the period of state three. Therefore, the amount of charge in the capacitor C 2P  is Q 2P [n+0.5]=Q 2P [n]=C×YN[n] and the amount of charge in the capacitor C 2N  is Q 2N [n+0.5]=Q 2N [n]=C×YP[n]. Furthermore, based on the small-signal model analysis, the voltages VICM, VOCM 2  can be regarded as being grounded. Therefore, Q 3P [n+0.5]=0 and Q 3N [n+0.5]=0, Q 1P [n−0.5]=3C×XP[n+0.5] and Q 1N [n−0.5]=3C×XN[n+0.5]. 
         [0031]    The circuit then returns to state one. Referring to  FIG. 4E , suppose that the current time is Time=t[n−1]. The output signals YP[n+1], YN[n+1] of the fully-differential amplifier  210  are the output signals of the IPR filter  200 A. According to the charge conservation law, while Time=t[n+0.5] or Time=t[n+1], the amount of charge in a node F of the IPR filter  200   c  remains constant. Then, Q 1P [n+0.5]+Q 3P [n+0.5]+Q 2P [n+0.5]=Q 1P [n+1]+Q 3P [n+1]+Q 2P [n+1]           3C×XP[n+0.5]+0+C×YN[n]=0+2C×YP[n+1]+C×YP[n+1]           3C×XP[n+0.5]+0−C×YP[n]=0+2C×YP[n+1]+C×YP[n+1]           YP[n+1]=XP[n+0.5]−(⅓) YP[n] 
         [0032]    Thus, the derived transfer function is 
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         [0033]    To summarize, under the proposed condition that the IPR filter  200  shares a common fully-differential amplifier with the MDAC 1  circuit of the ADC  115 , the same transfer function H(z) (=1/(1+Kz −1 ), where K&lt;1) is still obtained. In comparison with a conventional IPR  114  having its own fully-differential amplifier, peak-to-average ratio and the magnitude of quantized noise is equally reduced and the same signal-to-noise ratio is attained. Therefore, the IPR filter  200  not only achieves the same function as that achieved conventionally, but also saves the cost of one fully-differential amplifier, and reducing the power consumption of the circuit as well. Nevertheless, it should be noted that the structures and the numbers of the switch modules and capacitors contained in the switch-capacitor circuit are not limited to these particular embodiments described above, as the switch-capacitor circuit may be modified and practiced in different but equivalent manners by referencing the teachings herein. 
         [0034]    While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.