Abstract:
An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the V DD  node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the V DD  node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage and tampering. The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low.

Description:
TECHNICAL FIELD  
       [0001]     The present invention relates to a control circuit for antifuse technology. In particular, the present invention relates to a programming, protection, and sensing device for an antifuse cell.  
       BACKGROUND ART  
       [0002]     Antifuses are used in integrated circuits to provide various circuit selection and configuration functions. When fabricated in a MOS technology, analog components, such as comparators or amplifiers, for example, may require an adjustment of operating parameters. Antifuses are used to select device configurations to effect parameter value adjustments.  
         [0003]     The antifuse is blown by applying a higher than normal voltage or laser beam to the antifuse. The high voltage, for example, produces a short circuit where an open circuit once existed. The application of the laser beam creates a similar short circuit condition. The blown antifuse alters a high impedance situation to a current conducting path that effects a change in a logic level with an applied current. The antifuse generally comprises two conductors, either metal and/or a semiconductor material, having some kind of dielectric or insulating material between the two conductors. In recent practice the dielectric is set to approximately half the normal thickness of a thin oxide FET gate. In the presence of high voltage or laser power the thin oxide is electrically broken down to change from a non-conducting to a conducting condition. The change in conduction is done without affecting any remaining components of a circuit.  
         [0004]     For sensing the logic state of the antifuse device, a sense amplifier is provided to identify the antifuse device to be either non-conducting or conducting. However, the sense amplifier should require very low power consumption in the application of complex communications integrated circuits. In order to satisfy a requirement for low power, small devices are used in the sense amplifier which are susceptible to damage due to overvoltage. What is needed is a device capable of providing both programming capability of the antifuse and electrical isolation from overvoltage of the accompanying sense amplifier.  
       SUMMARY  
       [0005]     An antifuse programming, protection, and sensing device incorporates a control circuit to program and protect an antifuse. The antifuse, which is initially constructed as a low conductivity path, is programmable to a high conductivity path by application of an elevated voltage across terminals of the antifuse. Application of 0 volts to the V DD  node of a conduction control portion of the antifuse programming, protection, and sensing device allows an elevated voltage for programming to be applied to the antifuse. Upon application of a nominal working voltage to the V DD  node of the conduction control circuitry, the antifuse and an adjoining sense amplifier circuit are protected from overvoltage.  
         [0006]     The electrical path to the antifuse for applying the elevated programming voltage and for providing electrical protection from overvoltage and tampering is attained by the same network of devices. The application of one of the two different levels of V DD  alternates the programming and protection network between the two modes of operation. Additionally, the network for electrically isolating the sense amplifier circuitry also, alternatively, electrically couples the sense amplifier with the same two levels of V DD . The sense amplifier supplies a sense current to the antifuse, measures a voltage at an input to the antifuse, and determines a programmed state if a measured voltage level is low. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0007]      FIG. 1  is a schematic diagram of an exemplary antifuse programming, protection, and sensing device.  
         [0008]      FIG. 2  is a schematic diagram of another embodiment of an exemplary antifuse programming, protection, and sensing device with a plurality of antifuse devices. 
     
    
     DETAILED DESCRIPTION  
       [0009]     With reference to  FIG. 1 , an exemplary antifuse programming, protection, and sensing device contains an antifuse MFUSE. The antifuse MFUSE is a thin oxide NMOS transistor. The antifuse MFUSE is fabricated with a gate node, a source node, and a body node tied to ground level so that a conduction path through the antifuse MFUSE, from a drain node to ground, is highly resistive. In this configuration the antifuse MFUSE is considered an open circuit.  
         [0010]     The antifuse MFUSE is connected between a VFUSE node  105  and ground. With a sufficiently high voltage applied to a drain of the antifuse MFUSE, it is damaged (blown) producing a low resistance path from the drain of the VFUSE node  105  to ground. In this state the antifuse MFUSE can be considered a short circuit.  
         [0011]     A sense amplifier  130 , containing a NAND gate structure M 4 , M 8 , M 5 , and M 7  and a buffer M 15 , M 16 , M 13 , and M 14 , is used to sense the antifuse MFUSE and determine if it has been blown or not. An OUTPUT pad  110  communicates a BLOWN signal (not shown), which is a digital logic signal indicating the antifuse MFUSE state. In some applications, the BLOWN signal can be used to enable or disable on-chip circuitry depending on the state of the antifuse MFUSE.  
         [0012]     To read the antifuse MFUSE, a  READ  signal is applied at a READBAR input  120 . The READBAR input  120  connects to the input of a logic inversion device  132  comprised of a first pullup device M 9  and a pulldown device M 10 . The antifuse MFUSE state is read when, for example, 1.8 Volts (V) is applied to the V DD  node  115  and the  READ  signal is driven to the logic level 0. When the antifuse MFUSE is blown, a low resistance path is created from the VFUSE node  105  to ground. A bias circuit  128  is made from a second pullup device M 3  and a bias resistor R 3 . A coupling circuit  145  is made from a transmission gate M 2  and a series resistor R 2 . The coupling circuit  145  is used with a blown antifuse MFUSE to pull down a voltage at the VFUSE_PROTECTED node  125  against the weaker pullup current presented by the bias circuit  128 . The low resistance path from the VFUSE node  105  to ground is small enough compared to the bias resistor R 3  to allow the signal at the VFUSE_PROTECTED node  125  to attain a voltage less than a maximum for a logic level zero. The bias resistor R 3  is selected to be approximately greater than, for example, ten times the value of the low resistance path of the blown antifuse MFUSE. When the potential at the VFUSE_PROTECTED node  125  is pulled low, the sense amplifier  130  has the logic level 0 input and thus drives the BLOWN signal to a logic level 1 at the OUTPUT pad  110 .  
         [0013]     When the antifuse MFUSE is not blown, there is no conduction path from the VFUSE node  105  to ground. The bias circuit  128  pulls the potential at the VFUSE_PROTECTED node  125  up to the logic level 1. When the  READ  signal is the logic level 0, due to the presence of the logic inversion device  132 , the NAND gate structure M 4 , M 8 , M 5 , and M 7  of the sense amplifier  130  has only logic level 1&#39;s on its input and thus drives the BLOWN signal to a logic level 0. When the  READ  signal is at the logic level 1, the BLOWN signal is driven to the logic level 1 regardless of the state (blown or not) of the antifuse MFUSE.  
         [0014]     A control circuit  150  is comprised of a pulldown protection device M 0 , a first pullup resistor R 0 , a second resistor R 1 , a first zero threshold device M 1 A, a second zero threshold device M 1 B, and a series coupling device M 12 . The control circuit  150  is used to either open or close a conduction path from an INPUT pad  134  to the VFUSE node  105 . The control circuit  150  produces a conduction path when the antifuse MFUSE is to be blown. The control circuit  150  is effectively a protection device when the conduction path is open. The conduction path is open when the potential at the V DD  node  115  is powered to a high level of, for example, 1.8 V. With the conduction path open, the state of the antifuse MFUSE can be properly sensed.  
         [0015]     The antifuse MFUSE is blown by applying a programming voltage (not shown) greater than 10 V to the INPUT pad  134 , 0 V to ground, and a 0 V potential to the V DD  node  115 . Under these conditions the pulldown protection device M 0  in the control circuit  150  and the transmission gate M 2  in the coupling circuit  145  are “off.” With the pulldown protection device M 0  and the transmission gate M 2  “off,” a voltage at an M 1 GATE node  135  rises to greater than 10 V with the programming voltage applied. The first zero threshold device M 1 A and the second zero threshold device M 1 B are thick-oxide NMOS devices with threshold voltages (V T ) near 0 V. When the first zero threshold device M 1 A and the second zero threshold device M 1 B are turned “on,” a potential at a source node of the series coupling device M 12  rises to greater than 10 V and the series coupling device M 12  is turned “on.” With the series coupling device M 12  turned “on,” a potential greater than 10 V is applied to the VFUSE node  105 . A potential at the VFUSE node  105  being greater than 10 V is sufficient to blow the antifuse MFUSE.  
         [0016]     With a nominal voltage of, for example, 1.8 V applied to the V DD  node  115 , the pulldown protection device M 0  turns “on” and pulls a gate of the first zero threshold device M 1 A and a gate of the second zero threshold device M 1 B to about 0V. The series combination of the first zero threshold device M 1 A, the second zero threshold device M 1 B, and the series coupling device M 12  is a highly resistive path between the INPUT pad  134  and the VFUSE node  105 . The highly resistive path allows the antifuse MFUSE state to be properly sensed.  
         [0017]     Additional considerations are included to prevent tampering with circuit operation. The INPUT pad  134  node is typically connected to a package bonding pad. In a case where the antifuse MFUSE is blown, the sense amplifier  130  indicates the incorrect state of the antifuse MFUSE if excessive voltage on the INPUT pad  134  causes the potential at the VFUSE node  105  to rise to a level causing an erroneous measurement. The present invention is designed to prevent excessive voltage on the INPUT pad  134  from raising the potential at the VFUSE node  105  while a nominal voltage is applied to the V DD  node  115 .  
         [0018]     As discussed supra, when the nominal voltage is applied to the V DD  node  115 , a voltage at the M 1 GATE node  135  is pulled low by the pulldown protection device M 0 . When voltage is applied to the INPUT pad  134 , a very small current can flow from the INPUT pad  134  to the VFUSE node  105 . However, the current is not large enough to cause the antifuse MFUSE state to be sensed incorrectly.  
         [0019]     If enough voltage is applied to the drain of the first zero threshold device M 1 A to cause punchthrough, the source of the first zero threshold device M 1 A rises in voltage and limits the punchthrough current. The limited current and voltage is not enough to subsequently cause punchthrough of the second zero threshold device M 1 B. Therefore, the path from the INPUT pad  134  to the VFUSE node  105  does not become more conductive and thus protects the antifuse MFUSE.  
         [0020]     With an increase in voltage on the INPUT pad  134  the possibility of breaking down the drain-oxide junction of the first zero threshold device M 1 A is present. If such a breakdown occurs, R 1  prevents the voltage at the M 1 GATE node  135  from rising, thus preventing significant current flow from the INPUT pad  134  to the VFUSE node  105 .  
         [0021]     An electrostatic discharge device  140  is made from an electrostatic discharge transistor MESD and an electrostatic discharge resistor RESD. With a further increase in voltage applied to the INPUT pad  134 , damage to the drain junction of the discharge transistor MESD or the first zero threshold device M 1 A may occur and cause a low resistance from the INPUT pad  134  to ground. The low resistance path prevents the INPUT pad  134  voltage from increasing.  
         [0022]     The coupling circuit  145  protects the sense amplifier  130  connected to the VFUSE_PROTECTED node  125 . When the potential at the V DD  node  115  equals 0 V and a high voltage is applied on the INPUT pad  134 , the transmission gate M 2  is “off” preventing high voltage from reaching the VFUSE_PROTECTED node  125 . The series resistor R 2  limits any possible high current flow to the VFUSE_PROTECTED node  125 .  
         [0023]     With a voltage greater than 10 V applied to the INPUT pad  134  and the potential at the V DD  node  115  equal to 0 V, the second zero threshold device M 1 B continues to be protected from damage causing a condition of continuing conduction after the potential at the V DD  node  115  returns to the nominal operating voltage. With continued rising voltage on the INPUT pad  134 , the pulldown protection device M 0  enters snapback breakdown, which in combination with the first pullup resistor R 0  limits the potential at the M 1 GATE node  135  to a magnitude less than a breakdown voltage. As the potential at the INPUT pad  134  continues to rise, the discharge transistor MESD is damaged and produces a low resistance path to ground. The low resistance path prevents the voltage on the INPUT pad  134  from rising further.  
         [0024]     With reference to  FIG. 2 , a schematic diagram of another embodiment of an exemplary antifuse programming, protection, and sensing device contains a plurality of antifuse devices MFUSE 1 , MFUSE 2 , and MFUSE 3  each connected to a corresponding one of a plurality of VFUSE nodes  205 A,  205 B, and  205 C. With the plurality of antifuse devices MFUSE 1 , MFUSE 2 , and MFUSE 3 , redundancy is added to the circuit and reliability is increased. Additionally, each of the plurality of antifuse devices MFUSE 1 , MFUSE 2 , and MFUSE 3  is connected to a corresponding one of a plurality of series coupling devices M 121 , M 122 , and M 123 . The plurality of series coupling devices M 121 , M 122 , and M 123  are each connected to a corresponding one of a plurality of second zero threshold devices M 1 B 1 , M 1 B 2 , and M 1 B 3 ; each of the plurality of second zero threshold devices M 1 B 1 , M 1 B 2 , and M 1 B 3  is connected to a corresponding one of a plurality of first zero threshold devices M 1 A 1 , M 1 A 2 , and M 1 A 3 ; and are each connected to an INPUT pad  234 . A control circuit  250  is comprised of a pulldown protection device M 0 , a first pullup resistor R 0 , a second resistor R 1 , the plurality of first zero threshold devices M 1 A 1 , M 1 A 2 , and M 1 A 3 , the plurality of second zero threshold devices M 1 B 1 , M 1 B 2 , and M 1 B 3 , and the plurality of series coupling devices M 121 , M 122 , and M 123 . Operation of the control circuit is as discussed supra with reference to  FIG. 1 , with the plurality of devices operating in parallel, as indicated, for redundancy.  
         [0025]     Within a coupling circuit  245 , a plurality of transmission gates M 21 , M 22 , and M 23  connect in series to provide a path for the plurality of antifuse devices MFUSE 1 , MFUSE 2 , and MFUSE 3  to connect with a series resistor R 22 . The coupling circuit connects to the VFUSE_PROTECTED node  125  which is connected to an input of the sense amplifier  130 . Each one of the plurality of transmission gates M 21 , M 22 , and M 23 , the plurality of series coupling devices M 121 , M 122 , and M 123 , and the pulldown protection device M 0  have a control input connected to a third pullup resistor R 5  which is connected to the V DD  node  115  to provide bias levels for programming and protection as described supra with reference to  FIG. 1 . The sense amplifier  130 , bias circuit  128 , and logic inversion device  132  are connected an behave as described supra.  
         [0026]     An electrostatic discharge device  240  is comprised of a plurality of electrostatic discharge transistors MESD 1 , MESD 2  connected in parallel to the INPUT pad  234 . Each one of the plurality of electrostatic discharge transistors MESD 1 , MESD 2  is biased with a plurality of electrostatic discharge resistors RESD 1 , RESD 2 . Each one of the combinations taken from the plurality of electrostatic discharge transistors MESD 1 , MESD 2  and the plurality of electrostatic discharge resistors RESD 1 , RESD 2  operates the same as the electrostatic discharge device  140  described supra with reference to  FIG. 1 . A paralleling of components within the electrostatic discharge device  240  adds redundancy and reliability to the antifuse programming, protection, and sensing device.  
         [0027]     While various portions of an exemplary antifuse programming, protection, and sensing device have been depicted with exemplary components and configurations, an artisan in the field of controllers of electronic storage circuits would readily recognize alternative embodiments for accomplishing a similar result. For instance, a bias circuit has been represented as a PMOS pullup transistor in series with a resistor. One skilled in the art would recognize that a pullup device may be realized from either an NMOS device with a compensated gate voltage, an NMOS device with an aspect ratio appropriate for beta ratioing, or from a pullup resistor alone. Even though a sense amplifier has been portrayed as a NAND gate structure with series buffer, a skilled artisan would recognize that a level sensing device or voltage sensing circuit configured from a differential amplifier or instrumentation amplifier would achieve an equivalent result.  
         [0028]     As further examples, even though a coupling circuit has been shown being implemented from a single NMOS transmission gate and series resistor, an artisan skilled in the field could achieve an equivalent coupling circuit with a parallel combination of NMOS and PMOS transistors with complementary control inputs in series with a resistor. While a logic inversion device has been shown driven by a complementary read control signal and in turn shown driving an adjacent input of a NAND gate to effect gating of a signal on the adjacent input to the NAND gate, one skilled in the art would be able to accomplish the same control with a gating logic device composed of a transmission gate, driven by the control signal, in series with a buffer.  
         [0029]     While an antifuse has been presented as a thin oxide NMOS transistor, one skilled in the art would recognize that the programmability of an additive or subtractive fuse-like characteristic is realizable through electrically configurable conduction devices such as laser programmed fuses, thin ONO (oxide-nitride-oxide) layers sandwiched between a polysilicon layer over an n+ diffusion, or EPROMs. These and further changes to the structure and fabrication of the present invention are readily contemplated in light of the disclosed material. Therefore, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.