Abstract:
A programmable logic device, a memory device and a microcontroller manufactured on a single integrated circuit chip. In one example, the programmable logic device may comprise one or more macrocells each comprising an input/output macrocell or a buried macrocell. In another example, the programmable logic device may be a complex programmable logic device (CPLD) or a programmable logic array (PLA).

Description:
FIELD OF THE INVENTION 
   The present invention relates to microcontrollers generally and, more particularly, to a microcontroller incorporating a programmable logic device. 
   BACKGROUND OF THE INVENTION 
   Conventional approaches to the fabrication of microcontrollers and programmable devices generally require the fabrication of a microcontroller and a programmable device as discrete independent packages or components. In applications where a limited number of gates are required, the overhead (e.g., the additional processing steps) associated with fabricating a programmable device such as a complex programmable logic device (CPLD), a programmable logic device (PLD) or a programmable logic array (PLA), in addition the overhead associated with fabricating a discrete microcontroller, makes the overall design impractical. While previous approaches may implement a microcontroller interface external to the programmable device, conventional approaches have not implemented a programmable device on the same chip as the a microcontroller. 
   SUMMARY OF THE INVENTION 
   The present invention concerns a programmable logic device, a memory device and a microcontroller manufactured on a single integrated circuit chip. In one example, the programmable logic device may comprise one or more macrocells each comprising an input/output macrocell or a buried macrocell. In another example, the programmable logic device may be a complex programmable logic device (CPLD) or a programmable logic array (PLA). 
   The objects, features and advantages of the present invention include fabricating a programmable logic device, a memory device and a microcontroller on a single integrated circuit. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
       FIG. 1  is a block diagram of a preferred embodiment of the present invention; 
       FIG. 2  is a more detailed block diagram of a preferred embodiment of the present invention; 
       FIG. 3  is a more detailed block diagram of an I/O macrocell illustrated in  FIG. 2 ; 
       FIG. 4  is a more detailed block diagram of a buried macrocell illustrated in  FIG. 2 ; and 
       FIG. 5  is a more detailed block diagram of the programmable interconnect matrix illustrated in FIG.  2 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 1 , a block diagram of a circuit  10  is shown in accordance with a preferred embodiment of the present invention. The circuit  10  generally comprises a programmable logic device (or circuit)  12 , a microcontroller  14  and an EPROM  16 . The programmable device  12  may have an input and/or output  20   a  and an input and/or output  20   n  that may each receive or send signals from external devices. The programmable device  12  may also have an input  22 , an input  24  and an output  26 . The input  22  may receive control information from an output bus  28  of the microcontroller  14 . The input  24  may receive data information from an output bus  30  of the microcontroller  14 . 
   The input  32  of the microcontroller  14  may be a multi-bit input that may receive data signals from the output bus  26  of the programmable device  12 . The microcontroller  14  may include an output  34  that may present address information to an input  36  of the EPROM  16 . An output  38  of the EPROM  16  may present data information to an input  40  of the microcontroller  14 . The EPROM  16  may be implemented as a variety of non-volatile memories including an EPROM, an EEPROM, a flash memory, etc. If the programmable device  12 , the microcontroller  14  and the EPROM  16  are fabricated as a single circuit  10 , the overall device area needed to implement a particular application requiring the particular elements of each component may be reduced by combining one or more processing steps common to each device. 
   Referring to  FIG. 2 , a more detailed block diagram of the circuit  10  is shown. In particular, the programmable logic device  12  is shown implemented as a programmable interconnected matrix (PIM)  50 , an input/output (I/O) macrocell  52 , an input/output (I/O) macrocell  54 , a buried macrocell  56  and a buried macrocell  58 . The PIM  50  is shown comprising an output  60  that may present a signal to an input  62  of the macrocell  54 . An output  64  of the macrocell  54  may present a signal to an input  66  of the PIM  50 . The macrocell  54  may also present a signal at an output  68 , through a buffer  70 , to the output  20   a . The buffer  70  may be enabled or disabled with signal  69 . The output of the buffer  70  may also be presented to an input  72  of the PIM  50 . 
   The macrocell  54 , the buffer  70  and the output  20   a  generally represent the devices necessary to implement an typical I/O macrocell (to be described in more detail in connection with FIG.  3 ). The macrocell  52  may have inputs and outputs similar to the macrocell  54  and is shown represented with the primed reference numbers  60 ′,  62 ′,  64 ′,  66 ′,  68 ′  69 ′ and  70 ′. 
   The buried macrocell  58  (to be described in more detail in connection with  FIG. 4 ) generally comprises an input  80  that may receive a signal from an output  82  of the PIM  50 . An output  84  of the buried macrocell  58  may present a signal to an input  86  of the PIM  50 . The buried macrocell  56  may have similar inputs and outputs as the buried macrocell  58  and is shown generally represented with the primed reference numbers  80 ′,  82 ′,  84 ′ and  86 ′. 
   The microcontroller  14  is shown generally connected to additional peripherals generally labeled as other peripheral block  90  and other peripheral block  92 . The other peripherals may be additional components necessary to implement the circuit  10  in a particular design application. For example, the circuit  10  may be implemented in the context of a Peripheral Component Interconnect (PCI) computer bus. In such an example, the other peripherals  90  and  92  may represent components of the PCI bus. Examples of PCI peripherals may include a PCI bridge, a PCI host adapter (e.g., ISA, EISA, MCA, SCSI, etc.), or other PCI peripherals or PCI agents. The PIM  50  additionally comprises an input  94  that may receive a signal (e.g., CLK) from an external pin  96  or an external pin  98 . The pins  96  and  98  are generally connected to the input  94  through an inverter  100  and an inverter  102 . As a result, the input  94  may receive the signal CLK representing an external periodic clock. The inverter  100  may be used as part of an oscillator circuit when combined with external components. The PIM  50  may also receive additional external signals  104  at the PIM input  106 . 
   Referring to  FIG. 3 , a more detailed block diagram of the I/O macrocell  52  or  54  is shown. In one example, the I/O macrocell  52  is shown having a memory block (or circuit)  110 , a multiplexor block (or circuit)  112  and a gate  114 . The multiplexor block  112  may be implemented as a 2:1 multiplexor having an output  115  that may present a signal to the buffer  70 . The memory block  110  may be implemented as a flip-flop that may operate in a variety of modes determined by a first select input  116  and a second select input  118 . The mode of the memory block  110  may be determined by the following TABLE 1: 
   
     
       
             
             
             
             
           
         
             
                 
               TABLE 1 
             
             
                 
                 
             
             
                 
               C2 
               C1 
               Mode 
             
             
                 
                 
             
           
           
             
                 
               1 
               1 
               D-FF 
             
             
                 
               1 
               0 
               T-FF 
             
             
                 
               0 
               1 
               Latch 
             
             
                 
               0 
               0 
               Buffers 
             
             
                 
                 
             
           
        
       
     
   
   The mode column in TABLE 1 generally illustrates the mode of operation of the memory block  110 . The first mode generally indicates a D-flip-flop operation, the second mode generally indicates a T-flip-flop (toggle) operation, the third mode generally indicates a latch operation and the fourth mode generally indicates a buffer operation. 
   The memory block  110  also has an input  120  that receives a signal from the gate  114 . The gate  114  comprises a number of inputs  122   a - 122   n . Each of the inputs  122   a - 122   n  may receive a product term signal (e.g., ProdTerm 0 -ProdTermN). When the gate  114  is implemented as an OR gate, a signal may be presented to the input  120  when any of the product term signals ProdTerm 0 -ProdTermN are present at the inputs  122   a - 122   n . The block  110  also comprises an input  130  that may receive a clock signal (e.g., CLK). The memory block  110  also has an input  132  that may receive a reset signal (e.g., RST Term). The configuration signals C 1  and C 2  may be presented to the inputs  116  and  118  and may be received from the EPROM  16 . As a result, the functionality of the macrocell  52  may be adjusted after the fabrication of the circuit  10 . 
   The memory block  110  also comprises an output  140  and an output  142  that generally represent an output Q and an output Q bar. The output Q bar may be a complementary signal to the output Q presented at the output  140 . The multiplexor  112  has an input  144  and an input  146  that may each receive the output Q and the output Q bar, respectively. The multiplexor block  112  also has a select input  150  that may receive a select signal C 0  that may be used to select between the input  144  and the input  146  to provide the signal at the output  115 . The input C 0  may be a configuration bit received from the EPROM  16 . As a result, the macrocell  52  may invert the polarity of the signal presented at the output  20   a  in a post-production step after the fabrication of the circuit  10 . 
   Referring to  FIG. 4 , a more detailed block diagram of the buried macrocell  58  is shown. The buried macrocell  58  comprises similar blocks and components as the macrocell  52  that are generally indicated with primed referenced numbers. For example, the block  110 ′ may be similar to the block  110  and the block  112 ′ may be similar to the block  112 . The buried macrocell  58  generally does not implement the buffer  70  or the input/output  20   a . As a result, the buried macrocell  58  may be implemented to control internal functions of the programmable logic device  12 . 
   Referring to  FIG. 5 , a more detailed diagram of the programmable interconnect matrix  50  is shown. The programmable interconnect matrix  50  is shown generally connected to an I/O macrocell  52  and a buried macrocell  56 . The PIM  50  has a number of inputs  160   a - 160   n  that each may receive a number of external inputs. The signals received at the inputs  160   a - 160   n  are generally presented on an internal line  162   a  and an internal  162   b . The internal line  162   b  is generally inverted through an inverter  164 . The signals from the I/O macrocell  52  are generally received at an input  170 , an input  172 , an input  174 , an input  176  and an input  178 . The PIM  50  may present the product term signals ProdTerm 0 -ProdTermN at the outputs  180   a - 180   n  that may be presented to the inputs  122   a - 122   n . Similar outputs  190 ,  192  and  194  may be presented to the buried macrocell  56 . Similarly, the outputs  122   a - 122   n  present the product term signals ProdTerm 0 -ProdTermN. 
   The PIM  50  may present the signals to the data inputs  32   a - 32   n  of the microcontroller  14 . Address, control and data out signals may be presented at the outputs  28  and  30  to the inputs  22  and  24 , respectively. The symbol  200  generally indicates a programmable connection that is in an open state. The symbol  202  generally indicates a programmable connection that is an active state. When open, a vertical signal (i.e., a signal received from the inputs  22  and  24 ) generally has no affect on the horizontal inputs (i.e.,  170 - 1708 ). However, when a connection is active, a low condition on the vertical signal generally forms a low condition on the horizontal signal. The horizontal wires are generally arranged to form a “wired and” or “wired or” function. The active state of the vertical select wire (active high or active low) and the active state of the horizontal wire (high or low) are not generally critical and may depend on the requirements of the specific implementation. 
   While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.