Abstract:
An emitter-coupled logic circuit provides differential outputs which are delivered to pairs of transistors in emitter-coupled logic (ECL) switches. The differential outputs allow additional ECL switches to be connected between a positive and negative supply voltage. A unique current source for the ECL switches includes diodes and/or transistors connected in parallel with the ECL switches such that the supply current is relatively independent of fluctuations in the supply voltage and yet the voltage drop across the current source is minimized.

Description:
This application is a continuation of application Ser. No. 08/193,318, filed Feb. 8, 1994, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to emitter-coupled logic circuits and, in particular, an improved series-gated emitter-coupled logic circuit which permits a greater number of decision-making levels to be connected between the positive and negative supply voltages. 
     BACKGROUND OF THE INVENTION 
     Emitter-coupled logic circuits generally operate by switching currents between two parallel current paths. A switching transistor is connected in each of the parallel paths, and the emitters of the transistors are coupled together. A basic current-mode logic (CML) switch 10 is illustrated in FIG. 1. The switch is connected between a positive supply voltage V CC  and a negative supply voltage V EE . A current source CS supplies a constant current I S . In the normal arrangement, V BB  is a reference voltage which is applied to the base of a transistor Q2 and the input voltage V IN  is applied to the base of a transistor Q1. V BB  is set at a point halfway between the high and low states of the input voltage V IN . Thus, when V IN  is high, transistor Q1 conducts and a voltage drop across a load resistor R1 causes the output V C1  to go low. Conversely, when V IN  is low, transistor Q2 conducts and the output voltage V C1  goes high. 
     The output voltage V C2  is the inverse of V C1 . That is, when V IN  is high, the output V C2  is high; when V IN  is low, the output V C2  is low. 
     The minimum voltage swing between the high and low states of V IN  necessary to switch the current completely between transistors Q1 and Q2 is about 250 mV, centered about V BB . Alternatively, transistors Q1 and Q2 can be driven differentially with a smaller voltage swing (e.g., 150 mV). Normally, the input signal swing is made considerably larger (approximately 600-750 mV for a single-ended input and 300-350 mV for differential inputs) to provide noise immunity and to allow for variations in the output voltage levels in the CML switches connected into a given logic network. In FIG. 1, VC1 ranges from V CC  (typically ground) when transistor Q1 is turned off to approximately -0.35 V when Q1 is conducting the current I S  (i.e., I S  ×R1=0.35 V). 
     A conventional buffered emitter-coupled logic (ECL) circuit 20 is illustrated in FIG. 2. To avoid transistor saturation and accommodate large voltage swings, as well as to increase the interconnect driving capabilities, emitter followers Q3 and Q4 have been added. The emitter followers Q3 and Q4 have their collectors connected to a separate positive supply voltage V CCA  to ensure that any changes in load currents during switching do not cause a change in V CC  through the small but finite inductance of the V CCA  bond wire and package lead. Outside the package, the V CC  and V CCA  leads are normally connected to a common V CC  distribution. Thus, the voltages at the emitters of emitter followers Q3 and Q4 are approximately one diode drop (φ) below the output voltages V C1  and V C2 . Since R1=R2, I S  ×R1=I S  ×R2, which is equal to about 750 mV. Assuming that 750 mV≈φ, the output voltages V&#39; C1  and V&#39; C2  vary between a high state of about -φ and a low state of about -2φ. 
     FIGS. 1 and 2 show a single level of decision-making, represented by the conductive state of the transistor pair Q1 and Q2. A series of decision-making levels can be used to perform AND and NAND logic functions. FIG. 3 illustrates an AND/NAND logic gate 30, which includes an additional transistor pair consisting of transistors Q5 and Q6. Unless inputs A and B are both high, no current flows through load resistor R1, and a current flows through load resistor R2. If only input A is low, for example, current flows through transistors Q2 and Q5; if only input B is low, a current flows through transistor Q6. Hence, the output V C1  is equal to AB and the output V C2  is equal to AB. 
     In FIG. 3, assuming that V CC  is set at ground, input A would vary between -φ (high) and -2φ (low) and reference voltage V BB  would be set at approximately -1.5φ. Therefore, in the worst case, the coupled emitters of transistors Q1 and Q2 would be at approximately -2.5φ. The input B must be translated downwards by φ, so that it varies between -2φ and -3φ, and the reference voltage V&#39; BB  is set at about -2.5φ. 
     The need to translate additional inputs downwards sets a limit on the number of decision-making levels that can be used in a series-gated ECL circuit. For a typical negative supply voltage V EE  of -5.2 V, the practical limit known in the prior art is three levels. FIG. 4 illustrates a schematic circuit diagram of a generalized three-level ECL circuit 40, transistors Q7 and Q8 representing the third level. As shown, the coupled emitters of transistors Q5 and Q6 are at about -3.5φ and the additional input C is shifted downward by a transistor Q9 and a diode D1. Thus, input C is translated downward by 2φ so that the voltage at the base of transistor Q7 varies between -3.0φ (high) and -4.0φ (low). The third reference voltage V&#39;&#39; BB  is set at -3.5φ. 
     FIG. 4 also illustrates that current source CS includes a transistor Q10 and a resistor RCS. The current I S  is determined by an internally generated reference voltage V CS , the value of resistor RCS, and the base-emitter voltage of transistor Q10. V CS  is designed to remain fixed with respect to the negative supply voltage V EE , which makes I S  independent of supply voltage. Regulating the current I S  in this way simplifies system design because the output voltage and switching parameters are not sensitive to changes in V EE . Output voltage levels are determined primarily by the voltage drops across load resistors R1 and R2 resulting from the collector currents of transistors Q1 and Q2. Since these collector currents are determined by I S  and the α&#39;s of transistors Q1 and Q2, the voltage drops across the load resistors R1 and R2 are relatively insensitive to variations in V EE . 
     Using a current source of this kind creates a voltage drop of approximately 1.5φ between the base of transistor Q10 and the negative supply voltage V EE . This is the result of the band gap regulator design. Since the collector of transistor Q10 is at a voltage approximately equal to -4.5φ, the total voltage drop between the positive and negative supply rails is approximately 6φ. With a supply voltage of 5.2 V (V EE  =-5.2 V±5%), which is typical in 10 KH logic, this arrangement limits the number of decision-making levels that can be connected in a series-gated arrangement to a maximum of three. 
     Since the use of series-gated arrangements greatly enhances logic capability and performance with low device count, it is desirable to increase the permissible number of decision-making levels. This is accomplished in a circuit in accordance with the principles of this invention. 
     SUMMARY OF THE INVENTION 
     An emitter-coupled logic (ECL) circuit according to this invention includes a plurality of basic emitter-coupled switches, each switch representing a decision-making level and containing a pair of transistors connected in respective parallel current paths. A unique output circuit provides closely-spaced output voltages. 
     In the preferred embodiment, a pair of differential inputs are applied to each pair of transistors, with a true input being applied to one transistor of each pair and an inverse input being applied to the other transistor of the pair. 
     The output circuit provides a plurality of closely-spaced outputs. A PN junction (preferably the base-emitter junction of a transistor) is connected in series with a load resistor. A voltage divider is connected in parallel with this series combination. Outputs may be taken at a point in the series path between the load resistor and the PN junction, an intermediate point in the voltage divider, and at an end of the voltage divider. Additional outputs can be created by adding more PN junctions and voltage dividers. Inverse outputs can be generated by connecting a similar circuit to a second load resistor. 
     A supply current (I S ) source includes a plurality of PN junctions (in the form of diodes and/or transistors) connected serially in a conduction path parallel with the decision-making levels. The series of PN junctions together provide a preselected voltage drop across the decision-making levels and ensure that the supply current is largely independent of variations in the voltage between the positive and negative supply voltages. This arrangement minimizes the voltage drop required by the current source and maximizes the number of levels that may be included between the positive and negative supply voltages. (As used herein, the terms &#34;positive&#34; and &#34;negative&#34; supply voltage express the relative voltage difference between the two supply voltages. Either supply voltage may be positive, negative or grounded in absolute terms.) 
     In a preferred embodiment, a total of four decision-making levels are provided in an ECL circuit supplied by a voltage difference of only 3.3 V. This invention is not limited to a 3.3 V power supply, however, but may be applied to any supply voltage. 
     The ECL logic circuit of this invention is preferably formed in an integrated circuit (IC) chip. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a circuit diagram of a basic CML switch. 
     FIG. 2 illustrates a circuit diagram of a buffered ECL circuit. 
     FIG. 3 illustrates a conventional logic circuit configured to perform AND and NAND functions. 
     FIG. 4 illustrates a conventional logic circuit which includes three decision-making levels. 
     FIG. 5 illustrates an ECL logic circuit in accordance with this invention. 
    
    
     DESCRIPTION OF THE INVENTION 
     FIG. 5 illustrates an ECL circuit 50 according to the invention which includes four decision-making levels interposed between positive and negative supply rails separated by 3.3 V. In this embodiment, V CC  is set at ground and V EE  is set at -3.3 V. The four decision-making levels include transistor pairs Q 1  and Q 2 , Q 3  and Q 4 , Q 5  and Q 6 , and Q 7  and Q 8 , respectively. The collector of transistor Q 3  is connected to the emitters of paired transistors Q 1  and Q 2  ; the collector of transistor Q 5  is connected to the emitters of paired transistors Q 3  and Q 4  ; etc. The collectors of transistors Q 2 , Q 4 , Q 6  and Q 8  may be connected directly to the positive supply voltage V CC  or may be connected to other transistor pairs (not shown) to form a logic circuit in accordance with techniques well known in the art. For example, transistors Q 2 , Q 4 , Q 6  and Q 8  may be connected into an octal decoding tree of the kind illustrated in FIG. 2-7 of the &#34;F100K ECL User&#39;s Handbook&#34;, Fairchild Camera and Instrument Corporation (1982), which is incorporated herein by reference. 
     Load resistors R 1  and R 2  are connected between V CC  and the collectors of transistors Q 1  and Q 2 , respectively. A constant current I S  is supplied by a current supply C S  which is connected between the emitters of transistors Q 7   and Q 8  and the negative supply voltage V EE . Resistors R 1  and R 2  are sized such that the constant current I S  through either of them provides a voltage drop equal to 0.5φ (approximately 375 mV). The voltages at various points in the circuit are designated with reference to ground by multiples of a diode voltage drop φ. (Each unit φ is equal to approximately 750 mV.) 
     Differential inputs are supplied to the base terminals of transistors Q 1  and Q 2 , Q 3  and Q 4 , Q 5  and Q 6 , and Q 7  and Q 8 . In particular, an input A is supplied to the base of transistor Q 1  and an inverse input A is supplied to the base of transistor Q 2 , a second input B is supplied to the base of transistor Q 3 , and an inverse input B is supplied to the base of transistor Q 4 , etc. 
     Current supply C S  includes diodes D 1  and D 2 , a transistor Q 9 , and resistors R CS , R D  and R 3 . (Since ECL circuit 50 is preferably formed in an IC chip, diodes D 1  and D 2  would actually be transistors with shorted collector-base terminals.) The emitter of transistor Q 9  is connected through a resistor R CS  to the coupled emitter terminals of transistors Q 7  and Q 8 . The base of transistor Q 9  is connected through a resistor R 3  to the negative supply voltage V EE . Resistor R CS  is connected in series with a damping resistor R D  to V EE . The combination of diodes D 1  and D 2  and transistor Q 9  yields a voltage of -3φ at the common junction of resistors R CS  and R D . Each of diodes D 1  and D 2  and transistor Q 9  provides a PN junction which is forward-biased and contributes a single diode voltage drop φ when circuit 50 is operative. The PN junctions in diodes D 1  and D 2  and transistor Q 9  are connected serially in a conduction path 54 which is connected in parallel with the four decision-making levels shown in FIG. 5 (represented by transistor pairs Q 1  /Q 2 , Q 3  /Q 4 . Q 5  /Q 6 , Q 7  /Q 8 ). Resistor R 3  is used to bias diodes D 1  and D 2 . 
     ECL circuit 50 also includes a true output circuit 51 and an inverse output circuit 52. True output circuit 51 includes a transistor Q 10  having a base tied to the collector of transistor Q 2 . Resistors R 5  and R 6 , which are equal, are connected in parallel with the collector-emitter path of transistor Q 10 . The common junction between resistors R 5  and R 6  is connected to the base of a transistor Q 11 . The emitters of transistors Q 10  and Q 11  are connected through resistors R 7  and R 8 , respectively, to the negative supply voltage V EE . 
     Similarly, inverse output circuit 52 includes a transistor Q 12  having a base connected to the collector of transistor Q 1 , equal resistors R 9  and R 10  connected in parallel with the collector-emitter path of transistor Q 12 , and a transistor Q 13  having a base connected to the common junction between resistors R 9  and R 10 . The emitters of transistors Q 12  and Q 13  are connected through resistors R 11  and R 12 , respectively, to the negative supply voltage V EE . 
     As indicated in FIG. 5, the true outputs A, B, C and D are taken from output circuit 51 as follows. Output A is connected to the base of transistor Q 10 , output B is connected to the junction of resistors R 5  and R 6  and the base of transistor Q 11 , output C is connected to the emitter of transistor Q 10 , and output D is connected to the emitter of transistor Q 11 . Similarly, in inverse output circuit 52, output A is connected to the base of transistor Q 12 , output B is connected to the common junction of resistors R 9  and R 10 , output C is connected to the emitter of transistor Q 12 , and output D is connected to the emitter of transistor Q 13 . 
     As noted above, resistors R 1  and R 2  are sized such that R 1  ×I S  =0.5φ and R 2  ×I S  =0.5φ. Thus, when transistor Q 1  is turned on, the voltage at the base of transistor Q 12  is equal to -0.5φ, and the voltage at the base of transistor Q 10  is equal to 0 V. Conversely, when transistor Q 1  is turned off and transistor Q 2  is turned on, the voltage at the base of transistor Q 12  is equal to 0 V and the voltage at the base of transistor Q 10  is equal to -0.5φ. Thus output A varies between a high state of 0 V and a low state of -0.5φ. The voltage at the emitter of transistor Q 10  is 1.0φ below the voltage at the base of transistor Q 10 , and resistors R 5  and R 6 , which are equal, act as a voltage divider which divides the voltage between the positive voltage supply and the negative emitter of transistor Q 10  by 2. Thus the voltage at output B is equal to -0.5φ in its high state and -0.75φ in its low state. The voltage at output C is double these values, namely, -φ in its high state and -1.5φ in its low state. Since output B is connected to the base of transistor Q 11  and output D is connected to the emitter of transistor Q 11 , output D is one diode drop below output B. Hence output D varies between -1.5φ in its high state and -1.75φ in its low state. The high (V OH ) and low (V OL ) outputs of true output circuit 51 are summarized in Table 1. 
     
                       TABLE 1______________________________________Output         V.sub.OH                  V.sub.OL______________________________________A              0       -0.5φB              -0.5φ                  -0.75φC              -φ  -1.5φD              -1.5φ                  -1.75φ______________________________________ 
    
     By a similar process, the inverse outputs A, B, C and D can be determined and are shown in Table 2. 
     
                       TABLE 2______________________________________Output         V.sub.OH                  V.sub.OL______________________________________A              0       -0.5φB              -0.5φ                  -0.75φC              -φ  -1.5φD              -1.5φ                  -1.75φ______________________________________ 
    
     The differential output pairs A/A, B/B, C/C and D/D are connected to the corresponding inputs of an ECL circuit similar to ECL circuit 50. Thus output A is connected to the base of a transistor corresponding to transistor Q 1  and output A is connected to the base of a transistor corresponding to transistor Q 2 . Similarly, the outputs B/B, C/C and D/D would be connected to transistor pairs corresponding to transistors Q 3  /Q 4 , Q 5  /Q 6 , and Q 7  /Q 8 . 
     The voltage at the emitters of transistor pairs Q 1  /Q 2 , Q 3  /Q 4 , Q 5  /Q 6  and Q 7  /Q 8  is equal to a diode drop below the voltage at the base of whichever transistor in the pair is conducting. For example, when transistor Q 1  is conducting, its base voltage is equal to 0 V, and its emitter voltage is therefore equal to -φ; when transistor Q 2  is conducting its base voltage is equal to 0 V and thus the voltage at its emitter remains at -φ. From the above tables, it is apparent that the voltage at the emitters of transistors Q 3  and Q 4  is equal to -1.5φ, the voltage at the emitters of transistors Q 5  and Q 6  is equal to -2φ and the voltage at the emitters of transistors Q 7  and Q 8  is equal to -2.5φ. 
     Accordingly, the voltage across resistor R CS  is equal to -2.5φ-(-3φ)=0.5φ, and ##EQU1## 
     This demonstrates that the supply current I S  is relatively constant since it is not effected by fluctuations in the negative supply voltage V EE . Such variations are absorbed by the damping resistor R D . 
     The magnitude of I S  in turn determines the values of resistors R 1  and R 2 . If V S  represents the desired voltage swing of outputs A and A: ##EQU2## 
     The differential outputs of an ECL circuit according to this invention may be connected to the base terminals of a corresponding transistor pair in a similar ECL circuit. The need to translate the outputs is eliminated. 
     It will be understood that the ECL circuit illustrated in FIG. 5 is merely illustrative of the many and varied types of logic circuits that can be constructed using techniques well known in the art. While the ECL circuit described contains four decision-making levels with a supply voltage difference of only 3.3 V, if the supply voltage were increased, more levels could be included. For example, with a voltage difference of 5.2 V, seven decision-making levels could be included in a single ECL circuit. Moreover, one of output circuits 51 and 52 may be omitted, and single-ended inputs could be substituted for the differential inputs A/A, etc., with the base of one transistor in transistor pairs Q 1  /Q 2 , etc., being tied to a reference voltage (see V BB , V&#39; BB  in FIG. 3). Many additional and alternative embodiments will be apparent to those skilled in the art, all of which are intended to be included within the broad scope of this invention.