Abstract:
A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.

Description:
CLAIM OF PRIORITY 
       [0001]    The present application claims priority from Japanese patent application JP 2007-185425 filed on Jul. 17, 2007, the content of which is hereby incorporated by reference into this application. 
       FIELD OF THE INVENTION 
       [0002]    The present invention relates to a semiconductor device, and relates in particular to technology effective for use with SiP (System in Package) made up of stacked semiconductor integrated circuits and semiconductor integrated circuits used in microprocessors, etc. 
       BACKGROUND OF THE INVENTION 
       [0003]    The technology studied by the inventors may include the following technology for semiconductors. 
         [0004]    Along with the increasing device miniaturization achieved by semiconductor manufacturing technology, the problem of inadequate I/O capability on semiconductor chips is becoming more and more serious. 
         [0005]    This problem of inadequate I/O capability is due to an increasing number of circuits as the semiconductor chips become smaller. Moreover as the operation of each circuit speeds up, the I/O processing load needed to implement semiconductor chip functions becomes larger. The number of terminals on a semiconductor chip however is basically determined by the chip size due to restrictions such as wire bonding. The number of terminals does not increase when chips are made smaller so there is no improvement in I/O processing capability. 
         [0006]    To resolve the problem of inadequate I/O capability on semiconductor chips, three-dimensional coupling techniques were intensively developed for forming terminals in two-dimensional shapes on the upper surface and lower surface of the semiconductor chip and then stacking the semiconductor chips in multiple layers to transmit information between the stacked chips. 
         [0007]    Three-dimensional coupling techniques can be broadly grouped into a contact method that makes the semiconductor chips physically contact each other by way of via holes (or through holes); and a non-contact method that carries out non-contact communication by utilizing coils and capacitors. 
         [0008]    The non-contact method includes an inductive coupling method utilizing stacked semiconductor chips formed as coils that cause an electrical current to flow in the coil mounted in the semiconductor chip for transmitting information, to induce a magnetic field, and transmit information by measuring the inductive current occurring in the coil mounted in the semiconductor chip that receives the information. The non-contact method also includes a capacitive coupling method where a capacitor is formed between the semiconductor chip for receiving information and the semiconductor chip for transmitting information, and information is transmitted by charging/discharging the capacitor from the semiconductor chip on the side transmitting the information, and detecting the charge on the capacitor at the semiconductor chip on the side receiving the information. 
         [0009]    JP-A No. 2006-066454 discloses an example of technology for transmitting data between chips by utilizing inductive type three-dimension coupling technology. Also, JP-A No. 2004-253186 discloses an example of technology for transmitting data between chips by utilizing capacitive type three-dimensional coupling technology. 
       SUMMARY OF THE INVENTION 
       [0010]    However a study of the above semiconductor devices of the related art by the present inventors revealed the following problems. 
         [0011]    Supplying electrical power to the semiconductor chips for example is impossible when using either of the inductive or capacitive type coupling methods. Moreover, communication between the semiconductor chip and a device outside the package containing that chip requires making a physical connection. 
         [0012]    Therefore, when forming a SiP from multiple stacked semiconductor chips containing non-contact type three-dimensional couplings, the coil or capacitor for the three dimensional coupling, as well as a physical connection to the power supply and ground, and for communicating outside the package, must all be present within the package. 
         [0013]    Also, when forming a SiP from multiple stacked semiconductor chips with the same function, developing and manufacturing multiple types of chips to match the stacked positions is not desirable. Instead, stacking semiconductor chips manufactured with the same design information is preferable in terms of development costs. 
         [0014]    In integrated circuits of the related art containing three-dimensional coupling circuits that utilize inductive coupling or capacitive coupling, the electrical power was supplied to the applicable integrated circuit by way of wire bonding or micro-bumps or via holes (through holes). 
         [0015]    If a so-called “pyramid” SiP where the surface area of the integrated circuit installed in the lower position is large, and the surface area of the integrated circuit installed in the upper position is small, then bonding wire also connects to the integrated circuit installed at the intermediate (mid) position. However, in the so-called “inverted pyramid” SiP or the case where the chip sizes are the same or the upper chip surface area is larger than the lower chip, then when connecting to the integrated circuit at the intermediate position by bonding wire, then spacers must be inserted between both chips and a space provided between the upper and lower chips. 
         [0016]    When using micro-bumps then an interposer must be inserted between the chips, and a separate integrated circuit and external terminal must be connected to the micro-bump formed on the integrated circuit. 
         [0017]    When stacking identically designed chips containing via holes, the chips are stacked on each other with no offset in order to make contact with the via holes on adjacent chips. 
         [0018]    Insertion of spacers and interposers should be avoided in three-dimensional couplings in order to keep the transmission distance as short as possible. Mounting multiple transmission coils along the same axis when using inductive type three-dimensional coupling disrupts communications so countermeasures such as transmission time-sharing were required to restore communications via three-dimensional coupling where chips of identical design were stacked with no offsets. 
         [0019]    In view of the above problems with the related art, the present invention has the object of providing technology for semiconductor devices that allows stacking multiple chips of the same design and also improving the information transmission capability of the three-dimensional coupling while eliminating spacers and interposers. 
         [0020]    Other objectives and unique features of this invention will become apparent from the description in these specifications and the drawings. 
         [0021]    A brief description of typical aspects disclosed in this invention is given as follows. 
         [0022]    Namely, the semiconductor device of this invention is a first semiconductor integrated circuit including a three-dimensional coupling circuit (three-dimensional coupling transmit terminal group and three-dimensional coupling receiver terminal group); and a second and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole) in a stacked configuration. 
         [0023]    The semiconductor device of this invention is a stacked first and second and third semiconductor integrated circuits containing a three-dimensional coupling circuit and feed-through electrode. 
         [0024]    The typical effects rendered by the invention disclosed in these specifications are briefly described as follows.
   (1) The invention achieves high-speed communication by three-dimensional coupling between semiconductor integrated circuits (semiconductor chips), communication by physical wiring between the semiconductor integrated circuit and outside the package; and supply of power to the semiconductor integrated circuit.   (2) The invention reduces the costs required for developing semiconductor chips to a minimum.   
 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]      FIG. 1  is a block diagram showing the related function connections of the SiP of the first through fifth embodiments of this invention; 
           [0028]      FIG. 2  is a drawing showing the internal structure of the SiP when the SoC (System-on-chip), the memory A, and the memory B are stacked using the technology of the prior art; 
           [0029]      FIG. 3  is a drawing seen from a horizontal view showing the semiconductor integrated mounted in the SiP of the first embodiment of this invention; 
           [0030]      FIG. 4  is a drawing seen from a top view showing the semiconductor integrated mounted in the SiP of the first embodiment of this invention; 
           [0031]      FIG. 5  is a top view of the SoC of the first embodiment of this invention; 
           [0032]      FIG. 6  is a top view of the memory A of the first embodiment of this invention; 
           [0033]      FIG. 7  is a top view of the memory B of the first embodiment of this invention; 
           [0034]      FIG. 8  is a drawing showing the terminal array of the three-dimensional coupling of the SoC (System-on-chip) of the first embodiment of this invention; 
           [0035]      FIG. 9  is a drawing showing the terminal array of the three-dimensional coupling for the memory A of the first embodiment of this invention; 
           [0036]      FIG. 10  is a drawing showing the terminal array of the three-dimensional coupling for the memory B of the first embodiment of this invention; 
           [0037]      FIG. 11  is a drawing as seen from a horizontal view of the semiconductor integrated circuit mounted in the SiP of the second embodiment of this invention; 
           [0038]      FIG. 12  is a drawing as seen from a top view of the semiconductor integrated circuit mounted in the SiP of the second embodiment of this invention; 
           [0039]      FIG. 13  is a top view of the SoC of the second embodiment of this invention; 
           [0040]      FIG. 14  is a drawing showing a horizontal view of the semiconductor integrated circuit mounted in the third embodiment of this invention; 
           [0041]      FIG. 15  is a drawing showing a top view of the semiconductor integrated circuit mounted in the third embodiment of this invention; 
           [0042]      FIG. 16  is a top view of the SoC of the third embodiment of this invention; 
           [0043]      FIG. 17  is a top view of the memory A of the third embodiment of this invention; 
           [0044]      FIG. 18  is a top view of the memory B of the third embodiment of this invention; 
           [0045]      FIG. 19  is a drawing showing the terminal array for the three-dimensional coupling terminals on the SoC (System-on-chip) of the third embodiment of this invention; 
           [0046]      FIG. 20  is a drawing showing the terminal array for the three-dimensional coupling terminals on the Memory A of the third embodiment of this invention; 
           [0047]      FIG. 21  is a drawing showing the terminal array for the three-dimensional coupling terminals on the Memory B of the third embodiment of this invention; 
           [0048]      FIG. 22  is a drawing as seen from a horizontal view showing the semiconductor integrated circuit mounted in the SiP of the fourth embodiment of this invention; 
           [0049]      FIG. 23  is a top view of the semiconductor integrated circuits stacked in the Sip of the fourth embodiment of this invention; 
           [0050]      FIG. 24  is a top view of the SoC (System-on-chip) of the fourth embodiment of this invention; 
           [0051]      FIG. 25  is a drawing as seen from a horizontal view showing the semiconductor integrated circuit mounted in the Sip of the fifth embodiment of this invention; 
           [0052]      FIG. 26  is a top view of the SiP of the SiP of the fifth embodiment of this invention; 
           [0053]      FIG. 27  is a block diagram showing the functional connection relations of the SiP of the sixth embodiment of this invention; 
           [0054]      FIG. 28  is a drawing as seen from a horizontal view showing the semiconductor integrated circuits mounted in the SiP of the sixth embodiment of this invention; 
           [0055]      FIG. 29  is a top view showing the semiconductor integrated circuits stacked in the SiP of the sixth embodiment of this invention; 
           [0056]      FIG. 30  is a top view of the SoCA of the sixth embodiment of this invention; 
           [0057]      FIG. 31  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups A on the SoCA in the sixth embodiment of this invention; 
           [0058]      FIG. 32  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups B on the SoCB in the sixth embodiment of this invention; 
           [0059]      FIG. 33  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups C on SoCC in the sixth embodiment of this invention; 
           [0060]      FIG. 34  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups D on SoCD in the sixth embodiment of this invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0061]    The embodiments of this invention are hereinafter described in detail based on the drawings. The same structural members are as a general rule assigned the same reference numerals in all drawings for the embodiments and repeated descriptions are emitted. 
       First Embodiment 
       [0062]    The first embodiment of this invention is stacked semiconductor integrated circuits contained in the SiP with the terminals set upwards and connected by bonding wire. 
         [0063]      FIG. 1  is a block diagram showing the structure of the semiconductor device of the first embodiment of this invention.  FIG. 1  is a logical block diagram showing the related functional connections for the System In Package (Hereafter, called SIP.) of the first embodiment of this invention. 
         [0064]    The SiP  10  contains a SoC 101 , a memory A 102 , and a memory B 103  as well as a function for communicating outside the SiP 10 . The SoC 101  implements the applicable communication function by loading the program stored in the memory A 102  and memory B 103 . The SoC 101  also contains a function for writing on the memory A 102  and the memory B 103 . 
         [0065]    The SoC 101  as well as memory A 102  and memory B 103  are semiconductor integrated circuits made for example from single crystal silicon and including CMOS (complementary MOS transistors) or bipolar transistors formed by conventional semiconductor integrated circuit technology. The SoC 101  as well as memory A 102  and memory B 103  are connected to power and ground during operation. 
         [0066]    The SoC 101 , memory A 102  and memory B 103  therefore each contain a power supply terminal VDD and ground terminal VSS. The SiP 10  further contains an external VDD terminal and external VSS terminal in order to connect the power supply and the ground to each of the applicable power supply terminals and applicable ground terminals. The applicable external VDD terminal connects to each VDD terminal on the SoC 101 , the memory A 102  and the memory B 103 . The applicable external VSS terminal connects to each VSS terminal on the SoC 101 , the memory A 102  and the memory B 103 . 
         [0067]    In order to communicate outside the SoC 101  and SiP 10 , the SoC 101  IO input terminal connects to the external IO input terminal on the SiP 10 ; and the IO output terminal on the SoC 101  connects to the external IO output terminal on SiP 10 . 
         [0068]    Moreover, in order to access the memory via the SoC 101 , the SoC 101  address terminal, command terminal, clock terminal, write data A terminal, and read data A terminal respectively connect to the memory A 102  address terminal, command terminal, clock terminal, write data terminal and read data terminal. The SoC 101  address terminal, command terminal, clock terminal, write data B terminal, and read data B terminal respectively connect to the memory B 103  address terminal, command terminal, clock terminal, write data terminal and read data terminal. 
         [0069]    To make the unique features of this invention easy to understand, the physical structure of SiP in the aforementioned technology and related problems are described while referring to the drawings. 
         [0070]      FIG. 2  is a drawing showing an internal view of the SiP 10 , where the SoC 101 , memory A 102 , memory B 103  are stacked by the aforementioned techniques. 
         [0071]    In  FIG. 2 , the SoC 201 , memory A 202  and memory B 203  respectively correspond to the SoC 101 , memory A 102  and memory B 103  in  FIG. 1 . 
         [0072]    A spacer  204  is a member for forming a space for connecting the bonding wires to the terminal side of the memory A 202 . 
         [0073]    A package substrate  205  is a member containing wiring (layers) mutually connecting to the SoC 201 , memory A  202 , memory B 203 ; and the SoC 201 , memory A 202 , memory B 203  and the external terminal  207  described later on. 
         [0074]    The external terminal  207  is a connection terminal for connecting the SiP 10  with an external device. 
         [0075]    A bonding wire  206  is wire for connecting the SoC 201 , memory A 202 , memory B 203  and the package substrate  205 . 
         [0076]    The package substrate and chips inside the SiP are currently mostly connected by bonding wire. 
         [0077]    Bonding wire connection techniques have already been established yet reducing the size of bonding pads formed on the chip that allow connecting bonding wires is difficult so using multiple bonding wires to connect the chips is also difficult, and this limits data transfer between chips. Moreover in order to connect the chip terminal side (surface where bonding wire is connected) by bonding wire to a chip blocked by another chip as in memory A 202  in  FIG. 2 , a space must be formed on the upper chip by using a spacer. Reducing the thickness of the entire SiP in order to make this space is difficult. 
         [0078]    This invention reduces power consumption and improves data transfer by switching communications between the SoC 101  and memory A 102  and memory B 102  to a three-dimensional coupling terminated within the SiP 10  and switches the power and ground connections from wire bonding to via (through) holes in order to eliminate the spacers required for three-dimensional coupling. 
         [0079]    The physical structure of the SiP 10  of this invention is described next while referring to the drawings. 
         [0080]      FIG. 3  is a drawing showing a horizontal view of the semiconductor integrated circuit mounted in the SiP 10  of the first embodiment of this invention. 
         [0081]    In the SiP 10  of this invention, the SoC 301 , and memory A 302  and memory B 303  are all stacked with the terminal side upward. Hereafter, in these specifications, the state where the terminal side of the integrated circuit is upwards is expressed as, “face-up”, and the state where the terminal side of the integrated circuit is downwards is expressed as “face-down”. 
         [0082]    The structure of SiP 10  is described first. 
         [0083]    The SiP 10  contains an SoC 301 , a memory A 302 , a memory B 303 , a package substrate  304 , an external terminal  305 , and bonding wires  306 - 308 . 
         [0084]    The SoC 301 , memory A 302 , memory B 303  respectively correspond to the SoC 101 , memory A 102 , and memory B 103  in  FIG. 1 . 
         [0085]    The memory A 302  contains a power supply via hole  309  and a ground via hole  310 . The applicable power supply via hole and applicable ground via. 
         [0086]    The memory B 303  contains a power supply via hole  311  and a ground via hole  312 . The applicable power supply via hole B 303 . 
         [0087]    The package substrate  304  is a member containing the SoC 301 , a memory A 302 , a memory B 303 , a package substrate  304 , and external terminal  305  described later on. 
         [0088]    The external terminal  305  is a connection terminal for connecting the SiP 10  to an external device. 
         [0089]    The bonding wire  306  is a bonding wire for connecting the SoC 301  and the package substrate  304 . The bonding wire  306  corresponds to a wire for connecting the VDD terminal, VSS terminal, IO input terminal, IO output terminal of the SoC 101 , to the respective external VDD terminal, external VSS terminal, external IO input terminal and external IO output terminal in  FIG. 1 . 
         [0090]    The bonding wire  307  is a bonding wire group for connecting the package substrate  304  to the power supply via hole  311  of memory B 303 . The bonding wire  307  corresponds to the wire between the external VDD terminal and the VDD terminal of memory B 103  in  FIG. 1 . 
         [0091]    The bonding wire  308  is a bonding wire for connecting the package substrate  304  to the ground via hole  312  of memory B 303 . The bonding wire  308  corresponds to the wire between the external VSS terminal and the VSS terminal of memory B 103  in  FIG. 1 . 
         [0092]    The three-dimensional coupling transmit terminal group  313  is three-dimensional coupling transmission terminals used by the SoC 301  for sending address, command, clock and write data to the memory A 302  and the memory B 303 . This terminal group  313  corresponds to the address terminal, command terminal clock terminal, write data A terminal, and write data B terminal of SoC 101  in  FIG. 1 . The three-dimensional coupling transmit terminal group is a coil for sending data by the inductive coupling method, and implemented using the semiconductor integrated circuit wiring layer. 
         [0093]    The three-dimensional coupling receive terminal group  314  is three-dimensional coupling receive terminals used by the SoC 301  for receiving read data from the memory A 302 . This terminal group  314  corresponds to the read data A terminal of SoC 101  in  FIG. 1 . The three-dimensional coupling receive terminal group  314  is a coil for receiving data by the inductive coupling method, and implemented using the semiconductor integrated circuit wiring layer. 
         [0094]    The three-dimensional coupling receive terminal group  315  is three-dimensional coupling receive terminals used by the SoC 301  for receiving read data from the memory B 303 . This terminal group  315  corresponds to the read data B terminal of SoC 101  in  FIG. 1 . 
         [0095]      FIG. 4  is a top view of the semiconductor integrated circuit mounted in the SiP 10  for the first embodiment of this invention. 
         [0096]    In this SiP 10  structure, the SoC 301  is stacked on the package substrate  304 , the memory A 302  is stacked on the SoC 301 , and the memory B 303  is stacked on the memory A 302 . 
         [0097]    The memory A 302  and the memory B 303  are identically shaped memories. The memory B 303  is mounted directly above the memory A 302  and so this memory A 302  does not appear in  FIG. 4 . 
         [0098]      FIG. 5  is a top view of the SoC 301 . 
         [0099]    A bonding pad group  5010  and the three-dimensional coupling terminal groups  313 - 315  are positioned on the SoC 301  terminal side. The bonding wire  306  is connected to the bonding pad group  5010 . 
         [0100]      FIG. 6  is a top view of the memory A 302 . 
         [0101]    The three-dimensional coupling terminal groups  316 ,  317 , and the power supply via hole  309  and ground via hole  310  are formed on the memory A  302  terminal side. 
         [0102]      FIG. 7  is a top view of the memory B 303 . 
         [0103]    The three-dimensional coupling terminal groups  318 ,  319  and the power supply via hole  311  and ground via hole  312  are formed on the memory B  303  terminal side. 
         [0104]    The relative positions of the SoC 301  and memory A 302  and memory B 303  are described next. 
         [0105]    First of all, the relation of the SoC 301  and the memory A 302  is described. 
         [0106]    In the first embodiment, the SoC 301  chip surface area is larger than the memory A 302  and the memory B 303 , so that a bonding pad group  5010  can be formed on the SoC 301  even if the memory A 302  and memory B 303  are directly stacked on the terminal side of SoC 301 . The memory A 302  is therefore stacked on the terminal side of SoC 301 , while avoiding the bonding pad group  5010 . 
         [0107]    The three-dimensional coupling between the SoC 301  and memory A 302  is described here while referring to the drawing. 
         [0108]      FIG. 8  is a drawing showing the terminal array of the three-dimensional coupling terminal groups  313 - 315  on SoC 301 . 
         [0109]    The three-dimensional coupling transmit terminal group  313  includes a Clock, CS, RW, A 4 -A 0 , and WD 7 -WD 0 . 
         [0110]    The three-dimensional coupling receive terminal group  314  includes RD 3 -RD 0 . 
         [0111]    The three-dimensional coupling receive terminal group  315  includes RD 7 -RD 4 . 
         [0112]      FIG. 9  is a drawing showing the terminal array for the three-dimensional coupling receive terminal group  316  and three-dimensional coupling transmit terminal group  317  on the memory A 302 . 
         [0113]    The three-dimensional coupling receive terminal group  316  includes a Clock, CS, RW, A 4 -A 0 , and WD 3 -WD 0 . Communication is performed via these terminals while paired with the respective Clock, CS, RW, A 4 -A 0 , and WD 3 -WD 0  terminals of three-dimensional coupling transmit terminal group  313 . 
         [0114]    The three-dimensional coupling transmit terminal group  317  includes RD 3 -RD 0 . Communication is performed via these terminals while paired with respective RD 3 -RD 0  of three-dimensional coupling receive terminal group  314 . 
         [0115]    Therefore the memory A 302  is stacked so that the three-dimensional coupling receive terminal group  316  is positioned directly above the three-dimensional coupling transmit terminal group  313  on the terminal side of SoC 301 . 
         [0116]    The three-dimensional coupling between the memory B 303  and the SoC 301  is described next while referring to the drawings. 
         [0117]      FIG. 10  is a drawing showing the terminal array for the three-dimensional terminal groups  318 - 319  on memory B 303 . 
         [0118]    The three-dimensional coupling receive terminal group  318  includes a Clock, CS, RW, A 4 -A 0 , and WD 3 -WD 0 . Communication is performed via these terminals while paired with the respective Clock, CS, RW, A 4 -A 0 , and WD 7 -WD 4  terminals of three-dimensional coupling transmit terminal group  313 . 
         [0119]    The three-dimensional coupling receive terminal group  319  includes the RD 3 -RD 0 . Communication is performed via these terminals while paired with respective RD 7 -RD 4  of three-dimensional coupling receive terminal group  314 . 
         [0120]    The memory B 303  is therefore stacked so that the three-dimensional coupling receive terminal group  318  is positioned directly above the three-dimensional coupling transmit terminal group  313  on the terminal side of SoC 301 . 
         [0121]    The SoC 301  containing the three-dimensional coupling terminals is in this way electrically coupled to the memory A 302 , memory B 303  containing three-dimensional coupling terminals and via holes by using the bonding wire  306 - 308  and the package substrate  304  to make up a SiP without using spacers. The memory A 302  enclosed by the SoC 301  and memory B 303  can therefore be connected to the power supply and ground while stacked without having to offset the memory A 302  and memory B 303 . 
         [0122]    Moreover, simultaneously sending (broadcasting) an address to multiple memory chips by utilizing a pair of address terminals in the SoC allows cutting the number of three-dimensional transmit coupling terminals mounted in the SoC by half compared to sending the addresses to individual memory chips between the SoC and memory without broadcasting. 
         [0123]    The semiconductor device of the first embodiment can therefore connect the power supply and ground terminals of the semiconductor chip to the power supply and ground terminals of the package by wire bonding wire and via holes; and connect the terminals utilized for communication outside the semiconductor chip package to the power supply and ground terminals of the package by wire bonding; and by using three-dimensional coupling technology to connect the terminals used for communication between the semiconductor chips, performs high-speed communication between chips by three-dimensional coupling, performs communication between the semiconductor chips and outside the package by physical wiring, and supplies power to the semiconductor chip. 
       Second Embodiment 
       [0124]    The second embodiment of this invention stacks the semiconductor integrated circuit face-down in the SiP. The physical structure of the SiP of the second embodiment is described next. The logical structure of the SiP of the second embodiment is identical to the logical structure of the SiP of the first embodiment. 
         [0125]      FIG. 11  is a drawing of the semiconductor integrated circuit mounted in the SiP of the second embodiment of this invention as seen from a horizontal view. 
         [0126]    The SoC 1101 , the memory A 1102  and the memory B 1103  are all mounted face-down in the SiP 20 . 
         [0127]    The structure of the SiP 20  is described first. 
         [0128]    The SiP 20  contains an SoC 1101 , the memory A 1102  and the memory B 1103 , the package substrate  1104 , the external terminal  1105 , and the micro-bumps  1106 - 1108 . 
         [0129]    The SoC 1101 , the memory A 1102 , and the memory B 1103  correspond to the respective SoC 1101 , memory A 102 , and memory B 103  in  FIG. 1 . 
         [0130]    The memory A 1102  of the second embodiment is identical to the memory A 302  of the first embodiment. 
         [0131]    The memory B 1103  of the second embodiment is identical to the memory B 303  of the first embodiment. 
         [0132]    The package substrate  1104  is a member with internal wiring for connecting the SoC 1101 , memory A 1102 , memory B 1103  with the external terminal  1105  described later on. 
         [0133]    The external terminal  1105  is a connection terminal for connecting the SiP 20  to an external device. 
         [0134]    A micro-bump  1106  is a bump group for connecting the SoC 1110  with the package substrate  1104 . The micro-bump  1106  corresponds to a wire for connecting the VDD terminal, VSS terminal, IO input terminal, IO output terminal on SoC 101  to the respective external VDD terminal, external VSS terminal, external IO input terminal, and external IO output terminal in  FIG. 1 . 
         [0135]    A micro-bump  1107  is a bump group for connecting the power supply via hole  1109  of SoC 1101  with the package substrate  1104 . The micro-bump  1107  corresponds to wiring between the VDD terminal on SoC 101  and the external VDD terminal as shown in  FIG. 1 . 
         [0136]    A micro-bump  1108  is a bump group for connecting the ground via hole  1110  of SoC 1101  and the package substrate  1104 . The micro-bump  1108  corresponds to wiring between the VSS terminal on SoC 101  and the external VSS terminal as shown in  FIG. 1 . 
         [0137]    The three-dimensional coupling transmit terminal group  1115  and the three-dimensional coupling receive terminal groups  1116 - 1117  respectively correspond to the three-dimensional coupling transmit terminal group  313  and the three-dimensional coupling receive terminal groups  314 - 315  of the first embodiment. 
         [0138]      FIG. 12  is a drawing showing a top view of the semiconductor integrated circuit mounted in the SiP 20 . 
         [0139]    The SiP 20  of the second embodiment employs a structure where the SoC 1101  is stacked on the package substrate  1104 , the memory A 1102  is stacked on the SoC 1101 , and the memory B 1103  is stacked on the memory A 1102 . 
         [0140]    The memory A 1102  and the memory B 1103  are identically shaped memories. The memory B 1103  is mounted directly above the memory A 1102  so that the memory A 1102  does not appear in  FIG. 12 . 
         [0141]      FIG. 13  is a top view of the SoC 1101 . 
         [0142]    The three-dimensional coupling transmit terminal group  1115  and the three-dimensional coupling receive terminal groups  1116 - 1117  and the power supply via holes  1109  and ground via holes  1110  are formed on the upper side of the SoC 1101 . 
         [0143]    The SoC 1101  of the second embodiment includes the power supply via holes  1109  and ground via holes  1110 . The applicable via hole is exposed on both sides of the SoC 1101 , and connects respectively to the internal power supply mesh and ground mesh of SpC 1101 . 
         [0144]    As described above, a SiP can be formed without using spacers, by utilizing a micro-bump  1106  and micro-bumps  1107 - 1108  to electrically couple an SoC 1110  containing three-dimensional coupling terminals, with a memory A 1102 , and memory B 1103  containing three-dimensional coupling terminals and via holes. 
         [0145]    The memory A 1102  enclosed between the SoC 1110  and the memory B 1103 , can also be stacked with no offset versus memory B 1103 . 
         [0146]    The semiconductor device of the second embodiment can therefore connect the power supply and ground terminals of the semiconductor chip to the power supply and ground terminals of the package by bumps and via holes; and connect terminals utilized for communication outside the semiconductor chip package with the power supply and ground terminals of the package by bumps; and by using three-dimensional coupling technology to connect the terminals used for communication between the semiconductor chips, performs high-speed communication between chips by three-dimensional coupling, performs communication between the semiconductor chips and outside the package by physical wiring, and supplies power to the semiconductor chip. 
       Third Embodiment 
       [0147]    In the first and second embodiments, three-dimensional communication was directly performed between the SoC and memory A, and also between the SoC and memory B. However the inductive coupling coefficient is inversely proportional to the square of the distance between the coils so three-dimensional coupling to couple the memory B to the SoC requires installing a large coil because of the long distance between the chips. This large coil reduces the number of installable coils, and does not allow raising the data transfer rate. 
         [0148]    The third embodiment described next is a method for communicating with a small coil by utilizing a chip with a signal relay function positioned in the intermediate layer. 
         [0149]    The SiP function of the third embodiment is identical to that of the first embodiment. 
         [0150]      FIG. 14  is a drawing showing a horizontal view of the semiconductor integrated circuit mounted on the SiP 210  in the third embodiment of this invention. 
         [0151]    The SoC 2101 , the memory A 2102 , and the memory B 2103  are all mounted face-up in the Sip 210 . 
         [0152]    The structure of the SiP 210  is described next. 
         [0153]    The SiP 210  includes the SoC 2101 , memory A 2102 , memory B 2103 , package substrate  2104 , external terminal  2105 , and bonding wires  2106 - 2108 . 
         [0154]    In the first embodiment the memory B 303  was stacked directly above the memory A 302 . However in the third embodiment, the memory B 2103  is offset (shifted) to the right versus the memory A 2102 , and the memory A 2102  is also offset (shifted) to the right versus the SoC 2101 . The amount of offset of memory B 2103  versus memory A 2102  is equivalent to the amount of offset of memory A 2102  versus the SoC 2102 . In the third embodiment that offset amount is hereafter expressed as D. 
         [0155]    The SoC 2101 , memory A 2102 , and memory B 2103  respectively correspond to SoC 101 , memory A 102 , and memory B 103  of  FIG. 1 . 
         [0156]    The memory A 2102  contains a power supply via hole  2109  and ground via hole  2110 . The applicable power supply via hole  2109  and applicable ground via hole  2110  are exposed on both surfaces of the memory A 2102 . 
         [0157]    In these specifications, the exposed portion of power supply via hole  2109  is hereafter called the power supply terminal for memory A 2102 . The exposed portion of the ground via hole  2110  is hereafter called the ground terminal for memory A 2102 . 
         [0158]    The power supply via hole  2109  bends inside the memory A 2102  and couples the power supply terminal on the upper side of memory A 2102 , with the power supply terminal on the lower side offset to the left just by a amount D from the applicable power supply terminal. The ground via hole  2110  in the same way, bends inside the memory A 2102  and couples the ground terminal on the upper side of memory A 2102  with the ground terminal on the lower side offset to the left just by an amount D from the applicable ground terminal. 
         [0159]    The memory B 2103  contains a power supply via hole  2111  and a ground via hole  2112 . The applicable power supply via hole  2111  and a groundviahole  2112  are exposed on both surfaces of the memory B 2103 . 
         [0160]    In these specifications, the exposed portion of power supply via hole  2111  is called the power supply terminal for memory B 2103 ; and the exposed portion of the ground via hole  2112  is called the ground terminal for memory B 2103 . 
         [0161]    The power supply via hole  2111  bends inside the memory B 2103 , and couples the power supply terminal on the upper side of memory B 2103  to the power supply terminal on the lower side offset to the left just by amount D from the applicable power supply terminal. The ground via hole  2112  in the same way, bends inside the memory B 2103 , and couples the ground terminal on the upper side of memory B 2103 , to the ground terminal on the lower side offset to the left just by a amount D from the applicable ground terminal. 
         [0162]    The package substrate  2104  is a member with internal wiring for connecting the SoC 2101 , memory A 2102 , memory B 2103 , and the external terminal  2105  described later on. 
         [0163]    The external terminal  2105  is a connection terminal for connecting the SiP 210  with an external device. 
         [0164]    The bonding wire  2106  is a bonding wire group for connecting the package substrate  2104  with the SoC 2101 . The bonding wire  2106  corresponds to a wire for connecting the VDD terminal, VSS terminal, IO input terminal and IO output terminal of SoC 101 , to the respective external VDD terminal, external VSS terminal, external IO input terminal, and external IO output terminal in  FIG. 1 . 
         [0165]    The bonding wire  2107  is a bonding wire group for connecting the power supply via hole  2111  of memory B 2103  with the package substrate  2104 . The bonding wire  2107  corresponds to the wiring between the external VDD terminal and VDD terminal of memory B 103 . 
         [0166]    The bonding wire  2108  is a bonding wire group for connecting the package substrate  2104  to the ground via hole  2112  of the memory B 2103 . The bonding wire  2108  corresponds to the wiring between the external VSS terminal and the VSS terminal of memory B 103  in  FIG. 1 . 
         [0167]    The three-dimensional coupling transmit terminal group  2113  is a three-dimensional coupling transmit terminal group for transmitting address, command, and write data from the SoC 2101  to the memory A 2102 . The three-dimensional coupling transmit terminal group  2113  corresponds to the address terminal, command terminal, write data A terminal, and write data B terminal of SoC 2101  in  FIG. 1 . 
         [0168]    The three-dimensional coupling receive terminal group  2114  is a three-dimensional coupling receive terminal group for the SoC 2101  to receive read data sent from the memory A 2102 . In the third embodiment, the memory A 2102  relays the read data output from the memory B 2103  and therefore corresponds to the read data A terminal and the read data B terminal of SoC 2101  in  FIG. 1 . 
         [0169]      FIG. 15  is a top view showing the semiconductor integrated circuit mounted in the SiP 210 . 
         [0170]    The SiP 210  employs a structure where the SoC 2101  is stacked on the package substrate  2104 , the memory A 2102  is stacked on the SoC 2101 , and the memory B 2103  is stacked on the memory A 2102 . 
         [0171]      FIG. 16  is a top view of the SpC 2101 . 
         [0172]    The three-dimensional coupling terminal groups  2113 - 2114  and bonding wire group  2301  are formed on the upper surface of the SoC 2101 . A bonding wire  2106  connects to the bonding pad group  2301 . 
         [0173]      FIG. 17  is a top view of the memory A 2102 . 
         [0174]    The three-dimensional coupling terminal groups  2115 - 2118  and power supply via hole  2109  and ground via hole  2110  are formed on the terminal side of the memory A 2102 . 
         [0175]    The three-dimensional coupling terminal group  2117  is formed at a position offset to the right just by an amount D from the three-dimensional coupling terminal group  2115 . 
         [0176]    The three-dimensional coupling terminal group  2118  is formed at a position offset to the right just by an amount D from the three-dimensional coupling terminal group  2116 . 
         [0177]    The three-dimensional coupling terminal group  2117  resends the signal received by the three-dimensional coupling terminal group  2115 . 
         [0178]    The three-dimensional coupling terminal group  2116  resends the signal received by the three-dimensional coupling terminal group  2118 . 
         [0179]      FIG. 18  is a top view of the memory B 2103 . 
         [0180]    The three-dimensional coupling terminal groups  2119 - 2122  and power supply via holes  2111  and the ground via holes  2112  are formed on the terminal side of the memory B 2103 . 
         [0181]    The three-dimensional coupling terminal group  2121  is formed at a position offset to the right just by an amount D from the three-dimensional coupling terminal group  2119 . 
         [0182]    The three-dimensional coupling terminal group  2122  is formed at a position offset to the right just by an amount D from the three-dimensional coupling terminal group  2120 . 
         [0183]    The relative positions of the memory A 2102 , memory B 2103  and SoC 2101  are described next. 
         [0184]    The relative positions of the SoC 2101  and memory A 2102  is described first. 
         [0185]    In the third embodiment, the memory A 2102  is stacked offset to the right by an amount D relative to the SoC 2101 , so that the bonding pad group  2301  can be installed. 
         [0186]    The three-dimensional coupling between the SoC 2101  and the memory A 2102  is described here while referring to the drawing. 
         [0187]      FIG. 19  is a drawing showing the terminal array of the three-dimensional coupling receive terminal group  2114  and three-dimensional coupling transmit terminal group  2113  of SoC 2101 . 
         [0188]    The three-dimensional coupling transmit terminal group  2113  includes a Clock, CS, RW, A 4 -A 0 , WD 7 -WD 0 . The three-dimensional coupling receive terminal group  2114  contains an RD 7 -RD 0 . 
         [0189]      FIG. 20  is a drawing showing the terminal arrays of the three-dimensional coupling transmit terminal groups  2116 ,  2117  and the three-dimensional coupling receive terminal groups  2115 ,  2118  of memory A 2102 . 
         [0190]    The three-dimensional coupling receive terminal group  2115  includes a Clock, CS, RW, A 4 -A 0 , and WD 7 -WD 0 . Communication is performed via these terminals while paired with the respective Clock, CS, RW, A 4 -A 0 , and WD 7 -WD 0  of the three-dimensional coupling transmit terminal group  2313 . 
         [0191]    The three-dimensional coupling transmit terminal group  2116  includes RD 7 -RD 0 . These terminals communicate while paired with the respective RD 7 -RD 0  terminals of three-dimensional coupling receive terminal group  2114 . 
         [0192]    On the memory A 2102 , the three-dimensional coupling receive terminal group  2115  is stacked at a position overlapping the three-dimensional coupling transmit terminal group  2113  on the terminal side of SoC 2101 . 
         [0193]    The three-dimensional coupling transmit terminal group  2117  includes a Clock, CS, RW, A 4 -A 0 , WD 7 -WD 0 . 
         [0194]    The three-dimensional coupling receive terminal group  2118  includes RD 7 -RD 0 . 
         [0195]    The three-dimensional coupling of the memory A 2102  to the memory B 2103  is described next while referring to the drawing. 
         [0196]      FIG. 21  is a drawing showing the terminal arrays of the three-dimensional coupling transmit terminal groups  2120 ,  2121  and the three-dimensional coupling receive terminal groups  2119 ,  2122  of memory B 2103 . 
         [0197]    The three-dimensional coupling receive terminal group  2119  includes a Clock, CS, RW, A 4 -A 0 , and WD 7 -WD 0 . Communication is performed via these terminals while paired with the respective Clock, CS, RW, A 4 -A 0 , and WD 7  of three-dimensional coupling transmit terminal group  2117 . 
         [0198]    The three-dimensional coupling transmit terminal group  2120  includes RD 7 -RD 0 . These terminals communicate while paired with the respective RD 7 -RD 0  terminals of three-dimensional coupling receive terminal group  2118 . 
         [0199]    The third embodiment does not utilize the three-dimensional coupling receive terminal group  2122  and the three-dimensional coupling transmit terminal group  2121 . 
         [0200]    Therefore on the memory B 2103 , the three-dimensional coupling receive terminal group  2119  is stacked at a position directly above the three-dimensional coupling transmit terminal group  2117  on the memory A 2102  terminal side. 
         [0201]    A SiP can therefore be formed in this way without using spacers, by electrically coupling the SoC 2101 , memory A 2102 , memory B 2103  inside the SiP 210  by bonding wires  2106 - 2108 . 
         [0202]    Moreover, in the third embodiment, communication by three-dimensional coupling was limited entirely to adjacent chips by offset-stacking the semiconductor integrated circuits, and by installing the three-dimensional the same as this offset amount. 
         [0203]    Small three-dimensional transmit coils and receive coils could therefore be used in the third embodiment. 
         [0204]    Moreover, since all chips in the third embodiment are stacked with an offset, a space can be provided within the Sip for installing bonding wires and bonding pads on all chips. 
         [0205]    The memory chip design cost can also be kept low by using an identical design for the chips in the memory A 2102  and the memory B 2103 . 
         [0206]    Also, by arraying the terminals or terminal groups utilized for the three-dimensional connection in the sequence of transmit-receive-receive-transmit, and by stacking them with an offset just by the width required for wire bonding, so that a minimum of semiconductor types can be used, and semiconductor chip development costs in this way held to a minimum. 
       Fourth Embodiment 
       [0207]    The fourth embodiment is described using as an example, the SiP 10  of the first embodiment with the memory A, memory B, and a SoC stacked in that order of nearness to the package substrate. 
         [0208]    The physical structure of the SiP of the fourth embodiment is described next. The logical structure of the SiP of the fourth embodiment is identical to the structure of the first embodiment. 
         [0209]      FIG. 22  is a drawing showing the semiconductor integrated circuit mounted in the SiP 30  as seen from a horizontal view. 
         [0210]    The SoC 3101 , the memory A 3102 , and the memory B 3103  are all stacked face-up in the SiP 30 . 
         [0211]    The structure of the SiP 30  is described first. 
         [0212]    The SiP 30  includes the SoC 3101 , memory A 3102 , memory B 3103 , package substrate  3104 , external terminal  3105 , and the bonding wires  3106 - 3108 . 
         [0213]    The SoC 3101 , memory A 3102 , and memory B 3103  correspond respectively to the SoC 101 , memory A 102 , memory B 103  of  FIG. 1 . 
         [0214]    The memory A 3102  of the fourth embodiment is identical to the memory A 302  of the first embodiment. 
         [0215]    The memory B 3103  of the fourth embodiment is identical to the memory B 303  of the first embodiment. 
         [0216]    The package substrate  3104  is a member with internal wiring for connecting to the SoC 3101 , memory A 3102 , memory B 3103 , and the external terminal  3105  described later on. 
         [0217]    The external terminal  3105  is a connection terminal for connecting the SiP 30  with an external device. 
         [0218]    The bonding wire  3106  is a bonding wire group for connecting the package substrate  3104  to the SoC 3101 . The bonding wire  3106  corresponds to wire for connecting the VDD terminal, VSS terminal, IO input terminal and IO output terminal of SoC 101  in  FIG. 1  to the respective external VDD terminal, external VSS terminal, external IO input terminal, and external IO output terminal of  FIG. 1 . 
         [0219]    The bonding wire  3107  is a bonding wire group for connecting the package substrate  3104  with the power supply via holes  3109  of SoC 3101 . The bonding wire  3107  corresponds to wiring between the external VDD terminal and the VDD terminal of SoC 101  in  FIG. 1 . 
         [0220]    The bonding wire  3108  is a bonding wire group for connecting the package substrate  3104  with the ground via holes  3112  of SoC 3101 . The bonding wire  3108  corresponds to wiring between the external VSS terminal and the VSS terminal of SoC 101  in  FIG. 1 . 
         [0221]    The three-dimensional coupling transmit terminal group  3115  and the three-dimensional coupling receive terminal groups  3116 - 3117  respectively correspond to the three-dimensional coupling transmit terminal group  313  and the three-dimensional coupling receive terminal groups  314 - 315  of the first embodiment. 
         [0222]      FIG. 23  is a top view of the semiconductor integrated circuits stacked in the SiP 30 . 
         [0223]    The SiP 30  of the fourth embodiment employs a structure where the memory A 3102  is stacked on the package substrate  3104 , the memory B 3103  is stacked on the memory A 3102 , and the SoC 3101  is stacked on the memory B 3103 . 
         [0224]    The memory A 3102  and the memory B 3103  are identical shaped memories. The memory B 3103  is mounted directly above the memory A 3102  so that the memory A 3102  does not appear in  FIG. 23 . 
         [0225]      FIG. 24  is a top view of the SoC 3101 . 
         [0226]    The three-dimensional coupling transmit terminal group  3115 , the three-dimensional coupling receive terminal groups  3116 - 3117 , the power supply via holes  3109  and the ground via holes  3112  are formed on the upper side of the SoC 3101 . 
         [0227]    The relative positions of the SoC 3101  and memory A 3102 , and memory B 3103  are described next. 
         [0228]    The three-dimensional coupling between the SoC 3101  and memory A 3102 , as well as between the SoC 3101  and the memory B 3103  are identical to the three-dimensional coupling of the first embodiment. 
         [0229]    A SiP can therefore be formed without utilizing spacers as described above, by using the bonding wires  3106 - 3108  to electrically couple the SoC 3101 , the memory A 3102 , and the memory B  3103  containing the three-dimensional terminals. 
         [0230]    A particular feature of the fourth embodiment is that the SoC 3101  is positioned at the upper most layer, and the bonding pad is installed over the entire surface of the terminal side of SoC 3101  so that SoC (System-on-chip) containing a larger number of terminals can be stacked. 
       Fifth Embodiment 
       [0231]    In the example in the fifth embodiment, the memory A, memory B and SoC in the SiP 10  of the first embodiment, are mounted in that order of closeness to the package substrate. 
         [0232]    The physical structure of the SiP of the fifth embodiment is described next. The logical structure of the SiP of the fifth embodiment is identical to the structure of the first embodiment. 
         [0233]    The SiP 40  of the present invention is described next while referring to the drawings. 
         [0234]      FIG. 25  is a drawing showing the semiconductor integrated circuits mounted in the SiP 40  as seen from a horizontal view. 
         [0235]    The SoC 4101  is positioned face-up, and the memory A 1401  and memory B 4103  are both stacked face-down in the SiP 40 . 
         [0236]    The structure of the SiP 40  is described first. 
         [0237]    The SiP 40  includes the SoC 4101 , memory A 4102 , memory B 4103 , package substrate  4104 , external terminal  4105 , bonding wire  4106 , and micro-bumps  4107 - 4108 . 
         [0238]    The SoC 4101 , memory A 4102 , and memory B 4103  correspond respectively to the SoC 101 , memory A 102 , and memory B 103  in  FIG. 1 . 
         [0239]    The SoC 4101  contains a power supply via hole  4116 , and a ground via hole  4117 . The applicable power supply via hole  4116  and ground via hole  4117  are respectively formed on the lower surface of the SoC 4101 . 
         [0240]    The memory A 4102  of the fifth embodiment is identical to the memory A 302  of the first embodiment. 
         [0241]    The memory B 4103  of the fifth embodiment is identical to the memory B 303  of the first embodiment. 
         [0242]    The package substrate  4104  is a member containing internal wiring for connecting the SoC 4101 , memory A 4102 , memory B 4103  and the external terminal  4105  described later on. 
         [0243]    The external terminal  4105  is a connection terminal for connecting the SiP 40  to an external device. 
         [0244]    The bonding wire  4106  is a bonding wire group for connecting the SoC 4101  with the package substrate  4104 . The bonding wire  4106  corresponds to the wiring for connecting the IO input terminal, IO output terminal of SoC 101  to the respective external IO input terminal, external IO output terminal. 
         [0245]    The micro-bump  4107  is a micro-bump group for connecting the package substrate  4104  with the power supply via hole  4116  of the SoC 4101 . The micro-bump  4107  corresponds to wiring between the external VDD terminal and the VDD terminal of the SoC 101  in  FIG. 1 . 
         [0246]    The micro-bump  4108  is a micro-bump group for connecting the package substrate  4104  with the ground via hole  4117  of the SoC 4101 . The micro-bump  4108  corresponds to wiring between the external VSS terminal and the VSS terminal of the SoC 101  in  FIG. 1 . 
         [0247]    The three-dimensional coupling transmit terminal group  4113  and the three-dimensional coupling receive terminal groups  4114 - 4115  respectively correspond to the three-dimensional coupling transmit terminal group  313  and the three-dimensional coupling receive terminal groups  314 - 315  of the first embodiment. 
         [0248]      FIG. 26  is a drawing showing a top view of the SiP 40  The SiP 40  of the fifth embodiment employs a structure where the memory A 4102  is stacked on the package substrate  4104 , the memory B 4103  is stacked on the memory A 4102 , and the SoC 4101  is stacked on the memory B 4103 . 
         [0249]    The memory A 4102  and the memory B 4103  are identical-shaped memories. The memory B 4103  is mounted directly above the memory A 4102  so that the memory A 4102  does not appear in the upper view drawing of SiP 40 . 
         [0250]    The three-dimensional coupling transmit terminal group  4113  and the three-dimensional coupling receive terminal groups  4114 - 4115  and bonding pad group  4201  are formed on the upper side of the SoC 4101 . 
         [0251]    The relative positions of the memory A 4102 , the memory B 4103  and the SoC 4101  are described next. 
         [0252]    The three-dimensional coupling between the memory A 4102  and SoC 4101 , and between the SoC 4101  and memory B 4103  are identical to the three-dimensional coupling of the first embodiment. 
         [0253]    The SoC 4101  is stacked at a position where the power supply via hole  4116  of SoC 4101  is in contact with the power supply via hole  4110  of memory B 4103 ; and the ground via hole  4117  of SoC 4101  is in contact with the ground via hole  4112  of memory B 4103 . 
         [0254]    The SiP can therefore be formed without spacers as described above by utilizing the bonding wire  4106  to electrically couple the SoC 4101 , the memory A 410  and memory B 4103  containing the three-dimensional coupling terminals and via holes. 
       Sixth Embodiment 
       [0255]      FIG. 27  is a block diagram showing the functional connection relations of the system-in-package (hereafter described as SiP) of the sixth embodiment. 
         [0256]    The SiP 50  contains the SoCA 501 , the SoCB 502 , the CoCC 503 , and the SoCD 504  as well as a function to communicate outside the SiP 50 . The SoCA 501 , the SoCB 502 , the SoCC 503 , and the SoCD 504  perform communications by loading and executing the program stored in the respective internal memories. The SoCA 501 , the SoCB 502 , the CoCC 503 , and the SoCD 504  also communicate with each other and operate linked to each other. 
         [0257]    The SoCA 501  as well as the SoCB 502  and SoCC 503  and the SoCD 504  are semiconductor integrated circuits formed on a semiconductor substrate such as single crystal silicon for forming conventional CMOS (complementary MOS transistors) or bipolar transistors by semiconductor integrated circuit technology. The power supply and ground are connected to these circuits during operation. 
         [0258]    The SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  therefore each contain a power supply terminal VDD and ground terminal VSS. Moreover, the SiP 50  contains an external power supply terminal and an external ground terminal for connecting the respective power supply and ground to the applicable power supply terminal and applicable ground terminal. The power supply terminals for the SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  each connect to the applicable external power supply terminal. Moreover, the ground terminals for the SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  each connect to the applicable external ground terminal. 
         [0259]    The SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  each contain an IO input terminal and an IO output terminal for communicating outside the SiP 50 . 
         [0260]    In order for the SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  to communicate outside the SiP 50 , the IO input terminal of SoCA 501  connects to the external IO input terminal A of SiP 50 ; the TO output terminal of SoCA 501  connects to the external output terminal A of SiP 50 ; the IO input terminal of SoCB 502  connects to the external IO input terminal B of SiP 50 ; The IO output terminal of SoCB 502  connects to the external IO output terminal B of SiP 50 ; the IO input terminal of SoCC 503  connects to the external IO input terminal C of SiP 50 ; the IO output terminal of SoCC 503  connects to the external IO output terminal of SiP 50 ; the IC input terminal of SoCD 504  connects to the external IO input terminal D of SiP 50 ; and the IC output terminal of SoCD 504  connects to the external IO output terminal D of SiP 50 . 
         [0261]    Moreover, the SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  respectively contain a comm. input 1  terminal and a comm. output  1  terminal and comm. input  2  terminal and comm. output  2  terminal for communicating with each other. 
         [0262]    A total of eight terminals (bit  7 -bit  0 ) make up these communication input terminals and communication output terminals. 
         [0263]    In order for the SoCA 501 , SoCB 502 , SoCC 503  and SoCD 504  to communicate with each other, the comm. output terminal  2  of SoCA 501  connects to the comm. input terminal  1  of SoCB 502 ; the comm. input terminal  2  of SoCA 501  connects to the comm. output terminal  1  of SoCB 502 ; the comm. output terminal  2  of SoCB 502  connects to the comm. input terminal  1  of SoCC 503 ; the comm. input terminal  2  of SoCB 502  connects to the comm. output terminal  1  of SoCC 503 ; and the comm. output terminal  2  of SoCC 503  connects to the comm. input terminal  1  of SoCC 504 ; and the comm. input terminal  2  of SoCC 503  connects to the comm. output terminal  1  of SoCC 504 . 
         [0264]    In the sixth embodiment, data transfer performance is improved and power consumption is reduced by utilizing three-dimensional coupling for communication between the SoCA 501 , and SoCB 502 , and SoCC 503  and SoCD 504  connected within the SiP 50 . 
         [0265]      FIG. 28  is a drawing showing the semiconductor integrated circuits mounted in the SiP 50  as seen from a horizontal view. 
         [0266]    In the sixth embodiment, the SoCA 5201 , SoCB 5202 , and SoCC 5203  and SoCD 504  are stacked face-up within the SiP 50 . 
         [0267]    The structure of the SiP 50  is described next. 
         [0268]    The SiP 50  includes an SoCA 5201 , SoCB 5202 , SoCC 5203 , and SoCD 5204 , package substrate  5205 , external terminal  5206  and bonding wires  5207 - 5210 . 
         [0269]    The SoCA 5201 , SoCB 5202 , SoCC 5203 , and SoCD 5204  correspond respectively to the SoCAS 01 , SoCB 502 , SoCC 503  and SoCD 504  in  FIG. 27 . 
         [0270]    The package substrate  5205  is a member with internal wiring for connecting the latter described external terminal  5206  with the SoCA 5201 , SoCB 5202 , SoCC 5203 , and SoCD 5204 . 
         [0271]    The external terminal  5206  is a connection terminal for connecting the SiP 50  to an external device. 
         [0272]    The bonding wire  5207  is a bonding wire group for connecting the package substrate  5205  to the SoCA 5201 . The bonding wire  5207  corresponds to wiring for connecting the VDD terminal, VSS terminal, IC input terminal, and IO output terminal of SoCA 501  to the respective external VDD terminal, external VSS terminal, external IO input A terminal, and external IO output A terminal in  FIG. 27 . 
         [0273]    The bonding wire  5208  is a bonding wire group for connecting the package substrate  5205  to the SoCB 5202 . The bonding wire  5208  corresponds to wiring for connecting the VDD terminal, VSS terminal, IO input terminal, and IO output terminal of SoCB 502  in  FIG. 27  to the respective external VDD terminal, external VSS terminal, external IO input B terminal, and external IO output B terminal in  FIG. 27 . 
         [0274]    The bonding wire  5209  is a bonding wire group for connecting the package substrate  5205  to the SoCC 5203 . The bonding wire  5209  corresponds to wiring for connecting the VDD terminal, VSS terminal, IO input terminal, and IC output terminal of SoCC 503  in  FIG. 27  to the respective external VDD terminal, external VSS terminal, external IO input C terminal, and external IO output C terminal in  FIG. 27 . 
         [0275]    The bonding wire  5210  is a bonding wire group for connecting the package substrate  5205  to the SoCD 5204 . The bonding wire  5210  corresponds to wiring for connecting the VDD terminal, VSS terminal, IO input terminal, and IO output terminal of SoCD 504  to the respective external VDD terminal, external VSS terminal, external IO input D terminal, and external IO output D terminal in  FIG. 27 . 
         [0276]    The three-dimensional coupling transmit terminal group A 5211  and three-dimensional coupling receive terminal group A 5212  are three-dimensional coupling terminal groups respectively equivalent to the comm. output  2  terminal and comm. input  2  terminal of SoCA 501  in  FIG. 27  and are utilized by the SoCA 501  for communicating with the SoCB 5202 . 
         [0277]    The three-dimensional coupling receive terminal group A 5213  and the three-dimensional coupling transmit terminal group A 5214  are a three-dimensional coupling terminal group and respectively correspond to the comm. input  1  terminal and the comm. output  2  terminal of SoCA 501  in  FIG. 27 . 
         [0278]    The three-dimensional coupling transmit terminal group B 5215  and the three-dimensional coupling receive terminal group B 5216  are the three-dimensional coupling terminal group and respectively correspond to the comm. output  2  terminal and the comm. input  2  terminal of SoCA 502  in  FIG. 27 , and are utilized by the SoCB 5202  for communicating with the SoCC 5203 . 
         [0279]    The three-dimensional coupling receive terminal group B 5217  and the three-dimensional coupling transmit terminal group B 5218  are the three-dimensional coupling terminal group and respectively correspond to the comm. input  1  terminal and the comm. output  1  terminal of SoCB 502  in  FIG. 27 , and are utilized by the SoCB 5202  for communicating with the SoCA 5201 . 
         [0280]    The three-dimensional coupling transmit terminal group C 5219  and the three-dimensional coupling receive terminal group C 5220  are a three-dimensional coupling terminal group and respectively correspond to the comm. output  2  terminal and the comm. input  2  terminal of the SoCC 503  in  FIG. 27 ; and are utilized by the SoCC 5203  for communicating with the SoCAD 204 . 
         [0281]    The three-dimensional coupling receive terminal group C 5221  and the three-dimensional coupling transmit terminal group C 5222  are the three-dimensional coupling terminal group and respectively correspond to the comm. input  1  terminal and the comm. output  1  terminal of SoCC 503  in  FIG. 27 , and are utilized by the SoCC 5203  for communicating with the SoCB 5202 . 
         [0282]    The three-dimensional coupling transmit terminal group D 5223  and the three-dimensional coupling receive terminal group D 5224  are the three-dimensional coupling terminal group and respectively correspond to the comm. output  2  terminal and the comm. input  2  terminal of the SoCD 504  in  FIG. 27 . 
         [0283]    The three-dimensional coupling receive terminal group D 5225  and the three-dimensional coupling transmit terminal group D 5226  are the three-dimensional coupling terminal group and respectively correspond to the comm. input  1  terminal and the comm. output  1  terminal of SoCD 504  in  FIG. 27 . 
         [0284]      FIG. 29  is a top view of the semiconductor integrated circuits stacked in the SiP 50 . 
         [0285]    The SiP 50  of the sixth embodiment employs a structure where the SoCD 5204  is stacked on the package substrate  5205 , the SoCC 5203  is stacked on the SoCD 5204 , the SoCB 5202  is stacked on the SoCC 5203 , and the SoCA 5201  is stacked on the SoCB 5202 . 
         [0286]      FIG. 30  is a top view of the SoCA 5201  of the sixth embodiment. 
         [0287]    A three-dimensional coupling terminal group A 5211 - 5214  and a bonding pad group A 5401  are formed on the upper side of the SoCA 5201 . A bonding wire  5207  is connected to the bonding pad group A 5401 . 
         [0288]    The SoCB 5202 , the SoCC 5203 , SoCD 5204  are SoC (System-on-chip) with the same structure as the SoCA 5201 . Other than the number attached to the connected bonding wires and three-dimensional coupling terminal groups, the structure is identical to the SoCA 5201 . 
         [0289]    In the sixth embodiment, the X direction is toward the left and right in  FIG. 28 . The direction parallel to the package substrate  5205  and perpendicular to the left and right directions in  FIG. 28  is called the Y direction. 
         [0290]    Moreover, the direction to the right of the X direction is here set as the positive direction, and the Y direction toward you when viewing  FIG. 28  is set as the positive direction. 
         [0291]    The three-dimensional coupling between the SoCA 5201  and the SoCB 5202  is described next while referring to the drawings. 
         [0292]    The three-dimensional coupling transmit terminals and the three-dimensional coupling receive terminals are referred to by the general name of three-dimensional coupling terminals. 
         [0293]      FIG. 31  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups A 5211 - 5214  on the SoCA 5201 .  FIG. 32  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups B 5215 - 5218  on the SoCB 5202 . 
         [0294]    The three-dimensional coupling transmit terminal group A 5211  contains bit  7 -bit  0  of T 2 . 
         [0295]    The three-dimensional coupling receive terminal group A 5212  contains bit  7 -bit  0  of R 2 . 
         [0296]    The three-dimensional coupling receive terminal group A 5213  contains bit  7 -bit  0  of R 1 . 
         [0297]    The three-dimensional coupling transmit terminal group A 5214  contains bit  7 -bit  0  of T 1 . 
         [0298]    The three-dimensional coupling receive terminal group A 5213  is formed at a position offset in the X direction by just an amount X, and offset in the Y direction by just an amount Y relative to the three-dimensional coupling transmit terminal group A 5211 . 
         [0299]    The three-dimensional coupling transmit terminal group A 5214  is formed at a position offset in the X direction by just an amount X, and offset in the Y direction by just an amount Y relative to the three-dimensional coupling receive terminal group A 5212 . 
         [0300]    The three-dimensional coupling transmit terminal group B 5215  contains bit  7 -bit  0  of T 2 . 
         [0301]    The three-dimensional coupling receive terminal group B 5216  contains bit  7 -bit  0  of R 2 . 
         [0302]    The three-dimensional coupling receive terminal group B 5217  contains bit  7 -bit  0  of R 1 . 
         [0303]    The three-dimensional coupling transmit terminal group B 5218  contains bit  7 -bit  0  of T 1 . 
         [0304]    The three-dimensional coupling receive terminal group B 5217  is formed at a position offset in the X direction by just an amount X, and offset in the Y direction by just an amount Y relative to the three-dimensional coupling transmit terminal group B 5215 . 
         [0305]    The three-dimensional coupling transmit terminal group B 5218  is formed at a position offset in the X direction by just an amount X, and offset in the Y direction by just an amount Y relative to the three-dimensional coupling receive terminal group B 5216 . 
         [0306]    When the SoCA 5201  is offset in the X direction, and offset in the Y direction relative to the SoCB 5202  and is stacked above the SoCB 5202 , then the bits from bit  7  to bit  0  of T 2  on SoCA 5201  are respectively positioned directly above the bits from bit  7  to bit  0  of R 1  on the SoCB 5202 . Transmission is in this way implemented from the SoCB 5201  to the SoCA 5202 . 
         [0307]    When the SoCA 5201  is offset in the same way in the X direction by just an amount X, offset in the Y direction by just an amount Y relative to the SoCB 5202  and is stacked above the SocB 5202 , then the bits from bit  7 -bit  0  of R 2  on SoCA 5201  are respectively positioned directly above the bits from bit  7 -bit  0  of T 1  on the SoCB 5202 , so that transmission is in this way implemented from SoCB 5202  to SoCA 5201 . 
         [0308]    The three-dimensional coupling between the SoCB 5202  and the SoCC 5203  are described next while referring to the drawing. 
         [0309]      FIG. 33  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups C 5219 - 5222  on SoCC 5203 . 
         [0310]    The three-dimensional coupling transmit terminal group C 5219  contains bit  7 -bit  0  of T 2 . 
         [0311]    The three-dimensional coupling receive terminal group C 5220  contains bit  7 -bit  0  of R 2 . 
         [0312]    The three-dimensional coupling receive terminal group C 5221  contains bit  7 -bit  0  of R 1 . 
         [0313]    The three-dimensional coupling transmit terminal group C 5222  contains bit  7 -bit  0  of T 1 . 
         [0314]    The three-dimensional coupling receive terminal group C 5221  is formed at a position offset in the X direction just be amount X, and offset in the Y direction just by an amount Y relative to the three-dimensional coupling transmit terminal group C 5219 . 
         [0315]    The three-dimensional coupling transmit terminal group C 5222  is formed at a position offset in the X direction just by amount X, and offset in the Y direction just by an amount Y relative to the three-dimensional coupling receive terminal group C 5220 . 
         [0316]    When the SoCB 5202  is offset in the X direction just be amount X, and offset in the Y direction just by an amount Y relative to the SoCC 5203  and stacked above the SoCC 5203 , bits from bit  7  to bit  0  of T 2  on SoCB 5202  are respectively positioned directly above the bits from bit  7  to bit  0  of R 1  on the SoCC 5203 . Transmission is in this way carried out from the SoCB 5202  to the SoCC 5203 . 
         [0317]    When the SoCB 5202  is offset in the same way in the X direction just by an amount X and offset in the Y direction just by an amount Y relative to the SoCC 5203  and stacked above it, then the bits from bit  7  to bit  0  of R 2  on the CB 5202  are positioned directly above the bits from bit  7  to bit  0  of T 1  on the SoCC 5203 . Transmissions are in this way made from the SoCC 5203  to the SoCB 5202 . 
         [0318]    The three-dimensional coupling between the SoCC 5203  and the SoCD 5204  is described next while referring to the drawing. 
         [0319]      FIG. 34  is a drawing showing the terminal arrays of the three-dimensional coupling terminal groups D 5223 - 5226  on SoCD 5204 . 
         [0320]    The three-dimensional coupling transmit terminal group D 5223  contains bit  7 -bit  0  of T 2 . 
         [0321]    The three-dimensional coupling receive terminal group D 5224  contains bit  7 -bit  0  of R 2 . 
         [0322]    The three-dimensional coupling receive terminal group D 5225  contains bit  7 -bit  0  of R 1 . 
         [0323]    The three-dimensional coupling transmit terminal group D 5226  contains bit  7 -bit  0  of T 1 . 
         [0324]    The three-dimensional coupling receive terminal group D 5225  is formed at a position offset in the X direction just by an amount X and offset in the Y direction just by an amount Y relative to the three-dimensional coupling transmit terminal group D 5223 . 
         [0325]    The three-dimensional coupling transmit terminal group D 5226  is formed at a position offset in the X direction just by an amount X and offset in the Y direction just by an amount Y relative to the three-dimensional coupling receive terminal group D 5224 . 
         [0326]    When the SoCC 52 C 3  is offset in the X direction just by an amount X and offset in the Y direction just by an amount Y relative to the SoCD 5204  and stacked over the SoCD 5204 , bits from bit  7  to bit  0  of T 2  on SoCC 5203  are respectively positioned directly over the bits from bit  7  to bit  0  of R 1  on the SoCD 5204 . Transmission is in this way carried out from the SoCC 5203  to the SoCD 5204 . 
         [0327]    In the same way, when the SoCC 5203  is offset and stacked in the X direction just by an amount X and n the Y direction just by an amount Y relative to the SoCD 5204 , the bits from bit  7  to bit  0  of T 2  on SoCC 5203  are respectively positioned directly over the bits from bit  7  to bit  0  of T 1  of SoCD 5204 . Transmission is in this way carried out from the SoCD 5204  to the SoCC 5203 . 
         [0328]    The sixth embodiment of this invention can stack multiple chips having the same design by positioning the chips separate from each other while aligned to match the offset when stacking the three-dimensional coupling receive terminals, and three-dimensional coupling transmit terminals paired with the applicable terminals. The chip types can in this way be held to a minimum and chip development costs and be kept low. 
         [0329]    In particular by offsetting the chips in the two X and Y directions during stacking, even chips other than the topmost stacked chip can be arranged so that bonding pads are formed across two sides of the chip. 
         [0330]    The sixth embodiment was described using an example where integrated circuits with the identical functions and structure were stacked. However, the shape (contour) of the chips for stacking need not be a problem if the three-dimensional coupling receive terminals, and three-dimensional coupling transmit terminals paired with the applicable terminals are aligned to match the offset of the semiconductor integrated circuits during the stacking. 
         [0331]    Many types of semiconductor integrated circuit types using three-dimensional couplings can therefore be stacked if the offsets for the three-dimensional coupling receive terminals, and three-dimensional coupling transmit terminals paired with the applicable terminals are standardized. 
         [0332]    The invention rendered by the present inventors was described in detail based on the embodiments. Needless to say however, this invention is no limited by these embodiments and all manner of changes and adaptations not departing from the spirit and scope of this invention are allowable.