Abstract:
An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Description:
[0001]    The present U.S. Patent Application is a Division of U.S. patent application Ser. No. 12/579,517, filed on Oct. 15, 2009, which is a Division of U.S. patent application Ser. No. 11/751,786, filed on May 22, 2007 and issued as U.S. Pat. No. 7,646,082 on Jan. 12, 2010. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates generally to integrated circuit internal package interconnects, and more particularly, to a methodology and multi-layer substrate that has improved signal integrity and impedance matching. 
         [0004]    2. Description of Related Art 
         [0005]    High-density interconnect schemes for processor packages, as well as other very-large-scale integrated (VLSI) circuits typically use a large number of circuit layers to connect one or more dies to electrical terminals disposed on one or more surfaces of the package, as well as to interconnect multiple dies in multi-die packages. 
         [0006]    A typical stack-up for a present-day VLSI circuit substrate is fabricated in very thin layers on one or both sides of a rigid core that provides stiffness and stability to integrated circuit substrates, which may then be encapsulated after dies are attached. The core typically includes pass-through vias that have a larger diameter than the vias used between the thin circuit layers and that pass between thin insulating layers. For example, in a substrate having a core 800 μm thick, the diameter of the through vias may be 500 μm in diameter, while the outer layer interconnects may have vias only 50 μm in diameter. The reason for the larger diameter holes through the core is the relative thickness of the core, which makes reliable fabrication and resin/conductive filling of the vias more difficult than for vias between the thin insulating layers in the outer circuit layers that are laminated on the core. 
         [0007]    Since the interconnect routing density directly determines the required size of the final package, routing resources are critical in an integrated circuit package and space is at a premium. However, for critical signal paths such as clock and high-speed logic signal distribution, transmission lines must be maintained throughout the signal path in order to prevent signal degradation. Therefore, a reference voltage plane (e.g., ground) metal layer is provided on the surface of the core, with voids around the via and interconnect areas at the surface(s) of the core so that a transmission line is provided for the next signal layer above/below the core surface metal layer(s). As a result, signal path conductors must be routed around the large diameter vias passing through the core which are not connected to the metal layer. Further, the signal path conductors must also be routed away from discontinuities in the metal layers(s) caused by the voids through which the vias pass, since the lack of reference voltage plane metal will cause a change in impedance of the transmission line. Therefore, the number of signal routing channels is severely limited by the presence of the large-diameter vias that extend through the core that provide signal paths, and the large-diameter vias that provide voltage planes other than the voltage plane connected to the core surface metal layer. 
         [0008]    It is therefore desirable to provide a multi-layer integrated circuit, substrate and method that maintain signal integrity and impedance matching in an integrated circuit package while providing an increased amount of signal routing channels. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    The objective of improving signal integrity and impedance matching in a multi-layer integrated circuit substrate is provided in an integrated circuit substrate, and methods for making and designing the integrated circuit substrate. 
         [0010]    The substrate includes a core having large diameter vias and at least one signal layer having signal conductors having a width substantially smaller than the diameter of the large diameter vias. The signal conductors are connected to large diameter vias by a small diameter portion passing through a first insulating layer disposed between the core and a transmission line reference plane metal layer, and a second insulating layer disposed between the transmission line reference plane metal layer and the signal layer. 
         [0011]    The transmission line reference plane metal layer defines voids having an area larger than the area of signal-bearing large diameter vias, so that the presence of the transmission line reference plane metal layer does not cause substantial insertion capacitance with respect to critical signals. Metal is provided in the transmission line reference plane metal layer over large diameter vias that connect to power distribution (e.g., V DD  and ground), other voltage planes such as reference voltages/returns, and non-critical signal paths resulting in improved transmission line impedance profile and an increased number of routing channels available above the transmission line reference plane metal layer. 
         [0012]    The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like components, and: 
           [0014]      FIG. 1  is a top view of a Prior Art integrated circuit substrate. 
           [0015]      FIG. 2A  is a cross-sectional view of a substrate in accordance with an embodiment of the present invention. 
           [0016]      FIG. 2B  is top view of the substrate of  FIG. 2A . 
           [0017]      FIG. 3  is a graph depicting an expected time-domain reflectometer display depicting a performance improvement provided by the substrate of the present invention. 
           [0018]      FIGS. 4A-4G  are cross sectional views illustrating steps in the manufacture of a substrate in accordance with an embodiment of the present invention. 
           [0019]      FIG. 4H  is a cross sectional view of an integrated circuit package in accordance with an embodiment of the present invention. 
           [0020]      FIG. 5  is a pictorial diagram depicting a workstation computer system by which design methods and computer program products are executed in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    The present invention concerns integrated circuit package substrates and methods of designing and making the substrates that solve impedance matching and isolation problems associated with prior art substrates. Referring now to  FIG. 1 , a top view of a prior art integrated circuit package substrate is shown. A core dielectric layer  10  is covered by a reference voltage plane (e.g., ground or other power distribution plane) metal layer  11  through which voids  15  are provided so that the tops of plated through vias  12 B,  12 C and interconnect “jog” conductor stubs  16  are electrically isolated from metal layer  11 . An insulating layer  13  is disposed atop the metal layer  11  and signal conductors  18  are routed in routing channels atop insulating layer  13 . Plated through reference voltage plane vias  12 A are electrically connected to metal layer  11  and therefore have no voids disposed around their top ends. As illustrated, a very limited number of routing channels are available for signal conductors  18 , as in order to form proper transmission lines, the signal conductors are routed over continuous portions of metal layer  11 , including areas above the tops of reference voltage plane vias  12 A. Small diameter vias  14  provide for connection of signal conductors  18  to upper layers laminated above the metal layer corresponding to signal paths  18 . 
         [0022]    Referring now to  FIG. 2A , an integrated circuit package substrate in accordance with an embodiment of the present invention is shown. The substrate includes a core  30  including through-via conductors provided by resin-filled plated-through hole (RFPs)  32 A- 32 C. Metal layers are formed by plating, deposition or laminating on both sides of core  30  containing jog stubs  34 A- 34 C and areas of reference voltage plane layer  31 , with an insulating layer  35  laminated above stubs  34 A- 34 C and reference voltage plane layer  31 , similar to the substrate of  FIG. 1 . However, in the substrate of  FIG. 2A , a transmission line reference plane metal layer  37  is laminated, or otherwise deposited, above insulating layer  35  and a second insulating layer  39  is laminated, or otherwise deposited, above transmission line reference plane metal layer  37 . A signal layer including signal path conductors  38  that are laminated or otherwise deposited above insulating layer  39 . For each critical signal-bearing RFP  32 A, large-diameter voids  33  in transmission line reference plane metal layers  37  are provided above and below ends of signal-bearing RFPs  32 A, which substantially eliminates the shunt capacitance from signal-bearing RFP  32 A to transmission line reference plane metal layers  37 . While large-diameter voids are devoid of metal, in practice, the voids will generally be filled with dielectric, lamination adhesive or other non-conductive material. Signal-bearing RFPs  32 A are connected to signal path conductors  38  by stubs  34 A and small-diameter vias  36 A. Without large diameter voids  33 , the shunt capacitance from the ends of signal-bearing RFP  32 A to transmission line reference plane metal layers  37  will cause signal degradation. Voltage plane RFPs  32 B and  32 C (and optionally RFPs bearing non-critical signals) have no corresponding large-diameter voids in transmission line reference plane metal layer  37 , which increases their distributed capacitance by the shunt capacitance from RFPs  32 B, 32 C to transmission line reference plane metal layer  37 , which is generally desirable. 
         [0023]    Reference plane RFP  32 B, which corresponds to the voltage plane to which transmission line reference plane metal layer  37  is connected, has a stub  34 B connecting to transmission line reference plane metal layer  37  through a small via  36 B. Blind vias connected to transmission line reference plane metal layer  37  can further be used in connections to signal path layers added above the layer containing signal conductors  38 , to provide electrical connection to the particular voltage plane connected to transmission line reference plane metal layer  37 , if needed. Therefore, no void is needed in transmission line reference plane metal layer  37  above reference plane RFP  32 B. Other voltage plane RFPs  32 C will generally require formation of vias  36 C extending to other layers above transmission line reference plane metal layer  37  from stubs  34 C. Small-diameter voids  33 A provide connection to other voltage plane RFPs  32 C and extend only above the ends of stubs  34 C, for signal routing channels above transmission line reference plane metal layer  37  above the top ends (and beneath the bottom ends for layers applied beneath core  30 , not specifically shown) of other voltage plane RFPs  32 C. Thus, in contrast to the substrate of  FIG. 1 , the substrate of the present invention provides for routing of signal path conductors  38  in routing channels extending anywhere above reference plane RFPs  32 B and other voltage plane RFPs  32 C that were not available for routing signal path conductors in the substrate of  FIG. 1 . The voltage plane used to provide a reference to transmission line reference plane metal layer  37  may be a power supply voltage supplying the input/output drivers (the I/O signal reference and/or return voltage) or ground. 
         [0024]    Referring now to  FIG. 2B , a top view of the integrated circuit package substrate of  FIG. 2A  is shown. Voids  33  are defined by transmission line reference plane metal layer  37 , with additional metal removed above signal path stubs  34 A and small diameter voids  33 A for vias  36 A that connect signal path stubs  34 A to other signal layers. The resulting integrated circuit package substrate has improved isolation between signal path conductors  38  routed over the continuous portions of transmission line reference plane metal layer  37 , while eliminating the shunt capacitance from signal-bearing RFPs  32 A to metal layer  37 . Increased routing channels are provided in the regions extending over the top ends (or bottom ends) of voltage plane RFPs  32 B and  32 C. Thus, the substrate of the present invention provides improved signal performance in signal paths, providing for higher processor or other VLSI circuit operating frequencies, while providing increased routing flexibility by providing more routing channels that can have full signal performance no matter whether signal paths are routed above core RFPs that carry power distribution and/or non-critical signals. 
         [0025]    Referring now to  FIG. 3 , an expected time domain reflectometer (TDR) display illustrating the advantages of the present invention is shown. The solid line  80  depicts a reflectometer measurement of a signal path from a signal RFP extending to a signal path, such as signal path  18  of  FIG. 1 . The capacitance is estimated as 0.1 pF and results in an impedance drop from 50 ohms to approximately 41 ohms The dashed line  82  represents a TDR display of the impedance from a signal RFP to a signal path such as signal path  38  of the substrate of  FIGS. 2A-2B . The reduction in capacitance provided by the voids  33  in transmission line reference plane metal layer  37  above signal RFPs  32 A and small-diameter vias  33 A provide a reduction in the shunt capacitance and consequent reflection, keeping the transmission line impedance of the signal path above  47  ohms 
         [0026]    Referring now to  FIGS. 4A-4G , a method of making an integrated circuit substrate and integrated circuit in accordance with an embodiment of the invention is shown. As shown in  FIG. 4A , starting from a core dielectric layer  40  having via holes  41  formed therein, holes  41  are filled with resin/metal to form PTHs  42 . Stubs  44  and reference plane areas  43  are formed on both surfaces of core  40 , as shown in  FIG. 4B . An insulating layer  45  is then applied to one or both sides of the core dielectric layer  40 , over stubs  44  as shown in  FIG. 4C . Next, insulating layer  45  is opened to generate small-diameter via holes, forming insulating layer  55 . Then, metal is added in the small-diameter via holes to form small vias  56  to connect to voltage plane RFPs as shown in  FIG. 4D . Next, a transmission line reference plane metal layer  58  with voids  57  is applied as shown in  FIG. 4E . Voids  57 , will generally be filled with dielectric insulating material or lamination adhesive as described above. Both the insulating layer  55  and transmission line reference plane metal layer  58  may be applied as laminates, or the insulating layer may be deposited and/or transmission line reference plane metal layer  58  may be plated atop insulating layer  55 . Voids  57  may be pre-formed in transmission line reference plane metal layer  58  or etched. Next, as shown in  FIG. 4F , another insulating layer  60  is applied in a manner similar to that for insulating layer  55 , and small voids  62  are formed or pre-formed in insulating layer  60  for connection to signal RFPs. Finally, blind vias  64  and a signal layer  66  are formed as shown in  FIG. 4G  that provide electrical connection to signal RFPs. Blind vias  64  and signal layer  66  may be formed at the same time, for example, by plating, or blind vias  64  may be formed first by filling or plating and then signal layer  66  laminated or plated to connect to blind vias  64 . 
         [0027]    Referring now to  FIG. 4H , an integrated circuit in accordance with an embodiment of the present invention is shown. The substrate of  FIG. 4G  is further modified by adding further signal layers, and optionally voltage plane layers on one or both sides of the core dielectric layer  40 . As illustrated another insulating layer  55 A and signal layer  66 A are added, but in practice, numerous other layers may be added. A semiconductor die  70  is attached to lands or other structures accessible from the top layer of the substrate shown in  FIG. 4G  and terminals or lands (not shown) may similarly be added to the bottom side of the substrate after other circuit layers are added. Alternatively, lands can be formed directly on the bottom side of core dielectric layer  40  or terminals may be attached to the bottom side of RFPs  42 . 
         [0028]    Referring now to  FIG. 5 , a workstation computer system  100  is shown in which the methods of the present invention are carried out in accordance with an embodiment of the present invention, according to program instructions that may be embodied in a computer program product in accordance with a present invention, for example program instructions stored on a CD-ROM disc CD. Workstation computer system includes a processor  102  for executing the program instructions coupled to a memory  104  for storing the program instructions, data and results used in designing integrated circuit substrates in accordance with embodiments of the present invention. Workstation computer system  100  also includes peripheral devices such as CD-ROM drive  105  for reading discs such as CD in order to load the program instructions into workstation computer  100 . Input devices, such as a keyboard  107 A and a mouse  107 B are coupled to workstation computer system  100  for receiving user input. A graphical display  106  for displaying results such as the layout of metal layer  37  of  FIGS. 2A-2B  and simulations such as that of  FIG. 3 . The depicted workstation computer  100  is only exemplary and illustrates one type of computer system and arrangement suitable for carrying out the design methods of the present invention. 
         [0000]    The design methods generally identify the locations of signal bearing vias and generate a mask design for a transmission line reference plane metal layer that includes voids around the profile of the signal-bearing vias so that capacitive coupling between the ends of the signal-bearing vias and the transmission line reference plane metal layer is substantially reduced. 
         [0029]    While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention.