Abstract:
A packet data communication on-chip interconnect system is provided including a network interface efficiently controlling a transaction performed between at least one master intellectual property (IP) block and at least one slave IP block connected via a Network on a Chip (NoC). According to an aspect of the present invention, traffic functioning and throughput of the entire NoC may be improved by appropriately controlling an operation of performing a lock operation according to an Advance eXtensible Interface (AXI) protocol in the network interface of the packet data communication on-chip interconnect system.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Korean Patent Application No. 10-2005-0127558, filed on Dec. 22, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a packet data communication on-chip interconnect system, and more particularly, to a network interface efficiently controlling transaction performed between at least one master intellectual property (IP) block and at least one slave IP block connected via a Network on a Chip (NoC), and a packet data communication on-chip interconnect system including the network interface.  
         [0004]     2. Description of the Related Art  
         [0005]     An Advanced Microcontroller Bus Architecture (AMBA) Advanced extensible Interface (AXI) protocol is a more suitable bus protocol for a high-speed/high-end system than a related art on-chip bus protocol and has channels associated with read, write, address, and write response, which are respectively separated, individually operated, and have transaction properties such as multiple-outstanding address, write data interleaving.  
         [0006]     An NoC is a network style on-chip interconnect system manufactured to overcome structural defects of a related art bus structural on-chip interconnect system. A high-speed/high-end/low power System on a Chip (SoC) may be embodied via the NoC. According to a packet data communication mode defined to support an AXI protocol in the NoC  100 , a plurality of Intellectual Property (IP) blocks  110  shown in  FIG. 1  may perform efficient data processing via packet routing of an NoC backbone  120 .  
         [0007]     In designing a packet data communication on-chip interconnect system shown in  FIG. 1 , a system designer may variously design the blocks  110  or the NoC backbone  120  according to the AXI protocol. The AXI protocol may be easily applied to any field such as not only a point-to-point system but also a multilayer system, via an interface between at least one master IP block and at least one slave IP block. Particularly, since the AXI protocol supports multi-transaction elegantly, parallel burst transmission is possible, thereby improving throughput. Therefore, a particular operation may be performed for a short time and various operations are performed by a plurality of IP blocks integrated in one chip, thereby reducing power consumption.  
         [0008]     According to the AXI protocol, a master IP block is cross connected to a slave IP block via a network interface, when a lock operation is performed between one master IP,block and the slave IP block, an arbiter in an interconnect system may control a transaction input from another master IP block to the slave IP block until an unlock transfer is issued from the master IP block requesting a lock access. However, in a packet data communication on-chip interconnect system, since a master IP block is connected to an NoC backbone via a network interface and is connected to a destination slave IP block via at least one router included in the NoC backbone, there is no centralized data transfer controller between the master IP block and the slave IP block.  
         [0009]     As described above, since the centralized data transfer controller does not exist in the packet data communication on-chip interconnect system, when the packet data communication interconnect system supports a lock operation defined by the AXI protocol, problems described below may occur.  
         [0010]     When a lock sequence is transferred from a second master IP block to a slave IP block while a transaction is performed between a first master IP block and the slave IP block, according to the AXI protocol, a lock access requested by the second master IP block may not be accepted. In this case, the second master IP block has to wait for a ready response with respect to the lock access for a predetermined amount of time or has to retransfer the lock sequence when the ready response is not received, thereby generating a delay in processing a certain task and dropping a traffic efficiency of an NoC backbone.  
         [0011]     When a transaction including a lock sequence is input from a second master IP block to a slave IP block while a lock operation is performed between a first master IP block and the slave IP block, according to the AXI protocol, the lock operation performed between the first master IP block and the slave IP block fails. In this case, the slave IP block has to transfer a SLVERR response with respect to the lock sequence to the first master IP block and the first master IP block has to retransfer the lock sequence to the slave IP block to perform the lock operation from the beginning again. Therefore, with an increase of traffic of an NoC backbone, efficiency of utilizing a resource of the first master IP block may be decreased.  
       SUMMARY OF THE INVENTION  
       [0012]     An aspect of the present invention provides a method of supporting a lock operation in a packet data communication on-chip interconnect system including a plurality of master IP blocks and a plurality of slave IP blocks transferring data via network interface, centering around an NoC backbone.  
         [0013]     An aspect of the present invention provides a packet data communication on-chip interconnect system efficiently controlling a lock operation performed between a master IP and a slave IP  
         [0014]     An aspect of the present invention also provides a packet data communication on-chip interconnect system which adds a simple operation logic to a network interface.  
         [0015]     An aspect of the present invention also provides a packet data communication on-chip interconnect system in which traffic efficiency of the entire NoC as well as throughput may be improved.  
         [0016]     According to an aspect of the present invention, there is provided a network interface of a packet data communication on-chip interconnect system, the network interface including: a state controller which monitors a transaction between a slave IP block and at least one master IP block connected via a Network on a Chip (NoC) backbone; and a buffer which buffers a data burst input from the master IP block, wherein, when a lock sequence is received from a second master IP block while the slave IP block transacts with a first master IP block, the state controller controls the buffering of the lock sequence received from the second master IP block in the buffer, and when the transaction between the slave IP block and the first master IP block is completed, the state controller controls the lock sequence buffered in the buffer to be transferred to the slave IP block.  
         [0017]     According to another aspect of the present invention, there is provided a network interface of a packet data communication on-chip interconnect system, the network interface including: a state controller which monitors a transaction between a slave IP block and at least one master IP block connected via an NoC backbone; and a buffer which buffers a data burst input from the master IP block; and a response generation unit which generates an error response according to control of the state control unit, wherein, when the data burst is input from a second master IP block while the slave IP block is in a lock operation with a first master IP block, the state controller controls discarding the data burst buffered in the buffer, the generating of the error response by the response generating unit, and transferring the error response transferred to the second master IP block via the NoC backbone. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and/or other aspects of the present invention will become apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings of which:  
         [0019]      FIG. 1  is a schematic diagram illustrating a related art general packet data communication on-chip interconnect system;  
         [0020]      FIG. 2  is a diagram illustrating connection relations of IP blocks included in a packet data communication on-chip interconnect system;  
         [0021]      FIG. 3  is a diagram illustrating an operation theory of a network interface according to an exemplary embodiment of the present invention;  
         [0022]      FIG. 4  is a diagram illustrating an operation theory of a network interface according to another exemplary embodiment of the present invention;  
         [0023]      FIG. 5  is a block diagram illustrating a configuration of a network interface according to an exemplary embodiment of the present invention;  
         [0024]      FIG. 6  is a flowchart illustrating an operation method of the network interface according to an exemplary embodiment of the present invention; and  
         [0025]      FIG. 7  is a flowchart illustrating an operation method of the network interface according to another exemplary embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The exemplary embodiments are described below to explain the present invention by referring to the figures.  
         [0027]      FIG. 2  is a diagram illustrating a packet data communication on-chip interconnect system  200  according to an exemplary embodiment of the present invention.  
         [0028]     Referring to  FIG. 2 , the packet data communication on-chip interconnect system  200  includes a Network on-Chip (NoC) backbone  210  and at least one IP block  220  to  250  performing a series of processes according to an AXI protocol.  
         [0029]     As shown in  FIG. 2 , each of the IP blocks  220  to  250  accesses the NoC backbone  210  to perform a transaction with other IP blocks or to be connected to network interfaces (NIs)  221 ,  231 ,  241 , and  251  interfacing a data burst transferred from other IP blocks.  
         [0030]     Master IP blocks  220 ,  230  and  240  perform transactions with a slave IP block  250  via at least one router (not shown) included in the NoC backbone  210 . The NoC backbone  210  routes a packet or a flit according to the AXI protocol, between a plurality of the IP blocks  220  to  250 .  
         [0031]     For example, the master IP blocks  220 ,  230  and  240  may transfer packet data formed of a header and a payload to the slave IP block  250  and may record or read data from the slave IP block  250 . The NoC backbone  210  routes the packet data transferred between the master IP blocks  220 ,  230  and  240  and the slave IP block  250  with reference to a destination address included in the packet data. The described packet may be transferred after being divided into a predetermined size of a flit. In the present specification, the data transferred between several IP blocks via the NoC backbone  210  is transferred in a form of a packet or flit and the packet or flit data transferred via the NoC backbone  210  may be designated by a data burst.  
         [0032]     Similar to a general high-speed communication packet theory, the header of the packet data may include a data length, lock information, a source identification (ID), a destination ID, and a packet type, such as a data read/write request. Also, the payload may include an address of a slave IP block in which data is read or written, and data. Particularly, when lock access request information is included in the header, a flit input from another IP block may not be input to the slave IP block performing the lock operation while a master IP block communicates with the slave IP block and may be input to the relevant IP block after the lock operation is finished by an unlock transfer issued from the master IP block.  
         [0033]     Since the described type of communication between the master IP block and the slave IP block has already been disclosed in a prior publication related to the AXI protocol, detailed description thereof will be omitted and only a detailed configuration according to the present invention in the present specification will be described. Also, though packet data is transferred according the AXI protocol in the packet data communication on-chip interconnect system according to the present exemplary embodiment in the present specification, it can also be applied to a packet data communication on-chip interconnect system operating by other protocols supporting a lock operation, such as Advanced High-performance Bus (AHB) protocol or Advanced Peripheral Bus (APB) protocol in addition to the AXI protocol.  
         [0034]     In the packet data communication on-chip interconnect system  200 , the NIs  221 ,  231 ,  241 , and  251  of each of the IP blocks  220  to  250 , for example, the NI  251  of the slave IP block  250  buffers a lock sequence input from other master IP blocks while performing transaction with a particular master IP block or generates an error response with respect to a data burst input from other IP blocks and transfers the error response to the master IP block inputting the data burst while performing a lock operation with a particular master IP block. There are problems of the described related art technology, namely, a case in which a lock sequence is input from the master IP 1   220  while performing transaction between the master IP 2   230  and the slave IP block  250 .  
         [0035]     Referring to  FIG. 3 , an operation of the network interface of the packet data communication on-chip interconnect system according to an exemplary embodiment of the present invention will be schematically described below.  
         [0036]     As shown in  FIG. 3 , the master IP 2   230  transfers a flit burst  310  formed of addresses Al and A 2  to the slave IP block  250 , and the master IP 1   220  inputs a lock sequence burst  320  to the slave IP block  250  while transferring a flit burst formed of data D 1  and D 2 . According to the related art technology, the lock sequence burst  320  input from the master IP 1   220  is not accepted. Accordingly, the master IP 1   220  has to wait for a ready response with respect to a lock access request for a predetermined amount of time or has to again transfer a lock sequence burst  320  when the response is not received from the slave IP block  250 . The network interface  251  according to the present exemplary embodiment buffers the lock sequence burst  320  input from the master IP 1   220  in a buffer and transfers the buffered lock sequence burst  320  to the slave IP block  250 . In  FIG. 3 , as transaction performed with the master IP 2   230 , a maximum length of a burst is  2  and flits including an address and data are divided and transferred into two bursts.  
         [0037]     Referring to  FIG. 4 , an operation of the network interface of the packet data communication on-chip interconnect system according to another exemplary embodiment of the present invention will be schematically described below.  
         [0038]     Referring to  FIG. 4 , a case in which the master IP  220  tries to perform a transaction with the slave IP block  250  while a lock operation is performed between the master IP 2   230  and the slave IP block  250  is illustrated.  
         [0039]     In  FIG. 4 , after a lock operation starts with transferring a lock flit burst  410 , formed of the address Al and the data D 1 , to the slave IP block  250  by the master IP 2   230 , the master IP 1   220  tries to transfer a flit burst  420  formed of an address A 21  and data D 21 , D 22 , and D 23  to the slave IP block  250 . The master IP 2   230  only transfers the lock flit burst  410  and does not transfer a lock flit burst  430 . The slave IP block  250  operates in a lock operation mode with the master IP 2   230  until an unlock transfer  440  is issued from the master IP 2   230 . In this case, when the flit burst  420  is input from the master IP 1   220 , the lock operation fails according to the AXI protocol. Accordingly, the network interface  251  discards the flit burst  420  transferred from the master IP 1   220  and generates and transfers an error response to the master IP 1   220 . The master IP 1   220  receiving the error response may retransfer the flit burst  420  to the slave IP block  250  after the unlock transfer  440  is issued from the master IP 2   230 . In  FIG. 4 , though the discarded flit burst  420  is described as a normal flit, the operation may be applied to a case in which a flit burst transferred from the master IP 1   220  is a lock sequence. Also, the error response described with reference to  FIG. 4  may be, for example, a slave error response (SLVERR) that is one of AXI protocol responses.  
         [0040]      FIG. 5  is a block diagram illustrating a configuration of the network interface according to an exemplary embodiment of the present invention.  
         [0041]     Referring to  FIG. 5 , the network interface of a group of slave IP blocks included in the packet data communication on-chip interconnect system includes a state controller  510 , a buffer  520 , and a response generator  530 . In  FIG. 5 , though the configuration of the network interface capable of supporting the operation theory of the network interface according to the embodiments of the present invention described with reference to  FIGS. 3 and 4 , those skilled in the art would readily recognize that the network interface may include the state controller  510  and the buffer  520  or the state controller  510  and the response generator  530 .  
         [0042]     As described above, the network interface  500  included in the packet data communication on-chip interconnect system processes data transactions between the NoC backbone  210  and the IP blocks  220  to  250  operating as a master or a slave. Methods of operating the network interface  500  (hereinafter, referred to as the NI  500 ) according to the present exemplary embodiment will be described below with reference to  FIGS. 6 and 7 .  
         [0043]      FIG. 6  is a flowchart illustrating an operation method of the network interface according to an exemplary embodiment of the present invention.  
         [0044]     The NI  500  is in an idle state in which transaction with a master IP block or a slave IP block is not performed ( 601 ). The NI  500  receives a data burst from a first master IP block and transfer the data burst to a slave IP block ( 602 ), and packet data transaction is performed ( 603 ).  
         [0045]     When a lock sequence is input from a second master IP block while the transaction is performed between the first master IP block and the slave IP block ( 604 ), the NI  500  buffers the input lock sequence to the buffer  520  ( 605 ). When the transaction is performed between the first master IP block and the slave IP block, the state controller  510  controls the buffering of the lock sequence input from the second master IP block to the NI  500 .  
         [0046]     When the transaction between the first master IP block and the slave IP block is finished ( 606 ), the NI  500  transfers the lock sequence buffered to the buffer  520  to the slave IP block ( 607 ). According to the transferred lock sequence, the slave IP block transfers a ready response to the second master IP block and a lock operation is performed between the second master IP block and the slave IP block ( 608 ).  
         [0047]      FIG. 7  is a flowchart illustrating an operation method of the network interface according to another exemplary embodiment of the present invention.  
         [0048]     The NI  500  is in an idle state in which transaction with a master IP block or a slave IP block is not performed ( 701 ). The NI  500  receives a lock sequence from a first master IP block ( 702 ) and transfers the lock sequence to the slave IP block via the NI  500 , and the lock operation is performed ( 703 ).  
         [0049]     When a flit burst is input from the second master IP block ( 704 ) while the lock operation is performed, the state controller  510  controls discarding of the received flit burst and the response generator  530  to generate a SLVERR response ( 705 ). The generated SLVERR response is transferred to the second master IP block ( 706 ). When an unlock transfer is issued from the first master IP block and the lock operation is finished ( 707 ), the second master IP block retransfers the flit burst transferred in  704  ( 708 ). The flit burst transferred from the second master IP block is transferred to the slave IP block via the NI  500 , and the second master IP block and the slave IP block transfer and receive the flit burst and perform transaction ( 709 ).  
         [0050]     The function used in the method and apparatus disclosed in the present specification can also be embodied as computer readable codes on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, optical data storage devices, and carrier waves (such as data transmission through the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.  
         [0051]     Although a few exemplary embodiments of the present invention have been shown and described, the present invention is not limited to the described exemplary embodiments. Instead, it would be appreciated by those skilled in the art that changes may be made to these exemplary embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.