Abstract:
A monitoring system is disclosed in which fiber-optic cables are used with sensors, e.g., a temperature sensor, to transmit analog data from the sensors in binary form to a receiver. The binary information is then analyzed by a microprocessor, which is attached to the receiver, to monitor the system. The purpose of the fiber-optic cables is to ensure the isolation of the transmitted data from surrounding electrical noise and natural phenomena. That noise tends to distort the transmittal of such sensor data in prior systems which use hard wires instead of fiber-optic cables. Unlike prior systems in which a fiber-optic light source known as an &#34;L.E.D.&#34; (light-emitting diode) is normally kept &#34;on&#34;, the main feature of this system is that its L.E.D. is normally kept &#34;off&#34; and is turned &#34;on&#34; only when information is desired. This greatly increases the life of the L.E.D., which is important when the system is used in remote places, such as satellites, where an electrician is not available to replace a burned-out diode.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to monitoring systems that use electro-optical transmission lines to transmit sensor data to a central processor. 
     Electro-optical transmission systems are known in which electrical signals are coupled to a first electrical connector member where the signal is converted by means of a light-emitting diode (an &#34;L.E.D.&#34;) to an electrical output signal, and the output signal is transmitted by a fiber-optic cable to a light-receiving diode in a second connector member which receives the optical signal and converts it back to an electrical signal. Such electro-optical transmission systems have the advantage over conventional hard-wire transmission systems in that they are not susceptible to electro-magnetic interference (&#34;E.M.I.&#34;) and radio frequency interference (&#34;R.F.I.&#34;). Since these systems are not subject to electrical noise, they are often used in high technology situations, such as monitoring systems in satellites, to precisely transmit electrical data. 
     Besides being relatively immune to electrical noise, another aspect which makes the fiber-optic cable attractive is the lighter weight of the cable as compared to a shielded link using conventional hard wire. Further, fiber-optic links also have a greater bandwidth, which enables more information to be transmitted if the information is multiplexed. 
     While these systems have proved quite useful, especially in satellites for transmitting information from a remote sensor with a high degree of accuracy, these systems have a serious drawback. Their L.E.D.s are usually kept &#34;on&#34; even when information is not desired. Thus, the L.E.D. of most prior systems quickly burns out. And, as soon as it does, the system is useless. The system can no longer transmit information until the L.E.D. is replaced. 
     While this may be only a minor setback in places where the diode can be easily replaced, it is fatal when the system is in a remote area, where repair is unfeasible. Consequently, a need exists for a system in which the life of the L.E.D. is prolonged. 
     SUMMARY OF THE INVENTION 
     An electro-optical device for transmitting analog data via fiber optics is disclosed. In the preferred embodiment, the device basically comprises a transmission circuit for receiving electrical analog data from a sensor, converting the data into a string of binary information and transforming the information into light pulses by an L.E.D. for subsequent transmittal via a fiber-optic cable to a receiver unit, where the information is converted back into an analog signal prior to sending it to a microprocessor in a monitoring system. The device includes a means for allowing the L.E.D. to be normally kept &#34;off&#34; when no information is desired by a user, and to be turned &#34;on&#34; only when a new string of monitoring information is desired. This means includes a self-resetting means for automatically clearing the receiver unit after the L.E.D. is turned &#34;on&#34; so that the string of sensor information transmitted by the receiver circuit to the monitor only includes the new information obtained by the device after the diode is turned &#34;on&#34; and does not include any stale information previously stored by the device. 
     The transmission circuit includes an analog-to-digital converter for receiving analog data and converting the data into binary information, a shift register connected to the converter for receiving a string of binary information and shifting the information to the L.E.D. where it is transformed into light pulses. 
     A fiber-optic cable is attached at one of its ends and is adapted to receive the light pulses and transmit them to the receiver circuit. 
     The receiver circuit is attached to the opposite end of the fiber-optic cable and includes a light-receiving diode for receiving the light pulses transmitted by the cable and converting them back into electrical data signals, a de-multiplexer connected to the light-receiving diode for handling the data and sending the data to an attached shift register, and a digital-to-analog converter attached to the shift register for receiving a string of data in binary form from the shift register, converting the data back to an analog signal and transmitting it to the monitoring system. 
     It is the primary object of the present invention to provide an electro-optical transmission system in which the life of the L.E.D. is conserved and the system&#39;s life is thereby prolonged. 
     It is a more specific object to provide an electro-optical transmission system for transmitting sensor data in spacecraft, wherein the L.E.D. is normally kept &#34;off&#34; when no information is desired by a user and is turned &#34;on&#34; only when information is desired. By keeping the L.E.D. &#34;off&#34; until information is desired, the L.E.D. will usually last a longer time before it burns out and, consequently, the usual life of the entire system will be prolonged. 
     It is another object to provide an electro-optical transmission system that is self-resetting so that when the system is turned &#34;on&#34;, the only information that will be transmitted is the information desired by the user and not information previously stored by the device. 
     Other aspects and advantages of the invention will become more apparent from the following description taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a system block diagram of the invention; 
     FIG. 2 is a block diagram of the transmission circuit shown in FIG. 1; 
     FIG. 3 is a schematic of an optical receiver used in the receiving circuit of FIG. 1; 
     FIG. 4 is a block diagram of the receiving circuit; and, 
     FIGS. 5A-5D collectively are a timing diagram for the transmission circuit, with FIG. 5A representing the clock pulses from a timer, FIG. 5B representing the output of a binary counter which counts the pulses, FIG. 5C representing the output of a flip flop which resets an analog-to-digital converter in response to the counter&#39;s output and instructs the converter when to start and stop the conversion of analog electrical signals into binary bits, and FIG. 5D representing an output line of the converter that governs the shifting of data into and out of a shift register. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to the drawings in detail, an electro-optical transmission link 10 is illustrated for transmitting analog data in a monitoring system (not shown) from remote sensors, e.g., a temperature sensor, in binary form to a microprocessor. As shown in FIG. 1, the link 10 includes a transmission circuit 12 for receiving an electrical analog signal 13 and converting it into an optical signal via a photoelectric cell 14 (an L.E.D.), and a fiber-optic cable 16 for transmitting the optical signal from the transmission circuit to a receiving circuit 18 where the optical signal is converted back to an electrical signal prior to sending it along output line 19 to the microprocessor. 
     When information is not desired, the L.E.D. is kept &#34;off&#34; and is turned &#34;on&#34; only when a new string of information is desired. To prevent the system from misinforming the user with stale information that was stored prior to the L.E.D. being shut &#34;off&#34; in a previous cycle, the receiver unit 18 includes a selfresetting circuitry for clearing the receiver unit after the L.E.D. is turned &#34;on&#34; so that the receiver is &#34;empty&#34; prior to it sending a first bit of new sensor data to the microprocessor. 
     THE TRANSMISSION CIRCUIT 
     As shown in FIG. 2, the transmission circuit 12 includes an analog-to-digital converter 20 (&#34;A/D&#34; converter), here an MN5143 A/D converter by Micro Networks Corporation. This chip requires only eight clock cycles for the binary encoding of the analog data from the sensor. 
     Timing for the transmission circuit is accomplished by a standard 555 timing chip (numbered 22 in the drawings) which is set in the astable mode. The output of the timer 22 is set to have a &#34;high&#34; output for 2.2 msec. and a &#34;low&#34; output for 1.4 msec. for a total clock cycle of 3.6 msec. The frequency of the clock is set to be about 277 Hz. The timer 22 controls the A/D converter 20 along with a standard 74199 eight-bit shift register (numbered 24 in the drawings), a standard 74163 four-bit binary counter (numbered 26 in the drawings), and a standard 7474 dual D-type flip flop (numbered 28 in the drawings). 
     The timing diagram for the transmission circuit 12 is shown in FIGS. 5A-5D. The main lines shown represent the clock output 30, the counter output 32, an output 34 of a standard 7476 J-K flip flop 36 and an &#34;end of convert&#34; (&#34;E.O.C.&#34;) output 38 from the A/D converter 20. 
     The timer 22 is designed to operate as an astable multivibrator. Its output is connected to the clock input pin of the counter 26 which counts the clock cycles. At counts of sixteen, the output line 32 of the counter goes &#34;high&#34; (represented by reference numeral 39 in FIG. 5B). This &#34;high&#34; serves to toggle or switch over the J-K flip flop 36 whose output 34 governs a &#34;start convert&#34; line 40 of the A/D converter 20. When the start convert line is brought &#34;low&#34;, the A/D converter 20 goes into a reset mode (represented by reference numeral 41 in FIG. 5C), and upon returning to a &#34;high&#34; sixteen clock cycles later (at 42), the A/D converter 20 starts the conversion process (at 43) of transmitting an analog signal from the data and converting it into an optical signal. 
     The conversion process is completed in eight clock cycles (as at 44), and the E.O.C. line 38 is then brought &#34;low&#34; to signify that the conversion has been completed. The E.O.C. line governs the loading and shifting of the data into and out of the shift register 24. When the E.O.C. is &#34;low&#34; (as at 45 in FIG. 5D), the data is loaded into the register along data line 46 in FIG. 2, and when the E.O.C. is &#34;high&#34; (as at 47 in FIG. 5D), the data is shifted out of the register along data line 48 in FIG. 2. 
     The E.O.C. line 38 also controls the setting of a &#34;sync bit&#34; and the clearing of a &#34;buffer&#34;. When the E.O.C. line goes &#34;low&#34;, the first D flip flop 28a (of the double flip flop 28) is activated which produces a &#34;high&#34; output (the &#34;sync bit&#34;) and clears the output of the second D flip flop 28b (the &#34;buffer&#34;). 
     The buffer is needed due to the sync output being &#34;high&#34; for a period of time between the setting of the output and the time of the actual transmission. This &#34;high&#34; could be mistaken for the data by the receiver circuit 18. By using the buffer, the output will be &#34;low&#34; until the actual transmission of the data. When the flip flop 36 again toggles to the reset position at 41, the E.O.C. line 38 will go &#34;high&#34; to initiate the transmission of the data through the double flip flop 28 along line 49 to the data output line 50. 
     Referring again to FIG. 2, the transmission circuit&#39;s L.E.D. 14 is attached to the output line 50. In the preferred embodiment, the L.E.D. is a Radio Shack Infrared L.E.D., Model No. XC-880-A. It is connected to a 1000-ohm resistor 51 and a direct current biasing voltage of 5 volts, shown at number 52. 
     The L.E.D. receives strings of binary information from the line 50 in the form of electrical signals and transforms these signals into light pulses. The light pulses are then transmitted to an end (not shown) of the fiber-optic cable 16, and from there to the receiver circuit 18. 
     THE RECEIVER CIRCUIT 
     The first step in the receiver circuit 18 is to acquire the information obtained between the fiber-optic cable 16 which interconnects the output of the L.E.D. 14 to the receiver circuit 18. This initial step is accomplished by the optical receiver 53 illustrated in FIG. 3. In this figure, the information is initially received by an infrared phototransistor or light-receiving diode 54, here a TIL-414 Infrared Phototransistor by Radio Shack, connected to a 12-volt power source, indicated by the reference numeral 55. The phototransistor 54 is connected to a standard LM 311 optical amplifier 56 set up as a comparator by connection to the phototransistor 54 and a resistor 57 of 1000 ohms, a resistor 58 of 121 ohms, a resistor 59 of 4700 ohms and a 5-volt power source, indicated by the reference numeral 60. 
     In this setup, line 62 is the &#34;read&#34; line for the comparator and line 64 is the reference voltage line. When the photo diode 54 detects a light pulse from the fiber-optic cable 16, the diode 54 goes into the conducting mode and transmits about 0.4 volts. The comparator 56 reads the voltage via line 62 and triggers a 5-volt pulse from source 60. 
     The 5-volt pulse goes from output line 66 of the comparator 56 to a standard 74156 de-multiplexer 68 shown in FIG. 4. After a string of pulses, i.e., the analog data, is received by the de-multiplexer, the de-multiplexer separates the data. 
     Only two of the de-multiplexer&#39;s lines are used, those which correspond respectively to binary readings of 00 and 11. The &#34;00&#34; line (shown at 70 in the drawings) is designed to handle the &#34;sync bit&#34; while the &#34;11&#34; line (shown at 72) is used to handle the data. 
     The &#34;00&#34; and &#34;11&#34; lines are controlled by the output of a standard 7476 J-K flip flop 74, which selects the line to be used. When a low is applied to the &#34;clear&#34; input of the flip flop at 76, the flip flop selects the &#34;11&#34; line--the data line 70. On the other hand, when a low is applied to the &#34;preset&#34; input of the flip flop at 78, the &#34;00&#34; line is selected--the &#34;sync bit&#34; line 72. 
     If the sync bit line is selected, the chips which are then affected are the timer 22, shown in FIGS. 2 &amp; 4, and a standard 74163 four-bit binary counter 82 shown in FIG. 4. The sync signal prepares the receiving circuit 18 for receiving a new string of information. 
     On the next clock pulse, the information present in output line 66 of the comparator 56 is passed via data line 84 to a standard 74199 eight-bit shift register. At the same time that the data is being entered, the counter 82 is counting the bits of information being accepted. Upon counting the eighth bit, the counter 82 signals the shift register 86 via line 88 (called the &#34;most significant bit&#34; line) to hold the data which has been loaded into the register. At this point, the data is transferred to a standard 74244 eight-bit buffer register 90 via data line 92. The buffer register 90 is enabled or triggered to accept the information from the register by an inverted signal from the most significant bit line 88, caused by a passing of the line 88 signal through a standard 7406 HEX-Inverter 94. 
     From the buffer register 90, the information is passed via data line 96 to a digital-to-analog converter 98 (here, Precision Monolithics, Inc.&#39;s DAC-03 BDX2 D/A converter) for reconverting the signal to an analog output. This output is then transmitted along line 19 to the microprocessor. 
     The output may also be run to a warning system 102, such as that shown by a standard LM 741 amplifier 104 set up as a comparator via attachment to a 5-volt power source 106 and two resistors 108, 110 arranged to provide a reference voltage. When the comparator reads a voltage from output 100 that exceeds a preselected value, a signal is transferred along line 112 to a warning device such as an alarm or electrical readout device (not shown). 
     While the data is transferred to the buffer register 90, the counter 82 is still in operation counting the clock pulses. When the sixteenth pulse occurs, the output line 114 of the counter 82 is brought &#34;high&#34;. This line is used to set the J-K flip flop 74 to a &#34;high&#34; output which sets the circuit for the next sync bit. 
     In addition to the elements previously disclosed, the receiver circuit 18 includes a built-in reset characteristic which allows the system to be turned on at any time regardless of the state of the incoming information. A standard 7408 quad AND gate 116 and a standard 7400 quad NAND gate 117 are hooked up together and communicate with a sync line 118 of the de-multiplexer 68, an &#34;enabler&#34; line 120 of the flip flop 74 and a reset line 119 attached to the counter 82 and the timer 22. The result is that the sync line 118 signal is inverted and the output (along line 119) of the AND gate 116 is &#34;high&#34; when the sync line 118 is &#34;low&#34;. This &#34;low&#34;, which occurs when the flip flop is &#34;high&#34; and the sync 118 is also &#34;high&#34; will reset the timer 22 and binary counter 82 via line 119 and will clear the flip flop 74. 
     In the preferred embodiment, the receiver circuit 18 also includes a line-lost warning system generally indicated at 121. This warning system is comprised of a second, standard 74163 four-bit binary counter 122 which is attached to the enabler line 120 from the flip flop 74 and a standard 7406 HEX-Inverter 124 and a standard 7408 quad AND gate 126. One input line 128 of the AND gate 126 is attached to data line 84, while the other input line 129 is connected to the enabler line 120 and the inverter 124. 
     This second binary counter 122 will detect a failure of the transmission circuit. If the transmission fails, there will be no reset of the counter via flip flop 74. In that event, the standard 555 timer 130, attached to the binary counter 122 will continue to clock the counter. The output line 132 will thus be &#34;high&#34; on every sixteenth clock pulse. By monitoring the status of the line in relation to the clock pulses, by means of a flip-flop network (not shown), it will be easy to detect a failure due to the absence of a reset (sync) pulse. 
     The preferred embodiment also includes a pair of openended leads at 134, 136 for hook-up of optional equipment such as read-out devices (not shown). The lead 134 is for hook-up to the &#34;most significant bit&#34; line 88, while the lead 136 is for hook-up to an output line 138 from timer 22. 
     While a single embodiment of the present invention has been expressly disclosed, it should be understood that obvious structural modifications can be made without departing from the spirit of the invention. For example, the chips presently used in the system are of the 74 series because they are economical. However, these chips do not meet the military temperature range. Therefore, if the military temperature range is desired, the 54 series chips may be used. 
     Accordingly, reference should be made primarily to the accompanying claims, rather than to the specification, to determine the scope of the invention.