Abstract:
An operational amplifier circuit has a differential input circuit including a first transistor, which receives a first input signal and generates a first voltage, and a second transistor, which receives a second input signal and generates a second voltage. An output stage circuit includes a third transistor responsive to the second voltage, a fourth transistor connected to the third transistor, a fifth transistor responsive to the first voltage, and a sixth transistor connected to the fifth transistor. The output stage circuit generates an output signal of the amplifier circuit at a first node between the fifth and sixth transistors. A seventh transistor connected between the third and fourth transistors controls the potential at a second node between the third and seventh transistors to be the same as the potential of the first input signal in correspondence with the first input signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-147469, filed on May 26, 2006, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to an operational amplifier circuit. 
     An operational amplifier circuit is often used as a basic operation circuit in a semiconductor integrated circuit device. There is a demand for further improvement in various properties of the basic operation circuit due to the higher integration and lower power consumption of semiconductor integrated circuit devices. 
     Japanese Laid-Open Patent Publication No. 9-219636 discloses one example of an operational amplifier circuit. This conventional operational amplifier circuit will be described with reference to  FIG. 1 . 
     The operational amplifier circuit  10  includes a constant current source  11 , a current mirror circuit  12 , a differential input circuit  20 , and an output stage circuit  30 . The constant current source  11  supplies constant current I 1  to the current mirror circuit  12 . The current mirror circuit  12  includes N-channel MOS transistors N 1  and N 2 . The drain of the transistor N 1  is connected to the constant current source  11 . The sources of the transistors N 1  and N 2  are connected to a low potential power supply VS. The drain of the transistor N 1  is connected to the gates of the transistors N 1  and N 2 , and the drain of the transistor N 2  is connected to the differential input circuit  20 . 
     The differential input circuit  20  includes a differential pair  21  and a current mirror circuit  22 . The differential pair  21  includes N-channel MOS transistors N 3  and N 4 . A connection node between the sources of the two transistors N 3  and N 4  is connected to the drain of the transistor N 2 . The drains of the transistors N 3  and N 4  are respectively connected to the drains of P-channel MOS transistors P 1  and P 2  configuring the current mirror circuit  22 . The sources of the transistors P 1  and P 2  are connected to a high potential power supply VD, and the drain of the transistor P 2  is connected to the gates of the transistors P 1  and P 2 . 
     The gates of the transistors N 3  and N 4  configuring the differential pair  21  are respectively connected to first and second input terminals T 1  and T 2  and receive first and second input signals IP and IM, respectively. Therefore, the differential input circuit  20 , which is operated based on the bias current I 2  supplied from the transistor N 2 , changes the potential V 1  at node A between the transistors N 3  and P 1  and the potential V 2  at node B between the transistors N 4  and P 2  in a complementary manner by having current flow in accordance with the potential difference between the first and second input signals IP and IM. 
     The nodes A and B of the differential input circuit  20  are connected to the output stage circuit  30 . 
     The output stage circuit  30  includes P-channel MOS transistors P 3  and P 4  and a current mirror circuit  31 . The current mirror circuit  31  includes N-channel MOS transistors N 5  and N 6 . The gates of the transistors P 3  and P 4  are connected to the nodes B and A, respectively. Further, the node B is connected to the drain and the gate of the transistor P 2 . Therefore, the transistor P 3  and the transistor P 2  operate as a current mirror. 
     The source of the transistor P 3  is connected to the high potential power supply VD, and the drain is connected to the drain of the transistor N 5 . The transistor P 4 , which functions as a former transistor of a final output stage, has a source is connected to the high potential power supply VD and a drain connected to an output terminal To. Therefore, drain current I 6  corresponding to the gate voltage of the transistor P 4  is supplied to the output terminal To. 
     The transistor N 5  has the same element size as the transistor N 1  of the current mirror circuit  12 . Further, the transistor N 5  has a source connected to the low potential power supply VS and a drain connected to the transistor P 3  and the gates of the two transistors N 5  and N 6 . The transistor N 6  functions as a latter transistor in the final output stage. The transistor N 6  has a source connected to the low potential power supply VS and a drain connected to the output terminal To. The drain voltages of the two transistors P 4  and N 6  are output from the output terminal To as an output signal Vout. The transistor N 6  draws in drain current I 7  corresponding to the element size ratio of the transistor N 5  and the transistor N 6  from the output terminal To. 
     The operational amplifier circuit  10  receives the output signal Vout as the second input signal IM. That is, the second input terminal T 2  is connected to the output terminal To, and the operational amplifier circuit  10  operates as a voltage follower. The first input signal IP and the second input signal IM thus become equal when the gate voltage of the transistor P 3  and the gate voltage of the output transistor P 4  are the same, that is, when the same current is output to the nodes A and B of the current mirror circuit  22  configured by the transistors P 1  and P 2 . 
     SUMMARY OF THE INVENTION 
     The problems described below arise when the first input signal IP varies in the operational amplifier circuit  10  of  FIG. 1 . 
     When the first input signal IP increases and becomes higher than the second input signal IM, the potential V 1  at the node A decreases. Decrease in the potential V 1  at the node A, that is, decrease in the gate voltage of the transistor P 4  increases the output signal Vout. As a result, the potential of the output signal Vout becomes equal to the potential of the first input signal IP. In this manner, the operational amplifier circuit  10  operates to shift to a state in which the first input signal IP is equal to the output signal Vout (second input signal IM). 
     When the output signal Vout, or the second input signal IM, increases in a manner following the first input signal IP as described above, the potential V 2  at the node B also decreases in the same manner as the potential V 1  at the node A. The drain current I 5  of the transistor P 3  varies as the potential V 2  at node B varies, that is, as the gate voltage of the transistor P 3  varies. However, the drain voltage of the transistor P 3  (potential V 3  at node C) is dependent on the drain voltage of the transistor N 5  that operates as a diode. The drain voltage of the transistor N 5  is substantially constant irrespective of the current value of the drain current I 5 . The drain voltage of the transistor P 3  thus becomes substantially constant. This results in the drain current I 5  being substantially constant (see single-dashed line in  FIG. 4 ). 
     The drain current I 6  of the transistor P 4  decreases as the output signal Vout increases. The ratio between the drain current I 5  of the transistor P 3  and the drain current I 6  of the transistor P 4  changes from the ideal element size ratio. The transistor N 6  causes the flow of drain current I 7  having a current value corresponding to the element size ratio of the transistor N 5  and the transistor N 6  with the current mirror circuit  31 . The drain current I 6  of the transistor P 4  decreases as the output signal Vout increases. Thus, the supply current of the drain current I 6  of the transistor P 4  with respect to the required current value of the drain current I 7  of the transistor N 6  becomes insufficient and decreases the output signal Vout of the operational amplifier circuit  10 . As a result, a difference is created between the first input signal IP and the output signal Vout (second input signal IM). This generates an offset voltage. The drain current I 6  increases as the output signal Vout decreases. Thus, the drain current I 6  consequently becomes substantially constant (see single-dashed line in  FIG. 4 ) irrespective of the variation of the first input signal IP in the same manner as the drain current I 5 . 
       FIG. 2  is a graph showing the input and output characteristic of the first input signal IP and the output signal Vout in the operational amplifier circuit  10  of  FIG. 1 . The single-dashed line shows the ideal input and output characteristics of an operational amplifier circuit, and the solid line indicates the actual input and output characteristics of the operational amplifier circuit  10  shown in  FIG. 1 . As the first input signal IP becomes closer to the high potential power supply VD, the potential of the output signal Vout becomes lower than the ideal potential, that is, the first input signal IP. This increases the difference between the output signal Vout and the first input signal IP. In other words, the offset voltage increases as the first input signal IP becomes closer to the high potential power supply VD. 
     The present invention provides an operational amplifier circuit capable of suppressing the generation of the offset voltage. 
     One aspect of the present invention is an operational amplifier circuit for generating an output signal from a first input signal and a second input signal. The operational amplifier circuit has a differential input circuit including a first transistor for receiving the first input signal and generating a first voltage and a second transistor for receiving the output signal as the second input signal and generating a second voltage. An output stage circuit is connected to the differential input circuit and includes a third transistor responsive to the second voltage. A fourth transistor is operatively connected to the third transistor. A first node is formed between the third transistor and the fourth transistor. A fifth transistor is responsive to the first voltage. A sixth transistor is connected in series to the fifth transistor. The fourth transistor and the sixth transistor form a first current mirror. A second node is formed between the fifth transistor and the sixth transistor. The output signal is generated at the second node. A control circuit, connected to the differential input circuit and the output stage circuit, controls the potential at the first node using the first input signal. 
     Another aspect of the present invention is an operational amplifier circuit for generating an output signal from a first input signal and a second input signal. The operational amplifier circuit has a differential input circuit including a first transistor of a first conduction type for receiving the first input signal and generating a first voltage and a second transistor of the first conduction type for receiving the output signal as the second input signal and generating a second voltage. An output stage circuit is connected to the differential input circuit. The output stage circuit includes a third transistor of a second conduction type differing from the first conduction type and being responsive to the second voltage. A fourth transistor of the first conduction type is operatively connected to the third transistor. A fifth transistor of the second conduction type is responsive to the first voltage. A sixth transistor of the first conduction type is connected in series to the fifth transistor. The fourth transistor and the sixth transistor form a first current mirror. A first node is formed between the fifth transistor and the sixth transistor. The output signal is generated at the first node. A seventh transistor of the second conduction type is connected between the third transistor and the fourth transistor and is responsive to a control voltage corresponding to the first input signal. 
     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
         FIG. 1  is a circuit diagram of a conventional operational amplifier circuit; 
         FIG. 2  is a characteristic diagram showing the input and output characteristic of the operational amplifier circuit of  FIG. 1 ; 
         FIG. 3  is a schematic circuit diagram of an operational amplifier circuit according to a preferred embodiment of the present invention; 
         FIG. 4  is a characteristic diagram showing variation in the output current of the operation amplifier circuit of  FIG. 3 ; and 
         FIG. 5  is a diagram showing the frequency characteristics of the operational amplifier circuit of  FIGS. 1 and 3 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the drawings, like numerals are used for like elements throughout. 
     An operational amplifier circuit  1  according to a preferred embodiment of the present invention will now be described with reference to  FIGS. 3 and 4 .  FIG. 3  is a schematic circuit diagram of an operational amplifier circuit  1  according to a preferred embodiment of the present invention. 
     The operational amplifier circuit  1  includes a constant current source  11 , a current mirror circuit  12 , a differential input circuit  20 , an output stage circuit  30 , and a control circuit  40 . The constant current source  11  supplies constant current I 1  to the current mirror circuit  12 . The current mirror circuit  12  includes N-channel MOS transistors N 1  and N 2 . The drain of the transistor N 1  is connected to the constant current source  11 . The sources of the transistors N 1  and N 2  are connected to the low potential power supply VS, the drain of the transistor N 1  is connected to the gates of the transistors N 1  and N 2 , and the drain of the transistor N 2  is connected to the differential input circuit  20 . The transistor N 2  has an element size that is two times greater than that of the input transistor N 1 . Therefore, the current mirror circuit  12  supplies the differential input circuit  20  with bias current I 2  that is two times greater than the drain current of the transistor N 1 , that is, the constant current I 1  of the constant current source  11 . 
     The differential input circuit  20  includes a differential pair  21  configured by N-channel MOS transistors N 3  and N 4 , and a current mirror circuit  22  configured by a pair of P-channel MOS transistors P 1  and P 2 . The gate of the transistor N 3 , which is connected to the first input terminal T 1 , receives the first input signal IP provided to the first input terminal T 1 . The gate of the transistor N 4 , which is connected to the second input terminal T 2 , receives the second input signal IM provided to the second input terminal T 2 . The transistors P 1  and P 2  are of the same size. Thus, the transistor P 1  causes the flow of drain current having a current value that is the same as the drain current of the transistor P 2 . 
     A node A between the transistors N 3  and P 1  and a node B between the transistors N 4  and P 2  are connected to the gate of the transistor P 4  and the gate of the transistors P 3  of the output stage circuit  30 , respectively. The transistor P 3  has a source connected to the high potential power supply VD and a gate connected to the drain and the gate of the transistor P 2 . Therefore, the transistor P 3  and the transistor P 2  operate as a current mirror. The transistor P 3  has an element size that is the same as the transistor P 2  and causes the flows of drain current I 5  corresponding to the gate voltage of the transistor P 2  (potential V 2  at the node B). The transistor P 4 , which functions as a former transistor in the final output stage, has a source connected to the high potential power supply VD and a drain connected to the output terminal To. The transistor P 4 , which has an element size that is ten times greater than that of the transistor P 1 , supplies drain current I 6 , which corresponds to the element size and the gate voltage (potential V 1  of node A) of the transistor P 4 , to the output terminal To. 
     The drain and the gate of the transistor N 1  are connected to the gate of an N-channel MOS transistor N 11  (first constant current source) in the control circuit  40 . The transistor N 11  has a source connected to the low potential power supply VS and a drain connected to the source of an N-channel MOS transistor N 12 . That is, the transistor N 11  and the transistor N 1  operate as a current mirror. Therefore, the transistor N 11  supplies drain current I 11 , which corresponds to the element size ratio of the transistor N 1  and the transistor N 11 , to the transistor N 12 . 
     The source of the transistor N 12  is connected to the drain of the transistor N 11  and to the gate of a P-channel MOS transistor P 11 . The drain of the transistor N 12  is connected to the drain and gate of a P-channel MOS transistor P 12  that operates as a diode. The gate of the transistor N 12  is connected to the gate of the N-channel MOS transistor N 3  configuring the differential pair  21 . That is, the gate of the transistor N 12  receives the first input signal IP. 
     The drain of the transistor P 12  is connected to the gate of the transistor P 12  and to the drain of the transistor N 12 . The source of the transistor P 12  is connected to the high potential power supply VD. 
     The transistor P 11  has a gate, which is connected to a node D (the source of transistor N 12 ) between the transistor N 12  and the transistor N 11 , and a source, which is connected to the drain of the P-channel MOS transistor P 3 . The drain of the transistor P 11  is connected to the drain of the transistor N 5  of the current mirror circuit  31 . A connection point between the transistor P 11  and the transistor P 3  is defined as node C. In the preferred embodiment, the element size of the transistor N 12  and the transistor P 11  and the element size of the transistors N 11  and P 12  relative to the transistors P 3  and N 5  are set so that the gate-source voltage Vgs 1  of the transistor N 12  and the gate-source voltage Vgs 2  of the transistor P 11  are substantially equal. In the preferred embodiment, the control circuit  40  is configured by transistors N 11 , N 12 , P 1 , and P 12 . 
     The current mirror circuit  31  includes a pair of N-channel MOS transistors N 5  and N 6 . The transistor N 5  has the same element size as the transistor N 1  of the current mirror circuit  12 . The transistor N 5  has a source connected to the low potential power supply VS and a drain connected to the drain of the transistor P 11  and the gates of the two transistors N 5  and N 6 . The transistor N 6  functions as the latter transistor in the final output stage. The transistor N 6  has a source connected to the low potential power supply VS and a drain connected to the output terminal To. The drain voltages of the two transistors P 4  and N 6  are output from the output terminal To as the output signal Vout. The transistor N 6 , which has an element size that is ten times greater than that of the transistor N 5 , draws in drain current I 7  that is ten times greater than that of the drain current of the transistor N 5  from the output terminal To. 
     The operational amplifier circuit  1  receives the output signal Vout as the second input signal IM. Thus, the second input terminal T 2  is connected to the output terminal To, and the operational amplifier circuit  1  operates as a voltage follower. 
     The operation of the operational amplifier circuit  1  will now be discussed. 
     When the potentials at the first and second input signals IP and IM are substantially equal (IP=IM), the current mirror circuit  12  supplies the differential pair  21  with bias current I 2  having a current value that is two times greater than that of the constant current I 1  of the constant current source  11 . 
     The bias current I 2  is equally distributed to the transistors N 3  and N 4 . Thus, the drain currents I 3  and I 4  are substantially equal (I 3 =I 4 ) and have a current value that is one half the bias current I 2  (I 3 =I 4 =I 2 ×½=I 1 ). 
     The drain current I 5  of the transistor P 3  is substantially equal to the drain current I 4  of the transistor N 4  (I 5 =I 4 =I 1 ) due to the current mirror circuit  22  and the current mirror of the transistors P 2  and P 3 . The current mirror circuit  31  generates the drain current I 7  having a current value that is ten times greater than that of the drain current I 5  of the transistor N 5  (I 7 =I 5 ×10). 
     If the drain currents I 3  and I 4  are substantially equal, the potentials V 1  and V 2  at the nodes A and B, that is, the gate voltages of the transistors P 3  and P 4  are substantially equal. Thus, the drain currents I 5  and I 6  of the transistors P 3  and P 4  are determined by the element size ratio. In other words, the element size of the transistor P 4  is ten times greater than that of the transistor P 3  (transistors P 1  and P 2 ). Thus, the drain current I 6  of the transistor P 4  has a current value that is ten times greater than the drain current I 5  of the transistor P 3  (I 6 =I 5 ×10). 
     The drain current I 6  of the transistor P 4  and the drain current I 7  of the transistor N 6  are substantially equal (I 6 =I 7 =I 5 ×10). This stabilizes the potential at the output signal Vout. The second input signal IM is thus held at a potential that is substantially equal to the potential at the first input signal IP (IP=IM). 
     When the first input signal IP is higher than the second input signal IM (output signal Vout) (IP&gt;IM), the current mirror circuit  12  supplies the differential pair  21  with the bias current I 2  having a current value that is two times greater than the constant current I 1  of the constant current source I 1 . 
     The first input signal IP is higher than the second input signal IM. Thus, the differential pair  21  distributes the bias current I 2  to the transistors N 3  and N 4  such that a greater amount of current is distributed to the transistor N 3 . Therefore, the drain current I 3  of the transistor N 3  is greater than one half the bias current I 2  of the transistor N 2  (I 3 &gt;I 2 ×½=I 1 ). 
     When the drain current I 3  of the transistor N 3  increases and the drain current I 4  of the transistor N 4  decreases, the potential V 1  at the node A decreases and the potential V 2  at the node B increases (V 1 &lt;V 2 ). When the potential V 1  of the node A decreases, the gate voltage of the transistor P 4  decreases. Thus, the output signal Vout increases. Specifically, the output signal Vout increases in response to the voltage difference between the first input signal IP and the second input signal IM. The increase in the output signal Vout decreases the drain current I 6  of the transistor P 4 . 
     The drain current I 5  of the transistor P 3  at this point is as follows. First, the node D between the transistors N 11  and N 12  has a potential V 11  obtained by subtracting the gate-source voltage Vgs 1  of the transistor N 12  from the gate voltage of the transistor N 12  (potential at first input signal IP) (V 11 =IP−Vgs 1 ). The potential V 11  at the node D is supplied to the transistor P 11  as a gate voltage. Therefore, the node C has a potential V 3  obtained by adding the gate-source voltage Vgs 2  of the transistor P 11  to the gate voltage of the transistor P 11  (potential V 11  of the node D) (V 3 =V 11 +Vgs 2 =IP−Vgs 1 +Vgs 2 ). In the preferred embodiment, the gate-source voltage Vgs 1  of the transistor N 12  is set to be substantially the same as the gate-source voltage Vgs 2  of the transistor P 11  due to element size of each of the transistors N 5 , N 11 , N 12 , P 3 , P 11 , and P 12 , as described above. Therefore, the potential V 3  at the node C becomes substantially the same as the first input signal as shown by the following equation. 
     
       
         
           
             
                 
             
             ⁢ 
             
               
                 
                   
                     
                       V 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     = 
                     
                       IP 
                       - 
                       
                         Vgs 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         Vgs 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                 
               
               
                 
                   
                     = 
                     
                       IP 
                       - 
                       
                         Vgs 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       + 
                       
                         Vgs 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                 
               
               
                 
                   
                     = 
                     IP 
                   
                 
               
             
           
         
       
     
     The gate-source voltage Vgs 1  of the transistor N 12  is determined by the drain voltage and the drain current of the transistor N 12 . In other words, the gate-source voltage Vgs 1  of the transistor N 12  is determined by the drain voltage of the transistor P 12  and the drain current I 11  of the transistor N 11 . The gate-source voltage Vgs 2  of the transistor P 11  is determined by the drain voltage and the drain current of the transistor P 11 . In other words, the gate-source voltage Vgs 2  of the transistor P 11  is determined by the drain voltage of the transistor N 5  and the drain current I 5  of the transistor P 3 . 
     The potential V 3  at the node C, that is, the drain voltage of the transistor P 3  increases as the first input signal IP increases. In other words, the potential V 3  at the node C (drain voltage of the transistor P 3 ) becomes substantially equal to the voltage of the first input signal IP in a manner following the variation of the first input signal IP. This decreases the drain current I 5 . 
     The drain current I 5  and the drain current I 6  in this case will now be described in detail. The output signal Vout increases and the potential V 3  at the node C increases as the first input signal IP increases. Therefore, the drain voltage of the transistor P 3  and the drain voltage of the transistor P 4  become substantially equal. That is, the drain voltages of the transistors P 3  and P 4  both have the first input signal IP. The drain currents I 5  and I 6  of the transistors P 3  and P 4  thus have current values corresponding to their element sizes. That is, both drain currents I 5  and I 6  decrease as the first input signal IP increases while maintaining the current values at an ideal ratio of 1:10 (I 6 =I 5 ×10), as shown by the solid line in  FIG. 4 . More specifically, if the current value of the drain current I 5  is “E” when the first input signal IP is equal to the low potential power supply VS, the current value of the drain current I 6  becomes “10×E”. As the first input signal IP varies to the high potential power supply VD, the current value of the drain current I 5  decreases from “E” to “F”, and the current value of the drain current I 6  decreases from “10×E” to “10×F”. Thus, the drain currents I 5  and I 6  of the transistors P 3  and P 4  have small current values in the operational amplifier circuit  1  of the preferred embodiment as compared to the conventional operational amplifier circuit  10  (see single-dashed line in  FIG. 4 ) when the first input signal IP increases. This decreases the power consumption. 
     The current mirror circuit  31  generates the drain current I 7  with a current value that is ten time greater than the drain current I 5  of the transistor N 5  (I 7 =I 5 ×10). Therefore, the drain current I 6  of the transistor P 4  and the drain current I 7  of the transistor N 6  become equal (I 6 =I 7 =I 5 ×10) even if the first input signal IP increases. This stabilizes the potential of the output signal Vout, and the second input signal IM is held at a potential substantially equal to the first input signal IP (IP=IM). 
     When the first input signal IP is lower than the second input signal IM (potential of output signal Vout) (IP&lt;IM), the current mirror  12  supplies the differential pair  21  with bias current I 2  having a current value that is two times greater than the constant current I 1  of the constant current source  11 . 
     The first input signal IP is lower than the second input signal IM. Thus, the differential pair  21  distributes the bias current I 2  to the transistors N 3  and N 4  such that a greater amount of current is distributed to the transistor N 4 . Accordingly, the drain current I 3  of the transistor N 3  is less than one half the bias current I 2  of the transistor N 2  (I 3 &lt;I 2 ×  1 / 2 =I 1 ). 
     When the drain current I 3  of the transistor N 3  decreases, and the drain current I 4  of the transistor N 4  increases, the potential V 1  at the node A increases and the potential V 2  of the node B decreases (V 1 &gt;V 2 ). The gate voltage of the transistor P 4  increases when the potential V 1  at the node A increases. Therefore, the output signal Vout decreases. Specifically, the output signal Vout decreases in correspondence with the voltage difference between the first input signal IP and the second input signal IM. The decrease in the output signal Vout increases the drain current I 6  of the transistor P 4 . 
     The potential V 3  at the node C between the transistors P 3  and P 11  becomes substantially equal to the voltage of the first input signal IP (V 3 =IP) in a manner following the variation of the first input signal IP, as described above. Therefore, the potential V 3  at the node C, that is, the drain voltage of the transistor P 3  decreases as the first input signal IP decreases. This increases the drain current I 5 . 
     In this manner, the output signal Vout and the potential V 3  at the node C decreases as the first input signal IP decreases. Therefore, the drain voltage of the transistor P 3  and the drain voltage of the transistor P 4  become substantially equal, that is, the drain voltages of the transistors P 3  and P 4  both have the first input signal IP. For this reason, the drain currents I 5  and I 6  of the transistors P 3  and P 4  have current values corresponding to their element size. That is, the drain currents I 5  and I 6  both increase as the first input signal IP decreases while maintaining the ideal current value ratio of 1:10 (I 6 =I 5 ×10). 
     The current mirror circuit  31  generates the drain current I 7  having a current value that is ten times greater than that of the drain current IS of the transistor N 5  (I 7 =I 5 ×10). Therefore, the drain current I 6  of the transistor P 4  and the drain current I 7  of the transistor N 6  become equal (I 6 =I 7 =I 5 ×10) even if the first input signal IP decreases. This stabilizes the potential of the output signal Vout and holds the second input signal IM at a potential substantially equal to the first input signal IP (IP=IM). 
       FIG. 5  is a graph showing a simulation result regarding the frequency characteristic of the operational amplifier circuit  1  shown in  FIG. 3  and the operational amplifier circuit  10  shown in  FIG. 1 . The simulation was performed with the operational amplifier circuits  1  and  10  having the same power consumption. In  FIG. 5 , the horizontal axis represents the first input signal IP, and the vertical axis represents the unit gain frequency. 
     As apparent from  FIG. 5 , the unit gain frequency of each of the operational amplifier circuits  1  and  10  varies so as to increase when the first input signal IP approaches the high potential power supply VD. However, the frequency of the operational amplifier circuit  1  varies more gradually than the operational amplifier circuit  10 . More specifically, the range of unit gain frequency variation caused by the variation of the first input signal IP is small in the operational amplifier circuit  1  of the present invention compared to the conventional operational amplifier circuit  10 . That is, the difference between the unit gain frequency when the first input signal IP reaches the high potential power supply VD and the unit gain frequency of when the first input signal IP reaches the low potential power supply VS is small in the operational amplifier circuit  1 . Therefore, the change in responding speed caused by variation of the first input signal IP is small in the operational amplifier circuit  1 . This stabilizes the responding speed. 
     Furthermore, the unit gain frequency when the first input signal IP reaches the low potential power supply VS is largely increased in the operational amplifier circuit  1  of the present invention compared to the conventional operational amplifier circuit  10 . Therefore, the responding speed of the operational amplifier circuit  1  is significantly increased by adding the transistors N 11 , N 12 , P 1 , and P 12 , that is, the control circuit  40 . 
     The operational amplifier circuit  1  of the embodiment has the following advantages. 
     (1) The P-channel MOS transistor P 11  is arranged between the transistor P 3  and the transistor N 5 , and the first input signal IP is provided to the gate of the transistor P 11  via the N-channel MOS transistor N 12 . Thus, the potential V 3  at the node C varies in a manner following the variation of the first input signal IP. Furthermore, the element size of each of the transistors N 5 , N 11 , N 12 , P 3 , P 11 , and P 12  is determined so that the gate-source voltages Vgs 1  and Vgs 2  of the transistors N 12  and P 11  are substantially equal. The potential at the output signal Vout thus stabilizes even if the first input signal IP varies, in particular, even if the first input signal IP approaches the high potential power supply VD due to increase in the first input signal IP. Therefore, the first input signal IP and the second input signal IM are maintained at substantially the same potential (IP≈IM). Thus the operational amplifier circuit  1  suppresses the generation of offset voltage caused by variation of the first input signal IP. 
     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms. 
     The P-channel MOS transistor P 12  in the above embodiment may be omitted. That is, the drain of the N-channel MOS transistor N 12  may be directly connected to the high potential power supply VD. 
     The P-channel MOS transistor P 11  in the above embodiment may be changed to an N-channel MOS transistor, and the N-channel MOS transistor N 12  may be changed to a P-channel MOS transistor. 
     The N-channel MOS transistors N 11  and N 12  and the P-channel MOS transistor P 12  in the above embodiment may be omitted. That is, the first input terminal T 1  may be directly connected to the gate of the P-channel MOS transistor P 11 . In this case, the P-channel MOS transistor P 11  may be changed to the N-channel MOS transistor. 
     The transistors P 3 , P 4 , N 5 , and N 6  configuring the output stage circuit  30  in the above embodiment may be configured by the P-channel MOS transistor or the N-channel MOS transistor. 
     In the above embodiment, the P-channel MOS transistors configuring the operational amplifier circuit  1  may each be changed to an N-channel MOS transistor, and the N-channel MOS transistors configuring the operational amplifier circuit  1  may each be changed to a P-channel MOS transistor. Needless to say, in this case, the high potential power supply VD and the low potential power supply VS are exchanged with each other. 
     The control circuit of the present invention is not limited to the control circuit  40  shown in  FIG. 3 . In a further embodiment, the control circuit may be formed, for example, by a variable resistor connected between the transistor P 3  and the transistor N 5 . In such control circuit, the resistance value of the variable resistor changes in accordance with the variation of the first input signal IP. More specifically, the control circuit increases the resistance value of the variable resistor as the first input signal IP increases and decreases the resistance value of the variable resistor as the first input signal IP decreases. Thus, the drain voltage of the transistor P 3  varies as the first input signal IP varies without being dependent on the voltage of the diode connected transistor N 5 . As a result, the same advantages as the above embodiment are obtained. 
     Each transistor in the above embodiment is not limited to a MOS transistor and may be a bipolar transistor. 
     The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.