Abstract:
A method for fast static compaction in sequential circuits with finite output states by removing subsequences of test vectors from a vector test set. The method has the following steps: (1) relaxing the output states of the sequential circuits; (2) identifying a candidate subsequence of test vectors from the vector test set for removal; (3) temporarily removing the candidate subsequence of test vectors from the vector test set; (4) performing fault simulation on remaining test vectors from the vector test set; (5) examining fault simulation results against a set of removal criteria; (6) permanently removing the temporarily removed candidate subsequence if said set of removal criteria are met; (7) replacing the temporarily removed candidate subsequence if said set of removal criteria are not met; and (8) repeating steps (1) through (7) until all candidate subsequences of test vectors have been identified.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a method for compacting test sets for sequential circuits. More specifically, to a state relaxation based subsequence removal method for fast static compaction in sequential circuits. 
     This application relates to U.S. application Ser. No. 09/001,542 filed on Oct. 31, 1997 entitled, &#34;Partitioning and Recording Methods for Static Test Sequence Compaction of Sequential Circuits,&#34; which is assigned to the Assignee of the present invention and which is incorporated herein by reference. 
     2. Background and Description of Related Art 
     Test application time (TAT) of sequential circuits is proportional to the number of test vectors in a test set and directly impacts the cost of testing. Thus, shorter test sequences are desired. Two types of compaction techniques exist: dynamic and static compaction. Dynamic techniques perform compaction concurrently with the test generation process and often require modification of the test generator. Static test sequence compaction, on the other hand, is a post-processing step after test generation. Static techniques are independent of the test generation algorithm and require no modification of the test generator. Even if dynamic compaction is performed during test generation, static compaction can further reduce the test set size obtained after test generation. 
     Several static compaction approaches for sequential circuits have been proposed in the following papers: Niermann, T. M., et al. &#34;Test Compaction for Sequential Circuits,&#34; IEEE Trans. Computer-Aided Design, vol. 11, no. 2, pp. 260-67, February 1992, So, B., &#34;Time-efficient Automatic Test Pattern Generation System,&#34; Ph.D. Thesis, EE Dept. Univ. of Wisconsin-Madison, 1994, Pomeranz, I., et al., &#34;On Static Compaction of Test Sequences for Synchronous Sequential Circuits,&#34; Proc. Design Automation Conf., pp. 215-20, June 1996 and Hsiao, M. S. et al., &#34;Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors,&#34; Proc. IEEE VLSI Test Symp., pp. 188-195, April 1995. 
     Recent proposals include overlapping and reordering of test sequences obtained from targeting single faults to achieve compaction (Niermann and So). However, these approaches cannot be used on test sequences produced by random or simulation-based test generators. 
     Static compaction based on vector insertion, omission, or selection has also been investigated (Pomeranz). These methods require multiple fault simulation passes. They eliminate vectors from a test set without reducing the fault coverage that can be obtained using the original test set. When a vector is to be omitted or swapped, the fault simulator is invoked to make sure that the fault coverage is unaffected by the alteration to the test sequence. Very compact test sets can be achieved at the expense of prohibitively long execution times. 
     A fast static compaction technique for sequential circuits based on removing subsequences of test vectors was reported recently (Hsiao). This approach is based on two observations: (1) test sequences traverse through a small set of states that are frequently re-visited, and (2) subsequences corresponding to cycles may be removed from a test set under certain conditions. However, if test sets have few or no states that are re-visited, then the subsequence removal algorithm performs poorly. FIG. 1 is a table showing the number of vectors and states traversed by the HITEC test sets for some ISCAS89 benchmark circuits. Information regarding these test sets and circuits can be found in the following papers: Niermann, T. M., et al., &#34;HITEC: A Test Generation Package for Sequential Circuits,&#34; Proc. European Conf. Design Automation (EDAC), pp. 214-18, 1991, Niermann, T. M., et al., &#34;Method for Automatically Generating Test Vectors for Digital Integrated Circuits,&#34; U.S. Pat. No. 5,377,197, 1994, and Brglez, F., et al., &#34;Combinational Profiles of Sequential Benchmark Circuits,&#34; Int. Symposium on Circuits and Systems,&#34; pp. 1929-34, 1989. Similar trends are seen in test sets generated by other test generators. 
     SUMMARY OF THE INVENTION 
     Consider a test set T that has no state that is re-visited. Therefore, the test set has no cycles. Obviously, the subsequence removal algorithm reported in Hsiao will not be able to compact the test set. However, by using state relaxation, one can identify a subsequence that may be removed. For example, assume that the test set T transfers a finite state machine from state S initial  to S final  without repeating any states. If T sub  is a subsequence of test set T that transfers the finite state machine from state S i  to state S j , states S i  and S j  must be different since the test set has no cycles. It is possible that not all specified values in state S i  are essential to reach state S j  using subsequence T sub . Therefore, state S i  can be relaxed by unspecifying the non-essential bits in state S i . Similarly, not all bits in state S j  need to be specified in order to transfer the machine to state S final . 
     Without loss of generality, assume that S i  and S j  are 10110 and 00100, respectively. Assuming that state S j  can be relaxed to X01X0, then the first and the fourth state bits (flip-flop values) are unspecified. State relaxation ensures that if T sub  is removed from the test set, then it will still be possible to transfer the machine to the state S final  using the modified sequence. Removal of a subsequence T sub  means that vectors V i  . . . V j-1  will be removed from test set T. Note that the last vector (vector V j ) of subsequence T sub  is still part of the test set. Stated differently, the relaxed S j  now covers state S i , and the subsequence T sub  has created a cycle that may be removed to achieve compaction. 
     Relaxation of states can be computed efficiently using a support-set algorithm, such as the one described in the paper by A. Raghunathan, entitled, &#34;Acceleration Techniques for Dynamic Vector Compaction,&#34; Proc. Intl. Conf. Computer-Aided Design, pp. 310-17, 1995. Support-sets can be computed in linear time and space complexity, thus making the relaxation approach very feasible. If the test set has cycles, then state relaxation can be used to find larger cycles. The size of a cycle is the number of vectors in the subsequence causing the cycle. 
     The basic steps of the invention are to: (1) relax the output states of the machine; (2) identify a candidate recurrent subsequence for removal; (3) perform a fault simulation analysis to determine if the subsequence can be removed; (4) remove the subsequence and/or identify the next candidate recurrent subsequence for removal. 
     The present invention has several advantages. Test sets that could not be compacted by existing subsequence removal techniques due to absence of cycles can now be compacted. The size of cycles in a test set can be significantly increased by state relaxation, and removal of the larger sized cycles leads to better compaction. The invention requires only two fault simulation passes as compared to trial and re-trial methods that require multiple fault simulation passes. significantly higher compaction is achieved in short execution times as compared to currently known subsequence removal methods. Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the invention consistently results in significantly higher compaction in short execution times when compared with known subsequence removal methods. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a table showing the number of states traversed by HITEC test sets. 
     FIG. 2 is diagram of ISCAS89 sequential benchmark circuit s27. 
     FIG. 3(a) is a diagram showing fault-effects entering and exiting a subsequence being identical. 
     FIG. 3(b) is a diagram showing fault-effects entering and exiting a subsequence being different. 
     FIG. 4 is a diagram showing the removal of a relaxed subsequence. 
     FIG. 5(a) is a diagram showing fault-free state relaxation. 
     FIG. 5(b) is a diagram showing fault masking after removing a subsequence. 
     FIG. 6 is a chart showing application of the present invention on a set of test vectors. 
     FIG. 7 is a table showing compaction results for HITEC test sets. 
     FIG. 8 is a table showing compaction results for STRATEGATE test sets. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The preferred embodiments will be described below with reference to the figures and the following examples. Given a sequential circuit test vector set T consisting of n vectors V1 . . . V n , the subsequence from the i th  vector to the j th  vector (0≦i≦j≦n) of T is represented as T[V i , V i+1 , . . . , V j  ]. Here, V i  and V j  are the i th  and j th  vectors in the test vector set T, respectively. Key terms are described in the following paragraphs. 
     A recurrent subsequence (T rec ) transfers a finite state machine from a given initial state to the same state. Essentially, T rec  re-visits the initial state of the finite state machine. This subsequence is responsible for traversing a cycle in the state diagram of the finite state machine. 
     A recurrent subsequence is an inert subsequence (T inert ) if no faults are detected within the subsequence during fault simulation, with fault dropping, of the test set T. Fault dropping means that as the test set is compacted, faults that are detected by test vectors that will remain in the final compacted test vector set are excluded from the pool of faults that must be detected by the remaining uncompacted test vectors. Inert subsequences can be removed from the test set without adversely affecting the fault coverage under certain conditions. See for example, Hsiao cited above. 
     Flip-flops that are assigned the don&#39;t care value of X are considered to be unspecified. If state S i  is partially specified, then an exhaustive set of states can be obtained by enumerating don&#39;t care (unassigned) values of S i . For example, state X01 is partially specified and it represents two states 001 and 101. 
     State S j  covers state S i  if the group of states represented by S i  are a subset of states represented by S j . For example, consider two states S 1  and S 2  that are represented by bit vectors X01 and 00X, respectively. State S 1  does not cover state S 2 . This is because state S 2  represents two states 000 and 001 and state S 1  does not include the state 000. If states S 1  and S 2  are fully specified, then S 1  covers S 2  only when S 1  and S 2  are identical. 
     A flip-flop is relaxed if its value is changed from 0 or 1 to a don&#39;t care value X. 
     Consider states S i , S j  and their relaxations S i   R ,S j   R . State S j   R  strictly covers the relaxed state S i   R  if S j   R  covers unrelaxed state S i . Note that S j   R  may or may not cover S i   R . For example, let S j   R  be X01 and S i   R  be 00X. S j   R  does not cover S i   R . However, if S i  was 001 before relaxation, then S j   R  covers S i . Therefore, S j   R . strictly covers S i   R . 
     Consider two relaxed states S i   R  and S j   R . A relaxed recurrent subsequence T relaxed .sbsb.-- rec  transfers a finite state machine from state to state S i   R  to state S j   R  such that S j   R  strictly covers S j   R . 
     A relaxed inert subsequence T relaxed .sbsb.-- insert  is a relaxed recurrent subsequence if no faults are detected within the subsequence during fault simulation (with fault dropping) of the test set T. 
     Given a state S i , its relaxation can be computed by deriving support sets. Methods for deriving support sets are well known. See for example, Raghunathan, A., et al., &#34;Acceleration techniques for dynamic vector compaction,&#34; Proc. Intl. conf. Computer-Aided Design, pp. 310-17, 1995, which is incorporated herein by reference. Consider an input vector that produces a response v (0 or 1) at a primary output Z of a combinational circuit. The input vector may or may not be fully specified. A vector is not fully specified if some of the primary inputs are unspecified (these inputs are assigned the don&#39;t care value X). A support set of the primary output Z is any set of signals (including primary inputs) that satisfy all the following conditions: 
     SS1 All signals in the set assume a logic value 0 or 1 (i.e., no signal may assume the unknown value). 
     SS2 The primary output Z is a member of the set. 
     SS3 The logic value on any signal other than a primary input signal in the support set is uniquely determined only by logic values of other signals in the support set. 
     A support set is minimal if no signal in the set can be deleted without violating conditions SS2 or SS3 . The minimum support set is the support set of least cardinality. The minimum support set is also minimal, but the converse is not true. 
     An input vector can cause several primary outputs of a circuit to assume known values. In the case of multiple primary outputs, condition SS2 is modified to require that each of the primary outputs be included in the support set. Support sets can be used to compute the set of flip-flop values in the present state that are sufficient to produce the desired next state for any given input vector. 
     Consider the ISCAS89 sequential benchmark circuit s27 shown in FIG. 2. This circuit has four primary inputs (G1, G2, G3 and G4), one primary output (G17) three flip-flops (G5, G6and G7) and intermediate logic elements G4, G8, G9, G10, G11, G12, G13, G14, G15and G16. Let inputs to the circuit be represented by the vector &lt;G1, G2, G3, G4&gt;. The state of the sequential circuit is given by the vector &lt;G5, G6, G7&gt;. If the initial state of the circuit is 100 and an input vector 1X10 is applied, the circuit produces an output value of 1. The input vector transfers the sequential circuit to the state 100. Logic simulation shows th at the same next-state and primary output value can also be obtained if the initial state of the machine were any one of the following three states: 101, 110 or 111. This example shows that for a given input vector, there may be several initial states that will transfer the sequential circuit to the same next-state and primary output values. The set of initial states for the example can be re presented succinctly by the state vector 1XX. This state is the relaxation of all four initial states. 
     State relaxation provides a significant advantage during fault simulation. A fault effect at a flip-flop with relaxed value cannot be propagated to any primary output or flip-flop. This is because a value of 0 or 1 on a relaxed flip-flop has no impact on primary outputs or next-state values. Consider again the example circuit s27 of FIG. 2. A fault-effect cannot be propagated on the relaxed flip-flop G7 to the primary output or flip-flops. This is because a controlling value G16=0 blocks propagation of a fault effect to the primary output or flip-flops G5 and G6 , and a controlling value of G3=1 prevents propagation of a fault effect to the flip-flop G7. 
     State relaxation can be achieved using several approaches. Support sets are used to derive the relaxed state efficiently. Support set computation has a linear time and space complexity. Consider again the circuit s27 shown in FIG. 2. Signal (G3=1) alone is a support set for the assignment (G13=0). On the other hand, signals (G5=1, G9=1, G16=0, G4=0, G8=0, G14=0, G1=0) together form a possible support set for (G11=0). 
     Ideally, one should consider states for relaxation in reverse order of their appearance during logic simulation of test set T. This maximizes the number of relaxed flip-flop values. Consider a test set T[V 1 , . . . , V n  ] and let S i  (1≦i≦n) be the state of the machine when vector V i  is simulated. States can be relaxed in the order S n  . . . S 1  to maximize relaxed values. Since next-state values on flip-flops determine the extent of relaxation possible for the present state, it is useful to relax state S j  first before considering all states S i , 1≦i&lt;j. The cost of memory storage for reverse order relaxation, however, is extremely high. This requires storage of logic values of signal values for all vectors in test set T. 
     An alternative and less expensive approach is to relax states in the same order as they are visited during logic simulation of test set T. This means that each state is relaxed with respect to the fully-specified next-state, because the next-state has not yet been relaxed. 
     Iterative relaxation of states over the entire test set several times can further reduce the number of flip-flops in the support sets. The first iteration relaxes each state with respect to the fully-specified next-states, the second iteration further relaxes every state by computing corresponding support sets with respect to the already relaxed successive states computed in the first iteration, and so on. However, iterative relaxation of states increases execution times. Experimental results show that minimal support sets based on the successive fully-specified states are sufficient to significantly compact test sets. 
     A flip-flop has a fault effect if it has a different Boolean (0 or 1) value for the good and faulty circuit. If a flip-flop has a value of 1 (0) in the good circuit and a value of 0 (1) in the faulty circuit, this combination of values is represented as D (D). Flip-flops can already have fault effects before the application of the first vector in the subsequence T sub . Similarly, flip-flops can have fault effects after the application of the subsequence. 
     Consider an inert subsequence T sub . This subsequence may be removed from the test set without any reduction in fault coverage under certain conditions. If fault-effects on flip-flops before and after the application of the inert subsequence are identical (see FIG. 3(a)), then the subsequence can be safely removed. However, it is possible that fault effects before and after the application of the subsequence may differ (see FIG. 3(b)). In this situation, further analysis is required before the subsequence can be removed. 
     For example, consider a flip-flop that has no fault effect before the application of the subsequence, however, it exhibits a fault effect after simulation of the subsequence. Removal of the subsequence is possible only if it can be established that the fault effect cannot be propagated to a primary output by the remaining vectors in test set T. 
     A recurrent subsequence can be removed if it satisfies (1) all conditions specified for an inert subsequence, and (2) faults detected within the subsequence can also be detected elsewhere in the test set T. 
     The basic subsequence removal algorithm is described below: 
     basic --  subsequence --  removal() 
     /* FIRST FAULT Simulation PASS */ 
     Collect recurrent &amp; inert subsequences 
     /* SECOND FAULT SIMULATION PASS */ 
     For each subsequence T subi  collected 
     If any of the removal criteria satisfied 
     Remove T subi  from the test set 
     The algorithm consists of two passes. The first fault simulation pass is used to identify and collect inert and recurrent subsequences assuming a fault-free machine. The second fault simulation pass checks to see if inert and recurrent subsequences satisfy all conditions specified for the removal of the subsequences by analyzing machines with faults. The two-pass algorithm has significant storage savings since faulty states have to be recorded only in the second pass. Faulty states are recorded only at the boundaries of each inert or recurrent subsequence. 
     Consider a subsequence T sub  consisting of vectors V i  . . . V j . Let S i  be the initial state of the machine when vector V i  is simulated during logic simulation of the subsequence. Consider the case illustrated in FIG. 4, the subsequence T sub  is not a recurrent subsequence because the initial state S i  (1011) differs from the final state S i+1  (0110) of subsequence T sub . Assume that state relaxation allows the first flip-flop of state S i  and second flip-flop value of state S j  to be relaxed (i.e., relaxation of these flip-flops indicates that these flip-flop values are not necessary to reach the corresponding next-states S i+1  or S j+1 , respectively). Note that the relaxed state S j   R  strictly covers relaxed state S i   R  since the unrelaxed value of the first flip-flop in S i  is 1. If T sub  were to be removed from the test set, state S j+1  is still reachable by applying vector V j+1  when the present state of the circuit is S i  instead of S j . If no faults are detected within T sub , T sub  is simply a relaxed inert subsequence, and its removal will not affect the fault coverage, provided that boundary conditions described in the detailed example below. Even if faults are detected within T sub , T sub  can still be removed if faults detected within the subsequence can also be detected by other vectors in the test sequence. 
     The relaxed subsequence removal technique also requires two fault simulation passes. In the first pass, fault-free states traversed by the test set are relaxed. This pass also identifies relaxed inert and recurrent subsequences. In the second fault simulation pass, boundary conditions for removal of each relaxed inert or recurrent subsequences are examined. 
     Fault masking can occur within an inert subsequence. It is also possible that a relaxed inert subsequence will mask a fault. Note that a relaxed inert subsequence can mask a fault even when the corresponding inert subsequence does not mask a fault. Consider the example shown in FIGS. 5(a) and 5(b), with the subsequence T sub  composed of vectors V i  . . . V j . A few flip-flop values of interest are shown for states S i  and S j  in FIG. 5(a). Values of these flip-flops in the faulty circuit are shown in FIG. 5(b). A flip-flop value is shown as D (D) if it assumes a value of 1 (0) in the good circuit, and a value of 0 (1) in the faulty circuit. During fault simulation, assume the two flip-flops in state S i  have fault effects of D and D, respectively. The AND gate does not exhibit a fault effect since fault effects at the inputs of the AND gate mask each other. However, during the course of simulation of T sub , it is possible that both flip-flops have identical fault effects of are resulting in the propagation of the fault effect across the AND gate. In this case, the fault effects are not mask ed by the AND gate, and the fault effect produced at the output of the AND gate may further propagate to a primary output. 
     Next the state relaxation scenario is considered. Assume that state relaxation of state results in the state S j   R  shown in FIG. 5(a). Removal of the subsequence T subi  implies that vectors V i  . . . V j-1  will be removed. Therefore, vector V j  will be applied with a present state of S i  after subsequence removal (FIG. 5(b)). In the modified sequence, no fault effect will appear at the output of the AND gate due to fault masking. Although this situation is rare, the fault coverage after test sequence compaction may be slightly lower due to fault masking. 
     Next a more detailed example of the method will be describe with reference to FIG. 6. Assume that the test set consists of 15 test vectors (Part A). The Output State column reflects the primary output of a fault-free machine after each test vector has been applied. Note that test vectors 3 through 12 represent a recurrent subsequence because the output state of the machine is the same after application of both test vectors 3 and 12. Note that test vectors 2 through 11 are also a recurrent subsequence. 
     The first step is to relax the output states. The Relaxed State column shows the results of the relaxation. The next step is to identify candidate subsequences for removal by identifying relaxed recurrent subsequences. One such subsequence comprises test vectors 2 through 14. Note that relaxation has allowed a larger candidate subsequence to be identified. 
     The boundary conditions of this candidate subsequence must now be examined to see if it can be removed. First, test vectors 2 through 13 are removed from the test set as shown in part B. Then fault simulations are performed for all identified faults (5 in this example) and the output states are relaxed. If the application of test vector 14 creates the same output state for each fault as the machine with no faults (the relaxed state column), the boundary conditions are met and the candidate subsequence can be removed permanently from the set of test vectors. However, as shown in Part B, application of test vector 14 with fault 2 creates a different output state (00). 
     This does not mean that the subsequence cannot be removed, however, further analysis is required. The subsequence can still be removed if fault 2 is found by another subsequence of test vectors or if fault 2 would never be found by any of the test vectors in the set. Note that nearly all test vector sets will not detect all faults in a machine. If neither of these conditions are met, the candidate subsequence cannot be removed and the next candidate subsequence is analyzed. 
     In this example, another candidate subsequence comprises test vectors 2 through 13. Part C shows the results of fault simulation after test vectors 2 through 12 have been removed. Note that after fault simulation, application of test vector 14 creates the same output state as the machine with no faults (the relaxed state column). Therefore, the boundary conditions are met and the candidate subsequence can be removed permanently from the set of test vectors. 
     This process continues until all candidate subsequences have been examined. 
     Experimental Results 
     The relaxed recurrent subsequence algorithm was implemented in C. ISCAS89 sequential benchmark circuits and several synthesized circuits were used to evaluate the effectiveness of the algorithm. All experiments were performed on a Sun UltraSPARC with 256 MB RAM. Test sets generated by two test generators (HITEC and STRATEGATE) were statically compacted. HITEC is a deterministic test generator for sequential circuits, while STRATEGATE employs genetic algorithms for generating test vectors. 
     The compaction results for HITEC and STRATEGATE test vectors are shown in FIGS. 7 and 8, respectively. The total numbers of faults for the circuits are shown in FIG. 7 only. The original numbers of vectors and fault coverages are shown for each table, followed by the compaction results for the previous approach described in the Hsiao article referred to above, and this invention, including fault coverages after compaction, percent reduction of original test set sizes, and execution times in seconds. The compaction schemes involve the combined approach of inert-subsequence removal followed by the recurrent-subsequence removal for all test sets. The execution times for the relaxed recurrent-subsequence removal algorithm are slightly longer than those for the non-relaxed removal algorithm. This is because of the extra times needed for computing support sets and for considering more candidate subsequences that have become eligible for removal. 
     For most circuits, a significant reduction in test set size was observed. For instance, in circuits s1488 and s1494, reductions for HITEC test vectors increased from 7.95% to 34.2% and 8.67% to 42.7%, respectively. For s35932, the reductions increased from 4.44% to 40.0%! Similar trends are seen for many other circuits as well. In circuits s1423 and s5378, the original number of vectors in the HITEC test set are small with low fault coverages; thus, they were not considered. 
     Significant reductions are obtained for the STRATEGATE test vectors, too. For instance, in the s1423 test vectors, the reductions in test set was 23% over the original technique, which already achieved 38.1%, without decrease in fault coverage. In circuits s298 and s344, for instance, the relaxed recurrent-subsequence removal increased test set reductions from 0% to 7.7% and 8.1% to 25.6%, respectively for these two circuits. 
     Note that some of the compacted test set vectors produced slightly lower fault coverages than those of the original test sets. This is due to the fault masking phenomenon. This problem was also present in the original subsequence removal compaction technique described in Hsiao cited above. Nevertheless, the drop in fault coverages is marginal. 
     A static test set compaction framework based on relaxed recurrent-subsequence removal has been described. Significant reductions in test set size over previously known techniques are obtained in short execution times. Sufficient conditions for removing subsequences have been identified that begin and end on different fully-specified states, without adversely affecting the fault coverage. As opposed to trial and re-trial based approaches to static compaction, only two fault simulation passes are required in this compaction technique. As a result, large test sets and circuits can be quickly processed by using this technique. Furthermore, the state relaxation technique is a general approach that can also be used to significantly augment many recently proposed static compaction approaches. 
     While the above is a description of the invention in its preferred embodiments, various modifications and equivalents may be employed. Therefore, the above description and illustration should not be taken as limiting the scope of the invention which is defined by the claims.