Abstract:
Provided are an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. Since a finite state machine (FSM) for generating a stop signal and an FSM for generating a control signal that controls a swap operation, a shift operation, and a polynomial operation for each basic cell of the modified Euclidean algorithm are used, an area-efficient RS decoder can be realized without using a conventional degree computation unit for comparing and calculating degrees.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2007-0045111, filed on May 9, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. 
         [0004]    This present invention is derived from a research project supported by the Information Technology (IT) Research &amp; Development (R&amp;D) program of the Ministry of Information and Communication (MIC) and the Institute for Information Technology Advancement (IITA) [2006-S-060-01, OTH-based 40G Multi-service Transmission Technology]. 
         [0005]    2. Description of the Related Art 
         [0006]    Reed-Solomon (RS) code is a forward error correction (FEC) code used in a wide variety of applications such as magnetic storage media, optical storage media, wired communication, and satellite communication. RS code is typically expressed as RS(n,k,t), where n denotes the number of code symbols, k denotes the number of data symbols, t denotes the number of symbols whose error can be corrected, and t=(n-k)/2. Accordingly, in the case of a RS( 255 , 239 ), t=8. 
         [0007]      FIG. 1  is a block diagram of a conventional RS decoder. 
         [0008]    Referring to  FIG. 1 , a syndrome polynomial computation (SC) block generates a syndrome polynomial S(x) and represents an error pattern of a received codeword. The syndrome polynomial S(x) is input to a key-equation solver (KES) block of the RS decoder. The KES block solves a key equation S(x)σ(x)=ω(x)mod x2t using any one of a Euclidean algorithm, a modified Euclidean algorithm, and a Berlecamp-Massay algorithm, which are for obtaining an error locator polynomial σ(x) and an error value polynomial ω(x). 
         [0009]    Since the Euclidean algorithm is used to compute inverse elements of a Galois field, the Euclidean algorithm requires a look-up table (LUT) stored in a read-only memory (ROM). However, since the modified Euclidean algorithm does not require such LUT, the modified Euclidean algorithm can reduce a latency caused by the use of the LUT. Also, since the modified Euclidean algorithm can use a systolic-array structure, the modified Euclidean algorithm can faster and more easily pipeline blocks than the Berlecamp-Massay algorithm. 
         [0010]    The polynomials σ (x) and ω(x) are input to a Chien search block and a Forney algorithm operation block to calculate locations and values of errors. 
         [0011]    The modified Euclidean algorithm used in the KES block set initial values as shown in Equation 1 to obtain the error locator polynomial σ(x) and the error value polynomial ω(x) by erasing a highest degree term and iteratively reducing degrees. In Equation 1, S(x) denotes the aforesaid syndrome polynomial. 
         [0000]        R   0 (x)=x 2t   , Q   0 ( x )= S ( x ),  L   0 ( x )=0 , U   0 ( x )=1   (1). 
         [0012]    Equations 2 and 3 show values of polynomials R i (x), Qi(x), L i (x), and U i (x), which are to be recursively calculated i times. In Equations 2 and 3, a i  and b i  respectively denote coefficients of highest degree terms of the polynomials R i (x) and Q i (x), and the values of the polynomials R i (x), Q i (x), L i (x), and U i (x) are determined by the degrees of polynomials R i−1 (x) and Q i−1 (x), wherein deg(R i (x)) and deg(Q i (x)) respectively denote degrees of the polynomials R i (x) and Q i (x). When deg(R i (x))&lt;deg(L i (x)), the recursive operation stops, and the polynomials R i (x) and L i (x) at this time become an error value polynomial and an error locator polynomial, respectively. 
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         [0013]    The modified Euclidean algorithm recursively solves Equation 2 through Equation 4, whereas a conventional method calculates degrees of the two polynomials R i−1 (x) and Q i−1 (x) to obtain I i−1 , of Equation 4 and generates a control signal to quickly solve Equations 2 and 3. The control signal includes a stop signal for stopping the recursive operation when deg(R i (x))&lt;deg(L i (x)). 
         [0014]      FIGS. 2A and 2B  respectively illustrate a basic cell PE1 200 of a modified Euclidean algorithm for solving Equations 2 through Equation 4 and a conventional operation circuit in which basic cells are connected in a systolic-array fashion. 
         [0015]    Initial values set as shown in Equation 5 are input to the basic cell PE1 200. If a degree deg(R i−1 (x)) is equal to or greater than a degree deg(Q i−1 (x)), an arithmetic operation is performed and a switching signal becomes 0. If the degree deg(R i−1 (x)) is less than the degree deg(Q i−1 (x)), however, the switching signal becomes 1. When the switching signal is 1, polynomials R i−1 (x) and Q i−1 (x) are swapped, polynomials L i−1 (x) and U i−1 (x) are swapped, and the degrees deg(R i−1 (x)) and deg(Q i−1 (x)) are swapped by a multiplexer. After arithmetic operations are performed, polynomials R i (x), Q i (x), L i (x), and U i (x) are output from the multiplexer. If t errors are generated, polynomials R 2t (x) and L 2t (x) which are obtained by performing arithmetic operations on 2t cells become an error value polynomial and an error locator polynomial, respectively. If errors less than t errors are generated, that is, if a first coefficient of the polynomial Q i (x) output from the multiplexer is 0, the polynomials Q i (x) and U i (x) become an error value polynomial and an error locator polynomial, respectively, and operations are performed on 2t basic cells by comparing a degree deg(Q i (x)), which is obtained using deg(Q i (x))=deg(Q i−1 (x))-1, with t and then a shift operation is performed so that degrees of polynomials Q 2t (x) and U 2t (x) become t-1 and t, respectively. 
         [0016]      FIG. 3  is a circuit diagram of a conventional operation circuit in which one basic cell is iteratively used by sending an output of the basic cell as an input in a systolic-array fashion. 
         [0017]    When a clock latency, which is a time delay between an input of a basic cell to an output of the basic cell, is m, 2t-m registers are needed. Accordingly, the number of shift registers increases as the clock latency m decreases. When compared with the conventional operation circuit of  FIG. 2B  using 16 basic cells, the conventional operation circuit of  FIG. 3  using one basic cell can considerably reduce a hardware area, but suffers from a high clock latency because the shift registers should be passed each time. 
         [0018]    Since the conventional operation circuits of  FIGS. 2 and 3  for the modified Euclidean algorithm comprise basic cells for implementing Equations 1 through 4, and each of the basic cells comprises a degree computation unit for calculating and comparing degrees of polynomials, the conventional operation circuits of  FIGS. 2 and 3  are large. 
         [0019]      FIG. 4  illustrates a conventional operation circuit for a degree computationless modified Euclidean algorithm.  FIG. 5  illustrates operations performed on polynomials to generate control signals in the degree computationless modified Euclidean algorithm of  FIG. 4 . 
         [0020]    The conventional operation circuit for the degree computationless modified Euclidean algorithm of  FIG. 4  has an area-efficient architecture that requires a clock latency of 2t to obtain a final output, uses 3t+2 cells, and does not include a degree computation unit for calculating and comparing degrees. However, the conventional operation circuit of  FIG. 4  has a low clock speed because it is difficult to pipeline blocks. In addition, the conventional operation circuit of  FIG. 4  cannot process a new input until an error value polynomial and an error locator polynomial are obtained using outputs of the blocks after a clock latency of 2t. Accordingly, when the conventional operation circuit of  FIG. 4  is applied to a 4-channel parallel structure sharing one KES block, a clock latency per syndrome calculation block is linearly increased. 
       SUMMARY OF THE INVENTION 
       [0021]    The present invention provides a high-speed area-efficient operation circuit for a modified Euclidean algorithm, which can efficiently process data streams and can easily pipeline blocks without using a degree computation unit which is included in a basic cell of a conventional operation circuit for a modified Euclidean algorithm, and a method of implementing the modified Euclidean algorithm. 
         [0022]    According to an aspect of the present invention, there is provided an operation circuit for a modified Euclidean algorithm of a systolic-array structure comprising a plurality of basic cells in order to obtain an error value polynomial and an error locator polynomial on the basis of a syndrome polynomial, each of the basic cells comprising: a control signal generating unit generating a control signal for a swap operation and/or a shift operation, on the basis of a finite state machine (FSM) consisting of a function that determines whether a swap operation and/or a shift operation is performed on polynomials C i−1  and D i−1  on the basis of a value of the polynomial C i−1  and degrees of the polynomials C i−1  and D i−1 ; and an operation unit performing a swap operation or/and a shift operation and then a polynomial operation on polynomials C i−1 , D i−1 , E i−1 , and F i−1  according to the control signal, wherein a polynomial C 0  input to a first basic cell among the basic cells is a value obtained by multiplying the syndrome polynomial by x, a polynomial D 0  input to the first basic cell is a value having a degree twice higher than the number of symbols whose errors can be corrected, a polynomial E 0  input to the first basic cell is x, a polynomial F 0  input to the first basic cell is 0, and even-numbered basic cells among the basic cells decrease degrees of output polynomials C i  and D i  by 1. 
         [0023]    According to another aspect of the present invention, there is provided a method of implementing a modified Euclidean algorithm of a systolic-array structure comprising a plurality of basic cells in order to obtain an error value polynomial and an error locator polynomial on the basis of a syndrome polynomial, the method comprising: generating a control signal for a swap operation and/or a shift operation, on the basis of an FSM consisting of a function that determines whether a swap operation and/or a shift operation is performed on polynomials C i−1  and D i−1  on the basis of a value of the polynomial C i−1  and degrees of the polynomials C i−1  and D i−1 ; performing a swap operation or/and a shift operation and then a polynomial operation on polynomials C i−1 , D i−1 , E i−1 , and F i−1  according to the control signal; and recursively performing the generating of the control signal and the performing of the operations, and decreasing by 1 degrees of polynomials C i  and D i  output as the operation results when performing operations on even-numbered basic cells, wherein a polynomial C 0  input to a first basic cell among the basic cells is a value obtained by multiplying the syndrome polynomial by x, a polynomial D 0  input to the first basic cell is a value having a degree twice higher than the number of symbols whose errors can be corrected, a polynomial E 0  input to the first basic cell is x, and a polynomial F 0  input to the first basic cell is 0. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0024]    The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
           [0025]      FIG. 1  is a block diagram of a conventional Reed-Solomon (RS) decoder; 
           [0026]      FIG. 2A  is a circuit diagram of a basic cell of a conventional modified Euclidean algorithm; 
           [0027]      FIG. 2B  illustrates a conventional operation circuit in which basic cells of  FIG. 2A  are connected in a systolic-array fashion; 
           [0028]      FIG. 3  is a block diagram of a conventional operation circuit in which one basic cell is iteratively used by sending an output of a basic cell as an input in a systolic-array fashion; 
           [0029]      FIG. 4  illustrates a conventional operation circuit for a degree computationless modified Euclidean algorithm; 
           [0030]      FIG. 5  illustrates operations performed on polynomials to generate control signals in the degree computationless modified Euclidean algorithm of  FIG. 4 ; 
           [0031]      FIG. 6  is a circuit diagram of an operation circuit for a modified Euclidean algorithm according to an embodiment of the present invention; 
           [0032]      FIG. 7  illustrates a finite state machine (FSM) for generating an operation control signal according to an embodiment of the present invention; and 
           [0033]      FIG. 8  illustrates an FSM for generating a stop signal according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0034]    The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. 
         [0035]      FIG. 6  is a circuit diagram of an operation circuit for a modified Euclidean algorithm according to an embodiment of the present invention. 
         [0036]    In the present invention, Equations 2 through 4 are transformed into Equations 6 through 8 in order to remove a conventional degree computation unit for calculating and comparing degrees. 
         [0000]        R   i ( x )= b   i−1   R   i−1 ( x )− x   |l   i−1   |   a   i−1   Q   i−1 ( x ) 
         [0000]        Q   i ( x )= Q   i−1 ( x )  (6) 
         [0000]        R   i ( x )= a   i−1   Q   i−1 ( x )− x   |l   i−1   |   b   i−1   R   i−1 ( x ) 
         [0000]        Q   i ( x )= R   i−1 ( x )  (7) 
         [0000]      if(l x−1 &lt;0)SWAP(R i−1 (x),Q i−1 (x)) 
         [0000]        R   i ( x )= b   i−1   R   i−1 ( x )− x   |l   i−1   |   a   i−1   Q   i−1 ( x ) 
         [0000]        Q   i ( x )= Q   i−1 ( x )  (8) 
         [0000]      if(l i−1 &lt;0)SWAP(R i−1 (x),Q i−1 (x)) 
         [0000]        L   i ( x )= b   i−1   L   i−1 ( x )− x   |l   i−1   |   a   i−1   U   i−1 ( x ) 
         [0000]        U   i ( x )= U   i−1 ( x )  (9) 
         [0037]    When σ  i−1  is 1, Equation 2 becomes Equation 6, and when σ i−1  is 0, Equation 2 becomes Equation 7. When I i−1  is a negative number and polynomials R i−1 (x) and Q i−1 (x) are swapped in Equation 6, since a polynomial R i−1 (x)new is the polynomial Q i−1 (x), a polynomial Q i−1 (x)new is the polynomial R i−1 (x), a coefficient a i−1— new is a coefficient b i−1  of a highest degree term of the polynomial Q i−1 (x), and a coefficient b i−1— new is a coefficient a i−1  of a highest degree term of the polynomial R i−1 (x), the same result is obtained as when the polynomials R i−1 (x) and Q i−1 (x) are applied to Equation 7. That is, each of Equations 6 and 7 can be transformed into Equation 8 and Equation 9 can be transformed in the same manner. 
         [0038]    In  FIG. 6 , operations of Equation 8 performed on basic cells may include a shift operation, a polynomial operation, and a swap operation. That is, there are three control signals of the basic cells. The operation circuit of  FIG. 6  is similar to a polynomial arithmetic block of  FIG. 2A . In  FIG. 6 , a shift operation, which multiples data by x, and an arithmetic operation, which multiplies a coefficient of a highest degree term of a first input polynomial by a second input polynomial and a coefficient of a highest degree term of the second input polynomial by the first input polynomial and then adds the multiplication results, cannot be simultaneously performed on the basic cells, and a shift operation cannot be repeatedly performed on one basic cell two or more times. 
         [0039]    A polynomial on which a shift operation is to be performed should be located at an output end of a multiplexer. Input patterns should be used in order to generate three control signals without using the number I i−1 . Three input patterns are given by Equations 11 through 13. 
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                           x 
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                       = 
                       
                         x 
                         
                           2 
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                         Q 
                         0 
                       
                        
                       
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                         x 
                         ) 
                       
                     
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                             - 
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                               t 
                             
                             - 
                             1 
                           
                         
                       
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                          
                         
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                             2 
                           
                         
                       
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                           1 
                         
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                           x 
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                         S 
                         0 
                       
                     
                   
                    
                   
                     
 
                   
                    
                   
                     { 
                     
                       
                         
                           
                             
                               
                                 S 
                                 i 
                               
                               = 
                               0 
                             
                             , 
                           
                         
                         
                           
                             
                               
                                 
                                   2 
                                    
                                   t 
                                 
                                 - 
                                 
                                   1 
                                   · 
                                   k 
                                 
                               
                               ≤ 
                               i 
                               ≤ 
                               
                                 
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                                   t 
                                 
                                 - 
                                 
                                   1 
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                             , 
                           
                         
                       
                       
                         
                           
                             
                               
                                 S 
                                 i 
                               
                               ≠ 
                               0 
                             
                             , 
                           
                         
                         
                           otherwise 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where k is an integer. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         R 
                         0 
                       
                        
                       
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                         ) 
                       
                     
                     = 
                     
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                         0 
                       
                        
                       
                         ( 
                         x 
                         ) 
                       
                     
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                               t 
                             
                             - 
                             1 
                           
                         
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                             - 
                             1 
                           
                         
                       
                       + 
                       
                         
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                           1 
                         
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                           x 
                           1 
                         
                       
                       + 
                       
                         S 
                         0 
                       
                     
                   
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                     { 
                     
                       
                         
                           
                             
                               
                                 S 
                                 i 
                               
                               = 
                               0 
                             
                             , 
                           
                         
                         
                           
                             
                               
                                 
                                   2 
                                    
                                   t 
                                 
                                 - 
                                 1 
                                 - 
                                 m 
                               
                               ≤ 
                               i 
                               &lt; 
                               
                                 
                                   2 
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                                   t 
                                 
                                 - 
                                 1 
                               
                             
                             , 
                             
                                 
                             
                              
                             
                               m 
                               &gt; 
                               0 
                             
                             , 
                           
                         
                       
                       
                         
                           
                             
                               
                                 S 
                                 i 
                               
                               ≠ 
                               0 
                             
                             , 
                           
                         
                         
                           otherwise 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where m is an integer. 
         [0040]    Since a degree of Q 0 (x) is always less than a degree of R 0 (x), a basic cell 1 of  FIG. 6  has the input pattern given by Equation 10. Equation 11 shows the input pattern when a value of S i  is not 0. This means that only a highest degree term of R 0 (x) is removed from operations of Equation 8. That is, a degree of R 1 (x) is equal to a degree of Q 1 (x)(=Q 0 (x))). R 2 (x) and Q 2 (x) can be obtained by using Equation 8. If R 2 (x) is obtained by removing only the highest degree term of R 1 (x), R 2 (x) and Q 2 (x) are swapped and the input pattern given by Equation 11 is obtained. If R 2 (x) is obtained by removing not only the highest degree term but also the second highest degree term of R 1 (x), R 2 (x) and Q 2 (x) are swapped and then the input pattern given by Equation 12 is obtained. A process in which a degree of Q i (x) is greater than a degree of R i (x) while the highest degree term of R i (x) is removed and thus the two polynomials are swapped is referred to as a start of a new operation. 
         [0041]    In  FIG. 6 , C 1 (x) and D 1 (x) respectively become R 1 (x) and Q 1 (x), C 2 (x) and D 2 (x) respectively become R 2 (x) and Q 2 (x). When a polynomial operation or a shift operation is performed, an output of D i (x) one clock later than an output of C i (x), such that x, which is multiplied to Q i−1 (x) for an addition in Equation 8, can be removed and a polynomial operation can be directly performed without a shift operation by multiplying R i−1 (x) by x before R i−1 (x) and Q i−1 (x) are swapped. 
         [0042]      FIG. 7  illustrates a finite state machine (FSM) for generating an operation control signal. In  FIG. 7 , a state S 0  denotes a state when an operation is initially performed or a new operation starts, and a control signal Sw and a control signal Sht for basic cells are output. When the control signal Sw is 1, a swap operation is performed, when the signal Sht is 1, a shift operation is performed, and when the signal Sht is 0, a polynomial operation s performed. The state S 0  transits to a state S1 or a state S2 according to whether degrees of two input polynomials are equal to each other. An input signal Sl indicates whether the degrees of the two input signals are equal to each other. In the case of Equation 11, since degrees of two input polynomials are equal to each other, the input signal Sl becomes 1 and the state S 0  transits to the state S 1 . In this case, since a polynomial operation is performed, the control signal Sht becomes 0, and since C 0 (x) is xQ 0 (x), the control signal Sw becomes 1 for the polynomial operation. If R 1 (x) is obtained by removing only the highest degree term of R 0 (x), a polynomial operation is performed, and the control signal when the input signal Sl is 1 in the state S 1  of  FIG. 7  is applied to a basic cell 2. If R i (x) is obtained by removing only the highest degree term of R i−1 (x), the state in  FIG. 7  repeatedly transits between the states S 0  and S 1 . 
         [0043]    In the case of the input pattern of Equation 12, since a degree of xQ 0 (x) input to the basic cell 1 is less than a degree of R 0 (x), an operation of multiplying xQ 0 (x) by x is performed. Hence, when the input signal Sl is 0, the initial state S 0  of  FIG. 7  transits to a state S 2 , and a control signal for a shift operation is generated. If degrees of two input polynomials x2Q 0 (x) and R 0 (x) of the basic cell 2 are equal to each other, a polynomial operation is performed. If a degree of a polynomial, which is obtained by multiplying Q 1 (x)(=Q 0 (x)) by x, is equal to a degree of R 1 (x), a polynomial operation is performed. If the degree of the polynomial, which is obtained by multiplying Q 1 (x)(=Q 0 (x)) by x, is not equal to the degree of R 1 (x), however, it is determined whether degrees of R 1 (x) and Q 1 (x) are equal to each other. If it is determined that the degrees of R 1 (x) and Q 1 (x) are equal to each other, a polynomial operation is performed. If it is determined that the degrees of R 1 (x) and Q 1 (x) are not equal to each other, since the degree of R 1 (x) is less than the degree of Q 1 (x), a swap operation is performed. When k is 1, the state S 0  transits to states S 2 , S 3 , S 1 , and S 1 . 
         [0044]    In the case of the input pattern of Equation 13, the basic cell 1 becomes the same as in Equation 11. However, since a degree of R 1 (x) is less than a degree of Q 1 (x) in this case, a swap operation, instead of a polynomial operation, is performed on R 1 (x) and Q 1 (x). Since a swap operation and a polynomial operation can be simultaneously performed but a polynomial operation and a shift operation cannot be simultaneously performed, a shift operation is performed so that a polynomial operation is performed right before a swap operation is performed. Hence, when the input signal Sl is 0 in the state S 1  of  FIG. 7 , a control signal for a shift operation is generated. After the operation for the basic cell 2 terminates, the state S 0  is maintained. 
         [0045]    The FSM of  FIG. 7  is completed using the aforementioned rules and it is assumed that k&lt;8. Accordingly, no error is generated in a state S 16  during transmission through channels and when a syndrome value is 0. If t errors are generated, an error locator polynomial and an error value polynomial can be obtained after performing operations on 2t basic cells. However, if v(&lt;t) errors are generated, an error locator polynomial and an error value polynomial can be obtained by performing operations on basic cells less than 2t basic cells. Considering that a degree of an error value polynomial is less than a degree of an error locator polynomial, a stop signal for stopping a polynomial operation is generated in an FSM. 
         [0046]      FIG. 8  illustrates an FSM for generating a stop signal, according to an embodiment of the present invention. In  FIG. 8 , it is determined what polynomial among C i−1 (x) and E i−1 (x) is first input with a value other than 0 to basic cells. If E i−1 y(x) is first input to the basic cell, an initial state S 0  transits to a state S 2 , and the state S 2  is maintained until a stop reset signal is input. On the other hand, if C i−1 (x) is first input to the basic cell or E i−1 y(x) and C i−1 (x) are simultaneously input to the basic cells, the initial state S 0  transits to a state S 1  and the state S 1  is maintained until a stop reset signal is input. 
         [0047]    A value of each of C i−1 (x) and E i−1 (x) is 0 or 1, and ‘−’ means that a corresponding input/output does not affect a state transition. If a stop signal becomes 1, only a shift operation is performed on the basic cells. However, there are things to additionally consider in order to guarantee that C 2t (x) and E 2t (x) have right values after operations are performed on 2t basic cells. For example, although outputs of a 6 th  basic cell are an error value polynomial and an error locator polynomial, since one degree per two basic cells should be reduced in order that a degree of C 6 (x) of the 6 th  basic cell becomes 12 and a degree of C 2t (x) becomes 7, registers 2 in even-numbered cells are removed. 
         [0048]    Referring to  FIG. 6 , each basic cell  600  of the operation circuit for the modified Euclidean algorithm includes a swap operation unit  610 , a shift operation unit  620 , a polynomial operation unit  630 , a control signal generating unit  640 , and a stop signal generating unit  650 . 
         [0049]    The control signal generating unit  640  generates a control signal on the basis of the FSM of  FIG. 7 . In detail, the control signal generating unit  640  transits to a state on the basis of a state Sin received from a previous basic cell and a polynomial C i−1  output from the previous basic cell, and generates an operation control signal upon the state transition. 
         [0050]    The stop signal generating unit  650  generates a stop signal on the basis of the FSM of  FIG. 8 . In detail, the stop signal generating unit  650  transits to a state on the basis of polynomials C i−1  and D i−1  output from a previous basic cell, and generates a stop signal. Once the stop signal is generated, outputs of the basic cell become an error locator polynomial and an error value polynomial. 
         [0051]    The operation units  610 ,  620 , and  630  perform operations according to the control signals of the control signal generating unit  640  and the stop signal generating unit  650 , and particularly, even-numbered basic cells reduce degrees by removing registers  602 ,  632 , and  634  marked by dotted lines in  FIG. 6 . 
         [0052]    As described above, since a degree computation unit for comparing and calculating degrees, which is included in a basic cell of a conventional operation circuit for a modified Euclidean algorithm, is removed, in the present invention, data streams can be efficiently processed, blocks can be easily pipelined, and hardware complexity can be reduced. 
         [0053]    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.