Abstract:
A receiving circuit includes: a detector configured to detect a position at which logics of first data and second data acquired by sampling received data using two clocks having mutually-different phases do not match each other as an edge; and an adjustment circuit configured to perform an adjustment causing an internal clock frequency to be close to a data frequency in the received data based on a first probability that logics of third data in a next cycle of the first data and the second data match each other and a second probability that logics of fourth data in a next cycle of the second data and the third data match each other.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2015-206654, filed on Oct. 20, 2015, the entire contents of which are incorporated herein by references. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a receiving circuit and a method for controlling a frequency. 
       BACKGROUND 
       [0003]    A clock and data recovery (CDR) circuit extracting a clock from received data and restoring the received data has been used in a receiving circuit. The CDR circuit is largely divided into two types, i.e., a type using a reference clock and a type that does not use a reference clock (reference clockless CDR circuit). The type using a reference clock generates a frequency according to a data rate by using a phase locked loop (PLL) circuit. For this reason, the CDR circuit of the type that uses a reference clock does not have a frequency adjusting function. The reference clockless (the type that does not use a reference clock) CDR circuit generates a clock signal of a frequency according to a data rate by using the CDR circuit. For this reason, the CDR circuit of the type that does not use a reference clock has a frequency adjusting function. 
         [0004]    Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2013-135423 and Japanese Laid-Open Patent Publication No. 11-331135. 
       SUMMARY 
       [0005]    According one aspect of the embodiments, a receiving circuit includes: a detector configured to detect a position at which logics of first data and second data acquired by sampling received data using two clocks having mutually-different phases do not match each other as an edge; and an adjustment circuit configured to perform an adjustment causing an internal clock frequency to be close to a data frequency in the received data based on a first probability that logics of third data in a next cycle of the first data and the second data match each other and a second probability that logics of fourth data in a next cycle of the second data and the third data match each other. 
         [0006]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0007]      FIG. 1  is a diagram illustrating an exemplary frequency detector (FD) control according to this embodiment; 
           [0008]      FIG. 2  is a diagram illustrating an example of a truth value table used in the FD control; 
           [0009]      FIG. 3  is a diagram illustrating an example of a 2×oversampling CDR circuit according to this embodiment; 
           [0010]      FIG. 4  is a diagram illustrating an exemplary circuit configuration of an edge detector; 
           [0011]      FIG. 5  is a diagram illustrating an exemplary circuit configuration of a data match determining unit; 
           [0012]      FIG. 6  is a diagram illustrating an example of a truth value table used by a probability calculating circuit; 
           [0013]      FIG. 7  is a flowchart illustrating an example of the process of the FD according to this embodiment; and 
           [0014]      FIG. 8  is a diagram illustrating an example of another 2×oversampling CDR circuit. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0015]    When there is a difference between the frequency of an internal clock and the frequency of data, a data edge (transition point) is shifted. In order to determine the direction of this shift, sampling information of three or more points per unit interval (UI) is necessary. 
         [0016]    A receiving circuit corrects data with high precision using two pieces of input data. Such a receiving circuit selects and then corrects two pieces of input data having a center phase of input data of a binary level for one UI interposed therebetween and detects a phase in which the level of the input data transits as a boundary phase of one UI based on the corrected input data. The level of any data out of two pieces of the corrected input data is determined based on the detected boundary phase and corrected based on a correction value according to the level of the data in the past. 
         [0017]    A received signal is sampled using a high-speed clock signal having a cycle faster than the bit rate, and a code change point is detected from the sampling signal. The bit rate of the received signal is recognized based on this code change point and the received signal is extracted based on the bit rat. 
         [0018]    In a 4×oversampling technology, sampling data is performed using a clock of four phases for one UI. When an oversampling is performed, the number of comparators is increased according to the number of phases to be acquired, and the circuit scales of a clock buffer, a demultiplexer, and the like are also increased. When the circuit scales are increased, the power consumption also increases. 
         [0019]    An aspect of the present disclosure is to decrease the circuit scale and reduce the power consumption. 
         [0020]    An embodiment of the present disclosure implements a 2×oversampling CDR capable of determining a shift direction. In the 2×oversampling CDR, compared to the 4×oversampling, the number of comparators may be decreased, and the circuit scales of a clock buffer, a demultiplexer, and the like may be decreased. Accordingly, the power consumption may also be decreased. 
         [0021]    According to the 2×oversampling CDR of an embodiment of the present disclosure, received data is sampled with a slightly shifted phase (e.g., shifted by minimum resolution of a phase rotator), and a logical relationship between the data of two points is checked, whereby a frequency comparison may be realized. In the 2×oversampling CDR, by acquiring a magnitude relationship between a data frequency and an internal clock frequency, a shift direction is determined, and a frequency detector (FD) control for adjusting the internal clock frequency is performed. 
         [0022]      FIG. 1  is a diagram illustrating an exemplary FD control according to this embodiment. A frequency detector (FD) included in a 2×oversampling CDR circuit adjusts an error between the frequency of received data and the internal clock frequency up to about 1% by performing the FD control. Cases  101  to  103  illustrate examples where a receiving circuit receives data in an order of “1,” “0,” and “1.” 
         [0023]    When a data frequency F data  is higher than the internal clock frequency F clk  (in the case of Case  101 ), the frequency detector (FD) performs an adjustment to increase the internal clock frequency F clk . For example, the FD transmits an instruction for increasing the internal clock frequency to a voltage controlled oscillator (VCO). The VCO increases the internal clock frequency in accordance with the instruction. 
         [0024]    When an error between the data frequency F data  and the internal clock frequency F clk  is small (in the case of Case  102 ), the frequency detector (FD) ends the frequency adjustment (FD control) by the FD. The FD determines that the error between the data frequency F data  and the internal clock frequency F clk  converges within a specific range (e.g., within 1%). 
         [0025]    When a data frequency F data  is lower than the internal clock frequency F clk  (in the case of Case  103 ), the frequency detector (FD) performs an adjustment to decrease the internal clock frequency F clk . For example, the FD transmits an instruction for decreasing the internal clock frequency to the VCO. The VCO decreases the internal clock frequency in accordance with the instruction. 
         [0026]    In this way, the internal clock frequency F clk  is adjusted to be close to the data frequency F data . For the adjustment, a magnitude relationship between the data frequency F data  and the internal clock frequency F clk  may be required to be determined. Determination methods of Case  101  to Case  103  will be described below. 
         [0027]    (1) A phase rotator fixedly sets a phase difference between a lead phase A and a lag phase B. 
         [0028]    (2) The FD detects a position at which the phases A and B do not match each other, as a data edge (transition point). In Case  101  to Case  103 , an interval between data D A0  and data D B0  at which data transits from 1 to 0 is detected as an edge. 
         [0029]    (3) The FD determines a logical match between data D B0  and data D A1  that is data of a next cycle from a cycle in which an edge is detected. In addition, the FD determines a logical match between data D A1  and data D B1  that are data of a next cycle form a cycle in which an edge is detected. 
         [0030]    (4) The FD adjusts the internal clock frequency based on results of the logical match between the data D B0  and the data D A1  and the logical match between the data D A1  and the data D B1 . 
         [0031]    When data is received in an order of “1,” “0,” and “1” in a state in which the data frequency F data  is higher than the internal clock frequency F clk  (Case  101 ), the data D B0  is 0, and the data D A1  is 1, and accordingly, the logics do not match each other. Meanwhile, when data is received in an order of “1,” “0,” and “0,” in the state in which the data frequency F data  is higher than the internal clock frequency F clk , the data D B0  is 0, and the data D A1  is 0, and accordingly, the logics match each other. Since received data is assumed to be random, when the data frequency F data  is higher than the internal clock frequency F clk , a probability that the logics of the data D B0  and the data D A1  match each other is 50%. 
         [0032]    When data is received in an order of “1,” “0,” and “1” in a state in which the data frequency F data  is higher than the internal clock frequency F clk  (Case  101 ), the data D A1  is 1, and the data D B1  is 1, and accordingly, the logics match each other. In addition, when data is received in an order of “1,” “0,” and “0” in the state in which the data frequency F data  is higher than the internal clock frequency F clk , the data D A1  is 0, and the data D B1  is 0, and accordingly, the logics match each other. Accordingly, when the data frequency F data  is higher than the internal clock frequency F clk , a probability that the logics of the data D A1  and the data D B1  match each other is 100%, regardless of received data. 
         [0033]    When data is received in an order of “1,” “0,” and “1” in a state in which an error between the data frequency F data  and the internal clock frequency F clk  is small (Case  102 ), the data D B0  is 0, and the data D A1  is 0, and accordingly, the logics match each other. In addition, when data is received in an order of “1,” “0,” and “0” in a state in which an error between the data frequency F data  and the internal clock frequency F clk  is small, the data D B0  is 0, and the data D A1  is 0, and accordingly, the logics match each other. Accordingly, when the error between the data frequency F data  and the internal clock frequency F clk  is small, a probability that the logics of the data D B0  and the data D A1  match each other is 100%. 
         [0034]    When data is received in an order of “1,” “0,” and “1” in a state in which an error between the data frequency F data  and the internal clock frequency F clk  is small (Case  102 ), the data D A1  is 0, and the data D B1  is 1, and accordingly, the logics do not match each other. Meanwhile, when data is received in an order of “1,” “0,” and “0” in a state in which an error between the data frequency F data  and the internal clock frequency F clk  is small, the data D A1  is 0, and the data D B1  is 0, and accordingly, the logics match each other. When the error between the data frequency F data  and the internal clock frequency F clk  is small, received data is assumed to be random, and accordingly, a probability that the logics of the data D A1  and the data D B1  match each other is 50%. 
         [0035]    When data is received in an order of “1,” “0,” and “1” in a state in which the data frequency F data  is lower than the internal clock frequency F clk  (Case  103 ), the data D B0  is 0, and the data D A1  is 0, and accordingly, the logics match each other. In addition, when data is received in an order of “1,” “0,” and “0” in a state in which the data frequency F data  is lower than the internal clock frequency F clk , the data D B0  is 0, and the data D A1  is 0, and accordingly, the logics match each other. Accordingly, when the data frequency F data  is lower than the internal clock frequency F clk , a probability that the logics of the data D B0  and the data D A1  match each other is 100%. 
         [0036]    When data is received in an order of “1,” “0,” and “1” in a state in which the data frequency F data  is lower than the internal clock frequency F clk  (Case  103 ), the data D A1  is 0, and the data D B1  is 0, and accordingly, the logics match each other. In addition, when data is received in an order of “1,” “0,” and “0” in a state in which the data frequency F data  is lower than the internal clock frequency F clk , the data D A1  is 0, and the data D B1  is 0, and accordingly, the logics match each other. Accordingly, when the data frequency F data  is lower than the internal clock frequency F clk , a probability that the logics of the data D A1  and the data D B1  match each other is 100%. 
         [0037]    For example, by performing the processes of (1) to (3) plural times, the FD may calculate probabilities of the logical match between the data D B0  and the data D A1  and the logical match between the data D A1  and the data D B1 , and the FD may determine one of the states of Case  101  to Case  103  as the state of the received data. In the case of Case  101  and Case  103 , by transmitting an instruction for adjusting the internal clock frequency to be close to the data frequency to the VCO, the FD may decrease the error between the data frequency F data  and the internal clock frequency F clk . 
         [0038]    When the control process using the FD ends, the process proceeds to a phase detector, and a fine adjustment of the frequency and the phase is performed. 
         [0039]    In this way, by measuring two points of the phases A and B, the adjustment of the internal clock frequency through the 2×oversampling CDR may be performed. By implementing the 2×oversampling CDR, compared to 4×oversampling, the number of comparators may be decreased, and the circuit scales of a clock buffer, a demultiplexer, and the like may be decreased. As a result, the amount of power consumption may also be reduced. 
         [0040]      FIG. 2  is a diagram illustrating an example of a truth value table used in the FD control. The truth value table  200  is a table in which a relationship between the data frequency F data  and the internal clock frequency F clk  and the probability of a logical match between the data D B0  and the data D A1  and the probability of a logical match between the data D A1  and the data D B1  are associated with each other. 
         [0041]    The FD, for example, for 100 pieces of data, performs the processes of (1) to (3) and calculates the probability of the logical match between the data D B0  and the data D A1  and the probability of the logical match between the data D A1  and the data D B1 . The FD sets the the probability of the match to 50% when the probability of the logical match is within 50 times ±10% and sets the probability of the match to 100% when the probability of the logical match is 90 times or more. 
         [0042]    Here, when the data frequency F data  included in the truth value table  200  is remarkably higher than the internal clock frequency F clk  and when the data D A1  and the data D B1  are applied in a cycle after two cycles from a cycle in which an edge is detected, the probability of the logical match between the data D A1  and the data D B1  may be 50%. For this reason, in the truth value table  200 , the probability of a logical match between the data D A1  and the data D B1  when the data frequency F data  is higher than the internal clock frequency F clk  is a match probability of being “equal to or less than 100%.” 
         [0043]    When the probability of the logical match between the data D B0  and the data D A1  is 50%, and the probability of the logical match between the data D A1  and D B1  is 100%, the FD determines that the data frequency F data  is higher than the internal clock frequency F clk . 
         [0044]    When the probability of the logical match between the data D B0  and the data D A1  is 100%, and the probability of the logical match between the data D A1  and D B1  is 50%, the FD determines that an error between the data frequency F data  and the internal clock frequency F clk  is small. 
         [0045]    When the probability of the logical match between the data D B0  and the data D A1  is 100%, and the probability of the logical match between the data D A1  and the data D B1  is 100%, the FD determines that the data frequency F data  is lower than the internal clock frequency F clk . 
         [0046]    The FD, according to the determination, transmits an instruction to increase/decrease the internal clock frequency to the VCO. 
         [0047]      FIG. 3  is a diagram illustrating an example of the 2×oversampling CDR circuit according to this embodiment. A receiving circuit  300  is an example of the 2×oversampling CDR circuit. The receiving circuit  300  includes a linear equalizer (LE)  301 , a sampler  302 , an FD  303 , a filter  306 , a VCO  307 , a PD  308 , a digital filter  309 , and a phase rotator  310 . 
         [0048]    The LE  301  is a circuit that restores a high-frequency component of an input data signal that has been lost in a transmission line by decreasing a gain for a low-frequency component and equivalently intensifying the high-frequency component. The sampler  302  determines the logics of the input data signal of which the high-frequency component has been restored by the LE at timings of clocks CKA and CKB and converts the restored input data signals into digital values (0/1). 
         [0049]    The FD  303  performs an edge detection from data D A0  and data D B0 , determines a shift direction by acquiring a magnitude relationship between the data frequency and the internal clock frequency by using data D A1  and D B1  of a next cycle from a cycle in which the edge detection is performed, and performs an adjustment of the internal clock frequency. For example, the FD  303  causes an error between the data frequency and the internal clock frequency to be close up to about 1%. The PD  308  performs an adjustment of eliminating the error between the data frequency and the internal clock frequency and causing the phases to match each other. 
         [0050]    As for the filter  306 , a low pass filter is used as a feedback loop filter. In a circuit including feedback, unnecessary oscillation may occur in accordance with amplification of signal variations of short periods, and the filter  306  excludes the variations of short periods. The VCO  307  is a circuit that controls an output frequency using an input voltage. The VCO  307  operates as an adjustment unit adjusting the internal clock frequency in accordance with an instruction received from the FD  303 . The digital filter  309  may be a low pass filter as well. 
         [0051]    The FD  303  according to this embodiment includes an edge detector  304  and a data match determining unit  305 . The edge detector  304  detects a position (between the data D A0  and the data D B0 ) at which logics of data do not match each other at the phases A and B transmitted from the sampler  302  as an edge. When an edge is detected, the edge detector  304  notifies the data match determining unit  305  of the detection of the edge. 
         [0052]    When the detection of the edge is notified from the edge detector  304 , the data match determining unit  305  determines a logic match between the data D B0  and the data D A1  that is the data of a next cycle form a cycle in which an edge is detected. In addition, the data match determining unit  305  determines a logic match between the data D A1  and the data D B1  that are data of a next cycle form a cycle in which an edge is detected. The data match determining unit  305  transmits an instruction to adjust the internal clock frequency based on the results of the logic match between the data D B0  and the data D A1  and the logic match between the data D A1  and D B1 . The VCO  307  controls the internal clock frequency in accordance with an instruction transmitted from the data match determining unit  305 . 
         [0053]    In this way, by measuring two points of the phases A and B, the internal clock frequency may be adjusted using the 2×oversampling CDR. By implementing the 2×oversampling CDR, compared to 4×oversampling, the number of comparators may be decreased, and the circuit scales of the clock buffer and the like may be decreased. Accordingly, the amount of power consumption may also be reduced. 
         [0054]      FIG. 4  is a diagram illustrating an example of the circuit configuration of the edge detector. The edge detector  304  includes an XOR  323  that takes exclusive logical OR between data D A  of a phase A acquired by a sampler  302   a  and data D B  of a phase B acquired by a sampler  302   b.  By taking the exclusive logical OR using the XOR  323 , a match between the data D A  of the phase A and the data D B  of the phase B may be determined. 
         [0055]    For example, the XOR  323  compares the input data D A  and D B  of 16 bits with each other in the units of bits. The XOR  323  determines the bits of D A [N] and D B [N] (here, N=0 to 15) of which logics do not match each other. The XOR  323  outputs EDGE=1 that is a signal representing that a corresponding bit is an edge when no match is determined, and outputs EDGE=0 when no edge is found. 
         [0056]      FIG. 5  is a diagram illustrating an exemplary circuit configuration of the data match determining unit. The data match determining unit  305  includes an XNOR  331 , an XNOR  332 , a combinational circuit  333 , and a probability calculating circuit  334 . 
         [0057]    The XNOR  331  determines a match between data D B0  and data D A1 . For example, the XNOR  331  takes logical exclusive NOR of data D B(0+N)  and data D A(1+N) . When the values of the data D B(0+N)  and the data D A(1+N)  match each other, the XNOR  331  outputs “1” representing that the logics match each other. The XNOR  332  determines a match between data D A1  and data D B1 . For example, the XNOR  332  takes logical exclusive NOR of data D A(1+N)  and data D B(1+N) . When the values of the data D A(1+N)  and the data D B(1+N)  match each other, the XNOR  332  outputs “1” representing that the logics match each other. 
         [0058]    The combinational circuit  333  receives a processing result of the XNOR  331 , a processing result of eth XNOR  332 , and the value of an edge transmitted from the edge detector  304 . When EDGE=1 is received (when an edge is detected by the edge detector), the combinational circuit  333  handles the processing results received from the XOR  331  and the XOR  332  to be valid. The combinational circuit  333  may acquire a result of the logical match between the data D B0  and the data D A1  and a result of the logical match between the data D A1  and the data D B1  for a bit at which an edge has been detected by the edge detector. 
         [0059]    The probability calculating circuit  334  receives the result of the logical match between the data D B0  and the data D A1  and the result of the logical match between the data D A1  and the data D B1  for the bit at which an edge has been detected by the edge detector from the combinational circuit  304 . The probability calculating circuit  334  includes a memory and stores, in the memory, the result of the logical match between the data D B0  and the data D A1  and the result of the logical match between the data D A1  and the data D B1  which are transmitted from the combinational circuit  333  for a case where an edge is detected. The probability calculating circuit  332  calculates “a probability of a logical match between the data D B0  and the data D A1 ” and “a probability of a logical match between the data D A1  and the data D B1 ” based on the result of the logical match between the data D B0  and the data D A1  and the result of the logical match between the data D A1  and the data D B1  that are stored. 
         [0060]    The probability calculating circuit  334  outputs an instruction to increase or decrease the internal clock frequency based on “the probability of a logical match between the data D B0  and the data D A1 ” and “the probability of a logical match between the data D A1  and the data D B1 ” that are calculated. The probability calculating circuit  334  determines whether or not to increase or decrease the internal clock frequency, based on a truth value table  400  to be described later with reference to  FIG. 6 . 
         [0061]      FIG. 6  is a diagram illustrating an example of the truth value table used by the probability calculating circuit. The probability calculating circuit  334  outputs an instruction to increase or decrease the internal clock frequency based on “the probability of a logical match between the data D B0  and the data D A1 ,” “the probability of a logical match between the data D A1  and the data D B1 ” that are calculated, and the truth value table  400 . 
         [0062]    The probability calculating circuit  334  outputs an instruction to decrease the internal clock frequency when “the probability of a logical match between the data D B0  and the data D A1 ” is 90% or more, and “the probability of a logical match between the data D A1  and the data D B1 ” is 90% or more based on the truth value table  400 . For this reason, when “the probability of a logical match between the data D B0  and the data D A1 ” is 90% or more, and “the probability of a logical match between the data D A1  and the data D B1 ” is 90% or more, the VCO  307  decreases the internal clock frequency. 
         [0063]    The probability calculating circuit  334  does not adjust the internal clock frequency when “the probability of a logical match between the data D B0  and the data D A1 ” is 90% or more, and “the probability of a logical match between the data D A1  and the data D B1 ” is less than 90% based on the truth value table  400 . 
         [0064]    The probability calculating circuit  334  outputs an instruction to increase the internal clock frequency when “the probability of a logical match between the data D B0  and the data D A1 ” is less than 90% based on the truth value table  400 . For this reason, when “the probability of a logical match between the data D B0  and the data D A1 ” is less than 90%, the VCO  307  increases the internal clock frequency. 
         [0065]      FIG. 7  is a flowchart illustrating an exemplary process of the FD control according to this embodiment. When data is received, the receiving circuit  300  starts a FD control process. The phase rotator  310  fixedly sets a phase difference between phases A and B (Operation S 101 ). The edge detector  304  detects a position at which data values of the phases A and B do not match each other as a data edge (transition point) (Operation S 102 ). The data match determining unit  305  determines a logical match between data D B0  and data D A1  and a logical match between the data D A1  and D B1  (Operation S 103 ). 
         [0066]    The data match determining unit  305  determines whether results of the logical match between the data D B0  and the data D A1  and the logical match between the data D A1  and D B1  corresponding to a sufficient number (for example,  100 ) for calculating probabilities are stored in the memory (Operation S 104 ). When it is determined that results corresponding to the sufficient number are not stored in the memory (No in Operation S 104 ), the FD repeats the process from Operation S 102 . When it is determined that results corresponding to the sufficient number are stored in the memory (Yes in Operation S 104 ), the data match determining unit  305  calculates a probability that the logics of the data D B0  and the data D A1  match each other and a probability that the logics of the data D A1  and the data D B1  match each other (Operation S 105 ). The data match determining unit  305  outputs an instruction to increase or decrease the internal clock frequency based on the probability that the logics of the data D B0  and the data D A1  match each other, the probability that the logics of the data D A1  and the data D B1  match each other, and the truth value table  400  (Operation S 106 ). The data match determining unit  305  determines whether or not an error between the internal clock frequency and the data frequency is sufficiently small (converges) (Operation S 107 ). 
         [0067]    When it is determined that the error between the internal clock frequency and the data frequency is not small (No in Operation S 107 ), the FD repeats the process from Operation S 102 . When it is determined that the error between the internal clock frequency and the data frequency is sufficiently small (Yes in Operation S 107 ), the fixation of the phase difference set in the phase rotator  310  is released (Operation S 108 ). When the process of Operation S 108  ends, the control process using the FD ends. 
         [0068]    When the control process using the FD ends, the process proceeds to the PD, and a fine adjustment of the phase and the like is performed. 
         [0069]    In this way, by measuring two points of the phases A and B, the internal clock frequency may be adjusted through the 2×oversampling CDR. By implementing the 2×oversampling CDR, compared to 4×oversampling, the number of comparators may be decreased, and the circuit scales of a clock buffer, a demultiplexer, and the like may be decreased. As a result, the amount of power consumption may also be reduced. 
         [0070]      FIG. 8  is a diagram illustrating an example of another 2×oversampling CDR circuit. In a receiving circuit  500  of  FIG. 8 , the same configuration as that of the receiving circuit  300  of  FIG. 3  will be denoted by the same reference numeral as used for the receiving circuit  300  of  FIG. 3 . The receiving circuit  500  includes a demultiplexer  501  between the sampler  302  and the FD  303  of the receiving circuit  300 . 
         [0071]    The demultiplexer  501  extracts components of an input signal and outputs the components as individual signals. By measuring two points of the phases A and B, the internal clock frequency may be adjusted through the 2×oversampling CDR. By implementing the 2×oversampling CDR, compared to 4×oversampling, the number of comparators may be decreased, and the circuit scales of a clock buffer, a demultiplexer, and the like may be decreased. As a result, the amount of power consumption may also be reduced. 
         [0072]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to an illustrating of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.