Abstract:
Latch structures and systems are disclosed that enhance latch speed and provide complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to enhance regenerative feedback signals and generate CMOS-level latch signals.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application Ser. No. 60/387,525 filed Jun. 6, 2002. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to electronic latches. 
     2. Description of the Related Art 
     A variety of modern signal-conditioning systems require electronic latches which can be latched to indicate the state of a fluctuating input signal at a selected latch time. Because these systems often process complementary metal-oxide-semiconductor (CMOS) signals and generally operate at high speeds, there is a continuing search for latch structures that enhance latch speed but provide CMOS-level latch signals. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to latch structures and systems that realize enhanced latch speed while providing CMOS-level latch signals. These goals are realized with bipolar junction structures and CMOS structures that are arranged to enhance regenerative feedback signals and generate CMOS-level latch signals. 
     The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a latch embodiment of the present invention; and 
     FIG. 2 is block diagram of an analog-to-digital converter that includes the latch of FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a latch embodiment  20  that receives a differential input signal S in  at a differential input port  22 . The latch tracks the input signal during an acquire mode and transitions from the acquire mode to a latch mode in response to a latch command signal S ltchcmd  at a command port  23 . During the latch mode, the latch provides, at a differential output port  24 , a differential output signal S out  which corresponds to the state of the input signal S in  at the time that the latch command signal S ltchcmd  was initiated. The latch&#39;s structure obtains a number of significant advantages which are indicated in the following description. 
     In particular, the latch  20  includes a differential amplifier  25 , a cross-coupled pair  26  of first and second isolation transistors  27  and  28 , a cross-coupled pair  30  of first and second latch transistors  31  and  32  and a pair  34  of first and second current-limiting transistors  35  and  36 . The isolation transistors  27  and  28  have first current terminals (e.g., sources)  37  and second current terminals  38  (e.g., drains), the latch transistors  31  and  32  provide collectors  39  and the current-limiting transistors  35  and  36  are each coupled between a respective one of the second current terminals  38  and a respective one of the collectors  39 . The differential amplifier  25  is coupled between the differential input port  22  and the first current terminals  37  and provides a differential signal, e.g., a differential current  40 , in response to the input signal S in . 
     The latch  20  also includes a pair  42  of first and second switches  43  and  44  and preferably includes a shorting transistor  46  that are all responsive to the latch command signal S ltchcmd  at the command port  23 . The switches  43  and  44  are coupled to the first current terminals  37  and the shorting transistor  46  is coupled between the collectors  39 . 
     The latch  20  further includes first and second control transistors  50  and  51  that each have a base coupled to a respective one of the collectors  39  and has a collector coupled to a control terminal (e.g., gate) of the current-limiting transistor that is also coupled to that respective one of the collectors  39 . Preferably, resistors  52  and  53  are inserted in the bases of the control transistors  50  and  51  and resistors  54  and  55  couple their collectors to a supply voltage (e.g., V DD ). 
     The cross-coupling of the isolation transistors  27  and  28  and the latch transistors  31  and  32  provides positive feedback which will urge the latch transistors into one of two stable states in response to the differential current  40  (latch transistor  31  is on and latch transistor  32  is off in a first state and latch transistor  31  is off and latch transistor  32  is on in a second state). In an acquisition operational mode, however, the latch command signal S ltchcmd  is in a state that turns off the switches  43  and  44  and causes the shorting transistor  46  to present a low shorting impedance between the collectors  39 . 
     Accordingly, the low shorting impedance of the shorting transistor  46  substantially eliminates feedback signals and the latch transistors  31  and  32  are thus restrained from moving to either of their stable states. In addition, the switches  43  and  44  do not supply currents that would support either stable state. In the acquisition mode, therefore, the collectors  39  remain relatively low so that the control transistors  50  and  51  remain off and a high signal (V DD ) is applied to the control terminals (e.g., gates) of the current-limiting transistors  35  and  36 . In response, these transistors present relatively low acquire impedances. 
     The latch operational mode is initiated when the latch command signal S ltchcmd  changes to a state that turns on the switches  43  and  44  and causes the shorting transistor  46  to transition from its low shorting impedance to a greater isolating impedance. Accordingly, the cross-coupled feedback process of the latch is enabled and it rapidly urges the latch  20  into the stable state that is indicated by the differential current  40  at the time when the latch command signal S ltchcmd  was initiated. 
     In the indicated stable state, one of the latch transistors  31  and  32  is on and the other is off. The base of the “on” latch transistor provides a sense signal S sns  to the base of one of the control transistors  50  and  51 . In response, that control transistor&#39;s collector provides a control signal S cntrl  to the gate of one of the current-limiting transistors that causes its impedance to transition from the low acquire impedance to a greater latch impedance. In particular, the control signal S cntrl  is substantially V be +V gs  wherein V be  is the base to emitter voltage of the control transistor and V gs  is the gate-to-source voltage of the current-limiting transistor. 
     This lowered control signal initiates the significantly greater latch impedance in the current-limiting transistor which reduces the base current to the “on” latch transistor and limits its saturation. The latch impedance also generates the upper level of a CMOS-level signal at a corresponding side of the output port  24  while the lower level is provided at the other side of the output port. 
     As with any electronic structure, parasitic capacitances are inevitably associated with the output signal port  24  and, accordingly, the regenerative time constant of the latch  20  is proportional to this parasitic capacitance divided by the transconductance of either of the latch transistors  31  and  32 . Because the transconductance of bipolar junction transistors is proportional to their collector current, they generally provide a substantially lower time constant than other transistors. 
     Accordingly, latch structures of the present invention realize a number of important latch features. First, they provide CMOS-level output signals S out  which are desired by a variety of CMOS systems yet their latch speed is enhanced because cross-coupled bipolar junction latch transistors drive the latch&#39;s regenerative feedback. Current drain is reduced because the current drawn from the switches ( 43  and  44 ) that corresponds to an “off” isolation transistor ( 27  or  28 ) drops to substantially zero and the base current to the “on” latch transistor is limited. The limited base current further enhances the latch speed. 
     Latch embodiments of the invention are especially important in systems that employ a significant number of latches. For example, FIG. 2 illustrates a flash analog-to-digital converter (ADC)  60  which converts an analog input signal S in  at an input port  62  to a digital output signal S out  at an output port  64 . The ADC  60  includes a sampler  66 , comparators  68 , latches  70  and encoders  72 . 
     A resistive ladder  74  provides reference signals S ref  and, in response to the input signal S in  (which may be a differential signal) and timing signals T s , the sampler  66  provides sample signals S smpl . The comparators compare each sample signal to the reference signals and provide decision signals S dcsn  that define the state of the sample relative to the reference signals. 
     In response to a latch command signal S ltchcmd  (also shown at command port  23  in FIG.  1 ), the latches  70  provide latched output signals S ltchd  which correspond to the state of the decision signals S dcsn  at the time of the latch command signal S ltchcmd . The latched output signals S ltchd  are then converted to various digital output signal formats, e.g., an N-bit binary output or a Gray-code binary output). 
     Although latch embodiments of the invention essentially perform a sampling process, the flash ADC  60  preferably includes the sampler  66  so that the comparators  68  can process a held signal rather than a changing signal. Because the ADC  60  may contain a substantial number of latches, its current drain can be significantly reduced by use of the latch embodiments of the invention. 
     The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.