Abstract:
An electronic odometer is disclosed, in which, in order to provide higher reliability, integrated traveled distance data to be stored in a nonvolatile memory is divided into three portions, i.e., high order digit data, medium order digit data, and low order digit data. A plurality of memories constituting the nonvolatile memory having the digit representative of the medium order digit data as the address thereof or as a part of the address thereof are selected, and the high order digit data which is required to be the most reliable of the three portions is written into at least three of the selected memories. The low order digit data is written into at least one of the rest of the selected memories. When extracting the integrated traveled distance data from these memories, the high order digit data is determined by applying majority rule to the data read out from the three memories. It is thus achieved to enhance the reliability on the integrated traveled distance data by the application of majority rule.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an electronic odometer mounted on a vehicle for writing and reading data of integrated distance traveled using an EEPROM. 
     2. Description of the Prior Art 
     An electronic type odometer indicating an integrated distance traveled by a vehicle is arranged such that signals from a traveled distance sensor capable of generating the signal representative of number of revolutions of a wheel shaft or the like are counted and the integrated traveled distance obtained from the number of counts is indicated on a suitable digital indicator. Since the odometer uses the battery of the vehicle as its power source, it is necessary to supply it with electricity at all times so that the data of the integrated traveled distance may not be lost even when power supply to the counter portion is removed due to exchange of the battery or such trouble as line breakage, or the data may not be lost when the main power supply to the vehicle is turned off. To meet this necessity, it is practiced to write data of integrated traveled distance into a nonvolatile memory. 
     Under the present situations, however, there is a limit to the number of times of writing into a nonvolatile memory. To cope with this problem, there have been proposed various means such as that disclosed in the gazette published by the Patent Office of Japan for Laid-open Patent Publication No. 56-84512 wherein a counted from a preset counter is stored in a nonvolatile memory at the time when power is turned off. When the operation is resumed, the data from the memory is preset in the counter. Japanese Laid-open Patent Publication No. 56-154611 teaches counting by a C-MOS counter wherein a plus 1 is written into a nonvolatile memory by a carry generator each time a carry is generated while keeping the C-MOS counter supplied with power at all times. Japenese Laid-open Patent Publication No. 59-196414 teaches having the data of the integrated traveled distance sequentially written into a plurality of nonvolatile memories thereby updating the data every time a predetermined distance has been traveled and, when the operation is resumed, having all the data in the plurality of nonvolatile memories read out and the maximum value of them selected. 
     In writing integrated traveled distance data into a nonvolatile memory, the number of times of writing for updating data in a nonvolatile memory is reduced by the above described prior art, but there still remains a point somewhat problematic as to the realiability on the data obtained at the time of resuming operation. That is, supposing erroneous data are written in the nonvolatile memory, determination whether some data is erroneous or not will become more reliable if sets of data sufficiently large in number are written in the memory. In this sense, the number of sets of data written in the memory in the above described prior art is considered insufficient. 
     Hence, an invention was made as disclosed in the gazette published by the Patent Office of Japan for Laid-open Patent Publication No. 62-201312, in which, when employing a nonvolatile memory, the memory address was used as a portion of the integrated traveled distance data, thereby achieving reduction in number of times of writing data into the nonvolatile memory and enhancement of reliability on the data. 
     SUMMARY OF THE INVENTION 
     In order to provide higher reliability than was obtained in the above described prior art, integrated traveled distance data to be stored in a nonvolatile memory is divided into three portions, i.e., high order digit data, medium order digit data, and low order digit data. A plurality of memories, constituting the nonvolatile memory, are selected using the digit representative of the medium order digit data as the address thereof or as a part of the address thereof. The high order digit data which is required to be the most reliable of the three portions are written into at least three of the selected memories. The low order digit data is written into at least one of the other selected memories. When extracting the integrated traveled distance data from these memories, the high order digit data is determined by applying majority rule to the data read out from the three memories. Thus, the present invention aims at enchancement of the reliability on the integrated traveled distance data by the application of majority rule. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram showing an electronic odometer; 
     FIG. 2 is an explanatory diagram showing the relationship between memories and written data in an EEPROM in a first embodiment; 
     FIG. 3 is an explanatory diagram showing relationship between memories and written data in an EEPROM in a second embodiment; and 
     FIG. 4 is an explanatory diagram showing relationship between and written data in an EEPROM in a third embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will be described below with reference to the accompanying drawings. 
     FIG. is a schematic block diagram showing the present invention. A traveled distance sensor 1 outputs a pulse signal every time the vehicle travels a predetermined distance. A CPU 2 causes a RAM 3 included therein to store the number of the pulse signals and every time value is increased by an amount corresponding to &#34;1&#34; km of traveled distance, for example , the CPU 2 alters the indicated value on the indicator display 4 by supplying it with an increment of &#34;1&#34; km, and at the same time, alters the value stored in an EEPROM 5 as a nonvolatile memory externally provided for the CPU 2 by supplying it with an increment of &#34;1&#34; km. The EEPROM 5 is provided so that, even when the data of traveled distance up to a point of time is erased from the RAM 3 during loss of power, for example, while exchanging the battery, the accurate data of traveled distance up to that point of time can always be restored by transferring the data from the EEPROM 5 to the RAM 3. 
     FIG. 2 is a drawing for explaining memory structure of the EEPROM 5 and writing operation for altering data therein in a first embodiment. The EEPROM 5 is comprised of a total of 40 memories at addresses from &#34;00&#34; to &#34;39&#34;, each memory being formed of 16 14ts. The traveled distance data used in the present embodiment comprises six digits. The higher order four digits will be taken as &#34;high order digit data&#34;, the lowest-order digit will be taken as &#34;low order digit data&#34;, and the remaining one digit will be taken as &#34;medium order digit data&#34;. For example, when &#34;123456&#34; km is used as one example of the distance data, &#34;1234&#34;, &#34;6&#34;, and &#34;5&#34; correspond to the high order digit, low order digit, and medium order digit data, respectively. Such division is determined based on reliability of data. More specifically, while a change of &#34;1&#34; made by mistake in the high order digit data means an error in units of at least &#34;100&#34; km, a change of &#34;1&#34; in the medium and low order digit data can be confined within an error in units of at most &#34;10&#34; km. 
     Then , a means must be devised to control occurrence of an error in altering the high order digit data. To improve the reliability on the data in the present embodiment, the high order digit data is written into memories at three addresses selected out of the addresses &#34;00&#34; to &#34;29&#34; using the medium order digit data as an address. The low order digit data is written into a memory at one address selected according to the medium order digit data out of the addresses &#34;30&#34; to &#34;39&#34;. More specifically, since the medium order digit data is &#34;5&#34; in the data &#34;123456&#34; km, four addresses &#34;05&#34;, &#34;15&#34;, &#34;25&#34;, and &#34;35&#34; are selected, and the addresses &#34;05&#34;, &#34;15&#34;, and &#34;25&#34; are used the high order digit data and the address &#34;35&#34; is used for the low order digit data. 
     Operation will be described below. The case where write operation is performed while the power is being normally supplied will be described first. 
     When the CPU 2 has counted the pulse signals from the traveled distance sensor 1 which corresponds to &#34;1&#34; km and alters the value in the RAM 3 from &#34;123455&#34; km to &#34;123456&#34; km, the data in the EEPROM 5 must also be altered from &#34;123455&#34; km to &#34;123456&#34; km. The CPU 2, first, reads the data in the RAM 3 and adds &#34;1&#34; km to the data &#34;123455&#34; km thereby altering it to &#34;123456&#34; km. The CPU 2 also divides data into the high order digit data constituted of four digits from the most significant digit, &#34;1234&#34;, medium order digit data constituted of the fifth digit from the most significant digit, &#34;5&#34;, and low order digit data constituted of the sixth digit from the most significant digit, &#34;6&#34;. In the alteration of data at this time, the data which must be altered is only the sixth digit, &#34;5&#34;, to be altered to &#34;6&#34;. Hence, no alteration for the high order digit data is performed, but the low order digit data &#34;6&#34; is written into memory at the address &#34;35&#34; selected according to the medium order digit data, &#34;5&#34; thereby finishing the alteration. 
     In succession to the above described operation, the alteration from 
     
         ______________________________________  from &#34;123456&#34; km       ↓       &#34;123457&#34; km       ↓       &#34;123458&#34; km       ↓  to   &#34;123459&#34; km______________________________________   to 
    
     is effected only by changing the data in the memory at the address &#34;35&#34; in this way , &#34;6&#34;→&#34;7&#34;→&#34;8&#34;→&#34;9&#34;. 
     Now, the case where the data is altered from &#34;123459&#34; km to &#34;123460&#34; km will be described. 
     The CPU 2, the same as before, divides the data &#34;123460&#34; km, obtained by adding &#34;1&#34; km to &#34;123459&#34; km, into the high order digit data constituted of four digits from the most significant digit, &#34;1234&#34;, the medium order digit data constituted of the fifth digit from the most significant digit, &#34;5 &#34;, and the low order digit data constituted of the sixth digit from the most significant digit, &#34;0&#34;. The low order digit data being &#34;0&#34; means that a carry to the medium order digit data has been generated. In fact, the medium order digit data is changed from &#34;5&#34; to &#34;6&#34;. At this time , the CPU 2 selects addresses &#34;06&#34;, &#34;16&#34;, &#34;26&#34;, and &#34;36&#34; anew according to the new medium order digit data &#34;06&#34;, and writes the high order data &#34;1234&#34; into the addresses &#34;06&#34;, &#34;16&#34; , and &#34;26&#34; and the low order digit data &#34;0&#34; into the address &#34;36&#34; and thereby finishes the alteration. 
     Thus, relationships between the medium order digit data and the selected addresses become as shown below. 
     
         ______________________________________ ##STR1## 
    
     
         ______________________________________ ##STR2##______________________________________ 
    
     The medium order digit data is the data of the second digit from the least significant digit, namely, it is the data representing the tens digit, and therefore, it is altered with an increment of &#34;1&#34; for every 10 km, and it reverts to the same data after traveling of &#34;100&#34; km. This means that the same memories are selected again when a distance of &#34;100&#34; km is traveled. To be more specific, paying attention to one of the memories for the high order digit, the memory at the address &#34;01&#34;, for example, it is only when the medium order digit data is altered from &#34;0&#34; to &#34;1&#34; that data is written into the address &#34;01&#34;, and it is when a distance of &#34;100&#34; km has been traveled that the medium order digit data is altered again from &#34;0&#34; to &#34;1&#34;. This means that writing into the memory for the high order digit data is executed once for each &#34;100&#34; km and , hence, 10 3  times of writing is made therein while a distance of 100,000 km is traveled. This number of times is sufficiently small to meet the condition for the upper limit of the number of times for writing data into the EEPROM 5, 10 4  times. As to the memory for the low order digit data, however, data is written therein at the rate of 10 times for each &#34;100&#34; km distance, and hence, writing is made 10 4  times therein while the distance of 100,000 km is traveled. In this case, the condition for the upper limit is barely met. 
     Thus, while the power is being normally supplied, the data of integrated traveled distance is written into the EEPROM 5 without violating the condition for upper limit of the number of times of writing into the EEPROM 5. 
     When the power supply to the CPU 2 is temporarily stopped for such reason as exchanging the battery, the data stored in the RAM 3 within the CPU 2 becomes lost. As a measure to meet the situation, the latest data is read from the EEPROM 5 and the read data is transferred to the RAM 3. Through this process, the RAM 3 is enabled to restore the same data as stored therein before the data was lost. 
     Referring again to FIG. 2, the operation to read out data from the EEPROM 5 will be described below. 
     We suppose now that trouble as described above has occurred when the data in the RAM 3 is &#34;123456&#34; km. The contents in the memories of the EEPROM 5 at this time are the same as shown in FIG. 2. In order for the CPU 2 to read out the data &#34;123456&#34; km from the EEPROM 5, it must first search for the memory loaded with the latest data. The method for the searching is disclosed in the gazette published by the Patent Office of Japan for Laid-open Patent Publication No. 62-254013. 
     As shown in FIG. 2, the next higher values of data is stored in sucessively higher locations of the memory. As shown, the most recently loaded location will be the highest addressed location before a change to a lower value. In the example of FIG. 2, locations 00 to 05 store the high order data value &#34;1234&#34; and locations 06 to 09 store the next lower high order data value &#34;1233&#34;. Similarly, locations 10 to 15 store the high order value &#34;1234&#34; while locations 16 to 19 store the next lower high order data value &#34;1233&#34;; and the locations 10 to 15 store the high order data value &#34;1234&#34; while locations 16 to 19 store the next lower high data value &#34;1233&#34;. As shown in FIG. 2 a first change in the stored data value occurs at location 06, a second change in the stored data value occurs at the location 16, and a third change occurs at the location 26. The correct start point in each address range, i.e. the location most recently written into, is the location preceding the change point. In the example of FIG. 2, the most recently written high order locations therefore are 05, 15 and 25. 
     To recognize the correct start points, data values in different locations are compared sequentially to determine the change points, preferably in the manner disclosed in Japanese Patent Laying Open No. 62-254013. Having found the change point by such a comparative process, or similar search technique, the location having an address number one less than the change point will be selected as the locations most recently written. 
     When the addresses of the memories storing the latest data for the high order digit are found to be &#34;05&#34;, &#34;15&#34;, and &#34;25&#34; through the above mentioned searching method, the CPU 2 applies majority rule to &#34;1234&#34;, &#34;1234&#34;, and &#34;1234&#34; written in the three memories and determines the data &#34;1234&#34; as the high order digit data. As to the data of the medium order digit, it also applies majority rule to the lower order digits of the selected addresses &#34;05&#34;, &#34;15&#34;, and &#34;25&#34; and determines &#34;5&#34; as the medium order digit data. As to the low order digit data, the CPU 2 reads out &#34;6&#34; written in the memory at the address &#34;35&#34; according to the medium order digit data &#34;5&#34; and determines the data &#34;6&#34; as the low order digit data. 
     Even when the data at the address &#34;05&#34; is not &#34;1234&#34; but &#34;1230&#34;, the data &#34;1234&#34; at the addresses &#34;15&#34; and &#34;25&#34; is preferentially taken up by majority rule and this data &#34;1234&#34; is determined to be the high order digit data. 
     When the CPU 2 in search for the address &#34;05&#34; has selected the address &#34;06&#34; by mistake, the data written at the address &#34;6&#34; is &#34;1233&#34;. However, the same as described above, the data &#34;1234&#34; written at the addresses &#34;15&#34; and &#34;25&#34; is determined as the high order digit data. Also as to the medium order digit data, the lower order digit &#34;5&#34; of the addresses &#34;15&#34; and &#34;25&#34; is preferentially selected by majority rule and this data &#34;5&#34; is determined to be the medium order digit data. 
     Accordingly, the present embodiment has an effect that, when integrated traveled distance data are to be transferred from the EEPROM to the RAM 3, the high order digit data and medium order digit data requiring higher reliability are determined by majority rule, and therefore, even when the CPU 2 makes a malfunction or a certain error is included in the data in the EEPROM 5, accurate data of integrated traveled distance can be transferred to the RAM 3. 
     Referring now to FIG. 3, a second embodiment of the present invention will be described, but since it differs from the above described embodiment only in the method of writing the low order digit data, this part only will be described below. 
     The above described embodiment was such that only one set of the low order digit data is written in one of the memories at the addresses &#34;30&#34; to &#34;39&#34; allotted to the low order digit data. In the present embodiment, it is made possible to write three sets of data into one memory. 
     As shown in FIG. 3, three sets of data &#34;6&#34; for the low order digit are written in the memory at the address &#34;35&#34;. 
     Therefore, when the integrated traveled distance data are transferred from the EEPROM 5 to the RAM 3, majority rule is applied not only to the high order digit data and medium order digit data, but also to the low order digit data, of which three sets of data are written in one memory. Accordingly, the reliability on the integrated traveled distance data can be enhanced. 
     FIG. 4 shows a third embodiment of the present invention. 
     The memory structure is such that there are set up totally 60 memories at addresses from &#34;00&#34; to &#34;59&#34; therein, each memory of those at the addresses from &#34;00&#34; to &#34;29&#34; is constituted of 12 bits for writing in high order digit data and each memory of those at the addresses from &#34;30&#34; to &#34;59&#34; is constituted of 8 bits for writing in low order digit data. Also in this embodiment, six-digit data is used for the integrated traveled distance data. When the data &#34;123456&#34; is again taken as a particular example, &#34;123&#34; corresponds to the high order digit data, &#34;4&#34; corresponds to the medium order digit data, and &#34;56&#34; corresponds to the low order digit data. 
     There are six memories which are selected according to the data of the medium order digits. The addresses of these memories are &#34;04&#34;, &#34;14&#34;, &#34;24&#34;, &#34;34&#34;, &#34;44&#34;, and &#34;54&#34;. In the memories at the addresses &#34;04&#34;, &#34;14&#34;, and &#34;24&#34;, there is written the high order digit data &#34;123&#34;, and in the memories at the addresses &#34;34&#34;, &#34;44&#34;, and &#34;54&#34;, there is written the low order digit data &#34;56&#34;. 
     As the integrated traveled distance data is increased, the data in the memories at the addresses &#34;34&#34;, &#34;44&#34;, and &#34;54&#34; is altered in increments of &#34;1&#34;. 
     When such data is changed from &#34;99&#34; to &#34;00&#34;, a carry is generated and the medium order digit data is also altered with an increment of &#34;1&#34;. Thus, it is altered from &#34;4&#34; to &#34;5&#34;, whereby memories at the addresses &#34;05&#34;, &#34;15&#34;, &#34;25&#34;, &#34;35&#34;, &#34;45&#34;, and &#34;55&#34; are selected anew as the six memories. The high order digit data &#34;123&#34; and the low order digit data &#34;00&#34; are written into the newly selected memories, followed by similar operations. The memories at the addresses &#34;34&#34;, &#34;44&#34;, and &#34;54&#34; in which the data have been altered at every increase of &#34;1&#34; km will not be written in, with data therein remaining &#34;99&#34;, until a distance of &#34;100&#34; km is traveled and the medium order digit becomes &#34;4&#34; again. It is after a distance of &#34;1000&#34; km has been traveled that the memories at the addresses &#34;04&#34;, &#34;14&#34;, and &#34;24&#34; are written in again. 
     Therefore, during the period that a distance of 100,000 km is traveled, the memories at the addresses &#34;00&#34; to &#34;29&#34; are each written in 10 3  times, and the memories at the addresses &#34;30&#34; to &#34;59&#34; are each written in 10 4  times. Each of which meets the condition for uppper limit of the times of writing into the EEPROM 5. 
     When it becomes necessary to read out the data of integrated traveled distance from the EEPROM 5 for some trouble as described before, supposing that the contents of the memories at that time are the same as shown in FIG. 4, the CPU 2 searches for the six memories in which the latest data are written and picks out those at the addresses &#34;04&#34;, &#34;14&#34;, &#34;34&#34;,&#34;44&#34;, and &#34;54&#34;, and then reads out data &#34;123&#34;, &#34;123&#34;, and &#34;123&#34; from the former three memories and determines the high order digit data to be &#34;123&#34; by majority rule. Similarly, data &#34;56&#34;, &#34;56&#34;, and &#34;56&#34; are read out from the latter three memories and the low order digit data is determined to be &#34;56&#34; by majority rule. For the medium order digit data, by suitably selecting five addresses from the addresses of the six memories and applying majority rule to the lower digit of the addresses, it is enabled to determine the medium order digit data to be &#34;4&#34;. 
     Also in this embodiment, the reliability on the integrated traveled distance data read out from the EEPROM 5 can be enhanced. 
     The present invention has other applications than those in the above described embodiments. For example, when the integrated traveled distance data is indicated to the decimal fraction, integer digits may be taken as the high order digit data and the decimal fraction portion may be taken as the low order digit data. 
     Such a memory structure may also be made which has memories set up at addresses from &#34;00&#34; to &#34;99&#34;, in which high order digit data is written into memories at corresponding seven addresses picked out of those from &#34;00&#34; to &#34;69&#34; and low order digit data is written into memories at corresponding three addresses picked out of those from &#34;70&#34; to &#34;99&#34;, the high order digit data is determined by majority rule applied to data from the seven addresses and the low order digit data is determined by majority rule applied to data from the three addresses, and the integrated traveled distance data read out in accordance with the determined data is displayed on the indicator 4.