Abstract:
To maintain the amplitude of an oscillating signal within a defined range, the detected peak level of the oscillating signal is compared to a reference voltage. If the detected peak level is determined as being greater than the reference voltage, the common source/drain voltage of a differential amplifier driving the crystal oscillator across its input terminals is reduced so as to lower the amplitude of the oscillation signal. If the detected peak level is determined as being smaller than the reference voltage, the common source/drain voltage of the differential amplifier driving the crystal oscillator is increase so as to raise the amplitude of the oscillation signal.

Description:
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   BACKGROUND OF THE INVENTION 
   The present invention relates to integrated circuits, and more particularly to regulating the amplitude of an oscillating signal. 
   Crystal oscillators are widely used in electronic circuits and use stable electromechanical resonance characteristics of a piezoelectric crystal, such as quartz, to generate a clock signal. When a quartz crystal is cut along certain crystal axes to form parallel-plate electrodes, it can be made to resonate when excited. The resonant frequency depends on the material and dimensional properties of the crystal, such as the size, the orientation of the crystal faces, and the mounting of the crystal on its mechanical supports. Because of their insensitivity to time and temperature variations, crystal oscillators are widely used in applications requiring clock signals. 
     FIG. 1  is a transistor schematic diagram of an oscillator  10  as known in the prior art. Oscillator  10  is shown as including a crystal  20  disposed between input and output terminals of a CMOS inverter formed by PMOS transistor  12  and NMOS transistor  14 . The oscillation signal generated between nodes X 1  an X 2  has an amplitude that varies between supply voltages Vdd and ground. Oscillator  10  is thus inappropriate for use in applications requiring relatively high accuracy oscillation frequency driven by small time-varying signals. 
   BRIEF SUMMARY OF THE INVENTION 
   In accordance with one embodiment of the present invention, an amplitude modulating circuit adapted to modulate the amplitude of a crystal oscillator includes, in part, a peak detector, an amplitude regulator, and a differential oscillator. The peak detector detects the peak level of the oscillating signal. The amplitude regulator compares the detected peak level with a level-shifted reference voltage. If the detected peak level is determined as being greater than the level-shifted reference voltage, the common voltage of a differential amplifier disposed in the differential oscillator, configured to drive the crystal oscillator across its input terminals, is reduced so as to lower the amplitude of the oscillation signal. The reverse operation occurs if the detected peak level is determined as being smaller than the reference voltage. 
   In some embodiments, the peak detector includes a transistor adapted to receive the oscillating signal and to charge a capacitor to a voltage representative of the detected peak level. A second transistor disposed in the peak detector enables the capacitor to be discharged during off periods. 
   A pair of diode-connected transistors disposed in a first leg of the amplitude regulator generates the reference voltage. A second pair of transistors disposed in a second leg of the amplitude regulator shift the voltage level of the reference voltage. A differential amplifier disposed in the amplitude regulator compares and amplifies the detected peak level to the level-shifted reference voltage. If the detected peak level is greater than the level-shifted reference voltage, the node supplying voltage to an input terminal of a differential amplifier disposed in the amplitude regulator is reduced. This, in turn, causes a voltage controlling the common voltage of the differential amplifier disposed in the differential oscillator to decrease, thereby causing a reduction in the amplitude of the differential signal. If, on the other hand, the detected peak level is smaller than the level-shifted reference voltage, the node supplying voltage to the input terminal of the differential amplifier disposed in the amplitude regulator is reduced. This, in turn, causes the voltage controlling the common-voltage of the differential amplifier disposed in the differential oscillator to increase, thereby causing an increase in the amplitude of the differential signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of an oscillator, as known in the prior art. 
       FIGS. 2A and 2B , collectively forming  FIG. 2 , are schematic diagrams of an amplitude-regulated crystal oscillator, in accordance with one embodiment of the present invention. 
       FIG. 3  is a timing diagram of a number of signals generated by the voltage-controlled crystal oscillator of  FIG. 2 , in accordance with one embodiment of the present invention. 
       FIG. 4  is a schematic diagram of a voltage-controlled oscillator, in accordance with one embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 2A and 2B , collectively forming  FIG. 2 , are transistor schematic diagrams of an oscillator  100 , in accordance with one embodiment of the present invention. Oscillator  100  is shown as including a biasing circuit  150 , a peak detector  200 , an amplitude regulator  250 , a differential oscillator  300 , and a differential comparator  350 , in accordance with one embodiment of the present invention. 
   Transistors  47 ,  78 ,  63  and  79  of biasing circuit  150  form a cascode current mirror. Signal PD is applied to inverter  102  whose output signal PDB is applied to inverter  104 . Signal PDB is applied to the gate terminal of PMOS transistor  68 . The output signal of inverter  104  is applied to the gate terminal of transistor  67 . Transistors  67  and  68  are used to power down biasing circuit  150 , which in turn, turns off oscillator  100 . Transistor  60  of peak detector  200  and transistors  61  and  62  of amplitude regulator  250  are current source transistors biased using diode-connected transistor current source  64  of biasing circuit  150 . The signal PD is also used to power down current sources formed by transistors  60 ,  61  and  62 . This, in turn, powers down oscillator  100 . 
   Differential oscillator  300  includes a differential stage  305 , that includes transistors  48  and  49 . Current-source transistor  32  is used to bias differential oscillator  300 . Transistors  50  and  27  provide a load to differential stage  305 . Differential stage  305  is a differential inverter that inverts the signal received via node X 1 , coupled to the gate terminal of transistor  49 , and generates a signal X 2  coupled to the drain terminal of transistor  49 . Transistors  76  and  77  form a transmission gate providing a resistive load between the gate and drain terminals of transistor  49 . Crystal oscillator  308  is disposed between the gate and drain terminals of transistor  49  and is understood to be external to oscillator  100 . Because of transmission gate  310  nodes X 1  and X 2  are at the same DC bias. 
   The amplitude of the oscillation signal generated by crystal oscillator  308 , in accordance with one embodiment of the present invention, is allowed to oscillate between the ground potential—via transistor  27 —and the voltage present on node Vs. The source terminals of both transistors  48  and  49 , and the drain terminal of transistor  32  are also connected to node Vs. 
   The voltage at node Vs is controlled by the voltage at node Va to which the gate terminals of transistors  48  and  54  are coupled. In other words, the voltage variations at node Vs follow the voltage variations at node Va. Accordingly, by controlling the voltage at node Va, the amplitude of the signal between nodes X 1  and X 2  is regulated. 
   Transistor  60  together with transistor  56  and capacitor  202 , in part, form a peak detector  200 . Peak detector  200  is adapted to detect the peak amplitude of the voltage signal present on node X 2 . The detected peak level at node Vpk is smaller than the voltage present on node X 2  by the threshold voltage of transistor  56 . As the sinusoidal voltage on node X 2  rises, the voltage at node Vpk that is coupled to the source terminal of transistor  56  also rises. 
   Capacitor  202  stores the charges present on node Vpk. As the voltage on node X 2  falls, because the source terminal of transistor  56  is maintained substantially at its peak value established by the charges stored in capacitor  202 , transistor  56  is turned off. In other words, the voltage at node Vpk follows the voltage at node X 2  as the voltage at node X 2  rises, but droops down slowly as the voltage at node X 2  falls. Transistor  60  is used to enable node Vpk to be reset to the ground potential when the oscillator  308  is shut down by providing a slow discharge path for the charges stored across capacitor  202 .  FIG. 3  shows a timing diagram of voltages at nodes X 2 , Vref, Vamp 1  and Vpk. Capacitor  204 , which is a compensation capacitor, together with resistor  206 , which is a nulling resistor, ensure that the peak detector is stable and does not oscillate. 
   Amplitude regulator  250  includes, in part, a differential amplifiers stage  252  that is biased by transistor current source  62 . The channel-widths and channel-lengths of diode-connected transistors  54  and  55  are selected so as to establish a desired DC bias voltage at node Va. For example, in one embodiment when the supply voltage Vcc is at 3 volts, the channel-widths and channel-lengths of transistors  54  and  55  are selected such that node Va is at 2 volts. Similarly, the channel-widths and channel-lengths of diode-connected transistors  65  and  66  are selected so as to establish a desired reference voltage at node Vref. The reference voltage level at node Vref is shifted down by the gate-to-source voltage of transistor  59  to generate the voltage at node Vamp 1 . 
   Transistors  59  and  61  together form a source-follower amplifier. Transistors  59  and  61  respectively match and track transistors  56  and  60  disposed in peak detector  200 . Therefore, the voltage at node Vref defines, in part, the peak voltage of the oscillation. For example, if the voltage at Vref is set to 2 volts, the voltage at node X 2  cannot exceed 2 volts. 
   The voltage at node Vamp 1 , i.e., the source terminal of transistor  59 , is maintained equal to the voltage at node Vpk, i.e., the source terminal of transistor  56  by the differential stage  252 . Therefore, the voltage at node Vref defines the voltage at node Vamp 1 , which in turn, defines the voltage at node Vpk. 
   Assume that the voltage at node Vpk rises in response to the rising amplitude of the voltage at node X 2 . Therefore, the voltage at node Vpk exceeds the voltage at node Vamp 1 . This causes transistor  57  to conduct more current, thereby pulling the voltage at node Va lower. The reduction in the voltage at node Va, in turn, causes the voltage at node Vs to go down, which in turn causes the amplitude of the voltage at nodes X 1  and X 2  to decrease. Therefore, if the amplitude of signals at node X 1  and X 2  exceeds Vref, amplitude regulator  250  reduces the voltage at node Va. This reduction, in turn, reduces the voltage at node Vs so as to cause the amplitude at nodes X 1  and X 2  to decrease. The reverse operations happen if the amplitude of signals at node X 1  and X 2  falls below the voltage at node Vref. 
   In the embodiment shown in  FIG. 2 , the voltage at node Vref is defined by the channel-width to channel-length ratio of transistors  65  and  66 . It is understood, however, that any other circuit that generates a voltage reference, such as a bandgap circuit may also be used to establish the voltage at node Vref. As descried above, the voltage at node Vamp 1  is level shifted with respect to voltage at node Vref. If the voltages at nodes Vamp 1  and Vpk are equal, then the amplitude of signals X 1  and X 2  is the same as the voltage Vref. 
   If the amplitude of the signals at nodes X 1  and X 2  increases above Vref, the voltage at node Vpk increase, thereby causing the voltage at node Va to decrease. This, in turn, causes the voltage at node Vs to decrease thus causing the amplitude of signals X 1  and X 2  to decease until the amplitude of signals X 1  and X 2  reaches the voltage level defined by node Vref. If, on the other hand, the amplitude of the signals at nodes X 1  and X 2  falls below Vref, the voltage at node Vpk decreases, thereby causing the voltage at node Va to increase. This, in turn, causes the voltage at node Vs to increase thus causing the amplitude of signals X 1  and X 2  to increase until the amplitude of signals X 1  and X 2  reaches the voltage level of defined by node Vref. Consequently, by modulating the voltage at node Va using amplitude regulator  250 , the amplitude of signals X 1  and X 2  is maintained at the voltage level defined by node Vref. Amplitude regulation is terminated when signal REGB applied to the gate terminal of transistor  80  is raised to a high voltage. 
   Differential comparator  350  is shown as including a differential amplifier  352  biased by transistor  74 . The gate terminal of transistor  75 , i.e., a first input terminal of the differential comparator  350 , is coupled to node X 2 , and the gate terminal of transistor  73 , a second input terminal of the differential comparator  350 , is coupled to node Va. Any differential voltage between these two input terminals is amplified by differential amplifier  352  and buffered by inverters  354  and  356 . The output signal of inverter  356  is a rail-to-rail oscillation signal that is used as a clock signal to other circuits. 
     FIG. 4  is a schematic diagram of a voltage-controlled crystal oscillator  400 , in accordance with one embodiment of the present invention. Voltage-controlled crystal oscillator  400  is shown as including, in part, a crystal oscillator  405 , varactors  410 ,  415 , and an oscillator  100 , as described above. By varying the capacitances of the varactors, the frequency of operation of the signals carried between nodes X 1  and X 2  varies, thus allowing this oscillator to be used as a voltage-controlled-crystal-oscillator (VCXO). The VCXO when used in a feedback loop of a phased-locked-loop (PLL) provide a relatively tight frequency control. 
   The above embodiments of the present invention are illustrative and not limiting. Various alternatives and equivalents are possible. The invention is not limited by the type of peak detector, amplitude regulator, oscillator, differential or otherwise, comparator, etc. The invention is not limited to the frequency of oscillation. The invention is not limited by the type of integrated circuit in which the present disclosure may be disposed. Nor is the disclosure limited to any specific type of process technology, e.g., CMOS, Bipolar, or BICMOS that may be used to manufacture the present disclosure. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.