Abstract:
A method for reducing the noise associated with a clock signal for a latch based circuit has been developed. The method includes storing a charge at a pre-determined time of the clock cycle and releasing the stored charge also at a pre-determined time of the clock cycle. The charge is released onto the power grid of the system served by the clock signal in synchronization with the operation of the latch.

Description:
BACKGROUND OF INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates generally to electronic circuitry. More specifically, the invention relates a method for reducing the noise associated with a clock signal for a latch based circuit.  
           [0003]    2. Background Art  
           [0004]    In all microprocessor-based systems, including computers, the clock circuit is a critical component. The clock circuit generates a clock signal that is a steady stream of timing pulses that synchronize and control the timing of every operation of the system. FIG. 1 shows a prior art diagram of an ideal clock signal  10 . An entire clock cycle  12  includes a rising or leading edge  14  and a falling or trailing edge  16 . These edges  14 ,  16  define the transition between the low phase and high phase of the signal.  
           [0005]    [0005]FIG. 2 shows a block diagram of a prior art local clock signal distribution system. The clock signal  30   a  is input to a clock header  32  which serves to buffer the clock signal. From the header  32 , the clock signal  30   b  is input to an edge-triggered latch  34  where it serves to trigger the latch. A latch is a memory device that is commonly used in integrated circuits. It is dependent upon a clock signal to initiate its function. Latches take input data and distribute output data during the entire clock high phase. Most data tends to be waiting at the latch by the time the clock pulses high, therefore most latches switch on the rising edge of the clock.  
           [0006]    Latches are also made to work on the clock low phase and consequently tend to switch on the falling edge of the clock. Both types of latches are commonly used in order make use of both phases of the clock for computation.  
           [0007]    [0007]FIG. 3 shows a digital logic schematic of the prior art local clock signal distribution system as shown in FIG. 2. The clock signal  30   a  is input to the clock header  32 . The clock header  32  includes a NAND gate  36  and an inverter  38   a.  Once inside the clock header  32 , the clock signal  30   a  is one of the inputs to the NAND gate  36 . The other NAND input  42  is a signal that is HIGH so that the gate  36  simply inverts the value of the clock signal  30   a.  This NAND input  42  is switched to LOW to turn off the clock header  32  if needed. Next, the signal  30   a  passes through the inverter  38   a  which inverts the signal back to its original value. The clock signal  30   b  then passes from the clock header  32  to the latch  34 . Once in the latch  34 , the signal  30   b  is split into two paths. The first path passes through one inverter  38   b,  and the second path passes through two consecutive inverters  38   c  and  38   d.  Each path feeds into separate control transistors  40   a  and  40   b  that control the DATA_IN  44  and DATA_OUT  46  paths of the latch  34 .  
           [0008]    Clock induced supply noise (hereafter “clock noise”) problems on the system power grid are usually caused by the large amount of current that is used in clock signal distribution. This current comes from the switching transistors that are controlled by the clock signal. As these transistors switch states, the current noise spikes onto the power grid due to the current demand or “current draw” of the switching transistors. These high current demands cause noise in the system voltage supply due to voltage (IR) drops and inherent system inductance (L di/dt). A clock signal distribution circuit uses a significant amount of current in a short amount of time because the spikes occur twice per clock cycle: once on the current draw of the leading edge and once on the current draw of the falling edge of the signal. This puts the noise at a very high frequency (2× the clock frequency). This noise can cause missed timing if the power supply is too low or component failure if the power supply voltage is too high. The noise can even escape “off the chip” and affect the other components of the system.  
           [0009]    [0009]FIG. 4 shows a graph of current draw during a clock cycle period of a latch based circuit. The circuit could use both rising edge latches and falling edge latches. The value “I”  35  represents the full value of a current draw. The value “¾ I”  37  represents 75% of the full value while the value “½ I”  39  represents 50% of the full value. The first current draw  41  of the graph represents the draw that results from the leading edge of a clock cycle (at clock cycle=0). The second current draw  43  represents the draw that results from the falling edge of the clock cycle (at clock cycle=t/2). As shown, the leading edge draw  41  is the full value (“I”) of current draw. The trailing edge draw  43  is the same value of the leading edge draw  41 . Also, each of the current draws  41  and  43  have a duration (“d”)  45  when the value is above “½ I”  39 .  
           [0010]    A common technique to alleviate noise is adding additional power to the grid. This power is added upon sensing a voltage drop due to noise. However, such techniques only respond to noise at a much lower frequency than clock noise and also respond only to a certain threshold of noise. Consequently, a need exists for a technique that generates a response to clock noise at a synchronized frequency with the clock noise itself.  
         SUMMARY OF INVENTION  
         [0011]    In some aspects, the invention relates to a method for reducing noise of a clock signal for a latch-based circuit, comprising: storing a charge upon receipt of a first signal; and dumping the charge onto a system power grid upon receipt of a second signal, wherein storing the charge and dumping the charge are synchronized with the operation of at least one latch.  
           [0012]    In another aspect, the invention relates to a method for reducing noise of a clock signal for a latch-based circuit, comprising: step of storing a charge upon receipt of a first signal; step of dumping the charge onto a system power grid upon receipt of a second signal; and step of synchronizing storing the charge and dumping the charge with the operation of at least one latch.  
           [0013]    Other aspects and advantages of the invention will be apparent from the following description and the appended claims. 
       
    
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0014]    [0014]FIG. 1 shows a graph of an ideal clock signal.  
         [0015]    [0015]FIG. 2 shows a block diagram of a prior art embodiment of a clocking circuit for a latch.  
         [0016]    [0016]FIG. 3 shows a digital logic schematic of a prior art embodiment of a clocking circuit for a latch.  
         [0017]    [0017]FIG. 4 shows a graph of current draw during a clock cycle period of a latch based circuit.  
         [0018]    [0018]FIG. 5 shows a block diagram of a block diagram of one embodiment of the present invention.  
         [0019]    [0019]FIG. 6 shows a digital logic schematic of one embodiment of the present invention.  
         [0020]    [0020]FIG. 7 a  shows an equivalent circuit of a portion of the digital logic schematic shown in FIG. 6 during a charge phase.  
         [0021]    [0021]FIG. 7 b  shows an equivalent circuit of a portion of the digital logic schematic shown in FIG. 6 during a discharge phase.  
         [0022]    [0022]FIG. 8 shows a digital logic schematic of an alternative embodiment of the present invention.  
         [0023]    [0023]FIG. 9 shows a digital logic schematic of an alternative embodiment of the present invention.  
         [0024]    [0024]FIG. 10 shows a digital logic schematic of an alternative embodiment of the present invention.  
         [0025]    [0025]FIG. 11 shows a graph of current draw during a clock cycle period of the embodiments of the present invention shown in FIGS.  6 - 10 . 
     
    
     DETAILED DESCRIPTION  
       [0026]    Exemplary embodiments of the invention will be described with reference to the accompanying drawings. Like items in the drawings are shown with the same reference numbers.  
         [0027]    [0027]FIG. 5 shows a block diagram of a local clock signal distribution system (similar to that shown in FIG. 2) with a clock noise reduction circuit  48  added in accordance with one embodiment of the present invention. The clock signal  30   a  is input to a clock header  32  which serves to buffer the clock signal. From the header  32 , the clock signal  30   b  is input to a latch  34  where it serves to trigger the device. In this embodiment of the present invention, the initial clock signal  30   a  is split before the signal  30   a  is input into the header  32 . The parallel split of the signal  30   a  is input into a clock noise reduction circuit  48 . Upon sensing the rising edge of the clock signal  30   a,  the clock noise reduction circuit  48  will dump charge  50  onto the power grid of the system. The dumped charge  50  will alleviate the current noise spike associated with the clock cycle.  
         [0028]    [0028]FIG. 6 shows a logic schematic of a clock noise reduction circuit  48  in accordance with one embodiment of the present invention. Specifically, FIG. 6 shows an embodiment of a clock noise reduction circuit that is triggered on the rising edge of the clock signal. Once inside the noise reduction circuit  48 , the clock signal  30   a  is split into two separate branches. The first branch is directly input into a NAND gate  51 . The other branch is input into a first inverter  50   a  that simply inverts the signal value. Next the signal is input to a second inverter  50   b  which inverts the signal back to its original value. Finally, the signal is input into a third inverter  50   c  which once again inverts the signal. The output of the third inverter  50   c  is then input into the second input of the NAND gate  51 .  
         [0029]    The output of the NAND gate  51  is input into to a fourth inverter  53   a.  This inverter  53   a  inverts the signal value. The signal  52  (hereafter referred to as “charge signal”) is then split off into two branches. One branch of the charge signal  52  is input into a fifth inverter  53   b  which once again inverts the signal. The output of the fifth inverter  53   b  (hereafter referred to as “dump signal”) is then input, along with the charge signal  52 , into three circuit control transistors: a charge control transistor  56 ; a dump control transistor  58 ; and a connecting transistor  60 . It is important to note that the charge signal  52  and the dump signal  54  will have opposite values because the charge signal passes through the fifth inverter  53   b.    
         [0030]    The charge control transistor  56  connects the system power supply (Vdd) with the system ground (Vss) through an charge capacitor  62   a.  The charge capacitor  62   a  is located between the charge control transistor  56  and Vss. The transistor  56  is controlled (i.e. switched on and off) with the charge signal  52 . The transistor  56  is a “P-type” transistor which means that the transistor is “on” (allows current to pass) when the charge signal  52  is low. Conversely, the transistor  56  is “off” (does not allow current to pass) when the charge signal  52  is high.  
         [0031]    The dump control transistor  58  also connects the system power supply (Vdd) with the system ground (Vss) through a dump capacitor  62   b.  The dump capacitor  62   b  is located between the dump control transistor  58  and Vdd. The transistor  58  is controlled (i.e. switched on and off) with the dump signal  54 . The transistor  58  is an “N-type” transistor which means that the transistor is “on” (allows current to pass) when the dump signal  54  is high. Conversely, the transistor  58  is “off” (does not allow current to pass) when the dump signal  54  is low.  
         [0032]    Finally, the connecting transistor  60  connects both sides of the circuit. Specifically, the connecting transistor  60  connects the sides between the control transistors  56 ,  58  and the respective capacitors  62   a,    62   b.  The connecting transistor  60  is a “P-type” transistor which means that the transistor is “on” (allows current to pass) when the dump signal  54  is low. Conversely, the transistor  60  is “off” (does not allow current to pass) when the dump signal  54  is high.  
         [0033]    In normal operation, the control circuit has two phases of operation: a charge phase and a dump phase. In each phase, the circuit is activated by an “active low” signal. The means that the respective control signal (charge  52  or dump  54 ) initiates its respective phase when it is low rather than high.  
         [0034]    Specifically, during the charge phase, the charge signal  52  will be low and the dump signal  54  will be high. As a result, the charge control transistor  56  and the dump control transistor  58  are both “on” while the connecting transistor  60  is “off”. This allows both capacitors  62   a,    62   b  to charge in preparation for the dump phase. During the dump phase, the charge signal  52  will be high and the dump signal  54  will be low. As a result, the charge control transistor  56  and the dump control transistor  58  are both “off” while the connecting transistor  60  is “on”. This allows both capacitors  62   a,    62   b  to dump their charge on the power grid and consequently reduce the peak current draw.  
         [0035]    In comparing FIG. 6 with FIG. 3, it is important to note that the clock header  32  and latch  34  are synchronized with the clock noise reduction circuit  48 . The header  32  and latch  34  have a three separate layers of inverters  38   a,    38   b,    38   c,    38   d  along with the NAND gate  36 , while the clock noise reduction circuit  48  has a total of six inverters  50   a - c,    53   a - c  and a NAND gate  51 . The components of FIG. 6 are sized such that the transistors  56 ,  58 , and  60  are switched at the same time as the transistors  40   a  and  40   b  of FIG. 3. This causes the charge dumping to happen when data_out is being first driven by data_in in FIG. 3.  
         [0036]    [0036]FIGS. 7 a  and  7   b  show the equivalent circuits of a portion of the digital logic schematic shown in FIGS.  6  during a charge phase and discharge phase respectively. In each figure, the “off” transistors have been deleted while the “on” transistors have been replaced by a standard circuit connection. Specifically, FIG. 7 a  shows an equivalent circuit during the charge phase. It shows the two capacitors  62   a  and  62   b  connected in parallel between Vdd and Vss. FIG. 7 b  shows an equivalent circuit during the dump phase. It shows the two capacitors  62   a  and  62   b  connected in series between Vdd and Vss.  
         [0037]    When the capacitors  62   a  and  62   b  are in parallel during the charge phase, the each store a charge value “Q”, where Q=(Capacitance Value “C”)×Vdd. Consequently, the total charge stored by the circuit is 2 Q. When the capacitors  62   a  and  62   b  are in series during the dump phase, each capacitor  62   a  and  62   b  will have a voltage equal to Vdd/2 across it. Consequently, each capacitor will store only Q/2 for a total stored charge of Q by the circuit. The excess charge will be dumped onto the power grid.  
         [0038]    The circuit  48  shown in FIG. 6 triggers the dump phase on the rising edge of the clock signal  30   a.  However, the circuit could easily be arranged to trigger the dump phase on the falling edge of the clock signal  30   a.  FIG. 8 shows a logic schematic of a clock noise reduction circuit  63  in accordance with one embodiment of a falling edge triggered circuit. The noise reduction circuit  63  is similar to the rising edge triggered circuit  48  shown in FIG. 6 in that is has the same configuration of the clock signal  30   a  splitting into two separate branches once inside the circuit  63 . However, both branches are input into a NOR gate  55 . The first branch is input directly into the gate  55  with the CLK signal  30   a.  The second branch inputs into the gate  55  after passing the CLK signal  30   a  through three sequential inverters  50   a,    50   b,    50   c.    
         [0039]    The output of the NOR gate  55  is passed through a fourth inverter  57   a  and a fifth inverter  57   b.  The signal  52  (hereafter referred to as “charge signal”) is then split off into two branches. One branch of the charge signal  52  is input into a sixth inverter  57   c  which once again inverts the signal. The output of the sixth inverter  57   c  (hereafter referred to as “dump signal”) is then input, along with the charge signal  52 , into three circuit control transistors: a charge control transistor  56 ; a dump control transistor  58 ; and a connecting transistor  60 . Each is arranged in a similar configuration with respect to Vdd, Vss, and capacitors  62   a,    62   b,  as the rising edge circuit  48  of FIG. 6. It is important to note that the charge signal  52  and the dump signal  54  will have opposite values because the charge signal passes through the sixth inverter  57   c.    
         [0040]    The circuit  63  will perform in a similar manner as the circuit  48  shown and described in FIGS. 6, 7 a,  and  7   b.  However, the primarily difference in the performance of the circuits shown in FIG. 6 and FIG. 8 is the dump signal  54  and the charge signal  52 . As discussed previously, the dump signal for the circuit shown in FIG. 6 goes “low” during the rising edge of the CLK signal  30   a  and therefore initiates the dump phase on the rising edge. In contrast, the dump signal for the circuit shown in FIG. 8 goes “low” during the falling edge of the CLK signal  30   a  and therefore initiates the dump phase on the falling edge. As previously discussed, in each circuit the respective charge signals  52  are the inverse of their respective dump signals  54 . As such, the charge phases are initiated to dump on one edge of the clock signal and recharge a short time later. The phase will not do anything during the other clock transition. The other aspects of the performance of both types of circuits are essentially the same.  
         [0041]    [0041]FIG. 9 shows a logic schematic of a clock noise reduction circuit  69  in accordance with alternative embodiment of a rising edge triggered circuit. The noise reduction circuit  69  will have identical performance to the rising edge triggered circuit  48  shown in FIG. 6. The noise reduction circuit  69  is similar to the rising edge triggered circuit  48  shown in FIG. 6 in that is has the same configuration of the clock signal  30   a  splitting into two separate branches once inside the circuit  69 . However, both branches are input into a NOR gate  59 . The first branch inputs into the gate  59  after passing the CLK signal  30   a  through four sequential inverters  50   a,    50   b,    50   c,  and  50   d.  The second branch passes the CLK signal  30   a  through a fifth inverter  50   e  before being input into the gate  59 .  
         [0042]    The output of the NOR gate  59  is split off into two branches. One branch of the output  52  (hereafter referred to as “charge signal”) is input into a sixth inverter  61  which once again inverts the signal. The output of the sixth inverter  61  (hereafter referred to as “dump signal”) is then input, along with the charge signal  52 , into three circuit control transistors: a charge control transistor  56 ; a dump control transistor  58 ; and a connecting transistor  60 . Each is arranged in a similar configuration with respect to Vdd, Vss, and capacitors  62   a,    62   b,  as the rising edge circuit  48  of FIG. 6. It is important to note that the charge signal  52  and the dump signal  54  will have opposite values because the charge signal passes through the sixth inverter  57   c.    
         [0043]    [0043]FIG. 10 shows a logic schematic of a clock noise reduction circuit  71  in accordance with alternative embodiment of a falling edge triggered circuit. The noise reduction circuit  71  will have identical performance to the falling edge triggered circuit  63  shown in FIG. 8. The noise reduction circuit  71  is similar to the falling edge triggered circuit  63  shown in FIG. 8 in that is has the same configuration of the clock signal  30   a  splitting into two separate branches once inside the circuit  71 . However, both branches are input into a NAND gate  73 . The first branch inputs into the gate  59  after passing the CLK signal  30   a  through four sequential inverters  50   a,    50   b,    50   c,  and  50   d.  The second branch passes the CLK signal  30   a  through a fifth inverter  50   e  before being input into the gate  59 .  
         [0044]    The output of the NAND gate  51  is input into to a sixth inverter  53   a.  This inverter  53   a  inverts the signal value. The signal  52  (hereafter referred to as “charge signal”) is then split off into two branches. One branch of the charge signal  52  is input into a seventh inverter  53   b  which once again inverts the signal. The output of the seventh inverter  53   b  (hereafter referred to as “dump signal”) is then input, along with the charge signal  52 , into three circuit control transistors: a charge control transistor  56 ; a dump control transistor  58 ; and a connecting transistor  60 . Each is arranged in a similar configuration with respect to Vdd, Vss, and capacitors  62   a,    62   b,  as the rising edge circuit  48  of FIG. 6. It is important to note that the charge signal  52  and the dump signal  54  will have opposite values because the charge signal passes through the fifth inverter  53   b    
         [0045]    [0045]FIG. 11 shows a graph of current draw during a clock cycle period of the rising edge and falling edge noise reduction circuits as shown in FIGS.  6 - 10 . In both circuits, the results in reducing the current draw during the clock signal switching are similar. Specifically, the graph of FIG. 11 is set up on the same scale as the graph of the prior art performance shown in FIG. 4. The value “I”  35  represents the full value of a current draw. The value “¾ I”  37  represents 75% of the full value while the value “½ I”  39  represents 50% of the full value. The first current draw of the graph  70  represents the draw that results from the leading edge of a clock cycle (at clock cycle=0). The second current draw  72  represents the draw that results from the falling edge of the clock cycle (at clock cycle=t/2). As shown, the leading edge draw  70  and the trailing edge draw  72  are both at about 50% (½ I)  39  of the full current draw. This represents a substantial improvement in noise reduction by reducing the peak current draw. Each current draw  70 ,  72  has a duration (“2 d”)  74  that is approximately twice as long as the corresponding duration (“d”) of the prior art current draws  41 ,  43  shown in FIG. 4.  
         [0046]    All of the described circuits produce a pulse that controls the switching of the capacitors (through the NAND or NOR gates and the inverters on the other input). The pulse causes the capacitors to go into series when the latches are switching and the extra charge could be used. The pulse goes away after the latches have switched causing the capacitors to go back to parallel and subsequently pull charge back into the capacitors. The net result is a longer current spike but with a smaller magnitude and consequently, less noise.  
         [0047]    While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims.