Abstract:
According to some embodiments, a charge pump includes a first transistor to steer an amount of current to a second transistor coupled to the first transistor in a first folded cascode arrangement and to a current mirror to sink substantially the amount of current from a load, and a third transistor to steer the amount of current to a fourth transistor coupled to the third transistor in a second folded cascode arrangement to source substantially the amount of current to the load.

Description:
BACKGROUND  
         [0001]    Charge pumps are used to source current to or sink current from a load in response to control signals. Typically, these control signals consist of an UP signal and a DOWN signal. Current is sourced to the load in a case that the UP signal is active and the DOWN signal is inactive, and current is sunk from the load in a case that the UP signal is inactive and the DOWN signal is active. Ideally, no current flows through the load if both control signals are in the same state.  
           [0002]    In a non-ideal charge pump, some current flows to or from the load if both control signals are in the same state. This current is known as leakage current. Leakage current may be reduced for a particular charge pump by tri-stating the output and/or increasing the output impedance of the charge pump.  
           [0003]    A non-ideal charge pump also introduces delays into the system in which it is implemented. For example, many charge pumps employ switched current mirror structures. When a current is mirrored, the speed by which a current is switched through the mirror is limited by the device transit frequency of the transistors comprising the mirror. These delays may be significant in a case that the device transit frequency is similar to the phase detector comparison rate, which is the rate at which the charge pump control signals are updated. Hence, conventional charge pumps using switched current mirrors provide current matching at the expense of speed.  
           [0004]    [0004]FIG. 1 illustrates a conventional differential charge pump that does not employ a current mirror. Charge pump  1  includes p-channel metal-oxide semiconductor (PMOS) transistor  2 . Transistor  2  receives voltage signal V CMFB  from a common-mode feedback amplifier and generates a current which results in a stable common-mode voltage at the output of charge pump  1 .  
           [0005]    A drain of transistor  2  is coupled to sources of PMOS transistor  3  and PMOS transistor  4 . Drains of transistors  3  and  4  are respectively coupled to drains of n-channel metal-oxide semiconductor (NMOS) transistor  5  and NMOS transistor  6 , and source terminals of transistors  5  and  6  are coupled to one another and to current source I 1 . These elements operate to generate differential output signal component OUT_N based on the differential charge pump control signals UP (composed of component signals UP and UPB) and DOWN (composed of DN and DNB). Charge pump  1  uses a second set of the above-described elements to generate differential output signal component OUT_P. However, the components of the UP and DOWN differential control signals are applied to the second set of elements in a different arrangement.  
           [0006]    Charge pump  1  therefore uses PMOS current switches stacked on NMOS current switches to steer the UP and DOWN signals to a load. These current switches require high output impedance because they are directly coupled to the output of charge pump  1 . This direct coupling also presents problems with signal feedthrough. Additionally, since the current switches are both PMOS and NMOS, charge pump  1  may require level shifting of the differential control signals. Level shifting may be required to allow for enough voltage dynamic range at the output of charge pump  1 . Yet another drawback of charge pump  1  is its use of local feedback, which complicates its design. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1 is a diagram illustrating a conventional charge pump.  
         [0008]    [0008]FIG. 2 is a diagram of a charge pump according to some embodiments.  
         [0009]    [0009]FIG. 3 is a diagram of a charge pump according to some embodiments.  
         [0010]    [0010]FIG. 4 is a diagram of a differential-output charge pump according to some embodiments.  
         [0011]    [0011]FIG. 5 is a block diagram of a differential-output charge pump according to some embodiments.  
         [0012]    [0012]FIG. 6 is a block diagram of a system according to some embodiments.  
     
    
     DETAILED DESCRIPTION  
       [0013]    [0013]FIG. 2 illustrates charge pump  10  according to some embodiments. As described with respect to FIG. 1, the UP and DOWN control signals used to control charge pump  10  are differential control signals, each composed of two components (UP &amp; UPB, DN &amp; DNB) which together define a state of a respective differential control signal. Charge pump  10  steers a current I so as to source or sink current I at output node OUT based on the control signals. Although charge pump  10  includes only one output, charge pump  10  may be modified as described below to output a differential signal.  
         [0014]    Current sources I M , I CP , I U  and I D  in FIG. 2 each generate a current equal to I. Charge pump  10  also includes current switches comprising NMOS transistors m 1  through m 4 . Each of transistors m 1  through m 4  receives a respective component of the differential control signals. A source of transistor m 1  is coupled to a source of transistor m 2  and to current source I U . Also, a source of transistor m 3  is coupled to a source of transistor m 4  and to current source I D .  
         [0015]    A drain of transistor m 1  is coupled to a source of PMOS transistor m 5  in a folded cascode arrangement. A drain of transistor m 5  is in turn coupled to an output of NMOS current mirror  15  and to output node OUT. A drain of transistor m 3  is also coupled in a folded cascode arrangement to a source of PMOS transistor m 6 , and a drain of transistor m 6  is coupled to an input of current mirror  15 . Current mirror  15  generates at its output any current that is present at its input.  
         [0016]    To explain the operation of charge pump  10 , it will be assumed that the UP differential control signal is inactive and the DOWN differential control signal is active. Corresponding values of component signals UP, UP_B, DN and DN_B are low, high, high and low, respectively. Since transistors m 1  through m 4  are NMOS-type, these values cause transistors m 1  and m 4  to conduct current and cause transistors m 2  and m 3  to block current flow.  
         [0017]    As mentioned above, I CP =I=I U . Current I therefore flows through conducting transistor m 1 , and no net current flows through transistor m 5 . Current I from current source I M  does not flow through non-conducting transistor m 3 , but rather flows through transistor m 6  and to the input of current mirror  15 . Current I is mirrored in amplitude and direction at the output of current mirror  15 . Since no current flows through transistor m 5 , the mirrored current I sinks from output node OUT.  
         [0018]    In a case that that the UP differential control signal is active and the DOWN differential control signal is inactive, values of component signals UP, UP_B, DN and DN_B are high, low, low and high, respectively. These values cause transistors m 2  and m 3  to conduct current and cause transistors m 1  and m 4  to block current flow. I CP =I flows through transistor m 5  since no current flows through transistor m 1 . Current I flows through transistor m 5  because I M =I D =I, resulting in no net current flow through transistor m 6 . Consequently, no current flows at the input or the output of current mirror  15 . The current I flowing through transistor m 5  therefore flows entirely to output node OUT.  
         [0019]    [0019]FIG. 3 illustrates charge pump  20  according to some embodiments. Charge pump  20  also steers a current I so as to source or sink current I at output node OUT based on components of differential charge pump control signals. Charge pump  20  differs from charge pump  10  in that current switches m 11  through m 14  are PMOS transistors and current mirror  25  is also comprised of PMOS transistors. Again, current sources I M , I CP , I U  and I D  each generate a current equal to I.  
         [0020]    A source of transistor m 11  is coupled to a source of transistor m 12  and to current source I D , while a source of transistor m 13  is coupled to a source of transistor m 14  and to current source I U . A drain of transistor m 11  is coupled to a source NMOS transistor m 15  in a folded cascode arrangement, and a drain of transistor m 15  is in turn coupled to an output of current mirror  25  and to output node OUT. A drain of transistor m 13  is also coupled in a folded cascode arrangement to a source of NMOS transistor m 16 , and a drain of transistor m 16  is coupled to an input of current mirror  25 .  
         [0021]    One example of operation of charge pump  20  will be described below with respect to an inactive UP differential control signal and an active DOWN differential control signal. Corresponding values of component signals UP, UP_B, DN and DN_B are low, high, high and low. Since transistors m 11  through m 14  are PMOS-type, these values cause transistors m 12  and m 13  to conduct current and cause transistors m 11  and m 14  to block current flow.  
         [0022]    Current I therefore flows through transistor m 13  and no current flows through transistor m 16 . Accordingly, no net current flows at the input of output of current mirror  25 . Current I CP =I flows through transistor m 15  because no current flows through transistor m 11 . Since no current flows at the output of current mirror  25 , current I that flows through transistor m 15  is sunk from output node OUT. Charge pump  10  and charge pump  20  therefore both sink current I from an output node in response to an inactive UP differential control signal and an active DOWN differential control signal.  
         [0023]    Charge pump  10  and charge pump  20  therefore use a current mirror to either sink or source current, but not to sink and source current. Such an arrangement may offer low voltage headroom and reasonably high-speed operation.  
         [0024]    [0024]FIG. 4 illustrates fully-differential charge pump  30  according to some embodiments. As a fully-differential charge pump, charge pump  30  receives differential control signals UP and DOWN and generates a differential output signal based thereon. As shown, charge pump  30  utilizes charge pump  10  to generate the OUT_P component of the differential output signal.  
         [0025]    Charge pump  30  utilizes charge pump  11  to generate the OUT_N component of the differential output signal. Charge pump  11  is identical to charge pump  10  except in that a drain of the NMOS transistor receiving the DN_B component is coupled to an output of the current mirror rather than to an input of the current mirror. Similarly, a drain of the NMOS transistor receiving the UP_B component is coupled to the input of the current mirror rather than to its output. These differences result in an OUT_N component that is opposite to the OUT_P component generated by charge pump  10  in response to identical UP and DOWN control signals. A more general structure of a fully-differential charge pump is illustrated in FIG. 5. Charge pump  40  includes charge pumps  45  and  46 , each of which may be implemented by charge pump  10 . As shown, a particular set of control signals UP, UP_B, DN and DN_B is applied to the inputs of charge pump  45  as described above with respect to charge pump  10 . The control signals are applied differently to charge pump  46 , with the UP signal applied to the DN input (transistor m 4 ), the UP_B signal applied to the DN_B input (transistor m 3 ), the DN signal applied to the UP input (transistor m 2 ) and the DN_B signal applied to the UP_B input (transistor m 1 ). Buffer  50  buffers and/or provides required impedance levels for output signals OUT_P and OUT_N.  
         [0026]    Charge pumps  45  and  46  differ from charge pump  10  by the inclusion of current source I CMFB . Current sources I CMFB  and I CP  together generate a current equal to I by virtue of voltage signal V CMFB . More specifically, current source I CMFB  receives voltage signal V CMFB  from a common-mode feedback amplifier (not shown). The common-mode feedback amplifier receives output signals OUT_P and OUT_N from charge pumps  45  and  46 , detects a common-mode output voltage of charge pump  40  based on the received output signals, receives a common-mode reference voltage, and generates output voltage signal V CMFB  based on the detected common-mode voltage and the reference voltage.  
         [0027]    One advantage of a fully-differential charge pump according to some embodiments are the similar speeds by which current is sunk from or sourced to a load. Moreover, a fully-differential charge pump according to some embodiments may only require matching of differential source currents and matching of differential sink currents, rather than matching of source currents to sink currents.  
         [0028]    [0028]FIG. 6 is a block diagram of a system according to some embodiments. System  100  includes transceiver chip  110  for receiving and transmitting data. Transceiver chip  110  includes charge pump  10  within a Clock and Data Recovery (CDR) circuit. The CDR circuit is used to extract a clock to retime the data received by transceiver chip  110 .  
         [0029]    Such a signal may be received from optical interface  120 . Optical interface  120  is coupled to transceiver  110 , receives electrical signals from transceiver  110 , and transmits optical signals based on the received electrical signals. Optical interface  120  also receives optical signals and transmits electrical signals to transceiver  110  based on the received optical signals.  
         [0030]    Backplane interface  130  is also coupled to transceiver  110 . Electrical signals are transmitted between transceiver  110  and a backplane (not shown) through backplane interface  130 . System  100  may be embodied in a communications module. The communications module may in turn be an element of a line card used to transmit and receive data to and from an optical medium.  
         [0031]    Charge pump  10  may also be embodied in a Phase-Lock Loop or other circuit requiring one or more of high output impedance, high speed of operation, high output dynamic range, low leakage current and decreased device matching requirements such as those relating to static phase error in certain clock and data recovery loops. However, embodiments need not possess all or any of these characteristics.  
         [0032]    The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known current sources, switches and current mirrors. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.