Abstract:
The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission and, more particularly, to an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of the cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies. 
     2. Description of the Prior Art 
     FIG. 1 is a schematic diagram showing a data transmission system. In FIG. 1, the data transmission system comprises two portions: a transceiver T X    10  and a receiver R X    12 , where a cable  14  is interposed between the transceiver T X    10  and the receiver R X    12  for communication. In general, a cable has a characteristic impedance Z Φ . If the input impedance Z in , at the input terminal of the receiver R X    12  does not match the characteristic impedance Z 101  of the cable  14 , signal reflection may occur which may distort signals. Therefore, the input impedance Z in  of the receiver R X    12  must be properly adjusted to match the characteristic impedance Z 101  of the cable  14 , so as to reduce signal reflection and prevent signals from distortion. 
     FIG. 2A to FIG. 2D are schematic diagrams showing various conventional impedance matching circuits in accordance with the prior art. In FIG. 2A, Z 101  denotes the characteristic impedance of a cable  202 , Z in  denotes the input impedance  206  viewed at the input terminal of the receiver R X    208 , and R 101  denotes a stable resistor  204  interposed between the input terminal of the receiver R X    208  and a voltage source V dd . Generally, the input impedance Z in    206  at the input terminal of the receiver R X    208  is relatively large. More particularly, the resistance of the input impedance Z in    206  is much larger than that of the stable resistor R 101    204 . Hence, the parallel connection of the stable resistor R 101    204  and the input impedance Z in    206  results in a resistance value approximately equal to that of the stable resistor R 101    204 . When the resistance of the stable resistor R 101    204  is determined to be equal to that of the characteristic impedance Z 101  of the cable  202 , impedance matching can be achieved. 
     In FIG. 2B, Z 101  denotes the characteristic impedance of the cable  212 , Z in  denotes the input impedance  216  viewed at the input terminal of the receiver R X    218 , and R 101  denotes the stable resistor  214  interposed between the input terminal of the receiver R X    218  and the ground. Generally, the input impedance Z in    216  at the input terminal of the receiver R X    218  is relatively large. More particularly, the resistance of the input impedance Z in    216  is much larger than that of the stable resistor R 101    214 . Hence, the parallel connection of the stable resistor R 101    214  and the input impedance Z in    216  results in a resistance value approximately equal to that of the stable resistor R 101    214 . When the resistance of the stable resistor R 101    204  is determined to be equal to that of the characteristic impedance Z 101  of the cable  212 , impedance matching can be achieved. 
     In FIG. 2C, Z 101  denotes the characteristic impedance of a cable  222 , and Z in  denotes the input impedance  226  viewed at the input terminal of the receiver R X    228 . The input terminal of the receiver R X    228  is connected to the drain of a p-channel MOSFET (abbreviated as “PMOS” hereinafter)  224 . The source of the PMOS  224  is connected to a voltage source V dd , while the gate of the PMOS  224  is connected to the control terminal of a feedback control circuit  225 . A precise resistor R ext    227  is interposed between the signal terminal of the feedback control circuit  225  and the voltage source V dd . R eff  denotes the equivalent resistance viewed at the drain of the PMOS  224 , therefore the resistance of the precise resistor R ext    227  is expressed as R ext =α·R eff , where the value of α is controlled by the feedback control circuit  225 . Generally, the input impedance Z in    226  at the input terminal of the receiver R X    228  is relatively large. More particularly, the resistance of the input impedance Z in    226  is much larger than the equivalent resistance R eff  viewed at the drain of the PMOS  224 . Hence, the parallel connection of the equivalent resistance R eff  and the input impedance Z in    226  results in a resistance value approximately equal to the equivalent resistance R eff  When the equivalent resistance R eff  is determined to be equal to that of the characteristic impedance Z 101  of the cable  222 , impedance matching can be achieved. 
     In FIG. 2D, Z 101  denotes the characteristic impedance of a cable  232 , and Z in  denotes the input impedance  236  viewed at the input terminal of the receiver R X    238 . The input terminal of the receiver R X    238  is connected to the drain of an n-channel MOSFET (abbreviated as “NMOS” hereinafter)  234 . The source of the NMOS  234  is connected to the ground, while the gate of the NMOS  234  is connected to the control terminal of a feedback control circuit  235 . A precise resistor R ext    237  is interposed between the signal terminal of the feedback control circuit  235  and the ground. R eff  denotes the equivalent resistance viewed at the drain of the NMOS  234 , therefore the resistance of the precise resistor R ext    237  is expressed as R ext =β·R eff  where the value of β is controlled by the feedback control circuit  235 . Generally, the input impedance Z in    236  at the input terminal of the receiver R X    238  is relatively large. More particularly, the resistance of the input impedance Z in    236  is much larger than the equivalent resistance R eff  viewed at the drain of the NMOS  234 . Hence, the parallel connection of the equivalent resistance R eff  and the input impedance Z in    236  results in a resistance value approximately equal to the equivalent resistance R eff . When the equivalent resistance R eff  is determined to be equal to that of the characteristic impedance Z 101  of the cable  232 , impedance matching can be achieved. 
     From FIG. 2A to FIG. 2D, the stable resistor R 101  and the precise resistor R ext  have to change as the characteristic impedance Z 101  of the cable varies. When there are a considerable number of cables, the number of the stable resistors increases as the number of cables increases, resulting in increased fabrication cost and complexity of the impedance matching circuit. 
     FIG. 3 is a schematic diagram showing another conventional impedance matching circuit in the prior art. In FIG. 3, R cur  denotes a built-in/external bias resistor  302  for providing the transistor mib  304  with the current I bias . A current mirror circuit is composed of the transistor mdrz  306 , the transistor mb7  308 , the transistor mdlz  310 , the transistor mdri  312 , the transistor ma7  314 , the transistor mdli  316  and the transistor mib  304 . Since all the gates of the above transistors are connected together, the current in the current mirror is proportional to the bias current I bias  according to the W/L ratio of the transistors. 
     The gate voltage V ref  of both the transistor muri  318  and the transistor mulz  320  is a reference voltage, the potential level of which is ΔV lower than that of the voltage source V dd . The transistor muli  322 , the transistor muri  318 , the transistor mulz  320  and the transistor murz  324  are used for level-shifting, that is, making the gate voltage V ref  of the transistors decrease to a voltage value approximately equal to the threshold voltage and then outputting an output voltage (i.e., as a source follower). 
     An operational amplifier with an output voltage V oa  is composed of the transistor mal  326 , the transistor ma2  328 , the transistor ma3  330 , the transistor ma4  332 , and the transistor ma5  334 . The gate voltage V ref  is level-shifted by the transistor muri  318  and then applied to the gate of the transistor ma2  328  through the node ka2. For the output voltage V oa , a negative feedback circuit (where the capacitor mca  340  serves as a frequency compensation capacitor for stabilizing the operational amplifier) is formed of the transistor mna2  336 , the transistor mna1  338 , the gate voltage V ref , and the node ka1. Hence, the voltage at the node ka1 is equal to that at the node ka2, where the former is a voltage obtained by level shifting the voltage V ext  and the latter is a voltage obtained by level shifting the voltage V ref  Therefore, the voltage V ext  is equal to voltage V ref . 
     Another operational amplifier with an output voltage V ob  is composed of the transistor mb1  342 , the transistor mb2  344 , the transistor mb3  346 , the transistor mb4  348 , and the transistor mb5  350 . The gate voltage V ref  is level-shifted by the transistor mulz  320  and then applied to the gate of the transistor mb2  344  through the node kb2. For the output voltage V ob , a negative feedback circuit (where the capacitor mcb  354  serves as a frequency compensation capacitor for stabilizing the operational amplifier) is formed of the transistor mz0  352 , the voltage V xx , the transistor murz  324 , and the node kb1. Hence, the voltage at the node kb1 is equal to that at the node kb2, where the former is a voltage obtained by level shifting the voltage V xx  and the latter is a voltage obtained by level shifting the voltage V ref . Therefore, the voltage V xx  is equal to voltage V ref . 
     The gate of the transistor mna2  336  is connected to the gate of the transistor mnb2  356 . Therefore, the current flowing through the transistor mna2  336  is equal to the current flowing through the transistor mnb2  356 , and the current flowing through the resistor R ext    358  is equal to the current flowing through the transistor mz0  352 , which means that the resistance value of the resistor R ext    358  is equal to the equivalent resistance of the transistor mz0  352 . 
     The circuit as shown in FIG. 3 is characterized in that V ext =V ref =V xx  and that the current flowing through the resistor R ext    358  is equal to the current flowing through the transistor mz0  352 . Therefore, the equivalent resistance of the transistor mz0  352  can be regarded equal to the resistance value of the resistor R ext    358 , even though it takes two operational amplifiers to meet the above conditions. 
     Let us assume that the width of the transistor mz0  352  is equal to W p , the width of the transistor mlp1  360  is equal to 10W p , the width of the transistor mlp2  362  is equal to W p , the width of the transistor mnb2  356  is equal to W s , the width of the transistor mnx  364  is equal to 11W s  and the gate of the transistor mnb2  356  is connected to the gate of the transistor mnx  364 . As a result, the current flowing through the transistor mnx  364  is 11 times the current flowing through the transistor mnb2  356 , and the current flowing through the transistor mlp1  360  is 10 times the current flowing through the transistor mz0  352 . In addition, the current flowing through the transistor mlp2  362  is equal to the current flowing through the transistor mz0  352  (because the gate of the transistor mlp1  360 , the gate of the transistor mlp2  362  and the gate of the transistor mz0  352  are connected). Therefore, the equivalent resistance viewed at the node datab towards the voltage source V dd  is one tenth of the equivalent resistance of the transistor mz0  352  and the equivalent resistance viewed towards the ground approaches infinity. Accordingly, the equivalent resistance at the node datab is equal to ({fraction (1/10)})*R ext //infinity=({fraction (1/10)})*R ext . (wherein the term “//” means parallel) 
     However, there are still some problems related to the prior art impedance matching circuit in that: (1) the resistance for impedance matching of the impedance matching circuit as well as the resistor R ext  should change when the characteristic impedance of the cable varies; (2) two operational amplifiers are required to complete a negative feedback circuit so that the fabrication cost as well as the complexity may increase; and (3) the resistance value for impedance matching of the impedance matching circuit can not be changed by simply changing the voltage V ref  of the impedance matching circuit. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is the primary object of the present invention to provide an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies. 
     In order to achieve the foregoing objects, the present invention provides an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission. The impedance matching circuit comprises: a first transistor, a second transistor, a resistor and a negative feedback control circuit. The first transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the first transistor is connected to a voltage supply, and the load terminal of the first transistor is connected to an input terminal of the receiver. The second transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the second transistor is connected to a voltage supply, and the control terminal of the second transistor is connected to the control terminal of the first transistor. One terminal of the resistor is connected to the load terminal of the second transistor, while the other terminal is connected to the ground. An inverting input terminal of the negative feedback control circuit receives an adjustable reference voltage, a non-inverting input terminal of the negative feedback control circuit is connected to the load terminal of the second transistor, and an output terminal of the negative feedback control circuit is connected to the control terminal of the second transistor. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage. 
     It is preferable that the negative feedback control circuit can be implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier. 
     It is preferable that the impedance matching circuit further comprises: a multiplexer. The multiplexer includes a select terminal and a signal output terminal, wherein the multiplexer receives a plurality of voltage signals having different magnitudes, selects one from the plurality of voltage signals according to a select signal received by the select terminal, and then outputs the voltage signal as the reference voltage into the inverting input terminal of the negative feedback control circuit. 
     It is preferable that the negative feedback control circuit further comprises a reference voltage generator for generating the voltage signals to be output to the multiplexer. 
     It is preferable that the first transistor is a p-channel MOSFET and the second transistor is a p-channel MOSFET. 
     In order to achieve the foregoing objects, the present invention provides an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission. The impedance matching circuit comprises: a first transistor, a second transistor, a resistor and a negative feedback control circuit. The first transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the first transistor is connected to an input terminal of the receiver, and the load terminal of the first transistor is connected to the ground. One terminal of the resistor is connected to a voltage source. The second transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the second transistor is connected to another terminal of the resistor, the control terminal of the second transistor is connected to the control terminal of the first transistor, and the load terminal of the second transistor is connected to the ground. An inverting input terminal of the negative feedback control circuit receives an adjustable reference voltage, a non-inverting input terminal of the negative feedback control circuit is connected to the power supply terminal of the second transistor, and an output terminal of the negative feedback control circuit is connected to the control terminal of the second transistor. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage. 
     It is preferable that the negative feedback control circuit can be implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier. 
     It is preferable that the impedance matching circuit further comprises: a multiplexer. The multiplexer includes a select terminal and a signal output terminal, wherein the multiplexer receives a plurality of voltage signals having different magnitudes, selects one from the plurality of voltage signals according to a select signal received by the select terminal, and then outputs the voltage signal as the reference voltage into the inverting input terminal of the negative feedback control circuit. 
     It is preferable that the negative feedback control circuit further comprises a reference voltage generator for generating the voltage signals to be output to the multiplexer. 
     It is preferable that the first transistor is an n-channel MOSFET and the second transistor is an n-channel MOSFET. 
     Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The objects, spirits and advantages of the preferred embodiments of the present invention will be readily understood by the accompanying drawings and detailed descriptions, wherein: 
     FIG. 1 is a schematic diagram showing a data transmission system; 
     FIG. 2A to FIG. 2D are schematic diagrams showing various conventional impedance matching circuits in accordance with the prior art; 
     FIG. 3 is a schematic diagram showing another conventional impedance matching circuit in the prior art; 
     FIG. 4 is a schematic diagram showing an impedance matching circuit in accordance with one embodiment of the present invention; and 
     FIG. 5 is a schematic diagram showing an impedance matching circuit in accordance with another embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention providing an impedance matching circuit can be exemplified by the preferred embodiments as described hereinafter. 
     Embodiment I 
     Please refer to FIG. 4, which is a schematic diagram showing an impedance matching circuit in accordance with one embodiment of the present invention. In FIG. 4, an impedance matching circuit  400  with adjustable resistance is used for facilitating impedance matching between the characteristic impedance of a cable  402  and the input impedance at the input terminal of a receiver  404  for data transmission. The impedance matching circuit  400  is described hereinafter. 
     The source of the p-channel MOSFET (abbreviated as “PMOS” hereinafter)  406  is connected to the voltage source V dd  and the drain of the PMOS  406  is connected to an input terminal of the receiver  404 . The source of the PMOS  408  is connected to the voltage source V dd  and the gate of the PMOS  408  is connected to the gate of the PMOS  406 . One terminal of the resistor R ext    410  is connected to the drain of the PMOS  408  and the other terminal of the resistor R ext    410  is connected to the ground. The inverting input terminal of the operational amplifier  412  receives a reference voltage V ref , the non-inverting input terminal of the operational amplifier  412  is connected to the drain of the PMOS  408 , and the output terminal of the operational amplifier  412  is connected to the gate of the PMOS  408 . The select terminal of the multiplexer  414  receives a select signal SEL, and the signal output terminal outputs the reference voltage V ref  to the inverting input terminal of the operational amplifier  412 . Moreover, The reference voltage generator  416  includes a plurality of voltage output terminals for outputting the reference voltage V ref  to the signal input terminal of the multiplexer  414 . 
     In FIG. 4, the reference voltage at the inverting input terminal of the operational amplifier  412  is expressed as V ref =α·V dd , where 0&lt;α≦1. A negative feedback circuit is formed of the PMOS  406 , the PMOS  408 , and the resistor R ext    410 . According to the virtual short circuit theory, we obtain V ref =α·V dd =V ext , where V ext  is the voltage across the drain of the PMOS  408  and the resistor R ext    410 . Assuming that the equivalent resistance viewed at the drain of the PMOS  408  is R eq , we obtain the voltage          V   ext     =         R   ext         R   ext     +     R   eq         ·       V   dd     .                              
     That is        α   =       R   ext         R   ext     +     R   eq                                
     and the equivalent resistance          R   eq     =         1   -   α     α     ·       R   ext     .                              
     Let us assume that the aspect ratio of the PMOS  406  is            (     W   L     )     P1     ,                          
     the aspect ratio of the PMOS  408  is            (     W   L     )     P2     ,                          
     and the ratio between          (     W   L     )     P1                          
     and          (     W   L     )     P2                          
     is x, then            (     W   L     )     P1     =     x   ·         (     W   L     )     P2     .                              
     Let us assume that R 101  denotes the equivalent resistance viewed at the drain of the PMOS  406 , where                R   Φ     =                1       μ   P     ·     C   ox     ·       (     W   L     )     P1     ·     (       V   sg1     -          V   tP            )                       R   eq     =                1       μ   P     ·     C   ox     ·       (     W   L     )     P2     ·     (       V   sg2     -          V   tP            )                       V   sg1     =                V   sg2                   ⇒     R   Φ       =                  1   x     ·     R   eq                     ⇒     R   Φ       =                    1   x     ·       1   -   α     α            R   ext                                    
     where, μ p  is the carrier mobility, C ox  is the electric capacitance per unit area at the gate, V sg1  and V sg2  are the voltage drops across the source and the gate, and |V tp | is the threshold voltage. 
     Therefore, when the input impedance Z in    418  at the input terminal of the receiver  404  is relatively large, the parallel connection of the equivalent resistance R 101  of the impedance matching circuit  400  and the input impedance Z in    418  results in a resistance value approximately equal to equivalent resistance R 101  of the impedance matching circuit  400 . When the resistance of equivalent resistance R 101  of the impedance matching circuit  400  is determined to be equal to that of the characteristic impedance Z 101  of the cable  402 , impedance matching can be achieved. 
     When the characteristic impedance Z 101  of the cable  402  varies, the multiplexer  414  of the impedance matching circuit  400  outputs a reference voltage V ref  with a different magnitude to the inverting input terminal of the operational amplifier  412 . As the V ref  at the inverting input terminal of the operational amplifier  412  is adjusted, the value of α as well as the value of R eq  is also adjusted. Accordingly, the value of the equivalent resistance R 101  is adjusted to match the varied characteristic impedance Z 101  of the cable  402 . Therefore, when the characteristic impedance Z 101  of the cable  402  varies, the multiplexer  414  selects a suitable reference voltage V ref  from the reference voltage generator  416  to change the equivalent resistance R 101  of the impedance matching circuit  400  such that the equivalent resistance R 101  is equal to the resistance value of the characteristic impedance Z 101  of the cable  402 . Therefore, impedance matching is achieved. 
     Embodiment II 
     FIG. 5 is a schematic diagram showing an impedance matching circuit in accordance with another embodiment of the present invention. In FIG. 5, an impedance matching circuit  500  with adjustable resistance is used for facilitating impedance matching between the characteristic impedance of a cable  502  and the input impedance at the input terminal of a receiver  504  for data transmission. The impedance matching circuit  500  is described hereinafter. 
     The source of the n-channel MOSFET (abbreviated as “NMOS” hereinafter)  506  is connected to the ground and the drain of the NMOS  506  is connected to an input terminal of the receiver  504 . The source of the NMOS  508  is connected to the ground and the gate of the NMOS  508  is connected to the gate of the NMOS  506 . One terminal of the resistor R ext    510  is connected to the drain of the NMOS  508  and the other terminal of the resistor R ext    510  is connected to the voltage source V dd . The inverting input terminal of the operational amplifier  512  receives a reference voltage V ref  the non-inverting input terminal of the operational amplifier  512  is connected to the drain of the NMOS  508 , and the output terminal of the operational amplifier  512  is connected to the gate of the NMOS  508 . The select terminal of the multiplexer  514  receives a select signal SEL, and the signal output terminal outputs the reference voltage V ref  to the inverting input terminal of the operational amplifier  512 . Moreover, The reference voltage generator  516  includes a plurality of voltage output terminals for outputting the reference voltage V ref  to the signal input terminal of the multiplexer  514 . 
     In FIG. 5, the reference voltage at the inverting input terminal of the operational amplifier  512  is expressed as V ref =β·V dd , where 0&lt;β≦1. A negative feedback circuit is formed of the NMOS  506 , the NMOS  508 , and the resistor R ext    510 . According to the virtual short circuit theory, we obtain V ref =β·V dd =V ext , where V ext  is the voltage across the drain of the NMOS  508  and the resistor R ext    510 . Assuming that the equivalent resistance viewed at the drain of the NMOS  508  is R eq . we obtain the voltage          V   ext     =         R   ext         R   ext     +     R   eq         ·       V   dd     .                              
     That is,        β   =       R   ext         R   ext     +     R   eq                                
     and the equivalent resistance          R   eq     =         1   -   β     β     ·       R   ext     .                              
     Let us assume that the aspect ratio of the NMOS  506  is            (     W   L     )     n1     ,                          
     the aspect ratio of the NMOS  508  is            (     W   L     )     n2     ,                          
     and the ratio between          (     W   L     )     n1                          
     and          (     W   L     )     n2                          
     is y, then            (     W   L     )     n1     =     y   ·         (     W   L     )     n2     .                              
     Let us assume that R 101  denotes the equivalent resistance viewed at the drain of the NMOS  506 , where                    R   Φ     =                1       μ   n     ·     C   ox     ·       (     W   L     )     n1     ·     (       V   gs1     -          V   tn            )                       R   eq     =                1       μ   n     ·     C   ox     ·       (     W   L     )     n2     ·     (       V   gs2     -          V   tn            )                       V   sg1     =                V   sg2                  
     ⇒     R   Φ       =           1   y     ·     R   eq            
     ⇒     R   Φ       =         1   y     ·       1   -   β     β            R   ext                                
     where, μ n  is the carrier mobility, C ox  is the electric capacitance per unit area at the gate, V gs1  and V gS2  are the voltage drops across the source and the gate, and |V in | is the threshold voltage. 
     Therefore, when the input impedance Z in    518  at the input terminal of the receiver  504  is relatively large, the parallel connection of the equivalent resistance R 101  of the impedance matching circuit  500  and the input impedance Z in    518  results in a resistance value approximately equal to equivalent resistance R 101  of the impedance matching circuit  500 . When the resistance of equivalent resistance R 101  of the impedance matching circuit  500  is determined to be equal to that of the characteristic impedance Z 101  of the cable  502 , impedance matching can be achieved. 
     When the characteristic impedance Z 101  of the cable  502  varies, the multiplexer  514  of the impedance matching circuit  500  outputs a reference voltage V ref  with a different magnitude to the inverting input terminal of the operational amplifier  512 . As the V ref  at the inverting input terminal of the operational amplifier  512  is adjusted, the value of β as well as the value of R eq  is also adjusted. Accordingly, the value of the equivalent resistance R 101  is adjusted to match the varied characteristic impedance Z 101  of the cable  502 . Therefore, when the characteristic impedance Z 101  of the cable  502  varies, the multiplexer  514  selects a suitable reference voltage V ref  from the reference voltage generator  516  to change the equivalent resistance R 101  of the impedance matching circuit  500  such that the equivalent resistance R 101  is equal to the resistance value of the characteristic impedance Z 101  of the cable  502 . Therefore, impedance matching is achieved. 
     According to the above discussion, the present invention discloses an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies. Therefore, the present invention has been examined to be progressive, advantageous and applicable to the industry. 
     Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to persons skilled in the art. This invention is, therefore, to be limited only as indicated by the scope of the appended claims.