Abstract:
A method for manufacturing a polysilicon layer includes providing a substrate, forming an amorphous silicon layer on an entire surface of the substrate, defining an active area on the amorphous silicon layer, doping the amorphous silicon layer with a semiconductor material, depositing a metal layer on the amorphous silicon layer; and applying a voltage to the amorphous silicon layer to form a polysilicon layer using a joule heat that is generated from the applied voltage.

Description:
This application claims the benefit of Korean Patent Application No. 1999-11740, filed on Apr. 3, 1999, which is hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a method for manufacturing polysilicon rapidly from amorphous silicon and more specifically, the present invention relates to a method for forming crystallized polysilicon channels in thin film transistors. 
     2. Discussion of the Related Arts 
     Thin film transistors (TFTs) are vital for high performance liquid crystal displays (LCDs), which are one of the most important components of a laptop computer. TFTs are also applied in other two-dimensional (2D) displays, sensors, and electronics. Currently, most large arrays of TFTs are formed on amorphous materials, such as a hydrogen amorphous silicon (a-Si:H). However, a-Si:H based TFTs have drawbacks such as low mobility and high photosensitivity. Therefore, extra process steps are required in the manufacturing process to compensate for these problems. For example, a black matrix is used to block light from reaching the TFTs, and the drivers for the display have to be manufactured in a separate process from the TFTs of the array. 
     To avoid the problems related to displays with a-Si:H based TFTs, polysilicon TFTs are preferred. However, one significant drawback to a polysilicon TFT is high leakage current. But, proper design of a polysilicon TFT structure can minimize the leakage current, and the display panel manufacturing process is simplified and cost is reduced when the drive circuits are integrated into the pixel TFT manufacturing process. However, a major problem with manufacturing polysilicon TFTs is the formation of polysilicon under certain required conditions, which include: (1) a low process temperature, for example, less than 550° C. on a low temperature glass; (2) a large glass substrate; and (3) a high throughput. 
     Therefore, high temperature processes, such as annealing, which are conducted at temperatures of about 700° C., are not suitable for the low temperature glass that is required for manufacturing polysilicon TFTs. Several other methods, including laser crystallization, furnace annealing, and reactive chemical vapor deposition have been used for preparing the polysilicon. But these methods also require either high temperatures or lengthy process times. Also, uniformity over a large area is difficult to achieve. Therefore, with conventional methods, high quality polysilicon cannot be made efficiently. 
     FIG. 1 shows another conventional method for making polysilicon called Metal Induced Lateral Crystallization (MILC), which is included in the furnace annealing method. Referring to FIG. 1, after an amorphous silicon layer  21  is provided on a glass substrate  20 , an insulating material is deposited on the amorphous silicon layer  21  and then patterned to define a protection film  23 . On the amorphous silicon layer  21  is provided a metal layer  25  made of a material such as Ni or Pd. Next, the substrate  20  and the metal layer  25  are heated in an electric furnace for over ten hours at about 550° C. A portion of the amorphous silicon layer  21  that is beneath the protection film  23 , where the metal has not been deposited, is crystallized from the outer portions towards the inner portions and constitutes a polysilicon layer  22 . 
     As mentioned earlier, the conventional methods require either a high temperature process or a lengthy process. Therefore, as in the other conventional methods, the throughput with the MILC process is low, and high quality polysilicon can not be formed. 
     SUMMARY OF THE INVENTION 
     To overcome the problems described above, preferred embodiments of the present invention provide a method of manufacturing polysilicon crystals in a TFT such that polysilicon is formed on a large glass substrate rapidly and at low temperatures with the resultant polysilicon TFTs having a high throughput rate. 
     A preferred embodiment of the present invention provides a method for manufacturing a polysilicon layer including the steps of providing a substrate, forming an amorphous silicon layer on an entire surface of the substrate, and patterning the amorphous silicon layer, forming an active area on the amorphous silicon layer; and applying a voltage to the amorphous silicon layer to form a polysilicon layer using a joule heat that is generated from the applied voltage. 
     In another preferred embodiment of the present invention, a method for manufacturing a polysilicon layer in a thin film transistor includes providing a substrate, forming an amorphous silicon layer on the entire surface of the substrate, forming an active area on the amorphous silicon layer, doping the amorphous semiconductor layer with a semiconductor material, and depositing a metal layer on the amorphous silicon layer; and applying a voltage to the amorphous silicon layer, and converting the amorphous silicon layer into a polysilicon layer using a joule heat generated from the applied voltage. 
     In preferred embodiments, the joule heat that is generated by the voltage applied to the amorphous silicon layer crystallizes the undoped portion of the amorphous silicon layer. During the crystallization process, the temperature of the amorphous silicon layer is increased only to about 500° C., which is much lower than the conventional methods. 
     Further, in preferred embodiments, there are three preferred methods to form the active area of the TFT. In a first preferred method, the active area is defined by forming a protection layer on a predetermined portion of the amorphous silicon layer, doping the amorphous silicon layer with a semiconductor material, and then depositing a metal layer over the substrate and covering the protection layer and the doped amorphous silicon layer. A second preferred method includes providing a photoresist protection layer on the amorphous silicon layer and etching the photoresist protection layer, doping the amorphous silicon layer with a semiconductor material, and depositing a metal layer on the amorphous silicon layer to cover the photoresist protection layer, and patterning the photoresist protection layer and the metal layer to expose a portion of the amorphous silicon layer that is beneath the photoresist protection layer. Finally, a third preferred method includes doping the amorphous silicon layer with a semiconductor material, depositing a metal layer on the amorphous silicon layer, and patterning the doped amorphous silicon layer and the metal layer such that the amorphous silicon layer is over-etched so that a doped portion of the amorphous silicon layer is removed thereby exposing substantially an undoped portion of the amorphous silicon layer. 
     Other features, elements and advantages of the present invention will be described in detail below with reference to preferred embodiments of the present invention and the attached drawings. 
    
    
     BRIEF DESCRIPTION OF THE ATTACHED DRAWINGS 
     The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus do not limit the present invention and wherein: 
     FIG. 1 illustrates a conventional method for making polysilicon which is referred to as Metal Induced Lateral Crystallization; 
     FIG. 2 is a cross-sectional view for illustrating the beginning step in the process for making a polysilicon layer according to preferred embodiments of the present invention; 
     FIG. 3 is a plan view illustrating a first sample pattern for the active area of a thin film transistor according to a preferred embodiment of the present invention; 
     FIG. 4 is a plan view illustrating a second sample pattern for the active area of the thin film transistor according to a preferred embodiment of the present invention; 
     FIG. 5 is a plan view illustrating a third sample pattern for the active area of the thin film transistor according to another preferred embodiment of the present invention; 
     FIGS. 6A to  6 C are sectional views taken along the line VI—VI of FIG. 4, and which shows a first preferred method for manufacturing the active area of the thin film transistor; 
     FIGS. 7A to  7 B illustrates a second preferred method for manufacturing the active area of the thin film transistor; 
     FIGS. 8A to  8 B illustrates a third preferred method for manufacturing the active area of the thin film transistor; 
     FIG. 9 is a plan view illustrating a method of crystallizing polysilicon according to another preferred embodiment of the present invention; and 
     FIG. 10 illustrates a manufacturing process for a thin film transistor according to another preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 2 shows the beginning step in the process for manufacturing a polysilicon layer for an active layer of a TFT according to a preferred embodiment of the present invention. Referring to FIG. 2, an insulating material such as SiO 2  is deposited on an entire surface of the glass substrate  100  to provide a buffer layer  111 . The buffer layer  111  is used to prevent misalignment between the glass-substrate  100  and a semiconductor layer that is to be provided later, and also to prevent the semiconductor layer from being contaminated. On the buffer layer  111 , there is deposited an amorphous silicon material to provide an amorphous silicon layer  113 . At this point, a pattern can be selected from several patterns for defining the active area of the thin film transistor. One of the factors to be considered in selecting a pattern includes the current-flow when a voltage is applied. 
     FIGS. 3 to  5  show various patterns for defining the active area of the TFT. FIG. 3 shows a first sample pattern. In the first sample pattern, the amorphous silicon is deposited on the entire surface of the glass substrate  100 , and the active areas  150  of the TFTs are provided in the form of a matrix. FIG. 4 shows a second sample pattern, which is a modification of the first pattern. The amorphous silicon material is deposited and then patterned in the shape of laterally extended amorphous silicon layers  113  preferably having a substantially octagonal shape and having an active area  150  with a substantially rectangular shape. The second pattern has the advantage of having a low caloric value for the entire silicon layer  113 . 
     For a more detailed explanation, the expression for the caloric value “H” is given below:        H   =       P   ×   t     =         V   2     R     ×   t                              
     where “V” is a voltage, “R” is a resistance, and “t” is a time period. More specifically, since the area where a voltage is applied (i.e., the patterned amorphous silicon layer  113 ) to the substrate  100  is decreased, the resistance of the amorphous silicon layer  113  is increased. Thus, according to the above equation, the caloric value of the silicon layer  113  is decreased, which helps to maintain the glass substrate  100  at a low temperature during the crystallization process. 
     FIG. 5 shows a third sample pattern, which is a modification of the second pattern. An active area  150  and an amorphous silicon layer  113  are preferably formed in the same way as the second pattern. The width of the active area  150  is preferably substantially the same as the amorphous silicon layer  113 . As in the second sample pattern, the caloric value of the entire silicon layer  113  is reduced since the area of the silicon layer is reduced. 
     After defining the active area  150 , a method for manufacturing the active area  150  according to preferred embodiments is as follows. There are three preferred methods for manufacturing the active area of the TFT in the present invention. 
     FIGS. 6A to  6 C illustrate a first preferred method for manufacturing the active area of the TFT. Though FIGS. 6A to  6 C are sectional views of FIG. 4, the sample patterns for the silicon layer as shown in FIGS. 3 and 5 can also be used in the following method. Referring to FIG. 6A, after patterning the amorphous silicon layer  113 , an insulating substance is then deposited on the amorphous silicon layer  113  and then patterns to define a protection layer  115 . Next, N-type or P-type semiconductor material dopes the amorphous silicon layer  113 . This process creates a surface with a low resistance on the amorphous silicon layer  113 . 
     Referring to FIG. 6B, a metal layer  117  is deposited over the entire surface of the substrate  100  and covers the protection layer  115  and the doped silicon layer  113 . The metal layer  117  preferably uses a metal such as Ni or Pd for defining a silicide layer that is created by the reaction of the metal layer  117  with the silicon layer  113 . Note that when the reaction creates the silicide layer, the resistance of the silicon layer  113  is decreased. Thus, the silicide layer is used as a heating element for a joules heat. Note that the amorphous silicon is a semiconductor material so that the resistivity of the amorphous silicon layer becomes lower as the temperature of the amorphous silicon becomes higher. Lower resistivity can also be achieved when the amorphous silicon layer is doped by the N-type or P-type semiconductor material. Therefore, the amorphous silicon layer can be used as the heating element for supplying the joules heat when a voltage is applied such that the resistivity of the amorphous silicon layer is lowered to a predetermined level. 
     Referring to FIG. 6C, a voltage for the crystallization process is applied at both terminals of the substrate  100 . As described previously, because of the doping process and the silicide layer, the caloric value in the active area  150  is higher because of its lower resistance. Note that the crystallization of the polysilicon  160  proceeds from the interface between the metal layer  117  and the ion-doped amorphous silicon layer  113  towards the inside of the amorphous silicon layer  113 . 
     FIGS. 7A to  7 B show a second preferred method for manufacturing an active area for a TFT. Referring to FIG. 7A, after patterning the amorphous silicon layer  113 , N-type or P-type semiconductor material dopes the amorphous silicon layer  113 . Thereafter, a metal layer  117  is deposited on an entire surface of the amorphous silicon layer  113 . 
     Referring to FIG. 7B, the doped amorphous silicon layer  113  and the metal layer  117  is patterned to form an active area  150 . Note that at this point, the active region  150  of the amorphous silicon layer  113  is over-etched so that the doped portion may be removed. This is done to prevent the TFT from having low switching characteristics. 
     A third preferred method for manufacturing the active area of a TFT is shown in FIGS. 8A to  8 B. Referring to FIG. 8A, after patterning the amorphous silicon layer  113 , a photoresist is deposited on the amorphous silicon layer  113  and then patterned to provide a photoresist protection layer  140 . Then, N-type or P-type semiconductor material dopes the amorphous silicon layer  113 , and a metal layer  117  is then deposited on the amorphous silicon layer  113  and covers the photoresist protection layer  140 . 
     Referring to FIG. 8B, the photoresist protection layer  140  and the metal layer  117  is etched so that a predetermined portion of the amorphous silicon layer  113 , the portion which is directly beneath the photoresist layer  140 , is exposed to define the active area  150 . Note that in the present preferred method, there is no need for the amorphous silicon layer  113  to be over-etched as in the method of FIG. 7B since the active area  150  is not doped due to the protection layer  140 . 
     In the second and third preferred methods, the next step in the manufacturing process is to apply a voltage for crystallization of the polysilicon. Referring to FIG. 9, when a voltage is applied to both terminals of the substrate  100 , polysilicon crystals  160  are grown at the exposed portion  150  of the amorphous silicon layer  113 . The polysilicon crystals  160  grow towards the inside of the amorphous silicon layer  113  from the interface between the metal layer  117  and the doped amorphous silicon layer  113 . 
     Referring to FIG. 10, the amorphous silicon layer  113  is then etched, and only the polysilicon layer  160  remains. Next, an insulating material and a metal conductive material are sequentially deposited on the polysilicon layer  160  and then patterned simultaneously to provide a first insulating layer  180  and a gate electrode  190 , respectively, and which are patterned such that the end portions of the polysilicon layer  170  are exposed. Then, N-type or P-type semiconductor material dopes the exposed end portions of the polysilicon layer  160  for defining source and drain regions  200  and  210 . Then, an insulating material is deposited on the entire surface of the substrate  100  to provide a second insulating layer  220  and covers the gate electrode  190 . First and second contact holes  230  and  240  are provided on the second insulating layer  220  for exposing the source and drain regions  200  and  210 . Source and drain electrodes  250  and  260  are then defined to electrically connect the source and drain regions  200  and  210 . 
     Therefore, preferred embodiments of the present invention provide a method for manufacturing polysilicon TFTs such that a polysilicon layer is provided at relatively low temperatures, for example, less than about 550° C., and maintaining the glass substrate at a low temperature for about five hours so that a throughput is high. 
     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.