Abstract:
A system includes a master and a slave coupled via a wire pair for transmitting differential data. The master and slave are each powered by a local DC power supply. In a normal mode, a DC voltage and differential data are supplied over the same wire pair. The differential data is processed by a PHY AC-coupled to the wire pair. To enter a low power sleep mode, such as due to a temporary non-use of the system, the master interrupts the DC voltage on the wire pair, which signals to the slave to enter the sleep mode. The system is woken up by reapplying the DC voltage to the wire pair to signal to the slave to wake up. Only the DC path, and not the data path, is used for signaling the sleep mode and awake mode, so the data path can be disabled to conserve power.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. provisional application Ser. No. 62/160,369, filed May 12, 2015, by Andrew J. Gardner et al, assigned to the present assignee and incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to systems where DC power and data are transmitted from one piece of data terminal equipment to another via a twisted wire pair. The invention more particularly relates to techniques for putting the system into a low power sleep mode and waking the system up from the sleep mode even if the data path physical layer has been disabled during the sleep mode. 
     BACKGROUND 
     In a Power over Data Lines (PoDL) system, DC power from Power Sourcing Equipment (PSE) is transmitted over a single twisted wire pair to a Powered Device (PD) after the system goes through a powering up routine, referred to as a detection and classification routine, that indicates that the PD is PoDL compatible. The same twisted wire pair also transmits/receives differential data signals, typically in accordance with the Ethernet protocols. A DC coupling network couples DC to the wire pair, and an AC coupling network couples the differential data to the wire pair. DC and AC decoupling networks decouple the DC power and AC data from the wire pair. In this way, the need for providing any external power source for the PD can be eliminated. The standards for PoDL are set out in IEEE 802.3 and are well-known. 
     In a PoDL system, the units coupled to the wire pair are sometimes referred to as a master and a slave (rather than a PSE and a PD), since either unit may control the other. The master may sometimes act as a slave. In some of the examples below, one unit is designated as a master and the other unit is designated as a slave; however, the designations may be reversed depending on the function being performed. 
       FIG. 1  illustrates conventional PoDL system including AC/DC coupling/decoupling networks (C 1 -C 4 , L 1 -L 4 ) between a PSE  10  and a PD  12 . The PSE  10  includes a DC voltage source  13  and a differential data portion whose interface to the wire pair  16  is identified as a physical layer (PHY)  17 . The PHY  17  may include transceivers and other circuitry for processing the data in accordance with the IEEE standards. The PD  12  has a similar PHY  18 . The details of the data portion of the PoDL system are not particularly relevant to the present invention. 
     Other types of systems (non-PoDL systems) include a DC power source at both end terminals, so PoDL is not required for normal operation. Data is transmitted over a twisted wire pair between the two terminals. 
     In some applications, it is desired for the system to enter a low power sleep mode (or standby mode) after being initially powered up, where power is removed from certain circuitry to conserve power. This may be done by a master or slave issuing a sleep mode code, using the differential data path (the twisted wire pair), and the processors in the master and slave then controlling the circuits to go into a low power mode. However, the PHYs must remain powered to receive a wake-up signal over the data path. The PHYs consume power in the sleep mode, which may be undesirable if very low power consumption is needed. 
     What is needed is a technique for allowing the PHYs to also be disabled in a sleep mode and allowing the PHYs to be woken up without using the data path. 
     SUMMARY 
     In a system using a twisted wire pair to communicate differential data between two end terminals, a sleep mode signal and a wake up signal are transmitted between a master and a slave in a non-PoDL system (both ends have a DC power supply) solely using a DC path. Therefore, since the data path is not needed, the PHYs can be disabled during the sleep mode along with any other data processing circuitry to conserve power. This is particularly valuable where the power supply is a battery. 
     In one embodiment, either of the units coupled to the wire pair can be a master or a slave, and the units are symmetrical. The designation in the examples is arbitrary. The master and slave each include a DC voltage transmitter and a DC voltage receiver. During normal operation, the master and slave may each be powered by their own local power supply. 
     Either the master or the slave is capable of coupling a DC voltage to the twisted wire pair. The DC voltage is supplied to the wire pair by the transmitter in the master. The output of the transmitter while supplying the DC voltage is a low impedance resulting from the transmitter being in an ON state, which is referred to as a dominant state. This dominant state represents a logical low signal. The slave, during this normal operation, detects the DC voltage from the wire pair. 
     In one embodiment, the master and slave both include a transmitter and receiver, independent from the data path, coupled to the wire pair. A microcontroller is coupled to the transmitter and receiver in the master and slave. 
     Sleep mode may be initiated after a period of non-use. When a sleep mode is to be initiated by the master, the master&#39;s microcontroller controls the master&#39;s transmitter to switch to a high impedance output (a recessive state). When the slave enters sleep mode, the slave&#39;s microcontroller controls the slave transmitter to switch to a high impedance state causing the wire pair to be at 0 volts. The mutual termination of DC voltage by both the master and the slave causes both microcontrollers to disable their PHY for the data path and any other unnecessary circuitry in order to conserve power. 
     If the master microcontroller later issues a wake up signal, the master transmitter switches to its dominant state to couple a DC voltage to the wire pair, and this DC voltage is detected by both the slave receiver and the master receiver. The slave receiver, upon detecting the DC voltage, outputs a wake up signal to the slave microcontroller, and the slave microcontroller responds by enabling the slave PHY. Similarly, the master receiver may output a wake up signal to the master microcontroller in response to a wakeup DC voltage transmitted from the slave, and the master microcontroller may then enable the master PHY. The system is then able to operate normally. 
     The DC voltage on the wire pair does not affect any data reception since the PHYs may be coupled to the wire pair using AC-coupling capacitors, and the DC voltage is common mode so does not affect the detection of the differential data by the PHYs. 
     In other embodiments, the sleep mode may be signaled by multiple DC pulses (creating a code) on the wire pair. 
     If one of the transmitters is in a dominant state and the other transmitter is in a recessive state, the contention is resolved in favor of the dominant state. 
     Thus, the signaling for indicating a sleep mode and wake up is solely via the DC path, so the data path may be shut down during the sleep mode. This technique can be applied to PoDL systems, where a PSE always powers the PD by a DC voltage via the same wire pair used to conduct data, or to non-PoDL systems, where both terminals have their own DC power supply. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a conventional PoDL Ethernet system using a single wire pair for supplying power and data to the PD. 
         FIG. 2  illustrates a system, in accordance with one embodiment of the invention, where DC signaling using only the DC path is used to put the system in a sleep mode and wake the system from the sleep mode. 
         FIG. 3  illustrates a possible master transmitter for the circuit of  FIG. 2 . 
         FIG. 4  illustrates highly compressed waveforms showing voltage levels on the wire pair and various outputs of the microcontroller, transmitters, and receivers when the system is waking up from a sleep mode and then going into a sleep mode. 
         FIG. 5  is a flow chart showing steps used for entering a sleep mode and waking up from the sleep mode. 
     
    
    
     Elements that are the same or equivalent are labeled with the same numeral. 
     DETAILED DESCRIPTION 
       FIG. 2  illustrates one embodiment of a system in accordance with the present invention. 
     A master  20  and a slave  22  are shown coupled to a twisted wire pair  24 . The designation of master and slave is arbitrary since either can be the master. In one embodiment, the master  20  includes an electronic control unit in an automobile, and the slave is a sensor or an accessory in the automobile. It is assumed that the master  20  and slave  22  are each coupled to a DC power supply (not shown) through a connection external to the wire pair  24 . The wire pair  24  carries differential data (an AC signal). The capacitors C 1 -C 4  only pass the AC data signal to the PHY 1  or the PHY 2  physical layers, which interface the wire pair to the data processing circuitry of the master  20  and slave  22 . Such PHY circuitry may include transceivers, conditioning circuits, etc. 
     The master  20  includes a microcontroller uC 1  that receives a sleep mode initiation signal or a wake up initiation signal at its input/output terminal  28 . One output of the microcontroller uC 1  controls the state of a transmitter  30  in a transceiver XCVR 1 , where the transmitter  30  has power input terminals coupled to a locally generated DC voltage, and where the transmitter  30  is controlled to provide the DC voltages V 1 + and V 1 − at its output terminals. Another input into the microcontroller uC 1  is the output of receiver  32 . Another output of the microcontroller uC 1  controls a power switch SWX 1  for the physical layer PHY 1  portion of the data path. When the PHY 1  is to be enabled, the En 1  signal is asserted to close the switch SWX 1 . The En 1  signal may shut down and enable other circuitry in the master  20  for conserving power; however, the present invention is directed to the control of the PHY 1 . 
     The slave  22  contains symmetrical circuitry including a transceiver XCVR 2  comprising a transmitter  34  and a receiver  36  coupled to the slave microcontroller uC 2 . The transmitter  34  is controlled to provide the DC voltages V 2 + and V 2 − at its output terminals. The microcontroller uC 2  controls a switch SWX 2  to enable or disable the physical layer PHY 2  for the slave&#39;s data path. 
     The differential transceivers XCVR 1  and XCVR 2  are DC-coupled to the wire pair  24  via resistors R 1 -R 2  and R 3 -R 4 , respectively. The DC coupling resistor values are constrained by the Ethernet PHYs&#39; medium dependent interface (MDI) return loss (RL) requirement. MDI RL is defined as: 
               MDI   ⁢           ⁢   RL     =     20   ×       log   10     ⁡     (              100   ⁢   Ω     -     Z   MDI           100   ⁢   Ω     +     Z   MDI              )               
where Z MDI  is the impedance looking into either MDI 1  or MDI 2  from the wire pair  24 . A typical requirement for MDI RL may be for a loss of −20 dB or more which yields a minimum value for R 1 -R 4  of ˜250Ω. A value significantly greater than 250Ω may be chosen for R 1 -R 4  in order to provide margin against the MDI RL limit. Resistors R 5 -R 6  discharge the outputs of the transceivers XCVR 1  and XCVR 2  during the recessive state, respectively, and have values much greater than R 1 -R 4 . Capacitors C 5 -C 6  in conjunction with resistors R 1 -R 2  and R 3 -R 4 , respectively, filter the AC signal resulting from the Ethernet PHYs operation.
 
     During normal operation, when the system is “awake,” the master microcontroller uC 1  may control its transmitter  30  to be in its dominant state, and the slave microcontroller uC 2  may control its transmitter  34  to be in the recessive state. The master  20  and slave  22  are powered by their local DC power supplies. The transmitter  30  in its dominant state has a low impedance and provides the voltages V 1 + and V 1 − on the wire pair  24 , shown in  FIG. 2 . This control signal to the transmitter  30  is arbitrarily designated as a low logic level signal. The microcontroller uC 1  also closes the switch SWX 1  via the signal En 1  to supply power to the physical layer PHY 1  for the data path, thus enabling the PHY 1 . Concurrently, the slave&#39;s receiver  36  detects the DC voltage differential across the wire pair  24  and outputs a control signal to the slave microcontroller uC 2  indicating that the slave is receiving the master&#39;s dominant voltage. The microcontroller uC 2  enables the physical layer PHY 2  for the data path by closing the switch SWX 2  via the signal En 2  to supply power to the PHY 2 . Data may then be transmitted and received between master  20  and slave  22  via the PHY 1  and PHY 2 . 
     A sleep signal can be initiated in any number of ways, such as by a timer, non-use of the system, user control, detecting a load current is below a threshold level, etc. In one embodiment, a sleep signal is applied to the master microcontroller uC 1 , or is initiated by the master microcontroller uC 1 . The microcontroller uC 1  then controls the transmitter  30  to go into a high impedance recessive state, where the DC voltage V 1 + and V 1 − is no longer coupled to the wire pair  24 . The shunt resistors R 5  and R 6  discharge the capacitors C 5  and C 6  and wire pair  24  so that, after a brief period, the voltage across the wire pair  24  is zero volts. The receivers  32  and  36  detect the zero volt differential and output a logic high signal. The outputs of the receivers  32  and  36  are sensed by the respective microcontrollers uC 1  and uC 2 . The slave microcontroller uC 2  then removes the asserted En 2  signal, which causes the switch SWX 2  (e.g., a transistor) to open (e.g., turn off), disabling the physical layer PHY 2  for the data path to conserve power. Similarly, the master microcontroller uC 1  then removes the asserted En 1  signal, which causes the switch SWX 1  to open, disabling the physical layer PHY 1  for the data path to conserve power. 
     At this stage in the sleep mode, both transceivers XCVR 1  and XCVR 2  are in their recessive states (e.g., high impedance open circuits) and both physical layers PHY 1  and PHY 2  are disabled. 
       FIG. 3  illustrates a possible type of transmitter  30 , where MOSFETs M 1  and M 2  turn on in the dominant state to couple the DC voltage V+ and −V− to the wire pair  24  and turn off in the recessive state to allow the shunt resistors R 5  and R 6  to discharge the wire pair  24 . Level shifters  40  and  42  appropriately level shift the sleep or wake up control signal from the microcontroller uC 1  to control the MOSFETs M 1  and M 2 . Many other types of circuits can be used instead. 
     Eventually, a wake up event will occur, such as when it is determined that the system is required to perform an operation.  FIG. 4  illustrates various highly compressed waveforms representing the voltages (V MDI+  and V MDI− ) at the Medium Dependent Interface (MDI 1  or MDI 2 ) for the wire pair  24  and the logic levels at the various transmitters and receivers. 
     Prior to time T 0 , it is assumed the system is in a sleep mode with zero voltage across the wire pair  24  and the transceivers XCVR 1  and XCVR 2  being in their recessive states. At time T 0 , the master microcontroller uC 1  receives a wake up signal, which signals that the DC voltage (V 1 + and V 1 − in  FIG. 2 ) should be applied to the wire pair. The microcontroller uC 1  then controls the transmitter  30  to be in its dominant state so as to apply the DC voltage to the wire pair  24 . The master and slave receivers  32  and  36  detect the voltage differential on the wire pair  24  and switch to their dominant states, causing the respective microcontrollers uC 1  and uC 2  to assert the En 1  and En 2  signals to apply power to the respective physical layers PHY 1  and PHY 2  for the data path. The slave transmitter  34  is optionally controlled to be in its dominant state for a short period in response to the received DC voltage. 
     Between time T 0  and T 1 , the system is operating normally, where DC voltage and differential data are transmitted over the wire pair  24 . It is again noted that the transmitted DC voltage is not necessarily used to power either of the end terminals, so the DC power can be low. 
     At time T 1 , the wake up signal into terminal  28  of  FIG. 2  is deasserted, signifying that a sleep mode is initiated. There is a slight delay before the master transmitter  30  is controlled to be in its recessive state to give the system time to complete any required routines. After the transmitter  30  goes into its recessive state, the resistors R 5  and R 6  discharge the voltage on the wire pair  24 , as shown by the V MDI+  and V MDI−  waveforms. 
     A time T 2 , the voltage differential has gone below a threshold and the receivers  32  and  36  go into their recessive (e.g., off) states and output a high impedance. The master and slave microcontrollers uC 1  and uC 2  then deassert the En 1  and En 2  signals to disable the physical layer PHY 1  and PHY 2  to conserve power. 
     The self-explanatory flowchart of  FIG. 5 , comprising steps  50 - 58 , reiterates the basic process discussed above where the sleep mode and awake mode are signaled solely using the DC path rather than the data path. This enables the data path to be disabled during the sleep mode to conserve power. 
     If one of the transmitters is in a dominant state and the other transmitter is in a recessive state, the contention is resolved, by the processing systems, in favor of the dominant state. 
     A central electronic control unit (ECU) will typically be part of the system, and this ECU may always be powered for managing the wake up initiation for coming out of sleep mode. 
     If it is known that one unit will always be a master and the linked unit will always be a slave, there is no need for a receiver in the master if the master microcontroller can disable the master PHY without any feedback from such a receiver. Similarly, if it is known that one unit will always be a master and the linked unit will always be a slave, there is no need for a DC transmitter in the slave. In the example of  FIG. 2 , the two sides use symmetrical circuitry for simplicity of use. 
     The communication between the end terminals using only the DC path can be used for any purpose while the PHYs are either enabled or disabled. Pulsed codes may be transmitted using the DC path. In the event of a bus collision between the two DC transmitters, the DC receivers at both ends may detect the discrepancy and force their associated transmitter to delay a transmission in order to arbitrate the bus. Therefore, half-duplex serial communication between the two ends of the link may be realized while the AC-coupled PHYs are disabled. 
     While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications.