Abstract:
Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.

Description:
TECHNICAL FIELD 
       [0001]    Various exemplary embodiments disclosed herein relate generally to all-digital phase-locked loops (ADPLLs) having reduced settling times. 
       BACKGROUND 
       [0002]    Current solutions for ADPLLs may use a time interval to adjust various lock states. During this settling time, disturbances in both phase and frequency may occur. Because of these disturbances, the output signal of the PLL cannot be used during the settling time. 
       SUMMARY 
       [0003]    A brief summary of various exemplary embodiments is presented below. Some simplifications and omissions may be made in the following summary, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope of the invention. Detailed descriptions of an exemplary embodiment adequate to allow those of ordinary skill in the art to make and use the inventive concepts will follow in later sections. 
         [0004]    Various exemplary embodiments relate to a non-transitory medium encoded with instructions for execution of a method of reducing a settling time of a Phase Locked Loop (ADPLL), the non-transitory medium including: instructions for_calculating, in a processor, a frequency for a Digital Controlled Oscillator (DCO) by searching for the frequency based upon operational parameters of the DCO; instructions for comparing the calculated frequency to a measured frequency; and instructions for compensating, based upon the comparison, the ADPLL to decrease a settling time. 
         [0005]    In various exemplary embodiments, the DCO may be controlled by a plurality of capacitor banks. The plurality of capacitor banks may comprise a Process-Voltage-Temperature (PVT) bank, an Acquisition (ACQ) bank, and a Tracking (TR) bank. There may be instructions for setting a desired frequency between two smallest possible steps of the TR bank. There also may be instructions for setting a threshold for the TR bank; instructions for determining whether the TR bank will exceed the stored threshold; and instructions for exchanging capacitors between banks when the TR bank is about to exceed the stored threshold. There additionally may be instructions for exchanging capacitors between the TR bank and the ACQ bank and instructions for exchanging capacitors between the ACQ bank and the PVT bank. The instructions for calculating may use either binary or linear searching. There further may be instructions for measuring a difference between an ambient temperature and a standard temperature based upon the DCO frequency; instructions for storing the DCO frequency at the standard temperature; and instructions for comparing a DCO frequency at the ambient temperature to the stored DCO frequency. 
         [0006]    Further, various exemplary embodiments relate to a hardware device including: a network interface; a memory device; and a processor in communication with the interface memory device, the processor being configured to calculate a frequency for a Digital Controlled Oscillator (DCO) by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, the ADPLL to decrease a settling time. 
         [0007]    In various exemplary embodiments, the DCO may be configured to be controlled by a plurality of capacitor banks. The plurality of capacitor banks may comprise a Process-Voltage-Temperature (PVT) bank, an Acquisition (ACQ) bank, and a Tracking (TR) bank. The processor may be configured to set a desired frequency between two smallest possible steps of the TR bank, set a threshold for the TR bank, determine whether the TR bank will exceed the stored threshold, and, when the TR bank is about to exceed the stored threshold, exchange capacitors between banks. The processor may also be configured to either exchange capacitors between the TR bank and the ACQ bank, or exchange capacitors between the ACQ bank and the PVT bank. The processor may additionally be configured to measure a difference between an ambient temperature and a standard temperature based upon the DCO frequency, store the DCO frequency at the standard temperature, and compare a DCO frequency at the ambient temperature to the stored DCO frequency. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]    In order to better understand various exemplary embodiments, reference is made to the accompanying drawings, wherein: 
           [0009]      FIG. 1  illustrates a tuning diagram for an ADPLL; 
           [0010]      FIG. 2  illustrates a first embodiment of an improved ADPLL; 
           [0011]      FIG. 3  illustrates an exemplary schematic diagram for a DCO. 
           [0012]      FIG. 4  illustrates an improved tuning diagram for a ADPLL; and 
           [0013]      FIG. 5  illustrates a second embodiment of an improved ADPLL. 
       
    
    
       [0014]    To facilitate understanding, identical reference numerals have been used to designate elements having substantially the same or similar structure and/or substantially the same or similar function. 
       DETAILED DESCRIPTION 
       [0015]    The description and drawings illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, “or,” as used herein, refers to a non-exclusive or (i.e., and/or), unless otherwise indicated (e.g., “or else” or “or in the alternative”). Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. As used herein, the terms “context” and “context object” will be understood to be synonymous, unless otherwise indicated. 
         [0016]      FIG. 1  illustrates a tuning diagram for an ADPLL. The time for locking is on the order of 60 μs. Because of disturbances in phase and frequency during the settling period before locking, the output signal of the ADPLL cannot be used for reception of a radio signal. For an analog PLL, the output of the receiver would be disturbed too much, while for a digital PLL, loss of data will occur. Thus, locking for ADPLLs may be disrupted. 
         [0017]    Various exemplary embodiments are described below that may calculate the settling period settings for the ADPLL. Further, an iterative set of calculations may be made based upon the fact that a digitally controlled oscillator (DCO) may have various levels of control resolution. 
         [0018]      FIG. 2  illustrates a first embodiment of an improved ADPLL  200 . ADPLL  200  includes a digitally-controlled oscillator (DCO) model device  210 , a ramp generator  220 , a filter  230 , a TDC  240 , a divider  250 , and a DCO  260 . These devices are described in further detail below. 
         [0019]    The DCO model device  210  receives a Frequency Control Word (FCW) signal as input. Based upon the FCW signal, it produces a Process-Voltage Temperature (PVT) signal and an Acquisition (ACQ) signal. The PVT and ACQ signals are subsequently used for calibration. The DCO model device  210  also forwards a copy of the FCW signal to an adder of ramp generator  220 . 
         [0020]    The ramp generator  220  receives a combination of the FCW signal from the DCO model device  210  and a feedback phase signal as an input signal. Ramp generator  220  then samples this input signal with reference frequency f ref  and, in this way, generates a reference phase, φ ref . The FCW signal may be added to the content of the register each f ref  cycle. In particular, ramp generator  220  may generate the reference phase φ ref  by integrating the FCW signal over time. 
         [0021]    In an exemplary embodiment, each register may represent a number by a certain number of bits. Application of the FCW signal results in the content of the register increasing in a staircase shape. This value of the register may continue to increase until a maximum representable number, which is defined by the bit-width of the register, is reached. The register then will “flip over”. After flipping over, the content of the register is the modulo value of the sum of the register content and the FCW signal, divided by a maximum number defined by the bit width of the register or any other set maximum number lower than the maximum count defined by the bit width of the register. 
         [0022]    For example, a ramp may be applied to an adder. The adder then subtracts the feedback phase from the reference phase. Thus, the feedback phase is compared to the input phase. The difference between the reference and feedback phases is the control signal for the loop. A feedback loop then sends the reference phase, φ ref , back to an adder so that it can be combined with the FCW signal to produce the input signal for ramp generator  220 . 
         [0023]    Filter  230  receives, from an adder, a combination of the reference phase, φ ref , and a feedback signal, φ v , as an input signal. In the case of linear control, this may be a difference between reference and feedback phases. Other methods might be used to compare the signals. Filter  230  may generate a new TR for the DCO based upon the phase difference during each reference cycle. 
         [0024]    The time-to-digital converter (TDC)  240  receives a DCO output signal (LO) from the DCO  260  as input. This received signal may be a local oscillator (LO) signal. The TDC  240  then compares the phase of the input signal to the phase of the reference frequency f ref  to produce output phf f . TDC  240  may provide a resolution enhancement of the phase measurement, e.g., by measuring the position of the reference edge within a DCO period. 
         [0025]    The divider  250  receives the DCO output signal from the DCO  260  and produces phf i  as output. The combination of phf f  and phf i  results in φ v . 
         [0026]    The DCO  260  receives the PVT and ACQ signals from the DCO model device  210  as input. The DCO  260  receives a TR signal that combines signals from both the DCO model device  210  and the filter  230 . The DCO  260  may be an inductive-capacitive (LC) oscillator that is controlled by a plurality of capacitor banks. The capacitor banks may include a PVT bank, an ACQ bank, and a TR bank. Based upon the PVT, ACQ, and TR signals, DCO  260  produces output, which may be the local oscillator (LO) signal. 
         [0027]      FIG. 3  illustrates an exemplary schematic diagram for a DCO  300 . The DCO  300  may include a power supply  310 , a pair of inductors  320 , a PVT capacitor bank  330 , an ACQ capacitor bank  340 , a TR capacitor bank  350 , a pair of transistors  360 , an inductor  370 , and a ground  380 . 
         [0028]    A power supply  310  may be coupled between two inductors  322  and  324  of the pair of inductors  320 . The opposite ends of inductors  322  and  324  may be coupled to opposing ends of PVT capacitor bank  330 , ACQ capacitor bank  340 , and TR capacitor bank  350 . 
         [0029]    A PVT capacitor bank  330  may include a first capacitor bank  332 , a switch  334 , and a second capacitor bank  336 . An input PVT signal may be coupled to switch  334 , which may be disposed between first capacitor bank  332  and second capacitor bank  336 . Each least significant bit (LSB) in the input PVT signal may correspond to a step within a range of 5 MHz to 10 MHz. Each step may be a 5 fF capacitor. For both first capacitor bank  332  and second capacitor bank  336 , switch  334  may select from among multiple inputs of the capacitor banks to allow for various capacitance values based upon the selection. 
         [0030]    An ACQ capacitor bank  340  may include a first capacitor  342 , a switch  344 , and a second capacitor  346 . An input ACQ signal may be coupled to switch  344  that is disposed between first capacitor  342  and second capacitor  346 . Each LSB in the input ACQ signal may correspond to a step within a range of 500 KHz to 1.2 MHz. Each step may be a 500 aF ccit The first capacitor  342  and the second capacitor  346  may also be implemented by a capacitor bank, wherein switch  344  may select from among multiple inputs of the capacitor bank to allow for various capacitance values based upon the selection. 
         [0031]    A TR capacitor bank  350  may include a first capacitor  352 , a switch  354 , and a second capacitor  356 . An input TR signal may be coupled to switch  354 , which may be disposed between first capacitor  352  and second capacitor  356 . Each LSB in the input TR signal may correspond to a step within a range of 15 KHz to 50 KHz. Each step may be a 10 aF capacitor. The first capacitor  352  and the second capacitor  356  may also be implemented by a capacitor bank, wherein switch  354  may select from among multiple inputs of the capacitor bank to allow for various capacitance values based upon the selection. 
         [0032]    The pair of transistors  360  may be Field-Effect Transistors (FETs). The FETs  360  may be cross-coupled so that the source of transistor  362  is coupled to the gate of transistor  364  while the source of transistor  364  is coupled to the gate of transistor  362 . The drain of transistor  362  may be coupled to the drain of transistor  364 . The pair of FETs  360  may represent a gain cell. 
         [0033]    Inductor  370  may be coupled to the drains of both transistor  362  and transistor  364 . An opposite end of inductor  370  may be coupled to ground  380 . 
         [0034]    The model that describes the DCO for ideal capacitors can be described by an equation: 
         [0000]    
       
         
           
             
               f 
               DCO 
             
             = 
             
               
                 
                   ( 
                   
                     1 
                     + 
                     
                       tempCoeff 
                       · 
                       
                         
                           T 
                           - 
                           
                             T 
                             o 
                           
                         
                         
                           T 
                           o 
                         
                       
                     
                   
                   ) 
                 
                 x 
               
               
                 
                   
                     
                       
                         
                           1 
                           
                             f 
                             max 
                             2 
                           
                         
                         + 
                         
                           
                             ( 
                             
                               
                                 1 
                                 
                                   f 
                                   
                                     pvt 
                                     , 
                                     min 
                                   
                                   2 
                                 
                               
                               - 
                               
                                 1 
                                 
                                   f 
                                   max 
                                   2 
                                 
                               
                             
                             ) 
                           
                           · 
                           
                             pvt 
                             
                               pvt 
                               max 
                             
                           
                         
                         + 
                         
                           
                             ( 
                             
                               
                                 1 
                                 
                                   f 
                                   
                                     acq 
                                     , 
                                     min 
                                   
                                   2 
                                 
                               
                               - 
                               
                                 1 
                                 
                                   f 
                                   max 
                                   2 
                                 
                               
                             
                             ) 
                           
                           · 
                         
                       
                     
                   
                   
                     
                       
                         
                           acq 
                           
                             acq 
                             max 
                           
                         
                         + 
                         
                           
                             ( 
                             
                               
                                 1 
                                 
                                   f 
                                   
                                     tr 
                                     , 
                                     min 
                                   
                                   2 
                                 
                               
                               - 
                               
                                 1 
                                 
                                   f 
                                   max 
                                   2 
                                 
                               
                             
                             ) 
                           
                           · 
                           
                             tr 
                             
                               tr 
                               max 
                             
                           
                         
                       
                     
                   
                 
               
             
           
         
       
     
         [0035]    The values pvt, acq, and tr are received as described above. Respective frequency values f pvt,min , f acq,min , and f tr,min  are minimum frequencies respectively associated with the PVT, ACQ, and TR capacitor banks. The value f max  represents a maximum frequency. The values pvt max , acq max , and tr max  are the maximum values that the variables pvt, acq, and tr may take and are based upon the parameters of the respective PVT, ACQ, and TR capacitor banks. The x in the exponent represents the characteristic of the temperature dependency. In an exemplary embodiment, the capacitors may have a linear dependency from temperature where x=2. 
         [0036]    A temperature coefficient, tempCoeff, indicates the sensitivity of the output frequency versus temperatures. There is also a ratio of an ambient temperature T to a reference temperature T 0 . Based upon all of these parameters, the equation produces a DCO frequency, fDCO. 
         [0037]    This formula is a good description for the oscillator frequency when the capacitor banks provide good matching properties. If there is mismatch, then the contribution of each capacitor is expressed by the individual frequency change with reference to the maximum frequency. In this case, pvt i , acq i , trk are the values of each bit, which may be either one or zero. In this case, the equation is modified as set forth below: 
         [0000]    
       
         
           
             
               f 
               DCO 
             
             = 
             
               
                 
                   ( 
                   
                     1 
                     + 
                     
                       tempCoeff 
                       · 
                       
                         
                           T 
                           - 
                           
                             T 
                             o 
                           
                         
                         
                           T 
                           o 
                         
                       
                     
                   
                   ) 
                 
                 x 
               
               
                 
                   
                     
                       
                         
                           1 
                           
                             f 
                             max 
                             2 
                           
                         
                         + 
                         
                           
                             ∑ 
                             i 
                           
                            
                           
                             
                               ( 
                               
                                 
                                   1 
                                   
                                     f 
                                     
                                       pvt 
                                       , 
                                       min 
                                       , 
                                       i 
                                     
                                     2 
                                   
                                 
                                 - 
                                 
                                   1 
                                   
                                     f 
                                     max 
                                     2 
                                   
                                 
                               
                               ) 
                             
                             · 
                             
                               pvt 
                               i 
                             
                           
                         
                         + 
                         
                           
                             ∑ 
                             j 
                           
                            
                           
                             
                               ( 
                               
                                 
                                   1 
                                   
                                     f 
                                     
                                       acq 
                                       , 
                                       min 
                                       , 
                                       j 
                                     
                                     2 
                                   
                                 
                                 - 
                                 
                                   1 
                                   
                                     f 
                                     max 
                                     2 
                                   
                                 
                               
                               ) 
                             
                             · 
                           
                         
                       
                     
                   
                   
                     
                       
                         
                           acq 
                           j 
                         
                         + 
                         
                           
                             ∑ 
                             k 
                           
                            
                           
                             
                               ( 
                               
                                 
                                   1 
                                   
                                     f 
                                     
                                       tr 
                                       , 
                                       min 
                                       , 
                                       k 
                                     
                                     2 
                                   
                                 
                                 - 
                                 
                                   1 
                                   
                                     f 
                                     max 
                                     2 
                                   
                                 
                               
                               ) 
                             
                             · 
                             
                               tr 
                               k 
                             
                           
                         
                       
                     
                   
                 
               
             
           
         
       
     
         [0038]    This equation may also be expressed by ratios of the terms. In an ideal case the ratio between the terms 
         [0000]    
       
         
           
             
               ( 
               
                 
                   1 
                   
                     f 
                     
                       
                         
                           pvt 
                           / 
                           acq 
                         
                         / 
                         tr 
                       
                       , 
                       min 
                       , 
                       i 
                     
                     2 
                   
                 
                 - 
                 
                   1 
                   
                     f 
                     max 
                     2 
                   
                 
               
               ) 
             
              
             
                 
             
              
             and 
              
             
                 
             
              
             
               ( 
               
                 
                   1 
                   
                     f 
                     
                       
                         
                           pvt 
                           / 
                           acq 
                         
                         / 
                         tr 
                       
                       , 
                       min 
                       , 
                       
                         i 
                         + 
                         1 
                       
                     
                     2 
                   
                 
                 - 
                 
                   1 
                   
                     f 
                     max 
                     2 
                   
                 
               
               ) 
             
           
         
       
     
         [0000]    is 2. It is possible to either calculate the f do  frequency based on capacitor settings or find a configuration of capacitor settings for a certain f dco  frequency. 
         [0039]    The values for oscillator models may be taken from simulations or measurements. Input signals can represent frequencies from measurements or simulations which express the frequencies in the oscillator models. The representations may be counter states, capacitor values, or other parameters. 
         [0040]    The values for f max  and f pvt/acq/tr,min  may be measured and stored during either a boot phase of the system or during a product test phase. These values may also be simulation results or estimations. The values would subsequently be stored in a non-volatile memory. If measurement is done during the boot phase, there may be a measuring circuit in the system. Otherwise, the measurement may be done outside the system. 
         [0041]    During a calculation procedure, a certain fa dco  is selected so that the desired frequency is between two smallest possible steps of the TR bank. Any search algorithm may be used, such as a binary search algorithm. However, in case of mismatch issues such as large Integral-Non-Linearity (INL), a binary search algorithm may fail, causing the ADPLL system to get out of lock. In such cases, a linear search algorithm may be a safer algorithm. 
         [0042]    The search algorithm starts with a coarse bank looking for a setting so that the desired frequency is between two settings of a first bank with the coarsest resolution. It then steps to the next bank with finer resolution and repeats the process. The search may start either at a minimum frequency or a maximum frequency of the DCO, provided that the stepping is done monotonously. 
         [0043]    In pseudo-code, the algorithm can be written in the following manner: 
         [0000]    
       
         
               
             
           
               
                   
               
             
             
               
                 For pvt = 0:pvtmax 
               
               
                  if(fdco(pvt,0,0) &gt;= fdcotarget and fdco(pvt+1,0,0) &lt;= fdcotarget) 
               
               
                    pvtsel = pvt; 
               
               
                    break; 
               
               
                  end 
               
               
                 end 
               
               
                 For acq = 0:acqmax 
               
               
                   if(fdco(pvtsel,acq,0) &gt;= fdcotarget and fdco(pvtsel,acq+1, 0) &lt;= 
               
               
                 fdcotarget) 
               
               
                    acqsel = acq; 
               
               
                    break; 
               
               
                  end 
               
               
                 end 
               
               
                 For tr = 0:trmax 
               
               
                   if(fdco(pvtsel,acqsel,tr) &gt;= fdcotarget and fdco(pvtsel,acqsel, tr+1) &lt;= 
               
               
                 fdcotarget) 
               
               
                  trsel = tr; 
               
               
                    break; 
               
               
                  end 
               
               
                 end 
               
               
                   
               
             
          
         
       
     
         [0044]    Model values for PVT, ACQ, and TR can be calculated by using the pvt i ,acq i ,trk values and their respective weights: 
         [0000]    
       
         
           
             capbankvalue 
             = 
             
               
                 ∑ 
                 i 
               
                
               
                 
                   capbankvalue 
                   
                     
                         
                     
                      
                     i 
                   
                 
                 · 
                 
                   weight 
                   i 
                 
               
             
           
         
       
     
         [0045]    The value Capbankvalue=PVT, ACT, or TR, while weight i =2 i , for example. 
         [0046]    The order of bits, MSB or LSB, does not change the calculation. 
         [0047]    There may be process dependencies and deviations from the model in the ADPLL system that introduce errors. Compensating for such errors may require a second phase that functions as a learning phase. In this learning phase, differences between the value after settling of the system and the calculated value are stored. It may not necessary to store these differences for all frequencies. In lieu of storing all differences, the calculations may be done in large frequency intervals. Interpolation would be used to estimate the differences for frequencies between these intervals. In an ideal case, no correction would be necessary. 
         [0048]    Model values may be compensated to reflect a temperature offset between the ADPLL system at a reference temperature for the frequency at which the model values were determined and the actual temperature. Such compensation may be more accurate if a dependency between temperature and frequency is not expressed as a linear relationship. A second, third, or higher order polynomial function or another suitable approximation may be used. 
         [0049]    The implementation of the model may involve either a hardcoded design or a piece of software in a microprocessor. To ease implementation, it may be possible to use approximations like a Taylor series for the model. 
         [0050]    To further stabilize the device, the phase error of the phase detector and the TR value of the loop filter should be initially set to a neutral value. This neutral value may zero. This setting will discharge the loop filter, so that the loop only gets rid of a small phase or frequency offset. This may be done by the loop filter, which only has a TR bank output, thereby providing a difference between the calculated value and the necessary value. 
         [0051]    The model may also compensate for temperature drift of the ADPLL system. Capacitors may be exchanged between the TR bank and the ACQ bank if the TR bank is about to exceed a critical limit. If the temperature dependency of the oscillator is sufficiently large, the ACQ bank might also exceed a threshold. In that case, capacitors may be exchanged between the ACQ bank and the PVT bank. If the temperature of the system is known, new settings can be generated by the model and immediately applied. 
         [0052]    The model may also be used to sense temperatures. If the process spread is negligible and the frequency is only influenced by temperature, the model may measure the difference between the temperature at which the DCO was characterized and the actual temperature. 
         [0053]    For an analog PLL system, this method may be used for varactor tuning. In this case, tuning voltages may be added to the model in addition to the capacitor bank settings. The model may compensate for the accuracy of the tuning voltages. 
         [0054]      FIG. 4  illustrates an improved tuning diagram for a ADPLL. Unlike the prior art tuning diagram illustrated in  FIG. 1 , locking of the ADPLL may occur without any settling phase in  FIG. 4 . 
         [0055]      FIG. 5  illustrates a second embodiment of an improved ADPLL  500 . 
         [0056]    ADPLL  500  includes a digitally-controlled oscillator (DCO) model device  510 , a ramp generator  520 , a filter  530 , a TDC  540 , a divider  550 , and a DCO  560 . These units are described in further detail below. 
         [0057]    The DCO model device  510  receives a Frequency Control Word (FCW) signal as input. Based upon the received FCW signal, it produces PVT, ACQ, and TR calibration signals. The DCO model device  510  also forwards a copy of the FCW signal to an adder of the frequency to phase converter  520 . The DCO model device  510  may be implemented using a processor running instructions. 
         [0058]    The ramp generator  520  receives a combination of the FCW signal from the DCO model device  510  and a feedback phase signal as an input signal. Ramp enerator  520  then samples this input signal with reference frequency f ref  and, in this way, generates a reference phase, φ ref . In particular, ramp generator  520  may generate the reference phase φ ref  by integrating the FCW signal over time. This happens by adding the FCW signal to the content of the register during each f ref  cycle. 
         [0059]    Filter  530  receives, at an adder, a combination of the reference phase, φ ref , and a feedback signal, φ v , as an input signal. It compares this input signal to the reference frequency f re f to produce PVT, ACQ, and TR signals as output. 
         [0060]    The time-to-digital converter (TDC)  540  receives a signal from the DCO  260  as input. This received signal may be a local oscillator (LO) signal. It then /compares this input signal to the reference frequency f ref  to produce output phf f . 
         [0061]    The divider  550  receives the LO signal from the DCO  260  as input and produces phf i  as output. The combination of phf f  and phf i  results in φ v . 
         [0062]    The DCO  560  receives PVT, ACQ, and TR signals that combine the PVT, ACQ, and TR signals from filter  530  with the PVT, ACQ, and TR signals from DCO model device  510 . DCO  560  is an inductive-capacitive (LC) oscillator that is controlled by a plurality of capacitor banks. The capacitor banks may include a PVT bank, an ACQ bank, and a TR bank. Based upon the PVT, ACQ, and TR signals, DCO  560  produces the LO signal as output. The DCO  560  may operate like the DCO  300  depicted in  FIG. 3   
         [0063]    In this embodiment, the filter compensates for differences between calculated and optimal values of the PVT, ACQ, and TR capacitor banks. Both the phase error and the loop filter content may be reset to zero, thereby providing a discharge function when applying the estimated values for each bank 
         [0064]    The accuracy of this method may be improved during operation by a learning procedure. If previously used values are stored in the model for subsequent use, the lock time can be reduced to zero. This method may also be improved by interpolation between known values. If the mismatch properties of the PVT, ACQ, and TR banks are known, calibration signals may also compensate for the known mismatches. 
         [0065]    When switching between a certain number of known frequencies, e.g., two known frequencies, a settling time will be used only once for determination of each setting. The determined settings may then be stored. The stored settings may subsequently be used to tune between these frequencies, eliminating any additional settling time. 
         [0066]    It should be noted that various aspects of the above embodiments may be combined resulting in other embodiments. Also, various steps in the methods may be performed in a different order or simultaneously. Also various aspects of the embodiments above may be implemented using processors and computer instructions to result in a specific machine implementing the embodiment. Also, portions of the embodiments above may be implemented using ASICs or other specific hardware elements. 
         [0067]    As used herein, the term “processor” will be understood to encompass a variety of devices such as microprocessors, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and other similar processing and computing devices. 
         [0068]    Other embodiments that use wireless power capabilities between a transaction terminal and mobile device powered by the wireless power in order to complete a transaction are envisioned. 
         [0069]    It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. 
         [0070]    Although the various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects thereof, it should be understood that the invention is capable of other embodiments and its details are capable of modifications in various obvious respects. As is readily apparent to those skilled in the art, variations and modifications can be effected while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in any way limit the invention, which is defined only by the claims.