Abstract:
Embodiments of the disclosed technical solution provides a shift register unit circuit which operates based on two clock signals and comprises input terminals, a pre-charging circuit, a level pulling-down circuit, a outputting circuit and a scan signal output terminal. Embodiments of the disclosed technical solution also provides a shift register having at least two shift register unit circuits connected in cascade, and further provides a liquid crystal display array substrate and a liquid crystal display. The disclosed technical solution stabilizes the wave output from the scan signal output terminal and has small noise by means of a design of pulling down the level, and may realize the GOA circuit utilizing less TFTs circuits, so that the circuit structure is simple and power consumption is small.

Description:
BACKGROUND 
       [0001]    A disclosed technical solution relates to a shift register unit circuit, a shift register, an array substrate and a liquid crystal display. 
         [0002]    The liquid crystal display is a plane display which employs glass substrate as the substrate, and forms color film structure or TFT circuit structure on the glass substrate. In order not to increase any process and manufacture cost, a manufacture process for forming TFTs (Thin Film Transistor) in a pixel circuit is employed to manufacture a driving circuit to make the pixel circuit and the driving circuit on a same substrate only by designing a GOA (Gate driver IC On Array) circuit (for example, a principle view of the shift register unit circuit in the GOA circuit as shown in  FIG. 1 ). In this case, a best scenario is to use transistors such as TFTs to form the driving circuit including the shift register so as to reduce the manufacture costs. However, in prior art, the shift register unit circuit formed by the transistors has a disadvantage of high power consumption due to too many TFTs used in the circuit; further, there are problems that a gate driving output of the shift register is not stable and has many burrs. 
       SUMMARY 
       [0003]    For the above problems, the disclosed technical solution provides a shift register unit circuit, shift register, array substrate and liquid crystal display which may have low power consumption and output a stable gate scan signal. 
         [0004]    According to an embodiment, the shift register unit circuit comprises: 
         [0005]    input terminals including a start signal input terminal, a first clock signal input terminal and a second clock signal input terminal; 
         [0006]    a pre-charging circuit for outputting a turn-on level in response to an enable level of a start signal and of a first clock signal, and keeping the turn-on level being output during one clock period of the first clock signal; 
         [0007]    a level pulling-down circuit for pulling down a level at an output terminal of the pre-charging circuit and outputting a low level in response to the enable level of the second clock signal, and for output a high level in response to a disable level of the second clock signal, after the turn-on level is input; and for outputting the high level after the turn-on level is turned off; 
         [0008]    an outputting circuit, which is coupled to the output terminal of the level pulling-down circuit, for pulling down a level at an output terminal of the outputting circuit and outputting the low level in response to the high level output from the level pulling-down circuit, and for outputting the high level in response to the low level output from the level pulling-down circuit; and 
         [0009]    a scan signal output terminal, which is coupled to the output terminal of the outputting circuit, for outputting a scan signal. 
         [0010]    The level pulling-down circuit comprises a first level pulling-down circuit and a second level pulling-down circuit, wherein: 
         [0011]    the first level pulling-down circuit pulls down the level at the output terminal of the pre-charging circuit and outputs the pulled-down low level, after the turn-on level is input; and outputs the high level after the turn-on level is turned off; 
         [0012]    the second level pulling-down circuit outputs the low level in response to the enable level of the second clock signal, and outputs the high level in response to the disable level of the second clock signal, when the first level pulling-down circuit outputs the pulled-down low level; and the second level pulling-down circuit outputs the high level when the first level pulling-down circuit outputs the high level. 
         [0013]    Furthermore, the shift register unit circuit may comprises a feedback circuit for feeding the scan signal output via the output terminal back to the output terminal of the level pulling-down circuit so as to stabilize the output scan signal. 
         [0014]    In a detail implementation, the pre-charging circuit comprises a first switch, a first node and a capacitor, wherein: 
         [0015]    a gate of the first switch is connected to the first clock signal, a drain thereof is connected to the start signal, and a source thereof is coupled to the first node; 
         [0016]    the first node is a turn-on level output terminal of the pre-charging circuit; and 
         [0017]    one terminal of the capacitor is coupled to the first node, and the other terminal is coupled to the low level. 
         [0018]    In a detailed implementation, the first level pulling-down circuit comprises a second switch, a second node and a third switch, wherein: 
         [0019]    a gate and a drain of the second switch are coupled to each other, the drain thereof is connected to the high level, and a source thereof is coupled to the second node; 
         [0020]    the second node is the output terminal of the first level pulling-down circuit; 
         [0021]    a gate of the third switch is connected to the turn-on level output terminal of the pre-charging circuit, a drain thereof is coupled to the second node, and a source thereof is connected to the low level. 
         [0022]    In a detailed implementation, the second level pulling-down circuit comprises a fourth switch, a third node and a fifth switch, wherein: 
         [0023]    a gate of the fourth switch is connected to the second clock signal, a drain thereof is coupled to the output terminal of the first level pulling-down circuit, and a source thereof is coupled to the third node; 
         [0024]    the third node is the output terminal of the second level pulling-down circuit; 
         [0025]    a gate and a drain of the fifth switch are coupled to each other, the drain thereof is connected to the high level, and a source thereof is coupled to the third node. 
         [0026]    In a detailed implementation, the outputting circuit comprises a sixth switch and a seventh switch, wherein: 
         [0027]    a gate and a drain of the sixth switch are coupled to each other, the drain thereof is connected to the high level, and a source thereof is coupled to the scan signal output terminal; 
         [0028]    a gate of the seventh switch is coupled to the output terminal of the second level pulling-down circuit, a drain thereof is coupled to the scan signal output terminal, and a source thereof is connected to the low level. 
         [0029]    In a detailed implementation, the feedback circuit comprises a eighth switch, a fourth node and a ninth switch, wherein: 
         [0030]    a gate and a drain of the eighth switch are coupled to each other, the drain thereof is connected to the high level, and a source thereof is coupled to the fourth node; 
         [0031]    the fourth node is a feedback output terminal of the feedback circuit and is coupled to the output terminal of the level pulling-down circuit; 
         [0032]    a gate of the ninth switch is coupled to the scan signal output terminal, a drain thereof is coupled to the fourth node, and a source thereof is connected to the low level. 
         [0033]    According to an embodiment, the shift register includes at least two shift register unit circuits connected in cascade, wherein each of the shift register unit circuit operates based on two clock signals and is any one of the above-described shift register unit circuit. 
         [0034]    According to an embodiment, there is provided a liquid crystal display array substrate on which a GOA circuit is disposed, and the shift register in the GOA circuit is the above-described shift register. 
         [0035]    According to an embodiment, there is provided a liquid crystal display, which comprises a liquid crystal display array substrate as described above. 
         [0036]    The disclosed technical solutions have advantageous effects as follows. 
         [0037]    a) Less TFTs (thin film transistor) are used in the shift register unit circuit to realize the GOA circuit, therefore the circuit structure is simple and power consumption is reduced clearly. 
         [0038]    b) A design of pulling down the level is utilized, so that the gate scan signal output from the shift register is stable and has small noise. 
         [0039]    c) The signal output from the shift register is further stabilized and has smaller noise by adding one feedback circuit. 
         [0040]    d) The shift register is suitable for the requirements of GOA circuit including TFTs which utilize LTPS (Low Temperature Poly-silicon) as an active layer, and is also suitable for the GOA circuit including TFTs which utilize amorphous silicon (a-Si) as the active layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0041]      FIG. 1  is a basic principle diagram of a shift register unit circuit in a GOA circuit; 
           [0042]      FIG. 2  is a schematic view of the shift register unit circuit according to an Embodiment 1 of the disclosed technical solution; 
           [0043]      FIG. 3  is a schematic view of the shift register unit circuit according to an Embodiment 2 of the disclosed technical solution; 
           [0044]      FIG. 4  is a timing diagram of the Embodiment 1 of the disclosed technical solution; 
           [0045]      FIG. 5  is a schematic view illustrating a structure of a shift register according to the embodiment of the disclosed technical solution; and 
           [0046]      FIG. 6  is a schematic view illustrating a process for outputting gate scan signals line-by-line from top to bottom in the shift register according to the embodiment of the disclosed technical solution. 
       
    
    
     DETAILED DESCRIPTION 
       [0047]    Below detailed implementations of the disclosed technical solution will be described in further details in connection with the accompanying drawings. 
         [0048]      FIG. 2  illustrates a principle view of a shift register unit circuit according to one embodiment of the disclosed technical solution. The shift register unit circuit comprises: input terminals, a pre-charging circuit  1 , a level pulling-down circuit  200 , an outputting circuit  4  and a scan signal output terminal  7 , wherein: 
         [0049]    the input terminals includes a start signal input terminal  61 , a first clock signal input terminal  62  and a second clock signal input terminal  63 ; 
         [0050]    the pre-charging circuit  1  outputs a turn-on level in response to an enable level of a start signal and of a first clock signal, and keeps the turn-on level being output during one clock period of the first clock signal; 
         [0051]    the level pulling-down circuit  200  pulls down a level at an output terminal of the pre-charging circuit and outputs a low level in response to the enable level of the second clock signal, and outputs a high level in response to a disable level of the second clock signal, after the turn-on level is input; and outputs the high level after the turn-on level is turned off; 
         [0052]    the outputting circuit  4  which is coupled to the output terminal of the level pulling-down circuit  200 , pulls down a level at an output terminal of the outputting circuit  4  and outputs the low level in response to the high level output from the level pulling-down circuit  200 , and outputs the high level in response to the low level output from the level pulling-down circuit  200 ; and 
         [0053]    the scan signal output terminal  7  is coupled to the output terminal of the outputting circuit  4 , and outputs a scan signal. 
         [0054]    As a further embodiment of the disclosed technical solution, in order to make the scan signal output from the shift register unit circuit stable and having less burrs, the level pulling-down circuit  200  comprises a first level pulling-down circuit  2  and a second level pulling-down circuit  3 , wherein: 
         [0055]    the first level pulling-down circuit  2  pulls down the level at the output terminal of the pre-charging circuit  1  and outputs the pulled-down low level from the output terminal (a node B as shown in the  FIG. 2 ) of the first level pulling-down circuit  2  after the turn-on level is input; and outputs the high level after the turn-on level is turned off; 
         [0056]    the second level pulling-down circuit  3  outputs the low level from the output terminal (a node QB as shown in the  FIG. 2 ) of the second level pulling-down circuit  3  in response to the enable level of the second clock signal, and outputs the high level in response to the disable level of the second clock signal, when the first level pulling-down circuit  2  outputs the pulled-down low level; and the second level pulling-down circuit  3  outputs the high level from the output terminal thereof when the first level pulling-down circuit  2  outputs the high level. 
         [0057]    As a further embodiment of the disclosed technical solution, in order to make the scan signal output from the shift register unit circuit stable and having less burrs, the shift register unit circuit further comprises a feedback circuit  5  for feeding the scan signal output via the scan signal output terminal  7  back to the output terminal of the level pulling-down circuit  200  so as to stabilize the output scan signal, as shown in  FIG. 3 . 
         [0058]    In the disclosed technical solution, the enable level is a high level, and the disable level is a low level. 
         [0059]    Below the shift register unit circuit will be described in further details in connection with the detailed embodiments. 
       Embodiment 1 
       [0060]      FIG. 2  illustrates a shift register unit circuit according to an embodiment of the disclosed technical solution, and all of switches T 1 -T 7  in this embodiment are TFTs (Thin Film Transistor). As can be seen from the  FIG. 2 , the pre-charging circuit  1  comprises a first switch T 1 , a first node A and a capacitor C. A gate of the first switch T 1  is connected to a first clock signal CKB, a drain thereof is connected to a start signal (the start signal may be a STV signal or a level signal output from the shift register unit circuit in the last stage), and a source thereof is coupled to the first node A; the first node A is a turn-on level output terminal of the pre-charging circuit  1 ; and one terminal of the capacitor C is coupled to the first node A, and the other terminal is coupled to a low level V SS . 
         [0061]    The first level pulling-down circuit  2  comprises a second switch T 2 , a second node B and a third switch T 3 . A gate and a drain of the second switch T 2  are coupled to each other, the drain thereof is connected to a high level Vdd, and a source thereof is coupled to the second node B. The second node B is the level output terminal of the first level pulling-down circuit  2 . A gate of the third switch T 3  is connected to the turn-on level output terminal of the pre-charging circuit  1 , a drain thereof is coupled to the second node B, and a source thereof is connected to the low level V SS . 
         [0062]    The second level pulling-down circuit  3  comprises a fourth switch T 4 , a third node QB and a fifth switch T 5 . A gate of the fourth switch T 4  is connected to a second clock signal CK, a drain thereof is coupled to the level output terminal of the first level pulling-down circuit  2 , and a source thereof is coupled to the third node QB. The third node QB is the output terminal of the second level pulling-down circuit  3 . A gate and a drain of the fifth switch T 5  are coupled to each other, the drain thereof is connected to the high level V dd , and a source thereof is coupled to the third node QB. 
         [0063]    The outputting circuit  4  comprises a sixth switch T 6  and a seventh switch T 7 . A gate and a drain of the sixth switch T 6  are coupled to each other, the drain thereof is connected to the high level V dd , and a source thereof is coupled to the scan signal output terminal V out . A gate of the seventh switch T 7  is coupled to the output terminal of the second level pulling-down circuit  3 , a drain thereof is coupled to the scan signal output terminal V out , and a source thereof is connected to the low level V SS . 
         [0064]      FIG. 4  illustrates an operating timing diagram of the embodiment. As shown in the figure, the above-described circuit is operated under the first clock signal CKB and the second clock signal CK which are input differentially. That is to say, the first clock signal CKB and the second clock signal CK are input differentially, therefore the second clock signal CK is at the low level when the first clock signal CKB is at the high level, while the second clock signal CK is at the high level when the first clock signal CKB is at the low level, and the first clock signal CKB and the second clock signal CK have a same clock period. 
         [0065]    At time period t 0 ˜t 1  in the  FIG. 4 , the first clock signal CKB outputs the low level, and the second clock signal CK outputs the high level. At this time, the first switch T 1  is turned off, the start signal such as STV coupled to the first switch T 1  outputs the low level, that is, the node A outputs the low level. When the node A outputs the low level, the third switch T 3  is turned off and the node B outputs the high level. Then the fourth switch T 4  is turned on, while the fifth switch T 5  is also turned on, and the node QB outputs the high level. When the node QB outputs the high level, the seventh switch T 7  is turned on and the scan signal output terminal V out  outputs the low level. 
         [0066]    At time period t 1 ˜t 2  in the  FIG. 4 , the first clock signal CKB outputs the high level, and the second clock signal CK outputs the low level. At this time, the first switch T 1  is turned on, the start signal (STV) outputs the high level, and therefore the node A outputs the high level and at the same time the capacitor C is charged. The third switch T 3  is turned on and the node B outputs the low level, when the node A outputs the high level; the fourth switch T 4  is turned off, the fifth switch T 5  is turned on, and the node QB outputs the high level; when the node QB is at the high level, the seventh switch T 7  is turned on and the scan signal output terminal V out  outputs the low level. 
         [0067]    At time period t 2 ˜t 3  in the  FIG. 4 , the first clock signal CKB outputs the low level, and the second clock signal CK outputs the high level. At this time, the start signal outputs the low level and the charging of the capacitor C stops. The capacitor C starts to discharge, and the node A maintains to be at the high level until the discharging of the capacitor C is completed (that is, the time t 3  in the figure). When the node A outputs the high level, the third switch T 3  is turned on so that the high level output from the node A is pulled down for the first time and outputted, that is, the node B outputs the low level. At this time, the second clock signal CK outputs the high level so as to turn on the fourth switch T 4 , while the fifth switch T 5  is turned on; since the voltage division on T 5  is bigger than that on T 4  by setting the width/length ratio of the channel of the T 4  and T 5 , the node QB still outputs the low level; when the node QB is at the low level, the seventh switch T 7  is turned off and the scan signal output terminal V out  outputs the high level. 
         [0068]    At time period t 3 ˜t 4  in the  FIG. 4 , the first clock signal CKB outputs the high level, and the second clock signal CK outputs the low level. The switch T 1  is turned on since the first clock signal CKB outputs the high level, but the start signal coupled to the drain of the first switch T 1  outputs the low level and the discharging of the capacitor C is completed, therefore the node A outputs the low levels. When the node A is at the low level, the third switch T 3  is turned off so that the node B outputs the high level. As the second clock signal CK outputs the low level, the fourth switch T 4  is turned off. While the fifth switch T 5  is turned on, the node QB outputs the high level, and the seventh switch T 7  is turned on so that the scan signal output terminal V out  outputs the low level. 
         [0069]    After time t 4 , the scan signal output terminal V out  would always outputs the low level as long as the start signal does not output the high level, regardless how the first clock signal CKB and the second clock signal CK change. When the start signal outputs the high level again, the above-described shift register unit circuit would repeat the operation timing from t 0  again. 
       Embodiment 2 
       [0070]      FIG. 3  illustrates a shift register unit circuit according to another embodiment of the disclosed technical solution. This embodiment adds a feedback circuit  5  on the basis of Embodiment 1, wherein the feedback circuit  5  feeds the scan signal output via the scan signal output terminal V out  back to the output terminal (namely, at the node QB in the  FIG. 3 ) of the second level pulling-down circuit  3 , in order to stabilize the outputted scan signal. As shown in  FIG. 3 , the feedback circuit  5  comprises a eighth switch T 8 , a fourth node D and a ninth switch T 9 . Wherein a gate and a drain of the eighth switch T 8  are coupled to each other, the drain thereof is connected to the high level V dd , and a source thereof is coupled to the fourth node D. The fourth node D is a feedback output terminal of the feedback circuit  5  and is coupled to the output terminal of the second level pulling-down circuit  3 . A gate of the ninth switch T 9  is coupled to the scan signal output terminal, a drain thereof is coupled to the fourth node D, and a source thereof is connected to the low level V SS . 
         [0071]    Its operation principle is as follows. When V out  outputs the high level, the ninth switch T 9  is turned on, the fourth node D outputs the low level, and the low level output from the fourth node D is fed back to the node QB in  FIG. 3 , so that the low level output from the node QB is more stable and in turn the high level output from the scan signal output terminal V out  is more stable. When V out  outputs the low level, the ninth switch T 9  is turned off, the fourth node D is at the high level, and the high level output from the fourth node D is fed back to the node QB in  FIG. 3  so as to stabilize the high level output from the node QB, and in turn the low level output from the scan signal output terminal V out  is more stable. 
         [0072]    As shown in  FIG. 5 , the shift register comprises multiple stages of the shift register units S 1 , S 2 , . . . , S n , wherein respective stages of the shift register units generate their scan signals at respective output terminals (OUT 0 , OUT 1 , OUT 2 , . . . OUT n ). The shift register unit at each stage has a first clock input port CKB, a second clock input port CK, a start signal input port, a reset signal input port RT and a scan signal output port OUT n . All of the shift register units at respective stages utilize the shift register unit circuits with the above-described circuit structure. Wherein, 
         [0073]    In the shift register unit S 1  at the first stage, the start signal STV is input to its start signal input port, the first clock signal is input to its first clock input port, the second clock signal is input to its second clock input port, and its reset signal input port is connected to the scan signal output port of the shift register unit at the next stage; 
         [0074]    In the shift register unit S 2  at a stage just next to the first stage, a scan signal output from the shift register unit S 1  at the first stage is input to a start signal input port of the shift register unit S 2 , the second clock signal is input to its first clock input port, the first clock signal is input to its second clock input port, and its reset signal input port is connected to the scan signal output port of the shift register unit at the next stage; 
         [0075]    The rest can be done in the same way until the shift register unit S n , and for a shift register unit S n  which is connected in cascade at the last stage, no reset signal is needed to be input. 
         [0076]    It is noted that, in the shift register unit S n  where n is an odd number, the first clock signal should be input to its first clock input port and the second clock signal should be input to its second clock input port. Instead, in the shift register unit S n  where n is an even number, the second clock signal should be input to its first clock input port and the first clock signal should be input to its second clock input port. 
         [0077]    As shown in  FIG. 6 , the shift register operates under two clocks and outputs the gate scan signals line-by-line from top to bottom. 
         [0078]    A liquid crystal display array substrate according to an embodiment of the disclosed technical solution has a GOA circuit disposed on it, a shift register of the GOA circuit has a structure including at least two shift register unit circuits connected in cascade (as shown in  FIG. 5 ) and operates based on two-phase clock signal. Wherein, the shift register unit circuit comprises: 
         [0079]    input terminals including a start signal input terminal, a first clock signal input terminal and a second clock signal input terminal; 
         [0080]    a pre-charging circuit for outputting a turn-on level in response to an enable level of a start signal and of a first clock signal, and keeping the turn-on level being output during one clock period of the first clock signal; 
         [0081]    a level pulling-down circuit for pulling down a level at an output terminal of the pre-charging circuit and outputting a low level in response to the enable level of the second clock signal, and for output a high level in response to a disable level of the second clock signal, after the turn-on level is input; 
         [0082]    an outputting circuit for inverting the level output from the level pulling-down circuit and outputting it; and 
         [0083]    a scan signal output terminal, which is coupled to the output terminal of the outputting circuit, for outputting a scan signal. 
         [0084]    In a liquid crystal display array substrate according to an embodiment of the disclosed technical solution, the level pulling-down circuit comprises a first level pulling-down circuit and a second level pulling-down circuit, wherein: 
         [0085]    the first level pulling-down circuit pulls down the level at the output terminal of the pre-charging circuit and outputs the pulled-down low level after the turn-on level is input; and outputs the high level after the turn-on level is turned off; 
         [0086]    the second level pulling-down circuit outputs the low level in response to the enable level of the second clock signal, and outputs the high level in response to the disable level of the second clock signal, when the first level pulling-down circuit outputs the low level; and the second level pulling-down circuit outputs the high level when the first level pulling-down circuit outputs the high level. 
         [0087]    In a liquid crystal display array substrate according to an embodiment of the disclosed technical solution, the shift register unit circuit may further comprises a feedback circuit for feeding the scan signal output via the scan signal output terminal back to the output terminal of the level pulling-down circuit so as to stabilize the output scan signal. 
         [0088]    The shift register unit circuit integrated on the liquid crystal display array substrate according to an embodiment of the disclosed technical solution may be the circuit having the structures as described in the above Embodiment 1 and Embodiment 2. 
         [0089]    A liquid crystal display according to an embodiment of the disclosed technical solution comprises a liquid crystal display array substrate having the above-described structure. 
         [0090]    The above are only exemplary embodiments of the disclosed solution, but the scope sought for protection is not limited thereto. Instead, any or all modifications or replacements as would be obvious to those skilled in the art are intended to be included within the scope of the present invention. Therefore, the scope of the present invention is defined in the appended claims.