Abstract:
A sigma-delta converter having dynamic dithering that reduces or removes idle-channel tones and increase linearity of the converter. The dither is differentiated in multiple orders before being applied to the converter quantizer. The differentiation order and the amplitude of the dither are determined dynamically based on the input signal amplitude in order to obtain the most effectiveness of dithering. The dynamic dither can be used in both analog-to-digital and digital-to-analog converters.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to sigma-delta converters, including those adapted for use in audio applications.  
       BACKGROUND OF THE INVENTION  
       [0002]     Idle-channel tones exist in sigma-delta converters. In audio applications, the idle-channel tones can cause unpleasant noise detectable by the human ear. Dithering is the most popular method to reduce the idle-channel tones. One effective dithering method is to add a noise-shaped random series, called dither, in such a way that the dither transfer function is the same as the quantization noise transfer function. A sigma-delta modulator having generalized conventional dither is shown at  10  in  FIG. 1 . X(n) and y(n) are the input and output, respectively, of the modulator  10 . G(z) is the feedforward Z transfer function, and H(z) is the feedback transfer function of the modulator. A pseudorandom series dither d(n) is added to the input of the quantizer.  
         [0003]     From literature and simulations, the dithering amplitude must be big enough to remove the idle-channel tones. For example, an 1-bit quantizer, δ/Δ&gt;0.5, where δ is the peak-to-peak range of the dither, and Δ is the quantizer interval. When a fixed-amplitude of dither is applied all the time, the dithering is referred as static dithering. When adding a static dither to a modulator, the noise and distortion characteristics for large input signals are adversely affected. Noise floor of the sigma-delta modulator  10  may increase by several decibels. With static dither, when the input signal is approaching full scale, sigma-delta modulators have reduced dynamic range or dynamic range penalty. To avoid this effect, a dynamic dither that decreases its power when input level increases is preferred.  
         [0004]      FIG. 2  shows a prior-art dynamic dither scheme at  20 . The input  22  can be an analog signal for an analog-to-digital converter (ADC), or a digital signal for a digital-to-analog converter (DAC). A coarse input power level estimator  24  determines how much of the dither signal d(n) will be adjusted based on the input level of input  22 . A quantizer Q, shown at  26 , has an output fed back to form the negative-feedback loop. Dither signal d(n) is a random number series. Signal d′(n), which is proportional to dither d(n), can be digital for a DAC or analog for an ADC, and is determined by the output of the coarse input power level estimator  24  and dither d(n). In one example, if the input at  22  is idle or very small, signal d′(n) has a big amplitude, and it will attenuate with the input signal increase. Thus, this dither method  20  is called dynamic dithering. The attenuation factor is normally the function of the input amplitude. For example, (1−|x(n)| α ), where α=¼.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention achieves technical advantages as a sigma-delta converter having dynamic dithering that reduces or removes idle-channel tones and increases linearity of the converter. The dither is differentiated in multiple orders before being applied to the quantizer of the converter. The differentiation order and the amplitude of the dither are determined dynamically based on the input signal amplitude in order to obtain the most effectiveness of dithering. The dynamic dither can be used in both analog-to-digital and digital-to-analog converters.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  is a diagram of a conventional sigma-delta converter having static dithering;  
         [0007]      FIG. 2  is a diagram of a conventional sigma-delta converter having dynamic dithering;  
         [0008]      FIG. 3  is a diagram of one embodiment of the invention including a sigma-delta converter having differentiated dynamic dithering;  
         [0009]      FIG. 4  is a FFT plot of idle-channel noise of a converter without dither;  
         [0010]      FIG. 5  is a FFT plot of idle-channel noise of a converter with dither gain adjusted according to the input signal level;  
         [0011]      FIG. 6  is a FFT plot of idle-channel noise dither for one embodiment of the present invention;  
         [0012]      FIG. 7  is a plot of simulated signal-to-noise-and-distortion (SNDR) versus input signal amplitude; and  
         [0013]      FIG. 8  is a plot of SNDR versus input level plots for the dithers in Table 1.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0014]     Although a dynamic dither with uniformly distributed pseudorandom numbers is good enough for many applications, the present invention achieves technical advantages by providing more randomness of the pseudorandom numbers obtained by differentiating the uniformly distributed pseudorandom numbers. At the same time, this differentiation performs a noise shaping function (high-pass) to the dither, thus reducing the dither&#39;s noise power in signal-band. Thus, the differentiated dither generates an even better signal to noise ratio when the modulator is idle or with very small input amplitudes. The differentiation order of the dither can also be dynamically adjusted in order to get optimal signal-to-noise performance.  
         [0015]     Referring to  FIG. 3  there is shown a differentiated dynamic dithering scheme in a sigma-delta converter  30  according to one preferred embodiment of the invention. The converter  30  can be a DAC or an ADC. In the embodiment of  FIG. 3 , a pseudorandom generator  32  generates a uniformly distributed random number series. A peak detector  34  determines how big the input amplitude is relative to a full-scale input. For a DAC converter, the peak detector is conveniently placed to receive the digital input signal provided at input  36 . For an ADC converter, it is more convenient to place the peak detector  34  after a quantizer Q, shown at  38 , and a SINC filter (not shown) to get the amplitude represented digitally with reasonable short delay to apply dither soon enough.  
         [0016]     Based on the input level of the digital input signal at input  36 , the peak detector  34  sends a signal to a variable gain amplifier  40  to responsively set the dither signal d(n) amplitude as a function thereof. Advantageously, variable gain amplifier  40  also sends a signal  42  to a multiplexer  44  to responsively choose and establish a differentiation order. Every differentiator  46  has a transfer function of (1−z −1 )*0.5, which makes its output have the same peak-to-peak range as its input. Differentiator — 1&#39;s output connects to the input of the Differentiator — 2, the output of Differentiator — 2 connects to the input of the next Differentiator, and so on. All of the different outputs of differentiators  46  are connected to the multiplexer  44 . The multiplexer&#39;s output d′(n) is added into the output of the filter  48 , as shown. If the converter  30  is a DAC, then output d′(n) is a digital value. If the converter  30  is an ADC, then output d′(n) is an analog signal. The quantizer Q generates the converter output at  50 , which output  50  is fed back to the converter input to form a negative-feedback loop. An unlimited number of differentiators may be used in theory, but for minimal cost of silicon, a limited number of differentiators or differentiation order is chosen as desired. The number of the differentiation order, and the variable gain, are optimized given the order of the sigma-delta converter and the quantizer architecture.  
         [0017]     To simulate the dynamic dithering shown in  FIG. 2 , the gain is adjusted as in Table 1 below, and signal d′(n) is always equal to d(n).  
                           TABLE 1                                   INPUT AMPLITUDE RELATIVE               TO FULL-SCALE   GAIN                           (−∞˜−30 dB)   1           [−30 dB, −24 dB)   ½           [−24 dB, −18 dB)   ¼           [−18 dB, −12 dB)   1/8           [−12 dB, −6 dB)   1/16           [−6 dB, 0 dB)   1/32           [0 dB, +∞)   0                      
 
         [0018]     Referring now to Table 2 below there is shown a dynamic differentiation order and gain based on input amplitude according to one embodiment of the present invention.  
                       TABLE 2                       INPUT AMPLITUDE RELATIVE       DIFFERENTIATION       TO FULL-SCALE   GAIN   ORDER                   (−∞˜−90 dB)   2   3       [−90 dB, −30 dB)   1   0       [−30 dB, −24 dB)   1/2   0       [−24 dB, −18 dB)   1/4   0       [−18 dB, −12 dB)   1/8   0       [−12 dB, −6 dB)   1/16   0       [−6 dB, 0 dB)   1/32   0       [0 dB, +∞)   0   0                  
 
         [0019]      FIG. 4  shows at  60  an idle-channel noise FFT plot for a second-order nine-level sigma-delta DAC with a sampling frequency of 4.8 MHz without dither. The DAC input is a short-time sine wave followed by long-time  0 . Tones are apparent.  
         [0020]      FIG. 5  shows at  70  the same DAC with the prior-art dither of Table 1 (dither gain is adjusted according to the input signal level). The tones are effectively removed.  
         [0021]      FIG. 6  shows at  80  the same DAC with new dither in Table 2 according to one embodiment of the present invention. When the input level is lower than −90 dBFS (meaning dB relative to Full-Scale), the differentiation order is set to 3 and the dither gain is set to 2. When the input level is higher than −90 dBFS, the differentiation order is 0 and the gain is set to the same as the prior-art dither. The differentiation order can be set to 1 or 2 instead of 0 when the input increases, and the gain needs to be set accordingly to get close to optimal result. The dithers in Table 1 and Table 2 are both effective to remove idle-channel tones. However, the new dither according to the present invention is better than the prior-art dither because the tones appearing at the high frequency range is several dB lower.  
         [0022]      FIG. 7  shows at  90  a plot of simulated Signal-to-Noise-and-distortion (SNDR) versus input amplitude level. When the input level is lower than −90 dBFS, SNDR for the new dither (Table 2), shown at  94 , is consistently several dB higher than the prior-art dither (Table 1), shown at  92 , and is the same when the input level is higher than −90 dBFS.  
         [0023]     Since higher SNDR can be obtained at low input levels when the differentiation order is set high, the differentiation order can be always set to high as in Table 3.  
                             TABLE 3                           Fixed Differentiation Order            INPUT AMPLITUDE RELATIVE       DIFFERENTIATION       TO FULL-SCALE   GAIN   ORDER               −∞˜−90 dB   2   3       [−90 dB, −30 dB)   1   3       [−30 dB, −24 dB)   1/2   3       [−24 dB, −18 dB)   1/4   3       [−18 dB, −12 dB)   1/8   3       [−12 dB, −6 dB)   1/16   3       [−6 dB, 0 dB)   1/32   3       [0 dB, +∞)   0   3                  
 
         [0024]     The differentiation order can also be adjusted gradually from high to low as in Table 4.  
                             TABLE 4                           More Dynamic Differentiation Orders and Gains            INPUT AMPLITUDE RELATIVE       DIFFERENTIATION       TO FULL-SCALE   GAIN   ORDER               (−∞˜−72 dB)   2   3       [−72 dB, −48 dB)   1.5   2       [−48 dB, −30 dB)   1.2   1       [−30 dB, −24 dB)   1/2   0       [−24 dB, −18 dB)   1/4   0       [−18 dB, −12 dB)   1/8   0       [−12 dB, −6 dB)   1/16   0       [−6 dB, 0 dB)   1/32   0       [0 dB, +∞)   0   0                  
 
         [0025]      FIG. 8  shows at  100  the SNDR versus input level plots for the dithers in Table 1 (Prior-art), Table 3, and Table 4. The X-axis is the input amplitude relative to the full scale. The Y-axis is the SNDR. The prior-art dithering of Table 1 is shown at  104 , the dithering of Table 3 is shown at  102 , and line  106  shows the dithering of Table 4. It is appreciated in these plots, by gradually adjusting the differentiation order, the SNDR curve is smoother, and thus is a preferred way of implementing the dithering with dynamic differentiation order and gain adjustment with the input levels. The SNDR for this improved dither is higher than or the same as the prior-art dither.  
         [0026]     Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.