Abstract:
A supplementary DC power source is coupled to the DC link circuit of an active power line conditioner (APLC) for sustaining uninterrupted AC power to a load during the time interval needed for AC power restoration or for an alternate or a back-up AC source to be brought on line to power the load upon temporary or continued failure of an AC power source. The supplementary DC source is comprised of a rectifier circuit across which is connected a storage capacitor. A boost converter and an auctioneer diode are coupled between the storage capacitor and the DC link circuit so that when the DC link drops in voltage in response to a sag in the AC source voltage upon loss of the AC voltage source, the necessary power is provided by the storage capacitor and boost converter. A pair of fast acting switches are also coupled between the AC source and the power bus feeding the inverters to isolate the AC source from the APLC and the load upon loss of the AC source. When the back-up AC source is required and comes up to voltage and is synchronized with the APLC, the fast acting switches are again closed to connect the back-up AC source to the APLC and the load.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to an active power line conditioner (APLC) which is utilized to regulate the quality of electrical energy delivered to a load and more particularly to a series-parallel active power line conditioner which sustains uninterrupted power to a load for a predetermined time, typically 150 milliseconds, upon loss of the AC source voltage and its restoration or for a back-up source of AC voltage to be brought on line. 
     2. Description of Related Art 
     Electric supply networks are increasingly being exposed to the consequences of non-linear loads, such as data processing equipment, numerical controlled machines, variable speed motor drives, robotics, medical apparatus and communication equipment. Such loads draw non-linear pulse-like currents instead of sinusoidal currents which are drawn by linear loads, i.e. resistors, inductors and capacitors. These non-linear currents flow through the source impedance of the source of the electrical energy such as one or more AC generators, thus causing distortion of the AC line voltage. 
     To overcome AC line voltage distortion and apply a sinusoidal voltage to a non-linear load, there has been developed a class of power electronic devices, known as active power line conditioners (APLCs), which are connected between an AC power source and the load and comprise active power filters typically utilizing one or two switching inverters arranged in a series, parallel or series-parallel configuration. The inverters are controlled, generally by pulse-width modulation (PWM) techniques, to control the flow of current between a DC energy storage element and the AC supply lines to which they are connected. Such devices are shown and described in U.S. Pat. Nos. 4,651,265; 3,825,815, and 5,355,295, and are herein intended to be incorporated by reference. 
     In a conventional series-parallel APLC, two inverters are arranged to share a common DC link. In such an arrangement, the inverters cooperate to effect a transfer of real power between the source or load and the DC link so that the load continually sees an ideal sinusoidal current and voltage. 
     The series inverter in a series-parallel APLC is typically coupled to the AC supply source via a coupling transformer. The series inverter applies a voltage of selected magnitude and polarity to the secondary winding of the transformer to inject load voltage harmonics so as to zero current harmonics generated by the source, while the parallel inverter operates to inject source current harmonics in order to zero the load voltage harmonics. Thus, if the source voltage sags during part of the AC input waveform, the parallel inverter will sense the change and inject current into the line which will reduce the source current. The series inverter, on the other hand, senses the reduction in source current and then boosts the source voltage which returns the load voltage close to the desired fundamental voltage. The voltage boosts satisfies the parallel inverters, whereupon it reduces the current injection. 
     In an APLC, a capacitor or an inductor is typically used as an energy storage element to insure the presence of voltage on the DC link during variations in the demands placed on the inverters to deliver a clean sinusoidal AC voltage to the load. Theoretically, the capacitor or inductor should be able to provide sufficient energy to the inverters during a loss of the primary AC source voltage being furnished, for example, by an AC generator; however, in actuality, these storage elements have been found unable to furnish sufficient energy on their own during the time it takes for the generator voltage to be restored or for a second or back-up generator to come up to voltage and be synchronized with the load before being brought on line. More importantly, the loss of the AC source voltage from the generators results in a highly undesirable opening of one leg of the load circuit. 
     SUMMARY 
     It is the primary object of the present invention to enhance the capability of an active powerline conditioner such that it can provide uninterrupted, conditioned power to a load during a loss of AC input power for a predetermined time interval, e.g. 150 msec. This time is manifested during two periods of time. First, power is provided for a short specified time immediately after the primary AC source is lost upon the tripping of a circuit breaker and subsequently restored by reclosure of the breaker or before an alternate or back-up AC source is connected to the input bus. Second, power is provided for as long as is necessary to resynchronize the original AC source with the load or to, synchronize the alternate AC source with the load before it is brought on line. 
     The foregoing and other objects of the invention are achieved by the inclusion of a supplementary DC source coupled to the DC link circuit of an APLC which includes a series inverter and a parallel inverter coupled between an AC voltage source and a load. The supplementary DC source is comprised of a rectifier circuit across which is connected a storage capacitor. A boost converter and an auctioneer diode are coupled between the storage capacitor and the DC link circuit so that when the DC link drops in voltage in response to a sag in the AC source voltage upon loss of the AC voltage source, the DC link voltage is provided by the storage capacitor and boost converter. Also, a series connected fast acting switch isolates the AC source and its circuit braker from the APLC inverters and the load when there is a loss of AC voltage. With the loss of AC voltage from the source, the DC voltage on the link circuit is first maintained by the storage capacitor and boost circuit for a predetermined time interval, such as 150 msec, until the AC source is restored upon the tripping and reclosure of the circuit breaker or until an alternate AC source, e.g. a back-up generator, is brought on-line and reenergizes the AC input bus at an arbitrary voltage and phase angle. When the AC input bus is reenergized, it recharges the storage capacitor through a bridge rectifier and then continues to supply power through the rectifier and boost converter to the link circuit while the phase of the AC load voltage is brought into synchronization with the AC source. When the load is synchronized with the AC source voltage, the fast acting switch is again closed to reconnect AC source voltage to the APLC inverters and the load. 
     Further scope of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood, however, that the detailed description and specific examples, are provided by way of illustration only, since various changes and modifications within the spirit and scope of the invention will readily become apparent to those skilled in the art from this detailed description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood when considered together with the accompanying drawings wherein: 
     FIG. 1 is an electrical schematic diagram illustrative of the preferred embodiment of the invention; and 
     FIG. 2 is a partial electrical block diagram illustrative of the control circuitry for operating the embodiment shown in FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings and more particularly to FIG. 1, reference numeral 10 denotes an active power line conditioner (APLC) of the series-parallel type of APLC used to supply an AC output voltage V 0  to a load 12 from either a primary AC source or a secondary/back-up AC source 16, both of which typically comprise AC generators. As shown, the primary and secondary AC sources 14 and 16 are individually connected into the system by means of a circuit breaker such as an automatic bus transfer (ABT) switch including two sets of contacts 18 a  and 18 b  which are selectively coupled to an input power bus 20 in front of a switch S1. While FIG. 1 discloses the preferred embodiment, it should be noted that the present invention is also intended to encompass a system which includes a single AC source 14 and switch having only one set of contacts 18 a . 
     The APLC 10 comprises a conventional series-parallel device including a series inverter 24 and a parallel inverter 26 interconnected by a shared DC link circuit 28 including a capacitor 29 (C1) which is connected across the DC terminals of the inverters 24 and 26 and functions as a DC storage element. 
     The inverters 24 and 26 each include two pairs of switching devices, i.e. well known IGBT power switching devices, which are operated in a complementary manner by a control unit 30. The control unit 30 receives inputs from appropriate sensors within the APLC 10 which, among other things, provide information regarding the following parameters: The AC input voltage V 1 , the AC output voltage V 0 , the DC link voltage V dc , the AC series inverter current I s  and AC parallel inverter current I p . In response to signals corresponding to these parameters, the control unit 30 generates appropriate gating signals Q s  and Q p  to the inverters 24 and 26 which causes the IGBTs to operate so as to deliver regulated and conditioned power to the load 12 at a fundamental frequency, typically 60 Hz. 
     The series inverter 24 provides AC regulation voltage of the AC line voltage on power bus 32 via a coupling transformer 34 consisting of a primary winding 36 and a secondary winding 38 as well as an inductor 40. As is well known, the series inverter 24 operates to apply an AC regulation (+/-) voltage to the AC input voltage V 1  in the proper phase and magnitude such that the AC output voltage V 0  is regulated. The parallel inverter 26 is connected across the load 12 to add or decrease line current on the power bus 32 also in a well known manner. 
     The preceding description comprises typical state of the art operation of an APLC. One can refer to the prior art, for example U.S. Pat. No. 5,355,295, for a more detailed treatment of this type of device, if need be. 
     The inventive concept of this invention is directed to a means for insuring the availability of AC output voltage V 0  across the load 12 during the time it takes to match voltages and synchronize the load 12 to the source following a loss of primary AC source 14 and after the primary AC source 14 or the backup AC source 16 reenergizes the APLC input bus 20 within a 150 msec time limit. 
     As is shown in FIG. 1, an additional circuit 44 is interposed between the APLC 10 and the AC sources 14 and 16. The circuit 44 includes a full wave diode rectifier 45 (D1) connected to the input power bus 20 and a current return path 22 via terminals 46 and 48. A second storage capacitor 49 (C2) is coupled across the output terminals 50 and 52 of the bridge rectifier 51. Additionally, a boost converter module B1 including an IGBT 54 and an inductor 56 is connected to the capacitor 49. A diode 57 (D2) couples the DC link circuit 28 to the boost converter module B1. The circuit 44 also includes a fast acting AC power switch S1, shown consisting of two series connected solid state switches 58 and 60, which may be, for example, IGBTs, and the input power bus 20 connected to the input of the APLC 10. 
     A second switch shown by a single pole device 59 (S2) is connected across the secondary winding 38 of series inverter transformer 34. This switch comprises an electrical switch which is controlled by the control unit 30 by means of a control signal S2 generated thereby in a manner to be described. 
     Appropriate sensors are additionally provided to measure and provide signals corresponding to the frequency f 1  of the input voltage V 0  which appears on input power bus 20, a DC voltage V boost  which appears across the solid state switch 54 of the boost converter module B1 and the frequency f LOAD  of the voltage V 0 . These signals are also applied to the control unit 30. 
     The control unit 30 in addition to generating gating signals Q s  and Q p  for the solid state switches in the series inverter and parallel converter, respectively, in accordance with well known PWM techniques, also now generates a pair of gating signals S1 for operating the two solid state switches 58 and 60 of the power switch S1. The control unit 30 also generates a signal pulse train B 1  for gating the solid state switch 54 of the boost converter B1 and a control signal S2 for operating the electrical switch 59 coupled across the primary winding 36 of the inverter transformer 34 in the APLC 10. Circuitry for generating these signals as well as a DISABLE signal for disabling the solid state power switching devices of the series inverter 24 when the switch S2 is closed is shown in FIG. 2. 
     When the circuit breaker 18 is set as shown in FIG. 1 to connect the generator 14 to the input power bus 20, capacitor 29 acts as the primary energy storage element to insure the presence of a DC voltage V dc  on the DC link circuit 28 during variations in the demands placed on the series and parallel inverters 24 and 26. In most instances, capacitor 29 can provide sufficient energy to the inverters 24 and 26 during a reduction or &#34;sagging&#34; of the AC voltage V 0  being furnished by the primary AC source 14. However, in the event that the primary source 14 is temporarily lost or it becomes necessary to connect the alternate generator 16 in its place by setting the breaker 18 such that contacts 18a open while contacts 18b close, the primary storage element C1 cannot by itself furnish sufficient energy. 
     In such an event, S1 is opened and power is temporarily supplied to the load 12 by alternate means. The energy stored in capacitor 49 will supply this power for a short time interval, for example 150 msec, through the boost converter B1 until the alternate AC source 16 reenergizes input bus 20 at an arbitrary phase angle and voltage level. The reenergized bus 20 recharges C2 and supplies power to the load 12 through the boost converter B1, diode D2, and DC link circuit 28 of the APLC 10. This continues until the input bus voltage V 1  on the input bus 20 has been synchronized in frequency and phase and matched in voltage with the load voltage V 0  across the load 12, at which time normal operation is restored by reclosing S1 and opening S2. The DC voltage generated by the diode rectifier bridge B1 charges the storage capacitor 49 to a voltage that is set slightly below the normal APLC DC link voltage V dc . This reverse biases diode D2 and prevents it from conducting. This is important during normal operations because the rectifier D1 is an undesirable nonlinear load which would draw current harmonics from the AC source 14. However, upon the loss of AC voltage from the primary source 14, and until the input bus 20 is reenergized, the boost converter B1 boosts the voltage so that diode D2 conducts and supplies current to the DC link 28. 
     Looking now to FIG. 2, the loss of the source voltage on the input bus 20 is sensed and applied to the control unit 30 where it is fed to a comparator circuit 62. The comparator circuit 62 compares various parameters of the input voltage, such as voltage, frequency, or the rates of change of either, with an established setpoint(s) 64. When the parameter(s) cross the setpoint(s), the comparator 62 outputs a loss of voltage signal on signal lead 66. This signal is commonly fed to a V boost  regulator 68, a reference frequency generator 70, a logic circuit 72, and a S 1  and S 2  control circuit 74. When a loss of voltage signal appears on circuit lead 66, the V boost  regulator 68 and the reference frequency generator 70 are enabled and a signal is applied to the S 1  and S 2  control circuit 74 for stopping the generation of the S1 gating signals, thus causing solid state switches 58 and 60 to be non-conductive. This isolates the APLC 10 and load 12 from input power bus 20. 
     With the loss of AC voltage from the primary source 14, the APLC DC link voltage V dc  is maintained by the secondary storage capacitor 49 which is now in parallel with capacitor C1 for a required ride-through time interval, e.g. 150 msec. for the reclosure of the breaker 18 should it trip for any reason or for the back-up source, i.e. generator 16 to be connected to the input bus 20 via closure of switch contacts 18 b  of the breaker 18, to come up to voltage and be synchronized with the APLC load voltage V 0 . During this time interval, the bridge rectifier D1 supports the load requirement along with the storage capacitor 49 so that there is no loss of current I L  to the load 12. Concurrently with the loss of voltage being detected by the comparator 62, the pulse train B 1  of gate signals for solid state switch 54 of the boost converter B 1  is generated by a pulse signal generator 76 in response to the output of a V boost  voltage regulator 68 which receives as an input an error signal coupled from a summing junction 78 which receives a reference value from a V boost  reference circuit 80 and the V boost  signal value detected across the IGBT switch element 54. 
     Also upon the detection of the loss of source voltage V 1 , the control unit 30 deactivates the series inverter 24 by closing the switch S2 across the primary winding 36 of the transformer 34 as well as inhibits generation of the gating signals Q s . This is accomplished through S 1  and S 2  control circuit 74 and S2 signal generator 82 which also applies an inhibit signal to the Q s  gating signal generator 84. 
     The control unit 30 also acts to establish a fundamental reference frequency for a phase lock loop (PLL) 86 shown in FIG. 2 being connected to the output of the reference frequency generator 70. The PLL 86 controls two PWM control circuits 88 and 90 which controls the Q s  generator 10 and a Q p  gating signal generator 92, respectively. The fundamental reference frequency will be generated by the generator 70 until the back-up generator 16 comes up to full voltage and the switch S1 is reclosed. 
     The reclosure of the solid state switch S1 requires that the primary generator 14 first be resynchronized, if necessary, or that the back-up generator 16 be synchronized with the load 12. Synchronization is achieved by switching the input to the phase-locked loop (PLL) circuit 86 to the reference frequency signal from the frequency reference generator 70. The switch is performed by a multiplexer 71 when the loss-of-voltage signal on circuit lead 66 becomes active. Reference generator 70 insures that the APLC 10 has a frequency reference input even when the input AC bus 20 is deenergized. Also, it makes the frequency reference change slowly from the phase of primary AC source 14 to the phase of the back-up AC source 16. The reference frequency generator 70 receives frequency error and phase error inputs from summing points 94 and 96, respectively. As shown in FIG. 2, summing point 94 generates a frequency error signal from input signals corresponding to the frequency f 1  on the input bus 20, and the frequency f load  of the AC signal applied to the load 12. Summing point 96 generates a phase error signal from a pair of detectors 98 and 100, respectively also receiving inputs corresponding to f 1  and f load . 
     The phase error signal from the summing junction 96 is applied to the logic circuit 72 along with the frequency error signal from summing junction 94 by circuit leads 102 and 104. When the frequency error signal and the phase error signal are substantially zero, indicating that both signals V 1  and V 0  are synchronized both in frequency and phase, the logic circuit 72 generates a command signal for the control circuit 74 to close switch S1, open switch S2 and enable the generation of the gating signals Q s . 
     As shown in FIG. 2, a time delay circuit is placed between the logic circuit 72 and the control circuit 74, as well as the Q s  generator 84 in order for enhancing operation; however, when desirable, such an element may be deleted. 
     Accordingly, restoration of AC voltage to the APLC 10 and load 12 via the power bus 20 is achieved upon reclosure of the switch S1. When this occurs, the normal DC link voltage V dc  generated by the APLC 10 is reestablished. Since its normal value is slightly higher than that drive from the boost converter B1, the diode D2 will block current from the DC link circuit 28 from being fed back to the boost converter B1. The APLC 10 will thereafter continue functioning as normal, with all power now being supplied by the back-up generator 16. 
     Thus the circuitry 44 in conjunction with the control unit 30 will detect the loss of the voltage source, e.g. AC generator 14, measure the frequency f 1  appearing on the input bus 20, the frequency f load  of the voltage V 0  across the load 12 control the switch S1 between the source and the load, turn off the series inverter along with closing switch S2 to activate the boost converter B1 and generate a reference frequency for synchronizing the APLC 10 and load 12 with the back-up generator 16 before it is brought on line or resynchronize the primary generator 14, if need be, with the load 12 where the breaker 18 trips and recloses within the 150 msec. time limit. 
     Having thus described what is at present considered to be the preferred embodiment of the invention, it should be noted that the same has been made by way of illustration and not limitation. Accordingly, all modifications, alterations and changes coming within the spirit and scope of the invention are herein meant to be included.