Abstract:
Coherent detection of high-speed digital wireless communications becomes more difficult when the frequencies of the transmitter and receiver oscillators do not coincide. A frequency-locked loop may be used to characterize this frequency offset by processing the samples received on a pilot channel. Rather than using the offset information thus derived to correct the frequency of the received signal, the invention realizes a considerable computational savings by applying a frequency correction to the despread pilot samples instead.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to wireless communications. More specifically, this invention relates to systems for digital wireless communications that employ coherent detection. 
     2. Description of Related Art and General Background 
     1) Spread Spectrum and Code-division Multiple-access 
     Spread spectrum communication techniques are robust to noise, allow for the use of low transmission power, and have a low probability of intercept. For such reasons, much of the early development of spread spectrum technology was performed by military researchers. Recently, however, the advantages of this technology have led to its increasing use for consumer applications as well: most notably, in advanced digital cellular telephone systems. 
     Whereas most other communication techniques modulate a carrier signal with one or more data signals alone, spread spectrum techniques also modulate the carrier with a pseudorandom noise or ‘pseudonoise’ (PN) signal. In the frequency-hopping variant of spread spectrum systems, the value of the PN signal at a particular instant determines the frequency of the transmitted signal, and thus the spectrum of the signal is spread. In the direct sequence spread spectrum (DSSS) variant, the bit rate of the PN signal (called the ‘chip rate’) is chosen to be higher than the bit rate of the information signal, such that when the carrier is modulated by both signals, its spectrum is spread. 
     Communication systems that support multiple individual signals over a single channel must employ some technique to make the various signals distinguishable at the receiver. In time-division multiple-access (TDMA) systems, the individual signals are transmitted in nonoverlapping intervals such that they are orthogonal (and thus separable) in time space. In frequency-division multiple-access (FDMA) systems, the signals are bandlimited and transmitted in nonoverlapping subchannels such that they are orthogonal in frequency space. In code-division multiple-access (CDMA) systems, the signals are spread through modulation by orthogonal or uncorrelated code sequences such that they are orthogonal or nearly orthogonal in code space and may be transmitted across the same channel at the same time while remaining distinguishable from one another at the receiver. An exemplary CDMA system is described in U.S. Pat. No. 4,901,307, entitled “SPREAD SPECTRUM MULTIPLE-ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS,” issued Feb. 13, 1990 and assigned to the assignee of the present invention, and the disclosure of which is hereby incorporated by reference. 
     In a CDMA DSSS system, then, each individual carrier signal is modulated by a data signal and a pseudonoise (PN) signal that is at least nearly orthogonal to the PN signals assigned to all other users, thus spreading the spectrum of the transmitted signal while rendering it distinguishable from the other users&#39; signals. Before spreading and modulation onto the carrier, the data signal typically undergoes various encoding and interleaving operations designed, for example, to increase data redundancy and allow error correction at the receiver. The data signals may also be encrypted to provide extra security against eavesdroppers. The generation of CDMA signals in a spread spectrum communications system is disclosed in U.S. Pat. No. 5,103,459, entitled “SYSTEM AND METHOD FOR GENERATING SIGNAL WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM,” issued Apr. 7, 1992 and assigned to the assignee of the present invention, and the disclosure of which is hereby incorporated by reference. 
     2) Phase Modulation 
     In a DSSS telecommunications system, the baseband information signal is typically spread by the PN sequences to have a bandwidth of 1 MHz or more. In order to transmit the spread baseband signal over a radio channel, it is necessary to modulate it onto an RF carrier of the desired frequency. 
     Various methods of modulating digital baseband signals onto RF carriers exist. These methods typically operate by varying the amplitude, phase, and/or frequency of one or both of the in-phase (I) and quadrature (Q) components of the carrier according to the data symbol to be transmitted at any particular instant. DSSS systems commonly use a variant of either phase-shift keying (PSK), in which the phase states in the carrier components correspond to data symbols being transferred, or quadrature amplitude modulation (QAM), in which both the phases and the amplitudes of the carrier components are modulated. 
     In an exemplary system using binary PSK (BPSK) modulation, a transition of the carrier from a base phase state (defining a phase of zero) to a second phase state which is different by 180 degrees (i.e. a phase shift of π radians away from zero) may be designated to indicate a transition from a data symbol  0  to a data symbol  1 . The converse phase shift of π radians back to zero would then be designated to indicate a transition from a data symbol  1  to a data symbol  0 . Between these transitions, the phase of the carrier indicates whether a data symbol  0  is being transmitted (phase of zero) or a data symbol  1  instead (phase of π radians). An improved ratio of data rate to bandwidth may be obtained by using quadrature PSK (QPSK) modulation, in which the data symbols are encoded into 180-degree shifts in both the I and Q components. These and other variants of PSK modulation are well known in the art. 
     Note that in PSK modulation, all phase states have significance only in relation to the base phase state. If this reference state is unknown, then only the points of phase state transition may be identified, and the actual identities of the symbols cannot be determined. In the BPSK system described above, for example, a phase shift of π radians indicates either a transition from 0 to 1 or from 1 to 0. Unless one knows the relation between the base phase state and either the starting or the ending phase state, it is impossible to determine which transition was meant. 
     This phase ambiguity problem may be addressed in several different ways. One approach has been to avoid it by using a modulation which is suitable for noncoherent detection and does not require knowledge of the base phase state, such as differential PSK (DPSK). A more power-efficient method uses orthogonal signalling sets to encode the data symbols in a manner which is unambiguous regardless of the base phase state. The Hadamard-Walsh functions are one suitable signalling set, as discussed in Chapter 4 of CDMA:  Principles of Spread Spectrum Communications  by Andrew J. Viterbi, Addison Wesley Longman, Reading, Mass., 1995, which chapter is herein incorporated by reference. However, by providing the informational redundancy necessary to avoid the phase ambiguity problem, these methods may also reduce the achievable data throughput of the channel. An alternative approach has been to use a coherent detection scheme. 
     3) Coherent Detection and Phase Noise 
     In pilot-assisted coherent detection, the base phase state is derived from a pilot signal, a signal of known form which is transmitted along with the data signal to provide a phase and magnitude reference. One method of transmitting pilot and data channels over the same carrier is to cover the channels with different orthogonal codes (e.g., with different Walsh functions). At the receiver, the pilot channel may be used to establish carrier synchronization and enable coherent detection by, for example, using a phase-locked loop to keep the output of a local oscillator at a constant phase angle with respect to the received pilot. 
     Unfortunately, carrier synchronization is often complicated by the presence of phase noise. Phase noise may have two components, one being random and the other being more determinable. The random component is primarily due to Doppler effects caused by relative motion between the transmitter and receiver (or apparent motion between the two, as might be caused by a reflector). The maximum magnitude f d     —     max  of such a Doppler shift is defined as 
     
       
         
           f 
           d 
           
             — 
           
           max 
           =f 
           c 
           ×v/c, 
         
       
     
     where f c  is the carrier frequency in Hz, v is the relative velocity in m/sec, and c is the speed of light. For carrier frequencies in the gigahertz range and relative velocities of a few hundred miles per hour, the Doppler component may be on the order of hundreds of Hertz. 
     Because the Doppler component changes rapidly and may exceed a few percent of the data rate, it is typically very difficult to track using a phase-locked loop. An alternative way to compensate for this random component is to use the known pilot signal to obtain an estimate of the channel&#39;s effects. This estimate is usually in the form of a complex vector which represents the rotation in phase introduced by the channel and is used to compensate for the same rotation in the data samples. 
     Phase noise also arises as a frequency offset within the system architecture, caused primarily by a difference in frequency between the oscillators in the transmitter and the receiver. This difference may arise, for example, because of variances in manufacture or drift due to aging or temperature, and the effect of this offset is to introduce a phase rotation into the samples which remains relatively constant with respect to time. Section 10.1.1.3 of the IS-98A standard (TIA/EIA, July 1996) allows the frequency of the mobile station&#39;s carrier to have an error of as much as 300 Hz once the oscillators have been phase-locked. 
     If the constant-rotating-component frequency offset is compensated separately, then a much better estimate of the random component of the phase noise may be obtained. One method of correcting the frequency offset is by using a digital frequency-locked loop (DFLL). The elements and principles of operation of digital frequency-locked loops are well known in the art and are described, for example, in “Convergence and Output MSE of Digital Frequency-Locked Loop for Wireless Communications” by the inventor Ling,  Proceedings of the  1996  IEEE Vehicular Technology Conference,  Atlanta, pp. 1215-1219, and “AFC Tracking Algorithms” by Francis D. Natali,  IEEE Transactions on Communications,  vol. COM-32, no. Aug. 8, 1984, pp. 935-947, which documents are hereby incorporated by reference. 
     Frequency Offset Correction 
     FIG. 1 illustrates one method of frequency offset correction that uses a DFLL. An RF stage (not shown) supplies received analog data to conversion and correction block  110  for A/D conversion and frequency correction. As detailed below, the frequency correction operation may be performed either before or after A/D conversion. The digitized and corrected in-phase (I) and quadrature (Q) sample streams are despread by PN spreader  115  and then by data despreader  120  and pilot despreader  130  to obtain the symbols of the data and pilot channels, respectively. 
     Frequency discriminator  140  receives the despread pilot samples and generates an instantaneous frequency error {circumflex over (f)}. As illustrated in FIG. 2, the value {circumflex over (f)} is calculated as the imaginary portion of the complex product of the current pilot sample and the complex conjugate of the previous pilot sample. In loop filter  150 , the instantaneous frequency error {circumflex over (f)} is scaled to control the convergence and bandwidth of the DFLL and then integrated to obtain a more accurate offset frequency estimate {tilde over (f)}. This estimate of offset frequency is input to block  110  and used to adjust the phase of the received data. 
     In block  110 , frequency correction may be applied in the analog domain by inputting analog data at RF or IF and using a voltage-controlled oscillator (VCO) controlled by the DFLL to downconvert the signal to baseband before A/D conversion. While it is relatively easy to perform frequency correction on an analog signal, however, for some applications it is not practical. For example, the signal received by a CDMA base station will typically contain signals from many users, each component signal having a different frequency offset. For a TDMA base station, the signal received during each time slot will typically come from a different user and have a different frequency offset than the signal received in adjacent time slots. In such cases, it is preferable to perform the frequency correction in the digital domain. Moreover, better temperature stability and reliability of operation can be obtained in a smaller circuit area if the correction is performed digitally instead. 
     Frequency correction may be applied in the digital domain by inputting analog data to block  110  at baseband and applying complex rotations to the samples after A/D conversion. One disadvantage to performing the correction after digitization is that it becomes more intensive, requiring a complex rotation to be performed on every sample. For a typical chip rate of 1.2288 Mcps and a sampling rate of twice the chip rate, this method would require nearly 2.5 million complex rotations to be performed every second. The power and available area required to support such a processing rate renders digital frequency correction infeasible for many applications. 
     SUMMARY OF THE INVENTION 
     By performing frequency correction processing on the pilot channel after despreading, rather than on the received samples before despreading, the invention considerably reduces the computational effort required to compensate for a frequency offset in the data channel. In order to maintain coherence between the data and pilot channels, the invention also includes derotating the channel estimate and delaying the samples in the data channel before coherent detection is performed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a method of frequency correction. 
     FIG. 2 shows a circuit diagram for frequency discriminator  140 . 
     FIG. 3 is a block diagram of the first embodiment of the invention. 
     FIG. 4 shows a circuit diagram for a quadricorrelator being a preferred implementation of frequency discriminator  140 . 
     FIG. 5 shows a circuit diagram for a complex multiplier. 
     FIG. 6 illustrates a first implementation of loop filtering, phase calculation, and delay block  250 . 
     FIG. 7 illustrates an implementation of frequency offset integrator  340 . 
     FIG. 8A illustrates an implementation of phase adjustment integrator  350 . 
     FIG. 8B illustrates a second implementation of phase adjustment integrator  350 . 
     FIG. 9 illustrates a second implementation of loop filtering, phase calculation, and delay block  250 . 
     FIG. 10 illustrates a first-order implementation of loop filter  325 . 
     FIG. 11 illustrates a second-order implementation of loop filter  325 . 
     FIG. 12 is a block diagram of an alternative embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3 is a block diagram of the first embodiment of the invention. In a preferred implementation, the circuit of FIG. 3 (except for loop filtering, phase calculation, and delay block  250 ) would be replicated for several receivers, each receiving a different multipath instance of the signal from the same or different antennas. Such single-path receivers are commonly referred to as Rake ‘fingers.’ In such an implementation, loop filtering, phase calculation, and delay (LFPCD) block  250  would be common to all fingers, receiving a value {circumflex over (f)} i  from each finger and outputting complex pairs (cos θ, −sin θ) and (cos φ, sin φ) in common to all fingers. 
     In the preferred embodiment of FIG. 3, the baseband analog data received from the RF and/or IF stages (not shown) passes through A/D converter  210 , is despread by the PN sequence in PN despreader  115 , and undergoes further despreading in data despreader  120  and pilot despreader  130 . Despreaders  115  and  120  may be implemented as complex multipliers as illustrated in FIG. 5, where the inputs I_ 2  and Q_ 2  are the respective despreading codes. Assuming that the frequency offset is much lower than the data sample rate, the frequency offset may be ignored during the despreading operations. 
     In a preferred implementation, the pilot channel is covered by Walsh function 0 (i.e., the covering function is effectively a constant value). In this case, pilot despreader  130  may be implemented as an integrate-and-dump circuit. The integration period should be long in order to reduce the sample frequency and thus reduce the computational load, but on the other hand the integration period should be short so that the phase shift due to the frequency offset is negligible within that period. For a frequency offset of 300 Hz and a Doppler component of a few hundred Hertz, an integration period of about 200 μs is used for one embodiment. Before further processing, it may be desirable to truncate the pilot samples by right-shifting, for example. Truncation serves to reduce the data bitwidth in later stages, and a moderate amount of truncation and rounding at this stage has not been shown to introduce any performance degradation. However, truncation is optional. 
     After despreading, the pilot samples are rotated in phase rotator  220 . A preferred implementation of phase rotator  220  is a complex multiplier, as shown in FIG.  5 . The complex values which represent the angle of rotation θ are output by LFPCD block  250  as described below. 
     The rotated pilot samples are input to frequency discriminator  140 , which outputs a measure {circumflex over (f)} of the instantaneous frequency error. In a preferred implementation, frequency discriminator  140  (whose functionality is shown in FIG. 2) is implemented as a quadricorrelator as illustrated in FIG.  4 . 
     FIG. 6 shows a block diagram of LFPCD block  250 . As noted above, in a preferred implementation, a number of fingers individually calculate instantaneous frequency errors {circumflex over (f)} i . These values are input to LFPCD block  250  through frequency error combiner  310 . In a preferred implementation, combiner  310  outputs a value {circumflex over (f)} Σ  as the sum of the values {circumflex over (f)} i . However, combiner  310  may be constructed to output a weighted or non-weighted average of these values as well. If only one value of {circumflex over (f)} is input to LFPCD block  250 , combiner  310  may be omitted. 
     Limiter  320  provides a measure of system stability by restricting the possible range of the frequency error reported. In an alternative implementation, robustness is not necessary or is provided elsewhere. In such implementations, limiter  320  may be omitted. 
     Loop filter  325  receives the limited or non-limited frequency error value {circumflex over (f)} Σ  (or {circumflex over (f)}, as appropriate) and outputs a frequency offset value f off . FIG. 10 shows one implementation of a first-order filter suitable for use as loop filter  325 . In this implementation, scaler  330  receives the input signal and outputs a scaled error value {circumflex over (f)} sc . It is preferable to avoid multiplication in this stage by choosing a scaling factor of 2 −n  and implementing scaler  330  as a right-shifter. As noted in the references incorporated above, for a first-order DFLL, the scaling factor determines the time constant of the DFLL (or, equivalently, its loop bandwidth) according to the following expression: 
     
       
           T   c   =NT   s /(α k   d   k   0 ), 
       
     
     where T c  is the time constant of the DFLL in seconds; N is the insertion delay of the frequency discriminator and update interval of the loop filter in samples; T s  is the sample period in seconds; α is the nondimensional scaling factor; k d  is the gain of the frequency discriminator in LSB/Hz, where LSB denotes the least significant bit of the output of the frequency discriminator; and k 0  is the resolution of the phase rotation operation in Hz/LSB, where LSB denotes the least significant bit of the input to the digital-to-frequency converter (here, the input to lookup table  360 ). In a typical application, the scaling factor is the only factor in this expression that can be changed dynamically. (Parameters that may affect the values of the other factors in the expression above include the integration period, the signal-to-noise ratio, and the particular implementation of the digital-to-frequency converter.) 
     Of course, the scaling factor must also be chosen with regard to the number of fingers input to frequency error combiner  310  and the nature of combination performed therein (e.g. whether the inputs are averaged or simply accumulated). In order to keep the frequency error at the DFLL output below a desirable value, e.g., 100 Hz and ensure that this error will not degrade receiver performance, it is desirable for the time constant to be within the range from approximately 10 to approximately a few hundred milliseconds. In the exemplary application, typical values for the scaling factor range from approximately 2 2  (4) to approximately 2 −4  (1/16). 
     Frequency offset integrator  340  receives the scaled frequency error value {circumflex over (f)} sc  and outputs a frequency offset value f off  that characterizes the difference in frequency between the oscillators of the transmitter and receiver. In a preferred implementation, frequency offset integrator  340  is constructed as a perfect integrator as shown in FIG.  7 . Assuming that the frequencies of the transmitter and receiver oscillators are perfectly constant and that the random component of the phase noise does not affect the DFLL, then one can see that the value of {circumflex over (f)} sc  will approach zero and that the value of f off  will approach a constant. The range of possible values for f off  represents the range of frequency offsets that may be compensated by this circuit. 
     One of ordinary skill in the art will recognize that loop filters of higher order, such as the second-order configuration shown in FIG. 11, may be used instead of a first-order configuration for loop filter  325  if, for example, a different convergence characteristic is desired. In these alternative implementations of the invention, the structures of frequency offset integrators  340   a  and  340   b  will typically be the same as shown in FIG. 7 for integrator  340 , and first scaler  330   a  and second scaler  330   b  may each have the same constant value or may have different constant values. 
     Phase adjustment integrator  350  serves to convert the frequency offset f off  into a phase adjustment factor θ. In a preferred implementation, phase adjustment integrator  350  has either the structure shown in FIG. 8A or the one shown in FIG. 8B; the maximum and minimum values of output value θ substantially correspond to π and −π, respectively; and overflow is ignored such that phase adjustment integrator  350  performs modulo 2π accumulation. 
     Lookup table  360  is preprogrammed to convert the phase value θ into a pair of values representing a complex phase vector (for example, cos θ and sin θ). After passing through complex conjugator  370 , this complex vector is input to phase rotator  220 , where the pilot sample is rotated according to the following expression: 
     
       
           r   p   e   j(p−θ)   =r   p   e   jp   e   −jθ   =r   p (cos  p+j  sin  p )(cos θ− j  sin θ), 
       
     
     where r p  is the magnitude of the pilot sample, p is the angle of the pilot sample as received, and p−θ is the angle of the pilot sample after correction of the frequency offset. 
     The rotated pilot samples are also input to pilot filter  160 , which produces an estimate of the channel. The channel estimate represents the distortions of phase rotation and magnitude scaling introduced into the pilot signal by the channel and is typically reported as a vector in I/Q space. The number of taps N in filter  160  is chosen to provide the best overall channel estimate. On one hand, it is desirable that the channel remains relatively constant over the life span of the estimate, so that N should remain small. On the other hand, an estimate of higher accuracy may be obtained with a larger N. Filter  160  may be implemented as either an IIR or a FIR filter. In a preferred embodiment, filter  160  is an complex eight-tap rectangular averager. 
     Because the channel estimate is constructed from rotated pilot samples, its phase does not coincide with the phase of the samples in the data channel to be demodulated. Therefore, it is necessary to remove the rotation that was introduced by phase rotator  220  before this estimate may be applied to the data channel. Toward this end, the phase rotation factors that were supplied to phase rotator  220  by phase calculation block  250  are delayed by derotation delay  380  such that they reach phase derotator  240  at substantially the same time as the corresponding channel estimate is produced by pilot filter  160 . As shown in FIG. 6, derotation delay  380  may receive the values θ from phase adjustment integrator  350 . In a preferred implementation, however, as shown in FIG. 9, derotation delay  380  receives θ and also f off , and a split-sample delay time is effectively obtained by combining these two values in an appropriate proportion. 
     Lookup table  390  is preprogrammed to convert the delayed phase value φ into a pair of values representing a complex phase vector (for example, cos φ and sin φ). In a preferred implementation, lookup tables  360  and  390  are the same unit, and the addressing input to this table is multiplexed between phase adjustment integrator  350  and derotation delay  380 . Note that if lookup tables  360  and  390  are not the same unit, then lookup table  360  may be modified to hold complex conjugate values instead, thereby dispensing with the need for complex conjugator  370 . 
     The complex vector is input to phase derotator  240 . As with phase rotator  220 , the preferred implementation of phase derotator  240  is a complex multiplier as shown in FIG.  5 . Because the phase adjustment vector is not complex conjugated in this stage, the rotation introduced by phase rotator  220  is removed from the channel estimate according to the following expression: 
     
       
           e   j(p−θ+φ)   =e   j(p−θ)   e   jφ =[(cos  p+j  sin  p )(cos θ− j  sin θ)](cos φ+ j  sin φ), 
       
     
     where p−θ is the angle of the channel estimate, and p−θ+φ is the angle of the channel estimate after restoration of the frequency offset. In a preferred implementation, the derotation angle φ has the same value as the rotation angle θ, so that the value of p−θ+φ is simply p, the angle of the pilot sample as received. However, it is also possible to refine the value of φ on the basis of information that was not available when the value of θ was calculated. 
     After derotation, the channel estimate passes through complex conjugator  170  and is combined with the despread and delayed data samples in coherent detector  190 . As with phase rotator  220  and derotator  240 , the preferred implementation of coherent detector  190  is a complex multiplier as shown in FIG.  5 . 
     In the preferred embodiments described and illustrated above, the phase rotation θ is calculated from a first set of pilot samples, taken at a first point in time from the stream of samples output by PN despreader  115 . In phase rotator  220 , the phase rotation θ is then applied to a second set of pilot samples, taken from the same stream of samples output by PN despreader  115  but at a later point in time than the first set. In an alternative embodiment, as shown in FIG. 12, the phase rotation θ calculated from a set of pilot samples is applied in phase rotator  220  back to the same set of pilot samples by, for example, keeping a copy of each set of pilot samples in a buffer  260 . 
     The foregoing description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles presented herein may be applied to other embodiments without use of the inventive faculty. For example, even though the preferred embodiment relates to a CDMA receiver with a code-division-multiplexed pilot, the invention may also be applied to a receiver with a time-division-multiplexed pilot or to a TDMA receiver. Additionally, one of ordinary skill in the art will recognize that although the preferred embodiment of the invention processes signals that have been digitized, the novel principles described herein are equally applicable to a system that processes analog signals or to a hybrid system. Thus, the present invention is not intended to be limited to the embodiments shown above, but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein.