Abstract:
A semiconductor device includes a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs.

Description:
BACKGROUND 
       [0001]    The present invention relates generally to integrated circuit (IC) designs, and more particularly to sense amplifiers operated under Hamming distance methodology for improving performance or reducing layout areas thereof. 
         [0002]    A differential amplifier is a circuit module that generates outputs in response to a voltage difference between various inputs. It is commonly used in IC chips, such as memory devices, for amplifying sensed data signals. The differential amplifier is typically consisted of electronic components that can be grouped into symmetric halves, each being connected to a differential input. The electronic components of the two symmetric halves need to match in their dimensions, materials and structures in order to ensure that the outputs from the differential amplifier accurately reflects the voltage difference between the inputs. As a result, the size of the differential amplifier cannot be scaled down easily because the smaller the amplifier the more susceptible it is to mismatch due to manufacturing process variations. 
         [0003]      FIG. 1  illustrates a first distribution curve  102  of a first group of differential sense amplifiers and a second distribution curve  104  of a second group of differential sense amplifiers, which are half the size of the differential sense amplifiers in the first group. The offset voltages for each group of differential sense amplifiers are normally distributed, in which the curve  102  is more concentrated and the curve  104  is more spread out. The curves  102  and  104  show that there are more small amplifiers outside a predetermined range of input swing than the large ones. This raises reliability issues as the differential sense amplifiers are scaled down. 
         [0004]      FIG. 2  illustrates a conventional differential sense amplifier within a layout area  202 . A new design for differential sense amplifiers has been proposed to reduce the layout area without compromising their reliability. Naveen Verma, Anantha P. Chandrakasan, “A 65 nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 64-65, February 2007. As shown in  FIG. 3 , the layout area  202  is split into two halves  302  and  304 , each of which is implemented with a differential sense amplifier. Assume that the offset voltages for the large amplifier in the layout area  202  and the amplifier in the layout area  302  or  304  are normally distributed, and the probability of failure for the small amplifier is 0.001, which is translated into a z value of 3.09 in a standard normal distribution. The probability of failure for the large differential sense amplifier is therefore 0.000006, which is obtained by looking up the standard normal distribution table with a z value of 4.369, i.e., 3.09*(2) 1/2  as the large amplifier is twice bigger than the small amplifier. Although the probability of failure for one small amplifier (0.001) is higher than that for one large amplifier (0.000006), the probability of two small amplifiers failing at the same time (0.000001=0.001*0.001) is lower than the probability of failure for one large amplifier. In other words, for the same reliability level, the overall size of two small amplifiers  302  and  304  would be smaller than one large amplifier  202 . 
         [0005]    The conventional dual sense amplifier design requires an initial testing process where all the sense amplifiers are scanned in order to select the sense amplifier with better performance from each pair of sense amplifiers. Additional registers are required for storing the status of the sense amplifiers in support of their operation. As a result, the conventional dual sense amplifier design can be quite complicated and resource-consuming. 
         [0006]    Thus, what is needed is a simple design for differential sense amplifiers that reduces the layout areas without compromising the reliability. 
       SUMMARY 
       [0007]    The present invention discloses a semiconductor device including a first sense amplifier coupled to an input for generating a first output; a second sense amplifier couple to the input for generating a second output; and a third sense amplifier coupled to the input for generating a third output, wherein a fourth output amplifying the input is generated based on combinations of logic states of the first, second and third outputs. 
         [0008]    The construction and method of operation of the invention, however, together with additional objectives and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  illustrates graphs showing distributions of offset voltages for small and large differential sense amplifiers. 
           [0010]      FIG. 2  illustrates a layout area in which a conventional differential sense amplifier is implemented. 
           [0011]      FIG. 3  illustrates a layout area in which conventional dual sense amplifiers are implemented. 
           [0012]      FIG. 4  illustrates a schematic of a differential sense amplifier in accordance with one embodiment of the present invention. 
           [0013]      FIG. 5  illustrates a layout area in which a plurality of differential sense amplifiers operating under Hamming distance methodology are implemented in accordance with one embodiment of the present invention. 
           [0014]      FIG. 6  illustrates a schematic of a Hamming operation circuit in accordance with one embodiment of the present invention. 
           [0015]      FIG. 7  illustrates distributions of offset voltages for the proposed differential sense amplifiers and the conventional differential sense amplifiers. 
       
    
    
     DESCRIPTION 
       [0016]    This invention describes a semiconductor device containing sense amplifiers operated under Hamming distance methodology for improving performance or reducing layout areas thereof. The following merely illustrates various embodiments of the present invention for purposes of explaining the principles thereof. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of this invention. 
         [0017]      FIG. 4  illustrates a schematic of a differential sense amplifier  400  in accordance with one embodiment of the present invention. The differential sense amplifier  400  includes NMOS transistors N 1 , N 2  and N 3 , PMOS transistors P 1 , P 2 , P 3 , P 4 , P 5 , P 6  and P 7 . The PMOS transistors P 3  and P 4  are connected at their sources, which are further connected to the supply voltage Vdd. The drains of the PMOS transistors P 3  and P 4  are connected to the drains of the NMOS transistors N 1  and N 2 , respectively. The sources of the NMOS transistors N 1  and N 2  are connected together with the drain of the NMOS transistor N 3 , which is further connected to ground or Vss at its source. The gates of the PMOS transistor P 3  and the NMOS transistor N 2  are connected together at a node  402 , which is connected to the drains of the PMOS transistor P 4  and the NMOS transistor N 1 . The gates of the PMOS transistor P 4  and the NMOS transistor N 1  are connected together at a node  404 , which is connected to the drains of the PMOS transistor P 3  and the NMOS transistor N 2 . The gates of the PMOS transistors P 3  and P 4  are connected via the PMOS transistor P 5 , which is controlled by an enable signal from a pad  412 . The gates of the PMOS transistors P 1  and P 2  are controlled by a control signal from a pad  410 . 
         [0018]    Differential input signals from pads  418  and  420  are applied to the gates of the NMOS transistors N 1  and N 2 , respectively. The voltage difference between the input signals are reflected by the currents on the two parallel paths of a current mirror constructed by the PMOS transistors P 3  and P 4 , and the NMOS transistors N 1  and N 2 , which in turn generates differential outputs at the pads of  408  and  406 . 
         [0019]    Table 1 below shows the sizes of electronic components in the differential sense amplifier  400  as they are manufactured by various generations of semiconductor processing technologies. 
         [0000]    
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 W/L (n90) 
                 W/L (n65) 
                 W/L (n45) 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 N1 
                 2/0.2 
                 2/0.18 
                    2/0.175 
               
               
                   
                 N2 
                 2/0.2 
                 2/0.18 
                    2/0.175 
               
               
                   
                 N3 
                  1/0.15 
                 2/0.08 
                    2/0.042 
               
               
                   
                 P1 
                  1/0.15 
                 1.2/0.1   
                 0.52/0.07 
               
               
                   
                 P2 
                  1/0.15 
                 1.2/0.1   
                 0.52/0.07 
               
               
                   
                 P3 
                 1/0.2 
                 1/0.12 
                 0.52/0.12 
               
               
                   
                 P4 
                 1/0.2 
                 1/0.12 
                 0.52/0.12 
               
               
                   
                 P5 
                 1/0.1 
                 1.2/0.12   
                 0.52/0.12 
               
               
                   
                 P6 
                 1/0.1 
                 1/0.1  
                 0.52/0.07 
               
               
                   
                 P7 
                 1/0.1 
                 1/0.1  
                 0.52/0.07 
               
               
                   
                   
               
             
          
         
       
     
         [0020]    As shown in table 1, the sizes of the NMOS transistors N 1  and N 2  do not shrink much as the semiconductor processing technology advances from n 90  to n 45 . The reason is that the smaller the NMOS transistors the more susceptible they are to device mismatch due to manufacturing process variations. A serious device mismatch would cause the differential sense amplifier to fail. 
         [0021]      FIG. 5  illustrates a differential sense amplifier unit  500  in accordance with one embodiment of the present invention. The differential sense amplifier unit  500  is comprised of three differential sense amplifiers SA- 1 , SA- 2  and SA- 3 , each of which can be designed as the schematic, for example, shown in  FIG. 4 . The three differential sense amplifiers SA- 1 , SA- 2  and SA- 3  can been seen as one unit that generates a single output reflecting an amplified input. The differential sense amplifiers SA- 1 , SA- 2  and SA- 3  operate under Hamming distance methodology, in which the Hamming distance between two strings of equal length is the number of positions for which the corresponding symbols are different. Table 2 below shows a truth table of the Hamming distance operation. 
         [0000]                                        TABLE 2                           Total Number   Total Number   Hamming       SA-1   SA-2   SA-3   of “1s”   of “0s”   Output                   0   0   0   0   3   0       0   0   1   1   2   0       0   1   0   1   2   0       0   1   1   2   1   1       1   0   0   1   2   0       1   0   1   2   1   1       1   1   0   2   1   1       1   1   1   3   0   1                    
As shown in Table 2, each differential sense amplifier SA- 1 , SA- 2  or SA- 3  generates an output, and the Hamming output (the signal output of the unit  500 ) is determined based on combinations of the logic states of the outputs of the differential sense amplifiers SA- 1 , SA- 2  and SA- 3 . Specifically, the output of the unit  500  is equal to the majority logic states of the outputs from the differential sense amplifiers SA- 1 , SA- 2 , and SA- 3 . For example, if the output of the differential sense amplifier SA- 1  is “1,” the output of the differential sense amplifier SA- 2  is “1” and the output of the differential sense amplifier SA- 3  is “0,” the output of the unit  500  will be 1, whereas if the output of the differential sense amplifier SA- 1  is “0,” the output of the differential sense amplifier SA- 2  is “0” and the output of the differential sense amplifier SA- 3  is “1,” the output of the unit  500  will be 0. The Hamming distance truth table can be expressed by the following equation: Y=C*B+A*C+A*B+A*B*C, where Y denotes the output of the unit  500 , A the output of SA- 1 , B the output of SA- 2 , and C the output of SA- 3 .
 
         [0022]      FIG. 6  illustrates a schematic of a Hamming operation circuit  600  as an exemplar circuit implementation of the above-described three-amplifier Hamming distance operation. The circuit  600  is comprised of AND gates  602 ,  604  and  606 , and an OR gate  608 . The AND gate  602  has one input terminal coupled to an output A from the differential sense amplifier SA- 1 , and another coupled to an output B from the differential sense amplifier SA- 2 . The AND gate  604  has one input terminal coupled to the output B from the differential sense amplifier SA- 2 , and another coupled to an output C from the differential sense amplifier SA- 3 . The AND gate  606  has one input terminal coupled to the output C from the differential sense amplifier SA- 3 , and another coupled to the output A from the differential sense amplifier SA- 1 . The output terminals of the AND gates  602 ,  604  and  606  are coupled to the input terminals of the OR gate  608 , which generates an output based on various combinations of the A, B and C in accordance with the above Hamming distance truth table. 
         [0023]      FIG. 7  illustrates the distributions of offset voltages for differential sense amplifiers of various sizes and configurations. Referring to  FIGS. 5 and 7  simultaneously, the curve  706  shows the distribution of offset voltages for differential sense amplifiers of the same size such as SA- 1 , the curve  704  shows the distribution of offset voltages for differential sense amplifiers of the size equal to the combination of SA- 1 , SA- 2  and SA- 3 , and the curve  702  shows the distribution of offset voltages for the unit  500  that include three small differential sense amplifiers SA- 1 , SA- 2  and SA- 3  operating under the Hamming operation methodology. As shown in the drawing, the curve  706  is flatter and wider than the curve  704 , meaning that a single smaller differential sense amplifier has a higher failure probability than a single larger differential sense amplifier. Likewise, the curve  704  is flatter and wider than the curve  702 , meaning that a differential sense amplifier has a higher failure probability than an equal-sized differential sense amplifier unit having three smaller amplifiers operating under the Hamming distance methodology. The probability that three small differential sense amplifiers fail at the same time is lower than the probability that a large sense amplifier triple the size of the small amplifier fails. In other words, if the expected failure probability of a single differential sense amplifier were set to be the same as that of an amplifier unit having three smaller differential sense amplifiers, the size of the amplifier unit would have been smaller than the large amplifier. 
         [0024]    It is noted that the number of the differential sense amplifiers can exceed three for each amplifier unit. For example, each amplifier unit can include 2*n+1 differential sense amplifiers where n is a natural number, and the logic state of the Hamming output is determined by a majority logic state among those of the outputs from the (2*n+1) differential sense amplifiers. 
         [0025]    One advantage of the present invention is that the proposed multiple differential sense amplifiers operated under the Hamming distance methodology do not require a testing process during an initial period of running an IC. This proposed amplifier unit does not need to select a signal differential sense amplifier for operation, as all outputs from the amplifiers within the unit are considered to generate a final output that represents an input received by the unit. As a result, no additional register is needed for storing the status of the individual differential sense amplifiers. 
         [0026]    The disclosed invention also has the advantage of improving the reliability as the possibility of a plurality of differential sense amplifiers failing at the same time is lower than that of a single differential sense amplifier having the same layout area as the combination of the three smaller ones. In other words, if the reliability of one large differential sense amplifier and that of the proposed amplifier unit are held at the same level, the layout area of the proposed amplifier unit would be smaller than the conventional differential sense amplifier. 
         [0027]    The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims. 
         [0028]    Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.