Abstract:
When a plurality of sub-processors are daisy chained in a loop, for example, to a main processor by a one-way bus, a command packet from the main processor addressed to itself is transmitted to the one-way bus which form a return path back to the main processor so as to easily specify a fault portion. If the command packet is returned to the main processor within a predetermined time, it is determined that no fault exists within the electronic device. When a fault exists, a test signal is transmitted to sub-processors via a dedicated signal line, separate from the one-way bus, to trigger a test packet that will be routed through the one way bus. The faulty portion in the electronic device is specified based on whether the test packet transmitted via the one-way bus in accordance with the test packet from each sub-processor is received within a predetermined time.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a technology for the fault diagnosis of an electronic device including an image forming apparatus.  
           [0003]    2. Description of the Related Art  
           [0004]    In accordance with the high speed of data processing of computer devices, data transfer speed needs to be fast between units or between devices. Consequently, a connecting method between the devices shifts from asynchronous transfer parallel bus connection using a read/write signal to synchronous transfer parallel bus connection (e.g., a PCI bus) using a reference clock. Further, the transfer clock on the bus becomes fast and the serial bus is used to reduce the number of signals on the bus. Japanese Patent Laid-Open No. 2002-230536 discloses a dedicated data transfer method, by which data transfer is not two-way directional but is fixed in the one-way direction. The serial bus reduces the number of signal lines and the physical connection between the devices becomes easy. Since data transfer is one-way, the timing of an interface circuit is designed with allowance.  
           [0005]    Further, Japanese Patent Laid-Open No. 4-100446 discloses contents in which, upon receiving a packet error during packet transfer between devices connected in a ring via a LAN, the network is switched to a backup network from a general network and the faulty device is disconnected. In particular, in an image forming apparatus, unpreferably, one portion of the image forming apparatus is disconnected and is not used. Each portion of the image forming apparatus is connected for executing a series of processing.  
           [0006]    Furthermore, Japanese Patent Laid-Open No. 02-153655 discloses contents in which the loop-back communication test in a communication control integrated circuit determines whether or not the communication control integrated circuit has a fault. To specify the fault portion in the circuit Japanese Patent Laid-Open No. 02-153655 needs the loop-back communication test for an internal portion or the loop-back communication test for an external portion and results in the complicated control. In an apparatus, which does not communicate with the external portion, it is too difficult to specify the fault portion.  
           [0007]    As mentioned above, the serial bus connection between the device and the one-way communication are important technologies for improving the speed of data transfer. However, when the individual devices are connected in a daisy chain or in a loop, if any fault occurs in the connected portion, then the access to all the devices is impossible. Therefore, a user can find only the existence of fault and, inconveniently, the extensive test using a dedicated measuring instrument is necessary for identifying the fault portion.  
           [0008]    A boundary scanning method is popular for fault diagnosis of devices in a factory. However, the boundary scanning method is not suited to the self-diagnosis of devices for maintenance in the field. That is, the boundary scanning method needs one-to-one corresponding relationship between test data and the device and, upon changing the device, the test data must be used in accordance with the changed device. Then, in the self-diagnosis, the version of device is checked and the test data suitable thereto must be selected. However, since device information is not readable while the access to the device is impossible, additional means must be provided, e.g., necessary information is previously stored. Since the test data for boundary scanning method has the size of approximately 100 KB per LSI in the case of a very-large-scale integrated circuit (VLSI), pre-installing the test data has cost impact for embedded.  
           [0009]    It is an object of the present invention to provide an electronic device in which, when a plurality of processors are connected in a loop by a one-way bus, a fault portion in the structure is easily detected.  
         SUMMARY OF THE INVENTION  
         [0010]    According to the present invention, there is provided an electronic device having connecting means for connecting, in a loop, a main control portion for controlling the electronic device and a plurality of sub-processing portions for executing specific functions, comprising: a signal line for transmitting a test signal from the main control portion to the sub-processing portions, different from the connecting means connected in the loop; a generating unit for generating predetermined packet data to the connecting means; sub-processing portions comprising a receiving and transmitting unit for receiving the packet data and transmitting it to the next portion; a determining unit for determining whether or not a fault exists at any portion in the electronic device in accordance with whether or not the sub-processing portion normally receives the packet data transmitted to the main control portion; a transmitting unit for transmitting the test signal to the sub-processing portions via the signal line in case that the determining unit determines that the fault exists; and a fault portion specifying unit for specifying a fault portion in the electronic device based on whether or not a test packet transferred via the connecting means is normally received, wherein the test packet is generated by the sub-processing portion in accordance with the test signal.  
           [0011]    In addition, according to the present invention, there is provided an electronic device having connecting means for connecting, in a loop, a main control portion for controlling the electronic device and a plurality of sub-processing portions for executing specific functions, comprising: a signal line for transmitting a test signal from the sub-processing portions to the main control portion, different from the connecting means connected in the loop; a generating unit for generating predetermined packet data to the connecting means; sub-processing portions comprising a receiving and transmitting unit for receiving the packet data and transmitting it to the next portion; a determining unit for determining whether or not a fault exists at any portion in the electronic device in accordance with whether or not the sub-processing portion normally receives the packet data transmitted to the main control portion; a transmitting unit for transmitting a test packet to the connecting means in case that the determining unit determines that the fault exists; and a fault portion specifying unit for specifying a fault portion of the electronic device based on a state of the test signal transmitted via the corresponding signal line from the sub-processing portions in accordance with the test packet.  
           [0012]    In addition, according to the present invention, there is provided an electronic device having connecting means a main control portion for controlling the device and a plurality of sub-processing portions for executing specific functions in a loop, comprising: a signal line for transferring a test signal, arranged between the sub-processing portion and the main control portion, different from the connecting means; a generating unit for generating predetermined packet data to the connecting means; sub-processing portions comprising a receiving and transmitting unit for receiving the packet data and transmitting it to the next portion; a determining unit for determining whether or not a fault exists at any portion in the electronic device in accordance with whether or not the sub-processing portion normally receives the packet data transmitted to the main control portion; and a fault portion specifying unit for specifying a fault portion in the electronic device via the corresponding signal line between the sub-processing portion and the main control portion in case that the determining unit determines that the fault exists. 
       
    
    
       [0013]    Further, objects, features, and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the attached drawings.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    [0014]FIG. 1 is a diagram showing the structure of a digital color copying machine according to a first embodiment;  
         [0015]    [0015]FIG. 2 is a diagram showing the structure of a main processor according to the first embodiment;  
         [0016]    [0016]FIG. 3 is a diagram showing the structure of an image output processor according to the first embodiment;  
         [0017]    [0017]FIG. 4 is a diagram showing the structure of an imaging processor according to the first embodiment;  
         [0018]    [0018]FIG. 5 is a diagram showing the structure of an image input processor according to the first embodiment;  
         [0019]    [0019]FIG. 6 is a diagram showing the structure of an interface between the processors according to the first embodiment;  
         [0020]    [0020]FIG. 7A is a diagram showing an example of the structure of a data packet according to the first embodiment;  
         [0021]    [0021]FIG. 7B is a diagram showing an example of the structure of a command packet according to the first embodiment;  
         [0022]    [0022]FIG. 7C is a diagram showing an example of the structure of an interrupt packet according to the first embodiment;  
         [0023]    [0023]FIG. 8 is a diagram showing an example of the structure of an interrupt packet for test according to the first embodiment;  
         [0024]    [0024]FIG. 9 is a flowchart showing fault diagnosis processing according to the first embodiment;  
         [0025]    [0025]FIG. 10 is a diagram showing the structure of a digital color copying machine according to a second embodiment;  
         [0026]    [0026]FIG. 11 is a diagram showing the structure of a main processor according to the second embodiment;  
         [0027]    [0027]FIG. 12 is a diagram showing the structure of an image output processor according to the second embodiment;  
         [0028]    [0028]FIG. 13 is a showing the structure of an imaging processor according to the second embodiment;  
         [0029]    [0029]FIG. 14 is a diagram showing the structure of an image input processor according to the second embodiment; and  
         [0030]    [0030]FIG. 15 is a flowchart showing fault diagnosis processing according to the second embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]    Hereinbelow, preferred embodiments of the present invention will be described with reference to the drawings.  
       First Embodiment  
       [0032]    [0032]FIG. 1 is a diagram showing the structure of a digital color copying machine (image forming apparatus) as an electronic device according to a first embodiment of the present invention. Here, the digital color copying machine is described and, however, it is not limited to this and the electronic device may be a printer, a scanner, an image communication device for transmitting image data via a communication network, or a digital camera.  
         [0033]    Referring to FIG. 1, reference numeral  101  denotes a main processor (hereinafter, referred to as a MAIN) for systematically controlling the digital color copying machine, reference numeral  102  denotes a synchronous dynamic memory (hereinafter, referred to as a RAM) which functions as a main memory of the MAIN  101 , reference numeral  103  denotes a read only memory (hereinafter, referred to as a ROM) which stores a boot-up program, etc., and reference numeral  104  denotes a hard disk (hereinafter, referred to as an HD) which stores a control program, etc.  
         [0034]    Reference numeral  105  denotes a local area network (hereinafter, referred to as a LAN) in conformity with Ethernet (registered trademark), reference numeral  106  denotes an image output processor (hereinafter, referred to as a VO) which executes a function for outputting image data to a printer, and reference numeral  107  denotes a printer unit.  
         [0035]    Reference numeral  108  is an imaging processor (hereinafter, referred to as an IP) for the rotation of image, the enlargement and reduction of the image, and for color correction. Reference numeral  109  denotes a synchronous dynamic memory (hereinafter, referred to as a RAM) having a function as a work memory for image processing in the IP  108 , reference numeral  110  denotes an image input processor (hereinafter, referred to as a VI) having a function for inputting the image data from a scanner unit  111 , and reference numeral  111  denotes a scanner unit.  
         [0036]    The VO  106 , IP  108 , and VI  110  are sub-processors which execute the specific functions to the MAIN  101 . The MAIN  101 , the VO  106 , the IP  108 , and the VI  110  are connected in a loop by a one-way serial bus (hereinafter, simply referred to as a serial bus), and the data is transmitted between the processors. Referring to FIG. 1, the MAIN  101  is connected to the VO  106  by a serial bus  112   a  through which a signal is transmitted from the MAIN  101  to the VO  106 , the VO  106  is connected to the IP  108  by a serial bus  112   b  through which the signal is transmitted from the VO  106  to the IP  108 , the IP  108  is connected to the VI  110  by a serial bus  112   c  through which the signal is transmitted from the IP  108  to the VI  110 , and the VI  110  is connected to the MAIN  101  by a serial bus  112   d  through which the signal is transmitted from the VI  110  to the MAIN  101 .  
         [0037]    According to the first embodiment, signal lines  113   a,    113   b,  and  113   c  for transmitting test signals which will be described later are further connected from the MAIN  101  to the sub-processors, namely, to the VO  106 , the IP  108 , and the VI  110 . The signal lines  113   a  to  113   c  are connected independently of the serial buses.  
         [0038]    With the above structure, the MAIN  101  converts the image data held on the RAM  102  into packet data and transfers it to the VO  106 , thus outputting the data by the printer unit  107  and forming the image. The image data held on the RAM  102  is transferred to the IP  108  and is subjected to the image processing, thereby rotating, enlarging, and reducing the image and correcting the color of the image. Further, the MAIN  101  receives scanning image data of the scanner unit  111  received by the VI  110  and stores it on the RAM  102 . Furthermore, the MAIN  101  communicates, via the LAN  105 , with another device such as a computer on the network.  
         [0039]    The MAIN  101 , the VO  106 , the IP  108 , and the VI  110  are very-large-scale integrated circuits (VLSIs) and the detailed description is given of them hereinbelow.  
         [0040]    The MAIN  101  has the internal structure as shown in FIG. 2.  
         [0041]    Reference numeral  201  denotes a CPU, reference numeral  202  denotes a cross bar switch (hereinafter, referred to as XB), reference numeral  203  denotes a physical-layer interface (hereinafter, referred to as a PHY) for connection to a physical layer of Ethernet, reference numeral  204  denotes a LAN controller (hereinafter, referred to as a LANC) for communication on the local area network, reference numeral  205  denotes a memory controller (hereinafter, referred to as MC), reference numeral  206  denotes a serial bus output interface (hereinafter, referred to as SBO), reference numeral  207  denotes a serial bus input interface (hereinafter, referred to as SBI), reference numeral  208  denotes a hard disk controller (hereinafter, referred to as an HDC), reference numeral  209  denotes an input/output port (hereinafter, referred to as an I/O), and reference numeral  210  denotes an interrupt controller (hereinafter, referred to as an IC).  
         [0042]    The CPU  201  controls overall operation of the apparatus by executing program code held in the ROM  103  and the RAM  102 . The ROM  103  stores the boot-up program, and the CPU  201  starts to execute contents of the ROM  103  upon starting the apparatus. A control program stored in the HD  104  is loaded to the RAM  102  and the boot-up program jumps the control program, thereby starting the execution of the control program.  
         [0043]    The XB  202  transfers the data between the units in the MAIN  101  in accordance with address spaces allocated to the units. Further, the XB  202  has an arbitrating function upon the simultaneous access of a plurality of units.  
         [0044]    The LANC  204  and the PHY  203  have a function for communication with other devices via the network. The MC  205  controls the access to the RAM  102  and the ROM  103 . The SBO  206  is an interface circuit for outputting data of the serial bus, converts the data stored in the RAM  102  into predetermined packet data, and transmits the converted packet data. The SBI  207  is a serial bus input interface, which converts the received packet data into internal data, and transfers the converted data to a predetermined unit.  
         [0045]    The HDC  208  is a control circuit for inputting and outputting data of the HD  104 , and controls the hard disk by, e.g., an Ultra DMA method. The HD  104  has function for storing program data executed by the CPU  201  and storing the image data stored on the RAM  102 . The I/O  209  is an input/output port and has three output ports for TEST 1 , TEST 2 , and TEST 3  signals according to the first embodiment which are transferred via the signal lines  113   a,    113   b,  and  113   c.  At the three output ports, the CPU  201  sets the logical level of the TEST 1 , TEST 2 , and TEST 3  signals to the H/L level.  
         [0046]    The IC  210  is a unit which processes the interrupt in the MAIN  101 , collects information on the interrupts caused in the units of the portions and on an interrupt packet received by the SBI  207 , and notifies the information to the CPU  201 .  
         [0047]    [0047]FIG. 3 is a diagram showing the structure of the VO  106 .  
         [0048]    Referring to FIG. 3, reference numeral  301  denotes a serial bus input interface (hereinafter, referred to as an SBI), reference numeral  302  denote a serial bus output interface (hereinafter, referred to as an SBO), reference numeral  303  denotes a packet interpreter (hereinafter, referred to as a PI), reference numeral  304  denotes an image processing unit for printer (hereinafter, referred to as a PIP) for printer, reference numeral  305  denotes a printer output interface (hereinafter, referred to as a PRC), reference numeral  306  denotes a serial communication unit (hereinafter, referred to as a UART), and reference numeral  307  denotes an interrupt controller (hereinafter, referred to as an IC).  
         [0049]    The SBI  301  and the SBO  302  basically has the same functions as those incorporated in the MAIN  101 . The PI  303  is a unit which determines which is the packet data received via the SBI  301  from the serial bus  102   a,  and determines whether the packet data is the command packet, the data packet, or the interrupt packet, as will be described later. The PI  303  determines whether or not the received packet data is for the VO  106  and further determines whether or not it is for the unit in the VO  106 . When the received packet data is for another processor, the PI  303  promptly transmits the packet data from the SBO  302  to the serial bus  102   b,  and further transmits it to the next unit (namely, the IP  108 ).  
         [0050]    When the received packet is a command packet indicating a command to a unit in the VI  301 , the register in the unit reads/writes the data. When the received packet is the data packet for the PIP  303 , the image data as contents of the data packet is transferred to the PIP  304 . The PIP  304  converts the received image data into data suitable for the output by the printer unit  107 , the PRC  305  transfers the data to the printer unit  107 , and it executes the printing operation.  
         [0051]    The PIP  304  has a function for converting a received RGB image into CMYK-color data and a γ curve converting function for correcting the property of the printer unit  107 . The PRC  305  has functions for converting the image data into data at the operating speed of the printer unit  107  and outputting it. The UART  306  is a unit for communication with the printer unit  107 , and detects a state of the printer unit  107  and instructs the printing operation.  
         [0052]    An IC  307  detects an interrupt factor in the VO  106  and instructs the generation of the interrupt packet to the PI  303 . The generated interrupt packet is transmitted to the next processor via the SBO  302 . The interrupt factor of the IC  307  is cleared and is masked depending the command packet. The IC  307  receives the TEST 1  signal from the MAIN  101  and, then, instructs the generation of an interrupt packet for test to the PI  303 , which will be described later. Consequently, even in a state in which the data is not read/written to the registers of the units in the VO processor and the command packet is not received, the interrupt packet for test is generated and is transmitted to the serial bus. Therefore, in the case in which the abnormal state occurs in the VO processor and the command packet is not outputted to the IP  108 , the VI  110 , and the MAIN  101  at the latter stage, it is checked to see if the communication interface normally functions with the IP  108 , the VI  110 , and the MAIN  101  at the latter stage.  
         [0053]    [0053]FIG. 4 is a diagram showing the structure of the imaging processor IP  108 .  
         [0054]    Reference numeral  401  denotes a serial bus input interface (hereinafter, referred to as an SBI), reference numeral  402  denotes a serial bus output interface (hereinafter, referred to as an SBO), reference numeral  403  denotes a packet interpreter (hereinafter, referred to as a PI), reference numeral  404  denotes an interrupt controller (hereinafter, referred to as an IC), reference numeral  405  denotes a resolution converting unit (hereinafter, referred to as an RSC), reference numeral  406  denotes a memory controller (hereinafter, referred to as an MC), reference numeral  407  denotes a binarizing unit (hereinafter, referred to as a BI), and reference numeral  408  denotes a rotating unit (hereinafter, referred to as an ROT).  
         [0055]    The SBI  401 , the SBO  402 , and the PI  403  have the same functions as those of the VO  106 . When the received packet data is the command packet for the unit in the IP  108 , the PI  403  reads/writes the data in the register in the unit. When the received packet data is the data packet for the unit in the IP  108 , the PI  403  transmits the data to the unit and further transmits, from the SBO  402 , the data which is processed by the unit and is returned.  
         [0056]    The RSC  405  converts the resolution of the data, thereby enlarging or reducing the data. The MC  406  is a unit which controls the access to the RAM  109 , and enables the unit in the IP  108  to use the RAM  109  as a work area.  
         [0057]    The BI  407  has a function for halftone processing of multi-value data and converting the processed data into binary data. The function of the BI  407  is mainly used upon binarizing the scanned image before transferring it to the computer.  
         [0058]    The ROT  408  executes the rotation of the image, and has a function for rotating the input image data by an angle of 90° on the unit basis and generating a new packet.  
         [0059]    The IC  404  detects the interrupt factor caused in the IP  108 , and instructs the generation of the interrupt packet to the PI  403 . The IC  404  receives the TEST 2  signal from the MAIN  101  and, then, instructs the generation of the interrupt packet for test to the PI  403 , which will be described later.  
         [0060]    Consequently, even in a state in which the data is not read/written to the registers of the units in the IP processor and the command packet is not received, the interrupt packet for test is generated and is transmitted to the serial bus. Therefore, in the case in which the abnormal state occurs in the IP processor and the command packet is not outputted to the VI  110  and the MAIN  101  at the latter stage, it is checked to see if the communication interface normally functions with the VI  110  and the MAIN  101  at the latter stage.  
         [0061]    [0061]FIG. 5 is a diagram showing the structure of the VI  110 .  
         [0062]    Reference numeral  501  denotes a serial bus input interface (hereinafter, referred to as an SBI), reference numeral  502  denotes a serial bus output interface (hereinafter, referred to as an SBO), reference numeral  503  denotes a packet interpreter (hereinafter, referred to as a PI), reference numeral  504  denotes a scanner input interface (hereinafter, referred to as an SCC), reference numeral  505  denotes a serial communication controller (hereinafter, referred to as a UART), and reference numeral  506  denotes an interrupt controller (hereinafter, referred to as an IC).  
         [0063]    The SBI  501 , the SBO  502 , the PI  503 , and the IC  506  have the same functions as those of the VO  106 . The SCC  504  is an interface which receives the image data transmitted from the scanner unit  111  and transmits it to the PI  503 . The PI  503  converts the received data into the data packet, and transmits the converted data from the SBO  502 . The UART  505  communicates with the scanner unit  111 . The IC  506  receives the TEST 3  signal from the MAIN  101  and, then, instructs the generation of the interrupt packet for test to the PI  503 , which will be described later.  
         [0064]    Consequently, even in a state in which the data is not read/written to the registers of the units in the VI processor and the command packet is not received, the interrupt packet for test is generated and is transmitted to the serial bus. Therefore, in the case in which the abnormal state occurs in the VI processor and the command packet is not outputted to the MAIN  101  at the latter stage, it is checked to see if the communication interface normally functions with the MAIN  101  at the latter stage.  
         [0065]    Next, the structure of the serial bus will briefly be described. FIG. 6 shows the structure of the serial bus for connecting the SBO  502  in the processors and the SBI  501  in the processor next thereto.  
         [0066]    Synchronously to a clock (hereinafter, referred to as a CLK)  60  (60 MHz), data having a 64-bit width is transmitted to the SBO  502  in the processor. The SBO  502  converts the CLK  60  into a CLK  480  (480 MHz) by multiplying the CLK  60  by eight and transmits the serial data having the data width on 8-bit unit basis. That is, the number of CLKs is eight times and the data width is ⅛ and, therefore, the data transfer speed in the processor is the same as that on the serial bus. A START signal is a signal indicating the head of the packet data.  
         [0067]    The SBI  501  detects the START signal, then, fetches the data synchronously to the CLK  480 , returns it to 64-bit data synchronous to the CLK  60  (60 MHz) therein, and transfers the 64-bit data to the processor. Referring to FIG. 6, a WAIT signal is asserted when the SBI  501  temporarily does not receive the packet data due to some factor. During asserting the WAIT signal, the SBO  502  stops the output. The SBO  502  and the SBI  501  include a buffer in which the buffer overflow is prevented while controlling the WAIT signal.  
         [0068]    Next, the format of packet data will be described. FIG. 7A is a diagram showing the structure of the data packet, FIG. 7B is a diagram showing the structure of the command packet, and FIG. 7C is a diagram showing the structure of the interrupt packet. In any packet, 16-byte data is a header portion indicating the property of the packet, and sequentially continues to the data portion.  
         [0069]    Referring to FIG. 7A, the header portion in the data packet contains, starting from the head, s packet type, s chip ID, an image type, a job ID, s processing command, and a data length.  
         [0070]    The packet type identifies the format of packet data. For example, reference numeral  00 H denotes the data packet, reference numeral  01 H denotes the command packet, and reference numeral  02 H denotes the interrupt packet.  
         [0071]    The chip ID indicates to which processor the packet data is addressed. Since the chip IDs are individually allocated to the processors, each processor determines that the packet data addressed thereto by checking the property of the chip ID.  
         [0072]    The image type indicates the property of the image data included in the data packet, reference numeral  00 H denotes an RGB color image having  24  bits, reference numeral  01 H denotes a monochrome image having 8 bits, and reference numeral  02 H denotes a YUV color image.  
         [0073]    With respect to the job ID, upon dividing the large-sized data into a plurality of pieces of packet data and processing them, the same job ID is allocated to the same data so as to identify the same data.  
         [0074]    The processing command indicates the property for prescribing which of the units in the processors performs which processing. For example, when the IP  108  executes the resolution conversion, the processing command designates the unit number and the processing mode of the RSC  405 , thereby executing a predetermined operation.  
         [0075]    The data length is a field indicating the actual data length after the header portion. The data length of the data packet is indicated by an integer multiple of 16 bytes, and the remainder is set as padding. The SBOs  206 ,  302 ,  402 , and  502  in each processor performs the processing so that the data length is the multiple of 16 bytes by adding the data  00 H.  
         [0076]    In the case of the command packet shown in FIG. 7B, as mentioned above, the packet type indicates  01 H, the chip ID indicates the same meaning as that of the data packet. In the fields of the command type (hereinafter, referred to as a CMD TYPE) and the command number (hereinafter, referred to as a CMD NUM), the command packet instructs the command for the processor. The CMD TYPE indicates the execution of the writing operation in the case of the packet type  00 H and of the reading operation in the case of the packet type  01 H. The CMD NUM indicates the number of commands in the data portion. In accordance with the CMD NUM, a pair of the address and the data of the register which should read/write the data is written to the data portion. The command portion is an integer multiple of 16 bytes and a short portion of the integer multiple has padding of  00 H by using the SBOs  206 ,  302 ,  402 , and  502 .  
         [0077]    The interrupt packet shown in FIG. 7C indicates the packet type  02 H, and includes the chip ID of the processor having the interrupt and the unit ID having the interrupt in the header portion. Only the MAIN  101  processes the interrupt packet and, therefore, the chip ID of the header portion indicates not the address but the processor having the interrupt. The field of a factor register of the unit indicating the interrupt contents is usually copied to the data portion. The interrupt data portion is an integer multiple of 16 bytes, and a short portion of the integer multiple has the padding of  00 H by the SBOs  206 ,  302 ,  402 , and  502 .  
         [0078]    According to the first embodiment, the structure of the digital color copying machine is as mentioned above. Next, a detailed description is given of fault diagnosis processing of the digital color copying machine as the electronic device according to the first embodiment.  
         [0079]    [0079]FIG. 9 is a flowchart showing the fault diagnosis processing according to the first embodiment. A program corresponding to the flowchart shown in FIG. 9 is included in the program stored in the HD  104 , is loaded to the RAM  102 , and is executed by the CPU  201  in the MAIN  101 .  
         [0080]    The MAIN  101  transmits the command packet addressed thereto from the SBO  206  to the serial bus  112   a  (step S 1 ). In place thereof, the MAIN  101  may transmit the command packet for setting the chip ID which does not exist on the serial bus loop. When the circuit connection is not abnormal, the processor other than the MAIN  101  doesn&#39;t recognize the packet addressed thereto. Then, the packet data is transmitted to the next processor and, therefore, the packet data is to be returned to the SBI  207  of the MAIN  101 .  
         [0081]    It is determined whether or nor the transmitted packet data is normally returned (step S 2 ). If the transmitted packet data is normally returned, it is determined that it is “no abnormal”. If the transmitted packet data is not normally returned or the packet data is broken, any processor has the fault or it is considered that the serial bus for connecting the processors is abnormal. In this case, the processing sequent to step S 3  generates the interrupt packet for the diagnosis to the processors and tests the processors and the connection between the processors.  
         [0082]    The TEST 3  signal from the I/O port  209  is asserted to the VI  110  at the most downstream position of the serial bus loop starting from the MAIN  101  (step S 3 ).  
         [0083]    The IC  506  of the VI  110  receives the TEST 3  signal and, then, instructs the PI  503  to generate the predetermined interrupt packet for test (hereinafter, simply referred to as a “test packet”) as mentioned above. As a result, the VI  110  transmits the test packet to the serial bus  112   d.    
         [0084]    [0084]FIG. 8 shows an example of the data structure of the interrupt packet for test. The structure of the interrupt packet is the same as that shown in FIG. 7C. However, the data embedded in the data portion is not data on the actual interrupt but the test data for the data signal having 8 bits on the serial bus. That is, the data portion comprises the test data which determines that the signal changes to 1 or 0 corresponding to the 8 bits of the data signal and that the data signals are transmitted normally.  
         [0085]    The MAIN  101  determines whether or not the test packet is normally received from the VI  110  (for example, whether or not it is received for a predetermined time) (step S 4 ). When the test packet is not received for the predetermined time, it is determined that the operation of the VI  110  or the connection between the MAIN  101  and the VI  110  is abnormal. When the test packet is received for the predetermined time, the chip ID and the unit ID of the interrupt packet is stored in the register of the IC  210 . The data portion is stored at a predetermined address in the RAM  102 . After that, the interrupt is notified to the CPU  201 . The CPU  201  receives the interrupt packet and, then, checks the chip ID, the unit ID, and the data of the data portion of the processor in which the interrupt packet is caused. Thus, the CPU  201  confirms that the VI  110  normally transmits the interrupt packet for test and that at least the connection between the VI  110  and the MAIN  101  and the operation of the VI  110  is normal. In this case, the processing sequence advances to step S 5 .  
         [0086]    In step S 5 , the TEST 2  signal of the I/O  209  is asserted and, in accordance therewith, it is determined whether or not the test packet to be transferred from the IP  108  is received for a predetermined time (step S 6 ). When it is determined that the test packet is not received for the predetermined time, it is determined that the operation of the IP  108  or the connection between the VI  110  and the IP  108  is abnormal. When it is determined that the test packet is received normally for the predetermined time, the operation of the IP  108  or the connection between the VI  110  and the IP  108  is not abnormal. The processing sequence advances to step S 7 .  
         [0087]    In step S 7 , the TEST 1  signal of the I/O  209  is asserted and, in accordance therewith, it is determined whether or not the test packet to be transferred from the VO  106  is received for a predetermined time (step S 8 ). When it is determined that the test packet is not received for the predetermined time, it is determined that the operation of the VO  106  or the connection between the IP  108  and the VO  106  is abnormal. When it is determined that the test packet is received for the predetermined time, it is determined that the operation of the MAIN  101  or the connection between the VO  106  and the MAIN  101  is abnormal.  
         [0088]    In the above-mentioned fault diagnosis processing, depending on whether or not to receive, for a predetermined time, the test packet to be transferred via the one-way serial bus from the sub-processor in accordance with the test signal transferred via the dedicated signal line from the main processor, the fault portion is specified in the electronic device. The test signal may be transmitted in any order. However, as mentioned above, it is efficient that the fault portion is specified by sequentially testing the sub-processors starting from one at the most downstream of the bus loop having the main processor at the start point.  
         [0089]    Consequently, even in a state in which the sub-processor does not transmit the command packet from the MAIN  101  to the unit at the latter stage via the serial bus, the interrupt packet for test is generated in the sub-processor in accordance with the instruction of the MAIN  101  via the signal line and it is transmitted to the serial bus. Therefore, the interrupt packet for test is transmitted to the serial bus at the latter stage and thus it is checked to see if the communication interface normally functions with the processor at the latter stage and the abnormal state is specified.  
       Second Embodiment  
       [0090]    According to the first embodiment, the sub-processors transmit the test packet to the serial bus in accordance with the test signal transferred via the dedicated signal line from the main processor. Advantageously, with a contrary relationship between the test signal from the main processor and the test packet from the sub-processor, the sub-processor transmits the test signal via the dedicated signal line to the main processor in accordance with the test packet transferred from the main processor to the serial bus.  
         [0091]    The structure will be described in detail with reference to the drawings. In the following drawings, the same portions as those according to the first embodiment are designated by the same reference numerals, they are not described, and only different portions are described.  
         [0092]    [0092]FIG. 10 is a diagram showing the structure of a digital color copying machine according to the second embodiment, corresponding to FIG. 1. The signal lines  113   a,    113   b,  and  113   c  shown in FIG. 1 are signals lines to the corresponding sub-processors from the MAIN  101 . On the other hand, signal lines  100   a,    100   b,  and  100   c  shown in FIG. 10 are signals lines from the corresponding sub-processors to the MAIN  101 .  
         [0093]    [0093]FIG. 11 is a diagram showing the internal structure of the MAIN  101  according to the second embodiment, corresponding to FIG. 2. The I/O  209  has three input ports of the TEST 1 , TEST 2 , and TEST 3  signals.  
         [0094]    [0094]FIG. 12 is a diagram showing the structure of the VO  106  according to the second embodiment, corresponding to FIG. 3. The IC  307  shown in FIG. 3 receives the TEST 1  signal and, then, instructs the generation of the test packet to the PI  303 . However, the VO  106  shown in FIG. 12 includes an input/output port (hereinafter, referred to as an I/O)  308  and the I/O  308  operates so that the TEST 1  signal is asserted in accordance with the instruction from the PI  303  which receives the test packet.  
         [0095]    [0095]FIG. 13 is a diagram showing the structure of the IP  108  according to the second embodiment, corresponding to FIG. 4. The IC  404  shown in FIG. 4 receives the TEST 2  signal and, then, instructs the generation of the test packet to the PI  403 . However, the IP  108  shown in FIG. 13 includes an input/output port (hereinafter, referred to as an I/O)  409 , and the I/O  409  operates so that the TEST 2  signal is asserted in accordance with the instruction from the PI  403  which receives the test packet.  
         [0096]    [0096]FIG. 14 is a diagram showing the structure of the VI  110  according to the second embodiment, corresponding to FIG. 5. Referring to FIG. 5, the IC  506  receives the TEST 3  signal and, then, instructs the generation of the test packet to the PI  503 . However, referring to FIG. 14, the VI  110  has the input/output port (hereinafter, referred to as an I/O)  507  and the I/O  507  operates to assert the TEST 3  signal in accordance with the instruction from the PI  503  which receives the test packet.  
         [0097]    [0097]FIG. 15 is a flowchart showing the fault diagnosis processing according to the second embodiment. A program corresponding to the flowchart shown ion FIG. 15 is included in the program stored in the HD  104  and, as mentioned above, it is loaded to the RAM  102  and is executed by the CPU  201  in the MAIN  101 .  
         [0098]    First, the MAIN  101  transmits the command packet addressed thereto from the SBO  206  to the serial bus  100   a  (step S 21 ). When the circuit connection is normal, the MAIN  101  recognizes that another processor has the packet data having the chip ID different from that of the MAIN  101  and the packet data is transmitted to the next processor. Thus, the packet data is to be returned to the SBI  207  in the MAIN  101 .  
         [0099]    Then, it is determined whether or not the transmitted packet data is normally returned (step S 22 ). If it is determined that the packet data is normally returned, it is determined that “no abnormal”. On the other hand, if it is determined that the packet data is not normally returned or that the packet data is broken, it is determined that any of the processors has a fault or the serial bus for connecting between the processors is abnormal. In this case, in the processing subsequent to step S 23 , the test packet is transmitted and, thereby, the transmission of the test signal from the sub-processors causes the test of the processors and of the connection between the processors. The MAIN  101  transmits the test packet with the structure shown in FIG. 8 to the serial bus  112   a  (step S 23 ).  
         [0100]    The test packet is a specific packet for diagnosis which is defined by the packet type  04 H in the header portion. The sub-processor receives the packet and, then, detects the test mode. Further, it is tested whether or not the test data portion matches the data which is previously stored. When it is confirmed that the test data portion is correctly received, the TEST signal is asserted and the test packet is transferred to the next processor.  
         [0101]    The VO  106  receives the test packet and, then, the PI  303  instructs the I/O  308  to assert the TEST 1  signal and transmits the test packet from the SBO  302  to the next IP  108 . Similarly, the PI  403  of the IP  108  receives the test packet and, then, allows the I/O  409  to assert the TEST 2  signal and transmits the test packet from the SBO  402 . Further, the VI  110  receives the test packet and, then, the PI  503  allows the I/O  507  to assert the TEST 3  signal and transmits the test packet from the SBO  502 .  
         [0102]    When the MAIN  101  transmits the test packet in step S 23 , it waits for a predetermined time (step S 24 ). By checking the levels (statuses) of the TEST 1 , TEST 2 , and TEST 3  signals from the input ports, it is determined whether or not the VO  106 , the IP  108 , and the VI  110  normally receive the packet data for test.  
         [0103]    In step S 25 , it is checked to see if the TEST 1  signal from the VO  106  has the high level (referred to as an HI). When the TEST 1  signal does not have the HI, it is determined that the operation of the VO  106  or the connection between the MAIN  101  and the VO  106  is abnormal. When the TEST 1  signal is HI, it is determined that at least the operation of the VO  106  or the connection between the MAIN  101  and the VO  106  is not abnormal. Then, the processing sequence advances to step S 26 .  
         [0104]    In step S 26 , it is checked to see if the TEST 2  signal from the IP  108  is HI. When it is determined that the TEST 2  signal is not HI, the operation of the IP  108  or the connection between the VO  106  and the IP  108  is abnormal. When it is determined that TEST 2  signal is HI, it is determined that at least the operation of the IP  108  or the connection between the VO  106  and the IP  108  is not abnormal and the processing sequence advances to step S 27 .  
         [0105]    In step S 27 , it is determined whether or not the TEST 3  signal from the VI  110  is HI. When it is determined that the TEST 3  signal is not HI, it is determined that the operation of the VI  110  or the connection between the IP  108  to the VI  110  is abnormal. When it is determined that the TEST 3  signal is HI, it is determined that the operation of the MAIN  101  or the connection between the VI  110  and the MAIN  101  is abnormal.  
         [0106]    As mentioned above, according to the second embodiment, the fault portion is specified by determining whether or not the test signal is received from the sub-processor in accordance with the test packet for a predetermined time. Consequently, even in a state in which the sub-processor does not transmit the command packet from the MAIN  101  to the unit at the latter stage via the serial bus, the interrupt packet for test is generated in the sub-processor in accordance with the instruction of the MAIN  101  via the signal line and it is transmitted to the serial bus. Therefore, the interrupt packet for test is transmitted to the serial bus at the latter stage and thus it is checked to see if the communication interface normally functions with the processor at the latter stage and the abnormal state is specified.  
         [0107]    A brief description is given of the fault diagnosis processing of the electronic device according to the second embodiment. That is, the electronic device comprises the main processor for entirely controlling the electronic device and the sub-processors for executing the specific functions, which are connected to each other in a loop by a one-way bus. Further, the electronic device comprises the signal line for transmitting the test signal from the sub-processors to the main processor, unlike the one-way bus. In the fault diagnosis processing, first, the main processor transmits the predetermined packet data to the one-way bus, and determines whether or not the fault exists at any portion in the electronic device in accordance with whether or not the packet data is normally returned to the main processor. Next, when it is determined that the fault exists, the test packet is transmitted to the one-way bus and the fault portion in the electronic device is specified based on the state of the test signal which is transmitted via the corresponding signal line from the sub-processor in accordance with the test packet.  
         [0108]    According to the first and second embodiments, the digital color copying machine is described as the examples. However, the present invention is not limited to these, and can widely be applied to electronic devices including a computer device and various image processing apparatuses in which a plurality of processors realize a predetermined function in cooperation therewith.  
       Other Embodiments  
       [0109]    The first and second embodiments of the present invention are described in detail as mentioned above. However, the present invention can be applied to a system comprising a plurality of devices or an apparatus comprising a single device. Further, the present invention can be applied to the fault diagnosis method of the electronic device.  
         [0110]    The present invention is accomplished by directly or remotely supplying, to a system or an apparatus, the program (corresponding to the flowchart shown in FIG. 9 or FIG. 15) of software for realizing the functions of the first and second embodiments and by reading and executing the supplied program code by a computer in the system or apparatus. In this case, any format having the program functions can be used.  
         [0111]    Therefore, the present invention is realized by the program code installed to the computer so as to realize the functions and processing of the present invention by the computer. That is, the claims of the present invention include the computer program for realizing the functions and the processing of the present invention.  
         [0112]    In this case, any program format having the above functions can be used, e.g., object code, a program executed by an interpreter, script data supplied to an OS, etc.  
         [0113]    As for a recording medium to supply the program, it is able to use a floppy disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD-R), and the like.  
         [0114]    In addition, as a method for supplying the program, a homepage on the Internet is accessed by using a browser of a client computer, and the computer program of the present invention is supplied by the homepage or a compressed file including an automatic install function is loaded to the recording medium such as a hard disk. Further, the program code forming the program of the present invention is divided into a plurality of files and the files are downloaded from the different homepages. That is, the claims of the present invention include a WWW server which allows a plurality of users to download the program file for executing the functions and the processing of the present invention by the computer.  
         [0115]    The program of the present invention is enciphered, is stored in a storage medium such as a CD-ROM, and is distributed to users. Key information for decipher on a homepage via the Internet is downloaded by the user which passes a predetermined condition, and the enciphered program is executed by using the key information and is installed to the computer.  
         [0116]    The functions of the aforementioned embodiment can be effected not only by executing the program which is read out by the computer, but also by executing a part or all of the actual processing on the OS (Operating System) which operates on the computer based on the instruction of the program.  
         [0117]    In addition, the functions according to the first and second embodiments are executed by the program read from the recording medium to a memory included in a function expansion board inserted in the computer or a function extension unit connected to the computer and by thereafter entirely or partly executing the actual processing based on the instruction of the program by the CPU of the function expansion board or the function extension unit.  
         [0118]    According to the embodiments of the present invention, it is possible to provide the electronic device in which the portion having the fault is easily specified when a plurality of processors are connected in a loop by the one-way bus.  
         [0119]    It is to be understood that the phraseology or terminology employed herein in for the purpose of description and not of limitation. While the invention has been described with reference to the structures disclosed herein, it is not confined to the details set forth and this application is intended to cover such modifications or changes as may come within the purposes of the improvements or the scope of the following claims.