Abstract:
A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates generally to the field of semiconductor integrated circuits and, more particularly, to an improved SiGe device with SiGe-embedded dummy pattern that encircles the SiGe device, which is capable of alleviating the micro-loading effect during the epitaxial growth of SiGe. 
   2. Description of the Prior Art 
   As known in the art, stress can be introduced in the channel region of a MOS transistor to increase carrier mobility, thereby enhancing the performance of the MOS transistor. Generally, it is desirable to induce tensile stress in the channel region of an NMOS device in a source-to-drain direction, and to induce compressive stress in the channel region of a PMOS device in a source-to-drain direction. Typically, to induce compressive stress in the channel region of a PMOS transistor, epitaxially grown SiGe (also referred to as SiGe stressor) is formed in the source and drain regions of the PMOS devices. Since SiGe has a greater lattice constant than silicon, it expands after annealing and induces compressive stress to the channel region in a source-to-drain direction. 
   However, the conventional SiGe technology suffers from the influence of micro-loading effect, which occurs due to a difference in pattern densities on a single die. The micro-loading effect leads to variation of epitaxial growth rates between a region of a higher density and a region of a lower density. Due to the difference in growth rates, the thickness of the resulting SiGe film becomes non-uniform. In addition, the composition of the epitaxial SiGe stressor in an isolated active region usually differs from that in a densely packed active region. Such non-uniformities may alter the stress level of the epitaxial SiGe stressor and adversely affect device performance. 
   Accordingly, there is a strong need in this industry to provide an improved SiGe device and method for alleviating the micro-loading effect, while at the same time overcoming the deficiencies of the prior art. 
   SUMMARY OF THE INVENTION 
   It is one object of the present invention to provide an improved SiGe device with specially designed SiGe-embedded dummy pattern that encompasses the SiGe device, which is capable of alleviating the micro-loading effect during the epitaxial growth of SiGe. 
   According to the claimed invention, a semiconductor device with dummy patterns for alleviating micro-loading effect comprises a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of first dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the first dummy patterns contains SiGe. 
   From one aspect of this invention, a semiconductor device comprises a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; a plurality of SiGe-embedded, cell-like dummy patterns provided on the semiconductor substrate within the middle annular region, wherein each of the SiGe-embedded, cell-like dummy patterns has substantially the same structure as that of the SiGe device; and a plurality of SiGe-free, cell-like dummy patterns in the outer region. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
       FIG. 1  is a schematic top view showing the layout of the SiGe device and SiGe dummy pattern in accordance with the first preferred embodiment of this invention; 
       FIG. 2  is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the second preferred embodiment of this invention; 
       FIG. 3  is a schematic, cross-sectional view taken along line I-I of  FIG. 2 ; 
       FIG. 4  is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the third preferred embodiment of this invention; 
       FIG. 5  is a cross-sectional view taken along line II-II of  FIG. 4 ; and 
       FIG. 6  is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the fourth preferred embodiment of this invention. 
   

   DETAILED DESCRIPTION 
   This invention pertains to an improved SiGe device with SiGe-embedded dummy patterns encompassing the SiGe device, which is capable of alleviating or counteracting the micro-loading effect during the epitaxial growth of SiGe. Such SiGe device may be a circuit component of mixed-signal circuits, RF circuits or analog circuits, and is usually designed as an isolated component in order to avoid coupling effect. 
     FIG. 1  is a schematic top view showing the layout of the SiGe device and SiGe dummy pattern in accordance with the first preferred embodiment of this invention. As shown in  FIG. 1 , a SiGe device  100  is formed in an isolated region  10  of a substrate  1 . The substrate  1  may be a silicon substrate, silicon-on-insulator (SOI) substrate or other suitable semiconductor substrates. The SiGe device  100  may include but not limited to P-channel metal-oxide-semiconductor (PMOS) transistors or bipolar junction transistors. By way of example, the SiGe device  100  is a PMOS transistor and comprises a gate stack  101 , a P +  source diffusion region  102  and a P +  drain diffusion region  103 . 
   An N well  12  is formed in the isolated region  10  of a substrate  1 , wherein the SiGe device  100  is fabricated within the N well  12 . Both of the P +  source diffusion region  102  and the P +  drain diffusion region  103  contain an epitaxially grown SiGe stressor layer. Shallow trench isolation (STI)  14  is formed in the substrate  1  to electrically isolate the SiGe device  100 . 
   Typically, the steps before growing the SiGe stressor layer in the source and drain regions include forming a gate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, and forming recesses in the silicon substrate along gate spacers. Then the SiGe stressor layer may be epitaxially grown in the recesses and annealed. The SiGe stressor layer may be formed by any suitable methods known in the art, for example, selective epitaxial growth (SEG) methods. 
   To effectively counteract the micro-loading effect of SiGe growth, a plurality of SiGe dummy patterns  20  are added to a middle annular region  300 . The middle annular region  300  is between an inner region  200  and an outer region  400 , wherein the SiGe device  100  is disposed within the inner region  200 . The SiGe dummy patterns  20  surround the SiGe device  100 . The SiGe dummy patterns  20  are active areas, which are defined concurrently with the active area or oxide define (OD) region of the SiGe device  100 . SiGe is grown in these active areas concurrently with the SiGe stressor layer grown in the P +  source diffusion region  102  and the P +  drain diffusion region  103  of the SiGe device  100 . 
   Please refer to  FIG. 2  and  FIG. 3 .  FIG. 2  is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the second preferred embodiment of this invention, and  FIG. 3  is a schematic, cross-sectional diagram taken along line I-I of  FIG. 2 , wherein like numeral numbers designate like regions, elements or layers. 
   As shown in  FIG. 2  and  FIG. 3 , likewise, a SiGe device  100  is formed in an N well  12  of a substrate  1 . The substrate  1  may be a silicon substrate, silicon-on-insulator (SOI) substrate or other suitable semiconductor substrates. According to the second preferred embodiment, the SiGe device  100  may include but not limited to a PMOS transistor and comprises a gate stack  101 , a P +  source diffusion region  102  and a P +  drain diffusion region  103 . A SiGe stressor layer  102   a  is formed on the P +  source diffusion region  102  and a SiGe stressor layer  103   a  is formed on the P +  drain diffusion region  103 . STI  14  is formed in the substrate  1  to electrically isolate the SiGe device  100 . 
   In this embodiment, a plurality of SiGe-embedded dummy diffusion regions  32  and a plurality of dummy poly-Si patterns  34  are provided around the SiGe device  100 . As best seen in  FIG. 2 , the SiGe-embedded dummy diffusion regions  32  and the dummy poly-Si patterns  34 , which together encompass the SiGe device  100 , are arranged in an alternate manner. However, any other arrangements make SiGe-embedded dummy diffusion regions  32  appear around the SiGe device  100  may also be used. 
   Referring to  FIG. 3 , to effectively counteract the micro-loading effect of SiGe growth, a dummy SiGe layer  32   a  is grown in each of the SiGe-embedded dummy diffusion regions  32 . The dummy SiGe layer  32   a  is grown concurrently with the SiGe stressor layers  102   a  and  103   a . As best seen in  FIG. 3 , the dummy poly-Si patterns  34  are situated directly above the STI  14  and do not overlap with the SiGe-embedded dummy diffusion regions  32 . 
   As shown in  FIG. 2  and  FIG. 3 , the plurality of SiGe-embedded dummy diffusion regions  32  and the plurality of dummy poly-Si patterns  34  are disposed within a middle annular region  300 . The middle annular region  300  is between an inner region  200  and an outer region  400 , wherein the SiGe device  100  is disposed within the inner region  200 . A plurality of dummy poly-Si patterns  34  and a plurality of SiGe-free dummy diffusion regions  36  are provided in the outer region  400 . The term “SiGe-free” refers to not containing SiGe herein. No SiGe is grown in the SiGe-free dummy diffusion regions  36 . Likewise, the dummy poly-Si patterns  34  and the SiGe-free dummy diffusion regions  36  are arranged, but not limited to, in an alternate manner. Each dummy poly-Si pattern  34  is formed on the STI  14 . Analogously, the dummy poly-Si pattern  34  does not overlap with the SiGe-free dummy diffusion region  36  in the outer region  400 . 
   Please refer to  FIG. 4  and  FIG. 5 .  FIG. 4  is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the third preferred embodiment of this invention, and  FIG. 5  is a schematic, cross-sectional diagram taken along line II-II of  FIG. 4 . As shown in  FIG. 4 , a SiGe device  100  is formed in an N well  12  of a substrate  1 . The substrate  1  may be a silicon substrate, SOI substrate or other suitable semiconductor substrates. According to the third preferred embodiment, the SiGe device  100  may include but not limited to a PMOS transistor and comprises a gate stack  101 , a P +  source diffusion region  102 , a P +  drain diffusion region  103 , and a P channel between the P +  source diffusion region  102  and the P +  drain diffusion region  103 . SiGe stressor layers  102   a  and  103   a  are formed on the P +  source diffusion region  102  and the P +  drain diffusion region  103 , respectively. STI  14  is formed in the substrate  1  to electrically isolate the SiGe device  100 . 
   According to the third preferred embodiment, a plurality of SiGe-embedded, cell-like dummy patterns  332  are disposed within the middle annular region  300 , which is between the inner region  200  and the outer region  400 . The SiGe device  100  is disposed within the inner region  200 . A plurality of SiGe-free, cell-like dummy patterns  432  are disposed within the outer region  400 . 
   In this embodiment, the SiGe-embedded, cell-like dummy patterns  332  are fabricated concurrently with the SiGe device  100 . Therefore, each of the SiGe-embedded, cell-like dummy patterns  332  may have the same structure as that of the SiGe device  100  except that no contact is formed on the SiGe-embedded, cell-like dummy patterns  332 . That is, each of the SiGe-embedded, cell-like dummy patterns  332  has a dummy gate  301 , a dummy P +  diffusion region  302  and a dummy P +  diffusion region  303 . SiGe layers  302   a  and  303   a  are formed on the dummy P +  diffusion region  302  and the dummy P +  diffusion region  303 , respectively. 
   Each of the SiGe-free, cell-like dummy patterns  432  disposed within the outer region  400  may have the same structure as that of the SiGe device  100  except the contact and the SiGe layer. As best seen in  FIG. 5 , each of the SiGe-free, cell-like dummy patterns  432  has a dummy gate  401 , a dummy P +  diffusion region  402  and a dummy P +  diffusion region  403 . No SiGe layers are formed on the dummy P +  diffusion region  402  and the dummy P +  diffusion region  403 . 
     FIG. 6  is a schematic top view showing the layout of the SiGe device and SiGe-embedded dummy pattern in accordance with the fourth preferred embodiment of this invention. As shown in  FIG. 6 , a SiGe device  100   a  is formed in an inner region  200 . A plurality of SiGe-embedded, cell-like dummy patterns  332   a  are formed in the middle annular region  300  that surrounds the inner region  200 . A plurality of SiGe-free, cell-like dummy patterns  432   a  are formed in the outer region  400 . 
   The SiGe-embedded, cell-like dummy patterns  332   a  may be fabricated concurrently with the SiGe device  100   a . Therefore, each of the SiGe-embedded, cell-like dummy patterns  332   a  may have the same structure as that of the SiGe device  100   a  except that no contact is formed on the SiGe-embedded, cell-like dummy patterns  332   a . Each of the SiGe-free, cell-like dummy patterns  432   a  disposed within the outer region  400  may have the same structure as that of the SiGe device  100   a  except the contact and the SiGe layer. 
   One germane feature of the fourth preferred embodiment as set forth in  FIG. 6  is that a plurality of poly-Si dummy patterns  502  are added in the middle annular region  300 . In this embodiment, these poly-Si dummy patterns  502  are disposed on the STI  14  and situated between the SiGe-embedded, cell-like dummy patterns  332   a . By adding these poly-Si dummy patterns  502 , the poly-Si critical dimension (CD) can be improved. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.