Abstract:
The present invention provides for a phased locked loop. A capacitor has an associated leakage current. A differential circuit is coupled to the capacitor of a low pass filter. A voltage follower circuit is coupled to the output of the differential circuit. The gate of a field effect transistor (FET) is coupled to an output of the voltage follower circuit. A current mirror is coupled to the FET, the current mirror having a first source and a second source, wherein the second current mirror source is coupled to the drain of the FET, wherein an output of the first current mirror source is coupled to the capacitor. Through the employment of current mirror source, leakage charge within the capacitor is replaced.

Description:
TECHNICAL FIELD 
   The invention relates generally to compensating for capacitive leakage and, more particularly, to compensating for capacitive leakage in a phase locked loop circuit 
   BACKGROUND 
   Phase Locked Loops (PLLs) can be an integral component of systems that use clocking for various operations. These systems can include microprocessors, wireless/wireline transceivers, and other devices known to those of skill in the art. Generally, PLLs are used to generate an output waveform which has a timing relationship with an input waveform, such as a 1:1 ratio, a 2:1 ratio, and so on. For instance, an input waveform of 60 Hertz could be inputted into a PLL to generate an output waveform of 120 Hertz. Furthermore, there would be a predefined phase relationship between the input wave and the output wave. 
   One important element of a PLL is a low pass filter, which typically comprises passive elements, such as capacitors and resistors. In a PLL, the voltage on the LPF is used as an input signal to a voltage controlled oscillator (VCO). Therefore, the voltage on the capacitor should remain stable, so that a stable oscillation occurs within the PLL, thereby leading to a stable output frequency. 
   Often, metal oxide semiconductors (MOSs) can be used as capacitors within a PLL. For instance, the gate and the source, or the gate and the drain, of a MOS can be used within an integrated circuit as the cathode and anode of a capacitor. However, with the rapid advancement of CMOS technology and the resulting reduction in the gate oxide thickness, a regime is being entered wherein the effect of leakage current through the gate dielectric is a problem. 
   There are two major regimes pertaining to gate leakage in metal-oxide-semiconductor (MOS) devices. These regimes are the “Fowler-Nordheim” regime and the “direct tunneling” regime. In the Fowler-Nordheim tunneling regime, which is dominant for thick (greater the 50 angstrom) oxides, the tunneling is a two-step process. In the first phase, in the presence of a large electric field, carriers at the oxide-semiconductor interface are accelerated. This increases the energy of the carriers (the carriers become ‘hot’) such that the barrier they encounter is reduced from trapezoidal to triangular. The tunneling current for the Fowler-Nordheim regime is proportional to the below:
 
IαE ox   2  exp(−B[1−(1−qV ox /C) 1.5 /E ox )
 
   wherein “E ox ,” is the electric field strength across the gate oxide/dielectric, which is dependent on the potential (V ox ) across the MOS capacitor, and B is a constant. 
   In the direct tunneling regime, the oxide is thin enough for carriers to directly tunnel across the trapezoidal barrier. The current in the direct tunnel regime is proportional to the following equation:
 
IαE ox   2  exp(−B[1−(1−qV ox /C) 1.5 /E ox )
 
   wherein E ox  is the electric field across the gate oxide/dielectric, q is the electric charge in coulombs, V ox  is the voltage across the capacitor dielectric, and B and C are constants. In both of the above equations, the leakage current is exponentially dependent on the voltage across the capacitor. 
   Generally, the leakage current through the capacitor is exponentially dependent upon the voltage across, as well as the thickness of, the gate dielectric. That is, as the thickness of the gate dielectric gets smaller, the leakage current increases exponentially. Also, increasing the voltage across the capacitor will result in an exponential increase in leakage current. 
   One trend in device technology is for thinner gate dielectrics to help achieve higher performance. However, the penalty for this is the associated exponential increase in leakage current. In a PLL, the effect of capacitance leakage on PLL performance can be most noticeable when the PLL is in the “locked” state (that is, there is a determined relationship between the input phase and the output phase of the waveforms) and the capacitor is not being charged by either charge pump, what is otherwise referred to as a “high Z” state. Suppose, just before the PLL locks, the voltage at node X  125  in  FIG. 1  is set to a voltage value V. Once the PLL is locked, the charge pumps are both disconnected, but for stable operation, the voltage at node X should also remain stable. However, due to gate leakage of the large MOS device which is used as a capacitor, the voltage at node X decays to ground with a time constant that is determined by the effective resistance associated with the tunneling current as well as the value of the capacitance. In some cases, the low pass filter cap is not too leaky. In other words, the time duration over which the discharging takes place is large enough that the resulting jitter will have most of its spectral components within the PLL loop bandwidth. As a result, this jitter is not filtered out. 
   One conventional solution to minimize this effect is to add a resistor in parallel with the low pass filter capacitor between node X of  FIG. 1  and electrical ground. If this added resistor has a value smaller than the effective resistance associated with the tunneling current in the filter capacitor, the resulting jitter at node X will have its spectrum pushed out to higher frequencies. However, the addition of this resistor reduces the effective dominant pole frequency of the PLL, thereby reducing PLL bandwidth. So, one faces the tradeoff of lowered PLL bandwidth with reduced leakage induced jitter. 
   In the time domain, this resistor can be considered as making the LPF capacitor leakier, thereby pushing the center of the spectral distribution of the jitter at Node X to a higher frequency, which can subsequently be filtered out. However, while long-term jitter is filtered out, the output of the VCO can suffer from substantial cycle-to-cycle jitter. 
   Therefore, there is a need for an apparatus and a method for compensating for leakage current from a capacitor that addresses at least some of the concerns associated with conventional apparatuses and methods for compensating for current leakage from a capacitor. 
   SUMMARY OF THE INVENTION 
   The present invention provides for a phased locked loop. A capacitor has an associated leakage current. A differential circuit is coupled to the capacitor. A voltage follower circuit is coupled to the output of the differential circuit. The gate of a field effect transistor (FET) is coupled to an output of the voltage follower circuit. A current mirror is coupled to the FET, the current mirror having a first source and a second source, wherein the second current mirror source is coupled to the drain of the FET, wherein an output of the first current mirror source is coupled to the capacitor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following Detailed Description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  schematically depicts a conventional phase locked loop; 
       FIG. 2  illustrates a charge compensation circuit that uses a differential circuit with a resistor; and 
       FIG. 3  illustrates a charge compensation circuit that uses a differential circuit with a transistor. 
   

   DETAILED DESCRIPTION 
   In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electro-magnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art. 
   In the remainder of this description, a processing unit (PU) may be a sole processor of computations in a device. In such a situation, the PU is typically referred to as an MPU (main processing unit). The processing unit may also be one of many processing units that share the computational load according to some methodology or algorithm developed for a given computational device. For the remainder of this description, all references to processors shall use the term MPU whether the MPU is the sole computational element in the device or whether the MPU is sharing the computational element with other MPUs, unless otherwise indicated. 
   It is further noted that, unless indicated otherwise, all functions described herein may be performed in either hardware or software, or some combination thereof. In a preferred embodiment, however, the functions are performed by a processor, such as a computer or an electronic data processor, in accordance with code, such as computer program code, software, and/or integrated circuits that are coded to perform such functions, unless indicated otherwise. 
   Turning now to  FIG. 1 , disclosed is a prior art PLL circuit  100 . A phase-frequency detector (PFD)  110  is coupled to a charge pump  120 . The charge pump  120  has a current source  122  and current sink  124 . The PFD  110  compares the difference between phases of a reference clock frequency and the feedback clock frequency to thereby generate signals to charge the capacitor  134  of the low pass filter  130  through use of the current source  122  or the current sink  124 . The voltage on the anode of capacitor  134  is then applied to the voltage controlled oscillator (VCO)  140 . The VCO generates an oscillatory output signal at a given frequency as a function of the capacitor  134  voltage. The output of the VCO  140  is then divided in a frequency divider/n  150 , and fed back into the PFD  110 . 
   However, should the charge pumps  120  be turned into the “off” condition by the PFD  110 , there is no replacement of charge at the capacitor  134 , as it continues to drain through a resistor  132 . Therefore, there would be “drift” of voltage by the capacitor  134  as charge leaks out of the capacitor  134 , which then changes the signal output frequency of the VCO. This changed output is then fed back into the PFD  110 , after the frequency divider  150  has processed the changed signal. The PFD  110  would then alter its output to compensate for this change. This drift of output signal of the VCO  140  could lead to an undesirable oscillation of the output frequency signal. 
   Turning now to  FIG. 2 , illustrated is a system  200  which employs capacitive current leakage correction, such as is used in a PLL. In the system  200 , a phase-frequency detector (PFD) (not shown) is coupled to a charge pump  220 . The charge pump  220  has a current source  222  and current sink  224 . The PFD compares the difference between phases of a reference clock frequency and the feedback clock frequency to thereby generate signals to charge the capacitor  242  of the low pass filter  240  through use of the current source  222  or the current sink  224 . The voltage on the cathode of the low pass filter  240  is then applied to the voltage controlled oscillator (VCO). The VCO generates an oscillatory output signal at a given frequency as a function of the low pass filter  240  voltage. 
   The low pass filter  240  comprises a capacitor C  242  and its corresponding leakage current I L    244  coupled to the node x  229 . There is a differential circuit (DC)  270  coupled to the output of the C  242 . The DC  270  comprises a differential amplifier (DA)  275 , and a resistor R 1   277  that is coupled across an input and the output of the DA  275 . The non-inverting input of the DA  275  is coupled to V ref . The output of the differential circuit  270  is coupled to a DA  283 . The output of the DA  283  is coupled to the gate of a FET  285 . The drain of the FET  285  is coupled to the current source  262  of a current mirror  260 , and the source of the FET  285  is coupled to a resistor R 2   287 . The resistor R 2   287  is coupled to V ref , which can be, for instance, ground. 
   The current mirror  260  comprises a first and second current source  261 ,  262 . The ratio of the current between current sources  261  and  262  is typically substantially one-to-one, although the ratio between the current sources  261 ,  262 , can vary in proportion to the proportion of resistance between R 1  and R 2 . In other words, if R 2  has ten times greater resistance than R 1 , then current source  261  conducts ten times the current than is conducted from R 2 . The current source  260  is coupled to node X  229 . The circuit  200  is described for purposes of small signal analysis. Therefore, various biasing currents are not shown for the system  200 , but are understood to be present by those of ordinary skill in the art. 
   In the system  200 , the current sources  222 ,  224  are turned off and on by the PFD as a function of a comparison between the reference clock and a feedback clock signal. The low pass filter  240  comprises a capacitor C  242  with a leakage current I L . 
   The anode of C  242  is kept at V ref , such as ground, by the DA  275 . A current flows from the output of  275  counter-clockwise through the R 1   277  to the V ref . This is true because this analysis is done when analyzing small signals and the biasing current is not shown in  FIG. 2 . Therefore, the voltage V x  equals V ref  plus the resistance R 1  times I L . The voltage of V x  is then conveyed by the second DA  283  to the top of R 2   287 . The voltage across R 2  is equal to {(V ref +I L R 1 )−V ref }, which equals I L R 1 . Therefore, the current through R 2  is I L R 1 /R 2 . If R 1  is equal to R 2 , then the current through R 2  is equal to I L . The current I L  is also driven by the voltage drop across the source of the FET  285 . The current I L  is then drawn from the current source  262  of the current mirror  260 . The current mirror  260  has a current source  261 , which then is also I L . This I L  is then flows into the capacitor C  242  to replace the leakage charge. 
   In a further embodiment, R 1   277  and R 2   287  are not substantially identical resistances. However, the current source  261  and  262  are in proportion to one another as well. For instance, if the resistance of R 2   287  is ten times larger than the resistance R 1   285 , the current source  261  will source ten times more current than the current source  262 . This ensures that the I L  is properly generated as replacement charge. 
   Turning now to  FIG. 3 , illustrated is a system  300  which employs capacitive current leakage correction, such as is used in a PLL. In the system  300 , a PFD (not shown) is coupled to a charge pump  320 . The charge pump  320  has a current source  322  and current sink  324 . The PFD compares the difference between phases of a reference clock frequency and the feedback clock frequency to thereby generate signals to charge the capacitor  342  of the low pass filter  340  through use of the current source  322  or the current sink  324 . The voltage on the anode of the low pass filter  340  is then applied to the VCO. The VCO generates an oscillatory output signal at a given frequency as a function of the low pass filter  340  voltage. 
   The low pass filter  340  comprises a capacitor  342  and its corresponding leakage current I L    344  coupled to the node x  329 . There is a differential circuit  370  coupled to the output of the C  342 . The differential circuit  370  comprises a DA  375  and FET  377 . The FET  377  is coupled across an input and the output of the DA  375 , and the gate of FET  377  is coupled to Voltage source V bias . The output of the differential circuit  370  is coupled to a DA  383 . The output of the DA  383  is coupled to the gate of a FET  385 . The current through FET  385  is I bias  minus I L . The source of the FET  385  is coupled to the drain of a FET  387 . The source of the FET  387  is coupled to the voltage level V ref , which can be ground. The anode of C  342  is also coupled to a current drain I bias    376 . The drain of the FET  385  is also coupled to a current source  361  of a current mirror  360 . 
   The current mirror  360  comprises a first and second current source  361 ,  362 . The ratio of the current between current sources  361  and  362  can be substantially one, although the ratio between the current sources  361 ,  362 , can vary in proportion to the proportion of current sources, as will be described below. The current source  360  is coupled to node X  329 . In the system  300 , the current sources  322 ,  324  are turned off and on by the PFD as a function of a comparison between the reference clock and a feedback clock signal. The current from each branch of the current mirror  360  is I bias . Therefore, the current going to LPF  340  is I L , which conveys leakage current to compensate for the leakage charge from C  342 . 
   Coupled to the current source  362 , there is an I bias  generating circuit  390 . In the I bias  generating circuit  390 , there is a differential circuit  399  coupled to an I bias  current generator  392 . The differential circuit  399  comprises a DA  393  and FET  391 . The FET  391  is coupled across an input and the output of the DA  394 , and the gate of FET  391  is coupled to Voltage source Vbias. The output of the differential circuit  399  is coupled to a DA  394 . The output of the DA  394  is coupled to the gate of a FET  395 . The source of the FET  395  is coupled to the drain of a FET  396 . The source of the FET  396  is coupled to V ref , which can be ground. The drain of the FET  395  is also coupled to a current mirror  360 . A number of aspects of the I bias  generating circuit  390  are similar to either the differential circuit  370 , the differential follower  383 , FETs  385 , FET M 2   387 , and so on. In other words, a number of aspects are replicated. This can greatly improve I bias  matching between the I bias  generating circuit  390  and the differential circuit  370 , DA  383 , and so on. 
   The circuit  300  can act substantially as follows. The LPF has a leakage current I L    344 . The gate of the FET M 1   377  is coupled to a V bias  voltage, which is above V ref . The current through FET M 1   377  is a current I bias , minus the leakage current I L . Even with the leakage current I L  subtracted from I bias , I bias  minus I L  is still large enough to ensure that the components, such as M 1  FET  377 , stay biased in their substantially linear response regions. Both the I L  and the “I bias  minus I L ” currents are drained off by the I bias  current sink  376 . 
   Therefore, the voltage at V D  is the voltage gain across M 1   377  plus the V ref  voltage. The DA  383  applies the same voltage to the drain of FET M 2   387  and the source of the FET  385 . Also, the V bias  voltage applied at FET  387  is substantially the same as is found in FET M 1   377 . Due to the voltage across M 2   387 , and if M 2  and M 1  have the same area or otherwise have the same response curve, the current through FET  385  is also I bias −I L . Therefore, the I bias  current comes from the current mirror  360 . 
   Similarly, in the bias current generator circuit  390 , I bias  is generated externally by using an FET, such as M 4   396 , biased by an external voltage source. The I bias  generating circuit  390 , and hence the current mirror  360 , is used so that I bias  does not end up over-charging the LPF  340 . The drain of a FET M 3   391  is coupled to a V bias  voltage, which is above V ref . The current through M 3  is a current I bias . The I bias  current is drained off by the I bias  current sink  392 . 
   Therefore, the voltage at V D     —     Replica  is the voltage gain across M 3   391  plus the V ref  voltage. The general relation between the sizes of FET  391  and  396 , and the current mirrors  361  and  362  is substantially as follows. If FET  391  is “K” times larger than that of FET  396 , indicating FET  391  conducts “K” times more current than FET  396 , then current mirror  361  is “K” times larger than current mirror  362 . In other words, current mirror  361  conducts K times more current than current mirror  362 . K is any number greater than zero. The DA  394  has the same voltage applied to the drain of FET M 4   396 , which is also V D     —     Replica . Also, the gate voltage at M 3   391  is set to V bias . Due to the voltage across M 4   396 , and if M 3  and M 4  have the same response curve (that is, “K” equals “one”), then the current through FET M 4   396  is also I bias . Therefore, the I bias  current comes from the current mirror  360 . 
   In the circuit  300 , the transistors  385 ,  387 ,  395 , and  396  need not be in a linear region to operate well. The resistances of M 1   377  and the M 2   387 , however, are to be substantially identical. If the source, gate and drain voltages of M 1   377  and M 2   387  are substantially the same then, regardless of which region they are operating in, the effective resistance they introduce is substantially identical. This can be a beneficial property, because the circuit  300  can function very well under a variety of operating conditions. However, one requirement is that I bias  is selected so that, under all operating conditions, V D  is higher voltage than V ref . 
   The circuits  200 ,  300  have at least two benefits. Extra circuitry is not being used within the PFD or elsewhere within the charge pump  220  to compensate for leakage currents, which is advantageous in that it does not introduce extra noise into the node X, the driver node for the VCO. Secondly, these circuits enable leakage compensation even in processes where the leakage current characteristics are not well modeled. 
   It is understood that the present invention can take many forms and embodiments. Accordingly, several variations may be made in the foregoing without departing from the spirit or the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying mechanisms on which these programming models can be built. 
   Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.