Abstract:
A clock reproduction circuit receives a multi-valued input data signal to generate a reproduced clock signal with a higher accuracy. The clock reproduction circuit includes a data judgement block which judges whether or not three consecutive data are such that a first-order data is equal to a third-order data and is not equal to a second-order data, and a phase-locked-loop (PLL) which controls or does not control the phase of the reproduced clock depending on the judgement result by the data judgement block.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a clock reproduction circuit and, more particularly, to a clock reproduction circuit that reproduces a clock signal from an input serial data signal including multi-valued data. 
   2. Description of the Related Art 
   There is known a signal transmission system that uses multi-valued data in place of binary data, in a serial data signal to be transmitted. Patent Publication JP-05-236043A describes a clock reproduction circuit used in a multi-valued data receiving circuit. In general, a clock reproduction circuit installed in a receiving circuit detects the falling edge and the rising edge of a transmitted serial data signal and sets the clock pulse of the reproduced clock signal between the rising edge and the falling edge or between the falling edge and the rising edge. 
   The clock reproduction circuit described in JP-05-236043A detects a timing at which multi-valued data crosses a plurality of reference voltage levels and compares the phase between the detected timing and the output clock signal of the clock reproduction circuit, to thereby output a phase error signal in proportion to the result of the phase comparison. Based on the magnitude of the phase error signal, the phase and frequency of the reproduced clock are controlled. The clock reproduction circuit adopts the method described above to allow the reproduced clock signal in the receiving circuit to be pulled in synchrony with the transmitted data signal at a high speed. 
   In the case where multi-valued data is used in a high-speed signal transmission system, a transmission data signal assumes a plurality of levels of signal amplitude corresponding to the data values. Accordingly, the timing at which an input signal crosses a plurality of reference voltages in the receiving circuit varies depending on the value of the data transmitted. Therefore, if a technique is used in which the rising and falling edges of the transmitted signal are detected and the clock pulse of the reproduced clock signal is set between the rising (falling) edge and the falling (rising) edge, the center of the clock pulse of the reproduced clock signal is deviated from the center of the signal waveform depending on the level of the data value, with the result that jitter is generated in the reproduced clock signal. If the center of the clock pulse of the reproduced clock signal is deviated from the center of the reproduced data, the time margin for identifying the reproduced data is reduced. In particular, the problem of the insufficient time margin will be critical in a higher-speed signal transmission system. 
   SUMMARY OF THE INVENTION 
   In view of the above situation of the conventional technique, it is an object of the present invention to provide a clock reproduction circuit capable of setting a larger time margin in the receiving circuit that receives multi-valued data in a high-speed signal transmission system, by suppressing variation in the phase of the clock pulse and generating a stable reproduced clock signal. 
   It is also an object of the present invention to provide a method for generating a reproduced clock signal from a multi-valued serial data signal. 
   The present invention provides a clock reproduction circuit for receiving a multi-valued input data signal to generate a reproduced clock signal, including: a data judgement block which judges whether or not three consecutive data of the input data signal are such that a first-order data is equal to a third-order data and is not equal to a second-order data, to output a first judgement result or a second judgement result depending on the judgement; and a phase-locked-loop (PLL) circuit which controls a phase of the reproduced clock signal if the data judgement block outputs the first judgement result, and does not control the phase of the reproduced clock signal if the data judgement block outputs the second judgement result. 
   The present invention also provides a method for generating a reproduced clock signal based on a multi-valued input data signal, including the steps of: judging whether or not three consecutive data of the input data signal are such that a first-order data is equal to a third-order data and is not equal to a second-order data, to output a first judgement result or a second judgement result depending on the judgement; and controlling a phase of the reproduced clock signal if the data judgement block outputs the first judgement result, without controlling the phase of the reproduced clock signal if the data judgement block outputs the second judgement result. 
   In accordance with the clock reproduction circuit and method of the present invention, the change timing of the signal including the three consecutive data which change in a symmetrical manner in the signal waveform is used for the phase control performed in the PLL circuit; whereas the change timing of the signal including the three consecutive data which do not change in an asymmetrical manner, that is, the center between the data change timings of the signal waveform does not correspond to the center of the signal data, is not used for the phase control in the PLL circuit. Therefore, it is possible to satisfactorily suppress a variation in the clock pulse to thereby obtain a reproduced clock signal having reduced jitter. 
   In the clock reproduction circuit according to a preferred embodiment of the present invention, the data judgement block includes: a plurality of comparators for comparing the input data signal against respective reference voltages each corresponding to one of data values in the input data signal, to output respective comparison results; a plurality of latch elements, each disposed corresponding to one of the comparators, for latching the respective comparison results; and a data reproduction block for reproducing the three consecutive data based on the comparison results latched by the latch elements. In this case, the clock reproduction circuit can be realized with a relatively simple structure. A flip-flop may be used as the latch element. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing a clock reproduction circuit according to an embodiment of the present invention; 
       FIG. 2  is a graph showing the general relationship between signal levels of multi-valued data and reference voltages used for detection of the multi-valued data; and 
       FIG. 3  is a graph showing the change timing patterns of an input signal including multi-valued serial data at the time when the input signal is detected in the comparator shown in  FIG. 1 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   An embodiment of the present invention will be described below with reference to the accompanying drawings.  FIG. 1  is a block diagram showing a clock reproduction circuit according to the embodiment of the present invention. The clock reproduction circuit includes a PLL circuit P 1 , a comparator block including a plurality of comparators S 1  to S 3  which compare an input signal against respective reference voltage levels VR 1  to VR 3 , a flip-flop block which latches the comparison results from the comparators S 1  to S 3  in response to the output clock signal from the PLL circuit P 1 , and a phase adjustment circuit Ti which is attached to the PLL circuit P 1  to control the phase adjustment performed by the PLL circuit P 1 , based on the comparison results latched by the flip-clop block. The serial data signal to be input to the clock reproduction circuit of the present embodiment includes multi-valued data having potential levels VIL 1 , VIL 2 , VIL 3 , VIL 4  and assuming any of four data values corresponding to the potential levels. 
   The serial data signal including multi-valued data is input to each of the comparators S 1  to S 3 . The comparator S 1  compares the input serial data signal against the reference voltage VR 1  and outputs the comparison result to the flip-flop FF 1   a . The data of the flip-flop FF 1   a  is delivered to the next flip-flop FF 1   b . The comparator S 2  compares the input serial data signal against the reference voltage VR 2  and outputs the comparison result to the flip-flop FF 2   a . The data of the flip-flop FF 2   a  is delivered to the next flip-flop FF 2   b . The comparator S 3  compares the input serial data signal against the reference voltage VR 3  and outputs the comparison result to the flip-flop FF 3   a . The data of the flip-flop FF 3   a  is delivered to the next flip-flop FF 3   b . The output data of the flip-flops FF 1   a , FF 1   b , FF 2   a , FF 2   b , FF 3   a , FF 3   b  that configure the flip-flop block are delivered to the phase adjustment circuit T 1 . The phase adjustment circuit T 1  controls the PLL circuit P 1  based on the outputs from the flip-flops FF 1   a , FF 1   b , FF 2   a , FF 2   b , FF 3   a , FF 3   b.    
     FIG. 2  shows the signal waveform of the transmitted multi-valued data. The serial data signal including the multi-valued data has four levels VIL 1 , VIL 2 , VIL 3 , VIL 4 , as shown in  FIG. 2 . The receiving circuit generates, within the circuit, three reference voltages VR 1 , VR 2 , VR 3  and detects whether the received serial data signal assumes any of potential levels VIL 1  to VIL 4 . In addition, the receiving circuit detects the falling or rising edge of the serial data signal, sets the clock pulse of the reproduced clock signal between the rising edge and the falling edge or between the falling edge and the rising edge, and receives therein the transmitted serial data based on the timing of the reproduced clock signal. 
   In transmission of a multi-valued serial data signal, the respective data assume a plurality of potential levels and thus the data signal has a plurality of signal amplitudes. As a result, the timing at which the serial data signal crosses the reference voltages varies depending on the data value. With reference to  FIG. 3 , this situation will be described in detail. 
   In the rising edge of the input waveform, the timing at which the input signal crosses the reference voltage VR 1  is the time instant: 
   R 3 , if the signal level rises from VIL 1  to VIL 4 ; 
   R 2 , if the signal level rises from VIL 2  to VIL 4 ; and 
   R 1 , if the signal level rises from VIL 3  to VIL 4 . 
   Similarly, in the falling edge of the input waveform, the timing at which the input signal crosses the reference voltage VR 1  is the time instant: 
   F 1 , if the signal waveform falls from VIL 4  to VIL 1 ; 
   F 2 , if the signal waveform falls from VIL 4  to VIL 2 ; and 
   F 3 , if the signal waveform falls from VIL 4  to VIL 3 . 
   The clock pulse of the reproduced clock signal is set between the adjacent edges of the serial data signal. Accordingly, assuming that the timing of the rising edge in the waveform of the input serial data signal is the time instant R 1 , the location of the clock pulse in the reproduced clock signal varies depending on whether the next timing of the falling edge of the waveform assumes either the time instant F 1 , F 2 , or F 3 . In this case, if the timing of falling edge of the input waveform is F 3 , the center of the clock pulse of reproduced clock signal is located at the center of the signal waveform, and thus resides at the data center. However, if the timing of falling edge of the input waveform is F 1  or F 2 , the center of the clock pulse in the reproduced clock signal is deviated from the center of the waveform, and thus deviates from the data center. 
   In view of the characteristics of the above multi-valued data, the clock reproduction circuit according to the embodiment of the present invention is configured to operate as follows. In  FIG. 1 , the comparators S 1 , S 2 , S 3  compare the input serial data signal against the reference voltages VR 1 , VR 2 , VR 3 , respectively, and delivers the comparison results each representing “1” or “0” to the flip-flops FF 1   a , FF 2   a , FF 3   a , respectively. The data of the flip-flops FF 1   a , FF 2   a , FF 3   a  are then delivered to the flip-flops of the next stage FF 1   b , FF 2   b , FF 3   b  in response to the next clock pulse. 
   Thus, it is possible for the clock reproduction circuit to determine the behavior of the input signal waveform based on the current output data of the flip-flops FF 1   a , FF 2   a , FF 3   a , FF 1   b , FF 2   b , FF 3   b  and previous output data of the flip-flops FF 1   b , FF 2   b , FF 3   b . Assuming that the current output data are such that FF 1   b =‘1’, FF 2   b =‘1’, FF 3   b =‘1’, FF 1   a =‘0’, FF 2   a =‘0’ and FF 3   a =‘0’, and the previous output data stored in the phase adjustment circuit T 1  are such that FF 1   b =‘1’, FF 2   b =‘1’ and FF 3   b =‘1’, the pattern of the three consecutive data in the input signal thus detected can be represented by a waveform which first assumed VIL 1 , then VIL 4  and finally VIL 1 . As another example, assuming that the current output data are such that FF 1   b =‘1’, FF 2   b =‘1’, FF 3   b =‘1’, FF 1   a =‘0’, FF 2   a =‘1’ and FF 3   a =‘1’, and the previous output data stored in the phase adjustment circuit T 1  are such that FF 1   b =‘1’, FF 2   b =‘1’ and FF 3   b =‘1’, the pattern of the three consecutive data in the input signal thus detected can be represented by a waveform which first assumed VIL 1 , then VIL 4 , and finally VIL 3 . 
   If the waveform of the input signal assumes VIL 1 , VIL 4  and VIL 1  in the order of the occurrence, the input signal crosses the reference voltage VR 1  at the time instants R 3  and F 1  in  FIG. 3 . In this case, the data signal waveform is symmetric and therefore the center of the clock pulse in the reproduced clock signal can be set at the center of the data signal based on the timing of both the rising and falling edges of the central data (second-order data) having a VIL 4  level. 
   On the other hand, if the waveform of the input signal assumes VIL 1 , VIL 4  and VIL 3  in the order of the occurrence, the data signal waveform is asymmetric and the input signal crosses the reference voltage VR 1  at the time instants R 3  and F 3 . If the center of the clock pulse in the reproduced clock signal is determined based on the rising and falling edges of the central data having a VIL 4  level, the center of the clock pulse is deviated from the center of the signal waveform to the right side. 
   As described above, in transmission of the multi-valued data, the amount of change (signal amplitude) in the data signal varies depending on the data value, whereby the timing at which the input signal crosses the reference voltage set in the receiving circuit varies depending on the waveform. Therefore, if the clock pulse of the reproduced clock signal is set simply by detecting the rising or falling edge of the serial data signal in the receiving circuit, the center of the clock pulse may be deviated in some cases from the center of the data depending on the pattern of the data signal waveform. 
   In the present embodiment, the phase adjustment circuit T 1  determines how the input signal has changed based on the outputs from the FF 1   a , FF 2   a , FF 3   a , FF 1   b , FF 2   b , FF 3   b  and controls the clock phase while using only the following patterns: 
   VIL 1 →VIL 2 →VIL 1 ; 
   VIL 1 →VIL 3 →VIL 1 ; 
   VIL 1 →VIL 4 →VIL 1 ; 
   VIL 2 →VIL 3 →VIL 2 ; 
   VIL 2 →VIL 4 →VIL 2 ; 
   VIL 3 →VIL 4 →VIL 3 ; 
   VIL 2 →VIL 1 →VIL 2 ; 
   VIL 3 →VIL 1 →VIL 3 ; 
   VIL 4 →VIL 1 →VIL 4 ; 
   VIL 3 →VIL 2 →VIL 3 ; 
   VIL 4 →VIL 2 →VIL 4 ; and 
   VIL 4 →VIL 3 →VIL 4 . 
   More specifically, only when the signal waveform is changed in a symmetrical manner, the PLL circuit P 1  sets the phase of the reproduced clock based on the timing of the central data of the three consecutive data. In the case of the change patterns other than those described above, the PLL circuit P 1  does not set the phase of the reproduced clock using the timing of the central data of the three consecutive data, and waits for the subsequent change timing. 
   As described above, whether or not the phase control is performed for the current signal pattern is determined at each timing in the PLL, thereby allowing the phase of the reproduced clock to be set in the center of the data signal at any time. 
   Although the two-stage flip-flops are exemplified in the above embodiments, three-stage flip-flops may be used so as to store three consecutive data. Although whether or not the phase control is performed is determined in the PLL circuit in the above embodiment, the phase control may be triggered by a signal from outside. Further, although the multi-valued data has four data values in the above embodiment, the clock reproduction circuit can be applied to the receiving circuit using multi-valued data having any number of data values, so long as the number is equal to or grater then 3. 
   Although the present invention has been described with reference to the preferred embodiment, the clock reproduction circuit according to the present invention is not limited to the configuration shown in the above embodiment and various changes, modifications, or alternations to the embodiment described herein may be made, none of which depart from the spirit of the present invention. All such changes, modifications, and alternations should therefore be regarded as within the scope of the present invention.