Abstract:
A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is related to U.S. patent application Ser. No. ______, entitled “Digital Signal Processor Having Instruction Set with One or More Non-Linear Complex Functions;” U.S. patent application Ser. No. ______, entitled “Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table;” and U.S. patent application Ser. No. ______, entitled “Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table with Exponentially Varying Step-Size,” each filed contemporaneously herewith and incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention is related to digital signal processing techniques and, more particularly, to techniques for digital processing of non-linear complex functions. 
       BACKGROUND OF THE INVENTION 
       [0003]    Digital signal processors (DSPs) are special-purpose processors utilized for digital processing. Signals are often converted from analog form to digital form, manipulated digitally, and then converted back to analog form for further processing. Digital signal processing algorithms typically require a large number of mathematical operations to be performed quickly and efficiently on a set of data. 
         [0004]    DSPs thus often incorporate specialized hardware to perform software operations that are often required for math-intensive processing applications, such as addition, multiplication, multiply-accumulate (MAC), and shift-accumulate. A Multiply-Accumulate architecture, for example, recognizes that many common data processing operations involve multiplying two numbers together, adding the resulting value to another value and then accumulating the result. Such basic operations can be efficiently carried out utilizing specialized high-speed multipliers and accumulators. 
         [0005]    DSPs, however, generally do not provide specialized instructions to support complex mathematical functions, such as exp, log, cos, 1/x and x K . Increasingly, however, there is a need for complex arithmetic operations in processors. A nonlinear function is any problem where the variable(s) to be solved for cannot be written as a linear sum of independent components. A complex number can be written in the form a+bi, where a and b are real numbers, referred to as the real part and the imaginary part of the complex number, respectively. Many applications require complex arithmetic operations, such as complex addition or complex multiplications. 
         [0006]    If supported at all, a DSP supports a non-linear function by using a large table look-up (LUT). An exemplary LUT may store on the order of 2,000 16 bit values, and thus require 32 kilobits of random access memory (RAM). The LUT is typically implemented in a separate dedicated SRAM (so that data and the non-linear LUT can be accessed at the same time to achieve improved performance). 
         [0007]    In cases where the DSP is based on VLIW (Very Long Instruction Word) or SIMD (Single Instruction Multiple Data) architectures with N issues slots, the memory size becomes even larger. The LUT must be replicated N times because each issue slot must be able to read different values in the look-up table simultaneously, as the values of the data in each issue slot may be different. This replication of memory results in an even greater silicon area. For example, assuming a LUT in a 4-way vector co-processor, a memory size of 128 Kb is required (32 Kb×4). In addition, if different non-linear functions are required for different parts of a program being executed, the various LUTs must be loaded into memory, thereby significantly increasing latency and potentially reducing performance. 
         [0008]    A need therefore exists for a digital signal processor having an instruction set that supports one or more non-linear functions using a look-up table of reduced size. 
       SUMMARY OF THE INVENTION 
       [0009]    Generally, a digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. According to one aspect of the invention, a digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said at least two obtained values to obtain a value, y, using a factorized polynomial interpolation. 
         [0010]    A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a schematic block diagram of an exemplary digital signal processor that incorporates features of the present invention; 
           [0012]      FIG. 2  is a schematic block diagram of an exemplary vector-based digital signal processor that processes one or more numbers simultaneously in accordance with an embodiment of the present invention; 
           [0013]      FIG. 3  illustrates a plot of a non-linear function  300  that may be processed in accordance with the present invention; and 
           [0014]      FIG. 4  is a flow chart illustrating an exemplary interpolation process  400  for a non-linear function that employs factorized polynomial interpolation in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    The present invention provides a digital signal processor having an instruction set that supports one or more non-linear functions using one or more look-up tables of reduced size. Generally, one or more look-up tables store a subset of values for a non-linear function and an interpolator interpolates at least two values obtained from the look-up table(s) to obtain the result using factorized polynomial interpolation. As used herein, the term “digital signal processor” shall be a processor that executes instructions in program code. Further, a hard-wired logic implementation of digital signal processing functions is not considered herein. 
         [0016]    In this manner, the present invention supports non-linear functions by using a smaller look-up table than required by conventional techniques. As previously indicated, an exemplary look-up table may store on the order of 2,000 16 bit values, and thus require 32 kilobits of random access memory (RAM). With the present invention, a smaller look-up table can be employed to store a subset of the 2,000 values, such as 128 values. An interpolator will interpolate two or more values obtained from the smaller look-up table(s) to obtain the desired result. As discussed further below in conjunction with  FIG. 3 , the interpolation can be a linear interpolation or a higher order interpolation such as quadratic or cubic interpolation. 
         [0017]      FIG. 1  is a schematic block diagram of an exemplary digital signal processor  100  that incorporates features of the present invention. As shown in  FIG. 1 , the exemplary digital signal processor  100  includes one or more functional units  110  for non-linear functions. In addition, the digital signal processor  100  comprises one or more look-up tables  120  that store a subset of values for a non-linear function. Performance of the digital signal processor  100  may be further improved by employing a technique for mapping the input data to non-uniformly spaced sub-samples stored in the look-up table  120 , such as an exponentially varying step-size, as described in U.S. patent application Ser. No. ______, filed contemporaneously herewith and entitled “Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table with Exponentially Varying Step-Size,” incorporated by reference herein. 
         [0018]    An interpolator  130  interpolates two or more values obtained from a look-up table  120  to obtain the desired result. The interpolator  130  may also include a modulo arithmetic unit (not shown) to support periodic functions, such as sine and cosine (e.g., by wrapping the input angle of the trigonometric sine and cosine functions). 
         [0019]    Thus, in implementing the non-linear function, the non-linear functional unit(s)  110  obtain two or more values from the subset of values stored in the look-up table(s)  120  and then initiate the interpolator  130  to interpolate the two or more obtained sub-sample values to obtain the desired result. 
         [0020]    As previously indicated, according to one aspect of the invention, the an interpolator  130  interpolates two or more values obtained from the look-up table(s)  120  to obtain the desired result using polynomial interpolation, such as a Taylor series. In addition, as discussed further below in conjunction with  FIG. 4 , a Horner scheme (canonical factorized form of a polynomial) can optionally be employed to minimize the hardware complexity in terms of number of multiplications and additions that are needed to implement the interpolation operation. 
         [0021]    In various embodiments, the digital signal processor  100  may use hardware or a look-up table (or a combination thereof) to compute the non-linear values of the data. Generally, if the digital signal processor  100  is processing software code that includes a predefined instruction keyword corresponding to a non-linear math function and any appropriate operands for the function, the instruction decoder must trigger the appropriate non-linear functional units  110  that are required to process the instruction (e.g., connect two registers, apply one or more nonlinear mathematical operations on the values contained therein, and store the result in a third register). It is noted that a non-linear functional unit  110  can be shared by more than one instruction. 
         [0022]    Generally, the present invention extends conventional digital signal processors to provide an enhanced instruction set that supports one or more non-linear functions using one or more look-up tables and an interpolation function. As shown in  FIG. 1 , a digital signal processor  100  in accordance with the present invention receives at least one number as an input, applies one or more non-linear functions to the input and generates an output value. 
         [0023]    The disclosed digital signal processors may have a scalar architecture, as shown in  FIG. 1 , that processes a single number at a time, or a vector architecture, as discussed hereinafter in conjunction with  FIG. 2 , that processes one or more numbers simultaneously. In the case of a vector-based digital signal processor implementation, the input number is a vector comprised of a plurality of scalar numbers that are processed in parallel. 
         [0024]      FIG. 2  is a schematic block diagram of an exemplary vector-based digital signal processor  200  that processes one or more numbers simultaneously in accordance with an embodiment of the present invention. Generally, the vector-based implementation of  FIG. 2  increases the number of MIPs (instructions per second), relative to the scalar implementation of  FIG. 1 , by performing different processes concurrently. Thus, the vector-based digital signal processor  200  contains plural non-linear functional units  210 - 1  through  210 -N. For example, a dual digital signal processor  200  contains two non-linear functional units  210 - 1  and  210 - 1  that are capable of performing two independent non-linear function operations concurrently. 
         [0025]    As noted above, the input to the vector-based digital signal processor  200  is a vector. X, comprised of a plurality of scalar numbers, x n , that are processed in parallel. For example, assume a vector-based digital signal processor  200  supports a non-linear function for a vector, X, where X is comprised of scalar numbers x 1  through x 4 . The exemplary function may be expressed as follows: 
         [0000]      NL_vec4(x 1 ,x 2 ,x 3 ,x 4 ,type,mod), 
         [0000]    where type may be, for example, ‘sin’, ‘cos’, ‘log 10’, ‘exp’ or ‘sqrt’. Mod=‘2*π’ for a period of 2π, and ‘0’ for non-periodic functions. 
         [0026]    As previously indicated, an interpolator  130  interpolates two or more values obtained from the look-up table  120  to obtain the desired result. 
         [0027]    Interpolation 
         [0028]    In one embodiment, the interpolator  130  employs a linear interpolation, such as a linear spline, to interpolate two or more sub-sample values obtained from the look-up table  120  to obtain the desired result. 
         [0029]      FIG. 3  illustrates a plot of a non-linear function  300  that may be processed in accordance with the present invention. As shown in  FIG. 3 , the non-linear function  300  is sub-sampled and the sub-sampled values, such as x 1  and x 2 , can be stored in the look-up table  120 . If the non-linear function  300  must be evaluated for a value, x, that is not stored in the look-up table  120 , the digital signal processor  100  retrieves the two or more stored sub-sampled values, such as y 1  and y 2  that are stored for x 1  and x 2 , and interpolates to find the value, y, for x, as follows: 
         [0000]        y=m ( x−x   1 )+ y   1    
         [0000]    where m equals (y 2 −y 1 )/(x 2 −x 1 ). 
         [0030]    It is noted that performance may optionally be further improved by employing one or more polynomial interpolation algorithms, such as a Taylor series, as described in U.S. patent application Ser. No. ______, filed contemporaneously herewith and entitled “Digital Signal Processor with One or More Non-Linear Functions Using Factorized Polynomial Interpolation,” incorporated by reference herein. 
         [0031]    Polynomial Interpolation 
         [0032]    The present invention recognizes that performance may be further improved by employing a polynomial interpolation algorithm, such as a Taylor series, based on the following polynomial: 
         [0000]        Y=a   n ( x−x   1 ) n   +a   n-1 ( x−x   1 ) n-1   + . . . +a   0    
         [0033]    Factorized Polynomial Interpolation (Horner Scheme) 
         [0034]    An embodiment of the present invention recognizes that the complexity of the above polynomial is significant, due to the number of multiplication operations that are required. Thus, one embodiment of the present invention employs a Horner scheme to minimize the number of operations required to perform the polynomial interpolation. 
         [0035]    In the exemplary case of a third order polynomial, the above polynomial expression can be rewritten as follows: 
         [0000]        Y=a   0 +( x−x   1 )*( a   1 +( x−x   1 )*( a   2 +( x−x   1 )* a   3 )). 
         [0000]    In this manner, only 3 multiply-accumulate operations are needed to implement an exemplary third order polynomial. 
         [0036]      FIG. 4  is a flow chart illustrating an exemplary interpolation process  400  for a non-linear function that employs factorized polynomial interpolation in accordance with the present invention. The interpolation process  400  may be implemented, for example, by one or more functional units  210  from the exemplary vector-based digital signal processor  200  of  FIG. 2 . As shown in  FIG. 4 , the exemplary interpolation process  400  initially maps the input bits to a table row during step  410  and reads N values. Thereafter, factorized (Horner) polynomial interpolation is performed during step  420 . 
       CONCLUSION 
       [0037]    While exemplary embodiments of the present invention have been described with respect to digital logic blocks and memory tables within a digital signal processor, as would be apparent to one skilled in the art, various functions may be implemented in the digital domain as processing steps in a software program, in hardware by circuit elements or state machines, or in combination of both software and hardware. Such software may be employed in, for example, a digital signal processor, application specific integrated circuit or micro-controller. Such hardware and software may be embodied within circuits implemented within an integrated circuit. 
         [0038]    Thus, the functions of the present invention can be embodied in the form of methods and apparatuses for practicing those methods. One or more aspects of the present invention can be embodied in the form of program code, for example, whether stored in a storage medium, loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a processor, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a device that operates analogously to specific logic circuits. The invention can also be implemented in one or more of an integrated circuit, a digital signal processor, a microprocessor, and a micro-controller. 
         [0039]    It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.