Abstract:
A power switch circuit that ensures suppression of an increase in a transient current. The power switch circuit includes a first transistor, which generates an output voltage in response to a control signal, and a time difference generation circuit, which delays the control signal by performing a logical process with the output voltage of the first transistor and the control signal.

Description:
FIELD 
       [0001]    The present invention relates to a power switch circuit which controls the supply of power to an internal circuit of a semiconductor integrated circuit device. 
       BACKGROUND 
       [0002]    When internal circuits of a semiconductor integrated circuit device is supplied with power and the internal circuits are simultaneously supplied with power, transient current noise increases and generates power noise. Therefore, semiconductor integrated circuits are provided with a plurality of power switch circuits arranged between power supplies and internal circuits. The power switch circuits sequentially become conductive to suppress the peak value of the transient current. The operation of such power switch circuits must be stabilized. 
         [0003]      FIG. 5  shows an example of a prior art semiconductor integrated circuit device including power switch circuits SW 1  to SWn. The power switch circuits SW 1  to SWn are arranged between a high potential power supply V DD  and a plurality of logic circuits  1 . Each logic circuit  1  is supplied with power V SS . When each of the power switch circuits SW 1  to SWn becomes conductive, each logic circuit  1  is supplied with the power V DD . 
         [0004]    The power switch circuits SW 1  to SWn sequentially become conductive in response to a control signal E provided from a power control circuit. That is, a control signal E is input to an input terminal EI of the power switch circuit SW 1  in the initial stage. After a predetermined delay time elapses, the control signal E is provided from an output terminal EO to the power switch circuit SW 2  in the next stage. 
         [0005]    In the same manner, the power switch circuit SW 2  becomes conductive in response to the control signal E input to the input terminal EI. After a predetermined delay time elapses, the control signal E is provided from an output terminal EO to the power switch circuit SW 3  in the next stage. 
         [0006]      FIG. 6  shows the structure of the power switch circuits SW 1  to SWn. The power switch circuits SW 1  to SWn have identical structures. Thus, the power switch circuit SW 1  will now be described. 
         [0007]    The control signal E is input to the input terminal EI and provided to the gate of a P-channel MOS transistor T 1 . Therefore, when an L level signal is input to the input terminal EI, the transistor T 1  becomes conductive and the power V DD , which is supplied to a terminal PS, is supplied from a terminal PD to the logic circuit  1 . 
         [0008]    The signal EI input to the input terminal E is output from the output terminal EO through a time difference generation circuit  2 . The time difference generation circuit  2  includes, for example, an even number of series-coupled inverter circuits  3  as shown in  FIG. 7 . 
         [0009]    In such a configuration, each of the power switch circuits SW 1  to SWn transfers the control signal E after the delay time set by the time difference generation circuit  2  elapses. Thus, the transistors T 1  sequentially become conductive as the control signal E and the power V DD  is sequentially supplied to the logic circuits  1 . 
         [0010]    In the semiconductor integrated circuit device that includes the power switch circuits SW 1  to SWn, the power switch circuits SW 1  to SWn sequentially become conductive, and the plurality of logic circuits  1  are sequentially supplied with the power V DD . This suppresses the transient current. 
         [0011]    However, the timing difference in which the power switch circuits SW 1  to SWn become conductive is fixed by the time difference generation circuit  2 . Thus, when a transient current flows to the power switch circuit in the preceding stage due to a load change in the logic circuit  1 , this may cause the power switch circuit in the next stage to become conductive. 
         [0012]    Transient current may flow in parallel to the plurality of power switch circuits. This results in a shortcoming in which an increase in the transient current still cannot be suppressed. 
       SUMMARY 
       [0013]    It is an object of the present invention to provide a power switch circuit that ensures suppression of increases in transient currents. 
         [0014]    A first aspect of the present invention provides a power switch circuit. The power switch circuit includes a first transistor which generates an output voltage in response to a control signal. A time difference generation circuit delays the control signal by performing a logical process with the control signal and the output voltage of the first transistor. 
         [0015]    A second aspect of the present invention provides a semiconductor integrated circuit device. The semiconductor integrated circuit device includes a plurality of logic circuits and a plurality of power switch circuits which sequentially become conductive in response to a control signal and which are respectively coupled to the plurality of logic circuits. Each of the plurality of power switch circuits includes a first transistor, which generates an output voltage in accordance with a voltage of a high potential power supply in response to the control signal and supplies the output voltage to the corresponding logic circuit, and a time difference generation circuit, which delays the control signal by performing a logical process with the control signal and the output voltage of the first transistor. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0016]      FIG. 1  is a block diagram showing a first embodiment of the semiconductor integrated circuit including a plurality of power switch circuits; 
           [0017]      FIG. 2  is a circuit diagram of the power switch circuit of  FIG. 1 ; 
           [0018]      FIG. 3  is a circuit diagram showing the power switch circuit of a second embodiment; 
           [0019]      FIG. 4  is a block diagram showing a third embodiment of the semiconductor integrated circuit including a plurality of power switch circuits; 
           [0020]      FIG. 5  is a block diagram showing a prior art semiconductor integrated circuit including a plurality of power switch circuits; 
           [0021]      FIG. 6  is a circuit diagram of the power switch circuit of  FIG. 5 ; and 
           [0022]      FIG. 7  is a circuit diagram of the power switch circuit of  FIG. 5 . 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
     First Embodiment 
       [0023]    A first embodiment of a semiconductor integrated circuit device according to the present invention will now be discussed with reference to the drawings. 
         [0024]      FIG. 1  shows a semiconductor integrated circuit device including a plurality of power switch circuits SWX 1  to SWXn respectively supplying a plurality of logic circuits  1  with power V DD . The power switch circuits SWX 1  to SWXn sequentially become conductive in response to a control signal E provided from a power control circuit  11  to sequentially supply the plurality of logic circuits  1  with the power V DD . 
         [0025]    The power switch circuits SWX 1  to SWXn have identical structures. Thus, the structure of the power switch circuit SWX 1  will now be described in detail with reference to  FIG. 2 . 
         [0026]    Input terminal EI, which receives a control signal E, is coupled to the gate of a P-channel MOS transistor T 1 , which is a switch transistor. The transistor T 1  has a source coupled to a terminal PS, which receives the power V DD , and a drain coupled to a terminal PD, which supplies the power V DD  to the logic circuit  1 . 
         [0027]    The input terminal EI is coupled to the initial one of the two stages of series-coupled inverter circuits  13   a  and  13   b , and the output terminal of the next stage inverter circuit  13   b  is coupled to an output terminal EO of the power switch circuit SWX 1 . In the first embodiment, the inverter circuits  13   a  and  13   b  form a transfer unit. 
         [0028]    The inverter circuit  13   a  is configured by a P-channel MOS transistor TP 1  and an N-channel MOS transistor TN 1 , and the inverter circuit  13   b  is configured by a P-channel MOS transistor TP 2  and an N-channel MOS transistor TN 2 . The sources of the transistors TP 1  and TP 2  are coupled to the terminal PS. Power V SS  is supplied to the source of the transistor TN 1  in the inverter circuit  13   a.    
         [0029]    An N-channel MOS transistor (activation transistor) T 2  is arranged between the power VSS and the source of the transistor TN 2  of the inverter circuit  13   b , and the gate of the transistor T 2  is coupled to the terminal PD. The threshold value of the transistor T 2  is desirably set at a high value. In the first embodiment, the inverter circuits  13   a  and  13   b  and transistor T 2  form a time difference generation circuit  20 . 
         [0030]    As shown in  FIG. 1 , the output signal power switch circuit SWXn in the final stage is supplied to an EOR (exclusive OR) circuit  12 , which is a logical operation circuit. The EOR circuit  12  performs an exclusive OR operation with the control signal E provided to the first stage power switch circuit SWX 1  and the output signal of the power switch circuit SWXn to generate a determination signal representing the operation result. 
         [0031]    The operation of the semiconductor integrated circuit device including the power switch circuits SWX 1  to SWXn will now be discussed. 
         [0032]    In each of the power switch circuits SWX 1  to SWXn, when an L level signal E is provided to the input terminal EI, the transistor T 1  is activated thereby starting the supply of the power V DD  from the terminal PD to the logic circuit  1 . Further, a transient current starts to flow to the logic circuit  1 . Also, the control signal E is transferred to the inverter circuits  13   a  and  13   b.    
         [0033]    As the transient current of the logic circuit  1  converges and the potential at the terminal PD increases to a level close to the power V DD , the transistor T 2  is activated. This activates the inverter circuit  13   b , and an L level output signal having the same phase as the control signal E is output from the output terminal EO. 
         [0034]    In each of the power switch circuit SWX 1  to SWXn, such an operation supplies current from the terminal PD to the logic circuit  1  based on the input of an L level control signal E. After the transient current converges and the terminal PD increases to a level close to the power V DD , an L level output signal is provided from the output terminal EO to the next stage power switch circuit. Therefore, the next stage power switch circuit does not become conductive during a period in which a transient current flows from a single power switch circuit to the logic circuit  1 . 
         [0035]    After an H level control signal E is output from the power control circuit  11  and the control signal E falls to an L level to supply the power V DD  to each logic circuit  1 , the EOR circuit  12  generates an H level determination signal F as an initial value. 
         [0036]    Then, when an L level output signal is output from the output terminal EO of the power switch circuit SWXn in the final stage based on the L level control signal E provided from the power control circuit  11 , the EOR circuit  12  generates an L level determination signal F. 
         [0037]    As a result, by using, for example, an external device (not shown) to detect the L level determination signal F, it can be verified that the transistor T 1  of each of the power switch circuits SWX 1  to SWXn is operating normally and the power V DD  is being supplied to the logic circuits  1 . 
         [0038]    This is because the transistor T 1  must operate normally and the potential at the terminal PD must increase for the output signal of the power switch circuits SWX 1  to SWXn to fall to the L level. 
         [0039]    When the determination signal F remains at the H level without falling to the L level after the L level control signal E is output from the power control circuit  11 , there is a possibility that the transistor T 1  in one of the logic circuits  1  is not operating normally or an abnormal current continuously flowing in one of the logic circuits  1 . Therefore, the use of the external device enables determination of whether there is an abnormality in the semiconductor integrated circuit device. 
         [0040]    When an H level control signal E is output from the power control circuit  11 , that is, in a standby state, the transistor T 1  in the power switch circuit SWX 1  is inactivated. This stops the supply of power from the power switch circuit SWX 1  to the logic circuit  1  and stops the flow of leakage current from the power V DD  to the logic circuit  1 . 
         [0041]    The H level control signal E also generates an L level output signal with the inverter circuit  13   a  and an H level output signal EO with the inverter circuit  13   b . Therefore, an H level signal is supplied to the input terminals ET of every one of the power switch circuits SWX 1  to SWXn. Further, in the same manner as the power switch circuit SWX 1 , the supply of power to the logic circuits corresponding to the power switch circuits SWX 2  to SWXn is stopped, and the flow of leakage current is stopped. 
         [0042]    The power switch circuits SWX 1  to SWXn of the first embodiment has the advantages described below. 
         [0043]    (1) Regardless of a load change in each logic circuit  1 , transient current does not flow in parallel to the logic circuits  1  from two or more power switch circuits. Therefore, an increase in the transient current is suppressed, and fluctuation of the power voltage is also suppressed. 
         [0044]    (2) During operation testing, the determination signal F may be used to determine whether or not the transistor T 1  of each power switch circuit is operating normally. 
         [0045]    (3) During normal usage, the determination signal F may be used to determine whether or not abnormal current is flowing to the logic circuits  1  when power is being supplied from the power switch circuits to the logic circuits  1 . 
         [0046]    (4) If the control signal E is set at an H level in a standby state, the supply of the power V DD  from the power switch circuits SWX 1  to SWXn to the logic circuits  1  is stopped, and the flow of leakage current from the power V DD  to the logic circuits  1  is stopped. 
       Second Embodiment  
       [0047]      FIG. 3  shows a second embodiment. The second embodiment uses different power switch circuits SWX 1  to SWXn. In the second embodiment, the switch transistor T 1  of each of the power switch circuits SWX 1  to SWXn shown in  FIG. 2  is replaced by an N-channel MOS transistor T 3 . The same reference numbers are given to parts of the power switch circuits SWX 1  to SWXn that are the same as those of the first embodiment. 
         [0048]    The input terminal EI, which receives the control signal E, is coupled to the gate of an N-channel MOS transistor T 3 , which is a switch transistor. The transistor T 3  has a drain coupled to the terminal PS, which receives the power V DD , and the source is coupled to the terminal PD, which supplies the power V DD  to the logic circuit  1 . 
         [0049]    The input terminal EI is coupled to the initial one of the two stages of series-coupled inverter circuits  13   a  and  13   b , and the output terminal of the next stage inverter circuit  13   b  is coupled to the output terminal EO of the power switch circuit. 
         [0050]    The sources of the P-channel MOS transistors TP 1  and TP 2  of the inverter circuits  13   a  and  13   b  are coupled to the terminal PS, and an N-channel MOS transistor T 4  is arranged between the power V SS  and the source of the N-channel MOS transistor TN 1  in the inverter circuit  13   a . In the second embodiment, the inverter circuits  13   a  and  13   b  and the transistor T 4  form a time difference generation circuit  30 . 
         [0051]    In the power switch circuit SWX 1 , when the control signal E rises to the H level, the transistor T 3  is activated and the power V DD  is supplied from the terminal PD to the logic circuit  1 . Further, transient current flowing to the logic circuit  1  is converged, and when the terminal PD increases to a level close to the power V DD , the transistor T 4  is activated and the inverter circuit  13   a  is activated. Therefore, the inverter circuit  13   a  generates an L level output signal. 
         [0052]    As a result, the output signal of the inverter circuit  13   b  rises to the H level, and an H level output signal is output from the output terminal EO to the power switch circuit in the next stage. 
         [0053]    When the control signal E falls to the L level, the transistor T 3  is inactivated, the supply of the power V DD  to the logic circuit  1  is stopped, and the flow of leakage current to the logic circuit  1  is stopped. Then, an L level output signal is provided from the output terminal to the power switch circuit in the next stage, and each power switch operates in the same manner. 
         [0054]    In the second embodiment, such an operation obtains the same advantages as the power switch circuits of the first embodiment. 
       Third Embodiment 
       [0055]      FIG. 4  shows a third embodiment. In the third embodiment, switch transistors Ts (T 5 , T 6 , T 7 , and T 8  in  FIG. 4 ) are arranged between the logic circuits  1  and the power switch circuits SWX 1  to SWXn of the first embodiment. Further, control signals E 1  to En are provided from a power control circuit  13  to the gate of each transistor Ts. 
         [0056]    The transistors Ts are configured by P-channel MOS transistors and connect the logic circuits  1  and the power switch circuits SWX 1  to SWXn when the control signal E 1  through En falls to an L level. Further, the transistors Ts uncouple the logic circuits  1  and the power switch circuits SWX 1  to SWXn when the control signal E 1  through En rises to an H level. The other parts are the same as the first embodiment. 
         [0057]    In such a configuration, when the L level control signal E is provided from the power control circuit  13  to the power switch circuit SWX 1 , the control signal E is sequentially transferred to the power switch circuits in the subsequent stages in the same manner as the first embodiment. 
         [0058]    Then, when power V DD  is supplied from the terminal PD of each of the power switch circuits SWX 1  to SWXn, the power V DD  is supplied to the logic circuit  1  through the transistor Ts that has been activated by the control signals E 1  to En. 
         [0059]    Therefore, the logic circuits  1  supplied with the power V DD  from the power switch circuits SWX 1  to SWXn are selective with the control signals E 1  through En. 
         [0060]    When the L level control signal E provided from the power control circuit  13  rises to an H level, the switch transistor is inactivated in each of the power switch circuits SWX 1  to SWXn, the supply of power V DD  to the terminal PD is stopped, and the flow of leakage current to the logic circuit  1  is stopped. 
         [0061]    In addition to the advantages of the first embodiment, the third embodiment has the advantage described below. 
         [0062]    (5) The logic circuits  1  that are supplied with the power V DD  from the power switch circuits SWX 1  to SWXn may be selected with the control signal E 1  to En.