Abstract:
The present invention generally relates to setup/hold time control devices, and more specifically, to a setup/hold time control device which can change setup/hold time of various control signals applied from an input buffer by software operation commands. The setup/hold time control device of the present invention comprises transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the present invention can provide a technique which can optimize the setup/hold time with small cost in comparison with a physical metal option control system.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention generally relates to a setup/hold time control device, and more specifically, to a technique to control setup/hold time of various control signals applied from an input buffer by a software operation command.  
           [0003]    2. Description of the Prior Art  
           [0004]    [0004]FIG. 1 is a circuit diagram illustrating a conventional setup/hold time control device.  
           [0005]    The conventional setup/hold time control device comprises inverters IV 1 ˜IV 4  for performing a driver function, MOS capacitors C 1 ˜C 4  for performing a signal delay function, metal option unit  2  and  3 , and a latch  4 .  
           [0006]    Here, the inverters IV 1  and IV 2  outputs signals by driving an address, a command signal or input data applied from an input buffer  1 . The inverter IV 3  outputs a signal by driving an output signal of the metal option unit  2 . The inverter IV 4  drives an output signal of the metal option unit  3  to provide a global bus line control signal GB_BL to the latch  4 .  
           [0007]    The metal option units  2  and  3  comprising metal option switches MO 1 ˜MO 4  selectively control the MOS capacitors C 1 ˜C 4  to control seup/hole time of the global bus line control signal GB_BL.  
           [0008]    The MOS capacitors C 1  and C 2  are selectivel connected to an output terminal of the inverter IV 2  by the metal option switches MO 1  and MO 2 . The MOS capacitors C 3  and C 4  are selectively connected to an output terminal of the inverter IV 3  by the metal option switches MO 3  and MO 4 .  
           [0009]    The latch  4  latches the global bus line control signal GB_BL in synchronization with a clock signal CLK to output the latched signal into a global bus line (not shown). Here, in order that the global bus line control signal GB_BL inputted into the latch  4  may be valid, the global bus line control signal GB_BL should be transmitted into the latch earlier than the clock signal CLK by a predetermined time (setup time). When the latch  4  performs a latch operation in synchronization with the clock signal, a state of the global bus line control signal GB_BL should be maintained for a predetermined time (hold time).  
           [0010]    Here, it is most ideal that the clock signal CLK is enabled after the setup time of the global bus line control signal, and the state of the global bus line control signal GB_BL for the hold time.  
           [0011]    However, it is difficult to satisfy the above ideal condition because signals inputted externally from an actual chip through the input buffer  1  are influenced by length of an internal transmission line, various noises, capacitance or resistance.  
           [0012]    Accordingly, the conventional setup/hole time control device is designed to control the setup/hold time of the global bus line control signal GB_BL by selectively connecting signal delay devices such as the MOS capacitors C 1 ˜C 4  for delaying signals to the drivers IV 1 ˜IV 4 .  
           [0013]    In other words, the metal option switches MO 1 ˜MO 4  needing physical apparatus are used to regulate the setup/hold time of the global bus line control signal. As a result, since variations in circuits of metal layers are required to regulate the setup/hold time, the conventional device has a problem of physically long time and high cost consumption.  
         SUMMARY OF THE INVENTION  
         [0014]    In order to overcome the above-described problem, the present invention has an object to provide a setup/hold time control device to appropriately control setup/hold time of various control signals applied to a global bus line by controlling setup/hold time of various signals applied from an input buffer according to a decoded test mode control signal.  
           [0015]    There is provided a setup/hole time control apparatus, comprising: a driver for outputting a global bus line control signal by driving an output signal of an input buffer; a signal delay unit for delaying the global bus line control signal selectively connected to the driver; a decoding unit for outputting a test mode delay signal by decoding a test control signal for determining to control setup/hold time corresponding to the global bus line control signal, a test mode entry signal, and a test mode end signal; and a delay control unit for controlling the setup/holde time of the global bus line control signal by selectively connecting the signal delay unit to the driver according to a state of the test mode delay signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a circuit diagram illustrating a conventional setup/hold time control device.  
         [0017]    [0017]FIG. 2 is a circuit diagram illustrating a setup/hold time control device according to the present invention.  
         [0018]    [0018]FIG. 3 is a circuit diagram illustrating a decoding unit according to the present invention.  
         [0019]    [0019]FIG. 4 is an operating timing diagram illustrating a setup/hold time control device according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]    The present invention will be described in detail referring to the accompanying drawings.  
         [0021]    [0021]FIG. 2 is a circuit diagram illustrating a setup/hold time control device according to the present invention.  
         [0022]    Referring to FIG. 2, the setup/hold time control device of the present invention comprises a driver  20 , signal delay units  30  and  40 , delay control units  50  and  60 , and a latch  70 .  
         [0023]    The driver  20  comprises inverters IV 5 ˜IV 8  for outputting a global bus line control signal GB_BL into a latch  70  by driving an address applied from an input buffer  10 , a command signal or input data. Here, the inverters IV 5  and IV 6  output signals by driving an output signal of the input buffer  10 . The inverter IV 7  outputs a signal by driving an output signal of the delay control unit  50 . The inverter IV 8  drives an output signal of the delay control unit  60  to provide the global bus line control signal GB_BL to the latch  70 .  
         [0024]    The signal delay unit  30  comprises MOS capacitors C 5  and C 6  selectively connected to an output terminal of the inverter IV 6  by the delay control unit  50 . The signal delay unit  40  comprises MOS capacitors C 7  and C 8  selectively connected to an output terminal of the inverter IV 7  by the delay control unit  60 .  
         [0025]    The delay control unit  50  comprising an inverter IV 9  and transmission gates T 1  and T 2  selectively controls MOS capacitors C 5  and C 6  to control the setup/hold time of the global bus line control signal provided to the latch  70 . The inverter IV 9  inverts a test mode delay signal TM_DLY&lt;0&gt;. The transmission gates T 1  and T 2  selectively connects the MOS capacitors C 5  and C 6  to the output terminal of the inverter IV 6  according to a state of the test mode delay signal TM_DLY&lt;0&gt;.  
         [0026]    Here, the transmission gates T 1  and T 2  receive the test mode delay signal TM_DLY&lt;0&gt; through a NMOS gate, and the inverted test mode delay signal TM_DLY&lt;0&gt; by the inverter IV 9  through a PMOS gate.  
         [0027]    The delay control unit  60  comprising an inverter IV 10  and transmission gates T 3  and T 4  selectively controls MOS capacitors C 7  and C 8  to control the setup/hold time of the global bus line control signal provided to the latch  70 . The inverter IV 10  inverts a test mode delay signal TM_DLY&lt;1&gt;. The transmission gates T 3  and T 4  selectively connects the MOS capacitors C 7  and C 8  to the output terminal of the inverter IV 7  according to a state of the test mode delay signal TM_DLY&lt;1&gt;.  
         [0028]    Here, the transmission gates T 3  and T 4  receive the test mode delay signal TM_DLY&lt;0&gt; through a NMOS gate, the test mode delay signal TM_DLY&lt;1&gt; through a PMOS gate, and the inverted test mode delay signal TM_DLY&lt;1&gt; by the inverter IV 10  through a NMOS gate.  
         [0029]    The latch  70  latches the global bus line control signal GB_BL in synchronization with a clock signal CLK to output the latched signal into a global bus line (not shown).  
         [0030]    [0030]FIG. 3 is a circuit diagram illustrating a decoding unit for controlling the test mode delay signal TM_DLY&lt;0&gt; of FIG. 2.  
         [0031]    The decoding unit comprises a logic unit  80  and latches  90  and  100 . The logic unit  80  logically operates a test control signal TCS and a test mode entry signal TM_EP. The latches  90  and  100  latches an output signal of the logic unit  80  and an test mode end signal TM_EXP to output a test mode delay signal TM_DLY&lt;1:0&gt;.  
         [0032]    Here, the logic unit  80  comprises an inverter IV 11  and NAND gates ND 1  and ND 2 . The inverter IV 11  inverts a test control signal TCS. The NAND gate ND 1  NANDs a the test control signal TCS and the test mode entry signal TM_EP. The NAND gate ND 2  NANDs the test mode entry signal TM_EP and an output signal of the inverter IV 11 .  
         [0033]    The latch  90  comprises NAND gates ND 3  and ND 4  for feeding back each output signal as an input signal each other. A NAND gate ND 3  NANDs an output signal of the NAND gate ND 1  and an output signal of the NAND gate ND 4  to output the test mode delay signal TM_DLY&lt;0&gt;. The NAND gate ND 4  NANDs the test mode end signal TM_EXP and an output signal of the NAND gate ND 3 .  
         [0034]    The latch  100  comprises NAND gates ND 5  and ND 6  for feeding back each output signal as an input signal each other. The NAND gate ND 5  NANDs an output signal of the NAND gate ND 2  and an output signal of the NAND gate ND 6  to output the test mode delay signal TM_DLY&lt;1&gt;. The NAND gate ND 6  NANDs the test mode end signal TM_EXP and an output signal of the NAND gate ND 5 .  
         [0035]    The operation process o the setup/hold time control device is described referring to FIG. 4.  
         [0036]    In a case of a normal operation mode, the test mode delay signal TM_DLY&lt;1:0&gt; becomes at a low state. When the test mode delay signal TM_DLY&lt;0&gt; is at a low state, the transmission gates T 1  and T 2  are all turned off, outputs of the MOS capacitors C 5  and C 6  do not affect an output terminal of the inverter IV 6 . When the test mode delay signal TM_DLY&lt;1&gt; is at a low sate, the transmission gates T 3  and T 4  are turned on, and an output terminal of the inverter IV 7  is connected to the MOS capacitors C 7  and C 8 . AS a result, an output signal of the inverter IV 7  is delayed by the MOS capacitors C 7  and C 8 , and the global bus line control signal GB_BL is delayed.  
         [0037]    In order to delay the setup/hold time of the global mode delay signal GB_BL in a test mode state, the decoding unit is controlled to have the test mode delay signal TM_DLY&lt;0&gt; at a high level. On the other hand, in order to advance the setup/hold time of the global bus line control signal GB_BL, the delay unit is controlled to have the test mode delay signal TM_DLY&lt;1&gt; at a high level.  
         [0038]    When the test control signal TCS is at a high level, in order to delay the setup/hold time of the global bus line control signal GB_BL, the test mode entry signal TM_EP is enabled to a high level.  
         [0039]    When the test mode entry signal TM_EP is enabled to the high level, the NAND gate of the logic unit  80  outputs a low signal, and the NAND gate ND 2  outputs a high signal. Then, the latch  90  outputs the test mode delay signal TM_DLY&lt;0&gt; at the high level, and the latch  100  outputs the test mode delay signal TM_DLY&lt;1&gt; at the low level.  
         [0040]    Thereafter, when the test mode delay signal TM_DLY&lt;0&gt; becomes at the high level, the transmission gates T 1  and T 2  of the delay control unit  50  are all turned on, and an output signal of the inverter IV 6  is delayed by the capacitors C 5  and C 6 . When the test mode delay signal TM_DLY&lt;1&gt; becomes at the low level, the transmission gates T 3  and T 4  of the delay control unit  60  are all turned on, and an output signal of the inverter IV 10  is delayed by the MOS capacitors C 7  and C 8 .  
         [0041]    Next, when a test mode end signal TM_EXPb is generated, the test mode delay signal TM_DLY&lt;0&gt; is disabled to the low level, and maintained at a normal state.  
         [0042]    As a result, when the test control signal TCS is at the high level, the test mode delay signal TM_DLY&lt;0&gt; becomes at the high level to delay the setup/hold time of the global bus line control signal GB_BL.  
         [0043]    On the other hand, when the test control signal TCS is at the low level, the test mode entry signal TM_EP is enabled to the high level to advance the setup/hold time of the global bus line control signal.  
         [0044]    When the test mode entry signal TM_EP is enabled to the high level, the NAND gate ND 1  of the logic unit  80  outputs a high signal, and the NAND gate ND 2  outputs a low signal. Then, the latch  90  outputs the test mode delay signal TM_DLY&lt;0&gt; at the low level, and the latch  100  outputs the test mode delay signal TM_DLY&lt;1&gt; at the high level.  
         [0045]    Next, when the test mode delay signal TM_DLY&lt;0&gt; becomes at the low level, the transmission gates T 1  and T 2  of the delay control unit  50  are all turned off, and output signal of the inverter IV 6  is not delayed. When the test mode delay signal TM_DLY&lt;1&gt; becomes at the high level, the transmission gates T 3  and T 4  of the delay control unit  60  are all turned off, and an output signal of the inverter IV 7  is not delayed.  
         [0046]    Thereafter, when the test mode end signal TM_EXPb is generated, the test mode delay signal TM_DLY&lt;1&gt; is disabled to the low level, and maintained at a normal state.  
         [0047]    Accordingly, when the test control signal TCS is at the low level, the test mode delay signal TM_DLY&lt;1&gt; becomes at the high level to advance the setup/holde time of the global bus line control signal GB_BL.  
         [0048]    As discussed earlier, a setup/hold time control signal of the present invention can optimize the setup/hold time with small cost by changing the setup/hold time of control signals outputted from an input buffer by software operation commands without any physical variation in metal layers.