Abstract:
Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, that tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Description:
FIELD OF THE INVENTION 
       [0001]    Certain embodiments of the invention relate generally to comparators, and more particularly to a cascoded comparator with dynamic biasing for column parallel single slope ADCs. 
       BACKGROUND OF THE INVENTION 
       [0002]    As computers and processors become more powerful, more and more signal processing is being done in the digital domain. Digital signal processing can perform complex operations to manipulate input data to approximate real world analog signals, and the operations can be performed in real time, or the digital data can be stored for future processing. Since real world signals exist as analog signals, these analog signals need to be converted to equivalent digital signals. 
         [0003]    Analog to digital converters (ADCs) are used in many applications, such as, for example, converting analog control signals in industrial applications, audio signals in music, photographic images in digital cameras, and video images in digital video cameras. As with most circuits, there are many different types of ADCs where tradeoffs are made for different limitations. Some, such as the “flash” ADC, are relatively expensive in circuitry and layout space and, accordingly, limited in resolution since every additional bit requires doubling of the number of comparators, but very fast in conversion speed. Others, such as the ramp ADC, can be fairly simple but slow in conversion time. And as the amount of resolution increases, the conversion time will increase. 
         [0004]    Accordingly, a particular application needs to take into account various limitations and determine which design best serves its purposes. However, picking a specific design, and possibly modifying it to improve its design, can still present certain challenges that need to be overcome. 
         [0005]    For high resolution and high speed imaging, column parallel ADC architecture has become the most widely used ADC in CMOS image sensors. One key challenge to achieving good performance of CMOS image sensors is to reduce noise or other signal offsets from affecting the converted digital data. 
         [0006]    With column parallel single slope ADCs, all comparators are connected to a common ramp signal. If there is a large uniform area in an image, many comparators may have the same pixel value. Accordingly, many comparators can toggle at the same time as the input ramp signal reaches the pixel voltage. The toggling comparator outputs can couple to the input ramp signal and create a glitch that can affect the conversion of other pixels in that row. 
         [0007]    A method to eliminate this coupling is to cascode transistors to the comparator differential pair. With cascoded transistors, when the comparator outputs toggle the cascode transistor clamps the drain voltage of the input transistor so that there is no switching signal to couple to the input ramp signal. The problem with adding cascodes to the comparator input circuit is that the input signals are not constant and have a wide full scale range. Therefore it is difficult to select an optimal cascode bias voltage. 
         [0008]    Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings. 
       BRIEF SUMMARY OF THE INVENTION 
       [0009]    Certain embodiments of the invention provide a cascoded comparator with dynamic biasing for column parallel single slope ADCs. Aspects of the invention may comprise receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, may track the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively. 
         [0010]    The first input signal is a downwardly ramping voltage signal and the second input signal is a sampled pixel voltage. The output signal may be dependent on comparison of a voltage level of the first input signal to a voltage level of the second input signal. 
         [0011]    An embodiment of the invention for a cascoded comparator with dynamic biasing for column parallel single slope ADCs where the comparator has a single ended output may comprise a first PMOS transistor with a source terminal coupled to a positive voltage supply, and a drain terminal of the first PMOS transistor coupled to a source terminal of a second PMOS transistor and to a source terminal of a third PMOS transistor. A fourth PMOS transistor may have a source terminal coupled to the drain terminal of the second PMOS transistor, and a fifth PMOS transistor may have a source terminal coupled to the drain terminal of the third PMOS transistor. 
         [0012]    A first NMOS transistor may have a drain terminal coupled to a drain terminal of the fourth PMOS transistor, and a second NMOS transistor may have a drain terminal coupled to a drain terminal of the fifth PMOS transistor, to a gate of the first NMOS transistor, and to a gate of the second NMOS transistor. A source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor may be coupled to ground. 
         [0013]    A cascode bias generator with an output terminal may be coupled to a gate of the fourth PMOS transistor, and a gate of the fifth PMOS transistor. An input terminal of the cascode bias generator may receive a first input ramp signal. 
         [0014]    Furthermore, a biasing signal may be applied to a gate terminal of the first PMOS transistor, and a second input ramp signal may be applied to a gate terminal of the second PMOS transistor. An input pixel signal may be applied to a gate terminal of the third PMOS transistor, and a cascode biasing signal generated by the cascode bias generator may be applied to a gate terminal of the fourth PMOS transistor and to a gate terminal of the fifth PMOS transistor. The cascode biasing signal, which may be offset by a substantially fixed voltage with respect to the input ramp signal, may track the input ramp signal. An output signal may be at the node where the drain terminal of the fourth PMOS transistor is coupled to the drain terminal of the first NMOS transistor. 
         [0015]    An embodiment of the invention for a cascoded comparator with dynamic biasing for column parallel single slope ADCs where the comparator has differential outputs may comprise a first PMOS transistor with a source terminal coupled to a positive voltage supply, and a drain terminal of the first PMOS transistor coupled to a source terminal of each of a second PMOS transistor and a third PMOS transistor. A fourth PMOS transistor with a source terminal may be coupled to the drain terminal of the second PMOS transistor, and a fifth PMOS transistor may have a source terminal coupled to the drain terminal of the third PMOS transistor. 
         [0016]    A first NMOS transistor may have a drain terminal coupled to a drain terminal of the fourth PMOS transistor, to a gate terminal of the first NMOS transistor, to a drain terminal of a second NMOS transistor, and to a gate terminal of a third NMOS transistor. A fourth NMOS transistor may have a drain terminal coupled to a drain terminal of the fifth PMOS transistor, to a gate terminal of the fourth NMOS transistor, to a drain terminal of the third NMOS transistor, and to a gate terminal of the second NMOS transistor. 
         [0017]    A source terminal of each of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor are coupled to ground. A cascode bias generator may have an output terminal coupled to a gate terminal of the fourth PMOS transistor and to a gate terminal of the fifth PMOS transistor. 
         [0018]    Furthermore, a biasing signal may be applied to a gate terminal of the first PMOS transistor. A first input ramp signal may be applied to a gate terminal of the second PMOS transistor, an input pixel signal may be applied to a gate terminal of the third PMOS transistor, and a second input ramp signal may be applied to an input terminal of the cascode bias generator. A cascode biasing signal generated by the cascode bias generator may be applied to a gate terminal of the fourth PMOS transistor and to a gate terminal of the fifth PMOS transistor. 
         [0019]    The cascode biasing signal, offset by a substantially fixed voltage from the first input ramp signal, may track the first input ramp signal. A first differential output signal may be at the node where the drain terminals of the first and second NMOS transistors are coupled, and a second differential output signal may be at the node where the drain terminals of the third and fourth NMOS transistors are coupled. 
         [0020]    An embodiment of the invention for a cascoded comparator with dynamic biasing for column parallel single slope ADCs may comprise a cascode bias generator, where the cascode bias generator comprises a first PMOS transistor that has a source terminal coupled to a positive voltage supply, and a drain terminal of the first PMOS transistor coupled to a source terminal of a second PMOS transistor and to a source terminal of a third PMOS transistor. 
         [0021]    A first NMOS transistor that has a drain terminal coupled to a drain terminal of the second PMOS transistor and to a gate terminal of the second PMOS transistor. The cascode bias generator may comprise a second NMOS transistor that has a drain terminal coupled to a drain terminal of the third PMOS transistor, and to a gate of the second NMOS transistor. A source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor may be coupled to ground. 
         [0022]    A first biasing signal applied to a gate terminal of the first PMOS transistor, an input ramp signal applied to a gate terminal of the third PMOS transistor, and a second biasing signal is applied to a gate terminal of the first NMOS transistor. 
         [0023]    An output signal, which is the cascode biasing signal, is at the node where the drain terminal of the second PMOS transistor is coupled to the gate terminal of the second PMOS transistor and to the drain terminal of the first NMOS transistor. The output signal, which may be offset by a substantially fixed voltage with respect to the input ramp signal, may track the input ramp signal. 
         [0024]    These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0025]      FIG. 1  is a block diagram of exemplary system for analog to digital conversion that may be used with an embodiment of the invention. 
           [0026]      FIG. 2  is a block diagram of an exemplary system for column parallel analog digital converters that may be used with an embodiment of the invention. 
           [0027]      FIG. 3  is a block diagram of an exemplary comparator architecture that may be used with an embodiment of the invention. 
           [0028]      FIG. 4A  is a schematic of an exemplary single ended output cascoded comparator in conjunction with a cascode bias generator in accordance with an embodiment of the invention. 
           [0029]      FIG. 4B  is a schematic of an exemplary differential output cascoded comparator in conjunction with a cascode bias generator in accordance with an embodiment of the invention. 
           [0030]      FIG. 5  is a schematic of an exemplary dynamic biasing circuitry in accordance with an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0031]    Embodiments of the present invention will be described in detail with reference to the accompanying drawings such that the scope of the present invention can be easily embodied by those skilled in the art. 
         [0032]    Certain embodiments of the invention may be found in a method and system for a cascoded comparator with dynamic biasing for column parallel single slope analog to digital comparators (ADCs). 
         [0033]      FIG. 1  is a block diagram of exemplary system for analog to digital conversion and digital to analog conversion that may be used with an embodiment of the invention. Referring to  FIG. 1 , there is shown a portion of a circuitry for processing input data, comprising the ADC  110 , the processor  120 , and the control logic  130 . 
         [0034]    The ADC  110  converts input analog signals, such as, for example, pixel signals from a video image sensor (not shown in  FIG. 1 ) to equivalent digital signals. The digital signals output by the ADC  110  may be further processed by the processor  120 . The processor  120  may, for example, use digital signal processing methods to compress the digital signals from the ADC  110  to a standard video format such as MPEG1, MPEG2, or MPEG4. The processor  120  may also comprise a memory block  122  where code may be stored. This code may be executed by the processor  120  to perform various functions such as, for example, digital signal processing. The memory block  122  may also be used to store digital signals from the ADC  110  and/or digital signals that result from processing the digital signal from the ADC  110 . 
         [0035]    The control logic  130  may comprise circuitry that generates clocks, control and enable signals, and commands for a variety of modules, such as the ADC  110 . For example, the control logic  130  may generate a clock signal that is used for counting in the ADC  110 , where the clock signal is not continuously running. A running clock comprises pulses while a non-running clock is in either a low state or a high state. The control logic  130  may also output enable signals that enable the counters in the ADC  110  to count during specific portions of time, and also reset signals. 
         [0036]      FIG. 2  is a block diagram of an exemplary column parallel analog digital converter configuration that may be used with an embodiment of the invention. Referring to  FIG. 2 , there are shown a pixel array  200  and an ADC array  210 . The pixel array  200  may comprise pixel elements  201  and switching elements  202 . The pixel elements  201  may comprise suitable circuitry that outputs, for example, voltage proportional to an amount of light detected by the pixel element  201 . The pixel element  201  may be sensitive to specific wavelengths of the impinging light. The ADC array  210  may comprise, for example, an array of ADC elements  211 , where each ADC element  211  may correspond to a column of the pixel elements  201 . The outputs of the ADC elements  211  may be stored in a memory block  212 . The ADC element  211  may comprise, for example, a comparator element (not shown) and a counter (not shown). 
         [0037]    In operation, appropriate control signals from, for example, the control logic  130  may enable the switching elements  202  to open and close appropriately so that output voltage from a particular pixel element  201  is communicated to the ADC array  210 . Accordingly, for each column Column — 1 to Column_m, only one particular switch element  202  in all of the rows Row — 1 to Row_n may be closed during a row scan time so that output voltage from the corresponding pixel element  201  is communicated to the ADC array  210  during that scan time. Therefore a true pixel voltage may be communicated to a corresponding ADC element  211  when only one pixel is selected for the column. 
         [0038]    The output voltage from one of the pixel elements  201  in each of the columns Column — 1 to Column_m may be converted to equivalent digital values by the corresponding ADC elements  211 . However, since there is a plurality of ADC elements  211 , each ADC element  211  may need to be calibrated so that each ADC element  211  outputs a similar digital value for a given input. Calibration may be done periodically, for example, such as once during a row scan time or once during a frame. The particular period for calibration may be design and/or implementation dependent. 
         [0039]      FIG. 3  is a block diagram of an exemplary comparator architecture that may be used with an embodiment of the invention. Referring to  FIG. 3 , there is shown a comparator element  300 , which may be similar to the comparator element used in the ADC element  211 , comprising comparator  310 , coupling capacitors C 1  and C 2 , and switching elements SW 1  and SW 2 . 
         [0040]    In operation, the switching elements SW 1  and SW 2  may be closed by a command from, for example, the control logic  130  to reset inputs of the comparator  310  to a known state. The switching elements SW 1  and SW 2  may then be opened and the input signals PXL and RMP may be applied. The input signal PXL may be, for example, a voltage from a pixel, and the input signal RMP may be a downward sloping voltage signal. 
         [0041]    Generally, the input signal RMP may be at a higher initial voltage level than the input signal PXL. Accordingly, output signal Cmp_out of the comparator  310  may be deasserted. However, as the input signal RMP is decreasing in voltage, there may be a point when the level of the input signal RMP crosses the level of the input signal PXL. As the input signal RMP decreases further and the input signal RMP is less than the as the input signal PXL, the comparator may assert the output signal Cmp_out. The output signal Cmp_out may be communicated to, for example, a counter corresponding to the comparator element  300 . The counter may be, for example, part of the same ADC element  211  as the comparator element  300 . The control logic  130  may then control various signals that may be used to give a final equivalent digital value of the analog input signal. In cases where the comparator  310  has complementary outputs, there may also be an output signal Cmp_out_n that is of opposite voltage level with respect to the output signal Cmp_out. For example, when the output signal Cmp_out is at a high voltage level, the output signal Cmp_out_n is at a low voltage level, and vice versa. 
         [0042]      FIG. 4A  is a schematic of an exemplary single ended output cascoded comparator in conjunction with a cascode bias generator, in accordance with an embodiment of the invention. Referring to  FIG. 4A , there is shown an exemplary schematic for a cascoded comparator  400 , which may be used in place of the comparator  310 . 
         [0043]    The comparator  400  comprises a cascode bias generator  410 , PMOS transistors  420 ,  421 ,  422 ,  423 , and  424 , and NMOS transistors  425  and  426 . A source terminal of the PMOS transistor  420  is coupled to the voltage supply V+ and a drain terminal of the PMOS transistor  420  is coupled to source terminals of the PMOS transistors  421  and  422 . An input signal VBP may be applied to a gate terminal of the PMOS transistor  420 . The input signal VBP may be used to bias the PMOS transistor  420  so that the PMOS transistor  420  may be a current source. 
         [0044]    A drain terminal of the PMOS transistor  421  is coupled to a source terminal of the PMOS transistor  423 , and a drain terminal of the PMOS transistor  422  is couple to a source terminal of the PMOS transistor  424 . An input signal V RMP  may be applied to a gate terminal of the PMOS transistor  421 , and an input signal V PXL  may be applied to a gate terminal of the PMOS transistor  422 . The input signal V PXL  may be a pixel voltage from, for example, a pixel element  201  in the pixel array  200 . The input signal V RMP  may be a time-varying voltage that ramps from a higher voltage level to a lower voltage level. 
         [0045]    A drain terminal of the PMOS transistor  423  is coupled to a drain terminal of the NMOS transistor  425 , and a drain terminal of the PMOS transistor  424  is coupled to a drain terminal of the NMOS transistor  426 . A biasing signal VCASC may be applied to gate terminals of the PMOS transistors  423  and  424 . Accordingly, the biasing signal VCASC may provide the same biasing voltage for the cascode PMOS transistors  423  and  424 . 
         [0046]    Gate terminals of the NMOS transistors  425  and  426  may be coupled to each other and to the drain terminals of the PMOS transistor  424  and the NMOS transistor  426 . Source terminals of the NMOS transistors  425  and  426  may be coupled to ground. Accordingly, the NMOS transistor  426  may be in a diode configuration. A voltage at the node where the drain terminal of the PMOS transistor  423  is coupled to the drain terminal of the NMOS transistor  425  may be VOUT, an output signal of the comparator  400 . VOUT may correspond to Cmp_Out in  FIG. 3 . 
         [0047]    The cascode bias generator  410  may comprise suitable circuitry to generate a biasing signal VCASC. The biasing signal VCASC may track, with an offset, an input signal such as, for example, the input signal V RMP , and the biasing signal VCASC may be communicated to the cascode PMOS transistors  423  and  424 . Accordingly, since the cascode PMOS transistors  423  and  424  are biased by the same biasing voltage from the biasing signal VCASC output by the cascode bias generator  410 , the cascode PMOS transistors  423  and  424  may have similar operating characteristics regardless of the level of the input signal V RMP . 
         [0048]    In operation, the input signal VBP may be applied to the PMOS transistor  420  so that the PMOS transistor  420  may source current for the PMOS transistors  421 ,  422 ,  423 , and  424 , and the NMOS transistors  425  and  426 . If the PMOS transistors  423  and  424  are biased with a fixed gate voltage VCASC, then the VSD (source to drain voltage) for the PMOS transistors  421  and  422  may be different when the input signal V RMP  crosses the input signal V PXL  at different voltage levels of the input signal V PXL . Accordingly, the operating characteristics of the PMOS transistors  421  and  422  may vary at different voltage levels of the input signal V PXL , which may lead to inaccurate outputs by the output signal VOUT. 
         [0049]    However, various embodiments of the invention may use the input signal V RMP  as a reference, and the cascode bias generator  410  may provide some offset to the input signal V RMP  to generate the biasing signal VCASC. The biasing signal VCASC may be communicated to the gate terminals of the cascode PMOS transistors  423  and  424 . Therefore, the input signal V RMP  and biasing signal VCASC are substantially identical ramp signals that are separated by a fixed offset. Accordingly, the VSD of the comparator input pair, PMOS transistors  421  and  422 , may be constant regardless of the voltage level of the input signal RMP. Accordingly, the operating characteristics of the PMOS transistors  421  and  422  will be the same regardless of the voltage level of the input signal RMP. 
         [0050]      FIG. 4B  is a schematic of an exemplary differential output cascoded comparator, in accordance with an embodiment of the invention. Referring to  FIG. 4B , there is shown an exemplary schematic for a cascoded comparator  450 , which may be used in place of the comparator  310 . 
         [0051]    The cascoded comparator  450  may be similar to the cascoded comparator  400  except for the output section. Accordingly, the cascoded comparator  450  comprises the cascode bias generator  410 , the PMOS transistors  420 ,  421 ,  422 ,  423 , and  424 , and the NMOS transistors  425  and  426 . Additionally, the cascoded comparator  450  comprises NMOS transistors  427  and  428 . 
         [0052]    A source terminal of the PMOS transistor  420  is coupled to the voltage supply V+ and a drain terminal of the PMOS transistor  420  is coupled to source terminals of the PMOS transistors  421  and  422 . An input signal VBP may be applied to a gate terminal of the PMOS transistor  420 . The input signal VBP may be used to bias the PMOS transistor  420  so that the PMOS transistor  420  may be a current source. 
         [0053]    A drain terminal of the PMOS transistor  421  is coupled to a source terminal of the PMOS transistor  423 , and a drain terminal of the PMOS transistor  422  is couple to a source terminal of the PMOS transistor  424 . An input signal V RMP  may be applied to a gate terminal of the PMOS transistor  421 , and an input signal V PXL  may be applied to a gate terminal of the PMOS transistor  422 . The input signal V PXL  may be a pixel voltage from, for example, a pixel element  201  in the pixel array  200 . The input signal V RMP  may be a time-varying voltage that ramps from a higher voltage level to a lower voltage level. 
         [0054]    A drain terminal of the PMOS transistor  423  is coupled to a drain terminal of the NMOS transistor  425 , a gate terminal of the NMOS transistor  425 , a drain terminal of the NMOS transistor  427 , and a gate terminal of the NMOS transistor  428 . A drain terminal of the PMOS transistor  424  is coupled to a drain terminal of the NMOS transistor  426 , a gate terminal of the NMOS transistor  426 , a drain terminal of the NMOS transistor  428 , and a gate terminal of the NMOS transistor  427 . Source terminals of the NMOS transistors  425 ,  426 ,  427 , and  428  may be coupled to ground. Accordingly, the NMOS transistors  425  and  426  may be in a diode configuration. 
         [0055]    A biasing signal VCASC may be applied to gate terminals of the PMOS transistors  423  and  424 . Accordingly, the biasing signal VCASC may provide the same biasing voltage for the cascode PMOS transistors  423  and  424 . A voltage at the drain terminal of the NMOS transistor  425  may be VOUT+, an output signal of the comparator  400 . A voltage at the drain terminal of the NMOS transistor  426  may be VOUT−, an output signal of the comparator  400 . VOUT+ and VOUT− may correspond to Cmp_Out and Cmp_Out_n in  FIG. 3 . 
         [0056]    The cascode bias generator  410  may comprise suitable circuitry to generate a biasing signal VCASC. The biasing signal VCASC may track, with an offset, an input signal such as, for example, the input signal V RMP , and the biasing signal VCASC may be communicated to the cascode PMOS transistors  423  and  424 . Accordingly, since the cascode PMOS transistors  423  and  424  are biased by the same biasing voltage from the biasing signal VCASC output by the cascode bias generator  410 , the cascode PMOS transistors  423  and  424  may have similar operating characteristics regardless of the level of the input signal V RMP . 
         [0057]    In operation, the input signal VBP may be applied to the PMOS transistor  420  so that the PMOS transistor  420  may source current for the PMOS transistors  421 ,  422 ,  423 , and  424 , and the NMOS transistors  425 ,  426 ,  427 , and  428 . If the PMOS transistors  423  and  424  are biased with a fixed gate voltage VCASC, then the VSD (source to drain voltage) for the PMOS transistors  421  and  422  may be different when the input signal V RMP  crosses the input signal V PXL  at different voltage levels of the input signal V PXL . Accordingly, the operating characteristics of the PMOS transistors  421  and  422  may vary at different voltage levels of the input signal V PXL , which may lead to inaccurate outputs by the output signals VOUT+ and VOUT−. 
         [0058]    However, various embodiments of the invention may use the input signal V RMP  as a reference, and the cascode bias generator  410  may provide some offset to the input signal V RMP  to generate the biasing signal VCASC. The biasing signal VCASC may be communicated to the gate terminals of the cascode PMOS transistors  423  and  424 . Therefore, the input signal V RMP  and biasing signal VCASC are substantially identical ramp signals that are separated by a fixed offset. Accordingly, the VSD of the comparator input pair, PMOS transistors  421  and  422 , may be constant regardless of the voltage level of the input signal RMP. Accordingly, the operating characteristics of the PMOS transistors  421  and  422  will be the same regardless of the voltage level of the input signal RMP. 
         [0059]      FIG. 5  is a schematic of an exemplary dynamic biasing circuitry, in accordance with an embodiment of the invention. Referring to  FIG. 5 , there is shown an exemplary schematic for a cascode bias generator  500  that may be similar to, for example, the cascode bias generator  410 . 
         [0060]    The cascode bias generator  500  comprises PMOS transistors  510 ,  511 , and  512 , and NMOS transistors  513  and  514 . A source terminal of the PMOS transistor  510  is coupled to a voltage supply V+, and a drain terminal of the PMOS transistor  510  is coupled to source terminals of the PMOS transistors  511  and  512 . A voltage at this node where the PMOS transistors  510 ,  511 , and  512  are coupled to each other may be referred to as a common voltage VC. An input signal VBP may be applied to a gate terminal of the PMOS transistor  510 . The input signal VBP may be, for example, the same input signal VBP used to bias the PMOS transistor  420 , and may also be used to bias the PMOS transistor  510  so that the PMOS transistor  510  may be a current source. 
         [0061]    A drain terminal of the PMOS transistor  511  is coupled to a gate terminal of the PMOS transistor  511  and also to a drain terminal of the NMOS transistor  513 . Accordingly, the PMOS transistor  511  may be configured as a diode. Voltage at the node where the drain terminal of the PMOS transistor  511  is coupled to the drain terminal of the NMOS transistor  513  may be the biasing signal VCASC, an output signal of the cascode bias generator  500 . 
         [0062]    A drain terminal of the PMOS transistor  512  is coupled to a drain terminal of the NMOS transistor  514  and to a gate terminal of the NMOS transistor  514 . Accordingly, the NMOS transistor  514  may be configured as a diode. An input signal RMP may be supplied to a gate terminal of the PMOS transistor  512 . Source terminals of the NMOS transistors  513  and  514  is coupled to ground. An input signal VBN may be supplied to a gate terminal of the NMOS transistor  513 . The input signal VBN may be a biasing signal so that the NMOS transistor  513  may be a current sink. 
         [0063]    In operation, the PMOS transistor  510  and the NMOS transistor  513  may be biased by the biasing signals VBP and VBN, respectively. The input signal RMP may be the same input signal RMP that is applied to the comparator  400  is applied. As the input signal RMP changes, the common voltage VC tracks voltage of the input signal RMP with an offset of VGS_ 512 , which is a gate to source voltage for the PMOS transistor  512 . 
         [0064]    Since the common voltage VC is also applied to the source terminal of the PMOS transistor  511 , voltage of the biasing signal VCASC also tracks voltage of the input signal RMP with an offset of VGS_ 512 −VGS_ 511 , where VGS_ 511  is a gate to source voltage for the PMOS transistor  511 . By adjusting a width to length (W/L) ratio of the PMOS transistor  511  so that VGS_ 511 &gt;VGS_ 512 , the voltage level of the biasing signal VCASC can be lower than the voltage level of the input signal RMP by a desired voltage. The desired voltage may be a voltage determined to properly bias, for example, the cascode PMOS transistors  423  and  424  in the comparator  400 . 
         [0065]    Since the PMOS transistor  510  supplies a fixed current I, if the NMOS transistor  513  sinks a fixed current I/2 then the remaining current I/2 from the PMOS transistor  510  must flow through the PMOS transistor  512  and the NMOS transistor  514 . As the input signal RMP changes, the diode connection of the NMOS transistor  514  may allow some dynamic current to be steered to/from the PMOS transistor  511  to charge/discharge the output node where the biasing signal VCASC is present. However, as described earlier, the current relationship between the various transistors ensures that the biasing signal VCASC will always track the input signal RMP. 
         [0066]    Although some embodiments of the invention have been described, the invention is not so limited. For example, while specific transistors may have been described as being NMOS transistors and others as being PMOS transistors, these specific transistors may be changed to different types to perform the desired functions of various embodiments of the invention. Additionally, various other circuitry may be designed as various embodiments of the invention. 
         [0067]    While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.