Abstract:
A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

Description:
REFERENCE TO PRIORITY APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 10-2008-0062866, filed Jun. 30, 2008, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated herein by reference. 
       BACKGROUND 
       [0002]    As a feature size of a control gate of flash memories decreases due to high integration of flash memories, a resistance of the control gate increases and thus problems, such as an RC delay and a voltage drop may occur. To address these problems, a metal layer is formed on a polysilicon layer and thermally treated to form a metal silicide layer. Thus, a control gate having a structure in which a metal silicide layer and a polysilicon layer are stacked has been introduced. 
         [0003]    To obtain a resistance required for a control gate when a design rule is less than or equal to 50 nm, a thick metal silicide layer of 500Å or greater needs to be formed. However, as a silicidation reaction occurs for a narrow line width, voids are formed within the control gate or the profile of silicide deteriorates. 
       SUMMARY 
       [0004]    The inventive concept provides a method of manufacturing a semiconductor device, by which an interlayer dielectric layer can be formed within a narrow space between stacked gate structures, without generating voids within the interlayer dielectric layer, thus contributing to uniform recessing of the interlayer dielectric layer and formation of a metal silicide layer with a uniform shape, and by which formation of the metal silicide layer within an undesired region of an active region of a semiconductor substrate due to pitting generated in the semiconductor substrate can be prevented. 
         [0005]    According to an aspect of the inventive concept, there is provided a method of forming a gate electrode of a semiconductor device, the method comprising: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a hard mask layer, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the hard mask layer is exposed; selectively removing the hard mask layer of which the top surface is exposed in the first interlayer dielectric layer; and forming a third silicon layer for control gates in an area from which the hard mask layer was removed to form a silicon layer for control gates which comprises the third silicon layer and the second silicon layer. 
         [0006]    The method may further include: recessing the first interlayer dielectric layer so that an tipper portion of the silicon layer protrudes over the first interlayer dielectric layer; and forming a metal silicide layer for the upper portion of the silicon layer. Alternatively, the method may further include: sequentially forming a first dielectric layer, a first silicon layer, a second dielectric layer, a second silicon layer, and a mask layer on the semiconductor substrate in the stated order; forming the mask pattern by patterning the mask layer; and etching the first dielectric layer, the first silicon layer, the second dielectric layer, and the second silicon layer by using the mask pattern as an etch mask, so as to form the tunnel dielectric layer, the first silicon layer, the intergate dielectric layer, and the second silicon layer. The first dielectric layer may include a silicon oxide layer, the second dielectric layer may include an oxide-nitride-oxide (ONO) layer, and the mask layer may include a silicon nitride layer. 
         [0007]    The forming of the first interlayer dielectric layer may include: depositing a dielectric material for the first interlayer dielectric layer in spaces between the plurality of stacked structures so as to fill the spaces between the plurality of stacked structures: and performing chemical mechanical polishing (CMP) on the deposited dielectric material for the first interlayer dielectric layer by using the mask pattern as an CMP stop layer. 
         [0008]    The first interlayer dielectric layer may include a Medium Temperature Oxide (MTO) layer or a Tetra-Ethyl-Ortho-Silicate (TEOS) oxide layer. 
         [0009]    The mask pattern may be selectively removed using a wet etching technique using phosphoric acid. 
         [0010]    The forming of the third silicon layer in the area from which the mask pattern was removed may include: forming polysilicon on the semiconductor substrate so as to fill the area from which the mask pattern was removed; and performing CMP on the polysilicon so that the first interlayer dielectric layer is exposed. Alternatively, the forming of the third silicon layer in the area from which the mask pattern was removed may include: growing epitaxial silicon on the second silicon layer by selective epitaxial growth (SEG); and performing CMP on the grown epitaxial silicon so that the first interlayer dielectric layer is exposed. 
         [0011]    The forming of the metal silicide layer may include: forming a metal layer on the semiconductor substrate from which the silicon layer protrudes over the first interlayer dielectric layer; thermally treating the semiconductor substrate on which the metal layer has been formed; and removing a portion of the metal layer that does not react to the thermal treatment and remains without turning into the metal silicide layer. The metal layer may include at least one metal selected from the group consisting of Co, Ni, Ti, Hf, NiTa, and NiPt. 
         [0012]    According to another aspect of the inventive concept, there is provided a method of forming a gate electrode of a semiconductor device, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a silicon layer for floating gates, an intergate dielectric layer, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a silicon layer for control gates in an area from which the mask pattern was removed; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the first interlayer dielectric layer; and forming a metal silicide layer for the upper portion of the silicon layer. 
         [0013]    The forming of the plurality of stacked structures may include: sequentially forming a first dielectric layer, a first silicon layer, a second dielectric layer, and a mask layer; forming the mask pattern by patterning the mask layer; and etching the first dielectric layer, the first silicon layer, and the second dielectric layer by using the mask pattern as an etch mask, so as to form the tunnel dielectric layer, the silicon layer, and the intergate dielectric layer. 
         [0014]    The first dielectric layer may include a silicon oxide layer, the second dielectric layer comprises an ONO layer, and the mask layer comprises a silicon nitride layer. 
         [0015]    The forming of the silicon layer in the area from which the mask pattern was removed may include: forming polysilicon on the semiconductor substrate so as to fill the area from which the hard disk layer was removed; and performing CMP on the polysilicon so that the first interlayer dielectric layer is exposed. 
         [0016]    The forming of the metal silicide layer on the silicon layer may include: forming a metal layer on the semiconductor substrate from which the silicon layer protrudes over the first interlayer dielectric layer; thermally treating the semiconductor substrate on which the metal layer has been formed; and removing a portion of the metal layer that does not react to the thermal treatment and remains without turning into the metal silicide layer. 
         [0017]    The metal layer may include at least one metal selected from the group consisting of Co, Ni, Ti, Hf, NiTa, and NiPt. 
         [0018]    The forming of the metal silicide layer may include: forming a metal layer on the semiconductor substrate from which the silicon layer protrudes over the first interlayer dielectric layer; thermally treating the semiconductor substrate on which the metal layer has been formed; and removing a portion of the metal layer that does not react to the thermal treatment and remains without turning into the metal silicide layer. Alternatively, the forming of the metal silicide layer may include turning the entire silicon layer into the metal silicide layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0020]      FIGS. 1A through 1H  are cross-sectional views illustrating a method of forming a control gate of a flash memory, according to an embodiment of the inventive concept; and 
           [0021]      FIGS. 2A through 2E  are cross-sectional views illustrating a method of forming a control gate of a flash memory, according to another embodiment of the inventive concept. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0022]    The inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to one skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted. 
         [0023]      FIGS. 1A through 1H  are cross-sectional views illustrating a method of forming a control gate of a flash memory, according to an embodiment of the inventive concept. 
         [0024]    Referring to  FIG. 1A , a tunnel dielectric layer  111 , a first silicon layer  113  for floating gates, an intergate dielectric layer  115 , a second silicon layer  117   a  for control gates, and a hard mask layer  119  are sequentially formed on a semiconductor substrate  100  in the order stated. The tunnel dielectric layer  111  may be formed of a silicon oxide layer by thermal oxidation or chemical vapor deposition (CVD), or formed of a material having a low dielectric constant. The intergate dielectric layer  115  may be an oxide-nitride-oxide (ONO) layer, which is a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The first silicon layer  113  and the second silicon layer  117   a  may be formed of polysilicon. The second silicon layer  117   a  is formed to be lower in height than a control gate that is to be finally formed. The hard mask layer  119  may be formed of a material having etching selectivity to silicon or a silicon oxide layer, for example, may be formed of silicon nitride. The hard mask layer  119  may be formed to have a height corresponding to a result obtained by subtracting the height of the second silicon layer  117   a  from that of the final control gate. For example, if the height of the final control gate is 1500Å the second silicon layer  117   a  may be formed to have a height of 500Å and the hard mask layer  119  may be formed to have a height of 1000Å. Accordingly, a sum of the heights of the second silicon layer  117   a  and the hard mask layer  119  is equal to the height of the final control gate. 
         [0025]    Referring to  FIG. 1B , the tunnel dielectric layer  111 , the first silicon layer  113 , the intergate dielectric layer  115 , the second silicon layer  117   a,  and the hard mask layer  119  are patterned to form stacked gate structures  110 . At this time, the hard mask layer  119  may be first patterned, and then the remaining stacked layers below the hard mask layer  119  may be etched using the patterned hard mask layer  119  as an etch mask. The hard mask layer  119  may also serve as a sacrificial pattern for forming a third silicon layer  117   b  for control gates (see  FIG. 1E ), after serving as the etch mask to form the stacked gate structures  110 . 
         [0026]    Referring to  FIG. 1C , a first interlayer dielectric layer  120  is formed between the stacked gate structures  110 . The first interlayer dielectric layer  120  may be formed by depositing a material for the first interlayer dielectric layer  120  on the semiconductor substrate  100  on which the stacked gate structures  110  have been formed and performing chemical mechanical polishing (CMP) on the material for the first interlayer dielectric layer  120  by using the hard mask layer  119  as an CMP stop layer. According to the CMP, the hard mask layer  119  is exposed on the top surface of the first interlayer dielectric layer  120 . The material for the first interlayer dielectric layer  120  may be silicon oxide including Medium Temperature Oxide (MTO) or Tetra-Ethyl-Ortho-Silicate (TEOS). 
         [0027]    In the present embodiment, since the sum of the heights of the second silicon layer  117   a  and the hard mask layer  119  is equal to the height of the final control gate, the height of the stacked gate structures  110  is decreased, and thus an aspect ratio between stacked gate structures  110  is lowered. Therefore, when the material for the first interlayer dielectric layer  120  is deposited between the stacked gate structures  110 , overhangs are not generated, and thus voids are not formed within the first interlayer dielectric layer  120 . 
         [0028]    Referring to  FIG. 1D , the hard mask layer  119  exposed on the top surface of the first interlayer dielectric layer  120  is removed. The hard mask layer  119  may be selectively removed according to a wet etching method using phosphoric acid. When the hard mask layer  119  is removed, trenches  125  are formed in the first interlayer dielectric layer  120 , and the top surface of the second silicon layer  117   a  is exposed through the trenches  125 . 
         [0029]    Referring to  FIG. 1E , the trenches  125  are filled to form the third silicon layer  117   b,  thereby forming a silicon layer  117 . The third silicon layer  117   b  may be formed by depositing polysilicon on the entire surface of the semiconductor substrate  100  and then performing CMP on the polysilicon by using the first interlayer dielectric layer  120  as an etch-stop layer. Alternatively, the silicon layer  117  may be formed by selectively growing epitaxial silicon in the trenches  125  according to a Selective Epitaxial Growth (SEG) technique and then performing CMP on the grown epitaxial silicon by using the first interlayer dielectric layer  120  as the etch-stop layer. 
         [0030]    Referring to  FIG. 1F , the first interlayer dielectric layer  120  is recessed to expose parts of the side surfaces of the silicon layer  117 . The first interlayer dielectric layer  120  may be recessed by etchback. In the present embodiment, parts of the side surfaces of the silicon layer  117  for control gates are exposed; however, the inventive concept is not limited thereto, and thus, in another embodiment, the entire side surfaces of the silicon layer  117  may be exposed. 
         [0031]    Referring to  FIG. 1G , a metal layer  132  is formed on the entire surface of the semiconductor substrate  100  on which parts of the side surfaces of the silicon layer  117  are exposed. The metal layer  132  may be formed of a material such as Co, Ni, Ti, Hf, NiTa, or NiPt, or a mixture of two or more of the foregoing materials. The metal layer  132  may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). 
         [0032]    Referring to  FIG. 1H , the semiconductor substrate  100  on which the metal layer  132  has been formed is thermally treated to form a metal silicide layer  134  on the silicon layer  117 . The metal silicide layer  134  may be formed according to a two-stage thermal treatment process, or a thermal treatment process having three or more stages. Remaining portions of the metal layer  132  that do not react with the silicon layer  117  during the silicidation reaction are removed. Since the metal layer  132  contacts the top surfaces and the parts of the side surfaces of the silicon layer  117 , the metal silicide layer  134  may be evenly formed on the silicon layer  117 . In the present embodiment illustrated in  FIG. 1H , only a part of the silicon layer  117  reacts with the metal layer  132  to form the metal silicide layer  134 , and the remaining portion of the silicon layer  117  does not undergo a silicidation reaction and thus remains as the silicon layer  117 . Accordingly, in the present embodiment, a control gate is a stack of the remaining portion of the silicon layer  117  and the metal silicide layer  134 ; however, the inventive concept is not limited thereto, and thus, in another embodiment, the entire silicon layer  117  may undergo a silicidation reaction with the metal layer  132 , and thus the control gate may be made up of only the metal silicide layer  134 . In another embodiment, to prevent oxidation of the metal layer  132 , a capping layer (not shown), for example, a TiN capping layer, may be further formed on the metal layer  132  to prevent oxidation, and cause a silicidation reaction so as to form the metal silicide layer  134 . The capping layer may be removed together with the metal layer  132  when the metal layer  132  is removed. 
         [0033]    Thereafter, although not shown in the drawings, a second interlayer dielectric layer is formed on the semiconductor substrate  100  on which the metal silicide layer  134  has been formed, and metal wires are formed, thereby completing the manufacture of the flash memory. 
         [0034]      FIGS. 2A through 2E  are cross-sectional views illustrating a method of forming a control gate of a flash memory, according to another embodiment of the inventive concept. 
         [0035]    The present embodiment illustrated in  FIGS. 2A through 2E  is different from the one illustrated in  FIGS. 1A through 1H  in that a hard mask layer  119  is directly formed on the intergate dielectric layer  115 , as opposed to forming the second silicon layer  117   a  on the integrate dielectric layer  115 . Like reference numerals in  FIGS. 2A through 2E  and  FIGS. 1A through 1H  denote like elements, and thus their description will be omitted. 
         [0036]    Referring to  FIG. 2A , the tunnel dielectric layer  111 , the first silicon layer  113 , the intergate dielectric layer  115 , and the hard mask layer  119  are sequentially formed on the semiconductor substrate  100  in the order stated. The tunnel dielectric layer  111  may be formed of silicon oxide by thermal treatment or CVD, or formed of a material having a low dielectric constant. The intergate dielectric layer  115  may be an ONO layer, which is a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The first silicon layer  113  may be formed of polysilicon. The hard mask layer  119  may be formed of a material having etching selectivity to silicon or a silicon oxide layer, for example, silicon nitride. The hard mask layer  119  may be formed to have a height equal to the height of a control gate. 
         [0037]    Referring to  FIG. 2B , the tunnel dielectric layer  111 , the first silicon layer  113 , the intergate dielectric layer  115 , and the hard mask layer  119  are patterned to form stacked gate structures  210 . At this time, the hard mask layer  119  may be first patterned, and then the remaining stacked layers below the hard mask layer  119  may be etched using the patterned hard mask layer  119  as an etch mask. The hard mask layer  119  may also serve as a sacrificial pattern when forming the control gates, after serving as the etch mask to form the stacked gate structures  210 . 
         [0038]    Similar to  FIG. 1C , referring to  FIG. 2C , the first interlayer dielectric layer  120  is formed between stacked gate structures  210 . In the present embodiment, since the second silicon layer  117   a  is not formed, the heights of the stacked gate structures  210  are decreased as compared to those of the stacked gate structures  110 , and thus the depths of spaces between stacked gate structures  210  are also decreased as compared to those between the stacked gate structures  110 . Therefore, when the first interlayer dielectric layer  120  is formed between the stacked gate structures  210 , overhangs are not generated, and thus voids are not formed within the first interlayer dielectric layer  120 . 
         [0039]    Referring to  FIG. 2D , the hard mask layer  119  exposed on the top surface of the first interlayer dielectric layer  120  is removed. The hard mask layer  119  may be selectively removed according to a wet etching method using phosphoric acid. When the hard mask layer  119  is removed, trenches  125  are formed in the first interlayer dielectric layer  120 , and the top surface of the intergate dielectric layer  115  is exposed through the trenches  125 . 
         [0040]    Referring to  FIG. 2E , the silicon layer  117  is formed in the trenches  125 . The silicon layer  117  may be formed by depositing polysilicon on the entire surface of the semiconductor substrate  100  and then performing CMP on the deposited polysilicon by using the first interlayer dielectric layer  120  as an etch-stop layer. 
         [0041]    A subsequent operation of forming a metal silicide layer of a control gate is the same as described for  FIGS. 1F through 1H . 
         [0042]    In the above-described embodiments of the inventive concept, it will be understood that the first silicon layer  113 , the second silicon layer  117   a,  the third silicon layer  117   b,  and the silicon layer  117  are all conductive silicon layers. 
         [0043]    In the above-described embodiments of the inventive concept, a method of forming a control gate of a floating gate type flash memory has been illustrated. However, the inventive concept may be applied to a method of forming a control gate of a charge trap type flash memory and further to a method of forming an upper gate electrode of a stacked gate structure. 
         [0044]    While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.