Abstract:
A spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output regularly or irregularly within limits. The clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. Since phase shifting is performed open-loop, total phase shift is defined by design.

Description:
BACKGROUND 
       [0001]    It is well known that digital systems tend to generate radio frequency noise at harmonics of the clock frequencies of logic within the system, this is a result of switching transients throughout the system. In systems with fixed clock frequencies, this noise can be significant enough at particular frequencies to cause problems with other electronic devices, including radios and similar high-gain systems; in some systems this noise may result in sufficient electromagnetic radiation to cause issues with regulatory agencies. 
         [0002]    A technique that has been used to reduce noise at particular peak frequencies is to modulate the clock frequency, “spreading” the clock frequency into a band. Spreading the clock frequency also spreads spectrum of the radiated harmonics from switching transients in the system, with result that intensity at nominal harmonic frequencies is reduced at the expense of increased noise at nearby frequencies. Clock generators that provide a frequency spreading function are referred to herein as spread-spectrum clock generators. 
         [0003]    Some prior clock-frequency-spreading systems use a phase-locked loop to dither phase, and hence frequency, by shifting phase between the voltage-controlled oscillator (VCO) of the phase locked loop and the phase detector of the phase locked loop; U.S. Pat. No. 8,593,228 FIG. 8 discloses a system of this type. Accumulated phase shift at the phase detector causes a modulation on the VCO control voltage, modulating VCO output frequency periodically and slowly. 
         [0004]    Some integrated circuits are mixed-signal integrated circuits that rely on sampling of analog signals at precise times, or on transitioning signals into analog circuitry at precise times. Clock jitter, such as would result if a VCO of a PLL clock generator driving an analog clock were to vary in frequency, could result in an undesirable noise-equivalent in sampled-data circuitry; for example clock jitter in a delta-sigma digital-to-analog converter (DAC) could cause noise on the DAC output. In typical mixed-signal integrated circuits, digital switching noise is a much stronger contributor to electromagnetic interference than is analog switching noise. 
       SUMMARY 
       [0005]    In an embodiment, a spread-spectrum clock generator has a phase-locked loop locked to a reference signal that gives a stable-frequency output to a variable phase shifter. The variable phase shifter provides a spread-spectrum clock output because its phase-shift is determined by a pseudorandom sequence generator and the pseudorandom sequence generator changes its output within limits. In particular embodiments, frequency changes regularly, and in other embodiments frequency changes irregularly 
         [0006]    In another embodiment, the clock generator performs a method of generating a spread-spectrum clock including locking the phase-locked loop to the reference signal, and phase shifting the stable frequency signal by a phase-shift determined by the pseudorandom sequence generator, and changing the phase-shift determined by the pseudorandom sequence generator. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0007]      FIG. 1  is a block diagram of a clock generator providing frequency-spreading on digital clocks, while providing optional analog clocks at fixed frequency. 
           [0008]      FIG. 2  illustrates an embodiment of an exemplary portion of phase-shifting variable-delay delay line  110  of  FIG. 1 . 
           [0009]      FIG. 3  illustrates an alternative embodiment of an exemplary portion of phase-shifting variable-delay delay line  110  of  FIG. 1 . 
           [0010]      FIG. 4  illustrates an alternative embodiment of the clock generator using a delay line and multiplexor as a variable phase delay. 
           [0011]      FIG. 5  illustrates a block diagram of a random sequence generator for use in the embodiments of  FIGS. 1 and 4 . 
           [0012]      FIG. 6  is a flowchart of operation of the random sequence generator of  FIG. 5 . 
           [0013]      FIG. 7  is a waveform diagram illustrating waveforms of the clock generator of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0014]    A clock generator  100  is illustrated in  FIG. 1 . The clock generator receives a reference signal  102 , and a phase-locked loop, PLL  104 , is configured to be locked to the reference signal. In typical embodiments, the phase-locked loop  104  has a reference divider, phase detector and filter, voltage-controlled oscillator, and feedback divider as known in the art of phase-locked loop clock generator circuits. In this system, phase-locked loop  104  is not dithered to spread noise frequencies, so phase-locked loop output  106  is referred to herein as a stable-frequency output even though it may track changes in the reference signal  102 . Phase-locked loop output  106  drives an optional analog-clock divider  108 . Phase-locked loop output  106  also drives a frequency-spreading system  109 , within which it drives phase-shifting variable-delay delay line  110  of a variable phase-shifter  112 , with a controlling decoder  114  controlled by a random sequence generator  116  adapted to vary phase-shifting variable-delay delay line  110 . Phase-shifting variable-delay line  110  imposes a variable phase shift on its output  121 , a phase shift that changes with delay of phase-shifting variable-delay delay line  110 . 
         [0015]    Output  121  from phase-shifting variable-delay delay line  110  may be buffered by a clock driver and used as digital clocks to portions of the system (including random sequence generator  116 ). In some embodiments, output  121  is divided by an optional digital clock divider  120  to produce multiple clock phases or lower frequency clocks  122  to drive other portions of the system. 
         [0016]    An embodiment of phase-shifting variable-delay delay line  110 , as shown in  FIG. 2  may include stages  150 ,  162  each stage including one or more inverters  152 ,  154  with a capacitive load  156 , the capacitive load switchable through a transmission gate  158  and associated logic  160  ( FIG. 2 ). Each stage serves to provide an output that is delayed slightly from its input. In an embodiment each stage is non-inverting, and in an alternative embodiment each stage is inverting; delay from input to output of each stage is determined not by clock signals, but by analog factors such as the “R-C” circuit delay contributed by on-resistance of transistors and circuit capacitance. In order to better vary delay, and hence assist in scattering frequencies, the phase-shifting variable-delay delay line may have different switchable capacitive loads in each stage, hence capacitive load  156  of stage  150  may differ from load  164  of stage  162 . The number of stages  150 ,  162  in phase-shifting variable-delay delay line  110  may vary without departing from the scope hereof. 
         [0017]    In certain alternative embodiments, the variable-delay stages  202  ( FIG. 3 ) of the phase-shifting variable-delay delay line  110  may rely on gate delays as illustrated in  FIG. 3 , without a switchable capacitive load. In the variable-delay delay-line stage  202  of  FIG. 3 , a multiplexor formed of transistors  204 ,  206 ,  208 ,  210  and inverter  212  selects an input to output inverter  214  from a signal that has been delayed by an even number of inverters  216 ,  218 , or an undelayed signal  220 . Stage  202  may be inverting, in which case undelayed signal  220  is input to the stage, or may be noninverting with a buffer inverter  222 . 
         [0018]    An alternative embodiment  250  ( FIG. 4 ), which requires some care in design so that change of delay triggered by the random sequence generator  252  does not cause clock glitches, substitutes a multiplexor  254  and a non-variable, but multiply-tapped, multi-inverter delay line  256  in variable phase shifter  258  of the frequency-spreading system  259 . 
         [0019]    Output  221  from multiplexor  254  may be buffered by a clock driver and used as digital clocks to portions of the system (including random sequence generator  252 ), in some embodiments be divided by an optional clock divider  260  to produce multiple clock phases or lower frequency clocks  261  to drive other portions of the system. 
         [0020]    In some embodiments, which may include the embodiments of  FIGS. 1 and 4 , the random sequence generator  300 ,  252  and  116  (from  FIGS. 5, 4 and 1  respectively) has structure and operation as illustrated in  FIGS. 5 and 6 . A random number generator  302  generates  352  a pseudorandom number, this random number generator is advanced to a new value every N clock cycles, the random number with a predetermined range representing a range of permissible phase offsets. In most embodiments, N is a known fixed integer number greater than or equal to one, in a particular embodiment N is two. A subtractor  304  compares  354  the random number to a prior random sequence generator  116  and  252  (from  FIGS. 4 and 1  respectively) output as held in a register  306  to determine an intermediate value  307  corresponding to how far the random number has moved from the prior sequence generator output, and in which direction. A magnitude comparator  308  compares the intermediate value to a phase-change limit constant  310  to determine  356  if the intermediate value is below minus the phase-change limit constant  310 , between minus the phase-change limit constant  310  and the phase-change limit constant  310 , or above phase-change limit constant  310 , simultaneously a limit-up value and a limit-down value are determined  358  by adding (in adder  312 ) and subtracting (in subtractor  314 ) phase-change limit constant  310  to the prior sequence generator output in register  306 . Next, a multiplexor  320  selects  360  from the limit up value, the limit down value, or the random number, according to magnitude comparator  308  results, to provide a change-limited value in the range from the limit-down value to the limit-up value to register  306 , where it becomes  362  random sequence generator  252  and  116  (from  FIGS. 4 and 1  respectively), output as register  306  updates at the next clock. In an embodiment, the multiplexor is configured to select the limit down value if the random number generator output is smaller than or equal to the prior sequence generator output minus the limit constant, the multiplexor  320  is configured to select the limit up value if the random number generator output is greater than or equal to the prior sequence generator output plus the limit constant, and the random number generator output in all other conditions. This output is latched in the register  306 . To ensure the sequence generator provides glitch-free, clocked-synchronized, change-limited output  322  to the variable phase-shifter  112  and  258  (from  FIGS. 1 and 4  respectively), output  322  is taken from register  306 . 
         [0021]    In some embodiments, including those where the random number generator  302  is not updated every clock cycle, we permit a phase change of up to the limit indicated by the phase-change limit constant  310  in the first clock cycle after each update of random number generator  302 , with any remaining phase change indicated by the random number implemented in one or more subsequent clock cycles. This can be done by determining a residue, or remaining phase change, limiting the residue, and applying the residue in one or more intermediate subsequent clock cycles. This can also be done simply, by updating register  306  again in intermediate subsequent clock cycles, which has the effect of repeating  364  the steps of determining  354  intermediate value, determining  356  if intermediate value is between plus and minus the limit, determining limit-up and limit-down values  358 , selecting  360  the limit-down value, the random number, or the limit-up value, and updating  362  delay value register. After intermediate subsequent clock cycles where residue is applied, a later subsequent clock cycle updates random number generator  302  output and limited phase changes are applied. In the embodiment of  FIG. 5 , this is implemented by providing a frequency divider  326  that divides a raw clock  324  and uses divided clock to update random number generator  302 , while updating register  306  each cycle. In alternative embodiments, other fixed division ratios may be used, in one such embodiment, random number generator  302  updates every six cycles of raw clock  324 , and register  306  updates every two cycles, with three updates of register  306  for each update of random number generator  302 ; in this embodiment, after random number generator  302  updates, register  306  is updated three successive times with a delay value that does not change by more than the limit constant  310  in each update. In an alternative embodiment, we permit a phase change of up to the limit indicated by the phase-change limit constant  310  in the first clock cycle after each update of random number generator  302 , with any remaining phase change indicated by the random number implemented in one or more subsequent clock cycles, until all phase change indicated by the random number is implemented, whereupon the random number is updated in a following clock cycle; this has the effect of somewhat randomizing updates of the random number generator and varying N, the division ratio between clock and the random number generator. 
         [0022]    In another alternative embodiment, particularly useful for systems with low clock-jitter tolerance, limit constant  310  is set to one, limiting changes to phase shifter  322  to be one step at a time, a minimum phase shift at each cycle. To implement this, random number generator  302  will holds output until register  306 , which decreases or increases its value one step at a time, reaches that number. Then random number generator  302  will advance its output. In this particular embodiment, the update period (N) of random number generator  352  depends on the random number it generated. In a particular embodiment of this minimum-phase-shift embodiment, register  306  is implemented with a parallel-loadable up-down counter with the adder  312  and subtractor  314  replaced by the increment and decrement carry chain of the counter. 
         [0023]    Operation of the spread-spectrum clock generator is illustrated in  FIG. 7 , with reference to  FIGS. 1 and 4 . Phase-locked loop output  106  is a stable-frequency waveform, in a particular embodiment a square wave  402 . Variable phase shifter  258 ,  112 , output  404 , corresponding to the delay line output or multiplexor output, betrays some unsteadiness or phase jitter as changes to the random sequence generator output  406  propagate to variable phase shifter output  404 . For example, when random sequence generator output  406  transitions from a first value  408  to a second value  412  and this transition propagates to phase shifter output  404 , a phase shift from a first phase  410  to a second phase  414  can be seen. Similarly when random sequence generator output  406  transitions from second value  412  to a third value  416  and this transition propagates to phase shifter output  404 , a phase shift from second phase  414  to a third phase  418  is seen. 
         [0024]    With reference to  FIGS. 1, 4 and 5 , the spread clock spectrum produced by a system incorporating embodiments depends on the unitary increment of phase shift available at the variable phase shifter  112 ,  258 , the maximum phase change limit constant  310 , the range of random numbers generated by random number generator  302 , whether N is fixed or variable, and if fixed the value of N, and the fundamental frequency of phase locked loop output  106 , as well as other factors. In some particular embodiments, one or more of these factors is configurable within a range at run time, and in other embodiments one or more of these factors is determined by design. 
       Combinations 
       [0025]    A spread-spectrum clock generator system according to the principles described herein may be assembled with a variety of combinations of components. For example, the system may use either (the delay line of  FIG. 2 , of  FIG. 3 , or another configurable-delay delay line in an embodiment resembling  FIG. 1 ), or the delay-line and multiplexor of  FIG. 4 , with the computational circuitry of  FIG. 5 . In alternative embodiments, the limit computations discussed with reference to  FIG. 5  are performed in alternative ways; we note that these computations can be performed in two&#39;s complement signed arithmetic, or in other number systems. Specific combinations anticipated include            
         [0026]    A spread-spectrum clock generator designated A including a phase-locked loop adapted to lock to a reference signal and providing a stable-frequency output to a variable phase shifter, the variable phase shifter providing a spread-spectrum clock output; and a pseudorandom sequence generator having an output configured to control phase shift of the variable phase shifter, the pseudorandom sequence generator configured to change its output. 
         [0027]    A spread spectrum clock generator designated AA including the spread spectrum clock generator designated A wherein the pseudorandom sequence generator further includes a random number generator having an output, circuitry adapted to determine a difference between the random number generator output and a prior output of the pseudorandom sequence generator, circuitry adapted to determine if the difference between the random number generator output and the prior output of the pseudorandom sequence generator exceeds a limit, and circuitry for selecting as the pseudorandom sequence generator output one of the output of the random number generator, a limit-up value, and a limit-down value. 
         [0028]    A spread spectrum clock generator designated AB including the spread spectrum clock generator designated A or AA further comprising an analog clock generator coupled directly to the stable frequency output of the phase-locked loop. 
         [0029]    A spread spectrum clock generator designated AC including the spread spectrum clock generator designated A, AA, or AB wherein the variable phase shifter comprises a variable-delay delay line. 
         [0030]    A spread spectrum clock generator designated AD including the spread spectrum clock generator designated AC wherein the variable-delay delay line comprises a plurality of stages where at least some stages comprise at least one load capacitor coupled through a selectable transmission gate. 
         [0031]    A spread spectrum clock generator designated AE including the spread spectrum clock generator designated AC wherein the variable-delay delay line comprises a plurality of stages where at least some stages comprise a multiplexor configured to select between a more-delayed and a less-delayed signal. 
         [0032]    A spread spectrum clock generator designated AF including the spread spectrum clock generator designated AC wherein the variable-delay delay line includes a plurality of delay stages coupled in series, and a multiplexor configured to select an output of the plurality of delay stages as the variable-delay delay line&#39;s output. 
         [0033]    A spread spectrum clock generator designated AG including the spread spectrum clock generator designated A, AA, AB, AC, AD, AE, or AF further comprising an analog clock divider coupled to receive the phase locked loop output directly, the spread-spectrum clock output being configured to drive a digital clock driver. 
         [0034]    A method of generating a spread-spectrum clock designated B including locking a phase-locked loop to a reference signal, the phase locked loop providing a stable frequency signal; phase shifting the stable frequency signal by a phase-shift determined by a pseudorandom sequence generator; and changing the phase-shift determined by the pseudorandom sequence generator. 
         [0035]    A method of generating a spread spectrum clock designated BA including the method designated B wherein the phase-shift determined by a pseudorandom sequence generator is a phase-shift selected between a random number, a limit-up phase shift determined from a prior output of the pseudorandom sequence generator, and a limit-down phase shift determined from the prior output of the pseudorandom sequence generator. 
         [0036]    A method of generating a spread spectrum clock designated BB including the method designated B or BA wherein the phase shift is performed by a variable-delay delay line. 
         [0037]    A method of generating a spread spectrum clock designated BC including the method designated BB wherein the variable-delay delay line comprises a plurality of stages where at least some stages comprise at least one load capacitor coupled through a selectable transmission gate. 
         [0038]    A method of generating a spread spectrum clock designated BD including the method designated BB wherein the variable-delay delay line comprises a plurality of stages where at least some stages comprise a multiplexor configured to select between a more-delayed and a less-delayed signal. 
       CONCLUSION 
       [0039]    Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall there between.