Abstract:
An apparatus for decoding a received BCH code signal for correcting a combined complex error is disclosed which includes a syndrome generating circuit for generating two n-bit syndromes corresponding to the received signal, a syndrome converting circuit for converting the two n-bit syndromes to a 2n-bit syndrome, a random error correcting circuit, a burst error correcting circuit, two combining circuits and output selecting circuit. The random error correcting circuit inputs the two n-bit syndromes and outputs a random error correction signal to one of the combining circuits and the burst error correcting circuit inputs the 2n-bit syndrome and outputs a burst error correction signal to the other of the combining circuits. The combining circuits combine the correction signals to the received BCH code signal. The output selecting circuit selectively outputs one of the combined signals from the combining circuits in accordance with the decoding conditions of the error correcting circuits and the result of comparison between the decoded and error-corrected signals from the combining circuits.

Description:
This application is a continuation of application Ser. No. 07/445,174, filed Dec. 4, 1989. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an error correction apparatus in a digital communication system using a BCH (Bose-Chandhuri-Hocqueghem) code, more particularly relates to a BCH code decoding apparatus for correcting a complex error in a digital communication system. 
     2. Description of the Prior Art 
     FIG. 1 is a block diagram showing a conventional combined-error-correcting circuit for correcting both random and burst errors, as described, for example, in &#34;Error Control Coding: Fundamentals and Applications&#34; by S. LIN and D. J. COSTELLO, Jr., pp. 280-282, published by Prentice-Hall, Inc., 1988. In the figure, numeral 1 is an input terminal for inputting a received coded message, 39 is a burst-error-correcting unit for correcting a burst error by burst trapping, 40 is a random-error-correcting unit for correcting a random error, 6 is an output selecting circuit for selecting either the output from the burst-error-correcting unit 39 or the output from the random-error-correcting unit 40 and 9 is an output terminal for outputting an decoded result. 
     The operation of the above-mentioned prior art will now be described. A received message which has been decoded at a transmitter site before transmitting and includes errors added in the communication path is input from the input terminal 1 into both the burst-error-correcting unit 39 and the random-error-correcting unit 40. The message is decoded by the respective correcting units, and either the decoded output from the burst-error-correcting unit 39 or the decoded output from the random-error-correcting unit 40 is selected by the output selecting circuit 6 in response to the condition of the communication path, and thereby the selected output is delivered from the output terminal 9 as an output of the complex error correcting circuit. 
     Since conventional complex error correcting circuits are generally arranged as described above, it is necessary to control the output selecting circuit 6 in response to the condition of the communication path with respect to the concrete error correcting code, but there is shown no definite suggestion as to how the condition of the communication path can be concretely grasped and there is also shown no criterion to appropriately judge such a condition, therefore it is difficult to accurately control the selecting circuit 6. There is a further problem that, because of the burst error correcting unit and the random error correcting unit being independently arranged from each other, it is necessary that the respective units independently include syndrome generating circuits for extracting the error condition. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to solve such problems as described above and to obtain an apparatus for decoding a BCH code signal and for correcting a complex error combined in the BCH code signal which is capable of grasping the condition of the communication path, concretely providing a criterion for judging the condition of the communication path and commonly using a syndrome generating circuit for a burst error correcting unit and a random error correcting unit. 
     This object is achieved by an apparatus for decoding a BCH code used for correcting a complex error which is capable of grasping the condition of a communication path by using the decoded result of a burst error correcting unit with a burst trapping function as well as the decoded result of the random error correcting unit having a circuit for deciding the result of an operation with a circuit for making an operation of integers of modulo 2 n  -1, thereby concretely providing a criterion for judging the condition of the communication path to control an output selecting circuit and there being further provided a means for converting a syndrome, thereby the common use of a syndrome generating circuit can be attained. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a block diagram showing a conventional apparatus for decoding a BCH code with a correction function of complex error; 
     FIG. 2 is a block diagram showing an apparatus for decoding a BCH code with a correction function of a complex error according to this invention; 
     FIG. 3 is a block diagram showing details of the random error correcting circuit shown in FIG. 2; 
     FIG. 4 is a detailed diagram of the burst error correcting circuit shown in FIG. 2; 
     FIG. 5 shows a detailed diagram of the output selecting circuit illustrated in FIG. 2; and 
     FIG. 6 is a table showing the criterion for controlling the output selecting switch incorporated in the output selection control circuit shown in FIG. 5. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will now be described. Referring now to FIG. 2, there is shown in block diagram form a error correcting unit. In the drawing, numeral 1 denotes an input terminal for inputting a coded message received; 2, a syndrome generating circuit for generating two n-bit syndromes for correcting a random error; 3, a delay circuit for holding the received message during the period of generating the syndromes and correcting an error; 4, a syndrome converting circuit for performing a conversion from the two n-bit syndromes generated in the syndrome generating circuit 2 to a 2n-bit syndrome for a burst trapping circuit for correcting a burst error correcting; 5, a burst error correcting circuit for calculating the position in which a burst error is generated, and the pattern of the burst error; 6, an output selecting circuit incorporating a criterion for grasping and judging the condition of a communication path by using the decoded results of the burst error correcting circuit 5 and a random error correcting circuit mentioned next; 7, a random error correcting circuit for receiving as an input, the syndrome which is vector expressed by the polynomial basis in a finite field and obtained with the syndrome generating circuit 2, converting the syndrome vector-expressed syndrome to an exponential expression of a primitive element of the finite field, obtaining an error position polynomial by normalizing the converted exponential repression with an integer operation of modulo 2 n  -1, obtaining the radical of the normalized error position polynomial by looking up a table of the normalized error position pre-calculated the constant terms of the normalized error position polynomial, calculating the true error position from the normalized error position, and correcting the random error; 8, a data ROM for storing data for converting the syndrome vector-expressed by the polynomial basis in the finite field obtained by the syndrome generating circuit 2 into the exponential expression of the primitive element of the finite field and data of the normalized error position which is the radical of the normalized error position polynomial; 9, an output terminal for outputting the decoded results; 10, a terminal for outputting a signal when an uncorrectable error showing the final decoded condition is detected; and 11-a and 11-b, exclusive OR circuits for adding error correction pulses output from the burst error and random error correcting circuits 5 and 7 to the received message. 
     FIG. 8 shows the details of the random error correcting circuit 7 shown in FIG. 2, and in this figure, numeral 12 is an input terminal for inputting the syndrome vector-expressed with the polynomial basis in the finite field obtained by the syndrome generating circuit 2 shown in FIG. 2, 13 a register for holding the input syndrome, 14 an adding circuit with modulo 2 n  -1, 15 a complementary number circuit with modulo 2 n  -1, 16 a register for temporarily holding data, 2 n  -1, a register having a function for checking the results of calculation by the adding circuit 14 with modulo 2 n  -1 and the complementary number circuit 15 with modulo 2 n  -1, 18 counter circuits for calculating the true error position, 19 an OR circuit for mixing the correction pulses output from the counter circuits 18 and 18, 20 an address control circuit for outputting an address to the data ROM 8 which stores the data for converting the syndrome vector-expressed with the polynomial basis in the finite field to the exponential expression of the primitive element of the finite field and the data of the normalized error position which is a radical of the normalized error position polynomial, 17 a register which receives the output of data ROM 8 and compares it to 2.sup. n -1. If the output of ROM 8 is equal to 2 n  -1, this indicates an uncorrectable error 21 an address terminal for outputting and address to the data ROM 8, 22 a data input terminal to which data are inputted from the data ROM 8, 23 an output terminal for outputting the correction pulse, and 24 a terminal for outputting an uncorrectable error detection signal when an error can not be corrected by the random error correcting circuit 7. 
     FIG. 4 shows the details of the burst error correcting circuit 5 shown in FIG. 2 in which numeral 25 is an input terminal for inputting the output of the syndrome converting circuit 4 illustrated in FIG. 2, 26 a 1-bit delay circuit, 27 a switch for controlling a feedback circuit consisting of the delay circuits 28 connected in loop through the switch, 28 a selecting switch for selecting either the output from the syndrome converting circuit 4 or the data from the feedback circuit, 29 a trapping (zero detection) circuit for detecting the fact that the upper (2n-b)-bits of the linear feedback shift register, of the feedback circuit having 2n-bits in length become zero, 30 a terminal outputting an uncorrectable burst error detection signal when an error which can not be corrected by the burst error correcting circuit 5 is detected, and 31 an error-pattern output terminal for serially outputting an error-pattern to be corrected when the burst error is corrected. 
     FIG. 5 is a detailed block diagram of the output selecting circuit 6 shown in FIG. 2 including the criterion for grasping and judging the condition of the communication path by using the decoded results of the burst error and random error correcting circuits 5 and 7 shown in FIG. 2. In FIG. 5, numeral 32 denotes an input terminal for the data which has been corrected by using the output from the random error correcting circuit 7, 33 an input terminal for data which has been corrected by using the output from the burst error correcting circuit 5, 34 an exclusive OR circuit for comparing the data corrected by the random error correcting circuit 7 and the data corrected by the burst error correcting circuit 5, 85 an input terminal of the uncorrectable error detection signal from the terminal 24 related to the random error correcting circuit 7, 36 an input terminal of the uncorrectable error detection signal from the terminal 31 related to the burst error correcting circuit 5, 37 an output selecting switch for selecting either the data corrected by the random error correcting circuit 7 or the data corrected by the burst error correcting circuit 5, and 38 an output selection control circuit for generating an uncorrectable signal to the terminal 10 (shown in FIGS. 2 and 4) depending on the uncorrectable error detection signals input from the random and burst error correcting circuits 7 and 5 to the input terminals 35 and 36, and the generating a control signal or controlling the output selecting switch 37 in accordance with the error detection signals and the output signal from the exclusive OR circuit 34 which compares the data input to the terminal 32, which has been corrected by the random error correcting circuit 7 and the data input to the terminal 33, which has been corrected by the burst error correcting circuit 5. 
     FIG. 6 is a table showing the criterion for controlling the output selecting switch 37 incorporated in the selecting circuit 6 and the criterion for deciding the uncorrectable error signal to the terminal 10. 
     The operation will now be described. A message which has been coded at a transmitter side and includes errors added at the communication path is received at the input terminal 1. Two n-bit syndromes S 1 , S 3  expressed by vectors of the polynomial basis in the finite field generated by the syndrome generating circuit 2. The two n-bit syndromes S 1 , S 3  are then input to the random error correcting circuit 7 and the syndrome converting circuit 4. In the random error correcting circuit 7, the input syndromes S 1 , S 3  are held in the register 13 and output as address of the data ROM 8 through the address control circuit 20 to the address output terminal 21. The syndromes S 1 , S 3  are converted by the data ROM 8 from the vector expression with the polynomial basis in the finite field to the exponential expression of primitive element of finite field, log S 1  and log S 3 . The converted syndromes log S 1  and log S 3 , are stored into the register 16 by way of the data input terminal 22 and the register 17. Based on the exponentially expressed syndromes log S 1  and log S 3  stored in the register 16, the constant term (log S 3  -3×log S 1 ) of the normalized error position polynomial is calculated using the adding circuit 14 and the complementary number circuit 15, and the constant term (log S 3  -3×log S 1 ) is then output as address of the data ROM 8 through the address control circuit 20 and, the address output terminal 21. The constant term (log S 3  -3×log S 1 ) is then converted by the data ROM 8 to two roots i=log α i  and j=log α j  of the normalized error position polynomial. α is a primitive element of a finite field and α i  and α j  are radicals of the normalized error position polynomial, i.e. they are represented the normalized error position. The two radicals i=log α i  and j=log α j  of the error position polynomial normalized by the data ROM 8 are directed through the data input terminal 22 and the register 17 and added by the adding circuit 14 with log S 1  and stored in the counter circuit 18 for calculating the true error position. At this time, the result of addition is checked by the register 17, and if it is in an uncorrectable condition, an uncorrectable error detection signal is output to the terminal 24. The true error position stored in the counter circuit 18 is counted down, and when the content of the counter circuit 18 becomes zero, an error correction pulse is given through the OR circuit 19 to the exclusive OR circuit 11-a. 
     On the other hand, the two n-bit syndromes S 1  and S 3  input into the syndrome converting circuit 4 are converted to 2n-bit syndromes and thereafter input to the burst error correcting circuit 5. For example, for (511,493) BCH codes having the generated polynomial of: 
     
         g(x)=X.sup.18 +X.sup.15 +X.sup.12 +X.sup.10 +X.sup.8 +X.sup.7 +X.sup.6 +X.sup.3 +1 
    
     the conversion is performed in accordance with the following equations: 
     
         S1.sub.O =S.sub.1.spsb.7 +S.sub.1.spsb.4 +S.sub.1.spsb.3 +S.sub.1.spsb.1 +S.sub.1.spsb.O +S.sub.3.spsb.7 +S.sub.3.spsb.4 +S.sub.3.spsb.3 +S.sub.3.spsb.1 
    
     
         S1.sub.1 =S.sub.1.spsb.8 +S.sub.1.spsb.5 +S.sub.1.spsb.4 +S.sub.1.spsb.2 +S.sub.1.spsb.1 +S.sub.1.spsb.O +S.sub.3.spsb.8 +S.sub.3.spsb.5 +S.sub.3.spsb.4 +S.sub.3.spsb.1 +S.sub.3.spsb.O 
    
     
         S1.sub.2 =S.sub.1.spsb.6 +S.sub.1.spsb.5 +S.sub.1.spsb.3 +S.sub.1.spsb.2 +S.sub.1.spsb.1 +S.sub.1.spsb.O +S.sub.3.spsb.6 +S.sub.3.spsb.5 +S.sub.3.spsb.3 +S.sub.3.spsb.1 +S.sub.3.spsb.O 
    
     
         S1.sub.3 =S.sub.1.spsb.6 +S.sub.1.spsb.2 +S.sub.3.spsb.6 +S.sub.3.spsb.3 +S.sub.3.spsb.2 
    
     
         S1.sub.4 =S.sub.1.spsb.7 +S.sub.1.spsb.3 +S.sub.3.spsb.7 +S.sub.3.spsb.4 +S.sub.3.spsb.3 
    
     
         S1.sub.5 =S.sub.1.spsb.8 +S.sub.1.spsb.4 +S.sub.1.spsb.O +S.sub.3.spsb.8 +S.sub.3.spsb.5 +S.sub.3.spsb.4 +S.sub.3.spsb.O 
    
     
         S1.sub.6 =S.sub.1.spsb.7 +S.sub.1.spsb.5 +S.sub.1.spsb.4 +S.sub.1.spsb.3 +S.sub.3.spsb.7 +S.sub.3.spsb.6 +S.sub.3.spsb.5 +S.sub.3.spsb.4 +S.sub.3.spsb.3 
    
     
         S1.sub.7 =S.sub.1.spsb.8 +S.sub.1.spsb.7 +S.sub.1.spsb.6 +S.sub.1.spsb.5 +S.sub.1.spsb.3 +S.sub.1.spsb.1 +S.sub.3.spsb.8 +S.sub.3.spsb.6 +S.sub.3.spsb.5 +S.sub.3.spsb.3 +S.sub.3.spsb.1 
    
     
         S1.sub.8 =S.sub.1.spsb.8 +S.sub.1.spsb.6 +S.sub.1.spsb.3 +S.sub.1.spsb.2 S.sub.1.spsb.1 +S.sub.1.spsb.O +S.sub.3.spsb.6 +S.sub.3.spsb.3 +S.sub.3.spsb.2 +S.sub.3.spsb.1 +S.sub.3.sbsp.O 
    
     
         S1.sub.9 =S.sub.1.spsb.7 +S.sub.1.spsb.4 +S.sub.1.spsb.3 +S.sub.1.spsb.2 +S.sub.1.spsb.1 +S.sub.3.spsb.7 +S.sub.3.spsb.4 +S.sub.3.spsb.3 +S.sub.3.spsb.2 +S.sub.3.spsb.1 
    
     
         S1.sub.10 =S.sub.1.spsb.8 +S.sub.1.spsb.7 +S.sub.1.spsb.5 +S.sub.1.spsb.2 +S.sub.1.spsb.1 +S.sub.3.spsb.8 +S.sub.3.spsb.7 +S.sub.3.spsb.5 +S.sub.3.spsb.2 +S.sub.3.spsb.1 
    
     
         S1.sub.11 =S.sub.1.spsb.8 +S.sub.1.spsb.6 +S.sub.1.spsb.3 +S.sub.1.spsb.2 +S.sub.1.spsb.O +S.sub.3.spsb.8 +S.sub.3.spsb.6 +S.sub.3.spsb.3 +S.sub.3.spsb.2 +S.sub.3.spsb.o 
    
     
         S1.sub.12 =S.sub.1.spsb.O +S.sub.3.spsb.O 
    
     
         S1.sub.13 =S.sub.1.spsb.1 +S.sub.3.spsb.1 
    
     
         S1.sub.14 =S.sub.1.spsb.2 +S.sub.3.spsb.2 
    
     
         S1.sub.15 =S.sub.1.spsb.7 +S.sub.1.spsb.4 +S.sub.1.spsb.1 +S.sub.1.spsb.O +S.sub.3.spsb.7 +S.sub.3.spsb.4 +S.sub.3.spsb.1 +S.sub.3.spsb.O 
    
     
         S1.sub.16 =S.sub.1.spsb.8 +S.sub.1.spsb.5 +S.sub.1.spsb.2 +S.sub.1.spsb.1 +S.sub.3.spsb.8 +S.sub.3.spsb.5 +S.sub.3.spsb.2 +S.sub.3.spsb.1 
    
     
         S1.sub.17 =S.sub.1.spsb.6 +S.sub.1.spsb.3 +S.sub.1.spsb.2 +S.sub.1.spsb.O +S.sub.3.spsb.6 +S.sub.3.spsb.3 +S.sub.3.spsb.2 +S.sub.3.spsb.O 
    
     In the burst error correcting circuit 5, the switch 27 for controlling the feedback is closed and the selecting switches 28 are turned to the sides &#34;a&#34; connected to the input terminals 25 so that the two n-bit syndromes converted by the syndrome converting circuit 4 are inputted to the delay circuit 26 of the linear feedback shift register circuit having 2n-bit in length. The selecting switch 28 is then turned to the linear feedback shift register circuit sides &#34;b&#34; and the burst error pattern is checked by the trapping (zero detection) circuit 29 while performing the shifting operation. If the burst error pattern is detected by the trapping (zero detection) circuit 29, the switch 27 is opened and the error pattern is serially output from the error pattern output terminal 81 to the exclusive OR circuit 11-b. At this time, if no error pattern is detected by the shifting operation throughout the code length, the signal of uncorrectable error detected by the trapping (zero detection) circuit 29 is output to the terminal 80. 
     If an error pattern is detected at the random error correcting circuit 7 or the burst error correcting circuit 5, the received message is read out from the delay circuit 3 in which the received message has been held, the respective error patterns detected at the random and burst error correcting circuits 7 and 5 are separately combined to the received message by the exclusive OR circuits 11-a, 11-a, and thus the random and burst errors are corrected to provide their decoded messages. Thereafter, the decoded messages corrected by the random error and burst error correcting circuits 7 and 5 and the outputs from the uncorrectable error detection terminals 24, 30 connected to the random error and burst error correcting circuits 7 and 5 are input to the output selecting circuit 6. In the output selecting circuit 6, the respective messages input from the random error and burst error correcting circuits 7 and 5 are compared by the exclusive OR circuit 34. The result of comparison by the exclusive OR circuit 34 and the uncorrectable error detection signals from the terminals 24, 30 are input to the output selection control circuit 38 which, in turn, controls the output selecting switch 37 in accordance with the criterion of output selection shown in FIG. 6. Thus, if both of the uncorrectable error detection signals from the terminals 24, 30 indicates correction and if the output of the exclusive OR circuit 34 which compares the respective decoded messages indicates that the decoded messages are identical, then the output selecting switch 37 is turned to its &#34;a&#34;-side to select the output of the random error correcting circuit 7 through the exclusive OR circuit 11-a, and if the uncorrectable error detection signal from the terminal 24 shows correction and the uncorrectable error detection signal from the terminal 30 detects an uncorrectable error, the output selecting switch 37 is turned to its &#34;a&#34;-side to select the same output as above, and if the uncorrectable error detection signal from the terminal 30 indicates correction and the uncorrectable error detection signal from the terminal 24 shows detection of any uncorrectable error, then the output selecting switch 37 is turned to its &#34;b&#34;-side to select the output of the burst error correcting circuit 5 through the exclusive OR circuit 11-b, and in other cases, the signal which represents the exist of an uncorrectable error is output at the terminal 10. The final decoded message selected by the output selecting circuit 6 is output through the output terminal 9. 
     In the above-described embodiment, the random error correction circuit 7 is provided with the circuit performing operation with modulo 2 n  -1, but there may be provided a random error correcting circuit using a conventional linear period shift register circuit. Furthermore, the code length is not definitely limited, but it is a matter of course that a similar effect can also be brought forth with a shortened code. 
     As described above, according to the present invention, there can effectively be provided a higher reliable circuit for decoding a BCH code in order to correct a complex error by the provision of the output selecting circuit incorporating the criterion of selecting the outputs of the random error and burst error correcting circuits. 
     It is further understood by those skilled in the art that the foregoing description is a preferred embodiment of the disclosed device and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.