Abstract:
A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.

Description:
[0001]    This Application is a division of U.S. patent application Ser. No .11/458,120 filed on Jul. 18, 2006 which is a division of U.S. patent application Ser. No. 10/904,582 filed on Nov. 17, 2004, now U.S. Pat. No. 7,122,439 issued Oct. 17, 2006. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to the field of semiconductor device fabrication; more specifically, it relates to a method fabricating a bottle trench and a bottle trench capacitor. 
       BACKGROUND OF THE INVENTION 
       [0003]    One use for trench capacitors is for the storage node of dynamic random access memory (DRAM) cells. As DRAM cell design rules become ever smaller, the required cell capacitance does not become smaller proportionally but remains relatively fixed. The use of bottle trench capacitors is one way of increasing the capacitance trench capacitors as the dimensions of DRAM cells decrease. However, present schemes for forming bottle trench capacitors suffer from etch related defects during formation of the bottle portion of the capacitor. These defects can cause shorting of the capacitor to the P-well of the DRAM cell and/or uneven capacitor dielectric formation. Further, poor bottle diameter size control due to non-uniform wet etch processes can lead to irregular bottle diameter, often resulting in merging of the bottles of adjacent DRAM cells. Merging of adjacent the bottles of adjacent trench capacitors can cause single bit fails in DRAM cell arrays. Defects and merged trenches can reduce DRAM processing yield, reliability and performance. Therefore, there is a need for a bottle trench capacitor process with reduced susceptibility to process defects and merging of adjacent trenches during formation of the bottle portion of the capacitor. 
       SUMMARY OF THE INVENTION 
       [0004]    The present invention is directed to a method of forming an upper region of a trench (collar region of a bottle trench capacitor) and a wider lower region of the trench (bottle region of the bottle trench capacitor) by oxidation of sidewall and bottom surfaces of the lower portion of trench while protecting the upper region and removal of the oxidized layer thus formed. 
         [0005]    A first aspect of the present invention is a method comprising: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench. 
         [0006]    A second aspect of the present invention is a method, comprising: (a) providing a substrate; (b) forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench, the upper region abutting the lower region; (c) forming a protective layer on the sidewalls and the bottom of the trench; (d) removing the protective layer from the sidewalls in the lower region of the trench and from the bottom of the trench; (e) oxidizing a layer of the substrate exposed in step (d) on the sidewalls in the lower region of the trench and on the bottom of the trench; and (f) removing the layer of the substrate oxidized in step (e) from the lower region of the trench. 
         [0007]    A third aspect of the present invention is a method, comprising: (a) providing a substrate; (b) forming a trench in the substrate, the trench having sidewalls and a bottom; (c) forming a first silicon oxide layer on the sidewalls and the bottom of the trench, forming a silicon nitride layer on the silicon oxide layer and forming a polysilicon layer on the silicon nitride layer; (d) forming a second silicon oxide layer on the polysilicon layer, (e) partially filling the trench with an organic material, a top surface of the organic material defining a boundary between a lower region and an upper region the trench, the upper region adjacent to a top surface of the substrate and the lower region adjacent to the bottom of the trench; (f) removing the second silicon oxide layer in the upper region; (h) removing the organic material from the trench; (i) converting an outermost layer of the polysilicon layer in the upper region to a nitrided silicon layer; (j) removing in order the second silicon oxide layer, the polysilicon layer, the silicon nitride layer and the first silicon oxide layer from the lower region and the bottom of the trench; (k) forming an oxidized layer of the substrate on the sidewalls and the bottom of the trench exposed in step (j) in the lower region of the trench; and (l) removing the oxidized layer of the substrate from lower region of the trench. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0008]    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
           [0009]      FIGS. 1 through 14  are partial cross-sectional views illustrating fabrication of a trench capacitor according to the present invention is according to the present invention; and 
           [0010]      FIG. 15 , is a cross-sectional view of a DRAM cell using a bottle trench capacitor, the bottle region of which was formed according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]      FIGS. 1 through 15  are partial cross-sectional views illustrating fabrication of a trench capacitor according to the present invention is according to the present invention. In  FIG. 1 , formed in a substrate  100  is a trench  105 . Substrate  100  may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Substrate  100  may include an uppermost epitaxial silicon layer. For the purposes of the present invention, a silicon substrate is defined as a bulk silicon substrate, the silicon layer of a SOI substrate, an uppermost epitaxial silicon layer formed on either a bulk or SOI substrate or a silicon layer formed on a substrate of any other material. Trench  105  may be formed by any number of anistropic etch processes, such as plasma etching and reactive ion etching (RIE), known in the art using a hard mask that is lithographically defined. A top surface  110  of substrate  100  defines a horizontal or lateral direction and a vertical direction is defined as a direction perpendicular to the horizontal direction. Trench  105  includes sidewalls  115  and a bottom  120 . In  FIG. 1 , the hard mask used to define trench  105  includes a pad oxide layer  125  formed on top surface  110  of substrate  100  and a pad nitride layer  130  formed on a top surface  135  of pad oxide layer  125 . Trench  105  has a width W and a depth D (where D is measured from top surface  110  of substrate  100 ). While W and D are functions of technology design groundrules which are ever decreasing, in one example W is about 100 nm to about 200 nm and D is about 6 microns to about 10 microns. In one example, pad oxide layer  125  comprises silicon oxide about 40 Å to about 130 Å thick and pad nitride layer  130  comprises silicon nitride about 1500 Å to about 2500 Å thick 
         [0012]    In  FIG. 2 , a silicon oxide layer  140  is formed on sidewalls  115  and bottom  120  of trench  105 , a silicon nitride layer  145  is formed on silicon oxide layer  140  and pad nitride layer  130 , and a polysilicon layer  150  is formed on silicon nitride layer  145 . Silicon oxide layer  140  may be formed by thermal oxidation of a layer of substrate  100  on sidewalls  115  and bottom  120  of trench  105  after trench  105  has been formed. Alternatively, silicon oxide layer  140  may be formed by any number of methods, such as chemical-vapor deposition (CVD), low-pressure chemical-vapor deposition (LPCVD) and plasma enhanced chemical-vapor deposition (PECVD) known in the art. Silicon nitride layer  145  and polysilicon layer  150  are conformal coatings and may be formed by any number of methods, such as CVD, LPCVD and PECVD known in the art. In one example, silicon oxide layer  140  is about 30 Å to about 100 Å thick, silicon nitride layer  145  is about 40 Å to about 150 Å thick and polysilicon layer  150  is about 200 Å to about 500 Å thick. 
         [0013]    In  FIG. 3 , a high temperature oxidation is performed to convert an outer layer of polysilicon layer  150  to a silicon oxide layer  155 . In one example, silicon oxide layer  155  is formed by thermal oxidation in dry oxygen at a temperature of about 1000° C. and is about 100 Å to about 500 Å thick. Alternatively, silicon oxide layer  155  may be formed by a conformal deposition process such as LPCVD. 
         [0014]    In  FIG. 4 , a photoresist layer  160  is formed over a top surface  165  of silicon oxide layer  150 . Photoresist layer  160  fills trench  105 . Other organic materials may be subsituted for photoresist. 
         [0015]    In  FIG. 5 , resist layer  160  is recessed to a depth D 1  measured from top surface  110  of silicon substrate  100 . Depth D 1  defines an upper region  170  and a lower region  175  of trench  105 . Depth D 1  may be selected to correspond to be below the bottom of a P-well formed in an upper region of substrate  100  in which an N-channel field effect transistor (NFET) of a DRAM memory cell will be formed (see  FIG. 15 ). In the case of a DRAM cell utilizing a buried strap, D 1  defines the depth of a region where a collar oxide will be formed adjacent to the buried strap, the buried strap connecting the source of the NFET to the polysilicon plate of the capacitor (see  FIG. 15 ). The collar oxide will isolate all or an upper portion of upper region  170  from the NFET of a DRAM memory cell. In one example D 1  is about 1.0 microns to about 2.0 microns. Resist layer  160  may be recessed by any number of RIE processes well known in the art that do not etch silicon oxide. 
         [0016]    In  FIG. 6 , a portion of silicon oxide layer  155 , not covered by resist layer  160  is removed, for example, using buffered HF or by chemical downstream etch (CDE) or other plasma based etching process, thus exposing polysilicon layer  150  in upper region  170  of trench  105 . 
         [0017]    In  FIG. 7 , resist layer  160  (see  FIG. 6 ) is removed, for example, using Huang cleans (aqueous mixtures of H 2 SO 4  and H 2 O 2  and NH 4   0 H and H 2 O 2 ) followed by an SC-2 clean (aqueous HCI). 
         [0018]      FIG. 8 , a plasma nitridation process using, for example, using NH 3 , NO, N 2 O or HNO 3  gas is performed in order to convert an outer layer of polysilicon layer  150  to a silicon nitride layer  180  where polysilicon layer  150  is not covered by silicon oxide layer  155 . Thus in trench  105 , silicon nitride layer  180  is formed only in upper region  170 . In one example, silicon nitride layer  180  is about 5 Å to about 50 Å thick. 
         [0019]    Silicon oxide layer  140 , silicon nitride layer  145 , polysilicon layer  50  and silicon nitride layer  180  act as protective layers protecting sidewalls  115  of upper region  170  of trench  105  during subsequent processing steps that form a bottle region in silicon substrate as described infra. 
         [0020]    In  FIG. 9 , silicon oxide layer  155  (see  FIG. 8 ) is removed using, for example, dilute HF, from lower region  175  of trench  105  and thus exposing polysilicon layer  150  in the lower region. 
         [0021]    In  FIG. 10 , polysilicon layer  150  is removed in lower region  175  of trench  105  using for example, a three step process of first dilute HF etch, followed by an aqueous solution of HN 3  and H 2 O 2  at a temperature between about 50° C. and about 80° C. followed by a second dilute HF etch thus exposing silicon nitride layer  145  in the lower region. Polysilicon layer  150  is not removed from upper region  170  because the polysilicon layer in the upper region is covered by silicon nitride layer  180 . 
         [0022]    In  FIG. 11 , silicon nitride layer  145  is removed in lower region  175  of trench  105 , for example, by a CDE or other plasma based etching process selective silicon nitride to silicon oxide thus exposing silicon oxide layer  140  in the lower region. Silicon nitride layer  145  is not removed from upper region  170  because silicon nitride layer  145  in the upper region is covered by polysilicon layer  150 . All of remaining silicon nitride layer  180  (see  FIG. 10 ) is also removed thus exposing polysilicon layer  150  in upper region  170 . 
         [0023]    In  FIG. 12 , silicon oxide layer  140  is removed in lower region  175  of trench  105  using, for example, aqueous dilute HF thus exposing sidewalls  115  and bottom  120  of trench  105  in the lower region. Silicon oxide layer  140  is not removed from upper region  170  because silicon oxide layer  140  in the upper region is covered by silicon nitride layer  145  and polysilicon layer  150 . 
         [0024]    In  FIG. 13 , a thermal oxidation step is performed forming oxide layer  185  on all exposed surfaces of trench  105  and converting polysilicon layer  150  (see  FIG. 12 ) in upper region  170  to a silicon oxide layer  190 . Sidewalls  115  of trench  105  in upper region  170  are not oxidized because of the protection afforded by silicon nitride layer  145 . In one example, the thermal oxidation step is performed in a furnace using dry oxygen at a temperature of about 1000° C. Wet oxidation (using H 2 O or a mixture of H 2 O and O 2 ) at a temperature of about 800° C. may be used as well. In one example, a thickness T of silicon oxide layer  185  is about ¼ the width W or greater (see  FIG. 1 ) of trench  105 . The thickness T is a function of the length of time of the thermal oxidation. 
         [0025]    In  FIG. 14  silicon oxide layers  185  and  190  (see  FIG. 13 ) are removed, for example using dilute aqueous HF creating sidewalls  195  and bottom  200  of a bottle region  205  of trench  105  in what was lower region  175  (see  FIG. 13 ). Trench  105  of  FIG. 13  is now trench  105 A of  FIG. 14  and has an approximate “bottle” shape, with upper region  170  being the “neck” of the “bottle.” Another way of describing the geometry of trench  105 A is that a cross-sectional area of lower region  175  of trench  105 A is greater than a cross-sectional area of upper region  170  of trench  105 A. Bottle region  205  has a width W 1 . While it may be desirable for width W 1  to be large, for example, to increase capacitance by increasing the surface area of sidewalls  115  and bottom  120 , the maximum value of width W 1  is constrained by the spacing between adjacent trenches  105 A in an integrated circuit chip. Adjacent trenches cannot be allowed to contact. In one example W 1  is about equal to 1.5 times W to about 2 times W (see  FIG. 1 ). 
         [0026]    Note no silicon etching was performed in formation of bottle region  205 . The use of silicon etchants can lead to various defects during formation of the “bottle” because of pinholes in protective layers may allow etching of silicon in sidewalls  115  of upper region  170  and because silicon etchants can cause sidewalls  195  of bottle region  205  to be rough. Either of these types of defects can adversely affect processing yield, reliability and DRAM performance. 
         [0027]    In  FIG. 15 , is a cross-sectional view of a DRAM cell using a bottle trench capacitor, the bottle region of which was formed according to the present invention. In  FIG. 15 , silicon nitride layer  145  and silicon oxide layer  140  on sidewalls  115  of upper region  170  were removed using appropriate wet etching processes. After removing the silicon nitride layer  145  and silicon oxide layer  140 , a DRAM cell was completed as described briefly infra. 
         [0028]    A silicon oxide layer  210  was formed on exposed silicon surfaces in trench  105 A and a node nitride layer  215  was formed on silicon oxide layer using, for example, an LPCVD process. An oxy-nitride layer  220  was formed on node silicon nitride layer  215  using, for example, a thermal oxidation process. An N-doped first polysilicon layer  225  was deposited in trench  105 A using, for example, an LPCVD process. First polysilicon layer  225  was removed from upper portion  170 A of upper region  170  using, for example, an isotropic etch process. Node nitride layer  215  and oxy-nitride layer  220  were removed from upper portion  170 A from of upper region  170  using, for example, a mixture of HF and ethylene glycol. 
         [0029]    A collar oxide layer  230  was formed in upper portion  170 A of upper region  170  using, for example, an LPCVD process. An N-doped second polysilicon layer  235  was deposited in upper portion  170 A of upper region  170  using, for example, an LPCVD process and then etched back using, for example, a RIE process. Collar oxide layer  230  exposed above second polysilicon layer  235  was removed using for example, a wet etching process. 
         [0030]    A plasma nitridation process was performed to form a nitrided layer  240  for variable retention time control. An N-doped third polysilicon layer  245  was deposited using, for example, an LPCVD process and a buried strap  250  was formed by out-diffusion of dopant (in one example arsenic) from third polysilicon layer  2450 . Third polysilicon layer  245  was etched back using, for example, an RIE process, and a thick oxide layer  255  formed using, for example an LPCVD or PECVD process. 
         [0031]    Shallow trench isolation (STI) (not shown) was formed, pad oxide layer  125  and pad nitride layer  130  removed and then a gate dielectric layer  260  was formed. Sources  265  and drains  270  were formed using spacer, extension implantation and source/drain ion implantation processes and gate electrodes  275 A and  275 B formed using, for example polysilicon LPCVD and RIE processes. Gate electrodes  275 A are wordlines (WLs) of a DRAM cell  280  and gate electrode  275 B is a passing wordline going to other DRAM cells. 
         [0032]    First, second and third polysilicon layers  225 ,  235  and  240  are examples of an electrically conductive material that may be used to fill trench  105 A and act as a first plate of bottle trench capacitor  285 . Many other combinations of dielectric layers and electrically conductive plate materials and methods of forming the dielectric layer and plates known in the may be subsituted. 
         [0033]    In the case that bottle trench capacitor  285  is used in an NFET gated DRAM cell, a P-well region  290  of substrate  100  is illustrated in approximate position relative to upper region  170 , P-well region  285  may be formed after formation of bottle trench capacitor  280  or prior to formation of trench  105  (see  FIG. 14 ). 
         [0034]    Therefore, the present invention provides a bottle trench capacitor process with reduced susceptibility to process defects and merging of adjacent trenches during formation of the bottle portion of the capacitor. 
         [0035]    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.