Abstract:
A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Description:
RELATED APPLICATIONS 
     This application is a division of U.S. patent application Ser. No. 11/781,370 filed on Jul. 23, 2007 which is a division of U.S. patent application Ser. No. 11/275,638 filed on Jan. 20, 2006 and now U.S. Pat. No. 7,298,008 issued on Nov. 20, 2007. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of integrated circuits; more specifically, it relates to an electrostatic discharge (ESD) protection device for use in integrated circuits fabricated on silicon-on-insulator (SOI) substrates and a method of fabricating the ESD protection device. 
     BACKGROUND OF THE INVENTION 
     In order to meet increasing performance targets, advanced complimentary metal-oxide-silicon (CMOS) technologies are being scaled down in size to the point that sensitivity to ESD is becoming a significant reliability problem. The use of silicon control rectifiers (SCRs) to protect CMOS technologies built with bulk silicon substrates is known in the industry. However, current SCR-based ESD protection devices suffer from high junction capacitance and current crowding making them unsuitable for CMOS technologies built with SOI substrates. Therefore, there is an ongoing need for an SCR device for electrostatic discharge (ESD) protection in integrated circuits fabricated on silicon-on-insulator (SOI) substrates. 
     SUMMARY OF THE INVENTION 
     A first aspect of the present invention is a silicon control rectifier, comprising: silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane. 
     A second aspect of the present invention is a silicon control rectifier, comprising: a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; a first doped region in the silicon layer, the first doped region having a first net peak doping concentration, a second doped region having a second net peak doping concentration and a third doped region having a third net peak doping concentration, the second and third net peak doping concentrations being a same doping concentration, the first doped region between and abutting the second and third doped regions, the second and third doped regions not abutting; a fourth doped region in the silicon layer in the silicon layer, the fourth doped region having a fourth net peak doping concentration in the silicon layer, the fourth doped region abutting only the second doped region; a fifth doped region in the silicon layer, the fifth doped region having a fifth net peak doping concentration in the silicon layer, the fifth doped region abutting only the third doped region; wherein a path of current flow from the fourth doped region, through the second doped region, the first doped region and the third doped region to the fifth doped region, is in a single horizontal direction parallel to the horizontal plane. 
     A third aspect of the present invention is a method of fabricating a silicon control rectifier, comprising: forming a blanket doped region having a net peak doping concentration in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; forming a first doped region in the silicon layer, the first doped region having a first net peak doping concentration, the first doped region dividing the blanket doped region into a second doped region having a second net peak doping concentration and a third doped region having a third net peak doping concentration, the second and third net peak doping concentrations being a same doping concentration, the first doped region between and abutting the second and third doped regions, the second and third doped regions not abutting; forming a fourth doped region in the silicon layer, the fourth doped region having a fourth net peak doping concentration in the silicon layer, the fourth doped region abutting only the second doped region; forming a fifth doped region in the silicon layer, the fifth doped region having a fifth net peak doping concentration in the silicon layer, the fifth doped region abutting only the third doped region; wherein a path of current flow from the fourth doped region, through the second doped region, the first doped region and the third doped region to the fifth doped region, is in a single horizontal direction parallel to the horizontal plane. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
         FIG. 1A  is a plan view and  1 B is a cross-section through line  1 B- 1 B of  FIG. 1A  illustrating a first step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; 
         FIG. 2A  is a plan view and  2 B is a cross-section through line  2 B- 2 B of  FIG. 2A  illustrating a second step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; 
         FIG. 3A  is a plan view and  3 B is a cross-section through line  3 B- 3 B of  FIG. 3A  illustrating a third step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; 
         FIG. 4A  is a plan view and  4 B is a cross-section through line  4 B- 4 B of  FIG. 4A  illustrating a fourth step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; 
         FIG. 5A  is a plan view and  5 B is a cross-section through line  5 B- 5 B of  FIG. 5A  illustrating a fifth step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; 
         FIG. 6  is a schematic diagram of an ESD protection circuit according to an embodiment of the present invention; 
         FIG. 7A  is a plan view and  7 B is a cross-section through line  7 B- 7 B of  FIG. 7A  illustrating the ESD protection circuit of  FIG. 5  superimposed over the SCR ESD protection device illustrated in  FIGS. 5A and 5B , and 
         FIG. 8  is a simulated lateral profile of an SCR ESD protection device according to the embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     CMOS devices comprise N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs). NFETs are fabricated in a P-well with region of the P-well under a gate electrode comprising the channel of the NFET and N-doped source/drains formed in the P-well on either side of gate. PFETs are fabricated in an N-well with region of the N-well under a gate electrode comprising the channel of the PFET and P-doped source/drains formed in the N-well on either side of gate. 
       FIG. 1A  is a plan view and  1 B is a cross-section through line  1 B- 1 B of  FIG. 1A  illustrating a first step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention. In  FIG. 1A , a region of shallow trench isolation (STI)  100  having a perimeter  105  surrounds a P-well  110 . 
     In  FIG. 1B , it can be seen P-well  110  and STI  100  are formed in a single crystal silicon layer  115 . Silicon layer  115  is formed in over a buried oxide layer (BOX)  120 . BOX  120  is formed over a bulk silicon substrate  125 . Silicon layer  115 , BOX  120  and substrate  125  comprise an SOI substrate  130 . 
     BOX  110  may be formed by forming a patterned mask over silicon layer  115 , etching away regions of the silicon layer not protected by the patterned mask down to BOX  120 , depositing an oxide to back fill the regions of silicon layer etched away and performing a chemical-mechanical polish (CMP) so that a top surface of P-well  110  is coplanar with a top surface of STI  100 . The patterned mask, may be a hard-mask, for example, a patterned layer of silicon nitride (Si 3 N 4 ) that itself was patterned using a photolithographic process. Silicon layer  115  may be etched, for example, by reactive ion etching (RIE). 
     P-well  110  may be formed by ion-implantation of a boron species, in one example, implantation of BF 2 . The boron ion-implantation may be performed through a thin oxide layer (not shown in  FIG. 1B ). In one example, P-well  110  has a peak boron concentration between about 2E18 atoms/cm 3  and about 7E18 atoms/cm 3 . A peak dopant concentration is the highest concentration of a dopant within a given region. 
     Formation of P-well  110  may be performed simultaneously with formation of the P-wells of CMOS NFETs used in the functional circuits of an integrated circuit to be protected by the SCR ESD protection device whose fabrication is being described. 
       FIG. 2A  is a plan view and  2 B is a cross-section through line  2 B- 2 B of  FIG. 2A  illustrating a second step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention. In  FIGS. 2A and 2B , an N-well region  135  is formed in silicon layer  115 . N-well region  135  divides P-well  110  (see  FIGS. 1A and 1B ) into a first P-well region  110 A and a second P-well region  110 B. A first side of N-well region  135  abuts first P-well region  110 A along a first PN junction  137  and an opposite second side of N-well region  135  abuts first P-well region  110 B along a second PN junction  138 . 
     N-well region  135  may be formed by forming a patterned photoresist mask over silicon layer  115 , ion implanting an N-type dopant species into the silicon layer where the silicon layer is not protected by the photoresist mask and then removing the photoresist mask. 
     N-well  135  region may be formed by ion-implantation a N-dopant species, in one example, by ion implantation of arsenic (As). The As ion-implantation may be performed through a thin oxide layer (not shown in  FIG. 2B ). In one example, N-well  135  region has a peak boron concentration between about 6E17 atoms/cm 3  and about 1E18 atoms/cm 3 . 
     Formation of N-well region  135  may be performed simultaneously with formation of the N-wells of CMOS PFETs used in the functional circuits of an integrated circuit to be protected by the SCR ESD protection device whose fabrication is being described. 
       FIG. 3A  is a plan view and  3 B is a cross-section through line  3 B- 3 B of  FIG. 3A  illustrating a third step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention. In  FIG. 3A , a gate stack  140  is formed over first P-well region  110 A, second P-well region  110 B and N-well region  135 . A first gate region  145  of gate stack  140  overlaps first P-well region  110 A and the first side of N-well region  135  (PN junction  137 ). A second gate stack region  150  of gate stack  140  overlaps second P-well region  110 B and the second side of N-well region  135  (PN junction  138 ). 
     First and second gate stack regions  145  and  150  extend parallel to each other. First and second gate stack regions  145  and  150  are connected by an integrally formed spine  152  perpendicular to the first and second gate stack regions. A second integrally formed spine  153  extends perpendicular to second gate stack region  150  on an opposite side of gate stack region from spine  152 . Opposite ends of first gate stack region  145  and opposite ends of second gate stack region  150  overlap perimeter  105 . Spine  152  does not overlap perimeter  105 . The end of spine  153  not joined to second gate stack region  150  overlaps perimeter  105 . 
     In  FIG. 3B , first gate stack region  145  and second gate stack region  150  comprise a polysilicon layer  155  over a gate dielectric layer  160 . Though gate dielectric layer  160  is shown only under first and second gate stack regions  145  and  150 , the gate dielectric layer may extend over the entire top of surface of silicon layer  115 . 
     Gate stack  140  may be formed by forming a blanket gate dielectric layer over silicon layer  115 , forming a blanket polysilicon layer over the gate dielectric layer, forming a patterned photoresist mask over the blanket polysilicon layer, etching away regions of the blanket polysilicon silicon layer not protected by the patterned photoresist mask down to the blanket dielectric layer to form a patterned polysilicon layer, removing the photoresist mask and optionally etching away the blanket dielectric layer not protected by the patterned polysilicon. The blanket polysilicon layer may be etched, for example, using an RIE. The blanket gate dielectric may be etched, for example, using an RIE or by wet etching. 
     Formation of gate stack  140  may be performed simultaneously with formation of the gate electrodes of CMOS PFETs and/or NFETs used in the functional circuits of an integrated circuit to be protected by the SCR ESD protection device whose fabrication is being described. 
       FIG. 4A  is a plan view and  4 B is a cross-section through line  4 B- 4 B of  FIG. 4A  illustrating a fourth step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention. In  FIGS. 4A and 4B , highly doped first and second P-type regions  165  and  170  are formed in silicon layer  115 . First P-type region  165  is formed in a region of first P-well region  110 A. A portion of first P-well  110 A region remains between N-well region  135  and first P-type region  165  under first gate stack region  145 . An interface  172  separates the remaining first P-well region  110 A from first P-type region  165 . An interface  173  separates the remaining second P-well region  110 B from second P-type region  170 . 
     First and second P-type regions  165  and  170  may be formed by forming a patterned photoresist mask over silicon layer  115 , ion implanting a P-type dopant species into the silicon layer where the silicon layer is not protected by the photoresist mask or gate stack  140  and then removing the photoresist mask. 
     First and second P-type regions  165  and  170  may be formed by ion-implantation of a boron species, in one example, implantation of BF 2 . The boron ion-implantation may be performed through a thin oxide layer (not shown in  FIG. 4B ). In one example, first and second P-type regions  165  and  170  have a peak boron concentration between about 1E20 atoms/cm 3  and about 2E20 atoms/cm 3 . 
     Formation of first and second P-type regions  165  and  170  may be performed simultaneously with formation of the source/drains of CMOS PFETs used in the functional circuits of an integrated circuit to be protected by the SCR ESD protection device whose fabrication is being described 
       FIG. 5A  is a plan view and  5 B is a cross-section through line  5 B- 5 B of  FIG. 5A  illustrating a fifth step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention. In  FIGS. 5A and 5B , highly doped first and second N-type regions  175  and  180  are formed in silicon layer  115 . A portion of first P-well  110 A region remains between second P-type region  170  and first N-type region  175  under spine  152  of gate stack  140  and remains between first N-type region  175  and second P-well region  110 B under second gate stack region  150 . A PN junction  182  separates the remaining second P-well region  110 B from first N-type region  175 . Second N-type region  180  is formed between first and second P-well regions  110 A and  110 B and abuts first N-type region  135  along an interface  183  and PN junctions  137  and  138 . 
     First and second N-type regions  175  and  180  may be formed by forming a patterned photoresist mask over silicon layer  115 , ion implanting an N-type dopant species into the silicon layer where the silicon layer is not protected by the photoresist mask or gate stack  140  and then removing the photoresist mask. 
     First and second N-type regions  175  and  180  may be formed by ion-implantation of phosphorus. The phosphorus ion-implantation may be performed through a thin oxide layer (not shown in  FIG. 5B ). In one example, first and second N-type regions  175  and  180  have a peak boron concentration between about 1E20 atoms/cm 3  and about 2E20 atoms/cm 3 . 
     Formation of first and second N-type regions  175  and  180  may be performed simultaneously with formation of the source/drains of CMOS NFETs used in the functional circuits of an integrated circuit to be protected by an SCR ESD protection device (herein after SCR)  185  whose fabrication is now essentially complete. 
     It should be understood that the various PN junctions  137 ,  138  and  182  and interfaces  172 ,  173  and  183  are illustrated under gate stack  140 . Even though edges of gate stack  140  are used to define PN junctions  137 ,  138  and  182  and interfaces  172 ,  173  and  183 , various heat cycles and other processes cause the dopants to diffuse under the gate stack. Also, structures such as sidewall spacers (well known in the art) on the sides of gate stack  140  may be present before or after the various ion implantations processes described but have not been shown for clarity. Sides of gate stack  140  project in a vertical plane perpendicular to the plane of the paper of, for example,  FIG. 5A . 
       FIG. 6  is a schematic diagram of an ESD protection circuit  190  according to an embodiment of the present invention. In  FIG. 6 , ESD protection circuit  190  includes SCR  185 , an I/O pad  195  and circuit(s)  200  of an integrated circuit to be protected. SCR  185  comprises a bipolar PNP transistor T 1 , an NPN bipolar transistor T 2  and first and second resistors R 1  and R 2 . A first terminal of resistor R 2  is connected to VDD and a second terminal of resistor R 2  is connected to the base of transistor T 1  and the collector of transistor T 2 . The emitter of transistor T 1  is connected to I/O pad  195  and circuit(s)  200 . The collector of transistor T 1  is connected to the base of transistor T 2  and a first terminal of resistor R 1 . A second terminal of resistor R 1  and the emitter of transistor T 2  are connected to ground. 
       FIG. 7A  is a plan view and  7 B is a cross-section through line  7 B- 7 B of  FIG. 7A  illustrating the ESD protection circuit of  FIG. 5  superimposed over SCR  185  illustrated in  FIGS. 5A and 5B . In  FIG. 7A , first transistor T 1  comprises first P-type region  165  and first P-well region  110 A as the emitter of transistor T 1 , N-well region  135  as the base of transistor T 1  and second P-well region  110 B as the collector of transistor T 1 . Second transistor T 2  comprises first N-type region  175  a as the emitter of transistor T 2 , second P-well region  110 B as the base of transistor T 2  and N-well region  135  as the collector of transistor T 2 . First P-type region  165  may be considered an anode and first N-type region  175  may be considered the cathode of SCR  185 . 
     Second P-type region  170  may be used to provide contact to first P-well region  110 B which is located under gate stack  140  as well as being lightly doped Second N-type region  180  may be used to contact N-well region  135  which is lightly doped. A wire contacting lightly doped silicon (i.e. less than about 1E18 dopant atm/cm 3 ) results in a high resistance contact, while a wire contacting highly doped silicon (i.e. greater than about 1E18 dopant atm/cm 3 ) results in a lower resistance contact. A metal silicide layer formed on the top surface of silicon regions, as is known in the art, may be used to further reduce contact resistance. Care must be taken to avoid shorts to gate stack  140 , for example, by forming dielectric spacers on the sidewalls of gate stack  140 . 
     In  FIG. 7B , it can be seen that first P-type region  165  is connected to I/O pad  195  and circuit(s)  200 . First N-type region  175  is connected to ground and N-well region  135  is connected to VDD. Connections to I/O  195 , circuit(s)  200 , VDD and ground are by wires or metal contact studs (not shown) contacting first P-type region  165 , and N-type region  180  (which is physically touching and electrically connected to N-well region  135 ) and first N-type region  175  respectfully. A metal silicide layer as described supra (not shown) may be formed on the top surfaces of first P-type region  165 , N-well region  135  and first N-type region  175  to ensure a low resistance contact (also known as an ohmic contact). Also resistor R 1  is seen to be the internal resistance of first N-type region  175  and resistor R 2  is seen to be the internal resistance of N-well  135 . 
     Gates  145  and  150  are not functional elements of SCR  185 . In one example, gates  145  and  150  are floating. In another example gates  145  and  150  are connected to ground. With gate  145  and  150  grounded, there will be some current leakage between N-well region  135  and first N-type region  175 . 
     Charge dissipation current flow in SCR  185  is from first P-type region  165  (the anode of the SCR) through first P-well region  110 A, N-well region  135 , second P-well region  110 B to first N-type region  175  along a current path  205 . Current path  205  is a single straight line current path in a first horizontal direction defined by line  7 B- 7 B and all planes parallel to a plane defined by the top surface of silicon layer  115 . Current flow in SCR  185  is only in a single horizontal direction as opposed to prior art SCR devices where the current must turn about 90° from emitter  1  to the base/collectors and another 90° from the base/collectors to emitter  2 . Thus, in the prior art devices, charge dissipation current is flowing in two different horizontal directions. The change in horizontal direction of current flow in prior art SCRs cause current crowding, limiting the amount of charge that can be dissipated. 
     The speed of turn on of SCR  185  is controlled by distance L (in the first horizontal direction between PN junction  137  and PN junction  138 : the larger the value of L, the slower the turn on of SCR  185 ; the smaller the value of L, the faster the turn on of SCR  185 . In one example L is between about 100 and 250 nm. W is the width (in the second horizontal direction) of N-well region  135  and along with the depth D (in a vertical direction) and the doping concentration of the N-well region controls the amount of current SCR  185  can carry. W, L and D are mutually orthogonal. 
       FIG. 8  is a simulated lateral profile of an SCR ESD protection device according to the embodiments of the present invention. The term lateral direction refers to a direction parallel to the first horizontal direction (and not to the second horizontal direction) as described supra. A peak concentration is a maximum doping concentration in a given region. A net doping concentration is the difference between the doping concentrations of a first dopant type and a second and opposite dopant type, the concentration of the first dopant type being greater than the concentration of the second dopant type. Thus, a net peak doping concentration is the maximum difference between the doping concentration of a first dopant type less the doping concentration of a second dopant type, the concentration of the first dopant type being greater than the concentration of the second dopant type. The concentration of the second dopant type may be zero. The terms doped P-type or doped N-type should be understood to mean net doping. For example, a region having both N- and P-type dopants, with a higher concentration of N-type dopant than P-type dopant would be considered to be doped N-type and vice versa. 
     In  FIG. 8 , curve  210  represents an approximate and exemplary lateral doping profile for SCR  185  of  FIG. 7A . Point  215  marks the PN junction between the portions of SCR  185  formed from P-type region  165  and first P-well region  110 A (see  FIG. 7A ) and N-well region  135  (see  FIG. 7A ). Point  220  marks the PN junction between the portions of SCR  185  formed from N-well region  135  (see  FIG. 7A ) and P-well region  110 B (see  FIG. 7A ). Point  225  marks the PN junction between the portions of SCR  185  formed from P-well region  110 B (see  FIG. 7A ) and N-type region  175  (see  FIG. 7A ). 
     In one example, the peak doping concentrations of P-type region  165  and N-type regions  175  are advantageously each greater than a peak doping concentration of N-well region  135  and a peak doping concentration of P-well region  110 B. In one example, the peak doping concentration of P-well region  110 B is advantageously greater than the peak doping concentration of N-well region  135 . In one, example, the peak doping concentrations of P-type region  165  and N-type regions  175  are advantageously each at least two orders of magnitude greater than the peak doping concentrations of both said P-well region  110 B and said N-well region  135 . 
     Thus, the embodiments of the present invention provide an SCR device for ESD protection in integrated circuits fabricated on silicon-on-insulator SOI substrates. 
     The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.