Abstract:
A pulse signal amplifier is disclosed which includes at least an emitter follower type drive stage consisting of a pair of complementary transistors and a field effect transistor connected to the drive stage and ON/OFF controlled thereby. A capacitive element is connected between the collectors of the complementary transistors and a pulse current signal source is provided to supply a charge current to the capacitive element and a drive current to the complementary transistors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a pulse signal amplifier, and is directed more particularly to a pulse signal amplifier in which a power supply circuit for a drive stage is simplified. 
     2. Description of the Prior Art 
     In a prior art pulse signal amplifier having an FET (field effect transistor) as the final stage amplifying element, in order to drive the FET at a high speed there is provided a drive circuit which consists of a pair of complementary transistors connected in an emitter-follower configuration. In this case, a power supply circuit for the drive circuit is provided separately from a power supply circuit to the final stage amplifying element so as to avoid that the fluctuation in the power supply source at the final stage affects on the drive stage. 
     However, when the power supply circuits are provided separately for the final stage and the drive stage as in the prior art, the circuit construction becomes complicated and the circuit becomes expensive. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a pulse signal amplifier free from the defect inherent to the prior art. 
     It is another object of the invention to provide a pulse signal amplifier in which a part of a pulse current signal driving a driving circuit is charged in a capacitor and the voltage thereacross is used as a DC voltage source for the drive stage. 
     In accordance with an aspect of the present invention, a pulse signal amplifier is provided, which includes a pulse current signal source, an impedance transfer circuit consisting of first and second transistors each having first, second and third electrodes, the first electrodes of which are connected to each other and supplied with the output of the pulse current signal source and the second electrodes of which are connected to each other, a field effect transistor having gate, source and drain electrodes, the gate electrode of which is connected to the connection point of the second electrodes of said first and second transistors, the drain and source electrodes of which are connected between a DC voltage source and a reference point through a load, the pulse signal amplifier being characterized by a capacitive element having a pair of first and second terminals, the first terminal of which is connected to the third electrode of the first transistor and the second electrode of which is connected to the third electrode of the second transistor and to the reference point, and a switching element connected between the output of the pulse current signal source and the third electrode of the first transistor so as to carry a part of the output current of the pulse current signal source to the capacitive element to charge the same when the gate current of the field effect transistor is not supplied through the third and second electrodes of the first transistor. 
     The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like reference numerals and letters designate the same elements. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a prior art pulse signal amplifier; 
     FIG. 2 is a circuit diagram showing an example of the pulse signal amplifier according to the present invention; 
     FIGS. 3A to 3D are waveform diagrams used for explaining an operation of the pulse signal amplifier of the invention shown in FIG. 2; and 
     FIG. 4 is a circuit diagram showing another example of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In order to better understand the present invention, a prior art pulse signal amplifier will be described firstly with reference to FIG. 1. In this prior art amplifier by way of example, there is provided an insulating gate type field effect transistor Q 1a  (in this example, an N-channel enhancement type MOS FET (field effect transistor) which forms an amplifier of a common source circuit type. A source of the transistor Q 1a  is grounded and its drain is connected to a voltage source +B through a load registor R 2a  and to an output terminal t. 
     There is also provided an impedance transfer circuit 3a consisting of transistors. In this case, the impedance transfer circuit 3a is formed of an emitter-follower configulation type complementary push-pull circuit using bi-polar transistors Q 2a  (PNP-type) and Q 3a  (NPN-type). In this case, in place of the bi-polar transistor an FET can be used. This impedance transfer circuit 3a is supplied with an operating voltage from a DC voltage source E a . In detail, the collector of the transistor Q 3a  is connected to the positive terminal of the voltage source E a  which is grounded at its negative terminal. The emitter of the transistor Q 3a  is connected to the emitter of the transistor Q 2a  whose collector is grounded. The output side of the impedance transfer circuit 3a i.e. connection point between the emitters of the transistors Q 2a  and Q 3a  is connected to the gate of the transistor Q 1a . 
     There is further provided a pulse current signal source 2a formed of PNP-type bi-polar transistor Q 4a  whose emitter is connected through a resistor R 2  to the voltage source +B and of a pulse source 1 which is connected at its one end to the base of the transistor Q 4a  and at its other end to the voltage source +B. The collector of the transistor Q 4a  in the pulse current signal source 2a is grounded through a resistor R 1a  and also commonly connected to the bases of the transistors Q 2a  and Q 3a  in the impedance transfer circuit 3a. 
     In the above prior art pulse signal amplifier, the DC voltage source E a , which supplies the DC voltage to the impedance transfer circuit 3a as the operating voltage, is separate from the voltage source +B for the transistor Q 1a , so that this prior art pulse signal amplifier is complicated in circuit construction and hence expensive. 
     Now, the present invention free from the defect of the prior art will be hereinafter described with reference to the attached drawings. 
     An example of the pulse signal amplifier according to the present invention will be described with reference to FIG. 2 in which the reference numerals corresponding to those used in FIG. 1 designate the same elements, respectively, and their detailed description will be omitted. 
     In the example of the invention shown in FIG. 2, a voltage source circuit 4a, which is a parallel circuit consisting of a capacitor C a  (for example, having the capacity of 10 μF) and a Zener diode D za  as a constant voltage element, is connected to the pulse current signal souce 2a in the pulse signal amplifier in place of the voltage source E a  used in the piror art, and the output from the voltage source circuit 4a is applied to the impedance transfer circuit 3a as the operating voltage. That is, the collector of the transistor Q 3a  is grounded through the capacitor C a  and connected to the cathode of the Zener diode D za  whose anode is in turn grounded. The collector of the transistor Q 3a  is also connected to that of the transistor Q 4a  through a diode D 2a . 
     An operation of the pulse signal amplifier of the invention shown in FIG. 2 will be described with reference to the waveforms illustrated in FIGS. 3A to 3D. A pulse current or rectangular current I 1 , which is developed from the pulse current signal source 2a and has the waveform shown in FIG. 3A and the frequency of, for example, 500 KH z , is divided into a current I 2 , which flows to the resistor R 1a  and to the bases of the transistors Q 2a  and Q 3a  and whose waveform is shown in FIG. 3B, and into a current I 3 , which flows through the diode D 2a  to the voltage source circuit 4a mainly and whose waveform is shown in FIG. 3C. A current I G  flowing to the gate G of the transistor Q 1a  has such a waveform as just formed by differentiating the rectangular current I 1  shown in FIG. 3A, as illustrated in FIG. 3D. This is caused by the input capacities (of for example, about 1000 pF) existing between the gate and drain and between the gate and source of the transistor Q 1a . Since the current I G  has the above waveform, the waveforms of the current I 2  and I 3  are not rectangular as that of the current I 1  but of waveforms such as shown in FIGS. 3B and 3C, respectively. The value of the current I 2  at its flat portion is expressed by (V x  +V d )/R 1a  if it is assumed that the DC voltage of the voltage source circuit 4a is taken as V x , the forward voltage drop of the diode D 2a  is taken as V d , and the resistance of the resistor R 1a  is taken as R 1a , respectively. 
     Therefore, when the transistor Q 4a  is in ON-state and the transistor Q 3a  is in OFF-state or period T c  in FIG. 3D, the capacitor C a  is charged by the current I 3  (=I 1  -I 2 ). The voltage across the capacitor C a  can be used as the voltage source of the impedance transfer circuit 3a. In this case, if the mean value of a partial current of the current I 3 , which is used to charge the capacitor C a , is selected greater than the mean value of the positive portion of the current I G , the potential at the collector of the transistor Q 3a  can be kept substantially constant. In the example of the invention shown in FIG. 2, the Zener diode D za  is provided so as to prevent the voltage across the capacitor C a  from being increased unnecessarily. 
     Thus, the field effect transistor Q 1a  is turned ON and OFF in response to the polarity of the pulse source 1 of the pulse current signal source 2a, and an amplified output pulse is delivered to the output terminal t. 
     In the example of the invention shown in FIG. 2, the enhancement type MOS FET is used as the FET Q 1a , but in place thereof a depression type MOS FET or triode characteristic FET can be used. 
     Another example of the invention will be now described with reference to FIG. 4, in which the parts or elements corresponding to those in FIG. 2 are marked with the same reference numerals and letters and their detailed description will be omitted. 
     The example of the invention shown in FIG. 4 is the case where the present invention is applied to a complementary push-pull type MOS FET pulse signal amplifier so that two amplifier circuits each being substantially same as that shown in FIG. 2 are used. In this case, a PWM (pulse width modulated) signal source is used as the pulse signal source. 
     In FIG. 4, transistors Q 1a  and Q 1b  are respectively insulating gate typefield effect transistors of an N-channel and a P-channel types (in the illustrated example, enhancement type MOS FETs) and the MOS FETs are each connected in a common source configuration circuit. That is, the sources of the respective transistors Q 1a  and Q 1b  are connected to the voltage sources -B and +B and the drains thereof are connected together to the output terminal t to which a load 6 is connected. 
     The impedance transfer circuit 3a and the voltage source circuit 4a for the transistor Q 1a  are formed similar to those of FIG. 2. In this case, in place of the resistor R 1a  used in FIG. 2, an SRPP (shunt regulated push-pull) circuit 5a is provided as an active load which will be described later. That is, the SRPP circuit 5a is formed of a PNP-type bi-polar transistor Q 5a , a diode D 1a  connected between the base and emitter of the transistor Q 5a  and a resistor R 3a  connected between the base and collector of the transistor Q 5a . The base of the transistor Q 5a  is further connected to the collector of the transistor Q 4a , the collector of the transistor Q 5a  is connected to the voltage source -B and the emitter thereof is connected to the commonly connected bases of the transistors Q 2a  and Q 3a , respectively. 
     Since the pulse current signal source, the impedance transfer circuit, the voltage source circuit and the SRPP circuit for the other transistor Q 1b  are substantially same as those for the transistor Q 1a , they are marked with the corresponding reference with the suffix b in place of a and their detailed description will be omitted. In this case, the conductivity and the connection polarity of the transistors and the connection polarity of the diodes in the two amplifier circuits are selected opposite. The pulse source 1 (which is such a pulse source, whose pulse width is to be modulated and which has the carrier frequency of, for example, 500 KH z ) is connected between the commonly connected bases of the transistors Q 4a  and Q 4b  and the ground. 
     In the example of FIG. 4, it is possible that, at the base side of the transistors Q 3a  and Q 2a  and similarly at the base side of the transistors Q 3b  and Q 2b , there is additionally provided a diode in the same direction as the diode D 1a  and diode D 1b , respectively. 
     Next, an operation of the example of the invention shown in FIG. 4 will be now described. During the negative half cycle of the pulse source 1, the transistor Q 4a  turns ON and hence the current I 1  flows out from the collector of the transistor Q 4a . This current I 1  is divided into the current I 3  to the diode D 2a  and the current I 2  to the resistor R 3a  as set forth above. A part of the current I 2  flows through the diode D 1a  to the base of the transistor Q 3a  in the impedance transfer circuit 3a, so that the transistor Q 3a  becomes ON. When the diode D 1a  becomes ON, the base-emitter of the transistor Q 5a , which forms the SRPP circuit 5a together with the diode D 1a  and the resistor R 3a , is reverse-biased and hence the transistor Q 5a  turns OFF. Due to the conduction of the transistor Q 3a , the input capacity of the FET Q 1a  is charged by the current I G  (its positive portion) shown in FIG. 3D and then the FET Q 1a  turns ON. Thus, at the output terminal t there is developed the voltage -B. In this case, during the interval T c  shown in FIG. 3D, the capacitor C a  is charged by the current I 3 , and accordingly it serves as the voltage source for the impedance transfer circuit 3a. 
     When the transistor Q 4a  is in OFF-state, the base-emitter of the transistor Q 5a  is biased in the forward direction and hence the transistor Q 5a  turns ON (diode D 1a  turns OFF). Thus, at this time the transistor Q 2a  is made ON, so that the input capacity of the FET Q 1a  is discharged and hence the FET Q 1a  becomes OFF. 
     During the positive half cycle of the pulse source 1, the similar operation to that described above is carried out by the other amplifier circuit and hence the other FET Q 1b  turns ON with the result that at the output terminal t there is developed the voltage +B. 
     According to the present invention, the output side of the impedance transfer circuit, which consists of transistors, is connected to the gate of the insulating gate type FET, which forms the common source configuration type amplifier, and the pulse current signal source is connected to the input side of the impedance transfer circuit. Thus, in the invention there is no need to provide a separate voltage source to the impedance transfer circuit from the FET. As a result, the pulse signal amplifier of the present invention is simple in circuit construction and inexpensive. 
     It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention so that the spirits or scope of the invention should be determined by the appended claims only.