Abstract:
An environment sensing/control circuit for use in conjunction with an electronic subsystem. The invention is capable of sensing and controlling conditions of the environment of the subsystem. The invention is capable of being implemented as a stand-alone device or replicated numerous times in an integrated circuit. The invention identifies changes including intermittent changes, in the environment of the subsystem from a reference state, the reference state being dynamically determined by a processor. Upon detecting such a change, the invention signals the processor. The invention can also serve as a flexible interface for control signals from the processor to the subsystem.

Description:
This is a continuation of application Ser. No. 07/806,603, filed on Dec. 12, 1991, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an environment sensing/control circuit for an electronic subsystem, and more particularly, to a dual-mode circuit for controlling an electronic subsystem and for detecting intermittent errors in such a subsystem. 
     2. Description of Related Art 
     Modern electronic systems often comprise subsystems containing various components. Reliable operation of the subsystems is often essential to the operation of the systems in which they operate. For example, an on-line transaction processing (OLTP) computer system may include a data storage subsystem which must be highly reliable in order to minimize the possibility of data loss and system failure (&#34;downtime&#34;). In order to provide the most reliable operation for such subsystems, some systems are designed with processors which are capable of sensing and controlling the environment of the associated subsystems. In this way, the system has positive control over its environment, and can activate redundant or back-up systems if a failure occurs, or indicate the occurrence and location of faults for quick repair and recovery. 
     FIG. 1 shows a prior art system comprising an electronic subsystem 1, containing a variety of controllable elements, such as disk drives 2, power supplies 3, and fans 4, as well as a number of sensors, such as temperature sensors 5. Other sensors may be placed within the disk drives 2, power supply 3, and fans 4 for indicating the operational state of those components. 
     A plurality of analog signal lines 10 couple the sensors and controllable elements within the subsystem 1 to an analog controller 11, which contains suitable electronic elements (such as controllable switches to activate and deactivate controllable elements and digital-to-analog converters) for control purposes, and sensing circuits (such as analog-to-digital converters) necessary to process the signals transmitted on the signal lines 10. As shown in FIG. 1, some of the signal lines 10 comprise a single conductor (such as the control lines between each temperature sensor 5 and the analog controller 11), while others actually comprise two conductors, one to carry an activation signal from the analog controller 11 to a controllable element (such as the disk drive 2) and the other to carry a verification signal back to the analog controller 11 as an indication that the controllable element has properly responded to the activation signal. 
     The analog controller 11 is also configured to directly communicate with digital circuitry. Each control line and each sensing line coupled to the analog controller typically has a corresponding digital signal line 12. Typically, to actuate a controllable element within the subsystem 1, the corresponding digital signal line 12 is set to a logical state. The analog controller 11 provides an analog output in direct response to the logical state of each corresponding digital input. Similarly, the analog controller 11 provides a digital output corresponding to each analog input. 
     It is possible to couple the digital signal lines 12 directly to a central processing unit (CPU) 13, thereby permitting the CPU 13 to monitor the digital signal outputs of the analog controller 11, and provide digital signal inputs to the analog controller 11. However, to do so would require the CPU to constantly monitor the digital signal line 12. For many applications, this would constitute a waste of processor resources. Accordingly, it has been known to provide an environment sensing/control circuit 14 as an intermediate circuit between the CPU 13 and the analog controller 11. The purpose of the environment sensing/control circuit 14 is to latch control signals from the CPU 13, provide such latched signals as digital inputs to the analog controller 11, sense digital inputs from the analog controller 11, and provide an indication to the CPU 13 of changes in such conditions. 
     FIG. 2 is a schematic diagram of a prior art environmental sensing/control circuit. The circuit actually comprises two distinct sections, a control section and a sensing section. Both sections are coupled to the CPU 13 by a processor bus 21, which may be a standard bus. The major elements of both sections are individually addressable by the CPU 13 by supplying an address which is decoded (the decoder is not shown, but is conventional) such that individual &#34;enable&#34; lines would be coupled to each such major element. In addition, the major elements of both sections are coupled to data input and output lines on the bus 21 for communication with the CPU 13. 
     In FIG. 2, the control section comprises a control memory register 22, which may be simply a D-type flip-flop. When the control memory register 22 is addressed by the CPU 13, the CPU 13 can provide a logical &#34;0&#34; or a logical &#34;1&#34; on the bus 21 as the input to the control memory register 22 to be &#34;latched&#34; within the control memory register 22. The output of the control memory register 22 is provided on a control output connection 23, which would be directly coupled over a digital input signal line 12 to the analog controller 11. 
     For reliability purposes, the control memory register 22 is provided with an addressable driver 22&#39; which permits the output of the control memory register 22 to be coupled back onto the bus 21 so that the CPU 13 can verify that its input to the control memory register 22 was, in fact, latched. This capability is referred to in the art as &#34;read after write&#34; verification. 
     In use, the CPU 13 would address the control memory register 22 and set a logical &#34;0&#34; or logical &#34;1&#34; into the control memory register 22. If desired, the CPU 13 would then read the output of the control memory register 22 by means of the associated driver 22&#39;. The output of the control memory register 22 is coupled by output connection 23 to the analog controller. For example, if the CPU 13 commanded that a disk drive 2 within the subsystem 1 be powered up, the control section of an environment sensing/control circuit 14 corresponding to the selected disk drive 2 would be addressed by the CPU 13, and the logical value corresponding to &#34;power-up&#34; (e.g., logical &#34;1&#34;) would be stored in the corresponding control memory register 22. The output of the control memory register 22 would be converted by the analog controller 11 to a suitable signal to cause power to be provided to the selected disk drive 2. 
     The sensing section shown in FIG. 2 is somewhat more complex than the control section. Digital condition signals from the analog controller 11 are provided as an input to the sensing section via an environmental condition input connection 24, which is coupled to a sensing driver 25. The CPU 13 can directly monitor the condition signal on connection 24 by selecting an addressable direct input driver 25. 
     The digital condition signal on input connection 24 is also provided to a two-input exclusive-OR (XOR) gate 26, which functions as a comparator. The other input of the XOR gate 26 is provided by a reference memory register 27, which again may be a D-type flip-flop. The reference memory register 27 has an associated driver 27&#39;, to provide a &#34;read after write&#34; verification capability. The input to the reference memory register 27 is provided by the CPU 13. The reference memory register 27 latches its input and provides that value as an input to the XOR gate 26. The output of the XOR gate 26 is coupled to a tri-statable driver 28, which is coupled to the processor bus 21. 
     In operation, the CPU 13 sets a value in reference memory register 27, the output of which is constantly compared with the condition signal on input connection 24. This configuration permits the CPU 13 to set a reference value in the reference memory register 27, and detect any changes or &#34;exceptions&#34; of the condition signal on input connection 24 from that reference value. For example, if the condition signal on input connection 24 represents a temperature state as monitored by the analog controller 11, and has a value of &#34;0&#34; when the temperature is within normal operating limits and a value of &#34;1&#34; when a corresponding temperature sensor 5 within the subsystem 1 detects an out-of-limit condition, the CPU 13 might latch a logical &#34;0&#34; into the reference memory register 27. The output of the XOR gate 26 would, therefore normally be a &#34;0&#34; when the condition signal on input 24 is also a &#34;0&#34; (indicating normal temperature), and would change to a logical &#34;1&#34; if the condition signal on input connection 24 differs in value from the reference signal stored in reference memory register 27. If, on the other hand, the condition being monitored was &#34;valid voltage level present&#34; in a disk drive 2, the normal condition might be a logical &#34;1&#34; and failure would be a logical &#34;0.&#34; In this case, a &#34;1&#34; would be latched into the reference memory register 27. 
     It should be clear from the description above that every control line to the analog controller 11 and every sensing line from the analog controller 11 requires a dedicated control section or sensing section of the type shown in FIG. 2. Thus, for a plurality of digital signal lines 12, a plurality of circuits of the type shown in FIG. 2 would be required. It is possible for the CPU 13 to be configured so as to poll all of the control and sensing sections of a plurality of environment sensing/control circuits. However, it is known to instead use an interrupt technique to provide a single signal to the CPU 13 to indicate that the CPU 13 needs to determine which of a plurality of environment sensing/control circuits has detected an &#34;exception&#34; to a reference signal. Therefore, a &#34;global&#34; OR gate 29 is provided, coupled to the output of each sensing section XOR gate 26 for the plurality of environmental sensing/control circuits. Thus, whenever any of the sensing sections indicates an exception from a reference state, an interrupt request (IRQ) signal is provided by OR gate 29 to the CPU 13. The CPU 13 may then invoke an interrupt routine designed to address each environmental sensing/control circuit individually to detect which XOR gate 26 indicates an exception to a reference state. 
     A number of problems exist with the prior art environment sensing/control circuits. A principal problem is that the CPU 13 may not respond to an IRQ signal in a sufficiently timely manner to check all of the individual sensing sections of the environment sensing/control circuits before the condition which caused the interrupt signal to become active returns to its &#34;non-exception&#34; state. This is problematic for at least three reasons. The first is that time can be wasted checking each sensing section to determine which caused the interrupt; processing resources are therefore wasted. The second reason is that an intermittent condition which should have been identified can go undetected, thereby reducing the reliability of the subsystem 1 as a whole. The third reason is that interruptions of the CPU 13 in response to intermittent signals can interfere with other operations which the CPU 13 must perform. 
     Another problem that can occur with the prior art is that once an exception condition exists within the sensing section of an environment sensing/control circuit, the CPU 13 has no means for controllably deactivating the sensing section. Under certain conditions, the CPU 13 may wish to ignore some exception conditions, while still retaining the ability to monitor other exception conditions. The prior art environment sensing/control circuits provide no means for accomplishing this function. 
     Yet another problem which exists in the prior art is that the input logic convention of the analog controllers 11 is sometimes not consistent. Some analog controllers require a low voltage level input to indicate a logical &#34;1&#34;, while other analog controllers require a high voltage level input to indicate a logical &#34;1.&#34; This lack of uniformity makes it more difficult for a programmer to use a uniform polarity convention when writing program code which instructs the CPU 13. A similar problem exists with respect to digital output signals from an analog controller 11. 
     A further problem of the prior art is that the control section and sensing section of the environment sensing/control circuit each require a dedicated signal line. When implementing such a circuit in an integrated circuit, it may be difficult to predict in advance how many control sections and how many sensing sections are required for a particular application. In addition, economics dictate that an integrated circuit have as few signal pins as possible. Therefore, the prior art is not flexible in providing a good match between the number of control sections and the number of sensing sections required for a variety of applications, while minimizing the number of pins in an integrated circuit implementation. 
     Therefore, it is desirable to provide an environment sensing/control circuit which has means for (1) detecting intermittent error conditions in order to allow a processor to detect which condition among many has caused an exception, (2) selectively and dynamically permitting control of the input and output polarity convention of the circuit, (3) selectively preventing changes in the environmental conditions from generating an interrupt signal, and (4) providing maximum flexibility in configuring control and sensing sections, while minimizing the number of signal lines or pins required for the circuit. 
     The present invention provides such an environment sensing/control circuit. 
     SUMMARY OF THE INVENTION 
     The present invention is capable of sensing and controlling the condition of the environment of an electronic subsystem. Furthermore, the invention is capable of being implemented as a stand-alone device or being replicated numerous times in an integrated circuit (IC). 
     A typical system in which the invention is used comprises a plurality of electronic subsystems, a central processing unit (CPU) which controls and monitors the electronic subsystems, an analog controller, and the inventive environment sensing/control circuit. 
     The invention identifies changes in digital condition signals, representing the environment of an electronic subsystem, from a reference state. The reference state can be dynamically set by the CPU. Additionally, the invention when replicated, can monitor several conditions simultaneously. Further, the invention can record and indicate which conditions being monitored, including conditions which are intermittent, have changed. Upon detecting a change, the invention signals the CPU that the change has occurred. The invention also serves as a programmable interface for control signals from the CPU to the analog controller. 
     The invention permits very inexpensive and flexible environment sensing and control to be achieved, due to the ease with which it can be reconfigured and inexpensively replicated in an IC. 
     In the preferred embodiment of the invention, memory registers are provided for storing reference states set by the CPU. Additional memory registers are provided for storing flags which indicate that the state of a particular condition being monitored in the subsystem is different from the reference state. One flag is provided for each condition that is being monitored. By setting a flag in a memory register, a change from the reference state by the condition being monitored can be detected by the CPU at a later time. In this way, a change can be detected even if the monitored condition returns to the reference state before the CPU has had an opportunity to identify which particular condition changed. 
     The preferred embodiment of the invention also incorporates a memory register which may be externally and dynamically programmed to determine whether changes in a particular environmental condition are to be reported to the CPU. This is accomplished by suppressing the output of a comparator that detects when the condition is different from the reference. However, even upon selecting to suppress the comparator output, changes in the condition are nonetheless recorded by the invention and may be made available to the CPU at a later time. 
     Additionally, the preferred embodiment has all the necessary circuitry to either sense changes in the environment of a subsystem or send control signals to the subsystem. The determination as to whether the invention is used to sense or control the environment is made by a command to the invention from the CPU. In the preferred embodiment, a single port is used for both the sensing function and the controlling function. The invention may, however, be configured to provide a separate port for each function. When so configured, sensing and controlling can be done simultaneously by the same circuit. 
     When programmed to operate in a &#34;control mode&#34; of operation, the invention accepts inputs from a CPU. These inputs are stored in a register and then applied to a subsystem for the purpose of causing some change in the condition of the subsystem in response to information received by the CPU. 
     Whether the invention utilizes the conventions of positive or negative logic for I/O signals in either a &#34;sense mode&#34; or the control mode can be programmed by an input applied to the invention. When positive logic is selected, a logical &#34;1&#34; state is indicative of an active condition and a logical &#34;0&#34; is indicative of an inactive condition. When negative logic is selected, a logical &#34;0&#34; state is indicative of an active condition and a logical &#34;1&#34; is indicative of an inactive condition. 
     An additional feature of the preferred embodiment is that all memory registers which are programmable by the CPU can be read back by the CPU. This allows positive confirmation that information has been properly written to each memory register. 
     Further aspects of the present invention will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. It should be understood, however, that the detailed description and the specific examples, while representing the preferred embodiment of the invention, are given by way of illustration only. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a prior art environment sensing/control circuit used with a processor and electronic subsystem. 
     FIG. 2 is a detailed schematic of a prior art environment sensing/control circuit. 
     FIG. 3 is a detailed schematic diagram of the inventive environment sensing/control circuit. 
     FIG. 4 is a block diagram of the invention having a single output connection. 
     FIG. 5 is a block diagram of the invention as used with an analog controller having latched control inputs. 
     Like reference numbers in the various drawings refer to like elements. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best presently contemplated modes of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. 
     The inventive environment sensing/control circuit accepts the same inputs and outputs as the environment sensing/control circuits which are presently known in the prior art. In this way, the invention can be retro-fitted into existing systems. Therefore, FIG. 1 will be referenced when the following discussion refers to the components of the system external to the invention. 
     FIG. 3 is a detailed schematic of the inventive environment sensing/control circuit. The invention is divided into two distinct sections, a control section and a sensing section. Both sections are coupled to a CPU 13 (refer to FIG. 1) by a processor bus 21, which may be a standard bus similar to the bus 21 shown in FIG. 2 described above. In the preferred embodiment, the invention is fabricated in an integrated circuit (IC). However, it is equally acceptable to have the circuit built from discrete components. 
     The control section comprises a control memory register 22 and an associated addressable driver 22&#39;, which are connected and which operate in a manner similar to the corresponding elements shown in FIG. 2 described above. The control section further comprises an output exclusive-OR (XOR) gate 30, an output polarity memory register 31, an associated addressable driver 31&#39;, and an addressable output driver 32. The outputs of the control memory register 22 and the output polarity memory register 31 are coupled to the output XOR gate 30 as shown in FIG. 3. 
     The input to the output polarity memory register 31 is coupled to the processor bus 21 and can be &#34;latched&#34; when addressed by the CPU 13 by a procedure similar to the procedure implemented to latch data into the control memory register 22 of FIG. 2. The associated addressable driver 31&#39; allows the CPU 13 to perform &#34;read after write&#34; verification. 
     The output polarity memory register 31, in conjunction with the output XOR gate 30, creates a programmable inversion means which operates to cause the output of the control memory register 22 to be inverted when the output of the output polarity memory register 31 is a logical &#34;1.&#34; The output of the control memory register 22 passes through the output XOR gate 30 unaltered when a logical &#34;0&#34; is latched into the output polarity memory register 31. In this way, a control signal from the CPU 13 which is latched into the control memory register 22 can be selectively inverted by a command to the invention which is latched into the output polarity memory register 31. This capability allows standard software modules to be encoded which will be applicable to any analog controller 11 or any controllable element of a subsystem which is coupled to the invention, regardless of the polarity convention of the coupled device. 
     The output driver 32 coupled to the output XOR gate 30 allows the control section of the invention to be buffered from a control output connection 23. By buffering the control section from the output connection 23, both the sensing section (described below) and the control section of the invention may share the same port or pin. 
     The sensing section includes an input section that comprises a direct input driver 25, an exception XOR gate 26, a reference memory register 27, an associated driver 27&#39;, an addressable exception state driver 28, and an interrupt OR gate 29 connected as shown in FIG. 3. These components of FIG. 3 perform functions similar to the functions performed by the corresponding components shown in FIG. 2 and described above. Thus, the reference memory register 27 latches data provided by the CPU 13 via the bus 21 when the reference memory register 27 is properly addressed. The data so provided determines a reference value to be compared against a condition signal provided to the invention at an environmental condition input connection 24 from an analog controller 11 (refer to FIG. 1). The comparison is provided by the exception XOR gate 26, the output of which is coupled (through an AND gate 36, described below) to the exception state driver 28, which in turn is coupled to the bus 21. The output of the exception XOR gate 26 is coupled to the interrupt OR gate 29, which provides an interrupt request (IRQ) signal to the CPU 13 upon the occurrence of a exception condition. 
     Additionally, an input XOR gate 34 is present in the invention, and is coupled to the direct input driver 25 as shown in FIG. 3. The input XOR gate 34 is coupled to the output from an input polarity memory register 35, and to the input connection 24. The input polarity memory register 35, like the output polarity memory register 31, latches data from the bus 21 when properly addressed. An associated driver 35&#39; provides a &#34;read after write&#34; verification capability. When a logic &#34;1&#34; is latched into the input polarity memory register 35, the input signal provided to the invention by the analog controller 11 at input connection 24 is inverted by the input XOR gate 34. When a logic &#34;0&#34; is latched into the input polarity memory register 35, the input condition signal passes through the input XOR gate 34 unaltered. The input polarity memory register 35 thus provides the capability to adapt the invention to analog controllers which utilize either a negative or positive logic convention. 
     As shown in FIG. 3, a programmable switching means is provided by the two-input AND gate 36 and an interrupt (IRQ) disable memory register 38. The AND gate 36 allows the output of the exception XOR gate 26 to be provided to the input of the exception state driver 28, the input of the interrupt OR gate 29, and to the input of an IRQ memory register 37, whenever the second input to the AND gate 36 is at a logic &#34;1&#34; state. The second input to the AND gate 36 is coupled to the IRQ disable memory register 38, the input of which is coupled to the processor bus 21. An associated driver 38&#39; provides &#34;read after write&#34; verification capability. 
     The inclusion of this circuit in the invention allows the CPU 13 to prevent unwanted IRQ signals from distracting the CPU 13 from executing more essential routines, and permits the CPU 13 to detect subsequent interrupts which are channeled through the same interrupt OR gate 29 by other environment sensing/control circuits. It is particularly important that the CPU 13 have the ability to disable inputs to the interrupt OR gate 29 after they have been acknowledged. Otherwise, if a condition that caused an exception signal input to the interrupt OR gate 29 persists after the CPU 13 has acknowledged the existence of the condition, subsequent changes detected by any other environment sensing/control circuits will go undetected by the CPU 13. 
     As noted above, the exception state driver 28 provides a signal to the CPU 13 which indicates the result of the comparison between the reference value in reference memory register 27 and a condition signal from the input connection 24. In response to the IRQ signal generated as a result of an exception condition, the CPU 13 can poll the environment sensing/control circuits and determine the current state of the condition as indicated by either the exception signal, which is made available to the processor by addressing the exception state driver 28 or the condition signal, which is made available to the processor by addressing the direct input driver 25. However, this ability to monitor an input condition signal for an exception does not reliably detect intermittent changes to a condition signal. Therefore, also made available to the CPU 13 is the exception signal value latched into the IRQ memory register 37, the output of which is coupled to the bus 21. The IRQ memory register 37 latches the output of the AND gate 36 upon a transition from a logic &#34;0&#34; to a logic &#34;1&#34; of the output from the interrupt OR gate 29. By latching the exception signal which is output by the AND gate 36, the CPU 13 can identify which condition signal has deviated from the reference value against which the condition signal is compared, even when the condition signal returns to its original state before the CPU 13 has had an opportunity to address each environment sensing/control circuit to determine which one caused the IRQ signal to the CPU 13. 
     Additionally, the output of the interrupt OR gate 29 is coupled to a Set/Reset (S/R) flip-flop 39, which captures any transition from a logic &#34;0&#34; to a logic &#34;1&#34; by the output of the interrupt OR gate 29. This gives the CPU 13 a single latched indication that at least one exception condition has occurred. The reset input to the (S/R) flip-flop 39 is coupled to the Bus 21 and is under the control of the CPU 13. In this way the CPU 13 may reset the S/R flip-flop 39 upon acknowledging a set condition. Alternatively, the S/R flip-flop can be reset automatically after the CPU 13 reads the IRQ status, by connecting the reset input of S/R flip-flop 39 to the address line (not shown) associated with the IRQ memory register 37. Also, as in FIG. 2, the direct input driver 25 of FIG. 3 provides direct information regarding the status of the environmental condition to the CPU 13 via the bus 21. 
     Thus, the preferred embodiment of the invention, as described above, provides an environment sensing/control circuit which has means for detecting intermittent exception conditions in order to allow a processor to detect which condition signal, among many, has caused an exception signal to be created. The environment sensing/control circuit also has means for selectively and dynamically permitting control of the input and output polarity convention of the circuit, and selectively preventing changes in the environmental conditions from generating an interrupt signal. 
     In addition, the circuit shown in FIG. 3 can be implemented such that a single input/output (I/O) pin is used. In such an embodiment, input connection 24 and output connection 23 are &#34;wired&#34; together (as indicated by the dotted line in FIG. 3) and a single I/O pin 39 as shown in FIG. 4 is used to interface the sensing/control circuit 14&#39; to the analog controller 11. When the circuit is in a &#34;control mode,&#34; the output driver 32 is enabled, permitting the output of the control memory register 22 to determine the signal level that appears on the single I/O pin 39. When the circuit is used in a &#34;sense mode,&#34; the output driver 32 is disabled (i.e., placed into high impedance mode), and the I/O pin 39 is used to conduct signals from the analog controller 11 to the sensing section of the circuit 14&#39;. Because the I/O pin 39 can be used as either an input connection or an output connection, the sensing/control circuit can be replicated numerous times in an integrated circuit, and the determination as to whether the integrated circuit that forms a complete sensing/control circuit is used in a control mode or a sensing mode can be made under processor control. In this way, the number of pins dedicated to output control purposes and the number of pins dedicated to input sensing purposes can be dynamically configured for each particular application. Alternatively, as shown in FIG. 3, the circuit can be implemented with an independent output connection 23 and an independent input connection 24. 
     In an alternative embodiment of the invention, shown in FIG. 5, the inventive environment sensing/control circuit 14&#39; is used in conjunction with an analog controller 11&#39; that has latchable inputs. That is, the analog controller 11&#39; has an Enable input which, when activated, permits data to be stored into input memory registers (such as latches 40) of the analog controller 11&#39; while disabling the digital outputs (e.g., by means of tri-statable drivers 41) of the analog circuit 11&#39;. Thus, by coupling the I/O pin 39 to both an input circuit and an output circuit of the analog controller 11&#39;, it is possible to use a single I/O pin in conjunction with the inventive circuit and still utilize both the control section and the sensing section of each circuit. Normally, each environment sensing/control circuit would be in the sense mode (i.e., the output driver 32 of the circuit is disabled). Each digital input to the analog controller 11&#39; would also normally be disabled. 
     When in the control mode, the Enable input to the analog controller 11&#39; would be activated, thereby disabling digital output drivers 41 in the analog controller 11&#39;, and latching into the input latches 40 of the analog controller 11&#39; the corresponding signal from a coupled control section of an environment sensing/control circuit 14&#39;. In the environment sensing/control circuit 14&#39;, each output driver 32 would be enabled, thereby permitting the contents of the control memory register 22 to be coupled through its I/O pin 39 to an input of the analog controller 11&#39;. As shown in FIG. 5, all of the latchable inputs to the analog controller 11&#39; would be programmed at the same time. When the Enable input to the analog controller 11&#39; is inactive, the digital output signals of the analog controller 11&#39; are again enabled, thereby providing input signals to the sensing section of corresponding environment sensing/control circuits. This configuration thus permits the inventive environment sensing/control circuit to be used in both the control mode and the sense mode over a single I/O pin. 
     It will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the memory registers, which are shown in the above description as being implemented by flip-flops, could be implemented by memory locations within a larger addressable integrated circuit memory array, such as a &#34;first in, first out&#34; (FIFO) memory register in place of the flip-flop 37 shown in FIG. 3. Use of a FIFO would allow environmental changes to be recorded between the time of the first occurrence of an exception condition and the time the memory is read. Further, the invention could be used to control and sense environmental conditions for a large variety of subsystems within a larger system of which the invention is a part, and is not limited to the specific example of fans, power supplies, and disk drive units within a disk drive subsystem. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiment, but only by the scope of the appended claims.