Abstract:
Provided is a low power random bit generator utilizing a multiplying digital to analog converter (MDAC) which is used in a switched capacitor amplifying circuit and an analog to digital converter with a pipeline architecture. The low power random bit generator includes: an MDAC, outputting a predetermined analog voltage formed by using a ground voltage, a reference voltage, an initial voltage and a digital signal; a comparator, outputting a direct current (DC) voltage determined by comparing the analog voltage with the ground voltage; and a data storage unit, storing a predetermined digital signal corresponding to the DC voltage, and outputting the digital signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority of Korean Patent Application No. 10-2004-0072106, filed on Sep. 9, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a random number generator, and more particularly, to a low power random bit generator and a random number generator using the random bit generator.  
         [0004]     2. Description of the Related Art  
         [0005]     As information security becomes increasingly important, random number generators, which produce an encryption key and a decoding key, become more essential for many types of electronic systems.  
         [0006]     To be embedded in a mobile system such as a smart card, the random number generator should have a simple configuration and consume little power. In particular, if the random number generator is implemented on a semiconductor chip, the random number generator should be compact.  
         [0007]      FIG. 1  is a block diagram of a random number generator using an analog system. The random number generator includes a random bit generator (RBG)  100 , a post processor  200 , and an output buffer  300 .  
         [0008]     The RBG  100 , which is an analog signal processing unit, generates a predetermined random bit signal by using a noise source.  
         [0009]     The post processor  200 , which is a digital signal processing unit, receives the random bit signal and performs predetermined digital signal processing on the received random bit signal. As a result of the digital signal processing, the randomness of the random bit is increased. Through digital signal processing, algorithms are digitally processed, such as correction and compression, for the random bit signal.  
         [0010]     The random bit signal on which digital processing has been performed is transmitted to the outside through the output buffer  300 .  
         [0011]     A typical way to generate a random bit signal by using an analog signal is to use white noise that is obtained from a resistor which is not biased at a constant voltage. Since the voltage level of a noise signal is typically extremely low, it is not until the noise signal is amplified by an amplifier with a very high gain that the noise signal can be used.  
         [0012]     In general, the amplifier consumes much power, thereby increasing the power consumption of a system and the size of a chip. Moreover, in the amplifier, the power supply rejection ratio (PSRR) is deteriorated due to: a) noise caused by peripheral digital logic circuits operating at high frequencies on a semiconductor chip; b) power supply noise; and c) flicker noise. In other words, the amplifier may output unexpected voltage or current due to various types of noise.  
         [0013]     To prevent or reduce as much as possible the influence of the digital circuits operating at high frequencies, the amplifier should be separated from the peripheral circuits. However, the separation of the amplifier from the peripheral circuits cannot be easily implemented and requires a large area. Further, to suppress spike noise from a power supply, a resistor having a large resistance and a capacitor having a large capacitance should be installed on the power supply.  
       SUMMARY OF THE INVENTION  
       [0014]     The present invention provides a low power random bit generator. The present invention also provides a random number generator including a low power random bit generator.  
         [0015]     According to an exemplary embodiment of the present invention, there is provided a random bit generator comprising: a multiplying digital to analog converter (MDAC), a comparator, and a data storage unit.  
         [0016]     The MDAC outputs a predetermined analog voltage formed by using a ground voltage, a reference voltage, an initial voltage and a digital signal. The comparator outputs a direct current (DC) voltage determined by comparing the analog voltage with the ground voltage. The data storage unit stores a predetermined digital signal corresponding to the DC voltage, and outputs the digital signal.  
         [0017]     The MDAC may include: an operational amplifier, of which a first input terminal is connected to the ground voltage, outputting the analog voltage from an output terminal; a first capacitor, of which a first terminal is connected to a second input terminal of the operational amplifier; a second capacitor, of which a first terminal is connected to the second input terminal of the operational amplifier; a first switch, selecting either the reference voltage or the ground voltage, each of which is connected to input terminals of the first switch, and transmitting the selected voltage to an output terminal of the first switch in response to the digital signal; a second switch selecting one of the output terminal of the first switch, the initial voltage and the analog voltage, and transmitting the selection to a second terminal of the first capacitor in response to a first control signal; a third switch selecting either the initial voltage or the ground voltage, and transmitting the selection to a second terminal of the second capacitor in response to a second control signal; and a fourth switch selectively connecting the second input terminal and the output terminal of the operational amplifier in response to a third control signal.  
         [0018]     According to another exemplary embodiment of the present invention, there is provided a random number generator comprising a random bit generator and a digital post processor. The random bit generator includes: a multiplying digital to analog converter (MDAC) that generates a random bit by using an initial voltage, a reference voltage, a ground voltage and a digital signal each of which has a predetermined voltage level; a comparator that compares the random bit of the MDAC with the ground voltage; and a data storage unit that stores output data of the comparator and outputs the digital signal. The digital post processor digitally performs an algorithm on the digital signal, such as correction and compression, for the output data. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0020]      FIG. 1  is a block diagram of a random number generator in an analog system;  
         [0021]      FIG. 2  is a block diagram of a low power random bit generator according to an exemplary embodiment of the present invention;  
         [0022]      FIG. 3  is a circuit diagram of a multiplying digital to analog converter (MDAC) illustrated in  FIG. 2  during a sample/hold mode;  
         [0023]      FIG. 4  is a circuit diagram of the MDAC illustrated in  FIG. 2  during an amplify mode;  
         [0024]      FIG. 5A  is a circuit diagram of the MDAC illustrated in  FIG. 2  during a sample/hold mode;  
         [0025]      FIG. 5B  is a circuit diagram of the MDAC illustrated in  FIG. 2  during a first step of the amplify mode; and  
         [0026]      FIG. 5C  is a circuit diagram of the MDAC illustrated in  FIG. 2  during a second step of the amplify mode. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0027]     The present invention will be described in detail by the use of exemplary embodiments of the invention with reference to the attached drawings.  
         [0028]      FIG. 2  is a block diagram of a low power random bit generator according to an exemplary embodiment of the present invention. The random bit generator includes a multiplying digital to analog converter (MDAC)  210 , a comparator  230 , and a data storage unit  250 .  
         [0029]     The MDAC  210  outputs a predetermined analog voltage Vout 1  which is produced by using a ground voltage GND, a reference voltage Vref, an initial voltage Vin and a digital signal Dout.  
         [0030]     The MDAC  210  includes an operational amplifier OP AMP, a first capacitor C 1 , a second capacitor C 2 , a first switch SW 1 , a second switch SW 2 , a third switch SW 3 , and a fourth switch SW 4 .  
         [0031]     A positive input terminal (+) of the operational amplifier OP AMP is connected to the ground voltage GND, and an output terminal of the operational amplifier OP AMP outputs the analog voltage Vout 1 . A negative terminal of the first capacitor C 1  is connected to a negative input terminal (−) of the operational amplifier OP AMP. A negative terminal of the second capacitor C 2  is also connected to the negative input terminal (−) of the operational amplifier OP AMP. The first switch SW 1  selects either the reference voltage Vref or the ground voltage GND, each of which is connected to input terminals of the first switch SW 1 , and transmits the selected voltage to an output terminal of the first switch SW 1  in response to the digital signal Dout. The second switch SW 2  selects one of the output terminal of the first switch SW 1 , the initial voltage Vin and the analog voltage Vout 1 , and transmits the selection to a positive terminal of the first capacitor C 1  in response to a first control signal CON 1 . The third switch SW 3  selects either the initial voltage Vin or the analog voltage Vout 1 , and transmits the selection to a positive terminal of the second capacitor in response to a second control signal CON 2 . The fourth switch SW 4  selectively connects together the negative input terminal (−) and the output terminal of the operational amplifier OP AMP in response to a third control signal CON 3 . The terminals are connected together when the fourth switch is turned on (closed position).  
         [0032]     The comparator  230  outputs a DC voltage Vout 2  determined by comparing the analog voltage Vout 1  with the ground voltage GND.  
         [0033]     The data storage unit  250  stores a predetermined digital signal corresponding to the DC voltage Vout 2 , and outputs the digital signal Dout.  
         [0034]     The operational amplifier OP AMP may be a general two (2) stage operational amplifier, which is characterized by low power consumption. The 2 stage operational amplifier is an operational amplifier composed of two stages such as a differential input stage and an amplifying stage, or a differential input stage and a buffer stage. The comparator  230  can be implemented by using a 2 stage operational amplifier, hence reducing power consumption.  
         [0035]     The data storage unit  250  may be implemented by using a D-type flip-flop.  
         [0036]     The random bit generator  210  can operate in two modes: a sample/hold mode and an amplify mode.  
         [0037]     In the sample/hold mode, a voltage that has been initially sampled in the MADC  210  is held, and the resulting analog voltage Vout 1  is compared with the ground voltage GND by the comparator  230  results in the DC voltage Vout 2  which is stored in the data storage unit  250 .  
         [0038]      FIG. 3  is a circuit diagram of the MDAC illustrated in  FIG. 2  during the sample/hold mode. In the sample/hold mode, the initial voltage Vin connected to the second switch SW 2  and the third switch SW 3  is selected in response to the first control signal CON 1  and the second control signal CON 2 , respectively. The fourth switch SW 4  operating in response to the third control signal CON 3  is turned on (closed position). The first switch SW 1  operating in response to the digital signal Dout is not used at this moment, and therefore it does not matter which input terminal of the first switch SW 1  is selected.  
         [0039]     According to the above-described selection operations of the switches, the positive terminals of each capacitor C 1  and C 2  are provided with the initial voltage Vin, and their negative terminals are connected to the negative input terminal (−) of the operational amplifier OP AMP. The negative input terminal (−) and the output terminal of the operational amplifier OP AMP are connected together, and the positive input terminal (+) of the operational amplifier OP AMP remains connected to the ground voltage GND. Since the operational amplifier OP AMP operates like a buffer, the negative input terminal (−) of the operational amplifier OP AMP becomes a virtual ground having a voltage level of the ground voltage GND. Assuming that each capacitor C 1  and C 2  has equal capacitance C, the respective capacitors C 1  and C 2  are charged with charges of C*Vin. The two capacitors C 1  and C 2  are connected in parallel between the initial voltage Vin and the virtual ground, thus the total amount of charge between the initial voltage Vin and the virtual ground is 2*C*Vin.  
         [0040]     In the amplify mode, the charges stored during the sample/hold mode are amplified.  
         [0041]      FIG. 4  is a circuit diagram of the MDAC illustrated in  FIG. 2  during the amplify mode. The data storage unit  250  is reset to a logic low (“0”) during a first cycle. The first switch SW 1  selects the ground voltage GND in response to the output of the digital signal Dout. In the amplify mode, the second switch SW 2  selects the output of the first switch SW 1 . Thus, the positive terminal of the first capacitor C 1  is connected to the ground voltage GND and the negative terminal of the first capacitor C 1  remains connected to the negative input terminal (−) of the operational amplifier OP AMP. The third switch SW 3  selects the output terminal of the operational amplifier OP AMP in response to the second control signal CON 2 . Thus, the positive terminal of the second capacitor C 2  is connected to the output terminal of the operational amplifier OP AMP and the negative terminal of the second capacitor C 2  also remains connected to the negative input terminal (−) of the operational amplifier OP AMP. The fourth switch SW 4  operating in response to the third control signal CON 3  is turned off (open position).  
         [0042]     During the amplify mode illustrated in  FIG. 4 , the MDAC  210  is set in a two-step switching operation. First, the negative terminals of the first and second capacitors C 1  and C 2  remain connected to the negative input terminal (−) of the operational amplifier OP AMP and the positive terminal of the second capacitor C 2  is connected to the output terminal of the operational amplifier OP AMP by the third switch SW 3  operating in response to the second control signal CON 2 . At first, the second switch SW 2  maintains the previous selection, in this case connecting the positive terminal of the first capacitor C 1  with the initial voltage Vin. After a predetermined time, the third switch SW 3  remains unchanged and the second switch SW 2  selects the ground voltage GND in response to the first control signal CON 1 , thus connecting the positive terminal of the first capacitor C 1  to the ground voltage GND.  
         [0043]      FIGS. 5A through 5C  are circuit diagrams illustrating procedures when the MDAC illustrated in  FIG. 2  transits from the sample/hold mode illustrated in  FIG. 3  to the amplify mode illustrated in  FIG. 4 .  
         [0044]      FIG. 5   a  is a circuit diagram of the MDAC illustrated in  FIG. 2  during the sample/hold mode.  
         [0045]      FIG. 5   b  is a circuit diagram of the MDAC illustrated in  FIG. 2  during a first step of the amplify mode.  
         [0046]      FIG. 5C  is a circuit diagram of the MDAC illustrated in  FIG. 2  during a second step of the amplify mode.  
         [0047]     For convenience of description, it is assumed that the two capacitors C 1  and C 2  illustrated in  FIG. 2  have equal capacitance and the initial voltage Vin has a higher voltage level than the ground voltage GND.  
         [0048]     Referring to  FIG. 5A , at the moment of sampling the positive terminals of the first and second capacitors C 1  and C 2 , which are connected to the initial voltage Vin, will be charged with positive charges, and the negative terminals of the first and second capacitors C 1  and C 2  will be charged with negative charges.  
         [0049]     Referring to  FIG. 5B , during the first step of the amplify mode, the positive terminal of the second capacitor C 2  connects to the output terminal of the operational amplifier OP AMP and the negative terminal of the second capacitor C 2  remains connected to the negative input terminal (−) of the operational amplifier OP AMP.  
         [0050]     Since the negative input terminal (−) of the operational amplifier OP AMP has a voltage level equal to the ground voltage GND, the output terminal Vout has a voltage level equal to the initial voltage Vin.  
         [0051]     Referring to  FIG. 5C , in the second step of the amplify mode, since the positive terminal of the first capacitor C 1  is switched from the initial voltage Vin to the ground voltage GND, the positive terminal of the first capacitor C 1  has a voltage level equal to the ground voltage GND. At this moment the charge on the negative terminal of the first capacitor C 1  is preserved according to the energy conservation law, and the negative charge on the negative terminal of the first capacitor C 1  moves to the second capacitor C 2 . Accordingly, the analog voltage Vout 1  of the output terminal of the operational amplifier OP AMP becomes  2 *Vin. The initial voltage Vin is amplified two times through the transition from the sample/hold mode to the amplify mode.  
         [0052]     When the transition from the sample/hold mode to the amplify mode is considered as a single cycle, the cycle described above corresponds to a first cycle of the circuit operation. A second cycle of an exemplary embodiment of the present invention will be described below.  
         [0053]     When the first cycle is completed, a predetermined digital signal Dout has been stored in the data storage unit  250 .  
         [0054]     In an exemplary embodiment of the present invention, when the digital signal Dout is a logic high (“1”), the first switch SW 1  connects to the reference voltage Vref and the analog voltage Vout 1  of the MDAC  210  can be denoted by equation 1. 
 
Vout 1 = 2 Vin−Vref   (1) 
 
         [0055]     When the digital signal Dout is a logic low (“0”), the first switch SW 1  connects to the ground voltage GND and the analog voltage Vout 1  of the MDAC  210  can be denoted by equation 2. 
 
Vout 1 = 2 Vin   (2) 
 
         [0056]     In an exemplary embodiment of the present invention, the initial voltage Vin which was used to perform sampling during the sample/hold mode in the first cycle is not used in the second cycle, but a feedback loop is employed in which the analog voltage Vout 1 , the ground voltage GND and the reference voltage Vref, that were produced in the previous cycle, are used as the input signals to the positive terminal of the first capacitor C 1 . The first switch SW 1  operating in response to the digital signal Dout is not used during the sample/hold mode in the first cycle, but is used during the sample/hold mode in following cycles.  
         [0057]     During the sample/hold mode in following cycles of an exemplary embodiment, the second switch SW 2  selects one of the output of the first switch SW 1  and the analog output Vout 1  as randomly determined by the first control signal CON 1 . Accordingly, the first capacitor C 1  and the second capacitor C 2  can be discharged when the second switch SW 2  and the third switch SW 3  both select the analog voltage Vout 1  and the fourth switch SW 4  is selectively turned on (closed). Alternatively, during the sample/hold mode in following cycles, the second capacitor C 2  can be discharged while the first capacitor C 1  can be charged to either the ground voltage GND or the reference voltage Vref based on the Dout selection to the first switch SW 1  where in this case the second switch SW 2  selects the output of the first switch SW 1 , the third switch SW 3  selects the analog voltage Vout 1 , and the fourth switch SW 4  is selectively turned on (closed).  
         [0058]     By repeating these cycles, the MDAC can randomly generate an analog voltage Vout 1 . The analog voltage Vout 1  is used in a comparator or a data storage unit, and a low power random bit generator and a random number generator using the random bit generator can be made.  
         [0059]     As described above, the random bit generator and the random number generator using the random bit generator can be implemented by using the capacitors, the switches, and the operational amplifier with a simple structure, thereby consuming less power and minimizing the area occupied by the random number generator when implemented on a semiconductor chip.  
         [0060]     In another exemplary embodiment of the present invention, a random number generator uses a random bit generator as described above and a digital post processor that digitally performs an algorithm, such as correction and compression, on the random bit output data. The algorithms performed by the digital post processor, such as correction and compression, are known in the art and will not be described.  
         [0061]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.