Abstract:
Efficient low EMI switching output stages and methods that may be used, by way of example, in class D amplifiers. The output stages comprise class AB output stages having complementary FETs for the output. The FETs are switched in response to a switch control signal in a manner to simultaneously switch the FETs so that both FETs are not off at the same time. The extent to which both FETs are on at the same time is controlled to maintain efficiency of the circuit, and preferably the output voltage slew rate is set by circuit parameters to a relatively low slew rate. By maintaining conduction in one or both the FETs during the transition, forced conduction through a parasitic diode in either FET, as may occur in response to an inductive load (an effect commonly called freewheeling), together with the rapid and wide voltage swing associated therewith, is avoided. The removal of dead time (time when all switches are OFF), and associated freewheeling behavior, enables a controlled reduction in the output voltage slew rate and grossly reduces EMI emissions. The invention is particularly useful for switching power level outputs, and/or where lead wires or substantial circuit traces may be connected thereto.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to the field of electromagnetic interference (EMI) control in complementary FET switching circuits. 
   2. Prior Art 
   Electromagnetic Interference (EMI) is a common problem in modern electronic systems. Many everyday consumer products combine complex digital signal processing with radio frequency transmit and receive circuitry for communication. The former is an unintentional source of EMI that can interfere with the latter “intentional” source, as well as any other RF sources in the vicinity of the emitter. As a result, there exists stringent high frequency emissions limits on most everyday electronic equipment. 
   As one example, for class D amplifiers, the fast switching of the output FETs can cause strong emissions at high frequencies. For filterless class D amplifiers, the magnitude of the emissions is a strong function of the length of the wires connecting the amplifier to the speaker. Since the speaker presents an inductive load to the amplifier, the rate of change of the electric field is usually much higher than the rate of change of the magnetic field around the emitter. Therefore, the high frequency characteristics of the output switching voltage waveform mostly determine the EMI performance. There are essentially two components to this waveform: (1) the transition from negative supply to positive supply and vice versa, and (2) the ringing and settling due to various parasitic LC tank circuits around the power FETs and their packaging. To fully understand the details here, refer to  FIG. 1  and note that, for an inductive load, current cannot change instantaneously in the inductor, and therefore, when both devices are OFF, current must continue to flow somewhere, and can therefore only flow through the FET parasitic diodes. Depending on the direction of the load current, the parasitic diode could either cause the output to transition to a diode drop above the positive supply rail, or a diode-drop below the negative supply rail. When one or the other of the FETs is subsequently turned ON, the load current flows through the FET, causing the output voltage to either droop toward the nearest supply rail, or to transition to the opposite supply rail. 
   The ringing and settling depend on the distributed LC tank circuits that include package and bond-wire inductance and parasitic FET capacitances. For example, assume for discussion that the output FET gate series resistors shown in  FIG. 1  are zero. Every time the gate of one of the output FETs is switched to the supply rail, an LC tank is formed from the supply line inductance and FET gate-source and gate-drain capacitances, damped only by the ON resistance of a switch, which might only be a few ohms. The FET gate voltage can ring with a frequency of 100 s of MHz, an oscillation which will couple through to the output. This can easily be visible in the output voltage spectrum as an emissions spike at the LC tank frequency. Depending on which way the output is transitioning, and the direction of the load current, various LC tank frequencies can be observed. 
   The slew rate of the output transition from low to high and vice versa determines how much the wideband frequency content of the output voltage deviates from that of an ideal square waveform. For example, the frequency spectrum of a square pulse with equal and finite rise and fall times τ will exhibit harmonics that follow a sinc (sin x/x) envelope when compared to the frequency spectrum of an ideal square waveform (ideal being one with infinitely fast edges). This sinc envelope has spectral nulls at frequencies that are integer multiples of 1/τ. Making τ be 10 ns or greater under all operating conditions can therefore result in a significant emissions benefit. 
   Therefore it is desired that the gate voltage transitions of both FETs be controlled in such a way as to limit the output voltage slew rate, and attempt to damp the described parasitic sources of oscillation. Referring to  FIG. 1 , conventional means to achieve this involve either adding resistors in series with the output FET gates, or reducing the aspect ratio of the output FET gate driving switches to increase the RC time constant formed by the gate and the driving switch. Both solutions increase the transition time of the output FET gates, but the time between one FET turning OFF and the next FET turning ON is relatively poorly controlled, and will typically lead to substantial dead time (time when both switches are OFF) as shown in the typical waveforms of  FIG. 2 . Furthermore, for an inductive load (see  FIG. 2 ), the point at which the output voltage transition occurs is also poorly controlled, and in fact, can occur either at the beginning or end of the dead time, depending on the direction of the load current. (Note that the direction of the load current determines which one of the parasitic FET diodes must conduct during the dead time.) This effect results in distortion. The time used for FET gate transitions leads to efficiency loss, because the FETs are operating in a high ON resistance mode for a relatively large fraction of the switching period. Finally, these shortcomings limit the maximum frequency of operation of the output power stage, and this is in itself largely contrary to high fidelity and high efficiency filterless class D circuit design art. 
   The foregoing discusses the prior art as related to class D amplifiers such as are frequently used to drive a speaker. However similar problems are encountered in any application that uses two or more complementary FETs as a switched output stage to drive heavy loads, including resistive, capacitive, inductive and complex loads in response to an input signal. In that regard, such circuits are considered herein, in a broad sense, as a form of class D amplifier. 
   Furthermore, for illustrative purposes, schematics of the prior art and disclosed invention show a single-ended speaker driver configuration. It should be noted that the invention can be readily applied to a full H-bridge load configuration, as is more common in the class D art. Considering the single-ended case merely simplifies the foregoing discussion. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram illustrating a typical prior art class D amplifier driving a speaker and using parasitic diode conduction during the period both output FETs are turned off. 
       FIG. 2  presents waveforms characteristic of the prior art. 
       FIG. 3  is a schematic diagram of the present invention with exemplary waveforms illustrating the principles of operation thereof. 
       FIG. 4  is a circuit diagram of an exemplary embodiment of the present invention. 
       FIG. 5  presents exemplary waveforms for the embodiment of  FIG. 4 . 
       FIGS. 6   a  and  6   b  illustrate the application of the present invention to full H bridge circuits. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention, among other things, has two main characteristics that offer improvement over the prior art. These may be illustrated in relation to  FIG. 3 . As shown therein, a control circuit receives an input switching signal V IN  and provides gate controls for complementary FETs providing a load current I load  at an output voltage V OUT , in this example to a speaker as a load. In the primary examples provided herein, the complementary FETs are n channel and p channel FETS, though this is not a limitation of the invention. For purposes of specificity in this example, assume that the load current is zero, and that at time t 0 , the input voltage V IN  changes from 0 to V DD , signaling that the n channel device should be turned off (V GN  should go low) and that the p channel device should be turned on (V GP  should also go low). While both of the gate control voltages Y GP  and V GN  should go low, it may be seen that the gate control voltages V GP  and V GN  are controlled in a coordinated manner so that they essentially simultaneously cross the threshold voltage of the respective FET. Thus both FETs are not off at the same time, and in fact, are both somewhat turned on during the transition through the threshold voltages, giving rise to a current from V DD  to ground (I 1 =I 2 ) during the transition that peaks at a value I MAX . For simplicity, the effect of parasitic capacitance at the output is ignored in the exemplary waveforms. In practice, I 1  and I 2  will differ during the transition by an amount sufficient to charge this parasitic capacitance. This fact doesn&#39;t affect the foregoing analysis. 
   The advantages of this approach include:
         (1) Zero dead time. The output FET gates are switched simultaneously (and not sequentially). This provides the ability to reduce the output voltage slew rate with minimal periods of time where efficiency is reduced (those periods being the dead time and gate voltage transition time). The output voltage transition point is better controlled. The parasitic FET diodes do not conduct and cause distortion.   (2) The control circuit controls the gate voltages to allow a limited crowbar (both devices ON) current, I max , in transition. This prevents very large crowbar switching currents that would otherwise occur when switching the gates simultaneously, and which can lead to excessive static (no load) power dissipation and/or could destroy the devices. Thus, a high efficiency is maintained.       

     FIG. 4  shows a preferred embodiment of the invention. The crowbar control circuit consists of a MOSFET translinear circuit (MN 1 - 5 , MP 1 - 5 ) that is commonly used in class AB amplifiers as a quiescent current control circuit. When used as a digital switching stage in this application, the circuit exhibits the characteristics listed above, and operates as follows. 
   Consider the low-to-high output transition illustrated in the exemplary waveforms of  FIG. 5 . When V IN  goes from low to high, current Iref is steered through current mirrors MP 7 /MP 8  and MN 6 /MN 2 . Initially, MP 2  has no current. Both gate voltages V GP  and V GN  are high. MP 3  is ON and operating in its triode region (Vds˜0), which means that V GP  and V GN  must track each other. Note that MN 3  is OFF and so I MN2 =I MP3 , and note that this current flows from the gate of MP 1 , charging it&#39;s gate capacitance. V GP  will decrease until roughly a threshold voltage below V DD , such that MP 3  satisfies the PMOS triode region equation I MP3 =(KW/L)*(Vsg−Vth−Vsd/2)*Vsd, where K is the mobility times oxide capacitance per unit area product, and where W and L are the transistor width and length and Vth is the absolute value of the threshold voltage. At this point, V GP  will stay roughly constant, and I MP3  must then decrease to reflect the decrease in the rate of change of V GP . Most of I MN2  now flows through the gate of MN 1 , thus further discharging V GN , but at a faster rate. V GN  then continues to decrease until MN 3  turns ON at roughly a threshold voltage above ground. MN 3  will then start to conduct the current I MN2  and V GN  will be held roughly constant. MN 3 &#39;s current flows through the gate capacitance of MP 1 , causing. V GP  to decrease at a rate given approximately by dV GP /dt=−I MN2 /C g (MP1) . As the voltage V GP  approaches the voltage V GN , MN 3  enters the triode region, which causes V GN  to track V GP  again. V GN  will continue to decrease so as to satisfy the NMOS triode region equation I MN3 =(KW/L)*(Vgs−Vth−Vds/2)*Vds, where Vds is gradually decreasing, and so Vgs must be increasing. V GP  and V GN  continue reducing until MN 2  shuts off when its Vds becomes zero. 
   Note that at no point during this cycle are MP 3  and MN 3  both OFF (Vgs&lt;Vth for both transistors). Therefore, either the translinear circuit MP 1 - 5  or the translinear circuit MN 1 -MN 5  is controlling the current I 1  and I 2  when Iload=0. In the region when I MN2 =I MP3 , I max  can be written as I max =β MP1 [√(I BIAS /β MP4 )+√(I BIAS /β MP5 )−√(I REF /β MP3 )] 2 , where
 
β MPn =( KW/ 2 L ) Mpn 
 
   In the region when I MN2 =I MN3 , I max  can be written as I max =β MN1 [√(I BIAS /β MN4 )+√(I BIAS /β MN5 )−√(I REF /β MN3 )] 2 , where
 
β MNn =( KW/ 2 L ) MNn 
 
   Thus, at all times during the transition, I max  is well controlled, as the extent to which both MP 1  and MN 1  are partially on at the same time is well controlled. 
   The output slew rate is now controllable by varying I BIAS , I REF  and the transistor aspect ratios, since |dV OUT /dt|&lt;=I max /C out , where C out  is the sum of the output FET (MN 1 /MP 1 ) drain capacitances, which would be well known, plus any additional loading capacitance, which would typically be small compared to that of the FETS. 
   Referring now to  FIG. 5 , the behavior of the circuit with both a resistive and inductive load can be compared with that of the prior art. In particular, the behavior of the gate voltages is approximately independent of the load, and it can be noted that, for an inductive load, there is no dead time where both output FETs are OFF and, as a result, the FET parasitic diodes do not carry current. Note that the reverse conducting mode of the NMOS transistor during the gate transition (V GN  getting smaller) can cause the output voltage to droop by 100–300 mV below ground, but this droop is too small to cause the MOS parasitic diode to turn on. The load current therefore traverses from MN 1  to MP 1  as MOS channel current only. 
   For the class D audio application, the implication of this behavior is profound. Most importantly, it means that the output voltage transitions can be completely controlled by the FET gate voltages in the presence of an inductive load such as a speaker. Compare this with the prior art of  FIGS. 1 and 2  in response to an inductive load, and note that the output high-to-low transition in response to the same input signal condition occurs at the point of turn OFF of the P channel FET. The output slew rate is therefore not only very large, but highly load-dependent and also dependent on the speaker. DC impedance. This is because dV out /dt=−I load /Cout, where I load  would usually be much greater than I max . For example, in a typical application, I load &gt;1A for a 4 ohm speaker with V DD =5V. Compare this with a controlled I max  in the range of 30 mA, and it is clear that the output slew rate of the present invention can be designed to be much lower, independent of the load, and correspondingly much better emissions performance can be achieved with the described invention. In that regard, while the slew rates on V OUT  appear as high in  FIG. 5  as in the prior art of  FIG. 2 , these Figures are schematic only, the slew rate of the present invention being readily controllable and limited as described. 
   For example, in one embodiment of the invention, a 20 dB margin has been achieved under FCC class B EMI limits. Furthermore, an identical circuit but with a prior art switching power stage exhibits only 5 dB of margin. The maximum power efficiency is the same as the prior art realization. This is because the total time spent by the FET gates in transitioning between the supply rails is typically equal to less than 10% of the overall switch control signal period. This maximizes efficiency and frequency of operation and minimizes distortion. In this embodiment, the power stage operates at up to a 2 MHz switching frequency, which is typically 5–10 times faster than prior art slew-limited designs can safely operate. The transition time of a voltage on the output terminal is at least 10 ns under all operation conditions. 
   In the specific exemplary embodiment hereinbefore described, a specific class AB amplifier output stage has been used for purposes of explanation of the present invention and not for purposes of limitation of the invention. In particular, any class AB amplifier output stage having a provision for controlling the quiescent current may be used, though preferably one having a sufficiently high frequency response to allow achievement of the EMI reduction at the high switching rates readily achievable by the present invention. Thus in a broad sense, in one aspect, the present invention comprises an input stage that receives a switch control signal and a class AB output stage controlled by the input stage to switch complementary output FETs with a controlled slew rate and with a crowbar effect in the switching while controllably limiting the serial current through the output FETS during the time both output FETs are turned on. Typically the input signal will be a two state signal, or will be converted to one or more two state signals in the input stage. 
   In another aspect, the present invention comprises a switch control circuit for controlling the switching of complementary FET devices to limit the EMI generated by providing a controlled slew rate of the output voltage and by simultaneous switching of the FET devices to avoid any period during which both FET devices are turned off. Typically the FET devices will be power devices, and may be discrete or integrated devices. In that regard, the exemplary circuit disclosed herein is a fully integrated CMOS circuit, though the present invention may readily be implemented in a BiCMOS process if desired. 
   The control circuit and the complementary FETS being switched may comprise a class D amplifier, or may comprise a switching circuit for any complementary FETs, typically power FETS, to reduce the EMI generated during switching. While a single pair of complementary FETS are shown in the exemplary embodiment, the invention may readily be applied to the switching of multiple pairs of complementary FETS, such as, by way of example, full H bridge circuits as used in class D amplifiers and otherwise. This is illustrated in  FIGS. 6   a  and  6   b , wherein each circuit is controlled by a respective control signal, which control signals may or may not be complementary control signals. 
   This invention is particularly applicable to filterless class D audio amplifiers to enable ultra-low emissions performance. In particular, the present invention enables filterless EMI performance that is 20 dB or more below FCC class B radiated emissions standards. Unlike many conventional low EMI solutions, the invention is not accompanied by a large degradation in distortion, efficiency characteristics or reduced operating frequency. The present invention is applicable to any application that uses 2 or more complementary FETs as an output stage to drive heavy loads (either resistive, capacitive or inductive). For example, charge pump power supplies can use the circuit, as can I/O pin drivers in microprocessors or digital signal processors. Often, these circuits use crude means to limit output transition times and emissions, at the expense of efficiency and/or operating frequency. 
   While certain preferred embodiments of the present invention have been disclosed and described herein or purposes of illustration, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.