Abstract:
A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 2007-104035, filed on Oct. 16, 2007, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present general inventive concept disclosed herein relates to a semiconductor, and more particularly, to a semiconductor package with an improved reliability, and an electronic device having the same. 
         [0004]    2. Description of the Related Art 
         [0005]    Generally, a semiconductor package has a structure that a semiconductor chip is protected from an external environment by being molded with an epoxy molding compound (EMC).  FIG. 1  is a top plan view illustrating a conventional semiconductor package. Referring to  FIG. 1 , a semiconductor chip  11  includes a plurality of die pads  13 , and the die pads  13  are electrically connected to outer terminals  14  by interconnections  15 . The semiconductor chip  11  is molded with a molding layer  12  such as an epoxy molding compound (EMC). A semiconductor package  10  is electrically connected to an external device through the outer terminal  14 . 
         [0006]    An interface  16  is formed between the semiconductor chip  11  and the molding layer  12 . Since the semiconductor chip  11  and the molding layer  12  have different materials, a physical characteristic such as a mechanical characteristic and a thermal characteristic may be different. A mechanical stress or a thermal stress which is applied to a semiconductor package  10  may be concentrated on the interface  16 . If a mechanical stress or a thermal stress is concentrated on the interface  16 , a crack may occur at the interface  16 , or a lamination phenomenon in which the semiconductor chip  11  and the molding layer  12  are separated from each other may occur. A crack or a lamination phenomenon may cause a crack of the interconnection  15  or a disconnection of the interconnection  15 . Thus, a reduction in reliability of the semiconductor package  10 , such as an electrical malfunction, may occur. 
       SUMMARY OF THE INVENTION 
       [0007]    Example embodiments provide a semiconductor package. The semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. 
         [0008]    Additional aspects and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept. 
         [0009]    The foregoing and/or other aspects and utilities of present general inventive concept can be achieved by providing a semiconductor package, including a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer, and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. 
         [0010]    The foregoing and/or other aspects and utilities of present general inventive concept can also be achieved by providing a semiconductor package, including a semiconductor chip including die pads and an interconnection which connects the die pads to an outside of the semiconductor package, the interconnection including an altered shape portion at an interface between the semiconductor chip and a molding layer package to provide a reinforced strength at the interface. 
         [0011]    The altered shape portion of the interconnection may include a larger cross-sectional area than other portions of the interconnection. 
         [0012]    The altered shape portion of the interconnection may include a 90° bend to extend along a portion of the interface and a second 90° bend to extend perpendicular to and away from the interface through the semiconductor package. 
         [0013]    The package may include a molding layer surrounding the chip. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    These and/or other aspects and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which: 
           [0015]      FIG. 1  is a top plan view depicting a semiconductor package in accordance with a conventional art. 
           [0016]      FIG. 2  is a top plan view depicting a semiconductor package in accordance with an embodiment of the present general inventive concept. 
           [0017]      FIG. 3  is a top plan view depicting a portion of  FIG. 2 . 
           [0018]      FIGS. 4 to 8  are top plan views depicting different embodiments of interconnection depicted in  FIG. 3 . 
           [0019]      FIG. 9  is a perspective view depicting an example of an electronic device including a semiconductor package in accordance with an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]    The present general inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the general inventive concept are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the general inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. 
         [0021]      FIG. 2  is a top plan view depicting a semiconductor package in accordance with an embodiment of the present general inventive concept. 
         [0022]    Referring to  FIG. 2 , a semiconductor package  100  may have a molded structure in which a semiconductor chip  110  is molded by a molding layer  120  such as an epoxy molding compound (EMC). Each of the semiconductor chip  110  and the molding layer  120  may have a flat structure of a square. The semiconductor chip  110  may have a plurality of die pads  130 . The semiconductor package  100  may include a plurality of outer terminals  140  which are electrically connected to the plurality of die pads  130 . 
         [0023]    The die pads  130  may be arranged in a row to be adjacent to four sides (i.e., an upper side, a lower side, a right side and a left side) of the semiconductor chip  110 . Alternatively, the die pads  130  may be arranged in a row to be adjacent to two sides (i.e., upper and lower sides or right and left sides) of the semiconductor chip  110 . In other words the die pads  130  may extend along and adjacent to each of the four sides of the semiconductor chip  110 , in one long row. Alternatively, the die pads  130  may be arranged in a row on a center portion of the semiconductor chip  110 . The plurality of die pads  130  may be electrically connected to the plurality of outer terminals  140  through a plurality of interconnections  150 . The outer terminals  140  may be arranged in a row around the four sides of the semiconductor chip  110 . 
         [0024]    The die pads  130  may be arranged inside of the semiconductor chip  110  but the outer terminals  140  may be arranged outside of the semiconductor chip  110 . Since the interconnection  150  extends from the die pads  130  to the outer terminals  140 , the interconnection  150  may overlap with an interface  160  disposed between the semiconductor chip  110  and the molding layer  120 . The interconnection  150  may be a pattern which is redistributed. The interconnection  150  may be directly formed on the interface  160  or an insulating layer maybe disposed between the interconnection  150  and the interface  160 . 
         [0025]    A width of a portion of the interconnection  150  which overlaps with the interface  160  may be larger than a width of a portion of the interconnection  150  which does not overlap with the interface  160 , as described later with reference to  FIGS. 3 through 8 . As an example, as described later with reference to  FIGS. 3 through 7 , the portion of the interconnection  150  which overlaps with the interface  160  may have a nonlinear shape and the portion of the interconnection  150  which does not overlap with the interface  160  may have a linear shape. Alternatively, as described later with reference to  FIG. 8 , the portion of the interconnection  150  which overlaps with the interface  160  may have a linear shape extending along the interface  160  and the portion of the interconnection  150  which does not overlap with the interface  160  may have a linear shape extending in a direction which is perpendicular to the interface  160 . 
         [0026]      FIG. 3  is a top plan view depicting a portion of  FIG. 2 . Referring to  FIG. 3 , the interconnection  150  may include a first interconnection portion  151  of a linear shape, a second interconnection portion  152 - 1  of a round shape and a third interconnection portion  153  of a linear shape. The second interconnection portion  152 - 1  may alternatively have an oval shape. The first interconnection portion  151  extends in a direction which is perpendicular to an extending direction of the interface  160  and is electrically connected to the die pad  130 . The third interconnection portion  153  also extends in a direction which is perpendicular to an extending direction of the interface  160  and is electrically connected to the outer terminal  140 . The second terminal  152 - 1  is disposed at a position which overlaps with the interface  160  located between the first interconnection portion  151  and the third interconnection portion  153 . A width of the second interconnection portion  152 - 1  is relatively larger than widths of the first and third interconnections portions  151  and  153 . Therefore, even though a mechanical stress or a thermal stress is concentrated on the interface to cause a crack on the interface  160 , a crack which occurs on the interconnection  150  does not cause a disconnect due to a thick width of the second interconnection portion  152 - 1 . 
         [0027]      FIGS. 4 to 8  are top plan views depicting different embodiments of interconnection depicted in  FIG. 3 . Since interconnections depicted in  FIGS. 4 to 8  are similar to the interconnection depicted in  FIG. 3 , the description of common features already discussed above will be omitted for brevity, while any new or different features will be described in further detail below. 
         [0028]    As depicted in  FIG. 4 , the interconnection  150  may include a second interconnection portion  152 - 2  having a square shape. As depicted in  FIG. 5 , the interconnection  150  may include a second interconnection portion  152 - 3  having a diamond shape. As depicted in  FIG. 6 , the interconnection  150  may include a second interconnection portion  152 - 4  having a cross shape. As depicted in  FIG. 7 , the interconnection  150  may include a second interconnection portion  152 - 5  having a ring shape. 
         [0029]    As depicted in  FIG. 8 , the interconnection  150  may include a second interconnection portion  152 - 6  having a linear shape extending in a direction which is the same as an extending direction of the interface  160 . The interconnection  150  has a first bent portion  181  which is perpendicularly bent between the first interconnection portion  151  and the second interconnection portion  152 - 6  and a second bent portion  182  which is perpendicularly bent between the second interconnection portion  152 - 6  and the third interconnection portion  153 . Thus, the interconnection  150  can have a structure of a stair shape. 
         [0030]      FIG. 9  is a perspective view depicting an example of an electronic device including a semiconductor package in accordance with an embodiment of the present general inventive concept. 
         [0031]    Referring to  FIG. 9 , the semiconductor package  100  according to an embodiment of the present general inventive concept shown in  FIG. 2  may be used in an electronic device  1000  such as a note book. The electronic device  1000  may include a desk top computer, a camcorder, a cellular phone, a game machine, a portable multimedia player (PMP), a memory card, a display device such as LCD and PDP, and various electronic devices. Since the electronic device  1000  includes the semiconductor package  100  in which the interconnection  150  having a superior mechanical characteristic and a superior thermal characteristic is formed, the electronic device  1000  can be used in a severe circumstance without a malfunction. 
         [0032]    Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.