Abstract:
Provided is a circuit for controlling a data bus connecting a bitline sense amplifier to a data sense amplifier in accordance with a variation of an operating frequency of a memory device, being comprised of a pulse width adjusting circuit for varying a pulse width of an input signal in accordance with the operating frequency of the memory device after receiving the input signal, a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit, and an output circuit for outputting a first signal to control the data bus in response to a signal outputted from the signal transmission circuit.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method for controlling a sense amplifier of a memory device, and more particularly, to a method and circuit for automatically controlling an operation of a sense amplifier in correspondence with variations of operating voltage and frequency of a memory device. 
         [0003]    2. Description of the Related Art 
         [0004]      FIG. 1  is a diagram illustrating a read and write operations in a general memory device. 
         [0005]    As shown in  FIG. 1 , during a write operation, data applied through an input/output data pad is transferred to a bitline sense amplifier through a data input buffer and a data input register. While, during a read operation, cell data amplified by the bitline sense amplifier is transferred to the input/output data pad through a data sense amplifier, a pipe register, and a data output buffer. 
         [0006]    In  FIG. 1 , signal Yi is a pulse signal to connect the bitline sense amplifier with the data sense amplifier so as to control an operation of a data bus. While the signal Yi controlling the data bus is being enabled, the write data is transferred to the bitline sense amplifier from a write driver and the read data is transferred to the data sense amplifier from the bitline sense amplifier. It is advantageous to make a pulse width of the signal Yi wider in transferring valid data in an active operation mode (the read or write operation). It is also efficient to improve the performance of tDPL (a time from when a CAS pulse signal is generated internally by a write command to when a precharge pulse signal is generated internally by a precharge command) because the time parameter tDPL contributes to making restoring facilities of data better. 
         [0007]    Therefore, it is usual to establish the pulse width of the signal Yi as wider as possible within the permissible range and to use it with shrinking down in accordance with operational conditions. In reference, as an operating frequency of a memory device increases (i.e., a clock cycle period is shorter), a permissible pulse width of the signal Yi becomes narrower. 
         [0008]    Meanwhile, as the signal Yi is made from responding to a read/write strobe pulse signal rdwtatbzp 13  output from a read/write strobe pulse generator, hereinafter will be explained about the read/write strobe pulse generator. 
         [0009]      FIG. 2A  illustrates an example of a conventional read/write strobe pulse generator and  FIG. 2B  is a waveform diagram of signals used in the circuit shown in  FIG. 2A . 
         [0010]    In  FIG. 2A , signals extyp 8  and icasp 6  are signals to make a data transmission line short or open, so as to read data to a peripheral circuit from a cell array of the memory device or to write data in the cell array of the memory device from a peripheral circuit. For information, it&#39;s named a core section for the range including a memory cell and a bitline sense amplifier and the rest a peripheral circuit. 
         [0011]    In detail, the signal extyp 8  is a pulse signal that is generated in sync with a clock signal when a read or write command (burst command) is applied to the memory device. And, the signal icasp 6  is a signal to be used in operating the memory device by generating a self-burst operation command that is established with a burst length set by an MRS (mode register set) mode from a clock time later by one clock cycle period than a clock time when a read or write command is applied from the external. 
         [0012]    The signal rdwtstbzp 13  is a signal to be active for the burst length set by the MRS mode, being activated in sync with the signals of the burst operation command (external=exryp 8  &amp; internal=icasp 61 ). In other words, the signal rdwtstbzp 13  is to be used to inform an activation time of the input/output sense amplifier in amplifying and transferring data, which is to be sent to a peripheral circuit from a core circuit region, to the data output buffer, resetting the data transmission line of the peripheral circuit after completing the data amplification and transmission by the sense amplifier. 
         [0013]    A signal pwrup is a signal to set an initial data value, retaining low level after falling down to low level from high level. Signal term_z is a signal used in a test mode being held on low level during a normal operation. A signal tm_clkpulsez is used in a test mode. Such signals will be described in detail in conjunction with embodiments of the present invention hereinafter. 
         [0014]    A circuit operation of  FIG. 2A  is illustrated, as follows, with reference to the waveform diagram of  FIG. 2B . 
         [0015]    As illustrated in  FIG. 2B , when the read/write command is applied to the memory device in sync with the clock signal clock, the pulse signal extyp 8  is generated. If the pulse signal extyp 8  is enabled, a plurality of pulse signals icasp 6  is generated in sync with the next clocks in sequence. As shown in  FIG. 2B , the read/write strobe pulse signal rdwtstbzp 13  is generated in sync with rising edges of the pulse signals extyp 8  and icasp 6 . 
         [0016]    Here, in the conventional circuit shown in  FIG. 2A , it can be seen that the pulse width of the read/write strobe pulse signal rdwtstbzp 13  generated from a pulse width adjusting circuit  200  is fixed nevertheless of the operating frequency of the memory device. Here, a delay time from a node A from a node D is determined by a delay circuit  20 . As the delay time of the delay circuit  20  in the pulse width adjusting circuit  200  is fixed, the pulse width of the signal outputted from the pulse width adjusting circuit  200  is always constant without regarding to the operating frequency of the memory device. 
         [0017]    But, it needs to adjust a pulse width of the read/write strobe pulse signal rdwtstbzp 13  when an operating frequency of the memory device varies. In a conventional art, while the delay time of the delay circuit  20  is variable by modifying a metal option during a FIB process when an operating frequency of the memory device varies, it needs much costs and times. 
         [0018]    In addition, with the conventional art, there is no way to correct a variation of the pulse width of the read/write strobe pulse signal rdwtstbzp 13  when an operation voltage of the memory device varies. 
       SUMMARY OF THE INVENTION 
       [0019]    Accordingly, the present invention has been made in an effort to solve the problems occurring in the related art, and an object of the present invention is to provide a method of automatically controlling a pulse width of a signal output from a pulse width adjusting circuit in accordance with variation of an operating frequency of a memory device. 
         [0020]    Another object of the present invention is to provide a method of controlling a pulse width of a read/write strobe pulse signal rdwtstbzp 13  in correspondence with variation of an external clock signal. 
         [0021]    In order to achieve the above object, according to one aspect of the present invention, there is provided a read/write strobe pulse generator generally usable even when an operating frequency of a memory device varies. 
         [0022]    According to another aspect of the present invention, there is also provided a method of delaying a signal outputted from a read/write strobe pulse generator by applying an external address signal and controlling a width of the read/write pulse. 
         [0023]    According to still another aspect of the present invention, what&#39;s provided is a method of controlling a pulse width of a read/write strobe pulse signal rdwtstbzp 13  in accordance with variation of an operation voltage of a memory device. 
         [0024]    By the features of the present invention, an embodiment of the present invention is a circuit for controlling an enabling period of an internal control signal in accordance with variation of an operating frequency in a memory device, which comprises a pulse width adjusting circuit for changing a pulse width of an input signal in accordance with the operating frequency; a signal transmission circuit for buffing a signal outputted from the pulse width adjusting circuit; and an output circuit for outputting a first signal to control an operation of a data bus of the memory device in response to a signal output from the signal transmission circuit. 
         [0025]    In this embodiment, the pulse width adjusting circuit comprises a first delay circuit and a NAND gate, in which the NAND gate receives the input signal and an output signal of the first delay circuit, and the first delay circuit receives the input signal and a clock signal of the memory device and adjusts a delay time in accordance with a frequency of the clock signal until the input signal is applied to an input terminal of the NAND gate. 
         [0026]    In this embodiment, as a cycle period of the clock signal is shorter, a pulse width of the first signal is narrower. 
         [0027]    Another embodiment of the present invention is a method for controlling an enabling period of an internal control signal in accordance with variation of an operating frequency in a memory device, which comprises the steps of: (a) receiving an input signal; (b) delaying the input signal for a predetermined time; (c) operating the input signal and a signal delayed from the input signal in a NAND logic; and (d) outputting a result of operating the NAND logic. 
         [0028]    In this embodiment, it further comprises the step of: (b-1) determining the predetermined time of the step (b) in accordance with a frequency of a clock signal of the memory device. 
         [0029]    In this embodiment, as the frequency of the clock signal increases, a pulse width of a signal outputted from the step (d) is narrower. 
         [0030]    In this embodiment, it further comprises the step of (b-2) more reducing a pulse width of a signal outputted from the step (d) by using an address signal of the memory device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0031]    The above objects, and other features and advantages of the present invention will become more apparent after a reading of the following detailed description when taken in conjunction with the drawings, in which: 
           [0032]      FIG. 1  is a diagram illustrating a read and write operation in a general memory device; 
           [0033]      FIG. 2A  illustrates an example of a conventional read/write strobe pulse generator; 
           [0034]      FIG. 2B  is a waveform diagram of signals used in the circuit shown in  FIG. 2A ; 
           [0035]      FIG. 3  illustrates an exemplary embodiment of a read/write strobe pulse generator in accordance with the present invention; 
           [0036]      FIGS. 4 through 10  illustrate embodiments of a delay circuit  30  in a pulse width adjusting circuit  300  shown in  FIG. 3 ; 
           [0037]      FIG. 11  is an operational timing diagram of the conventional circuit shown in  FIG. 2A ; 
           [0038]      FIG. 12  is a waveform diagram illustrating a pulse width variation of the read/write strobe pulse signal rdwtstbzp 13  output from the conventional circuit of  FIG. 2A  when an operation voltage vdd of a memory device varies; 
           [0039]      FIG. 13  is a waveform diagram of signals used in the circuit of the present invention, specifically an exemplary waveform diagram of signals used in the circuit of  FIG. 5 ; 
           [0040]      FIG. 14  is a diagram illustrating a procedure of changing logical levels of flag signals Flag 1  and Flag  2  in accordance with a frequency of a clock signal clk_in; 
           [0041]      FIG. 15  is a diagram illustrating a waveform of an output signal rdwtstbzp 13  when paths C 1  and C 2  shown in  FIG. 10  are used therein; and 
           [0042]      FIG. 16  is a waveform diagram illustrating a variation of the output signal rdwtstbzp 13  in accordance with a variation of the operation voltage. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0043]    Reference will now be made in greater detail to a preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts. 
         [0044]      FIG. 3  illustrates an exemplary embodiment of a read/write strobe pulse generator in accordance with the present invention. 
         [0045]    The circuit of  FIG. 3  is different from the circuit of  FIG. 2A  in that a delay circuit  30  in a pulse width adjusting circuit  300  is controlled by a clock signal clk_in and address signals add_ 0  and add_ 1 . 
         [0046]    The circuit of  FIG. 3  is comprised of an input signal receiver  310 , a pulse width adjusting circuit  300 , a signal transmission circuit  320 , a test mode circuit  330 , and an output circuit  340 . 
         [0047]    The input signal receiver  310  includes inverters INV 30  and INV 31 , and a NAND gate NAND 30 . An input signal extyp 8  is applied to the inverter INV 30  and an input signal icasp 6  is applied to the inverter INV 31 . Output signals of the inverters INV 30  and INV 31  are applied to the NAND gate NAND 30 . 
         [0048]    The pulse width adjusting circuit  300  includes the delay circuit  30  and the NAND gate NAND 31 . 
         [0049]    The delay circuit  30  receives an output signal of the NAND gate NAND 30 , a test mode signal tmz_l, the clock signal clk_in, and the address signals add_ 0  and add_ 1 . 
         [0050]    The NAND gate NAND 31  receives the output signal of the NAND gate NAND 30  and an output signal of the delay circuit  30 . An output signal of the pulse width adjusting circuit  300  is an output signal of the NAND gate NAND 31 . A delay time from a node A to a node D is determined by the delay circuit  30 . The delay time by the delay circuit  30  is adjustable by means of a frequency of the clock signal clk_in and the address signals add_ 0  and add_ 1 . In reference, the test mode signal tmz_l is a control signal to determine whether or not a current operation is a test mode, retaining low level during the test mode while retaining high level during a normal operation mode. The add_ 0  and add_ 1  are external address signals to be used in the test operation mode. Functions of the signals will be explained relative to the detail circuit hereinafter. 
         [0051]    The signal transmission circuit  320  includes inverters INV 32 , INV 33 , and INV 34  that, receive and buff the signal outputted from the pulse width adjusting circuit  300 . 
         [0052]    The test mode circuit  330  includes transistors P 31 , P 32 , and N 31  and a latch circuit  301 . As illustrated in  FIG. 3 , the PMOS transistor P 31  and the NMOS transistor N 31  are connected between a power source voltage and a ground in series. The PMOS transistor P 32  is connected between the power source voltage and a node NODE 31 . The latch  301  temporarily stores a signal of the node NODE 31 . Here, termz is a signal used in the test mode and the signal pwrup is that as stated in  FIG. 2A . 
         [0053]    The output circuit  340  includes a NAND gate  302  and inverters INV 35  and INV 36 . The NAND gate  302  receives an output signal of the inverter INV 34 , the signal termz, and an output signal of the latch circuit  301 . The signal termz functions to inhibit the read/write strobe pulse signal rdwtstbzp 13 . An output signal of the NAND gate  302  is applied to the inverters INV 35  and INV 36  serially connected from each other. An output signal of the inverter INV 36  as an output signal of the output circuit  340  becomes the read/write strobe pulse signal rdwtstbzp 13 . 
         [0054]    In a normal operation, the input signals extyp 8  and icasp 6  are generated into the read/write strobe pulse signal rdwtstbzp 13  after a predetermined time. During this, it is possible for the pulse width adjusting circuit  300  to control a pulse width of the read/write strobe pulse signal rdwtstbzp 13  by modifying a pulse width of the input signals extyp 8  and icasp 6  with using the clock signal clk_in that varies dependent on variation of an operating frequency. 
         [0055]      FIGS. 4 through 10  illustrate embodiments of the delay circuit  30  in the pulse width adjusting circuit  300  shown in  FIG. 3 . As described later, the clock signal clk_in is applied to the delay circuit  30  so as to detect an operating frequency of the memory device. And, at the beginning of the test mode, the test mode signal tmz_l of low level is applied thereto. Also, at the beginning of the test mode, the address signals add_ 0  and add_ 1  are applied to further tune a delay time. In reference, the node A and D shown in  FIG. 3  correspond to those node A and D shown in  FIG. 4 . 
         [0056]    Hereinafter, it will be described in more detail about the circuits shown in  FIGS. 4 through 10 . 
         [0057]      FIG. 4  is a block diagram illustrating an internal structure of the delay circuit shown in  FIG. 3  in detail. 
         [0058]    As illustrated in  FIG. 4 , the delay circuit  30  in  FIG. 3  is comprised of delay units  401 ,  402 , and  403 , a frequency detector  404 , a voltage detector  405 , a test mode address signal receiver  406 , and a reference voltage generator  407 . Exemplary circuits of the frequency detector  404 , the voltage detector  405 , and the test mode address signal receiver  406  are shown in  FIGS. 4 ,  5 , and  6 , respectively. 
         [0059]    In  FIG. 4 , the frequency detector  404  receives the clock signal clk_in and then outputs operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  which control a delay path of the delay unit  401 . Logical levels of the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  vary in accordance with a frequency of the clock signal clk_in. The delay path from the node A to the node D is alterable in accordance with a frequency of the clock signal clk_in. 
         [0060]    The reference voltage generator  407  is enabled by the power-up signal pwrup, outputting a plurality of reference voltages vref_ 0  and vref_ 1 . The reference voltage generator  407  is a circuit capable of outputting stable reference voltages without affecting from an operation voltage, which is constructed with circuit structures well known by those skilled in this art. 
         [0061]    The voltage detector  405  detects a variation of the operation voltage vdd by comparing the operation voltage vdd to the reference voltages vref_ 0  and vref_ 1 . The voltage detector  405  outputs a plurality of voltage selection signals vsel_ 0   z , vsel_ 1   z , and vsel_ 2   z  to control the delay path of the delay unit  402 . Thus, delay times of delay paths C 1  are determined by logical level of the voltage selection signals vsel_ 0   z , vsel_ 1   z , and vsek_ 2   z.    
         [0062]    In accordance with a logical level of the test mode signal tmz_ 1 , a signal of the node C 1  can be transferred to the node D directly or through the delay unit  403 . When the test mode signal tmz_ 1  is high level, the signal of the node C 1  is transferred directly to the node D. 
         [0063]    The test mode address signal receiver  406  receives an address signal and outputs a plurality of selection signals sel_ 0   z , sel_ 1   z , sel_ 2   z , and sel_ 3   z . Responding to the selection signals sel_ 0   z , sel_ 1   z , sel_ 2   z , and sel_ 3   z , a delay time of the delay unit  403  is adjusted. As aforementioned, the delay unit  403  is used as a delay path in the test mode, which means that it is possible to conduct an additional delay tuning operation by using the address signal when the test mode signal tmz_ 1  is being low level. 
         [0064]    Exemplary features of the components shown in  FIG. 4  are illustrated in  FIGS. 5 through 10 . 
         [0065]      FIG. 5  illustrates, as an example of the frequency detector  404  shown in  FIG. 4 , a circuit for outputting the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  that determine a range of the operating frequency of the memory device in response to the clock signal clk_in. 
         [0066]    In  FIG. 5 , after detecting an operating frequency of the memory device by generating a plurality of internal signals dlic 4 _ref, dlic 4 , dlic 4   d   1 , dlic 4   d   2 , cmp, flag_ 1 , and flag_ 2  in response to the clock signal clk_in, the operating frequency detection signals dec_pz, dec_ 1   z , and dec_ 2   z  are finally outputted therefrom to be determined the range of the operating frequency of the memory device. 
         [0067]    As illustrated in  FIG. 5 , the clock signal clk_in is applied to a frequency divider  500 . The divider  500  outputs the frequency dividing signal dlic 4 _ref having a period longer than that of the clock signal clk_in. As shown in the waveform diagram of  FIG. 13 , a cycle period of the frequency dividing signal dlic 4 _ref is four times of that of the clock signal clk_in. At this case, a low level term of the frequency dividing signal dlic 4 _ref is identical to the cycle period tCLK of the clock signal clk_in. However, the cycle period of the frequency dividing signal dlic 4 _ref may be alterable by those skilled in this art. 
         [0068]    The frequency dividing signal dlic 4 _ref is outputted with phase inversion after being delayed by a buffer circuit  501  composed of odd-numbered inverters. The phase-inversed frequency dividing signal is denoted as dlic 4 . Waveforms of those signals dlic 4 _ref and dlic 4  are shown in  FIG. 13 . 
         [0069]    In  FIG. 5 , the frequency dividing signal dlic 4 _ref and the phase-inversed frequency dividing signal dlic 4  are applied to a NAND gate NAND 51 . An output signal from the NAND gate NAND 51  is applied to a delay unit  506  and a NOR gate NOR 51 . The NOR gate NOR 51  receives the output signal of the NAND gate NAND 51  and an output signal of the delay unit  506 , and outputs the pulse signal cmp. The output signal cmp of the NOR gate NOR 51  is illustrated in  FIG. 13 . The phase-inversed frequency dividing signal dlic 4  is applied to delay units delay_A and delay_B. Here, there is a difference between delay times of the delay units delay_A and delay_B. Output signals of the delay units delay_A and delay_B are represented to as dlic 4   d   1  and dlic 4   d   2 , respectively. 
         [0070]    The output signal dlic 4   d   1  of the delay unit delay_A and the frequency dividing signal dlic 4 _ref are applied to a flipflop circuit  502 . The flipflop circuit  502  is constructed of two NAND gates input/output terminals of which are cross-coupled each other. Output signals from two output terminals of the flipflop circuit  502  are e and f, respectively. 
         [0071]    The output signal dlic 4   d   2  of the delay unit delay_B and the frequency dividing signal dlic 4 _ref are applied to a flipflop circuit  503 . The flipflop circuit  503  is constructed of two NAND gates input/output terminals of which are cross-coupled each other. Output signals from two output terminals of the flipflop circuit  503  are g and h, respectively. 
         [0072]    A NAND gate NAND 52  receives the output signal cmp of the NOR gate NOR 51  and the output signal e of the flip-flop circuit  502 . A NAND gate NAND 53  receives the output signal cmp of the NOR gate NOR 51  and the output signal if of the flipflop circuit  502 . A NAND gate NAND 54  receives the output signal cmp and the output signal g of the flip-flop circuit  503 . A NAND gate NAND 55  receives the output signal cmp of the NOR gate NOR 51  and the output signal h of the flipflop circuit  503 . 
         [0073]    Output signals of the NAND gates NAND 52  and NAND 53  are applied to the flipflop circuit  504 . The flipflop circuit  504  is constructed of two NAND gates input/output terminals of which are cross-coupled each other. An output signal of the flipflop circuit  504  is represented to as a flag signal flag_ 1 . 
         [0074]    Output signals of the NAND gates NAND 54  and NAND 55  are applied to the flipflop circuit  505 . The flipflop circuit  505  is constructed of two NAND gates input/output terminals of which are cross-coupled each other. An output signal of the flipflop circuit  505  is represented to as a flag signal flag_ 2 . 
         [0075]    In reference, when a delay time by delay unit  508  is longer than that by delay unit  507  (i.e., delay_A&lt;delay_B), logical levels of the flag signals are as follows. 
         [0076]    If tCLK&lt;delay_A, the flag signals flag_ 1  and flag_ 2  are all low levels. Here, tCLK is a cycle period of the clock signal clk_in. 
         [0077]    If delay_A&lt;tCLK&lt;delay_B, the flag signal flag_ 1  is high level while the flag signal flag_ 2  is low level. 
         [0078]    If tCLK&gt;delay_B, the flag signal flag_ 1  and flag_ 2  are all high levels. 
         [0079]    In  FIG. 5 , the flag signals flag_ 1  and flag_ 2  are applied each to inverters INV 51  and INV 52 . Output signals of the inverters INV 51  and INV 52  are applied to NAND gate NAND 56 . The NAND gate NAND 56  outputs the operating frequency detection signal dec_ 0   z.    
         [0080]    Next, the flag signal flag_ 2  is applied to an inverter INV 53 . An output signal of the inverter INV 53  and the flag signal flag_ 1  are applied to a NAND gate NAND 57 . The NAND gate NAND 57  outputs the operating frequency detection signal dec_ 1   z.    
         [0081]    Finally, the flag signals flag_ 1  and flag_ 2  are applied to a NAND gate NAND 58 . The NAND gate NAND 58  outputs the operating frequency detection signal dec_ 1   z.    
         [0082]      FIG. 6  is a circuit for outputting voltage selection signals vsel_ 2   z , vsel_ 1   z , and vsel_ 0   z  so as to control a delay time of an input signal in accordance with variation of an operation voltage. The voltage selection signals generated in  FIG. 6  are used for selecting a delay path of a circuit shown in  FIG. 9 . 
         [0083]      FIG. 6  illustrates two differential amplifying comparators. As shown in  FIG. 6 , there are a differential amplifying comparator for comparing the operation voltage vdd to the reference voltage vref_ 0  and another differential amplifying comparator for comparing the operation voltage vdd to the reference voltage vref_ 1 . The reference voltage vref_ 0  is lower than the reference voltage vref_ 1  (vref_ 0 &lt;vref_ 1 ). 
         [0084]    As noticed from  FIG. 6 , if vdd&lt;vref_ 0 , output signals DET_ 0  and DET_ 1  of the differential amplifying comparator are all high levels. 
         [0085]    If vref_ 0 &lt;vdd&lt;vref_ 1 , the output signal DET_ 0  is high level while the output signal DET_ 1  is low level. 
         [0086]    If vdd&gt;vref_ 1 , the output signals DET_ 0  and DET_ 1  of the differential amplifying comparator are all low levels. 
         [0087]    The output signal DET_ 0  of the differential amplifying comparator is applied to an inverter INV 61  and an output signal of the inverter INV 61  is DET_ 0   b . The output signal DET_ 1  of the differential amplifying comparator is applied to an inverter INV 62  and an output signal of the inverter INV 62  is DET_ 1   b.    
         [0088]    In  FIG. 6 , NAND gate NAND 61  receives the signals DET_ 0   b  and DET_ 1   b  and an output signal of the NAND gate NAND 61  is the voltage selection signal vsel_ 2   z.    
         [0089]    A NAND gate NAND 62  receives the signals DET_ 0   b  and DET_ 1   b  and an output signal of the NAND gate NAND 62  is the voltage selection signal vsel_ 1   z.    
         [0090]    A NAND gate NAND 63  receives the signals DET_ 0  and DET_ 1  and an output signal of the NAND gate NAND 63  is the voltage selection signal vsel_ 0   z.    
         [0091]    As can be seen by  FIG. 6 , the circuits of  FIG. 6  are provided to detect a fluctuation of the operation voltage vdd relative to the reference voltages vref_ 0  and vref_ 1 . 
         [0092]      FIG. 7  illustrates circuit elements for generating the selection signals sel_ 3   z , sel_ 2   z , sel_ 1   z , and sel_ 0   z  to designate delay paths in response to the address signals add_ 0  and add_ 1 . 
         [0093]    As illustrated in  FIG. 7 , an inverter INV 71  receiving the address signal add_ 0  outputs a phase-inversed address signal add_ 0   b . An inverter INV 72  receiving the address signal add_ 1  outputs phase-inversed address signal add_ 1   b . Next, the delay path selection signals sel_ 3   z , sel_ 2   z , sel_ 1   z , and sel_ 0   z  are generated resulting from logical combinations with the address signals. That is, the NAND gate NAND 71  receives the address signals add_ 0   b  and add_ 1   b  and then outputs the selection signal sel_ 3   z . The NAND gate NAND 72  receives the address signals add_ 0   b  and add_ 1  and then outputs the selection signal sel_ 2   z . The NAND gate NAND 73  receives the address signals add_ 0  and add_ 1   b  and then outputs the selection signal sel_ 1   z . The NAND gate NAND 74  receives the address signals add_ 0  and add_ 1  and then outputs the selection signal sel_ 0   z.    
         [0094]      FIG. 8 , as an exemplary feature of the delay circuit  30 , shows an example of a circuit for selecting a delay path of an input signal with using the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  that are generated in  FIG. 5 . 
         [0095]    The circuit of  FIG. 8  comprises a plurality of delay units  801 ,  802 ,  803 , and  804 , and switching units  811 ,  812 ,  814 ,  815 , and  816  which are controlled by the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z . Each of modulation circuits  817  and  818  is composed of a NAND gate and an inverter which are connected in series. Input terminals of the modulation circuits  817  and  818  receive a signal of the node A. 
         [0096]    In  FIG. 8 , the whole delay time is taken from the node A to the node D. Here, the nodes A and D of  FIG. 8  are the same with the nodes A and D of  FIG. 3 . 
         [0097]    A signal input through the node A of  FIG. 8  is an output signal from the input signal receiver  310  of  FIG. 3 , which is the signal extyp 8  or icasp 6 . 
         [0098]    In  FIG. 8 , the operating frequency detection signals dec_ 1   z  and dec_ 2   z  control turn-on/off operations of the switching units  811  and  814 . The operating frequency detection signal dec_ 0   z  controls a turn-on/off operation of the switching unit  812 . The operating frequency detection signal dec_ 2   z  controls a turn-on/off operation of the switching unit  815 . The test mode signal tmz_ 1  controls a turn-on/off operation of the switching unit  816 . 
         [0099]    In operation, when a NAND gate NAND 81  receiving the operating frequency detection signals dec_ 1   z  and dec- 2   z  outputs a high-level output signal, the switching units  811  and  814  are turned on. Thus, the input signal received through the node A passes by way of the delay unit  801 , the modulation circuit  817 , the delay unit  802 , the modulation circuit  818 , and the switching unit  814 , in sequence. Here, the switching unit  815  is controlled by the operating frequency detection signal dec_ 2   z . Therefore, while a signal passing through the switching unit  814  is transferred to the node B through the delay unit  804  when the operating frequency detection signal dec_ 2   z  is low level, it is transferred directly to the node C when the operating frequency detection signal dec_ 2   z  is high level. 
         [0100]    In operation, when the switching unit  812  is turned on in response to the operating frequency detection signal dec_ 0   z , the input signal received through the node A passes by way of the delay unit  801 , the modulation circuit  817 , and the switching unit  812 , in sequence. Here, the switching unit  815  is controlled by the operating frequency detection signal dec_ 2   z . While a signal passing through the switching unit  812  is transferred to the node B through the delay unit  804  when the operating frequency detection signal dec_ 2   z  is low level, it is transferred directly to the node B when the operating frequency detection signal dec_ 2   z  is high level. 
         [0101]    Next, a signal on the node B is transferred to the node C 1  through the switching unit  816 . A signal at the node C 1  may be transferred to the node D through the switching unit  816  directly or transferred to the node D through the delay path of C 1 -C 2 -D. 
         [0102]    Hereinafter, it will be described in detail about the alternative delaying operations. 
         [0103]    Referring to  FIG. 8 , the switching unit  816  is turned on/off by the test mode signal tmz_ 1 . In a test mode, the test mode signal tmz_ 1  retains low level. In a normal operation mode, the test mode signal retains high level. 
         [0104]    In the normal operation mode, a signal on the node C 1  is forwarded to a delay path of C 1 -D. In other words, the signal on the node C 1  is transferred to the node D by way of the switching unit  816 , an inverter INV 81 , and a NAND gate NAND 83 . Here, the NAND gate NAND 83  receives signals output from the inverter INV 81  and the node A. 
         [0105]    In the test mode, the signal on the node C 1  is transferred to the node C 2  through the circuit shown in  FIG. 10 . The signal transferred to the node C 2  is transferred to the node D by way of the switching unit  816 , the inverter INV 81 , and the NAND gate NAND 83 . 
         [0106]      FIG. 9  illustrates a circuit disposed on a delay path of B-C 1 . The delay path circuit of  FIG. 9  is selected by the voltage selection signals vsel_ 2   z , vsel_ 1   z , and vsel_ 0   z  which are generated in  FIG. 6 . 
         [0107]    As illustrated, the circuit of  FIG. 9  is comprised of delay units  901 ,  902 , and  903 , switching units  911 ,  912 ,  913 , and  914 , and NAND gates NAND 91  and NAND 92 . 
         [0108]    The NAND gates NAND 91  and NAND 92  receive the voltage selection signals vsel_ 1   z  and vsel_ 0   z . The switching unit  911  is turned on/off by an output signal of the NAND gate NAND 91 . The switching unit  913  is turned on/off by an output signal of the NAND gate NAND 92 . The switching unit  912  is turned on/off by the voltage selection signal vsel_ 2   z . The switching unit  914  is turned on/off by the voltage selection signal vsel_ 0   z.    
         [0109]    In operation, if the switching units  911  and  913  are turned on, a signal on the node B passes through the delay unit  901 , the switching unit  911 , the delay unit  911 , and the switching unit  913 , in sequence. A delay path of the signal passing through the switching unit  913  is alterable in accordance with the voltage selection signal vsel_ 0   z . That is, when the voltage selection signal vsel_ 0   z  is high level, the signal passing through the switching unit  913  is transferred to the node C 1  by way of the switching unit  914 . Otherwise, when the voltage selection signal vsel_ 0   z  is low level, the signal passing through the switching unit  913  is transferred to the node C 1  by way of the delay unit  903  and the switching unit  914 . 
         [0110]    In operation, if the switching unit  912  is turned on, a signal on the node B passes through the delay unit  901  and the switching unit  912 . A delay path of the signal passing through the switching unit  912  is alterable in accordance with the voltage selection signal vsel_ 0   z . That is, when the voltage selection signal vsel_ 0   z  is high level, the signal passing through the switching unit  912  is transferred to the node C 1  by way of the switching unit  914 . Otherwise, when the voltage selection signal vsel_ 0   z  is low level, the signal passing through the switching unit  912  is transferred to the node C 1  by way of the delay unit  903  and the switching unit  914 . 
         [0111]      FIG. 10 , as an exemplary feature of a circuit interposed between the nodes C 1  and C 2 , illustrates a circuit for controlling a delay rate with using address signals in a test mode (when tmz_ 1  of  FIG. 8  is low level). 
         [0112]    The circuit of  FIG. 10  is comprised of delay units  1000 ,  1001 ,  1002 ,  1003 , and  1004 , switching units  1011 ,  1012 ,  1013 ,  1014 , and  1015  which are controlled by the selection signals sel_ 3   z , sel_ 2   z , sel_ 1   z , and sel_ 0   z , and conversion circuits  1017  and  1018 . Each of the conversion circuits  1017  and  1018  is a NAND gate and an inverter which are connected in series. A signal of the node C 1  is inputted through input terminals of the conversion circuits  1017  and  1018 . In  FIG. 10 , the whole delay time is taken from the node C 1  to the node C 2 . Here, the nodes C 1  and C 2  are identical to the nodes C 1  and C 2  shown in  FIG. 8 . And, a signal of the node C 1  is inputted through an input terminal of NAND gate NAND 103 . 
         [0113]    As stated above in connection with  FIG. 7 , the selection signals sel_ 3   z , sel_ 2   z , sel_ 1   z , and sel_ 0   z , which control turn-on/off operations of the switching units, are made from logical combinations with address signals. 
         [0114]    As can be seen from  FIGS. 7 and 10 , when the address signals add_ 0  and add_ 1  are all low levels, the selection signal sel_ 3   z  is enabled in low level. When the address signals add_ 0  and add_ 1  are respectively low and high levels, the selection signal sel_ 2   z  is enabled in low level. When the address signals add_ 0  and add_ 1  are respectively high and low levels, the selection signal sel_ 1   z  is enabled in low level. When the address signals add_ 0  and add_ 1  are all high levels, the selection signal sel_ 0   z  is enabled in low level. 
         [0115]    In  FIG. 10 , NAND gates NAND 101  and NAND 102  receive the selection signals sel_ 2   z  and sel_ 3   z . The switching unit  1011  is turned on/off by an output signal of the NAND gate NAND 101 . The switching unit  1014  is turned on/off by an output signal of the NAND gate NAND 102 . The switching unit  1012  is turned on/off by the selection signal sel_ 1   z . The switching unit  1013  is turned on/off by the selection signal sel_ 0   z . The switching unit  1015  is turned on/off by the selection signal sel_ 3   z.    
         [0116]    In operation, when the selection signals sel_ 2   z  and sel_ 3   z  are all low levels, an output signal of the NAND gate NAND 101  receiving the selection signals sel_ 2   z  and sel_ 3   z  is high level. Thus, the switching units  1011  and  1014  are turned on. As a result, a signal receiver through the node C 1  passes through the delay units  1000  and  1001 , the conversion circuit  1017 , the delay unit  1001 , the switching unit  1011 , the delay unit  1001 , the conversion circuit  1018 , and the switching unit  1014 , in sequence. Here, if the selection signal sel_ 3   z  is low level, the signal passing through the switching unit  1014  is transferred to the node C 2  by way of the NAND gate NAND 103  and inverter INV 101  after passing through the delay unit  1004  and the switching unit  1015 . Otherwise, if the selection signal sel_ 3   z  is high level, the signal passing through the switching unit  1014  is transferred to the node C 2  by way of the switching unit  1015 , the NAND gate NAND 103 , and inverter INV 101 . Therefore, when the selection signals sel_ 2   z  and sel_ 3   z  are all low levels, the signal passing through the switching unit  1014  is transferred to the node C 2  by way of the NAND gate NAND 103  and the inverter INV 101  after passing through the delay unit  1004 . 
         [0117]    In operation, when the selection signal sel_ 1   z  is low level, the switching unit  1012  is turned on. Thus, a signal input through the node C 1  passes through the delay units  1000  and  1001 , the conversion circuit  1017 , the delay unit  1002 , and the switching unit  1012 , in sequence. If the selection signal sel_ 3   z  is low level, the signal passing through the switching unit  1012  is transferred to the node C 2  by way of the NAND gate NAND 103  and the inverter INV 101  after passing through the delay unit  1004  and the switching unit  1015 . Otherwise, if the selection signal sel_ 3   z  is high level, the signal passing through the switching unit  1012  is transferred to the node C 2  by way of the switching unit  1015 , the NAND gate NAND 103 , and the inverter INV 101 . 
         [0118]    In operation, when the selection signal sel_ 0   z  is low level, the switching unit  1013  is turned on. Thus, a signal input through the node C 1  passes through the delay unit  1000  and the switching unit  1013 , in sequence. If the selection signal sel_ 3   z  is low level, the signal passing through the switching unit  1013  is transferred to the node C 2  by way of the NAND gate NAND 103  and inverter INV 101  after passing through the delay unit  1004  and the switching unit  1015 . Otherwise, if the selection signal sel_ 3   z  is high level, the signal passing through the switching unit  1013  is transferred to the node C 2  by way of the switching unit  1015 , the NAND gate NAND 103 , and inverter INV 101 . 
         [0119]    As illustrated in  FIG. 10 , in the test mode, it is possible to adjust a delay time taken from the node C 1  to the node C 2  by using the selection signals generated from logical combinations with the external address signals add_ 0  and add_ 1 . For example, when the test mode signal tmz_ 1  is high level, the delay path between the nodes C 1  and C 2  is inhibited. 
         [0120]    But, if the test mode signal tmz_ 1  is low level, the delay path between the nodes C 1  and C 2  is open and adjustable by means of the selection signals. 
         [0121]      FIG. 11  is an operational timing diagram of the conventional circuit shown in  FIG. 2A . 
         [0122]    As can be seen from  FIG. 11 , the conventional circuit is just capable of adjusting only a pulse width of the output signal rdwtstbzp 13  in accordance with a logical level of a signal tmz_clkpulsez. 
         [0123]      FIG. 12  is a waveform diagram illustrating a pulse width variation of the read/write strobe pulse signal rdwtstbzp 13  output from the conventional circuit of  FIG. 2A  when an operation voltage vdd of a memory device varies. 
         [0124]    As illustrated in  FIG. 12 , the conventional circuit has a problem that a pulse width of the read/write strobe pulse signal rdwtstbzp 13  decreases when the operation voltage rises. 
         [0125]      FIG. 13  is a waveform diagram of signals used in the circuit of the present invention, specifically an exemplary waveform diagram of signals used in the circuit of  FIG. 5 .  FIG. 13  illustrates waveforms of the clock signal clk_in, the frequency dividing signal dlic 4 _ref, the phase-inversed frequency dividing signal dlic 4 , the delay signals dlic 4   d   1  and dlic 4   d   2 , the pulse signal amp, the flag signals flag_ 1  and flag_ 2 , and the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z.    
         [0126]    In  FIG. 13 , the cycle period of the frequency dividing signal dlic 4 _ref is four times of tCLK. And, the low level term of the frequency dividing signal dlic 4 _ref is identical to that of tCLK. The phase-inversed frequency dividing signal dlic 4  is opposite to the frequency dividing signal dlic 4 _ref in phase and generated with a predetermined delay time. 
         [0127]    The phase-inversed frequency signal dlic 4  is outputted as the delay signal dlic 4   d   1  after passing through the delay unit having the delay time of delay_A. The phase-inversed frequency dividing signal dlic 4  is also outputted as the delay signal dlic 4   d   2  after passing through the delay unit having the delay time delay_B. At this case, the phase-inversed frequency dividing signal dlic 4  and the delay signals dlic 4   d   1  and dlic 4   d   2  have high level terms as same as that of tCLK. In  FIG. 13 , it is established of delay_A&lt;delay_B. 
         [0128]    Hereinafter, it will be described in detail about the signal waveform diagram of  FIG. 8  with reference to the circuit of  FIG. 4 . 
         [0129]    In the condition of that the frequency dividing signal dlic 4 -ref, the delay signal dlic 4   d   1  and the pulse signal cmp are all high levels, initial values of the nodes e, f, g, and h in  FIG. 4  are all high levels. In this condition, if the delay signal dlic 4   d   1  changes to high level earlier than the frequency dividing signal dlic 4 _ref, the node e transits to low level. Next, when the pulse signal cmp transits to high level, the node h transits to low level. Thus, the flag signal flag_ 1  becomes high level. 
         [0130]    On the other hand, if the frequency dividing signal dlic 4 _ref changes to high level earlier than the delay signal dlic 4   d   1 , the node f transits to low level. Next, when the pulse signal cmp transits to high level, the node g transits to low level. Thus, the flag signal flag_ 1  becomes low level. 
         [0131]    As described above, it is important in  FIG. 5  that it determines a logical level of the flag signal flag_ 1  in accordance with which one of the two signals dlic 4 _ref and dlic 4   d   1  to be compared transits to high level earlier before the pulse signal cmp goes to high level. 
         [0132]    A procedure of generating the flag signal flag_ 2  is substantially identical to that of the flag signal flag_ 1 , so will be omitted about it. 
         [0133]    On the other side, the delay rates represented by delay_A and delay_B are provided to detect a frequency range of the clock signal clk_in. For instance, in  FIG. 13 , the fact that a rising edge of the delay signal dlic 4   d   1  is earlier than that of the frequency dividing signal dlic 4 _ref means that the delay rate of delay_A is smaller than the cycle period of the clock signal clk_in. As such, the fact that a rising edge of the delay signal dlic 4   d   2  is later than that of the frequency dividing signal dlic 4 _ref means that the delay rate of delay_B is larger than the cycle period of the clock signal clk_in. Therefore, such cases form the relation of delay_A&lt;tCK&lt;delay_B.  FIG. 13  illustrates waveform features satisfying the conditional relation. 
         [0134]      FIG. 14  is a diagram illustrating a procedure of changing logical levels of the flag signals flag_ 1  and flag_ 2  in accordance with a frequency of the clock signal clk_in. For sections A, B, and C of  FIG. 14 , it can be seen of delay_A&lt;delay_B. 
         [0135]    When tCK&lt;delay_A as like the section A of  FIG. 14 , the flag signals flag_ 1  and flag_ 2  are all low levels. 
         [0136]    When delay_A&lt;tCK&lt;delay_B as like the section B of  FIG. 14 , the flag signal flag_ 1  is high level while flag_ 2  is low level. 
         [0137]    When tCK&gt;delay_B as like the section C of  FIG. 14 , the flag signals flag_ 1  and flag_ 2  are all high levels. 
         [0138]    As such, it can be understood that the flag signals include the information for the operating frequency of the memory device. With those flag signals, logical levels of the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  are determined to select the delay path in the circuit shown in  FIG. 8 . 
         [0139]      FIG. 15  is a diagram illustrating a waveform of the output signal rdwtstbzp 13  when paths C 1  and C 2  shown in  FIG. 10  are used therein. As aforementioned, the circuit of  FIG. 10  is to be used in the test mode that begins in response to the test mode signal tmz_ 1  shown in  FIG. 8 . In other words, the delay time is further adjustable by applying the address signals during the test mode. 
         [0140]    The selection signals sel_ 3   z , sel_ 2   z , sel_ 1   z , and sel_ 0   z  are generated from logical combinations with the address signals as aforementioned with reference to  FIG. 7 . 
         [0141]    Section A of  FIG. 15  illustrates waveforms of the input signal extyp 8  and the output signal rdwtstbzp 13  when the operating frequency detection signals dec_ 2   z  and dec_ 1   z  are all high levels while the operating frequency detection signal dec_ 0   z  is low level. 
         [0142]    Section B of  FIG. 15  illustrates waveforms of the input signal extyp 8  and the output signal rdwtstbzp 13  when the operating frequency detection signals dec_ 0   z  and dec_ 2   z  are all high levels while the operating frequency detection signal dec_ 1   z  is low level. 
         [0143]    Section C of  FIG. 15  illustrates waveforms of the input signal extyp 8  and the output signal rdwtstbzp 13  when the operating frequency detection signals dec_ 0   z  and dec_ 1   z  are all high levels while the operating frequency detection signal dec_ 2   z  is low level. 
         [0144]    As can be seen from the sections A, B, and C in  FIG. 15 , a pulse width of the output signal rdwtstbzp 13  is variable in accordance with logical levels of the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  which contain the information for the operating frequency of the memory device. Further, the pulse width of the output signal rdwtstbzp 13  is also variable in accordance with logical levels of the selection signals sel_ 0   z , sel_ 1   z , sel_ 2   z , and sel_ 3   z  when the logical levels of the operating frequency detection signals dec_ 0   z , dec_ 1   z , and dec_ 2   z  are equal from each other (e.g, in the section A). 
         [0145]      FIG. 16  is a waveform diagram illustrating a variation of the output signal rdwtstbzp 13  in accordance with a variation of the operation voltage. 
         [0146]    As illustrated in  FIG. 16 , it can be seen that the pulse width of the output signal rdwtstbzp 13  is variable in accordance with logical levels of the voltage selection signals vsel_ 2   z , vsel_ 1   z , and vsel_ 0   z . In the conventional circuit as shown in  FIG. 12 , a pulse width of the output signal rdwtstbzp 13  decreases along an increase of the operation voltage vdd. However, the present invention is configured, as shown in  FIG. 16 , with that the pulse width of the output signal rdwtstbzp 13  does not decrease even along an increase of the operation voltage vdd. Such a result of simulation, as illustrated in  FIG. 16 , is just provided for notifying an improvement by the present invention over the conventional art. It is also possible to enable the pulse width of the output signal rdwtstbzp 13  to be stable by properly selecting the delay path by means of the voltage selection signals even when the operation voltage varies. 
         [0147]    As apparent from the above description, the present invention provides a method and circuit for controlling a pulse width of the read/write strobe pulse signal rdwtstbzp 13  to control an operation of an Yi pulse signal by detecting an operating frequency of the memory device. 
         [0148]    By utilizing the method and circuit according to the present invention, the pulse width of the read/write strobe pulse signal rdwtstbzp 13  is optimally adjusted to control an enabling period of the Yi pulse signal. 
         [0149]    With the method and circuit of the present invention, as it is possible to automatically adjust a pulse width of the Yi signal, there is no need of an FIB process for tuning delay times whenever an operating frequency varies. Therefore, it downs costs and times relative to the conventional case. 
         [0150]    Moreover, the present invention offers a reliable operation by reducing a pulse width variation of the read/write strobe pulse signal when an operation voltage varies. 
         [0151]    In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.