Abstract:
A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.

Description:
[0001]    This application is a divisional application claiming priority to Ser. No. 10/905,041, filed Dec. 13, 2004. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to semiconductor transistors, and more particularly, to sidewall semiconductor transistors. 
         [0004]    2. Related Art 
         [0005]    In a typical semiconductor transistor, there exist capacitances between the gate contact region and the source/drain contact regions of the transistor. It is desirable to minimize these capacitances. Therefore, there is a need for a novel transistor structure in which the capacitances between the gate contact region and the source/drain contact regions of the transistor are reduced. There is also a need for a method for fabricating the novel transistor structure. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention provides a semiconductor structure, comprising (a) a substrate; and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate, and wherein the semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. 
         [0007]    The present invention also provides a method for fabricating a semiconductor structure, the method comprising (a) providing a substrate, a semiconductor region, a gate dielectric region, and a gate block, wherein the semiconductor region, the gate dielectric region, and the gate block are on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate block, wherein the semiconductor region is electrically insulated from the gate block by the gate dielectric region, wherein the semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate, and wherein the semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate; and (b) forming a gate region from the gate block; and (c) forming first and second source/drain regions in the semiconductor region, wherein the first and second source/drain regions are aligned with the gate region. 
         [0008]    The present invention also provides a method for fabricating a semiconductor structure, the method comprising (a) providing a substrate, a semiconductor region, a gate dielectric region, and a gate block, wherein the semiconductor region, the gate dielectric region, and the gate block are on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate block, wherein the semiconductor region is electrically insulated from the gate block by the gate dielectric region, wherein the semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate, and wherein the semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate; and (b) forming a gate region from the gate block; and (c) using a mask comprising the gate region to form first and second source/drain regions in the semiconductor region 
         [0009]    The present invention provides a novel transistor structure in which the capacitances between the gate contact region and the source/drain contact regions of the transistor are reduced. The present invention also provides a method for fabricating the novel transistor structure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIGS. 1A-1G  show perspective views of a semiconductor structure used to illustrate a transistor fabrication method, in accordance with embodiments of the present invention. 
           [0011]      FIG. 1H  shows a top view of the semiconductor structure of  FIG. 1G  along the plane  1 H, in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]      FIGS. 1A-1G  show perspective views of a semiconductor structure  100  used to illustrate a transistor fabrication method, in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 1A , in one embodiment, the method starts out with providing a substrate  110 . In one embodiment, the substrate  110  can comprise a dielectric material such as silicon dioxide. 
         [0013]    Next, in one embodiment, a semiconductor (e.g., silicon, germanium, etc.) layer  120  can be formed on top of the substrate  110  using any conventional method. 
         [0014]    Next, in one embodiment, a dielectric layer  130  can be formed on top of the semiconductor layer  120  by, illustratively, thermal oxidation. 
         [0015]    Next, in one embodiment, a nitride layer  140  can be formed on top of the dielectric layer  130  by, illustratively, chemical vapor deposition (CVD). 
         [0016]    Next, in one embodiment, a patterned photoresist layer  145  can be formed on top of the nitride layer  140  by, illustratively, a lithography process. 
         [0017]    Next, in one embodiment, the patterned photoresist layer  145  can be used as a mask to etch away only uncovered portions of the nitride layer  140 , then etch away only uncovered portions of the dielectric layer  130 , and then etch away only uncovered portions of the semiconductor layer  120  followed by the removal of the patterned photoresist layer  145 . The resulting structure  100  is shown in  FIG. 1B . After these etching steps, what remains of the semiconductor layer  120  can be referred to as the semiconductor region  120  ( FIG. 1B ). 
         [0018]    Next, with reference to  FIG. 1B , in one embodiment, the method continues with the step of forming a gate dielectric region  150  on a side wall  122  of the semiconductor region  120 . In one embodiment, the gate dielectric region  150  can be formed by thermal oxidation. 
         [0019]    Next, with reference to  FIG. 1C , in one embodiment, a gate block  160  is formed on top of the substrate  110  and on a side wall  152  of the gate dielectric region  150 . In one embodiment, the gate block  160  can comprise poly-silicon. In one embodiment, the gate block  160  can be formed by depositing a gate layer of poly-silicon (not shown) on top of the entire structure  100  of  FIG. 1B  and then planarizing a top surface of the gate layer until a top surface  142  of the nitride layer  140  is exposed to the atmosphere. 
         [0020]    Next, with reference to  FIG. 1D , in one embodiment, a channel cap block  170  can be formed on top of the nitride layer  140  and on a portion of the gate block  160 . In one embodiment, the channel cap block  170  can comprise a dielectric material such as silicon dioxide. In one embodiment, the channel cap block  170  can be formed by a lithography process. 
         [0021]    Next, in one embodiment, a patterned photoresist layer  175  can be formed on top of the channel cap block  170  and the gate block  160 , using, illustratively, a lithography process. 
         [0022]    Next, in one embodiment, the patterned photoresist layer  175  can be used to etch away only uncovered portions of the channel cap block  170 , and then etch away only uncovered portions of the gate block  160 , resulting in the structure  100  of  FIG. 1E . What remains of the channel cap block  170  after these etching steps can be referred to as the channel cap region  170 . Also, what remains of the gate block  160  after these etching steps can be referred to as the gate region  160 . 
         [0023]    Next, with reference to  FIG. 1E , in one embodiment, the patterned photoresist layer  175 , the channel cap region  170 , and the gate region  160  (which can be collectively referred to as the block  160 , 170 , 175 ) can be used as a mask to form extension regions  124   a  and  124   b  in the semiconductor region  120 . The extension region  124   b  is behind the block  160 , 170 , 175  and is not shown in  FIG. 1E  for simplicity, but is shown in  FIG. 1H . In one embodiment, the extension regions  124   a  and  124   b  can be formed by an extension implantation process represented by an arrow  124 ′ whose direction also indicates the direction of the extension ion bombardment. Extension dopant concentration in regions  124   a  and  124   b  can range from 1e19 cm −3  (i.e., 10 19  atoms/cm 3 ) to 5e20 cm −3  (i.e., 5×10 20  atoms/cm 3 ). For an n-type MOSEFET, n-type dopants, such as As (arsenic) and/or P (phosphorus), can be used for extension implantation. For a p-type MOSEFET, p-type dopants, such as B (boron) and/or In (indium), can be used for extension implantation. In one embodiment, the extension implantation process can be followed by an extension anneal process. 
         [0024]    Next, in one embodiment, the block  160 , 170 , 175  can be used again as a mask to form halo regions  126   a  and  126   b  in the semiconductor region  120 . The halo region  126   b  is behind the block  160 , 170 , 175  and is not shown in  FIG. 1E  for simplicity, but is shown in  FIG. 1H . In one embodiment, the halo regions  126   a  and  126   b  can be formed by a halo implantation process represented by an arrow  126 ′ whose direction also indicates the direction of the halo ion bombardment. Halo dopant concentration in regions  126   a  and  126   b  can range from 5e17 cm −3  to 1e19 cm −3 . For an n-type MOSEFET, p-type dopants, such as B and/or In, can be used for halo implantation. For a p-type MOSEFET, n-type dopants, such as As and/or P, can be used for halo implantation. In one embodiment, the halo implantation process can be followed by a halo anneal process. Next, in one embodiment, the patterned photoresist layer  175  can be removed. 
         [0025]    Next, with reference to  FIG. 1F , in one embodiment, gate spacers  180   a  and  180   b  can be formed on side walls of the channel cap region  170  and of a portion the gate region  160 . In one embodiment, the gate spacers  180   a  and  180   b  can be formed by depositing a nitride gate spacer layer (not shown) on top of the entire structure  100  of  FIG. 1E  (with the patterned photoresist layer  175  having been removed) and then etching back the nitride gate spacer layer. 
         [0026]    Next, in one embodiment, the channel cap region  170 , the gate region  160 , and the gate spacers  180   a  and  180   b  (which can be collectively referred to as the block  160 , 170 , 180 ) can be used as a mask to form source/drain (S/D) regions  128   a  and  128   b  by implantation in the semiconductor region  120 . As a result, the S/D regions  128   a  and  128   b  are aligned with the gate region  160 . In one embodiment, the S/D doping concentration in region  120  is higher than 1e19/cm −3  so as to reduce junction capacitance. The S/D region  128   b  is behind the block  160 , 170 , 180  and is not shown in  FIG. 1F  for simplicity, but is shown in  FIG. 1H . In one embodiment, the S/D regions  128   a  and  128   b  can be formed by an S/D implantation process represented by an arrow  128 ′ whose direction also indicates the direction of S/D ion bombardment. S/D dopant concentration in regions  128   a  and  128   b  can range from 1e20 cm −3  to 5e20 cm −3 . For an n-type MOSEFET, n-type dopants, such as As and/or P, can be used for S/D implantation. For a p-type MOSEFET, p-type dopants, such as B and/or In, can be used for S/D implantation. In one embodiment, the S/D implantation process can be followed by an S/D anneal process. 
         [0027]    Next, with reference to  FIG. 1G , in one embodiment, a dielectric gate cover  162  can be formed on top and on side walls of the gate region  160  of  FIG. 1F . In one embodiment, the dielectric gate cover  162  (˜5-10 nm thick) can be formed by thermally oxidizing exposed-to-the-atmosphere surfaces of the structure  100  of  FIG. 1F . Alternatively, the dielectric gate cover  162  can be formed by CVD (chemical vapor deposition) deposition of a thin nitride layer (˜10-20 nm thick) on top and on side walls of the gate region  160  of  FIG. 1F . 
         [0028]    Next, in one embodiment, a gate contact hole  165  can be formed in the dielectric gate cover  162 , and S/D contact holes  125   a  and  125   b  can be formed in the dielectric layer  130 . The S/D contact hole  125   b  is behind the block  160 , 170 , 180  and is not shown for simplicity. In one embodiment, the S/D contact holes  125   a  and  125   b  can be formed symmetrically with respect to the block  160 , 170 , 180 . 
         [0029]    Next, in one embodiment, conventional gate contact and S/D contact processes can be used to form gate contact region and S/D contact regions (not shown, but located in the respective contact holes). In one embodiment, the gate contact region and the S/D contact regions can comprise a silicide such as platinum silicide, NiSi, or CoSi 2 . In one embodiment, metal wires (not shown) can be formed directly attached to these silicide gate contact regions and S/D contact regions so that the underlying gate region  160  and the S/D region  128   a  and  128   b  can be electrically accessed. 
         [0030]      FIG. 1H  shows a top view of the semiconductor structure  100  of  FIG. 1G  along the plane  1 H, in accordance with embodiments of the present invention. 
         [0031]    With reference back to  FIG. 1G , the gate contact hole  165  can be formed away from the semiconductor region  120  (i.e., moved to the right). As a result, the distance between the gate contact region and the S/D contact regions are greater resulting in lower capacitances between the gate contact region and the S/D contact regions. Moreover, comparing with conventional planar MOSFET, this structure has less chance of shorting between S/D via and gate conductor. 
         [0032]    With reference back to  FIG. 1E , the gate region  160  is formed on the sidewall  152  of the gate dielectric region  150 . Therefore, the structure  100  can be referred to as sidewall semiconductor transistor with small overlap capacitance. 
         [0033]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.