Abstract:
A PSE includes a PSE controller that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs, via a switch, if certain conditions are met. Two different levels of currents are supplied to different terminals of the PSE controller that are connected to the data wire pairs and the spare wire pairs, and the resulting voltages are measured. The voltages are used to determine the PD impedances at the ends of the data wire pairs and spare wire pairs to determine whether a PD is connected to the data wire pair, whether another PD is connected to the spare wire pair, or whether a single PD is connected to both the data wire pairs and the spare wire pairs.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority to U.S. provisional application Ser. No. 61/989,316, filed May 6, 2014, by David Dwelley et al. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to Power over Ethernet (PoE) systems, where DC power is generated by Power Sourcing Equipment (PSE) and transmitted over differential data lines to a Powered Device (PD). The invention more particularly relates to a PSE that can detect a variety of possible types of PDs, if any, connected to the data wire pairs and spare wire pairs of the Ethernet cable and appropriately configure its output. 
     BACKGROUND 
     In PoE, limited power is transmitted to Ethernet-connected equipment (e.g., VoIP telephones, WLAN transmitters, security cameras, etc.) from an Ethernet switch. In a PoE system, DC power from the switch is transmitted over one or more twisted wire pairs. The same twisted wire pair may also transmit/receive differential data signals. In this way, the need for providing any external power source for the PDs can be eliminated. The standards for PoE and PoDL are set out in IEEE 802.3 and are well-known. The PSE&#39;s typically include one or more ICs that are specifically designed for a particular PoE configuration and cabling. There are a variety of cabling permutations, such as straight-thru, crossover, and Y-cables. 
     PSEs are sometimes given the option of which twisted wire pairs to power: the data pair and/or the spare pair. Certain high power PoE systems exceed the present IEEE limit of 25.5 W and must send power to the PD(s) over all four pairs simultaneously to share the power load. 
     What is needed is a single PSE design capable of detecting all types of PoE topologies using a single PSE architecture such that the PSE can support a variety of current and future PoE cabling and power permutations. 
     SUMMARY 
     A PSE includes a PSE controller IC that performs a handshaking routine with any PDs connected to the data wire pairs and spare wire pairs and applies power to the data wire pairs and spare wire pairs if certain conditions are met. The PSE controller IC controls a switch (e.g., a MOSFET) to supply the full PoE voltage to the data wire pairs and the spare wire pairs if the conditions are met. 
     An OUT 1  pin of the PSE controller IC supplies test currents to the data wire pairs to determine if a PoE-compatible PD is connected to the data wire pairs. An OUT 2  pin of the PSE controller IC supplies test currents to the spare wire pairs to determine if a PoE-compatible PD is connected to the spare wire pairs. The data wire pairs and spare wire pairs are connected to the switch (supplying the full PoE voltage) via low value resistors. 
     The resistors and switch are also connected to a SENSE pin of the PSE controller IC. 
     By supplying the test currents and detecting the voltages at the various pins, it is determined by the PSE controller IC whether a single PD is connected to all the four wire pairs, or whether a single PD is connected to the data wire pairs, or whether a single PD is connected to the spare wire pair. The PSE controller then closes the switch to supply power to all the wire pairs if certain conditions are met. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a table identifying allowable voltages that may be applied to the 8 wires in a standard CAT-5 Ethernet cable, in accordance with the IEEE standards. 
         FIG. 2  illustrates a prior art PoE system where power is supplied by a single PSE controller IC to a single PD converter via the data wire pairs. 
         FIG. 3  illustrates a prior art PoE system where power is supplied by a single PSE controller IC to a single PD converter via the data wire pairs and the spare wire pairs. 
         FIG. 4  illustrates a prior art PoE system where power is independently supplied by dual PSE controller ICs to associated PD converters via the data wire pairs and the spare wire pairs. 
         FIG. 5  illustrates a prior art PoE system where power is supplied by a single PSE controller IC to a single PD converter via the data wire pairs and to another device via the spare wire pairs. 
         FIG. 6  illustrates a PoE system in accordance with one embodiment of the invention, where handshaking tests are performed to determine whether one or more PoE-compatible devices are connected to the data wire pairs and the spare wire pairs. 
         FIG. 7  illustrates a PoE system in accordance with another embodiment of the invention, where separate PD controllers/converters are connected to the data wire pairs and spare wire pairs, and handshaking tests are performed to determine whether one or more PoE-compatible devices are connected to the data wire pairs and the spare wire pairs. 
     
    
    
     DETAILED DESCRIPTION 
     A PSE technique is described that can detect a variety of types of PoE configurations and then supply the correct power to the wire pairs. In this way, a single PSE product can support a variety of current and future PoE cabling and power permutations. 
     In the various figures, only the power channels of the PoE system are shown. The data channels, supplying differential data to the wire pairs from any source, may be conventional and are not shown. 
     It is important to define the terms cable, pair-set, and pair. A standard Ethernet cable is composed of 8 individual conductors. These are grouped into four twisted pairs. The IEEE PoE standard groups two sets of twisted pairs into Alternative A (Data Pairs) or Alternative B (Spare Pairs). These groups of 4 conductors will be referred to as pair-sets.  FIG. 1  is a chart from the IEEE standards illustrating the allowable voltages that can be applied to the various wires by the PSE. 
     A traditional IEEE two-pair PSE-PD system is shown in  FIG. 2 . A PSE controller IC  12 , in the PSE  14 , performs low voltage/current tests via the data wire pairs  16 ,  17  to detect whether the PD  20  is PoE-compatible and to detect the power requirements of the PD  20 . This is referred to as detection and classification. The PD controller IC  22  operates with the PSE controller IC  12  to perform the handshaking routines. If the PD  20  is PoE-compatible, the PSE  12  provides ground and −55V to the wire pairs  16  and  17 , respectively. These voltages are polarity corrected by the diode bridges in the PD  20 . A DC/DC converter  24  then converts the received voltage to the target voltage Vout needed by the PD load. 
     The PSE controller IC  12  will detect, classify, and provide power via either the data pairs or the spare pairs but not both. The PD  20  must be designed to accept power on either set of pairs. 
       FIG. 3  illustrates a modern four pair PSE-PD system, such as an LTPoE++ system by Linear Technology Corporation. A single PD  28  presents its detection signature (25 kOhm resistor R PD ) on all four pairs using the LTPoE++PD controller IC  30 . The single LTPoE++PSE controller IC  32  detects the PD controller signals on all four pairs and supplies power to the four pairs. In this way, relatively high power may be shared by the four sets of twisted pairs. 
       FIG. 4  illustrates another known topology for transmitting power over the four pairs. In  FIG. 4 , two PSE controller ICs  12 A and  12 B independently operate with two PD controller ICs  22 A and  22 B to determine, in the detection and classification phases, whether to supply power over their associated data wire pairs and spare wire pairs. The DC/DC converters  24 A and  24 B then supply the target voltage in parallel to the PD load. Such a solution is cost prohibitive due to the multiplicity of PSE and PD controllers. 
     In addition, as shown in  FIG. 5 , Y-cables exist which are physically split into two connectors. The PSE side of the cable is composed of a single RJ45 jack containing all four pairs, as normal. The other end of the cable is split into two pair-sets. Each pair set is terminated with a separate RJ45 jack. Thus a single PSE  34  can simultaneously supply power to the PD  28  via the data wire pairs and to a separate device, such as a Network Interface Controller  36 , via the spare wire pairs. The Y-cable  38  by itself is also shown in  FIG. 5 . 
     One drawback of the system of  FIG. 5  is that an LTPoE++ (single PSE/PD, four pair) PSE controller IC  32  may detect a PD controller IC  30  on one pair-set, while the other pair-set is unconnected, and then power all four pairs (both pair-sets.) If the Network Interface Controller  36  was later attached at the second endpoint, it may be damaged if not compatible with the voltage on the spare wire pair. 
     The present invention enables a PSE to determine what type of Ethernet endpoints are attached and then power them appropriately. 
       FIG. 6  illustrates a PSE configuration, in accordance with one embodiment of the invention, where the PSE controller IC  40 , in the PSE  42 , has a single power channel, via the FET  44 , and uses dual sense resistors R S1  and R S2  to detect the one or more PDs, if any, coupled to the data wire pairs  46  and the spare wire pairs  48 . A PSE voltage source supplies −55 VDC, although other voltages may be used. 
     First, the PSE controller  40  performs a detection routine to sense a characteristic impedance (e.g., 25 kOhms) in the PD (not shown) that signifies that it is PoE-compatible. The detection is performed by injecting two different currents, I DET1  and I DET2 , on the wire pairs and measuring the delta voltage, described in detail below. This two-point detection allows the PD signature resistance to be isolated from any static diode voltage drops. The routines may be carried out by any type of programmed system in the PSE controller IC  40 . A programmed processor, firmware, a state machine, or other logic may be used to carry out the routines described below. Existing PSE controller IC hardware may be easily modified to carry out the inventive routines and provide the various signals on the output pins shown in  FIG. 6 . 
     Three types of detections are possible by sourcing the detection currents from the OUT 1 , OUT 2 , and SENSE pins, respectively, on the PSE controller IC  40 . Results may be combined to determine the type of attached PD or PDs. 
     Assume R S1 =R S2 , and R S1 &lt;&lt;R SIG , where R SIG  is the signature resistance of a PoE-compatible PD. In one embodiment, the resistors R S1  and R S2  are less than 1 Ohm, such as 0.1-0.25 Ohms, so there is only a small voltage drop across the resistors. 
     OUT 1  Detection 
     During the detection phase, a small forced current I DET1  will be driven out the OUT 1  pin over the data wire pairs, and a voltage will be generated based on the PD load and the wire resistance. V 1   1  (VOUT 1 −V EE ) will then be measured at the OUT 1  pin after a reasonable settling time. 
     Then, a second, slightly smaller current I DET2  will be driven out the OUT 1  pin. V 1   2  (VOUT 1 −V EE ) will then be measured after a reasonable settling time. The PD resistance R PD  is then detected as follows to determine whether the signature resistance is present.
 
 R   PD   =ΔV/ΔI =( V 1 1   −V 1 2 )/( I   DET1   −I   DET2 )
 
     If a valid ˜25 kOhm PD resistance is detected by the PSE controller IC  40 , then it is concluded that a single PD is present at the end of the cable. The PD may be attached on Alt A (see table of  FIG. 1 ), Alt B, or both, via the set of diode bridges shown in  FIG. 2 . 
     Y-cable topologies in which the Alt A branch of the Y-cable is connected to a valid PD and the Alt B branch is open may be detected by monitoring the detection voltage V 12  across R S1  and R S2 , where V 12 =OUT 1 −OUT 2 . If VOUT 1 =VOUT 2 , both the Alt A and Alt B branches are connected to the PD. If VOUT 1 ≠VOUT 2 , one branch is floating or connected to an invalid detection signature. The PSE  42  may choose not to provide power to a Y-cable topology. 
     OUT 2  Detection 
     Also during the detection phase, a small forced current I DET1  will be driven out the OUT 2  pin over the spare wire pairs. V 2   1  (VOUT 2 −V EE ) will be measured at the OUT 2  pin after a reasonable settling time. Then, a second, slightly smaller current I DET2  will be driven out the OUT 2  pin. V 2   2  (VOUT 2 −V EE ) will be measured after a reasonable settling time. The PD resistance is then calculated.
 
 R   PD   =ΔV/ΔI =( V 2 1   −V 2 2 )/( I   DET1   −I   DET2 )
 
     If a valid ˜25 kOhm PD resistance is calculated, then a single PD is present at the end of the cable. The PD may be attached on Alt A, Alt B or both, via the set of diode bridges shown in  FIG. 2 . 
     Y-cable topologies in which the Alt B branch of the Y-cable is connected to a valid PD and the Alt A branch is open may be detected by monitoring the voltage V 21  across R S1  and R S2 , where V 21 =OUT 2 −OUT 1 . A PSE may choose not to provide power to a Y-cable topology. 
     SENSE Detection 
     Also during the detection phase, a small forced current I DET1  will be driven out the SENSE pin to both sets of wire pairs. VS 1  (VSENSE−V EE ), V 1 S 1  (VOUT 1 −VSENSE) and V 2 S 1  (VOUT 2 −VSENSE) will then be measured after a reasonable settling time. 
     Then, a second, slightly smaller current I DET2  will be driven out the SENSE pin. VS 2  (VSENSE−V EE ), V 1 S 2  (VOUT 1 −VSENSE) and V 2 S 2  (VOUT 2 −VSENSE) will then be measured after a reasonable settling time. The PD resistance is then calculated.
 
 R   PD   =ΔV/ΔI =( VS   1   −VS   2 )/( I   DET1   −I   DET2 )
 
     If a valid ˜25 kOhm PD resistance is calculated, then a single PD is present at the end of the cable. The PD may be attached on Alt A, Alt B or both, via the set of diode bridges shown in  FIG. 2 . 
     Y-cable topologies in which one branch of the Y-cable is connected to a valid PD and the other branch is open may be detected by monitoring the voltage difference between V 1 S N  and V 2 S N . A PSE may choose not to provide power to a Y-cable topology. 
     If a ˜12.5 kOhm PD resistance is detected (e.g., two 25 kOhm resistors in parallel), then dual PDs are likely present at the end of the cable as shown in  FIG. 7 . In order to determine whether both individual PD signature resistors are ˜25 kOhm, the voltage differences across V 1 S N  and V 2 S N  can be examined. Generally, the individual values of resistors which are in parallel can be determined by examining the voltage across the parallel resistors. In this case, the voltage is (VSENSE−V EE ) and the current through each individual resistor is (V 1 S/R S1 ) and (V 2 S/R S2 ). 
     Classification 
     Once it is determined during the detection phase that there is at least one PoE-compatable PD coupled to either the data pair or the spare pair, a classification routine may be performed to identify the type or power the PD requires, such as Type I or Type II, specified by the IEEE standards. A classification voltage can be introduced by the PSE via the SENSE pin. Classification current for the Alt A and Alt B pair-sets can be independently measured by determining the voltages across R S1  (V 1 S CLS ) and R S2  (V 2 S CLS ). 
     When V 1 S CLS  and V 2 S CLS  do not match, a Y-cable or invalid PD is present. The PSE can determine whether it will power on such an invalid PD or cable topology. 
     Once the handshaking routines are complete, and the PSE  42  determines to supply the full PoE voltage to the data pairs and spare pairs, the PSE controller IC  40  closes the FET  44  to supply operating power to the data pairs and spare pairs via the resistors R S1  and R S2 . 
     As seen, a single PSE controller performs tests to determine the types of PDs connected to the data pairs and spare pairs and supplies the appropriate power to the data pairs and the spare pairs depending on the results of the detection and classification tests. 
     Although the controllers are described as IC&#39;s, they may be formed of discrete components. 
     While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications.