Abstract:
A termination network simultaneously provides a voltage-limited output direct current (dc) bias and termination of a broadband distributed amplifier operating down to an arbitrary low frequency. It is capable of being fabricated in a single Integrated Circuit (IC) chip, without the excess power dissipation associated with biasing through a termination resistor, and without the use of external inductor networks. It also limits the maximum dynamic voltage swing on the outputs of the active gain devices used within the distributed amplifier, so as to increase the reliability of the distributed amplifier under large signal over drive conditions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/363,059, filed Mar. 11, 2002, which application is incorporated by reference herein. 
     
    
     
       BACKGROUND  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to the field of electronic components for optical and broadband communication systems, and in particular, to techniques implemented in integrated circuit (IC) technology for biasing and terminating the output of a broadband distributed amplifier.  
           [0004]    2. Background  
           [0005]    Distributed amplifiers are multi-stage amplifiers used in optical and broadband communication systems to amplify signals over a broad frequency band, including frequencies below 500 MHz. Distributed amplifiers require their input and output lines to be terminated by a load impedance equal to the characteristic impedance of each line to maximize power transfer from the distributed amplifier to the load. Preferably, this terminating load impedance (hereinafter also referred to as “impedance termination”) provides constant impedance over the entire frequency range of operation of the distributed amplifier. The impedance termination also provides direct current (dc) biases to the active gain devices in the distributed amplifier used to amplify signals. One such active gain device is the Field Effect Transistor (FET), which typically requires dc biases applied to its input terminals (e.g., gate, base) and to its output terminals (e.g., drain, collector) to place the device in an amplifying state.  
           [0006]    Biasing the input lines of a distributed amplifier is typically not a problem, because the input terminals of the active gain devices, which make up the distributed amplifier, use little input bias current as compared to output bias current. The input bias current is also small compared to the input line impedance of the distributed amplifier. Thus, a dc bias can be applied to the input line of a distribute amplifier directly through a termination resistor without excessive power dissipation.  
           [0007]    By contrast, it is not simple to design the impedance termination for a distributed amplifier using IC technology when the amplifier has to operate at frequencies below 500 MHz. For example, it is difficult to maintain constant output impedance termination while providing dc bias to the output terminals of the active gain devices in the distributed amplifier. This is because the output terminals of the active gain devices draw a significant amount of bias current.  
           [0008]    One conventional solution is to provide the impedance termination on chip, and to bring the de bias through an internal inductor or an external biasing choke network. The use of an internal inductor is not an ideal solution when the lowest frequency of operation of the distributed amplifier is below 500 MHz because the size of the inductor is too large to realize on chip. A large internal inductor tends to have series resonance that limits the maximum frequency range of the distributed amplifier.  
           [0009]    Alternatively, an external choke can be implemented as a single large inductor off chip when the lowest frequency of operation is above 50 MHz. An external choke, however, is also not an ideal solution because of the high cost of manufacturing a suitable inductor (e.g., one that is free of spurious series resonance from 50 MHz to greater than 30 GHz). Additionally, because such inductors are physically large and of an awkward shape they are difficult to mechanically mount inside a microcircuit package next to a distributed amplifier IC using automated assembly equipment. This means they must be assembled by hand, which adds significantly to the cost of the packaged distributed amplifier assembly.  
           [0010]    When the amplifier is required to operate at frequencies below 50 MHz, as is often the case in optical communication systems, one inductor is usually not enough. For such an amplifier, a more complicated network can be used, such as the network described in V. Kaman, T. Reynolds, A. Petersen, J. E. Bowers, “A 100 KHz to 50 GHz Traveling-Wave Amplifier IC Module,” IEEE Microwave and Guided Wave Letters, Vol. 9, Section 10, pp. 416-418, October (1999). While this network can achieve the required performance without adding any extra dc power dissipation, it is expensive to implement. Indeed, it may be more than twice as expensive as the single inductor method used down to 50 MHz, because it requires at least two physically large inductors, which must be mechanically supported, and which require even more expensive hand assembly.  
           [0011]    Another common solution is to provide the dc bias to the output line of the distributed amplifier through a reverse termination resistor. This method of providing the dc bias to the output line dissipates excess power on chip. For example, a broadband amplifier which can drive 8 Volts (peak-to-peak) into a 50 Ohm load is typically biased at about 8 Volts with 250 mA of collector current, and dissipates 2 Watts of dc power when biased using a large inductor, as previously discussed. The most common output line characteristic impedance for optical and broadband applications is 50 Ohms. If one were to provide the output bias through a 50 Ω termination resistor in the above example, the amplifier would have to be biased at about 20.5 Volts instead of 8 Volts. This allows for 12.5 Volts (250 mA*50 Ω=12.5 V) voltage drop across the biasing resistor, and leads to over 5 Watts of power dissipation, most of which is being dissipated in the reverse termination resistor. Besides the power dissipation, the reverse termination resistor has to be physically large to pass 250 mA of collector current.  
           [0012]    There are several problems associated with implementing large termination resistors on chip. Such resistors are typically implemented as large thin film resistors, which have a large shunt capacitance and limited current handling capability. Many IC foundries have stringent limits on the current handling capability of thin film resistors. To avoid this problem a special thin film resistor process can be requested, which handles twice-as much current (e.g., using a lower Ω/sq thin film of extra thickness), but typically costs more to fabricate.  
           [0013]    Accordingly, there is a need for an impedance termination that can simultaneously provide voltage-limited output dc bias and proper termination of a broadband distributed amplifier, operating down to an arbitrary low frequency. It should be capable of being fabricated in a single IC chip, without the excess power dissipation associated with biasing through a reverse termination resistor, and without the use of external biasing chokes. It should also limit the maximum dynamic voltage swing on the outputs of the active gain devices used within the distributed amplifier, so as to significantly increase the reliability of the distributed amplifier under large signal over drive conditions.  
         SUMMARY OF THE INVENTION  
         [0014]    The present invention overcomes the deficiencies of conventional circuits and techniques by integrating or otherwise connecting a voltage-limited distributed current source with an integrated circuit (e.g., a distributed amplifier, broadband amplifier, mixer, oscillator, etc.) to provide biasing and termination impedance for the integrated circuit.  
           [0015]    In one embodiment of the present invention, an integrated circuit device comprises an integrated circuit (e.g., a distributed amplifier) having input and output lines connected to a distributed current source. The integrated circuit includes one or more gain devices connected to the output line. The distributed current source includes one or more current sources connected to the output line and the gain devices. A frequency dependent termination network is connected to the output line for providing a termination impedance and a sensing device for sensing a change in bias voltage on the output line.  
           [0016]    In one embodiment of the present invention, an integrated circuit (e.g., a distributed amplifier) having input and output lines is connected to a termination network including at least one current source and a sensing device for sensing a change in output bias voltage on the output line.  
           [0017]    In one embodiment of the present invention, an integrated circuit device comprises an integrated circuit (e.g., a distributed amplifier) having input and output lines connected to a distributed current source. The integrated circuit includes one or more gain devices connected to the output line. The distributed current source includes one or more current sources connected to the output line and the one or more gain devices. A termination network is connected to the output line and includes at least one current source and a sensing device for sensing a change in output bias voltage on the output line.  
           [0018]    The frequency dependent termination network for each of the foregoing embodiments can include a bias control loop connected to the output line for automatically adjusting the bias voltage on the output line. The termination networks can include various frequency dependent termination loads, including but not limited to one or more resistor-capacitor (RC) networks in star and ladder configurations or a combination of star and ladder RC networks. The termination network can also include one or more M-derived matching inductor-capacitor (LC) sections.  
           [0019]    A delay section can be inserted in the input and/or output lines to control phase delays in the input and output lines. In one embodiment of the present invention, one or more layers of resistive film material (e.g., TFR film, bulk resistor layer) can be disposed under the input and/or output lines to increase the loss along the lines. Also, the shunt conductance of each current source can be increased at high frequencies by adding an additional RC network in shunt with each current source. To reduce jitter the distributed current sources can be configured as a Tee or Pi attenuators by connecting the current sources in shunt with one or more series resistors, which are connected in series with one or more matching inductors.  
           [0020]    The present invention also includes various embodiments of current sources. One or more of these current sources can be a depletion mode load style current source. The current sources can include one or more of the following: a capacitive element to reduce capacitance of the current source, a resistive element to suppress oscillations in output current due to process variations, a capacitive element to maintain constant voltage at higher frequencies, and a diode for forward biasing gain devices. The currents sources can also use negative conductance to compensate for losses down the output line of the integrated circuit, such as a distributed amplifier.  
           [0021]    The present invention can be fabricated in a single integrated circuit chip without the excess power dissipation associated with supplying the bias current through an output reverse termination resistor, and without the use of an expensive off chip biasing choke. The present invention also limits the maximum dynamic voltage swing on the outputs of the active gain devices used within the distributed amplifier, thereby increasing the reliability of the distributed amplifier under large signal over drive conditions. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    [0022]FIG. 1 is a block diagram of an integrated circuit including a distributed amplifier and an output bias and termination impedance network, in accordance with one embodiment of the present invention.  
         [0023]    [0023]FIG. 2A is a circuit model of the distributed amplifier and the output bias termination impedance network shown in FIG. 1, in accordance with one embodiment of the present invention.  
         [0024]    [0024]FIG. 2B is a circuit model of the distributed amplifier and the output bias termination impedance network shown in FIG. 1 with extra shunt loss and extra lossy transmission lines, in accordance with one embodiment of the present invention.  
         [0025]    [0025]FIG. 3 is a circuit diagram of a frequency dependent output bias and termination impedance network having an automatic bias control loop, in accordance with one embodiment of the present invention.  
         [0026]    [0026]FIG. 4 is a circuit model of two adjacent sections of a distributed current source, in accordance with one embodiment of the present invention.  
         [0027]    [0027]FIG. 5 is a circuit diagram of an N section distributed amplifier integrated with a distributed current source.  
         [0028]    [0028]FIG. 6 is a circuit diagram of a “jth” section of an N section distributed amplifier with a current source and a lossless delay section added to provide output bias and maintain equal phase delays, in accordance with one embodiment of the present invention.  
         [0029]    [0029]FIG. 7 is a diagram of an integrated circuit, including an N section distributed amplifier integrated with a distributed current source and lossless delay sections, in accordance with one embodiment of the present invention.  
         [0030]    [0030]FIGS. 8A and 8B are circuit diagrams of complementary P-type current mirror style current sources for use in a distributed current source, in accordance with the present invention.  
         [0031]    FIGS.  9 A-F are circuit diagrams of depletion mode load style current sources for use in a distributed current source, in accordance with the present invention.  
         [0032]    [0032]FIG. 10 is a diagram of an equivalent circuit for a current source having a series capacitor to reduce effective current source capacitance, in accordance with one embodiment of the present invention.  
         [0033]    [0033]FIG. 11 is a diagram of an integrated circuit, including a distributed amplifier connected to a distributed current source output termination, in accordance with one embodiment of the present invention.  
         [0034]    FIGS.  12 A-C are circuit diagrams of frequency dependent termination impedance networks, in accordance with the present invention.  
         [0035]    [0035]FIG. 13 is a circuit diagram of a six section distributed current source, in accordance with one embodiment of the present invention.  
         [0036]    [0036]FIG. 14 is a diagram of an integrated circuit, including a distributed amplifier integrated with distributed current source termination with extra current sources added at the output, in accordance with one embodiment of the present invention.  
         [0037]    [0037]FIG. 15 is a diagram of an integrated circuit, including a distributed amplifier integrated with distributed current source termination with extra current sources added at the output and delay sections added to maintain equal phase delays, in accordance with one embodiment of the present invention.  
         [0038]    [0038]FIG. 16 is a circuit diagram of a distributed current source configured as a Tee or Pi attenuator, in accordance with one embodiment of the present invention.  
         [0039]    [0039]FIG. 17 is a circuit diagram of a distributed current source, which is the distributed current source shown in FIG. 16 modified to reduce bias dependence at high frequencies, in accordance with one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF EMBODIMENTS  
       [0040]    The present invention is described below using symbols and nomenclature known to those skilled in the art of integrated circuit technology. Like elements are collectively designated by a single numerical designation, and individual elements within the numerically designated set of elements are designated alphanumerically. For example, elements “a” and “b” are referred to collectively as elements  100  or  100   a - b  and individually as element  100   a  and element  100   b.    
         [0041]    The semiconductor devices described in the embodiments below can be any type of known device, including without limitation, Bipolar Junction Transistors (BJTs), Field Effect Transistors (FETs), Pseudomorphic high electron mobility (pHEMPTs), Dual Gate Devices, and Cascode Pairs. These devices can be made of any material, including without limitation, Silicon (Si), Gallium Arsenide (GaAs), Indium Phosphate (InPh), and Gallium Nitride (GaN).  
         [0042]    Distributed Current Source Model  
         [0043]    [0043]FIG. 1 is a block diagram of an integrated circuit (IC)  100  including a distributed amplifier  102 , an output bias and termination impedance network  104 , and an input bias and termination impedance network  106 , in accordance with one embodiment of the present invention. The distributed amplifier  102  includes gain devices  108   a - c  (e.g., FET, BJT, pHEMPT), which are used to amplify input signals received from input transmission line  112 . While only three gain devices are shown in FIG. 1, any number of gain devices can be used with the present invention.  
         [0044]    The output bias and impedance termination network  104  (“termination network  104 ”) is connected to the distributed amplifier  102  via an output transmission line  114  to provide dc biases to the outputs of the active gain devices  108   a - c  and a terminating load impedance that is substantially constant over the entire frequency range of operation of the distributed amplifier  102 . In one embodiment of the present invention, current sources  110   a - b  are connected to the output transmission line  114  and interleaved with the gain devices  108   a - c  to provide the dc bias current to the outputs (e.g., collectors, drains, etc.) of the gain devices  108   a - c , as described more fully with respect to FIG. 2 below.  
         [0045]    FIGS.  2 A- 2 B are circuit model diagrams of the distributed amplifier  102  connected to the termination network  104  shown in FIG. 1, in accordance with one embodiment of the present invention. For clarity purposes, only the outputs  200   a - c  (e.g., collector, drain, etc.) of the gain devices  108   a - c  of the distributed amplifier  102  are modeled in FIGS.  2 A- 2 B. The outputs  200   a - c  are modeled as controlled current sources  202   a - c  connected in shunt with output capacitances  204   a - c . The current sources  202   a - c  and capacitances  204   a - c  are connected to the output transmission line  114 .  
         [0046]    The termination network  104  comprises a bias current source  206 , a reverse termination resistor  208 , a sense resistor  210  and a dc voltage source  212 . The bias current source  206  is connected in shunt with the reverse termination resistor  208 , and provides a biasing current I bias  to the outputs  200   a - c . If the biasing current I bias  does not match the current I bias     —     da  drawn by the outputs  200   a - c , then the bias voltage V bias  at node  214  will tend to rail. The current mismatch I mismatch  causes a voltage drop across the sense resistor  210 , which can be measured and used to adjust the voltage across the reverse termination resistor  208  using voltage source  212 . The bias current source  206  replaces the external rf choke used in conventional output termination networks for distributed amplifiers.  
         [0047]    In one embodiment of the present invention, one or more layers of resistive film material (e.g., TFR film, bulk resistor layer) can be disposed under the transmission line  114  to increase the loss. Also, the shunt conductance of each current source can be increased at high frequencies by adding an additional RC network in shunt with each current source, as shown in FIG. 2B.  
         [0048]    While the termination network  104  shown in FIGS.  2 A- 2 B can be used to terminate the output of a distributed amplifier, the termination network  104  can also provide the bias current and the load termination concurrently for other types of circuits, including but not limited to broadband amplifiers, mixers, oscillators, and any other circuit that could benefit from bias current and load termination.  
         [0049]    Automatic Bias Control  
         [0050]    [0050]FIG. 3 is a circuit diagram of a frequency dependent output bias and termination impedance network  300  (“termination network  300 ”) having an automatic bias control loop, in accordance with one embodiment of the present invention. The termination network  300  is another embodiment of the termination network  104  and can be connected to node  214  of the distributed amplifier  102  shown in FIG. 2.  
         [0051]    The termination network  300  comprises a bias current source  302 , a comparing device  304  (e.g., operational amplifier), a reverse termination resistor  306 , a reverse termination capacitor  308 , a sense resistor  310 , a sense capacitor  312 , and a dc voltage source  314 . The values for these devices can be selected to provide a desired frequency response (e.g., 30 KHz). The reverse termination resistor  306 , the sense resistor  310  and the comparing device  304  are configured to function as a bias control loop for maintaining a desired dc bias voltage V bias  at node  214  over temperature variations and through aging of the gain devices  108   a - c . The bias current source  302  is connected in shunt with the reverse termination resistor  306 , and provides a biasing current I bias  to the distributed amplifier  102  via node  214 . If the biasing current I bias  does not match the current I bias     —     da  drawn by the outputs  200   a - c  of the gain devices  108   a - c  in the distributed amplifier  102 , then the bias voltage V bias  at node  214  will tend to rail. The current mismatch I mismatch  is sensed by the comparing device  304 , which balances the currents I bias  and I bias     —     da  by adjusting the bias voltage V bias  at node  214  to the desired value using voltage source  314 .  
         [0052]    The termination network  300  can be auto-inserted and auto-assembled during the IC fabrication process, thus eliminating the need for costly hand assembly typically required with conventional circuits and techniques.  
         [0053]    Reducing the Effect of Parasitic Output Capacitance  
         [0054]    While the interleaving of a distributed current source into the output bias network of a distributed amplifier is conceptually straight forward, realizing an ideal current source on an IC chip at high frequencies is difficult to achieve in practice. Practical current sources that can be realized in conventional IC processes typically have parasitic output capacitance, finite output resistance, and limited dynamic range.  
         [0055]    The parasitic output capacitance associated with a practical on chip active current source can be modeled by distributing the capacitance over two or more sections of the distributed current source. FIG. 4 is a circuit model of a “jth” section  402   a  and “jth+1” section  402   b  of a distributed current source  400 , in accordance with one embodiment of the present invention. The jth section  402   a  is modeled as a fixed current source  404   a  connected to a shunt parasitic capacitance  408   a  (C parcsj ) and the jth+1 section  402   b  is modeled as a fixed current source  404   b  connected to a shunt capacitance  408   b  (C parcsj+1 ). The sizes of the jth and jth+1 sections  402   a ,  402   b , in the distributed current source  400  need not be the same. Small elemental inductances  406   a  (L j ) and  406   b  (L j+1 ) are inserted into an artificial transmission line  412  between sections  402   a ,  402   b , forming an artificial line low-pass filter, which absorbs the parasitic capacitance  408   a.    
         [0056]    In practice, the elemental inductances  406   a ,  406   b , are realized using a small length of high impedance transmission line. The image impedance Z i  and comer frequency F c  of the “ith” stage of a distributed amplifier can be represented mathematically by equations (1) and (2), as follows:  
               Z   i     =               L     j   -   1       +     L   j         2        C   parcsj                        ,             (   1   )                 F   c     =     1     π              L     j   -   1       +     L   j       2       *     C   parcsj                 (   2   )                               
 
         [0057]    It is noted from equations (1) and (2), that the image impedance Z i  and the corner frequency F c  are functions of the elemental inductance  410  (L j−1 ) from the “j−1th” section of the distributed current source  400  and the elemental inductance  406   a  (L j ) and capacitance  408   a  (C paracsj ) of the “jth” section  402   a.    
         [0058]    The techniques described above are used with distributed current sources to reduce the effects of shunt parasitic capacitance on the frequency response of a distributed amplifier. Equations (1) and (2) generally describe how the capacitances of the current sources of the biasing network or the capacitances of the gain devices of the distributed amplifier are absorbed into an artificial transmission line with an arbitrary bandwidth with comer frequency F c .  
         [0059]    Distributed Current Source Integrated With Distributed Amplifier  
         [0060]    [0060]FIG. 5 is a circuit diagram of an integrated circuit  501 , including an N section distributed amplifier  500  integrated with a distributed current source  502 . The distributed current source  502  is in shunt with a reverse termination resistor  516  to simultaneously provide dc bias and proper impedance termination. The distributed amplifier  500  is realized on an IC chip and comprises gain devices  504   a -N (e.g., ED-MOS or CMOS digital inverter gates), where each gain device  504   a -N can be an E-type, pull-down active gain device. The distributed current source  502  comprises current sources  506   a -M (e.g., ED-MOS or CMOS digital inverter gates) integrated with the gain devices  504   a -N, where each current source  506   a -M can be a D-type, pull-down active current source. Inductor elements  508   a -N are preferably inserted into output transmission line  512  between nodes  510   a -N, and are shared by the gain devices  504   a -N and the current sources  506   a -M. As discussed previously with respect to FIG. 4, the inductor elements absorb the shunt parasitic capacitance contributed by the current sources  506   a -M to reduce the effect of such capacitance on the frequency response of the distributed amplifier  500 .  
         [0061]    The design of the integrated circuit  501  shown in FIG. 5 is constrained by the desired input and output impedances of the two artificial transmission lines  512 ,  514 , which make up a transversal filter. The delays on lines  512 ,  514 , should be approximately equal for input signals to arrive in phase at the output port. Moreover, to achieve a fast rise time the distributed amplifier  500  should have a broad bandwidth, requiring the cut-off frequencies of the lines  512 ,  514 , to be greater than some minimum desired frequency.  
         [0062]    The image impedance Z oi  and cut-off frequency F ci  of the “ith” stage of the distributed amplifier  500  is represented mathematically as:  
               Z   ei     =           L   i       C   i         ,              and             (   1   )                 F   ci     =       1   π              1       L   i     *     C   i                      .               (   2   )                               
 
         [0063]    It is noted from equations (1) and (2), that Z oi  and F ci  are functions of the capacitance C i  at nodes  510   a -N. Thus, by inserting current sources  506   a -M into the output transmission line  512  at each node  510   a -N, the corner frequency F ci  and output image impedance Z oi  will change. Since it is desirable to maintain a fixed comer frequency F ci  and output image impedance Z oi  at each node  510   a -N to achieve desired transversal filter characteristics, the gain devices  504   a -N of the distributed amplifier  500  can be made smaller in size to maintain the desired capacitance C i , and therefore the same image impedance Z oi  and comer frequency F ci . For example, in one embodiment one could make the gain devices  504   a -N in the distributed amplifier  500  about two-thirds of their normal size. Unfortunately, reducing the size of the gain devices  504   a -N results in less gain and output swing from the distributed amplifier  500   
         [0064]    The reduced gain and output swing cannot be fixed by simply adding more sections (e.g., gain devices) to the distributed amplifier  500  because for any distributed amplifier design there is an optimal number of sections (e.g., usually about six to nine), which is determined primarily by losses down the input transmission line  514 . Also, the extra conductance contributed by the current sources  506   a -M only add to the gain roll-off along the output transmission line  512 . While reducing the size of the gain devices  504   a -N may be adequate for some applications, there are other applications where more output power and gain with less gain roll-off is desired. Thus, a new topology is needed that enables the integration of the distributed current source  502  into the distributed amplifier  500  without having to reduce the size of the gain devices  504   a -N in the distributed amplifier  500  to accommodate the additional capacitances contributed by the current sources  506   a -M in the distributed current source  502 .  
         [0065]    In one embodiment of the present invention, the reduced output swing limitation is resolved by fixing the size of the gain devices  504   a -N. To fix the size of the gain devices  504   a -N, one can add extra lossless delay sections to the current sources  506   a -M so that the current sources  506   a -M and gain devices  504   a -N need not attach to the same nodes (e.g., nodes  510   a -N). The use of delay sections in the output and input transmission lines  512 ,  514 , is described more fully with respect to FIG. 6 below.  
         [0066]    Adding Lossless Delay Sections To Maintain Equal Phase Delays  
         [0067]    [0067]FIG. 6 is a circuit diagram of the “jth” section  600  of an N section distributed amplifier, including a current source  602 , a gain device  604  and lossless delay sections  606   a - b , in accordance with one embodiment of the present invention. The delay section  606   a  includes inductor elements  608   a ,  608   b , and capacitor  610   a . The delay section  606   b  includes inductors  608   c ,  608   d , and capacitor  610   b . The current source  602  is connected to the output transmission line  612  and the gain device  604  is connected to both the output transmission line  612  and the input transmission line  614 . In one embodiment, the current source  602  is a D-type, active pull-up device (half the width) and provides bias current to the gain device  604 .  
         [0068]    The delay sections  606   a - b  are added to each current source  602  inserted into the transmission lines  612 ,  614 , to maintain equal phase delays on the transmission lines  612 ,  614 . The capacitor  610   a  is connected to the current source  602  to match the output capacitance of the gain device  604  (C outj /2). The inductor elements  608   a ,  608   b , are approximately equal to the output inductance L outj  of the output image line filter (L outj )/2, and the capacitor  610   b  is approximately equal to the input capacitance of the gain device  604  (C inFETj ). The inductor elements  608   c  and  608   d  are approximately equal to the input inductance of the input image line filter (L outj /2).  
         [0069]    The delay sections  606   a - b  shown in FIG. 6 provide one whole delay, while absorbing the parasitic capacitance contributed by the current source  602  into the output transmission line  612 . By inserting the delay sections  606   a - b  into the output transmission line  612 , a full-sized gain device  604  can be used in the distributed amplifier. In this way, the same performance can be achieved as from providing the bias through a conventional off-chip bias choke, except for extra losses along the output transmission line  612  due to the finite output conductance of the current source  602 . As shown in FIG. 5, the current source  602  is preferably added before the gain device  604  to minimize such losses.  
         [0070]    In another embodiment, the capacitor  610   a  is removed and the inductor elements  608   a ,  608   b  are selected to be approximately half the output inductance of the output image line filter (L outj /4). Likewise, the capacitor  610   b  is selected to be approximately half the. input capacitance (C inFETj /2) of the gain device  604  and the inductors  608   c ,  608   d , are selected to be approximately half the input inductance (L inj /4) of the input image line filter. Such an embodiment is used in the distributed amplifier  702  described with respect to FIG. 7 below.  
         [0071]    [0071]FIG. 7 is a circuit diagram of an N section distributed amplifier  700 , including gain devices  702   a -N integrated with a distributed current source  704  including current sources  706   a -M, in accordance with one embodiment of the present invention. Lossless delay sections  708   a - b  are added for every two gain devices  702   a -N to provide output bias and maintain equal phase delays. The current sources  706   a -M can be, for example, a D-type active pull-up current sources.  
         [0072]    The delay section  708   a  comprises inductor elements  710   a - b  and shunt capacitor  712 , which are inserted in the input transmission line  718  for every two gain devices  702   a -N. The delay section  708   b  includes inductor element  714 , which is inserted in the output transmission line  716  for every two gain devices  702   a -N. The inductor element  714  is approximately equal to the average of the other inductor elements L out  inserted in the output transmission line  716 . Likewise, the shunt capacitor  712  is approximately equal to the average of the input capacitances of the gain devices  702   a -N on either side of the shunt capacitor  712 , and the inductor element  710   a - b  are approximately equal to the average of the inductor elements L in  inserted in the input transmission line  718  either side of the inductor element  710 . Adding the capacitor  712  and inductor elements  710   a - b  to the input transmission line  718  and the inductor element  714  (and optionally a capacitor as shown in FIG. 6) to the output transmission line  716  maintains the desired matched phase delays on the transmission lines  716  and  718 .  
         [0073]    In each of the previous two embodiments of distributed current sources for both the ED MOS gate style with a depletion load for each gain device (FIG. 5) as well as the interleaved current source with extra phase-compensating filter elements (FIG. 7), the final performance of the distributed amplifier is dependant on the quality of the current sources. The following section describes several embodiments of current sources that can be integrated with a distributed amplifier, in accordance with the present invention.  
         [0074]    Active Current Sources  
         [0075]    The active current sources that can be realized on chip have several non-ideal properties. For example, a practical active current source has parasitic capacitance, which can only be absorbed up to the amount of capacitance present at each node of the output transmission line where the current source is inserted. As discussed previously with respect to FIG. 4, this capacitance is constrained by the image impedance Z i  and cut-off frequency F c  for the “ith” section of the distributed amplifier.  
         [0076]    A practical active current source also has finite output conductance. The attenuation factor α 0  down the output transmission line is approximately 
         α 0 =(1/(2 *l ))* Z   io *( G   CS   +G   gq ),  (5) 
         [0077]    where the length  1  is the length of a unit section of the output transmission line, Z io  is the characteristic impedance of the output transmission line, and G cs  and G gq  are the output conductances of the current source and the gain transistor, respectively. The losses along the output transmission line due to the attenuation factor α 0  reduce both the gain and the output power of the distributed amplifier.  
         [0078]    An active current source also has a limited amount of output current because there is a maximum current I max , which a given size device can supply. Therefore, any current source constructed with this kind of device will only be able to source a finite amount of current I CS , which is less than I max .  
         [0079]    A practical active current source also has a limited range of voltage swing. It behaves as a current source when the voltage drop across it is greater than its knee voltage V knee . Below V knee  the current source behaves like a resistor with its output current depending on the voltage applied across it. At higher applied voltages across the current source, the output conductance G CS  increases abruptly near the breakdown voltage V bd  of the current source.  
         [0080]    The output conductance of an active current source is non-linear, which leads to more distortion when using the distributed amplifier in a linear mode. Besides the curvature to the current-voltage (I-V) plot from the transition near V knee  and also towards the higher voltages as you approach V bd , there can also be kinks due to traps and other non-linearities.  
         [0081]    Several embodiments of current sources that take into account the above characteristics of practical current sources are discussed below with respect to FIGS. 8 and 9.  
         [0082]    Complementary P-Type Current Mirror Style Current Sources  
         [0083]    [0083]FIGS. 8A and 8B are circuit diagrams of two current source topologies implemented with complimentary-type devices that can be integrated with a distributed amplifier, in accordance with the present invention. With complementary devices, the output current I out  is typically supplied out of an isolated node (e.g., a drain, a collector, etc.). This helps to keep the current constant regardless of the voltage applied across it.  
         [0084]    [0084]FIG. 8A shows a current mirror  800  comprising transistors  802 ,  804 , and a small series feedback resistor  806  (R s ). Adding the feedback resistor  806  helps to keep the output current I out  constant over IC process variations. The current source  800  has a control node  808  for controlling the output current I out . The control node  808  isolated from the output node  810  of the transistor  804 , so the applied voltage at control node  808  does not effect the output current I out .  
         [0085]    [0085]FIG. 8B shows a Wilson current source  812  constructed from transistors  812 ,  814 , and  816 . The Wilson current source  812  has lower output conductance G CS  at low frequencies than the current mirror  800 . At high frequencies, however, the current mirror  800  and Wilson current source  812  provide similar performance. The Wilson current source  812  also has less headroom due to an additional voltage drop across transistor  818 .  
         [0086]    The current mirror  800  and Wilson current source  812  shown in FIGS. 8A and 8B are implemented using PNP BJT current sources, but other IC processes can also be used to fabricate these current sources, including without limitation, PMOS and PJFET processes. If the IC process offers various complementary devices (e.g., n-type, p-type), then the faster complimentary device type (e.g., n-type) are preferably used for the gain devices in the distributed amplifier and the slower complementary device type (e.g., p-type) to construct the distributed current source.  
         [0087]    Often there are no complementary devices available with the IC process offered by the typical foundry. Such is the case with most GaAs MESFET and pHEMT processes. In such cases, there are various current source topologies based solely on depletion mode FET devices, as described below with respect to FIGS.  9 A- 9 F.  
         [0088]    Depletion Mode Load Style Current Sources  
         [0089]    FIGS.  9 A- 9 F are circuit diagrams of various current source topologies based on depletion mode FET devices which can be integrated with a distributed amplifier, in accordance with the present invention. The basic current source  900  shown in FIG. 9A sources a fair amount of current for its capacitance (i.e., a favorable I CS /C CS ). With its gate connected to its source, its control nodes  901   a ,  901   b , are fixed so it has relatively high immunity to variations in applied voltage to its output node. This is equally true for the current sources  908  and  910 , shown in FIGS. 9E and 9F. The current sources  900 ,  908 , and  910 , all have a fixed output current I out  that depends on the current I dss  of the IC process, which can vary significantly from wafer to wafer.  
         [0090]    The current sources  902  and  906  shown in FIGS. 9B and 9D avoid this problem by enabling the output current I out  to be adjusted by varying the voltage across the control nodes  903   a ,  903   b , and control nodes  909   a ,  909   b , respectively, to be varied at the price of susceptibility to variations in the output voltage. Capacitors  919 ,  921  (C gs ) can also be added to the current sources  902  and  906 , respectively, to maintain a constant gate-to-source voltage at higher frequencies.  
         [0091]    The current source shown in FIG. 9C uses a series negative feedback resistor  907  (R s ) to suppress oscillations, which helps keep the output current I out  consistent over variations in I dss  due to process variations. This same series feedback approach can be applied to the current sources  908 ,  910 , shown in FIGS. 9E and 9F. However, when you drop voltage across the feedback resistor  907  to provide feedback you pinch off the device, resulting in a lower I CS /C CS . One way to get around this problem is to forward bias the transistor  923  as shown in FIG. 9D by using a forward biased diode  911  to supply a positive gate-to-source bias. By forward biasing the transistor  923 , the current source  906  is able to source the most output current I out  for a given device size.  
         [0092]    One way to double the current for a given amount of capacitance, while also halving the conductance G CS  and doubling the breakdown voltage V bd , is to use a dual current source  908  having two transistors in series as shown in FIG. 9E. This dual current source  908 , however, also doubles the knee voltage V knee , so it requires a greater bias voltage, resulting in reduced efficiency. It also has half as sharp of V knee  as a single current source leading to softer clipping, greater amplitude variation, and increased jitter.  
         [0093]    All of the current sources shown in FIGS.  9 A-F (other than the dual gate current source  908  shown in FIG. 9E) have a high output conductance G CS  and so are not ideally suited for integrating into a distributed amplifier. The dual gate current source  908  has a little less current for a lower I CS /C CS  and also a higher V knee  for a lower efficiency than the basic depletion load current sources. It has such a low amount of output conductance it can even be negative. As can be observed from equation (5), the negative output conductance G CS  enhances the gain of the distributed amplifier by reducing the attenuation factor α 0  down the output transmission line, as can be noted from equation (5).  
         [0094]    Reducing Effective Current Source Capacitance  
         [0095]    [0095]FIG. 10 is a diagram of an equivalent circuit of a current source  1000 , including a series capacitor  1002  (C series ) to reduce the effective current source capacitance  1004  (C cseff ), in accordance with one embodiment of the present invention. The series capacitor  1002  can be applied to any of the current sources shown in FIGS. 8 and 9 to increase I CS /C CS . Adding the capacitor  1002  in series with the current source  1000  decreases the effective capacitance of the current source  1000 . This technique works well in a small signal sense to reduce the effective current source capacitance  1004 . To provide the dc current, a shunt RL network  1006  is used to provide the dc bias voltage V dd . The value of resistor  1008  the RL network  1006  is selected so that it will recharge the series capacitor  1002  for all bit patterns in the input signal without shorting the series capacitor  1002 . One embodiment of a distributed current source comprising current sources having series capacitors is described with respect to FIG. 11 below.  
         [0096]    Six Section Distributed Current Source With Series Capacitor  
         [0097]    [0097]FIG. 11 is a circuit diagram of a six section distributed current source  1100 , in accordance with one embodiment of the present invention. The distributed current source  1100  includes six R sbias  feedback style current sources  1110   a - e  (e.g., the depletion mode load style current sources shown in FIGS. 9C and 9D), each connected to a series capacitor network  1108   a - e  comprising a shunt RL network (R iso , L iso ) and a series bypass capacitor C bypass , as described with respect to FIG. 10. The RL network (R iso , L iso ) isolates off-chip circuitry from the current source  1100 .  
         [0098]    The RL bias network  1112  provides dc bias current while providing isolation from off-chip circuitry via R bias  and L bias . The inductor L bias  is a backside via used to ground the capacitor C bias , which is a chip bypassing capacitor for the drain bias. R bias  is the bond wire resonance suppression resistor. The value of R bias  can be determined as follows: 
           R   bias =2 {square root}{square root over (L bondwire /C bias )},   (6) 
         [0099]    where L bondwire  is the inductance of the bond wire. The shunt RL network (R iso     —     bias , L iso     —     bias ) allows the bias current to flow through the inductor L iso     —     bias . The resistor R iso     —     bias  provides high frequency isolation between the bond wire and off-chip circuitry and the on-chip biasing current sources. The shunt RL network (R iso     —     bias , L iso     —     bias ) allows the distributed current source to have consistent performance independent of the bond wire length off-chip.  
         [0100]    When the bypass capacitors C bypass  in the networks  1108   a - f  are large, the respective current sources  1110   a - f  reduce to standard distributed current source lines (e.g., FIG. 9C). When the bypass capacitors C bypass  are about the same value as the capacitances C CS  of the respective current sources  1110   a - f , then the current sources  1110   a - f  reduce to series capacitors that reduce the effective capacitances of the current sources  1110   a - f , as described with respect to FIG. 10.  
         [0101]    The distributed current source  1100  includes M-derived inductor-capacitor (LC) matching sections  1104 ,  1106 , located at opposite ends of the distributed current source  1100 . The M-derived LC matching sections  1104 ,  1106 , are used to transition from fixed reference impedance Z 0  (e.g., 50 Ohms), to the image impedance Z i  of the artificial transmission line. The image impedance Z i  is the impedance required to terminate an artificial transmission line as to have the same impedance as if the artificial transmission line was infinitely long. The image impedance Z i  has strong frequency dependence near the cut-off frequency of the artificial transmission line. Using an M-derived termination with M=0.6, provides a near optimal matching circuit to match from the frequency dependent image impedance Z i  to the fixed frequency reference impedance Z 0  of a constant impedance test environment. A further description of these techniques can be found in I.O. Zobel, “Theory and Design of Electric Wave Filters,” Bell Sys. Tech. Jour., January 1923.  
         [0102]    The image line filter of the distributed current source  1100  can be better matched at its ends by including the M-derived LC sections  1104 ,  1106 . The M-derived LC section  1106 . connected to the input of the distributed current source  1100  is optional, and provides impedance matching for testing and modeling. The M-derived LC section  1104  is connected to a frequency dependent termination network  1102  and adjusts the output bias current, as described more fully with respect FIG. 2.  
         [0103]    The termination network  1102  embodiment of the circuits shown in FIGS.  12 A-C. The network  1102  has high impedance at lower frequencies such that the shunt combination of the conductance of all the distributed current sources and the frequency dependent termination maintains a proper termination down to dc. At high frequencies, the capacitances of the distributed current sources will dominate, requiring lower termination impedance because the distributed current sources are behaving as a lossy artificial transmission line. The values for the active devices in the termination network  1102  (e.g., capacitors C 1 , C 2 , C 3 , C 4  and inductors L 1 , L 2 ) can be selected to provide the desired bandwidth for the frequency dependent termination network  1102 . The port labeled V bias     —     sense  can be used to sense changes in the bias voltage and the port labeled V bias     —     force  can be used to adjust the bias voltage in response to any sensed changes, as previously described with respect to FIGS. 2 and 3.  
         [0104]    At higher frequencies (e.g., above 2 GHz to 5 GHz), the termination network  1102  behaves like a lossy transmission line and wants to be terminated with Z i  of the output transmission line  1114 . At 30 KHz, which is close to dc, the current sources  1110   a - f  are no longer distributed and so the termination wants to be 15% to 35% higher, so that the sum of the conductances G CS  of the current sources  1110   a - f  and the termination network  1102  equals 1/Z i  of the output transmission line  1114 . Therefore, the optimal broadband termination impedance is frequency-dependant; that is, higher near dc and drops to Z i  over several decades of bandwidth.  
         [0105]    FIGS.  12 A-C are circuit diagrams showing various resistor-capacitor (RC) networks with this kind of frequency response, in accordance with the present invention. FIG. 12A is a circuit diagram of a frequency dependent termination impedance star network comprising one or more series RC sections. FIG. 12B is a circuit diagram of a frequency dependent termination impedance ladder network comprising one or more RC ladder sections. FIG. 12C is a circuit diagram of a frequency dependent termination impedance combination network including both series and ladder RC sections. One or more of these RC networks can be used in the frequency dependent termination networks shown in FIGS. 2A, 2B,  3 , and  11  as well as in the embodiments described below with respect to FIGS.  12 - 14 . For example, any one of the circuits shown in FIGS.  12 A-C can replace the fixed termination resistor  306  in FIG. 3 to provide a frequency dependent termination impedance.  
         [0106]    Distributed Amplifier With Distributed Current Source Output Termination  
         [0107]    [0107]FIG. 13 is a circuit diagram of an integrated circuit  1301 , including a distributed amplifier  1300  having an input transmission line  1310  and an output transmission line  1308 , integrated with a distributed current source output termination network  1304 , in accordance with one embodiment of the present invention. The distributed amplifier  1300  includes N sections of active gain devices  1302   a -N. Each gain device  1302   a -N has an output (e.g., drain) connected to the output transmission line  1308  and an input (e.g., gate) connected to the input transmission line  1310 . Each active gain device  1302   a -N is separated from its neighboring active gain device  1302   a -N by an elemental inductance (L aout ) inserted in the output transmission line  1308  and an elemental inductance (L ain ) in the input line  1310 . The elemental inductances L aout , L ain , provide equal phase delays on the output and input transmission lines  1308 ,  1310 , as previously discussed with respect to FIGS. 6 and 7.  
         [0108]    The current source output termination network  1304  comprises M current sources  1306   a -M, each current source  1306   a -M is connected to the output transmission line  1308  the distributed amplifier  1300  and separated from its neighboring current source  1306   a -M by an elemental inductance L csm . The current sources  1306   a -M can be implemented with any of the current sources described with respect to FIGS.  8 - 9 .  
         [0109]    The output transmission line  1308  terminated with a frequency dependent termination impedance network  1312  comprising a reverse termination resistor R termout  and a sense resistor R sense  for monitoring the output bias voltage, as previously described with respect to FIGS. 2 and 3.  
         [0110]    The current source output termination network  1304  solves the problems associated with having the current sources  1306   a -M sharing the same output transmission line  1308  the distributed amplifier  1300  by placing the current sources  1306   a -M in the back of the distributed amplifier  1300  in between the frequency dependent termination network  1312  and the output of the distributed amplifier  1300 . In this way, the current sources  1306   a -M form an active lossy transmission line, which provides dc bias and impedance termination to the output of the distributed amplifier  1300  at the same time. The shunt conductances G CS  of the current sources  1306   a -M no longer reduce the gain nor the output power of the distributed amplifier  1300 . In fact, the loss helps to reduce the magnitude of the reflections off the reverse termination resistor R termout  at higher frequencies.  
         [0111]    Reducing Pattern Dependent Jitter  
         [0112]    When a distributed current source is integrated with a distributed amplifier, the overall simulated performance of the combination compares favorably in all respects with the same distributed amplifier biased with a conventional ideal rf choke, except for extra bit pattern dependent jitter. There are at least two sources of this extra bit pattern dependent jitter. These include clipping the voltage at the distributed current source, which causes reflections that are spatially well separated from the output, and the extra bounce on the current sources provided by a series capacitor in the drain bias network.  
         [0113]    In one embodiment of the present invention, one or more extra current sources are added near the output to clip the voltage on the top of the output waveform to reduce the extra jitter induced from saturating the distributed current source devices near the reverse termination. By using the knee voltages V knee  of the current sources to clip the tops of the output waveform and the knee voltages of the gain devices to clip the bottoms of the output waveform, the amplitude of the output waveform can be kept more constant over variations in bit pattern. Two embodiments of this technique are described below with respect to FIGS. 14 and 15.  
         [0114]    [0114]FIG. 14 is a circuit diagram of an integrated circuit  1401 , including a distributed amplifier  1400  integrated with a distributed current source termination network  1404  including extra current sources  1408   a  and  1408   b , in accordance with one embodiment of the present invention. The topology shown in FIG. 14 is a variation of the topology shown in FIG. 11, whereby most of the current (e.g., 80-90%) is supplied from the distributed current source termination network  1402 , as described with respect to FIG. 11, and the remainder is supplied from the extra current sources  1408   a ,  1408   b , embedded in output transmission line  1410  of the distributed amplifier  1400 , using the techniques for absorbing parasitic capacitance and maintaining equal phase delays described with respect to FIGS. 6 and 7.  
         [0115]    The output transmission line  1410  is terminated with a frequency dependent termination impedance network  1414  comprising a reverse termination resistor R termout  and a sense resistor R sense  for monitoring the output bias voltage, as previously described with respect to FIGS. 2 and 3.  
         [0116]    [0116]FIG. 15 is a circuit diagram of an integrated circuit  1501 , including a distributed amplifier  1500  integrated with a distributed current source termination network  1504  including extra current sources  1508   a  and  1508   b , in accordance with one embodiment of the present invention. The topology shown in FIG. 15 is a variation of the topology shown in FIG. 14, and includes delay sections  1516   a - b . The delay section  1516   a  is connected to the input transmission line  1512  of the distributed amplifier  1500 , and includes inductor elements  1518   a - b  and shunt capacitor  1520 . The delay section  1516   b  includes inductor element  1522  inserted in the output transmission line  1510 . The delay sections  1516   a - b  are used to maintain equal phase delays between the output and input transmission lines  1510 ,  1512 , as previously described with respect to FIGS. 6 and 7. The output transmission line  1510  is terminated with a frequency dependent termination impedance network  1514  comprising a reverse termination resistor R termout  and a sense resistor R sense  for monitoring the output bias voltage, as previously described with respect to FIGS. 2 and 3.  
         [0117]    Using a Tee or Pi Attenuator To Reduce Jitter  
         [0118]    [0118]FIG. 16 is a circuit diagram of a distributed current source  1600  configured as a Tee attenuator, in accordance with one embodiment of the present invention. The distributed current source  1600  includes two current sources  1602   a - b . Each current source  1602   a - b  is modeled by a shunt capacitance  1604   a - b  (C ds ) and a shunt resistance  1606   a - b  (R ds ). Each current source  1608   a - b  is also connected in shunt with a series resistor  1610   a - c  (R series ), which is connected in series with a matching inductor  1612   a - c  (L series ). The input capacitances  1604   a - c  are compensated for by adding the series inductances  1612   a - c  to keep the characteristic impedance Z 0  constant. For a single current source, the characteristic impedance Z 0  can be represented mathematically as follows: 
           Z   0 ={square root}{square root over (( R   series   +jWL   series )/( G   dS   +jwC   dS ))},  (7) 
         [0119]    where G ds  is the shunt conductance of the current source.  
         [0120]    The configuration shown in FIG. 16 makes the shunt resistance of the current sources into attenuators, which reduces jitter when the distributed amplifier is driven into saturation. The distributed current source  1600  can include any number of gain devices and can also be configured as a pi attenuator.  
         [0121]    [0121]FIG. 17 is a circuit diagram of a distributed current source  1700 , which is the distributed current source  1600  shown FIG. 16 modified to reduce bias dependence at high frequencies, in accordance with one embodiment of the present invention. The distributed current source  1700  is the same configuration as the distributed current source  1600  except for the addition of inductors  1702   a - c  connected in shunt with the series resistors  1610   a - c . The added inductors  1702   a - c  shunt the series resistors  1610   a - c  at dc so that a voltage is not dropped across the series resistors  1610   a - c.    
         [0122]    The above description is included to illustrate the operation of the preferred embodiments and is not meant to limit the scope of the invention. Rather, the scope of the invention is to be limited only by the claims. From the above discussion, many variations will be apparent to one skilled in the relevant art that would yet be encompassed by the spirit and scope of the invention.