Abstract:
A partitioned optical delay line apparatus for time-steering large array antenna converting microwave signals to optical signals which are optically delayed in binary programmable fiberoptic delay lines to provide a number of output signal delay sets.

Description:
STATEMENT OF GOVERNMENT INTEREST 
     The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalty thereon. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to an optical delay line apparatus and, more particularly, to a partioned optical delay line apparatus for time steering of large one-dimensional array antennas. 
     The state of the art of optical delay line apparatus is well represented and alleviated to some degree by the prior art apparatus and approaches which are contained in the following U.S. Patents: 
     U.S. Pat. No. 3,368,202 issued to Crousel on Feb. 6, 1968; 
     U.S. Pat. No. 4,671,604 issued to Soref on June 9, 1987; 
     U.S. Pat. No. 4,671,605 issued to Soref on June 9, 1987; 
     U.S. Pat. No. 4,714,314 issued to Yang et al on Dec. 22, 1987; 
     U.S. Pat. No. 4,725,844 issued to Goodwin et al on Feb. 16, 1988; 
     U.S. Pat. No. 4,814,773 issued to Wechsberg et al on Mar. 21, 1989; 
     U.S. Pat. No. 4,814,774 issued to Herczfeld on Mar. 21, 1989; and 
     U.S. Pat. No. 4,832,433 issued to de La Chapelle et al. on May 23, 1989. 
     The Crousel patent is directed to a memory core matrix and simple delay means like magnetic drum apparatus or sonic delay lines in place of the complicated interconnection network, summation equipment and shift registers which are employed in a multibeam receiving system. 
     The Soref patent (604) describes a wavelength dependent, tunable, optical time delay system for electrical signals having a conversion/tuning unit for converting an incoming electrical signal into an optical signal as well as selectively varying the wavelength of the optical signal. By selectively varying the wavelength of the optical signal, the electrical signal can effectively and rapidly time delayed as desired in response to the electronic signal. 
     The Soref patent (605) is directed to a length dependent, optical time delay/filter device for electrical signals made up of a plurality of optical fibers of varying lengths. Depending upon which fibers an optical signal (converted from an incoming electrical signal) passes through determines the time of travel of the optical signal through the device, and as a result thereof is time delayed. 
     The Yang et al patent discloses a mode dependent, optical time delay system for electrical signals having a highly multi-mode optical fiber having a step index profile in optical alignment with an optical source which is capable of converting an incoming electrical signal into an optical signal. 
     The Goodwin et al patent discusses a technique for applying selected phase delays to an optical carrier signal, the phase delays being referenced to a radio-frequency (rf) subcarrier signal. The optical signal to be phase delayed is introduced into a phase delay network comprising multiple optical paths and multiple electro-optical switches, controllable by signals generated in switching logic. The selected delays can be introduced for purposes of data modulation, or for steering an antenna beam in a phased-array antenna. 
     The Wechsberg et al patent describes a fiber optic feed network for a radar which couples the antenna with the transmitting and receiving circuitry. The feed system includes a set of optical multiplexers interconnected by sets of optical fibers. Microwave energy of the radar is converted to optical radiation for communication to the antenna, and then converted back to the microwave energy. 
     The Herczfeld patent discloses an optically controlled phased array antenna system and method of operating same utilizing fiber optic transmission lengths and controlled piezo-electric crystals or equivalent elements to introduce predetermined time delays into each light signal by controlling the respective length of each fiber optic link. The light carrying fibers are wrapped around the respective crystals in accordance with a pattern to introduce time delays corresponding to the amount of stretch given to the fiber by the energized crystals. Beam scanning is achieved by controlling the matrix of crystals to introduce appropriate time delays into the optical signals which drive the respective antenna elements. 
     The de La Chapelle et al patent is directed to a fiber-optic feed network using series/parallel connected light emitting optic-electronic components, such as laser diodes for distributing RF, microwave, MMW, digital signals, and pulse modulated light. The diodes are selected in number and impedance to provide a good wideband impedance match to the RF/microwave/MMW/digital driving source. 
     In a K-element 1-D array antenna with element to element spacing of λ/2, the time delay T k  required by the kth element for antenna pointing at angle θ with respect to boresight is given by 
     
         T.sub.k =kλsinθ/2c                            (1.1) 
    
     The total number R of different delays required for steering the antenna over a total angle θ M  with resolution θ o , is equal to 
     
         R=θ.sub.M /θ.sub.o                             ( 1.2) 
    
     Typical R values are of the order of several thousands. An efficient fiberoptic delay line architecture that can easily handle this large number of delays and thus addressing each element, is the binary programmable fiberoptic delay line (BIFODEL). In the BIFODEL the microwave signal to be delayed, is converted to an optical signal via the use of a laser diode and is then routed through M fiber segments, where M=log 2  (R). Each fiber segment has a length that is equal to twice the length of its right neighbor. The length of the smallest segment is such that the delay introduced corresponds to the desired delay resolution T min . Selection of the fiber segments, through which the signal is routed, can be achieved via the use of M 2×2 optical switches, each of which allows the signal to enter or to bypass a specific fiber segment. After the signal has been routed through the proper fiber segments, it is detected and subsequently buffered and further processed. The importance of the BIFODEL comes because the total number of delays that can be generated is equal to 2 M , and thus with a small number of fiber segments a very large number of delays can be generated, e.g., for M=12 we have up to 4,096 possible delays. A BIFODEL prototype with M=8 and passband in the 500-1000 MHz band has been demonstrated in the R&amp;D Center. 
     Equation 1 shows that the delay and the delay resolution T min  of the BIFODEL are different for each element, and this implies that a different BIFODEL is required for each array element. This situation is impractical because it results in a large amount of hardware since current and future 1- and 2-D antenna arrays with several thousand elements are rather typical, which implies that several thousand different BIFODELs would be required. Note that a far worse situation would be faced with 2-D antennas as well, with the hardware complexity requirement being proportional to K 2 , where K×K are the array dimensions. 
     Efficient delay line architectures that can handle the above problems without requiring K different BIFODELs do not exist, at least in the open literature. In this disclosure there is presented a new, very powerful technique that is appropriate for large array antennas (&gt;1,000), and when used in conjunction with either of the disclosed architectures or even simple BIFODELs it realizes very large hardware savings (&gt;92 percent). 
     While the above-cited references are instructive, there still remains a need to provide a partitioned optical delay line apparatus for time steering of very large one-dimension array antennas. The present invention is intended to satisfy that need. 
     SUMMARY OF THE INVENTION 
     The present invention utilizes a partitioned optical delay line apparatus which is capable of time steering very large (i.e. &gt;1000 elements) one-dimensional array antennas. The apparatus provides for the generation of multiple beams with savings in hardware greater than 92 percent of prior art devices. 
     The total number of different delays required for steering an antenna over a total angle 
     
         R=θ.sub.M /θ.sub.O 
    
     are typically in the order of several thousands. An efficient fiberoptic delay line device which can handle this large number of delay and thus address each element is the binary programmable fiberoptic delay line (BIFODEL). The (BIFODEL) delays the microwave signal and linearly modulates the intensity of a laser diode. The optical signal produced is then routed through fiber segments which each have different lengths and thus provide a variety of delay s elections that can be utilized to provide an overall delay corresponding to the desired delay resolution. 
     It is one object of the present invention, therefore, to provide an improved partitioned optical delay line apparatus. 
     It is another object of the invention to provide an improved partitioned optical delay line apparatus that can time-steer numerically large one-dimensional array antennas. 
     It is still another object of the invention to provide an improved partitioned optical delay line apparatus wherein the total number of different delays that are required for steering an antenna over a wide angle is generated by a programmable fiberoptic delay line. 
     It is yet another object of the invention to provide an improved partitioned optical delay line apparatus wherein the output signals from the fiberoptic delay line comprise a plurality of sets of output delay signals. 
     It is still a further object of the invention to provide an improved partitioned optical delay line apparatus wherein a very large number of delays can be generated with a small number of optic fiber segments. 
     These and other advantages, objects and features of the invention will become more apparent after considering the following description taken in conjunction with the illustrative embodiment in the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a delay line for generating delays of the jth set; 
     FIG. 2 is a block diagram of a partitioned delay line apparatus according to the present invention; and 
     FIG. 3 is a block diagram of a partitioned binary programmable fiberoptic delay line apparatus for steering an NXE element one-dimensional antenna array. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Consider partition the K elements of an 1-D array into E sets of N elements each, such that K=NE, in which N&lt;&lt;K, e.g., for K=1000, N=64. Using the indices j=1, 2, 3, . . . , E, and i=1, 2, 3, . . . , N for representing the set and element address respectively, we can translate T k  into T ji  using to the following relations: 
     
         j=[k-1/N]+1                                                (2.1) 
    
     
         i=k-(j-1)N                                                 (2.2) 
    
     where [k-1/N] denotes the integer value of the quotient k-1/N. Note that Equation 2.2 can be used in order to translate T ji  into T k . Hereafter the 1st or j=1 element set will be called the &#34;reference&#34; set, and will denote its N delays T 1i , (i=1, 2, . . . , N) by T i  (i=1, 2, . . . , N). It should be noted that each of these N delays may take up to R different values. 
     It is possible to design an efficient partitioned delay line architecture if the delays required by any set are basically the delays of the reference set added to a bias delay which is the same for each set, however, it varies from set to set. To see this consider applying Equation 2.2 for the description of the delay T ji  =T k , which becomes: 
     
         T.sub.ji =T.sub.i +(j-1)T.sub.N                            (2.3) 
    
     where T N  is the delay of the Nth element of the reference set. Equation 2.3 shows that the delay required by the ith element of the jth set is equal to the delay of the ith element of the reference set plus a bias delay which is equal to j-1 times the delay of the Nth element of the reference set. Observe that the bias term depends only on j and not on i, and thus it is common to all the elements of a given set. This implies that the hardware requirements for addressing the N elements of the jth set consist of an N-channel delay line (appropriate for addressing the reference set) cascaded to a single bias delay line. The latter must be able to provide R different bias delays with delay resolution of j-1)T Nmin , where T Nmin  is the delay resolution of the Nth element of the reference set. 
     Referring now ti FIG. 1, there is shown a block diagram of a BIFODEL-based implementation example for addressing the N elements of the jth set. In FIG. 1, the data in the upper part of the block used for representing the BIFODEL (binary programmable fiberoptic delay line) denotes the delay resolution or minimum delay BIFODEL requirement. The lower part of the block denotes the number of BIFODEL delay stages. It is important to realize that since N&lt;&lt;K, the N-channel reference set delay line could be implemented by using either a recirculating delay line apparatus or by a cascaded BIFODEL apparatus. 
     From the above it should be obvious that the same N-channel reference delay line is required by each element set. This implies that the same N-channel reference delay line can be used for all the E element sets in conjunction with power division. This technique is the basis of the partitioned delay line apparatus. Turning now to FIG. 2, there is shown a block diagram of a partitioned delay line apparatus. It may be seen that one N-channel reference delay line and E bias binary programmable fiberoptic delay line units are used in order to address all the K=NE elements of the array antenna. It is important to note that for the implementation of FIG. 2, all the bias binary programmable fiberoptic delay line units are optical, that is, they accept an optical input (such as the output provided by the reference delay line), and they should be able to support the optical bandwidth of the reference delay line which provide each of the N delayed signals on a different optical wavelength. Furthermore, an optical demultiplexer (DEMUX) is required at the output of each bias binary programmable fiberoptic delay line unit in order to separate the N progressively delayed signals each of which is carried by a different optical wavelength. 
     The total number of binary programmable fiberoptic delay line units required for the implementation of the architecture of FIG. 2 when the reference N-channel delay line is implemented with recirculating (C R ) or cascaded (C C ) BIFODELs is equal to 
     
         CR=E                                                       (2.4) 
    
     
         C.sub.C log.sub.2 (N)+E-1                                  (2.5) 
    
     where in both cases the number of bias binary programmable fiberoptic delay line units is equal to E-1. In both cases and for all binary programmable fiberoptic delay line units the number of delay M is equal to log 2  R. It is important to note that the presence of a separate bias binary programmable fiberoptic delay line unit per element set allows us to steer each set differently, and thus up to E different output beams may be generated. 
     It should be noted that in an alternative configuration, the N-channel reference delay line in the architecture of FIG. 2 can be substituted with N binary programmable fiberoptic delay line units each of which operates at a different optical wavelength. This circuit configuration is shown in FIG. 3 in which N reference binary programmable fiberoptic delay line units with outputs at wavelengths λ 1 , λ 2 , . . . , λ N  are optically multiplexed (MUX) and consequently power divided into E channels, each of which drives a bias binary programmable fiberoptic delay line unit. Each reference binary programmable fiberoptic delay line unit has a delay resolution that is equal to the delay resolution of the element to which it corresponds. For both the reference and the bias binary programmable fiberoptic delay line units the number of stages M is equal to log 2  (R). The requirements for the bias binary programmable fiberoptic delay line units are the same as for those in the circuit configuration that is shown in FIG. 2. These requirements are that the binary programmable fiberoptic delay line units must be optical with a bandwidth that supports all N optical wavelengths, and they must incorporate an optical DEMUX at their output. For this circuit configuration, the total number C B  of binary programmable fiberoptic delay line units that are required is equal to 
     
         C.sub.B =N+E-1                                             (2.6) 
    
     Equations 2.4, 2.5 and 2.6 demonstrate the circuit configurations of FIGS. 2 and 3 do achieve every significant delay line savings since neither of the C R , C C , and C B  are proportional to the product of NE which is the case of the straightforward implementation. In order to compare the hardware requirements of the various circuit configurations, a calculation has been made for C R , C C  and C B  for the case of K=1000 and for N values of 8, 16, 32 and 64. The results are shown in Table 1. 
     
                       TABLE 1______________________________________BIFODEL Hardare Requirements and Savings for K = 1000When the N-Channel Reference Delay Line is Implementedwith a Recirculating (C.sub.R), Cascaded (C.sub.C)and Separate BIFODEL (C.sub.B) Delay LinesRecirculating        Cascaded     Separate-BIFODEL      Savings        Savings      SavingsN   C.sub.R      Percentage                C.sub.C                     Percentage                             C.sub.B                                  Percentage______________________________________ 8  125    87.5      127  87.3    132  86.816  63     93.7      66   93.4    78   92.232  32     96.8      36   96.4    63   93.764  16     98.4      21   97.9    79   92.1______________________________________ 
    
     It should be noted that a straightforward binary programmable fiberoptic delay line unit implementation would require 1,000 different binary programmable fiberoptic delay line units. It can be seen that, as the above data show, for partitions with N≧16 all three approaches achieve very significant hardware savings which exceed 92 percent. It may further be noted that the use of recirculating and cascaded binary programmable fiberoptic delay line units achieve basically the same amount of savings which is slightly better than the savings possible with the separate binary programmable fiberoptic delay line unit approach. With respect to the latter achitecture, there is an optimum partition which yields the maximum possible savings, and is: 
     
         N=E=K                                                      (2.7) 
    
     The present invention discloses a very powerful partitioned delay line circuit configuration that can be implemented with a variety of binary fiberoptic delay line configurations. This architecture can time steer array antennas with several thousand elements, and yields hardware savings of over 92 percent with respect to that required by a straightforward implementation. 
     Although the invention has been described with reference to a particular embodiment, it will be understood to those skilled in the art that the invention is capable of a variety of alternative embodiments within the spirit and scope of the appended claims: