Abstract:
An electronic device disclosed herein includes a single photon avalanche diode (SPAD) configured to detect an incoming photon and to generate a first pulse signal in response thereto. Pulse shaping circuitry is configured to generate a second pulse signal from the first pulse signal by high pass filtering the first pulse signal. The pulse shaping circuitry includes a transistor drain-source coupled between a first node and a reference node, and a capacitor coupling the first node to an anode of the SPAD.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates to the field of single photon avalanche diodes, and, more particularly, to a pulse shaping filter for a single photon avalanche diode. 
       BACKGROUND 
       [0002]    Single photon avalanche diodes (SPADs) are used in a variety of applications, such as time of flight ranging systems, to detect incoming photons. When impinged upon by an incoming photon, a SPAD in combination with a detection circuit generates an output electrical pulse. 
         [0003]    However, these output pulses are relatively “long”, lasting on the order of 10 ns or more. Due to these relatively long pulses, depending on the frequency of arrival of incoming photons, it is possible for the distinct output pulses of the SPAD to “pile up”. That is, due to the pulse lengths, the time between impinging of individual photons may be less than the length of the pulses, and thus individual events are no longer seen as the pulses overlap one another. 
         [0004]    This results in the inability to distinguish the different incoming photons, which can render a time of flight ranging system inaccurate, since such a time of flight ranging system precisely measures the time between emission of a photon and receipt of the photon, after reflection from an object. 
         [0005]    To that end, pulse shaping circuits are used to shorten the output pulses from a SPAD. An electronic device including such a pulse shaping circuit is now described with reference to  FIG. 1 . Here, the electronic device  100  includes a SPAD  102  coupled between a high voltage node VHV and a node N 1  at the anode of the SPAD  102 . A first transistor T 1  is coupled between node N 1  and ground and is switched by a signal Vquench, and a second transistor T 2  is coupled between the node N 1  and a pull up node VANA and is switched by an enable signal EN. An output inverter  104  has an input coupled to the node N 1 . The voltage at N 1  is shown in  FIG. 2 , labeled as ANODE, and the output voltage output from inverter  104  is shown in  FIG. 2 , labeled as PIX_OUT. As can be seen, the pulse from PIX_OUT is substantial in duration, which as explained above is undesirable. 
         [0006]    Therefore, the electronic device  100  includes a pulse shaper  106  that operates to truncate the PIX_OUT signal so as to produce a signal PS_OUT suitable for use. The pulse shaper  106  includes an inverter  108  receiving the signal PIX_OUT as input, and outputting the signal PS_INT, which is an in inverted version of PIX_OUT, as shown in  FIG. 2 . A delay block  110  is coupled to the output of the inverter  108  and generates a delayed version of PS_INT, shown as PS_DEL in  FIG. 2 . The delay block  110  is coupled to an inverting input of an AND gate  112 , and the output of the inverter  108  is coupled to a non-inverting input of the AND gate  112 . The resulting signal, PS_OUT, is a truncated version of PS_INT, and is suitable for use. 
         [0007]    As can be seen from  FIG. 1 , the pulse shaping circuit  100  utilizes multiple logic components, and therefore consumes an undesirable amount of current and area. Since reductions in both power consumption and area are commercially desirable, new designs of pulse shaping circuits  100  are desired. 
       SUMMARY 
       [0008]    This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter. 
         [0009]    An electronic device disclosed herein includes a single photon avalanche diode (SPAD) configured to detect an incoming photon and to generate a first pulse signal in response thereto. Pulse shaping circuitry is configured to generate a second pulse signal from the first pulse signal by high pass filtering the first pulse signal. 
         [0010]    Another embodiment is directed to an electronic device having a photodiode with an anode coupled to a first node and a cathode coupled to a high voltage node. A first resistance is coupled between the first node and a reference node, and a second resistance is coupled between a second node and the reference node. A capacitor is coupled between the first and second nodes. An inverter has an input coupled to the second node and an output generating a pixel output. 
         [0011]    A further embodiment is directed to a single photon avalanche diode (SPAD) having an anode coupled to a first node and a cathode coupled to a supply voltage. A first variable resistance is coupled between the first node and a reference node, and a second variable resistance coupled between a second node and the reference node. A capacitor is coupled between the first and second nodes, and an inverter has an input coupled to the second node and an output generating a pixel output. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a schematic diagram of a prior art single photon avalanche diode pixel having a pulse shaping circuit. 
           [0013]      FIG. 2  is a timing diagram of the various signals of the circuit of  FIG. 1 . 
           [0014]      FIG. 3  is a schematic diagram of a single photon avalanche diode pixel having a pulse shaping circuit in accordance with this disclosure. 
           [0015]      FIG. 4  is a timing diagram of the various signals of the circuit of  FIG. 3 . 
           [0016]      FIG. 5  is a schematic diagram of another embodiment of a single photon avalanche diode pixel having a pulse shaping circuit in accordance with this disclosure. 
           [0017]      FIG. 6  is a timing diagram of the various signals of the circuit of  FIG. 5 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    In the following description, numerous details are set forth to provide an understanding of the present disclosure. It will be understood by those skilled in the art, however, that the embodiments of the present disclosure may be practiced without these details and that numerous variations or modifications from the described embodiments may be possible. 
         [0019]    With reference to  FIG. 3 , a single photon avalanche diode (SPAD) pixel circuit is now described. The SPAD pixel circuit  200  includes a SPAD  202  having a cathode coupled to a high voltage node VHV and an anode coupled to a node N 1 . A first transistor Q 1  an NMOS transistor having its drain coupled to node N 1 , its source coupled to the reference node, and its gate coupled to receive a control signal Vquench. A second transistor Q 2  is a PMOS transistor having its source coupled to the pull up node VANA, its drain coupled to node N 1 , and its gate coupled to an enable signal EN. 
         [0020]    A pulse shaper  206  is coupled to node N 1 . The pulse shaper  206  includes a capacitor C coupled between node N 1  and a node N 2 . A third transistor Q 3  is an NMOS transistor having its drain coupled to the node N 2 , its source coupled to the reference node, and its gate coupled to a biasing signal Vhpbias. An inverter  204  has an input coupled to node N 2 . 
         [0021]    Operation of the SPAD pixel circuit  200  is now described. The circuit  200  is capable of operating in a disabled mode and an enabled mode. In the disabled mode, the enable signal EN is low, causing the transistor Q 2  to pull the node N 1 , and thus the anode of the SPAD  202 , to the voltage at the pull up node VANA, such that the voltage VHV-VANA is not sufficient to bias the SPAD  202  for avalanche mode; in this mode the pixel Vquench line is connected to ground to prevent a leakage path through Q 1 . In the disabled mode, the SPAD  202  is therefore between the high voltage VHV and the pull up voltage VANA, and does not generate an output when inpinged upon by an incoming photon. 
         [0022]    When in the enabled mode, the enable signal EN is high, switching off the transistor Q 2 . Then, when the SPAD  202  is impinged upon by an incoming photon, it generates a pulse at node N 1 , which is represented in the graph of  FIG. 4  as ANODE. The RC time constant, or time for the signal ANODE at node N 1  to fall below the threshold of the inverter  204 , is set by the resistance of transistor Q 1 , to secure a robust SPAD quenching operation, and is undesirably long. 
         [0023]    Therefore, the pulse shaper  206  is used. The capacitor C blocks the DC component but allows the fast rising edge on the ANODE at SPAD event to pass to node N 2 . The transistor Q 3  serves to sink current from the node N 2 , the signal of which is represented in the graph of  FIG. 4  as VTRIG. The rate at which the transistor Q 3  sinks current from the node N 2  depends upon the resistance between its drain and source, which is adjusted via application of the bias signal VHPBIAS to its gate. 
         [0024]    The RC time constant of the signal VTRIG at node N 2  is dominated by the total capacitance at node N 2  and the resistance between the drain and source of transistor Q 3 . Via careful selection of the capacitance of the capacitor C, and of the biasing voltage VHPBIAS, the width of the pulse of the signal VTRIG can thus be adjusted. The processed signal VTRIG is fed to the input of the inverter  204 , and then output, represented as the signal PIX_OUT in  FIG. 5 . 
         [0025]    In addition, the “dead” time of the SPAD  202  can be adjusted via selection of the quench signal VQUENCH, which adjusts the resistance between the drain and source of transistor Q 1 , and therefore the discharge rate of the anode of the SPAD  202 . 
         [0026]    This pulse shaper  206  provides for a properly shaped output signal of a desired length, and does so with low area overhead and low power consumption through the use of a sole and only transistor Q 3  plus capacitor C, as opposed to the prior art design of  FIG. 1 , the logic components of which utilize multiple transistors. The capacitor can be implemented as a MIM or MOM structure over existing pixel circuitry, requiring no additional area. Thus, the physical size of the SPAD pixel circuit  200 , and the power consumption thereof, can be reduced utilizing the devices described herein. 
         [0027]    As should be readily appreciated, the SPAD may instead be coupled to a negative supply, and the circuit adjusted accordingly. Such an embodiment is now described with reference to  FIG. 5 . 
         [0028]    Here, the SPAD pixel circuit  200 ′ includes a SPAD  202 ′ having its anode coupled to a negative voltage node −Ve and a cathode coupled to node N 1 ′. The first transistor Q 1 ′ is a PMOS transistor having its drain coupled to node N 1 ′, its source coupled to a positive supply node +Ve, and its gate coupled to receive the control signal Vquench. The second transistor Q 2 ′ is an NMOS transistor having its source coupled to the reference node, its drain coupled to node N 1 ′, and its gate coupled to the enable signal ENB. 
         [0029]    The pulse shaper  206 ′ is coupled to node N 1 ′. The pulse shaper  206 ′ includes a capacitor C coupled between node N 1 ′ and node N 2 ′. The third transistor Q 3 ′ is a PMOS transistor having its drain coupled to the node N 2 ′, its source coupled to a logic supply, and its gate coupled to a biasing signal Vhpbias. The inverter  204 ′ has an input coupled to the node N 2 ′ and a supply terminal coupled to the logic supply. 
         [0030]    Operation of the SPAD pixel circuit  200 ′ proceeds similarly to that of the SPAD pixel circuit  200 . With reference to  FIG. 6 , in operation when the SPAD  202 ′ is impinged upon by an incoming photon, it generates a pulse at node N 1 ′, pulling N 1 ′ low, which is represented in the graph of  FIG. 6  as ANODE. The RC time constant, or time for the signal ANODE at node N 1 ′ to rise above the threshold of the inverter  204 ′, is set by the resistance of transistor Q 1 ′, to secure a robust SPAD quenching operation. The capacitor C blocks the DC component but allows the fast falling edge on the ANODE at SPAD event to pass to node N 2 ′. The transistor Q 3 ′ serves to source current to the node N 2 ′, the signal of which is represented in the graph of  FIG. 4  as VTRIG. The rate at which the transistor Q 3 ′ sources current to the node N 2 ′ depends upon the resistance between its drain and source, which is adjusted via application of the bias signal VHPBIAS to its gate. The processed signal VTRIG is fed to the input of the inverter  204 ′, and then output, represented as the signal PIX_OUT in  FIG. 6 . 
         [0031]    Although the preceding description has been described herein with reference to particular means, materials and embodiments, it is not intended to be limited to the particulars disclosed herein; rather, it extends to all functionally equivalent structures, methods, and uses, such as are within the scope of the appended claims.