Abstract:
High performance thin-film, transistors are entirely processed at temperatures not exceeding 150° C., using amorphous multi component dielectrics based on the mixture of high band gap and high dielectric constant (K) materials. The sputtered or ink jet printed mixed dielectric materials such as Ta 2 O 5  with SiO 2  or Al 2 O 3  or HfO 2  with SiO 2  or Al 2 O 3  are used. These multicomponent dielectrics allow producing amorphous dielectrics to be introduced in high stable electronic devices with low leakage currents, while preserving a high dielectric constant. This results in producing thin film transistors with remarkable electrical properties, such as the ones produced based on Ga—In—Zn oxide as channel layers and where the dielectric was the combination of the mixture Ta 2 O 5 :SiO 2 , exhibiting field-effect mobility exceeding 35 cm 2  V −1  s −1 , close to 0 V turn-on voltage, on/off ratio higher than 10 6  and subthreshold slope below 0.24 V dec −1 .

Description:
TECHNICAL FIELD 
       [0001]    Transparent electronics is one of the most fascinating and fast-growing research areas since the first fully transparent thin-film transistors (TFTs) based on ZnO were presented in 2003. 1  A significant effort has been put on enhancing device&#39;s performance and lowering their maximum processing temperature 2  down to at least 150° C., since this is normally seen as the upper limit for the so-called low temperature electronics, where low cost and flexible substrates are used. Besides that, we must include all silicon based CMOS technology demanding for use of high k dielectrics exhibiting very low leakage current highly relevant of all set of devices in micron, submicron and nanoscale ranging sizes. 
       SUMMARY OF THE INVENTION 
       [0002]    In summary, the properties of sputtered or ink jet multicomponent thin-film dielectrics based on mixtures of high band gap and high κ such as Ta 2 O 5  with SiO 2  or Al 2 O 3  or HfO 2  with SiO 2  or Al 2 O 3  are the core of the present invention. These materials were used to produce as a proof of concept transparent TFTs using Ga—In—Zn oxides as channel layer with a maximum processing temperature of 150° C. All the dielectric thin-films exhibit an amorphous structure. As suggested by XPS and ellipsometry analysis, short-range order increases as the total amount of the metal component of the high κ component, such as Ta or Hf, for instance, concentration increase, i.e., disorder is easier to obtain with multicomponent dielectrics. For these multicomponent dielectrics, parameters such as E opt  and κ can be adjusted between those of their constituting binary oxides. Integration of these insulators on transparent TFTs results in devices with remarkable performance. Even if the properties of TFTs employing Ta 2 O 5  are considerably enhanced over the other sputtered binary dielectrics tested (SiO 2  and Al 2 O 3 ), the off-current and I G  are relatively high, due to the low band offset of Ta 2 O 5  with GIZO. These limitations are significantly improved when Ta 2 O 5 :SiO 2  (produced by co-sputtering) or Ta 2 O 5 :Al 2 O 3  s.t. (produced from a single target) or HfO 2 :SiO 2  or HfO 2 :Al 2 O 3  dielectrics are used instead. For instance, best overall TFT properties are obtained with Ta 2 O 5 :SiO 2 : μ FE =35.5 cm 2  V −1  s −1 , V on =0 V, on/off ratio=3.3×10 6  and S=0.24 V dec −1 . For the Ta 2 O 5 :Al 2 O 3  system similar performance can be achieved (even higher on/off ratio, exceeding 10 7 ), but only when the dielectric thin-film is produced from a single target with a predetermined composition, since co-sputtering of Ta 2 O 5  and Al 2 O 3  results in considerable damage of the growing film and deteriorated device performance. Overall similar results can be achieved with other proposed combinations, such as the ones referred involving hafnia with silica or hafnia with alumina. 
         [0003]    The overall results are comparable with the ones exhibited by devices using 400° C. PECVD deposited SiO 2  dielectric, proving that a correct balance between good semiconductor/dielectric interfaces and high-κ bulk dielectrics that compensate defects inherent to physical and low-temperature processing can be achieved with these multicomponent insulators. 
         [0004]    They also can be used in all known CMOS technology. 
         [0005]    When the TFTs are stressed under constant I D  stress, V G @1nA (V on ) and S are the most significantly affected parameters, but they change under different dynamics for the various dielectrics. While devices using Ta 2 O 5  reveal a reversible V on  shift, the ones based on Ta 2 O 5 :SiO 2  dielectric do not show a significant variation on this parameter, but S increases during stressing time, due to the increase in the off-current (also in a reversible way). Ta 2 O 5 :Al 2 O 3  and PECVD SiO 2  TFTs present similar stress mechanisms that result in V on  shift (reversible) and in the appearance of kinks in the transfer curves (hence, affecting S). These kinks are only removed after annealing, suggesting that they might be related with defect states creation in the dielectric during stress. The detailed physics behind the stress mechanisms of these oxide semiconductor TFTs is currently under study. Note that the magnitude of variations obtained herein is comparable to the one reported on literature for GIZO TFTs stressed under similar conditions, but produced using PECVD SiN x  deposited at temperatures exceeding 300° C., even considering the larger timescale of the present stress tests (24 h) against 44, 46 the ones reported on literature (10 h). 44, 46    
         [0006]    TFTs using Ta 2 O 5 :SiO 2  as the dielectric layer were also used as a proof of concept to fabricate an active matrix backplane of a LCD display, showing that these low temperature devices are, even at this early stage, already compatible with current display technologies and seem to be a viable solution for more demanding applications, such as AMOLED displays. 
         [0007]    The present invention comprises a process for manufacturing a dielectric for an electronic semiconductor device comprising the step of depositing a multicomponent amorphous binary oxide as the device dielectric, wherein a first component binary oxide has a substantially higher band gap, E G , and substantially lower dielectric constant, κ, than a second component binary oxide which has a substantially lower band gap, E G , and substantially higher dielectric constant, κ. 
         [0008]    A preferred embodiment is such that the first component binary oxide is one or more of SiO 2  or Al 2 O 3 , and the second component binary oxide is one or more of Ta 2 O 5 , HfO 2 , Y 2 O 3  or TiO 2 . 
         [0009]    A preferred embodiment comprises the depositing step comprising rf magnetron sputtering of:
       Ta 2 O 5 , HfO 2 , Y 2 O 3  or TiO 2 , and   SiO 2  or Al 2 O 3 .       
 
         [0012]    A preferred embodiment is such that the sputtering is carried out below 150° C. 
         [0013]    A preferred embodiment is such that the dielectric is obtained by:
       single-target sputtering with a target mixture of the first component binary oxide and the second component binary oxide, or   co-sputtering the first component binary oxide and the second component binary.       
 
         [0016]    A preferred embodiment comprises a step of annealing at 150° C. for more than 25 minutes in air. 
         [0017]    A preferred embodiment is such that the rf power ratios vary from 0.1 to 10 between the target containing the high dielectric material and the target containing the high band gap material, either in the ceramic or in the metal form, under an argon atmosphere and the presence of an oxygen partial pressure that varies from 0% to 99% of the total deposition pressure. 
         [0018]    A preferred embodiment comprises ink jet deposition of suspensions and solutions comprising said multicomponent amorphous binary oxide with sizes varying from 1 nm to 40 nm. 
         [0019]    The present invention also describes a dielectric for using in an electronic semiconductor device comprising a multicomponent amorphous binary oxide dielectric, wherein a first component binary oxide has a substantially higher band gap, E G , and substantially lower dielectric constant, κ, than a second component binary oxide which has a substantially lower band gap, E G , and substantially higher dielectric constant, κ. 
         [0020]    A preferred embodiment is such that the first component binary oxide is one or more of SiO 2  or Al 2 O 3 , and the second component binary oxide is one or more of Ta 2 O 5 , HfO 2 , Y 2 O 3  or TiO 2 . 
         [0021]    The present invention also describes a transistor wherein its dielectric is the said multicomponent amorphous binary oxide dielectric. 
         [0022]    A preferred embodiment is such that the dielectric is obtainable by any one of the previously mentioned processes. 
         [0023]    A preferred embodiment comprises as the active semiconductor a multicomponent amorphous oxide comprising a plurality of metallic cations with electronic configuration (n−1)d 10  ns 0  with n≧4. 
         [0024]    A preferred embodiment comprises GIZO as the active semiconductor and further comprising IZO as the gate electrode. 
         [0025]    A preferred embodiment comprises a display comprising a plurality of said transistor as active display elements. 
         [0026]    A preferred embodiment comprises said dielectric in a transistor wherein it is a NMOSFET, PMOSFET, MISFET or other CMOS transistor. 
         [0027]    A preferred embodiment comprises an electronic device comprising a plurality of said transistor and/or display as active device elements. 
       BACKGROUND OF THE INVENTION 
       [0028]    More recently, it was proved that multicomponent amorphous oxide semiconductors based on combinations of metallic cations with (n−1)d 10 ns 0  (n≧4) electronic configuration, like gallium-indium-zinc oxide (GIZO) 3-6 , provide enhanced performance over single binary oxides. Besides that, due to their amorphous structure, these materials also allow for lower processing temperature, improved reproducibility and uniformity in large areas and smoother surfaces when compared with polycrystalline materials 7, 8 . Even if with post-processing temperatures of only 150° C., the TFTs based on amorphous oxide semiconductors present remarkable characteristics 3 , the overall maximum processing temperature of these devices is generally much higher and dictated by the nature and fabrication process of the dielectric layer. 
         [0029]    Most of the oxide semiconductor based TFTs rely on conventional dielectrics from Si technology, like PECVD SiO 2   9, 10  and SiN x :H 11, 12 , or even thermally-grown SiO 2  when Si wafers are used as substrates 3, 13, 14 . While good performance can be obtained with these dielectrics when processed above 250-300° C., their properties are generally degraded when temperatures around 150° C. are established as the maximum for transistor fabrication 14-17 . The lower performance is usually consequence of less compact films and higher density of defects on the dielectric&#39;s bulk and on its interface with the oxide semiconductor. 
         [0030]    Chemically deposited organic dielectrics have been investigated for transparent TFTs produced at low temperature with very promising results, but usually their growing and/or curing process is rather slow 18-20 . Physical routes like radio-frequency (r.f.) magnetron sputtering have also been tested for low-temperature dielectric fabrication. This technique is theoretically not seen as a potential candidate for the production of reliable insulators, since dielectrics are generally very hard to sputter, leading to the usage of high power densities that might damage the growing films and interfaces. 
         [0031]    Nevertheless, working oxide semiconductor based TFTs were already obtained with low temperature sputtered SiO 2   5 , ferromagnetic materials, like Bi 1.5 Zn 1.0 Nb 1.5 O 7  (BZN) with MgO capping layers 21 , and high-κ dielectrics, like Y 2 O 3   22, 23 , Al 2 O 3   24 , HfO 2   25  and Ta 2 O 5   26 . but they suffer from the problem related crystallinity and so leakage problems, which does not happen with the proposed multicomponent dielectric structures, since they are amorphous. 
         [0032]    Given that substrate/film bombardment can indeed be a problem in sputtering, materials with a high-κ are desirable, since their added capacitance can compensate the higher density of interface traps and thus improve transistor performance, namely decrease the subthreshold slope (S) and the operating voltage 27 . However, some of these dielectrics, specially the higher-κ ones, present a polycrystalline structure even if deposited at room temperature, whereas an amorphous structure is generally preferred since grain boundaries act as preferential paths for impurities diffusion and leakage current, resulting in inferior dielectric&#39;s reliability 28 . Besides that, amorphous materials present smoother surfaces, which can bring improved interface properties 27, 28 . High-κ materials have another drawback: as a general rule, higher-κ corresponds to lower bandgap (E G ), hence to less favorable band offsets between the dielectric and the semiconductor, resulting in structures with low breakdown voltage and high leakage current 27, 29 . This is even more severe when we consider their integration with oxide semiconductors, which have a considerably higher than Si or organic semiconductors. 
         [0033]    As a possible solution for these high-κ related issues, multicomponent dielectrics based on a mixture of Ta 2 O 5  (high-κ, low E G ) and SiO 2  or Al 2 O 3  (low-to-moderate κ, high E G ) produced by sputtering at room temperature are proposed. Sputtered Ta 2 O 5 , which has been extensively used as a dielectric is organic TFTs 30, 31  is here selected as a starting high-κ material essentially due to its relatively high sputtering rate even with low power density, which results in high throughput and low damage to the growing film and its interfaces. The combination of Ta 2 O 5  with SiO 2  or Al 2 O 3  has been found to be useful for applications such as optical filters and corrosion resistant coatings 32-34 , but in most cases the materials are grown as multi-layer structures rather as single multicomponent layers. However, for a transistor&#39;s insulator, multicomponent layers (or alternatively multiple layers of multicomponent materials) are preferable since binary oxides often have a tendency to crystallize even at low (post)processing temperatures 27-29 . The resulting amorphous insulators presented in this invention exhibit good properties and allow to produce oxide semiconductor based TFTs with comparable performance to the ones fabricated on PECVD and even thermal SiO 2 . Good stability under 24 h current stress measurements, with recoverable turn-on voltage variation smaller than 2 V in optimized transistors, and integration of the devices in an active matrix liquid crystal display (AMLCD) are also shown to prove the viability for these dielectrics to be used in current and future electronic applications where very low temperature processing and high performance are required. 
       GENERAL DESCRIPTION OF THE INVENTION 
       [0034]    The devices were produced with a staggered bottom gate structure on top of Corning 1737 glass substrates. The gate electrode was a 180 nm thick In—Zn—O (denoted IZO) layer deposited by r.f. magnetron sputtering at room temperature in a home-made system, using a In 2 O 3 :ZnO ceramic target with a nominal composition of 85 wt % of In 2 O 2  and 15 wt % of ZnO. The ceramic target was processed by solid state reaction from In 2 O 3  (Puratronic, 99.997%) and ZnO (Puratronic, 99.9995). A power density (P rf ) of 2.5 Wcm −2 , an oxygen and argon atmosphere (0.75% O 2 ) and a deposition pressure (p dep ) of 0.2 Pa were used for processing the IZO thin-films. The dielectric films were also produced by r.f. magnetron sputtering without intentional substrate heating in an AJA 1300-F system. Ar/O 2  flow ratio of 14/1 and p dep =0.3 Pa were used for all the dielectrics. The binary oxides—Ta 2 O 5 , SiO 2  and Al 2 O 3 — were sputtered from commercially available ceramic targets (Super Conductor Materials, SCM), using P rf ≈4.9, 7.4 and 9.9 Wcm 2 , respectively. Note that different P rf  values were used in order to maintain sputtering rates for SiO 2  and Al 2 O 3  at reasonable values (&gt;2 nm min −1 ). 
         [0035]    For Ta 2 O 5  a sputtering rate of 4 nm min −1  was achieved, even if using a lower P rf . For the multicomponent dielectrics, co-sputtering of Ta 2 O 5  and SiO 2  using a P rf  ratio of 0.67 was used to grow Ta 2 O 5 :SiO 2  films, while Ta 2 O 5 :Al 2 O 3  films were produced by two different approaches: by co-sputtering of Ta 2 O 5  and Al 2 O 3 , with a P rf  ratio of 0.5; or using a single target having a nominal composition of 75 wt % of Ta 2 O 5  and 25 wt % of Al 2 O 3 . The composition of the target, prepared by solid state synthesis from Ta 2 O 5  (Alfa Aesar 99.95%) and Al 2 O 3  (Alfa Aesar, 99.99%), corresponds to TaAlO 4   35 . A P rf =7.4 Wcm −2  was used to produce the dielectric films from this target. All the insulators were 300-350 nm thick to prevent high leakage current. 
         [0036]    The semiconductor layer, a Ga—In—Zn—O film (denoted GIZO) 25-30 nm thick, was sputtered from a commercial ceramic target (LTS (Chemical) Inc.) with a composition of 61 wt % of Ga 2 O 3 , 18 wt % of In 2 O 3  and 21 wt % of ZnO. The same home-made system used for IZO films was used for GIZO, being the deposition parameters reported elsewhere 3 . For the source/drain electrodes, IZO layers were deposited under similar conditions as the electrode, but with a thickness around 300 nm in order to enhance carrier injection. All the layers were patterned using conventional lift-off process. The transistors were produced with a width to length ratio (W/L) of 25/25 μm. After production, the devices were annealed at 150° C. for hour in air. The electrical properties of the TFTs were evaluated using a Cascade Microtech M150 probe station inside a dark box and an Agilent 4155C parameter analyzer. 
         [0037]    To study the structural, compositional and electrical properties of the dielectrics, thin-films were also deposited on p-type Si wafers, using 200 nm thick Al electrodes (1 mm diameter) deposited by e-beam evaporation on both sides of the Si/insulator structures for electrical measurements. X-ray diffraction (XRD) measurements were performed at room temperature on a Siemens D-500 diffractometer, using Cu Kαradiation (λ=1.5418 Å). X-ray photoelectron spectroscopy (XPS) was carried out using a PHI ESCA 5500. Capacitance and dielectric constant were extracted from metal-insulator-semiconductor (MIS) structures biased in accumulation mode, using the quasi-static capacitance-voltage (QSCV) mode of the Agilent 41550 parameter analyzer, being the obtained results confirmed at 1 MHz using an Agilent 4294A precision impedance analyzer. The thicknesses of the thin-films were measured using a Sloan Dektak 3 profilometer. Optical properties of the insulators were studied by spectroscopic ellipsometry, using a Jobin Yvon UVISEL ellipsometer. The measurements were made in a range between 0.65 and 6.5 eV with an incidence angle of 70° and the data were modulated with a four-layer model consisting of substrate (c-Si reference), interfacial layer (SiO 2  reference), bulk (a dispersion model to simulate the various insulator films) and surface roughness composed of 50% of dielectric material and 50% of voids 36 . 
         [0038]    To show the viability of the processes and materials described above, a 2″ diagonal active matrix backplane with 128×128 pixels was produced and integrated in an AMLCD by Hewlett-Packard. In these first prototypes, Ti/Au electrodes were used instead of IZO, to allow for better integration with driver&#39;s circuitry. Additionally, reactive ion etching (RIE) was used to pattern the dielectric layer (Ta 2 O 5 :SiO 2 ), in order to reduce the damage and subsequent failure on the MIS capacitors that is commonly caused by the lift-off process in larger areas. Before integration with the LCD frontplane, the backplane was covered with a spin-coated negative photoresist, SU-8, which acted as a passivation layer. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0039]      FIG. 1 . ( a ) Structural and ( b ) compositional analysis of the sputtered dielectrics annealed in air at 300° C., obtained by XRD and XPS, respectively. Peak positions for β crystalline orthorhombic Ta 2 O 5  (ASTM, card 25-0922) are shown for reference in ( a ). 
           [0040]      FIG. 2 . Spectroscopic ellipsometry data obtained for the dielectric films of Ta 2 O 5 :SiO 2  ( a  and  b ) and Ta 2 O 5 :Al 2 O 3  ( c  and  d ) systems. Dependences of the refractive index and the extinction coefficient on the energy are presented, for films deposited on c-Si substrates. 
           [0041]      FIG. 3 . Electrical characterization of the transparent TFTs: ( a ) transfer characteristics of devices based on Ta 2 O 5 , SiO 2  and co-sputtered Ta 2 O 5 :SiO 2  dielectrics, obtained with V D =15V (V D =20V for PECVD SiO 2 ); ( b ) Field-effect mobility versus gate voltage extracted with V D =1V (linear regime) for Ta 2 O 5 :SiO 2  and PECVD SiO 2  devices; ( c ) output characteristics of Ta 2 O 5 :SiO 2  based transistors; ( d ) transfer characteristics of devices based on Ta 2 O 5 , Al 2 O 3 , co-sputtered Ta 2 O 5 :Al 2 O 3  and single target Ta 2 O 5 :Al 2 O 3  dielectrics, obtained with V D =15V. 
           [0042]      FIG. 4 . Transfer characteristics obtained with 177-1-15V (V D =20V for PECVD SiO 2 ) at different stages of the constant current stress/recovery process for TFTs based on: ( a ) Ta 2 O 5 ; ( b ) Ta 2 O 5 :SiO 2 ; ( c ) single target Ta 2 O 5 :Al 2 O 3 ; ( d ) PECVD SiO 2  dielectrics. 
           [0043]      FIG. 5 . Variation of gate voltage at I D =1 nA and subthreshold slope during the constant current stress/recovery process for the devices depicted in  FIG. 4 , based on: ( a ) Ta 2 O 5 ; ( b ) Ta 2 O 5 :SiO 2 ; ( c ) single target Ta 2 O 5 :Al 2 O 3 ; ( d ) PECVD SiO 2  dielectrics. 
           [0044]      FIG. 6 . ( a ) Photograph of a glass substrate including various transparent TFTs based on Ta 2 O 5 :SiO 2  dielectric. The figure also shows an image obtained by optical microscopy of a pixel of the active matrix backplane where these devices were integrated ( b ). A photograph of the fabricated AMLCD display employing Ta 2 O 5 :SiO 2  based TFTs is presented in ( c ). 
       
    
    
     TABLE CAPTIONS 
       [0045]    Table 1. Electrical parameters extracted for the devices depicted in  FIG. 3 . Dielectric constants for each insulator and gate leakage current values before and after the stress tests presented in  FIGS. 4 and 5  are also given. 
       DETAILED DESCRIPTION OF THE INVENTION 
     Dielectric&#39;s Characterization 
       [0046]      FIGS. 1   a  and  1   b  show the structural and compositional data obtained for the produced dielectrics. Note that the presented data refers to films intentionally annealed at a higher temperature (300° C.) than the one used on the TFTs (150° C.), in order to investigate the stability of their properties, namely of their structure, when subjected to higher temperatures. Concerning structural properties ( FIG. 1   a ), the SiO 2  and Al 2 O 3  films present an amorphous structure, as expected for these large bandgap materials 29 . For the Ta 2 O 5  based compositions a broad diffraction peak appears close to 2θ=30°, suggesting that some short-range order exists in the thin-films, but crystallization (i.e., long-range ordering) is not achieved. 
         [0047]    XPS and spectroscopic ellipsometry analysis suggest that this short-range order can be affected by composition, namely by the amount of Ta present in the films. According to the XPS data ( FIG. 1   b ), Ta content is decreased from 30.4% in pure Ta 2 O 5  to 16.3% in Ta 2 O 5 :Al 2 O 3  s.t. (s.t. denotes films produced from a single target), while the other multicomponent dielectrics exhibit intermediate percentages. In addition, spectroscopic ellipsometry analysis reveals that the broadening parameter is higher for the multicomponent oxides (1.86-1.96) than for the Ta 2 O 5  (1.73) films, suggesting higher degree of short-range ordering for Ta 2 O 5  than for multicomponent thin films 37 . This supports the hypothesis that Ta 2 O 5  is the responsible element for the enhancement of such short-range ordering and that its mixture with lower-κ materials is effective to increase the disorder and so inhibit crystallization. 
         [0048]    Furthermore, note that these structures, even when considering only the pure Ta 2 O 5  films, show a considerably lower tendency to crystallize than other high-x materials, such as HfO 2  or Y 2 O 3 , which can bring benefits in terms of electrical performance, reliability and integration 36 . Concerning the compositional analysis of the thin-films, the results also show that good correlation between nominal (i.e., target composition) and experimental values is found for the different binary compositions. The largest discrepancy is obtained for the pure Ta 2 O 5  films, with 28.6% Ta/71.4% 0 and 30.4% Ta/69.6% O, for the nominal and experimental values, respectively. 
         [0049]    The spectroscopic ellipsometry data are presented in  FIGS. 2   a - d  and provide good support to the structural and compositional data discussed above. Starting by the refractive index (n) evolution of Ta 2 O 5  and SiO 2  related dielectrics ( FIG. 2   a ), it is evident that SiO 2  is incorporated in the co-sputtered Ta 2 O 5 :SiO 2  film, since its n plot is located between those of pure Ta 2 O 5  and SiO 2  films. In addition, the co-sputtered film&#39;s n plot is closer to the Ta 2 O 5  one, both in absolute values and shape, suggesting a higher concentration of Ta than Si, in agreement with the XPS data depicted in  FIG. 1   b . Valuable information concerning the absorption rise at the onset of conduction band is given by the extinction coefficient (k) plot ( FIG. 2   b ). An increase on the optical bandgap (E opt ) from 4.08 to 4.27 eV is achieved when comparing pure Ta 2 O 5  and co-sputtered Ta 2 O 5 :SiO 2  films, suggesting SiO 2  incorporation in the latter. Note that the E opt  values presented herein are lower than the ones usually reported in the literature for Ta 2 O 5  (around 4.5 eV), even if the analyzed films are close to the ideal stoichiometry, according to XPS data. This is attributed to two factors: first, the simulation model used here takes into account the absorption due to tail-states (located inside the bandgap, close to the bands) to calculate E opt ; second, the sputtering process may induce some damage to the structure, reflected in the broadening of the band-tails. For the Ta 2 O 5 :Al 2 O 3  system similar conclusions can be drawn: both Ta 2 O 5 :Al 2 O 5  films (co-sputtered and s.t.) present n plots located between the Ta 2 O 5  and Al 2 O 3  ones ( FIG. 2   c ). Once again, in agreement to XPS data, the s.t. film n plot suggests higher Al 2 O 3  incorporation, since its n plot is closer to the Al 2 O 3  reference and the onset of absorption starts for higher energy than the co-sputtered film ( FIG. 2   d ). The E opt  determined for the Ta 2 O 5 :Al 2 O 3  films were 4.14 eV (co-sputtered) and 4.35 eV (s.t.). When comparing the co-sputtered Ta 2 O 5 :SiO 2  and Ta 2 O 5 :Al 2 O 3  E opt  values, note that the higher value of the former can be a consequence of two factors: its slightly smaller amount of Ta 2 O 5  and the higher bandgap of SiO 2  when compared with Al 2 O 3 ; the higher damage induced during the co-sputtering process when using Al 2 O 3 , since a higher P rf  was needed for this material to attain reasonable incorporation rates (see “Experimental details” section). A damaged structure and poor compactness might be reasons for the poor device performance obtained with Al 2 O 3  and co-sputtered Ta 2 O 5 :Al 2 O 3 , as will be shown later. 
         [0050]    The κ values of the dielectric films were determined from MIS capacitors and are presented in Table 1. The obtained values are in agreement with the XPS data, showing a trend to increase with the Ta 2 O 5  content in the thin-films. The binary films, specially the Ta 2 O 5  ones, present κ values close to the ones expected for the nominal compositions 29 , meaning that their composition should be close to the theoretical stoichiometry. For the SiO 2  and Al 2 O 3  films higher variations of κ from the nominal values were found, which might be explained by the above mentioned structural damage occurred during sputtering with higher P. As expected, the multicomponent dielectrics present κ values between those of their constituent binary oxides. 
       Influence of Dielectrics on TFTs&#39; Electrical Characteristics 
       [0051]    Transfer characteristics for GIZO TFTs fabricated using the dielectric systems based on Ta 2 O 5 :SiO 2  and Ta 2 O 5 :Al 2 O 3  are presented in  FIGS. 3   a  and  3   d , respectively, being the extracted electrical parameters presented in Table 1. For all the dielectrics, noticeable field-effect modulation is obtained, with on/off ratio always exceeding 10 4 , proving that GIZO is a viable solution for a low-temperature transistor&#39;s semiconductor, even when processed with alternative dielectrics. For devices with sputtered SiO 2 , although the requisites of low off-current and close to 0 V turn-on voltage (V on ) are fulfilled, their S is very high and the maximum source-drain current (T D ) is around two orders of magnitude lower than that of TFTs fabricated with Ta 2 O 5  based dielectrics. This results in devices with the lowest field-effect mobility (μ FE , extracted by the transconductance with V D =1 V), around 1 cm 2  V −1  s −1 . Note that sputtered SiO 2  should allow for better performing GIZO TFTs, namely in terms of S and μ FE , as was already demonstrated by Ofuji et al. 5  The poor characteristics reported herein should be attributed to a non-optimized SiO 2  processing, which results in a degradation of film&#39;s compactness and large semiconductor/dielectric interface trap density. These factors, together with the low κ of SiO 2 , significantly affect the number of charges that can be induced and, from these, the ones that can actually act as free carriers to modulate the TFT channel conductivity. A completely different electrical behavior is verified when Ta 2 O 5  is used as the dielectric layer, with devices exhibiting large μ FE  (36.1 cm 2  V −1  s −1 ) and low S (0.31 V dec −1 ), in parallel with close to 0 V V on . This clearly shows the advantage of using high-κ dielectrics for low temperature TFTs: even if it can be expected that the interface quality of low temperature Ta 2 O 5 /GIZO is far from the one of high temperature thermal or PECVD SiO 2 /GIZO, the extra capacitance provided by the high-x dielectric allows for easier interface trap filling due to the higher number of induced charges 38 . Nevertheless, although the on/off ratio is one order of magnitude higher than that of sputtered SiO 2  TFTs, its value is limited by the high-off current (≈0.5 nA), which arises as a consequence of the low bandgap of Ta 2 O 5  and of its poor band offset in relation to GIZO. 
         [0052]    A remarkable improvement is achieved when co-sputtered Ta 2 O 5 :SiO 2  is used instead of Ta 2 O 5 . While maintaining a high μ FE , almost equal to the one of TFTs with Ta 2 O 5  dielectric, the off-current is decreased by more than one order of magnitude, being comparable to the one obtained for sputtered SiO 2  and concomitant with the decrease verified for the gate leakage current (I G ). I G -V G , plots for Ta 2 O 5  and Ta 2 O 5 :SiO 2  are presented in  FIG. 3   a  to elucidate this result. This allows for an on/off ratio increase of the same order of magnitude, exceeding 3×10 6 . Furthermore, since essentially depends on GIZO&#39;s bulk and interface trap densities, 12  and given that all the devices were produced with the same GIZO process, S variations among different dielectrics can provide a valid indicator about the quality of these dielectrics and their interfaces with GIZO. 
         [0053]    In the case of Ta 2 O 5 :SiO 2 , S is improved over Ta 2 O 5 , suggesting better dielectric and/or interface properties. However, note that the S improvement may also be a consequence of the lower off-current, which permits a more notorious channel conductivity modulation as the first free charges are induced close to the interface, leading to a more abrupt increase of I D  in the subthreshold region. Nevertheless, the fact that the V on  obtained for this multicomponent dielectric is 0 V (i.e., the TFT doesn&#39;t require the application of a V G  to compensate charges or traps prior to the formation of the channel layer) may also reinforce the hypothesis of better interface and/or bulk properties of Ta 2 O 5 :SiO 2  when compared with single Ta 2 O 5  and SiO 2  dielectrics. 
         [0054]    For comparison, the transfer characteristic of a GIZO device produced on a Si/PECVD SiO 2  substrate (dielectric process at 400° C.) is shown in  FIG. 3   a  and the extracted electrical parameters are presented in Table 1. Even if the TFTs employing Ta 2 O 5 :SiO 2  had a maximum processing temperature of 150° C., against 400° C. of the PECVD SiO 2  ones, their electrical performance is comparable. Nevertheless, in spite of having similar S and V o , values, PECVD SiO 2  devices still exhibit lower off-current (due to lower I G ) and higher on/off ratio, exceeding 10 7 . Additionally, PECVD SiO 2  transistors present higher μ FE , despite the higher-κ of Ta 2 O 5 :SiO 2  and its good interface properties with GIZO, as demonstrated above. The reason for the higher μ FE  of PECVD SiO 2  TFTs should be related with the fact that the peak values of μ FE  presented in Table 1 are obtained for high V G , when the conductive channel is located closer to the semiconductor/dielectric interface. Under this situation, the improved interface provided by the PECVD SiO 2  is expected to play an important role: in brief, the extra capacitance of Ta 2 O 5 :SiO 2  helps the devices to present an abrupt increase of I D  in the subthreshold region (hence low S), even if higher density of traps exists for this dielectric. But when the transistor is operated at higher gate bias the interface quality starts to play a more important role, since the free carriers move closer to it. This phenomenon is illustrated in  FIG. 3   b , where the evolution of μ FE  with V G  is presented for devices with Ta 2 O 5 :SiO 2  and PECVD SiO 2  dielectrics. 
         [0055]      FIG. 3   c  shows an example of typical output characteristics obtained for TFTs with Ta 2 O 5 :SiO 2  dielectric. No evidence of current crowding appears for low V D , indicating that the IZO source-drain electrodes have low electrical resistivity, create good ohmic contacts with GIZO and that contact resistance is not significantly limiting device performance 39, 40 . Furthermore, hard saturation is achieved for large V D , meaning that full pinch-off is attained, . . . , the entire thickness of GIZO can be depleted of free carriers close to the drain electrode 41 . 
         [0056]    Transfer characteristics for TFTs based on Ta 2 O 5 :Al 2 O 3  dielectrics are shown in  FIG. 3   d . As mentioned before, high P rf  was required to deposit Al 2 O 3  films with reasonable growth rates, but this processing condition may result in films with poor compactness and high density of pinholes, that may deteriorate the insulating properties of the thin-films. These assumptions are confirmed by the electrical properties of TFTs with Al 2 O 3  as the dielectric layer, which exhibit very high I G  and off-current, as well as a large V on . These values are the highest among all the dielectrics analyzed in this work. Nevertheless, note that even if the S and μ FE  values are worse than the ones obtained with the best performing dielectrics, they are better than the ones achieved with sputtered SiO 2 , due to the higher κ of Al 2 O 3 . 
         [0057]    When Ta 2 O 5  and Al 2 O 3  are co-sputtered, the device properties start to approach those of TFTs with Ta 2 O 5 , namely in terms of V on  and μ FE . However, the high off-current obtained for Al 2 O 3  devices is still verified, due to the above mentioned degradation effects caused by Al 2 O 3  processing. Note also that interface properties of co-sputtered Ta 2 O 5 :Al 2 O 3  are expected to be worse than those of Ta 2 O 5 :SiO 2 , since that even with the extra capacitance of the former (due to its higher content of Ta and substitution of SiO 2  by Al 2 O 3 ), the devices present lower μ FE . A significant difference in TFT characteristics is obtained when Ta 2 O 5 :Al 2 O 3  is processed from a single target. In this case, the film grows at a reasonably fast rate (around 3 nm min −1 ) even using considerably lower than for Al 2 O, diminishing film&#39;s bombardment. The advantages of these transistors are obvious: first, the I G  and off-current are comparable to the ones typically obtained with high temperature SiO 2  (see Table 1). This represents a decrease on these parameters of 2 to 3 orders of magnitude over Ta 2 O 5  based devices. Due to the low off-current and improved interface properties with GIZO, the transistors present high on/off ratio, exceeding 10 7 , low S, approaching 0.2 V dec −1  and high μ FE , similar to the one presented by the co-sputtered Ta 2 O 5 :Al 2 O 3  (and even Ta 2 O 5 :SiO 2 ) devices, even if its κ is significantly reduced from 21.7 to 14.2, essentially due to the lower amount of Ta 2 O 5  (see  FIG. 1   b ). Given this lower (higher) amount of Ta 2 O 5  (Al 2 O 3 ), V on  is shifted toward the Al 2 O 3  TFT plot, but it still presents a low value of 1 V. 
         [0058]    Although not mentioned in the above analysis, electrical measurements were also performed in double sweep mode, to access the hysteresis magnitude obtained with the different dielectrics. The verified hysteresis is always clockwise, consistent with trap filling by accumulated electrons at (or close) the semiconductor/dielectric interface 36 . Concerning hysteresis&#39;s magnitude, it is in most of the cases smaller than 0.5 V, with Ta 2 O 5 :SiO 2  exhibiting the smaller value, around 0.1 V. The larger values are registered for dielectrics containing Al 2 O 3 , being the magnitude higher as its content increased: 0.4 V for Ta 2 O 3 :Al 2 O 3 , 0.5 V for Ta 2 O 5 :Al 2 O 3  s.t. and around 2.5 V for pure Al 2 O 3 . Besides the already mentioned damage induced during Al 2 O 3  film&#39;s growth, it is expected that dielectrics containing this binary compound should intrinsically present some defect states at or close to their surface, which might induce phenomena of charge trapping and instability 42 . Consecutive measurements of transfer characteristics were performed to evaluate early-stage aging of devices 3 . During these measurements all the properties remain unchanged, except V on  that shifts toward more positive values, in agreement with electron trapping at (or close) the semiconductor/dielectric interface. After three consecutive measurements V on  starts stabilizing, being its variation from the first to the third measurements similar to the hysteresis values reported above, since charge trapping should be the dominant mechanism inducing the variations in both measurement processes. 
         [0059]    Besides this early-stage stability evaluation, more demanding stress tests were performed on selected devices, in order to evaluate how they would perform when integrated in electronic circuits. Constant current stress measurements were chosen for this purpose since they can accurately simulate the severe stress conditions that a TFT may be subjected when integrated in an analog circuit environment 43 . 
         [0060]    These tests were carried out during 24 h, at room temperature, keeping the drain and gate terminals shorted in a diode-connected configuration, with the source electrode grounded 44 . This configuration permits automatic V G  adjustment (thus, V on ) to maintain the constant I D . During this period the measurements were shortly interrupted several times to access the device&#39;s transfer characteristics at different stress times. Note that a constant I D =10 μA was used, which can be considered a severe test condition given that only 1 μA is required to display full range of white-gray-color in an active matrix organic light-emitting diode (AMOLED) display 45 . 
         [0061]    Additionally, note that the timescale of these measurements is significantly larger than the one usually found on literature for bias or current stress in GIZO TFTs 6, 45-50 .  FIGS. 4   a - d  present transfer characteristics obtained during I D  stress and recovery, for TFTs employing Ta 2 O 5 , Ta 2 O 5 :SiO 2 , Ta 2 O 5 :Al 2 O 3  s.t. and PECVD SiO 2  dielectrics. Variations of V G  measured at I D =1 nA (ΔV G @1nA) and S (ΔS) for the devices depicted in  FIG. 4  are given in  FIGS. 5   a - d . V G  at 1 nA is presented rather than V on  or threshold voltage (V T ), since the determination of these last parameters can be inaccurate for devices presenting non-abrupt rises of I D  or other non-idealities (such as kinks), which can appear during stress tests. This procedure to estimate “threshold voltage” was already performed previously by different authors 51, 52 . 
         [0062]    Starting by TFTs with Ta 2 O 5 , the evolution of their properties follows the expected trend when charge trapping at the dielectric or at its interface with GIZO is the dominant instability mechanism 50 . In fact, the transfer curves shift in a parallel way, hence without appreciable change of μ FE  or S ( FIGS. 4   a  and  5   a ). Only V G @1nA shifts significantly during stress, about 5 V, but the initial properties are almost recovered 4-5 h after the stress test. After 1 week, the initial device properties are fully recovered. This is consistent with predominant electron trapping rather than ionic drift, since for the latter additional energy would need to be supplied to the devices (for instance, by a subsequent annealing treatment) for ions to diffuse back to their original locations 38 . Still, even after 1 week recovery time, I G  was more than two orders of magnitude higher than in the initial state (see Table 1), suggesting irreversible creation of defects on Ta 2 O 5 , which is facilitated by the low band offset of this material with GIZO. 
         [0063]    The transistors with Ta 2 O 5 :SiO 2  show considerably improved stress resistance over Ta 2 O 5  ones, also without any appreciable changes on μ FE . Now ΔV G @1nA reaches a maximum of −1.75 V after 24 h (only −0.3 V after 10 h), being recovered after 3-4 h. In addition, only a small and recoverable increase of is verified after 24 h stress. However, the Ta 2 O 5 :SiO 2  devices exhibit some increase of the off-current with stress time, affecting the subthreshold region, thus the S value, which increases around 0.55 V. The reason behind this phenomenon is still under study, but should be related with non-idealities also found on output characteristics measured with very small V G , where an abrupt increase of I D  happens for high V D , when the device should supposedly be in the saturation regime. As a positive remark, note that the devices can sustain repeated stress/recovery cycles similar to the ones presented herein without permanent degradation of their electrical properties. 
         [0064]    The most unstable properties are verified for the TFTs based on Ta 2 O 5 :Al 2 O 3  dielectric ( FIGS. 4   c  and  5   c ), in accordance to the higher hysteresis of this dielectric system mentioned before. In spite of no appreciable or permanent degradation is verified for I G  and off-current, the curves shift significantly toward positive V G  (ΔV G @1nA≈12 V), which is accompanied by the appearance of noticeable kinks after the 24 h stress. Given this, it seems that two concurrent factors are playing an important role on the instability of Ta 2 O 5 :Al 2 O; devices: charge trapping at or close the semiconductor/dielectric interface and possible creation of new defect states or ion migration on the Al 2 O 3  based dielectric after some stress time, which can only be removed by a subsequent annealing treatment. This is in fact reinforced by the recover dynamics of these devices, where it can be seen that the initial V G @1nA is almost fully recovered after 1 week (V on  is actually fully recovered), but the kink still persists. After the annealing treatment the initial properties are reestablished. Note that defect creation on oxides is known for a long time 53  and for instance, in the particular case of Al 2 O 3 , is believed to be responsible not only for instability 42  but also for interesting effects such as resistive switching in memories, 54  but the exact dynamics of all these defect creation processes are not clear to date. 
         [0065]    As a reference device, a transistor based on PECVD SiO 2  dielectric was also subjected to constant I D  stress. As expected, due to its high temperature and well established dielectric process fabrication, the variation of the overall electrical parameters is the lowest among all the tested insulators ( FIGS. 4   d  and  5   d ). However, some variations were probable to appear, since it is known that electrical stressing can have several effects on CVD deposited SiO 2 , such as the release of contaminants (hydrogen, for example) or breaking of weak bonds. 55, 56  In fact, like with Ta 2 O 5 :Al 2 O 3 , it is verified that a kink appears after 24 h stress, suggesting some sort of defect creation on SiO 2 , although to a much lower extent than for Ta 2 O 5 :Al 2 O 3 . This also happens simultaneously with charge trapping at the semiconductor/dielectric interface, but in a less pronounced way than for Ta 2 O 5 :Al 2 O 3  (lower ΔV G @1nA), which is expectable given the improved interface properties of PECVD SiO 2 . Again, a defect creation mechanism in the dielectric is plausible for this case, since the initial properties are only recovered after annealing. 
         [0066]      FIG. 6   a  shows a photograph of a 2.5×2.5 cm glass substrate with several TFTs produced with a Ta 2 O 5 :SiO 2  dielectric layer, being notorious the transparency of the devices. To prove that these low temperature devices can indeed be used in electronic circuits, TFTs based on this dielectric were used to fabricate an active matrix backplane to control a 128×128 pixels LCD display. The simple pixel architecture, based on a single TFT per pixel (pixel area 350×350 μm 2 ), is shown in an optical microscope image ( FIG. 6   b ). An area of the final LCD display is presented in  FIG. 6   c , showing that the TFTs based on low temperature dielectrics, even at this early stage, can already be used for real world applications. 
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                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 I G  @ V G  = 15 V [A] 
               
             
          
           
               
                 Dielectric 
                   
                 μ FE   
                 V on   
                 On/Off 
                 S 
                 Before 
                 After 24 h 
               
               
                 material 
                 κ 
                 [cm 2 V −1 s −1 ] 
                 [V] 
                 ratio 
                 [Vdec −1 ] 
                 stress 
                 stress 
               
               
                   
               
             
          
           
               
                 SiO 2   
                 5.0 
                 1.3 
                 −0.25 
                 2.8 × 10 4   
                 1.08 
                 9.7 × 10 −12   
                 — 
               
               
                 Al 2 O 3   
                 8.4 
                 11.1 
                 3.00 
                 2.0 × 10 4   
                 0.58 
                 2.2 × 10 −6    
                 — 
               
               
                 Ta 2 O 5   
                 24.6 
                 36.1 
                 0.50 
                 2.9 × 10 5   
                 0.31 
                 6.2 × 10 −9    
                 5.3 × 10 −7    
               
               
                 Ta 2 O 5 : SiO 2   
                 17.3 
                 35.5 
                 0 
                 3.3 × 10 6   
                 0.24 
                 4.2 × 10 −10   
                 7.2 × 10 −10   
               
               
                 Ta 2 O 5 : Al 2 O 3   
                 21.7 
                 32.1 
                 0.50 
                 3.7 × 10 4   
                 0.63 
                 7.4 × 10 −10   
                 — 
               
               
                 Ta 2 O 5 : Al 2 O 3  s.t. 
                 14.2 
                 31.4 
                 1.00 
                 1.4 × 10 7   
                 0.23 
                 1.7 × 10 −12   
                 6.2 × 10 −12   
               
               
                 PECVD SiO 2   
                 3.9 
                 43.0 
                 0 
                 3.8 × 10 7   
                 0.27 
                 2.8 × 10 −11   
                 2.2 × 10 −11