Abstract:
An integrated test circuit arrangement is provided that contains integrated test structures, at least one integrated heating element, an integrated detection unit, an integrated supply unit, and a control unit. The integrated detection unit detects at least one physical property for each of the test structures. The integrated supply unit supplies each of the test structures with a current or a voltage in switchable fashion independently of one another. The control unit is connected to outputs of the detection unit on an input side and controls the supply unit dependent on the detection results.

Description:
BACKGROUND 
   This application is the national stage application of international application number PCT/DE03/003129, filed on Sep. 19, 2003, which claims the benefit of priority to German Patent Application 102 45 152.4, filed on Sep. 27, 2002, incorporated herein by reference. 
   The invention relates to an integrated test circuit arrangement containing a multiplicity of test structures. 
   SUMMARY 
   Test structures that are subjected to reliability tests, by way of example, are or contains inter alia dielectrics, metallizations or electronic components, in particular integrated components. In order to accelerate the test, it is possible, on the one hand, to use for example higher temperatures, higher currents and/or higher voltages during testing and during normal operation of the arrangement to be tested. On the other hand, it is possible to achieve for example acceptably short test durations by the structures to be tested not being tested until failure, but rather only until a specific limit value is reached. 
   It is an object of the invention to specify, for testing electronic test structures, a circuit arrangement constructed in a simple manner which, in particular, enables testing in an environment that is as simple as possible and with the fewest possible interventions by operating personnel. Moreover, the intention is to specify a test method. 
   The invention is based on the consideration that it is possible to integrate many of the devices required for a reliability test in the test circuit arrangement, so that these devices do not have to be separately procured, maintained and operated. 
   Therefore, the test circuit arrangement according to the invention contains, besides the test structures, at least one heating element and/or at least one detection unit and/or at least one supply unit. The heating element serves for heating the test structures to a temperature required for the reliability test, which temperature is usually considerably greater than the room temperature of the room in which the test is carried out. For each test structure, the detection unit detects a physical quantity established on account of the heating and, if appropriate, on account of additional measures at the test structure, for example the resistance thereof or the leakage current thereof. 
   The use of the test circuit arrangement with an integrated heating element makes it possible to carry out the reliability tests without using a thermal cabinet. It would be necessary to fix the devices with the test structures on circuit boards into the thermal cabinet and load them in each case by a dedicated current or voltage source. Such thermal cabinets would only be required in small numbers, and so they would be very expensive to produce. At test temperatures of, for example, greater than two hundred degrees Celsius or even greater than three hundred degrees Celsius, it would be necessary to satisfy particular requirements made of a stable contact between the device, the circuit board or between the circuit board and the connections. This would result in very expensive circuit boards which, moreover, would only have a very limited service life at the test temperatures mentioned, for example of just a thousand test hours. 
   In one development of the circuit arrangement according to the invention, test structures of a group have the same construction. The same construction is the basis for a reliable comparison result. By way of example, all the test structures of a group comprise:
         interconnects which preferably comprise a metal, and/or which are in each case led into another metallization layer or metallization plane by means of at least one via or contact hole which particularly influences the reliability,   dielectric layers to which a test voltage is applied, or   electronic components, e.g. active electronic components such as transistors or passive electronic components such as capacitors, resistors or coils.       

   In another development, test structures of different groups are integrated into the test circuit arrangement, for example a group with via interconnects, a group with dielectrics and a group with active electronic components. Separate thermal cabinets would be required for the tests of such different groups since different test requirements exist. 
   In a next development with a test circuit arrangement containing different groups of test structures, the test structures of different groups are integrated spatially, i.e. in different planes parallel to the plane of a carrier substrate for the test structures. These measures enable a multiplicity of test structures to be arranged and tested even when the integrated circuit arrangement has a very small area. By way of example, so-called via  1  structures could be arranged below so-called MIM capacitor structures (Metal Insulator Metal). 
   In a next development, a group of test structures contains more than fifty, more than one hundred or even more than a thousand test structures. The statistical meaningfulness of the test results increases considerably as the number of test structures increases. Very many test structures can be integrated into the test circuit arrangement without a high additional outlay in terms of process engineering. The test of these structures likewise requires no or at any rate only comparatively little additional outlay. 
   In a next development of the circuit arrangement according to the invention, the heating element is a resistance heating element which preferably comprises polycrystalline silicon. In order to set the conductivity of the polycrystalline silicon, it is doped. However, other developments also make use of heating elements which comprise a metal. If the heating element is fed with AC current, then it is possible to prevent or considerably reduce degradation processes, e.g. electromigration in particular in heating elements made of metal. 
   In one development, a supply unit is also integrated into the test circuit arrangement. The supply unit contains for example a multiplicity of voltage sources or of current sources. In one configuration, the supply unit supplies the test structures with a current or a voltage independently of one another. An independent supply makes it possible to terminate the test of one test structure despite continuing a test at other identically constructed test structures of the circuit arrangement before the test structure fails. In addition, the material is available after the conclusion of the test for material examinations in a state at which a failure criterion was just fulfilled. 
   In a next development, the heating element has a straight profile or a meandering profile. Heating elements with a triangular function profile, i.e. a zigzag profile, or with a rectangular function profile are also used. 
   In another development, the supply unit contains a plurality of current sources or a plurality of voltage sources. In particular current sources containing a plurality of current mirrors can be integrated in a particularly simple manner. On the basis of the choice of the areas of the transistors contained in a current mirror, currents which are a multiple or a faction of a reference current, for example an integral multiple or a faction of integral values, can be generated in a particularly simple manner. 
   In a next development, the detection unit is connected to each test structure or can be connected to each test structure. The detection unit contains at least one counter unit, which is clocked in accordance with a predetermined clock. A detection unit constructed in this way can detect physical properties at individual test structures and determine the detection instant with the aid of the counter unit. By way of example, the counter unit could be an electronic clock. 
   In another development, the detection unit contains at least one multiplex unit, the inputs of which are electrically connected to a respective test structure. The use of a multiplex unit makes it possible to utilize assemblies of the detection unit successively for a plurality of test structures. Thus, in a next development, the output of the multiplex unit is connected to the input of a comparison unit, the input of which is electrically connected to a reference structure. The reference structure has for example a different construction and/or different dimensions than the test structure. What is achieved by means of this development is that a multiplicity of test structures can be tested with a comparison unit. The error or failure criterion of a test structure is predefined by the reference structure. 
   In a next development, the circuit arrangement contains a control unit, which is connected to the outputs of the detection unit on the input side. The control unit for example outputs detection results and/or drives the supply unit in a manner dependent on the detection results. By way of example, if the failure criterion is generated by a test structure, then the current source or the voltage source for this test structure is switched off. This measure ensures that the test structure can be examined later with the aid of material examining methods, the state when meeting the failure criterion being preserved. 
   In another development, the control unit additionally outputs a datum for ascertaining the detection time and a datum for identifying a specific test structure in a manner dependent on a detection result for this test structure. When the data are in a fixedly predefined order, identifiers for the test structures are not absolutely necessary because the position of a test datum in the order specifies the test structure associated with this test datum. What is thus achieved through the use of the control unit is that the circuit arrangement can output a set of results for all the test structures examined in digital form. As a result, the tests can be carried out with low complexity, cost-effectively and for large numbers. The area of the integrated circuit arrangement that is required for the control unit and for the detection unit is more than compensated for by the saving of a multiplicity of connection pads. 
   In another development, the circuit arrangement contains a substrate, for example made of a semiconductor, in particular made of silicon. The test structures, the heating element, the detection unit and, if appropriate, also the supply unit and/or the control unit are arranged in the substrate or in a manner mechanically fixed to the substrate. To put it another way, the individual parts of the circuit arrangement cannot be released from the substrate without said circuit arrangement being destroyed, in particular not by means of mechanical tools or manually, as would be the case with thermal cabinets. 
   In a next development, the test circuit arrangement is arranged in a plastic housing or in a ceramic housing. On account of the integration of the heating element, plastic housings can still be used even at temperatures of above two hundred degrees Celsius. 
   The invention additionally relates to a test method for testing test structures, in which the following steps are implemented without limitation by the order specified:
         integration of test structures into an integrated circuit arrangement,   integration of at least one detection unit and/or a supply unit into the integrated circuit arrangement,   connection of the test structures to the supply unit,   detection in each case of at least one physical property of the test structures by means of the detection unit.       

   The use of an integrated heating element makes it possible, in one development or in another aspect, for example to implement reliability tests without using a complex test apparatus, for example without using a thermal cabinet. 
   In another development, the heating element is heated to temperatures of greater than two hundred degrees Celsius or greater than three hundred degrees Celsius. Despite these high temperatures, only a low heating power is required because only the volume occupied by the circuit arrangement or even only a part of said volume has to be heated, but not the comparatively large volume of a heating cabinet. 
   In another development, output electronics integrated into the integrated circuit arrangement output a set of result data for all the test structures. The outputting of a set of result data with a predefined data structure gives rise to an interface that permits operation of the test circuit arrangement independently of units for the complete evaluation of the result data. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Exemplary embodiments of the invention are explained below with reference to the accompanying drawings, in which: 
       FIG. 1  shows the division of the area of an integrated test circuit arrangement between different functional units, and 
       FIG. 2  shows a basic illustration of the inter-connection of functional units for the test of a group of test structures. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows an integrated test circuit arrangement  10  arranged on a substrate  11  for example on a square silicon chip having edge lengths L that are smaller than ten millimeters. A connection region  14  containing a plurality of connections  16  to  26  that are electrically insulated from one another is arranged along an edge  12 . The function of the connections  16  to  26  is explained in more detail below with reference to  FIG. 2 . 
   Three test structure groups T 1  to T 3  extend along an edge  30  of the circuit arrangement  10  that adjoins the edge  12 . Two further test structure groups T 4  and T 5  are situated along an edge  32  opposite the edge  30 . The test structure groups T 1  to T 5  occupy approximately identical areas in the exemplary embodiment. The test structure group T 1  contains metallic via interconnects, by way of example. The test structure group T 2  contains dielectrics by way of example. 
   An evaluation circuit  34  and a timer unit  36 , the functions of which is explained in more detail below with reference to  FIG. 2 , are additionally situated between the test structure group T 4  and the connection region  14 . Moreover, in the integrated circuit arrangement  10 , there are additionally a multiplicity of current sources and voltage sources  40  and a plurality of comparators  42  in a central region between the test structure groups T 1  to T 3 , on the one hand, and the test structure groups T 4  and T 5 , on the other hand. The voltage sources are required for the test of the dielectrics, by way of example. In another exemplary embodiment, only current sources  40  or only voltage sources  40  are utilized. 
   In the exemplary embodiment explained, there are no further assemblies situated in the circuit arrangement  10 , in particular no user circuits besides the test circuit. 
   In another exemplary embodiment, by contrast, the circuit arrangement  10  contains components of a user circuit, see dashed line  50 . The user circuit is for example a memory unit  28  having several million memory cells or a processor  27 . In this exemplary embodiment, the reliability tests are carried out on structures that have been fabricated by means of the same processes as identical structures in the user circuit. With such an integrated circuit, ongoing production can be monitored in the manner of random sampling or in its entirety in a very reliable manner. 
     FIG. 2  shows a basic illustration of the combination of functional units of the integrated circuit arrangement  10 . These functional units include a multiplicity of current sources  60  to  68 , which form a part of the current/voltage sources  40 . 
   A heating element  70  lies below test interconnects  80  to  86  having the same construction and below a reference interconnect  88 , which has the same construction as the test interconnects  80  to  86  but is twenty percent longer than the interconnects  80  to  86 . The test interconnects  80  to  86  form the test structures of the test structure group T 1 . There are connecting interconnects  90  to  98  in each case between the current sources  60  to  68  at one end and the test interconnects  80  to  86  and also the reference interconnect  88  at the other end. The connecting interconnect  98  is shown dashed in  FIG. 2  since the current source  68  feeds a current into the reference interconnect  88  during the test only when the reference interconnect  88  is used for a comparison with one of the test interconnects  80  to  86 . 
   At the other end the current sources  60  to  68  are also connected to a ground line M which leads, with the interposition of a resistor, by way of example, to the other ends of the test interconnects  80  to  86  and to the other end of the reference interconnect  88 , see arrow  100 . 
   The current sources  60  to  68  are realized with the aid of current mirrors which duplicate a reference current impressed via the connection  16 . In addition, the current sources  60  to  68 , as explained in more detail below, can be individually switched on and switched off. 
   The heating element  70  is supplied with an AC current, by way of example, via the connections  18  and  20 . A resistance contained in the heating element  70  has a meandering profile. 
   The ends of the interconnects  80  to  86  which are not connected to the current sources  60  to  68  are connected to the inputs of a multiplexer  102 . By way of example, the multiplexer  102  has two hundred input lines  110  to  116 . The output of the multiplexer  102  is connected to the noninverting input of a comparator  42   a  that is associated with the comparators  42 . The inverting input of the comparator  42   a  is connected to that end of the reference interconnect  88  which is not connected to the current source  68 , see arrow  120 . 
   The control inputs of the multiplexer  102  are connected to the outputs of a counting unit  130 . The counting unit  130  counts for example cyclically from one to two hundred, see arrow  132 . 
   The output of the comparator  42   a  leads to the evaluation circuit  34 , see connecting interconnect  140 . The output of the evaluation circuit  34  is connected to the connection  26 . The evaluation circuit  34  accesses the counter value of the counting unit  130  and the timer unit  86 , which is realized by a further counter in the exemplary embodiment, see arrows  150  and  152 . An arrow  160  symbolizes the control function of the evaluation circuit  34  with regard to the current sources  60  to  68 . 
   The timer unit  36  and the counter unit  130  are clocked by a clock T present at the connection  24 . By way of example, the clock T has a clock period of ten milliseconds. 
   In order to test the interconnects  80  to  86  for reliability or in order to determine the life time, for example with regard to electromigration, at the beginning of the test the current sources  60  to  66  are switched on, so that they in each case feed a constant current into the test interconnects  80  to  86 . An AC voltage is applied to the heating element  70  and then a constant temperature of two hundred and fifty degrees Celsius, for example, is generated at the test interconnects  80  to  86  and also at the reference interconnect  88  with the aid of a temperature regulating circuit. With each clock pulse of the clock T, the counter value of the counter unit  130  is incremented by the value one. As a result, a voltage is successively tapped off at the interconnects  80  to  86  and compared with the voltage tapped off at the reference interconnect  88  in the comparator  42   a . In order to restrict the electromigration in the reference interconnect  88 , the constant-current source  68  is switched off again between the individual comparisons. 
   As soon as a voltage signal that signals an identical voltage value at both inputs of the comparator  42   a  or a larger voltage value at the noninverting input of the comparator  42   a  occurs at the output of the comparator  42   a  or on the connecting line  140 , the evaluating circuit  34  reads the counter reading in the counter unit  130 . Said counter reading indicates that test interconnect  80  to  86  at which a voltage is currently being tapped off. The counter reading that has been read is recorded in a memory unit (not illustrated) of the evaluation circuit or gives serves for determining a memory location for storing a result datum. In addition, the evaluation circuit  34  accesses the counter value of the timer circuit  36 . The value is read and stored together with the counter value of the counter unit  130  in the memory unit or at the memory location determined. The counter value of the timer unit  36  indicates the detection instant at which the voltage was tapped off at the relevant interconnect  80  to  86 . As an alternative, the detection instant can be determined with the aid of the counter value of the timer unit  36 . 
   In addition, in the case where the voltages at the input of the comparator  42   a  are identical, the evaluation circuit  34  causes that current source  60  to  66  to be switched off which leads to an interconnect  80  to  86  at which a voltage is currently being tapped off. As a result, a multiple recording of counter readings for a test interconnect  80  to  86  is also avoided. By way of example, the counter reading of the counter unit  130  can again be used for determining the interconnect  80  to  86 . 
   If all the current sources  60  to  66  have been switched off successively or if a predefined value has been reached in the timer unit  36 , then the evaluation unit  34  outputs a set of detection data at the connection  26 . By way of example, a data processing system is connected to the connection  26  and is used to represent the detection data on a display unit. The data can also be stored with the aid of the data processing system for later evaluations. 
   In another exemplary embodiment, just a single counter is used in place of the timer unit  36  and the counter unit  130 . The most significant digits of the counter value are passed to the multiplexer  102  via a data bus, see arrow  132 . In this way, the inputs of the multiplexer  102  that lead to the interconnects  80  to  86  are again cyclically connected to the output of the multiplexer  102 . The evaluation circuit  34  needs to read only one counter value in this case. It is possible to determine from this counter value both the detection time and that of the test interconnect  80  to  86  at which a voltage was tapped off at the detection instant. 
   If, as explained in the exemplary embodiment, the reference interconnect has a length that is twenty percent greater than the length of the test interconnects  80  to  86 , then the nonreactive resistance of the reference interconnect  88  is also twenty percent greater than the nonreactive resistance of an inter-connect  80  to  86 . The failure criterion predefined by the reference interconnect  88  consists in terminating the test of a test interconnect  80  to  86  if the resistance of a test interconnect  80  to  86  has increased by twenty percent. This means in other words that the change dR in the resistance R of an interconnect  80  amounts to twenty percent of the original resistance R at the start of the test, i.e. dR/R=20%. Other values for the failure criterion or else other failure criteria can be predefined in an analogous way.