Abstract:
A circuit including a first stage register that operates in response to a first clock having a period T CYCLE , a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds T CYCLE , and (2) such that the signal delay between the second and third registers is less than T CYCLE  minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within T CYCLE .

Description:
FIELD OF THE INVENTION 
   The present invention relates to a method and structure for optimizing the timing margin in a system that implements sequential logic. More specifically, the present invention relates to a method and structure for using a delayed clock signal to shift the timing between various pipes of sequential logic. 
   RELATED ART 
     FIG. 1  is a block diagram illustrating a circuit  100  that includes input register  101 , output register  102 , and combinational logic  105 . Input register  101  is located in a first timing block, and output register  102  is located in a second (subsequent) timing block. Input register  101  and output register  102  latch the input data values D 1  and D 2 , respectively, in response to rising edges of a common clock signal (CLK). Input register  101  and output register  102  provide the latched data values as output data signals Q 1  and Q 2 , respectively. The delay between the rising edge of the clock signal CLK and the time that the input register  101  provides the output data signal Q 1  is referred to as the clock-to-output delay (or CLK-to-Q delay). Because input and output registers  101  and  102  operate in response to the clock signal CLK, these registers are generally referred to as sequential logic circuits. 
   Input register  101  provides the output data signal Q 1  to combinational logic circuit  105 . Combinational logic circuit  105 , which is typically configured to receive other signals (not shown), includes non-clocked logic, such as inverters, logical AND circuits, logical NAND circuits, logical NOR circuits and/or logical OR circuits. Combinational logic circuit  105  provides the data signal D 2  in response to the provided input signals, including the data signal Q 1  provided by input register  101 . The delay that exists between a transition in the data signal Q 1  and a corresponding transition in the data signal D 2  (i.e., the delay introduced by combinational logic circuit  105 ), is referred to as combinational logic delay. 
   The nature of synchronous sequential logic requires that the register-to-register delay be less than one cycle of the clock signal CLK. Stated another way, the CLK-to-Q delay of the input register  101  plus the combinational logic delay associated with combinational logic  105  must be less than the duration of one cycle of the clock signal CLK (e.g., one clock period, TCLK). As defined herein, the register-to-register delay is the delay existing from the input of input register  101  to the input of output register  102 . 
   If the timing blocks including input register  101  and output register  102  are located far apart, the uncertainty in clock skew and signal RC delay will be relatively large, leaving less margin for the combinational logic delay. Furthermore, if both timing blocks are under simultaneous development, one of the timing blocks has to be finished first in order to obtain accurate timing information, which is then used to optimize the other timing block. In a tight timing situation, several rounds of iteration are typically required before the timing goals are achieved. These iterations will have a major impact on the development schedule. In the extreme case that the output data value Q 2  provided by output register  102  is provided to a register (not shown) in a third timing block, it will take even longer to optimize the logic to meet all of the timing goals. 
   In addition, cross coupling capacitance between adjacent signal lines results in delay variations (delay error) when the associated signals switch together. This cross coupling capacitance can result in a glitch in a signal that has a weak drive and/or is transmitted on a long resistive wire. If the glitch is large enough to be interpreted as an incorrect logic state by downstream logic, a logic error (glitch error) can occur. 
   Designers have attempted to overcome the above-described problems as follows. A register-to-register delay longer than one cycle of the clock signal CLK is typically resolved by logic partitioning. That is, part of the combinational logic circuit  105  is moved either before input register  101 , or after output register  102 , thereby reducing the register-to-register delay between input register  101  and output register  102 . However, moving a part of combinational logic circuit  105  in this manner typically increases the register-to-register delay at the input of input register  101  (upstream) or the output of output register  102  (downstream). The increased register-to-register delay in the upstream or downstream circuitry may cause the register-to-register delay associated with the upstream or downstream circuitry to become longer than one cycle of the clock signal CLK, thereby requiring further partitioning. 
   Moreover, moving part of the combinational logic circuit  105  upstream of input register  101  or downstream of output register  102  may result in the use of many more registers. For example, moving part of the combinational logic of a decoding logic circuit downstream (or moving part of the combinational logic of an encoding circuit upstream) would undesirably require the addition of many additional registers. 
   Delay &amp; glitch error resulting from the cross-coupling capacitance between adjacent signal lines have been avoided by re-routing the signal lines, such that the ‘victim’ signal lines are located away from the ‘aggressor’ signal lines. However, in the case of a massive parallel data path, this technique is not useful because all of the signal lines in the parallel data path are switching together. Other approaches have various disadvanges and limitations. Increasing the driver strength on the ‘victi’ signal lines is not an effective scheme for long signal lines, and causes more problems when the ‘victim’ signal lines become the ‘aggressor’ signal lines when it is their turn to switch. Increasing the signal line width will increase the capacitance, and hence increase the power and path delay. Increasing the signal line spacing will increase the area consumption and possibly the wire length. 
   It would therefore be desirable to have an improved method and structure for controlling register-to-register delay and cross-coupling capacitance between adjacent signal lines. 
   SUMMARY 
   Accordingly, the present invention provides a sequential logic circuit including a first stage register, a second stage register and a third stage register. The first stage register operates in response to a first clock signal having a period T CYCLE . Combinational logic is located between the first stage register and the second stage register. A programmable delay circuit is configured to selectively introduce a programmable delay to the first clock signal, thereby creating a delayed clock signal. The second stage register operates in response to the delayed clock signal. If the signal delay from the first stage register to the second stage register (i.e., the register-to-register delay) exceeds T CYCLE , then the programmable delay circuit is controlled to introduce a positive programmable delay to the first clock signal. The positive programmable delay is selected to exceed the time by which the register-to-register delay exceeds T CYCLE  by at least the set up time of the second register. The positive programmable delay must also be selected such that the signal delay between the second and third registers is less than T CYCLE  minus the programmable delay. Introducing the programmable delay in this manner eliminates the need to move portions of the combinational logic before the first stage registers or after the second stage registers. 
   One or more additional clock signals having fixed delays with respect to the programmable delayed clock signal can also be generated. These fixed delay clock signals are used to operate additional second stage registers, such that the outputs of the various second stage registers transition in a staggered pattern, thereby minimizing signal cross-coupling. 
   The present invention will be more fully understood in view of the following description and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of conventional sequential logic elements located in separate timing blocks, with combinational logic located therebetween. 
       FIG. 2  is a block diagram of a sequential logic circuit in accordance with one embodiment of the present invention. 
       FIG. 3  is a waveform diagram illustrating the timing of a control path within the sequential logic circuit of  FIG. 2  in accordance with one embodiment of the present invention. 
       FIG. 4  is a waveform diagram illustrating the timing of a data path within the sequential logic circuit of  FIG. 2  in accordance with one embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
     FIG. 2  is a block diagram of a sequential logic circuit  200  in accordance with one embodiment of the present invention. Timing circuit  200  includes first stage registers  201 - 203 , second stage registers  211 - 213 , third stage register  221 , combinational logic circuits  231 - 233 , arithmetic logic unit (ALU)  235 , programmable clock delay circuit  241 , and fixed clock delay circuits  242  and  243 . Sequential logic circuit includes a control path (which includes register  201 , combinational logic  231  and register  211 ), a first data path (which includes register  202 , combinational logic  232  and register  212 ), and a second data path (which includes register  203 , combinational logic  233  and register  213 ). A first timing block (pipe  01 ) is defined from the inputs of registers  201 - 203  to the inputs of registers  211 - 213 . A second timing block (pipe  02 ) is defined from the inputs of registers  211 - 213  to the input of register  221 . 
   Control register  201  and programmable delay circuit  241  are coupled to receive a first clock signal K 1 . Data registers  202  and  203  are coupled to receive a second clock signal K 2 . In the described embodiment, the second clock signal K 2  has the same frequency as the first clock signal K 1 , but is slightly delayed with respect to the first clock signal K 1  because of physical clock tree skew. In other embodiments, the first and second clock signals K 1  and K 2  are identical clock signals. 
   A command value C 1  is latched into command register  201  in response to an edge (e.g., a rising edge) of the first clock signal K 1 . In response, command register  201  provides an output command value C 2  to combinational logic  231 . Combinational logic  231  then provides a command value C 3  to the input of register  211 . Register  211  latches the command value C 3  into command register  211  in response to an edge (e.g., a rising edge) of clock signal Kθ. 
   Clock signal Kθ is provided by programmable delay circuit  241  in response to the first clock signal K 1 . If the clock-to-output delay (D 201 ) of register  201  plus the combinational logic delay (D 231 ) of combinational logic  231  (i.e., the register-to- register delay from register  201  to register  211 ) is less than or equal to the period (T K1 ) of the first clock signal K 1 , then programmable delay circuit  241  is disabled, such that no significant delay is introduced to the first clock signal K 1  (i.e., K 1 =Kθ). 
   However, if the register-to-register delay from register  201  to register  211  is greater than the period T K1  of the first clock signal K 1 , then programmable delay circuit  241  can be enabled, such that a positive programmable delay θ is introduced to the first clock signal K 1 . The programmable delay θ is selected such that the command value C 3  is valid before the corresponding edge of the delayed first clock signal Kθ activates command register  211 . That is, the programmable delay θ is selected such that the period T K1  of the first clock signal K 1  plus the programmable delay θ is greater than or equal to the register-to-register delay from register  201  to register  211 . 
   Introducing a positive programmable delay θ to the first clock signal K 1  changes the timing requirements for the next timing block (i.e., pipe  02 ). More specifically, the allowable register-to-register delay from register  211  to register  221  must be less than the period T K1  of the first clock signal K 1 , minus the programmable delay θ. Note that if this timing problem were solved in a conventional manner, by moving part of combinational logic  231  after register  211 , the delay path of the next timing block (pipe  02 ) would be increased. Hence, the programmable delay θ introduced to the first clock signal K 1  does not really tighten the timing requirement for the next timing block (pipe  02 ) when compared with the conventional alternative. 
     FIG. 3  is a waveform diagram illustrating the timing of the control path in accordance with one embodiment of the present invention. At time T 0 , the first clock signal transitions to a logic high state, thereby causing command register  201  to latch the command value C 1 . After clock-to-out delay D 201 , command register  201  provides a valid output command value C 2 . Combinational logic  231  provides a valid command value C 3  after the combinational logic delay D 231 . In the example of  FIG. 3 , the clock-to-out delay D 201  plus the combinational logic delay D 231  is greater than the period T K1  of the first clock signal K 1 . Thus, command value C 3  does not become valid until after the rising edge of the first clock signal K 1  occurs at time T 1 . Consequently, programmable delay circuit  241  is controlled to introduce programmable delay θ, thereby creating delayed clock signal Kθ. In one embodiment, programmable delay θ is selected in response to the contents of a register. 
   As illustrated in  FIG. 3 , the programmable delay θ is selected such that the rising edge of clock signal Kθ occurs after control value C 3  has become valid. The rising edge of clock signal Kθ (after time T 1 ) causes command register  211  to latch the command value C 3 . After clock-to-out delay D 211  (associated with command register  211 ), command register  211  provides a valid output command value C 4 . Note that ALU  235  must provide the result R 1  associated with command value C 4  prior to time T 2  in order to meet the timing requirements. The falling edge of clock signal K 3  (after time T 1 ) causes output register  221  to latch the result R 1 . After clock-to-out delay D 221  (associated with output register  221 ), output register  221  provides a valid output result R 2 . In this manner, delayed clock signal Kθ effectively distributes the timing requirements of the control path over the first and second timing blocks (pipe  01  and pipe  02 ). 
   If the command value C 1  is received from another logic block and the command value C 4  is transmitted to yet another logic block, the input and output timing specifications will require more margin for clock skew and uncertainty (based on the large delay introduced by long input and output signal lines). In one embodiment, the programmable delay θ is at least partially metal layer programmable to allow for last minute adjustments of the programmable delay θ, when timing information associated with the other logic blocks becomes available. 
   Turning now to the first and second data paths, the first and second data values DA 1  and DB 1  are latched into data registers  202  and  203 , respectively, in response to an edge (e.g., a rising edge) of the second clock signal K 2 . In response, data registers  202  and  203  provide latched data values DA 2  and DB 2 , respectively, to combinational logic circuits  232  and  233 , respectively. In response, combinational logic circuits  232  and  233  provide data values DA 3  and DB 3 , respectively, to the inputs of data registers  212  and  213 , respectively. Data registers  212  and  213  latch the data values DA 3  and DB 3 , respectively, in response to edges (e.g., rising edges) of delayed clock signals K 2 δ and Kδ, respectively. 
   Delayed clock signals K 2 δ and Kδ are provided by fixed delay circuits  242  and  243 , respectively, in response to the clock signal Kθ. Fixed delay circuits  242  and  243  introduce delays of 2δ and δ, respectively, to clock signal Kθ. That is, the delay introduced by delay circuit  242  is twice the delay introduced by delay circuit  243 . 
   Within the second timing block (pipe  02 ), registers  211 ,  212  and  213  provide a latched command value C 4 , a latched operand OP_A and a latched operand OP_B, respectively, in response to the clock signals Kθ, K 2 δ and Kδ, respectively. Command value C 4  and operands OP_A and OP_B are provided to ALU  235 . In response, ALU  235  generates a result R 1 , which is provided to an input of register  221 . Register  221  operates in response to a third clock signal K 3 . In the described embodiment, the third clock signal K 3  is the inverse of the first clock signal K 1 . 
   In the past, if command value C 4  and operands OP_A and OP_B were required to travel a long distance to the same destination, cross-coupling of these signals would have been unavoidable. However, in accordance with one aspect of the present invention, operand OP_B has an extra delay of δ with respect to command value C 4 , and operand OP_A has an extra delay of 2δ with respect to command value C 4  (and an extra delay of δ with respect to operand OP_B). The delay δ is selected such that command value C 4  is fully transitioned to the next state before operand OP_B starts to transition (e.g., command value C 4  reaches 90% of the Vcc supply voltage on a zero-to-one transition when (or before) operand OP_B reaches 90% of V cc  on a one-to-zero transition). Selecting the delay δ in this manner also ensures that operand OP_B is fully transitioned to the next state before operand OP_A starts to transition. In this manner, the registers of the control path, the first data path and the second data path are effectively divided into three groups, each operating in response to a slightly different clock signal. 
   By dividing the registers  211 - 213  into two or more groups (three groups in the present embodiment), and interleaving the output signals from the different register groups, signal cross-coupling can be avoided. Note that the register-to-register delay from register  212  to register  221  must be less than the period T K1  of the first clock signal K 1  by delay  2 δ. Similarly, the register-to-register delay from register  213  to register  221  must be less than the period T K1  of the first clock signal K 1  by delay δ. 
   The division of the registers  211 - 213  into different groups makes clock gating more flexible and more efficient. In the embodiment of  FIG. 2 , combinational logic  231  provides a delay enable signal EN 1 #, which can be used to enable and disable the delayed clock signals K 2 δ and Kδ on a per cycle basis. 
     FIG. 4  is a waveform diagram illustrating the timing of the first and second data paths in accordance with one embodiment of the present invention.  FIG. 4  illustrates the same time period as  FIG. 3 . At time T 0 , the first clock signal K 1  transitions to a logic high state. After a clock skew delay, the second clock signal K 2  transitions to a logic high state, thereby causing data registers  202  and  203  to latch the input data values DA 1  and DB 1 , respectively. After respective clock-to-out delays D 202  and D 203 , data registers  202  and  203  provide valid output data values DA 2  and DB 2 , respectively. Combinational logic circuits  232  and  233  provide valid data values DA 3  and DB 3  after combinational logic delays D 232  and D 233 . 
   As illustrated in  FIG. 4 , fixed delay circuits  242  and  243  introduce delay  2 δ and delay δ, respectively, to clock signal Kθ, thereby creating clock signals K 2 δ and Kδ, respectively. The rising edge of clock signal Kδ occurs (a delay δ) after the rising edge of clock signal Kθ. The rising edge of the clock signal Kδ causes data register  212  to latch the input data value DA 3 . After an associated clock-to-out delay D 212 , data register  212  provides valid operand value OP_B. 
   The rising edge of clock signal K 2 δ occurs (a delay  2 δ) after the rising edge of clock signal Kθ. The rising edge of the clock signal K 2 δ causes data register  213  to latch the input data value DB 3 . After an associated clock-to-out delay D 213 , data register  213  provides valid operand value OP_A. Again, note that ALU  235  must provide result R 1  in response to command value C 4  and operand values OP_A and OP_B prior to time T 2 . 
   Benefits of the present invention include the following. In general, delaying clock signal Kθ (and thereby clock signals K 2 δ and Kδ) has the benefit of adjusting/controlling the timing of multiple registers. That is, adjusting clock signal Kθ replaces the need of adjusting the timing of all of the data and control signals going through the registers. 
   In addition, the present invention eliminates the need to move portions of the combinational logic  231 - 233  to the left of registers  201 - 203 , or to the right of registers  211 - 213  ( FIG. 2 ), because the present invention can fix the timing boundary. This is particularly beneficial for custom implementation of sequential logic, as the design cycle for this type of implementation is much longer than place and route implementation. Moreover, the programmable delay θ can be register programmable, which enables silicon debugging/prototyping without requiring expensive silicon re-spin. In addition, in high speed applications, where the process is pushed to the limit, programmable delay θ can be fuse programmable, thereby achieving highest yield to fastest speed grade. 
   The present invention also provides improved adaptation to highly uncertain logic delay &amp; clock skew. The burden of such uncertainty is shared by more than one pipe of logic. By avoiding pushing the timing limit on only one pipe of logic, adjusting the programmable delay θ can achieve a better yield to fastest speed grade. In a case where only one register is involved from the input of a timing block to the output of the timing block, the programmable delay θ can shift the margin from the input interface to the output interface &amp; vice versa. 
   In addition, dividing the registers within a timing block into groups with small delays between the groups has various benefits. For example, the signals in the critical path that needs fastest clock to output (e.g., the command path in  FIG. 2 ) are not slowed down by cross coupling as long as the neighboring signals are in another register group. With more than one register group, an output signal can always be located adjacent to two neighboring signals that are not switching at the same time as the output signal. Hence, delay error can be avoided. With more than two register groups, an output signal can always be located adjacent to two neighboring signals that are not switching at the same time as each other, or at the same time as the output signal. Hence, the worst case glitch from a neighboring signal is reduced by 50 percent. In other words, signal lines can run in parallel for a length two times as long as a conventional design. 
   Dividing the registers into separately clocked groups also enables a fine grain clock gating scheme, which saves more power. Moreover, staggering the register switching reduces current surge/spike, because the switching is spread out over time. This in turn will reduce the power surge and IR drop in the power grid. 
   Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. For example, although the second timing block (pipe  02 ) has been illustrated as a generic ALU  235  that receives command C 4  and operands OP_A and OP_B as inputs, it is understood that the logic in the first timing block (pipe  01 ) can be repeated in the second timing block in other embodiments. That is, the logic of the first timing block (pipe  01 ) can be invoked in any timing block, as needed. Thus, the invention is limited only by the following claims.