Abstract:
Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority from Japanese Patent Application No. 2003-146319, which was filed on May 23, 2003, in the Japanese Patent Office, the disclosure of which is incorporated herein in its entirety by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a memory testing apparatus and testing method in which the test results corresponding to the performance of a memory under test are stored in a failure memory and subsequently counting the failure bits stored in the failure memory, and more particularly, to a memory testing apparatus and method, which can reduce the time required for functional testing of memory devices.  
         [0004]     2. Description of the Related Art  
         [0005]     Memory testing apparatuses perform tests for various operational parameters of a memory, such as a power supply voltage margin and access time, and count defective bits of the memory. A conventional memory testing apparatus, such as the one disclosed in Japanese Laid-Open Patent Publication No. hei 9-33615, determines whether a memory is eligible to undergo subsequent wafer processing operations based on the number of defective bits detected in the memory. If the number of defective bits detected in the memory exceeds a predetermined number, the memory is determined to be irreparable and is then excluded from subsequent wafer processing operations. If, on the other hand, the memory is determined to be repairable, the memory will be subjected to additional processing during which an attempt to repair the memory will be included. A conventional memory testing apparatus will now be described more fully with reference to  FIG. 1 .  
         [0006]      FIG. 1  is a block diagram of according to one example of a conventional memory testing apparatus. As illustrated in  FIG. 1 , a test head  1  is electrically connected to a memory  10  to be tested (hereinafter, referred to as a device under test (DUT)) for transmitting/receiving signals to/from the DUT  10 . The test head  1  includes a format controller FC, a driver D, a comparator C, and a digital comparator DC. The format controller FC reshapes a pattern input thereto and outputs the reshaped pattern to the driver D. The driver D receives the reshaped pattern from the format controller FC and adjusts or sets the desired voltage level, and outputs the adjusted pattern to the DUT  10 . The comparator C receives the output from the DUT  10  and checks the voltage level of the output signal. The digital comparator DC compares outputs received by the comparator C with expected pattern data received from the pattern generator to determine whether the DUT  10  fails or passes the memory test.  
         [0007]     A pattern generator  2  outputs patterns (i.e., an input pattern and an expected output pattern) to the test head  1  and simultaneously generates addresses. An address pointer  3  may also be used for generating addresses. A multiplexer  4  selects between the addresses generated by the pattern generator  2  or the addresses generated by the address pointer  3 . A failure memory  5  stores failure data obtained from the test head  1  corresponding to the addresses received from the multiplexer  4 . A failure bit counter  6  counts the failure bits of the failure memory  5 . A controller  7  controls the address pointer  3 , the multiplexer  4 , the failure memory  5 , and the failure bit counter  6 . A central processing unit (CPU)  8  controls the pattern generator  2  and the controller  7 .  
         [0008]     The operation of the conventional testing apparatus generally according to  FIG. 1  will now be described further with reference to the operational flowchart for such a conventional testing apparatus provided in  FIG. 2 . As illustrated in  FIG. 2 , the CPU  8  sets the level of a power supply voltage to be supplied to the DUT  10  to a predetermined level, such as 3.3 V, in step S 11 . In response to this voltage setting, the test head  1  will apply the predetermined voltage to the power port(s) of the DUT  10  using a direct current (DC) generator (not shown).  
         [0009]     The CPU  8  will then instruct the pattern generator  2  to initiate a function test using a signal A′ in step S 12 . The CPU  8  also informs the controller  7  that the pattern generator  2  has been instructed to initiate the function test. In response, the controller  7  will set the multiplexer  4  to select the addresses generated by the pattern generator  2  and also command the failure memory  5  to perform a write operation.  
         [0010]     The pattern generator  2  outputs a background pattern (sometimes also referred to as a rear or initialization pattern) that will write a data value of “1” or “0” into each cell of the memory in order to initialize the individual memory cells with a predetermined state. The format controller FC receives the background pattern from the pattern generator  2 , reshapes the background pattern, outputs the reshaped background pattern to the DUT  10  via a driver D, and performs a write operation in step S 13 .  
         [0011]     Once the memory cells have been initialized, during step S 14  the pattern generator  2  will generate and output a read/write test pattern and corresponding memory addresses to the format controller FC. The format controller FC will reshape the addresses and the test pattern and output the reshaped addresses and the reshaped input pattern to the DUT  10  via the driver D. The digital comparator DC will receive the resulting output pattern from the DUT  10  via the comparator C and compare the output pattern from the DUT  10  with the expected output pattern received from the pattern generator  2 . Based on this comparison, the digital comparator DC will determine whether the DUT  10  has passed or failed the function test and will output failure data as the determination result. The failure data output from the digital comparator DC will be associated within the failure memory  5  to the corresponding address data received from the multiplexer  4 . The failure memory  5  typically maintains a once-failed state whereby a memory cell address that has failed to respond correctly to any test pattern will be recorded as a “failed” cell even if it passes other test patterns. In step S 15 , the pattern generator  2  notifies the CPU  8  that the function test has been completed by using a signal B′.  
         [0012]     In step S 16 , the CPU  8  commands the controller  7  to count the failure bits of the DUT  10 . The controller  7  sets the multiplexer  4  to output the address information from the address pointer  3  and commands the failure memory  5  to read the failure data. In step S 17 , the address pointer  3  sequentially outputs the address of each cell of the failure memory  5  using the multiplexer  4 , and the failure bit counter  6  counts the number of failure bits of the failure memory  5 . In step S 18 , the controller  7  notifies the CPU  8  that the counting of the failure bits of the failure memory  5  has been completed in response to an ending signal output from the address pointer  3 .  
         [0013]     Thereafter, the CPU  8  determines if each of the power supply voltage tests has been completed. If additional supply voltage tests are required, the operation returns to step S 11  where the CPU  8  resets the level of the power supply voltage to the next scheduled voltage that will be supplied to the DUT  10  by test head  1 . The remaining scheduled voltages may be higher, such as 3.6 V, or lower, such as 3.0 V, than the initial power supply voltage as operational margin tests to aid in the detection of “soft” cell errors. Once the power supply voltage has been reset, steps S 12 -S 18  are performed to complete another funtional test cycle on the DUT  10 . This sequence of resetting the power supply voltage and rerunning the functional test steps will continue until the CPU  8  determines that functional tests have been run at each of the scheduled voltages and the testing of the DUT  10  is complete.  
         [0014]     For example, using the conventional method and apparatus to conduct a series of four functional tests, AC 1 -AC 4  and collect the corresponding failure bit counts FB 1 -FB 4  will involve an operation sequence of:
 
AC 1 →FB 1 →AC 2 →FB 2 →AC 3 →FB 3 →AC 4 →FB 4 .
 
 with each of the operations requiring a certain amount of time to complete. As a result, the cumulative time required to complete the full testing and failure bit counting sequence may be represented by:
 
 T   AC1   +T   FB1   +T   AC2   +T   FB2   +T   AC3   +T   FB3   +T   AC4   +T   FB4 =Total Test Time.
 
         [0016]     As described above, in the conventional prior art, the various operational margin tests and the process of counting the defective bits of a memory device under test are performed sequentially. However, as the storage capacity of the memory devices being tested increases, the time and expense required to perform such operational margin tests on the predetermined memory and count the detected failures also increases.  
       SUMMARY OF THE INVENTION  
       [0017]     The present invention provides an exemplary memory testing apparatus and method for operating such an apparatus, that can reduce the time required to test a memory from that required using the conventional memory testing apparatus and methods.  
         [0018]     According to an exemplary embodiment of the present invention, there is provided a memory testing apparatus arranged and configured to store the test results for a memory under test in a failure memory and count the failure bits of the failure memory. The exemplary memory testing apparatus includes a pattern generator that can generate background patterns, test patterns, and addresses and will output the test patterns to the memory and simultaneously generates addresses in response to a count ending signal; an address pointer that can generate addresses; a selector, arranged and configured to select either the addresses generated by the pattern generator or the addresses generated by the address pointer and output the selected addresses to the failure memory; and a controller that controls the operation of the selector and the counting of the failure bits of the failure memory, outputs the count ending signal to the pattern generator after counting the failure bits, and simultaneously controls the selector to select the addresses generated by the pattern generator when the pattern generator generates the background pattern.  
         [0019]     The pattern generator may include a background pattern commanding unit, which initiates the output of the background pattern to the memory, and a test pattern commanding unit, which initiates outputting the test patterns to the memory when it receives the count ending signal from the controller.  
         [0020]     The controller may include a count commanding unit, which commands the failure bits of the failure memory to be counted when the pattern generator generates the background pattern, and outputs the count ending signal to the pattern generator when the counting of the failure bits of the failure memory has been completed.  
         [0021]     The present invention also provides an exemplary memory testing method that stores the test results corresponding to a memory under test in a failure memory and counts the failure bits that have been accumulated in the failure memory. The exemplary memory testing method includes the steps of enabling a pattern generator to generate a background pattern and output the background pattern to the memory; enabling a selector to select addresses generated by an address pointer and counting failure bits of the failure memory when the pattern generator generates the background pattern; and enabling the selector to select addresses generated by the pattern generator and allowing the pattern generator to generate test patterns and output to the memory so that the memory can be tested. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0023]      FIG. 1  is a block diagram of a conventional memory testing apparatus;  
         [0024]      FIG. 2  is a flowchart generally corresponding to a conventional memory testing method;  
         [0025]      FIG. 3  is a block diagram of a memory testing apparatus according to an embodiment of the present invention;  
         [0026]      FIG. 4  is a flowchart of the operation of the memory testing apparatus generally corresponding to  FIG. 3 ; and  
         [0027]      FIG. 5  is a block diagram of a memory testing apparatus according to another embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS  
       [0028]     The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.  FIG. 3  is a block diagram of a memory testing apparatus according to an exemplary embodiment of the present invention. In  FIGS. 1, 3  and  5 , corresponding reference numerals indicate corresponding, if not identical, elements whose descriptions will not be repeated for the sake of brevity.  
         [0029]     Referring to  FIG. 3 , a pattern generator  20 , which generally corresponds to the pattern generator  2  of  FIG. 1 , generates a background pattern to be applied to a memory (hereinafter referred to as a device under test (DUT))  10  and outputs a count starting signal C′. In addition, the pattern generator  20  generates test patterns, i.e., read/write test patterns, and addresses and outputs the test patterns to the DUT  10  when it receives a count ending signal D′. The pattern generator  20  includes a background pattern commanding unit  21  and a test pattern commanding unit  22 . The background pattern commanding unit  21  initiates the output of the background pattern and simultaneously outputs the count starting signal C′. The test pattern commanding unit  22  initiates the output of the test patterns to the DUT  10  in response to the count ending signal D′.  
         [0030]     A CPU  80 , which generally corresponds to the CPU  8  of  FIG. 1 , includes a count commanding unit  81 . The CPU  80  commands a controller  7  to count the failure bits of a failure memory  5  when the background pattern is generated, and outputs the count ending signal D′ to the pattern generator  20  when the counting of the defective bits of the DUT  10  (as recorded in the failure memory) has been completed. More specifically, when the count commanding unit  81  receives the count starting signal C′ from the pattern generator  20 , it commands the controller  7  to count the defective bits of the DUT  10 . When the controller  7  notifies the count commanding unit  81  that the counting of the defective bits of the DUT  10  is complete, the count commanding unit  81  outputs the count ending signal D′ to the pattern generator  20 .  
         [0031]     The operation of the memory testing apparatus of  FIG. 3  will now be described in greater detail with reference to  FIG. 4 .  FIG. 4  is a flowchart of an exemplary mode of operation of a memory testing apparatus generally corresponding to  FIG. 3 . Here, it is assumed that the DUT  10  is a dynamic random access memory (DRAM).  
         [0032]     In a first round of a memory testing method, the CPU  80  sets the level of a power supply voltage to be supplied to the DUT  10  to an initial voltage, such as 3.3 V, in step S 21  so that the test head  1  will apply the predetermined voltage to the power port(s) of the DUT  10  using a DC voltage generator (not shown).  
         [0033]     In step S 22 , the CPU  80  commands the pattern generator  20  to initiate a function test through the output of signal A′.  
         [0034]     In step S 31 , the background pattern commanding unit  21  initiates the output of the background pattern and outputs the count starting signal C′ to the CPU  80 . A format controller FC receives the background pattern from the pattern generator  20 , reshapes the received background pattern, and outputs the reshaped background pattern to the DUT  10  via a driver D.  
         [0035]     At this time, the count commanding unit  81  of the CPU  80  receives the count starting signal C′ and commands the controller  7  to count the defective bits of the DUT  10  in step S 23 . Then, the controller  7  controls a multiplexer  4  to select the address pointer  3  as the source of the addresses transmitted to the failure memory  5  and issues a read command to the failure memory. The address pointer  3  sequentially outputs the address of each cell of the failure memory  5  through the multiplexer  4  and the failure bit counter  6  counts the failure bits present in the failure memory  5 . The controller  7  receives an ending signal from the address pointer  3  and notifies the CPU  80  that the counting of the failure bits of the failure memory  5  has been completed. The controller  7  then controls the multiplexer  4  to select the addresses generated by the pattern generator  20  as the source of the addresses transmitted to the failure memory  5  and issues a write command to the failure memory.  
         [0036]     Until the count commanding unit  81  of the CPU  80  receives the ending signal via the controller  7 , it stays in a standby mode in step S 24 . When the counting of the failure bits of the failure memory  5  has been completed, the count commanding unit  81  outputs the count ending signal D′ to the pattern generator  20  in step S 25 .  
         [0037]     In steps S 32  and S 33 , the test pattern commanding unit  22  of the pattern generator  20  generates a refresh pattern and outputs the refresh pattern to the DUT  10  until it receives the count ending signal D′ from the CPU  80 . Here, the refresh pattern is a pattern for refreshing the DUT  10 , i.e., a DRAM. The format controller FC receives the refresh pattern from the pattern generator  20 , reshapes the refresh pattern, and outputs the reshaped refresh pattern to the DUT  10  via the driver D to refresh the DUT  10 .  
         [0038]     When the test pattern commanding unit  22  receives the count ending signal D′, it outputs the read/write test pattern and addresses in step S 34 . The format controller FC reshapes the addresses and the test pattern received from the pattern generator  20 , which is one of the read/write test patterns, and outputs the reshaped addresses and the reshaped input pattern to the DUT  10  via the driver D.  
         [0039]     The output of the DUT  10  in response to the input received from driver D is input to a digital controller DC via a comparator C. The digital comparator DC generates and outputs failure data by comparing the detected output of the DUT  10  with an expected output pattern corresponding to the read/write test pattern received from the pattern generator  20 . The failure data reflecting the performance of the DUT  10  is written on the failure memory  5  at the addresses selected by the multiplexer  4  with the failure memory  5  maintaining a once-failed state. In step S 26 , the pattern generator  20  notifies the CPU  80  that the funtional test can be completed with signal B′, and the CPU  80  completes the function test.  
         [0040]     Thereafter, in subsequent rounds of the exemplary memory testing method, the CPU  80  resets the level of the power supply voltage to the next predetermined voltage value, such as 3.6 V or 3.0 V, in step S 21  and initiate another round of functional testing of the DUT  10  until each of the predetermined power supply voltage levels and/or other operational margin testing inputs have been completed. Other operational margin testing may include variations in, for example, the GND or low voltage levels, the input voltage levels and the output voltage levels.  
         [0041]     As described above, in each subsequent round of the memory testing method, while the pattern generator  20  generates the background pattern for initializing the memory device, the failure bits that were detected and accumulated in the failure memory  5  during the previous round of funtional testing, are counted, thereby considerably reducing the time taken to test a given DUT  10 .  
         [0042]     For example, in contrast to the conventional testing sequence described above, utilizing an apparatus and a method according to an exemplary embodiment of the present invention to conduct the same series of four funtional tests, AC 1 -AC 4  and collect the corresponding failure bit counts FB 1 -FB 4  will involve an operation sequence of:
 
 AC   1 →( AC   2   +FB   1 )→( AC   3 + FB   2 )→( AC   4 + FB   3 )→ FB   4 .
 
 wherein the failure bit counting operation for the preceding funtional test is conducted during the “write” portion of the next functional test. Indeed, each of the parenthetical expressions could be expanded to reflect this sequence along the lines of:
 
((AC NW +FB n-1 )+AC nR )
 
 in which the W and R subscripts indicate the “write” and “read” operations respectively. As suggested by this expression, the addresses applied to the DUT and the Failure Memory are identical during the “read” operation but may be different during the “write” operation, thereby allowing the Failure Memory to be accessed for the purpose of counting the failure bits as the next test pattern is written into the DUT. 
 
         [0045]     By utilizing the at least partial simultaneous funtional testing and failure bit counting, reduces the cumulative time required to complete the full testing and failure bit counting sequence may be represented by:
 
 T   AC1   +T   AC2   +T   AC3   +T   AC4   +T   FB4 =Total Test Time.
 
 As a result, testing operations conducted according to the exemplary embodiments of the present invention can reduce the total test time by:
 
 T   FB1   +T   FB2   +T   FB3 =Total Test Time.
 
 and thereby improve productivity without reducing the thoroughness of the applied testing or allow for additional testing to increase the thoroughness of the funtional testing without increasing the required test time. The advantages of utilizing a testing protocol according to the present invention will tend to be even greater as the size and complexity of the DUTs continue to increase. 
 
         [0048]      FIG. 5  is a block diagram of a memory testing apparatus according to another exemplary embodiment of the present invention. As illustrated in  FIG. 5 , a background pattern commanding unit  23 , which generally corresponds to the background pattern commanding unit  21  of  FIG. 3 , is installed in a pattern generator  20  and initiates outputting a background pattern to a DUT  10 . A count commanding unit  82 , which generally corresponds to the count commanding unit  81  of  FIG. 3 , is installed in a CPU  80  and commands a controller  7  to count the failure bits maintained in the failure memory  5 , while commanding the pattern generator  20  to perform a functional memory test. In addition, the CPU  80  outputs a count ending signal D′ to the pattern generator  20  when the controller  7  notifies the CPU  80  that the counting of the failure bits in the failure memory  5  has been completed.  
         [0049]     The operation of the memory testing apparatus of  FIG. 5  is very similar to that of the memory testing apparatus of  FIG. 3 . However, the background pattern commanding unit  23 , unlike the background pattern commanding unit  21 , does not output the count starting signal C′. In addition, the count commanding unit  82 , unlike the count commanding unit  81 , does not receive the count starting signal C′ from the pattern generator  20  and controls the controller  7  to count the failure bits of the failure memory  5 .  
         [0050]     The count commanding unit  82  commands the controller  7  to count the failure bits of the failure memory  5  without the help of the count starting signal C′ output from the pattern generator  20  of  FIG. 3 . Therefore, the memory testing apparatus corresponding to  FIG. 5  may be able to reduce the testing time required for a given DUT  10  to a level below that required for a memory testing apparatus corresponding to  FIG. 3 .  
         [0051]     As will be appreciated by those skilled in the art, the present invention may be embodied in various configurations and should not, therefore, be considered or interpreted as limited to the detailed embodiments described herein. For example, although in the exemplary embodiments of the present invention, the controller  7  and the CPU  80  are illustrated as separate elements, they could also be integrated into a single controller. In addition, in the exemplary embodiments of the present invention, when the DUT  10  is a DRAM, the pattern generator  20  refreshes the DUT  10  by repeatedly outputting a refresh pattern. However, the pattern generator  20  could just as easily refresh the DUT  10  by repeatedly outputting a background pattern.  
         [0052]     According to the present invention, it is possible to reduce the time taken to test a memory by counting failure bits of the memory while a pattern generator generates a background pattern.