Abstract:
An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Description:
FIELD OF THE INVENTION 
       [0001]    The present disclosure relates to the field of microelectronics, and more specifically to the design of digital integrated circuits. It more specifically aims at specific arrangements relative to the adjustment of the output impedance of digital ports. 
       BACKGROUND OF THE INVENTION 
       [0002]    Generally, digital components have input and output ports which enable the exchange of signals with neighboring components. As an example, communication between a microprocessor and a random access memory (RAM) may be mentioned. 
         [0003]    In the search for high performance, increasing the operating frequency of the processor may be desirable, and thus the frequency of exchanges with neighboring components. At a certain level, the characteristic impedance of the connection between the output of a component and the input of the neighboring component may have an influence on the quality of the transmitted signal. In other words, it may be advantageous for the input or output impedance of an input or output port to be calibrated. 
         [0004]    Various specifications exist depending on the technology used, which may set the optimal input or output impedance value, as well as the tolerances. To respect these specifications, it may be desirable to calibrate the output impedance of the concerned output ports, since it may depend on multiple factors. One can, in particular, mention factors associated with the component manufacturing process, or factors capable of varying along with the circuit operation, and in particular, the temperature of use, or the value of the power supply voltage for an autonomous device. Calibration of the output impedance of a digital port has already been provided by selecting an appropriate number of active transistors in a buffer or driver stage between a control terminal of the output signal and the actual output terminal. 
       SUMMARY OF THE INVENTION 
       [0005]    Calibration circuits known to date, ensuring the selective activation of various transistors, may cause parasitic signals on reconfiguration of the buffer stages during a calibration process. It may thus be desirable to allow calibrations at any time of the operating cycle of a circuit while generating the smallest possible amount of disturbance during calibration cycles. 
         [0006]    With this in mind, the embodiments thus provide an integrated circuit that includes at least one digital output port that includes at least one stage assembled in parallel. Each buffer stage is connected, on one hand, to a common output signal control terminal and, on the other hand, to the output terminal of this port. Each buffer stage may include at least two subassemblies of at least two MOSFET transistors. That is, each buffer stage may include a first subassembly of at least two transistors called pull-up transistors, having their sources connected to a common high voltage, and having their drains connected to a common node connected to the output terminal. Each buffer stage may also include a second subassembly of at least two transistors called pull-down transistors, having their sources connected to a common low voltage, and having their drains connected to a common node connected to the output terminal of the port. 
         [0007]    In other words, the first subassembly may include at least two pull-up transistors and the second subassembly may include at least two pull-down transistors. All the transistors are mounted in parallel between two common nodes. In particular, the drains of the transistors of the first and second subassemblies are connected to the common node connected to the output terminal of the port. The sources of the pull-up transistors are connected to the common high voltage, and the sources of the pull-down transistors are connected to the common low-voltage. 
         [0008]    In addition, the transistors are formed in the thin semiconductor layer of an FDSOI-type substrate. This substrate includes a relatively thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. The areas of the thick semiconductor layer facing the transistors are connected to a circuit for adjusting their voltage to vary the threshold voltage of the transistors. In other words, this circuit enables setting, by analog means or circuitry, of the impedance of each of the transistors, by acting on the voltage applied to the back plane or ground plane of the transistor. 
         [0009]    Each transistor may be selected via their gate, and the selected transistors are thus mounted in parallel between two common nodes. This approach allows combining a plurality of buffers and a plurality of first and second subassemblies, thus allowing a finer calibration setting. 
         [0010]    According to various embodiments the adjustment circuit may be controlled by a comparator stage that includes a voltage divider comprising an external calibration resistor. The adjustment circuit may include a capacitive element having its charge or its discharge controlled by the comparator stage. The adjustment circuit may be controlled by a calibration starting circuit, enabling action of the setting circuit during predetermined periods. Each buffer stage may include a resistive linearization element between the common node to which are connected the sources of the transistors and the output terminal of the output port. 
         [0011]    The integrated circuit may also include an activation circuit, capable of selectively connecting the gates of all or part of the transistors of a subassembly to the common output signal control terminal. The integrated circuit may also include a configuration circuit capable of connecting in parallel all or part of the buffer stages. 
         [0012]    The present embodiments also provide a method for adjusting the output impedance of a digital output port of an integrated circuit. The port may include one or several buffer stages arranged in parallel, and each connected, on the one hand, to a common terminal for controlling the output signal and, on the other hand, to the output terminal of the port. Each stage may include at least two subassemblies of MOSFET transistors, that is, a subassembly of at least two pull-up transistors having their sources connected to a common high potential, and having their drains connected to a common node connected to the output terminal of the port, and a subassembly of at least two pull-down transistors, having their sources connected to a common low potential, and having their drains connected to a common node, connected to the output terminal. 
         [0013]    The transistors may be formed in the thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating said thin and thick semiconductor layers. The voltage of the areas of the thick semiconductor layer may be arranged in front of the transistors and adjusted to set the threshold voltage of each transistor. 
         [0014]    According to different alternative executions, all or part of the transistors of each subassembly may be selectively activated by selectively connecting the gate of all or part of the transistors of a subassembly to the common output signal control terminal. All or part of the buffer stages may be selectively connected in parallel. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a schematic diagram showing an output port according to a first embodiment. 
           [0016]      FIG. 2  is a schematic cross-sectional view of an embodiment of a substrate including transistors of the output port of  FIG. 1 . 
           [0017]      FIG. 3  is a schematic cross-sectional view of another embodiment of a substrate including transistors of the output port of  FIG. 1 . 
           [0018]      FIG. 4  is a schematic diagram of a circuit for calibrating the output port of  FIG. 1 . 
           [0019]      FIG. 5  is a schematic diagram of a portion of the circuit for adjusting the back plane voltage applied to the respective pull-up transistor in accordance with an embodiment. 
           [0020]      FIG. 6  is another schematic diagram of a portion of the circuit for adjusting the back plane voltage applied to the respective pull-down transistor in accordance with an embodiment. 
           [0021]      FIG. 7  is flow diagram showing a process for calibrating the output port of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0022]    The following description will use terms power supply voltage or high voltage, also designated by abbreviations V DD , VDD E  or the like, to refer to the same type of high voltage level. Similarly, terms “low-level voltage”, ground, or abbreviations GND, GND E  or the like are equivalent. 
         [0023]    As illustrated in  FIG. 1 , an integrated circuit  1  includes a plurality of output ports  2 . Each output port includes several buffer stages  3  arranged in parallel, and which are all connected to a common terminal  4  for controlling the output signal. The terminal  4  is typically connected to a core portion of the integrated circuit. These different stages  3  are also all connected to output terminal  5  connecting integrated circuit  1  to the neighboring components. 
         [0024]    In the illustrated embodiment, each output stage  3  includes a plurality of transistors  10 ,  11 ,  12 ,  20 ,  21 ,  22 , which enable connection of the output terminal  5  to the high voltage or to the low voltage, according to output signal  4 . In practice, the different transistors of a buffer stage have different characteristics enabling coverage of the widest desired impedance range with the appropriate combinations. Thus, as an example, the transistors may have increasing gate widths having their values doubling from one transistor to the other to be able to use a binary selection mode. Of course, other configurations may be envisaged with different distributions of the characteristics of the different transistors. 
         [0025]    More specifically, part of these transistors  10 ,  11 ,  12 , enable connection of the output terminal  5  to a high voltage, typically, a power supply voltage V DDE . Such pMOS-type transistors have their drains all connected to a common node  30 , itself connected to the output terminal  5  via a linearization resistor  31 . 
         [0026]    Other transistors  20 ,  21 ,  22  may be complementary transistors, that is, nMOS, and have their sources connected to a low potential node GND E , while their drains are all connected to the common node  30 , also having the drains of the other pull-up transistors connected thereto. 
         [0027]    In the embodiment of  FIG. 1 , the output port includes a linearization resistor  31 , which is used to make the voltage-vs.-current characteristic of the output port more linear. However, in certain configurations, the linearization resistor may be omitted. 
         [0028]    The gate of each of these transistors is connected to logic gates enabling to apply the voltage present on control terminal  4  thereto, according to configuration signals. More specifically, pull-up transistors  10 ,  11 ,  12  have their gates connected to gates  60 ,  61 ,  62  having an inverting output and which provide a logic “and” between the signal originating from control terminal  4  and a configuration signal  40 ,  41 ,  42 . In other words, when configuration signal  40 ,  41 ,  42  is at a high level, transistors  10 ,  11 ,  12  are in the off state, whatever the value of the signal originating from the control terminal  4 . Thus, transistors  10 ,  11 ,  12  are deactivated. Conversely, when configuration signal  40 ,  41 ,  42  is at a low level, transistors  10 ,  11 ,  12  switch to the on or off state when the signal originating from the control terminal  4  is respectively in the high or low state. 
         [0029]    Complementarily, the nMOS-type pull-down transistors have gates controlled by an inverting “or” gate  70 ,  71 ,  72  having an input connected to the control terminal  4 . The other terminal is connected to a configuration signal  50 ,  51 ,  52 . Similarly, when the configuration signals  50 ,  51 ,  52  are in a low state, transistors  20 ,  21 ,  22  are off, whatever the state of the control signal  4 . However, when the configuration signals  50 ,  51 ,  52  are at a high level, transistors  20 ,  21 ,  22  are on or off when the signal from the control terminal  4  is respectively low or high. 
         [0030]    In the illustrated embodiment, the different buffer stages  3  are identical, and the control signal for activating their different transistors is also identical so that the different stages are electrically connected in parallel. The general output impedance of the output port thus corresponds to the impedance of a stage divided by the number of stages arranged in parallel. According to an appropriate control of the activation of the different transistors of the stages arranged in parallel, it may be possible to modulate the number of stages arranged in parallel, and thus the value of the general output impedance of the port according to the value required by the application. 
         [0031]    Transistors  10 ,  11 ,  12 ,  20 ,  21 ,  22  of the output ports are formed from FDSOI-type substrates. Thus, as illustrated in  FIG. 2 , the pull-down transistor  100  is formed in a thin layer  101  of the FDSOI substrate. The thin semiconductor layer  101  is supported by an oxide layer  102 , which separates the thin layer  101  from a thick layer  103 . Thus, the transistor  100  may be totally insulated by the oxide layer  102  from the rest of the substrate  103 . In contrast to the transistor  100 , the thick layer  103  has, in contact with the oxide layer  102 , an area forming a ground plane or back plane  106 , and having a voltage capable of being controlled through an analog doping well  107  at the level of terminal  108 . It should be noted that for an nMOS-type transistor, it may thus be preferable to provide a deep insulation well  109  which is itself set to the high voltage by the terminal  110  to reverse-bias the PN junction formed with the well  107 , and thus reduce the chances of the substrate from being at the potential of the terminal  108 . 
         [0032]    For the pull-up transistors  150  illustrated in  FIG. 2 , a ground plane area  156  may also be set to a variable voltage to vary the threshold voltage of the transistor  150 . For this purpose, an N-doped well  107  enables setting of the ground plane  156  to a variable voltage, higher than the ground, via a terminal  158 . It should be noted that it is desirable that the rest of the substrate  120  be maintained at the low voltage via the terminal  160  to reverse-bias the PN junctions between the rest of the substrate and the N well  107  at the variable voltage. 
         [0033]    In such a configuration, the ground plane  106  of the pull-down transistor may be taken to a potential ranging up to the voltage of the VDD power supply. This configuration, however, enables the application of a reverse voltage, lower than GND for the pull-down transistor  100 , and higher than VDD for the pull-up transistor  150  corresponding to a configuration slowing down the transistor performances. 
         [0034]      FIG. 3  illustrates an alternative configuration where the pull-down transistor  200  has an N-doped ground plane  206 , which is placed into contact with the terminal  208  of the application of the variable potential via a well  207 , also N-doped. The maintaining of the rest  220  of the substrate at a potential equal to GND enables reverse-biasing of the PN junction between the rest of the substrate  220  and the well  207 . 
         [0035]    In such a configuration, for the pull-up transistor  250 , the area  256  forming the ground plane may be maintained at a variable potential, adjustable via the terminal  258  connected by a P-doped well  257 . To insulate the well  257  from the rest of the substrate  220 , a deep well  259  is formed and is maintained at a relatively high potential to reverse-bias the PN junction existing with the P well  257 , and the junction existing with the rest of the substrate  220 . 
         [0036]    In such a configuration, the voltage which may be applied to the back plane of the pull-down transistor  200  may be higher than the like in the example of  FIG. 2 , which enables acceleration of the transistor for obtaining better dynamics. The same can be observed for the pull-up transistor  250  with a ground plane which may be substantially lowered, and in particular, below the zero potential to increase the corresponding effect. 
         [0037]    As illustrated in  FIG. 1 , the terminals enabling setting of the potential of the ground planes of the different pull-up and pull-down transistors are controlled by an adjustment circuit integrated in a circuit for calibrating the impedance of the output port. Similarly, the orders of activation  40 ,  41 ,  42 ,  50 ,  51 ,  52  of the different transistors are also controlled by this circuit for calibrating the impedance. 
         [0038]    An embodiment of such a circuit is described in simplified manner in  FIG. 4 . Specifically, in the illustrated embodiment, the calibration circuit  300  includes a first area  301  corresponding to a replica of the assembly of the pull-up transistors  10 - 12  and the linearization resistor  31 . Thus, the pull-up transistors of circuit  301  are directly controlled by codes  310 . 
         [0039]    At output  302  of the linearization resistor, the circuit is connected to an external calibration resistor  304  which may have a value determined by the specifications of the technology used. For example, for standard LPDDR 2, it may be desirable for the impedance of the output ports to be 34.3Ω±15%. Still, as an example, when the output port includes seven stages in parallel, it may be desirable that each stage have a nominal individual impedance of 240Ω. By modulating the number of stages placed in parallel, it may thus be possible to program the total impedance to 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, 34.3Ω by selecting the adequate number of stages, individually calibrated to 240Ω. 
         [0040]    The external calibration resistor  304  is thus selected with this value so that the output terminal  302  of the circuit  301  replicating of the assembly of pull-up transistors to be half the power supply voltage. For this purpose, an automaton  350  scans the different possible combinations of activation codes  310  of the transistors. The output voltage of the replica circuit  301  is sampled to be compared by a comparator  308  to half the high power supply voltage  307 . The result of the comparison is sent to the automaton  350  to determine the optimal combination of activation codes for obtaining an impedance of the front assembly of pull-up transistors  301 , which may be as close as possible to the external calibration resistance  304 . 
         [0041]    For the pull-down transistors, the calibration is performed by using two replica circuits, that is, on the one hand, a circuit  320  replicating the set of pull-up transistors and, on the other hand, a circuit  330  replicating the set of pull-down transistors. 
         [0042]    The transistors of the circuit  320  replicating the pull-up transistors are controlled by activation codes  311  equal to codes  310  determined for the above-mentioned replica circuit  301 . The same logic is applied to the set of pull-down transistors of the replica circuit  330 , which are controlled by a set of activation codes  321  also controlled by the automaton  350 . 
         [0043]    Midpoint  340  of the outputs  322 ,  332  of the circuits  320 ,  330  replicating the pull-down and pull-up transistors is measured and compared with half the power supply voltage by comparator  358 . Comparator  358  delivers the results  359  of the comparison to the automaton  350  to have it determine the optimal code for the voltage of midpoint  340  to be as close as possible to half the power supply voltage. 
         [0044]    This phase of digital calibration, by the selective application of a number of pull-up and pull-down transistors, may be completed by an adjustment of the resistance of each of the transistors by action on the potential applied to the ground plane such as discussed above. More specifically, and as illustrated in  FIG. 4 , the calibration circuit  300  includes an adjustment stage  400 , which enables application of an adjustable voltage on the ground plane and the pull-up transistors. 
         [0045]    More specifically, and as illustrated in  FIG. 4 , the adjustment circuit  400  includes a switch  401  controlled by the automaton  350 . This switch enables connection of the common terminal  408  of the different ground planes of the transistors of replica circuit  301  either to a fixed value  405 , in particular, during initialization phases, and in particular during the adjustment of the different activation codes  40 ,  42 ,  50 ,  52 , or to a variable value  406  determined by the adjustment circuit  410 , which will be described in further detail below. The adjustable voltage  406  is determined according to the comparison of the output voltage  302  of the replication circuit with half the value of the power supply voltage. 
         [0046]    The same line of reasoning applies for the circuit  330  replicating the pull-down transistors with a terminal  458  common to the different ground planes of these transistors and which is selectively connected by the switch  451  controlled by the automaton  350 , between a fixed voltage  455  for initialization phases, and a variable voltage  456  determined by analog adjustment circuit  450 . Similarly, the voltage of the junction point  340  of the circuits  320 ,  330  replicating the pull-up transistors and the pull-down transistors is measured and compared with half the power supply voltage to enable the adjustment circuit  450  to accordingly modify the adjustable voltage  456 . 
         [0047]    The circuit  460  for adjusting the variable voltage applied to the ground planes of the pull-up transistors is illustrated in  FIG. 5 . Thus, at its input, this circuit receives, on the one hand, a signal  501  representative of an order for starting a calibration phase and, on the other hand, result  502  of the comparison of the voltage of the output of the circuit replicating the pull-up transistors with half the power supply voltage. Thus, the signal  501  for controlling the calibration phases can take a zero value outside of the calibration phases, and a value equal to 1 during the calibration phases. 
         [0048]    Similarly, the comparison signal has a value equal to 0 or 1 according to whether the output voltage of the replica stage  301  is greater or lower than half the power supply voltage. The first stage  510  of the adjustment circuit  400  delivers two signals  505 ,  506  to a second stage  520 , formed of two multiplexers having a common terminal, and further connected, for one,  521 , to the high potential and, for the other,  522 , to the low potential. 
         [0049]    The first multiplexer  521  generates a signal  524  which controls a transistor  535  enabling raising of the voltage across buffer capacitance  550 , itself connected to the different ground planes of the pull-up transistors of replica circuit  301  via the switch  401  illustrated in  FIG. 4 . The second multiplexer  522  delivers a signal  525  which controls a charge pump  538  which, on the contrary, enables decreasing of the voltage across the capacitance  550  when it is activated. 
         [0050]    To return to the first stage, the signal  505  takes a 1 or 0 value according to whether the voltage to be applied to the ground plane is to be increased or decreased to obtain the optimal output resistance. The second signal  506  makes the two multiplexers  521 ,  522  of the second stage  520  active or blocks them. Thus, when a rising edge is detected on the control signal  501  of a calibration phase, the state of the comparison signal  502  is set to be applied to the common terminals of the two multiplexers  521 ,  522 . The second signal  506  is then set to 0, which starts the calibration process  550  either by increasing or decreasing the voltage across the buffer capacitance, which corresponds to the voltage applied to the different ground planes. 
         [0051]    When a state switching is observed on the comparison signal  502 , the targeted impedance has been reached. Accordingly, the control signal  506  of the multiplexers switches state by switching to a high value, which stops the analog calibration phase. 
         [0052]    The following truth table summarizes the different possible configurations. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                   
               
               
                   
                   
                   
                   
                 Capacitance 
               
               
                 506 
                 505 
                 524 
                 525 
                 voltage 550 
               
               
                 (CAL/CUT) 
                 (UP/DN) 
                 (UP_CMD) 
                 (DN_CMD) 
                 (PU_BB) 
               
               
                   
               
             
             
               
                 0 
                 0 
                 1 
                 1 
                 Decreasing 
               
               
                 0 
                 1 
                 0 
                 0 
                 Increasing 
               
               
                 1 
                 X 
                 1 
                 0 
                 Stable 
               
               
                   
               
             
          
         
       
     
         [0053]      FIG. 6  illustrates a diagram  450  similar to that of  FIG. 5 , adapted to control the adjustable voltage of the ground planes of the pull-down transistors. The difference may essentially lie in the use of a charge pump  638  to raise the voltage in the capacitance  650  across which the voltage applied to the ground plane can be found. 
         [0054]      FIG. 7  illustrates a simplified algorithm of operation of the calibration circuit. Thus, after a phase  701  of starting the integrated circuit, a first phase of digital calibration of the impedance of the assembly of pull-up transistors  702  is first carried out by determining the optimal set of configuration codes to activate the transistors to obtain an impedance as close as possible to the desired impedance. 
         [0055]    During first phase  702 , the voltage applied to the ground planes of the pull-up transistors is maintained at an initialization value VBBinit. In the specific embodiment corresponding to the configuration of  FIG. 3 , where the ground plane voltage of the pull-up transistors may be adjusted between −VDDE and +VDDE, VBBinit is equal to GNDE. More generally, VBBinit may be selected as the midpoint between the limiting voltages applicable to the ground plane. This enables, after a digital calibration to compensate for the effects on the impedance due to the manufacturing process, as much amplitude in one direction as in the other to compensate for impedance variations due to phenomena such as temperature or the value of the power supply voltage. 
         [0056]    At a subsequent step  703 , the digital calibration of the pull-down transistors is performed as mentioned above by maintaining the ground plane voltage of the pull-down transistors at an initial value, for example, selected as the midpoint of the possible excursion. In the case of the configuration of  FIG. 3 , the voltage applicable to the ground planes of the pull-down transistors may vary between GNDE and 2xVDDE, so that the initial value is selected to be VDDE. 
         [0057]    It may be chosen to no longer act on the different activation codes of the transistors of each of the stages to limit jitter phenomena which might occur based upon modifications of the activation codes, in particular of large-weight activation codes. The system thus provides a self-calibration of the impedance only by the analog adjustment  705  of the voltage applied to the ground planes of the pull-up transistors, and then of the pull-down transistors,  706 . Both calibrations  705 ,  706  may be performed regularly, with no impact or at least a limited impact on signal transmission, since the impedance characteristics of the concerned stage vary continuously. Thus, the starting of a new calibration phase by analog means or circuitry  705 , 706  may be triggered after a settable delay  708 , and if desirable, a monitoring  704  of the temperature and/or of the power supply voltage. 
         [0058]    Based upon the foregoing, an integrated circuit that includes such a mechanism for adjusting its output impedance may have a better impedance tuning sharpness, since this tuning is performed continuously or no longer discretely. Further, this adjustment may occur more frequently than for a simple digital adjustment, since it generates but little disturbance on signal transmission. 
         [0059]    Although a combination of two digital and analog adjustments has been described, the above-described principle may apply to systems where the impedance setting is performed by analog means or circuitry only by adapting the impedance range. Similarly, in certain applications a single pull-up or pull-down transistor per stage may be used, with an accordingly modified impedance excursion.