Abstract:
An output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit change a value of the variable impedance of the signal output path.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This is a continuation application of U.S. application Ser. No. 13/592,368 filed on Aug. 23, 2012, and U.S. application Ser. No. 13/592,368 is a continuation application of U.S. application Ser. No. 13/014,672 filed on Jan. 26, 2011, which are included in its entirety herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to an output buffer circuit capable of enhancing stability, and more particularly to an output buffer circuit that increases a phase margin of an operational amplifier by adjusting output path impedance of the operational amplifier. 
         [0004]    2. Description of the Prior Art 
         [0005]    Output buffers are usually applied to various electronic devices for isolating signals from input terminals to output terminals to avoid the input terminals being affected by loading and for enhancing driving ability. In Liquid Crystal Display (LCD) devices, for example, source drivers charge each pixel in LCD panels to an individual voltage level to drive liquid crystal molecules of each pixel by using the output buffers. Hence, the driving ability of the output buffer is highly related to display performance and responding time of the LCD devices. 
         [0006]    Please refer to  FIG. 1 , which is a schematic diagram of a conventional source driver  10 . The source driver  10  includes a shift register  11 , a data latch (or known as a line buffer)  12 , a digital-to-analog converter (DAC)  13 , an output buffer  14 , and an output switch  15 . The shift register  11  is utilized for sequentially receiving image data DATA according to a clock signal CLK. When the image data corresponding to a horizontal scan line data is received, the data latch  12  grabs the data temporarily stored in the shift register  11  according to a data loading signal LOAD generated by a timing controller (not shown), such that the shift register  11  can proceed to receive the image data of a next horizontal scan line. The DAC  13  then converts the digital pixel data stored in the data latch  12  to analog voltages and outputs the analog voltages to the output buffer  14 . The output buffer  14  is utilized for providing sufficient driving ability, and the output switch  15  is utilized for sequentially coupling the output buffer  14  to a corresponding data line DL. Accordingly, the data line DL can be drove. 
         [0007]    In  FIG. 1 , the output buffer  14  and the output switch  15  is known as an output buffer circuit of the source driver  10 . More specifically, as shown in  FIG. 2 , the output buffer  14  includes an operational amplifier  110 , and the output switch  15  includes a switch SW for forming a signal path to the data line DL via an output pad P of the source driver  10 . The operational amplifier  110  has a positive input terminal IN+, a negative input terminal IN− and an output terminal OUT. The positive input terminal IN+ is utilized for receiving an analog voltage. The output terminal OUTPUT is coupled to the negative input terminal IN− to form a negative feedback loop. The operational amplifier  110  is utilized for driving the voltage of the output pad P to a certain voltage level according to the analog voltage received by the positive input terminal IN+. However, in order to drive different pixels of the data line DL at different time, the source driver  10  must renew the analog voltage frequently. The source driver  10  turns off the switch SW when renewing the analog voltage, and turns on the switch SW for outputting the analog voltage being renewed to the data line DL until the data line DL is ready to be charged. 
         [0008]    When the switch SW is turned on, the output terminal OUT of the operational amplifier  110  is electrically connected to the data line DL through the output pad P. In general, the stabilization time of the output voltage is determined by capacitive load CLOAD of the date line DL, turn-on impedance of the switch SW and output impedance of the operational amplifier  110 . However, in order to decrease power loss, the conventional source driver continuously reduces the DC currents of the output buffer, causing that a phase margin of the operational amplifier is decreased and thus the stabilization time is increased. Under this condition, it is inevitable to postpone the testing time of the output voltage, resulting in the increase of the testing cost. 
       SUMMARY OF THE INVENTION 
       [0009]    It is therefore an objective of the claimed invention to provide an output buffer circuit capable of enhancing stability. 
         [0010]    The present invention discloses an output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal to reach a predetermined level, the output control unit change a value of the variable impedance of the signal output path. 
         [0011]    The present invention further discloses an output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and one or more output switches, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, wherein when the operational amplifier starts to charge or discharge the second terminal, the one or more output switches has a first impedance, and when the voltage level at the second terminal is detected to reach a predetermined level, the one or more output switches has a second impedance different from the first impedance. 
         [0012]    The present invention further discloses an output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal for a predetermined time, the output control unit change a value of the variable impedance of the signal output path. 
         [0013]    The present invention further discloses an output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and one or more output switches, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, wherein when the operational amplifier starts to charge or discharge the second terminal, the one or more output switches has a first impedance, and when the operational amplifier charges or discharges the second terminal for a predetermine time, the one or more output switches has a second impedance different from the first impedance. 
         [0014]    The present invention further discloses an output buffer circuit of a source driver includes an operational amplifier, having a first terminal as an output of the operational amplifier, and an output control unit, coupled between the output terminal of the operational amplifier and a second terminal for driving a load, to generate a variable impedance of a signal output path between the first terminal and the second terminal, wherein when the operational amplifier charges or discharges the second terminal, and after the second terminal reaches a stable state, and the output control circuit gradually changes the impedance of the signal output path. 
         [0015]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a schematic diagram of a conventional source driver. 
           [0017]      FIG. 2  is a schematic diagram of an output buffer circuit of the source driver in  FIG. 1 . 
           [0018]      FIG. 3  is a schematic diagram of an output buffer circuit according to an embodiment of the present invention. 
           [0019]      FIG. 4  is a signal timing diagram of the output buffer circuit in  FIG. 3 . 
           [0020]      FIG. 5  is a schematic diagram of an output buffer circuit according to another embodiment of the present invention. 
           [0021]      FIG. 6  is a signal timing diagram of the output buffer circuit in  FIG. 5 . 
           [0022]      FIG. 7  is a schematic diagram of an output buffer circuit according to further another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0023]    Please refer to  FIG. 3 , which is a schematic diagram of an output buffer circuit  30  according to the embodiment of the present invention. The output buffer circuit  30  includes an operational amplifier  31 , a capacitive load CLOAD and an output control unit  32 . The operational amplifier  31  has a positive input terminal IN+, a negative input terminal IN−, and an output terminal OUT. The positive input terminal IN+ is utilized for receiving an analog voltage. The output terminal OUTPUT is coupled to the negative input terminal IN− to form a negative feedback loop. The operational amplifier  31  generates a corresponding output voltage to the output terminal OUT according to the analog voltage received by the positive input terminal IN+. The output control unit  32 , coupled between the output terminal OUT of the operational amplifier  31  and the capacitive load CLOAD, is utilized for controlling electrical connection between the output terminal OUT of the operational amplifier  31  and the capacitive load CLOAD to form a signal output path, and for adjusting impedance of the signal output path when the signal output path is formed. 
         [0024]    Therefore, when the operational amplifier  31  charges the capacitive load CLOAD, the embodiment of the present invention adjusts the impedance of the signal output path to control zero point locations of the operational amplifier, so as to increase phase margin of the operational amplifier. As a result, the stability of the whole system is enhanced and the stabilization time and the testing cost are thus reduced. 
         [0025]    In the embodiment of the present invention, the output control unit  32  may include a plurality of output switches, for turning on or off the electrical connection between the output terminal OUT of the operational amplifier  31  and the capacitive load CLOAD to form the signal output path. In this case, the impedance of the signal output path is then determined by the quantity of the turned-on switches. 
         [0026]    In  FIG. 3 , for example, the output control unit  32  includes two CMOS transmission gates, each composed of a PMOS switch (PSW 1  and PSW 2 ) and an NMOS switch (NSW 1  and NSW 2 ), for performing switch operation according to control signals OPC 1  and OPC 2  and inversion signals OPCB 1  and OPCB 2  thereof. Principles and detailed operations of the CMOS transmission gates are well-known by those skilled in the art, and thus are not further narrated herein. Please refer to  FIG. 4 , which is a signal timing diagram of the output buffer circuit  30 . At first, the operational amplifier  31  receives an analog voltage from the output of a front circuit in a data load phase. Then, when the output buffer circuit  30  intends to charge the capacitive load CLOAD by the output voltage of the operational amplifier  31  (i.e. in an output phase of the operational amplifier), all the PMOS switches PSW 1 , PSW 2  and the NMOS switches NSW 1 , NSW 2  are turned on. At this time, the impedance of the signal path between the operational amplifier  31  and the capacitive load CLOAD becomes a minimum value such that the operational amplifier  31  can charge and discharge the capacitive load CLOAD quickly. When the capacitive load CLOAD is charged to a predetermined level (or being charged for a predetermined time), some of the CMOS transmission gates such as the switches NSW 2  and PSW 2 , for example, are turned off, for increasing the impedance of the signal path between the operational amplifier  31  and the capacitive load CLOAD. 
         [0027]    In this way, the zero-point positions of the operational amplifier can be controlled by the impedance of the signal output path, so as to increase the phase margin of the operational amplifier. As a result, the stability of the whole system is enhanced and thus the stabilization time and the testing cost can be reduced. 
         [0028]    In addition, the control signals OPC 1 , OPC 2  and the inversion signals OPCB 1 , OPCB 2  thereof are generated by a control signal generation unit  33 . The control signal generation unit  33  switches logic levels of the control signals OPC 1 , OPC 2  and the inversion signals OPCB 1 , OPCB 2  to turn off some of the transmission gates when the voltage level of the capacitive load CLOAD reaches to a stable state, such as when the capacitive load CLOAD is charged to a predetermined level or a predetermined time after the output phase of the operational amplifier begins, for example. 
         [0029]    Please note that, in the embodiment of the present invention, the plurality of output switches included by the output control unit  32  are implemented by the CMOS transmission gates in order to meet requirements of a variety of output voltage levels of the operational amplifiers. However, in other embodiments of the present invention, each output switch can be implemented by any kind of transistor switches such as PMOS switches, NMOS switches or bipolar transistor switches, etc., and is not restricted herein. 
         [0030]    Certainly, the output switch quantity of the output control unit  32  can be adjusted according to actual demands and is not limited to this. Please refer to  FIG. 5 , which is a schematic diagram of an output buffer circuit  50  according to another embodiment of the present invention. Compared to the output buffer circuit  30  of  FIG. 3 , the output control unit  52  includes four pairs of transmission gates, each composed of a PMOS switch (PSW 3 -PSW 6 ) and an NMOS switch (NSW 3 -NSW 6 ), for performing switch operations according to control signals OPC 3 -OPC 6  and inversion signals OPCB 3 -OPCB 6  thereof, respectively. Please refer to  FIG. 6 , which is a signal timing diagram of the output buffer circuit  50 . Similarly, in a data load phase, the operational amplifier  51  receives an analog voltage from the output of a front circuit. Then, when the output buffer circuit  50  intends to charge the capacitive load CLOAD by the output voltage of the operational amplifier  51  (i.e. in an output phase of the operational amplifier), all the PMOS switches PSW 3 -PSW 6  and the NMOS switches NSW 3 -NSW 6  are turned on. At this time, the impedance of the signal path between the operational amplifier  51  and the capacitive load CLOAD becomes a minimum value, such that the operational amplifier  51  can charge or discharge the capacitive load CLOAD quickly. When the capacitive load CLOAD is charged to a predetermined level (or being charged for a predetermined time), the CMOS transmission gates are sequentially turned off to gradually increase the impedance of the signal path between the operational amplifier  51  and the capacitive load CLOAD. 
         [0031]    In this way, during the process that the output switches are sequentially turned off, the output path of the operational amplifier has impedance larger than the condition when all the output switches are turned on, so that the phase margin of the operational amplifier is increased. As a result, the stability of the whole system is enhanced, so as to reduce the stabilization time and the testing cost. 
         [0032]    On the other hand, please refer to  FIG. 7 , which is a schematic diagram of an output buffer circuit  70  according to another embodiment of the present invention. The output buffer circuit  70  includes an operational amplifier  71 , a capacitive load CLOAD and an output control unit  72 . Compared to the above embodiments, the output control unit  72  only includes one output switch SW 1  for turning on or off the electrical connection between the output terminal OUT of the operational amplifier  71  and the capacitive load CLOAD according to a control signal OPC, so as to form a signal output path. The control signal OPC is generated by a control signal generation unit  73 . When the voltage level of the capacitive load CLOAD reaches to a stable state such as when the capacitive load CLOAD is charged to a predetermined voltage level, or a predetermined time after the operational amplifier enters into the output phase, for example, the control signal generation unit  73  adjusts the voltage level of the control signal OPC to control conductivity of the output switch SW 1 . In this way, the impedance of the signal output path can be adjusted according to the conductivity of the output switch SW 1 . 
         [0033]    That is to say, when the output buffer circuit  70  intends to charge the capacitive load CLOAD by the output voltage of the operational amplifier  71 , the output switch SW 1  would be turned on completely. At this time, the impedance of the signal path between the operational amplifier  71  and the capacitive load CLOAD becomes a minimum value, such that the operational amplifier  71  can charge or discharge the capacitive load CLOAD quickly. When the capacitive load CLOAD is charged to a stable state such as reaching to a predetermined voltage level or being charged for a predetermined period, for example, the output switch SW 1  would be switched to an incomplete conduction state according to level variation of the control signal OPC, such that the impedance of the signal path between the operational amplifier  71  and the capacitive load CLOAD is increased. 
         [0034]    In general, the control signals of the output switches are generated by low-voltage logic circuits. Thus, level shifters are required to transform the control signals to the level of high-voltage components, such that the output switches can be turned on or off by the control signals. In the embodiment of the present invention, the control signal generation unit  73  includes level shifters LS 1 -LSn, and a multiplexer MUX. The level shifters LS 1 -LSn generate supply voltages VDD 1 ˜VDDn according to a logic signal LG, respectively. The multiplexer MUX is coupled to the level shifters LS 1 -LSn, and is utilized for switching the supply voltages VDD 1 ˜VDDn according to the voltage of the capacitive load CLOAD, to generate the control signal OPC of the output switch SW 1 . The relationship of the supply voltages VDD 1 ˜VDDn is as follows: VDD 1 &gt;VDD 2 &gt; . . . &gt;VDDn&gt;GND. 
         [0035]    In the embodiment of the present invention, the output switch SW 1  is completely turned on when the control signal OPC has a level of VDD 1 , and is completely turned off when the control signal OPC has a level of GND. Since the output switch SW 1  is implemented by a CMOS transmission gate, by the conduction characteristics of CMOS devices, the impedance of the output switch SW 1  is higher when the control signal OPC has a level less than the supply voltage VDD 1  than when the output switch SW 1  is turned on completely. The increase of the impedance affects the zero position of the operational amplifier, to improve the phase margin of the operational amplifier and shorten the stabilization time of the output buffer circuit. 
         [0036]    In short, the embodiment of the present invention varies the transistor gate voltage of the output switch to control the output path impedance of the operational amplifier, so as to shorten the stabilization time of the output buffer circuit. Certainly, the spirit of the above embodiment is not limited to the case shown in the figure. All output buffer circuits that adjust the impedance of the signal output path to improve the stability of the output buffer circuit belong to the scope of the present invention. 
         [0037]    To sum up, the output buffer circuit of the present invention controls the output path impedance of the operational amplifier to adjust the zero position of the operational amplifier, so as to shorten the stabilization time and the testing time. As a result, the testing cost of the source driver can be effectively reduced, while the competitiveness is raised. 
         [0038]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.