Abstract:
A system and method is disclosed for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group.

Description:
RELATED APPLICATIONS  
       [0001]    This application is related to concurrently filed and commonly assigned U.S. patent application Ser. No. ______ entitled “PROCESS AND SYSTEM FOR DEVELOPING DYNAMIC CIRCUIT GUIDELINES”, attorney docket number 10014072-1, the disclosure of which is hereby incorporated herein by reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention is directed to designing dynamic circuits and, more specifically, to a system and method for representing all silicon-on-insulator (SOI)-based dynamic circuits via a combination of, at most, three logic circuits.  
         BACKGROUND  
         [0003]    Dynamic circuits are circuits designed for high speed logic gates. The intent for such circuits is typically to achieve the fastest switching speed available with the lowest possible power consumption. Dynamic circuits have been implemented in bulk complementary metal-oxide semiconductor (CMOS) in order to take advantage of the speed and power benefits of CMOS. Recent advances in integrated circuit technology have shown the speed and power advantages of SOI-based integrated circuits. FIG. 1A is a cross-section view of CMOS device  100 . P-type body/substrate  101  includes two n-type wells, source  102  and drain  103 . Gate terminal  104 , along with source  102  and drain  103  form the CMOS field effect transistor (CMOSFET). In operation, a large capacitance typically forms between source  102  and body/substrate  101  and between drain  103  and body/substrate  101 . This capacitance not only delays the switching speed, but also contributes to added power consumption.  
           [0004]    [0004]FIG. 1B is a cross-section view of SOI device  105 . SOI device  105  includes n-type source  109 , gate terminal  111 , p-type substrate  106 , and n-type drain  110 . However, unlike bulk CMOS device  100 , oxide layer  107  isolates source  109  and drain  110  from body  108 . Because the source-to-body and drain-to-body junctions are isolated, there is not as much junction capacitance formed in SOI device  105  as in CMOS device  100 . As a result, SOI-based designs are approximately 30% faster than CMOS designs, with a typical 80% reduction in power consumption.  
           [0005]    The isolation of the junctions in SOI-based devices results in a body voltage that may float depending on the configuration of the circuit in which the device is included. In comparison, the body voltage in bulk CMOS devices remains more or less constant. The floating body effect in SOI-based technology, therefore, creates problems in the design of dynamic circuits.  
         BRIEF SUMMARY OF THE INVENTION  
         [0006]    The present invention is directed to a system and method for designing a dynamic circuit in a silicon-on-insulator (SOI) process comprising the steps of representing the dynamic circuit using at least one logic circuit, wherein the at least one logic circuit is selected from a group consisting of: an OR circuit with a DNG field effect transistor (FET), an OR circuit without said DNG FET, and an AND circuit, and wherein the at least one logic circuit is selected according to body voltage characteristics of each circuit in the group. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    [0007]FIG. 1A is a cross-section view of a CMOS device;  
         [0008]    [0008]FIG. 1B is a cross-section view of a SOI device;  
         [0009]    [0009]FIG. 2 is a circuit diagram representation of an OR logic circuit as used in accordance with an embodiment of the present invention;  
         [0010]    [0010]FIG. 3 is a circuit diagram representation of an OR logic circuit with a DNG FET as used in accordance with an embodiment of the present invention;  
         [0011]    [0011]FIG. 4 is a circuit diagram representation of an AND logic circuit as used in accordance with an embodiment of the present invention;  
         [0012]    [0012]FIG. 5 is a circuit schematic illustrating a wide gate width OR circuit and one possible corresponding model circuit generated according to one embodiment of the present invention;  
         [0013]    [0013]FIG. 6 is a circuit schematic illustrating a wide gate width OR circuit with a DNG FET and one possible corresponding model circuit generated according to one embodiment of the present invention;  
         [0014]    [0014]FIG. 7 is a circuit schematic illustrating a wide gate width AND/OR circuit and one possible corresponding model circuit generated according to one embodiment of the present invention; and  
         [0015]    [0015]FIG. 8 is a schematic illustrating a complex dynamic circuit gate and one possible corresponding model circuit generated according to one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    Dynamic circuits typically are constructed with similar basic parts. FIG. 2 is a circuit diagram representation of an OR logic circuit in accordance with an embodiment of the present invention. While FIG. 2 shows one of the circuits used in design methodologies implemented according to the teachings of the present invention, it is also configured as a simple dynamic circuit. OR circuit  20  may comprise one FET positioned to assist in charging storage node  23  to the appropriate/desired charge/value. This FET is generally referred to as “pre-charge” FET  21 . Another typical feature of a dynamic circuit, such as OR circuit  20 , is another FET positioned to hold the storage node  23  at the desired charge/value. This FET is generally referred to as “holder” FET  28  and may be either a p- or n-type FET (typically a p-type, PFET) depending on the configuration of the overall circuit technology. Because of their typical configuration, pre-charge FET  21  will generally be the same type (p- or n-) as holder FET  28 .  
         [0017]    A dynamic circuit, such as OR circuit  20 , may also generally include another FET positioned to provide a path to ground for storage node  23  during evaluation of the circuit (i.e., when the circuit content/charge is read). This FET is generally referred to as “pull-down” FET  25 . Because its function usually causes it to sink or pass considerable current, pull-down FET  25  is generally a strong, robust transistor. Furthermore, there may be multiple FETs making up the function of pull-down FET  25 . It should be further noted that, depending on the configuration of the circuit, the holder and pre-charge FETs could be NFETs with the pull-down FET being PFET. A dynamic circuit, such as OR circuit  20 , may also have a forward inverter, such as inverter  27 , which inverts the value/charge on storage node  23 , for output  29 .  
         [0018]    Many dynamic circuits are clock-driven circuits, meaning that their cycles are triggered by clock pulses. There are typically two clock phases for dynamic circuits: pre-charge phase and evaluation phase. The pre-charge phase generally occurs when pull-down FET  25  is turned off and pre-charge FET  21  is on. During this phase, pre-charge FET  21  will typically charge storage node  23 . The evaluation phase generally occurs when clock  24  is in a second state, such as the high state. During the evaluation phase, pull-down FET  25  will be on when OR circuit  20  is to be evaluated. This allows pull-down FET  25  to provide a path to ground; thereby, allowing OR circuit  20  to be evaluated. Depending on what OR circuit  20  is evaluating, pull-down FET  25  may either turn on and discharge storage node  23 , or remain off in which case storage node  23  should maintain its charge with the help of holder FET  28 . Holder FET  28  is typically designed to be weak so that during the evaluation phase pull-down FET  25  will be stronger than holder FET  28 ; thus, storage node  23  will be discharged and OR circuit  20  evaluated.  
         [0019]    Complexity typically arises during the pre-charge phase when pre-charge FET  25  is off and storage node  23  is being held at charge. In this situation, a problem sometimes arises when noise is present on pull-down FET  25 . Even though a FET will typically not turn on until a threshold voltage is reached, current may still leak through the device (referred to as sub-threshold leakage) if voltage on the gate terminal increases. The noise may supply enough voltage to the gate terminal to increase the amount of sub-threshold leakage, which may lead to incorrectly evaluating the circuit.  
         [0020]    Another source of leakage in SOI devices comes from the parasitic bipolar junction transistor (BJT) that may form in an NFET. Referring again to FIG. 1B, an NFET generally comprises n-type source  109  (emitter), p-type body  108  (base), and n-type drain  110  (collector). Under the right conditions, this configuration may activate the BJT and begin BJT leakage current leaking through the SOI device. This may occur when source  109  voltage drops below the body voltage (i.e., forward biasing the base-emitter junction). Because source  102  (FIG. 1A) is typically tied to substrate  101  (FIG. 1A) in bulk CMOS, parasitic BJT leakage, while still there, usually does not create a problem.  
         [0021]    To minimize the sub-threshold and BJT leakage, the circuit&#39;s immunity to noise generally needs to be increased. One way to increase a circuit&#39;s noise immunity is to increase the size of holder FET  28 . Increasing holder FET  28 &#39;s size generally makes it more difficult for pull-down FET  25  to turn on; thus, making it more difficult for noise across pull-down FET  25  to inadvertently turn them on. However, by increasing the size of holder FET  28 , it also typically becomes more difficult to evaluate OR circuit  20  when desired. This difficulty generally arises because holder FET  28  and pull-down FET  25  will likely compete between pulling-down or maintaining the storage node charge. Consequently, to evaluate OR circuit  20 , the size of pull-down FET  25  will usually need to be larger than the size of holder FET  28 .  
         [0022]    Another method for increasing the circuit&#39;s noise immunity would be to change the forward inverter ratio (FIR). The FIR is generally considered to be the ratio between the FETs of the circuit&#39;s forward inverter. The higher the FIR ratio, the faster the transistors will typically switch, whereas the lower the ratio, the slower the transistors will likely switch. The objective in designing SOI dynamic circuits then is to find the optimal ratio, where the circuit is as fast as possible while remaining immune to noise.  
         [0023]    In the design and modeling of CMOS dynamic circuits, a single-circuit model is typically used to represent and/or model the worst-case scenarios of all dynamic circuits. OR circuit  20 , shown in FIG. 2, is generally the single model circuit used to model the “worst-case” design in CMOS. Designer&#39;s typically design for worst-case in order to create robust circuits capable of operation in the worst-case. In CMOS technology, a single-circuit model is adequate to model any circuit architecture because the bodies are coupled to the substrate and, thus, essentially connected to ground. However, in SOI technology single-circuit-type modeling is inadequate due to the existence of the “floating body.” Consequently, the body voltage may change, both dynamically and statically, making it impractical to model SOI dynamic circuits with only a single-circuit because the body voltage may range (i.e., “float”) anywhere from 0 to V DD . Furthermore, using only a single circuit-model, while producing a robust circuit, would generally sacrifice considerable performance in certain circuit configurations. As a result, each SOI-based dynamic circuit is generally modeled individually. This modeling process can be extremely time consuming and, therefore, expensive to implement. For complex circuits, many man-hours of engineer time may be expended.  
         [0024]    Referring again to FIG. 2, FIG. 2 is a circuit diagram representation of OR circuit  20  as used in accordance with an embodiment of the present invention. OR circuit  20  includes a clock-based precharge p-type field effect transistor (precharge PFET  21 ), wherein its gate is connected to input clock  24 , its source terminal is connected to voltage source, V DD    22 , and its drain terminal is connected to storage node  23 . OR circuit  20  also includes a pull-down n-type field effect transistor(s) (pulldown NFET  25 ), which generally comprises one or more NFETs in parallel with one another, wherein the drain terminals are connected to storage node  23 .  
         [0025]    Dynamic circuits usually have two processing phases: the precharge phase and the evaluation phase. These processing phases may be emulated via OR circuit  20  in FIG. 2. The precharge phase of OR circuit  20  occurs when input clock  24  is in a low state, i.e., precharge PFET  21  is turned on, which in turn charges storage node  23 . Holder PFET  28  assists in maintaining the charge of storage node  23 . The evaluation phase occurs when input clock  24  is in a high state and precharge PFET  21  is turned off. Although it is not necessary, pull-down NFET  25  may be turned on during the evaluation phase. When on, pull-down NFET  25  provides a path for the charge stored in storage node  23  to be pulled down to ground  26 .  
         [0026]    Forward inverter  27  drives the correct logic value of holder PFET  28  gate to the rest of the circuitry via output  29 . Forward inverter  27  will output the opposite value of storage node  23 . For example, if storage node  23  is a 1, the inverter will put a 0 onto the gate of holder PFET  28 ; thereby, turning it on and helping maintain the charge on storage node  23 . As storage node  23  goes to 0, the input to forward inverter  27  is switched to 0; thereby causing its output to change from 0 to 1. This also causes the value at holder PFET  28  gate to be 1. As a result, the holder PFET  28  is turned off, allowing the storage node  23  to go completely to 0.  
         [0027]    [0027]FIG. 3 is a circuit diagram representation of an OR logic circuit with a DNG FET in accordance with an embodiment of the present invention. The DNG FET, also referred to as a clock FET or foot FET, is typically an n-channel device at the bottom of the pull-down tree whose gate is connected to a precharge clock (CLK  34 ), preventing a stack or row of FETs with static inputs from pulling down during the precharge phase. DNG is ground (GND) spelled backwards. Similar to OR circuit  20  depicted in FIG. 2, DNG-OR circuit  30  includes clock-based precharge PFET  31 , voltage source  32 , storage node  33 , one or more pull-down NFET(s) (pull-down NFET  35 ), forward inverter  38 , and holder PFET  39 . However, unlike OR circuit  20  of FIG. 2, DNG-OR circuit  30  contains DNG FET  36 , which is shown in FIG. 3 as an NFET transistor, wherein the gate terminal is connected to clock  34  and the source is connected to ground  37 . OR circuit  20  generally has more noise immunity than DNG-OR circuit  30  primarily because the body of pull-down NFET  35  is allowed to “float” up to V DD .  
         [0028]    The precharge and evaluation phases of DNG-OR circuit  30  are activated similar to OR circuit  20  of FIG. 2. When input clock  34  is low, precharge PFET  31  is turned on and storage node  33  is charged to V DD , with the help of holder PFET  39 . DNG-FET  36  is off during the precharge phase. The evaluation phase occurs when input clock  34  goes high. In this instant, the high clock state turns off precharge PFET  31  and may cause the DNG-FET  36  to bring storage node  33  to ground  37  depending on the gate voltage of the pull-down FET(s).  
         [0029]    During the precharge phase, pull-down NFET  35  are typically in a low state. However, if pull-down NFET  35  is in a high state for some reason, such as if the transistor makes a late transition in a cycle, it could cause that NFET to remain on during a portion of the precharge phase. Because the NFET is turned on while storage node  33  is at V DD , the value at interstitial node (INT)  300  is V DD  minus some threshold voltage, V T . In this instant, there are diodes between the body and the drain terminal, and the body and the source terminal of pull-down NFET  35 . These diodes are created in pull-down NFET  35  because the body is a p-type material (body  108  of FIG. 1B) and the drain and the source terminals are n-type (source  109  and drain  110  of FIG. 1B). Consequently, there is a pn-junction between each of the two (i.e., the body and the drain, and the body and the source.) This creates a reverse-biased diode causing charge to leak on the body. This also triggers the body voltage to “float” high because there is a charge coming from both the source and the drain of the NFET(s) through the body.  
         [0030]    Both the OR circuit without DNG FET and the OR circuit with DNG FET logic circuits function as OR gates. When pull-down NFET  25  and  35  switch on, the current will pass through the pull-down NFET  25  and  35  to ground. Accordingly, the output will be in the high state. However, if pull-down NFET  25  and  35  are off, in this instance there is no connection to ground  26  and  37  and this portion of the circuit is off. As storage nodes  23  and  33  transition to the low state, outputs  29  and  301  of the circuit will be high. In contrast, when storage nodes  23  and  33  transition to the high state, outputs  29  and  301  will be low. Such functioning of pull-down NFET  25  and  35  act like an OR logic gate, wherein outputs, Y,  29  and  301  are of the value where Y=A+B.  
         [0031]    [0031]FIG. 4 is a circuit diagram representation of an AND logic circuit in accordance with an embodiment of the present invention. AND circuit  40  of FIG. 4 is similar to DNG-OR circuit  30  of FIG. 3. As in FIGS. 1 and 2, AND circuit  40  contains clock-based precharge PFET  42 , clock-based DNG FET  46 , holder PFET  49 , pull-down NFET  45 , storage node  43 , and inverter  48 . In one embodiment of the present invention, AND logic circuit has a precharge phase and an evaluation phase. As in FIGS. 2 and 3, the pre-charge phase begins when input clock  44  is in the low state. This turns on precharge PFET  42  and turns off pull-down NFET  45 . Holder PFET  49  assists in maintaining the charge of storage node  43 . Further, holder PFET  49  may assist in charging storage node  43  when forward inverter  48  switches to output logic value 1. The evaluation phase of AND circuit  40  occurs when input clock  44  is in the high state; thereby, turning off precharge PFET  42  and holder PFETs  49 . This turns on pull-down NFET  45 , which, in turn, might deplete the voltage in storage node  43  and bring its value to ground.  
         [0032]    AND logic circuit  40  functions as an AND logic gate, wherein output  400 , Y, is of the value where Y=A·CLK. Both pull-down NFET(s)  45  and DNG FET  46  are typically in the high state to allow the circuit to be evaluated. Accordingly, if either NFET  45  or DNG FET  46  are in the low state, the current will not pass to ground  47 , and the circuit will not be evaluated. It should be noted that in additional embodiments, instead of having DNG FET  46 , AND logic circuit  40  may have an additional variable input node, such as B, where Y=A·B.  
         [0033]    OR circuit  20 , DNG-OR circuit  30 , and AND circuit  40  of the present invention are preferably the optimal subset of logic circuits used to represent all dynamic circuit types.  
         [0034]    The OR circuit  20  is preferably used to represent wide gate-width OR circuits that have a single pull-down FET. When the widths of the individual pull down FETs are added together, an equivalent width for a single pull-down FET is obtained. In an embodiment of the present invention, the cumulative width of the pull-down FET(s) is then used to reference a table and obtain the corresponding holder FET width and FIR. As the sources of all pull-down FETs are tied directly to ground, the body of the pull-down FET(s) typically does not equal more than 0.5 V. Consequently, there will be less leakage current.  
         [0035]    Each of OR circuit  20 , DNG-OR circuit  30 , and AND circuit  40  of the present invention has individual body voltage variations. Consequently, when OR circuit  20 , DNG-OR circuit  30 , and/or AND circuit  40  are combined together to form a simulation circuit, the logic circuits adequately model the dynamic and static body voltage variations of a SOI-based dynamic circuit. The body voltage in OR circuit  30  (FIG. 3) reaches the highest body voltage, AND circuit  40  (FIG. 4) has the second highest, while DNG-OR circuit  20  (FIG. 2) achieves the lowest body voltage. As each logic circuit results in a different body voltage, the optimal dynamic circuit simulation can be achieved via a combination of the various OR circuit  20 , DNG-OR circuit  30 , and AND circuit  40  of the present invention.  
         [0036]    In OR circuit  20 , shown in FIG. 2, the body voltage is determined by the diodes existing between the body and drain terminal as well as the body and source terminal. The diode between the body and drain terminal is typically reversed biased. However, if the body ever gets above 0.5 V the diode between the body and source terminal is typically forward biased. As a result, the body-drain diode might raise the voltage of the body, yet, the body-source diode usually prevents it from exceeding 0.5V.  
         [0037]    In AND logic circuit  40 , depicted in FIG. 4, the body voltage is determined, at least in part, by the body-drain and body-source diodes as in OR circuit  20 . If the top pull-down NFET  45  were left on (i.e. the FET made a late transition), I NT  node  401  would be allowed to charge up to V DD  minus V T , resulting in generally no forward biased diode compressing the body voltage, and dumping charge onto the body; thus, allowing the body voltage to float near V DD . In this situation, before the circuit can be evaluated, the pull-down NFET(s) would typically need to make a low transition. As a result of pull-down NFET(s) making this low transition, the capacitive effect causes the body voltage to fall. Moreover, capacitance exists between the gate and the source, the gate and the body, and the source and the body.  
         [0038]    As the input (gate voltage) is lowered, the source voltage is also lowered, lowering the body voltage as well. Because this process generally causes the source voltage to be less than the body voltage, the combination of the n-type source, the p-type body, and the n-type drain form an n-p-n BJT, in which the body becomes the base of the BJT. With the body (base) voltage higher than the source (emitter) voltage, some parasitic BJT current leakage is observed from the storage node, as well as sub-threshold voltage resulting in a degradation of the storage node.  
         [0039]    DNG-OR circuit  30 , depicted in FIG. 3, has the highest body voltage. In DNG-OR circuit  30 , the body voltage is determined by the diodes as in OR circuit  20  and AND circuit  40 . However, just as in AND circuit  40 , if pull-down NFET  35  were left on (i.e. the FET made a late transition), I NT  node  300  would be allowed to charge up to V DD  minus V T , resulting in generally no forward biased diode compressing the body voltage, and dumping charge onto the body; thus, allowing the body voltage to float near V DD . However, DNG-OR circuit  30  differs from AND circuit  40 , as the sources of all pull-down NFETs are connected (i.e. pull-down NFETs in parallel), wherein the common node is I NT  node  300 . This configuration typically results in a large amount of capacitance on I NT  node  300 ; even larger capacitance than typically associated with the AND logic circuits. With this capacitance, as the gate makes a transition, it encounters a much more difficult time effecting/moving the source voltage (i.e., the voltage at I NT  node  300 ).  
         [0040]    [0040]FIG. 5 is a circuit schematic illustrating a wide gate width OR circuit and one possible corresponding model circuit generated according to one embodiment of the present invention. Wide OR circuit  500  may be represented by OR circuit  510 . The widths of pull-down FETs  501  gates may preferably be summed together and simulated with single pull-down FET  511  having a gate width equal to that sum. The user would preferably need only to sum the widths of pull-down FETs  501  and then consult generated design guideline tables to determine what size holder FET  512  should be. It should be noted that the design guideline tables may be generated using technology described in the co-pending, commonly assigned patent application entitled, “PROCESS AND SYSTEM FOR DEVELOPING DYNAMIC CIRCUIT GUIDELINES,” Ser. No. 10/XXX,XXX, attorney docket number 10014072-1.  
         [0041]    [0041]FIG. 6 is a circuit schematic illustrating a wide gate width OR circuit with a DNG FET and one possible corresponding model circuit generated according to one embodiment of the present invention. Wide OR circuit  600  with DNG FET  602  may be reduced and modeled by DNG-OR circuit  610 . Similar to the example illustrated in FIG. 5, the widths of pull-down FETs  601  may preferably be summed and the size of corresponding holder FET  612  may preferably be obtained from a table.  
         [0042]    [0042]FIG. 7 is a circuit schematic illustrating wide gate width AND/OR circuit  700  and one possible corresponding model circuit  710  generated according to one embodiment of the present invention. Just as in FIGS. 5 and 6, the widths of pull-down FET(s)  701  are summed and the corresponding holder FET  712  value(s) are obtained from a table. Further shown in FIG. 7 is one example of corresponding model circuit  710  that includes DNG FET  713  with clock  721  in place of the inputs shown with wide gate width AND/OR circuit  700 .  
         [0043]    [0043]FIG. 8 is a schematic illustrating a complex dynamic circuit gate and one possible corresponding model circuit generated according to one embodiment of the present invention. With complex gate  800  and its corresponding simulation circuit  8000 , the size of holder FET  802  is obtained by breaking complex gate  800  into each of model logic circuit subset elements  810 ,  820  and  830 . For each model logic circuit  810 ,  820 , and  830  the widths of pull-down FETs  811 ,  821 , and  831  are added together and the size of corresponding holder FET  812 ,  822  and  832  are preferably obtained from a table.  
         [0044]    The described embodiments of the present invention allow dynamic circuit designers to optimize the design of any dynamic circuit fabricated in SOI material. Therefore, instead of using only a single-circuit model, which would sacrifice performance characteristics for simplicity, or hand-designing each circuit, which is extremely costly, designers may preferably create and simulate circuit designs that balance the amount of expected leakage, and therefore, noise immunity, against the desired performance characteristics. Each of the three different model circuit types preferably reflect different amounts of body voltage, which effects the expected leakage and noise immunity, therefore, the best performance may be designed for the simplicity that could be achieved through the modeling process.