Abstract:
Disclosed is a temperature sensor for an integrated circuit having at least one field effect transistor (FET) having a polysilicon gate, in which a current and a voltage is supplied to the polysilicon gate, changes in the current and the voltage of the polysilicon gate are monitored, wherein the polysilicon gate of the at least one FET is electrically isolated from other components of the integrated circuit, and the changes in the current or voltage are used to calculate a change in resistance of the polysilicon gate, and the change in resistance of the polysilicon gate is used to calculate a temperature change within the integrated circuit.

Description:
FIELD OF THE INVENTION 
   The present invention relates to a temperature sensor embedded within a semiconductor circuit. 
   BACKGROUND OF THE INVENTION 
   High powered very large scale integration (VLSI) circuits are widely used in the electronics industry. Major uses include clock buffers, wordline drivers and I/O buffers. During their operation, VLSI circuits generate heat internally. This self-heating increases the junction temperature in the device, and can result in failure of the VLSI circuit. 
   Generally, VLSIs are comprised of a plurality of field effect transistors (FETs) laid out on a substrate.  FIG. 1  is a simplified diagram of an FET showing the self-heating. Shown in  FIG. 1  are channel  101 , gate  102 , oxide  103  and substrate  104 . Within the channel  101  to gate  102  junction, the self-heating is shown as bursts  105 . Points where the source voltage Vs, the drain voltage Vd, and the gate voltage Vg are also shown. As the voltages are applied to the source, gate and drain of the device, internal heating begins to occur. As shown in this simplified diagram, the self-heating bursts  105  are non-uniform and in their distribution and degree. 
     FIG. 2  is a schematic diagram illustrating a single finger VLSI circuit. Shown in  FIG. 2  is a single finger VLSI  201 . P junction FET (PFET)  202  and N junction FET (NFET)  203  comprise the VLSI  201  shown in  FIG. 2 . PFET  202  is comprised of a source  202   a , a drain  202   b , and a gate  202   c , and NFET  203  is comprised of a source  203   a , a drain  203   b , and a gate  203   c . Voltage (+V)  205  and Ground (GND)  206  are also depicted in  FIG. 2 . PFET  202  and NFET  203  are controlled through gate connector  204 . The gates and gate connector are shown in a hatched detail. The gate connector  204  extends horizontally between gates  202   c  and  203   c . The “single finger” structure of the VLSI  201  refers to the single vertical part of the gate  204 . As voltages are applied to the VLSI  201 , the regions about the PFET  202  and the NFET  203  will begin to generate heat due to the flow of current through each of the PFET  202  and NFET  203 . As stated earlier, this heat, if allowed to reach critical values, can deteriorate ideal operation or completely destroy the VLSI  201 . 
   Polysilicon, or polycrystalline silicon, has long been used as the conducting gate and gate connector material in MOSFET and CMOS processing technologies. For these technologies it is deposited using reactors at high temperatures. More recently, polysilicon is being used in very large scale integration (VLSI) electronics. The main advantage of polysilicon is that it allows more complex, high-speed circuitry to be created on the glass substrate. 
     FIG. 3  is a schematic diagram illustrating a multi-finger VLSI circuit. Shown in  FIG. 3  is a multi-finger VLSI  301 . A plurality of P junction FETs (PFETs)  302  and a plurality of N junction FETs (NFETs)  303  comprise the VLSI  301  shown in  FIG. 3 . Each PFET  302  is comprised of a source  302   a , a drain  302   b , and a gate  302   c , and each NFET  303  is comprised of a source  303   a , a drain  303   b , and a gate  303   c . Voltage (+V)  305  and Ground (GND)  306  are also depicted in  FIG. 3 . Each PFET  302  and each NFET  303  are controlled through gate connector  304 . The gates and gate connectors are shown in a hatched detail. The gate connector  304  extends horizontally between each of the FETs. Vout  307  is the output voltage points for the FETs. The “multi-finger” structure of the VLSI  301  refers to the plurality of  302   c  gates and plurality of  303   c  gates. As voltages are applied to the VLSI  301 , the regions about the PFETs  302  and the NFET  303  will begin to generate heat due to the flow of current through each of the PFETs  302  and NFETs  303 . As stated earlier, this heat, if allowed to reach critical values, can deteriorate ideal operation or completely destroy the VLSI  301 . 
   Currently, various models are utilized to estimate this internally generated heat. One such model is the Berkeley Short-channel IGFET Model for MOS transistors (BSIM). The BSIM and other design models approximate the internal operations of a circuit at a design stage. These models use know values and operating parameters of the circuit components to assist in the design of the final integrated circuit using highly mathematical statistical models. The BSIM in particular also includes statistical models to estimate the internal heating of the integrated circuit. Although the BSIM is a good method to approximate the internal temperature of the integrated circuit, using approximations and statistical models can only produce estimated results. 
   During the operational states of the circuits, the self-heating is also know to be non-uniform throughout the topology of the circuit. Again, only approximations and estimations are available to measure the differences in temperature occurring at these differing levels of the integrated circuit. As a result, the integrated circuits that are designed using the conventional methods cannot accurately account for the variations in temperature throughout the cross sections of the final integrated circuit product. 
   SUMMARY OF THE INVENTION 
   One of the main shortcomings of the conventional temperature measurement systems is their lack for accurately measuring the real-time internal temperature of an integrated circuit. There are no current solutions to this problem. 
   An object of the present invention is to substantially solve at least the above problems and/or disadvantages and to provide at least the advantages below. 
   Accordingly, an object of the present invention is to provide a system for measuring internal temperatures of high-powered VLSI circuits. 
   Another object of the present invention is to provide a system to assist in the design of integrated circuits independent of the conventional self-heating models. 
   Another object of the present invention is to provide a system to identify circuit topologies prone to self-heating. 
   A further object of the present invention is to provide a system to improve thermal model-to-hardware correlation. 
   It is still a further object of the present invention is to provide a system for assessing thermal impact on an integrated circuit device performance. 
   The above and other objects and aspects are made possible by a temperature sensor for an integrated circuit having at least one field effect transistor (FET) having a polysilicon gate, comprising means for supplying a current and a voltage to the polysilicon gate; and means for monitoring changes in the current and the voltage of the polysilicon gate, wherein the polysilicon gate of the at least one FET is electrically isolated from other components of the integrated circuit, and wherein the changes in the current or voltage are used to calculate a change in resistance of the polysilicon gate, and wherein the change in resistance of the polysilicon gate is used to calculate a temperature change within the integrated circuit. 
   Another object of the present invention is to embed a thermometer within on-chip clock buffers, I/O drivers, wordline drivers, latches, etc. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, aspects, and advantages of the present invention will be better understood from the following detailed description of preferred embodiments of the invention with reference to the accompanying drawings that include the following: 
       FIG. 1  is a simplified diagram of an FET showing the self-heating; 
       FIG. 2  is a schematic diagram illustrating a single finger VLSI circuit; 
       FIG. 3  is a schematic diagram illustrating a multi-finger VLSI circuit; 
       FIG. 4  is a schematic diagram of a multi-finger VLSI circuit according to an embodiment of the present invention; 
       FIG. 5  is a chart illustrating the effect of multiple active fingers; 
       FIG. 6  is a graph illustrating the die-to-die variation when only the sensor is active; 
       FIG. 7  is a graph illustrating the thermal resistance of a NFET versus a PFET; 
       FIG. 8  illustrates four different thermal resistances versus conductivity graphs; 
       FIG. 9  is a graph illustrating performance versus temperature of a clock buffer; 
       FIG. 10  is a graph illustrating performance versus temperature; and 
       FIG. 11  is a diagram illustrating an integrated circuit configuration for determining the temperature at sub-threshold operating conditions according to additional embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
   Several preferred embodiments of the present invention will now be described in detail herein below with reference to the annexed drawings. In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings. In the following description, a detailed description of known functions and configurations incorporated herein has been omitted for conciseness. 
   One of the main shortcomings of the conventional temperature measurement systems is their lack for accurately measuring real-time internal temperatures at varying layers of an integrated circuit. The novel system for measuring internal temperatures of high-powered VLSI circuits disclosed herein provides a solution for these shortcomings. 
   As stated earlier, self-heating in integrated circuits intricately affects the design, construction and performance of the final product. Great amounts of time and money are spent correcting and preventing the failures of the integrated circuits due to the internal heating. Complex cooling apparatus are used as a heating prevention method, but these cooling apparatus are not accurately targeted to the specific heating zones of the integrated circuit since, prior to the present invention, not accurate measurement system was available. 
     FIG. 4  is a schematic diagram of a multi-finger VLSI circuit according to an embodiment of the present invention. Shown in  FIG. 4  is a multi-finger VLSI  401 . A plurality of P junction FETs (PFETs)  402  and a plurality of N junction FETs (NFETs)  403  comprise the VLSI  401  shown in  FIG. 4 . Each PFET  402  is comprised of a source  402   a , a drain  402   b , and a gate  402   c . Each NFET  403  is comprised of a source  403   a , a drain  403   b , and a gate  403   c . Voltage (+V)  405  and Ground (GND)  406  are also depicted in  FIG. 4 . Each gate of each PFET  402  and each NFET  403  are controlled through gate connector  404 . The gates and gate connector are shown in a hatched detail. The gate connector  404  connects to each gate of the PFETs  402  and NFETs  403 , and extends horizontally between them. Vout  407  is the output voltage points for the FETs. Additionally shown in  FIG. 4  are PFET  420 , comprised of a source  420   a , a drain  420   b , and a gate  420   c , and NFET  430 , comprised of a source  430   a , a drain  430   b , and a gate  430   c.    
   As can be seen in  FIG. 4 , each of gate  420   c  and gate  430   c  has been isolated from the gate connector  404 . Also each end of gates  420   c  and  430   c  has been extended by gate extenders  443 ,  444 ,  453  and  454 . Connected to gate extender  444  is a probe point  441 , and connected to gate extender  443  is a probe point  442 . Connected to gate extender  454  is a probe point  451 , and connected to gate extender  453  is a probe point  452 . Gate  420   c  and gate extenders  443  and  444 , comprise temperature sensor  440 . Gate  430   c  and gate extenders  453  and  454 , comprise temperature sensor  450 . PFET  420  and NFET  430  become inactive when their respective gates  420   c  and  430   c  are utilized as temperature sensors. This loss of a single PFET and a single NFET in the VLSI  401  produces a minimal impact on the operation of the VLSI  401 , but greatly increases the use of the gates for the temperature sensors. 
   The operation of a temperature sensor according to the present invention will now be described with reference to  FIG. 4 . The following description of the present invention will be limited to temperature sensor  440 , although the description also applies to temperature sensor  450 . 
   It is well known in the art that the electrical resistance of a conductor changes with temperature. The 3-dimensional Poisson&#39;s equation
 
∇λ∇ T+q= 0  (1)
 
where T is the temperature, q is the heat/volume, and λis the thermal conductivity, can be used to analyze and determine the temperature change. By determining the thermal conductivity of the isolated gate finger, i.e. gate  420   c , the change in temperature can be calculated, by solving Equation (1) for T
 
   
     
       
         
           
             
               
                 
                   ∇ 
                   T 
                 
                 = 
                 
                   
                     - 
                     q 
                   
                   
                     ∇ 
                     λ 
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   The probe points  441  and  442  provide access points to the temperature sensor  440  to supply a voltage and a current through the gate  420   c  of the temperature sensor  440 , and measure the voltage across the temperature sensor  440 , and measure the current through the temperature sensor  440 . The resistance of the temperature sensor  440  is calculated by the following Equation 3 
                 R   =     V   I             (   3   )               
where R is the calculated resistance, V is the measured voltage, and I is the measured current.
 
   There are two methods for calibrating the temperature sensor  440 . First, the resistance of the temperature sensor  440  can be calibrated as a function of the chuck temperature. Second, the resistance of the temperature sensor  440  can be calibrated as a function of the sub-threshold leakages. Whichever method is utilized, and other calibration techniques are of course contemplated, a calibration of the temperature sensor is needed to ensure proper temperature measurements. 
   Four main temperature test procedure modes are available through the use of the novel temperature sensor disclosed herein. The four modes are as follows: mode 1—all gates active (i.e. all of the gates and the temperature sensor (i.e. the gates  420   c  and  430   c  of the temperature sensors  440  and  450 , respectively) are active); mode 2—only the temperature sensor is active; mode 3—all gates are active and the temperature sensor is inactive; and mode 4—all gates inactive (all gates and the temperature sensor are inactive). The temperature sensor gate is considered inactive when no current or voltage is introduced through its gate element. Each of the four modes of operation will now be described in further detail. Mode 1 determines the temperature of the integrated circuit while all of the gates of all of the PFETs and NFETs are active, and the temperature sensor is active. This first mode of all gates active determines the highest level of internal heating that will occur in the integrated circuit. Mode 2 determines the internal heat generated while only the temperature sensor gate is active, and can be used as a calibration temperature. Mode 3 measures the current and voltage of the temperature sensor while all of the other gates are active, but no current and voltage is being applied to the temperature sensor. This mode allows for any leakage currents and voltages to be measured, and can be used in calibration procedures. Mode 4 measures the current and voltage of the temperature sensor while all of the gates are inactive, including the temperature sensor gate. 
   In addition to the above embodiment of the present invention, temperature measurements attained through the determination of sub-threshold leakage currents can also be obtained using the temperature sensor according to the embodiment of the present invention. The leakages through these devices can be measured using a similar four pad temperature sensor structure as previously described. It is well known that the sub-threshold current leakages of integrated circuit elements are related to the temperature, as shown by the following Equation 4
 
 I=I   0 ( e   (Vq/kT) −1)  (4)
 
where V is the applied voltage, T is the temperature, q is the electron charge, and I 0  is the saturation current. The current-voltage characteristics can be obtained for the leakages and the temperature can be extrapolated from the obtained leakage characteristics especially from the sub-threshold leakages.
 
     FIG. 11  is a diagram illustrating an integrated circuit configuration for determining the temperature at sub-threshold operating conditions according to additional embodiments of the present invention. Many of the elements shown in  FIG. 11  are similar to those in  FIG. 4 , and as such, the duplicative elements will not be described herein. Integrated circuit  1101  is shown in  FIG. 11 . In addition to the embodiment shown in  FIG. 4 , two additional embodiments are shown in  FIG. 11 ; a second embodiment for determining the sub-threshold leakage current between the sources and the drains of the FETs of the integrated circuit, and a third embodiment for determining the sub-threshold leakage current between a single source and a single drain of one FET of the integrated circuit. As will be shown and described, intermediate variations are contemplated, namely, the leakage current of any number of the FETs, from one to all, can be determined using this method. The temperature can then be determined from the slope of the plot of the Vq/kT term. 
   The new elements of the second embodiment include current pad  1102  and current pad  1103 . By placing the FETs into a sub-threshold state by applying the proper voltages to Voltage  405  and Vout  40 , the sub-threshold leakage current between the sources and the drains can be measured at pads  1102  and  1103 . Then the temperature can be determined by calculating the slope of the line formed by the plot of Vq/kT. 
   The third embodiment PFET  1110  is shown comprising source  1110   a , drain  1110   b , and gate  1110   c . Generally, it is noted that PFET  1100  has been electrically isolated from Voltage  405  and Vout  407 . Connected to source  1110   a  is pad  1104 , and connected to drain  1110   b  is pad  1105 . In this embodiment, the leakage current of the single PFET  1110  can be determined by placing the PFET  1110  into a sub-threshold state by applying the proper voltages to pads  1104  and  1105 , the sub-threshold leakage current between the source  1110   a  and the drain  1110   b  can be measured at pads  1104  and  1105 . Then the temperature can be determined by calculating the slope of the line formed by the plot of Vq/kT. 
     FIG. 5  is a chart illustrating the effect of multiple active fingers. Shown in  FIG. 5  are the junction and layer M 1  temperature rises. As can be seen, an increase in the active number of fingers increases the junction temperature. Also, a close thermal coupling between the fingers within the same body increases the thermal resistance by three times. 
     FIG. 6  is a graph illustrating the die-to-die variation when only the sensor is active. As the power increases, the temperature change increases almost linearly. 
   The following tables illustrate thermal resistance data as determined according to the present invention. In the following tables, the temperature sensors are located at two different FET locations, and listed in the tables as “1”or “2”. Also, the conditions of the device are as follows: “A” denotes that only the sensor gate is active during temperature measurements; “B” denotes that all of the gates are active during temperature measurements; and “C” denotes that all of the gates except for the sensor gate are active during temperature measurements. 
   
     
       
             
             
             
             
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
                 
               0.13 micron 
               0.09 micron 
                 
                 
             
             
               Gate 
               technology 
               technology 
               0.09 
               0.09 
             
             
               Conditions 
               (degrees C/mW) 
               (degrees C/mW) 
               micron 
               micron 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               1A 
               18.5 
               24.2 
             
             
               1B 
               4.9 
               5.8 
             
             
               1C 
               2.6 
               2.6 
             
             
               2A 
               16.1 
               22.6 
               39 
               41 
             
             
               2B 
               2.0 
               1.8 
               4.4 
               4.7 
             
             
               2C 
               1.1 
               0.9 
                 
               3.2 
             
             
                 
             
           
        
       
     
   
   
     
       
             
             
             
           
             
             
             
           
         
             
               TABLE 2 
             
             
                 
             
             
                 
               0.13 micron 
               0.09 micron 
             
             
               Gate 
               technology (degrees 
               technology (degrees 
             
             
               Conditions 
               C-micrometer/mW) 
               C-micrometer/mW) 
             
             
                 
             
           
           
             
                 
             
           
        
         
             
               1A 
               49.40 
               64.61 
             
             
               1B 
               104.66 
               123.89 
             
             
               1C 
               48.59 
               48.59 
             
             
               2A 
               42.99 
               60.34 
             
             
               2B 
               149.52 
               134.57 
             
             
               2C 
               79.30 
               64.88 
             
             
                 
             
           
        
       
     
   
     FIG. 7  is a graph illustrating the thermal resistance of a NFET versus a PFET. During the temperature measurements, only the sensor gate was active. Also, the gate, the source and the drain voltages were all equal. 
     FIG. 8  illustrates four different thermal resistances versus conductivity graphs. Diagram (a) of  FIG. 8  illustrates the thermal resistance based on the temperature of the sensor versus standard test data of 0.13 micron technology. Diagram (b) of  FIG. 8  illustrates the thermal resistance based on the temperature of the sensor versus standard test data of 0.09 micron technology. Diagram (c) of  FIG. 8  illustrates the thermal resistance ratios of the temperature of the sensors in an all on versus only the sensor on of 0.13 micron technology. Diagram (d) of  FIG. 8  illustrates the thermal resistance of maximum versus sensor readings of 0.13 micron technology. 
     FIG. 9  is a graph illustrating performance versus temperature of a clock buffer. The graph is shown scaled to a bilk performance at 25 degrees Celsius. The performance gain of the SOI is 20% greater than the bulk. The performance change is 1.2% per 10 degrees Celsius for the SOI, and 1.32% per 10 degrees Celsius for the bulk. 
     FIG. 10  is a graph illustrating performance versus temperature. As can be seen the delay increases as the temperature increases of the two technologies shown in  FIG. 10 . 
   Similar methodology, that is a four point probe structure at the end of metal lines wherein the two top pads are used for voltage and current and the two bottom pads are used for voltage and current, can be used for measuring the temperature of metal lines by calibrating the resistance of the metal lines connected to a device or a circuit. 
   Also in both methodologies individual devices can be separated in the multifinger topology and source and drain current can be separately tapped off in the sub-threshold regime. The spacing of the devices can also be varied to study the temperature rise based on the leakage data based on various spacing designs. 
   It is also contemplated that both of the structures can be used in planar or in 3-D plane topology. 
   In summary, the present invention provides a system for measuring internal temperatures of high-powered VLSI circuits, can vitally assist in the design of integrated circuits independent of the conventional self-heating models, is able to identify circuit topologies prone to self-heating, can improve thermal model-to-hardware correlation, enables the assessing thermal impact on an integrated circuit device performance, can greatly assist in the design of integrated circuits independent of the conventional self-heating models, and can greatly improve the thermal model-to-hardware correlation. 
   While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.