Abstract:
A sense amplifier flip flop comprises a pre-charging portion connected between a first power voltage and first and second nodes and pre-charging the first and second nodes to a predetermined voltage in response to a clock signal, a differential input portion connected between a second power voltage and third and fourth nodes and receiving an input signal and an inverted input signal to generate a voltage difference between the input signal and the inverted input signal to the third and fourth nodes in response to the clock signal, a differential amplifying portion including a first inverter which includes a first pull-up transistor and a first pull-down transistor serial-connected between the first power voltage and the third node and inverts a signal of the second node to be outputted to the first node and a second inverter which includes a second pull-up transistor and a second pull-down transistor serial-connected between the first power voltage and the fourth node and inverts a signal of the first node to be outputted to the second node, amplifying the voltage difference between the third and fourth nodes, and applying first and second body bias voltages to the first and second pull-up transistors, a bias voltage generating portion generating the first and second bias voltages for adjusting an offset of an electric current flowing through the third and fourth nodes, and a latch portion for latching signals of the first and second nodes to output an output signal and an inverted output signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of Korean Patent Application No. 2006-0010881, filed Feb. 3, 2006, the disclosure of which is hereby incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    This disclosure relates to a sense amplifier flip flop and, more particularly, to a sense amplifier flip flop which adjusts an offset. 
         [0004]    2. Description of the Related Art 
         [0005]    A system which performs an input or output operation at high speeds has many important parts. However, an input/output portion is one of the parts which critically affect a performance of the system. Among such an input/output portion, a flip flop exactly receives an input signal and samples it. 
         [0006]    A semiconductor memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) includes a data input buffer which detects an externally input data signal and buffers it at a predetermined level for matching logic levels within its memory cells and a latch which continuously maintains data input from an external portion until the data is transmitted to the memory cell. 
         [0007]      FIG. 1  is a circuit diagram illustrating a first conventional sense amplifier flip flop. A pre-charging portion  10  includes a PMOS transistor P 1  connected between a power voltage Vdd and a first node Node 1  and a PMOS transistor P 2  connected between a power voltage Vdd and a second node Node 2 . The PMOS transistors P 1  and P 2  receive a clock signal CLK through their gates and are turned on to pre-charge the first and second nodes Node 1  and Node 2  when the clock signal CLK having a low level is applied, respectively. 
         [0008]    A differential input portion  20  includes an NMOS transistor N 1  which is connected between a common node NodeC and a ground voltage Vss and serves as a switch for driving the differential input portion  20  in response to the clock signal CLK, an NMOS transistor N 2  connected between a third node Node 3  and the common node NodeC to receive an input signal D, and an NMOS transistor N 3  connected between a fourth node Node 4  and the common node NodeC to receive an inverted input signal DB. When the clock signal having a high level is applied, the NMOS transistor N 1  is turned on, so that the differential input portion  20  receives the input signal D and the inverted input signal DB, respectively, through the NMOS transistors N 2  and N 3  to detect a voltage difference between the input signal D and the inverted input signal DB. 
         [0009]    A differential amplifying portion  30  includes two inverters, i.e., first and second inverters  30 - 1  and  30 - 2  respectively connected between the power voltage Vdd and the third and fourth nodes Node 3  and Node 4 . An input of the first inverter  30 - 1  is connected to the node Node 2 , and an input of the second inverter  30 - 2  is connected to the first node Node 1 . 
         [0010]    The differential amplifying portion  30  amplifies the voltage difference between the input signal D and the inverted input signal DB, detected by the differential input portion  20 , to output a differential signal Mout and an inverted differential signal MoutB respectively to the first and second nodes Node 1  and Node 2 . 
         [0011]    A latch portion  40  includes two NAND gates  40 - 1  and  40 - 2 . The first NAND gate  40 - 1  receives the differential signal Mout and an inverted output signal QB, i.e., an output of the second NAND gate  40 - 2  to output an output signal Q, and the second NAND gate  40 - 2  receives the inverted differential signal MoutB and an output signal Q, i.e., an output of the first NAND gate  40 - 1  to output an inverted output signal QB. 
         [0012]    The latch portion  40  latches the differential signal Mout and the inverted differential signal MoutB as an SR latch to output the output signal Q and the inverted output signal QB. 
         [0000]    
       
         
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
             
             
               
                 CLK(L) 
                 D 
                 Mout 
                 MoutB 
                 Q 
               
               
                   
                 X 
                 1 
                 1 
                 Hold 
               
               
                 CLK(H) 
                 H 
                 0 
                 1 
                 0 
               
               
                   
                 L 
                 1 
                 0 
                 1 
               
               
                   
               
             
          
         
       
     
         [0013]    Table 1 is a truth table of the sense amplifier flip flop of  FIG. 1 . An operation of the sense amplifier flip flop is described below with reference to  FIG. 1  and Table 1. When the clock signal CLK having a low level is applied, the PMOS transistors P 1  and P 2  of the pre-charging portion  10  are turned on, and the NMOS transistor N 1  of the differential input portion  20  is turned off. As a result, the power voltage Vdd is applied to the first and second nodes Node 1  and Node 2 , and the differential signal Mout and the inverted differential signal MoutB, each having a high level are applied to the latch portion  40 . The latch portion  40  by the nature of the SR latch maintains the output signal Q and the inverted output signal QB “as is” in a previous state when the differential signal Mout and the inverted differential signal MoutB both have a high level. At the same time, the pre-charging portion  10  pre-charges the first and second nodes Node 1  and Node 2 . 
         [0014]    When the clock signal CLK having a high level is applied, the PMOS transistors P 1  and P 2  of the pre-charging portion  10  are turned off, and the NMOS transistor N 1  of the differential input portion  20  is turned on. 
         [0015]    When the input signal D having a high level is applied to the differential input portion  20 , the NMOS transistor N 2 , which receives the input signal D, is turned on, and the NMOS transistor N 3 , which receives the inverted input signal DB, is turned off. 
         [0016]    When the NMOS transistor N 2  of the differential input portion  20  is turned on, since the first and second nodes Node 1  and Node 2  have been pre-charged, the NMOS transistor N 4  of the first inverter  30 - 1  of the differential amplifying portion  30  is also turned on. As a result, a voltage level of the first node Node 1  is lowered. When the voltage level of the first node Node 1  is lowered, the PMOS transistor P 3  is turned off. As a result, the differential signal Mout transitions to a low level, and is output to the latch portion  40 . 
         [0017]    In contrast, the NMOS transistor N 3  of the differential input portion  20  and the NMOS transistor N 5  of the second inverter  30 - 2  are turned off, and the PMOS transistor P 4  is turned on. As a result, the second node Node 2  is maintained at a pre-charged voltage level, and the inverted differential signal MoutB transitions to a high level and is output to the latch portion  40 . 
         [0018]    The latch portion  40  outputs the output signal Q having a low level and the inverted output signal QB having a high level when the differential signal Mout transitions to a low level and the inverted differential signal MoutB transitions to a high level. 
         [0019]    When the input signal D having a low level is applied to the differential input portion  20 , the NMOS transistor N 2 , which receives the input signal D, is turned off, and the NMOS transistor N 3 , which receives the inverted input signal DB, is turned on. 
         [0020]    When the NMOS transistor N 3  of the differential input portion  20  is turned on, since the first and second nodes Node 1  and Node 2  have been pre-charged, the NMOS transistor N 5  of the second inverter  30 - 2  of the differential amplifying portion  30  is also turned on. As a result a voltage level of the second node Node 2  is lowered. When the voltage level of the second node Node 2  is lowered, the PMOS transistor P 4  is turned off, so that the inverted differential signal MoutB transitions to a low level and then is output to the latch portion  40 . 
         [0021]    In contrast, the NMOS transistor N 2  of the differential input portion  20  and the NMOS transistor N 4  of the first inverter  30 - 1  are turned off, and the PMOS transistor P 3  is turned on. As a result, the first node Node 1  is maintained at the pre-charged voltage level, and the differential signal Mout transitions to a high level and is output to the latch portion  40 . 
         [0022]    The latch portion  40  outputs the output signal Q having a high level and the inverted output signal QB having a low level when the differential signal Mout transitions to a high level and the inverted differential signal MoutB transitions to a low level. 
         [0023]    That is, the first and second inverters  30 - 1  and  30 - 2  of the differential amplifying portion  30  are connected such that the inputs crosses the outputs of the other inverter and thus amplify and output a small voltage difference applied from the differential input portion  20 . 
         [0024]    The sense amplifier flip flop of  FIG. 1  has a structure including a master including the pre-charging portion  10 , the differential input portion  20 , and the differential amplifying portion  30  and a slave latch including of the latch portion  40 . There is an advantage in that the master is configured in the form of a differential amplifier and is capable of handling a signal level having small magnitude, and the slave latch can perform a stable high speed operation and thus can process an input signal level having small magnitude at a high speed. 
         [0025]    However, there is a disadvantage in that a voltage offset may occur as well. Such an offset may occur as a result of a processing error, a layout error, or mismatching of a threshold voltage Vth in the NMOS transistor. 
         [0026]      FIG. 2  is a circuit diagram illustrating a second conventional sense amplifier flip flop. The sense amplifier flip flop of  FIG. 2  includes multiple capacitors as a solution for resolving the offset problem. Capacitors C 11  to C 13  and C 21  to C 23  are respectively connected to the third and fourth nodes Node 3  and Node 4  to control an electric current which flowing from the differential amplifying portion  30  to the differential input portion  22  to thereby adjust the offset. 
         [0027]    When the input signal D and the inverted input signal DB each have a high level, there should be no voltage difference between the two signals D and DB. As a result, there should be no difference in the electric current which flows from the NMOS transistor N 4  through the third node Node 3  as compared with the electric current which flows from the NMOS transistor N 3  through the fourth node Node 4 . 
         [0028]    However, if it is assumed that an electric current I+I offset  which flows through the fourth node Node 4  is greater than an electric current I which flows through the third node Node 3  by the offset current I offset , the offset current I offset  is a cause of errors when the input signal is determined and thus should be offset. 
         [0029]    To this end, a predetermined number of capacitors among the capacitors C 21  to C 23  are connected to the fourth node Node 4 , enough to offset the offset current I offset  from the current I+I offset  which flows through the fourth node Node 4 . The remaining capacitor(s) and the capacitors C 11  to C 13  connected to the third node Node 3  are disconnected by fuse cutting. For example, if the offset current offset is offset by the capacitor  21 , the remaining capacitors C 11  to C 13 , C 22 , and C 23  are disconnected by fuse cutting. 
         [0030]      FIG. 3  is a circuit diagram illustrating a third conventional sense amplifier flip flop. In  FIG. 3 , as a method for resolving the offset problem, NMOS transistors N 2 , N 21 , N 22 , N 3 , N 31 , and N 32  are arranged in the differential input portion  24 . 
         [0031]    The sense amplifier flip flop of  FIG. 2  reduces the offset current I offset  to adjust the offset, whereas the sense amplifier flip flop of  FIG. 3  allows the current I flowing through the third node Node 3  to increase by the offset current I offset  to adjust the offset. 
         [0032]    If it is assumed that an electric current I+I offset , which flows through the fourth node Node 4 , flows by the offset current I offset  more than an electric current (I), which flows through the third node Node 3 , as in  FIG. 2 , a predetermined number of NMOS transistors are remain connected to allow a greater electric current to flow to the NMOS transistor N 2  side connected to the third node Node 3 . The remaining NMOS transistors are disconnected by fuse cutting. 
         [0033]    For example, if an additional electric current that is as much as the offset current I offset  flows to the third node Node 3  due to the NMOS transistor N 21 , the remaining transistors N 22 , N 31 , and N 32  are disconnected by fuse cutting. 
         [0034]    Similarly to the circuit of  FIG. 3 , If it is assumed that an electric current I+I offset , which flows through the fourth node Node 4 , flows by the offset current I offset  more than an electric current (I), which flows through the third node Node 3 , it is possible to make an electric current flow more to the NMOS transistor N 2  side by increasing the size of the NMOS transistor N 2 . 
         [0035]    Unfortunately, in adjusting the offset of the sense amplifier flip flops shown in  FIGS. 2 and 3 , multiple capacitors or transistors are required, and thus there is a disadvantage in that it is not easy to design and the layout area size of the sense amplifier flip flop is increased. In addition, a process for blowing off the fuses to adjust the offset is needed. 
       SUMMARY 
       [0036]    It is an object of the present invention to provide a sense amplifier flip flop which easy adjusts the offset. 
         [0037]    One aspect of the present invention is to provide a sense amplifier flip flop, comprising: a pre-charging portion connected between a first power voltage and first and second nodes and pre-charging the first and second nodes to a predetermined voltage in response to a clock signal, a differential input portion connected between a second power voltage and third and fourth nodes and receiving an input signal and an inverted input signal to generate a voltage difference between the input signal and the inverted input signal to the third and fourth nodes in response to the clock signal, a differential amplifying portion including a first inverter which includes a first pull-up transistor and a first pull-down transistor serial-connected between the first power voltage and the third node and inverts a signal of the second node to be outputted to the first node and a second inverter which includes a second pull-up transistor and a second pull-down transistor serial-connected between the first power voltage and the fourth node and inverts a signal of the first node to be outputted to the second node, amplifying the voltage difference between the third and fourth nodes, and applying first and second body bias voltages to the first and second pull-up transistors, a bias voltage generating portion generating the first and second bias voltages for adjusting an offset of an electric current flowing through the third and fourth nodes, and a latch portion for latching signals of the first and second nodes to output an output signal and an inverted output signal. 
         [0038]    The bias voltage generating portion includes a plurality of resistors and a plurality of output nodes between a third power voltage having a higher level than or equal level to the first power voltage and a fourth power voltage having a level between the first power voltage and the second power voltage, and the first and second body bias voltages are selected in the plurality of output nodes and then outputted. 
         [0039]    Another aspect of the present invention is to provide a sense amplifier flip flop, comprising: a pre-charging portion connected between a first power voltage and first and second nodes and pre-charging the first and second nodes to a predetermined voltage in response to a clock signal, a differential input portion connected between a second power voltage and third and fourth nodes and receiving an input signal and an inverted input signal to generate a voltage difference between the input signal and the inverted input signal to the third and fourth nodes in response to the clock signal, a differential amplifying portion including a first inverter which includes a first pull-up transistor and a first pull-down transistor serial-connected between the first power voltage and the third node and inverts a signal of the second node to be outputted to the first node and a second inverter which includes a second pull-up transistor and a second pull-down transistor serial-connected between the first power voltage and the fourth node and inverts a signal of the first node to be outputted to the second node, amplifying the voltage difference between the third and fourth nodes, and applying first and second body bias voltages to the first and second pull-down transistors, a bias voltage generating portion generating the first and second bias voltages for adjusting an offset of an electric current flowing through the third and fourth nodes, and a latch portion for latching signals of the first and second nodes to output an output signal and an inverted output signal. 
         [0040]    The bias voltage generating portion includes a plurality of resistors and a plurality of output nodes between a third power voltage having a lower level than or equal level to the second power voltage and a fourth power voltage having a level between the first power voltage and the second power voltage, and the first and second body bias voltages are selected in the plurality of output nodes and then outputted. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0041]    The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing embodiments in detail with reference to the attached drawings in which: 
           [0042]      FIG. 1  is a circuit diagram illustrating a first conventional sense amplifier flip flop; 
           [0043]      FIG. 2  is a circuit diagram illustrating a second conventional sense amplifier flip flop; 
           [0044]      FIG. 3  is a circuit diagram illustrating a third conventional sense amplifier flip flop; 
           [0045]      FIG. 4  is a circuit diagram illustrating a sense amplifier flip flop according to a first embodiment; 
           [0046]      FIG. 5  is a circuit diagram illustrating a first bias voltage generating portion which generates the first and second body bias voltages of  FIG. 4 ; 
           [0047]      FIG. 6  is a circuit diagram illustrating a sense amplifier flip flop according to a second embodiment; 
           [0048]      FIG. 7  is a circuit diagram illustrating a second bias voltage generating portion which generates the third and fourth body bias voltages of  FIG. 6 ; and 
           [0049]      FIG. 8  is a circuit diagram illustrating a sense amplifier flip flop according to a third embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0050]    Embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, embodiments may take different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the following claims to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification. 
         [0051]      FIG. 4  is a circuit diagram illustrating a sense amplifier flip flop according to a first embodiment, Referring to  FIG. 4 , a pre-charging portion  10  includes a PMOS transistor P 1  coupled between a power voltage Vdd and a first node Node 1 , and a PMOS transistor P 2  coupled between a power voltage Vdd and a second node Node 2 . The PMOS transistors P 1  and P 2  receive a clock signal CLK through their gates and are configured to turn on to pre-charge the first and second nodes Node 1  and Node 2 , respectively, when the clock signal CLK having a low level is applied. 
         [0052]    A differential input portion  20  includes an NMOS transistor N 1  coupled between a common node NodeC and a ground voltage Vss, and serving as a switch for driving the differential input portion  20  in response to the clock signal CLK, an NMOS transistor N 2  coupled between a third node Node 3  and the common node NodeC to receive an input signal D, and an NMOS transistor N 3  coupled between a fourth node Node 4  and the common node NodeC to receive an inverted input signal DB. When the clock signal CLK having a high level is applied, the NMOS transistor N 1  is turned on, so that the differential input portion  20  receives the input signal D and the inverted input signal DB, respectively, through the NMOS transistors N 2  and N 3  to detect a voltage difference between the input signal D and the inverted input signal DB. 
         [0053]    A differential amplifying portion  32  includes two inverters, i.e., first and second inverters  32 - 1  and  32 - 2 . The inputs of the two inverters  32 - 1  and  32 - 2  are coupled to the outputs of the other inverters. The inverter  32 - 1  includes a PMOS transistor P 3  and an NMOS transistor N 4 , and the inverter  32 - 2  includes a PMOS transistor P 4  and an NMOS transistor N 5 . The PMOS transistor P 3  is coupled between the power voltage and the first node Node 1 , and the PMOS transistor P 4  is coupled between the power voltage and the second node Node 2 . The NMOS transistor N 4  is coupled between the first node Node 1  and the third node Node 3 , and the NMOS transistor N 5  is coupled between the second node Node 2  and the fourth node Node 4 . 
         [0054]    Gates of the PMOS transistor P 3  and the NMOS transistor N 4  of the first inverter  32 - 1  are commonly coupled to the second node Node 2 , and gates of the PMOS transistor P 4  and the NMOS transistor N 5  of the second inverters  32 - 2  are commonly coupled to the first node Node 1 . The PMOS transistor P 3  receives a first body bias voltage Vbias 1  through its body, and the PMOS transistor P 4  receives a second bias body voltage Vbias 2  through its body. The first and second body bias voltages Vbias 1  and Vbias 2  change the threshold voltages of the PMOS transistors P 3  and P 4  respectively to adjust the offset between the electric current which flows through the third node Node 3  and the electric current which flows through the fourth node Node 4 . 
         [0055]    The differential amplifying portion  30  amplifies the voltage difference between the input signal D and the inverted input signal, detected by the differential input portion  20 , to output a differential signal Mout and an inverted differential signal MoutB respectively to the first and second nodes Node 1  and Node 2 . 
         [0056]    A latch portion  40  includes two NAND gates  40 - 1  and  40 - 2 . The first NAND gate  40 - 1  receives the differential signal Mout and an inverted output signal QB, i.e., an output of the second NAND gate  40 - 2  to output an output signal Q, and the second NAND gate  40 - 2  receives the inverted differential signal MoutB and an output signal Q, i.e., an output of the first NAND gate  40 - 1  to output an inverted output signal QB. 
         [0057]    The latch portion  40  latches the differential signal Mout and the inverted differential signal MoutB as an SR latch to output the output signal Q and the inverted output signal QB. 
         [0058]    An operation of the sense amplifier flip flop of  FIG. 4  is described below. When the clock signal CLK having a low level is applied, the PMOS transistors P 1  and P 2  of the pre-charging portion  10  are turned on, and the NMOS transistor N 1  of the differential input portion  20  is turned off. The NMOS transistors N 2  and N 3  of the differential input portion  20  and the PMOS transistors P 3  and P 4  and the NMOS transistors N 4  and N 5  of the differential amplifying portion  32  are also turned off, and the power voltage Vdd is applied to pre-charge the first and second nodes Node 1  and Node 2 . The latch portion  40  maintains the output signal Q and the inverted output signal QB in a previous state since the differential signal Mout and the inverted differential signal MoutB are output at a high level from the first and second nodes Node 1  and Node 2 . 
         [0059]    When the clock signal CLK having a high level is applied, the PMOS transistors P 1  and P 2  of the pre-charging portion  10  are turned off, and the NMOS transistor N 1  of the differential input portion  20  is turned on. 
         [0060]    When the NMOS transistor N 1  is turned on, the NMOS transistors N 2  and N 3  of the differential input portion  20  receive the input signal D and the inverted input signal DB via their gates so that the voltage difference between the two signals D and DB is detected. 
         [0061]    When the input signal D having a high level is applied to the gate of the NMOS transistor N 2 , the inverted input signal DB having a low level is applied to the gate of the NMOS transistor N 3 . As a result, the NMOS transistor N 2  is turned on, the NMOS transistor N 3  is turned off, the NMOS transistor N 4  of the differential amplifying portion  32  coupled to the NMOS transistor N 2  is turned on, and the voltage level of the first node Node 1  which is pre-charged is lowered. Thus, the NMOS transistor N 5  is turned off. 
         [0062]    Since the PMOS transistor P 3  is turned off, and the NMOS transistors N 1 , N 2  and N 4  are turned on, the voltage level of the first node Node 1  is lowered, so that the differential signal Mout is output at a low level. Also, since the PMOS transistor P 4  is turned on and the NMOS transistors N 3  and N 5  are turned off, the second node Node 2  is maintained at the pre-charged voltage level, so that the inverted differential signal MoutB is output at a high level. 
         [0063]    The latch portion  40  receives and latches the differential signal Mout output from the first node Node 1  and the inverted differential signal MoutB output from the second node Node 2  to output the output signal Q having a low level and the inverted output signal QB having a high level. 
         [0064]    When the input signal D having a low level is applied to the gate of the NMOS transistor N 2 , the inverted input signal DB having a high level is applied to the gate of the NMOS transistor N 3 . 
         [0065]    The NMOS transistor N 2  is turned off, and the NMOS transistor N 3  is turned on. Thus, the NMOS transistor N 4  of the differential amplifying portion  32  coupled to the NMOS transistor N 2  is turned off, and the NMOS transistor N 5  is turned on. When the NMOS transistor N 5  is turned on, the voltage level of the pre-charged second node Node 2  is lowered. 
         [0066]    With respect to the first node Node 1 , since the PMOS transistor P 3  is turned on and the NMOS transistors N 2  and N 4  are turned off, the pre-charged voltage level is maintained, and the differential signal Mout is output at a high level. 
         [0067]    With respect to the second node Node 2 , since the PMOS transistor P 4  is turned off and the NMOS transistors N 1 , N 3  and N 5  are turned on, the voltage level is lowered, and the inverted differential signal MoutB is output at a low level. 
         [0068]    The latch portion receives and latches the differential signal Mout output from the first node Node 1  and the inverted differential signal MoutB output from the second node Node 2  to output the output signal Q having a high level and the inverted output signal QB having a low level. 
         [0069]    However, the operation of the sense amplifier flip flop of  FIG. 4  described above is an operation of a case where there is no offset. In order to detect the offset of the sense amplifier flip flop of  FIG. 4 , if the current I+I offset  flowing through the fourth node Node 4  is greater than the current I flowing through the third node Node 3  by the offset current I offset  when the input signal D and the inverted input signal DB are respectively applied at a high level to the NMOS transistors N 2  and N 3 , the first body bias voltage Vbias 1  is applied to the PMOS transistor P 3  of the differential amplifying portion  32 , and the second body bias voltage Vbias 2  is applied to the PMOS transistor P 4 . The first and second body bias voltages Vbias 1  and Vbias 2  may be positive, and thus the threshold voltages of the PMOS transistors P 3  and P 4  are increased. As a result, the current which flows to the drains of the PMOS transistors P 3  and P 4  may be reduced. Since the current I+I offset  flowing through the fourth node Node 4  is greater by the offset current I offset , the second body bias voltage Vbias 2  is set to be higher than the first body bias voltage Vbias 1  so that the threshold voltage Vth of the PMOS transistor P 4  is higher than the threshold voltage Vth of the PMOS transistor P 3 . 
         [0070]    The threshold voltage of the NMOS transistor is increased in proportion to a square root of the body bias voltage. In a saturation region, the current flowing to the drain of the NMOS transistor is in proportion to the square of the threshold voltage Vth. 
         [0071]    Accordingly, the offset of the sense amplifier flip flop is adjusted by adjusting the first and second body bias voltages Vbias 1  and Vbias 2  respectively applied to the bodies of the PMOS transistors P 3  and P 4  of the differential amplifying portion  32 . 
         [0072]    In order to adjust the offset, the above-described embodiment applies the body bias voltages Vbias 1  and Vbias 2  respectively to the PMOS transistors P 3  and P 4 . However, the body bias voltage can be applied to only one of the PMOS transistors P 3  and P 4 . For example, the second body bias voltage Vbias 2  applied to the PMOS transistor P 4  is adjusted higher when the current flowing through the fourth node Node 4  is much, whereas the second body bias voltage Vbias 2  applied to the PMOS transistor P 4  is adjusted lower when the current flowing through the fourth node Node 4  is small. 
         [0073]      FIG. 5  is a circuit diagram illustrating a first bias voltage generating portion which generates the first and second body bias voltages of  FIG. 4 . 
         [0074]    In an embodiment, the first bias voltage generating portion includes a resistor network. The sense amplifier flip flop is part of a DRAM. The DRAM has an external voltage that is applied from an external portion, and an internal voltage that is internally generated. Here, a first external voltage Vext 1  is higher than a first internal voltage Vint 1 , and the power voltage Vdd of  FIG. 4  can be used as the first internal voltage Vint 1 . The first bias voltage generating portion includes multiple resistors R 11  to R 16  coupled between the first external voltage Vext 1  and the first internal voltage Vint 1  and outputs the bias voltage to output terminals A 11  to A 17  respectively coupled between the resistors R 11  to R 16 . 
         [0075]    Although the first external voltage Vext 1  has been described as higher than the first internal voltage Vint 1 , such voltages may have any relationship as desired to create the desired bias voltages. In addition, although the first external voltage Vext 1  has been described as being generated external to the DRAM, and the first internal voltage Vint 1  has been described as being internally generated, both voltages may be internally or externally generated as desired. 
         [0076]    The greater the number of the resistors arranged between the first external voltage Vext 1  and the first internal voltage Vint 1  is, the more precisely the voltage is adjusted. 
         [0077]    As a voltage used to adjust the offset of the sense amplifier flip flop of  FIG. 4 , the first body bias voltage Vbias 1  and the second body bias voltage Vbias 2  are selected in the output terminals A 11  to A 17  and then applied to the PMOS transistors P 3  and P 4 . 
         [0078]      FIG. 6  is a circuit diagram illustrating a sense amplifier flip flop according to a second embodiment. 
         [0079]    The sense amplifier flip flop of  FIG. 4  adjusts the offset by applying the first and second body bias voltages to the bodies of the PMOS transistors P 3  and P 4  of the differential amplifying portion  32 , whereas the sense amplifier flip flop of  FIG. 6  adjusts the offset by applying third and fourth body bias voltages to the bodies of the NMOS transistors N 4  and N 5  of the differential amplifying portion  34 . 
         [0080]    In order to detect the offset of the sense amplifier flip flop of  FIG. 6 , if the current I+I offset  flowing through the fourth node Node 4  is greater than the current I flowing through the third node Node 3  by the offset current I offset , when the input signal D and the inverted input signal DB are respectively applied at a high level to the NMOS transistors N 2  and N 3 , the third body bias voltage Vbias 3  is applied to the NMOS transistor N 4  of the differential amplifying portion  34 , and the fourth body bias voltage Vbias 4  is applied to the NMOS transistor N 5 . The third and fourth body bias voltages Vbias 3  and Vbias 4  may be negative, and the threshold voltages of the NMOS transistors N 4  and N 5  are increased, which reduces the current which flows to the sources of the NMOS transistors N 4  and N 5 . Since the I+I offset  flowing through the fourth node Node 4  flows more by the offset current I offset , the fourth body bias voltage Vbias 4  is set to be lower than the third body bias voltage Vbias 3  so that the threshold voltage Vth of the NMOS transistor N 5  is higher than the threshold voltage Vth of the NMOS transistor N 4 . 
         [0081]    Accordingly, the offset of the sense amplifier flip flop is adjusted by adjusting the third and fourth body bias voltages Vbias 3  and Vbias 4  respectively applied to the bodies of the NMOS transistors N 4  and N 5  of the differential amplifying portion  34 . 
         [0082]    In order to adjust the offset, the above-described embodiment applies the body bias voltages Vbias 3  and Vbias 4  respectively to the NMOS transistors N 4  and N 5 . However, the body bias voltage can be applied to only one of the NMOS transistors N 4  and N 5 . That is, the fourth body bias voltage Vbias 4  applied to the NMOS transistor N 5  is adjusted lower when the current flowing through the fourth node Node 4  is much, whereas the third body bias voltage Vbias 4  applied to the NMOS transistor N 5  is adjusted higher when the current flowing through the fourth node Node 4  is small. 
         [0083]      FIG. 7  is a circuit diagram illustrating a second bias voltage generating portion which generates the third and fourth body bias voltages of  FIG. 6 . 
         [0084]    In  FIG. 7 , a second external voltage Vext 2  is lower than a second internal voltage Vint 2 , and the ground voltage Vss of  FIG. 4  can be used as the second internal voltage Vint 2 . The second bias voltage generating portion includes multiple resistors R 21  to R 26  coupled between the second external voltage Vext 2  and the second internal voltage Vint 2  and outputs the bias voltage to output terminals A 21  to A 27  respectively coupled between the resistors R 21  to R 26 . 
         [0085]    The greater the number of the resistors arranged between the second external voltage Vext 2  and the second internal voltage Vint 2  is, the more precisely the voltage is adjusted. 
         [0086]    As a voltage necessary to adjust the offset of the sense amplifier flip flop of  FIG. 6 , the third body bias voltage Vbias 3  and the fourth body bias voltage Vbias 4  are selected in the output terminals A 21  to A 27  and then applied to the NMOS transistors N 4  and N 5 . 
         [0087]    Similar to the bias voltage generating portion described in  FIG. 5 , the voltage Vext 2  and the voltage Vint 2 , may be any voltage from any source as desired. 
         [0088]      FIG. 8  is a circuit diagram illustrating a sense amplifier flip flop according to a third embodiment. The sense amplifier flip flops of  FIGS. 4 and 6  adjust the offset by applying the first and second body bias voltages to the bodies of the PMOS transistors P 3  and P 4  of the differential amplifying portion  32  or by applying the third and fourth body bias voltages to the bodies of the NMOS transistors N 4  and N 5  of the differential amplifying portion  34 , respectively. However, the sense amplifier flip flop of  FIG. 8  adjusts the offset by applying the first and second body bias voltages to the bodies of the PMOS transistors P 3  and P 4  of the differential amplifying portion  36  and applying the third and fourth body bias voltages to the bodies of the NMOS transistors N 4  and N 5  of the differential amplifying portion  36 . 
         [0089]    In order to detect the offset of the sense amplifier flip flop of  FIG. 8 , if the current I+I offset  flowing through the fourth node Node 4  is greater than the current I flowing through the third node Node 3  by the offset current I offset , when the input signal D and the inverted input signal DB are respectively applied at a high level to the NMOS transistors N 2  and N 3 , the first body bias voltage Vbias 2  is applied to the PMOS transistor P 3 , the second body bias voltage Vbias 2  is applied to the PMOS transistor P 4 , the third body bias voltage Vbias 3  is applied to the NMOS transistor N 4 , and the fourth body bias voltage Vbias 4  is applied to the NMOS transistor N 5 . The first and second body bias voltages Vbias 1  and Vbias 2  may be positive, and the threshold voltages of the PMOS transistors P 3  and P 4  are increased, which reduces the current which flows to the drains of the PMOS transistors P 3  and P 4 . The third and fourth body bias voltages Vbias 3  and Vbias 4  may be negative, and the threshold voltages of the NMOS transistors N 4  and N 5  are increased, which reduces the current which flows to the sources of the NMOS transistors N 4  and N 5 . Since the current I+I offset  flowing through the fourth node Node 4  is greater by the offset current I offset , the second body bias voltage Vbias 2  is set to be higher than the first body bias voltage Vbias 1  so that the threshold voltage Vth of the PMOS transistor P 4  is higher than the threshold voltage Vth of the PMOS transistor P 3 , and the fourth body bias voltage Vbias 4  is set to be lower than the third body bias voltage Vbias 3  so that the threshold voltage Vth of the NMOS transistor N 5  is higher than the threshold voltage Vth of the NMOS transistor N 4 . 
         [0090]    Accordingly, the offset of the sense amplifier flip flop is adjusted by adjusting the first and second body bias voltages Vbias 1  and Vbias 2  respectively applied to the bodies of the PMOS transistors P 3  and P 4  of the differential amplifying portion  36  and the third and fourth body bias voltages Vbias 3  and Vbias 4  respectively applied to the bodies of the NMOS transistors N 4  and N 5 . 
         [0091]    In order to adjust the offset, the above-described embodiment applies the body bias voltages Vbias 1  and Vbias 2  respectively to the PMOS transistors P 3  and P 4 , and applies the body bias voltages Vbias 3  and Vbias 4  respectively to the NMOS transistors N 4  and N 5 , but one or more of the body bias voltages can be applied to corresponding one or more of the PMOS transistors P 3  and P 4  and the NMOS transistors N 4  and N 5 . That is, the second body bias voltage Vbias 2  applied to the PMOS transistor P 4  is adjusted higher or the fourth body bias voltage Vbias 4  applied to the NMOS transistor N 5  is adjusted lower when the current flowing through the fourth node Node 4  is much, whereas the second body bias voltage Vbias 2  applied to the PMOS transistor P 4  is adjusted lower or the fourth body bias voltage Vbias 4  applied to the NMOS transistor N 5  is adjusted higher when the current flowing through the fourth node Node 4  is small. 
         [0092]    In  FIG. 8 , the first and second body bias voltages Vbias 1  and Vbias 2  are generated by the first bias voltage generating portion of  FIG. 5 , and the third and fourth body bias voltages Vbias 3  and Vbias 4  are generated by the second bias voltage generating portion of  FIG. 7 . 
         [0093]    As described above, the sense amplifier flip flop which adjusts the offset according to an embodiment includes the pre-charging portion, the differential input portion, the differential amplifying portion, and the latch portion, and adjusts the offset by applying the body bias voltage to the body of the MOS transistor of the differential amplifying portion to adjust the threshold voltage of the MOS transistor. Thus, it is easy to design, and the layout area size is small, and the offset of the sense amplifier flip flop can be adjusted without fuse cutting. 
         [0094]    Although particular embodiments have been described, one skilled in the art will understand that various modifications may be made without departing from the spirit and scope of the following claims.