Abstract:
A technique and apparatus for increasing the peak output pulse power of a capacitor driven high-power diode and square-loop saturable reactor pulse compression generator or transmitter (such as a Loran-C transmitter or other high power pulse generator) with the aid of a minority carrier sweep-out circuit interposed, within the pulse compression circuit.

Description:
FIELD  
       [0001]     The present invention relates to high-power RF solid-state generators or transmitters wherein RF pulses are generated by means of magnetic pulse compression and pulse forming networks; the invention being more particularly, though not exclusively, concerned with SCR switching-controlled generators used for U.S. Coast Guard Loran-C navigation (and for similar transmitters) such as of the Accufix® type of Megapulse, Inc., the assignee of the present invention, the basic operational principles of which are described, for example, in my earlier U.S. Pat. Nos. 4,001,598; 3,832,573; and 3,889,263; and with techniques for increasing the peak output pulse power capability thereof.  
       BACKGROUND  
       [0002]     Such pulse generators or transmitters basically embody SCR-controlled capacitor charging and displaying circuits driving square-loop saturable magnetic reactor pulse compression circuits comprising series-resonant circuits feeding an output RF transformer for energizing an antenna load to radiate RF pulses at the desired output frequency to which the series resonant circuit is tuned—100 kHz for a Loran-C transmitter.  
         [0003]     Prior to the discovery of the present invention, the peak output power that could be so generated was limited, as later more fully explained, by the minority carrier charges stored in the solid-state junction of the pulse compression circuit high-power diode connected in series with the saturable reactor, being dissipated by the rapid build-up of reverse current as the reactor saturates. Heretofore, the possible peak output power was limited by the minority carriers in the high power diode and not by the actual power ratings of the capacitors and other circuit components, which were thus under-used in such pulse generators.  
         [0004]     In accordance with the present invention, this limitation of high-power pulse output has been totally overcome and the full power ratings of the circuit components now made available for use, by the insertion of a novel type of minority carrier sweep-out circuits for the pulse compression circuit diode, and in a novel shunt position in the pulse compression circuit.  
         [0005]     While the broad concept of minority carrier sweep-out networks for priming-loss reduction and for eliminating dissipated minority carrier sweep-out losses in the SCR junctions of SCR-controlled energy switching circuits has been used for many years by said assignee and others, as described in my prior U.S. Pat. No. 4,230,955 (and also in U.S. Pat. No. 4,674,022), the discovery has now been made that a novel configuration sweep-out circuit is possible for the minority carriers developed in the series solid-state diode itself of a pulse compression circuit, and that such use may now enable the employment of the full actual voltage and power ratings of the pulse generator circuit components, allowing substantially increased peak output power to be generated by the same transmitter.  
       OBJECTS OF INVENTION  
       [0006]     It is accordingly a primary object of this invention to provide a new and improved method of and apparatus for obviating the RF peak output power limitations of prior solid-state generators as above described, and to enable the increasing of the peak output pulse power deliverable by capacitor-driven high-power diode and square-loop saturable reactor pulse compression generators through use of minority carrier sweep-out circuits for the pulse compression circuit high-power series diode of such circuit.  
         [0007]     A further object is to provide such an improved apparatus in which the full power rating of the components of the pulse compression circuit now becomes usable for generating higher peak output pulses.  
         [0008]     Other and further objects will be explained hereinafter and are more fully delineated in the appended claims.  
       SUMMARY  
       [0009]     In summary, however, from one of its important aspects, the invention embraces in a radio-frequency pulse generator comprising a capacitor voltage-discharge-driven series-connected high power solid-state diode and square loop saturable magnetic reactor series-resonant pulse compression circuit for delivering-high voltage pulses to a load such as an antenna tuned to said radio frequency, a method of removing limitations on the use of the full voltage rating of said capacitor and thus on the peak power output of said pulse compression circuit caused by minority carrier charges stored in the solid-state diode junction at the time of reverse current saturation of said reactor during the series resonance of said circuit, that comprises, interposing a minority carrier sweep-out circuit in the pulse compression circuit, and adjusting the sweep-out circuit to produce a time of recovery of said diode less than said time of reverse current saturation of said reactor, thereby to eliminate said limitations and to permit the use of the full voltage rating of said capacitor to enable the increasing of said peak power output.  
         [0010]     Preferred and best mode designs are later fully described. 
     
    
     DRAWINGS  
       [0011]     The invention will now be described with reference to a preferred embodiment shown applied to a Loran-C type transmitter for purposes of illustration, and in which  
         [0012]      FIG. 1  presents a schematic circuit diagram of an improved pulse compression generator or transmitter using the present invention;  
         [0013]      FIG. 2  is a graph illustrating the voltage and current waveforms developed in the operation of the circuit of  FIG. 1 ;  
         [0014]      FIG. 3  is a graph showing high-power diode current developed in  FIG. 1  and the resulting load voltage;  
         [0015]      FIG. 4  is a waveform diagram illustrating the saturable reactor square-loop electrical characteristics in the pulse compression circuit of  FIG. 1 ; and  
         [0016]      FIGS. 5 and 6  contrast the voltage and current waveforms developed in the absence of the use of the sweep-out circuit of the present invention in the pulse compression circuit, and with the use of such sweep-out circuit, respectively. 
     
    
     DESCRIPTION OF PREFERRED EMBODIMENT  
       [0017]     Referring to  FIG. 1 , the high-power pulse generator or transmitter with magnetic pulse compression is shown consisting of four basic parts labeled “C 1  Charging Circuit”  1 , “C 2  Charging Circuit”  2 , “Pulse Compression Circuit”  3 , and “Output RF Transformer”  4 . Voltage from a DC power supply, say of the order of 300 volts for the illustrative Loran-C transmitter application, charges the capacitor C 1  in response to the switching action of SCR 1 . A first series saturable reactor SR 1  and a second switching SCR 2 , shown shunted by resistance R S  and by capacitance C S , serve as the second resonance-charging circuit  2  voltage doubler for capacitor C 2 , as is well-known. The before-mentioned high-power solid-state diode D 1  is then shown connected in series in the pulse compression circuit  3  as shunted by capacitor C 5  and resistance, and series-connected in a series-resonant circuit with a second square-loop saturable magnetic reactor SR 2 , driving the primary or left-hand winding of the output RF transformer  4 , which is in turn coupled to a secondary step-up transformer winding (ratio 2:50) that energizes the ultimate load, such as a tuned transmitting antenna. A conventional reset circuit is shown coupled to each of the saturable reactors SR 1  and SR 2 .  
         [0018]     The operation of the system of  FIG. 1  is as follows, referencing the illustrative waveforms and examples of  FIGS. 2 and 3 . At the start of the pulse generating process, (t=0 in  FIG. 2 ), the voltages on C 1  and C 2  are negative and equal in magnitude. The charging of C 1  occurs in the time interval 0 to 150 μsec. This is followed by a time interval of 100 μsec. (150 to 250 μsec.) to allow SCR 1  to recover. At 250 μsec., SCR 2  is turned on, triggering the discharge or transferring of the charge on C 1  to C 2  in the time interval 250 to 265 μsec. In this time-interval, the voltage on C 2  drives the square-loop saturable reactor SR 2  from negative to positive saturation, which occurs at 265 μsec. Capacitor C 2  and the saturable reactor SR 2  form the before-mentioned series-resonant circuit tuned to the desired output frequency; i.e. 100 kHz for a Loran-C transmitter antenna. Thus, a 15 μsec. current pulse (i SCR2 ) of peak amplitude 3,300 amperes is converted into a 5 μsec. high current pulse of amplitude 10,000 amperes.  
         [0019]     The shaded area labeled A 1  in  FIG. 2 , is the volt-time area that drives SR 2  from negative to positive, with saturation occurring at time 
 
T pos.sat ≅265 μsec 
 
 The shaded area labeled A 2  in  FIG. 2  is the volt-time area that drives SR 2  from positive to negative saturation. Since A 1 =A 2 , the time of negative saturation T neg.sat , occurs at approximately 276.5 μsec. In the time interval between T possat  and T negsat , the SR 2  current is very small, shown as Δi SR 2  in  FIGS. 4 and 5 . 
 
         [0020]     As earlier noted, the high-voltage series diode D 1  will recover when all the minority carriers in the diode junction have been removed. Without the presence of the saturable reactor SR 2  in series with the diode D 1 , the reverse recovery current of D 1  would be that shown as the dotted curve in  FIG. 5 . The current-time area labeled Q 1  in  FIG. 5  is the minority carrier charge stored in the junction.  
         [0021]     With SR  2  in series with D 1 , on the other hand, as shown, the reverse current is limited to a small, Δi SR 2 , as shown in  FIGS. 4 and 5 . This small value of reverse current lasts until SR 2  saturates in the reverse direction, which, for the above example, occurs at 
 
T neg.sat ≅276.5 μsec. 
 
         [0022]     At such time, the reverse current builds up rapidly until the stored minority carriers have been swept out, such occurring when the shaded area Q 2  is equal to Q 1  at time 
 
T D1Rec ≅277.5 μsec. 
 
         [0023]     A large reverse current spike is generated, however, as shown in  FIG. 5 . This could cause overheating and voltage breakdown of the diode D 1 . To prevent this from happening, the diode D 1  must recover before the reactor SR 2  saturates. Thus, 
 
T D1Rec &lt;T neg.sat . 
 
 In the past, to satisfy this inequality, T neg.sat  has been increased by decreasing the C 2  reverse voltage. This decrease has been obtained by lowering the C 2  forward voltage. Thus, an upper limit has been set on the C 2  forward voltage. Typically, in the above example, this voltage limit is 800 volts, and this, in turn, has limited the peak output pulse power. 
 
         [0024]     In accordance with the present invention, this inequality is satisfied in a very different way; namely, by decreasing T D1Rec  through inserting a “minority carrier sweep-out circuit” consisting of the series interconnection of a diode D 2  and a resistor R S , shown in  FIG. 1  as connected in shunt in the pulse compression circuit  3  from the point of series connection of D 1  and SR 2  to the bottom terminal of the primary winding of the step-up output transformer  4 .  
         [0025]     The voltage and current waveforms of this sweep-out circuit are shown in  FIG. 6 . The current i D2  sweeps out the minority carrier charge in diode D 1  as shown by the shaded area Q 3  in  FIG. 6 . The diode D 1  recovers when the area Q 3  becomes equal to the area Q 2  in  FIG. 5 . As seen from  FIG. 6 , the time of the recovery of the diode D 1  is approximately 
 
T D1Rec ≅272 μsec. 
 
 Since the negative saturation of SR 2  occurs at 276.5 μsec., the before-stated inequality 
 
 T D1Rec &lt;T neg.sat  
 
 is thus satisfied. 
 
         [0026]     The incorporation of this “sweep-out circuit” has now made it possible to increase the voltage used on capacitor C 2  from 800 volts to 1000 volts. Thus, the output power of the transmitter has now been substantially increased, in this case by a factor of  
           (       1   ⁢     ,     ⁢   000     800     )     2     =     1.56   .         
 
         [0027]     The invention, of course, is not limited to the illustrative Loran-C configuration and exemplary values presented, but, as before indicated, are useful in other applications, as well.  
         [0028]     Further modifications, indeed, will occur to those skilled in this art, and such are considered to fall within the spirit and scope of the invention as defined in the appended claims.