Abstract:
A base cell for a gate array or standard cell integrated circuit design has N and P wells organized in checkerboard fashion, each well containing several P and N devices respectively. A first of the plurality of relatively deep P regions is adjacent to at least a first and a second of the plurality of relatively deep N regions. The first relatively deep N region is adjacent to the first relatively deep P region along a first edge of the first relatively deep N region, and to the second relatively deep P region along a second edge of the relatively deep N region. The first and second edges of the relatively deep N region are perpendicular. An array of the base cells therefore has a checkerboard pattern, unlike the striped pattern of typical gate array and standard cell designs. The array of the base ceLls is amenable to minimizing clock parasitic capacitance when clocked inverters, including the complimentary clocked inverters of latches, are laid out at vertexes of the checkerboard pattern.

Description:
CROSS REFERENCE TO RELATED PATENT APPLICATION  
       [0001]    The present invention claims priority from United States Provisional Patent application Ser. No. 60/238,228 filed Oct. 5, 2000, the disclosure of which is herein specifically incorporated by this reference. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The invention relates to the fields of standard-cell and mask programmed gate-array integrated circuit design. In particular, the invention relates to a cell design for use in CMOS gate-array integrated circuit design that allows reduced parasitic capacitance of clock-line input interconnect.  
         BACKGROUND OF THE INVENTION  
         [0003]    Clock line routing delay is a perennial issue in the art of integrated circuit design. It is known that excessive power drain can result from slow rise and fall times of clock lines because common clocked-inverter or multiplexor-based “flip-flop” designs can conduct “crowbar” current during slow, delayed, clock edges. It is also known that clock skew, or excessive differences in clock delay, to different flip-flops of a chip can cause logical malfunction because signals may propagate in a different clock cycle than that required by the logical design of the chip.  
           [0004]    Signal routing delay, including clock routing delay, on an integrated circuit is largely a function (F) of the distributed resistance (R) of the interconnect distributing the signal and of the distributed load capacitance (C) driven by the signal. Function F is a complex function of the way the R and C is structured, is primarily a function of the product of various components of R and C, and that part of function F is the R-C delay of the routing.  
           [0005]    The capacitance C comprises gate capacitance of load devices as well as parasitic capacitances coupling the signal routing to adjacent signal routing, metal interconnect on other layers, the integrated circuit substrate, source and drain regions of devices, and other features on the chip. The resistance R comprises the resistance of connections between layers of the chip and resistance resulting from the sheet resistivity of the interconnect. While sheet resistivity of metal interconnect may be as low as 0.05 ohms per square, a 0.25 micron wide metal line only a quarter of an inch long of 0.05 ohm material presents approximately 1250 ohms resistance— enough to be significant.  
           [0006]    It is known that high R-C delays in clock line routing on an integrated circuit can cause slow, delayed, rise and fall times. Further, high R-C delays in clock line routing can cause excessive clock skew. It is therefore desirable to keep R-C delays of clock lines low to ensure that chips will work well.  
           [0007]    Many techniques have been used to reduce the amount and effect of clock line R-C delay on integrated circuits. Several techniques must often be combined to produce acceptable results. Common techniques include:  
           [0008]    1. distributing multiple clock drivers over the chip while balancing driver sizes, and distribution grid or tree layouts, to equalize delay among the multiple grids and trees that result,  
           [0009]    2. use of wider-than-minimum metal for clock distribution to reduce R,  
           [0010]    3. connecting clock distribution lines into grid or tree structures to reduce R,  
           [0011]    4. driving long, slow, or heavily loaded clock lines at multiple points,  
           [0012]    5. use of silicon on insulator technologies to reduce parasitic capacitance,  
           [0013]    6. deliberate addition of delay to flip-flop designs to reduce skew sensitivity,  
           [0014]    7. local buffering of clock lines at, or internal to, flip-flops to reduce the number of devices driven by the clock lines, thereby reducing load C on the clock lines, and  
           [0015]    8. spacing clock lines further from other circuitry than the minimum spacing used elsewhere in the chip.  
           [0016]    These techniques require substantial design effort, circuitry, processing expense, layout space, or sacrifice of potential performance. It is therefore desirable to reduce the effect of R-C delay of clock lines in other or additional ways.  
           [0017]    Many flip-flop designs used today have multiple clocked inverters, or, equivalently, standard inverters driving through clock-controlled transmission gates. These structures are often coupled in pairs, such that a first clocked inverter is driving while a second inverter of the pair is in a high impedance state; when the clock has an opposite value the first inverter is in high impedance and the second inverter drives. A typical D-type edge-triggered flip-flop design incorporates two such clocked inverter pairs. Other clocked gates, such as clocked NAND, NOR, AND-OR-INVERT, and OR-AND-INVERT gates are often paired with clocked inverters to build other flip-flops, including common types of D-type edge-triggered flip-flops having a reset input.  
           [0018]    Masked programmed gate-array integrated circuits are typically built on a master-slice having a regular array of P and N type transistors. A base-cell for such an array is a small portion of such a regular array that may be replicated in the circuit layout to form a larger portion of the array. Because latchup considerations require spacing between adjacent N and P type transistors, these transistors are typically built in rows, where devices in the same row are of the same type; this permits placement of more devices per unit area than possible with other designs. A common design for use with a “sea of gates” router alternates pairs of rows of N type devices with pairs of rows of P type devices. Similarly, a common design for use with a channel router has device strips separated by routing channels. Each device strip comprises a row of N type devices adjacent to a row of P type devices.  
           [0019]    Standard-cell integrated circuit designs are typically created by first designing a library of standardized designs for performing typical logical functions, each such standardized design is known as a “cell”. A logical design of the integrated circuit, or portion thereof, is made that invokes cells of the library; specifying cell types and interconnections between cells. Layout is performed by placing required cells in a chip layout, then interconnecting the cells and any surrounding logic as required by the logical design of the circuit.  
           [0020]    Cells of a standard cell library are frequently placed adjacent to other cells of the same library. Each cell must therefore be designed such that placement next to any other cell of the library does not cause unexpected design rule violations (such as spacing violations) or functional problems because of short circuits between portions of the adjacent cells. This is enforced by designing cells according to a set of cell-edge rules. In order to ensure cell-edge rules are met, cell libraries have been designed where the transistors of each cell are fabricated in rows in a regular pattern, with higher-level interconnect defining connections of the transistors. A section of the regular pattern of such devices can also be described as a base-cell.  
           [0021]    It is also known that modern dynamic memory devices often have logic in them. For example, memory devices may contain data registers to perform dual-data-rate conversion or on-chip caching functions. Similarly, memory devices are known that have internal refresh address counters and multiplexers, as well as address latches and counters for receiving multiplexed addresses and performing burst-mode read or write operations.  
         SUMMARY OF THE INVENTION  
         [0022]    A base-cell layout has been devised that incorporates N-channel devices in P-well, and P-channel devices in N-well, in each row of the base cell. This base cell is suitable for either gate-array or standard-cell design methodology. The base cell has two rows, such that a region of P-channel devices in N-well of the second row is adjacent to the region of N-channel devices in P-well of the first row.  
           [0023]    The base-cell is copied and arrayed, with mirrored and flipped copies of the cell, in the gate-array or standard-cell design layout such that the well masks have a checkerboard appearance. This array layout is intended for fabrication in a junction-isolated (not a silicon-on-insulator) integrated circuit fabrication process which may be of the N-Well, P-Well, or Twin-Well type.  
           [0024]    This results in a gate array that, while it has fewer total devices per unit area than does a typical row-based gate array, is more convenient for laying out of clocked-gate pairs and multiplexor circuits. Circuits having large quantities of clocked-gate, including clocked inverter pairs, can be laid out into the gate array with less interconnect resistance and capacitance on the clock and not(clock) lines than attained on typical layouts.  
           [0025]    Particularly, the base-cell layout of the present invention allows on-chip clock lines to be laid out in a substantially straight, linear arrangement that significantly aids overall device performance and design time to market with only a small increase in the requisite on-chip area, or “real estate”.  
           [0026]    The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0027]    [0027]FIG. 1 is a schematic of a Latch design, as commonly used in the design of CMOS integrated circuits;  
         [0028]    [0028]FIG. 2, an example of racethrough caused by clock-skew should RC delays of clock lines be excessive;  
         [0029]    [0029]FIG. 3, a layout of a gate array base-cell as known in the art;  
         [0030]    [0030]FIG. 4, an example layout of an array of transistors in base cells as known in the art, the transistors being in rows of N and P type transistors in P and N type wells respectively;  
         [0031]    [0031]FIG. 5, an array of transistors according to the base-cell layout of the present invention;  
         [0032]    [0032]FIG. 6, an example layout of an array of transistors base cells of the present invention, having wells organized in “checkerboard” fashion;  
         [0033]    [0033]FIG. 7, an example of a latch implemented on a base cell of the present invention; and  
         [0034]    [0034]FIG. 8, an example of a particular implementation of the present invention illustrating an arrayed, simplified clocking circuit and having outboard clk and clkb lines with an alternating, reversed Pch 2 &lt;-&gt;Nch 2  and Pch 4 &lt;-&gt;Nch 4  wireup. 
     
    
     DETAILED DESCRIPTION  
       [0035]    A latch as commonly used in the art of CMOS integrated circuit design has a first clocked inverter, comprising first  100  (FIG. 1) and second  102  pulldown devices and first  106  and second  104  pullup devices. The latch also has a second clocked inverter, comprising third  108  and fourth  110  pulldown devices and third  112  and fourth  114  pullup devices. The latch also has an inverter stage  116  generating an output Q, and receives three inputs, IN, Clock, and Not(Clock).  
         [0036]    It is known that two latches of this type may be combined, with reversed Clock and Not(Clock) inputs, to form an edge-triggered D-type flip-flop. It is also known that one or more of the clocked inverters of one or more latches of an edge-triggered D-type flip-flop may be replaced with one or more clocked gates of other types to add additional inputs, such as a reset or set input, to the flip-flop.  
         [0037]    For this patent, the term “clocked gates” includes clocked inverters, clocked NOR gates, clocked NAND gates, clocked AND-OR gates, and other types of complex, clocked gates. The inverter of one or more latches may also be replaced by a NAND, NOR, or other gate as required to provide appropriate logic function for the flip-flop. Some flip-flop designs also include a clock inverter to produce one phase of the clock locally.  
         [0038]    Modern integrated circuits may incorporate many hundreds, or even thousands, of latches and flip-flops of this type.  
         [0039]    In every such latch, there is inevitably parasitic routing capacitance, such as capacitances  118  and  120 , on the Clock and Not(Clock) lines of the latch. Interconnect resistance is also inevitable. This parasitic routing capacitance combines with other capacitances, including gate capacitance of the devices  104 ,  102 ,  110 , and  112 , and resistance, including interconnect resistance, to produce an effective RC delay between a clock driver and clock devices, such as devices  104 ,  102 ,  110 , and  112 .  
         [0040]    Consider a pair of D-type flip-flops  200  (FIG. 2) and  202 , each built of a pair of the latches of FIG. 1. There are potentially four different RC delays  204 ,  206 ,  208 , and  210  on the clock and not(clock) lines. It is known that, if delays  208  and  210  on the clock and not(clock) lines of the second flip-flop  202  are greater by a certain amount than the delays  204  and  206  on clock and not(clock) lines of the first flip-flop  200 , then data may skip through the second flip-flop  202  in the same clock cycle in which it is sampled by the first flip flop  200 . This is one of several types of mal-operation that can be caused by excessive difference in clock delay, known as excessive clock skew.  
         [0041]    It is known that the effective RC delay can be reduced in several ways, including holding routing capacitances  118  (FIG. 1) and  120  to a minimum.  
         [0042]    A traditional base cell for a CMOS integrated circuit layout has a strip of P-type devices. In modern processes these may be formed in an N-well  316  (FIG. 3) where polysilicon gate “dogbones”  300 ,  302 ,  304 ,  306 ,  308 ,  310 ,  312 , and  314  cross P-type diffused regions  320 ,  322 , and  324 . These polysilicon regions are known as dogbones because they often are made narrower in their middles than at their ends, where they must be wide enough for contacts.  
         [0043]    Similarly, there is a parallel strip of N-type devices, formed in a P-well  326  where polysilicon gate “dogbones”  330 ,  332 ,  334 ,  336 ,  338 ,  340 ,  342 , and  344  cross N-type diffused regions  350 ,  352 , and  354 . Each dogbone may be contacted to by contacts (not shown) at either end for gate connection to the devices, and source or drain connections may be made at contact locations, such as potential contact locations  360  and  362 , to the diffused regions. In each base cell, there are also well and substrate ties for prevention of latchup as known in the art.  
         [0044]    A typical CMOS integrated circuit formed from these base cells has multiple base cells arrayed in mirrored form, such that the same-polarity wells of adjacent base cells are merged to the greatest extent possible. This is typically done to avoid the chip-area cost associated with well-to-well spacing design rules. As a result, distinct pairs of rows of N-type devices  400  (FIG. 4) in P-wells  402 , and pairs of rows of P-type devices  404  in N-wells  406  may be seen in a typical array; these rows may extend for great distances across each chip. It is known that customized contact, metal, and via (metal to metal connection) layers may be used to connect the devices of the base cells into circuitry, including circuitry forming multiple clocked inverters or flip-flops. Similarly, standard cells can be designed incorporating similar base-cells; the standard cells being interconnected to form an integrated circuit.  
         [0045]    A base cell of the present invention also has two rows. In the first row, it has a short strip of P-type devices, where polysilicon gate dogbones  500  (FIG. 5) cross P-type diffused regions  502  in a relatively deep N-type region, which may be an N-well  504 . Adjacent to, and in the same row as, the short strip of P-type devices is a strip of N-type devices where polysilicon gate dogbones  506  cross N-type diffused regions  508  in a relatively deep P-type region, which may be a P-well  510 . Deep P region  516  is adjacent to deep N region  524  along a first edge, and to relatively deep N region  504  along a second edge, where the first and second edge are perpendicular. Similarly relatively deep N region  504  is adjacent to relatively deep P region  516  along a first edge, and to relatively deep P region  510  along a second edge, where the first and second edge are perpendicular.  
         [0046]    In the second row, adjacent to the short strip of P-type devices of the first row, is a short strip of N-type devices formed by polysilicon gate dogbones  512  crossing N-type diffused regions  514  in a relatively deep P-type region, which may be a P-well  516 . Similarly, adjacent to the strip of N-type devices of the first row, is a strip of P-type devices formed by polysilicon gate dogbones  520  cross P-type diffused regions  522  in a relatively deep N-type region, which may be an N-well  524 . In each base cell, there are also well and/or substrate ties  530  for prevention of latchup as known in the art.  
         [0047]    Four of the relatively deep regions, or wells, of the base cell are organized about a vertex  532 .  
         [0048]    The base cell provides a pattern of two-high and four-high with center tap stacks of devices. These can be coupled into a variety of logic gates in the manner known in the art of CMOS integrated circuit design.  
         [0049]    A typical CMOS design layout of the present invention has multiple base cells arrayed in mirrored form, such that the wells of adjacent base cells are merged to a significant extent. As a result, a checkerboard pattern of short strips of N-type devices  600  (FIG. 6) in P-wells  602 , alternating with short strips of P-type devices  604  in N-wells  606  may be seen in each row pair of the array. These row pairs are fabricated such that each first row pair is adjacent to a second row pair such that a strip of N-type devices in P-well of the first row pair is adjacent to a strip of P-type devices in N-well of the second row pair. This array therefore presents a checkerboard pattern of alternating device types in alternating well types.  
         [0050]    A CMOS base cell of the present invention lends itself to being connected with contact and metal layers into a latch similar to that of FIG. 1. Such a latch has an input IN (FIG. 7), an output Q, a power rail  700 , a ground rail  702 , a CLOCK input  704 , and a NOT(CLOCK) input  706 . The two clock devices  708  and  709  and two not(clock) devices  710  and  711  of the latch can be laid out where each pair is in one column, thereby allowing minimum CLOCK and NOT(CLOCK) routing. The CLOCK and NOT(CLOCK) devices are further laid out about a vertex  712  of the checkerboard-like pattern of N-wells and P-wells. This allows for small parasitic loads on the clock and not(clock) lines.  
         [0051]    The latch as illustrated utilizes a first level of metal, including the clock  704 , not(clock)  706 , power rail  700 , and ground rail  702 , and a second level of metal having the IN input and Q output. The metal layers are connected together with vias  716 , and to the polysilicon dogbones and diffused regions with contacts  718  as known in the art. The metal layer used for each of these signals is the designer&#39;s choice, latches built on an array of the present invention may have actual layout varying from that illustrated in FIG. 7.  
         [0052]    Not all CLOCK and NOT(CLOCK) devices need be at vertexes of the pattern, for example but not by way of limitation, devices  711  and  714  could have been switched in the latch of FIG. 7 without unduly detracting from the principles of the invention. It is desirable, however, that parasitic capacitance of the CLOCK and NOT(CLOCK) lines be held low by minimizing the length of interconnect used to connect these lines, wherever they may be located in a latch or flip-flop, to their associated transistors. Minimizing the length of interconnect connecting these lines to their transistors is done by placing the transistors close to the associated CLOCK or NOT(CLOCK) line.  
         [0053]    Similarly, other register types, including D-type flip-flops and D flip-flops with reset or preset inputs, can also be laid out such that each component latch has little parasitic interconnect load on its CLOCK and NOT(CLOCK) lines.  
         [0054]    While the invention has been described with reference to CLOCK and NOT(CLOCK) input signals to latches, since flip-flops are built from latches the invention is equally applicable to flip-flops. The invention is also applicable to other forms of logic as well, including high-speed multiplexers. With multiplexers having two complementary select inputs, SEL and SELX, the SEL line is equivalent to a CLOCK, and the SELX line equivalent to a NOT(CLOCK) line as heretofore described.  
         [0055]    [0055]FIG. 8 depicts an example of a particular implementation of the present invention illustrating an arrayed, simplified clocking circuit and having outboard clk and clkb lines with an alternating, reversed Pch 2 &lt;-&gt;Nch 2  and Pch 4 &lt;-&gt;Nch 4  wireup.  
         [0056]    The base cell design of the present invention also lends itself to minimizing load on select lines of multiplexers, such as two-to-one multiplexers implemented as paired stacks of four devices. Each stack of such a multiplexer resembles a clocked inverter, differing in that the clock and not(clock) devices of clocked inverters connect to select and not(select) inputs of the multiplexer instead.  
         [0057]    P-well and N-well junction-isolated processes are known in addition to the dual-well junction-isolated process illustrated. In a P-well process, the substrate is utilized in place of an N-Well. Similarly, in an N-well process the substrate is utilized in place of a P-Well as a P-diffused region deep relative to N-type diffused device regions . Base cells equivalent to those discussed can therefore be fabricated in a P-well process or in an N-well process.  
         [0058]    The invention has been described with reference to a base cell in which all transistors are present in all designs. The invention is also applicable to standard-cell designs wherein particular “dogbones” that are not needed for particular cell designs are omitted from the layout. Omitting unneeded devices has advantage in that parasitic capacitances and resistances are reduced, while cell-edge rules are still enforced.  
         [0059]    In a particular group of embodiments of the present invention, an array of latch cells having layout as herein described is coupled into an array of data registers integrated with a Dynamic RAM circuit. In certain of these embodiments, the data registers as herein described are utilized to form dual-data-rate and quad-data-rate data output registers and internal cache registers.  
         [0060]    While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various other changes in the form and details may be made without departing from the spirit and scope of the invention.