Abstract:
A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority benefit of provisional application Ser. No. 60/721,214, filed Sep. 28, 2005, the full disclosure of which is incorporated herein by reference. 
     
    
     BACKGROUND  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to a static memory. More particularly, the present invention relates to magnetoresistive random access memory (MRAM).  
         [0004]     2. Description of Related Art  
         [0005]     Magnetoresistive random access memory is a type of non-volatile memory with fast programming time and high density. A MRAM cell has two ferromagnetic layers separated by a non-magnetic layer. Information is stored as directions of magnetization vectors in the two ferromagnetic layers.  
         [0006]     In conventional MRAM of a standard structural design, a single via is utilized for each GMR (Giant Magnetoresistance) memory bit end, and a metal is deposited into each via. However, the via in such conventional design is usually small, which results in residue remained inside the via after etching. In addition, the smaller via also causes unfavorable electrical contact between two adjacent GMR memory bits.  
         [0007]     For the forgoing reasons, there is a need for developing a method and a structure to improving the contact of two adjacent GMR memory bit.  
       SUMMARY  
       [0008]     A method is provided for contacting two adjacent GMR memory bits. First, a GMR stack layer is formed on a first dielectric layer, which is on a substrate. Then, the GMR stack layer is patterned to form at least two GMR memory bits. Next, a second dielectric layer is formed on the GMR memory bits and the first dielectric layer. Then, the second dielectric layer is patterned to form a via to expose two adjacent ends of the GMR memory bits. Finally, a metal plug is formed in the via and on the second dielectric layer.  
         [0009]     A connection for two adjacent GMR memory bits is also provided, wherein at least two GMR memory bits are on the first dielectric layer, on a substrate. In addition, a second dielectric layer is on the first dielectric layer and the GMR memory bits, wherein a via in the second dielectric layer is to expose two adjacent ends of the GMR memory bits. Finally, a metal plug is filled in the via and on the second dielectric layer.  
         [0010]     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     The invention can be more fully understood by reading the following detailed description of the preferred embodiment, with reference made to the accompanying drawings as follows:  
         [0012]      FIGS. 1A-1C  depicts a cross-sectional view of manufacturing process according to one embodiment of this invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0013]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0014]     According to one embodiment of the present invention, a manufacturing process is proved, wherein one single larger via is utilized for two adjacent bit ends.  FIGS. 1A-1C  illustrate a cross-sectional view of manufacturing process of the embodiment of this invention. First, referring to  FIG. 1A , a substrate  100  having a first dielectric layer  102  thereon is provided. Then a GMR stack layer is deposited and patterned on the first dielectric layer  102  to form GMR memory bits  104  and  106 . Patterning is performed by, for example, a photolithography process and an etching process sequentially.  
         [0015]     Next, as shown in  FIG. 1B , a second dielectric layer  108  is formed on the first dielectric layer  102  and both GMR memory bits  104  and  106 , and then is patterned to form a via  110  therein. Patterning is performed by, for example, a photolithography process and an etching process sequentially. After that, the via  110  is formed to exposes two adjacent ends of the GMR memory bits  106  and  104 .  
         [0016]     Referring to  FIG. 1C , a metal layer is deposit to fill into via  110  and on the second dielectric layer  108 . The metal layer is then patterned to form a metal plug  112  in the via  110  and on the second dielectric layer  108  to electrically connect the two adjacent ends of the GMR memory bits. The metal plug  112  used herein can be, for example, tungsten, or other conductive metals, which connects two adjacent ends of the GMR memory bits  104  and  106 .  
         [0017]     A third dielectric layer  114  can be further formed on the second dielectric layer  108  and the metal plug  112 . The first dielectric layer  102 , the second dielectric layer  108 , and the third dielectric layer  114  are formed by, such as chemical vapor deposition. Moreover, a material of the dielectric layers  102 ,  108  and  114  can be, for example, silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or other usable dielectric materials. The thickness of the dielectric layer is about 1500-3500 Angstroms.  
         [0018]     Accordingly, a larger via is proved, which decreases residue inside the via after etching process. In addition, since a single larger via is utilized for two adjacent bit ends, higher density bit layout is allowed. The electrical contact between the two adjacent GMR memory bits is also improved.  
         [0019]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.