Abstract:
The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present invention, one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one of some of bits of a column address signal. It is thus possible to reduce unnecessary switching current.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a Divisional application of Continuation application Ser. No. 12/252,970, filed Oct. 16, 2008, and issued as U.S. Pat. No. 7,952,943, which is a Continuation application of parent Ser. No. 11/320,855, filed Dec. 30, 2005, and issued as U.S. Pat. No. 7,447,083. This application is based upon and claims the benefits of the priority from the prior Korean Patent Application No. 10-2005-0094947 filed on Oct. 10, 2010, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to semiconductor devices, and more particularly, to semiconductor memory devices. 
     2. Discussion of Related Art 
     In general, a semiconductor memory device includes a column decoder that decodes a column address signal and outputs a column decoding signal in order to read data stored in a part of a plurality of memory cells connecter to an activated word line. 
       FIG. 1  is a schematic block diagram of s semiconductor memory device in the related art.  FIG. 1  shows an example of an X16 Dynamic Random Access Memory (DRAM), which has 16 data I/O pins and can process 16 data. Referring to  FIG. 1 , a semiconductor memory device  10  includes a memory cell array  11 , a column decoder  12 , main sense amplifiers  13  to  16 , an I/O circuit  17  and  10  pads P 1  to P 16 . 
     The memory cell array  11  has column memory cell blocks B 1  to B 4 . The semiconductor memory device  10  includes an 8K (8×1024) number of memory cells in a column direction. In other words, one word line (e.g., WL 1 ) is connected to an 8K number of memory cells. Each of the column memory cell blocks B 1  to B 4  has a 2K (2×1024) number of memory cells in a column direction. The construction of the column memory cell blocks B 1  to B 4  will be described in more detail below. The construction of the column memory cell blocks B 1  to B 4  is the same. Therefore, only the column memory cell block B 1  will be described as an example. Reference will be made to an exaggerated portion of the column memory cell block B 1  in  FIG. 1 . The column memory cell block B 1  includes a plurality of memory cell mats MAT disposed in matrix form. Local I/O lines LIO 0  to LIO 3  parallel to word lines WL 1  to WLn are disposed in twos between the memory cell mats MAT. Furthermore, local I/O lines LIO 0 , LIO 2  parallel to the word lines WL 1  to WLn are also disposed at both sides of the outmost of the memory cell mats. Furthermore, the local I/O lines LIO 0  to LIO 3  are respectively connected to main local I/O lines ML 0  to ML 3 s. 
     The column decoder  12  decodes a column address signal (ADD_COL). The construction and operation of the column decoder  12  will be described in more detail with reference to  FIG. 2 . The column decoder  12  includes an address driver  21  and address decoders  22  to  25 . The address driver  21  buffer a 9-bit column address signal (ADD_COL) and outputs the result to the address decoders  22  to  25 . The address decoder  22  decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_A 1  to DEC_A 512 ). The address decoder  23  decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_B 1  to DEC_B 512 ). The address decoder  24  decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_C 1  to DEC_C 512 ). The address decoder  25  decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_D 1  to DEC_D 512 ). 
     A read operation of the semiconductor memory device  10  will now be described in short. One of (e.g., WL 1 ) of the word lines WL 1  to WLn is activated. The column decoder decodes the column address signal (ADD_COL) and outputs column decoding signals (DEC_A 1  to DEC_A 512 ), DEC_B 1  to DEC_B 512 ), DEC_C 1  to DEC_C 512 ), DEC_D 1  to DEC_D 512 ). The column decoding signals (DEC_A 1  to DEC_A 512 ) are input to the mats MAT of the column memory cell block B 1 , respectively. The column decoding signals (DEC_B 1  to DEC_B 512 ) are input to the mats MAT the column memory cell block B 2 , respectively. Furthermore, the column decoding signals (DEC_C 1  to DEC_C 512 ) are input to the mats MAT of the column memory cell block B 3 , respectively. The column decoding signals (DEC_D 1  to DEC_D 512 ) are input to the mats MAT of the column memory cell block B 4 , respectively. Some data (not shown) of the memory cells included in the mats MAT of the column memory cell block B, are loaded onto the local I/O lines LIO 0  to LIO 3  in response to the column decoding signals (DEC_A 1  to DEC_A 512 ). Thereafter, the data loaded onto the local I/O lines LIO 0  to LIO 3  are input to the main sense amplifier  13  through the main local I/O lines ML 0  to ML 3 . In the same manner as the column memory cell block B 1 , data from the column memory cell blocks B 2  to B 4  are input to the main sense amplifiers  14  to  16  through the main local I/O lines ML 4  to ML 15 . 
     The main sense amplifier  13  amplifies the data received through the main local I/O lines ML 0  to ML 3  and outputs the amplified data (ND 0  to ND 3 ) to global I/O lines GIO 0  to GIO 3 . The main sense amplifiers  14  to  16  amplify data received through the main local I/O lines ML 4  to ML 15  and output the amplified data (ND 4  to ND 15 ) to global I/O lines GIO 4  to GIO 15 , in the same manner as the main sense amplifier  13 . 
     The I/O circuit  17  outputs the amplified data (ND 0  to ND 15 ), which are received through the global I/O lines GIO 0  to GIO 15 , to the output data (DO to D 15 ) through the IO pads P 0  to P 15 . However, if a logic value of any one of 8 bits of the column address signal (ADD_COL) is changed in the semiconductor memory device  10 , the address decoders  22  to  25  of the column decoder  12  are all operated. If the address decoders  22  to  25  are operated, a problem arises because high switching current is consumed unnecessarily. 
     Meanwhile, in the semiconductor memory device  10 , the local I/O lines LIO 0  to LIO 3  included in one column memory cell block must be disposed corresponding to a 2K number of memory cells. Therefore the length (A 1 ) of each of the local I/O lines LIO 0  to LIO 3  is relatively long. If the length of the local I/O line is long as described above, a voltage of data signals transferred through local I/O lines is attenuated. A problem arises because data cannot be read accurately. 
     SUMMARY OF THE INVENTION 
     An advantage of the present invention is that it provides semiconductor memory devices in which one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one or some of bits of a column address signal, reducing unnecessary switching current. 
     Another advantage of the present invention is that it provides a read operation method of a semiconductor memory device, in which one of a plurality of decoding units of a column decoder is selectively operated according to a logic value(s) of one or some of bits of a column address signal, reducing unnecessary switching current. 
     A semiconductor memory device according to an aspect of the present invention includes a memory cell array, a row decoder, a column decoder, sense amplifier groups and a data I/O circuit. The memory cell array includes a plurality of column groups, each having a predetermined number of column memory blocks. Each of the predetermined number of column memory blocks includes a plurality of memory cells sharing a plurality of word lines. The row decoder decodes a row address signal and activates one of a plurality of word lines according to the decoding result. The column decoder decodes a column address signal in response to a logic value(s) of one or some of bits of the column address signal and outputs column decoding signals to one of the plurality of column groups. The sense amplifier groups are respectively connected to the plurality of column groups through main local I/O line groups. The data I/O circuit outputs output data to I/O pads in response to amplified data, which are received through global I/O lines. Each of the sense amplifier groups amplifies internal data, which are received from a corresponding one of the plurality of column groups, and outputs the amplified data to the global I/O lines, and when any one of the plurality of column groups outputs the internal data in response to the column decoding signals, the remaining column groups do not output the internal data. 
     A read operation method of a semiconductor memory device according to an aspect of the present invention includes the steps of activating one of a plurality of word lines; decoding a column address signal in response to logic value(s) of one of some of bits of the column address signal, and outputting column decoding signals to any one of a plurality of column groups, each having a predetermined number of column memory blocks; amplifying internal data, which are received from one of the plurality of column groups through one of main local I/O line groups correspondingly connected to the plurality of column groups, and outputting the amplified data to global I/O lines, respectively; and outputting output data to I/O pads in response to the amplified data received from the global I/O lines. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram of s semiconductor memory device in the related art; 
         FIG. 2  is a detailed block diagram of a column decoder shown in  FIG. 1 ; 
         FIG. 3  is a schematic block diagram of s semiconductor memory device according to an embodiment of the present invention; 
         FIG. 4  is a detailed block diagram of the column decoder shown in  FIG. 3 ; 
         FIG. 5  is a detailed circuit diagram of a memory cell block shown in  FIG. 3 ; 
         FIG. 6  is a schematic block diagram of a semiconductor memory device according to another embodiment of the present invention; 
         FIG. 7  is a detailed block diagram of a column decoder shown in  FIG. 6 ; 
         FIG. 8  is a schematic block diagram of s semiconductor memory device according to further another embodiment of the present invention; 
         FIG. 9  is a detailed block diagram of a column decoder shown in  FIG. 8 ; 
         FIG. 10  is a schematic block diagram of s semiconductor memory device according to further another embodiment of the present invention; and 
         FIG. 11  is a detailed block diagram of a column decoder shown in  FIG. 10 . 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention will now be described in connection with preferred embodiments with reference to the accompanying drawings. 
       FIG. 3  is a schematic block diagram of s semiconductor memory device according to an embodiment of the present invention.  FIG. 3  shows an example of an X16 DRAM in which a 16 number of data can be processed at once. 
     Referring to  FIG. 3 , a semiconductor memory device  100  includes a memory cell array  101 , a row decoder  102 , a column decoder  103 , first and second sense amplifier groups  104 ,  105  and a data I/O circuit  106 . 
     The memory cell array  101  includes first and second column groups CBG 1 , CBG 2 . The first column group CBG 1  includes column memory blocks CB 1  to CB 4 . The second column group CBG 2  includes column memory blocks CB 5  to CB 8 . Though not shown in the drawing, each of the column memory blocks CB 1  to CB 8  includes a plurality of memory cells that share word lines WL 1  to WLK (K is an integer). The number of memory cells connected to one word line, of memory cells of each of the column memory blocks CB 1  to CB 8 , can be set to 4×(2 J−1 ) (J is an integer). For example, when J is 9, the number of memory cells connected to one word line is 1K (1×1024). The construction of the column memory blocks CB 1  to CB 8  will be described in more detail with reference to  FIG. 5 . 
     The construction of the column memory blocks CB 1  to CB  8  is the same. Therefore, only the column memory block CB 1  will be described as an example. The column memory block CB 1  includes a plurality of memory cell mats CM disposed in matrix form. Local I/O lines LIO 0  to LIO 3  parallel to word lines WL 1  to WLK are disposed in twos between the memory cell mats CM. Furthermore, the local I/O lines LIO 0  to LIO 3  are also disposed in two at both sides of the outmost side of the memory cell mats CM. The local I/O lines LIO 0  to LIO 3  are respectively connected to four main local I/O lines MLIO. Reference will be made to an exaggerated portion of the memory cell mat CM in  FIG. 5 . 
     The memory cell mat CM includes a memory cell block  160 , sense amplifiers SAU 1  to SAUM, SAL 1  to SALM (M is an integer) and Y-select circuits SU 1  to SUM, SL 1  to SLM (M is an integer). The memory cell block  160  includes a plurality of memory cells. The sense amplifiers SAU 1  to SAUM, SAL 1  to SALM sense and amplify a voltage difference of bit lines BL, BLB connected to the plurality of memory cells and output read data. The Y-select circuits SU 1  to SUM, SL 1  to SLM output the read data, which are received from the sense amplifiers SAU 1  to SAUM, SAL 1  to SALM, to the local I/O lines LIO 0  to LIO 3 , respectively, in response to column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 ), respectively. Four Y-select circuits SU 1 , SU 2 , SL 1  and SL 2  are operated in response to one column decoding signal (e.g., DEC 1 _ 1 ). 
     The row decoder  102  decodes a row address signal (RADD) and activates one of the word lines WL 1  to WLK according to the decoding result. 
     The column decoder  103  decodes a column address signal (CADD) in response to a logic value of one (e.g., AYJ) of bits (AY 1  to AYJ) (J is an integer) of the column address signal (CADD), and outputs a column decoding signals (not shown). The column decoder  103  will be described in detail below with reference to  FIG. 4 . The column decoder  103  includes a select circuit  110 , first and second address drivers  120 ,  130 , and first and second decoding units  140 ,  150 . 
     The select circuit  110  receives the most significant bit (AYJ) of the bits (AY 1  to AYJ) of the column address signal (CADD) as a select signal. The select circuit  110  can be implemented using a demultiplexer. The select circuit  110  outputs bits (AY 1  to AY(J−1)) to one of the first and second output terminals OUT 1 , OUT 2 ) according to a logic value of the select signal (AYJ). In more detail, the select circuit  110  outputs the bits (AY 1  to AY(J−1)) to the first output terminal OUT 1  when according to a logic value of the select signal (AYJ) is ‘0’, and outputs the bits (AY 1  to AY(J−1)) to a second output terminal OUT 2  when a logic value of the select signal (AYJ) is ‘1’. 
     The first address driver  120  buffers the bits (AY 1  to AY(J−1)) received from the first output terminal OUT 1 . The second address driver  130  buffers the bits (AY 1  to AY(J−1)) received from the second output terminal OUT 2 . 
     The first decoding unit  140  includes address decoders  141  to  144 . The address decoder  141  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 ) to the column memory block CB 1 . The address decoder  142  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 2 _ 1  to DEC 2 _ 2   J−1 ) to the column memory block CB 2 . The address decoder  143  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 3 _ 1  to DEC 3 _ 2   J−1 ) to the column memory block CB 3 . The address decoder  144  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 4 _ 1  to DEC 4 _ 2   J−1 ) to the column memory block CB 4 . 
     The second decoding unit  150  includes address decoders  151  to  154 . The address decoder  151  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 5 _ 1  to DEC 5 _ 2   J−1 ) to the column memory block CB 5 . The address decoder  152  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 6 _ 1  to DEC 6 _ 2   J−1 ) to the column memory block CB 6 . The address decoder  153  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 7 _ 1  to DEC 7 _ 2   J−1 ) to the column memory block CB 7 . The address decoder  154  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 8 _ 1  to DEC 8 _ 2   J−1 ) to the column memory block CB 8 . 
     Referring back to  FIG. 3 , in a read operation, each of the column memory blocks CB 1  to CB 4  outputs internal data (not shown) according to the column decoding signal. This will be described in more detail. 
     The column memory block CB 1  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 1 ) in response to the column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 ). The column memory block CB 2  outputs the four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 2 ) in response to the column decoding signals (DEC 2 _ 1  to DEC 2 _ 2   J−1 ). The column memory block CB 3  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 3 ) in response to the column decoding signals (DEC 3 _ 1  to DEC 3 _ 2   J−1 ). The column memory block CB 4  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 4 ) in response to the column decoding signals (DEC 4 _ 1  to DEC 4 _ 2   J−1 ). In the same manner as the column memory blocks CB 1  to CB 4 , the column memory blocks CB 5  to CB 8  also output internal data (not shown) through main local I/O line groups (L 5  to L 8 ) in response to the column decoding signals (DEC 5 _ 1  to DEC 5 _ 2   J−1 , DEC 6 _ 1  to DEC 6 _ 2   J−1 , DEC 7 _ 1  to DEC 7 _ 2   J−1  and DEC 8 _ 1  to DEC 8 _ 2   J−1 ), respectively. When the column memory blocks CB 1  to CB 4  output the internal data, the column memory blocks CB 5  to CB 8  do not output the internal data. 
     Meanwhile, in a write operation, the column memory blocks CB 1  to CB 4  or CB 5  to CB 8  receive input data (not shown) through the main local I/O line groups (L 1  to L 4  or L 5  to L 8 ), respectively, in response to the column decoding signals (DEC( 1  to  4 )_ 1  to DEC( 1  to  4 )_ 2   J−1 , or DEC( 5  to  8 )_ 1  to DEC( 5  to  8 )_ 2   J−1 ). 
     The first sense amplifier group  104  includes main sense amplifiers MSA 1  to MSA 4 . The main sense amplifier MSA 1  amplifies the four-bit internal data, which are received form the column memory block CB 1  through the main local I/O lines MLIO of the main local I/O line group (L 1 ), and outputs the amplified data to the global I/O lines GIO 1  to GIO 4 . The main sense amplifier MSA 2  amplifies the four-bit internal data, which are received form the column memory block CB 2  through the main local I/O lines MLIO of the main local I/O line group (L 2 ), and outputs the amplified data to the global I/O lines GIO 5  to GIO 8 . The main sense amplifier MSA 3  amplifies the four-bit internal data, which are received form the column memory block CB 3  through the main local I/O lines MLIO of the main local I/O line group (L 3 ), and outputs the amplified data to the global I/O lines GIO 9  to GIO 12 . The main sense amplifier MS 4  amplifies the four-bit internal data, which are received form the column memory block CB 4  through the main local I/O lines MLIO of the main local I/O line group (L 4 ), and outputs the amplified data to the global I/O lines GIO 13  to GIO 16 . 
     The second sense amplifier group  105  includes main sense amplifiers MSA 5  to MSA 8 . The operation of the main sense amplifiers MSA 5  to MSA 8  is the same as that of the main sense amplifiers MSA 1  to MSA 4 . Description thereof will be omitted for simplicity. 
     The data I/O circuit  106  outputs output data DO 1  to DO 16  to the I/O pads (PD 1  to PD 16 ) in response to the amplified data received from the main sense amplifiers MSA 1  to MSA 4  or MSA 5  to MSA 8  through the global I/O lines GIO 1  to GIO 16 . 
     A read operation process of the semiconductor memory device  100  will be then described. Assuming that the column address signal (CADD) is 9 bits (i.e., bits (AY 1  to AY 9 )) and the most significant bit (AY 9 ) is logic ‘0’. 
     The row decoder  102  decodes the row address signal (RADD) and activates one (e.g., WL 1 ) of the word lines WL 1  to WLK according to the decoding result. The select circuit  110  of the column decoder  103  outputs the bits (AY 1  to AY 8 ) to the first output terminal OUT 1  since the most significant bit (AY 9 ) is logic ‘0’. The first address driver  120  outputs the bits (AY 1  to AY 8 ), which are received from the first output terminal OUT 1 , to the address decoders  141  to  144  of the first decoding unit  140 , respectively. The address decoders  141  to  144  decode the bits (AY 1  to AY 8 ), respectively, and output the column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 , DEC 2 _ 1  to DEC 2 _ 2   J−1 , DEC 3 _ 1  to DEC 3 _ 2   J−1  and DEC 4 _ 1  to DEC 4 _ 2   J−1 ) to the column memory blocks CB 1  to CB 4 , respectively. A this time, the second address driver  130  and the second decoding unit  150  do not operate. 
     Consequently, the column memory blocks CB 1  to CB 4  output 16-bit internal data through the main local I/O line groups L 1  to L 4  in response to the column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 , DEC 2 _ 1  to DEC 2 _ 2   J−1 , DEC 3 _ 1  to DEC 3 _ 2   J−1  and DEC 4 _ 1  to DEC 4 _ 2   J−1 ). The main sense amplifiers MSA 1  to MSA 4  of the first sense amplifier group  104  amplify the 16-bit internal data and output the amplified data to the global I/O lines GIO 1  to GIO 16 . The data I/O circuit  106  outputs the output data (DO 1  to DO 16 ) to the I/O pads (PD 1  to PD 16 ) in response to the amplified data, which are received from the main sense amplifiers MSA 1  to MSA 4  through the global I/O lines GIO 1  to GIO 16 . 
     As described above, in the semiconductor memory device  100 , any one of the first and second decoding units  140 ,  150  of the column decoder  103  operates according to a logic value of the most significant bit (AYJ) of the column address signal (CADD). It is thus possible to significantly reduce a switching current that is unnecessarily consumed. Furthermore, since the memory cell array  101  is divided into the column memory blocks CB 1  to CB 8 , the number of memory cells connected to one word line, of memory cells included in each of the column memory blocks CB 1  to CB 8  can be reduced. 
     When the number of memory cells connected to one word line is reduced as described above, the length (A 2 ) of each of the local I/O lines LIO 1  to LIO 4  included in each of the column memory blocks CB 1  to CB 8  can be reduced. It is thus possible to a voltage of data signals, which are transferred through the local I/O lines LIO 1  to LIO 4 , from being attenuated. For example, in the case of the column address signal (CADD) is 9 bits, the number of memory cell connected to one word line, of memory cells included in one column memory block (e.g., CB 1 ) is 1K (1×1024). In this case, the length (A 2 ) is shorter than the length (A 1 ) shown in  FIG. 1 . 
       FIG. 6  is a schematic block diagram of a semiconductor memory device according to another embodiment of the present invention, and shows an example of an X16 DRAM. 
     Referring to  FIG. 6 , a semiconductor memory device  200  includes a memory cell array  201 , a row decoder  202 , a column decoder  203 , first to fourth sense amplifier groups  204  to  207  and a data I/O circuit  208 . The construction and operation of the semiconductor memory device  200  are the same as those of the semiconductor memory device  100  shown in  FIG. 3  except for the memory cell array  201 , the column decoder  203  and the first to fourth sense amplifier groups  204  to  207 . Therefore, only the memory cell array  201 , the column decoder  203  and the first to fourth sense amplifier groups  204  to  207  will be described. 
     The memory cell array  201  includes first to fourth column groups CBG 1  to CBG 4 . The column group CBG 1  includes column memory blocks CB 1  to CB 4 . The column group CBG 2  includes column memory blocks CB 5  to CB 8 . The column group CBG 3  includes column memory blocks CB 9  to CB 12 . The column group CBG 4  includes column memory blocks CB 13  to CB 16 . The construction of the column memory blocks CB 1  to CB 16  is the same as that of the column memory block CB 1  shown in  FIG. 5 . Description thereof will be omitted in order to avoid redundancy. 
     Referring to  FIG. 7 , the column decoder  203  includes a select circuit  210 , first to fourth address drivers  220  to  250  and first to fourth decoding units  260  to  290 . 
     The select circuit  210  receives the most significant two bits (AYJ, AY(J−1)) of bits (AY 1  to AYJ) of a column address signal (CADD) as select signals. The select circuit  210  can be implemented using a demultiplexer. Furthermore, the select circuit  210  outputs bits (AY 1  to AY(J−2)) to any one of first to fourth output terminals OUT 1  to OUT 4  according to logic values of the select signals (AYJ, AY(J−1)). In more detail, the select circuit  210  outputs the bits (AY 1  to AY(J−2)) to the first output terminal OUT 1  when logic values of the select signals (AYJ, AY(J−1)) are ‘00’, and outputs the bits (AY 1  to AY(J−2)) to the second output terminal OUT 2  when logic values of the select signals (AYJ, AY(J−1)) are ‘01’. In addition, the select circuit  210  outputs the bits (AY 1  to AY(J−2)) to the third output terminal OUT 3  when logic values of the select signals (AYJ, AY(J−1)) are ‘10’. The select circuit  210  outputs the bits (AY 1  to AY(J−2)) to the fourth output terminal OUT 4  when logic values of the select signals (AYJ, AY(J−1)) are ‘11’. 
     The first address driver  220  buffers the bits (AY 1  to AY(J−2)) received from the first output terminal OUT 1 . The second address driver  230  buffers the bits (AY 1  to AY(J−2)) received from the second output terminal OUT 2 . The third address driver  240  buffers the bits (AY 1  to AY(J−2)) received from the third output terminal OUT 3 . The fourth address driver  250  buffers the bits (AY 1  to AY(J−2)) received from the fourth output terminal OUT 4 . 
     The first decoding unit  260  includes address decoders  261  to  264 . The address decoder  261  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−2 ) to the column memory block CB 1 . The address decoder  262  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 2 _ 1  to DEC 2 _ 2   J−2 ) to the column memory block CB 2 . Furthermore, the address decoder  263  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 3 _ 1  to DEC 3 _ 2   J−2 ) to the column memory block CB 3 . The address decoder  264  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 4 _ 1  to DEC 4 _ 2   J−2 ) to the column memory block CB 4 . 
     The second decoding unit  270  includes address decoders  271  to  274 . The address decoders  271  to  274  decode the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 5 _ 1  to DEC 5 _ 2   J−2 , DEC 6 _ 1  to DEC 6 _ 2   J−2 , DEC 7 _ 1  to DEC 7 _ 2   J−2  and DEC 8 _ 1  to DEC 8 _ 2   J−2 ) to the column memory blocks CB 5  to CB 8 , respectively. 
     The third decoding unit  280  includes address decoders  281  to  284 . The address decoders  281  to  284  decode the bits (AY 1  to AY(J−2)) and output column decoding signals (DEC 9 _ 1  to DEC 9 _ 2   J−2 , DEC 10 _ 1  to DEC 10 _ 2   J−2 , DEC 11 _ 1  to DEC 11 _ 2   J−2  and DEC 12 _ 1  to DEC 12 _ 2   J−2 ) to the column memory blocks CB 9  to CB 12 , respectively. 
     The fourth decoding unit  290  includes address decoders  291  to  294 . The address decoders  291  to  294  decode the bits (AY 1  to AY(J−2)) and output column decoding signals (DEC 13 _ 1  to DEC 13 _ 2   J−2 , DEC 14 _ 1  to DEC 14 _ 2   J−2 , DEC 15 _ 1  to DEC 15 _ 2   J−2  and DEC 16 _ 1  to DEC 16 _ 2   J−2 ) to the column memory blocks CB 13  to CB 16 , respectively. 
     Referring back to  FIG. 6 , in the read operation, the column memory blocks CB 1  to CB 16  output internal data (not shown) in response to corresponding column decoding signals. When one of first to fourth column groups CBG 1  to CBG 4  outputs internal data, the remaining column groups do not output internal data. 
     The first sense amplifier group  204  includes main sense amplifiers MSA 1  to MSA 4 . The main sense amplifiers MSA 1  to MSA 4  are connected to the column memory blocks CB 1  to CB 4 , respectively, through main local I/O lines MLIO of main local I/O line groups L 1  to L 4 , respectively. The main sense amplifiers MSA 1  to MSA 4  amplify four-bit internal data, which are received from the column memory blocks CB 1  to CB 4 , respectively, and output the amplified data to global I/O lines GIO 1  to GIO 16 , respectively. 
     The second sense amplifier group  205  includes main sense amplifiers MSA 5  to MSA 8 . The main sense amplifiers MSA 5  to MSA 8  are connected to the column memory blocks CB 5  to CB 8 , respectively, through main local I/O lines MLIO of main local I/O line groups L 5  to L 8 , respectively. The main sense amplifiers MSA 5  to MSA 8  amplify four-bit internal data, which are received from the column memory blocks CB 5  to CB 8 , respectively, and output the amplified data to the global I/O lines GIO 1  to GIO 16 , respectively. 
     The third sense amplifier group  206  includes main sense amplifiers MSA 9  to MSA 12 . The main sense amplifiers MSA 9  to MSA 12  are connected to the column memory blocks CB 9  to CB 12 , respectively, through main local I/O lines MLIO of main local I/O line groups L 9  to L 12 , respectively. The main sense amplifiers MSA 9  to MSA 12  amplify the four-bit internal data, which are received from the column memory blocks CB 9  to CB 12 , respectively, and output the amplified data to the global I/O lines GIO 1  to GIO 16 , respectively. 
     The fourth sense amplifier group  207  includes main sense amplifiers MSA 13  to MSA 16 . The main sense amplifiers MSA 13  to MSA 16  are connected to the column memory blocks CB 13  to CB 16 , respectively, through main local I/O lines MLIO of main local I/O line groups L 13  to L 16 , respectively. The main sense amplifiers MSA 13  to MSA 16  amplify four-bit internal data, which are received form the column memory blocks CB 13  to CB 16 , respectively, and output the amplified data to the global I/O lines GIO 1  to GIO 16 , respectively. 
       FIG. 8  is a schematic block diagram of s semiconductor memory device according to further another embodiment of the present invention, and shows an example of an X8 DRAM, which ca process an 8 number of data at once. Referring to  FIG. 8 , a semiconductor memory device  300  includes a memory cell array  301 , a row decoder  302 , a column decoder  303 , first and second sense amplifier groups  304 ,  305 , and a data I/O circuit  306 . 
     The construction and operation of the semiconductor memory device  300  is the same as those of the semiconductor memory device  100  shown in  FIG. 3  except for the memory cell array  301 , the column decoder  303 , the first and second sense amplifier groups  304 ,  305 , and the number of global I/O lines. Therefore, only the memory cell array  301 , the column decoder  303 , and the first and second sense amplifier groups  304 ,  305  will be describe with reference to  FIG. 8 . 
     The memory cell array  301  includes first and second column groups CBG 11 , CBG 12 . The first column group CBG 11  includes column memory blocks CB 11 , CB 12  and the second column group CBG 12  includes column memory blocks CB 13 , CB 14 . Though not shown in the drawing, each of the column memory blocks CB 11  to CB 14  includes a plurality of memory cells that share word lines WL 1  to WLK (K is an integer). The number of memory cells connected to one word line, of memory cells of each of the column memory blocks CB 11  to CB 14 , can be 4×(2 J−1 ) (J is an integer). For example, when J is 9 (i.e., the column address signal is 9 bits), the number of memory cells connected to one word line is 1K (1×1024). The construction of the column memory blocks CB 11  to CB 14  is the same as that of the column memory block CB 1 , which has been described with reference to  FIG. 5 . Description thereof will be omitted for simplicity. 
     The column decoder  303  decodes a column address signal (CADD) in response to a logic value of one (e.g., AYJ) of bits (AY 1  to AYJ) (J is an integer) of a column address signal (CADD) and outputs column decoding signals (not shown). The column decoder  303  will be described in more detail with reference to  FIG. 9 . 
     The column decoder  303  includes a select circuit  310 , first and second address drivers ( 320 ,  330 ), and first and second decoding units  340 ,  350 . 
     The select circuit  310  receives the most significant bit (AYJ) of the bits (AY 1  to AYJ) of the column address signal (CADD) as a select signal. The select circuit  310  can be implemented using a demultiplexer. The select circuit  310  outputs bits (AY 1  to AY(J−1)) to any one of first and second output terminals OUT 1 , OUT 2  according to a logic value of the select signal (AYJ). In more detail, the select circuit  310  outputs the bits (AY 1  to AY(J−1)) to the first output terminal OUT 1  when a logic value of the select signal (AYJ) is ‘0’ and outputs, the bits (AY 1  to AY(J−1)) to the second output terminal OUT 2  when a logic value of the select signal (AYJ) is ‘1’. 
     The first address driver  320  buffers the bits (AY 1  to AY(J−1)) received from the first output terminal OUT 1 . The second address driver  330  buffers the bits (AY 1  to AY(J−1)) received from the second output terminal OUT 2 . 
     The first decoding unit  340  includes address decoders  341 ,  342 . The address decoder  341  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 ) to the column memory block CB 11 . The address decoder  342  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 2 _ 1  to DEC 2 _ 2   J−1 ) to the column memory block CB 12 . 
     The second decoding unit  350  includes address decoders  351 ,  352 . The address decoder  351  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 3 _ 1  to DEC 3 _ 2   J−1 ) to the column memory block CB 13 . The address decoder  352  decodes the bits (AY 1  to AY(J−1)) and outputs column decoding signals (DEC 4 _ 1  to DEC 4 _ 2   J−1 ) to the column memory block CB 14 . 
     Referring back to  FIG. 8 , in the read operation, each of the column memory blocks CB 11  to CB 14  outputs internal data (not shown) according to a column decoding signal. This will be described in more detail below. 
     The column memory block CB 11  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 11 ) in response to the column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−1 ). The column memory block CB 12  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 12 ) in response to the column decoding signals (DEC 2 _ 1  to DEC 2 _ 2   J−1 ). The column memory block CB 13  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 13 ) in response to the column decoding signals (DEC 3 _ 1  to DEC 3 _ 3   J−1 ). The column memory block CB 14  outputs four-bit internal data (not shown) through main local I/O lines MLIO of a main local I/O line group (L 14 ) in response to the column decoding signals (DEC 4 _ 1  to DEC 4 _ 2   J−1 ). When the column memory blocks CB 11 , CB 12  output the internal data, the column memory blocks CB 13 , CB 14  do not output the internal data. 
     The first sense amplifier group  304  includes main sense amplifiers MSA 1 , MSA 2 . The main sense amplifier MSA 1  amplifies the four-bit internal data, which are received from the column memory block CB 11  through the main local I/O lines MLIO of the main local I/O line group (L 11 ), and outputs the amplified data to global I/O lines GIO 1  to GIO 4 . The main sense amplifier MSA 2  amplifies the four-bit internal data, which are received from the column memory block CB 12  through the main local I/O lines MLIO of the main local I/O line group (L 12 ), and outputs the amplified data to global I/O lines GIO 5  to GIO 8 . The main sense amplifier MSA 3  amplifies the four-bit internal data, which are received from the column memory block CB 13  through the main local I/O lines MLIO of the main local I/O line group (L 13 ), and outputs the amplified data to global I/O lines GIO 1  to GIO 4 . The main sense amplifier MSA 14  amplifies the four-bit internal data, which are received from the column memory block CB 14  through the main local I/O lines MLIO of the main local I/O line group (L 14 ), and outputs the amplified data to global I/O lines GIO 5  to GIO 8 . 
     The data I/O circuit  306  outputs output data (DO 11  to DO 18 ) to I/O pads PD 11  to PD 18  in response to the amplified data, which are received from the main sense amplifiers MSA 1 , MSA 2  or MSA 3 , MSA 4  from the global I/O lines GIO 1  to GIO 8 . 
       FIG. 10  is a schematic block diagram of s semiconductor memory device according to further another embodiment of the present invention, and shows an X8 DRAM which can process an 8 number of data at once. 
     Referring to  FIG. 10 , a semiconductor memory device  400  includes a memory cell array  401 , a row decoder  402 , a column decoder  403 , first to fourth sense amplifier groups  404  to  407 , and a data I/O circuit  408 . The construction and operation of the semiconductor memory device  400  are the same as those of the semiconductor memory device  300  shown in  FIG. 8  except for the memory cell array  401 , the column decoder  403 , and the first to fourth sense amplifier groups  404  to  407 . Therefore, only the memory cell array  401 , the column decoder  403 , and the first to fourth sense amplifier groups  404  to  407  will be described with reference to  FIG. 10 . 
     The memory cell array  401  includes first to fourth column groups CBG 11  to CBG 14 . The column group CBG 11  includes column memory blocks CB 11 , CB 12  and the column group CBG 12  includes column memory blocks CB 13 , CB 14 . The column group CBG 13  includes column memory blocks CB 15 , CB 16  and the column group CBG 14  includes column memory blocks CB 17 , CB 18 . In this case, the construction of the column memory blocks CB 11  to CB 18  is the same as that of column memory block CB 1  that has been described in detail with reference to  FIG. 5 . Description thereof will be omitted for simplicity. 
     Referring to  FIG. 11 , the column decoder  403  includes a select circuit  410 , first to fourth address drivers  420  to  450  and first to fourth decoding units  460  to  490 . 
     The select circuit  410  receives the most significant two bits (AYJ, AY(J−1)) of bits (AY 1  to AYJ) of a column address signal (CADD) as select signals. The select circuit  410  can be implemented using a demultiplexer. The select circuit  410  outputs bits (AY 1  to AY(J−2)) to any one of first to fourth output terminals OUT 1  to OUT 4  according to logic values of the select signals (AYJ, AY(J−1)). In more detail, the select circuit  410  outputs the bits (AY 1  to AY(J−2)) to the first output terminal OUT 1  when logic values of the select signals (AYJ, AY(J−1)) are ‘00’, and outputs the bits (AY 1  to AY(J−2)) to the second output terminal OUT 2  when logic values of the select signals (AYJ, AY(J−1)) are ‘01’. In addition, the select circuit  410  outputs the bits (AY 1  to AY(J−2)) to the third output terminal OUT 3  when logic values of the select signals (AYJ, AY(J−1)) are ‘10’. The select circuit  410  outputs the bits (AY 1  to AY(J−2)) to the fourth output terminal OUT 4  when logic values of the select signals (AYJ, AY(J−1)) are ‘11’. 
     The first address driver  420  buffers the bits (AY 1  to AY(J−2)) received from the first output terminal OUT 1 . The second address driver  430  buffers the bits (AY 1  to AY(J−2)) received from the second output terminal OUT 2 . The third address driver  440  buffers the bits (AY 1  to AY(J−2)) received from the third output terminal OUT 3 . The fourth address driver  450  buffers the bits (AY 1  to AY(J−2)) received from the fourth output terminal OUT 4 . 
     The first decoding unit  460  includes address decoders  461 ,  463 . The address decoder  461  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 1 _ 1  to DEC 1 _ 2   J−2 ) to the column memory block CB 11 . The address decoder  462  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 2 _ 1  to DEC 2 _ 2   J−2 ) to the column memory block CB 12 . 
     The second decoding unit  470  includes address decoders  471 ,  472 . The address decoder  471  decodes bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 3 _ 1  to DEC 3 _ 2   J−2 ) to the column memory block CB 13 . The address decoder  472  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 4 _ 1  to DEC 4 _ 2   J−2 ) to the column memory block CB 14 . 
     The third decoding unit  480  includes address decoders  481 ,  482 . The address decoder  481  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 5 _ 1  to DEC 5 _ 2   J−2 ) to the column memory block CB 15 . The address decoder  482  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 6 _ 1  to DEC 6 _ 2   J−2 ) to the column memory block CB 16 . 
     The third decoding unit  490  includes the address decoders  491 ,  492 . The address decoder  491  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 7 _ 1  to DEC 7 _ 2   J−2 ) to the column memory block CB 17 . The address decoder  492  decodes the bits (AY 1  to AY(J−2)) and outputs column decoding signals (DEC 8 _ 1  to DEC 8 _ 2   J−2 ) to the column memory block CB 18 . 
     Referring back to  FIG. 10 , in the read operation, the column memory blocks CB 11  to CB 18  output internal data (not shown) according to the column decoding signals. When any one of the first to fourth column groups CBG 11  to CBG 14  outputs the internal data, the remaining column groups do not output the internal data. 
     The first sense amplifier group  404  includes main sense amplifiers MSA 1 , MSA 2 . The main sense amplifiers MSA 1 , MSA 2  are connected to the column memory blocks CB 11 , CB 12 , respectively, through the main local I/O lines MLIO of the main local I/O line groups (L 11 , L 12 .) The main sense amplifiers MSA 1 , MSA 2  amplify the four-bit internal data, which are received from the column memory blocks CB 11 , CB 12 , respectively, and output the amplified data to global I/O lines GIO 1  to GIO 8 , respectively. 
     The second sense amplifier group  405  includes the main sense amplifiers MSA 3 , MSA 4 . The main sense amplifiers MSA 3 , MSA 4  are connected to the column memory blocks CB 13 , CB 14 , respectively, through the main local I/O lines MLIO of the main local I/O line groups (L 13 , L 14 ), respectively. The main sense amplifiers MSA 3 , MSA 4  amplify the four-bit internal data, which are received from the column memory blocks CB 13 , CB 14 , respectively, and output the amplified data to the global I/O lines GIO 1  to GIO 8 . 
     The third sense amplifier group  406  includes the main sense amplifiers MSA 5 , MSA 6 . The main sense amplifiers MSA 5 , MSA 6  are connected to the column memory blocks CB 15 , CB 16 , respectively, through the main local I/O lines MLIO of the main local I/O line groups (L 15 , L 16 ), respectively. The main sense amplifiers MSA 5 , MSA 6  amplify four-bit internal data, which are received from the column memory blocks CB 15 , CB 16 , respectively, and output the amplified data to the global I/O lines GIO 1  to GIO 8 . 
     The fourth sense amplifier group  407  includes the main sense amplifiers MSA 7 , MSA 8 . The main sense amplifiers MSA 7 , MSA 8  are connected to the column memory blocks CB 17 , CB 18 , respectively, through the main local I/O lines MLIO of the main local I/O line groups (L 17 , L 18 ), respectively. The main sense amplifiers MSA 7 , MSA 8  amplify the four-bit internal data, respectively, which are received from the column memory blocks CB 17 , CB 18 , and output the amplified data to the global I/O lines GIO 1  to GIO 8 . 
     In the semiconductor memory device and read operation method thereof, any one of a plurality of decoding units of a column decoder is selectively driven. It is thus possible to reduce unnecessary switching current. 
     Furthermore, in the semiconductor memory device and read operation method thereof according to the present invention, the number of memory cell connected to one word line, of memory cells included in each of column memory blocks, is reduced. Therefore, the length of a local I/O line can be shortened and a voltage of data signals transferred through the local I/O line can be prevented form being attenuated. 
     Although the foregoing description has been made with reference to the preferred embodiments, it is to be understood that changes and modifications of the present invention may be made by the ordinary skilled in the art without departing from the spirit and scope of the present invention and appended claims.