Abstract:
A device and method for controlling self-refresh is disclosed, which reduces current when a semiconductor device stays in a self-refresh operation. The device for controlling self-refresh includes: a bulk voltage controller configured to combine an idle signal indicating an active termination state of a bank and a self-refresh signal so as to generate a control signal for controlling a bulk voltage, a bulk voltage driver configured to vary a level of the bulk voltage in response to the control signal, and output the bulk voltage with a different level, and a refresh controller configured to output the self-refresh active signal upon receiving the bulk voltage as a bulk bias voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C 119(a) to Korean Patent Application No. 10-2012-0150995 filed on Dec. 21, 2012 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    Embodiments of the present invention generally relate to a device and method for controlling self-refresh, and more particularly to a technology for reducing a current when a semiconductor device is in a self-refresh operation. 
         [0003]    Generally, in a memory unit of a dynamic random access memory (DRAM), a plurality of unit cells each of which contains one transistor and one capacitor, is configured in the form of a matrix in a manner where the unit cells are arranged in a plurality of rows and columns. Addresses designate such rows and columns, and commands for performing the read/write operation in each cell unit are provided to such addresses. 
         [0004]    A DRAM cell stores charge-type data in a cell, but due to material limitations of silicon requisite for cell fabrication, the data needs to be periodically recharged to prevent data loss. 
         [0005]    Data stored in a DRAM cell is recharged by eliminating leakage current, sensing and amplifying the data of the cell, and rewriting the sensed and amplified data back into the cell. This recharge operation is referred to as a refresh operation. 
         [0006]    Effectively, the refresh operation reads data from the DRAM cell, amplifies the read data, and re-stores the amplified data. The refresh operation is performed by a bit line sense amplifier (sense-amp) located close to a memory cell array. 
         [0007]    The refresh operation begins when a refresh command is received, after which one of a plurality of rows contained in a unit cell array is selected on the basis of a row address activated by the refresh command. 
         [0008]    As a corresponding word line of the selected row is charged with a constant potential, all cells connected to the selected row are activated, and data is transmitted to a bit line through an activated cell. Data is amplified due to the operation of the bit line sense-amplifier, and is subsequently stored in the selected cell. 
         [0009]    The most representative refresh methods for synchronous DRAMs are classified into an auto-refresh method and a self-refresh method. In an auto-refresh method, an auto-refresh operation is performed through an external terminal of a synchronous DRAM chip at a predetermined time. 
         [0010]    However, in a self-refresh method, when a command is provided, a subsequent refresh operation is automatically carried out in response to an indication message from a timer embedded in a chip. 
         [0011]    A method for entering the self-refresh mode in the synchronous DRAM is synchronized with a clock signal. That is, an entry mode is determined by external signals such as a RAS bar signal (RAS#), a CAS bar signal (CAS#), a column selection signal (CS#), a clock enable signal (CKE), etc. at a positive edge of the clock signal. 
         [0012]    However, there is a need for a condition capable of terminating a self-refresh operation either after the refresh operation is executed on the basis of a constant internal period during the self-refresh operation, or at any time during the refresh operation. That is, during the self-refresh operation, internal operations of the chip are asynchronously operated and are not affected by external clocks. 
         [0013]    Particularly, the self-refresh termination operation is achieved by deactivation of a pin of a clock enable signal (CKE). Therefore, the self-refresh termination operation is asynchronously achieved. 
         [0014]    A method for terminating the self-refresh operation is also achieved by reactivation of a clock enable signal. That is, as the clock enable signal is activated, the external clock signal is re-applied to the chip, and the chip operation is re-affected by the external clock signal. After completion of the self-refresh operation, a predetermined delay time elapses, and subsequently another operation starts. 
         [0015]    The operation intervals of the self-refresh mode can be classified into a first operation interval, a second operation interval, and a third operation interval. According to the first operation interval, the synchronous DRAM is synchronized with the clock signal to enter the self-refresh mode. According to the second operation interval, the internal refresh operation of the synchronous DRAM is asynchronously performed. According to the third operation interval, the synchronous DRAM is asynchronously terminated. 
         [0016]    Since how long a mobile product can function with an embedded battery is an important factor in the product, it is very important for a mobile DRAM mounted to such products to reduce a self-refresh current generated in a DRAM standby state. 
       SUMMARY 
       [0017]    Various embodiments of the present invention are directed to providing a self-refresh control device that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
         [0018]    An embodiment of the present invention relates to a method for reducing a current requisite for a self-refresh operation using a bulk-bias control scheme, and stably performing the self-refresh operation by controlling a signal indicating termination of a self-refresh active operation. 
         [0019]    In accordance with an embodiment of the present invention, a self-refresh control device includes: a bulk voltage controller configured to combine an idle signal indicating an active termination state of a bank and a self-refresh signal so as to generate a control signal for controlling a bulk voltage; a bulk voltage driver configured to vary a level of the bulk voltage in response to the control signal, and output the bulk voltage with a different level; and a refresh controller configured to output the a self-refresh active signal upon receiving the bulk voltage as a bulk bias voltage. 
         [0020]    In accordance with another embodiment of the present invention, a method for controlling self-refresh, comprising the steps of: generating an idle signal by combining bank addresses; combining the idle signal indicating an active termination state of a bank and a self-refresh signal so as to generate a control signal for controlling a bulk voltage; varying a level of the bulk voltage in response to the control signal, and outputting the bulk voltage with a different level; and outputting a self-refresh active signal upon receiving the bulk voltage as a bulk bias voltage. 
         [0021]    In accordance with another embodiment of the present invention, a method for controlling self-refresh, comprising the steps of: using a bulk-bias control scheme; and stably performing the self-refresh operation by controlling a signal indicating termination of a self-refresh active operation. 
         [0022]    It is to be understood that both the foregoing general description and the following detailed description of the present invention are explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a block diagram illustrating a self-refresh control device according to an embodiment of the present invention. 
           [0024]      FIG. 2  is a detailed circuit diagram illustrating a control signal generator of  FIG. 1 . 
           [0025]      FIG. 3  is a detailed circuit diagram illustrating a bulk voltage controller of  FIG. 1 . 
           [0026]      FIG. 4  is a detailed circuit diagram illustrating a bulk voltage driver of  FIG. 1 . 
           [0027]      FIG. 5  is a detailed circuit diagram illustrating a refresh controller of  FIG. 1 . 
           [0028]      FIG. 6  is a timing diagram illustrating a self-refresh control device according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0030]    Referring to  FIG. 1 , the self-refresh control device may include a control signal generator  10 , a bulk voltage controller  100 , a bulk voltage driver  200 , a refresh controller  300 , and a memory cell  400 . 
         [0031]    The control signal generator  10  may combine a plurality of bank addresses BA, such as BA&lt; 0 &gt;-BA&lt; 7 &gt; (not illustrated), to generate an idle signal RASIDLE. The idle signal RASIDLE may transition to a low level when none of the bank addresses from among a plurality of bank addresses (BA&lt; 0 &gt;-BA&lt; 7 &gt;) is in an active state. 
         [0032]    The idle signal RASIDLE may be maintained at a high level when at least one bank address from among a plurality of bank addresses (BA&lt; 0 &gt;-BA&lt; 7 &gt;) is in an active state. That is, at least one bank from among a plurality of bank addresses (BA&lt; 0 &gt;-BA&lt; 7 &gt;) is activated in a specific interval in which the idle signal RASIDLE is activated to a high level. If the idle signal RASIDLE transitions to a low level, this may indicate that the active operation of all banks has been terminated. 
         [0033]    The bulk voltage controller  100  may output a control signal AB in response to a self-refresh signal SREF and an idle signal RASIDLE. The bulk voltage driver  200  may drive and output the bulk voltage VBULK in response to the control signal AB for the self-refresh active operation. 
         [0034]    The bulk voltage controller  100  may be configured to output the control signal AB having a high level when the idle signal RASIDLE is activated in the self refresh operation, that is, the self refresh signal SREF has a high level. Therefore, the bulk voltage driver  200  may not vary the level of the bulk voltage VBULK. 
         [0035]    On the other hand, if the active operation of all banks is terminated during the self-refresh active operation such that the idle signal RASIDLE is deactivated, the control signal AB is transitioned to a low level and subsequently outputted. Therefore, the bulk voltage driver  200  may be controlled to increase the level of the bulk voltage VBULK. 
         [0036]    The refresh controller  300  may receive the bulk voltage VBULK as a bulk bias voltage, and output an active signal ACT to the memory cell  400 . If the active signal ACT is activated, a word line of each memory cell  40  may be enabled such that the self-refresh operation of each bank is carried out. 
         [0037]    Referring to  FIG. 2 , the control signal generator  10  may include a plurality of NOR gates (NOR 1 -NOR 5 ), a plurality of NAND gates (ND 1 , ND 2 ), and an inverter IV 1 . 
         [0038]    The NOR gate NOR 1  may perform a NOR operation on bank addresses BA&lt; 0 &gt; and BA&lt; 1 &gt;, and output the NOR operation result. The NOR gate NOR 2  may perform a NOR operation on bank addresses BA&lt; 2 &gt; and BA&lt; 3 &gt;, and output the NOR operation result. The NOR gate NOR 3  may perform a NOR operation on bank addresses BA&lt; 4 &gt; and BA&lt; 5 &gt;, and output the NOR operation result. The NOR gate NOR 4  may perform a NOR operation on bank addresses BA&lt; 6 &gt; and BA&lt; 7 &gt;, and output the NOR operation result. 
         [0039]    The NAND gate ND 1  may perform a NAND operation on output signals of the NOR gates NOR 1  and NOR 2 . The NAND gate ND 2  may perform a NAND operation on output signals of the NOR gates NOR 3  and NOR 4 . The NOR gate NOR 5  may perform a NOR operation on output signals of the NAND gates ND 1  and ND 2 . The inverter IV 2  may invert the output signal of the NOR gate NOR 5  so as to output an idle signal RASIDLE. 
         [0040]    If at least one bank address from among bank addresses BA&lt; 0 &gt;-BA&lt; 7 &gt; is in an active state, the control signal generator  10  may output a high-level idle signal RASIDLE. If all bank addresses BA&lt; 0 &gt;-BA&lt; 7 &gt; are at a low level after completion of the active operation, the control signal generator  10  may transition the idle signal RASIDLE to a low level. 
         [0041]    Referring to  FIG. 3 , the bulk voltage controller  100  may include a delay unit  110 , a NAND gate ND 3 , a NOR gate NOR 6 , and a plurality of inverters IV 2 -IV 4 . The NAND gate ND 3 , the NOR gate NOR 6 , and a plurality of inverters IV 2 -IV 4  may correspond to logic operation units. 
         [0042]    The delay unit  110  may delay the self-refresh signal SREF for a predetermined period of time and output a delay signal PWDD. The NAND gate ND 3  may perform a NAND operation on the idle signal RASIDLE and the control signal AB. The inverter IV 3  may invert the output signal of the NAND gate ND 3 . 
         [0043]    The NOR gate NOR 6  may perform a NOR operation on the delay signal PWDD inverted by the inverter IV 2  and the output signal of the inverter IV 3 , such that it outputs a control signal A. The inverter IV 4  may invert the control signal A such that it outputs the control signal AB. 
         [0044]    Referring to  FIG. 4 , the bulk voltage driver  200  may include a first voltage supply unit  210  and a second voltage supply unit  220 . The first voltage supply unit  210  may provide a power-supply voltage VDD 1  as a bulk voltage VBULK, and the second voltage supply unit  220  may provide a peri-voltage VPERI as a bulk voltage VBULK. The peri-voltage VPERI may be lower than the power-supply voltage VDD 1  and indicate an external input voltage. 
         [0045]    The first voltage supply unit  210  may include a PMOS transistor P 1  disposed between the power-supply voltage VDD 1  input terminal and the bulk voltage (VBULK) output terminal, such that it receives the control signal AB through a gate terminal. 
         [0046]    The second voltage supply unit  220  may include a PMOS transistor P 2  disposed between the peri-voltage VPERI input terminal and the bulk voltage (VBULK) output terminal, such that it receives the control signal A through a gate terminal. 
         [0047]    Referring to  FIG. 5 , the refresh controller  300  may include a plurality of voltage drivers, such as a plurality of PMOS transistors P 3 -PN. The PMOS transistors P 3 -PN may be coupled in parallel between a peri-voltage VPERI input terminal and an active signal ACT output terminal, such that the bulk voltage VBULK may be applied to the PMOS transistors P 3 -PN through the bulk terminal. For example, the PMOS transistor may receive gates voltages having a high level to be turned on in the active mode, and may receive the gates voltages having a low level to be turned off in the self refresh mode. 
         [0048]    The self-refresh control device according to an embodiment of the present invention may be configured to use a PMOS bulk bias control scheme of the PMOS transistors P 3 -PN so as to reduce the self-refresh current. The self-refresh control device can reduce an off-leakage current of the PMOS transistors P 3 -PN using the bulk bias control scheme. 
         [0049]    The sub-threshold leakage current occurs in an off-state transistor. The off-leakage current may be inversely proportional to a threshold voltage Vt (not shown) of the transistor, and may be proportional to a drain-source voltage Vds (not shown). 
         [0050]    Therefore, in order to reduce the off leakage current during the self-refresh active operation, bulk voltage levels of the PMOS transistors P 3 -PN may be increased. In the self-refresh active operation mode, the first voltage supply unit  210  may be turned on such that the bulk voltage VBULK is increased to the power-supply voltage VDD 1 . In the normal mode, the second voltage supply unit  220  may be turned on such that the bulk voltage VBULK is reduced to the peri-voltage VPERI. 
         [0051]    The bulk bias control scheme using the self-refresh interval aims to reduce an off leakage current using transistor characteristics. The bulk bias control scheme applies a higher voltage than a source voltage to the bulk bias of the transistor, such that it can control the leakage current that flows from a source terminal to a drain terminal. 
         [0052]    However, the refresh operation may frequently be carried out. Accordingly, in order to reduce power consumption between the refresh entry and the refresh exit, the bulk voltage may be kept consistent for a predetermined period of time after the self-refresh operation begins. Referring to  FIG. 6 , the self-refresh signal SREF may be activated such that the self-refresh mode starts operation. Then, after a lapse of delay time of the delay unit  110 , the delay signal PWDD may transition to a high level. 
         [0053]    In the conventional art, after a lapse of a predetermined delay time after entering the self-refresh mode, the bulk voltage VBULK increases. However, when entering the self-refresh mode, a control signal for executing the self-refresh operation is generated such that the self-refresh active operation is performed per bank. 
         [0054]    That is, when the bulk voltage VBULK of a transistor increases in response to an input bulk bias, the active signal ACT may be activated. If the active operation is performed under the condition that the bulk voltage VBULK varies, a gate terminal of the transistor for the self-refresh operation may transition to a high or low level. 
         [0055]    As a result, the bulk voltage VBULK may become unstable such that it is impossible to stably perform the self-refresh operation. Therefore, the self-refresh operation for each cell may be incorrectly performed, resulting in the occurrence of data loss. 
         [0056]    An embodiment of the present invention controls the bulk voltage VBULK to not change when the bank is activated during the self-refresh operation. That is, an embodiment of the present invention controls a signal indicating a termination of the self-refresh active operation to stabilize the self-refresh operation. 
         [0057]    Upon receiving the self-refresh command, the self-refresh signal SREF may be activated. If the self-refresh operation begins by activation of the self-refresh signal SREF, the delay signal PWDD may transition to a high level after a lapse of delay time of the delay unit  110 . In order to prevent power consumption caused by frequent execution of the self-refresh operation, the self-refresh signal SREF activated by the self-refresh entry may be delayed for a predetermined time, resulting in formation of the delay signal PWDD. 
         [0058]    Provided that the delay signal PWDD and the idle signal RASIDLE are at a high level, the control signal A may be maintained at a low level without change. If the control signal A is at a low level, the PMOS transistor P 2  is turned on and the PMOS transistor P 1  is turned off in  FIG. 4 . 
         [0059]    Accordingly, the bulk voltage VBULK is output at a peri-voltage VPERI level, where the peri-voltage VPERI is applied to bulk terminals of the PMOS transistors P 3 -PN. Therefore, the same voltage may be applied to a source terminal and a bulk terminal of each of the PMOS transistors P 3 -PN. 
         [0060]    The delay signal PWDD may be at a high level during a rising time of the bulk voltage VBULK. If the idle signal RASIDLE indicating an active operation state of the bank transitions to a high level on the condition that the delay signal PWDD is at a high level, the bulk voltage VBULK may not increase and remain unchanged, as shown in  FIG. 6 . 
         [0061]    Thereafter, the control signal generator  10  may allow the idle signal RASIDLE to be transitioned to a low level when all bank addresses 
         [0062]    BA&lt; 0 &gt;-BA&lt; 7 &gt; are at a low level due to termination of the active operation. If the idle signal RASIDLE transitions to a low level on the condition that the delay signal PWDD is at a high level, this may indicate that the active operation of all banks is terminated. Therefore, when the idle signal RASIDLE transitions to a low level, the control signal A may transition to a high level and the control signal AB may transition to a low level. 
         [0063]    Thus, the PMOS transistor P 2  may be turned off and the PMOS transistor P 1  may be turned on. Therefore, the bulk voltage 
         [0064]    VBULK may be output as a power-supply voltage level VDD 1 , such that a power-supply voltage VDD 1  is applied to bulk terminals of the PMOS transistors P 3 -PN. 
         [0065]    A source voltage of each of the PMOS transistors P 3 -PN is a peri-voltage VPERI. Therefore, the power-supply voltage VDD 1  higher than that of a source terminal may be applied to the bulk terminal of each of the PMOS transistors P 3 -PN, such that an off leakage current flowing from a source terminal to a drain terminal of each of the PMOS transistors P 3 -PN can be greatly reduced. 
         [0066]    Assuming that the control signal AB is at a low level, the bulk voltage VBULK can maintain its value even when the idle signal RASIDLE transitions to a high level in a subsequent process. In other words, assuming that the bulk voltage VBULK increases and the subsequent idle signal RASIDLE transitions to a high level, the active operation may be carried out. 
         [0067]    The active operation state in which the bulk voltage VBULK increases may indicate that the bulk voltage VBULK has already been stabilized to the power-supply voltage level VDD 1 . Therefore, assuming that the control signal AB is at a low level and the subsequent idle signal RASIDLE transitions to a high level, the bulk voltage level VBULK may remain unchanged unless changed by the self-refresh signal SREF. 
         [0068]    As is apparent from the above description, the various embodiments of the present invention can remove unstable elements of the self-refresh active region, and can stably perform the self-refresh operation. 
         [0069]    Those skilled in the art will appreciate that the present invention may be carried out in other specific ways than those set forth herein without departing from the spirit and essential characteristics of the present invention. The above various embodiments are therefore to be construed in all aspects as illustrative and not restrictive. The scope of the invention should be determined by the appended claims and their legal equivalents, not by the above description, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein. Also, it is obvious to those skilled in the art that claims that are not explicitly cited in each other in the appended claims may be presented in combination as an embodiment of the present invention or included as a new claim by a subsequent amendment after the application is filed. 
         [0070]    Although a number of illustrative embodiments consistent with the invention have been described, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. Particularly, numerous variations and modifications are possible in the component parts and/or arrangements which are within the scope of the disclosure, the drawings, and the accompanying claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.