Abstract:
The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to semiconductor wafer processing and, more particularly, to a method for dicing a semiconductor wafer using laser technology. 
     2. Description of the Related Art 
     In a typical semiconductor manufacturing process, a large number of semiconductor devices are formed on a silicon wafer. The semiconductor devices are made by forming thin layers of semiconductor, insulator, and metal materials patterned to form electronic components and integrated circuits. After the semiconductor devices are formed on the wafer, each of the devices (die) must be separated. The process of separating the individual die is referred to as “dicing” the wafer. 
     Traditionally, dicing saws have been used for dicing a semiconductor wafer. However, where the thickness of the semiconductor wafer is very thin, the dicing process performed by the cutting blade can result in the collapse of the semiconductor wafer. In addition, the traditional cutting blade is no longer suitable for very narrow cutting lines. Although laser-based techniques have been used to overcome some of the problems with sawing, yield rates are low when singulating wafers having uneven surfaces using conventional laser cutting technology. 
     SUMMARY OF THE INVENTION 
     One aspect of the disclosure relates to a semiconductor device. In one embodiment, the semiconductor device includes a die; at least one conductive via formed in the die; a passivation layer disposed on a portion of a back surface of the die, wherein the conductive via protrudes from the passivation layer; and a protection cap disposed on the protruded end of the conductive via; wherein the passivation layer has a lateral surface inclined at an angle greater than 90 degrees with respect to a portion of the back surface of the die not covered by the passivation layer. The portion of the back surface of the die not covered by the passivation layer is situated along a periphery of the back surface of the die and has a first roughness. An upper surface of the passivation layer has a second roughness, the first roughness substantially less than the second roughness. The first roughness is caused by a laser sintering process. Additionally, a lateral surface of the die has a first portion having a third roughness, a second portion having a fourth roughness, and a third portion having a fifth roughness; wherein the third roughness, the fourth roughness, and the fifth roughness are substantially different. The fourth roughness is caused by laser stealth dicing. In an embodiment, the fourth roughness is at least 50 times greater than the first roughness. Additionally, the third roughness and the fifth roughness is each greater than the first roughness. 
     Another aspect of the disclosure relates to a semiconductor package. In one embodiment, the semiconductor package includes a first substrate; a semiconductor device disposed on the first substrate, comprising: a die; at least one conductive via formed in the die; a passivation layer disposed on a portion of a back surface of the die, wherein the conductive via protrudes from the passivation layer; and a protection cap disposed on the protruded conductive via; wherein the passivation layer has a lateral surface inclined at an obtuse angle with respect to a portion of the back surface of the die not covered by the passivation layer; a second semiconductor device disposed on the semiconductor device and electrically connected to the conductive via; and a molding compound encapsulating the first substrate, the semiconductor device and the second semiconductor device. The passivation layer has a lacuna portion along a periphery of the passivation layer, and a lateral side of the passivation layer assumes an inclination angle of 90 degrees to 115 degrees with respect to the back surface of the die. In an embodiment, the protection cap comprises a seed layer, a Cu layer on the seed layer, a Ni layer on the Cu layer, a Pd layer on the Ni layer and an Au layer on the Pd layer. In another embodiment, the protection cap comprises a seed layer, a Cu layer on the seed layer, a Ni layer on the Cu layer, and a Sn/Ag alloy or Au layer on the Ni layer. The portion of the back surface of the die not covered by the passivation layer is situated along a periphery of the back surface of the die and has a first roughness. An upper surface of the passivation layer has a second roughness, the first roughness substantially less than the second roughness. The first roughness is caused by a laser sintering process. Additionally, a lateral surface of the die has a first portion having a third roughness, a second portion having a fourth roughness, and a third portion having a fifth roughness; wherein the third roughness, the fourth roughness, and the fifth roughness are substantially different. The fourth roughness is caused by laser stealth dicing. Additionally, the third roughness and the fifth roughness is each greater than the first roughness. 
     Another aspect of the disclosure relates to a method of dicing a semiconductor wafer. In one embodiment, the method includes providing a semiconductor wafer having a first surface, a second surface and a passivation layer, wherein the passivation layer is disposed on the second surface; applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; applying a second laser, wherein the second laser passes through the second surface of the semiconductor wafer and focuses at an interior portion of the semiconductor wafer; and applying a lateral force to the semiconductor wafer. The method can further include forming a protection cap on each of the tips. The step of providing the semiconductor wafer comprises: providing the semiconductor wafer having the first surface, the second surface and the at least one conductive via, wherein the conductive via is disposed in the semiconductor wafer; attaching a first carrier to the first surface of the semiconductor wafer; exposing a tip of the at least one conductive via by removing a portion of the semiconductor wafer from the second surface; covering the exposed tips with the passivation layer; and thinning the passivation layer so that the tips protrude from the passivation layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present invention; 
         FIG. 2  illustrates a partially enlarged view of  FIG. 1 ; 
         FIGS. 3 to 21  illustrate a semiconductor process for making a semiconductor device according to an embodiment of the present invention; 
         FIG. 22  illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention; 
         FIGS. 23 to 26  illustrate a semiconductor process for making a semiconductor package according to another embodiment of the present invention; 
         FIGS. 27 to 31  illustrate a semiconductor process for making a semiconductor device according to another embodiment of the present invention; and 
         FIGS. 32 to 37  illustrate a semiconductor process for making a semiconductor package according to another embodiment of the present invention. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 1 , a cross-sectional view of a semiconductor device  1 , according to an embodiment of the present invention, is illustrated. The semiconductor device  1  comprises a substrate  10 , an active surface  18  disposed on a first (lower) surface  101  of the substrate  10 , an integrated circuit (not shown) formed on the active surface  18 , a passivation layer  12  disposed on a second (upper) surface  102  of the substrate  10 , the substrate further having third (side) surfaces  103 , at least one conductive via  14  formed in the substrate  10 , wherein a protection cap  16  is formed over a protruding end of the conductive via  14 , at least one die bond pad  20  disposed on the active surface  18  and a connection element  22  disposed on each of the bond pads  20 , respectively. The connection element  22  may be a copper pillar, solder or a solder bump, a stud bump or a combination of any of the above. 
     The substrate  10  can be made from silicon, germanium, gallium arsenide, or other semiconductor material. The integrated circuit is formed by wafer fabrication technology known to those of ordinary skill. The active surface  18  has bond pads  20  which are electrically connect to the integrated circuit. However, it is to be understood that the substrate  10  may be an interposer having no integrated circuit. 
     The passivation layer  12  is disposed on the second surface  102  of the substrate  10 . The passivation layer  12  may be a non-conductive polymer such as polyimide (PI), epoxy, polybenzoxazole (PBO) or benzocyclobutene (BCB); alternatively, an inorganic passivation layer, such as silicon dioxide (SiO 2 ) may be used. In the present embodiment, the passivation layer  12  is a photo sensitive polymer, such as benzocyclobutene (BCB). 
     The conductive via  14  is disposed in the substrate  10  and surrounded by a non-conductive liner  24 . The conductive via  14  is made of a suitable conductive material such as copper, and the material of the liner  24  is an insulation material such as a non-conductive polymer, including polyimide (PI), epoxy, polybenzoxazole (PBO) or benzocyclobutene (BCB), or an inorganic material, such as silicon dioxide (SiO 2 ). The conductive via  14  penetrates the substrate  10  and the passivation layer  12 , and an end of the conductive via  14  and the liner  24  protrude from the passivation layer  12 . In the present embodiment, the top surface of the protruding end of the conductive via  14  is substantially coplanar with the top surface of the liner  24 . 
     The protection cap  16  is disposed on the protruding ends of the conductive via  14  and the liner  24 . In this embodiment, the protection cap  16  covers the top surface of the conductive via  14  and the protruding portion of the liner  24 . 
     Referring to  FIG. 2 , a partially enlarged view of  FIG. 1  is illustrated. The protection cap  16  has a seed layer  26 , a first conductive layer  281 , a second conductive layer  282 , a third conductive layer  283 , and a fourth conductive layer  284 , as shown. At a periphery of the semiconductor device  1 , a lateral surface of the passivation layer  12  has a tapered shape having an angle θ which is a result of a two-stage laser dicing process described in detail below. 
     The passivation layer  12  has a top surface  120 , a side surface  121  and a lacuna portion  122 . The lacuna portion  122  surrounds the passivation layer  12 , so that a part of the second surface  102  of the substrate  10  is exposed. There is a step between the top surface  120  and the second surface  102  of the substrate  10 ; that is, the side surface  121  of the passivation layer  12  is not coplanar with the side surface  103  of the substrate  10 , and the inclination angle θ is formed between the side surface  121  of the passivation layer  12  and the second surface  102  of the substrate  10 . 
     The second surface  102  of the substrate  10  has a first roughness R 1  and the top surface  120  of the passivation layer  12  has a second roughness R 2 . As will be described in greater detail, the roughness R 1  is caused by a first stage laser process. The roughness R 2  is larger than the first roughness R 1 . 
     The side surface  103  of the substrate  10  includes a first portion  103   a  having a third roughness R 3 , a second portion  103   b  having a fourth roughness R 4 , and a third portion  103   c  having a fifth roughness R 5 . As will be seen, the fourth roughness R 4  is caused by a second stage laser process. The third roughness R 3  and the fifth roughness R 5  are caused by a lateral tensile force. The third roughness R 3 , the fourth roughness R 4 , and the fifth roughness R 5  are different. Additionally, the first roughness R 1  is different from the third roughness R 3 , the forth roughness R 4 and the fifth roughness R 5 . 
     According to experimental data, the fourth roughness R 4  caused by the second laser process is larger than the first roughness R 1  caused by the first laser process. More specifically, the fourth roughness R 4  is at least 80 times larger than the first roughness R 1 . The third roughness R 3  and the fifth roughness R 5  caused by the lateral tensile force are larger than the first roughness R 1 . More specifically, the third roughness R 3 and the fifth roughness R 5  is at least 50 times larger than the first roughness R 1 . 
     Table 1 summarizes experimental data of the surface roughness, as discussed above. This experimental data were obtained using a white light interferometer, which is a non-contact way to measure the surface roughness (“roughness”) known in the art. As shown, three (3) samples were taken for each roughness R 1  to R 5  , and the mean values were then calculated. For instance, the mean roughness found for R 1  (resulting from the first laser process) was a vertical deviation of 0.0026 μm which is relatively “smooth” compared to the 0.290 μm mean roughness for R 4 (resulting from the second laser process) which is more than 100 times greater. 
     
       
         
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Surface Roughness 
                 R1(μm) 
                 R2(μm) 
                 R3(μm) 
                 R4(μm) 
                 R5(μm) 
               
               
                   
               
             
             
               
                 Sample #1 
                 0.0014 
                 0.0171 
                 0.209 
                 0.367 
                 0.460 
               
               
                 Sample #2 
                 0.0027 
                 0.0182 
                 0.399 
                 0.245 
                 0.972 
               
               
                 Sample #3 
                 0.0037 
                 0.0154 
                 0.312 
                 0.259 
                 0.410 
               
               
                 Mean of Samples 
                 0.0026 
                 0.0169 
                 0.307 
                 0.290 
                 0.614 
               
               
                 #1, #2 and #3 
               
               
                   
               
             
          
         
       
     
     Referring to  FIGS. 3 to 21 , a semiconductor process for making the semiconductor device  1 , according to an embodiment of the present invention, is illustrated. Referring to  FIG. 3 , a semiconductor wafer  11  is provided. The semiconductor wafer  11  has the first surface  101 , the second surface  102 , the at least one conductive via  14  and a plurality of cutting lines (not shown) which would indicate where the semiconductor wafer  11  is to be singulated into individual die. A first adhesive  30  is applied to the first surface  101  of the semiconductor wafer  11 . In this embodiment, the first adhesive  30  is a solvent-dissolving adhesive, such as one of the X5000 and X5300 adhesive products manufactured by Sumitomo Chemical. 
     Additionally, a first carrier  31  is provided, which can be metal, a semiconductor material or an insulating material such as glass. The first carrier  31  has a first isolation coating  32  disposed on a surface  311  thereof. In this embodiment, the first isolation coating  32  is a hydrophobic coating. 
     Referring to  FIG. 4 , the first carrier  31  is attached to the first surface  101  of the semiconductor wafer  11  by the adhesive  30 . In this embodiment, the connection elements  22  are embedded in the first adhesive  30 , and the thickness of the first adhesive  30  is larger than the height of the connection elements  22 . 
     The first isolation coating  32  has a characteristic that the adhesion force between the first isolation coating  32  and the first adhesive  30  is relatively weak in comparison with the adhesion force between the first adhesive  30  and the semiconductor wafer  11 . Furthermore, the area of the first isolation coating  32  is slightly smaller than that of the first adhesive  30  to ensure the semiconductor wafer  11  can be adhered to the first carrier  31  by the first adhesive  30   
     When the first carrier  31  and the first adhesive layer  30  are immersed in a solvent (not shown), part of the first adhesive layer  30  is dissolved and the first isolation coating  32  is exposed. After that, the first carrier  31  and the isolation coating  32  can be easily detached due to the weak adhesion force between the first adhesive layer  30  and the isolation coating  32 . 
     Referring to  FIG. 5 , a surface treatment is conducted on the second surface  102  of the semiconductor wafer  11 . The second surface  102  of the semiconductor wafer  11  is thinned by grinding and/or etching, so that a portion of the semiconductor wafer  11  is removed from the second surface  102 , and the conductive via  14  protrudes from the second surface  102  of the semiconductor wafer  11 . Thus, the end or tip of the conductive via  14 , which may include the liner  24 , is exposed. 
     Referring to  FIG. 6 , a passivation layer  12  is formed on the second surface  102  by a laminating process or a spin coating process, for example, so as to cover the tips of the conductive vias  14 . The passivation layer  12  may be a non-conductive polymer such as polyimide (PI), epoxy, polybenzoxazole (PBO) or benzocyclobutene (BCB); alternatively, an inorganic passivation layer, such as, silicon dioxide (SiO 2 ), may be used. In this embodiment, the passivation layer  12  can be a photo sensitive polymer such as benzocyclobutene (BCB), and can be formed by spin coating or spray coating. 
     Referring to  FIG. 7 , the passivation layer  12  is thinned by grinding and/or etching, so that the tips of the conductive vias  14  protrude from the passivation layer  12 . That is, portions of the passivation layer  12  remain on the second surface  102  of the semiconductor wafer  11  and fill or interlace the areas between the tips of the conductive vias  14 . 
     Referring to  FIG. 8 , the protection cap  16  is formed on the tip of the conductive via  14  and protruding portion of the liner  24 . 
     Referring to  FIG. 9 , a partially enlarged view of  FIG. 7 , illustrates the protruding conductive via  14  with the liner  24  and the remaining portions of the passivation layer  12  disposed in between the tips of the conductive vias  14  and recessed below a distal end of the vias  14 . 
     Referring to  FIG. 10 , a seed layer  26 , such as a Ti/Cu layer or a Ti/W layer is disposed on the passivation layer  12 , the conductive vias  14  and the liners  24  by sputtering or other methods known to those of ordinary skill. The seed layer  26  conforms to the topography of the upper surfaces of the various elements including the conductive vias  14  and the passivation layer  12 . 
     Referring to  FIG. 11 , a photo-resist layer  34  is formed on the seed layer  26 , and a plurality of openings  341  are patterned in the photo-resist layer  34 . The positions of the openings  341  correspond to the conductive vias  14 , and have a tapered shape such that the top portion of each of the openings  341  is wider than the bottom portion of each of the openings  341 . 
     Referring to  FIG. 12 , a first conductive layer  281 , a second conductive layer  282 , a third conductive layer  283  and a fourth conductive layer  284  are formed in the openings  341 , over the tips of the vias  14 . In this embodiment, the first conductive layer  281  is Cu, the second conductive layer  282  is Ni, the third conductive layer  283  is Pd, and the fourth conductive layer  284  is Au. However, in other embodiments, the multi-layered structure disposed on the seed layer  26  may comprise a first conductive layer (Cu), a second conductive layer (Ni) and a third conductive layer (Sn/Ag or Au). Then, the photo-resist layer  34  is removed by photo-resist stripper, and part of the seed layer  26  that is disposed outside the first layer  281  is removed by etching process, so as to form the protection caps  16 . 
     Referring to  FIG. 13 , a second carrier  36  is provided. In this embodiment, the second carrier  36  is a handling tape  36  which has a first surface  361 , a second surface  362  and an adhesive layer (not shown) disposed on the second surface  362 . The second surface  362  of the handling tape  36  is attached to the second surface  102  of the semiconductor wafer  11  through the adhesive layer (not shown) and the protection caps  16  are embedded into the adhesive (not shown). 
     Referring to  FIG. 14 , the first carrier  31  and the first adhesive layer  30  are further immersed in a solvent (not shown), for example, gamma-Butyrolactone (GBL) or Propylene Glycol Monomethyl Ether Acetate (PGMEA), part of the first adhesive layer  30  is dissolved and the first isolation coating  32  is exposed. After that, the first carrier  31  and the isolation coating  32  is easily detached due to the weak adhesion force between the first adhesive layer  30  and the isolation coating  32 . Thus, the first carrier  31  is detached from the semiconductor wafer  11 . However, in other embodiments, a cutting process of the semiconductor wafer  11  may be conducted to detach the first carrier  31 . 
     Referring to  FIG. 15 , an ultraviolet (UV) light (shown by arrows  38 ) is applied on the first surface  361  of the handling tape  36  so as to reduce the adhesion of the first dicing tape  36 . Then, a dicing tape  40 , such as a UV tape, is attached to the first or lower surface  101  of the semiconductor wafer  11 . 
     Referring to  FIG. 16 , the handling tape  36  is detached from the semiconductor wafer  11  and the upper surface of the wafer  11 , including the protection caps  16 , are exposed. 
     Referring to  FIG. 17 , a first laser  42 , for example a laser sintering machine, such as model DFL7160 by DISCO Corporation, is applied and focuses on the passivation layer  12  to remove a part of the passivation layer  12  and form a plurality of trenches  123  in the vicinity of the wafer cut lines. Such process is a laser sintering process or a laser grooving process, and is further described as follows. The energy from the first laser  42  melts and then evaporates portions of the passivation layer  12  so as to form a plasma on the top surface thereof. As the plasma extends into the passivation layer  12 , more and more materials are removed, and the trench  123  is formed. In this embodiment, the trenches  123  correspond to the cutting lines (not shown), and a width of each of the trenches  123  is less than a width of each of the cutting lines. 
     Referring to  FIG. 18 , a partially enlarged view of  FIG. 17  is illustrated. As show, the trench  123  exposes a part of the second surface  102  of the semiconductor wafer  11 . An inclination angle θ is formed between the side surface  121  of the passivation layer  12  and the second surface  102  of the semiconductor wafer  11 . The first laser  42  is used to remove a part of the passivation layer  12  to ensure the flatness of the second surface  102  of the semiconductor wafer  11 . In this embodiment, the first laser  42  is fixed in a specific wavelength, and no matter a shorter or longer pulse width, the trench  123  will show an inclination angle θ which is greater than 90 degrees and smaller than about 115 degrees. Referring to  FIG. 19 , another example of the trench  123  of the passivation layer  12  is illustrated. As shown in the figure, the semiconductor wafer  11  is further removed by the first laser  42  so as to form a notch  111  to ensure the passivation layer  12  on the surface of the cutting line is substantially entirely removed. 
     Referring to  FIG. 20 , a second laser  44 , for example, a laser stealth dicing machine such as model DFL7360 by DISCO Corporation is applied along the trench  123 . The second laser  44  is different from the first laser  42 , and passes through the exposed second surface  102  of the semiconductor wafer  11 . The second laser  44  focuses at an interior portion of the semiconductor wafer  11  so as to break the crystal structure of the material of the semiconductor wafer  11 . 
     The second laser  44  at a wavelength capable of transmitting through the semiconductor wafer  11  is condensed by an objective lens and focused onto a point inside the semiconductor wafer  11 . The second laser  44  uses short pulses oscillating at a high repetition rate and can be highly condensed to a diffraction threshold level. The second laser  44  is formed at an extremely high peak power density both time and spatially compressed in the vicinity of the light focus point. When the second laser  44  transmitting through the semiconductor wafer  11  exceeds a peak power density during the condensing process, a nonlinear absorption effect causes a phenomenon in which extremely high absorption occurs at localized points. By optimizing the second laser  44  and optical system characteristics to cause the nonlinear absorption effect just in the vicinity of the focal point inside the semiconductor wafer  11 , only localized points in the semiconductor wafer  11  can be selectively laser-machined without damaging the front and back surface inside the semiconductor wafer  11 . That is, the laser stealth dicing described herein makes use of wavelengths that transmit through the monocrystalline silicon semiconductor wafer to be diced, so that the laser beam can be guided to the vicinity of the focal laser machining within the semiconductor wafer  11 . Therefore, a compressive stress is generated in a degeneration layer having a polycrystalline silicon state with high density dislocation in the cutting line. 
     Referring to  FIG. 21 , a lateral tensile force (shown as arrow  46 ) is applied to the semiconductor wafer  11  for example by means of the dicing tape  40 , so as to separate the wafer  11  into a plurality of semiconductor devices  1  as shown in  FIG. 1 . The semiconductor wafer  11  will be put on an enlarging apparatus (not shown). A lateral tensile force acts on the semiconductor wafer  11  attached to the enlarging apparatus. The semiconductor wafer  11  is singulated along the cutting lines, and is thus divided into the individual semiconductor devices  1 . 
     To optimize the yield of the individual devices  1 , the laser stealth dicing should be focused at the midpoint of the crystalline structure of the semiconductor wafer  11 . Therefore, the planarity of the exposed second surface  102  of the semiconductor wafer  11  is significant. However, in this embodiment, the passivation layer  12  was disposed on the second surface  102  of the semiconductor wafer  11  with the at least one conductive via  14 . The first laser  42  was used to remove a part of the passivation layer  12  to increase the planarity of the second surface  102  exposed from the semiconductor wafer  11 . Further, the dicing process of this embodiment uses a laser rather than a cutting blade, so that it will not result in the collapse of the semiconductor wafer  11  and is suitable for narrow cutting lines. 
     Referring to  FIG. 22 , a cross-sectional view of a semiconductor package  2 , according to another embodiment of the present invention, is illustrated. The semiconductor package  2  comprises a bottom substrate  46 , the semiconductor device  1 , a top semiconductor device  48  and a molding compound  50 . The bottom substrate  46  is, for example, an organic substrate. The semiconductor device  1  is the same as the semiconductor device  1  as shown in  FIG. 1 , and is disposed on the bottom substrate  46 . 
     The top semiconductor device  48  is disposed on the semiconductor device  1  and has at least one top external connection element  481  on a surface thereof. The protection cap  16  contacts the top external connection element  481 . 
     The molding compound  50  encapsulates the bottom substrate  46 , the semiconductor device  1  and the top semiconductor device  48 . In this embodiment, the semiconductor package  2  further comprises an underfill  52 , a non-conductive paste  54  and a plurality of solder balls  56 . The underfill  52  is disposed between the semiconductor device  1  and the bottom substrate  46  so as to protect the external connection elements  22 . The non-conductive paste  54  is disposed between the top semiconductor device  48  and the semiconductor device  1 . The solder balls  56  are disposed on the bottom surface of the bottom substrate  46 . 
     Referring to  FIGS. 23 to 26 , a semiconductor process for making a semiconductor package according to another embodiment of the present invention is illustrated. Referring to  FIG. 23 , a third carrier  58  and a bottom substrate  46  are provided. The bottom substrate  46  is attached to the third carrier  58  by an adhesive layer  60 . 
     Referring to  FIG. 24 , the semiconductor device  1  is picked up and bonded to the bottom substrate  46  by a bonding head (not shown). An underfill  52  is formed between the semiconductor device  1  and the bottom substrate  46  so as to protect the external connection elements  22 . 
     Referring to  FIG. 25 , a non-conductive paste  54  is formed over the passivation layer  12 , and the top semiconductor device  48  is stacked on the semiconductor device  1 . Meanwhile, the protection cap  16  contacts a top external connection element  481  (for example, solder ball) of the top semiconductor device  48 . 
     Referring to  FIG. 26 , a molding compound  50  is formed to encapsulate the bottom substrate  46 , the semiconductor device  1  and the top semiconductor device  48 . Then, the third carrier  58  and the adhesive layer  60  are removed, and a plurality of solder balls  56  are formed on the bottom surface of the bottom substrate  46 . Thus, the semiconductor package  2  of  FIG. 22  is obtained. 
     Referring to  FIGS. 27 to 31 , a semiconductor process for making the semiconductor device  1 , according to another embodiment of the present invention, is illustrated. The UPH (unit per hour) of the simplified process described below could be higher than the previous process described above, and the yield could be enhanced by omitting a re-mount step to the dicing tape  40 . This embodiment is subsequent to the step of  FIG. 8 . 
     Referring to  FIG. 27 , a first laser  42  is applied and focuses on the passivation layer  12  to remove a part of the passivation layer  12  and form a plurality of trenches  123 . In this embodiment, the trenches  123  correspond to the cutting lines (not shown), and a width of each of the trenches  123  is less than a width of each of the cutting lines. 
     Referring to  FIG. 28 , a second carrier is provided. In this embodiment, the second carrier is a handling tape  36  which has a first surface  361 , a second surface  362  and an adhesive layer (not shown) disposed on the second surface  362 . The second surface  362  of the handling tape  36  is attached to the second surface  102  of the semiconductor wafer  11  through the adhesive layer (not shown) and the protection caps  16  are embedded into the adhesive (not shown). 
     Referring to  FIG. 29 , the first carrier  31  and the first adhesive layer  30  are further immersed in a solvent (not shown), for example, gamma-Butyrolactone (GBL) or Propylene Glycol Monomethyl Ether Acetate (PGMEA), part of the first adhesive layer  30  is dissolved and the first isolation coating  32  is exposed. After that, the first carrier  31  and the isolation coating  32  is detached due to the weak adhesion force between the first adhesive layer  30  and the isolation coating  32 . Therefore, the first carrier  31  is detached from the semiconductor wafer  11 . However, in other embodiment, a cutting process of the semiconductor wafer  11  may be conducted to detach the first carrier  31 . 
     Referring to  FIG. 30 , a second laser  44  is applied along the trench  123 . The second laser  44  is different from the first laser  42 , and passes through the handling tape  36  and the exposed second surface  102  of the semiconductor wafer  11 . The second laser  44  focuses at an interior of the semiconductor wafer  11  so as to break the crystal structure of the material of the semiconductor wafer  11 . In this embodiment, the second surface  102  of the semiconductor wafer  11  in the trenches  123  is smooth after being processed by the first laser  42 , thus, the cutting quality of the second laser  44  is ensured. 
     Referring to  FIG. 31 , a lateral force to  46  is applied to the semiconductor wafer  11  so as to form a plurality of semiconductor devices  1  as shown in  FIG. 1 . 
     Referring to  FIGS. 32 to 37 , a semiconductor process for making the semiconductor package  2 , according to another embodiment of the present invention, is illustrated. This embodiment is subsequent to the step of  FIG. 27 . Referring to  FIG. 32 , a non-conductive paste  54  is formed over the passivation layer  12 , and a plurality of top semiconductor devices  48  are stacked on the semiconductor wafer  11 . Meanwhile, the protection cap  16  contacts a top external connection element  481  (for example, solder ball) of the top semiconductor device  48 . 
     Referring to  FIG. 33 , a second carrier is provided. In this embodiment, the second carrier is a handling tape  36  which has a first surface  361 , a second surface  362  and an adhesive layer (not shown) disposed on the second surface  362 . The second surface  362  of the handling tape  36  is attached to the second surface  102  of the semiconductor wafer  11  through the adhesive layer (not shown) and the part of the top semiconductor devices  48  are embedded into the adhesive (not shown). 
     Referring to  FIG. 34 , the first carrier  31  and the first adhesive layer  30  are further immersed in a solvent (not shown), for example, gamma-Butyrolactone (GBL) or Propylene Glycol Monomethyl Ether Acetate (PGMEA), part of the first adhesive layer  30  is dissolved and the first isolation coating  32  is exposed. After that, the first carrier  31  and the isolation coating  32  is detached due to the weak adhesion force between the first adhesive layer  30  and the isolation coating  32 . Therefore, the first carrier  31  is detached from the semiconductor wafer  11 . However, in another embodiment, a cutting process of the semiconductor wafer  11  may be conducted to detach the first carrier  31 . 
     Referring to  FIG. 35 , a second laser  44  is applied along the trench  123 . The second laser  44  is different from the first laser  42 , and passes through the handling tape  36  and the exposed second surface  102  of the semiconductor wafer  11 . The second laser  44  focuses at an interior of the semiconductor wafer  11  so as to break the crystal structure of the material of the semiconductor wafer  11 . 
     However, in other embodiments, a dicing tape (not shown) may be attached to the first surface  101  of the semiconductor wafer  11 . Then, the handling tape  36  is detached from the semiconductor wafer  11 , so that the second laser  44  directly passes through the exposed second surface  102  of the semiconductor wafer  11  and focuses at an interior of the semiconductor wafer  11 . In this embodiment, the exposed second surface  102  of the semiconductor wafer  11  is smooth after being processed by the first laser  42 , ensuring good cutting quality with a high yield. 
     Referring to  FIG. 36 , a lateral force (shown as arrow  46 ) is applied to the semiconductor wafer  11  so as to form a plurality of combo devices  3  as shown in  FIG. 37 . Then, the combo device  3  is picked up and bonded to the bottom substrate  46  on the third carrier  58  by a bonding head (not shown). An underfill  52  is formed between the semiconductor device  1  and the bottom substrate  46  so as to protect the external connection elements  22 . Then, a molding compound  50  is formed to encapsulate the bottom substrate  46  and the combo device  3 . Then, the third carrier  58  is removed, and a plurality of solder balls  56  are formed on the bottom surface of the bottom substrate  46 . Thus, the semiconductor package  2  of  FIG. 22  is obtained. 
     While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present invention which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.