Abstract:
A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by: maintaining the in a stand-by mode when no memory read/write commands are to be executed, and if any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.

Description:
PRIORITY CLAIM  
       [0001]     This application claims priority from European patent application No. 05014614.1, filed Jul. 6, 2005, which is incorporated herein by reference.  
       TECHNICAL FIELD  
       [0002]     An embodiment of the present invention relates to power consumption management techniques. The embodiment was developed by paying specific attention to the possible application in the field of processing devices such as e.g. micro-controllers.  
       BACKGROUND  
       [0003]     Reducing the overall power consumption is a key factor in ensuring proper operation of a wide gamut of electronic components and devices.  
         [0004]     For instance, a micro-controller can save power while it is not operating, by staying in one of its low power modes (WAIT, HALT, ACTIVE HALT). In the low power modes, the micro-controller switches off the core, the embedded oscillators, the memories, the analog macro cells and/or the gating clock to the peripherals. When a routine is to be executed, the micro-controller can be “awoken” from an external/internal interrupt. After executing the routine, the micro-controller can return to one of its low power modes until a new request arrives.  
         [0005]     Typically, the higher is the power consumption reduction in the selected state, the longer is the time required to wake up the micro-controller from the low-power mode. To reduce the micro-controller power consumption, it is also useful to switch the internal clock controller to a low-power/low-frequency oscillator. When the micro-controller is fed with this low frequency oscillator source, the system is working in a SLOW mode. In this SLOW mode the micro-controller is still operating: the core and the other parts of the micro-controller are active but fed with a low-frequency clock thus reducing power consumption.  
         [0006]     While operating, a micro-controller is able to access the embedded non-volatile memory in order to fetch, decode, and execute the instructions of a program. When the micro-controller is fed with a low- power/low-frequency oscillator and is working in the SLOW mode, the memory is still consuming power because the memory is always ON. When the memory is accessed by the core, it consumes power for an entire clock cycle even it the time required to access the memory is lower.  
       SUMMARY  
       [0007]     From the foregoing description of the current situation, there exists the need to define solutions capable of managing power consumption in a more satisfactory way as compared to the solutions according to the known art.  
         [0008]     An embodiment of the invention thus provides a fully satisfactory response to those needs.  
         [0009]     An embodiment of the present invention is a method. An embodiment of the invention also relates to a corresponding system as well as to a related computer program product, loadable in the memory of at least one computer and including software code portions for performing the steps of the method of an embodiment of the invention when the product is run on a computer. As used herein, reference to such a computer program product is intended to be equivalent to reference to a computer-readable medium containing instructions for controlling a computer system to coordinate the performance of the method of an embodiment of the invention. Reference to “at least one computer” is intended to highlight the possibility for an embodiment of the present invention to be implemented in a distributed/ modular fashion.  
         [0010]     An embodiment described herein is based on the recognition of the fact that, if the micro-controller is working in the SLOW mode, the clock period is longer than the time required to execute a read memory command. In order to reduce the overall power consumption, the embodiment described herein provides a memory interface able to manage a STAND-BY low-power memory mode. When the micro-controller is working in the SLOW mode, a clock controller asserts a SLOW mode signal recognizing that the system clock period is greater than the standby memory recovery time plus the memory access time. The memory interface controls the memory status in order to maintain the memory in the STAND-BY mode when no memory read/write commands are required. The interface controls the memory entry/recover operations, using an asynchronous read access protocol. A dedicated analog circuit, able to provide a “Ready” signal, monitors the STAND-BY condition. The memory interface switches the memory ON only for the time requested to perform a memory read/write command. After the end of the memory read/write operation, the memory interface puts again the memory in the STAND-BY mode.  
         [0011]     In this way, when the micro-controller is working in the SLOW mode, there is a significant memory-power consumption reduction. As a result, the entire micro-controller power consumption is reduced: in fact, the power-consumption contribution of the memory is often huge if compared to the other components embedded in a micro-controller. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     One embodiment of the invention will now be described, by way of example only, with reference to the enclosed figures of drawing, wherein:  
         [0013]      FIG. 1  shows an exemplary architecture of a micro-controller according to an embodiment of the invention,  
         [0014]      FIG. 2  shows an exemplary circuit embodiment,  
         [0015]      FIG. 3  shows an exemplary time-diagram of a read-memory- access operation according to an embodiment of the invention, and  
         [0016]      FIG. 4  shows a portion of the memory block of  FIG. 1  according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0017]      FIG. 1  shows an example of micro-controller architecture including, according to an arrangement known per se, an address decoder  10 , a “core” block  20 , a clock controller  30 , and a memory interface block  40  according to an embodiment of the invention. The memory-inteface block  40  controls the memory access to a non-volatile memory block  70 . The memory block  70  comprises a STAND-BY monitor block  75  able to generate a Ready signal on a line  130 .  
         [0018]     When the core block  20  receives a memory access command (read/write) or the micro-controller is put in a low-power mode, the memory-interface block  40  implements a protocol in order to manage the read/write access to the non-volatile memory block  70 . The memory-interface block  40  also manages the entry/recover operation of the non-volatile memory block  70  in one of its low power modes (STAND-BY, POWER DOWN).  
         [0019]     A STAND-BY management block  50  included in the memory-interface block  40  manages the entry/recover operation of the non-volatile memory block  70  from its low-power STAND-BY mode. The STAND-BY management block  50  controls the non-volatile memory block  70  by means of a “standby” signal fed on a line  120 . This signal is an input for the STAND-BY monitor block  75 , shown in  FIG. 4 , and is used to generate the output signal of the memory block  70 .  
         [0020]     When the micro-controller is in the SLOW mode, i.e. a “slowmode” signal fed on a line  110  is high, the STAND-BY management block  50  puts the memory cells of the non-volatile memory block  70  in a STAND-BY mode. When the core block  20  requires a read/write memory access, i.e. a “nselmem” signal on a line  80  is set low and a “rw” signal on a line  90  is high, a “OKSelMem” signal on a line  170  is set low and fed to the STAND-BY management block  50  and to the non volatile memory block  70 . When the “OKSelMem” signal on the line  170  is low, the STAND-BY management block  50  automatically switches the memory  70  from the STAND-BY mode to an OPERATING mode.  
         [0021]     The STAND-BY management block  50  masks the memory clock, provided by the clock controller  30  on a line  100 , by means of a Ø1 line  150 , until the memory has completely recovered from the STAND-BY mode.  
         [0022]     When the memory block  70  is operative, a “ready” signal on a line  130  is fed to the STAND-BY management block  50 . The STAND-BY management block  50  performs the read/write access to the memory block  70  and then puts again the memory block  70  in the STAND-BY mode setting high the standby signal on the line  120 .  
         [0023]     During a reading operation, the memory block  70  sets high a readbusy signal on line  140 .  
         [0024]     A busy signal on line  160  is set high to indicate that the memory block  70  is executing a write memory operation.  
         [0025]     The microcontroller can be initialized by a reset signal on a line  180 .  
         [0026]      FIG. 3  shows a time-diagram of a read memory access operation, where the signals of  FIG. 1  are shown.  
         [0027]     The time period T_standby required for the memory to recover from the STAND-BY mode plus the access time T_acc spent to perform a read access is lower than the T_cych clock period in which the read access is executed.  
         [0028]     In this way, when the micro-controller is in the SLOW mode, the following advantages are achieved in terms of memory power consumption: 
        the memory is always in the STAND-BY mode until the core requires a memory access, and     the memory is accessed, for a read command, for a very short time (T_standby+T acc) if compared to clock period (T_cych), and then the memory is put again in the STAND-BY mode.        
 
         [0031]     In an embodiment, the micro-controller works in SLOW mode (and the “slowmode” signal  110  is high) with a clock source of 32 KHz (T_cych=31.25 μs), and a memory with a T_standby equal to 700 ns and a T_acc equal to 80 ns.  
         [0032]      FIG. 2  shows an exemplary arrangement of the STAND-BY management block  50 .  
         [0033]     The output signal of a NOR port  6  corresponds to the standby signal fed on line  120  of  FIG. 1 . This signal is normally high while the micro-controller is working in the SLOW mode (slowmode signal  110  high). When the core block  20  requires a memory read access in SLOW mode (slowmode signal  110  high) the CORE block  20  puts low the nselmem signal on line  80  and high the rw signal on line  90  for a clock cycle. As a consequence, the memory interface block  40  puts low the memory read enable OkSelMem signal on line  170  which is the input of an inverter port  13 . The output of the inverter  13  and the output of a delay cell  14  are fed to an AND port  3  which is the clock for a Flip-Flop block  4 .  
         [0034]     When there is a read access attempt by the core block  20 , the output of the Flip-Flop  4  is switched from logic value zero to logic value one, and as a consequence the output of an AND port  5  goes high.  
         [0035]     The consequence of a reading access is that the standby signal  120 , output of a NOR port  6 , goes low, indicating that memory is to be awakened from the STAND-BY mode to perform a read access command.  
         [0036]     After a T_stop period of  700  ns the memory is ready, so the ready signal on line  130  goes high. During the T stop period, when the ready signal on line  130  is low, the output of an INVERTER  9  is high, so a mask signal, output of a NAND port  7 , is low. A mask signal on line  190  (see  FIG. 2  and  FIG. 3 ) coming from NAND port  7  masks the memory Ø1 clock signal on line  150 , which is the output signal of an AND port  8 , in order to prevent the core block  20  from starting a read access while the memory block  70  is not ready. After the T_stop period, the ready signal on fine  130  is set high by the memory, indicating that the memory block  70  is ready to be accessed.  
         [0037]     At this moment, the Ø1 signal on line  150 , is unmasked and the readbusy signal on line  140  is set high for a T_acc period, when line  200 , that is the Ø1 signal shifted clock generated inside the memory, is high (see  FIG. 2 ), indicating that a reading operation is in course.  
         [0038]     After the T_acc period the read data is available, and the memory block  70  sets low the readbusy signal on line  140 . An impulse imp_rb is generated at the output of an OR port  1  (which has as inputs the readbusy signal and the output of the delay cell  11 ). In this way, after the conclusion of the read access, the output of the Flip-Flop  4  goes low and the standby signal on line  120  goes high again in order to specify that the memory is again in the STAND-BY mode.  
         [0039]     On the other hand, if the core block  20  requires a write access, the memory interface sets high the busy signal on line  160  for the memory-write access time so the output standby signal of the NOR port  6  goes low in order to allow the write operation in the memory block  70 .  
         [0040]      FIG. 4  shows an example of an embodiment of the STAND-BY monitor block  75 . This arrangement is used to generate the “Ready” signal on line  130  able to monitor the STAND-BY mode.  
         [0041]     In the reset state, i.e. when the signal on line  185  is low, a Flip-Flop block  490  is reset by the output of an OR port  480  driven by an INVERTER port  410  and an AND port  470 , the Ready signal on line  130  is high and the memory block  70  is not in STAND BY mode.  
         [0042]     In the OPERATING mode, the Standby signal on line  120  is low, the Reset signal on line  185  is high, and the Ready signal on line  130  is still high.  
         [0043]     When the Standby signal on line  120  goes high, the memory block  70  enters the STAND-BY mode, the Flip-Flop  490  switches and the Ready signal on line  130  goes to the low level without any delay. In this mode the memory block  70  is in a low-consumption state and cannot be accessed for a reading or erasing/writing operation.  
         [0044]     An out_reg_boost signal on line  125  is the output of a BOOST regulator and gives the information that the HV voltage (VBOOST), to perform the reading operation, has overcome a specific threshold. In the STAND BY mode the BOOST circuit is on, working with a specific regulation (STAND-BY regulation). This is a soft, less accurate regulation that ensures a voltage VBOOST quite stable around its final value.  
         [0045]     The out_reg_boost signal on line  125  is fed to an AND port  420  which receives as input the output signal from the Flip-Flop block  490 . The output signal of the AND port  420  is fed to the CLOCK input of a Flip-Flop block  460 .  
         [0046]     In order to recover the memory block  70  from the STAND-BY mode, the Standby signal on line  120  go low; in this way the reset of the Flip-Flop block  460  is released and on the first rising edge of the out_reg_boost signal on line  125  the output of the Flip-Flop block  460  goes high forcing to the logic value “one” the output of the Flip-Flop block  490 .  
         [0047]     An OR port  440  receives as input the Standby signal on line  120  and the output signal of the INVERTER port  410 .  
         [0048]     The output of the Flip-Flop block  490 , is fed to an INVERTER port  430 . The output signal of port  430  is fed to an OR port  450 , that receives also the output signal from the OR port  440 . The output signal of the OR port  450  is fed to the RESET input of the Flip-Flop block  460 .  
         [0049]     The output of the Flip-Flop block  460  is fed to the AND port  470  that receives also as input the inverted Standby signal.  
         [0050]     The output of the Flip-Flop block  490 , after a delay introduced by an analog delay block  500 , is transferred on the Ready signal on line  130 .  
         [0051]     The analog delay  500  used in this embodiment is able to delay a signal only when there is a transition from the low level to the high level.  
         [0052]     In conclusion, the Ready signal on line  130  is low when the Standby signal on line  120  is high (memory in STAND-BY mode) and also when the Standby goes low and the memory has not yet completed the recovery from the STAND-BY mode.  
         [0053]     The circuitry described above may be disposed in an Integrated Circuit (IC), such as a system on a chip, and this IC may be incorporated into a system.  
         [0054]     Without prejudice to the underlying principles of the invention, the details and the embodiments may vary, also appreciably, with reference to what has been described by way of example only, without departing from the spirit and scope of the invention.