Abstract:
A parabola generator for providing dynamic correction includes a capacitor source of a parabolic input signal at a frequency related to a horizontal deflection frequency coupled to a first terminal of the capacitor. A diode switch is coupled to a voltage at a reference level and to a second terminal of the capacitor for periodically clamping a peak level of a signal developed at the second terminal. A transistor switch is responsive to a periodic switch control signal and coupled to the second terminal of the capacitor for periodically clamping a signal applied from the second terminal, during retrace, for removing a parasitic parabolic voltage portion to generate a dynamic correction signal. The dynamic correction signal is coupled to the cathode ray tube to vary a field in a beam path of an electron beam of the cathode ray tube for providing dynamic correction.

Description:
[0001]     This application claims the benefit of the priority date of U.S. Provisional patent application Ser. No. 60/374,280, filed Apr. 19, 2002. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates to a waveform generator for controlling an electron beam in a cathode ray tube (CRT), and more particularly to a parabola generator for dynamic focus voltage.  
       BACKGROUND OF THE INVENTION  
       [0003]     It is known to generate a dynamic focus voltage that is applied to a focus electrode of a cathode-ray tube (CRT) for changing the focus of the CRT as the length of the beam path changes during horizontal and vertical scanning. For example, U.S. Pat. No. 6,300,731, entitled DYNAMIC FOCUS VOLTAGE AMPLITUDE CONTROLLER, in the name of John Barrett George, describes such an arrangement. There, a parabolic horizontal rate voltage is applied to a focus voltage amplifier.  
         [0004]     A data sheet of a deflection processor integrated circuit (IC) TA1317AN published by Toshiba Corporation describes generation of a parabola waveform for horizontal dynamic focus. The peak-to-peak amplitude of the parabola waveform is selectable such that the level of the parabola at the center of horizontal trace remains the same at the different selections of the peak-to-peak amplitude. Whereas, at the end of trace, the peak level of the parabola is different at the different selections of the peak-to-peak amplitude.  
         [0005]     Also, between the end of one trace and the beginning of the next trace, a parasitic or undesirable waveform portion is generated in IC TA1317AN. When applied to the focus voltage amplifier, this parasitic waveform portion, that occurs, during retrace, may produce an undesirable distortion in a portion of the dynamic focus voltage that occurs outside retrace, in a visible portion of the horizontal scan line, near the end of trace. It may be desirable to eliminate the parasitic waveform portion without disturbing the portion of the dynamic focus voltage that occurs in the vicinity of the end of trace. It may also be desirable to do so in a manner that preserves the ability to adjust the peak-to-peak amplitude of the parabola waveform.  
         [0006]     In carrying out an aspect of the invention, a first parabola waveform is capacitively coupled via a capacitor to a first semiconductor switch responsive to a first reference voltage and forming a clamp. The clamp generates a second parabola waveform having a peak level, at the end of trace, that is determined by the first reference voltage. The clamping operation of the first semiconductor switch causes the capacitor to charge in a manner to provide level shifting. Advantageously, at selectively different peak-to-peak amplitudes of the first parabola waveform, the peak amplitude of the second parabola waveform remains the same. Thus, the level shifting, advantageously, preserves the ability to select different peak-to-peak amplitudes of the second parabola waveform. A second semiconductor switch, responsive to a periodic switch control signal and to a second reference voltage, replaces in the second parabola waveform an undesirable waveform portion of the first parabola waveform that occurs between the end of trace and the beginning of the immediately following trace of the second parabola waveform with a constant level. The constant level is determined in accordance with the second reference voltage. Thereby, the undesirable waveform portion is, advantageously, removed.  
       SUMMARY OF THE INVENTION  
       [0007]     A waveform generator, embodying an inventive feature includes a source of a periodic input correction signal. A first semiconductor switch is coupled to a capacitor and is responsive to a signal at a first reference level for developing a direct current voltage in the capacitor that level shifts the periodic, input correction signal. The direct current voltage in the capacitor is level shifted by an amount determined in accordance with the first reference level. A second semiconductor switch is responsive to the level shifted, periodic input correction signal and to a periodic switch control signal for generating a periodic output dynamic correction signal. The periodic output dynamic correction signal has a frequency related to a deflection frequency and a waveform portion, controlled by an operation of the second semiconductor switch. The waveform portion occurs, during a corresponding portion of a period of the output dynamic correction signal. The dynamic correction signal is coupled to a cathode ray tube to vary a field in a beam path of an electron beam of the cathode ray tube for providing dynamic correction. 
     
    
     BRIEF DESCRIPTION OF THE DRAWING  
       [0008]      FIG. 1   a  is a simplified diagram in block and schematic form illustrating inter alia a dynamic focus and high voltage-related focus signal combiner and a parabola voltage generating circuit, according to an aspect of the invention;  
         [0009]      FIG. 1   b  is a more detailed diagram of a portion of the dynamic focus and high voltage-related focus signal combiner of  FIG. 1   a;    
         [0010]      FIG. 1   c  is an alternative embodiment for the parabola voltage generating circuit of  FIG. 1   a , according to another aspect of the invention; and  
         [0011]      FIG. 2  is a simplified equivalent diagram of an arrangement in which three picture tubes are used. 
     
    
     DESCRIPTION OF THE INVENTION  
       [0012]     In  FIG. 1   a , a television apparatus designated generally as  10  includes at lower right a cathode-ray tube (CRT) or kinescope  12  which includes a screen  12   s , an ultor or high voltage (anode) terminal  12 U, a focus terminal  12 F, and a cathode  12 C. Cathode  12 C of CRT  12  is illustrated as being connected to a source of image signal in the form of video source  14 . As noted in  FIG. 1   a , CRT  12  may be one of three similar CRTs, as might be used, for example, in a projection television arrangement.  
         [0013]     The ultor or high voltage terminal  12   u  of CRT  12  of  FIG. 1   a  is connected by way of a conductor  9  to an ultor or high voltage and focus voltage source illustrated as a block  49 . Block  49  is illustrated in more detail in  FIG. 1   b . In  FIG. 1   b , elements corresponding to those of  FIG. 1   a  are designated by like reference numerals. Structure  49  of  FIG. 1   b  includes an integrated high voltage/focus voltage transformer/rectifier arrangement designated generally as  50 , which includes a primary winding  50   p  having one end connected to a source of regulated B+ and another end connected to a horizontal output transistor illustrated as a block  218 , which is a part of deflection block  18  at upper left of  FIG. 1   a . Transformer  50  of  FIG. 1   b  also includes a distributed secondary winding made up of secondary sections designated  50   s , with a rectifier or diode, some of which are designated  52 , located between each pair of secondary sections. The uppermost secondary winding  50   s  in transformer  50  is connected by way of the serial combination of an inductor  50   i  and a further rectifier or diode  52 ′ to high voltage conductor  9 , from which the high voltage is coupled to ultor terminal  12   u  of  FIG. 1   a . The lowermost secondary winding  50   s  of transformer  50  of  FIG. 1   b  is connected by way of the series combination of an inductor  50   i   2  and a diode  52 ′ to ground. Resistor  4 R′ represents the distributed resistance of the secondary windings  52  lying above tap  50 , and a capacitor C′ connected between transformer terminal  9  and tap  50   t  represents the distributed capacitance of the windings lying above tap  50   t . Similarly, resistor  2 R′ represents the distributed resistance of windings  52  and inductor  50   i   2 , lying below tap  50   t  of transformer  50 , and capacitor  2 C′ represents the distributed capacitance. Tap  50   t  of transformer  50  of  FIG. 1   b  is connected by way of a focus voltage conductor  11  to input terminal  26   i   2  of focus control  26  of  FIG. 1   a . Within focus control  26  of  FIG. 1   a , the focus voltage from transformer  50  is coupled to focus terminal  12 F by means of a focus control  26  voltage divider designated as  28 . Voltage divider  28  includes resistors R 101  and R 102 , with a tap  28   t  therebetween. Tap  28   t  is connected to focus terminal  12 F of CRT  12 . Focus control  26  includes an input port  26   i   1  to which other focus signals may be applied.  
         [0014]     Also in  FIG. 1   a , a deflection arrangement (Defl) illustrated at upper left as a block  16  receives composite (COMP) video or at least separated synchronization signals at a port  16   i . Deflection arrangement  16  produces vertical and horizontal deflection signals, illustrated together as being generated at an output terminal  16   o  and applied by way of a path  19  to deflection windings, illustrated together as  12 W, which is or are associated with the CRT  12 , all as known in the art. Deflection arrangement  16  also includes a deflection processor  18 , which for example is a Toshiba TA1317AN deflection processor. Deflection processor  18  produces horizontal dynamic focus signals at an output port  18 H, and vertical dynamic focus signals at an output port  18 V.  
         [0015]     A dynamic focus combining circuit and amplifier, designated generally as  20  in  FIG. 1   a , includes a differential amplifier  22  including NPN transistors Q 5  and Q 6 , together with a common emitter resistor R 10  and base resistors R 504  and R 505 . Vertical dynamic focus signals from terminal  18 V of deflection processor  18  are applied by way of an AC-gain determining resistor R 301  and a dc blocking capacitor C 301  to a first input port  22   i   1  of differential amplifier  22 . A voltage divider including resistors R 1  and R 12  provides bias and additional AC gain control for input terminal  22   i   1  of differential amplifier  22 . Horizontal dynamic focus signals produced at terminal  18 H of deflection processor  18 , contain, or are associated with, a retrace parabola. The retrace parabola is removed from the horizontal dynamic focus signals in order to limit the bandwidth of the signals so that following slew-rate-limited circuits can respond usefully. The horizontal rate dynamic focus signals are applied from output terminal  18 H of deflection processor  18  to an input port  24   i  of a retrace parabola removal circuit  24 . The retrace parabola is removed from the horizontal dynamic focus signal by retrace parabola removal circuit  24 , which includes transistors Q 201  and Q 202 , diodes D 201 , D 201 , and D 203 , capacitors C 201  and C 202 , and resistors R 16 , R 201 , R 202 , R 203 , R 204  and R 205 .  
         [0016]     In  FIG. 1   a , retrace parabola removal circuit  24 , embodying an inventive feature, includes the series combination of a resistor R 16 , a coupling capacitor C 201  and a resistor R 205  electrically connected between input port  24   i  and the base of inverting amplifier transistor Q 401 . In the absence of switching transistor Q 201 , the horizontal-rate dynamic focus signals would be, or are, coupled from input port  24   i  to output port  24   o  with the positive peak portion of the signal at  24   i  inverted to a negative peak and clamped to near ground potential at terminal  24   o . A source  24 H of horizontal retrace pulses couples positive-going pulses by way of a resistor R 204  and a capacitor C 202 , coupled in parallel, to the base of a grounded-emitter NPN transistor Q 202 . Transistor Q 202  is nonconductive during the horizontal trace interval, and conductive during the horizontal retrace interval. When transistor Q 202  is nonconductive during the horizontal trace interval, PNP transistor Q 201  receives no base bias, and is nonconductive. During horizontal retrace, when transistor Q 202  is conductive, a voltage divider including resistors R 202  and R 203  applies a forward bias to the base-emitter junction of transistor Q 201 , as a result of which transistor Q 201  turns ON. The emitter current of transistor Q 201  flows through a diode D 201  to the +V 1  supply voltage, so the emitter of transistor Q 201  is held at a voltage which is one semiconductor junction voltage drop (one VBE) below or more negative than the +V 1  source voltage. Transistor Q 201  also saturates or achieves a state of little collector-to-emitter voltage drop, so the collector of Q 201 , and therefore the base voltage of inverter transistor Q 401 , rises to within one VBE of the +V 1  source. There is then very little or no current flowing in resistor R 401  because a voltage in excess of one semiconductor junction voltage drop (one VBE) is required to turn on inverter transistor Q 401 . With transistor Q 401  off there is no current flow in collector resistor R 402  and voltage  24   o  across Resistor R 402  is zero. Thus, output voltage  24   o  of retrace parabola removal circuit  24  is set to a fixed voltage, at or very near ground, during horizontal retrace, regardless of the magnitude of the horizontal dynamic focus signal applied to input port  24   i . A diode D 202  and a resistor R 201  together form a voltage divider that provides a reference voltage two (2) diode voltage drops (2 VBE) below or more negative than the +V 1  voltage source applied to the anode of D 201 . Thus, the cathodes of diodes D 202  and D 203  are 2 VBE below +V 1 . Diode D 203  together with capacitor C 201  clamps the most positive portion of the horizontal dynamic focus waveform to the voltage at the emitter of transistor Q 201 . During horizontal retrace the voltage at the collector of transistor Q 201  is fixed. The voltage at the junction terminal between resistor R 16  and capacitor C 201  decreases due to the undesired retrace pulse that is part of the horizontal dynamic focus waveform at terminal  24   i . Resistor R 205  limits current flow in capacitor C 201  during horizontal retrace to prevent the voltage across capacitor C 201  from changing to a value that is not related to the desired value resulting from peak detection. During horizontal trace the high input impedance of transistor Q 401  prevents signal attenuation due to resistor R 205 . The voltage drops across diodes D 202  and D 203  cancel each other, and minimize changes in the clamped output signal due to temperature-dependent changes in the diode VBE. Similarly, diode  201  cancels the VBE drop in transistor Q 401  such that the collector current from Q 401  is zero during the most positive portion of the waveform at the base of transistor Q 401 . This clamps to ground the most negative portion of the waveform appearing in inverted form across resistor R 402 , including that portion or part eliminated during horizontal retrace by switching transistor Q 201 . The ground clamping action maintains a predictable direct voltage or DC if the horizontal dynamic focus waveform amplitude changes, as for example by bus control of Deflection Processor IC  18 .  
         [0017]      FIG. 1   c  illustrates a parabola removal circuit  24 ′, that can be substituted in  FIG. 1   a  for parabola removal circuit  24 . Similar symbols and numerals in  FIGS. 1   a  and  1   c  indicate similar items or functions. The horizontal dynamic focus voltage waveform from output  18 H of deflection processor integrated circuit  18  of  FIG. 1   a  contains both a desired parabola shaped waveform, during the horizontal trace time, and an undesired parabola shaped waveform, during the horizontal retrace time. The horizontal dynamic focus voltage waveform from output  18 H is developed at input  24   i  of retrace removal circuit  24 ′ of  FIG. 1   c  coupled through a resistor R 16 ′ and a capacitor C 201 ′, coupled in series, to the anode of a diode D 203 ′ and also to a base of an inverting amplifier transistor Q 401 ′. The cathode of diode D 203 ′ is coupled to a voltage reference circuit  500 .  
         [0018]     Circuit  500  includes a voltage divider formed by a pair of series coupled resistors R 206  and R 207 . A junction terminal between resistors R 206  and R 207  is formed at a base of a transistor Q 203  to provide negative feedback. The feedback causes a collector-to-emitter voltage, Q 203 Vce, of transistor Q 203  to track a base-to- emitter voltage Q 203 Vbe of transistor Q 203  according to the gain relationship: Q 203 Vce/Q 203 Vbe=(R 206 +R 207 )/R  206 . The symbols Q 203 Vce and Q 203 Vbe in the equation indicate the corresponding values of the items. The values of resistors R 206  and R 207  can be selected for values of gain greater than one. A collector resistor R 201 ′ of transistor Q  203  supplies a return to ground for currents either through transistor Q 203 , resistors R 206  and R 207  or diode D 203 .  
         [0019]     Capacitor C 201 ′ and diode D 203 ′ act as a peak detector such that during the initial cycles of the waveform at terminal  24   i , capacitor C 201 ′ will charge to have, across capacitor C 201 ′, an average voltage VC 201 ′. As a result, the positive peaks of the waveform at the base of transistor Q 401 ′ are at a level one silicon semiconductor junction (Vbe) voltage above the collector voltage of transistor Q 203  developed across resistor R 201 ′. The collector voltage of transistor Q 203  is, in turn, below a 9 volt supply voltage V 1 , developed at the emitter of transistor Q 203 , by the value of collector-to-emitter voltage Q 203 Vce. The voltage at the emitter of transistor Q 401 ′ will be 1 Vbe above transistor Q 401 ′ base voltage.  
         [0020]     To prevent current flow in transistor Q 401 ′ and a collector resistor R 402 ′, the voltage across resistor R 401 ′ has to be near zero. Therefore, the value of resistor R 207  is selected so that collector-to-emitter voltage Q 203 Vce is equal to the sum of the voltage across diode D 203 ′ and the turn on threshold voltage of transistor Q 401 ′. This sum voltage is slightly less than 2 Vbe because the turn on threshold base-emitter voltage of transistor Q 401 ′ is less than the value to fully turn on transistor Q 401 ′.  
         [0021]     The waveform across resistor R 402 ′ at terminal  24   o  will appear inverted relative to that at terminal  24   i  with the inverted peaks at ground potential. If the amplitude of the waveform at terminal  24   i  is changed or adjusted, the inverted peaks appearing at terminal  24   o  will remain fixed at ground potential and the positive going amplitude will change with respect to this ground reference.  
         [0022]     As the circuit operating temperature changes, the voltage across transistor Q 203  will change so as to cancel or compensate the changes in the voltages across diode D 203 ′ and in the base-emitter voltage of transistor Q 401 ′ such that the inverted peak ground clamp at terminal  24   o  remains within 0.1 volts of ground. During horizontal retrace, a switching transistor Q 202 ′ is turned on via a positive horizontal retrace pulse at source  24 H′. A resistor R 204 ′ limits base current to transistor Q 202 ′ during the pulse and a capacitor C 202 ′ aids in turning transistor Q 202 ′ off quickly from a saturated turn on state at the end of the retrace pulse. During the retrace pulse, current from transistor Q 401 ′ that would result from the operation of transistor Q 401 ′ that inverts the unwanted retrace parabola is diverted to ground via transistor Q 202 ′ so that ground voltage is maintained at output terminal  24   o . Transistor Q 401 ′ isolates the peak detecting and clamping portion of circuit  24 ′, that includes diode D 203 ′ and capacitor C 201 ′, from the parabola removal portion, that includes transistor Q 202 ′ so that the voltage across capacitor C 201 ′ is advantageously, unaffected by the operation of transistor Q 202 ′.  
         [0023]     The horizontal dynamic focus signals with retrace parabola removed are generated at an output port  24   o  of retrace parabola removal circuit  24  of  FIG. 1   a , and are applied to the base of an inverting amplifier including PNP transistor Q 401  and resistors R 401  and R 402 . The amplified horizontal dynamic focus signals (with retrace parabola removed) are capacitively coupled from the collector of transistor Q 401  by way of the series-parallel combination of an AC gain determining resistor R 17  and capacitors C 24  and C 401  to the second input port  22   i   2  of differential amplifier  22 . Differential amplifier  22  produces collector currents from both transistors which are related to the combination of the vertical and horizontal dynamic focus signals. The currents in the collector of transistor Q 6  flow to direct voltage supply V 1  without any effect. The current flow in the collector of Q 5  represents the desired combined dynamic focus signals.  
         [0024]     The “dynamic focus amplifier” designated generally as  17  in  FIG. 1   a  includes differential amplifier  22 , a Q 1  Protection Circuit designated as a block  25 , a Q 1  Bias Detector circuit  32 , feedback components R 2  and C 504 , direct-current (DC) gain determining resistors R 5 , R 11 , and R 12 , vertical gain determining components R 301 , C 301 , R 11 , and R 12 , horizontal gain determining components C 401 , C 24 , and R 17 , and surge limiting resistors R 503  and R 25 , all of which are discussed below. Terminal  17   o  is the output port of the dynamic focus amplifier  17 .  
         [0025]     A transistor Q 20  of  FIG. 1   a  is connected in a cascode arrangement with transistor Q 5  of differential amplifier  22 , with a low-value surge-protection resistor R 506  therebetween. Transistor Q 20  is a high-voltage transistor with low current gain and high voltage gain. The base of transistor Q 20  is connected by a surge protection resistor R 25  to direct voltage source V 1 , so the emitter of transistor Q 20  can never rise above voltage V 1 . This arrangement also maintains constant voltage at the collector of transistor Q 5 , so there is no voltage change at the collector which can be coupled through the collector-to-base “Miller” capacitance to act as degenerative feedback at higher frequencies, so that transistor Q 5  maintains a broad bandwidth.  
         [0026]     Transistors Q 1  and Q 20  of  FIG. 1   a , and their ancillary components, together constitute a portion of high-voltage dynamic focus signal amplifier  17  for amplification of the combined dynamic focus signals. The load on the dynamic focus signal amplifier  17  is largely capacitive and equal to the parallel combination of capacitors C 602 , Cwire, and CT 1  in the CRT(s) which is(are) driven with amplified dynamic focus signal. This parallel capacitance is charged through transistor Q 1  and discharged through transistor Q 20 . In  FIG. 1   a , the collector of NPN transistor Q 1  is connected by way of a diode D 501  to receive supply voltage V 2 , and its emitter is connected by way of a resistor R 501  and a zener diode D 4  to the collector of transistor Q 20 . The base of transistor Q 1  is connected by a conductor  60  to the collector of transistor Q 20 . The base of transistor Q 1  is also connected by way of a resistor R 502  to the junction of a capacitor C 501  and the cathode of a diode D 502 . The other end of capacitor C 501 , and the cathode of a zener diode D 503 , are connected to the junction of resistor R 501  with the anode of zener diode D 4 . The cathode of diode D 502  and the anode of zener diode D 503  are connected to output terminal  17   o  of Q 1  bias detector  32 . Resistor R 2  in parallel with capacitor C 504  provide degenerative feedback from a location near the output terminal  17   o  to input port  22   i   2  of differential amplifier  22 .  
         [0027]     In operation of dynamic focus signal amplifier  17  of  FIG. 1   a , the collector current of transistor Q 5  is coupled through The emitter-to-collector path of transistor Q 20 , diode D 4 , capacitor C 501  and diode D 502  to the output  17   o  of dynamic focus amplifier  17 . As a result of the current flow from transistor Q 20  to output terminal  17   o , capacitor C 501  charges. The charging continues until the zener or breakdown voltage of zener diode D 503  is reached, after which time D 503  conducts so as to hold the voltage across capacitor C 501  constant and equal to the zener voltage. A small fraction of the collector current of Q 20  flows through resistor R 502 . During conduction of collector current in transistor Q 20 , transistor Q 1  is maintained OFF or nonconductive because the voltage drop across zener diode D 4  reverse-biases the base-emitter junction of transistor Q 1 .  
         [0028]     When collector current in transistor Q 20 l of  FIG. 1   a  decreases to zero during a portion of the operating cycle of dynamic focus signal amplifier  17 , transistor Q 1  is turned ON or rendered conductive by discharge of capacitor C 501  through resistor R 502 , the base-emitter junction of transistor Q 1 , and resistor R 501  back to capacitor C 501 . With Q 1  conductive, a substantial Q current tends to flow from supply V 2  through diode D 501 , the collector-to-emitter path of transistor Q 1 , resistor R 501 , and forward-biased diode D 503  to the amplifier output terminal  17   o . Overcurrent damage to transistor Q 1  is prevented by a feedback voltage developed across emitter resistor R 501 , which limits the collector current to a value established by the zener voltage of diode D 4  (minus one base-emitter junction voltage) felt across the emitter resistor R 501 , so that Q 1  operates at constant current when the zener voltage is reached. Capacitor C 501  stores sufficient charge to keep Q 1  ON during that entire portion of the amplifier cycle during which Q 20  is OFF, and also to keep Q 1  ON when the collector-to-emitter voltage of Q 1  is low. This allows the maximum positive amplifier voltage to closely approach the voltage of supply V 2 . Resistor R 1 , connected between the positive V 2  supply and output terminal  17   o , precharges capacitor C 501  at start-up so that the cyclic AC pumping operation can start. Diode D 501  in conjunction with resistor R 502  tend to protect transistor Q 1  from overcurrent through its collector-to-base junction in the event of an internal arc in picture tube  12  between the high voltage or ultor terminal  12 U and the focus terminal  12 F.  
         [0029]     Amplifier  17  of  FIG. 1   a may be considered to be a high voltage operational amplifier, at least from the point of view of its output terminal  17   o . In this operational amplifier, resistor R 2  and capacitor C 504  provide feedback from output to input, and resistors R 5 , R 11 , and R 12  set the direct (DC) operating point. Resistor R 17  and capacitor C 24  set the dynamic or AC gain for horizontal-rate dynamic focus signals, while resistors R 301 , R 11 , and R 12  together with capacitor C 301  set the dynamic or AC gain for vertical-rate dynamic focus signals.  
         [0030]     The amplified combined vertical and horizontal dynamic bias signals produced at output port  17   o  of Q 1  Bias Detector  32  of  FIG. 1   a  may be viewed as being produced by a low-impedance source. The signals are applied from port  17   o  through a surge limiting resistor R 503  to a first input port  34   i   1  of a beam current load sensing focus tracking circuit  34  (“combining” circuit  34 ). A second input port  34   i   2  is connected to the ultor terminal  12 U of picture tube  12 , for receiving the ultor voltage. An output port  34   o  of beam current load sensing focus tracking or combining circuit  34  is connected to input port  26   i   1  of focus control block  26 , and possibly to other corresponding focus controls associated with other picture tubes than picture tube  12 , all illustrated together as a block  36 . A cost saving according to one aspect of the invention is achieved over regulated high voltage sources by allowing the high voltage to vary in response to beam current. Thus, high voltage source  49  is not regulated.  
         [0031]     As illustrated in  FIG. 1   a , a resistor R 601  is connected in parallel with a capacitor C 601 , and the parallel combination of R 601  with C 601  is connected at one end to input port  34   i   1  of combining circuit  34 . The other end of the parallel combination of R 601  with C 601  is connected to output port  34   o  of combining circuit  34 . Combining circuit  34  also contains the series combination of a resistor R 602  with a capacitor C 602 , and one end of the series combination is connected to second input port  34   i   2 , while the other end of the series combination is connected to output port  34   o.    
         [0032]     Beam current load sensing focus tracking circuit  34  of  FIG. 1   a  may be viewed as a frequency-sensitive combiner, which combines the combined vertical and horizontal dynamic focus signals applied to its first input terminal  34   i   1  with components of the high voltage applied to its second input port  34   i   2 . The resulting combined signals are applied to input port  26   i   1  of focus control block  26  for combination with a “static” component of the focus voltage.  
         [0033]     The focus control  26  and the beam current load sensing focus tracking circuit  34  of  FIG. 1   a  can be made by using the following values of components  
                                                           R101   50   Megohms           R102   80   Megohms           R601   5.6   Megohms           R602   940   Kilohms           C101   1000   picofarads           C601   470   picofarads           C602   2[00   picofarads                      
 
 The stray wiring capacitance is designated as C wire  and has a value of 10 picofarads, and the capacitance CT 1  of the focus electrode of a single picture tube, such as picture tube  12 , is about 25 picofarads. The output impedance of the Q 1  Bias Detector  32  and the resistance of R 503  are ignored as being too small relative to other values to affect the results. Those skilled in the art will recognize that the series capacitor C 602  connected between second input port  34   i   2  and output terminal  34   o  of combining circuit  34  allows only variations or changes (“sag”) in the high voltage to be coupled to output port  34   o . Similarly, the presence of capacitor C 101  connected between input port  26   i   1  of focus control block  26  and tap  28 t of voltage divider  28  prevents the coupling of direct signal components to the tap  28 t. Capacitor C 101  together with the parallel combination of resistors R 101  and R 102  constitutes a high-pass filter having a cutoff or break frequency of about 5 Hertz (Hz). 
 
         [0034]      FIG. 2  is a simplified equivalent circuit or schematic diagram of a television or video display apparatus according to an aspect of the invention in which red, green, and blue cathode-ray or picture tubes are used for the display. The red, green and blue picture tubes are illustrated as blocks  12 R,  12 G, and  12 B, respectively, their ultor terminals are identified as  12 UR,  12 UG, and  12 UB, respectively, and their focus terminals are identified as  12 FR,  12 FG, and  12 FB, respectively. In  FIG. 2 , elements corresponding to those of  FIG. 1   a  are designated by like reference numerals. Elements R 101 , R 102 , and C 101  have appended letters R, G or B to identify corresponding elements associated with the red, green and blue cathode-ray tube displays, respectively. In  FIG. 2 , a source V_DF represents the combined vertical and horizontal dynamic focus signal source applied to first input port  34   i   1  of combiner  34 .  
         [0035]     Source V_HV of  FIG. 2  represents the high or ultor supply voltage source. Voltage source V_HV includes an integrated transformer  250  with a primary winding  250   p . Primary winding  250   p  is connected at one end to a source of regulated B+ and at the other end to a block representing a switching horizontal output transistor. Transformer  250  also includes a distributed secondary winding, including a plurality of windings, each of which is designated  250   s . The distributed secondary winding of transformer  250  is grounded at one end. A set of diodes, some of which are designated as  252 , is interspersed between the winding secondary sections  250   s , and act to rectify the high voltage produced on an output conductor illustrated as  209 . A “static” focus voltage is produced at a tap  250   t  of transformer  250 . In one embodiment of the invention, tap  250   t  is a ⅓ tap relative to the ultor voltage, so that the static focus voltage produced at tap  250   t  is about ⅓ of the high voltage produced on conductor  209 , and remains at a fixed percentage of the ultor voltage.  
         [0036]     The high or ultor voltage V_HV is coupled by way of conductor  209  to terminal  34   i   2  of combining circuit  34 , and to the ultor connections  12 UR,  12 UG, and  12 UB of the red, green, and blue picture tubes  12 R,  12 G, and  12 B, respectively, of  FIG. 2 , so that combiner  34  and all the cathode-ray tubes are fed in common from the ultor supply V_HV. The static focus voltage is coupled from tap  250   t  by way of a conductor illustrated as  211  to the red, blue and green focus terminals  12 FR,  12 FG, and  12 FB, respectively, by resistive voltage dividers  126 R,  126 G, and  126 B, respectively. Voltage divider  126 R includes series resistor R 101 R and shunt resistor R 102 R having a tap  126 Rt therebetween. Tap  126 Rt is coupled to red picture tube focus terminal  12 FR. Resistor R 101 R has a value of 50 Megohms and resistor R 102 R has a value of 80 Megohms. Similarly, voltage divider  126 G includes series resistor R 101 G and shunt resistor R 102 G having a tap  126 Gt therebetween. Tap  126 Gt is coupled to green picture tube focus terminal  12 FG. Resistor R 101 G has a value of 50 Megohms, and resistor R 102 G has a value of 80 Megohms. Also, voltage divider  126 B includes series resistor R 101 B and shunt resistor R 102 B having a tap  126 Bt therebetween. Tap  126 Bt is coupled to blue picture tube focus terminal  12 FB. Resistor R 101 B has a value of 50 Megohms and resistor R 102 B has a value of 80 Megohms. Thus, each focus terminal  12 FR,  12 FG, and  12 FB of the red, green, and blue picture tubes “sees” its static focus voltage as being sourced from an impedance of about 30 Megohms, just as in the arrangement of  FIG. 1   a.    
         [0037]     Output terminal  34   o  of combiner  34  of  FIG. 2  is coupled to each of the red, green and blue focus terminals  12 FR,  12 FG, and  12 FB, respectively, by a coupling capacitor C 101 R, C 101 G, and C 101 B, respectively. Each of capacitors C 101 R, C 101 G, and C 101 B has a value of 1000 pF. The capacitance of the red, green and blue picture tubes are designated as CT 1 R, CT 1 G, and CT 1 B, respectively.