Abstract:
In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

Description:
BACKGROUND OF THE INVENTION 
   This invention relates in general to semiconductor power devices and in particular to a trench MOS-gated transistor with reduced miller capacitance. 
     FIG. 1  shows a simplified cross-section view of a conventional vertical trenched gate MOSFET  100 . An epitaxial layer  104  of n-type conductivity type extends over n-type substrate  102  which forms the drain contact region. Well region  106  of p-type conductivity type is formed in an upper portion of epitaxial layer  104 . Gate trench  109  extends through well region  106  and terminates just below the interface between epitaxial layer  104  and well region  106 . Gate trench  109  is lined with a dielectric layer  112  along its sidewalls and bottom, and is filled with polysilicon material  110  forming the transistor gate. Source regions  108  flank each side of trench  109 , and overlap gate  110  along the vertical dimension. In the on-state, a current flows vertically from drain terminal  114  to source terminal  116  through substrate  102 , epitaxial layer  104 , channel regions in well region  106  along the outer sidewalls of trench  109 , and finally source regions  108 . 
   Epitaxial layer  104  together with substrate  102  form the drain region. As can be seen, gate  110  overlaps the drain region along the bottom of trench  109 . It is desirable to minimize this gate-drain overlap in order to improve the transistor switching speed. The gate-drain charge Qgd is proportional to this overlap area and inversely proportional to the thickness of the dielectric along the bottom of trench  109 . Several methods to reduce Qgd have been proposed including reducing the trench width, using thicker dielectric along the trench bottom, eliminating portions of the gate along the trench flat bottom portion, and extending the p-type well region slightly deeper than the trench. Each of these techniques has its own advantages and disadvantages. Some require a more complex process technology, while others are not as effective in reducing Qgd without adversely impacting other device characteristics. 
   Thus, an MOS-gated transistor with improved characteristics including a substantially reduced miller capacitance, and which is simple to manufacture is desirable. 
   BRIEF SUMMARY OF THE INVENTION 
   In accordance with an embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region and a second portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region. 
   In accordance with another embodiment of the present invention, a trench MOS-gated transistor includes a silicon layer of a first conductivity type over a silicon substrate. A well region of a second conductivity type is formed in an upper portion of the silicon layer. A gate trench extends through the well region and terminates within the silicon layer. Source regions of the first conductivity type flank each side of the gate trench. The gate trench is filled with a polysilicon material at least up to and partially overlapping with the source regions. A silicon region of the second conductivity type extends along a bottom portion of the trench such that a gap is formed between the silicon region and the well region through which gap a current flows when the transistor is in an on state. 
   In accordance with another embodiment of the invention, a trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region. 
   In accordance with yet another embodiment of the invention, a trench MOS-gated transistor is formed as follows. An epitaxial layer of a first conductivity type is formed over a substrate. A well region of a second conductivity type is formed in an upper portion of the epitaxial layer. A trench is formed which extends through the well region and terminates within the epitaxial layer. Dopants of the second conductivity type are implanted along the bottom of the trench to form a region of the second conductivity type extending along a bottom portion of the trench such that a gap is formed between the region of the second conductivity type and the well region through which gap a current flows when the transistor is in an on state. 
   These and other embodiments of the invention will be described with reference to the accompanying drawings and following detailed description. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a simplified cross-section view of a conventional vertical trenched gate MOSFET; 
       FIG. 2A  shows a simplified cross section view of a vertical trenched-gate MOSFET in accordance with an embodiment of the present invention; 
       FIG. 2B  shows a simplified top layout view of the vertical trenched-gate MOSFET in  FIG. 2A ; 
       FIG. 3  shows a simplified cross section view of a vertical trenched-gate MOSFET in accordance with another embodiment of the present invention. 
       FIG. 4  shows a simplified top layout view of an alternate embodiment of the present invention wherein the cell structures in  FIGS. 2A and 3  are combined; 
       FIG. 5  shows the current and voltage waveforms for the  FIG. 2A  MOSFET embodiment versus those for the prior art  FIG. 1  MOSFET; and 
       FIG. 6  shows current and voltage waveforms for the  FIG. 3  MOSFET versus those for the prior art  FIG. 1  MOSFET. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   In accordance with an embodiment of the invention, the gate-drain capacitance of a MOSFET is reduced by using an implant region under the trenched gate wherein the implant region is contiguous with the well region of the MOSFET. The implant region makes the area of the trench under which it is formed inactive as it blocks conduction in the corresponding portion of the transistor channel. One suitable application for this embodiment would be high voltage devices in which the contribution of the channel resistance to the transistor on resistance Rdson is low. In another embodiment, an implant region under the gate trench is formed such that there is a gap between the implant region and the well region through which the channel current can flow. In this embodiment, the impact of the implant region on Rdson is minimized, and thus a suitable application for this embodiment would be low voltage devices. Both these embodiments are particularly useful in designs requiring a tight trench cell pitch such as tight alternating pn pillar pitch of a superjunction device or low Rdson. These two embodiments may be combined together in a single MOSFET. Alternatively, one of both of these embodiments may be combined with the prior art structure shown in  FIG. 1  as needed. 
     FIG. 2A  shows a simplified cross section view of a vertical trenched-gate MOSFET  200  in accordance with an embodiment of the present invention. An epitaxial layer  204  of n-type conductivity type extends over n-type substrate  202  which forms the drain contact region. Well region  206  of p-type conductivity type is formed in an upper portion of epitaxial layer  204 . Gate trench  209  extends through well region  206 . A portion  206   a  of well region  206  directly below trench  209  extends deeper into epitaxial layer  204  than other portions of well region  206  such that gate trench  209  terminates within portion  206   a . Gate trench  209  is lined with a dielectric layer  212  along its sidewalls and bottom. Trench  209  is filled with polysilicon material  210  forming the transistor gate. Source regions  208  flank each side of trench  209  and overlap gate  210  along the vertical dimension. In an alternate embodiment, trench  209  is partially filled with polysilicon material with dielectric material atop the polysilicon. Note that one or more of substrate  202 , epitaxial layer  204 , well region  206  including portion  206   a , and source regions  208  may be from crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or silicon germanium (SiGe). 
   In  FIG. 2A , because gate  210  does not overlap epitaxial layer  204 , no channel is formed above portion  206   a  in the on state. In one variation of the  FIG. 2A  embodiment, the trenched-gate cell is stripe shape (i.e., is laid out in an open cell configuration) as shown in the simplified top layout view in  FIG. 2B . Stripe-shaped trenched-gate  210  extends vertically with source regions  208  flanking each side of trenched-gate electrode  210 . As shown, deeper extending well portions  206   a  are formed periodically along a length of the striped trenched-gate electrode  210 . Where portion  206   a  is not formed (e.g., along dashed line  1 - 1 ) the cell cross section is similar to that in  FIG. 1  (i.e., gate trench  210  extends clear through well region  206  and terminates within epitaxial layer  204  such the gate trench overlaps epitaxial layer  204  along the vertical dimension). In this manner, in the on state, current flow is established (in a similar manner to that described above in reference to  FIG. 1 ) along those portions of the trench sidewalls below which deeper extending well portions  206   a  are not formed. Current flow is however blocked where deeper extending well portions  206   a  are formed under the gate. The gate-drain overlap is thus reduced by an amount corresponding to portions  206   a . Further, since the total well region  206  is increased in size, the gate to source capacitance or Qgs increases. Thus, the Qgd/Qgs ratio advantageously decreases further. The switching characteristics of the MOSFET are therefore substantially improved. 
   In one embodiment, the  FIG. 2A  structure is formed as follows. Epitaxial layer  204  is formed over substrate  202  using conventional techniques. Well region  206  is formed in an upper portion of epitaxial layer  204  by implanting and driving in p-type dopants using known techniques. Trench  209  is then formed by etching the silicon using conventional silicon etch techniques. Using a masking layer, the bottom of trench  209  is then selectively implanted with p-type dopants to thus form regions  206   a . In one embodiment, an implant dose in the range of 1×10 13 -1×10 14  cm −3  and an implant energy in the range of 40-120 KeV are used. In another embodiment, the thickness of region  206   a  at its deepest point is in the range of 0.2-0.41 μm. Dielectric layer  212 , doped polysilicon  2210  filling trench  209 , and source regions  208  are all formed using conventional methods. 
     FIG. 3  shows a simplified cross section view of a vertical trenched-gate MOSFET  300  in accordance with another embodiment of the present invention. Cross section view of MOSFET  300  is similar to that in  FIG. 2A  except that instead of the deeper extending well portion  206   a , p-type region  307  is formed directly below trench  309 . As shown in  FIG. 3 , region  307  is formed such that there is a gap between well region  306  and region  307  at each of the bottom corners of trench  309 . During the on state, current flows through these gaps. Thus, by using region  307  with gaps as shown, the gate-drain overlap is significantly reduced without blocking the current flow. In one embodiment, region  307  is formed by carrying out a shallow boron implant through the bottom the trench using an implant energy in the range of 30-80 KeV. In one embodiment, region  307  has a thickness in the range of 0.1-0.3 μm, and the gap between region  307  and well region  306  is in the range of 0.1-0.3 μm. As in the  FIG. 2A  embodiment, one or more of substrate  302 , epitaxial layer  304 , well region  306 , region  307 , and source regions  308  may be from crystalline silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or silicon germanium (SiGe). 
   In the stripe-shaped cell layout embodiment, region  307  may be continuous along the length of the striped trench gate. Region  307  may be extended up at the ends of or other locations along the striped trench gate to electrically contact well region  306 . Alternatively, region  307  is not biased and thus is allowed to electrically float. In an alternate embodiment, similar to the layout shown in  FIG. 2B , a number of p-type regions  307  are formed periodically along the length of the stripe such that the cell structure along portions of the stripe (e.g., at dashed line  1 - 1 ) is similar to that in prior art  FIG. 1 . Alternatively, the  FIG. 2A  and  FIG. 3  embodiments may be combined as shown in the layout diagram in  FIG. 4 . In  FIG. 4 , regions  206   a  correspond to region  206   a  in  FIG. 2A  and regions  307  correspond to region  307  in  FIG. 3 . As indicated by the two arrows, no current conduction occurs where regions  206   a  are formed, but current can flow where regions  307  are formed as well as between regions  206   a  and  307 . The particular arrangement of regions  307  and  206   a  is not limited to that shown in  FIG. 4 . Many other arrangements are possible. In yet another embodiment, the regions between regions  206   a  and  307  are eliminated such that nowhere along the stripe is a cell structure similar to that shown in the prior art  FIG. 1  is formed. 
   In one embodiment of the invention, the well region  206  and region  206   a  under the gate trench in  FIG. 2A , and the well region  306  and the region  307  under the gate trench in  FIG. 3  may be formed as follows. A shallow blanket implant (in the active region) of p-type dopants into the epitaxial layer is carried out. A deep implant of p-type dopants into selected areas of the epitaxial layer is then carried out using a masking layer. These two implant steps may be carried out in reverse order. A temperature cycle is then carried out to drive both implanted dopants deeper into the epitaxial layer. As a result, a well region corresponding to the shallow blanket implant and predefined silicon regions corresponding to the deep implant are formed in the epitaxial layer such that the deepest portion of the predefined silicon regions is deeper than a bottom surface of the well region. To obtain the structure in  FIG. 2A , the above two implant steps and the temperature cycle need to be designed so that after driving in the dopants, the silicon regions are contiguous with the well regions. Alternatively, to form the structure in  FIG. 3 , the two implant steps and the temperature cycle need to be designed so that after the dopants are driven in and the gate trench is formed, a gap is formed between each of the silicon regions and the well region. In view of this disclosure, one skilled in the art would know how to design the two implant steps and the temperature cycle in order to obtain the structures shown in  FIGS. 2A and 3 . 
   In another method of forming the well region  206  and region  206   a  under the gate trench in  FIG. 2A , and the well region  306  and the region  307  under the gate trench in  FIG. 3 , a shallow implant of p-type dopants into selected areas of the epitaxial layer is first carried out using a masking layer. A temperature cycle is then performed to drive the implanted dopants deeper into the epitaxial layer. A blanket implant (in the active region) of p-type dopants into the first silicon region is then carried out. A second temperature cycle is then performed to drive the implanted dopants from the blanket implant step deeper into the epitaxial layer and to drive the dopants from the shallow implant step even deeper into the epitaxial layer. As a result, a well region corresponding to the blanket implant and silicon regions corresponding to the shallow implant are formed such that the deepest portion of the silicon regions is deeper than a bottom surface of the well region. To obtain the structure in  FIG. 2A , the above two implant steps and two temperature cycles need to be designed so that after driving in the dopants the silicon regions are contiguous with the well regions. Alternatively, to form the structure in  FIG. 3 , the two implant steps and the two implant steps need to be designed so that after the dopants are driven in and the gate trench is formed, a gap is formed between each of the silicon regions and the well region. As with the preceding embodiment, in view of this disclosure, one skilled in the art would know how to design the two the implant steps and the two temperature cycles in order to obtain the structures shown in  FIGS. 2A and 3 . 
   The table below shows the simulation results for Qgs, Qgd, and Qgd/Qgs ratio for each of MOSFET  100  in prior art  FIG. 1 , MOSFET  200  in  FIG. 2A , and MOSFET  300  in  FIG. 3 . A 600V superjunction MOSFET with a 6 μm pitch and 0.6 μm trench width was used for the simulation. 
   
     
       
             
             
             
             
             
           
             
             
             
             
             
           
         
             
                 
                 
             
             
                 
               Parameter 
               FIG. 1 
               FIG. 2A 
               FIG. 3 
             
             
                 
                 
             
           
           
             
                 
             
           
        
         
             
                 
               Qgs nC/cm 2   
               72.8 
               103.8 
               73.2 
             
             
                 
               Qgd nC/cm 2   
               36.4 
               27.3 
               31.6 
             
             
                 
               Qgd/Qgs 
               0.50 
               0.26 
               0.43 
             
             
                 
                 
             
           
        
       
     
   
   As can be seen MOSFETS  200  and  300  both have lower Qgd than prior art MOSFET  100 , and both have higher Qgs than prior art MOSFET  100 . A lower Qgd/Qgs ratio is thus obtained for both MOSFETs  200  and  300  than that for MOSFET  100 . The simulation waveforms in  FIGS. 5 and 6  show similar results.  FIG. 5  shows the Idrain, Vdrain, and Vgate for the  FIG. 2A  MOSFET and for the prior art  FIG. 1  MOSFET, and  FIG. 6  shows the same parameters for the  FIG. 3  MOSFET and the prior art  FIG. 1  MOSFET. 
   The cross-section views and top layout view of the different embodiments may not be to scale, and as such are not intended to limit the possible variations in the layout design of the corresponding structures. Also, the various transistors can be formed in cellular architecture including hexagonal or square shaped transistor cells. 
   Although a number of specific embodiments are shown and described above, embodiments of the invention are not limited thereto. For example, it is understood that the doping polarities of the structures shown and described could be reversed and/or the doping concentrations of the various elements could be altered without departing from the invention. As another example, the various exemplary vertical transistors described above have the trenches terminating in the drift regions, but they can also terminate in the more heavily doped substrate. As yet another example, the present invention is shown and described in the context of vertical MOSFET embodiments, but regions  206   a  in  FIG. 2A and 307  in  FIG. 3  can be similarly formed in other trenched gate structures such as trenched gate IGBTs and lateral trenched gate MOSFETs. 
   Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claim, along with their full scope of equivalents.