Abstract:
The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional patent application of pending U.S. patent application Ser. No. 11/306,746, entitled “Integrated Circuit Comb Capacitor,” filed on Jan. 10, 2006. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates generally to semiconductor devices, and more particularly to an improved integrated circuit comb capacitor. 
         [0004]    2. Description of the Related Art 
         [0005]    As ULSI integrated circuits scale to smaller dimensions and increased function and circuit density, many electronic functions that were formerly off-chip are now being incorporated on-chip. These then take advantage of fabrication economies as well as reduced electrical signaling distances to become cheaper and add higher system function and higher performance. One family of devices that has been the focus of increased innovation for on-chip integration is BEOL passive devices. Although interconnects themselves are, strictly speaking, also passive devices, that term is conventionally applied to other passive electronic devices such as resistors, capacitors, inductors, and varactors. Although resistors and capacitors have always been integrated in the FEOL for transistor logic circuits, those FEOL passive devices suffer from voltage nonlinearities and unwanted parasitic impedances that render them not useful for many types of analogue circuits such as for RF or wireless applications. Inductors in general can only obtain useful parameters when integrated in the BEOL wiring levels. 
         [0006]    For BEOL capacitors, the most common type of device is the planar metal-insulator-metal (MIM) parallel plate capacitor. This requires one or more added photomask levels to fabricate lower and upper electrode plates, the capacitor dielectric, and contacts to the plates. These are usually distinct from other interconnects and via contacts formed in the same wiring level. The disadvantages of MIM capacitors is the number of added masks and process steps, the asymmetry in parasitic capacitive coupling to the substrate of the upper and lower electrodes, the limited dielectric reliability at the small thicknesses needed for sufficient capacitance density, and the chip real-estate occupied which often requires exclusion of wiring from areas directly below the MIM capacitor. 
         [0007]    Another type of BEOL capacitor is the interdigitated comb-comb type; this is comprised of multiple line-to-line capacitor fingers connected in parallel (so their capacitances add) with alternating bias between each pair of lines. The devices rely on standard wiring sidewall depths and minimum interline spacings to maximize their capacitances. These dimensions are such that a single-level comb-comb capacitance density is much smaller per unit layout area than what is possible with the MIM capacitors, and as well the typically larger dimensional deviations associated with the interconnect thicknesses and spacings may make it more challenging to meet design specifications. On the other hand, the interdigitated integrated circuit comb capacitor requires no additional photomasks or processing steps (as long as the same interline dielectric is used) and has no asymmetry in parasitic coupling to the substrate for the two electrodes. 
         [0008]      FIG. 1  shows an integrated circuit comb capacitor  150  created in accordance with the prior art. Therefore, in accordance with the prior art, the capacitor electrodes  150   a  have the same depth and spacing between neighboring capacitor electrodes  150   a  as interconnects  160  formed in the same wiring level. The capacitor is preferably made from copper damascene embedded in a low-k dielectric (∈) material  102  such as SiCOH organosilicate glass. The capacitor electrodes  150   a  are characterized by their lengths (into/out of page), widths, depths, spacings, and if trapezoidal, their sidewall angles (α). When energized as in an active IC circuit, the successive electrodes  150   a  are typically biased in an alternating sense such as Vdd (+) and Ground (−) or with an AC signal to perform the capacitor function. 
         [0009]    More recently, an enhancement to the integrated circuit comb capacitor  150  has been described which solves some of the aforementioned problems. Called the vertical parallel plate (VPP) capacitor, this is comprised of multilevel stacks of interdigitated integrated circuit comb capacitors  150 . With VPP capacitors, areal capacitance densities equal those of the MIM devices, there are still no added photomasks or processing steps, and there is still no asymmetry in parasitics for both electrodes. In addition, when multiple levels are combined, the statistical variations in linewidth and spacing dimensions tend to average out so that more uniform results, better matching, and tighter tolerances may be obtained from chip to chip and wafer to wafer. The disadvantage is the number of levels and layout area required to achieve a given capacitance. 
         [0010]    This disadvantage becomes larger for integration of the VPP capacitor in modern low-k BEOL levels, where capacitance density decreases directly in proportion to the decrease in the interline and interlevel dielectric constants. This disadvantage does not apply to the MIM case which uses a separate capacitor dielectric. However, the other disadvantages of the MIM capacitor remain for integration in low-k BEOL. In addition, with CMOS scaling driving reductions in all wiring dimensions, the interlevel BEOL vertical spacings decrease while the MIM thickness does not, such that fabrication becomes difficult or impossible due to excessive topography over the MIM areas. 
         [0011]    Given the above discussion, there is still a need to obtain larger capacitance densities especially for low-k BEOL integrated capacitors, while adding minimal masking levels, minimizing capacitance tolerances, and preserving symmetry in electrode-substrate coupling parasitics. 
         [0012]    What is needed in the art is an improved low-k BEOL integrated circuit comb capacitor, which minimizes capacitance tolerances and preserves symmetry in parasitic electrode-substrate coupling and that is created with a minimum of additional masking levels or process steps. 
       BRIEF SUMMARY OF THE INVENTION 
       [0013]    The invention is directed to a method and structure. More specifically, the method of the invention is directed to a method for creating a capacitor that comprises a forming and modifying step. The forming step comprises forming a capacitor opening and a non-capacitor opening in dielectric, while the modifying step comprises modifying the dielectric along the surfaces of the capacitor opening such that the modification increases the capacitance of the capacitor. More specifically, the structure of the invention is directed to a capacitor that comprises non-capacitor and capacitor openings. The non-capacitor openings are formed in dielectric and have a prescribed spacing between nearest neighboring non-capacitor openings in same metal line level, while the capacitor openings formed in the dielectric in the same metal line level as the non-capacitor openings have a spacing between nearest neighboring capacitor openings that is less than the prescribed spacing between nearest neighboring non-capacitor openings. 
         [0014]    A first embodiment of the invention is directed to a method for creating a capacitor, comprising the steps of depositing, forming, protecting, creating, expanding, and filling. The depositing step comprises depositing a low-k dielectric. The forming step comprises forming openings in the low-k dielectric with at least one opening comprising a non-capacitor opening and at least one opening comprising a capacitor opening. The protecting step comprises protecting any non-capacitor opening from dielectric constant modification. The creating step comprises creating a porous region along surfaces of the capacitor opening. The expanding step comprises expanding at least one capacitor opening by selectively removing the modified dielectric along the surfaces of the capacitor opening. The filling step comprises filling the non-capacitor opening and the expanded capacitor opening with a conductive material. 
         [0015]    A second embodiment of the invention is directed to method for creating a capacitor, comprising the steps of depositing, removing, forming, protecting, and infusing. The depositing step comprises depositing a low-k dielectric comprising a dielectric matrix and porogen. The removing step comprises removing porogen from the low-k dielectric. The forming step comprises forming openings in the porous dielectric with at least one opening comprising a non-capacitor opening and at least one opening comprising a capacitor opening. The protecting step comprises protecting any non-capacitor opening from dielectric constant modification. The infusing step comprises infusing the porous dielectric along the surfaces of the capacitor opening with a material having a dielectric constant higher than the dielectric constant of the porous dielectric prior to the infusion. 
         [0016]    A third embodiment of the invention is directed to a method for creating a capacitor, comprising the steps of depositing, forming, protecting, infusing, filling, and removing. The depositing step comprises depositing a low-k dielectric comprising a porogen. The forming step comprises forming openings in the low-k dielectric with at least one opening a non-capacitor opening and at least one opening a capacitor opening. The protecting step comprises protecting any non-capacitor opening from dielectric constant fluctuation. The infusing step comprises infusing the porous dielectric along surfaces of the at least one capacitor opening with a material having a dielectric constant higher than the dielectric constant of the porous dielectric prior to infusion. The filling step comprises filling the non-capacitor and capacitor openings with a conductive material. The removing step comprises removing porogen from the low-k dielectric. 
         [0017]    The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have a reduced spacing between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level. The invention creates an integrated circuit comb capacitor with higher capacitance density than prior art integrated circuit comb capacitors with the use of at most one additional, noncritical photomask. 
         [0018]    For at least the foregoing reasons, the invention improves upon integrated circuit comb capacitors. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]    The features and the element characteristics of the invention are set forth with particularity in the appended claims. The figures are for illustrative purposes only and are not drawn to scale. Furthermore, like numbers represent like features in the drawings. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows, taken in conjunction with the accompanying figures, in which: 
           [0020]      FIG. 1  depicts a prior art integrated circuit comb capacitor  150 . 
           [0021]      FIGS. 2   a - 2   e  depict the formation of an integrated circuit comb capacitor  250  in accordance with a first embodiment of the invention. 
           [0022]      FIG. 3  depicts a VPP capacitor in accordance with the first embodiment of the invention. 
           [0023]      FIG. 4  depicts a modified version of the VPP capacitor in  FIG. 3 . 
           [0024]      FIGS. 5   a - 5   e  depict the formation of an integrated circuit comb capacitor  550  in accordance with a second embodiment of the invention. 
           [0025]      FIGS. 6   a - 6   e  depict the formation of an integrated circuit comb capacitor  550  in accordance with a third embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0026]    The invention will now be described with reference to the accompanying figures. In the figures, various aspects of the structures have been depicted and schematically represented in a simplified manner to more clearly describe and illustrate the invention. 
         [0027]    By way of overview and introduction, the invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have a reduced spacing between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level. All embodiments of the invention comprise formation of capacitor openings and modifying the dielectric along the surfaces of the capacitor openings such that the modification results in a capacitor with increased capacitance density. 
         [0028]    A first embodiment of the invention will be described with reference to the  FIGS. 2   a - 2   e , which depict the formation of an improved capacitor, and more specifically an improved integrated circuit comb capacitor  250 . The first embodiment is described generally as creating a modified dielectric  204  along the surfaces of the capacitor openings  220  formed in low-k dielectric  102 , removing the modified dielectric  204  along the surfaces of the capacitor openings  220 , and filling the capacitor openings  220  with a conductive material  112 . The first embodiment is described more specifically herein below with reference to  FIGS. 2   a - 2   e , individually. 
         [0029]      FIG. 2   a  depicts the formation of single damascene non-capacitor openings  210 , which are formed for non-capacitor wiring in low-k dielectric  102 . Preferably, the low-k dielectric  102  comprises one of SiCOH or porous SiCOH. While not depicted, dual damascene non-capacitor openings  210  could also be formed in the low-k dielectric  102 . Dual damascene non-capacitor openings  210  would comprise an interconnect and via portion. 
         [0030]      FIG. 2   b  depicts the formation of single damascene capacitor openings  220  in low-k dielectric  102 , while a block mask  222 , protects the non-capacitor openings  210 . As with the non-capacitor openings  210 , while a single damascene capacitor opening  220  is depicted in  FIG. 2   b , dual damascene capacitor openings  220  could also be formed in the low-k dielectric  102 . Dual damascene capacitor openings  220  would comprise an interconnect and via portion. Both the non-capacitor openings  210  and the capacitor openings  220  are formed by conventional photomask and etching steps. While  FIGS. 2   a - 2   b  depict the formation of non-capacitor openings  210  and capacitor openings  220  in two steps, the non-capacitor opening  210  and the capacitor openings  220  could be formed in the low-k dielectric  102  in one step with the same photomask. 
         [0031]      FIG. 2   c  depicts modifying the low-k dielectric  102  along the surfaces of capacitor openings  220 . More specifically, a chemically and/or physically modified dielectric  204  is created along the surfaces of the capacitor openings  220 . The modified dielectric  204  is created by depleting carbon and possibly oxidizing the remaining material from surfaces of the capacitor openings  220 . Generally, carbon is depleted with the wafer at room temperature in a reactive ion etch tool with activation of either an oxidizing plasma, such as O 2 , N 2 O, or H 2 O, or a reducing plasma, such as N 2 /H 2  or H 2 . Further modification, by oxidation of the remaining material, occurs in an oxidizing plasma. Following modification, the modified dielectric  204  results in a porous SiO 2 -like material. The low-k dielectric  102  may have a dielectric constant less than or approximately equal to 3.0, while the modified dielectric  204  has a dielectric constant greater than 4.0. Although the modified dielectric  204  has the property of a higher dielectric constant, which is advantageous from an increased capacitive density perspective, this material also poor dielectric breakdown, high electrical leakage, and high water absorption, which is disadvantageous from performance and reliability perspectives. Therefore, as depicted in  FIG. 2   d , the modified dielectric  204  is selectively removed. 
         [0032]      FIG. 2   d  depicts the selective removal of the modified dielectric  204  from the surfaces of the capacitor openings. The block mask  222  has been removed, which therefore exposes the non-capacitor openings to etch processing. The modified dielectric  204  etches more quickly in a typical solution such as a diluted hydrofluoric acid (DHF), e.g. 100:1 H 2 O:HF, than the low-k dielectric  102  etches. The disparate etch rates results in a modified capacitor opening  220  that is deepened and widened such that there are reduced spacings between neighboring capacitor openings  220  as compared with other interconnects and via contacts formed in the same metal wiring level and reduced vertical spacings between the bottom of the wiring level and any conductors within the substrate. As discussed herein above, the capacitance of the integrated circuit comb capacitor  250  increases with the modified depth and width of the capacitor electrodes  250   a , which decreases the spacing between capacitor electrodes  250   a . After the modified dielectric  204  has been removed, the integrated circuit comb capacitor  250  will be metallized, planarized and capped. The final integrated circuit comb capacitor  250  is depicted in  FIG. 2   e.    
         [0033]      FIG. 2   e  depicts the capacitor of the first embodiment of the invention, namely a capacitor with capacitor electrodes  250   a  that are deepened and widened such that there are reduced spacings between neighboring capacitor electrodes  250   a  than as compared with other interconnects  160  and via contacts formed in the same metal wiring level. A conductive material  112 , i.e. copper, fills the modified capacitor openings  220  and the non-capacitor openings  210 . Thereafter, the capacitor electrodes  250   a  and interconnects  160  are planarized and capped  242 . 
         [0034]      FIG. 3  depicts a VPP capacitor in accordance with the first embodiment of the invention depicted in  FIGS. 2   a - 2   e . As described above, a VPP capacitor is comprised of multilevel stacks of integrated circuit comb capacitors  250 . In  FIG. 3 , each integrated circuit comb capacitor  350  in the multilevel stack has been created in accordance with the first embodiment of the invention. While  FIGS. 2   a - 2   e  depict a single damascene capacitor,  FIG. 3  depicts a dual damascene capacitor. The dual damascene capacitor depicted in  FIG. 3  comprises an interconnect and via portion created in accordance with a first embodiment of the invention. Therefore, the capacitor electrodes  250   a  are deepened and widened such that there are reduced spacings between neighboring capacitor electrodes  250   a  as compared with other interconnects and via contacts formed in the same metal wiring level. While not depicted in  FIG. 3 , a VPP capacitor could also be comprised of stacks of single damascene integrated circuit comb capacitors. 
         [0035]      FIG. 4  depicts a modified version of the VPP capacitor in  FIG. 3 . The VPP capacitor of  FIG. 4  differs from the VPP capacitor of  FIG. 3  in that after removal of the modified dielectric  204  (not shown), but prior to deposition of a conductive material  112  a further step is performed. More specifically, an etch or chemical-mechanical planarization (CMP) hard mask  424  is used to create a VPP capacitor with a bulging shape  450 . The bulging shape creates a VPP capacitor with a maximum minimum spacing between neighboring capacitor electrodes  250   a  occurring towards the midpoint of the capacitor electrodes  250   a  as depicted in  FIG. 4 , as opposed to the top of the capacitor electrodes  250   a  as depicted in  FIGS. 2   e  and  3 . A maximum minimum spacing occurring towards the midpoint of the neighboring capacitor electrodes  250   a  as opposed to the top of the neighboring capacitor electrodes  250   a  could have advantages from a reliability perspective to the extent that process induced leakage paths occur at the interface with the cap  242 . 
         [0036]      FIGS. 5   a - 5   e  depict the formation of an integrated circuit comb capacitor  550  in accordance with a second embodiment of the invention. Unlike the first embodiment, in the second embodiment the modified dielectric  204  along the surfaces of the capacitor openings  220  is not removed, but instead infused with a high-k dielectric  506 . The second embodiment is described more specifically herein below with reference to  FIGS. 5   a - 5   e , individually. 
         [0037]      FIG. 5   a  depicts a low-k dielectric  102  deposited on a capping layer  242 . Beneath the capping layer  242 , capacitor electrodes  550   a  preexist. 
         [0038]      FIG. 5   b  depicts modifying the low-k dielectric. The modification creates a porous material  204 . Similar to the first embodiment of the invention, the second embodiment of the invention creates a porous material  204 , however unlike the first embodiment of the invention, in the second embodiment of the invention the porous material  204  is not limited to the surfaces of the capacitor openings  220 . 
         [0039]      FIG. 5   c  depicts the formation of non-capacitor openings  210  and capacitor openings  220  in the modified dielectric  204 . While in  FIG. 5   c , the non-capacitor openings  210  and capacitor openings  220  are formed in one step with the same photomask. The non-capacitor openings  210  and capacitor openings  220  could also be formed in two steps as was previously described herein above with reference to  FIGS. 2   a - 2   b . Dual damascene capacitor openings  220  are shown in  FIG. 5   c . Therefore, the capacitor openings  220  comprises an interconnect and a via portion. 
         [0040]      FIG. 5   d  depicts modifying the modified dielectric  204  along the surfaces of the capacitor openings  220 . Once again, the non-capacitor openings  222  are protected with a block mask  222 . As mentioned herein above, unlike the first embodiment of the invention in the second embodiment of the invention, the modified dielectric  204  is not removed, but instead infused with a high-k dielectric  506 . The high-k dielectric  506  has a higher dielectric constant than the modified dielectric  204 . 
         [0041]      FIG. 5   e  depicts filling the non-capacitor opening  210  and modified non-capacitor openings  220  with a conductive material  112 . 
         [0042]      FIGS. 6   a - 6   e  depict the formation of an integrated circuit comb capacitor  650  in accordance with a third embodiment of the invention. Similar to the second embodiment of the invention, in the third embodiment of the invention the modified dielectric  204  along the surfaces of the capacitor openings  220  is not removed but instead infused with a high-k dielectric  506 . Unlike the second embodiment of the invention, in the third embodiment of the invention the modified dielectric  204  is created after the non-capacitor openings  210  and capacitor openings  220  are filled with a conductive material  112 . The third embodiment is described more specifically herein below with reference to  FIGS. 6   a - 6   e , individually. 
         [0043]      FIG. 6   a  depicts a low-k dielectric  102  deposited on a capping layer  242 . Beneath the capping layer  242  preexists capacitor electrodes  550   a  created in accordance with the second embodiment of the invention. 
         [0044]      FIG. 6   b  depicts forming non-capacitor opening  210  and capacitor openings  220  in low-k dielectric  102 . Unlike in the second embodiment of the invention, the low-k dielectric  102  is not modified, prior to the formation of the non-capacitor opening  210  and capacitor openings  220 . 
         [0045]      FIG. 6   c  depicts modifying the dielectric  204  along the surfaces of the capacitor openings  220 . This step of the third embodiment of the invention is similar to the step depicted in  FIG. 2   c  of the first embodiment of the invention. In both the third and first embodiments of the invention, a block mask  222  protects the non-capacitor openings in the low-k dielectric  102 , while modifications are made along the surfaces of the capacitor openings  220 . The modifications create a porous material  204  along the surfaces of the capacitor openings  220 . Unlike the first embodiment, but similar to the second embodiment, the modified dielectric  204  is not removed in the third embodiment. 
         [0046]      FIG. 6   d  depicts modifying the modified dielectric  204  along the surfaces of the capacitor openings  220 . Once again, the non-capacitor openings  222  are protected with a block mask  222 . As mentioned herein above, unlike the first embodiment, the modified dielectric  204  is not removed, but similar to the second embodiment, the modified dielectric  204  is infused with a high-k dielectric  506 . The high-k dielectric  506  has a higher dielectric constant than the modified dielectric  204 . 
         [0047]      FIG. 6   e  depicts filling the non-capacitor opening  210  and modified non-capacitor openings  204  with a conductive material  112 , and removing porogen from low-k dielectric  102 . Unlike the second embodiment of the invention, in the third embodiment of the invention the porogen is removed from the low-k dielectric  102  after formation of the non-capacitor openings  210  and capacitor openings  220 . 
         [0048]    While the invention has been particularly described in conjunction with a specific preferred embodiment and other alternative embodiments, it is evident that numerous alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore intended that the appended claims embrace all such alternatives, modifications and variations as falling within the true scope and spirit of the invention.