Abstract:
A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional of U.S. application Ser. No. 12/424,123, filed on Apr. 15, 2009, which in turn is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-112206, filed on Apr. 23, 2008, the entire contents of which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    An aspect of the embodiments discussed herein is directed to a method of manufacturing the semiconductor device including a capacitive element. 
       BACKGROUND 
       [0003]    As a mobile communication medium such as a cell phone becomes sophisticated in performance and is miniaturized, high capacity and high performance level are required of an electrostatic capacity element used in a semiconductor integrated circuit for communication use. Such an electrostatic capacity element includes a lower electrode as a first conductive layer, an upper electrode as a second conductive layer, and a dielectric layer sandwiched between the lower electrode and the upper electrode. From among the elements, a metal-insulator-metal (MIM) capacitive element having metal electrodes, in particular, has a low parasitic capacitance and a low parasitic resistance and may achieve high performance. 
         [0004]    Japanese Laid-open Patent Publication No. 2005-79513 discusses a technique of a semiconductor device including an MIM capacitive element that includes a lower electrode, an upper electrode having an area larger than an area of the upper electrode, and a dielectric layer. In accordance with the disclosure, an insulating layer is deposited on a top surface and a side wall of the upper electrode to maintain insulation on the dielectric layer. 
         [0005]    Opening operations of opening via holes in the upper electrode and the lower electrode of the MIM capacitive element in the semiconductor device are performed separately. Since the opening operation needs a plurality of mask formation operations, a manufacturing process has an increased number of operations. To decrease manufacturing operations, the opening operations are preferably performed on the upper electrode and the lower electrode at the same operation. If such an opening operation is performed, the upper electrode may be overetched because of a difference in thickness of the electrodes, and the dielectric layer may be damaged. 
       SUMMARY 
       [0006]    According to an aspect of an embodiment, a method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode, forming a third insulating layer over the second insulating layer and the first layer, the third insulating layer having the etching resistance property smaller than the etching resistance property of the second insulating layer and the first layer against an etchant for etching the third insulating layer, selectively removing the third insulating layer to form a first aperture exposing the second insulating layer above the wiring layer, a second aperture exposing the first layer above the upper electrode, and a third aperture exposing the first layer above the dielectric layer, and performing an etching operation to expose the wiring layer below the first aperture, the upper electrode below the second aperture, and the lower electrode below the third aperture. 
         [0007]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0008]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0009]      FIGS. 1A-1D  are cross-sectional views each illustrating a method of manufacturing a semiconductor device  50   a  according to a first embodiment; 
           [0010]      FIGS. 2A-2D  are cross-sectional views each illustrating the method of manufacturing the semiconductor device  50   a  according to the first embodiment; 
           [0011]      FIGS. 3A-3C  are cross-sectional views each illustrating a method of manufacturing a semiconductor device  50   b  according to a second embodiment; 
           [0012]      FIGS. 4A-4D  are cross-sectional views each illustrating the method of manufacturing the semiconductor device  50   b  according to the second embodiment; 
           [0013]      FIGS. 5A-5C  are cross-sectional views each illustrating the method of manufacturing the semiconductor device  50   b  according to the second embodiment; 
           [0014]      FIG. 6  is a Weibull plot relating to dielectric breakdown of the MIM capacitive element  20   b  of the semiconductor device  50   b;    
           [0015]      FIGS. 7A-7D  are cross-sectional views each illustrating a method of manufacturing a semiconductor device  50   c  according to a third embodiment; 
           [0016]      FIGS. 8A-8D  are cross-sectional views each illustrating the method of manufacturing the semiconductor device  50   c  according to the third embodiment; 
           [0017]      FIGS. 9A-9C  are cross-sectional views each illustrating a method of manufacturing a semiconductor device  50   d  according to the fourth embodiment; 
           [0018]      FIGS. 10A-10D  are cross-sectional views each illustrating the method of manufacturing the semiconductor device  50   d  according to the fourth embodiment; and 
           [0019]      FIGS. 11A-11C  are cross-sectional views each illustrating the method of manufacturing the semiconductor device  50   d  according to the fourth embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0020]    A first embodiment, a second embodiment, a third embodiment and a fourth embodiment are described below. The present technique is not limited to these embodiments. 
         [0021]      FIGS. 1A-1D  and  FIGS. 2A-2D  illustrate in detail a structure and a manufacturing method of a semiconductor device  50   a  including a metal-insulator-metal (MIM) capacitive element  20   a  in accordance with a first embodiment. 
         [0022]    In the semiconductor device  50   a  of the first embodiment, a lower electrode  5   b  in the MIM capacitive element  20   a  may be made of a material different from a material of a wiring layer  2 . Since the lower electrode  5   b  and the wiring layer  2  are present at different depths in the semiconductor device  50   a , the wiring layer  2  may be formed right below the MIM capacitive element  20   a . A high degree of design freedom is provided in the design of the semiconductor device  50   a.    
         [0023]    Referring to  FIG. 2D , the structure of the semiconductor device  50   a  of the first embodiment is described below. 
         [0024]    The semiconductor device  50   a  includes the MIM capacitive element  20   a  above a substrate  30 . An interlayer insulator  9  is formed to cover the substrate  30  and the MIM capacitive element  20   a.    
         [0025]    The substrate  30  includes a lower interlayer insulator  1 , the wiring layer  2 , a diffusion preventing layer  3 , and a silicon dioxide (SiO 2 ) layer  4 . The lower interlayer insulator  1  is made of silicon dioxide (SiO 2 ). The wiring layer  2  is formed in the lower interlayer insulator  1 . The diffusion preventing layer  3  is formed over the lower interlayer insulator  1  and the wiring layer  2 . The silicon dioxide layer  4  is formed on the diffusion preventing layer  3 . 
         [0026]    The MIM capacitive element  20   a  includes an upper electrode  7   b , a dielectric layer  6   b , and the lower electrode  5   b . The lower electrode  5   b  and the dielectric layer  6   b  extend over the upper electrode  7   b . It is noted that a first etching stopper  8   b  is formed, covering the upper electrode  7   b  and the dielectric layer  6   b.    
         [0027]    A via hole  11   a  is opened in the interlayer insulator  9  and the first etching stopper  8   b  to establish electrical connection with the upper electrode  7   b  in the MIM capacitive element  20   a . A via hole  11   b  is opened in the interlayer insulator  9 , the first etching stopper  8   b , and the dielectric layer  6   b  to establish electrical connection with the lower electrode  5   b  in the MIM capacitive element  20   a . A via hole  11   c  is opened in the interlayer insulator  9 , the silicon dioxide layer  4 , and the diffusion preventing layer  3  to establish electrical connection with the wiring layer  2  of the substrate  30 . A via wiring  12   a  is formed by filling the via hole  11   a  with a conductor into. A via wiring  12   b  is formed by filling the via hole  11   b  with a conductor. A via wiring  12   c  is formed by filling the via hole  11   c  with a conductor. The wiring layer  2  extends below the MIM capacitive element  20   a . The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  are formed at different depths of the semiconductor device  50   a . The via wiring  12   a  and the via hole  11   a  are collectively referred to as a first contact via, the via wiring  12   b  and the via hole  11   b  are collectively referred to as a second contact via, and the via wiring  12   c  and the via hole  11   c  are collectively referred to as a third contact via. 
         [0028]    A method of manufacturing the semiconductor device  50   a  of the first embodiment is described below with reference to  FIGS. 1A-1D  and  FIGS. 2A-2D . 
         [0029]    Referring to  FIG. 1A , the diffusion preventing layer  3  made of silicon carbide (SiC) and having a thickness of, for example, about 70 nm is deposited over the wiring layer  2  in the lower interlayer insulator  1  through a sputtering process. The wiring layer  2  is made of copper, for example. The silicon dioxide layer  4  having a thickness of, for example, about 100 nm is deposited on the diffusion preventing layer  3  through a sputtering process. A first conductive layer  5   a  made of titanium nitride (TiN) and having a thickness of, for example, about 150 nm is then deposited on the silicon dioxide layer  4  through a sputtering process. A dielectric layer  6   a  made of silicon dioxide (SiO 2 ) and having a thickness of, for example, about 40 nm is deposited on the first conductive layer  5   a  through a chemical vapor deposition (CVD) process. A second dielectric layer  7   a  made of titanium nitride and having a thickness of, for example, about 100 nm is deposited on the dielectric layer  6   a  through a sputtering process. 
         [0030]    Referring to  FIG. 1B , the second conductive layer  7   a  is patterned through a lithographic process and an etching process to form the upper electrode  7   b . In this process, the first conductive layer  5   a  and the dielectric layer  6   a  extend over the upper electrode  7   b.    
         [0031]    With reference to  FIG. 1C , a first etching stopper  8   a  is formed to a thickness of 70 nm through a CVD process to cover the upper electrode  7   b  and the dielectric layer  6   a.    
         [0032]    With reference to  FIG. 1D , the first etching stopper  8   a  and the dielectric layer  6   a  are treated by a lithographic process and an etching process to form the lower electrode  5   b.    
         [0033]    With reference to  FIG. 2A , a plasma SiO 2  layer is formed to a thickness of, for example, about 650 nm as the interlayer insulator  9  using a silane gas to cover the silicon dioxide layer  4 , the lower electrode  5   b , the dielectric layer  6   b , and the first etching stopper  8   b . The interlayer insulator  9  is formed, for example, using one of silane gases (SiH 2 Cl 2 , SiH 4 , Si 2 H 4 , Si 2 H 6 , etc) through, for example, a CVD process. 
         [0034]    Referring to  FIG. 2B , a via hole  10   a , a via hole  10   b , and a via hole  10   c  are opened in the interlayer insulator  9  toward the upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2 , respectively, at the same operation through a lithographic process and an etching process. The interlayer insulator  9  and the silicon dioxide layer  4  are etched, for example, using C 4 F 6 /Ar/O 2  gases containing fluorine based C 4 F 6  gas through a reactive ion etching (RIE) process. A chamber temperature is, for example, room temperature, and the gas flow rates are, for example, 10-30 sccm for the C 4 F 6  gas, 100-300 sccm for the Ar gas, and 5-15 sccm for the O 2  gas. 
         [0035]    Gas flow rates and pressure conditions are adjusted so that the interlayer insulator  9  has an etching rate higher than that of each of the first etching stopper  8   b , the dielectric layer  6   b , and the diffusion preventing layer  3 . More specifically, gas flow rates and pressure conditions are adjusted so that each of the first etching stopper  8   b , the dielectric layer  6   b , and the diffusion preventing layer  3  has an etching rate equal to or lower than 0.1 times the etching rate of the interlayer insulator  9 , under the same etching condition as the etching condition applied to the interlayer insulator  9 . Such an adjustment prevents the upper electrode  7   b  and the lower electrode  5   b  from being overetched. 
         [0036]    Referring to  FIG. 2C , the first etching stopper  8   b , the dielectric layer  6   b , and the diffusion preventing layer  3  respectively present at the bottoms of the via hole  10   a , the via hole  10   b , and the via hole  10   c  are removed. These layers are etched using, for example, CH 2 F 2 /N 2 /O 2  gases containing a fluorine based CH 2 F 2  gas through the RIE process. In this etching process, the chamber temperature is room temperature, and gas flow rates are, for example, 10-35 sccm for the CH 2 F 2  gas, 50-100 sccm for the N 2  gas, and 15-40 sccm for the O 2  gas. The via hole  11   a , the via hole  11   b , and the via hole  11   c  are thus opened. 
         [0037]    Referring to  FIG. 2D , tungsten (W) fills the via hole  11   a , the via hole  11   b , and the via hole  11   c  through a CVD process to form the via wiring  12   a , the via wiring  12   b , and the via wiring  12   c . A barrier metal formation operation is not illustrated. The semiconductor device  50   a  including the MIM capacitive element  20   a  is thus produced. 
         [0038]    With the semiconductor device  50   a  including the MIM capacitive element  20   a  manufactured as described above, the lower electrode  5   b  is made of a material different from a material of the wiring layer  2 . The via holes are opened to the upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  at the same process operation. Since the first etching stopper  8   b  covers the entire the MIM capacitive element, each electrode may be protected from overetching and free from contact failure. Since the lower electrode  5   b  and the wiring layer  2  are deposited at different depths, a wiring may be formed right below the MIM capacitive element  20   a . The design freedom of the semiconductor device  50   a  may be increased. 
         [0039]    A second embodiment is described below with reference to  FIGS. 3A-3C  through  FIGS. 5A-5C .  FIGS. 3A-3C  through  FIGS. 5A-5C  illustrate in detail a structure of a semiconductor device  50   b  having an MIM capacitive element  20   b  in accordance with the second embodiment. Elements identical to those described in connection with the first embodiment are designated with the same reference numerals and the discussions thereof are omitted here. 
         [0040]    The semiconductor device  50   b  of the second embodiment includes a first etching stopper  8   d  and the dielectric layer  6   b , both made of silicon nitride (SiN). With this structure, a groove defect generated in a dielectric layer  6   c  present beneath the upper electrode  7   b  in the course of a patterning process of the upper electrode  7   b  is filled with the first etching stopper  8   d  that is made of the same material as the dielectric layer  6   c . More specifically, the defect of the dielectric layer  6   c  is corrected. This arrangement may control a reduction in withstanding voltage of the MIM capacitive element  20   b  and lot-to-lot manufacturing variations in a capacitance of the MIM capacitive element  20   b.    
         [0041]    A structure of the semiconductor device  50   b  of the second embodiment is described below with reference to  FIG. 5C . 
         [0042]    The semiconductor device  50   b  includes the MIM capacitive element  20   b  on the substrate  30 . The interlayer insulator  9  is formed, covering the substrate  30  and the MIM capacitive element  20   b.    
         [0043]    The MIM capacitive element  20   b  includes the upper electrode  7   b , a dielectric layer  6   d , and the lower electrode  5   b . The lower electrode  5   b  and the dielectric layer  6   d  extend over the upper electrode  7   b . The first etching stopper  8   d  is formed, covering the upper electrode  7   b  and the dielectric layer  6   d.    
         [0044]    The via hole  11   a  is opened in the interlayer insulator  9  and the first etching stopper  8   d  to establish electrical connection with the upper electrode  7   b  of the MIM capacitive element  20   b . The via hole  11   b  is opened in the interlayer insulator  9 , the first etching stopper  8   d , and the dielectric layer  6   d  to establish electrical connection with the lower electrode  5   b  of the MIM capacitive element  20   b . The via hole  11   c  is opened in the interlayer insulator  9 , the silicon dioxide layer  4 , and the diffusion preventing layer  3  to establish electrical connection with the wiring layer  2  of the substrate  30 . The via wiring  12   a  is formed by filling the via hole  11   a  with a conductor. The via wiring  12   b  is formed by filling the via hole  11   b  with a conductor. The via wiring  12   c  is formed by filling the via hole  11   c  with a conductor. The wiring layer  2  extends below the MIM capacitive element  20   b . The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  are formed at different depths of the semiconductor device  50   b . The via wiring  12   a  and the via hole  11   a , the via wiring  12   b  and the via hole  11   b , and the via wiring  12   c  and the via hole  11   c  are respectively collectively referred to as a contact via. 
         [0045]    A method of manufacturing the semiconductor device  50   b  of the second embodiment is described below with reference to  FIGS. 3A-3C  through  FIGS. 5A-5C . 
         [0046]    Referring to  FIG. 3A , the diffusion preventing layer  3  is deposited over the wiring layer  2  in the lower interlayer insulator  1  in the same manner as previously described with reference to  FIG. 1A . The silicon dioxide layer  4  is deposited on the diffusion preventing layer  3  in the same manner as previously described with reference to  FIG. 1A . The first conductive layer  5   a  is then deposited on the silicon dioxide layer  4  in the same manner as previously described with reference to  FIG. 1A . The dielectric layer  6   c  made of silicon nitride (SiN) and having a thickness of, for example, about 40 nm is deposited on the first conductive layer  5   a  through a CVD process. The second conductive layer  7   a  made of titanium nitride and having a thickness of, for example, about 100 nm is deposited on the dielectric layer  6   c  through a sputtering process, for example. 
         [0047]    Referring to  FIG. 3B , the second conductive layer  7   a  is patterned through a lithographic process and an etching process to form the upper electrode  7   b . In this process, the first conductive layer  5   a  and the dielectric layer  6   a  are formed to extend over the upper electrode  7   b.    
         [0048]      FIG. 3C  is an expanded view of a contact portion denoted by the letter A between the underside of the upper electrode  7   b  and the dielectric layer  6   c  in  FIG. 3B .  FIG. 3C  illustrates a groove defect that is generated in a dielectric layer  6   c  present beneath the upper electrode  7   b  in the course of the patterning process of the second conductive layer  7   a . Such a groove defect may cause a reduction in the withstanding voltage of the MIM capacitive element  20   b  and lot-to-lot variations in the capacitance of the MIM capacitive element  20   b.    
         [0049]    With reference to  FIG. 4A , a first etching stopper  8   c  is formed to a thickness of, for example, about 70 nm through a CVD process to cover the upper electrode  7   b  and the dielectric layer  6   c .  FIG. 4B  is an expanded view of a contact portion denoted by the letter A between the underside of the upper electrode  7   b  and the dielectric layer  6   c  in  FIG. 4A . As illustrated in  FIG. 4B , the first etching stopper  8   c  made of the same material of the dielectric layer  6   c  may fill a groove defect that has been generated in the dielectric layer  6   c  present beneath the upper electrode  7   b  in the course of the patterning process of the upper electrode  7   b . The defect of the dielectric layer  6   c  is thus corrected. This arrangement may control a reduction in the withstanding voltage of the MIM capacitive element  20   b  and lot-to-lot variations in the capacitance of the MIM capacitive element  20   b.    
         [0050]    With reference to  FIG. 4C , the first etching stopper  8   d , the dielectric layer  6   c , and the first conductive layer  5   a  are treated by a lithographic process and an etching process. Through this process, the first etching stopper  8   d , the dielectric layer  6   d , and the lower electrode  5   b  are formed. The MIM capacitive element  20   b , including the upper electrode  7   b , the dielectric layer  6   d , and the lower electrode  5   b , is thus formed. 
         [0051]    With reference to  FIG. 4D , a SiO 2  layer is formed to a thickness of, for example, about 650 nm as the interlayer insulator  9  using a silane gas to cover the silicon dioxide layer  4 , the lower electrode  5   b , the dielectric layer  6   d , and the first etching stopper  8   d  in the same manner as described with reference to  FIG. 2A . 
         [0052]    Referring to  FIG. 5A , a via hole  10   a , a via hole  10   b , and a via hole  10   c  are opened in the interlayer insulator  9  and the silicon dioxide layer  4  toward the upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2 , respectively, at the same operation through a lithographic process and an etching process. The interlayer insulator  9  and the silicon dioxide layer  4  are etched, for example, using C 4 F 6 /Ar/O 2  gases containing a fluorine based C 4 F 6  gas through an RIE process. A chamber temperature is, for example, room temperature, and the gas flow rates are, for example, 10-30 sccm for the C 4 F 6  gas, 100-300 sccm for the Ar gas, and 5-15 sccm for the O 2  gas. 
         [0053]    Gas flow rates and pressure conditions are adjusted so that the interlayer insulator  9  has an etching rate higher than that of each of the first etching stopper  8   d , the dielectric layer  6   d , and the diffusion preventing layer  3 . More specifically, gas flow rates and pressure conditions are adjusted so that each of the first etching stopper  8   d , the dielectric layer  6   d , and the diffusion preventing layer  3  may have an etching rate equal to or lower than 0.1 times the etching rate of the interlayer insulator  9 , under the same etching condition as the etching condition applied to the interlayer insulator  9 . Such an etching condition may prevent the upper electrode  7   b  and the lower electrode  5   b  from being overetched. 
         [0054]    Referring to  FIG. 5B , the first etching stopper  8   d , the dielectric layer  6   d , and the diffusion preventing layer  3  respectively present at the bottoms of the via hole  10   a , the via hole  10   b , and the via hole  10   c  are removed. These layers are etched using, for example, CH 2 F 2 /N 2 /O 2  gases containing a fluorine based CH 2 F 2  gas through the RIE process. In this etching process, the chamber temperature is, for example, room temperature, and gas flow rates are, for example, 10-35 sccm for the CH 2 F 2  gas, 50-100 sccm for the N 2  gas, and 15-40 sccm for the O 2  gas. The via hole  11   a , the via hole  11   b , and the via hole  11   c  are thus produced. 
         [0055]    Referring to  FIG. 5C , for example, tungsten (W) placed to fill the via hole  11   a , the via hole  11   b , and the via hole  11   c  through a CVD process to form the via wiring  12   a , the via wiring  12   b , and the via wiring  12   c  in the same manner as previously described with reference to  FIG. 2D . A barrier metal formation operation is not illustrated. The semiconductor device  50   b  including the MIM capacitive element  20   b  is thus produced. 
         [0056]      FIG. 6  illustrates a Weibull plot relating to dielectric breakdown of the MIM capacitive element  20   b  of the semiconductor device  50   b . The Weibull plot of  FIG. 6  illustrates a distribution of cumulative probability of the dielectric breakdown of the MIM capacitive element  20   b  of the semiconductor device  50   b . In  FIG. 6 , the ordinate represents the cumulative probability of the dielectric breakdown of the dielectric layer  6   d  in the MIM capacitive element  20   b , and the abscissa represents time (h) to the dielectric breakdown of the dielectric layer  6   d  in the MIM capacitive element  20   b . The data plot denoted by a broken line represents the distribution of the cumulative probability of dielectric breakdowns and time to the dielectric breakdowns of the MIM capacitive element with a voltage as high as 20 V applied between the upper electrode and the lower electrode in the semiconductor device. In this case, the semiconductor device has no first etching stopper formed on the side wall of the upper electrode. The data plot denoted by a solid line represents the distribution of the cumulative probability of dielectric breakdown and time to the dielectric breakdown of the MIM capacitive element  20   b  with a voltage as high as 20 V applied between the upper electrode  7   b  and the lower electrode  5   b  in the semiconductor device  50   b . In this case, the semiconductor device  50   b  has the first etching stopper  8   d  formed on the side wall of the upper electrode  7   b.    
         [0057]    Referring to  FIG. 6 , the rate of dielectric breakdown increases with time in the semiconductor device having the MIM capacitive element with no first etching stopper formed on the side wall of the upper electrode. In accordance with the second embodiment, the semiconductor device  50   b  having the MIM capacitive element  20   b  with the first etching stopper  8   d  formed on the side wall of the upper electrode  7   b  provides the data plot indicating the cumulative probability of block diagram generally shifted to longer life side. The gradient of the data plot sharply increases at 0.5×10 −2  (h) and later. The first etching stopper  8   d  formed on the side wall of the upper electrode  7   b  may thus control a reduction in the withstanding voltage of the MIM capacitive element  20   b  and lot-to-lot manufacturing variations in the capacitance of the MIM capacitive element  20   b.    
         [0058]    The first etching stopper  8   d  and the dielectric layer  6   d  are made of silicon nitride (SiN) in the semiconductor device  50   b  having the MIM capacitive element  20   b  in accordance with the second embodiment. With this structure, the groove defect generated in the dielectric layer  6   c  present beneath the upper electrode  7   b  in the course of the patterning process of the upper electrode  7   b  is filled with the first etching stopper  8   d  that is made of the same material as the dielectric layer  6   c . More specifically, the defect of the dielectric layer  6   c  may be corrected. This arrangement may control a reduction in the withstanding voltage of the MIM capacitive element  20   b  and lot-to-lot manufacturing variations in the capacitance of the MIM capacitive element  20   b.    
         [0059]    A third embodiment is described below with reference to  FIGS. 7A-7D  and  FIG. 8A-8D .  FIGS. 7A-7D  and  FIG. 8A-8D  illustrate in detail a structure of a semiconductor device  50   c  having an MIM capacitive element  20   c  in accordance with the third embodiment. In the discussion of the third embodiment, elements identical to those described in connection with the first and second embodiments are designated with the same reference numerals and the discussion thereof are omitted here. 
         [0060]    The semiconductor device  50   c  of the third embodiment includes a second etching stopper  13   b  and the dielectric layer  6   b . With this structure, the second etching stopper  13   b  formed on the upper electrode  7   b , a first etching stopper  8   f  formed on the lower electrode  5   b , and the diffusion preventing layer  3  formed on the wiring layer  2  are removed at the same operation of removing each etching stopper remaining at the bottom of each via. The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  may thus be prevented from being overetched. A good contact may thus be established when each of the via hole  11   a , the via hole  11   b , and the via hole  11   c  is filled with the metal. The wiring layer  2  is arranged below the MIM capacitive element  20   c . The upper electrode  7   b , the lower electrode  5   b  and the wiring layer  2  are formed at different depths. 
         [0061]    A structure of the semiconductor device  50   c  of the third embodiment is described below with reference to  FIG. 8D . 
         [0062]    The semiconductor device  50   c  includes the MIM capacitive element  20   c  on the substrate  30 . The interlayer insulator  9  is formed, covering the substrate  30  and the MIM capacitive element  20   c.    
         [0063]    The MIM capacitive element  20   c  includes the upper electrode  7   b , the dielectric layer  6   b , and the lower electrode  5   b . The lower electrode  5   b  and the dielectric layer  6   b  are formed to extend over the upper electrode  7   b . The first etching stopper  8   f  is formed, covering the upper electrode  7   b  and the dielectric layer  6   b . The second etching stopper  13   b  is formed on the upper electrode  7   b.    
         [0064]    The via hole  11   a  is opened in the interlayer insulator  9  and the first etching stopper  8   f  to establish electrical connection with the upper electrode  7   b  of the MIM capacitive element  20   c . The via hole  11   b  is opened in the interlayer insulator  9 , the first etching stopper  8   f , and the dielectric layer  6   b  to establish electrical connection with the lower electrode  5   b  of the MIM capacitive element  20   c . The via hole  11   c  is opened in the interlayer insulator  9 , the silicon dioxide layer  4 , and the diffusion preventing layer  3  to establish electrical connection with the wiring layer  2  of the substrate  30 . The via wiring  12   a  is formed by filling the via hole  11   a  with a conductor. The via wiring  12   b  is formed by filling the via hole  11   b  with a conductor. The via wiring  12   c  is formed by filling the via hole  11   c  with a conductor. The wiring layer  2  extends below the MIM capacitive element  20   b . The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  are formed at different depths in the semiconductor device  50   c . The via wiring  12   a  and the via hole  11   a , the via wiring  12   b  and the via hole  11   b , and the via wiring  12   c  and the via hole  11   c  are respectively collectively referred to as a contact via. 
         [0065]    A method of manufacturing the semiconductor device  50   c  of the third embodiment is described below with reference to  FIGS. 7A-7D  and  FIGS. 8A-8D . 
         [0066]    Referring to  FIG. 7A , the diffusion preventing layer  3 , the silicon dioxide layer  4 , the first conductive layer  5   a , the dielectric layer  6   a , the second conductive layer  7   a , and a second etching stopper  13   a  are laminated in that order over the wiring layer  2  in the lower interlayer insulator  1 . The diffusion preventing layer  3  is made of silicon carbide and has a thickness of, for example, about 70 nm. The silicon dioxide layer  4  has a thickness of, for example, about 100 nm. The first conductive layer  5   a  is made of titanium nitride and has a thickness of, for example, about 150 nm. The dielectric layer  6   a  is made of silicon nitride and has a thickness of, for example, about 40 nm. The second conductive layer  7   a  is made of titanium nitride and has a thickness of, for example, about 100 nm. The second etching stopper  13   a  is made of silicon carbide and has a thickness of, for example, about 31 nm. 
         [0067]    Referring to  FIG. 7B , the second etching stopper  13   a  and the second conductive layer  7   a  are patterned through a lithographic process and an etching process to form the second etching stopper  13   b  and the upper electrode  7   b . In this process, the first conductive layer  5   a  and the dielectric layer  6   a  are formed to extend over the second etching stopper  13   b  and the upper electrode  7   b.    
         [0068]    Referring to  FIG. 7C , a first etching stopper  8   e  made of silicon carbide is deposited to a thickness of, for example, about 47 nm through a CVD process, thereby covering the second etching stopper  13   b , the upper electrode  7   b  and the dielectric layer  6   a.    
         [0069]    With reference to  FIG. 7D , the first etching stopper  8   e , the second etching stopper  13   b , the dielectric layer  6   a , and the first conductive layer  5   a  are treated by a lithographic process and an etching process. Through this process, the first etching stopper  8   f , the second etching stopper  13   b , the dielectric layer  6   b , and the lower electrode  5   b  are formed. The MIM capacitive element  20   c , including the upper electrode  7   b , the dielectric layer  6   b , and the lower electrode  5   b , is thus formed. 
         [0070]    With reference to  FIG. 8A , a SiO 2  layer is formed to a thickness of, for example, about 650 nm as the interlayer insulator  9  using a silane gas to cover the silicon dioxide layer  4 , the lower electrode  5   b , the dielectric layer  6   b , and the first etching stopper  8   f.    
         [0071]    Referring to  FIG. 8B , the via hole  10   a , the via hole  10   b , and the via hole  10   c  are opened in the interlayer insulator  9  and the silicon dioxide layer  4  respectively toward the upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  at the same operation through a lithography process and an etching process in the same manner as described with reference to  FIG. 2B . The interlayer insulator  9  and the silicon dioxide layer  4  are etched using, for example, a mixture of a C 4 F 6  gas, an Ar gas and an O 2  gas in the opening operation of the via hole  10   a , the via hole  10   b , and the via hole  10   c.    
         [0072]    Gas flow rates and pressure conditions are adjusted so that the interlayer insulator  9  has an etching rate higher than that of each of the first etching stopper  8   f , the dielectric layer  6   b , and the diffusion preventing layer  3 . More specifically, gas flow rates and pressure conditions are adjusted so that each of the first etching stopper  8   f , the dielectric layer  6   b , and the diffusion preventing layer  3  may have an etching rate equal to or lower than 0.1 times the etching rate of the interlayer insulator  9 , under the same etching condition as the etching condition applied to the interlayer insulator  9 . Such an adjustment prevents the upper electrode  7   b  and the lower electrode  5   b  from being overetched. 
         [0073]    In the etching process, the etching rate of the silicon dioxide layer may be preferably about 65 times the etching rate of the silicon carbide layer. Subsequent to the opening of via holes, the first etching stopper  8   f  remaining in each of the via hole  10   a , the via hole  10   b , and the via hole  10   c  is about 70 nm thick on the upper electrode  7   b  and about 25 nm thick on the lower electrode  5   b . In addition to the first etching stopper  8   f , the dielectric layer  6   b  made of silicon nitride and having a thickness of about 40 nm is present on the lower electrode  5   b.    
         [0074]    Referring to  FIG. 8C , the first etching stopper  8   f , the dielectric layer  6   b , and the diffusion preventing layer  3  respectively present at the bottoms of the via hole  10   a , the via hole  10   b , and the via hole  10   c  are removed. These layers are etched using, for example, CH 2 F 2 /N 2 /O 2  gases containing a fluorine based CH 2 F 2  gas through the RIE process. In this etching process, the chamber temperature is, for example, room temperature, and gas flow rates are, for example, 10-35 sccm for the CH 2 F 2  gas, 50-100 sccm for the N 2  gas, and 15-40 sccm for the O 2  gas. The via hole  11   a , the via hole  11   b , and the via hole  11   c  are thus opened. 
         [0075]    If the silicon carbide layer and the silicon nitride layer are etched at the same operation using a mixture of the CH 2 F 2  gas, the O 2  gas, and the N 2  gas, the etching rate of the silicon carbide may become about 1.13 times the etching rate of the silicon nitride. The amounts of etch under the etching condition are 40 nm for the silicon nitride layer and 45 nm for the silicon carbide layer. The first etching stopper  8   f  and the second etching stopper  13   b  on the upper electrode  7   b , the first etching stopper  8   f  and the dielectric layer  6   b  on the lower electrode  5   b , and the diffusion preventing layer  3  on the wiring layer  2  are removed at the same operation of removing each etching stopper remaining at the bottom of each via. The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  are prevented from being overetched. A good contact is established when each via is filled with the metal. 
         [0076]    Referring to  FIG. 8D , for example, tungsten (W) is placed to fill the via hole  11   a , the via hole  11   b , and the via hole  11   c  through a CVD process to form the via wiring  12   a , the via wiring  12   b , and the via wiring  12   c . A barrier metal formation operation is not illustrated. The semiconductor device  50   c  including the MIM capacitive element  20   c  is thus produced. 
         [0077]    The second etching stopper  13   b  is formed on the upper electrode  7   b  in the semiconductor device  50   c  of the third embodiment. With this structure, the second etching stopper  13   b  formed on the upper electrode  7   b , the first etching stopper  8   f  formed on the lower electrode  5   b , and the diffusion preventing layer  3  formed on the wiring layer  2  are removed in the removal process of the etching stopper remaining in each of the via hole  10   a , the via hole  10   b , and the via hole  10   c . The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  may be prevented from being overetched. A good contact may be established in the filling of the via hole  11   a , the via hole  11   b , and the via hole  11   c  with the metal. 
         [0078]    A fourth embodiment is described below with reference to  FIGS. 9A-9C  through  FIGS. 11A-11C .  FIGS. 9A-9C  through  FIGS. 11A-11C  illustrates in detail a structure and a manufacturing method of a semiconductor device  50   d  having an MIM capacitive element  20   d  in accordance with the fourth embodiment. Elements identical to those described in connection with the first through third embodiments are designated with the same reference numerals and the discussions thereof are omitted here. 
         [0079]    As the semiconductor device  50   b  of the second embodiment, the semiconductor device  50   d  of the fourth embodiment includes the first etching stopper  8   h  and the dielectric layer  6   d , both made of silicon nitride (SiN). With this structure, a groove defect generated in a dielectric layer  6   d  present beneath the upper electrode  7   b  in the course of a patterning process of the upper electrode  7   b  is filled with the first etching stopper  8   h  that is made of the same material as the dielectric layer  6   d . More specifically, the defect of the dielectric layer  6   d  is corrected. This arrangement thus controls a reduction in withstanding voltage of the MIM capacitive element  20   d  and lot-to-lot manufacturing variations in the capacitance of the MIM capacitive element  20   d.    
         [0080]    A structure of the semiconductor device  50   d  of the fourth embodiment is described below with reference to  FIG. 11C . 
         [0081]    The semiconductor device  50   d  includes the MIM capacitive element  20   d  on the substrate  30 . The interlayer insulator  9  is formed, covering the substrate  30  and the MIM capacitive element  20   d.    
         [0082]    The MIM capacitive element  20   d  includes the upper electrode  7   b , the dielectric layer  6   c , and the lower electrode  5   b . The lower electrode  5   b  and the dielectric layer  6   d  are formed to extend over the upper electrode  7   b . The first etching stopper  8   h  is formed, covering the upper electrode  7   b  and the dielectric layer  6   d . The second etching stopper  13   b  is formed on the upper electrode  7   b.    
         [0083]    The via hole  11   a  is opened in the interlayer insulator  9  and the first etching stopper  8   h  to establish electrical connection with the upper electrode  7   b  of the MIM capacitive element  20   d . The via hole  11   b  is opened in the interlayer insulator  9 , the first etching stopper  8   h , and the dielectric layer  6   b  to establish electrical connection with the lower electrode  5   b  of the MIM capacitive element  20   d . The via hole  11   c  is opened in the interlayer insulator  9 , the silicon dioxide layer  4 , and the diffusion preventing layer  3  to establish electrical connection with the wiring layer  2  of the substrate  30 . The via wiring  12   a  is formed by filling the via hole  11   a  with a conductor. The via wiring  12   b  is formed by filling the via hole  11   b  with a conductor. The via wiring  12   c  is formed by filling the via hole  11   c  with a conductor. The wiring layer  2  extends below the MIM capacitive element  20   d . The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  are formed at different depths of the semiconductor device  50   d . The via wiring  12   a  and the via hole  11   a , the via wiring  12   b  and the via hole  11   b , and the via wiring  12   c  and the via hole  11   c  are respectively collectively referred to as a contact via. 
         [0084]    A method of manufacturing the semiconductor device  50   d  of the fourth embodiment is described below with reference to  FIGS. 9A-9C  through  FIGS. 11A-11C . 
         [0085]    Referring to  FIG. 9A , the diffusion preventing layer  3 , the silicon dioxide layer  4 , the first conductive layer  5   a , the dielectric layer  6   c , the second conductive layer  7   a , and a second etching stopper  13   a  are laminated in that order over the wiring layer  2  in the lower interlayer insulator  1 . The diffusion preventing layer  3  is made of silicon carbide and has a thickness of, for example, about 70 nm. The silicon dioxide layer  4  has a thickness of, for example, about 100 nm. The first conductive layer  5   a  is made of titanium nitride (TiN) and has a thickness of, for example, about 150 nm. The dielectric layer  6   c  is made of silicon nitride and has a thickness of, for example, about 40 nm. The second conductive layer  7   a  is made of titanium nitride and has a thickness of, for example, about 100 nm. The second etching stopper  13   a  is made of silicon nitride and has a thickness of, for example, about 48 nm. The dielectric layer  6   c  and the second etching stopper  13   a  are made of the same material, namely, silicon nitride. 
         [0086]    Referring to  FIG. 9B , the second conductive layer  7   a  and the second etching stopper  13   a  are patterned through a lithographic process and an etching process to form the upper electrode  7   b  and the second etching stopper  13   b . In this process, the first conductive layer  5   a  and the dielectric layer  6   c  are formed to extend over the second etching stopper  13   b  and the upper electrode  7   b.    
         [0087]      FIG. 9C  is an expanded view of a contact portion denoted by the letter B between the underside of the upper electrode  7   b  and the dielectric layer  6   c  in  FIG. 9B .  FIG. 9C  illustrates a groove defect that is generated in the dielectric layer  6   c  present beneath the upper electrode  7   b  in the course of the patterning process of the second conductive layer  7   a . Such a groove defect causes a reduction in the withstanding voltage of the MIM capacitive element  20   d  and lot-to-lot variations in the capacitance of the MIM capacitive element  20   d.    
         [0088]    With reference to  FIG. 10A , a first etching stopper  8   g  made of silicon nitride is formed to a thickness of, for example, about 43 nm to cover the upper electrode  7   b  and the dielectric layer  6   c  through a CVD process.  FIG. 10B  is an expanded view of a contact portion denoted by the letter B between the underside of the upper electrode  7   b  and the dielectric layer  6   c  in  FIG. 10A . As illustrated in  FIG. 10B , the first etching stopper  8   g  made of the same material of the dielectric layer  6   c  may fill a groove defect that has been generated in the dielectric layer  6   c  generated beneath the upper electrode  7   b  in the course of the patterning process of the upper electrode  7   b . The defect of the dielectric layer  6   c  is thus corrected. This arrangement controls a reduction in the withstanding voltage of the MIM capacitive element  20   d  and lot-to-lot variations in the capacitance of the MIM capacitive element  20   d.    
         [0089]    With reference to  FIG. 10C , the first etching stopper  8   g , the dielectric layer  6   c , and the first conductive layer  5   a  are treated by a lithographic process and an etching process. Through this process, the first etching stopper  8   h , the dielectric layer  6   d , and the lower electrode  5   b  are formed. The MIM capacitive element  20   d , including the upper electrode  7   b , the dielectric layer  6   d , and the lower electrode  5   b , thus results. 
         [0090]    With reference to  FIG. 10D , a plasma SiO 2  layer is formed to a thickness of, for example, about 650 nm as the interlayer insulator  9  using a silane gas to cover the silicon dioxide layer  4 , the lower electrode  5   b , the dielectric layer  6   d , and the first etching stopper  8   h.    
         [0091]    Referring to  FIG. 11A , the via hole  10   a , the via hole  10   b , and the via hole  10   c  are opened in the interlayer insulator  9  and the silicon dioxide layer  4  toward the upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2 , respectively, at the same operation through a lithographic process and an etching process in the same manner as described with reference to  FIG. 8B . The interlayer insulator  9  and the silicon dioxide layer  4  are etched using, for example, a mixture of a C 4 F 6  gas, an Ar gas and an O 2  gas in the opening operation of the via hole  10   a , the via hole  10   b , and the via hole  10   c.    
         [0092]    Gas flow rates and pressure conditions adjusted so that the interlayer insulator  9  has an etching rate higher than that of each of the first etching stopper  8   b , the second etching stopper  13   b , the dielectric layer  6   d , and the diffusion preventing layer  3 . More specifically, gas flow rates and pressure conditions are adjusted so that each of the second etching stopper  13   b , the first etching stopper  8   b , the dielectric layer  6   d , and the diffusion preventing layer  3  may have an etching rate equal to or lower than 0.1 times the etching rate of the interlayer insulator  9 , under the same etching condition as the etching condition applied to the interlayer insulator  9 . Such an adjustment prevents the upper electrode  7   b  and the lower electrode  5   b  from being overetched. 
         [0093]    In the etching process, the etching rate of the silicon dioxide layer may be preferably about 19 times the etching rate of the silicon carbide layer. Subsequent to the etching process, a silicon nitride layer having a thickness of, for example, about 62 nm is present on the upper electrode  7   b  and the lower electrode  5   b  at each via bottom. 
         [0094]    Referring to  FIG. 11B , the first etching stopper  8   h , the second etching stopper  13   b , the dielectric layer  6   d , and the diffusion preventing layer  3  respectively present at the bottoms of the via hole  10   a , the via hole  10   b , and the via hole  10   c  are removed. These layers are etched using, for example, CH 2 F 2 /N 2 /O 2  gases containing a fluorine based CH 2 F 2  gas through the RIE process. In this etching process, the chamber temperature is, for example, room temperature, and gas flow rates are, for example, 10-35 sccm for the CH 2 F 2  gas, 50-100 sccm for the N 2  gas, and 15-40 sccm for the O 2  gas. The via hole  11   a , the via hole  11   b , and the via hole  11   c  are thus opened. 
         [0095]    If the silicon carbide layer and the silicon nitride layer are etched at the same operation using, for example, a mixture of the CH 2 F 2  gas, the O 2  gas, and the N 2  gas, the etching rate of the silicon carbide may become about 1.13 times the etching rate of the silicon nitride. The etching stopper remaining on the upper electrode  7   b  and the etching stopper remaining on the lower electrode  5   b  at the via hole are silicon carbide layers having a thickness of, for example, about 70 nm under this condition. The first etching stopper  8   h  and the second etching stopper  13   b  on the upper electrode  7   b , the first etching stopper  8   h  and the dielectric layer  6   d  on the lower electrode  5   b , and the diffusion preventing layer  3  on the wiring layer  2  are removed at the same operation as the operation of removing each etching stopper remaining at the bottom of each via hole. The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  may be prevented from being overetched. A good contact is established when each via hole is filled with the metal. 
         [0096]    Referring to  FIG. 11C , for example, tungsten (W) is placed to fill the via hole  11   a , the via hole  11   b , and the via hole  11   c  through a CVD process to form the via wiring  12   a , the via wiring  12   b , and the via wiring  12   c  in the same manner as previously described with reference to  FIG. 2D . A barrier metal formation operation is not illustrated. The semiconductor device  50   d  including the MIM capacitive element  20   d  is thus produced. 
         [0097]    In accordance with the semiconductor device  50   d  of the fourth embodiment, the second etching stopper  13   b  is formed on the upper electrode  7   b . With this structure, the second etching stopper  13   b  formed on the upper electrode  7   b , the first etching stopper  8   h  formed on the lower electrode  5   b , and the diffusion preventing layer  3  formed on the wiring layer  2  are removed at the same operation as the operation of removing the etching stopper remaining at the bottom of each via hole. The upper electrode  7   b , the lower electrode  5   b , and the wiring layer  2  may be prevented from being overetched. A good contact may thus be established when each via hole is filled with the metal. 
         [0098]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the embodiment and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a illustrating of the superiority and inferiority of the embodiment. Although the embodiments have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.