Abstract:
A circuit to power multiple load elements is presented. Fewer discrete components and fewer output terminals are required to power multiple devices. A single high-power DC boost circuit powers multiple AC devices. An end-user can selectively power a subset of the AC devices electrically connected to the present invention. The circuit includes a first and second reference voltage terminal, and a first, second, and third switch. The circuit also includes a first control switch and a second control switch in electrical communication with the first switch and the second switch, respectively. The first control switch provides either a first control signal or a second control signal to a control terminal of the first switch. Similarly, the second control switch provides either the first control signal or the second control signal to a control terminal of the third switch.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to circuits that power load devices, and in particular to circuits that supply load devices with AC voltages derived from DC sources. 
     BACKGROUND OF THE INVENTION 
     There are two types of electrical power. Direct current (DC) electrical power is characterized by its constant voltage and current. This is the type of power delivered, for example, by electrical storage cells, chemical batteries, and photovoltaic devices. Although typically used to power electrical devices, resistive losses proportionate to the square of its amperage render it undesirable for long-range power transmission. 
     Alternating current (AC) electrical power is typically characterized by time-varying voltage and current values whose time-average values are typically zero. Typically, its resistive losses are much smaller than those incurred through the transmission of DC power and therefore it is the power of choice for long-range power transmission. However, its varying voltage and current renders it unsuitable to power devices designed around logic levels that correspond to constant voltage levels. Therefore, most digital logic circuits are designed and operate on DC power. 
     However, certain circuit components, like electroluminescent panels and electrical motors, require AC power to operate due to design or device characteristics. Therefore, circuit designers are often faced with the problem of converting a supplied DC voltage to an AC voltage to power these devices. Additionally, certain equipment can have multiple loads which require separate control. For example, some cellular phones and personal digital assistants include multiple electroluminescent components and/or piezoelectric transducers which require separate power control. It is desirable to use a single DC power supply with minimal circuit components to individually control power to the loads of such devices. 
     SUMMARY OF THE INVENTION 
     The present invention relates to a circuit and method for powering AC devices using DC voltage sources. The present invention provides an improved circuit that requires fewer discrete components to power multiple devices. The circuit enables a user to selectively power a subset of the AC devices electrically connected to the present invention. The present invention also enables a user to switch the direction of the current flow through multiple load devices while reducing the number of components. 
     In one aspect, the invention relates to a circuit for driving multiple load elements. The circuit includes a first reference voltage terminal and a second reference voltage terminal. The circuit also includes a first, second, and third switch, each having an output terminal. The circuit also includes a first control switch in electrical communication with the first switch. The first control switch provides either a first control signal or a second control signal to a control terminal of the first switch. The circuit further includes a second control switch in electrical communication with the third switch. The second control switch provides either the first control signal or the second control signal to a control terminal of the third switch. The output terminal of the first switch is coupled to the first reference voltage terminal when the first control signal is in a first state. The output terminal of the first switch is coupled to the second reference voltage terminal when the first control signal is in a second state. Similarly, the output terminal of the third switch is coupled to the first reference voltage terminal when the second control signal is in a first state. The output terminal of the third switch is coupled to the second reference voltage terminal when the second control signal is in a second state. 
     In one embodiment, the first control switch has a selection terminal. A first selection signal applied to the selection terminal of the first control switch determines whether the first control switch provides the first control signal or the second control signal to the control terminal of the first switch. In a further embodiment, the second control switch also has a selection terminal. A second selection signal applied to the selection terminal of the second control switch determines whether the second control switch provides the first control signal or the second control signal to the control terminal of the third switch. 
     In another aspect, the invention relates to a method for powering multiple load elements. The method includes the step of providing a first load and a second load, each having a first load terminal and a second load terminal. The second load terminal of the first load is electrically coupled to the first load terminal of the second load. The method also includes the steps of selecting a power state or an off state for each load device and applying a first reference voltage to the second load terminal of the first load. The method includes the additional step of applying a second reference voltage to the first load terminal of the first load if the power state is selected for the first load. If the power state is selected for the second load, the second reference voltage is applied to the second load terminal of the second load. If the off state is selected for the first load, the first reference voltage is applied to the first load terminal of the first load. Similarly, if the off state is selected for the second load, the first reference voltage is applied to the second load terminal of the second load. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features and advantages of the invention will become apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed on illustrating the principles of the present invention. 
     FIG. 1 is a highly schematic block diagram depicting an embodiment of the invention; 
     FIG. 2 is a signal diagram showing the operation of the embodiment of FIG. 1; 
     FIG. 3 is a flowchart describing an embodiment of a method of using the invention; and 
     FIG. 4 is a schematic diagram of an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As an overview and referring to FIG. 1, a circuit  100  for selectively powering AC load devices using a DC source includes a first reference voltage terminal  5  to receive a first voltage and a second reference voltage terminal  20  to receive a second voltage. The first reference voltage terminal  5  is connected to a first input terminal  6   a ,  6   b ,  6   c  of a first switch  15   a , a second switch  15   b , and a third switch  15   c , respectively (generally  15 ). The second reference terminal  20  is connected to a second input terminal  21   a ,  21   b ,  21   c  of each switch  15   a ,  15   b ,  15   c , respectively. In one embodiment, each switch  15  is a single-pole double-throw (SPDT) switch. 
     A first load  45   a  is connected between an output terminal  46   a  of the first switch  15   a  and an output terminal  46   b  of the second switch  15   b . A second load  45   b  is connected between the output terminal  46   b  of the second switch  15   b  and an output terminal  46   c  of the third switch  15   c . The configuration of the output terminals  46   a ,  46   b , and  46   c  (generally  46 ) of the switches  15   a ,  15   b ,  15   c , respectively, with the corresponding loads  45   a ,  45   b  generally  45 ) are referred to as H-bridges. Whereas conventional methods use a separate H-bridge for each load device  45 , the present invention utilizes H-bridges that share a common leg. In FIG. 1, for example, this common leg includes the second switch  15   b . In one embodiment, the load devices  45  are electroluminescent (EL) lamps. 
     A first control switch  70   a  transmits a first input control signal  58   a , which in one embodiment is either a first control signal  62  (e.g., clock signal) or a second control signal  67  (e.g., complementary clock signal), to a control terminal  63   a  of the first switch  15   a . Optionally, the clock signals  62 ,  67  can be replaced by other forms of switching signals. The first input to control signal  58   a  causes the voltage provided at the output terminal  46   a  of the first switch  15   a  to alternate between the first voltage and the second voltage. The clock signal  62  is applied as a second input control signal  58   b  to a control terminal  63   b  of the second switch  15   b . A second control switch  70   b  transmits a third input control signal  58   c , which is either the first control signal  62  or the second control signal  67 , to a control terminal  63   c  of the third switch  15   c . The third input control signal  58   c  causes the voltage provided at the output terminal  46   c  of the third switch  15   c  to alternate between the first voltage and the second voltage. 
     A first selection signal  105   a  is applied to a selection terminal  68   a  of the first control switch  70   a  and controls the operation of the first control switch  70   a . A second selection signal  105   b  is applied to a selection terminal  68   b  of the second control switch  70   b  and controls the operation of the second control switch  70   b . When the first selection signal  105   a  is deasserted, the first control switch  70   a  applies the first control signal  62  to the control terminal  63   a  of the first switch  15   a . Thus, the same control signal  62  is applied to the control terminals  63   a ,  63   b  of the first and second switches  15   a ,  15   b , respectively. In an embodiment in which the same first control signal  62  causes the first switch  15   a  and the second switch  15   b  to connect their respective output terminals  46   a ,  46   b  to the same reference voltage terminal  5 ,  20 , no voltage difference exists between the two load terminals  65   a ,  66   a  of the first load  45   a  and no power is delivered to the first load  45   a.    
     In another embodiment, the first switch  15   a  connects its output terminal  46   a  to one reference voltage terminal  5 ,  20  in response to the first control signal  62  being applied to the control terminal  63   a  of the first switch  15   a  and the second switch  15   b  connects its output terminal  46   b  to the other reference voltage terminal  5 ,  20  in response to the first control signal  62  being applied to the control terminal  63   b  of the second switch  15   b . Thus, power is delivered to the first load  45   a  when the same control signal  62  is applied to the control terminal  63   a ,  63   b  of the first and second switches  15   a ,  15   b , respectively, because a voltage difference exists across its two load terminals  65   a ,  66   a  of the first load  45   a.    
     When the first selection signal  105   a  is asserted, the first control switch  70   a  applies the second control signal  67  to the control terminal  63   a  of the first switch  15   a . In an embodiment in which the second control signal  67  causes the first switch  15   a  to connect its output terminal  46   a  to one reference voltage terminal  5 ,  20  and the first control signal  62  causes the second switch  15   b  to connect its output terminal  46   b  to the other reference voltage terminal  5 ,  20 , a voltage difference exists between the two load terminals  65   a ,  66   a  of the first load  45   a . The voltage applied across the two load terminals  65   a ,  66   a  of the first load  45   a  results in the delivery of power to the first load  45   a . In contrast, no voltage difference exists between the two load terminals  65   a ,  66   a  of the first load  45   a  and no power is applied to the first load  45   a  when the first selection signal  105   a  is deasserted. Furthermore, if the control signals  62 ,  67  are maintained out of phase, AC power is delivered to the first load  45   a.    
     Similarly, when the second selection signal  105   b  is asserted, the second control switch  70   b  applies the second control signal  67  to the control terminal  63   c  of the third switch  15   c . In an embodiment in which the second control signal  67  causes the third switch  15   c  to connect its output terminal  46   c  to one reference voltage terminal  5 ,  20  and the first control signal  62  causes the second switch  15   b  to connect its output terminal  46   b  to the other reference voltage terminal  5 ,  20 , a voltage difference exists between the two load terminals  65   b ,  66   b  of the second load  45   b  and power is applied to the second load  45   b . In contrast, no voltage difference exists between the two terminals  65   b ,  66   b  of the second load  45   b  and no power is applied to the second load  45   b  when the second selection signal  105   b  is deasserted. If the control signals  62 ,  67  are maintained out of phase, AC power is delivered to the second load  45   b . The principle discussed above can be extended to any number of loads which have one load terminal connected to the output terminal  46   b  of the second switch  15   b.    
     FIG. 2 depicts the signal inputs and the resulting outputs for the circuit  100  of FIG. 1 for several clock cycles. The input control signals  58   a ,  58   b , and  58   c  are shown for reference. The selection signals  105   a  and  105   b  determine whether the clock signal  62  (e.g., clock) or the complementary clock signal  67  (e.g., {overscore (clock)}) is transmitted through the control switch  70   a  and  70   b , respectively, as the first and third input control signals  58   a  and  58   c , respectively. In one embodiment in which the first selection signal  105   a  is in a high state (a), the first control switch  70   a  transmits {overscore (clock)} as the first input control signal  58   a  to the control terminal  63   a  of the first switch  15   a . As described above, the clock signal  62  is transmitted as the second input control signal  58   b  to the control terminal  63   b  of the second switch  15   b.    
     When the {overscore (clock)} is transmitted as the first input control signal  58   a  to the control terminal  63   a  of the first switch  15   a , the voltage applied at the first load terminal  65   a  is out of phase with respect to the voltage applied at the second load terminal  66   a  of the first load  45   a , resulting in a voltage difference across the first load  45   a . Consequently, power is delivered to the first load  45   a . As the voltage of each clock signal  62  and  67  alternates, the polarity of the voltage difference between the first load terminal  65   a  and the second load terminal  66   a  of the first load  45   a  alternates, resulting in the delivery of AC power. This is shown as section (f) of the voltage  33   a.    
     If the first selection signal  105   a  is switched to a low state (b), the first input control signal  58   a  is substantially the same as the clock signal  62 . Consequently, the voltage applied to both load terminals  65   a ,  66   a  of the first load  45   a  is in phase and the same and therefore no voltage difference is present between the first load terminal  65   a  and the second load terminal  66   a  of the first load  45   a . Thus, no power is delivered to the first load  45   a . This is shown as section (g) of the voltage  33   a.    
     Similarly, when the second selection signal  105   b  for the second load  45   b  is in a high state (c) and (e), {overscore (clock)} is transmitted as the third input control signal  58   c  to the control terminal  63   c  of the third switch  15   c . This causes power to be applied between the first load terminal  65   b  and the second load terminal  66   b  of the second load  45   b , as shown as sections (h) and (j) of the voltage  33   b . When the second selection signal  105   b  is in a low state (d), no power is applied to the second load  45   b , as shown in section (i) of the voltage  33   b.    
     The flowchart of FIG. 3 depicts a method for powering two load devices according to one embodiment of the invention. The circuit with the two loads is initialized (step  300 ), which includes establishing control (e.g., clock) signals and reference voltages. The method also includes applying (step  302 ) a first voltage to the common terminal of the loads, thereby applying the first voltage to the second load terminal of the first load and the first load terminal of the second load. A power state (i.e., ON state or OFF state) is then independently selected (step  304 ) for the first and second loads. As described above, power is applied to a load device when a voltage difference exists between the first load terminal and the second load terminal of the load device. If an ON state was selected for the first load in step  304 , a second voltage is applied (step  308 ) to the independent load terminal of the first load. Because the first voltage is applied in step  302  to the common terminal of the two load devices, a voltage difference exists across the first and second load terminals of the first load device and power is applied to the first load device. However, if an OFF state is selected in step  304  for the first load device, the first voltage is applied (step  310 ) to the first load terminal of the first load device. Because the first voltage is applied in step  302  to the common terminal of the two load devices, no voltage difference exists across the first and second load terminals of the first load device. Therefore, no power is applied to the first load device. 
     Similarly, if an ON state is selected in step  304  for the second load device, the second voltage is applied (step  314 ) to the second load terminal of the second load device. Because the first voltage is applied in step  302  to the common terminal of the two loads, a voltage difference exists between the first and second load terminals of the second load device. Therefore, power is applied to the second load device. However, if an OFF state is selected in step  304  for the second load device, the first voltage is applied (step  316 ) to the second load terminal of the second load device. Therefore, no voltage difference exists between the first and second load terminals of the second load device and no power is applied to the second load device. The steps of the method are repeated with the phase of the voltages applied to each load being reversed (step  318 ). 
     FIGS. 4A,  4 B,  4 C, and  4 D are sections of a schematic diagram of an embodiment of a detailed circuit for powering the first and second loads  45   a ,  45   b  (not shown). The detailed circuit includes the first switch  15   a , the second switch  15   b , the third switch  15   c , the first control switch  70   a , and the second control switch  70   b . Each control switch  70   a  and  70   b  includes an electrostatic discharge (ESD) protection circuit  448   a  and  448   b , respectively. Drivers  110   a ,  110   b , and  110   c  provide the correct level input control signals  58   a ,  58   b , and  58   c , respectively, to the control terminal  63   a ,  63   b , and  63   c , respectively, of the switch  15   a ,  15   b , and  15   c , respectively. A high voltage boost circuit  408  is used to generate the voltage applied across the first reference voltage terminal  5  and the second reference voltage terminal  20 . A clock generator  60  produces a high frequency clock signal and also includes an ESD protection circuit  424 . The high frequency clock signal is provided to a frequency divider  440 . The frequency divider  440  reduces (i.e., divides) the frequency of the high frequency clock signal by a predetermined scale factor to produce the clock signal  62  and the complementary clock signal  67 . 
     The first and second load terminals  65   a  and  66   b  of the first load  45   a  are coupled to the output terminal  46   a  of the first switch  15   a  and the output terminal  46   b  of the second switch  15   b , respectively. The first and second load terminals  65   b  and  66   b  of the second load  45   b  are coupled to the output terminal  46   b  of the second switch  15   b  and the output terminal  46   c  of the third switch  15   c , respectively. Because the second load terminal  66   a  of the first load  45   a  and the first load terminal  65   b  of the second load  45   b  are coupled together, the output terminal  46   b  (ELCOM) of the second switch  15   b  forms a common terminal to the first and second loads  45   a  and  45   b.    
     The first switch  15   a  includes a four transistor network having transistors Q 1 , Q 4 , Q 8 , and Q 12 . The transistors Q 1  and Q 4  form a first sub-switch and the transistors Q 8  and Q 12  form a second sub-switch to permit rapid switching between the first and second reference voltages. If a positive voltage is applied to the control terminal  63   a ,  63   b ,  63   c  (generally  63 ) of the respective switch  15 , and consequently to the base of Q 12 , current flows through the collector of Q 12 . As a result, the top transistor Q 1  is connected to the second reference voltage terminal  20 . Transistor Q 8  is configured as a diode. When a positive voltage is applied to the Q 12  base, the second sub-switch formed from transistors Q 8  and Q 12  connects the second reference voltage terminal  20  to the output terminal  46  of the switch  15 . 
     If substantially no voltage is applied to the control terminal  63  and consequently the base of Q 12 , then no current flows through the collector of Q 12  and the Q 12  transistor is in an “off” state. As a result, the transistor Q 4  is in an “on” state because a positive voltage is applied to the base of Q 4 . Therefore, if a voltage transient is generated at coil terminal  412 , transistor Q 1  is changed to an “on” state. Current flows through the collector of the Q 1  transistor into the base of the Q 4  transistor to turn the Q 4  transistor to an “on” state. As a result, the transistor Q 1  turns to the “on” state more rapidly because current flows through the Q 4  collector and into the Q 1  base. The second switch  15   b  includes the four transistors Q 2 , Q 5 , Q 10 , and Q 13  and the third switch  15   c  includes the four transistors Q 3 , Q 6 , Q 11 , and Q 14 , which function in a manner similar to the four transistors Q 1 , Q 4 , Q 8 , and Q 12  of the first switch  15   a.    
     If the voltages of the clock signal  62  and the complementary clock signal  67  transition, the loads  45   a ,  45   b  are discharged to prevent a high negative voltage from occurring at the output terminal  46  of the switch  15 . The diodes D 7   a , D 7   b , and D 7   c  allow the rapid discharge of the two loads  45   a ,  45   b  to prevent the occurrence of the high negative voltage. Similarly, the diodes D 6   a , D 6   b , D 6   c  protect the transistors Q 4 , Q 5 , and Q 6  by preventing a high negative voltage from occurring at their bases. 
     In further detail, each control switch  70  includes two pairs of MOSFETs. Each pair of MOSFETs includes an n-channel MOSFET  455   a ,  455   b ,  455   c ,  455   d  (generally  455 ) and a p-channel MOSFET  456   a ,  456   b ,  456   c ,  456   d  (generally  456 ). The gate of each n-channel MOSFET  455  is connected to the gate of the respective p-channel MOSFET  456 . The source of each n-channel MOSFET  455  is connected to the drain of the respective p-channel MOSFET  456  and the drain of the n-channel MOSFET  455  is connected to the source of the respective p-channel MOSFET  456 . Clock signal  62  is transmitted to the source of the n-channel MOSFET  455   a ,  455   c  and the drain of the p-channel MOSFET  456   a ,  456   c . Complementary clock signal  67  is transmitted to the source of the other n-channel MOSFET  455   b ,  455   d  and the drain of the p-channel MOSFET  456   b ,  456   d.    
     Each control switch  70   a ,  70   b  also includes an inverter  452   a ,  452   b  (generally  452 ). The inverter  452   a  causes one pair of MOSFETs  455   a ,  456   a  to be in an “on” state when the other pair of MOSFETs  455   b ,  456   b  is in an “off” state, thus allowing only one of the control signals  62 ,  67  to be transmitted by the first control switch  70   a  to the control terminal  63   a  of the first switch  15   a . Similarly, the inverter  452   b  causes the MOSFET pair  455   c ,  456   c  to be in an “on” state when the other pair of MOSFETs  455   d ,  456   d  is in an “off” state, thus allowing only one of the control signals  62 ,  67  to be transmitted by the second control switch  70   b  to the control terminal  63   c  of the third switch  15   c.    
     While the invention has been particularly shown and described with reference to specific preferred embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.