Abstract:
There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based on and claims priority under 35 USC 119 from Japanese Patent Application No. 2009-076404 filed on Mar. 26, 2009, the disclosure of which is incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The invention relates to a reference potential generating circuit of a semiconductor memory and more particularly, to a reference potential generating circuit included in an internal power supply circuit mounted in a semiconductor memory. 
         [0004]    2. Related Art 
         [0005]    In the related art, various technology for suppressing overshoot at the time of supplying power in a voltage generating circuit mounted in a semiconductor integrated circuit have been suggested (for example, Japanese Patent Application Laid-Open (JP-A) No. 2005-122574). 
         [0006]      FIG. 11  illustrates an example of a reference potential generating circuit included in an internal power supply circuit mounted in a ROM functioning as a semiconductor memory. 
         [0007]    A reference potential generating circuit  100  illustrated in  FIG. 11  has a structure in which a PMOS transistor P 2  and an NMOS transistor N 3  for reference potential correction are connected in series and this circuit is connected parallel to a circuit in which a PMOS transistor P 1 , plural DMOS transistors D 1  to D 4 , an NMOS transistor N 1 , an NMOS transistor N 1  and an NMOS transistor N 2  are connected in series. The gate of the PMOS transistor P 1  receives an internal power supply enable signal CEB_GEN output by an internal power supply control circuit (not illustrated). The plural DMOS transistors D 1  to D 4  are for current supply and whose gates are connected to each other. The NMOS transistor N 1  is for temperature compensation and whose gate is connected to the gates of the DMOS transistors D 1  to D 4 . The gate of NMOS transistor N 2  is applied with a power supply voltage VCC. A reference potential VCWREF is output from a connection point C of the DMOS transistors D 2  and D 3 . 
         [0008]    In the reference potential generating circuit  100  having the above configuration, since a variation in the reference potential VCWREF is fed back by the NMOS transistor N 1  for temperature compensation, excellent temperature and voltage characteristics may be obtained. 
         [0009]    A gate of the PMOS transistor P 2  for voltage correction is connected to a connection point B of the DMOS transistor D 4  and the NMOS transistor N 1 , and the power supply voltage VCC is applied to a gate of the NMOS transistor N 3 . 
         [0010]    For example, when the internal power supply enable signal CEB_GEN is at a low level, a mode becomes a normal operation mode. When the internal power supply enable signal CEB_GEN is at a high level, the mode becomes a standby mode. 
         [0011]    In the reference potential generating circuit  100 , when a level of the internal power supply enable signal CEB_GEN becomes low and the mode becomes the normal operation mode, in order to start to supply power to an internal circuit by the internal power supply circuit, first, if the PMOS transistor P 1  is turned on, a current Ia flows through the DMOS transistor D 1 . Thereby, as illustrated in  FIG. 12 , a voltage VREF_A at a connection point A gradually increases. However, a coupling noise of the voltage VREF_A with respect to a voltage VPG at the connection point B increases, and the voltage VGP increase as the voltage VREF_A increases. As a result, the PMOS transistor P 2  for reference potential correction is not turned on and the current Ip does not flow. 
         [0012]    Meanwhile, since the current Ia immediately flows through the DMOS transistors D 1  to D 4  for current supply, the reference potential VCWREF output from the connection point C may overshoot, as illustrated in  FIG. 12 . This phenomenon becomes notable when resistance generated from the gate of the PMOS transistor P 2  for reference potential correction to a ground through the NMOS transistors N 1  and N 2  for temperature compensation increases. 
       SUMMARY 
       [0013]    Accordingly, it is an object of the invention to provide a reference potential generating circuit of a semiconductor memory that can prevent a reference potential from overshooting at the starting time, without deteriorating temperature and voltage characteristics. 
         [0014]    According to an aspect of the invention, there is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes plural first MOS transistors, which are used for supply of a current to an internal circuit of the semiconductor memory and are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group and are used for temperature compensation; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential output from a predetermined connection point of the plural first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to permit the supply of power to the internal circuit of the semiconductor memory is input. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    Exemplary embodiments of the present invention will be described in detail based on the following figures, wherein: 
           [0016]      FIG. 1  is a diagram illustrating a schematic configuration of a ROM; 
           [0017]      FIG. 2  is a diagram illustrating a schematic configuration of an internal power supply control circuit; 
           [0018]      FIG. 3  illustrates waveforms of signals from individual components of the internal power supply control circuit and an internal power supply circuit; 
           [0019]      FIG. 4  is a diagram illustrating a schematic configuration of the internal power supply circuit; 
           [0020]      FIG. 5  is a circuit diagram illustrating a reference voltage generating circuit according to an embodiment; 
           [0021]      FIG. 6  is a diagram illustrating waveforms of potentials of individual components of the reference voltage generating circuit according to the embodiment; 
           [0022]      FIG. 7A  is a diagram illustrating measurement results of a relationship between a power supply voltage and a reference voltage under plural temperature conditions in a reference voltage generating circuit according to the related art; 
           [0023]      FIG. 7B  is a diagram illustrating measurement results of a relationship between a passage time after a level of an internal power supply enable signal becomes low and a reference potential in plural conditions in the reference voltage generating circuit according to the related art; 
           [0024]      FIG. 8A  is a diagram illustrating measurement results of a relationship between a power supply voltage and a reference voltage under plural temperature conditions in the reference voltage generating circuit according to the embodiment; 
           [0025]      FIG. 8B  is a diagram illustrating measurement results of a relationship between a passage time after a level of an internal power supply enable signal becomes low and a reference potential in plural conditions in the reference voltage generating circuit according to the embodiment; 
           [0026]      FIG. 9  is a table illustrating a comparison result of characteristics of the reference voltage generating circuit according to the related art and the reference voltage generating circuit according to the embodiment; 
           [0027]      FIG. 10  is a circuit diagram of a reference voltage generating circuit according to a modification of the embodiment; 
           [0028]      FIG. 11  is a circuit diagram of the reference voltage generating circuit according to the related art; and 
           [0029]      FIG. 12  is a diagram illustrating waveforms of potentials of individual components of the reference voltage generating circuit according to the related art. 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    Hereinafter, an embodiment of the invention will be described in detail with reference to the drawings. 
         [0031]      FIG. 1  illustrates the schematic configuration of a ROM  10  that functions as a semiconductor memory according to the embodiment. As illustrated in  FIG. 1 , the ROM  10  includes a memory cell array  12 , an address buffer  14 , a row decoder selector  16 , a column decoder  18 , a BL selector  20 , a sense amplifier  22 , an output buffer  24 , an internal power supply control circuit  26 , and an internal power supply circuit  28 . 
         [0032]    The memory cell array  12  is composed of plural sub-arrays and each sub-array includes plural memory cells. 
         [0033]    The address buffer  14  stores an address designated by a control circuit (not illustrated) that controls the ROM  10 . 
         [0034]    The row decoder selector  16  selects a word line WL and a sub-array selection line DS according to a row address included in the address stored in the address buffer  14 , applies a voltage VCW supplied from the internal power supply circuit  28  to the selected word line WL, and applies a voltage VCWP supplied from the internal power supply circuit  28  to the sub-array selection line DS. 
         [0035]    The column decoder  18  outputs a column address, which is included in the address stored in the address buffer  14 , to a bit line (BL) selector  20 . 
         [0036]    The BL selector  20  selects a bit line BL according to the column address output from the column decoder  18  and applies a voltage CDV, which is supplied from the internal power supply circuit  28  through the sense amplifier  22 , to the selected bit line BL. 
         [0037]    The sense amplifier  22  detects a current flowing through a memory cell, which is selected by the word line WL selected by the row decoder selector  16  and the bit line BL selected by the BL selector  20 , among memory cells constituting the memory cell array  12 , and outputs data corresponding to a determination result of ‘0’ or ‘1’ to the output buffer  24 . 
         [0038]    The output buffer  24  stores the input data of the memory cell and outputs the stored data, when a level of an output enable signal OEB input from a control circuit (not illustrated) to control the ROM  10  becomes low. 
         [0039]    When a level of a chip enable signal CEB input from the control circuit (not illustrated) to control the ROM  10  becomes low, the internal power supply control circuit  26  causes a level of the internal power supply circuit enable signal CEB_GEN to become low, to permit the supply of power from the internal power supply circuit  28  to the internal circuits such as the row decoder selector  16 , the column decoder  18 , and the sense amplifier  22 . As a result, the voltage CDV is supplied from the internal power supply circuit  28  to the sense amplifier  22 , the voltage VCW is supplied to the row decoder selector  16 , and the voltage VCWP is supplied to the row decoder selector  16  and the column decoder  18 . 
         [0040]    When the chip enable signal CEB is at a low level, the ROM  10  enters in a normal operation mode. When the chip enable signal CEB is at a high level, the ROM  10  enters in a standby mode. 
         [0041]    As illustrated in  FIG. 2 , the internal power supply control circuit  26  includes a start-up circuit  30 , a timer control circuit  32 , a periodic signal generating circuit  34 , and an internal power supply enable signal generating circuit  36 . 
         [0042]    The start-up circuit  30  outputs a low-level signal during a constant period, when power is supplied, and outputs a signal EVCINT (illustrated in the first graph of  FIG. 3 ), whose level becomes high, to the timer control circuit  32 . During a period in which the signal EVCINT is at a low level, since the internal power supply circuit  28  enters in an always-on state, the internal power supply circuit  28  enters in the always-on state during a predetermined period from the supply of the power. This is because various voltages such as the voltage VCWP are increased to a necessary voltage level in a short time. 
         [0043]    When the chip enable signal CEB is at a low level, that is, when the mode is the normal operation mode, the timer control circuit  32  always outputs a high-level signal. Only when the level of the chip enable signal CEB becomes high, the mode changes to the standby mode, and the level of the signal EVCINT input from the start-up circuit  30  is high, the timer control circuit  32  outputs a signal TIMEB (illustrated in the second graph of  FIG. 3 ), whose level is switched to a low level, to the periodic signal generating circuit  34 . 
         [0044]    When the level of the signal EVCINT is low, the level of the signal TIMEB becomes high and the periodic signal generating circuit  34  does not operate. 
         [0045]    When the level of the signal TIMEB input from the timer control circuit  32  becomes low, the periodic signal generating circuit  34  outputs a periodic signal TIM 2 , which repeats a high level and a low level with a predetermined period T 1  as illustrated in  FIG. 3 , to the internal power supply enable signal generating circuit  36 . 
         [0046]    The internal power supply enable signal generating circuit  36  outputs the internal power supply enable signal CEB_GEN whose level becomes low during a predetermined period T 2  with a predetermined duty ratio N to the internal power supply circuit  28  in synchronization with a rising edge of a periodic signal TIM 2  input from the periodic signal generating circuit  34 . 
         [0047]    When the chip enable signal CEB is at a low level, the internal power supply enable signal generating circuit  36  always maintains the level of the internal power supply enable signal CEB_GEN at a low level. 
         [0048]    As illustrated in  FIG. 4 , the internal power supply circuit  28  includes a reference potential generating circuit  50 , a first voltage generating circuit  52 A to generate a voltage VCWP, a second voltage generating circuit  52 B to generate a voltage VCW, and a third voltage generating circuit  52 C to generate a voltage CDV. 
         [0049]    When the level of the internal power supply enable signal CEB_GEN output from the internal power supply enable signal generating circuit  36  becomes low, the reference potential generating circuit  50  generates a reference potential VCWREF and outputs the reference potential VCWREF to the first to third voltage generating circuits  52 A to  52 C. 
         [0050]    The first voltage generating circuit  52 A generates the voltage VCWP, based on the input reference potential VCWREF, and outputs the voltage VCWP to the row decoder selector  16  and the column decoder  18 . 
         [0051]    The second voltage generating circuit  52 B generates the voltage VCW, based on the input reference potential VCWREF, and outputs the voltage VCW to the row decoder selector  16 . 
         [0052]    The third voltage generating circuit  52 C generates the voltage CDV, based on the input reference potential VCWREF, and outputs the voltage CDV to the sense amplifier  22 . 
         [0053]    When the level of the internal power supply enable signal CEB_GEN output from the internal power supply enable signal generating circuit  36  becomes low, the internal power supply circuit  28  supplies power to the individual components in the ROM  10 . The graph at the bottom in  FIG. 3  illustrates a waveform of a consumption current of the internal power supply circuit  28  in the standby mode. 
         [0054]    As such, in the standby mode, the internal power supply enable signal CEB_GEN is a signal that intermittently permits the supply of power from the internal power supply circuit  28 . When the internal power supply enable signal CEB_GEN is at a high level, the consumption current of the internal power supply circuit  28  becomes almost zero. Thereby, in the standby mode, since the ROM  10  intermittently operates, the voltages VCWP, VCW, and CDV that are output from the internal power supply circuit  28  output the same set values as those in the case of the normal operation during the period T 2  where the level of the internal power supply enable signal CEB_GEN becomes low, during the period where the signal TIMEB is at a low level, as illustrated in the second graph of  FIG. 3 , and gradually decrease during the other period. This operation is repeated. 
         [0055]    Therefore, even in the standby mode, the consumption current can be suppressed while a voltage level is maintained at an arbitrary level. As a result, the consumption current of the ROM  10  in the standby mode can be suppressed. When the mode changes to the normal operation mode, the level of the voltage applied to the individual components of the ROM  10  can be quickly increased to a necessary level, thereby suppressing an access speed from being lowered. 
         [0056]      FIG. 5  is a circuit diagram of the reference potential generating circuit  50 . In  FIG. 5 , the same components as those in the reference potential generating circuit  100  illustrated in  FIG. 11  are denoted by the same reference numerals and the detailed description thereof is omitted. 
         [0057]    As illustrated in  FIG. 5 , the reference potential generating circuit  50  has a structure in which a coupling noise cancellation circuit  60  to cancel the coupling noise of the voltage VREF_A with respect to the voltage VPG at the connection point B is provided between the gate of the PMOS transistor P 1  receiving the internal power supply enable signal CEB_GEN and the gate of the PMOS transistor P 2  for reference potential correction. This structure is a differentiates the reference potential generating circuit  50  illustrated in  FIG. 5  from the reference potential generating circuit  100  illustrated in  FIG. 11 . 
         [0058]    The coupling noise cancellation circuit  60  has a structure in which two inverters I 1  and I 2  and an NMOS transistor N 5  are connected in series. An input side of the inverter I 1  receives the internal power supply enable signal CEB_GEN. A drain and a source of the NMOS transistor N 5  are connected to the gate of the PMOS transistor P 2 . The NMOS transistor N 5  has a function of decreasing the voltage VPG applied to the gate of the PMOS transistor P 2  at the starting up time. The number of inverters is not limited to two. For example, the number of inverters may be an even number greater than or equal to four or the inverters may be omitted. 
         [0059]    In the reference potential generating circuit  50 , when the level of the internal power supply enable signal CEB_GEN becomes low and the mode becomes the normal operation mode, in order to begin supplying power to the internal circuits such as the row decoder selector  16 , the column decoder  18 , and the sense amplifier  22  by the internal power supply circuit  28 , if the PMOS transistor P 1  is turned on, the current Ia is made to flow through the DMOS transistor D 1 . 
         [0060]    Accordingly, as illustrated in  FIG. 6 , the voltage VREF_A at the connection point A gradually increases. However, the coupling noise of the voltage VREF_A with respect to the voltage VPG is canceled by the coupling noise cancellation circuit  60 . That is, the coupling noise cancellation circuit  60  generates a cancellation noise to decrease the voltage VPG, at the starting up time. Thereby, since the voltage VPG does not increase as the voltage VREF_A increases, the PMOS transistor P 2  for correction is turned on, and the current Ip can be made to flow. For this reason, the reference potential VCWREF can be prevented from overshooting. 
         [0061]      FIG. 7A  illustrates measurement results of a relationship between the power supply voltage VCC and the reference potential VCWREF of the reference potential generating circuit  100  illustrated in  FIG. 11 , when the temperature is set to −10° C., 25° C., 80° C., and 105° C.  FIG. 7B  illustrates measurement results of a relationship between the time passed after the level of the internal power supply enable signal CEB_GEN becomes low and the reference potential VCWREF, when the temperature is −10° C. and the power supply voltage VCC is 3.6 V, the temperature is 25° C. and the power supply voltage VCC is 3.3 V, and the temperature is −105° C. and the power supply voltage VCC is 2.7 V. 
         [0062]      FIG. 8A  illustrates measurement results of a relationship between the power supply voltage VCC and the reference potential VCWREF of the reference potential generating circuit  50  according to the embodiment, under the same conditions as those of  FIG. 7A .  FIG. 8B  illustrates measurement results of a relationship between the time passed after the level of the internal power supply enable signal CEB_GEN becomes low and the reference potential VCWREF, under the same conditions as those of  FIG. 7B . 
         [0063]      FIG. 9  illustrates a calculation result of a time needed when a voltage becomes at least 95% of a DC value (voltage where a characteristic becomes constant) of the reference potential VCWREF from the start, a calculation result of a time needed when the voltage becomes at least 98% of the DC value (voltage where a characteristic becomes constant) of the reference potential VCWREF from the start, and a calculation result of the overshooting amount (maximum value of the reference potential VCWREF/DC value of the reference potential VCWREF) of the reference potential VCWREF, with respect to each of the case where the temperature is −10° C. and the power supply voltage VCC is 3.6 V and the case where the temperature is 105° C. and the power supply voltage VCC is 2.7 V, a calculation result of a voltage characteristic illustrated by a difference with the reference potential VCWREF when the power supply voltage is 3.3 V, with respect to each of the case where the temperature is 25° C. and the power supply voltage VCC is 3.6 V and the case where the temperature is 25° C. and the power supply voltage VCC is 2.7 V, and a calculation result of a temperature characteristic illustrated by a difference with the reference potential VCWREF when the temperature is 25° C., with respect to each of the case where the power supply voltage VCC is 3.3 V and the temperature is −10° C. and the case where the power supply voltage VCC is 3.3 V and the temperature is 105° C., from the measurement results illustrated in  FIGS. 7A to 8B , which are calculated with respect to each of the reference potential generating circuit  100  (in related art) and the reference potential generating circuit  50  (in this invention). The measurement results related to the overshooting, the voltage characteristic, and the temperature characteristic in the invention are illustrated together with values converted into the voltage VCW. 
         [0064]    As illustrated in  FIG. 9 , in the reference potential generating circuit  100  according to the related art, the temperature characteristic is excellent, but the rising edge of the potential comes late and the overshooting amount is large. In contrast to the reference potential generating circuit  100  in the related art, the reference potential generating circuit  50  in the present embodiment has excellent temperature and voltage characteristics, a small overshooting amount, and a fast rising edge of the potential. 
         [0065]    In the embodiment, the configuration where the NMOS transistor N 5  illustrated in  FIG. 5  is used as the element to cancel the coupling noise has been described, but the present invention is not limited thereto. For example, as illustrated in  FIG. 10 , the PMOS transistor P 3  may be reversely connected. That is, the gate of the PMOS transistor P 3  may be connected to the gate of the PMOS transistor P 2  and the drain and the source thereof may be connected to the output side of the inverter I 2 . 
         [0066]    In the embodiment, the case where the invention is applied to the ROM functioning as the semiconductor memory has been described, but the present invention can be applied to any semiconductor memory, such as a DRAM, which has an internal power supply. 
         [0067]    According to an aspect of the invention, there is provided a reference potential generating circuit of a semiconductor memory, wherein the fourth MOS transistor is an NMOS transistor of which a drain and a source are connected to the gate of the third MOS transistor and a gate receives the permission signal. 
         [0068]    According to the invention, the reference potential can be prevented from being overshoot at the time of the start, without deteriorating the temperature and voltage characteristics.