Abstract:
A splitter unit including a chassis containing splitter cards. The splitter unit includes a central processing unit mounting location. The splitter unit also includes test access devices that are inactive when the central processing unit mounting location is vacant. The splitter unit is configured such that the splitter cards provide passive signal splitting even when the central processing unit mounting location is vacant.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to telecommunications equipment. More particularly, the present invention relates to telecommunications equipment used in twisted pair telephone carrier systems. 
   BACKGROUND OF THE INVENTION 
   Telecommunications systems for transmitting voice and data to and from subscribers (i.e., residences and businesses) are known. An exemplary telecommunications system  10  is schematically shown in  FIG. 1 . The system  10  includes a Main Distribution Frame  12  (MDF) for connecting digital subscriber lines  13  (DSLs) to internal lines  14  within a telephone server&#39;s central office  15 . The central office  15  frequently includes a DSLAM  18  (Digital Subscriber Line Access Multiplexer) and a voice switch  19 . The DSLAM  18  transmits data to and receives data from a communications network/backbone  21 . The voice switch  19  transmits voice signals to and receives voice signals from a communications network/backbone  23 . The networks  21  and  23  can be dedicated lines that are part of the same network. POTS splitter devices  16  (i.e., Plain Old Telephone Service splitter devices) are used at the central office  15  to combine data signals from the DSLAM  18  with voice signals from the voice switch  19 . By combining the signals, the signals can be simultaneously routed to a subscriber  25  through a single DSL  13 . Signals transmitted from subscribers  25  to the central office  15  are also routed through the POTS splitter devices  16 . At the POTS splitter devices  16 , the signals are split and directed to the DSLAM  18  and the voice switch  19 . Typically, the splitter devices  16  include low pass filters for removing the data content from any signals transmitted from the splitter devices  16  to the voice switch  19 . Since DSLAMs  18  frequently include high pass filters for removing the voice band, the splitter devices  16  usually do not include filters for filtering the voice content from the signals transmitted to the DSLAM  18 . 
   The ability to provide DSL service to a customer is dependent upon the quality of the outside plant copper lines providing telephone service to the customer. Before providing service, it is important “qualify” the copper lines to ensure that an acceptable quality of service can be delivered. This process is known as loop qualification. In addition to loop qualification, it is also important for service providers to have fault isolation capabilities. To perform loop qualification or fault isolation, the service provider typically dispatches a technician or utilizes a remote access and test device. Remote test access is desirable because it can eliminate repetitive technician dispatches and ensures timely fault restoration. Real estate is a premium in the central office environment. Thus, it is also desirable to conserve space by integrating test access devices into existing components in the service provider&#39;s central office. 
   SUMMARY 
   One inventive aspect of the present disclosure relates to a splitter device having test access devices that can be activated to provide remote test access capabilities. In one embodiment, the splitter device is configured to have passive splitter capabilities when the test access devices are inactive. If remote test access is desired, the splitter device can be upgraded by adding a central processing unit that activates the test access devices. This enables a customer to defer the costs associated with activating the test access devices until remote test access is required. 
   A variety of other inventive aspects of the disclosure are set forth in part in the description that follows, and in part will be apparent from the description, or may be learned by practicing the inventive aspects. The inventive aspects relate to individual features as well as combinations of features. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of an exemplary prior art telecommunications system; 
       FIG. 2  is a front, perspective view of a splitter unit having inventive aspects in accordance with the principles of the present disclosure; 
       FIG. 3  is a rear perspective view of the splitter unit of  FIG. 2 ; 
       FIG. 4  is a top view of the splitter unit of  FIG. 2 ; 
       FIG. 5  is an exploded view of the splitter unit of  FIG. 2  with a majority of the cards removed; 
       FIG. 6  is an exploded view of the splitter unit of  FIG. 2  showing reinforcing dividers mounted within the chassis; 
       FIG. 7  is a front perspective view of a back plane of the splitter unit of  FIG. 2 ; 
       FIG. 8  is an exploded view of the back plane of  FIG. 7 ; 
       FIG. 9  is a front view of a distribution circuit board that is a component of the back plane of  FIG. 7 ; 
       FIG. 10  is a top view of the distribution circuit board of  FIG. 9 ; 
       FIG. 11  is a rear view of the distribution circuit board of  FIG. 9 ; 
       FIG. 12  is a front view of a central processing unit interface printed circuit board that is a component of the back plane of  FIG. 7 ; 
       FIG. 13  is a side view of the central processing unit interface printed circuit board of  FIG. 12 ; 
       FIG. 14  is a back view of the central processing unit interface printed circuit board of  FIG. 12 ; 
       FIG. 15  is a side view of a splitter card that is a component of the splitter unit of  FIG. 2 ; 
       FIG. 16  is a front view of the splitter card of  FIG. 15 ; 
       FIG. 17  provides a circuit schematic for one splitter of the splitter card of  FIG. 15 ; 
       FIG. 18  is a side view of a central processing unit card that is a component of the splitter unit of  FIG. 2 ; 
       FIG. 19  is a front view of the central processing unit card of  FIG. 18 ; 
       FIG. 20  is a schematic diagram of the splitter unit of  FIG. 2  with the central processing unit card mounting location vacant; 
       FIG. 21  is a schematic diagram of the splitter unit of  FIG. 2  showing the central processing unit card mounted at the central processing unit card mounting location and with test relay switches of the system in normal positions; 
       FIG. 22  illustrates the schematic of  FIG. 21  with the test relay switches switched from the normal positions to intrusive testing positions; and 
       FIG. 23  illustrates the schematic of  FIG. 21  with the relay switches oriented to provide non-intrusive signal monitoring. 
   

   While the embodiments disclosed herein are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail below. It is to be understood, however, that the intention is not to limit the inventive aspects of the present disclosure to the particular embodiments described. On the contrary, the disclosed embodiments are merely examples of how certain inventive aspects may be practiced, and that other embodiments are not excluded. 
   DETAILED DESCRIPTION 
   In the following detailed description, references are made to the accompanying drawings that depict various embodiments in which the inventive aspects may be practiced. It is to be understood that other embodiments may be utilized, and structural and functional changes may be made without departing from the scope of the inventive aspects 
   It will be appreciated that the various aspects of the present invention are applicable to a variety of telecommunications service options including, among other things, ADSL (Asymmetric Digital Subscriber Line), IDSL (Integrated Services Digital Network DSL), SDSL (Symmetric DSL) and VDSL (very high speed DSL) services. 
     FIGS. 2-6  illustrate a splitter unit  50  having features that are examples of inventive aspects in accordance with the principles of the present disclosure. The splitter unit  50  includes a chassis  52  for holding a central processing unit (CPU) card  56  and a plurality of splitter cards  54 . As best shown in  FIG. 5 , the depicted chassis  52  includes 22 splitter card mounting locations  70  and one CPU card mounting location  72 . Top and bottom card edge guides  74  are provided at each of the card mounting locations  70 ,  72 . It will be appreciated that in other embodiments the splitter card capacity can be varied. 
   Referring to  FIG. 5 , the splitter chassis  52  has a rectangular configuration defined by left and right walls  58 L and  58 R, top and bottom walls  60 T and  60 B, and rear wall  62 . As best shown in  FIG. 4 , flanges  65  are provided on the left and right walls  58 L,  58 R for allowing the splitter unit  50  to be fastened (e.g., by screws or bolts) to a conventional rack, frame or cabinet. A front  64  of the chassis  52  is preferably open to allow for the insertion of the splitter cards  54  and the CPU card  56 . When the chassis  52  is not fully loaded with splitter cards, blank panels  57  (see  FIG. 2 ) can be used to close the open front  64  of the chassis  52 . By removing the blank panels, additional splitter cards can be added to the chassis  52  as capacity requirements increase. A blank panel can be used to block the CPU card mounting location  72  when the CPU card mounting location  72  is vacant. 
   Referring to  FIG. 6 , the chassis  52  can also include reinforcing dividers  66  that segregate the interior of the chassis  52  into multiple compartments. In the embodiment of  FIG. 6 , a separate compartment  67  is provided that segregates the CPU card  56  from the splitter cards  54 . 
   Referring to  FIGS. 5 and 7 , the splitter unit  50  includes an interface back plane  104  having components for providing electrical connections with the splitter cards  54  when the cards  54  are mounted within the chassis  52 . For example, each of the splitter card mounting locations  70  includes first, second and third interface connectors  106 - 108  arranged in a vertical column. In the depicted embodiment, the connectors  106 - 108  comprise card edge connectors. As shown in  FIG. 5 , the splitter cards  54  include first, second and third card edge extensions  112 - 114  that respectively align with the connectors  106 - 108 . When the splitter cards  54  are fully inserted into the splitter card mounting locations  70 , the card edge extensions  112 - 114  fit within their respective interface connectors  106 - 108  to provide an interface between the splitter cards  54  and the back plane. 
   Referring to  FIG. 8 , mini back plane circuit boards  116  are provided at each of the splitter card mounting locations  70 . The mini back plane circuit boards  116  electrically connect the second and third interface connectors  107 ,  108  of each splitter card mounting location to a corresponding set of LINE, VOICE and DATA connectors  76 ,  78  and  80 . The LINE connectors  76  can be used to provide interface locations for allowing the splitter unit  50  to interface with outside lines such as digital subscriber lines  13  (see  FIG. 1 ). The VOICE connectors  78  (i.e. POTS connectors) can be used to provide interface locations for allowing the splitter unit  50  to interface with a voice switch such as voice switch  19  (see  FIG. 1 ). The DATA connectors  80  can be used to provide interface locations for allowing the splitter unit  50  to interface with a DSLAM such as DSLAM  18  (see  FIG. 1 ). In a non-limiting embodiment, the connectors  76 ,  78  and  80  can be RJ-21 connectors for use in providing connections with corresponding connectors provided on cables such as 25-pair twisted pair cables. 
   The mini back plane circuit boards  116  are aligned generally perpendicular relative to the rear wall  62  of the chassis  52 . The interface connectors  107  and  108  are secured to front edges of the circuit boards  116 . The LINE, VOICE and DATA connectors  76 ,  78  and  80  are fastened to the circuit boards  116  adjacent rear edges of the circuit boards  116 . As shown in  FIG. 8 , the LINE, VOICE and DATA connectors  76 ,  78  and  80  mount within openings  118  defined by the rear wall  62  of the chassis  52 . Fasteners are used to secure the connectors  77 ,  78  and  80  within the openings  118 . When mounted within the openings, the connectors  76 ,  78  and  80  define an array of vertical columns and are accessible from a rear side of the chassis  52  (see  FIG. 3 ). 
   To maintain alignment and spacing between the mini back plane circuit boards  116 , a reinforcing bracket  120  (see  FIG. 8 ) is secured (i.e., fastened) to the rear wall  62  of the chassis  52 . The reinforcing bracket  120  includes a first portion  121  fastened to the rear wall  62  of the chassis  52 , and a second portion  122  that angles forwardly and downwardly from the rear wall  62 . The second portion  122  includes a plurality of notches  124 . Each notch  124  receives and supports a top edge of a corresponding one of the mini back plane circuit boards  116 . 
   It will be appreciated that the mini back plane circuit boards  116  include tracings for electrically connecting the sets of connectors  107  and  108  to their corresponding sets of LINE, VOICE and DATA connectors  76 ,  78  and  80 . For example,  FIG. 20  schematically shows a mini back plane circuit board  116  having connector  107  electrically to LINE and VOICE connectors  76  and  78 , and connector  108  electrically connected to DATA connector  80 . Mini back plane circuit boards  116  are also described in U.S. application Ser. No. 09/549,133, entitled “Splitter Architecture For A Telecommunications System” filed Apr. 13, 2000, which is hereby incorporated by reference in its entirety. 
   Referring again to  FIG. 8 , the interface back plane  104  also includes a distribution circuit board  130 . The distribution circuit board  130  mounts within the chassis  52  at a location above the mini back plane circuit boards  116  and is preferably aligned parallel to the rear wall  62  of the chassis  52 . The connectors  106  corresponding to each of the splitter card mounting locations  70  are mounted on a front side of a distribution circuit board  130  (see  FIGS. 8-10 ). Test connectors  90  and  92  are mounted on a back side of the distribution circuit board  130  (see  FIGS. 10 and 11 ). 
   As schematically depicted in  FIG. 20 , the distribution circuit board  130  includes tracings that electrically connect the connectors  106  to the test connector  90 . As also shown schematically in  FIG. 20 , the distribution circuit board  130  can also include tracings for connecting the test connector  90  in series with the test connector  92 . When the distribution board  130  is secured to the rear wall  62  of the chassis, the test connectors  90 ,  92  extend through openings  93  defined by the rear wall  62  so as to be accessible from the rear of the chassis  52  (see  FIG. 3 ). The test connector  90  provides an interface location for connecting the splitter unit  50  to a test head or other testing device. The test connector  92  is preferably used to daisy chain multiple chassis together. 
   Referring now to  FIGS. 5 and 7 , the interface back plane  104  of the splitter unit  50  further includes structure for providing an interface with the CPU card  56  when the CPU card  56  is mounted at the CPU card mounting location  72 . For example, the back plane  104  includes a CPU back plane circuit board  140  having a front side to which first and second interface connectors  142  and  144  are mounted (see  FIGS. 12 and 13 ). The CPU back plane circuit board  140  mounts to the chassis behind the CPU card mounting location  72 . When secured to the chassis  52 , the circuit board  140  is generally parallel to the rear wall  62  of the chassis  52 . The interface connectors  142  and  144  are depicted as card edge connectors adapted to receive corresponding first and second card edge extensions  146 ,  148  of the CPU card  56  when the CPU card  56  is mounted at the CPU card mounting location  72 . A connector  149  including an array of conductive pins is also provided on the front side of the CPU back plane circuit board  140 . The pins of the connector  149  are adapted to be received within corresponding receptacles of a connector  151  provided on the back side of the distribution circuit board  130 . Thus, when the chassis  52  is assembled, the connectors  149  and  151  provide an electrical interface between the CPU back plane circuit board  140  and the distribution circuit board  130 . 
   As shown in  FIGS. 13 and 14 , a power connector  94 , an alarm connector  96 , an Ethernet connector  98 , a serial port  100  and an auxiliary port  102  are mounted on the back side of the CPU back plane circuit board  140 . As shown schematically in  FIG. 20 , the CPU back plane circuit board  140  includes tracings for electrically connecting the CPU interface connectors  142 ,  144  to the connectors  94 ,  96 ,  98 ,  100  and  102 . When the splitter unit  50  is assembled, the back side of the CPU back plane circuit board  140  is covered by a panel  141  (see  FIG. 3 ) that is separately removable from the rear wall  62  of the chassis  52 . The panel  141  defines openings corresponding to each of the connectors  94 ,  96 ,  98 ,  100  and  102  such that the connectors are accessible from the rear of the chassis  52 . 
   Referring again to  FIGS. 5 and 7 , one aspect of the splitter unit  50  is that the various back plane circuit boards are separately removable from the chassis  52 . For example, each of the mini back plane circuit boards  116  is separately or individually removable from the chassis  52 . Similarly, the distribution circuit board  130  as well as the CPU interface circuit board  140  are separately and individually removable from the chassis  52 . By using a number of separately removable circuit boards at the interface back plane  104 , repairs can be simplified because it is not necessary to remove a back plane board that corresponds to a large number of different type of components. Instead, only the board corresponding to the defective component need be removed and replaced. 
   Referring now to  FIGS. 15-16 , one of the splitter cards  54  is shown in isolation from the splitter chassis  52 . The depicted splitter card  54  includes a plurality of splitters  182  (e.g., 24 splitters) mounted on a circuit board  184 . The splitter card  54  also includes a front faceplate  186  mounted to a front edge of the circuit board  184 . Retaining latches  188  are located at top and bottom edges of the faceplate  186  for retaining the splitter card  54  in the chassis  52 . As previously indicated, the splitter card  54  also preferably includes first, second and third card edge extensions  112 - 114  located at a rear edge of the circuit board  184 . The first extension  112  is rearwardly offset relative to the second and third extensions  113 ,  114 . When the card  54  is fully inserted within a splitter card mounting location of the chassis  52 , the extensions  112 - 114  are respectively received in the connectors  106 - 108  to provide an electrical interface between the splitter card  54  and the back plane  104  of the splitter unit  50 . It will be appreciated that when the extensions  112 - 114  are received within the card edge connectors  106 - 108 , springs of the connectors  106 - 108  engage conductive pads or contacts of the extensions  112 - 114  to provide electrical connections thereinbetween. 
   The splitters  182  of the splitter unit  50  can have a number of different configurations. For example, the splitters can include conventional POTS splitter circuits. A conventional POTS splitter circuit functions to split a signal (e.g., a signal from a DSL) into two signals. One of the split signals is typically passed through one or more low pass filters capable of passing the relatively lower frequency voice content of the signal (e.g., less than about 4 kilohertz) and rejecting signal content above the voice band (e.g., 30 kilohertz and above). This “voice-only” signal can then be transmitted from the splitter  182  to a voice switch such a voice switch  19 . The other split signal can be transmitted from the splitter  182  to a DSLAM such as DSLAM  18 . For such an embodiment, it is assumed that the DSLAM or other digital multi-plexer that ultimately receives the composite signal will provide any required high-pass filter elements to remove the relatively low frequency voice content of the composite signal. In other embodiments, high pass filtration can be done at the splitters  182 . It will be appreciated that ISDN (integrated services digital network) filter circuits could also be used. Exemplary splitters/combiners incorporating low pass filters are sold by Vacuumschmelze GmbH of Germany. 
   It will be appreciated that signals are transmitted bi-directionally through the splitters  182 . Thus, signals transmitted from DSLAMs and voice switches to the splitters  182  are combined at the splitters  182  such that the signals can be simultaneously routed to a subscriber  25  through a single DSL  13 . 
   It is preferred for the splitter unit  50  to include test access devices that selectively provide test access through the test connector  90 . In the preferred embodiment, selective test access is provided by relay switches provided on the splitter cards  54  (see  FIG. 17 ). However, it will be appreciated that in other embodiments test access devices may be provided elsewhere within the splitter unit  50 . 
   Referring to  FIG. 17 , a splitter and relay switch schematic is provided. It will be appreciated that in the embodiment of  FIGS. 15 and 16 , separate relay switch configurations are provided for each of the 24 splitters provided on the splitter card  54 . However, for ease of explanation and clarity, only one of the splitters and its corresponding relay switch configuration are shown in  FIG. 17 . 
   Referring to  FIG. 17 , the splitter card  54  includes a LINE signal path  200  that extends from the card edge extension  113  to a splitter  182 . At the splitter  182 , the LINE signal path  200  splits into a VOICE signal path  202  that returns to the second card edge extension  113 , and a DATA signal path  204  that extends to the third card edge extension  114 . The splitter  182  includes a low pass filter  206  positioned along the VOICE signal path  202 . A mechanized loop test signature  208  is also positioned along the VOICE signal path  202 . While the various signal paths have been schematically depicted as single lines, since the system is preferably a twisted pair system, it will be appreciated that the single lines are each representative of a pair of paths. 
   An over voltage and overcurrent protector  210  is positioned along the LINE signal path  200  between the second card edge extension  113  and the splitter  182 . Test access devices are also provided along the LINE signal path  200  between the second card edge extension  113  and the splitter  182 . For example, the test access devices include a switching device  212  including two integral switches that are preferably concurrently actuated. The two switches include an upstream intrusive test switch  214  that opens and closes an upstream test access path  215 , and a downstream intrusive test switch  216  that opens and closes a downstream test access path  217 . The test access devices also include a monitor switch  218  that opens and closes a monitor test path  220 . 
   The switching device  212  and the switch  218  are controlled by a switch controller  230  provided on the circuit board  184 . The switch controller  230  preferably also controls all of the test access switches corresponding to the other 23 splitters which are not shown in  FIG. 17 . The switch controller  230  includes logic  232 , memory  234  and a driver  236 . 
   In  FIG. 17 , the switches  214 ,  216  and  218  are shown in their “normal” positions. The “normal” positions are the positions to which the switches  214 ,  216  and  218  return when not activated or when no power is being supplied to the splitter card  54 . When the switches  214 ,  216  and  218  are in their “normal” positions, the monitor test path  220 , the upstream test access path  215  and the downstream test access path  217  are open, and the switch  214  closes the LINE signal path  200  such that the LINE signal path  200  electrically connects the second card edge extension  213  to the splitter  182 . To provide upstream and downstream intrusive test access, the switches  214  and  216  are moved to activated positions as shown in  FIG. 22 . When the switch  214  is activated, the LINE signal path  200  between the splitter  182  and the second card edge extension  113  is broken, and the splitter  182  is electrically connected to the upstream test access path  215 . The upstream test access path  215  electrically connects to an upstream test bus  240  that extends to the first card edge extension  112 . When the switch  214  is actuated, the switch  216  is also preferably simultaneously actuated. By actuating switch  216 , the downstream test access path  217  is placed in electrical connection with the second card edge extension  113 . The downstream test access path  217  is electrically connected to a downstream test bus  242  that extends to the first card edge extension  112 . It will be appreciated that the test access switches corresponding to all of the splitters  182  are electrically connected to the upstream and downstream test buses  240  and  242  in the same manner as being representative test switches  214 ,  216  and  218  shown in  FIG. 17 . 
     FIGS. 18 and 19  show the CPU card  56  in isolation from the chassis  52 . The CPU card  56  includes a circuit board  400  having a front edge  402  and a rear edge  406 . A faceplate  408  is mounted at the front edge  402 . The faceplate  408  includes top and bottom latches  410  for securing the CPU card  56  within the chassis  52 . When the CPU card mounting location  72  is vacant, a blank cover similar to the cover  408  can be used to enclose the front of the CPU card mounting location  72 . 
   Referring to  FIG. 18 , the CPU card  56  includes a power/voltage converter  412  and a central processing unit  414  mounted on the circuit board  400 . As shown schematically in  FIG. 21 , tracings are provided for electrically connecting the voltage converter  412  and the central processing unit  414  to the card edge extensions  146 ,  148  provided at the rear edge  406  of the circuit board  400 . 
   A significant feature of the splitter unit  50  is that the splitters  182  of the splitter cards  54  are operational as telecommunications splitters regardless of whether the CPU card  56  is mounted in the CPU card mounting location  72  or not.  FIG. 20  schematically shows the splitter unit  50  with the CPU card mounting location  72  vacant. In this configuration, no power is provided to the splitter cards  54  and no CPU is present for controlling the switch controllers  230 . Therefore, with the CPU card mounting location  72  vacant, the test access switches  214 ,  216  and  218  assume their “normal” positions. With the switches  214 ,  216  and  218  in their “normal” positions as show in  FIG. 20 , no test access is provided. However, the line pathway  200  is closed such that the splitters  182  of the splitter cards  54  can still operate as passive splitters. For example, LINE signals can enter the splitter unit  50  through the LINE connector  76 , and travel through the LINE pathway  200  to the splitter  182 . At the splitter  182 , the signal is passively split thereby causing a VOICE signal to be routed out of the splitter unit  50  through the VOICE connector  78  and a DATA signal to be routed out of the splitter unit through the DATA connector  80 . Since the system is bi-directional, signals can also travel in the opposite direction. For example, signals input through the VOICE and DATA connectors  78  and  80  are combined at the splitter  182  and output through the LINE connector  76 . 
     FIG. 21  shows the splitter unit  50  with the CPU card  56  mounted at the CPU card mounting location  72 . In  FIG. 21 , a power source  500  is connected to the power connector  94 , the Ethernet  502  is connected to the Ethernet connector  98 , a personal computer  504  is connected to the serial port  100 , and a test head  506  connected to the auxiliary port  102  and the test head interface connector  90 . It will be appreciated that test heads are known in the art and are commercially available from companies such as Harris Corporation of Melbourne, Fla. (e.g., the Harris 107A/S test head) or Spirent Communications. 
   With the CPU card  56  mounted at the CPU card mounting location  72 , power from the power source  500  is routed through the voltage converter  412  of the CPU card  56  and to the splitter cards  54 . Also, by linking the Ethernet  502  to the CPU  414 , the switch controller  230  as well as the test head  506  can be controlled from a remote location. The personal computer  504  is linked to the CPU  414  to provide local control of the switch controllers  230  and the test head  506 . The test head  506  is linked to the CPU through the auxiliary port  102 . The presence of the CPU card  56  in the CPU card mounting location  72  allows a user to remotely or locally activate the switches  214 ,  216  and  218  when test access is desired or required. 
   In  FIG. 21 , the switches  214 ,  216  and  218  are still in their “normal” positions.  FIG. 22  shows the switches  214  and  216  in activated positions. The switches can be activated by the switch controller  230  in response to control signals from the CPU  414 . When the switches  214  and  216  are activated, intrusive upstream and downstream test access are provided. In other words, when the switches  214  and  216  are actuated, the LINE pathway  200  between the LINE connector  76  and the splitter  182  is broken, and the splitter  182  is instead linked to the test head  506  to provide upstream test access (see  FIG. 22 ). Concurrently, the LINE connector  76  is also linked to the test head  506  to provide downstream test access (see  FIG. 22 ). 
     FIG. 23  shows the switches  214  and  216  in their normal positions, and the switch  218  in the activated position. The switch  218  can be activated in response to control commands received by the switch controller  230  from the CPU  414 . With the switch  218  activated, the monitor test path allows a monitor level signal to be provided to the test head  506  by the downstream bus  240 . 
   It has been appreciated by the inventors that the configuration of the splitter unit  50  has advantages in the marketplace. Often, service providers prefer to defer as many costs as possible. When setting up an initial splitter system, it is sometimes not necessary to immediately provide test access. By providing a system that can operate as a passive splitter system without the presence of a CPU card, the cost of the CPU card and related firmware, hardware or software can be deferred until test access is desired or required. At the time test access is desired or required, it is not necessary to replace the existing splitter system or add a separate test access device to the system. Instead, the service provider need only purchase the CPU card which immediately upgrades the system from a passive splitter system to a splitter system with integral remote test access.