Abstract:
A switched capacitor circuit  300 , including a sampling capacitor  303 , switches  301, 304  for charging the sampling capacitor  303  during a charging phase, and switches  302, 305  for transferring charge from the sampling capacitor  303  to a load  313  in the feedback loop of an operational amplifier  312  during a dump phase. Circuitry  701  controls the discharge of sampling capacitor  303  during the dump phase to minimize transients at the input of the operational amplifier  312  and thereby minimize input threshold voltage variation.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to switched-capacitor techniques and in particular to switched-capacitor circuits with reduced distortion in the transfer function. 
     2. Description of the Related Art 
     Delta-sigma modulators are particularly useful in digital to analog and analog to digital converters (DACs and ADCs). Using oversampling, the delta-sigma modulator spreads the quantization noise power across the oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally; the delta sigma modulator-performs noise shaping by acting as a lowpass filter to the input signal and a highpass filter to the noise; most of the quantization noise power is thereby shifted out of the signal band. 
     The typical delta sigma modulator includes a summer summing the input signal with negative feedback, a linear filter, quantizer and a feedback loop with a digital to analog converter coupling the quantizer output and the inverting input of the summer. In a first order modulator, the linear filter comprises a single integrator stage while the filter in higher a order modulator comprises a cascade of a corresponding number of integrator stages. The quantizer can be either a one-bit or a multiple-bit quantizer. Higher-order modulators have improved quantization noise transfer characteristics over those of lower order, although stability becomes a more critical design factor as the order increases. 
     Switched-capacitor filters/integrators are useful in a number of applications, including the integrator stages in delta sigma modulators. Generally, in a basic singled-ended switched-capacitor integrator, the input signal is sampled by switches onto a sampling capacitor during the sampling (charging) phase. A reference voltage may also be sampled onto a reference sampling capacitor during this phase. During the following dump phase, the charge on the sampling capacitor(s) is transferred at the summing node of a operational amplifier to the integrator capacitor in the amplifier feedback loop. The operational amplifier drives the integrator output. 
     During the dump phase, transients of up to a few volts can occur at the summing nodes. These relatively high voltages can cause the threshold voltage of the MOSFETs at the operational amplifier inputs to temporarily vary from the expected nominal threshold voltages. Consequently, an offset is introduced at the inputs of the operational amplifier which can in turn cause distortion in the circuit transfer function. In high performance applications, this distortion may not be acceptable. Hence, techniques are required for minimizing summing node transients in switched capacitor circuits, especially those switched capacitor circuits used in high performance applications where minimization of distortion is desirable. 
     SUMMARY OF THE INVENTION 
     The principles of the present invention address the problem of variation in the input threshold voltage of an operational amplifier and in particular, operational amplifiers used in switched capacitor circuits. 
     According to one embodiment of these principles, a switched-capacitor circuit is disclosed includes a sampling capacitor, switches for charging the sampling capacitor during a charging phase, and switches for transferring charge from the sampling capacitor to a load in a feedback loop of an operational amplifier during a dump phase. Circuitry is provided for controlling discharge of the sampling capacitor during the dump phase to minimize transients at the input of the operational amplifier and thereby minimize input threshold voltage variation. 
     Thus, according to the inventive principles, the input transients at the operational amplifier inputs are substantially reduced and consequently input threshold voltage variation is also reduced. Ultimately, the reduction in input threshold voltage variation reduces distortion in the amplifier output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a high level functional block diagram of an analog to digital converter suitable for illustrating the application of the inventive principles; 
     FIG. 2 is a functional block diagram of an exemplary  5   th  order delta-sigma modulator suitable for use in circuits and systems such as the analog to digital converter shown in FIG. 1; 
     FIG. 3 is an electrical schematic diagram of a switched capacitor integrator embodying the inventive principles; 
     FIG. 4 is a timing diagram illustrating the relationship between the control signals shown in FIG. 3; 
     FIG. 5 is an electrical schematic diagram of first sampling capacitor discharge control circuitry according to the inventive principles; 
     FIG. 6 is an electrical schematic diagram of second sampling capacitor discharge control circuitry according to the inventive principles; and 
     FIG. 7 is an electrical schematic diagram of third sampling capacitor discharge control circuitry according to the inventive principles. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted in FIGS. 1-7 of the drawings, in which like numbers designate like parts. 
     FIG. 1 is a high level functional block diagram of a single-chip audio analog-to-digital (A/D)  100  suitable for practicing the principles of the present invention. A/D converter  100  is only one of a number of possible applications employing delta-sigma modulators. Other examples include digital to analog converters (DACs) and Codecs. 
     A/D converter  100  includes two conversion paths for converting left and right channel analog audio data respectively received at left and right analog differential inputs AINL+/− and AINR+/−. The analog inputs are each passed through an input gain stage  101  and then to a  5 th order delta-sigma modulator. 
     Each delta-sigma modulator is represented in FIG. 1 by a summer  102 , low-pass filter  104 , comparator (quantizer)  105  and DAC  106  in the feedback loop. The outputs from the delta-sigma modulators are passed through a decimation filter  107 , which reduces the sample rate, and a low pass filter  108 . The delta sigma modulators sample the analog signal at the oversampling rate and output digital data in either single-bit or multiple-bit form, depending on the quantization, at the oversampling rate. The resulting quantization noise is shaped and generally shifted to frequencies above the audio band. 
     The resulting left and right channel digital audio data are output through a single serial port SDOUT of serial output interface  109 , timed with serial clock SCLK and left-right clock LRCLK in accordance with the Digital Interface Format (DIF). The SCLK and LRCLK clocks can be generated externally and input to converter  100  or can be generated on-chip, along with the associated data, in response to a received master clock MCLK. 
     FIG. 2 is an exemplary  5 th order delta-sigma modulator  200  comprising an input summer  201  and  5  integrator stages  202   a,e . Delta sigma modulator  200  is of a weighted feed-forward design in which the outputs of each of the integrator stages are passed through a gain stage (amplifier)  203   a,e  to summer  205 . Amplifiers  203   a,e  allows the outputs of the integrator stages to be weighted at the summer  204  input. The output from summer  204  is quantized by a multiple-bit.quantizer  205  which provides the multiple-bit digital output signal. Additionally, the output from quantizer  205  is feedback to the inverting input of summer  201  through digital to analog converter  207 . (A 5th order feed-forward design was selected for describing the application of the inventive concepts; in actual implementations the order as well as the configuration of the modulator will vary.) 
     FIG. 3 is an electrical schematic diagram of a typical switched capacitor integrator  300  suitable for the first stage of delta sigma modulator  200 . Generally, the first integrator stage of a delta- sigma modulator is the most critical to setting the distortion performance and therefore will be the focus of the following discussion. It should be noted however that the concepts discussed below are useful in a number of switched capacitor applications, including various delayed and undelayed switched capacitor integrators. 
     Switched capacitor integrator  300  operates in two non-overlapping phases φ 1  and φ 2  per sample. This timing is shown in FIG.  4 . As will be discussed further, in the preferred embodiment each phase is composed of rough and fine subphases (φ 1R , φ IF , φ 2R , φ 2F ). In the general case, during Phase  1  (φ 1 ) switches  301   a-d  and  304   a,b  close and the differential input voltage V IN  is sampled onto input sampling capacitors (C IN )  303   a,b . Switches  302   a,d  and  305   a,b  are open during φ 1 . 
     Also during φ 1 , the differential reference signal V REF  on to reference sampling capacitors (C REF )  306   a,b  by switches  307   a,d  and  308   a,b . Switches  309   a,d  and  310   a,b  are open during Phase  1 . Switches  311   a,d  under the control of the complementary bits D and /D from the 1-bit data output from the quantizer couple or cross-couple reference sampling capacitors C REF    306   a,b  to the inverting and non-inverting summing inputs to op amp  312 . 
     During Phase  2  (φ 2 ) the switches reverse their configuration with switches  302   a,d  and  305   a,b  closing and switches  301   a,d  and  304   a,b  opening for the input path. For the reference path, switches  307   a,d  and  308   a,b  open and switches  309   a,d  and  310   a,b  close. Consequently, the charge on input and reference sampling capacitors C IN  and C REF  is transferred to the inverting (−) and non-inverting (+) inputs of opamp  312  (the summing nodes) and integrator capacitors (C 1 )  313   a,b.    
     As previously noted, in the preferred integrator  300  operates in rough and fine subphases. During the rough subphase of Phase  1  (φ 1R ), the input plates P of sampling capacitors C IN  and C REF  are driven by rough buffers  314   a,c  and  315   a,d  which provide an increased charging current. Subsequently, these plates are brought to their full sampling voltage during the Phase  1  fine subphase (φ 1F ) by direct coupling to the corresponding input or reference voltage. More importantly, during phase  2  charge dumping, rough buffers  314  and  315  provide increased drive during the rough subphase (φ 2R ) to rapidly slew the voltage on capacitor input plates P towards the opposite voltage to transfer the sampled charge to plates P′ and integration capacitors C IN . The charge transfer is completed during the Phase  2  fine subphase (φ 2F ) by direct coupling of capacitor input plates P to the appropriate input. 
     Without special efforts, large transients can develop at the summing nodes during Phase  2 . Specifically, during the initial charge dump, the inputs of the opamp will attempt to follow different voltages, depending on the complementary charges on sampling capacitors C IN  and C REF . These voltages can be on the order of a few volts depending on the values of V REF +/ − and V IN +/. Relatively large voltages such as these can cause a temporary variation in the threshold voltage (V t ) of the MOSFETs at the opamp inputs. Specifically, the V t  of a given MOSFET subjected to a relatively high gate to source voltage (V gs ) may develop a “memory” and accordingly vary. This variation in V t  effectively acts as a signal dependent offset between the differential inputs of the opamp to which the opamp settles at the end of the dump stage. Consequently, a signal dependant residual charge remains on capacitors C IN  and C REF , resulting in distortion at the integrator output. 
     The present inventive concepts advantageously address this problem by reducing the voltage transients appearing at the opamp summing nodes to a few hundred millivolts or less. 
     According to a first embodiment, a resistor R IN  ( 501 ) is inserted in series with each input sampling capacitor C IN  and/or a resistor R REF . ( 502 ) is provided in series with each reference voltage sampling capacitor C REF . This is illustrated in FIG.  5 . The resistors in the reference voltage paths are particularly advantageous since the reference sampling capacitors C REF  normally provide a larger charge dump. Resistors R IN  and R REF  lengthen the time constant of the capacitor discharge phase and limit the current such that the discharge does not exceed the slew rate of the opamp. Although these resistors are shown in front of the capacitors in FIG. 5, they may also follow the capacitors without deviating from the basic principles of the invention. 
     This can also be done by replacing resistors with current limiting devices such as MOSFETs  601  and  602  biased in saturation, as shown in FIG.  6 . The current in this case is maintained below the slew capability of opamp  312  such that the opamp will remain in the small signal settling mode. 
     FIG. 7A illustrates a further embodiment in which the switches  305   a,b  and/or switches  310   a,b  are replaced by a pass-gate formed by a pair of switches (transistors)  701  and  702 . Here, switch  701  is smaller and has a higher impedance than switch  702  which is larger and has a lower impedance. During the Phase  2 , switches  701  and  702  are alternatively turned-on the rough (φ 2R ) and fine sub-phases (φ 2F ). Specifically, during the rough dump phase ( 100   2R ), smaller, higher impedance switch  701  is used to discharge the associated sampling capacitors to the summing nodes with a longer time constant to allow the opamp to settle. During the subsequent fine phase, larger, lower impedance resistor  702  is used to complete the charge transfer. (As an alternative, switches  701  and  702  can be made of equal size and a resistance added in series with switch  701  to achieve the same effect). 
     In a further application of the inventive concepts, rough buffers  314  are designed such that the drive sampling capacitors C IN  and C REF  at a slew rate less than the slew rate of the opamp. In other words: 
       S   IN   +S   REF   ≦S   AMP   
     where in S IN  is the maximum slew rate (dV/dt) Max  of the rough buffer of one differential input signal path, S REF  is the maximum slew rate (dV/dt) Max  of the rough buffer of one differential reference signal path and S AMP  is the maximum slew rate of the opamp (dV/dt) Max  Under these constraints, the summing node voltages at the inputs to the opamp to not transition faster than the opamp can settle them. Consequently, spikes and similar transients are substantially reduced or eliminated such that the threshold voltages of the opamp input transistors do not vary significantly. 
     In sum, the present concepts address the problem of distortion caused by transient-induced offsets at the input of the opamp. Specifically, by substantially reducing or eliminating transients at the summing nodes during the charge dump phase, variation in the threshold voltages of the opamp input transistors is controlled. In turn, voltage offset between the opamp inputs are minimized which reduces the output distortion caused by residual charge on the integration capacitors. 
     Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.