Abstract:
A semiconductor device includes a substrate; a semiconductor region formed on the substrate; and a silicide layer as a contact layer formed directly contacting the semiconductor region; wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered and a method for making a semiconductor device which has the steps of: forming selectively a given conductive type semiconductor region on a substrate; forming a Co—Si alloy layer on the entire surface of the semiconductor region; introducing Si into the entire surface or part of the Co—Si alloy layer; and conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to a semiconductor device, and more particularly to, a semiconductor device that uses a layer of silicide, which is an intermetallic compound of silicon and metals, as the contact layer which directly contacts a semiconductor region such as source and drain, and also relates to a method for making the semiconductor device.  
         BACKGROUND OF THE INVENTION  
         [0002]    In memories and LSI(large-scale integrated circuit) such as a microprocessor, which are known as the representative of semiconductor devices, the dimensions of device have been increasingly fine-structured with an increase in integration density. Also, the semiconductor region to compose the device has been formed shallower. Further, when forming a contact in semiconductor region, the size of contact hole to be formed in interlayer dielectric film has been also limited.  
           [0003]    For example, in recent LSI that is composed of MOS (metal oxide semiconductor), when forming a contact in semiconductor region composed of a source region and a drain region, the size of the contact hole to be formed in the interlayer dielectric film is designed to be a fine value of less than 0.4 μm (in diameter). As the contact hole is fine-structured like this, the kind of materials for upper wiring layer that can be formed well-adhesive to the contact hole is limited. Tungsten (W) is known as one of the excellent wiring materials applicable to such object.  
           [0004]    Here, when forming a contact in semiconductor region, if a wiring material of tungsten is adhered directly to the semiconductor region, the contact characteristic is deteriorated due to the reaction of the semiconductor region and tungsten. To prevent this, a high-melting-point metal layer to function as the barrier layer has been laid between them. As the high-melting-point metal layer, a two-layer film of Ti/TiN with excellent barrier performance is generally used. Ti (titanium) is formed on the semiconductor region side and TiN (nitride-titanium) is formed on the tungsten side. Tungsten has a characteristic easy to adhere to TiN.  
           [0005]    Also, in the case of forming a contact in a shallow semiconductor region, an increase in contact resistance becomes an issue. It is known that to form a silicide layer such as Co—Si alloy (CoSi 2 ), a silicide compound, on the surface of the semiconductor region is effective in restraining the contact resistance from increasing.  
           [0006]    Problems occurred when the contact resistance increases are explained below. FIG. 1 is an illustrative cross sectional view showing the electrode part of a MOS transistor composing LSI. In FIG. 1, 101 is a Si substrate,  102  is a source region,  104  is a channel region,  105  is a gate oxide film,  106  is a sidewall oxide film,  107  is a gate electrode,  108  is an interlayer dielectric film,  109  is a contact hole,  110  is a barrier layer compose of two-layer film of Ti/TiN,  111  is a wiring layer of tungsten, and  112  is an upper wiring layer of Al-system metal.  
           [0007]    Here, the resistance parasitic to the current path when the MOS transistor is turned on is classified into components listed below.  
           [0008]    Rc: resistance inside the contact hole (in this case, a resistivity of tungsten, which is reversely proportional to the square of the diameter of contact hole)  
           [0009]    Rx: contact resistance of the barrier layer and the silicide layer (reversely proportional to the square of the diameter of contact hole)  
           [0010]    Rs: resistance of the silicide layer  
           [0011]    Rms: contact resistance of the silicide layer and the source/drain region  
           [0012]    Rch: channel resistance  
           [0013]    The total resistance Rt when the MOS transistor is turned on is given by expression 1:  
             Rt= 2 Rc+ 2 Rx+ 2 Rs+ 2 Rms+Rch   [1] 
           [0014]    The contact resistance Rco is given by expression  2 :  
             Rco=Rc+Rx   [2] 
           [0015]    In FIG. 1, as the dimensions of the MOS transistor decrease with an increase in integration density of LSI, especially Rx abruptly increases in reverse proportion to the square of the diameter of contact hole, and therefore the contact resistance Rco increases based on expression 2. Along with this, the total resistance Rt increases based on expression 1 and thereby on-current decreases. Therefore, a problem occurs in that the operation speed of the entire LSI is lowered. This is because the amount of electric charge supplied to the next-stage element (transistor) decreases due to the decrease in on-current.  
           [0016]    Semiconductor devices where a silicide layer composed of Co—Si alloy layer is formed in its semiconductor region so as to restrain the contact resistance from increasing are, for example, disclosed in Japanese patent application laid-open No.7-78788 (1995), and H. Kawaguchi et al., “A Robust 0.15 μm CMOS Technology with CoSi 2  Salicide and Shallow Trench Isolation”, 1997 Symposium on VLSI Technology Digest of Technical Papers 9B-4 (1997) pp.125-126.  
           [0017]    [0017]FIG. 2 shows an example of semiconductor device described in Japanese patent application laid-open No.7-78788. Between a lower conductor region  202  as source/drain region formed in a semiconductor substrate  200  and an upper wiring layer  206  formed on insulating layers  204 A,  204 B on a gate electrode  220  to cover the lower conductor region  202 , there is provided electrical connection through a connection hole (intermediate conductor layer)  208 . The connection hole  208  is composed of a monocrystal CoSi 2  (Co—Si alloy) layer  210  formed on the surface of the lower conductor region  202 , a tungsten layer  214  as a wiring material deposited (buried) in a contact hole  212  formed in the insulating layers  204 A,  204 B, and a monocrystal TiN layer  216  formed between the layers  210  and  214 . Here, the monocrystal TiN layer  216  functions as a barrier layer to control the reaction of the lower conductor region  202  and the tungsten layer  214 . Under the upper wiring layer  206 , there is formed a barrier layer  218  of two-layer film of Ti, TiON from below.  
           [0018]    However, in the conventional technique described in Japanese patent application laid-open No.7-78788, there is a problem that the silicide layer of Co—Si alloy layer used as the contact layer does not sufficiently play a role to suppress an increase in contact resistance (Rx). This is because the Si content of the Co—Si alloy layer or a Co—Si—Ti alloy layer to be formed through the reaction of the Co—Si alloy layer and Ti as the component of the barrier layer formed on the Co—Si alloy layer is small.  
         SUMMARY OF THE INVENTION  
         [0019]    Accordingly, it is an object of the invention to provide a semiconductor device that the contact resistance of silicide layer used as a contact layer can be sufficiently restrained from increasing, thereby restraining the on-current from reducing and enhancing the operation speed.  
           [0020]    It is an object of the invention to provide a method for making such a semiconductor device.  
           [0021]    According to the invention, a semiconductor device, comprising:  
           [0022]    a substrate;  
           [0023]    a semiconductor region formed on the substrate; and  
           [0024]    a silicide layer as a contact layer formed directly contacting the semiconductor region;  
           [0025]    wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered.  
           [0026]    According to another aspect of the invention, a method for making a semiconductor device, comprising the steps of:  
           [0027]    forming selectively a given conductive type semiconductor region on a substrate;  
           [0028]    forming a Co—Si alloy layer on the entire surface of the semiconductor region;  
           [0029]    introducing Si into the entire surface or part of the Co—Si alloy layer;  
           [0030]    forming a Ti-included layer in part of the Co—Si alloy layer; and  
           [0031]    conducting the thermal treatment of the substrate to react the introduced Si with the Co—Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0032]    The invention will be explained in more detail in conjunction with the appended drawings, wherein:  
         [0033]    [0033]FIG. 1 is an illustrative cross sectional view showing a conventional semiconductor device for explaining a problem occurring when the contact resistance increases,  
         [0034]    [0034]FIG. 2 is a cross sectional view showing another conventional semiconductor device,  
         [0035]    [0035]FIG. 3 is a cross sectional view showing a semiconductor device in a first preferred embodiment according to the invention,  
         [0036]    [0036]FIG. 4 is a characteristic diagram showing the reduction effect of contact resistance of the semiconductor device in the first embodiment,  
         [0037]    [0037]FIG. 5 is a characteristic diagram showing the reduction effect of contact resistance of the semiconductor device in the first embodiment,  
         [0038]    FIGS.  6  to  16  are cross sectional views showing a method for making the semiconductor device in a second preferred embodiment according to the invention,  
         [0039]    [0039]FIG. 17 is a cross sectional view showing a method for making a semiconductor device in a third preferred embodiment according to the invention,  
         [0040]    [0040]FIGS. 18 and 19 are cross sectional views showing a method for making a semiconductor device in a fourth preferred embodiment according to the invention,  
         [0041]    [0041]FIG. 20 is a cross sectional view showing a method for making a semiconductor device in a fifth preferred embodiment according to the invention, and  
         [0042]    [0042]FIG. 21 is a cross sectional view showing a method for making a semiconductor device in a fifth preferred embodiment according to the invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0043]    The preferred embodiments of the invention will be explained below, referring to the drawings. The explanations are concretely made using the embodiments.  
         [0044]    [Embodiment 1] 
         [0045]    [0045]FIG. 3 is a cross sectional view showing a semiconductor device in the first preferred embodiment of the invention.  
         [0046]    The semiconductor device in this embodiment, as shown in FIG. 3, relates to a semiconductor device with a complementary MOS IC composition. It is composed of a p-channel type MOS transistor  2  and a n-channel type MOS transistor  3  that are formed on a semiconductor substrate  1  of p-type monocrystal silicon through a device isolation oxide film  19 , and an interlayer dielectric film to cover the surface of the transistors  2 ,  3 .  
         [0047]    In the p-channel type MOS transistor  2 , a p + -type source region  5  and a p + -type drain region  6  are formed in an n-type well  4  formed on the semiconductor substrate  1 , and a gate electrode  9  of polycrystal Si with a thickness of 100 to 300 nm is formed on the surface of a channel region  7  between the regions  5 ,  6  through a gate oxide film  8  of 2 to 5 nm thick. On the gate electrode  9 , a silicide layer  10  of Co—Si alloy layer is formed. The side of the gate electrode  9  is covered with sidewall oxide film  11  of 50 to 200 nm thick. A p − -type LDD (lightly doped drain) region  21  is formed adjacent to the p + -type source region  5  and the p + -type drain region  6 .  
         [0048]    On the entire surface of the p + -type source region  5  and the p + -type drain region  6 , the silicide layer  10  of Co—Si alloy layer is formed, and a Si-rich silicide layer  12  of Co—Si—Ti alloy layer is selectively formed in the silicide layer  10 . The Si-rich silicide layer  12  is made to be rich in Si while including such a Si amount that the contact resistance is significantly lowered.  
         [0049]    At the region where the silicide layer  12  is formed in the interlayer dielectric film  20 , a contact hole  13  is formed. On the side and bottom of the contact hole  13 , a two-layer barrier layer  14  of Ti (of about 50 nm thick)/TiN (of about 50 nm thick), where the Ti layer is located on the silicide layer  12  side, is formed to connect with the silicide layer  12 . Also, a wiring layer  15  of tungsten is formed in the contact hole  13  to connect with the barrier layer  14 .  
         [0050]    On the wiring layer  15 , a barrier layer  16  of TiN (with a thickness of about 50 nm) is formed to connect with the barrier layer  14 , and an upper wiring layer  17  of AlCu etc. is formed on the barrier layer  16 . On the upper wiring layer  17 , an anti-reflective coating  18  of TiN with a thickness of 200 to 500 nm is formed. The anti-reflective coating  18 , which is necessary for a stage of the manufacturing process, is finally left as it is.  
         [0051]    On the other hand, in the n-channel type MOS transistor  3 , a n + -type source region  25  and a n + -type drain region  26  are formed in a p + -type well  24  formed on the semiconductor substrate  1 , and a gate electrode  29  of polycrystal Si with a thickness of 100 to 300 nm is formed on the surface of a channel region  27  between the regions  25 ,  26  through a gate oxide film  28  of 2 to 5 nm thick. On the gate electrode  29 , a silicide layer  30  of Co—Si alloy layer is formed. The side of the gate electrode  29  is covered with sidewall oxide film  31  of 50 to 200 nm thick. A n − -type LDD region  22  is formed adjacent to the n + -type source region  25  and the n + -type drain region  26 .  
         [0052]    On the entire surface of the n + -type source region  25  and the n + -type drain region  26 , the silicide layer  30  of Co—Si alloy layer is formed, and a Si-rich silicide layer  32  of Co—Si—Ti alloy layer is selectively formed in the silicide layer  30 . The Si-rich silicide layer  32  is made to be rich in Si while including such a Si amount that the contact resistance is significantly lowered.  
         [0053]    At the region where the silicide layer  32  is formed in the interlayer dielectric film  20 , a contact hole  33  is formed. On the side and bottom of the contact hole  33 , a two-layer barrier layer  34  of Ti (of about 50 nm thick)/TiN (of about 50 nm thick), where the Ti layer is located on the silicide layer  32  side, is formed to connect with the silicide layer  32 . Also, a wiring layer  35  of tungsten is formed in the contact hole  33  to connect with the barrier layer  34 .  
         [0054]    On the wiring layer  35 , a barrier layer  36  of TiN (with a thickness of about 50 nm) is formed to connect with the barrier layer  34 , and an upper wiring layer  37  of AlCu etc. is formed on the barrier layer  36 . On the upper wiring layer  37 , an anti-reflective coating  38  of TiN with a thickness of 200 to 500 nm is formed. The anti-reflective coating  38 , which is necessary for a photolithography stage of the manufacturing process, is finally left as it is.  
         [0055]    When the Si-rich silicide layer  12  of the p-channel type MOS transistor  2  and the Si-rich silicide layer  32  of the n-channel type MOS transistor  3  are formed in the contact hole with a diameter of about 0.2 μm, Si with a dose amount of about 5×10 15  cm −2  is included in the Si-rich silicide layers  12 ,  32 .  
         [0056]    [0056]FIG. 4 is a characteristic diagram showing the reduction effect of contact resistance due to the Si-rich silicide layer  32  that is formed in the n + -type source region  25  and the n + -type drain region  26  of the n-channel type MOS transistor  3 . The vertical axis indicates contact resistance on the regions  25 ,  26  and the horizontal axis indicates contact hole sizes (diameter, μm). In FIG. 4, curve a represents a characteristic obtained when the Si-rich silicide layer  32  is formed, and curve b represents a characteristic obtained when the Si-rich silicide layer  32  is not formed. Meanwhile, curve a represents the case that the ion-implantation (I/I) of Si is conducted on the conditions of acceleration energy of 5 keV and dose amount of 5×10 15  cm −2  so as to make it to be rich in Si.  
         [0057]    [0057]FIG. 5 is a characteristic diagram obtained, based on the characteristic diagram in FIG. 4, when the contact hole size is specified to have a diameter of about 0.2 μm, where the vertical axis indicates contact resistance and the horizontal axis indicates the conditions of ion-implantation (acceleration energy and dose amount) Apparent from FIGS. 4 and 5, by ion-implanting Si to a contact hole with a diameter of about 0.2 μm with a dose amount of about 5×10 15  cm −2  to form the Si-rich silicide layer, the contact resistance can be reduced to 15 to 17 Ω.  
         [0058]    Also, apparent from FIG. 4, even when the contact hole size is fine-structured to have a diameter less than about 0.27 μm, the contact resistance can be significantly reduced by forming the Si-rich silicide layer by the method in this embodiment.  
         [0059]    Although the characteristic diagrams in FIGS. 4 and 5 are shown for the example that the Si-rich silicide layer  32  that is formed in the n + -type source region  25  and n + -type drain region  26  of the n-channel type MOS transistor  3 , the contact resistance can be similarly reduced when the Si-rich silicide layer  12  that is formed in the p + -type source region  5  and p + -type drain region  6  of the p-channel type MOS transistor  2 .  
         [0060]    As described above, in this embodiment, the Si-rich silicide layers  12 ,  32  of Co—Si—Ti alloy layer each are formed in the p + -type source region  5  and p + -type drain region  6  of the p-channel type MOS transistor  2 , and in the n + -type source region  25  and n + -type drain region  26  of the n-channel type MOS transistor  3 . Thereby, the amount of Si included in the respective silicide layers  12 ,  32  can be made rich. Therefore, the respective silicide layers  12 ,  32  can sufficiently play a role to suppress an increase in contact resistance.  
         [0061]    Accordingly, the contact resistance of the silicide layer used as a contact layer can be restrained from increasing, and therefore the on-current can be prevented from reducing. As a result, the operation speed of the semiconductor device can be enhanced.  
         [0062]    [Embodiment 2] 
         [0063]    FIGS.  6  to  16  are cross sectional views showing, in the order of processes, a method of making a semiconductor device in the second preferred embodiment of the invention. For the semiconductor device in the first embodiment, the method in the second embodiment is explained below in the order of the processes.  
         [0064]    First, as shown in FIG. 6, by using the semiconductor substrate  1  of p-type monocrystal silicon and applying a well-known partial oxidation technique to that, the device isolation oxide film  19  to isolate regions for forming MOS transistors is formed. Then, as shown in FIG. 7, while masking the region for forming the n-channel type MOS transistor on the semiconductor substrate  1  by photoresist  40 , a n-type impurity such as phosphor (P) and arsenic (As) is, as shown by arrows, ion-implanted into the region for forming the p-channel type MOS transistor, thereby forming the n-type well  4 . Then, as shown in FIG. 8, while masking the region for forming the p-channel type MOS transistor on the semiconductor substrate  1  by photoresist  40 , a p-type impurity such as boron (B) is, as shown by arrows, ion-implanted into the region for forming the n-channel type MOS transistor, thereby forming the p-type well  24 .  
         [0065]    Then, as shown in FIG. 9, by conducting the thermal oxidation of the semiconductor substrate  1 , the gate oxide film  8 ,  28  of 2 to 5 nm thick is formed in the region enclosed by the device isolation oxide film  19 . Then, polycrystal Si film of 100 to 300 nm thick is formed on the gate oxide film  8 ,  28  by CVD (chemical vapor deposition), and then the gate electrodes  9 ,  29  are formed by removing unnecessary part by photolithography.  
         [0066]    Then, as shown in FIG. 10, using an impurity source such as BF 2 , boron is ion-implanted, as shown by arrows, into the region for forming the p-channel type MOS transistor on the semiconductor substrate  1  on the conditions of acceleration energy of  3  to  7  keV and dose amount of 5×10 13  to 1×10 14  cm −2 , thereby forming the p − -type LDD region  21  in the n-type well  4 .  
         [0067]    Then, arsenic is ion-implanted, as shown by the arrows, into the region for forming the n-channel type MOS transistor on the semiconductor substrate  1  on the conditions of acceleration energy of 10 to 20 keV and dose amount of 1×10 14  to 1×10 15  cm −2 , thereby forming the n − -type LDD region  22  in the p-type well  24 . These p − -type LDD region  21  and n − -type LDD region  22  can be sequentially formed in two steps by using the photoresist mask  40  described earlier.  
         [0068]    Then, as shown in FIG. 11, oxide film of 50 to 200 nm thick is formed on the semiconductor substrate  1  by CVD, then removing unnecessary part by etch back, forming the sidewall oxide films  11 ,  31  on the side of the gate electrodes  9 ,  29 .  
         [0069]    Then, as shown in FIG. 12, using an impurity source such as BF 2 , boron is ion-implanted, as shown by arrows, into the region for forming the p-channel type MOS transistor on the conditions of acceleration energy of 10 to 40 keV and dose amount of 1×10 15  to 6×10 15  cm −2 . Then, arsenic is ion-implanted, as shown by the arrows, into the region for forming the n-channel type MOS transistor on the conditions of acceleration energy of 20 to 70 keV and dose amount of 1×10 15  to 6×10 15  cm −2 . Then, the semiconductor substrate  1  is annealed at 900 to 1100° C. for 5 to 30 sec. in N 2  atmosphere to raise the expansion-diffusing of boron and arsenic ion-implanted as described above, thereby forming the p + -type source region  5  and p + -type drain region  6 , and the n + -type source region  25  and n + -type drain region  26 .  
         [0070]    Then, as shown in FIG. 13, on the entire surface of the p + -type source region  5  and p + -type drain region  6 , and on the entire surface of the n + -type source region  25  and n + -type drain region  26 , further on the gate electrodes  9 ,  29 , the silicide layers  10 ,  30  of Co—Si layer are formed. In detail, first, the semiconductor substrate  1  is pretreated with hydrofluoric acid, then forming Co of 5 to 20 nm thick on the entire surface by sputtering. Then, by annealing at 600 to 700° C. for 10 to 60 sec. in N 2  atmosphere, Co reacts with Si and, thereby, the silicide layers  10 ,  30  of Co—Si alloy layer are formed. Then, the semiconductor substrate  1  is treated with a mixed solution of H 2 SO 4  (sulfuric acid) and H 2 O 2  (hydrogen peroxide) to remove excessive Co, then annealing at 750 to 900° C. for 5 to 20 sec. in N 2  atmosphere again, thereby forming the complete silicide layers  10 ,  30  of Co—Si alloy layer.  
         [0071]    Then, as shown in FIG. 14, Si is ion-implanted, as shown by arrows, to the entire surface of the semiconductor substrate  1  on the conditions of acceleration energy of 1 to 20 keV and dose amount of 5×10 14  to 7×10 15  cm −2 .  
         [0072]    Then, at part of the silicide layer  10  of Co—Si alloy layer on the entire surface of the p + -type source region  5  and p + -type drain region  6 , and at part of the silicide layer  10  of Co—Si alloy layer on the entire surface of the n + -type source region  25  and n + -type drain region  26 , the Si-rich silicide layers  12 ,  32  of Co—Si—Ti alloy layer are formed. In detail, first, the interlayer dielectric film  20  is formed on the entire surface of the semiconductor substrate  1  by CVD, and then part of the film is removed by photolithography to expose part of the silicide layers  10 ,  30  to open the contact holes  13 ,  33 . Then, Ti of about 500 Å thick and TiN of about 500 Å thick are sequentially formed on the interlayer dielectric film  20  including the contact holes  13 ,  33  by sputtering, thereby forming the two-layer barrier layers  14 ,  34  of Ti/TiN, where Ti is located downside. Then, by annealing at 650 to 850° C. for 10 to 60 sec. in N 2  atmosphere, Si, which is ion-implanted as described earlier, reacts with Ti of the silicide layers  10 ,  30  of Co—Si alloy layer and of the two-layer barrier layers  14 ,  34  of Ti/TiN and, thereby, the silicide layers  12 ,  32  of Co—Si—Ti alloy layer are formed.  
         [0073]    Then, as shown in FIG. 16, the wiring layers  15 ,  35  of tungsten are formed in the contact holes  13 ,  33  to connect with the barrier layers  14 ,  34 . In detail, first, by CVD using tungsten hexafluoride (WF6) as an impurity source, at a substrate temperature of  400  to 500° C., tungsten is formed on the barrier layers  14 ,  34  including the contact holes  13 ,  33 . Then, by CMP (chemical mechanical polishing), the barrier layers  14 ,  34  and tungsten on the interlayer dielectric film  20  are removed thereby flattening the surface. Thereby, the wiring layers  15 ,  35 , with tungsten only in the contact holes  13 ,  33 , are formed.  
         [0074]    Then, as shown in FIG. 16, the TiN layer  16   a  of about 50 nm thick, the AlCu layer  17   a  of 400 to 600 nm thick and the TiN layer  18   a  of 20 to 50 nm thick are sequentially formed on the entire surface of the interlayer dielectric film  20 , by sputtering. Then, patterning by photolithography using reactive ion etching, the semiconductor device shown in FIG. 3 is obtained. Meanwhile, the TiN layer  18   a  is provided as an anti-reflective coating to prevent the precision of patterning from reducing due to the reflection of light on the AlCu layer  17   a  during the exposure in photolithography.  
         [0075]    As described above, in this embodiment, in forming the p + -type source region  5  and p + -type drain region  6  of the p-channel type MOS transistor  2 , and in forming the n + -type source region  25  and n + -type drain region  26  of the n-channel type MOS transistor  3 , the silicide layers  10 ,  30  of Co—Si alloy layer are formed on the entire surface of the regions  5 ,  6 ,  25  and  26 , then, in advance, ion-implanting to the entire surface of the silicide layers  10 ,  30 , then forming the two-layer barrier layers  14 ,  34  of Ti/TiN followed by the annealing, thereby forming the Si-rich silicide layers  12 ,  32  while reacting Si with the Co—Si alloy layer and Ti. Thus, the semiconductor device in the first embodiment can be made by such a simple method. Namely, this method is performed adding only the process of ion-implanting Si in FIG. 14 to the conventionally-conducted process, without requiring another process. Therefore, the manufacturing process can be simplified.  
         [0076]    [Embodiment 3] 
         [0077]    [0077]FIG. 17 is a cross sectional view showing a method for making a semiconductor device in the third preferred embodiment of the invention.  
         [0078]    The big difference of the composition of the method for making a semiconductor device in the third embodiment from that in the second embodiment is that the epitaxial selective growth of Si is conducted, instead of the entire-surface ion-implantation of Si shown in FIG. 14.  
         [0079]    Namely, as shown in FIG. 17, using Si 2 H 6  as an impurity source, the epitaxial growth is conducted on the conditions of flow rate of 1 to 20 SCCM (standard cubic centimeter per minute), pressure of less than 1×10 −2  Torr, 600 to 750° C. and 1 to 60 min. Thereby, a Si layer  41  is selectively grown on the entire surface of the silicide layers  10 ,  30  of Co—Si alloy layer. Thereafter, by conducting processes similar to those shown in FIGS. 15 and 16, the semiconductor device shown in FIG. 3 is obtained. Meanwhile, except this difference, this embodiment is similar to the second embodiment above-mentioned. Therefore, in FIG. 17, like parts are indicated by like reference numerals as used in the second embodiment and their explanations are omitted herein.  
         [0080]    Thus, also in this embodiment, the same effect as that described in the second embodiment can be obtained.  
         [0081]    [Embodiment 4] 
         [0082]    [0082]FIGS. 18 and 19 are cross sectional views showing a method for making a semiconductor device in the fourth preferred embodiment of the invention.  
         [0083]    The big difference of the composition of the method for making a semiconductor device in the fourth embodiment from that in the second embodiment is that the partial ion-implantation of Si is conducted, instead of the entire-surface ion-implantation of Si shown in FIG. 14.  
         [0084]    Namely, as shown in FIG. 18, the interlayer dielectric film  20  is formed on the entire surface of the semiconductor substrate  1 , then removing part of the film by photolithography to expose part of the silicide layers  10 ,  30  to open the contact holes  13 ,  33 .  
         [0085]    Then, as shown in FIG. 19, Si is ion-implanted, as shown by arrows, into the semiconductor substrate  1  on the conditions of acceleration energy of 1 to 20 keV and dose amount of 1×10 14  to 7×10 15  cm −2 . Thereby, Si is implanted into part of the silicide layers  10 ,  30  through the contact holes  13 ,  33 . Sequentially, by conducting the same processes as those shown in FIGS. 15 and 16, the semiconductor device shown in FIG. 3 is obtained.  
         [0086]    Thus, also in this embodiment, the same effect as that described in the second embodiment can be obtained.  
         [0087]    Beside, in this embodiment, the Si-rich silicide layers  12 ,  32  are selectively formed at the bottom of the contact holes  13 ,  33 , and are made amorphous-like due to the etching in forming the contact holes  13 ,  33 . Therefore, the formation of the silicide layers  12 ,  32  can be facilitated.  
         [0088]    [Embodiment 5] 
         [0089]    [0089]FIG. 20 is a cross sectional view showing a method for making a semiconductor device in the fifth preferred embodiment of the invention.  
         [0090]    The big difference of the composition of the method for making a semiconductor device in the fifth embodiment from that in the third embodiment is that the epitaxial selective growth of Si shown in FIG. 17 is conducted after forming the contact holes.  
         [0091]    Namely, as shown in FIG. 18, the interlayer dielectric film  20  is formed on the entire surface of the semiconductor substrate  1  by CVD, and then the contact holes  13 ,  33  are formed. Then, as shown in FIG. 20, using Si 2 H 6  as an impurity source, the epitaxial growth is conducted on the conditions of flow rate of 1 to 20 SCCM, pressure of less than 1×10 −2  Torr, 600 to 750° C. and 1 to 60 min. Thereby, the Si layer  41  is selectively grown on part of the silicide layers  10 ,  30  of Co—Si alloy layer. Thereafter, by conducting the same processes as those shown in FIGS. 15 and 16, the semiconductor device shown in FIG. 3 is obtained.  
         [0092]    Thus, also in this embodiment, the same effect as that described in the third and fourth embodiments can be obtained.  
         [0093]    [Embodiment 6] 
         [0094]    [0094]FIG. 21 is a cross sectional view showing a method for making a semiconductor device in the sixth preferred embodiment of the invention.  
         [0095]    The big difference of the composition of the method for making a semiconductor device in the sixth embodiment from that in the fourth embodiment is that the partial ion-implantation of Ti is conducted before conducting the partial ion-implantation of Si.  
         [0096]    Namely, as shown in FIG. 18, the interlayer dielectric film  20  is formed on the entire surface of the semiconductor substrate  1 , then opening the contact holes  13 ,  33 . Then, as shown in FIG. 21, Ti is ion-implanted, as shown by arrows, into the semiconductor substrate  1  on the conditions of acceleration energy of 1 to 30 keV and dose amount of 1×10 14  to 1×10 15  cm −2 . Thereby, Ti is implanted into part of the silicide layers  10 ,  30  through the contact holes  13 ,  33 . Since the surface of Co—Si alloy layerof the silicide layers  10 ,  30  is made amorphous-like due to the ion-implantation of Ti, the formation of the Si-rich silicide layers (Co—Si—Ti alloy layers)  12 ,  32  to follow this can be facilitated.  
         [0097]    Sequentially, Si is ion-implanted, as shown by arrows, on the conditions of acceleration energy of 1 to 20 keV and dose amount of 5×10 14  to 7×10 15  cm −2 . Thereby, Si is implanted into part of the silicide layers  10 ,  30  through the contact holes  13 ,  33 , like Ti. Thereafter, by conducting the same processes as those shown in FIGS. 15 and 16, the semiconductor device shown in FIG. 3 is obtained.  
         [0098]    Thus, also in this embodiment, the same effect as that described in the fourth embodiment can be obtained.  
         [0099]    Although the preferred embodiments of the invention have been detailed as above referring to the drawings, the concrete composition of this invention is not limited to these embodiments and this invention includes any alterations of designing in the scope of this invention. For example, the components of the Si-rich silicide layer, which is composed of Co—Si—Ti alloy layer, may be replaced with another component, e.g., tungsten, except Si. Also, tungsten, which is used as a wiring material, may be replaced with another material, e.g., Al-system metal. Also, the substrate is not limited to the semiconductor substrate.  
         [0100]    Also, though, in the above embodiments, this invention is applied to the MOS type semiconductor device, this invention is not limited to this, and, if only using the silicide layer as the contact layer, may be applied to another semiconductor device, e.g., a bipolar type semiconductor device.  
         [0101]    Also, in the sixth embodiment, the ion-implantation of Ti may be conducted after the ion-implantation of Si. Also, the conditions of the ion-implantation of various impurities and thermal treatment can be altered according to need.  
         [0102]    Also, in the above embodiments, the Si-rich silicide layer is formed by ion-implanting Si into the contact hole with a diameter of about 0.2 μm at a dose amount of about 5×10 15  cm −2 . However, when, for the contact hole with a diameter of 0.1 to 0.2 μm, Si is ion-implanted at a dose amount of 2×10 15  cm −2  to 8×10 15  cm −2 , similar effect to that described above can be obtained.  
         [0103]    Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may be occurred to one skilled in the art which fairly fall within the basic teaching here is set forth.