Abstract:
A pipeline-based circuit with a postponed clock-gating mechanism and related driving method are disclosed for reducing power consumption, and the driving method does not deteriorate processing performance of the pipeline-based circuit. A pipeline-based circuit has a plurality of logic operators cascaded to form at least a pipeline, a pipeline control unit for generating at least a control signal to each logic operator for controlling whether one logic operator needs to pipe data to next logic operator, and a control value calculator for setting a valid bit of each logic operator following a currently activated logic operator according to the control signals generated from the pipeline control unit. When each logic operator begins operating, the related control value is used to determine whether or not a clock signal piping data of the present logic operator to next logic operator is gated to reduce power consumption. This postponed clock-gating mechanism avoids the degradation of pipeline clock speed limitation.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a pipeline-based circuit. In particular, the present invention discloses a pipeline-based circuit utilizing a postponed clock-gating mechanism for reducing power consumption.  
         [0003]     2. Description of the Prior Art  
         [0004]     An accurate clock signal is a key factor for a logic circuit to perform a correct logic operation. That is, the clock signal is used to drive kernel circuit units such as counters and registers within the logic circuit, and a stable clock signal such as a clock signal generated from a crystal oscillator always functions as a reference clock to arbitrate operations of the circuit units within the logic circuit. However, all of the circuit units within the logic circuit are not always active. When some of the circuit units enter an idle mode, these idle circuit units do not need to be driven by the clock signal continuously for performing related operations. If the clock signal is still inputted into the idle circuit units, power consumption of the logic circuit is increased unnecessarily. It is well known that the power consumption of the logic circuit is mainly generated from delivering the clock signal to these circuit units and enabling these circuit units to run related logic operations. In order to reduce power consumption of the logic circuit such as a microprocessor, the clock signals are gated from triggering the idle circuit units. Therefore, unwanted power consumption is accordingly eliminated. In other words, the clock signal transferred to an idle circuit unit is first converted to be one signal with a fixed logic value (“1” or “0”). Taking a clock signal that is a square wave for example, the logic value “1” corresponding to a high voltage and the logic value “0” corresponding to a low voltage are alternatively switched. The clock signal is gated after the clock signal is converted to hold either the logic value “1” or the logic value “0”. Because the logic circuit drives one internal circuit unit through a converted clock signal holding a fixed logic value, the operation associated with the circuit unit is blocked. Therefore, the total power consumption of the logic circuit is further reduced. The above-mentioned process is a well-known clock-gating mechanism.  
         [0005]     Please refer to  FIG. 1  and  FIG. 2 .  FIG. 1  is a schematic diagram of a prior clock-gating circuit  10 , and  FIG. 2  is a timing diagram of signals of the clock-gating circuit  10  shown in  FIG. 1 . The clock-gating circuit  10  has a controller  12  and a plurality of logic gates  14   a ,  14   b ,  14   c . Each of the logic gates  14   a ,  14   b ,  14   c  performs the AND logic operation. The controller  12  includes a plurality of clock control units  13   a ,  13   b ,  13   c  respectively used for generating control signals  15   a ,  15   b ,  15   c  to corresponding logic gates  14   a ,  14   b ,  14   c . In addition, a system clock generator  16  is capable of generating a clock signal  17  to the logic gates  14   a ,  14   b ,  14   c . Then, the logic gates  14   a ,  14   b ,  14   c  respectively output clock-gating output signals  18   a ,  18   b ,  18   c  to corresponding logic units  20   a ,  20   b ,  20   c . The above clock-gating output signals  18   a ,  18   b ,  18   c  are used to drive the logic units  20   a ,  20   b ,  20   c.    
         [0006]     When the logic unit  20   a  enters the idle mode, the clock control unit  13   a  is activated to gate the clock signal  17  through the control signal  15   a . Please refer to  FIG. 2 . During a period t 0 ˜t 2 , the control signal  15   a  holds the logic value “1” corresponding to a high voltage. Therefore, the clock signal  17  successfully passes through the logic gate  14   a . That is, the waveform of the clock-gating output signal  18   a  is identical to the waveform of the clock signal  17 , and the clock-gating output signal  18   a  drives the running logic unit  20   a  successfully. However, when the logic unit  20   a  does not need to be activated during a period t 2 ˜t 4 , the clock control unit  13   a  outputs the control signal  15   a  with the logic value “0” corresponding to a low voltage. The clock signal  17  is gated through the logic gate  14   a . That is, the clock-gating output signal  18   a  holds the constant logic value “0” during the period t 2 ˜t 4 , and the operation of the logic unit  20   a  is interrupted to reduce power consumption. During a period t 4 ˜t 5  and a period t 7 ˜t 8 , the control signal  15   a  corresponds to the logic value “1” so that the clock signal  17  is inputted into the logic unit  20   a  again. During a period t 5 ˜t 7 , the logic unit  20   a  does not need to be activated. Therefore, the control signal  15   a  then corresponds to the logic value “0” to gate the clock signal  17  from driving the logic unit  20   a  for reducing power consumption.  
         [0007]     Similarly, with regard to other logic units  20   b ,  20   c , the clock control units  13   b ,  13   c  output the control signals  15   b ,  15   c  corresponding to the logic value “0” to gate the clock signal  17  through the logic gates  14   b ,  14   c  when the logic units  20   b ,  20   c  do not need to be activated. For the logic unit  20   b , the clock control unit  13   b  gates the clock signal  17  to reduce power consumption during periods t 0 ˜t 1 , t 3 ˜t 4 , t 5 ˜t 7 . For the logic unit  20   c , the clock control unit  13   c  gates the clock signal  17  to reduce power consumption during a period t 5 ˜t 6 . Please note that the operations associated with the logic units  20   b ,  20   c  are not repeated for simplicity.  
         [0008]     For the logic circuit, a pipeline structure, generally speaking, is adopted to improve processing efficiency. Please refer to  FIG. 3 , which is a block diagram of a prior art pipeline-based circuit  30 . The pipeline-based logic circuit  30  includes a plurality of processing units  32   a ,  32   b ,  32   c , a pipeline control unit  34 , and a clock-gating unit  36 . Each of the processing units  32   a ,  32   b ,  32   c  includes a logic unit  38   a ,  38   b ,  38   c  and a buffer unit  40   a ,  40   b ,  40   c . The logic units  38   a ,  38   b ,  38   c  are used to perform predetermined logic operations respectively. For example, the logic unit  38   a ,  38   b , or  38   c  can be an adder for doing binary addition or a multiplier for doing binary multiplication.  
         [0009]     The buffer units  40   a ,  40   b ,  40   c  corresponding to the logic units  38   a ,  38   b ,  38   c  are used to store calculation results outputted from the logic units  38   a ,  38   b ,  38   c . Then, a calculation result currently stored in one logic unit is passed to a logic unit next to the current logic unit. The buffer units  40   a ,  40   b ,  40   c  can be prior art flip-flops. If the logic unit  38   a  is used to output a calculation result having a bit length equaling  64 , the buffer unit  40  needs  64  flip-flops to store the calculation result. In addition, one clock signal is necessary for controlling the buffer units  40   a ,  40   b ,  40   c  to store the calculation results generated from the logic units  38   a ,  38   b ,  38   c  and controlling the buffer units  40   a ,  40   b ,  40   c  to output the stored calculation results.  
         [0010]     The pipeline control unit  34  is used to control the operation of the pipeline established by the processing units  32   a ,  32   b ,  32   c . As shown in  FIG. 3 , the pipeline control unit  34  is capable of outputting control signals PA, PB, PC to control the processing units  32   a ,  32   b ,  32   c . For example, an input data DATA_IN is inputted into the processing unit  32   a . Therefore, the logic unit  38   a  starts processing the input data DATA_IN according to a predetermined logic operation. After the predetermined logic operation is done, the pipeline control unit  34  generates the control signal PA according to current operating modes of the logic units  32   a ,  32   b ,  32   b , and outputs the control signal PA to the logic unit  32   a  for activating the buffer unit  40   a  to store a calculation result generated from the logic unit  32   a . At the same time, the stored calculation result is passed to the next logic unit  32   b . As mentioned above, one of the logic units  32   a ,  32   b ,  32   c  in the pipeline-based logic circuit  30  may not be used to process the input data DATA_IN. For example, after the input data DATA_IN has been processed by the logic units  32   a ,  32   b , a branch may occur to terminate the process for the input data DATA_IN. Therefore, the logic unit  32   b  does not need to pass its calculation result to the next logic unit  32   c  for following operations. For the input data DATA_IN, any logic units following the logic unit  32   b  do not need to be activated. In other words, the related buffer units do not need to transfer calculation results stage by stage. Therefore, a prior art clock-gating mechanism can be adopted to reduce power consumption of the inactive buffer units.  
         [0011]     The clock-gating unit  36  is used to control the clock signals inputted into the buffer units  40   a ,  40   b ,  40   c  positioned in the corresponding processing units  32   a ,  32   b ,  32   c  to achieve the goal of saving power. Generally speaking, the clock-gating unit  36  generates the clock signals CLK_GA, CLK_GB, CLK_GC inputted to the buffer units  40   a ,  40   b ,  40   c  according to a system clock CLK_S and the control signals PA, PB, PC generated from the pipeline control unit  34 . The control signals PA, PB, PC are determined according to predetermined conditions. For instance, data transmission statuses associated with a bus and operating statuses of logic units function as the predetermined condition used by the pipeline control unit  34  to output the control signal PB. Please note that the predetermined conditions for the processing units  32   a ,  32   b ,  32   c  may differ from each other. For example, each of the control signals PA, PB, PC comprises a piping enable signal for driving a corresponding logic unit to pipe its calculation result to the next logic unit, and a piping flush signal for nullifying the calculation result generated by the corresponding logic unit. Concerning the logic unit  32   b , suppose that the control signal PB itself is a piping enable signal, and corresponds to three conditions A, B, C. That is, the three conditions A, B, C are used to determine whether the piping enable signal is outputted to make the processing unit  32   b  pipe its calculation result to the next processing unit  32   c . The conditions A, B, C are related to the operating statuses of the logic units  32   a ,  32   b ,  32   c , and the pipeline control unit  34  only uses the conditions A, B, C to set the control signal PB corresponding to the logic unit  32   b . The pipeline control unit  34  is capable of determining if the piping enable signal is outputted to the logic unit  32   b  after the conditions A, B, C have been successfully determined. Therefore, the pipeline control unit  34  needs to wait until all of the conditions A, B, C are determined. That is, the pipeline control unit  34  has to wait a longer period of time before generating the piping enable signal for the processing unit  32   b . When the control signal PB is used to drive the prior art clock-gating mechanism, the above-mentioned delay time actually affects the operation of the clock-gating unit  36 . The reason is described as follows.  
         [0012]     Please refer to  FIG. 4  and  FIG. 5 .  FIG. 4  is an example schematic diagram of the clock-gating unit  36  shown in  FIG. 3 , and  FIG. 5  is a timing diagram of signals running in the clock-gating unit  36  shown in  FIG. 3 . The clock-gating unit  36  has a logic gate  42  and an inverter  44 . The logic gate  44  performs an NOR logic operation upon the clock control signal CLK_ENB and the clock signal CLK_S to generate the clock signals CLK_GA, CLK_GB, CLK_GC for the processing units  32   a ,  32   b ,  32   c . The clock control signal CLK_ENB is generated from a predetermined logic operation upon the piping enable signal and the pipeline flush signal of each processing unit  32   a ,  32   b ,  32   c . For example, suppose that the clock control signal CLK_ENB for the processing unit  32   b  is determined by the piping enable signal only. As mentioned above, when all of the conditions A, B, C correspond to the logic value “1”, the clock control signal CLK_ENB is set by the logic value “1” at t 4 . As shown in  FIG. 5 , the clock control signal CLK_ENB does not have a transition from the logic value “0” to the logic value “1” until t 4 . With the processing performed by the clock-gating unit  36 , the clock signal CLK_GB has a falling edge at t 3 , and corresponds to the logic value “0” during a period t 3 ˜t 4 . Then, the clock signal CLK_GB has a rising edge at t 4 , and the clock signal CLK_GB holds the logic value “1” after t 4 . If the processing unit  32   b  connected to the clock-gating unit  36  is triggered by rising edges of the clock signal CLK_GB, the clock-gating unit  36  should make the clock signal CLK_GB hold the logic value “1” after to t 0  gate the clock signal CLK_S. However, because the clock control signal CLK_ENB is late-arrived as shown in  FIG. 5 , the processing unit  32   b  is triggered twice respectively at t 0  and t 4 . In other words, the clock signal CLK_GB leaves the logic value “0” at t 4 . Therefore, the clock signal CLK_GB having the rising edge at t 4  is capable of triggering the processing unit  32   b , and as such, the clock signal CLK_GB cannot achieve the goal of reducing power consumption.  
         [0013]     Furthermore, a glitch is induced to affect the operation of the processing unit  32   b . According to the prior art, the period t 0 ˜t 1  is defined to be a clock-gating hold time, and the period t 2 ˜t 3  is defined to be a clock-gating setup time. In other words, the clock control signal CLK_ENB needs to be inputted before a falling edge of the clock signal CLK_S. Otherwise, the clock signal CLK_GB generates the unwanted glitch during the period t 3 ˜t 4 . The unwanted glitch induced for each of the clock signals CLK_GA, CLK_GB, CLK_GC likely results in the pipeline-based logic circuit  30  functioning incorrectly.  
       SUMMARY OF INVENTION  
       [0014]     It is therefore a primary objective of this invention to provide a pipeline-based circuit utilizing control values to control the operation of the clock-gating mechanism so that whether or not a clock signal is gated is predetermined by the control values before each stage of the pipeline-based circuit starts working.  
         [0015]     Briefly summarized, the preferred embodiment of the present invention discloses a pipeline-based circuit. The pipeline-based circuit has a plurality of logic operators cascaded to form at least a pipeline, a pipeline control unit for generating at least a control signal to each logic operator for controlling whether one logic operator needs to pipe data to a next logic operator, and a control value calculator for setting a control value of each logic operator following a currently activated logic operator according to the control signals generated from the pipeline control unit. When each logic operator begins operating, the related control value is used to determine whether or not a clock signal piping data of the present logic operator to the next logic operator is gated to reduce power consumption.  
         [0016]     It is an advantage of the present invention that the claimed pipeline-based circuit can prevent the possibly late-arrived control signal from affecting the operation of the clock-gating unit. That is, the claimed pipeline-based circuit is capable of gating clock signals in time for saving power successfully. In addition, the claimed pipeline-based circuit needs to implement additional second buffer units only. The circuit structure of the second buffer unit is simple, and the implementation is straightforward. Therefore, the control values can be easily applied to pipeline-based circuits having different pipeline structures for accomplishing the same purpose of reducing power consumption. In addition, the postponed clock-gating mechanism avoids the degradation of pipeline clock speed.  
         [0017]     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0018]      FIG. 1  is a schematic diagram of a prior clock-gating circuit.  
         [0019]      FIG. 2  is a timing diagram of signals of the clock-gating circuit shown in  FIG. 1 .  
         [0020]      FIG. 3  is a block diagram of a prior art pipeline-based circuit.  
         [0021]      FIG. 4  is a schematic diagram of a clock-gating unit shown in  FIG. 3 .  
         [0022]      FIG. 5  is a timing diagram of signals of the clock-gating unit shown in  FIG. 3 .  
         [0023]      FIG. 6  is a block diagram of a pipeline-based circuit according to the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0024]     Please refer to  FIG. 6 , which is a block diagram of a pipeline-based circuit  50  according to the present invention. The pipeline-based circuit  50 , which can be a microprocessor or a digital signal processor (DSP), has a plurality of processing units  52   a ,  52   b ,  52   c , a pipeline control unit  54 , and a control value generator  56 . The processing units  52   a ,  52   b ,  52   c  are cascaded to establish a pipeline. Each of the processing units  52   a ,  52   b ,  52   c  has a logic unit  58   a ,  58   b ,  58   c , a clock-gating unit  60   a ,  60   b ,  60   c , a first buffer unit  62   a ,  62   b ,  62   c , and a second buffer unit  64   a ,  64   b ,  64   c . Taking the processing unit  52   a  for example, the logic unit  58   a  is used to perform a predetermined logic operation such as addition or multiplication. The first buffer unit  62   a  is used to store a calculation result outputted from the logic unit  58   a , and to pass the stored calculation result to the next processing unit  52   b . The clock-gating unit  60  is used to control a clock signal inputted into the first buffer unit  62   a  according to an operating status (an “active”mode or an “idle”mode) of the first buffer unit  62   a . If the first buffer unit  62   a  does not need to be driven by the clock signal, the clock signal is gated for reducing power consumption. In the preferred embodiment, the second buffer units  64   a ,  64   b ,  64   c  store control values  66   a ,  66   b ,  66   c  respectively, and the control values  66   a ,  66   b ,  66   c  are used for controlling the clock-gating units  60   a ,  60   b ,  60   c  to gate clock signals inputted into the first buffer units  62   a ,  62   b ,  62   c . In addition, the pipeline control unit  54  outputs control signals GOA, GOB, GOC, NullA, NullB, NullC for controlling operations of the processing units  52   a ,  52   b ,  52   c . For instance, when the pipeline control unit  54  delivers the control signal GOA to the processing unit  52   a , it means that the calculation result of the logic unit  58   a  needs to be piped to the next processing unit  52   b . However, if the pipeline control unit  54  outputs the control signal NullA to the processing unit  52   a , it means that the calculation result generated from the logic unit  58   a  needs to be nullified. Similarly, the control signals GOB, GOC, NullB, NullC perform the same operation mentioned above, and repeated description is omitted for conciseness. The preferred embodiment, therefore, sets the control values  66   a ,  66   b ,  66   c  according to the control signals GOA, GOB, GOC, NullA, NullB, NullC corresponding to the processing units  52   a ,  52   b ,  52   c . That is, the control value generator  56  generates the control signals Va″, Vb″, Vc″ respectively to set corresponding control values  66   a ,  66   b ,  66   c . Please note that the control signals Va″, Vb″, Vc″ represent the updated control signals Va, Vb, Vc for setting the control values  66   a ,  66   b ,  66   c . The detailed operation related to controlling the first buffer units  62   a ,  62   b ,  62   c  through the control values  66   a ,  66   b ,  66   c  inputted into corresponding clock-gating units  60   a ,  60   b ,  60   c  is described as follows.  
         [0025]     In the preferred embodiment, the clock-gating units  60   a ,  60   b ,  60   c  do not gate the clock signals generated by a clock generator from being inputted into corresponding first buffer units  62   a ,  62   b ,  62   c  if the control values  66   a ,  66   b ,  66   c  hold the logic value “1”. On the contrary, the clock-gating units  60   a ,  60   b ,  60   c  gate the clock signals from being inputted into corresponding first buffer units  62   a ,  62   b ,  62   c  for reducing power consumption if the control values  66   a ,  66   b ,  66   c  hold the logic value “0”. Please note that the first buffer units  62   a ,  62   b ,  62   c  and the second buffer units  64   a ,  64   b ,  64   c  in the preferred embodiment are built using flip-flops, and the first buffer units  62   a ,  62   b ,  62   c  and the second buffer units  64   a ,  64   b ,  64   c  can store data or output data according to the received clock signals. The circuit structures of the clock-gating units and the flip-flops are well known, and the lengthy description is skipped for simplicity. In addition, the first buffer units  62   a ,  62   b ,  62   c  and the second buffer units  64   a ,  64   b ,  64   c  can be implemented by other circuits capable of storing data and outputting data.  
         [0026]     Suppose that the logic value “1” has been assigned to the control values  66   a ,  66   b ,  66   c  in the processing units  52   a ,  52   b ,  52   c  through the control signals Va″, Vb″, Vc″. Therefore, the clock signals are passed to the first buffer units  62   a ,  62   b ,  62   c  through the clock-gating units  60   a ,  60   b ,  60   c  for driving the logic units  58   a ,  58   b ,  58   c  to generate calculation results respectively. Then, the pipeline control unit  54  starts setting logic values of the control signals GOA, GOB, GOC, NullA, NullB, NullC according to the defined rules for the processing units  52   a ,  52   b ,  52   c . In the preferred embodiment, the control value generator  56  generates the control signals Va″, Vb″, Vc″ for updating the control values of the processing units  52   a ,  52   b ,  52   c  according to the control signals GOA, GOB, GOC, NullA, NullB, NullC, Va, Vb, Vc. The control signals Va, Vb, Vc inputted into the control value generator  56  represent the control values  66   a ,  66   b ,  66   c  currently stored in the second buffer units  64   a ,  64   b ,  64   c , and the control signal Va″, Vb″, Vc″, outputted from the control value generator  56  are used to update the control values  66   a ,  66   b ,  66   c  currently stored in the second buffer units  64   a ,  64   b ,  64   c . In other words, the control signals Va, Vb, Vc and the control signals Va″, Vb″, Vc″ are identical. However, the control signals Va, Vb, Vc and the control signals Va″, Vb″, Vc″ respectively represent the current control values and the next control values.  
         [0027]     For the control value  66   b  of the processing unit  52   b , the rules for determining the control signal Vb″ are listed below. 
    Rule (1): if Va=1 &amp; GOA &amp; !NullA, Vb=1     Rule (2): if Vb=1 &amp; !GOA &amp; !GOB &amp; !NullB, Vb″=1     Rule (3): if GOA &amp; NullA, Vb=0     Rule (4): if !GOA &amp; GOB, Vb″=0     Rule (5): if Va=0 &amp; GOA, Vb″=0    
 
         [0033]     The above rules are described as follows. For the rule (1), the control value  66   a  holds the logic value “1” so that the clock signal is successfully inputted into the first buffer unit  62   a . Therefore, the first buffer unit  62   a  functions normally owing to the operative clock signal. In addition, the pipeline control unit  54  outputs the control signal GOA to the processing unit  52   a  for making the processing unit  52   a  pipe the calculation result to the next processing unit  52   b . At this time, the pipeline control unit  54  does not output the control signal NullA to the processing unit  52   a  yet for making the processing unit  52   a  nullify the calculation result. Therefore, the control value  66   b  is set to the logic value “1”. In other words, the following first buffer unit  62   b  is enabled to start working according to the rule (1).  
         [0034]     For the rule (2), the control value  66   b  holds the logic value “1” so that the clock signal is successfully inputted into the first buffer unit  62   b . Now, the first buffer unit  62   b  functions normally owing to the operative clock signal. In addition, the pipeline control unit  54  does not output the control signal GOA to the processing unit  52   a  yet for making the processing unit  52   a  pipe the calculation result to the next processing unit  52   b , and the pipeline control unit  54  does not output the control signal GOB to the processing unit  52   b  yet for making the processing unit  52   b  pipe the calculation result to the next processing unit  52   c . At the same time, the pipeline control unit  54  does not output the control signal NullB to the processing unit  52   b  for making the processing unit  52   b  nullify the calculation result. Therefore, the control value  66   b  is not modified, and still keeps the original logic value “1”.  
         [0035]     For the rule (3), the pipeline control unit  54  outputs the control signal NullA to the processing unit  52   a  for nullifying the calculation result of the processing unit  52   a . That is, the output data of the logic unit  58   a  is cleared. At the same time, the pipeline control unit  54  generates the control signal GOA for driving the processing unit  52   a  to pipe the calculation result to the next processing unit  52   b . It is noteworthy that the calculation result of the processing unit  52   a  has been nullified. Therefore, the data inputted into the logic unit  58   b  is not valid, and the processing unit  52   b  does not need to activate the first buffer unit  62   b  for piping the calculation result of the logic unit  58   b  to the next processing unit  52   c . The logic value “0” is assigned to the control value  66   b  so that the clock-gating unit  60   b  gates the clock signal from being inputted into the first buffer unit  62   b.    
         [0036]     For the rule (4), the pipeline control unit  54  outputs the control signal GOB to the processing unit  52   b  for controlling the processing unit  52   b  to pipe the calculation result to the next processing unit  52   c . However, the pipeline control unit  54  does not output the control signal GOA to the processing unit  52   a  yet. Therefore, the logic unit  58   b  of the processing unit  52   b  does not receive any input data used for calculating the calculation result, and no calculation result needs to be passed to the next processing unit  52   c  through the first buffer unit  62   b . The logic value “0” is then assigned to the control value  66   b  so that the clock-gating unit  60   b  gates the clock signal from being inputted into the first buffer unit  62   b . In other words, the first buffer unit  62  is unable to output any valid data to the processing unit  52   c.    
         [0037]     For the rule (5), the clock signal originally inputted into the first buffer unit  62   a  is gated because the control value  66   a  currently holds the logic value “0”. Therefore, the first buffer unit  62   a  is unable to function normally for piping the calculation result of the processing unit  52   a  to the next processing unit  52   b . Even though the pipeline control unit  54  outputs the control signal GOA to the processing unit  52   a , the processing unit  52   a  is still unable to pipe its calculation result to the next processing unit  52   b . Concerning the processing unit  52   b , the processing unit  52   b  does not receive any valid input data for the logic unit  58   b . The first buffer unit  62   b  of the processing unit  52   b , therefore, does not need to be driven by the clock signal for piping the calculation result of the logic unit  58   b  to the processing unit  52   c . The logic value “0” is then assigned to the control value  66   b.    
         [0038]     The control values  66   a ,  66   b ,  66   c  of the processing units  52   a ,  52   b ,  52   c  hold either the logic value “1” or the logic value “0” according to the above-listed rules. From the above description, the control value  66   c  of the processing unit  52   c  following the processing unit  52   b  must correspond to the logic value “0” through the rule (5) after the control value  66   b  of the processing unit  52   b  is set to the logic value “0” through the rule (3), the rule (4), or the rule (5). Therefore, when the processing unit  52   c  starts working, the control value  66   c  drives the clock-gating unit  60   c  to gate the clock signal from being inputted into the first buffer unit  62   c.    
         [0039]     In the preferred embodiment, the second buffer units  64   a ,  64   b ,  64   c  also need to be driven by clock signals for storing control values  66   a ,  66   b ,  66   c  and outputting the control values  66   a ,  66   b ,  66   c  to corresponding clock-gating units  60   a ,  60   b ,  60   c . Though the second buffer units  64   a ,  64   b ,  64   c  are added to the processing units  52   a ,  52   b ,  52   c  to keep the control values  66   a ,  66   b ,  66   c  used for controlling clock signals inputted into the first buffer units  62   a ,  62   b ,  62   c . Compared with the power consumption of a system clock generator continuously outputting clock signals to drive the idle first buffer units  62   a ,  62   b ,  62   c , the power consumption of the system clock generator continuously outputting the clock signals to drive the second buffer units  64   a ,  64   b ,  64   c  is negligible. For example, the logic unit  58  generates the calculation result having a bit length equaling  64 . The first buffer unit  62   a , therefore, requires  64  flip-flops to handle the calculation result correctly. However, only one flip-flop is needed to keep the control value  66   a . To sum up, the preferred embodiment having these additional second buffer units  64   a ,  64   b ,  64   c  does not greatly raise the power consumption of the system clock generator. Actually, the preferred embodiment not only reduces the power consumption, but also allows operation of the clock-gating unit to conform to the limitation of the well-known clock-gating setup time.  
         [0040]     In addition, the preferred embodiment uses the control values  66   a ,  66   b ,  66   c  to drive the clock-gating units  60   a ,  60   b ,  60   c . The control value  66   c  of the processing unit  52   c  following the processing unit  52   b  certainly corresponds to the logic value “0” through the rule (5) after the control value  66   b  of the processing unit  52   b  is set to the logic value “0” through the rule (3), the rule (4), or the rule (5). Therefore, when the processing unit  52   c  starts working, the control value  66   c  drives the clock-gating unit  60   c  to gate the clock signal from being inputted into the first buffer unit  62   c . In other words, the power consumption of the system clock generator is quickly reduced when the processing unit  52   c  starts working. The time wasted for waiting a pipeline control unit of a running prior processing unit to finish delivering a wanted control signal to a clock-gating unit for gating a clock signal is cut down now with the help of the claimed control values. That is, with the implementation of the control values, the preferred embodiment is capable of transmitting the control values to the clock-gating units when the corresponding processing units start working. Therefore, the preferred embodiment can prevent the control signal delayed by the pipeline control unit from affecting the operation of the clock-gating unit. That is, the preferred embodiment is capable of gating clock signals correctly for saving power, and is capable of effectively improving cycle time of the pipeline-based circuit  50 .  
         [0041]     Please note that the preferred embodiment only utilizes one pipeline to illustrate its operation. However, the pipeline-based circuit  50  can be built according to a super-scalar structure or a super-pipeline structure. In addition, the pipeline-based circuit  50  still can utilize the control values to control corresponding clock-gating units. Taking a super-scalar structure with a plurality of pipelines for example, a plurality of processing units are located at each pipeline. Therefore, a plurality of buffer units used for storing control values are then implemented according to a total number of the processing units. With the above-mentioned rules for determining the control values, the control values are capable of achieving the goal of saving power through correctly gating clock signals. To sum up, the claimed control values can be easily implemented on the pipeline-based circuits  50  having different pipeline structures. Therefore, the pipeline-based circuit according to the present invention has great scalability.  
         [0042]     In contrast to the prior art, the claimed pipeline-based circuit utilizes second buffer units to store control values used for controlling clock-gating units. When one processing unit does not need to pipe a calculation result to a next stage, the related control value is set by a predetermined logic value so that the clock signal is gated when the processing unit starts working. In other words, after the processing unit starts working, the operation of gating the clock signal for reducing power consumption associated with the clock signal is completed within a prior art clock-gating setup time. Furthermore, when following processing units start working, the corresponding control values are set by the same predetermined value according to the above-mentioned claimed rules for gating the clock signals inputted into the first buffer units of the following processing units. Therefore, the claimed pipeline-based circuit can prevent the late-arrived control signal from affecting the operation of the clock-gating unit. That is, the claimed pipeline-based circuit is capable of gating clock signals in time for saving power successfully. In addition, the claimed pipeline-based circuit only requires additional second buffer units. The circuit structure of the second buffer unit is simple, and the implementation is easy. Therefore, the control values can be easily applied to pipeline-based circuits having different pipeline structures for accomplishing the same purpose of reducing power consumption.  
         [0043]     Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.