Abstract:
A novel finite impulse response filter apparatus and method. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operates are connected to and odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.

Description:
BACKGROUND OF THE INVENTION 
     The invention relates generally to the field of finite impulse response filters and more specifically to digital sample interpolators for use in digital-to-analog video encoders. 
     In the television environment, there are many different standards for representing color information which are commonly referred to as color spaces. Color Spaces generally differ from each other in several respects including the signal magnitudes, frequency spectrum characteristics, and sampling frequencies (for digital color spaces). 
     Typically, conversion from one color space to another involves simple equation solving and filtering. In some cases however the sample rates need to be changed. For example, converting 4:2:2 YCrCb Color Space data as defined by CCIR-601 to YUV data which is used to form a composite TV signal requires sample rate conversion. The 4:2:2 term refers to a difference in the sample rates between Y (13.5 MHz) and the Cr/Cb (both sampled at 6.75 MHz). In order to maintain signal integrity, the conversion process requires interpolation of the individual Y, Cr, and Cb components to 27 MHz. Additionally, the data is linearly scaled: 
     Y out  =a 0  *Y in   
     U out  =a 1  *Cb in   
     V out  =a 2  *Cr in   
     where a 0 , a 1 , a 2  vary depending on which signal format, such as NTSC, PAL-BDGHI, PAL-N, PAL-M, etc. is required. The data must also be frequency filtered as required by the specific format. For example, YUV data must conform to the CCIR-624 and/or RS-170A standards which define the frequency characteristics. 
     An improved method and apparatus for providing the interpolation, scaling, and filtering required for video format conversion is therefore desirable. 
     SUMMARY OF THE INVENTION 
     A filter in accordance with one aspect of the present invention includes a delay line, a multiplier, and a summer. The delay line has an input for receiving a time multiplexed data stream and at least one tap. The multiplier has an input for receiving samples connected to the tap and multiplies the samples by a coefficient to form weighted samples which are provided on a multiplier output. The summer has an input connected to the multiplier output and a second input. The summer adds the weighted samples with samples received on the second input to form a summer output. The time multiplexed data stream comprises a first signal and a second signal each having a series of samples. The samples of the first signal and the samples of the second signal are interlaced to form the time multiplexed data stream. The filter alternatingly operates on the samples of the first data signal and the samples of the second data signal forming a filtered time multiplexed output. 
     Preferred embodiments may include a multiplexer connected to the delay line input. The multiplexer has inputs for receiving the first signal and the second signal and multiplexes the first and second signals into the time multiplexed data stream. The filter may also have a demultiplexer connected to the summer output for separating the time multiplexed output into the component first and second signals. The filter may also have a coefficient multiplexer connected to an input of the multiplier. The coefficient multiplexer may alternatively provide a first or a second coefficient to the multiplier providing different responses for even and odd cycles or for the first and second first signals, or both. The filter may also have an output multiplexer for re-sequencing the filtered time multiplexed output. 
     A filter in accordance with another aspect of the present invention includes an input for receiving a time multiplexed data stream comprising a first signal and a second signal each having a series of samples. The samples of the first signal and the samples of the second signal are interlaced to form the time multiplexed data stream. The filter includes a delay line having an input connected to receive the data stream, an odd tap and an even tap for respectively providing odd and even delays. A first multiplier is connected to the odd tap and a second multiplier is connected to the even tap. A first summer is connected to the first multiplier and a second summer is connected to the second multiplier. A crossbar switch has a first input connected to the output of the first summer and a second input connected to the output of the second summer. The crossbar switch has a first output and a second output. The crossbar switch selectively operates to respectively connect the first and second inputs to the first and second outputs in a direct mode and alternates to a crossbar mode connecting the first and second inputs to the second and first outputs. The first multiplier and summer alternate, operating on the samples of the first data signal and the samples of the second data signal, forming a first filtered time multiplexed output. The second multiplier and summer also alternate, operating on the samples of the second data signal and the samples of the first data signal, forming a second filtered time multiplexed output. The crossbar switch alternates between the direct and crossbar modes parsing the first and second filtered time multiplexed outputs into a filtered first signal and a filtered second signal. 
     Preferred embodiments may include a multiplexer connected to the delay line input. The multiplexer has inputs for receiving the first signal and the second signal and multiplexes the first and second signals into the time multiplexed data stream. The filter may also have a first and a second coefficient multiplexer respectively connected to an input of the first and the second multipliers. The coefficient multiplexer may alternatively provide a first or a second coefficient to the respective multiplier allowing the filter response for the first signal to be different from the filter response for the second signal. 
     A two stage filter in accordance with another aspect of the present invention includes a first stage and a second stage. The first stage includes a first stage delay line, a first stage multiplier, and a first stage summer. The first stage delay line has an input for receiving a time multiplexed data stream and has a tap output. The first stage multiplier has an input connected to the tap, for multiplying the input by a first selected coefficient and forming weighted samples as a multiplier output. The first stage summer has at least one input connected to the first stage multiplier output and forms a sum as an adder output. The time multiplexed data stream includes a first input stream and a second input stream, each comprising a series of input samples which are interlaced. The first stage alternatingly operates on the input samples of the first input stream and the input samples of the second input stream, forming a filtered time multiplexed output having alternating output samples. The second stage includes a second stage delay line, an even multiplier, an odd multiplier, an even adder, and an odd adder. The second stage delay line has an input connected to receive the filtered time multiplexed output and has an odd and an even tap output for respectively providing odd and even delays. The even multiplier has an input connected to the even tap, for multiplying the input by a first coefficient and forming weighted samples as an output. The odd multiplier has an input connected to the odd tap, for multiplying the input by a second coefficient and forming weighted samples as an output. The even adder has an input connected to the even multiplier output and provides a sum as an output. The odd adder has an input connected to the odd multiplier output and provides a sum as an output. The second stage operates on the filtered time multiplexed output of the first stage and forms two second stage filtered time multiplexed outputs having alternating output samples. 
     A filter method in accordance with another aspect of the present invention receives a time multiplexed data stream comprising a first input stream and a second input stream. Each input stream comprises a series of input samples which are interlaced in the multiplexed data stream. A selected delay is imposed on the input forming a delayed signal. The delayed signal is multiplied by a coefficient forming weighted samples. An addition is performed using the weighted samples forming a sum as a filtered time multiplexed output having alternating output samples. 
     Preferred embodiments may also include receiving the first data stream as a first input and the second data stream as a second input. The input samples of the first and second data streams are interlaced to form the time multiplexed data stream. The alternating output samples may be separated into a first output data stream and a second output data stream. The coefficient may be alternated between a first value and a second value. The first value may be used for multiplying the delayed signal respective of the first data stream and the second value may be used to multiply the delayed signal respective of the second data stream. The filter method may provide a first response for the first data stream and a second response for the second data stream. 
     A filter method in accordance with another aspect of the present invention receives a time multiplexed data stream comprising a first input stream and a second input stream. Each input stream comprises a series of input samples which are interlaced in the multiplexed data stream. A selected odd delay and a selected even delay are imposed on the input to form an odd delayed signal and an even delayed signal. The odd delayed signal is multiplied by a first coefficient forming odd weighted samples and the even delayed signal is multiplied by a second coefficient forming even weighted samples. An addition is performed using the odd weighted samples to form odd sums as a first multiplexed output and an addition is performed using the even weighted samples to form even sums as a second multiplexed output. 
     Preferred embodiments may also include routing the odd sums to a first output and the even sums to a second output in a direct mode and routing the odd sums to the second output and the even sums to the first output in a crossbar mode. The odd multiplying and summing steps operate on the input samples of the first data signal during a first interval and of the second data signal during a second interval, and provide a first filtered time multiplexed output. The even multiplying and summing steps operate on the input samples of the second data signal during a first interval and of the first data stream during a second interval, and provide a second filtered time multiplexed output. The selectively routing step operates in the direct mode during the first interval and in the crossbar mode during the second interval thus parsing the first and second filtered time multiplexed outputs into a filtered first output signal and a filtered second output signal. The first data stream may be received as a first input and the second data stream may be received as a second input. The input samples of the first and second data streams are interlaced to forming the time multiplexed data stream. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a functional block diagram of one embodiment of a time shared finite impulse response filter with a multiple signal stream capability. 
     FIG. 2 is a functional block diagram of another embodiment of a time shared finite impulse response filter with a multiple signal stream capability. 
     FIG. 3 is a functional block diagram of a multiplexer for cascading the filters of FIG. 1 and FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring to FIG. 1, a time shared finite impulse response filter with a multiple signal stream capability in accordance with one aspect of the present invention will be described. Filter 100 is configured as a 1-to-2 interpolator for interpolating two color difference input signals Cr and Cb from a 6.75 MHz data rate up to a 13.5 MHz data rate for use in a video encoder. Unless otherwise noted the components of filter 100 are clocked at a frequency of 27 MHz which is twice the 13.5 MHz output data rate. The filter 100 operation will be described in terms of a four clock cycle with each clock cycle being labeled sequentially as phases 0-3, φ 0 , φ 1 , φ 2 , and φ 3 . Phases φ 0  and φ 2  may be called the even phases and phases φ 1  and φ 3  may be called the odd phases. 
     The two input data streams Cr and Cb are fed to filter inputs 11 and 12, respectively. A 2-to-1 multiplexer 10 clocked at half clock frequency (13.5 MHz) receives the input data streams Cr and Cb and provides a multiplexed data stream on signal line 13. Multiplexer 10 passes the Cb input 12 to output 13 during the first two phases φ 0 , φ 1  of the cycle and passes the Cr input 11 to output 13 during the last two phases φ 2 , φ 3 . The multiplexed data stream is a sequence of alternating samples from each of the input data streams Cr and Cb. For input streams having sample sequences Cb0, Cb1, Cb2, etc. and Cr0, Cr1, Cr2, etc., the multiplexed data stream appears as Cb0, Cr0, Cb1, Cr1, Cb2, Cr2, etc. Since the multiplexer operates at half clock frequency, each sample in the multiplexed stream remains on the output 13 for two clock cycles. 
     The multiplexed data stream is fed to the input of delay line 110 which has several tapped delay outputs. As shown in FIG. 1, tap outputs 112, 113, 114, and 115 provide 4, 8, 12, and 16 clock delays, respectively. A sample presented to input 111 at clock cycle 0 will appear at tap 112 at clock cycle 4, at tap 113 at clock cycle 8, at tap 114 at clock cycle 12, and at tap 115 at clock cycle 16. For convenience, each position of the delay line has been labeled with a respective number e.g. t 0  or t 12  representative of its delay in clock cycles. Input 111 is called the t 0  sample, tap 112 may be called the t 4  sample, and taps 113, 114, and 115 may be respectively called the t 8 , t 12 , and t 16  samples. Intermediate delay line positions are numbered similarly e.g. t 15  corresponds to the 15th delay line position. 
     Assuming that the multiplexed input data stream contains samples Cb0, Cr0, Cb1, Cr1, Cb2, Cr2, etc. in sequence. Delay line 110 will fill with samples Cb0 at t 16  and t 15 , Cr0 at t 14  and t 13 , Cb1 at t 12  and t 11 , Cr1 at t 10  and t 9 , Cb2 at t 8  and t 7 , Cr2 at t 6  and t 5 , Cb3 at t 4  and t 3 , Cr3 at t 2  and t 1 , and Cb4 at t 0 . All of the delay line tap outputs t 0 , t 4 , t 8 , t 12 , and t 16  are multiples of four clocks, therefore, samples from only one of the two input data streams will be present at the taps at any particular moment. Taps t 16  (115), t 12  (114), t 8  (113), t 4  (112) and input t 0  (111) will respectively contain Cb0, Cb1, Cb2, Cb3, and Cb4 respectively for the first two phases φ 0 , φ 1  of each four clock cycle. During the second two phases φ 2 , φ 3  of the four clock cycles Cr0, Cr1, Cr2, Cr3, and Cr4 will be present on taps t 16 , t 12 , t 8 , t 4 , and t 0 , respectively. 
     Alternatively, the delay line may be clocked at half of the clock frequency which would require only half as many delay line positions. In the example of FIG. 1, the delay line would have 8 delay positions, each sample would occupy only one delay line position, and the tap outputs would still be t 16 , t 12 , t 8 , t 4 , and t 0 , because the delay would be clocked at one half clock frequency. Each sample would still be held at the respective tap output for two system clocks or one delay line clock. 
     Multiplexers 20, 30, 40, 50, 60, and 70 provide the sample present at their respective even &#34;E&#34; inputs on their respective outputs during the even phases φ 0  and φ 2  of the four phase operating cycle. Similarly, the samples present at the respective odd &#34;O&#34; inputs are provided on the respective multiplexer outputs during the odd phases φ 1 , φ 3 . For example, multiplexer 70 presents the A 1  value on its output during the even clock cycles φ 0 , φ 2  and the A 2  value during the odd clock cycles φ 1 , φ 3 . 
     Adders 120, 130, 140, and 150 respectively receive two input values and form a sum on an output during each clock cycle. For example, adder 120 sums the samples present on inputs 121 and 122 and provides the sum on output 123 each clock cycle. Multipliers 1160, 170, and 180 operate similarly forming the product of their respective inputs and providing the product on their respective outputs during each clock cycle. 
     Starting with adder 120 the overall operation of the filter 100 will be described. Adder 120 forms a sum on output 123 of the samples presented to its inputs 121 and 122 every clock cycle. Input 122 of adder 120 is fed from multiplexer 20 which provides the t 16  values during the even phases and t 12  during the odd phases to adder input 122. Samples from the input to are fed to the other input 121 of adder 120. Adder 120 therefore outputs the sum t 0  +t 16  during the even clock phases φ 0  and φ 2 , and the sum t 0  +t 12  during the odd clock phases φ 1  and φ 3 . 
     Multiplier 160 having an input 161 connected to the output 123 of adder 120 weights each sum produced by adder 120. A multiplexer 70 may be provided at input 162 of multiplier 160 to alternate the weighting coefficients A 1  and A 2  for each sum. Thus multiplier 160 multiplies sum t 0  +t 16  by weighting coefficient A 1  in the even clock phases and multiplies sum t 0  +t 12  by weighting coefficient A 2  in the odd clock phases. 
     Similarly, adder 130 has an input 131 connected to tap t 4  and an input connected to multiplexer 30 which is connected to taps t 8  and t 12 . Adder 130 thus forms sums t 4  +t 8  during the odd clock phases and t 4  +t 12  during the even clock phases. Multiplier 170 has an input 171 connected to the output 133 of adder 130 and an input 172 connected to multiplexer 60 which provides weighting coefficients B 1  and B 2 . Multiplier 170 multiplies the sum t 4  +t 12  by weighting coefficient B 1  during the even clock phases and multiplies the sum t 4  +t 8  by weighting coefficient B 2  during the odd clock phases. 
     Adder 140 has an input 141 connected to an output 173 of multiplier 170 and an input 142 connected to output 163 of multiplier 160. Adder 140 adds together the results of each multiplication forming the sum A 1  (t 0  +t 16 )+B 1  (t 4  +t 12 ) in the even clock phases and the sum A 2  (t 0  +t 12 )+B 2  (t 4  +t 8 ) in the odd clock phases. Multiplier 180 multiplies the output of multiplexer 40 by coefficient C from input 182. Multiplexer 40 outputs t 8  and zero during the even and odd phases, respectively. The output of multiplier 180 is therefore the product of C and t 8  during the even clock phases and zero during the odd clock phases. Adder 150 has an input 151 connected to output 143 of adder 140 and an input 152 connected to output 183 of multiplier 180. Adder 150 thus provides the even sum of A 1  (t 0  +t 16 )+B 1  (t 4  +t 12 )+C(t 8 ) during the even clock phases and the odd sum A 2  (t 0  +t 12 )+B 2  (t 4  +t 8 ) in the odd clock phases. 
     In each four clock cycle, two interpolated Cr and two interpolated Cb values are generated and output by adder 150 on output 153. In clock cycle φ 0  a first interpolated Cb value is calculated using the weighted sum A 1  (t 0  +t 16 )+B 1  (t 4  +t 12 )+C(t 8 ), then in clock cycle φ 1  a second interpolated Cb value is calculated using the weighted sum A 2  (t 0  +t 12 )+B 2  (t 4  +t 8 ). Similarly, in clock cycle φ 2  a first interpolated Cr value is calculated using the weighted sum A 1  (t 0  +t 16 )+B 1  (t 4  +t 12 )+C(t 8 ), and finally in clock cycle φ 3  a second interpolated Cr value is calculated using the weighted sum A 2  (t 0  +t 12 )+B 2  (t 4  +t 8 ). Output 153 is thus time multiplexed. 
     A deinterleaver 190 may be provided to separate the multiplexed interpolated output samples. In FIG. 1, demultiplexer 50 has an input 51 connected to output 153 of adder 150 and two outputs, 52 and 53. Operated at one half clock frequency, demultiplexer 50 connects input 51 to output 52 during the first two clock phases and to output 53 during the second two clock phases. In this way, the multiplexed interpolated Cb and Cr output samples may be separated and steered to their respective output lines 52, 53. Alternatively, the deinterleaver 190 may be omitted in applications where subsequent stages operate on multiplexed data streams. 
     Alternatively, a stream multiplexer 400 as shown in FIG. 3 may be provided to create a data stream having the samples alternate every sample instead of every second sample. Referring to FIG. 3, a delay line 410 which is clocked using the 27 MHz clock has an input 411, a one clock delay tap and a two clock delay tap 412 and 413, respectively. Similar to the labeling conventions used in FIG. 1, the delay line input 411 and two taps are respectively labeled t 0 , t 1 , and t 2 , respectively representing a zero, one, and two clock delay. 
     Multiplexer 430 has three inputs A (433), B (432), and C (431), and an output 434. Multiplexer 430 is also clocked at the 27 MHz clock rate and is synchronized to the four clock cycle of filter 100 in FIG. 1. During clock phases φ 0  and φ 1 , multiplexer 430 provides the samples from the B input 432 on output 434. During clock phase φ 2  samples from the A input 433 are provided on output 434 and the samples from the C input 431 are provided on the output during clock phase φ 3 . 
     The overall operation of stream multiplexer 400 will now be described assuming an input sample stream having a sequence of Cb0, Cb1, Cr0, Cr1, Cb2, Cb3, Cr2, etc. During the first clock phase, φ 0 , Cb0 is presented to input 411, yielding t 0  =Cb0. The delay line 410 is empty, leaving t 1  and the output undefined. During the second clock phase, φ 1 , Cb1 is presented to the input 411, and Cb0 is shifted to the first tap yielding t 0  =Cb1 and t 1  =Cb0. Cb0 is therefore output during the second clock phase. In the third clock phase, φ 2 , t 0  =Cr0), t 1  =Cb1, and t 2  =Cb0 and Cr0 is output. In the fourth clock phase, φ 3 , t 0  =Cr1, t 1  =Cr0, and t 2  =Cb1. Cb1 is output during the fourth clock phase, φ 3 . Finally the next clock starts a new first phase φ 0  during which, Cr1 shifted to the t 1  position and is output by the multiplexer. It will be appreciated that the stream multiplexer of FIG. 3 may be used to restore the output of filter 100 to an alternating sample stream in which adjacent samples from each data stream are interlaced with samples from the other stream. 
     Referring to FIG. 2, a second stage interpolator is used to demonstrate another aspect of the present invention. As with FIG. 1, the filter components of filter 200 are operated at a clock frequency of 27 MHz unless otherwise noted. The operation of filter 200 in FIG. 2 will be described in terms of a two clock cycle with each clock cycle being labeled phases φ 0  and φ 1 . 
     Filter 200 accepts 13.5 MHz Cr and Cb data streams as inputs, performs a second stage of 1-to-2 interpolation, and provides two 27 MHz interpolated data streams as outputs. An input multiplexer 380 may be used to accept two 13.5 MHz data streams Cr and Cb on multiplexer inputs 381 and 382, respectively. During the first clock phase, φ 0 , Cb samples from input 382 are provided to filter input 211. Similarly, the Cr samples from input 381 are provided to input 211 during the second clock phases, φ 1 . A 27 MHz multiplexed data stream is provided to input 211 of filter 200 by output 383 of multiplexer 380. The multiplexed data stream includes alternating interlaced Cr and Cb samples. Alternatively, a multiplexed data stream may be provided directly to input 211 omitting multiplexer 380. In another alternative, the second stage filter 200 may be cascaded onto the output of the first stage filter 100 using the stream multiplexer 400 of FIG. 3 between the output 153 of Filter 100 and the input 211 of filter 200. 
     Filter input 211 is connected to the input to of delay line 210. Eight tapped delay outputs t 1  (212), t 2  (213), t 3  (214), t 4  (215), t 5  (216), t 6  (217), t 7  (218), and t 8  (219) on delay line 210 respectively provide 1, 2, 3, 4, 5, 6, 7, and 8 clock delays. Assume that the multiplexed input data stream contains samples Cb0, Cr0, Cb1, Cr1, Cb2, Cr2, etc. in sequence. Delay line 210 will then fill with samples Cb0 in t 8 , Cr0 in t 7 , Cb1 in t 6 , Cr1 in t 5 , Cb2 in t 4 , Cr2 in t 3 , Cb3 in t 2 , Cr3 in t 1 , and Cb4 in t 0 . The even delay taps t 0 , t 2 , t 4 , t 6 , and t 8  will contain the Cb samples on the even clock phases φ 0  and the Cr samples on the odd phases φ 1 . Conversely, the odd delay taps will contain the Cb samples during the odd clock phases φ 1  and the Cr samples during the even clock phases φ 0 . 
     The adders 310, 320, 330, 340, 350, 360, and 370 and the multipliers 220, 230, 240, 250, and 260 operate in the same manner as described in connection with FIG. 1. Adder 310 having an input 311 connected to t 0  and an input 312 connected to t 8  forms a sum t 0  +t 8  every clock cycle on output 313. Multiplier 220 having an input 221 connected to adder 310 and an input 222 for receiving weighting coefficient D forms the product D(t 0  +t 8 ) on its output 223. Similarly, adder 330 and multiplier 240 together form the weighted sum F(t 2  +t 6 ). Adder 360 having inputs 361 and 362 respectively connected to outputs 243 and 223 of multipliers 240 and 240 forms the sum of D(t 0  +t 8 )+F(t 2  +t 6 ) on its output 363. Adder 350 combines the output 363 of adder 360 with the product of H(t 4 ) from multiplier 260 forming the sum D(t 0  +t 8 )+F(t 2  +t 6 )+H(t 4 ) on its output 353. 
     Adder 320 having an input 321 connected to t 1  and an input 322 connected to t 7  forms a sum t 1  +t 7  every clock cycle on output 323. Multiplier 230 having an input 231 connected to adder 320 and an input 232 for receiving weighting coefficient E forms the product E(t 1  +t 7 ) on its output 233. Similarly, adder 340 and multiplier 250 together form the weighted sum G(t 3  +t 5 ). Adder 370 having inputs 371 and 372 respectively connected to outputs 233 and 253 of multipliers 230 and 250 forms the sum of E(t 1  +t 7 )+G(t 3  +t 5 ) on its output 373. 
     In each two clock cycle, two interpolated Cb and two interpolated Cr values are output by filter 200. In the even clock cycles φ 0 , output 353 provides an interpolated Cb value according to the weighted sum D(t 0  +t 8 )+F(t 2  +t 6 )+H(t 4 ) and output 373 provides an interpolated Cr value according to the weighted sum E(t 1  +t 7 )+G(t 3  +t 5 ). During the odd clock cycles φ 1 , output 353 provides a second interpolated Cr value according to the weighted sum D(t 0  +t 8 )+F(t 2  +t 6 )+H(t 4 ) and output 373 provides a second interpolated Cb value according to the weighted sum E(t 1  +t 7 )+G(t 3  +t 5 ). Each output 353 and 373 thus provides a multiplexed data stream consisting of the interpolated and interlaced Cr and Cb values. 
     Crossbar switch 390 may be used to separate the multiplexed outputs into their respective components by steering output 353 to filter output 394 and output 373 to filter output 393 during the even phases φ 0  and reversing during the odd phases φ 1 . During the odd phases, output 353 is connected to filter output 393 and output 373 is connected to filter output 394. 
     The filters 100 and 200 and multiplexer 400 may be synchronized by setting a clock phase counter to the starting phase, φ 0  with the introduction of each data sample to the input of filter 100. 
     In alternative embodiments, different filter configurations may be implemented providing additional flexibility. Referring to filter 100 in FIG. 1 for example, multiplexers 60 and 70 may be omitted where the weighting coefficients are the same for the even and odd sums. Alternatively, four-to-one multiplexers may be provided at the multiplier inputs for filter implementations that provide a different response for each data stream. In such cases, the filter 100 would provide four different responses, an odd and even response for each data stream. In a non-interpolating embodiment, multiplexer 10 may be operated at the full clock frequency allowing multiplexers 60 and 70 to be used to provide different filter responses for each data stream. Similarly, four-to-one multiplexers operated at the full clock frequency may be provided at the input to delay line 110 and at the multiplier inputs to provide a four data stream filter having different responses for each data stream. 
     From the foregoing description it will be apparent that improvements in finite impulse response filters and methods have been provided to reduce the complexity and cost and improve the performance of the filters. While preferred embodiments have been described, it will be appreciated that variations and modifications of the herein described systems and methods, within the scope of the invention will be apparent to those of skill in the art. Accordingly, the foregoing description should be taken as illustrative and not in a limiting sense.