Abstract:
A device and a method for controlling a photosensitive cell including a photodiode adapted to discharging into a read node via a MOS transfer transistor, the device being adapted to providing a signal for controlling the gate of the MOS transfer transistor to a first level for which the MOS transfer transistor is off or to a second level for which the MOS transfer transistor is on, including means for providing a transition control signal between the second level and the first level of determined average slope.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to the control of a photosensitive cell made in monolithic form of an image sensor intended to be used in shooting devices such as, for example, shooting cameras, camcorders, digital microscopes, or digital cameras. More specifically, the present invention relates to a photosensitive cell based on semiconductors.  
           [0003]    2. Discussion of the Related Art  
           [0004]    [0004]FIG. 1 schematically shows the circuit of a photosensitive cell of a photosensitive cell array of an image sensor. With each photosensitive cell of the array are associated a precharge device and a read device. The precharge device is formed of an N-channel MOS transistor M 1 , interposed between a supply rail Vdd and a read node S. The gate of precharge transistor M 1  receives a precharge control signal RST. The read device is formed of the series connection of two N-channel MOS transistors, M 2 , M 3 . The drain of first read transistor M 2  is connected to supply rail Vdd. The source of second read transistor M 3  is connected to input terminal P of an electronic processing circuit (not shown). The gate of first read transistor M 2  is connected to read node S. The gate of second read transistor M 3  is capable of receiving a read signal RD. The photosensitive cell comprises a charge storage diode D 1  having its anode connected to a reference supply rail or circuit ground GND and its cathode directly connected to node S. The photosensitive diode comprises a photodiode D 2  having its anode connected to reference supply rail GND and its cathode connected to node S via an N-channel charge transfer MOS transistor M 4 . The gate of charge transfer transistor M 4  is capable of receiving a charge transfer control signal T. Generally, signals R D , RST, and T are provided by control circuits not shown in FIG. 1 and can be provided to all the photosensitive cells of a same row of the cell array.  
           [0005]    [0005]FIG. 2 shows an example of a timing diagram of signals R D , RST, T, and of voltage V RD  at node S of the circuit of FIG. 1 for a read cycle of the photosensitive cell of FIG. 1. Signals R D , RST, and T are binary signals varying between high and low levels that can be different for each of the signals.  
           [0006]    Between two read cycles of the photosensitive cell, signal T is low. Transfer transistor M 4  is thus off. The lighting causes the forming and the storage of charges at the level of photodiode D 2 . Further, signal RST is high. Precharge transistor M 1  is thus on. Voltage V RD  is then substantially equal to voltage Vdd.  
           [0007]    At a time t 0 , the array row containing the photosensitive cell to be read is selected by setting, to the high level, signal R D . The precharge of read node S is interrupted by setting at time t 1  signal RST to the low state, thus turning off precharge transistor M 1 . Voltage V RD  at read node S is then set to a precharge level V RST  which can be lower than voltage Vdd due to a coupling with precharge transistor M 1 . Precharge level V RST  is generally disturbed by noise essentially originating from the thermal noise of the channel of precharge transistor M 1 . This noise is sampled and maintained on charge storage diode D 1  upon turning-off of precharge transistor M 1 . Precharge level V RST  is then stored outside of the photosensitive cell via read transistors M 2 , M 3 .  
           [0008]    At time t 2 , signal T is set to the high state. Transfer transistor M 4  is then on; which enables transfer of the charges stored in photodiode D 2  to read node S. Photodiode D 2  is designed so that all the charges stored therein are transferred to read node S. Voltage V RD  then decreases to reach a wanted signal level V RD . Once the charge transfer has been performed, signal T is set at time t 3  to the low level, thus enabling isolating photodiode D 2  again and resuming a cycle of charge forming and storage due to the lighting. Desired signal level V RD  is then read via read transistors M 2 , M 3 . Like precharge level V RST , desired signal level V RD  is especially disturbed by the thermal noise of the channel of precharge transistor M 1 , which has been sampled and maintained on charge storage diode D 1 . The subtraction of signals V RD  and V RST  by the processing circuit enables suppressing the noise of precharge transistor M 1  by a double correlated sampling. Once the reading is over, signal RST is set to the high state at time t 4  to precharge read node S again. Finally, at time t 6 , signal R D  is set to the low state to deselect the photosensitive cell.  
           [0009]    It is possible for diode D 1  not to be formed by a specific component. The function of storing the charges originating from photodiode D 2  is then ensured by the apparent capacitance at read node S which is formed of the capacitances of the sources of transistors M 1  and M 4 , of the input capacitance of transistor M 2 , as well as of all the stray capacitances present at node S.  
           [0010]    [0010]FIG. 3 illustrates, in a partial simplified cross-section view, an implementation in monolithic form of the assembly of photodiode D 2  and of transfer transistor M 4  of FIG. 1. These elements are formed in a same active area of a lightly-doped semiconductor substrate  1  of a first conductivity type, for example, type P (P − ). This substrate for example corresponds to an epitaxial layer on a silicon wafer which forms reference supply rail GND. The active area is delimited by field insulation areas  2 , for example, made of silicon oxide (SiO 2 ), and corresponds to a well  3  of the same conductivity type as underlying substrate  1 , but more heavily doped. Above the surface of well  3  is formed an insulated gate structure  4  possibly provided with lateral spacers. On either side of gate  4 , at the surface of well  3 , are source and drain regions  5  and  6  of the opposite conductive type, for example, N. Drain region  6 , to the right of gate  4 , is heavily doped (N + ). Source region  5  is formed on a much larger surface area than drain region  6  and forms with underlying substrate  3  the junction of photodiode D 2 . Gate  4  and drain  6  form one piece with metallizations (not shown) which enable putting these regions in contact respectively with transfer control signal T and the gate of transistor M 2  (node S). The structure is completed by heavily-doped P-type regions  8  and  9  (P + ). Regions  8  and  9 , underlying areas  2 , are connected to the reference or ground voltage via well  3  and substrate  1 . Photodiode D 2  is of the so-called completely depleted type and comprises, at the surface of its source  5 , a P-type region  7 , shallow and more heavily doped (P + ) than well  3 . Region  7  is in lateral (vertical) contact with region  8 . It is thus permanently maintained at the reference voltage level.  
           [0011]    [0011]FIG. 4 schematically illustrates the voltage levels of the different regions of FIG. 2. The curve in strip-dot lines illustrates the system state just after time t 2 . Heavily-doped P-type regions  7 ,  8 , and  9  are permanently maintained at the reference or ground voltage, for example, 0 V. Region  5  of photodiode D 2 , completely charged, is at a voltage V DC . Transistor M 4  is on. Channel region  3  of transistor M 4  is at a voltage V TR . Region  6  corresponding to node S is at precharge level V RST . Between times t 2  and t 3 , the charges accumulated in region  5  are transferred to region  6 . The curve in full line illustrates the system state just after time t 3 . The charges stored in photodiode D 2  being completely transferred to node S, photodiode D 2  reaches a so-called depletion quiescent level V D  set by the sole characteristics of photodiode D 2 . Transfer transistor M 4  being off, channel region  3  is at 0 V. Region  6  is at the level of wanted signal V RD . Region  5  of photodiode D 2  then forms an empty potential well which refills according to the photodiode lighting.  
           [0012]    Generally, the high level of transfer control signal T applied to the gate of transfer transistor M 4  is such that the voltage in channel region  3  of transistor M 4  is intermediary between depletion level V D , and wanted signal level V RD , in such voltage conditions.  
           [0013]    For denser and denser technologies with photosensitive cells of small dimensions and lower and lower control signals, it becomes difficult to ensure a good charge transfer from photodiode D 2  to read node S.  
           [0014]    To improve the charge transfer, it is possible to increase the high level of signal T applied on the gate of transfer transistor M 4  to increase the intensity of the electric field enabling the charge flow. However, if the level of the channel of transfer transistor M 4  becomes relatively too high with respect to supply voltage Vdd, charges may be stored during the charge transfer in channel region  3  of transfer transistor M 4  due to the capacitive character of transistor M 4 . Charges can thus be sent back to photodiode D 2  at the falling edge of signal T from the high level to the low level at time t 3 . This may translate as an error on the measured wanted signal level V RD  and result in a so-called “trailing” effect upon successive readings of a photosensitive cell, due to the reading of residual charges of the previous image upon reading of the next image.  
         SUMMARY OF THE INVENTION  
         [0015]    The present invention provides a method and a device for controlling a photosensitive cell enabling ensuring complete transfer of the charges from the photodiode to the read node.  
           [0016]    To achieve these and other objects, the present invention provides a device for controlling a photosensitive cell comprising a photodiode adapted to discharging into a read node via a MOS transfer transistor, said device being adapted to providing a signal for controlling the gate of the MOS transfer transistor to a first level for which the MOS transfer transistor is off or to a second level for which the MOS transfer transistor is on, comprising means for providing a transition control signal between the second level and the first level of determined average slope.  
           [0017]    According to an embodiment of the present invention, the device comprises a MOS transistor of a first conductivity type connected to a voltage source at the second level and to a control line, said control line being connected to the gate of the transfer MOS transistor, and a MOS transistor of a second conductivity type connected to said control line and to a terminal of a constant current source, the other terminal of said constant current source being connected to a voltage source at the first level.  
           [0018]    According to an embodiment of the present invention, the device further comprises a constant current source arranged between the transistor of the first conductivity type and the voltage source at the second level.  
           [0019]    According to an embodiment of the present invention, the gates of the transistors of the first and second conductivity types receive a binary signal.  
           [0020]    According to an embodiment of the present invention, the control signal is simultaneously provided to the gates of the transfer transistors of several photosensitive cells.  
           [0021]    The present invention also provides a method for controlling a photosensitive cell, comprising a photodiode adapted to discharging into a read node via a MOS transfer transistor, comprising providing to the gate of the MOS transfer transistor a control signal at a first level to turn off said transfer transistor or at a second level to turn on said transfer transistor, and comprising providing, upon transition from the second level to the first level, a control signal of determined average slope.  
           [0022]    According to an embodiment of the present invention, he control signal is a signal of non-zero finite slope between the second level and the first level.  
           [0023]    According to an embodiment of the present invention, the control signal comprises an intermediary stage with a zero slope between the second level and the first level.  
           [0024]    According to an embodiment of the present invention, the duration of said transition of the control signal from the second level to the first level is greater than 50 ns.  
           [0025]    The foregoing object, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]    [0026]FIG. 1, previously described, shows an electric diagram of a photosensitive cell;  
         [0027]    [0027]FIG. 2, previously described, illustrates a timing diagram of characteristic voltages of the circuit of FIG. 1;  
         [0028]    [0028]FIG. 3, previously described, shows a simplified partial cross-section view of a portion of the circuit of FIG. 1 made in monolithic form;  
         [0029]    [0029]FIG. 4, previously described, schematically illustrates voltage levels in the structure of FIG. 3;  
         [0030]    [0030]FIG. 5 shows a first embodiment of the last stage of a control circuit providing charge transfer control signal T;  
         [0031]    [0031]FIG. 6 shows a timing diagram of voltages characteristic of the circuit of FIG. 1 controlled by the control circuit of FIG. 5;  
         [0032]    [0032]FIG. 7 shows a second embodiment of the last stage of the control circuit; and  
         [0033]    [0033]FIG. 8 shows a timing diagram of voltages characteristic of the circuit of FIG. 1 controlled by the control circuit of FIG. 7. 
     
    
     DETAILED DESCRIPTION  
       [0034]    The same elements have been referred to with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, FIG. 3 is not drawn to scale.  
         [0035]    The present invention comprises providing a charge transfer control signal T having a determined average slope upon transition between the high level and the low level to enable complete transfer of the charges between photodiode D 2  and read node S.  
         [0036]    [0036]FIG. 5 shows a first embodiment of the last stage of a control circuit providing charge transfer control signal T to the gate of transfer transistor M 4 . The control circuit may be connected to a line L connected to all the transfer transistor gates of the photosensitive cells of a same photosensitive cell row. The control circuit comprises a P-type MOS transistor M 5  having its drain connected to a high-level voltage source V TH  and having its source connected to line L. The control circuit comprises an N-type MOS transistor M 6  having its drain connected to line L and having its source connected to a terminal of a constant current source I providing a current of intensity Id. The other terminal of constant current source I is connected to a low-level voltage source V TL . The gates of transistors M 5 , M 6  each receive a binary signal C provided by the preceding stage of the control circuit. According to an alternative of the present invention, the gates of transistors M 5 , M 6  are not connected and each receive a distinct control signal.  
         [0037]    When signal C is low, transistor M 6  is off and transistor M 5  is on. Transfer control signal T is then at high level V TH . When signal C switches high, transistor M 5  is off and transistor M 6  is on. Line L, as seen from the control circuit, exhibits an apparent capacitance C L  originating among others from the gates capacitances of the charge transfer transistors of the different photosensitive cells in the row. Current source I then causes a transition of constant slope of signal T from high level V TH  to low level V TL . The duration of the transition between the high and low levels is given by the following relation:  
           T   d   =C   L ( V   TH   −V   TL )/ I   d    
         [0038]    The constant slope of transfer control signal T is adjusted to enable all the charges present under the gate of transfer transistor M 4  to flow towards read node S before the voltage of the channel of transfer transistor M 4  reaches the reference level, for example, 0 volt. The phenomenon of charges returning to photodiode D 2  is then suppressed. It is desired to obtain a maximum value of T d  of approximately 0.5 μs and preferably of approximately 0.2 μs. For this purpose, one can choose V TH  equal to 3.5 V, V TL  equal to 0 V, and C L  equal to several picofarads.  
         [0039]    [0039]FIG. 6 shows a timing diagram of signals R D , RST, and T of the photosensitive cell of FIG. 1 receiving a transfer control signal T provided by the control circuit of FIG. 5. Duration T d  can be adjusted by intensity I d  of the current provided by current source  1 . Current source I may be formed in any known manner, for example, by a current mirror.  
         [0040]    [0040]FIG. 7 shows a second embodiment of the last stage of the control circuit providing signal T. As compared to the circuit of FIG. 5, the circuit according to the second embodiment comprises a second constant current source I′ providing a current of intensity I d ′ and arranged between the drain of transistor M 5  and the source of high-level voltage V TH . Second constant current source I′ enables ensuring a transition at constant slope of a duration T d ′ of signal T between low level V TL  and high level V TH . Duration T d ′ is given by a relation similar to the expression of duration T d , in which the amount of current I d  is replaced by the amount of current I d ′ provided by constant current source I′.  
         [0041]    Preferably, current sources I, I′ provide currents of the same value so that durations T d  and T d ′ are equal. This enables obtaining symmetrical rising and falling edges of signal T and suppressing unwanted coupling effects which can appear with the control circuit of FIG. 5.  
         [0042]    According to an alternative of the present invention, not shown, the control circuit may provide a transfer control signal T which exhibits upon switching from the high level to the low level one stage or several intermediary stages at constant intermediary levels between high and low levels V TH  and V TL . The intermediary level and the duration of the stage are set to ensure a complete charge transfer from photodiode D 2  to read node S. The intermediary level is such that the voltage of the channel of charge transfer transistor M 4  is smaller than V D  to leave time to the charges present under transistor M 4  to set off to read node S. A stage may also be provided upon transition of signal T from the low level to the high level.  
         [0043]    According to an alternative of the present invention, not shown, the control circuit may provide a transfer control signal T which exhibits upon switching from the high level to the low level one or several portions at non-zero constant slope, it being possible to provide the portions at constant slope between the high level and an intermediary level between the high and low levels, between an intermediary level between the high and low levels and the low level, or between a first intermediary level between the high and low levels and a second intermediary level between the high and low levels smaller than the first intermediary level.  
         [0044]    According to an alternative of the present invention, not shown, transfer control signal T may exhibit upon switching from the high level to the low level a succession of portions at non-zero constant slope or of portions at zero slope.  
         [0045]    According to an alternative of the present invention, not shown, transfer control signal T may exhibit upon switching from the high level to the low level one or several portions at non-constant slope varying according to a determined law.  
         [0046]    According to another alternative of the present invention, two control circuits operating identically may be arranged at both ends of line L.  
         [0047]    Of course, the present invention is likely to have various alterations, modifications, and improvement which will readily occur to those skilled in the art. In particular, the drain of second read MOS transistor M 3  may be connected to supply rail Vdd, and the source of second transistor M 3  may be connected to the drain of first read transistor M 2 . The source of first read transistor M 2  is then connected to input terminal P of the processing circuit. The operation of such a photosensitive cell is similar to what has been described previously. Further, the present invention has been described in the context of a photosensitive cell in which four MOS transistors are associated with a photodiode. However, the present invention may apply to photosensitive cells in which some of the MOS transistors, especially read transistor M 2  and M 3  and precharge transistors M 1 , are put in common between several photodiodes. Further, in the present invention, some of said N-type transistors may be replaced with P-type transistors by accordingly modifying the associated gate control signals.  
         [0048]    Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.