Abstract:
A level shifting circuit includes a charging means consisting of a charging regulator circuit which charges a second node to a logic “H” by setting a second switching circuit to an ON state and thereafter brings back the second switching circuit to an OFF state when a first node is changed from a logic “H” to a logic “L” by a change of an input signal, and charges the first node to the logic “H” by setting a first switching circuit to the ON state and thereafter brings back the first switching circuit to the OFF state when the second node is changed from the logic “H” to the logic “L” by the change of the input signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a level shifting circuit for converting a logical level. 
     2. Description of Related Art 
     FIG. 7 is a circuit diagram to show a conventional level shifting circuit. In a semiconductor device using two types of voltage sources, a low voltage source (VCCL) and a high voltage source (VCCH), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH (VCCL&lt;VCCH). In FIG. 7, reference sign IN_L denotes an input signal having the logical level of the voltage VCCL, sign OUT_H denotes an output signal having the logical level of the voltage VCCH, signs INV 0701 _L and INV 0702 _L denote inverters operating by the low voltage source (VCCL), sign INV 0703  denotes an inverter operating by the high voltage source (VCCH), signs MP 0701  and MP 0702  denote P-type transistors and signs MN 0701  and MN 0702  denote N-type transistors. 
     FIG. 8 is a waveform chart to show an operation of the conventional level shifting circuit. 
     Next, an operation will be discussed. 
     The operation of the level shifting circuit shown in FIG. 7 will be discussed below, referring to the waveform chart of FIG.  8 . In the following discussion, the logic High level of the voltage VCCL is represented as “H_l” level, the logic High level of the voltage VCCH is represented as “H_h” level and the logic Low level (0 V) of these voltages are represented as “L” level. 
     In a state where the input signal IN_L is stationary at the “L” level, a node N 0701  has the “H_l” level and a node N 0702  has the “L” level, and the N-type transistor MN 0701  is in an ON state and the N-type transistor MN 0702  is in an OFF state. Further, a node N 0703  has the “L” level and a node N 0704  has the “H_h” level, and the P-type transistor MP 0701  is in the OFF state and the P-type transistor MP 0702  is in the ON state. The output signal OUT_H has the “L” level. 
     When the input signal IN_L changes from the “L” level to the “H_l” level (t 0  of FIG.  8 ), the node N 0701  comes into the “L” level and the node N 0702  comes into the “H_l” level by the operations of the inverters INV 0701 _L and INV 0702 _L ( 1 ,  2  of FIG. 8) and the N-type transistor MN 0701  comes into the OFF state and the N-type transistor MN 0702  comes into the ON state. At this time, since the P-type transistor MP 0702  remains in the ON state, the potential of the node N 0704  falls to a voltage value V0 obtained by dividing the voltage VCCH by the ON-resistance of the P-type transistor MP 0702  and the ON-resistance of the N-type transistor MN 0702  ( 3  of FIG.  8 ). When the potential of the node N 0704  becomes VCCH−VthP (VthP represents a threshold voltage of the P-type transistor) or lower, the P-type transistor MP 0701  comes into the ON state and the node N 0703  is charged up to the voltage VCCH ( 4  of FIG. 8) and when the potential of the node N 0704  becomes the threshold voltage of the inverter INV 0703  or lower, the output signal OUT_H becomes “H_h” level ( 5  of FIG.  8 ). Further, since the node N 0703  is charged up to the voltage VCCH, the P-type transistor MP 0702  comes into the OFF state and the node N 0704  is completely discharged to 0 V ( 6  of FIG.  8 ). 
     When the input signal IN_L changes from the “H_l” level to the “L” level (t 1  of FIG.  8 ), a series of operation is performed, almost like the above, where the node N 0701  changes to the “H_l” level and the node N 0702  changes to the “L” level ( 11 ,  12  of FIG.  8 ), the N-type transistor MN 0701  comes into the ON state and the N-type transistor MN 0702  comes into the OFF state, the potential of the node N 0703  falls to V0 ( 13  of FIG.  8 ), the P-type transistor MP 0702  comes into the ON state, the potential of the node N 0704  rises up to the voltage VCCH ( 14  of FIG.  8 ), and then when the potential of the node N 0704  becomes the threshold voltage of the inverter INV 0703  or higher, the output signal OUT_H changes to the “L” level ( 15  of FIG. 8) and the potential of the node N 0703  changes to 0 V ( 16  of FIG.  8 ). 
     As discussed above, there is a case in the conventional level shifting circuit, where the P-type transistor MP 0701  and the N-type transistor MN 0701  come into the ON state at the same time or where the P-type transistor MP 0702  and the N-type transistor MN 0702  come into the ON state at the same time ( 3 ,  13  of FIG.  8 ), and the voltage V0 of the node N 0701  or the node N 0702  at that time should be VCCH−VthP or lower. Assuming that the ON-resistance of the P-type transistor is RonP and the ON-resistance of the N-type transistor is RonN, since V0=VCCH*RonN/(RonP+RonN), it is necessary to satisfy a relation RonP&gt;RonN in order to set V0 to a low value to some degree. Further, assuming that the channel width of a transistor is W and the channel length thereof is L, since the ON-resistance thereof is in proportion to L/W, it is necessary to set the channel width W smaller and/or the channel length L larger in order to increase the ON-resistance and it is necessary to set the channel width W larger and/or the channel length L smaller in order to decrease the ON-resistance. 
     Since the conventional level shifting circuit has the above constitution, since a gate-source voltage (VCCL) at the time when the N-type transistors MN 0701  and MN 0702  are in the ON state is lower than a gate-source voltage (−VCCH) at the time when the P-type transistors MP 0701  and MP 0702  are in the ON state, the ON-resistance RonN of the N-type transistor is hard to reduce even if L/W of the N-type transistors MN 0701  and MN 0702  is made smaller, and this tendency is accelerated as the difference between the voltage VCCH and the voltage VCCL becomes larger. Therefore,in order to satisfy the relation R on P&gt;R on N, it is necessary to set the ON-resistance RonP extremely high. Since the nodes N 0701  and N 0702  are charged by the P-type transistors MP 0701  and MP 0702  ( 4 ,  14  of FIG.  8 ), however, the charging speed becomes lower when the ON-resistance RonP is extremely high, and this causes a problem that a delay time of the output signal OUT_H from the input signal IN_L may increase. 
     In contrast to this, though it is possible to satisfy the relation RonP&gt;RonN with RonP kept low to some degree by setting L/W of the N-type transistors MN 0701  and MN 0702  extremely smaller than L/W of the P-type transistors MP 0701  and MP 0702 , since a value (RonP+RonN) becomes small in this case, a through current which flows when the P-type transistor MP 0701  and the N-type transistor MN 0701  come into the ON state at the same time or the P-type transistor MP 0702  and the N-type transistor MN 0702  come into the ON state at the same time becomes large and this increases the power consumption. 
     SUMMARY OF THE INVENTION 
     The present invention is intended to solve the above described problems and it is an object of the present invention to provide a level shifting circuit which realized an increase of the potential difference allowing the logic-level conversion and a reduction of the delay time and the through current. 
     In the level shifting circuit in accordance with the present invention, a charging means is made up of a first P-type transistor and a second P-type transistor whose drains are connected to said first and second nodes respectively, whose gates are connected to said second and first nodes respectively and whose sources are connected to said second voltage source; a first switching circuit and a second switching circuit connected in parallel to said first and second P-type transistors respectively, and keeping an OFF state at a stationary state when said input signal does not change; and a charging regulator circuit which charges said second node to a logic “H” by setting said second switching circuit to an ON state and thereafter brings back said second switching circuit to an OFF state when said first node is changed from a logic “H” to a logic “L” by a change of said input signal, and charges said first node to the logic “H” by setting said first switching circuit to the ON state and thereafter brings back said first switching circuit to the OFF state when said second node is changed from the logic “H” to the logic “L” by the change of said input signal. 
     As discussed above, according to the present invention, since the ON-resistances of the first and second P-type transistors are set extremely high, a through current which flows when the first P-type transistor and the first N-type transistor come into the ON state at the same time or when the second P-type transistor and the second N-type transistor come into the ON state at the same time, can be made extremely small. 
     Further, even if the ON-resistances of the first and second N-type transistors become relatively large because the difference of the first and second voltage sources becomes large, it is possible to reduce the divided voltage value. 
     Furthermore, since no through current flows through the first and second switching circuits for charging the first and second nodes, it is possible to optimize the ON-resistances thereof with a high priority given to charging speed and avoid an increase in delay time caused by lower power consumption. 
     Thus, the present invention produces an effect of providing a level shifting circuit which increases the potential difference allowing the logic-level conversion and reduces the delay time and the through current. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram to show a level shifting circuit in accordance with a first preferred embodiment of the present invention; 
     FIG. 2 is a waveform chart to show an operation of the level shifting circuit in accordance with the first preferred embodiment of the present invention; 
     FIG. 3 is a circuit diagram to show a level shifting circuit in accordance with a second preferred embodiment of the present invention; 
     FIG. 4 is a waveform chart to show an operation of the level shifting circuit in accordance with the second preferred embodiment of the present invention; 
     FIG. 5 is a circuit diagram to show a level shifting circuit in accordance with a third preferred embodiment of the present invention; 
     FIG. 6 is a waveform chart to show an operation of the level shifting circuit in accordance with the third preferred embodiment of the present invention; 
     FIG. 7 is a circuit diagram to show a conventional level shifting circuit; and 
     FIG. 8 is a waveform chart to show an operation of the conventional level shifting circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereafter, the preferred embodiments of the present invention will be discussed. 
     First Preferred Embodiment 
     FIG. 1 is a circuit diagram to show a level shifting circuit in accordance with the first preferred embodiment of the present invention. In a semiconductor device using two types of voltage sources, a low voltage source (VCCL: the first voltage source) and a high voltage source (VCCH: the second voltage source), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH. In FIG. 1, reference sign IN_L denotes an input signal having the logical level of the voltage VCCL and sign OUT_H denotes an output signal having the logical level of the voltage VCCH. Reference sign INV 0101 _L denotes an inverter operating by the low voltage source (VCCL), to which the input signal IN_L is inputted. Reference sign INV 0102 _L denotes an inverter operating by the low voltage source (VCCL), whose input is an output of the inverter INV 0101 _L (node N 0101 ). 
     Reference sign MN 0101  denotes an N-type transistor (the first N-type transistor) whose drain is connected to a node N 0103  (the first node), gate is connected to the output of the inverter INV 0101 _L (node N 0101 ) and source is grounded. Reference sign MN 0102  denotes an N-type transistor (the second N-type transistor) whose drain is connected to a node N 0104  (the second node), gate is connected to an output of the inverter INV 0102 _L (node N 0102 ) and source is grounded. 
     Reference sign MP 0101  denotes a P-type transistor (the first P-type transistor) whose drain is connected to the node N 0103 , gate is connected to the node N 0104  and source is connected to the high voltage source (VCCH). Reference sign MP 0102  denotes a P-type transistor (the second P-type transistor) whose drain is connected to the node N 0104 , gate is connected to the node N 0103  and source is connected to the high voltage source (VCCH). Reference sign MP 0103  denotes a P-type transistor (the first switching circuit, the third P-type transistor) connected in parallel to the P-type transistor MP 0101 , and sign MP 0104  denotes a P-type transistor (the second switching circuit, the fourth P-type transistor) connected in parallel to the P-type transistor MP 0102 . 
     Reference signs NOR 0101  and NOR 0102  denote NOR gates (the first and second NOR gates) operating by the high voltage source (VCCH), whose respective outputs (node N 0105  and node N 0106 ) are connected to gate inputs of the other NOR gates, to form a RS flip-flop (charging regulator circuit). An input of this RS flip-flop on the side of NOR gate NOR 0101  is connected to the node N 0104  and an input on the side of NOR gate NOR 0102  is connected to the node N 0103 . Reference sign NOR 0103  denotes a NOR gate (charging regulator circuit, the third NOR gate) operating by the high voltage source (VCCH), whose input is connected to the nodes N 0104  and N 0105 . Reference sign INV 0104  denotes an inverter (charging regulator circuit, the first inverter) operating by the high voltage source (VCCH), whose input is connected to an output of the NOR gate NOR 0103  and output is connected to a gate of the P-type transistor MP 0103  (node N 0107 ). Reference sign NOR 0104  denotes a NOR gate (charging regulator circuit, the fourth NOR gate) operating by the high voltage source (VCCH), whose input is connected to the nodes N 0103  and N 0106 . Reference sign INV 0105  denotes an inverter (charging regulator circuit, the second inverter) operating by the high voltage source (VCCH), whose input is connected to an output of the NOR gate NOR 0104  and output is connected to a gate of the P-type transistor MP 0104  (node N 0108 ). 
     Reference sign INV 0103  denotes an inverter operating by the high voltage source (VCCH), whose input is connected to the node N 0104  and output is the output signal OUT_H. 
     In the present constitution, the ON-resistances of the P-type transistors MP 0101  and MP 0102  are set extremely high and the ON-resistances of the P-type transistors MP 0103  and MP 0104  are set to a value which allows the nodes N 0103  and N 0104  to be charged at an adequate speed. The ON-resistances of the N-type transistors MN 0101  and MN 0102  are set to a value which allows the nodes N 0103  and N 0104  to be discharged at an adequate speed. 
     FIG. 2 is a waveform chart to show an operation of the level shifting circuit in accordance with the first preferred embodiment of the present invention. 
     Next, an operation will be discussed. 
     The operation of the discussed-above level shifting circuit will be discussed below, referring to the waveform chart of FIG.  2 . 
     In a state where the input signal IN_L is stationary at the “L” level, the node N 0101  has the “H_l” level and the node N 0102  has the “L” level, and the N-type transistor MN 0101  is in an ON state and the N-type transistor MN 0102  is in an OFF state. Further, the node N 0103  has the “L” level and the node N 0104  has the “H_h” level, and the P-type transistor MP 0101  is in the OFF state and the P-type transistor MP 0102  is in the ON state. The output signal OUT_H has the “L” level. In the RS flip-flop consisting of the NOR gates NOR 0101  and NOR 0102 , the node N 0105  is set to the “L” level and the node N 0106  is set to the “H_h” level. Gates of the P-type transistors MP 0103  and MP 0104  (node N 0107  and node N 0108 ) both have the “H_h” level and the P-type transistors MP 0103  and MP 0104  are in the OFF state. 
     When the input signal IN_L changes from the “L” level to the “H_l” level (t 0  of FIG.  2 ), the node N 0101  comes into the “L” level and the node N 0102  comes into the “H_l” level by the operations of the inverters INV 0101 _L and INV 0102 _L ( 1 ,  2  of FIG. 2) and the N-type transistor MN 0101  comes into the OFF state and the N-type transistor MN 0102  comes into the ON state. At this time, since the P-type transistor MP 0102  remains in the ON state, the potential of the node N 0104  falls to a voltage value V1 obtained by dividing the voltage VCCH by the ON-resistance of the P-type transistor MP 0102  and the ON-resistance of the N-type transistor MN 0102  ( 3  of FIG.  2 ). When the potential of the node N 0104  becomes the threshold voltage of the NOR gate NOR 0103  or lower, the node N 0107  comes into the “L” level ( 4  of FIG. 2) and when the potential of the node N 0104  becomes the threshold voltage of the inverter INV 0103  or lower, the output signal OUT_H becomes “H_h” level ( 5  of FIG.  2 ). When the node N 0107  comes into the “L” level, the P-type transistor MP 0103  comes into the ON state to charge the node N 0103  up to the voltage VCCH ( 6  of FIG.  2 ). When the node N 0103  comes into the “H_h” level, the P-type transistor MP 0102  comes into the OFF state and the node N 0104  is completely discharged to 0 V ( 7  of FIG.  2 ), and in the RS flip-flop consisting of the NOR gates NOR 0101  and NOR 0102 , the node N 0105  is set to the “H_h” level and the node N 0106  is set to the “L” level ( 8 ,  9  of FIG.  2 ). When the node N 0105  comes into the “H_h” level, the node N 0107  comes into the “H_h” level and the P-type transistor MP 0103  comes into the OFF state ( 10  of FIG.  2 ). Since the P-type transistor MP 0101  is in the ON state at the time when the potential of the node N 0104  becomes VCCH−VthP (VthP represents the threshold voltage of the P-type transistor) or lower ( 3  of FIG.  2 ), the “H_h” level of the node N 0103  is kept. The above is a series of operation of the level shifting circuit, which is caused by the change of the input signal IN_L from the “L” level to the “H_l” level. 
     An operation in the case where the input signal IN_L changes from the “H_l” level to the “L” level (t 1  of FIG. 2) is the same as above, and potential changes of the respective nodes are shown by  11  to  20  of FIG.  2 . 
     Thus, in the first preferred embodiment, since the ON-resistances of the P-type transistors MP 0101  and MP 0102  are set extremely high, the through current which flows when the P-type transistor MP 0101  and the N-type transistor MN 0101  come into the ON state at the same time or when the P-type transistor MP 0102  and the N-type transistor MN 0102  come into the ON state at the same time can be made extremely small. Moreover, even if the ON-resistances of the N-type transistors MN 0101  and MN 0102  becomes relatively larger as the difference between the voltage VCCL and the voltage VCCH becomes large, it is possible to reduce the value of V1. Further, since no through current flows through the P-type transistors MP 0103  and MP 0104  for charging the nodes N 0103  and N 0104 , it is possible to optimize the ON-resistances thereof with a high priority given to charging speed and avoid an increase in delay time caused by lower power consumption. 
     Second Preferred Embodiment 
     FIG. 3 is a circuit diagram to show a level shifting circuit in accordance with the second preferred embodiment of the present invention. In the second preferred embodiment, the NOR gates which are constituents of the first preferred embodiment are replaced by NAND gates. 
     In a semiconductor device using two types of voltage sources, the low voltage source (VCCL) and the high voltage source (VCCH), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH. In FIG. 3 reference sign IN_L denotes the input signal having the logical level of the voltage VCCL and sign OUT_H denotes the output signal having the logical level of the voltage VCCH. Reference sign INV 0301 _L denotes an inverter operating by the low voltage source (VCCL), to which the input signal IN_L is inputted. Reference sign INV 0302 _L denotes an inverter operating by the low voltage source (VCCL), whose input is an output of the inverter INV 0301 _L (node N 0301 ). 
     Reference sign MN 0301  denotes an N-type transistor whose drain is connected to a node N 0303 , gate is connected to the output of the inverter INV 0301 _L (node N 0301 ) and source is grounded. Reference sign MN 0302  denotes an N-type transistor whose drain is connected to a node N 0304 , gate is connected to an output of the inverter INV 0302 _L (node N 0302 ) and source is grounded. 
     Reference sign MP 0301  denotes a P-type transistor whose drain is connected to the node N 0303 , gate is connected to the node N 0304  and source is connected to the high voltage source (VCCH). Reference sign MP 0302  denotes a P-type transistor whose drain is connected to the node N 0304 , gate is connected to the node N 0303  and source is connected to the high voltage source (VCCH). Reference sign MP 0303  denotes a P-type transistor connected in parallel to the P-type transistor MP 0301 , and sign MP 0304  denotes a P-type transistor connected in parallel to the P-type transistor MP 0302 . Reference signs INV 0304  and INV 0305  denote inverters (charging regulator circuit, the first and second inverters) whose inputs are connected to the nodes N 0304  and N 0303  respectively, operating by the high voltage source (VCCH). Reference signs NAND 0301  and NAND 0302  denote NAND gates (the first and second NAND gates) operating by the high voltage source (VCCH) and the respective outputs (node N 0305  and node N 0306 ) are connected to gate inputs of the other NAND gates, to form a RS flip-flop. An input of this RS flip-flop on the side of NAND gate NAND 0301  is connected to an output of the inverter INV 0304  and an input on the side of NAND gate NAND 0302  is connected to an output of the inverter INV 0305 . Reference sign NAND 0303  denotes a NAND gate (charging regulator circuit, the third NAND gate) operating by the high voltage source (VCCH), whose input is connected to an output of the inverter INV 0304  and the node N 0305  and output is connected to a gate of the P-type transistor MP 0303  (node N 0307 ). Reference sign NAND 0304  denotes a NAND gate (charging regulator circuit, the fourth NAND gate) operating by the high voltage source (VCCH), whose input is connected to an output of the inverter INV 0305  and the node N 0306  and output is connected to a gate of the P-type transistor MP 0304  (node N 0308 ). 
     Reference sign INV 0303  denotes an inverter operating by the high voltage source (VCCH), whose input is connected to the node N 0304  and output is the output signal OUT_H. 
     In the present constitution, the ON-resistances of the P-type transistors MP 0301  and MP 0302  are set extremely high and the ON-resistances of the P-type transistors MP 0303  and MP 0304  are set to a value which allows the nodes N 0303  and N 0304  to be charged at an adequate speed. The ON-resistances of the N-type transistors MN 0301  and MN 0302  are set to a value which allows the nodes N 0303  and N 0304  to be discharged at an adequate speed. 
     FIG. 4 is a waveform chart to show an operation of the level shifting circuit in accordance with the second preferred embodiment of the present invention. 
     Next, an operation will be discussed. 
     The operation of the discussed-above level shifting circuit will be discussed below, referring to FIG.  4 . 
     In a state where the input signal IN_L is stationary at the “L” level, the node N 0301  has the “H_l” level and the node N 0302  has the “L” level, and the N-type transistor MN 0301  is in the ON state and the N-type transistor MN 0302  is in the OFF state. Further, the node N 0303  has the “L” level and the node N 0304  has the “H_h” level, and the P-type transistor MP 0301  is in the OFF state and the P-type transistor MP 0302  is in the ON state. The output signal OUT_H has the “L” level. In the RS flip-flop consisting of the NAND gates NAND 0301  and NAND 0302 , the node N 0305  is set to the “H_h” level and the node N 0306  is set to the “L” level. Gates of the P-type transistors MP 0303  and MP 0304  (node N 0307  and node N 0308 ) both have the “H_h” level and the P-type transistors MP 0303  and MP 0304  are in the OFF state. 
     When the input signal IN_L changes from the “L” level to the “H_l” level (t 0  of FIG.  4 ), the node N 0301  comes into the “L” level and the node N 0302  comes into the “H_l” level by the operations of the inverters INV 0301 _L and INV 0302 _L ( 1 ,  2  of FIG. 4) and the N-type transistor MN 0301  comes into the OFF state and the N-type transistor MN 0302  comes into the ON state. At this time, since the P-type transistor MP 0302  remains in the ON state, the potential of the node N 0304  falls to a voltage value V1 obtained by dividing the voltage VCCH by the ON-resistance of the P-type transistor MP 0302  and the ON-resistance of the N-type transistor MN 0302  ( 3  of FIG.  4 ). When the potential of the node N 0304  becomes the threshold voltage of the inverter INV 0304  or lower, the node N 0307  comes into the “L” level ( 4  of FIG. 4) and when the potential of the node N 0304  becomes the threshold voltage of the inverter INV 0303  or lower, the output signal OUT_H becomes “H_h” level ( 5  of FIG.  4 ). When the node N 0307  comes into the “L” level, the P-type transistor MP 0303  comes into the ON state and the node N 0303  is charged up to the voltage VCCH ( 6  of FIG.  4 ). When the node N 0303  comes into the “H_h” level, the P-type transistor MP 0302  comes into the OFF state and the node N 0304  is completely discharged to 0 V ( 7  of FIG.  4 ), and in the RS flip-flop consisting of the NAND gates NAND 0301  and NAND 0302 , the node N 0305  is set to the “L” level and the node N 0306  is set to the “H_h” level ( 8 ,  9  of FIG.  4 ). When the node N 0305  comes into the “L” level, the node N 0307  comes into the “H_h” level and the P-type transistor MP 0303  comes into the OFF state ( 10  of FIG.  4 ). Since the P-type transistor MP 0301  is in the ON state at the time when the potential of the node N 0304  becomes VCCH−VthP (VthP represents the threshold voltage of the P-type transistor) or lower ( 3  of FIG.  4 ), the “H_h” level of the node N 0303  is kept. The above is a series of operation of the level shifting circuit, which is caused by the change of the input signal IN_L from the “L” level to the “H_l” level. 
     An operation in the case where the input signal IN_L changes from the “H_l” level to the “L” level (t 1  of FIG. 4) is the same as above, and potential changes of the respective nodes are shown by  11  to  20  of FIG.  4 . 
     Thus, in the second preferred embodiment, since the ON-resistances of the P-type transistors MP 0301  and MP 0302  are set extremely high, the through current which flows when the P-type transistor MP 0301  and the N-type transistor MN 0301  come into the ON state at the same time or when the P-type transistor MP 0302  and the N-type transistor MN 0302  come into the ON state at the same time can be made extremely small. Moreover, even if the ON-resistances of the N-type transistors MN 0301  and MN 0302  becomes relatively larger as the difference between the voltage VCCL and the voltage VCCH becomes large, it is possible to reduce the value of V1. Further, since no through current flows through the P-type transistors MP 0303  and MP 0304  for charging the nodes N 0303  and N 0304 , it is possible to optimize the ON-resistances thereof with a high priority given to charging speed and avoid an increase in delay time caused by lower power consumption. 
     Third Preferred Embodiment 
     FIG. 5 is a circuit diagram to show a level shifting circuit in accordance with the third preferred embodiment of the present invention. In the third preferred embodiment, the logic gates which are constituents of the first preferred embodiment are reduced. 
     In a semiconductor device using two types of voltage sources, the low voltage source (VCCL) and the high voltage source (VCCH), the level shifting circuit serves as a circuit which converts the logical level of the voltage VCCL into the logical level of the voltage VCCH. In FIG. 5, reference sign IN_L denotes the input signal having the logical level of the voltage VCCL and sign OUT_H denotes the output signal having the logical level of the voltage VCCH. Reference sign INV 0501 _L denotes an inverter operating by the low voltage source (VCCL), to which the input signal IN_L is inputted. Reference sign INV 0502 _L denotes an inverter operating by the low voltage source (VCCL), whose input is an output of the inverter INV 0501 _L (node N 0501 ). 
     Reference sign MN 0501  denotes an N-type transistor whose drain is connected to a node N 0503 , gate is connected to the output of the inverter INV 0501 _L (node N 0501 ) and source is grounded. Reference sign MN 0502  denotes an N-type transistor whose drain is connected to a node N 0504 , gate is connected to an output of an inverter INV 0502 _L (node N 0502 ) and source is grounded. 
     Reference sign MP 0501  denotes a P-type transistor whose drain is connected to the node N 0503 , gate is connected to the node N 0504  and source is connected to the high voltage source (VCCH). Reference sign MP 0502  denotes a P-type transistor whose drain is connected to the node N 0504 , gate is connected to the node N 0503  and source is connected to the high voltage source (VCCH). Reference signs NOR 0501  and NOR 0502  denote NOR gates operating by the high voltage source (VCCH), whose respective outputs (node N 0505  and node N 0506 ) are connected to gate inputs of the other NOR gates, to form a RS flip-flop. An input of this RS flip-flop on the side of NOR gate NOR 0501  is connected to the node N 0504  and an input on the side of NOR gate NOR 0502  is connected to the node N 0503 . Reference signs MP 0503  and MP 0504  denote P-type transistors (the first switching circuit, the third and fourth P-type transistors) which are inserted, being connected in series to each other, between the high voltage source (VCCH) and the node N 0503 , and a gate of the P-type transistor MP 0503  is connected to the node N 0504  and a gate of the P-type transistor MP 0504  is connected to the node N 0505 . Reference signs MP 0505  and MP 0506  denote P-type transistors (the second switching circuit, the fifth and sixth P-type transistors) which are inserted, being connected in series to each other, between the high voltage source (VCCH) and the node N 0504 , and a gate of the P-type transistor MP 0505  is connected to the node N 0503  and a gate of the P-type transistor MP 0506  is connected to the node N 0506 . 
     Reference sign INV 0503  denotes an inverter operating by the high voltage source (VCCH), whose input is connected to the node N 0504  and output is the output signal OUT_H. 
     In the present constitution, the ON-resistances of the P-type transistors MP 0501  and MP 0502  are set extremely high. The ON-resistances of the P-type transistors MP 0503  and MP 0504  are set to a value which allows the node N 0503  to be charged at an adequate speed, and the ON-resistances of the P-type transistors MP 0505  and MP 0506  are set to a value which allows the node N 0506  to be charged at an adequate speed. The ON-resistances of the N-type transistors MN 0501  and MN 0502  are set to a value which allows the nodes N 0503  and N 0504  to be discharged at an adequate speed. 
     FIG. 6 is a waveform chart to show an operation of the level shifting circuit in accordance with the third preferred embodiment of the present invention. 
     Next, an operation will be discussed. 
     The operation of the discussed-above level shifting circuit will be discussed below, referring to the waveform chart of FIG.  6 . 
     In a state where the input signal IN_L is stationary at the “L” level, the node N 0501  has the “H_l” level and the node N 0502  has the “L” level, and the N-type transistor MN 0501  is in the ON state and the N-type transistor MN 0502  is in the OFF state. Further, the node N 0503  has the “L” level and the node N 0504  has the “H_h” level, and the P-type transistor MP 0501  is in the OFF state and the P-type transistor MP 0502  is in the ON state. The output signal OUT_H has the “L” level. In the RS flip-flop consisting of the NOR gates NOR 0501  and NOR 0502 , the node N 0505  is set to the “L” level and the node N 0506  is set to the “H_h” level. At this time, the P-type transistor MP 0503  is in the OFF state and the P-type transistor MP 0504  is in the ON state, which are connected in series to each other, and the P-type transistor MP 0505  is in the ON state and the P-type transistor MP 0506  is in the OFF state, which are connected in series to each other. 
     When the input signal IN_L changes from the “L” level to the “H_l” level (t 0  of FIG.  6 ), the node N 0501  comes into the “L” level and the node N 0502  comes into the “H_l” level by the operations of the inverters INV 0501 _L and INV 0502 _L ( 1 ,  2  of FIG. 6) and the N-type transistor MN 0501  comes into the OFF state and the N-type transistor MN 0502  comes into the ON state. At this time, since the P-type transistor MP 0502  remains in the ON state, the potential of the node N 0504  falls to a voltage value V1 obtained by dividing the voltage VCCH by the ON-resistance of the P-type transistor MP 0502  and the ON-resistance of the N-type transistor MN 0502  ( 3  of FIG.  6 ). When the potential of the node N 0504  becomes VCCH−VthP (VthP represents the threshold voltage of the P-type transistor) or lower, the node N 0503  comes into the ON state and when the potential of the node N 0504  becomes the threshold voltage of the inverter INV 0503  or lower, the output signal OUT_H becomes “H_h” level ( 4  of FIG.  6 ). When the node N 0503  comes into the ON state, since the P-type transistors MP 0503  and MP 0504  which are connected in series to each other both come into the ON state, the node N 0503  is charged up to the voltage VCCH ( 5  of FIG.  6 ). When the node N 0503  comes into the “H_h” level, the P-type transistor MP 0502  comes into the OFF state and the node N 0504  is completely discharged to 0 V ( 6  of FIG.  6 ), and in the RS flip-flop consisting of the NOR gates NOR 0501  and NOR 0502 , the node N 0505  is set to the “H_h” level and the node N 0506  is set to the “L” level ( 7 ,  8  of FIG.  6 ). When the node N 0505  comes into the “H_h” level, the P-type transistor MP 0504  comes into the OFF state. Since the P-type transistor MP 0501  is in the ON state at the time when the potential of the node N 0504  becomes VCCH−VthP (VthP represents the threshold voltage of the P-type transistor) or lower ( 3  of FIG.  6 ), the “H_h” level of the node N 0503  is kept. The above is a series of operation of the level shifting circuit, which is caused by the change of the input signal IN_L from the “L” level to the “H_l” level. 
     An operation in the case where the input signal IN_L changes from the “H_l” level to the “L” level (t 1  of FIG. 6) is the same as above, and potential changes of the respective nodes are shown by  11  to  18  of FIG.  6 . 
     Thus, in the third preferred embodiment, since the ON-resistances of the P-type transistors MP 0501  and MP 0502  are set extremely high, the through current which flows when the P-type transistor MP 0501  and the N-type transistor MN 0501  come into the ON state at the same time or when the P-type transistor MP 0502  and the N-type transistor MN 0502  come into the ON state at the same time can be made extremely small. Moreover, even if the ON-resistances of the N-type transistors MN 0501  and MN 0502  becomes relatively larger as the difference between the voltage VCCL and the voltage VCCH becomes large, it is possible to reduce the value of V1. Further, since no through current flows through the P-type transistors MP 0503  and MP 0504 , which are connected in series to each other, for charging the nodes N 0503  and N 0504 , or through the P-type transistors MP 0505  and MP 0506 , it is possible to optimize the ON-resistances thereof with a high priority given to charging speed and avoid an increase in delay time caused by lower power consumption.