Abstract:
A liquid crystal display control system comprises a liquid crystal panel, a plurality of data latches for storing digital gray scale data, and a plurality of D/A converters for converting the outputs of the data latches into analog signals to be applied to the liquid crystal panel. The display data is digital signals, and the digital signals are processed up to the D/A converters just before the liquid crystal panel. Afterwards, the digital signals are converted into analog signals in the horizontal display period of relatively slow operating speed, and therefore analog circuits having many adjusting points may be reduced. Accordingly, the adjusting positions are reduced, and the adjusting process in mass production is simplified. In the case of a large screen display, in particular, although the data transfer speed is high, since the display data are digital signals, a high display quality is obtained by transferring the signals without deteriorating the display data. Moreover, the constitution is composed of digital circuits up to the D/A converters just before the liquid crystal panel, and therefore, the power consumption is small, and the economy and portability are excellent, while the mounting area is reduced, thereby realizing a liquid crystal display control system of small size and light weight.

Description:
This application is a continuation of application Ser. No. 07/872,820 filed Apr. 24, 1992 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a liquid crystal display (LCD) control system used in televisions, personal computers, work stations or the like. 
     In communications appliances, information appliances, audio and visual appliances, the signal processing form is recently changing from the analog signal processing to digital data signal processing. These appliances are also in the trend of downsizing, lighter weight and smaller power consumption. As the display devices used in such appliances,the conventional cathode-ray tubes (CRTs) have been gradually replaced by thin and lightweight liquid crystal panels. For example, in personal computers, work stations, televisions, visual telephones and the like, the data signals are processed digitally, and liquid crystal panels are used as display devices, and small and lightweight appliances are realized. Speaking of liquid crystal panels, in order that the liquid crystal may replace the CRT to occupy the throne of display devices, improvement of picture quality and display of high resolution must be both achieved. In the picture quality, especially, multicolor display is demanded. 
     For example, if eight-bit display for each of R, G, B (16,700,000 colors) which is closer to the natural color than four-bit display for each of R, G, B (4,096 colors) is realized, a color tone as close to the natural color as the present CRT display television will be obtained, and the applications of liquid crystal panel will be expanded dramatically. As for the high resolution display, if the high resolution liquid crystal panel in the number of dots as many as the high definition television (HDTV) is realized, the liquid crystal panel will play a major role in the image field in the future. 
     There is hence a increasing demand for a new LCD control system applicable to the multicolor and high resolution tendency, in consideration of suitability to the digital, downsizing and lower power consumption trend of appliances and the future of the liquid crystal panel. 
     Hitherto, in the LCD control system for driving this type of thin film transistor (TFT) liquid crystal panel, a DA converter for converting display data into analog signal and a sample hold circuit for holding and delivering the analog signal were used. 
     FIG. 20 is a structural diagram of a conventional LCD control system. Its operation is described below while referring to FIG. 20. 
     A display controller 2 delivers a gate driver control signal 4 to a gate driver 3 for controlling the gate electrode of a TFT liquid crystal panel 1. The controlled gate driver 3 renders one line valid out of arbitrary lines of the TFT liquid crystal panel 1. The display controller 2 reads out, by a display address signal 6, display data from a video random access memory (RAM) 5 for storing the digital display data. 
     The display data stored in the video RAM 5 is the address data of a RAM 7, and it is converted into gray scale data (color scale data in the case of a color liquid crystal panel) to be applied to the TFT liquid crystal panel 1 by the RAM 7. This is intended to curtail the memory capacity in the video RAM 5 by storing the gray scale data large in data quantity in the RAM 7 functioning as lookup table. Meanwhile, to change the display gray scale level (or display color), it is enough to change the gray scale data of the RAM 7 only, and, advantageously, it can be changed quickly. 
     The converted gray scale data is converted into analog signal by a DA converter 8. Conversion into analog signal is necessary because analog signal is used for charging and discharging of the display signal to the liquid crystal capacitor attached to each pixel of the TFT liquid crystal panel 1. The display signal converted into analog signal is fed into an amplifier 10 by way of an inverting/noninverting circuit 9 composed of such analog circuit as voltage follower and the like. The inverting/noninverting circuit 9 is intended to invert the polarity of the voltage applied to the liquid crystal periodically (generally in frame period), which is an essential function for driving the liquid crystal. The amplifier 10 is to boost the analog signal delivered from the DA converter 8 up to a voltage level (about 10 V) to be applied to the TFT liquid crystal panel 1. A gain and offset control circuit 11 is to adjust the gain and Offset of the amplifier 10 so as to obtain the optimum display quality for liquid crystal display. 
     The TFT liquid crystal panel 1, unlike the CRT, must be driven in the horizontal period unit because the response speed of the TFT is slow. Accordingly, by holding the display signals for the portion of one line, they are produced simultaneously, which is called the line sequential driving. 
     A liquid crystal display signal 12 coming out of the amplifier 10 is fed into a sample hold circuit 15, and is sampled and held. The sample hold circuit 15 is same in the number of horizontal pixels as the TFT liquid crystal panel 1, and therefore the liquid crystal display signal 12 from the amplifier 10 is sampled sequentially by the sample hold circuit 15 designated by a shift register 13 operating at a low voltage (about 5 V). 
     The shift register 13 is the bits in the same number as the number of horizontal pixels of the TFT liquid crystal panel 1, and sequentially transfers pulse 18 generated from the display controller 2 in the horizontal direction by a transfer clock 17. The transfer pulse from the shift register 13 is boosted (to about 10 V) by a level shifter 14, and one of the sample hold circuits 15 is selected, and the liquid crystal display signal 12 is sampled. When all display signals of one line are sampled, the display controller 2 delivers an output timing signal 16 to the sample hold circuit 15, and the sample hold circuit 15 delivers an analog signal to be applied to the TFT liquid crystal panel 1. When the signal is applied to the TFT liquid crystal panel 1, one line out of arbitrary lines designated by the gate driver 3 is displayed. 
     In such conventional constitution of the LCD control system, however, the amplifier 10 having the gain and offset control circuit 11 is required, and in order to obtain an appropriate display quality, plural control points are needed in the gain and offset control circuit 11. Accordingly, the process required in adjustment procedure becomes a bottleneck for mass production. In the case of large-screen display, meanwhile, the data transfer speed is high, and high speed display signals pass through the DA converter 8, inverting/noninverting circuit 9 and amplifier 10, which are all analog circuits. As a result, the display signals are distorted, the display quality deteriorates, and a high resolution required for multicolor display is not obtained. Therefore, even if the DA converter 8 possesses the resolution of eight bits, the resolution after passing through the analog circuits may be lowered to about four bits to six bits. 
     Moreover, in the analog circuits of high speed and large amplitude, regardless of the signal level, the internal circuits possess a bias power source with a large current consumption or a reference current source, and therefore a large current is always flowing. Besides, the supply voltage of analog circuit must be sufficiently large as compared with the signal level of the analog signal to be processed in order to have a sufficient working range (dynamic range) of the operational amplifier. As a result, the analog circuits are large in power consumption, and, although the liquid crystal display device is small and light, the power supply unit becomes larger in size, and the portability is sacrificed, and the working time becomes short if working on batteries. Concerning reduction of size and weight, as compared with the digital circuit advanced in the degree of integration, the analog circuit requires a wide area for mounting to incorporate the diversified parts for composing the circuit including the resistors, capacitors and variable resistors. Thus, the conventional LCD control system involved many problems. 
     The invention is hence intended to solve these problems of the prior art by presenting an LCD control system reduced in the number of adjusting points, improved in mass productivity, capable of obtaining a high display quality, small in power consumption, and small in the mounting area. 
     SUMMARY OF THE INVENTION 
     The present invention relates to an LCD control system comprising a liquid crystal panel, storage means (for example latches, flip flops, memory devices, etc.) for storing digital gray scale data, and plural DA converters for converting the outputs of the storage means into analog signals to be applied to the liquid crystal panel. 
     In the LCD control system of the invention, the display data is digital signals, and the digital signals are processed up to the DA converter just before the liquid crystal panel. Afterwards, the digital signals are converted into analog signals in a horizontal display period  slow in the operating speed relatively, and therefore the analog circuits having many adjusting points may be omitted. Accordingly, the number of adjusting points is reduced, and the adjusting processes in mass production are simplified. Besides, in particular, in the case of large screen display, although the data transfer speed is high, since the display data are digital signals, a high display quality is obtained by transferring signals without deteriorating the display data. In addition, since the structure is composed of digital circuits up to the DA converter just before the liquid crystal panel, the power consumption is small, the economy and portability are excellent, and the mounting area is reduced, so that a compact LCD control system may be realized. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the constitution of LCD control system of an embodiment of the invention, 
     FIG. 2 is a structural diagram showing an output circuit in a first embodiment for composing the LCD control system of the invention, 
     FIG. 3 is a structural diagram showing an output circuit in a second embodiment for composing the LCD control system of the invention, 
     FIG. 4 is a structural diagram showing an output circuit in a third embodiment for composing the LCD control system of the invention, 
     FIG. 5 is a structural diagram showing an output circuit in a fourth embodiment for composing the LCD control system of the invention, 
     FIG. 6 is a structural diagram showing an output circuit in a fifth embodiment for composing the LCD control system of the invention, 
     FIG. 7 is a structural diagram showing an output circuit in a sixth embodiment for composing the LCD control system of the invention, 
     FIG. 8 is a structural diagram showing an output circuit in a seventh embodiment for composing the LCD control system of the invention, 
     FIG. 9 is a structural diagram showing an output circuit in an eighth embodiment for composing the LCD control system of the invention, 
     FIG. 10 is an equivalent circuit diagram in charging operation of the output circuit in FIG. 9, 
     FIGS. 11A, 11B are equivalent circuit diagrams in output operation of analog signal in the output circuit in FIG. 9, 
     FIG. 12 is an operation timing chart of the output circuit in FIG. 9, 
     FIGS. 13 is a structural diagram showing an output circuit in a ninth embodiment for composing the LCD control system of the invention, 
     FIG. 14 is an equivalent circuit diagram in charging operation of the output circuit in FIG. 13, 
     FIG. 15 is a structural diagram showing an output circuit using a resistance type DA converter in a tenth embodiment for composing the LCD control system of the invention, 
     FIG. 16 is a structural diagram showing an output circuit using a resistance type DA converter in an eleventh embodiment for composing the LCD control system of the invention, 
     FIG. 17 is a structural diagram showing an output circuit using a current source type DA converter in a twelfth embodiment for composing the LCD control system of the invention, 
     FIG. 18 is a structural diagram showing an output circuit using a over-sampling method DA converter in a thirteenth embodiment for composing the LCD control system of the invention, 
     FIG. 19 is a timing chart for explaining the operation of the output circuit in FIG. 18, 
     FIG. 20 is a block diagram showing the constitution of a conventional LCD control system. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to FIG. 1, the operation of LCD control system in an embodiment of the invention is described in detail below. 
     FIG. 1 shows a liquid crystal display control system in an embodiment of the invention. A display controller 30 delivers a gate driver control signal 4 to a gate driver 3, and the gate driver 3 renders valid an arbitrary line in a TFT liquid crystal panel 1. The display controller 30 reads out, by a display address signal 6, display data from a video RAM 5. The display data stored in the video RAM 5 is the address data of a RAM 7, and it is converted into gray scale data in the RAM 7. The gray scale data is converted into digital liquid crystal display data 33 after passing through an inverting/noninverting circuit 31. 
     The TFT liquid crystal panel 1 holds the display data for the portion of one line, and delivers simultaneously, which is called line sequential drive. The liquid crystal display data 33 produced from the inverting/noninverting circuit 31 is fed into a data latch 34, and is latched and held. Since the data latches 34 are as many as the number of horizontal pixels of the TFT liquid crystal panel 1, the liquid crystal display data from the inverting/noninverting circuit 31 are sequentially latched in the data latches 34 specified by a shift register 32. 
     The shift register 32 has as many bits as the number of horizontal pixels of the TFT liquid crystal, and transfers the pulse 39 generated by the display controller 30 sequentially in the horizontal direction by transfer clock 38. The pulse 39 which is the output of the shift register 32 specifies one data latch 34, and sequentially the data latch 34 latches the liquid crystal display data 33. The latched data is boosted by a level shifter 35, and fed into a DA converter 36. When all display data for the portion of oneline are completely latched, the display controller 30 delivers an output timing signal 37 to the DA converter 36, and the DA converter 36 produces an analog signal to be applied to the TFT liquid crystal panel 1. When the data is applied in the TFT liquid crystal panel 1, one line out of arbitrary lines specified by the gate driver 3 is displayed. 
     According to the LED control system in FIG. 1, the DA converter 36 is disposed just before the TFT liquid crystal panel 1, and the gray scale data converted by the RAM 7 is processed directly in the digital form without undergoing analog processing, and therefore high speed analog circuit and control circuit are omitted, and a display screen of high quality is obtained. 
     Besides, the data latches 34 are provided as many as the number of horizontal pixels of the TFT liquid crystal panel 1, and adjustment-free DA converters 36 are provided as many as the number of horizontal pixels for converting the output of the data latches 34 into analog signals to be applied to the TFT liquid crystal panel 1, so that the analog circuits are not needed, and the adjusting points required in amplifier and the like are saved, so that the mass producibility may be enhanced. 
     Still more, since the digital display data is converted into analog signal by the DA converter 36 just before applying signal to the pixels of the TFT liquid crystal panel 1, especially in the case of large screen display, in spite of high data transfer speed, data does not deteriorate, and is displayed in high display quality. At the same time, by transferring the display data without using analog circuits which consume much electric power, the power consumption may be saved. In addition, instead of analog circuits having a large number of parts, the display data can be transferred by the digital circuit which may be advanced in the degree of integration, and therefore; the mounting surface area is reduced, so that a compact excellent LCD control system is realized. 
     Next, a first embodiment of an output circuit comprising a DA converter for composing the LCD control system of the invention is described while referring to FIG. 2. 
     In FIG. 2, n capacitors C 0 , C 1 , . . . , C n-1 , possess a same capacitance C, and one electrode of each one of the capacitors C 0 , C 1 , . . . , C n-1  is grounded. The other electrode of each one of the capacitors C 0 , C 1 , . . . , C n-1  is connected with one terminal of each one of switches S 0 , S 1 , . . . , S n-1  . The switches S 0 , S 1 , . . . , S n-1  are turned on or off by selection signals L 0 , L 1 , . . . , L n-1 , respectively, while the other terminals are commonly connected. 
     The output circuit has a three-terminal operational amplifier 41, and an input signal 42 is fed to a noninverting input terminal B of the operational amplifier 41. The commonly connected terminals of the switches S 0 , S 1 , . . . , S n-1  are connected to the noninverting input terminal B of the operational amplifier 41. The noninverting input terminal B of the operational amplifier 41 is also connected to a power supply V DD  through a charging switch 43, and is grounded through a discharging switch 44. The charging switch 43 is turned on or off by a charging timing signal 45, and the discharging switch 44 is turned on or off by a discharging timing signal 46. The output Y of the operational amplifier 41 is fed back to a inverting input terminal A of the operational amplifier 41 as a feedback signal 47. The output voltage from this output circuit is produced from an output terminal V out . 
     The operation of thus composed output circuit of the LCD control system is explained below. First, the discharging switch 44 is turned on by the discharging timing signal 46, and the charging switch 43 is turned off by the charging timing signal 45. Next, by the selection signals L 0 , L 1 , . . . , L n-1 , all switches S 0 , S 1 , . . . , S n-1  are set in ON state. As a result, the electric charge stored in all capacitors C 0 , C 1 , . . . , C n-1  is discharged. 
     Next, by the discharging timing signal 46, the discharging switch 44 is set in OFF state, and a specified number of swiches out of the switches S 0 , S 1 , . . . , S n-1  are set in ON state by the selection signals L 0 , L 1 , . . . , L n-1 . Consequently, when the charging switch 43 is set in ON state by the charging timing signal 45, a specified number of capacitors of the capacitors C 0 , C 1 , . . . , C n-1  are charged by the specified switches out of the swiches S 0 , S 1 , . . . , S n-1  in ON state. 
     By the charging timing signal 45, the charging switch 43 is set in OFF state, and all switches S 0 , S 1 , . . . , S n-1  are set in ON state by the selection signals L 0 , L 1 , . . . , L n-1 . As a result, all electric charge stored in a specific number of capacitors is equally distributed and averaged in all capacitors C 0 , C 1 , . . . , C n-1 , and the voltage due to the averaged electric charge is generated. Thus generated voltage is fed into the noninverting input terminal B of the operational amplifier 41 as input signal 42. Since the output Y of the operational amplifier 41 is fed to the inverting input terminal A as a feedback signal 47, the operational amplifier 41 is an amplifier with gain of 0 dB, and the voltage entering the noninverting input terminal B is directly delivered to the output terminal V out . 
     Supposing, for example, that specific switches out of the switches S 0 , S 1 , . . . , S n-1  are set in ON state and that A pieces of capacitor out of n capacitors C 0 , C 1 , . . . , C n-1  are charged, the stored electric charge Q may be expressed in Formula (1). 
     
         Q=A×C×V.sub.DD                                 (1) 
    
     After A pieces of capacitor are charged, by setting the charging switch 43 in OFF state and further setting all (i.e. N) switches S 0 , S 1 , . . . , S n-1  in ON state, since the electric charge Q is constant even after the stored electric charge is averaged, assuming the obtained voltage to be V 0 , the following relation is established: 
     
         Q=N×C×V.sub.0                                  (2) 
    
     Therefore, from Formula (1) and (2), we obtain 
     
         V.sub.0 =(A/N)×V.sub.DD                              (3) 
    
     Thus, according to the embodiment in FIG. 2, since the electric charges stored in specific capacitors from the power supply V DD  are distributed and averaged in all capacitors C 0 , C 1 , . . . , C n-1 , by properly selecting the number of capacitors to be charged, a required voltage may be generated without setting multiple reference voltages. Therefore, the number of wirings may be notably curtailed in the LCD control system of the invention. 
     As described herein, since the LCD control system having the output circuit shown in FIG. 2 possesses plural capacitors having an identical capacitance, and switches attached to the individual capacitors, the electric charge is stored in a specified number of capacitors by setting specific switches in ON state. Next, by stopping supply of electric charge to the capacitors, and distributing and averaging the stored electric charge in all capacitors, the voltage averaged by all these capacitors is obtained. By feeding this voltage into the amplifier, an output voltage proportional to the averaged voltage is obtained. In this way, in the LCD control system of the embodiment, by varying the number of switches to be set in ON state, a required voltage may be generated, and it is not necessary to set many reference voltages as in the prior art. Therefore, according to the embodiment in FIG. 2, the number of wirings and the number of circuits may be saved in the LCD control system. 
     Making reference to FIG. 3, a second embodiment of the output circuit comprising a DA converter for composing the LCD control system of the invention is explained below. 
     The output circuit in FIG. 3 possesses eight capacitors CP 0 , CP 1 , . . . , CP k , . . . , CP 7  connected in parallel, and the capacitances of the capacitors CP 0 , CP 1 , . . . , CP 7  are respectively reference capacitances C, 2×C, . . . , 2 k  ×C, . . . , 128×C. 
     The negative side electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  are connected to the inverting input terminal A of the operational amplifier 41, and the positive side electrodes of capacitors CP 0 , CP 1 , . . . , CP 7  are connected to a power supply -V ref  for feeding a reference input voltage through discharging switches SWB 0 , SWB 1 , . . . , SWB 7 , respectively. Furthermore, one of the terminals of each one of charging switches SWA 0 , SWA 1 , . . . , SWA 7  is connected to the positive side electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7 . These charging switches SWA 0 , SWA 1 , . . . , SWA 7  are set in ON state when sampling the input voltage. 
     At the other terminals of the charging switches SWA 0 , SWA 1 , . . . , SWA 7 , one of the terminals of each one of digital input switches SW 0 , SW 1 , . . . , SW 7  is connected. The digital input switches SW 0 , SW 1 , . . . , SW 7  correspond to the bits of the digital signal fed in the output circuit, and are set in ON state when the corresponding bit is 1, and set in OFF state when 0. 
     Furthermore, the other terminals of the digital input switches SW 0 , SW 1 , . . . , SW 7  are connected to a power supply +V ref  for supplying reference input voltage. 
     Switches are composed of the charging switches SWA 0 , SWA 1 , . . . , SWA 7 , discharging switches SWB 0 , SWB 1 , . . . , SWB 7 , and digital input switches SW 0 , SW 1 , . . . , SW 7 . 
     A charging switch SWA 8  is connected between the inverting input terminal A and output terminal of the operational amplifier 41. A charging switch SWA 9  is connected between the positive electrode of a negative feedback capacitor CP 8  and the reference input voltage (power supply) -V ref , and it is set in ON state when sampling the input voltage of the operational amplifier 41. A discharging switch SWB 8  is connected between the positive electrode of the negative feedback capacitor CP 8  and the output V out , and discharges the stored electric charge. 
     The output Y of the operational amplifier 41 is fed back to the inverting input terminal A of the operational amplifier 41 through the charging switch SWA 8 , and is fed back to the inverting input terminal A through the discharging switch SWB 8  and negative feedback capacitor CP 8 . The noninverting input terminal B of the operational amplifier 41 is connected to the reference input voltage (power supply) -V ref , and is connected to the inverting input terminal A through the charging switch SWA 9  and negative feedback capacitor CP 8 . The negative feedback capacitor CP 8  possesses a capacitance of 2 8  ×C (256C) of the reference capacitance. The output voltage generated by this output circuit is produced from the output terminal V out . 
     The operation of thus composed output circuit of LCD control system is explained below. In the first place, the discharging switches SWB 0 , SWB 1 , . . . , SWB 8  are set in ON state. As a result, the output Y of the operational amplifier 41 is negatively fed back to the inverting input terminal A of the operational amplifier 41 through the discharging switch SWB 8 . By such negative feedback, the potential difference between the inverting input terminal A and the noninverting input terminal B becomes an offset voltage V off  as shown in Formula (4). ##EQU1## 
     Besides, the potential difference between positive and negative electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  becomes equal also to the offset voltage V off . At this time, the electric charge Q DCn  stored in each of the capacitors CP 0 , CP 1 , . . . , CP 7  is 
     
         Q.sub.DCn =2.sup.n ×C×V.sub.off [n=0 to 7]     (5) 
    
     Consequently, the eight-bit digital input signal is fed to the digital input switches SW 0 , SW 1 , . . . , SW 7 , and corresponding to the individual bits of the digital input signal, the digital input switches SW 0 , SW 1 , . . . , SW 7  are set in ON state or OFF state. The most significant bit (MSB) of the digital input signal corresponds to the digital input switch SW 7 , and the least significant bit (LSB) of the digital input signal corresponds to the digital input switch SW 0 . 
     Then, after setting all of dischargeing switches SWB 0 , SWB 1 , . . . , SWB 8  in OFF state, all of charging swiches SWA 0 , SWA 1 , . . . , SWA 9  are set in ON state. At this time, of the digital input switches SW 0 , SW 1 , . . . , SW 7 , the electric charge Q CCn  stored in the capacitors connected to the switches set in ON state is 
     
         Q.sub.CCn =2.sup.n ×C×((+V.sub.ref)-(-V.sub.ref)+V.sub.off)[n=0 to 7]                                                     (6) 
    
     Besides, since the charging switch SWA 9  is set in ON state, the offset voltage V off  is applied to the negative feedback capacitor CP 8  as shown in Formula (7). 
     
         V.sub.CP8 =V.sub.off                                       (7) 
    
     Therefore, the electric charge Q CP8  stored in the negative feedback capacitor CP 8  is as shown in Formula (8). 
     
         Q.sub.CP8 =256×C×V.sub.off                     (8) 
    
     Sequentially, after setting all of charging switches SWA 0 , SWA 1 , . . . , SWA 9  in OFF state, the discharging switches SWB 0 , SWB 1 , . . . , SWB 8  are all set in ON state. At this time, since the output Y of the operational amplifier 41 is negatively fed back to the inverting input terminal A through the discharging switch SWB 8 , the potential difference between the inverting input terminal A and the noninverting input terminal B becomes equal to the offset voltage V off  again. 
     Besides, the potential difference between the positive and negative electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  becomes also equal to the offset voltage V off . At this time, the electric charges moving from the negative electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  are collected in the negative electrode of the negative feedback capacitor CP 8 . The electric charge quantity ΔQ CP8  moving to the negative electrode of the negative feedback capacitor CP 8  is expressed as follows, supposing the numerical value of bit information 0 or 1 of digital input signal to be bitn. 
     
         ΔQ.sub.CP8 =(1×bit0+2×bit1+4×bit2+8bit3+16×bit4 +32×bit5+64×bit6+128×bit7)×C×((+V.sub.ref)-(-V.sub.ref))                                               (9) 
    
     For example, when a digital input signal of &#34;10110010&#34; in binary notation is supplied, bit0, bit2, bit3 and bit6 are 0 (OFF state), while bit1, bit4, bit5 and bit7 are 1 (ON state), and the electric charge quantity ΔQ CP8  moving to the negative electrode of the negative feedback capacitor CP 8  is determined from Formula (10). ##EQU2## 
     At this time, the electric charges opposite in the polarity to the moved electric charges and same in the quantity are collected at the positive electrode of the negative feedback capacitor CP 8 . The potential of the negative electrode of the negative feedback capacitor CP 8  is at the same potential as the inverting input terminal A of the operational amplifier 41, and from Formula (4), we obtain 
     
         (Potential at negative electrode of capacitor CP.sub.8) =(-V.sub.ref)-V.sub.off                                   (11) 
    
     Hence, if the electric charges are not moved by the capacitors CP 0 , CP 1 , . . . , CP 7 , the output V out  of the output circuit is obtained as follows from Formulas (7) and (11) 
     
         V.sub.out =(-V.sub.ref)-V.sub.off +V.sub.off =-V.sub.ref   (12) 
    
     and when the electric charges are moved as in Formula (9), the output V out  is 
     
         V.sub.out =(1/256)×(1.bit0+2.bit1+4.bit2+8.bit3+16.bit4+32.bit5 +64.bit6+128.bit7)×((+V.sub.ref)-(-V.sub.ref))+(-V.sub.ref)(13) 
    
     When the binary digital signal &#34;10110010&#34; shown in the example above is entered, the output is 
     
         V.sub.out =(178/256)×((+V.sub.ref)-(-V.sub.ref))+(-V.sub.ref)(14) 
    
     Thus, in the embodiment in FIG. 3, corresponding to each bit of eight-bit digital signal, capacitors CP 0 , CP 1 , . . . , CP 7  having reference capacitances of 2 0  to 2 7  times, respectively, and switches for turning on or off the charging to the capacitors depending on the bit information of the input digital signal are provided, so that the electric charge corresponding to the numerical value expressed by the input digital signal are charged in the capacitors, and the output voltage proportional to the stored electric charge is obtained by the amplifier, thereby a required output voltage is obtained. That is, a necessary voltage may be generated without setting many reference voltages. Therefore, according to the LCD control system in which the output circuit shown in FIG. 3 is incorporated, the number of wirings may be reduced significantly. 
     As described herein, the LCD control system having the output circuit in the embodiment in FIG. 3 comprises n capacitors connected in parallel possessing different capacitances ranging from 2 to the power of 0 to 2 to the power of (n-1) of (2 0  to 2 n-1  times as large as) the reference capacitance (n: a positive integral number), and each capacitor is provided with n switches for turning on or off the charge or discharge of electric charge, and therefore by turning on or off the n switches depending on the bit information of digital signal, the electric charge corresponding to the digital input signal is stored in the capacitors. When the voltage generated by the stored electric charge is supplied in the amplifier, the output voltage corresponding to the digital input signal is obtained. Thus, in the LCD control system having the output circuit in the embodiment in FIG. 3, a necessary voltage may be generated without having to set many reference voltages. Therefore, the number of wirings and number of circuits may be saved in the LCD control system. 
     Referring then to FIG. 4, a third embodiment of the output circuit comprising a DA converter for composing the LCD control system of the invention is described below. 
     In the output circuit in FIG. 4, two reference input voltages are supplied from a power supply +V ref16  and a power supply +V ref , and the potential difference between the power supply -V ref  and the power supply +V ref16  is 1/16 of the potential difference between the power supply -V ref  and the power supply +V ref . The output circuit of the embodiment comprises eight capacitors CP 0 , CP 1 , . . . , CP 7  connected in parallel, and a negative feedback capacitor CP 8 . The capacitors CP 0 , CP 1 , . . . , CP 7  consist of a set of four capacitors CP 0  to CP 3 , and a set of another four capacitors CP 4  to CP 7 . The capacitance of capacitors CP 0  and CP 4  is the reference capacitance C, the capacitance of capacitors CP 0  and CP 5  is 2×C, the capacitance of capacitors CP 2  and CP 6  is 4×C, the capacitance of capacitors CP 3  and CP 7  is 8×C, and the capacitance of the negative feedback capacitor CP 8  is 16×C. In the embodiment, meanwhile, the positive side electrodes of the capacitors CP 0  to CP 3  are connected to the reference input voltage (power supply) +V ref16  through charging switches SWA 0  to SWA 3  and digital input switches SW 0  to SW 3 , and the positive side electrodes of the capacitors CP 4  to CP 7  are connected to the reference input voltage (power supply) +V ref  through charging switches SWA 4  to SWA 7  and digital input switches SW 4  to SW 7 . The composition of other parts is same as in the output circuit in the second embodiment shown in FIG. 3, and the corresponding parts are identified with the same reference numbers. 
     The operation of thus composed output circuit of the LCD control system is explained below. At the beginning, the discharging switches SWB 0 , SWB 1 , . . . , SWB 8  are set in ON state. Hence, the output Y of the operational amplifier 41 is negatively fed back to the inverting input terminal A of the operational amplifier 41 through the discharging switch SWB 8  and the negative feedback capacitor CP 8 . By such negative feedback, the potential difference between the inverting input terminal A and noninverting input terminal B becomes the offset voltage V off  as shown in Formula (15). ##EQU3## 
     The potential difference between positive and negative electrodes of capacitors CP 0 , CP 1 , . . . , CP 7  is also equal to the offset voltage. At this time, the electric charge quantity Q DCn  charged in the capacitors CP 0 , CP 1 , . . . , CP 7  is 
     
         Q.sub.DCn =2.sup.n ×C×V.sub.off [n=0 to 3] 
    
     
         Q.sub.DCn =2.sup.n-4 ×C×V.sub.off [n=4 to 7]   (16) 
    
     Consequently, an eight-bit digital input signal is fed in the digital input switches SW 0 , SW 1 , . . . , SW 7 , and corresponding to each bit of the digital signal, the digital input switches SW 0 , SW 1 , . . . , SW 7  are set in ON state or OFF state. The most significant bit (MSB) of the digital input signal corresponds to the digital input switch SW 7 , and the least significant bit (LSB) of the digital input signal corresponds to the digital input switch SW 0 . 
     After setting all of discharging switches SWB 0 , SWB 1 , . . . , SWB 8  in OFF state, all of charging switches SWA 0 , SWA 1 , . . . , SWA 9  are set in ON state. At this time, the electric charge Q ccn  charged in the capacitors connected to the switches set in ON state out of the digital input switches SW 0 , SW 1 , . . . , SW 7  is as follows. 
     
         Q.sub.ccn =2.sup.n ×C×(((+V.sub.ref)-(-V.sub.ref))/16+V.sub.off) [n=0 to 3 ] 
    
     
         Q.sub.ccn =2.sup.n-4 ×C×((+V.sub.ref)-(-V.sub.ref)+V.sub.off) [n=4 to 7]                                                (17) 
    
     Besides, since the charging switch SWA 9  is set in ON state, an offset voltage V off  is applied to the capacitor CP 8  as shown in Formula (18). 
     
         V.sub.CP8 =V.sub.off                                       (18) 
    
     Therefore, the electric charge Q CP8  stored in the negative feedback capacitor CP 8  is as shown in Formula (19). 
     
         Q.sub.CP8 =16×C×V.sub.off                      (19) 
    
     Next, after setting all of charging switches SWA 0 , SWA 1 , . . . , SWA 9  in OFF state, all of discharging switches SWB 0 , SWB 1 , . . . , SWB 8  are set in ON state. At this time, since the output Y of the operational amplifier 41 is negatively fed back to the inverting input terminal A through the discharging switch SWB 8  and the negative feedback capacitor CP 8 , the potential difference between the inverting input terminal A and the noninverting input terminal B becomes equal to the offset voltage V off  again. At the same time, the potential difference between the positive and negative electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  becomes also equal to the offset voltage V off . At this time, the electric charges moving from the negative electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  are collected at the negative electrode of the negative feedback capacitor CP 8 . The electric charge quantity ΔQ CP8  moving to the negative electrode of the negative feedback capacitor CP 8  is as follows, expressing the numerical value of the bit information 0 or 1 of digital input signal as bitn. ##EQU4## 
     For example, when a digital input signal of &#34;10110010&#34; in binary notation is supplied, bit0, bit2, bit3 and bit6 are 0 (OFF state), and bit1, bit4, bit5 and bit7 are 1 (ON state), and the electric charge quantity ΔQ CP8  moving to the negative electrode of the negative feedback capacitor CP 8  at this time is obtained from Formula (21). ##EQU5## 
     At this time, the electric charges of the same quantity of the charges being moved and opposite in polarity are collected at the positive electrode of the negative feedback capacitor CP 8 . The potential of the negative electrode of the negative feedback capacitor CP 8  is same as the potential at the inverting input terminal A of the operational amplifier 41, and from Formula (15) it is known as follows. 
     
         (Potential at negative electrode of capacitor CP.sub.8) =(-V.sub.ref)-V.sub.off                                   (22) 
    
     Hence, if the electric charges are not moved by the capacitors CP 0 , CP 1 , . . . , CP 7 , the output V out  of the output circuit is calculated from Formulas (18) and (22) as follows 
     
         V.sub.out =(-V.sub.ref)-V.sub.off +V.sub.off =-V.sub.ref   (23) 
    
     and when the electric charges are moved as shown in Formula (20), it follows that ##EQU6## 
     When the binary digital signal &#34;10110010&#34; in the example above is entered, the output is 
     
         V.sub.out =(178/256)×((+V.sub.ref)-(-V.sub.ref))+(-V.sub.ref)(25) 
    
     Thus, according to the embodiment in FIG. 4, capacitors consist of two sets of capacitors comprising four capacitors, of which capacitance ranges from 2 0  to 2 3  of the specified reference capacitance, and the two sets are supplied with voltages of 2 0  and 2 -4  (1/16) of the reference voltage +V ref , and therefore by turning on or off the eight switches provided in the capacitors CP 0 , CP 1 , . . . , CP 7  corresponding to the bit information of eight-bit digital signal, the electric charge corresponding to the numerical value expressed by the input digital signal is stored in the capacitors. The voltage proportional to the stored electric charge is generated by the operational amplifier 41, and an output voltage corresponding to the input digital signal is obtained. Besides, by the constitution of the embodiment, the total capacitance value of the capacitors for composing the output circuit may be reduced to about 1/11 of that of the output circuit in the second embodiment. 
     As explained herein, the LCD control system posessing the output circuit in FIG. 4 comprises n capacitors consisting of m sets possessing different capacitance ranging from 2 to the power of 0 to 2 to the power of (n-1) of (2 0  to 2 n-1  times as large as) the specified reference capacitance value (n: a positive integral number), and power supply group for supplying voltages ranging from 2 to the power of (-n)×0 to 2 to the power of (-n)×(m-1) of [2.sup.(-n)×0 to 2.sup.(-n)(m-1) times as large as] the specified reference voltage to m sets (n, m: positive integral numbers), and therefore by turning on or off the n×m switches disposed in the capacitors on the basis of the bit information of the digital signal, the electric charge corresponding to the digital input signal is stored in the capacitors. The voltage proportional to the stored electric charge is generated by the amplifier, and an output voltage corresponding to the digital input signal is obtained without having to set many reference voltages. Therefore, according to the embodiment, the number of wirings and number of circuits may be reduced in the LCD control system. 
     A fourth embodiment of an output circuit comprising a DA converter for composing the LCD control system of the invention is described below by reference to FIG. 5. 
     The output circuit in FIG. 5 possesses eight capacitors CP 0 , CP 1 , . . . , CP 7  connected in parallel, a negative feedback capacitor CP 8 , and a dividing capacitor CP 9 . The capacitors CP 0 , CP 1 , . . . , CP 7  consist of one set composed of four capacitors CP 0  to CP 3 , and the other set composed of four capacitors CP 4  to CP 7 . These capacitors CP 0 , CP 1 , . . . , CP 7  correspond to each bit of the eight-bit digital signal, and in the embodiment in FIG. 5, the capacitors CP 0  to CP 3  correspond to the lower four bits, and the capacitors CP 4  to CP 7 , to the upper four bits. 
     The dividing capacitor CP 9  is connected in series to one set of capacitors CP 0  to CP 3 , and divides the voltage generated by the capacitors CP 0  to CP 3  corresponding to the lower four bits. The dividing capacitor CP 9  is connected parallel to the other set of capacitors CP 4  to CP 7 . 
     The capacitance of capacitors CP 0  and CP 4  is the reference capacitance C, the capacitance of capacitors CP 1  and CP 5  is 2×C, the capaciance of capacitors CP 2  and CP 6  is 4×C, the capacitance of capacitors CP 3  and CP 7  is 8×C, the capacitance of the negative feedback capacitor CP 8  is 16×C, and the capacitance of the dividing capacitor CP 9  is the reference capacitance C. 
     The negative side electrodes of the capacitors CP 0  to CP 3  corresponding to the lower four bits are connected to the positive side electrode of the dividing capacitor CP 9 , and the negative side electrode of the dividing capacitor CP 9  and the capacitors CP 4  to CP 7  corresponding to the upper four bits are connected to the inverting input terminal A of the operational amplifier 41. 
     The positive side electrodes of the capacitors CP 0 , CP 1 , . . . , CP 7  are connected to the power supply -V ref  for supplying reference input voltage through discharging switches SWB 0 , SWB 1 , . . . , SWB 7  turned on or off depending on the bit data of the digital signal, and are likewise connected to the power supply +V ref  for supplying reference input voltage through charging switches SWA 0 , SWA 1 , . . . , SWA 7  turned on or off depending on the bit data of the digital signal. 
     A sampling circuit is composed of the capacitors CP 0 , CP 1 , . . . , CP 7 , charging switches SWA 0 , SWA 1 , . . . , SWA 7 , and discharging switches SWB 0 , SWB 1 , . . . , SWB 7 , while a DA converter is composed of the operational amplifier 41 and negative feedback capacitor CP 8 . 
     The charging switches SWA 0 , SWA 1 , . . . , SWA 7  are set in ON state when sampling the input voltage. Switches are composed of the charging switches SWA 0 , SWA 1 , . . . , SWA 7  and discharging switches SWB 0 , SWB 1 , . . . , SWB 7 . 
     The other constitution is same as in the output circuit shown in FIG. 4, and the corresponding parts are identified with the same reference numbers. For the sake of simplicity of explanation, as shown in FIG. 5, the potential at the negative side electrodes of the capacitors CP 0  to CP 3  is supposed to be V 1 , and the potential at the negative side electrodes of the dividing capacitor CP 9  and the capacitors CP 4  to CP 7 , to be V 2 . 
     The operation of thus composed output circuit of the LCD control system is described below. 
     The operational amplifier 41 functions so that the inverting and noninverting input terminals A, B may be always at identical potential, and therefore in the stationary state the inverting and noninverting input terminals A, B are at the reference input voltage -V ref . Therefore, the reference input voltage -V ref  is applied also to the negative electrodes of the capacitors CP 4  to CP 7  corresponding to the upper four bits. 
     On the other hand, the reference input voltage -V ref  appearing at the inverting input terminal A of the operational amplifier 41 is divided by the parallel capacitance of the capacitors CP 0  to CP 3  corresponding to the lower four bits, and the dividing capacitor CP 9 , and the potential V 1  is applied to the negative electrodes of the capacitors CP 0  to CP 3  corresponding to the lower four bits. 
     In this state, depending on the specified input digital signal, for example, the charging switches SWA 0 , SWA 1 , . . . , SWA 7  are set in ON state, and at the same time the charging switches SWA 8 , SWA 9  are set in ON state, and all of discharging switches SWB 0 , SWB 1 , . . . , SWB 8  are set in OFF state. At this time, a potential of -V ref  is applied to both ends of the negative feedback capacitor CP 8 . 
     On the other hand, the reference input voltage +V ref  is applied to the positive electrodes of the capacitors CP 4  to CP 7  corresponding to the upper four bits through the charging switches SWA 4 , . . . , SWA 7 . As a result, the capacitors CP 4  to CP 7  are charged. This is the state of sampling depending on the input digital signal. 
     Next, when the charging switches SWA 0 , SWA 1 , . . . , SWA 9  are set in OFF state, and the discharging switch SWB 4 , . . . , SWB 8  are set in ON state, the electric charges stored in the capacitors CP 4  to CP 7  are moved to the negative feedback capacitor CP 8 . The voltage generated as a result of this movement of electric charges is delivered as the output V out  through the discharging switch SWB 8 . In consequence, the voltage of the output V out  being so far the reference input voltage -V ref  changes to the voltage corresponding to the electric charges stored in the negative feedback capacitor CP 8 . This voltage depends on the input digital signal, and thereby digital-to-analog conversion has been substantially effected. 
     Shown above is a case of simultaneous charging of the capacitors CP 4  to CP 7  corresponding to the upper four bits, but it is the same when other digital signal is fed. For example, when a digital signal to charge any one of the capacitors CP 0  to CP 3  corresponding to the lower four bits is fed, instead of the reference input voltage -V ref , charging is effected on the basis of the divided potential V 1 , and the fundamental sampling and amplifying actions are quite the same. 
     Thus, in the output circuit comprising a digital-to-analog converter in FIG. 5, the resolution of 1/16 is realized by the capacitors CP 4  to CP 7  corresponding to the upper four bits, and the resolution of 1/256 is realized by the capacitors CP 0  to CP 3  corresponding to the lower four bits. 
     The digital-to-analog conversion action of the digital-to-analog converter in FIG. 5 is explained practically below by using numerical expressions. 
     In the first place, the electric charge at the negative side electrodes of the capacitors CP 0 , CP 1 , CP 2 , CP 3  corresponding to the lower four bits and the dividing capacitor CP 9  is numerically expressed, by supposing that a charge K (coulomb) is present, as being not neutralized. Here, assuming the potential of the positive side electrode of the capacitor CP n  to be V CPn , it follows that ##EQU7## 
     After first setting the discharge switches SWB 0 , SWB 1 , . . . , SWB 8  in OFF state, the charging switches SWA 0 , SWA 1 , . . . , SWA 9  are set in ON state. As a result, V CP0  to V CP7  become +V ref . At this time, the charging switch SWA 8  is in ON state, and the output Y (output V out ) of the operational amplifier 41 is negatively fed back to the inverting input terminal A of the operational amplifier 41 throught the charging switch SWA 8 , and therefore the potential V 2  becomes as follows, with respect to the offset voltage V off  generated between the noninverting input terminal B and inverting input terminal A of the operational amplifier 41. 
     
         V.sub.2 =(-V.sub.ref)-V.sub.off                            (27) 
    
     On the other hand, the divided potential V 1  at the negative side electrode of the capacitors CP 0  to CP 3  becomes as follows from Formulas (26) and (27): ##EQU8## 
     At this time, since the changing switch SWA 9  is set in ON state, the positive side electrode of the negative feedback capacitor CP 8  is connected to the reference input potential (power supply) -V ref , and an offset voltage V off  is applied to the negative feedback capacitor CP 8  as shown in Formula (29). Therefore, the voltage V CP8  at both ends of the negative feedback capacitor CP 8  is 
     
         V.sub.CP8 =V.sub.off                                       (29) 
    
     Then, after setting the charging switches SWA 8  and SWA 9  in OFF state, the discharging switch SWB 8  is set in ON state, and the ON or OFF state is set for the charging switches SWA 0 , SWA 1 , . . . , SWA 7  and discharging switches SWB 0 , SWB 1 , . . . , SWB 7  corresponding to the bits on the basis of the bit information of the input eight-bit digital signal. The most significant bit (MSB) of the digital input corresponds to the charging switch SWA 7  and discharging switch SWB 7 , and the least significant bit (LSB) corresponds to the charging switch SWA 0  and discharging switch SWB 0 . 
     For example, when bit n is 1, the charging switch SWA n  is set in OFF state, and the discharging switch SWB n  is set in ON state. When bit n is 0, the charging switch SWA n  is set in ON state and the discharging switch SWB n  is set in OFF state. At this time, the potential V 1  is obtained as follows, supposing each bit of the eight-bit digital input signal to be bit0 (LSB) to bit7 (MSB), and its inverted data to be Nbit0 (LSB) to Nbit7 (MSB): ##EQU9## 
     Since the operational amplifier 41 is negatively fed back, a potential difference corresponding to the offset voltage shown in Formula (31) is generated between the inverting input terminal A and noninverting input terminal B. ##EQU10## 
     Therefore, the potential V 2  is, same as in Formula (27): 
     
         V.sub.2 =(-V.sub.ref)-V.sub.off                            (32) 
    
     Accordingly, when the voltage applied to the voltages V CP0  to V CP7  applied to the positive side electrode of the capacitors CP 0 , CP 1 , . . . , CP 7  is changed from +V ref , to -V ref , the electric charge at the negative side electrodes of the dividing capacitor CP 9  and the capacitors CP 4 , CP 5 , CP 6 , CP 7  corresponding to the upper four bits are moved to the negative side electrode of the negative feedback capacitor CP 8 . The electric charge quantity ΔQ CPn  moving from these capacitors CP 4  to CP 7  is 
     
         ΔQ.sub.CPn =2.sup.n-4 ×C×((+V.sub.ref)-(-V.sub.ref)×bitn(n=4 to 7)(33) 
    
     Formula (33) is to express the upper four bits. 
     The electric charge quantity ΔQ CP9  moving from the dividing capacitor CP 9  is ##EQU11## 
     Formula (34) is to express the lower four bits. 
     Supposing all bits of the digital input signal to be 0, the electric charge quantity ΔQ CP8  moving to the negative feedback capacitor CP 8  is known as follows from Formulas (33) and (34): 
     
         ΔQ.sub.CP8 =0                                        (35) 
    
     Therefore, from Formulae (29) and (32), the output V out  from the operational amplifier 41 is 
     
         V.sub.out =-V.sub.ref                                      (36) 
    
     For example, when a digital input signal of &#34;10110010&#34; in binary notation is supplied, bit0, Nbit1, bit2, bit3, Nbit4, Nbit5, bit6 and Nbit7 are 0, and Nbit0, bit1, Nbit2, Nbit3, bit4, bit5, Nbit6 and bit7 are 1, and the output V out  from the operational amplifier 41 is, from Formulas (33) and (34), as follows: ##EQU12## 
     In this way, the voltage corresponding to the input digital signal is obtained in the output V out , and digital-to-analog conversion is effected. 
     Thus, according to the embodiment in FIG. 5, comprising one dividing capacitor CP 9  connected in series to a set of capacitors CP 0  to CP 3  corresponding to the lower four bits of the digital signal, and connected in parallel to a set of capacitors CP 4  to CP 7  corresponding to the upper four bits, the electric charge stored in the set of capacitors CP 0  to CP 3  corresponding to the lower four bits is distributed in the dividing capacitor CP 9 , and the voltage proportional to the stored electric charge in the dividing capacitor CP 9  and the set of capacitors CP 4  to CP 7  corresponding to the upper four bits is generated by the operational amplifier 41. Meanwhile, the number of switches and the capacitance in the embodiment are reduced same as in the output in the third embodiment shown in FIG. 4, while the reference power supply does not require the power supply of +V ref16  as used in the fourth embodiment, and it is possible to operate with two reference voltages. 
     As described herein, the LCD control system having the output circuit of the embodiment in FIG. 5 comprises (m-1) dividing capacitors connected in series to the capacitors in each set excluding the set corresponding to the most significant n bits of digital signal, and connected in series of the capacitors of the set corresponding to the next significant n bits, and therefore the electric charge stored in the capacitors in the set excluding the set corresponding to the most significant n bits is distributed in the electric charge of the dividing capacitor. The voltage proportional to the stored electric charges in the dividing capacitors and the capacitors of the set corresponding to the most significant n bits is generated by the operational amplifier, and an output voltage corresponding to the digital input signal may be obtained without having to set many reference voltages as in the prior art. Therefore, according to the embodiment, the number of wirings and the number of circuits in the LCD control system may be reduced. 
     A fifth embodiment of an output circuit comprising a DA converter for composing the LCD control system of the invention is described below while referring to FIG. 6. 
     In order to inspect the capacitors of the capacitive type DA converters shown in FIG. 2 through FIG. 5, the inspection precision of 2 to the nth power (n: a positive integral number) is needed depending on the increase of the number of bits. Accordingly, if the number of bits is particularly large in digital signal, an inspection apparatus of an extremely high inspection precision is required. 
     The output circuit in FIG. 6 is intended to solve such problem, and is to present an LCD control system capable of inspecting capacitors corresponding to all bits of input digital signal by using an inspection apparatus of a relatively low inspection precision. 
     In FIG. 6, a test switch SWT is connected between both ends of a dividing capacitor CP 9 . The other constitution is same as in the output circuit in the fourth embodiment shown in FIG. 5, and the corresponding parts are identified with the same reference numbers. 
     In thus composed LCD control system, its operation is described below. 
     At the time of digital-to-analog conversion, the test switch SWT is set in OFF state, and the operation of digital-to-analog conversion is same as in the output circuit in the fourth embodiment shown in FIG. 5, and its explanation is omitted. 
     The inspection of the LCD control system is explained. 
     Inspection is effected, with the tester (not shown) connected to the output V out , by measuring the output V out  by turning on or off the charging switches SWA 0 , SWA 1 , . . . , SWA 7 , and discharging switches SWB 0 , SWB 1 , . . . , SWB 8 . 
     The LCD control system in FIG. 6 is intended to convert the eight-bit digital signal into an analog signal, and it is therefore necessary to measure the output voltage, at a precision of 1/256 of the reference input voltage, depending on the ON or OFF state of the charging switches SWA 0 , SWA 1 , . . . , SWA 7 , and discharging switches SWB 0 , SWB 1 , . . . , SWB 8 . That is, as for the capacitors CP 4  to CP 7  corresponding to the upper four bits, it is enough to measure the changes of the output voltage at a precision of 1/16 of the reference input voltage. For example, when the reference input voltage is 5 (V), the precision of 5/16 (V) , that about 300 mV is needed. As for the capacitors CP 0  to CP 3  corresponding to the lower four bits, a precision of its further 1/16 is needed. 
     Some of the analog testers have a precision of about 10 mV, and with such analog testers, the DA converters shown in FIGS. 2 to 5 may be sufficiently inspected. Generally, however, analog testers have only several terminals, and they are not suited to inspection of DA converters having more than 100 terminals. Yet, analog testers are very expensive. 
     On the other hand, digital testers generally have about 200 terminals, and are hence suited to inspection of DA converters. However, the precision of digital testers is about 50 mV, at best. 
     Therefore, the capacitors CP 4  to CP 7  of upper four bits requiring precision of only about 300 mV may be sufficiently measured by the digital testers with a precision of about 50 mV, but the capacitors CP 0  to CP 3  of lower four bits requiring a precision of its 1/16 cannot be measured by the digital testers having a precision of only 50 mV. 
     In the embodiment, accordingly, when testing the capacitors CP 0  to CP 3  of lower four bits, the test switch SWT is set in ON state, and the both ends of the dividing capacitor CP 9  are short-circuited. 
     In this way, the connective relationship of the capacitors CP 0  to CP 3  of the lower four bits to the operational amplifier 41 is same as the connective relationship of the capacitors CP 4  to CP 7  of the upper four bits to the operational amplifier 41. Therefore, the change of output V out  due to capacitors CP 0  to CP 3  of lower four bits is about 300 mV, same as the change of output V out  due to capacitors CP 4  to CP 7  of upper four bits. As a result, it is enough to measure with a digital tester having a precision of about 50 mV. 
     Thus, in the embodiment shown in FIG. 6, a samping circuit is composed of plural first capacitors corresponding to each lower bit of the input digital signal, plural second capacitors corresponding to each upper bit of input digital signal, plural switches turned on or off depending on the input digital signal and controlling charging and discharging of the capacitors of the first and second capacitors, and a dividing capacitor connected between the common node of the first capacitors and the common node of the second capacitors, and the voltage corresponding to the electric charge quantity appearing in the common node of the second capacitors is amplified by the amplifier and delivered as analog signal, and a switch is connected parallel to the dividing capactior. 
     In this constitution, as for the first capacitors corresponding to the lower bits, too, the connective relationship may be set same as in the second capacitors corresponding to the upper bits by turning on the switch connected parallel to the dividing capacitor and short-circuiting the both ends of the dividing capacitor. Accordingly, it is possible to inspect at the same precision as in the second capacitors corresponding to the upper bits. Therefore, the capacitors corresponding to all bits can be inspected by using an inspection apparatus of a relatively low inspection precision. 
     Shown below are sixth and seventh embodiments of the output circuit comprising a DA converter for composing the LCD control system of the invention. 
     In the constitution of the capacitive type DA converter above, the operating point of the operational amplifier is either at the potential (+V ref ) or at the potential (-V ref ), and is biased to the periphery of the dynamic range of the operational amplifier. It is hence susceptible to fluctuations of supply voltage, and the supply voltage characteristics are poor. 
     The six and seventh embodiments of the invention are intended to present the LCD control system capable of solving such problems. 
     In the sixth embodiment, the mutually different first and second potentials are selectively applied to one end of the capacitor according to the input digital data, and the other end of the capacitor is connected to the inverting input terminal of the operational amplifier. At the same time, a potential nearly in the middle of the first and second potentials is applied to the noninverting input terminal of the operational amplifier, and the same potential as the first or second potential selectively applied to the other end of the feedback capacitor of which one end is connected to the inverting input terminal of the operational amplifier. 
     In the LCD control system of the seventh embodiment, the mutually different first and second potentials, and a third potential nearly in the middle of the first and second potentials are selectively applied to one end of the capacitor according to the input digital data, and the other end of the capacitor is connected to the inverting input terminal of the operational amplifier, and a same potential as the third potential is applied to the noninverting input terminal of the operational amplifier, and a feedback capacitor is connected between the inverting input terminal and output terminal of the operational amplifier. 
     In this consitution, the operating point of the operational amplifier may be set at a middle voltage of the first and second potentials, and the operational amplifier may be operated nearly in the middle of its dynamic range. As a result, the LCD control system resistant to fluctuations of supply voltage and excellent in supply voltage characteristics may be obtained. 
     Referring now to FIG. 7 and FIG. 8 the sixth and seventh embodiments of the output circuit comprising a DA converter for composing the LCD control system of the invention are described in detail below. 
     FIG. 7 is a structural diagram showing the output circuit in the sixth embodiment of the LCD control system of the invention. In FIG. 7, when each analog switche SWA or SUB is in ON state, each potential V ina  or V inb  is applied to one end of the capacitor CA. It is supposed here that the potential V ina  is lower than the potential V inb . 
     The other end of the capacitor CA is connected to the inverting input terminal A of the operational amplifier 41 through a node at which a potential VB appears. The noninverting input terminal B of the operational amplifier 41 is connected to a potential VC. 
     One end of the feedback capacitor CB is connected to analog SUE the inverting input terminal A of the operational amplifier 41. An analog switch SWF is connected between a inverting input terminal A and an output terminal V out  of the operational amplifier 41. An analog switch SWE is connected between the other end of the feedback capacitor CB and output terminal V out . When an analog switch SWD is set in ON state, the potential VD is applied to the feedback capacitor CB. 
     Concerning the capacitive type DA converter incorporated in thus composed LCD control system of the embodiment in FIG. 7, its operation is described below. Provided that, as shown in Formula (38), the potential VD is supposed to be same as the potential V inb , and the potential VC is in the middle between the potential V ina , and potential V inb . ##EQU13## 
     The operation of the capacitive type DA converter consists of the charge cycle of the electric charges into the capacitor CA, and the discharge cycle of the movement of the electric charges from the capacitor CA to the feedback capacitor CB and consequent output of the analog voltage from output terminal V out . 
     First, in the charge cycle, the analog switch SWA, analog switch SWF, and analog switch SWD are in ON state, while the analog switch SWB and analog switch SWE are in OFF state. Accordingly, the potential VA is equal to the potential V ina . By the action of the operational amplifier 41, the potential VB and the potential of the output terminal V out  are equal to the potential VC. At this time, the potentials at each end of the capacitor CA are the potential VA and potential VB respectively, and the following relation is established. 
     
         (Potential difference of capacitor CA) =(potential V.sub.ina -potential VB)(39) 
    
     Likewise, as for the feedback capacitor CB, since the potentials at each end are the potential VB and potential VD respectively, their relation is as shown in Formula (40). ##EQU14## 
     Next, in the discharge cycle, the analog switch SWF and analog switch SWD are set in OFF state, while the analog switch SWE is set on ON state. When the input digital data is 1, the analog switch SWB is set in ON state, and the analog switch SWA is set in OFF state. Accordingly, the potential VA is equal to the potential V inb , and the potential difference at both ends of the capacitor CA is as shown in Formula (41). 
     
         (Potential difference of capacitor CA) =(potential V.sub.inb -potential VB)(41) 
    
     Accordignly, the electric charges having been charged at the negative side electrode of the capacitor. CA are moved to the feedback capacitor CB, and the electric charges are moved to the output terminal V out  side (positive side electrode) of the feedback capacitor CB in a manner to cancel this electric charge movement. The moving electric charge quantity ΔQ CB  is expressed in Formula (42). 
     
         ΔQ.sub.CB =[potential V.sub.inb -potential V.sub.ina ]×(capacitance of capacitor CA)                     (42) 
    
     The potential VB is not changed because a negative feedback is applied to the operational amplifier 41. Therefore, the potential of the output terminal V out  produced as a result of movement of the electric charges becomes as shown in Formula (43). ##EQU15## 
     On the other hand, when the input digital data is 0, the analog switch SWB is set in OFF state, and the analog switch SWA is set in ON state. Accordingly, the electric charges are not moved in the capacitor CA, and the potential of the output terminal V out  is in the relation of 
     
         Potential of output terminal V.sub.out =potential V.sub.inb.(44) 
    
     The potential difference V 1-0  of the output terminal V out  when the input digital data is 1 and when 0 is ##EQU16## 
     In the embodiment in FIG. 7, incidentally, the potential VD is set equal to the potential V inb , but it may be, otherwise, set equal to the potential V ina . 
     Thus, in the embodiment in FIG. 7, the analog switch SWE is connected between the output terminal V out  of the operational amplifier 41 and the other end of the feedback capacitor CB, and the analog switch SWD is connected between the output terminal V out  of the operational amplifier 41 and one end of the feedback capacitor CB so as to apply the same potential as the potential V ina  or potential V inb , and the potential VC having the middle potential between the potential V ina  and potential V inb  is applied to the noninverting input terminal B of the operational amplifier 41. Therefore the operating point of the operational amplifier 41 may be set at the middle potential of the potential V ina  and potential V inb , that is, near the middle of the dynamic range of the operational amplifier 41. It is hence possible to realize the LCD control system resistant to fluctuations of supply voltage and excellent in supply voltage characteristics. 
     In FIG. 7, meanwhile, the analog switch SWA, analog switch SWB and capacitor CA are disposed by one set each, and the input digital data of one bit is converted into analog signal, but it is also possible to dispose plural sets of analog switch SWA, analog switch SWB and capacitor CA individually to convert into digital data of multiple bits into analog signal. In this case, each capacitance of the plural capacitors CA may FIG. 8 is a structural diagram showing the output circuit in the seventh embodiment of the LCD control system of the invention. When the analog switch SWC is set in ON state, the potential V inc  is applied to the capacitor CA. The feedback capacitor CB is connected between the inverting input terminal A and output terminal V out  of the operational amplifier 41. The other constitution is same as in the output circuit in the sixth embodiment shown in FIG. 7. 
     In thus composed capacitive type DA converter incorporated in the LCD control system of the embodiment, the operation is described below. It is supposed, as shown in Formula (46), that the potential VC and potential V inc  are a middle potential of the potential V ina  and potential V inb . 
     
         Potential VC=potential V.sub.inc =[potential V.sub.inb +potential V.sub.ina ]/2                                                       (46) 
    
     The operation of the capacitive type DA converter consists of the charge cycle of electric charges into the capacitor CA, and the discharge cycle of movement of the electric charges from the capacitor CA to the feedback capacitor CB and subsequent output from the output terminal V out . 
     In the charge cycle, the analog switch SWC and analog switch SWF are set in ON state, while the analog switch SWA and analog switch SWB are set in OFF state. Accordingly, the potential VA is equal to the potential V inc . By the action of the operational amplifier 41, the potential VB and the potential at the output terminal V out  are equal to the potential VC. As a result, the potential difference at both ends of the capacitor CA is as shown in Formula (47). 
     
         (Potential difference of capacitor CA) =potential V.sub.inc -potential VB(47) 
    
     Next, in the discharge cycle, the analog switch SWC and analog switch SWF are set in OFF state. 
     In this state, when the input digital data is 1, the analog switch SWA remains OFF, while the analog switch SWB is turned on. To the contrary, when the input digital data is 0, the analog switch SWB remains OFF, and the analog switch SWA is turned on. Accordingly, the potential VA is equal to the potential V inb  when the input digital data is 1, and equal to the potential V ina  when the input digital data is 0. 
     Therefore, the potential difference at both ends of the capacitor CA, when the input digital data is 1, is as follows. 
     
         (Potential difference of capacitor CA) =potential V.sub.inb -potential VB(48) 
    
     When the input digital data is 0, the relation is 
     
         (Potential difference of capacitor CA) =potential V.sub.ina -potential VB(49) 
    
     Accordingly, the electric charges having been charged at the negative side electrode of the-capacitor CA are moved to the negative side electrode of the feedback capacitor CB, and the electric charges are moved to the output terminal V out  side of the feedback capacitor CB in such a manner as to cancel this movement of electric charges. The electric charge quantity ΔQ CB  being moved is, when the input digital data is 1, as follows. 
     
         ΔQ.sub.CB =[potential V.sub.inb -potential V.sub.inc ]×(capacitance of capacitor CA)                     (50) 
    
     When the input digital data is 0, the relation is 
     
         ΔQ.sub.CB =[potential V.sub.ina -potential V.sub.inc ]=(capacitance of capacitor CA)                                          (51) 
    
     The potential VB is equal to the potential VC and is not changed because a negative feedback is applied to the operational amplifier 41. Therefore, the potential of the output terminal V out  is, when the input digital data is 1, determined as follows from Formula (50). ##EQU17## When the input digital data is 0, the relation is ##EQU18## 
     The voltage difference V 1-0  of the output terminal V out  when the input digital data is 1 and when 0 is ##EQU19## 
     Thus, according to the embodiment in FIG. 8, by installing the analog switch SWC for applying the potential V inc  nearly in the middle between the potential V ina  and potential V inb , and applying the potential VC equal to the voltage nearly in the middle between the potential V ina  and potential V inb  to the noninverting input terminal B of the operational amplifier 41, first the middle potential V inc  is sampled in the charge cycle, and then the output analog voltage may be varied, starting from the middle potential. Accordingly the LCD control system resistant to fluctuations of supply voltage and excellent in supply voltage characteristics may be realized. Besides, since the output analog voltage is also changed from the potential near the central position, a high voltage is hardly applied to the analog switch SWF, and in this respect, too, the LCD control system of stable operation is realized. 
     In the embodiment in FIG. 8, too, the analog switch SWA, analog switch SWB, and analog switch SWC and capacitor CA may be disposed in plural sets each, and the input digital data of multiple bits may be converted into analog signal. At this time, the plural capacitors CA may be individually weighted. 
     Thus, in the embodiment shown in FIG. 7, the mutually different first and second potentials are selectively applied to one end of the capacitor according to the input digital data, the other end of the capacitor is connected to the inverting input terminal of the operational amplifier, and a potential nearly in the middle of the first and second potentials is applied to the noninverting input terminal of the operational amplifier, and moreover a potential equal to the first or second potential is applied to the other end of the feedback capacitor of which one end is connected to the inverting input terminal of the operational amplifier. 
     Besides, in the embodiment shown in FIG. 8, the mutually different first and second potentials, and a third potential having a potential near the middle of the first and second potentials are selectively applied to one end of the capacitor according to the input digital data, and the other end of the capacitor is connected to the inverting input terminal of the operational amplifier, and a same potential as the third potential is applied to the noninverting input terminal of the operational amplifier, and a feedback capacitor is connected between the inverting input terminal and output terminal of the operational amplifier. 
     By so constituting, the operating point of the operational amplifier may be set at a middle potential of the first and second potentials, and the operational amplifier may be operated nearly in the middle of its dynamic range. Hence, the LCD control system resistant to fluctuations of supply voltage and excellent in supply voltage characteristics may be realized. 
     An eighth embodiment of the LCD control system of the invention is described below. 
     In the LCD control system which repeats the charge cycle and discharge cycle periodically, the duration of the charge cycle is longer because the load by a large capacitance is charged and discharged in the charge cycle. As a result, the discharge cycle time is relatively shorter, and the power consumption increases by charging and discharging the load capacitor. 
     The eighth embodiment of the invention is intended to solve the above problems, and presents an LCD control system capable of shortening the charge cycle time and saving the power consumption. 
     In other words, in the embodiment, a switch for connecting and disconnecting the load is connected between the output terminal of the operational amplifier of the output circuit comprising a DA converter and the load capacitor of the liquid crystal panel, and this switch is set in OFF state in the charge cycle. 
     In this constitution, in the charge cycle, the load capacitor of the operational amplifier is cut off, and the load of the operational amplifier may be reduced, so that the operational amplifier may operate at high speed, while the power consumption is saved. Incidentally, in the discharge cycle, the switch for load connection and disconnection is set in ON state, and the load is connected to the output terminal of the operational amplifier, so that the liquid crystal capacitors of the liquid crystal panel may be charged and discharged as usual, and a desired display may be appeared. 
     The eighth embodiment of the output circuit comprising a DA converter for composing the LCD control system of the invention is described below while referring to FIG. 9 to FIG. 12. 
     FIG. 9 is a structural diagram showing the output circuit in the eighth embodiment of the LCD control system of the invention. In FIG. 9, a capacitor 52 is connected between the output terminal and inverting input terminal A of an operational amplifier 51, and functions as a negative feedback circuit, and a load capacitor 53 comprises a liquid crystal capacitor and wiring capacitor of the TFT liquid crystal panel (corresponding to the TFT liquid crystal panel 1 in FIG. 1). Plural capacitors 54 to 56 have their one end each connected to the inverting input terminal A of the operational amplifier 51. A switch 57 is connected between the output terminal and the inverting input terminal A of the operational amplifier 51. Switches 58 to 60 are connected between the other ends of the capacitors 54 to 56 and the power source terminal, and switches 61 to 63 are connected between the other ends of the capacitors 54 to 56 and the ground. 
     In the diagram, the switches 57 to 63 are shown in a form of mechanical switches, but actually they are analog switches becoming ON or OFF depending on the digital input data. 
     In the embodiment, a switch 64 for connection or disconnection of the load is connected between the output terminal of the operational amplifier 51 and the load capacitor 53. This switch 64 is also an analog switch turned on or off by the digital input data. 
     In thus composed LCD control system in FIG. 9, its operation is described below. 
     in this LCD control system, too, the basic operation consists of charge cycle and discharge cycle. 
     First the charge cycle is explained. In the charge cycle, the switch 57 is set in ON state, and the output terminal and inverting input terminal A of the operational amplifier 51 are short-circuited. At this time, the operational amplifier 51 works as voltage follower circuit. 
     In the charge cycle, moreover, the switch 64 for connecting and disconnecting the load is set in OFF state, and the load capacitor 53 is separated from the output terminal of the operational amplifier 51. 
     In this state, the switches 58 to 60 are set in ON slate, and the switches 61 to 63 are set in OFF state. At this time, the equivalent circuit is as shown in FIG. 10. Since the inverting input terminal A of the operational amplifier 51 is assumed to be grounded, the supply voltage is applied to the capacitors 54 to 56. 
     At this time, the load capacitor 53 is not connected to the output terminal of the operational amplifier 51, and the output terminal of the operational amplifier 51 is directly connected to the inverting input terminal A which is assumed to be grounded. Accordingly, a stable state is established in a short time. In the stable state, the output voltage V 0  of the operational amplifier 51 is at the ground level. 
     The discharge cycle is described below. Only three capacitors 54 to 56 are shown in FIG. 9, but actually there are as many as the number of bits of the digital input data that is entered, and therefore the switches 58 to 63 are also as many as the number of bits actually. In the discharge cycle, the switches 58 to 63 are set in OFF state or in ON state depending on the digital input data for liquid crystal display, and the electric charges stored in the capacitors 54 to 56 are discharged depending on the digital data. 
     In the discharge cycle, moreover, the switch 64 for connecting and disconnecting the load connected to the output terminal of the operational amplifier 51 is set in ON state, and the load capacitor 53 is connected to the output terminal of the operational amplifier 51. 
     When the digital input data is 0, as shown in FIG. 11A, the capacitors 54 to 56 remain connected to the power source terminals. At this time, since there is no change in the input voltage at the inverting input terminal A of the operational amplifier 51, the output voltage V 0  of the output terminal remains at the ground level. 
     On the other hand, when the digital datas are all 1, as shown in FIG. 11B, the capacitors 54 to 56 are connected to the ground. At this time, the input voltage of the inverting input terminal A of the operational amplifier 51 is changed in the negative direction against the ground, and hence the output voltage of the operational amplifier 51 is changed in the positive direction, thereby raising the output voltage V 0  of the output terminal. This output voltage V 0  is applied to the load capacitor (the liquid crystal capacitor of the liquid crystal panel) 53 through the switch 64 for connecting and disconnecting the load, so that the display corresponding to the input data is appeared. 
     FIG. 12 is a timing chart showing with the charging operation and the discharge operation when the input data is 1 in the embodiment in FIG. 9. In FIG. 12, t 1  denotes the time until the charge cycle shown in FIG. 10 is completed, and t 2  is the time until the discharge cycle is completed. 
     In the LCD control system in FIG. 9, since the load capacitor 53 is separated from the output terminal of the operational amplifier 51 at the time of charging, the charge cycle time t 1  can be shortened. 
     Thus, in the embodiment in FIG. 9, in the LCD control system repeating the charge cycle and discharge cycle periodically, the operating speed can be accelerated by separating the load from the output terminal of the operational amplifier in charge cycle. Besides, since the load capacitor is not charged or discharged in the charge cycle, the power consumption may be reduced. 
     A ninth embodiment of output circuit for composing the LCD control system of the invention is described below by referring to FIG. 13 and FIG. 14. 
     In FIG. 13, a reference power source 65 is connected to a noninverting input terminal B of an operational amplifier 51. A reference power source 66 is at the same potential as the reference power source 65. A switch 67 is connected between an inverting input terminal A of the operational amplifier 51 and the reference power source 66, and it is an electronic switch turned on or off by a digital signal. Except for the switch 64 for connecting and disconnecting the load, the other constitution is same as in the output circuit in the embodiment shown in FIG. 9. 
     In thus composed LCD control system in FIG. 13, its operation is explained below. 
     In this LCD control system, too, the basic operation consists of charge cycle and discharge cycle. 
     First the charge cycle is explained. In the charge cycle, the switch 57 is set in ON state, and the output terminal and inverting input terminal A of the operational amplifier 51 are short-circuited. At this time, the operational amplifier 51 works as voltage follower circuit. Furthermore, in the charge cycle, the switch 67 for the reference power source is set in ON state. 
     In this state, the switches 58 to 60 are set in ON state, and the switches 61 to 63 are set in OFF state. At this time, the equivalent circuit becomes as shown in FIG. 14. Since the inverting input terminal A of the operational amplifier 51 is assumed to be grounded, the supply voltage is applied to the capacitors 54 to 56. 
     To the inverting input terminal A of the operational amplifier 51, the reference power source 66 at the same potential as the reference power source 65 is connected. To the load capacitor of the feedback circuit, the reference power source of a large output current and a stable voltage is connected, so that a stable state is established in a short time. In the stable state, the output voltage V 0  of the operational amplifier 51 is at the ground level. 
     The discharge cycle is explained. Only three capacitors 54 to 56 are shown in FIG. 13, but actually there are as many as the number of bits of the digital input data that is entered, and the switches 58 to 63 are also as many as the number of bits. In the discharge cycle after opening the switche 67 for reference power source, the switches 58 to 63 are set in ON or OFF state depending on the digital input data for liquid crystal display, and the electric charges stored in the capacitors 54 to 56 are discharged depending on the digital input data. In the discharge cycle, switches 58 to 63 are set in ON or OFF state, the electric charges stored in the capacitors 54 to 56 are moved into the capacitor 52, and an analog voltage depending on the digital input data is generated. 
     In the embodiment in FIG. 13, too, same as in the embodiment in FIG. 9, the charge cycle time t 1  in FIG. 12 may be shortened. 
     Thus, in the embodiment in FIG. 13, by connecting the reference power source to the input terminal of the operational amplifier at the time of charge cycle, the charging speed to the load capacitor of the feedback circuit may be accelerated. 
     The output circuits of the LCD control system in the foregoing embodiments are all composed of capacitive type DA converter, but it may be also possible to compose by using resistors, current source or oversampling. 
     Referring to FIG. 15, a tenth embodiment of an output circuit composed of a DA converter using resistors is explained below. 
     The switches 73 to 77 are turned on or off depending on the weight of the digital gray scale data. The resistors 78 to 82 divide the reference voltage 72, and generate gray scale voltages. Of the plural gray scale voltages generated by dividing, one gray scale voltage corresponding to the digital gray scale data is selected by one of the switches 73 to 77. The selected gray scale voltage is delivered through an operational amplifier 71 functioning as a voltage follower circuit. 
     The resistance type DA converter in FIG. 15 divides the reference voltage by plural resistors, and generates gray scale voltages and selects, among these gray scale voltages, the gray scale voltage depending on the digital gray scale data by the switches. 
     In the embodiment in FIG. 15, all resistance values of resistors are equal, but the number of resistors may be decreased by using a resistor having the resistance value proportional to the factorial of bits. 
     An eleventh embodiment of an output circuit composed of a DA converter using resistors is shown below while referring to FIG. 16. 
     The switches 94 to 97 are turned on or off depending on the digital gray scale data. Supposing all resistance values of input resistors 98 to 101 to be equal, the input currents flowing in the input resistances are all equal. The switches 94 to 97 are as many as the number of gray scales. When the switches 94 to 97 in the number corresponding to the digital gray scale data are set in ON state, an input current corresponding to the gray scale flows into the feedback resister 92. An output voltage corresponding to the input current is generated by the operational amplifier 91 and the feedback resister 92 functioning as current/voltage conversion circuit. 
     In the-embodiment in FIG. 16, the resistance values of all input resistors are equal, but the number of resistors may be decreased by using the resistor having a resistance value proportional to the factorial of bits. 
     A twelfth embodiment of an output circuit composed of a DA converter using constant current source is described below by reference to FIG. 17. 
     The switches 114 to 117 are turned on or off depending on the digital gray scale data. The constant current sources 118 to 121 as many as the number of gray scales are provided. Some of the constant current sources 118 to 121 are selected by some of the switches 114 to 117. The selected constant current sources are delivered by the operational amplifier 111 and the feedback resistance 112 functioning as current/voltage conversion circuit. 
     In the embodiment in FIG. 17, all current values of constant current sources are equal, but the number of constant current sources may be decreased by using a constant current source having the current value proportional to the factorial of bits. 
     A thirteenth embodiment of an output circuit composed of a DA converter using oversampling method is explained below by reference to FIG. 18. 
     In the embodiment in FIG. 18., the digital gray scale data is not transferred parallel, but is transferred serially. Examples of serial data are shown in FIG. 19. FIG. 19 is an example of transferring the pulse strings t 4  equal to the gray scale value of the digital gray scale data in a specific cycle t 3 . By the transfer serial data in FIG. 19, the switch 127 in FIG. 18 is turned on and off, a constant electric charge is moved from the reference voltage 126 to the integrating circuit 125. As a result, a voltage in an amplitude proportional to the digital gray scale data is generated in the integrating circuit 125. 
     According to the LCD control system of the invention, by disposing the DA converter immediately before the liquid crystal panel and processing the gray scale data directly in digital form without having to processing into analog form, the high speed analog circuit and regulating circuit may be omitted, and a display picture of high quality is obtained. 
     By employing the data latch means for storing the gray scale data and the adjustment-free DA converter for converting the output of digital data latch means into analog signal to be applied to the liquid crystal panel, the high speed analog circuit and regulating circuit are not needed, and the adjusting circuits necessary in the amplifier and the like may be reduced, so that the mass producibilty may be enhanced. 
     According to the output circuit used in the LCD control system of the invention, by turning on or off the switches depending on the bit information of digital signal, charging and discharging of capacitors may be realized by a refference voltage, and a necessary output voltage is generated, and it is hence not necessary to use many reference voltages. Therefore,the number of wirings and number of circuits may be reduced.