Abstract:
A semiconductor device includes a plurality of transistors formed on a semiconductor substrate, a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction, a second local wiring which is formed above the first local wiring and which electrically connects to at least one of the plurality of transistors and extends in a second direction, a plurality of first wirings which are formed above the second local wiring and which extend in a third direction, at least each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively, and a second wiring which is formed above the first wiring and which electrically connects to at least one of the plurality of first wirings and extends in a fourth direction.

Description:
[0001]    This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-87443 filed on Apr. 11, 2011, the content of which is incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device and a wiring layout method. 
         [0004]    2. Description of the Related Art 
         [0005]    A semiconductor device such as a dynamic random access memory (DRAM) and a flash memory are generally known for storing information. JP2010-27201A discloses one example of DRAM in its  FIG. 5 . The structure of a related semiconductor device will be explained with reference to  FIG. 1 .  FIG. 1  is a block diagram showing a structural example of the main part of the related semiconductor device. 
         [0006]    As shown in  FIG. 1 , semiconductor device  100  includes memory cell array  11  in which a plurality of memory cells are provided, and a peripheral circuit region for writing data into the memory cells and reading the data from the memory cells. The peripheral circuit region includes sub-word driver (SWD)  12 , X decoder  13 , sense amplifier (SA)  16 , Y decoder  17 , and data control circuit  18  for controlling input and output of the data. 
         [0007]      FIG. 2  shows one example of the layout of the X decoder shown in  FIG. 1 . As shown in  FIG. 2 , X decoder  13  includes a plurality of main-word drivers (MWDs)  14  and data control circuit  15 . The memory cells each having the same circuit are arranged in memory cell array  11 , but the same circuits are not arranged in a logic circuit such as the data control circuit  15 . MWD  14  is a type of logic circuit. As shown in  FIG. 2 , MWDs  14  each having the same circuit structure are repeatedly arranged to be adjacent to each other to provide an assembly of MWDs  14 . 
         [0008]    One example of the layout of the semiconductor device arranged in one MWD  14  will be explained below.  FIG. 3A ,  FIG. 3B  and  FIG. 4A  to  FIG. 4C  are plan views showing one example of the pattern layout in the structure of part of the MWD. 
         [0009]    In these drawings, the horizontal direction is referred to as an X-axis direction and the vertical direction is referred to as a Y-axis direction. The right direction is referred to as an X-axis positive direction and the upper direction is referred to as a Y-axis positive direction. If all semiconductor devices provided in MWDs  14  are illustrated, the wiring patterns are too complicated to clearly show the layout of the semiconductor devices and the wiring patterns. Accordingly, eight metal oxide semiconductor (MOS) transistors are extracted from the MWDs to explain the layout of the transistors and the wiring connected to the transistors as the structure necessary for explaining the problem to be solved by the present invention. 
         [0010]      FIG. 3A  is a plan view showing the layout of active regions and gate electrodes. The active region is surrounded by an isolation region on the surface of the semiconductor substrate, in which source electrodes and drain electrodes of the MOS transistors are formed. A channel region is provided between the source electrode and the drain electrode in the active region. 
         [0011]    In the region shown in  FIG. 3A , four MOS transistors  21   a  to  21   d  are arranged on the upper stage in the X-axis direction and four MOS transistors  31   a  to  31   d  are arranged on the lower stage in the X-axis direction. 
         [0012]    Hereinafter, the MOS transistor is simply referred to as a “transistor”. The following explanation is given on the premise that transistors  21   a  to  21   d  and  31   a  to  31   d  are N MOS transistors. However, transistors  21   a  to  21   d  and  31   a  to  31   d  may be PMS transistors. 
         [0013]    Four transistors  21   a  to  21   d  on the upper stage shown in  FIG. 3A  share active region  24 . Gate electrode  22   a  of transistor  21   a  is provided by combining two rectangle patterns into one. The longitudinal direction of the rectangle patterns corresponds to the Y-axis direction. The drain electrode is arranged between the two rectangle patterns. Other transistors  21   b  to  21   d  have the same structure as transistor  21   a.  The gate electrodes  22   a  to  22   d  are arranged in parallel. Each of transistors  21   a  to  21   d  shares the source electrode with the adjacent transistor. A channel longitudinal direction corresponds to the X-axis direction and a channel width direction corresponds to the Y-axis direction. 
         [0014]    Four transistors  31   a  to  31   d  on the lower stage are paired. A pair of transistors share the active region. In the example shown in  FIG. 3A , transistors  31   a  and  31   b  share active region  34   a  and transistors  31   c  and  31   d  share another active region  34   b.  Gate electrodes  32   a  to  32   d  of transistors  31   a  to  31   d  are provided by rectangle patterns. The longitudinal direction thereof corresponds to the Y-axis direction. Gate electrodes  32   a  to  32   d  are arranged in parallel. 
         [0015]    As shown in  FIG. 3A , in each of gate electrodes  22   a  to  22   d  of the four transistors on the upper stage, the connection portion between the two rectangle patterns is arranged to be more negative than each transistor in the Y-axis negative direction. In the four transistors on the lower stage, drawing-out portions of gate electrodes  32   a  and  32   d  are arranged to be more positive than transistors  31   a  and  31   d  in the Y-axis positive direction, and drawing-out portions of gate electrodes  32   b  and  32   c  are arranged to be more negative than transistors  31   b  and  31   c  in the Y-axis negative direction. 
         [0016]    Incidentally, contacts formed on the active region shown in  FIG. 3A  will be explained later in detail. Gate electrodes  22   a  to  22   d  and  32   a  to  32   d  are made of polycide provided by laminating refractory metal films on a polysilicon film on which conductive impurities are diffused. 
         [0017]      FIG. 3B  is a plan view showing the layout of tungsten wirings formed on a layer above the gate electrodes shown in  FIG. 3A . Tungsten wirings  25   a  to  25   d,    35   a  to  35   d,    36   a,    36   b,    37   a,  and  37   b  are provided on gate electrodes  22   a  to  22   d  and  32   a  to  32   d  shown in  FIG. 3A  through interlayer insulating film  81 . Tungsten wirings  25   a  to  25   d  are connected to the drain electrodes of transistors  21   a  to  21   d  through contacts  41 , respectively. 
         [0018]    Gate electrode  22   a  shown in  FIG. 3A  is connected to the drain electrode of transistor  31   a  through contacts  41  and tungsten wiring  35   a.  Similarly, gate electrode  22   b  shown in  FIG. 3A  is connected to the drain electrode of transistor  31   b  through contacts  41  and tungsten wiring  35   b,  and gate electrode  22   c  is connected to the drain electrode of transistor  31   c  through contacts  41  and tungsten wiring  35   c.  Further, gate electrode  22   d  shown in  FIG. 3A  is connected to the drain electrode of transistor  31   d  through contacts  41  and tungsten wiring  35   d.    
         [0019]    Gate electrode  32   a  shown in  FIG. 3A  is connected to tungsten wiring  36   a  through contacts  41 , and gate electrode  32   b  is connected to tungsten wiring  36   b  through contacts  41 . Gate electrode  32   c  shown in  FIG. 3A  is connected to tungsten wiring  36   c  through contacts  41 , and gate electrode  32   d  is connected to tungsten wiring  36   d  through contacts  41 . 
         [0020]    The source electrode shared by transistors  31   a  and  31   b  shown in  FIG. 3A  is connected to tungsten wiring  37   a  through contacts  41 , and the source electrode shared by transistors  31   c  and  31   d  is connected to tungsten wiring  37   b  through contacts  41 . 
         [0021]      FIG. 4A  is a plan view showing the layout of a conductive pad formed on a layer above the tungsten wirings shown in  FIG. 3B . Conductive pad  51  shown in  FIG. 4A  is provided on tungsten wirings  25   a  to  25   d  shown in  FIG. 3B  through interlayer insulating film  82 . Conductive pad  51  is made of tungsten. Conductive pad  51  is arranged on the upper stage in  FIG. 4A . The source electrodes of transistors  21   a  to  21   d  shown in  FIG. 3A  are connected to conductive pad  51  through contacts  41  and  43 . 
         [0022]      FIG. 4B  is a plan view showing the layout of first aluminum (Al) wirings formed on a layer above the conductive pad shown in  FIG. 4A .  FIG. 4B  shows AL wirings  62   a  to  62   d  and  64   a  to  64   d  that correspond to the first Al wirings, and via holes  45  that correspond to first via holes. 
         [0023]    Al wirings  62   a  to  62   d  and  64   a  to  64   d  are provided on conductive pad  51  shown in  FIG. 4A  through interlayer insulating film  83 . Al wiring  64   a  is connected to tungsten wiring  36   a  shown in  FIG. 3B  through via hole  45 , and Al wiring  64   b  is connected to tungsten wiring  36   b  shown in  FIG. 3B  through via hole  45 . Similarly, Al wiring  64   c  is connected to tungsten wiring  36   c  shown in  FIG. 3B  through via hole  45 , and Al wiring  64   d  is connected to tungsten wiring  36   d  through via hole  45 . Al wirings  62   a  to  62   d  correspond to a main-word line (MWL) for transmitting a selection/non-selection signal of MWD  14  to SWD  12 . Al wirings  64   a  to  64   d  correspond to a MWD selection signal supply line that relays an address signal for selecting MWD  14 . 
         [0024]      FIG. 4C  is a plan view showing a state after second via holes and second Al wirings are formed.  FIG. 4C  shows via holes  47  that correspond to the second via holes, and Al wirings  71   a  to  71   d  that correspond to the second Al wirings. 
         [0025]    Al wirings  71   a  to  71   d  are provided on Al wirings  62   a  to  62   d  and  64   a  to  64   d  shown in  FIG. 4B  through interlayer insulating film  84 . The address signal for selecting MWD  14  is inputted from the outside to Al wirings  71   a  to  71   d . Al wiring  71   a  is connected to Al wiring  64   a  through via hole  47 . Al wiring  71   a  is connected to gate electrode  32   a  shown in  FIG. 3A  through Al wiring  64   a  shown in  FIG. 4B  and tungsten wiring  36   a  shown in  FIG. 3B . Al wiring  71   b  is connected to Al wiring  64   b  through via hole  47 . Al wiring  71   b  is connected to gate electrode  32   b  through Al wiring  64   b  and tungsten wiring  36   b.    
         [0026]    Al wiring  71   c  is connected to Al wiring  64   c  through via hole  47 . Al wiring  71   c  is connected to gate electrode  32   c  through Al wiring  64   c  and tungsten wiring  36   c.  Al wiring  71   d  is connected to Al wiring  64   d  through via hole  47 . Al wiring  71   d  is connected to gate electrode  32   d  through Al wiring  64   d  and tungsten wiring  36   d.    
         [0027]    As shown in FIG,  4 C, the direction where the second Al wirings extend corresponds to the X-axis direction, and also corresponds to the direction where the plurality of MWDs  14  are arranged in parallel. As shown in  FIG. 4B , the direction where the first Al wirings extend corresponds to the direction that intersects the X-axis direction (i.e., Y-axis direction). 
         [0028]    The address signal for selecting MWD  14  is supplied from the outside through any one of Al wirings  71   a  to  71   d  serving as the second Al wirings, and is inputted to a predetermined transistor device through a MWD selection signal supply line out of Al wiring  64   a  to  64   d  serving as the first Al wirings which corresponds to the second Al wirings. More specifically, the address signal is supplied to the second Al wirings, the MWD selection signal supply line, the tungsten wiring, and the predetermined transistor device in this order. 
         [0029]    As described above, Al wirings  62   a  to  62   d  that correspond to MWL of MWD  14  are provided on the first wiring layer on which the first Al wirings are formed in the area where MWDs  14  are provided. Accordingly, the MWD selection signal supply lines and the MWLs are arranged on the first wiring layer corresponding to the MWDs that are repetitively arranged. 
         [0030]    As shown in  FIG. 4B , the MWD selection signal supply lines and MWLs are arranged on the first wiring layer in the MWD region at the minimum pitch for ensuring insulation properties, thus area of the MWD selection signal supply lines and MWLs occupies the most part of the area of MWD region. Even though the interval of the memory cells can be reduced by downsizing the memory cells and the pitch of the patterns is relaxed by wiring except for the first Al wirings, a reduction in the entire circuit of the MWDs is suppressed by the pitches of the first Al wirings in the MWD region and thus a reduction in the entire circuit of the semiconductor device is prevented. 
       SUMMARY 
       [0031]    In one embodiment, there is provided a semiconductor device that includes: a semiconductor substrate; a plurality of transistors formed on the semiconductor substrate; a first local wiring layer including a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction; a second local wiring layer which is formed above the first local wiring layer and which includes a second local wiring electrically connected to at least one of the plurality of transistors and extending in a second direction; a first wiring layer which is formed above the second local wiring layer and which includes a plurality of first wirings extending in a third direction, each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively; and a second wiring layer which is formed above the first wiring layer and which includes second wirings electrically connected to at least one of the plurality of first wirings and extending in a fourth direction. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0032]    The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0033]      FIG. 1  is a block diagram showing a structural example of the main part of a related semiconductor device; 
           [0034]      FIG. 2  shows one example of the layout of an X decoder shown in  FIG. 1 ; 
           [0035]      FIG. 3A  is a plan view showing the layout of a part of a MWD of the related semiconductor device; 
           [0036]      FIG. 3B  is a plan view showing the layout of another part of the MWD of the related semiconductor device; 
           [0037]      FIG. 4A  is a plan view showing the layout of another part of the MWD of the related semiconductor device; 
           [0038]      FIG. 4B  is a plan view showing the layout of another part of the MWD of the related semiconductor device; 
           [0039]      FIG. 4C  is a plan view showing the layout of another part of the MWD of the related semiconductor device; 
           [0040]      FIG. 5A  is a plan view showing the layout of a part of a MWD of a semiconductor device according to a first embodiment; 
           [0041]      FIG. 5B  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the first embodiment; 
           [0042]      FIG. 6A  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the first embodiment; 
           [0043]      FIG. 6B  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the first embodiment; 
           [0044]      FIG. 6C  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the first embodiment; 
           [0045]      FIG. 7  is a cross-sectional view for explaining the wiring structure of the semiconductor device according to the first embodiment; 
           [0046]      FIG. 8  is a cross-sectional view for explaining structures of a memory cell array region and a peripheral circuit region; 
           [0047]      FIG. 9A  is a plan view showing the layout of a part of a MWD of a semiconductor device according to a first example; 
           [0048]      FIG. 9B  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the first example; 
           [0049]      FIG. 9C  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the first example; 
           [0050]      FIG. 10A  is a plan view showing the layout of a part of a MWD of a semiconductor device according to a second example; 
           [0051]      FIG. 10B  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the second example; 
           [0052]      FIG. 10C  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the second example; 
           [0053]      FIG. 11A  is a plan view showing the layout of a part of a MWD of a semiconductor device according to a second embodiment; and 
           [0054]      FIG. 11B  is a plan view showing the layout of another part of the MWD of the semiconductor device according to the second embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0055]    The invention will now be described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes. 
       First Embodiment  
       [0056]    The structure of a semiconductor device according to a first embodiment will be explained below. The semiconductor device according to the first embodiment has the structure as shown in  FIGS. 1 and 2 . The structure of MWDs  14  shown in  FIG. 2  is different from that in a related semiconductor device. The structure of the MWDs in the semiconductor device according to the first embodiment will be explained below. 
         [0057]      FIG. 5A ,  FIG. 5B  and  FIG. 6A  to  FIG. 6C  are plan views showing one example of the pattern layout in the structure of part of the MWD in the semiconductor device according to the first embodiment. In these drawings, the horizontal direction is referred to as an X-axis direction and the vertical direction is referred to as a Y-axis direction. 
         [0058]      FIG. 5A  is a plan view showing the layout of active regions and gate electrodes. In the region shown in  FIG. 5A , four transistors  21   a  to  21   d  are arranged on the upper stage in the X-axis direction and four transistors  31   a  to  31   d  are arranged on the lower stage in the X-axis direction. The layout shown in  FIG. 5A  is the same as the layout explained with reference to  FIG. 3A , and thus the detailed explanation thereof is omitted. 
         [0059]      FIG. 5B  is a plan view showing the layout of tungsten wirings formed on a layer above the gate electrodes shown in  FIG. 5A . 
         [0060]    Tungsten wirings  25   a  to  25   d,    35   a  to  35   d,    37   a,  and  37   b  are provided on gate electrodes  22   a  to  22   d  and  32   a  to  32   d  shown in  FIG. 5A  through interlayer insulating film  81 . Tungsten wirings  25   a  to  25   d  are connected to the drain electrodes of transistors  21   a  to  21   d  through contacts  41 , respectively. 
         [0061]    Compared to the layout shown in  FIG. 3B , tungsten wirings  36   a  to  36   d  shown in  FIG. 3B  are not provided in the layout shown in  FIG. 5B . The structure of tungsten wirings  35   a  to  35   d,    37   a  and  37   b  is the same as the structure explained with reference to  FIG. 3B , and thus a detailed explanation thereof is omitted. Incidentally, tungsten wirings  35   a  to  35   d,    37   a,  and  37   b  serve as local wirings for connecting the gate electrodes of the transistors on the upper stage shown in  FIG. 5A  and the drain electrodes of the transistors on the lower stage shown in  FIG. 5A . These local wirings correspond to first local wirings of the present invention, and a wiring layer where tungsten wirings  25   a  to  25   d,    35   a  to  35   d,    37   a,  and  37   b  are provided corresponds to a first local wiring layer of the present invention. 
         [0062]      FIG. 6A  is a plan view showing the layout of a conductive pad and local wirings formed on a layer above the tungsten wirings shown in  FIG. 5B . Conductive pad  51  and local wirings  52   a  to  52   d  shown in  FIG. 6A  are provided on tungsten wirings  25   a  to  25   d,    35   a  to  35   d,    37   a,  and  37   b  shown in  FIG. 5B  through interlayer insulating film  82 . Local wirings  52   a  to  52   d  are formed on the layer where conductive pad  51  is formed, and are made of tungsten. 
         [0063]    Conductive pad  51  is arranged on the upper stage in  FIG. 5A . The source electrodes of transistors  21   a  to  21   d  shown in  FIG. 5A  are connected to conductive pad  51  through contacts  41  and  43 . Conductive pad  51  serves as a power wiring for supplying the power potential and ground potential to transistors  21   a  to  21   d . Local wirings  52   a  to  52   d  are arranged on the lower stage in  FIG. 5A . Local wirings  52   a  to  52   d  correspond to the second local wirings of the present invention, and a wiring layer where conductive pad  51  and local wirings  52   a  to  52   d  are provided corresponds to a second local wiring layer of the present invention. 
         [0064]    The longitudinal direction of the patterns of local wirings  52   a  and  52   b  corresponds to the X-axis direction. Local wirings  52   a  and  52   b  are arranged in parallel to be spaced at a predetermined distance from each other. The longitudinal direction of the patterns of local wirings  52   c  and  52   d  corresponds to the X-axis direction. Local wirings  52   c  and  52   d  are arranged in parallel to be spaced at a predetermined distance from each other. Local wiring  52   a  is connected to gate electrode  32   a  shown in  FIG. 5A  through contacts  41  and  43 , and local wiring  52   b  is connected to gate electrode  32   b  through contacts  41  and  43 . Local wiring  52   c  is connected to gate electrode  32   c  shown in  FIG. 5A  through contacts  41  and  43 , and local wiring  52   d  is connected to gate electrode  32   d  through contacts  41  and  43 . 
         [0065]      FIG. 6B  is a plan view showing the layout of the first Al wirings formed on a layer above the conductive pad shown in  FIG. 6A .  FIG. 6B  shows Al wirings  61   a  to  61   d  and  62   a  to  62   d  that correspond to the first Al wirings, and via holes  45  that correspond to the first via holes. 
         [0066]    Al wirings  61   a  to  61   d  and  62   a  to  62   d  are provided on conductive pad  51  and local wirings  52   a  to  52   d  shown in  FIG. 6A  through interlayer insulating film  83 . The structure of Al wirings  62   a  to  62   d  is the same as that shown in  FIG. 4B . The longitudinal direction of the patterns of Al wirings  62   a  to  62   d  corresponds to the Y-axis direction. Al wirings  62   a  to  62   d  are arranged in parallel. 
         [0067]    The layout shown in  FIG. 6B  will be explained as compared with the layout shown in  FIG. 4B . Al wirings  61   a  and  61   b  are arranged instead of Al wiring  64   a  shown in  FIG. 4B . When the length in the direction orthogonal to the longitudinal direction of the wiring patterns is defined as the width, Al wirings  61   a  and  61   b  are disposed at the same position in the X-axis direction and the patterns thereof have the same width. Al wirings  61   c  and  61   d  are arranged instead of Al wiring  64   d  shown in  FIG. 4B . Al wirings  61   c  and  61   d  are disposed at the same position in the X-axis direction and the patterns thereof have the same width. Al wirings  64   b  and  64   c  shown in  FIG. 4B  are not provided in the layout shown in  FIG. 6B . Since the patterns for Al wirings  64   b  and  64   c  shown in  FIG. 4B  can be eliminated according to the first embodiment, a space for two wirings indicated by dashed lines in  FIG. 6B  can be obtained. 
         [0068]    Al wiring  61   a  is connected to local wiring  52   a  shown in  FIG. 6A  through via hole  45 , and Al wiring  61   b  is connected to local wiring  52   b  shown in  FIG. 6A  through via hole  45 . Similarly, Al wiring  61   c  is connected to local wiring  52   c  shown in  FIG. 6A  through via hole  45 , and Al wiring  61   d  is connected to local wiring  52   d  shown in FIG,  6 A through via hole  45 . 
         [0069]      FIG. 6C  is a plan view showing a state after the second via holes and the second Al wirings are formed.  FIG. 6C  shows via holes  47  that correspond to the second via holes, and Al wirings  71   a  to  71   d  that correspond to the second Al wirings. Hereinafter, a wiring layer where the second Al wirings are formed is referred to as a second wiring layer. 
         [0070]    Al wirings  71   a  to  71   d  are provided on Al wirings  61   a  to  61   d  and  62   a  to  62   d  shown in  FIG. 6B  through interlayer insulating film  84 . The longitudinal direction of the patterns of Al wirings  71   a  to  71   d  corresponds to the X-axis direction. Al wirings  71   a  to  71   d  are arranged in parallel. 
         [0071]    Al wiring  71   a  is connected to Al wiring  61   a  through via hole  47 . Al wiring  71   a  is connected to gate electrode  32   a  shown in  FIG. 5A  through Al wiring  61   a  shown in  FIG. 6B  and local wiring  52   a  shown in  FIG. 6A . Al wiring  71   b  is connected to Al wiring  61   b  through via hole  47 . Al wiring  71   b  is connected to gate electrode  32   b  through Al wiring  61   b  and local wiring  52   b.    
         [0072]    Al wiring  71   c  is connected to Al wiring  61   c  through via hole  47 . Al wiring  71   c  is connected to gate electrode  32   c  through Al wiring  61   c  and local wiring  52   c.  Al wiring  71   d  is connected to Al wiring  61   d  through via hole  47 . Al wiring  71   d  is connected to gate electrode  32   d  through Al wiring  61   d  and local wiring  52   d.    
         [0073]    Compared to the layout shown in  FIG. 4C , the positions of via holes  47  are different in the layout shown in  FIG. 6C . It is because the positions of via holes  47  are provided corresponding to the positions of Al wirings  61   a  to  61   d . Also, the order of Al wirings  71   a  to  71   d  is different. In  FIG. 4C , Al wirings  71   b ,  71   c,    71   a,  and  71   d  are provided in this order in the Y- axis positive direction. In  FIG. 6C , Al wiring  71   c,    71   b,    71   d,  and  71   a  are provided in this order in the Y-axis positive direction. This order is decided to connect Al wirings  61   a  to  61   d  to Al wirings  71   a  to  71   d  through via holes  47 , respectively. 
         [0074]    Next, the operation of the control circuit provided by transistors  31   a  and  31   b  out of transistors  31   a  to  31   d  shown in  FIG. 5A  will be briefly explained below. Here, a signal having a voltage level that is not less than the threshold voltage of transistors  21   a  to  21   d  and  31   a  to  31   d  is referred to as a High signal. The power potential or ground potential is applied to the source electrode shared by transistors  31   a  and  31   b  from the outside through tungsten wiring  37   a.    
         [0075]    When a High signal is inputted to Al wiring  71  a from the outside, the High signal is transmitted to gate electrode  32   a  through Al wiring  61  a and local wiring  52   a.  When gate electrode  32   a  is raised to the voltage level of the High signal, transistor  31   a  is turned on. When transistor  31   a  is turned on, the source and the drain electrodes have a conduction channel between them, so that a signal having a voltage level of the source electrode shared by transistors  31   a  and  31   b  is transmitted to gate electrode  22   a  of transistor  21   a  through tungsten wiring  35   a.    
         [0076]    On the other hand, when a High signal is inputted to Al wiring  71   b  from the outside, the High signal is transmitted to gate electrode  32   b  through Al wirings  71   b  and  61   b  and local wiring  52   b.  When gate electrode  32   b  is raised to the voltage level of the High signal, transistor  31   b  is turned on. When transistor  31   b  is turned on, the source and the drain electrodes have a conduction channel between them, so that a signal having a voltage level of the source electrode shared by transistors  31   a  and  31   b  is transmitted to gate electrode  22   b  of transistor  21   b  through tungsten wiring  35   b.    
         [0077]    Next, the cross-sectional structure of part of the MWD explained with reference to  FIGS. 5A to 6C  will be explained below.  FIG. 7  is a cross-sectional view for explaining the cross-sectional structure of the semiconductor device according to the first embodiment. In  FIG. 7 , the reference numerals of the typical patterns of the respective wiring layers are marked. Tungsten wiring  54  indicates wiring of the tungsten layer where conductive pad  51  and local wirings  52   a  to  52   d  are formed as shown in  FIG. 6A . 
         [0078]    As shown in  FIG. 7 , the active region  24  provided adjacent to the surface of the semiconductor substrate (not shown) is connected to tungsten wiring  25  through contact  41 . The active region  24  is also connected to tungsten wiring  54  through a laminated plug provided by placing contact  43  on contact  41 . At this time, tungsten wiring  54  is conductive pad  51 . 
         [0079]    Gate electrode  22  is connected to tungsten wiring  25  through contact  41 , and also connected to tungsten wiring  54  through the laminated plug. At this time, tungsten wiring  54  is local wirings  52   a  to  52   d.  Tungsten wirings  25  and  54  are connected to Al wiring  61  through via hole  45 . Al wiring  61  provided on the first wiring layer is connected to Al wiring  71  provided on the second wiring layer through via hole  47 . 
         [0080]    The cross-sectional structure of the peripheral circuit region including the MWDs will be explained below as compared to the cross-sectional structure of the memory cell array region. 
         [0081]      FIG. 8  is a cross-sectional view for explaining the structure of the memory cell array region and the peripheral circuit region. The cross-section of the peripheral circuit region shown in  FIG. 8  is the cross-section of part of the MWD. Here, the cross-sections taken along the line A-A and the line B-B in  FIGS. 5A to 6C  are illustrated. 
         [0082]    The structure of the memory cell array region will be explained with reference to  FIG. 8 . A plurality of memory cells having control transistors including gate electrode  22   e  and capacitor  90  serving as a memory element on semiconductor substrate  101  are provided in the memory cell array region. Capacitor  90  is provided by lower electrode  91 , capacitor insulating film  92 , and upper electrode  93 . 
         [0083]    Contact pad  55  connected to the bottom portion of lower electrode  91  is provided on the side close to the lower surface of the lower electrode  91 . Contact pad  55  prevents displacement between the bottom portion of lower electrode  91  and contact  43   a  in the process of manufacturing the semiconductor device according to the first embodiment. 
         [0084]    The drain electrode of the control transistor is connected to bit line  35   e  through bit contact  41   a.  The source electrode of the control transistor is connected to contact  43   a  through cell contact  41   b . Contact  43   a  is connected to lower electrode  91  of capacitor  90  through contact pad  55 . Upper electrode  93  of capacitor  90  is connected to Al wiring  61  e through via hole  45   a.    
         [0085]    With reference to  FIG. 8 , the structure of the wiring layer and the plug layer will be explained as compared to the peripheral circuit region and the memory cell array region. 
         [0086]    Gate electrode  22   e  is provided in the memory cell array region and on the same layer where gate electrodes  32   a  and  32   b  are provided in the peripheral circuit region. Bit contact  41   a  and cell contact  41   b  are provided in the memory cell array region and on the same layer where contact  41  is provided in the peripheral circuit region. Bit line  35   e  is provided in the memory cell array region and on the same layer where tungsten wirings  35   a,    35   b,  and  37   a  are provided in the peripheral circuit region. 
         [0087]    Contact  43  provided in the peripheral circuit region is formed simultaneously with contact  43   a  provided in the memory cell array region in the process of manufacturing the semiconductor device. Contact pad  55  is provided in the memory cell array region and on the same layer where local wiring  52   a  is provided in the peripheral circuit region. In the cross-section taken along the line B-B of the peripheral circuit region shown in  FIG. 8 , local wiring  52   a  is connected to gate electrode  32   a  through contact  43 . However, as shown in  FIG. 7 , local wiring  52   a  may be connected to gate electrode  32   a  using the laminated plug provided by contacts  41  and  43 . 
         [0088]    Via hole  45  provided in the peripheral circuit region is formed simultaneously with via hole  45   a  provided in the memory cell array region in the process of manufacturing the semiconductor device. Al wiring  61   e  is provided in the memory cell array region and on the same layer where Al wirings  61   a ,  61   b ,  62   a,  and  62   b  are provided in the peripheral circuit region. In the peripheral circuit region, a space indicated by a dashed line is provided on the first wiring layer. 
         [0089]    As explained with reference to  FIG. 8 , the wiring and plug are formed in the peripheral circuit region simultaneously with the formation of the wiring and plug in the memory cell array region. Comparing  FIG. 4A  with  FIG. 6A , the patterns of local wirings  52   a  to  52   d  are added in the first embodiment. However, a step of forming a new conductive layer is not necessary because conductive pad  51  and contact pad  55  are formed on the same layer. 
         [0090]    Since the second local wiring for connecting the first wiring to one of the transistors is provided between the first local wiring layer and the first wiring layer according to this embodiment, a part of the wiring pattern formed on the first wiring layer can be omitted. Thus, a space can be obtained on the first wiring provided by repeating a line-and-space pattern. 
         [0091]    The patterns of the local wirings formed on the same layer where the contact pad is formed are provided in parallel in the MWD region in the X-axis direction. The MWD selection signal supply lines for connecting the second Al wirings corresponding to the local wirings have the same length in the X-axis direction, and are connected to the local wirings at the same position in the X-axis direction. Thus, a space can be obtained on the first wiring layer in the MWD region in the X-axis direction. 
         [0092]    Since the space can be obtained on the first wiring layer according to this embodiment, the space occupied by the wirings can be reduced and the wiring drawn in other regions can be positioned. Consequently, the entire MWD circuit can be downsized and thus the entire circuit of the semiconductor device can be downsized. 
         [0093]    Further, by positioning the draw wiring in the space on the first wiring layer, the second Al wiring which is not used in the MWD can be drawn out to the circuit outside the MWD region. To connect the second Al wirings in two regions sandwiching the MWD region, the draw wiring is provided in the space on the first wiring layer. Accordingly, the second Al wirings in the two regions can be connected by the draw wiring. 
         [0094]    In this embodiment, gate electrodes  32   a  to  32   d  of transistors  31   a  to  31   d  are drawn out to the second Al wiring through the local wiring. However, the source electrodes or drain electrodes may be drawn instead of the gate electrodes. 
         [0095]    Also, in this embodiment, the structure of the semiconductor device is explained. However, the layout of the wiring layer and the plug layer explained with reference to  FIG. 5A  to  FIG. 6C  may be adopted to the wiring layout method at the stage of designing the circuit pattern. The wiring layout method according to this embodiment may be adopted to computer aided design (CAD) by executing a program in which the wiring layout method according to this embodiment is described. 
       FIRST EXAMPLE  
       [0096]    The first example is another structural example for obtaining a space for two wirings on the first wiring layer. In this example, a detailed explanation of the same structure as that of the semiconductor device explained with reference to  FIG. 5A  to  FIG. 8  is omitted, and only features different from the semiconductor device according to the first embodiment will be explained in detail below. 
         [0097]      FIGS. 9A to 9C  are plan views showing one example of the pattern layout of part of the MWD in the semiconductor device according to this example. In these drawings, the horizontal direction is referred to as an X-axis direction and the vertical direction is referred to as a Y-axis direction. In this example, the layout of the active regions and the gate electrodes is the same as in  FIG. 5A  and the layout of the tungsten wirings formed on the layer above the gate electrodes is the same as in  FIG. 5B , and thus a detailed explanation thereof is omitted.  FIG. 9A  shows the layout of the conductive pad and the local wirings according to this example, but their layout is the same as in  FIG. 6A . Thus, a detailed explanation thereof is omitted. 
         [0098]      FIG. 9B  is a plan view showing the layout of the first Al wirings formed on the layer above the conductive pad shown in  FIG. 9A .  FIG. 9B  shows Al wirings  61   a  to  61   d  and  62   a  to  62   d  that correspond to the first Al wirings, and via holes  45  that correspond to the first via holes. 
         [0099]    The layout shown in  FIG. 9B  will be explained as compared with the layout shown in  FIG. 4B . Similarly to the layout shown in  FIG. 6B , Al wirings  61   a  and  61   b  are provided instead of Al wiring  64   a  shown in  FIG. 4B , and Al wirings  61   c  and  61   d  are provided instead of Al wiring  64   d  shown in  FIG. 4B . In this example, Al wiring  62   a  is provided at the position where Al wiring  62   b  is provided as shown in  FIG. 4B , and Al wiring  62   b  is provided at the position where Al wiring  64   b  is provided as shown in  FIG. 4B . Al wiring  62   c  is provided at the position where Al wiring  64   c  is provided as shown in  FIG. 4B , and Al wiring  62   d  is provided at the position where Al wiring  62   c  is provided as shown in  FIG. 4B . Since wiring is not provided at the position where Al wirings  62   a  and  62   d  are provided as shown in  FIG. 4B , a space for two wirings indicated by dashed lines in  FIG. 9B  can be obtained. 
         [0100]      FIG. 9C  is a plan view showing a state after the second via holes and the second Al wirings are formed.  FIG. 9C  shows via holes  47  that correspond to the second via holes, and Al wirings  71   a  to  71   d  that correspond to the second Al wirings. 
         [0101]    In this example, Al wirings  61   a  to  61   d  are connected to Al wirings  71  a to  71   d  through via holes  47 , respectively. Compared to the layout shown in FIG. 
         [0102]      6 C, the positions of via holes  47  and the order of Al wirings  71   a  to  71   d  are different in the layout shown in  FIG. 9C . As already explained above in the first embodiment, this is because the first Al wirings and the second Al wirings are connected corresponding to the positions of via holes  47 . The layout of via holes  47  and Al wirings  71   a  to  71   d  may be the same as that shown in  FIG. 6C . 
         [0103]    Since space for one wiring is provided on both ends of the MWD in the layout on the first wiring layer, space for two wirings can be obtained between adjacent MWDs. 
       SECOND EXAMPLE  
       [0104]    The second example is another structural example for obtaining space for three wirings on the first wiring layer. In this example, the detailed explanation of the same structure as that of the semiconductor device explained with reference to  FIG. 5A  to  FIG. 8  is omitted, and only features different from the semiconductor device according to the first embodiment will be explained in detail below. 
         [0105]      FIGS. 10A to 10C  are plan views showing one example of the pattern layout of part of the MWD in the semiconductor device according to this example. In these drawings, the horizontal direction is referred to as an X-axis direction and the vertical direction is referred to as a Y-axis direction. In this example, the layout of the active regions and the gate electrodes is the same as in  FIG. 5A  and the layout of the tungsten wirings formed on the layer above the gate electrodes is the same as in  FIG. 5B . Thus, a detailed explanation thereof is omitted. 
         [0106]      FIG. 10A  is a plan view showing the layout of the conductive pad and local wirings formed on the layer above the tungsten wirings shown in  FIG. 5B . Conductive pad  51  and local wirings  53   a  to  53   d  shown in  FIG. 10A  are provided on tungsten wirings  25   a  to  25   d,    35   a  to  35   d,    37   a,  and  37   b  shown in  FIG. 5B  through interlayer insulating film  82 . Local wirings  53   a  to  53   d  are formed on the same layer where conductive pad  51  is formed, and are made of tungsten. 
         [0107]    Local wirings  53   a  to  53   d  are arranged on the lower stage in  FIG. 10A . The longitudinal direction of the patterns of local wirings  53   a  to  53   d  corresponds to the X-axis direction. Local wirings  53   a  to  53   d  are arranged in parallel to be spaced at a predetermined distance from each other. Local wiring  53   a  is connected to gate electrode  32   a  through contacts  41  and  43 , and local wiring  53   b  is connected to gate electrode  32   b  through contacts  41  and  43 . 
         [0108]    Local wiring  53   d  has a rectangular shape whose a distal portion protrudes in the Y-axis positive direction. This rectangular-shaped portion is connected to gate electrode  32   d  through contacts  41  and  43 . Local wiring  53   c  has a rectangular shape whose a distal portion protrudes in the Y-axis negative direction. This rectangular-shaped portion is connected to gate electrode  32   c  through contacts  41  and  43 . 
         [0109]      FIG. 10B  is a plan view showing the layout of the first Al wirings formed on the layer above the conductive pad shown in  FIG. 10A .  FIG. 10B  shows Al wirings  62   a  to  62   d  and  63   a  to  63   d  that correspond to the first Al wirings, and via holes  45  that correspond to the first via holes. Al wirings  63   a  to  63   d  are connected to local wirings  53   a  to  53   d  through via holes  45 , respectively. 
         [0110]    The layout shown in  FIG. 10B  will be explained as compared with the layout shown in  FIG. 9B . The layout of Al wirings  62   a  to  62   d  is the same as that according to the first example explained with reference to  FIG. 9B . In this example, Al wirings  63   a  to  63   d  are provided at the position where Al wirings  61   a  and  61   b  are provided as shown in  FIG. 9B . In this example, wiring is not provided at the position where Al wirings  61   c  and  61   d  are provided as shown in  FIG. 9B . Since space for one more wiring is added on the first wiring layer as compared to the layout shown in  FIG. 9B  according to this example, space for three wirings indicated by dashed lines in  FIG. 10B  can be obtained. In the layout shown in  FIG. 10B , space for two wirings is obtained on one end of the MWD in the X-axis positive direction and space for one wiring is obtained on the other end in the X-axis negative direction. 
         [0111]      FIG. 10C  is a plan view showing the state after the second via holes and the second Al wirings are formed.  FIG. 10C  shows via holes  47  that correspond to the second via holes, and Al wirings  71   a  to  71   d  that correspond to the second Al wirings. 
         [0112]    In this example, Al wirings  63   a  to  63   d  are connected to Al wirings  71   a  to  71   d  through via holes  47 , respectively. Compared to the layout shown in  FIG. 9C , the positions of via holes  47  and the order of Al wirings  71   a  to  71   d  are different in the layout shown in  FIG. 10C . As already explained above in the first embodiment, this is because the first Al wirings and the second Al wirings are connected corresponding to the positions of via holes  47 . 
         [0113]    By providing space for one wiring on one end of the MWD and space for two wirings on the other end in the layout of the first wiring layer, space for three wiring can be obtained between adjacent MWDs. Incidentally, a space for four first Al wirings can be locally obtained by symmetrically arranging wirings next to the layout shown in  FIG. 10B . Such a structure will be explained in detail with reference to  FIG. 10B . Space for the four first Al wirings (two wirings ×2) can be obtained by providing a layout that is line-symmetric to the layout shown in  FIG. 10B  about the right end side as a symmetrical axis at the right side of the layout shown in  FIG. 10B . 
       Second Embodiment  
       [0114]    One example of the structure for drawing the second Al wiring that is not used in the MWD to the outside of the MWD region using the semiconductor device according to the present invention is shown in a second embodiment. The semiconductor device according to the first embodiment explained with reference to  FIG. 5A  to  FIG. 8  is used in this embodiment, but may be the semiconductor device according to the first or second example. 
         [0115]      FIGS. 11A and 11  B are plan views showing the layout of part of the MWD in the semiconductor device according to the second embodiment.  FIG. 11A  shows the layout corresponding to the layout shown in  FIG. 6B , and  FIG. 11B  shows the layout corresponding to the layout shown in  FIG. 6C . The detailed explanation of the same structure as that of the semiconductor device according to the first embodiment is omitted, and only features different from the semiconductor device according to the first embodiment will be explained below. 
         [0116]    Compared to  FIG. 6B , Al wirings  65  and  66  are added in  FIG. 11A . Al wirings  65  and  66  correspond to the first Al wirings. Al wiring  65  is not connected to the circuit of MWD  14 , and is connected to SWD  12  shown in  FIG. 1 . Al wiring  66  is not connected to the circuit of MWD  14 , and is connected to data control circuit  15  shown in  FIG. 2 . 
         [0117]    Compared to  FIG. 6C , Al wirings  75  and  76  are added in  FIG. 11B . Al wirings  75  and  76  correspond to the second Al wirings. Al wirings  75  and  76  are not used in the circuit of MWD  14 . Al wiring  75  is connected to Al wiring  65  shown in  FIG. 11A  through via hole  47 , and Al wiring  76  is connected to Al wiring  66  shown in  FIG. 11A  through via hole  47 . 
         [0118]    In the second embodiment, Al wiring  75  is connected to SWD  12  through via hole  47  and Al wiring  65 . Al wiring  65  serves as draw wiring for connecting Al wiring  75  which is not used in MWD  14  to SWD  12 . Al wiring  76  is connected to data control circuit  15  through via hole  47  and Al wiring  66 . Al wiring  66  serves as draw wiring for connecting Al wiring  76  which is not used in MWD  14  to data control circuit  15 . 
         [0119]    The layout method is not limited to that shown in  FIGS. 11A and 11B . The draw wiring for connecting SWD  12  and data control circuit  15  may be provided in the space of MWD  14 , and the second Al wiring of SWD  12  and the second Al wiring of data control circuit  15  may be connected by the second via hole and the draw wiring. 
         [0120]    By positioning the draw wiring in the space of the first wiring layer in the semiconductor device according to the first embodiment, the second Al wiring which is not used in the MWD can be drawn out to the circuit outside the MWD region as explained in the second embodiment. To connect the second Al wirings in two areas sandwiching the MWD region, the draw wiring is provided in the space of the first wiring layer. Accordingly, the second Al wirings in the two areas can be connected by the draw wiring. 
         [0121]    In the above-described embodiments and examples, the direction where the second Al wirings extend is defined as the X-axis and the direction where the first Al wirings extend is defined as the Y-axis, and the direction where the first Al wirings extend orthogonally intersects the direction where the second Al wirings extend. However, the direction where the first Al wirings extend does not need to be orthogonal to the direction where the second Al wirings extend. 
         [0122]    Since the second local wiring for connecting the first wirings to one of the transistors is provided between the first local wiring layer and the first wiring layer in the semiconductor device as described above, a part of the wiring pattern formed on the first wiring layer can be omitted. 
         [0123]    According to the wiring layout method as described above, the plurality of local wirings connected to the plurality of transistors are arranged in parallel so that the longitudinal direction of their patterns corresponds to the second direction. The plurality of first wirings connected to the plurality of second wirings corresponding to the plurality of local wirings have the same length in the second direction and are disposed at the same position in the second direction so as to be connected to the local wirings corresponding to the first wirings. Thus, space can be obtained in the second direction on the layer where the first wirings are provided. 
         [0124]    In all of the above-described embodiments and examples, space can be provided on the wiring provided by repeating a line-and-space pattern. Thus, the space occupied by the wiring can be reduced and the wiring drawn in other regions can be positioned. Consequently, the entire circuit of the semiconductor device can be downsized. 
         [0125]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.