Abstract:
In an apparatus including a shift register adapted to pass a start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals, a data register adapted to latch sequential data signals of the large amplitude level in synchronization with the latch signals, and a data latch circuit adapted to latch all the sequential data signals latched in the data register in synchronization with a strobe signal, a receiver converts differential clock signals of a small amplitude level into the clock signal of the large amplitude level from a timing of generation of the strobe signal to a timing of completion of latching all the sequential data signals in the data register, and transmits the clock signal of the large amplitude level to the shift register, and also, converts differential data signals of the small amplitude level into the sequential data signals from a timing of generation of the start signal to the timing of completion of latching all the sequential data signals in the data register and transmits the sequential data signals to the data register.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an apparatus for inputting a clock signal and data signals of a small amplitude level such as a data line driver of a liquid crystal display (LCD) apparatus. 
     2. Description of the Related Art 
     Generally, an LCD apparatus is constructed by an LCD panel having data lines (or signal lines), scan lines (or gate lines) and liquid crystal cells each located at one intersection between the data lines and the scan lines, a plurality of data line drivers provided at a horizontal edge of the LCD panel and connected by a cascade connection to each other for driving the data lines, and a plurality of scan line drivers provided at a vertical edge of the LCD panel and connected by a cascade connection to each other to drive the scan lines. 
     In an extended graphics array (XGA) formed by 1024×3×768 dots, eight data line drivers each for driving 384 (=128×3) data lines are provided. In this case, use is made of a low speed CMOS interface or a low speed large amplitude interface between modules of the drivers and their controller using a clock frequency of about 60 MHz. 
     On the other hand, in a super extended graphics array (SXGA) formed by 1280×3×1024 dots, ten data line drivers each for driving 384 (=128×3) data lines are provided. Also, in an ultra extended graphics array (UXGA) formed by 1600×3×1200 dots, sixteen data line drivers each for driving 300 (=100×3) data lines are provided. In both of these cases, although use is made of a high speed CMOS interface, such a high speed CMOS interface needs to adopt a parallel transmission system in order to avoid electro magnetic interference (EMI) noise, which, however, increases the number of connections. Therefore, use is now made of a high speed small amplitude interface between modules of the drivers and their controller using a clock frequency of higher than 60 MHz. 
     In the SXGA or UXGA using the above-mentioned high speed small amplitude interface, a receiver formed by a clock signal receiver (differential amplifier) and data signal receivers (differential amplifiers) are required. Also, in order to decrease the power consumption, the clock signal receiver and the data signal receivers are both activated only from a timing of generation of a start signal to a timing of completion of latching all data signals (see; JP-11-249626). 
     In the above-described prior art, however, since the restoration of the data signal receivers from a deactivation state to an activation state requires a certain time, the clock signal receiver needs to be activated sufficiently before the activation of the data signal receivers. For simply realizing this, the clock receiver was always activated. This increases the power consumption. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide an apparatus for inputting a clock signal and data signals of a small amplitude level without increasing the power consumption. 
     According to the present invention, in an apparatus including a shift register adapted to pass a start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals, a data register adapted to latch sequential data signals of the large amplitude level in synchronization with the latch signals, and a data latch circuit adapted to latch all the sequential data signals latched in the data register in synchronization with a strobe signal, a receiver converts differential clock signals of a small amplitude level into the clock signal of the large amplitude level from a timing of generation of the strobe signal to a timing of completion of latching all the sequential data signals in the data register, and transmits the clock signal of the large amplitude level to the shift register, and also, converts differential data signals of the small amplitude level into the sequential data signals from a timing of generation of the start signal to the timing of completion of latching all the sequential data signals in the data register and transmits the sequential data signals to the data register. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be more clearly understood from the description set forth below, with reference to the accompanying drawings, wherein, 
         FIG. 1  is a block circuit diagram illustrating a first embodiment of the LCD apparatus according to the present invention; 
         FIG. 2  is a detailed block circuit diagram of the data line driver of  FIG. 1 ; 
         FIG. 3  is a detailed block circuit diagram of the receiver of  FIG. 2 ; 
         FIGS. 4A and 4B  are timing diagrams for explaining the operation of one of the differential amplifiers of  FIG. 3 ; 
         FIG. 5  is a circuit diagram of the bias voltage generating circuit of  FIG. 3 ; and 
         FIG. 6  is a timing diagram for explaining the operation of the LCD apparatus of  FIGS. 1 ,  2  and  3 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In  FIG. 1 , which illustrates an embodiment of the LCD apparatus according to the present invention, reference numeral  1  designates an LCD panel having 1280×1024 pixels each formed by three color dots, i.e., R (red), G (green) and B (blue). Therefore, the LCD panel  1  includes 3932160 dots located at 3840 (=1028×3) data lines (or signal lines) DL and 1024 scan lines (or gate lines) SL. One dot is formed by one thin film transistor Q and one liquid crystal cell C. For example, if one dot is represented by 64 gradation voltages, one pixel is represented by 262144 (=64×64×64) colors, This LCD panel is called an SXGA. 
     In order to drive the 3840 data lines DL, ten data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10  each for driving 384 data lines are provided along a horizontal edge of the LCD panel  1 . On the other hand, in order to drive the 1024 scan lines SL, four gate line drivers  3 - 1 ,  3 - 2 ,  3 - 3  and  3 - 4  each for driving 256 gate lines are provided along a vertical edge of the LCD panel  1 . 
     A controller  4  receives color signals R, G and B, a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC from a personal computer or the line using a low voltage differential signaling (LVDS) interface, and generates a horizontal start signal HST, differential horizontal clock signals HCKN/HCKP, video signals DN/DP, and a strobe signal STB for the data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10 , a vertical start signal VST and a vertical clock signal VCK for the gate line drivers  3 - 1 ,  3 - 2 ,  3 - 3  and  3 - 4 . In this case, the horizontal start signal HST, the strobe signal STB, the vertical start signal VST and the vertical clock signal VCK are of a CMOS level, while the differential horizontal clock signals HCKN/HCKP and the differential data signals DN/DP are of a small amplitude level. 
     The small amplitude differential signaling is known by reduced swing differential signaling (registered trademark “RSDS” of National Semiconductor Corporation), min-low voltage differential Signaling (trademark “min-LVDS” of Texas Instrument Corporation) or current mode advanced differential signaling (trademark “CIADS” of NEC Corporation). 
     In  FIG. 1 , the data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10  are arranged by a cascade connection method to pass the horizontal start signal HST therethrough in synchronization with the differential horizontal clock signals HCKN/HCKP. In this case, if a horizontal start signal output from the data line driver  2 - 1  is denoted by HST 1 , the horizontal start signal HST 1  is supplied to the data line driver  2 - 2 . Also, if a horizontal start signal output from the data line driver  2 - 2  is denoted by HST 2 , the horizontal start signal HST 2  is supplied to the data line driver  2 - 3 . Further, if a horizontal start signal output from the data line driver  2 - 9  is denoted by HST 9 , the horizontal start signal HST 9  is supplied to the data line driver  2 - 10 . 
     Also, in  FIG. 1 , the scan line drivers  3 - 1 ,  3 - 2 ,  3 - 3  and  3 - 4  are arranged by a cascade connection method to pass the vertical start signal VST therethrough in synchronization with the vertical clock signals VCK. In this case, if a vertical start signal output from the scan line driver  3 - 1  is denoted by VST 1 , the vertical start signal VST 1  is supplied to the scan line driver  3 - 2 . Also, if a vertical start signal output from the data line driver  3 - 2  is denoted by VST 2 , the vertical start signal VST 2  is supplied to the scan line driver  3 - 3 . Further, if a vertical start signal output from the scan line driver  3 - 3  is denoted by VST 3 , the vertical start signal VST 3  is supplied to the scan line driver  3 - 4 . 
     The operation of the LCD apparatus of  FIG. 1  will now be briefly explained. A vertical start signal VST is shifted within the shift registers of each of the scan line drivers  3 - 1 ,  3 - 2 ,  3 - 3  and  3 - 4 , one scan line is selected to turn ON all the thin film transistors Q connected thereto. On the other hand, a horizontal start signal HST is shifted within the shift registers of each of the data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10 , video data of one scan line is latched. Then, the gradation voltages corresponding to the video data are applied by the strobe signal STB via the thin film transistors at the scan line to the liquid crystal cells C thereof. After that, the gradation voltages applied to the liquid crystal cells C are maintained until the next selecting operation is performed thereon. 
     In  FIG. 2 , which is a detailed block circuit diagram of the data line driver  2 - 1  of  FIG. 1 , the data line driver  2 - 1  is constructed by a horizontal shift register  201 , a data register,  202 , a data latch circuit  203 , a level shifter  204 , a digital/analog (D/A) converter  205 , and an output buffer  206  formed by voltage followers. Also, the data line driver  2 - 1  is constructed by a receiver  207  for receiving the differential horizontal clock signals HCKN/HCKP and the differential video signals DN/DP as well as the horizontal start signal HST, the strobe signal STB and a data end signal DE to convert the differential horizontal clock signals HCKN/HCKP and the differential video signal DN/DP of a small amplitude level into a horizontal clock signal HCO and video signals D of a CMOS level. 
     The horizontal shift register  201  shifts the horizontal start signal EST in synchronization with the horizontal clock signal HCK, to sequentially generate latch signals LA 1 , LA 2 , . . . , LA 128 . The horizontal shift register  201  also generates the horizontal start signal HST 1  for the next stage data line driver  2 - 2 , and the data end signal DE which is delayed for a predetermined time period as compared with the horizontal start signal HST 1 . 
     The data register  202  latches the video signals D(18 bits) formed by red data ( 9 )(6 bits), green data (G)(6 bits) and blue data (B)(6 bits) in synchronization with the latch signals LA 1 , LA 2 , . . . , LA 128 , to generate video signals D 1 , D 2 , . . . , D 384 , respectively. 
     The data latch circuit  203  latches the video signals D 1 , D 2 , . . . , D 384  of the data register  202  in synchronization with the strobe signal STB. 
     The level shifter  204  shifts the video signals D 1 , D 2 , . . . , D 384  by a level shift amount ΔV applied to the liquid crystal of the LCD panel  1  to generate video signals D 1 ′, D 2 ′, . . . , D 384 ′. That is, the level shift amount ΔV is a preset voltage to initiate the change of the transmittance of the liquid crystal. 
     The D/A converter  205  performs D/A conversions upon the shifted video signals D 1 ′, D 2 ′, . . . , D 384 ′, using the multi-gradation voltages such as 64 gradation voltages to generate analog voltages which are applied via the output buffer  206  to data lines DL 1 , DL 2 , . . . , DL 384 , respectively. 
     The receiver  207  of  FIG. 2  will be explained next with reference to  FIG. 3 . 
     In  FIG. 3 , a clock signal receiver (differential amplifier)  301  amplifies the difference in voltage between the differential clock signals HCKN and HCKP of a small amplitude level as shown in  FIG. 4A  to generate the clock signal HCK of a CMOS level as shown in  FIG. 4B . On the other hand, a data signal receiver (differential amplifier)  302 - 00  ( 302 - 01  and  302 - 02 ) amplifies the difference in voltage between differential red video signals D 00 N and D 00 P (D 01 N and D 01 P, D 02 N and D 02 P) of a small amplitude level to generate red video signals D 00  and D 01  (D 02  and D 03 , D 04  and D 05 ) of a CMOS level. Also, a data signal receiver (differential amplifier)  302 - 10  ( 302 - 11  and  302 - 12 ) amplifies the difference in voltage between differential green video signals D 10 N and D 10 P (D 11 N and D 11 P, D 12 N and D 12 P) of a small amplitude level to generate green video signals D 10  and D 11  (D 12  and D 13 , D 14  and D 15 ). Further, a data signal receiver (differential amplifier)  302 - 20  ( 302 - 21  and  302 - 22 ) amplifies the difference in voltage between differential blue video signal D 20 N and D 20 P (D 21 N and D 21 P, D 22 N and D 22 P) of a small amplitude level to generate blue video signals D 20  and D 21  (D 22  and D 23 , D 24  and D 25 ). 
     To the differential amplifier  301  is applied a bias voltage V b1  from a bias voltage generating circuit  303  via a switch  304  which is controlled by an RS flip-flop  305 . On the other hand, to the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  is applied a bias voltage V b2  from the bias voltage generating circuit  303  via a switch  306  which is controlled by an RS flip-flop  307 . 
     The RS flip-flop  305  is set by the strobe signal STB and reset by the data end signal DE. Therefore, a control signal C 1  generated from the RS flip-flop  305  is high from a rising timing of the strobe signal STB to a rising timing of the data end signal DE, to turn ON the switch  304  so that the differential amplifier  301  is activated. 
     On the other hand, the RS flip-flop  307  is set by the horizontal start signal HST and reset by the data end signal DE. Therefore, a control signal C 2  generated from the RS flip-flop  307  is high from a rising timing of the horizontal start signal HST to a rising timing of the data end signal DE, to turn ON the switch  306  so that the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  are activated. 
     In  FIG. 5 , which is a detailed circuit diagram of the bias voltage generating circuit  303  of  FIG. 3 , the bias voltage generating circuit  303  is constructed by a bias current source  501 , a bias voltage generating section  502  for the bias voltage V b1  and a bias voltage generating section  503  for the bias voltage V b2 . 
     The bias current source  501  is formed by a diode-connected P-channel MOS transistor Q 1  and a diode-connected N-channel HOS transistor Q 2  connected in series between a power supply terminal V cc  and a ground terminal GND. 
     The bias voltage generating section  502  is formed by a diode-connected P-channel MOS transistor Q 3  and an N-channel Mos transistor Q 4  connected in series between the power supply terminal V cc  and the ground terminal GND. In this case, the gate of the N-channel MOS transistor Q 4  is connected to the gate of the N-channel MOS transistor Q 2 , so that the N-channel transistors Q 2  and Q 4  form a current mirror circuit where a current flowing through the P-channel MOS transistor Q 1  is defined by an input current and a current flowing through the N-channel MOS transistor Q 4  is defined by an output current. 
     The bias voltage generating section  503  is formed by a diode-connected P-channel MOS transistor Q 5  and an N-channel MOS transistor Q 6  connected in series between the power supply terminal V cc  and the ground terminal GND. In this case, the gate of the N-channel MOS transistor Q 6  is connected to the gate of the N-channel MOS transistor Q 2 , so that the N-channel transistors Q 2  and Q 6  form a current mirror circuit where a current flowing through the P-channel MOS transistor Q 1  is defined by an input current and a current flowing through the N-channel MOS transistor Q 6  is defined by an output current. 
     The operation of the LCD apparatus of  FIGS. 1 ,  2  and  3  will be explained next with reference to  FIG. 6  where the differential data signals DN/DP are effective for the data line driver  2 - 1  during a time period T 1 , for the data line driver  2 - 2  during a time period T 2 , . . . , and for the data line driver  2 - 10  during a time period T 10 . 
     First, at time t 1 , when a strobe signal STB is generated from the controller  4 , the RS flip-flop  305  of each of the data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10  is set, so that the control signal C 1  of each of the data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10  is made high. As a result, the differential amplifier  301  of each of the data line drivers  2 - 1 ,  2 - 2 , . . . ,  2 - 10  is activated. 
     Next, at time t 2 , when a horizontal start signal HST is generated from the controller  4 , the control signal C 2  of the data line driver  2 - 1  is made high. As a result, the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  of the data line driver  2 - 1  are activated. 
     Next, at time t 3 , the horizontal shift register  201  of the data line driver  2 - 1  generates a horizontal start signal HST 1  which is received by the data line driver  2 - 2 . Therefore, the control signal C 2  of the data line driver  2 - 2  is made high. As a result, the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  of the data line driver  2 - 2  are activated. 
     Next, at time t 4 , when a data end signal DE is generated from the horizontal shift register  201  of the data line driver  2 - 1 , the RS flip-flops  305  and  307  of the data line driver  2 - 1  are reset, so that the control signals C 1  and C 2  of the data line driver  2 - 1  are both made low. As a result, the differential amplifiers  301 ,  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  of the data line driver  2 - 1  are all deactivated. 
     Thus, in the data line driver  2 - 1 , the time period of activation of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  defined by C 2 =high covers the effective time period T 1  of the differential data signals DN/DP. Also, the time period of activation of the differential amplifier  301  defined by C 1 =high covers the time period of activation of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302  - 22 . Particularly, the start timing of activation of the differential amplifier  301  is sufficiently advanced as compared with that of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22 . 
     Next, at time t 5 , when a data end signal DE is generated from the horizontal shift register  201  of the data line driver  2 - 2 , the RS flip-flops  305  and  307  of the data line driver  2 - 2  are reset, so that the control signals C 1  and C 2  of the data line driver  2 - 2  are both made low. As a result, the differential amplifiers  301 ,  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  of the data line driver  2 - 2  are all deactivated. 
     Thus, in the data line driver  2 - 2 , the time period of activation of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  defined by C 2 =high covers the effective time period T 2  of the differential data signals DN/DP. Also, the time period of activation of the differential amplifier  301  defined by C 1 =high covers the time period of activation of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22 . Particularly, the start timing of activation of the differential amplifier  301  is sufficiently advanced as compared-with that of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22 . 
     Similarly, at time t 6 , the horizontal shift register  201  of the data line driver  2 - 9  generates a horizontal start signal HST 9  which is received by the data line driver  2 - 10 . Therefore, the control signal C 2  of the data line driver  2 - 10  is made high. As a result, the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  of the data line driver  2 - 10  are activated. 
     Next, at time t 7 , when a data end signal DE is generated from the horizontal shift register  201  of the data line driver  2 - 10 , the RS flip-flops  305  and  307  of the data line driver  2 - 10  are reset, so that the control signals C 1  and C 2  of the data line driver  2 - 10  are both made low. As a result, the differential amplifiers  301 ,  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  of the data line driver  2 - 10  are all deactivated. 
     Thus, in the data line driver  2 - 10 , the time period of activation of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22  defined by C 2 =high covers the effective time period T 10  of the differential data signals DN/DP. Also, the time period of activation of the differential amplifier  301  defined by C 1 =high covers the time period of activation of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22 . Particularly, the start timing of activation of the differential amplifier  301  is sufficiently advanced as compared with that of the differential amplifiers  302 - 00 ,  302 - 01 ,  302 - 02 ,  302 - 10 ,  302 - 11 ,  302 - 12 ,  302 - 20 ,  302 - 21  and  302 - 22 . 
     Note that the present invention can be applied to other apparatuses than LCD apparatuses. 
     As explained hereinabove, the restoration from deactivation to activation of the differential amplifiers for the differential data signals are carried out sufficiently before the restoration from deactivation to activation of the differential amplifier for the differential clock signals.