Abstract:
A method of amplifying an input signal comprises providing a semiconductor die, forming an LNA input stage having a transconductance, on the semiconductor die, and desensitizing the LNA input stage transconductance to variations in process and environmental conditions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a divisional of U.S. patent application Ser. No. 10/242,879 filed on Sep. 11, 2002 now U.S. Pat. No. 6,977,553. The disclosure of the above application is incorporated herein by reference in its entirety. 

   TECHNICAL FIELD 
   An aspect of the invention relates to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) amplifiers. 
   BACKGROUND 
   There is a growing demand for mobility in today&#39;s world. The rapid progress in the wireless industry makes the ubiquitous connection possible. Radio Frequency (RF) transceivers are important components for wireless devices. The majority of the RF ICs used in the wireless communication were implemented using either GaAs or silicon bipolar technologies. Not until recently, when the continuous scaling of CMOS technology brought the cutoff frequency (f T ) of MOS transistors up to multi-tens of GHz, were such circuits built in CMOS technology possible. The advantage of using Complementary Metal-Oxide-Semiconductor (CMOS) RF is that it can be integrated with digital functions easily. As a result, it is possible to incorporate the whole system on one single chip which yields low cost, small form factor wireless devices. A Low Noise Amplifier (LNA) is an important building block in the wireless transceiver. For LNAs, the gain linearity applied to a signal is an important operating characteristic, especially when the incoming signal is large. Under that condition, amplification by the LNA actually could be greater or smaller than one, and the noise contribution from the LNA may be negligible compared to the input signal. In fact, the linearity of the LNA becomes the most important figure of merit. Gain linearity is generally characterized as a 1 dB compression point or third order Input Intercept Point (IIP3). The gain linearity is typically related to the transconductance of a MOSFET in an input stage of the amplifier. For example, the transconductance of a MOSFET operating in the saturation region is constant only when the input signal is small. When the input signal is large, the transconductance may vary as a function of the input signal, leading to nonlinear amplification of the signal. Source degeneration may be employed at lower frequencies to increase the linearity of the input stage. However, at higher frequencies source degeneration may not be effective due to the large parasitic capacitance of the device. Also, source degeneration may increase power consumption due to the relative low gm/Id for the MOSFET in comparison with a bipolar device. In addition, Gain control is also very important in practical applications since the gain of the LNA could vary with process and temperature if not properly controlled. 
   SUMMARY 
   A method of amplifying an input signal comprises providing a semiconductor die, forming an LNA input stage having a transconductance, on the semiconductor die, and desensitizing the LNA input stage transconductance to variations in process and environmental conditions. 
   The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 

   
     DESCRIPTION OF DRAWINGS 
       FIG. 1  is a block diagram of an aspect of a transceiver. 
       FIG. 2A  is a schematic diagram of an aspect of an LNA. 
       FIG. 2B  is a schematic diagram of an aspect of an LNA. 
       FIG. 2C  is a schematic diagram of an aspect of an LNA. 
       FIG. 2D  is a schematic diagram of an aspect of an amplifier. 
       FIG. 3  is a schematic diagram of an aspect of a bias circuit for a linear input stage. 
       FIG. 4  is a schematic diagram of an aspect of an amplifier. 
       FIG. 5  is a flow diagram of an aspect of an operation for generating a linear input stage. 
       FIG. 6  is a flow diagram of an aspect of an operation for biasing a linear input stage. 
   

   Like reference symbols in the various drawings indicate like elements. 
   DETAILED DESCRIPTION 
     FIG. 1  shows an aspect of a wireless transceiver  10  for communicating information. The wireless transceiver  10  may include a Low Noise Amplifier (LNA)  12  for amplifying an input signal. An input signal  14  to the LNA  12  may be amplified by a linear input stage  18  constructed in accordance with the principles of the invention. A bias circuit  16  may supply bias signals to the linear input stage  18  in accordance with the principles of the invention. The LNA  12  preferably includes both the bias circuit  16  and the linear input stage  18 . However, the LNA  12  may include the bias circuit  16  combined with a conventional linear input stage, or the linear input stage  18  combined with a conventional bias circuit. An output stage  20  may provide further amplification of the input signal. 
   A mixer  22  may combine the amplified input signal with a Radio Frequency (RF) LO signal  24 . A filter  26  and amplifier  23  may filter and amplify the combined signal, and mix the generated signal with an Intermediate Frequency (IF) LO signal. An analog-to-digital converter (ADC)  28  may convert the mixed signal to a digital signal for further processing. 
   A digital-to-analog converter  27  may convert a digital signal to an analog signal for transmission by a transmitter  25 . 
     FIG. 2A  shows an aspect of an LNA input stage  200  for amplifying an input signal, v in . The LNA input stage  200  may be constructed using any CMOS process including NMOS and PMOS. The input signal, v in , to the LNA input stage  200  modulates the resistance of a first device  202  that is connected to a second device  204  having a low input impedance. Due to the low input impedance of the second device  204 , the voltage v x  at the junction of the first and second devices  202  and  204  may remain relatively constant. The input stage  200  is configured so that changes in the input signal cause linearly proportional changes in conductance of the first device  202 . In the case where v x  is relatively constant and the conductance of the first device  202  changes in linear proportion to changes in the input signal, i out  is about linearly proportional to v in . 
     FIG. 2B  shows an aspect of an NMOS implementation  210  of the LNA input stage  200 . The resistance of a first device  212  is modulated in response to an input signal v in . An NMOS transistor  214  in combination with an amplifier  216  provides a low impedance at the junction of the NMOS transistor  214  and the first device  212 . 
     FIG. 2C  shows an aspect of another NMOS implementation  220  of the LNA input stage  210 . Here, the resistance of a first NMOS transistor  222  is modulated in response to an input signal v in . The first NMOS transistor is biased into the triode region. A second NMOS transistor  224  in combination with an amplifier  226  provide a low impedance at the junction of the first and second NMOS transistors  222  and  224 . 
     FIG. 2D  shows an aspect of an amplifier  30  for amplifying an input signal in accordance with the principles of the LNA input stage  200 . Here, a linear input stage  32  may include an upper MOSFET, MB,  34  and a lower MOSFET, MA,  36  connected in a cascode configuration. The input impedance of the upper MOSFET  34  at the junction of the upper and lower MOSFETs  34  and  36 , may be made low relative to the lower MOSFET  36  by controlling the relative sizes of the upper and lower MOSFETs  34  and  36 . The linear input stage  32  is preferably constructed as an integrated circuit using Complementary Metal Oxide Semiconductor (CMOS) technology, but other circuit technologies may also be used including discrete MOSFETs. Both NMOS and PMOS devices may be used. An input signal is AC coupled through a capacitor  40  to the gate of the lower MOSFET  36 . A bias circuit  38  biases the upper MOSFET  34  into the saturation region and the lower MOSFET  36  into the triode region. Here, the lower MOSFET  36  acts as a variable resistor changing conductance in linear proportion to changes in the input signal. The impedance of the junction of MOSFETs  34  and  36  may be made lower by selecting the transconductance, g m , of the upper MOSFET  34  to be larger than both g ds  and g m  of the lower MOSFET  36  so that Vds of the lower MOSFET  36  remains relatively constant over changes in the input signal. For example, an input switch ratio defined as the ratio of the size of the upper MOSFET  34  to the size of the lower MOSFET  36  may be selected to be at least four, so that g m  of the upper MOSFET  34  is greater than both the g ds  and g m  of the lower MOSFET. One aspect of the invention recognizes that if the Vds of the lower MOSFET  36  is maintained relatively constant and the lower MOSFET  36  is biased into the triode region, then the output current of the lower MOSFET  36  will be linearly proportional to the input signal. The following derivation illustrates that for a device in deep triode region: 
   
     
       
         
           
             
               I 
               d 
             
             = 
             
               μ 
               ⁢ 
               
                   
               
               ⁢ 
               
                 C 
                 ⁡ 
                 
                   [ 
                   
                     
                       
                         ( 
                         
                           
                             V 
                             gs 
                           
                           - 
                           
                             V 
                             th 
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         V 
                         ds 
                       
                     
                     - 
                     
                       
                         1 
                         2 
                       
                       ⁢ 
                       
                         V 
                         ds 
                         2 
                       
                     
                   
                   ] 
                 
               
             
           
           , 
         
       
     
   
               g   ds     =         ∂     I   d         ∂     V   ds         =       μ   ⁢           ⁢   C   ⁢       W   L     ⁡     [       (       V   gs     -     V   ds       )     -     V   ds       ]         ≈     β   ⁡     (       V   gs     -     V   t       )             ,         
where
 
             β   =     μC   ⁢     W   L         ,         
the output AC current is as follows:
   i   out =ν ds   g   ds =β( V   gs   −V   t )ν ds    
Which shows that i out  may be a linear function of the input signal, leading to an increase in linearity. The amount of linearity achieved may be controlled by adjusting the ratio of the upper MOSFET size to the lower MOSFET size. A load resistor  39  may be connected to the upper MOSFET  34 . Another way of looking at it is to view the lower MOSFET  36  as a normal MOSFET which has its own transconductance gm. The following derivation illustrates that the linearity of g m  may be dependent on Vds for a MOSFET operated in the triode region.
 
               I   d     =     μ   ⁢           ⁢     C   ⁡     [         (       V   gs     -     V   th       )     ⁢     V   ds       -       1   2     ⁢     V   ds   2         ]           ,         
thus the transconductance of the device is,
 
   
     
       
         
           
             g 
             m 
           
           = 
           
             
               μ 
               ⁢ 
               
                   
               
               ⁢ 
               C 
               ⁢ 
               
                 W 
                 L 
               
               ⁢ 
               
                 V 
                 ds 
               
             
             = 
             
               β 
               ⁢ 
               
                   
               
               ⁢ 
               
                 V 
                 ds 
               
             
           
         
       
     
   
   The sensitivity of gm to variations in the input signal may be reduced by reducing the sensitivity of Vds to variations in the input signal, thereby increasing the linearity of the amplification. 
   However, since β is function of process and temperature variation, the gain of the amplifier may vary too. One way to reduce that sensitivity is to bias the input stage so that βVds is less sensitive to environmental variations. 
     FIG. 3  shows an aspect of a bias circuit  50  for a linear input stage. The bias circuit  50  may control the variation of the linear input stage transconductance to reduce sensitivity to process, environmental effects such as temperature, and power. The bias circuit  50  includes an upper MOSFET, M 2 ,  52  connected to a lower MOSFET M 1 ,  54 . The upper MOSFET  52  is operated in the saturation region and the lower MOSFET is operated in the triode region. A third MOSFET, M 3 ,  56  operates to bias the lower MOSFET  52  into the triode region. To set the bias to the lower MOSFET  52 , the magnitude of the current, I 3 , flowing through M 3   56  may be controlled as well as controlling the physical characteristics of M 3   56  such as size. For example, if I 3  is selected to equal I 1  (the current flowing through M 1 ), then a bias switch ratio defined as the ratio of the size of M 1   54  to the size of M 3   56  should be selected to be at least greater than one, and preferably greater than 1.4. A resistor  58  connected from the gate of M 1   56  decouples the input signal from the bias circuit  50 . 
     FIG. 4  shows an aspect of an amplifier  59  including a bias circuit  60  connected to a linear input stage  82 . The bias circuit  60  is similar in function to bias circuit  50  with corresponding elements in the range of  62  to  68 . The linear input stage  82  is similar in function to linear input stage  32  with corresponding elements in the range of  84  to  86 . The amplifier  59  advantageously combines the benefits of both the linear input stage  82  and the bias circuit  60 . An input signal may be AC coupled through a capacitor  60  to the gate of the lower MOSFET  86 . A load resistor  88  may be connected to the upper MOSFET  84  to obtain an output from the drain of the upper MOSFET  84 . 
   The following derivation may be used to select the devices for the linear input stage  82  and the bias circuit  60  of a preferred embodiment, and demonstrate how the gm of the input stage is controlled to be less sensitive to environmental variations. The linear input stage transconductance, g mA  may be as follows: 
   g mA =βV ds,A =β(V b −V dsat,B −V th,B ) where V b  is the voltage from the gate of MB to ground. 
   For discussion purpose, let&#39;s assume 
                 (     W   L     )     2     =       (     W   L     )     β       ,         (     W   L     )     I     =       (     W   L     )     A             
and I 1 =I 2 , then V dsa,2 =V dsat,B  and V th,2 =V th,B , the transconductance of MA becomes; g mA =β(V b −V dsat,2 −V th,2 )=βV ds,1 . I 1  is not limited to any specific ratio of I 2  as long as the ratio of (W/L) 1  to (W/L) A  and (W/L) 2  to (W/L) B  are properly scaled so that the current densities are about the same for those devices. The ratio of the size of M 2  to the size of M 1  should be approximately equal to the ratio of the size of MB to the size of MA.
 
   For the same reason, let&#39;s assume I 3 =I 1 , and 
                 (     W   L     )     1     =     X   ·       (     W   L     )     3         ,         
where X&gt;1.0 and preferably 1.4. Then M 1  is also in the triode region, and if M 1  in deep triode region, Vgs−Vth&gt;&gt;Vds/2, then I 1 ≈β(V gs,1 −V th,1 )V ds,1   
             g   mA     =       β   ⁢           ⁢     V     ds   ,   1         =       β   ⁢       I   1       β   ⁡     (       V     gs   ,   1       -     V     th   ,   1         )           =         I   3       (       V     gs   ,   1       -     V     th   ,   3         )       =       g     m   ,   3       /   2                 
If current I 3  is a constant gm bias current which is;
 
             Ids   =     A   β       ,         
where A can be chosen to only depend on an external resistor value and ratio of two transistors[1], then,
 
g mA =g m,3 /2=√{square root over (2*I 3 *β)}/2=√{square root over (A/2)} which is a constant.
 
   Here, I 3  does not have to equal I 1 , instead “X”, the ratio of the size of M 3  to the size of M 1 , can be set to a predetermined value and the ratio of I 3  to I 1  varied. Also, the ratios 
             (     W   L     )     1         
and
 
             (     W   L     )     3         
may be varied to bias M 1  into the triode region.
 
     FIG. 5  shows an aspect of an operation for generating a linear input stage. Starting at block  100 , a semiconductor die is provided. At block  102 , a first MOSFET having a predetermined size is formed. At block  104 , a second MOSFET having a size greater than the first MOSFET is formed. At block  106 , the second MOSFET is connected in cascode with the first MOSFET. At block  108 , the first MOSFET is biased into the triode region. At block  110 , the second MOSFET is biased into the saturation region. At block  112 , an input signal is applied to the gate of the first MOSFET causing a change in I d  of the MOSFETs that is approximately a linear function of the AC voltage applied to the first MOSFET gate. 
     FIG. 6  shows an aspect of an operation for biasing a linear input stage. Starting at blocks  120  and  122 , first and second MOS devices are provided. At block  124 , the ratio of the first MOS device size to the second MOS device is selected to be a predetermined value, Rb. At block  126 , the second MOS device is connected in cascode with the first MOS device. At block  128 , the first MOS device is biased into the triode region. At block  130 , the second MOS device is biased into the saturation region such as by connecting the gate and drain of the second MOS device together. At block  132 , a linear input stage having “A” and “B” MOS devices is provided. At block  134 , the ratio of the “A” MOS size to the “B” MOS size is selected to be about Rb. At block  136 , the first and second MOS devices are connected to the linear input stage. 
   A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.