Abstract:
A semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0181147, filed on Dec. 17, 2015, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present disclosure relates to a semiconductor device, and in particular, to high-speed semiconductor modules. 
         [0003]    In a data processing system (e.g., computer or communication system), a semiconductor module with multiple semiconductor packages is generally provided on a module board. A delay time of signals to be transmitted from or to the semiconductor package is dependent on, or proportional to, a distance from a connector of the module board, and thus, the semiconductor module may suffer from a reduced processing speed or signal distortion. To overcome these technical issues, various semiconductor module structures are being studied. 
       SUMMARY 
       [0004]    Some embodiments include a semiconductor module, comprising: a module substrate with an electric connection element; at least one semiconductor package provided on the module substrate, the at least one semiconductor package including a plurality of semiconductor chips; and a connection region electrically connecting the semiconductor package to the module substrate, wherein the connection region comprises: a first region electrically connected between data signal terminals of a first chip of the semiconductor chips of the semiconductor package and the module substrate; a second region electrically connected between data signal terminals of a second chip of the semiconductor chips of the semiconductor package and the module substrate; and a third region electrically connected between command/address signal terminals of both the first and second chips of the semiconductor package and the module substrate, wherein the first region is closer to the electric connection element of the module substrate, compared with the third region. 
         [0005]    Some embodiments include a semiconductor module, comprising: a module substrate; a plurality of semiconductor packages arranged in a first direction on the module substrate; an electric connection element extending on the module substrate in the first direction; wherein each of the semiconductor packages comprises: a package substrate having a top surface and a bottom surface opposite to each other; and a plurality of semiconductor chips provided on the top surface of the package substrate and arranged in a second direction crossing the first direction; wherein: the semiconductor chips are mounted in common on the top surface of the package substrate; the first and second directions are parallel to the top surface of the package substrate; and the second direction is a direction extending away from the electric connection element. 
         [0006]    Some embodiments include a semiconductor module, comprising a plurality of semiconductor packages provided on a module substrate with an electric connection element, wherein each of the semiconductor package comprises: a package substrate having a bottom surface and a top surface opposite to each other, the bottom surface facing the module substrate; a plurality of semiconductor chips mounted in common on the top surface of the package substrate such that their distances from the electric connection element of the module substrate are different from each other, when measured on the top surface of the package substrate; and a plurality of electric connection elements of the package substrate provided on the bottom surface of the package substrate to electrically connect the semiconductor chips to the module substrate, wherein the plurality of electric connection elements of the package substrate comprise: a plurality of first connection elements electrically connected to data signal terminals of the semiconductor chips; and a plurality of second connection elements electrically connected to command/address signal terminals of the semiconductor chips, wherein the package substrate comprises: a first connection region that is provided on the bottom surface of the package substrate and on which the first connection elements are arranged; and a second connection region that is provided on the bottom surface of the package substrate and on which the second connection elements are arranged, wherein the first connection region is closer to the electric connection element of the module substrate than the second connection region. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    Embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein. 
           [0008]      FIG. 1A  is a plan view illustrating a semiconductor module according to some embodiments. 
           [0009]      FIG. 1B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 1A . 
           [0010]      FIG. 1C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 1A . 
           [0011]      FIG. 1D  is a sectional view taken along line IA-IB of  FIG. 1C . 
           [0012]      FIG. 2A  is a bottom plan view illustrating a modified example of  FIG. 1C . 
           [0013]      FIG. 2B  is a sectional view taken along line IA′-IB′ of  FIG. 2A  illustrating a modified example of  FIG. 1D . 
           [0014]      FIG. 3A  is a plan view illustrating a semiconductor module according to some embodiments. 
           [0015]      FIG. 3B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 3A . 
           [0016]      FIG. 3C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 3A . 
           [0017]      FIG. 3D  is a sectional view taken along line IC-ID of  FIG. 3C . 
           [0018]      FIGS. 3E and 3F  are bottom plan views illustrating modified examples of  FIG. 3C . 
           [0019]      FIG. 4A  is a plan view illustrating a semiconductor module according to some embodiments. 
           [0020]      FIG. 4B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 4A . 
           [0021]      FIG. 4C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 4A . 
           [0022]      FIG. 4D  is a sectional view taken along line IE-IF of  FIG. 4C . 
           [0023]      FIG. 5A  is a plan view illustrating a semiconductor module according to some embodiments. 
           [0024]      FIG. 5B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 5A . 
           [0025]      FIG. 5C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 5A . 
           [0026]      FIG. 5D  is a sectional view taken along line IG-IH of  FIG. 5C . 
           [0027]      FIG. 5E  is a sectional view taken along line II-IJ of  FIG. 5C . 
       
    
    
     DETAILED DESCRIPTION 
       [0028]      FIG. 1A  is a plan view illustrating a semiconductor module according to some embodiments.  FIG. 1B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 1A .  FIG. 1C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 1A .  FIG. 1D  is a sectional view taken along line IA-IB of  FIG. 1C . 
         [0029]    Referring to  FIG. 1A , a semiconductor module  10  may include a module substrate  90  having two opposite surfaces (e.g., a top surface  90   a  and a bottom surface  90   b ), at least one semiconductor package  100  provided on the top surface  90   a  of the module substrate  90 , and a connector  95  provided on an edge region of the top surface  90   a  of the module substrate  90 . Arrows  151  and  152  may represent transmission or routing of data signals (e.g., DQ, DQS, DQSB) to be exchanged between the semiconductor package  100  and the connector  95 . As used herein, the data signals will be denoted by reference characters “DQ 1 ” and/or “DQ 2 ”. For example, the reference characters “DQ 1 ” may include data signals, such as DQ, DQS, and DQSB. The same may be true of the reference characters “DQ 2 ”. 
         [0030]    The semiconductor module  10  may include a memory module (e.g., a dynamic random access memory (DRAM), static random access memory (SRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), Resistive Random Access Memory (RRAM), flash memory, or electrically erasable programmable read-only memory (EEPROM) module). For example, the semiconductor module  10  may include multiple semiconductor packages  100 , and each of the semiconductor packages  100  may include two or more memory chips. The semiconductor module  10  may further include a buffer chip  190  provided on the top surface  90   a  of the module substrate  90 . The buffer chip  190  may be configured to provide signals (e.g., command signals (CMD), address signals (ADDR), and control signals (CTRL)), which are provided from an external device  80  (e.g., a memory controller), to the semiconductor package  100  in a buffered manner. The external device  80  may be configured to use such signals to control reading and writing data from and to the semiconductor package  100 . Arrow  195  may represent transmission or routing of non-data signals (e.g., CMD, ADDR, and CTRL) to be transmitted from the external device  80  or the buffer chip  190  to the semiconductor package  100 . For brevity, the non-data signals will be referred to as a ‘command/address signal C/A’. For example, the command/address signal C/A may include the command signals (CMD), the address signals (ADDR), and the control signals (CTRL) and so on. 
         [0031]    The module substrate  90  may have a rectangular shape; for example, a length of the module substrate  90  may be longer in a first direction X than in a second direction Y perpendicular to the first direction X. The semiconductor packages  100  may be spaced apart from each other in the first direction X. The buffer chip  190  may be provided at a center of the top surface  90   a  of the module substrate  90  or at a region adjacent to the center. The connector  95  may include multiple pads, which are provided on a lower edge region of the top surface  90   a  of the module substrate  90  and are arranged in the first direction X. 
         [0032]    A structure provided on the top surface  90   a  of the module substrate  90  may be substantially the same as or similar to that on the bottom surface  90   b  of the module substrate  90 . For example, the semiconductor module  10  may further include multiple semiconductor packages  100  provided on the bottom surface  90   b  of the module substrate  90 , and in some embodiments, the semiconductor module  10  may further include a buffer chip  190  provided on the bottom surface  90   b  of the module substrate  90 . 
         [0033]    Referring to  FIGS. 1B and 1D , the semiconductor package  100  may include a package substrate  101  (e.g., a printed circuit board) having two opposite surfaces (e.g., a top surface  101   a  and a bottom surface  101   b ), at least two chip stacks  110  and  120  provided on the top surface  101   a  of the package substrate  101 , and a mold layer  103  covering the chip stacks  110  and  120 . 
         [0034]    The first chip stack  110  may include a first lower semiconductor chip  111  and a first upper semiconductor chip  112  stacked on the top surface  101   a  of the package substrate  101 . A first adhesive layer  113  may be provided between the first lower semiconductor chip  111  and the package substrate  101  and between the first lower semiconductor chip  111  and the first upper semiconductor chip  112 . The first lower semiconductor chip  111  and the first upper semiconductor chip  112  may be electrically connected to each other and/or to the package substrate  101  through first bonding wires  114 . Each of the first lower semiconductor chip  111  and the first upper semiconductor chip  112  may include first chip pads  116 , to which the first bonding wires  114  are electrically connected. In some embodiments, at least one semiconductor chip may be further stacked on the first upper semiconductor chip  112 . 
         [0035]    The second chip stack  120  may have a same or similar structure as the first chip stack  110 . For example, the second chip stack  120  may include a second lower semiconductor chip  121 , a second upper semiconductor chip  122 , a second adhesive layer  123 , second bonding wires  124 , and second chip pads  126  similar to the corresponding structures of the first chip stack  110 . 
         [0036]    The semiconductor chips  111 ,  112 ,  121 , and  122  may have the same structure or may be of the same kind; for example, all of the semiconductor chips  111 ,  112 ,  121 , and  122  may be memory chips of the same kind. In some embodiments, at least one of the semiconductor chips  111 ,  112 ,  121 , and  122  may be configured to have a structure different from the others. Although only two chip stacks  110  and  120  have been used as examples, in other embodiments, more chip stacks may be similarly mounted on the package substrate  101 . 
         [0037]    According to this embodiment, as shown in  FIG. 1B , the first and second chip stacks  110  and  120  may be mounted together on the single package substrate  101 . The first and second chip stacks  110  and  120  may be arranged in the second direction Y on the single package substrate  101 . Accordingly, it is possible to reduce a size (e.g., a length H 1  in the second direction Y) of the semiconductor package  100 . Each of the first and second bonding wires  114  and  124  may extend in the first direction X. This may make it possible to reduce a space between the first and second chip stacks  110  and  120 , and thus, the size H 1  of the semiconductor package  100  can be further reduced. Since the size H 1  of the semiconductor package  100  is reduced, it is possible to reduce a size H 2  of the semiconductor module  10  of  FIG. 1A  in the second direction Y. 
         [0038]    Referring to  FIGS. 1C and 1D , the semiconductor module  10  may include multiple connection regions  110 A,  120 A, and  130 A, which are provided on the bottom surface  101   b  of the package substrate  101  and include connection elements  115 ,  125 , and  135 , respectively, which are used to electrically connect the semiconductor package  100  to the module substrate  90 . The connection regions  110 A,  120 A, and  130 A may include a first data connection region  110 A and a second data connection region  120 A, which are respectively used as transmission paths of the data signals DQ 1  and DQ 2  to be transmitted from and/or to the semiconductor package  100 , and a common connection region  130 A, which is used as a transmission path of the command/address signal C/A to be transmitted to the semiconductor package  100 . 
         [0039]    The first data connection region  110 A may include multiple first connection elements  115 , which are used as transmission paths of the first data signal DQ 1  to be transmitted between the first chip stack  110  and the connector  95 . The first connection elements  115  may be electrically connected to the first chip pads  116  through the first bonding wires  114 . Some of the first chip pads  116  may be data signal terminals configured to transmit and/or receive the first data signal DQ 1 . The second data connection region  120 A may include multiple second connection elements  125 , which are used as transmission paths of the second data signal DQ 2  to be transmitted between the second chip stack  120  and the connector  95 . The second connection elements  125  may be electrically connected to the second chip pads  126  through the second bonding wires  124 . Some of the second chip pads  126  may be data signal terminals configured to transmit and/or receive the second data signal DQ 1 . The common connection region  130 A may include multiple third connection elements  135 , which are used as transmission paths of the command/address signal C/A to be transmitted to the semiconductor package  100 . The third connection elements  135  may be electrically connected to the first chip pads  116  and the second chip pads  126 . Some of the first chip pads  116  and the second chip pads  126  may be command/address signal terminals configured to transmit and/or receive the command/address signal C/A. The first to third connection elements  115 ,  125 , and  135  may include, for example, solder bumps or solder balls, which are provided between the bottom surface  101   b  of the package substrate  101  and the top surface  90   a  of the module substrate  90 ; however, in other embodiments, different structures may be used for the first to third connection elements  115 ,  125 , and  135 . 
         [0040]    A pair of the first and second chip stacks  110  and  120  may be configured to share the command/address signal C/A. This may make it possible to reduce the number of the third connection elements  135 . The command/address signal C/A to be transmitted to the semiconductor package  100  may be transmitted to one of the first and second chip stacks  110  and  120  through at least one of the third connection elements  135 . For example, the command/address signal C/A may be transmitted to at least one the semiconductor chips  111 ,  112 ,  121 , and  122 , which is selected by at least one (e.g., a chip select ball) of the third connection elements  135 . The data signals DQ 1  and DQ 2  may be transmitted to corresponding ones of the semiconductor chips  111 ,  112 ,  121 , and  122  through corresponding ones of the connection elements  115  and  125 . 
         [0041]    Each of the first and second data connection regions  110 A and  120 A may be overlapped with at least a portion of the first chip stack  110 , and the common connection region  130 A may be overlapped with at least a portion of the second chip stack  120 . However, embodiments are not limited thereto. For example, the common connection region  130 A may be overlapped with at least a portion of the first chip stack  110 . 
         [0042]    According to this embodiment, at least one of the first and second data connection regions  110 A and  120 A may be closer to the connector  95 , compared with the common connection region  130 A. For example, the first and second data connection regions  110 A and  120 A may be arranged in the first direction X on the bottom surface  101   b  of the package substrate  101  and may be provided adjacent to the connector  95 . Since the first data connection region  110 A is adjacent to the connector  95 , it is possible to reduce a length of the first routing  151  between the connector  95  and the first chip pads  116 , which are electrically connected to the first connection elements  115 . The reduction in length of the first routing  151  may make it possible to realize faster transmission or exchange of the first data signal DQ 1  between the first chip stack  110  and the connector  95 . Since the second data connection region  120 A is positioned similarly, transmission or exchange of the second data signal DQ 2  between the second chip stack  120  and the connector  95  may also be improved. 
         [0043]    In some embodiments, the semiconductor package  100  may further include a third chip stack and a third data connection region, and here, the third data connection region may be used as a signal path for third data signals to be transmitted to the third chip stack. The third chip stack in conjunction with the first and second chip stacks  110  and  120  may be arranged in the second direction Y. The third data connection region in conjunction with the first and second data connection regions  110 A and  120 A may be arranged in the first direction X. In some embodiments, all data connection regions of the semiconductor package  100  may be arranged along the X direction so that each is adjacent to the connector  95 . 
         [0044]    As used herein, each of the first and second routings  151  and  152  may be used to refer to a “signal transmission” or a “signal transmission path”, but embodiments are not limited thereto. For example, the first routing  151  may represent signal lines between the first connection elements  115  and the connector  95 , and the second routing  152  may represent signal lines between the second connection elements  125  and the connector  95 . 
         [0045]      FIG. 2A  is a bottom plan view illustrating a modified example of  FIG. 1C .  FIG. 2B  is a sectional view taken along line IA′-IB′ of  FIG. 2A  illustrating a modified example of  FIG. 1D . 
         [0046]    Referring to  FIG. 2A , the common connection region  130 A and a mixed data connection region  140 A may be provided on the bottom surface  101   b  of the package substrate  101 . Here, the common connection region  130 A may be used as a transmission path of the command/address signal C/A, and the mixed data connection region  140 A may be provided to be adjacent to the connector  95 , closer than the common connection region  130 A, and may be used as transmission paths of the data signals DQ 1  and DQ 2 . The mixed data connection region  140 A may include multiple the first connection elements  115 , which are provided to electrically connect the first chip stack  110  to the connector  95 , and multiple the second connection elements  125 , which are provided to electrically connect the second chip stack  120  to the connector  95 . According to this embodiment, the first connection elements  115  and the second connection elements  125  may be mixed and provided in the single mixed data connection region  140 A. 
         [0047]    Referring to  FIG. 2B , the semiconductor package  100  may have a single-layered structure. For example, the semiconductor package  100  may include the first lower semiconductor chip  111  and the second lower semiconductor chip  121  provided on the top surface  101   a  of the package substrate  101 . The first lower semiconductor chip  111  and the second lower semiconductor chip  121  may be connected to the package substrate  101  through bonding wires, as described previously with reference to  FIGS. 1C and 1D . However, in other embodiments, the chip stacks may be used in place of one or more of the single semiconductor chips  111  and  121  as described above. 
         [0048]      FIG. 3A  is a plan view illustrating a semiconductor module according to some embodiments.  FIG. 3B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 3A .  FIG. 3C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 3A .  FIG. 3D  is a sectional view taken along line IC-ID of  FIG. 3C .  FIGS. 3E and 3F  are bottom plan views illustrating modified examples of  FIG. 3C . 
         [0049]    Referring to  FIG. 3A , a semiconductor module  20  may have a structure similar to the semiconductor module  10  of  FIG. 1A . The semiconductor module  20  may include multiple semiconductor packages  200 , which are provided on the top surface  90   a  of the module substrate  90  and are arranged in the first direction X. In some embodiments, multiple semiconductor packages  200  may be further provided on the bottom surface  90   b  of the module substrate  90 . 
         [0050]    Referring to  FIGS. 3B and 3D , the semiconductor package  200  may be mounted on the top surface  101   a  of the single package substrate  101  and may include at least two chip stacks  210  and  220 , which are encapsulated with a mold layer  203 . The first chip stack  210  and the second chip stack  220  may be arranged in the second direction Y. 
         [0051]    The first chip stack  210  may be stacked on the top surface  101   a  of the package substrate  101  may include a first lower semiconductor chip  211  and a first upper semiconductor chip  212 . The first chip stack  210  may include at least one first through electrode  214 , which is provided in each the first lower semiconductor chip  211  and the first upper semiconductor chip  212 . For example, the first through electrode  214  may be provided to penetrate at least a portion of each of the first lower semiconductor chip  211  and the first upper semiconductor chip  212 . First connection terminals  213  (e.g., solder balls or solder bumps) may be provided between the first lower semiconductor chip  211  and the package substrate  101  and between the first lower semiconductor chip  211  and the first upper semiconductor chip  212  and may be electrically connected to the first through electrodes  214 . The first lower semiconductor chip  211  and the first upper semiconductor chip  212  may be electrically connected to each other and/or to the package substrate  101  through the first through electrodes  214 . In some embodiments, at least one semiconductor chip may be further stacked on the first upper semiconductor chip  212 . 
         [0052]    The second chip stack  220  may have a same or similar structure as the first chip stack  210 . For example, the second chip stack  220  may be stacked on the top surface  101   a  of the package substrate  101  and may include a second lower semiconductor chip  221 , a second upper semiconductor chip  222 , second connection terminals  223  and second through electrodes  224  similar to corresponding structures of the first chip stack  210 . 
         [0053]    In addition to the above features, the semiconductor module of  FIGS. 3C and 3D  may be configured to have substantially the same features as that of  FIGS. 1C and 1D . In some embodiments, as described previously with reference to  FIG. 2A , the semiconductor module  20  may include the common connection region  130 A and the mixed data connection region  140 A. 
         [0054]    As shown in  FIG. 3B or 3C , the first through electrodes  214  may be arranged on a center region, which is elongated in the second direction Y, of the first chip stack  210  to form one or more columns parallel to the second direction Y. Similarly, the second through electrodes  224  may be arranged on a center region, which is elongated in the second direction Y, of the second chip stack  220  to form one or more columns parallel to the second direction Y. The first through electrodes  214  and the second through electrodes  224  may be provided to be aligned in the second direction Y. 
         [0055]    Alternatively, as shown in  FIG. 3E , the first through electrodes  214  may be arranged on a center region, which is elongated in the first direction X, of the first chip stack  210  to form one or more columns parallel to the first direction X. Similarly, the second through electrodes  224  may be arranged on a center region, which is elongated in the first direction X, of the second chip stack  220  to form one or more columns parallel to the first direction X. In some embodiments, as shown in  FIG. 3F , the first through electrodes  214  and the second through electrodes  224  may be arranged in a mesh or grid shape. 
         [0056]      FIG. 4A  is a plan view illustrating a semiconductor module according to some embodiments.  FIG. 4B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 4A .  FIG. 4C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 4A .  FIG. 4D  is a sectional view taken along line IE-IF of  FIG. 4C . 
         [0057]    Referring to  FIG. 4A , a semiconductor module  30  may have a structure similar to the semiconductor module  10  of  FIG. 1A . The semiconductor module  30  may include multiple semiconductor packages  300 , which are arranged in the first direction X on at least one of the top and bottom surfaces  90   a  and  90   b  of the module substrate  90 . 
         [0058]    Referring to  FIGS. 4B and 4D , the semiconductor package  300  may have a single-layered structure. For example, the semiconductor package  300  may include a first semiconductor chip  311  and a second semiconductor chip  321 , which are arranged in the second direction Y on the top surface  101   a  of the package substrate  101  and are encapsulated with a mold layer  303 . In some embodiments, the first semiconductor chip  311  and the second semiconductor chip  321  may be mounted on the package substrate  101  in a flip-chip manner. The first semiconductor chip  311  may be electrically connected to the package substrate  101  through one or more first connection terminals  314  (e.g., solder balls or solder bumps). The first semiconductor chip  311  may include first chip pads  316  coupled to the first connection terminals  314 . Similarly, the second semiconductor chip  321  may be electrically connected to the package substrate  101  through one or more second connection terminals  324  (e.g., solder balls or solder bumps). The second semiconductor chip  321  may include second chip pads  326  coupled to the second connection terminals  324 . 
         [0059]    Referring to  FIGS. 4C and 4D , the bottom surface  101   b  of the package substrate  101  and a structure thereon may be the same as or similar to that described with reference to  FIGS. 1C and 1D . For example, the semiconductor module  30  may include the first and second data connection regions  110 A and  120 A, which are adjacent to the connector  95 , and the common connection region  130 A, which is farther away from the connector  95 . In addition to the above features, the semiconductor module of  FIGS. 4C and 4D  may be configured to have substantially the same or similar features as that of  FIGS. 1C and 1D . In some embodiments, as described previously with reference to  FIG. 2A , the semiconductor module  30  may include the common connection region  130 A and the mixed data connection region  140 A. 
         [0060]      FIG. 5A  is a plan view illustrating a semiconductor module according to some embodiments.  FIG. 5B  is a top plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 5A .  FIG. 5C  is a bottom plan view illustrating a portion (e.g., a semiconductor package) of  FIG. 5A .  FIG. 5D  is a sectional view taken along line IG-IH of  FIG. 5C .  FIG. 5E  is a sectional view taken along line II-IJ of  FIG. 5C . 
         [0061]    Referring to  FIG. 5A , a semiconductor module  40  may have a structure similar to the semiconductor module  10  of  FIG. 1A . The semiconductor module  40  may include multiple semiconductor packages  400 , which are arranged in the first direction X on at least one of the top and bottom surfaces  90   a  and  90   b  of the module substrate  90 . 
         [0062]    Referring to  FIG. 5B , the semiconductor package  400  may be provided on the top surface  101   a  of the package substrate  101  and may include a first chip stack  410  and a second chip stack  420  encapsulated with the mold layer  403  (e.g., see  FIG. 5D or 5E ). The first and second chip stacks  410  and  420  may be arranged in the first direction X. For example, if a size of the semiconductor package  400  or the semiconductor module  40  is not strongly dependent on some dimensions (e.g., lengths in the first direction X) of the semiconductor chips provided in the first and second chip stacks  410  and  420 , the first and second chip stacks  410  and  420  may be arranged in the first direction X. 
         [0063]    As shown in  FIG. 5D , the first chip stack  410  may include a first lower semiconductor chip  411  and a first upper semiconductor chip  412 , which are stacked on the top surface  101   a  of the package substrate  101 , a first adhesive layer  413 , which is used to attach the first lower semiconductor chip  411  to the first upper semiconductor chip  412  and attach the first lower semiconductor chip  411  to the package substrate  101 , and first bonding wires  414 , which are used to electrically connect the first lower semiconductor chip  411  and the first upper semiconductor chip  412  to the package substrate  101 . The first lower semiconductor chip  411  and the first upper semiconductor chip  412  may include first chip pads  416  electrically connected to the first bonding wires  414 . Each of the first bonding wires  414  may extend in the second direction Y, as shown in  FIG. 5B . 
         [0064]    As shown in  FIG. 5E , the second chip stack  420  may include a second lower semiconductor chip  421  and a second upper semiconductor chip  422 , which are stacked on the top surface  101   a  of the package substrate  101 , a second adhesive layer  423 , which is used to attach the second lower semiconductor chip  421  to the second upper semiconductor chip  422  and attach the second lower semiconductor chip  421  to the package substrate  101 , and second bonding wires  424 , which are used to electrically connect the second lower semiconductor chip  421  and the second upper semiconductor chip  422  to the package substrate  101 . The second lower semiconductor chip  421  and the second upper semiconductor chip  422  may include second chip pads  426  electrically connected to the second bonding wires  424 . Each of the second bonding wires  424  may extend in the second direction Y, as shown in  FIG. 5B . 
         [0065]    Referring to  FIGS. 5C, 5D, and 5E , the bottom surface  101   b  of the package substrate  101  and a structure thereon may be the same as or similar to that described with reference to  FIGS. 1C and 1D . In addition to the above features, the semiconductor module of  FIGS. 5C to 5E  may be configured to have substantially the same or similar features as that of  FIGS. 1C and 1D . In some embodiments, as described previously with reference to  FIG. 2A , the semiconductor module  40  may include the common connection region  130 A and the mixed data connection region  140 A. 
         [0066]    According to some embodiments, multiple semiconductor packages are integrated into a single semiconductor package, and thus, it is possible to reduce a total size of the semiconductor package and to reduce a size of a semiconductor module. Furthermore, connection terminals may be arranged to reduce or minimize a length of a routing path, and thus, it is possible to improve a data processing speed of the semiconductor module. 
         [0067]    While particular embodiments have been shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.