Abstract:
A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of provisional patent application Ser. No. 61/714,326, filed Oct. 16, 2012, and provisional patent application Ser. No. 61/790,080, filed Mar. 15, 2013, the disclosures of which are hereby incorporated by reference in their entirety. 
     
    
     FIELD OF THE DISCLOSURE 
       [0002]    The present disclosure relates generally to the miniaturization of integrated circuit (IC) packages, and specifically to the redistribution of the connection points of an IC package. 
       BACKGROUND 
       [0003]    Modern integrated circuit (IC) packages are constantly shrinking in size to accommodate their increasing use in handheld devices. Although the use of small IC packaging saves space in a host device, the connection points of a small IC package may require significant resources to properly connect to a substrate for integration into a system. Further, the same components used in handheld devices may also be used in larger systems and devices where space is not an issue. Using a small IC package in a larger system may result in unnecessary complexity and expense due to the difficulty of integration. 
         [0004]    Processes have been developed for producing redistribution layers for repositioning the connection points of an IC package. These redistribution layers may bring the connection points of the IC package closer together (i.e., a “fan in” layer), or further apart (i.e., a “fan out” layer). Processes for developing redistribution layers often require specialized equipment, thereby driving up the cost of a system. Further, the produced redistribution layers may introduce undesirable parasitic capacitance or inductance into a system due to the thickness of the conductive material in the layer. Accordingly, a process is needed to produce a redistribution layer for the connection points of an IC package at a low cost while minimizing the impact of the layer on the operation of the IC device. 
       SUMMARY 
       [0005]    The present invention relates to a process for generating a redistribution layer for redistributing the contact points of an IC package. A carrier layer including a first plate-able layer is used to support one or more selectively plated redistribution paths. The first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over-molded for stability. The carrier layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the carrier layer, fine geometries for redistributing the contact points of the 
         [0006]    IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device. 
         [0007]    Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0008]      FIG. 1  is a schematic representation of an IC package with an attached redistribution layer. 
           [0009]      FIG. 2  is a schematic representation of an IC package with an attached redistribution layer according to an additional embodiment. 
           [0010]      FIG. 3  is a schematic representation of an IC package with an attached redistribution layer according to an additional embodiment. 
           [0011]      FIGS. 4A and 4B  are diagrams representing the process for creating a redistribution layer. 
           [0012]      FIGS. 5A-5O  are a graphic representation of each step of the process described in  FIG. 4  for creating the redistribution layer. 
           [0013]      FIGS. 6A and 6B  are diagrams representing the process for creating a redistribution layer according to an additional embodiment of the present disclosure. 
           [0014]      FIGS. 7A-7O  are a graphic representation of each step of the process described in  FIG. 6  for creating the redistribution layer. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
         [0016]    It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0017]    It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
         [0018]    Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
         [0019]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0020]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0021]    Turning now to  FIG. 1 , an IC package  10  with an attached redistribution layer  12  is shown. Connection points  14  of the IC package  10  are attached to the redistribution layer  12  at one or more package connection pads  16 . Although the IC package  10  shown is a bumped die package, any form of IC package may be used according to the present disclosure. The package connection pads  16  are soldered to one or more redistribution paths  18 , which are in turn plated to one or more redistributed connection pads  20 . The redistribution paths  18  are covered by a patterned soldering mask  22 . The IC package  10  and the redistribution layer  12  are stabilized by an over molding layer  24 . As shown in  FIG. 1 , the redistributed connection pads  20  of the redistribution layer  12  relocate the connection points  14  of the IC package  10  by a predetermined distance D. Accordingly, the connection points  14  of the IC package  10  are redistributed to facilitate integration of the IC package  10  into a system. 
         [0022]      FIG. 2  shows the IC package  10  with the attached redistribution layer  12  according to one embodiment of the present disclosure. According to this embodiment, the IC package  10  is a wire-bonded die. The connection points  14  of the IC package  10  are connected to the redistribution layer  12  at the package connection pads  16  by one or more bond wires  26 . A die attach material  28  may also be provided in order to secure the wire-bonded die to the redistribution layer  12 . The package connection pads  16  are wire bonded to one or more redistribution paths  18 , which are in turn plated to the one or more redistributed connection pads  20 . The redistribution paths  18  are covered by the patterned soldering mask  22 . The IC package and the redistribution layer  12  are stabilized by the over molding layer  24 . As shown in  FIG. 2 , the redistributed connection pads  20  of the redistribution layer  12  relocate the connection points  14  of the IC package  10  by a predetermined distance D. Accordingly, the connection points  14  of the IC package  10  are redistributed to facilitate integration of the IC package  10  into a system. 
         [0023]      FIG. 3  shows the IC package  10  with the attached redistribution layer  12  according to an additional embodiment of the present disclosure. According to this embodiment, the IC package  10  is a non-bumped die without extruding connection points. The connection points  14  of the IC package  10  are directly connected to the redistribution layer  12  by the package connection pads  16 , for example, by a soldering process. The package connection pads  16  are plated to one or more redistribution paths  18 . In this embodiment, the redistribution layer has two layers of redistribution paths  18  in order to properly connect to the IC package  10 . A top layer of redistribution paths  18 B is adapted to align with the connection points  14  of the IC package  10 , and is plated to a bottom layer of redistribution paths  18 A. The bottom layer of redistribution paths  18 A is plated to the one or more redistributed connection pads  20 . The bottom layer of redistribution paths  18 A is covered by the patterned soldering mask  22 . The IC package  10  and the redistribution layer  12  are stabilized by the over molding layer  24 . As shown in  FIG. 3 , the redistributed connection pads  20  of the redistribution layer  12  relocate the connection points  14  of the IC package  10  by a predetermined distance D. Accordingly, the connection points  14  of the IC package  10  are redistributed to facilitate integration of the IC package  10  into a system. 
         [0024]    With reference to the flow diagram of  FIG. 4  and the corresponding graphical representations of  FIG. 5 , a manufacturing process for the redistribution layer  12  is provided according to one embodiment of the present disclosure. The process begins by bonding a copper foil  30  to a rigid carrier  32  to form a base carrier  34  (step  100  and  FIG. 5A ). A first plating resist  36  is then applied to the copper foil  30  (step  102  and  FIG. 5B ). The first plating resist  36  is imaged, then developed to form a first patterned plating resist  38  (step  104  and  FIG. 5C ). The areas of the copper foil  30  exposed through the first patterned plating resist  38  are then plated to form one or more redistribution paths  18  (step  106  and  FIG. 5D ). This step may be repeated one or more times to form multiple layers of redistribution paths  18 . A second plating resist  40  is then applied on top of the first patterned plating resist  38  (step  108  and FIG.  5 F), and is imaged and developed to form a second patterned plating resist  42  (step  110  and  FIG. 5G ). The areas of the redistribution paths  18  exposed through the second patterned plating resist  42  are then plated to form the one or more package connection pads  16  (step  112  and  FIG. 5H ). The first patterned plating resist  38  and the second patterned plating resist  42  are then removed, using, for example, a chemical etching/stripping process (step  114  and  FIG. 5I ). 
         [0025]    The connection points  14  of the IC package  10  are then connected to the package connection pads  16  (step  116  and  FIG. 5J ), and the IC package  10  is over molded with the over molding layer  24  for stability (step  118  and 
         [0026]      FIG. 5K ). The base carrier  34  is then removed by first removing the rigid carrier  32  (step  120  and  FIG. 5L ), then removing the copper foil  30  with a chemical etch process (step  122  and  FIG. 5M ). The rigid carrier  32  may be removed, for example, by a mechanical routing process. A soldering mask  21  is applied to the exposed surface from which the base carrier  34  was removed (step  124  and  FIG. 5N ), and is imaged and developed to form a patterned soldering mask  22  (step  126  and  FIG. 5O ). The areas of the redistribution paths  18  exposed through the patterned soldering mask  22  are then plated to form the one or more redistributed connection pads  20  (step  128  and  FIG. 5P ). 
         [0027]    The composition, structure, and type of components used to generate the redistribution layer  12  can vary in the manufacturing process. In one embodiment, the copper foil  30  may be approximately 3-5 microns thick. The rigid carrier  32  may comprise a laminate material or any other rigid material suitable for supporting the copper foil  30  throughout the manufacturing process. The redistribution paths  18  may be made of electrodeposited copper approximately 10-30 microns thick. The one or more package connection pads  16  may be made of electrodeposited tin approximately 5-20 microns thick, deposited electroless nickel and immersion gold, with respective approximate thicknesses of 0.4-6.0 microns and 0.05-0.15 microns, immersion silver approximately 0.12-0.20 microns thick, electrodeposited nickel and gold, with respective approximate thicknesses of 3.0-6.0 microns and 0.05-0.15 microns, or an organic solderability preservative. 
         [0028]    The one or more redistributed connection pads  20  may be made of electrodeposited tin approximately 5-20 microns thick, deposited electroless nickel and immersion gold, with respective approximate thicknesses of 0.4-6.0 microns and 0.05-0.15 microns, immersion silver approximately 0.12-0.20 microns thick, electrodeposited nickel and gold, with respective approximate thicknesses of 3.0-6.0 microns and 0.05-0.15 microns, or an organic solderability preservative. 
         [0029]    With reference to the flow diagram of  FIG. 6  and the corresponding graphical representations of  FIG. 7 , a manufacturing process for the redistribution layer  12  is provided according to one embodiment of the present disclosure. The process begins by application of a first plating resist  45  to a plate-able copper carrier layer  44  (step  200  and  FIG. 7A ). The first plating resist  45  is then imaged and developed to form a first patterned plating resist  46  (step  202  and  FIG. 7B ). The areas of the plate-able copper carrier layer  44  exposed through the first patterned plating resist  46  are then plated to form a first protective layer  48  (step  204  and  FIG. 7C ). The first protective layer  48  is then plated to form one or more redistribution paths  18  (step  206  and  FIG. 7D ). This step may be repeated one or more times to form multiple layers of redistribution paths  18 . A second plating resist  50  is then applied on top of the first patterned plating resist  46  (step  208  and  FIG. 7F ), and imaged and developed to form a second patterned plating resist  52  (step  210  and  FIG. 7G ). The areas of the redistribution paths  18  exposed through the second patterned plating resist  52  are then plated to form the one or more package connection pads  16  (step  212  and  FIG. 7H ). The first patterned plating resist  46  and the second patterned plating resist  52  are then removed, using, for example, a chemical etching/stripping process (step  214  and  FIG. 7I ). 
         [0030]    The connection points  14  of the IC package  10  are then connected to the package connection pads  16  (step  216  and  FIG. 7J ), and the IC package is stabilized with the over molding layer  24  (step  218  and  FIG. 7K ). The plate-able copper carrier layer  44  is then removed using, for example, a chemical etching process (step  220  and  FIG. 7L ). The first protective layer  48  is also removed, using, for example, a chemical etching process (step  222  and  FIG. 7M ). A soldering mask  21  is applied to the exposed surface from which the plate-able copper carrier layer  44  and the first protective layer  48  were removed (step  224  and  FIG. 7N ). The soldering mask  21  is imaged and developed to form a patterned soldering mask  22  (step  226  and  FIG. 7O ). The exposed surface of the one or more redistribution paths  18  are then plated to form the one or more redistributed connection pads  20  (step  228  and  FIG. 7P ). 
         [0031]    The composition, structure, and type of components used to generate the redistribution layer  12  can vary in the manufacturing process. The plate-able copper carrier layer  44  may comprise a rigid copper sheet approximately 100-150 microns in thickness. The protective layer may comprise nickel or tin approximately 3-5 microns in thickness, and may be adapted to be easily etched away. The redistribution paths  18  may be made of electrodeposited copper approximately 10-30 microns thick. 
         [0032]    The one or more package connection pads  16  may be made of electrodeposited tin approximately 5-20 microns thick, deposited electroless nickel and immersion gold, with respective approximate thicknesses of 0.4-6.0 microns and 0.05-0.15 microns, immersion silver approximately 0.12-0.20 microns thick, electrodeposited nickel and gold, with respective approximate thicknesses of 3.0-6.0 microns and 0.05-0.15 microns, or an organic solderability preservative. 
         [0033]    The one or more redistributed connection pads  20  may be made of electrodeposited tin approximately 5-20 microns thick, deposited electroless nickel and immersion gold, with respective approximate thicknesses of 0.4-6.0 microns and 0.05-0.15 microns, immersion silver approximately 0.12-0.20 microns thick, electrodeposited nickel and gold, with respective approximate thicknesses of 3.0-6.0 microns and 0.05-0.15 microns, or an organic solderability preservative. 
         [0034]    Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.