Abstract:
An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells.

Description:
RELATED APPLICATION 
       [0001]    This application is a continuation of and claims the priority benefit of U.S. application Ser. No. 12/423,013, filed on Apr. 14, 2009, now allowed, which is a continuation application (CA) of U.S. Utility patent application Ser. No. 11/096,878, filed on Apr. 1, 2005, now U.S. Pat. No. 7,535,771, issued on May 19, 2009. The prior application Ser. No. 11/096,878 application claims the benefit of U.S. Provisional Application No. 60/624,553, entitled “NROM MEMORY DEVICES AND METHODS TO IMPROVE ERASE UNIFORMITY AND TO SCREEN FOR MARGINAL MEMORY CELLS,” filed on Nov. 4, 2004. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. 
     
    
     FIELD 
       [0002]    The present invention relates generally to non-volatile memories and, more particularly, to devices and methods to improve erase uniformity and to screen for marginal memory cells for nitride read-only memories (NROMs). 
       BACKGROUND 
       [0003]    The increasing demand for consumer electronics, such as digital cameras, MP3 players, laptop computers, and personal data assistants (PDAs), requires non-volatile memory devices to store large amounts of data. Non-volatile memory devices for mass storage are cost driven in order to obtain the lowest cost productions. One type of low cost non-volatile memory is a nitride read only memory (NROM). 
         [0004]    A NROM memory cell includes an oxide-nitride-oxide (ONO) gate dielectric and a controlling gate above the ONO gate dielectric. It allows two spatially-separated charge distributions in the nitride layer of the ONO gate dielectric, respectively, at the areas above the source and drain junctions of the memory cell. As a result, the ONO dielectric can store two bits of information per memory cell above those junctions. Thus, the NROM 2-bit memory cell architecture is attractive at least because it can decrease memory array size and the cost of making non-volatile memory devices. 
         [0005]    A NROM memory cell can be programmed by “channel hot-electron injection.” In a program operation, depending on the voltages applied to source, drain, and gate nodes, the electrons in the drain&#39;s pinch-off region can move toward the nitride layer of the ONO dielectric to program the memory cell. The NROM memory cell can be erased by “band-to-band hot hole injection.” In an erase operation, depending on the voltages applied, holes are generated by band-to-band tunneling under the ONO dielectric of the appropriate junction. The holes can be injected into the ONO dielectric if a strong lateral electric field is generated in the channel region. Those injected holes can combine with electrons of the stored charge to erase the memory cell for a particular bit above a desired junction. 
         [0006]    Erase operations rely heavily on having a strong lateral electric field generated in the channel region. To perform an erase operation correctly, proper voltages must be applied to the source, drain, and gate nodes of the memory cell. FIGS.  1  and  2  illustrate prior art NROM cells with the applied node voltages shown to perform prior erase operations. Referring to  FIG. 1 , a single side erase can be performed using band-to-band hot hole injection for the NROM memory cell. For example, to erase Bit  1 , node  101  receives a (−) negative voltage from a negative pump circuit, node  102  receives a (+) positive voltage from a positive pump circuit, and node  103  is connected to ground. To erase Bit  2 , node  101  receives a (−) negative voltage from a negative pump circuit, node  102  is connected to ground, and node  103  receives a (+) positive voltage from a positive pump circuit. The following TABLE 1 lists the voltages and connections for the nodes of  FIG. 1 , as detailed above. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 (Prior Erase Operation) 
               
             
          
           
               
                 Nodes 
                 Erasing Bit 1 
                 Erasing Bit 2 
               
               
                   
               
               
                 Node 101 
                 (−) Negative Voltage 
                 (−) Negative Voltage 
               
               
                 Node 102 
                 (+) Positive Voltage 
                 GND 
               
               
                 Node 103 
                 GND 
                 (+) Positive Voltage 
               
               
                   
               
             
          
         
       
     
         [0007]    This prior NROM memory cell operation suffers from a disadvantage that if the (+) positive voltage applied to nodes  102  or  103  to erase Bit  1  or Bit  2 , respectively, exceeds the punch-through voltage of the memory cell, the positive pump circuit will crash, causing the erase operation to fail. This occurs when the bit-line bias is over the punch-through voltage. For example, when a large bias exists between the source and the drain, punch through may occur at the channel region, causing the voltage difference to drop. The drop in the voltage difference may result in an insufficient lateral electric field, thereby impacting an erase operation or causing non-erase of the bit. 
         [0008]    Referring to  FIG. 2 , to erase Bit  1 , node  201  receives a (−) negative voltage from a negative pump circuit, node  202  receives a (+) positive voltage from a positive pump circuit, and node  103  is floating. To erase Bit  2 , node  201  receives a (−) negative voltage from a negative pump circuit, node  202  is floating, and node  203  receives a (+) positive voltage from a positive pump circuit. The following TABLE 2 lists the voltages and connections for the nodes of  FIG. 2 , as detailed above. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 (Prior Erase Operation) 
               
             
          
           
               
                 Nodes 
                 Erasing Bit 1 
                 Erasing Bit 2 
               
               
                   
               
               
                 Node 201 
                 (−) Negative Voltage 
                 (−) Negative Voltage 
               
               
                 Node 202 
                 (+) Positive Voltage 
                 Floating 
               
               
                 Node 203 
                 Floating 
                 (+) Positive Voltage 
               
               
                   
               
             
          
         
       
     
         [0009]    This prior NROM memory cell suffers from a disadvantage that nodes  202  or  203 , when floating to erase Bits  1  or  2 , may be coupled to an uncertain voltage level due to bit-line coupling or leakage current, causing the erase operation to fail. In particular, the uncertainty in voltage level may cause erase non-uniformity across memory cells. 
         [0010]    Furthermore, some memory cells in the prior art NORM memory arrays may suffer marginal defects, such as buried drain oxide breakdown, source-drain leakage, and so forth. Such marginal defects can cause serious problems in a NROM memory array after fabrication, and screening such defects during testing can be difficult. As noted above, if one side of a memory cell is connected to GND and the other side of the memory cell is connected to a positive pump circuit, the bit-line bias may exceed the punch-through voltage, causing the pump circuit to crash. Moreover, if one side of the memory cell is floating during an erase, the memory cell can be coupled to an uncertain voltage that causes instabilities during erase operations. For example, the threshold voltage (Vt) distribution after an erase operation will become wider. The variation of the uncertain voltage level may cause erase non-uniformity across the memory cells. 
         [0011]    Thus, what is needed are improved NROM non-volatile memory devices and NROM memory cell operations and testing methods to screen for marginal defects. 
       SUMMARY 
       [0012]    An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells. 
         [0013]    An embodiment of the invention provides a method of operating one of a plurality of memory cells. Each of the plurality of memory cells has a first node, a second node and a third node and is coupled to one of a plurality of bit lines. The method includes following steps. A negative voltage is provided to the first node of one of the plurality of memory cells. A positive voltage is provided to the second node of one of the plurality of memory cells. The third node of one of the plurality of memory cells is coupled to a common node formed by a connection of the plurality of bit lines which is respectively coupled to the third nodes of the plurality of memory cells. 
         [0014]    An embodiment of the invention provides another memory array including a first and a second memory cells, a first and a second bit lines and a first and a second switches. Each of the first and the second memory cells has a first node, a second node, and a third node. The first and the second bit lines are respectively coupled to the third nodes of the first and the second memory cells. The first and the second switches respectively corresponding to the first and the second bit lines couple the first and the second bit lines together. 
         [0015]    In an embodiment of the invention, the device comprises two set of sub-devices respectively coupling a part of the plurality of bit lines together to form different common nodes. 
         [0016]    In an embodiment of the invention, the common node could be coupled to a limited current source. 
         [0017]    In an embodiment of the invention, the limited current source may have a current in relation to a current resulted at the second node which is provided with a positive voltage. 
         [0018]    In an embodiment of the invention, the second node of one of the plurality of memory cells could be coupled to a positive voltage when the third node is coupled to the common node. 
         [0019]    In an embodiment of the invention, the operating could be an erasing operation. 
         [0020]    It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are not intended to limit the scope of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]    The accompanying drawings, which are incorporated in, and constitute a part of the specification, illustrate exemplary implementations and examples of the invention and, together with the detailed description, serve to explain the principles of the invention. In the drawings, 
           [0022]      FIG. 1  illustrates a prior art NROM memory cell during an erase operation; 
           [0023]      FIG. 2  illustrates another prior art NROM memory cell during an erase operation; 
           [0024]      FIG. 3  illustrates one example of a NROM memory cell with exemplary node voltages capable of coupling to a common node; 
           [0025]      FIG. 4  illustrates one example of a NROM memory cell with exemplary node voltages capable of coupling to a limited current source; 
           [0026]      FIG. 5  illustrates one example of a NROM memory array having a virtual ground array and a discharge system; 
           [0027]      FIG. 6  illustrates one example of the discharge system of  FIG. 5  in further detail; 
           [0028]      FIG. 7  illustrates one example of a flow diagram to screen for marginal memory cells performing defective erase operations; 
           [0029]      FIG. 8  illustrates one example voltage distribution for screening out marginal memory cells; and 
           [0030]      FIG. 9  illustrates another example of a flow diagram to screen for marginal memory cells performing defective erase operations. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    Reference will now be made in detail to exemplary embodiments and examples of the invention, some of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0032]    The following examples and implementations can overcome disadvantages of conventional NROM memory devices and improve erase uniformity for NROM memory cells and screening of memory cells for marginal defects. According to one example, a NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one side of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. By coupling to a common node or a limited current source, the source-side voltage can be stabilized and identical for each NROM cell in a memory array during an erase, thereby improving erase uniformity. 
         [0033]    Other examples and implementations can avoid punch through and maintain a desired lateral electric field during an erase operation, which also improves erase uniformity. Additionally, as described below, a memory array can be easily screened for marginal memory cells based on a threshold voltage distribution of the memory cells after a unique test mode erasing operation. 
         [0034]      FIG. 3  illustrates one example of a NROM memory cell having nodes capable of coupling to a common node for an erase operation. For example, to erase Bit  1 , node  301  receives a (−) negative voltage from a negative pump circuit, node  302  receives a (+) positive voltage from a positive pump circuit, and node  303  is coupled to a common node. To erase Bit  2 , node  301  receives a (−) negative voltage from a negative pump circuit, node  302  is coupled to a common node, and node  303  receives a (+) positive voltage from a positive pump circuit. The following TABLE 3 lists the voltages and connections for nodes  302  and  303  for erasing Bits  1  and  2  in  FIG. 3 , as detailed above. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 (Erase Operation Using Common Node) 
               
             
          
           
               
                   
                 Nodes 
                 Erasing Node 302 
                 Erasing Node 303 
               
               
                   
                   
               
               
                   
                 Node 301 
                 (−) Negative Voltage 
                 (−) Negative Voltage 
               
               
                   
                 Node 302 
                 (+) Positive Voltage 
                 Couple to Common Node 
               
               
                   
                 Node 303 
                 Couple to Common Node 
                 (+) Positive Voltage 
               
               
                   
                   
               
             
          
         
       
     
         [0035]    Referring to TABLE 3, in this example, when erasing Bits  1  and  2 , the voltage level, provided by a common node connection, may be maintained at an proper value, such as a value that remains high enough to prevent punch through of the memory cell, but still remains low enough to maintain a strong lateral electric field in the channel region to render bit erase. In this manner, coupling nodes  302  and  303  to such common node may improve the erase uniformity of the memory cell. 
         [0036]      FIG. 4  illustrates one example of a NROM memory cell having nodes capable of coupling to a limited current source for an erase operation. For example, to erase Bit  1 , node  401  receives a (−) negative voltage from a negative pump circuit, node  402  receives a (+) positive voltage from a positive pump circuit, and node  403  receives current from a limited current source. To erase Bit  2 , node  401  receives a (−) negative voltage from a negative pump circuit, node  402  receives current from a limited current source, and node  403  receives a (+) positive voltage from a positive pump circuit. The following TABLE 4 lists the voltages and connections for nodes  402  and  403  for erasing Bits  1  and  2  in  FIG. 4 , as detailed above. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 (Erase Operation Using Current Source) 
               
             
          
           
               
                   
                 Nodes 
                 Erasing Node 402 
                 Erasing Node 403 
               
               
                   
                   
               
               
                   
                 Node 401 
                 (−) Negative Voltage 
                 (−) Negative Voltage 
               
               
                   
                 Node 402 
                 (+) Positive Voltage 
                 Couple to Current Source 
               
               
                   
                 Node 403 
                 Couple to Current Source 
                 (+) Positive Voltage 
               
               
                   
                   
               
             
          
         
       
     
         [0037]    Referring to TABLE 4, in this example, when erasing Bits  1  and  2 , the current level of the limited current source can be set at a ratio of the erase current consumption. For example, the current level can be based on a ratio of the band-to-band erase current level and the positive pump circuit loading current level. In this manner, the voltage level of nodes  402  and  403  can be dynamic and related to the other node&#39;s voltage level. For example, if bit-line stepping is applied for an embedded erase operation for node  402 , then the voltage level of node  403  can be adjusted by the limited current source. Bit-line stepping erasing is the process that, if an erase verify fails after a one shot erase, the drain-side bit-line voltage level is increased for a retry erase shot. Also, because nodes  402  or nodes  403  of two or more memory cells in an array are commonly coupled to the same limited current source, the design may improve the erase uniformity of the memory cells in the array. 
         [0038]      FIG. 5  illustrates one example of a NROM memory array  500  capable of having the memory cells shown in  FIGS. 3 and 4 . For example, a plurality of memory cells  503  in the memory array  500  can refer to the memory cells described above. These memory cells  503  are arranged in “n” rows that can store two bits of information above a source junction and a drain junction per memory cell. In this example, the gate node of the first row of memory cells couples with a word line WL 0  and the gate node of the n.sup.th row of memory cells couples with the n.sup.th word line WLn. Any number of memory cells and rows of memory cells can be implemented for memory array  500 . 
         [0039]    The memory array  500  also includes a virtual ground array  502  and a discharge system  501 . In this example, the virtual ground array  502  outputs a plurality of metal bit lines, e.g., lines MBL 0  to MBL 3 , that couple at nodes between select transistors having select inputs (SEL 0 , SEL 1 ) and (SEL 2 , SEL 3 ) arranged in series, respectively, for selectively providing voltage and/or current. The select transistors for controlling the coupling to MBLs have their gate nodes coupled to respective select inputs (e.g., SEL 0 , SEL 1 , SEL 2 , and SEL 3 ) that selectively turn on their respective transistors. In this example, the select transistors are coupled to respective bit lines BL 0  through BL 7 . Depending on which select transistors are on, the bit lines can be coupled to a common node or a limited current source via the metal bit lines (“MBLs”) within the discharge system  501 , as illustrated in  FIG. 6  and explained in further detail below. 
         [0040]    For example, if the select input SEL 0  is on, the bit line BL 0  couples with metal bit line MBL 0  that can be coupled to a common node or limited current source within discharge system  501 . Likewise, if the select input SEL 1  is on, the bit line BL 2  couples with metal bit line MBL 0  that can be coupled to a common node or limited current source. In this manner, bit lines BL 0  and BL 2  can both be coupled to a common node or limited current source. The other bit lines can also be coupled to a common node or limited current source within discharge system  501  via metal bit lines MBL 1  through MBL 3  in a similar manner as bit lines BL 0  and BL 2 . 
         [0041]    Thus, the select inputs allow control of coupling certain nodes of the memory cells to a common node or a limited current source. In particular, the even-numbered bit-line connections, e.g., BL 0 , BL 2 , BL 4 , and BL 6 , couple with the nodes of the transistors coupled to select inputs SEL 0  and SEL 1 . The odd-numbered bit-line connections, e.g., BL 1 , BL 3 , BL 5 , and BL 7 , couple with the nodes of the transistors coupled to select inputs SEL 2  and SEL 3 . In this manner, sets of bit-line connections pair other sets of bit-line connections. For example, even bit-line connections BL 0  and BL 2  pair with odd bit-line connections BL 1  and BL 3  to at least control erasing of four memory cells in four columns. 
         [0042]      FIG. 6  illustrates the discharge system  501  of  FIG. 5  in further detail. The discharge system includes nodes  601  and  602  and a plurality of discharge or pull-down transistors DISCH  0  through DISCH n coupled to respective metal bit lines MBL 0  through MBLn. The nodes  601  and  602  can represent a common node or a current source or connect to the same. In this example, node  601  is coupled to discharge transistors DISCH  0 , DISCH  2 , and DISCH n−1 and node  602  is coupled to discharge transistors DISCH  1 , DISCH n−2, and DISCH n. When the discharge transistors are on, the discharge system  501  can connect the metal bit lines MBLs to a common node or act as limited current source. 
         [0043]    In one example, nodes  601  and  602  can be or connect to a common node, examples of which include a floating ground or a positive voltage source. If the common node is a positive voltage source, the voltage level from this source should be set high enough to prevent punch-through and low enough to maintain a lateral electric field for proper erase capabilities. If nodes  601  and  602  are common nodes and a particular discharge transistor is on, the corresponding metal line to the discharge transistor will be coupled to a common node. If the discharge system  501  acts as a limited current source, the nodes  601  or  602  can be or connect to a current source. When a discharge transistor is on, it will discharge a current from its corresponding node  601  or  602  that is or connect to a current source, thereby providing a limited current source. 
         [0044]    The operation of erasing a memory cell with respect to  FIGS. 5 and 6  will now be described. Referring to  FIG. 5 , if the side supplying a (+) positive voltage to  503  memory cell during an erase operation, the side will turn off a corresponding discharge transistor and the opposite side of the memory cell will couple to a common node or to a limited current source within the discharge system  501  shown in  FIG. 6 . 
         [0045]    For example, in  FIG. 5 , to erase even bits (adjacent to the even bit lines BL 0 , BL 2 , BL 4 , BL 6 , and so on) of the NROM memory cells  503 , the even metal bit lines (MBL 0 , MBL 2 , and so on) can be coupled to positive voltage sources using Y-pass gates and Y-decoders (or column decoders) for erasing the drain-side bias. The odd metal bit lines (MBL 1 , MBL 3 , and so on) can be coupled to node  602  that is or connected to a common node or current source within discharge system  501  via respective discharge transistors. To erase odd bits (adjacent to odd bit lines BL 1 , BL 3 , BL 5 , BL 7 , and so on) of the NROM memory cells, the odd metal bit lines (MBL 1 , MBL 3 , and so on) can be coupled to positive voltage sources using Y-pass gates and Y-decoders (or column decoders) for erasing drain-side bias. The even metal bit lines (MBL 0 , MBL 2 , and so on) can be coupled to node  601  that is or connected to a common node or a current source via respective discharge transistors. 
         [0046]    The following TABLE 5 illustrates exemplary voltage values for erasing bits in the memory array  500  of  FIG. 5  in a user mode and test mode. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                   
                 User mode 
                 Test mode 
               
             
          
           
               
                   
                 Even Bits 
                 Odd Bits 
                 Even Bits 
                 Odd Bits 
               
               
                   
               
               
                 WL 
                 VG (−3 V) 
                 VG (−3 V) 
                 VG (−3 V) 
                 VG (−3 V) 
               
               
                 MBL even 
                 VD (4~8 V) 
                 VS (501) 
                 VD (4~8 V) 
                 VS (501) 
               
               
                 MBL odd 
                 VS (501) 
                 VD (4~8 V) 
                 VS (501) 
                 VD (4~8 V) 
               
               
                 SEL 0/1 
                 11 V 
                 11 V 
                 11 V 
                 GND 
               
               
                 SBL 2/3 
                 11 V 
                 11 V 
                 GND 
                 11 V 
               
               
                 BL even 
                 VD (4~8 V) 
                 VS (501) 
                 VD (4~8 V) 
                 Floating 
               
               
                 BL odd 
                 VS (501) 
                 VD (4~8 V) 
                 Floating 
                 VD (4~8 V) 
               
               
                   
               
             
          
         
       
     
         [0047]    Referring to Table 5, during user mode erase operation, the memory cells  503  at the drain node are coupled to a positive pump circuit and the memory cells  503  at the source node are coupled to a common node or a limited current source by the discharge system  501  (e.g., the select inputs SEL 0  to SEL 3  all turn-on). By coupling the source node of two or more memory cells together to a common node, the source-side voltage of every NROM cell in memory array which be erased are balanced and identical among themselves, thereby providing a proper level that may be high enough to prevent punch through and low enough to maintain the lateral electric field for erase operations. 
         [0048]    In this manner, the erase uniformity across the memory cells of the memory array  500  is improved. During test mode for an erase operation, the memory cells at the source node are separated and kept floating by having half of the select inputs SEL 0  to SEL 3  on and the other half off. Therefore, during test mode erase operation the source-side (BLn) voltage of every column of NROM memory cell may be different due to bit-line coupling or leakage current caused by marginal defects, such as buried drain oxide breakdown, source-drain leakage, and so forth. The source-side voltage different of memory cell will caused the erase ability and speed non-uniform. This allows for easy screening of hard defects of the memory cells performing unsatisfactory erase operations. 
         [0049]      FIG. 7  illustrates one example of a flow diagram  700  to screen for marginal memory cells performing defective erase operations. Initially, the whole memory array is pre-programmed to “0” (step  702 ). Next, the whole memory array is erased with test mode erase bias (step  704 ). After the erase operation, each memory block is verified (step  706 ). If any block verification fails, a determination is made if it was the last block. If yes, operation  700  returns to step  704 . If not, operation  700  returns to step  706 . 
         [0050]    At step  706 , if any block verification passes, the whole memory blocks the threshold voltage (VT) distribution is checked and the erase-stubborn bits are screened out (step  708 ). Through the screening process, a defective or marginal cell, which may include a cell that is not aligned with other cells in operational characteristics, may be identified. A defective or marginal cell may be replaced with a dummy cell or back-up cells that is available to a memory array, such as by rewiring the dummy or back-up cell to become part of the array. Therefore, the operational integrity or uniformity of the array may be achieved. 
         [0051]    Referring to  FIG. 8 , an exemplary threshold voltage (VT) distribution is shown where the Vt distribution for marginal cells deviates from the non-marginal cells. EV stands for erase verify WL voltage, RD stands for read WL voltage, and PV stands for programming verify WL voltage. 
         [0052]      FIG. 9  illustrates another example flow diagram  900  to screen for marginal memory cells performing defective erase operations. Initially, the whole memory array is pre-programmed to “0” (step  902 ). Next, the whole array is erased using “N” shots, e.g. by injecting holes. The memory blocks are checked by the VT distribution, as shown in  FIG. 8 , and the erase-stubborn bits are screened out from the non-erase-stubborn bits. 
         [0053]    Thus, NROM memory devices and methods to improve erase uniformity and to screen for marginal memory cells have been described. In the foregoing specification, the invention has been described with reference to specific examples and embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.