Abstract:
A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate). Since no wire bonds are required, the resulting package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application is related to Application No. [Attorney Docket No. 7573 US] and Application No. [Attorney Docket No. 7791 US, both of which were filed by the same applicants on the same date as this application and both of which are incorporated herein by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    After the processing of a semiconductor wafer has been completed, the resulting integrated circuit (IC) chips or dice must be separated and packaged in such a way that they can be connected to external circuitry. There are many known packaging techniques. Most involve mounting the die on a leadframe, connecting the die pads to the leadframe by wire-bonding or otherwise, and then encapsulating the die and wire bonds in a plastic capsule, with the leadframe left protruding from the capsule. The encapsulation is often done by injection-molding. The leadframe is then trimmed to remove the tie bars that hold it together, and the leads are bent in such a way that the package can be mounted on a flat surface, typically a printed circuit board (PCB).  
           [0003]    This is generally an expensive, time-consuming process, and the resulting semiconductor package is considerably larger than the die itself, using up an undue amount of scarce “real estate” on the PCB. In addition, wire bonds are fragile and introduce a considerable resistance between the die pads and the leads of the package.  
           [0004]    The problems are particularly difficult when the device to be packaged is a “vertical” device, having terminals on opposite faces of the die. For example, a power MOSFET typically has its source and gate terminals on the front side of the die and its drain terminal on the back side of the die. Similarly, a vertical diode has its anode terminal on one face of the die and its cathode terminal on the opposite face of the die. Bipolar transistors, junction field effect transistors (JFETs), and various types of integrated circuits (ICs) can also be fabricated in a “vertical” configuration.  
           [0005]    Accordingly, there is a need for a process which is simpler and less expensive than existing processes and which produces a package that is essentially the same size as the die. There is a particular need for such a process and package that can be used with semiconductor dice having terminals on both their front and back sides.  
         SUMMARY OF THE INVENTION  
         [0006]    The process of fabricating a semiconductor device package in accordance with this invention begins with a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines. Each die comprises a semiconductor device. A surface of the front side of each die comprises a passivation layer and at least one connection pad in electrical contact with a terminal of the semiconductor device. The back side of each die may also be in electrical contact with a terminal of the semiconductor device.  
           [0007]    The process comprises the following steps: attaching a conductive substrate to a back side of the wafer; cutting through the wafer along a scribe line to form a first cut, the first cut exposing the conductive substrate and a side edge of a die, a kerf of the first cut having a first width W 1 ; forming a metal layer which extends from the portion of the conductive substrate exposed by the first cut, along the side edge of the die, and onto at least a portion of the passivation layer; cutting through the conductive substrate along a line that corresponds to the scribe line to form a second cut, a kerf of the second cut having a second width W 2  that is smaller than the first width Wl such that at least a portion of the metal layer remains on the side edge of the die and forms a part of a conductive path between the conductive substrate and a location on the front side of the die.  
           [0008]    The process may also include forming at least one additional metal layer in electrical contact with the at least one connection pad. Forming the metal layer may include depositing several sublayers.  
           [0009]    Form the metal layer may comprise, for example, depositing a metal sublayer on the front side of the die, the side edge of the dice and the exposed portion of the conductive substrate; depositing a mask layer; patterning the mask layer; removing a portion of the mask layer so as form an opening that exposes a first portion of the metal sublayer, a remaining portion of the mask layer covering a second portion of the metal sublayer, the second portion of the metal sublayer being in contact with the conductive substrate and the side edge of the die; removing the first portion of the metal sublayer; and removing the remaining portion of the mask layer.  
           [0010]    This invention also includes a process for making an electrical connection between a first side of a semiconductor die and a location on a second side of the semiconductor die, the process commencing while the die is a part of a semiconductor wafer. The process comprises attaching a conductive substrate to the first side of the wafer; cutting through the semiconductor wafer from the second side of the wafer to expose a part of the conductive substrate; forming a metal layer extending laterally from the location on the second side of the die along an edge of the die to the exposed part of the conductive substrate; and cutting through the conductive substrate while leaving intact a region of contact between the metal layer and the conductive substrate.  
           [0011]    According to another aspect, this invention includes a package for a semiconductor device comprising: a die containing a semiconductor device, a front side of the die comprising a passivation layer and a connection pad, the connection pad being in electrical contact with the semiconductor device; a conductive plate attached to a back side of the die, the conductive plate extending beyond a side edge of the die to form a protruding portion of the conductive plate; and a metal layer extending from the protruding portion of the conductive plate, along the side edge of the die and onto the passivation layer, the metal layer being electrically insulated from the connection pad.  
           [0012]    According to yet another aspect, this invention also includes a semiconductor structure comprising a conductive substrate; a plurality of semiconductor dice attached to the substrate, rows of the dice being separated from each other by a plurality of parallel trenches, a passivation layer on a front side of each die; and a metal layer lining the bottoms and walls of the trenches and extending onto the passivation layer  
           [0013]    Semiconductor packages according to this invention do not require an epoxy capsule or bond wires; the substrate attached to the die serves to protect the die and act as a heat sink for the die; the packages are very small (e.g., 50% the size of molded packages) and thin; they provide a very low on-resistance for the semiconductor device, particularly if the wafer is ground thinner; they are economical to produce, since they require no molds or lead frames; and they can be used for a wide variety of semiconductor devices such as diodes, MOSFETs, JFETs, bipolar transistors and various types of integrated circuit chips.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    This invention will be better understood by reference to the following drawings (not drawn to scale), in which similar components are similarly numbered.  
         [0015]    [0015]FIG. 1 illustrates a top view of a semiconductor wafer.  
         [0016]    FIGS.  2 A- 2 B,  3 ,  4 ,  5 , and  6 A- 6 B through  12 A- 12 B illustrate the steps of a process of fabricating a semiconductor package in accordance with this invention.  
         [0017]    [0017]FIG. 13A illustrates a bottom view of a semiconductor package in accordance with this invention.  
         [0018]    [0018]FIG. 13B illustrates a cross-sectional view of the semiconductor package.  
         [0019]    [0019]FIG. 14 illustrates a cross-sectional view of a semiconductor package in accordance with this invention wherein solder balls are used to make the electrical connections between the package and a printed circuit board.  
     
    
     DESCRIPTION OF THE INVENTION  
       [0020]    [0020]FIG. 1 shows a top view of a semiconductor wafer  100  which contains dice  100 A,  100 B through  100 N. The individual dice are separated by a perpendicular network of scribe lines, with scribe lines  108  running in the Y direction and scribe lines  110  running in the X direction. Metal pads for connecting to external circuit elements are located on the top surface of each of the dice  100 A- 100 N. For example, since dice  100 A- 100 N contain vertical power MOSFETs, each die has a source connection pad  106 S and a gate connection pad  106 G.  
         [0021]    Wafer  100  is typically has a thickness in the range of 15-30 mils. Wafer  100  is typically silicon but it could also be another semiconductor material such as silicon carbide or gallium arsenide.  
         [0022]    As described above, before dice  100 A- 100 N can be used they must be packaged in a form that allows them to be connected to external circuitry.  
         [0023]    The process of this invention is illustrated in FIGS.  2 A- 2 B,  3 ,  4 ,  5 , and  6 A 6 B through  12 A- 12 B, which show two dice  100 A and  100 B that are part of a semiconductor wafer  100 . While only two dice are shown for purposes of explanation, it will be understood that wafer  100  would typically include hundreds or thousands of dice.  
         [0024]    In each drawing where applicable, the figure labeled “A” is a top or bottom view of the wafer; the figure labeled “B” is an enlarged cross-sectional view taken at the section labeled “B-B” in the “A” figure. As described below, in the course of the process the wafer is attached to a conductive plate, the back side of the wafer facing the conductive plate. In the finished package the wafer is normally positioned under the conductive plate, although at some points in the process the structure may be inverted, with the conductive plate under the wafer. Unless the context clearly indicates otherwise, as used herein “above”, “below”, “over”, “under” and other similar terms refer to the package in its finished form with the conductive plate above the wafer.  
         [0025]    This invention will be described with respect to a package for a vertical power MOSFET, which typically has source and gate terminals on its front side and a drain terminal on its back side. It should be understood, however, that the broad principles of this invention can be used to fabricate a package for any type of semiconductor die which has one or more terminals on both its front and back sides or on its front side alone. As used herein, the “front side” of a die or wafer refers to the side of the die or wafer on which the electrical devices and/or a majority of the connection pads are located; “back side” refers to the opposite side of the die or wafer. The directional arrow labeled “Z” points to the front side of the wafer and identifies the drawings in which the wafer is inverted.  
         [0026]    Referring to FIGS.  2 A- 2 B, since dice  100 A and  100 B contain power MOSFETs (shown symbolically), each die has a gate metal layer  102 G and a source metal layer  102 S overlying the top surface of the silicon or other semiconductor material. Gate metal layer  102 G and source metal layer  102 S are in electrical contact with the gate and source terminals (not shown), respectively, of the power MOSFETs within dice  100 A and  100 B. In FIG. 2A, the separation between layers  102 G and  102 S is shown by the dashed lines.  
         [0027]    Typically, metal layers  102 G and  102 S include aluminum, although copper layers are also being used. In most embodiments of this invention, metal layers  102 G and  102 S need to be modified so that they will adhere to a solder metal such as tin/lead, for the reasons described below. If there is a native oxide layer on the metal, this native oxide layer must first be removed. Then a solderable metal, such as gold, nickel or silver, is deposited on the exposed metal. The removal of the oxide layer and deposition of a solderable metal can be accomplished by means of a number of known processes. For example, an aluminum layer can be sputter-etched to remove the native aluminum oxide layer and then gold, silver or nickel can be sputtered onto the aluminum. Alternatively, the die can be dipped in a liquid etchant to strip away the oxide layer and the solderable metal can then be deposited by electroless or electrolytic plating. Electroless plating includes the use of a “zincating” process to displace the oxide, followed by the plating of nickel to displace the zincate.  
         [0028]    In one embodiment metal layers  102 G and  102 S include a 3 μm sublayer of Al overlain by a 1,000 Å TiN sublayer and a 500 Å Ti sublayer.  
         [0029]    A passivation layer  104  overlies a portion of gate metal layer  102 G and source metal layer  102 S. Passivation layer  104  can be formed of phosphosilicate glass (PSG) 1 μm thick, for example, or polyimide or nitride. Openings in passivation layer  104  define a gate connection pad  106 G and source connection pads  106 S.  
         [0030]    Dice  100 A and  100 B are separated by a Y-scribe line  108 , which can be 6 mils wide. X-scribe lines  110  perpendicular to scribe line  108  at the top and bottom of dice  100 A and  100 B can be 4 mils wide.  
         [0031]    Wafer  100  can initially be ground from its backside  112  to a thickness T (about 8 mils, for example), as shown in FIG. 3. The grinding may be performed using a grinding machine available from Strausbaugh. During the grinding the front side of wafer  100  is typically taped. Grinding reduces the resistance to current flow from the front side to the back side of the wafer.  
         [0032]    As an alternative to grinding, wafer  100  can be thinned by lapping or etching the back side of the wafer.  
         [0033]    As shown in FIG. 4, a metal layer  114  is then formed on the backside  112  of wafer  100 . For example, metal layer  114  can include a 500 Å titanium sublayer overlain by a 3,000 Å nickel sublayer and a 1 μm silver sublayer. The titanium, nickel and silver sublayers can be deposited by evaporation or sputtering. Metal layer  114  is used to provide good adhesion to the silver-filled epoxy, described below.  
         [0034]    Next, as shown in FIG. 5, a metal plate  116  is attached to metal layer  114  and the backside of the wafer  100 , using a layer  115  of a conductive cement such as conductive silver-filled epoxy or metallic cement. Metal plate can be copper or aluminum and can be  6  mils thick, for example.  
         [0035]    As shown in FIGS.  6 A- 6 B, wafer  100  is cut, using a conventional dicing saw, along the Y-scribe line  108 . In this case the kerf W 1  of the cut is the same as the width of the scribe line (6 mils). The cut is made just deep enough to expose a surface  118  of the metal plate  116  as well as side edges  120  of the dice  100 A and  100 B. In this embodiment, no cut is made along X-scribe lines  110  at this point in the process.  
         [0036]    A 500 Å titanium sublayer  122  is then sputtered on the front side of wafer  100 , covering the passivation layer  104 , the connection pads  106 G and  106 S, the exposed surface  118  of metal plate  116 , and the side edges  120  of dice  100 A and  100 B. A 1 μm aluminum sublayer is  123  then sputtered on top of titanium sublayer  122 . Sublayers  122  and  123  are shown in FIGS.  7 A- 7 B.  
         [0037]    Next a photoresist mask layer  124  is deposited over sublayers  122  and  123 . Photoresist mask layer  124  is patterned, using conventional photolithographic methods, and a portion of layer  124  is removed, yielding the pattern shown in FIGS.  8 A- 8 B. As shown, the portions of photoresist layer  124  that remain cover the connection pads  106 G and  106 S, the surface  118  of metal plate  116 , the side edges  120  of dice  100 A and  100 B, and a portion of passivation layer  104  adjacent the side edges  120  of dice  100 A and  100 B. Photoresist layer  124  is also left in place over a portion of passivation layer  104 .  
         [0038]    Sublayers  122  and  123  are then etched through the openings in photoresist layer  124 , using a wet chemical etchant. The remaining portions of photoresist layer  124  are stripped. In the resulting structure, shown in FIGS.  9 A- 9 B, portions of sublayers  122  and  123  remain on the connection pads  106 G and  106 S. These portions are designated  122 G,  123 G and  122 S,  123 S, respectively. Another portion of sublayers  122  and  123 , designated  122 D,  123 D, extends from the exposed surface  118  of metal plate  116 , up the side edges  120  of dice  100 A and  100 B, and onto a portion of passivation layer  104 . Portions  122 G,  123 G and  122 S,  123 S and  122 D,  123 D of metal layers  122 ,  123  are electrically insulated from each other.  
         [0039]    A nickel sublayer  126 , for example 10 μm thick, is then deposited on the remaining portions of sputtered aluminum sublayer  123 , preferably by electroless plating. A gold sublayer  127 , which can be 0.1 μm thick, is then electrolessly plated onto nickel sublayer  126 . The resulting structure is illustrated in FIGS.  10 A- 10 B. Sublayers  126 ,  127  are divided into portions  126 S,  127 S which overlie portions  122 S,  123 S and are in electrical contact with the source pads  106 S; portions  126 G,  127 G which overlie portions  122 G,  123 G and are in electrical contact with the gate pads  106 G; and portions  126 D,  127 D which overlie portions  122 D,  123 D and are in electrical contact with the drain terminal of the device. Portions  126 S,  127 S and  126 G,  127 G and  126 D,  127 D are electrically insulated from each other. As an alternative, sublayer  126  may also be copper deposited by electroplating.  
         [0040]    As shown in FIGS.  10 A- 10 B, sublayers  122 ,  123 ,  126  and  127  together form a metal layer  129 . As will be apparent to those skilled in the art, in other embodiments metal layer  129  can contain fewer or more than four sublayers. Moreover, metal layer  129  can contain fewer or more than two sputtered layers and fewer or more than two plated layers. The sublayers may also be deposited by other processes such as evaporation, electroless or electrolytic plating, stencil-printing or screen-printing. Sublayers  122 ,  123 ,  126  and  127  are sometimes referred to herein collectively as metal layer  129 .  
         [0041]    At this stage of the process there exists semiconductor structure comprising a conductive substrate, represented by metal plate  116 ; a plurality of semiconductor dice  100 A- 100 N attached to the substrate. Rows of the dice are separated from each other by parallel trenches, the trenches being represented by the cuts extending through the wafer  100 , a front side of each die comprising a passivation layer  104 ; and a metal layer  129  lining the bottoms and walls of the trenches and extending onto the passivation layers.  
         [0042]    Optionally, a layer  130  of solder paste is then stencil or screen printed on at least a portion of the horizontal surfaces of metal layer  129 . The solder paste is reflowed to produce the gate solder posts  128 G, the source solder posts  128 S and the drain solder posts  128 D shown in FIGS.  11 A- 11 B. Solder posts  128 S,  128 S and  128 D are electrically insulated from each other.  
         [0043]    As shown in FIGS.  12 A- 12 B, dice  100 A and  100 B are detached by sawing through metal plate  116  in the Y-direction. The saw blade is selected such that the kerf W 2  of the cut is less than kerf W 1  of the cut that was previously made to separate dice  100 A and  100 B. Since W 1  was 6 mils, W 2  could be 2 mils, for example. As a result the portion of metal layer  129  that extends up the side edges  120  of dice  100 A and  100 B remains in place and forms a part of an electrical connection between metal plate  116  and the drain solder posts  128 D.  
         [0044]    Dice  100 A and  100 B are then separated from the neighboring dice in the Y direction by cutting wafer  100  and metal plate  116  along the X-scribe lines  110 , using a dicing saw. Alternatively, dice  100 A and  100 B can be separated from the neighboring dice in the Y direction by photolithographic patterning and etching.  
         [0045]    A bottom view of the resulting semiconductor device package  140  is shown in FIG. 13A, and a cross-sectional view of package  140  is shown in FIG. 13B. Package  140  comprises die  100 A, which has been inverted as compared with FIG. 12B. A front side of die  100 A comprises connection pad  106 S in electrical contact with the semiconductor device (e.g., a MOSFET) within die  100 A and passivation layer  104 . Package  140  also includes conductive plate  116 , a back side of die  100 A being attached to conductive plate  116 . Conductive plate  116  has a width X 2  greater than a width X 1  of die  100 A such that conductive plate  116  extends beyond a side edge  120  of the die  100 A to form an protruding portion  142  of conductive plate  116 . A flange portion of metal layer  144  is in contact with the protruding portion  142  of the conductive plate  116 , and metal layer  144  extends from the protruding portion  142 , along the side edge  120  of the die  100 A and onto the passivation layer  104 . The metal layer  144  is in electrical contact with the drain terminal of the MOSFET but is electrically insulated from source connection pads  102 S and gate connection pads  102 G. A second metal layer  146  is in electrical contact with source connection pads  102 S but electrically insulated from gate connection pads  102 G and the drain terminal of the MOSFET and a third metal layer  148  is in electrical contact with gate connection pads  102 G but electrically insulated from source connection pads  102 S and the drain terminal of the MOSFET.  
         [0046]    Package  140  can easily be mounted on, for example, a PCB using solder posts  128 S and  128 D. Solder post  128 G is not shown in FIG. 13B but it too would be connected to the PCB so that the source, gate, and drain terminals of the MOSFET would be connected to the external circuitry. The drain terminal is on the back side of die  100 A and is electrically connected via conductive plate  116 . Package  140  contains no wire bonds and, as has been shown, can be manufactured in a batch process using the entire wafer.  
         [0047]    [0047]FIG. 14 shows a cross-sectional view of a package  150  which is similar to package  140 , except that solder balls  152 S,  152 D and  152 G (not shown in FIG. 14) are used in place of solder posts  128 S,  128 D and  128 G. The solder balls may be applied in a conventional manner by depositing and reflowing solder paste or by other processes such as screen-printing or solder jetting (using, for example, equipment available from Pac Tech GmbH, Am Schlangenhorst 15-17, 14641 Nauen, Germany) or by using the wafer level solder ball mounter available from Shibuya Kogyo Co., Ltd., Mameda-Honmachi, Kanazawa 920-8681, Japan. Conductive polymer bumps are another alternative, using for example thermosetting polymers, B-state adhesives, or thermoplastic polymers.  
         [0048]    While a specific embodiment of this invention has been described, the described embodiment is intended to be illustrative and not limiting. For example, the die may have any number of connection pads on its front side. It will be apparent to those who are skilled in the art that numerous alternative embodiments are possible within the broad scope of this invention.