Abstract:
A circuit and method for detecting if a sum of a first multibit number A of N bits and a second multibit B of N bits equals a third multibit number C of N bits prior to availability of the sum of A and B. A propagate signal, a generate signal and a kill signal are generated for each bit in the proposed sum. A zero signal is formed from these signals. The particular manner of formation of the zero signal for each bit depends upon the state of the third multibit number C for the corresponding bit and the prior bit. The zero signal is an exclusive OR of the corresponding propagate signal P n  and a kill signal K n1  of a prior bit if the current bit and the prior bit of C are &#34;00&#34;. The zero signal is an exclusive NOR of the corresponding propagate signal P n  and a generate signal G n-1  of a prior bit if the current bit and the prior bit of C are &#34;01&#34;. The zero signal is an exclusive NOR of the corresponding propagate signal P n  and a kill signal K n-1  of a prior bit the current bit and the prior bit of C are &#34;10&#34;. The zero signal is an exclusive OR of the corresponding propagate signal P n  and a generate signal G n-1  of a prior bit if the current bit and the prior bit of C are &#34;11&#34;. The sum of A and B equals C if all the zero signals are active &#34;1&#34;. The propagate signal, generate signal and kill signal of the various bits can be used to from the sum. This technique provides the equality signal before the carry of the sum can ripple through the addition.

Description:
This application is a continuation of U.S. patent application Ser. No. 08/166,370 filed Dec. 13, 1993, now U.S. Pat. No. 5,508,950, which is a divisional of U.S. patent application Ser. No. 07/922,926 filed Jul. 31, 1992, now U.S. Pat. No. 5,270,955. 
    
    
     CROSS-REFERENCE TO RELATED PATENTS AND APPLICATIONS 
     This application is related to the following U.S. Patents and patent applications: U.S. Pat. No. 4,815,019; U.S. patent application Ser. No. 07/953,637 filed Sep. 29, 1992; and U.S. patent application Ser. No. 07/923,282 filed Jul. 31, 1992 and now abandoned. 
     1. Field of the Invention 
     This invention generally relates to computer arithmetic logic units in general, and a method of detecting an arithmetic or logical computation result in particular. 
     2. Background of the Invention 
     In the field of computing, program execution branch decisions are frequently made based on the result of a previous computation. A typical computer has an arithmetic logic unit (ALU) which performs mathematical operations on two or more &#34;N&#34; bit operands where &#34;N&#34; represents the total number of bits per operand. It will also be convenient to refer to the &#34;n&#34;th bit where &#34;n&#34; is an index variable whose value is between 0 and N-1, inclusive. A typical computation result upon which branching decisions are made is the ALU=0 condition. Many times a branch will be made if the result of a computation is zero, otherwise program execution will continue at the next command, or vice versa. Heretofore in this field, tests for arithmetic computation results relied upon the actual computation results. 
     SUMMARY OF THE INVENTION 
     This invention recognizes that the timing of the zero condition (ALU=0) signal is often more critical than the computation result itself. In the preferred embodiment of the present invention, the zero condition signal will be computed before the actual computation result becomes available. 
     The preferred embodiment of the present invention produces a signal for each bit, herein known as a one-bit-zero signal, of an ALU such that the arithmetic or logic condition signal may be computed independently from the computation result. The nth one-bit-zero signal, where n is between 0 and N-1, inclusive, is preferably dependent only upon nth and n minus first (n-1)th bit of each operand. The least significant (zeroeth) one-bit-zero detector is dependent only on the zeroeth bit of each operand and a carry-in signal, C in , since an (n-1)th bit is not available for the least significant one-bit-zero detector. 
     In a preferred embodiment of the present invention, all of the one-bit-zero signals are then logically and&#39;ed to produce a global ALU=0 signal independent of the computation result. The inventive concepts described herein may be incorporated within adder designs, subtracter designs, or ALU designs. Within any of these designs, or others, the inventive concepts described herein may be utilized to detect arithmetic conditions including a computation result of &#34;0&#34; or a zero result in all bits, a computation result of &#34;1&#34; or a one result in all bits, or a subfield=&#34;0&#34; or &#34;1&#34;. Extending this logic, any selected logic result can be compared to a known value to expediently determine whether said logic result is identical to said known value. 
     In a preferred embodiment of the invention a zero detection circuit is described. The circuit comprises a set of one-bit-zero cells which receive a first operand, A, a second operand, B, and a C in , and generates a set of one-bit-zero signals, Z. A combinatorial circuit receives the set of one-bit-zero signals and provides a selected output which is a known function of the one-bit-zero signals. In a preferred embodiment, the combinatorial circuit is a logical AND function which detects a condition when all the one-bit-zero signals are positively asserted. In various embodiments of the preferred invention the one-bit-zero signals may be operable to detect a zero condition for operations of addition, subtraction, or a logic operation. Other devices, systems and methods are also disclosed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the drawings: 
     FIG. 1 is a schematic diagram of a prior art ALU=0 circuit; 
     FIG. 2 is a schematic diagram of another prior art ALU=0 circuit; 
     FIG. 3 is a partial schematic diagram of the Propagate and Generate circuitry of the prior art ALU&#39;s of FIGS. 1-2; 
     FIG. 4 is a schematic diagram of a preferred embodiment ALU=0 circuit; 
     FIG. 5 is high level schematic diagram of an adder which incorporates a preferred embodiment ALU=0 circuit; 
     FIG. 6 is a schematic diagram of the AND tree of FIG. 5; 
     FIG. 7 is a schematic diagram of a one-bit-zero cell which could be incorporated into the ALU of FIG. 5 for addition; 
     FIG. 8 is a schematic diagram of a one-bit-zero cell which could be incorporated into the ALU of FIG. 5 for subtraction; 
     FIG. 9 is a schematic diagram of a one-bit-zero cell which could be incorporated into the ALU of FIG. 5 for performing general arithmetic and logical operations; 
     FIG. 10 is a schematic diagram of a one-bit cell for detecting a &#34;one&#34; condition; 
     FIG. 11 is a schematic diagram of a SUBFIELD-0 cell, 
     FIG. 12 is a schematic diagram of a one-bit-zero cell for bit n=0 and bit n-1=1; 
     FIG. 13 is a schematic diagram of a one-bit-zero cell for bit n=1 and bit n-1=0; and 
     FIG. 14 is a schematic diagram of a one-bit-zero cell for bit n=1 and bit n-1=0. 
     Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, a prior art ALU=0 circuit 20 is schematically depicted. This ALU=0 circuit 20 receives the result outputs, R 0  through R N-1 , of the ALU 22. The ALU 22 performs a specified arithmetic operation on its operands. A 0  through A N-1  and B 0  through B N-1 . These operations may be arithmetic operations such as addition or subtraction or specified logical operations such as a logical AND or logical OR. The ALU=0 circuit 20 consists of a combinatorial logic circuit which has been depicted here as an N bit logical NOR gate 24. By definition of the NOR function, the ALU=0 output of this NOR gate 24 will be positively asserted if and only if all inputs to the NOR gate 24 is zero (hence, the computation result is zero). Typically this N bit AND gate 24 would be implemented with a network of smaller gates which would perform the same function. The difficulty with this architecture is the arithmetic or logical computation must be completed and the outputs of the ALU 22 must be available before a determination of the ALU=0 condition can be made. 
     FIG. 2 schematically depicts another prior art ALU=0 circuit 30 disclosed by Bosshart in U.S. Pat. No. 4,815,019. This ALU=0 circuit 30 actually computes ALU≠0 and operates advantageously with a carry-select lookahead ALU by deriving preliminary ALU≠0 signals for each section 32 of the ALU prior to a carry-in signal being received by that section. The preliminary ALU≠0 outputs are the outputs of OR gates 34. The OR gates 34 receive the least significant bit of their associated ALU section 32, the R≠0 signal from their associated ALU section 32, and the ALU≠0 from an earlier section OR gate 34, if applicable. Thus, the ALU≠0 ripples across the ALU through OR gates 34 as the carry signal ripples across the ALU sections 32. When the carry-in signal is received, a final comparison is made with the least significant bit of the section and the final ALU≠0 signal is generated. The R≠0 computation for any ALU section 32 is completed one gate delay after the ALU result for that section is completed. The final ALU≠0 computation is completed one gate delay after the carry-select lookahead ALU computation is complete. It is obvious to one of ordinary skill in the art that the ALU≠0 signal may be inverted to obtain an ALU=0 signal, if necessary. 
     FIG. 3 is a schematic diagram of a one-bit adder cell for prior art adders. N of these cells would be integrated with the carry-out, C n , of each cell feeding the carry-in of its next most significant neighbor. C n  of the most significant (N-1st) cell would be a C out  signal for use by other adders operating on yet more significant bits of an operand of greater than N bits. C n-1  of the least significant (zeroeth) cell would be a C in  signal supplied from the C out  signal from additional adders operating on yet less significant bits of an operand of greater than N bits. The circuit 40 serves to compute a one bit sum S n  based on the one bit operands A n  and B n , and on a carry-in signal C n-1  from a less significant one-bit cell. In the case of the least significant one-bit cell, C n-1  will be C in . This one-bit cell also generates two internal signals commonly referred to as the &#34;Generate&#34; signal, G n , and the &#34;Propagate&#34; signal, P n . The propagate cell 42 is a logical XOR gate whose function is described by the equation P n  =A n  ⊕B n , where ⊕ is the symbol for the logical XOR function. By definition of the XOR function, P n  =0 if A n ,B n  =0,0 or 1,1 and P n  =1 if A n ,B n  =0,1 or 1,0. The generate cell 44 is a logical AND gate whose function is described by the equation G n  =A n  ·B n , where · is the symbol for the logical AND function.. By definition of the AND function, G n  =0 if A n ,B n  =0,0 or 0,1 or 1,0 and G n  =1 if A n ,B n  =1,1. The one-bit sum S n  is output from another XOR gate 46 whose output is P n  ⊕C n-1 . The carry output C n  is defined as the output of an OR gate 48 whose inputs are G n  and the output of an AND gate 50. The AND gate 50 receives P n  and C n-1 . The output C n  is defined in terms of C n-1 , P n , and G n  as C n  =G n  +P n  ·C n-1 , where &#34;+&#34; is the symbol for a logical OR. In other words, a carry is generated if a generate signal (G n ) occurs OR if a propagate signal (P n ) occurs AND a carry-in (C n-1 ) is present. 
     FIG. 4 schematically illustrates a preferred embodiment ALU=0 circuit 60. FIG. 4 shows an N bit ALU-0 circuit 60 which receives inputs A 0  through A N-1 , B 0  through B N-1 , where n is between 0 and N-1, inclusive. Each of N one-bit-zero cells 62 receives inputs A n , B n  and K n-1 , where n is from 0 to N-1, inclusive. k n  is a &#34;kill&#34; signal which will be described below. Each nth one-bit-zero cell outputs a one-bit-zero signal Z n  and a &#34;kill&#34; signal K n  to be received by the next most significant (n+1) cell. A combinatorial circuit represented in FIG. 4 by an N bit AND gate 64 serves to output a single ALU=0 signal if all Z n  for n-0 to N-1 are positively asserted. This N-bit AND gate 64 would typically be effected by a network of gates of less than N bits in a manner obvious to one of ordinary skill in the art of digital logic circuit design. The advantage of this architecture is the generation of an ALU=0 signal which is available within several stages of combinatorial logic gate delays. The amount of logic gate delays is on the order of log 2  N multiplied by a gate delay, whereas the amount of delay incurred in a prior art ALU=0 detector circuit is the computation delay, which vanes from roughly 1+log 2  N to 2N multiplied by a gate delay, in addition to a combinatorial logic gate delays (log 2  N) which still must be used to decode the computation result for ALU=0. The preferred embodiment ALU=0 circuitry of FIG. 4 could be utilized within an ALU, using the ALU&#39;s existing Propagate and Generate circuitry, if available, in conjunction with new one-bit-zero, Kill, and combinatorial ALU=0 circuitry to generate the ALU=0 signals. Alternatively, the preferred embodiment circuitry could be implemented in a separate unit, using its own PGKZ (Propagate, Generate, Kill, and Zero) circuitry to receive A 0  through A N-1 , B 0  through B N-1 , and C in  thereby forming a standalone ALU=0 circuit. 
     FIG. 5 depicts, in a high level schematic diagram, a preferred embodiment circuit 70 which incorporates a preferred embodiment ALU=0 circuit. This circuit 70 receives inputs A n  and B n  for n-0 to N-1, receives a carry-in signal, C in , and outputs resultant R n  for n-0 to N-1 and ALU=0. The inputs A n  and B n  are received by a PGK section 72 which generates a Propagate signal P n , a Generate signal G n , and a Kill signal K n  for n=0 to N-1, inclusive. The P n , G n , and K n  signal definitions are defined as follows: ##EQU1## Implementations of the circuit schematically and functionally described are numerous and well known of one having ordinary skill in the art of digital circuit design. The one-bit-zero cell array 74 receives the PGK signals and generates a Zero signal Z n  based on P n  and K n-1 . For the least significant bit of the one-bit-zero array 74 K in . (described below) serves as K n-1 . The Z n  signal is described by the equation: Z n  =P n  ⊕K n-1 . By definition of the XOR (⊕) function, Z n  =0 if P n ,Z n-1  =0,0 or 1,1 and Z n  =1 if P n ,Z n-1  =0,1 or 1,0. The one-bit-zero cell array 74 passes on the PGZ (Propagate, Generate, and Zero) signals. The one-bit-zero AND tree 76 receives the Zero signals and outputs a positively asserted ALU=0 signal if all Z n  =1 (positively asserted) for n=0 to N-1, inclusive. The combinatorial logic circuit 76, preferably an AND tree, merely passes the PG signals through, unaffected. The PG signals are shown passing through the one-bit-zero AND tree 76 merely for drawing convenience. No need exists for the routing of these signals to pass through or near the AND tree 76. Still referring to FIG. 5, the adder circuit 78 receives the PG signals, and generates an operation result R n  for n=0 to N-1, inclusive, in a manner well known to one of ordinary skill in the art. For example, this adder 78 may be a carry-select lookahead adder as described by Bosshart in U.S. Pat. No. 4,815,019. Alternatively, it may be a ripple carry adder composed of N partial cells of FIG. 3, in which XOR gate 46 computes S n  from C n-1  and P n , and OR gate 48 and AND gate 50 computes C n  from P n  and G n  (n is from 0 to N-1, inclusive). The adder circuit 78 may actually perform as an arithmetic/logic circuit to generate a result for addition, subtraction, or a logical operation depending on the method used to generate P n  and G n  from the PGK generating unit 72. In the preferred embodiment of the present invention, the operation of adder circuit 78 is not dependent on the operation being performed. In the preferred embodiment, all operation-specific functions are performed within the PGK generating unit 72. The preferred embodiment adder shown in FIG. 5 further comprises an inverter 80 for receiving a C in  signal from a less significant arithmetic and logic circuit, and inverting that signal for use as K in  by the PGK generating unit 72 and the one-bit-zero cell array 74. 
     Referring now to FIG. 6, a possible embodiment carry tree 76 as mentioned above is depicted. In this embodiment of carry tree 76, N has been chosen to be 32 bits although N may be chosen to be any number. The carry tree 76 of this embodiment serves to provide a 32 bit AND function providing an ALU-0 signal from the N one-bit-zero signals, Z n . The carry tree 76 comprises a four-input AND gate 90 and four eight-input AND gates 92. As is well known in the art, these eight-input AND gates 92 could be formed from a two-input NOR gate 94 receiving the output of two four-input NAND gates 96. Furthermore, many further functional implementations of a 32 bit AND can be accomplished by one of ordinary skill in the art. 
     Referring now to FIG. 7, a first possible embodiment PGK generating circuit 72 cooperating with a possible embodiment one-bit-zero cell 74 for an adder is partially depicted. The embodiment of FIG. 7 is a one-bit PGKZ cell 100 for the nth bit of PGK generating circuit 72 and the nth bit of one-bit-zero cell array 74. The PGKZ cell 100 comprises a first and second XOR gate 102,104, an AND gate 106, and a NOR gate 108 and inputs A n , B n , and K n-1 . Outputs of this PGKZ cell 100 are P n , G n , K n , and Z n . For the least significant bit (i.e. n=0), K in  is K n-1 . As schematically depicted in the figure, the function of this cell is described by: ##EQU2## 
     Referring now to FIG. 8, a second possible embodiment PGK generating circuit 72 cooperating with a possible embodiment one-bit-zero cell 76 for a subtracter is partially depicted. The embodiment of FIG. 8 is a one-bit PGKZ cell 110 for the nth bit of PGK generating circuit 72 and the nth bit of one-bit-zero cell array 74. The PGKZ cell 110 comprises an XOR gate 112, an XNOR gate 114, a first and second NOR gate 116,118, and a first and second inverter 120,122. The PGKZ cell 110 inputs A n , B n , and K n-1 . Outputs of this PGKZ cell 110 are P n , G n , K n , and Z n . For the least significant bit (i.e. n=0), K in  is K n-1 . As schematically depicted in the figure, the function of this cell is described by: ##EQU3## 
     Referring now to FIG. 9, a third possible embodiment PGK generating circuit 72 cooperating with a possible embodiment one-bit-zero cell 76 for a general purpose ALU is partially depicted. The embodiment of FIG. 9 is a one-bit PGKZ cell 130 for the nth bit of PGK generating circuit 72 and the nth bit of one-bit-zero cell array 74. The PGKZ cell 130 comprises an XOR gate 132, a three input AND gate 134, a NAND gate 136, an OR gate 138, a first and second inverter 140,142, and a first, second, and third AND-OR-INVERT gate 144,146,148. Each of the AND-OR-INVERT gates is described functionally by a NOR function 150, and a pair of AND functions 152. The PGKZ cell 130 inputs A n , B n , K n-1 , and special ALU control signals C0, C1, C2, C3, and ARITH. Outputs of this PGKZ cell 130 are P n , G n , K n , and Z n . For the least significant bit (i.e. n-0), K in  is K n-1 . As schematically depicted in the figure, the function of this cell is described by: ##EQU4## Examination of FIG. 9 in conjunction with the above equations for P n , G n , K n , and Z n  reveals that the signal ARITH serves to select between arithmetic and logical operations. Examination of K n  reveals that if ARITH is negatively asserted, then K n  will be positively asserted regardless of other signal inputs. As the &#34;kill&#34; signal, K, is functionally opposite a &#34;carry&#34; function, K being positively asserted means that carries will not occur during logical operations. This functionality is consistent with well understood principles of logic circuit design. 
     Referring now to FIG. 10, an alternate embodiment PGK1 cell 160 of an ALU=1&#39;s circuit of an adder comprising N PGK1 cells shown schematically. This alternate embodiment PGK1 uses the Generate signal carried in from the next least significant bit (n-1st), in conjunction with the Propagate signal to assert a one-bit-one signal Z n  &#39;. This PGK1 cell 160 comprises a first and second XOR gate 162,164, a NOR gate 166, and an AND gate 168. The PGK1 cell 160 inputs A n , B n , and G n-1 . Outputs of this PGK1 cell 160 are P n , G n , K n , and Z n  &#39;. For the least significant bit (i.e. n=0), G n-1  is 0. As schematically depicted in the figure, the function of this cell is described by: ##EQU5## 
     FIG. 11 shows a SUBFIELD=0 circuit 170 which operates as the ALU circuit described above, but inputs the sum of the least significant bit (S n , n=4 in this instance) of the subfield directly into a two input NOR gate 172, and receives a SUBALU-0 which is the output of a NAND gate 174 which NAND&#39;s the remaining one-bit-zero signals of the subfield. (Z n  n=5, 6, and 7 in this instance). Generally a SUBFIELD-0 circuit is implemented by NANDing the outputs of the 1-bit zero cells for all but the LSB of the subfield, then NORing that result with the ALU output of the subfield. A SUBFIELD=1&#39;s can be implemented in an analogous manner. 
     For detecting constant values other than all 0&#39;s or all 1&#39;s, the circuit of the preferred embodiment need only be slightly modified. For example, in the adder ALU=0 embodiment the one-bit-zero signal is identified as P n  ⊕K n-1 . In other words, assuming the next less significant (n-1) bit is zero, the zero detection in the nth bit is the XOR of bit&#39;s (bit n) propagate output with the next less significant (n-1) bit&#39;s kill output. Now, the complement of the one-bit zero signal detects a one in bit n assuming bit n-1 is zero. This logic can be described by the equation P n  ⊙K n-1 . Likewise, P n  ⊕G n-1 , can be used to detect a one at bit n assuming bit n-1 is also one and P n  ⊙G n-1  detects a zero at bit n assuming bit n-1 is a one. 
     The logic above may be summarized as follows. For a detector for any desired constant output, there are a total of four patterns to search for when building the equivalent of the one-bit-zero cell to detect the required output at bit n. These reflect the two possible values required at each bit with the two possible values required at bit n-1. The equations for the four conditions are summarized in the table below: 
     
         ______________________________________bit n        bit n-1  logic equation______________________________________0            0        P.sub.n ⊕k.sub.n-10            1        P.sub.n ⊙G.sub.n-11            0        P.sub.n ⊙K.sub.n-11            1        P.sub.n ⊕G.sub.n-1______________________________________ 
    
     The circuitry for the logical equations above are as follows: FIG. 7 shows the logical circuit for the one-bit-zero cell for bit n=0 and bit n-1=0 where Z n  =P n  ⊕K n-1  ; FIG. 12 shows the logic circuit for the one-bit-zero cell for bit n=0 and bit n-1=1 where Z n  =P n  ⊙G n-1  ; FIG. 13 shows the logic circuit for the one-bit-zero cell for bit n=1 and bit n-1=0 where Z n  =P n  ⊙K n-1  ; and, FIG. 14 shows the logic circuit for the one-bit-zero cell for bit n=1 and bit n-1=1 where Z n  =P n  ⊕G n-1 . The logical circuit of FIG. 12 has the same or identical PGK section 72 as that of FIG. 7, but differs in its implementation of the one-bit-zero cell array 274 by using an EXNOR gate with inputs P n  and G n-1  to correspond with its logic equation. The logical circuit of FIG. 13 has the same or identical PGK section 72 as that of FIG. 7, but differs in its implementation of the one-bit-zero cell 374 by using an EXNOR gate to correspond with its logic equation. The logical circuit of FIG. 14 has the same or and identical PGK section 72 as that of FIG. 7, but differs in its implementation of the one-bit-zero cell array 474 by using an EXOR gate with inputs P n  and G n-1  to correspond with its logic equation. 
     For detecting a subfield equal to a arbitrary constant, all bits but the lsb of the field require one of the cells above. All their outputs are AND&#39;ed together, then this is AND&#39;ed with the requirement that the LSB of the field have the required value. This circuit is identical to the SUBFIELD=0 detector circuit of FIG. 7, with the exception that the one-bit-zero cells are replaced with the cells from the table above, and that the LSB may be required to be one rather than zero. 
     The table, below, describes the drawing elements used in the specification hereinabove. 
     
                       TABLE______________________________________               PreferredDrawing Generic     or Specific  AlternateElement Term        Term         Terms______________________________________20      Prior Art   ALU = 0 C.sub.in22      Arithmetic  ALU   Logic Unit24      Combinatorial               N bit logical                            NOR gate   Logic Circuit               NOR gate30      Prior Art   Carry-select   ALU = 0     Lookahead   Circuit     ALU = 0 Circuit32      Arithmetic  ALU Section   Logic Unit   Section34      OR gate40      Prior Art One-   bit Adder Cell42      Propagate Cell               XOR gate44      Generate Cell               AND gate46      Sum Cell    XOR gate48      OR gate     OR gate50      AND gate60      Preferred   N bit ALU = 0   Embodiment  Circuit   ALU = 0   Circuit62      One-bit-zero   Cell64      Combinatorial               N bit AND Gate   Circuit70      Preferred   Embodiment   Adder72      PGK Section PGK Circuitry74      One-bit-zero   Cell Array76      One-bit-zero               AND Tree   AND Tree78      Adder Unit  Adder        Carry-look-                            ahead Adder,                            Ripple Carry                            Adder80      Inverter90      Four-input   AND Gate92      Eight-input   AND Gate94      Two-input   NOR Gate96      Four-input   NAND Gate100     Adder PGKZ  Adder One-bit   Cell        PGKZ Cell102,104 XOR Gate106     AND Gate108     NOR Gate110     Subtracter  Subtracter One-   PGKZ Cell   bit PGKZ Cell112     XOR Gate114     XNOR Gate116,118 NOR Gate120,122 Inverter130     ALU PGKZ   Cell132     XOR Gate134     AND Gate    Three-input               AND Gate136     NAND Gate138     OR Gate140,142 Inverter144,146,148   AND-OR-   INVERT Gate150     NOR Function               NOR Gate152     AND Function               AND Gate160     PGK1 Cell   Adder ALU = 1               PGK Cell162,164 XOR Gate166     NOR Gate168     AND Gate170     Subfield = 0   Circuit172     NOR Gate174     NAND GateA       First Operand               N bit First               OperandB       Second      N bit Second   Operand     OperandA.sub.n nth Bit of First   OperandB.sub.n nth Bit of Sec-   ond OperandZ.sub.n nth One-Bit-               nth Zero Signal   Zero SignalP.sub.n Propagate   nth Propagate   Signal      SignalG.sub.n Generate Signal               nth Generate               SignalK.sub.n Kill Signal nth Kill SignalK.sub.n-1   Kill-in Signal               n Minus First                            K.sub.in - Kill-in               Kill Signal  to LSBS.sub.n Sum Signal  nth Sum SignalC.sub.n-1   Carry-in Signal          C.sub.in - Carry-in                            to LSBC.sub.n Carry-out                C.sub.out - Carry-out   Signal                   from MSBALU = 0 Arithmetic  ALU = 0 Signal                            ALU = 0   Zero Condi-              Output   tion SignalPGZ     PGZ Signal  Propagate, Gen-               erate, and Carry               SignalsPGKZ    PGKZ Signal Propagate, Gen-               erate, Kill and               Zero SignalsPG      PG Signal   Propagate and               Generate SignalsPGK     PGK Signal  Propagate, Gen-               erate and Kill               SignalC0      ALU Control   SignalC1      ALU Control   SignalC2      ALU Control   SignalC3      ALU Control   SignalARITH   ALU Control Arithmetic/   Signal      Logical Select               SignalZ.sub.n &#39;   ALU = 1     nth ALU = 1   Signal      Signal______________________________________ 
    
     A few preferred embodiments have been described in detail hereinabove. It is to be understood that the scope of the invention also comprehends embodiments different from those described, yet within the scope of the claims. Words of inclusion are to be interpreted as nonexhaustive in considering the scope of the invention. 
     While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, logic circuits are envisioned in TTL, CMOS, NMOS, ECL, Bi-CMOS, BIPOLAR or any of many other logic families. The circuitry envisioned herein might be incorporated as a part of a larger integrated circuit design, or could stand alone as a single integrated circuit design. It is therefore intended that the appended claims encompass any such modifications or embodiments.