Abstract:
The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to the architecture of a phase-change nonvolatile memory array.  
           [0003]    2. Description of the Related Art  
           [0004]    As is known, phase-change memory (PCM) arrays are based on storage elements that use a class of materials which have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous, disorderly phase to a crystalline or polycrystalline, orderly phase, and the two phases are associated to considerably different values of resistivity.  
           [0005]    At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase-change cells. The chalcogenide that currently offers the most promise is formed by a Ge, Sb and Te alloy (Ge 2 Sb 2 Te 5 ) and is widely used for storing data in overwritable disks.  
           [0006]    In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa. The characteristics of the chalcogenides in the two phases are shown in FIG. 1. As may be noted, at a given read voltage, here designated by Vr, there is a variation in resistance of more than 10.  
           [0007]    Phase change may be obtained by locally increasing the temperature, as shown in FIG. 2. Below 150° C. both phases are stable. Above 200° C. (nucleation starting temperature, designated by T x ), there takes place fast nucleation of the crystallites, and, if the material is kept at the crystallization temperature for a sufficient length of time (time t 2 ), it changes its phase and becomes crystalline. To bring the chalcogenide back into the amorphous state, it is necessary to raise the temperature above the melting temperature T m  (approximately 600° C.) and then to cool the chalcogenide off rapidly (time t 1 ).  
           [0008]    From the electrical standpoint, it is possible to reach both the critical temperatures, namely the crystallization temperature and the melting point, by causing a current to flow through a resistive element which heats the chalcogenic material by the Joule effect.  
           [0009]    The basic structure of a phase-change storage element  1  which operates according to the principles described above is shown in FIG. 3 and comprises a resistive element  2  (heater) and a programmable element  3 . The programmable element  3  is made with a chalcogenide and is normally in the crystalline state in order to enable a good flow of current. One part of the programmable element  3  is in direct contact with the resistive element  2  and forms a phase-change portion  4 .  
           [0010]    If an electric current having an appropriate value is made to pass through the resistive element  2 , it is possible to heat the phase-change portion  4  selectively up to the crystallization temperature or to the melting temperature and to cause phase change.  
           [0011]    The state of the chalcogenic material can be measured by applying a sufficiently small voltage, such as not to cause a sensible heating, and by then reading the current that is flowing. Given that the current is proportional to the conductivity of the chalcogenide, it is possible to discriminate wherein state the chalcogenide is.  
           [0012]    Of course, the chalcogenide can be electrically switched between different intermediate states, thus affording the possibility of obtaining a multilevel memory.  
           [0013]    In practice, a phase-change memory element or PCM storage element  1  can be considered as a resistor which conducts a different current according to its phase. In particular, the following convention is adopted: a phase-change storage element is defined as “set” when, once it is appropriately biased, it conducts a detectable current (this condition may be associated to a logic condition “1”) and as “reset” when, in the same biasing conditions, it does not conduct current or conducts a much lower current than that of a cell that is set (logic condition “0”).  
           [0014]    The use of PCM storage elements has already been proposed in memory arrays formed by a plurality of memory cells arranged on rows and columns. In order to prevent the memory cells from being affected by noise caused by adjacent memory cells, generally each memory cell comprises a PCM storage element of the type described above and a selection element, such as a MOS transistor or a diode, in series to the PCM storage element.  
           [0015]    When the selection element is a diode, each cell is connected at the intersection of two selection lines, perpendicular to one another, one of which is parallel to the rows of the memory array, while the other is parallel to the columns.  
           [0016]    When the selection element is a transistor, different solutions are known which are essentially based upon biasing the source terminal of the selection element at variable voltages that depend upon the reading or programming operation (set, reset) of the memory. For example, according to U.S. Pat. No. 6,314,014, a first terminal of the PCM storage element is biased at a biasing voltage the value of which depends upon the operation (either reading or programming) of the cell, a second terminal of the PCM storage element is connected to a drain terminal of the selection transistor, the gate terminal of the selection transistor is connected to a row line, and the source terminal of the selection transistor is connected to a column line. In practice, selection of the cell takes place via the source and gate terminals of the selection transistor. Alternatively, the drain terminal of the selection transistor can be biased at the biasing voltage, and the memory cell  1  can be coupled between the source terminal and its own column line.  
           [0017]    All the above known solutions thus entail biasing of three different terminals of the cell, and hence special biasing lines, which complicate the circuits associated to the memory array. In addition, on account of the non-zero biasing of the source region, there is a sensible body effect, which determines an increase in the threshold voltage of the selection transistor, and hence of the voltage that is to be generated and fed within the memory, of course involving additional costs.  
         BRIEF SUMMARY OF THE INVENTION  
         [0018]    An embodiment of the present invention provides an architecture for phase-change memory arrays which will overcome the disadvantages of the prior art solutions.  
           [0019]    An embodiment of the present invention is directed to a phase-change nonvolatile memory array formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.  
       
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0020]    For a better understanding of the present invention, preferred embodiments thereof are now described, purely as non-limiting examples, with reference to the attached drawings, wherein:  
         [0021]    [0021]FIG. 1 shows the current-versus-voltage characteristic of a phase-change material;  
         [0022]    [0022]FIG. 2 shows the temperature-versus-current plot of a phase-change material;  
         [0023]    [0023]FIG. 3 shows the basic structure of a PCM storage element;  
         [0024]    [0024]FIG. 4 illustrates the architecture of a memory array according to the invention;  
         [0025]    [0025]FIG. 5 shows the simplified circuit diagram of a cell connected to respective column selection elements;  
         [0026]    [0026]FIG. 6 illustrates the structure of a memory cell that can be used in the memory array of FIG. 4; and  
         [0027]    [0027]FIG. 7 illustrates a different structure of a memory cell that can be used in the memory array of FIG. 4. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]    With reference to FIG. 4, a memory array  8  comprises a plurality of memory cells  10  arranged according to rows and columns and connected to bit lines  11  (parallel to the columns of the memory array  8 ) and word lines  12  (parallel to the rows of the memory array  8 ).  
         [0029]    Each memory cell  10  is formed by a PCM storage element  15  and a selection element  16 .  
         [0030]    The PCM storage element  15  is made like the PCM storage element  1  of FIG. 3 and comprises a heating element and a programmable element (which are not illustrated).  
         [0031]    The selection element  16  is formed by an NMOS transistor, preferably of low-threshold type.  
         [0032]    In each memory cell  10 , the gate terminal of the NMOS transistor  16  is connected to the respective word line  12  having address WL n−1 , WL n , WL n+1 , . . . , the source terminal (during normal operation of the memory array  8 , namely during reading or setting and resetting operations) is connected to a ground region  18 , and the drain terminal is connected to a first terminal of the PCM storage element  15 . A second terminal of the PCM storage element  15  is connected to a respective bit line  11  having address BL n−1 , BL n , BL n+1 , . . . .  
         [0033]    In the memory array  8  it is possible to program or read a single memory cell  10  by appropriately biasing the bit line  11  and the word line  12  connected thereto. All the bit lines  11  and all the word lines  12  that are not addressed must be grounded.  
         [0034]    [0034]FIG. 5 shows a possible addressing diagram for a memory cell  10  through a column decoder  20  and a row decoder  21 . In particular, of the column decoder  20  there are shown two selection transistors  22 ,  23  connected between a supply line  24  set at Vcc and a function-selection node  25 . The selection transistors  22 ,  23  are PMOS transistors, connected in series, and are driven by address signals which supply appropriate voltages for selecting/deselecting the transistors.  
         [0035]    The function-selection node  25  is connected to a drain terminal of a function-selection transistor  26 , of NMOS type, which has a source terminal connected to a respective bit line  11 .  
         [0036]    The function-selection transistor  26  is used for selecting the operation (set/reset or read) to be carried out on the selected memory cell  10 ; thereby it receives an appropriate operation-selection signal S.  
         [0037]    [0037]FIG. 5 moreover illustrates four memory cells  10  the selection transistors  16  of which are connected to the ground region  18  through a source line  27 .  
         [0038]    In each memory cell  10 , the gate terminal of the NMOS transistor  16  is connected to a respective word line  12  coming form the row decoder  21 .  
         [0039]    The NMOS transistors  16  are preferably natural transistors, namely ones that have not undergone a step of threshold-modification implantation. Consequently, the NMOS transistors  16  have a low threshold voltage (as low as 0 V). Consequently, they require a lower voltage than standard transistors to reach a same operating point (i.e., to feed the same amount of current). The leakage currents of these transistors are not, on the other hand, important, in so far as they are limited by the selection transistors  22 ,  23  of the column decoder  21 .  
         [0040]    [0040]FIG. 6 illustrates the embodiment of a memory cell  10 . As shown, a metal bit line  11  extends in a first direction of the memory cell  10  and is in contact with a strip  30  of chalcogenic material corresponding to the programmable element  3  of FIG. 3. A resistive element  31  (preferably of TiSiN and corresponding to the resistive element  2  of FIG. 3) extends vertically and is in direct contact at the top with the strip  30  and at the bottom with a first pillar plug  32 . The first plug  32  extends as far as a surface  33   a  of a substrate  33 , and is here in contact with a drain region  34  of the N +  type. The substrate  33  is of the P type, and the portion between the drain region  34  and the source region  36  forms a channel region. A word line  12 , of polysilicon, extends on top of the substrate  33  and is insulated from the latter. A second plug  35 , of metal, connects the source region  36 , of N +  type, formed in the substrate  33 , to the ground region  18 , through the source line  27 . An insulating region  40 , of oxide, for example made using the shallow-trench technique, surrounds the area of the substrate  33  housing the cell  10 .  
         [0041]    The plugs  32 ,  35  are preferably made as tungsten local interconnections. The second plug  35  can be connected to the ground region  18  either directly, via a single source line  27 , or with the interposition of a special selector which enables selective connection of one memory cell  10  or a group of memory cells  10  to the ground region  18 . The source region  36  and the second plug  35  are preferably shared with an adjacent memory cell  10  (shown on the left in FIG. 6).  
         [0042]    The word line  12  forms the gate electrode of the NMOS transistor  16 . Its resistivity can be lowered by silicidation (for instance, with tungsten, titanium, cobalt or nickel) or using the metal-strap technique.  
         [0043]    The bit line BL is a multilayer line and comprises a barrier layer (of titanium or titanium nitride—not shown) overlaid on the strip  30  and separating the chalcogenic material of the strip  30  from the metal (for example AlCu) used for reducing the resistivity of the bit line  11 .  
         [0044]    There may moreover be provided a metal line parallel to the bit line  11  (or to the word line  12 ) for reducing their resistivity, and hence increasing the speed of access to the memory cell  10 .  
         [0045]    Furthermore, it is possible to form contacts on the source line  27  so as to simplify current sinking.  
         [0046]    [0046]FIG. 7 illustrates a different embodiment of a split-gate cell  10 ′. As may be noted, the split-gate cell  10 ′ has a symmetrical structure with respect to a vertical plane passing through the center of the first plug  32 . Consequently, the split-gate cell  10 ′ of FIG. 7 has two gate regions  12 , two source regions  36 , two second plugs  35 , and two source lines  27  which are connected to ground. The gate regions  12  are connected in parallel, as are the source regions  36 ; consequently, the split-gate cell  10 ′ is electrically equivalent to the memory cell  10  of FIG. 6.  
         [0047]    Moreover, analogously to the embodiment of FIG. 6, the two source regions  36  and the two source lines  27  may be shared with two adjacent split-gate cells  10 ′, one on the left and one on the right.  
         [0048]    The embodiment of FIG. 7 affords the advantage that no field insulation is required (insulating region  40  of FIG. 6) for insulating the drain regions  34  (on which the PCM storage element  15  is formed) of adjacent cells in the direction of the bit line  11 , since the insulation between adjacent cells is obtained due to the presence of the two gate regions  12 . There are no corners of active area within the memory array, and the defects are considerably reduced (as is the leakage caused by these defects).  
         [0049]    The split-gate cell  10 ′ of FIG. 7 is longer in the direction of the bit line  11  than the memory cell  10  of FIG. 6, but this disadvantage can be partly offset by reducing the gate width W. In fact, with the same gate width W, the output current of the split-gate cell  10 ′ is twice that of the memory cell  10  of FIG. 6.  
         [0050]    The advantages of the memory array described herein are illustrated hereinafter. In the first place, the cells are not affected by the body effect, since the source terminals of the selection transistors are connected to ground. The use of selection transistors of a low-threshold type enables driving currents of adequate values to the cells during programming; that is, it enables a reduction of the programming voltages and/or of the area occupied in the chip. Metal straps on the source line are not strictly necessary. The resulting architecture is very similar to the standard architecture in NOR-type flash memories, and consequently it is possible to use selection and accessory circuitry of a known type.  
         [0051]    Finally, it is clear that numerous modifications and variations may be made to the memory array described and illustrated herein, all falling within the scope of the invention, as defined in the attached claims.  
         [0052]    All of the above U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety.