Abstract:
A trigger circuit for triggering corresponding memory cells of a column redundant circuit includes a determining circuit for generating a determining signal according to an accessed row address, and a plurality of comparing circuits jointly electrically connected to the column redundant circuit for receiving the determining signal, each of the comparing circuits selectively generating a trigger signal to the column redundant circuit according to the determining signal and an accessed column address.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a trigger circuit of a column redundant circuit, and more particularly, to a trigger circuit for a column redundant device. 
     2. Description of the Prior Art 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic diagram illustrating a conventional column redundant device  100 . As shown in  FIG. 1 , the column redundant device  100  comprises a column redundant circuit  110  and a trigger circuit  120 . The column redundant circuit  110  is also known as a Redundant Column Selection Line (RCSL). The trigger circuit  120  comprises an activation fuse set  121 , a comparator  122  and a column address fuse set  123 . 
     The column redundant device  100  is utilized for replacing failed memory cells of a DRAM (Dynamic Random Access Memory). For example, if the memory cell in the X th  column and the Y th  row is failed, when the DRAM accesses the memory cell in the X th  column and the Y th  row, the trigger circuit  120  will trigger the column redundant circuit  110  to replace all of the memory cells in the X th  column. As a result, the DRAM will not access the failed memory cell. Therefore, the column redundant circuit  110  necessarily comprises a column of memory cells for replacing a column of memory cells having even only one failed memory cell. 
     In the trigger circuit  120 , the column address fuse set  123  is utilized for recording column addresses of the failed memory cells. As mentioned above, if the failed memory cell exists in the X th  column and the Y th  row, the column address fuse set  123  will record the column address “X”. The activation fuse set  121  is utilized for storing signals that determines if the trigger circuit  120  should be enabled (activated). If the signals stored in the activation fuse set  121  determine that the trigger circuit  120  should be enabled, the activation fuse set  121  will enable the comparator  122 . On the contrast, if the signals stored in the activation fuse set  121  determine that the trigger circuit  120  should not be enabled, the activation fuse set  121  will not enable the comparator  122 . The comparator  122  comprises an activation end, a first input end, a second input end, and an output end. The activation end of the comparator  122  is utilized for receiving signals from the activation fuse set  121  and the comparator  122  is enabled accordingly. The first input end of comparator  122  is utilized for receiving column addresses of the memory cells accessed by the DRAM. The second input end of the comparator  122  is electrically connected to the column address fuse set  123 , for receiving the recorded column addresses of the failed memory cells (i.e. the column “X”). When the comparator  122  is enabled, the comparator  122  compares the column address of the memory cell accessed by the DRAM and the recorded column address of the column address fuse set  123 . If both are the same, it means that a failed memory cell exists in the column address corresponding to the memory cell accessed by the DRAM, causing the comparator  122  generating a trigger signal to the column redundant circuit  110 . When the column redundant circuit  110  receives the trigger signal transmitted from the comparator  122 , the column redundant circuit  110  automatically replaces all of the memory cells in the X th  column. So, the DRAM accesses the memory cells replaced by the column redundant circuit  110  instead of the failed memory cells. 
     The drawback of the prior art is when there is a failed memory cell in a column of memory cells, the column redundant circuit  110  replaces the column of memory cells having a failed memory cell with a corresponding column of memory cells. In other words, if there are N failed memory cells spreading in different columns, the column redundant circuit  110  needs N columns of memory cells for replacement. However, there are other usable memory cells in the column of memory cells only having a failed memory cell to be abandoned and wasted, causing the column redundant circuit  110  needs more memory cells to work. 
     In addition, as long as the DRAM accesses data, the comparator  122  is required to compare the column address of the memory cell accessed with the recorded column addresses of failed memory cells. Since accesses for the column address in the DRAM are faster and more than that for the row address, the comparator  122  is required to compare frequently, causing considerable power consumption. 
     SUMMARY OF THE INVENTION 
     It is therefore a primary objective of the claimed invention to provide a trigger circuit of a column redundant circuit, which can saves power consumption and is more convenient for users. 
     The present invention discloses a trigger circuit for triggering corresponding memory cells of a column redundant circuit. The trigger circuit comprises a determining circuit for generating a determining signal according to an accessed row address, and a plurality of comparing circuits jointly electrically connected to the column redundant circuit for receiving the determining signal, each of the comparing circuits selectively generating a trigger signal to the column redundant circuit according to the determining signal and an accessed column address. 
     The present invention further discloses a column redundant device, which comprises a column redundant circuit and a trigger circuit. The column redundant circuit comprises a first column redundant memory cell, and a second column redundant memory cell. The trigger circuit is utilized for triggering the first or second column redundant memory cell of the column redundant circuit respectively for replacing a first failed memory cell or a second failed memory cell when a memory accesses the first memory cell or the second failed memory cell. The first failed memory cell comprises a first failed column address and a first failed row address. The second failed memory cell comprises a second failed column address and a second failed row address. The trigger circuit comprises a determining circuit for generating a determining signal according to an accessed row address, and a first comparing circuit and a second comparing circuit, jointly electrically connected to the column redundant circuit for receiving the determining signal respectively, the first comparing circuit generating a first trigger signal to the column redundant circuit according to the determining signal and an accessed column address, the second comparing circuit generating a second trigger signal to the column redundant circuit according to the determining signal and the accessed column address. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram illustrating a conventional column redundant device. 
         FIG. 2  is a schematic diagram of a column redundant device of a DRAM according to an embodiment of the present invention. 
         FIG. 3  is a schematic diagram of a determining circuit according to an embodiment of the present invention. 
         FIG. 4  is a schematic diagram of bits of the row address. 
         FIG. 5  is a schematic diagram of the column redundant circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 .  FIG. 2  is a schematic diagram of a column redundant device  200  of a DRAM according to an embodiment of the present invention. The column redundant device  200  comprises a trigger circuit  210  and a column redundant circuit  220 . The trigger circuit  210  comprises a determining circuit  221 , a comparing circuit  222 , a comparing circuit  223 , and a logic gate OR 1 . The logic gate OR 1  can be an “OR” gate. The comparing circuit  222  comprises an activation-determining module AND 1 , a comparator CMP 1 , a column address fuse set  2221  and an activation fuse set  2222 . The comparing circuit  223  comprises an inverter INV 1 , an activation-determining module AND 2 , a comparator CMP 2 , a column address fuse set  2231  and an activation fuse set  2232 . The activation-determining modules AND 1  and AND 2  can be “AND” gates. 
     The determining circuit  221  is utilized for receiving a row address of a memory cell accessed by the DRAM, and transmitting a determining signal S 1  to the activation-determining module AND 1  and the inverter INV 1  according to a failed row address data. 
     In the comparing circuit  222 , the activation-determining module AND 1  comprises two input ends and an output end. One input end of the activation-determining module AND 1  is electrically connected to an output end of the determining circuit  221 , the other input end of the activation-determining module AND 1  is electrically connected to the activation fuse set  2222 , and the output end of the activation-determining module AND 1  is electrically connected to an activation end of the comparator CMP 1 . The activation-determining module AND 1  performs “AND” operation on the determining signal S 1  and data stored in the activation fuse set  2222  for enabling the comparator CMP 1 . More precisely, only when the determining signal S 1  and data stored in the activation fuse set  2222  are both logic “1”, the comparator CMP 1  is enabled. When either of the determining signal S 1  and data stored in the activation fuse set  2222  is not logic “1”, the comparator CMP 1  is not enabled. The comparator CMP 1  comprises an activation end E, a first input end  1 , a second input end  2  and an output end O. The activation end E of the comparator CMP 1  is electrically connected to the output end of the activation-determining module AND 1 . When the activation-determining module AND 1  generates logic “1”, the comparator CMP 1  is enabled. The first input end  1  of the comparator CMP 1  is utilized for receiving a column address of a memory cell accessed by the memory. The second input end  2  of the comparator CMP 1  is electrically connected to the column address fuse set  2221 , for receiving a column address of a failed memory cell (i.e. the column “P”, or the P th  column). When the comparator CMP 1  is enabled, the comparator CMP 1  compares the column address of the memory cell accessed by the memory and the recorded column address of the failed memory cell (the column “P”). If both are the same, it means that a failed memory cell exists in the column address corresponding to the memory cell accessed by the memory, causing the comparator CMP 1  to generate a trigger signal S 2 , which is transmitted to the column redundant circuit  220  via the logic gate OR 1 . 
     In the comparing circuit  223 , the inverter INV 1  is electrically connected to the output end of the determining circuit  221 , for inverting the determining signal S 1 . The activation-determining module AND 2  comprises two input ends and an output end. One input end of the activation-determining module AND 2  is electrically connected to an output end of the inverter INV 1 , the other input end of the activation-determining module AND 2  is electrically connected to the activation fuse set  2232 , and the output end of the activation-determining AND 2  is electrically connected to the activation end of the comparator CMP 2 . The activation-determining module AND 2  performs “AND” operation on the inverted signal of the determining signal S 1  and data stored in the activation fuse set  2232  for enabling the comparator CMP 2 . More precisely, only when the determining signal S 1  is logic “0” and data stored in the activation fuse set  2232  is logic “1”, the comparator CMP 2  is enabled. In other situations, the comparator CMP 2  is not enabled. The comparator CMP 2  comprises an activation end E, a first input end  1 , a second input end  2 , and an output end O. The activation end E of the comparator CMP 2  is electrically connected to the output end of the activation-determining module AND 2 . When the activation-determining module AND 2  generates logic “1”, the comparator CMP 2  is enabled. The first input end  1  of the comparator CMP 2  is utilized for receiving a column address of a memory cell accessed by the memory. The second input end  2  of the comparator CMP 2  is electrically connected to the column address fuse set  2231 , for receiving a column address of a failed memory cell (i.e. the column “Q”, or the Q th  column). When the comparator CMP 2  is enabled, the comparator CMP 2  compares the column address of the memory cell accessed by the memory and the recorded column address of the failed memory cell (the column “Q”). If both are the same, it means that a failed memory cell exists in the column address corresponding to the memory cell accessed by the memory, causing the comparator CMP 2  to generate a trigger signal S 3 , which is transmitted to the column redundant circuit  220  via the logic gate OR 1 . 
     The logic gate OR 1  performs “OR” operation on the received trigger signals S 2  and S 3 , and accordingly generates a trigger signal S 4  to the column redundant circuit  220 . In other words, either the trigger signal S 2  or the trigger signal S 3  is generated, the column redundant circuit  220  receives the trigger signal S 4 . 
     The column address of the failed memory cell recorded in the column address fuse set  2221  and that recorded in the column address fuse set  2231  can be different (i.e. the above-mentioned columns “P” and “Q”). Namely, the comparing circuits  222  and  223  can compare memory cells in different columns respectively, and use the column redundant memory cells in the same column of the column redundant circuit  220  for replacing the failed memory cells in different columns. More particularly, memory cells of one column in the column redundant circuit  220  can be used for replacing failed memory cells in different columns. For example, if a failed memory cell exists in the 15 th  row of the column “P” and another failed memory cell exists in the 16 th  row of the column “Q”, when the DRAM accesses the memory cell in the column “P” and the 15 th  row, the column redundant circuit  220  can use a column redundant memory cell in a column corresponding to the 15 th  row to replace the memory cell in the column “P” and the 15 th  row, and when the DRAM accesses the memory cell in the column “Q” and the 16 th  row, the column redundant circuit  220  can use a column redundant memory cell in the same column corresponding to the 16 th  row to replace the memory cell in the column “Q” and the 16 th  row. As a result, compared to the prior art requiring two columns of the column redundant memory cells in this situation, the present invention only requires one column of the column redundant memory cells, so as to save memory cells used. 
     Please refer to  FIG. 3 .  FIG. 3  is a schematic diagram of the determining circuit  221  according to an embodiment of the present invention. As shown in  FIG. 3 , the determining circuit  221  can be realized with a multiplexer  2211  and a row address fuse set  2212 . The multiplexer  2211  comprises four input ends I 1 , I 2 , I 3 , and I 4 , a control end C, and an output end O. The input ends I 1 , I 2 , I 3 , and I 4  of the multiplexer  2211  are respectively utilized for receiving different bits of the row address of the memory cell the DRAM accessed. The present embodiment assumes the row address of the memory cell the DRAM accessed to be four bits for example, but number of bits is not limited. The row address fuse set  2212  is electrically connected to the control end C of the multiplexer  2211  and is utilized for providing a predefined failed row address data to the multiplexer  2211  for controlling one of the input ends I 1 , I 2 , I 3 , and I 4  of the multiplexer  2211  to electrically connect to the output end of the multiplexer  2211 , so as to transmit one bit out of the row address of the memory cells accessed by the DRAM as the determining signal S 1 . In  FIG. 3 , RA 3  represents the highest bit (the 4 th  bit) of the row address, RA 2  represents the second highest bit (the 3 th  bit) of the row address, RA 1  represents the second lowest bit (the 2 th  bit) of the row address, and RA 0  represents the lowest bit (the 1 th  bit) of the row address. The row address fuse set  2212  controls the multiplexer  2211  to transmit one bit of the row address (namely, one of RA 3 , RA 2 , RA 1 , and RA 0 ) to the output end O as the determining signal S 1 . 
     Please refer to  FIG. 4  and  FIG. 3 .  FIG. 4  is a schematic diagram of the bits of the row address. As shown in  FIG. 4 , every row has corresponding row address. For example, the row address of the 16 th  row is [1111], and values of RA 3 , RA 2 , RA 1 , and RA 0  are all 1. The row address of the 15 th  row is [1110], and values of RA 3 , RA 2  and RA 1  are all 1 except that value of RA 0  is 0. When one memory cell in the column “P” and the 15 th  row of the DRAM is failed (failed memory cell  1 ) and another memory cell in the column “Q” and the 16 th  row of the DRAM is failed (failed memory cell  2 ), the row address fuse set  2212  configures the input ends I 4  of the multiplexer  2211  electrically connected to the output end O of the multiplexer  2211 . As a result, the determining signal S 1  is RA 0 , which is utilized for distinguishing memory cells of the 16 th  row and the 15 th  row. When the memory cell accessed by the DRAM is in the 16 th  row, the determining signal S 1  is set as logic “1”. So, the comparing circuit  222  is enabled to determine if the memory cell accessed by the DRAM is in the column “P”. If so, the trigger signal S 4  is transmitted to the column redundant circuit  220  to replace the failed memory cell. When the memory cell accessed by the DRAM is in the 15 th  row, the determining signal S 1  is set as logic “0”. So, the comparing circuit  223  is enabled to determine if the memory cell accessed by the DRAM is in the column “Q”. If so, the trigger signal S 4  is transmitted to the column redundant circuit  220  to replace the failed memory cell with a memory cell in the same column but in different row. 
     Please refer to  FIG. 5 .  FIG. 5  is a schematic diagram of the column redundant circuit  220 . As shown in  FIG. 5 , the column redundant circuit  220  may be realized with memory cells in one single column. In this embodiment, there are 16 rows. That is, the column redundant circuit  220  comprises  16  memory cells in a same column. The memory cell in the 16 th  row can be utilized for replacing the failed memory cell  1 , and the memory cell in the 15 th  row can be utilized for replacing the failed memory cell  2 . Compared to the prior art, if the failed memory cells  1 , and  2  are in different columns, two columns of the column redundant memory cells are needed. But in the present invention, only one column of the column redundant memory cells is needed, such that saving cost. 
     In conclusion, in the present invention, the column redundant device can replace failed memory cell of different columns with the same column memory cell, such that saving memory cells used. Moreover, the column redundant device does not need to compare that if the column address of the memory cell accessed is the column address of the failed memory cell as long as the DRAM accesses the memory cell, which saves power consumption and is more convenient for users. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.