Abstract:
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority from Japanese Patent Application No. 2008-255638 filed on Sep. 30, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    An aspect of the present invention relates to a method of manufacturing a semiconductor device. 
         [0004]    2. Description of the Related Art 
         [0005]    As a technique for achieving a fine structure of wiring patterns or the like in a semiconductor integrated circuit or the like, there is proposed a pattern forming method in which side wall patterns are formed on side walls of core patterns formed on a target film and in which the target film masked with the side wall patterns or patterns embedded in between the side wall patterns are processed to form wiring patterns, gate electrodes, etc. (e.g. see U.S. Pat. No. 6,063,688). By such method, for example, line-and-space-shaped periodic patterns can be formed. 
         [0006]    In the periodic patterns such as line-and-space patterns, even when end patterns and a central pattern are designed to be equal, each end pattern and the central pattern are different in arrangement environment. Accordingly, each end pattern and the central pattern are different in the influence of a proximity effect caused in a manufacturing process, and there is a possibility that dimensional error may occur. 
       SUMMARY OF THE INVENTION 
       [0007]    According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns as a mask, thereby forming first patterns including: periodic patterns arranged periodically; and aperiodic patterns arranged aperiodically with respect to the periodic patterns; removing the resist patterns; forming a second film on the target film to cover the first patterns; processing the second film to reveal the target film, thereby forming second side wall patterns on side walls of the first patterns; selectively removing the periodic patterns of the first patterns to leave the aperiodic patterns of the first patterns; and processing the target film with the aperiodic patterns of the first patterns and the second side wall patterns as a mask, thereby forming a target patterns including: periodic target patterns arranged periodically; aperiodic target patterns arranged adjacent to both end parts of the periodic target patterns and arranged aperiodically with respect to the periodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with respect to the periodic target patterns. 
         [0008]    Another aspect of the present invention, there is provided a memory device including: a semiconductor substrate; a insulating film formed on the semiconductor substrate; a plurality of word lines arranged periodically; two of select gates arranged at both ends of the word lines, each select gate being arranged aperiodically with respect to the word lines; and two of dummy patterns arranged between the word lines and each select gate, each dummy pattern being arranged periodically with respect to the word lines. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIGS. 1A and 1B  illustrate a pattern in a semiconductor device according to an embodiment of the invention. 
           [0010]      FIGS. 2A to 2F  are sectional views illustrating a method of manufacturing a semiconductor device according to the embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0011]    An embodiment of the invention will be described below in detail with reference to the drawings. 
       Embodiment 
       [0012]    A semiconductor device manufacturing method according to this embodiment will be described with reference to  FIGS. 1A and 1B  and  FIGS. 2A to 2F . Forming of gate patterns of a NAND flash memory by the semiconductor device manufacturing method will be described here. 
         [0013]      FIGS. 1A and 1B  illustrate gate patterns of an NAND flash memory.  FIG. 1A  shows a plan view of the gate patterns.  FIG. 1B  shows a sectional view of the gate patterns taken along the broken line A-A′ in  FIG. 1A . 
         [0014]    As shown in  FIG. 1A , the gate patterns  1  include: line-and-space-shaped patterns  2  (line-and-space patterns  2 ) having a number X of parallel line patterns (L 1  to LX) arranged periodically with given spaces; and aperiodic patterns  3  disposed aperiodically adjacent to opposite end portions of the line-and-space patterns  2 . The line-and-space patterns  2  are functioning as word lines, and the periodic patterns  3  are functioning as select gate patterns SG 1  and SG 2 . 
         [0015]    The fact that “the select gate patterns are aperiodic” means that the select gate patterns are aperiodic relative to the line-and-space patterns  2 . Accordingly, the select gate patterns may be periodic to each other or may be periodic relative to other patterns (except dummy patterns which will be described later) than the line-and-space patterns  2 . 
         [0016]    In this embodiment, in the line-and-space patterns  2 , the line sizes (W 1  to WX) and the space sizes (S 1  to SX) are equal to one another. The line size, the space size and the number of lines can be set respectively arbitrarily. For example, the line size and the space size can be set to be in a range of from about 30 nm to about 60 nm and the number of lines can be set to be 16, 32, 64 or 128. Though not shown, extracted patterns on which contacts with upper layer wiring are to be disposed are connected to the line patterns of the line-and-space patterns  2  respectively. 
         [0017]    The distance between each select gate pattern SG 1  or SG 2  and the line-and-space patterns  2  is larger than the line size and space size of the line-and-space patterns  2 . For example, the distance between each select gate pattern SG 1  or SG 2  and the line-and-space patterns  2  can be set to be about three times as much as the line size and space size. 
         [0018]    In this embodiment, a dummy pattern  4  is provided between the line-and-space periodic patterns  2  and each aperiodic pattern  3 . The dummy patterns  4  are formed so as to be electrically independent of the periodic patterns  2  and the aperiodic patterns  3 . 
         [0019]    The dummy patterns  4  are line-shaped patterns parallel with the respective line patterns of the line-and-space patterns  2 . The dummy patterns  4  are formed adjacent to the line-and-space patterns  2 . Each dummy pattern  4  is formed distant from a corresponding end line pattern (L 1 , LX) of the line-and-space patterns  2  by the same size (SO, SX+1) as the space size (S 1  to SX) of the line-and-space patterns  2 . Accordingly, the distance between each end line pattern (L 1 , LX) of the line-and-space patterns  2  and a pattern adjacent to the end line pattern (L 1 , LX) is equalized to the distance between the central line pattern (LX/ 2 ) of the line-and-space patterns  2  and a pattern adjacent to the central line pattern (LX/ 2 ), so that the same peripheral environment is provided in each line pattern. 
         [0020]    The size of each dummy pattern  4  is equal to the size of each line pattern (L 1  to LX) of the line-and-space patterns  2 . Accordingly, the size of each end line pattern (L 1 , LX) of the line-and-space patterns  2  and the size of the central line pattern (LX/ 2 ) of the line-and-space patterns  2  are equalized to the size of a pattern adjacent to the end line pattern (L 1 , LX) and the size of a pattern adjacent to the central line pattern (LX/ 2 ), so that the same peripheral environment is provided in each line pattern. 
         [0021]    As shown in  FIG. 1B , the line-and-space patterns  2 , the select gate patterns (aperiodic patterns  3 ) and the dummy patterns  4  are formed on a semiconductor substrate  5  through a gate insulating film (not shown) and made of polysilicon materials respectively. 
         [0022]    A method of forming the gate patterns  1  of the semiconductor device shown in  FIGS. 1A and 1B  will be described below with reference to  FIGS. 2A to 2F .  FIGS. 2A to 2F  are sectional views illustrating the method of forming the gate patterns  1  of the semiconductor device shown in  FIG. 1B . 
         [0023]    First, as shown in  FIG. 2A , a target film  6  of a gate pattern material such as a polysilicon film is formed on a semiconductor substrate  5  through a gate insulating film (not shown). Then, a first film  7  of a laminated structure having a silicon oxide film  7   a  and an amorphous silicon film  7   b  is formed on the target film  6 . A resist film is formed on the first film  7  through an antireflection film (not shown) in a coating manner. Then, after a photo mask is disposed in an exposure device, a mask pattern image is formed in the resist film by the exposure device. The resist film is developed to form resist patterns  8 . 
         [0024]    The resist patterns  8  include: line-and-space patterns  9  having a number (1+X/ 2 ) of parallel line patterns arranged periodically with given spaces; and aperiodic patterns  10  disposed adjacent to the line-and-space patterns. 
         [0025]    Then, as shown in  FIG. 2B , the amorphous silicon film  7   b  masked with the resist patterns  8  is processed. Then, the resist patterns  8  are removed, and the amorphous silicon film  7   b  is subjected to slimming in an etching manner. Then, the silicon oxide film  7   a  masked with the slimmed amorphous silicon film  7   b  is processed. 
         [0026]    Like the resist patterns  8 , first patterns  11  formed in the first film  7  include: line-and-space patterns  12  having a number (1+X/ 2 ) of parallel line patterns arranged periodically; and aperiodic patterns  13  disposed adjacent to the line-and-space patterns. The line-and-space patterns  12  are formed so that the ratio of the line size to the space size is 1:3. 
         [0027]    In this embodiment, as the first film  7  formed on the target film  6 , a laminated film having a silicon oxide film  7   a  and an amorphous silicon film  7   b  is used. However, a laminated film formed of other materials such as a laminated film having a carbon film and an amorphous silicon film, a laminated film having a carbon film and an SOG film or a single layer film such as a silicon nitride film may be used as the first film  7 . 
         [0028]    In this embodiment, the amorphous silicon film  7   b  as an upper layer portion of the first film  7  is subjected to slimming. However, the amorphous silicon film  7   b  masked with the resist patterns  8  may be processed after the resist patterns  8  are subjected to slimming. In this case, the step of applying slimming to the amorphous silicon film  7   b  can be removed. 
         [0029]    Then, as shown in  FIG. 2C , a second film  14  such as an oxide film, a nitride film, etc. is formed on the target film  6  and on the first patterns  11  so that the first patterns  11  are covered with the second film  14 . 
         [0030]    Then, as shown in  FIG. 2D , the second film  14  is etched to form second side wall patterns  15  on side walls of the first patterns  11 . 
         [0031]    Then, as shown in  FIG. 2E , periodically arranged patterns  12  are selectively removed from the first patterns  11 . That is, a resist film is applied on the target film  6 , the first patterns  11  and the second side wall patterns  15 , the resist film is processed to have patterns selectively revealing the periodically arranged patterns  12  of the first patterns  11  and the second side wall patterns  15  formed on side walls thereof, and the revealed periodic patterns  12  are removed with the resist patterns. 
         [0032]    As a result of selectively removing the first patterns  11 , the second side wall patterns  15  are formed as line-and-space patterns  16  having a number (X+2) of line patterns parallel with one another and periodically arranged. The line-and-space patterns  16  are formed so that the ratio of the line size to the space size is 1:1. 
         [0033]    Finally, as shown in  FIG. 2F , the target film  6  masked with the first patterns  11  and the second side wall pattern  15  is processed to form gate patterns  1  as shown in  FIG. 1B . 
         [0034]    In this manner, line-and-space patterns  2 , as word lines, having a number X of line patterns arranged periodically and each separated from the adjacent line patterns, aperiodic select gate patterns  3  arranged adjacent to the line-and-space patterns, and electrically-independent dummy patterns  4  formed between the line-and-space patterns  2  and the select gate patterns  3  are simultaneously formed on the semiconductor substrate  5  as shown in  FIG. 1B . 
         [0035]    The dummy patterns  4  and the line-and-space patterns  2  formed in the target film  6  are formed simultaneously with the second side wall patterns  15  of periodic line-and-space patterns as a mask. The dummy patterns  4  are provided as two line patterns respectively adjacent to end line patterns of the line-and-space patterns  2  to be periodic with respect to the line-and-space patterns  2 . 
         [0036]    For this reason, the distance (space size) between each end line of the line-and-space patterns  2  and a pattern adjacent to the end line and the distance (space size) between the central line of the line-and-space patterns  2  and a pattern adjacent to the central line are equalized. Further, the size of a pattern adjacent to the end line of the line-and-space patterns  2  and the size of a pattern adjacent to the central line of the line-and-space patterns  2  are equalized. 
         [0037]    According to this embodiment, each end line of the periodic line-and-space patterns  2  and the central line of the periodic line-and-space patterns  2  have the same peripheral pattern environment. Accordingly, dimensional error caused in an etching process or the like can be suppressed. 
         [0038]    In this embodiment, the dummy patterns  4  are formed by use of the second side wall patterns  15  that are used to form fine-size target patterns in the target film  6 . As a result, the dummy patterns  4  can be formed while preventing the chip area from being increased. 
         [0039]    Generally, in the semiconductor device, two resist dummy regions are provided between periodic patterns and aperiodic patterns. For example, if two resist patterns are provided correspondingly for the two dummy regions, since two side-wall patterns are formed at both sides of one resist pattern, two dummy patterns are formed in each of the two dummy regions. 
         [0040]    In this embodiment, only one resist pattern in total is formed to provide the two dummy regions, and the one dummy pattern  4  is respectively assigned between the periodic patterns  2  and each aperiodic pattern  3 . Therefore, the area required for providing the dummy regions are reduced as compared with the above comparison example. 
         [0041]    According to this embodiment, while suppressing dimensional error of patterns, pattern area in the lithography is prevented so that chip area of the semiconductor device is suppressed. 
         [0042]    In this embodiment, formation of gate patterns of an NAND flash memory is described. However, the invention can be applied to formation of other patterns of semiconductor device. For example, when this embodiment is applied to a method of manufacturing a semiconductor device having periodic patterns and aperiodic patterns, dummy patterns can be formed therebetween.