Abstract:
An apparatus for driving a plasma display panel that includes first and second signal lines for supplying first and second voltages, respectively, and first and second inductors coupled to one terminal of a panel capacitor. A first current path is formed from the panel capacitor to the second signal line via the second inductor to drop the voltage of the panel capacitor from the first voltage to the second voltage. A second current path is formed to recover the current flowing to the second inductor towards the first signal line, while the voltage of the panel capacitor is sustained at the second voltage. A third current path is formed from the first signal line to the panel capacitor via the first inductor while the current flowing to the second inductor is recovered, to raise the voltage of the panel capacitor from the second voltage to the first voltage. A fourth current is also formed to recover the current flowing to the first inductor towards the first signal line, while the voltage of the panel capacitor is sustained at the first voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Korean Patent Application No. 2002-0030324 filed on May 30, 2002 in the Korean Intellectual Property Office, the content of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     (a) Field of the Invention 
     The present invention relates to an apparatus and method for driving a plasma display panel. More specifically, the present invention relates to an address driver circuit for a plasma display panel. 
     (b) Description of the Related Art 
     In recent years, flat panel displays such as a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and the like have been actively developed. The PDP is advantageous over the other flat panel displays in regard to its high luminance, high luminous efficiency, and wide view angle, and accordingly, it is favorable for making a large-scale screen of more than 40 inches as a substitute for the conventional cathode ray tube (CRT). 
     The PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images and includes, according to its size, more than several scores to millions of pixels arranged in a matrix pattern. Such a PDP is classified into a direct current (DC) PDP and an alternating current (AC) PDP according to its discharge cell structure and the waveform of the driving voltage applied thereto. 
     The DC PDP has electrodes exposed to a discharge space to allow DC to flow through the discharge space while voltage is applied, and thus requires a resistance for limiting the current. Contrarily, the AC PDP has electrodes covered with a dielectric layer that naturally form a capacitance component to limit the current and to protect the electrodes from the impact of ions during discharge, and is thus superior to the DC PDP in regard to long lifetime. 
     Typically, the driving method of the AC PDP is composed of a reset (initialization) step, an addressing (write) step, a sustain discharge step, and an erase step. 
     In the reset step, the state of each cell is initialized in order to readily perform an addressing operation on the cell. In the write step, wall charges are formed on selected “on”-state cells (i.e., addressed cells) in the panel. In the sustain step, a discharge occurs to actually display an image on the addressed cells. In the erase step, the wall charges on the cells are erased to end the sustain discharge. 
     In the AC PDP, the panel between address, sustain, and scan electrodes acts as a capacitance load and is therefore called a panel capacitor. Due to the capacitance of the panel capacitor, there is a need for a reactive power in order to apply a waveform for addressing or sustain discharge. A circuit for recovering the reactive power and reusing it is called a “power recovery circuit”, some of which have been suggested by L. F. Weber (in U.S. Pat. Nos. 4,866,349 and 5,081,400). 
     With the conventional power recovery circuit mounted on an address buffer board, a parasitic inductance component L p  as shown in FIG. 1 may be caused by the output pattern  10  running in the lengthwise direction of the address buffer board. In FIG. 1, the circuit on the left side of parasitic inductance component L p  is a power recovery circuit proposed by Weber, and capacitor C p  is a panel capacitor functioning as a capacitive load. 
     In detail, there is a need for a plurality of address-driving ICs in order to drive address electrodes, because all the address electrodes cannot be coupled to a single address-driving IC. With the plural address-driving ICs coupled to one power recovery circuit, a parasitic inductance component may be formed on the output pattern in which the address-driving ICs are coupled to the address buffer board. The parasitic inductance component causes an extreme distortion of the address-driving waveform. Namely, an undesired pulse rise may occur in the rise/drop interval of the address-driving waveform because of the parasitic inductance component. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention a power recovery circuit recovers a reactive power necessary for address driving and minimizes the effect of a parasitic inductance component existing in an address driver circuit. Energy is stored in both inductors and parasitic inductance components. First and second inductors have one terminal thereof coupled to both terminals of a path coupled to one terminal of a panel capacitor. 
     In a first aspect of the present invention, there is provided an apparatus for driving a PDP. A first switch and a first capacitor are coupled in series between the other terminal of the first inductor and a first power source supplying a first voltage. A second switch and a second capacitor are coupled in series between the other terminal of the second inductor and the first power source. A third switch is coupled between a second power source for supplying a second voltage and the one terminal of the first inductor. A fourth switch is coupled between the one terminal of the second inductor and the first power source. The first and second capacitors are charged to a voltage substantially corresponding to half of the second voltage. Preferably, a parasitic inductance component is formed on the path. The apparatus further includes first and second diodes respectively formed on a path including the first switch and the first inductor and a path including the second switch and the second inductor. The apparatus further includes a first diode coupled between the first power source and the other terminal of the first inductor, and a second diode coupled between the other terminal of the second inductor and the second power source. Preferably, the third and fourth switches have a body diode. 
     In a second aspect of the present invention, there is also provided an apparatus for driving a PDP. A first voltage changer changes the terminal voltage of the panel capacitor to a second voltage using the energy stored in a first inductor and a resonance. A second voltage changer changes the terminal voltage of the panel capacitor to the first voltage using the energy stored in a second inductor and the resonance. A power supply section includes first and second power sources, the first power source supplying the first voltage and sustaining the terminal voltage of the panel capacitor at the first voltage, the second power source supplying the second voltage and sustaining the terminal voltage of the panel capacitor at the second voltage. The energy is stored in the first inductor through a current path formed from the first inductor to one terminal of the panel capacitor, while a terminal voltage of the panel capacitor is sustained at a first voltage. Further, the energy is stored in the second inductor through a current path formed from one terminal of the panel capacitor to the second inductor, while the terminal voltage of the panel capacitor is sustained at the second voltage. Preferably, the apparatus further includes first and second capacitors charged to a third voltage substantially corresponding to half of the difference between the second voltage and the first voltage. The apparatus further includes a first switch being coupled between the first inductor and the first capacitor and performing a switching operation to flow a current to the first inductor; and a second switch being coupled between the second inductor and the second capacitor and performing a switching operation to flow a current to the second inductor. Preferably, the apparatus includes a first path for recovering a current flowing to the first inductor, and a second path for recovering a current flowing to the second inductor. The first voltage changer further includes a switch performing a switching operation to sustain the terminal voltage of the panel capacitor at the second voltage and having a body diode through which a current flowing to the first inductor is recovered. Likewise, the second voltage changer further includes a switch performing a switching operation to sustain the terminal voltage of the panel capacitor at the first voltage and having a body diode through which a current flowing to the second inductor is recovered. 
     In a third aspect of the present invention, there is provided a method for driving a PDP. Energy is stored in a first inductor coupled to one terminal of a path coupled to one terminal of the panel capacitor, while a terminal voltage of the panel capacitor is sustained at a first voltage. The terminal voltage of the panel capacitor is changed to a second voltage using the energy stored in the first inductor and a resonance. A current flowing to the first inductor is recovering while sustaining the terminal voltage of the panel capacitor at the second voltage. Energy is stored in a second inductor coupled to the other terminal of the path, while the terminal voltage of the panel capacitor is sustained at the second voltage. The terminal voltage of the panel capacitor is changed to the first voltage using the energy stored in the second inductor and the resonance. A current flowing to the second inductor is recovered while sustaining the terminal voltage of the panel capacitor at the first voltage. In storing the energy in the first inductor, there is used a first capacitor charged to a third voltage substantially corresponding to half of the difference between the second voltage and the first voltage. In storing the energy in the second inductor, the difference between the second voltage and the third voltage charged on the second capacitor is used. Preferably, the terminal voltage of the panel capacitor is sustained at the second voltage using a power source for supplying the second voltage, and a current flowing to the first inductor is recovered through a path formed between the first inductor and the power source. Preferably, the terminal voltage of the panel capacitor is sustained at the first voltage using a power source for supplying the first voltage, and a current flowing to the second inductor is recovered through a path formed between the power source and the second inductor. 
     In a fourth aspect of the present invention, there is further provided an apparatus for driving a PDP. A panel capacitor is coupled on a lengthwise conductive pattern and an address-driving waveform is applied to the panel capacitor. The apparatus includes first and second inductors each having one terminal thereof coupled to both terminals of the conductive pattern. Here, a first current path is formed to flow a first current through the first inductor and the conductive pattern. A second current path is formed to cause a resonance of the first inductor and the panel capacitor while the first current flows, thereby changing a voltage of the panel capacitor to a first voltage due to the resonance. A third current path is formed to recover a current remaining in the first inductor, while the voltage of the panel capacitor is sustained at the first voltage. A fourth current path is then formed to flow a second current through the conductive pattern and the second inductor. A fifth current path is formed to cause a resonance of the second inductor and the panel capacitor while the second current flows, thereby changing the voltage of the panel capacitor to a second voltage due to the resonance. A sixth current path is formed to recover a current remaining in the second inductor while the voltage of the panel capacitor is sustained at the second voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an illustration of a parasitic inductance component in a power recovery circuit according to prior art. 
     FIG. 2 is an illustration of a PDP according to an embodiment of the present invention. 
     FIG. 3 is a circuit diagram of an address driver according to an embodiment of the present invention. 
     FIGS. 4A to  4 H are illustrations showing the current paths in the respective modes according to an embodiment of the present invention. 
     FIG. 5 is a timing diagram of the PDP according to the embodiment of the present invention. 
     FIG. 6 is an illustration showing an address-driving waveform measured according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 2 is an illustration of the PDP according to an embodiment of the present invention. The PDP includes plasma panel  100 , address driver  200 , scan/sustain driver  300 , and controller  400 . 
     Plasma panel  100  includes a plurality of address electrodes A 1  to A m  arranged in columns and a plurality of scan electrodes Y 1  to Y n  and sustain electrodes X 1  to X n  alternately arranged in rows. Controller  400  receives an external image signal (e.g., a video signal), and generates an address drive control signal and a sustain discharge signal and applies them to address driver  200  and scan/sustain driver  300 , respectively. 
     Address driver  200  receives the address drive control signal from controller  400  and applies a display data signal for selection of discharge cells to be displayed to the individual address electrodes. Scan/sustain driver  300  receives the sustain discharge signal from controller  400  and applies a sustain pulse voltage alternately to the scan and sustain electrodes for a sustain discharge on the selected discharge cells. Address driver  200  and scan/sustain driver  300  include a driver circuit (i.e., a power recovery circuit) for recovering reactive power and reusing it. 
     Hereinafter, a description will be given as to the address driver according to the embodiment of the present invention with reference to FIGS. 3 to  6 . FIG. 3 is a circuit diagram of the address driver according to an embodiment of the present invention. FIGS. 4A to  4 H are illustrations showing the current paths in the respective modes according to an embodiment of the present invention. FIG. 5 is a timing diagram of the PDP according to the embodiment of the present invention. FIG. 6 is an illustration showing an address-driving waveform measured according to an embodiment of the present invention. 
     The power recovery circuit of address driver  200  according to the embodiment of the present invention is coupled to address electrodes A 1  to A m  via a plurality of address buffer ICs, and the output pattern coupled to the address buffer ICs acts as a parasitic inductance component. Address electrodes A 1  to A m  together with other electrodes X 1  to X n  and Y 1  to Y n  function as a capacitive load, which is usually denoted as a panel capacitor C p . Here, the address buffer ICs apply the voltage for addressing in the power recovery circuit only to the selected discharge cells. 
     Expediently, in FIG. 3, the address buffer ICs are not shown and the parasitic inductance component is equivalently denoted as parasitic inductors L p1  and L p2 , assuming that address voltage V a  is applied to one panel capacitor. In order to select discharge cells, a voltage is applied to the terminal of the panel capacitor other than that to which address voltage V a  is applied, and said voltage is assumed as ground voltage 0V in FIG. 3 
     As shown in FIG. 3, power recovery circuit  220  includes voltage rising unit  222 , voltage falling unit  224  and power supply section  226 . 
     Voltage rising unit  222  includes inductor L c1  coupled to panel capacitor C p  via parasitic inductor L p1 , and switch S 1  and capacitor C c1  coupled in series between inductor L c1  and the ground terminal. Voltage rising unit  222  may further include diode D 1  that determines a current path on the path formed with inductor L c1  and switch S 1 . 
     Likewise, voltage falling unit  224  includes inductor L c2  coupled to panel capacitor C p  via parasitic inductor L p2 , and switch S 2  and capacitor C c2  coupled in series between inductor L c2  and the ground terminal. Voltage falling unit  224  may further include diode D 2  that determines a current path on the path formed with inductor L c2  and switch S 2 . 
     Voltage rising unit  222  and voltage falling unit  224  may respectively further include diodes D 3  and D 4  and diodes D 5  and D 6  that determine the current path. Diode D 3  is coupled between power source V a  for supplying address voltage V a  and a contact between inductor L c1  and switch S 1 . Diode D 4  is connected between the ground terminal and the contact between inductor L c1  and switch S 1 . Diode D 5  is connected between power source V a  and a contact between inductor L c2  and switch S 2 . Diode D 6  is connected between the ground terminal and the contact between inductor L c2  and switch S 2 . 
     A contact between switch S 1  and capacitor C c1  in the voltage rising unit  222  is coupled to a contact between switch S 2  and capacitor C c2  in voltage falling unit  224 . Between panel capacitor C p  and power source V a  may be formed clamping diode D c , which prevents the voltage of panel capacitor C p  from exceeding address voltage V a  in the actual circuit. 
     Power supply section  226  includes switches S 3  and S 4 . Switch S 3  is coupled between power source V a  and panel capacitor C p  via parasitic inductor L p1 . Switch S 4  is coupled between the ground terminal and panel capacitor C p  via parasitic inductor L p2 . 
     Switches S 1 , S 2 , S 3 , and S 4  included in voltage rising unit  222 , voltage falling unit  224 , and power supply section  226  may include transistors such as MOSFETs, and each has a body diode. 
     Now, a sequential change of the operation of power recovery circuit  220  according to the embodiment of the present invention will be described with reference to FIGS. 4A to  4 H,  5 , and  6 . The operation proceeds in the order of eight modes M 1  to M 8  by the manipulation of switches S 1  to S 4 . The phenomenon called “LC resonance” hereinafter is not a continuous oscillation but a change in voltage and current caused by the combination of the inductors, the parasitic inductors, and panel capacitor C p  when switches S 1  and S 2  are turned on. 
     In the embodiment of the present invention, it is assumed that before the start of Mode  1 , capacitors C c1  and C c2  are charged to voltage V a /2 amounting to half of address voltage V a , and that switch S 4  is turned on to sustain voltage V p  between both terminals of panel capacitor C p  at 0V. 
     (1) Mode  1  (M 1 ) 
     Reference will be made to FIG.  4 A and the M 1  interval of FIG. 5 to describe the operation in Mode  1 . 
     In Mode  1 , with switch S 4  on, switch S 1  is turned on to form a current path that includes capacitor C c1 , switch S 1 , diode D 1 , inductor L c1 , parasitic inductors L p1  and L p2 , and switch S 4 . Current I LC1  flowing to inductor L c1  linearly increases due to voltage V a /2 charged on capacitor C c1 . Hence the energy is stored in inductor L c1 . This current flows to parasitic inductors L p1  and L p2  as well and the energy is also stored in parasitic inductors L p1  and L p2 . 
     (2) Mode  2  (M 2 ) 
     Reference will be made to FIG.  4 B and the M 2  interval of FIG. 5 to describe the operation in Mode  2 . 
     In Mode  2 , with switch S 1  on, switch S 4  is turned off to form a current path that includes capacitor C c1 , switch S 1 , diode D 1 , inductor L c1 , parasitic inductor L p1 , and panel capacitor C p . Due to the LC resonance formed on the current path, a resonance current flows to inductor L c1  and terminal voltage V p  of panel capacitor C p  (hereinafter referred to as “panel terminal voltage”) increases to address voltage V a . The energy stored in inductor L c1  and parasitic inductor L p1  makes panel terminal voltage V p  increase to address voltage V a  stably despite the effect of the parasitic component. 
     Current I LC2  flowing to parasitic inductor L p2  is recovered to power source V a  via inductor L c2  and diode D 5 . 
     (3) Mode  3  (M 3 ) 
     Reference will be made to FIG.  4 C and the M 3  interval of FIG. 5 to describe the operation in Mode  3 . 
     The panel terminal voltage V p  cannot exceed address voltage V a  due to the body diode of switch S 3 . When panel terminal voltage V p  reaches address voltage V a , switch S 3  is turned on. With switch S 3  on, panel terminal voltage V p  is sustained at address voltage V a  due to power source V a . Current I LC1  flowing to inductor L c1  linearly decreases to 0A through a current path that includes capacitor C c1 , switch S 1 , diode D 1 , inductor L c1 , and the body diode of switch S 3 . Namely, this current is recovered to power source V a . 
     (4) Mode  4  (M 4 ) 
     Reference will be made to FIG.  4 D and the M 4  interval of FIG. 5 to describe the operation in Mode  4 . 
     In Mode  4 , switch S 1  is turned off when current I LC1  flowing to inductor L c1  is decreased to 0A. Because switch S 3  is in the “on” position at this time, panel terminal voltage V p  is sustained at address voltage V a  due to power source V a . 
     (5) Mode  5  (M 5 ) 
     Reference will be made to FIG.  4 E and the M 5  interval of FIG. 5 to describe the operation in Mode  5 . 
     In Mode  5 , with switch S 3  on, switch S 2  is turned on to form a current path that includes switch S 3 , parasitic inductors L p1  and L p2 , inductor L c2 , diode D 2 , switch S 2 , and capacitor C c2 . Due to the difference between power source V a  and voltage V a /2 charged on capacitor C c2 , current I LC2  flowing to inductor L c2  linearly increases. Thus the energy is stored in inductor L c2 . This current flows to parasitic inductors L p1  and L p2  as well and the energy is also stored in parasitic inductors L p1  and L p2 . 
     (6) Mode  6  (M 6 ) 
     Reference will be made to FIG.  4 F and the M 6  interval of FIG. 5 to describe the operation in Mode  6 . 
     In Mode  6 , with switch S 2  on, switch S 3  is turned off to form a current path that includes panel capacitor C p , parasitic inductor L p2 , inductor L c2 , diode D 2 , switch S 2 , and capacitor C c2 . Due to the LC resonance formed on the current path, a resonance current flows to inductor L c2  and panel terminal voltage V P  of panel capacitor C p  decreases to 0V. The energy stored in inductor L c2  and parasitic inductor L p2  makes panel terminal voltage V p  decrease to 0V stably despite the effect of the parasitic component. 
     (7) Mode  7  (M 7 ) 
     Reference will be made to FIG.  4 G and the M 7  interval of FIG. 5 to describe the operation in Mode  7 . 
     Panel terminal voltage V p  cannot drop below the ground voltage due to the body diode of switch S 4 . When panel terminal voltage V p  reaches the ground voltage, switch S 4  is turned on. With switch S 4  on, panel terminal voltage V p  is sustained at 0V. Current I L2  flowing to inductor L c2  linearly decreases to 0A through a current path that includes the body diode of switch S 4 , inductor L c2 , diode D 2 , switch S 2 , and capacitor C c2 . Namely, this current is recovered to capacitor C c2 . 
     (8) Mode  8  (M 8 ) 
     Reference will be made to FIG.  4 H and the M 8  interval of FIG. 5 to describe the operation in Mode  8 . 
     In Mode  8 , switch S 2  is turned off when current I LC2  flowing to inductor L c2  is decreased to 0A. Because switch S 4  is in the “on” position at this time, panel terminal voltage V p  is sustained at 0V due to the ground terminal. 
     As described above, in the embodiment of the present invention, the energy is not only stored in inductors L c1  and L c2  in Mode  1  and Mode  5 , respective, but also in parasitic inductors L p1  and L p2 , and it is used to change the panel terminal voltage thereby reducing a distortion caused by the parasitic inductance component. An actual experiment reveals, as shown in FIG. 6, that a rise pulse hardly occurs in the rise and drop intervals of the address-driving waveform. 
     It is impossible to form a current path of a different direction in the ground voltage interval between drop and rise intervals of panel terminal voltage V p , because the ground voltage interval is short as is characteristic of the address-driving waveform. According to the embodiment of the present invention, however, the direction of the current flowing to inductors L c1  and L c2  and parasitic inductors L p1  and L p2  is constant at any time. This facilitates the rise/drop operation of panel terminal voltage V p  despite the shortness of the ground voltage interval. 
     While this invention has been described in connection with specific embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.