Abstract:
When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a gate with a metal layer. 
         [0003]    2. Description of the Related Art 
         [0004]    Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density. 
         [0005]    One of the most widespread technologies is the complementary metal-oxide-semiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs and N-channel FETs, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies. 
         [0006]    Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials, such as, for example, dopant atoms or ions, may be introduced into the original semiconductor layer. 
         [0007]    When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices. 
         [0008]    Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages, such as dopant ion implantations, source and drain region formation and substrate silicidation, are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out. 
         [0009]    HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology. 
         [0010]    For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level. 
         [0011]    In the gate-first HKMG approach, a thin film of a silicon/germanium (SiGe) alloy is deposited on the surface of the silicon layer in order to adjust the transistor threshold voltage to a desired level. Since a portion of this thin film is included in the channel region of the FET, this SiGe thin film is also commonly referred to as “channel SiGe.” 
         [0012]    Furthermore, in the HKMG technology, a thin “work function metal” layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage can thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). A work function metal, such as, for example, aluminum, may also be included in the gate metal layer. 
         [0013]    Since the gate material formed on top of the gate metal layer is usually a semiconductor, for example, polysilicon, a Schottky barrier is established at the interface between the gate metal layer and the gate semiconductor material. This undesirably degrades the AC performance by limiting the circuit switching speed. 
         [0014]      FIGS. 1   a - 1   c  show some aspects of a transistor manufacturing flow according to the known gate-first HKMG approach. 
         [0015]      FIG. 1   a  schematically illustrates a cross-sectional view of a semiconductor structure  100  in an advanced manufacturing stage. The semiconductor structure  100  has been obtained after forming insulation regions  102   b  in a semiconductor layer  102 . The insulation regions  102   b  may have been formed as shallow trench isolations. The semiconductor layer  102 , typically comprising mono-crystalline silicon, is formed on a substrate  101 , which may be comprised of any appropriate carrier. 
         [0016]    Active regions  102   a  are subsequently formed in the semiconductor layer  102 . This may comprise performing one or more well implantations. Active regions are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience of display, a single active region  102   a  is illustrated, which is laterally limited by insulation regions  102   b.    
         [0017]      FIG. 1   a  shows that a FET  150  has been formed after defining the active region  102   a . In the gate-first HKMG, a gate structure  160  is formed on the upper surface of the active region  102   a . Although not shown, a thin channel SiGe film may have been deposited on the surface of the active region  102   a  before forming the gate structure  160 . 
         [0018]    The gate structure  160  is formed by sequentially stacking layers of different materials, which are subsequently patterned so as to obtain the desired gate structure size and dimensions. The stack making up the gate structure  160  comprises an insulation layer  161  formed on the surface of the active region  102   a , a gate metal layer  164  and a gate material layer  162  exposed to the outside. 
         [0019]    The insulation layer  161 , formed on the surface of the active region  102   a , comprises a high-k material. The gate metal layer  164  is formed between the insulation layer  161  and the gate material  162  so as to adjust the transistor threshold voltage. The gate material layer  162 , formed directly on the upper surface of the gate metal layer  164 , typically comprises a semiconductor such as polysilicon. 
         [0020]      FIG. 1   b  shows that, after forming the gate stack, this can be protected by forming a spacer structure  163  on its sidewalls. The spacer structure  163  may be advantageously used as an implantation mask in subsequent manufacturing stages. 
         [0021]    After forming the gate structure  160  and the spacer structure  163 , several implantations are carried out in order to define source and drain regions  151  of the transistor  150 . The implantations may comprise halo/extension implants giving rise to extension regions  151   e  and halo regions (not shown) in the active region  102   a . After performing halo/extension implantations, the spacer structure  163  may be broadened and an additional series of implantations may be carried out in order to form deep regions  151   d  of source and drain regions  151 . 
         [0022]    An annealing step follows the series of implantations defining source and drain regions  151 . Annealing is performed in order to activate the implanted dopant ions and to allow the crystalline structure to recover from implantation damage. After the annealing process, a channel region  155  of the transistor  150  rests defined between source and drain regions  151 . 
         [0023]    After the annealing step, metal silicide layers  153  and  165  are formed in order to decrease the contact resistance to the electrodes of the transistor  150 , as shown in  FIG. 1   c.    
         [0024]    Salicidation (i.e., self-aligned silicidation) is typically performed by depositing a refractory metal layer onto the exposed face of the semiconductor structure  100 . The refractory metal layer may comprise, for example, a metal such as nickel, titanium, cobalt and the like. Preferably, the refractory metal layer comprises nickel. The refractory metal layer may also comprise platinum, which in some cases may promote a more homogeneous formation of nickel monosilicide. 
         [0025]    A heat treatment is then applied to the semiconductor structure  100  in order to promote a chemical reaction between the metal atoms of the deposited layer and the silicon atoms of the exposed surface of the semiconductor structure  100 . 
         [0026]      FIG. 1   c  shows that, as a result of the heat treatment, the metal silicide layer  153  has formed partly in and partly on top of the active region  102   a , thus forming an interface with the source and drain regions  151 . Furthermore, the metal silicide layer  165  has formed on top of the gate structure  160 , thus forming an interface with the gate material  162  exposed before the deposition of the refractory metal layer. It should be noted that the silicon material contained in the sidewall spacer structure  163  and the isolation regions  102   b  does not substantially take part in the chemical reaction induced during the heat treatment process, as it is present in those features only as a thermally stable silicon dioxide and/or silicon nitride material. 
         [0027]    As said above, the transistor resulting from the above-described manufacturing flow is affected by the drawback of the Schottky barrier forming at the interface between the gate metal layer  164  and the gate material  162 . In order to get rid of this Schottky barrier, it would be convenient to form a metal silicide layer  165  of a thickness sufficient for directly forming an interface with the gate metal layer  164 . 
         [0028]    One method of achieving this goal is forming so-called “fully silicided” gates, wherein the metal silicide layer  165  totally replaces the gate material  162  so as to directly contact the gate metal layer  164 . 
         [0029]    In the state of the art, formation of fully silicided gates has been limited by the correlation existing between the thickness of the metal silicide layer  153  on the source/drain regions and that of the metal silicide layer  165  on top of the gate. This is due to the fact that typically the same salicidation step is used for forming metal silicide layers  153  and  165 . Thus, increasing the thickness of the metal silicide  165  on the gate structure generally causes a simultaneous increase of the thickness of the metal silicide  153  contacting the source/drain regions of the transistor. 
         [0030]    However, the thickness of the source/drain metal silicide  153  may not be increased beyond an upper limit. In general, the thickness of the metal silicide layer  153  must be considerably smaller than the thickness of the semiconductor layer  102 . This limitation becomes more and more problematic as the typical device sizes decrease, since reducing, for example, the gate length also requires a corresponding scaling of the source and drain regions  151  in the vertical direction. 
         [0031]    An example of a method of forming a fully silicided gate structure may be found in U.S. Pat. No. 6,821,887. In this patent, the height of the gate structure is appropriately chosen so as to permit the reaction of all gate material with the refractive metal during the silicidation process described above. However, this method poses a stringent limitation on the vertical dimension of the gate structure. 
         [0032]    By using known methods, it is thus particularly difficult to obtain a fully silicided gate while maintaining the thickness of the source/drain metal silicide layer at a sufficiently low value. Therefore, a need arises for an improved transistor manufacturing method, permitting formation of a fully silicided gate which does not require a simultaneous broadening of the source/drain metal silicide layers. 
       SUMMARY OF THE INVENTION 
       [0033]    The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. 
         [0034]    The present disclosure is based on the new and inventive idea that the manufacturing process of a transistor can be improved by introducing an additional pure metal layer between the gate metal layer and the gate material in an HKMG structure. In this manner, two metal silicide layers can be formed in the gate structure: a first metal silicide layer in electrical contact with the gate metal layer and a second metal silicide layer formed on the first metal silicide layer. Based on this idea, one illustrative semiconductor structure includes an active region formed in a semiconductor layer and a transistor having a gate structure and a source region and a drain region formed in the active region, wherein the gate structure includes a gate insulating layer formed on the surface of the active region, a gate metal layer formed on the insulating layer, a first metal silicide layer formed on the gate metal layer and a second metal silicide layer formed on the first metal silicide layer. The gate structure of the semiconductor structure implements a fully silicided metal gate, since the second metal silicide layer is in electrical contact with the gate metal layer through the first metal silicide layer, without the presence of any gate semiconductor material between the gate metal layer and the second metal silicide layer. Furthermore, due to the presence of the first metal silicide layer, the thickness of the first metal layer can be maintained low, while simultaneously ensuring that the first and second metal silicide layer are in electrical contact. 
         [0035]    A method of forming a semiconductor structure is also provided which includes forming an active region in a semiconductor layer and forming a gate structure on the active region, wherein forming the gate structure includes forming an insulating layer on the surface of the active region, forming a gate metal layer on the insulating layer, forming a pure metal layer on the gate metal layer and forming a gate material layer on the pure metal layer. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0036]    The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: 
           [0037]      FIGS. 1   a - 1   c  schematically illustrate cross-sectional views of a semiconductor structure comprising a transistor during subsequent stages of a manufacturing process flow according to the prior art; 
           [0038]      FIGS. 2   a - 2   e  schematically illustrate cross-sectional views of a semiconductor structure during subsequent manufacturing stages of a manufacturing process flow according to an embodiment of the present invention. 
       
    
    
       [0039]    While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0040]    Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. 
         [0041]    The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. 
         [0042]    It should be noted that, where appropriate, the reference numbers used in describing the various elements illustrated in  FIGS. 2   a - 2   e  substantially correspond to the reference numbers used in describing the corresponding elements illustrated in  FIGS. 1   a - 1   c  above, except that the leading numeral for corresponding features has been changed from a “1” to a “2”. For example, semiconductor device  100  corresponds to semiconductor device  200 , gate insulation layer  161  corresponds to gate insulation layer  261 , gate electrode  160  corresponds to gate electrode  260 , and so on. Accordingly, the reference number designations used to identify some elements of the presently disclosed subject matter may be illustrated in FIGS.  2   a - 2   e  but may not be specifically described in the following disclosure. In those instances, it should be understood that the numbered elements shown in  FIGS. 2   a - 2   e  which are not described in detail below substantially correspond with their like-numbered counterparts illustrated in  FIGS. 1   a - 1   c , and described in the associated disclosure set forth above. 
         [0043]    Furthermore, it should be understood that, unless otherwise specifically indicated, any relative positional or directional terms that may be used in the descriptions below—such as “upper,” “lower,” “on,” “adjacent to,” “above,” “below,” “over,” “under,” “top,” “bottom,” “vertical,” “horizontal” and the like—should be construed in light of that term&#39;s normal and everyday meaning relative to the depiction of the components or elements in the referenced figures. For example, referring to the schematic cross-section of the semiconductor device  200  depicted in  FIG. 2   a , it should be understood that the gate electrode structure  260  is formed “above” the active region  202   a  and that the pure metal layer  266  is formed “below” or “under” the gate material  262 . 
         [0044]      FIG. 2   a  shows a cross section of a semiconductor structure  200  during an advanced manufacturing stage substantially corresponding to the fabrication method according to the prior art shown in  FIG. 1   a.    
         [0045]    The semiconductor structure  200  comprises a semiconductor layer  202  in which isolation regions  202   b  have been formed. Isolation regions  202   b  may comprise, for example, shallow trench isolations. The isolation regions  202   b  laterally define an active region  202   a . A plurality of active regions  202   a  may be formed in the semiconductor layer  202 , although only one is shown in  FIG. 2   a . One or a series of implantations, e.g., well implantations, may have been performed in order to provide active region  202   a  with a desired doping profile. 
         [0046]    According to one embodiment, the semiconductor layer  202  comprises silicon. According to a particular embodiment, the semiconductor layer  202  comprises mono-crystalline silicon. 
         [0047]    The layer  202  is formed attached to a substrate  201 . The substrate  201 , which may represent any appropriate carrier material, and the semiconductor layer  202  may form a silicon-on-insulator (SOI) configuration. Alternatively, the semiconductor layer  202  may be formed in the bulk of the substrate  201 . 
         [0048]    Although not shown, a thin film of a semiconductor alloy, e.g., a channel SiGe film, may have been epitaxially formed on the surface of the semiconductor layer  202 . 
         [0049]    The semiconductor structure  200  comprises a transistor  250  formed partly in and partly on the semiconductor layer  202 . The transistor  250  may be a FET, for example an N-channel FET or a P-channel FET. For example, the transistor  250  may form with a second transistor of an opposite polarity (not shown) a pair used in the CMOS technology. 
         [0050]    The transistor  250  comprises a gate structure  260 , formed on the surface of the semiconductor layer  202  after having defined the active region  202   a  and, where needed, after forming a channel semiconductor alloy film. The semiconductor alloy may comprise SiGe. The gate structure  260  is preferably formed according to the HKMG technology. According to a particular embodiment, the gate structure  260  is performed according to the gate-first HKMG approach. 
         [0051]    Thus, the gate structure  260  comprises a gate insulating layer  261  formed directly on the surface of the active region  202   a . The insulating layer  261  comprises a high-k material. By high-k material it is referred to a material with a dielectric constant “k” higher than 10. Examples of high-k materials used as insulating layers in gate electrodes are tantalum oxide (Ta 2 O 5 ), strontium titanium oxide (SrTiO 3 ), hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO 2 ) and the like. 
         [0052]    The gate structure  260  further comprises a gate metal layer  264  formed on the gate insulating layer  261  in order to permit threshold voltage adjustment. The gate metal layer  264  may comprise a metal such as tantalum or tungsten. Preferably, the gate metal layer  264  comprises a nitride such as, for example, titanium nitride or tantalum nitride. A certain percentage of a work function metal species, such as aluminum and the like, may be included in the gate metal layer  264  in combination with other materials. 
         [0053]    A gate material layer  262  is then formed in the gate structure  260  so as to expose an upper surface thereof to the outside. Typically, the gate material layer  262  comprises a semiconductor. In some embodiments, the gate material layer  262  comprises polysilicon. 
         [0054]    Unlike the gate structure known from the prior art described above, the gate structure  260  according to one embodiment of this disclosure further comprises a pure metal layer  266  formed on the gate metal layer  264  so as to form an interface and be in electrical contact therewith. The gate material layer  262  is then formed directly on the pure metal layer  266 , so that the pure metal layer  266  is sandwiched between the gate material layer  262  and the gate metal layer  264 . 
         [0055]    The pure metal layer  266  comprises a metal which, when the system is heated, can form a metal silicide compound with the semiconductor material of the gate material layer  262 . For example, the pure metal layer  266  may comprise a refractory metal. In some embodiments, the metal layer  266  comprises at least one of titanium (Ti) or cobalt (Co). Alternatively, the pure metal layer  266  may comprise any metal known in the art. Examples of metals which can be used for forming the pure metal layer  266  include copper, gold, silver, aluminum, etc. In some embodiments, the thickness of the pure metal layer  266  ranges from about 10-30 nm. In general, the thickness of the pure metal layer  266  is chosen so that, during a salicidation process described in the following, a lower-lying silicide layer formed as a result of the reaction of the pure metal layer  266  with the gate material  262  merges with an upper-lying metal silicide layer formed above the lower-lying silicide layer, thereby resulting in a fully silicided gate. 
         [0056]    As shown in  FIG. 2   b , a spacer structure  263  is formed on the sidewalls of the gate stack  260 . Subsequently, source and drain regions  251  of the transistor  250  are formed in the active region  202   a . Formation of the source/drain regions  251  is achieved in an analogous way to the traditional manufacturing flow described with reference to  FIG. 1   b . Namely, a first series of ion implantations is usually performed so as to define halo regions (not shown) and extension regions  251   e  in the active region  202   a . Subsequently, a second series of implantations is performed in order to define deep regions  251   d  of the source/drain regions  251 . The spacer structure  263  may be conveniently broadened after performing halo/ 2162 . 241700  extension implantations and before starting the second series of implantations forming deep regions  251   d.    
         [0057]    After performing all necessary implantations for defining source/drain regions  251 , the semiconductor structure  200  is annealed in order to activate the implanted ions and allow the lattice structure of the semiconductor layer  250  to recover from implantation damage. At the end of the annealing process, the channel region  255  of the transistor  250  rests defined in the active region  202   a  between the source and the drain regions  251 . 
         [0058]    According to the embodiment shown in  FIGS. 2   c  and  2   d , a salicidation process is performed after carrying out the activation annealing. 
         [0059]    As shown in  FIG. 2   c , the salicidation starts by depositing a metal layer  208  on the surface of the semiconductor structure  200 . The metal layer  208  preferably comprises nickel. Alternatively, the metal layer  208  may comprise titanium or cobalt. It should be noted that, after depositing the metal layer  208 , the semiconductor material of the gate material layer  262  is sandwiched between the pure metal layer  266  and the deposited metal layer  208  on top. 
         [0060]    After depositing the metal layer  208 , a heat treatment is applied to the semiconductor structure  200 . The heat treatment may be performed at a temperature in the range of about 300-500° C. for a time period ranging from approximately 10 seconds to a few minutes. 
         [0061]    For example, the heat treatment may be a two-step process. A first heat treatment step may be performed in the range of approximately 250-400° C. for a time period of approximately 10-90 seconds. After the first heat treatment step, any non-reacted metal of the layer  208  may be selectively removed by one of a variety of well-known etch/cleaning processes. Finally, a second heat treatment step may be performed in the range of approximately 400-500° C., again for a time period of approximately 10-90 seconds. 
         [0062]      FIG. 2   d  shows the semiconductor structure  200  after the heat treatment included in the salicidation process has been accomplished. The heat treatment initiates a chemical reaction between the metal atoms of the metal layer  208  and the semiconductor atoms included in those surface portions of the semiconductor structure  200  which form an interface with the metal layer  208 . This chemical reaction results in formation of metal silicide layer  253  formed partly in and partly on the source/drain regions  251  so as to form an interface therewith. Furthermore, the chemical reaction between the deposited metal layer  208  and the semiconductor material, typically silicon, of the gate material layer  262  results in formation of a metal silicide layer  265  included in the gate structure  260  and having an upper surface exposed to the outside. Metal silicide layers  253  and  265  typically comprise nickel silicide (NiSi). 
         [0063]    In contrast to the method and system known from the prior art, the heat treatment included in the salicidation according to the claimed invention further initiates a chemical reaction between the metal atoms in the pure metal layer  266  and the semiconductor material of the gate material layer  262  in contact with the pure metal layer  266 . This additional chemical reaction results in formation of a second metal silicide layer  266   a  lying between the gate metal layer  264  and the first metal silicide layer  265 . In some embodiments, the second metal silicide layer  266   a  comprises at least one of titanium disilicide (TiSi 2 ) or cobalt disilicide (CoSi 2 ). 
         [0064]    During the heat treatment, all metal material of the pure metal layer  266  may react with the semiconductor material of the gate metal layer  262 . If this is the case, the second metal silicide layer  266   a  forms an interface with the gate metal layer  264 , as shown in  FIG. 2   d . Alternatively, the thickness of the pure metal layer  266  may be large enough that a residual portion thereof remains on the gate metal layer  264  after completing the heat treatment. In this case, the second metal silicide layer  266   a  forms an interface with the residual portion of the pure metal layer  266 . 
         [0065]    According to an advantageous embodiment, the salicidation process is optimized so that all semiconductor material included in the gate material layer  262  reacts during the heating treatment, either with above-lying metal film  208 , or with below-lying pure metal layer  266 . The parameters of the salicidation process which may be varied in order to optimize the process include type and thickness of the deposited metal layer  208 , number of steps of the heat treatment, temperature and duration of the heat treatment, etc. 
         [0066]    According to some embodiments, the metal film  208  comprises nickel and has a thickness in the range of about 10-15 nm. Furthermore, the heat treatment is performed in two subsequent stages, as described above. In some embodiments, a first heat treatment is performed at a temperature of approximately 270-330° C. for 10-50 seconds. All unreacted nickel is subsequently stripped. A second heat treatment is performed at a temperature of approximately 400-480° C., again for a time of approximately 10-50 seconds. This second heat treatment transforms the nickel silicide phase into the low-resistivity phase. 
         [0067]    If all semiconductor material of the gate material  262  takes part in the reaction during the heat treatment, then first metal silicide layer  265  and the second metal silicide layer  266   a  are in electrical contact with each other through a shared interface. Thus, the gate structure  250  shown in  FIG. 2   d  is fully silicided, since no semiconductor material is present between the gate metal layer  264  and the exposed metal silicide layer  265 . 
         [0068]    After the salicidation process, the gate metal layer  264  forms a metal-metal junction either with the second metal silicide layer  266   a , or with the residual portion of the pure metal layer  266 . Thus, no Schottky barrier is present between the gate metal layer  264  and the layer lying above it. Furthermore, since the second silicide layer  266   a  forms a metal-metal junction with the first metal silicide layer  265 , no Schottky barrier is present between the first metal silicide layer  265  and the second metal silicide layer  266   a  either. 
         [0069]    The semiconductor structure and the method according to the present disclosure provide a significant improvement with respect to the state in the art. By using the claimed manufacturing method, it is possible to implement a gate structure wherein the first metal silicide layer  265  is in electrical contact with the gate metal layer  264  through the second metal silicide layer  266   a , without the presence of any metal-semiconductor junctions or Schottky barriers therebetween. 
         [0070]    Furthermore, a fully silicided gate can be obtained without having to unduly increase the thickness of the metal silicide  253  contacting the source/drain regions  251  of the transistor. This is achieved due to the presence of an additional pure metal layer  266  between the gate metal layer  264  and the semiconductor gate material  262 . 
         [0071]    A salicidation process can then be performed wherein the semiconductor gate material  262  reacts with a deposited metal layer  208  lying on top of the gate material and with the metal of the additional metal layer  266  lying under the gate material. If the salicidation is optimized so that all semiconductor material in the gate reacts with the metal on top and under it, then a fully silicided gate is formed. 
         [0072]    In contrast to the prior art, in the fully silicided gate hereby proposed, the upper metal silicide layer  265 , typically comprising nickel silicide, does not have to extend into the gate structure all the way down to the surface of the gate metal layer  264 . Conversely, the thickness of the upper metal silicide layer  265 , correlated to the thickness of the gate/source metal silicide layer  253 , can be maintained at a relatively low value due to the presence of the additional metal silicide layer  266   a  sandwiched between the metal silicide layer  265  and the gate metal layer  264 . In this respect, the thickness of the pure metal layer  266  can be appropriately chosen so as to have a first metal silicide layer  265  of a given thickness. 
         [0073]      FIGS. 2   a - 2   d  show an embodiment of the claimed manufacturing flow wherein the first metal silicide layer  265  and the second metal silicide layer  266   a  are formed in the course of the same silicidation process. However, according to other embodiments not shown in the figures, the second metal silicide layer  266   a  may be formed before the first metal silicide layer  265 . 
         [0074]    More specifically, according to a further embodiment, the gate structure is initially formed so as to comprise a gate insulation layer  261 , a gate metal layer  264  and a pure metal layer  266  on top of the gate metal layer  264 . A first salicidation process is then carried out resulting in a lower metal silicide layer  266   a . A gate material layer, typically comprising a semiconductor material such as polysilicon, is then formed on the surface of the lower metal silicide layer  266   a . Gate and source regions of the transistor are then formed as described above in relation to the first embodiment. Finally, a second silicidation is performed by depositing a metal-containing layer and performing a heat treatment, as described above with reference to  FIGS. 2   c  and  2   d . The second silicidation results in formation of metal silicide layers  253  electrically contacting the source and drain regions of the transistor and of upper metal silicide layer  265  electrically contacting the lower metal silicide layer  266   a . After performing the second silicidation process, the system looks again as in  FIG. 2   d.    
         [0075]    Also by means of this second embodiment, a fully silicided gate can be obtained, while maintaining the thicknesses of the metal silicide layers  265  and  253  low. This can again be achieved due to the presence of the lower metal silicide layer  266   a.    
         [0076]    After the salicidation processes described above, the manufacturing flow continues in a conventional manner. 
         [0077]      FIG. 2   e  shows the semiconductor structure  200  in an advanced manufacturing process stage following that shown in  FIG. 2   d . As shown in  FIG. 2   d , after formation of the metal silicide layers  253 ,  265  and  266   a , a stressed material layer  220  is deposited on the surface of the semiconductor structure  200 . The stressed material layer  220  may comprise silicon nitride (Si 3 N 4 ). Subsequently, a UV curing process is applied at a temperature ranging from 400-500° C. 
         [0078]    An interlayer dielectric layer  230  is then deposited on the stressed material layer  220 . The interlayer dielectric layer  230  may comprise an oxide, such as, for example, silicon dioxide (SiO 2 ). An etching process is then applied, for example through a patterned mask, in order to form via openings  272  and  274 . Openings  272  expose predetermined portions of the metal silicide layer  253  contacting the source and drain regions  251 . On the other hand, via openings  274  expose predetermined portions of the first metal silicide layer  265  contacting the gate  260 . 
         [0079]    Finally, via openings  272  and  274  can be filled with a metal (not shown), for example tungsten or copper, so as to form electrical contacts to the source and drain regions and to the gate electrode of the transistor  250 . 
         [0080]    The present invention provides a convenient method for forming a fully silicided gate of a transistor, which can, for example, be a FET. The proposed device and method find an advantageous application in semiconductor manufacturing technologies starting from 45 nm and beyond. In particular, the claimed method and device may be applied to the 28 nm technology and beyond. The method and device may be advantageously applied in conjunction with the HKMG technology, particularly within the framework of the gate-first HKMG approach. 
         [0081]    The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.