Abstract:
A Reflective Field Emission Display (FED) pixel element and system employing same are disclosed. In the FED system disclosed, each pixel element is composed of at least one emitter that is operable to emit electrons and at least one reflector that is operable to attract and reflect the emitted electrons onto a transparent anode layer that oppositely positioned with respect to the emitter and reflector and is operable to attract the reflected electrons. In one aspect of the invention, the emitter layer is shaped to bound the reflector layer forming an electrical boundary that focuses the reflected electron beam onto a phosphor layer interposed between the transparent layer. In another aspect of the invention, a high voltage and a corresponding high voltage phosphor is applied to the transparent anode layer. The use of high voltage and high voltage phosphor is advantageous as it causes the reflected electrons to be drawn deeper into the phosphor layer and, hence, reduces unwanted emissions back into the vacuum of the pixel element. In still another aspect of the invention, a plurality of phosphor layers are applied to the transparent layer to produce a color display as reflected electrons are attracted to the transparent layer.

Description:
PRIORITY FILING DATE  
       [0001]    This application claims the benefit of the earlier filing date, under 35 U.S.C. §119, of U.S. Provisional Patent Applications;  
         [0002]    Ser. No. ______ , entitled “Configuration of Edge Emitter Display,” filed on Aug. 16, 2002; and  
         [0003]    Serial No. 60/399,825, entitled “Reflective Edge Emitter FED with Shaped Emitter Layer,” filed on Jul. 31, 2002, the entirety of which are incorporated by reference herein.  
       RELATED APPLICATIONS  
       [0004]    This application is a continuation-in-part of commonly assigned, co-pending, patent application:  
         [0005]    Ser. No. 10/102,450, entitled “Field-Emission Matrix Display Based on Electron Reflection,” filed on Mar. 20, 2002, the entirety of which is incorporated by reference herein. 
     
    
     
       FIELD OF THE INVENTION  
         [0006]    The present invention relates to solid-state displays and more specifically to edge-emitter reflective field emission pixel elements having shaped emitter elements for electron beam focusing for displays.  
         BACKGROUND OF THE INVENTION  
         [0007]    Solid state and non-Cathode Ray Tube (CRT) display technologies are well-known in the art. Light Emitting Diode (LED) displays, for example, include semiconductor diode elements that may be arranged in configurations to display alphanumeric characters. Alphanumeric characters are then displayed by applying a potential or voltage to specific elements within the configuration. Liquid Crystal Displays (LCD) are composed of a liquid crystal material sandwiched between two sheets of a polarizing material. When a voltage is applied to the sandwiched materials, the liquid crystal material aligns in a manner to pass or block light. Plasma displays conventionally use a neon/xenon gas mixture housed between sealed glass plates that have parallel electrodes deposited on the surface.  
           [0008]    Passive matrix displays and active matrix displays are flat panel displays that are used extensively in laptop and notebook computers. In a passive matrix display, there is a matrix or grid of solid-state elements in which each element or pixel is selected by applying a potential to a corresponding row and column line that forms the matrix or grid. In an active matrix display, each pixel is further controlled by at least one transistor and a capacitor that is also selected by applying a potential to a corresponding row and column line. Active matrix displays provide better resolution than passive matrix displays, but they are considerably more expensive to produce.  
           [0009]    While each of these display technologies has advantages, such as low power and lightweight, they also have characteristics that make them unsuitable for many other types of applications. Passive matrix displays have limited resolution, while active matrix displays are expensive to manufacture.  
           [0010]    The edge emitter FED pixel element disclosed in U.S. patent application Ser. No. 10/102,450, entitled “Field-Emission Matrix Display Based on Electron Reflection,” is representative of a pixel element that may be included in a low-cost, lightweight, high-resolution display system. In such a display, a high screen brightness with a minimum power consumption is advantageous. One method for achieving a high screen brightness is to concentrate the reflected electron beam onto an associated phosphor layer with little or no scattering, or cross-talk, of the electron beam from one pixel element into adjacent pixel elements, or as will be appreciated, an adjacent sub-pixel element.  
           [0011]    Hence, there is a need for a method of concentrating or focusing the electron beam of edge-emitter FED pixel elements onto associated phosphor layers to substantially reduce electron beam cross-talk between adjacent elements.  
         SUMMARY OF THE INVENTION  
         [0012]    An edge-emitter Field Emission Display (FED) pixel element and associated matrix display is disclosed. The FED pixel element has a reflector layer and an anode layer having a phosphor layer thereon, and a shaped emitter layer, which bounds a reflector layer and focuses a reflected electron beam to avoid scattering of the electron beam as it travels to the anode. Also disclosed is the use of high-voltage and high-voltage phosphor on the anode layer that advantageously improves the pixel element&#39;s operational life. Also disclosed, is a method of determining the voltage on the anode layer to enhance the focusing of the electron beam based on the distance between the anode and the reflecting surface. In another aspect of the invention, a plurality of phosphor layers are applied to the transparent layer, which produce different levels of color as reflected electrons are attracted to the transparent layer and bombard corresponding phosphor layers. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    In the drawings:  
         [0014]    [0014]FIGS. 1 a - 1   e  illustrate cross-sectional views of different embodiments of Field-Emission Display (FED) pixel element in accordance with the principles of the invention;  
         [0015]    [0015]FIG. 2 illustrates a top view of the shaped-emitter pixel element in accordance with the principles of the invention;  
         [0016]    [0016]FIG. 3 illustrates a top view of the second embodiment of a shaped-emitter pixel element in accordance with the principles of the invention;  
         [0017]    [0017]FIGS. 4 a  and  4   b  illustrate top views of shaped-emitter pixel elements for color pixel elements in accordance with the principles of the invention;  
         [0018]    [0018]FIG. 5 illustrates a cross sectional view of a color pixel element in accordance with the principles of the present invention; and  
         [0019]    [0019]FIG. 6 illustrates a graph of line current versus reflector layer voltage for a pixel element fabricated in accordance with the principles of the invention.  
         [0020]    It is to be understood that these drawings are solely for purposes of illustrating the concepts of the invention and are not intended as a definition of the limits of the invention. It will be appreciated that the same reference numerals, possibly supplemented with reference characters where appropriate, have been used throughout to identify corresponding parts.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]    [0021]FIG. 1 a  illustrates a cross-sectional view of an edge-emitter Field Emission Display (FED) pixel element  100  in accordance with the principles of the invention. In this exemplary embodiment, pixel element  100  is fabricated by depositing at least one reflective layer  110  on a dielectric or non-conductive substrate  120 , e.g. glass, silicon dioxide (SiO2). Reflective layer  110  is representative of an electrode that may also be used to control a voltage or potential applied to pixel elements  100  that are arranged in a row or column, which are oriented orthogonal to the plane of FIG. 1 a , as will more fully be explained. Reflective electrode  110  may be any material possessing a high electrical conductivity and reflectivity selected from a group of metals, such as, gold, silver, aluminum, vanadium, niobium, chromium, molybdenum, etc. In a preferred embodiment, reflective layer  110  is formed from niobium.  
         [0022]    Insulator layer  130 , preferably silicon dioxide, SiO 2 , is next deposited on reflective layer  110 . Insulator layer  130  electrically isolates reflective layer  110  and is preferably in the range of about 0.5 microns thick. Emitter layer  140  is next deposited on insulating layer  130 . Emitter layer  140  is of a material that is operative to emit electrons when a sufficient potential difference exists between reflective layer  110  and emitter layer  140 . Emitter layer  140  is preferably selected from materials that emit electrons from an edge  142  when a potential difference exists between reflector layer  110  and emitter layer  140 . In the illustrated, and preferred, embodiment, emitter layer  140  is comprised preferably of a bottom conductive layer  150  and an edge emitter layer  170  having emitter edge  142 . Emitter edge layer or cathode layer  170  is composed of a material having a low-work function for emitting electrons. Emitter edge layer  170  may be a resistive material. In a preferred embodiment emitter edge layer  170  is an alpha-carbon (α-C) material formed as an edge in the range of 50-80 nanometers-thick. Alpha-carbon film is well known to have a low work function for electron emission into a vacuum. Conductive layer  150  is representative of an electrically conductive material that provides an electrical contact to the edge emitter layer  170  and may be used as a column or row connector in a FED display, as will be further explained.  
         [0023]    Pixel well  145  is next created by etching, for example using photo-resistant patterning, through emitter layer  140  and insulator film layer  130  to expose reflector layer  110 . Emitter layer  140  is etched or shaped such that it borders on all sides, i.e., circumjacent, exposed reflector layer  110 . Photo-resistant patterning is well known in the art and need not be discussed in detail herein. Pixel  100  preferably is in the order of 300×300 microns.  
         [0024]    As will be appreciated, the exposed width of reflector layer  110  may be determined by appropriately timing the etching of insulating layer  130 . Hence, in one aspect, emitter layer  140 , and more specifically, edge  142  and reflective layer  110  may be aligned and non-overlapping, i.e., self-aligned. In another aspect, emitter layer  140 , and more specifically, edge  142  may overlap reflective layer  110 , as shown.  
         [0025]    A transparent electrode, preferably an Indium Titanium Oxide (ITO)  180  is deposited on transparent plate  190 , e.g., glass. ITO layer  180  is an optically transparent conductive material that may be used to provide a known potential in selective areas of ITO  180 .  
         [0026]    Phosphor layer  195  is then deposited on ITO  180 . Phosphor layer  195  produces a predetermined or desired level of photonic activity or illumination when activated or bombarded by impinging electrons. In a preferred aspect, phosphor layer is deposited such that it is opposite a corresponding pixel well  145 .  
         [0027]    Although not shown, it would be appreciated that a dielectric material, such as SiO 2 , may be selectively placed as spacers to electrically separate transparent substrate  190  and emitter layer  140 .  
         [0028]    The confined pixel volume contained between pixel well  145  and transparent surface  190  is further evacuated to a pressure in the range of, 10 −5  to 10 −7 , and preferably, 10 6  torr. Methods for evacuating the gases within a sealed pixel element are well known in the art and need not be discussed in detail.  
         [0029]    In the operation of pixel element  100 , the application of a positive voltage or potential to reflective layer  110  relative to emitter layer  140  creates an electrical field that draws electrons from edge  142  of emitter layer  140  to reflective layer  110 . Electrons reflected from reflective layer  110  are then attracted to a positive voltage applied to ITO layer  180 , which in turn bombard phosphor layer  195 . It will be appreciated that emitter layer  140  and reflective layer  110  may be held at a known potential difference with is not sufficient to cause the emission of electrons from emitter layer  140 . An additional voltage, in the form of a pulse, may then be applied to reflective layer  110  to create a potential difference sufficient for emitter layer  140  to emit electrons.  
         [0030]    As will be appreciated, the gap between the edge  142  and reflector layer  110  can be made extremely small, preferably less than or equal to one (1) micron. In this case, the voltage or potential difference between edge  142  and reflector layer  110  can be reduced to a level between 20 and 200 volts. In a preferred embodiment, the potential between emitter layer  140  and reflector layer  110  is in the order of 25-50 volts. The potential of the combined phosphor  195 /ITO layer  180  may be kept at a significantly higher voltage to attract reflected electrons to a corresponding phosphor layer to illuminate substantially the entire phosphor layer corresponding the pixel element without reflected electrons being spread into an adjacent pixel element phosphor layer.  
         [0031]    [0031]FIG. 1 b  illustrates a second embodiment  200  of the invention in which emitter layer  140  is represented as layer  210 . In this embodiment, layer  210  is made of a conductive material suitable for emitting electrons from edge  215  when a potential difference exists between reflector layer  110  and emitter layer  210 . In this embodiment, layer  210  may be an electrically conductive material such as gold, silver, aluminum, molybdenum, etc. Preferably, layer  210  is fabricated from molybdenum.  
         [0032]    [0032]FIG. 1 c  illustrates a third embodiment  300  of the present invention in which emitter layer  140  includes layer  210  and insulating layer  310 , such as SiO 2 , deposited on layer  210 .  
         [0033]    [0033]FIG. 1 d  illustrates a fourth embodiment  400  of the present invention in which emitter layer  140  is composed of a resistive material  410 , such as alpha-silicon (α-Si), imposed between conductive layer  150  and edge emitter layer  170 , of FIG. 1 a.    
         [0034]    [0034]FIG. 1 e  illustrates a fifth embodiment  500  of the present invention, in which insulating layer  510  is deposited on edge emitter layer  170  shown in FIG. 1 d . Although not shown it will be appreciated that edge emitter layer  170  may be replaced by materials similar to those selected for edge emitter layer  210 .  
         [0035]    [0035]FIG. 2 a  illustrates a top view of a shaped-emitter, non-self-aligned, pixel element  600  in accordance with the principles of the invention. In this aspect, the edges  142  of emitter layer  140  extend over reflective layer  110 , as represented by dashed lines  605 . Emitter layer  140  is further shaped such that edges  142  form a perimeter, vertically offset from, around the reflective surface of reflector layer  110 . In this aspect, the reflective surface is substantially contained within the perimeter boundary determined by the edges  142 . A potential or voltage applied to emitter layer  140 , thus, creates an electrical barrier that restrains, or confines, the direction of electrons reflected from reflector layer  110  to remain within the bounds of edges  142 . Restraint or containment of the reflected electron beam substantially within the bounds of edges  142  is advantageous as it limits the spread of the electron beam and reduces cross-talk between pixel element or sub-pixel elements in color displays, as will be shown.  
         [0036]    Further illustrated is that emitter layer  140  may be in electrical communication with similar pixel elements (not shown) by at least one column row line  610  and reflective layer  110  may be in electrical communication with similar pixel elements (not shown) by row lines  620 . As is known in the art, pixel element  100  may be identified or addressed in a display unit composed of a matrix of similar pixel elements by its row identifier and its column identifier. Pixel element  600  may also be identified by a plurality of emitter layer  140  connected in rows and reflector layers  110  connected in columns, as is well-known.  
         [0037]    [0037]FIG. 2 b  illustrates a cross-sectional view through section A-A of the pixel element  600  shown in FIG. 2 a , showing paths of electrons reflected from reflector layer  110 . In this case, electrons  635  emitted from emitter layer  140  are attracted to, and reflected from, reflector layer  110 . The path of electrons reflected from reflector layer  110  at an initial angle substantially different than 90 degrees, as illustrated by angle  640 , may be directed or deflected by the potential difference between the reflected electron and the potential or voltage applied to emitter layer  140  to a substantially perpendicular direction of travel to ITO layer  180 . Hence, electrons  635  may be substantially maintained within the bounds of emitter layer  140  and as fewer electrons  635  penetrate the electrical barrier created by shaped-emitter layer  140  less interference with adjacent phosphor layers occurs and more electrons strike the desired phosphor layer  195 .  
         [0038]    Also illustrated are spacers  630 , which provide electrical separation of the electrically conductive ITO layer  180  and emitter layer  140 . Spacers  630  are conventionally fabricated from a dielectric material, such as SiO 2 , and further provide mechanical support to transparent layer  190  when the volume between transparent layer  190  and pixel well  145  is evacuated to create a vacuum therein.  
         [0039]    Although not shown, it would be appreciated that a cross-section view through section B-B of FIG. 2 a  would provide a similar deflection of reflected electrons. Hence, reflected electrons are restrained in both a lateral and orthogonal direction.  
         [0040]    [0040]FIG. 3 illustrates a top view of a second aspect of the shaped emitter layer  140  in accordance with the principles of the invention. In this aspect, emitter layer  140  is further shaped to contain a plurality of digits or projections that extend over reflective surface of reflector layer  110 . This addition of digits or projections to shaped-emitter layer  140  is advantageous as it increases the length of edge  142 , which increases the number of emitted electrons. Also, the increased edge length creates additional electrical barriers that further restrain electrons from exiting the pixel region.  
         [0041]    [0041]FIG. 4 a  illustrates a top view of another embodiment  700  of a color FED pixel element in accordance with the principles of the present invention. In this embodiment, pixel  700  is partitioned into three sub-pixel elements, represented as  710   a ,  710   b ,  710   c , which may be associated with red, green and blue phosphor layers, i.e., RGB.  
         [0042]    In a FED display system, each sub-pixel element is independently controlled by column lines  610   a ,  610   b ,  610   c  and row line  620 . Each sub-pixel emitter edge, represented as  142   a ,  142   b ,  142   c , respectively, operates as previously described to prevent electrons emitted from a corresponding reflector layer  110   a ,  110   b ,  110   c , to impinge upon the phosphor layers corresponding to an adjacent sub-pixel element phosphor layer. To maintain a desired 330×330 micron pixel size, each sub-pixel element  710   a ,  710   b ,  710   c , is in the order of 330×110 microns.  
         [0043]    [0043]FIG. 4 b  illustrates a cross-sectional view of embodiment shown in FIG. 4 a , which depicts the containment of electron beams,  635   a ,  635   b ,  635   c , reflected from corresponding reflector layers  110   a ,  110   b ,  110   c , as they are attracted to phosphor layers  755   a ,  755   b ,  755   c . In a preferred embodiment phosphor layers  755   a ,  755   b ,  755   c  emit a light in a band corresponding to one of the primary colors, i.e., red, green, blue. As would be appreciated the selection of colors and the order of the color phosphor layers may be exchanged without altering the scope of the invention.  
         [0044]    [0044]FIG. 5 illustrates a top-view of a preferred embodiment of a color FED pixel element using a shaped-emitter layer similar to that shown in FIG. 3. As previously discussed, the increase of the length of the emitter layer  140  edge  142  is advantageous as it increases the number of electrons emitted.  
         [0045]    Returning to FIG. 2 b , it will be understood, that the confinement of the electron path by shaped-emitter layer  140  is not exact and electrons  635  may continue toward ITO layer  180  on a path that may not be substantially perpendicular to reflector layer  110 . Hence, electron beam paths may cross before reaching the corresponding phosphor layer. One factor where electron beams may cross is the voltage or potential applied to ITO layer  180  as this voltage determines the level of attraction of electrons to ITO layer  180 . Thus, the electrons beam may be focused to a point between ITO layer  180  and reflector layer  110 . Hence, to have a maximum number of electrons strike a corresponding phosphor layer, ITO layer  180  may be positioned approximately at the electron focal point. Table 1 tabulates voltage or values on ITO layer  180  with regard to a distance between ITO layer  180  and reflector layer  110  that achieve reasonable focus with sufficient illumination of the corresponding phosphor layer.  
                             TABLE 1                           Applied ITO Voltage v. Distance                Preferred Voltage Range   Maximum Voltage       Distance   (volts)   (volts)                200 microns   600-800   1000        600 microns   2000-3000   4000       1100 microns   6000-7000   9000                  
 
         [0046]    Accordingly, for a desired distance between ITO layer  190  and reflector layer  110 , the voltage on ITO layer  190  may be selected to achieve a desired level of focus or image sharpness. As the distance between emitter layer  140  and reflector layer  110  is typically in the order of 1-2 microns, there is a negligible difference in the distance between emitter layer  140  and ITO layer  190 .  
         [0047]    The relatively high voltage on ITO layer  180  requires high-voltage phosphor, similar to that used on Cathode Ray Tubes (CRT), rather than the low-voltage phosphor used in current solid-state display technology. The high voltage and high-voltage phosphor is advantageous as it enables the electrons to penetrate deeper into the phosphor layer and reduces the emission of impurities into the evacuated FED pixel element, which occurs when electrons bombard the phosphor. High-voltage phosphor having low sulfur content is preferred.  
         [0048]    As would be understood by those skilled in the art, a sold-state flat panel display using reflected electron FED pixel elements disclosed herein may be formed by arranging a plurality of reflective edge pixel elements  100 , wherein emitter layers  140  are electrically connected in rows and reflector layer  110  are electrically connected in columns. The pixel elements may be formed on a single dielectric surface having spacers positioned thereon to establish a desired distance between pixel elements and transparent layer  190 . The spacers further provide mechanical support when the space between the pixel elements and the transparent surface  190  is evacuated and a vacuum is contained therein.  
         [0049]    Pixel elements may then be selected to produce an image viewable through transparent layer  190  by the application of voltages to selected rows and columns. Control of selected rows and columns may be performed by any means, for example, a processor, through appropriate row controller circuitry and column controller circuitry. As will be appreciated, a processor may be any means, such as a general purpose or special purpose computing system, or may be a hardware configuration, such as a dedicated logic circuit, integrated circuit, Programmable Array Logic, Application Specific Integrated circuit or any device that provides known voltage outputs on corresponding row and column lines in response to known inputs.  
         [0050]    [0050]FIG. 6 illustrates a graph  810  of measured line currents for two selected lines of a display constructed having 160 rows and 170 columns (160×170) of reflective pixel elements in accordance with the principles of the invention having 3 kv applied to ITO layer  180 . In this illustrated example of measured currents, as the reflector layer  110  voltage, represented as • V R , above a known threshold voltage increases, the current drawn by emitter layers of the pixel elements in the selected row,  820   a ,  820   b , referred to as I e , is shown to increase non-linearly, but substantially consistently. Similarly, the reflected current,  830   a ,  830   b , referred to as I a  is only a portion of the emitter current.  
         [0051]    In this specific embodiment, the threshold voltage is 90 volts. However, it would be appreciated that the threshold voltage for electron flow depends on the material selected for emitter layer  140 . Hence, although the characteristics of the present invention is presented with regard to an alpha-carbon material, it would be known by those skilled in the art to substitute a metal, for example, as emitter layer  140  and adjust the threshold voltage accordingly.  
         [0052]    Efficiency of the display may be determined as the power provided to the anode or ITO layer  180  and the power necessary to drive the display: Accordingly efficiency may be determined as:  
       η   =         I   a          V   a             I   a          V   a       +       I   e          V   r                                 
 
         [0053]    Although I e  is larger than I a , the efficiency remains significantly high as the value of V r  is significantly lower than V a .  
         [0054]    The brightness of the FED display may be determined as  
       B   =       η                   I   a          V   a         π                 A                             
 
         [0055]    where A is the area of the spot size on phosphor layer  195 .  
         [0056]    While there has been shown, described, and pointed out, fundamental novel features of the present invention as applied to preferred embodiments thereof, it will be understood that various omissions and substitutions and changes in the apparatus described, in the form and details of the devices disclosed, and in their operation, may be made by those skilled in the art without departing from the spirit of the present invention. For example, it is expressly intended that all combinations of those elements which perform substantially the same function in substantially the same way to achieve the same results are within the scope of the invention. Substitutions of elements from one described embodiment to another are also fully intended and contemplated.