Abstract:
In a semiconductor memory in which redundancy repair is carried out on a block basis, when a defective block of memory cells is replaced by a first redundant block, the adjacent normal block of memory cells closest to the defect, or a part of that normal block, is also replaced by memory cells in a second redundant block. This repair strategy provides a simple way to isolate a defective memory cell so that the defect does not affect non-replaced memory cells.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to redundancy repair in a semiconductor memory such as a programmable read-only memory (PROM), more particularly to block-wise redundancy repair. 
     2. Description of the Related Art 
     Each memory cell (hereinafter, cell) in a PROM typically consists of a single transistor with a floating gate. The memory cell is programmed by injecting charge into or removing charge from the floating gate, thereby altering the threshold value of the transistor. It is known art to provide a PROM with redundant memory cells that can be used to replace defective memory cells, thereby raising the yield of the PROM manufacturing process by enabling defective PROMs to be repaired. In one known redundancy repair scheme, an entire block of memory cells, including the defective memory cell, is replaced with a redundant block of memory cells. One advantage of this scheme is that it reduces the size of the circuitry that generates address signals to select the redundant memory cells. 
       FIG. 8  shows the general structure of a conventional PROM of this type, having a normal cell array  1  and a redundant cell array  2 A.  FIG. 9  shows the circuit structure of these cell arrays. The circuit structures of the cell drain selection circuit  3 , column decoder circuit  4 , defective cell block column redundancy selection circuit  5 , and row decoder circuit  8  in  FIG. 8  are shown in  FIGS. 3 ,  4 ,  5 , and  7 , respectively. 
     The normal cell array  1  in  FIG. 9  is divided into a plurality of blocks. Cell block  10 , for example, includes a pair of bit lines BL 2 , BL 3  and the memory cells ML 2 , MR 2 , ML 3 , MR 3 , etc. connected thereto. The redundant cell array  2 A has a single redundant cell block  20  with a similar structure, including a pair of redundant bit lines RBL 0 , RBL 1  and a plurality of redundant cells RML 0 , RMR 0 , RML 1 , RMR 1 , etc. The columns of cells in the normal cell array  1  are selected by four address signals AY 0 , AY 1 , AY 2 , AY 3 , of which AY 2  and AY 3  distinguish between different cell blocks. 
     In redundancy repair, if the circled cell ML 2  in  FIG. 9  is defective, for example, the entire cell block  10  including the defective cell is replaced with the redundant cell block  20  in the following procedure. 
     From  FIGS. 4 and 9 , it can be seen that cell block  10  is selected when column address signal AY 2  is high and column address signal AY 3  is low. In the defective cell block column redundancy selection circuit  5  in  FIG. 5 , fuse F 50  in fuse-programmable circuit  50  is cut, setting a redundancy enable signal FMAIN to the high logic level. A similar fuse is cut in fuse-programmable circuit  51 , setting a fuse-programmable address signal FY 2  to the high logic level, while the fuse in fuse-programmable circuit  52  is left uncut, setting a fuse-programmable address signal FY 3  to the low logic level. As a result, when column address signal AY 2  is high and column address signal AY 3  is low, the defective cell block column redundancy selection circuit  5  outputs a signal that selects redundant bit line RMBL 0  or RMBL 1 , depending on the value of address signal AY 1 , and redundant data RDATA are read from the redundant cell block  20  and amplified by a redundant sense amplifier. 
       FIG. 10  shows an example of a type of defect that may occur. The source terminal of memory cell transistor ML 2  is shorted to ground through a certain resistance, so that bit line BL 2  is pulled down to the ground level. This problem affects all of the memory cells connected to bit line BL 2 . 
     Moreover, if memory cell transistor ML 2  is programmed to the low-threshold state so that it turns on when word line select signal WL 1  is active, adjacent memory cell MR 1  is also affected. More specifically, if memory cell transistor MR 1  is also programmed to the low threshold state, then when memory cell MR 1  is read, the current iMC that should flow through transistor MR 1  is diminished by the current iL leaking through memory cell ML 2 , so bit line BL 1  receives only the difference current (iMR 1 =iMC−iL). The reduced current reduces the operating margin of the memory with respect to voltage and temperature variations, and if the defect at memory cell ML 2  worsens over time, memory cell MR 1  may become unreadable. 
     On the other side of cell block  10 , if bit line BL 3  or the source terminal of transistor MR 3  leaks current to ground, similar problems will occur when memory cell ML 4  is read. 
     Accordingly, when defective block  10  is replaced by redundant block  20 , it would be convenient if adjacent half-block  11  or  12 , comprising bit line BL 1  or BL 4  and its connected memory cells, could also be replaced, but a conventional memory designed for block-by-block redundancy repair does not permit the replacement of half-blocks, and in any case conventional block redundancy repair schemes do not contemplate the replacement of non-defective blocks or half-blocks. 
     Japanese Patent Application Publication No. H11-273392 (in particular FIGS. 1-3) discloses a PROM in which, when a bit line is defective, the memory cells connected to the bit line are programmed to the high-threshold state to prevent the defect from affecting other memory cells, and the memory cells thus programmed are replaced by redundant cells. This scheme, however, requires memory cells to be replaced on a bit-line basis rather than a block basis, making the circuit that controls the replacement and the circuit that reads data from the redundant memory cells more complex than when redundancy repair is performed block-wise. In particular, it is necessary to store the addresses of individual defective bit lines. The programming process also becomes more complex because it is necessary to program both the redundant memory cells and the memory cells they replace. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide a semiconductor memory in which redundancy repair can be carried out in a way that prevents defective memory cells from affecting non-replaced normal memory cells, without the need to program the defective memory cells or to store the addresses of individual lines of memory cells. 
     In the invented semiconductor memory, a cell block having a defective memory cell is replaced by a first redundant cell block, and a normal cell block adjacent to the defective cell block is replaced by a second redundant cell block. The normal cell block that is replaced is the normal cell block closest to the defective cell in the defective cell block. The defect in the defective cell block is thereby isolated so that it does not directly affect memory cells in blocks that have not been replaced. 
     The normal cell block that is replaced may be a half-block, with only half as many memory cells as the defective cell block, or may be a smaller fraction of a block. If the defective cell block has defective memory cells near both edges, the normal blocks or fractional blocks adjacent to both edges may be replaced with redundant blocks or redundant fractional blocks. 
     The invention also provides a method of selecting redundant memory cells in the first and second redundant cell blocks. The method includes storing the address of the defective cell block, generating a first redundant address signal selecting the first redundant cell block from the stored address of the defective cell block and an input address signal selecting the defective cell block, and generating a second redundant address signal selecting the second redundant cell block from the stored address of the defective cell block and an input address signal selecting a normal cell block or fractional block adjacent to the defective cell block. The second redundant address signal may be generated by incrementing or decrementing the stored address of the defective cell block, appending one or more ‘0’ bits or one or more ‘1’ bits, and comparing the result with the input address. 
     The invented redundancy repair method provides greater operating temperature and voltage margins than conventional methods that replace only the defective block of memory cells, and reduces the probability of failure due to gradual degradation of a defective memory cell. The invented method of selecting memory cells is also simpler than conventional methods in which redundancy repair is carried out on a line-by-line basis. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the attached drawings: 
         FIG. 1  is a block diagram of a semiconductor memory according to a first embodiment of the invention; 
         FIG. 2  is a circuit diagram of the normal and redundant cell arrays in  FIG. 1 ; 
         FIG. 3  is a circuit diagram of the cell drain selection circuit in  FIG. 1 ; 
         FIG. 4  is a circuit diagram of the column decoder circuit in  FIG. 1 ; 
         FIG. 5  is a circuit diagram of the defective cell block column redundancy selection circuit in  FIG. 1 ; 
         FIG. 6A  is a simplified diagram of the circuit in  FIG. 5 ; 
         FIG. 6B  is a simplified circuit diagram of the adjacent cell block column redundancy selection circuit in  FIG. 1 ; 
         FIG. 7  is a circuit diagram of the row decoder circuit in  FIG. 1 ; 
         FIG. 8  is a block diagram of a conventional PROM; 
         FIG. 9  is a circuit diagram of the normal and redundant cell arrays in  FIG. 8 ; and 
         FIG. 10  is a circuit diagram illustrating a problem in the conventional PROM. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters. 
     First Embodiment 
     Referring to  FIG. 1 , the semiconductor memory according to the first embodiment includes a normal cell array  1 , a redundant cell array  2 , a cell drain selection circuit  3 , a column decoder circuit  4 , a defective cell block column redundancy selection circuit  5 , an adjacent cell block column redundancy selection circuit  6 , and a row decoder circuit  8 . The difference between this semiconductor memory and the conventional memory shown in  FIG. 8  is the presence of the adjacent cell block column redundancy selection circuit  6  and an enlargement of the redundant cell array  2 . Both memories receive four column address signals AY 0 , AY 1 , AY 2 , AY 3  and three row address signals AX 1 , AX 2 , AX 3 . 
     Referring to  FIG. 2 , the normal cell array  1  accordingly has 16×8 memory cell transistors, sixteen of which (ML 0 , MR 0 , ML 1 , MR 1 , . . . , ML 7 , MR 7 ) receive word line select signal WL 1 . Current is supplied to the normal cell array  1  through memory cell drain select transistors MDSL 0 , MDSL 1 , . . . , MDSL 7 ; data signals are read out through column switch transistors MBL 0 , MBL 1 , . . . , MBL 7 . 
     In the normal cell array  1 , normal cells ML 2 , MR 2 , ML 3 , MR 3  and other normal cells in the same columns constitute one cell block  10 . Similarly, normal cells ML 0 , MR 0 , ML 1 , MR 1  and other normal cells in the same columns constitute another cell block; normal cells ML 4 , MR 4 , ML 5 , MR 5  and other normal cells in the same columns constitute still another cell block; normal cells ML 6 , MR 6 , ML 7 , MR 7  and other normal cells in the same columns constitute yet another cell block (the columns including cells ML 5 , MR 5 , ML 6 , MR 6 , and ML 7  are not shown). 
     In  FIG. 2 , the redundant cell array  2  comprises 8×8 redundant cells containing redundant memory cell transistors (redundant cells), eight of which (RML 0 , RMR 0 , RML 1 , RMR 1 , . . . , RML 3 , RMR 3 ) receive word line select signal WL 1 . Current is supplied to the redundant cell array  2  through redundant memory cell drain select transistors RMDSL 0 , RMDSL 1 , RMDSL 2 , . . . , RMDSL 4 ; data signals are read out through redundant column switch transistors RMBL 0 , RMBL 1 , . . . , RMBL 3 . 
     In redundant cell array  2 , redundant cells RML 0 , RMR 0 , RML 1 , RMR 1  and other redundant cells in the same redundant columns constitute a first redundant cell block  20  for replacing a defective cell block (e.g. cell block  10 ) in the normal cell array  1 . Redundant cells RML 2 , RMR 2 , RML 3 , RMR 3  and other redundant cells in the same columns constitute a second redundant cell block  21  for replacing a non-defective cell block adjacent to the defective cell block. More accurately, one or two non-defective half-blocks can be replaced. For example, if cell block  10  is defective, the memory cells in redundant cell block  21  may be used to replace adjacent half-block  11  (located to the left of cell block  10 ), adjacent half-block  12  (located to the right of cell block  10 ), or both adjacent half-blocks  11  and  12 . The presence of redundant cell block  21  distinguishes the redundant cell array  2  in embodiment 1 from the conventional redundant cell array  2 A in  FIGS. 8 and 9 . 
     Bit line BL 0  is connected to cell drain select line DSL 0  through normal cell ML 0  and seven other normal cells in the same column, and to cell drain select line DSL 1  through normal cell MR 0  and seven normal cells in the same column. Similarly, bit lines BL 1 , BL 2 , . . . , BL 7  are connected to cell drain select lines DSL 1 , DSL 2 , . . . , DSL 7 , respectively, through normal cells ML 1 , ML 2 , . . . , ML 7 , and seven other normal cells in the same column, and to cell drain select lines DSL 2 , DSL 3 , . . . , and redundant cell drain select line RDSL 0 , respectively through normal cells MR 1 , MR 2 , . . . , MR 7  and seven other normal cells in the same column. 
     Redundant bit line RBL 0  is connected to redundant cell drain select line RDSL 0  through redundant cell RML 0  and seven redundant cells in the same column, and to redundant cell drain select line RDSL 1  through redundant cell RMR 0  and seven redundant cells in the same column. Similarly, redundant bit lines RBL 1 , RBL 2 , RBL 3  are connected to redundant cell drain select lines RDSL 1 , RDSL 2 , RDSL 3 , respectively, through redundant cells RML 1 , RML 2 , RML 3  and seven redundant cells in the same column, and to redundant cell drain select lines RDSL 2 , RDSL 3 , RDSL 4 , respectively, through redundant cells RMR 1 , RMR 2 , RMR 3  and seven redundant cells in the same column. 
     Word select signal WL 1  is input to the gate electrodes of normal cells ML 0 , MR 0 , ML 1 , MR 1 , . . . , ML 7  (not shown), MR 7  and the redundant cells RML 0 , RMR 0 , RML 1 , RMR 1 , . . . , RML 3 , RMR 3  in the same row, connected to the same word line. Similarly, each of the other word line select signals WL 0 , WL 2 , . . . , WL 7  is input to the gate electrodes of sixteen normal cells and eight redundant cells disposed in a single row, on a single word line, in the same columns as normal cells ML 0 , MR 0 , ML 1 , MR 1 , . . . , ML 7 , MR 7  and redundant cells RML 0 , RMR 0 , RML 1 , RMR 1 , . . . , RML 3 , RMR 3 . 
     The cell drain select lines DSL 0 , DSL 1 , . . . , DSL 7  are connected to a cell drain voltage (CDV) power supply through respective cell drain select transistors MDSL 0 , MDSL 1 , . . . , MDSL 7 . The redundant cell drain select lines RDSL 0 , RDSL 1 , . . . , RDSL 4  are connected to the same CDV power supply through respective redundant cell drain select transistors RMDSL 0 , RMDSL 1 , . . . , RMDSL 4 . 
     A cell drain select signal DS 0  is input to the gate electrodes of the even-numbered cell drain select transistors MDSL 0 , MDSL 2 , MDSL 4 , MDSL 6  and redundant cell drain select transistors RMDSL 0 , RMDSL 2 , RMDSL 4 . Another cell drain select signal DS 0  is input to the gate electrodes of the odd-numbered cell drain select transistors MDSL 1 , MDSL 3 , MDSL 5 , MDSL 7  and redundant cell drain select transistors RMDSL 1 , RMDSL 3 . 
     Bit lines BL 0 , BL 1 , . . . , BL 7  are connected through respective column switch transistors MBL 0 , MBL 1 , . . . , MBL 7  to an output terminal from which a read-out data signal (DATA) is supplied to a sense amplifier (not shown). Redundant bit lines RBL 0 , RBL 1 , . . . , RBL 3 , are connected through respective redundant column switch transistors RMBL 0 , RMBL 1 , . . . , RMBL 3  to a redundant output terminal from which a redundant read-out data signal (RDATA) is supplied to a redundant sense amplifier (not shown). 
     Column select signals Y 0 , Y 1 , . . . , Y 7  are input to the gate electrodes of the column switch transistors MBL 0 , MBL 1 , . . . , MBL 7 . Column redundant select signal RYO is input to the gate electrode of redundant column switch transistor RMBL 0 , redundant column select signal RY 1  is input to the gate electrode of redundant column switch transistor RMBL 1 , upper redundant column select signal RYU is input to the gate electrode of redundant column switch transistor RMBL 2 , and lower redundant column select signal RYD is input to the gate electrode of redundant column switch transistor RMBL 3 . 
     The cell drain selection circuit  3  selects the memory cells connected to the left or right of each bit line, depending on the value of address signal AY 0 . When AY 0  is low, the cell drain selection circuit  3  drives cell drain select signal DS 0  high and cell drain select signal DS 1  low, selecting the memory cells connected to the left of the even-numbered bit lines MBL 0 , MBL 2 , . . . , MBL 6  and the memory cells connected to the right of the odd-numbered bit lines MBL 1 , MBL 3 , . . . , MBL 7 . When AY 0  is high, the cell drain selection circuit  3  drives cell drain select signal DS 0  low and cell drain select signal DS 1  high, selecting the memory cells connected to the right of the even-numbered bit lines MBL 0 , MBL 2 , . . . , MBL 6  and the memory cells connected to the left of the odd-numbered bit lines MBL 1 , MBL 3 , . . . , MBL 7 . 
       FIG. 3  shows an exemplary circuit structure of the cell drain selection circuit  3 . The cell drain selection circuit  3  in  FIG. 3  comprises an inverter  130  and a buffer B 30 . Column address signal AY 0  is input to the inverter  130  and the buffer B 30 ; the inverter  130  outputs cell drain select signal DS 0 , and the buffer B 30  outputs cell drain select signal DS 1 . 
       FIG. 4  shows an exemplary circuit structure of the column decoder circuit  4 , which generates the column select signals Y 0 , Y 1 , . . . , Y 7 . The column decoder circuit  4  in  FIG. 4  comprises three-input AND gates A 40 , A 41 , . . . , A 47 . AND gate A 40  receives inverted copies of column address signals AY 1 , AY 2 , AY 3  as inputs, and outputs column select signal Y 0 . AND gate A 41  receives column address signal AY 1  and inverted copies of column address signals AY 2 , AY 3  as inputs, and outputs column select signal Y 1 . AND gate A 42  receives column address signal AY 2  and inverted copies of column address signals AY 1  and AY 3  as inputs, and outputs column select signal Y 2 . AND gate A 43  receives column address signals AY 1  and AY 2  and an inverted copy of column address signal AY 3  as inputs, and outputs column select signal Y 3 . AND gate A 44  receives column address signal AY 3  and inverted copies of column address signals AY 1  and AY 2  as inputs, and outputs column select signal Y 4 . AND gate A 45  receives column address signals AY 1  and AY 3  and an inverted copy of column address signal AY 2  as inputs, and outputs column select signal Y 5 . AND gate A 46  receives column address signals AY 2  and AY 3  and an inverted copy of column address signal AY 1  as inputs, and outputs column select signal Y 6 . AND gate A 47  receives column address signals AY 1 , AY 2 , AY 3  as inputs, and outputs column select signal Y 7 . 
       FIG. 5  shows an exemplary circuit structure of the defective cell block column redundancy selection circuit  5 , which generates the column select signals RY 0 , RY 1  for the first redundant cell block  20 . The defective cell block column redundancy selection circuit  5  in  FIG. 5  comprises three fuse-programmable circuits  50 ,  51 ,  52 , two address selection circuits  53 ,  54 , and an address decoding circuit  55 . 
     Fuse-programmable circuit  50  generates a redundancy enable signal FMAIN that is programmed to the high logic level when redundancy repair is necessary and to the low logic level when redundancy repair is not necessary. When redundancy repair is necessary, fuse-programmable circuits  51  and  52  store the address of the defective cell block. 
     The fuse-programmable circuits  50 ,  51 , and  52  have identical structures, each including a resistor and fuse. In fuse-programmable circuit  50 , for example, one end of the resistor R 50  is connected to a power supply node, one end of the fuse F 50  is connected to the other end of the resistor R 50 , and the other end of the fuse F 50  is connected to a ground node. The redundancy enable signal FMAIN is output from a node at which the resistor R 50  and fuse F 50  of fuse-programmable circuit  50  are interconnected. A fuse programmable address signal FY 2  is output from a node at which the resistor and fuse in fuse-programmable circuit  51  are interconnected. Another fuse programmable address signal FY 3  is output from a node at which the resistor and fuse in fuse programmable circuit  52  of are interconnected. 
     The address selection circuits  53  and  54  are identically structured as exclusive-NOR (EXNOR) gates, each including a pair of inverters I 50 , I 51  and a pair of MOS switches M 50  and M 51 . Each address selection circuit compares one address bit with one fuse programmable address signal and generates a redundant column address signal. The redundant column address signal is high if the address bit and fuse programmable address signal have the same logic level, and low if they have different logic levels. 
     More specifically, address selection circuit  53  selects column address signal AY 2  or an inverted copy thereof according to the logic level of fuse programmable address signal FY 2 , and outputs the selected signal as a redundant column address signal FA 2 . Address selection circuit  54  selects column address signal AY 3  or an inverted copy thereof the according to the logic level of fuse programmable address signal FY 3 , and outputs the selected signal as a redundant column address signal FA 3 . 
     In the address selection circuit  53 , fuse programmable address signal FY 2  is input to inverter I 50 , the gate electrode of the n-channel metal-oxide-semiconductor (NMOS) transistor of MOS switch M 50 , and the gate electrode of the p-channel metal-oxide-semiconductor (PMOS) transistor of MOS switch M 51 . The inverted copy of fuse programmable address signal FY 2  output from inverter I 50  is input to the gate electrode of the PMOS transistor of MOS switch M 50  and the gate electrode of the NMOS transistor of MOS switch M 51 . Therefore, when MOS switch M 50  is on, MOS switch M 51  is off, and when MOS switch M 50  is off, MOS switch M 51  is on. Column address signal AY 2  is input to MOS switch M 50  and inverter I 51 , and the inverted copy of column address signal AY 2  output from inverter I 51  is input to MOS switch M 51 . The outputs of MOS switches M 50  and M 51  are interconnected at a node from which redundant column address signal FA 2  is output. 
     In identically structured address selection circuit  54 , fuse programmable address signal FY 3  is input to inverter I 50 , the gate electrodes of the NMOS transistor of MOS switch M 50 , and the gate electrode of the PMOS transistor of MOS switch M 51  (the inverters I 50 , I 51  and MOS switches M 50 , M 51  in address selection circuit  54  are not shown). The inverted copy of fuse programmable address signal FY 3  output from inverter I 50  is input to the gate electrode of the PMOS transistor of MOS switch M 50  and the gate electrode of the NMOS transistor of MOS switch M 51 . As in address selection circuit  53 , when MOS switch M 50  is on, MOS switch M 51  is off, and when MOS switch M 50  is off, MOS switch M 51  is on. Column address signal AY 3  is input to MOS switch M 50  and inverter I 51 , and the inverted copy of column address signal AY 3  output from inverter I 51  is input to MOS switch M 51 . The outputs of MOS switches M 50  and M 51  are interconnected at a node from which redundant column address signal FA 3  is output. 
     The address decoding circuit  55  generates the redundant column select signals RY 0 , RY 1  from column address signal AY 1 , redundant column address signals FA 2 , FA 3 , and the redundancy enable signal FMAIN. The address decoding circuit  55  comprises a three-input AND gate A 50  and a pair of two-input AND gates A 51  and A 52 . Redundancy enable signal FMAIN and redundant column address signals FA 2  and FA 3  are input to AND gate A 50 . AND gate A 51  receives the output signal of AND gate A 50  and an inverted copy of column address signal AY 1  as inputs, and outputs redundant column select signal RY 0 . AND gate A 52  receives the output signal of AND gate A 50  and column address signal AY 1  as inputs, and outputs redundant column select signal RY 1 . 
       FIG. 6A  shows a schematic representation of the circuit structure of the defective cell block column redundancy selection circuit  5  in  FIG. 5 .  FIG. 6B  shows a similarly schematic representation of the circuit structure of the adjacent cell block column redundancy selection circuit  6 . The adjacent cell block column redundancy selection circuit  6  comprises fuse-programmable circuits  56 ,  57 , adjacent address generating circuits  60 ,  61 ,  62 ,  63 ,  64 ,  65 , address selection circuits  66 ,  67 ,  68 ,  69 ,  70 ,  71 , and address decoding circuits  72 ,  73 . Fuse-programmable circuit  56 , adjacent address generating circuits  60 ,  61 ,  62 , address selection circuits  66 ,  67 ,  68 , and address decoding circuit  72  constitute an upper column redundancy selection circuit  74 ; fuse-programmable circuit  57 , adjacent address generating circuits  63 ,  64 ,  65 , address selection circuits  69 ,  70 ,  71 , and address decoding circuit  73  constitute a lower column redundancy selection circuit. 
     The adjacent cell block column redundancy selection circuit  6  selects one half of redundant cell block  21  to replace a half-block adjacent to a defective cell block in the normal cell array  1 . As inputs, both the upper and lower column redundancy selection circuits  74 ,  75  receive column address signals AY 1 , AY 2 , AY 3  and the fuse programmable address FY 3 , FY 2  of the defective block cell. The fuse programmable address signals FY 3 , FY 2  are received from fuse-programmable circuits  51  and  52  in the defective cell block column redundancy selection circuit  5 . 
     Upper column redundancy selection circuit  74  is programmable to select the lower half of redundant cell block  21  by driving the upper redundant column select signal RYU. The lower half of redundant cell block  21  is used to replace a normal half-block near a defective cell located in the upper (right) half of a defective cell block. Lower column redundancy selection circuit  75  is programmable to select the upper half of redundant cell block  21  by driving the lower redundant column select signal RYD. The upper half of redundant cell block  21  is used to replace a normal half-block near a defective cell located in the lower (left) half of a defective cell block. 
     Fuse-programmable circuits  56  and  57  have same structure as fuse-programmable circuits  50 ,  51  and  52  in the defective cell block column redundancy selection circuit  5 , each comprising a resistor and fuse connected in series between the power supply and ground to generate an output signal from the node at which they are interconnected. Fuse-programmable circuit  56  generates an upper redundancy enable signal FMAINU; fuse-programmable circuit  57  generates a lower redundancy enable signal FMAIND. 
     Adjacent address generating circuits  60 ,  61 , and  62  form an incrementer that increments the fuse-programmable address FY 3 , FY 2  of the defective cell block and appends a ‘0’ bit, thereby generating the address of the upper-adjacent (right-adjacent) half-block. These circuits  60 ,  61 ,  62  have identical half-adder structures, each comprising a two-input exclusive-OR (EXOR) gate EO 60  and a two-input AND gate A 60 . In adjacent address generating circuit  60 , the EXOR gate EO 60  takes the exclusive logical OR of two input signals INC 0  and FY 1 U that are both tied to the high logic level, and outputs a first upper fuse programmable address signal FYU 1  that is held at the low logic level. The AND gate A 60  in adjacent address generating circuit  60  takes the logical AND of the same two input signals INC 0  (high) and FY 1 U (high), and outputs a signal INC 1  that is held at the high logic level. The EXOR gate in adjacent address generating circuit  61  takes the exclusive logical OR of INC 1  (high) and fuse programmable address signal FY 2 , and outputs a second upper fuse programmable address signal FYU 2 , while the AND gate in adjacent address generating circuit  61  takes the logical AND of INC 1  (high) and FY 2 , and outputs a carry signal INC 2 . The EXOR gate in adjacent address generating circuit  62  takes the logical exclusive OR of INC 2  and fuse programmable address signal FY 3 , and outputs a third upper fuse programmable address signal FYU 3 . 
     Adjacent address generating circuits  63 ,  64 , and  65  form a decrementer that decrements the fuse-programmable address FY 3 , FY 2  of the defective cell block and appends a ‘1’ bit, thereby generating the address of the lower-adjacent (left-adjacent) half-block. These circuits  63 ,  64 ,  65  have identical structures, each comprising a two-input exclusive-NOR (EXNOR) gate EN 60  and a two-input OR gate  060 . In adjacent address generating circuit  63 , the EXNOR gate EN 60  takes the logical exclusive NOR of two input signals DEC 0  and FY 1 D that are tied to the low logic level, and outputs a first lower fuse programmable address signal FYD 1  that is held at the high logic level; the OR gate  060  takes the logical OR of input signals DEC 0  (low) and FY 1 D (low) and outputs a signal DEC 1  that is held at the low logic level. The EXNOR gate in adjacent address generating circuit  64  takes the logical exclusive NOR of DEC 1  (low) and FY 2 , and outputs a second lower fuse programmable address signal FYD 2 , while the OR gate in adjacent address generating circuit  64  takes the logical OR of DEC 1  (low) and FY 2 , and outputs a signal DEC 2 . The EXNOR gate in adjacent address generating circuit  65  takes the logical exclusive NOR of DEC 2  and FY 3 , and outputs a third lower fuse programmable address signal FYD 3 . 
     The AND gate in adjacent address generating circuit  62  and the OR gate in adjacent address generating circuit  65  are not used and may be omitted. 
     Address selection circuits  66 ,  67 ,  68 ,  69 ,  70  and  71  have the same structure as address selection circuits  53  and  54  in the defective cell block column redundancy selection circuit  5  (see  FIG. 5 ), each comprising a pair of inverters I 50 , I 51  and a pair of MOS switches M 50 , M 51  interconnected to function as an EXNOR gate. These circuits compare input column address signals A 3 , A 2 , A 1  individually with the upper fuse programmable address signals FYU 3 , FYU 2 , FYU 1  and the lower fuse programmable address signals FYD 3 , FYD 2 , FYD 1  to determine whether or not they match. 
     In upper column redundancy selection circuit  74 , address selection circuit  66  selects column address signal AY 1  or an inverted copy thereof according to the first upper fuse programmable address signal FYU 1 , and outputs a first upper redundant column address signal FAU 1 . Address selection circuit  67  selects column address signal AY 2  or an inverted copy thereof according to the second upper fuse programmable address signal FYU 2 , and outputs a second upper redundant column address signal FAU 2 . Address selection circuit  68  selects column address signal AY 3  or an inverted copy thereof according to the third upper fuse programmable address signal FYU 3 , and outputs a third upper redundant column address signal FAU 3 . 
     In lower column redundancy selection circuit  75 , address selection circuit  69  selects column address signal AY 1  or an inverted copy thereof according to the first lower fuse programmable address signal FYD 1 , and outputs a first redundant column lower address signal FAD 1 . Address selection circuit  70  selects column address signal AY 2  or an inverted copy thereof according to the second lower fuse programmable address signal FYD 2 , and outputs a second redundant column lower address signal FAD 2 . Address selection circuit  71  selects column address signal AY 3  or an inverted copy thereof according to the third programmable lower address signal FYD 3 , and outputs a third redundant column lower address signal FAD 3 . 
     Address decoding circuits  72  and  73  have identical structures, each comprising a four-input AND gate A 61 . The AND gate A 61  in address decoding circuit  72  receives the upper redundancy enable signal FMAINU and upper redundant column address signals FAU 1 , FAU 2  and FAU 3  as inputs, and outputs the upper redundant column select signal RYU. The similar AND gate (not shown) in address decoding circuit  73  receives the lower redundancy enable signal FMAIND and lower redundant column address signals FAD 1 , FAD 2  and FAD 3  as inputs, and outputs the lower redundant column select signal RYD. 
       FIG. 7  shows the circuit structure of the row decoder circuit  8 . The row decoder circuit  8  comprises three-input AND gates A 80 , A 81 , . . . , A 87 . AND gate A 80  receives inverted copies of row address signals AX 1 , AX 2 , and AX 3  as inputs, and outputs word line select signal WL 0 . AND gate A 81  receives row address signal AX 1  and inverted copies of row address signals AX 2  and AX 3  as inputs, and outputs word line select signal WL 1 . AND gate A 82  receives row address signal AX 2  and inverted copies of row address signal AX 1  and AX 3  as inputs, and outputs word line select signal WL 2 . AND gate A 83  receives row address signals AX 1  and AX 2  and an inverted copy of row address signal AX 3  as inputs, and outputs word line select signal WL 3 . AND gate A 84  receives row address signal AX 3  and inverted copies of row address signal AX 1  and AX 2  as inputs, and outputs word line select signal WL 5 . AND gate A 85  receives row address signals AX 1  and AX 3  and an inverted copy of row address AX 2  as inputs, and outputs word line select signal WL 5 . AND gate A 86  receives row address signals AX 2  and AX 3  and an inverted copy of row address AX 1  as inputs, and outputs word line select signal WL 6 . AND gate A 87  receives row address signals AX 1 , AX 2 , AX 3  as inputs, and outputs word line select signal WL 7 . 
     Another circuit (not shown) selects the output of the normal sense amplifier when all of the redundant column select signals RY 0 , RY 1 , RYU, RYD are low and selects the output of the redundant sense amplifier when one of the redundant column select signals RY 0 , RY 1 , RYU, RYD is high. 
     Normal Data Read-Out 
     Next, the reading of data from cell ML 2  in cell block  10  in  FIG. 2  will be described Under the assumption that cell block  10  is non-defective, using the letters H and L to indicate the high (‘1’) and low (‘0’) logic levels, respectively. 
     If the column address signal inputs (AY 0 , AY 1 , AY 2 , AY 3 ) are (L, L, H, L) and the row address signals (AX 1 , AX 2 , AX 3 ) are (H, L, L) are input, then the outputs (DS 0 , DS 1 ) of the cell drain selection circuit  3  are (H, L), the outputs (Y 0 , Y 1 , Y 2 , Y 3 -Y 7 ) of the column decoder circuit  4  are (L, L, H, L), and the outputs (WL 0 , WL 1 , WL 2 -WL 7 ) of the row decoder circuit  8  are (L, H, L). These signals select normal cell ML 2  and read out its data as follows. 
     As cell drain select signal DS 0  is high, cell drain select transistor MDSL 2  turns on and the cell drain voltage CDV is supplied to cell drain select line DSL 2 . As word line select signal WL 1  is high, the memory cell transistors that have been programmed to the low threshold level in the row including cells ML 0  to MR 7  and redundant cells RML 0  to RMR 3  turn on. 
     As column address signals (AY 3 , AY 2 , AY 1 ) are (L, H, L) the column select signals (Y 0 , Y 1 , Y 2 , Y 3 -Y 7 ) output from the column decoder circuit  4  are (L, L, H, L) and column switch transistor MBL 2  turns on. 
     By activating word line select signal WL 1  and turning on cell drain select transistor MDSL 2  and column switch transistor MBL 2 , address signals (AY 0 , AY 1 , AY 2 , AY 3 , AX 1 , AX 2 , AX 3 ) with values (L, L, H, L, H, L, L) select normal cell ML 2 . The read-out data signal (DATA) output from the output terminal of the normal cell array  1  is amplified by the sense amplifier (not shown), going high or low depending on whether normal cell ML 2  has been programmed to the low-threshold or high-threshold state. 
     Redundancy Repair ( 1 ) 
     If cell ML 2  is defective, its cell block  10  is replaced with redundant cell block  20  in the redundant cell array  2 , and the half-block  11  on the left side of cell block  10 , adjacent to the defective cell ML 2 , is replaced with the upper of the two redundant half-blocks in redundant cell block  21 . As a result, normal cell ML 1  is replaced by redundant cell RML 3 , normal cell MR 1  by redundant cell RMR 3 , defective cell ML 2  by redundant cell RML 0 , normal cell MR 2  by redundant cell RMR 0 , normal cell ML 3  by redundant cell RML 1 , and normal cell MR 3  by redundant cell RMR 1 . 
     In general, when any cell connected to the leftmost bit line BL 2  in cell block  10  is defective, the adjacent half-block  11  is replaced with the upper half-block of redundant cell block  21  in the redundant cell array  2 . The procedure for redundancy repair of cell block  10  with redundant cell block  20  and replacement of half-block  11  with the upper half-block of redundant cell block  21  includes the cutting of fuses in the defective cell block column redundancy selection circuit  5  and lower column redundancy selection circuit  75 . 
     In the defective cell block column redundancy selection circuit  5 , fuse F 50  in fuse-programmable circuit  50  is cut to enable redundancy repair. When the defective cell ML 2  is selected, column address signals (AY 3 , AY 2 , AY 1 ) have values (L, H, L) as column address signal AY 2  is high, the fuse in fuse-programmable circuit  51  is cut, and as column address signal AY 3  is low, the fuse in fuse-programmable circuit  52  is left connected. Therefore, the outputs (FMAIN, FY 2 , FY 3 ) of fuse-programmable circuits  50 ,  51 ,  52  are (H, H, L). 
     As fuse programmable address signal FY 2  is high, the address selection circuit  53  outputs column address signal AY 2  as redundant column address signal FA 2 . As fuse programmable address signal FY 3  is low, address selection circuit  54  outputs an inverted copy of column address signal AY 3  as redundant column address FA 3 . 
     When column address signals AY 2  and AY 3  are high and low, respectively, the inputs (FMAIN, FA 2 , FA 3 ) into the AND gate A 50  in the address decoding circuit  55  are (H, H, H), and the output from AND gate A 50  is high. When column address signal AY 2  is low or column address signal AY 3  is high, the three inputs of AND gate A 50  are not all high so the output from AND gate A 50  is low. 
     Therefore, when column address signal AY 3  and fuse programmable address signal FY 3  have the same value, and column address signal AY 2  and fuse programmable address signal FY 2  have the same value, the defective cell block column redundancy selection circuit  5  outputs redundant column select signals (RY 0 , RY 1 ) with values (H, L) if column address signal AY 1  is low, or (L, H) if column address signal AY 1  is high. When the value of column address signal AY 3  is not the same as the value of fuse programmable address signal FY 3 , or the value of column address signal AY 2  is not same as the value of fuse programmable address signal FY 2 , the redundant column select signals (RY 0 , RY 1 ) are both low (L, L). 
     In the adjacent cell block column redundancy selection circuit  6 , the fuse in fuse-programmable circuit  57  is cut to enable the replacement of the half-block  11  located left of cell block  10 . The fuse in fuse-programmable circuit  56  is left connected (the half-block  12  located to the right of cell block  10  is not replaced). Thus, the outputs (FMAINU, FMAIND) from fuse-programmable circuits  56  and  57  are (L, H). 
     In lower column redundancy selection circuit  75 , as the inputs (DEC 0 , FY 1 D) into adjacent address generating circuit  63  are (L, L), the outputs (FYD 1 , DEC 1 ) from adjacent address generating circuit  63  are (H, L). As the inputs (DEC 1 , FY 2 ) into adjacent address generating circuit  64  are (L, H), the outputs (FYD 2 , DEC 2 ) from adjacent address generating circuit  64  are (L, H). As the inputs (DEC 2 , FY 3 ) into adjacent address generating circuit  65  are (H, L), the lower fuse programmable address signal FYD 3  output from adjacent address generating circuit  65  is low. Thus, the outputs (FYD 1 , FYD 2 , FYD 3 ) from adjacent address generating circuits  63 ,  64 , and  65  are (H, L, L). 
     As lower fuse programmable address signal FYD 1  is high, column address signal AY 1  is output from address selection circuit  69  as lower redundant column address signal FAD 1 . As lower fuse programmable address signal FYD 2  is low, the inverted copy of column address signal AY 2  is output from address selection circuit  70  as lower redundant column address signal FAD 2 . As the lower fuse programmable address signal FYD 3  is low, the inverted copy of column address signal AY 3  is output from address selection circuit  71  as lower redundant column address signal FAD 3 . 
     When column address signals AY 1 , AY 2 , AY 3  are (H, L, L), the four inputs (FMAIND, FAD 1 , FAD 2 , FAD 3 ) into the AND gate in address decoding circuit  73  are (H, H, H, H), and the lower redundant column select signal RYD output therefrom is high. If column address signal AY 1  is low, column address signal AY 2  is high, or column address signal AY 3  is high, the four inputs into this AND gate are not all high, and the lower redundant column select signal RYD is low. 
     Therefore, the lower redundant column select signal RYD output from lower column redundancy selection circuit  75  is high when the value of column address signal AY 3  is the same as the value of lower fuse programmable address signal FYD 3 , the value of column address signal AY 2  is the same as the value of lower fuse programmable address signal FYD 2 , and the value of column address signal AY 1  is the same as the value of lower fuse programmable address signal FYD 1 . Otherwise, the lower redundant column select signal RYD output from lower column redundancy selection circuit  75  is low. 
     In upper column redundancy selection circuit  74 , as the inputs (INC 0 , FY 1 U) into adjacent address generating circuit  60  are (H, H), the outputs (FYU 1 , INC 1 ) from adjacent address generating circuit  61  are (L, H). As the inputs (INC 1 , FY 2 ) to adjacent address generating circuit  61  are (H, H), the outputs (FYU 2 , INC 2 ) from adjacent address generating circuit  64  are (L, H). As the inputs (INC 2 , FY 3 ) to adjacent address generating circuit  62  are (H, L), the upper fuse programmable address signal FYU 3  output from adjacent address generating circuit  62  is high. Thus, the outputs (FYU 1 , FYU 2 , FYU 3 ) from adjacent address generating circuits  60 ,  61 ,  62  are (L, L, H). 
     As upper fuse programmable address signal FYU 1  is low, an inverted copy of column address signal AY 1  is output from address selection circuit  66  as upper redundant column address signal FAU 1 . As upper fuse programmable address signal FYU 2  is low, an inverted copy of column address signal AY 2  is output from address selection circuit  67  as upper redundant column address signal FAU 2 . As upper fuse programmable address signal FYU 3  is high, column address signal AY 3  is output from address selection circuit  68  as upper redundant column address signal FAU 3 . 
     When column address signals AY 1 , AY 2 , AY 3  are (L, L, H), the corresponding inputs (FAU 1 , FAU 2 , FAU 3 ) into the AND gate A 61  in address decoding circuit  72  are (H, H, H), but the upper redundancy enable signal FMAINU is low, so the fourth input to AND gate A 61  is low and the upper redundant column select signal RYU output from AND gate A 61  is low. Other values of the column address signals AY 1 , AY 2 , AY 3  also produce a low output from AND gate A 61 . Therefore, the upper redundant column select signal RYU output from upper column redundancy selection circuit  74  is always low, regardless of the value of column address signal AY 3 , AY 2 , or AY 1 . 
     Following the above redundancy repair and replacement, data from the redundant cell blocks  20 ,  21  are read in place of data from the defective cell block  10  and adjacent normal half-block  11 . 
     Reading of Data from First Redundant Cell Block The operation by which redundant cell RML 0  in redundant cell block  20  is read in place of defective cell ML 2  in cell block  10  proceeds as follows. 
     When the input column address signals (AY 0 , AY 1 , AY 2 , AY 3 ) are (L, L, H, L) and the input row address signals (AX 1 , AX 2 , AX 3 ) are (H, L, L), the drain select signals (DS 0 , DS 1 ) output from the cell drain selection circuit  3  are (H, L), the column select signals (Y 0 , Y 1 , Y 2 , Y 3 -Y 7 ) output from the column decoder circuit  4  are (L, L, H, L), and the word line select signals (WL 0 , WL 1 , WL 2 -WL 7 ) output from the row decoder circuit  8  are (L, H, L). The input address therefore selects defective cell ML 2 , but because of the redundancy repair, the redundant sense amplifier reads data from redundant cell RML 0  instead, according to the following procedure. 
     As cell drain select signal DS 0  is high, redundant cell drain select transistor RMDSL 0  turns on and the cell drain voltage CDV is supplied to redundant cell drain select line RDSL 0 . As word line select signal WL 1  is high, the memory cell transistors that have been programmed to the low threshold level in the row including cells ML 0  to MR 7  and redundant cells RML 0  to RMR 3  turn on. 
     In the defective cell block column redundancy selection circuit  5 , column address signals (AY 3 , AY 2 , AY 1 ) are (L, H, L), the value of column address signal AY 3  being the same as the value of fuse programmable address signal FY 3 , and the value of column address signal AY 2  being the same as the value of fuse programmable address signal FY 2 . Therefore, redundant column address signals (FA 2 , FA 3 ) are (H, H). Since the redundancy enable signal FMAIN is also high and column address signal AY 1  is low, redundant column select signal RY 0  is high. The other redundant column select signal RY 1  output from the defective cell block column redundancy selection circuit  5  is low. 
     In upper column redundancy selection circuit  74 , column address signals (AY 3 , AY 2 , AY 1 ) are (L, H, L), and the value of column address signal AY 1  is the same as the value of upper fuse programmable address signal FYU 1 , but the value of column address signal AY 3  is not the same as the value of upper fuse programmable address signal FYU 3  and the value of column address signal AY 2  is not the same as the value of upper fuse programmable address signal FYD 2 . The upper redundant column address signals (FAU 3 , FAU 2 , FAU 1 ) are accordingly (L, L, H), and moreover, the upper redundancy enable signal FMAINU is low. The upper redundant column select signal RYU is therefore low. 
     In lower column redundancy selection circuit  75 , column address signals (AY 3 , AY 2 , AY 1 ) are (L, H, L), and the value of column address signal AY 3  is the same as the value of lower fuse programmable address signal FYD 3 , but the value of column address signal AY 2  is not the same as the value of lower fuse programmable address signal FYD 2 , and the value of column address signal AY 1  is not the same as the value of lower fuse programmable address signal FYD 1 . The lower redundant column address signals (FAD 3 , FAD 2 , FAD 1 ) are accordingly (H, L, L), so the lower redundant column select signal RYD is low. 
     The outputs (RYO, RY 1 , RYU, RYD) from the defective cell block column redundancy selection circuit  5  and adjacent cell block column redundancy selection circuit  6  are accordingly (H, L, L, L). Redundant column switch transistor RMBL 0  turns on while the other redundant column switch transistors RMBL 1 , RMBL 2 , RMBL 3  remain off. 
     As noted above, the low value of column address signal AY 0  activates drain select signal DS 0 . Thus, when address signals (AY 0 , AY 1 , AY 2 , AY 3 , AX 1 , AX 2 , AX 3 )=(L, L, H, L, H, L, L) for selecting defective cell ML 2  are input, word line select signal WL 1  is driven high, and redundant cell drain select transistor RMDSL 0  and redundant column switch transistor RMBL 0  turn on, selecting the redundant cell RML 0  that replaces defective cell ML 2 . The data bit programmed into this redundant cell RML 0  is output as redundant read-out data RDATA from the output terminal of the redundant cell array  2  to the redundant sense amplifier. 
     Data programmed into other redundant cells in the first redundant cell block  20  are similarly read in place of data in the corresponding memory cells in cell block  10 . 
     Reading of Data from Second Redundant Cell Block ( 1 ) The operation by which redundant cell RMR 3  in redundant cell block  21  is read in place of normal cell MR 1  in half-block  11  proceeds as follows. 
     When the input column address signals (AY 0 , AY 1 , AY 2 , AY 3 ) are (L, H, L, L) and the input row address signals (AX 1 , AX 2 , AX 3 ) are (H, L, L), the drain select signals (DS 0 , DS 1 ) output from the cell drain selection circuit  3  are (H, L), the column select signals (Y 0 , Y 1 , Y 2 -Y 7 ) output from the column decoder circuit  4  are (L, H, L), and the word line select signals (WL 0 , WL 1 , WL 2 -WL 7 ) output from the row decoder circuit  8  are (L, H, L). The input address therefore selects the cell MR 1  left-adjacent to the defective cell ML 2 , but because of the redundancy repair, the redundant sense amplifier reads data from redundant cell RMR 3  instead. 
     As cell drain select signal DS 0  is high, redundant cell drain select transistor RMDSL 4  turns on and the cell drain voltage CDV is applied to redundant cell drain select line RDSL 4 . As word line select signal WL 1  is high, the memory cell transistors that have been programmed to the low threshold level in the row including cells ML 0  to MR 7  and redundant cells RML 0  to RMR 3  turn on. 
     In the defective cell block column redundancy selection circuit  5 , since column address signals (AY 3 , AY 2 , AY 1 ) are (L, L, H), the value of column address signal AY 3  is the same as the value of fuse programmable address signal FY 3 , but the value of column address signal AY 2  is not the same as the value of fuse programmable address signal FY 2 . Redundant column address signals FA 2 , FA 3  are therefore (L, H), and redundant column select signals RY 0 , RY 1  are (L, L). 
     In the upper column redundancy selection circuit  74 , since column address signals (AY 3 , AY 2 , AY 1 ) are (L, L, H), the value of column address signal AY 2  is the same as the value of upper fuse programmable address signal FYU 2 , but the value of column address signal AY 3  is not the same as the value of upper fuse programmable address signal FYU 3 , and the value of column address signal AY 1  is not the same as the value of upper fuse programmable address signal FYU 1 . The upper redundant column address signals (FAU 3 , FAU 2 , FAUL) are accordingly (L, H, L), and moreover, the upper redundancy enable signal FMAINU is low. The upper redundant column select signal RYU is therefore low. 
     In the lower column redundancy selection circuit  75 , since column address signals (AY 3 , AY 2 , AY 1 ) are (L, L, H), the value of column address signal AY 3  is the same as the value of lower fuse programmable address signal FYD 3 , the value of column address signal AY 2  is the same as the value of lower fuse programmable address signal FYD 2 , and the value of column address signal AY 1  is the same as the value of the lower fuse programmable address signal FYD 1 . Therefore, the lower redundant column address signals (FAD 3 , FAD 2 , FAD 1 ) are (H, H, H). As the lower redundancy enable signal FMAIND is high, the lower redundant column select signal RYD is high. 
     The outputs (RY 0 , RY 1 , RYU, RYD) from the defective cell block column redundancy selection circuit  5  and adjacent cell block column redundancy selection circuit  6  are therefore (L, L, L, H). Redundant column switch transistor RMBL 3  turns on while the other redundant column switch transistors RMBL 0 , RMBL 1 , RMBL 2  remain off. 
     Thus when address signals (AY 0 , AY 1 , AY 2 , AY 3 , AX 1 , AX 2 , AX 3 )=(L, H, L, L, H, L, L) for selecting the normal cell MR 1  left-adjacent to defective cell ML 2  are input, word line select signal WL 1  is driven high, and redundant cell drain select transistor RMDSL 4  and redundant column switch transistor RMBL 3  turn on, selecting the redundant cell RMR 3  that replaces normal cell MR 1 . The data bit programmed into this redundant cell RMR 3  is output as redundant read-out data RDATA from the output terminal of the redundant cell array  2  to the redundant sense amplifier. 
     Data programmed into other redundant cells in the upper half of the second redundant cell block  21  are similarly read in place of data in the corresponding memory cells in half-block  11 . 
     Replacement of Both Adjacent Half-Blocks 
     If normal cell MR 3  in the cell array in  FIG. 2  is defective, the normal half-block  12  adjacent to the defective cell MR 3  on the right side of cell block  10  is replaced with the lower of the two redundant half-blocks in redundant cell block  21 . If both cells ML 2  and MR 3  are defective, both half-blocks  11  and  12  adjacent to the defective cell block  10  are replaced by the second redundant cell block  21  in the redundant cell array  2 , each being replaced by a separate redundant half-block in the single redundant cell block  21 . 
     When both cells ML 2  and MR 3  are defective, normal cell ML 1  is replaced by redundant cell RML 3 , normal cell MR 1  by redundant cell RMR 3 , defective cell ML 2  by redundant cell RML 0 , normal cell MR 2  by redundant cell RML 0 , normal cell ML 3  by redundant cell RML 1 , defective cell MR 3  by redundant cell RMR 1 , normal cell ML 4  by redundant cell RML 2 , and normal cell MR 4  by redundant cell RMR 2 . The replacement of cells in the defective cell block  10  and its left-adjacent normal half-block  11  proceeds as described above. The procedure for replacing the half-block  12  right-adjacent to cell block  10  with the lower half-block in the second redundant cell block  21  proceeds as follows. 
     In the adjacent cell block column redundancy selection circuit  6 , in order to enable redundancy repair of the half-block  12  located to the right of cell block  10 , the fuse in fuse-programmable circuit  56  is additionally cut. The two the outputs (FMAINU, FMAIND) of fuse programmable circuits  56  and  57  are now both high (H, H). 
     In upper column redundancy selection circuit  74 , when column address signals AY 1 , AY 2 , AY 3  are (L, L, H), the four inputs (FMAINU, FAU 1 , FAU 2 , FAU 3 ) into the AND gate A 61  in address decoding circuit  72  are (H, H, H, H), and the upper redundant column select signal RYU output therefrom is high. If column address signal AY 1  is high, column address signal AY 2  is high, or column address signal AY 3  is low high, then the four inputs into AND gate A 61  are not all high, and the upper redundant column select signal RYU is low. 
     Therefore, the upper redundant column select signal RYU output from upper column redundancy selection circuit  74  is high when the value of column address signal AY 3  is the same as the value of upper fuse programmable address signal FYU 3 , the value of column address signal AY 2  is the same as the value of upper fuse programmable address signal FYU 2 , and the value of column address signal AY 1  is the same as the value of upper fuse programmable address signal FYU 1 . Otherwise, the upper redundant column select signal RYU output from upper column redundancy selection circuit  74  is low. 
     Reading of Data from Second Redundant Cell Block ( 2 ) 
     The operation by which redundant cell RML 2  in redundant cell block  21  is read in place of normal cell ML 4  in half-block  12  proceeds as follows. 
     When the input column address signals (AY 0 , AY 1 , AY 2 , AY 3 ) are (L, L, L, H) and the input row address signals (AX 1 , AX 2 , AX 3 ) are (H, L, L), the drain select signals (DS 0 , DS 1 ) output from the cell drain selection circuit  3  are (H, L), the column select signals (Y 0  to Y 3 , Y 4 , Y 5 -Y 7 ) output from the column decoder circuit  4  are (L, H, L), and the word line select signals (WL 0 , WL 1 , WL 2 -WL 7 ) output from the row decoder circuit  8  are (L, H, L). The input address signal therefore selects the cell ML 4  right-adjacent to defective cell MR 3  in cell block  10 , but because of the redundancy repair, the redundant sense amplifier reads data from redundant cell RML 2  instead. 
     As cell drain select signal DS 0  is high, redundant cell drain select transistor RMDSL 2  turns on and the cell drain voltage CDV is applied to redundant cell drain select line RDSL 2 . As word line select signal WL 1  is high, the memory cell transistors that have been programmed to the low threshold level in the row including cells ML 0  to MR 7  and redundant cells RML 0  to RMR 3  turn on. 
     In the defective cell block column redundancy selection circuit  5 , since column address signals (AY 3 , AY 2 , AY 1 ) are (H, L, L), the value of column address signal AY 3  is not the same as the value of fuse programmable address signal FY 3 , and the value of column address signal AY 2  is not the same as the value of fuse programmable address signal FY 2 . Redundant column address signals FA 2 , FA 3  are therefore (L, L), and redundant column select signals RY 0 , RY 1  are (L, L). 
     In the upper column redundancy selection circuit  74 , since column address signals (AY 3 , AY 2 , AY 1 ) are (H, L, L), the value of column address signal AY 3  is the same as the value of upper fuse programmable address signal FYU 3 , the value of column address signal AY 2  is the same as the value of upper fuse programmable address signal FYU 2 , and the value of column address signal AY 1  is the same as the value of upper fuse programmable address signal FYU 1 . Upper redundant column address signals (FAU 3 , FAU 2 , FAUL) are therefore (H, H, H). As the upper redundancy enable signal FMAINU is also high, the upper redundant column select signal RYU is high. 
     In the lower column redundancy selection circuit  75 , since column address signals (AY 3 , AY 2 , AY 1 ) are (H, L, L), the value of column address signal AY 2  is the same as the value of lower fuse programmable address signal FYD 2 , the value of column address signal AY 3  is not the same as the value of lower fuse programmable address signal FYD 3 , and the value of column address AY 1  is not the same as the value of fuse programmable lower address FYD 1 . Lower redundant column address signals (FAD 3 , FAD 2 , FAD 1 ) are therefore (L, H, L) and lower redundant column select signal RYD is low. 
     The outputs (RY 0 , RY 1 , RYU, RYD) from the defective cell block column redundancy selection circuit  5  and adjacent cell block column redundancy selection circuit  6  are therefore (L, L, H, L). Redundant column switch transistor RMBL 2  turns on while the other redundant column switch transistors RMBL 0 , RMBL 1 , RMBL 3  remain off. 
     Thus when address signals (AY 0 , AY 1 , AY 2 , AY 3 , AX 1 , AX 2 , AX 3 )=(L, L, L, H, H, L, L) for selecting the normal cell ML 4  right-adjacent to defective cell MR 4  are input, row select signal WL 1  is driven high, and redundant cell drain select transistor RMDSL 2  and redundant column switch transistor RMBL 2  turn on, selecting the redundant cell RML 2  that replaces normal cell ML 4 . The data bit programmed into this redundant cell RML 2  is output as redundant read-out data RDATA from output terminal of redundant cell array  2  to the redundant sense amplifier. 
     Data programmed into other redundant cells in the lower half of the second redundant cell block  21  are similarly read in place of data in the corresponding memory cells in half-block  12 . 
     According to the embodiment described above, when a redundancy repair is performed to replace a cell block with a defective cell, the normal half-block nearest to the defective cell is also replaced with a redundant half-block. Block-wise redundancy repair can therefore be carried out without leaving non-replaced adjacent normal cells that might be affected by the defect in the manner shown in  FIG. 10 . Even when the defective cell is located at the edge of a cell block, the operating margin of the memory with respect to voltage and temperature variations is maintained and the problem of failure due to gradual degradation over time is mitigated without the need for a complex memory structure. 
     The normal cell blocks adjacent to the defective block are divided in half according to column address signal AY 1 . If the defect is located in the left half of the defective cell block, the upper half of the normal cell block to the left (the half-block selected when column address signal AY 1  is high) is replaced. If the defect is located in the right half of the defective cell block, the lower half of the normal cell block to the right (the half-block selected when column address signal AY 1  is low) is replaced. If both halves of the defective cell block include defective cells, both adjacent half-blocks are replaced simultaneously with one redundant cell block in a redundant cell array, an arrangement that avoids an undue increase in the chip size of the semiconductor memory. 
     The invention provides an adjacent cell block column redundancy selection circuit  6  with an upper column redundancy selection circuit  74  for generating an upper redundant column address higher by one than the address set in the fuse programmable circuits in the defective cell block column redundancy selection circuit  5 , and a lower column redundancy selection circuit  75  for generating a lower redundant column address lower by one than the address set in the fuse programmable circuits in the defective cell block column redundancy selection circuit  5 . This is the structure that makes it possible to select a redundant half-block to replace a half-block adjacent to the defective cell. 
     In the embodiment above, the normal cell array is divided into cell blocks with two bit lines apiece, but the cell blocks may include a larger number of bit lines apiece. In this case, when there is a defective memory cell at or near an edge of a cell block, the adjacent normal half-block may be replaced, or only the adjacent bit line may be replaced, if that provides adequate isolation of the defect. 
     More generally, if the defective cell block is selected by n address bits, then the replaced normal fractional block may selected by m address bits, where m and n are arbitrary integers such that m is greater than n. Equivalently, the first redundant cell block is selected by n address bits and the second (fractional) redundant cell block is selected by m address bits. 
     In the embodiment described above, the invention is applied to a column redundancy scheme, but the invention is also applicable to row redundancy schemes. 
     The invention is not limited to a programmable read-only memory; it can also be applied to other types of semiconductor memory, such as dynamic random-access memory (DRAM) and static random-access memory (SRAM). 
     Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.