Abstract:
The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points S i  and transition sampling points T i . In particular, these offsets are controlled by both coarse and fine adjustments. Typically CDR circuits employ feedback phase control information being supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates in general to synchronization of signals between different clock domains in a circuit employing a Voltage Controlled Delay Loop (VCDL) and in particular, to synchronization of phase control signals in a Clock and Data Recovery (CDR) circuit.  
       BACKGROUND OF THE INVENTION  
       [0002]     Currently, CDR circuits are based on timing signals provided by Delay Locked Loops (DLL) or Voltage Controlled Delay Loops (VCDL). An example of such prior art CDR circuits are described in U.S. Pat. No. 5,684,421 issued Nov. 4, 1997 to Chapman et al., which patent is hereby incorporated by reference. In a CDR system an internal clock, derived from a reference Phase-Lock Loop (PLL) clock, is used to oversample incoming data. Based on the results of this oversampled data, a recovered clock is derived by delaying the internal clock so that it provides data sampling adjusted to the center of the “eye” pattern of the received data.  FIG. 1  illustrates an example of sampling of a received digital data signal  10  wherein S 0  and S 1  depict sampling times corresponding to the center of the eye pattern. As also illustrated, sampling at transition points T 0  and T 1  would not properly detect the received data, although these points are used for data phase detection.  
         [0003]      FIG. 2  is a block diagram of a conventional CDR system in which a VCDL component  220  is used to generate multiphase clock signals for a data sampler  230  for sampling serial data  240 . In such a VCDL component, the phases of this multiphase clock need to be constantly adjusted to the phase deviations of the incoming data. As proper sampling of the serial data occurs, a Recovered Bit Clock  260  is derived which corresponds in timing (phase and frequency) to the serial data signal. This Recovered Bit Clock  260  is supplied to a filter (e.g., a second order PI filter, as is well-known) which produces a Phase Control Signal  250  which is supplied back to the VCDL component  220 . This Phase Control Signal  250  comprises feedback information on adjusting the phase of the multiphase clocks. For example, this signal may comprise instructions that the phase needs to be increased by a fixed amount, decreased by a fixed amount, or left unchanged.  
         [0004]     A problem exists in the prior art in that this Phase Control Signal  250  is in the recovered clock domain while the VCDL component operates in the PLL clock domain. That is, the Phase Control Signal  250  is derived and consequently changes as a function of the recovered clock timing. This recovered clock is independent and potentially changing its relation in time to the PLL clock. For the VCDL circuitry to properly utilize the information in this Phase Control Signal, synchronization of this signal relative to the PLL clock needs to be performed.  
       SUMMARY OF THE INVENTION  
       [0005]     The present invention synchronizes signals generated and used in different clock domains. The invention is applicable to a CDR circuit in which phase adjustment of a multiphase clock to the phase of incoming data is implemented by controlling phase offsets from the PLL frequency relative to data sampling points S i  and transition sampling points T i . In particular, these offsets are controlled by both coarse and fine adjustments.  
         [0006]     Typically CDR circuits employ feedback phase control information supplied to the VCDL. The above described adjustments result in these phase control signals having an arbitrary and time-changing relation to the PLL clock. By properly selecting an appropriate edge of the PLL clock signal as the sampling edge, the present invention synchronizes these phase control signals into the PLL clock domain in order to apply VCDL control in a synchronous manner. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     Various embodiments of the present invention will now be described in detail in conjunction with the annexed drawings, in which:  
         [0008]      FIG. 1  illustrates proper sampling times of a received digital signal;  
         [0009]      FIG. 2  is a block diagram of a conventional CDR circuit;  
         [0010]      FIG. 3  illustrates VCDL phase control according to an embodiment of the invention;  
         [0011]      FIG. 4  illustrates exemplary phase relationships between the PLL clock signal and the recovered clock according to an embodiment of the invention;  
         [0012]      FIG. 5  is a timing diagram of potential sampling points relative to different injection quadrants;  
         [0013]      FIG. 6A  depicts an exemplary injection point control register;  
         [0014]      FIG. 6B  illustrates a decoding scheme of the injection point in VCDL phase control according to an additional embodiment of the invention; and,  
         [0015]      FIG. 7  depicts an exemplary control circuit for sampling edge control of an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0016]     The present invention is intended for use in a system in which a sampling clock is derived using a VCDL multiphase clock.  FIG. 3  illustrates an exemplary multiphase clock wherein various phase delays or stages are depicted in a circular arrangement. The labeling convention of these stages correlates to that of  FIG. 1 . Items labeled  310  represent delay elements that are used to create a multiphase data sampling clock.  
         [0017]     S 3  is depicted as the current Injection Point  320  at which the PLL frequency is supplied. Coarse adjustments to these multiphase clocks are obtained by shifting this injection point  320 . Fine adjustments are attained by using a central interpolator  330 . The use of an injection point control in this manner is described in co-pending U.S. patent application Ser. No. 10/999,900 entitled “Delay Line with Injection Point Control”, the contents of which are hereby incorporated by reference. The use of a central interpolator is described in co-pending U.S. patent application Ser. No. 10/999,889 entitled “Central Interpolator”, the contents of which are also hereby incorporated by reference.  
         [0018]     As described above, coarse phase adjustments to this multiphase clock are performed by varying the injection point  320  of the PLL frequency. The location of the injection point  320  can be coded into one of four quadrants: quadrant  1  (Q 1 )—from T 0  to T 1 , quadrant  2  (Q 2 )—from T 1  to T 2 , quadrant  3  (Q 3 )—from T 2  to T 3 , and quadrant  4  (Q 4 )—from T 3  to T 0 . Within each quadrant there are four possible injection points, each incorporating a delay element  301 .  
         [0019]     When the injection point  320  of the PLL frequency is moved, the phase relations between the PLL clock and the recovered clock are changed. As depicted in  FIG. 2 , a phase control signal  250  is derived based on the recovered clock  260 . As described herein, this phase control signal provides phase control adjustment information to VCDL  220 . This information essentially comprises instructions to increase, decrease or retain the current phase delay.  
         [0020]      FIG. 4  depicts the corresponding phase relationships between the PLL clock signal  210  and various potential recovered bit clocks  260  in  FIG. 2 . That is,  FIG. 4  illustrates possible phases of the multiphase clock  300  from which a recovered bit clock  260  is derived. Referring to depicted signal  420  (which occurs when the injection point is in Q 1 ), a leading edge of the recovered clock occurs as early as  422  and as late as  424 , as a function of which injection point is used within the quadrant. Trailing edges  426  and  428 , respectively, occur subsequent to the leading edge in accordance with the clock period. Leading edge  429  depicts a second cycle of the recovered clock signal  420 .  
         [0021]     Signal  430  illustrates timing of leading and trailing edges which result from an injection point occurring in Q 2 . As illustrated in  FIG. 4 , the timing of leading and trailing edges of a recovered clock  260  relative to the PLL clock  210  are determined by the quadrant in which the injection point occurs.  
         [0022]     As described above with respect to  FIG. 2 , the phase control signal  250  is supplied to the VCDL  220 . This signal comprises instructions to increase, decrease or retain the current phase delay of the multiphase clock. The phase control signal  250  exists in the recovered clock domain. As a result, the phase relation between the phase control signal  250  and the PLL clock  210  is changing as a function of the injection point—in the same manner as depicted in  FIG. 4  with respect to the Recovered Clock  260 . Consequently in order for VCDL  220 , operating in the PLL clock domain, to properly obtain the phase delay adjustment instructions contained in the phase control signal  250 , synchronization of the phase control signal relative to the PLL clock needs to be performed.  FIG. 4 &#39;s timing diagram of these signals relative to each other illustrates a means for performing this synchronization that is implemented in various embodiments of the invention described below. Rising and falling edges of the PLL clock are depicted relative in time to the potential recovered clock signals for each of the four quadrants in which the injection point can occur. For any given quadrant, either a rising edge or a falling edge of the PLL clock (but not both) can be used to synchronize a signal in the recovered clock domain.  
         [0023]      FIG. 5  further illustrates the timing relationship between the phase control signal  250  (in the recovered clock domain) relative to the PLL clock. In particular, it illustrates the phase control signal  250  relative to the PLL clock for each of the different injection quadrants. In this figure, the phase control signal  250  is depicted as being fixed against the illustrated PLL clocks in the respective quadrants. As illustrated, to attain reliable sampling of the phase control signal  250 , the falling edges of the PLL clock can be used if the injection point is in quadrants  1  or  2  (e.g.,  510  and  520 , respectively). The rising edge can be used if the injection point is in quadrants  3  or  4  (e.g.,  530  and  540 , respectively).  
         [0024]     The propagation time for phase control signals with respect to the PLL clock can cause an additional skew between these signals. This skew may be dependent on the particular characteristics of the manufactured integrated circuit. Accordingly, it is frequently desirable to control which edge (rising or falling) of the PLL frequency is used for phase control sampling in each injection quadrant. In a further embodiment of the invention this is controlled by setting configuration bits to define which edge to employ. As a consequence, the synchronization of phase control signals into the PLL clock domain is performed more reliably.  
         [0025]      FIG. 6A  illustrates a 16-bit shift register  600  which is used to control the injection point of the multiphase clock depicted in  FIG. 3 . In one embodiment, this register resides in the VCDL component  220  and has a single bit (e.g.  610 ) indicating the position of the injection point. Shifting this bit position up or down corresponds to a shift in the injection point. A wrap-around function permits shifting up from bit position  640  to bit position  610  (as would shifting down from bit position  610  yield bit position  640 ). As illustrated in  FIG. 6A , the injection point quadrant is readily determined by the bit position in the register  600 .  
         [0026]      FIG. 6B  illustrates a decoding scheme for setting “I” (in-phase) and “Q” (quadrature) flags based on the quadrant in which the injection point occurs. If the injection point is located in quadrants  1  or  2  then the decoder output “1” (in-phase) is a one, otherwise it is a zero. If the injection point is in quadrants  4  or  1 , then the decoder output “Q” (quadrature) is a one, otherwise it is a zero.  
         [0027]     These I and Q flags are used for controlling the PLL edge to be employed by the control circuit depicted in  FIG. 7 . This control circuit uses two configuration bits, which can be changed under software control: IQSEL  710  (choosing between in-phase and quadrature decoder outputs) and IQINV  720  (allowing to invert the edge being used for synchronization). In operation, the control circuit of  FIG. 7  results in the sampling control being configured to latch the phase control signal  250  on different edges of the PLL clock in each injection quadrant according to the following table:  
                                                                           Setting   PLL Clock Edge            Scenario   Quadrant                IQINV   IQSEL   1   Quadrant 2   Quadrant 3   Quadrant 4               0   0   Rising   Rising   Falling   Falling       0   1   Rising   Falling   Falling   Rising       1   0   Falling   Falling   Rising   Rising       1   1   Falling   Rising   Rising   Falling                  
 
         [0028]     For the sake of comparison, the configuration of IQINV=1 and IQSEL=0 yields the “falling”, “falling”, “rising”, “rising” sampling points determined in the previous embodiment of the invention and illustrated in  FIG. 5 . The current embodiment takes into account potential propagation delay skew for different corners of IC manufacturing process. The use of the configuration settings can satisfy any systematic skew between the phase control signals  250  and the PLL clock  210 , and maintain the acceptable setup and hold requirements for the changing phase relations between the recovered clock and the PLL clock. In further embodiments of the invention, these configuration settings can be set to default values based on pre-characterization of the circuitry and/or adjusted by a user through a trial and error process.  
         [0029]     While the invention has been described with reference to the above embodiments, it will be appreciated by those of ordinary skill in the art that modifications can be made to the structure and elements of the invention without departing from the spirit and scope of the invention as a whole.