Abstract:
A method for manufacturing a semiconductor device includes forming a hard mask pattern and a spacer at both sides of the hard mask pattern. The method also includes forming a spacer pattern, so that the spacer remains in one direction to form a spacer pattern, forming a photoresist pattern having a pad type overlapping a side of the spacer pattern, and etching an underlying layer, with the photoresist pattern and the spacer pattern as a mask, to form an isolated pattern. The method improves resolution and process margins to obtain a highly-integrated transistor.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     The priority of Korean patent application No. 10-2007-0136952, filed Dec. 24, 2007, the disclosure of which is incorporated by reference in its entirety, is claimed. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device that does not require the manufacture of a dummy pattern to form an isolated pattern on a device, and improves resolution and process margins to obtain a highly-integrated transistor. 
     2. Brief Description of Related Technology 
     Semiconductor device pattern size is reduced as the devices become more highly integrated. In order to form a fine pattern, Various equipment and processes have been designed to form fine patterns for these devices. For example, a fine pattern may be obtainable by reducing an exposure wavelength, or by enlarging the size of a lens. However, these methods require new equipment development and increased manufacturing cost, which, in turn, results in difficulties in managing the equipment. 
     In an alternative method that uses conventional equipment employs a double exposure technology and a spacer patterning technology (SPT).  FIGS. 1 and 2  are plane diagrams illustrating a conventional method for manufacturing a semiconductor device using SPT.  FIG. 1  shows an isolated pattern  110  formed in a peripheral circuit region of a substrate  100 . The isolated pattern  110  includes a line-type pattern  110   a  and a rectangular pad  110   b  formed on the line-type pattern  119   a . A general photolithography process can be used to form patterns shown in  FIG. 1 . Photolithography methods, however, are limited by increased integration of the device. To overcome the limits, there are efforts to apply a light source having a short wavelength, an illuminator having high numerical aperture, and various resolution enhancement technology (RET) processes. The illuminator or the RET improves a margin of the photolithography process in dense patterns or half-dense patterns. However, the isolated pattern may reduce a margin in depth of focus (DOF). 
     In an etching process after the photolithography process for the isolated pattern of  FIG. 1 , a relatively larger bias is applied to the isolated pattern than to the dense pattern, which bias requires a smaller critical dimension in the etching process than in the photolithography process. During the photolithography process, a focus and an exposure latitude (EL) margin are reduced. To prevent the reduction, a method of forming a dummy pattern between an isolated pattern and its adjacent isolated pattern has been suggested. 
       FIG. 2  illustrates formation of a dummy pattern between isolated patterns. As shown, an isolated pattern  210  is formed over a semiconductor substrate  200 , and a dummy pattern  220  is formed between the isolated patterns  210 . 
     Although a method of forming a dummy pattern between isolated patterns has been suggested to increase a process margin and resolution of transistors in semiconductor device manufacturing methods, the process margin and resolution that can be increased by the dummy pattern are limited. 
     SUMMARY OF THE DISCLOSURE 
     Disclosed herein are various semiconductor device manufacturing methods that are directed at improving a depth of focus (DOF) margin and an exposure latitude (EL) margin to obtain a highly-integrated transistor. 
     According to one embodiment, a method for manufacturing a semiconductor device includes forming an underlying layer and a first hard mask layer over a semiconductor substrate, and forming a second hard mask pattern, the second hard mask pattern having a line type, over the first hard mask layer. The method also includes forming a spacer at sidewalls of the second hard mask pattern, and removing the second hard mask pattern so that the spacer remains. The method further includes removing a part of the spacer to form a spacer pattern, forming a photoresist pattern, the photoresist pattern having a pad type overlapping a part of the spacer pattern, over the first hard mask layer (including the spacer pattern), and etching the first hard mask layer, with the photoresist pattern and the spacer pattern as a mask to form a first hard mask pattern. The method also includes etching the underlying layer, with the first hard mask pattern as a mask, to form an underlying pattern. 
     According to another embodiment, a method for manufacturing a semiconductor device includes forming an underlying layer and a first hard mask layer over a semiconductor substrate, and forming a second hard mask pattern including a pad pattern and a line pattern over the first hard mask layer. The method also includes forming a spacer at sidewalls of the second hard mask pattern, removing the second hard mask pattern so that the spacer remains, and removing a part of the spacer to form a stepped-shaped spacer pattern. The method further includes forming a photoresist pattern, the photoresist pattern overlapping a part of the spacer pattern, over the first hard mask layer (including the spacer pattern). The method also includes etching the first hard mask layer, with the photoresist pattern and the spacer pattern as a mask, to form a first hard mask pattern, and etching the underlying layer, with the first hard mask pattern as a mask, to form an underlying pattern. 
     Additional features of the disclosed embodiments may become apparent to those skilled in the art from a review of the following detailed description, taken in conjunction with the drawings, and the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the disclosure, reference should be made to the following detailed description and accompanying drawings wherein: 
         FIGS. 1 and 2  are plane diagrams illustrating a conventional method for manufacturing a semiconductor device; and, 
         FIGS. 3   a  to  3   h  are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention. 
     
    
    
     While the disclosed method is susceptible of embodiments in various forms, there are illustrated in the drawings (and will hereafter be described) specific embodiments, with the understanding that the disclosure is intended to be illustrative, and is not intended to limit the invention to the specific embodiments described and illustrated herein. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIGS. 3   a  to  3   h  are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention.  FIGS. 3   a (i) to  3   h (i) are plane diagrams, and  FIGS. 3   a (ii) to  3   h (ii) are cross-sectional diagrams taken along line X-X′ of  FIGS. 3   a (i) to  3   h (i), respectively. 
     Referring to  FIG. 3   a , an underlying layer  305 , a first hard mask layer  310 , a second hard mask layer  315 , and anti-reflection film  320 , and a first photoresist pattern  325 , defining a pattern region, are formed over a semiconductor substrate  300 . The first photoresist pattern  325  includes a pad pattern  325   a  having a critical dimension ‘a’ and a line pattern  325   b  having a critical dimension ‘b’, wherein the critical dimension ‘a’ is greater than the critical dimension ‘b’ (i.e., a&gt;b). The pad pattern  325   a  is contacted with the line pattern  325   b . One side of the pad pattern  325   a  contacts with that of the line pattern  325   b , and an upper side of the pad pattern  325   a  is aligned with that of the line pattern  325   b.    
     The first photoresist pattern  325  may be formed to have a line type (not shown). A critical dimension (CD) of the first photoresist pattern  325  may be formed to be larger than that of a final pattern because an exposure process margin can be improved as pattern size becomes larger. The first photoresist pattern  325  may be formed to be one- to three-times larger than a final pattern. The first photoresist pattern  325  may be formed by exposure to a light source selected from the group consisting of I-Line, KrF, ArF, EUV, and F 2 , and combinations thereof. 
     Referring to  FIG. 3   b , the anti-reflection film  320  and the second hard mask layer  315  are etched with the first photoresist pattern  325 . The first photoresist pattern  325  and the etched anti-reflection film  320  are removed to form a second hard mask pattern  315   a . A spacer layer (not shown) having a given thickness is formed over the resulting structure, including the second hard mask pattern  315   a . A blanket-etching process is performed to deposit a spacer  330  at sidewalls of the second hard mask pattern  315   a.    
     Referring to  FIG. 3   c , the second hard mask pattern  315   a  is removed so that the spacer  330  formed at the sidewalls of the second hard mask pattern  315   a  may remain. As shown in  FIG. 3   c , the spacer  330  is formed along the sidewall of the removed pattern  315 , so that the spacer  330  is formed to have a close curved line (curved in the direction of the removed pattern  315 ). 
     Referring to  FIG. 3   d , a second photoresist pattern  335  is formed to open a part of the spacer  330 . The second photoresist pattern  335  is formed so that the spacer where a final pattern is formed may not be open. More specifically, and referring to  FIG. 3   d (i), the second photoresist pattern  335  is formed to open the spacer  330 , which is formed outside of the spacer  330  formed to have a close curved line. 
     Referring to  FIG. 3   d (ii), through a photoresist coating and a photo lithography the second photoresist pattern  335  is formed over a side of the spacer  330  so that the other side of the spacer  330  may be exposed. 
     An exposure process for forming the second photoresist pattern  335  is performed with a light source selected from the group consisting of I-Line, KrF, ArF, EUV, and F 2  and combinations thereof. 
     Referring to  FIG. 3   e , the spacer  330  exposed by the second photoresist pattern  335  is removed to form a spacer pattern  330   a  where a final pattern is formed. The spacer pattern  330   a  is formed to have a stepped-shape, shown in  FIG. 3   e , for example. A CD of the top surface having a stepped-shape may be formed smaller than that of the side having a stepped-shape. 
     When the second hard mask pattern  315   a  of  FIG. 3   b  has a line type, the spacer pattern  330   a  is formed to have a line type. 
     Referring to  FIG. 3   f , a third photoresist pattern  340  is formed which is overlapped with the top surface of the spacer pattern  330   a  and a part of the side adjacent to the top surface. The third photoresist pattern  340  is formed to have a pad type. A side of the third photoresist pattern  340  is aligned with a side of the spacer pattern  330   a . A CD of the minor axis of the third photoresist pattern  340  having a pad type is formed to be larger than that of the top surface of the spacer pattern  330   a  having a stepped-shape. 
     An exposure process for forming the third photoresist pattern  340  is performed with a light source selected from the group consisting of I-Line, KrF, ArF, EUV, and F 2  and combinations thereof. 
     Referring to  FIG. 3   g , the first hard mask layer  310  is etched with the third photoresist pattern  340  and the spacer pattern  330   a  as a mask to form a first hard mask pattern  310   a . Thereafter, the third photoresist pattern  340  is removed. 
     The first hard mask pattern  310   a  formed in the bottom of the spacer pattern  330   a  may be formed to have a CD larger than that of the spacer pattern  330   a.    
     Referring to  FIG. 3   h , the underlying layer  305  is etched with the first hard mask pattern  310   a  and the spacer pattern  330   a  as a mask to form an underlying pattern  305   a , to obtain a desired fine pattern. 
     The underlying pattern  305   a , defining an isolated pattern formed in a peripheral circuit region, is formed by a SPT process. As a result, a process margin can be improved without a dummy pattern. 
     As described above, according to an embodiment of the invention, a method for manufacturing a semiconductor device includes forming an isolated pattern having a fine CD by a SPT process, thereby improving a DOF margin and an EL margin to obtain a high-integrated transistor. 
     The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.