Abstract:
A semiconductor device includes a transistor that is used for a charge pump circuit, being configured with a fully depleted silicon-on-insulator transistor.

Description:
[0001]    This is a Divisional of U.S. patent application Ser. No. 11/373,915 filed on Mar. 14, 2006, which is hereby incorporated by reference in its entirety. This application claims priority to Japanese Patent Application No. 2005-083391 filed Mar. 23, 2005, which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates to a semiconductor device and a boost circuit, particularly to the ones suitable for configuration of a charge pump circuit with a fully depleted silicon-on-insulator (hereafter “SOI”) transistor. 
         [0004]    2. Related Art 
         [0005]    In common semiconductor devices, field-effect transistors are formed on SOI substrates. This is because these transistors are latch-up free and are easy to isolate devices therein, and have a comparatively small source/drain junction capacitance. Particularly, since fully depleted SOI transistors allow rapid, lower power-consumption operations, researches for achieving the operation of the SOI transistors in a fully depleted mode are very active. 
         [0006]    As semiconductor manufacturing processes advance, semiconductor integrated circuits become more multifunctional and highly integrated in a higher density, while the source voltage inside those semiconductor integrated circuits become lower and lower. Various power sources, including high voltage sources, are more often built in, as semiconductor integrated circuits become more multifunctional. For instance, 10V and/or more of high voltage is required for nonvolatile memories such as flash memory and electrically erasable programmable read-only memory (hereafter “EEPROM”), and for driver integrated circuits (hereafter “IC”) for display devices. In order to generate such high voltages with a boost circuit, a charge pump approach with which building-in the boost circuit to the semiconductor circuit is easy, is employed, instead of a switching regulator approach using coils and the like. Among the charge pump approach, Dickson charge pump circuit is commonly used, as disclosed in JP-A-2004-328901. 
         [0007]    However, in common charge pump circuits, ground contact of substrate terminals of transistors needs to be provided in order to deal with the latch-up phenomenon. This involved a problem of conversion efficiency deterioration, since transistors that configure the charge pumps need to be high voltage proof, which increases an internal impedance of charge pump circuits. 
       SUMMARY 
       [0008]    An advantage of the invention is to provide a semiconductor device and a boost circuit that can improve the conversion efficiency during the boosting, while preventing the latch-up. 
         [0009]    According to an aspect of the invention, a semiconductor device includes a transistor used for a charge pump circuit, being configured with a fully depleted silicon-on-insulator transistor. 
         [0010]    This allows the complete electric isolation of the transistor used in the charge pump circuit, thereby preventing the latch-up without using high voltage transistors. Consequently, the charge pump circuit may be configured using a transistor with the high transconductance, thereby reducing the internal impedance of the charge pump circuit. As a result, this allows the improvement of the conversion efficiency during the boosting, and the various power sources including high voltage sources may be built in to the semiconductor integrated circuit, while maintaining being compatibility with the increasingly low source voltage within the semiconductor integrated circuit. 
         [0011]    In this case, in the semiconductor device, the fully depleted silicon-on-insulator may include: a semiconductor layer formed on an insulation layer; a gate electrode arranged on the semiconductor layer; a source layer formed on the semiconductor layer, arranged on one side of the gate electrode; a drain layer formed on the semiconductor layer, arranged on the other side of the gate electrode; and a body-source junction layer which connects a body region under the gate electrode and the source layer. 
         [0012]    Here, since the SOI transistor is fully depleted, the hot carriers accumulated in the body region may be let out while suppressing a device area increase, in the case where the body region under the gate electrode is isolated. Consequently, this allows a prevention of drain deterioration caused by the accumulation of the hot carrier in the body region, thereby attaining a lower power consumption and low-power drive, while improving the conversion efficiency of the charge pump circuit. 
         [0013]    According to another aspect of the invention, a booster circuit includes: a first n-channel fully depleted silicon-on-insulator transistor in which a first pulse is emitted into a gate; a first p-channel fully depleted silicon-on-insulator transistor in which the first pulse is emitted into a gate, connected serially to the first n-channel fully depleted silicon-on-insulator transistor; a second n-channel fully depleted silicon-on-insulator transistor where a gate thereof is connected to a drain of the first n-channel fully depleted transistor; a second p-channel fully depleted silicon-on-insulator transistor, connected serially to the second n-channel fully depleted silicon-on-insulator transistor; a third p-channel fully depleted silicon-on-insulator transistor in which a second pulse which is in an opposite phase to the first pulse is emitted into a gate, a source thereof is connected to a drain of the second n-channel fully depleted silicon-on-insulator transistor; a third n-channel fully depleted silicon-on-insulator transistor in which the second pulse is emitted into a gate, connected serially to the third p-channel fully depleted silicon-on-insulator transistor, and a source thereof being connected to a source of the second n-channel fully depleted silicon-on-insulator transistor; a forth n-channel fully depleted silicon-on-insulator transistor where a source thereof is connected to the source of the second n-channel fully depleted silicon-on-insulator transistor, and where a gate thereof is connected to a drain of the third n-channel fully depleted transistor; a forth p-channel fully depleted silicon-on-insulator transistor which is connected serially to the forth n-channel fully depleted silicon-on-insulator transistor, a gate thereof being connected to a source of the third p-channel fully depleted silicon-on-insulator transistor, a source thereof being connected to the source of the second p-channel fully depleted silicon-on-insulator transistor, and a drain thereof being connected to a source of the first p-channel fully depleted silicon-on-insulator transistor; a first capacitor to which the first pulse is input, connected to the drain of the second n-channel fully depleted silicon-on-insulator transistor; and a second capacitor to which the second pulse is input, connected to a drain of the forth n-channel fully depleted silicon-on-insulator transistor. 
         [0014]    Hence the transistors used in the charge pump circuit may be configured with the fully depleted SOI transistors, allowing a complete electric isolation of these transistors. Consequently, the latch-up may be prevented without using the high voltage transistors, and the internal impedance of the charge pump circuit may be reduced, thereby allowing the improvement of the conversion efficiency of the charge pump circuit. 
         [0015]    In this case, in the booster circuit, the n-channel fully depleted silicon-on-insulator transistors and the p-channel fully depleted silicon-on-insulator transistors may have a source-tie structure. 
         [0016]    Therefore, in the case where the holes, generated in the drain edge, flows into the body region, those holes accumulated in the body region may be drained to the source, thereby allowing the suppression of the hot carrier accumulation in the body region. Consequently, since the SOI transistor is fully depleted, the drain deterioration may be prevented while suppressing an device area increase, in the case where the body region under the gate electrode is isolated. 
         [0017]    It this case, in this boost circuit, a lower electrode for any one of the first and the second capacitors is configured with a p-doped diffusion layer which constitutes the source/drain of any one of the first through fourth p-channel fully depleted silicon-on-insulator transistors, and wherein an upper electrode for any one of the first and the second capacitors is together with the formation of the first through forth p-channel fully depleted SOI transistors, configuring the charge pump circuit while preventing the complication of the manufacturing process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements. 
           [0019]      FIG. 1  is a circuit diagram showing an exemplary structure of one step-up operation of a boost circuit to which the invention is applied. 
           [0020]      FIG. 2  is a top view drawing showing a layout pattern of the boost circuit in  FIG. 1 . 
           [0021]      FIGS. 3A to 3C  are sectional drawings showing an exemplary structure of a fully depleted SOI transistor. 
           [0022]      FIGS. 4A to 4D  is a pattern diagram showing an output waveform of the boost circuit in  FIG. 1 . 
       
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0023]    A semiconductor device and a boost circuit in accordance with an embodiment of the invention will now be described with references to the accompanying drawings. 
         [0024]      FIG. 1  is a circuit diagram showing an exemplary structure of a boost circuit to which the invention is applied. 
         [0025]    In  FIG. 1 , a source of an n-channel field-effect transistor M 1  is connected to a LVDD terminal, and the source of a p-channel field-effect transistor M 2  is connected to a VDDORP terminal. A drain of the n-channel field-effect transistor M 1  and the drain of the p-channel field-effect transistor M 2  are both connected to a PHIA terminal. Further, the gate of the n-channel field-effect transistor M 1  and the gate of the p-channel field-effect transistor M 2  are both connected to a PHI terminal. Here, a substrate potential of the n-channel field-effect transistor M 1  is connected to the source of the n-channel field-effect transistor M 1 , and the substrate potential of the p-channel field-effect transistor M 2  is connected to the source of the p-channel field-effect transistor M 2 . 
         [0026]    The source of an n-channel field-effect transistor M 5  is connected to the LVDD terminal, and the source of a p-channel field-effect transistor M 6  is connected to a VDDO terminal. The drain of the n-channel field-effect transistor M 5  and the drain of the p-channel field-effect transistor M 6  are both connected to a PHIARP terminal. Further, the gate of the n-channel field-effect transistor M 5  and the gate of the p-channel filed-effect transistor M 6  are both connected to a PHIRP terminal. Here, the substrate potential of the n-channel field-effect transistor M 5  is connected to the source of the n-channel field-effect transistor M 5 , and the substrate potential of the p-channel field-effect transistor M 6  is connected to the source of the p-channel field-effect transistor M 6 . 
         [0027]    The sources of n-channel field-effect transistors M 3  and M 4  are connected to the LVDD terminal, and sources of p-channel field-effect transistors M 7  and M 8  are connected to a HVDD terminal. The drain of the n-channel field-effect transistor M 3  and the drain of p-channel field-effect transistor M 7  are both connected to the VDDO terminal, and the drain of the n-channel field-effect transistor M 4  and the drain of the p-channel field-effect transistor M 8  are both connected to the VDDORP terminal. The gate of the n-channel field-effect transistor M 3  is connected to the PHIA terminal, and the gate of the n-channel field-effect transistor M 4  is connected to the PHIARP terminal. The gate of the p-channel field-effect transistor M 7  is connected to the VDDORP terminal, and the gate of the p-channel field-effect transistor M 8  is connected to the VDDO terminal. 
         [0028]    Here, the substrate potential of the n-channel field-effect transistor M 3  is connected to the source of the n-channel field-effect transistor M 3 , and the substrate potential of the n-channel field-effect transistor M 4  is connected to the source of the n-channel field-effect transistor M 4 . Moreover, the substrate potential of the p-channel field-effect transistor M 7  is connected to the source of the p-channel field-effect transistor M 7 , and the substrate potential of the p-channel field-effect transistor M 8  is connected to the source of the p-channel field-effect transistor M 4  is connected to the source of the n-channel field-effect transistor M 4 . Moreover, the substrate potential of the p-channel field-effect transistor M 7  is connected to the source of the p-channel field-effect transistor M 7 , and the substrate potential of the p-channel field-effect transistor M 8  is connected to the source of the p-channel field-effect transistor M 8 . 
         [0029]    The PHI terminal is connected to the drain of the n-channel field-effect transistor M 3  via a capacitor C 1 , and the PHIRP terminal is connected to the drain of the n-channel field-effect transistor M 4 , via a capacitor C 2 . 
         [0030]      FIG. 2  is a top view drawing showing a layout pattern of the boost circuit in  FIG. 1 . 
         [0031]    N-wells NW 2 , NW 6 , NW 7 , NW 8 , NW 11 , NW 12 , and p-wells PW 1 , PW 3 , PW 4 , PW 5  are installed on the semiconductor substrate referred to in  FIG. 2 . The n-channel field-effect transistors M 1 , M 3 , M 4 , and M 5  referred to in  FIG. 1  are formed in p-wells PW 1 , PW 3 , PW 4 , and PW 5  respectively, and the p-channel field-effect transistors M 2 , M 6 , M 7 , and M 8  referred to in  FIG. 1  are formed in the n-wells NW 2 , NW 6 , NW 7 , and NW 8  respectively. The capacitors C 1  and C 2  referred to in  FIG. 1  are respectively formed in the n-wells NW 11  and NW 12 . 
         [0032]    A gate electrode G 1  is arranged on the p-well PW 1 , and in this p-well PW 1 , n-type impurity diffused layers N 1  and N 1 ′ are formed so as to sandwich the gate electrode G 1 . A gate electrode G 3  is arranged on the p-well PW 3 , and in this p-well PW 3 , n-type impurity diffused layers N 3  and N 3 ′ are formed so as to sandwich the gate electrode G 3 . A gate electrode G 4  is arranged on the p-well PW 4 , and in this p-well PW 4 , n-type impurity diffused layers N 4  and N 4 ′ are formed so as to sandwich the gate electrode G 4 . A gate electrode G 5  is arranged on the p-well PW 5 , and in the p-well PW 5 , n-type impurity diffused layers N 5  and N 5 ′ are formed so as to sandwich the gate electrode G 5 . 
         [0033]    A gate electrode G 2  is arranged on the n-well NW 2 , and in this n-well NW 2 , p-type impurity diffused layers P 2  and P 2 ′ are formed so as to sandwich the gate electrode G 2 . A gate electrode G 6  is arranged on the n-well NW 6 , and in this n-well NW 6 , p-type impurity diffused layers P 6  and P 6 ′ are formed so as to sandwich the gate electrode G 6 . A gate electrode G 7  is arranged on the n-well NW 7 , and in this n-well NW 7 , p-type impurity diffused layers P 7  and P 7 ′ are formed so as to sandwich the gate electrode G 7 . A gate electrode G 8  is arranged on the n-well NW 8 , and in this n-well NW 8 , p-type impurity diffused layers P 8  and P 8 ′ are formed so as to sandwich the gate electrode G 8 . 
         [0034]    An upper electrode U 1  is arranged on the n-well NW 11 , and in the n-well NW 11 , a p-type impurity diffused layer L 1  is formed so as to face the upper electrode U 1 . An upper electrode U 2  is arranged on the n-well NW 12 , and in the n-well NW 12 , a p-type impurity diffused layer L 2  is formed so as to face the upper electrode U 2 . 
         [0035]    The n-type impurity diffused layer N 1 , the p-type impurity diffused layer P 2 ′ and the gate electrode G 3  are interconnected via the lower metallization layer H 1 . The gate electrodes G 1 , G 2 , the p-type impurity diffused layer L 1 , and the PHI terminal are interconnected via a lower metallization layer H 2 . The n-type impurity diffused layer N 5 , the p-type impurity diffused layer P 6 ′, and the gate electrode G 4  are interconnected via a lower metallization layer H 3 . The n-type impurity diffused layer N 3 ′, the p-type impurity diffused layer P 7 , the gate electrode G 8 , and the upper electrode U 1  are interconnected via a lower metallization layer H 4 . The gate electrodes G 5 , G 6 , the p-type impurity diffused layer L 2 , and the PHIRP terminal are interconnected via a lower metallization layer H 5 . The p-type impurity diffused layer P 6  is connected to a lower metallization layer H 6 . The n-type impurity diffused layer N 1 ′ is connected to a lower metallization layer H 7 . The n-type impurity diffused layer N 5 ′ is connected to a lower metallization layer H 8 . The LVDD terminal is connected to a lower metallization layer H 9 . The n-type impurity diffused layer N 4  is connected to a lower metallization layer H 10 . The n-type impurity diffused layer N 4 ′, the p-type impurity diffused layer P 8 , the gate electrode G 7 , and the upper electrode U 2  are interconnected via a lower metallization layer H 11 . The p-type impurity diffused layers P 7 ′ and P 8 ′ are interconnected via a lower metallization layer H 12 . The n-type impurity diffused layer N 3  is connected to the circuit via a lower metallization layer H 13 . 
         [0036]    The lower metallization layers H 4  and H 6  are interconnected via an upper metallization layer H 21 . The lower metallization layers H 3 , H 6 , and H 11  are interconnected via an upper metallization layer H 22 . The lower metallization layers H 7 , H 8 , H 9 , H 10 , and H 13  are interconnected via an upper metallization layer H 23 . The lower metallization layer H 12  is connected to the circuit via an upper metallization layer H 24 . 
         [0037]    Here, the n-channel field-effect transistors M 1 , M 3 , M 4 , M 5 , and the p-channel field-effect transistors M 2 , M 6 , M 7 , M 8  may be configured with the fully depleted SOI transistors. 
         [0038]    Here, the n-channel field-effect transistors M 1 , M 3 , M 4 , M 5 , and the p-channel field-effect transistors M 2 , M 6 , M 7 , M 8  may be in a complete electric isolation; hence the latch-up may be prevented without using the high voltage transistors. Consequently, the n-channel field-effect transistors M 1 , M 3 , M 4 , M 5 , and the p-channel field-effect transistors M 2 , M 6 , M 7 , M 8 , all of which have high transconductance, may be used to configure the charge pump circuit, thereby allowing to reduce the internal impedance therein. As a result, this allows the improvement of the conversion efficiency during the boosting, and the various power sources including high voltage sources may be built into the semiconductor integrated circuit, while maintaining compatibility with the increasingly low source voltage within the semiconductor integrated circuit. 
         [0039]    By using the source-tie structured fully depleted SOI transistors for the n-channel field-effect transistors M 1 , M 3 , M 4 , M 5  and the p-channel field-effect transistors M 2 , M 6 , M 7 , M 8 , the device area may be reduced, since there is no need to pattern the back gate terminals for grounding the substrate on which the transistors are formed, around the n-wells NW 2 , NW 6 , NW 7 , NW 8 , NW 11 , NW 12 , and the p-wells PW 1 , PW 3 , PW 4 , PW 5 . 
         [0040]    Aluminum may be used for the lower metallization layers H 1  through H 13 , and the upper metallization layers H 21  through H 24 . The gate electrodes G 1  through G 8  and the upper electrodes U 1  and U 2  may be composed with polysilicon layer, and the p-type impurity diffused layers L 1  and L 2  may be used as the lower electrodes of the capacitors C 1  and C 2 . 
         [0041]    Consequently, the capacitors C 1  and C 2  may be formed together with the formation of the p-channel field-effect transistors M 2 , M 6 , M 7 , and M 8 , thereby configuring the charge pump circuit while preventing the complication of the manufacturing process. 
         [0042]      FIGS. 3A to 3B  are sectional drawings showing an exemplary structure of a fully depleted SOI transistor that has the source-tie structure. 
         [0043]    In  FIGS. 3A to 3B , a single-crystal semiconductor layer  23  is formed on an insulation layer  21 , and the single-crystal semiconductor layer  23  is separated with a device isolation insulation film  22 . Examples of material for the single-crystal semiconductor layer  23  include: Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, and ZnSe. An insulation layer or a buried insulation layer with materials such as SiO 2 , SiON, and Si 3 N 4  may be used for the insulation layer  21 . An SOI substrate, for instance, may be used as a supporting substrate that supports the insulation layer where the single-crystal semiconductor layer  23  is formed. Examples of substrates used for SOI substrate include: a Separation by Implanted Oxygen (SIMOX) substrate, an adhered substrate, and a laser annealed substrate. Insulation substrates formed with sapphire, glass, or ceramic may also be used for the supporting substrate. A gate electrode  25  is formed on the single-crystal semiconductor layer  23  via a gate insulation film  24 . A source layer  26   a  and a drain layer  26   b  are also formed on the single-crystal semiconductor layer  23 , arranged on each side of the gate electrode  25 . As shown in  FIG. 3B , the bottom of the source layer  26   a  and the drain layer  26   b  both make contact with the insulation layer  21 , and the body region under the gate electrode  25  is isolated between the source layer  26   a  and the drain layer  26   b.    
         [0044]    Body-source connection layers  27   a  and  27   b  are formed on the single-crystal semiconductor layer  23  that is on the side of the source layer  26   a,  arranged so as to sandwich the source layer  26   a,  touching the body region under the gate electrode  25 . An interlayer insulation film  29  is formed on the single-crystal semiconductor layer  23  on which the gate electrode  25  is formed. Source contacts C 11  and C 12  are formed on the source layer  26   a  side, so as to make contact with the source layer  26   a  and the body-source connection layers  27   a  and  27   b.    
         [0045]    Contact holes K 11  and K 12  are formed in the interlayer insulation film  29 , as shown in  FIG. 3C , arranged so that they cover the border between the source layer  26   a  and the body-source connection layer  27   a,  as well as between the source layer  26   a  and the body-source connection layer  27   b.  The source layer  26   a  and the body-source connection layers  27   a  and  27   b  are respectively connected to source metal layers  30   a  and  30   b  through the contact holes K 11  and K 12 . 
         [0046]    A gate contact C 15  is formed on the gate electrode  25  in order to make contact with it, and drain contacts C 13  and C 14  are formed on the drain layer  26   b  in order to contact it. 
         [0047]    Here, if the n-channel transistor is formed on the single-crystal semiconductor layer  23 , then the single-crystal semiconductor layer  23  and the body-source connection layers  27   a  and  27   b  are configured to p-type, and the source layer  26   a  and the drain layer  26   b  are configured to n +  type. 
         [0048]    Therefore, in the case where the holes, generated in the drain edge, flow into the body region, they may be released/drained to the source metal layers  30   a  and  30   b  through the body-source connection layers  27   a  and  27   b,  thereby allowing the suppression of the hot carrier accumulation in the body region. 
         [0049]    Consequently, since the SOI transistor is fully depleted, the drain deterioration caused by the hot carrier accumulation in the body region may be prevented while suppressing an area increase of parts, in the case where the body region under the gate electrode is isolated. 
         [0050]      FIG. 4  is a pattern diagram showing an output waveform of the boost circuit in  FIG. 1 . 
         [0051]    Here, for example, pulse signals with a duty ratio of 0.5 and an amplitude of 3V are input to the PHI terminal, and signals that are opposite phase to the ones input to the PHI terminal are input to the PHIRP terminal. Further, the pulse signals with a duty ratio of 0.5 and an amplitude of 3V are input to the PHIA terminal, and signals that are opposite phase to the ones input to the PHIA terminal is input to the PHIARP terminal. Moreover, the LVDD terminal is 3V, and the HVDD terminal is 6V, for instance. Still further, a 3V equivalent charge is accumulated on the capacitor C 2 , and no charge is accumulated in the capacitor C 1 . 
         [0052]    Subsequently, if the potential of the PHI terminal becomes 0V, then the n-channel field-effect transistor M 1  is switched off, and the p-channel field-effect transistor M 2  is switched on. If the potential of the PHI terminal becomes 0V, then the potential of the PHIRP terminal becomes 3V; thus the potential of the capacitor C 2  is pushed up by 3V, and the potential of the VDDORP terminal becomes 6V. If the potential of the VDDORP terminal is 6V, the potential of the PHIA terminal becomes 6V since the p-channel field-effect transistor M 2  is switched on, and the n-channel field-effect transistor M 3  is switched on. Thereafter, when the n-channel field-effect transistor M 3  is switched on, the potentials of the LVDD terminal and the PHI terminal are 3V and 0V respectively; hence the potential of the VDDO terminal becomes 3V and a voltage of 3V is applied to the capacitor C 1 , thereby accumulating the 3V equivalent charge. If the potential of the VDDO terminal is 3V, then the p-channel field-effect transistor M 8  is switched on, and the potential of the HVDD terminal becomes 6V. 
         [0053]    Subsequently, if the potential of the PHI terminal becomes 3V, then the n-channel field-effect transistor M 5  is switched off, and the p-channel field-effect transistor M 6  is switched on. If the potential of the PHIRP terminal is 0V, then the potential of the PHI terminal becomes 3V; thus the potential of the capacitor C 1  is pushed up by 3V, and the potential of the VDDO terminal becomes 6V. If the potential of the VDDO terminal is 6V, then the potential of the PHIARP terminal becomes 6V since the p-channel field-effect transistor M 6  is switched on, and the n-channel field-effect transistor M 4  is switched on. Thereafter, when the n-channel field-effect transistor M 4  is switched on, the potentials of the LVDD terminal and the PHIRP terminal are 3V and 0V respectively; hence the potential of the VDDORP terminal becomes 3V and a voltage of 3V is applied to the capacitor C 2 , thereby accumulating the 3V equivalent charge. If the potential of the VDDO terminal is 3V, then the p-channel field-effect transistor M 7  is switched on, and the potential of the HVDD terminal becomes 6V. 
         [0054]    As a result, a voltage of 6V is obtained by inputting the pulse signal with amplitude of 3V into the boost circuit indicated in  FIG. 1 . The input voltage may be boosted up by a factor of N, by connecting the boost circuit indicated in  FIG. 1  with n-steps. Here, the conversion efficiency of the charge pump circuit is normally in the range of approximately 60 to 70% (inclusive). However, by using the fully depleted SOI transistors for the n-channel field-effect transistors M 1 , M 3 , M 4 , M 5 , and the p-channel field-effect transistors M 2 , M 6 , M 7 , M 8 , the conversion efficiency of 80% may be obtained, improving the conversion efficiency. Consequently, a logic circuit and a boost circuit that operate in a low voltage may be packaged in a single chip, so that the logic circuit may be implemented in nonvolatile memories such as EEPROM that require 10V and/or more of high voltage, or in driver ICs for display devices such as liquid crystal. This allows an acceleration of semiconductor integrated circuits to become increasingly multifunctional and to be integrated in a higher density.