Abstract:
A cascade current Miller circuit includes a plurality of MOS transistors that form a current path (PASS 32 ) through which there is flown a current 1/m times the current flowing through a first pair of cascade current Miller circuits structured by two MOS transistors. Further, there are provided a plurality of MOS transistors that form a current path (PASS 33 ) through which there is flown a current 1/(m*3) times the current flowing through the first pair of cascade current Miller circuits. Further, there are provided a plurality of MOS transistors that form a current path (PASS 34 ) through which there is flown a current 2/(m*3) times the current flowing through the first pair of cascade current Miller circuits.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a cascade current Miller circuit that is advantageous for obtaining a voltage margin. 
     BACKGROUND OF THE INVENTION 
     FIG. 2 shows a conventional cascade current Miller circuit. The cascade current Miller circuit shown in FIG. 2 has a structure such that p-channel MOS transistors P 10  and P 12  forming a pair of current Miller circuits and p-channel MOS transistors P 11  and P 13  forming a pair of current Miller circuits are connected in cascade with each other. Of these pairs of current Miller circuits, the sources of the pair of current Miller circuits at the upper level (a first pair of current Miller circuits) are connected to a power supply voltage. Drain of the p-channel MOS transistor P 11 , that is the drain of one transistor of the two transistors forming the pair of current Miller circuits at the lower level (a second pair of current Miller circuits), is connected to a constant current source  9  that supply a constant current i. 
     Further, this cascade current Miller circuit has a structure such that n-channel MOS transistors N 10  and N 12  forming a pair of current Miller circuits and n-channel MOS transistors N 11  and N 13  forming a pair of current Miller circuits are connected in cascade with each other, to form a cascade Miller circuit. Drain of the n-channel MOS transistor N 10 , that is the drain of one transistor of the two transistors forming the pair of current Miller circuits at the upper level (a third pair of current Miller circuits), is connected to the drain of the p-channel MOS transistor P 13 . Thus the drain of the n-channel MOS transistor N 10  is connected to the drain of other transistor of the second pair of current Miller circuits. The sources of the pair of current Miller circuits at the lower level (a fourth pair of current Miller circuits) are connected to the ground. Further, the drain of the n-channel MOS transistor N 12 , that is the drain of other transistor of the third pair of current Miller circuits, is connected to a drain of a p-channel MOS transistor P 15 . The p-channel MOS transistor P 15  and a p-channel MOS transistor P 14  are cascade-connected and their sources are connected to a power supply voltage. 
     In the above-described structure, a current path (PASS 12 ) is formed by the p-channel MOS transistors P 14  and P 15  and the n-channel MOS transistors N 12  and N 13 , and a current path (PASS 10 ) is formed by the p-channel MOS transistors P 10  and P 11 . Further, a current path (PASS 11 ) is formed by the p-channel MOS transistors P 12  and P 13  and the n-channel MOS transistors N 10  and N 11 . Reference symbols shown at the bottom of the drawing indicate channel lengths (hereinafter to be referred to as L-size) and channel widths (hereinafter to be referred to as W-size) of the respective MOS transistors. Sizes within each bracket indicate L-size and W-size respectively. It is assumed that there is a relationship of PL 12 &gt;PL 13  and NL 11 &gt;NL 10 . 
     The operation of the cascade current Miller circuit will be explained below. At first, in FIG. 2, in the third and fourth current Miller circuits, there is a relationship that the W-size of the n-channel MOS transistor N 12  is n times the W-size of the n-channel MOS transistor N 10 , and the W-size of the n-channel MOS transistor N 13  is n times the W-size of the n-channel MOS transistor N 11 . Accordingly, the current flowing through the current path (PASS 12 ) is expressed as i*n by the current Miller transfer of a current i from the current path (PASS 11 ). 
     As shown in the drawing, a potential between the gate and the source (V GS10 ) and a potential between the drain and the source (V DS10 ) are equal, in the n-channel MOS transistor N 10  that is the origin of the current Miller transfer. Similarly, in the n-channel MOS transistor N 11 , a potential between the gate and the source (V GS11 ) and a potential between the drain and the source (V DS11 ) are equal. 
     Accordingly, a potential between the gate and the source (V GS13 ) has a relationship that V GS13 =V GS11 =V DS11  in the n-channel MOS transistor N 13  that is a current Miller transfer destination. Also, a potential between the gate and the source (V GS12 ) has a relationship that V GS12 =V G12 −V S12 =V GS11 +V GS10 −V DS13  in the n-channel MOS transistor N 12 . V G12  and V S12  respectively represent a gate potential and a source potential of the n-channel MOS transistor N 12 . 
     The following relationship is generally established in the saturation area of a MOS transistor. 
     
       
           V   GS   =SQRT (α IL/W ) +V   TH   
       
     
     where V GS , I, L, W and α respectively represent a voltage between the gate and the source, a drain current (I DS ), L-size and W-size, and a constant. 
     When Δ is substituted for SQRT (αIL/W), the following  10  relationship is established.                V   GS12     =                  Δ   11     +     V   TH11     +     Δ   10     +     V   TH10     -     V   DS13                   =                  Δ   13     +     V   TH13     +     Δ   12     +     V   TH12     -     V   DS13                                    
     Δ 10 , Δ 11 , Δ 12  and Δ 13  respectively represent the above Δ in the n-channel MOS transistors N 10 , N 11 , N 12  and N 13 . V TH10 , V TH11 , V TH12  and V TH13  respectively represent the above V TH  in the n-channel MOS transistors N 10 , N 11 , N 12  and N 13 . 
     In order for the above-described third and fourth pairs of current Miller circuits to operate normally, it is necessary that each MOS transistor always operates in the saturation area. In order for the MOS transistor to operate in the saturation area, it is necessary to satisfy the relationship V DS ≧V GS −V TH . Further, as the relationship of V GS =V TH +Δ is established in the saturation area as described above, in other words it is necessary to satisfy the relationship V DS ≧Δ. 
     On the other hand, it is necessary to satisfy the relationship V DS12 ≧V GS12 −V TH12  in the n-channel MOS transistor N 12 . This relationship can be modified as follows:                  V   D12     -     V   DS13       ≥                  V   G12     -     V   DS13     -     V   TH12                   =                  V   G10     -     V   DS13     -     V   TH12                     V   D12     ≥                  V   GS11     +     V   GS10     -     V   TH12                   =                  V   TH11     +     Δ   11     +     V   TH10     +       Δ                10     -     V   TH12                   =                  V   TH13     +     Δ   13     +     V   TH12     +     Δ   12     -     V   TH12                   =                  V   TH13     +     Δ   12     +     Δ   13                                    
     In the above expressions, V DS12 , V D12 , V G12 , V DS13  and V G10  respectively represent a voltage between the drain and the source of the n-channel MOS transistor N 12 , a drain potential of the same MOS transistor, a gate potential of the same MOS transistor, a voltage between the drain and the source of the n-channel MOS transistor N 13 , and a gate potential of the n-channel MOS transistor N 10 . 
     In order for the n-channel MOS transistors N 12  and N 13  to be always in saturation areas, it is necessary to satisfy the relationship of V DS   12 ≧Δ 12  and V DS13 ≧Δ 13 , that is, V D12  (=V DS12 +V DS13 )≧Δ 12 +Δ 13 . However, it is necessary to meet the following relationship V D12 ≧V TH13 +Δ 12 +Δ 13  as described above. Therefore, this cascade current Miller circuit requires an additional voltage of V TH13 . Thus, there has been known “a cascade current Miller circuit advantageous for obtaining a voltage margin” that has reduced the additionally-used voltage of V TH13 . 
     FIG. 3 is a diagram which shows a conventional cascade current Miller circuit advantageous for obtaining a voltage margin. In FIG. 3, current paths (PASS 25 ), (PASS 20 ) and (PASS  21  ) and MOS transistors P 20  to P 23 , P 27 , P 28 , N 20 , N 21 , N 28  and N 29  respectively correspond to (PASS 12 ), (PASS 10 ) and (PASS 11 ) and the MOS transistors P 10  to P 13 , P 14 , P 15 , N 10 , N 11 , N 12  and N 13  shown in FIG.  2 . 
     The cascade current Miller circuit shown in FIG. 3 includes, in addition to the circuit structure shown in FIG. 2, a p-channel MOS transistor P 24  forming a pair of current Miller circuits with the p-channel MOS transistor P 20 , p-channel MOS transistors P 25  and P 26  forming a pair of current Miller circuits, n-channel MOS transistors N 22  and N 24  forming a pair of current Miller circuits, n-channel MOS transistor N 23  and N 26  forming a pair of current Miller circuits, and n-channel MOS transistors N 25  and N 27  functioning as negative loads. 
     In the above-described structure, a current path (PASS 22 ) is formed by the p-channel MOS transistor P 24  and the n-channel MOS transistors N 22  and N 23 , a current path (PASS 23 ) is formed by the p-channel MOS transistor P 25  and the n-channel MOS transistors N 24 , N 25  and N 26 , and a current path (PASS 24 ) is formed by the p-channel MOS transistor P 26  and the n-channel MOS transistor N 27 . 
     The operation of the cascade current Miller circuit having the above-described structure advantageous for obtaining a voltage margin will be explained below. In FIG.  3 , there is a relationship such that the W-size of the n-channel MOS transistor N 28  is n times the W-size of the n-channel MOS transistor N 20 , and the W-size of the n-channel MOS transistor N 29  is n times the W-size of the n-channel MOS transistor N 21 . Accordingly, the current flowing through the current path (PASS 25 ) is expressed as i*n by the current Miller transfer of a current i from the current path (PASS 21 ). Further, as the p-channel MOS transistors P 20  and P 22  have the same sizes, the current i flowing through the current path (PASS 21 ) is the same as the current flowing through the current path (PASS 20 ). 
     Since the p-channel MOS transistors P 24  and P 22  have the same sizes, the current flowing through the current path (PASS 22 ) has the same magnitude i. Further, as the n-channel MOS transistors N 23  and N 26  have the same sizes, the current flowing through the n-channel MOS transistor N 26  has the same magnitude i. Further, as the size ratio of the p-channel MOS transistors P 25  to P 26  is 1:2, a current of magnitude i/3 flows through the current path (PASS 23 ) and a current of magnitude i*2/3 flows through the current path (PASS 24 ). 
     The potential at the node Y shown in this figure will be obtained. A drain potential V D22  of the n-channel MOS transistor N 22  can be expressed as follows.                V   D22     =                  V   DS22     +     V   DS23                   =                  V   GS22     +     V   GS23                   =                  V   TH22     +     Δ   22     +     V   TH23     +     Δ   23                   =                  V   TH20     +     Δ   20     +     V   TH21     +     Δ   21                                    
     In this case, V TH20  and Δ 20  represent a threshold level of the n-channel MOS transistor N 20  and the above Δ, respectively, and V TH21  and Δ 21  represent a threshold level of the n-channel MOS transistor N 21  and the above A , respectively. 
     Further, the drain voltage V D22  coincides with the gate voltage V G24  of n-channel MOS transistor N 24 , and the drain voltage V D26  of the n-channel MOS transistor N 26  can be expressed as V G24 −V GS24 −V DS25 . Therefore, the following relationship is established.                V   D26     =                  (       V   TH20     +     Δ   20     +     V   TH21     +     Δ   21       )     -     (       V   TH24     +     Δ   24       )     -     (       V   TH25     +     Δ   25       )                   =                  (       V   TH20     +     Δ   20     +     V   TH21     +     Δ   21       )     -     (       V   TH21     +       Δ   21     /     3         )     -                              (       V   TH21     +       Δ   21     /     3         )                                  
     In this case, V GS24  and V DS25  represent a voltage between the gate and the source of the n-channel MOS transistor N 24  and a voltage between the drain the source of the n-channel MOS transistor N 25 , respectively. 
     The potential of the node “Y” can be expressed as V D26 +V GS27 . Therefore, the following relationship is established as a result.                V   Y     =                  (       V   TH20     +     Δ   20     +     V   TH21     +     Δ   21       )     -     2        (       V   TH21     +       Δ   21     /     3         )       +                              (       V   TH21     +     2          Δ   21     /     3           )                 =                  V   TH20     +     Δ   20     +       Δ   21     .                                    
     In this case, V DS22 , V GS22 , V TH22  and Δ 22  represent a voltage between the drain and the source of the n-channel MOS transistor N 22 , a voltage between the gate and the source of the same MOS transistor, a threshold level of the same MOS transistor, and the above Δ, respectively. Further, V DS23 , V GS23 , V TH23  and Δ 23  represent a voltage between the drain and the source of the n-channel MOS transistor N 23 , a voltage between the gate and the source of the same MOS transistor, a threshold level of the same MOS transistor, and the above A, respectively. 
     On the other hand, in order for the n-channel MOS transistors N 28  to operate in a saturation area, it is necessary to meet the relationship of V DS28 ≧V GS28 −V TH28 . Therefore, the following relationship is established.                  V   D28     -     V   DS29       ≥                  V   G28     -     V   DS29     -     V   TH28                   =                  V   Y     -     V   DS29     -     V   TH28                   =                  V   TH20     +     Δ   20     +     Δ   21     -     V   DS29     -     V   TH20                                    
     In other words, the relationship of V DS28 ≧Δ 20 +Δ 21  is obtained. This corresponds to the theoretical expression of V D12 &gt;Δ 12 +Δ 13  obtained in the explanation of the normal cascade current Miller circuit. 
     Accordingly, this cascade current Miller circuit includes the above-described three current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) for obtaining the above-described voltage Y, in addition to the above-described normal cascade current Miller circuit. As a result, it is possible to operate for an input of a large signal corresponding to the voltage of V TH13  shown in FIG.  2 . 
     In the above expressions, V DS28 , V GS28 , V TH28 , V G28  and V D28  represent a voltage between the drain and the source of the n-channel MOS transistor N 28 , a voltage between the gate and the source of the same MOS transistor, a threshold level of the same MOS transistor, a gate voltage and a drain voltage of the same MOS transistor, respectively. V DS29  represents a voltage between the drain and the source of the n-channel MOS transistor N 29 . 
     Further, the n-channel MOS transistor N 29  has the following relationship.                V   DS29     =       V   Y     -     V   GS28                   =       V   Y     -     V   TH28     -     Δ   28                   =       V   Y     -     V   TH20     -     Δ   20                   =       V   TH20     +     Δ   20     +     Δ   21     -     V   TH20     -     Δ   20                   =       Δ   21     =     Δ   29                                    
     Thus, it is can be understood that the n-channel MOS transistor N 29  is in the saturation area when V DS29 ≧Δ 29 . 
     In the above-described cascade current Miller circuit advantageous for obtaining a voltage margin shown in FIG. 3, the magnitudes of the currents flowing through the three current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) are assumed as i, i/3 and i*2/3 respectively. However, as the object of the circuit is to obtain the above-described voltage Y, the magnitudes of i, i/3 and i*2/3 are not necessarily required in the above current paths. Particularly, when the other circuits do not require a large current by using this cascade current Miller circuit, the magnitudes of these currents flowing through the three current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) were not optimum. Therefore, these current levels have been a cause of interrupting energy saving of the circuit. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a cascade current Miller circuit advantageous for obtaining a voltage margin and having a low power consumption. 
     In order to achieve the object of the present invention, the cascade current Miller circuit according to the invention has such a configuration that the currents flowing through the three current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) shown in FIG. 3 are decreased. Thus, the power consumption of the circuit as a whole can be reduced. 
     Further, the sizes of the first to third MOS transistors are set smaller than the size of each MOS transistor constituting the first pair of cascade current Miller circuits so that the currents flowing through the three current paths additionally provided for increasing the variable range of the output voltage are set smaller than the current flowing through the first cascade current Miller circuit. Therefore, it is possible to use a small current for obtaining a desired level of output voltage in a smaller layout area of the circuit. 
     Further, the sizes of the first to third MOS transistors are set smaller than the size of each MOS transistor constituting the second pair of cascade current Miller circuits so that the currents flowing through the three current paths additionally provided for increasing the variable range of the output voltage are set smaller than the current flowing through the first cascade current Miller circuit. Therefore, it is possible to use a small current for obtaining a desired level of output voltage in a smaller layout area of the circuit. 
     Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a cascade current Miller circuit of one embodiment of the present invention; 
     FIG. 2 shows one example of a conventional cascade current Miller circuit; and 
     FIG. 3 shows one example of a conventional cascade current Miller circuit advantageous for obtaining a voltage margin. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     There will be explained in detail below an embodiment of a cascade current Miller circuit relating to the present invention with reference to the drawings. 
     The cascade current Miller circuit of the present embodiment is characterized in that, in the conventional cascade current Miller circuit advantageous for obtaining a voltage margin shown in FIG. 3, the currents flowing through the three current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) are decreased, thereby to reduce the power consumption of the circuit as a whole. 
     FIG. 1 shows the cascade current Miller circuit of this embodiment. The cascade current Miller circuit shown in FIG. 1 has the same structure as the cascade current Miller circuit shown in FIG. 3, except that the parts have been provided with different reference numbers. This cascade current Miller circuit is different from the conventional cascade current Miller circuit shown in FIG. 3 in that all the W-sizes of MOS transistors on current paths (PASS 32 ), (PASS 33 ) and (PASS 34 ) respectively are 1/m of the W-sizes of the MOS transistors shown in FIG. 3, so that the magnitudes of all the currents are decreased by 1/m and the layout area is also reduced. 
     Particularly, the present embodiment is characterized in that a potential Y′ (potential at the node Y′) shown in FIG. 1 is the same as the potential Y shown in FIG. 3 regardless of the reduction in the W-sizes of the MOS transistors. This potential Y′ will be explained below. First, a drain potential V D32  of an n-channel MOS transistor N 32  is expressed as follows.                V   D32     =                  V   DS32     +     V   DS33                   =                  V   GS32     +     V   GS33                   =                  V   TH32     +     Δ   32     +     V   TH33     +     Δ   33                   =                V   G34                                  
     Therefore, a drain potential VD 36  of an n-channel MOS transistor N 36  can be expressed as follows.                V   D36     =                  V   G34     -     V   GS34     -     V   GS35                   =                  V   TH32     +     Δ   32     +     V   TH33     +     Δ   33     -     V   TH34     -     Δ   34     -     V   TH35     -     Δ   35                   =                  V   TH32     +     Δ   32     +     V   TH33     +     Δ   33     -     V   TH33     -       Δ   33     /     3       -     V   TH33     -                                Δ   33     /     3                                    
     In view of the above fact, the potential Y′ can be expressed as follows.                V     Y   ′       =                      V   D     36     +     V   GS37       =       V   D36     +     V   TH33     +     2          Δ   33     /     3                         =                  V   TH32     +     Δ   32     +     V   TH33     +     Δ   33     -     V   TH33     -       Δ   33     /     3       -     V   TH33     -                                  Δ   33     /     3       +     V   TH33     +     2          Δ   33     /     3                       =                  V   TH30     +     Δ   30     +     Δ   31                                    
     This result corresponds to the above-described potential Y, that is, V Y =V TH20 +Δ 20 +Δ 21 , and thus V Y′  and V Y  have same magnitude. 
     Further, a potential Z′ (potential at the node Z′) is expressed as V Z′ =V GS31 =V TH31 +Δ 31  in FIG.  1 . Also, a potential Z shown in FIG. 3 is expressed as V Z =V GS21 =V TH21 +Δ 21 . Therefore, when the n-channel MOS transistors N 21  and N 31  have the same sizes, the potentials of these MOS transistors also coincide with each other. 
     As explained above, when the MOS transistors on the three current paths (PASS 32 ), (PASS 33 ) and (PASS 34 ) have sizes 1/m times the sizes of the conventional MOS transistors on the three current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) shown in FIG. 3 respectively, the power consumption of the circuit as a whole is also reduced to 1/m. Thus, it is also possible to reduce the size of the layout without changing the potentials Y′ and Z′ that are output. 
     According to the conventional cascade current Miller circuit shown in FIG. 3, the p-channel MOS transistors P 22  and P 24  have been set to have the same sizes in order to have the same current levels for the currents flowing through the current paths (PASS 22 ) and (PASS 21 ). Further, in order to set the threshold level V TH  of the n-channel MOS transistor N 21  equal to the threshold levels V TH  of the n-channel MOS transistors N 24 , N 25  and N 27  respectively, the L-sizes NL 21 , NL 24 , NL 25  and NL 27  of these n-channel MOS transistors have been set equal to each other. 
     Further, in order to cancel the above-described Δ(=SQRT (αIL/W)), the ratio of the W-sizes of the p-channel MOS transistors P 25  and P 26  has been set as PW 25 :PW 26 =1:2, and the W-sizes of the n-channel MOS transistors N 21  and N 27  have been designed to have the relationship of NW 27 =NW 21 /2. 
     On the other hand, according to the cascade current Miller circuit shown in FIG. 1, in order to reduce the volume of the current flowing through the current path (PASS 32 ), the W-sizes of the p-channel MOS transistors P 32  and P 34  are designed to have the relationship of PW 34 =PW 32 /m. Further, in order to set the current flowing through the n-channel MOS transistor N 36  at an equal level to that of the current flowing through the n-channel MOS transistor N 33 , these MOS transistors are set to have the same sizes. 
     Further, in order to set the threshold level V TH  of the n-channel MOS transistor N 31  equal to the threshold levels V TH  of the n-channel MOS transistors N 34 , N 35  and N 37  respectively, the L-sizes NL 31 , NL 34 , NL 35  and NL 37  of these n-channel MOS transistors are set equal to each other. Further, in order to cancel the above-described Δ(=SQRT (αIL/W)), the ratio of the W-sizes of the p-channel MOS transistors P 35  and P 36  is set as PW 35 :PW 36 =1:2, and the W-sizes of the p-channel MOS transistors N 31  and N 37  are designed to have the relationship of NW 37 =NW 31 /2. 
     According to the prior-art cascade current Miller circuit shown in FIG. 3, the total of the currents flowing through the three additionally-provided current paths (PASS 22 ), (PASS 23 ) and (PASS 24 ) becomes 2i, which has no significant problem when the current i has a small current value of around a few μA. However, when the current value i becomes as large as tens of μA to hundreds of μA, the current of 2i cannot be disregarded. 
     On the other hand, as explained above, according to the cascade current Miller circuit relating to the present embodiment, the reduction in the current value i to 1/m without changing the potentials Y′ and Z′ that are important for the circuit, is effective in achieving energy saving. Particularly, as the sizes of the transistors become smaller, the layout area can also be made smaller, which makes it possible to improve the theoretical yield of wafers. 
     As explained above, according to the present invention, as the currents flowing through the three current paths additionally provided for increasing the variable range of the output voltage are set smaller than the current flowing through the first cascade current Miller circuit, it is possible to use a small current for obtaining a desired level of output voltage. The present invention has an effect that it is possible to reduce the power consumption of the circuit as a whole. 
     Further, the sizes of the first to third MOS transistors are set smaller than the size of each MOS transistor constituting the first pair of cascade current Miller circuits so that the currents flowing through the three current paths additionally provided for increasing the variable range of the output voltage are set smaller than the current flowing through the first cascade current Miller circuit. There is also an effect that a small current can be used to obtain a desired output voltage, which makes it possible to decrease the power consumption of the circuit as a whole and to make smaller the layout area of the circuit. 
     Further, the sizes of the first to third MOS transistors are set smaller than the size of each MOS transistor constituting the second pair of cascade current Miller circuits so that the currents flowing through the three current paths additionally provided for increasing the variable range of the output voltage are set smaller than the current flowing through the first cascade current Miller circuit. There is also an effect that a small current can be used to obtain a desired output voltage, which makes it possible to decrease the power consumption of the circuit as a whole and to make smaller the layout area of the circuit. 
     Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.