Abstract:
An apparatus processes a packet and classifies the packet as a processed fast path packet or a slow path packet, wherein the processed fast path packet is forwarded to a fast path forwarding queue directly or is forwarded to a fast path output queue through a packet direct memory access controller. The apparatus not only improves the packet processing performance but also guarantees the quality of service.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an apparatus for processing packets and a system for using the same, and more particularly to an apparatus for improving the packet processing speed with classified fast path packets and classified slow path packets and a system for using the same. 
         [0003]    2. Description of the Related Art 
         [0004]    With the popularity of the internet, various applications are increasing rapidly. Numerous organizations devote extensive resources to research seeking improvements in internet data communication quality. When transmitting data in different applications, the allowable packet length varies and systems include a number of processing programs for manipulating packet data, such as examination, decomposition, combination, searching, comparison of content, and data rerouting. Accordingly, with rapid developments of bandwidth requirements in network applications, such as applications in home networks, campus networks, and business networks, as well as increasingly large quantities of packet data transmission, more and more attention is given to improving packet transmission performance and packet processing technology. 
         [0005]    Compared to data communication, transmission of voice over IP (VoIP) requires greater quality of service (QoS). The Qos index includes packet latency, packets lost, and packet delay jitter. When a large amount of data is suddenly forwarded in a network, the transmission of the voice packet is affected, and therefore the packet transmission may be postponed or abandoned because the network apparatus cannot handle it in time. When a packet delay occurs during VoIP service, users can distinguish the presence of an echo. An acceptable network transmission environment with good packet data processing performance ensures that the packet delay is less than 150 ms. Acceptable levels of sound delay for users of normal hearing are considered to be about 150 ms to 400 ms, and thus any delay over 400 ms will cause extremely poor sound quality for users. 
         [0006]    In order to improve the processing performance, many technologies and methods have been proposed. For example, a specific packet processing engine (PPE) in a system for processing packet data is configured to improve the packet processing speed.  FIG. 1  shows a block diagram of a packet processing system. A packet is forwarded to a packet processing engine (PPE)  109  through a media access control (MAC)  111  and a direct memory access (DMA) controller  110 . If the packet is processed by the PPE  109  and is classified as a processed fast path packet, then the packet is forwarded directly to a forwarding queue  108 . If the packet is processed by the PPE  109  and is classified as a slow path packet, then the packet is forwarded directly to a receiving queue  106 . Next, the packet is forwarded to a central processing unit (CPU)  101  for processing through a packet direct memory access (PDMA) controller  105  and an input queue  102 . Subsequently, a processed packet from the CPU is forwarded to the forwarding queue  108  through an output queue  103 , a scheduler  104 , and a PDMA controller  107 . Finally, the processed packet is forwarded to a wide area network (WAN) port through a DMA controller  112  and a MAC  113 . In this system, the PPE  109  can improve the processing speed of the fast path packet and can store the fast path packet to the output queue  108  directly for forwarding. However, due to the limited storage space of the forwarding queue  108 , most of the storage space may be occupied by fast path packets and thus the important slow path packets to be forwarded are postponed. Accordingly, current industry research is highly focused on improving both packet processing speeds and quality of service at the same time. 
       SUMMARY OF THE INVENTION 
       [0007]    An aspect of the present invention is to provide an apparatus for processing packets and a system for using the same. The apparatus processes and classifies a packet as a processed fast path packet or a slow path packet, wherein the processed fast path packet is forwarded to a fast path forwarding queue directly or is forwarded to a fast path output queue through a packet direct memory access controller to guarantee the quality of service. 
         [0008]    The first embodiment of the present invention discloses a packet processing apparatus. The packet processing apparatus comprises at least one PPE, a receiving queue, a first PDMA controller, a second PDMA controller, a fast path forwarding queue, and a slow path forwarding queue. The at least one PPE is configured to process a packet and classify the packet as a processed fast path packet or a slow path packet, and the receiving queue is configured to store the slow path packet. The first PDMA controller is configured to forward the slow path packet, which is stored in the receiving queue, to an input queue, and the second PDMA controller is configured to receive a processed slow path packet. The fast path forwarding queue is connected to the PPE and configured to store the processed fast path packet, and the slow path forwarding queue is connected to the second PDMA controller and configured to store the processed slow path packet. 
         [0009]    The second embodiment of the present invention discloses a packet processing system. The packet processing system comprises a packet processing apparatus shown in the first embodiment, a receiving queue, a central processing unit, and an output queue. 
         [0010]    The third embodiment of the present invention discloses a packet processing apparatus. The packet processing apparatus comprises at least one PPE, a receiving queue, a first PDMA controller, a second PDMA controller, and a forwarding queue. The PPE is configured to process a packet and classify the packet as a processed fast path packet or a slow path packet, and the receiving queue is configured to store the processed fast path packet and the slow path packet. The first PDMA controller is configured to forward the processed fast path packet, which is stored in the receiving queue, to an output queue or forward the slow path packet, which is stored in the receiving queue, to an input queue, and the second PDMA controller is configured to receive the processed fast path packet or a processed slow path packet. The forwarding queue is connected to the second PDMA controller and configured to store the processed fast path packet and the processed slow path packet. 
         [0011]    The fourth embodiment of the present invention discloses a packet processing system. The packet processing system comprises a packet processing apparatus shown in the third embodiment, a receiving queue, a central processing unit, and an output queue. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The invention will be described according to the appended drawings in which: 
           [0013]      FIG. 1  illustrates a block diagram of a packet processing system; 
           [0014]      FIG. 2  illustrates a block diagram of a packet processing apparatus according to one embodiment of the present invention; 
           [0015]      FIG. 3  illustrates the flow chart of a packet processing method according to one embodiment of the present invention; 
           [0016]      FIG. 4  illustrates a block diagram of a packet processing apparatus according to another embodiment of the present invention; and 
           [0017]      FIG. 5  illustrates the flow chart of a packet processing method according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]      FIG. 2  illustrates a block diagram of a packet processing apparatus according to one embodiment of the present invention. The packet processing apparatus  200  comprises a packet direct memory access (PDMA) controller  205 , a receiving queue  206 , a PDMA controller  207 , a slow path forwarding queue (SPFQ)  208 , a fast path forwarding queue (FPFQ)  208 ′, and a packet processing engine (PPE)  209 . The receiving queue  206  comprises a slow path high priority receiving queue (SPHPRQ)  25  and a slow path low priority receiving queue (SPLPRQ)  26 . The SPFQ  208  comprises a slow path high priority forwarding queue (SPHPFQ)  27  and a slow path low priority forwarding queue (SPLPFQ)  28 . The FPFQ  208 ′ comprises a fast path high priority forwarding queue (FPHPFQ)  29  and a fast path low priority forwarding queue (FPLPFQ)  30 . The above-mentioned receiving queue  206 , the SPFQ  208 , and the FPFQ  208 ′ are located in a static random access memory (SRAM). 
         [0019]    The PPE  209  is configured to process a packet and classify the packet as a processed fast path packet or a slow path packet. The processed fast path packet is a processed fast path high priority packet or a processed fast path low priority packet. The slow path packet is a slow path high priority packet or a slow path low priority packet. The SPHPRQ  25  is utilized to store the slow path high priority packet, and the SPLPRQ  26  is utilized to store the slow path low priority packet. The PDMA controller  205  is utilized to forward a slow path packet, which is stored in the SPLPRQ  26 , to an input queue  202 . A slow path high priority input queue (SPHPIQ)  21  is utilized to store the slow path high priority packet, and a slow path low priority input queue (SPLPIQ)  22  is utilized to store the slow path low priority packet. The PDMA controller  207  is utilized to receive a processed slow path packet processed by a central processing unit (CPU)  201 , wherein the processed slow path packet is a processed slow path high priority packet or a processed slow path low priority packet. The SPHPFQ  27  is utilized to store the processed slow path high priority packet, and the SPLPFQ  28  is utilized to store the processed slow path low priority packet. The FPHPFQ  29  is utilized to store the processed fast path high priority packet, and the FPLPFQ  30  is utilized to store the processed fast path low priority packet. In order to enable those skilled in the art to practice the present invention,  FIG. 2 , together with an apparatus for processing packets in accordance with another embodiment, is described as follows. 
         [0020]      FIG. 3  shows the flow chart of a packet processing method according to another embodiment of the present invention. A packet is inputted through a local area network (LAN) port, and is forwarded to the PPE  209  through a media access control (MAC)  211  and a direct memory access (DMA) controller  210 . In step S 301 , the PPE  209  receives the packet form the DMA controller  210 . In step S 302 , the PPE  209  is utilized to process the packet and classify the packet as a processed fast path packet or a slow path packet, wherein the processed fast path packet is a processed fast path high priority packet or a processed fast path low priority packet, and the slow path packet is a slow path high priority packet or a slow path low priority packet. In step S 303 , if the packet processed by the PPE  209  was classified as a processed fast path high priority packet or a processed fast path low priority packet, then the processed fast path high priority packet is stored in the FPHPFQ  29  or the processed fast path low priority packet is stored in the FPLPFQ  30  in step S 304 . In step S 303 , if the packet processed by the PPE  209  and was classified as a slow path high priority packet or a slow path low priority packet, then the slow path high priority packet is stored to the SPHPRQ  25  or the slow path low priority packet is stored to the SPLPRQ  26  in step S 306 . In step S 307 , the slow path high priority packet stored in the SPHPRQ  25  is forwarded to the SPHPIQ  21  through the PDMA controller  205 , or the slow path low priority packet stored in the SPLPRQ  26  is forwarded to the SPLPIQ  22 . The slow path high priority packet or the slow path low priority packet is processed by the CPU  201 . In step S 308 , a processed slow path packet is stored in an output queue  203 . The output queue  203  comprises a slow path high priority output queue (SPHPOQ)  23  and a slow path low priority output queue (SPLPOQ)  24 . The processed slow path packet is a processed slow path high priority packet or a processed slow path low priority packet. The packet stored in the output queue  203  is then forwarded to the PDMA controller  207  through a scheduler  204 . In step S 309 , the processed slow path high priority packet or the processed slow path low priority packet from the PDMA controller  207  is received. If the packet is the processed slow path high priority packet, then the packet is stored in the SPHPFQ  27 . If the packet is the processed slow path low priority packet, then the packet is stored in the SPLPFQ  28 . In step S 305 , the packet stored in the SPHPFQ  27 , the SPLPFQ  28 , the FPHPFQ  29 , or the FPLPFQ  30  is outputted to a direct memory access (DMA) controller  212 , and is outputted to a wide area network (WAN) port through a media access control  213 . 
         [0021]      FIG. 4  shows a block diagram of a packet processing apparatus according to another embodiment of the present invention. The packet processing apparatus  400  comprises a packet direct memory access (PDMA) controller  405 , a receiving queue  406 , a packet direct memory access (PDMA) controller  407 , a forwarding queue  408 , and a packet processing engine (PPE)  409 . The receiving queue  406  comprises a slow path high priority receiving queue (SPHPRQ)  47  and a slow path low priority receiving queue (SPLPRQ)  48 , a fast path high priority receiving queue (FPHPRQ)  49 , and a fast path low priority receiving queue (FPLPRQ)  50 . The above-mentioned receiving queue  406  and the forwarding queue  408  are located in a SRAM. 
         [0022]    The PPE  409  is utilized to process a packet and classify the packet as a processed fast path packet or a slow path packet. The processed fast path packet is a processed fast path high priority packet or a processed fast path low priority packet. The slow path packet is a slow path high priority packet or a slow path low priority packet. The SPHPRQ  47  is utilized to store the slow path high priority packet, and the SPLPRQ  48  is utilized to store the slow path low priority packet. The FPHPRQ  49  is utilized to store the fast path high priority packet, and the FPLPRQ  50  is utilized to store the fast path low priority packet. The PDMA controller  405  is utilized to forward packets, which are stored in the SPHPRQ  47  or the SPLPRQ  48 , to an input queue  402 , wherein a slow path high priority input queue (SPHPIQ)  41  is utilized to store the slow path high priority packet, and a slow path low priority input queue (SPLPIQ)  42  is utilized to store the slow path low priority packet. The PDMA controller  405  is also utilized to forward packets, which are stored in the FPHPRQ  49  or in the FPLPRQ  50 , to an output queue  403 . In the output queue  403 , a slow path high priority output queue (SPHPOQ)  43  is utilized to store a processed slow path high priority packet, a slow path low priority output queue (SPLPOQ)  44  is utilized to store a processed slow path low priority packet, a fast path high priority output queue (FPHPOQ)  45  is utilized to store the processed fast path high priority packet, and a fast path low priority output queue (FPLPOQ)  46  is utilized to store the processed fast path low priority packet. The output queue  403  is located in a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), or a double data rate (DDR) SDRAM. The PDMA controller  407  is utilized to receive the processed fast path high priority packet or the processed fast path low priority packet. The PDMA controller  407  is also utilized to receive the processed slow path high priority packet or the processed slow path low priority packet, both of which are processed by a CPU  401 . The forwarding queue  408  is utilized to store the processed slow path high priority packet, the processed slow path low priority packet, the processed fast path high priority packet, or the processed fast path low priority packet from the PDMA controller  407 . In order to enable those skilled in the art to practice the present invention,  FIG. 4 , together with an apparatus for processing packets in accordance with another embodiment, is described as follows. 
         [0023]      FIG. 5  shows the flow chart of a packet processing method according to another embodiment of the present invention. A packet is inputted through an LNA port, and is forwarded to the PPE  409  through a MAC  411  and a DMA controller  410 . In step S 501 , the PPE  209  receives the packet from the DMA controller  410 . In step S 502 , the PPE  409  is utilized to process the packet and classify the packet as a processed fast path packet or a slow path packet, wherein the processed fast path packet is a processed fast path high priority packet or a processed fast path low priority packet, and the slow path packet is a slow path high priority packet or a slow path low priority packet. In step S 503 , if the packet processed by the PPE  409  was classified as a processed fast path high priority packet or a processed fast path low priority packet, then the processed fast path high priority packet is stored in the FPHPRQ  49  or the processed fast path low priority packet is stored in the FPLPRQ  50  in step S 504 . In step  505 , the fast path high priority packet stored in the FPHPRQ  49  is forwarded to the fast path high priority output queue (FPHPOQ)  45  through the PDMA controller  405 , or the fast path low priority packet stored in the FPLPRQ  50  is forwarded to the FPLPOQ  46  through the PDMA  405 . Next, the packet in the FPHPOQ  45  or in the FPLPOQ  46  is forwarded to the PDMA controller  407  through a scheduler  404 . In step S 503 , if the packet processed by the PPE  409  was classified as a slow path high priority packet or a slow path low priority packet, then the slow path high priority packet is stored in the SPHPRQ  47  or the slow path low priority packet is stored in the SPLPRQ  48  in step S 508 . In step S 509 , the slow path high priority packet stored in the SPHPRQ  47  is forwarded to the SPHPIQ  41  through the PDMA controller  405 , or the slow path low priority packet stored in the SPLPRQ  48  is forwarded to the SPLPIQ  42 . The slow path high priority packet or the slow path low priority packet is processed by the CPU  401 . In step S 510 , a processed slow path packet is stored in the SPHPOQ  43  or in the SPLPOQ  44 . Next, the processed slow path packet is forwarded by the scheduler  404  to the PDMA controller  407 . The processed slow path packet is a processed slow path high priority packet or a processed slow path low priority packet. In step S 506 , the processed fast path high priority packet, the processed fast path low priority packet, the processed slow path high priority packet, or the processed slow path low priority packet from the PDMA controller  407  is received and is stored in the forwarding queue  408 . In step S 507 , the processed fast path high priority packet, the processed fast path low priority packet, the processed slow path high priority packet, or the processed slow path low priority packet stored in the forwarding queue  408  is outputted to a DMA controller  412 , and is finally outputted to a WAN port through a media access control  413 . 
         [0024]    The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.