Abstract:
A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes alumina and optionally a nitride, and has a layer thickness satisfying the high aspect ratio of the gaps between the surface structures, while adequately preventing dopants in doped glass layer from diffusing out of the doped glass layer to the surface structures and the substrate. Further, heavy water can be used during the formation of the alumina so that deuterium may be accomplished near the interface of surface structures and the substrate to enhance the performance of the device.

Description:
This application is a Divisional of U.S. application Ser. No. 10/233,279, filed Aug. 29, 2002, now U.S. Pat. No. 6,833,575, which is incorporated herein by reference. 

   FIELD 
   The present invention relates generally to integrated circuits, and in particular, to dielectric structures in semiconductor devices. 
   BACKGROUND 
   Semiconductor devices reside in many electrical products to operate as resistors, capacitors, transistors, memory cells, and other components. A typical semiconductor device has many surface structures formed above a substrate and many active regions formed within the substrate. The surface structures and the active regions act together to form the function of the semiconductor device. 
   A dielectric layer is usually blanketed over the surface structures and the substrate to insulate them from other circuit layers within the semiconductor device. Glass is usually the material for this kind of dielectric layer. 
   During manufacturing, the glass layer (dielectric layer) is first deposited. Next, a reflow (melting) process is performed to flatten the surface of the glass layer. Today, the glass is usually doped with materials such as boron and phosphorous (dopants) to reduce the temperature of the reflow process. Thus, a doped glass has one or more dopant materials. The dopant in the doped glass, however, tends to diffuse outward and migrate to the surface structures and the substrate. This outward diffusion may change the electrical properties of the surface structures, the active regions in the substrate, the substrate itself, and hence, the performance of the device. 
   Most devices now have a barrier layer sandwiched between the doped glass layer and the surface structures to prevent the migration of the dopant from the doped glass layer to the surface structures and the substrate. 
   Silicon nitride has been suggested as the material for the barrier layer. However, the device formed by the surface structures and the active regions may suffer from underalloy due to hydrogen blocking properties. Static retention time may decrease when silicon nitride is used on a silicon substrate. This may be caused by stress, interface build up, or fixed charge. 
   Further, today, with increasing aspect ratio (depth to width ratio) of the gaps between the surface structures (for example, narrower gaps), the barrier layer is limited to a certain layer thickness in these gaps. With this layer thickness limitation, silicon nitride and other tetraethooxysilane (TEOS) materials may not be thick enough to prevent the outward diffusion of the dopant in the doped glass. 
   Thus, there is a need for an alternative barrier layer. 
   SUMMARY OF THE INVENTION 
   The present invention provides structures and methods for an improved dopant barrier layer for doped glass. 
   One aspect offers a semiconductor device including a substrate with a surface structure formed over it. An alumina layer is formed on and conforming to the surface structure and the substrate. A doped glass layer is formed over the alumina layer. The semiconductor device further includes an insulating layer formed between doped glass layer and the surface structure and the substrate. 
   Another aspect provides a method of forming a device. The method includes forming an alumina layer on multiple surface structures and a substrate of the memory device. The method also includes covering the alumina layer with a doped glass layer. The method further includes planarizing the doped glass layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1A  is a cross-section of a semiconductor device according to an embodiment of the invention. 
       FIG. 1B  is a cross-section of a semiconductor device according to another embodiment of the invention. 
       FIGS. 2-6  are cross-sections of the semiconductor device of  FIG. 1A  during various processing stages according to embodiments of the invention. 
       FIG. 7A  is a cross-section of a portion of a memory device according to an embodiment of the invention. 
       FIG. 7B  is a cross-section of a portion of a memory device according to another embodiment of the invention. 
       FIGS. 8-15  are cross-sections of the portion of the memory device of  FIG. 7A  during various processing stages according to embodiments of the invention. 
       FIG. 16  shows a memory device according to an embodiment of the invention. 
       FIG. 17  shows a system according to an embodiment of the invention. 
   

   DESCRIPTION OF EMBODIMENTS 
   The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice it. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like numerals describe substantially similar components throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the full ambit of the claims and all available equivalents. 
     FIG. 1A  is a cross-section of a part of a semiconductor device according to an embodiment of the invention. Device  100  includes a substrate  102  and surface structures  104  and  106  formed on substrate  102  at interfaces  107  and  109 . Surface structures  104  and  106  are separated from each other by a gap  108 , which has a height (or depth) H and a width W. Device  100  can be any kind of device such as a dynamic random access memory (DRAM) device, a static random access memory device (SRAM), a flash memory device, a processor, an application specific integrated circuit (ASIC), or other semiconductor devices. 
   Substrate  102  can be a silicon wafer or any other conventional structure that is used as a base to form circuits. Surface structures  104  and  106  include semiconductor material, such as polysilicon, and can perform certain functions by themselves or in combination with structures in substrate  102 . For example, surface structures  104  and  106  can be gate structures of transistors, in which these gate structures together with structures in substrate  102  form transistors and memory cells a memory device. 
   Device  100  further includes a diffusion barrier  105  and a doped glass layer  130 , all formed over surface structures  104  and  106  and substrate  102 . Diffusion barrier  105  includes an alumina (Al 2 O 3 ) layer  110  and insulating layer  120 . Alumina layer  110  conforms to surface structures  104  and  106  and substrate  102 . Insulating layer  120  conforms to alumina layer  110 . The bottom surface of doped glass layer  130  conforms to insulating layer  120 . A top surface  115  of doped glass layer  130  is planarized (flat). In some embodiments, top surface  115  can be other shapes. Insulating layer  120  can include silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ), or other insulating materials. 
   In embodiments represented by  FIG. 1A , insulating layer  120  is formed over alumina layer  110 . In some embodiments, insulating layer  120  can be formed under alumina layer  110 . In other embodiments, insulating layer  120  is omitted. 
   Alumina layer  110  has a thickness T 1 . In some embodiments, T 1  is in the range of about 20 to about 200 Angstroms. Insulating layer  120  has a thickness T 2 . In some embodiments, T 2  is in the range of about 20 to about 200 Angstroms. In other embodiments, diffusion barrier  105  has a thickness T 3  in the range of about 20 to about 400 Angstroms. Doped glass layer  130  can be a silicate glass doped with one or more dopants such as boron and phosphorous, or other type of doped glass. For example, doped glass layer  130  can be Boronsilicate glass (BSG), or Phosphosilicate glass (PSG). In  FIG. 1 , doped glass layer  130  includes Borophosphosilicate glass (BPSG) and has a thickness T 4 . In some embodiments, T 4  is in the range of 2000 to 12000 Angstroms. 
   Device  100  also includes a contact structure  150  formed in a self aligned contact  160  which extends through doped glass layer  130  and diffusion barrier  105  to substrate  102 . Contact structure  150  provides electrical connection to active regions (not shown) formed within substrate  102 . 
   The aspect ratio of gap  108  is the ratio between the height H and the width W (H/W). A maximum thickness of a layer formed in gap  108  is limited by the aspect ratio of the gap. In some cases, without using alumina, a diffusion barrier  105  with a maximum allowable thickness may not be enough to prevent the diffusion of dopant from doped glass layer to surface structures  104  and  106  and substrate  102 . Thus, in these cases, including alumina layer  110  as a part of diffusion barrier  105  provides enough protection while staying within the maximum allowable thickness. In some embodiments, including alumina layer  110  as a part of diffusion barrier  105  increases the “width” remaining in gap  108  after the formation of diffusion barrier  105 , thereby allowing more room for the formations of other elements in the gap. 
   Alumina layer  110  and insulating layer  120  prevent dopant such as boron and phosphorous from doped glass layer  130  to diffuse to surface structures  104  and  106  and substrate  102 . 
   In some processes during the formation of device  100 , a hydrogen atom bonds with a silicon atom at interface  107  between surface structure  104  and substrate  102  and at interface  109  between surface structure  106  and substrate  104 . This hydrogen and silicon bond provides a certain electrical property at interfaces  107  and  109 . Other processes during the formation of device  100  may break the hydrogen and silicon bond and replace the hydrogen atom with another atom. The new atom may change the electrical property at interfaces  107  and  109  and may degrade the operation of device  100  over time. Alumina layer  110  reduces replacement of the hydrogen atom by another atom at the hydrogen and silicon bond, to maintain the electrical property at the interfaces. 
   In some embodiments, heavy water D 2 O (deuterium oxide) instead of regular water H 2 O used in the deposition of alumina layer  110  provides a source of deuterium near interfaces  107  and  109 . The source of deuterium near interfaces  107  and  109  maintains the electrical property at these interfaces. 
     FIG. 1B  is a cross-section of a semiconductor device according to another embodiment of the invention. Semiconductor device  180  includes elements similar to the elements of semiconductor device  100  ( FIG. 1A ). In  FIG. 1B , diffusion barrier  105  further includes another insulating layer  182 , in which alumina layer  120  is sandwiched between insulating layers  120  and  182 . 
     FIGS. 2-5  are cross-sections of the semiconductor device of  FIG. 1A  during various processing stages according to embodiments of the invention. In  FIG. 2 , surface structures  104  and  106  are formed on substrate  102  after some preliminary processes using known techniques. At this point structures (not shown) in the substrate are also formed. For examples, surface structures  104  and  106  of  FIG. 2  can be gate structures of transistors and substrate at this point includes source and drain regions. 
   In  FIG. 3 , alumina layer  110  with a thickness in the range of about 20 to about 200 Angstroms is formed over surface structure  104  and  106  and substrate  102 . An insulating layer  120  with a thickness in the range of about 20 to about 200 Angstroms is formed over alumina layer  110 . Alumina layer  110  and insulating layer  120  form diffusion barrier  105 . In embodiments represented by  FIG. 3 , insulating layer  120  is formed over alumina layer  110 . In some embodiments, insulating layer  120  can be formed under alumina layer  110 . In other embodiments, insulating layer  120  is omitted. 
   In  FIG. 4 , doped glass layer  130  is formed on insulating layer  120 . Layers  110 ,  120 , and  130  can be formed using a known technique such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition, or furnace deposition. 
   In  FIG. 5 , after a planarization process using a known technique is performed, the top surface of doped glass layer  130  is planarized, doped glass layer  130  has a final thickness T 4  of about 3000 to about 12000 Angstroms. The planarization process can include an optional heat treatment step to reflow doped glass layer  130  to achieve a rough planarization. A final step of the planarization process can be done by a conventional chemical mechanical polishing (CMP) process. 
   In  FIG. 6 , after the planarization process, a self aligned contact formation is performed using known etching techniques to form self aligned contacts  160 . Contact structure  150  is subsequently formed in self aligned contacts  160  using a known technique. During an etching process to form self aligned contacts  160 , since diffusion barrier  105  includes alumina layer  110 , the etching process can be done selectively to both insulating layer  120  and alumina layer  110  with a final controlled punch etch. This increases the margin for uniformity of the main etching process. Other processes such as metal contact formation (not shown) can be done to complete device  100 . 
     FIG. 7A  is a cross-section of a portion of a memory device according to an embodiment of the invention. Memory device  700  includes a substrate  702 , and many gate structures  704 . 1  through  704 . 4  formed over substrate  702 . A number of diffusion regions  706 . 1  through  706 . 3  are formed in substrate  702 . A number of isolation structures  707 . 1  and  707 . 2  are formed near diffusion region  706 . 1  at region  711 , and near diffusion region  706 . 3  at region  713 . Isolation structures  707 . 1  and  707 . 2  have side walls  715 . In some embodiments, isolation structures  707 . 1  and  707 . 2  are shallow trench isolation (STI) structures. Gate structure  704 . 2  is formed above a channel region  721  between diffusion regions  706 . 1  and  706 . 2 . Gate structure  704 . 3  is formed above a channel region  723  between diffusion regions  706 . 2  and  706 . 3 . 
   Gate structures  704 . 2 - 704 . 3  and diffusion regions  706 . 1 - 706 . 3  form a number of memory cells such as CELL 1  and CELL 2 . Each memory cell includes an access transistor and a storage capacitor. For example, in memory cell CELL 1 , gate structure  704 . 2  and diffusion regions  706 . 1  and  706 . 2 . form an access transistor. Diffusion region  706 . 1 , shared by the access transistor, forms one plate (storage node) of the storage capacitor. For simplicity,  FIG. 7A  omits the other plate (cell plate or plate electrode) of the storage capacitor and other structures of memory device  700 . 
   In embodiments represented by  FIG. 7 , substrate  702  includes silicon doped with a dopant, for example boron, to make it a P-type material. Diffusion regions  706 . 1 - 706 . 3  are doped with a dopant, for example phosphorous, to make them an N-type material. In some embodiments, substrate  702  can be an N-type material and diffusion regions  706 . 1 - 706 . 3  can be P-type material. 
   The N-type material has excess electrons as majority carriers for conducting current. The P-type material has excess holes as majority carriers for conducting current. In the description, the term “diffusion region” refers to a region having a semiconductor material doped with a dopant to become either an N-type material or a P-type material. 
   Each of the gate structures  704 . 1 - 704 - 4  includes a gate dielectric (gate oxide)  709  formed on substrate  702 , a doped polysilicon layer  712 , a suicide layer  714 , a capping dielectric layer  716 , and dielectric spacers  718 . Silicide layer  714  can include a compound of metal and silicon such as titanium silicide, tungsten silicide, and others. All the dielectrics can include material such as silicon oxide. Each of the gate structures  704 . 1 - 704 . 3  is also referred to as a word line. Between two adjacent gate structures is a gap  708 . 
   Memory device  700  also includes a diffusion barrier  705  and a doped glass layer  730 , all formed over gate structures  704 . 1 - 704 . 4  and substrate  702 . Diffusion barrier  705  includes an alumina layer  710  and an insulating layer  720 . Insulating layer  720  can include silicon nitride (Si 2 N 3 ), silicon dioxide (SiO 2 ), or other insulating materials. Alumina layer  710  has a thickness T 5 . In some embodiments, T 5  is in the range of about 20 to about 200 Angstroms. Insulating layer  720  has a thickness T 6 . In some embodiments, T 6  is in the range of about 20 to about 200 Angstroms. In other embodiments, diffusion barrier  705  has a thickness T 7  in the range of about 20 Angstroms to about 400 Angstroms. Doped glass layer  730  can be a silicate glass doped with one or more dopants such as boron and phosphorous, or other type of doped glass. For example, doped glass layer  730  can be Boronsilicate glass (BSG), or Phosphosilicate glass (PSG). In  FIG. 7 , doped glass layer  730  includes Borophosphosilicate glass (BPSG) and has a thickness T 8 . In some embodiments, T 8  is about 3000 Angstroms. In other embodiments, T 8  is in the range of 2000 to 5000 Angstroms. 
   In embodiments represented by  FIG. 7A , insulating layer  720  is formed over alumina layer  710 . In some embodiments, insulating layer  120  can be formed under alumina layer  710 . In other embodiments, insulating layer  720  is omitted. 
   Memory device  700  further includes a number of self aligned contacts  740 . 1  through  740 . 3  extending through doped glass layer  730  and diffusion barrier  705 . Contact structures  750 . 1  through  750 . 3  are formed in self aligned contacts  740 . 1 - 740 . 3  to provide electrical connections to diffusion regions  706 . 1 - 706 . 3 . Metal line structures  760 . 1  through  760 . 3  are formed over doped glass layer  730  and are connected to respective contact structures  750 . 1 - 750 . 3 . In some embodiments, metal line structure  760 . 1  is a bit line of memory device  700 , and metal line structures  760 . 2  and  760 . 3  connect to a common cell plate of the capacitors of memory device  700 .  FIG. 7A  omits the cell plate or clarity. 
   Alumina layer  710  provides advantages similar to that of alumina layer  110  described in  FIG. 1 . For example, alumina layer  710  allows more width (opening) left in gap  708  after the formation of diffusion barrier  705 , provides a barrier and a source for hydrogen at the interface between gate dielectric  709  and substrate  702 , and other advantages which will become apparent in the subsequent description. 
     FIG. 7B  is a cross-section of a portion of a memory device according to another embodiment of the invention. Memory device  780  includes elements similar to the elements of memory device  700  ( FIG. 7A ). In  FIG. 7B , diffusion barrier  705  further includes another insulating layer  782 , in which alumina layer  720  is sandwiched between insulating layers  720  and  782 . 
     FIGS. 8-14  are cross-sections of the portion of the memory device of  FIG. 7A  during various processing stages according to embodiments of the invention. In  FIG. 8 , gate structures  704 . 1 - 704 . 4 , diffusion regions  706 . 1 - 706 . 3 , and isolation structures  707 . 1  and  707 . 2  are formed on substrate  702  after some initial processes using known techniques. 
   In  FIG. 9 , a blanket alumina layer  710  with a thickness in the range of about 20 to about 200 Angstroms is formed over gate structures  704 . 1 - 704 . 4  and substrate  702  using a known technique such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition, or furnace deposition. In some embodiments, heavy water D 2 O (deuterium oxide) is used during the formation of alumina layer  710 . 
   In  FIG. 10 , insulating layer  720  with a thickness in the range of about 20 to about 200 Angstroms is formed on alumina layer  710  using a known technique. Alumina layer  710  and insulating layer  720  form diffusion barrier  705 . In embodiments represented by  FIG. 10 , insulating layer  720  is formed over alumina layer  710 . In some embodiments, insulating layer  720  can be formed under alumina layer  710 . In other embodiments, insulating layer  720  is omitted. 
   In some embodiments, the total thickness of alumina layer  710  and insulating layer  720  is about 20 Angstroms to about 400 Angstroms. In other embodiments, the total thickness of alumina layer  710  and insulating layer  720  is less than 250 Angstroms. Some conventional diffusion barriers have a thickness of about 250 Angstroms. Thus, in embodiments, the total thickness of less than 250 Angstroms (instead of 250 Angstroms) allows more opening (width) left in gap  708  after the formation of alumina layer  710  and insulating layer  720 . This enhances subsequent contact structure formation in gap  708  for purposes such as self aligned contact formation. 
   In  FIG. 11 , doped glass layer  730  is formed on insulating layer  720  using a known technique. 
   In  FIG. 12 , after a planarization process is performed using a known technique, the top surface of doped glass layer  730  is planarized, doped glass layer  730  has a final thickness of about 2000 to about 5000. The planarization process can include an optional heat treatment step to reflow doped glass layer  730  to achieve a rough planarization. A final step of the planarization process can be done by a conventional chemical mechanical polishing (CMP) process. 
   In  FIG. 13 , after the planarization process, self aligned contact formation using a known technique is performed to form self aligned contacts  740 . 1 - 740 . 3 . The self aligned contact formation begins with deposition of masking material  1302 . Subsequent etching forms self aligned contacts  740 . 1 - 740 . 3  extending through doped glass layer  730  and diffusion barrier  705  to diffusion regions  706 . 1 - 706 . 3 . 
   Since diffusion barrier  705  includes alumina layer  710 , the etching process can be done selectively to both insulating layer  720  and alumina layer  710  with a final controlled punch etch. This increases the uniformity of the main etching process. Further, in some embodiments, some portions of isolation structures  707 . 1  and  707 . 2  at side walls  715  in regions  711  and  713  may overlap the openings of self aligned contacts  740 . 1  and  740 . 3 . In these embodiments, the etching process may expose side walls  715 , leading to a parasitic diode in regions  711  and  713 . This increases the leakage of the adjacent storage nodes (diffusion regions  706 . 1  and  706 . 3 ) in regions  711  and  713 , thereby reducing the retention time of the memory cells. With alumina layer  710  being used as a diffusion barrier, selective etching can be done to the alumina layer to reduce the exposure of the side walls  715  of isolation structures  707 . 1  and  707 . 2 , thereby decreasing the leakage to maintain the retention time. 
   In addition, the presence of deuterium in alumina layer  710  may passivate defects in gate dielectrics  709  and STI structures  707 . 1  and  707 . 2 . The presence of deuterium in alumina layer  710  may also allow formation of silicon-deuterium type of bonds, leading to better retention time. 
   In  FIG. 14 , contact structures  750 . 1 - 750 . 3  are formed in self aligned contacts  740 . 1 - 740 . 3  using a known technique. In  FIG. 15 , metal line structures  760 . 1 - 760 . 3  are formed over doped glass layer  730  and are respectively connected to contact structures  750 . 1 - 750 . 3  to provide electrical connections to the underlying structures. 
     FIG. 16  shows a memory device according to an embodiment of the invention. Memory device  1600  includes a memory array  1601  having plurality of memory cells  1602  arranged in rows and columns along with word lines WL and bit lines BL. Row and column decoders  1604  and  1606  provide access to memory cells  1602  in response to address signals A 0 -AX on address lines (or address bus)  1608 . A data input circuit  1616  and data output circuit  1617  transfer data between memory cells  1602  and data lines (or data bus)  1610 . Data lines  1610  carry data signals DQ 0 -DQN. A memory controller  1618  controls the operations of memory device  1600  based on control signals on control input lines  1620 . Examples of control signals include a clock signal CLK, a row access strobe signal RAS*, a column access strobe CAS* signal, and a write enable signal WE*. Memory device  1600  is an integrated circuit and includes other circuit elements. For simplicity, the other circuit element are omitted from  FIG. 16 . 
   Memory device  1600  includes embodiments of device  100  ( FIG. 1 ) and device  700  ( FIG. 7 ). Thus, memory device  1600  has diffusion barriers such as diffusion barriers  105  and  705  with alumina layers  110  and  710  formed under doped glass layers such as doped glass layers  130  and  730 . 
     FIG. 17  shows a system according to an embodiment of the invention. System  1700  includes a first integrated circuit (IC)  1702  and a second IC  1704 . ICs  1702  and  1704  can include processors, controllers, memory devices, application specific integrated circuits, and other types of integrated circuits. In embodiments represented by  FIG. 17 , for example, IC  1702  represents a processor, and IC  1702  represents a memory device. Processor  1702  and memory device  1704  communicate using address signals on lines  1708 , data signals on lines  1710 , and control signals on lines  1720 . 
   Memory device  1704  can be memory device  1600  of  FIG. 16 . Thus, memory device  1704  has diffusion barriers such as diffusion barriers  105  and  705  with alumina layers  110  and  710  formed under doped glass layers such as doped glass layers  130  and  730 . 
   System  1700  represented by  FIG. 17  includes computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like. 
   CONCLUSION 
   Various embodiments of the invention provides structures and methods for an improved dopant barrier for doped glass. Although specific embodiments are described herein, those skilled in the art recognize that other embodiments may be substituted for the specific embodiments shown to achieve the same purpose. This application covers any adaptations or variations of the present invention. Therefore, the present invention is limited only by the claims and all available equivalents.