Abstract:
A method of etching a dielectric layer by a conductive mask includes providing the dielectric layer on a substrate, forming a pattern conductive mask on the dielectric layer, the pattern conductive mask contacting with the substrate, processing a dry etching on the dielectric layer by the pattern conductive mask. Because the conductive mask disperses a lot of electric charges, the electric charges are not able to be stored on the dry etched dielectric layer, and the multilevel interconnects and the elements under the dielectric layer will not burst.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an etching process with a conductive mask, more particular to, an etching process using a conductive mask to disperse electric charges caused from the dry etching process. 
   2. Description of the Prior Art 
   The semiconductor manufacture is more precise makes the integrated circuit has a revolution. The function and memory of the computer advance soon, and the peripheral industry develops, too. The semiconductor industry just likes Mor law forecasts the number of the transistor on the integrated circuit becomes double in eighteen months. So, the manufacture is more precise. The window process of the semiconductor was 0.18 mm in 1999, 0.13 mm in 2001, 90 nm in 2003 (0.09 mm), and now is 65 nm in 2005 (0.065 mm). 
   The contact plug and via plug always are the important technology in the semiconductor manufacture. The contact plug and via plug are able to electrically connect with the transistor, capacitor, the multilevel interconnects to form the whole integrated circuit. Except tungsten (W) and aluminum (Al) alloy can be the material of the contact plug and the via plug, the cooper process is a choice, too. When copper is the material of the multilevel interconnects, the via plug and the copper line need to be complete by the single damascene or the dual damascene, because copper can&#39;t be etched easily. But, the dry etching process of the contact hole, the via hole, or the trench causes a lot of electric charges on the dielectric layer. When the metal layer or the components almost are etched or already are etched, the metal layer under the dielectric layer or the components will burst, that causes the yield decreases. 
   Please refer to  FIG. 1 .  FIG. 1  is a diagram of a metal layer bursts caused by an etching process in the prior art. As  FIG. 1  shows, a semiconductor wafer  100  comprises a NMOS and a PMOS individually on the P well  102  and N well  104  of the P semiconductor substrate  101 . A STI (shallow trench isolation)  106  surrounds NMOS and PMOS to divide each NMOS and PMOS. Each PMOS and NMOS comprises a gate  108 ,  109 , and source/drain  110 ,  111  on the P well  102  and N well  104 . 
   Then, a contact etch stop layer (CESL)  113 , an undoped silica glass (USG)  112 , and a phosphorus-doped silica glass (PSG)  114  are doped on P semiconductor substrate  101  and cover the gate  108 ,  109 , source/drain  110 ,  111 , STI  106 , P well  102 , and N well  104 . For the multilevel interconnects electrically connect with the NMOS, PMOS, and other components, a contact plug  116  is formed by the lithograph process, the etching process, the doping process, and CMP. The one end of contact plug  116  contacts with the gate  108 , or with the source/drain  110 . The other end contacts with a metal layer  118 . The metal layer  118  is patterned and is doped a dielectric layer  120 . The dielectric layer  120  could comprise an HDP oxide  119  is formed by HDPCVD, a PE oxide  121  is formed by PECVD on the dielectric layer, and an cap oxide  123  on the an PB oxide  121 , as the individual manufacture demands. 
   As  FIG. 1  shows, a photoresist  122  is added on the dielectric layer  120 , after PEP, the pattern photoresist  122  is produced, the dry etching process is performed to form a via hole  124  in the dielectric layer  120 . In recently technology, the plasma dry etching process always applies with the via hole etching process. But, the dry etching process causes a lot of charges, and the charges store in the dielectric layer  120 . So, when the via hole etching process almost or already etches till the metal layer  118  surface, the stored charges will lead off, and will cause the metal layer  118  to form a burst  125 . Furthermore, the gate  108  or others component will burst. 
   So, how to avoid the via hole dry etching process is to induce the metal burst, which is an important issue in this domain. 
   SUMMARY OF THE INVENTION 
   The present invention relates to a method of an etching process with a conductive mask to solve the above-mentioned problem. 
   The present invention discloses a method of etching a dielectric layer comprising providing the dielectric layer on a substrate, forming a pattern conductive mask on the dielectric layer, the pattern conductive mask contacting with the substrate, processing a dry etching process on the dielectric layer by the pattern conductive mask. 
   The embodiment of the present invention is a method of forming a contact hole comprising providing a substrate, at least a component on the substrate, forming a dielectric layer on the component and the substrate, forming a conductive mask on the dielectric layer, the conductive mask contacting with the substrate, and processing an etching process with the conductive mask to etch a contact hole in the dielectric layer till the component surface. 
   The other embodiment of the present invention is a method of forming a via hole comprising providing a substrate, a first dielectric layer on the substrate, at least one multilevel interconnect layer, forming a second dielectric layer on the multilevel interconnects layer and the first dielectric layer, forming a pattern conductive mask on the second dielectric layer, the pattern conductive mask contacting with the substrate, and processing an etching process by the conductive mask to etch at least a via hole in the second dielectric layer till the multilevel interconnects layer surface. 
   The other embodiment of the present invention is a damascene method comprising providing a substrate, at least one conductive line on the substrate, forming a dielectric layer on the conductive line, forming a pattern conductive mask on the dielectric layer, the pattern conductive mask contacting with the substrate, processing an etching process by the pattern conductive mask to form at least one opening in the dielectric layer till the conductive line surface, and filling a copper into the opening. 
   The present invention uses the conductive mask to disperse the charges from the dry etching process into the big area conductive mask and to transmit the charges to the substrate. So, the charges will not be stored in the etched domain of the dielectric layer, the metal of the multilevel interconnects and the components will not burst, and the yield of the wafer will increases. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram of a metal layer bursts causes by an etching process in the prior art. 
       FIG. 2  is a diagram of the present invention applies with a contact hole etching process. 
       FIG. 3  is a diagram of the via hole etching process in the present invention. 
       FIG. 4  is a diagram of via hole etching process of the other embodiment of the present invention. 
       FIG. 5  is a diagram of the dual damascene process in the present invention. 
   

   DETAILED DESCRIPTION 
   Please refer to  FIG. 2 .  FIG. 2  is a diagram of the present invention applies with a contact hole etching process. A semiconductor wafer  200  comprises a NMOS and a PMOS individually on the P well  202  and N well  204  of the P semiconductor substrate  201 . A STI  206  surrounds NMOS and PMOS to divide each NMOS and PMOS. Each PMOS and NMOS comprises a gate  208 ,  209 , and source/drain  210 ,  211  on the P well  202  and N well  204 . 
   Then, a contact etch stop layer (CESL)  213 , an undoped silica glass (USG)  212 , and a phosphorus-doped silica glass (PSG)  214  are doped on the P semiconductor substrate  201 , and are covered the gate  208 ,  209 , source/drain  210 ,  211 , STI  206 , P well  202 , and N well  204 . Next, a lithography process and a photo-lithography process are processed to form a pattern conductive mask  215  over PSG  214 . The pattern conductive mask  215  is covered the edge of the semiconductor wafer  200  to contact with the P semiconductor substrate  201 . Then, a contact hole  217  dry etching process is processed. 
   It is deserved to be mentioned, the conductive mask  215  is made by the conductive photoresist in this embodiment. The conductive mask is made by the conductive resin, the solvent, and sensitizer. For example, the conductive resin could be a 3-hexyl-thiophene-3thiophene-ethane-methacylate copolymer. The solvent could be an aceto-nitrile solution of gold chloride. The sensitizer could be gold chloride. Of course, the material of the conductive photoresist is not limit in the above materials, it depends on the manufacture process. An anti reflect coating (ARC) is formed on the PSG  214 , then, the conductive mask  215  is formed. That can improve the photo-lithography process, and get better conductive mask  215  pattern. Furthermore, the pattern conductive mask  215  can be covered whole edge of the semiconductor wafer  200  or partial edge of the semiconductor wafer  200 . No matter the pattern conductive mask  215  is covered whole edge or partial edge of the semiconductor wafer  200 , the pattern conductive mask  215  can transmit the contact hole  217  dry etching process charges to the P semiconductor substrate  201 . 
   The present invention could apply with the via hole etching process. Please refer to  FIG. 3 .  FIG. 3  is a diagram of the via hole etching process in the present invention. It continues the semiconductor manufacture process of  FIG. 2 . When the contact hole  217  etching is completed, then, the conductive mask  215  is removed, a wash process is processed. That causes the contact hole  217  is formed in the USG  212  and PSG  214  till the gate  208 ,  209  surface or the source/drain  210 ,  211  surface. Next, metal Ta, TaN, or W is doped, and CMP is taken to form a contact plug  216 . Then, doping process, lithograph process, and etching process are achieved to from an Al—Cu alloy pattern of the metal layer  218 . The one end of the contact plug  216  contacts with the gate  208 , or contact with the ion doped area, like source/drain  210 . The other end contacts with the pattern metal layer  218  to form a multilevel interconnects layer. Then, doping a compound dielectric layer  220  depends on the demands. The dielectric layer  220  comprises a HDP oxide  219  is formed by a high density plasma doped process, an PE oxide  221  is formed by PECVD, and an cap oxide  223 . Finally, the present invention forms a pattern conductive mask  222  on the dielectric layer  220 . The pattern conductive mask  222  is covered the edge of the semiconductor wafer  200  to contact with the P semiconductor substrate  201 . The via hole  224  dry etching process is processed to form the via hole  224  till the corresponding pattern metal layer  218  surface. 
   In the embodiment, the conductive mask  222  is a conductive photoresist. And, an anti reflect coating (ARC) is formed on the dielectric  220  depends the demands, then, the conductive mask  222  is formed. That can improve the photo-lithography process, and get better conductive mask  222  pattern. The pattern conductive mask  222  can be covered whole edge of the semiconductor wafer  200  or partial edge of the semiconductor wafer  200  to transmit the via hole  224  dry etching process charges to the P semiconductor substrate  201 . 
   It deserves to be mentioned that the conductive mask  215 ,  222  in the present invention not only could be made by the conductive photoresist, but also could be made by a structure of a photoresist covers a metal layer. For example, please refer to  FIG. 4 .  FIG. 4  is a diagram of via hole etching process of the other embodiment of the present invention. As  FIG. 4  shows, the dielectric layer  220  is doped, dopes the structure of a pattern photoresist  227  covers a metal layer  225  to define the via hole  224  on the dielectric layer  220 . The structure of a pattern photoresist  227  covers a metal layer  225  could be the pattern conductive mask  222 . And the structure of a pattern photoresist  227  covers a metal layer  225  is covered the edge of the semiconductor wafer  200  to contact with the P semiconductor substrate  201 . The pattern photoresist  227  is an etching mask for etching the metal layer  225  and the dielectric layer  220  to form each via hole  224 . Or uses two-step pattern transfer process, the pattern photoresist  227  is an etching mask to etch the metal layer  225  to transfer the pattern of the photoresist  227  to the metal layer  225 . Then, removes the photoresist  227 . And the pattern metal layer  225  is an etching mask for the via hole  224  dry etching process. 
   In the present invention, the pattern conductive mask  215 ,  222  are the etching mask for the contact hole  217 , the via hole  224  or the trench of the single damascene opening. The charges formed by the plasma dry etching process could disperse uniformly on the conductive mask  215 ,  222 , not be stored on the PSG  214 , USG  212 , CESL  213 , and the dielectric layer  220 . And the pattern conductive mask  215 ,  222  are contacted with the P semiconductor substrate  201 , so the dry etching process charges can transmit to the P semiconductor substrate  201 . Because the charges are not be stored in the partial area in the dielectric layer. When it etches till or almost till the metal layer and the elements under the dielectric layer, the metal layer and the elements will not burst, not like the prior art. Otherwise, the structure of the photoresist covers the metal mask could select special metal material for providing for other functions. For example, the conductive mask  222  is made by the TiN or TaN. That could avoid the metal burst, and could increase defect and particle inspect rate of the dielectric layer  220  measure line for KLA-Tencor AIT type wafer (for example, residues and micro scratch). And, it could be the via hole  224  plug CMP stop layer, and be removed in the metal plug CMP process. 
   Besides, the present invention could apply with the single damascene or dual damascene of the copper process to from the copper via plug and the copper line. Please refer to  FIG. 5 .  FIG. 5  is a diagram of the dual damascene process in the present invention. A transistor  300  comprises a substrate  301 , a dielectric layer  302 , at least one conductive structure like a metal plug or a metal pattern, a conductive line  304  etc. in the dielectric layer  302 . A dielectric layer  306 , a pattern dielectric layer  308  are doped on the dielectric layer  302  and the conductive line  304 . The pattern dielectric layer  308  could be a PE oxide made by PECVD. A plurality of opening  310  is made by PEP with a photoresist layer (not shown) to define the copper line of the multilevel interconnects. Then, the dielectric layer  306 ,  308  is covered a pattern conductive mask  314 , and the pattern conductive mask  314  is covered the edge of the semiconductor wafer  300  to contact with the substrate  301 . The pattern conductive mask  314  has at least one opening  316  to define the copper via plug of the multilevel interconnects. After dry etching process, a via hole (not shown) is made on the dielectric layer  306 . Then, removes the pattern conductive mask  314 , and uses the pattern dielectric layer  308  to etch, the trench (not shown) could be made in the dielectric layer  306 . Finally, forms a copper via plug and a copper line in the opening of the dual damascene in the same time. And the trench first, via first, and no etching stop layer of the dual damascene are similar. The trench mask and the via mask could be used the conductive mask of the present invention to define the pattern and no metal burst problem. It needn&#39;t be mentioned. 
   Because the material of the conductive mask  314  could be the conductive photoresist on the dielectric layer  306 ,  308  for big area cover, and the conductive mask  314  is contacted with the substrate  301 . When the dry etch process is processed, the charges will not be stored in the etched dielectric layer  306 ,  308 , but be dispersed in big area conductive photoresist and be transmitted to the substrate  301 . When it etches till or almost till the conductive line  304 , the metal will not burst. 
   Of course, as the above-mentioned, in the embodiment, the conductive mask  314  could be a structure of a photoresist covers a metal layer. That means after the opening  310  is made, the metal layer and the photoresist for being the conductive mask. Patterns the metal layer and the photoresist, the via hole dry etching process is processed. Of course, the photoresist could chosen to be removed or stayed before via hole dry etching process. 
   The present invention also could apply with the single damascene. That means the via hole or the trench opening is made by PEP with the conductive mask, then, the opening of the metal layer in the dielectric is made by PEP with the conductive mask, the copper is doped to form the copper plug or the copper line. Because the charges contact with the big area conductive mask, the charges will not be stored, when etches till the dielectric layer, the metal will not burst. 
   In the prior art, the charges will be stored, when etches the dielectric layer till the metal plug, the conductive line, the ion doped area or the gate components, the metal will burst, the gate dielectric layer will breakdown, the quality and the yield decrease. And the product number decreases serious. The present invention uses the conductive mask, the charges disperse in the big area conductive mask and are transmitted to the substrate, not store in the etched area of the dielectric layer, the metal of the multilevel interconnects and the component will not burst. The wafer yield increases. The conductive mask could be made the conductive photoresist to avoid the metal burst. The present invention could use the structure of the photoresist layer covers the metal layer, and a special metal material for the metal layer. It could increase defect and particle inspect rate of the dielectric layer measure line for KLA-Tencor AIT type wafer (for example, residues and micro scratch). And, it could be the via hole plug CMP stop layer, and be removed in the metal plug CMP process to simply the manufacture and decrease the cost. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.