Abstract:
Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a solid state drive (SSD) tester, and more particularly to an SSD tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. 
         [0003]    2. Description of the Related Art 
         [0004]    Until now, hard disk drives (HDDs) have been most generally known and used as large capacity digital media storage devices. However, in recent years, as prices of NAND flash semiconductor devices, which can store the largest capacity among semiconductor devices having a memory function and data stored therein are not erased even when electric power is not supplied, are being lowered, large capacity digital medial storage apparatus such as solid state drives (SSDs) using a semiconductor having a memory function are newly appearing. 
         [0005]    Writing and reading speeds of such an SSD are 3 to 5 times as fast as those of existing hard disks, and its performance of reading/writing a random address required by a database management system is several hundreds of times as excellent as those of existing hard disks. In addition, an SSD is operated in a silent way, so a noise problem of an existing hard disk can be solved. Further, since the SSD is operated with power consumption significantly lower than that of a hard disk, the SSD is known as to most suitable for a digital device, such as a laptop computer, which requires low power consumption. 
         [0006]    In addition, the SSD has a higher durability against an external impact than an existing hard disk, and as the SSD can be manufactured to be smaller and more various in shape as compared with a hard disk having a fixed form in terms of an external design, an external shape of an electronic product employing the SSD can be made smaller, showing many excellent advantages in its applications. 
         [0007]    Due to its advantages, it is expected that distributions of SSDs can be expanded rapidly to searches, home shopping, storage media of video service servers, storage media for storing various R&amp;D materials, and special equipment, as well as existing desktop computers or laptop computers. 
         [0008]    As a scheme of testing the above-described SSD, an SSD tester according to the related art is illustrated in  FIG. 1 . 
         [0009]    The SSD tester according to the related art shown in  FIG. 1  includes a host terminal  10 , a network  20 , a communication interface unit  30 , a memory  40 , a micro processor  50 , a storage interface unit  60 , and a storage unit  70 . The storage interface unit  60  includes a plurality of storage interfaces  61 ˜ 60 +n. The storage unit  70  includes a plurality of storages  71 ˜ 70 +N, and respective storage interfaces perform the same function. Each unit in the above described SSD tester according to the related art is provided as a separate device. 
         [0010]    The network  20  maintains a wired/wireless network connection with the host terminal  10 . The network  20  may be network-connected to the host terminal  10  through wired communication such as LAN, USB, or RS-232, and wireless local area communication such as Bluetooth, Zigbee, or UWB. 
         [0011]    A user inputs a test condition through the host terminal  10 . The input test condition, which is received through the network  20 , is transferred to the micro processor  50  through the communication interface unit  30  of a next stage. 
         [0012]    The micro processor  50  generates a test pattern for testing the storage  70  in connection with the memory  40  according to the transferred test condition. The test pattern may be implemented as various types of test patterns which are widely used for testing an SSD and various types of storages. In addition, the micro processor performs a function of generating Frame Information Structure (FIS) data. 
         [0013]    The micro processor  50  controls test of the storage  70  using the generated test pattern. For example, the micro processor  50  generates a test signal based on the test pattern and transmits the test signal to the storage  70  through the storage interface unit  60  so that test of the storage  70  may be controlled. The test control includes storing the test pattern generated for the test in the storage  70 , reading out the test pattern from the storage  70 , and comparing the stored test pattern (expectation data) with the read test pattern (readout data) to process a fail. 
         [0014]    As well known in the related art, the micro processor  50  performs all functions related to the test, such as a function of generating the test pattern for testing the SSD, a function of generating the FIS data, a function of storing the test pattern in the storage  70 , a function of reading out data from the storage  70 , a function of comparing the stored data with the read data to determine whether a fail occurs. 
         [0015]    The storage interface unit  60  maintains interface with the storage  70 . The storage interface unit  60  performs Serial-ATA (SATA) interface with the storage  70 . 
         [0016]    However, in the related art as illustrated above, since the micro processor  50  completely performs all functions related to the SSD test, such as a function of generating the test pattern for testing the SSD, a function of generating the FIS data, a function of storing the test pattern in the storage  70 , a function of reading out data from the storage  70 , a function of comparing the stored data with the read data to determine whether a fail occurs, load of the micro processor is weighted so that a real-time test is impossible. 
         [0017]    Specifically, as described above, since one micro processor completely performs entire functions for the SSD test, the real-time test is impossible, so since when plural SSDs are tested, the SSDs must be sequentially tested, the micro processor requires much time to test all SSDs. 
       SUMMARY OF THE INVENTION 
       [0018]    Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide an SSD tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. 
         [0019]    It is another object of the present invention to provide an SSD tester capable of randomly generating various pattern data. 
         [0020]    According to an aspect of the present invention, there is provided a solid state drive tester which includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time. 
         [0021]    The test control unit includes: an embedded processor for controlling the test of the storage; and a test executing unit for generating a test pattern to test the storage, transmitting the test pattern to the storage, and determining whether a fail occurs by comparing the test pattern with a test pattern read out from the storage in cooperation with the embedded processor. 
         [0022]    The test control unit includes: a communication interface unit connected with the host terminal through a network to receive information of the user and to transmit a test result to the host terminal; and a storage interface unit for interfacing the storage. 
         [0023]    The test executing unit includes: a pattern data generator for generating pattern data by selecting one of pattern data generated corresponding to the test condition and random pattern data according to a pattern selection signal generated from the embedded processor; a fail processor for comparing the pattern data generated from the pattern data generator with test result data read out from the storage to determine whether the fail occurs and to generate fail information when the fail occurs; a fail memory for storing the fail information generated from the fail processor; and an instruction generator for transmitting a test instruction generated from the embedded processor to the storage interface unit. 
         [0024]    The pattern data generator includes: a pattern data memory for storing the pattern data generated according to the test condition; a pattern data creating unit for randomly generating the pattern data to output the pattern data as the random pattern data; and a multiplexer for outputting the pattern data by selecting one of the pattern data output from the pattern data memory and the pattern data output from the pattern data creating unit according to the pattern data selection signal output from the embedded processor. 
         [0025]    The pattern data creating unit includes a plurality of pattern data generators for randomly generating the pattern data. 
         [0026]    The fail processor includes: a comparing unit for comparing writing data generated from the pattern data generator with reading data read out from the storage to generate a fail signal when the writing data are not equal to the reading data; a fail counter for counting a number of the fail signals generated from the comparing unit to output a fail count value; and a fail memory address generator for generating a storage address to store the fail signal when the fail signal is generated from the comparing unit. 
         [0027]    The storage interface unit includes a plurality of multi-interfaces to simultaneously test a plurality of the storages, and the multi-interfaces comprise a plurality of interfaces corresponding to the interfaces of the storage, and interface with the storage by selecting one of the interfaces according to the interface selection signal generated from the embedded processor corresponding to the storage interface. 
         [0028]    According to the present invention, the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other, which are performed by an embedded processor, are divided into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. 
         [0029]    According to the present invention, since various pattern data can be randomly generated, a user can freely use desired pattern data. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0030]    The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: 
           [0031]      FIG. 1  is a schematic block diagram of a solid state drive test device according to the related art; 
           [0032]      FIG. 2  is a block diagram illustrating a configuration of an SSD tester according to an embodiment of the present invention; 
           [0033]      FIG. 3  is a block diagram illustrating an example of a test executing unit shown in  FIG. 2 ; 
           [0034]      FIG. 4  is a block diagram illustrating an example of a pattern data generator shown in  FIG. 3 ; 
           [0035]      FIG. 5  is a block diagram illustrating an example of a storage interface unit shown in  FIG. 2 ; and 
           [0036]      FIG. 6  is a block diagram illustrating an example of a fail processor shown in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0037]    Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. A detailed description of known functions and configurations of the present invention will be omitted when it may make the subject of the present invention unclear. 
         [0038]      FIG. 2  is a block diagram illustrating a configuration of an SSD tester according to an embodiment of the present invention. The SSD tester includes a host terminal  110 , a network  120 , a test control unit  130 , and a memory  140 . In  FIG. 2 , reference numeral  200  denotes a storage unit  200  including a plurality of storages  201  to  200 +N which are test targets. 
         [0039]    The host terminal  110  functions to receive a test condition for testing a storage from the user, and the network  120  is in charge of a data interface between the host terminal  110  and the test control unit  130 . 
         [0040]    A program for testing an SSD is stored in the memory  140 , and performs the function of a data memory device for storing pattern data for generating a test pattern and data generated in an SSD test. 
         [0041]    The test control unit  130  functions to generate a test pattern according to the test condition or to randomly generate a test pattern, and adaptively selects an interface according to a storage type of the storage to be tested to test the storage with the test pattern. Preferably, a plurality of devices installed in the test control unit  130  to test the SSD is implemented as one chip by using a field programmable gate array (FPGA). 
         [0042]    Preferably, the test control unit  130  is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time. 
         [0043]    The test control unit  130  according to the related art includes a communication interface unit  131  connected to the host terminal  110  through the network  120  to receive information of the user and to transmit the test result to the host terminal  110 , a storage interface unit  132  for interfacing the storage unit  200 , an embedded processor  133  for controlling the storage test, and a test executing unit  160  in cooperation with the embedded processor  133  for generating a test pattern for testing the storage and transmitting the test pattern to the storage, and for comparing the generated test pattern with a test pattern stored in the storage to process whether a fail occurs. Further, as shown in  FIG. 3 , the test executing unit  160  includes a pattern data generator  161  for selecting one of pattern data generated corresponding to the test condition according to a pattern selection signal generated from the embedded processor  133  and random pattern data to generate pattern data, a fail processor  162  for comparing the pattern data generated from the pattern data generator  161  with test result data read out from the storage to determining whether the fail occurs, such that fail information is generated when the fail occurs, a fail memory  163  for storing the fail information generated from the fail processor  162 , and an instruction generator  164  for transmitting a test instruction generated from the embedded processor to the storage interface unit  132 . 
         [0044]    In addition, as shown in  FIG. 4 , the pattern data generator  161  includes a pattern data memory  161   a  for storing the pattern data generated according to the test condition, a pattern data creating unit  161   b  for randomly generating pattern data to output the pattern data as random pattern data, and a multiplexer  161   c  for selecting one of the pattern data output from the pattern data memory  161   a  according to a pattern data selection signal output from the embedded processor  133  and the pattern data output from the pattern data creating unit  161   b  to output the selected data as the pattern data. 
         [0045]    Further, as shown in  FIG. 6 , the fail processor  162  includes a comparing unit  162   a  for comparing writing data generated from the pattern data generator  161  with reading data read out from the storage to generate a fail signal when the writing data is not equal to the reading data, a fail counter  162   b  for counting a number of the fail signal generated from the comparing unit  162   a  to output a fail count value, and a fail memory address generator  162   c  for generating a storage address to store the fail signal when the fail signal is generated from the comparing unit  162   a.    
         [0046]    Meanwhile, the storage interface unit  132  includes a plurality of multi-interfaces  151  to  151 +N. Here, internal configurations and operations of the plurality of multi-interfaces  151  to  151 +N are the same, and thus only one multi-interface  151  will be described below for convenience&#39; sake. 
         [0047]    As illustrated in  FIG. 5 , the multi-interface  151  includes an advanced host controller interface (AHCI)  151   a  for interfacing instruction data generated in the embedded processor  133 , a direct memory access (DMA) unit  151   b  for interfacing writing data generated in the embedded processor  133 , a serial-ATA (SATA) interface  151   c  for supporting an SATA interface between the advanced host controller interface  151   a  and the storage  201  and between the direct memory access unit  151   b  and the storage  201 , a serial attached SCSI (SAS) interface  151   d  for supporting an SAS interface between the advanced host controller interface  151   a  and the storage  201  and between the direct memory access unit  151   b  and the storage  201 , a PCI express (PCIe) interface  151   e  for supporting a PCIe interface between the advanced host controller interface  151   a  and the storage  201  and between the direct memory access unit  151   b  and the storage  201 , and a multiplexer (MUX)  151   f  for selecting one of the SATA interface  151   c , the SAS interface  151   d , and the PCIe interface  151   e  according to an interface selection signal generated in the embedded processor  133  to connect the storage  201  and the embedded processor  133 . 
         [0048]    In the above-described SSD tester according to the present invention, a plurality of test devices for testing a storage are implemented as one chip on one board by using FPGA. In this state, after a user who wants to test an SSD allows the solid state drive tester to access a test target storage, the user inputs a test condition through the host terminal  110 . Here, the test condition may include an interface selection signal for interfacing the test target storage and a test pattern selection signal. The test pattern selection signal is a signal for determining whether predetermined pattern data are selected or a plurality of random patter data arbitrarily generated are selected. 
         [0049]    The test condition of the user input through the host terminal  110  is transferred to the one-chipped test control unit  130  through the network  120 . 
         [0050]    The communication interface unit  131  of the test control unit  130  receives the test condition input by the user through the network  120 , and transfers the received test condition to the embedded processor  133 . If the test condition is input by the user and a test is requested, the embedded processor  133  extracts a test program for the storage test from the memory  140  and starts to test the storage. Here, as an initial operation of the test, test pattern data corresponding to the test condition input by the user are extracted from the memory  140  and are transferred to the test executing unit  160 . 
         [0051]    The test executing unit  160  is a separate logic for a module for executing a practical test separated from the embedded processor  133 . Thus, by separating the module (generating a test pattern data and confirming a fail) for executing the test from the embedded processor  133 , the burden of the embedded processor  133  may be reduced and the control and test for plural storages are performed at the same time, so that entire test time can be reduced. 
         [0052]    In more detail, as shown in  FIG. 3 , the pattern data generator  161  of the test executing unit  160  selects one of pattern data generated corresponding to the test condition according to the pattern data selection signal output from the embedded processor  133  and random pattern data to generate the pattern data. 
         [0053]    For example, as shown in  FIG. 4 , in the pattern data generator  161 , the pattern data generated corresponding to the test condition are stored in the pattern data memory  161   a  and are output to the multiplexer  161   c . The pattern data creating unit  161   b  randomly generates the pattern data (Psuedo Random Binary Sequence: PRBS) to transfer the pattern data to the multiplexer  161   c.    
         [0054]    Preferably, the pattern data creating unit  161   b  includes a plurality of pattern data creators  161   b - 1  to  161   b - 4 . 
         [0055]    For example, the pattern data creator  161   b - 1  generates 8-bit pattern data, the pattern data creator  161   b - 2  generates 16-bit pattern data, the pattern data creator  161   b - 3  generates 24-bit pattern data, and the pattern data creator  161   b - 4  generates 32-bit pattern data. 
         [0056]    The multiplexer  161   c  selects one of the pattern data stored in the pattern data memory  161   a  and the pattern data randomly generated from the pattern data creating unit  161   b  according to the pattern data selection signal generated from the embedded processor  133  to transfer the selected data to the multi-interface  151  of the storage interface unit  132 . When plural storages are tested at the same time, the pattern data are applied to the plurality of multi-interfaces at the same time. 
         [0057]    At this time, as illustrated in  FIG. 5 , an interface selection signal is provided to the multi-interface  151  to select an interface corresponding to the storage  201 . 
         [0058]    For example, an interface selection signal is applied from the embedded processor  133  to the multiplexer  151   f  of the multi-interface  151 , the multiplexer  151   f  selects one of the interfaces SATA, SAS, and PCIe according to the applied interface selection signal. That is, an interface corresponding to the interface of the storage  201  is selected. 
         [0059]    Thereafter, instruction data output from the embedded processor  133  for the test are input to the SATA interface  151   c , the SAS interface  151   d , and the PCIe interface  151   e  through the advanced host controller interface  151   a , respectively. 
         [0060]    In addition, writing data output from the test executing unit  160  are input to the SATA interface  151   c , the SAS interface  151   d , and the PCIe interface  151   e , respectively, through the DMA unit  151   b.    
         [0061]    When the instruction data output from the embedded processor  133  and the writing data output from the test executing unit  160  are input to the respective interfaces in this way, the multiplexer  151   f  selects only one interface according to an interface selection signal. The test of the storage  201  is started by transferring the instruction data and writing data input to the selected interface to the storage  201 . For example, when the interface of the storage  201  uses the SATA interface, the SATA interface  151   c  is selected, and the instruction data and writing data input to the SATA interface  151   c  are converted into a format suitable for the SATA interface to be applied to the storage  201 . 
         [0062]    Here, since standard interfaces are employed for the SATA interface, the SAS interface, and the PCIe interface, and protocols for interfaces, a detailed description of respective interfaces is omitted. 
         [0063]    Next, after result data for testing the storage  201  are read out according to a reading instruction, they are transferred to the embedded processor  133  through the multiplexer  151   f , the SATA interface  151   c , and the DMA unit  151   b  of the multi-interface  151 . 
         [0064]    If the data obtained by reading out the storage test are transferred to the embedded processor  133 , the embedded processor  133  transmits the readout data to the test executing unit  160 . 
         [0065]    As shown in  FIG. 6 , a comparator  162   a  of the fail processor  162  compares expectation data output from the pattern data generator  161  with the readout data (reading data) transferred from the embedded processor  133 , and does not generate a fail signal if they are the same and to the contrary, generates the fail signal if they are different. 
         [0066]    According to the generated fail signal, the fail counter  162   b  increases an internal count value by 1 to output a fail count value, and a fail memory address generator  162   c  generates and transfers an address of a fail memory to the fail memory  163 . 
         [0067]    The fail memory  163  stores expectation data and reading data inputted to the fail processor  162  as fail information by using the transferred address as a logical block address (LBA). 
         [0068]    As described above, in another characteristic of the present invention, since the embedded processor  133  does not perform fail processing during testing a storage but a test executing unit  160  as a logic separated from the embedded processor  133  performs fail processing, burden of the embedded processor  133  can be reduced and accordingly an entire storage test time can be reduced by simultaneously testing the storages. 
         [0069]    Further, the fail information stored in the fail memory  163  is transferred to the embedded processor  133  upon the request of the embedded processor  133 , and is transmitted to the host terminal  110  through the communication interface unit  131  and the network  120 . 
         [0070]    Thus, the user can easily recognize the test result of the storage tested through the host terminal  110 . 
         [0071]    As described above, the present invention separates the SSD test function performed in the embedded processor as a separate logic, so that burden of the embedded processor  133  can be reduced and accordingly an entire storage test time can be reduced. 
         [0072]    The present invention designs interface of a storage using an FPGA which allows a user to easily use the interface if needed. Various interfaces are implemented by one chip using an FPGA which allows the user to selectively use interface corresponding to the interface of the storage without changing H/W. 
         [0073]    The present invention is not limited to the above-described embodiment, and may be variously modified by those skilled in the art to which the present invention pertains without departing from the spirit of the present invention and the modification falls within the scope of the present invention.