Abstract:
The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without physically changing the control device. The device for controlling a setup/hold time of an input signal has transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the device for controlling a setup/hold time of an input signal can provide a technique which can optimize the setup/hold time at a small cost in comparison with a physical metal option control system.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention generally relates to a device for controlling a setup/hold time of an input signal, and more specifically, to a technique to control the setup/hold time of various control signals applied from an input buffer without physically changing the control device. 
   2. Description of the Prior Art 
     FIG. 1  is a circuit diagram illustrating a conventional device for controlling setup/hold time of input signal. 
   The conventional device for controlling a setup/hold time of an input signal comprises inverters IV 1 ˜IV 4  for performing a driver function, MOS capacitors C 1 ˜C 4  for performing a signal delay function, metal option unit  2  and  3 , and a latch  4 . 
   Here, the inverters IV 1  and IV 2  output signals by driving an address, a command signal or input data applied from an input buffer  1 . The inverter IV 3  outputs a signal by driving an output signal of the metal option unit  2 . The inverter IV 4  drives an output signal of the metal option unit  3  to provide a global bus line control signal GB_BL to the latch  4 . 
   The metal option units  2  and  3  comprising metal option switches MO 1 ˜MO 4  selectively control the MOS capacitors C 1 ˜C 4  to control setup/hold time of the global bus line control signal GB_BL. 
   The MOS capacitors C 1  and C 2  are selectively connected to an output terminal of the inverter IV 2  by the metal option switches MO 1  and MO 2 . The MOS capacitors C 3  and C 4  are selectively connected to an output terminal of the inverter IV 3  by the metal option switches MO 3  and MO 4 . 
   The latch  4  latches the global bus line control signal GB_BL in synchronous to a clock signal CLK to output the latched signal into a global bus line (not shown). Here, in order that the global bus line control signal GB_BL inputted into the latch  4  may be valid, the global bus line control signal GB_BL should be transmitted into the latch earlier than the clock signal CLK by a predetermined time (setup time). When the latch  4  performs a latch operation in synchronous to the clock signal, a state of the global bus line control signal GB_BL should be maintained for a predetermined time (hold time). 
   Here, the ideal condition is that the clock signal CLK is enabled after the setup time of the global bus line control signal GB_BL has passed, and the state of the global bus line control signal GB_BL for the hold time has been maintained. 
   However, it is difficult to satisfy the above ideal condition because signals inputted from outside of an actual chip through the input buffer  1  are influenced by length of an internal transmission line, various noises, capacitance or resistance, and so forth. 
   Accordingly, the device for controlling a setup/hold time of an input signal is designed to control the setup/hold time of the global bus line control signal GB_BL by selectively connecting signal delay devices such as the MOS capacitors C 1 ˜C 4 . 
   In other words, the metal option switches MO 1 ˜MO 4  requiring physical apparatus are used to regulate the setup/hold time of the global bus line control signal GB_BL. As a result, since circuits of metal layers need to be physically changed to regulate the setup/hold time, the conventional device has a problem consuming a long time and a high cost. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to a device for controlling a setup/hold time of an input signal that controls a setup/hold time of various control signals applied to a global bus line according to a decoded test mode control signal. 
   There is provided a device for controlling a setup/hold time of an input signal, comprising: a driver for outputting a global bus line control signal by amplifying an output signal from an input buffer, a signal delay unit for delaying the global bus line control signalselectively connected to the driver, a decoding unit for outputting a test mode delay signal by decoding a test control signal for determining to control setup/hold time corresponding to the global bus line control signal, a test mode entry signal, and a test mode exit signal, and a delay control unit for controlling the setup/hold time of the global bus line control signal by selectively connecting the signal delay unit to the driver according to a state of the test mode delay signal. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram illustrating a conventional device for controlling a setup/hold time of an input signal. 
       FIG. 2  is a circuit diagram illustrating a device for controlling a setup/hold time of an input signal according to an embodiment of the present invention. 
       FIG. 3  is a circuit diagram illustrating a decoding unit according to an embodiment of the present invention. 
       FIG. 4  is a timing diagram illustrating operation of a device for controlling a setup/hold time of an input signal according to an embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The present invention will be described in detail referring to the accompanying drawings. 
     FIG. 2  is a circuit diagram illustrating a device for controlling a setup/hold time of an input signal according to an embodiment of the present invention. 
   Referring to  FIG. 2 , the device for controlling a setup/hold time of an input signal of the present invention comprises a driver  20 , signal delay units  30  and  40 , delay control units  50  and  60 , and a latch  70 . 
   The driver  20  comprises inverters IV 5 ˜IV 8  for outputting a global bus line control signal GB_BL into a latch  70  by driving an address, a command signal or input data applied from an input buffer  10 . Here, the inverters IV 5  and IV 6  output signals by driving an output signal of the input buffer  10 . The inverter IV 7  outputs a signal by driving an output signal of the delay control unit  50 . The inverter IV 8  drives an output signal of the delay control unit  60  to provide the global bus line control signal GB_BL to the latch  70 . 
   The signal delay unit  30  comprises MOS capacitors C 5  and C 6  selectively connected to an output terminal of the inverter IV 6  controlled by the delay control unit  50 . The signal delay unit  40  comprises MOS capacitors C 7  and C 8  selectively connected to an output terminal of the inverter IV 7  controlled by the delay control unit  60 . 
   The delay control unit  50  comprising an inverter IV 9  and transmission gates T 1  and T 2  selectively connects MOS capacitors C 5  and C 6  to control the setup/hold time of the global bus line control signal GB_BL provided to the latch  70 . The inverter IV 9  inverts a test mode delay signal TM_DLY&lt;0&gt;. The transmission gates T 1  and T 2  selectively connects the MOS capacitors C 5  and C 6  to the output terminal of the inverter IV 6  according to a state of the test mode delay signal TM_DLY&lt;0&gt;. 
   Here, the transmission gates T 1  and T 2  receive the test mode delay signal TM_DLY&lt;0&gt; through a NMOS gate, and the inversion of the test mode delay signal TM_DLY&lt;0&gt; by the inverter IV 9  through a PMOS gate. 
   The delay control unit  60  comprising an inverter IV 10  and transmission gates T 3  and T 4  selectively connects MOS capacitors C 7  and C 8  to control the setup/hold time of the global bus line control signal GB_BL provided to the latch  70 . The inverter IV 10  inverts a test mode delay signal TM_DLY&lt;1&gt;. The transmission gates T 3  and T 4  selectively connects the MOS capacitors C 7  and C 8  to the output terminal of the inverter IV 7  according to a state of the test mode delay signal TM_DLY&lt;1&gt;. 
   Here, the transmission gates T 3  and T 4  receive the test mode delay signal TM_DLY&lt;1&gt; through a PMOS gate, and the inversion of the test mode delay signal TM_DLY&lt;1&gt; by the inverter IV 10  through a NMOS gate. 
   The latch  70  latches the global bus line control signal GB_BL in synchronous to a clock signal CLK to output the latched signal into a global bus line (not shown). 
     FIG. 3  is a circuit diagram illustrating a decoding unit for generating the test mode delay signal TM_DLY&lt;0&gt; of FIG.  2 . 
   The decoding unit comprises a logic unit  80  and latches  90  and  100 . The logic unit  80  logically operates a test control signal TCS and a test mode entry signal TM_EP. The latches  90  and  100  latches output signals of the logic unit  80  and an test mode exit signal TM_EXP to output a test mode delay signals TM_DLY&lt;1:0&gt;. 
   Here, the logic unit  80  comprises an inverter IV 11  and NAND gates ND 1  and ND 2 . The inverter IV 11  inverts a test control signal TCS. The NAND gate ND 1  NANDs the test control signal TCS and the test mode entry signal TM_EP. The NAND gate ND 2  NANDs the test mode entry signal TM_EP and an output signal of the inverter IV 11 . 
   The latch  90  comprises two cross-coupled NAND gates ND 3  and ND 4  with an output of a NAND gate fed back to an input of the other NAND gate. A NAND gate ND 3  NANDs an output signal of the NAND gate ND 1  and an output signal of the NAND gate ND 4  to output the test mode delay signal TM_DLY&lt;0&gt;. The NAND gate ND 4  NANDs the test mode exit signal TM_EXP and an output signal of the NAND gate ND 3 . 
   The latch  100  comprises two cross-coupled NAND gates ND 5  and ND 6  with an output of a NAND gate fed back to an input of the other NAND gate. The NAND gate ND 5  NANDs an output signal of the NAND gate ND 2  and an output signal of the NAND gate ND 6  to output the test mode delay signal TM_DLY&lt;1&gt;. The NAND gate ND 6  NANDs the test mode exit signal TM_EXP and an output signal of the NAND gate ND 5 . 
   The operation process of the device for controlling setup/hold time of input signal is described referring to FIG.  4 . 
   In case of a normal operation mode, the test mode delay signals TM_DLY&lt;1:0&gt; are maintained at a low state. When the test mode delay signal TM_DLY&lt;0&gt; is at a low state, the transmission gates T 1  and T 2  are all turned off, and outputs of the MOS capacitors C 5  and C 6  do not affect an output terminal of the inverter IV 6 . When the test mode delay signal TM_DLY&lt;1&gt; is at a low sate, the transmission gates T 3  and T 4  are turned on, and an output terminal of the inverter IV 7  is connected to the MOS capacitors C 7  and C 8 . AS a result, an output signal of the inverter IV 7  is delayed by the MOS capacitors C 7  and C 8 , and the global bus line control signal GB_BL is delayed. 
   In order to delay the setup/hold time of the global mode delay signal GB_BL in a test mode state, the decoding unit is controlled for the test mode delay signal TM_DLY&lt;0&gt; to be at a high level. On the other hand, in order to advance the setup/hold time of the global bus line control signal GB_BL, the delay unit is controlled for the test mode delay signal TM_DLY&lt;1&gt; to be at a high level. 
   When the test control signal TCS is at a high level, in order to delay the setup/hold time of the global bus line control signal GB_BL, the test mode entry signal TM_EP is enabled to a high level. 
   When the test mode entry signal TM_EP is enabled to the high level, the NAND gate ND 1  of the logic unit  80  outputs a low signal, and the NAND gate ND 2  outputs a high signal. Then, the latch  90  outputs the test mode delay signal TM_DLY&lt;0&gt; at the high level, and the latch  100  outputs the test mode delay signal TM_DLY&lt; 1 &gt; at the low level. 
   Thereafter, when the test mode delay signal TM_DLY&lt;0&gt; becomes high, the transmission gates T 1  and T 2  of the delay control unit  50  are all turned on, and an output signal of the inverter IV 6  is delayed by the MOS capacitors C 5  and C 6 . When the test mode delay signal TM_DLY&lt;1&gt; becomes low, the transmission gates T 3  and T 4  of the delay control unit  60  are all turned on, and an output signal of the inverter IV 10  is delayed by the MOS capacitors C 7  and CB. 
   Next, when a test mode exit signal /TM_EXP is generated, the test mode delay signal TM_DLY&lt;0&gt; is disabled to the low level, and maintained at a normal state. 
   As a result, when the test control signal TCS is at the high level, the test mode delay signal TM_DLY&lt;0&gt; becomes high to delay the setup/hold time of the global bus line control signal GB_BL. 
   On the other hand, when the test control signal TCS becomes low, the test mode entry signal TM_EP is enabled to the high level to advance the setup/hold time of the global bus line control signal GB_BL. 
   When the test mode entry signal TM_EP is enabled to the high level, the NAND gate ND 1  of the logic unit  80  outputs a high signal, and the NAND gate ND 2  outputs a low signal. Then, the latch  90  outputs the test mode delay signal TM_DLY&lt;0&gt; at the low level, and the latch  100  outputs the test mode delay signal TM_DLY&lt;1&gt; at the high level. 
   Next, when the test mode delay signal TM_DLY&lt;0&gt; becomes low, the transmission gates T 1  and T 2  of the delay control unit  50  are all turned off, and output signal of the inverter IV 6  is not delayed. When the test mode delay signal TM_DLY&lt;1&gt; becomes high, the transmission gates T 3  and T 4  of the delay control unit  60  are all turned off, and an output signal of the inverter IV 7  is not delayed. 
   Thereafter, when the test mode exit signal /TM_EXP is generated, the test mode delay signal TM_DLY&lt;1&gt; is disabled to the low level, and maintained at a normal state. 
   Accordingly, when the test control signal TCS is at the low level, the test mode delay signal TM_DLY&lt;1&gt; becomes high to advance the setup/hold time of the global bus line control signal GB_BL. 
   As discussed earlier, a setup/hold time control signal of the present invention can optimize the setup/hold time at a small cost by changing the setup/hold time of outputted from an input buffer without ng the control device.