Abstract:
Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

Description:
BACKGROUND OF THE INVENTION  
     RELATED APPLICATIONS  
       [0001]     This application claims the benefit of priority to Korean Patent Application 2004-56967, filed on Jul. 21, 2004, the disclosure of which is incorporated herein by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to dynamic random access memory (DRAM) semiconductor devices and systems, and more particularly to methods and apparatus for transitioning to a self-refresh mode in a device that performs per-bank auto-refresh operations.  
         [0004]     2. Description of the Related Art  
         [0005]     DRAM devices are well known and commonly found in digital systems having a need for read/write digital memory. DRAM devices are so-named because the data in each memory cell must be refreshed periodically by reading the data, or else the stored data will be corrupted. Modern synchronous DRAM devices (SDRAMs) typically employ an “auto-refresh” mode, which refreshes one row of the DRAM memory cell array each time an auto-refresh operation is initiated by an external memory controller. An internal refresh row counter increments through the rows for successive auto-refresh operations, and wraps back to the top of the array upon reaching the bottom. The DRAM memory controller thus has some flexibility as to when it issues the auto-refresh commands to a DRAM device, as long as all rows are refreshed within the maximum time specified for the array to maintain stable data.  
         [0006]     Many SDRAM devices contain multiple banks of memory, with the high-order row address bits supplied to the SDRAM along with an operation determining which bank is to receive the operation. Some of these devices allow a bank address to be supplied with an auto-refresh command, and then an auto-refresh operation is performed in the bank specified by the bank address with regard to the current refresh row while a data access operation may be performed in the unselected banks at the same time. Such devices will be referred to herein as Per-Bank Refresh (PBR) SDRAM devices. The inventor of the present application has filed a copending application, U.S. patent application Ser. No. 11/105,169, disclosing novel PBR SDRAM architectures and methods of operation, the disclosure of which is incorporated herein by reference.  
         [0007]     Many SDRAM devices also incorporate a “self-refresh” mode. In self-refresh mode, the SDRAM device generally enters a lower-power state during which it does not respond to bus commands until awakened. In self-refresh mode, the SDRAM device is expected to perform its own refresh operations, based on internal timing, sufficient to retain data saved in the memory device.  
       SUMMARY OF THE INVENTION  
       [0008]     It has now been recognized that at least some PBR SDRAM devices can benefit from a self-refresh mode that incorporates logic for transitioning to self-refresh mode at any point in an auto-refresh cycle, whether all banks have been refreshed for the current refresh row or not. Possible benefits include lessening the device-specific requirements on the memory controller, increasing the flexibility of the memory device, and allowing less critical timing for transitions to self-refresh mode.  
         [0009]     In one aspect of the present disclosure, a method of operating a multibank memory device is disclosed. The method comprises receiving an external refresh bank address, and performing an auto-refresh operation on a current row of a memory cell array bank corresponding to the external refresh bank address. The device responds to a power-down command by entering a self-refresh mode. Prior to updating the current row to a new row for the first time in self-refresh mode, the device completes auto-refresh operations (if necessary) for the current row in all memory cell array banks, e.g., by refreshing the current row in the banks that have not had a refresh operation performed on the current row, or by refreshing all banks for the current row, even if one or more of those banks have been auto-refreshed prior to entering self-refresh mode. Several embodiments are presented for completing refresh operations for the current row.  
         [0010]     In another aspect of the present disclosure, a synchronous memory device is disclosed. The memory device comprises a plurality n of independently addressable memory cell array banks, a refresh address generator to specify a current refresh row to all memory cell array banks, and bank address circuitry to receive an externally supplied bank address for a refresh operation and apply the refresh operation to the memory cell array bank corresponding to the bank address. A refresh bank address counter signals the refresh address generator to generate a new refresh row when refresh operations have been addressed to the current refresh row in each of the plurality of memory cell array banks. Self-refresh circuitry applies refresh operations to the memory cell array banks in a self-refresh mode, the self-refresh circuitry comprising circuitry to complete refresh operations for the current refresh row in all memory cell array banks upon entering self-refresh mode and before updating the current refresh row to a new row. The self-refresh circuitry can function according to several more specific embodiments, which will be further detailed below.  
         [0011]     Other aspects disclosed include memory controllers, memory modules, and memory systems useful with the disclosed memory devices. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIGS. 1A and 1B  illustrate in block diagram form, respectively, decoded auto-refresh and external auto-refresh signal versions of a synchronous dynamic random access memory (SDRAM) device according to a first embodiment;  
         [0013]      FIG. 2  illustrates a counting control signal generator useful, e.g., in the SDRAM device of  FIGS. 1A and 1B ;  
         [0014]      FIG. 3  contains a timing diagram showing an auto-refresh-to-self-refresh transition for the SDRAM device of  FIGS. 1A and 1B ;  
         [0015]      FIG. 4  contains a block diagram for an alternate self-refresh clock generator useful with the SDRAM device of  FIGS. 1A and 1B ;  
         [0016]      FIG. 5  contains an alternate timing diagram showing an auto-refresh-to-self-refresh transition for the SDRAM device of  FIGS. 1A and 1B ;  
         [0017]      FIGS. 6A and 6B  illustrate in block diagram form, respectively, decoded auto-refresh and external auto-refresh signal versions of a synchronous dynamic random access memory (SDRAM) device according to a second embodiment;  
         [0018]      FIG. 7  illustrates a set circuit useful, e.g., in the SDRAM device of  FIGS. 6A and 6B ;  
         [0019]      FIG. 8  contains a timing diagram showing an auto-refresh-to-self-refresh transition for the SDRAM device of  FIGS. 6A and 6B ;  
         [0020]      FIGS. 9A and 9B  illustrate in block diagram form, respectively, decoded auto-refresh and external auto-refresh signal versions of a synchronous dynamic random access memory (SDRAM) device according to a third embodiment;  
         [0021]      FIG. 10  contains a timing diagram showing an auto-refresh-to-self-refresh transition for the SDRAM device of  FIGS. 9A and 9B ;  
         [0022]      FIG. 11  illustrates an alternate arrangement for a counting control signal generator and a set circuit useful, e.g., in the FIGS.  9 A/ 9 B circuit to form a synchronous dynamic random access memory (SDRAM) device according to a permutation of the third embodiment;  
         [0023]      FIG. 12  contains a timing diagram showing an auto-refresh-to-self-refresh transition for an SDRAM device using the counting control signal generator and set circuit of  FIG. 11 ;  
         [0024]      FIGS. 13A and 13B  illustrate in block diagram form, respectively, decoded auto-refresh and external auto-refresh signal versions of a synchronous dynamic random access memory (SDRAM) device according to a fourth embodiment;  
         [0025]      FIG. 14  contains a timing diagram showing an auto-refresh-to-self-refresh transition for the SDRAM device of  FIGS. 13A and 13B ;  
         [0026]      FIG. 15  contains an alternate timing diagram showing an auto-refresh-to-self-refresh transition for the SDRAM device of  FIGS. 13A and 13B ;  
         [0027]      FIG. 16  depicts a memory system according to an embodiment using decoded auto-refresh commands;  
         [0028]      FIG. 17  depicts a memory system according to an embodiment using decoded auto-refresh commands and a memory module comprising multiple memory devices;  
         [0029]      FIG. 18  depicts a memory system according to an embodiment using external auto-refresh signals; and  
         [0030]      FIG. 19  depicts a memory system according to an embodiment using external auto-refresh signals and a memory module. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0031]      FIG. 1A  shows a SDRAM device  100  in block diagram form. A memory cell array  10  comprises a plurality of memory cell array banks  10 - 1  to  10 - n,  where n can be any number larger than 1, and is typically a power of 2. Each bank comprises a plurality of memory cells MC, each connected to a unique combination of one of a plurality of bit lines BL and one of a plurality of word lines WL, as is known in the art.  
         [0032]     A row address decoder circuit  12  selects one of main word lines for each memory operation based on a supplied row address radda. Each of the main word lines couples to a plurality of word lines (WLs) through a control circuit (not shown). Row address decoder circuit  12  comprises a plurality of row address decoders  12 - 1  to  12 - n,  each activating word lines in a respective one of the memory cell array banks  10 - 1  to  10 - n.  A plurality of bank select signals ba 1  to ban determines which of the row address decoders responds to row address radda.  
         [0033]     A column address decoder circuit  14  selects the bit line(s) that will be read/written during memory read/write operations, based on a column address cadd. Column address decoder circuit  14  comprises a plurality of column address decoders  14 - 1  to  14 - n,  each reading bit lines in a respective one of the memory cell array banks  10 - 1  to  10 - n.    
         [0034]     A refresh address generator  28  receives a count signal cnt when a new refresh row address should be generated. Refresh address generator  28  supplies a current refresh row address RADD to a selector  30 .  
         [0035]     An address latch  32  receives a plurality of external address signals ADD and a plurality of external bank address signals BA. An auto-refresh command signal AREF, an Active (ACT) signal, Write (WR) signal, and Read (RD) signal determine how ADD and BA are interpreted. During an active command, the ADD signals are latched and supplied as a row address radd to selector  30 , and the BA signals are latched and supplied as a bank address iba 1  to a first switch  34 . During a read or write command, the ADD signals (and possibly the BA signals as well) are latched and supplied as column address cadd to the column address decoder circuit  14 . During an auto-refresh command, the bank address signals BA are latched and supplied as bank address iba 1  to the first-switch  34 .  
         [0036]     A command decoder  20  receives external command signals COM and generates various control signals, including ACT, WR, and RD, AREF, and PD (a power-down signal). When an auto-refresh command and a power-down command are received together, command decoder  20  asserts PD to a self-refresh control signal generator  22 .  
         [0037]     Self-refresh control signal generator  22  asserts a self-refresh control signal SREF when the device enters self-refresh mode. That is, the device enters self-refresh mode when the power down signal PD is activated. SREF is supplied to several blocks, including first switch  34 , a clock generator  24 , selector  30 , and a second switch  40 .  
         [0038]     Clock generator  24  generates a refresh clocking signal SCLK when the device is in self-refresh mode and SREF is enabled. SCLK triggers a bank address generator  26  to generate a self-refresh bank address iba 2  on every SCLK cycle, e.g., in a predetermined repeating order that sequentially addresses each bank  10 - 1  to  10 - n.    
         [0039]     First switch  34  receives iba 1  and iba 2 , and self-refresh control signal SREF. When SREF is not asserted, iba 1  is passed through first switch  34  as a bank address iba. When SREF is asserted, iba 2  is passed through first switch  34  as bank address iba.  
         [0040]     A bank address decoder  36  decodes bank address iba to generate the appropriate bank select signal from the group ba 1 -ban.  
         [0041]     Selector  30  determines whether the current refresh address RADD or the address latch output address radd is passed to row address decoder circuit  12  as row address radda. The auto-refresh command signal AREF and the self-refresh control signal SREF are supplied to selector  30  as the selection signals-when either AREF or SREF is asserted, RADD is selected as address radda to row decoder  12 , and otherwise radd is selected.  
         [0042]     A second switch  40  passes bank select signals ba 1 -ban through as buffered bank select signals bba 1 -bban, respectively, based on auto-refresh command signal AREF or self-refresh control signal SREF. When either AREF or SREF is asserted, second switch  40  replicates each bank select signal onto its corresponding buffered bank select signal line.  
         [0043]     A counting control signal generator  38  receives buffered bank select signal lines bba 1 -bban. When each buffered bank select signal has been asserted for the current refresh row, counting control signal generator  38  asserts a count signal cnt to refresh address generator  28 , signaling refresh address generator  28  to update the current refresh row to a new row. As will be described in one optional arrangement of this embodiment, count signal cnt can also be supplied to clock generator  24 .  
         [0044]     A data input buffer  16  receives data signals DIN from an external data bus when Write signal WR is active, and supplies data signals din to memory array  10 . A data output buffer  18  receives data signals dout from memory array  10  when Read signal RD is active, and supplies data signals DOUT to the external data bus.  
         [0045]     An alternative arrangement SDRAM device  100 ′ is shown in  FIG. 1B . SDRAM device  100 ′ is similar to SDRAM device  100 , except that a dedicated external refresh signal EREF, instead of a decoded command AREF, determines when an auto-refresh operation is to be performed. The following figures will further illustrate operation of SDRAM devices  100  and  100 ′, assuming AREF and EREF behave similarly.  
         [0046]      FIG. 2  shows one embodiment of counting control signal generator  38 . Counting control signal generator  38  comprises latch circuits LA 1  to LAn, each receiving a corresponding buffered bank address signal bba 1  to bban, each providing one input to an n-input NOR gate NOR 1 . NOR gate NOR 1  provides the generator output signal cnt, which also feeds back to each latch circuit as a reset signal.  
         [0047]     Each latch circuit comprises two n-channel MOSFET transistors N 1  and N 2 , and a latch L formed from two inverters I 1  and  12  connected input-to-output with each other. Transistor N 1  acts as an isolation transistor, connecting latch L to the buffered bank address signal when the buffered bank address is asserted. When the buffered bank address is asserted, latch L is forced to a state where the output of the latch circuit is low. Once all buffered bank address signals have been asserted, all inputs to NOR 1  will be low, and NOR 1  asserts cnt.  
         [0048]     In each latch circuit, transistor N 2  is connected in a pull-down configuration to the input of latch L, with cnt provided as a gate signal to N 2 . Thus when cnt is asserted, it forces latch L to a state where the output of the latch circuit is high, resetting counting control signal generator  38  and deasserting cnt.  
         [0049]      FIG. 3  contains a timing diagram illustrating the operation of SDRAM devices  100  and  100 ′ with the counting control signal generator of  FIG. 2 , assuming a four-bank memory array with bank addresses  00 ,  01 ,  10 , and  11 . During a time period T 1 , the memory device is in normal mode, and responds to auto-refresh commands and active mode commands (not shown). Refresh address generator has generated a current refresh row address RADD with a value 0 . . . 0111. During T 1 , a first auto-refresh command is signaled with a supplied bank address BA equal to 00, which is latched by address latch  32  as internal bank address iba 1 . Because SREF is low, iba 1  is passed to bank address decoder  36 , which decodes the value 00 and asserts bank address select signal ba 1 . The AREF assertion activates second switch  40 , causing counting control signal generator  38  to latch bba 1 . The AREF assertion also causes selector  30  to pass the current refresh row address  0  . . .  0111  to row address decoder  12 . As a result, row  0  . . .  0111  in bank  10 - 1  is refreshed.  
         [0050]     Also during T 1 , a second auto-refresh command is signaled with a supplied bank address BA equal to 01. Through similar responses, counting control signal generator  38  now latches bba 2 , and row  0  . . .  0111 , bank  10 - 2  is refreshed.  
         [0051]     At a third AREF assertion, a power down command is issued, causing the value of PD to move to a logic high state. Self-refresh control signal generator  22  recognizes that the device is being placed in a low-power state, and asserts self-refresh control signal SREF to clock generator  24 . This ends time period T 1 , and begins a time period T 2  where the memory device is in a self-refresh mode. Note that at the time self-refresh mode is entered, only two of four banks (banks  10 - 1  and  10 - 2 ) have been refreshed for the current refresh row.  
         [0052]     Clock generator  24  responds to the SREF assertion by generating a first SCLK pulse to bank address generator  26 . Bank address generator generates a first internal bank address iba 2  with a value 00. Because SREF is now high, iba 2  is passed to bank address decoder  36 , which decodes the value 00 and asserts bank address select signal ba 1 . The SREF assertion activates second switch  40 , causing counting control signal generator  38  to attempt to latch bba 1  again (with no effect, since bba 1  has already been latched). The SREF assertion also causes selector  30  to pass the current refresh row address  0  . . .  0111  to row address decoder  12 . As a result, row  0  . . .  0111  in bank  10 - 1  is refreshed again, this time in self-refresh mode.  
         [0053]     Also during T 2 , a second SCLK assertion causes bank address generator to advance to a bank address of  01 . Through similar responses, counting control signal generator  38  now attempts to latch bba 2  again, and row  0  . . .  0111 , bank  10 - 2  is refreshed again.  
         [0054]     A third SCLK assertion causes bank address generator  26  to advance to a bank address of  10 . Through similar responses, counting control signal generator  38  now latches bba 3 , and row  0  . . .  0111 , bank  10 - 3  is finally refreshed.  
         [0055]     A fourth SCLK assertion causes bank address generator  26  to advance to a bank address of  11 . Through similar responses, counting control signal generator  38  now latches bba 4 , and row  0  . . .  0111 , bank  10 - 4  is finally refreshed.  
         [0056]     Note that after four SCLK assertions, the current refresh row  0  . . .  0111  has finally been refreshed in all banks and all four latch circuits in counting control signal generator  38  have latched their respective bank address select signals. This causes counting control signal generator  38  to assert cnt, resetting itself and advancing refresh address generator  28  to the next refresh row address RADD (with a value 0 . . . 1000). A new time period T 3  begins, during which the new row address is refreshed in all banks in self-refresh mode.  
         [0057]     It can be appreciated from the preceding example that no matter where the auto-refresh operation left off in the current row at the time of the power-down command (and independent of the order banks were addressed in auto-refresh operations for the current row), proper refresh operation is assured for all banks.  
         [0058]     Timing-wise, the worst case occurs when a power-down command is received with one bank left to refresh for the current row. Depending on the timing followed by the memory controller, it is possible that the remaining bank is nearing the end of its hold time.  FIGS. 4 and 5  illustrate a permutation on the first embodiment that addresses this timing scenario.  
         [0059]      FIG. 4  shows an alternate self-refresh clock generator  24 ′, comprising an auto-refresh clock reference  50 , a self-refresh clock reference  52 , a NOR gate NOR 2 , and an inverter  13 . Clock references  50  and  52  receive self-refresh control signal SREF and count signal cnt. Auto-refresh clock reference  50  is enabled when SREF is asserted, and subsequently disabled the first time cnt is asserted. When enabled, auto-refresh clock reference  50  generates a clocking signal aclk. Self-refresh clock reference  52  is disabled until the first time that SREF and cnt are asserted together, and is then enabled until SREF is deasserted. When enabled, self-refresh clock reference  52  generates a clocking signal sclk.  
         [0060]     NOR gate NOR 2  receives aclk and sclk, and supplies an output to inverter  13 . The output of inverter  13  is the self-refresh clocking signal SCLK. Thus in operation, a positive clock pulse on either aclk or sclk will produce a positive clock pulse on SCLK.  
         [0061]      FIG. 5  shows an exemplary timing diagram for the FIGS.  1 A/ 1 B embodiment, with the alternate self-refresh clock generator  24 ′.  FIG. 5  follows  FIG. 3  until the power-down signal (PD) is asserted at the end of T 1 . At that point, auto-refresh clock reference  50  is enabled, and generates four consecutive clock pulses, initiating four self-refresh operations. The four self-refresh operations address the four banks successively for the current row address  0  . . .  0111 , which was the current row address for auto-refresh operation during time period (T 1 ), just before entering the self-refresh operation. After the four banks have been refreshed, counting control signal generator  38  generates a counting signal cnt to refresh address generator  28  and self-refresh clock generator  24 . In response to the cnt pulse, auto-refresh clock reference  50  is disabled and self-refresh clock reference  52  is enabled. Self-refresh clock reference  52  then initiates self-refresh clock cycles during time period T 3  and beyond.  
         [0062]     The flexibility added by self-refresh clock generator  24 ′ is that the refresh operation for the row  0  . . .  0111  can be completed relatively quickly, and then “normal” self-refresh operations begin on the next refresh row at the standard refresh rate. Comparing  FIGS. 3 and 5 , the first four self-refresh cycles are completed at a rate t 1 , and then the following self-refresh cycles occur at a slower rate t 2 .  
         [0063]      FIGS. 6A and 6B  illustrate, respectively, SDRAM devices  200  and  200 ′ according to a second embodiment, in block diagram form. In many respects, SDRAM devices  200  and  200 ′ are similar to SDRAM devices  100  and  100 ′. Those aspects of SDRAM devices  200  and  200 ′ that are unchanged from SDRAM devices  100  and  100 ′ will not be re-described.  
         [0064]     Several elements of  FIG. 1A —bank address generator  26  and first switch  34 —are not included in  FIGS. 6A and 6B . Accordingly, internal bank address iba 1  is the solitary input to bank address decoder  36 .  
         [0065]     Instead of a bank address generator,  FIG. 6A  includes a set circuit  60  that is driven by self-refresh clocking signal SCLK. Set circuit  60  has one output connected to each bank select signal ba 1  to ban. When SCLK is pulsed, set circuit  60  asserts each bank select signal, thus causing all banks to be refreshed for the current refresh row at once.  
         [0066]     Switch  40  passes all bank select signals to counting control signal generator  38 , causing cnt to be asserted at each self-refresh cycle.  
         [0067]      FIG. 7  shows one possible configuration for set circuit  60 , comprising a delay means DLC, a NOR gate NOR 3 , and n p-channel transistors P 1 -Pn. SCLK is received at one input of NOR 3  and at the input of delay means DLC. The output of delay means DLC—a delayed version of SCLK—is supplied to the other input of NOR 3 . The delay time of delay means DLC is designed to be less than the positive pulse time of SCLK. This allows a positive SCLK pulse to appear at the output of DLC while the original pulse is still active. The result is an extended negative pulse at a node b at the output of NOR 3 .  
         [0068]     Node b connects to the gates of each p-channel transistor P 1  to Pn. Each p-channel transistor is coupled between a positive power supply voltage and a respective one of the bank select signal lines ba 1  to ban. Thus when NOR 3  drives node b low, each p-channel transistor is activated, connecting each bank select signal line to the positive power supply voltage.  
         [0069]      FIG. 8  contains an exemplary timing diagram for SDRAM devices  200  and  200 ′. Like in the previous timing examples,-auto-refresh operations are complete for banks  10 - 1  and  10 - 2 , on the row with row address  0  . . .  0111 , at the time that a power-down command (PD) is issued. When self-refresh control signal generator  22  activates SREF, clock generator  24  pulses SCLK. Set circuit  60  responds by asserting bank select signals ba 1 , ba 2 , ba 3 , and ba 4  at the same time. This causes all four banks  10 - 1 ,  10 - 2 ,  10 - 3 , and  10 - 4  to be refreshed simultaneously for row address  0  . . .  0111 , which was selected during the auto refresh operation. Switch  40  passes all four bank select signals as buffered bank select signals bba 1 -bba 4  to counting control signal generator  38 . Counting control signal generator  38  generates a positive pulse on cnt, resetting itself and advancing refresh address generator  28  to a new row address RADD with a value 0 . . . 1000. Each self-refresh cycle T 2 ′, T 3 ′, T 4 ′, etc. refreshes all four banks at once, with T 2 ′ refreshing simultaneously all banks for the row that was being auto-refreshed at the time of entry to self-refresh mode.  
         [0070]      FIGS. 9A and 9B  present a third embodiment, respectively, for a decoded-refresh command SDRAM  300  and an external-refresh signal SDRAM  300 ′. Taking  FIG. 9A  as an example, the SDRAM of  FIG. 1A  is enhanced with a set circuit  60 ′ like set circuit  60  of  FIG. 7 . A self-refresh clock generator  24 ′, as shown in  FIG. 4 , is used, with the clock signals aclk and sclk supplied as outputs. Clock signal aclk supplies set circuit  60 ′, and clock signal sclk supplies bank address generator  26 .  
         [0071]      FIG. 10  contains a timing diagram illustrating the operation of SDRAM devices  300  and  300 ′. Like in the previous timing examples, auto-refresh operations are complete for banks  10 - 1  and  10 - 2 , on the row with row address  0  . . .  0111 , at the time that a power-down command is issued. When self-refresh control signal generator  22  activates SREF, clock generator  24 ′ generates a positive pulse on aclk. Like in  FIG. 8 , this positive pulse causes set circuit  60 ′ to assert all bank select signals. This causes all four banks  10 - 1 ,  10 - 2 ,  10 - 3 , and  10 - 4  to be refreshed simultaneously for row address  0  . . .  0111  during time period T 2 ′. Switch  40  passes all four bank select signals as buffered bank select signals bba 1 -bba 4  to counting control signal generator  38 . Counting control signal generator  38  generates a positive pulse for counting signal cnt, resetting itself and advancing refresh address generator  28  to a new row address RADD with a value 0 . . . 1000 during time period T 3 .  
         [0072]     The positive pulse on cnt also causes clock generator  24 ′ to disable aclk generation and begin sclk generation. Over four following sclk pulses, bank address generator  26  steps through all bank addresses  00 ,  01 ,  10 , and  11 , causing bank address decoder  36  to successively assert bank select signals ba 1 , ba 2 , ba 3 , and ba 4 . Thus over four sclk pulses during time period T 3 , the four memory banks  10 - 1 ,  10 - 2 ,  10 - 3 , and  10 - 4  are successively refreshed for row address RADD with a value 0 . . . 1000 to be refreshed. Counting control signal generator  38  registers that each bank has been refreshed, and asserts cnt at the end of time period T 3  to advance the row address and start the bank address generator cycle over for a new refresh row.  
         [0073]      FIG. 11  shows a permutation on the set circuit and counting control signal generator of  FIGS. 9A and 9B . A counting control signal generator  38 ″ is arranged similar to counting control signal generator  38  of  FIG. 2 . The outputs of latches LA 1 -LAn, labeled S 1 -Sn, are routed to NOR 1  and are also routed to set circuit  60 ′.  
         [0074]     Set circuit  60 ″ receives the signal aclk, which drives one input, respectively, of n NAND gates NA- 1  to NA-n. The other inputs of NAND gates NA- 1  to NA-n are driven, respectively, by signals S 1  to Sn from counting control signal generator  38 ″. The outputs of NAND gates NA- 1  to NA-n respectively drive the gates of p-channel transistors P 1  to Pn. P-channel transistors P 1  to Pn are connected, like in  FIG. 7 , to bank select signal lines ba 1  to ban.  
         [0075]      FIG. 12  contains a timing diagram showing the operation of the SDRAM devices  300  and  300 ′ when counting control signal generator  38 ″ and set circuit  60 ″ are used. When the power-down command is issued, latches LA 1  and LA 2  are set (with low outputs) because two prior auto-refresh commands during time period T 1  were directed to bank addresses  00  and  01 . Latches L 3  (not shown) and L 4  (e.g., Ln in  FIG. 11 ) are not set, and thus have high outputs. As a result, when aclk is asserted, NA- 3  (not shown) and NA- 4  (e.g., NA-n in  FIG. 11 ) are driven low, activating transistors P 3  (not shown) and P 4  (e.g., Pn in FIG.  11 ). Thus as shown in  FIG. 12 , bank select signals ba 3  and ba 4  are pulsed and a refresh operation is carried out during time period T 2 ′ on memory banks  10 - 3  and  10 - 4 , but not memory banks  10 - 1  and  10 - 2 . This completes refresh operations for RADD  0  . . .  0111 , causing counting control signal generator  38 ″ to assert cnt. The assertion of cnt transfers operation to the bank address generator for normal self-refresh operation, as previously described.  
         [0076]      FIGS. 13A and 13B  illustrate a fourth embodiment, respectively, for a decoded-refresh command SDRAM  400  and an external-refresh signal SDRAM  400 ′. The primary difference between SDRAM  400 , for example, and SDRAM  100 , lies in the operation of first switch  34 ′ and clock generator  24 ″. These differences are best explained with reference to the timing diagram of  FIG. 14 .  
         [0077]     Like in the previous timing diagrams, an example is presented where a power-down command is issued when auto-refresh commands have been issued for bank addresses  00  and  01  and a current refresh row. Unlike in  FIG. 3 , however, the assertion of SREF by self-refresh control signal generator does not cause first switch  34 ′ to select internal bank address iba 2 . Instead, first switch  34 ′ continues to select internal bank address iba 1  from address latch  32 . Also, clock generator  24 ″ does not begin issuing SCLK pulses at the beginning of self-refresh mode.  
         [0078]     In the  FIG. 13A / 13 B embodiment, the memory controller is expected to complete refresh operations for the current row, even though self-refresh mode has been entered. SDRAM device  400  continues to respond to AREF commands during a time period T 22  at the start of self-refresh mode. Thus a memory controller supplies the remaining bank addresses ( 10  and  11 ) for the current row while issuing new auto-refresh commands in self-refresh mode, causing banks  10 - 3  and  10 - 4  to be refreshed for row address RADD with a value 0 . . . 0111.  
         [0079]     At the end of time period T 22 , counting control signal generator  38  detects that all banks have been addressed for the current refresh row, and pulses count signal cnt. This count signal (cnt) increases refresh address RADD through the refresh address generator  28 , activates (in combination with SREF) clock generator  24 ″, and switches (in combination with SREF) first switch  34 ′ from selecting internal bank address iba 1  to selecting internal bank address iba 2 . This transition causes the memory device to enter normal self-refresh mode.  
         [0080]      FIG. 15  shows an alternate legal timing diagram for SDRAM devices  400  and  400 ′. This timing diagram illustrates that the memory controller need not track the number or identity of memory banks that have not yet been refreshed for the current row when self-refresh mode is entered. Instead, the memory controller issues one auto-refresh command for each bank after entering self-refresh mode. If it so happens that the current row advances before the end of this cycle because all banks have been addressed for the current row, any remaining auto-refresh cycles are ignored.  
         [0081]     The memory devices described in the preceding embodiments are intended for use with a memory controller in a memory system. The memory controller can be integrated in a processor, or can be a separate integrated circuit that interfaces between memory and a processor. Several representative memory systems are illustrated in  FIGS. 16-19 .  
         [0082]      FIG. 16  shows a memory system  500  comprising a memory controller  600  and a memory device  100 . Memory controller  600  supplies commands COM, bank addresses BA, and row/column addresses ADD to memory device  100  over buses as illustrated. For write commands, memory controller  600  supplies write data Din to memory device  100  over a data bus. For read commands, memory controller  600  receives read data Dout from memory device  100  over the data bus. The memory controller is expected to provide Per-Bank Refresh (PBR) auto-refresh commands to memory device  100  when the device is in normal mode. Controller  600  is allowed, however, to place memory device  100  in a power-down state without regard to the state of the PBR cycle, as explained above. Of course, memory device  100  could be replaced, e.g., with memory device  200  or  300  described above as well. Memory device  100  could also be replaced with memory device  400 , with a controller  600  that provides the additional auto-refresh commands, after entry to a power-down state, necessary to complete the PBR cycle for the current refresh row.  
         [0083]     Although a single memory device is shown in  FIG. 16 , many memory systems incorporate one or more memory modules.  FIG. 17  illustrates a memory system  550  using controller  600  and a memory module  100 -m incorporating multiple memory devices  100 - 1  to  100 -n of the same type as memory device  100  (or, e.g.,  200 ,  300 , or  400  as discussed above). Function is similar to  FIG. 16 , with buffers and/or traces (not shown) on module  1   00 -m distributing the COM, BA, and ADD signals to each memory device  100 - 1  to  100 -n.  
         [0084]      FIGS. 16 and 17  illustrate memory systems that use decoded auto-refresh commands.  FIGS. 18 and 19  illustrate analogous memory systems  500 ′ and  550 ′ that use an external auto-refresh signal EREF, supplied by a memory controller  600 ′, to initiate auto-refresh operations. Memory systems  500 ′ and  550 ′ use the external auto-refresh versions of the memory devices described above, e.g., memory devices  100 ′,  200 ′,  300 ′, and  400 ′.  
         [0085]     Those skilled in the art will recognize that many other device configuration permutations can be envisioned and many design parameters have not been discussed. For instance, various features of the described embodiments can be combined with other embodiments in other permutations. The specific circuits described and shown in the drawings are merely exemplary-in most cases, other circuits can accomplish the same or similar functions. Such minor modifications and implementation details are encompassed within the embodiments of the invention, and are intended to fall within the scope of the claims.  
         [0086]     The preceding embodiments are exemplary. Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment.