Abstract:
The semiconductor memory device includes a memory cell array configured to include a plurality of blocks, wherein each of the blocks has pages and each of the pages includes memory cells, and a peripheral circuit configured to program the memory cells to target program states. Here, the peripheral circuit programs the memory cells to temporary program states by applying program voltages increasing step-by-step by a first incremental value, and then programs the memory cells to the target program states by applying program voltages increasing step-by-step by a second incremental value.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority from Korean Patent Application No. 10-2011-0139046, filed on Dec. 21, 2011, the contents of which are incorporated herein by reference in its entirety. 
       BACKGROUND NODE OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present invention generally relates to a semiconductor memory device and a method of operating the same, and relates to a semiconductor memory device for storing data and a method of operating the same. 
         [0004]    2. Related Art 
         [0005]    Recently, a semiconductor memory device, specifically a flash memory device where data in a memory cell is maintained without being extinguished when power is not supplied has been continuously used as a data storage medium. However threshold voltage distribution of a programmed memory cell in the flash memory device may be changed by various causes while a program operation is performed, and thus malfunction of the flash memory device may occur. 
         [0006]      FIG. 1  and  FIG. 2  are views illustrating a program method when data of 2 bits is stored in one memory cell in conventional flash memory device. Particularly,  FIG. 1  illustrates a method of programming a most significant bit MSB page after a least significant LSB page is programmed and a program state formed according to the programming.  FIG. 2  illustrates a method of programming a block including plural pages. 
         [0007]    In  FIG. 1 , in the case where a least significant bit LSB data is programmed (i.e., step (b)), the memory cells have two states, i.e. erase state E and least program state LP according to a threshold voltage (i.e., Vth) distribution. Memory cells having a threshold voltage corresponding to the erase state E may maintain the erase state E or have the least program state LP. The least program state LP means a state obtained by programming a least significant bit LSB of data of 2 bits. After the LSB data is programmed, the most significant bit MSB data is programmed (i.e. step (C)). Memory cells having a threshold voltage corresponding to an erase state E of the least significant bit LSB may maintain the erase state E or be programmed to a first program state P 1  at a first programming voltage PV 1 . Memory cells having a threshold voltage corresponding to the least program state LP at a Least programming voltage LPV may be programmed to a second program state P 2  at a second programming voltage PV 2 , or a third program state P 3  at a third programming voltage PV 3  when the most significant bit MSB is programmed. 
         [0008]    In  FIG. 2(   a ), a block includes a page, every LSB and MSB of one page may be programmed (i.e., PGM), and then a program operation may be performed for the next page. For example, a LSB program and MSB program regarding a WLk is performed, and then a LSB program and MSB program regarding a WLk+1 is performed. In  FIG. 2(   b ), after the LSB of one page is programmed, the MSB of the previous page is programmed immediately. For example, a MSB program regarding a WLk is performed after a LSB program regarding a WLk+1 is performed. It is known that interference in a direction of a word according to the method in  FIG. 2(   b ) is smaller than that according to the method in  FIG. 2(   a ). However, the time it takes for programming becomes longer in the case where the conventional method in  FIG. 1  and  FIG. 2  is used, and the width of the threshold voltage formed according to the programming is comparatively great. In addition, threshold voltage of memory cell, about which a program operation is finished, shifts due to interference when the program operation is performed. This occurrence causes the malfunction of the semiconductor memory device. 
       SUMMARY OF THE INVENTION 
       [0009]    Various embodiments provide for semiconductor memory device enhancing operation characteristics and a method of operating the same. 
         [0010]    A semiconductor memory device according to an embodiment includes a memory cell array configured to include a plurality of blocks, wherein each of the blocks has pages and each of the pages includes memory cells; and a peripheral circuit configured to program the memory cells to target program states. Here the peripheral circuit programs the memory cells to temporary program states by applying program voltages increasing step-by-step by a first incremental value, and then programs the memory cells to the target program states by applying program voltages increasing step-by-step by a second incremental value. 
         [0011]    A method of operating a semiconductor memory device according to an embodiment includes programming memory cells to temporary program states by applying program voltages that increase step-by-step by a first incremental value in a first program step; and programming the memory cells to target program states by applying program voltages that increase step-by-step by a second incremental value in a second program step. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The above and other features and advantages of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein: 
           [0013]      FIG. 1 ,  FIG. 2(   a ), and  FIG. 2(   b ) are views illustrating a program method when data of 2 bits is stored in one memory cell within a conventional flash memory device 
           [0014]      FIG. 3  is a view illustrating a semiconductor memory device according to an exemplary embodiment; 
           [0015]      FIG. 4  is a view illustrating the memory cell array in  FIG. 3 ; 
           [0016]      FIG. 5  is a view illustrating a program method in an example where data of 2 bits may be stored in one memory cell of the semiconductor memory device in  FIG. 3  and a program state formed according to the program method; 
           [0017]      FIG. 6  is a flowchart illustrating a method of programming one block including plural pages in an example where the data of 2 bits is stored in one memory cell in the semiconductor memory device in  FIG. 3 ; 
           [0018]      FIG. 7  is a view illustrating a program voltage applied to a selected word line in a semiconductor memory device according to an embodiment; and 
           [0019]      FIG. 8  is a flowchart illustrating the operation of a semiconductor memory device according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Hereinafter, the preferred embodiments of the present invention will be explained in more detail with reference to the accompanying drawings. Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. 
         [0021]    In the present invention, operation characteristics of the semiconductor memory device may be enhanced. 
         [0022]      FIG. 3  is a view illustrating a semiconductor memory device according to an exemplary embodiment. 
         [0023]    In  FIG. 3 , a semiconductor memory device  300  may include a memory cell array  310  and a peripheral circuit  320 . In the case where the semiconductor memory device  300  may be a NAND flash memory device, the peripheral circuit  320  may include a page buffer section  322 , an input/output circuit  324 , a row decoder  326 , and a voltage generation section  328 . 
         [0024]    The memory cell array  310  may be a data storage area of the semiconductor memory device  300  and may include memory cells (not illustrated) connected to bit lines BL (i.e., BL 1 , BL 2  . . . BLm) and word lines WL (i.e., WLn, WLn−1 . . . WL 2 , WL 1 ). The row decoder  326  and the memory cell array  310  may also be connected through source select lines SSL and drain select lines DSL. Each of the memory cells (not illustrated) in the memory cell array  310  may have an erase state or a program state. Each of the memory cells may store single bit data or multi bit data related to the program state. A memory cell for storing the single bit data may be referred to as a single level cell SLC, and a memory cell for storing multi bit data of above 2 bits may be defined as a multi level cell MLC. The single level cell SLC may have an erase state and one program state according to a threshold voltage. The multi level cell MLC may have an erase state and plural program states in accordance with a threshold voltage. The multi level cell MLC may be programmed to one of the threshold voltage distributions to store plural bits in one memory cell. 
         [0025]    The page buffer section  322  may operate as a writing driver or a sensing amplifier according to an operation mode. For example the page buffer section  322  may operate as the sensing amplifier in a read operation mode, and it may operate as the writing driver in a program operation mode. The page buffer section  322  may receive data to be programmed from the input/output circuit  324  in the program operation, and may store the received data in a latch (not illustrated). The page buffer section  322  may provide a ground voltage to the bit line BL of memory cells to be programmed in the program operation. The page buffer section  322  may provide a program inhibition voltage to a bit line BL of memory cells of which programming is inhibited. 
         [0026]    The input/output circuit  324  may deliver an address or program data, etc. inputted through an input/output terminal. The input/output circuit  324  may transmit a stored address to an address buffer (not illustrated), transmit program data to the page buffer section  322 , and transmit a command to a command register (not illustrated). In the read operation, read data provided from the page buffer section  322  may be outputted to an outside through the input/output circuit  324 . 
         [0027]    The row decoder  326  may usually select the word line WL in response to a row address. The row decoder  326  may deliver various word line voltages provided from the voltage generation section  328  to word lines WL. When the program operation is performed, a program voltage may be provided to a selected word line and a pass voltage may be applied to a word line not selected. When the read operation is performed, the row decoder  326  may provide a read voltage provided from the voltage generation section  328  to the selected word line and may apply the pass voltage to the word line not selected. The voltage generation section  328  may provide a voltage for program of the semiconductor memory device  300 . 
         [0028]      FIG. 4  is a view illustrating the memory cell array in  FIG. 3 . 
         [0029]    In  FIG. 4 , the memory cell array  310  may include cell strings ST (not illustrated) connected to corresponding bit lines BL (i.e., BL 1  . . . BLm). [added that the ST was not illustrated because they were not identified in  FIG. 4 ] The cell string ST has a drain select transistor DST connected to the bit line BL, a source select transistor SST connected to a common source line CSL, and memory cells MC or cell transistors MC (i.e., MCn, MCn−1 . . . MC 2 , MC 1 ) connected in serial between the drain select transistor DST and the source select transistor SST. Gates of the drain select transistors DST are connected to a drain select line DSL, gates of the source select transistors SST are connected to a source select line SSL, and a control gate of each of the memory cells MC is connected to a corresponding word line WL (i.e., WLn, WLn−1 . . . WL 2 , WL 1 ). The drain select transistor DST and the source select transistor SST may be general MOS transistors, and the memory cells MC may be a transistor having an electric charge storing layer such as a floating gate or a charge trap layer. 
         [0030]      FIG. 5  is a view illustrating a program method in the case where data of 2 bits is stored in one memory cell of the semiconductor memory device in  FIG. 3  and a program state is formed according to the program method. 
         [0031]    In  FIG. 5 , in the case where data of 2 bits is stored in one memory of the semiconductor memory device  300 , memory cells may have one erase state E, three temporary program states TP 1 , TP 2 , and TP 3 , and three target program states P 1 , P 2 , and P 3  in a program operation. Three temporary program states TP 1 , TP 2 , and TP 3  may mean temporary states in-between the program operation, and the memory cell may have finally one erase state E and three target program states P 1 , P 2 , and P 3  in the case where the program operation is finished. 
         [0032]    The semiconductor memory device  300  may use a program method different from the conventional program method where the most significant bit MSB and the least significant bit LSB are separately programmed in sequence. Additionally, memory cells in the semiconductor memory device  300  may be programmed to the temporary program state TP 1 , TP 2 , and TP 3  corresponding to the erase state E in a first program step (i.e., 1 st  PGM). Subsequently, the memory cells may be programmed to the target program state P 1 , P 2 , and P 3  corresponding to each of the temporary program states TP 1 , TP 2 , and TP 3 , respectively, in a second program step (i.e., 2 nd  PGM). The program operation of the memory cells is finished through the first program step and the second program step. The memory cells of the semiconductor memory device  300  may be programmed to a first target program state P 1  via first temporary program state TP 1  in a process of programming them from the erase state E to the first target program state P 1 , is programmed to second target program state P 2  via second temporary program state TP 2  in a process of programming them for the erase state E to the second target program state P 2 , and is programmed to third target program state P 3  via third temporary program state TP 3  in a process of programming them for the erase state E to the third target program state P 3 . Here, interval ΔV between a first verifying voltage PV 1 ′ for verifying the programming to the first temporary program state TP 1  and a second verifying voltage PV 1  for verifying the programming the first target program state P 1  may be determined optionally. The interval ΔV between first verifying voltages PV 1 , PV 2 ′, and PV 3 ′ corresponding to the temporary program state TP 1 , TP 2 , and TP 3  and second verifying voltages PV 1 , PV 2 , and PV 3  corresponding to the target program states P 1 , P 2 , and P 3  may be determined in consideration of the number of program voltages applied in the second program step. For example, the first verifying voltages PV 1 ′, PV 2 ′, and PV 3 ′ may be determined to levels corresponding to the second program step where the program operation is finished by using two or three program voltages. The interval ΔV between the first verifying voltages PV 1 ′, PV 2 ′, and PV 3 ′ corresponding to the temporary program state TP 1 , TP 2 , and TP 3  and the second verifying voltages PV 1 , PV 2 , and PV 3  corresponding to the target program states P 1 , P 2 , and P 3  may vary on the basis of program velocity. 
         [0033]      FIG. 6  is a flowchart illustrating a method of programming one block including plural pages in the case where data of 2 bits may be stored in one memory cell in the semiconductor memory device in  FIG. 3 . 
         [0034]    Referring to  FIG. 5  and  FIG. 6 , memory cells connected to word lines WL (i.e., WL 1 , WL 2  . . . WLn), i.e. n pages (i.e., 1st, 2nd . . . ) are programmed to corresponding temporal program state TP 1 , TP 2 , and TP 3  in the first program step (i.e., 1st PGM). If the first program step is finished, n pages are programmed corresponding target program state P 1 , P 2 , and P 3  in the second program step (i.e., 2nd PGM). That is, the pages are programmed in sequence to the temporary program states in the first program step, and they are programmed in sequence to the target program states in the second program step. 
         [0035]      FIG. 7  is a view illustrating a program voltage applied to a selected word line in a semiconductor memory device according to an embodiment. Additionally,  FIG. 7(   a ) illustrates program voltages Vpgm applied in the first step where the memory cells may be programmed to the temporary program states, and  FIG. 7(   b ) illustrates program voltages Vpgm provided in the second step where the memory cells may be programmed to the target program states. The semiconductor memory device  300  (see  FIG. 3)  of an embodiment may use an incremental step pulse program ISPP method to narrow threshold voltage distribution of the memory cell. In the program operation, the memory cell may be programmed according to preset bias condition, e.g. a program voltage applied to the word line or a bit line voltage provided to the bit line. Since the program voltages increasing by a given incremental value may be applied to a selected word line until the program operation is finished, the program operation may be performed through plural program loops. Each of the program loops may include a program operation (i.e., programming) and a program verifying operation (i.e., verifying). The program voltage Vpgm may be applied to the selected word line in the program operation, and a program verifying voltage PV may be provided to the selected word line in the program verifying operation. The program verifying operation may verify whether or not the memory cell is programmed to the target program state. 
         [0036]    Referring to  FIG. 5  and  FIG. 7(   a ), program voltages Vpgm 1  to Vpgm 4  applied to the selected word line augment step-by-step by first incremental value ΔV 1 . The verifying operation may verify whether or not the memory cell is programmed up to corresponding temporary program state TP 1  after the program voltages Vpgm 1  to Vpgm 4  are applied. The verifying operation may determine based on the first verifying voltage PV 1 ′ whether or not the memory cell is programmed up to the temporary program state TP 1 . 
         [0037]    Referring to  FIG. 5  and  FIG. 7(   b ), program voltages Vpgm 1  to Vpgm 4  applied to the selected word line augment step-by-step by second incremental value ΔV 2 . The verifying operation may verify whether or not the memory cell is programmed to corresponding target program state P 1  after the program voltages Vpgm 1  to Vpgm 4  are applied. The verifying operation determines based on the second verifying voltage PV 1  whether or not the memory cell is programmed to the target program state P 1 . The first incremental value ΔV 1  in  FIG. 7(   a ) is greater than the second incremental value ΔV 2  in  FIG. 7(   b ). Accordingly, the first program step is completed comparative rapidly, but width of threshold voltage distribution of the temporary program state is comparatively great. The second program step is finished comparative slowly, but width of threshold voltage distribution of the target program state is comparatively narrow. 
         [0038]    In  FIG. 7(   a ) and  FIG. 7(   b ), only verifying voltage PV 1  is applied in a verifying section of each of the program loops Loop 1  to Loop 3  for convenience of description. However, plural verifying voltages may be applied in each of verifying sections. Furthermore, a verifying voltage is applied in the verifying section of each of the program loops Loop 1  to Loop  3  in  FIG. 7(   a ) and  FIG. 7(   b ), but the verifying voltage may not be not provided in the first program loop Loop 1  and may be applied in the second program loop Loop 2  and the following loop. 
         [0039]      FIG. 8  is a flowchart illustrating operation of a semiconductor memory device according to an embodiment. 
         [0040]    In  FIG. 8 , memory cells may be programmed to temporary program states by applying program voltages increasing step-by-step by a first incremental value in a first program step S 410 , and they may be programmed to target program states by applying program voltage increasing step-by-step by second incremental value in a second program step S 420 . 
         [0041]    The second incremental value may be smaller than the first incremental value. As a result, the first program step S 410  has an effect where the width of threshold voltage distribution is great but program time reduces, and the second program step S 420  forms the threshold voltage distribution having a more narrow width by using the reduced program time. The number of the temporary program states may be identical to that of the target program states. The temporary program states may correspond to one-to-one with the target program states. An interval between first verifying voltages corresponding to the temporary program states and second verifying voltages corresponding to the target program states may be determined considering the number of the program voltages increasing step-by-step applied in the second program step. For example, the interval between the first verifying voltages and the second verifying voltages corresponding to the target program states is determined based on the second program step where the program operation is completed by applying two or three program voltages. The interval between the first verifying voltages corresponding to the temporary program states and the second verifying voltages corresponding to the target program states may vary depending on program velocity. Accordingly, the semiconductor memory device may further include a means for checking the program velocity. 
         [0042]    Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.