Abstract:
A protection relay for a power line system that employs current transformers for detecting current on a bus is provided with a fault trip scheme that includes transformer current saturation detection so as to avoid false tripping due to temporary transformer current saturation.

Description:
RELATED APPLICATION  
       [0001]    This application claims the benefit of priority pursuant to 35 USC 119 of provisional patent application entitled, “Electrical Bus Protection Method &amp; Apparatus”, having Serial No. 60/392,651 filed Jun. 27, 2002, and of provisional patent application of same title, having Serial No. 60/411,090 filed Sep. 16, 2002, the disclosures of these applications are hereby incorporated in their entirety by reference herein. 
     
    
     
       FIELD OF THE INVENTION  
         [0002]    The present invention generally relates to power line systems, and more particularly to an apparatus and method for protecting an electrical power line bus or other electrical conductors having a plurality of power or electrical energy transmission lines that transmit currents. More specifically, the invention relates to a signal processing scheme intended to prevent (block) false tripping by a bus protection protective relay due to miss-information derived from saturated current transformers connected to a bus protection relay.  
         BACKGROUND OF THE INVENTION  
         [0003]    Electrical power transmission line systems are of course well known. An exemplary system is shown and described in U.S. Pat. No. 6,307,703, entitled, “Parallel-Feeder Directional Overcurrent Protection, issued to Hindle, et al, herein incorporated by reference thereto. Many such protection systems are known in the art, as exemplified by U.S. Pat. No. 6,369,996, entitled, “Fault Protection Scheme,” issued to Bo, herein incorporated by reference thereto.  
           [0004]    Before proceeding, power lines or feeder lines, as used herein, refers to any electrical current transmitting line coupled to the bus for transmitting current either from equipment generators or delivered to equipment loads, and the like.  
           [0005]    Bus protection relays are also well known. One example of a bus protection relay is shown and described in the attached product brochure known as “B-PRO,” Model 8700/BUS, manufactured by NxtPhase Technologies, SRL (formerly APT Power Technologies), the attached brochure being incorporated herein by reference thereto.  
         SUMMARY OF THE INVENTION  
         [0006]    An object of the present invention is to provide a method and apparatus for protecting an electrical power line bus having a plurality of feeder lines coupled thereto.  
           [0007]    Another object of the present invention is to provide a method and apparatus for protecting an electrical power line bus having a plurality of feeder lines, including those connected or coupled to loads and equipment, where each bus is associated with one of a plurality of phase identified transmission lines—commonly a 3-Phase Power Line System.  
           [0008]    In accordance with the present invention, monitoring signals representative a respective one of the electrical characteristic of the current associated with each one of the power lines, e.g., feeder or equipment or generator lines, coupled to an electrical power line bus are signal processed in such a manner so as to derive a trip signal indicative of a fault condition so as to protect the bus from damage.  
           [0009]    In accordance with the present invention, a protection relay if provided for a power line system for protecting a bus. The bus is provided for transmitting current to and from one or more power lines for receiving and generating power, and where associated with each of the power lines is a current transformer for providing a line signal current representative of current flowing through a respective line. The protection relay is operative for generating a trip signal in response to a detected power signal line fault. In the present invention, the protection relay includes a signal processor responsive to signal line currents for generating a trip signal in response to a detected fault on any one of power lines. Further, means is provided responsive to the signal line currents for detecting current transformer saturation; and selectively generating a blocking signal for blocking the usual trip signal in response to detection of current saturation of the current transformer. In the preferred embodiment of the present invention, current saturation detection is provided by way of monitoring a phase value of a selected harmonic of signals derived from the all of the power line currents, associated with a single bus associated with a single phase. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 is a schematic block diagram of a bus protection system for one phase of a multi-phase power system and where a bus in coupled to a plurality of power lines.  
         [0011]    [0011]FIG. 2 is a block diagram of the method in accordance with the present invention.  
         [0012]    [0012]FIG. 3 is a graphical depiction of block and hold region of the bus protection in accordance with the present invention to prevent false tripping in the case where current transformer saturation occurs late after fault initiation. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0013]    In accordance with the present invention, the bus protection system includes a saturation detector that will detect all CT saturation conditions for external faults and block the differential protection from operating, when this condition occurs. Further the signal processing in accordance with the present invention is intended to be immune to partial or fully offset waveforms, harmonics, fault arcing resistance, capacitive or inductive loads, severity of saturation, speed at which saturation occurs, and CT saturation occurring during only a portion of a detected fault. The saturation detection in accordance with the present invention is intended to not interfere with internal faults (with or without saturation), not affect the operating speed of the bus-protection differential current detection function, and not require any special settings. Further, the bus protection system in accordance with the present invention is intended to be simple to use and may be enabled or disabled. Once enabled, a timer may be set to control how long an external current transformer saturation condition is permitted to block the differential protection—normally this timer may be set to be slightly longer than the maximum clearing time for an external fault.  
         [0014]    The signal processing scheme in accordance with the present invention is intended to prevent (block) false tripping by a bus protection protective relay due to miss-information derived from saturated current transformers connected to the relay. In a conventional protection relay, saturated current transformer information may appear to be overall current imbalance—when in fact there is none—and cause a highly undesirable false trip.  
         [0015]    [0015]FIG. 1 illustrates a protective relay  5  connected to a power system bus 1  in a conventional manner. It should be recognized that FIG. 1 illustrates a three phase system. Current transformers (CT)  3  provide current signals associated with a respective one feeder line—only one is numerically identified in the drawing. Protective relay  5  includes signal processing for arriving at a trip decision signal in response to received current signals from the CT is a conventional manner.  
         [0016]    Before proceeding, it should be recognized that protection relay  5  includes a variety of electrical components commonly including analog-to-digital transformations, a microprocessor for providing a variety of protective elements for monitoring power line currents derived from the current transformers employing a variety of logically combined algorithms as well known, Such systems are commonly commercially available by Schweitzer Engineering Laboratories, as well as the aforesaid “B-PRO,” Model 8700/BUS, manufactured by NxtPhase Technologies, SRL (formerly APT Power Technologies), the associated brochure being incorporated herein by reference thereto.  
         [0017]    [0017]FIG. 2 illustrates a signal processing scheme by way of the block diagram shown therein, and may be incorporated by hardware, firmware, software, and the like, in order to provide the trip decision signal  6 . The signal processing system in accordance with the present invention utilizes several derived characteristics of the feeder currents.  
         [0018]    In a conventional manner, both the phasor sum of the power line currents associated with the power lines coupled to the bus, and the magnitude sum of these currents are first determined—equations 1. In turn, the derivatives of the phasor sum and magnitude sum signal are determined—equations 2. A harmonic of the derivative expressions, more specifically the second harmonic, is derived—equations 3. In turn the phase between the second harmonics of the derivatives of the phasor sum signal and magnitude sum signal is determined and compared to a selected threshold, e.g., “5”—equations 4. This comparison is then used to generate a block tripping signal,  6  as illustrated in FIG. 1.  
         [0019]    [0019]FIG. 3 illustrates another aspect of the present invention, and is referred to by way of the last two blocks in block diagram illustrated in FIG. 2. To allow for the case where current transformer saturation occurs several cycles after fault initiation, a subsidiary BLOCK AND HOLD SIGNAL is generated. The BLOCK AND HOLD SIGNAL is indicative of the data pair consisting of the phasor sum signal lo and magnitude sum signal Ir falling within the shaded area of FIG. 3.  
         [0020]    The BLOCK AND HOLD signal is a “trip blocking signal” that is held for several cycles beyond the time at which late saturation is detected, since otherwise, the perceived fault trajectory may cause a false trip.  
         [0021]    The following mathematical descriptions depict the equations 1-4 referred to in the above exposition.  
         [0022]    Equations 1—The Calculation of IO (Phasor Sum) and IR (Magnitude Sum)  
         [0023]    The equations for the calculation of 10 and IR (for phase A, B, and C respectively)  
             IOa   =       ∑     i   =   1     M          IA   i                           IOb   =       ∑     i   =   1     M          IB   i                           IOc   =       ∑     i   =   1     M          IC   i                   IRa   =           2   1            ∑     i   =   1     M          IA   i                             IRb   =           2   1            ∑     i   =   1     M          IB   i                             IRa   =           2   1            ∑     i   =   1     M          IC   i                                     
 
         [0024]    where M is the number of power line inputs connected to the bus; IA, IB and IC are the fundamental power line current phasors (i.e. vector: a complex number).  
         [0025]    Equations 2—The Calculation of Derivative of IO and IR  
                    IOa_               It   n         =            IOa_                 t     n   -   1         ·     (     1   -           Δ                 t             TW           )         +             (       IOa   n     -     IOa     n   -   1         )             TW         ·   K                          IRa_               It   n         =            IRa_                 t     n   -   1         ·     (     1   -           Δ                 t             TW           )         +             (       IRa   n     -     IRa     n   -   1         )             TW         ·   K                                   
 
         [0026]    The above equations are only showed for phase A current signals associated with connected or coupled loads and equipment currents. Similar equations may be expressed for phase B and phase C load and equipment currents as should be understood by those skilled in the art.  
         [0027]    Where TW is a smoothing time constant, K is a scaling factor, and subscript “n” is an indication of the present value, and “n−1” is the value of one time step before. Δt is the time step.  
         [0028]    Equations 3—The Calculation of the Second Harmonics Phasor of the Derivative of IO and IR  
               HDft_           IOa_               t   n         =           2           N         ·       ∑     i   =   0       N   -   1                 IOa_                 t     n   -   i         ·            -   j     ·           2   ·   π   ·                N                                   HDft_           IRa_               t   n         =           2           N         ·       ∑     i   =   0       N   -   1                 IRa_                 t     n   -   i         ·            -   j     ·           2   ·   π   ·                N                                                 
 
         [0029]    where N is the half of the number of samples of the fundamental frequency, e.g., a 50 Hz or 60 Hz cycle. Phase B and Phase C are similar.  
         [0030]    Equations 4—The Calculation of the Phase Difference Between HDft_dIO_dt n  and HDft_dIR_dt n    
         [0031]    The phase difference is calculated through the product of HDft_dIO_dt n  and the conjugate of  
         [0032]    HDft_dIR_dt n , i.e.  
         Dot ProdOfdIOa_dIRa n =HDft_dIOa_dt n ·HDft_dIRa_dt n *{the conjugate} 
         [0033]    [0033]         tan        (     Pha   n     )       =           Im        (     ProdOf           IOa_               IRa   n         )                 Re        (     ProdOf           IOa_               IRa   n         )                                     
         [0034]    Where the superscript * represents the conjugate of a complex number, Im is to extract the imaginary part of the complex number, and Re is to extract the real part of the complex number.  
         [0035]    When tan(Pha n )&gt;T, issue a blocking signal to the differential protection function; otherwise do not block the differential protection. “T” is a preset value.  
         [0036]    Phase B and Phase C are similar.  
         [0037]    The bus protection system in accordance with the present invention includes a significant improvement to the traditional two slope differential characteristic that provides immunity to CT mismatch and minimal CT saturation sensitivity for external faults.  
         [0038]    It should be recognized that the aforesaid calculations and signal processing may be accomplished digitally by way of simple programming within the exiting systems well within the level of those skilled in the art within existing common well known protection relays similar to those as already described without additional hardware, and the like.