Abstract:
According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims benefit of priority under 35 USC 119 from the Japanese Patent Applications No. 2006-11332, filed on Jan. 19, 2006 and No. 2007-5807, filed on Jan. 15, 2007, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a NAND-type semiconductor storage device and a method for manufacturing the same.  
         [0003]     There have conventionally been developed NAND-type flash memories as nonvolatile semiconductor memories. A memory cell transistor of a NAND-type flash memory has a structure in which a floating gate electrode formed above a semiconductor substrate via a tunnel insulating film and a control gate electrode formed above the floating gate electrode via an interelectrode insulating film are stacked.  
         [0004]     A NAND-type flash memory is formed by series-connecting pairs of source and drain regions of a plurality of memory cell transistors between two selection transistors and connecting one of the selection transistors to a bit line and the other to a source line. A control gate electrode of each memory cell transistor serves as a part of a word line.  
         [0005]     An element isolation insulating film (i.e., an element isolation region) is formed between memory cell transistors which are adjacent to each other in the direction of a corresponding word line, and the memory cell transistors adjacent in the direction of the word line are isolated from each other by the element isolation insulating film. An interlayer insulating film is formed between a piece of wiring such as the bit line and the semiconductor substrate.  
         [0006]     In this case, the NAND-type flash memory has various problems such as variations in gate threshold voltage caused by a parasitic capacitance which occurs between the piece of wiring and the semiconductor substrate and a parasitic capacitance which occurs between the memory cell transistors adjacent in the direction of the word line.  
         [0007]     To prevent such problems, there is proposed formation of a NAND-type flash memory on an SOI substrate (see, e.g., Japanese Patent Laid-Open No. 2000-174241 and Japanese Patent Laid-Open No. 11-163303).  
         [0008]     However, since this method uses an SOI substrate as a substrate, it is higher in substrate cost than a case where an ordinary silicon substrate is used.  
         [0009]     The following are the names of documents pertaining to a NAND-type flash memory formed on an SOI:  
         [0010]     Japanese Patent Laid-Open No. 2000-174241 and  
         [0011]     Japanese Patent Laid-Open No. 11-163303.  
       SUMMARY OF THE INVENTION  
       [0012]     According to an aspect of the present invention, there is provided a NAND-type semiconductor storage device including  
         [0013]     a semiconductor substrate;  
         [0014]     a semiconductor layer formed on the semiconductor substrate;  
         [0015]     a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region;  
         [0016]     diffusion layers formed on the semiconductor layer in the memory transistor formation region;  
         [0017]     floating body regions between the diffusion layers;  
         [0018]     a first insulating film formed on each of the floating body regions;  
         [0019]     a floating gate electrode formed on the first insulating film;  
         [0020]     a control electrode on a second insulating film formed on the floating gate electrode; and  
         [0021]     contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region,  
         [0022]     wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.  
         [0023]     According to an aspect of the present invention, there is provided a NAND-type semiconductor storage device manufacturing method, including  
         [0024]     forming a layer to be removed on a substrate,  
         [0025]     removing a part of the layer to be removed,  
         [0026]     forming a semiconductor layer on the layer to be removed, after the part of the layer to be removed is removed,  
         [0027]     forming a trench which extends through the semiconductor layer and reaches the layer to be removed,  
         [0028]     removing the layer to be removed using the trench,  
         [0029]     forming a buried insulating film in a cavity formed after the layer to be removed is removed,  
         [0030]     forming a first insulating film above a region where the buried insulating film is formed,  
         [0031]     forming a floating gate electrode on the first insulating film,  
         [0032]     forming a second insulating film on the floating gate electrode,  
         [0033]     forming a control electrode on the second insulating film, and  
         [0034]     forming a pair of diffusion layers in the semiconductor layer to have the floating gate electrode between the pair of diffusion layers. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0035]     FIGS.  1 (A) and  1 (B) are a plan view and a sectional view, respectively, showing the configuration of a memory cell region of a NAND-type flash memory according to a first embodiment of the present invention;  
         [0036]     FIGS.  2 (A) and  2 (B) are a plan view and a sectional view, respectively, showing the configuration of a peripheral circuit region of the NAND-type flash memory according to the first embodiment of the present invention;  
         [0037]     FIGS.  3 (A) and  3 (B) are a plan view and a longitudinal sectional view, respectively, of an element specific to a step of a manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0038]     FIGS.  4 (A) and  4 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0039]     FIGS.  5 (A) and  5 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0040]     FIGS.  6 (A) and  6 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0041]     FIGS.  7 (A) to  7 (D) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0042]     FIGS.  8 (A) and  8 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0043]     FIGS.  9 (A) to  9 (D) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0044]     FIGS.  10 (A) and  10 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0045]     FIGS.  11 (A) and  11 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0046]     FIGS.  12 (A) and  12 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the first embodiment of the present invention;  
         [0047]      FIG. 13  is a sectional view showing the configuration of a memory cell region of a NAND-type flash memory according to a second embodiment of the present invention;  
         [0048]      FIG. 14  is a sectional view showing the configuration of a memory cell region of a NAND-type flash memory according to a third embodiment of the present invention;  
         [0049]      FIG. 15  is a sectional view showing the configuration of a memory cell region of a NAND-type flash memory according to a fourth embodiment of the present invention;  
         [0050]      FIG. 16  is a sectional view showing the configuration of a memory cell region of a NAND-type flash memory according to a fifth embodiment of the present invention;  
         [0051]     FIGS.  17 (A) and  17 (B) are a plan view and a longitudinal sectional view, respectively, of an element specific to a step of a manufacturing method for a NAND-type flash memory according to another embodiment of the present invention;  
         [0052]     FIGS.  18 (A) and  18 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0053]     FIGS.  19 (A) and  19 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0054]     FIGS.  20 (A) and  20 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0055]     FIGS.  21 (A) to  21 (D) are a plan view, a longitudinal sectional view, and transverse sectional views, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0056]     FIGS.  22 (A) and  22 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0057]     FIGS.  23 (A) to  23 (D) are a plan view, a longitudinal sectional view, and transverse sectional views, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0058]     FIGS.  24 (A) and  24 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0059]     FIGS.  25 (A) to  25 (D) are a plan view, a longitudinal sectional view, and transverse sectional views, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0060]     FIGS.  26 (A) and  26 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0061]     FIGS.  27 (A) to  27 (D) are a plan view, a longitudinal sectional view, and transverse sectional views, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0062]     FIGS.  28 (A) and  28 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0063]     FIGS.  29 (A) to  29 (D) are a plan view, a longitudinal sectional view, and transverse sectional views, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0064]     FIGS.  30 (A) and  30 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention;  
         [0065]     FIGS.  31 (A) and  31 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to still another step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention; and  
         [0066]     FIGS.  32 (A) and  32 (B) are a plan view and a longitudinal sectional view, respectively, of the element specific to the step of the manufacturing method for the NAND-type flash memory according to the embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0067]     Embodiments of the present invention will be explained below with reference to the drawings.  
       (1) First Embodiment  
       [0068]     FIGS.  1 (A) and  1 (B) show the configuration of a part of a memory cell region  10  of a NAND-type flash memory according to a first embodiment of the present invention. FIGS.  2 (A) and  2 (B) show the configuration of a part of a peripheral circuit region  20  of the NAND-type flash memory.  
         [0069]      FIG. 1 (A) shows a plan view of the memory cell region  10  of the NAND-type flash memory as seen from above; and  FIG. 1 (B), a longitudinal sectional view of the memory cell region  10  taken along a line A-A.  FIG. 2 (A) shows a plan view of the peripheral circuit region  20  of the NAND-type flash memory as seen from above; and  FIG. 2 (B), a longitudinal sectional view of the peripheral circuit region  20  taken along a line A-A.  
         [0070]     As shown in FIGS.  1 (A) and  1 (B), in the memory cell region  10  of the NAND-type flash memory, a buried insulating film  40  is selectively formed in a memory transistor formation region  10 A where memory cell transistors MC and selection transistors STD and STS are formed, on a P-type semiconductor substrate  30 .  
         [0071]     A P-type semiconductor layer  50  is formed to be arranged above the semiconductor substrate  30  via the buried insulating film  40  in the memory transistor formation region  10 A and be arranged on the semiconductor substrate  30  in contact plug formation regions  10 B where a bit line contact plug  70  and a source line contact plug  80  are formed.  
         [0072]     In each memory cell transistor MC, a P-type floating body  60  which is electrically floating is formed in the semiconductor layer  50  formed above the semiconductor substrate  30  via the buried insulating film  40 .  
         [0073]     The memory cell transistor MC has a structure in which a floating gate electrode  100  formed above the floating body  60  via a tunnel insulating film  90  and a control gate electrode (control electrode)  120  formed above the floating gate electrode  100  via an interelectrode insulating film  110  are stacked. Note that a silicide  130  is formed on the control gate electrode  120 .  
         [0074]     In the memory cell transistor MC, a channel region  140  is formed on a surface portion of the floating body  60 , and a pair  150  of N-type source and drain regions (diffusion layer) is formed on two sides of the floating body  60 .  
         [0075]     Note that in each of the selection transistors STD and STS, a gate electrode  170  is formed above the floating body  60  via a gate insulating film  160 . The gate electrode  170  is formed by short-circuiting the floating gate electrode  100  and control gate electrode  120 .  
         [0076]     In each contact plug formation region  10 B of the semiconductor layer  50 , the pair  150  of N-type source and drain regions is formed to be connected to the semiconductor substrate  30 . The pair  150  of N-type source and drain regions formed in the contact plug formation region  10 B and the P-type semiconductor substrate  30  are isolated from each other by a PN junction.  
         [0077]     The memory cell region  10  of the NAND-type flash memory is formed by series-connecting the pairs  150  of source and drain regions of the plurality of memory cell transistors MC between the two selection transistors STD and STS and connecting one of the selection transistors, the selection transistor STD to a bit line BL via the bit line contact plug  70  and the other, the selection transistor STS to a source line SL via the source line contact plug  80 . The control gate electrode  120  of each memory cell transistor MC serves as a part of a word line WL.  
         [0078]     An element isolation insulating film (element isolation region)  180  is formed between ones of the memory cell transistors MC which are adjacent to each other in the direction of the corresponding word line WL. The memory cell transistors MC adjacent to each other in the direction of the word line WL are isolated from each other by the element isolation insulating film  180 . An interlayer insulating film  190  is formed between the bit line BL and the semiconductor layer  50 .  
         [0079]     As shown in FIGS.  2 (A) and  2 (B), for example, a transfer transistor FT connected to the word line WL to supply a predetermined potential to the control gate electrode  120  of the memory cell transistor MC is formed in the peripheral circuit region  20  of the NAND-type flash memory.  
         [0080]     In the transfer transistor FT, an element isolation insulating film  200  is formed on each of surface portions of the semiconductor substrate  30 , and a gate electrode  220  is formed near the center of an element region of the semiconductor substrate  30  which is isolated by the element isolation insulating films  200  via a gate insulating film  210 .  
         [0081]     A silicide  230  is formed on a surface of the gate electrode  220 , and gate electrode sidewalls  240  are formed on side surfaces of the gate electrode  220 . A channel region  250  is formed below the gate electrode  220  and near a surface of the semiconductor substrate  30 . A pair  260  of source and drain regions is formed on two sides of the channel region  250 .  
         [0082]     A contact plug  270  is formed on each of upper surfaces of the pair  260  of source and drain regions, and a piece  280  of wiring is connected to each contact plug  270 . An interlayer insulating film  290  is formed between the pieces  280  of wiring and the semiconductor substrate  30 .  
         [0083]     A manufacturing method for a NAND-type flash memory according to this embodiment will be explained with reference to FIGS.  3 (A) to  12 (B).  
         [0084]     Note that FIGS.  3 (A),  5 (A),  7 (A),  9 (A), and  11 (A) show plan views of a memory cell region  300  in an element as seen from above, specific to respective steps of the manufacturing method and that FIGS.  3 (B),  5 (B),  7 (B),  9 (B), and  11 (B) show longitudinal sectional views of the memory cell region  300  in the element taken along lines A-A, specific to the respective steps.  
         [0085]     FIGS.  4 (A),  6 (A),  8 (A),  10 (A), and  12 (A) show plan views of a peripheral circuit region  310  in the element as seen from above, specific to the respective steps, and FIGS.  4 (B),  6 (B),  8 (B),  10 (B), and  12 (B) show longitudinal sectional views of the peripheral circuit region  310  taken along lines A-A.  
         [0086]     As shown in FIGS.  3 (A) and  3 (B) and FIGS.  4 (A) and  4 (B), a silicon germanium (SiGe) layer  330  with a germanium (Ge) concentration of, e.g., 30% is formed as a layer to be removed all over a semiconductor substrate  320  to a thickness of, e.g., about 25 nm by epitaxial growth technique.  
         [0087]     A silicon (Si) layer  340  is formed all over the silicon germanium layer  330  to a thickness of about 20 nm by epitaxial growth technique, and then, a silicon nitride (SiN) film  350  is formed all over the silicon layer  340 .  
         [0088]     The silicon nitride film  350  is patterned by lithography and RIE. With this operation, in the memory cell region  300 , a part of the silicon nitride film  350  which is formed in a contact plug formation region  300 B is removed, and in the peripheral circuit region  310 , a part of the silicon nitride film  350  which is formed therein is removed. The silicon layer  340  and silicon germanium layer  330  are sequentially etched using the silicon nitride film  350  as a mask, thereby exposing a surface of the semiconductor substrate  320 .  
         [0089]     As shown in FIGS.  5 (A) and  5 (B) and FIGS.  6 (A) and  6 (B), after the silicon nitride film  350  is removed, a silicon layer  360  is formed all over the semiconductor substrate  320  and silicon germanium layer  330  to, e.g., a thickness of 30 nm by epitaxial growth technique. Note that at this time, the silicon germanium layer  330  is used as a seed in a memory transistor formation region  300 A of the memory cell region  300  and that the semiconductor substrate  320  is used as a seed in each of the contact plug formation region  300 B and peripheral circuit region  310  of the memory cell region  300 .  
         [0090]     As shown in FIGS.  7 (A) to  7 (D) and FIGS.  8 (A) and  8 (B), a mask material  370  composed of, e.g., a silicon nitride film is deposited all over the silicon layer  360  and then patterned by lithography and RIE. Note that  FIG. 7 (C) shows a longitudinal sectional view of the memory cell region  300  taken along a line B-B and that  FIG. 7 (D) shows a longitudinal sectional view of the memory cell region  300  taken along a line C-C.  
         [0091]     The silicon layer  360 , silicon germanium layer  330 , and semiconductor substrate  320  are sequentially etched using the mask material  370  as a mask, thereby forming element isolation trenches  380 . At this time, in the memory transistor formation region  300 A of the memory cell region  300 , side surfaces of the silicon germanium layer  330  are exposed at an inner surface of each element isolation trench  380  ( FIG. 7 (D)).  
         [0092]     As shown in FIGS.  9 (A) to  9 (D) and FIGS.  10 (A) and  10 (B), the semiconductor substrate  30  is immersed in a predetermined etching solution. The silicon germanium layer  330  exposed at the inner surfaces of the element isolation trenches  380  is etched by wet etching and removed. Note that the etching solution to be used here is a mixed solution obtained by mixing an aqueous nitric acid solution of 70%, an aqueous hydrofluoric acid solution of 49%, an aqueous acetic acid solution of 99.9%, and water at a volume ratio of 40:1:257.  
         [0093]     With this operation, cavities (not shown) are formed in regions from which the formed silicon germanium layer  330  has been removed. In this case, a part of the silicon layer  360  which is formed in each contact plug formation region  300 B serves as a support unit which supports a part of the silicon layer  360  which is formed in the memory transistor formation region  300 A.  
         [0094]     The entire surface of the semiconductor substrate  320  is oxidized. With this operation, the cavities (not shown) are filled with buried insulating films  390 , each composed of, e.g., a silicon oxide (SiO 2 ) film, and a silicon oxide film (not shown) is formed on the inner surface of each element isolation trench  380  to a thickness of about 13 nm. As described above, an SOI structure is selectively formed in the memory transistor formation region  300 A of the memory cell region  300 .  
         [0095]     Each element isolation trench  380  is filled with, e.g., a silicon oxide film by CVD, and the silicon oxide film is planarized, thereby forming an element isolation insulating film  400 . Note that if the element isolation insulating films  400  are formed by filling the element isolation trenches  380  with silicon oxide films by CVD without oxidation, the buried insulating films  390  may be formed by filling the cavities (not shown) with the silicon oxide films.  
         [0096]     As shown in FIGS.  11 (A) and  11 (B) and FIGS.  12 (A) and  12 (B), the mask material  370  is removed. In the memory cell region  300 , a floating gate electrode  420  is formed above the silicon layer  360  via a tunnel insulating film  410 , and a control gate electrode  440  is formed above the floating gate electrode  420  via an interelectrode insulating film  430 . After that, a suicide  450  is formed on the control gate electrode  440 . In the peripheral circuit region  310 , after a gate electrode  470  is formed above the silicon layer  360  via a gate insulating film  460 , a silicide  480  is formed on the gate electrode  470 .  
         [0097]     After that, although not shown, pairs of source and drain regions are formed by ion implantation, and an interlayer insulating film is formed all over the silicon layer  360  by CVD. A source line contact plug and a source line are formed, and a bit line contact plug and a bit line are formed in sequence. In this manner, the NAND-type flash memory shown in FIGS.  1 (A),  1 (B),  2 (A), and  2 (B) is manufactured.  
         [0098]     As described above, according to this embodiment, an SOI structure can be selectively formed in the memory cell region  10  of the ordinary semiconductor substrate  30  without using an SOI substrate. This makes it possible to improve memory cell characteristics while keeping production costs low.  
         [0099]     More specifically, isolation of a piece of wiring such as the bit line BL and the semiconductor substrate  30  from each other by the buried insulating film  40  makes it possible to make a parasitic resistance generated between the piece of wiring and the semiconductor substrate  30  lower than a case where a NAND-type flash memory is formed on an ordinary semiconductor substrate without forming an SOI structure. Accordingly, variations in gate threshold voltage can be reduced.  
         [0100]     Complete isolation of ones of the memory cell transistors MC which are adjacent to each other in the direction of the corresponding word line from each other by the buried insulating film  40  makes it possible to make a parasitic capacitance which occurs between the memory cell transistors MC adjacent in the direction of the word line smaller than a case where a NAND-type flash memory is formed on an ordinary semiconductor substrate without forming an SOI structure. Accordingly, variations in gate threshold voltage can be reduced. In this case, occurrence of punch-through between the memory cell transistors MC adjacent in the direction of the word line can be inhibited. It is further possible to inhibit a parasitic MOS transistor using the element isolation insulating film  180  as a gate insulating film from being formed in a region where each control gate electrode  120  as a part of the word line WL and the element isolation insulating film  180  meet and increase a field inversion voltage.  
         [0101]     Selective formation of an SOI structure in the memory cell region  10  of the ordinary semiconductor substrate  30  eliminates the need to significantly change a design environment, unlike a case where a NAND-type flash memory is formed on an SOI substrate. Accordingly, development efficiency can be improved correspondingly. In this case, it is possible to ensure continuity with the specification of a conventional NAND-type flash memory formed on the semiconductor substrate.  
         [0102]     Since the transfer transistor FT formed in the peripheral circuit region  20  performs data erase and write operations for the memory cell transistor MC, a high voltage is applied to the transfer transistor FT. Accordingly, if an SOI structure is formed in the peripheral circuit region  20 , so-called floating body effects occur due to an applied high voltage, and punch-through becomes more likely to occur.  
         [0103]     If no SOI structure is formed in the peripheral circuit region  20  like this embodiment, punch-through can be suppressed, and the transistor characteristics of the transfer transistor FT formed in the peripheral circuit region  20  can be improved. In this case, even if a high electrostatic voltage is applied to the transfer transistor FT, no holes are accumulated in each floating body, like a case where an SOI structure is formed. Accordingly, occurrence of electrostatic discharge (ESD) can be inhibited correspondingly.  
       (2) Second Embodiment  
       [0104]      FIG. 13  shows the configuration of a part of a memory cell region  500  of a NAND-type flash memory according to a second embodiment of the present invention. Note that the same reference numerals denote the same components as those shown in FIGS.  1 (A) and  1 (B) and that an explanation thereof will be omitted.  
         [0105]     In this embodiment, a buried insulating film  510  is selectively formed in a memory transistor formation region  10 A except a part of a region where a floating body  60  of a selection transistor STD is formed and a part of a region where the floating body  60  of a selection transistor STS is formed.  
         [0106]     With this configuration, not only a pair  150  of source and drain regions formed in each of contact plug formation regions  10 B of a semiconductor layer  50  but also a part of the floating body  60  of the selection transistor STD and a part of that of the selection transistor STS are formed to be connected to a semiconductor substrate  30 .  
         [0107]     As described above, according to this embodiment, a backgate bias can be applied to each of the selection transistors STD and STS by applying a predetermined voltage to the semiconductor substrate  30 . This makes it possible to improve the cutoff characteristics of the selection transistors STD and STS.  
         [0108]     Since the area of a part of a bottom surface of the semiconductor layer  50  which is in contact with the semiconductor substrate  30  increases, the mechanical strength of the semiconductor layer  50  when removing a silicon germanium layer by wet etching (FIGS.  9 (A) to  9 (D)) can be increased. This makes it possible to inhibit collapse of the semiconductor layer  50  arranged above cavities formed by removing the silicon germanium layer and generation of dust. Accordingly, yields can be increased.  
         [0109]     According to this embodiment, the same effects as those of the first embodiment can be obtained. More specifically, an SOI structure can be selectively formed in the memory cell region  500  of the ordinary semiconductor substrate  30  without using an SOI substrate. This makes it possible to improve memory cell characteristics while keeping production costs low.  
       (3) Third Embodiment  
       [0110]      FIG. 14  shows the configuration of a part of a memory cell region  520  of a NAND-type flash memory according to a third embodiment of the present invention. Note that the same reference numerals denote the same components as those shown in FIGS.  1 (A) and  1 (B) and that an explanation thereof will be omitted.  
         [0111]     In this embodiment, a buried insulating film  530  is selectively formed in a region of a memory transistor formation region  10 A where a floating body  60  is formed such that the buried insulating film  530  corresponds to the floating body  60 . With this configuration, pairs  150  of source and drain regions formed in a semiconductor layer  50  are all formed to be connected to a semiconductor substrate  30 .  
         [0112]     As described above, according to this embodiment, the area of a part of a bottom surface of the semiconductor layer  50  which is in contact with the semiconductor substrate  30  becomes larger than that in the second embodiment. Thus, the mechanical strength of the semiconductor layer  50  when removing a silicon germanium layer by wet etching (FIGS.  9 (A) to  9 (D)) can be further increased. This makes it possible to inhibit collapse of the semiconductor layer  50  arranged above cavities formed by removing the silicon germanium layer and generation of dust. Accordingly, yields can be increased.  
         [0113]     According to this embodiment, the same effects as those of the first embodiment can be obtained. More specifically, an SOI structure can be selectively formed in the memory cell region  520  of the ordinary semiconductor substrate  30  without using an SOI substrate. This makes it possible to improve memory cell characteristics while keeping production costs low.  
       (4) Fourth Embodiment  
       [0114]      FIG. 15  shows the configuration of a part of a memory cell region  540  of a NAND-type flash memory according to a fourth embodiment of the present invention. Note that the same reference numerals denote the same components as those shown in FIGS.  1 (A) and  1 (B) and that an explanation thereof will be omitted.  
         [0115]     In this embodiment, a pair  550  of N-type source and drain regions is selectively formed on a surface portion of a semiconductor substrate  30  such that the pair  550  of N-type source and drain regions is in contact with a pair  150  of source and drain regions formed in each of contact plug formation regions  10 B of a semiconductor layer  50 .  
         [0116]     Each contact plug formation region  10 B of the semiconductor layer  50  is formed by epitaxially growing the semiconductor substrate  30 . Accordingly, in the contact plug formation region  10 B, a lattice mismatch (crystal misalignment) or crystal defect may occur at an interface between the semiconductor layer  50  and the semiconductor substrate  30 . If a depletion layer is formed at the interface between the semiconductor layer  50  and the semiconductor substrate  30  due to occurrence of a lattice mismatch or crystal defect, a leak current disadvantageously occurs between the semiconductor layer  50  and the semiconductor substrate  30 .  
         [0117]     In contrast, according to this embodiment, each of the interfaces between the semiconductor layer  50  and the semiconductor substrate  30  in the contact plug formation region  10 B is covered with the pair  550  of source and drain regions, and thus no depletion layer is formed at the interface. This makes it possible to inhibit occurrence of a leak current between the semiconductor layer  50  and the semiconductor substrate  30  in each contact plug formation region  10 B.  
         [0118]     According to this embodiment, the same effects as those of the first embodiment can be obtained. More specifically, an SOI structure can be selectively formed in the memory cell region  540  of the ordinary semiconductor substrate  30  without using an SOI substrate. This makes it possible to improve memory cell characteristics while keeping production costs low.  
       (5) Fifth Embodiment  
       [0119]      FIG. 16  shows the configuration of a part of a memory cell region  560  of a NAND-type flash memory according to a fifth embodiment of the present invention. Note that the same reference numerals denote the same components as those shown in FIGS.  1 (A) and  1 (B) and that an explanation thereof will be omitted.  
         [0120]     In this embodiment, an N-type floating body  570  is formed. A depression-type memory cell transistor is used as a memory cell transistor MC.  
         [0121]     This configuration reduces a gate threshold voltage. Accordingly, if a voltage applied to a control gate electrode  120  is the same, a cell current increases. This makes it possible to increase noise tolerance and improve the reliability of memory cell operation.  
         [0122]     According to this embodiment, the same effects as those of the first embodiment can be obtained. More specifically, an SOI structure can be selectively formed in a memory cell region  560  of an ordinary semiconductor substrate  30  without using an SOI substrate. This makes it possible to improve memory cell characteristics while keeping production costs low.  
         [0123]     Note that the above-described embodiments are merely examples and not intended to limit the present invention. More specifically, although a NAND-type flash memory is manufactured as a flash memory, any other flash memory having a structure in which a floating gate electrode and a control gate electrode are stacked, such as a NOR-type or AND-type one, may be manufactured instead.  
         [0124]     A manufacturing method for a NAND-type flash memory according to another embodiment will be explained with reference to FIGS.  17 (A) to  32 (B).  
         [0125]     Note that FIGS.  17 (A),  19 (A),  21 (A),  23 (A),  25 (A),  27 (A),  29 (A), and  31 (A) show plan views of a memory cell region  600  in an element as seen from above, specific to respective steps of the manufacturing method and that FIGS.  17 (B),  19 (B),  21 (B),  23 (B),  25 (B),  27 (B),  29 (B), and  31 (B) show longitudinal sectional views of the memory cell region  600  in the element taken along lines A-A, specific to the respective steps.  
         [0126]     FIGS.  21 (C),  23 (C),  25 (C),  27 (C), and  29 (C) show transverse sectional views of the memory cell region  600  taken along lines B-B, and FIGS.  21 (D),  23 (D),  25 (D),  27 (D), and  29 (D) show transverse sectional views of the memory cell region  600  taken along lines C-C.  
         [0127]     FIGS.  18 (A),  20 (A),  22 (A),  24 (A),  26 (A),  28 (A),  30 (A), and  32 (A) show plan views of a peripheral circuit region  610  in the element as seen from above, specific to the respective steps, and FIGS.  18 (B),  20 (B),  22 (B),  24 (B),  26 (B),  28 (B),  30 (B), and  32 (B) show longitudinal sectional views of the peripheral circuit region  610  taken along lines A-A.  
         [0128]     As shown in FIGS.  17 (A) and  17 (B) and FIGS.  18 (A) and  18 (B), a silicon germanium (SiGe) layer  630  with a germanium (Ge) concentration of, e.g., 30% is formed as a layer to be removed all over a semiconductor substrate  620  to a thickness of, e.g., about 25 nm by epitaxial growth technique.  
         [0129]     A silicon (Si) layer  640  is formed all over the silicon germanium layer  630  to a thickness of about 20 nm by epitaxial growth technique, and then, a silicon nitride (SiN) film  650  is formed all over the silicon layer  640 .  
         [0130]     The silicon nitride film  650  is patterned by lithography and RIE. With this operation, in the memory cell region  600 , parts of the silicon nitride film  650  which are formed in a bit line contact plug formation region  600 B and in, of element isolation insulating film formation regions, element isolation insulating film formation regions (to be referred to as support unit formation regions hereinafter)  600 C arranged at predetermined intervals in the direction of a word line WL are removed, and in the peripheral circuit region  610 , a part of the silicon nitride film  650  which is formed therein is removed.  
         [0131]     Note that a support unit for supporting the silicon layer to be formed on the silicon germanium layer  630  later is formed in each support unit formation region  600 C, as in the bit line contact plug formation region  600 B. A CVD oxide film  655 , for example, is then deposited all over the silicon nitride film  650 , and the CVD oxide film  655  is partially removed by RIE such that parts thereof are left on sidewalls of the silicon nitride film  650 .  
         [0132]     As shown in FIGS.  19 (A) and  19 (B) and FIGS.  20 (A) and  20 (B), the silicon layer  640  and silicon germanium layer  630  are sequentially etched using the silicon nitride film  650  and CVD oxide film  655  as masks, thereby exposing a surface of the semiconductor substrate  620 .  
         [0133]     After the silicon nitride film  650  and CVD oxide film  655  are removed, a silicon layer  660  is formed all over the semiconductor substrate  620  and silicon layer  640  to, e.g., a thickness of 30 nm by epitaxial growth technique.  
         [0134]     Note that at this time, the silicon layer  640  is used as a seed in a transistor formation region  600 A of the memory cell region  600  except the support unit formation regions  600 C and that the semiconductor substrate  620  is used as a seed in each of the contact plug formation region  600 B and support unit formation regions  600 C of the memory cell region  600  and the peripheral circuit region  610 .  
         [0135]     As shown in FIGS.  21 (A) to  21 (D) and FIGS.  22 (A) and  22 (B), a mask material  670  composed of, e.g., a silicon nitride film is deposited all over the silicon layer  660  and then patterned by lithography and RIE. With this operation, parts of the mask material  670  are left in regions which are to serve as element regions later.  
         [0136]     As shown in FIGS.  23 (A) to  23 (D) and FIGS.  24 (A) and  24 (B), a CVD-BSG film  672 , for example, is deposited all over the surface, and the CVD-BSG film  672  is partially removed by RIE such that parts thereof are left on sidewalls of the mask material  670 . At this time, one of the parts of the CVD-BSG film  672  is also left on sidewalls of the part of the mask material  670  formed in the peripheral circuit region  610 . After that, a photoresist is applied to the parts of the mask material  670  and those of the CVD-BSG film  672 , and exposure and development are performed. With this operation, a resist mask  674  having a pattern corresponding to the support unit formation regions  600 C is formed.  
         [0137]     As shown in FIGS.  25 (A) to  25 (D) and FIGS.  26 (A) and  26 (B), the parts of the CVD-BSG film  672  formed in element isolation insulating film formation regions  600 D (the element isolation insulating film formation regions except the support unit formation regions  600 C) are removed by, e.g., HF (hydrofluoric acid) vapor using the resist mask  674  and the parts of the mask material  670  as masks.  
         [0138]     The silicon layer  660  and silicon germanium layer  630  are sequentially etched using the resist mask  674  and the parts of the mask material  670  as masks, thereby forming trenches  680 . At this time, side surfaces of the silicon germanium layer  630  are exposed at an inner surface of each trench  680 .  
         [0139]     The semiconductor substrate  620  is immersed in a predetermined etching solution. The silicon germanium layer  630  exposed at the inner surfaces of the trenches  680  is etched by wet etching and removed. Note that examples of the etching solution to be used here include SH (a mixed solution of sulfuric acid and hydrogen peroxide) and a mixed solution of TMY and hydrogen peroxide.  
         [0140]     With this operation, cavities  685  are formed in regions from which the formed silicon germanium layer  630  has been removed. In this case, parts of the silicon layer  660  which are formed in the bit line contact plug formation region  600 B and support unit formation regions  600 C serve as support units which support a part of the silicon layer  660  which is formed in the transistor formation region  600 A.  
         [0141]     As shown in FIGS.  27 (A) to  27 (D) and FIGS.  28 (A) and  28 (B), the entire surfaces of the semiconductor substrate  620  and silicon layer  660  are oxidized. With this operation, a silicon oxide film  682  is formed on the inner surface of each trench  680 , and the cavities  685  are filled with buried insulating films  684 , each composed of a silicon oxide film. As described above, an SOI structure is selectively formed in the transistor formation region  600 A of the memory cell region  600 .  
         [0142]     As shown in FIGS.  29 (A) to  29 (D) and FIGS.  30 (A) and  30 (B), the silicon layer  660 , silicon oxide films  682 , and semiconductor substrate  620  are sequentially etched using the parts of the mask material  670  as a mask, thereby forming element isolation trenches  690 . Note that in this case, ones of the element isolation trenches  690  which are formed in the element isolation insulating film formation regions  600 D (the element isolation insulating film formation regions except the support unit formation regions  600 C) are deeper by the depth of each trench  680  than ones which are formed in the support unit formation regions  600 C. Each element isolation trench  690  is filled with, e.g., a silicon oxide film by CVD, and the silicon oxide film is planarized, thereby forming an element isolation insulating film  700 . After that, the mask material  670  is removed.  
         [0143]     As shown in FIGS.  31 (A) and  31 (B) and FIGS.  32 (A) and  32 (B), in the memory cell region  600 , a floating gate electrode  720  is formed above the silicon layer  660  via a tunnel insulating film  710 , and a control gate electrode  740  is formed above the floating gate electrode  720  via an interelectrode insulating film  730 . After that, a silicide  750  is formed on the control gate electrode  740 . In the peripheral circuit region  610 , after a gate electrode  770  is formed above the silicon layer  660  via a gate insulating film  760 , a silicide  780  is formed on the gate electrode  770 .  
         [0144]     After that, although not shown, pairs of source and drain regions are formed by ion implantation, and an interlayer insulating film is formed all over the silicon layer  660  by CVD. A source line contact plug and a source line are formed, and a bit line contact plug and a bit line are formed in sequence. In this manner, the NAND-type flash memory is manufactured.  
         [0145]     As described above, according to this embodiment, the part of the silicon layer  660  formed in the bit line contact plug formation region  600 B and the parts of the silicon layer  660  formed in the support unit formation regions  600 C serve as the support units, which support the part of the silicon layer  660  formed in the transistor formation region  600 A.  
         [0146]     Therefore, the mechanical strength of the silicon layer  660  when removing the silicon germanium layer  630  by wet etching (FIGS.  25 (A) to  25 (D)) can be made higher than that in the first embodiment. This makes it possible to inhibit collapse of the silicon layer  660  arranged above the cavities  685  formed by removing the silicon germanium layer  630  and generation of dust. Accordingly, yields can be increased.  
         [0147]     According to this embodiment, the same effects as those of the first embodiment can be obtained. More specifically, an SOI structure can be selectively formed in the memory cell region  600  of the ordinary semiconductor substrate  620  without using an SOI substrate. This makes it possible to improve memory cell characteristics while keeping production costs low.