Abstract:
In a semiconductor device having a signal line on which a voltage higher than the voltage supply is generated, a conductive layer following the potential variance of the voltage supply is positioned under an insulating film directly below the signal line in order to make the level of the signal line follow the potential variance of the voltage supply.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a semiconductor device, and especially relates to a semiconductor device comprising a signal line in which a voltage higher than the voltage supply is generated. 
     2. Description of the Prior Art 
     Recently, the voltage supply V CC  of a dynamic RAM (Random Access Memory) using MOS transistors has been lowered by degrees, and is in general V CC  =5 V. However, the electric charge accumulated in the memory cell in the case of V CC  =5 V is less than that in the case of V CC  =12 V or another higher voltage. Accordingly, the charging condition in the memory cell in the case of V CC  =5 V is disadvantageous for carrying out a refresh action and is apt to be influenced by α-rays and so on, and therefore it becomes necessary to generate a voltage higher than the voltage supply V CC  at the signal line by using a bootstrap circuit, a push-up circuit, or another type of circuit in order to utilize the V CC  level as much as possible. 
     A dynamic RAM semiconductor device in which a push-up circuit is used for the above-mentioned purpose is illustrated in FIG. 1. As illustrated in FIG. 1, this device has a push-up circuit PU, a precharger circuit PRE for the pair of bit lines BL and BL  which are driven by the output of the push-up circuit PU, and the sense amplifier circuit SA for the memory cells. FIG. 2 illustrates various voltage waveforms used to explain the operation of the push-up circuit PU of FIG. 1. 
     The push-up circuit PU consists of transistors Q 1  and Q 2 , a push-up capacitor C 1  and an output signal line S 1  as illustrating in FIG. 1. A clock signal φ 1  is applied as an input to the gate of the transistor Q 1  and another clock signal φ 2  is applied to the gate of the transistor Q 2 . As illustrated in FIG. 2, at first, the clock φ 1  is at the L(low) level and the clock φ 2  is at the H(high) level so that the transistor Q 1  is OFF and the transistor Q 2  is ON; therefore, the level of the output signal line S 1  is kept at the L level (V SS ). Then, the clock φ 2  falls to the L level to turn off the transistor Q 2  ; after that, the clock φ 1  rises to the H level (higher than V CC ) to fully turn on the transistor Q 1  so that the signal line S 1  is charged up to the V CC  level. Under this condition, the clock φ 1  falls to the L level to turn off the transistor Q 1 , and therefore the signal line S 1  is cut off from the voltage supply line V cc . Then, the clock φ 3  rises from the L level (V SS ) to the H level (V CC ) so that the level of the signal line S 1  is pushed up to a level V S1  higher than the voltage supply V CC  through the capacitor C 1 . 
     This voltage level V S1  of the signal line S 1  is applied as an input to the precharger circuit PRE. As illustrated in FIG. 1, the precharger circuit PRE consists of transistors Q 3 , Q 4  and Q 5 . The signal line S 1  is connected to all the gates of the transistors Q 3 , Q 4  and Q 5 . The drains of the transistors Q 3  and Q 4  are connected to the voltage supply V CC , and the sources of the transistors Q 3  and Q 4  are connected to the pair of bit lines BL and BL, respectively. The drain and source of the transistor Q 5  are connected to the pair of bit lines BL and BL, respectively. 
     The sense amplifier circuit SA consists of transistors Q 6 , Q 7  and Q 8  as illustrated in FIG. 1. The drain of the transistor Q 6  and the gate of the transistor Q 7  are both connected to one line BL of the pair of bit lines, and the gate of the transistor Q 6  and the drain of the transistor Q 7  are both connected to another line BL of the pair of bit lines. The sources of the transistors Q 6  and Q 7  are both connected to the drain of the transistor Q 8 , and the source of the transistor Q 8  is connected to the reference voltage V SS . The clock signal φ 4  is applied to the gate of the transistor Q 8 . 
     Transistors Q 9 , Q 9  &#39; . . . of the memory cells MC corresponding to the word lines WL 1 , WL 1  &#39; . . . are all connected to one line BL of the pair of bit lines, and transistors Q 10 , Q 10  &#39; . . . of the memory cells MC corresponding to the word lines WL 2 , WL 2  &#39; . . . are all connected to another line BL of the pair of bit lines. For example, if the content of the memory cell MC including the transistor Q 9  is &#34;1&#34; and the word line WL 1  is selected, when the clock φ 4  rises from the L level to the H level to turn on the transistor Q 8 , the sense amplifier circuit SA operates to turn off the transistor Q 6  and to turn on the transistor Q 7  so that the levels of the pair of bit lines are BL=H and BL=L. And if the content of the above-mentioned memory cell MC is &#34;0&#34;, then the circuit SA operates to turn on the transistors Q 6   and to turn off the transistor Q 7  so that the levels of the pair of bit lines are BL=L and BL=H. 
     In the sense amplifier circuit SA, preceding the above-mentioned sense action, it is necessary to precharge the pair of bit lines BL and BL so as to make the potentials of the pair of bit lines BL and BL equal to each other. In order to do so, when the clock φ 1  rises to the H level as illustrated in FIG. 2, the gate voltages of the transistors Q 3 , Q 4  and Q 5  rise to the V CC  level through the signal line S 1  and the pair of bit lines BL and BL are charged up from the voltage supply V CC  through the transistors Q 3  and Q 4 , respectively. The transistor Q 5  is connected between the pair of bit lines BL and BL, and it becomes conductive in order to make the potentials of the pair of bit lines BL and BL equal to each other. However, in the above-mentioned condition, the level of the signal line S 1  is nearly equal to the voltage supply V CC  so that the transistors Q 3  , Q 4  and Q 5  are not turned on fully, and therefore the potentials of the pair of bit lines BL and BL are lower than V CC  and are not completely equal to each other. Then, when the clock φ 1  falls to the L level and the clock φ 3  rises to the H level, the level of the signal line S 1  rises from V CC  to V S1  higher than V CC  so that the transistors Q 3 , Q 4  and Q 5   are fully turned on and the pair of bit lines BL and BL are both charged up to the voltage supply level V CC . 
     By the way, the level V S1  of the signal line S 1  is determined not only by the voltage supply V CC  and the level V.sub.φ3 of the clock φ 3  (in this case, V.sub.φ3 =V CC ) but is also determined by the push-up capacitor C 1 , the capacitor C 2 , which is formed along the wiring path of the signal line S 1 , and the capacitance C 3  at the gates of the transistors Q 3 , Q 4  and Q 5 . Thus, the level V S1  of the signal line S 1  is expressed by the following equation: ##EQU1## In order to charge up the pair of bit lines BL and BL to the voltage supply level V CC , it is necessary that the second term of the right side of the equation (1) be greater than the threshold voltage V th  of the transistors Q 3 , Q 4  and Q 5 . 
     However, even if the condition V S1  ≧V CC  +V th  is fulfilled in the case of V CC  =5 V and the pair of bit lines BL and BL are both charged up to the voltage supply level V CC , the voltage supply V CC  may rise from 5 V to 5.5 V (V CC  +ΔV CC ) after that. In such a case, the value of &#34;V CC  &#34; in the equation (1) will remain 5 V because at this time the clock φ 1  has already fallen enough so that the transistor Q 1  is turned off. Accordingly, the response of the level of the signal line S 1  to the variance of the voltage supply V CC  depends mainly on the dependence of the clock φ 3  upon the voltage supply V CC . An increase in the level of the signal line S 1  can be expressed by the following equation: ##EQU2## 
     Therefore, even if the clock φ 3  directly follows the variance of the voltage supply V CC , the level of the signal line S 1  may increase only a little compared with the increase of V CC , especially if the capacitor C 2  is relatively large (that is, the path of the signal line S 1  is long). Therefore, if the voltage supply V CC  is changed, it may be that the level V S1  of the signal line S 1  cannot be higher than the required level (V CC  +V th ). In such a case, the short-circuit between the pair of bit lines BL and BL through the transistor Q 5  is insufficient so that the sense amplifier circuit SA may make an error. 
     In addition to the voltage supply V CC , the potentials of the electrodes X adjacent the signal line S 1  forming the capacitor C 2  might be thought of as another factor in relation to the response of the level V S1  of the signal line S 1 . In the semiconductor device of the prior art, the signal line S 1  is formed to run the shortest path between the push-up circuit PU and the precharger circuit PRE, and therefore the adjacent electrodes along the path of the signal line S 1  may be locally adjacent the ground line V SS , the semiconductor substrate itself, the other signal line, the node in the circuit or the voltage supply line V CC . However, the proportion of the path of the signal line S 1  adjacent the voltage supply V CC  is generally small, and the potential of the adjacent electrode X as a whole could be thought of as being other than the voltage supply V CC . Accordingly, in the semiconductor device of the prior art, improvement of the response of the level V S1  to V.sub. CC according to the adjacent electrode X can not be expected. 
     Thus, as described above, when the voltage supply V CC  increases by ΔV CC , the increase of the level V S1  of the signal line S 1  is only ΔV S1  in the equation (2), and therefore it is difficult to push up the level V S1  to a level higher than (V CC  +V th ) after V CC  has increased even if the clock φ 3  increases by ΔV CC . 
     SUMMARY OF THE INVENTION 
     The main object of the present invention is to solve the above-mentioned problem of the semiconductor device of the prior art, and to provide a semiconductor device which can operate stably even when the voltage supply varies by shielding the signal line generating a voltage higher than the voltage supply with the voltage supply line. 
     In accordance with the present invention, there is provided a semiconductor device which includes a signal generating circuit in which the output terminal of the signal generating circuit is cut off from the voltage supply line and an output signal higher than the voltage supply is generated at the output terminal, a signal line layer connected to the output terminal, and a transistor, the gate of which is connected to the signal line layer and the drain of which is connected to the voltage supply line at least after the output terminal is cut-off from the voltage supply line, characterized in that the semiconductor device also includes means for following the voltage supply, which means makes the potential of the signal line layer follow the potential variance of the voltage supply line after the signal line layer is cut-off from the voltage supply line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a circuit diagram of a semiconductor device of the dynamic RAM of a prior art; 
     FIG. 2 illustrates various signal waveforms for explaining the operation of the circuit of FIG. 1; 
     FIGS. 3A and 3B illustrate, respectively, a sectional view and a plan pattern view of a semiconductor device in accordance with one embodiment of the present invention; 
     FIG. 4 illustrates an equivalent circuit diagram of the semiconductor device of FIGS. 3A and 3B; and 
     FIGS. 5A and 5B illustrate, respectively, a sectional view and a plan pattern view of a semiconductor device in accordance with another embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A semiconductor device in accordance with one embodiment of the present invention is illustrated in FIGS. 3A and 3B. FIG. 3A illustrates a principal sectional view of the above-mentioned semiconductor device and FIG. 3B illustrates a plan pattern view of the device. 
     The semiconductor device of FIGS. 3A and 3B comprises a p-type silicon semiconductor substrate 1, a silicon dioxide (SiO 2 ) layer 2 on the surface of the substrate 1, a polycrystal silicon layer 3 formed on the SiO 2  layer 2, a phosphosilicate glass (PSG) layer 4 for insulating between layers formed on the polycrystal silicon layer 3, aluminum (Al) wiring layers 5a and 5b upon the PSG layer 4, and a PSG layer 6 for covering the surface of the device. 
     The Al wiring layer 5b is a voltage supply (V CC ) line and is connected through the contact hole 7 to the polycrystal silicon layer 3, which is also used as a voltage supply line. The other Al wiring layer 5a is a signal line S 1 . 
     As illustrated in FIG. 3A, the polycrystal silicon layer 3 is arranged to be laid under the Al wiring layer 5A with the insulating PSG laywer 4 between them as much as possible, in order to increase the capacitance formed by the polycrystal silicon layer 3 and the Al wiring layer 5a. There are two ways to arrange the polycrystal silicon layer 3 as described above. One way is to change the wiring pattern of the Al wiring layer 5A so that the path of the Al wiring layer 5A runs on the area under which the polycrystal silicon layer 3 is formed with the insulating PSG layer 4 thereupon. The other way is to change the layout pattern of the polycrystal silicon layer 3 so that the polycrystal silicon layer 3 is laid under the Al wiring layer 5a with the insulating PSG layer 4 between them. In accordance with the embodiment of FIG. 3A, the latter way is adopted. The pattern of the Al wiring layer 5A is not changed and the polycrystal silicon layer 3 is formed under the Al wiring layer 5a with the insulating PSG layer 4 between them, even though the layer 3 is not necessary there, from the viewpoint of other circuit pattern design requirements. 
     FIG. 4 illustrates an equivalent circuit diagram of the signal line S 1  of the semiconductor device of FIG. 3A. According to the semiconductor device of FIG. 3A, the electrodes adjacent the signal line S 1  mainly have the potential of the voltage supply V CC , and the portions of the signal line S 1  adjacent the potentials other than the voltage supply V CC  are considered to be negligibly small. Accordingly, the potential at one side of the capacitor C 2  which is formed along the path of the signal line S 1 , is considered to be the voltage supply V CC  as simplified. 
     In the circuit of FIG. 4, when the clocks φ 1 , φ 2   and φ 3  are changed as illustrated in FIG. 2, the level V S1  of the signal line S 1  is expressed by the above-mentioned equation (1). If, after the clock φ 1  falls to the L level to cut off the signal line S 1  from the voltage supply line V CC , the voltage supply V CC  rises by ΔV CC , the level V S1  of the signal line S 1  is pushed up not only by the clock φ 3  through the capacitor C 1  but also by the voltage supply itself through the capacitor C 2 . Therefore, the level V S1  of the signal line S 1  would increase by ΔV S1  as expressed by the following equation: ##EQU3## 
     As described above, in the semiconductor device of FIG. 3A, the level of the signal line S 1  can follow the variance of the voltage supply V CC  even after the signal line S 1  is cut off from the voltage supply line V CC . 
     In addition, a semiconductor in accordance with another embodiment of the present invention is illustrated in FIGS. 5A and 5B. FIG. 5A illustrates a principal sectional vview of the above-mentioned semiconductor device and FIG. 5B illustrates a plan pattern view of the device. In the semiconductor device of FIG. 5A, an N +  -type diffusion layer 8 is formed upon a portion of the surface of the p-type silicon substrate 1, and a PSG layer 4 for insulating between layers is formed upon the silicon dioxide (SiO 2 ) film 9 on the substrate 1 and upon the N +  -type diffusion layer 8. Al wiring layers 5a and 5b for the signal line S 1  and for the voltage supply line V CC , respectively, are formed on the insulating PSG layer 4. A covering PSG layer 6 is formed on the surface of the device. The Al wiring layer 5b is connected to the N +  -type diffusion layer 8 through the contact hole 7. Therefore, a voltage supply wiring layer formed from the N +  -type diffusion layer 8 is provided directly under the Al wiring layer 5a of the signal line S 1  separated by the insulating PSG layer 4 thus forming capacitor C 2 . 
     Furthermore, though the conductive layer under the signal line S 1  is formed as a voltage supply wiring line in the above-mentioned two embodiments, the above-mentioned conductive layer may be formed as a signal line other than the voltage supply line which follows the variance of the voltage supply V CC . However, it is not preferable from the view of the drive capacity of the clock φ 3 , to form the above-mentioned conductive layer as the output signal line of the clock φ 3 . 
     As described above, according to the present invention, by means of extending the voltage supply line or another signal line equivalent to the voltage supply as much as possible under the output signal line of a push-up circuit or another circuit, the above-mentioned output signal line can be shielded equivalently, the level of the output signal line can follow the variance of the voltage supply by the capacitor formed along the output signal line, and the level of the output signal line can be made so that it is difficult for it to be influenced by the variance of the substrate potential.