Abstract:
A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

Description:
PRIORITY CLAIM 
     The present application is a divisional application from U.S. application patent Ser. No. 11/225,876 filed Sep. 12, 2005, which claims priority from French Application for Patent No. 04 09781 filed Sep. 15, 2004, the disclosures of which are hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field of the Invention 
     The present invention relates to memory cells protected against current or voltage spikes, in particular SRAM memory cells. 
     2. Description of Related Art 
     The continuing progressive miniaturization of electronic circuits allows smaller and smaller circuits having an increasingly higher performance to be obtained. On the other hand, these circuits are more and more sensitive to their external environment, and in particular to spurious logic events caused by an input of energy originating from outside of the circuit. 
     A spurious logic event is a localized change of state or a transitional state resulting in a voltage spike and/or a current spike at one point in an integrated circuit. By definition, a spurious event is unpredictable or practically so. Spurious logic events can have different origins. 
     A spurious logic event is, for example, induced by the impact of an energetic charged particle at one point of an integrated circuit. Such a spurious event is known as a ‘Single Event Upset’ or SEU. This type of spurious event appears in integrated circuits employed for applications in space, because of the radiation encountered outside of the protecting atmospheric and magnetospheric layers of the earth. This type of spurious event also occurs more and more frequently in integrated circuits for terrestrial applications, especially for the highest integration level technologies, such as 0.25 micron, 0.18 micron and 0.12 micron technologies and below. 
     A spurious logic event may also be induced by localized capacitive coupling between two layers of the same integrated circuit. This case is often referred to as a “glitch.” 
     Whatever its origin, a spurious event generally results in a voltage and/or a current spike on a digital or analog signal at an affected point in a circuit formed by the point of impact of the energetic particle, in the case of a spurious event of the SEU type. 
     If the equivalent capacitance of the circuit downstream of the affected point is denoted C, the voltage variation ΔV at the affected point being considered can be written ΔV=ΔQ/C, ΔQ being the charge variation resulting from the impact. The voltage variation ΔV is generally of very short duration, much shorter for example than the period of a clock signal controlling the circuit. 
     A spurious event may, or may not, have serious consequences for the downstream circuit that it affects. 
     For example, for a downstream circuit only using logic signals, if the voltage variation ΔV is small enough not to cause a change of state, the interference effect disappears in a reasonably short time, with no consequences for the downstream circuit. This is notably the case when the equivalent downstream capacitance is large or when the charge variation ΔQ is small. 
     On the contrary, if the voltage variation ΔV is larger, and notably if it is large enough to modify the value of a logic signal, then the consequences can be serious. 
     In particular, in the case of an SRAM memory cell, the voltage variation ΔV may reach a level such that the logic level stored in a data storage node is modified, together with the complementary logic level, so that the memory cell finds itself in a different stable state from its initial state prior to the arrival of the cause of interference. 
     Because of the increasing miniaturization of electronic circuits, and in particular of memory cells, the capacitance C of the junctions in which logic information is stored is decreasing, so that the voltage variations generated by the appearance of a spurious logic event often reach the threshold levels beyond which the stored information is modified, even for a small quantity of incident charge. Various methods are currently being used for protecting memory cells against spurious logic events. 
     In this regard, reference may be made to U.S. Pat. No. 5,570,313, the disclosure of which is hereby incorporated by reference, in which redundant data storage nodes are used for storing information in at least one pair of complementary nodes and in which, in order to restore information stored in one node of a pair to its initial state following a spurious event, the information stored in the other node is used. 
     This type of technique is effective for protecting a circuit against a localized spurious logic event, but it is ineffective for providing protection against spurious events affecting two complementary data storage nodes. 
     There is a need in the art to overcome this drawback and to provide a memory cell with improved protection against spurious events. 
     SUMMARY OF THE INVENTION 
     Accordingly, an embodiment of the invention comprises a memory cell protected against current or voltage spikes. A group of redundant data storage nodes store information in at least one pair of complementary nodes. The cell further includes means for restoring information to its initial state following a current or voltage spike modifying the information in one of the nodes of the pair, using the information stored in the other node. 
     According to an embodiment of the invention, the nodes of each pair are implanted on opposite sides from one another within a region of a substrate defining the boundaries of the memory cell. 
     The separation of the redundant nodes thus prevents a spurious event that alters the information contained in one of the nodes of a pair of redundant nodes from modifying the information stored in the other node, so that the altered information can be restored to its initial state. 
     According to another feature of the invention, the nodes of each pair of nodes are separated by a distance that is greater than the diameter of an ionized particle capable of generating a voltage spike. 
     For example, the nodes of each pair are separated from one another by at least 1 micron. 
     According to another feature of the invention, the nodes of each pair are disposed within wells of opposing conductivity types that define junctions isolating the nodes. The resistance of the memory cell to spurious logic events is thus further improved. 
     In one embodiment, the memory cell comprises four groups of transistors whose purpose is to control the voltage level of four respective data storage nodes. 
     For example, each group of transistors comprises a first and a second transistor, the first transistor being an MOS transistor of p type and the second transistor being an MOS transistor of n type, the source and the drain of the first transistor being respectively connected to a power supply voltage and to the drain of the second transistor, the source of the second transistor being connected to earth. 
     According to this embodiment, the drain of the first transistor and the gate of the second transistor of the first, second and third groups of transistors are connected to the gate and to the drain of the first transistor of the second, third and fourth groups of transistors, respectively. 
     Furthermore, the gate and the drain of the first transistor of the first group of transistors are connected to the drain of the first transistor and to the gate of the second transistor of the fourth group of transistors, respectively. 
     Lastly, according to this arrangement, the second transistor of the first and second groups of transistors is disposed within a first well of p type, the second transistor of the third and fourth groups of transistors being disposed within a second well of p type. These p-type wells are separated by a well of n type, within which the first transistors of the first, second, third and fourth groups of transistors are implanted. 
     In accordance with an embodiment of the invention, a memory cell comprises a pair of true data storage nodes and a pair of false data storage nodes. The true data storage nodes are separated by a distance that is greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell, and the false data storage nodes are separated by a distance that is greater than a diameter of an ionized particle capable of generating a current or voltage spike in the cell. 
     In accordance with another embodiment, a memory cell comprises a pair of true data storage nodes at the gate terminals of first and second transistors and a pair of false data storage nodes at the gate terminals of third and fourth transistors. The first and second transistors for the true data storage nodes are implanted in different wells of a first conductivity type, and the third and fourth transistors for the false data storage nodes are implanted in different wells of the first conductivity type. 
     In accordance with yet another embodiment, an integrated circuit memory comprises a semiconductor substrate including a region for a memory cell. A plurality of transistors are formed in a center area of the region. The memory cell includes first and second transistors associated with a pair of true data storage nodes and third and fourth transistors associated with a pair of false data storage nodes. The first and second transistors are formed in the region on opposite sides of the center area and the third and fourth transistors are formed in the region on opposite sides of the center area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the method and apparatus of the present invention may be acquired by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein: 
         FIG. 1  illustrates an operational block diagram of an SRAM cell; and 
         FIG. 2  illustrates a physical embodiment, according to the invention, of the SRAM cell in  FIG. 1  that improves its protection against spurious events. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An example of electronic circuit diagram of an SRAM memory cell protected against current or voltage spikes is shown in  FIG. 1 . Such a cell is fabricated according to the teachings of U.S. Pat. No. 5,570,313, which has already been mentioned. 
     As can be seen in  FIG. 1 , this memory cell comprises four groups of transistors E 1 , E 2 , E 3  and E 4  whose purpose is to control the voltage level of four respective data storage nodes N 1 , N 2 , N 3  and N 4 . 
     Each group of transistors comprises one p-type MOS transistor and one n-type MOS transistor of n type. 
     Thus, the SRAM memory cell comprises four p-type MOS transistors, namely MP 1 , MP 2 , MP 3  and MP 4 , and four n-type MOS transistors, namely MN 1 , MN 2 , MN 3  and MN 4 . 
     The source of each of the transistors MP 1 , MP 2 , MP 3  and MP 4  is connected to a DC voltage source Vdd, for example equal to 1.2 volts, and the source of the transistors MN 1 , MN 2 , MN 3  and MN 4  is connected to an earth/ground connection circuit Vss. The drain d of each p-type MOS transistor of a group i of transistors Ei (i=1, 2, 3, 4) is connected to the drain of the corresponding n-type MOS transistor MNi. 
     As far as the groups of transistors E 1 , E 2 , E 3 , E 4  are concerned, the nodes between the p-transistors and the n-transistors, respectively named N 4 , N 1 , N 2 , N 3 , are respectively connected to the gates of the p-MOS transistors of the groups E 2 , E 3 , E 4  and E 1  and to the gates of the n-MOS transistors of the groups E 4 , E 1 , E 2 , E 3 . 
     As previously indicated, the nodes N 1 , N 2 , N 3  and N 4  used for storing logic information are connected to the gates of the n-type MOS transistors MN 1 , MN 2 , MN 3  and MN 4 , respectively. 
     As can be seen in  FIG. 1 , the access to these nodes N 1 , N 2 , N 3  and N 4  is effected by means of access transistors MR 1 , MR 2 , MR 3  and MR 4 . The purpose of these transistors is for writing data received from BLT and BLF, but also for reading the logic data stored in these nodes, although other read circuits may also be used. 
     Indeed, the drain d of each of the transistors MR 1 , MR 2 , MR 3  and MR 4  is connected to the gate of the transistors MN 1 , MN 2 , MN 3  and MN 4 . The source of the transistors MR 1 , MR 2 , MR 3  and MR 4  receives data inputs from BLT and BLF. 
     The input BLT is connected to the source of the transistors MR 2  and MR 4 , while the input BLF is connected to the source of the transistors MR 1  and MR 3 . The clock signal H supplies the gate of these access transistors MR 1 , MR 2 , MR 3  and MR 4 . 
     This arrangement allows, on the one hand, the same data BLT to be written in the nodes N 2  and N 4 , and on the other, the same data BLF to be written in the nodes N 1  and N 3 . 
     The operational principle of this memory cell protected against spurious current and/or voltage events will now be illustrated in the light of an example of interference events, formed by an ionic impact caused at the junction of the transistor MN 1 , that is large enough to bring about a modification of the stored information. For example, the “1”, “0”, “1” and “0” data are respectively stored in the nodes N 1 , N 2 , N 3  and N 4 . If an interference event appears on the node N 1  that results in a transient negative voltage spike, the consequent voltage drop on the gate of the transistor MN 1  causes this transistor to turn off. On the contrary, this interference event causes the p-type MOS transistor MP 3  to start conducting. However, the voltage at the node N 2  is held at zero by the transistor MN 3 . The transistor MP 4  is therefore maintained in a conducting state, so that the transistor MP 1  remains off and the voltage on the node N 4  is unaltered. Similarly, the logic level stored in the node N 3  is not modified. 
     In parallel, the logic level of the node N 1  is restored by means of the transistor MP 2 . 
     The arrangement that has just been described allows a logic level stored in a node to be restored following interference generated by a spurious event. The storage of information in redundant data storage nodes also allows this information to be recovered as long as only one of the two nodes is affected. Indeed, if a spurious event manages to simultaneously affect the two nodes N 1  and N 3 , on the one hand, and N 2  and N 4 , on the other, then the information recovered becomes erroneous. 
       FIG. 2  shows an exemplary embodiment that prevents the possibility of a spurious event simultaneously altering two complementary nodes of a pair of nodes, in which information is redundantly stored. 
     The embodiment shown in  FIG. 2  corresponds to the electronic circuit diagram of the cell in  FIG. 1 . 
       FIG. 2  shows the layers of a material that is deposited on a semiconductor substrate in order to form the various elements of the circuit in  FIG. 1 . The technique for fabricating these elements is available to those skilled in the art and hence will not be described in detail in the following. 
     It will, however, be noted that the various transistors used to form the memory cell are formed within three isolated wells, namely a first p-type well C 1  or “p-well”, a second n type well C 2  or “n-well”, and a third p-type well C 3  or “p-well”. 
     As can be seen in  FIG. 2 , the access transistors MR 1  and MR 4 , together with the n type MOS transistors MN 1  and MN 2 , are disposed within the first well C 1 . Similarly, the access transistors MR 2  and MR 3 , together with the n type MOS transistors MN 3  and MN 4 , are formed within the third p-type well C 3 . Finally, the p type MOS transistors MP 1 , MP 2 , MP 3  and MP 4  are fabricated within the central n-type well C 2 . 
     Thus, as is apparent from the above, the MOS transistors of n type are each formed within a p-well well, whereas the MOS transistors of p type are formed within a well of n type. 
     As can be seen in  FIG. 2 , the bit lines BLF and BLT are respectively connected, on the one hand, to the sources of the transistors MR 1  and MR 3 , and on the other, to the sources of the transistors MR 2  and MR 4 , respectively. The clock signal H is connected to the gates of the access transistors MR 1 , MR 2 , MR 3  and MR 4  by means of suitable conducting layers. It can also be seen in this  FIG. 2  that the sources of the transistors MP 1 , MP 2 , MP 3  and MP 4  are connected to a DC power supply source Vdd. 
     As is known, these various connections are effected using appropriately placed conducting layers, connected to vias such as V. 
     In the embodiment according to the invention, the transistor MN 1  and the transistor MN 2 , on the one hand, and the transistors MN 3  and MN 4 , on the other, are placed within wells C 1  and C 3  which are distinct from one another and whose junctions ensure isolation between these transistors. In addition, within each well, the transistors MN 1  and MN 2 , together with the transistors MN 3  and MN 4 , are arranged such that the transistor MN 1  is placed on the opposite side from the transistor MN 3  and such that the transistor MN 2  is also placed on the opposite side from the transistor MN 4  in the region of the substrate where the memory cell is implanted, so that the transistor MN 1  is as far as possible from the transistor MN 3  and that the transistor MN 2  is also as far as possible from the transistor MN 4 . For example, these transistors are thus separated by a distance that is at least equal to 1 micron, so that an ionized particle, whose diameter is typically around 0.6 microns, that affects one of these transistors is prevented from also affecting the other transistor, although shorter distances could also be envisaged. 
     Similarly, the node N 1  is situated as far as possible from the node N 3 , and the node N 2  is also as far as possible from the node N 4 . 
     Thanks to this arrangement, the possibility of an ionized particle simultaneously affecting the nodes N 1  and N 3 , on the one hand, and the nodes N 2  and N 4 , on the other, is avoided. 
     Furthermore, thanks to the formation of the transistors MN 1  and MN 2 , on the one hand, and the transistors MN 3  and MN 4 , on the other, within two p-type wells separated by an n-type well in which the p-type transistors are implanted, the isolation of each pair of redundant data storage nodes is achieved. 
     Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.