Abstract:
A display substrate includes gate lines, driving circuit part, signal lines, connection lines and a contact part. Gate lines are formed on a display area and intersect data lines. Driving circuit part is formed on a peripheral area surrounding the display area and provides a gate signal to the gate lines. Signal lines are formed adjacent to the driving circuit part and provide a driving signal to the driving circuit part. Connection lines include a first end portion overlapped the signal lines and a second end portion electrically connected with the driving circuit part. A contact part is formed on the signal lines and connects the first end portion with the signal lines.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority to Korean Patent Application No. 2006-068523, filed on Jul. 21, 2006, the disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to a display substrate and a display device having the display substrate, and more particularly, to a display substrate having an enhanced display quality. 
         [0004]    2. Discussion of the Related Art 
         [0005]    A liquid crystal display (LCD) device includes a liquid crystal display panel and a driving circuit part providing a driving signal to the liquid crystal display panel. The liquid crystal display panel includes a display area having a plurality of pixels to display an image and a peripheral area surrounding the display area. Each of the pixels includes a gate line and a data line. 
         [0006]    A gate driving circuit is disposed in the peripheral area to provide a gate signal. Technology for integrating the gate driving circuit on the display panel is used to reduce the size of the display panel. The gate driving circuit includes a driving circuit part to generate a gate signal and lines to transmit a driving signal. 
         [0007]    When the gate driving circuit is integrated in the peripheral area, a sealing member is formed on an area corresponding to the gate driving circuit to cover the gate driving circuit. The sealing member can protect the gate driving circuit. 
         [0008]    Since a number of lines increase in response to various driving methods of the gate driving circuit, a margin of the sealing member to cover the gate driving circuit is decreased. Therefore, a reliability of the gate driving circuit may be deteriorated. 
       SUMMARY OF THE INVENTION 
       [0009]    Exemplary embodiments of the present invention provide a transflective liquid crystal display capable of increasing reflectivity, and a panel having the transflective liquid crystal display. 
         [0010]    According to an exemplary embodiment of the present invention, a display substrate includes gate lines, driving circuit part, signal lines, connection lines and a contact part. Gate lines can be formed on a display area and may intersect data lines. Driving circuit part can be formed on a peripheral area surrounding the display area and provides a gate signal to the gate lines. Signal lines can be formed adjacent to the driving circuit part and provide a driving signal to the driving circuit part. Connection lines may include a first end portion overlapping the signal lines and a second end portion electrically connected with the driving circuit part. A contact part can be formed on the signal lines and may connect the first end portion with the signal lines. 
         [0011]    According to an exemplary embodiment of the present invention, a display device includes a display substrate, a sealing member and a counter substrate. The display substrate may include a display area having gate lines and data lines intersecting the gate lines and a peripheral area having a gate driving circuit proving a gate signal to the gate lines. The gate driving circuit may include signal lines transmitting a driving signal, driving circuit part generating a gate signal by using the driving signal, connection lines having a first end portion overtapping the signal lines and a second end portion connected with the driving circuit part and a contact part connecting the first end portion with the signal lines. The sealing member can be formed on the peripheral area to cover the gate driving circuit. The counter substrate can be coupled with the display substrate by the sealing member. A liquid crystal layer can be interposed between the display substrate and the counter substrate. 
         [0012]    According to an exemplary embodiment of the present invention, a gap between signal lines of the gate driving circuit can be reduced so that a sufficient margin of the sealing member can be obtained. Therefore, a reliability of the gate driving circuit can be enhanced by covering the gate driving circuit with the sealing member. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    Exemplary embodiments of the present invention can be understood in more detail from the following descriptions taken in conjunction with the accompanying drawings, in which 
           [0014]      FIG. 1  is a plan view illustrating a display device in accordance with an exemplary embodiment of the present invention; 
           [0015]      FIG. 2  is a block diagram showing a gate driving circuit shown in  FIG. 1  according to an exemplary embodiment of the present invention; 
           [0016]      FIG. 3  shows a layout of the gate driving circuit shown in  FIG. 1 ; 
           [0017]      FIG. 4  is a cross-sectional view taken along the line I-I′ shown in  FIG. 3 ; 
           [0018]      FIG. 5  shows a layout of a gate driving circuit in accordance with an exemplary embodiment of the present invention; 
           [0019]      FIG. 6  is a block diagram showing a gate driving circuit in accordance with an exemplary embodiment of the present invention; 
           [0020]      FIG. 7  shows a layout of the gate driving circuit shown in  FIG. 6 ; 
           [0021]      FIG. 8  is a cross-sectional view taken along the line II-II′ shown in  FIG. 7 ; and 
           [0022]      FIG. 9  shows a layout of a gate driving circuit in accordance with an exemplary embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0023]    The invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. 
         [0024]      FIG. 1  is a plan view illustrating a display device in accordance with an exemplary embodiment of the present invention.  FIG. 2  is a block diagram showing a gate driving circuit shown in  FIG. 1 . 
         [0025]    Referring to  FIG. 1  and  FIG. 2 , a display device includes a display panel  300 . The display panel  300  includes a display substrate  100 , a counter substrate  200 , and a liquid crystal layer (not shown). The display panel  300  includes a display area (DA), a first peripheral area, a second peripheral area, a third peripheral area, and a fourth peripheral area (PA 1 , PA 2 , PA 3 , PA 4 ). The peripheral areas surround the display area (DA). 
         [0026]    The display substrate  100  includes a plurality of pixels in a matrix. Each of the pixels includes a thin film transistor (TFT) connected with a gate line (GA) and a data line (DA) and a pixel electrode (PE). 
         [0027]    A sealing member  50  is formed in the first, second, third, and fourth peripheral areas (PA 1  PA 2 , PA 3 , PA 4 ). The sealing member  50  couples the display substrate  100  with the counter substrate  200 . 
         [0028]    A pad member  110  is formed on the first peripheral area (PA 1 ) to transmit a driving signal to the display panel  300 . The pad member  110  includes a plurality of first pads  111  to receive the driving signal from a flexible printed circuit substrate and a plurality of second pads  113  having a mounted driving chip for outputting a data signal to the data lines (DA) by using the diving signal. 
         [0029]    A first gate driving circuit  140  is formed on the second peripheral area (PA 2 ) to output a gate signal to odd-numbered gate lines of the gate lines (GL). The first gate driving circuit  140  is formed within an area where the sealing member  50  is formed. The first gate driving circuit  140  includes signal lines  120  to transmit the driving signal and a driving circuit part  130  to generate the gate signal. 
         [0030]    A second gate driving circuit  150  is formed on the third peripheral area (PA 3 ) to output a gate signal to even-numbered gate lines of the gate lines (GL). The second gate driving circuit  150  is formed within an area where the sealing member  50  is formed. The second gate driving circuit  150  includes signal lines (not shown) to receive a driving signal and a driving circuit part (not shown) to generate the gate signal. In an embodiment of the present invention, the gate driving circuit may be formed on the second peripheral area (PA 2 ) or the third peripheral area (PA 3 ). 
         [0031]    In an embodiment, the first gate driving circuit  140  includes signal lines  120  and a driving circuit part  130 . The signal lines  120  include a first signal line  121 , a second signal line  122 , a third signal line  123  and a fourth signal line  124 . The first signal line  121  receives a gate off voltage (VOFF) and the second signal line  122  receives a first clock signal (CK). The third signal line  123  receives a second clock signal (CKB) and the fourth signal line  124  receives a vertical start voltage (STV) 
         [0032]    The driving circuit part  130  includes a shift register having a plurality of stages (SRC 1 ˜SRCk+1) connected to one another. The plurality of stages (SRC 1 ˜SRCk+1) includes stages (SRC 1 ˜SRCk) to supply a gate signal and a dummy stage (SRCk+1) to supply a dummy signal. 
         [0033]    Each of the stages includes a power terminal (VG), a first clock terminal (CK 1 ), a second clock terminal (CK 2 ), a first control terminal (CT 1 ), a second control terminal (CT 2 ) and an output terminal (OUT). The power terminal (VG) is connected with the first signal line  121  and receives the gate off voltage (VOFF). The first clock terminal (CK 1 ) is connected with the second signal line  122  and receives the first clock signal (CK). The second clock terminal (CK 2 ) is connected with the third signal line  123  and receives the second clock signal (CKB). 
         [0034]    In an embodiment, with respect to the odd-numbered stages (SRC 2   n− 1), the first clock signal (CK) is supplied to the first clock terminal (CK 1 ) and the second clock signal (CKB) is supplied to the second clock terminal (CK 2 ). With respect to the even-numbered stages (SRC 2   n ), the second cock signal (CKB) is supplied to the first clock terminal (CK 1 ) and the first clock signal (CK) is supplied to the second clock terminal (CK 2 ). Here, n is 1, 2, . . . k/2 wherein k is a multiple of 2. The first clock signal and the second clock signal (CK, CKB) have the same level as that of a gate on voltage (VON) with respect to a high level and the phases of the first and second clock signals are inverted. 
         [0035]    The first control terminal (CT 1 ) receives the vertical start signal (STV) or an output signal of a previous stage and controls a driving start time of the stage (SRC 1 ). The second control terminal (CT 2 ) receives an output signal of a next stage and controls a driving end time of the stage (SRC 1 ). The output terminal (OUT) supplies a gate signal (G 1 ) to a corresponding gate line. 
         [0036]      FIG. 3  shows a layout of the gate driving circuit shown in  FIG. 1 .  FIG. 4  is a cross-sectional view taken along the line I-I′ shown in  FIG. 3 . 
         [0037]    Referring to  FIG. 2  to  FIG. 4 , a gate driving circuit includes signal lines  120 , a driving circuit part  130  having a plurality of stages (SRC 2   n− 1, SRC 2   n ) and connection lines (not shown) electrically connecting the signal lines  120  and the driving circuit part  130 . 
         [0038]    Each of the stages (SRC 2   n− 1) includes a plurality of thin film transistors (TFTs) connected to each other. The TFTs include a gate electrode (GE) comprising a first conductive layer, a source and a drain electrode (SE, DE) comprising a second conductive layer and a channel (CH) comprising, for example, an amorphous layer or polycrystalline layer. 
         [0039]    The signal lines  120  extend in parallel with respect to the stages (SRC 2   n− 1, SRC 2   n ) and transmit driving signals to the stages (SRC 2   n− 1, SRC 2   n ). The signal lines  120  include the first signal line  121  transmitting the gate off voltage (VOFF), the second signal lines  122  transmitting the first cock signal (CK), the third signal line  123  transmitting the second clock signal (CKB) and the fourth clock signal  124  transmitting the vertical start voltage (STV). The signal lines  120  are formed in parallel with and at a predetermined distance from each other. The signal lines  120  comprise the first conductive layer. 
         [0040]    The connection lines include a first connection line  121   a , a second connection line  122   a  and a third connection line  123   a . The connection lines may comprise a second conductive layer insulated from the first conductive layer. Alternatively, when the signal lines  120  comprise the second conductive layer, the connection lines comprise the first conductive layer. 
         [0041]    The first connection line  121   a  comprises an extending portion extending in parallel with respect to the first signal line  121  and diverging portion diverging from each of the stages. The gate off voltage (VOFF) is applied to the first signal line  121  and a portion of the extending portion of the first connection line  121   a  to reduce a signal delay of the gate off voltage (VOFF). The gate off voltage (VOFF) is applied to each of the stages through the diverging portion of the first connection line  121   a.    
         [0042]    For example, the first connection line  121   a  is diverging toward the stage (SRC 2   n− 1) and is connected with the power terminal (VG) of the stage (SRC 2   n− 1). The first signal line  121  is connected with the first connection line  121   a  through a first contact part  121   c.    
         [0043]    The first contact part  121   c  includes a first contact hole (C 1 ), a second contact hole (C 2 ) and a first contact electrode (E 1 ). The first contact hole (C 1 ) exposes the first signal line  121 , and the second contact hole (C 2 ) exposes the first connection line  121   a . The first contact electrode E 1  connects the first signal line  121  with the first connection line  121   a  through the first and second contact holes (C 1 , C 2 ). 
         [0044]    A first end portion of the second connection line  122   a  overtaps the second signal line  122 . A second end portion of the second connection line  122   a  is electrically connected with a first clock terminal (CK 1 ) of the ( 2   n− 1) th  stage (SRC 2   n− 1). The second signal line  122  is electrically connected with the second connection line  122   a  through the second contact part  122   c.    
         [0045]    The second contact part  122   c  includes a third contact hole (C 3 ), a fourth contact hole (C 4 ) and a second contact electrode (E 2 ). The third contact hole (C 3 ) exposes the second signal fine  122  and the fourth contact hole (C 4 ) exposes the first end portion of the second connection line  122   a . The second contact electrode (E 2 ) connects the second signal line  122  with the second connection line  122   a  through the third and fourth contact holes (C 3 , C 4 ). 
         [0046]    The first end portion of the third connection line  123   a  overlaps the third signal line  123 . The second end portion of the third connection line  123   a  is electrically connected with the second clock terminal (CK 2 ) of the ( 2   n− 1) th  stage (SRC 2   n− 1). The third signal line  123  is connected with the third connection line  123   a  through the third contact part  123   c.    
         [0047]    The third contact part  123   c  includes a fifth contact hole (C 5 ), a sixth contact hole (C 6 ) and a third contact electrode (E 3 ). The fifth contact hole (C 5 ) exposes the third signal line  123 , and the sixth contact hole (C 6 ) exposes the first end portion of the third connection line  123   a . The third contact electrode (E 3 ) connects the third signal line  123  with the third connection line  123   a  through the fifth and sixth contact holes (C 5 , C 6 ). 
         [0048]    The first, second and third contact electrodes (E 1 , E 2  and E 3 ) comprise a third conductive layer. In an embodiment, the third conductive layer may comprise the same material as that of a pixel electrode that is formed in a pixel area and is insulated from the second conductive layer. 
         [0049]    Since the second and third contact parts  122   c ,  123   c  overlap the second and third signal lines  122 ,  123 , respectively, an additional contact area between the second and third signal lines  122 ,  123  is not required. Therefore, a width of gap between the second and third signal lines  122 ,  123  can be minimized. 
         [0050]    Since an area for the signal lines  120  can be minimized, a total area for the gate driving circuit can be minimized. A corrosion of the gate driving circuit is prevented by securing a margin of the sealing member to cover the gate driving circuit. 
         [0051]      FIG. 5  shows a layout of a gate driving circuit in accordance with an exemplary embodiment of the present invention. 
         [0052]    Referring to  FIGS. 2 and 5 , the signal lines  120  include the first signal line  121  transmitting the gate off voltage (VOFF), the second signal line  122  transmitting the first clock signal (CK), the third signal line  123  transmitting the second clock signal (CKB) and the fourth signal line  124  transmitting the vertical start voltage (STV). 
         [0053]    The connection lines include a first connection line  121   b , a second connection line  122   b  and a third connection line  123   b . The connection lines comprise a second conductive layer. The signal lines  120  and the connection lines may comprise different conductive layers from each other. 
         [0054]    In an embodiment, the first connection line  121   b  comprises an extending portion extending in parallel with respect to the first signal line  121  to receive a gate off voltage (VOFF) and a diverging portion diverging from the extending portion to electrically connect a power terminal (VG) of the ( 2   n− 1) th  stage (SRC 2   n− 1). 
         [0055]    The diverging portion of the first connection line  121   b  may be bent in a zigzag shape to enlarge a contact area. 
         [0056]    The first signal line  121  is electrically connected with the first connection line  121   b  through the first contact part  121   c ′. The first contact part  121   c ′ includes a first contact hole (C 1 ′), a second contact hole (C 2 ′) and a first contact electrode (E 1 ′). The first contact hole (C 1 ′) exposes the first signal line  121 , and the second contact hole (C 2 ′) exposes the first connection line  121   b . The first contact electrode (E 1 ′) electrically connects the first signal line  121  and the first connection line  121   b  through the first and second contact holes (C 1 ′, C 2 ′). 
         [0057]    A first end portion of the second connection line  122   b  overlaps the second signal line  122 , and a second end portion of the second connection line  122   b  is electrically connected with a first clock terminal (CK 1 ) of the ( 2   n− 1) th  stage (SRC 2   n− 1). For example, the first end portion of the second connection line  122   b  may have an overlapping area broader than that of the first end portion of the second connection line  122   a  as shown in  FIG. 3 . 
         [0058]    In an embodiment, since the first connection line  121   b  is formed in a zigzag shape, the second contact part  122   c ′ can have a contact area broader than that of the second contact part  122   c  as shown in  FIG. 3 . 
         [0059]    The second contact part  122   c ′ includes a third contact hole (C 3 ′) to expose the second signal line  122  and a fourth contact hole (C 4 ′) to expose the first end portion of the second connection line  122   b . The second contact part  122   c ′ includes a second contact electrode (F 2 ′) that connects the second signal line  122  and the second connection line  122   b  through the third and fourth contact holes (C 3 ′, C 4 ′). 
         [0060]    A first end portion of the third connection line  123   a  overlaps the third signal line  123 , and a second end portion of the third connection line  123   a  is electrically connected with a second clock terminal (CK 2 ) of the ( 2   n− 1) th  stage (SRC 2   n− 1). For example, the first end portion of the third connection line  123   b  may have an overlapping area broader than that of the first end portion of the third connection line  123   a  as shown in  FIG. 3 . 
         [0061]    In an embodiment, since the first connection line  122   b  is formed in a zigzag shape, the third contact part  123   c ′ can have a contact area broader than that of the second contact part  123   c  as shown in  FIG. 3 . 
         [0062]    The third contact part  123   c ′ includes a fifth contact hole (C 5 ′) to expose the third signal line  123  and a sixth contact hole (C 6 ′) to expose the first end portion of the third connection line  123   b . The third contact part  123   c ′ includes a third contact electrode (E 3 ′) that connects the third signal line  123  and the third connection line  123   b  through the fifth and sixth contact holes (C 5 ′, C 6 ′). 
         [0063]    The first, second and third contact electrodes (E 1 ′, E 2 ′, E 3 ′) may comprise a third conductive layer. In an embodiment, the third conductive layer may comprise the same material as that of a pixel electrode that is formed in a pixel area. 
         [0064]    Since the contact hole is formed on a corresponding signal line, a width of a gap between signal lines can be minimized, thereby minimizing an area for forming of the gate driving circuit. 
         [0065]      FIG. 6  is a block diagram for showing a gate driving circuit in accordance with an exemplary embodiment of the present invention. 
         [0066]    Referring to  FIG. 1  to  FIG. 6 , the gate driving circuit  140  includes signal lines  520  and a driving circuit  530 . 
         [0067]    The signal line  520  includes a first, a second, a third, a fourth, a fifth, a sixth, a seventh and an eighth signal lines  521 ,  522 ,  523 ,  524 ,  525 ,  526 ,  527 ,  528 . The first signal line  521  transmits a gate off voltage (VOFF). The second signal line  522  transmits a first clock signal (CK). The third signal line  523  transmits a second clock signal (CK′). The fourth signal line  524  transmits a third clock signal (CKB). The fifth signal line  525  transmits a fourth clock signal (CKB′). The sixth signal line  526  transmits a forward signal (DIR). The seventh signal line  527  transmits a reverse signal (DIRB). The eighth signal line  528  transmits a vertical start voltage (STV). 
         [0068]    The driving circuit part  530  includes a plurality of stages (SRC 1 ˜SRCk+1) connected to one another. The plurality of stages (SRC 1 ˜SRCk+1) supply a gate signal to odd-numbered gate lines of the plurality of gate lines (CL). Each stage (SRC 1 ) includes the power terminal (VG), the first clock terminal (CK 1 ), the second clock terminal (CK 2 ), the first control terminal (CT 1 ), the second control terminal (CT 2 ) and the output terminal (OUT). The stages (SRC 1 ˜SRCk+1) include a first terminal to receive the forward signal (DIR) for sequentially driving the stages (SRC 1 ˜SRCk+1) forwardly and a second terminal to receive the reverse signal (DIRB) for sequentially driving the stages (SRC 1 ˜SRCk+1) in reverse. 
         [0069]    In an embodiment, with respect to a  4   n− 3 rd  stage (SRC 1 ), the first dock signal (CK) is applied to the first clock terminal (CK 1 ), and the third clock signal (CKB) is applied to the second clock terminal (CK 2 ). With respect to a  4   n− 2 nd  stage (SRC 2 ), the second clock signal (CK) is applied to the first clock terminal (CK 1 ), and the fourth clock signal (CKB′) is applied to the second clock terminal (CK 2 ). With respect to a ( 4   n− 1) th  stage (SRC 3 ), the third clock signal (CKB) is applied to the first clock terminal (CK 1 ), and the first clock signal (CK) is applied the second dock terminal (CK 2 ). With respect to a  4   n   th  stage (SRC 4 ), the fourth clock signal (CKB′) is applied to the first clock terminal (CK 1 ), and the second clock signal (CK′) is applied to the second dock terminal (CK 2 ). Here, n is 1, 2, . . . k/4 and k is a multiple of 4. 
         [0070]    The first clock signal (CK) and the third clock signal (CK′) have a constant delay time. The first clock signal and the third clock signal (CK, CKB) are inverted with respect to each other with respect to phase. The second clock signal and the fourth clock signal (CK′, CKB′) are inverted with respect to each other with respect to phase. 
         [0071]      FIG. 7  shows a layout of the gate driving circuit shown in  FIG. 6 .  FIG. 8  is a cross-sectional view taken along the line II-II′ shown in  FIG. 7 . 
         [0072]    Referring to  FIG. 6  to  FIG. 8 , a gate driving circuit includes signal lines  520 , a driving circuit part  530  having a plurality of stages (SRC 4   n− 2, SRC 4   n− 1) and connection lines (not shown) connecting the signal lines  520  with the driving circuit part  530 . 
         [0073]    Each stage (SRC 4   n− 2) includes a plurality of thin film transistors (TFTs) connected to each other. The TFTs include the gate electrode (GE) comprising a first conductive layer, the source and the drain electrode (SE, DE) comprising a second conductive layer and the channel (CH) comprising, for example, an amorphous layer or polycrystalline layer. 
         [0074]    The signal lines  520  include a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth signal lines  521 ,  522 ,  523 ,  524 ,  525 ,  526 ,  527 ,  528 . The signal lines  520  may comprise a first conductive layer. 
         [0075]    The connection lines include a first, a second, a third, a fourth, a fifth, a sixth, and a seventh signal lines  521   a ,  522   a ,  523   a ,  524   a ,  525   a ,  526   a ,  527   a . The connection lines may comprise a second conductive layer insulated from the first conductive layer. Alternatively, when the signal lines  520  comprise the second conductive layer, the connection lines comprise the first conductive layer. 
         [0076]    In an embodiment, the first connection line  521   a  comprises an extending portion extending in parallel with respect to the first signal line  521  to receive the gate off voltage (VOFF) and a diverging portion diverging from the extending portion to electrically connect the power terminal (VG) of the ( 4   n− 2) th  stage (SRC 4   n− 2). The first signal line  521  is electrically connected with the first connection line  521   a  through the first contact part  521   c . The first contact part  521   c  includes a first contact hole (C 1 ), a second contact hole (C 2 ) and a first contact electrode (E 1 ). The first contact hole (C 1 ) exposes the third signal line  521 , and the second contact hole (C 2 ) exposes the first connection line  521   a . The first contact electrode (E 1 ) electrically connects the first signal line  521  and the first connection line  521   a  through the first and second contact holes (C 1 , C 2 ). 
         [0077]    A first end portion of the third connection line  523   a  overlaps the third signal line  523 , and a second end portion of the third connection line  523   a  is electrically connected with a first clock terminal (CK 1 ) of the ( 4   n− 2   ) th  stage (SRC 4   n− 2). The third signal line  523  is electrically connected with the third connection line  523   a  through a third contact part  523   c.    
         [0078]    The third contact part  523   c  includes a third contact hole (C 3 ), a fourth contact hole (C 4 ) and a second contact electrode (E 2 ). The third contact hole (C 3 ) exposes the third signal line  523 , and the fourth contact hole (C 4 ) exposes a first end portion of the third connection line  523   a . The second contact electrode (E 2 ) connects the third signal line  523  with the third connection line  523   a  through the third and fourth contact holes (C 3 , C 4 ). 
         [0079]    A first end portion of the fifth connection line  525   a  overlaps the fifth signal line  525 . A second end portion of the fifth connection line  525   a  is electrically connected with a second clock terminal (CK 2 ) of the ( 4   n− 2) th  stage (SRC 4   n− 2). The fifth signal line  525  is electrically connected with the fifth connection line  525   a  through the fifth contact part  525   c.    
         [0080]    The fifth contact part  525   c  includes a fifth contact hole (C 5 ), a sixth contact hole (C 6 ) and a third contact electrode (E 3 ). The fifth contact hole (C 5 ) exposes the fifth signal line  525 , and the sixth contact hole (C 6 ) exposes the first end portion of the fifth connection line  525   a . The third contact electrode (E 3 ) connects the fifth signal line  525  with the fifth connection line  525   a  through the fifth and sixth contact holes (C 5 , C 6 ). 
         [0081]    A first end portion of the sixth connection line  526   a  overlaps the sixth signal line  526 , and a second end portion of the sixth connection line  526   a  is electrically connected with the ( 4   n− 2) th  stage (SRC 4   n− 2). The sixth signal line  526  is electrically connected with the sixth connection line  526   a  through a sixth contact part  526   c.    
         [0082]    The sixth contact part  526   c  includes a seventh contact hole (C 7 ), an eighth contact hole (C 8 ) and a fourth contact electrode (E 4 ). The seventh contact hole (C 7 ) exposes the sixth signal line  526 , and the eighth contact hole (C 8 ) exposes the first end portion of the sixth connection line  526   a . The fourth contact electrode (E 4 ) connects the sixth signal line  526  with the sixth connection line  526   a  through the seventh and eighth contact holes (C 7 , C 8 ). 
         [0083]    A first end portion of the seventh connection line  527   a  overlaps the seventh signal line  527 , and a second end portion of the seventh connection line  527   a  is electrically connected with a ( 4   n− 2) th  stage (SRC 4   n− 2). The seventh signal line  527  is electrically connected with the seventh connection line  527   a  through a seventh contact part  527   c.    
         [0084]    The seventh contact part  527   c  includes a ninth contact hole (C 9 ), a tenth contact hole (C 10 ) and a fifth contact electrode (E 5 ). The ninth contact hole (C 9 ) exposes the seventh signal line  527 , and the tenth contact hole (C 10 ) exposes the first end portion of the seventh connection line  527   a . The fifth contact electrode (E 5 ) connects the seventh signal line  527  with the seventh connection line  527   a  through the ninth and tenth contact holes (C 9 , C 10 ). 
         [0085]    The ( 4   n− 1) th  stage (SRC 4   n− 1) is connected with the first, second, fourth, sixth and seventh connection lines  521   a ,  522   a ,  524   a ,  526   a , and  527   a  through the first, second, fourth, sixth and seventh connection lines  521   a ,  522   a ,  524   a ,  526   a  and  527   a . The first, second, fourth, sixth and seventh signal lines  521 ,  522 ,  523 ,  526  and  527  are connected with the first, second, fourth, sixth and seventh connection lines  521   a ,  522   a ,  524   a ,  526   a  and  527   a  through the first, second, fourth, sixth and seventh contact parts  521   c ,  522   c ,  524   c ,  526  and  527   c.    
         [0086]    Since the second, third, fourth, fifth, sixth and seventh contact parts  522   c ,  523   c ,  524   c ,  525   c ,  526   c  and  527   c  overlap the second, third, fourth, fifth, sixth and seventh signal lines  522 ,  523 ,  524 ,  525 ,  526  and  527 , respectively, an additional contact area between the signal lines is not needed. Therefore, a width of a gap between the signal lines can be minimized. 
         [0087]    Moreover, as an area to form the signal lines  520  can be minimized, a total area to form the gate driving circuit can be minimized. A corrosion of the gate driving circuit can be prevented by forming the gate driving circuit within an area where the sealing member  50  is formed. 
         [0088]      FIG. 9  is a layout for showing a gate driving circuit in accordance with an exemplary embodiment of the present invention. 
         [0089]    Referring to  FIG. 9 , a ( 4   n− 2) th  stage (SRC 4   n− 2) is electrically connected with a first, third, fifth, sixth and seventh signal lines  521 ,  523 ,  525 ,  526  and  527  through a first, third, fifth, sixth and seventh connection lines  521   b ,  523   b ,  525   b ,  526   b  and  527   b , respectively. 
         [0090]    In an embodiment, the first connection line  521   b  comprises an extending portion extending in parallel with respect to the first signal line  521  to receive the gate off voltage (VOFF) and a diverging portion diverging toward the ( 4   n− 2) th  stage (SRC 4   n− 2) to electrically connect the power terminal (VG) of the ( 4   n− 2) th  stage (SRC 4   n− 2). 
         [0091]    The diverging portion of the first connection line  521   b  may be bent in a zigzag shape to enlarge a contact area. 
         [0092]    The first signal line  521  is electrically connected with the first connection line  521   b  through a first contact part  521   c ′. The first contact part  121   c ′ includes a first contact hole (C 1 ′), a second contact hole (C 2 ′) and a first contact electrode (E 1 ′). The first contact hole (C 1 ′) exposes the first signal line  521 , and the second contact hole (C 2 ′) exposes the first connection line  521   b . The first contact electrode (E 1 ′) connects the first signal line  521  with the first connection line  521   b  through the first and second contact holes (C 1 ′, C 2 ′). 
         [0093]    A first end portion of the third connection line  523   b  overtaps the third signal line  523 , and a second end portion of the third connection line  523   b  is electrically connected with a first clock terminal (CK 1 ) of the ( 4   n− 2) th  stage (SRC 4   n− 2) For example, the first end portion of the second connection line  522   b  may have an overlapping area with the third signal line  523  broader than that of the first end portion of the third connection line  523   a  as shown in  FIG. 7 . 
         [0094]    In an embodiment, since the first connection line  521   b  is formed in a zigzag shape, the third contact part  523   c ′ can have a contact area broader than that of the third contact part  523   c  as shown in  FIG. 7 . 
         [0095]    The third contact part  523   c ′ includes a third contact hole (C 3 ′) to expose the third signal line  523  and a fourth contact hole (C 4 ′) to expose the first end portion of the third connection line  523   b . The third contact part  523   c ′ further includes a second contact electrode (E 2 ′) connecting the third signal line  523  with the third connection line  523   b  through the third and fourth contact holes (C 3 ′, C 4 ′). 
         [0096]    A first end portion of the fifth connection line  525   b  overlaps the fifth signal line  525 , and a second end portion of the fifth connection line  525   b  is electrically connected with the second clock terminal (CK 2 ) of the ( 4   n− 2) th  stage (SRC 4   n− 2). For example, the first end portion of the fifth connection line  525   b  may have an overlapping area with the fifth signal line  525  broader than that of the first end portion of the fifth connection line  525   a  as shown in  FIG. 7 . 
         [0097]    In an embodiment, since the first connection line  521   b  is formed in a zigzag shape, the fifth contact part  525   c ′ can have a contact area broader than that of the fifth contact part  525   c  as shown  FIG. 7 . The fifth contact part  525   c ′ includes a fifth contact hole (C 5 ′) to expose the fifth signal line  525  and a sixth contact hole (C 6 ′) to expose the first end portion of the fifth connection line  525   b . The fifth contact part  525   c ′ further includes a third contact electrode (E 3 ′) connecting the fifth signal line  525  with the fifth connection line  525   b  through the fifth and sixth contact holes (C 5 ′, C 6 ′). 
         [0098]    A first end portion of the sixth connection line  526   b  overlaps the sixth signal line  526 , and a second end portion of the sixth connection line  526   b  is electrically connected with the ( 4   n− 2) th  stage (SRC 4   n− 2). For example, the first end portion of the sixth connection line  526   b  may have an overlapping area with the sixth signal line  526  broader than that of the first end portion of the sixth connection line  526   a  as shown in  FIG. 7 . 
         [0099]    In an embodiment, since the first connection line  521   b  is formed in a zigzag shape, the sixth contact part  526   c  can have a contact area broader than that of the sixth contact part  526   c  as shown in  FIG. 7 . The sixth contact part  526   c ′ includes a seventh contact hole (C 7 ′) to expose the sixth signal line  526  and an eighth contact hole (C 8 ′) to expose the first end portion of the sixth connection line  526   b . The sixth contact part  526   c ′ further includes a fourth contact electrode (E 4 ′) connecting the sixth signal line  526  with the sixth connection line  526   b  through the seventh and eighth contact holes (C 7 ′, C 8 ′). 
         [0100]    A first end portion of the seventh connection line  527   b  overlaps the seventh signal line  527 , and a second end portion of the seventh connection line  527   b  is electrically connected with the ( 4   n− 2) th  stage (SRC 4   n− 2). For example, the first end portion of the seventh connection line  527   b  may have an overlapping area with the seventh signal line  527  broader than that of the first end portion of the seventh connection line  527   a  as shown in  FIG. 7 . 
         [0101]    In an embodiment, since the first connection line  521   b  is formed in a zigzag shape, the seventh contact part  527   a  can have a contact area broader than that of the seventh contact part  527   c  as shown in  FIG. 7 . The seventh contact part  527   c ′ includes a ninth contact hole (C 9 ′) to expose the seventh signal line  527  and a tenth contact hole (C 10 ′) to expose the first end portion of the seventh connection line  527   b . The seventh contact part  527   c ′ further includes a fifth contact electrode (E 5 ′) connecting the seventh signal line  527  with the seventh connection line  527   b  through the ninth and tenth contact holes (C 9 ′, C 10 ′). 
         [0102]    The first, second, third, fourth and fifth contact electrodes (E 1 , E 2 , E 3 , E 4  and E 5 ) may comprise a third conductive layer. For example, the third conductive layer comprises the same material as that of a pixel electrode that is formed in pixel areas. 
         [0103]    A ( 4   n− 1) th  stage (SRC 4   n− 1) is electrically connected with the first, the second, the fourth, the sixth and the seventh signal lines  521 ,  522 ,  523 ,  526  and  527  through a first, a second, a fourth, a sixth and a seventh contact parts  521   c ,  522   c ,  524 ,  526   c  and  527   c , respectively. 
         [0104]    As an area for forming the signal lines  520  can be minimized, a total area for forming the gate driving circuit can be minimized. Since the first connection line  521   b  is formed in a zigzag shape, the first, the second, the third, the fourth, the fifth, the sixth and the seventh contact parts  521   c ′,  522   c ′,  523   c ′  524   c ′,  525   c ′,  526  and  527   c ′ can have an enlarged contact area, respectively. 
         [0105]    Although the illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the present invention should not be limited to those precise embodiments and that various other changes and modifications may be affected therein by one of ordinary skill in the related art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.