Abstract:
A device and method for improving the synchronization and metastability resolving capabilities of a flip flop. At least one master latch resolves a metastable condition of a received data signal thereby generating a stable data signal which is received and then displayed by a slave latch. Latches with superior metastability time resolution are configured in a master-slave relationship along with a novel clocking scheme whereby the clock signal supplied to the master latch is inverted as compared to that which is supplied to slave latch. As a result, the input data is latched on a falling edge of a clock signal and subsequently displayed on the rising edge of the clock signal providing at one half cycle for the input data to settle before passing out the data thereby allowing metastabilities to resolve during that period.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to a digital circuitry and logic design. In particular, the present invention provides a long setup flip-flop with improved synchronization and metastability resolving capabilities.  
         BACKGROUND INFORMATION  
         [0002]    In the communication between digital subsystems that do not share a common time reference, signals may occur which are not stable. When this occurs a problem condition may arise where resolution to a logically defined state within a bounded period of time does not occur. The inability for a digital circuit to settle within a bounded period of time is commonly referred to as metastability and may lead to processing errors if not properly synchronized.  
           [0003]    Metastability is an increasingly significant problem for digital circuit design, particularly as clock rates increase. In addition to posing potential disorders in asynchronous systems, metastability can be a problem in synchronous systems where the data input is not kept stable during the setup and hold-time constraints of a flip-flop.  
           [0004]    A flip-flop is a bistable device, i.e. it has two stable states: “0” and “1” (also referred to as “low” and “high”). Under certain conditions, the flip-flop may enter a metastable state where node voltages remain near the threshold level. In this case, node voltages may not resolve to a logically defined state and where they may remain so for an indeterminate amount of time.  
           [0005]    In particular, a metastable state may be induced in an edged-triggered device, for example, with the simultaneous arrival of data during a sampling period. In an edge-triggered device, the input data signal is captured only during the very short time when the clock is changing (i.e. during the “edge” of the clock pulse). If the input signal changes during a clock edge it is possible to enter a metastable condition. In this instance, the flip-flop device may become unable to resolve to either a 0 or a 1 thereby requiring a prolonged period waiting period for the metastability to resolve. Typically, noise (switching and/or thermal) or a slight imbalance eventually causes resolution to occur. However, prior to resolution of this imbalance, the interpretation of the metastable signal may cause a synchronization failure where the undefined value is sampled by other digital circuitry and propagates through the system causing system failures and/or malfunctions.  
           [0006]    Once the flip-flop enters a metastable state, the probability that it will remain metastable some time later has been shown to be an exponentially decreasing function which determines the mean time between failure (MTBF):  
       MTBF   =            t     τ   r             T   w          f   c          f   d                               
 
           [0007]    where t is the time by which the device must be resolved (the metastability settling time), τ r  is the exponential decay rate indicating how long a device is expected to remain in a metastable state once placed there (the metastability time resolution constant), T w  is the likelihood of entering a metastable state (window of metastability propensity), f c  is the frequency of the clock, and f d  is the frequency of the data. It is desirable to maximize MTBF. This becomes increasingly difficult as the clock frequency f c  increases.  
           [0008]    In order to reduce the problems caused by metastability and thereby improve MTBF, circuits called synchronizers are utilized to resolve the undefined signal to be either in the low or high state before it is sampled by other digital circuitry. Typically, synchronizers utilize a latching element that holds data while metastabilities are being resolved. Often synchronizers utilize two cross-coupled CMOS inverters back-to-back, as depicted in circuit  1000  of FIG. 1, which employ a regenerative configuration with positive feedback to capture and retain the input data. Such an arrangement allows a whole clock cycle to resolve metastability. Multiple synchronizers may be cascaded to improve the metastability resolving characteristics of the circuit but at the cost of increased latency, i.e. a full clock period of latency for each additional synchronizer. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 shows a synchronizer circuit utilizing two cross-coupled CMOS inverters.  
         [0010]    [0010]FIG. 2 shows an exemplary embodiment of the synchronizer according present invention utilizing a master latch, slave latch, and novel clocking scheme design.  
         [0011]    [0011]FIG. 3 shows an exemplary embodiment of the present invention utilizing a sense amp latch as the master latch and a jam latch as the slave latch.  
         [0012]    [0012]FIG. 4 show an exemplary embodiment of the present invention utilizing an additional sense amp latch.  
         [0013]    [0013]FIG. 5 shows, in greater detail, an exemplary embodiment of the present invention utilizing an additional sense amp latch. 
     
    
     DETAILED DESCRIPTION  
       [0014]    The present invention provides a synchronizer that employs a long setup approach with superior metastability resolution capability to reduce latency by as much as one half period per clock cycle as compared with conventional synchronizers. Such reduced latency results in higher performance with a lower failure rate.  
         [0015]    As illustrated in FIG. 2 a , synchronizer  2000  according to the present invention includes master latch  202  connected in series with slave latch  203 . According to one embodiment, master latch  202  is configured in a precharge configuration. Clock signal CK is supplied to master latch  202  and its complement supplied to slave latch  203 . Input data D is latched on the falling edge of the clock signal CK and subsequently displayed on the rising edge of clock signal CK providing a full half cycle for input data D to settle before passing the data out to slave latch  203  allowing any metastabilities to resolve during that period. To increase this settling period, clock signal CK may be pulsed at a duration less than a 50% duty cycle. This allows the input data D to be captured in master latch  202  for an extended time period greater than a half cycle extending the time period in which mestabilities may be resolved. If the corresponding MTBF of master latch  202  is sufficient, then slave latch  203  functions as a buffer element. This simplifies the design and reduces restrictions on output timing. According to one embodiment, master latch  202  may be a sense amp latch incorporating a differential amplifier design and slave latch  203  may be a cross-coupled inverter latch commonly called a “jam latch”or, alternatively, slave latch  203  may be a tristateable latch. The sense amp latch is preferred because it possesses a superior metastability time resolution as compared to other latches enabling master latch  202  to resolve quickly and return to a precharge state when it is not latched. (Alternatively, of course, the master latch may return to a pre-discharge state) Although other transparent latches may be utilized for slave latch  203 , the jam latch is preferred because it is capable of storing data through both clock cycles as well as having a superior metastability time resolution as compared with other transparent latches (the tristateable latch would have a faster clock to output time but less superior metastability time resolution as compared with the jam latch). The combination of device elements with superior metastability time resolution and a novel clocking scheme produces a synchronizer with an improved MTBF without decreasing clock frequency.  
         [0016]    [0016]FIG. 2 b  illustrates a timing diagram for the embodiment of FIG. 2 a . Clock signal CK is generated at a regular interval, data signal D is supplied to master latch  202 , data output signal Dos represents the precharging characteristic of master latch  202 , and output signal OUT is produced by slave latch  203 . A comparison of signal transitions shows data signal D captured on a falling edge of clock signal CK and then subsequently displayed on the next rising edge of clock signal CK. In particular, as data signal D transitions from a low to high value prior to a falling edge of the clock signal CK, output signal OUT remains low prior to the following rising edge of clock signal CK. As clock signal CK rises, output signal OUT transitions from a low to high value thereby demonstrating the extended metastability resolution time.  
         [0017]    [0017]FIG. 3 is a transistor level diagram illustrating an exemplary embodiment of the present invention utilizing the sense amp latch, jam latch, and novel clocking scheme design. Sense amp latch (SAL) is comprised of PMOS transistors  320 - 324  and NMOS transistors  325 - 327 . More precisely, transistors  323  through  326  form two cross-coupled inverters providing a latching function to capture input data signal d, transistors  321  and  322  ensure that input data signal d and its inverted value appearing on node n 36  via inverter i 30  are properly supplied to the cross-coupled inverters, while transistors  320  and  327  operate to sense a differential across outputs nodes n 33  and n 34  of the two cross-coupled inverters. The jam latch is comprised of PMOS transistors  330 - 332  and NMOS transistors  333 - 338 . In particular, transistors  331  through  334  from two cross-coupled inverters providing a latching function to store data transferred from the SAL, transistors  335  and  336  ensure that the transferred data is properly supplied to the cross-coupled inverters, transistors  330  and  338  form an inverter presenting an output OUT, while transistor  337  receives clock signal ck in order to facilitate the timing of the latching function and presentation of output OUT. Clock signal ck is further supplied to the SAL in an inverted form via inverter i 31 . As such, input data signal d is latched on the falling edge of clock signal ck and then subsequently displayed on the rising edge of clock signal ck. A detailed description of the present invention exhibiting this behavior during the pertinent clock phases is described below.  
         [0018]    With clock signal ck high, inverter i 31  forces node n 30  to a low potential causing transistor  320  to turn on, which forms a short circuit between nodes n 33  and n 34 . The low potential of node n 30  also causes transistor  327  to turn off which removes a path to ground so neither transistor  325  nor transistor  326  will conduct. As a result, nodes n 33  and n 34  are allowed to float high with the incoming input data signal d. Upon input data signal d going high, transistor  321  will turn off and inverter i 30  will force node n 36  low causing transistor  322  to turn on thereby pulling node n 33  high which causes transistor  324  to turn off and transistor  326  to turn on. Likewise upon input data signal d going low, transistor  322  will turn off and transistor  321  will turn on thereby pulling node n 34  high which causes transistor  323  to turn off and transistor  325  to turn on. Thus, precharging occurs in the SAL when clock signal ck is high.  
         [0019]    When clock signal ck goes low, inverter i 31  forces node n 30  high causing transistor  327  to turn on and transistor  320  to turn off. With transistor  320  off, the short circuit between nodes n 33  and n 34  is removed enabling the nodes to be differentiated depending upon the current value of input data signal d. If data input signal d is currently high, node n 34  is pulled low via transistors  327  and  326  which cause transistor  325  to turn off thereby allowing node n 33  to remain high. Likewise, if input data input signal d is currently low, node n 33  is pulled low via transistors  327  and  325  which cause transistor  326  to turn off thereby allowing node n 34  to remain high. Hence, as clock signal goes low, a differential is formed across output nodes n 33  and n 34  in the cross-couple inverter circuitry of the SAL whereby a state of node n 33  high and node n 34  low represents a latched data value high and a state of node n 33  low and node n 34  high represents a latched data value low. This differential is driven to the jam latch via inverters i 32  and i 33  which deliver the inverted values of nodes n 33  and n 34  to transistors  335  and  336  via nodes n 39  and n 35  respectively. However, with transistor  337  turned off when clock signal is low, transistors  335  and  336  do not conduct thereby preserving the previously stored value in the jam latch circuitry. Thus, as long as clock signal ck remains low, transparency of data between the SAL and the jam latch is delayed, and metastabilities of the latched data in the SAL may continue to be resolved.  
         [0020]    As clock signal ck rises again, transistor  337  is turned on permitting the jam latch to receive latched data from the SAL. If the SAL has latched a high data value (n 34  low and n 33  high), inverters i 32  and i 33  drive nodes n 35  and n 39  high and low respectively, causing transistor  336  to turn on and transistor  335  to remain off. With transistors  337  and  336  turned on, node n 37  is pulled low causing transistor  332  to turn on and transistor  334  to turn off thereby pulling node n 38  high which turns transistor  331  off and transistor  333  on thereby holding node n 37  low. Likewise, if the SAL has latched a low data value (n 33  low and n 34  high), inverters i 32  and i 33  cause nodes n 39  and n 35  to go high and low respectively, which causes transistors  335  to turn on and transistor  336  to turn off. With transistors  337  and  335  on, node n 38  is pulled low causing transistor  331  to turn on and transistor  333  to turn off thereby pulling node n 37  high which turns transistor  332  off and transistor  334  on thereby holding node n 38  low. Hence, with holding either node n 37  or n 38  low while the other node is high, transferred data is latched in the jam latch and presented on output OUT via transistors  330  and  338 . With the data presented on output OUT upon the high clock signal, a full half cycle following the capture of data by the SAL, metastabilities are allowed to resolve during this extended period.  
         [0021]    The synchronization and metastability resolving characteristics may be further improved with the addition of one or more master latches. FIG. 4 shows an exemplary embodiment of the present invention including an additional master latch (e.g. a sense amp latch) connected in series with the previously described embodiment. Such a configuration improves synchronization and metastability resolution characteristics by utilizing a rising phase of the clock to capture data described below.  
         [0022]    Upon a rising edge of clock signal CK, the value of input data signal D is latched into first master latch  201  and the data of second master latch  202  is latched in slave latch  203 . Upon a falling edge of clock signal CK, slave latch  203  retains the previously clocked data while the current data is transferred from first master latch  201  to second master latch  202 . With clock signal CK low, first master latch  201  enters a pre-charge state enabling the device to resolve metastabilities for an additional one half clock cycle as compared to the device of FIG. 2 a . Thus, the addition of further master latch  201  allows the device one complete clock cycle to resolve metastabilities.  
         [0023]    [0023]FIG. 5 is a transistor level diagram illustrating an exemplary embodiment of the present invention utilizing the dual sense amp latch, jam latch, and novel clocking scheme design. The first sense amp latch (SAL 1 ) is comprised of PMOS transistors  510 - 514  and NMOS transistors  515 - 517 . The second sense amp latch (SAL 2 ) is comprised of PMOS transistors  520 - 524  and NMOS transistors  525 - 527 . The jam latch is comprised of PMOS transistors  530 - 532  and NMOS transistors  533 - 538 . The operation of SAL 2  and the jam latch is similar to the embodiment depicted in FIG. 3. SAL 1  operates similar to SAL 2  except that its supplied clock signal ck is not inverted as compared to the jam latch. As such, input data signal d is latched in SAL 1  on the rising edge of a clock signal ck, transferred to SAL 2  on the falling edge of clock signal ck, and displayed on the next rising edge of clock signal ck. A detailed description of the present invention exhibiting this behavior during pertinent clock phases is described below.  
         [0024]    With clock signal ck low, SAL 1  precharges in a similar fashion as the sense amp latch circuitry of FIG. 2 a  during its high clock phase. Nodes n 51  and n 52  are shorted circuited via transistor  510  which has been turned on by the low clock signal. Transistors  515  and  516  do not conduct since transistor  517  has been turned off by the low clock signal. As a result, nodes n 51  and n 52  are allowed to float high with the incoming input data signal. Upon input data signal d going high while clock signal ck is low, node n 56  is caused to go low by inverter i 50  and node n 52  is pulled high by transistor  512 . Likewise, upon input data signal d going low while clock signal ck is low, node n 51  is pulled high by transistor  511  which has been turned on by low input data signal d.  
         [0025]    Upon clock signal ck rising, transistor  510  is turned on thereby removing the short circuit between nodes n 52  and n 51  which enables them to be differentiated depending upon the current value of input data signal d. If input data signal d is currently high, node n 51  is pulled low via transistors  526  and  517  which have been turned on by the high clock signal ck thereby allowing node n 52  to remain high. Likewise, if input data signal d is currently low, node n 52  is pulled low via transistors  515  and  517  allowing node n 51  to remain high. The differential formed across nodes n 51  and n 52  is driven to SAL 2  where it is received by transistors  521  and  522  which impact output nodes n 53  and n 54 . However, nodes n 54  and n 53  of SAL 2  remain short circuited via transistor  520  which has been turned on by the inverted clock signal delivered to node n 50  via inverter i 51 . Furthermore, nodes n 53  and n 54  are allowed to float high via transistor  527  which has been turned off by the inverted clock signal. Thus, as clock signal ck rises, input data signal d is latched in SAL 1 , the transfer of data is delayed as SAL 2  precharges, and any metastability of the latched data may continue to be resolved.  
         [0026]    Upon clock signal ck falling, inverter i 51  causes node n 50  to go high which turns off transistor  520  thereby removing the short circuit between nodes n 54  and n 53  and allowing data latched in SAL 1  to be transferred to SAL 2 . If SAL 1  has latched a high data value (n 51  low and n 52  high), node n 53  is pulled high by transistor  522  causing transistor  526  to turn on thereby pulling node n 54  low via transistor  527  which as been turned on by the inverted clock signal on node n 50 . Likewise, if SAL 1  has latched a low data value (n 51  high and n 52  low), node  54  is pulled high by transistor  521  causing transistor  525  to turn on thereby pulling node n 53  low via transistor  527 . The differential across nodes n 53  and n 54  is then fed to inverters i 52  and i 53  which deliver the inverted value of the differential to transistors  535  and  536  via nodes n 59  and n 55  respectively. However, with transistor  537  turned off by the low clock signal, transistors  535  and  536  do not conduct thereby preserving the previously stored value in the jam latch. Hence with clock signal ck low, data from SAL 1  is latched in SAL 2  while transparency of the data in regards to the jam latch is delayed.  
         [0027]    Upon clock signal ck rising to a high value again, transistor  537  is turned on allowing either transistor  535  or transistor  536  to conduct depending upon the differential value delivered by inverters i 52  and i 53  to nodes n 59  and n 55  respectively. This action causes the cross-coupled inverters comprised of transistors  531 - 534  to pull either node n 57  or n 58  low with the other node high which causes a high or low value respectively to appear on output OUT via transistors  530  and  538  which providing an inverter function. Hence as clock signal ck goes high again, data latched in SAL 2  is transferred to the jam latch and displayed on output OUT.  
         [0028]    Addition of still further sense amplifier latches may provide further improvement in synchronization and metastability resolution characteristics. Each additional sense amplifier latch added may increase the allowable settling time and improve the MTBF of the device thereby reducing the failure rate. Furthermore, such increased settling time may be advantageously added in half cycles increments.