Abstract:
A display device including a plurality of data lines for transmitting a data current corresponding to image signals, a plurality of scan lines for selecting select signals, and a plurality of pixel circuits coupled to the data lines and the scan lines. The display device includes a data driver for supplying the data current corresponding to the image signals, and a demultiplexer including first and second sample/hold circuit groups having input terminals coupled to the data driver. Each of the sample/hold circuit groups includes at least two sample/hold circuits. The display device also includes a switch unit for switching between output terminals of the first and second sample/hold circuit groups and the data lines, and a scan driver for supplying the select signals to the scan lines.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority to and the benefit of Korea Patent Application No. 10-2003-0086113 filed on Nov. 29, 2003 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     (a) Field of the Invention  
         [0003]     The present invention relates to a display device. More specifically, the present invention relates to a demultiplexer for demultiplexing the data current in a display device.  
         [0004]     (b) Description of the Related Art  
         [0005]      FIG. 1  shows an active matrix organic light emitting diode (AMOLED) display device as an example of a current driven display device which needs current demultiplexing.  
         [0006]     The current driven display device includes an organic electroluminescent (EL) display panel  100 , a data driver  200  for providing a data current, a current demultiplexer  300  for performing 1:N demultiplexing on the data current, and scan drivers  400  and  500  for sequentially selecting a plurality of scan lines.  
         [0007]     A predetermined data current is applied to pixels  10  coupled to scan lines selected by the scan drivers  400  and  500 , and the pixels  10  display colors corresponding to the data current. A current demultiplex unit  300  is used so as to reduce the number of integrated circuits (ICs) of the data driver. That is, the current provided by the data driver  200  is 1:N-demultiplexed by the demultiplex unit  300 , and is applied to the pixels corresponding to the N data lines data[ 1 ] to data[n]. Usage of the demultiplex unit  300  reduces the number of ICs necessary for the data driver and saves purchase costs.  
         [0008]      FIG. 2  shows a conventional analog switch for a demultiplexer.  
         [0009]     The 1:2 demultiplexer shown in  FIG. 2  alternately switches the switches S 1  and S 2  to thereby output the data current to two data lines. A long time is required to program the data to the pixels  10  in order to realize high resolution in the current driven panel. When such conventional demultiplexing scheme is used to reduce the number of ICs of the data driver, however, the data programming time needs to be reduced since the data are to be programmed to the pixels each time the switches are alternately switched. Therefore, the conventional demultiplexer is not suitable for high-resolution display devices.  
       SUMMARY OF THE INVENTION  
       [0010]     In exemplary embodiments according to the present invention, is provided a demultiplexing device and method for reducing the number of ICs of the data driver without reducing the data programming time.  
         [0011]     Further, in exemplary embodiments according to the present invention, is provided a demultiplexing device and method appropriate for high-resolution display devices.  
         [0012]     In a first aspect of the present invention, is provided a display device including a plurality of data lines for transmitting a data current corresponding to image signals, a plurality of scan lines for transmitting select signals, and a plurality of pixel circuits coupled to the data lines and the scan lines. The display device includes: a data driver for supplying the data current corresponding to the image signals, and a demultiplexer including first and second sample/hold circuit groups having input terminals coupled to the data driver. Each said sample/hold circuit group includes at least two sample/hold circuits. The display device also includes a switch unit for switching between output terminals of the first and second sample/hold circuit groups and the data lines, and a scan driver for supplying the select signals to the scan lines. One of the sample/hold circuits of the first sample/hold circuit group samples the data current during at least a part of a period in which another one of the sample/hold circuits of the first sample/hold circuit group outputs a current to the switch unit. One of the sample/hold circuits of the second sample/hold circuit group samples the data current during at least a part of a period in which another one of the sample/hold circuits of the second sample/hold circuit group outputs a current to the switch unit.  
         [0013]     In a second aspect of the present invention, is provided a display device including a plurality of data lines for transmitting a data current corresponding to image signals, a plurality of scan lines for transmitting select signals, and a plurality of pixel circuits coupled to the data lines and the scan lines. The display device includes: a data driver for supplying the data current corresponding to the image signal, and a demultiplexer having an input terminal coupled to the data driver. The demultiplexer demultiplexes the data current to output as a demultiplexed data current. The display device also includes a switch unit for switching between an output terminal of the demultiplexer and the data lines, and a scan driver for supplying the select signals to the scan lines. Operations of the switch unit are repeated for each predetermined period.  
         [0014]     In a third aspect of the present invention, is provided a display device including a plurality of data lines for transmitting a data current corresponding to image signals, a plurality of scan lines for transmitting select signals, and a plurality of pixel circuits coupled to the data lines and the scan lines. The display device includes: a data driver for supplying the data current corresponding to the image signals, and a demultiplexer including first and second sample/hold circuit groups. Each of the first and second sample/hold circuit groups has an input terminal coupled to a data driver, and demultiplexes the data current to output as demultiplexed currents. The display device also includes a switch unit for switching between output terminals of the first and second sample/hold circuit groups and the data lines, and a scan driver for supplying the select signals to the scan lines. The first sample/hold circuit group includes first and third sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals are coupled with each other, and the output terminals are coupled with each other. The second sample/hold circuit group includes second and fourth sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals are coupled with each other, and the output terminals are coupled with each other.  
         [0015]     In a fourth aspect of the present invention, a demultiplexer for programming a time-divided data current, which is input by a data driver, to at least two signal lines, is provided. The demultiplexer includes: first and second sample/hold circuit groups each having an input terminal coupled to a data driver, and demultiplexing the data current to output as demultiplexed currents, and a switch unit for switching between output terminals of the first and second sample/hold circuit groups and the signal lines. The first sample/hold circuit group includes first and third sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals are coupled with each other, and the output terminals are coupled with each other. The second sample/hold circuit group includes second and fourth sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals are coupled with each other, and the output terminals are coupled with each other.  
         [0016]     In a fifth aspect of the present invention, a demultiplexing method for outputting a time-divided and sequentially input data current to at least two signal lines, is provided. The method includes: allowing first and second sample/hold circuits to sequentially sample the data current to store as first sampled data in a predetermined order during a first period; allowing the first and second sample/hold circuits to hold a current corresponding to the first sampled data to the signal lines during a second period; allowing third and fourth sample/hold circuits to sample the data current to store as second sampled data during the second period; and allowing the third and fourth sample/hold circuits to hold a current corresponding to the second sampled data to the signal lines during a third period.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention:  
         [0018]      FIG. 1  shows an AMOLED display device as an example of a current driven display device, which may use current demultiplexing according to exemplary embodiments of the present invention;  
         [0019]      FIG. 2  shows a conventional demultiplexer having analog switches;  
         [0020]      FIG. 3  shows a conceptual block diagram of a demultiplexer according to a first exemplary embodiment of the present invention;  
         [0021]      FIG. 4A  shows a first sample/hold circuit according to the first exemplary embodiment of the present invention;  
         [0022]      FIG. 4B  shows an equivalent circuit of the circuit shown in  FIG. 4A ;  
         [0023]      FIG. 5  shows a waveform of a control signal applied to a demultiplexer according to the first exemplary embodiment of the present invention;  
         [0024]      FIG. 6  shows a demultiplexer according to a second exemplary embodiment of the present invention;  
         [0025]      FIG. 7  shows a conceptualized view of a pixel group coupled to the demultiplexer shown in  FIG. 6 ;  
         [0026]      FIG. 8  shows numbers corresponding to the sample/hold circuits that are used for programming currents to the pixels of  FIG. 7  in first to fourth frames according to the second exemplary embodiment of the present invention;  
         [0027]      FIGS. 9A  to  9 D show waveforms of control signals applied to the demultiplexer in the first to fourth frames according to the second exemplary embodiment of the present invention;  
         [0028]      FIG. 10  shows an operation of a switch unit in the first to fourth frames according to the second exemplary embodiment of the present invention;  
         [0029]      FIG. 11  shows numbers corresponding to sample/hold circuits for supplying currents to pixels according to a third exemplary embodiment of the present invention;  
         [0030]      FIGS. 12A  to  12 D show waveforms of control signals applied to the demultiplexer in the first to fourth frames according to the third exemplary embodiment of the present invention;  
         [0031]      FIG. 13  shows an operation of a switch unit in the first to fourth frames according to the third exemplary embodiment of the present invention;  
         [0032]      FIG. 14  shows numbers corresponding to sample/hold circuits for supplying currents to pixels according to a fourth exemplary embodiment of the present invention;  
         [0033]      FIGS. 15A  to  15 D show waveforms of control signals applied to the demultiplexer in the first to fourth frames according to the fourth exemplary embodiment of the present invention; and  
         [0034]      FIGS. 16A and 16B  show an operation of a switch unit when an odd scan line and an even scan line are selected respectively according to the fourth exemplary embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0035]     In the following detailed description, only certain exemplary embodiments of the present invention are shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive.  
         [0036]     The term “couple” or the phrase such as “coupling one thing to another” refer to both directly coupling a first one to a second one and coupling the first one to the second one through a third one which is provided therebetween. To clarify the present invention, parts which are not described in the specification may have been omitted, and like elements are designated by like reference numerals.  
         [0037]      FIG. 3  shows a conceptual block diagram of a demultiplexer  600  according to a first exemplary embodiment of the present invention. By way of example, the demultiplexer  600  may be used as the demultiplexer  300  of  FIG. 1 .  
         [0038]     As shown, the demultiplexer  600  uses four sample/hold circuits which include data storage units  31 ,  32 ,  33 , and  34 ; sampling switches S 1 , S 2 , S 3 , and S 4 ; and holding switches H 1 , H 2 , H 3 , and H 4 . The data storage units  31 ,  32 ,  33 , and  34  are coupled to the data driver  200  through the sampling switches S 1 , S 2 , S 3 , and S 4 , respectively, and coupled to the data lines data[ 1 ] and data[ 2 ] through the holding switches H 1 , H 2 , H 3 , and H 4 , respectively.  
         [0039]     The terminologies of “to sample” and “to hold” used in the specification will now be defined.  
         [0040]     The sample/hold operation includes an operation for sampling the current flowing through the input terminal and writing it in the data storage units in the voltage format, a state for maintaining the written data and standing by since the input switches and the output switches are turned off, and an operation for supplying (“holding”) the current of the data lines by using the values corresponding to the written data. The above-noted stages can be referred to, respectively, as a “sampling” stage, a “standby” stage, and a “holding” stage based on the operations performed therein, for better clarification.  
         [0041]     The internal configuration of the sample/hold circuit according to the exemplary embodiment will now be described in detail. Since the four sample/hold circuits used in the demultiplexer  600  are substantially identically realized, one sample/hold circuit will be described hereinafter.  
         [0042]      FIG. 4A  shows a first sample/hold circuit according to a first exemplary embodiment, and  FIG. 4B  shows an equivalent circuit of the circuit shown in  FIG. 4A .  
         [0043]     The first sample/hold circuit includes a transistor M 1 , a capacitor Ch, sampling switches Sa, Sb, and Sc, and holding switches Ha and Hb, as shown in  FIG. 4B .  
         [0044]     The sampling switches Sa, Sb, and Sc represent the switch S 1  of  FIG. 4A , and they are turned on/off by substantially identical control signals. The holding switches Ha and Hb respectively represent the switch H 1  of  FIG. 4A , and they are turned on/off by substantially identical control signals.  
         [0045]     The sampling switch Sa is coupled between a power supply source VDD and a source of the transistor M 1 , and the holding switch Ha is coupled between a power supply source VSS and a drain of the transistor M 1 . A first terminal of the sampling switch Sb is coupled to a gate of the transistor M 1 , a second terminal thereof is coupled to a first terminal of the sampling switch Sc, and a second terminal of the sampling switch Sc is coupled to the drain of the transistor M 1 . Hence, the transistor M 1  is diode-connected when the sampling switches Sb and Sc are both turned on.  
         [0046]     An operation of the first sample/hold circuit will now be described in reference to  FIGS. 3, 4A  and  4 B.  
         [0047]     When the sampling switches Sa, Sb, and Sc are turned on and the holding switches Ha and Hb are turned off, the gate and the source of the transistor M 1  are coupled to thus form a diode connection, and the current flows to the data driver  200  through the transistor M 1  from the power supply source VDD. The capacitor Ch is charged with a gate-source voltage which corresponds to the current flowing to the transistor M 1 , and the first sample/hold circuit performs a sampling operation of the data.  
         [0048]     When the sampling switches Sa, Sb, and Sc and the holding switches Ha and Hb are turned off, the first sample/hold circuit enters the standby stage while another sample/hold circuit of the demultiplexer  600  holds the data to the data lines.  
         [0049]     When the sampling switches Sa, Sb, and Sc are turned off and the holding switches Ha and Hb are turned on, the current which corresponds to the gate-source voltage charged in the capacitor Ch is maintained to flow to the drain from the source of the transistor M 1 . In this instance, the first sample/hold circuit performs a data programming operation, and holds the data through the data lines.  
         [0050]      FIG. 4B  illustrates the transistor M 1  which is realized with a p channel transistor. In other embodiments, however, the transistor M 1  can be realized with any suitable active element which has a first electrode, a second electrode, and a third electrode, and controls the current flowing to the third electrode according to a voltage applied to the first and second electrodes.  
         [0051]      FIG. 4B  illustrates a single sample/hold circuit, but the scope of the present invention is not restricted to specific sample/hold circuits, and the scope thereof is applicable to demultiplexers which perform the demultiplexing operation to be subsequently described using the sample/hold circuits.  
         [0052]     Referring to  FIG. 5 , an operation of the demultiplexer  600  according to the first exemplary embodiment of the present invention will now be described.  
         [0053]      FIG. 5  shows a waveform of a control signal applied to the demultiplexer  600  according to the first exemplary embodiment of the present invention. It is assumed below that the sampling switches S 1 , S 2 , S 3 , and S 4  are turned on when the applied control signal is low, and the holding switches H 1 , H 2 , H 3 , and H 4  are turned on when the applied control signal is high.  
         [0054]     When the sampling switches S 1  and S 2  are sequentially turned on, the data storage units  31  and  32  input the data currents and perform a sampling operation. Further, when the sampling switches S 3  and S 4  are sequentially turned on, the data storage units  33  and  34  perform a sampling operation. At the same time, since a select signal Select[ 1 ] is applied and the holding switches H 1  and H 2  are turned on, the currents sampled by the data storage units  31  and  32  are held to the data lines data[ 1 ] and data[ 2 ] and are programmed to the pixels.  
         [0055]     When the select signal Select[ 2 ] is applied and the holding switches H 3  and H 4  are turned on (not illustrated), the currents sampled by the data storage units  33  and  34  are held to the data lines data[ 1 ] and data[ 2 ] and are programmed to the pixels.  
         [0056]     The above-noted operation is repeatedly performed, and the demultiplexer  600  demultiplexes the data current output from the data driver  200  and provides demultiplexed currents to the data lines data[ 1 ] and data[ 2 ].  
         [0057]     The demultiplexer  600  according to the first exemplary embodiment allows an increased data programming time when two sample/hold circuits sequentially sample the data currents provided from the data driver  200  while the other two sample/hold circuits hold the data through the data lines.  
         [0058]     However, when the demultiplexer  600  according to the first exemplary embodiment is actually used, repeated spot patterns may be found on the display panel  100  because of characteristic differences of the four sample/hold circuits included in the demultiplexer  600  or the orders for sampling the data currents. In detail, the reason is that the held currents are not the same even when the four sample/hold circuits sample the identical data currents.  
         [0059]     To address this problem, in other exemplary embodiments, the four sample/hold circuits supply the data currents to the respective pixels the same number of times, and an average of the output currents of the four sample/hold circuits may be supplied to the pixels.  
         [0060]     The average of the output currents of the four sample/hold circuits is supplied to the pixels in a second exemplary embodiment by repeating four frames which have different corresponding relations between the four sample/hold circuits and the pixels which receive the data currents from the four circuits.  
         [0061]     Referring to FIGS.  6  to  10 , a demultiplexer  700  according to the second exemplary embodiment will be described in detail.  
         [0062]      FIG. 6  shows the demultiplexer  700  according to the second exemplary embodiment of the present invention. By way of example, the demultiplexer  700  may be used as the demultiplexer  300  of  FIG. 1 .  
         [0063]     As shown, the demultiplexer  700  includes a first sample/hold circuit group  310 , a second sample/hold circuit group  320 , and a switch unit  330 . The first sample/hold circuit group  310  includes first (1st) and third (3rd) sample/hold circuits including, respectively, the data storage unit  31  and the switches S 1 , H 1  and the data storage unit  33  and the switches S 3 , H 3 . The second sample/hold circuit group  320  includes second (2nd) and fourth (4th) sample/hold circuits including, respectively, the data storage unit  32  and the switches S 2 , H 2  and the data storage unit  34  and the switches S 4 , H 4 .  
         [0064]     The first and second sample/hold circuit groups  310  and  320  demultiplex the data current provided from the data driver  200  and output results, and the switch unit  330  switches between output terminals of the first and second sample/hold circuit groups  310  and  320  and the data lines data [ 1 ] and data[ 2 ].  
         [0065]     In more detail, the switch unit  330  includes four switches G 1 , G 2 , G 3  and G 4 . The switch G 1  is coupled between the holding switches H 1 , H 3  and the data line data[ 1 ], and the switch G 3  is coupled between the holding switches H 1 , H 3  and the data line data[ 2 ]. Further, the switch G 2  is coupled between the holding switches H 2 , H 4  and the data line data[ 2 ], and the switch G 4  is coupled between the holding switches H 2 , H 4  and the data line data[ 1 ]. This way, the switch unit  330  can provide holding current from each of the first and second sample/hold circuit groups  310  and  320  to either the data line data[ 1 ] or to the data line data[ 2 ] depending on the state of the switches G 1 , G 2 , G 3  and G 4 .  
         [0066]     Referring now to FIGS.  7  to  10 , an operation of the demultiplexer  700  according to the second exemplary embodiment will be described in detail. For ease of description, a conceptual view of four pixels  1   a ,  1   b ,  2   a  and  2   b  that are coupled to the data lines data[ 1 ] and data[ 2 ] and the scan lines Select[ 1 ] and Select[ 2 ] are illustrated in  FIGS. 7 and 8 .  
         [0067]      FIG. 7  shows, by way of example, a pixel group coupled to the demultiplexer  700 , and  FIG. 8  shows numbers that correspond to the sample/hold circuits that are used for programming currents to pixels shown in  FIG. 7  according to the second exemplary embodiment of the present invention.  
         [0068]      FIGS. 9A  to  9 D show waveforms of control signals applied to the demultiplexer  700  in the first to fourth frames, and  FIG. 10  shows an operation of the switch unit  330  in the first to fourth frames.  FIGS. 9A  to  9 D illustrate the waveforms of the control signals during programming the current to the pixels  1   a ,  1   b ,  1   c  and  1   d . In  FIG. 10 , the switches of the switch unit  330  that are turned on for programming in each frame are indicated.  
         [0069]     As shown in  FIG. 9A , the sampling switches S 1 , S 2 , S 3 , and S 4  are sequentially turned on, and the data storage units  31 ,  32 ,  33 , and  34  sequentially sample the data currents input by the data driver  200  in the first frame. In this instance, since the data driver  200  outputs the data currents in the order of the data currents to be programmed to the pixels  1   a ,  1   b ,  2   a , and  2   b , the data storage units  31 ,  32 ,  33 , and  34  respectively sample the data currents to be programmed to the pixels  1   a ,  1   b ,  2   a , and  2   b.    
         [0070]     The holding switches H 3  and H 4  are turned on while the sampling switches S 1  and S 2  are turned on, but since this is before the select signal Select[ 1 ] is applied, no current is held to the data lines data[ 1 ] and data[ 2 ].  
         [0071]     The select signal Select[ 1 ] is applied to the pixels  1   a  and  1   b  and the holding switches H 1  and H 2  are turned on while the sampling switches S 3  and S 4  are turned on, and hence, the data storage units  31  and  32  hold the current to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0072]     As can be seen from  FIGS. 6 and 10 , the switch unit  330  provides the output current of the first sample/hold circuit group  310  to the data line data[ 1 ] and provides the output current of the second sample/hold circuit group  320  to the data line data[ 2 ] in the first frame.  
         [0073]     Therefore, the holding current of the data storage unit  31  is programmed to the pixel  1   a  through the data line data[ 1 ], and the holding current of the data storage unit  32  is programmed to the pixel  1   b  through the data line data[ 2 ].  
         [0074]     After this, an operation (not illustrated) for programming the data current to the pixels  2   a  and  2   b  is performed. In detail, the sampling switches S 1  and S 2  are sequentially turned on and the data storage units  31  and  32  sample the data currents. At this time, the select signal Select[ 2 ] is applied and the holding switches H 3  and H 4  are turned on so that the holding currents of the data storage units  33  and  34  are programmed to the pixels  2   a  and  2   b  through the data lines data[ 1 ] and data[ 2 ].  
         [0075]     Accordingly, the holding current of the first sample/hold circuit is programmed to the pixel  1   a  of the first frame, the holding current of the second sample/hold circuit is programmed to the pixel  1   b , the holding current of the third sample/hold circuit is programmed to the pixel  2   a , and the holding current of the fourth sample/hold circuit is programmed to the pixel  2   b.    
         [0076]     As shown in  FIG. 9B , the sampling switches S 2 , S 3 , S 4 , and S 1  are sequentially turned on in the second frame.  
         [0077]     The data storage units  32  and  33  sequentially perform a sampling operation while the sampling switches S 2  and S 3  are turned on.  
         [0078]     Further, the data storage units  34  and  31  sequentially perform a sampling operation while the sampling switches S 4  and S 1  are turned on. Also, the select signal Select[ 1 ] is applied and the holding switches H 2  and H 3  are turned on such that the holding currents of the data storage units  32  and  33  are programmed to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0079]     As can be seen from  FIGS. 6 and 10 , the switch unit  330  provides the output current of the first sample/hold circuit group  310  to the data line data[ 2 ] and provides the output current of the second sample/hold circuit group  320  to the data line data[ 1 ] in the second frame.  
         [0080]     Therefore, the holding current of the data storage unit  32  is programmed to the pixel  1   a  through the data line data[ 1 ], and the holding current of the data storage unit  33  is programmed to the pixel  1   b  through the data line data[ 2 ].  
         [0081]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the holding switches H 1  and H 4  are turned on such that the currents which correspond to the data sampled by the data storage units  31  and  34  are respectively held to the data lines data[ 2 ] and data[ 1 ] through the switch unit  330 .  
         [0082]     Therefore, the holding current from the data storage unit  31  is programmed to the pixel  2   b  through the data line data[ 2 ], and the holding current from the data storage unit  34  is programmed to the pixel  2   a  through the data line data[ 1 ].  
         [0083]     Accordingly, the holding current of the second sample/hold circuit is programmed to the pixel  1   a  of the second frame, the holding current of the third sample/hold circuit is programmed to the pixel  1   b , the holding current of the fourth sample/hold circuit is programmed to the pixel  2   a , and the holding current of the first sample/hold circuit is programmed to the pixel  2   b.    
         [0084]     The sampling switches S 3 , S 4 , S 1 , and S 2  are sequentially turned on and the data storage units  33 ,  34 ,  31 , and  32  sequentially sample the data current in the third frame.  
         [0085]     The select signal Select[ 1 ] is applied to the pixels  1   a  and  1   b  while the sampling switches S 1  and S 2  are turned on. In this instance, the holding switches H 3  and H 4  are turned on, and the data storage units  33  and  34  hold the currents to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0086]     As can be from  FIGS. 6 and 10 , the switch unit  330  transmits the output current of the first sample/hold circuit group  310  to the data line data[ 1 ] and transmits the output current of the second sample/hold circuit group  320  to the data line data[ 2 ] in the third frame.  
         [0087]     Therefore, the holding current of the data storage unit  33  is programmed to the pixel  1   a  through the data line data[ 1 ], and the holding current of the data storage unit  34  is programmed to the pixel  1   b  through the data line data[ 2 ].  
         [0088]     After this, when the select signal Select[ 2 ] is applied, the currents which correspond to the sampled data are output to the data storage units  31  and  32 , the holding current of the data storage unit  31  is programmed to the pixel  2   a  through the switch unit  330 , and the holding current of the data storage unit  32  is programmed to the pixel  2   b  through the switch unit  330 .  
         [0089]     Accordingly, the holding current of the third sample/hold circuit is programmed to the pixel  1   a  of the third frame, the holding current of the fourth sample/hold circuit is programmed to the pixel  1   b , the holding current of the first sample/hold circuit is programmed to the pixel  2   a , and the holding current of the second sample/hold circuit is programmed to the pixel  2   b.    
         [0090]     The sampling switches S 4 , S 1 , S 2 , and S 3  are sequentially turned on and the data storage units  34 ,  31 ,  32 , and  33  sequentially sample the data current in the fourth frame.  
         [0091]     The data storage units  34  and  31  sequentially perform a sampling operation while the sampling switches S 4  and S 1  are turned on.  
         [0092]     While the sampling switches S 2  and S 3  are turned on, the data storage units  32  and  33  sequentially perform a sampling operation. Also, the select signal Select[ 1 ] is applied to the pixels  1   a  and  1   b  and the holding switches H 1  and H 4  are turned on such that the holding currents of the data storage units  31  and  34  are programmed, respectively, to the data lines data[ 2 ] and data[ 1 ] through the switch unit  330 .  
         [0093]     As can be seen from  FIGS. 6 and 10 , the switch unit  330  provides the output current of the first sample/hold circuit group  310  to the data line data[ 2 ] and provides the output current of the second sample/hold circuit group  320  to the data line data[ 1 ] in the fourth frame.  
         [0094]     Therefore, the holding current of the data storage unit  31  is programmed to the pixel  1   b  through the data line data[ 2 ], and the holding current of the data storage unit  34  is programmed to the pixel  1   a  through the data line data[ 1 ].  
         [0095]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the currents corresponding to the data sampled by the data storage units  32  and  33  are held to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 . Therefore, the holding current of the data storage unit  32  is programmed to the pixel  2   a , and the holding current of the data storage unit  33  is programmed to the pixel  2   b.    
         [0096]     Accordingly, the holding current of the fourth sample/hold circuit is programmed to the pixel  1   a  of the fourth frame, the holding current of the first sample/hold circuit is programmed to the pixel  1   b , the holding current of the second sample/hold circuit is programmed to the pixel  2   a , and the holding current of the third sample/hold circuit is programmed to the pixel  2   b.    
         [0097]     When the sampling orders of the first to fourth sample/hold circuits are modified and the switch unit  330  switches between the output terminals of the first and second sample/hold circuit groups  310  and  320  and the data lines data[ 1 ] and data[ 2 ], the first to fourth sample/hold circuits supply the data currents to the pixels  1   a ,  1   b ,  2   a , and  2   b  the same number of times. Hence, the average of the output currents of the first to fourth sample/hold circuits is supplied to the respective pixels  1   a ,  1   b ,  2   a , and  2   b.    
         [0098]     Various embodiments can be formed by modifying the sampling orders of the first to fourth sample/hold circuits, which will be described in reference to third and fourth exemplary embodiments.  
         [0099]     Referring to FIGS.  11  to  13 , an operation of the demultiplexer  700  according to the third exemplary embodiment will be described.  
         [0100]      FIG. 11  shows numbers that correspond to the sample/hold circuits for supplying currents to pixels shown in  FIG. 7  according to the third exemplary embodiment of the present invention.  
         [0101]      FIGS. 12A  to  12 D show waveforms of control signals applied to the demultiplexer  700  in the first to fourth frames while programming the currents to the pixels  1   a ,  1   b ,  2   a  and  2   b  according to the third exemplary embodiment of the present invention.  FIG. 13  shows an operation of the switch unit  330  in the first to fourth frames according to the third exemplary embodiment of the present invention. By way of example,  FIG. 13  shows as to which of the switches G 1 , G 2 , G 3  and G 4  of the switch unit  330  are turned on and off for each of the frames.  
         [0102]     As the demultiplexer  700  in the first frame of the third exemplary embodiment, as shown in the timing diagram of  FIG. 12A , operates in substantially the same manner as it operates in the first frame of the second exemplary embodiment, which is illustrated in  FIGS. 8, 9A  and  10 ,  FIG. 12A  will not be discussed separately.  
         [0103]     As shown in  FIG. 12B , the sampling switches S 3  and S 4  are sequentially turned on and the data storage units  33  and  34  sequentially perform a sampling operation in the second frame.  
         [0104]     After this, the sampling switches S 1  and S 2  are sequentially turned on and the data storage units  31  and  32  sequentially perform a sampling operation. At the same time, the select signal Select[ 1 ] is applied and the holding switches H 3  and H 4  are turned on such that the holding currents of the data storage units  33  and  34  are output to the switch unit  330 .  
         [0105]     As can be from  FIGS. 6 and 13 , the switch unit  330  transmits the output current of the first sample/hold circuit group  310  to the data line data[ 1 ] and transmits the output current of the second sample/hold circuit group  320  to the data line data[ 2 ] in the second frame.  
         [0106]     Therefore, the holding current of the data storage unit  33  is programmed to the pixel  1   a  through the data line data[ 1 ], and the holding current of the data storage unit  34  is programmed to the pixel  1   b  through the data line data[ 2 ].  
         [0107]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the holding switches H 1  and H 2  are turned on such that the currents which correspond to the data sampled by the data storage units  31  and  32  are respectively held to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0108]     Therefore, the current of the data storage unit  31  is programmed to the pixel  2   a  through the data line data[ 1 ], and the current of the data storage unit  34  is programmed to the pixel  2   b  through the data line data[ 2 ].  
         [0109]     Accordingly, the holding current of the third sample/hold circuit is programmed to the pixel  1   a  of the second frame, the holding current of the fourth sample/hold circuit is programmed to the pixel  1   b , the holding current of the first sample/hold circuit is programmed to the pixel  2   a , and the holding current of the second sample/hold circuit is programmed to the pixel  2   b.    
         [0110]     As shown in  FIG. 12C , the sampling switches S 4  and S 3  are sequentially turned on and the data storage units  34  and  33  sequentially sample the data current in the third frame.  
         [0111]     After this, the sampling switches S 2  and S 1  are sequentially turned on and the data storage units  32  and  31  sequentially perform a sampling operation. At the same time, the select signal Select[ 1 ] is applied to the pixels  1   a  and  1   b  and the holding switches H 3  and H 4  are turned on such that the data storage units  33  and  34  hold the currents to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0112]     As can be seen from  FIGS. 6 and 13 , the switch unit  330  transmits the output current of the first sample/hold circuit group  310  to the data line data[ 2 ] and transmits the output current of the second sample/hold circuit group  320  to the data line data[ 1 ] in the third frame.  
         [0113]     Therefore, the holding current of the data storage unit  33  is programmed to the pixel  1   b  through the data line data[ 2 ], and the holding current of the data storage unit  34  is programmed to the pixel  1   a  through the data line data[ 1 ].  
         [0114]     After this, when the select signal Select[ 2 ] is applied, the currents which correspond to the sampled data are output to the data storage units  31  and  32 , the holding current of the data storage unit  31  is programmed to the pixel  2   b  by the switch unit  330 , and the holding current of the data storage unit  32  is programmed to the pixel  2   a.    
         [0115]     Accordingly, the holding current of the fourth sample/hold circuit is programmed to the pixel  1   a  of the third frame, the holding current of the third sample/hold circuit is programmed to the pixel  1   b , the holding current of the second sample/hold circuit is programmed to the pixel  2   a , and the holding current of the first sample/hold circuit is programmed to the pixel  2   b.    
         [0116]     As shown in  FIG. 12D , the sampling switches S 2  and S 1  are sequentially turned on and the data storage units  32  and  31  sequentially perform a sampling operation in the fourth frame.  
         [0117]     After this, the sampling switches S 4  and S 3  are sequentially turned on and the data storage units  34  and  33  sequentially perform a sampling operation. Also, the select signal Select[ 1 ] is applied to the pixels  1   a  and  1   b , and the holding switches H 1  and H 2  are turned on such that the holding current of the data storage units  31  and  32  are output to the switch unit  330 .  
         [0118]     As can be seen from  FIGS. 6 and 13 , the switch unit  330  transmits the output current of the first sample/hold circuit group  310  to the data line data[ 2 ] and transmits the output current of the second sample/hold circuit group  320  to the data line data[ 1 ] in the fourth frame.  
         [0119]     Therefore, the holding current of the data storage unit  31  is programmed to the pixel  1   b  through the data line data[ 2 ], and the holding current of the data storage unit  32  is programmed to the pixel  1   a  through the data line data[ 1 ].  
         [0120]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the currents which correspond to the data sampled by the data storage units  33  and  34  are respectively held to the data lines data[ 2 ] and data[ 1 ] through the switch unit  330 . Therefore, the holding current of the data storage unit  34  is programmed to the pixel  2   a , and the holding current of the data storage unit  33  is programmed to the pixel  2   b.    
         [0121]     Accordingly, the holding current of the second sample/hold circuit is programmed to the pixel  1   a  of the fourth frame, the holding current of the first sample/hold circuit is programmed to the pixel  1   b , the holding current of the fourth sample/hold circuit is programmed to the pixel  2   a , and the holding current of the third sample/hold circuit is programmed to the pixel  2   b.    
         [0122]     In the third exemplary embodiment, the numbers corresponding to the sample/hold circuits for providing the currents to the pixels  1   a ,  1   b ,  2   a , and  2   b  of the first frame are changed up and down in the second frame, the numbers corresponding to the sample/hold circuits of the second frame are changed right and left in the third frame, and the numbers corresponding to the sample/hold circuits of the third frame are changed up and down in the fourth frame. Hence, the first to fourth sample/hold circuits supply the data currents to the pixels  1   a ,  1   b ,  2   a , and  2   b  the same number of times.  
         [0123]     Referring to FIGS.  14  to  16 B, an operation of the demultiplexer according to the fourth exemplary embodiment will be described.  
         [0124]      FIG. 14  shows numbers corresponding to the sample/hold circuits for programming the currents to the pixels  1   a ,  1   b ,  2   a , and  2   b  according to the fourth exemplary embodiment of the present invention.  
         [0125]     As shown, the first to fourth sample/hold circuits program the current to the pixels  1   a ,  1   b ,  2   a , and  2   b  in the first frame, and the number of the sample/hold circuits of the whole frames are changed up and down in the second to fourth frames, and the numbers of the sample/hold circuits for programming the currents to the pixel corresponding to the scan line Select[ 2 ] are changed right and left.  
         [0126]      FIGS. 15A  to  15 D show waveforms of control signals applied to the demultiplexer  700  in the first to fourth frames according to the fourth exemplary embodiment of the present invention, and  FIGS. 16A and 16B  show an operation of the switch unit  330  when an odd scan line and an even scan line are selected, respectively.  
         [0127]     Referring to  FIGS. 15A  to  16 B, an operation of the demultiplexer  700  will be described. The operation of the demultiplexer  700  in the first frame corresponding to the timing diagram of  FIG. 15A  will not be described separately since it is substantially the same as that of the first frame in the second exemplary embodiment as illustrated in  FIG. 9A .  
         [0128]     As shown in  FIG. 15B , the sampling switches S 3 , S 4 , S 2 , and S 1  are sequentially turned on in the second frame.  
         [0129]     The data storage units  33  and  34  sequentially perform a sampling operation while the sampling switches S 3  and S 4  are turned on.  
         [0130]     The data storage units  32  and  31  sequentially perform a sampling operation while the sampling switches S 2  and S 1  are turned on. Also, the select signal Select[ 1 ] is applied and the holding switches H 3  and H 4  are turned on such that the holding currents of the data storage units  33  and  34  are programmed to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0131]     Since the operation of the switch unit  330  of the odd scan line is given in  FIG. 16A  in the second frame, the holding current of the data storage unit  33  is programmed to the pixel  1   a  through the data line data[ 1 ], and the holding current of the data storage unit  34  is programmed to the pixel  1   b  through the data line data[ 2 ].  
         [0132]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the holding switches H 1  and H 2  are turned on such that the currents which correspond to the data sampled by the data storage units  31  and  32  are respectively held to the data lines data[ 2 ] and data[ 1 ] through the switch unit  330 .  
         [0133]     Since the operation of the switch unit  330  of the even scan line is given in  FIG. 16B  in the second frame, the holding current of the data storage unit  31  is programmed to the pixel  2   b  through the data line data[ 2 ], and the holding current of the data storage unit  32  is programmed to the pixel  2   a  through the data line data[ 1 ].  
         [0134]     Accordingly, the holding current of the third sample/hold circuit is programmed to the pixel  1   a  of the second frame, the holding current of the fourth sample/hold circuit is programmed to the pixel  1   b , the holding current of the second sample/hold circuit is programmed to the pixel  2   a , and the holding current of the first sample/hold circuit is programmed to the pixel  2   b.    
         [0135]     As shown in  FIG. 15C , the sampling switches S 2 , S 1 , S 4 , and S 3  are sequentially turned on in the third frame.  
         [0136]     The data storage units  32  and  31  sequentially perform a sampling operation while the sampling switches S 2  and S 1  are turned on.  
         [0137]     The data storage units  34  and  33  sequentially perform a sampling operation while the sampling switches S 4  and S 3  are turned on. Also, the select signal Select[ 1 ] is applied and the holding switches H 1  and H 2  are turned on such that the holding currents of the data storage units  31  and  32  are programmed to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0138]     Since the operation of the switch unit  330  of the odd scan line is given in  FIG. 16A  in the third frame, the holding current of the data storage unit  31  is programmed to the pixel  1   b  through the data line data[ 2 ], and the holding current of the data storage unit  32  is programmed to the pixel  1   a  through the data line data[ 1 ].  
         [0139]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the holding switches H 3  and H 4  are turned on such that the currents which correspond to the data sampled by the data storage units  33  and  34  are respectively held to the data lines data[ 2 ] and data[ 1 ] through the switch unit  330 .  
         [0140]     Since the operation of the switch unit  330  of the even scan line is given in  FIG. 16B  in the third frame, the holding current of the data storage unit  33  is programmed to the pixel  2   b  through the data line data[ 2 ], and the holding current of the data storage unit  34  is programmed to the pixel  2   a  through the data line data[ 1 ].  
         [0141]     Accordingly, the holding current of the second sample/hold circuit is programmed to the pixel  1   a  of the third frame, the holding current of the first sample/hold circuit is programmed to the pixel  1   b , the holding current of the fourth sample/hold circuit is programmed to the pixel  2   a , and the holding current of the third sample/hold circuit is programmed to the pixel  2   b.    
         [0142]     As shown in  FIG. 15D , the sampling switches S 4 , S 3 , S 1 , and S 2  are sequentially turned on in the fourth frame.  
         [0143]     The data storage units  34  and  33  sequentially perform a sampling operation while the sampling switches S 4  and S 3  are turned on.  
         [0144]     The data storage units  31  and  32  sequentially perform a sampling operation while the sampling switches S 1  and S 2  are turned on. Also, the select signal Select[ 1 ] is applied and the holding switches H 3  and H 4  are turned on such that the holding currents of the data storage units  33  and  34  are programmed to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0145]     Since the operation of the switch unit  330  of the odd scan line is given in  FIG. 16A  in the fourth frame, the holding current of the data storage unit  33  is programmed to the pixel  1   b  through the data line data[ 2 ], and the holding current of the data storage unit  34  is programmed to the pixel  1   a  through the data line data[ 1 ].  
         [0146]     After this, the select signal Select[ 2 ] is applied to the pixels  2   a  and  2   b  and the holding switches H 1  and H 2  are turned on such that the currents which correspond to the data sampled by the data storage units  31  and  32  are respectively held to the data lines data[ 1 ] and data[ 2 ] through the switch unit  330 .  
         [0147]     Since the operation of the switch unit  330  of the even scan line is given in  FIG. 16B  in the fourth frame, the holding current of the data storage unit  31  is programmed to the pixel  2   a  through the data line data[ 1 ], and the holding current of the data storage unit  32  is programmed to the pixel  2   b  through the data line data[ 2 ].  
         [0148]     Accordingly, the holding current of the fourth sample/hold circuit is programmed to the pixel  1   a  of the fourth frame, the holding current of the third sample/hold circuit is programmed to the pixel  1   b , the holding current of the first sample/hold circuit is programmed to the pixel  2   a , and the holding current of the second sample/hold circuit is programmed to the pixel  2   b.    
         [0149]     By modifying the sampling orders of the first to fourth sample/hold circuits and differently establishing the operations of the switch unit in the odd frame and in the even frame according to the fourth exemplary embodiment, the first to fourth sample/hold circuits supply the data currents to the pixels  1   a ,  1   b ,  2   a , and  2   b  the same number of times.  
         [0150]     The 1:2 demultiplexer has been described for ease of description, but the scope of the present invention is not restricted to this, and various modified 1:N demultiplexers can be realized by using the scope of the present invention.  
         [0151]     Also, it is described above that the orders of the first to fourth sample/hold circuits programmed to the pixels per frame are modified, which can be executed per subframe.  
         [0152]     While this invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof.