Abstract:
A first processor has a processor port for peer-to-peer processor communications. A switch provides for switching communications from a path between said first processor and a second processor to a path between said first processor and a third processor (and vice-versa).

Description:
BACKGROUND 
       [0001]    Herein, related art is described for expository purposes. Related art labeled “prior art”, if any, is admitted prior art; related art not labeled “prior art” is not admitted prior art. 
         [0002]    Blades are, typically thin, modules that can be installed in a blade enclosure. Each blade can function as a server, so a blade system can provide multiple servers in a compact enclosure. Some blade systems provide for conjoining blades to define multi-blade servers that provide more computing power than can be provided by a single blade. For two or more blades to function as one, high-speed communications are required between the blades. 
         [0003]    Some blade systems provide high-speed “jumpers” that provide for high-speed inter-blade processor-to-processor communications. By manually replacing jumpers, the conjoining of blades can be changed. Other blade systems have blade enclosures that provide for automated control of inter-blade routings so that conjoining arrangements can be changed without manually changing jumpers or other components. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a schematic diagram of a blade system in accordance with an embodiment. 
           [0005]      FIG. 2  is a schematic diagram of the blade system of  FIG. 1  showing two different topologies it can assume. 
           [0006]      FIG. 3  is a schematic diagram of a blade of the blade system of  FIG. 1 . 
           [0007]      FIG. 4  is a schematic diagram showing two different topology of the invention. 
           [0008]      FIG. 5  is a schematic diagram showing a detail of a switch of the system of  FIG. 4 . 
           [0009]      FIG. 6  is a flow chart of a method that can be implemented in the contexts of the systems of  FIGS. 1 and 4 . 
       
    
    
     DETAILED DESCRIPTION 
       [0010]    In many multi-processor systems, processors can communicate with each other through a system bus. Beyond this, some processors have ports designed for faster point-to-point communications between pairs of processors. The present invention provides for coupling a switch to such a processor port so that the processor that port communicates with can be selected. In the context of blade and other systems, such switches can provide for economical automated switching between processor communications topologies, e.g., between an 8-processor parallel topology and a dual 4-processor topology. 
         [0011]    Accordingly, a system AP 1  includes a blade enclosure  11  connected to several networks including an in-band network  13 , out-of-band network  15 , and a storage-array, network  17 , as shown in  FIG. 1 . Blade enclosure  11  can hold up to sixteen blades, four of which B 1 -B 4  are shown. Each blade includes two processors, two sockets, two switches, a switch controller, and all or portions of point-to-point inter-processor communication pathways as indicated in the following Table I. 
         [0000]    
       
         
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE I 
               
             
             
               
                   
                   
               
               
                   
                 Blade components 
               
             
          
           
               
                   
                 Blade 1 
                 Blade 3 
                 Blade 5 
                 Blade 7 
               
               
                   
                   
               
             
          
           
               
                 Processors 
                 C1, C2 
                 C3, C4 
                 C5, C6 
                 C7, C8 
               
               
                 Sockets 
                 K1, K2 
                 K3, K4 
                 K5, K6 
                 K7, K8 
               
               
                 Switches 
                 S1, S2 
                 S3, S4 
                 S5, S6 
                 S7, S8 
               
               
                 Switch 
                 SC1 
                 SC3 
                 SC5 
                 SC7 
               
               
                 controllers 
               
               
                 Complete 
                 P12 
                 P34 
                 P56 
                 P78 
               
               
                 pathways 
               
               
                 Portions 
                 P13, P14, P16, 
                 P13, P23, P38, 
                 P57, P25, P58, 
                 P57, P47, 
               
               
                 of 
                 P24, P23, P25 
                 P14, P24, P47 
                 P68, P67, P16 
                 P67, P38, 
               
               
                 pathways 
                   
                   
                   
                 P58, P68 
               
               
                   
               
             
          
         
       
     
         [0012]    Processor (CPU) C 1  has three point-to-point processor communication ports Q 11 , Q 12 , and Q 13 . As shown in  FIG. 1 , processor C 1  is arranged so that it can communicate via its port Q 12  point-to-point with processor C 2  via its port Q 21  and intra-blade path P 12 . Processor C 1  can also communicate with its port Q 13  via inter-blade communications path P 13  with processor C 3  via its port Q 31 . Depending on the configuration of switch S 1 , processor C 1  can communicate with processor C 4  or processor C 6  through switches and pathways as shown. 
         [0013]    The configuration of switch S 1  is controlled by switch controller SC 1 , which also controls switch S 2 . Switch controller SC 1  controls switches S 1  and S 2  in unison so that processor C 1  is communicatively coupled to processor C 4  while processor C 2  is communicatively coupled to processor C 3  and so that processor C 1  is communicatively coupled to processor C 6  while processor C 2  is communicatively coupled to processor C 5 . At the time represented in  FIG. 1 , switch S 1  is configured so that processor C 1  communicates with processor C 6  and not with processor C 4 . Also, at that time, processor C 2  is configured to communicate with processor S 7  and not with processor S 3 . Likewise, switch controllers SC 3 , SC 5 , and SC 7  control respective pairs of switches in unison. In an alternative embodiment, a switch controller controls a blade&#39;s switches independently. 
         [0014]    While switches SC 1 , SC 3 , SC 5 , and SC 7  can be operated independently, in practice they are often controlled in unison to effect a change from one processor topology to another, e.g., to change how blades are conjoined. Which topology is selected depends on whether a single blade mode  21 , a dual-blade mode  23 , or a quad blade mode  25  is desired.  FIG. 2  represents system AP 1  before and after switch controllers SC 1 , SC 3 , SC 5 , and SC 7  change the configuration of all switches. The upper portion of  FIG. 2  corresponds to a 1*8 parallel, S-link, 2-hop topology TP 1 . The lower portion of  FIG. 2  corresponds to a 2*4, 3-link, 1-hop topology TP 2 . 
         [0015]    Each processor provides for 3 links; for example, processor C 1  provides for 3 links via respective ports Q 11 , Q 12 , and Q 13 . All other processors C 2 -C 8  similarly provide three links each. In topology TP 1 , processor C 1  can communicate with some processors (e.g., processors C 2 , C 3 , and C 6 ) directly (1-hop), but must communicate with the other processors through one of those three processors. For example, processor C 1  must communicate with processor C 4  through either processor C 2  or processor C 3 . This is an example of a 2-hop communication. In the case of topology TP 1 , two hops are the most that are required for any processor to communicate with any other processor. Thus, topology TP 1  is a 2-hop topology. 
         [0016]    In the case of topology TP 2 , processors C 1 -C 4  cannot communicate point-to-point with any of processors C 5 -C 8 , and vice versa. The eight processors have been split into two sets of four each. Within each set of four, however, all processors can communicate point-to-point without going through other processors. In other words, within sets of four, inter-processor communications involve only one hop. Hence, topology TP 2  involves two four-processor sets, with each processor providing for three links, and at most one hop per communicating pair. Topology TP 2  has the effect of arranging blades B 1 , B 3 , B 5 , and B 7  into two two-blade servers; however, the two-blade servers can also be used separately as one-blade servers. 
         [0017]    As indicated in  FIG. 3  for switch S 1 , the switches can be optical switches. In that case, port Q 11  can be an optical port that can be optically coupled to respective switches S 1  and S 2 . In this case, switch S 1  can include a beam splitter  31  for outgoing (from processor C 1 ) data and a beam selector  33  for incoming (to processor C 1 ) data. In this case, each path can include a pair of optical waveguide channels. Likewise, port Q 11  uses two optical waveguides for communicating involving switch S 1 . In an alternative embodiment, incoming and outgoing signals use the same waveguides bi-directionally. Electrical pathways, e.g., P 12 , P 13 , and P 14  can include pairs of opposing unidirectional channels (as shown in  FIG. 3 ) or a respective bi-directional channels. 
         [0018]    As also indicated in  FIG. 3 , switch controller SC 1  receives switch setting data via blade enclosure  11 . These settings  19  can be sent over in-band network  13  or an out-of-band network  15  by a management console. The same source would send settings data to switch controllers SC 3 , SC 5 , and SC 7  for coordinated topology changes. 
         [0019]    Various embodiments provide for processors with different numbers of links, different port technologies, and different processor communication technologies. For example, in system AP 4  of  FIG. 4 , processors D 1 -D 8  each have two electrical point-to-point communications ports (E 12  and E 13 ; E 21  and E 24 ; E 31  and E 33 ; E 42  and E 44 ; E 55  and E 57 ; E 66  and E 68 ; E 75  and E 78 ; and E 86  and E 87 ) and no optical point-to-point communications ports. Processors D 3 -D 6  have switches T 3 -T 6  associated with them, while processors D 1 , D 2 , D 7 . and D 8  have unswitched ports. 
         [0020]    In system AP 4 , point-to-point communications paths F 12 , F 13 , F 24 , F 57 , F 68 , and F 78  are unswitched electrical paths. Paths F 34 , F 35 , F 46 , and F 56  are switched optical paths. When switches T 3 -T 6  are configured so that paths F 35  and F 46  are selected and paths F 34  and F 56  are deselected, system AP 4  assumes a 1*8 parallel 2-link, 4-hop topology TP 3 , as shown in the upper portion of  FIG. 4 . When switches T 3 -T 6  are configured so that paths F 34  and F 56  are selected and paths F 35  and F 46  are deselected, system AP 4  assumes a 2*4 parallel, 2-link, 2-hop topology TP 4 , as shown in the lower portion of  FIG. 4 . 
         [0021]    Switches T 3 -T 4  must couple electrical ports to optical paths. Accordingly, electro-optical switches are used. For example, switch T 3  is shown in  FIG. 5 . Switch T 3  includes a beam splitter for outgoing optical signals and a selector for incoming optical signals. An electrical-to-optical converter  55  provides an interface between electrical port E 33  and beam splitter  51 . An optical-to-electrical converter  57  serves as an interface between selector  53  and electrical port E 33 . Switches T 4 -T 6  are similar to switch T 3 . 
         [0022]    Systems AP 1  and AP 4  provide for a method ME 1  flow-charted in  FIG. 6 . At method segment M 1 , switch configurations are set to implement selected processor communications topologies. At method segment M 2 , at least some processor pairs communicate with each other via switch pairs. 
         [0023]    The present invention provides for modular and non-modular computer systems and for modules other than blades. For example, the modules can be rack-mount computers. For another example, the modules can be processor cells, as in the current HP SuperDome 64P, which contains up to 16 4-processor cells. In addition, mixed-type modules are provided for; for example, a system can include full-capability blades (e.g., with processors, disk-storage, and network devices), as well as other blades, modules, or submodules (e.g., than could be inserted in a blade) that contained only processors. 
         [0024]    Generally, the invention provides for a variety of module types and configurations with different numbers of processors per module. The total number of processors in a processor communications topology can vary and can be other than a power of two. Larger numbers of processors can provide for more choices in topologies, as can larger numbers of point-to-point processor communications ports or links. The switches can be on the modules or external to the modules. These and other variations upon and modifications to the illustrated embodiment are within the scope of the following claims