Abstract:
A digital to analog converter including a first capacitor, a second capacitor, an operational amplifier, and a switch is disclosed. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier comprises an input and an output. The switch parallels the first and the second capacitors with the operational amplifier at the input and output according to a digital signal during a second period.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/821,275, filed Aug. 3, 2006, which is incorporated herein by reference. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a converter, and more particularly to a digital to analog converter. 
         [0004]    2. Description of the Related Art 
         [0005]    DACs are an essential interface circuit for converting signals from the digital domain into the analog domain and, particularly, the analog signal processing domain. DACs are also a key to many analog to digital converter techniques. DACs accept N-bit digital words or data and convert them into an analog voltage signal. The analog voltage signal ranges from zero to a maximum voltage corresponding to a reference voltage provided to the digital to analog converter. 
         [0006]    With regard to DAC performance for audio, there is a frequently used delta sigma modulation capable of realizing desired total harmonic distortion (ratio of harmonic component to signal), S/N (signal to noise ratio) or the like. According to the delta sigma modulation, by noise shaping technology, there is achieved an advantage in conversion. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    Digital to analog converters are provided. An exemplary embodiment of a digital to analog converter comprises a first capacitor, a second capacitor, an operational amplifier, and a switch. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier comprises an input and an output. The switch parallels the first and the second capacitors with the operational amplifier at the input and output according to a digital signal during a second period. 
         [0008]    Another exemplary embodiment of a digital to analog converter comprises a first capacitor, a second capacitor, an operational amplifier, a first switch module, and a second switch module. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier comprises a non-inverting input, an inverting input, a non-inverting output, and an inverting output. During a second period, the first switch module connects the first capacitor with the operational amplifier in parallel according to a digital signal and the second switch module connects the second capacitor with the operational amplifier in parallel according to the digital signal. 
         [0009]    Conversion methods are also provided. During a first period, a first voltage is stored in a first capacitor and a second voltage is stored in a second capacitor. During a second period, the first and the second capacitors are connected to an operational amplifier in parallel according to a digital signal. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a schematic diagram of an exemplary embodiment of a DAC; 
           [0013]      FIG. 2  is a schematic diagram of another exemplary embodiment of the DAC; and 
           [0014]      FIG. 3  is a schematic diagram of another exemplary embodiment of the DAC. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0015]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0016]      FIG. 1  is a schematic diagram of an exemplary embodiment of a DAC. DAC  10  comprises capacitors CIN P , CIN N , CF 1 , CF 2 , an operational amplifier  110 , and switches SW 1 ˜SW 12 . All nodes labeled OP are coupled together. All nodes labeled ON are coupled together. 
         [0017]    Switches SW 1 ˜SW 4  are controlled by a clock signal Φ 1 . Switches SW 1 , SW 3  and capacitor CIN P  are serially connected between a reference voltage VREFP and a common mode voltage V CM . Switches SW 2 , SW 4  and capacitor CIN N  are serially connected between a reference voltage VREFN and the common mode voltage V CM . 
         [0018]    Switches SW 5 ˜SW 8  are controlled by a clock signal Φ 2  and a digital code Di. Switches SW 9 ˜SW 12  are controlled by the clock signal Φ 2  and a digital code Dib. The digital code Di is generated by a delta-sigma modulator (DSM)  120 . An inverter  130  inverts the digital code Di to generate the digital code Dib. In this embodiment, the DSM  120  generates a single-bit code. 
         [0019]    In a first period, switches SW 1 ˜SW 4  are turned on such that the capacitor CIN P  stores an amount of charge (VREFP−V CM )*CIN P  and the capacitor CIN N  stores an amount of charge (VREFN−V CM )*CIN N . 
         [0020]    In a second period, switches SW 5 , SW 6 , SW 9 , and SW 10  connect the capacitor CIN P  to the operational amplifier  110  according to the digital codes Di and Dib. Similarly switches SW 7 , SW 8 , SW 11 , and SW 12  connect the capacitor CIN N  to the operational amplifier  110  according to the digital codes Di and Dib. 
         [0021]    In this embodiment, the operational amplifier  110  comprises a non-inverting input, an inverting input, a non-inverting output, and an inverting output. The capacitor CF 1  is coupled to the operational amplifier  110  in parallel at the inverting input and the non-inverting output. The capacitor CF 2  is coupled to the operational amplifier  110  in parallel at the non-inverting input and the inverting output. 
         [0022]    In the second period, switches SW 5  and SW 6  connect the capacitor CIN P  to the inverting input and the non inverting output of the operational amplifier  110  according to the digital code Di. Thus, the capacitor CIN P  is connected to the capacitor CF 1  in parallel. Similarly, switches SW 7  and SW 8  connect the capacitor CIN N  to the non inverting input and the inverting output of the operational amplifier  110  according to the digital code Di. Thus, the capacitor CIN N  is connected to the capacitor CF 2  in parallel. 
         [0023]    In the second period, switches SW 9  and SW 10  connect the capacitor CIN P  to the non inverting input and the inverting output of the operational amplifier  110  according to the digital code Dib. Thus, the capacitor CIN P  is connected to the capacitor CF 2  in parallel. Similarly, switches SW 11  and SW 12  connect the capacitor CIN N  to the inverting input and the non inverting output of the operational amplifier  110  according to the digital code Dib. Thus, the capacitor CIN N  is connected to the capacitor CF 1  in parallel. 
         [0024]    It is assumed that a logic high value of the clock signal Φ 1  or Φ 2  makes the corresponding switches turned on. When the clock signal Φ 1  or Φ 2  is low, the corresponding switches are turned off. 
         [0025]    In the first period, the clock signal Φ 1  is high such that switches SW 1 ˜SW 4  are turned on. The capacitor CIN P  stores the amount of charge (VREFP−V CM )*CIN P  and the capacitor CIN N  stores the amount of charge (VREFN−V CM )*CIN N    
         [0026]    In the second period, Φ 1  is low and Φ 2  is high. If the digital code Di is high and the digital code Dib is low, the switches SW 5 ˜SW 8  are turned on and the switches SW 1 ˜SW 4  are turned off. The capacitor CIN P  is connected to the capacitor CF 1  in parallel and the capacitor CIN N  is connected to the capacitor CF 2  in parallel. The output signal of the non-inverting output is determined by a charge sharing between CIN P  and CF 1 . That is, the charge (VREFP−V CM )*CIN P  transferred by the second period is added to the parallel connection of CIN P  and CF 1 . It is noted that CF 1  may have charge caused by the last Φ 2 . The final charge redistributes on the parallel connection of CIN P  and CF 1 . The output signal of the inverting output is determined by a charge sharing between CIN N  and CF 2 . That is, the charge (VREFN−V CM )*CIN N  transferred by the second period is added to the parallel connection of CIN N  and CF 2 . It is noted that CF 2  may have charge caused by the last Φ 2 . The final charge redistributes on the parallel connection of CIN N  and CF 2 . 
         [0027]    Similarly, if the clock signal Φ 2  and the digital code Dib are high and the clock signal Φ 1  and the digital code Di are low, the switches SW 9 ˜SW 12  are turned on and the switches SW 1 ˜SW 4  are turned off. The capacitor CIN P  is connected to the capacitor CF 2  in parallel and the capacitor CIN N  is connected to the capacitor CF 1  in parallel. The output signal of the non-inverting output is determined by a charge sharing between CIN N  and CF 1 . That is, the charge (VREFN−V CM )*CIN N  transferred by the second period is added to the parallel connection of CIN N  and CF 1 . It is noted that CF 1  may have charge caused by the last Φ 2 . The final charge redistributes on the parallel connection of CIN N  and CF 1 . The output signal of the inverting output is determined by a charge sharing between CIN P  and CF 2 . That is, the charge (VREFP−V CM )*CIN P  transferred by the second period is added to the parallel connection of CIN P  and CF 2 . It is noted that CF 2  may have charge caused by the last Φ 2 . The final charge redistributes on the parallel connection of CIN P  and CF 2 . 
         [0028]    As described previously, according to digital code Di, capacitor CIN P  is connected to capacitor CF 1  in parallel and the capacitor CIN N  is connected to capacitor CF 2  in parallel. Additionally, according to digital code Dib, capacitor CIN P  is connected to capacitor CF 2  in parallel and capacitor CIN N  is connected to capacitor CF 1  in parallel. 
         [0029]      FIG. 2  is a schematic diagram of another exemplary embodiment of the DAC.  FIG. 2  is similar to  FIG. 1  with the exception that DAC  20  provides a chopper function for modulating flicker noises of an operational amplifier  210  into a higher frequency band. The modulated flicker noises can be filtered out. As shown in  FIG. 2 , switches SW 5 ˜SW 12  are controlled by the clock signals Φ 2 , Φ ch , Φ chb , and digital codes Di and Dib. The clock signal Φ ch  is an inverted signal of the clock signal Φ chb . 
         [0030]    The DAC  20  does not require additional switches to achieve the chopper function. Switches SW 5 ˜SW 12  of DAC  20  additionally consider the clock signals Φ ch  and Φ chb  to comprise the chopper function. The Boolean operation of (Di*Φ ch +Dib*Φ chb ) can be implemented by digital circuits to control the switch SW 5 . Similarly, SW 6 -SW 12  can be controlled by digital circuits. For performing the chopping function, adding digital operation into a chip is less expensive than adding additional switches on signal paths of the DAC  20 . 
         [0031]      FIG. 3  is a schematic diagram of another exemplary embodiment of the DAC. The DAC  30  processes multi-bit codes. Inverters  331 ˜ 33   n  respectively process digital codes Di 1 ˜Di n  provided by the SDM  320  to generated digital codes Dib 1 ˜Dib n . All nodes labeled OP are coupled together. All nodes labeled ON are coupled together. All nodes labeled IP are coupled together. All nodes labeled IN are coupled together. 
         [0032]    In the first period, switches SW 1   1 ˜SW 4   1  and SW 1   n ˜SW 4   n  are controlled by the clock signal Φ 1  such that the capacitors CIN P1  and CIN Pn  are charged according to the reference voltage VREFP and V CM . The capacitors CIN N1  and CIN Nn  are charged according to the reference voltage VREFN and V CM . 
         [0033]    In the second period, switches SW 5   1 ˜SW 12   1  are controlled by the clock signal Φ 2  and digital codes Di 1  and Dib 1  such that the capacitor CIN P1  is connected to the capacitor CF 1  or CF 2  in parallel and the capacitor CIN N1  is connected to the capacitor CF 2  or CF 1  in parallel. Similarly switches SW 5   n ˜SW 12   n  are controlled by the clock signal Φ 2  and digital codes Di n  and Dib n  such that the capacitor CIN Pn  is connected to the capacitor CF 1  or CF 2  in parallel and the capacitor CIN Nn  is connected to the capacitor CF 2  or CF 1  in parallel. 
         [0034]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.