Abstract:
A device for correcting the phase of a vertically distorted digital picture receives picture data and a vertical phase correction signal, and assigns lines of the digital picture to a first half picture and to a second half picture. The lines of the second half picture are phase corrected with respect to the first half picture and the first and second half pictures are displayed sequentially. The phase correction is determined in response an increment signal that describes the change of an imaging factor in the veritcal direction of the digital picture on a line-by-line basis and a picture position signal indicative of whether the first half picture or the second half picture is being output.

Description:
PRIORITY INFORMATION 
     This application claims priority from international application PCT/EP01/05987, which claims priority from DE 100 26 739.4 filed May 30, 2000. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to the field of video image processing, and in particular to correcting the phase of a vertically distorted digital picture, such as a digital television picture. 
     Television signals are often displayed using interlaced scanning. As is shown in  FIG. 4 , the interlaced scanning method is characterized in that the picture being displayed (full picture) is decomposed into lines, such that the lines of this full picture are divided into two temporally sequential half pictures. The lines with an originally odd line number are displayed in the first half picture, and the lines with an originally even line number are displayed in the second half picture. The standard for displaying the picture is specified in the guideline ITU-R 601. 
     As shown in  FIG. 4 , the number of lines of each of the two half pictures is half the number of lines of the full picture. A vertical decimation factor (VDEC) can be defined for the interlaced scanning method. This factor corresponds to the ratio of the number of lines of the full picture to the number of lines of the half pictures. In the example of  FIG. 4 , the vertical decimation factor is two (2). 
       FIG. 4  also shows that a phase offset PHS exists between the lines of the first half picture and those of the second half picture. This phase offset amounts to one line. In general, the phase offset is calculated as follows: 
                   PHS   =     VDEC   2             (   1   )               
This phase offset must be taken into account at the beginning, when generating the second picture.
 
     The preceding description assumes a vertical decimation factor VDEC that is constant over the full picture or the half picture. However, for certain applications and for displaying certain effects, it may be desirable to create digital pictures by the interlaced scanning method, with a vertical distortion that changes as a function of vertical position. For example, expansion or compression of a picture or the display of a vertical panorama effect requires a change of the vertical decimation factor or expansion factor over the picture. The vertical decimation factor VDEC thus becomes a function of the line of the half picture, i.e. VDEC=VDEC(L), where L designates the particular line of the half picture. For displaying other effects, it is also conceivable to make the vertical decimation factor also dependent on other parameters, for example the pixel position, et cetera. However, to calculate a phase correction factor for the second half picture, so as to take into account the phase offset between the second half picture and the first half picture, only the vertical decimation factor VDEC on the line is relevant. The following therefore holds for the phase offset: 
                     PHS   ⁡     (   1   )       =       VDEC   ⁡     (   1   )       2             (   2   )               
It is necessary to perform a phase correction for the second half picture, since otherwise an undesirable picture distortion, which is perceived as interference, occurs in the vertical direction during the course of the picture.
 
     There is a need for a system and method of correcting the phase of a vertically distorted digital picture. 
     SUMMARY OF THE INVENTION 
     The phase correction signal for the second half picture is derived from a signal which contains information about the change of the vertical decimation factor of the second digital half picture. If the vertical decimation factor changes as a function of the line, the phase correction signal is determined for each individual line of the second half picture. 
     The phase correction vphscor can be determined in accordance with the following relation, where vinc(L) designates the vertical increment of the vertical decimation factor, i.e. the change of the vertical decimation factor in the vertical direction: 
                     vphscor   ⁡     (   1   )       =       1   2     ·     vinc   ⁡     (   1   )                 (   3   )               
The circuit needed for the phase correction can be constructed of only two adders with feedback, one limiter, a multiplexer, and an additional adder.
 
     The present invention can be used generally in the field of digital picture processing, especially in the field of digital television technology. A unit for picture processing with vertical picture distortion using the interlaced scanning method, based on the present invention, can be situated both before and after an appropriate picture memory. That is, the principle on which the present invention is based can be applied generally to a vertical distortion both before and after a picture memory. 
     These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings. 
    
    
     
       DESCRPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block circuit diagram illustration of a unit for vertical picture distortion; 
         FIG. 2  is a more detailed illustration of several elements of the unit illustrated in  FIG. 1 ; 
         FIGS. 3A and 3B  are block diagram illustrations of the arrangement of the units shown in  FIG. 1 , before and after a picture memory; and 
         FIG. 4  is a pictorial illustration of the decomposition of a full picture into the lines of two interlaced half pictures. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is a block diagram illustration of a digital signal processing unit  100 . The unit  100  includes a panorama generator circuit section  101 , an interpolation phase generator  103 , and an interpolation phase generator section  102 . The circuit sections  101 – 103  generate a phase correction signal vphase(L) on a line  105  for the second half picture of a digital full picture. The phase correction signal is input to an interpolation stage  104 . In dependence on the phase correction signal vphase(L) on the line  105 , which can also be designated as the vertical interpolation phase, the interpolation stage  104  calculates the decimated picture lines belonging to the digital picture data of a digital full picture, in accordance with the particular instantaneous value of the vertical decimation factor VDEC(L). The interpolation stage  104  outputs picture data on a line  110  corresponding to the decimated picture lines of the two half pictures of the digital full picture in the form of output data. 
     The signal vphase(L) on the line  105  designates the weighting between two original lines of the digital full picture, which is used by the interpolation stage  104  to calculate the decimated picture lines of the two digital half pictures and the corresponding digital picture data. The interpolation phase generator  103  calculates the vertical interpolation phase vphase(L) on the line  105  as a function of a vertical scale factor vscale(L) on a line  107 , and of a vertical phase correction vphscor(L) on a line  109 , which is generated by the phase correction circuit  102 . The vertical scale factor vscale(L) on the line  107  is a measure of the vertical decimation factor VDEC(L). A vertical increment vinc(L) signal on line  111  is input to the panorama generator  101  and the phase correction circuit  102 . This vertical increment describes the change of the vertical decimation factor (i.e., vinc(L)=0 if ΔVDEC(L)=0). The values and signals vinc(L), vscale(L), vphscor(L), and vphase(L) are each a function of the line L of the digital full picture and of the particular second digital half picture under consideration. 
       FIG. 2  is a more detailed block diagram illustration of the panorama generator  101 , the phase correction circuit  102  and the interpolation phase generator  103 . The interpolation phase generator  103  includes a digital oscillator, which is formed by a first adder  202  that is fed back through a register  204 . The reference symbols k and m designate the bit width of the data words transmitted within the interpolation phase generator  103 . The interpolation phase generator  103  also includes a second adder  206 , situated in its feedback path, and sums the output of the adder  202  and the vertical phase correction value vphscor(L) signal on the line  109 , and the summed value is output on the line  105  as the signal vphase(L). 
     Without considering this vertical phase correction vphscor(L), the vertical decimation factor VDEC(L), as a function of the vertical scale factor vscale(L) of the interpolation phase generator  103 , is defined as follows: 
                     VDEC   ⁡     (   1   )       =         2   k     +     vscale   ⁡     (   1   )           vscale   ⁡     (   1   )                 (   4   )               
As with the phase correction for the second half picture with a constant vertical decimation factor, with a variable vertical decimation factor the phase must be corrected for each new value of the vertical interpolation phase vphase(L). The phase correction is calculated as follows:
 
                     vphscor   ⁡     (   1   )       =         1   2     ·     ⅆ     ⅆ   l         ⁢     VDEC   ⁡     (   1   )                 (   5   )               
One thus obtains:
 
                     vphscor   ⁡     (   1   )       =         1   2     ·     ⅆ     ⅆ   l         ⁢     vscale   ⁡     (   1   )                 (   6   )               
Here we assume the convention VDEC(L)=vscale(L). A mathematical simplification and approximation then yields:
 
                     vphscor   ⁡     (   1   )       =         1   2     ·   Δ     ⁢           ⁢     vscale   ⁡     (   1   )                 (   7   )               
If the vertical increment, as already described, is now described by the change of the vertical scale factor and of the vertical decimation factor, that is if:
 
                     vphscor   ⁡     (   1   )       =       1   2     ·     vinc   ⁡     (   1   )                 (   9   )               
the phase correction can be derived directly from the vertical increment, as follows:
   vphscor ( L )=½· vinc ( L )  (9) 
The phase correction signal vphscor(L) for the second half picture can thus be derived directly from the increment vinc(L), which serves as the basis for the vertical scale factor vscale(L). The vertical scale factor vscale(L) serves as the control signal for generating the phase information vphase(L) for the interpolation by the interpolation stage  104 . Due to the above relation set forth in EQ. (8), the following relation holds:
   vscale ( L )= vscale ( L− 1)+ vinc ( L )  (10) or   vinc ( L )= vscale ( L )− vscale ( L− 1)  (11) 
The structure of an accumulator, shown in  FIG. 2 , thus results for the panorama generator  101 , which generates the vertical scale factor vscale(L). In principle, this accumulator is formed by an adder  210 , fed back through a register  209 .
 
     In addition, a limiter  205  is inserted into the feedback path, to prevent overflow of the register  209 . The reference symbols n, u and v again designate the word width of the respectively transmitted data words. 
     As shown in  FIG. 2 , the vertical phase correction vphscor(L) can be obtained by the combination of a multiplexer  207  with an evaluator  208  and by adding the adder  206  to the phase generator  103 . Information about the specific instantaneous half picture position (i.e., about the specific and continuously instantaneously processed half picture) is continuously conducted to the multiplexer  207 . If, at this instant, the first half picture is involved, the adder  206 , which has been added to the interpolation phase generator  103 , is ineffective, since the multiplexer  207  outputs the value “0”. On the other hand, for the second half picture, the value vinc(L)/2 is conducted to the adder  206  through the multiplexer  207  and the gain/evaluator  208 . One half of the vertical increment vinc(L) is thus added to each phase value calculated by the adder  202  of the interpolation phase generator  103 , so as to obtain the final phase vphase(L). The gain/evaluator  208  can be realized simply by a bit shift operation (i.e., shifting the bits of the data word vinc(L) by one place to the right or toward a less significant bit). 
     As shown in  FIGS. 3A and 3B , the unit for vertical picture distortion can be situated either before or after a picture memory.  FIG. 3A  shows a general diagram of an inventive unit  100  for vertical picture distortion by the interlaced scanning method in the acquisition path of an arrangement for digital video signal processing, in which the inventive unit  100  for vertical picture distortion is situated behind a data acquisition section  301  and before a picture memory  302 .  FIG. 3B  shows a general diagram of the arrangement of an inventive unit  100  for vertical picture distortion by the interlaced scanning method in the display path of an arrangement for digital video signal processing, where the inventive unit  100  is situated after a full picture memory  303  and before a unit  304 , which is used to display the picture by the interlaced scanning method. 
     Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.