Abstract:
In a switching converter that delivers power to a load, a transition between higher load and lower load modes is controlled by varying the width of switch control pulses in one operating phase and blanking individual pulses in another operating phase. Alternatively, in yet another operating phase the time interval between switch control pulses is varied and, at a given load condition, the time interval between successive pulses remains essentially constant.

Description:
BACKGROUND 
     This invention relates to power converters that are controlled by a pulse width modulator. One such converter is a switch-mode power converter. 
     A typical switch-mode power converter takes a rectified AC signal, steps down the voltage, and delivers a regulated DC signal. A switch controls the conduction period or duty cycle of the converter. Switching, in turn, is controlled based on a signal representative of the output of the converter. 
     Voltage regulation of the output is typically achieved by pulse width modulating (PWM) the conduction time of the switch (i.e., the period when the switch is closed) while keeping the switching frequency fixed. Regulation has also been achieved by varying the frequency of fixed-width pulses, as well as by various combinations and variations of PWM and frequency variation. 
     SUMMARY 
     In general, in one aspect, the invention features a method of controlling, in a switching converter that delivers power to a load, a transition from a higher load mode to a lower load mode. In a first operating phase, the output power is reduced by reducing the width of switch control pulses, and in a second operating phase, individual pulses are blanked. 
     Implementations of the invention may include one or more of the following features. In a third operating phase, the time interval between successive unblanked pulses may be increased and the frequency at which individual pulses are blanked may be varied. Every other pulse may be blanked. The first operating phase may occur prior to the load falling below a first threshold. The second operating phase may occur after the load falls below the first threshold and while the load is above a second threshold. The third operating phase may occur after the load falls below the second threshold. The pulses may be separated by essentially equal length time intervals that are longer than the time intervals between pulses in the higher load mode. 
     In general, in another aspect, the invention features an apparatus that includes a pulse width modulator for regulating the output power in one operating phase, and pulse blanking circuitry for blanking individual pulses in a second operating phase. Implementations of the invention may include pulse spreading circuitry for increasing the intervals between successive unblanked pulses during a third operating phase. 
     Among the advantages of the invention are one or more of the following. When the load (e.g., a &#34;green&#34; computer) is operated in a reduced-power standby mode and during the transition from the high-load mode to the standby mode, efficiency is improved by reducing switching losses and ripple at the converter&#39;s regulated output voltage is minimized. Other advantages and features will become apparent from the following description and from the claims. 
    
    
     DESCRIPTION 
     FIG. 1 is a schematic diagram of a switch-mode power converter. 
     FIGS. 2A-D are timing diagrams. 
     FIG. 3 is a schematic/block diagram of control circuitry. 
     FIG. 4 is timing diagrams. 
     FIG. 5 is a schematic diagram of dual slide modulator circuitry. 
     FIG. 6 is a schematic diagram of missing pulse generator circuitry. 
     FIG. 7 is a schematic diagram of timing logic circuitry. 
     FIGS. 8 through 12 are timing diagrams. 
    
    
     A fly-back switch-mode power converter 10, shown in FIG. 1, receives an unregulated AC signal (V IN ), rectifies it, and converts it to a DC signal (V OUT ) which is regulated at a level required by an electronic device 15 to which power is being supplied. 
     When switch SW is closed and opened repeatedly, power is delivered to the transformer 12 and subsequently forwarded to the load. The power supplied to the load is proportional to the proportion of time that the switch is closed, SW ON  /(SW ON  +SW OFF ), and can therefore be controlled in such a way as to regulate the requisite voltage level. 
     Coupled to V OUT  is an operational amplifier 14 that generates an error amplifier signal (V EAS ) which is fed back to circuitry 16 which controls switch SW. V EAS  is proportional to the power being consumed by the load. As V EAS  drops (when the power being consumed is decreasing), control circuitry 16 ensures that the total time that the switch SW is on (SW ON  /(S ON  +S OFF )) also drops. The control circuitry 16 generates an output signal PWM OUT  that is either HIGH or LOW. When PWM OUT  is HIGH (T ON ), switch SW is closed (SW ON ); when PWM OUT  is LOW (T OFF ), switch SW is open (SW OFF ). 
     The electronic device 15 being powered may be a computer which has a &#34;green&#34; mode in which major power-drawing components are powered down to a standby condition. This powering down may occur in three distinct phases shown in FIGS. 2A-D. For example, while the converter is fully loaded (i.e., an 80 percent duty cycle in which SW ON  /(SW ON  +SW OFF )=80%), V EAS  is at 10 volts. During the transition to the green mode, the transition beginning at t 0 , V EAS  drops as power is reduced until dropping to reference voltage V REF3  of, for example, 2.5 volts, at time t 1 . In the period from t 0  to t 1 , called the first phase, the converter 10 operates in a first mode, called the pulse width modulation (PWM) mode. During this first phase, PWM OUT  is a train of pulses 18 of constant frequency. The pulse width decreases as V EAS  decreases until a minimum pulse width 20 is reached at time t 1 . As V EAS  continues to drop below V REF3  (after time t 1 ), the width of PWM OUT  pulses remains constant and equal to the minimum pulse width 20. When V EAS  is below V REF3 , and until V EAS  drops to another reference voltage V REF2  of, for example, 2.0 volts at time t 2 , converter 10 operates in a second mode, called the missing pulse modulator (MPM) mode. The period from t 1  to t 2  is called the second phase. During this phase, single pulses of the constant-frequency, minimum-pulse-width pulse train begin to be blanked. The sequence is that a single pulse 21 is blanked followed by a number of consecutive pulses 22 being passed to PWM OUT . When V EAS  is slightly less than V REF3 , there may be, for example, 100 consecutive pulses passed between each blanked pulse 21. The number of consecutive passed pulses 22 decreases as V EAS  decreases until only a single pulse 23 is passed between successive blanked pulses 21 just before V EAS  reaches V REF2  (time t 2 ). (Note that the time scale of the third portion of FIG. 2B is shorter than the second portion of FIG. 2C.) When V EAS  drops below V REF2  at t 2 , a third phase is entered and the converter 10 operates in a third mode, called the single pulse modulator (SPM) mode. During this mode, as V EAS  continues to decrease, the time 24 between successive pulses 23 (still of the minimum pulse width) increases until a stable green mode of operation is reached in which the time between pulses is much longer than operation in a loaded mode and remains essentially constant. V EAS  could stop decreasing at any level and stable operation would be achieved at that point. 
     The circuitry 16 of FIG. 3 generates the PWM OUT  described above. The D-type flip-flop 30 is triggered by the falling edge of a pulse received at its clock input CK. Because the D input of the flip-flop is always HIGH (it is connected to V cc ), the output Q goes HIGH at the falling edge of a pulse received at the CK input. The CK input is fed by clock logic 31 designed modularly as an aid in the design process. Clock logic 31 has timing logic 32 (detail shown in FIG. 7) that receives a signal A from an oscillator 34 having a frequency of, for example, 50 kHz. During the first phase, timing logic 32 provides that output E of clock logic 31 will equal signal A, the 50 kHz pulse train. Therefore, in the first phase, the D flip-flop&#39;s output Q (PWM OUT ) goes HIGH at the trailing edge of each oscillator pulse (FIG. 4). 
     The D flip-flop&#39;s output Q (PWM OUT ) is cleared using a ramp signal RAMP1, a comparator 36 and associated circuitry. RAMP1 is received at the positive input of comparator 36. At the negative input of the comparator, signal M is received and equals V EAS  when V EAS  is greater than V REF3 . This is so because when V EAS  is greater than V REF3 , diode 38 is reverse biased, or off, thus making signal M equal to V EAS . (Note that the diodes, such as diode 38, disclosed in this application represent switches that can be implemented by any of numerous methodologies.) When V EAS  falls below V REF3 , however, diode 38 is forward biased and, because V REF3  is coupled directly to comparator 36 while V EAS  is isolated by resistor R1, signal M equals V REF3 . When RAMP1 first exceeds M, the output of comparator 36, which is the flip-flop&#39;s clear input CL, goes HIGH, causing PWM OUT  to be latched LOW (FIG. 4). Q remains LOW until the next oscillator pulse is received at the CK input. When Q is LOW, the HIGH Q&#39; energizes field effect transistor 40, thus holding RAMP1 at a predetermined low voltage level, for example, zero volts. At each oscillator pulse when Q goes HIGH and Q&#39; LOW, field effect transistor 40 becomes no longer energized and the capacitor 42 is allowed to charge thus creating the ramp portion of RAMP1 (FIG. 4). During this charging time, PWM OUT  is HIGH. As V EAS  falls toward V REF2 , the time necessary for RAMP1 to charge from the predetermined low voltage level to the level of V EAS  decreases. Thus, the pulse width of PWM OUT  decreases. Once V EAS  reaches V REF2  (causing M to be held at V REF2 ) the time required for RAMP1 to charge from the predetermined low voltage level to the level of M remains constant and the width of PWM OUT  pulses remains constant at the minimum pulse width 20. 
     When V EAS  is less than V REF2  (during the second and third phases), signal E output from clock logic 31 is affected by the circuit 60 of FIG. 5, called the &#34;dual slide modulator&#34; (DSM) and the circuit 70 of FIG. 6, called the &#34;missing pulse generator&#34; (MPG). During the second phase (when V EAS  drops from V REF3  to V REF2 ), the DSM circuit 60 produces a pulse train G of variable frequency, the frequency being inversely proportional to the level of V EAS  (FIG. 8). Each time G goes LOW, the MPG 70 produces a blanking pulse C received by timing logic 32 (FIG. 7). Signal E thus becomes, in the second phase, the oscillator signal A with a single pulse blanked at a frequency that increases as V EAS  decreases until every other pulse is blanked just before time t 2 . PWM OUT  continues to be a pulse stream whose pulses are of the minimum pulse width 20. However, because fewer pulses are received at the clock input CK of flip-flop 30, there will be fewer of the minimum-pulse-width pulses at PWM OUT . 
     Signal G, which determines the interval of the missing cycle pulses during phase two operation, is accomplished as follows: In the DSM circuit 60 of FIG. 5, while V EAS  is greater than V REF2 , diode D1 will be forward biased and diode D2 reverse biased. The positive input of comparator C1 will then equal V REF2 , and the negative input of comparator C2 will equal V EAS . A ramp signal RAMP2 is received at the negative input of comparator C1 and the positive input of comparator C2. The waveform of RAMP2 is shown in FIG. 8. When RAMP2 exceeds V EAS  during phase two, the output of comparator C2 goes HIGH thus resetting RS flip-flop 66 (i.e., resetting flip-flop 66 output Q to LOW) which causes RAMP2 to begin discharge (ramp down). When RAMP2 falls below V REF2 , the output of comparator C1 goes HIGH, setting RS flip-flop 66 so that output Q is HIGH, which causes RAMP2 to ramp upward and the cycle repeats. The output Q of RS flip-flop 66 is thus a pulse train whose frequency increases and pulse width decreases as V EAS  decreases. When Q is HIGH, capacitor C4 is charged from the Q output through resistor R1 and is said to &#34;ramp up.&#34; When Q is LOW, capacitor C4 now discharges through resistor R1 and thus is said to &#34;ramp down.&#34; Finally, signal D, which goes HIGH when V EAS  drops below V REF3 , is AND&#39;ed with the output of the RS flip-flop 66 (FIG. 5) such that there is an output at G only when V EAS  is less than V REF3 . In other words, signal D enables output G during second and third phase operation. 
     Signal G is received by the missing pulse generator (MPG) 70 (FIG. 6). As shown in FIGS. 9 and 10, for each time signal G goes LOW, signal C produced by MPG 70 goes LOW. A LOW C is used by timing logic 32 (FIG. 7), and specifically AND gate 81, to blank oscillator signal A during a single pulse of that signal so as to create a missing pulse stream at signal E and consequently PWM OUT . In FIG. 6, signal G is received at the clock input CK of a first D-type flip-flop 71. Initially, the clear input CL, which is Q3, to flip-flop 71 is LOW. At the falling edge of a G pulse, flip-flop 71 output Q1 goes HIGH and Q1&#39; LOW. A second D-type flip-flop 72 receives Q1&#39; at its clear input CL and the oscillator signal A at its clock input CK. When Q1&#39; goes LOW, flip-flop 72 output Q2 goes HIGH and Q2&#39; LOW at the next falling edge of a pulse of oscillator signal A. At the clock input CK of flip-flop 73 the oscillator signal A is received. Thus, when Q2&#39; (received at the clear input CL of flip-flop 73) is LOW, flip-flop 73 output Q3 goes HIGH at the trailing edge of the next oscillator pulse. Q3 going HIGH causes flip-flop 71 to clear, which causes flip-flop 72 to clear; flip-flops 71 and 72 being cleared causes flip-flop 73 to be cleared. Thus, MPG 70 produces an output signal C that is low during the time of the second oscillator pulse following G going LOW; otherwise output signal C is HIGH. Now referring to the timing logic circuit 32 (FIG. 7), by virtue of the fact that oscillator signal A and MPG output signal C are AND&#39;ed (by AND gate 81), AND gate 81 output N is the oscillator pulse A with a single pulse blanked where MPG output C is LOW (FIG. 8). As seen later, signal L received by AND gate 81 will always be HIGH and signal 0 received by OR gate 83 will always be LOW during phase two operation. Output signal E thus equals N during phase two operation, and is received at the clock input CK of the D flip-flop (FIG. 3). The missing pulse stream thus created at PWM OUT  during phase two operation is shown in the timing diagram of FIGS. 8, 9 and 10. 
     Early in phase two, when V EAS  is only slightly below V REF3 , the frequency of the pulse train G may be, for example, approximately 500 Hz. Given that the oscillator signal A is at 50 kHz, and because one oscillator pulse is blanked per pulse of G, at this early period of phase two one pulse per 100 oscillator pulses will be blanked (FIG. 8, E and PWM OUT ). As V EAS  continues to drop, the frequency of G increases which causes oscillator pulses to be blanked more frequently. When V EAS  gets very near V REF2 , the frequency of G will surpass 1/2 the frequency of oscillator signal A. When this occurs, even though there may be many more G pulses than A pulses, the MPG circuit 70 (FIG. 6) will not allow more than every other signal to be blanked. The timing diagram of FIG. 10 shows that this is true because not every instance of G going LOW results in a pulse being blanked. Rather, flip-flop 71 being cleared (i.e., Q1 being HIGH) is necessary before G going LOW will initiate the blanking of an oscillator pulse. Thus, in the MPM mode, a single pulse of the oscillator pulse train A is blanked at an increasing frequency that is inversely proportional to the level of V EAS  until every other oscillator pulse is blanked. 
     When V EAS  drops below V REF2 , the third phase begins in which converter 10 operates in the single pulse modulator (SPM) mode. In this phase, as V EAS  decreases, the time now begins to increase between successive pulses received by clock input CK (signal E) of D flip-flop 30 (FIG. 3), and thus also between successive pulses 23 output (PWM OUT ) from D flip-flop 30 (FIGS. 2A-D and 8). 
     If FIG. 5, when V EAS  drops below V REF2 , diode D1 becomes reverse biased and diode D2 forward biased. Therefore, during the SPM mode, the positive input of comparator C1 will equal V EAS , and the negative input of comparator C2 will equal V REF2 . Ramp signal RAMP2 thus continues to ramp up and down between V REF2  and V EAS  (FIG. 8) but the polarity is now reversed as V EAS  is less than V REF2 . When RAMP2 exceeds V REF2 , the output of comparator C2 goes HIGH thus resetting RS flip-flop 62 (i.e., Q goes LOW) and, because a HIGH Q&#39; is now fed back, RAMP2 ramps down. Then, when RAMP2 falls below V EAS , the output of comparator C1 goes HIGH thus setting flip-flop 62 (i.e., Q goes HIGH) and causing RAMP2 to ramp up. The output Q and also G (note that D is still HIGH because V EAS  is less than V REF3 ), as can be seen from the phase three portion of FIG. 8, are thus pulse trains whose frequency decrease as V EAS  decreases. 
     Operation of timing logic 32 of FIG. 7 in phase three differs depending upon whether the frequency of signal G is greater than 1/2 the oscillator frequency. In the early stages of phase three, the frequency of signal G will be greater than 1/2 the oscillator frequency. However, as V EAS  continues to drop, the frequency of G will continue to decrease until it is less than 1/2 the oscillator frequency (FIG. 8). For operation when V EAS  has fallen far enough below V REF2  and the frequency of signal G is less than 1/2 the oscillator frequency, signal N will always be LOW, K always HIGH, thus making signal E equal signal G (FIG. 11). Signal K is always HIGH because the SPM enable signal I is HIGH when V EAS  is less than V REF2  (FIG. 5) and the output of JK flip-flop 84 (signal U) will always be HIGH. Signal U will always be HIGH for the following reason. First, signal J is a pulse that occurs upon the second oscillator pulse following the trailing edge of a G pulse. If the frequency of G is less than 1/2 the frequency of the oscillator frequency, signal G will still be low when Q2 is HIGH. Therefore, D flip-flop 85 will not receive a pulse at its clock input CK; rather, the signal S received at the clock input CK will always be LOW. Consequently, the output of D flip-flop 85 (signal T) will always be low thereby making the set (J) input to flip-flop 84 always HIGH as will be its output (signal U). Thus, as seen in the timing diagram of FIG. 11, the clock logic&#39;s output E will be a pulse train whose frequency is tied to the frequency of G which decreases as V EAS  decreases. Thus, the time between pulses at PWM OUT  increases, and at a given load the time interval between pulses is of essentially equal length. 
     The purpose of JK flip-flop 84 and D flip-flop 85 in timing logic 32 (FIG. 7) is to ensure that during the initial stages of phase three, where the frequency of G is greater than 1/2 the frequency of oscillator signal A, the frequency of pulses E sent to flip-flop 30 of FIG. 3 does not exceed 1/2 the frequency of the oscillator. In other words, under this condition, output signal PWM OUT  looks very much like it did at the latter stages of phase two (FIGS. 2B, 2C and 8). This ensures a smooth transition between the MPM mode and SPM mode. In FIG. 12, the output of JK flip-flop 84 (signal U) is always LOW, as opposed to being always HIGH When V EAS  falls well below V REF3 . Because the frequency of G is greater than 1/2 the oscillator frequency, when Q2 goes HIGH, G is not always LOW; G will be HIGH during at least part of the time that Q2 is HIGH. Signal T output from flip-flop 85 will thus go HIGH when either signal G or Q2 goes LOW, and signal T will stay HIGH until signal J, received at the clear input CL, goes HIGH. Consequently, signal J input to JK flip-flop 84 will be LOW when signal J is received at the clock input CK of flip-flop 84, and its output (signal U) will always be LOW. Signal U being low thus causes signal G to be blanked and not seen at output signal E, and also signals C and A AND&#39;ed to not be blanked and seen at output signal E. Thus, in the SPM mode when f G  &gt;1/2f A , output signal E, and consequently PWM OUT , is the same as during the MPM mode when f G  &gt;1/2f A . At these times, a minimum width pulse is generated at PWM OUT  for every other oscillator pulse. 
     Other embodiments are within the scope of the claims.