Abstract:
A storage system (e.g., a magnetic disk system or a magnetic tape system) employing a write head, a write controller and a write driver circuit. In operation, the write head records data on a magnetic media (e.g., a magnetic tape or a magnetic disk) based on a flow of a write current through the write head, and the write driver circuit includes a variable power supply network and a variable power return network driving the write current through the write head based on a selection by the write controller of an operating power mode among a plurality of selectable power modes of the variable power supply network and the variable power return network. Each power mode of the variable power supply network and the variable power return network drives the write current with a different magnitude from the variable power supply network through the write head to the variable power return network.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention generally relates to “H” configuration of FET devices within a write driver circuit. The present invention specifically relates to power demands of the write driver circuit that are dependent upon a size of the FET devices. 
       BACKGROUND OF THE INVENTION 
       [0002]    Magnetic tape provides a means for physically storing data. As an archival medium, tape often comprises the only copy of the data. The tape is typically made as thin as practically possible to maximize the length of a tape stored on a tape reel and thereby maximize the amount of data that can be stored on the tape contained in a single cartridge. A tape drive is used to store and retrieve data with respect to the magnetic tape. An example of a tape drive is the IBM TotalStorage Enterprise Tape Drive 3592 manufactured by IBM Corporation. Tape drives are typically used in combination with an automated data storage library. For example, the IBM TotalStorage Enterprise Tape Library 3494 manufactured by IBM Corporation is an automated data storage library that may include one or more tape drives and data storage media for storing data with respect to the tape drives. 
         [0003]      FIGS. 1 and 2  illustrate an exemplary configuration of a known write mechanism of a tape drive employing a “H” configuration of write drivers in the form of FET devices M 1 -M 4  for driving a write current I W  through a write head L 1 . Under normal write conditions, an AC control signal IN and an AC control signal NOT_IN are applied to respective inverters to logic inverters A 1  and A 2  to facilitate a bi-directional cyclic flow of a write current I W  through write head L 1 . Specifically, in a first cycle phase with AC control signal IN being a logic low and AC control signal NOT_IN being a logic high, FETs M 2  and M 3  are conductive and FETs M 1  and M 4  are nonconductive whereby write current I W  flows from FET M 3  through write head L 1  to FET M 2 . Conversely, in a second cycle phase with AC control signal IN being a logic high and AC control signal NOT_IN being a logic low, FETs M 1  and M 4  are conductive and FETs M 2  and M 3  are nonconductive whereby write current I W  flows from FET M 4  through write head L 1  to FET M 1 . 
         [0004]    For the voltage mode write driver circuit of  FIG. 1 , a magnitude of write current I W  is dependent upon a voltage source V S  and a pair of resistors R 1  and R 2  in view of the design of FETs M 1 -M 4  having a low drain-source voltage drop when in a conductive state, and for the current mode write driver circuit of  FIG. 2 , the magnitude of write current I W  is dependent upon a current source I S  in view of the design of FETs M 1 -M 4  having a low drain-source voltage drop when in a conductive state. Nonetheless, for both write driver circuits, the size of FETs M 1 -M 4  must be selected for the maximum magnitude of write current I W  required for all applications. However, the AC power of AC control signals IN and NOT_IN are affected by the size of FETs M 1 -M 4 , as represented by a Z factor equal to a width of a FET divided by a length of a FET, and by the switching frequency at which AC control signals IN and NOT_IN are changing between logic states. 
         [0005]    As related to the size of FETs M 1 -M 4 , each FET M 1 -M 4  has a respective capacitance C 11 -C 42  that must be charged when switching a FET from being nonconductive to conductive, and must be discharged when switching a FET from being conductive to nonconductive. Each capacitance C 11 -C 42  is proportional to the size of FETs M 1 -M 4 . As a result, the total AC power of AC control signals IN and NOT_IN increases with any increase in the size of FETs M 1 -M 4 . Consequently, the storage industry is constantly striving to improve upon techniques for maximizing the magnitude of write current I W  required for all applications while minimizing the AC power needed to operate the write driver circuit. 
       SUMMARY OF THE INVENTION 
       [0006]    Various embodiments of the present invention provide a new and unique technique for maximizing the magnitude of write current I W  required for all applications while minimizing the AC power needed to operate the write driver circuit. 
         [0007]    A first form of the present invention is a method for operating a storage drive. The method involves a write controller selecting an operating power mode among a plurality of selectable power modes of a variable power supply network and a variable power return network electrically connected to a write head. Each power mode of the variable power supply network and the variable power return network drives a write current with a different magnitude from the variable power supply network through the write head to the variable power return network. The method further involves the write head recording data on a magnetic media (e.g., a magnetic disk or a magnetic tape) based on a flow of the write current through the write head. 
         [0008]    A second form of the present invention is a storage drive (e.g., a disk drive or a tape drive) comprising a write head and a write driver circuit. In operation, the write head records data on a magnetic media (e.g., a magnetic disk or a magnetic tape) based on a flow of a write current through the write head, and the write driver circuit includes a variable power supply network and a variable power return network driving the write current through the write bead based on a selection of an operating power mode among a plurality of selectable power modes of the variable power supply network and the variable power return network. Each power mode of the variable power supply network and the variable power return network drives the write current with a different magnitude from the variable power supply network through the write head to the variable power return network. 
         [0009]    A third form of the present invention is a storage system (e.g., a disk system or a tape system) comprising a write head, a write controller and a write driver circuit. In operation, the write head records data on a magnetic media (e.g., a magnetic disk or a magnetic tape) based on a flow of a write current through the write head, and the write driver circuit includes a variable power supply network and a variable power return network driving the write current through the write head based on a selection by the write controller of an operating power mode among a plurality of selectable power modes of the variable power supply network and the variable power return network. Each power mode of the variable power supply network and the variable power return network drives the write current with a different magnitude from the variable power supply network through the write head to the variable power return network. 
         [0010]    The aforementioned forms and additional forms as well as objects and advantages of the present invention will become further apparent from the following detailed description of the various embodiments of the present invention read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the present invention rather than limiting, the scope of the present invention being defined by the appended claims and equivalents thereof. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIGS. 1 and 2  illustrates a respective schematic diagram of a voltage mode H configuration write driver circuit and a current mode H configuration write driver circuit as known in the art; 
           [0012]      FIG. 3  illustrates a block diagram of one embodiment of a logic supply controller and a variable power supply network of a write driver in accordance with the present invention; 
           [0013]      FIG. 4  illustrates a block diagram of one embodiment of a logic return controller and a variable power return network of a write driver in accordance with the present invention; 
           [0014]      FIG. 5  illustrates a table listing different power modes of the networks illustrated in  FIGS. 3 and 4 ; 
           [0015]      FIG. 6  illustrates a schematic diagram of a first embodiment of a NFET write driver employing a logic supply controller and a variable power supply network in accordance with the present invention; 
           [0016]      FIG. 7  illustrates a schematic diagram of a first embodiment of a PFET write driver employing a logic return controller and a variable power return network in accordance with the present invention; 
           [0017]      FIGS. 8 and 9  illustrates tables listing different power modes of the NFET write driver and the PFET write driver illustrated in  FIGS. 6 and 7 ; 
           [0018]      FIG. 10  illustrates a schematic diagram of a second embodiment of a NFET write driver employing a logic supply controller and a variable power supply network in accordance with the present invention; 
           [0019]      FIG. 11  illustrates a schematic diagram of a second embodiment of a PFET write driver employing a logic return controller and a variable power return network in accordance with the present invention; 
           [0020]      FIGS. 12 and 13  illustrates tables listing different power modes of the NFET write driver and the PFET write driver illustrated in  FIGS. 10 and 11 ; 
           [0021]      FIG. 14  illustrates a block diagram of one embodiment of a voltage mode “H” configuration write driver circuit in accordance with the present invention; 
           [0022]      FIG. 15  illustrates a block diagram of one embodiment of a voltage mode “H” configuration write driver circuit in accordance with the present invention; and 
           [0023]      FIG. 16  illustrates a block diagram of one embodiment of a magnetic tape recorder system in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]      FIG. 3  illustrates a logic power supply manager  20  and a variable power supply network  30  for driving a write current I W  to a write head L 1 . To this end, variable power supply network  30  includes a “n” number of write drivers in the form of supply electronic switches SS (n≧2) connected in parallel between a positive supply node PSN and a negative supply node NSN with a voltage source V S  being connected to positive supply node PSN and write head L 1  being connected to negative supply node NSN. Based on one or more supply control signals SCS received from an external controller, logic power supply manager  20  utilizes logic components to provide one or more number of supply switching signals SSS to network  30  whereby one or more supply electronic switches SS can be switched between an open state and a closed state (e.g., one or more PFETs being switched between a conductive state and a nonconductive state). 
         [0025]      FIG. 4  illustrates a logic power return manager  40  and a variable power return network  50  for sourcing a write current I W  from write head L 1 . To this end, variable power return network  50  includes a “n” number of write drivers in the form of return electronic switches RS (n≧2) connected in parallel between a positive return node PRN and a negative return node NRN with write head L 1  being connected to positive return node PRN and a ground GND being connected to negative return node NRN. Alternatively, as indicated by the dashed lines, a current source I S  can be connected to negative return node NRN. Based on one or more return control signals RCS received from an external controller, logic power return manager  40  utilizes logic components to provide one or more return switching signals RSS to network  50  whereby each return electronic switch RS can be switched between an open state and a closed state (e.g., one or more NFETs being switched between a conductive state and a nonconductive state). 
         [0026]    Referring to  FIGS. 3 and 4 , networks  30  and  50  will drive write current I W  through write head L 1  based on a selection of an operational power mode among a number power modes as represented by table  60  shown in  FIG. 5 . Each power mode represents a different switching configuration of electronic switches SS 1 -SSn and RS 1 -RSn whereby the control signals SCS and RCS can be utilized to select a desired operating mode, and as shown in  FIG. 5 , each power mode provides a different magnitude of write current I W  based on its particular switching configuration of electronic switches SS 1 -SSn and RS 1 -RSn. Specifically, in view of electronic switches SS 1 -SSn and RS 1 -RSn having the same Z factor (e.g., a common Z factor for a n number PFETs and an n number of NFETs), each power mode provides a magnitude n (I Z ) as a function of a size of the closed switches among electronic switches SS 1 -SSn and RS 1 -RSn. 
         [0027]    In practice, there are no limitations or restrictions to the structural configurations of managers  20  and  40  and networks  30  and  50  as shown in  FIGS. 3 and 4 . To further illustrate an understanding of managers  20  and  40  and networks  30  and  50 ,  FIGS. 6 ,  7 ,  10  and  11  illustrate exemplary structural configurations of managers  20  and  40  and networks  30  and  50 . 
         [0028]    Referring to  FIG. 6 , a NFET write driver employs a logic return manager  41  and a variable power return network  51 . Manager  41  includes an inverter A 3 , a two-input AND gate A 4  and a two-input AND gate A 5 . Network  51  includes three (3) NFETs M 11 -M 13  connected in parallel between a drain node DN 1  and a source node SN 1  with write head L 1  being connected to drain node DN 1 . For a voltage mode, ground GND is connected to source node SN 1 . Alternatively for a current mode, as indicated by the dashed lines, current source I S  is connected to source node SN 1  instead of ground GND. Inverter A 3  provides a gate signal G_ 11  to a gate terminal of a NFET M 11  based on an inversion of a control signal IN_ 1 _N into gate signal G_ 11 . AND gate A 4  provides a gate signal G_ 12  to a gate terminal of a NFET M 12  based on a Boolean AND function of control signals IN_ 1 _N and S 2 _ON. AND gate A 5  provides a gate signal G_ 13  to a gate terminal of a NFET M 13  based on a Boolean AND function of control signals IN_ 11 _N and S 3 _ON. 
         [0029]    Referring to  FIG. 7 , a PFET write driver employs a logic return manager  21  and a variable power return network  31 . Manager  21  includes an inverter A 6 , an inverter A 7 , a two-input OR gate A 8 , an inverter A 9  and a two-input OR gate A 10 . Network  31  includes three (3) PFETs M 41 -M 43  connected in parallel between a source node SN 4  and a drain node DN 4  with voltage source V S  being connected to source node SN 4  and write head L 1  being connected to drain node DN 4 . Inverter A 6  provides a gate signal G_ 41  to a gate terminal of a PFET M 43  based on an inversion of a control signal IN_ 2 _P into gate signal G_ 41 . Inverter A 7  and OR gate A 8  provide a gate signal G_ 42  to a gate terminal of a PFET M 42  based on a Boolean OR function of control signal IN_ 2 _P and an inversion of control signal S 2 _ON. Inverter A 9  and OR gate A 10  provide a gate signal G_ 43  to a gate terminal of a PFET M 43  based on a Boolean OR function of control signal IN_ 2 _P and an inversion of control signal S 3 _ON. 
         [0030]    In operation, the NFET write driver of  FIG. 6  and PFET write driver of  FIG. 7  are switched in unison between a conductive state and a nonconductive state based on a selection of an operational power mode among three (3) power modes via the control signals as represented by power mode tables  61  and  62  shown in respective  FIGS. 8 and 9 . Each power mode represents a different switching configuration of NFETs M 11 -M 13  and PFETs M 41 -M 43  whereby the control signals IN_ 1 _N, IN_ 2 _P, S 2 _ON and S 3 _ON can be utilized to select a desired operating mode as best shown in  FIG. 8 . As best shown in  FIG. 9 , each power mode provides a different magnitude of write current I W  based on its particular switching configuration of NFETs M 11 -M 13  and PFETs M 41 -M 43  between a conductive state (“CONDUCT STATE”) and a nonconductive state (“NONCON STATE”). Specifically, in view of NFETs M 11 -M 13  and PFETs M 41 -M 43  having the same Z factor, each power mode provides a magnitude n(I Z ) as a function of a common size of the n number of conductive NFETs among NFETs M 11 -M 13  and the n number of conductive PFETs among PFETs M 41 -M 43 . More importantly, the common Z factor can be minimized in view of minimizing the capacitance C 111 -C 132  ( FIG. 6 ) and the capacitance C 411 -C 432  ( FIG. 7 ) of respective NFETs M 11 -M 13  and PFETs M 41 -M 43 . 
         [0031]    Referring to  FIG. 10 , a NFET write driver employs a logic return manager  42  and a variable power return network  52 . Manager  42  includes an inverter A 11 , a two-input AND gate A 12  and a two-input AND gate A 13 . Network  52  includes three (3) NFETs M 21 -M 23  connected in parallel between a drain node DN 2  and a source node SN 2  with write head L 1  being connected to drain node DN 2 . For a voltage mode, ground GND is connected to source node SN 2 . Alternatively for a current mode, as indicated by the dashed lines, current source I S  is connected to source node SN 2  instead of ground GND. Inverter A 11  provides a gate signal G_ 21  to a gate terminal of a NFET M 21  based on an inversion of a control signal IN_ 2 _N into gate signal G_ 21 . AND gate A 12  provides a gate signal G_ 22  to a gate terminal of a NFET M 22  based on a Boolean AND function of control signals IN_ 2 _N and S 2 _ON. AND gate A 13  provides a gate signal O_ 23  to a gate terminal of a NFET M 23  based on a Boolean AND function of control signals IN_ 2 _N and S 3 _ON. 
         [0032]    Referring to  FIG. 11 , a PFET write driver employs a logic return manager  22  and a variable power return network  32 . Manager  22  includes an inverter A 14 , an inverter A 15 , a two-input OR gate A 16 , an inverter A 17  and a two-input OR gate A 18 . Network  32  includes three (3) PFETs M 31 -M 33  connected in parallel between a source node SN 3  and a drain node DN 3  with voltage source V S  being connected to source node SN 3  and write head L 1  being connected to drain node DN 3 . Inverter A 14  provides a gate signal G_ 31  to a gate terminal of a PFET M 31  based on an inversion of a control signal N_ 1 _P into gate signal G_ 41 . Inverter A 1  Sand OR gate A 16  provide a gate signal G_ 32  to a gate terminal of a PFET M 32  based on a Boolean OR function of control signal IN_ 1 _P and an inversion of control signal S 2 _ON. Inverter A 17  and OR gate A 18  provide a gate signal G_ 33  to a gate terminal of a PFET M 33  based on a Boolean OR function of control signal IN_ 1 _P and an inversion of control signal S 3 _ON. 
         [0033]    In operation, the NFET write driver of  FIG. 10  and PFET write driver of  FIG. 11  are switched in unison between a conductive state and a nonconductive state based on a selection of an operational power mode among three (3) power modes via the control signals as represented by power mode tables  63  and  64  shown in respective  FIGS. 12 and 13 . Each power mode represents a different switching configuration of NFETs M 2 ′-M 23  and PFETs M 3 -M 33  whereby the control signals N_ 2 _N, IN_ 1 _P, S 2 _ON and S 3 _ON can be utilized to select a desired operating mode as best shown in  FIG. 12 . As best shown in  FIG. 13 , each power mode provides a different magnitude of write current I W  based on its particular switching configuration of NFETs M 21 -M 23  and PFETs M 31 -M 33  between a conductive state (“CONDUCT STATE”) and a nonconductive state (“NONCON STATE”). Specifically, in view of NFETs M 21 -M 23  and PFETs M 31 -M 33  having the same Z factor, each power mode provides a magnitude m(I Z ) as a function of a common size of the n number of conductive NFETs among switches NFETs M 21 -M 23  and the n number of conductive PFETs among PFETs M 31 -M 33 . More importantly, the common Z factor can be minimized in view of minimizing the capacitance C 211 -C 232  ( FIG. 10 ) and the capacitance C 311 -C 332  ( FIG. 11 ) of respective NFETs M 21 -M 23  and PFETs M 31 -M 33 . 
         [0034]      FIG. 14  illustrates an integration of the NFET write drivers and PFET write drivers shown in  FIGS. 6 ,  7 ,  10  and  11  into a voltage mode “H” configuration write driver circuit connected between a voltage source VS and ground GND. As shown in  FIG. 14 , control signals provided from an external controller are used to select a power mode of the write driver circuit as previously described herein in  FIGS. 8 ,  9 ,  12  and  13 . Furthermore, in a CMOS Off Chip Driver embodiment, a control signal IN_ 1  can be substituted for control signals IN_ 1 _P and IN_ 1 _N and a control signal IN_ 2  can be substituted for control signals IN 13    2 _P and IN_ 2 _N. 
         [0035]    Referring to  FIG. 14 , resistors R 1  and R 2  and inductor L 1  may be chosen to optimize the circuit depending on the desired write current and write frequency of the application. Typical values for the embodiment shown in  FIG. 14  are as follows. The write clock cycle frequency is in the range of 120-350 MHz. Voltage source V S  is programmable in the range of 3-6 volts in order to change the magnitude of write current I W  by as much as 40-50%. Resistors R 1  and R 2  have a resistance of 200Ω, and inductor L 1  has a typical inductance of 150 nanohenries. 
         [0036]      FIG. 15  illustrates an integration of the NFET write drivers and PFET write drivers shown in  FIGS. 6 ,  7 ,  10  and  11  into a current mode “H” configuration write driver circuit connected between voltage source V S  and current source I S . As shown in  FIG. 15 , control signals provided from an external controller are used to select a power mode of the write driver circuit as previously described herein in  FIGS. 8 ,  9 ,  12  and  13 . 
         [0037]    Typical values for the embodiment shown in  FIG. 15  are as follows. The write clock cycle frequency is in the range of 120-350 MHz. Current source I s  is programmable in a typical range of 10 to 50 milliamps in order to change the magnitude of write current I W , and inductor L 1  has a typical inductance of 150 nanohenries. 
         [0038]      FIG. 16  illustrates an embodiment of a magnetic tape recorder or tape drive system  120  incorporating a write driver circuit (“VPWDC”)  200  of the present invention (e.g., the voltage mode driver shown in  FIG. 14  or the current mode driver shown in  FIG. 15 . A tape drive controller  122  provides a motor control signal to rotate tape reels  124  and move magnetic tape  123  across the read/write transducer head  121 . Read/write channel  125  transmits read/write signals between the read/write transducer  121  and the controller  122 . The data is communicated through I/O channel  129  with host  131 . Lateral positioning of the transducer  121  with respect to the tape  123  is accomplished by positioning actuator  127 . The lateral repositioning is required to access the various tracks of the tape  123  with the transducer  121 . A servo system may be employed for accurate lateral repositioning of the transducer  121 . An exemplary servo system includes a servo detector  126  to detect both the track that the head is currently on and whether the head is off center. Controller  122  indicates the track address of a desired new track to position error detection controller  128  for repositioning the head. Servo detector  126  indicates the current track to position error detection controller  128 , and the controller provides a servo position error signal to positioning actuator  127  which repositions the transducer  121  to the new track. The servo system also provides track following signals to positioning actuator  127  so that the tracks on tape  123  may be closely spaced. Controller  122  uses logic control signals at Power on Reset to activate detector  200  whereby, upon a detection of an open write condition, controller  122  will report a RAS error to thereby flag a need for drive  200  to be serviced or replaced. 
         [0039]    Referring to  FIGS. 3-16 , those having ordinary skill in the art will appreciate numerous benefits and advantages of the illustrated embodiments of the present invention including, but not limited to, an efficient and effective technique for maximizing the magnitude of write current I W  required for all applications while minimizing the AC power needed to operate the write driver circuit. Furthermore, those having ordinary skill in the art will appreciate how to apply the inventive principles illustrates in  FIGS. 3-20  to more or less complex write drivers than the write drivers shown in  FIGS. 14 and 15 . Additionally, the write drivers of a network may or may not have a common Z factor, although a common Z factor is preferred. In particular, for FETs, the common Z factor of the FETs is defined as a common width of the FETs divided by a common length of the FETs. 
         [0040]    Those having ordinary skill in the art may develop other embodiments of the present invention in view of the inventive principles of the present invention described herein. The terms and expression which have been employed in the foregoing specification are used herein as terms of description and not of limitations, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or segments thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.