Abstract:
A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of priority to Japanese Patent Application Nos. 2006-196190 and 2006-196191, filed Jul. 18, 2006 and Jul. 18, 2006, respectively, of which full contents are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a data processing circuit and a data processing method. 
     2. Description of the Related Art 
       FIG. 10  illustrates the configuration of a data input processing system  1  that is applied to car audio systems or the like. The data input processing system  1  includes a main device  10  and a display device  20  that is detachable from the main device  10 . 
     The main device  10  is equipped with mechanisms and circuits to achieve the functions of a car audio system such as a CD or DVD player, a radio receiver, etc. On the other hand, the display device  20  is provided with a display panel  21  to indicate information on the control or the operation of the car audio system, a data input processing circuit  22 , a key scanning circuit  23 , a rotary encoder  24 , and a remote control receiver  25 . 
     The main device  10  is equipped with a controller  11  to control indication on the display panel  21 , and to receive signals from the key scanning circuit  23 , the rotary encoder  24 , and the remote control receiver  25 . The controller  11  inputs a clock signal CL, a data input signal DI, and a chip enable signal CE to an input interface  221  in the display device  20  for the display control or for the reception of the signals. 
     The input processing circuit  22  in the display device  20  includes the input interface  221  that communicates with the controller  11 , a control register  222  that memorizes input data that is input from the controller  11 , a display control unit  223  that controls the display panel  21  based on display data that is input as the input data, a signal generating unit  224  that provides a driving signal such as an operational clock signal for the display control unit  223 , and a signal selecting circuit  225  that selects either a key scanning signal or a rotary encoder detecting signal (hereinafter, these are collectively referred to as a slow processing signal), corresponding to the address data that is input from the controller  11  as a data-output request to be memorized at the control register  222 , and that outputs the selected slow processing signal. 
     The display device  20  is also equipped with a circuit (e.g., remote control receiver  25 ) that generates a signal with a short sampling period (hereinafter, referred to as a fast processing signal). The fast processing signal cannot be synchronized with a clock signal that is input from the main device  10  due to the insufficient processing capacity of a processor mounted on the display device  20 , and therefore, it is output to the main device  10  via an independent signal line different from a signal line for the slow processing signals. (refer to Japanese Patent Application Laid-Open Publication No. 8-221174) 
     In the case, as above, that individual signal lines to output a fast processing signal and a slow processing signal are arranged independently, the number of lines to connect the main device  10  and the display device  20  increased, and thus wiring becomes complicated. Thereby, the possibility of such a trouble as a faulty connection increases, and the manufacturing cost also increases due to the increased number of parts. 
     SUMMARY OF THE INVENTION 
     A data processing circuit according to an aspect of the present invention, comprises: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller. 
     Other features of the present invention will become apparent from descriptions of this specification and of the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For more thorough understanding of the present invention and advantages thereof, the following description should be read in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic view illustrating a configuration of a data input processing system  1  according to an embodiment of the present invention; 
         FIG. 2  is a timing chart showing examples of a slow processing signal and a fast processing signal according to an embodiment of the present invention; 
         FIG. 3  is a timing chart showing an operation of an input interface  221  when input data is input from a main device  10  according to an embodiment of the present invention; 
         FIG. 4  is a timing chart showing an operation of an input interface  221  when a data-output request is made, according to an embodiment of the present invention; 
         FIG. 5  is a timing chart showing a temporal relationship among a chip enable signal CE, a data input signal DI that are input from a main device  10 , and output data DO that is output from a multiplexer  226 , according to an embodiment of the present invention; 
         FIG. 6  is a schematic view illustrating a configuration of a data input processing system  1  according to an embodiment of the present invention; 
         FIG. 7  is a timing chart showing the concrete operation of a data input processing system  1  according to an embodiment of the present invention; 
         FIG. 8  is a schematic view illustrating a configuration of a data input processing system  1  according to an embodiment of the present invention; 
         FIG. 9  is a timing chart showing an operation of a data input processing system  1  according to an embodiment of the present invention; and 
         FIG. 10  is a schematic view illustrating a configuration of a data input processing system  1  applied to car audio systems or the like, according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     At least the following details will become apparent from descriptions of this specification and of the accompanying drawings. 
     In a data input processing circuit and a controller that are applied to a car audio system, etc. including a main device and a display device separate therefrom, a signal with a long sampling period that is output from a key scanning circuit or a rotary encoder and a signal with a short sampling period that is output from a remote control unit are output to the controller via a small number of signal lines, both the above signals being output from the data input processing circuit included in the display device to the controller included in the main device. 
     Outputting a slow processing signal (first digital signal) and a fast processing signal (second digital signal) to the controller by time-division multiplexing, it is possible to output the slow processing signal and the fast processing signal to the controller via a small number of signal lines. Thereby, it is possible to attain simple wiring, to reduce the possibility of a trouble such as a faulty connection, and to reduce manufacturing costs as the result of a reduced number of parts. 
     First Embodiment 
     An embodiment according to the present invention will be explained hereinafter.  FIG. 1  illustrates the configuration of a data input processing system  1  that is applied to a car audio system to be explained as an embodiment of the present invention. The data input processing system  1  includes a main device  10  and a display device  20  that is separable from the main device  10 . 
     The main device  10  includes mechanisms and circuits to achieve the functions of a car audio system such as a CD or DVD player, a radio receiver, etc. The display device  20  includes a display panel  21  to indicate information on the control or the operation of the car audio system, a data input processing circuit  22 , a key scanning circuit  23 , a rotary encoder  24 , and a remote control receiver  25 . 
     In the following explanation, a digital signal with a long sampling period as a signal that is output from the key scanning circuit  23  or the rotary encoder  24  is referred to as a slow processing signal (first digital signal), and a digital signal with a short sampling period as a signal that is output from the remote control receiver  25  is referred to as a fast processing signal (second digital signal). In this embodiment, the sampling period of a slow processing signal is assumed to be 500 μs and the sampling period of a fast processing signal is assumed to be 50 μs (see  FIG. 2 ). That is, the sampling period of the slow processing signal by a controller  11  is longer than the sampling period of the fast processing signal by the controller  11 . 
     The main device  10  is equipped with the controller  11  for the display control of the display panel  21  and for the reception of signals from the key scanning unit  23 , the rotary encoder  24 , and the remote control receiver  25 . The controller  11  and an input interface  221  are connected by three signal lines. The controller  11  inputs a clock signal CL, a data input signal DI, and a chip enable signal CE to the input interface  221  in the display device  20  via the signal lines for the display control or for the reception of the signals. The controller  11  and a multiplexer  226  are connected by a single signal line, and output data DO is output from the multiplexer  226  to the controller  11  via the signal line. 
     The controller  11  is equipped with a synchronous data processing unit  111  to process a slow processing signal and an asynchronous data processing unit  112  to process a fast processing signal, that are input as the output data DO from the display device  20 . The slow processing signal is input to the synchronous data processing unit  111  being synchronized with the clock signal CL. On the other hand, the fast processing signal is input to the asynchronous data processing unit  112  by digital-through, being asynchronous with the clock signal CL. The digital-through means that an input signal is output both without modification in its wave form and without synchronization. The asynchronous data processing unit  112  processes the fast processing signal, that is input by the digital-through, at a sampling frequency equal to or higher than a predetermined sampling period for the fast processing signal (50 μs). 
     The data input processing circuit  22  in the display device  20  includes the input interface  221 , a control resister  222 , a display control unit  223 , a signal generating unit  224 , a signal selecting circuit  225 , and the multiplexer (MPX)  226 . The input interface  221  receives the clock signal CL, the data input signal DI, and the chip enable signal CE that are input from the main device  10 , and stores the data, that is input as the input signal DI, in the control register  222 . 
       FIG. 3  is a timing chart showing the operation of the input interface  221  when input data is input from the main device  10 . In this case, the data input signal DI includes an address data (adrs 1 ) and the input data. The input data includes, e.g., display data that is described later and flags that are referred to when the multiplexer  226  selects one out of a plurality of fast processing signals. 
       FIG. 4  is a timing chart showing the operation of the input interface  221  and the multiplexer  226  when a data-output request is made by the main device  10 . In this case, an address data (adrs 2 ) designating a slow processing signal to be requested to be output, is input as the data input signal DI. The multiplexer  226  then outputs the output data DO corresponding to the address data (adrs 2 ) to the main device  10 . 
     The display control unit  223  in the data input processing circuit  22  controls the display panel  21  based on display data that is input as input data from the main device  10  and is memorized at the control register  222 . The signal generating unit  224  provides a drive signal to the display control unit  223 . 
     The signal selecting circuit  225  selects a slow processing signal (key scanning signal or rotary encoder detecting signal), that corresponds to the address data (adrs 2 ) that is input from the main device  10  as a data-output request and is memorized at the control register  222 , and outputs the selected slow processing signal to the multiplexer  226 . The signal selecting circuit  225  is a parallel/serial converting circuit, and a slow processing signal is input to the signal selecting circuit  225  as a parallel signal, and the slow processing signal that is output from the signal selecting circuit  225  is input to the multiplexer  226  as a serial signal that is synchronous with the clock signal CL. 
     The multiplexer  226  includes a first circuit  226 A that multiplexes a slow processing signal input from the signal selecting circuit  225  and a fast processing signal input from the remote control receiver  25  by time-division multiplexing, and a second circuit  226 B that outputs a time-division multiplexed signal to the main device  10  as the output data DO. The output periods of the slow and the fast processing signals, that include a single frame of the time-division multiplex, can be preset at the multiplexer  226 . Here, the single frame is assumed to be 500 μs, and the output period of the slow processing signal is assumed to be set at 50 μs and the output period of the fast processing signal is assumed to be set at 450 μs. 
       FIG. 5  is a timing chart showing the temporal relationship among the chip enable signal CE, the data input signal DI that are input from the main device  10 , and the output data DO that is output from the multiplexer  226 . An address data (adrs 2 ) is first input as the data input signal DI, and thereby, the output request of a slow processing signal is made by the main device  10 . In response to this, a slow processing signal (data 2 ) is output as the output data DO (t 1  to t 2 ). 
     An address data (adrs 1 ) and an input data are input from the main device  10  as the data input signal DI (t 3  to t 5 ). 
     The address data (adrs 2 ) is input from the main device  10  as the data input signal DI, and thereby, the output request of the slow processing signal is made by the main device  10  (t 6  to t 7 ), and in response to this, the slow processing signal (data 2 ) is output as the output data DO (t 7  to t 8 ). 
     The address data (adrs 2 ) is input from the main device  10  as the data input signal DI, and thereby, the output request of the slow processing signal is made by the main device  10  (t 9  to t 10 ), and in response to this, the slow processing signal (data 2 ) is output as the output data DO (t 10  to t 11 ). 
     As shown in the figure, the multiplexer  226  outputs a fast processing signal by the digital-through as the output data DO during the period other than the output period for a slow processing signal. That is, the multiplexer  226  outputs the slow processing signal in response to a request from the controller  11 , and outputs the fast processing signal during a period except a period when the slow processing signal is output. 
     Thus the data input processing system  1  has a mechanism to transmit a slow processing signal from the key scanning circuit  23  or the rotary encoder  24  and a fast processing signal from the remote control receiver  25  through a single serial signal line by time-division multiplexing. Hence the number of signal lines connecting the main device  10  and the display device  20  can be reduced, and simple wiring is attained. A trouble such as a faulty connection is also diminished, and manufacturing costs are reduced as the result of a reduced number of parts. 
     Periods other than output periods for a slow processing signal in time-division multiplexing, i.e., output periods for a fast processing signal by the digital-through can be utilized as periods for data input from the controller  11  to the input interface  221 . For a concrete example, the periods can be utilized as periods for display data input from the controller  11  to the input interface  221 , and thereby, the display data can be efficiently input from the main device  10  to the display device  20 . 
     In the case that no output request for a slow processing signal is made by the main device  10  during an output period for a slow processing signal, the output period for the slow processing signal may be utilized to output a fast processing signal. That is, if no request is made to output the slow processing signal from the controller  11 , the multiplexer  226  outputs the fast processing signal during a period when the slow processing signal should be output. Such this mechanism can be realized, for example, in the case that any output request is not made, by inputting the address data (adrs 1 ), that is for changing the setting of the output periods of time-division multiplex, from the controller  11  to the display device  20 , and thereby, changing the output period for time-division multiplex from the multiplexer  226 . With such a mechanism, a fast processing signal can be efficiently output to the controller  11 . 
     Second Embodiment 
     Since a fast processing signal from a remote control receiver  25  is input to a multiplexer  226  only when a remote controller is operated, a fast processing signal does not need to be output unless a fast processing signal is input. Therefore, it is preferred to halt the digital-through output of a fast processing signal in this case, from the viewpoint of the reduction of processing load on and of electric power consumption by the multiplexer  226 . 
     By the mechanism explained below, it is attained that a fast processing signal is output from the multiplexer  226  only when there is a signal input from the remote control receiver  25 .  FIG. 6  illustrates the configuration of a data input processing system  1  with the mechanism. 
     As shown in the figure, in the data input processing system  1 , a remote control signal, that is output from the remote control receiver  25 , is input not only to the multiplexer  226  but also to a signal selecting circuit  225 . On the occasion of the output of a remote control signal from the remote control receiver  25 , a slow processing signal that is synchronizable (hereinafter, referred to as a synchronous signal) by the signal selecting circuit  225  is output. The slow processing signal is, e.g., a signal that shifts between “High” and “Low” states at a frequency that allows sampling by the signal selecting circuit  225 , or a signal at a continuous “High” state for a predetermined period. 
     The specific operation of the data input processing system  1  is explained referring to  FIG. 7 . As shown in  FIG. 6 , a remote control signal that is output from the remote control receiver  25  is also input to the signal selecting circuit  225 . 
     As shown in  FIG. 7 , a controller  11  inputs an address data (adrs 2 ) indicating that the signal selecting circuit  225  is required to output a remote control signal input from the remote control receiver  25  at a predetermined timing, to an input interface  221  (t 0  to t 1 ). In the case that a synchronous signal is output according to the output of the remote control signal during an output period corresponding to the address data (adrs 2 ), the synchronous signal is output as the output data DO (data 2 ) from the multiplexer  226  to the controller  11  (t 1  to t 2 ). 
     When a synchronous signal is input, the controller  11  inputs an address data (adrs 1 ) indicating that the multiplexer  226  is required to start the digital-through output of a remote control signal by time-division multiplexing, to the input interface  221  (t 3  to t 4 ). Thereby, the multiplexer  226  starts the digital-through output of a fast processing signal that is time-division multiplexed with a slow processing signal, at the time t 4 ′ when a chip enable signal CE falls. 
     During the period of t 5  to t 6 , the address data (adrs 2 ) designating a slow processing signal to be requested to be output, is input as a data input signal DI, and corresponding to the address data (adrs 2 ), the slow processing signal is output as the output data DO from the multiplexer  226  to the main device  10  (t 6  to t 7 ). 
     When the input of a fast processing signal is stopped, the controller  11  inputs an address data (adrs 1 ) indicating that the multiplexer  226  is required to halt the digital-through output of a remote control signal by time-division multiplexing, to the input interface  221  (t 8  to t 9 ). Thereby, the multiplexer  226  stops the digital-through output of the fast processing signal that is time-division multiplexed with the slow processing signal, at the time t 9 ′ when a chip enable signal CE falls. 
     Employing the above mechanism, a fast processing signal is output from the multiplexer  226  only when a signal is input from the remote control receiver  25  (third circuit). Thereby, processing load on and power consumption by the multiplexer  226  can be reduced. 
     Third Embodiment 
     In the case, for example, that a plurality of remote control signals are input, or that another fast processing signal such as a USB signal or the like exists, a plurality of fast processing signals may need to be output to a main device  10  depending upon the configuration of a data input processing system  1 . In such the cases, employing the following mechanism for example, the plurality of fast processing signals are output to the main devise  10  through a single signal line for the output data DO. 
       FIG. 8  illustrates the configuration of a data input processing system  1  to explain the mechanism. As shown in the figure, in the data input processing system  1 , two remote control signals that are output from two remote control receivers  25  and  26  are input to a multiplexer  226 . As the case in the second embodiment, the remote control signals are also input to a signal selecting circuit  225 . 
       FIG. 9  is a timing chart showing the operation of the data input processing system  1  in this embodiment. As shown in the figure, a controller  11  inputs an address data (adrs 2 ) indicating that the signal selecting circuit  225  is required to output a signal from the remote control receiver  25  at a predetermined timing, to an input interface  221  (t 0  to t 1 ). The controller  11  also inputs the address data (adrs 2 ) indicating that the signal selecting circuit  225  is required to output a signal from the remote control receiver  26  at a predetermined timing, to the input interface  221  (t 3  to t 4 ). As the case in the second embodiment, the controller  11  determines if a synchronous signal is output from either the remote control receiver  25  or  26  (third circuit). The controller  11  can determine which remote control receivers a synchronous signal is output from, since one of fast processing signals is designated by the above address data (adrs 2 ). 
     In the case that a synchronous signal is output, the controller  11  inputs an address data (adrs 1 ) indicating that a remote control receiver outputting the synchronous signal is required to start the digital-through output of a remote control signal, to the input interface  221  (t 6  to t 7 ). Thereby, the multiplexer  226  starts the digital-through output of a fast processing signal that is time-division multiplexed with the slow processing signal, from the remote control receiver which outputs the synchronous signal, at the time t 7 ′ when a chip enable signal CE falls. 
     When the input of a fast processing signal is stopped, the controller  11  inputs an address data (adrs 1 ) indicating that the multiplexer  226  is required to halt the digital-through output of a remote control signal by time-division multiplexing, to the input interface  221  (t 11  to t 12 ). Thereby, the multiplexer  226  stops the digital-through output of the fast processing signal that is time-division multiplexed with the slow processing signal, at the time t 13  when a chip enable signal CE falls. 
     Employing the above mechanism, even in the case that a plurality of fast processing signals need to be output to the main device  10 , e.g., such a condition that a plurality of remote control signals are input or that another fast processing signal such as a USB signal or the like exists, a plurality of fast processing signals can be output to the main device  10  through a single signal line for the output data DO. 
     In the above embodiments, the number of fast processing signals is not limited as described above but larger numbers of fast processing signals may exist. 
     The above embodiments of the present invention are simply for facilitating the understanding of the present invention and are not in any way to be construed as limiting the present invention. The present invention may variously be changed or altered without departing from its spirit and encompass equivalents thereof. The number of slow processing signals is not limited to the above but larger numbers of slow processing signals may exist.