Abstract:
A nonvolatile memory cell with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the nonvolatile memory cell and the contact region of the nonvolatile memory cell. The charge storage state of the charge trapping structure affects the measured current.

Description:
RELATED APPLICATIONS  
       [0001]     This application is related to co-pending U.S. application Ser. No. 10/______, filed on the same date as the present application entitled METHOD AND APPARATUS FOR OPERATING A NON-VOLATILE MEMORY ARRAY, and to co-pending U.S. application Ser. No. 10/______ filed on the same date as the present application entitled METHOD AND APPARATUS FOR OPERATING A NON-VOLATILE MEMORY ARRAY. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to electrically programmable and erasable non-volatile memory, and more particularly to charge trapping memory that reads the contents of the charge trapping structure of the memory cell with great sensitivity.  
         [0004]     2. Description of Related Art  
         [0005]     Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry name PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.  
         [0006]     Conventional memory cell structures rely on the reverse read operation to determine the contents of the memory structure. However, the reverse read technique effectively couples together multiple locations of the charge trapping structure, even when only portion of the charge trapping structure contains data of interest. This dependence constrains the difficulty of using the charge trapping structure as nonvolatile memory, by narrowing the sensing window of currents measured from the reverse read technique.  
         [0007]     Thus, a need exists for a charge trapping memory cell that can be read without suffering substantial coupling between multiple locations of the charge trapping structure.  
       SUMMARY OF THE INVENTION  
       [0008]     A method of operating a memory cell, an architecture for an integrated circuit including such a memory cell, and a method of manufacturing such memory, are provided.  
         [0009]     A nonvolatile memory includes a body region, a contact region coupled to the body region, a bottom dielectric coupled to the body region, a charge trapping structure coupled to the bottom dielectric, a top dielectric coupled to the charge trapping structure, and a gate coupled to the top dielectric. The charge trapping structure has a charge storage state, which stores one bit or multiple bits, depending on the application and design of the memory cell.  
         [0010]     The logic applies a bias arrangement to determine the charge storage stage of the memory cell. The logic measures current flowing in response to the applied bias arrangement, to determine the charge storage stage of the memory cell. The measured current flows between the body region and the contact region.  
         [0011]     The bias arrangement applied by the logic causes a first voltage difference between the gate the contact region, and a second voltage difference between the body region and the contact region. The first voltage difference and the second voltage difference cause sufficient band-to-band tunneling current for the current measurement. However, the first voltage difference and the second voltage differences fail to change the charge storage state. Thus, the read operation is not destructive of the data stored in the charge trapping structure. In some embodiments the first voltage difference is at least about 5 V between the gate and the contact region, and the second voltage difference is less than about 5 V between the body region and the contact region.  
         [0012]     The voltage difference between the gate and the contact region creates an electric field which causes band bending in the contact region. The degree of band bending is affected by the charge storage state of the charge trapping structure, resulting in a band-to-band tunneling current in the contact region that varies with the charge storage state.  
         [0013]     In some embodiments, the body region is a well in a semiconductor substrate. In other embodiments, the body region is simply the semiconductor substrate.  
         [0014]     In some embodiments, the logic applies a second bias arrangement to adjust the charge storage state by increasing a net positive charge in the charge trapping structure, and applies a third bias arrangement to adjust the charge storage state by increasing a net negative charge in the charge trapping structure. In some embodiments, the second bias arrangement corresponds to programming and the third bias arrangement corresponds to erasing, and in other embodiments the second bias arrangement corresponds to erasing and the third bias arrangement correspond to programming. As generally used herein, programming refers to adding limited amounts of charge in the charge trapping structure, such as by the addition of holes or electrons to the charge trapping structure. Also as generally used herein, erasing refers to resetting the charge storage state of the charge trapping structure, such as by adding a single charge type throughout the charge trapping structure until equilibrium is reached. The invention encompasses both products and methods where programming refers to making the net charge stored in the charge trapping structure more negative or more positive, and products and methods where erasing refers to making the net charge stored in the charge trapping structure more negative or more positive.  
         [0015]     Net positive charge is increased in the charge trapping structure via current mechanisms such as band-to-band hot hole tunneling, for example from the gate, contact region, or body region. Net negative charge is increased in the charge trapping structure via current mechanisms such as electron tunneling, Fowler-Nordheim tunneling, channel hot electron injection current, and channel initiated secondary electron injection current, for example from the gate, contact region, or body region. In some embodiments, the measured current is at least about 10 times greater for the charge storage state adjusted by one of the second bias arrangement and the third bias arrangement than the measured current for the charge storage state adjusted by the other of the second bias arrangement and the third bias arrangement, for example about 100 nA for one measurement and about 1 nA for the other measurement.  
         [0016]     Other embodiments of the technology described above include a method for operating a memory cell, and a method of manufacturing nonvolatile memory according to the described technology.  
         [0017]     Other aspects and advantages of the technology presented herein can be understood with reference to the figures, the detailed description and the claims, which follow. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]      FIG. 1A  is a simplified diagram of a charge trapping memory cell, showing a read operation with a negative voltage on the gate being performed on a charge trapping structure with a charge storage state having relatively more net positive charge than  FIG. 1B . The memory cell has an n-type contact region.  
         [0019]      FIG. 1B  is a simplified diagram of a charge trapping memory cell, showing a read operation with a negative voltage on the gate being performed on a charge trapping structure with a charge storage state having relatively more net negative charge than  FIG. 1A . The memory cell has an n-type contact region.  
         [0020]      FIG. 1C  is a simplified diagram of a charge trapping memory cell, showing a read operation with a positive voltage on the gate being performed on a charge trapping structure with a charge storage state having relatively more net positive charge than  FIG. 1D . The memory cell has a p-type contact region.  
         [0021]      FIG. 1D  is a simplified diagram of a charge trapping memory cell, showing a read operation with a positive voltage on the gate being performed on a charge trapping structure with a charge storage state having relatively more net negative charge than  FIG. 1C . The memory cell has a p-type contact region.  
         [0022]      FIG. 1E  shows the circuit symbol for a charge trapping memory cell with a single contact region.  
         [0023]      FIG. 1F  shows the circuit symbol for two charge trapping memory cells each with a single contact region coupled in series.  
         [0024]      FIG. 2A  is a simplified diagram of a charge trapping memory cell with an n-type contact region, showing a program operation being performed that increases net positive charge in the charge trapping structure with holes from the contact region.  
         [0025]      FIG. 2B  is a simplified diagram of a charge trapping memory cell with an n-type contact region, showing an erase operation being performed on the charge trapping structure, with holes moving in the general direction from the gate to the contact and body regions.  
         [0026]      FIG. 2C  is a simplified diagram of a charge trapping memory cell with an n-type contact region, showing another erase operation being performed on the charge trapping structure, with holes moving in the general direction to the gate from the contact and body regions.  
         [0027]      FIG. 2D  is a simplified diagram of a charge trapping memory cell with a p-type contact region, showing a program operation being performed that increases net positive charge in the charge trapping structure with holes from a p-type substrate or well moving across an n-type body region.  
         [0028]      FIG. 2E  is a simplified diagram of a charge trapping memory cell with a p-type contact region, showing an erase operation being performed on the charge trapping structure, with holes moving in the general direction from the gate to the contact and body regions.  
         [0029]      FIG. 2F  is a simplified diagram of a charge trapping memory cell with a p-type contact region, showing another erase operation being performed on the charge trapping structure, with holes moving in the general direction to the gate from the contact and body regions.  
         [0030]      FIG. 3A  is a simplified diagram of a charge trapping memory cell with a p-type contact region, showing a program operation being performed that increases net negative charge in the charge trapping structure with electrons from the contact region.  
         [0031]      FIG. 3B  is a simplified diagram of a charge trapping memory cell with a p-type contact region, showing an erase operation being performed on the charge trapping structure, with electrons moving in the general direction from the gate to the contact and body regions.  
         [0032]      FIG. 3C  is a simplified diagram of a charge trapping memory cell with a p-type contact region, showing another erase operation being performed on the charge trapping structure, with electrons moving in the general direction to the gate from the contact and body regions.  
         [0033]      FIG. 3D  is a simplified diagram of a charge trapping memory cell with an n-type contact region, showing a program operation being performed that increases net negative charge in the charge trapping structure with electrons from an n-type substrate or well moving across a p-type body region.  
         [0034]      FIG. 3E  is a simplified diagram of a charge trapping memory cell with an n-type contact region, showing an erase operation being performed on the charge trapping structure, with electrons moving in the general direction from the gate to the contact and body regions.  
         [0035]      FIG. 3F  is a simplified diagram of a charge trapping memory cell with an n-type contact region, showing another erase operation being performed on the charge trapping structure, with electrons moving in the general direction to the gate from the contact and body regions.  
         [0036]      FIG. 4A  is a graph showing an erase operation being performed on different memory cells.  
         [0037]      FIG. 4B  is a graph showing a program operation being performed on a charge trapping structure of a memory cell.  
         [0038]      FIG. 4C  is a graph showing a program operation being performed on another charge trapping structure of another memory cell.  
         [0039]      FIG. 5A  is a simplified diagram of charge trapping memory cells with an p-type contact region having an isolation region between adjacent charge trapping memory cells.  
         [0040]      FIG. 5B  is a simplified diagram of charge trapping memory cells with a n-type contact region having an isolation region between adjacent charge trapping memory cells.  
         [0041]      FIG. 6A  is a simplified diagram of charge trapping memory cells with a p-type contact region without an isolation region between adjacent charge trapping memory cells.  
         [0042]      FIG. 6B  is a simplified diagram of charge trapping memory cells with an n-type contact region without an isolation region between adjacent charge trapping memory cells.  
         [0043]      FIG. 7A  is a simplified diagram of charge trapping memory cells with a p-type contact region and ONO stack continuous through the string of charge trapping memory cells having an isolation region between adjacent charge trapping memory cells.  
         [0044]      FIG. 7B  is a simplified diagram of charge trapping memory cells with an n-type contact region and ONO stack continuous through the string of charge trapping memory cells having an isolation region between adjacent charge trapping memory cells.  
         [0045]      FIGS. 8A and 8B  are simplified diagrams from the X-direction and Y-direction respectively of a string of charge trapping memory cells with a p-type contact region without an isolation region between adjacent charge trapping memory cells in the X-direction, and with an isolation region between adjacent charge trapping memory cells in the Y-direction.  
         [0046]      FIGS. 9A and 9B  are simplified diagrams from the X-direction and Y-direction respectively of a string of charge trapping memory cells with a n-type contact region without an isolation region between adjacent charge trapping memory cells in the X-direction, and with an isolation region between adjacent charge trapping memory cells in the Y-direction.  
         [0047]      FIG. 10  is a simplified diagram of strings of charge trapping memory cells, showing an erase operation being performed on the strings of charge trapping memory cells, with a negative voltage applied to the gates relative to the body regions.  
         [0048]      FIG. 11  is a simplified diagram of strings of charge trapping memory cells, showing an erase operation being performed on the strings of charge trapping memory cells, with a positive voltage applied to the gates relative to the body regions.  
         [0049]      FIG. 12  is a simplified diagram of strings of charge trapping memory cells, showing a programming operation being performed on selected memory cells of the strings of charge trapping memory cells.  
         [0050]      FIG. 13  is a simplified diagram of strings of charge trapping memory cells, showing a read operation being performed on the strings of charge trapping memory cells.  
         [0051]      FIG. 14  is a simplified diagram of an array of charge trapping memory cells, showing an erase operation being performed on the array of charge trapping memory cells, with a negative voltage applied to the gates relative to the body regions.  
         [0052]      FIG. 15  is a simplified diagram of an array of charge trapping memory cells, showing an erase operation being performed on the array of charge trapping memory cells, with a positive voltage applied to the gates relative to the body regions.  
         [0053]      FIG. 16  is a simplified diagram of an array of charge trapping memory cells, showing a programming operation being performed on selected memory cells of the array of charge trapping memory cells.  
         [0054]      FIG. 17  is a simplified diagram of an array of charge trapping memory cells, showing a read operation being performed on the array of charge trapping memory cells.  
         [0055]      FIG. 18  is a simplified diagram of an integrated circuit with an array of charge trapping memory cells and control circuitry. 
     
    
     DETAILED DESCRIPTION  
       [0056]      FIG. 1A  and  FIG. 1B  are simplified diagrams of a charge trapping memory cell, showing a read operation with a negative voltage on the gate being performed on a charge trapping structure. In  FIG. 1A , the charge trapping structure has a charge storage state with relatively more net positive charge than in  FIG. 1B . The charge trapping memory cell of  FIG. 1A  and  FIG. 1B  has a p-doped body region  170  and an n+-doped contact region  150 . The remainder of the memory cell includes a bottom dielectric structure  140  (bottom oxide) on the body region  170 , a charge trapping structure  130  on the bottom dielectric structure  140 , a top dielectric structure  120  (top oxide) on the charge trapping structure  130 , and a gate  110  on the oxide structure  120 . Representative top dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 5 to 10 nanometers, or other similar high dielectric constant materials, for example Al 2 O 3 . Representative bottom dielectrics include silicon dioxide and silicon oxynitride having a thickness of about 3 to 10 nanometers, or other similar high dielectric constant materials. Representative charge trapping structures include silicon nitride having a thickness of about 3 to 9 nanometers, or other similar high dielectric constant materials, including metal oxides such as Al 2 O 3 , HfO 2 , and others. The charge trapping structure may be a discontinuous set of pockets or particles of charge trapping material, or a continuous layer as shown in the drawing.  
         [0057]     The memory cell for PHINES-like cells has, for example, a bottom oxide with a thickness ranging from 2 nanometers to 10 nanometers, a charge trapping layer with a thickness ranging from 2 nanometers to 10 nanometers, and a top oxide with a thickness ranging from 2 nanometers to 15 nanometers.  
         [0058]     In some embodiments, the gate comprises a material having a work function greater than the intrinsic work function of n-type silicon, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including for example greater than about 5 eV. Representative gate materials include p-type poly, TiN, Pt, and other high work function metals and materials. Other materials having a relatively high work function suitable for embodiments of the technology include metals including but not limited to Ru, Ir, Ni, and Co, metal alloys including but not limited to Ru—Ti and Ni-T, metal nitrides, and metal oxides including but not limited to RuO 2 . High work function gate materials result in higher injection barriers for electron tunneling than that of the typical n-type polysilicon gate. The injection barrier for n-type polysilicon gates with silicon dioxide as the top dielectric is around 3.15 eV. Thus, embodiments of the present technology use materials for the gate and for the top dielectric having an injection barrier higher than about 3.15 eV, such as higher than about 3.4 eV, and preferably higher than about 4 eV. For p-type polysilicon gates with silicon dioxide top dielectrics, the injection barrier is about 4.25 eV, and the resulting threshold of a converged cell is reduced about 2 volts relative to a cell having an n-type polysilicon gate with a silicon dioxide top dielectric.  
         [0059]     In older memory cells, the material of a floating gate is an equipotential or nearly equipotential structure, such as highly doped polysilicon. Thus, charge that is added to the floating gate will tend to spread out evenly throughout the floating gate. If charge is added to the floating gate with the goal of raising the charge density of one portion of the floating gate, then because of the equipotential nature of the floating gate, typically sufficient charge must be added to the floating gate until the charge density of the entire floating gate is raised.  
         [0060]     In contrast with a floating gate, a charge trapping structure may be approximated as neither an equipotential nor nearly equipotential structure. When charge is added to the charge trapping structure, the added charge remains local to a portion of the charge trapping structure, rather than automatically spreading evenly throughout the charge trapping structure. Thus, when charge is added to the charge trapping structure with the goal of raising the charge density of one portion of the floating gate, the charge density of part of the charge trapping structure rises, while the charge density of the remainder of the charge trapping structure remains relatively unchanged. The requirement of the amount of added charge is much less for the charge trapping structure than for a comparable floating gate.  
         [0061]     In the diagram of  FIG. 1A , the charge trapping structure  130  of the memory cell has been programmed, for example via band-to-band hole injection into the charge trapping structure  130 . Prior to programming, the charge trapping structure  130  of the memory cell has been erased, for example via a channel reset operation injecting electrons via Fowler-Nordheim tunneling from the gate  110  to the charge trapping structure  130  and from the charge trapping structure  130  to the body region  170 .  
         [0062]     In the bias arrangement of  FIG. 1A  for reading the charge trapping structure  130 , the voltage of the gate  110  is −5 V, the voltage of the contact region  150  is 3 V, and the voltage of the body region  170  is 0 V. The memory cell of  FIG. 1B  is similar to memory cell of  FIG. 1A , except that a read operation is being performed on a charge trapping structure with higher net negative charge in the charge trapping structure  130 . In the bias arrangement of  FIG. 1B  for reading the charge trapping structure  130 , the voltage of the gate  110  is −5 V, the voltage of the contact region  150  is 3 V, and the voltage of the body region  170  is 0 V. In  FIGS. 1A and 1B , the bias arrangement is determined among the various terminals, such that the energy bands bend sufficiently to cause band-to-band current in the n+ doped contact region  150 .  
         [0063]     In this bias arrangements of  FIGS. 1A and 1B , the area of the junction between the p-doped body region  170  and the n+-doped contact region  150  displays the behavior of a reverse biased p-n junction. However, the gate voltage causes the energy bands to bend sufficiently such that band-to-band tunneling occurs in the n+-doped contact region  150 . The high doping concentration in the source  150 , the resulting high charge density of the space charge region, and the accompanying short length of the space charge region over which the voltage changes, contribute to the sharp energy band bending. Electrons in the valence band tunnel through the forbidden gap to the conduction band and drift down the potential hill, deeper into the n+-doped source  150 . Similarly, holes drift up the potential hill, away from the n+-doped contact region  150 , and toward the p-doped body region  170 .  
         [0064]     The voltage of the gate  110  controls the voltage of the portion of the body region  170  by the bottom dielectric structure  140  (bottom oxide). In turn, the voltage of the portion of the body region  170  by the bottom dielectric structure  140  (bottom oxide) controls the degree of band bending between the body region  170 , and the n+-doped contact region  150 . As the voltage of the gate  110  becomes more negative, the voltage of the portion of the body region  170  by the bottom dielectric structure  140  (bottom oxide) becomes more negative, resulting in deeper band bending in the n+-doped contact region  150 . More band-to-band current flows, as a result of at least some combination of 1) an increasing overlap between occupied electron energy levels on one side of the bending energy bands, and unoccupied electron energy levels on the other side of the bending energy bands, and 2) a narrower barrier width between the occupied electron energy levels and the unoccupied electron energy levels (Sze,  Physics of Semiconductor Devices,  1981).  
         [0065]     As mentioned above, in  FIG. 1A  the charge trapping structure  130  has relatively higher net positive charge, for example by being programmed and occupied by holes, whereas in  FIG. 1B  the charge trapping structure  130  has relatively higher net negative charge, for example by being erased and occupied with electrons. As a result, in accordance with Gauss&#39;s Law, when −5 V is applied to the gate  110 , the bottom dielectric structure  140  (bottom oxide) and the portion of the body region  170  by the bottom dielectric structure  140  is biased more negatively in  FIG. 1B  than  FIG. 1A . Thus, deeper band bending occurs between the contact region  150  and the body region  170  in  FIG. 1B  than  FIG. 1A , and more band band-to-band current flows between the contact region  150  and the body region  170  in the bias arrangement shown in  FIG. 1A  for reading the charge trapping structure  130 , than flows between the contact region  150  and the body region  170  in the bias arrangement shown in  FIG. 1B  for reading the charge trapping structure  130 .  
         [0066]      FIG. 1C  and  FIG. 1D  are simplified diagrams of a charge trapping memory cell, showing a read operation with a positive voltage on the gate being performed on a charge trapping structure. The charge trapping memory cell of  FIG. 1C  and  FIG. 1D  has an n-doped body region  170  and a p+-doped contact region  150 , unlike the charge trapping memory cell of  FIG. 1A  and  FIG. 1B  that has a p-doped body region  170  and an n+-doped contact region  150 .  
         [0067]     In  FIG. 1C , the charge trapping structure has a charge storage state with relatively more net positive charge than in  FIG. 1D . In the bias arrangement of  FIG. 1C  for reading the charge trapping structure  130 , the voltage of the gate  110  is 5 V, the voltage of the contact region  150  is −3 V, and the voltage of the body region  170  is 0 V. The memory cell of  FIG. 1D  is similar to memory cell of  FIG. 1C , except that a read operation is being performed on a charge trapping structure with higher net negative charge in the charge trapping structure  130 . In the bias arrangement of  FIG. 1D  for reading the charge trapping structure  130 , the voltage of the gate  110  is 5 V, the voltage of the contact region  150  is −3 V, and the voltage of the body region  170  is 0 V. In  FIGS. 1C and 1D , the bias arrangement is determined among the various terminals, such that the energy bands bend sufficiently to cause band-to-band current in the p+-doped contact region  150 .  
         [0068]     The bottom dielectric structure  140  (bottom oxide) and the portion of the body region  170  by the bottom dielectric structure  140  is biased more positively in  FIG. 1C  than  FIG. 1D . Thus, deeper band bending occurs between the contact region  150  and the body region  170  in  FIG. 1C  than  FIG. 1D , and more band band-to-band current flows between the contact region  150  and the body region  170  in the bias arrangement shown in  FIG. 1C  for reading the charge trapping structure  130 , than flows between the contact region  150  and the body region  170  in the bias arrangement shown in  FIG. 1D  for reading the charge trapping structure  130 .  
         [0069]     The difference in the bias arrangements of  FIGS. 1A and 1B  for reading, and the bias arrangements of  FIGS. 2A, 2D ,  3 A, and  3 D for programming, show a careful balance. For reading, the potential difference between the contact region and the body region should not cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state of the charge storage structure. In contrast, for programming, the potential difference between the contact region and the body region is sufficient to cause a substantial number of carriers to transit the tunnel oxide and affect the charge storage state of the charge storage structure.  
         [0070]      FIGS. 2A-2F  and are simplified diagrams of a memory cell that show program and erase operations being performed on the memory cell, primarily with holes.  
         [0071]     In  FIG. 2A , programming is accomplished using band-to-band tunneling induced hot hole injection, and in  FIGS. 2B and 2C , erasing is accomplished using the E-field induced hole tunneling (also known as Fowler-Nordheim tunneling) which causes tunneling current between the gate and the charge trapping structure, and between the body region and the charge trapping structure. The memory cell of  FIGS. 2A-2C  has an n-type contact region and a p-type body region.  
         [0072]     Thus, as illustrated in  FIG. 2A , the charge trapping structure  230  is programmed by applying −5 V to the gate  210 , 5 V to the contact region  250 , and 0 V to the body region  270 . This induces hot holes having sufficient energy to jump over the tunnel dielectric  240  into the charge trapping structure  230 .  FIG. 2B  illustrates E-field assisted hole tunneling in the general direction from the gate  210  to the body region  270  and the contact region  250 , induced by a relatively high positive bias on the gate  210  of 10 V and a relatively high negative bias of −10 V on the contact region  250  and body region  270 .  FIG. 2C  illustrates E-field assisted hole tunneling in the general direction to the gate  210  from the body region  270  and the contact region  250 , induced by a relatively high negative bias on the gate  210  of −10 V and a relatively high positive bias of 10 V on the contact region  250  and body region  270 .  
         [0073]     The memory cell of  FIGS. 2D-2F  has a p-type contact region  250  and an n-type body region  270 . In  FIG. 2D  a programming operation increases net positive charge in the charge trapping structure with holes from a p-type substrate or well  280 . This programming operation injects minority carrier holes across the n-type body region  270  by applying 6 V to the substrate or well  280 , 5 V to the body region  270 , −5 V to the contact region  250 , and −10 V to the gate  210 .  FIG. 2D  illustrates E-field assisted hole tunneling in the general direction from the gate  210  to the body region  270  and the contact region  250 , induced by a relatively high positive bias on the gate  210  of 10 V and a relatively high negative bias of −10 V on the contact region  250  and body region  270 .  FIG. 2F  illustrates E-field assisted hole tunneling in the general direction to the gate  210  from the body region  270  and the contact region  250 , induced by a relatively high negative bias on the gate  210  of −10 V and a relatively high positive bias of 10 V on the contact region  250  and body region  270 . In  FIGS. 2A-2F , the voltage of the contact region can also be floating.  
         [0074]     Other program and erase techniques can be used in operation algorithms applied to the PHINES type memory cell, as described for example in U.S. Pat. No. 6,690,601. Other memory cells and other operation algorithms might also be used.  
         [0075]      FIGS. 3A-3F  and are simplified diagrams of a memory cell that show program and erase operations being performed on the memory cell, primarily with electrons. In  FIG. 3A , programming is accomplished using band-to-band tunneling induced hot electron injection, and in  FIGS. 3B and 3C , erasing is accomplished using the E-field induced electron tunneling (also known as Fowler-Nordheim tunneling) which causes tunneling current between the gate and the charge trapping structure, and between the body region and the charge trapping structure. The memory cell of  FIGS. 3A-3C  has a p-type contact region and an n-type body region.  
         [0076]     Thus, as illustrated in  FIG. 3A , the charge trapping structure  330  is programmed by applying 5 V to the gate  310 , −5 V to the contact region  350 , and 0 V to the body region  370 . This induces hot electrons having sufficient energy to jump over the tunnel dielectric  340  into the charge trapping structure  330 .  FIG. 3B  illustrates E-field assisted electron tunneling in the general direction from the gate  310  to the body region  370  and the contact region  350 , induced by a relatively high negative bias on the gate  310  of −10 V and a relatively high positive bias of 10 V on the contact region  350  and body region  370 .  FIG. 3C  illustrates E-field assisted electron tunneling in the general direction to the gate  310  from the body region  370  and the contact region  350 , induced by a relatively high positive bias on the gate  310  of 10 V and a relatively high negative bias of −10 V on the contact region  350  and body region  370 .  
         [0077]     The memory cell of  FIGS. 3D-3F  has an n-type contact region  350  and a p-type body region  370 . In  FIG. 3D  a programming operation increases net negative charge in the charge trapping structure with electrons from an n-type substrate or well  380 . This programming operation injects minority carrier electrons across the p-type body region  370  by applying −6 V to the substrate or well  380 , −5 V to the body region  370 , 5 V to the contact region  350 , and 10 V to the gate  310 .  FIG. 3D  illustrates E-field assisted electron tunneling in the general direction from the gate  310  to the body region  370  and the contact region  350 , induced by a relatively high negative bias on the gate  310  of −10 V and a relatively high positive bias of 10 V on the contact region  350  and body region  370 .  FIG. 3F  illustrates E-field assisted electron tunneling in the general direction to the gate  310  from the body region  370  and the contact region  350 , induced by a relatively high positive bias on the gate  310  of 10 V and a relatively high negative bias of −10 V on the contact region  350  and body region  370 . In  FIGS. 3A-3F , the voltage of the contact region can also be floating.  
         [0078]      FIGS. 4A, 4B , and  4 C are graphs that show program and erase operations being performed on the memory cell, with data points taken by band-to-band read operations.  
         [0079]     In the graph of  FIG. 4A , memory cells each having a charge trapping part in a programmed state are erased via E-field assisted electron tunneling, induced by relatively high negative bias on the gate, and relatively high positive bias on the body region. The charge trapping part of both memory cells are simultaneously erased in the graph by applying −19.5 V to the gate, and grounding the body region, while the contact region is floating. For each data point, the read operation is performed by applying −10 V to the gate, 2 V to the contact region, and grounding the body region.  
         [0080]     In the graph of  FIG. 4B , the first charge trapping memory cell undergoes programming, and in the graph of  FIG. 4C , the second charge trapping memory cell undergoes programming. Curve  410  represents the read current of the first charge trapping memory cell. Curve  420  represents the read current of the second charge trapping memory cell. In  FIG. 4B , the first charge trapping memory cell is programmed by applying −8V to the gate and 5 V to the contact region, and grounding the body region. In  FIG. 4B , as the charge trapping structure is undergoing programming, the read current curve of the charge trapping structure  410  drops from a highest level of about 100 nA to a lowest level of about 1 nA. The programming of the first charge trapping memory cell does not substantially affect the read current curve of the neighboring second charge trapping memory cell  420 . In  FIG. 4C , the second charge trapping memory cell is programmed by applying −8V to the gate and 5 V to the contact region, and grounding the body region. In  FIG. 4C , as the second charge trapping memory cell is undergoing programming, the read current curve of the second charge trapping memory cell  420  drops from a highest level of about 100 nA to a lowest level of about 1 nA. The programming of the second charge trapping memory cell does not substantially affect the read current curve of the first charge trapping memory cell  410 . For each data point in  FIGS. 4B and 4C , the read operation is performed by applying −10 V to the gate, 2 V to the contact region, and grounding the body region.  
         [0081]     The sensing window shown in  FIGS. 4B and 4C  is relatively wide, because there is no reverse read which couples the measurement of the charge storage state of the charge trapping structure of interest with the charge storage state of another charge trapping structure, even if the two charge trapping structures belong to adjacent charge trapping memory cells. The read current resulting from a band-to-band read operation performed on a first charge trapping memory cell is relatively insensitive to the logical state of an adjacent second charge trapping memory cell, and the read current resulting from a band-to-band read operation performed on the second charge trapping memory cell is relatively insensitive to the logical state of the adjacent first charge trapping memory cell. Each charge trapping structure can store one bit or multiple bits. For example, if each charge trapping structure stores two bits, then there are four discrete levels of charge.  
         [0082]      FIGS. 5A and 5B  are simplified diagrams of charge trapping memory cells having an isolation region between adjacent charge trapping memory cells. In  FIG. 5A , each memory cell has a p+-doped contact region  527 , a bottom oxide  525 , a charge trapping structure  523 , a top oxide  521 , and an isolation region  530 . The memory cells are formed in an n-type substrate. A word line  510  provides a gate voltage to memory cells in a common row, and the bit line provides the contact region voltage to the p+-doped contact region  527  to memory cells in a common column. The memory cells in  FIG. 5B  are similar, but are formed in a p-type substrate  540  and have an n+-doped contact region  527 .  
         [0083]      FIGS. 6A and 6B  are simplified diagrams of charge trapping memory cells. In contrast with the memory cells of  FIGS. 5A and 5B , in  FIGS. 6A and 6B  the memory cells are formed without an isolation region between adjacent charge trapping memory cells. In  FIG. 6A , each memory cell has a p+-doped contact region  627 , a bottom oxide  625 , a charge trapping structure  623 , and a top oxide  621 . The memory cells are formed in an n-type substrate. A word line  610  provides a gate voltage to memory cells in a common row, and the bit line provides the contact region voltage to the p+-doped contact region  627  to memory cells in a common column. The memory cells in  FIG. 6B  are similar, but are formed in a p-type substrate  640  and have an n+-doped contact region  627 .  
         [0084]      FIGS. 7A and 7B  are simplified diagrams of charge trapping memory cells. In contrast with the memory cells of  FIGS. 5A and 5B , in  FIGS. 7A and 7B  the memory cells are formed with an ONO stack running continuously through the string of charge trapping memory cells. In  FIG. 7A , each memory cell has a p+-doped contact region  727 , a bottom oxide  725 , a charge trapping structure  723 , a top oxide  721 , and an isolation region  730 . The memory cells are formed in an n-type substrate. A word line  710  provides a gate voltage to memory cells in a common row, and the bit line provides the contact region voltage to the p+-doped contact region  727  to memory cells in a common column. The memory cells in  FIG. 7B  are similar, but are formed in a p-type substrate  740  and have an n+-doped contact region  727 .  
         [0085]      FIGS. 8A and 8B  are simplified diagrams of a string of charge trapping memory cells with a p-type contact region.  FIG. 8A  shows the string of charge trapping memory cells from the X-direction without an isolation region between adjacent charge trapping memory cells. Each memory cell has a p+-doped contact region  827 , a bottom oxide  825 , a charge trapping structure  823 , and a top oxide  821 . The memory cells are formed in an n-type substrate  840 . A word line  810  provides a gate voltage to memory cells in a common row (i.e., a common word line), and the bit line provides the contact region voltage to the p+-doped contact region  827  of memory cells in a common column (i.e., a common bit line).  FIG. 8B  shows the string of charge trapping memory cells from the Y-direction with an isolation region between adjacent charge trapping memory cells. Each memory cell has a bottom oxide  825 , a charge trapping structure  823 , a top oxide  821 , and an isolation region  830 . The memory cells are formed in an n-type substrate  840 . A word line  810  provides a gate voltage to memory cells in a common row (i.e., a common word line).  
         [0086]      FIGS. 9A and 9B  are simplified diagrams of a string of charge trapping memory cells with an n-type contact region.  FIG. 9A  shows the string of charge trapping memory cells from the X-direction without an isolation region between adjacent charge trapping memory cells. Each memory cell has an n+-doped contact region  927 , a bottom oxide  925 , a charge trapping structure  923 , and a top oxide  921 . The memory cells are formed in a p-type substrate  940 . A word line  910  provides a gate voltage to memory cells in a common row (i.e., a common word line), and the bit line provides the contact region voltage to the n+-doped contact region  927  of memory cells in a common column (i.e., a common bit line).  FIG. 9B  shows the string of charge trapping memory cells from the Y-direction with an isolation region between adjacent charge trapping memory cells. Each memory cell has a bottom oxide  925 , a charge trapping structure  923 , a top oxide  921 , and an isolation region  930 . The memory cells are formed in a p-type substrate  940 . A word line  910  provides a gate voltage to memory cells in a common row (i.e., a common word line).  
         [0087]      FIG. 10  is a simplified diagram of strings of charge trapping memory cells, showing an erase operation being performed on the strings of charge trapping memory cells. The voltage of the body region  1002  is 10 V. The word lines of the memory cells to be erased  1010 ,  1020 ,  1030 , and  1040  have a voltage of −10 V. The bit lines  1003 ,  1004 , and  1005  which provide the contact region voltages are floating. The memory cells of the array are erased, for example via FN tunneling of electrons from the gate to the charge trapping structure and from the charge trapping structure to the body region.  
         [0088]      FIG. 11  is a simplified diagram of strings of charge trapping memory cells, showing an erase operation being performed on the strings of charge trapping memory cells. The voltage of the body region  1102  is −10 V. The word lines of the memory cells to be erased  1110 ,  1120 ,  1130 , and  1140  have a voltage of 10 V. The bit lines  1103 ,  1104 , and  1105  which provide the contact region voltages are floating. The memory cells of the array are erased, for example via FN tunneling of electrons from the gate to the charge trapping structure and from the charge trapping structure to the body region.  
         [0089]      FIG. 12  is a simplified diagram of strings of charge trapping memory cells, showing a programming operation being performed on selected memory cells of the strings of charge trapping memory cells. The body region  1202  is grounded. The bit lines  1203  and  1205  which provide the contact region voltages of the memory cells to be programmed has a voltage of 5 V. The bit line  1204  not corresponding to the contact region of any memory cells to be programmed is grounded. The word line  1230  of the memory cells to be programmed has a voltage of −5 V. The word lines  1210  and  1220  between the bit lines  1203 ,  1204 , and  1205 , and the word line  1230  of the memory cells to be programmed have a voltage of 10 V. The word line  1240  on the other side of the word line  1230  of the memory cells to be programmed has a voltage of −5 V, or can be grounded. The 10 V on the word lines  1210  and  1220  cause an inversion in the body regions of the memory cells of word lines  1210  and  1220 , and the inversions electrically couple the voltages of bit lines  1203 ,  1204 , and  1205  to the contact regions of the memory cells of word line  1230 . The charge trapping structures  1233  and  1235  belong to the only memory cells at the intersection of: bit lines  1203  and  1205  and word line  1230  with voltages sufficiently high to cause the injection of charge across the bottom oxide of memory cells into the charge trapping structure. Thus, only the charge trapping structures  1233  and  1235  are programmed.  
         [0090]      FIG. 13  is a simplified diagram of strings of charge trapping memory cells, showing a read operation being performed on selected memory cells of the strings of charge trapping memory cells. The body region  1302  has a voltage of −10 V. The bit lines  1303 ,  1304 , and  1305  which provide the contact region voltages of the memory cells to be read have a voltage of 3 V. Alternatively, any bit lines not corresponding to the contact region of any memory cells to be read can be grounded. The word line  1330  of the memory cells to be read has a voltage of −5 V. The word lines  1310  and  1320  between the bit lines  1303 ,  1304 , and  1305 , and the word line  1330  of the memory cells to be read have a voltage of 10 V. The word line  1340  on the other side of the word line  1330  of the memory cells to be programmed has a voltage of −5 V, or can be grounded. The 10 V on the word lines  1310  and  1320  cause an inversion in the body regions of the memory cells of word lines  1310  and  1320 , and the inversions electrically couple the voltages of bit lines  1303 ,  1304 , and  1305  to the contact regions of the memory cells of word line  1330 . The charge trapping structures  1333 ,  1334 , and  1335  belong to the only memory cells at the intersection of: bit lines  1303 ,  1304 , and  1305  and word line  1330  with voltages sufficiently high to cause band-to-band current to flow between the contact regions and the body regions of the memory cells. Thus, only the charge trapping structures  1333 ,  1334 , and  1335  are read.  
         [0091]      FIG. 14  is a simplified diagram of an array of charge trapping memory cells, showing an erase operation being performed on the array of charge trapping memory cells. The body region  1402  has a voltage of 10 V. The bit lines  1403 ,  1404 , and  1405  which provide the contact region voltages of the memory cells to be read have a voltage of 10 V. The word lines  1410 ,  1420 ,  1430 , and  1440  of the memory cells to be erased have a voltage of −10 V. The memory cells of the array are erased, for example via FN tunneling of electrons to the body region from the charge trapping structure and to the charge trapping structure from the gate.  
         [0092]      FIG. 15  is a simplified diagram of an array of charge trapping memory cells, showing an erase operation being performed on the array of charge trapping memory cells. Unlike the erase operation in  FIG. 14 , in  FIG. 15 a  positive voltage is applied to the gates relative to the body regions. The body region  1502  has a voltage of −10 V. The bit lines  1503 ,  1504 , and  1505  which provide the contact region voltages of the memory cells to be read have a voltage of −10 V. The word lines  1510 ,  1520 ,  1530 , and  1540  of the memory cells to be erased have a voltage of 10 V. The memory cells of the array are erased, for example via FN tunneling of electrons from the body region to the charge trapping structure and from the charge trapping structure to the gate.  
         [0093]      FIG. 16  is a simplified diagram of an array of charge trapping memory cells, showing a programming operation being performed on selected memory cells of the array of charge trapping memory cells. The body region  1602  is grounded. The bit lines  1603  and  1605  which provide the contact region voltages of the memory cells to be programmed has a voltage of 5 V. The bit line  1604  not corresponding to the contact region of any memory cells to be programmed is grounded. The word line  1620  of the memory cells to be programmed has a voltage of −5 V. The word lines  1610 ,  1630 , and  1640  not corresponding to any memory cells to be programmed are grounded. The charge trapping structures  1623  and  1625  belong to the only memory cells at the intersection of: bit lines  1603  and  1605  and word line  1620  with voltages sufficiently high to cause the injection of charge across the bottom oxide of memory cells into the charge trapping structure. Thus, only the charge trapping structures  1623  and  1625  are programmed.  
         [0094]      FIG. 17  is a simplified diagram of an array of charge trapping memory cells, showing a read operation being performed on the array of charge trapping memory cells. The body region  1702  is grounded. The bit lines  1703 ,  1704 , and  1705  which provide the contact region voltages of the memory cells to be read have a voltage of 3 V. Alternatively, any bit lines not corresponding to the contact region of any memory cells to be read can be grounded. The word line  1720  of the memory cells to be programmed has a voltage of −5 V. The word lines  1710 ,  1730 , and  1740  not corresponding to any memory cells to be read are grounded. The charge trapping structures  1723 ,  1724 , and  1725  belong to the only memory cells at the intersection of: bit lines  1703 ,  1704 , and  1705  and word line  1720  with voltages sufficiently high to cause band-to-band current to flow between the contact regions and the body regions of the memory cells. Thus, only the charge trapping structures  1723 ,  1724 , and  1725  are read.  
         [0095]      FIG. 18  is a simplified block diagram of an integrated circuit according to an embodiment. The integrated circuit  1850  includes a memory array  1800  implemented using charge trapping memory cells, on a semiconductor substrate. A row decoder  1801  is coupled to a plurality of word lines  1802  arranged along rows in the memory array  1800 . A column decoder  1803  is coupled to a plurality of bit lines  1804  arranged along columns in the memory array  1800 . Addresses are supplied on bus  1805  to column decoder  1803  and row decoder  1801 . Sense amplifiers and data-in structures in block  1806  are coupled to the column decoder  1803  via data bus  1807 . Data is supplied via the data-in line  1811  from input/output ports on the integrated circuit  1850 , or from other data sources internal or external to the integrated circuit  1850 , to the data-in structures in block  1806 . Data is supplied via the data-out line  1815  from the sense amplifiers in block  1806  to input/output ports on the integrated circuit  1850 , or to other data destinations internal or external to the integrated circuit  1850 . A bias arrangement state machine  1809  controls the application of bias arrangement supply voltages  1808 , such as for the erase verify and program verify voltages, and the arrangements for programming, erasing, and reading the memory cells, such as with the band-to-band currents.  
         [0096]     While the present invention is disclosed by reference to the technology and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.