Abstract:
A cascoded current mirror device is disclosed that is capable of producing an output current that is a direct function of an input current received by that device. The cascoded current mirror includes at least two portions connected together in a cascode manner. Provision is also made for feedback connection between those portions. This feedback connection can, for example, be a buffering connection. Voltage signals are generated by this device that can be used to drive and control additional output stages. Each such additional output stage is capable of producing an additional output current.

Description:
FIELD OF THE INVENTION 
     The present invention relates to devices for producing or processing currents, and more particularly to the variety of such devices commonly referred to as current mirrors. 
     BACKGROUND OF THE INVENTION 
     In the field of transistorized current sources, it has been a general practice to employ current mirrors as current sources. Current mirrors have also been used to mirror a varying input signal current. Although such devices have served the purpose, they have not proven entirely satisfactory under all conditions of service because each type of current mirror has a limited operating range for permissible input currents, unless differently sized devices are used for each different application. This problem is overcome by the present invention. 
     A current mirror receives an input current into one node, typically into a low impedance, and produces an output current at another node. That output current is a direct function (such as a reproduction or linear scaling) of the input current. In some cases, multiple (equal or unequal) currents may be produced for distribution to different output nodes. Increased output resistance and increased effective open circuit voltage can be obtained by a cascode multiple current mirror configuration. An alternative configuration is the Wilson current source, which utilizes negative feedback in lieu of a cascode configuration. Such a configuration has been found to have improved output compliance, which is the voltage range at the output node over which the current source continues to function as a proper current source. However, with the Wilson current mirror, the accuracy with which the output current mirrors the input current is reduced. The cascoded current mirror has better such accuracy, but reduced compliance. Such devices are described in Gray, P. R. and Meyer, R. G. Analysis and Design of Analog Integrated Circuits, Second Edition (John Wiley &amp; Sons, New York 1984) pp. 233-246, 518-519 and 709-718, which is hereby incorporated by reference. Also see Allen, P. E. and Holberg, D. R. CMOS Analog Circuit Design, (Holt, Rinehart and Winston, Inc., New York, 1987) pp. 219-321 (especially pp. 219-239), which is also hereby incorporated by reference. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is the general purpose of the present invention to provide apparatus capable of producing an output current that is a direct function of an input current received by that apparatus. 
     Other objects of the present invention are to provide apparatus for producing an output current that is a direction function of a received input current and which can do so over a wide range of input currents. 
     Briefly, these and other objects of the present invention are accomplished by a cascoded current mirror wherein provision is made for connection, such as a buffering connection, between the cascoded portions to provide feedback between such portions of the apparatus. 
     The term &#34;terminal&#34; as used herein is generically, is not limited to a lug or screw, and for example includes but is used not limited to an electrode such as defined in McGraw-Hill Dictionary, intra. For example, but without limitation, Parker, S. P., ed. McGraw-Hill Dictionary of Scientific and Technical Terms 3rd ed. (McGraw-Hill, New York, 1984) at page 1623 has a definition of &#34;terminal&#34; as &#34;One of the electric input or output points of a circuit or component.&#34; When referring to a transistor, such a terminal can for example (but without limitation) be an emitter region. 
     One such device comprises apparatus for producing an output current that is a direct function of an input current received by that apparatus, the apparatus comprising a first active semiconductor device including at least first, second and third terminals; a second active semiconductor device including at least first, second and third terminals wherein the first terminal of the first device is operably connected to the first terminal of the second device and wherein the third terminal of the first device is operably connected to the third terminal of the second device; a third active semiconductor device including at least first, second and third terminals wherein the first terminal of the third device is operably connected to the second terminal of the first device; a fourth active semiconductor device including at least first, second and third terminals wherein the first terminal of the fourth device is operably connected to the second terminal of the second device, wherein the third terminal of the fourth device is operably connected to the third terminal of the third device; a fifth active semiconductor device including at least first, second and third terminals wherein the first terminal of the fifth device is operably connected to the third terminal of each of the first and second devices and wherein the third terminal of the fifth device is operably connected to the second terminal of the third device; a sixth active semiconductor device including at least first, second and third terminals wherein the first terminal of the sixth device is operably connected to the first terminal of the first device and the first terminal of the second device, and wherein the second and third terminals of the sixth device are operably connected to the third terminal of the first device, to the third terminal of the second device and to the first terminal of the fifth device; and a seventh active semiconductor device including at least first, second and third terminals wherein the first terminal of the seventh device is operably connected to the first terminal of each of the first, second and sixth devices, and wherein the second and third terminals of the seventh device are operably connected to the third terminal of each of the third and fourth devices; whereby an input current applied to the second terminal of the third device into the third terminal of the fifth device will result in production at the second terminal of the fourth device of an output current that is a direct function of that input current. Each of the first, second, third, fourth, fifth, sixth and seventh active semiconductor devices can for example each comprise a transistor. Each of the first, second, third, fourth, fifth, sixth and seventh active semiconductor devices can for example each comprise a field effect transistor wherein the first terminal of each of the active semiconductor devices comprises a source terminal of that device, the second terminal of each of the active semiconductor devices comprises a drain terminal of that device, and the third terminal of each of the active semiconductor devices comprises a gate terminal of that device. Each of the active semi-conductor devices can for example comprise a bipolar transistor wherein the first terminal of each of the active semiconductor devices comprises an emitter terminal of that device, the second terminal of each of the active semiconductor devices comprises a collector terminal of that device, and the third terminal of each of the active semiconductor devices comprises a base terminal of that device. 
     As another example, apparatus is provided for producing an output current that is a direct function of an input current received by that apparatus, the apparatus comprising a first active semiconductor device including at least first, second and third terminals; a second active semiconductor device including at least first, second and third terminals wherein the first terminal of the first device is operably connected to the first terminal of the second device and wherein the third terminal of the first device is operably connected to the third terminal of the second device; a third active semiconductor device including at least first, second and third terminals wherein the first terminal of the third device is operably connected to the second terminal of the first device; a fourth active semiconductor device including at least first, second and third terminals wherein the first terminal of the fourth device is operably connected to the second terminal of the second device, and wherein the third terminal of the fourth device is operably connected to the third terminal of the third device; a fifth active semiconductor device including at least at least first, second and third terminals wherein the first terminal of the fifth device is operably connected to the third terminal of each of the first and second devices and wherein the third terminal of the fifth device is operably connected to the second terminal of the third device; a first impedance device including at least first and second terminals wherein the first terminal of the first impedance device is operably connected to the first terminal of the first active semiconductor device and to the first terminal of the second active semiconductor device, and wherein the second terminal of the first impedance device is operably connected to the third terminal of the first active semiconductor device, to the third terminal of the second active semiconductor device and to the first terminal of the fifth active semiconductor device; and a second impedance device including at least first and second terminals wherein the first terminal of the second impedance device is operably connected to the first terminal of each of the first and second active semiconductor devices and the first impedance device, and wherein the second terminal of the second impedance device is operably connected to the third terminal of each of the third and fourth active semiconductor devices; whereby an input current applied to the second terminal of the third device and to the third terminal of the fifth device results in production at the second terminal of the fourth device of an output current that is a direct function of that input current. The first, second, third, fourth and fifth active semiconductor devices can for example each comprise a transistor. Each of the first, second, third, fourth and fifth active semiconductor devices can for example each comprise a field effect transistor, wherein the first terminal of each such field effect transistor comprises a source terminal of that FET, the second terminal of each such FET comprises a drain terminal of that FET and the third terminal of each such FET comprises a gate terminal of that FET. Each of the active semiconductor devices can for example comprise a bipolar transistor, wherein the first terminal of each such bipolar transistor comprises an emitter terminal of that bipolar transistor, the second terminal of each such bipolar transistor comprises a collector terminal that bipolar transistor, and the third terminal of each such bipolar transistor comprises a base terminal of that bipolar transistor. 
     As another example, apparatus is provided for producing an output current that is a direct function of an input current received by that apparatus, the apparatus comprising a first active semiconductor device including at least first, second and third terminals; a second active semiconductor device including at least first, second and third terminals wherein the first terminal of the first device is operably connected to the first terminal of the second device and wherein the third terminal of the first device is operably connected to the third terminal of the second device; a third active semiconductor device including at least first, second and third terminals wherein the first terminal of the third device is operably connected to the second terminal of the first device, and wherein the second terminal of the third device is operably connected to the third terminal of the first device and to the third terminal of the second device; a fourth active semiconductor device including at least first, second and third terminals wherein the first terminal of the fourth device is operably connected to the second terminal of the second device, wherein the third terminal of the fourth device is operably connected to the third terminal of the third device; a fifth active semiconductor device including at least first, second and third terminals wherein the first terminal of the fifth device is operably connected to the first terminal of each of the first and second devices, and wherein the second and third terminals of the fifth device are operably connected to the third terminal of each of the third and fourth devices; whereby an input current applied to the second terminal of the third device will result in production at the second terminal of the fourth device of an output current that is a direct function of that input current. 
     As another example, apparatus is provided for producing an output current that is a direct function of an input current received by that apparatus, the apparatus comprising a first active semiconductor device including at least first, second and third terminals; a second active semiconductor device including at least first, second and third terminals wherein the first terminal of the first device is operably connected to the first terminal of the second device and wherein the third terminal of the first device is operably connected to the third terminal of the second device; a third active semiconductor device including at least first, second and third terminals wherein the first terminal of the third device is operably connected to the second terminal of the first devices and wherein the second terminal of the third device is operably connected to the third terminal of the first device and to the third terminal of the second device; a fourth active semiconductor device including at least first, second and third terminals wherein the first terminal of the fourth device is operably connected to the second terminal of the second device, wherein the third terminal of the fourth device is operably connected to the third terminal of the third device; a first impedance device including at least first and second terminals wherein the first terminal of the first impedance device is operably connected to the first terminal of each of the first and second active semiconductor devices, and wherein the second and third terminals of the first impedance device are operably connected to the third terminal of each of the third and fourth active semiconductor devices; whereby an input current applied to the second terminal of the third active semiconductor device will result in production at the second terminal of the fourth active semiconductor device of an output current that is a direct function of that input current. 
     Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     In the drawing, 
     FIG. 1 is a schematic diagram of one embodiment of a current mirror according to the present invention; 
     FIG. 2 is a schematic diagram of another embodiment of another current mirror according to the present invention; 
     FIG. 3 is a schematic diagram of still another embodiment of still another current mirror according to the present invention; 
     FIG. 4 is a schematic diagram of yet another embodiment of yet another current mirror according to the present invention; 
     FIG. 5 is a schematic diagram of a further embodiment of a further current mirror according to the present invention; and 
     FIG. 6 is a schematic diagram of a still further embodiment of a still further current mirror according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     Referring now to the drawing, wherein like reference characters designate like or corresponding parts throughout the several views, there is shown in FIG. 1 a current mirror 11 including P-channel metal oxide-semiconductor (MOS) field effect transistors (FETs) 13, 15, 17, 19, 21, 23 and 27. For FETs 19 and 21, the respective gate and drain are connected to each other, to help ensure that these transistors remain in saturation. The input current I IN  controls through FET 17 the node 27 from which the V  Gate  A signal is produced. FET 17 is here connected to act as a source follower. As shown in FIGS. 5 and 6, the V Gate  A signal and the V Gate  B signal are generated by the present invention to drive and control additional output stages. FET 19 is used to bias source follower FET 17. As a result, FET 23 is held in the saturated region of operation, which is desirable for proper performance, and the impedance at the node 27 V  Gate  A output is set by the transconductance of FETs 17 and 19. However, inclusion of FET 17 necessitates additional current to bias FET 17. In this case, AC capacitive compensation may be added to the node to which the input current I IN  is applied to ensure stable operation. 
     In the embodiment of FIG. 1, input current I IN  controls output current I  OUT . The gate-to-source voltage V  GS  15 applied to FET 15 controls the output current produced by FET 15 and also determines the output current produced by FET 13. The current produced by FET 13 in turn controls FET 23 at the node to which input current I IN  is applied. Source follower FET 17 acts as a voltage buffer, and is connected via a feedback loop to FET 19. Taken together, FET 17 and FET 19, connected in the manner shown in FIG. 1, provide what may be considered to be an ideal voltage source producing a constant voltage of about 0.7 volts. This buffer voltage is applied to node 27 (from which control voltage V  Gate  A is produced), via a negative feedback loop. This loop tends to make the drain current I D  13 produced by FET 13 to be substantially equal to the input current I IN . However, these two currents are often not equal, due in part to any parasitic capacitance at the node 27 at which FET 13 and 19 are connected. In the event of such a mismatch, net current necessarily would be flowing out of the parasitic capacitance at that node, and to ground. The voltage applied to FET 13 would continue to change until currents I IN  and I D  are equal. 
     In FIG. 1, FETs 17 and 19 together may be considered to operate like an amplifier having an infinite input impedance, that controls the node 27 and control voltage V  Gate  A produced thereat. FETs 23 and 25 are connected in a cascode configuration with FETs 13 and 15. FET 21 in effect acts as a resistor having supply voltage V +   applied thereto and providing to FETs 23 and 25 the appropriate voltage for saturation. For the device of FIG. 1 to operate properly, all transistors 13 through 25 must operate in the saturation region, necessitating sufficient drain to-source voltage V DS  across each such transistor to saturate it. The buffer provided by FETs 17 and 19 gives more leeway for drain-to-source voltage V DS  23 of FET 23 within which that transistor would remain saturated. Accordingly, the device of FIG. 1 remains properly functional over a wide variety of input current I IN  values. 
     Second input current I INA  is applied to scaled FET 21 to generate cascode control voltage V Gate  B. I INA  should be nominally the same as I IN , but need not match precisely. Although precision of input current I IN  is needed for precision of output current I OUT , such precision is not critical for input current I INA . Input current I INA  is used to set up a bias condition, so it would suffice if I INA  is roughly similar to input current I IN . 
     V -  can be a negative bias voltage, a negative supply voltage, or a ground. V -  can be a negative bias voltage, a negative supply voltage, or a ground. V -  is utilized to dispose of current from FET 17. 
     For proper operation of current source 11, all transistors 13 through 25 must be saturated. Also, for proper operation of the device of FIG. 2, and for proper operation of the device of FIG. 3, all of the transistors shown therein must be saturated. For a transistor to be saturated, its drain-to-source voltage V DS  must be sufficient. For the device to be on, its gate to source voltage V GS  must be greater than the threshold voltage V T . In addition, for saturation the drain to source voltage V DS  must be greater than V GS  -V T , for the device to have sufficient drain-to-source voltage to be saturated. Accordingly, with an increased gate-to-source voltage V GS , the drain-to-source voltage V DS  required for saturation is increased. Unless FET 23 is buffered, the drain-to-source voltage applied thereto is limited. As a result, current source 11 without such buffering would have a more limited range of input current I IN  values over which FET 23 would be saturated, resulting in a limited input current range of operation for current source 11. In other words, without buffering, FET 23 would have limited V DS  headroom. The buffer provided by FET 17 with FET 19 provides FET 23 with more headroom by increasing the drain-to-source voltage applied to FET 23. This improved headroom permits current source 11 to drive a load over a wider voltage swing, and to operate over a wider range of input current I IN  values. The voltage amplitude at the gate of FET 23 and to the gate of FET 17 can thereby be reduced. Increasing such headroom also reduces headroom used up by current mirror 11. 
     As discussed above, FET 21 can be replaced with a resistor. Also, in the buffer utilized in the present invention, FET 19 can be replaced with a resistor. Such a current source 29 is illustrated in FIG. 2. Therein, FET 19 of FIG. 1 has been replaced with a resistor 19 connected between positive supply voltage V +  and node 27 to which the V  Gate  A input is supplied. Also, FET 21 of FIG. 1 is replaced in FIG. 2 with a resistor also connected between supply voltage V +  and node 35, at which voltage V Gate  B appears. FET 17 and resistor 31 together provide buffering to FET 23. Because of such buffering, the saturation region headroom for FET 23 is increased, permitting proper operation of current source 29 over a wider range than would have been possible without the buffering provided by FET 17 and resistor 31. 
     Although buffering of FET 23 is preferred, it is not necessary to proper operation of the invention. An operable current source 37 without such buffering is illustrated by the diagrammatic representation of FIG. 3. In FIG. 3, the buffer of FET 17 with FET 19 or resistor 31 has been replaced with conductor 39 connecting nodes 27 and 35. The elimination of FET 17 also results in elimination of supply voltage V - . Again, because of the scaling of FET 21, cascode voltage V Gate  B will be at an appropriate voltage to keep FET 13 and FET 15 just in the saturated region, provided FET 23 and FET 25 are sized the same as FET 13 and FET 15 respectively. This configuration satisfies the criterion that FET 13 and FET 15 see the same drain voltage, and that the compliance in output current I OUT  be at the desirable level of twice the difference between V GS  and V T . However, in FIG. 3, the drain to source voltage of V DS  of FET 23 is the threshold voltage V T . If input current I IN  is sufficiently large, then the difference between V GS  and V T  would be greater than threshold voltage V T . In that situation, FET 23 would not be in saturation, introducing a mismatch between input current I IN  and output current I OUT . As discussed above, this could make current source 37 operable under a narrower range of input current I IN  values than would have been possible had the buffering of FIG. 1 or FIG. 2 been utilized in lieu of conductor 39. Also, it may be necessary to apply some capacitance between supply voltage V +  and node 27 to discourage ringing in the feedback loop; the specifics of this will be dependent on the specific process and current densities used. 
     An alternative configuration to that of FIG. 3 is illustrated in FIG. 4. As discussed above, FET 21 of FIG. 3 can be replaced with resistor 33. 
     In FIGS. 1 and 3, the W/L ratio between FET diffusion width and FET diffusion length for FET 21 is preferably 1/4 of the ratio for any of the other FETs utilized in the current mirror illustrated. This results in a scaled device 21 to which an extra input current I INA  (which can be the same as I IN ) is applied to generate a cascode control voltage V Gate  B. Because of this scaling of FET 21, voltage V Gate  B will be at an appropriate voltage to keep FETs 13 and 15 just in the saturated region, provided FET 23 and FET 25 are sized the same as FET 13 and FET 15 respectively. As a result, FET 13 and FET 15 will each see the same drain voltage. 
     As shown in FIGS. 5 and 6, FETs 15 and 25 can be replicated as many times as desired. Generation of voltages V Gate  A and V Gate  B as discussed above, and provision of those voltages to corresponding ones of such additional FETs, enables inclusion of such additional FETs. For example, as shown in FIG. 5, the configuration of FIG. 1 can be augmented by the addition of FET 115 and FET 125. The gate of FET 115 is connected to received voltage V Gate  A, and the gate of FET 125 is connected to receive voltage V Gate  B. Also, as shown in FIG. 6, the configuration of FIG. 3 can be augmented by inclusion of additional FETs 115 and 125. The gate of FET 115 is connected to receive voltage V Gate  A, and the gate of FET 125 is connected to receive voltage V Gate  B. Again, FET 19 and FET 21 of FIG. 5 can each be replaced with a resistor, such as is shown in FIG. 2. Also, FET 21 of FIG. 6 can be replaced with a resistor, as shown in FIG. 4. In FIG. 5 and in FIG. 6, additional FET 125 produces an output current I OUT  2. Additional pairs of FET 215, 225, 315, 325, 415, 425, etc. can be added to any of the configurations of FIGS. 1 through 6, provided that the gate of each such additional FET is connected to receive voltage or voltage V Gate  A or voltage V Gate  B, as appropriate. In each case, the second additional FET 125, 225, 325, 425, etc. would produce another output current I OUT2 , I OUT3 , I OUT4 , or I OUT5 , etc. The relationship between the input current I IN  and any output current can be determined by scaling of a corresponding pair of FETs 15 and 25, 115 and 125, 215 and 225, 315 and 325, 415 and 425, etc. As one example, if the ratio of diffusion width to diffusion length of FET 15 and FET 25 is substantially identical to the corresponding ratio of FET 13 and FET 23, then output current I OUT  produced thereby would be substantially equal to input current I IN . If, however, the ratio of diffusion width to diffusion length of FET 115 and of FET 125 is twice that of FET 13 and FET 23, then output current I OUT2  produced thereby would be substantially equal to twice input current I IN . Such scaling of FETs 115 and 125 is preferably accomplished by appropriately setting the diffusion width of those FETs. For the example just given, where output current I OUT2  is to be twice input current I IN , the diffusion width of FET 115 and the diffusion width of FET 125 should be twice the diffusion width of FET 13 and of FET 23. Other proportions and relationships between I IN  and an output current of the present invention can be set as desired by such scaling of the pair of FETs 15 and 25, 115 and 125, etc. from which that output current is produced. 
     It should be understood that, although FETs are preferred, the present invention can be used in similar fashion with similar operation with devices other than those illustrated. For example, the transistors illustrated in FIGS. 1 through 4 can be n-channel FETs, p-channel FETs, CMOS, or bipolar transistors. Although PMOS transistors are illustrated, all topologies shown in the drawings are equally valid for NMOS transistors. Additionally, the illustrated topologies are useful for a wide range of possible device geometries, e.g., lengths and widths of diffusion regions. 
     Some of the many advantages of the invention should now be readily apparent. For example, a novel current mirror has been provided which is capable of producing an output current that is a direct function of an input current received by that apparatus. Higher accuracy mirror functions are provided over wider ranges of input currents through the provision of additional headroom for saturation operation. A precision current mirror has been provided featuring high output impedance, accurate mirroring at arbitrary scaling factors, and improved voltage compliance at the output current nodes. The present invention is capable of producing an output current that is a direct function of a received input current, and is capable of doing so over a substantially wide range of input currents. 
     Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, the invention may be practiced otherwise than as specifically described.