Abstract:
A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This continuation application claims the benefit of application Ser. No. 11/161,525 filed on Aug. 8, 2005 and incorporated herein in its entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a method and related apparatus for reducing power consumption, and more particularly, to a method and related apparatus for reducing chipset power consumption while accessing memory modules. 
         [0004]    2. Description of the Prior Art 
         [0005]    Computer systems are indispensable to the information society. With the computer system, it is convenient for users to calculate, access, and manage a large amount of information, data, and video at high speed. Therefore, information technology manufacturers have been devoted to improving the performance of computer systems to manage data more securely and speedily. However, while the performance of computer systems is improved, how to reduce power consumption becomes an important issue. 
         [0006]    Generally, a typical computer system comprises a central processing unit (CPU), a chipset, a memory device, and other peripheral circuits. The CPU can process information and data to control the operation of the computer system. The memory device, such as a dynamic random-access memory (DRAM), can temporarily store programs, and data required by the CPU. The chipset can manage the communication between the CPU (or other peripheral circuits) and the memory device. 
         [0007]    Data is stored in the memory device and has a corresponding address that allows random access. In the computer system, the memory device includes several memory modules. Each memory module has a plurality of address pins, each address pin being used for receiving a one-bit address. The chipset includes a plurality of driving units respectively connected to the address pins of each memory module, each driving receiving power and outputting a one-bit address to a corresponding address pin. When the chipset accesses data of a certain address in the memory device, the chipset will control the driving units respectively to output a one-bit address to the corresponding address pins. Then the memory module gathers all one-bit addresses to obtain a complete address, such as a row address (RAS) or a column address (CAS). According to the assigned address, the chipset can access the required data. 
         [0008]    In the prior art, memory modules are independent circuits and combined into a memory device, which is electrically connected to the computer system by insertion into a slot. Depending on the user&#39;s budget and requirement, the user can install the required memory capacity. As known in the art, a larger memory capacity requires more bits to assign addresses. Generally, driving units of the chipset are more than address pins of the memory device so as to support different memory capacities or larger memory capacities. For instance, most chipsets can support a 4 GB memory capacity. However, most memory device configurations have a memory capacity smaller than 4 GB and thereby require fewer address bits. 
         [0009]    Current chipsets can support the configuration for 2-bit bank addresses and 14-bit RAS/CAS addresses, and therefore the typical chipset includes 16 driving units. Actually, it is only necessary to have 2-bit bank addresses and 12-bit RAS/CAS addresses to assign an address in a 64 MB memory module. However, in the prior art, no matter whether the configuration of the memory module is smaller than the memory capacity supported by the chipset, each driving unit of the chipset still consumes power. Thus, when the prior art computer system accesses the memory device, some address pins of the memory module are not used, but the corresponding driving units still consume power increasing overall power consumption. 
       SUMMARY OF THE INVENTION 
       [0010]    It is therefore a primary objective of the claimed invention to provide a method for reducing chipset power consumption while accessing a memory module to solve the above-mentioned problem. 
         [0011]    The claimed invention provides a method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0013]      FIG. 1  is a diagram of a computer system according to the present invention. 
           [0014]      FIG. 2  is a flowchart of the operation of the chipset of  FIG. 1 . 
           [0015]      FIG. 3  is a diagram of another embodiment of a computer system based on the present invention. 
           [0016]      FIG. 4  is a flowchart of the operation of the chipset of  FIG. 3 . 
           [0017]      FIG. 5  is a diagram of the operation of each driving unit when the computer system of  FIG. 3  is working. 
       
    
    
     DETAILED DESCRIPTION  
       [0018]    Please refer to  FIG. 1 , which is a diagram of a computer system  10  according to the present invention. The computer system comprises a central processing unit (CPU)  12 , a peripheral circuit  14 , a basic input/output system (BIOS)  16 , a chipset  20 , and a memory module  30 . The CPU  12  processes information and data to control the operation of the computer system  10 . The memory module  30  temporarily stores programs and data required by the CPU  12 . The peripheral circuit  14  can be a hard disc, an optical disc drive or inserted cards, such as a graphic card, a network interface card, a sound card, etc. When booting the computer system, the BIOS  16  not only stores settings and program codes for the basic inspection, but also detects the configuration of the memory module  30  to generate corresponding configuration information. The chipset  20  manages the communications among the CPU  12 , the memory module  30 , the peripheral circuit  14 , and the BIOS  16 . 
         [0019]    In order to implement the present invention, the chipset  20  includes an access circuit  21 , an address module  22 , a plurality of driving units  23  (this embodiment has 16 driving units  23 ), a control module  24 , and a buffer module  26 . The access circuit  21  receives the request from the CPU  12  (or the peripheral circuit  14 ) to write data into and read data from a specific address of the memory module  30 . Each driving unit  23  includes one or more output buffers  27  for outputting a sub-address, and one or more input amplifiers  28  (such as a driving amplifier) for receiving signals input into the driving unit  23 . Each driving unit  23  corresponds to a pin, as marked as BA 0 , BA 1 , and MA 0  to MA 13  in  FIG. 1 , connected to an address pin  32  of the memory module  30 . When the access circuit  21  writes data in a determined address of the memory module  30 , the address module  22  controls each driving unit  23  based on the determined address accordingly, such that each driving unit  23  outputs one-bit (a sub-address) of the determined address. The control module  24  controls the output buffers  27  or the input amplifiers  28  of the driving units  23  to output or receive signals. In addition, the buffer module  26  temporarily stores the configuration of the memory module  30  detected by the BIOS  16  when booting the computer system  10 . When the chipset  20  operates, the control module  24  determines which driving units  23  are required by the memory module  30  based on information of the buffer module  26  so as to disable (i.e. turn off) unused driving units  23 . Since disabled driving units  23  will stop draining power and stop driving corresponding pins, power consumption can be reduced. 
         [0020]    Please refer to  FIG. 2 , which is a flowchart of the operation of the chipset  20 . The steps are as follows. 
         [0021]    Step S 201 : When the computer system  10  is booted, the BIOS  16  detects the configuration of the memory module  30  to determine how many bits are required to assign an address so that number X of required address pins is determined. 
         [0022]    Step S 202 : The number X is stored in the buffer module  26  and is compared to the number of the driving units  23  of the chipset  20 . 
         [0023]    Step S 203 : Determine whether the number X is smaller than the number of the driving units  23  of the chipset  20 . If smaller than the number of the driving units  23 , step S 204  is performed. 
         [0024]    Step S 204 : When the number X is smaller than the number of the driving units  23 , the control module  24  determines which driving units  23  are unused based on the information of the buffer module  26 , and disables such unused driving units  23 , such that the number of the driving units driven by the chipset  20  is equal to the number X of required address pins to reduce power consumption. If the number X is not smaller than the number of the driving units  23 , the control module  24  does not disable any driving units  23 . 
         [0025]    For instance, if the memory capacity of the memory module  30  has 256 MB, which requires 2-bit bank addresses and 13-bit RAS/CAS addresses (13-bitRAS addresses and 10-bit CAS addresses) for addressing, the control module  24  can disable the driving unit  23  corresponding to the pin MA 13 . Pins BA 0 , BA 1  and MA 0  to MA 12  are used to support the configuration of the memory module  30 . Similarly, if the memory capacity of the memory module  30  has 128 MB, which requires 1-bit bank addresses and 13-bit RAS/CAS addresses (13-bit RAS addresses and 10-bit CAS addresses) for addressing, the control module  24  disables the driving units  23  corresponding to pins BA 1  and MA 13 . Fourteen driving units  23  corresponding to pins BA 0 , and MA 0  to MA 12  are used to access the memory module  30 . 
         [0026]    Please refer to  FIG. 3 , which is a diagram of another embodiment of a computer system  50  based on the present invention. Devices or elements of the computer system  50  in  FIG. 3  that have the same functions as those of the computer system  10  in  FIG. 1  have the same reference numerals, and repeated details are omitted. In  FIG. 3 , the computer system  50  comprises two memory modules  60  and  70  using the same bus line connected to the chipset  40 . In other words, the same driving unit  23  is connected to address pins  62  and  72  of the memory modules  60  and  70 . Another difference from the embodiment of  FIG. 1  is that the chipset  40  of  FIG. 3  further includes a comparison module  45 . The memory modules  60  and  70  use the same bus line in the computer system  50 , but the configurations of the two memory modules  60  and  70  might not be the same. The comparison module  45  is used to determine which memory module requires more bits to assign addresses and disables (i.e. turns off) driving units  23  accordingly. Briefly, the comparison module  45  is capable of determining the configurations of the memory modules  60  and  70  so as to disable driving units  23  accordingly. 
         [0027]    Please refer to  FIG. 4 , which is a flowchart of the operation of the chipset  40 . The steps are as follows. 
         [0028]    Step S 401 : When the computer system  50  is booted, the BIOS  16  detects the configurations of the memory modules  60  and  70  to determine how many bits are required to assign an address so that a first number X 1  and a second number X 2  of address pins respectively required by the memory modules  60  and  70  are determined. The first address-pin number X 1  comprises numbers of pins for addressing first bank address and first RAS/CAS address, and the second address-pin number X 2  comprises numbers of pins for addressing second bank address and second RAS/CAS address. 
         [0029]    Step S 402 : The numbers X 1  and X 2  are stored in the buffer module  26 . The control module  45  derives the numbers of first bank-address pins and second bank-address pins from the numbers of X 1  and X 2 , and sets the maximum of the first bank-address number and the second bank-address number to a bank-address-pin maximum. Also, a RAS/CAS-address-pin maximum is derived from the maximum of the first and the second RAS/CAS-address-pin numbers. The control module  45  determines a required address-pin maximum according to the RAS/CAS-address-pin maximum and the bank-address-pin maximum. 
         [0030]    Step S 403 : The required address-pin maximum is compared with the number of driving units  23  of the chipset  20 . When the required address-pin maximum is smaller than the number of the driving units  23 , step S 404  is performed. 
         [0031]    Step S 404 : When the required address-pin maximum is smaller than the number of the driving units  23 , the control module  24  determines which driving units  23  are unused based on the information of the buffer module  26 , and disables such unused driving units  23 , such that the number of the driving units driven by the control module  45  is equal to the required address-pin maximum to reduce power consumption. If the required address-pin maximum is not smaller than the number of the driving units  23 , the control module  24  does not disable any driving units  23 . 
         [0032]    Please refer to  FIG. 5 , which is a diagram of the operation of each driving unit when the computer system  50  of  FIG. 3  is working. Suppose that the chipset  40  supports 2-bit bank addresses (BA 0  and BA 1 ) and 14-bit RAS/CAS addresses (MA 0 -MA 13 ), each bank and RAS/CAS address corresponding to a driving unit  23 . Therefore, the chipset includes 16 driving units  23 , and corresponding memory modules  60  and  70  respectively include 16 address pins  62  and  72  for receiving sub-addresses from the chipset  40 . Suppose that the memory capacity of the memory module  60  is 64 MB, which requires 2-bit bank addresses, 12-bit RAS addresses, and 9-bit CAS addresses. Therefore, assigning address requires BA 0 , BA 1  and MA 0  to MA 11 . Generally, bits of RAS address are more than bits of CAS address, and an RAS address is transmitted before a corresponding CAS address is transmitted. The memory capacity of the memory module  70  is 128 MB, which requires 1-bit bank addresses, 13-bit RAS addresses, and 10-bit CAS addresses, requiring BA 0 , BA 1  and MA 0  to MA 12  to assign addresses. Since the memory modules  60  and  70  use the same bus line, the memory module  70  only needs BA 0  while the memory module  60  still requires both BA 0  and BA 1 . Therefore, the control module  24  determines that the bank-address-pin maximum is 2 and that the RAS/CAS-address-pin maximum is 13 according to the configurations of the memory modules  60  and  70 . To access the memory modules  60  and  70 , BA 0 , BA 1  and MA 0  to MA 12  are used. The control module  24  will disable the driving unit  23  corresponding to pin MA 13 . In  FIG. 5 , the dotted line represents unused address pins  62  and  72  or address pins corresponding to unused driving units  23 . For instance, MA 13  of the memory module  60 , BA 1  and MA 13  of the memory module  70 , and MA 13  of the chipset  40  are unused. 
         [0033]    Additionally, each module of the presented invention can be implemented by hardware or firmware codes. For instance, the comparison module  45  and the control module  24  can be logic circuits. In summary, the BIOS  16  automatically detects the configurations of the memory modules  60  and  70  when the computer system  50  is booted. The comparison module  45  of the chipset  40  determines which address pins  62  and  72  are unused according to the detecting result. Then the control module  24  disables such unused driving units  23 . When the computer system  50  accesses the memory module  60  or  70 , the disabled driving units  23  do not receive/consume power. The present invention can disable unused driving units  23  properly when accessing data so as to reduce power consumption. Therefore, when accessed data is larger, power consumption is reduced by disabling unused driving units  23 . 
         [0034]    The present invention detects configurations of each memory module by the BIOS when booting the computer system, and determines how many address pins are unused accordingly. Then the chipset disables corresponding driving units to reduce power consumption. For instance, suppose that the chipset can support 2-bit bank addresses and 14-bit RAS/CAS addresses, and therefore includes 16 driving units. The memory device includes two memory modules. One has 64 MB and requires 2-bit bank addresses and 12-bit RAS/CAS addresses to assign addresses, and the other has 256 MB and requires 2-bit bank addresses and 13-bit RAS/CAS addresses to assign addresses. According to the configurations of the memory modules, the chipset only has to drive 15 driving units to output 2-bit bank addresses and 13-bit RAS/CAS addresses so as to access the two memory modules. As mentioned above, the present invention utilizes the BIOS to detect the configurations of memory modules, and then determines which address pins are unused accordingly. The control module disables driving units corresponding to unused address pins so as to reduce power consumption. 
         [0035]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.