Abstract:
Power consumption of a low-power flyback power converter under standby-load or no-load conditions is reduced by modulating the OFF time of the flyback transformer&#39;s main switch as a function of the feedback control current when the load drops below a predetermined level. This modulation overcomes the conventional frequency-increasing modulation of the ON time at low output power levels so as to reduce the switching frequency, and hence the switching losses, to minimal levels as the load is reduced. Excessive frequency reduction can optionally be avoided by a clamping feature that limits the expansion of the OFF time.

Description:
FIELD OF INVENTION  
         [0001]    This invention relates to low-power power supplies, and more particularly to circuitry for varying both the ON time and the OFF time of the main current switch in a flyback converter type power supply when the load drops below a predetermined level, so as to reduce the power consumption of the power supply when the device being powered is in a “sleep” mode or turned off.  
         BACKGROUND OF THE INVENTION  
         [0002]    The recent proliferation of rechargeable electronic equipment, such as mobile telephones, PDA&#39;s and notebook computers has dramatically increased the number of chargers connected to the public electricity supply. These chargers typically have no on/off switch and are frequently left permanently “plugged-in” to the wall socket. The “standby” power consumption (i.e., when the equipment is off and any batteries fully charged) of current technology chargers places a significant load on the public electricity supply. It has been estimated that in Europe, such chargers unnecessarily consume the equivalent of the output of three power stations. Environmental and economic considerations therefore make it desirable to significantly reduce the standby power of electronic equipment and chargers. In Germany, regulations known as “Blue Angel”, provide, for example, that cellular phone chargers or personal computers may not consume more than 0.5 W when the equipment is off (i.e., an open load), or 5 W when the equipment is in “sleep” mode.  
           [0003]    Inexpensive low-power conversion systems such as those typically used in cell phone or laptop computer chargers usually use a simple and low-cost self-oscillation flyback converter topology. This type of converter uses pulse width modulation with a fixed OFF time and a variable ON time to accommodate the power requirements of the load. The lighter the load, the higher the switching frequency and hence the higher the switching loss. In conditions where the device is being powered in a “sleep” mode or turned off, the switching loss becomes substantial and needs to be remedied.  
           [0004]    Conventionally, excessive switching loss is reduced by “burst mode” operation in which the pulse width modulator is randomly switched between an OFF mode and an ON mode. The burst rate is unpredictable and is affected by a number of factors, such as the loop response and other second-order circuit parameters. This method has several major problems:  
           [0005]    1) The circuit consumes high power at no load and light load, especially before the “burst mode” operation is activated;  
           [0006]    2) The unpredictable random “burst” operation may create electromagnetic interference and ripple problems;  
           [0007]    3) The system has poor flexibility in setting the operational point at which power saving is initiated;  
           [0008]    4) The response of a particular unit is difficult to control over a production spread; and  
           [0009]    5) Audible noise is generated in “burst mode” operation.  
           [0010]    The disadvantages of random “burst” operation have been addressed in U.S. Pat. Nos. 5,481,178, 5,731,694 and 5,994,885 to Wilcox, et al. In those patents, “burst” operation is still used, but the burst rate is dependent on the output capacitor and the offset current II. The circuits of these patents have an off-time control but only for the purpose of limiting the switching frequency to keep it out of the audible range.  
           [0011]    A need consequently still exists for a reliable, predictable, controllable and quiet power reduction circuit for standby-load or no-load conditions in low-power electronic power supplies.  
         SUMMARY OF THE INVENTION  
         [0012]    The present invention fills the above-stated need by providing a circuit which operates as a conventional ON time modulator under normal load conditions, but switches to a dual mode modulation when the load is reduced to a predetermined level. In the dual mode, the circuit modulates both the ON time and the OFF time simultaneously in opposite directions. By setting the gain of the OFF time control higher than the gain of the ON time control, the switching frequency is reduced as the output power declines. Consequently, the circuit of the invention has the following advantages:  
           [0013]    1) Input power is reduced at both no load and light load;  
           [0014]    2) No audible noise due to lack of “bursts” under no-load conditions;  
           [0015]    3) Predictable behavior at no load;  
           [0016]    4) Cut-in level of power saving mode can easily be set by appropriate choice of component values and is therefore repeatable over the production spread; and  
           [0017]    5) The circuit has better large-step load response due to the dual mode modulation. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]    The forgoing aspects and the attendant advantages of the present invention will become more readily appreciated by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:  
         [0019]    [0019]FIG. 1 is a block diagram illustrating the basic function the inventive components of the converter circuit;  
         [0020]    [0020]FIG. 2 is a circuit diagram of a preferred embodiment of a flyback converter circuit of this invention;  
         [0021]    [0021]FIG. 3 is a waveform diagram showing various waveforms in the circuit of FIG. 2;  
         [0022]    [0022]FIG. 4 is a circuit diagram of an alternative embodiment of a flyback converter circuit of the invention;  
         [0023]    [0023]FIG. 5 is a waveform diagram showing various waveforms in the circuit of FIG. 4; and  
         [0024]    [0024]FIG. 6 is an output power vs. switching frequency diagram for the circuit of FIG. 2. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0025]    The block diagram of FIG. 1 illustrates the components which control the operation of the inventive converter circuit. A load-responsive feedback control signal  10 , which is an inverse function of the load on the power supply output, is applied to a dual slope ramp generator  12  and to a current comparator  14 . The dual slope ramp generator  12  generates a ramp signal having a first slope with a steep, fixed gradient  16  followed by a less steep slope  18  that is modulated by the feedback control signal  10 . The gradient of the first slope, the rate of change of the second slope, the minimum gradient of the second slope, and the turning point from the first to the second slope are all determined by component values in the circuit as discussed below. The ramp generator  12  is reset by the ramp reset signal  20  when the gate drive  22  is ON.  
         [0026]    The ramp signal  24  generated by the dual slope ramp generator  12  is compared by a comparator  26  to a reference  28 . When the ramp signal  24  exceeds the reference  28 , an ON trigger signal  30  is coupled to a gate driver  32 .  
         [0027]    ON time modulation of the main switch  38  is generated in a conventional way. A current comparator  14  compares the control signal  10  to a current ramp signal  34  which is generated in line  36  during the ON time of main switch  38  by the flyback action of the converter. When the current in line  36  exceeds the current of control signal  10 , the current comparator  14  couples an OFF trigger signal  40  to the gate driver  32 . The relationship of the control signal  10  to the current in line  36  is such that the ON time of switch  38 , which is a direct function of the load, can become minimal but not zero at no load.  
         [0028]    [0028]FIG. 2 illustrates a first preferred embodiment of the inventive flyback converter circuit. It operates as follows: On startup, a voltage PV cc  is conventionally developed on line  42  as capacitor  44  is charged from the input voltage  46  through voltage divider resistors  48 . A capacitor  50  is concurrently charged from PV cc  through resistors  54  and  56 . During startup, the current sink  58  is off and diode  60  is reverse biased, so that resistor  62  does not affect the charging of capacitor  50 . The voltage of capacitor  50  is compared to the bias voltage of transistor  64 , which is set at ½ PV cc  by voltage divider resistors  66  and  68 . When the charge on capacitor  50  reaches ½ PV cc , a pulse of amplitude PV cc  is generated on the emitter of transistor  70 . This pulse peak charges the gate of the main switch  38  and initiates the switching cycle, causing the generation of PV cc  to be taken over by the auxiliary winding  72  of transformer  74  via diode  73  and capacitor  44 .  
         [0029]    The ON time of main switch  38 , during which energy is stored in the primary winding  75  of transformer  74 , is controlled by the OFF trigger signal  40  of FIG. 1.  
         [0030]    The OFF trigger signal  40  is generated as follows: The control current sink  58  is controlled by the voltage feedback loop signal  10  which is a function of the load. The current sink  58  produces a DC bias voltage equal to I c *(R 76  +R 78 ) on the base of transistor  80 . Resistor  78  is a current sense resistor of very low impedance as compared to resistor  76 , so that the bias voltage on the base of transistor  80  is essentially I c * R 76 . When the main switch  38  turns on, its drain current I d  ramps up so that a ramp voltage I d * R 78  is produced and added to the bias produced by current sink  58 . Eventually, the total base bias on transistor  80  reaches the threshold of 0.6V at which point transistor  80  turns on and discharges the gate of main switch  38  to turn it off. Thus, the ON time of main switch  38  is controlled only by the load-responsive current sink  58  and the values of resistors  76  and  78  in a conventional manner.  
         [0031]    In accordance with the invention, the OFF time of main switch  38 , during which energy is released by primary winding  75 , is not fixed as in conventional flyback converters, but is controlled differently at high loads than at low loads or no load. The inventive OFF time modulation works as follows (to generate the ON trigger signal  30 ): When the main switch  38  turns off, capacitor  50  charges up from PV cc  through resistors  54  and  56  just as on start-up. The OFF time of main switch  38  is determined by the time required to charge capacitor  50  to ½ PV cc . The charging time t of capacitor  50  is  
           t=−C   50   R   54+56 *1 n (1− V   50   /PV   cc ).  
         [0032]    Unlike at startup, however, diode  60  may no longer be back-biased, and some of the charging current of capacitor  50  may be diverted through resistor  62 , depending upon the voltage drop across resistor  82 . At high load, the main switch drain current I d  is high and the current through current sink  58  is low enough to maintain the voltage drop across resistor  82  at less than ½ PV cc . Diode  60  is still reverse biased, and  
           t=−C   50   *R   54+56 *1 n (1−½  PV   cc   /PV   cc )=0.7 C   50   *R   54+56 .  
         [0033]    These quantities being constant, the OFF time at high loads is constant, and the switching frequency depends only on the ON time modulation provided by the OFF trigger signal  40 .  
         [0034]    If the load is now reduced to a level such that the current I c  through current sink  58  becomes high enough to produce a voltage drop across resistor  82  greater than ½ PV cc , the OFF period of main switch  38  is no longer constant. To simplify the analysis of what happens, the following assumptions can be made: a) the current through resistor  62  and diode  60  (which is now no longer reverse-biased) is so small compared to I c  that it has no significant effect on the main control loop nor on the bias voltage across resistor  82 ; b) the forward voltage drop across diode  60  is negligible; and c) resistor  54  is very much greater than resistor  56  so that resistor  56  can be disregarded in the charging process of capacitor  50 .  
         [0035]    With the foregoing assumptions in mind, the charging process of capacitor  50  can be seen to be divided into two stages. In the first stage, capacitor  50  charges from zero to PV cc −(I c *R 82 ) in the same manner as described above for high loads. In the second stage, capacitor  50  charges from PV cc −(I c *R 82 ) to ½ PV cc  . In the second stage, charging is slower because some of the charging current is diverted through resistor  62  and diode  60 . The charging time t 1  of the first stage is simply  
           t   1   =−C   50   *R   54 *1 n ( I   c   *R   82   /PV   cc ).  
         [0036]    In computing the charging time t 2  of the second stage, the equivalent charging voltage source is  
           V   0   =[PV   cc   *R   62 +( PV   cc   −I   c   * R   82 )*  R   54 ]/( R   54   +R   62 ),  
         [0037]    which resolves into  
           V   0   =PV   cc −( I   c   *R   82   *R   54 /( R   54   +R   62 )).  
         [0038]    With the equivalent output impedance being  
           R=R   54   *R   62 /( R   54   +R   62 ),  
         [0039]    the second stage charging time is  
           t   2   =−C   50   *R* 1 n (1−½  PV   cc   /V   0 )+ C   50   *R* 1 n [1−( PV   cc −( I   c   * R   82 )) V   0 ].  
         [0040]    Because V 0  decreases with increasing I c , both terms of the t 2  equation increase with increasing I c . Consequently, as the load approaches the standby-load or no-load condition, capacitor  50  takes longer to charge, the OFF time of main switch  38  gets longer, and the switching frequency drops.  
         [0041]    The operation of the inventive circuit of FIG. 2 is illustrated in FIG. 3, in which graph  84  depicts the load current, graph  86  depicts the main switch current I d , graph  88  depicts the control current I c , graph  90  depicts the charging ramp of capacitor  50 , and graph  92  depicts the resulting gate drive for main switch  38 . The dotted graph  94  depicts the voltage of node A, the junction of resistor  82  and diode  60 , with reference to common. The threshold value of the control current I c  at which the OFF time modulation starts can be adjusted by an appropriate selection of R 82 . The threshold control current I c(th)  is determined by R 82  in accordance with the formula I c(th) =½ PV cc /R 82 . Once R 82  is chosen, the OFF time change rate can be adjusted by varying R 62 . The smaller R 62 , the greater the charging current diverted from resistor  54  and the higher the OFF time change rate. If R 62  is made too small, however, capacitor  54  can never be charged up to ½ PV cc , and the circuit goes into an undesirable clamped low frequency mode in which I c  starts to oscillate. By postulating an infinite OFF time at zero load, the minimum value of R 62  can be calculated to be  
           R   62min   =R   54 *[1.2* R   82 /( R   76   *PV   cc )−1].  
         [0042]    In practice, where some small amount of power is dissipated to the output circuit even at no load, R 62  must be kept sufficiently above its minimum value to prevent the switching frequency at zero load from falling below the minimum necessary to keep the output rail in regulation.  
         [0043]    An alternative way to prevent clamped low frequency operation is shown in the embodiment of a flyback converter shown in FIG. 4. In this alternative embodiment, a zener clamping diode  96  is coupled in parallel with resistor  82  to limit the voltage drop across resistor  82 . The clamping action of zener diode  96  prevents t 2  from becoming excessively large and thereby allowing the switching frequency to drop below acceptable limits. The effect of the zener diode  96  on the operation of the circuit is shown in FIG. 5, which uses the same graphs as FIG. 3 but shows voltage  98  as the zener clamping voltage. Although the zener diode  96  has no effect on the ON time of main switch  38 , which is regulated by I c , it does prevent the OFF time from increasing any further once I c  has reached the level of V z /R 82 , where V z  is the zener voltage.  
         [0044]    Some specific examples of appropriate settings of the inventive circuit are as follows: For a PC power supply auxiliary converter such as a 10W auxiliary supply, the “Blue Angel” condition in standby mode is defined as a 5W input. The desirable working frequencies are about 60 kHz from 10 W to 7W and about 25 kHz below 7W. For that purpose, R 82  would be chosen in the inventive circuit to start the frequency reduction at 7W. The voltage drop across resistor  82  at 5W can then be calculated, and in the embodiment of FIG. 4 a zener diode of that voltage would be shunted across resistor  82 . Finally, resistor  62  would be selected to set the switching frequency to 25 kHz at 5W.  
         [0045]    For a cell phone charger or adapter, the “Blue Angel” condition is defined as no load. Desirable working frequencies for a 6.5W charger are about 60 kHz from 6.5W to 3W, decreasing to less than 1 kHz at no load. R 82  is first set at 4.7K to set the onset of frequency reduction at 3W. R 62min  is then calculated to be about 42K at a PV cc  of 18V. With that value of R 62 , the circuit will just enter the clamped low frequency mode at no load.  
         [0046]    The circuit of this invention provides power savings of about 0.15W in the second example over a corresponding prior art circuit at no load. At a light load of about 0.1W output power, which in the prior art would be just before the onset of the “burst” mode, the savings are even greater: about 0.25 W. FIG. 6 illustrates the sharp decline in switching frequency as the output power approaches the no-load condition in a 6.5W charger with a 39K value of R 62 .  
         [0047]    As a matter of illustration, component values have been indicated in FIG. 2. These are, however, given only as examples, and it should be understood that the invention can be carried out in many different ways encompassed by the scope of the following claims. In general, the embodiments of the apparatus described above are illustrative of the principles of the present invention and are not intended to limit the invention to the particular embodiments described. Other embodiments of the present invention can be adapted for use in standby power or no-load environment. Accordingly, while the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.