Abstract:
A magnetic recording control circuit for controlling current through a magnetic recording head includes a switch network, a signal coupler, and first and second voltage clamps. The switch network is connected to first and second magnetic recording head node regions and includes first, second, third, and fourth switches each having a variable magnitude conduction path and a control region. The signal coupler includes an input region and a plurality of output regions each connected to the control region of a corresponding switch. The first and second voltage clamps limit voltage differences between the magnetic recording head node regions and the control regions of the first and second switches.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims priority from Provisional Application No. 60/082,322, filed Apr. 20, 1998 for “H-Switch Speedup and Breakdown Prevention” by John J. Price, Jr. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a magnetizing current control circuit which operates with a magnetic recording head in a magnetic data storage and retrieval system. In particular, the present invention relates to a magnetizing current control circuit having improved switching performance and circuit component voltage breakdown prevention. 
     In magnetic data storage and retrieval systems, a magnetic recording head records two-logic-state data to a magnetic data storage medium, such as a magnetic tape or magnetic disc. The magnetic recording head has an inductive coil with currents provided therethrough in alternate directions, representing the data, to impart a series of alternate magnetic field patterns over time to the magnetic medium moving by it. Producing alternate magnetic field patterns over time entails switching the electric current through the inductive coil between forward and reverse directions therethrough to correspond to the data. Current flowing through the inductive coil generates a magnetic field oriented in a direction corresponding to the direction of flow through the coil; thus, reversing the direction of current reverses the orientation of the magnetic field. The magnetic fields generated by the inductive coil currents intersect the magnetic medium to polarize adjacent magnetic medium regions which in effect serve as data symbol storage positions on the medium and so form magnetic patterns along a corresponding one of more or less concentric tracks in the medium from which an information signal can be retrieved. 
     Controlling the directions of currents through the inductive coil is the purpose of a magnetizing current control circuit. A typical magnetizing current control circuit includes a switching network and a signal coupler. The switching network is connected to the ends of the inductive coil in the magnetic recording head at first and second head nodes, and includes four switching transistors arranged as pairs with each pair member connected to a corresponding one of these head nodes. One pair is switched on directing current flow in one direction through the inductive coil with the other pair switched off and, alternatively, this latter pair is switched on to direct current flow through the inductive coil in the opposite direction with the first pair being switched off. More specifically, the switching transistors are connected to the inductive coil such that a first switching transistor is connected between a first electrical power source and the first head node, a second switching transistor is connected between the first electrical power source and the second head node, a third switching transistor is connected between the first head node and a second electrical power source, and a fourth switching transistor is connected between the second head node and the second electrical power source. 
     The signal coupler, which responds to input signals, provides control signals to selectively switch the four switching transistors on and off in pairs, thereby controlling the direction of current through the inductive coil. Specifically, to direct current in one direction through the inductive coil, the signal coupler switches on the first and fourth switching transistors and switches off the second and third switching transistors. Conversely, to direct current in the opposite direction through the inductive coil, the signal coupler switches off the first and fourth switching transistors and switches on the second and third switching transistors. 
     One principle concern in the performance of magnetizing current control circuits is the duration of time needed to complete a switching of current direction through the inductive coil which directly affects the switching rate. Switching rate, a measure of how often the magnetizing current control circuit can reverse current direction through the inductive coil per unit of time, determines the maximum linear spatial density of data along a track in the magnetic medium. Ultimately, a higher switching rate yields denser data storage and thus greater total data capacity for a magnetic medium. 
     A key determinant of the current reversal switching time duration is the head swing voltage, i.e. the voltage difference between the head nodes of the magnetizing current control circuit. The larger the voltage drop applied in the opposite direction across the inductive coil after a switching to reverse the current therethrough, the quicker the change in direction of current through the inductive coil. This is because the voltage-current characteristic of an inductive coil is determined by V=Ldi/dt+R L I, where V is the voltage across the inductive coil, di/dt is the rate of change of current over time through the inductive coil, L is the inductance of the inductive coil, R L  is the resistance of the inductive coil, and I is the current through the inductive coil. Because the inductance of the inductive coil is constant and the resistance of the inductive coil is relatively small, there is a direct relationship between the voltage impressed across the inductive coil after switching and the rate of change of current over time through the inductive coil. 
     In typical magnetizing current control circuits, the head swing voltage is equal to the voltage difference between the emitters of the first and second switching transistors. In order to create a large voltage difference between the emitters of the first and second switching transistors after a switching to reverse the current through the inductive coil, a similarly large voltage difference is applied to the bases of the first and second switching transistors. After the direction of current changes through the inductive coil, the voltage difference between the emitters of the first and second switching transistors (which is equal to the head swing voltage) decreases to nearly zero while the voltage difference between the bases of the first and second switching transistors remains constant. As a result, the remainder of the large voltage difference between the bases of the first and second switching transistors is compensated by the base-emitter pn junction of either the first or second switching transistor. However, the base-emitter pn junctions of the switching transistors have a low breakdown voltage. Exceeding the breakdown voltage allows a reverse current to flow through these base-emitter pn junctions, and over time sufficiently degrades the current gain of the switching transistors, thereby reducing current to the magnetic recording head and ultimately the magnetic strength of the data it records to a magnetic medium. To avoid exceeding the breakdown voltage of these base-emitter pn junctions it is typically necessary to sacrifice switching rate by limiting head swing voltage (e.g. limiting the voltage difference between the first and second electrical power sources). 
     Accordingly, there is a need for a magnetizing current control circuit that prevents breakdown of the first and second switching transistors without diminishing the head swing voltage. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention is a magnetic recording control circuit for controlling current through a magnetic recording head. A switch network is connected to first and second magnetic recording head node regions and includes first, second, third, and fourth switches each having a variable magnitude conduction path and a control region. A signal coupler includes an input region and a plurality of output regions each connected to the control region of a corresponding switch. First and second voltage clamps limit voltage differences between the magnetic recording head node regions and the control regions of the first and second switches. In one preferred embodiment, each of the switches and voltage clamps are bipolar junction transistors having a collector, an emitter, and a base. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit schematic diagram of a magnetic recording control circuit embodying the present invention. 
     FIG. 2 shows a voltage waveform plot of the voltage at the base of the first switching transistor in the magnetic recording control circuit of FIG.  1 . 
     FIG. 3 shows a current waveform plot of the current through an inductive coil connected to the magnetic recording control circuit of FIG.  1 . 
     FIG. 4 shows a voltage waveform plot of the voltage between the emitter and the base of the first switching transistor in the magnetic recording control circuit of FIG.  1 . 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a circuit schematic diagram of a magnetic recording control circuit  10  embodying the present invention. Magnetic recording control circuit  10  controls the magnitude and direction of current through a magnetic recording head  11  represented in the diagram as an inductive coil L H . Magnetic recording head  11 , which is coupled into the remainder of the circuit between circuit head nodes H 1  and H 2 , includes inductive coil L H  along with magnetic material positioned in magnetic fields generated by current there through. Magnetic recording control circuit  10  includes a switching network  12 , a signal coupler  14  in two separate sections, voltage clamping transistors Q 7  and Q 8 , operating voltage source nodes V 1  and V 2 , current generators I 1  and I 2 , input signal circuit nodes WDP and WDN, and the circuit head nodes H 1  and H 2  previously mentioned. 
     Switching network  12  includes switching transistors Q 1 -Q 4 . Switching transistors Q 1 -Q 4  are npn bipolar junction transistors each having a collector, an emitter, and a base. Each of switching transistors Q 1  and Q 2  has its collector connected to operating voltage source node V 1  and the emitter of each is connected to a corresponding one of head nodes H 1  and H 2 . Each of switching transistors Q 3  and Q 4  has its collector connected to a corresponding one of head nodes H 1  and H 2  and the emitter of each is connected to one side of current generator I 1 , the other side of which is connected to operating voltage source node V 2 . The bases of switching transistors Q 1 -Q 4  are each connected to a corresponding one of the outputs of signal coupler  14 . 
     Signal coupler  14  includes switching transistors Q 5  and Q 6  and resistors R 1  and R 2 . Switching transistors Q 5  and Q 6  are npn bipolar junction transistors each having a collector, an emitter, and a base. Input signal nodes WDP and WDN are directly connected respectively to the bases of switching transistors Q 5  and Q 6  in signal coupler  14  and to the bases of switching transistors Q 3  and Q 4  in switching network  12 . Each of switching transistors Q 5  and Q 6  has its emitter connected to one side of current generator I 2 , and the collector of each is connected to operating voltage source node V 1  through a corresponding one of resistors R 1  and R 2 . The other side of current generator I 2  is connected to operating voltage source node V 2 . 
     Voltage clamping transistors Q 7  and Q 8  are npn bipolar junction transistors each having a collector, an emitter, and a base. Each of voltage clamping transistors Q 7  and Q 8  has its collector connected to operating voltage source node V 1 . Also, the emitter of each is connected to the base of a corresponding one of switching transistors Q 1  and Q 2 , and the base of each is connected to a corresponding one of head nodes H 1  and H 2 . 
     In an initial input signal situation chosen for purposes of description, input signal node WDN has a significantly higher voltage than input signal node WDP, for example. In the steady state, with the initial input signal so as to result in the voltage at WDN being greater than that at WDP, switching transistor Q 5  in signal coupler  14  will be found to be turned off, switching transistor Q 6  in signal coupler  14  will be found to be turned on, switching transistors Q 1  and Q 4  in switching network  12  will be found to be turned on, switching transistors Q 2  and Q 3  in switching network  12  will be found to be turned off, voltage clamping transistor Q 7  will be found to be turned off, and voltage clamping transistor Q 8  will be found to be turned on. The voltages at head nodes H 1  and H 2  will be found to be approximately V 1 −VBE, as the base current of switching transistor Q 1  is small and the resistance of inductive coil L H  is low (VBE is the voltage drop across the base-emitter pn junction of switching transistor Q 1 ). Current I 1  will be found to be drawn from operating voltage source node V 1 , primarily through the collector and emitter of switching transistor Q 1 , through magnetic recording head  11  from head node H 1  to H 2 , through the collector and emitter of switching transistor Q 4 , through current generator I 1 , and into operating voltage source node V 2 . Current I 2  will be found to be drawn from operating voltage source node V 1 , primarily through resistor R 2  and the collector and emitter of voltage clamping transistor Q 8 , through the collector and emitter of switching transistor Q 6 , through current generator I 2 , and into operating voltage source node V 2 . 
     When the input signal on nodes WDP and WDN is subsequently changed to then have a significantly higher voltage at input signal node WDP than at input signal node WDN, signal coupler  14  passes this change therethrough to turn on switching transistor Q 3  in switching network  12  and to turn off switching transistor Q 4  in switching network  12 . In addition, in this circumstance, switching transistor Q 5  in signal coupler  14  is turned on and switching transistor Q 6  in signal coupler  14  is turned off, thereby drawing an increased current through resistor R 1  (because voltage clamping transistor Q 7  remains initially still turned off as it was prior to the change at input signal nodes WDP and WDN) and reducing the current drawn through resistor R 2 . This condition causes the voltage at the base of switching transistor Q 1  to initially drop to approximately V 1 −R 1 I 2  and the voltage at the base of switching transistor Q 2  to rise toward operating source voltage V 1 . With switching transistor Q 3  turned on and the voltage at the base of switching transistor Q 1  (which remains initially still turned on as it was prior to the change at input signal nodes WDP and WDN) approximately V 1 −R 1 I 2 , the voltage at the emitter of switching transistor Q 1  is approximately V 1 −R 1 I 2 −VBE, where VBE is the voltage drop across the base-emitter pn junction of switching transistor Q 1 . In addition, when the voltage at the base of switching transistor Q 2  begins to rise toward operating source voltage V 1 , voltage clamping transistor Q 8  is turned off because the voltage at the emitter of voltage clamping transistor Q 8  (which is equal to the voltage at the base of switching transistor Q 2 ) is no longer a VBE lower than the voltage at its base (which is equal to the voltage at head node H 2  and is still approximately V 1 −VBE as it was prior to the change at input signal nodes WDP and WDN). When the voltage at the base of switching transistor Q 2  is approximately at operating source voltage V 1 , switching transistor Q 2  is turned on because the base of switching transistor Q 2  is then a VBE higher than the voltage at its emitter (which is equal to the voltage at head node H 2 ). 
     Because the voltage at head node H 1  (which is equal to the voltage at the emitter of switching transistor Q 1 ) is approximately V 1 −R 1 I 2 −VBE and the voltage at head node H 2  is approximately V 1 −VBE, a voltage drop of approximately R 1 I 2  volts is initially created across inductive coil L H  from head node H 2  to H 1 . As a result, current I 1  (which, prior to the change at input signal nodes WDP and WDN, was flowing through inductive coil L H  from head node H 1  to H 2 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 2  to H 1 . 
     After the change in direction of current I 1  through inductive coil L H  so that current I 1  now flows from head node H 2  to H 1 , the voltage at head node H 1  will rise to nearly the voltage at head node H 2 . This is because once the direction of current I 1  is established, the rate of change of current I 1  will decrease to nearly zero and cause the voltage across inductive coil L H  to also decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 2  is held approximately constant during the remainder of this input signal situation because the voltage drop VBE across the base-emitter pn junction of switching transistor Q 2  (which is turned on) is approximately constant and the voltage drop across resistor R 2  is small because of the gain of switching transistor Q 2 . Therefore, as the voltage difference between head nodes H 2  and H 1  decreases to nearly zero, the voltage at head node H 1  will rise to nearly the voltage at head node H 2 . 
     When the voltage at head node H 1 (which is equal to the voltage at the emitter of switching transistor Q 1 ) begins to rise from V 1 −R 1 I 2 −VBE with the decreasing voltage across inductive coil L H , switching transistor Q 1  will be turned off because the voltage at the emitter of switching transistor Q 1  is no longer a VBE lower than the voltage at its base (which is held at approximately V 1 −R 1 I 2  by transistor Q 5  being turned on). As the voltage at head node H 1  continues to rise toward V 1 −VBE (which is the voltage at head node H 2 ), it will eventually be a VBE higher than the voltage at the base of switching transistor Q 1 . When this occurs, voltage clamping transistor Q 7  is turned on because the voltage at the base of voltage clamping transistor Q 7  (which is equal to the voltage at head node H 1 ) is a VBE higher than the voltage at its emitter (which is equal to the voltage at the base of switching transistor Q 1 ). For the remainder of this input signal situation after voltage clamping transistor Q 7  is turned on, as the voltage at head node H 1  rises, voltage clamping transistor Q 7  causes the voltage at the collector of switching transistor Q 5  and so at the base of switching transistor Q 1  to also rise. This is because the rising voltage at the base of voltage clamping transistor Q 7  forces its emitter voltage to rise through drawing an increased current through the collector and emitter of voltage clamping transistor Q 7  to supply some of the collector current to switching transistor Q 5  which reduces the current drawn through R 1  so that the voltage thereacross decreases. As a result, voltage clamping transistor Q 7  limits the voltage difference between head node H 1  and the base of switching transistor Q 1  to a VBE, where VBE is the voltage drop across the base-emitter pn junction of voltage clamping transistor Q 7 . Thus, when the voltage at head node H 1  is nearly V 1 −VBE (which is the voltage at head node H 2 ), the voltage at the base of switching transistor Q 1  is approximately V 1 − 2 VBE. 
     Therefore, because switching transistors Q 2  and Q 3  are turned on and switching transistors Q 1  and Q 4  are turned off with the voltage at node WDP exceeding that at node WDN, current I 1  is drawn from operating voltage source node V 1 , primarily through the collector and emitter of switching transistor Q 2 , through magnetic recording head  11  from head node H 2  to H 1 , through the collector and emitter of switching transistor Q 3 , through current generator I 1 , and into operating voltage source node V 2 . As described above, the voltage at the collector of switching transistor Q 5  and the base of switching transistor Q 1  is also raised in this situation by voltage clamping transistor Q 7  from approximately V 1 −R  1 I 2  to nearly within a VBE of the voltage at head node H 2 . voltage at the collector of switching transistor Q 5 , in starting closer to operating source voltage V 1 , rises to voltage V 1  more quickly when the input signal situation is subsequently reversed to the voltage at node WDN exceeding that at node WDP. This is because switching transistor Q 5  has at its collector inherent structural and other associated, or parasitic, capacitances which require charging or discharging during switching and prevent the voltage at the collector of switching transistor Q 5  from instantaneously rising to operating voltage V 1 . Also, because voltage clamping transistor Q 7  keeps the voltage at the emitter of switching transistor Q 1  (which is equal to the voltage at head node H 1 ) a VBE higher than the voltage at the base of switching transistor Q 1 , switching transistor Q 1  is held off without any possibility that the breakdown voltage of the base-emitter pn junction of switching transistor Q 1  will be exceeded because it is greater than a VBE. 
     Waveform  20  in FIG. 2 shows the voltage waveform at the base of switching transistor Q 1  during both input signal relative magnitude situations. Waveform  22  shows the voltage waveform at the same location in a magnetic recording control circuit without the presence of voltage clamping transistors Q 7  and Q 8 . The start of an input signal situation in which the voltage at node WDN changes from exceeding that at node WDP to the opposite condition begins at 15 ns and ends at 30 ns in FIG.  2 . Waveform  22  shows that without voltage clamping transistors Q 7  and Q 8 , the voltage at the base of switching transistor Q 1  drops below 1.5 V and, after a short voltage increase, remains low until the next change in the input signal. Waveform  20  shows that with voltage clamping transistors Q 7  and Q 8 , the voltage at the base of switching transistor Q 1  also drops below 1.5 V but then has a short voltage increase to settle at approximately 5.2 V at which value this voltage remains until the next relative magnitude change in the input signal on nodes WDP and WDN. 
     Waveform  24  in FIG. 3 shows the current through inductive coil L H  from head node H 2  to H 1  during the same input signal situations depicted in FIG.  2 . Waveform  26  shows the current in the same direction through inductive coil L H  in a magnetic recording control circuit without the presence of voltage clamping transistors Q 7  and Q 8 . The start of an input signal situation in which the voltage at node WDN changes from exceeding that at node WDP to the opposite condition begins at 15 ns and ends at 30 ns in FIG.  3 . Waveform  26  shows that without voltage clamping transistors Q 7  and Q 8 , the current through inductive coil L H  changes direction and rises to 59 mA at approximately 18.5 ns. Waveform  24  shows that with voltage clamping transistors Q 7  and Q 8 , the current through inductive coil L H  changes direction and rises to 59 mA at approximately 18.0 ns. 
     Waveform  28  in FIG. 4 shows the voltage waveform across the emitter-base pn junction of switching transistor Q 1  during the same input signal situations depicted in FIG.  2 . Waveform  30  shows the voltage waveform at the same location in a magnetic recording control circuit without the presence of voltage clamping transistors Q 7  and Q 8 . The start of an input signal situation in which the voltage at node WDN changes from exceeding that at node WDP to the opposite condition begins at 15 ns and ends at 30 ns in FIG.  4 . Waveform  30  shows that without voltage clamping transistors Q 7  and Q 8 , the voltage across the emitter-base pn junction of switching transistor Q 1  rises to over 8 V. Waveform  28  shows that with voltage clamping transistors Q 7  and Q 8 , the voltage across the emitter-base pn junction of switching transistor Q 1  never exceeds 2.5V. 
     When the input signal on nodes WDP and WDN is subsequently changed to again have a significantly higher voltage at input signal node WDN than at input signal node WDP as in the initial input signal steady state situation described above, signal coupler  14  passes this change therethrough to turn on switching transistor Q 4  in switching network  12  and to turn off switching transistor Q 3  in switching network  12 . In addition, in this circumstance, switching transistor Q 6  in signal coupler  14  is turned on and switching transistor Q 5  in signal coupler  14  is turned off, thereby drawing an increased current through resistor R 2  (because voltage clamping transistor Q 8  remains initially still turned off as it was prior to the change at input signal nodes WDP and WDN) and reducing the current drawn through resistor R 1 . This condition causes the voltage at the base of switching transistor Q 2  to initially drop to approximately V 1 −R 2 I 2  and the voltage at the base of switching transistor Q 1  to rise toward operating source voltage V 1 . With switching transistor Q 4  turned on and the voltage at the base of switching transistor Q 2  (which remains initially still turned on as it was prior to the change at input signal nodes WDP and WDN) approximately V 1 −R 2 I 2 , the voltage at the emitter of switching transistor Q 2  is approximately V 1 −R 2 I 2 −VBE, where VBE is the voltage drop across the base-emitter pn junction of switching transistor Q 2 . In addition, when the voltage at the base of switching transistor Q 1  begins to rise toward operating source voltage V 1 , voltage clamping transistor Q 7  is turned off because the voltage at the emitter of voltage clamping transistor Q 7  (which is equal to the voltage at the base of switching transistor Q 1 ) is no longer a VBE lower than the voltage at its base (which is equal to the voltage at head node H 1  and is still approximately V 1 −VBE as it was prior to the change at input signal nodes WDP and WDN). And when the voltage at the base of switching transistor Q 1  is approximately at operating source voltage V 1 , switching transistor Q 1  is turned on because the base of switching transistor Q 1  is then a VBE higher than the voltage at its emitter (which is equal to the voltage at head node H 1 ). 
     Because the voltage at head node H 2  (which is equal to the voltage at the emitter of switching transistor Q 2 ) is approximately V 1 −R 2 I 2 −VBE and the voltage at head node H 1  is approximately V 1 −VBE, a voltage drop of approximately R 2 I 2  volts is initially created across inductive coil L H  from head node H 1  to H 2 . As a result, current I 1  (which, prior to the change at input signal nodes WDP and WDN, was flowing through inductive coil L H  from head node H 2  to H 1 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 1  to H 2 . 
     After the change in direction of current I 1  through inductive coil L H  so that current I 1  now flows from head node H 1  to H 2 , the voltage at head node H 2  will rise to nearly the voltage at head node H 1 . When the voltage at head node H 2  (which is equal to the voltage at the emitter of switching transistor Q 2 ) begins to rise from V 1 −R 2 I 2 −VBE with the decreasing voltage across inductive coil L H , switching transistor Q 2  will be turned off because the voltage at the emitter of switching transistor Q 2  is no longer a VBE lower than the voltage at its base (which is held at approximately V 1 −R 2 I 2  by transistor Q 6  being turned on). As the voltage at head node H 2  continues to rise toward V −VBE (which is the voltage at head node H 1 ), it will eventually be a VBE higher than the voltage at the base of switching transistor Q 2 . When this occurs, voltage clamping transistor Q 8  is turned on because the voltage at the base of voltage clamping transistor Q 8  (which is equal to the voltage at head node H 2 ) is a VBE higher than the voltage at its emitter (which is equal to the voltage at the base of switching transistor Q 2 ). For the remainder of this input signal situation after voltage clamping transistor Q 8  is turned on, as the voltage at head node H 2  rises, voltage clamping transistor Q 8  causes the voltage at the collector of Q 6  and so at the base of switching transistor Q 2  to also rise. This is because the rising voltage at the base of voltage clamping transistor Q 8  forces its emitter voltage to rise through drawing an increased current through the collector and emitter of voltage clamping transistor Q 8  to supply some of the collector current to switching transistor Q 6  which reduces the current drawn through R 2  so that the voltage thereacross decreases. As a result, voltage clamping transistor Q 8  limits the voltage difference between head node H 2  and the base of switching transistor Q 2  to a VBE, where VBE is the voltage drop across the baseemitter pn junction of voltage clamping transistor Q 8 . Thus, when the voltage at head node H 2  is nearly V 1 −VBE (which is the voltage at head node H 1 ), the voltage at the base of switching transistor Q 2  is approximately V 1 − 2 VBE. 
     Therefore, because switching transistors Q 1  and Q 4  are turned on and switching transistors Q 2  and Q 3  are turned off with the voltage at node WDN exceeding that at node WDP, current I 1  is drawn from operating voltage source node V 1 , primarily through the collector and emitter of switching transistor Q 1 , through magnetic recording head  11  from head node H 1  to H 2 , through the collector and emitter of switching transistor Q 4 , through current generator I 1 , and into operating voltage source node V 2 . As described above, the voltage at the collector of switching transistor Q 6  and the base of switching transistor Q 2  is also raised in this situation by voltage clamping transistor Q 8  from approximately V 1 −R 2 I 2  to nearly within a VBE of the voltage at head node H 1 . As a result, the voltage at the collector of switching transistor Q 6 , in starting closer to operating source voltage V 1 , rises to operating source voltage V 1  more quickly when the input signal situation is subsequently reversed to the voltage at node WDP exceeding that at node WDN. This is because switching transistor Q 6  has at its collector inherent structural and other associated, or parasitic, capacitances which require charging or discharging during switching and prevent the voltage at the collector of switching transistor Q 6  from instantaneously rising to operating voltage V 1 . Also, because voltage clamping transistor Q 8  keeps the voltage at the emitter of switching transistor Q 2  (which is equal to the voltage at head node H 2 ) a VBE higher than the voltage at the base of switching transistor Q 2 , switching transistor Q 2  is held off without any possibility that the breakdown voltage of the base-emitter pn junction of switching transistor Q 2  will be exceeded because it is greater than a VBE. 
     Waveform  20  in FIG. 2 shows the voltage waveform at the base of switching transistor Q 1  during both input signal relative magnitude situations. Waveform  22  shows the voltage waveform at the same location in a magnetic recording control circuit without the presence of voltage clamping transistors Q 7  and Q 8 . The start of an input signal situation in which the voltage at node WDP changes from exceeding that at node WDN to the opposite condition begins at 0 ns and ends at 15 ns in FIG.  2 . Waveform  22  shows that without voltage clamping transistors Q 7  and Q 8 , the voltage at the base of switching transistor Q 1  rises to 7.5 V at approximately 6 ns. Waveform  20  shows that with voltage clamping transistors Q 7  and Q 8 , the voltage at the base of switching transistor Q 1  rises to  7 . 5  V at approximately 1 ns. 
     Waveform  24  in FIG. 3 shows the current through inductive coil L H  from head node H 2  to H 1  during the input signal situations depicted in FIG.  2 . Waveform  26  shows the current in the same direction through inductive coil L H  in a magnetic recording control circuit without the presence of voltage clamping transistors Q 7  and Q 8 . The start of an input signal situation in which the voltage at node WDP changes from exceeding that at node WDN to the opposite condition begins at 0 ns and ends at 15 ns in FIG.  3 . Waveform  26  shows that without voltage clamping transistors Q 7  and Q 8 , the current through inductive coil L H  changes direction and drops to −59 mA at approximately 4.0 ns. Waveform  24  shows that with voltage clamping transistors Q 7  and Q 8 , the current through inductive coil L H  changes direction and drops to −59 mA at approximately 3.5 ns. 
     Waveform  28  in FIG. 4 shows the voltage waveform across the emitter-base pn junction of switching transistor Q 1  during the same input signal situations depicted in FIG.  2 . Waveform  30  shows the voltage waveform at the same location in a magnetic recording control circuit without the presence of voltage clamping transistors Q 7  and Q 8 . The start of an input signal situation in which the voltage at node WDP changes from exceeding that at node WDN to the opposite condition begins at 0 ns and ends at 15 ns in FIG.  4 . Waveform  30  shows that without voltage clamping transistors Q 7  and Q 8 , the voltage across the emitter-base pn junction of switching transistor Q 1  rises to over 8 V. Waveform  28  shows that with voltage clamping transistors Q 7  and Q 8 , the voltage across the emitter-base pn junction of switching transistor Q 1  never exceeds 2.5 V. 
     Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.