Abstract:
This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.

Description:
BACKGROUND 
     This application relates to reducing linearity degradation in delay lines and, more particularly, to dynamic element matching of delay line components. 
     A Time to Digital converter (TDC) is used for converting a signal of sporadic pulses into a digital representation of their time indices. In other words, a TDC is used to output the time of arrival for each incoming pulse. Because the magnitudes of the pulses are not usually measured, a TDC is used when the important information is to be found in the timing of events. The performance of the TDC depends on the accuracy of a delay of delay elements in the TDC. In practice, the variations of the delay elements are quite high due to process deviations and temperature variations resulting in system performance degradations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items. 
         FIG. 1  is simplified schematic diagram for a time to digital converter (TDC) that generates a measurement signal (Ym) and a generation signal Ys(t) from an input signal using poly-phases of a reference clock (φ) by interchanging delay elements in accordance with the invention. 
         FIG. 2  is a simplified block diagram of a system for generating poly-phases of a clock (φ) by interchanging the delay elements to provide dynamic element matching for delay lines. 
         FIG. 3  is a simplified schematic diagram of one implementation of a circuit shown in  FIG. 2  for interchanging delay elements using multiplexer blocks to provide dynamic element matching for delay lines. 
         FIG. 4  is a simplified schematic diagram of another implementation of a circuit shown in  FIG. 2  for interchanging delay elements using a permutation matrix to provide dynamic element matching for delay lines. 
         FIG. 5  is a simplified schematic diagram of a further implementation of a circuit shown in  FIG. 2  for interchanging delay elements using ring delay elements to provide dynamic element matching for delay lines. 
         FIG. 6   a  is simplified schematic diagram of an exemplary implementation of a synchronous pulse width modulator with a two-output TDC that includes a poly-phase sampler circuit with dynamic element matching for delay lines. 
         FIG. 6   b  is simplified schematic diagram of an exemplary implementation of an asynchronous pulse width modulator with a one-output TDC that includes a poly-phase sampler circuit with dynamic element matching for delay lines. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein are techniques for providing dynamic element matching (DEM) for delay lines. The order of delay elements (or coupling points) fed the reference clock (φ) are modified dynamically to optimize performance. DEM for delay lines saves circuit layout area because the matching requirements to the building blocks used to construct the circuit can be relaxed. Further using DEM minimizes the error of the overall delay of the delay lines as an error in a single building block can be eliminated. In addition, improved linearity of the delay lines can be achieved. 
     The system includes a filter to receive and filter a target signal, a threshold detector to provide an indication signal when the filtered target signal exceeds a threshold voltage. The system also includes a multiple output delay circuit. The multiple output delay circuit includes a delay line circuit including delay line elements. The delay line circuit receives a clock signal and generates delayed clock signals. An interchange circuit dynamically interchanges the delay line elements to minimize an effect of the delay variations of the delayed line elements on the delayed clock signals. A sample and hold circuit receives and samples the indication signal using the delayed clock signal and generates an output signal. A demodulator demodulates the output signal. 
     In one implementation, a system is shown that includes an analog to digital converter. In the system, a device is included having a delay circuit with a plurality of delay line elements. The delay circuit receives a clock signal. The delay line elements have delay variations and generate delayed clock signals. An interchange circuit is included to dynamically rearrange the delay line elements to minimize an effect of the delay variations on the delayed clock signals. A sample and hold (S/H) circuit receives a target signal and the delayed clock signals. The S/H circuit samples and holds a received target signal using the delayed clock signals. Further the S/H circuit generates an output signal by sampling the target signal with the delayed clock signals. 
     In another described implementation, a method is shown that generates a clock signal and feeds the clock signal through a delay line circuit having delay line elements with delay variations. Delayed clock signals are generated with the delay line elements. The delay line elements are dynamically interchanged to minimize the effect of the delay variations on the delayed clock signals. 
     The techniques described herein may be implemented in a number of ways. One example environment and context is provided below with reference to the included figures and ongoing discussion. 
     Exemplary Systems and Operation 
     An exemplary TDC system  100  is shown in  FIG. 1 . TDC system  100  includes an interchange circuit  101  connected to delay line circuit  102 . Delay circuit  102  is connected via a poly-phase signal and hold (S/H) circuit  104  to a measurement circuit  106  and a generation circuit  108 . A clock φ is fed to the delay line circuit  102 , which generates poly-phases of the clock φ for poly-phase S/H circuit  104 . 
     Delay line circuit  102  includes a number of delay elements (not shown) with a predetermined delay (T). The number (N) of delay elements determines the number of poly-phases supplied to poly-phase S/H circuit  104 . The delay T is chosen such that N times T is equal to the cycle duration of the clock φ. The order of the elements in the delay line circuit  102  is controlled by interchange circuit  101 . Further details of the delay line circuit  102  are explained in connection with  FIG. 2 . 
     Input signal y(t) is supplied to poly-phase S/H circuit  104 . At each poly-phase (designated as φ i ), input signal y(t) is sampled by the poly-phase S/H circuit  104 , so that the signal y(t) effectively is sampled N times higher than the frequency of the clock φ. One signal from the output of poly-phase S/H circuit  104  is fed through measurement circuit  106  to generate a measurement signal Ym. Another signal from the output of poly-phase S/H circuit  104  is fed through generation circuit  108  to generate a delayed input signal Ys(t). 
       FIG. 2  illustrates a simplified block diagram of a system  200  for generating poly-phases of a clock. System  200  includes interchange circuit  202  coupled with delay circuit  204 . Delay circuit  204  includes delay elements  206   a - 206   n  each having a predetermined delay T. Delay circuit  204  receives a clock signal φ, which is fed to delay elements  206   a - 206   n . Delay circuit  204  uses delay elements  206   a - 206   n  to generate one or more poly-phase clock signals (N×φ i ) that are fed to line  208 . In one implementation, delay elements  206   a - 206   n  are connected in series. The number (N) of delay elements  206   a - 206   n  determines the number (N) of poly-phase clock signals. The order of the delay elements  206   a - 206   n  are controlled by interchange circuit  202 . Generally any kind of algorithm for rearranging or interchanging the delay line elements  206   a - 206   n  can be incorporated in interchange circuit  202  and applied to delay circuit  204 . Examples of systems incorporating the dynamic selection of delay elements are shown in  FIGS. 3-5 . 
       FIG. 3  is a simplified schematic diagram of one implementation of a system  300  for interchanging delay elements. System  300  includes multiplexer blocks  302   a - 302   n  that are connected in series to provide dynamic element matching for delay lines. Multiplexer blocks  302   a - 302   n  are substantially identical and thus the details of multiplexer block  302   a  will be described in detail. Although only four blocks  302   a - 302   n  are shown, any number of multiplexer blocks may be used in system  300 . 
     Multiplexer block  302   a  includes parallel connected delay elements  304   a - 310   a  having a common input and have an output connected to different terminals of multiplexer  312   a . Delay elements  306   a - 306   n  each having a predetermined delay T. Delay module  302   a  receives a clock signal φ, which is fed via delay elements  304   a - 310   n  to multiplexer  312   a . Each of the multiplexers  312   a - 312   d  is controlled by an interchange circuit, such as interchange circuit  202  ( FIG. 2 ). Interchange circuit selects which signal on a multiplexer&#39;s input terminal, such as multiplexer  312   a , is to be provided to the multiplexer&#39;s output terminal. The signal on the multiplexer&#39;s output terminal, such as multiplexer  312   a , is fed to an input terminal on an adjacent connected multiplexer block, such as block  302   b . Further the signal on the multiplexer&#39;s output terminal may be fed to a poly-phase signal and hold circuit, such as circuit  104  (See  FIG. 1 ). 
       FIG. 4  is a simplified schematic diagram of another implementation of a system  400  to interchange delay elements using a permutation matrix. System  400  includes N×N switching matrix  402  having input terminals and output terminals (such as output terminal  414 ). Connected to input terminals of switching matrix  402  are the outputs of delay elements  404 - 410 . Delay elements  404 - 410  each having a predetermined delay T. Switching matrix  402  is connected on its output terminals to the input terminals of delay elements  404 - 410 . Switching matrix  402  is fed clock signal φ on one of its input terminals. The signal on output terminal  414  may be fed to a poly-phase signal and hold circuit; such as circuit  104  (See  FIG. 1 ). 
     In one implementation, switching matrix  402  is connected to permutation selector  412  (or an interchange selector) that selects which input of switching matrix  402  is to be connected to which input of delay elements  404 - 410 . Permutation selector  414  also selects which input of switching matrix is to be connected to output terminal  414 . 
       FIG. 5  is a simplified schematic diagram of another implementation of a circuit  500  for interchanging delay elements to provide dynamic element matching for delay lines. Circuit  500  includes ring delay line modules  502 - 508  connected to reference selector  510  and a line that is fed clock signal φ. The ring delay line modules  502 - 508  are connected in series with the other ring delay line modules  502 - 508  and have an input terminal and an output terminal. The output terminal of the ring delay line modules  502 - 508  are connected in series to an input terminal of the next of the ring delay line modules. The last ring delay line module  508  has an output terminal connected to the input terminal of the first ring delay line module  502 . Although four ring delay line modules  502 - 508  are shown, the embodiment is not limited to four modules, and any number of ring delay line modules may be used. 
     Ring delay line modules  502 - 508  are identical, thus only ring delay line module  502  will be described. Ring delay line module  502  includes switch  502   a , with an output terminal connected to a delay element  502   b . Delay element  502   b  includes input terminals  502   c ,  502   d  and  502   e . Input terminal  502   c  is connected to the output terminal of a delay element in an adjacent delay line module, such as module  508 . Input terminal  502   d  is connected to a line that is fed the clock signal φ. Input terminal  502   e  is connected to reference selector  510 . Delay element  502   b  has a delay time of T. In one implementation, the time T has a predetermined value such that the number of ring delay line modules (N) times T is less than the time of a period of clock signal φ. 
     Reference selector  510  is connected to delay line modules  502 - 508 . Reference selector  510  selects whether line modules  502 - 508  are fed clock signal φ via a delay line element to the line module&#39;s output terminal or fed the output signal from an adjacent line module to the line module&#39;s output terminal. The reference selector selects the right module based on the history and ensures that all the delay elements are used equally often on average. In other words, the mismatch is set to zero on average. 
       FIG. 6   a  is simplified schematic diagram of an exemplary implementation of a synchronous pulse width modulator  600   a . Pulse width modulator  600   a  includes an input terminal  602   a  connected through adder circuit  604   a  to filter  606   a . The output terminal of filter is connected to detector  608   a . An output terminal of detector  608   a  is connected to TDC  610   a  (also referred to as a multiple output delay circuit). One exemplary TDC is shown in  FIG. 1 , e.g. TDC  100 , with two-outputs that include a poly-phase sampler circuit with dynamic element matching for delay lines. TDC  610   a  has a measurement output signal Ym that is fed via demodulator  612   a  to output terminal  614   a  and has an output signal Ys(t) that is fed to a negative terminal of adder  604   a.    
     In operation of synchronous pulse width modulator  600   a , a signal to be pulse width modulated is received on terminal  602   a . The signal is combined using adder circuit  604   a  with the inverse of the output signal Ys(t) from TDC  610   a . The combined signal is fed to filter  606   a . Filter  606   a  then filters the combined signal and then feeds the filtered combined signal to detector  608   a . Detector  608   a  generates an indication signal for TDC  610   a  when the level of the filtered combined signal exceeds a predetermined voltage level. TDC  610   a  generates a delayed indication signal Ys(t) for adder circuit  608   a . TDC  610   a  also provides a measurement signal Ym that is demodulated by demodulator  612   a  and fed as a pulse width modulated signal to output terminal  614   a . The delay elements in TDC  610   a  are arranged using the techniques previously described. 
       FIG. 6   b  is simplified schematic diagram of an exemplary implementation of an asynchronous pulse width modulator  600   b . Pulse width modulator  600   b  includes an input terminal  602   b  connected through adder circuit  604   b  to filter  606   b . The output terminal of filter  608   b  is connected to detector  608   b . An output terminal of detector  608   b  is connected to TDC  610   b  and a negative terminal of adder circuit  604   b . One exemplary TDC is shown in  FIG. 1 , e.g. TDC  100 , and includes a poly-phase sampler circuit with dynamic element matching for delay lines. TDC  610   b  has a measurement output terminal that is coupled via demodulator  612   b  to output terminal  614   b.    
     In operation of asynchronous pulse width modulator  600   b , a signal to be pulse width modulated is received on terminal  602   b . The received signal is combined with the inverse of the output signal Y(t) from detector  608   b  and fed to filter  606   b . Filter  606   b  then filters the combined signal and then feeds the filtered combined signal to detector  608   b . Detector  608   b  generates an indication signal for TDC  610   b  when the level of the combined filtered signal from filter  606   b  exceeds a predetermined voltage level. TDC  610   b  provides a measurement signal Ym that is demodulated by demodulator  612   b  and fed as a pulse width modulated signal to output terminal  614   b . The delay elements in TDC  610   b  are arranged using the techniques previously described. 
     Conclusion 
     Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as preferred forms of implementing the claims.