Abstract:
Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Description:
FIELD OF THE INVENTION  
       [0001]     Embodiments of this invention relate to improving the skew in a byte lane in a memory module.  
       BACKGROUND  
       [0002]     Memory modules (e.g., Single In-Line Memory Modules (SIMMs)), Dual In-Line Memory Modules (DIMMs), and Small Outline DIMMs (SODIMMs)) are common in the computer industry, and generally comprise a printed circuit board (PCB) having a number of memory chips thereon. Such memory chips are usually DRAM memory chips, and more typically synchronous DRAMs (e.g., DDRx DRAMs). By incorporating several memory chips on a single PCB, the modules can hold large amounts of data, and thus are useful in computing applications. Generally, data is retrieved from the module by a call from some master device that needs access to the data, e.g., a microprocessor, which typically calls for eight bits of data (i.e., a “byte”) at one time.  
         [0003]     A memory module  10  (shown in isolation in  FIG. 1A ) typically mounts to a system (such as mother board  12 ) by way of a connector  18 , as shown in cross-section in  FIG. 1B . In this particular example, the module  10  is a SODIMM module. SODIMM modules are useful in applications such as notebook computers because of their low profiles. This low profile is facilitated by the use of a 90-degree connector  18 , which allows the module  10  to be positioned parallel to the mother board  12  when mounted in the connector  18 .  
         [0004]     The particular memory module  10  illustrated has memory chips  16  on the top ( 16   t ) and bottom ( 16   b ) of a PCB  14 . As one skilled in the art will understand, the PCB  14  further contains contacts  20  at one edge of the PCB  14 . These contacts  20  connect to pins on the memory chips  16   t  and  16   b  (not shown) via circuit traces in the PCB  14  (not shown). As illustrated, the contacts  20 , like the memory chips, appear on the top ( 20   t ) and bottom ( 20   b ) of the PCB  14 . Typically, such contacts are tinned or gold plated to ensure good electrical connection with the connector  18  as discussed further below.  
         [0005]     When the memory module  10  is positioned within the connector  18  (e.g., by press fit, by the use of latches, or by other means in the art), as shown in  FIG. 1B , the contacts  20  further connect to conductors  22  molded inside of the plastic connector body  18 . These conductors  22  are in turn connected to traces on the mother board  12  (not shown) and ultimately to other electrical components on the mother board  12 , such as a microprocessor (not shown). Because the conductors  22  communicate with both the top  20   t  and bottom  20   b  contacts, the conductors  22  within the connector  18  body will also be split into top ( 22   t ) and bottom ( 22   b ) conductors.  
         [0006]     When the memory module  10  is so coupled to the mother board  12 , it will be noticed that the electrical pathway between the contacts  20  and the motherboard  12  differs depending on whether top or bottom contacts are considered. This is because, by necessity, conductors  22   t  are longer than conductors  22   b , e.g., by approximately 10 millimeters. As a result, the signals passing from the chips  16  through the top contacts  20   t  and top conductors  22   t  will arrive at the mother board  12  slightly delayed with respect to similar signals passing through the bottom contacts  20   b  and bottom conductors  22   b.    
         [0007]     This difference in length has a small, but potentially critical, effect on the timing of the signals that pass through the conductors  22 . For example, suppose a microprocessor on the mother board  12  calls to the memory module to provide a byte of data (from outputs DQ 0 -DQ 7 ). These signals (e.g., in a DDRx DRAM module) appear on opposite sides of the memory module  10 , as shown in  FIG. 1C . Specifically, the first four bits, DQ 0 -DQ 3 , or “nibble” of data corresponding to pins  5 ,  7 ,  15  and  17  on the module, are output on the bottom contacts  20   b  of the module. The other nibble, DQ 4 -DQ 7 , corresponding to pins  4 ,  6 ,  16 , and  18  of the module  10 , are output on the top contacts  20   t  of the module. (Although a typical DDRx DRAM module would have many dozens of pins, only a few are shown in  FIG. 1C ).  
         [0008]     However, data from these module outputs will typically be called for at the same time, i.e., on a byte basis. When the microprocessor makes such a call, the length difference inside the connector will cause the data corresponding to the nibble DQ 0 -DQ 3  to arrive at the mother board  12  slightly before nibble DQ 4 -DQ 7 , e.g., perhaps on the order of 50 picoseconds or so. That is to say, a 50 ps “skew” is introduced in the byte lane. While this delay is relatively small, it can represent a significant portion of the data valid window on a memory module containing high speed memory chips (e.g., 20% of the data valid window on a DDR3 DRAM module).  
         [0009]     To put this problem into further perspective,  FIG. 2  shows the timing of the signals comprising the byte lane as they reach the mother board  12 . The data is accompanied by a data valid signal, DQS, which is also sent by the module  10  when the byte is called for. Essentially, DQS represents a signal which indicates to the calling entity, e.g., the microprocessor, when the data called for is valid. The DQS signal, as to this particular byte, is also provided on the top contact  20   t  of the module  10 . As is shown, the DQS signal arrives at the motherboard when nibble DQ 4 -DQ 7  also arrives, as they are all provided through the top contacts  20   t  of the module and the top conductors  22   t  of the connector  18 . However, nibble DQ 0 -DQ 3 , outputs to the bottom contacts  20   b  of the module  10 , and thus arrives earlier by virtue of its shorter path through conductors  22   b  in the connector  18 . The result of this skew is that the DQS signal doesn&#39;t exactly accurately indicate to the microprocessor when valid data is necessarily present for the entirety of the byte lane.  
         [0010]     This problem has been rectified in the prior art by adjusting the lengths of the electrical traces on the mother board. Specifically, the length of the traces between the connector  18  and, for example, the microprocessor on the mother board  12  were lengthened for the “earlier” nibble, DQ 0 -DQ 3  in the present example. In other words, the mother board traces for the earlier nibble would be longer than those for the later nibble, DQ 4 -DQ 7 . In so doing, and assuming the increase trace length compensates for the timing differential caused by the connector conductors  22   t  and  22   b , the signals will be provided to the microprocessor at the same time, overcoming this problem.  
         [0011]     However, this prior art solution is not optimal. First, it requires the mother board design to account for delays caused by the connector  18  and to specifically engineer the trace lengths. This may be inconvenient. Moreover, an otherwise undesired diversion in the trace length (such as a serpentine) is required, and may not be possible if space does not permit on the mother board.  
         [0012]     Second, such lengthening of trace lengths essentially tailors the mother board for a particular connector, rendering the motherboard non-optimal if other types of connectors are to be used. For example, consider the O-degree connector  18  of  FIG. 3 . This connectors orients the module  10  perpendicularly to the mother board  12  when mounted, as would be typical in a desktop computer. Moreover, given this configuration, it can be seen that the conductors  22  inside of the connector  18  are of the same length. In other words, the O-degree connector  18  of  FIG. 3  does not cause the same skew problem between nibbles in the byte lane as does the 90-degree connector  18  of  FIG. 1B . Therefore, if the trace lengths on the mother board  12  are optimized for a particular type of connector, the use of other connectors would be non-optimal. Hence, adjustment of trace lengths does not make for a universal solution.  
       SUMMARY  
       [0013]     Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. One such external factor can comprise the use of a connector with internal conductors of different lengths that adds skew to the integrated circuit&#39;s or module&#39;s byte lane, which otherwise is called and desired to be provided synchronously in parallel to its destination (e.g., a mother board or microprocessor). To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or the integrated circuits on the module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]     Embodiments of the inventive aspects of this disclosure will be best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings, in which:  
         [0015]      FIG. 1A  illustrates a perspective view of a prior art memory module.  
         [0016]      FIG. 1B  illustrates a cross-section of the module of  FIG. 1A  mounted to a mother board by a 90-degree connector.  
         [0017]      FIG. 1C  illustrates a table showing the pin outs on the module of  FIG. 1A  for exemplary bits in a byte lane.  
         [0018]      FIG. 2  illustrates timing signals for bits in a byte lane to show the problem of skew within the byte lane, and resulting skew with a data valid signal.  
         [0019]      FIG. 3  illustrates the module of  FIG. 1A  mounted to a mother board by a O-degree connector.  
         [0020]      FIGS. 4A and 4B  illustrate embodiment in delay circuits are selectively provided in the data output paths to provide a compensating skew in a byte lane of data.  
         [0021]      FIG. 4C  illustrates an embodiment similar to  FIG. 4A  in which programmable delay circuits are used.  
         [0022]      FIG. 5A  illustrates a delay circuit useable in the context of  FIGS. 4A and 4B .  
         [0023]      FIGS. 5B-5E  illustrates programmable delay circuits useable in the context of  FIG. 4C . 
     
    
     DETAILED DESCRIPTION  
       [0024]     The problem of skew of data within the byte lane of a memory module is solved by introducing an on-chip delay to certain output signals within the memory chips themselves. This on-chip delay is designed, in one embodiment, to compensate for skew that would otherwise be provided the connector (e.g., a 90-degree connector) used to connect the module to the mother board.  
         [0025]     However, before the specific solution to this problem is addressed, it should be realized that the on-chip delay technique disclosed herein can be used in broader manners and different contexts. For example, the on-chip delay technique can used to compensate for skews appearing on any parallel stream of data, and is not limited to addressing skew within a byte lane per se. The on-chip delay technique can also be used to compensate for skews related to the use of external factors other than connectors, including skews introduced by other devices external to the memory chips. The technique can also be used with respect to skews internal to the chips themselves. While particular useful in the context of memory chips, and more specifically memory modules, the techniques are adaptable to other technologies as well, such as microprocessor and multi-chip modules more generally. The technique has further pertinence to individual integrated circuits not comprising portions of a module. In short, the on-chip delay technique provides a broad solution to many different potential problems of skew. Moreover, such on-chip delays can be made programmable, as explained further below.  
         [0026]     In one embodiment, assume the specific problem of byte lane skew in a memory module introduced by the use of a 90-degree connector  18 , such as shown in  FIG. 1B . The solution to this specific problem does not require a programmable on-chip delay, as the delay associated with this particular connector  18  would be constant. Accordingly, a non-programmable delay can be used, with the goal of providing an approximately 50 ps delay to those nibbles in the byte lane (called the “earlier nibble”) which would otherwise arrive at the mother board before the other nibble (the “later nibble”).  
         [0027]     This is illustrated in one embodiment in  FIG. 4A . Shown are eight memory chips  50   0 - 50   7  together representing a byte lane of data (DQ 0 -DQ 7 ) from the memory module PCB on which the chips  50   x  are mounted (not shown for clarity). Depicted for each chip  50   x  is the data out path, which comprises an internal data out signal  52 , a standard output buffer  56 , a bond pad  58 , and a bond wire that ultimately connects to the lead frame of the package in which the chips  50   x  are positioned (not shown), and ultimately to the various contacts  20  (FIGS.  1 A-B) on the module  10 .  
         [0028]     As depicted, it is assumed that each of the eight DQ signals on the module  10  is derived from one bit of each of the eight memory chips  50   x . That is to say, it is assume that x1 DRAMs are used. Of course, this need not be the case, and the various data paths comprising the module&#39;s byte lane may be integrated on one or more memory chips. For example, each of the nibbles may be provided by four separate outputs on two different memory chips  55   x  (shown in dotted lines). More typically, in current-day DDR DRAMs modules, the eight data paths comprising a particular byte lane are all intergraded on one DRAM memory chip  57 , as shown in  FIG. 4B . In other words, typically ×8 or ×16 DRAMs are used, capable of outputting a byte or word of data in parallel. (Moreover,  FIG. 4B  illustrates the utility of the disclosed technique even when a call for data is made to a single integrated circuit).  
         [0029]     In any event, as to the earlier nibble in the byte lane (DQ 0 -DQ 3  in the example discussed earlier), a delay circuit  54  has been introduced between the data out signal  52  and the output buffer  56  so as to delay the signals on those data paths by an appropriate time (i.e., t=50 ps). The delay circuit  54  can be placed anywhere along the data path, including earlier “up stream” in the chip. Note that this delay circuit  54  does not appear in the later nibble in  FIG. 4A  or  4 B. Accordingly, when the microprocessor for example calls for data from the byte lane, the earlier nibble will be delayed by the delay circuits  54  by 50 ps, just as the later nibble will be delayed by virtue of the additional length of the top conductors  22   t  ( FIG. 1B ) in the connector. The result is that the byte will arrive at the mother board with no or reduced skew. This allows the data valid window to be set around the arrival of data at the microprocessor with greater accuracy and buffer, without the need to lengthen any circuit traces on the mother board. Although not shown, the data valid signal, DQS, may also be delayed if necessary, more specifically if it were provided on the bottom side of the module, although this is unnecessary in the example discussed earlier (see  FIG. 2 ).  
         [0030]      FIG. 5A  shows a simple way in which the on-chip delay circuit  54  can be fabricated. As shown, delay is introduced simply by providing a series of inverters  62 . Each inverter  62  provides some amount of delay to the internal data out signal  52 . Typically, this delay for a CMOS inverter is on the order of 10-20 ps for current CMOS technologies, and can be easily scaled by adjusting the gate lengths and widths of the NMOS and PMOS transistors which make up the inverter. (More specifically, and as one skilled in the art understands, the delay time of a CMOS inverter can be approximated by Δt=C*ΔVdd/I, where C is the capacitance of the load, Vdd is the power supply voltage, and I is the drive current. I can be adjusted by adjusting the width or length of the transistor). Therefore, assuming the transistors in the inverters  62  are properly scaled, a delay of approximately 15 ps (for example) can be achieved for each, with four in series providing a delay of approximately 60 ps, acceptably close to the 50 ps skew introduced by the 90-degree connector  18  ( FIG. 1B ). (An even number of inverters would be preferred to preserve the polarity of the internal data out signal  52 ).  
         [0031]     Even further preferable to the delay circuit  54  of  FIG. 5A  are delay circuits that are programmable. As applied to the byte lane data skew problem discussed above, programmability is desirable to provide greater flexibility in the type of connectors  18  ( FIG. 1B ) with which the modules can be used. As noted in the Background section, a given module  10  can be used with varying types of connectors  18 , such as 90-degree ( FIG. 1B ) or 0-degree connectors ( FIG. 3 ), and thus a fixed delay circuit  54  would not be optimal were it desired to use the module with either of these types of connector.  
         [0032]      FIG. 4C  illustrates the use of programmable delay circuits  54 . In this example, and compared to  FIG. 4A , it will be seen that each output comprising a bit in the byte lane has a delay circuit  54  in its data out path. However, no delay is set by the delay circuits in the later nibble (t=0), whereas the delay circuits  54  in the earlier nibble are once again set to approximately t—50 ps. Thus, the effect is the same as that shown in  FIGS. 4A and 4B , except that now that chips  50   x ,  55   x , or  57  can be made uniformly, and then later programmed to address the unique problems of skew present in the byte lane.  
         [0033]      FIG. 5B  illustrates a programmable delay circuit  54 . Again, inverters  62  are used as the basic delay element, with antifuses (AF)  64  spanning every two inverters  62 . In their unprogrammed state, the antifuses  64  act as open circuits, and hence a delay of eight inverter stages (e.g., 120 ps) would be introduced if none of the antifuses  64  are programmed; six stages if one of the antifuses are programmed; four stages if two of the antifuses are programmed; two stages if three of the antifuses are programmed; and no delay if all of the antifuses are programmed.  FIG. 5C  achieves this same programming ability, with the need to only program one antifuse to effect a delay between zero to eight inverter stages. As antifuses and methods for programming them are well known in the semiconductor art, the circuitry used to do so is not shown.  
         [0034]     Fuses could also be used, as illustrated in  FIGS. 5D and 5E . In their unprogrammed state, the fuses  66  act as short circuits, and hence no delay would be introduced if none of the fuses  66  are programmed in  FIG. 5D ; two inverter stages of delay if one of the fuses are programmed; four stages if two of the fuses are programmed; six stages if three of the fuses are programmed; and eight stages if all of the fuses are programmed.  FIG. 5E  achieves this same programming ability, with the need to only program one fuse to effect a delay between zero to eight inverter stages. As fuses and methods for programming them are well known in the semiconductor art, the circuitry used to do so is not shown. The fuses  66  may be either programmable by signal (i.e., by the application of a voltage across the fuse), or by light (e.g., by laser ablation).  
         [0035]     Such one-time programmable approaches are destructive. Once programmed, the chips  50  (and the modules in which they reside), are permanently tailored for a particular operating environment and/or connector. Therefore, and even further preferable approach to the delay circuit  54  are many-times programmable circuits whose delay can be readily changed. This would allow a module, for example, to be freely tailored for use in any operating environment at any time, even if previously programmed for a certain operating environment. One simple way of doing do, not illustrated in the Figures, would be to substitute an Erasable Programmable Read Only Memory (EPROM) cell for either the antifuses  64  of fuses  66  of  FIGS. 5B-5E . Such a cell could be UV erasable using radiation or electrically erasable via application of an erase voltage. Again, such techniques are well known in the art.  
         [0036]     Programming of the delay circuits on the memory chips can take place using an on chip mode register. As one skilled in the art understands, a mode register contains various settings used to tailor the operation of the chip. The mode register can be programmed using special test modes, usually by activating otherwise standard control signals on the chips or the module in unique sequences. Using such a standard technique, the delay value for each of the delay circuit can be easily programmed. Such programming could occur at the chip level (i.e., before the chips are mounted to a PCB), or at the board level (i.e., after mounting to the module PCB).  
         [0037]     Of course, the use of serially-connected inverters  62  is only one way of creating a delayed signal on of earlier nibble. One skilled in the art will recognize that many different types of fixed, one-time programmable, or freely programmable delay circuits can be used to achieve the goal of delaying the internal data out signal  52 . For example, other logic gates can be used, varying capacitances can be provided to achieve a desired granularity in the delay on the internal data out signal, etc.  
         [0038]     As used herein, a “mother board” need be only another board for communicating with the memory module. While such a board would typically contain a system microprocessor were the memory module to be used in a traditional computer configuration, this is not strictly necessary. Any board capable of calling the memory module could comprise the mother board, regardless of its configuration and function.  
         [0039]     It should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent.