Abstract:
The disclosed embodiment relates to a method of controlling a system including at least one inverter with six switches, which is linked to a battery, and supervised by a processor. The method implements a vector modulation, so that it is able to prevent the current linking the battery from passing through zero amperes by means of appropriate control logic. The disclosed embodiment also relates to device for controlling an electronic component.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is the National Stage of International Application No. PCT/FR2015/052708, having an International Filing Date of 8 Oct. 2015, which designated the United States of America, and which International application was published under PCT Article 21(2) as WO Publication No. 2016/055742 A1, and which claims priority from and the benefit of French Application No. 1459674, filed on 9 Oct. 2014, the disclosures of which are incorporated herein by reference in their entireties. 
     
    
     BACKGROUND 
     1. Field 
       [0002]    The presently disclosed embodiment pertains to the field of power electronics. 
         [0003]    The presently disclosed embodiment pertains more particularly to a method of controlling a three-phase inverter implementing a vector modulation technique. 
       2. Brief Description of Related Developments 
       [0004]    The scientific publication “ Optimal Common - Mode Voltage Reduction PWM Technique for Inverter Control With Consideration of the Dead - Time Effects—Part I: Basic Development ” (Yen-Shin Lai and Fu-San Shyu— IEEE Transactions on Industry Applications. Vol.  40  No.  6  November/December  2004) is known in the prior art. This scientific publication relates to the PWM (“Pulse Width Modulation”) technique, and more particularly to reducing the common-mode voltage. 
         [0005]    U.S. Patent Publication No. US 2014/0070736 (“Bayerische Motoren Werke Aktiengesellschaft”—BMW AG), which describes a power electronics apparatus and a method of piloting for an electrical machine and for the storage of electrical energy is also known in the prior art. This U.S. patent Publication describes a power electronics structure comprising an inverter to which an electrical machine can be connected, and at least one half-bridge to which two electrical energy storage devices can be connected. One of the two electrical energy storage devices supplies at least in a temporary manner the electrical machine and the other of the two electrical energy storage devices charges at least in a temporary manner another electrical energy storage device from among at least the two electrical energy storage devices by means of the electrical machine and of one of the half-bridges. Accordingly, a method of control for switching the power electronics operates according to the principle of spatial vector modulation. 
         [0006]    SVM (“Space Vector Modulation”) type modulation is known in the prior art. It is a method implemented in a digital manner to control three-phase inverters. This method is implemented in electric vehicles in particular. Modulation of SVM type uses vectors which correspond to individual switching configurations to generate a reference voltage.  FIG. 1  illustrates a three-phase inverter structure. In a binary manner, each vector results from a specific combination. For a three-phase inverter, such as represented in  FIG. 1 , there are eight (2 3 ) possible combinations. Table 1 hereinbelow indicates each vector and the corresponding voltage for each phase on the basis of a switching function which indicates “0” for open (“OFF”) and “1” for closed (“ON”). 
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 Vector corresponding to the switching logic 
               
             
          
           
               
                   
                   
                   
                   
                   
                   
                 Index 
               
               
                   
                   
                   
                   
                   
                   
                 number 
               
               
                   
                   
                   
                   
                   
                   
                 of 
               
               
                 Gate “a” 
                 V ao   
                 Gate “b” 
                 V bo   
                 Gate “c” 
                 V co   
                 vector 
               
               
                   
               
               
                 0 
                 −V dc /2 
                 0 
                 −V dc /2 
                 0 
                 −V dc /2 
                 0 
               
               
                 0 
                 −V dc /2 
                 0 
                 −V dc /2 
                 1 
                 V dc /2 
                 5 
               
               
                 0 
                 −V dc /2 
                 1 
                 V dc /2 
                 0 
                 −V dc /2 
                 3 
               
               
                 0 
                 −V dc /2 
                 1 
                 V dc /2 
                 1 
                 V dc /2 
                 4 
               
               
                 1 
                 V dc /2 
                 0 
                 −V dc /2 
                 0 
                 −V dc /2 
                 1 
               
               
                 1 
                 V dc /2 
                 0 
                 −V dc /2 
                 1 
                 V dc /2 
                 6 
               
               
                 1 
                 V dc /2 
                 1 
                 V dc /2 
                 0 
                 −V dc /2 
                 2 
               
               
                 1 
                 V dc /2 
                 1 
                 V dc /2 
                 1 
                 V dc /2 
                 7 
               
               
                   
               
             
          
         
       
     
         [0007]    The SVM method, based as it is on mathematical transformations, is appropriate for programming on processors of “Digital Micro Processors” type. 
         [0008]    In traditional SVM methods, the common-mode voltage (CMV) can take the following values: +/−V dc /2 or +/−V dc /6 as a function of the vectors used. During the switching times, the common-mode voltage can vary by +/−V dc /3. The common-mode current or CMC from which the leakage current originates is proportional to the variations of the CMV levels. 
         [0009]    Methods for reducing the common-mode voltage have recently been proposed. 
       SUMMARY 
       [0010]    The presently disclosed embodiment intends to remedy the drawbacks of the prior art by proposing a method of control offering better performance than the methods of the prior art, in particular within the framework of use in electric vehicles. 
         [0011]    For this purpose, the presently disclosed embodiment relates, in its most general acceptation, to a method of controlling a system comprising at least one six-switch inverter, linked to a battery, and piloted by a processor, said method implementing a vector modulation, characterized in that it is able to prevent the current absorbed by the battery from passing through zero Amperes by means of appropriate control logic. 
         [0012]    The method according to the presently disclosed embodiment makes it possible to obtain the following results: 
         [0013]    Increase the efficiency; 
         [0014]    Reduce the common-mode voltage and current; 
         [0015]    Reduce the impact in respect of electromagnetic compatibility; 
         [0016]    Limit the undulations in current taken at the batteries; and 
         [0017]    Reduce the dimensions of the filter of the DC bus. 
         [0018]    The method according to the presently disclosed embodiment makes it possible to limit the abrupt and periodic loadings of the DC bus (battery in particular) and to reduce switching losses. 
         [0019]    By virtue of the presently disclosed embodiment, the lifetime of the batteries, of the power components and of the motorization is increased. The presently disclosed embodiment makes it possible to increase the lifetime of the system, with enhanced adaptability. 
         [0020]    Advantageously, the method according to the presently disclosed embodiment does not require the addition of further components. This makes it possible not to increase production costs. 
         [0021]    According to one aspect, said method comprises a step of modifying a circular vector into another form which, as a function of the radius of a reference vector, can be transferred to the surface of a hexagon. 
         [0022]    According to one aspect, said method comprises a step of calculating the resulting zero time, and a step of allocating this time to the neighboring vectors, by allocating k percent to the first vector in each sector and (1−k) percent to the second vector, k lying between 0 and 1. 
         [0023]    The presently disclosed embodiment also pertains to a device for controlling a system comprising at least one inverter composed of six switches, linked to a battery, and controlled by a processor, said device comprising means for implementing a vector modulation, characterized in that it comprises means for preventing the current absorbed by the battery from passing through zero Amperes by means of appropriate control logic. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0024]    The disclosed embodiment will be better understood with the aid of the description, given hereinafter purely by way of explanation, of an aspect of the disclosed embodiment, with reference to the Figures in which: 
           [0025]      FIG. 1  illustrates a three-phase inverter structure with fictitious or non-fictitious capacitive midpoint O; 
           [0026]      FIGS. 2A and 2B  represent a simulation result for a reference vector, within the framework of the presently disclosed embodiment ( FIG. 2A  with a radius of 0.5 P.u and  FIG. 2B  with a radius of 0.8 P.u.); 
           [0027]      FIG. 3  illustrates the switching logic within the framework of the method according to the presently disclosed embodiment; 
           [0028]      FIG. 4  represents the amplitude of the fundamental of the output voltage divided by the mean voltage of the DC bus as a function of the radius of the reference circle; 
           [0029]      FIG. 5  illustrates the DC mode current within the framework of the method according to the presently disclosed embodiment, by injecting an active power of 1 pu; 
           [0030]      FIGS. 6A and 6B  represent the AC mode current for a traditional SVM method of control ( FIG. 6A ) and for a method according to the presently disclosed embodiment ( FIG. 6B ) by injecting an active power only; 
           [0031]      FIGS. 7A and 7B  illustrate the operating zone with k=0.33 ( FIG. 7A ) and k=0.66 ( FIG. 7B ); and 
           [0032]      FIG. 8  illustrates results obtained relating to the temperature of the inverter. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    The previous SVM methods are characterized by the following relation. To construct the reference vector, the third term (t z V 0 ) must be zero. 
         [0000]    
       
      
       T 
       s 
       V 
       ref 
       =t 
       i 
       V 
       i 
       +t 
       i+1 
       V 
       i+1 
       +t 
       z 
       V 
       0  
      
     
         [0000]    
       
      
       T 
       s 
       =t 
       i 
       +t 
       i+1 
       +t 
       z  
      
     
         [0034]    In the method according to the presently disclosed embodiment, the zero time is avoided by allocating in an equal manner a calculated zero time to two near active-vectors as follows. 
         [0000]    
       
         
           
             
               t 
               
                 i 
                  
                 
                   ( 
                   new 
                   ) 
                 
               
             
             = 
             
               ( 
               
                 
                   t 
                   i 
                 
                 + 
                 
                   
                     t 
                     z 
                   
                   / 
                   2 
                 
               
               ) 
             
           
         
       
       
         
           
             
               t 
               
                 i 
                 + 
                 
                   1 
                    
                   
                     ( 
                     new 
                     ) 
                   
                 
               
             
             = 
             
               ( 
               
                 
                   t 
                   
                     i 
                     + 
                     1 
                   
                 
                 + 
                 
                   
                     t 
                     z 
                   
                   / 
                   2 
                 
               
               ) 
             
           
         
       
       
         
           
             
               
                 T 
                 s 
               
                
               
                 V 
                 
                   ref 
                    
                   
                     ( 
                     new 
                     ) 
                   
                 
               
             
             = 
             
               
                 
                   ( 
                   
                     
                       t 
                       i 
                     
                     + 
                     
                       
                         t 
                         z 
                       
                       / 
                       2 
                     
                   
                   ) 
                 
                  
                 
                   V 
                   i 
                 
               
               + 
               
                 
                   ( 
                   
                     
                       t 
                       
                         i 
                         + 
                         1 
                       
                     
                     + 
                     
                       
                         t 
                         z 
                       
                       / 
                       2 
                     
                   
                   ) 
                 
                  
                 
                   V 
                   
                     i 
                     + 
                     1 
                   
                 
               
             
           
         
       
       
         
           
             
               
                 V 
                 
                   ref 
                    
                   
                     ( 
                     new 
                     ) 
                   
                 
               
               = 
               
                 
                   
                     
                       ( 
                       
                         
                           α 
                           i 
                         
                         + 
                         
                           
                             α 
                             z 
                           
                           / 
                           2 
                         
                       
                       ) 
                     
                      
                     
                       V 
                       i 
                     
                   
                   + 
                   
                     
                       ( 
                       
                         
                           α 
                           
                             i 
                             + 
                             1 
                           
                         
                         + 
                         
                           
                             α 
                             z 
                           
                           / 
                           2 
                         
                       
                       ) 
                     
                      
                     
                       V 
                       
                         i 
                         + 
                         1 
                       
                     
                      
                     
                         
                     
                      
                     with 
                      
                     
                         
                     
                      
                     
                       α 
                       i 
                     
                   
                 
                 = 
                 
                   
                     
                       t 
                       i 
                     
                     
                       T 
                       S 
                     
                   
                   = 
                   
                     
                       
                          
                         
                           V 
                           ref 
                         
                          
                       
                       
                          
                         
                           V 
                           i 
                         
                          
                       
                     
                      
                     
                       
                         sin 
                          
                         
                           ( 
                           
                             
                               π 
                               3 
                             
                             - 
                             θ 
                           
                           ) 
                         
                       
                       
                         sin 
                          
                         
                           ( 
                           
                             π 
                             3 
                           
                           ) 
                         
                       
                     
                   
                 
               
             
             , 
             
               
 
             
              
             
               
                 α 
                 
                   i 
                   + 
                   1 
                 
               
               = 
               
                 
                   
                     t 
                     
                       i 
                       + 
                       1 
                     
                   
                   
                     T 
                     S 
                   
                 
                 = 
                 
                   
                     
                       
                          
                         
                           V 
                           ref 
                         
                          
                       
                       
                          
                         
                           V 
                           
                             i 
                             + 
                             1 
                           
                         
                          
                       
                     
                      
                     
                       
                         sin 
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         sin 
                          
                         
                           ( 
                           
                             π 
                             3 
                           
                           ) 
                         
                       
                     
                      
                     
                         
                     
                      
                     and 
                      
                     
                         
                     
                      
                     
                       α 
                       z 
                     
                   
                   = 
                   
                     1 
                     - 
                     
                       α 
                       i 
                     
                     - 
                     
                       α 
                       
                         i 
                         + 
                         1 
                       
                     
                   
                 
               
             
           
         
       
       
         
           
             
               T 
               s 
             
              
             
                 
             
              
             is 
              
             
                 
             
              
             the 
              
             
                 
             
              
             sampling 
              
             
                 
             
              
             
               period 
               . 
             
           
         
       
     
         [0035]    The last equation can be reformulated as the following two equations. Thus, a new reference vector is created. This new reference is calculated as the sum of two near vectors by subtracting V i+1  from V i  which is multiplied by (α i −α i+1 ). 
         [0000]    
       
         
           
             
               V 
               
                 ref 
                  
                 
                   ( 
                   new 
                   ) 
                 
               
             
             = 
             
               
                 
                   1 
                   2 
                 
                  
                 
                   ( 
                   
                     1 
                     + 
                     
                       α 
                       i 
                     
                     - 
                     
                       α 
                       
                         i 
                         + 
                         1 
                       
                     
                   
                   ) 
                 
                  
                 
                   V 
                   i 
                 
               
               + 
               
                 
                   1 
                   2 
                 
                  
                 
                   ( 
                   
                     1 
                     - 
                     
                       α 
                       i 
                     
                     + 
                     
                       α 
                       
                         i 
                         + 
                         1 
                       
                     
                   
                   ) 
                 
                  
                 
                   V 
                   
                     i 
                     + 
                     1 
                   
                 
               
             
           
         
       
       
         
           
             
               V 
               
                 ref 
                  
                 
                   ( 
                   new 
                   ) 
                 
               
             
             = 
             
               
                 
                   
                     V 
                     i 
                   
                   + 
                   
                     V 
                     
                       i 
                       + 
                       1 
                     
                   
                 
                 2 
               
               + 
               
                 
                   ( 
                   
                     
                       α 
                       i 
                     
                     - 
                     
                       α 
                       
                         i 
                         + 
                         1 
                       
                     
                   
                   ) 
                 
                  
                 
                   
                     
                       V 
                       i 
                     
                     - 
                     
                       V 
                       
                         i 
                         + 
                         1 
                       
                     
                   
                   2 
                 
               
             
           
         
       
       
         
           
             C 
             = 
             
               
                 α 
                 i 
               
               - 
               
                 
                   α 
                   
                     i 
                     + 
                     1 
                   
                 
                  
                 
                     
                 
                  
                 designates 
                  
                 
                     
                 
                  
                 the 
                  
                 
                     
                 
                  
                 coefficient 
                  
                 
                     
                 
                  
                 indicated 
                  
                 
                     
                 
                  
                 in 
                  
                 
                     
                 
                  
                 
                   FIG 
                   . 
                   
                       
                   
                    
                   2 
                 
                  
                 
                   A 
                    
                   
                       
                   
                   . 
                 
               
             
           
         
       
     
         [0036]    Thus, the method according to the presently disclosed embodiment has changed the circular vector into another form which, as a function of the radius of the reference vector, can be transferred to the surface of the hexagon, as illustrated in  FIGS. 2A and 2B . V ref  new is obtained by projecting V ref  onto the hexagon in a manner parallel to the first bisector of the sector considered. 
         [0037]    On the basis of the method according to the presently disclosed embodiment, only two near vectors have been used. Consequently, the zero vectors have been eliminated. Table 2 shows the resulting changes of switching in each sector. As illustrated for each individual sector, two switches have been kept fixed at 1 or 0. 
         [0000]    
       
         
               
             
               
               
               
               
               
               
               
             
           
               
                 TABLE 2 
               
             
             
               
                   
               
               
                 Switching strategy within the framework of the presently 
               
               
                 disclosed embodiment 
               
             
          
           
               
                 Breaker 
                 Sector 1 
                 Sector 2 
                 Sector 3 
                 Sector 4 
                 Sector 5 
                 Sector 6 
               
               
                   
               
               
                 s1 
                 1 
                 x 
                 0 
                 0 
                 x 
                 1 
               
               
                 s3 
                 x 
                 1 
                 1 
                 x 
                 0 
                 0 
               
               
                 s5 
                 0 
                 0 
                 X 
                 1 
                 1 
                 x 
               
               
                   
               
             
          
         
       
     
         [0038]    Within the framework of the traditional SVM methods, the vectors can be implemented through varied modulation schemes. 
         [0039]    As mentioned in Table 2 hereinabove, within the framework of the presently disclosed embodiment, only two changes of switching are performed. 
         [0040]    Thus, within the framework of the method according to the presently disclosed embodiment, the switching losses can be reduced by 66% in comparison with the traditional SVM methods. 
         [0041]      FIG. 3  illustrates the switching strategy within the framework of the method according to the presently disclosed embodiment. 
         [0042]      FIG. 3  shows the behavior of the switches in the method according to the presently disclosed embodiment, implemented by a right-aligned sequence. 
         [0043]    In the method according to the presently disclosed embodiment, a new reference which operates according to a hexagon is imposed instead of implementing a circular reference. 
         [0044]      FIG. 4  represents the amplitude in voltage per DC voltage as a function of radius. 
         [0045]      FIG. 4  shows that in the method according to the presently disclosed embodiment, performance is not linear as in the traditional SVM methods and can vary between 0.73 P.u and 0.65 P.u. 
         [0046]    The main results obtained by virtue of the method according to the presently disclosed embodiment are as follows: decrease the current undulation, attenuate the common-mode voltage (CMV), reduce the electromagnetic interactions, avoid the current at zero Amperes, prolong the lifetime of the battery and finally decrease the cost and size of the battery. 
         [0047]      FIG. 5  illustrates the DC mode current within the framework of the method according to the presently disclosed embodiment, by injecting an active power of 1 pu. 
         [0048]    As may be seen in  FIG. 5 , the DC mode current is approximately constant by injecting an active power. Without passing through zero, it can satisfy the above-mentioned objectives. 
         [0049]      FIGS. 6A and 6B  represent the AC mode current for a traditional SVM method ( FIG. 6A ) and for a method according to the presently disclosed embodiment ( FIG. 6B ) by injecting solely an active power. Consequently, the phase voltage in AC mode would have the same form as that represented in  FIGS. 6A and 6B . 
         [0050]    Hereinafter, we will describe a particular aspect of the disclosed embodiment. 
         [0051]    After having calculated the resulting zero time from the traditional SVM methods, this time can be allocated in an equal or non-equal manner to the near vectors. By allocating k percent to the first vector in each sector and (1−k) percent to the second vector, the performance of the method can be modified. By applying the previous concepts to one of the previous equations, it is possible to extract the following equation, in which k is a value chosen arbitrarily between 0 and 1. 
         [0000]        T   s   V   ref(new) =( t   i +(1− k )* t   z ) V   i +( t   i+1   +k*t   z ) V   i+1  
 
         [0000]      α i(new) =(α i +(1− k )*α z )
 
         [0000]      α i+1(new) =(α i+1   +k*α   z )
 
         [0052]    Through a non-equal allocation (k≠0.5), the operating zone has a tendency toward the first vector or toward the second vector. Hereinafter, by allocating more time to the first vector ( FIG. 7A ), the operating zone moves toward the right side of the hexagon. Conversely, by imposing more time toward the left vector ( FIG. 7B ), it tends to operate on the left side. 
         [0053]      FIGS. 7A and 7B  illustrate the operating zone with k=0.33 ( FIG. 7A ) and k=0.66 ( FIG. 7B ). 
         [0054]    The main factors to be analyzed in order to evaluate the performance are: 
         [0055]    the common-mode voltage, this creating common-mode current and leading to the failure of the motor in it windings insulation (consequently, the life of the motor may be shortened); 
         [0056]    the electromagnetic interference noise, which depends greatly on the evolution of the common-mode voltage level; 
         [0057]    the DC mode zero current, which may shorten the life expectancy of the battery. 
         [0058]    The number of switchings depends on the number of “ON” (closed) and “OFF” (open) durations in a constant switching time, as shown in the following Table 3. The number of switchings has a direct relation to switching losses. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 3 
               
             
             
               
                   
               
               
                 Number of switchings 
               
             
          
           
               
                   
                   
                 Method according to 
                   
               
               
                   
                   
                 the disclosed 
               
               
                 Method 
                 Traditional SVM 
                 embodiment 
                 Reduction in loss 
               
               
                   
               
               
                 Number of 
                 6 
                 2 
                 66% 
               
               
                 switchings 
               
               
                 Novelty 
                 No 
                 Yes 
                 Yes 
               
               
                   
               
             
          
         
       
     
         [0059]    Thus, we see that the number of switchings has been divided by three. 
         [0060]    In the traditional SVM methods, the common-mode voltage may attain the values of 
         [0000]    
       
         
           
             ± 
             
               
                 V 
                 dc 
               
               2 
             
           
         
       
     
         [0000]    because of the zero vectors and 
         [0000]    
       
         
           
             ± 
             
               
                 V 
                 dc 
               
               6 
             
           
         
       
     
         [0000]    because of the active vectors. The electromagnetic interference relates to changes of level of the common-mode voltage which attains 
         [0000]    
       
         
           
             
               V 
               dc 
             
             3 
           
         
       
     
         [0000]    in the best of situations and 
         [0000]    
       
         
           
             
               2 
                
               
                 V 
                 dc 
               
             
             3 
           
         
       
     
         [0000]    in the worst or situations. Within the framework of the method according to the presently disclosed embodiment, given that Ts is allocated solely to the active vectors, the common-mode voltage may be limited to 
         [0000]    
       
         
           
             ± 
             
               
                 V 
                 dc 
               
               6 
             
           
         
       
     
         [0000]    and the electromagnetic interference is the result of a change of just 
         [0000]    
       
         
           
             
               V 
               dc 
             
             3 
           
         
       
     
         [0000]    of the common-mode voltage. The following Table 4 provides a summary of the common-mode voltage for each method. 
         [0000]    
       
         
               
             
               
               
               
               
             
           
               
                 TABLE 4 
               
             
             
               
                   
               
               
                 Common-mode voltage 
               
             
          
           
               
                   
                   
                 Method according to the 
                 Reduction in the  
               
               
                 Method 
                 Traditional SVM 
                 disclosed embodiment 
                 common-mode voltage 
               
               
                   
               
               
                 Maximum common- mode voltage 
                 
                   
                     
                       
                         ± 
                         
                           
                             V 
                             dc 
                           
                           2 
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         ± 
                         
                           
                             V 
                             dc 
                           
                           6 
                         
                       
                     
                   
                 
                 66% 
               
               
                   
               
             
          
         
       
     
         [0061]    The inventors of the presently disclosed embodiment have carried out tests and have noted that the method according to the presently disclosed embodiment allows a clear reduction in electromagnetic interference. 
         [0062]    The following Table 5 illustrates the electromagnetic interference reduction, which is obtained by virtue of the method according to the presently disclosed embodiment. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE 5 
               
             
             
               
                   
               
               
                 Common-mode voltage and electromagnetic interference 
               
             
          
           
               
                   
                   
                 Maximum 
               
               
                   
                   
                 electromagnetic 
               
               
                   
                 Measured maximum 
                 interference due to the 
               
               
                 Method 
                 common-mode voltage 
                 common-mode voltage 
               
               
                   
               
               
                 Method according to the presently disclosed embodiment 
                  66.6 V 
                 
                   
                     
                       
                         
                           2 
                           * 
                           66.6 
                         
                         
                           T 
                           s 
                         
                       
                     
                   
                 
               
               
                   
               
               
                 Traditional SVM 
                   190 V 
                 
                   
                     
                       
                         
                           2 
                           * 
                           190 
                         
                         
                           T 
                           s 
                         
                       
                     
                   
                 
               
               
                   
               
               
                 Improvement 
                 Reduction of 65% 
                 Reduction 
               
               
                   
               
             
          
         
       
     
         [0063]    The method according to the presently disclosed embodiment also makes it possible to reduce the temperature of the inverter. 
         [0064]      FIG. 8  and Table 6 hereinbelow illustrate results obtained relating to the temperature of the inverter. 
         [0000]    
       
         
               
             
               
               
               
             
               
               
               
             
           
               
                 TABLE 6 
               
             
             
               
                   
               
               
                 Temperature of the inverter 
               
             
          
           
               
                   
                 Temperature 
                 Temperature with method 
               
               
                 Operating time 
                 with traditional SVMs 
                 according to the 
               
               
                 (minutes) 
                 (centigrade) 
                 invention (centigrade) 
               
               
                   
               
             
          
           
               
                 0 
                 31 
                 31.1 
               
               
                 1 
                 33.6 
                 32.5 
               
               
                 2 
                 36.7 
                 33.8 
               
               
                 3 
                 37.8 
                 35 
               
               
                 4 
                 39.3 
                 35.7 
               
               
                 5 
                 41.1 
                 36.6 
               
               
                 6 
                 42.5 
                 37.2 
               
               
                 7 
                 44 
                 38.2 
               
               
                 8 
                 44.9 
                 38.7 
               
               
                 9 
                 45.9 
                 39.1 
               
               
                 10 
                 47.4 
                 39.8 
               
               
                 11 
                 48.2 
                 40.3 
               
               
                 12 
                 49 
                 44.9 
               
               
                 13 
                 49.4 
                 41.3 
               
               
                   
               
             
          
         
       
     
         [0065]    The performance of the inverter is in particular defined the efficiency as the ratio between the AC mode output power of the inverter (in effective value) and the DC mode input power which is imposed as input source. 
         [0066]    The performance obtained by virtue of the presently disclosed embodiment is represented in Table 7 hereinbelow: 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                   
               
               
                   
                 DC mode 
                 DC mode 
                 Input 
                 Output 
                   
               
               
                 Method 
                 voltage 
                 current 
                 power 
                 power 
                 Efficiency 
               
               
                   
               
             
             
               
                 Traditional SVMs 
                 401 Volts 
                 6.78 
                 2718 
                 2500 
                 91.4% 
               
               
                   
                   
                 Amperes 
                 Watts 
                 Watts 
               
               
                 Method according 
                 402 Volts 
                 7.29 
                 2930 
                 2820 
                 96.7% 
               
               
                 to the disclosed 
                   
                 Amperes 
                 Watts 
                 Watts 
               
               
                 embodiment 
               
               
                   
               
             
          
         
       
     
         [0067]    Thus, the efficiency of the system has been improved by more than 5%. 
         [0068]    The disclosed embodiment is described in the foregoing by way of example. It is understood that the person skilled in the art is able to carry out different variants of the disclosed embodiment without, however, departing from the scope of the disclosed embodiment.