Abstract:
The present invention provides a magnetic memory device that includes a magnetic memory cell switchable between two states by the application of a magnetic field wherein the magnetic field for such switching is dependent in part on a memory cell temperature. The device further includes at least one heater element proximate to the magnetic memory cell and series connected with the magnetic memory cell for heating of the magnetic memory cell. The device also includes a circuit for selectively applying the electrical current through the at least one heater element so as to heat the cell and facilitate cell state-switching.

Description:
FIELD OF THE INVENTION 
   The present invention relates to magnetic memory devices, and more specifically to a magnetic random access memory (MRAM) device. 
   BACKGROUND OF THE INVENTION 
   Non-volatile magnetic random access memory (MRAM) devices have the potential to replace volatile dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices in some applications. The MRAM devices include arrays of memory cells such as tunneling magneto-resistance (TMR), colossal magneto-resistance (CMR), and giant magneto-resistance (GMR) memory cells. 
   MRAM cells typically include “data” and “reference” layers. The data layer includes a writeable magnetic material, and the reference layer includes a fixed magnetic material. A dielectric layer in between the two has greater or lesser resistance to electrical current depending on whether the magnetic fields from the sandwiching layers are canceling or reinforcing one another. 
   During a write operation, the magnetization of the data layer can be switched between two opposite states by applying an electro-magnetic field through a nearby wire loop. Thus binary information can be stored. The reference layer usually includes a magnetic material in which the magnetization is pinned. A magnetic field applied to the data layer penetrates the reference layer with insufficient strength to switch the magnetization in the reference layer. 
   For example, in a TMR cell, the data layer and the reference layer are separated by a thin dielectric layer so that a tunneling junction is formed. The probability that electrons will be able to tunnel through the dielectric layer depends on the direction of the magnetization in the data layer relative to the direction of the magnetization in the reference layer. Therefore, the structure is “magneto-resistant” and information can be stored and retrieved by reading the magnitude of tunneling currents thereafter able to pass through the memory cell. 
   In general, the magnetic memory cells should be as small as possible. However, the smaller the cells are made, the more sensitive they are to thermal stability problems during operation. In order to compensate, the small magnetic memory cell data layers are fabricated with magnetic material that is more resistant to magnetic change. Unfortunately, generating the stronger fields necessary makes switching the memory cells more difficult during the write operation. Hence, there is a need for a magnetic memory device that addresses these concerns. 
   SUMMARY OF THE INVENTION 
   Briefly, a magnetic random access memory (MRAM) device embodiment of the present invention includes a magnetic memory cell switchable between two states by the application of a magnetic field. The magnetic field is dependent in part on a memory cell temperature. The device further includes at least one heater element proximate to the magnetic memory cell and series connected with the magnetic memory cell for heating of the magnetic memory cell. The device also includes a circuit for selectively applying the electrical current through the at least one heater element so as to heat the cell and facilitate cell state-switching. 
   The invention will be more fully understood from the following description of embodiments of the memory device. The description is provided with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a perspective diagram of a magnetic memory device in accordance with an embodiment of the present invention; 
       FIG. 2  is a schematic cross-sectional diagram of a magnetic memory device according to an embodiment; 
       FIG. 3  is a schematic cross-sectional diagram of a magnetic memory device according to an embodiment; 
       FIG. 4  is a schematic cross-sectional diagram of a magnetic memory device according to an embodiment; 
       FIG. 5  is a schematic cross-sectional diagram of a magnetic memory devices according to another embodiment; 
       FIG. 6  is a schematic cross-sectional diagram of a magnetic memory device according to a further embodiment; 
       FIG. 7  is a schematic diagram of a computer system embodying the device shown in  FIG. 1 ; and 
       FIG. 8  is a flow-chart for a method in accordance with an embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF EMBODIMENTS 
   Referring initially to  FIG. 1 , a magnetic random access memory (MRAM) embodiment is now described. The MRAM  100  includes a number of individual magneto-resistance memory (TMR) memory cells  102  and electrical heaters  103  connected in series. Each cell  102  is electrically connected and addressible by word and bit lines. For example, between word lines  104 ,  106 , and bit line  108 . For clarity only one bit line  108  is shown in  FIG. 1 . 
   When a current is applied along bit line  108 , a magnetic field will surround the bit line  108  which can be utilized to switch the magnetization of the memory cells  102 . During switching the heaters  103  generate heat which lowers the magnetic field strength for switching the memory cells  102  and thus heating facilitates switching of the memory cells. 
     FIG. 1  schematically indicates a circuit unit  110  that generates a voltage potential between the ends of bit line  108 . The circuit unit  110  may also generate a voltage potential along word lines  104  and  106 . For clarity, electrical connections to the circuit unit  110  are not shown for word lines  104  and  106 . Alternatively, the word lines  104  and  106  may be grounded. As the magnetic memory cells  102  have a finite resistivity, a current will also flow between bit line  108  and word lines  104  and  108  through respective magnetic memory cells  102 . 
   The device  100  also includes a control circuitry  112  for selectively applying an electrical current through the heaters so as to heat the cell and facilitate cell state-switching. For clarity, only one connection of the control circuitry  112  to the word line  104  and bit line  108  is shown. 
   MRAM  100  further includes a read circuit for sensing the resistance of selected memory cells  102  during read operations. During read operations, a constant supply voltage or a ground potential is applied to the bit line  108 . The constant supply voltage may be provided by an external circuit. The read circuit is not shown in order to simplify the description. 
   In general there are three methods of applying the potential to the magnetic memory cell  102  to determine the tunneling currents and therefore to sense the resistance state of the selected memory cells  102 . A first method uses a current source, voltage follower and comparator to determine the resistance state of a selected memory cell. A second method uses current sense amplifier and a voltage source to detect the resistance state of a selected memory cell. A third method uses a direct injection charge amplifier to apply an equal potential to MRAM  100  during a read operation on a selected memory cell  102 . 
   MRAM  100  may also include an array having any number of memory cells  102  arranged in any number of rows and columns. It can also use alternative technologies such as colossal magneto-resistance memory cells (CMR), and giant magneto-resistance memory (GMR) cells. 
     FIG. 2  shows a cross-sectional diagram of the memory cell  202  contacted by the word line  204 . The memory cell  202  includes a data layer  208 , a thin dielectric layer  210  and a reference layer  212 . In general, the magnetization in the data layer  208  of MRAM  200  can have two opposing directions so that binary information can be stored as a function of the direction of the magnetic field generated by the current applied to bit line  216 . 
   The reference layer  212  has a magnetic material in which the direction of magnetization can be pinned. The data layer  208  uses a magnetic material with a direction of magnetization that can be switched as a function of an applied magnetic field. 
   The dielectric layer  210  is thin enough so that a tunneling current will flow through the dielectric layer when a suitable electrical potential is applied. The tunneling probability, and therefore the effective resistance of the memory cell, depends on the direction of the magnetization in the data layer  210  relative to that of the reference layer  208 . Therefore, it is possible to magnetically store and electrically read data by sensing the magnetic orientation in the data layer from the resistance of the memory cell  102  to the tunneling current. 
   In this embodiment a further dielectric layer  214  is positioned between the data-layer  208  and the bit line  216 . The dielectric layer  214  is thin enough so that, when a potential is applied between the word line  204  and the bit line  216  a tunneling current will flow through the dielectric layer  214  resulting in generation of heat. The heat diffuses at least in part into the data layer  208 . Due to the heat, the magnetic field strength for switching the magnetization of the data layer  208  is lower and thus heating of the data layer  208  facilitates switching of the magnetization. 
   The dielectric layer  214  may have a thickness ranging from 0.5 to 10 nm and may be composed of any suitable dielectric material including for example aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) and magnesium oxide (MgO). 
   In this particular example the data layer  208  is composed of nickel iron (NiFe), the reference layer  212  is composed of cobalt iron (CoFe) and the dielectric layers  210  and  214  are composed of Al 2 O 3 . All layers have the same planar area of approximately 150 nm×300 nm, and the reference layer  212 , the data layer  208  and the dielectric layers  210  and  214  have a thickness of approximately 2 nm, 3.5 nm, 1.2 nm, and 1.2 nm, respectively. The resistance of the magnetic memory cell  202  (including contact resistances) is approximately 100 kOhms which in this embodiment equals approximately that of the resistance added to the device due to the presence of the additional tunneling junction at dielectric layer  214 . Therefore, the device includes two heat sources that develop approximately the same amount of heat. 
     FIG. 3  shows another embodiment which relates to the embodiment shown in  FIG. 2 .  FIG. 3  shows a portion of magnetic memory device  300  including magnetic memory cell  302  having data layer  304 , dielectric layer  306  and reference layer  308 . Analogous to the device shown in  FIG. 2 , a dielectric layer  310  is sandwiched between data layer  304  and bit line  312 . In this case the device  300  includes a third dielectric layer  314  positioned between reference layer  308  and word line  316  which forms further tunneling junction. Layer  310  and layer  314  have, in this embodiment, identical properties. Therefore, the device shown in this  FIG. 3  has a total of three tunneling junctions at dielectric layers  306 ,  310  and  314 . In this embodiment the three heat sources deliver an approximately equal amount of heat but alternatively the device may also be such that each heat-source delivers a different amount of heat. 
     FIG. 4  shows a cross-sectional representation of a portion of device  400 . Magnetic memory cell  402  includes data layer  404 , dielectric layer  406  and reference layer  408 . The magnetic memory cell  402  is contacted by word line  410 . In this embodiment a resistive layer  412  is positioned between the data-layer  404  and the bit line  414 . When a potential is applied between the word line  410  and the bit line  414  a current will flow through the layer  412  resulting in generation of heat. Therefore, the shown device has two heat sources—the tunneling junction at dielectric layer  406  and the resistive layer  412 . 
   Exemplary materials for the resistive layer  412  include semiconductors (e.g., Si, Ge, Se, C, SiC), oxides (e.g., HfO 2 , ZrO 2 , AlO), silicides (e.g., TaSi, WSi, TiSi), nitrides (e.g., TaN, TiN, TaSiN, WN, WSiN). For resistive layers including oxides, silicides and nitrides, the composition of the material may be adjusted to tailor the resistivity, but in this case the layer  412  is composed of amorphous silicon. The resistance of the resistive layer  412  depends on the thickness of the layer and its planar area. In this example the layer  412  has an area of approximately 150×300 nm and a thickness of about 20 nm. In this example the resultant resistance is of layer  412  is 100 kOhm. 
   In general, the heat-inducing layers  214  and  412  are selected so that the heat-induced by each layer may be 50% to 100% of that generated by the magnetic memory cell. Alternatively, the layer is selected so that the heat induced by the layer is greater than that generated by the magnetic memory cell. In this case each heat-inducing layer may have more than 50% of the design resistance of the magnetic memory cell and typically has more than 100% of the design resistance of the magnetic memory cell. 
   For example, the memory cell and each heat-inducing layer may have a resistance of 1 kOhm to 1 MOhm and a voltage of 2V may be applied across a series connection of the magnetic memory cell and the heat-inducing layer. 
   In the embodiments shown in  FIGS. 2 and 4  the heat-inducing layers  214  and  412  are in contact with the memory cell. Alternatively, at least one additional layer of insulating or conductive material may be disposed between each heat-inducting layer and the magnetic memory cell. 
     FIG. 5  shows another embodiment which relates to the embodiment shown in  FIG. 4 .  FIG. 5  shows a cross-sectional representation a portion of device  500 . Magnetic memory cell  502  includes data layer  504 , dielectric layer  506  and reference layer  508 . The magnetic memory cell  502  is contacted by word line  510 . Resistive layer  512  is positioned between the data-layer  504  and the bit line  514 . In this case the device  500  includes a further resistive layer  516  positioned between reference layer  508  and word line  518 . Resistive layers  512  and  516  are generally identical. Therefore, the device shown in this Fig. has a total of three heat sources: the tunneling junction at dielectric layer  506  and the resistive layers  512  and  516 . 
     FIG. 6  shows a combination of the embodiments shown in  FIGS. 2 to 3  and  4  to  5 .  FIG. 6  shows a cross-sectional representation a portion of MRAM  600 . Magnetic memory cell  602  includes data layer  604 , dielectric layer  606  and reference layer  608 . A resistive layer  610  is in contact with the bit line  612  and a dielectric layer  614  is disposed between the resistive layer  612  and the data layer  604 . In general, the resistive layer  610  and the dielectric layer  614  correspond in composition and dimensions to resistive layer  512  and dielectric layer  310  shown in  FIGS. 5 and 3  respectively. Therefore, the device includes two adjacent heat sources, namely the tunneling junction at dielectric layer  614  and the resistive layer  610  in addition to the tunneling junction at dielectric layer  606 . It is to be appreciated that alternatively or additionally a dielectric layer and a resistive layer may be disposed between word line  616  and reference layer  608 . 
     FIG. 7  shows a computer system  700  which embodies the memory device shown in  FIG. 1 . The computer system  700  has a main board  702  which is connected to a central processing unit  704  and magnetic memory device array  706 . The magnetic memory device array  706  includes the device shown in  FIG. 1 . The magnetic memory device array  706  and the central processing unit  704  are connected to a common bus  708 . The computer system  700  has a range of further components which are for clarity not shown. 
     FIG. 8  illustrates a method embodiment of storing data in a magnetic memory device such as device  100  shown in  FIG. 1 . The method  800  includes the step  802  of writing data to the magnetic memory cell by using a write current directed through a conductor adjacent the magnetic memory cell to generate a magnetic field to switch the data layer. In step  804  a heat current is directed through a heat-inducing layer that is proximate to the magnetic memory cell and series connected with the magnetic memory cell. In this embodiment the heat current is a branch current of the write current. The heat-inducing layer effects heating of the magnetic memory cell to reduce the strength of the magnetic field needed to switch the data layer. 
   Although the embodiments have been described with reference to particular examples, it is to be appreciated by those skilled in the art that the embodiments may take other forms. For example, the magnetic memory cells may be colossal magneto-resistance memory cells (CMR) or giant magneto-resistance memory (GMR) cells. Further, at least one additional layer of insulating or conductive material may be disposed between the bit-line and the memory cell. The at least one additional layer may be disposed between the memory cell and the at least one heat-inducing layer or between the at least one heat-inducing layer and the bit line. In this case the magnetic memory cell may be electrically isolated form the bit and/or word lines. 
   For example, a sense conductor may be in electrical contact with the memory cell (ie with the data layer) and an electrically insulating layer may be disposed between the bit line and the sense layer. Also, if there are more than one additional insulating or conductive layers, at least one of the additional layers may be disposed between the heat-inducing layer and the memory cell and at least one of the additional layers may be disposed between the bit line and the heat-inducing layer. Further, it is to be appreciated that each magnetic memory cell may include a number of additional layers such as capping, AF and seed layers.