Abstract:
A system and method of controlling the operation of linear variable-gain amplifiers to allow for such linear variable gain amplifiers to have a wider operating range at high current levels, control inputs for selectable gains and improved low-voltage operation. In a first mode, the amplifier includes an additional source of current to allow for an enhanced operating range. In a second embodiment, the amplifier includes a plurality of selective resistive levels and a selection system which allows the selection of one of the resistive levels which, in turn, controls the gain range of the amplifier system of the present invention. A third embodiment of the present invention illustrates the use of an amplifier system useful for a low voltage input signal to reduce errors caused by variations in the base to emitter in the two transistors providing the amplification. Also disclosed are embodiments for reducing the error in the amplifier output by providing additional stages to provide error reducing components which are added to the amplifier output.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to improvements in linear variable gain amplifiers. More particularly, the present invention relates to improvements in the operating range gain control of such amplifiers. 
     2. Background Art 
     Linear variable gain amplifiers are amplifiers which receive a pair of input signals and amplify the difference between the two signals in an output signal for subsequent use. Such amplifiers are used in many applications in common use today. For example, such devices are used in high-fidelity sound transmitting and receiving systems, as well as in servo systems such as are used for disk drive read channels. 
     It is desirable to control the gain of the linear variable amplifier while achieving a linear-in-dB gain control over a wide range of amplifier gains. Controlling the gain of the amplifier is accomplished typically through adjusting the bias current, as the voltage gain of the differential stage of the amplifier is directly related to the bias current. 
     Various systems have been proposed for increasing the gain of a linear variable gain amplifier, but the maximum bias current is limited by the lowest common mode voltage which does not have the transistors fall into the saturation region. However, as the supply voltage decreases, the usable bias level gets smaller. The prior art linear variable gain amplifier systems thus had a limited operating range, which is undesirable as it limits the usefulness of the amplifier. 
     Another limitation of the prior art linear variable gain amplifiers is the gain is often difficult to control and change quickly because the gain depends on the changing of current flowing through a transistor. It would be desirable to have an amplifier with discrete gain range control, but no such linear variable gain amplifier has been proposed in the prior art. 
     A third limitation of linear variable gain amplifiers is that low voltage applications frequently have an emitter-degenerated differential stage which makes it difficult to have a high-accuracy differential amplifier when operating at a low voltage. For applications which operate at low voltage, such as a servo control system, it would be desirable to have a high accuracy variable gain linear amplifier even when the input voltage is low. 
     Prior art linear variable gain amplifier systems have other limitations and disadvantages which will be apparent to those skilled in the art in view of the following description of the present invention. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes the disadvantages and limitations of the prior art systems for controlling the operating range of a variable gain amplifier. 
     The present invention has the advantage that, in one embodiment, the linear variable gain amplifier system may obtain a high gain, with a corresponding high bias current, without driving an input transistor into saturation. Such a linear variable gain amplifier system allows the input transistors to remain in the active or linear region, rather than driving the transistors into a saturation level when the bias current goes high. Such a system allows a larger usable range of bias current levels in the linear variable gain amplifier system of the present invention. 
     A second advantage of the amplifier circuits of the present invention is to provide a greater gain range of the amplifier and a controlled or selected gain operating at a quick speed. In this way the same linear variable gain amplifier could be operating at one gain and switched quickly to operate at a different gain without traversing through intermediate gains through a ramping of current through a transistor operating in the linear range. In one embodiment of the present invention, an amplifier with a discrete gain range selection is provided through the use of selectable (binary or digital) control inputs. That is, a particular gain range can be selected from among several options and applied to the linear variable gain amplifier by selecting an effective resistance and switching that resistance into the amplifier circuit though the use of one or more transistors which are turned on. The same system can be operated at a different gain range at a different time by selecting a different control input, causing a different impedance and therefor a different gain to be seen by the linear variable gain amplifier system of the present invention. This gain range may be selected by applying a selected resistance across the emitter of the transistor, either individually or in selective combinations to adjust the effective resistance seen by the amplifier and thus adjust the gain of the amplifier. 
     A third advantage of the amplifier system of one embodiment of the present invention is a linear variable gain amplifier system suitable for low voltage applications. This system is a high-accuracy differential linear amplifier system which is particularly useful for an emitter-degenerated differential stage, allowing use of a high accuracy differential amplifier in low voltage applications (such as servo disk driver or in the IF (Intermediate frequency) or base-band amplifier for wireless receivers where the input electrical signal may be quite small and needs substantial amplification for subsequent use. 
     The present invention is a linear variable gain amplifier which has improved performance and enhanced operating range. The enhanced operating range originates from having a wider operating current in one embodiment and permits a lower voltage operation without degrading the performance in an other embodiment. In a third variation, the amplifier of the present invention allows for binary (or switch) selection of effective resistors, alone or in combination, to select a gain range for the amplifier. 
     The operating features of the present invention provide various improvements in the linear variable gain amplifier system and can be selected and combined as appropriate for a given application. Thus, one application may require both a low input and a wide operating range and another application may require selectable gain control along with either a wide operating range or a low voltage input. 
     Other objects and advantages of the several amplifier embodiments of the present invention will be apparent to those skilled in the relevant art in view of the following description of the preferred embodiment, taken together with the accompanying drawings and the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Having thus described some objects and advantages of the present invention, the present invention of an improved amplifier system and method is described in connection with the accompanying drawings in which: 
     FIG. 1 is a circuit schematic diagram depicting a linear variable gain differential amplifier of the prior art. 
     FIG. 2 is a graph of a typical response of the amplifier of FIG. 1, plotting voltage out as a function of the bias current. 
     FIG. 3 is a circuit schematic diagram of one embodiment of the present invention; 
     FIG. 4 is a graph of a typical response of the circuit diagrammed in FIG. 3, plotting voltage out as a function of the bias current; 
     FIG. 5 is a circuit schematic diagram of a second embodiment of the present invention, an alternate design to that shown in FIG. 3; 
     FIG. 6 is circuit schematic diagram of an other embodiment of the amplifier of the present invention 
     FIG. 7 is a circuit schematic diagram of yet another alternate embodiment of the present invention; 
     FIG. 8 is a circuit schematic diagram of an extension of the amplifier circuit of FIG. 7; 
     FIG. 9 is a circuit schematic diagram of a modification of FIG.  8  and 
     FIG. 10 is a circuit schematic diagram of a variation of the embodiments of FIGS. 8 and 9. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In the following description of the preferred embodiments, the best implementations of practicing the invention presently known to the inventor will be described with some particularity. However, this description is intended as a broad, general teaching of the concepts of the present invention using several specific embodiments, but it is not intended to be limiting the present invention to the implementation as shown in any of these embodiments, especially since those skilled in the relevant art will recognize many variations and changes to the specific structure and operation shown and described with respect to these figures. 
     FIG. 1 illustrates a linear, variable-gain amplifier circuit of the prior art. A plus (or positive) input INP is applied to the base of a first transistor Q 1  and a minus or negative input INM is applied to the base of a second transistor Q 2 . The amplified output is taken between a plus (or positive) output Voutp and a minus (or negative) output Voutn at the collectors of the first transistor Q 1  and the second transistor Q 2 . A third transistor Q 3  is coupled with its emitter resistor R 3  to the emitters of the first transistor Q 1  and the second transistor Q 2  as shown in this FIG. 1, creating a common leg through which a main tail current (or bias current) I 1  passes. Resistors R 1  and R 2  are associated with the first transistor Q 1  and the second transistor Q 2 , respectively. Current I 0  passes through the resistors R 1 , R 2  from a bias current source Ibias. 
     The gain of the amplifier is a function of bias current I 1  passing through the transistor Q 3 , through a formula A v =g m  R c =I l /N T R c , where g m  is the transconductance of the transistors, which is derived to be I l/V   T  in bipolar transistors, where I l  is the bias current and V T  is the thermal voltage defined by kT/q where k is the Boltzman constant, T is the absolute temperature, and q is the charge of the electron. To increase the gain A v  of the amplifier, the bias current I l  must be increased. However, the maximum bias current I l  is limited by the supply voltage and the minimum collector voltage of Q 1  and Q 2  that keeps Q 1  and Q 2  from working at saturation region as increase in the bias current I 1  result in decreased voltage at V OUTP  and V OUTN . Consequently, as the supply voltage goes lower, the maximum bias current is also reduced because the voltage drop across the resistor increases as the bias current increases until the transistors Q 1  and Q 2  fall into saturation region based on the bias current through them. The maximum bias current I l  is limited by the lowest output voltage at V OUTP  and V OUTN  which does not have the transistors Q 1  and Q 2  fall into saturation region, which is approximately 2.7 volts for a maximum input voltage of about 3.3 volts. 
     FIG. 2 provides a graphical representation of a typical output for the amplifier circuit depicted in FIG.  1 . This graphical representation assumes that the supply voltage Vs is 3.3 volts and when the current flowing through the transistors Q 1  and Q 2  is very small (approaching 0), then the gain is low (a small signal is shown near I 1  approaching zero and Vs is approximately 3.3 volts). As the bias current I 1  increases, the signal amplification increases through the linear region until the bias current is approximately 1 milliamp (mA) in this example as shown in FIG. 2, where the output voltage Vout is approximately 2.7 volts. At the point where the output voltage Vout is approximately 2.7 volts, the current I 0  through each of the transistors Q 1  and Q 2  are at the verge of saturation region, and further increases in the bias current I 1  are limited by the saturated state of the transistors so that the minimum Vout never goes below a saturation value of approximately 2.7 volts. This is sometimes referred to as a clamped output and is depicted in FIG. 2 as a horizontal line beginning between 1 and 2 mA of bias current I 1 . One objective of the present invention is to keep the common mode output voltage from decreasing to have a symmetric shape rather than a clamped output where one side of the output is limited while the other side is not. 
     When the shape is not symmetric because one side is clamped, the output is distorted and the useful range of the amplifier is limited. It is thus desirable to avoid having the output clamped and to provide an amplifier with increased range of operation as will be discussed in connection with the embodiment of FIGS. 3 and 5 and the output of FIG.  4 . 
     FIG. 3 is a schematic circuit diagram for an improved amplifier circuit of the present invention. It includes the variable gain circuit of FIG. 1 with several field effect transistors M 1 , M 2 , M 3 , M 4  and M 5  added to selectively provide increased bias current I 1  passing through the transistor Q 3 , increasing the gain of the amplifier without driving the transistors Q 1  and Q 2  into saturation. The base amplifier includes the transistors Q 1  and Q 2  with the associated resistors R 1 , R 2 , with inputs INP and INM and the output taken across the terminals Voutn and Voutp. Added to the base amplifier circuit of FIG. 1 are a first field effect transistor M 1  coupled to provide additional current IM 1  into the transistor Q 1  and a second field effect transistor M 2  providing current IM 2  into the transistor Q 2 . The gate of the first field effect transistor M 1  and the second field effect transistor M 2  are each coupled to the gate of a field effect transistor M 3 . A fourth field effect transistor M 4  and a field effect transistor M 5  are coupled to third field effect transistor M 3  as shown in FIG.  3 . The first field effect transistor M 1  and the second field effect transistor M 2  are half the size of the third field effect transistor M 3 , so that the current flowing through each of the first and second field effect transistors M 1  and M 2  is half the current flowing through the third field effect transistor M 3 . An additional transistor Q 4  is coupled to the third and fourth field effect transistors M 3  and M 4  with a current I 2  passing through it which replicates the current I 1  passing through the transistor Q 3  because both transistors Q 1  and Q 3  have the same base drive. 
     In FIG. 3, the current I 1  is the current which determines the gain of the amplifier as described in connection with FIG. 1. I ref  should be set such that the voltage swing is placed in the middle of the operating range as shown in FIG.  4 . The current I ref  in the transistor M 5  is the optimum current level that is required by resistors R 1  and R 2  such that the common mode of the output swing can be placed between the supply voltage VCC and the minimum allowed voltage at the collector nodes of Q 1  and Q 2 . Until the current I 2  reaches Iref, the transistor M 3  stays off and keeps the transistors M 1  and M 2  off as M 4  can supply the necessary current to Q 4 , which is I 2 . Once the current I 2  increases past Iref, the difference in current (I 2 −Iref) has to be supplied from M 3  as I 3  because the maximum current I 4  is limited by Iref by current mirroring between M 4  and M 5 . Once M 3  is turned on, half of I 3  flows through each of the transistors M 1  and M 2  as they are mirrored with M 3  and the W/L ratio of M 1  and M 2  is designed to be half of that in M 3 . 
     The mathematical representation of I 3  is 
     
       
           I   3   =I   2   −I   4 =0 when  I 2     &lt;Iref   (1) 
       
     
     I 2 -Iref when I 2 &gt;=Iref 
     Hence, the bias current I 0  through R 1  or R 2  is calculated as 
     
       
           I 0     =I 1 / 2   - IM 1   =( I   1   −I 3   )/2 
       
     
     Also, I 1 =I 2  by the design. 
     Substituting I 3  from Equation (1) will make 
     
       
           I 0     =I 1 / 2   when  I 1     &lt;Iref=Iref /2 when  I   1   &gt;=Iref   (2) 
       
     
     At this point, only the necessary bias current I 0  flows though each of the collector resistors R 1  and R 2 , allowing the tail current I 1  to be greater than twice the bias current I 0  flowing through either resistors R 1  or R 2 . Equation (2) above shows that the bias current through R 1  and R 2  increases as I 1  increases until I 1  reaches Iref, which is a design value to set the optimum bias condition in R 1  and R 2 . Once I 1  increases past Iref, I 0  stays constant and won&#39;t change the bias level in R 1  and R 2 . 
     FIG. 4 provides a graphical representation of typical output for the circuit of FIG.  3 . The output common mode voltage follows the same downward path from bias current I 1  of zero (where the output voltage Vout is at the supply voltage of 3.3 volts) to a point marked Iref where the voltage turns flat as the bias current increase. The point where the voltage of Vout turns flat is theoretically equal to the reference current IrefR C  and is shown at a bias current I 1 , which is where the field effect transistor M 3  of FIG. 3 turns on to provide additional current through the field effect transistors M 1  and M 2  to add to the current I 0  passing through the transistors Q 1 , Q 2 . 
     The addition of the field effect transistors M 1  and M 2  in FIG. 3 to the variable gain amplifier of FIG. 1 has the unfortunate side effect of increasing the parasitic capacitance seen at the outputs Voutp, Voutn. Since the response time at the output of the amplifier is a function of the time constant of the amplifier system, any increase in the capacitance increases the response time and reduces the amplification during the response time, an undesirable effect. In order to reduce the effective capacitance seen at the output and to improve the amplifier response time, a cascode stage consisting of transistors Q 5  and Q 6  is added in FIG. 5 to the amplifier circuit of FIG.  3 . The usage of transistors Q 5  and Q 6  reduces the parasitic capacitance effect of the field effects transistors M 1 , M 2  in the circuit of FIG. 3 by isolating the outputs Voutp, Voutn from M 1  and M 2 . 
     FIG. 6 is an alternate embodiment of an amplifier system capable of operating at one of a plurality of gains, where different stages  601 ,  602  and  603  are provided for the amplifier circuit and signal inputs provided for selecting the desired gain range. Collector load resistors RC 1  and RC 2  are in common, shared across the stages, and positive input INP is coupled to the base of transistors Q 1 , Q 3  and Q 5  while the minus input INM is coupled to the base of transistors Q 2 , Q 4  and Q 6 . 
     The gain Av of the amplifier of this design can be approximated by the ratio of the collector resistor RC 1  divided by the emitter resistor RE 1   a . So, if the collector resistor RC 1  is 10K ohms and the emitter resistor is RE 1   a  is 1K ohms, then the gain of the amplifier is approximately 10. To increase the gain of the amplifier, one must either increase the collector resistor RC or decrease the emitter resistor RE, which is accomplished in the present invention by switching another digital input on, either with or without switching the first digital input off If a lower resistor replaces a previously-switched on emitter resistor, then the gain increases because of the lower emitter resistance. 
     So, common collector resistors RC and common outputs vop, von are coupled to a plurality of amplifier stages  601 ,  602 ,  603 , each of which is controlled by an input signal von 1 , von 2 , von 3 , respectively, coupled to the gate of a MOSFET M 61 , M 62 , and M 63 , respectively, and is driven by an input current iin 1 , iin 2  and iin 3 , respectively. So, the stage  601  includes a input signal von 1  which is coupled to the gate of the MOSFET M 61 . The input signal von 1  is high when the stage is to be turned off and low when the stage is to be turned on, since when the voltage is high on the input von 1 , then the MOSFET M 61  is turned on, bringing the base of the transistor Q 7  and Q 9  low. 
     The stage  602  includes a MOSFET  62  with an input von 2  used to turn the stage  602  and its emitter resistors on or off. Similarly, the stage  603  includes a MOSFET  613  and an input von 3  to turn the stage and its input resistors on or off. Typically, the emitter resistors in each stage would differ from each other to provide different gains when the stages are turned on individually. Thus, the resistor RE 1   a  might be 100 ohms, the resistor RE 2   a  might be 200 ohms and the resistor RE 3   a  might be 400 ohms. 
     If two stages are turned on at the same time, the effect is to have the resistance which is the equivalent of having the two emitter resistors in parallel, effectively reducing the resistance and increasing the gain of the amplifier, since the effect of resistors RA and RB in parallel is a resistance of (RA·RB)/(RA+RB), resistance which is less than either resistor alone. And, further, additional stages could be turned on, further reducing the effective emitter resistance and increasing the gain of the amplifier. 
     FIG. 7 is another alternate embodiment of the amplifier of the present invention and addresses the situation where an emitter-degenerated differential stage provides an output signal which is not linear enough over a wide range of input signals. It is well known that the amplifier in FIG. 1 has the gain in hyperbolic tangent function form (Av˜tanh Vin). Tanh x function can be approximated to x only if x is very small, which means that the gain is linear only if the input difference is very small. In order to improve the linearity of the differential amplifier in FIG. 1, emitter degeneration resistor RE is inserted as shown in the circuit  701  in FIG.  7 . The linearity of this amplifier is improved, but still there are applications where higher linearity is necessary. This non-linearity stems from differences in the transistors, particularly in the difference in the base-emitter voltages due to the current difference through the transistors as the input signal is changing. (a more detailed description is as follows: The voltage across the two emitter resistors RE should be proportional to the input voltage difference INP and INM. Otherwise the amplifier is not linear. In the circuit  701  in FIG. 7, when INP goes higher than INM, the current through transistor Q 1  goes higher that the current in transistor Q 2 . Hence, the base-emitter voltage of Q 1  is higher than that of Q 2 , so the voltage across between the two RE&#39;s will be smaller. If the input voltage difference is even larger, the loss in the voltage across the two RE&#39;s will be larger. Because of this effect, the gain is reduced if the input voltage difference is large.) Since the base-emitter voltage drop for a transistor is V T * ln(I 1 /IS) where IS is the saturation current of the transistor, the difference in voltage drops between the base and emitter of two transistors is a function of the log of the ratios of the currents in passing through the respective transistors. This design compensates for the difference in VBE voltages between Q 1  and Q 2  when INP goes high and INN goes low or vice versa. 
     The difference in voltage between the base and emitters (sometimes called an error voltage) is replicated in an additional stage and converted to an error current which is then subtracted from the current in the main amplifier stage. 
     So, FIG. 7 illustrates a linear variable gain amplifier having a main stage  701  and a adjusting stage  702 . The main stage is similar to that shown in other figures, particularly FIG. 1 in having a first transistor Q 1  and a second transistor Q 2 , each receiving at its base one of the inputs INP and INM. A collector resistor RC is associated with each transistor and the outputs von and vop are taken between the collector resistors RC and the collector of the respective transistor. An emitter resistor RE is associated with each transistor and current source I 0  provides current for the stage. 
     The stage  702  is a differential stage which includes transistor Q 7  coupled to the positive input INP and transistor Q 8  coupled to the negative input INM. Transistors Q 9  and Q 10  are coupled to the transistors Q 7  and Q 8 , respectively, with transistor Q 5  coupled to transistor Q 9  and transistor Q 6  coupled to transistor Q 10 . 
     The current output in the Q 1 -Q 2  differential stage is 
     
       
           I   out1 =( V   in   −Δ   V   BE1,2 )/2 R   E   (3) 
       
     
     In Equation (3) above, ΔV BE1,2  is the error term due to the base-emitter voltage difference in Q 1  and Q 2 . The base-emitter voltage of Q 1  and Q 2  are 
     
       
           V   BE1   =V   T ·ln( I   1   /I   S ) 
       
     
     
       
           V   BE2   =V   T ·ln( I   2   /I   S ). 
       
     
     Hence, 
     
       
         Δ V   BE1,2   =V   BF1   −V   BE2   =V   T ·ln( I 1     /I 2   )  (4) 
       
     
     The differential stage of Q 7  and Q 8  is a replica of Q 1 -Q 2  differential stage, and hence the output current of Q 7  and Q 8  are the same as those through Q 1  and Q 2 . The base-emitter voltage of Q 9  and Q 10  are 
     
       
           V   BE9   =V   T ·ln( I   1   /I   S ) 
       
     
     
       
           V   BE10   =V   T ·ln( I   2   /I   S ). 
       
     
     Hence, 
     
       
           V   out9,10   =V   BE9   −V   BE10   =V   T ·ln( I   1   /I   2 ). 
       
     
     From Equation (4) above, 
     
       
           V   out9,10   =V   BE1,2   (5) 
       
     
     The voltage in Equation (5) above is applied to the transconductor composed of Q 3 -Q 6 , which cancels the error voltage shown in Equation (4) [see Caprio], and the output current I out2  from Q 5 -Q 6  differential stage is 
     
       
           I   out2   =V   out9,10 /2 R   E   =ΔV   BE1,2 /2 R   E   (6) 
       
     
     In FIG. 7, I out2  is added to I out1 . From Equations (3) and (6) above, the output current of the overall circuit is 
     
       
           I   out   =I   out1   +I   out2 =(V in   −ΔV   BE1,2 )/2 R   E   +ΔV   BE1,2 /2 R   E   =V   in /2 R   E   
       
     
     Output voltage is 
     
       
           V   out   =I   out ·2 R   C   =R   E   /R   C   ·V   in   (7) 
       
     
     Hence the error term in Equation (3) above is completely removed, and the remained output is linear to the input voltage. 
     Intuitively, the error voltage existing in Q 1 -Q 2  pair is replicated at the emitters of Q 9  and Q 10 , which is converted into the equivalent error current in Q 5 -Q 6  pair. The cross connected pair of Q 3  and Q 4  removes the error existing in Q 5 -Q 6  stage, and subtracts the error current from the load resistors Rc. This cross connected differential stage composed of Q 3 -Q 6  is a well-known circuit. 
     The stacking of transistor pairs Q 5 -Q 3  and Q 6 -Q 4  increases the supply voltage. Removing transistors Q 3  and Q 4  will reduce the supply voltage and enable low voltage operation. However, removing transistors Q 3  and Q 4  will cause error in the differential stage Q 5  and Q 6  as described above. Any differential stage without error compensation has error voltage in base-emitter of the transistors as described above. 
     FIG. 8 illustrates a variation of the amplifier of FIG.  7 . In the embodiment of this FIG. 8, the amplifier consists of a first stage  801  and a second stage  802  similar to the second stage  702  of FIG. 7 with an intermediate stage  803 . The intermediate stage  803  is a repeat of the second stage  802  and reduces the error voltage. This intermediate stage  803  may be repeated as many times until the error voltage becomes acceptably small and the linearity in the output reaches an acceptable level. 
     The stage  802  differs from the stage  702  (in FIG. 7) in that the transistors Q 3  and Q 4  from stage  702  have been removed, with the output of the second stage  802  passing through the intermediate stage  803  and providing reduction in the error voltage. 
     When transistors Q 3  and Q 4  are removed from the FIG. 7 embodiment, the circuit with only transistors Q 5  and Q 6  makes for an error voltage which is reduced from the error voltage of stage  801 . In the circuit in FIG. 7, the differential stage composed of Q 3 , Q 4 , Q 5 , and Q 6  requires the supply voltage high. Q 3  and Q 4  are removed in FIG.  8 . However, the differential stage with Q 5  and Q 6  makes error voltage, which is smaller than that in circuit  801 . By using the same error voltage compensation circuit  802 , the error in  802  can be further reduced. The output current I out2  from Q 5 -Q 6  differential stage is 
     
       
           I   out2 =(Δ V   BE1,2   −ΔV   BE5,6 )/2 R   E ,  (8) 
       
     
     |ΔV BE5,6 |&lt;&lt;|ΔV BE1,2 | 
     The circuit of the second stage  802 , which reduces the error voltage, is repeated as the circuit  803  to reduce the error voltage in second stage  802 . The output current I out3  from Q 11 -Q 12  differential stage is 
     
       
           I   out3 =(Δ V   BE5,6   −ΔV   BE11,12 )/2 R   E ,  (9) 
       
     
     |ΔV BE11,12 |&lt;&lt;|ΔV BE5,6 |&lt;&lt;|ΔV BE1,2 | 
     Hence, 
     
       
           I   out   =I   out1   +I   out2   +I   out3 =( V   in   −ΔV   BE11,12 )/2 R   E   (10) 
       
     
     The intermediate stage  803  can be repeated as many times until the ΔV BE  term in Equation (10) above becomes sufficiently small to get the required linearity. 
     The second stage  802  reduces the error voltage and may be repeated as many times as necessary to reduce the error voltage to an acceptable value. In FIG. 8, the stage  803  is a repetition of the stage  802  and provides for a further correction of the error voltage, producing an output current which is equal to the difference in the base to emitter voltage of transistors Q 11  and Q 12  divided by twice the emitter resistor RE. The voltage differential of this stage is much less than the voltage difference of the previous stage  802  which in turn was much less than the voltage differential of the base amplifier  801 . 
     The current output equals the sum of the currents provided by each of the three stages  801 ,  802  and  803 , which equals the input voltage less the voltage differential between base and emitter of the third stage  803  (for resistors Q 11  and Q 12 ) divided by twice the emitter resistor RE, which, as the voltage differential for the third stage approaches zero, means that the distortion is reduced accordingly. The third stage  803  can be repeated as many times as is necessary until the error terms gets sufficiently small to get the required linearity in output amplification. As shown in Equation (10) above, the output current is now the sum of three current components, which will cause more voltage drop in the load resistors Rc, and reduces the common mode voltage of the outputs VOP and VON compared to FIG.  7 . By supplying the current to the output nodes, the additional current component can be compensated, and the common mode voltage at the output can be restored as shown in FIG.  9 . The current sources can be implemented with pMOS transistors as shown in FIG. 10, but those can be implemented with any devices that can form the current sources such as bipolar pnp transistors and MesFET&#39;s. 
     FIG. 9 is an alternate embodiment of the amplifier of FIG. 8 where transistor Q 11  includes current source I 3  and transistor Q 12  includes a current source I 4 . These current sources drive he transistors Q 11  and Q 12  with a uniform current and reduce the influence of the stage  803  on he error correction. 
     FIG. 10 is an alternate embodiment of the amplifier of FIG.  8  and FIG. 9 wherein a pMOS transistor M 1  is associated with the transistor Q 11  and a pMOS transistor M 12  is associated with the transistor Q 12 , with each of the pMOS transistors M 11  and M 12  driven by a supply voltage VGG. This provides a more uniform current supply for the transistors Q 11  and Q 12  in the intermediate stage  803 . 
     Of course, many modifications of the present invention will be apparent to those skilled in the relevant art in view of the foregoing description of the preferred embodiment, taken together with the accompanying drawings and the appended claims. For example, an amplifier using a improved gain such as is shown in FIG. 3 could be combined with the digital inputs of FIG. 6 to provide a digitally-selectable, linear variable gain amplifier having an enhanced gain. Additionally, an amplifier with an emitter degenerated differential stage as shown in FIGS. 7 and 8 could be used with either the digital control inputs of FIG. 6 or with the improved gain amplifier as shown and described in connection with FIGS. 3 and 5. Further, some elements of the present invention can be used to advantage without the corresponding use of other elements. For example, the use of the current source in FIG. 3 could be used with or without the cascode transistors as shown in FIG.  5 . The number of stages chosen in FIG.  6  and FIG. 8 are arbitrary and subject to design choice, as is the size of the elements (particularly resistors which determine the gain). While the description contemplated certain kinds of circuit elements such as FET and MOSFET transistors, those skilled in the art would be aware of other devices which have similar characteristics and which could be substituted in the circuits shown to achieve a similar result. Accordingly, the foregoing description of the preferred embodiment should be considered as merely illustrative of the principles of the present invention and not in limitation thereof.