Abstract:
An evaluation circuit comprises a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay.

Description:
BACKGROUND  
       [0001]     In semiconductor manufacturing, it is difficult to design and build a semiconductor chip having the same process for a positive channel field effect transistor (pFET) or negative channel field effect transistor (nFET) and the same characteristics in every batch of chips. Varying processes and characteristics of semiconductor chips from chip to chip can affect the performance of the semiconductor chip including the electrical behavior, set-up and hold times, off chip driver slew rate, etc. Sometimes these varying processes and characteristics can be so extreme that the semiconductor chip fails to meet specifications.  
         [0002]     A representative pFET or nFET of a semiconductor chip can be tested to determine whether the process for the pFETs and nFETs in the chip are fast (strong) or slow (weak). Based on the test results, action can be taken to offset any undesirable characteristics of the semiconductor chip due to the process. In addition, if an external voltage supplied to the semiconductor chip varies, by determining the variation, action can be taken to adjust for any effects the variation may cause. For example, by evaluating the characteristics of a pFET, nFET, and/or external voltage supplied to the semiconductor chip, an off-chip driver (OCD) on the chip can be adjusted as needed to compensate for any effects due to variations in the characteristics from nominal values.  
       SUMMARY  
       [0003]     One embodiment of the invention provides an evaluation circuit. The evaluation circuit comprises a test circuit configured to provide a test voltage indicative of a characteristic of a semiconductor device, a reference circuit configured to provide a first reference voltage, a first delay circuit configured to convert the test voltage into a first delay, a second delay circuit configured to convert the first reference voltage into a second delay, and a first latching circuit configured to determine a relationship between the first delay and the second delay. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.  
         [0005]      FIG. 1  is a block diagram illustrating one embodiment of a memory system having a voltage/process evaluation circuit.  
         [0006]      FIG. 2  is a block diagram illustrating one embodiment of a voltage/process evaluation circuit.  
         [0007]      FIGS. 3   a  and  3   b  are schematic diagrams illustrating one embodiment of a current starved inverter chain.  
         [0008]      FIG. 4  is a schematic diagram illustrating one embodiment of a latch.  
         [0009]      FIG. 5  is a schematic diagram illustrating one embodiment of a test circuit for evaluating a supplied voltage.  
         [0010]      FIG. 6  is a schematic diagram illustrating one embodiment of a reference circuit for evaluating a supplied voltage.  
         [0011]      FIG. 7  is a block diagram illustrating one embodiment of an evaluation circuit for evaluating a supplied voltage.  
         [0012]      FIG. 8  is a schematic diagram illustrating one embodiment of a test circuit for evaluating the process of a negative channel field effect transistor (nFET).  
         [0013]      FIG. 9  is a schematic diagram illustrating one embodiment of a reference circuit for evaluating the process of an nFET.  
         [0014]      FIG. 10  is a block diagram illustrating one embodiment of an evaluation circuit for evaluating the process of an nFET.  
         [0015]      FIG. 11  is a schematic diagram illustrating one embodiment of a test circuit for evaluating the process of a positive channel field effect transistor (pFET).  
         [0016]      FIG. 12  is a schematic diagram illustrating one embodiment of a reference circuit for evaluating the process of a pFET.  
         [0017]      FIG. 13  is a block diagram illustrating one embodiment of an evaluation circuit for evaluating the process of a pFET.  
         [0018]      FIG. 14  is a schematic diagram illustrating one embodiment of a reference circuit for providing multiple reference signals for evaluating the process of an nFET.  
         [0019]      FIG. 15  is a block diagram illustrating one embodiment of an evaluation circuit having multiple latches for evaluating the process of an nFET.  
         [0020]      FIG. 16  is a schematic diagram illustrating one embodiment of a reference circuit for providing multiple reference signals for evaluating the process of a pFET.  
         [0021]      FIG. 17  is a block diagram illustrating one embodiment of an evaluation circuit having multiple latches for evaluating the process of a pFET. 
     
    
     DETAILED DESCRIPTION  
       [0022]      FIG. 1  is a block diagram illustrating one embodiment of a memory system  100  having a voltage/process evaluation circuit. Memory system  100  includes a semiconductor chip  102  and a memory device  106 . Semiconductor chip  102  is electrically coupled to memory device  106  through path  104 . Semiconductor chip  102  includes voltage/process evaluation circuit  108  and off chip driver (OCD) circuit  112 . Voltage/process evaluation circuit  108  is electrically coupled to OCD  112  through path  110 . In one embodiment, semiconductor chip  102  includes a receiver circuit, generator circuit, a set up and hold time adjustment circuit, or any other suitable circuit. In one embodiment, memory device  106  and semiconductor chip  102  are a single semiconductor chip.  
         [0023]     Voltage/process evaluation circuit  108  evaluates the incoming voltage supplied to chip  102  and the process of a negative channel field effect transistor (nFET) and a positive channel field effect transistor (pFET) in chip  102 . The nFET and pFET that are evaluated are representative of all the nFETs and pFETs in chip  102 . The evaluation results are passed to portions of OCD  112  through path  110 . Based on the evaluation results, portions of OCD  112  are adjusted such that chip  102  meets specified specifications.  
         [0024]     Voltage/process evaluation circuit  108  utilizes a number of circuits to perform the evaluations. A test circuit is used to evaluate the external voltage supplied to chip  102 . The supplied voltage is converted into a delayed clock signal, where the delay is proportional to the value of the supplied voltage. A reference voltage representing a nominal value for the supplied voltage is also converted into a delayed clock signal, where the delay is proportional to the value of the reference voltage. The delay proportional to the supplied voltage is compared to the delay proportional to the reference voltage to compare the supplied voltage to the reference voltage.  
         [0025]     Voltage/process evaluation circuit  108  also includes test circuits to evaluate the processes for the nFETs and pFETs in chip  102 . The test circuits provide test voltages indicative of the processes for the FETs. The test voltages are converted into delayed clock signals, where the delays are proportional to the values of the test voltages. Reference voltages representing nominal values for the test voltages are also converted into delayed clock signals, where the delays are proportional to the reference voltages. The delays proportional to the FET processes are compared to the delays proportional to the reference voltages to compare the processes for the FETS to the reference values.  
         [0026]     By converting the test voltages and reference voltages to delays rather than comparing them directly using comparators, power is conserved and process detection and evaluation is completed more quickly than if comparators were used. This voltage and process evaluation can occur each time chip  102  is reset or whenever desired.  
         [0027]     Memory device  106  includes a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM, or other suitable memory. Memory device  106  communicates with chip  102  through path  104 .  
         [0028]      FIG. 2  is a block diagram illustrating one embodiment of voltage/process evaluation circuit  108 . Voltage/process evaluation circuit  108  includes test circuits  124  and  150 , reference circuits  132  and  142 , inverter chains  128 ,  136 ,  146 , and  154 , and latch  140 .  
         [0029]     Test circuit  124  is electrically coupled to internal voltage (V INT ) signal path  120  and inverter chain  128  through signal path  126 . Inverter chain  128  is electrically coupled to inverter chain  146  through clock (CLK) signal path  122  and inverter chain  136  through signal path  130 . Inverter chain  136  is electrically coupled to reference circuit  132  through signal path  134  and latch  140  through signal path  138 . Reference circuit  132  is electrically coupled to V INT  signal path  120 . Inverter chain  146  is electrically coupled to reference circuit  142  through signal path  144  and inverter chain  154  through signal path  148 . Reference circuit  142  is electrically coupled to V INT  signal path  120 . Inverter chain  154  is electrically coupled to test circuit  150  through signal path  152  and latch  140  through signal path  156 . Test circuit  150  is electrically coupled to V INT  signal path  120 . Latch  140  is electrically coupled to latch data one (D 1 ) signal path  158  and latch data two (D 2 ) signal path  160 . In one embodiment, inverter chains  128 ,  136 ,  146 , and  154  are current starved inverter chains.  
         [0030]     The V INT  signal is a voltage signal supplied by an external voltage source, internal voltage source, or other suitable voltage source. Test circuit  124  receives the V INT  signal on V INT  signal path  120  as an input and outputs a test voltage proportional to VINT to inverter chain  128  through signal path  126 . The test voltage is received by inverter chain  128  and controls inverter chain  128 . Inverter chain  128  receives the CLK signal through CLK signal path  122  as an input. Based on the test voltage received from test circuit  124 , the CLK signal is delayed as it propagates through inverter chain  128 . Inverter chain  128  outputs a delayed clock signal, which is proportional to the test voltage received from test circuit  124 , to inverter chain  136  through signal path  130 .  
         [0031]     Reference circuit  142  receives the V INT  voltage on V INT  signal path  120  as an input and outputs a reference voltage to inverter chain  146  through signal path  144 . In one embodiment, the reference voltage is a nominal voltage for the test voltage. The reference voltage is received by inverter chain  146  and controls inverter chain  146 . Inverter chain  146  receives the CLK signal through CLK signal path  122  as an input. Based on the reference voltage received from reference circuit  142 , the CLK signal is delayed as it propagates through inverter chain  146 . Inverter chain  146  outputs a delayed clock signal, which is proportional to the reference voltage received from reference circuit  142 , to inverter chain  154  through signal path  148 .  
         [0032]     Reference circuit  132  receives the V INT  signal on V INT  signal path  120  as an input and outputs a reference voltage to inverter chain  136  through signal path  134 . In one embodiment, the reference voltage is a voltage indicating a nominal process for either an nFET or pFET. The reference voltage is received by inverter chain  136  and controls inverter chain  136 . Inverter chain  136  receives the delayed clock signal from inverter chain  128  through signal path  130  as an input. Based on the reference voltage received from reference circuit  132 , the delayed clock signal is further delayed as it propagates through inverter chain  136 . Inverter chain  136  outputs a delayed clock signal, which is proportional to both the test voltage received from test circuit  124  and the reference voltage received from reference circuit  132 , to latch  140  through signal path  138 .  
         [0033]     Test circuit  150  receives the V INT  signal on V INT  signal path  120  as an input and outputs a test voltage to inverter chain  154  through signal path  152 . In one embodiment, the test voltage is indicative of the process for a pFET or nFET. The test voltage is received by inverter chain  154  and controls inverter chain  154 . Inverter chain  154  receives the delayed clock signal from inverter chain  146  through signal path  148  as an input. Based on the test voltage received from test circuit  150 , the delayed clock signal is further delayed as it propagates through inverter chain  154 . Inverter chain  154  outputs a delayed clock signal, which is proportional to both the reference voltage received from reference circuit  142  and the test voltage received from test circuit  152 , to latch  140  through signal path  156 .  
         [0034]     Latch  140  receives the delayed clock signal from inverter chain  136  through signal path  138  and the delayed clock signal from inverter chain  154  through signal path  156 . If the rising edge of the delayed clock signal on signal path  138  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  156 , latch  140  outputs a logic high level signal on D 1  signal path  158  and a logic low level signal on D 2  signal path  160 . If the rising edge of the delayed clock signal on signal path  156  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  138 , latch  140  outputs a logic low level signal on D 1  signal path  158  and a logic high level signal on D 2  signal path  160 . Latch  140  maintains the output signals on D 1  signal path  158  and D 2  signal path  160  until another evaluation is performed.  
         [0035]     The length of inverter chains  128 ,  136 ,  146 , and  154  are set such that the effect of the supplied voltage and the process of an nFET or pFET on semiconductor chip  102  can be balanced for evaluation.  
         [0036]      FIGS. 3   a  and  3   b  are schematic diagrams illustrating one embodiment of current starved inverter chain  128 . Inverter chains  136 ,  146 , and  154  are similar to inverter chain  128 . As illustrated in  FIG. 3   a , inverter chain  128  includes inverters  200   a - 200 ( n ). The CLK signal on CLK signal path  122  is electrically coupled to the input of inverter  200   a . The output of inverter  200   a  is electrically coupled to the input of inverter  200   b  through path  202   a . The output of inverter  200   b  is electrically coupled to the next inverter in inverter chain  128  through path  202   b , etc., until the input of the last inverter  200 ( n ) in inverter chain  128  is coupled to the output of the previous inverter in inverter chain  128 . The output of inverter  200 ( n ) is electrically coupled to path  202 ( n ), which is the same as signal path  130 . The controlling inputs of inverters  200   a - 200 ( n ) are electrically coupled to signal path  126 . The length of inverter chain  128  is based on the desired length of the delay for the CLK signal. The CLK signal on CLK signal path  122  is delayed as it propagates through each inverter  200   a - 200 ( n ) in proportion to the test voltage on signal path  126 .  
         [0037]      FIG. 3   b  illustrates inverter chain  128  in more detail. Inverter  200   a  includes transistors  214   a ,  216   a , and  220   a . Inverter  200   b  includes transistors  214   b ,  216   b , and  220   b . Inverter  200 ( n ) includes transistors  214 ( n ),  216 ( n ), and  220 ( n ). Transistors  214   a - 214 ( n ) are pFETs and transistors  216   a - 216 ( n ) and  220   a - 220 ( n ) are nFETs.  
         [0038]     V INT    320  is electrically coupled to one side of the source-drain path of transistor  214   a  through path  212   a . The other side of the source-drain path of transistor  214   a  is electrically coupled to one side of the source-drain path of transistor  216   a  and the gates of transistors  214   b  and  216   b  through path  202   a . The gate of transistor  214   a  and the gate of transistor  216   a  are electrically coupled to CLK signal path  122 . The other side of the source-drain path of transistor  216   a  is electrically coupled to one side of the source-drain path of transistor  220   a  through path  218   a . The other side of the source-drain path of transistor  220   a  is electrically coupled to ground or common  224  through path  222   a . The gate of transistor  220   a  is electrically coupled to the gates of transistors  220   b - 220 ( n ) through signal path  126 .  
         [0039]     V INT    320  is electrically coupled to one side of the source-drain path of transistor  214   b  through path  212   b . The other side of the source-drain path of transistor  214   b  is electrically coupled to one side of the source-drain path of transistor  216   b  and the gates of the next transistor  214  and transistor  216  in inverter chain  128 . The other side of the source-drain path of transistor  216   b  is electrically coupled to one side of the source-drain path of transistor  220   b  through path  218   b . The other side of the source-drain path of transistor  220   b  is electrically coupled to ground or common  224  through path  222   b.    
         [0040]     V INT    320  is electrically coupled to one side of the source-drain path of transistor  214 ( n ) through path  212 ( n ). The other side of the source-drain path of transistor  214 ( n ) is electrically coupled to signal path  202 ( n ), which is the same as signal path  130 , and one side of the source-drain source path of transistor  216 ( n ). The other side of the source-drain path of transistor  216 ( n ) is electrically coupled to one side of the source-drain path of transistor  220 ( n ) through path  218 ( n ). The other side of the source-drain path of transistor  220 ( n ) is electrically coupled to common or ground  224  through path  222 ( n ).  
         [0041]     Inverters  200   a - 200 ( n ) are current starved inverters controlled by the test voltage from test circuit  124  through signal path  126 . The CLK signal on CLK signal path  122  is delayed as it propagates through inverters  200   a - 200 ( n ). The delay of the CLK signal through inverters  200   a - 200 ( n ) is proportional to the test voltage on signal path  126  applied to the gates of transistors  220   a - 220 ( n ). Inverter chains  136 ,  146 , and  154  operate in a similar manner as inverter chain  128 .  
         [0042]      FIG. 4  is a schematic diagram illustrating one embodiment of latch  140 . Latch  140  includes NAND gates  300 ,  304 ,  306 , and  310 . One input of NAND gate  300  is electrically coupled to signal path  138  and the other input of NAND gate  300  is electrically coupled to the output of NAND gate  306  and one input of NAND gate  310  through path  308 . The output of NAND gate  300  is electrically coupled to one input of NAND gate  304  and one input of NAND gate  306  through path  302 . The other input of NAND gate  306  is electrically coupled to signal path  156 . The output of NAND gate  304  is electrically coupled to the other input of NAND gate  310  through D 1  signal path  158 . The output of NAND gate  310  is electrically coupled to the other input of NAND gate  304  through D 2  signal path  160 .  
         [0043]     In operation, if a rising edge of the delayed clock signal on signal path  138  arrives to the input of NAND gate  300  before a rising edge of the delayed clock signal on signal path  156  arrives to the input of NAND gate  306 , the output on D 1  signal path  158  transitions to a logic high level and the output on D 2  signal path  160  transitions to a logic low level. If a rising edge of the delayed clock signal on signal path  156  arrives to the input of NAND gate  306  before a rising edge of the delayed clock signal on signal path  138  arrives to the input of NAND gate  300 , the output on D 2  signal path  160  transitions to a logic high level and the output on D 1  signal path  158  transitions to a logic low level. The signals on D 1  signal path  158  and D 2  signal path  160  will remain constant until another evaluation is performed.  
         [0044]      FIG. 5  is a schematic diagram illustrating one embodiment of test circuit  124  for evaluating a supplied voltage. Test circuit  124  includes resistor  322  and resistor  324 . Resistor  322  is electrically coupled to V INT    320  through path  321  and resistor  324  through divided voltage (V DIV ) signal path  126 . Resistor  324  is electrically coupled to common or ground  224  through path  326 .  
         [0045]     In operation, test circuit  124  receives the V INT  signal, which is supplied by an external circuit to semiconductor chip  102 , and divides the V INT  between resistor  322  and  324 . Test circuit  124  outputs the V DIV  signal on signal path  126  to inverter chain  128 . The V DIV  signal is proportional to the V INT  signal.  
         [0046]      FIG. 6  is a schematic diagram illustrating one embodiment of reference circuit  142  for evaluating a supplied voltage. Reference circuit  142  includes voltage source  328 . Voltage source  328  is electrically coupled to reference voltage (V REF ) signal path  144  and common or ground  224  through path  330 . Reference circuit  142  provides a reference voltage, V REF , which indicates a nominal value for the supplied voltage for comparison to the V DIV  signal from test circuit  124 .  
         [0047]      FIG. 7  is a block diagram illustrating one embodiment of an evaluation circuit  331  for evaluating a supplied voltage. Supplied voltage evaluation circuit  331  includes test circuit  124 , reference circuit  142 , inverter chains  128  and  146 , and latch  140 . Test circuit  124  is electrically coupled to V INT  signal path  120  and inverter chain  128  through V DIV  signal path  126 . Reference circuit  142  is electrically coupled to V INT  signal path  120  and inverter chain  146  through V REF  signal path  144 . Clock signal path  122  is electrically coupled to inverter chain  128  and inverter chain  146 . Latch  140  is electrically coupled to inverter chain  128  through signal path  332 , inverter chain  146  through signal path  334 , D 1  signal path  158 , and D 2  signal path  160 . Signal path  332  is similar to signal path  138  and signal path  334  is similar to signal path  156  of latch  140  illustrated in  FIG. 4 .  
         [0048]     Test circuit  124  receives the V INT  signal on V INT  signal path  120  as an input and outputs the V DIV  signal to inverter chain  128  through signal path  126 . The V DIV  signal is received by inverter chain  128  and controls inverter chain  128 . Inverter chain  128  receives the CLK signal through CLK signal path  122  as an input. Based on the V DIV  signal received from test circuit  124 , the CLK signal is delayed as it propagates through inverter chain  128 . Inverter chain  128  outputs a delayed clock signal, which is proportional to the V DIV  signal received from test circuit  124 , to latch  140  through signal path  332 .  
         [0049]     Reference circuit  142  receives the V INT  voltage on V INT  signal path  120  as an input and outputs the V REF  signal to inverter chain  146  through signal path  144 . In one embodiment, the V REF  signal is a nominal voltage for the V DIV  signal. The V REF  signal is received by inverter chain  146  and controls inverter chain  146 . Inverter chain  146  receives the CLK signal through CLK signal path  122  as an input. Based on the V REF  signal received from reference circuit  142 , the CLK signal is delayed as it propagates through inverter chain  146 . Inverter chain  146  outputs a delayed clock signal, which is proportional to the V REF  signal received from reference circuit  142 , to latch  140  through path  334 .  
         [0050]     Latch  140  receives the delayed clock signal from inverter chain  128  through signal path  332  and the delayed clock signal from inverter chain  146  through signal path  334 . If the rising edge of the delayed clock signal on signal path  332  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  334 , latch  140  outputs a logic high level signal on D 1  signal path  158  and a logic low level signal on D 2  signal path  160 . If the rising edge of the delayed clock signal on signal path  334  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  332 , latch  140  outputs a logic low level signal on D 1  signal path  158  and a logic high level signal on D 2  signal path  160 . Latch  140  maintains the output signals on D 1  signal path  158  and D 2  signal path  160  until another evaluation is performed.  
         [0051]     If V DIV  is greater than V REF , which indicates the supplied voltage is greater than the nominal voltage, then a logic high level signal is latched on D 1  signal path  158  and a logic low level signal is latched on D 2  signal path  160 . If V DIV  is less than V REF , which indicates the supplied voltage is less than the nominal voltage, then a logic low level signal is latched on D 1  signal path  158  and a logic high level signal is latched on D 2  signal path  160 .  
         [0052]      FIG. 8  is a schematic diagram illustrating one embodiment of test circuit  150 , indicated as test circuit  150   a , for evaluating the process of an nFET. Test circuit  150   a  includes resistor  342 , transistor  344 , and voltage source  348 . Transistor  344  is an nFET. Resistor  342  is electrically coupled to VINT  320  through path  340  and one side of the source-drain path of transistor  344  through V nM  signal path  152   a . The other side of the source-drain path of transistor  344  is electrically coupled to common or ground  224  through path  352 . The gate of transistor  344  is electrically coupled to voltage source  348  through path  346 . Voltage source  348  is electrically coupled to common or ground  224  through path  350 .  
         [0053]     Voltage source  348  provides a voltage to the gate of transistor  344  to turn transistor  344  on (conducting). V INT  voltage  320  is divided between resistor  342  and the source-drain path of transistor  344  to output a voltage, V nM , on V nM  signal path  152   a . The V nM  voltage on V nM  signal path  142   a  is indicative of the process for transistor  344 . Transistor  344  is representative of all nFET transistors of semiconductor chip  102 .  
         [0054]      FIG. 9  is a schematic diagram illustrating one embodiment of reference circuit  132 , indicated as reference circuit  132   a , for evaluating the process of an nFET. Reference circuit  132   a  includes resistor  362  and current source  364 . Resistor  362  is electrically coupled to V INT    320  through path  360  and current source  364  through V nR  signal path  134   a . Current source  364  is electrically coupled to common or ground  224  through path  366 . The resistance of resistor  362  is substantially equal to the resistance of resistor  342 .  
         [0055]     Reference circuit  134   a  provides a reference voltage output on V nR  signal path  134   a  for comparison to the V nM  voltage on signal path  152   a . The voltage on V nR  signal path  134   a  indicates a nominal process for transistor  344 .  
         [0056]      FIG. 10  is a block diagram illustrating one embodiment of an evaluation circuit  368  for evaluating the process for nFET  344 . Evaluation circuit  368  includes reference circuit  132   a , test circuit  150   a , inverter chains  136   a  and  154   a , and latch  140 . Reference circuit  132   a  is electrically coupled to V INT  signal path  120  and inverter chain  136   a  through V nR  signal path  134   a . Test circuit  150   a  is electrically coupled to VINT signal path  120  and inverter chain  154   a  through V nM  signal path  152   a . Clock signal path  122  is electrically coupled to inverter chain  136   a  and inverter chain  154   a . Latch  140  is electrically coupled to inverter chain  136   a  through signal path  138   a , inverter chain  154   a  through signal path  156   a , D 1  signal path  158 , and D 2  signal path  160 .  
         [0057]     Reference circuit  132   a  receives the V INT  voltage on V INT  signal path  120  as an input and outputs the V nR  signal to inverter chain  136   a  through signal path  134   a . In one embodiment, the V nR  signal is a nominal voltage for the V nM  signal. The V nR  signal is received by inverter chain  136   a  and controls inverter chain  136   a . Inverter chain  136   a  receives the CLK signal through CLK signal path  122  as an input. Based on the V nR  signal received from reference circuit  132   a , the CLK signal is delayed as it propagates through inverter chain  136   a . Inverter chain  136   a  outputs a delayed clock signal, which is proportional to the V nR  signal received from reference circuit  132   a , to latch  140  through signal path  138   a.    
         [0058]     Test circuit  150   a  receives the V INT  signal on V INT  signal path  120  as an input and outputs the V nM  signal to inverter chain  154   a  through signal path  152   a . The V nM  signal is received by inverter chain  154   a  and controls inverter chain  154   a . Inverter chain  154   a  receives the CLK signal through CLK signal path  122  as an input. Based on the V nM  signal received from test circuit  150   a , the CLK signal is delayed as it propagates through inverter chain  154   a . Inverter chain  154   a  outputs a delayed clock signal, which is proportional to the V nM  signal received from test circuit  150   a , to latch  140  through signal path  156   a.    
         [0059]     Latch  140  receives the delayed clock signal from inverter chain  136   a  through signal path  138   a  and the delayed clock signal from inverter chain  154   a  through signal path  156   a . If the rising edge of the delayed clock signal on signal path  138   a  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  156   a , latch  140  outputs a logic high level signal on D 1  signal path  158  and a logic low level signal on D 2  signal path  160 . If the rising edge of the delayed clock signal on signal path  156   a  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  138   a , latch  140  outputs a logic low level signal on D 1  signal path  158  and a logic high level signal on D 2  signal path  160 . Latch  140  maintains the output signals on D 1  signal path  158  and D 2  signal path  160  until another evaluation is performed.  
         [0060]     If V nM  is greater than V nR , which indicates the process of nFET  344  is slower than nominal, then a logic low level signal is latched on D 1  signal path  158  and a logic high level signal is latched on D 2  signal path  160 . If V nM  is less than V nR , which indicates the process of nFET  344  is faster than nominal, then a logic high level signal is latched on D 1  signal path  158  and a logic low level signal is latched on D 2  signal path  160 .  
         [0061]      FIG. 11  is a schematic diagram illustrating another embodiment of a test circuit  150 , indicated as test circuit  150   b , for evaluating the process of a pFET. Test circuit  150   b  includes voltage source  402 , transistor  408 , and resistor  410 . Transistor  408  is a pFET. Voltage source  402  is electrically coupled to V INT    320  through path  400  and the gate of transistor  408  through path  404 . One side of the source-drain path of transistor  408  is electrically coupled to V INT    320  through path  406 . The other side of the source-drain path of transistor  408  is electrically coupled to resistor  410  thorough V pM  signal path  152   b . Resistor  410  is electrically coupled to common or ground  224  through path  412 .  
         [0062]     Voltage source  402  provides a voltage to the gate of transistor  408  to turn transistor  408  on (conducting). V INT    320  is divided between the source-drain path of transistor  408  and resistor  410  to output a voltage V pM , on V pM  signal path  152   b . The V pM  voltage on V pM  signal path  152   b  is indicative of the process for transistor  408 . Transistor  408  is representative of all pFET transistors of semiconductor chip  102 .  
         [0063]      FIG. 12  is a schematic diagram illustrating another embodiment of reference circuit  132 , indicated as reference circuit  132   b , for evaluating the process of a pFET. Reference circuit  132   b  includes current source  422  and resistor  424 . Current source  422  is electrically coupled to V INT    320  through path  420  and resistor  424  through V pR  signal path  134   b . Resistor  424  is electrically coupled to common or ground  224  through path  426 . The resistance of resistor  424  is substantially equal to the resistance of resistor  410 .  
         [0064]     Reference circuit  132   b  provides a reference voltage output on V pR  signal path  134   b  for comparison to the V pM  voltage on signal path  152   b . The voltage on V pR  signal path  134   b  indicates a nominal process for transistor  408 .  
         [0065]      FIG. 13  is a block diagram illustrating one embodiment of an evaluation circuit  428  for evaluating the process for pFET  408 . Evaluation circuit  428  includes reference circuit  132   b , test circuit  150   b , inverter chains  136   b  and  154   b , and latch  140 .  
         [0066]     Reference circuit  132   b  is electrically coupled to V INT  signal path  120  and inverter chain  136   b  through V pR  signal path  134   b . Test circuit  150   b  is electrically coupled to V INT  signal path  120  and inverter chain  154   b  through V pM  signal path  152   b . CLK signal path  122  is electrically coupled to inverter chain  134   b  and inverter chain  154   b . Latch  140  is electrically coupled to inverter chain  136   b  through signal path  138   b , inverter chain  154   b  through signal path  156   b , D 1  signal path  158 , and D 2  signal path  160 .  
         [0067]     Reference circuit  132   b  receives the V INT  voltage on V INT  signal path  120  as an input and outputs the V pR  signal to inverter chain  136   b  through signal path  134   b . In one embodiment, the V pR  signal is a nominal voltage for the V pM  signal. The V pR  signal is received by inverter chain  136   b  and controls inverter chain  136   b . Inverter chain  136   b  receives the CLK signal through CLK signal path  122  as an input. Based on the V pR  signal received from reference circuit  132   b , the CLK signal is delayed as it propagates through inverter chain  136   b . Inverter chain  136   b  outputs a delayed clock signal, which is proportional to the V pR  signal received from reference circuit  132   b , to latch  140  through signal path  138   b.    
         [0068]     Test circuit  150   b  receives the V INT  signal on V INT  signal path  120  as an input and outputs the V pM  signal to inverter chain  154   b  through signal path  152   b . The V pM  signal is received by inverter chain  154   b  and controls inverter chain  154   b . Inverter chain  154   b  receives the CLK signal through CLK signal path  122  as an input. Based on the V pM  signal received from test circuit  150   b , the CLK signal is delayed as it propagates through inverter chain  154   b . Inverter chain  154   b  outputs a delayed clock signal, which is proportional to the V pM  signal received from test circuit  150   b , to latch  140  through signal path  156   b.    
         [0069]     Latch  140  receives the delayed clock signal from inverter chain  136   b  through signal path  138   b  and the delayed clock signal from inverter chain  154   b  through signal path  156   b . If the rising edge of the delayed clock signal on signal path  138   b  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  156   b , latch  140  outputs a logic high level signal on D 1  signal path  158  and a logic low level signal on D 2  signal path  160 . If the rising edge of the delayed clock signal on signal path  156   b  arrives to the input of latch  140  before the rising edge of the delayed clock signal on signal path  138   b , latch  140  outputs a logic low level signal on D 1  signal path  158  and a logic high level signal on D 2  signal path  160 . Latch  140  maintains the output signals on D 1  signal path  158  and D 2  signal path  160  until another evaluation is performed.  
         [0070]     If V pM  is greater than V pR , which indicates the process of pFET  408  is faster than nominal, then a logic low level signal is latched on D 1  signal path  158  and a logic high level signal is latched on D 2  signal path  160 . If V pM  is less than V pR , which indicates the process of pFET  408  is slower than nominal, then a logic high level signal is latched on D 1  signal path  158  and a logic low level signal is latched on D 2  signal path  160 .  
         [0071]      FIG. 14  is a schematic diagram illustrating one embodiment of a reference circuit  500  for providing multiple reference signals for evaluating the process of an nFET. Reference circuit  500  includes resistors  502 ,  506 ,  510 , and  514 , and current source  518 . Resistor  502  is electrically coupled to V INT    320  through path  501  and resistor  506  through slowest process nFET reference voltage (V nRSS ) signal path  504 . Resistor  506  is electrically coupled to resistor  510  through slow process nFET reference voltage (V nRS ) signal path  508 . Resistor  510  is electrically coupled to resistor  514  through fast process nFET reference voltage (V nRF ) signal path  512 . Resistor  514  is electrically coupled to current source  518  through fastest process nFET reference voltage (V nRFF ) signal path  516 . Current source  518  is electrically coupled to common or ground  224  through path  520 . The sum of the resistances of resistors  502 ,  506 ,  510 , and  514  is substantially equal to the resistance of resistor  342 .  
         [0072]     Reference circuit  500  provides four reference voltages to compare to V nM  from test circuit  150   a . V nRSS  indicates the slowest process for nFET  344 . V nRS  indicates a slow process for nFET  344 , but faster than V nRSS . V nRF  indicates a fast process for nFET  344  and V nRFF  indicates the fastest process for nFET  344 . In other embodiments, reference circuit  500  includes more than four resistors to provide more than four reference voltages. Any suitable number of resistors to provide any suitable number of reference voltages can be provided.  
         [0073]      FIG. 15  is a block diagram illustrating one embodiment of an evaluation circuit  521  having multiple latches for evaluating the process for nFET  344 . Process evaluation circuit  521  includes inverter chains  522 ,  526 ,  542 ,  546 ,  562 ,  566 ,  582 , and  586 , and latches  530 ,  550 ,  570 , and  590 . In one embodiment, inverter chains  526 ,  546 ,  566 , and  586 , are replaced with a single inverter chain having an output coupled to latches  530 ,  550 ,  570 , and  590 . Inverter chains  522 ,  526 ,  542 ,  546 ,  562 ,  566 ,  582 , and  586  are similar to inverter chain  128 . Latches  530 ,  550 ,  570 , and  590  are similar to latch  140 .  
         [0074]     Inverter chain  522  is electrically coupled to V nRSS  signal path  504 , CLK signal path  122 , and latch  530  through signal path  524 . Inverter chain  526  is electrically coupled to V nM  signal path  152   a , CLK signal path  122 , and latch  530  through signal path  528 . Latch  530  is electrically coupled to nFET latch A data one (D n 1a) signal path  532  and nFET latch A data two (D n 2a) signal path  534 .  
         [0075]     Inverter chain  542  is electrically coupled to V nRS  signal path  508 , CLK signal path  122 , and latch  550  through signal path  544 . Inverter chain  546  is electrically coupled to V nM  signal path  152   a , CLK signal path  122 , and latch  550  through signal path  548 . Latch  550  is electrically coupled to nFET latch B data one (D n 1b) signal path  552  and nFET latch B data two (D n 2b) signal path  554 .  
         [0076]     Inverter chain  562  is electrically coupled to V nRF  signal path  512 , CLK signal path  122 , and latch  570  through signal path  564 . Inverter chain  556  is electrically coupled to V nM  signal path  152   a , CLK signal path  122 , and latch  570  through signal path  568 . Latch  570  is electrically coupled to nFET latch C data one (D n 1c) signal path  572  and nFET latch C data two (D n 2c) signal path  574 .  
         [0077]     Inverter chain  582  is electrically coupled to V nRFF  signal path  516 , CLK signal path  122 , and latch  590  through signal path  584 . Inverter chain  586  is electrically coupled to V nM  signal path  152   a , CLK signal path  122 , and latch  590  through signal path  588 . Latch  590  is electrically coupled to nFET latch D data one (D n 1d) signal path  592  and nFET latch D data two (D n 2d) signal path  594 .  
         [0078]     Reference circuit  500  outputs the V nRSS  signal to inverter chain  522  through signal path  504 . The V nRSS  signal is received by inverter chain  522  and controls inverter chain  522 . Inverter chain  522  receives the CLK signal through CLK signal path  122  as an input. Based on the V nRSS  signal received from reference circuit  500 , the CLK signal is delayed as it propagates through inverter chain  522 . Inverter chain  522  outputs a delayed clock signal, which is proportional to the V nRSS  signal received from reference circuit  500 , to latch  530  through signal path  524 .  
         [0079]     Test circuit  150   a  outputs the V nM  signal to inverter chain  526  through signal path  152   a . The V nM  signal is received by inverter chain  526  and controls inverter chain  526 . Inverter chain  526  receives the CLK signal through CLK signal path  122  as an input. Based on the V nM  signal received from test circuit  150   a , the CLK signal is delayed as it propagates through inverter chain  526 . Inverter chain  526  outputs a delayed clock signal, which is proportional to the V nM  signal received from test circuit  150   a , to latch  530  through signal path  528 .  
         [0080]     Latch  530  receives the delayed clock signal from inverter chain  522  through signal path  524  and the delayed clock signal from inverter chain  526  through signal path  528 . If the rising edge of the delayed clock signal on signal path  524  arrives to the input of latch  530  before the rising edge of the delayed clock signal on signal path  528 , latch  530  outputs a logic high level signal on D n 1a signal path  532  and a logic low level signal on D n 2a signal path  534 . If the rising edge of the delayed clock signal on signal path  528  arrives to the input of latch  530  before the rising edge of the delayed clock signal on signal path  524 , latch  530  outputs a logic low level signal on D n 1a signal path  532  and a logic high level signal on D n 2a signal path  534 . Latch  530  maintains the output signals on D n 1a signal path  532  and D n 2a signal path  534  until another evaluation is performed.  
         [0081]     Reference circuit  500  outputs the V nRS  signal to inverter chain  542  through signal path  508 . The V nRS  signal is received by inverter chain  542  and controls inverter chain  542 . Inverter chain  542  receives the CLK signal through CLK signal path  122  as an input. Based on the V nRS  signal received from reference circuit  500 , the CLK signal is delayed as it propagates through inverter chain  542 . Inverter chain  542  outputs a delayed clock signal, which is proportional to the V nRS  signal received from reference circuit  500 , to latch  550  through signal path  544 .  
         [0082]     Test circuit  150   a  outputs the V nM  signal to inverter chain  546  through signal path  152   a . The V nM  signal is received by inverter chain  546  and controls inverter chain  546 . Inverter chain  546  receives the CLK signal through CLK signal path  122  as an input. Based on the V nM  signal received from test circuit  150   a , the CLK signal is delayed as it propagates through inverter chain  546 . Inverter chain  546  outputs a delayed clock signal, which is proportional to the V nM  signal received from test circuit  150   a , to latch  550  through signal path  548 .  
         [0083]     Latch  550  receives the delayed clock signal from inverter chain  542  through signal path  544  and the delayed clock signal from inverter chain  546  through signal path  548 . If the rising edge of the delayed clock signal on signal path  544  arrives to the input of latch  550  before the rising edge of the delayed clock signal on signal path  548 , latch  550  outputs a logic high level signal on D n 1b signal path  552  and a logic low level signal on D n 2b signal path  554 . If the rising edge of the delayed clock signal on signal path  548  arrives to the input of latch  550  before the rising edge of the delayed clock signal on signal path  544 , latch  550  outputs a logic low level signal on D n 1b signal path  552  and a logic high level signal on D n 2b signal path  554 . Latch  550  maintains the output signals on D n 1b signal path  552  and D n 2b signal path  554  until another evaluation is performed.  
         [0084]     Reference circuit  500  outputs the V nRF  signal to inverter chain  562  through signal path  512 . The V nRF  signal is received by inverter chain  562  and controls inverter chain  562 . Inverter chain  562  receives the CLK signal through CLK signal path  122  as an input. Based on the V nRF  signal received from reference circuit  500 , the CLK signal is delayed as it propagates through inverter chain  562 . Inverter chain  562  outputs a delayed clock signal, which is proportional to the V nRF  signal received from reference circuit  500 , to latch  570  through signal path  564 .  
         [0085]     Test circuit  150   a  outputs the V nM  signal to inverter chain  566  through signal path  152   a . The V nM  signal is received by inverter chain  566  and controls inverter chain  566 . Inverter chain  566  receives the CLK signal through CLK signal path  122  as an input. Based on the V nM  signal received from test circuit  150   a , the CLK signal is delayed as it propagates through inverter chain  566 . Inverter chain  566  outputs a delayed clock signal, which is proportional to the V nM  signal received from test circuit  150   a , to latch  570  through signal path  568 .  
         [0086]     Latch  570  receives the delayed clock signal from inverter chain  562  through signal path  564  and the delayed clock signal from inverter chain  566  through signal path  568 . If the rising edge of the delayed clock signal on signal path  564  arrives to the input of latch  570  before the rising edge of the delayed clock signal on signal path  568 , latch  570  outputs a logic high level signal on D n 1c signal path  572  and a logic low level signal on D n 2c signal path  574 . If the rising edge of the delayed clock signal on signal path  568  arrives to the input of latch  570  before the rising edge of the delayed clock signal on signal path  564 , latch  570  outputs a logic low level signal on D n 1c signal path  572  and a logic high level signal on D n 2c signal path  574 . Latch  570  maintains the output signals on D n 1c signal path  572  and D n 2c signal path  574  until another evaluation is performed.  
         [0087]     Reference circuit  500  outputs the V nRFF  signal to inverter chain  582  through signal path  516 . The V nRFF  signal is received by inverter chain  582  and controls inverter chain  582 . Inverter chain  582  receives the CLK signal through CLK signal path  122  as an input. Based on the V nRFF  signal received from reference circuit  500 , the CLK signal is delayed as it propagates through inverter chain  582 . Inverter chain  582  outputs a delayed clock signal, which is proportional to the V nRFF  signal received from reference circuit  500 , to latch  590  through signal path  584 .  
         [0088]     Test circuit  150   a  outputs the V nM  signal to inverter chain  586  through signal path  152   a . The V nM  signal is received by inverter chain  586  and controls inverter chain  586 . Inverter chain  586  receives the CLK signal through CLK signal path  122  as an input. Based on the V nM  signal received from test circuit  150   a , the CLK signal is delayed as it propagates through inverter chain  586 . Inverter chain  586  outputs a delayed clock signal, which is proportional to the V nM  signal received from test circuit  150   a , to latch  590  through signal path  588 .  
         [0089]     Latch  590  receives the delayed clock signal from inverter chain  582  through signal path  584  and the delayed clock signal from inverter chain  586  through signal path  588 . If the rising edge of the delayed clock signal on signal path  584  arrives to the input of latch  590  before the rising edge of the delayed clock signal on signal path  588 , latch  590  outputs a logic high level signal on D n 1d signal path  592  and a logic low level signal on D n 2d signal path  594 . If the rising edge of the delayed clock signal on signal path  588  arrives to the input of latch  590  before the rising edge of the delayed clock signal on signal path  584 , latch  590  outputs a logic low level signal on D n 1d signal path  592  and a logic high level signal on D n 2d signal path  594 . Latch  590  maintains the output signals on D n 1d signal path  592  and D n 2d signal path  594  until another evaluation is performed.  
         [0090]     Table I below indicates the values for D n 1a, D n 2a, D n 1b, D n 2b, D n 1c, D n 2c, D n 1d, and D n 2d based on the value of V nM . A “0” indicates a logic low level and a “1” indicates a logic high level. The outputs indicating the process for nFET  344  are passed to OCD  112  or other circuits to adjust the circuits based on the process.  
                                                   TABLE I                       V nM     D n 1a   D n 2a   D n 1b   D n 2b   D n 1c   D n 2c   D n 1d   D n 2d   Process                   V nM  &gt; V nRSS     0   1   0   1   0   1   0   1   Slowest       V nRSS  &gt; V nM  &gt; V nRS     1   0   0   1   0   1   0   1   Slow       V nRS  &gt; V nM  &gt; V nRF     1   0   1   0   0   1   0   1   Nominal       V nRF  &gt; V nM  &gt; V nRFF     1   0   1   0   1   0   0   1   Fast       V nM  &lt; V nRFF     1   0   1   0   1   0   1   0   Fastest                  
 
         [0091]      FIG. 16  is a schematic diagram illustrating one embodiment of a reference circuit  600  for providing multiple reference signals for evaluating the process for a pFET. Reference circuit  600  includes current source  604  and resistors  608 ,  612 ,  616 , and  619 . Current source  604  is electrically coupled to V INT    320  through path  602  and resistor  608  through fastest process pFET reference voltage (V pRFF ) signal path  606 . Resistor  608  is electrically coupled to resistor  612  through fast process pFET reference voltage (V pRF ) signal path  610 . Resistor  612  is electrically coupled to resistor  616  through slow process pFET reference voltage (V pRS ) signal path  614 . Resistor  616  is electrically coupled to resistor  619  through slowest process pFET reference voltage (V pRSS ) signal path  618 . Resistor  619  is electrically coupled to common or ground  224  through path  620 . The sum of the resistances of resistors  608 ,  612 ,  616 , and  619  is substantially equal to the resistance of resistor  410 .  
         [0092]     Reference circuit  600  provides four reference voltages to compare to V pM  from test circuit  150   b . V pRSS  indicates the slowest process for pFET  408 . V pRS  indicates a slow process for pFET  408 , but faster than V pRSS . V pRF  indicates a fast process for pFET  408  and V pRFF  indicates the fastest process for pFET  408 . In other embodiments, reference circuit  600  includes more than four resistors to provide more than four reference voltages. Any suitable number of resistors to provide any suitable number of reference voltages can be provided.  
         [0093]      FIG. 17  is a block diagram illustrating one embodiment of an evaluation circuit  621  having multiple latches for evaluating the process for pFET  408 . Evaluation circuit  621  includes inverter chains  622 ,  626 ,  642 ,  646 ,  662 ,  666 ,  682 , and  686 , and latches  630 ,  650 ,  670 , and  690 . In one embodiment, inverter chains  626 ,  646 ,  666 , and  686 , are replaced with a single inverter having an output coupled to latches  630 ,  650 ,  670 , and  690 . Inverter chains  622 ,  626 ,  642 ,  646 ,  662 ,  666 ,  682 , and  686  are similar to inverter chain  128 . Latches  630 ,  650 ,  670 , and  690  are similar to latch  140 .  
         [0094]     Inverter chain  622  is electrically coupled to V pRFF  signal path  606 , CLK signal path  122 , and latch  630  through signal path  624 . Inverter chain  626  is electrically coupled to V pM  signal path  152   b , CLK signal path  122 , and latch  630  through signal path  628 . Latch  630  is electrically coupled to pFET latch A data one (D p 1a) signal path  632  and pFET latch A data two (D p 2a) signal path  634 .  
         [0095]     Inverter chain  642  is electrically coupled to V pRF  signal path  610 , CLK signal path  122 , and latch  650  through signal path  644 . Inverter chain  646  is electrically coupled to V pM  signal path  152   b , CLK signal path  122 , and latch  650  through signal path  648 . Latch  650  is electrically coupled to pFET latch B data one (D p 1b) signal path  652  and pFET latch B data two (D p 2b) signal path  654 .  
         [0096]     Inverter chain  662  is electrically coupled to V pRS  signal path  614 , CLK signal path  122 , and latch  670  through signal path  664 . Inverter chain  666  is electrically coupled to V pM  signal path  152   b , CLK signal path  122 , and latch  670  through signal path  668 . Latch  670  is electrically coupled to pFET latch C data one (D p 1c) signal path  672  and pFET latch C data two (D p 2c) signal path  674 .  
         [0097]     Inverter chain  682  is electrically coupled to V pRSS  signal path  618 , CLK signal path  122 , and latch  690  through signal path  684 . Inverter chain  686  is electrically coupled to V pM  signal path  152   b , CLK signal path  122 , and latch  690  through signal path  688 . Latch  690  is electrically coupled to pFET latch D data one (D p 1d) signal path  692  and pFET latch D data two (D p 2d) signal path  694 .  
         [0098]     Reference circuit  600  outputs the V pRFF  signal to inverter chain  622  through signal path  606 . The V pRFF  signal is received by inverter chain  622  and controls inverter chain  622 . Inverter chain  622  receives the CLK signal through CLK signal path  122  as an input. Based on the V pRFF  signal received from reference circuit  600 , the CLK signal is delayed as it propagates through inverter chain  622 . Inverter chain  622  outputs a delayed clock signal, which is proportional to the V pRFF  signal received from reference circuit  600 , to latch  630  through signal path  624 .  
         [0099]     Test circuit  150   b  outputs the V pM  signal to inverter chain  626  through signal path  152   b . The V pM  signal is received by inverter chain  626  and controls inverter chain  626 . Inverter chain  626  receives the CLK signal through CLK signal path  122  as an input. Based on the V pM  signal received from test circuit  150   b , the CLK signal is delayed as it propagates through inverter chain  626 . Inverter chain  626  outputs a delayed clock signal, which is proportional to the V pM  signal received from test circuit  150   b , to latch  630  through signal path  628 .  
         [0100]     Latch  630  receives the delayed clock signal from inverter chain  622  through signal path  624  and the delayed clock signal from inverter chain  626  through signal path  628 . If the rising edge of the delayed clock signal on signal path  624  arrives to the input of latch  630  before the rising edge of the delayed clock signal on signal path  628 , latch  630  outputs a logic high level signal on D p 1a signal path  632  and a logic low level signal on D p 2a signal path  634 . If the rising edge of the delayed clock signal on signal path  628  arrives to the input of latch  630  before the rising edge of the delayed clock signal on signal path  624 , latch  630  outputs a logic low level signal on D p 1a signal path  632  and a logic high level signal on D p 2a signal path  634 . Latch  630  maintains the output signals on D p 1a signal path  632  and D p 2a signal path  634  until another evaluation is performed.  
         [0101]     Reference circuit  600  outputs the V pRF  signal to inverter chain  642  through signal path  610 . The V pRF  signal is received by inverter chain  642  and controls inverter chain  642 . Inverter chain  642  receives the CLK signal through CLK signal path  122  as an input. Based on the V pRF  signal received from reference circuit  600 , the CLK signal is delayed as it propagates through inverter chain  642 . Inverter chain  642  outputs a delayed clock signal, which is proportional to the V pRF  signal received from reference circuit  600 , to latch  650  through signal path  644 .  
         [0102]     Test circuit  150   b  outputs the V pM  signal to inverter chain  646  through signal path  152   b . The V pM  signal is received by inverter chain  646  and controls inverter chain  646 . Inverter chain  646  receives the CLK signal through CLK signal path  122  as an input. Based on the V pM  signal received from test circuit  150   b , the CLK signal is delayed as it propagates through inverter chain  646 . Inverter chain  646  outputs a delayed clock signal, which is proportional to the V pM  signal received from test circuit  150   b  to latch  650  through signal path  648 .  
         [0103]     Latch  650  receives the delayed clock signal from inverter chain  642  through signal path  644  and the delayed clock signal from inverter chain  646  through signal path  648 . If the rising edge of the delayed clock signal on signal path  644  arrives to the input of latch  650  before the rising edge of the delayed clock signal on signal path  648 , latch  650  outputs a logic high level signal on D p 1b signal path  652  and a logic low level signal on D p 2b signal path  654 . If the rising edge of the delayed clock signal on signal path  648  arrives to the input of latch  650  before the rising edge of the delayed clock signal on signal path  644 , latch  650  outputs a logic low level signal on D p 1b signal path  652  and a logic high level signal on D p 2b signal path  654 . Latch  650  maintains the output signals on D p 1b signal path  652  and D p 2b signal path  654  until another evaluation is performed.  
         [0104]     Reference circuit  600  outputs the V pRS  signal to inverter chain  662  through signal path  614 . The V pRS  signal is received by inverter chain  662  and controls inverter chain  662 . Inverter chain  662  receives the CLK signal through CLK signal path  122  as an input. Based on the V pRS  signal received from reference circuit  600 , the CLK signal is delayed as it propagates through inverter chain  662 . Inverter chain  662  outputs a delayed clock signal, which is proportional to the V pRS  signal received from reference circuit  600 , to latch  670  through signal path  664 .  
         [0105]     Test circuit  150   b  outputs the V pM  signal to inverter chain  666  through signal path  152   b . The V pM  signal is received by inverter chain  666  and controls inverter chain  666 . Inverter chain  666  receives the CLK signal through CLK signal path  122  as an input. Based on the V pM  signal received from test circuit  150   b , the CLK signal is delayed as it propagates through inverter chain  666 . Inverter chain  666  outputs a delayed clock signal, which is proportional to the V pM  signal received from test circuit  150   b , to latch  670  through signal path  668 .  
         [0106]     Latch  670  receives the delayed clock signal from inverter chain  662  through signal path  664  and the delayed clock signal from inverter chain  666  through signal path  668 . If the rising edge of the delayed clock signal on signal path  664  arrives to the input of latch  670  before the rising edge of the delayed clock signal on signal path  668 , latch  670  outputs a logic high level signal on D p 1c signal path  672  and a logic low level signal on D p 2c signal path  674 . If the rising edge of the delayed clock signal on signal path  668  arrives to the input of latch  670  before the rising edge of the delayed clock signal on signal path  664 , latch  670  outputs a logic low level signal on D p 1c signal path  672  and a logic high level signal on D p 2c signal path  674 . Latch  670  maintains the output signals on D p 1c signal path  672  and D p 2c signal path  674  until another evaluation is performed.  
         [0107]     Reference circuit  600  outputs the V pRSS  signal to inverter chain  682  through signal path  618 . The V pRSS  signal is received by inverter chain  682  and controls inverter chain  682 . Inverter chain  682  receives the CLK signal through CLK signal path  122  as an input. Based on the V pRSS  signal received from reference circuit  600 , the CLK signal is delayed as it propagates through inverter chain  682 . Inverter chain  682  outputs a delayed clock signal, which is proportional to the V pRSS  signal received from reference circuit  600 , to latch  690  through signal path  684 .  
         [0108]     Test circuit  150   b  outputs the V pM  signal to inverter chain  686  through signal path  152   b . The V pM  signal is received by inverter chain  686  and controls inverter chain  686 . Inverter chain  686  receives the CLK signal through CLK signal path  122  as an input. Based on the V pM  signal received from test circuit  150   b , the CLK signal is delayed as it propagates through inverter chain  686 . Inverter chain  686  outputs a delayed clock signal, which is proportional to the V pM  signal received from test circuit  150   b , to latch  690  through signal path  688 .  
         [0109]     Latch  690  receives the delayed clock signal from inverter chain  682  through signal path  684  and the delayed clock signal from inverter chain  686  through signal path  688 . If the rising edge of the delayed clock signal on signal path  684  arrives to the input of latch  690  before the rising edge of the delayed clock signal on signal path  688 , latch  690  outputs a logic high level signal on D p 1d signal path  692  and a logic low level signal on D p 2d signal path  694 . If the rising edge of the delayed clock signal on signal path  688  arrives to the input of latch  690  before the rising edge of the delayed clock signal on signal path  684 , latch  690  outputs a logic low level signal on D p 1d signal path  692  and a logic high level signal on D p 2d signal path  694 . Latch  690  maintains the output signals on D p 1d signal path  692  and D p 2d signal path  694  until another evaluation is performed.  
         [0110]     Table II below indicates the values for D p 1a, D p 2a, D p 1b, D p 2b, D p 1c, D p 2c, D p 1d, and D p 2d based on the value of V pM . A “0” indicates a logic low level and a “1” indicates a logic high level. The outputs indicating the process for pFET  408  are passed to OCD  112  or other circuits to adjust the circuits based on the process.  
                                                   TABLE II                       V pM     D p 1a   D p 2a   D p 1b   D p 2b   D p 1c   D p 2c   D p 1d   D p 2d   Process                   V pM  &gt; V pRFF     0   1   0   1   0   1   0   1   Fastest       V pRFF  &gt; V pM  &gt; V pRF     1   0   0   1   0   1   0   1   Fast       V pRF  &gt; V pM  &gt; V pRS     1   0   1   0   0   1   0   1   Nominal       V pRS  &gt; V pM  &gt; V pRSS     1   0   1   0   1   0   0   1   Slow       V pM  &lt; V pRSS     1   0   1   0   1   0   1   0   Slowest                  
 
         [0111]     The evaluation circuits described herein enable high speed evaluation of the process and voltage characteristics of a semiconductor chip. The information obtained from the evaluation circuits can be used to adjust the semiconductor chip to compensate for any effects due to variations in the process or voltage characteristics.