Abstract:
A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention generally relates to the field of semiconductor devices and more particularly, to the manufacture of advanced metal oxide semiconductor field effect transistors (MOSFETs) with self-aligned contacts.  
       BACKGROUND OF THE INVENTION  
       [0002]     Transistor scaling has provided continued improvement in speed performance and circuit density in ultra-large scale integrated (ULSI) chips over the past few decades. As the gate length of the conventional bulk metal-oxide-semiconductor field-effect transistor (MOSFET) is reduced, it suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-30 nm regime, the requirements for body doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet in conventional device structures where bulk silicon substrates are employed.  
         [0003]     A promising approach to control short-channel effects and to sustain the historical pace of scaling is to use alternative device structures such as ultra-thin body transistors and multiple-gate transistors. An ultra-thin body (UTB) transistor has a body thickness that is less than half the gate length. In an ultra-thin body transistor, all current paths between the source and drain are in close proximity to the gate, resulting in good gate control of the channel potential. Multiple-gate transistor structures include the double-gate structure, triple-gate structure, omega-FET structure, and the surround-gate or wrap-around gate structure. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate potential of silicon MOSFETs. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps to suppress short channel effects, and prolongs the scalability of the MOS transistor.  
         [0004]     In the above-mentioned nanoscale device structures (including UTB transistors and multiple-gate transistors), the high current density flowing in the devices means that series resistances are an important consideration in the optimization of device performance. In addition, variations in the series resistance in the source and drain regions of the device result in significant variations in the electrical characteristics of the device. A manufacturable process needs to have an adequate robustness to ensure that variations in the device series resistance are kept to a minimum.  
         [0005]     For illustration purposes, an advanced device structure such as an ultra-thin body (UTB) transistor is first considered.  FIG. 1A  shows an enlarged, plane view of the UTB transistor  10 .  FIG. 1B  shows an enlarged, cross-sectional view through the dashed line A-A′ of  FIG. 1A . The UTB transistor  10  comprises an ultra-thin body  12  overlying an insulator layer  14  and a silicon substrate  30 . A transistor with a source  16  and a drain  18  separated by a gate electrode  20  is formed on the ultra-thin body  12 . The gate electrode  20  is further insulated by a spacer  32  and a gate dielectric layer  34 . A silicide layer  22  is formed in the source and drain regions  16 , 18 . Electrical connections to the source and drain regions  16 , 18  are formed by conductive contacts  24 , 26  to the silicided contact area  22 . Electrical current flowing from the source contact  24  to the drain contact  26  passes from source contact  24  into the silicided contact area  22  in the source, enters the source region  16 , the channel region  28  of the transistor  10 , and into the drain region  18 . The current then flows from the drain region  18  to the silicided contact area  22  in the drain region  18  to the drain contact  26 . The current encounters resistances in various parts of the transistor  10  as mentioned above. In an actual manufacturing process, the conductive contacts  24 , 26  may be misaligned.  
         [0006]     Referring now to  FIG. 2 , an example of a misaligned contact is illustrated. In this example, both the source and the drain contacts  24 , 26  are misaligned to the right. Consequently, the distance between the source contact  24  and the channel region  28  is reduced, while the distance between the drain contact  26  and the channel region  28  is increased. This results in a reduced source resistance and an increased drain resistance. Such variations in the source and drain resistances in the transistor  40  results in variations in the device characteristics.  
         [0007]     It is therefore an object of the present invention to provide a self-aligned contact hole for nanoscale silicon-on-insulator (SOI) devices.  
         [0008]     It is another object of the present invention to provide a method for forming nanoscale SOI devices with self-aligned source and drain contacts.  
       SUMMARY OF THE INVENTION  
       [0009]     In accordance with the present invention, a method for forming a self-aligned contact to an ultra-thin body transistor and the contact thus formed are disclosed.  
         [0010]     In a preferred embodiment, a method for forming a self-aligned contact to an ultra-thin body transistor can be carried out by the operating steps of providing an ultra-thin body transistor including a source region and a drain region separated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the ultra-thin body transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain region; and filling the contact hole with an electrically conductive material for establishing electrical communication with the source/drain region.  
         [0011]     In the method for forming a self-aligned contact to an ultra-thin body transistor, the gate stack may be a gate electrode which may be formed of a material of poly-crystalline silicon or poly-crystalline silicon-germanium. The gate electrode may be formed of a refractory metal. The gate stack may include a gate electrode and a gate capping layer, wherein the gate capping layer may be a dielectric material, or silicon nitride. The gate capping layer may further be a silicon nitride layer overlying a silicon oxide layer.  
         [0012]     The contact spacer may be a dielectric material, may be a silicon nitride, or may be a composite spacer. The contact spacer may have a width between about 20 angstroms and about 5000 angstroms. The passivation layer may be formed of a dielectric material, may be formed of silicon oxide, or may be formed to a thickness between about 500 angstroms and about 3000 angstroms. The electrically conductive material may be a metal, or may be a nitride of titanium nitride or tantalum nitride.  
         [0013]     The present invention is further directed to a method for forming a self-aligned contact to a multiple-gate transistor which may be carried out by the operating steps of providing a multiple-gate transistor that includes a source region and a drain region separated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the multiple-gate transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain region; and filling the contact hole with an electrically conductive material for establishing electrical communication with the source/drain region.  
         [0014]     The method for forming a self-aligned contact to a multiple-gate transistor may further include the step of providing the multiple-gate transistor in a double-gate transistor, in a triple-gate transistor, or in an omega field-effect transistor. The gate stack may be a gate electrode which may be formed by a material selected of poly-crystalline silicon or poly-crystalline silicon-germanium. The gate electrode may include a gate material such as a refractory metal. The gate stack may include a gate electrode and a gate capping layer, wherein the gate capping layer may be formed of a dielectric material, may be formed of silicon nitride, or may be formed of silicon nitride layer overlying a silicon oxide layer.  
         [0015]     In the method for forming a self-aligned contact to a multiple-gate transistor, the contact spacer may be formed of a dielectric material, may be formed of silicon nitride, or may be formed of a composite material. The contact spacer may have a width between about 20 angstroms and about 5000 angstroms. The passivation layer may be a dielectric material, may be silicon oxide, or may have a thickness between about 500 angstroms and about 3000 angstroms. The electrically conductive material may be tungsten or may be a nitride of titanium nitride and tantalum nitride.  
         [0016]     The present invention is further directed to a self-aligned contact device which includes an ultra-thin body transistor including a source region and a drain region separated by a gate stack; a contact spacer formed on the side of the gate stack; and an electrically conductive contact in contact with the contact spacer and in electrical communication with the source/drain region.  
         [0017]     The self-aligned contact device may be a gate electrode, which may be formed of a material of poly-crystalline silicon or poly-crystalline silicon-germanium. The gate electrode may include a gate material of a refractory metal. The gate stack may include a gate electrode and a gate capping layer, wherein the gate capping layer may be a dielectric, silicon nitride, or a silicon nitride layer overlying a silicon oxide layer. The contact spacer may be a dielectric, silicon nitride, or a composite spacer. The contact spacer may be formed to a width between about 20 angstroms and about 5000 angstroms. The passivation layer may be formed of a dielectric or may be formed of silicon oxide. The passivation layer may be formed to a thickness between about 500 angstroms and about 3000 angstroms. The electrically conductive material may be tungsten or may be a nitride of titanium nitride or tantalum nitride.  
         [0018]     The present invention is still further directed to a self-aligned contact device which includes a multiple-gate transistor that includes a source and a drain separated by a gate stack; a contact spacer formed on the side of the gate stack; and a conductive contact in contact with the contact spacer and in electrical communication with the source and drain.  
         [0019]     In the self-aligned contact device, the multiple-gate transistor may be a double-gate transistor, a triple-gate transistor, or an omega field-effect transistor. The gate stack may be a gate electrode, which may be formed of poly-crystalline silicon or poly-crystalline silicon-germanium. The gate electrode may be formed of a refractory metal. The gate stack may include a gate electrode and a gate capping layer which may be formed of a dielectric, of a silicon nitride, or of a silicon nitride layer overlying a silicon oxide layer. The contact spacer may be a dielectric, may be silicon nitride, or may be a composite spacer. The contact spacer may have a width between about 20 angstroms and about 5000 angstroms. The passivation layer may be formed of a dielectric material or may be formed of a silicon oxide. The passivation layer may be formed to a thickness between about 500 angstroms and about 3000 angstroms. The electrically conductive material may be tungsten or may be a nitride of titanium nitride or tantalum nitride. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     These and other objects, features and advantages of the present invention will become apparent from the following detailed description and the appended drawings in which:  
         [0021]      FIGS. 1A and 1B  are an enlarged, plane view and an enlarged, cross-sectional view, respectively, of a conventional ultra-thin body transistor.  
         [0022]      FIG. 2  is an enlarged, cross-sectional view of a conventional ultra-thin body transistor with a misaligned contact.  
         [0023]      FIGS. 3A and 3B  are an enlarged, plane view and an enlarged, cross-sectional view, respectively, of a present invention ultra-thin body transistor with self-aligned contact.  
         [0024]      FIGS. 4A and 4B  are enlarged, cross-sectional views of a present invention ultra-thin body transistor with and without a self-aligned contact, respectively.  
         [0025]      FIGS. 5A-5C  are enlarged, cross-sectional views illustrating the formation process of the present invention self-aligned contact to an ultra-thin body transistor.  
         [0026]      FIGS. 6A-6C  are enlarged, plane views illustrating the formation of the present invention self-aligned contact to an ultra-thin body transistor.  
         [0027]      FIG. 7  is an enlarged, perspective view of a present invention triple-gate transistor prior to the formation of the self-aligned contact.  
         [0028]      FIG. 8  is an enlarged, cross-sectional view taken along line C-C′ of  FIG. 7  through the gate electrode.  
         [0029]      FIGS. 9A-9D  are enlarged, cross-sectional views taken along line D-D′ illustrating the process steps for forming the present invention self-aligned contact to a triple-gate transistor.  
         [0030]      FIGS. 10A-10D  are enlarged, cross-sectional views taken along line E-E′ illustrating the process steps for forming a self-aligned contact in a triple-gate transistor.  
         [0031]      FIG. 11  is an enlarged, perspective view of an omega-FET.  
         [0032]      FIG. 12  is an enlarged, perspective view of a double-gate transistor. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0033]     The present invention concerns the provision of self-aligned contacts to the source and drain regions in advanced semiconductor device structures such as ultra-thin body transistors, double-gate transistors such as the finFET transistor, triple-gate transistors, and omega-FET. Transistors with two or more gates, including the double-gate transistor, the triple-gate transistor, and the omega-FET are termed “multiple-gate transistors”.  
         [0034]     In  FIG. 3A , the plane view of an improved contact scheme for the UTB transistor  50  is shown. An enlarged, cross-sectional view through the dash line B-B′ of  FIG. 3A  is shown in  FIG. 3B . The contacts  24 , 26  overlap a contact spacer  36 , so that any slight misalignment in the source and drain contacts  24 , 26  will not affect the distance between the source contact  24  and the channel region  28  and the distance between the drain contact  26  and the channel region  28 . The distances between the source contact  24  or the drain contact  26  and the channel region  28  is the same as long as the contact holes  44 , 46  overlap the contact spacer  36 . The distance between the source contact  24  and the channel region  28  is labeled X s , and the distance between the drain contact and the channel region is labeled X d , as shown in  FIG. 3D .  FIG. 3B  also shows the definition of the width X c  of the contact spacer  36 .  
         [0035]      FIGS. 4A and 4B  show transistor  60  in another embodiment of this invention. In  FIGS. 4A and 4B , a gate capping layer  42  overlies the gate electrode  20 . In this embodiment, the tolerance for the contact misalignment is larger. The provision of a mask, i.e. the gate capping layer  42 , over the gate electrode  20  ensures that even if the contacts  24 , 26  are grossly misaligned so that one of them overlaps the gate electrode  20 , an electrical short between the contacts  24 , 26  and the gate electrode  20  would not occur.  
         [0036]     A method for the fabrication of the present invention UTB transistor with self-aligned contact is now described. Referring now to  FIGS. 5A and 6A , a UTB transistor  70  is first formed. At this stage, the UTB transistor  70  comprises a source  16  and a drain  18  separated by a gate stack  72 . The gate stack  72  comprises a gate electrode  20 . The gate electrode  20  is formed of a gate material. The gate material may be polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), a refractory metal such as molybdenum and tungsten, compounds such as titanium nitride, or other suitable conducting material. In the preferred embodiment, a gate capping layer  42  is provided on the gate electrode  20 . The gate stack  72  therefore comprises the gate capping layer  42  and the gate electrode  20 , as shown in an enlarged, plane view of  FIG. 6A . The gate capping layer  42  may be formed of a dielectric material such as silicon oxide, silicon nitride, or any other suitable material that is insulating in nature. The gate capping layer  42  may also be formed of a silicon nitride layer overlying a silicon oxide layer.  
         [0037]     Shown in  FIGS. 5B and 6B , a contact spacer  36  is next formed. The contact spacer  36  is formed on the first spacer  32  of the device using techniques known and used in the art, i.e. deposition of the spacer material and anisotropic plasma etching. The contact spacer material may be a dielectric material such as silicon nitride or silicon dioxide. In the preferred embodiment, the spacer is formed of silicon nitride. The contact spacer  36  may also be a composite spacer comprising a plurality of layers such as a silicon nitride layer overlying a silicon oxide layer. The width X c  of the contact spacer  36 , shown in  FIG. 3B , is in the range between about 20 angstroms to about 5000 angstroms. Next, as shown in  FIGS. 5C and 6C , a passivation layer  74  is deposited. The passivation layer  74  may be formed of a dielectric such as silicon oxide. For example, silicon oxide can be deposited by low pressure chemical vapor deposition using tetraethosiloxane (TEOS) as a precursor in a temperature range between about 650 degrees Celsius and about 900 degrees Celsius. The thickness of the passivation layer  74  is between about 500 angstroms and about 300 angstroms. Selected portions of the passivation layer  74  are etched to form contact holes  44 , 46  in the passivation layer. Etching may be accomplished in a reactive plasma etcher using a reactant gas mixture such as carbon tetrafluoride and hydrogen. Contact holes  44 , 46  may overlap the contact spacers  36 , as shown in the enlarged, plane view of  FIG. 6C . Contact holes  44 , 46  are then filled with an electrically conductive material. The electrically conductive material may be a metal such as tungsten, a metallic nitride such as titanium nitride and tantalum nitride, or any other electrically conducting materials. The contact holes  44 , 46  may also be filled with a combination of the above mentioned materials.  
         [0038]     In the above illustration, a self-aligned contact scheme was described for an ultra-thin body transistor  70 . The use of a contact spacer  36  for the self-aligned contacts  24 , 26  may be applied in other advanced transistor structures such as double-gate transistors, triple-gate transistors, and omega-FETs.  
         [0039]     Referring now to  FIG. 7 , a triple-gate transistor  80  is shown. The triple-gate transistor  80  of  FIG. 7  is completed up to the process step prior to contact formation. The triple-gate transistor  80  has a source  16  and drain  18  separated by a gate stack  72 . The source/drain regions  16 , 18  may be formed of a silicide (not shown) and a heavily-doped source/drain (similar to the ultra-thin body transistor).  FIG. 8  shows an enlarged, cross-section view of the triple-gate transistor  80  of  FIG. 7  in the line containing C-C′. The line containing C-C′ of  FIG. 7  cuts through all three gates  82 , 84 , 86  of the gate electrode  20  as well as the channel region  28 . Referring to  FIG. 8 , a gate dielectric layer  34  wraps around the silicon fin  90  in the channel region  28  of the triple-gate transistor  80 . The gate electrode  20  in the triple-gate transistor  80  straddles over the silicon fin  90 . The gate electrode  20  forms three gates: one gate  84  on the top surface  88  of the silicon fin  90 , and two gates  82 , 86  on the sidewalls  92 , 94  of the silicon fin  90 .  
         [0040]     An enlarged, cross-sectional view taken along line D-D′ of  FIG. 7  is shown in  FIG. 9A . This cross-section cuts through the fin  90  and the top gate  84 . The cross-section in the line containing E-E′ of  FIG. 7  is shown in  FIG. 10A . This cross-section cuts through the fin  90  and the two gates  82 , 86  on the sidewalls  92 , 94  of the fin  90 . It should be noted that the gate electrode  20  may comprise a gate capping layer  42  overlying an electrically conductive gate material. The gate material may be comprised of poly-Si, poly-SiGe, a refractory metal such as molybdenum and tungsten, compounds such as titanium nitride, or other conducting materials.  
         [0041]     A simple process flow for fabricating the self-aligned contact for a triple-gate structure is to be described.  FIGS. 9A-9D  and  10 A- 10 D illustrate the process for forming the self-aligned contacts  24 , 26 . The method for forming a self-aligned contact begins with the completed triple-gate transistor  80  as shown in  FIGS. 9A and 10A . A contact spacer  36  is formed, as shown in  FIGS. 9B and 10B . The contact spacer  36  is formed using techniques known in the art for spacer formation, i.e. deposition of the spacer material and anisotropic plasma etching. The contact spacer material may be a dielectric material such as silicon nitride and silicon dioxide. In the preferred embodiment, the spacer material is a silicon nitride. The contact spacer  36  may also be a composite spacer formed by a plurality of layers such as a silicon nitride layer overlying a silicon oxide layer. The width of the contact spacer  36 , shown in  FIGS. 9B and 10B , is in the range from about 20 angstroms to about 5000 angstroms. This is followed by the deposition of a passivation layer  74 . The passivation layer  74  may be formed of a dielectric such as silicon oxide. For example, silicon oxide can be deposited by low pressure chemical vapor deposition using tetraethosiloxane (TEOS) as a precursor at a temperature between about 650 degrees Celsius and about 900 degrees Celsius. The thickness of the passivation layer  74  is preferably in the range from about 500 angstroms to about 3000 angstroms. Selected portions of the passivation layer  74  are patterned using lithography techniques and etched to form contact holes  44 , 46 . Etching may be accomplished in a reactive plasma etcher using a reactant gas mixture such as carbon tetrafluoride and hydrogen. Contact holes  44 , 46  may overlap the contact spacers  36 , as shown in  FIGS. 9C and 10C . Contact holes  44 , 46  are then filled with an electrically conductive material, as shown in  FIGS. 9D and 10D . The conductive contact material may be a metal such as tungsten, a metallic nitride such as titanium nitride and tantalum nitride, or any other conducting material. The contact hole may also be filled with a combination of the above mentioned materials.  
         [0042]     The self-aligned contact formation process may also be applied to other advanced device structures. For example, the omega-FET structure  100  shown in  FIG. 11 , and the double-gate transistor structure  110  shown in  FIG. 12 , is similar to the triple-gate transistor structure  80 . The self-aligned contact process described for the triple-gate transistor  80  may be applied generally to other multiple-gate transistors, such as the double-gate transistor  110  or the omega-FET  100 .  
         [0043]     While the present invention has been described in an illustrative manner, it should be understood that the terminology used is intended to be in a nature of words of description rather than of limitation.  
         [0044]     Furthermore, while the present invention has been described in terms of a preferred and alternate embodiment, it is to be appreciated that those skilled in the art will readily apply these teachings to other possible variations of the inventions.  
         [0045]     The embodiment of the invention in which an exclusive property or privilege is claimed are defined as follows.