Abstract:
A phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. In a first embodiment, the phase lock indication is controlled by monitoring a digital count. In a second embodiment, the phase lock indication signal is controlled by monitoring a capacitor voltage. Related operating methods are also discussed.

Description:
FIELD OF THE INVENTION 
     The present invention relates to phase detection circuits and methods of operation therefor, and more particularly, to phase lock detection circuits and methods of operation therefor. 
     BACKGROUND OF THE INVENTION 
     Phase lock loop (PLL) and other phase control circuits typically require a determination of when the circuit has achieved phase synchronization, i.e., “phase lock.” It is generally desirable that this determination be made as accurately as possible in order to meet system performance requirements. In addition, a typical charge-pump type phase lock loop generates relatively large currents when in its acquisition mode, i.e., when it is seeking phase lock, and generates a relative smaller current when phase lock is achieved. Consequently, typical phase control systems attempt to quickly achieve phase lock and to maintain phase lock without oscillation in order to reduce power dissipation. 
     Towards this end, it is generally desirable in phase lock loops and other phase control circuits to accurately detect phase lock in a manner which is less susceptible to noise. It is also desirable to detect phase lock in a manner that is less prone to oscillation as the loop transitions in or out of phase lock. 
     SUMMARY OF THE INVENTION 
     In light of the foregoing, it is an object of the present invention to provide phase lock detection circuits and methods of operation therefor which can provide accurate and stable phase lock detection. 
     It is another object of the present invention to provide phase lock detection circuits and methods of operation therefor that have improved immunity to noise. 
     These and other objects, features and advantages are provided according to the present invention by phase lock detection circuits and methods of operation therefor in which a digital phase detection circuit produces a phase detect signal from first and second input signals provided thereto, and a stabilized phase lock detection circuit produces a phase lock indication signal responsive to the phase detect signal, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. 
     The phase detection circuit preferably generates a window signal from the first input signal, the value of which is latched by a flip-flop circuit upon a transition of a delayed version of the second input signal to produce the phase detect signal. In this manner, a window detector is implemented that changes the phase detect signal to a logic state that indicates phase agreement when the second input signal has a phase delay with respect to the first input signal that falls within a time interval defined by the window signal. 
     The phase lock detection circuit may include a digital circuit that controls a digital count, the phase lock detection circuit changing the logic state of the phase lock detection signal when the digital count meets predetermined criteria. The predetermined criteria, e.g., a predetermined count threshold, may be programmably provided to the phase lock detection circuit. The phase lock detection circuit may alternatively include a circuit that controls a voltage across a capacitor, the phase lock detection circuit changing the logic state of the phase lock indication signal when the capacitor voltage meets predetermined criteria. 
     The present invention provides improved phase lock detection by utilizing circuitry that introduces hysteresis into the phase lock detection process. In this manner, oscillation or other instability caused by such factors as noise can be reduced and a more accurate indication of phase lock achieved. 
     In particular, according to the present invention, a phase lock detection circuit includes a phase detection circuit that produces a phase detect signal having one of a first logic state or a second logic state responsive to a first input signal and a second input signal applied thereto. A stabilized phase lock indication circuit is electrically coupled to the phase detection circuit and produces a phase lock indication signal having one of a first logic state or a second logic state, the phase lock indication signal changing to a respective one of its first and second logic states in response to the phase detect signal remaining in a respective one of its first and second logic states for a predetermined time interval. 
     The phase detection circuit may include a first delay circuit configured to receive the first input signal and operative to produce a delayed first input signal therefrom, and a logic gate electrically coupled to the first delay circuit and operative to produce a window signal at an output thereof, the window signal representing a logic ANDing of the first input signal and the delayed first input signal. A second delay circuit is configured to receive the second input signal and operative to produce a delayed second input signal therefrom. A flip-flop circuit is electrically coupled to the logic gate and to the second delay circuit, receiving the window signal at a data input thereof and receiving the delayed second input signal at a clock input thereof and producing a phase detect signal therefrom that has a logic state corresponding to the logic state of the window signal at a transition of the delayed second input signal. 
     The stabilized phase lock indication circuit may include means for increasing a value when the phase detect signal is in its first logic state and for decreasing the value when the phase detect signal is in its second logic state. Means may be provided for changing the phase lock indication signal to its first logic state when the value meets a first predetermined criterion and for changing the phase lock indication signal to its second logic state when the value meets a second predetermined criterion. 
     In a first embodiment according to the present invention, the stabilized phase lock indication circuit includes means for controlling a digital count responsive to the phase detect signal. Means are provided for changing the phase lock indication signal to its first logic state when the digital count meets a first predetermined criterion and for changing the phase lock indication signal to its second logic state when the digital count meets a second predetermined criterion. The means for controlling a digital count may include means for increasing the digital count when the phase detect signal is in its first logic state and for decreasing the digital count when the phase detect signal is in its second logic state. The means for changing the phase lock indication signal may include means for changing the phase lock indication signal to its first logic state when the digital count increases above a predetermined threshold and means for changing the phase lock indication signal to its second logic state when the digital count decreases below the predetermined threshold. 
     In a second embodiment according to the present invention, the stabilized phase lock indication circuit includes a capacitor and means for controlling a capacitor voltage across the capacitor responsive to the phase detect signal. Means are provided for changing the phase lock indication signal to its first logic state when the capacitor voltage meets a first predetermined criterion and for changing the phase lock indication signal to its second logic state when the capacitor voltage meets a second predetermined criterion. 
     The means for controlling a capacitor voltage may include means for charging the capacitor to increase the capacitor voltage when the phase detect signal is in its first logic state and for discharging the capacitor to decrease the capacitor voltage when the phase detect signal is in its second logic state. The means for changing the phase lock indication signal may include means for changing the phase lock indication signal to its first logic state when the capacitor voltage rises above a first predetermined threshold and for changing the phase lock indication signal to its second logic state when the capacitor voltage falls below a second predetermined threshold. 
     Related operating methods are also discussed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram illustrating an embodiment of a phase lock detection circuit according to the present invention; 
     FIG. 2A is a schematic diagram illustrating an embodiment of a phase detection circuit for the circuit of FIG.  1 . 
     FIG. 2B is a timing diagram illustrating exemplary operations for the circuit of FIG.  2 A. 
     FIG. 3 is a flowchart illustration of exemplary operations for detecting phase lock according to an aspect of the present invention. 
     FIG. 4 is a timing diagram illustrating exemplary operations for the circuit of FIG.  1 . 
     FIG. 5 is a schematic diagram illustrating another embodiment of a phase lock detection circuit according to the present invention. 
     FIG. 6 is a timing diagram illustrating exemplary operations for the circuit of FIG.  5 . 
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. As will be appreciated by one of skill in the art, the present invention may be embodied as methods or devices. 
     Referring to FIG. 1, an embodiment of a phase lock detection circuit  100  includes a phase detection circuit  101  and a stabilized phase lock indication circuit  103 . The phase detection circuit is configured to receive first and second input signals Clkl, Clkr, producing a phase detect signal lockdet therefrom that indicates whether the phases of the two input signals Clkl, Clkr are in agreement. For the illustrated embodiment, the phase detect signal lockdet takes on a “high” logic state when the phases of the first and second input signals Clkl, Clkr are in agreement and takes on a “low” logic state when the first and second input signals Clkl, Clkr are out of phase. 
     The stabilized phase lock indication circuit  103  controls a digital count responsive to the phase detect signal lockdet and the second input signal Clkr, and produces a phase lock indication signal LOCK based on the digital count. The stabilized phase lock indication circuit  103  increments or decrements the digital count responsive to the phase detect signal lockdet. The stabilized phase lock indication circuit  103  is also configured to receive a predetermined threshold threshold[n: 0 ] at a threshold input TH[n: 0 ], as well as a reset signal reset at a reset input RESET. The stabilized phase lock indication circuit  103  generates the phase lock indication signal LOCK based on a comparison of the digital count with the predetermined threshold threshold[n: 0 ], as explained in greater detail below. 
     Referring to FIG. 2A, an embodiment of a phase detection circuit  101  includes a first delay circuit  201  that produces a delayed first input signal clk 1  from the first input signal Clkl. The delayed second input signal clk 1  is then logically AND&#39;ed with the first input signal Clkl to produce a window signal clk 2 . A second delay circuit  205  produces a delayed second input signal clk 3  from the second input signal Clkr. The window signal clk 2  is applied to the data input D of a flip-flop circuit  207 , which is clocked by the delayed second input signal clk 3  that is applied to its clock input CK. The data outputs Q, QB of the flip-flop circuit  207  produce complementary signals lockdet, lockdetb that depend upon the logic state of the window signal clk 2  upon transition of the delayed second input signal Clkr. 
     This is illustrated more explicitly in FIG.  2 B. Assuming that the first and second input signals Clkl, Clkr are clock signals, the window signal clk 2  produced by the logic ANDing of the first input signal Clkl and the delayed first input signal clk 1  comprises a pulse signal, with the positive pulses of the window signal clk 2  occurring during time windows defined by the rising edge of the first input signal Clkl and the falling edge of the delayed first input signal clk 1 . The delayed second input signal clk 3  preferably is delayed with respect to the second input signal Clkr by a delay which is approximately half of the delay of the delayed first input signal clk 1  with respect to the first input signal Clkl, i.e., by a delay half as long as the time windows defined by the window signal clk 2 . 
     As illustrated, when the rising edge of the delayed second input signal clk 3  falls within one of the time windows defined by the window signal clk 2 , the phase detect signal lockdet changes to a “high” logic state, indicating phase agreement between the first input signal Clkl and the second input signal Clkr. When the rising edge of the delayed second input signal clk 3  falls outside of the window, however, the phase detect signal lockdet takes on a logic “low” state, indicating lack of phase agreement. The complementary phase detect signal lockdetb takes on logic states complementary to those of the phase detect signal lockdet. 
     FIGS. 3 and 4 illustrate exemplary operations  300  for the phase lock detection circuit  100  of FIG.  1 . Upon a rising edge of the second input signal Clkr (Block  302 ), the phase lock detection circuit  100  determines whether it is in a reset state (Block  304 ). If the circuit is reset, e.g., if the reset signal reset of FIG. 1 is currently asserted, the circuit initializes the digital count CNT[ 7 : 0 ] to zero and generates a phase lock indication signal LOCK having a logic state that indicates lack of phase lock (Block  306 ), and then awaits the next rising edge of the second input signal Clkr (Block  302 ). 
     If the phase lock indication circuit is not in the reset state, the circuit next determines if it currently is in an “on-lock” state, i.e., if the current logic state of the phase lock indication signal LOCK indicates phase lock (Block  308 ). If it does, the phase lock detection circuit next determines if the phase detect signal lockdet indicates phase agreement (Block  310 ). If it does, the digital count CNT[ 7 : 0 ] is set to twice a threshold value (Block  314 ). If not, the digital count CNT[ 7 : 0 ] is decremented (Block  312 ). 
     The digital count CNT[ 7 : 0 ] is then compared to the threshold value, here shown as being equal to four (4)(Block  316 ). If the count is less than the threshold value, the phase lock indication circuit changes the state of the phase lock indication signal LOCK to indicate lack of phase lock and resets the digital count CNT[ 7 : 0 ] to zero (Block  318 ). Otherwise, the circuit maintains the phase lock indication signal LOCK in a state that indicates phase lock. The circuit then awaits the next rising edge of the second input signal Clkr (Block  302 ). 
     If the test of the current circuit status (Block  308 ) indicates that the circuit is in an “off-lock” state, i.e., if the current state of the phase lock indication signal LOCK indicates lack of phase lock, the circuit determines if the phase detect signal lockdet indicates phase agreement (Block  320 ). If it does, the digital count CNT[ 7 : 0 ] is incremented (Block  324 ). If not, the digital count CNT[ 7 : 0 ] is reset to zero (Block  322 ) 
     The digital count CNT[ 7 : 0 ] is then compared to the threshold value (Block  326 ). If the count is greater than the threshold value, the phase lock indication circuit changes the logic state of the phase lock indication signal LOCK to indicate phase lock and sets the digital count CNT[ 7 : 0 ] to twice the threshold value (Block  328 ). Otherwise, the circuit maintains the phase lock indication signal LOCK in a logic state indicating lack of phase lock. The circuit then awaits the next rising edge of the second input signal Clkr (Block  302 ). 
     Referring to FIG. 4, the phase lock detection circuit of FIG. 1 operates such that when the phase detect signal lockdet has continuously remained in a “high” logic state for a first time interval T 1 , the phase lock indication signal LOCK is changed to a “high” logic state, indicating phase lock. When the phase detect signal lockdet has remained in a “low” logic state for a second time interval T 2 , the phase lock indication signal LOCK is changed to a “low” logic state to indicate lack of phase lock. 
     Those skilled in the art will appreciate that the circuits of FIGS. 1 and 2A may be implemented in a number of different ways using a number of different devices. For example, the phase detection circuit  101  and the stabilized phase lock indication circuit  103  may be implemented using a number of different types of devices, including discrete logic gates and counters, programmable logic devices (PLDs), application specific integrated circuits (ASICs) and the like. Those skilled in the art will also appreciate that logic architecture of these circuits may also be varied to encompass logically complementary implementations; for example, the control of the digital counter may be implemented such that the digital count decrements when the phase detect signal lockdet indicates phase agreement and increments when the phase detect signal indicates lack of phase agreement, with the reset and set functions for the count defined in Blocks  304 ,  318  and  328  being suitably replaced with complementary operations. 
     It will also be understood that the operations of FIGS. 3 and 4 may also be varied within the scope of the present invention. For example, the many of the operations  300  of FIG. 3 which are shown implemented in a serial fashion may also be performed concurrently. For example, the tests indicated in Blocks  304 ,  308 ,  310 , and  320  may be implemented as concurrent state transition criteria in a state machine embodied in a programmable logic device (PLD) or similar circuitry. In addition, although the illustrated embodiment implements symmetrical first and second time intervals T 1 , T 2 , those skilled in the art will appreciate that variation of the threshold value CNT[ 7 : 0 ] supplied to the phase lock indication circuit  103  may result in asymmetrical time intervals. 
     FIG. 5 illustrates another embodiment of a phase lock detection circuit  100 ′ according to the present invention. The phase lock detection circuit  100 ′ includes a phase detection circuit  101  such as that illustrated in FIGS. 1 and 2A, but includes a stabilized phase lock indication circuit  103 ′ that controls a capacitor voltage Vcap across a capacitor CAP in lieu of a digital count. 
     A capacitor charging circuit  510  provides means for controlling the voltage across the capacitor CAP responsive to the phase detect signal lockdetb generated by the phase detection circuit  101 . The capacitor charging circuit  510  includes a current source ILock that supplies current from a power supply bus vdd to a first terminal of the capacitor CAP. A ground signal GND is applied to a second terminal of the capacitor CAP. First and second multiplexers MUX 1 , MUX 2  which selectively apply the ground signal GND and the phase detect signal lockdetb to first and second switches sw 1 , sw 2  that are operative to discharge the capacitor CAP when in their closed states and that provide a high impedance at the second terminal of the capacitor CAP when in their open states. The first terminal of the capacitor is also connected to a third switch sw 3  that is operative to apply the ground signal GND to the capacitor CAP responsive to a sleep input signal sleep, thus discharging the capacitor when the sleep input signal sleep is asserted. The first terminal of the capacitor CAP is also connected to a threshold buffer circuit  540  that produces a logic signal clk 4  responsive to the capacitor voltage Vcap. The buffer  540  introduces hysteresis into the logic signal clk 4 , e.g., the logic signal clk 4  produced by the buffer  540  changes from a logic “low” to a logic “high” when the capacitor voltage Vcap increases past a first threshold voltage, and changes from a logic “high” to a logic “low” when the capacitor voltage Vcap decreases below a second threshold voltage that is less than the first threshold voltage. 
     A latching circuit  570  produces the phase lock indication signal LOCK responsive to the logic signal clk 4 . The latching circuit  570  includes first and second flip-flop circuits  520 ,  530 . The logic signal clk 4  is applied directly to the clock input CK of the first flip-flop circuit  520 . The logic signal clk 4  is also applied to an inverter  550 , producing an inverted logic signal clk 4 b that is applied to the clock input CK of the second flip-flop circuit  530 . The power supply bus voltage vdd is applied to the data inputs D of both of the first and second flip-flop circuits  520 ,  530 . The phase lock indication signal LOCK produced at the data output Q of the first flip-flop circuit  520  is applied to the reset input RB of the second flip-flop circuit  530 , and a signal produced at the complementary output QB of the second flip-flop circuit  530  is logically AND&#39;ed with an inverted version of the sleep input signal sleep in a logic gate  560  to produce a reset signal resetb that is applied to the reset input RB of the first flip-flop circuit  520 . 
     Referring now to both FIGS. 5 and 6, the first multiplexer MUX 1  applies the phase detect signal lockdetb to the first switch sw 1  when the phase lock indication signal LOCK is in a logic “low” state, i.e., a state indicating lack of phase lock, while the second multiplexer applies the ground signal GND to the second switch sw 2 , holding the second switch sw 2  open. When the phase detect signal lockdetb is “low,” indicating phase agreement, the first switch sw 1  is held open, allowing the voltage Vcap across the capacitor CAP to increase. When the phase detect signal lockdetb goes “high”, the first switch sw 1  closes, discharging the capacitor CAP and causing the capacitor voltage Vcap to decrease. If the phase detect signal lockdetb remains “low” for a sufficiently long time interval T 1 , however, the capacitor voltage Vcap increases past the first threshold voltage Vth 1 , causing the logic signal clk 4  of the buffer  540  to change to a logic “high.” In response, the phase lock indication signal LOCK is latched to a logic “high” value, indicating that phase lock has been achieved. 
     When the phase lock indication signal LOCK has a logic “high” value, the first multiplexer MUX  1  applies the ground signal GND to the first switch sw 1 , holding the first switch sw 1  open, while the second multiplexer MUX 2  applies the phase detect signal lockdetb to the second switch sw 2 . When the phase detect signal lockdetb is in a logic “low” state, indicating phase agreement, the second switch sw 2  is held open, allowing the capacitor CAP to charge and the capacitor voltage Vcap to increase. When the phase detect signal lockdetb goes “high,” the second switch sw 1  closes, causing the capacitor CAP to discharge and the capacitor voltage Vcap to decrease. If the phase detect signal lockdetb remains “high” for a sufficiently long time period T 2 , the capacitor voltage Vcap decreases below the second threshold voltage Vth 2 , causing the logic signal clk 4  produced by the buffer  540  to change state to a logic “low.” In response, the reset signal reset produced at the complementary data output QB of the second flip-flop circuit  530  goes “low,” resetting the first flip-flop circuit  520  and sending the phase lock indication signal LOCK “low.” 
     Preferably, the first switch sw 1  discharges the capacitor CAP at a faster rate when closed that the second switch sw 2  does when closed. This may be achieved, for example by using a first switch sw 1  that has a smaller “on” resistance than the second switch sw 2 . The first and second time intervals T 1 , T 2  can be given by:          T1   =       C   ×   Vth1       I                 Lock         ,   and             T2   =     Rsw2   ×   C   ×     ln        (     vdd     Vth2   -     Rsw2   ×   ILock         )           ,                          
     where Rsw 2  is the on resistance of the second switch sw 2 , and C is the capacitance of the capacitor CAP. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.