Abstract:
A semiconductor for suppressing power supply resonance caused by the external noise and preventing fluctuation of the power supply voltage. The semiconductor device includes first and second power supply wires for supplying power supply voltages, a variable capacitor circuit connected between the first and second power supply wires, a monitor circuit for detecting the fluctuation of the power supply voltage and generating an output signal indicating the detection thereof, and a controller for changing the capacitance value of the variable capacitor circuit based on the output signal of the monitor circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-042381, filed on Feb. 20, 2006, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for suppressing power supply resonance and for suppressing fluctuation in a power supply voltage.  
         [0003]     Normally, an inductance component parasitizes the power supply wires in a semiconductor chip. A capacitor is arranged between a high potential power supply wire and a low potential power supply wire in the chip to stabilize the power supply voltage. When a resonance frequency based on the inductance component and the capacitor coincides with the frequency of noise propagating in the high potential power supply wire or the low potential power supply wire in the semiconductor device, power supply resonance occurs and causes large fluctuations in the power supply voltage. Therefore, power supply resonance caused by noise must be prevented.  
         [0004]      FIG. 1  is a schematic circuit block diagram of a conventional semiconductor device (chip  1 ). Power supply voltage is supplied from an external power supply  2  to power supply terminals t 1  and t 2  of the chip  1  via external wires  3   a  and  3   b.  The power supply voltage is then supplied to a signal processor  5  via internal wires  4   a  and  4   b  of the chip  1 .  
         [0005]     The external wires  3   a  and  3   b  include inductances L 1  and L 2  and resistors R 1  and R 2 , respectively. The inductances L 1  and L 2  and the resistors R 1  and R 2  are actually distributed constants but are illustrated as concentrated constants in  FIG. 1  for the sake of convenience. A capacitor C 1  having a capacitance value of several pF to several tens of μF is connected between the output terminals of the external power supply  2  to stabilize the power supply voltage.  
         [0006]     The internal wires  4   a  and  4   b  include inductances L 3  and L 4  and resistors R 3  and R 4 , respectively. The inductances L 3  and L 4  and the resistors R 3  and R 4  are actually distributed constants but are illustrated as concentrated constants in  FIG. 1 . A capacitor C 2  is connected between the internal wires  4   a  and  4   b  to stabilize the power supply voltage. Most of the components of the inductances L 3  and L 4  parasitize an interposer and bonding wire of the IC package.  
         [0007]     With the above chip  1 , when the resonance frequency of the inductances L 3  and L 4  and the capacitor C 2  coincide with the frequency of internal noise N 1  propagating from the signal processor  5  to the internal wire  4   a  (or  4   b ), power supply resonance occurs and the power supply-voltage fluctuates.  
         [0008]     Thus, the capacitance value of the capacitor C 2  is set so that the resonance frequency of the inductances L 3  and L 4  and the capacitor C 2  does not coincide with the frequency of the internal noise N 1 . The capacitor C 2  attenuates the high frequency noise N 1  output from the signal processor  5 .  
         [0009]     External noise N 2  may be applied to the power supply terminals t 1  and t 2  via the external wires  3   a  and  3   b.  Power supply resonance also occurs and fluctuates the power supply voltage when the frequency of the noise N 2  coincides with the resonance frequency of the inductances L 3  and L 4  of the internal wires  4   a  and  4   b  and the capacitor C 2 .  
         [0010]     The connection of a capacitor between the internal wires  4   a  and  4   b  near the power supply terminals t 1  and t 2  in order to attenuate high frequency external noise N 2  has thus been proposed.  
         [0011]     However, it is difficult to arrange the capacitor near the power supply terminals t 1  and t 2  in a highly integrated chip  1 . Thus, the capacitor is arranged between the signal processor  5  and the power supply terminals t 1  and t 2  to absorb the external noise N 2  between the internal wires  4   a  and  4   b.    
         [0012]     The frequency of the external noise N 2  is determined in a state in which the chip  1  is mounted on a circuit board (e.g., printed circuit board). Thus, the frequency of the external noise N 2  cannot be specified during the design stage of the chip  1 . If power supply resonance occurs after the mounting of the chip  1 , the chip  1  must be re-designed to suppress power supply resonance.  
         [0013]     Japanese Laid-Open Patent Publication No. 2002-158448 discloses a multi-layer wiring substrate for reducing EMI noise by connecting a plurality of incorporated capacitors, which correspond to different resonance frequencies, in parallel. The capacitance value of each incorporated capacitor is controlled so that an anti-resonance frequency of each incorporated capacitor does not coincide with the frequency of a high frequency component contained in an electric signal.  
         [0014]     Japanese Laid-Open Patent Publication No. 2002-190640 (see FIG. 1b) discloses a laser oscillator power supply device provided with a resonance switch for forming a resonance circuit in accordance with the operation of the switch.  
         [0015]     Japanese Laid-Open Patent Publication No. 2001-175702 discloses a circuit designing method for reducing power supply noise by arranging a bypass capacitor having an optimum capacitance value at an optimum position and adjusting the resonance frequency.  
         [0016]     Japanese Laid-Open Patent Publication No. 7-202072 discloses a semiconductor device for suppressing the power supply noise in a wide frequency band by forming a plurality of capacitors having different capacitance values in a package and setting a plurality of resonance frequencies with a bypass capacitor and a conductor inductance.  
         [0017]     Japanese Laid-Open Patent Publication No. 2002-136103 discloses a power supply system for reducing power consumption by arranging a plurality of capacitors between an output terminal of a voltage power supply conversion circuit and ground. A capacitor having a large capacity is connected in a continuous operation mode for continuously outputting power supply voltage and disconnected in an intermittent operation mode for intermittently outputting the power supply voltage.  
       SUMMARY OF THE INVENTION  
       [0018]     The chip  1  shown in  FIG. 1  is designed so that the resonance frequency of the inductances L 3  and L 4  and the capacitor C 2  does not coincide with the frequency of the internal noise N 1 . This prevents power supply resonance caused by the internal noise N 1 . However, the frequency of the external noise N 2  is not specified when designing the chip  1 . Thus, the occurrence of power supply resonance caused by the external noise N 2  cannot be prevented.  
         [0019]     The present invention provides a semiconductor device that prevents power supply resonance caused by external noise and prevents the fluctuation of the power supply voltage.  
         [0020]     One aspect of the present invention is a semiconductor device including first and second power supply wires for supplying power supply voltage. A variable capacitor circuit is connected between the first and second power supply wires. A monitor circuit detects fluctuation in the power supply voltage and generates an output signal indicating detection thereof. A controller, connected to the variable capacitor circuit and the monitor circuit, changes capacitance value of the variable capacitor circuit based-on the output signal of the monitor circuit.  
         [0021]     Another aspect of the present invention is a semiconductor device including first and second power supply wires for supplying power supply voltage. Third and fourth power supply wires, each arranged independent from the first and second power supply wires, supply the power supply voltage. A first variable capacitor circuit is connected between the first and second power supply wires. A second variable capacitor circuit is connected between the third and fourth power supply wires. A first monitor circuit for detecting fluctuation of the power supply voltage supplied via the first and second power supply wires and generating a first output signal indicating detection thereof. A second monitor circuit for detecting fluctuation of the power supply voltage supplied via the third and fourth power supply wires and generating a second output signal indicating the detection. A controller, connected to the first and second variable capacitor circuits and the first and second monitor circuits, for separately changing capacitance value of each of the first and second variable capacitor circuits based on the first and second output signals.  
         [0022]     Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:  
         [0024]      FIG. 1  is a schematic circuit block diagram of a semiconductor device in the prior art;  
         [0025]      FIG. 2  is a schematic circuit block diagram of a semiconductor device according to a first embodiment of the present invention;  
         [0026]      FIG. 3  is a schematic circuit block diagram of an internal circuit of the semiconductor device of  FIG. 2 ;  
         [0027]      FIG. 4  is a flowchart showing the operation of a controller in the semiconductor device of  FIG. 2 ;  
         [0028]      FIG. 5  is a schematic circuit block diagram of a monitor circuit in a semiconductor device according to a second embodiment of the present invention;  
         [0029]      FIG. 6  is a schematic circuit block diagram of an internal circuit in a semiconductor device according to a third embodiment of the present invention; and  
         [0030]      FIG. 7  is a schematic circuit block diagram of an internal circuit in a semiconductor device according to a fourth embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]     In the drawings, like numerals are used for like elements throughout.  
         [0032]      FIG. 2  is a schematic circuit block diagram of a semiconductor device  10  according to a first embodiment of the present invention. The semiconductor device  10  includes an internal circuit  11 , a controller  12 , and a memory  13 . The memory  13  is configured by a non-volatile memory that holds the stored contents even when the supply of power is cut off.  
         [0033]      FIG. 3  shows one example of the internal circuit  11 . High potential power supply voltage of, for example., 3 V is supplied to the power supply terminal t 11 , and ground voltage (0 V) is supplied to the power supply terminal t 12  as low potential power supply voltage. The power supply terminals t 11  and t 12  are respectively connected to a signal processor  15  by power supply wires  14   a  and  14   b  (first and second power supply wires) so that the high potential power supply voltage and the low potential power supply voltage are supplied to the signal processor  15 .  
         [0034]     The power supply wire  14   a  includes an inductance L 11  and a resistor R 11 , and the power supply wire  14   b  includes an inductance L 12  and a resistor R 12 . The inductances L 11  and L 12  and the resistors R 11  and R 12  are actually distributed constants but are illustrated as concentrated constants in  FIG. 3  for the sake of convenience.  
         [0035]     A capacitor C 11  (first fixed capacitor) is connected between the power supply wires  14   a  and  14   b  near the signal processor  15  to stabilize the power supply voltage. The capacitance value of the capacitor C 11  is set so that the resonance frequency of the inductances L 11  and L 12  and the capacitor C 11  does not coincide with the frequency of the internal noised N 1  output from the signal processor  15 . The capacitance value of the capacitor C 11  is set to 50 pF in the first embodiment.  
         [0036]     A variable capacitor circuit  16  is connected in parallel to the capacitor C 11  between the power supply wires  14   a  and  14   b.  The variable capacitor circuit  16  changes its capacitance value to adjust the resonance frequency of the inductances L 11  and L 12 , the capacitor C 11 , and the variable capacitor circuit  16 .  
         [0037]     Specifically, the variable capacitor circuit  16  includes a capacitor C 12  having a first terminal connected to the power supply wire  14   b  and a second terminal connected to the power supply wire  14   a  via a switch  17   a.  The variable capacitor circuit  16  further includes a capacitor C 13  having a first terminal connected to the power supply wire  14   b  and a second terminal connected to the power supply wire  14   a  via a switch  17   b.  In other words, the variable capacitor circuit  16  includes a first set of the capacitor C 12  and the switch  17   a  and a second set of the capacitor C 13  and the switch  17   b,  with each set being connected in parallel between the power supply wires  14   a  and  14   b.  In the first embodiment, the capacitance value of the capacitor C 12  is set to 10 pF, and the capacitance value of the capacitor C 13  is set to 20 pF. The switches  17   a  and  17   b  are respectively activated and inactivated by single bit control signals SW 1  and SW 2  provided from the controller  12 . The control signal SW 1  corresponds to the lower rank bit of control data CD having two bits, and the control signal SW 2  corresponds to the higher rank bit of the control data CD.  
         [0038]     The switches  17   a  and  17   b  are respectively activated when the control signals SW 1  and SW 2  have an L level and inactivated when the control signal SW 1  and SW 2  have an H level.  
         [0039]     Therefore, the state of the switches  17   a  and  17   b  is controlled to be in one of four states, namely, states in which both switches  17   a  and  17   b  are activated, only the switch  17   a  is inactivated, only the switch  17   b  is inactivated, and both switches  17   a  and  17   b  are inactivated.  
         [0040]     Accordingly, the capacitance value of the variable capacitor circuit  16  is set to one of 0 pF, 10 pF, 20 pF, and 30 pF. Further, the total capacitance value of the capacitor C 11  and the variable capacitor circuit  16  is set to one of 50 pF, 60 pF, 70 pF, and 80 pF.  
         [0041]     Series-connected resistors R 13  and R 14  are connected in parallel to the signal processor  15  between the power supply wires  14   a  and  14   b.  In the first embodiment, for example, the resistor R 13  is set to have 100 kΩ, and the resistor R 14  is set to have 200 kΩ. Therefore, the potential at node ND 1 , which is a connection point of the resistors R 13  and R 14 , is set to be 2 V, whereas the potential is 3 V at the power supply terminal t 11 .  
         [0042]     The internal circuit  11  further includes a monitor circuit  20 . The monitor circuit  20  detects the occurrence of power supply resonance caused by external noise N 2  in the power supply voltage supplied to the power supply wires  14   a  and  14   b.    
         [0043]     In the same manner as the power supply terminals t 11  and t 12 , high potential power supply voltage of 3 V and ground voltage of 0 V are respectively supplied to power supply terminals t 13  and t 14  of the monitor circuit  20 . The power supply voltages supplied to the power supply terminal t 13  and t 14  are supplied to a comparator  19  by power supply wires  18   a  and  18   b  (first and second monitor power supply wires).  
         [0044]     The power supply wire  18   a  includes an inductance L 13  and a resistor R 15  having substantially the same values as the inductance L 11  and the resistor R 11  of the power supply wire  14   a.  The power supply wire  18   b  includes an inductance L 14  and a resistor R 16  having substantially the same values as the inductance L 12  and the resistor R 12  of the power supply wire  14   b.  The inductances L 13  and L 14  and the resistors R 15  and R 16  are actually distributed constants but are illustrated as concentrated constants in  FIG. 3 .  
         [0045]     A capacitor C 14  (second fixed capacitor) is connected between the power supply wires  18   a  and  18   b  near the comparator  19  to stabilize the power supply voltage. The capacitance value of the capacitor C 14  is set to be sufficiently lower than the capacitor Cd 1 , which is located near the signal processor  15 . In the first embodiment, the capacitance value of the capacitor C 14  is set to be, for example, 0.1 pF. Therefore, power supply resonance caused by external noises N 2  having the same frequency does not occur in the power supply wires  18   a  and  18   b  at the same time as in the power supply wires  14   a  and  14   b.    
         [0046]     Resistors R 17  and R 18  (reference resistor) are connected in series between the power supply wires  18   a  and  18   b  near the comparator  19 . In the first embodiment, for example, the resistor R 17  is set to have 50 kΩ and the resistor R 18  is set to have 200 kΩ. Therefore, the potential at node ND 2  between the resistors R 17  and R 18  is set to 2.4 V when there is no power supply resonance in the power supply wires  18   a  and  18   b.    
         [0047]     Node ND 2  is connected to a negative input terminal of the comparator  19 . A positive input terminal of the comparator  19  is connected to node ND 1 . The comparator  19  generates an output signal Cout having an H level when the potential at the node ND 1  becomes greater than the potential at the node ND 2 .  
         [0048]     Therefore, the comparator  19  generates the output signal Cout having an L level when there is no power supply resonance in the power supply wires  14   a,    14   b,  and  18   a,    18   b  since node ND 1  has 2 V and node ND 2  has 2.4 V.  
         [0049]     The comparator  19  generates the output signal Cout having an H level when power supply resonance occurs in the power supply wires  14   a  and  14   b  and the potential at the node ND 1  changes to voltage exceeding 2.4 V, that is, when the potential at the power supply wire  14   a  exceeds 3.6V.  
         [0050]     In the internal circuit  11 , the resonance frequency f of each power supply wire  14   a  and  14   b,    18   a  and  18   b  is calculated from the equation of f=1/(2π√(LC)). Assuming that the inductances L 11 , L 12 , and L 13 , L 14  of 4 nH parasitizes the power supply wires  14   a,    14   b,  and  18   a,    18   b,  the resonance frequency f is approximately 199 MHz in the power supply wires  14   a  and  14   b  when both switches  17   a  and  17   b  are activated and the capacitance value between the power supply wires  14   a  and  14   b  is set to 80 pF.  
         [0051]     The resonance frequency f becomes approximately 213 MHz when the switch  17   a  is inactivated and the capacitance value between the power supply wires  14   a  and  14   b  is set to 70 pF. Further, the resonance frequency f becomes approximately 230 MHz when the switch  17   b  is inactivated and the capacitance value between the power supply wires  14   a  and  14   b  is set to 60 pF. Moreover, the resonance frequency f becomes approximately 252 MHz when both switches  17   a  and  17   b  are inactivated and the capacitance value between the power supply wires  14   a  and  14   b  is set to 50 pF.  
         [0052]     The resonance frequency f is set to 5.6 GHz in the power supply wires  18   a  and  18   b  since the capacitance value between the wires  18   a  and  18   b  is 0.1 pF. The resonance frequency of the power supply wires  14   a  and  14   b  thus does not coincide with the resonance frequency of the power supply wires  18   a  and  18   b.  Therefore, power supply resonance caused by common external noise N 2  does not occur in the power supply wires  14   a  and  14   b  at the same times as in the power supply wires  18   a  and  18   b.    
         [0053]     The output signal Cout of the comparator  19  is provided to the controller  12 . The controller  12  switches the activated and inactivated states of the switches  17   a  and  17   b  to suppress power supply resonance when provided with the output signal Cout having an H level from the comparator  19 , that is, when power supply resonance occurs in the power supply wires  14   a  and  14   b.    
         [0054]     When power supply resonance is suppressed and the output signal Cout of the comparator  19  falls to an L level, the controller  12  stores the double bit control data CD, which sets the state of the switches  17   a  and  17   b,  in a predetermined region of the memory  13 . If power supply resonance is not suppressed even switching the activated and inactivated states of the switches  17   a  and  17   b,  the controller  12  stores alarm data ARM in a predetermined region of the memory  13 . Further, when a clear signal CLR is provided from an external device (e.g., microcomputer), which is not shown in the drawings, the controller  12  resets the control data CD to “00”, resets the alarm data ARM to “0”, and sets “1” for clear data CLRD (not shown in  FIG. 2 ).  
         [0055]     The operation of the controller  12  will now be described with reference to  FIG. 4 . The controller  12  resets the memory  13  when first activated subsequent to mounting of the chip (semiconductor device  10 ). That is, the controller  12  resets the alarm data ARM to “0” and resets the control data CD to “00”.  
         [0056]     When normal operation starts, the controller  12  first determines whether or not the clear data CLRD is “1” (step  1 ). If the clear data CLRD is not “1”, the controller  12  reads the control data CD and the alarm data ARM from the memory  13  and provides the internal circuit  11  with the control signals SW 1  and SW 2  corresponding to the control data CD (step  2 ).  
         [0057]     Since the control data CD is “00”, the switches  17   a  and  17   b  of the internal circuit  11  are both activated and the capacitance value between the power supply wires  14   a  and  14   b  is set to 80 pF.  
         [0058]     The controller  12  then determines whether or not the read alarm data ARM is “1” (step  3 ). If the alarm data ARM is not “1”, the controller  12  then determines whether or not the output signal Cout of the comparator  19  has an H level (step  4 ). If the output signal Cout of the comparator  19  has an L level, the controller  12  continues the determination of the output signal Cout in step  4 .  
         [0059]     If the output signal Cout of the comparator  19  has an H level, that is, if power supply resonance caused by external noise N 2  is occurring in the power supply wires  14   a  and  14   b  in step  4 , the controller  12  determines whether or not the control data CD is “11” (step  5 ). Since the control data CD is “00”, the controller  12  proceeds to step  6 . In step  6 , the controller  12  adds 1 to the control data CD of “00” and generates the control data CD of “01” (step  6 ).  
         [0060]     As the control signal SW 1  is set to an H level in accordance with the updated control data CD, the switch  17   a  is inactivated and the capacitance value between the power supply wires  14   a  and  14   b  is changed to 70 pF.  
         [0061]     Subsequently, the controller  12  writes the updated control data CD of “01” to the memory  13  (step  7 ) and proceeds to step  4 . The controller  12  starts to continue the determination of the output signal Cout again in step  4  if the power supply resonance in the power supply wires  14   a  and  14   b  is resolved and the output signal Cout of the comparator  19  falls to an L level.  
         [0062]     If the output signal Cout of the comparator  19  remains at an H level regardless of the change in the capacitance value, the power supply resonance has not been resolved. Thus, the controller  12  proceeds to step  5  and then step  6 . The controller  12  further adds 1 to the control data CD of “01” to generate the control data CD of “10”.  
         [0063]     As the control signal SW 2  is set to an H level and the control signal SW 1  is set to an L level in accordance with the updated control data CD, the switch  17   a  is activated, the switch  17   b  is inactivated, and the capacitance value between the power supply wires  14   a  and  14   b  is changed to 60 pF.  
         [0064]     The controller  12  then writes the control data CD, which has been updated to “10”, in step  7  to the memory  13  and proceeds to step  4 .  
         [0065]     If the output signal Cout of the comparator  19  remains at an H level regardless of the change in the capacitance value, the power supply resonance has not been resolved. Thus, the controller  12  repeats steps  5  to  7 . That is, the controller  12  adds 1 to the control data CD of “10” again to generate the control data CD of “11” and writes the control data CD to the memory  13 . The capacitance value between the power supply wires  14   a  and  14   b  is then changed to 50 pF.  
         [0066]     If the power supply resonance has not been-resolved even though the capacitance value has been changed to 50 pF, the controller  12  determines that the control data CD is “11” in step  5  and proceeds to step  8 . The controller  12  sets the alarm data ARM to “1” and writes the alarm data ARM to the memory  13  in step  8 . Then, the controller  12  terminates the processes for determining and resolving power supply resonance.  
         [0067]     Further, if the clear data CLRD is “1” in step  1 , the controller  12  proceeds to step  9 . The controller  12  resets the alarm data ARM to “0” and resets the control data CD to “00” in step  9  and then proceeds to step  3 .  
         [0068]     The clear data CLRD is set to “1” when the clear signal CLR is provided to the controller  12 . The clear signal CLR is provided when power supply resonance caused by the external noise N 2  is not resolved even though the capacitance value is changed. In this case, a new capacitor is provided between the power supply wires  14   a  and  14   b  in addition to the capacitor C 11  and the capacitors C 12 , C 13 . Power supply resonance caused by the external noise N 2  is resolved by repeating steps  3  to  7 .  
         [0069]     The semiconductor device  10  of the first embodiment has the advantages described below.  
         [0070]     (1) The monitor circuit  20  detects whether or not power supply resonance is occurring in the power supply wires  14   a  and  14   b  that supply power to the signal processor  15 . When the monitor circuit  20  detects power supply resonance, the controller  12  changes the capacitance value of the variable capacitor circuit  16  between the power supply wires  14   a  and  14   b  and to resolve the power supply resonance. This suppresses the power supply resonance caused by the external noise N 2  and prevents the power supply voltage from fluctuating.  
         [0071]     (2) The two capacitors C 12  and C 13 , which have different capacitance values, are connected in parallel between the power supply wires  14   a  and  14   b  by the switches  17   a  and  17   b  in the variable capacitor circuit  16 . The switches  17   a  and  17   b  are each activated and inactivated in response to the single bit control signals SW 1  and SW 2 . This enables the capacitance value between the power supply wires  14   a  and  14   b  to be changed among four values.  
         [0072]     (3) The alarm data ARM is stored in the memory  13  if power supply resonance cannot be resolved even though the variable capacitor circuit  16  changes the capacitance value. Therefore, the controller  12  may recognize that power supply resonance caused by external noise N 2  has not been resolved by reading the alarm data ARM.  
         [0073]     (4) The control data CD for setting the capacitance value required to resolve power supply resonance is stored in the memory  13 . Therefore, during reactivation of the system (semiconductor device  10 ), the capacitance value required to resolve power supply resonance is readily set based on the control data CD set during the previous activation.  
         [0074]      FIG. 5  is a schematic circuit block diagram of a monitor circuit  40  in a semiconductor device  30  according to a second embodiment of the present invention. In the second embodiment, the monitor circuit  20  (see  FIG. 3 ) of the first embodiment is replaced by the monitor circuit  40 . The monitor circuit  40  includes a DA converter  21  for generating reference voltage, which is supplied to the comparator  19 . Although not shown in  FIG. 5 , the semiconductor device  30  also includes other components such as the controller  12 , the memory  13 , the signal processor  15 , the variable capacitor circuit  16 , in the same manner as in the first embodiment.  
         [0075]     An output signal of the DA converter  21  is provided to the negative input terminal of the comparator  19 . A digital input signal is provided to the DA converter  21  from an external device (not shown) such as a microcomputer. The positive input terminal of the comparator  19  is connected to node ND 1  (see  FIG. 3 ) in the same manner as in the first embodiment.  
         [0076]     In the second embodiment, the reference voltage (analog voltage) supplied to the comparator  19  may be freely set by adjusting the digital input signal provided to the DA converter  21 . Therefore, the reference voltage for determining the occurrence of power supply resonance in the power supply wires  14   a  and  14   b  may be set as required.  
         [0077]      FIG. 6  is a schematic block circuit diagram of an internal circuit  60  in a semiconductor device  50  according to a third embodiment of the present invention. The internal circuit  60  includes two signal processors  22   a  and  22   b  in the third embodiment. Although not shown in  FIG. 6 , the semiconductor device  50  also includes other components such as the controller  12  and the memory  13  in the same manner as in the first embodiment.  
         [0078]     Power supply voltages (3 V and 0 V) are supplied to the signal processor  22   a  from power supply terminals t 1  and t 2  via power supply wires  23   a  and  23   b  (first and second power supply wires). The power supply voltages (3 V and 0 V) are supplied to the signal processor  22   b  from power supply terminals t 1   a  and t 2   a  via power supply wires  24   a  and  24   b  (third and fourth power supply wires). The power supply wires  23   a  and  23   b  are arranged independent from the power supply wires  24   a  and  24   b.  Inductances L 15 , L 16 , L 17 , and L 18  and resistors R 19 , R 20 , R 21 , and R 22  parasitize the power supply wires  23   a,    23   b,    24   a,  and  24   b,  respectively.  
         [0079]     A capacitor C 15  (fixed capacitor) and a variable capacitor circuit  25   a  are arranged in parallel between the power supply wires  23   a  and  23   b  to stabilize the power supply voltage. Further, a capacitor C 16  (fixed capacitor) and a variable capacitor circuit  25   b  are arranged in parallel between the power supply wires  24   a  and  24   b  to stabilize the power supply voltage. The variable capacitor circuits  25   a  and  25   b  are each configured to be similar to the variable capacitor circuit  16  of the first embodiment.  
         [0080]     Since the power supply wires  23   a,    23   b,    24   a,  and  24   b  are independent from each other, the inductances L 15 , L 16 , L 17 , and L 18  parasitizing the power supply wires  23   a,    23   b,    24   a,  and  24   b  also differ from each other. The frequency of power supply resonance caused by external noise N 2  in the power supply wires  23   a  and  23   b  differ from the frequency of power supply resonance caused by external noise N 2  in the power supply wires  24   a  and  24   b.    
         [0081]     Therefore, the semiconductor device  50  of the third embodiment includes a first monitor circuit  61   a  for detecting the occurrence of power supply resonance in the power supply wires  23   a  and  23   b,  and a second monitor circuit  61   b  for detecting the occurrence of power supply resonance in the power supply wires  24   a  and  24   b.  The monitor circuits  61   a  and  61   b  are each configured to be similar to the monitor circuit  20  of the first embodiment. More specifically, the monitor circuit  61   a  compares the potential at node ND 1   a  between the resistors R 23   a  and R 23   b  with the reference voltage to generate an output signal Cout 1   a  indicating the comparison result. The monitor circuit  61   b  compares the potential at the node ND 1   b  between the resistors R 24   a  and R 24   b  with the reference voltage to generate an output signal Cout 1   b  indicating the comparison result. The controller  12  then separately controls the capacitance values of the variable capacitor circuits  25   a  and  25   b  based on the output signals Cout 1   a  and Cbut 1   b  of the monitor circuits  61   a  and  61   b.    
         [0082]     As a result, in the third embodiment, power supply resonance occurring in the power supply wires  23   a  and  23   b  connected to the signal processor  22   a  is suppressed based on the capacitance value set in the variable capacitor circuit  25   a.  Further, power supply resonance occurring in the power supply wires  24   a  and  24   b  connected to the signal processor  22   b  is suppressed based on the capacitance value set in the variable capacitor circuit  25   b.    
         [0083]      FIG. 7  is a schematic block circuit diagram of an internal circuit  80  in a semiconductor device  70  according to a fourth embodiment of the present invention. In the internal circuit  80  of the fourth embodiment, the variable capacitor circuit  16  of the first embodiment is replaced by a variable capacitor circuit  81 . Although not shown in  FIG. 7 , the internal circuit  80  includes a monitor circuit similar to the monitor circuit  20  of the first embodiment (or the monitor circuit  40  of the second embodiment). The semiconductor device  70  also includes other components such as the controller  12  and the memory  13  in the same manner as the first embodiment.  
         [0084]     As shown in  FIG. 7 , the variable capacitor circuit  81  includes a set of a capacitor C 17  and a switch  26  connected between the power supply wires  18   a  and  18   b.  The capacitor C 17  and the switch  26  are connected in series. The switch  26  is activated and inactivated in response to a single bit control signal SW 1  from the controller  12 . The capacitor C 17  is electrically connected to the power supply wires  18   a  and  18   b  when the switch  26  is activated and disconnected when the switch  26  is inactivated.  
         [0085]     Therefore, in the fourth embodiment, the value of the capacitor connected between the power supply wires  18   a  and  18   b  is set to either the value of the capacitor C 11  or the total value of the capacitors C 11  and C 17 . That is, if the power supply resonance caused by external noise N 2  is not resolved with only the capacitor C 11 , the switch  26  is activated so that the power supply resonance is resolved based on the total value of the capacitors C 41  and C 17 . In the fourth embodiment, power supply resonance is resolved while minimizing the area occupied by the variable capacitor circuit  81  in the semiconductor device  70 .  
         [0086]     It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.  
         [0087]     The comparator  19  need not be configured as in the manner of each of the above embodiments. For example, a comparator may be configured so that it detects power supply resonance when the potential at node ND 1  becomes less than the potential at node ND 2 .  
         [0088]     In the first embodiment, the capacitance values of the capacitors C 12  and C 13  of the variable capacitor circuit  16  may be the same.  
         [0089]     In the first embodiment, the variable capacitor circuit  16  may include three or more sets of a capacitor and switch, which are connected in series between the power supply wires  14   a  and  14   b,  with each set connected in parallel between the power supply wires  14   a  and  14   b.    
         [0090]     The monitor circuits  61   a  and  61   b  of the third embodiment may be configured to be similar to the monitor circuit  40  of the second embodiment.  
         [0091]     In the first embodiment, the capacitor C 11  may be omitted, and power supply resonance may be suppressed only with the variable capacitor circuit  16 . In the third embodiment, the capacitors C 15  and C 16  may be omitted, and power supply resonance may be suppressed with only the variable capacitor circuits  25   a  and  25   b.    
         [0092]     The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.