Abstract:
A high frequency differential amplifier with a circuit topology which ensures that bias currents of the high transconductance differential transistors with minimum channel length are exactly equal, i.e., each differential transistor carries exactly half of the total current I 0  of the differential amplifier. This is achieved by coupling each differential transistor via its own current source to the reference potential. To insure a good match between the current sources, the current source devices are made with long channel lengths. Impedances are coupled between the junctions of each differential transistor pair and its current source to insure good AC gain. For the variable gain differential amplifier the spread in the gain control characteristics is reduced by making the aspect ratio of the first pair of differential transistors larger than that of the second pair of differential transistors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to high frequency differential amplifiers and more particularly to high frequency MOS differential amplifiers having high transconductance, matched differential devices, and minimal DC offset at the output. 
     2. Description of the Related Art 
     While designing high frequency amplifiers in MOS technology, designers are often forced to use small or even the minimum channel length of the technology for the amplifier transistors. This is needed to meet the high transconductance required by the application. However, if the amplifier is differential, serious problems can be encountered. While using small channel lengths, the matching of the differential devices is poor due to etching inaccuracies in the channel length. This results in DC offsets, low common mode rejection ratio (CMRR) and poor differential performance. For variable gain amplifiers based on the Gilbert Cell, the mismatches can lead to a lot of spread in the variable gain characteristics. The nicely balanced performance of the Gilbert Cell is also affected. 
     FIGS. 1 and 3 show a high frequency fixed and a Gilbert Cell based variable gain amplifier, respectively, having inputs In 1 , In 2  and outputs Out 1 , Out 2 . A power source V DD  connects via two load resistors  11  and  12  (R L ) to the drain of M 1 , M 2  and M 3 , M 4 . A series resistance  21 ,  22 ,  21 ′,  22 ′ (R S  ) couples each transistor via a current source  51 ,  52  (IS), with current I 0  (for FIG.  3 : I 0 +Δ, I 0 −ΔI 0 ), to ground. The current splits unequally between the differential transistors M 1 , M 2  and M 3 , M 4  if there are small differences in their channel lengths. This results in widely different transconductances between them and as a consequence the CMRR and differential and other balanced characteristics are spoilt. The unequal currents also cause DC offset at the amplifier outputs. As a result, the output signal handling capability is reduced. 
     FIGS. 2 and 4 a,    4   b  show how multiple stages of such amplifier stages have to be connected. Capacitive coupling  91 ,  92 ,  91 ′,  92 ′,  91 ″,  92 ″, (C C  ) between stages and at the input is used to prevent propagation and further amplification of DC offset appearing at the outputs of every amplifying stage. However, parasitic capacitances  71 ,  72 ,  71 ′,  72 ″,  71 ″,  72 ″, (C P  ) on the bottom plate of the coupling capacitors C C  load the outputs of the amplifier stages and this adversely affects the high frequency response of the overall amplifier. In addition, gate resistors  81 ,  82 ,  81 ′,  82 ′ (R G  )are coupled between a second power supply V GG  and the inputs of each amplifier stage. 
     Transistors M 1 , M 3  and M 2 , M 4  of FIG. 4 a  are coupled via load resistors  11 ,  12  (R L ), respectively, to power supply V DD . Transistors M 5 , M 7  and M 6 , M 8  of FIG. 4 b  are coupled via load resistors  11 ′,  12 ′ (R L ), respectively, to power supply V DD . 
     Note that throughout this document the same numerals and characters designate the same component. 
     Since usage of minimum channel length devices cannot be ruled out for high frequency applications, a topology modification to the conventional differential amplifier structures is needed to minimize the above problems. 
     Related art referring to differential amplifiers and Gilbert Cells are: U.S. Pat. No. 5,880,631 (Sahota), U.S. Pat. No. 5,949,286 (Jones), U.S. Pat. No. 6,111,463 (Kimura), and U.S. Pat. No. 6,229,395 (Kay) all use a single current source for a differential transistor pair with the disadvantages discussed above. 
     It should be noted that none of the above-cited examples of the related art connect each differential transistor only to a current source and from there to a reference voltage nor do they insure that the bias current for each differential transistor is exactly I 0 /2 of the transistor pair. 
     SUMMARY OF THE INVENTION 
     It is an object of at least one embodiment of the present invention to provide high frequency differential amplifier circuits and methods which utilize amplifier transistors using a small or minimum channel lengths of the technology. 
     It is another object of the present invention to provide high transconductance for those amplifier transistors. 
     It is yet another object of the present invention to provide excellent matching of the transconductance of the differential amplifier transistors. 
     It is still another object of the present invention to provide circuits and methods which are not sensitive to DC offsets at the inputs to those differential amplifiers. 
     It is a further object of the present invention to provide circuits and methods which do not cause DC offsets at the outputs of the differential amplifier. 
     It is yet a further object of the present invention to maintain good common mode rejection ratio (CMRR) at the signal frequencies of interest. 
     It is still a further object of the present invention to provide AC differential gains equal to those of the prior art. 
     It is lastly an object of the present invention to reduce the spread in the gain control characteristics for variable gain amplifiers. 
     These and many other objects have been achieved by a circuit topology which ensures that bias currents of the differential transistors are exactly equal, i.e., each differential transistor carries half of the total current I 0  of the differential amplifier. That is, the current in each differential transistor is I 0 /2. To insure a good match between the current sources, the current source devices are made with long channel lengths. This causes the DC bias conditions to be perfectly determined and the circuits are not sensitive to DC offsets at the outputs. Another benefit is that the transconductance of the differential devices is nearly equal. Any small differences are due to slightly different aspect ratios. The spread in the gain control characteristics for the variable gain differential amplifier can also be further reduced by making the aspect ratio of the first transistor pair larger than that of the second transistor pair. To insure good AC gain, impedances are coupled between the junctions of each differential transistor pair and its current source. 
     These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
     In the following, first and second conductivity types are opposite conductivity types, such as N and P types. Each embodiment includes its complement as well. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a high frequency fixed gain differential amplifier of the prior art. 
     FIG. 2 is a circuit diagram of a multistage high frequency fixed gain differential amplifier of the prior art. 
     FIG. 3 is a circuit diagram of a high frequency variable gain differential amplifier of the prior art. 
     FIGS. 4 a  and  4   b  are circuit diagrams of a multistage high frequency variable gain differential amplifier of the prior art. 
     FIG. 5 is a circuit diagram of a high frequency fixed gain differential amplifier of the preferred embodiment of the present invention. 
     FIG. 6 is a circuit diagram of a multistage high frequency fixed gain differential amplifier of the preferred embodiment of the present invention. 
     FIG. 7 is a circuit diagram of a high frequency variable gain differential amplifier of the preferred embodiment of the present invention. 
     FIGS. 8 a  and  8   b  are circuit diagrams of a multistage high frequency variable gain differential amplifier of the preferred embodiment of the present invention. 
     FIG. 9 is a special case of FIG.  5 . 
     FIG. 10 is a special case of FIG.  7 . 
     FIG. 11 is a block diagram of the method of providing a high frequency fixed gain differential amplifier. 
     FIG. 12 is a block diagram of the method of providing a high frequency variable gain differential amplifier. 
     FIG. 13 is a circuit diagram of a high frequency fixed gain differential amplifier of another preferred embodiment of the present invention utilizing metal-insulator-metal (MIM) capacitors. 
     FIG. 14 is a circuit diagram of a high frequency variable gain differential amplifier of another preferred embodiment of the present invention utilizing MIM capacitors. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIGS. 5 and 7 show the improved and modified topology corresponding to FIGS. 1 and 3 respectively. It can be observed that for the new topology, the bias currents are exactly equal to I 0 /2 each—exactly what is required. The current sources  51 ,  51 ′ and  52 ,  52 ′ (IS), each with current I 0 /2, can be implemented with long channel length devices to ensure good matching between them. In such a case, there is also no DC offset at the outputs. In other words, the DC bias conditions are perfectly determined. It can also be observed that the circuits are not sensitive to DC offsets at the inputs. 
     The transconductance g m  of the differential devices is nearly equal and the difference between the transconductances is not greater than 2.5%. The 2.5% is based on the fact that a difference in L (the length of the transistor channel) causes the threshold voltage V TH  of the differential transistors to be different. The smaller L is, the smaller V TH  is. With equal V GS  (the gate-source voltage), the current I D  (drain current of the transistor) can be different by about 15-20% for a 5% difference in L. For equal I D , the transconductance difference is 2.5% for a 5% difference in L—which is about the maximum expected. Therefore, good common mode rejection ratio (CMRR) and other differential and balanced characteristics can be maintained at signal frequencies. The AC differential gains are also the same as in FIGS. 1 and 2, provided the impedance of  41 ,  41 ′ and  42 ,  42 ′ (C S /2) is small compared to that of series resistance  31 ,  31 ′ and  32 ,  32 ′ ( 4 R S ) at signal frequency. Parasitic capacitances  71 ,  71 ′ and  72 ,  72 ′ (C P ) at the bottom plate of C S /2 actually help to improve the high frequency response of the amplifiers by reducing the impedance at the sources of the differential transistors. 
     Due to reduction in the differences in transconductances, the spread in the gain control characteristics for the variable gain amplifier is also reduced. This spread can be further reduced by making the aspect ratio of the M 1 -M 2  pair larger than that of the M 3 -M 4  pair of FIG.  7 . 
     FIGS. 6 and 8 show how multiple stages of the new amplifiers can be cascaded. Since the circuits are not sensitive to DC offsets at their outputs and inputs, direct coupling can be employed. This saves layout area and also does not degrade the high frequency response of the overall amplifier as does the related art in FIGS. 2 and 4. Simulations performed for all of the inventive circuits described above have verified the above claims and findings. 
     We now describe in more detail the circuit of FIG. 5 which is a modified Gilbert Cell differential amplifier. The drain of a first NMOS transistor is coupled via a first load resistor  11  (R L ) to a positive power supply V DD , where the junction of M 1  and the first resistor  11  provides a first output Out 1 . The source of transistor M 1  is coupled via a first current source  51 , with current I 0 /2to a second power supply GND (typically ground) less positive than the first power supply. A second NMOS transistor M 2 , designed to be identical to transistor M 1 , is similarly connected via a second load resistor  12  (R L ), equal in resistance to first resistor  11 , to power supply V DD , where the junction of M 2  and the second resistor  11  provides a second output Out 2 . The source of transistor M 2  is coupled via a second current source  52  (IS) and current I 0 /2, identical to first current source  51 , to GND. Gates of transistors M 1 , M 2  are in communication with first and second input terminals In 1 , In 2 , respectively. Outputs Out 1  and Out 2  provide a fixed gain differential output signal based on a first and a second input signal applied to input terminals In 1  and In 2 . As already discussed earlier, current sources IS are implemented in long channel length transistors thus minimizing the effects of channel length variations, thereby generating equal bias currents in all current sources. This requirement applies equally to all subsequently disclosed differential amplifier circuits as illustrated in FIG. 6 to FIG. 10, wherein the first and second current sources IS of the second differential amplifiers have the reference characters  51 ′ and  52 ′, respectively. 
     Frequency compensating means are connected between the sources of transistors M 1  and M 2 . These frequency compensating means may comprise two capacitors  41  and  42  (C S /2), where the bottom plate of each capacitor is connected to the source of M 1  and M 2 , as illustrated in FIG. 9, or it may comprise two circuits each consisting of a series resistor  31  or  32 ,  31 ′,  32 ′ ( 4 R S ) in series with capacitor  41  or  42 ,  41 ′,  42 ′ (C S /2), respectively, serially connected between M 1  and M 2 , M 3  and M 4 , M 5  and M 6 , M 7  and M 8 , as illustrated in FIG. 5 to FIG.  8 . The bottom plate of the first capacitor  41  is connected to the source of M 1  and the bottom plate of the second capacitor  42  is connected to the source of M 2 . The value of each capacitor C S /2 is:            C   S     /   2     &gt;&gt;     1     8        π        (       R   S     +     1     g   m         )            f   S                                
     where R S  is the resistance of the source of a MOS transistor, f S  is the signal frequency, and g m  is the transconductance of either M 1  or M 2 . 
     Parasitic capacitances  71 ,  71 ′ and  72 ,  72 ′ (C P ) are coupled between the plates of first and second capacitors  41 ,  41 ′ and  42 ,  42 ′, respectively, and ground (GND) and are illustrated in FIG. 5 to FIG. 10 where the transistors shown are NMOS transistors. It is understood by those skilled in the art that PMOS transistors could be used as well, in which case the sources will be substituted by drains and vice versa. Other types of switching devices can be used as well such as, but not limited to, npn or pnp bipolar transistors. The term channel length with reference to current sources will then have to be replaced by an equivalent device parameter. 
     FIG. 6 illustrates a multistage high frequency fixed gain differential metal oxide semiconductor (MOS) amplifier which comprises inputs In 1  and In 2  and outputs Out 1  and Out 2 , and a first and a second differential amplifier stage, each of these stages and inputs and outputs identical to the amplifier of FIG.  5 . The only difference is that the transistors of the second stage are labeled M 3  and M 4  for ease of identification. In addition, transistors M 3  and M 4  are coupled via resistors  11 ′ and  12 ′ (R L ) to power supply V DD . The two stages are coupled together by direct-coupling of the gate G 1  and G 2  of M 3  and M 4  to node A and node B of the first differential amplifier, respectively. Inputs G 1 , G 2  of the first differential amplifier stage are coupled to inputs In 1 , In 2 , respectively. Nodes A, B of the second differential amplifier stage are coupled to outputs Out 1 , Out 2 , respectively. The two differential amplifier stages together provide a fixed gain at outputs Out 1 , Out 2  based on signals applied to inputs In 1 , In 2 . 
     FIG. 7 illustrates a high frequency variable gain differential metal oxide semiconductor (MOS) amplifier which comprises a first and a second differential amplifier stage, each having an input G 1  and G 2  and outputs node A and node B. Both output nodes A are coupled together and output nodes B are coupled together. Both stages are similar to the differential amplifier circuit of FIG. 5 except that nodes A share a load resistor  11  (R L ) and that nodes B share a load resistor  12  (R L ) . Identical to FIG. 5 is the arrangement of the frequency compensating means and the parasitic capacitors  71 ,  71 ′ and  72 ,  72 ′ (C P ). As in FIG. 6, the transistors of the second stage are labeled M 3  and M 4  for ease of identification. Inputs G 1  and G 2  of the first differential amplifier stage are coupled to inputs In 1  and In 2 , respectively. Inputs G 1  and G 2  of the second differential amplifier stage are coupled to inputs In 2  and In 1 , respectively, i.e., in reverse order. Nodes B and A are coupled to outputs Out 1  and Out 2 , respectively. Each node A and B is coupled via a load resistor  11  and  12 , respectively, to a power supply V DD . The first and second differential amplifier stage together provide a variable gain at outputs Out 1  and Out 2  for the signals applied to inputs In 1  and In 2 . 
     The aspect ratio of the M 1 -M 2  pair is larger than that of the M 3 -M 4  pair in FIG. 7 as discussed earlier. Th relationship is:            (     W   L     )                   M1     =         (     W   L     )                   M2     =       m                   (     W   L     )                   M3     =     m                   (     W   L     )                   M4                                
     where W is the width and L is the length of a MOS transistor channel, and where M 1 , M 2 , M 3 , and M 4  designate the transistors of the circuit of FIG.  7 . 
     Typically, m ranges from 2 to 6. This range is derived as follows. Let aspect ratios of M 1 , M 2  be m(W/L) and those of M 3 , M 4  be (W/L). The transconductance of a MOS transistor is given by 
     
       
           g   m ={square root over (2 I   D   μC   OX   W/L )}  (1) 
       
     
     using eq. (1), the gain of the variable amplifier is given by              Av   =         (       g   m1     -     g   m3       )                     R   L       =       g   m0            R   L          [       m     -           I   0     -     Δ                   I   0             I   0     +     Δ                   I   0               ]                   (   2   )                                
     where 
     
       
           g   m0 ={square root over (( I   0   +ΔI   0 )μ C   OX W/L)}  (3) 
       
     
     It is seen from eq. (2) that the gain Av is a function of ΔI 0 . From eq. (2), the maximum value of Av is g m1 R L , when ΔI 0max =I 0  From eq. (2), the minimum value of Av is 0, when                Δ                   I     0      min         =         1   -   m       1   +   m                       I   0               (   4   )                                
     The most sensitive part of the gain-control characteristic is just above Av=0 as the gain is a very strong function of ΔI 0  there. Again, the circuitry which generates ΔI 0  is not very accurate generating ΔI 0 =0 because of DC offsets. But (4) shows that for m=1, ΔI 0min =0. That is why the gain spreads can be more for low Av, if m=1. However, if m=6, eq. (4) shows that ΔI 0min =−(5/7)I 0  and the effect of gain spread is reduced at low gain. In this case, the condition ΔI 0 =0 happens at higher gain, where the gain-control characteristic is not a very strong function of ΔI 0 , and the effects of DC offset are not too great. 
     The aspect ratio of M 1 , M 2  cannot be increased beyond a limit because its parasitic capacitance will increase, affecting high frequency operation. Therefore, those of M 3 , M 4  have to be reduced by increasing m. It can also be observed from eq. (4) that ΔI 0min  saturates at −I 0  for large values of m. The maximum value of m is also limited by the minimum dimensions allowed by the technology. 
     The currents flowing through the current sources IS of transistors M 1  and M 2  are equal and are:            I   0     +     Δ                   I   0         2                          
     The currents flowing through the current sources IS of transistors M 3  and M 4  are equal and are:            I   0     -     Δ                   I   0         2                          
     FIGS. 8 a  and  8   b  illustrate a multistage high frequency variable gain differential metal oxide semiconductor (MOS) amplifier which comprises a first variable gain differential amplifier (FIG. 8 a ) and a second variable gain differential amplifier (FIG. 8 b ), each identical to the circuit of FIG.  7 . Gates G 1  and G 2  of transistors M 1  and M 2  of the first variable gain differential amplifier are connected to inputs In 1  and In 2 , respectively. Gates G 1  and G 2  of transistors M 5  and M 6  of the second variable gain differential amplifier are direct-coupled to node B and node A of the first variable gain differential amplifier, respectively. Nodes B and A of the second variable gain differential amplifier are coupled to outputs Out 1  and Out 2 , respectively. The first and second variable gain differential amplifier together provide a variable gain at outputs Out 1  and Out 2  for the signals applied to inputs In 1  and In 2 . The currents flowing through the current sources IS of transistors M 1  to M 8  of both variable gain differential amplifiers are identical to those of the circuit of FIG.  7 . The gain is varied by adjusting ΔI 0  in the range              1   -   m       1   +   m                       I   0       &lt;     Δ                   I   0       &lt;     I   0                            
     FIG.  9  and FIG. 10 are special cases of FIG.  5  and FIG. 7, respectively, where R S =0. Everything else is the same. 
     We now refer to FIG.  13  and FIG. 14, representing another preferred embodiment of the present invention. FIG. 13 is a variation of FIG. 5, and FIG. 14 is a variation of FIG. 7, where the frequency compensating means comprises a serial combination of a first series resistive means  61  (Rs/2), a capacitor  101  (Cs), and a second series resistive means  62  (Rs/2), respectively, coupled between the sources of transistors M 1 , M 2  and with regards to FIG. 14 also between the sources of transistors M 3 , M 4 , where the frequency compensating means comprises series resistive means  61 ′, capacitor  101 ′, and series resistive means  62 ′. The embodiment as shown in FIG.  13  and FIG. 14 is the preferred embodiment for 0.35 μm and 0.18 μm CMOS technologies where metal-insulator-metal (MIM) capacitors are available for capacitor Cs. These capacitors have the same area efficiency as the standard poly-insulator-poly (PIP) capacitors but have negligible bottom plate parasitic capacitances. Parasitic capacitances C P  are, therefore, not shown. Otherwise, the circuits are the same. It is obvious to those skilled in the art that the above serial combination of a first series resistive means  61  (Rs/2), a MIM capacitor Cs, and a second series resistive means  62  (Rs/2) is equally applicable to the multistage high frequency fixed gain differential amplifier (FIG. 6) and the multistage high frequency variable gain differential amplifier (FIG. 8 a  and FIG. 8 b ). 
     With reference to FIG. 11, we now describe the method of creating a high frequency fixed gain differential amplifier, as illustrated in FIG. 5, which has bias currents exactly equal to I 0 /2 for each of the two transistors M 1  and M 2 , has no DC offset at the outputs, is not sensitive to DC offsets at the inputs and maintains good CMRR. 
     In BLOCK  1  a pair of MOS transistors is arranged into a differential amplifier configuration, where one end of each of the MOS transistors is coupled by identical resistive means to a first power supply. 
     In BLOCK  2  the other end of each of the MOS transistors is coupled via identical current sources to a second power supply. 
     In BLOCK  3  input signals are applied to the control gate of each of the MOS transistors. 
     In BLOCK  4  an amplified fixed gain differential output signal is received at each junction of the MOS transistor and the resistive means. 
     BLOCK  5  describes that by minimizing the effects of channel length variations through long channel length transistors of the current sources equal bias currents are generated in both current sources. 
     In BLOCK  6  frequency compensating means are coupled between the other end (bottom end) of the pair of MOS transistors. Frequency compensating means may comprise capacitive means coupled serially with resistive means, or capacitive means only. 
     With reference to FIG. 12, we now describe the method of creating a high frequency variable gain differential amplifier, as illustrated in FIG. 7, which has bias currents exactly equal to (I 0 +ΔI 0 )/2 for each of the two transistors M 1  and M 2  of a first differential amplifier stage and bias currents exactly equal to (I 0 −ΔI 0 )/2 for each of the two transistors M 3  and M 4  for a second differential amplifier stage, has no DC offset at the outputs, is not sensitive to DC offsets at the inputs and maintains good CMRR. 
     BLOCK  1  creates a Gilbert Cell comprised of four MOS transistors (two pairs), two load resistors, two inputs, and two output nodes, where sources (if NMOS transistors) of the four MOS transistors are not joined. 
     In BLOCK  2  each individual source of the four MOS transistors is coupled via identical current sources to a common reference voltage. 
     In BLOCK  3  the first and the second input signal is applied to a first and a second control gate of the second pair of MOS transistors, respectively. 
     In BLOCK  4  the first and the second input signal is applied to a second and a first control gate of the second pair of MOS transistors, respectively. 
     In BLOCK  5  an amplified variable gain differential output signal is received between the two output nodes. 
     BLOCK  6  describes that by minimizing the effects of channel length variations through long channel length transistors of the current sources equal bias currents are generated in both sets of current sources. 
     In BLOCK  7  frequency compensating means are coupled between the other end of each pair of MOS transistors. Frequency compensating means may comprise capacitive means coupled serially with resistive means, or capacitive means only. 
     Regarding FIG.  11  and FIG. 12, it is understood by those skilled in the art that, aside from NMOS transistors, PMOS transistors could be used as well, in which case sources will be substituted by drains and vice versa. Other types of switching devices can be used as well such as, but not limited to, npn or pnp bipolar transistors. The term channel length with reference to current sources will then have to be replaced by an equivalent device parameter. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.