Abstract:
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.

Description:
TECHNICAL FIELD 
     The present technology is directed to packaging semiconductor devices, such as memory and processors, and several embodiments are directed to package-on-package assemblies that have high density interconnect arrays. 
     BACKGROUND 
     Packaged semiconductor dies, including memory chips, microprocessor chips, logic chips and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, imager devices and other circuitry, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry. 
     Semiconductor manufacturers continually reduce the size of die packages to fit within the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. The dies in such vertically-stacked packages can be interconnected by electrically coupling the bond pads of the individual dies with the bond pads of adjacent dies using through-silicon vias (TSVs). 
     Another approach for increasing the power or capacity of a system is to vertically stack separate packages in a package-on-package assembly (POP assembly) in which each package can have one or more vertically stacked dies. Conventional POP assemblies have a bottom package that includes a bottom substrate and a bottom die, a top package that includes a top substrate with a top die, and a plurality of large solder balls that electrically connect the bottom and top packages. Although such POP assemblies are useful and relatively inexpensive to manufacture, they are not well suited for high-density applications that require a large number of input/output connections in a small footprint. For example, conventional through mold via and solder ball interconnects are limited to a pitch of 300 μm (e.g., spacing between interconnects of 300 μm) because large solder balls require a significant amount of lateral real estate. This is not suitable for many applications that require a pitch of no more than 150 μm. Therefore, it would be desirable to develop a POP assembly that can provide suitably tight pitches to accommodate advanced devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic cross-sectional view of a semiconductor package-on-package assembly in accordance with an embodiment of the present technology. 
         FIG. 1B  is a schematic top view of the semiconductor package-on-package assembly shown in  FIG. 1A  taken along line  1 B- 1 B. 
         FIGS. 2A-2C  are schematic cross-sectional views illustrating a method of forming a semiconductor package-on-package assembly in accordance with an embodiment of the present technology. 
         FIG. 3  is a schematic cross-sectional view of a semiconductor package-on-package assembly in accordance with another embodiment of the present technology. 
         FIGS. 4A-4D  are schematic cross-sectional views illustrating a method of forming a semiconductor package-on-package assembly in accordance with an embodiment of the present technology. 
     
    
    
     DETAILED DESCRIPTION 
     Specific details of several embodiments of stacked semiconductor die packages and methods of manufacturing such die packages are described below. The term “semiconductor device” generally refers to a solid-state device that includes semiconductor material. A semiconductor device can include, for example, a semiconductor substrate, wafer, or die that is singulated from a wafer or substrate. Throughout the disclosure, semiconductor devices are generally described in the context of semiconductor dies; however, semiconductor devices are not limited to semiconductor dies. 
     The term “semiconductor device package” can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor device package can also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise incorporated into the casing. The term “stacked package assembly” or “package-on-package assembly” (POP assembly) can refer to an assembly of one or more individual semiconductor device packages stacked on each other. 
     As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor device or package in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, vertical/horizontal and left/right can be interchanged depending on the orientation. 
       FIG. 1A  is a schematic top view of a POP assembly  100  (“assembly  100 ”) in accordance with an embodiment of the present technology, and  FIG. 1B  is a schematic cross-sectional view of the assembly  100  taken along line  1 B- 1 B. Referring to  FIG. 1A , the assembly  100  includes a first semiconductor device package  102   a  and a second semiconductor device package  102   b . The first semiconductor device package  102   a  includes a base substrate  110 , a high density interconnect array  120 , and a first semiconductor die  130 . The base substrate  110  has a first side  112 , a second side  114  opposite the first side  112 , and at least one layer  116  that has circuitry (e.g., copper traces and vias) for electrically coupling the first semiconductor die  130  to electrical connectors  118 . The base substrate  110 , for example, can be a circuit board or other type of substrate commonly used in semiconductor device packages. In the illustrated embodiment, the base substrate  110  has a die-attach region D and a perimeter region P. 
     The high density interconnect array  120  can include a plurality of stacked via structures  122  (identified individually as  122   a - 122   d  in  FIG. 1A ) configured to create an array of tall interconnects that are spaced laterally apart from one another by a short distance. The illustrated embodiment shows four separate stratums of stacked via structures  122   a - 122   d , but it will be appreciated that the interconnect array  120  can include any suitable number of stacked via structures  122  to provide the desired height “H” of the interconnect array  120 . The individual stacked via structures  122  can each include a matrix material  124  and a plurality of interconnect segments  126  that are arranged in the array. The individual stacked via structures  122  are formed sequentially such that the vertically aligned interconnect segments  126  are electrically coupled to each other to form individual interconnects  128 . By forming the interconnect segments  126  in a series of individual stratums of matrix material  124 , the interconnect segments  126  can be spaced closely together and have small diameters. Additionally, by stacking the individual interconnect structures  122 , the height (e.g., length) of the individual interconnects  128  can be much greater than the width of the interconnects  128  or the spacing between interconnects  128  so that the interconnect array  120  can have a height sufficient to accommodate the first semiconductor die  130  or a plurality of stacked first semiconductor dies  130 . As a result, the lateral distance between individual interconnects  128  (e.g., the pitch “p”) can be small. For example, the pitch p is generally less than 300 μm and more particularly approximately 50 μm-150 μm, which is significantly less than conventional interconnect arrays of POP assemblies. 
     Referring to  FIGS. 1A and 1B  together, the interconnect array  120  can be arranged in the perimeter region P of the base substrate  110  such that the interconnect array  120  defines a cavity  129  that exposes the die-attach region D at the front side  112  of the base substrate  110 . It will be appreciated that the interconnect array  120  can have different configurations, such as along only one side of the first semiconductor die  130 , a minimum of two sides (e.g. adjacent to each other at a corner or parallel to each other on opposite sides), or other configurations relative to the first semiconductor die  130 . 
     Referring back to  FIG. 1A , the first semiconductor die  130  is attached to the die-attach region D at the first side  112  of the base substrate  110 . The first semiconductor die  130  can be electrically coupled to the circuitry (not shown) of the base substrate  110  by the electric couplers  132  (e.g., solder balls or solder bumps) using flip-chip mounting technologies. The first semiconductor die  130  shown in  FIG. 1A  is accordingly a silicon-on-chip configuration. In the illustrated embodiment, the height H of the interconnect assembly  120  is greater than the height of the first semiconductor die  130  relative to the front side  112  of the base substrate  110 . In other embodiments, the height of the interconnect assembly  120  can be equal to or less than the height of the first semiconductor die  130  depending on the structures used to mount the second semiconductor device package  102   b  to the first semiconductor device package  102   a.    
     The second semiconductor device package  102   b  is attached to the interconnect assembly  120  and electrically coupled to the individual interconnects  128  by electric couplers  103  (e.g., solder balls or solder bumps). The second semiconductor device package  102   b  can include an interposer substrate  140  and at least one second semiconductor die  150  attached to the interposer substrate  140 . The interposer substrate  140  can be a circuit board or other member that includes circuitry for electrically coupling the second semiconductor die  150  to the interconnects  128  of the interconnect assembly  120 . The embodiment shown in  FIG. 1A  includes two semiconductor dies  150  that are encapsulated by a dielectric material  160 , such as a molding compound or other suitable encapsulant, and electrically coupled to the circuitry of the interposer substrate by electric couplers  152  (e.g., solder bumps or solder balls). 
     The second semiconductor device package  102   b  can be a memory device in which the semiconductor dies  150  are memory dies (e.g., DRAM, LPDRAM, SRAM, Flash, etc.), and the first semiconductor device package  102   a  can be a logic device, processor and/or another memory device. Additionally, even though each of the first and second semiconductor device packages  102   a  and  102   b  are shown having a single level of semiconductor dies, it will be appreciated that each of the device packages  102   a  and  102   b  can have a plurality of stacked dies within each package. For example, the first semiconductor device package  102   a  can have a plurality of first semiconductor dies  130  stacked on each other within the cavity  129  formed by the interconnect assembly  120 . In still other embodiments, the first semiconductor die  130  can be wire bonded to the base substrate  110  and/or the second semiconductor dies  150  can be wire bonded to the interposer substrate  140  instead of using flip-chip connectors such as solder bumps or solder balls. 
       FIGS. 2A-2C  are schematic cross-sectional views of a method for manufacturing a first semiconductor device package (such as the first semiconductor device package  102   a ) for a POP assembly (such as the POP assembly  100  shown in  FIG. 1A ) in accordance with an embodiment of the present technology.  FIGS. 2A-2B  more specifically illustrate stages of forming a high density array of interconnects in the first semiconductor device package. Like reference numbers refer to like components throughout  FIGS. 1-2C . 
       FIG. 2A  illustrates the method after the first interconnect structure  122   a  has been formed on or attached to the perimeter region P at the first side  112  of the base substrate  110 . The first interconnect structure  122   a  can be made by forming a stratum of the matrix material  124  and then forming (a) a plurality of discrete holes  125  and (b) a large opening  127  through the matrix material. The matrix material  124  can be a build-up film that is deposited on the base substrate  110  or a pre-impregnated fiberglass material (“prepreg”) formed apart from the substrate  110  and then attached to the perimeter region P. The holes  125  are arranged in the desired pattern of interconnects  128  of the interconnect assembly  120 , and the opening  127  is configured to provide access to the die-attach region D at the first side  112  of the base substrate  110 . The holes  125  and the opening  127  can be formed using laser drilling techniques or by photolithographic patterning and etching the matrix material  124 . The holes  125  and the opening  127  can alternatively be formed by stamping or punching a prepreg-type matrix material that is formed apart from the base substrate  110 . The discrete holes  125  are filled with a conductive material, such as copper, gold, tungsten, and/or other suitable highly conductive materials, to form the interconnect segments  126 . For example, copper can be deposited into the holes  125  using electroplating, electroless plating, or other suitable deposition techniques known in the semiconductor manufacturing arts. In one embodiment, copper can be plated in the holes by depositing a copper seed layer using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques, and then bulk plating copper on to the seed layer using electroplating or electroless plating processes. Tungsten, on the other hand, can be deposited using CVD, PVD or other techniques. 
     In one embodiment, each interconnect structure  122  is formed separately apart from the base substrate  110 . In such embodiments the conductive material is accordingly deposited into the holes  125  before the interconnect structure  122  is attached to the base substrate  110 . For example, the first interconnect structure  122   a  can be formed separately and then attached to the first side  112  of the base substrate. The other individual interconnect structures  122   b - d  can also be formed separately and sequentially stacked on the first interconnect structure  122   a . Alternatively, all of the individual interconnect structures  122  can be formed separately apart from the base substrate  110  and stacked on each other apart from the base substrate  110  such that the entire interconnect array  120  is preassembled before it is attached to the base substrate  110 . 
     In another embodiment, the individual interconnect structures  122  can be formed sequentially on or over the base substrate  110 . For example, the first interconnect structure  122   a  can be formed on the first surface  112  of the base substrate  110  by (a) depositing the matrix material  124  on the first surface  112 , (b) forming the holes  125  in the matrix material  124 , and then (c) filling the holes  125  with a conductive material to form the interconnects segments  126 . The second interconnect structure  122   b  can then be similarly formed on the first interconnect structure  122   a  (shown in dotted lines), and additional interconnect structures  122   c  and  122   d  can be formed sequentially (shown in dotted lines). The opening  127  can be formed either before or after filling the holes  125  with the conductive material. For example, the opening  127  can be formed in one stratum of the matrix material  124  before the next stratum of matrix material  124  is deposited. In an alternative embodiment, a plurality of the stratums of the matrix material  124  for the interconnect structures  122   a - d  can be deposited and processed to form the interconnect segments  126  in each stratum, and then the opening  127  can be formed through all of the stratums of matrix material  124  in a single step. 
       FIG. 2B  illustrates an embodiment of the method after the full interconnect assembly  120  has been completed. At this stage of the process, the interconnect assembly  120  has the desired height H so that the cavity  129  is deep enough to accommodate one or more of the second semiconductor dies  130 . The interconnect assembly  120 , and accordingly the individual interconnects  128 , are formed before the first semiconductor die  130  is attached to the die-attach area D of the base substrate  110 . 
       FIG. 2C  illustrates an embodiment of the method after the first semiconductor die  130  has been mounted to the base substrate  110  in the die-attach region D. In the illustrated embodiment, the first semiconductor die  130  is attached to the base substrate  110  and electrically coupled to the base substrate circuitry therein by a plurality of individual couplers  132  (e.g., solder balls or solder bumps). In one embodiment, an optional encapsulant or underfill material  134  can be deposited into the cavity  129  to encase the first semiconductor die  130 . The second semiconductor device package  102   b  ( FIG. 1A ) can subsequently be attached to the interconnect assembly  120  by the couplers  103  ( FIG. 1A ) to complete the POP assembly  100  shown in  FIG. 1A . 
       FIG. 3  is a schematic cross-sectional view illustrating a POP assembly  300  (“assembly  300 ”) in accordance with another embodiment of the present technology. The assembly  300  can include a first semiconductor device package  302   a  and a second semiconductor device package  302   b . The first semiconductor device package  302   a  can include a base substrate  310 , an interconnect array  320  located in a peripheral region of the base substrate  310 , and a first semiconductor die  330  located in a die-attach region of the base substrate  310  and electrically coupled to the base substrate  310  by couplers  332  (e.g., solder balls or solder bumps). The second semiconductor device package  302   b  can include an interposer substrate  340 , a second semiconductor die  350  electrically coupled to the interposer substrate  340  by couplers  352  (e.g., solder balls or solder bumps), and an encapsulant  360  covering the second semiconductor die  350 . The assembly  300  can further include electrical couplers  354  that electrically connect the second semiconductor device package  302   b  to the interconnect assembly  320 . 
     In the embodiment illustrated in  FIG. 3 , the interconnect assembly  320  has a plurality of interconnects  322  that are separated from one another by gaps  324 . The individual interconnects  322 , for example, can be freestanding conductive posts made from copper or other suitable electrically conductive materials. 
       FIGS. 4A-4C  are schematic cross-sectional views of a method for manufacturing the assembly  300  in accordance with an embodiment of the technology.  FIG. 4A  illustrates the method after a photo-imageable material  321  has been deposited onto the base substrate  310  and patterned to form a plurality of holes  323 . The pattern of holes  323  can be arranged to correspond to the configuration of the interconnects  322  of the interconnect assembly  320 . 
       FIG. 4B  illustrates the method after a conductive material, such as copper, has been deposited into the holes  323  to form the individual interconnects  322 . The conductive material can be deposited using electroplating, electroless plating, and/or other suitable deposition techniques used in the semiconductor arts. For example, in one embodiment a seed layer ( FIG. 4A ) can be deposited onto the top of the base substrate  310  using PVD or CVD techniques before the photo-imageable material  321  has been deposited. In such cases, the photo-imageable material  321  is then deposited onto the seed layer  311  ( FIG. 4A ). A bulk conductive material can then be electroplated onto the seed layer to fill the openings  323  ( FIG. 4B ). 
       FIG. 4C  illustrates the method after the photo-imageable material  321  has been removed to form the gaps  324  between the interconnects  322  and an open region  329  over the die-attach region of the base substrate  310 . The seed layer  311  ( FIGS. 4A and 4B ) is then removed from the top surface of the base substrate  310  such that the interconnects  322  are electrically isolated from each other. The interconnects  322  in the embodiment illustrated in  FIG. 4C  are accordingly freestanding relative to each other. 
       FIG. 4D  shows the method after the first semiconductor die  330  has been attached to the base substrate  310  in the die-attach region. The second semiconductor device package  302   b  can then be attached to the interconnects  322  to form the POP assembly  300  shown in  FIG. 3 . 
     From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. For example, the interconnects  322  shown in  FIG. 3  can be conductive posts formed by three-dimensional printing techniques. Accordingly, the invention is not limited except as by the appended claims.