Abstract:
A SDRAM mid a tinier lockout circuit. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and a circuit for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

Description:
BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to the field of synchronous circuits; more specifically, it relates to a lockout timer for synchronous circuits and especially for synchronous dynamic random access memory circuits. 
   2. Background of the Invention 
   Generally synchronous circuits, such a synchronous dynamic random access memory (SDRAM) circuits are designed to run at a pre-determined clock speed and with specified minimum fixed timings between critical input/output (I/O) events. It would be cost-effective to design and build synchronous circuits that can run at more than one clock speed as well as meet more than one set of I/O event timing specifications. 
   SUMMARY OF INVENTION 
   A first aspect of the present invention is a timer lockout circuit comprising: a delay circuit for receiving and delaying a first timing signal; first circuit for receiving the first timing signal from the first delay circuit and for latching the first timing signal; programmable timing circuit for receiving the first timing signal from the first circuit and for delaying the first timing signal by a programmable time interval; a one-shot generator for receiving the first timing signal from the programmable timing circuit and for generating a set signal; a second circuit for receiving the set signal from the one-shot generator and for latching the set signal; a third circuit for receiving a second timing signal and for latching the second timing signal; a combinational logic circuit for receiving the set signal from the second circuit and for receiving the second timing signal from the third circuit and for generating a third timing signal; and a second delay circuit for receiving and delaying the third timing signal and for simultaneously resetting the first circuit, the second circuit and the third circuit after delaying the third timing signal. 
   A second aspect of the present invention is a timer lockout circuit comprising: first means for receiving a first timing signal from a first delay circuit and for latching the first timing signal; second means for receiving the first timing signal from the first means and for delaying the first timing signal by a programmable time interval; third means for receiving the first timing signal from the second means and for generating a set signal; fourth means for receiving the set signal from the third means and for latching the set signal; fifth means for receiving a second timing signal and for latching the second timing signal; sixth means for receiving the set signal from the fourth means and for receiving the second timing signal from the fifth means and for generating a third timing signal; and seventh means for simultaneously resetting the first means, the fourth means and the fifth means. 
   A third aspect of the present invention is a SDRAM comprising: at least one bank of DRAM cells; the SDRAM operable to a first write recovery time; a first circuit for programming the SDRAM operable to a second write recovery time; and a second circuit for delaying the start of a precharge command for a time interval equal to the first write recovery time when the SDRAM is operable to the second write recovery time. 
   A fourth aspect of the present invention is a SDRAM comprising: at least one bank of DRAM cells; the SDRAM operable to a first write recovery time; a first circuit for programming the SDRAM operable to a second write recovery time; and a second circuit for delaying the start of a precharge command for a time interval equal to the first write recovery time when the SDRAM is operable to the second write recovery time. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
       FIG. 1  is a schematic circuit diagram of an SDRAM circuit according to the present invention; 
       FIG. 2  is a timing diagram of the SDRAM circuit of  FIG. 1 ; 
       FIG. 3  is a schematic circuit diagram of a timer lockout circuit according to the present invention; and 
       FIG. 4  is a timing diagram of the timer lockout circuit of  FIG. 3 . 
   

   DETAILED DESCRIPTION 
   While the present invention will be described using an SDRAM circuit as an example of a synchronous circuit to which the present invention is applicable and while a SDRAM according to the present invention is one aspect of the present invention, certain other aspects of the present invention are applicable to other synchronous circuits such as static RAMs, controllers and microprocessors. 
     FIG. 1  is a schematic circuit diagram of an SDRAM circuit according to the present invention. In  FIG. 1 , an SDRAM  100  includes DRAM banks  105  and a support circuit region  110 . DRAM banks  105  include a multiplicity of memory cells  115  arranged in rows and columns and accessible through word lines  120  connected to read, write and address circuits in support circuit region  110  and a multiplicity of bit lines true  125 A and a multiplicity of bit lines complement  125 B also connected to read, write and address circuits in the support region. Each bit line true  125 A/bit line complement  125 B bit line pair is connected to a sense amplifier  130 . The output of sense amplifiers  130  are coupled to data lines  135 . 
   A DRAM is written or read (after a bank is selected) by bringing a selected word line high to move the charge stored in all cells coupled to that wordline to the bit lines. The sense amplifiers amplify this small amount of charge. Bit lines must be precharged after a write prior to a read or the next write cycle. Writing, reading and precharging take finite amounts of time to accomplish. These times are reflected in the DRAM specifications in Table I which are typical examples of such specification. 
                                   TABLE I                       Specification   DDR 266   DDR 333                           t CK     7.5 ns   6.0 ns           t WR      15 ns    12 ns           t RP      15 ns    18 ns                        
Table I lists two different JEDEC Solid State Technology Association (Washington D.C.) double data rate (DDR) specifications. Table I is meant to be exemplary of the problem solved by the present invention. A DDR specification means data may be written/read on both the rise and fall of a clock pulse. The clock period is t CK . The clock frequency of the SDRAM specification is 1/t CK .
 
   The parameter t WR  is defined as the write recovery time, the minimum amount of time that must elapse after a write before a bit line precharge command &lt;PC&gt; may be issued. This timing starts at the first rising clock edge after the last data &lt;D&gt; is coupled to the DRAM I/O pins. Because a &lt;PC&gt; command brings down a word line, t WR  determines the minimum internal time t WRT , to write a memory cell. 
   The parameter t RP  is defined as the precharge to RAS (row address strobe) time and is the time after a &lt;PC&gt; command which must elapse before a bank activate &lt;BA&gt; command may be issued. Because a &lt;BA&gt; command brings up a word line, t RP  determines the minimum internal time t EQL , to equalize (precharge) a bitline. The relationship between the &lt;BA&gt; command, the &lt;W&gt; command, the &lt;PC&gt; command, &lt;D&gt;, t WR , t RP , t WRT  and t EQL  (as well as a read &lt;R&gt;) command is illustrated in  FIG. 2  and described in more detail infra. 
   While it is straightforward to design a SDRAM that can meet either the DDR  266  or DDR  333  specification separately (i.e. DDR  266 : t WR =15 ns and tRP=15 ns for t WR +t RP =30 ns or DDR  333 : t WR =12 ns and t RP =18 ns for t WR +t RP =30 ns), meeting both specifications outright requires that the SDRAM satisfy the minimum timing of each specification (i.e. t WR =12 ns and t RP =15 ns, reducing the total t WR +t RP =30 ns to 27 ns). The result is that the internal timing, t WRT  is also reduced by 3 ns. The purpose of the timer lockout circuit  140  in support circuit region  110  of SDRAM  100  is to allow both specifications to be met without a corresponding reduction in tWRT. 
   Timer lockout circuit  140  utilizes the normal column address strobe clock (CASCLK) and normal wordline off signal (WLOFF 1 ) to produce a new wordline off signal (WLOFF 2 ) which meets both of the timing specifications shown in Table I. WLOFF 1  is generated by a precharge &lt;PC&gt; command. Timer lockout circuit  140  maintains internal timings t WRT  and t EQL  while requiring only that the sum of the minimum t WR  specification and the minimum t RP  specification remain constant. This is accomplished by the timer lockout circuit delaying the start of &lt;PC&gt; commands by the difference between the two t WR  specifications. This has the effect of trading off “extra” tEQL time for t WRT  time. In the example of Table I, the WLOFF 2  signal will be issued exactly the same amount of time after the &lt;PC&gt; command (CASCLK) for both DDR  266  and DDR  333  specifications. The result is that the internal t WRT  and t EQL  timing will also be the same, even though their external counterparts, t WR  and t RP , are different. Timer lockout circuit  140  is illustrated in  FIG. 3  and described in more detail infra. 
     FIG. 2  is a timing diagram of SDRAM  100  of  FIG. 1 . In  FIG. 2 , two sets of timings are illustrated. The first set of timings is for the DDR  266  specification and the second set is for the DDR  333  specification. In both sets of timing diagrams after a &lt;W&gt; command, &lt;D&gt; starts to be written onto bitlines one clock cycle later. This is the write latency (W L ). Note that a single four-bit data burst is shown as an example only. The number of data bits in the burst (burst length), as well as the number of consecutive bursts may be greater or less than that shown. In the example of  FIG. 2 , all data is written in groups of two data bits so that one CASCLK pulse is generated every time two bits of data are to be written. Thus, the four bit data burst in  FIG. 2  results in two CASCLK pulses. The leading edge of a CASCLK pulse starts the process of writing data. Each time a CASCLK pulse occurs, timer lockout circuit  140  (see  FIG. 1  or  FIG. 3 ) will reset and start timing from zero. In the example of  FIG. 2 , there are two instances of CASCLK. The first instance (or assertion) starts the timer, and the second instance (or re-assertion) resets the timer to zero (i.e. timer lockout circuit  140  of  FIG. 1  did not time out). This is important because a write data burst can be interrupted, making it unclear exactly which &lt;D&gt; is the last, and therefore on which CLK edge the t WR  timing should begin. 
   In the DDR  226  specification, the CLK period is 7.5 ns, t WR  and t RP  are both 2 CLK periods (15 ns) in duration, and t TOT  is 4 CLK periods (30 ns ) in duration. In the DDR  333  specification the CLK period is 6.0 ns, t WR  is 2 CLK periods (12 ns ) in duration, t RP  is 3 CLK periods (18 ns ) in duration, and t TOT  is 5 CLK periods (30 ns ) in duration. Note however, that the internal timings, t WRT  and t EQL , are the same for both cases. This is accomplished by timer lockout circuit  140 . (see FIG .  3 ) delaying the end of t WRT  relative to &lt;PC&gt; by 3 ns 
     FIG. 3  is a schematic circuit diagram of timer lockout circuit  140  according to the present invention. In  FIG. 3 , timer lockout circuit includes a first inverting delay  145 , a first latch  150 , a first inverter  155 , a programmable timer  160 , a one shot pulse generator  165 , a second latch  170 , a second inverter  175 , a third latch  180 , an AND gate  185  and a second inverting delay  190 . 
   First inverting delay  145  and first inverter  155  receive CASCLK and first inverting delay  145  generates a setSTART signal that is coupled to the set input of first latch  150 . First inverter  155  generates a resetSTART signal that is coupled to the reset input of first latch  150 . First latch  150  generates a START signal that is coupled to one-shot pulse generator  165  through programmable time  160  which delays the START signal by an amount determined by the value of TMTWR signal. In the present example, TMTWR is a four-bit word used to blow (program) fuses or antifuses that set the delay through programmable timer  160 . The length of delay through programmable timer  160  is the difference in time between t WR  of the DDR  266  specification and the DDR  333  t WR  specification, in the present example 3 ns (adjusted for signal delay through first inverting delay  145 , first latch  150 , and one shot pulse generator  165 ). Programmable timer  160  will reset to zero and restart timing every time a start signal is received even if timing has previously started and was not completed. One shot pulse generator  165  generates a setTWR signal that is coupled to the set input of second latch  170 . WLOFF 1  is coupled to the input of second inverter  175 . Second inverter  175  generates a setPRE signal coupled to the set input of third latch  180 . The output of second latch  170  is a TWR signal and the output of third latch  180  is a PRE signal, which are ANDed together by AND gate  185  to produce WLOFF 2 . WLOFF 2  is coupled to an input of inverting delay  190 . The output of inverting delay  190  (a RESET signal) is coupled to the reset inputs of first, second and third latches  150 ,  170  and  180 . 
   In operation, when CASCLK goes high, resetSTART goes low, resetting first latch  150  and START goes low. After a programmable delay by programmable timer  160 , one shot generator  165  pulses setTWR low, second latch  170  sets so TWR goes high. If both PRE and TWR are high, then WLOFF 2  is high. 
   From a SRDAM point of view, since WLOFF 1  is derived from the &lt;PC&gt; command when the &lt;PC&gt; command goes high, third latch  180  sets and the PRE signal is presented to AND gate  185 . After a data write event (CASCLK pulses) programmable timer  160  times out, setting second latch  170  and TWR is presented to AND gate  185 . Thus, when both conditions, WLOFF 1  is high and programmable timer  160  times out, WLOFF 2  goes high. 
   IF WLOFF 1  goes high after programmable timer  160  times-out (an therefore a sufficient amount of internal write time t WRT  has elapsed), then WLOFF 2  looks substantially like WLOFF 1 . However, if the timer has not timed-out (and therefore insufficient write time t WRT  has elapsed), then WLOFF 2  is a delayed version of WLOFF 1  that will allow additional t WRT  time. First inverting delay  145  ensures that enough time is allowed to reset programmable timer  160  before the programmable timer must be re-started. Timer lockout circuit  140  essentially times the rise of CASCLK to the end of tWRT and presents that timing as WLOFF 2 . 
     FIG. 4  is a timing diagram of timer lockout circuit  140  of  FIG. 3  summarizing the operation of the lockout circuit. 
   The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.