Abstract:
Memory writing system and method determining an optimum data amount per one-time data transmission to one memory writer to enable optimization of communication efficiency and write speed, include: setting the amount of data to be transmitted per one-time transmission from a writer controller to different values for respective memory writers; transmitting data of each of the data amounts from the writer controller to a corresponding one of the memory writers; measuring, for each of the data amounts, a processing time required for the writer controller to transmit data to the corresponding memory writer and a data write time of the corresponding memory writer; obtaining, for each of the data amounts, a correlation between the processing time and the data write time based on respective measured values; setting an optimum data amount based on the correlation to satisfy a desired data write time condition; and, after the optimum data amount is set, sequentially transmitting data of the optimum data amount from the writer controller to the memory writers.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a system and method for writing data into nonvolatile memories, such as flash memories. 
         [0003]    2. Description of the Related Art 
         [0004]    For mass production of large scale integrated circuits (LSIs) equipped with flash memories, a writing system is constructed on a part of a production line to write data, such as programs, into the flash memories. The writing system may be automated, but to do so is costly. For this reason, in the case where the number of LSIs to be produced can be manually coped with, a conventional writing system may be constructed as shown in  FIG. 1 . 
         [0005]    In the writing system of  FIG. 1 , LSIs  1   1  to  1   n , each equipped with a flash memory, are one-to-one connected to flash writers  2   1  to  2   n , respectively. Each of the flash writers  2   1  to  2   n  is connected to one writer controller  4  via a distributor  3 . The writer controller  4  holds data to be written into each of the LSIs  1   1  to  1   n . As the writer controller  4  is operated by a user of a production line, it performs a control operation to supply the data to the respective flash writers  2   1  to  2   n  through the distributor  3 , thereby allowing the data to be written into the respective LSIs  1   1  to  1   n . At the time that the writer controller  4  recognizes completion of the writing into all the LSIs  1   1  to  1   n , the user disconnects the respective LSIs  1   1  to  1   n  from the corresponding flash writers  2   1  to  2   n . Then, the user connects LSIs  1   1  to  1   n  into which data is written to the corresponding flash writers  2   1  to  2   n  and repeats the writing of the data in the same sequence. 
         [0006]    In this conventional writing system, the number n of connectable LSIs  1   1  to  1   n  is generally on the order of several to several tens due to restrictions by communication standards, etc. For example, for the writing into a total of twenty thousand LSIs using a system in which the LSIs are connectable 20 by 20, it is necessary to repeat the above sequence 1000 times. For this reason, it is required to shorten a write time for a plurality of memories, as shown in Japanese Patent Kokai No. 2004-102438 (patent literature 1) and Japanese Patent Kokai No. H11-250684 (patent literature 2). 
         [0007]    In order to make the production line efficient under the condition of maintaining the configuration of the writing system as it is, the shortening of a write time per one sequence is a problem to be solved. On the other hand, there is a limit in the size of write data that each flash writer can receive through one-time communication. In this regard, the writer controller may always set the size of write data to be transmitted to the limit. In this case, the write time is minimized, but channel occupancy of the writer controller is increased because the writer controller and the distributor are generally interconnected via one communication channel. This is not preferable in terms of communication efficiency. Therefore, there is a need to promote the optimization of the communication efficiency and write time. 
       SUMMARY OF THE INVENTION 
       [0008]    However, in the conventional writing system, no consideration is given to writing in an optimum state. For the convenience of description of this point, it is here assumed that five LSIs  1   1  to  1   5  are connected to the flash writers  2   1  to  2   5  in the conventional writing system of  FIG. 1 .  FIG. 2  shows communications between the writer controller  4  and the flash writers  2   1  to  2   5  in the aforementioned connection state. The writer controller  4  includes a writer controller commander  41  and a write processor  42  therein. Also, the distributor  3  shown in  FIG. 1  is omitted. For data writing, first, the writer controller  4  divides write data by a predetermined size and sequentially transmits every write data of the predetermined size to each flash writer  2   1  to  2   5 . If the flash writer  2   1  receives write data of the predetermined size, then it writes the received data into the LSI  1   1 . Similarly, if the flash writer  2   2  receives write data of the predetermined size, then it writes the received data into the LSI  1   2 . The flash writers  2   3  to  2   5  also write data into the LSIs  1   3  to  1   5  in the same manner. The writer controller  4  inquires writing results from the flash writers  2   1  to  2   5 . After confirming writing results fed back from all the flash writers  2   1  to  2   5 , the writer controller  4  performs second-time writing of data of the predetermined size. The above operation is repeated until write data is exhausted. 
         [0009]    In this writing system, a write data transmission process and a writing result reception process are executed for writing of data of the predetermined size, as shown in  FIG. 3 . In  FIG. 3 , Tt is a time until the writer controller  4  prepares and transmits write data of the predetermined size for one LSI, Tw 1  is a time until each flash writer  2   1  to  2   5  receives data and completes writing of the received data, and Tw 2  is a period for which the writer controller  4  receives a writing result from every flash writer. A write time Tw is defined as Tw=Tw 1 +Tw 2 . 
         [0010]    The writer controller  4  proceeds to the writing result reception process immediately after performing the write data transmission process. This is because the writer controller  4  cannot expect when writing results will be fed back from the flash writers  2   1  to  2   5 . As a result, since the writer controller  4  occupies the communication channel for the writing result reception process until receiving writing results, a smaller write data size per one sequence is advantageous to communication efficiency. However, in the case where the write data size is too small, data writing by flash writers having already received data may be ended before completion of the write data transmission process, resulting in generation of standby times of those flash writers, thereby making it impossible to promote the shortening of the write time. That is, although the write data size needs to be set to an optimum value, it is difficult to determine the optimum value in advance. This is because the optimum value is dependent on a variety of parameters, such as a processing speed of the writer controller  4 , a communication speed of the communication channel, a processing speed of each flash writer  2   1  to  2   5 , and a write speed of the flash memory equipped in each LSI  1   1  to  1   5 . Consequently, in the conventional writing system, there is a problem that no consideration is given to writing in an optimum state. 
         [0011]    Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a memory writing system and method which can determine an optimum data amount per one-time data transmission to one memory writer to enable optimization of communication efficiency and write speed. 
         [0012]    In accordance with an aspect of the present invention, the above and other objects can be accomplished by the provision of a memory writing system including a writer controller and a plurality of memory writers, the writer controller sequentially transmitting data to the memory writers over a communication channel and repeating this transmission operation, each of the memory writers, whenever receiving data transmitted from the writer controller, writing the received data into a nonvolatile memory, the system further including a first setting component which sets the amount of data to be transmitted per one-time transmission from the writer controller to different values for the respective memory writers, a first transmission controller which transmits data of each of the data amounts from the writer controller to a corresponding one of the memory writers, a measurement component which measures, for each of the data amounts, a processing time required for the writer controller to transmit data to the corresponding memory writer and a data write time of the corresponding memory writer, a correlation detection component which obtains, for each of the data amounts, a correlation between the processing time and the data write time based on respective measured values of the processing time and data write time measured by the measurement component, a second setting component which sets an optimum data amount based on the correlation to satisfy a desired data write time condition, and a second transmission controller which sequentially transmits, after the optimum data amount is set, data of the optimum data amount from the writer controller to the memory writers. 
         [0013]    In accordance with another aspect of the present invention, there is provided a memory writing method of a memory writing system, the memory writing system including a writer controller and a plurality of memory writers, the writer controller sequentially transmitting data to the memory writers over a communication channel and repeating this transmission operation, each of the memory writers, whenever receiving data transmitted from the writer controller, writing the received data into a nonvolatile memory, the method including a first setting step of setting the amount of data to be transmitted per one-time transmission from the writer controller to different values for the respective memory writers, a first transmission control step of transmitting data of each of the data amounts from the writer controller to a corresponding one of the memory writers, a measurement step of measuring, for each of the data amounts, a processing time required for the writer controller to transmit data to the corresponding memory writer and a data write time of the corresponding memory writer, a correlation detection step of obtaining, for each of the data amounts, a correlation between the processing time and the data write time based on respective measured values of the processing time and data write time measured at the measurement step, a second setting step of setting an optimum data amount based on the correlation to satisfy a desired data write time condition, and a second transmission control step of, after the optimum data amount is set, sequentially transmitting data of the optimum data amount from the writer controller to the memory writers. 
         [0014]    According to the memory writing system and the memory writing method of the present invention, the writing data transmitting process and the writing result receiving process are performed in accordance with the optimum data amount obtained by the processing time required for the writer controller to transmit data to the corresponding memory writer and the data write time of the corresponding memory writer. Thus the data writing into the nonvolatile memory is realized while maintaining an optimum communication efficiency and an optimum writing speed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram showing a conventional writing system; 
           [0016]      FIG. 2  is a block diagram showing a system including an internal configuration of a writer controller in  FIG. 1 ; 
           [0017]      FIG. 3  is a timing diagram of a write data transmission process and a writing result reception process; 
           [0018]      FIG. 4  is a block diagram showing an embodiment of the present invention; 
           [0019]      FIG. 5  is a flow chart illustrating an optimum data size calculation operation of a writer controller in  FIG. 4 ; 
           [0020]      FIG. 6  is a flow chart illustrating a data write operation of the writer controller in  FIG. 4 ; 
           [0021]      FIG. 7  is a block diagram showing another embodiment of the present invention; and 
           [0022]      FIG. 8  is a flow chart illustrating a data write operation of a writer controller in  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    Now, exemplary embodiments of the present invention will be described in detail with reference to the annexed drawings. 
         [0024]      FIG. 4  shows a memory writing system of the present invention. This memory writing system corresponds to the same five LSIs  1   1  to  1   5 , each having a flash memory, and includes flash writers  2   1  to  2   5 , a distributor  3 , and a writer controller  4 , similarly to the system shown in  FIG. 1 . 
         [0025]    The writer controller  4  includes a writer controller commander  41 , a write processor  42 , and a processing time measurer  43 . The writer controller commander  41  controls the write processor  42  and the processing time measurer  43 . The writer controller commander  41  generates commands including a write command to the write processor  42  such that the write processor  42  transmits data of the maximum size MAX_SIZE to each flash writer, and receives a writing result from each flash writer. The write processor  42  sequentially supplies write data to the flash writers  2   1  to  2   5  in response to the write command. 
         [0026]    Also, the writer controller commander  41  generates a measurement command consisting of a start command and a stop command to the time measurer  43  such that the time measurer  43  measures a processing time. The time measurer  43  includes a timer (not shown), and starts time measurement of the timer in response to the start command and stops the measurement of the timer in response to the stop command. Then, the timer measurer  43  provides a time measured by the timer as the processing time to the writer controller commander  41 . 
         [0027]    In the memory writing system of the present invention with this configuration, as shown in  FIG. 5 , first, the writer controller commander  41  sets a variable n to 1 (step S 1 ) and starts the time measurement of the timer of the processing time measurer  43  (step S 2 ). This is for starting measurement of the processing time of the writer controller  4  itself. Then, the writer controller commander  41  commands the write processor  42  to prepare data to be transmitted to a flash writer  2   n  and transmit the prepared data to the flash writer  2   n  (step S 3 ). This data is transmitted from the write processor  42  to the flash writer  2   n  through the distributor  3 . Here, the size size_n of the data to be transmitted to the flash writer  2   n  (n=1 to 5) is (MAX_SIZE/5)×n. That is, the size size_ 1  of the data to the flash writer  2   1  is MAX_SIZE/5, the size size_ 2  of the data to the flash writer  2   2  is 2(MAX_SIZE/5), the size size_ 3  of the data to the flash writer  2   3  is 3(MAX_SIZE/5), the size size_ 4  of the data to the flash writer  2   4  is 4(MAX_SIZE/5), and the size size_ 5  of the data to the flash writer  2   5  is MAX_SIZE. 
         [0028]    At the time that the writer controller commander  41  detects completion of the data transmission from the write processor  42  to the flash writer  2   n  (YES at step S 4 ), it stops the time measurement of the timer of the processing time measurer  43  (step S 5 ). The processing time of the writer controller, measured at this time, is provided as Tt to the writer controller commander  41 . The writer controller commander  41  stores the processing time Tt for the flash writer  2   n  (step S 6 ). 
         [0029]    Then, the writer controller commander  41  again starts the time measurement of the timer of the processing time measurer  43  (step S 7 ). This is for starting measurement of a write time of the flash writer  2   n . When a writing result indicative of writing completion from the flash writer  2   n  is fed back to the write processor  42  (YES at step S 8 ), the writer controller commander  41  stops the time measurement of the timer of the processing time measurer  43  (step S 9 ). The write time, measured at this time, is provided as Tw to the writer controller commander  41 . The writer controller commander  41  stores the write time Tw for the flash writer  2   n  (step S 10 ). 
         [0030]    The above steps S 2  to S 10  are carried out similarly with respect to each of the flash writers  2   2  to  2   5 , in addition to the flash writer  2   1 . That is, the writer controller commander  41  determines whether n is greater than or equal to 5 (step S 11 ), and, if n&lt;5, adds 1 to n (step S 12 ) and then proceeds to step S 2 . On the other hand, if n·5, the writer controller commander  41  proceeds to the next step S 13 . 
         [0031]    By the above operation, five measurements for the respective flash writers  2   1  to  2   5  can be provided as the write time Tw. Therefore, the writer controller commander  41  obtains a correlation between the write time Tw and the data size size_n through a method of least squares (step S 13 ). The obtained correlation is expressed as a function, such as Tw(size_n). 
         [0032]    It can be seen from this result that the equality of the processing time of the writer controller  4  and the write time indicates an optimum state of communication efficiency and write speed. As a result, a condition for the optimum state (desired data write time condition) is 4 Tt=Tw(size_n). In a write process, for example, if the writer controller  4  ends transmission of data to the flash writer  2   1 , the flash writer  2   1  begins to write the data into the LSI  1   1 , whereas the writer controller  4  sequentially transmits data to the other four writers  2   2  to  2   5 . Therefore, it is preferable that, at the time that the data transmission to the writers  2   2  to  2   5  is completed, the flash writer  2   1  should end the writing into the LSI  1   1  and be ready to receive new data. Consequently, the equality of the write time Tw(size_n) of one flash writer and the data transmission processing time 4 Tt of four flash writers is a condition for the optimum state. A data size size_n to satisfy this condition is obtained as an optimum data size size_opt=size_n (step S 14 ). 
         [0033]    If the optimum data size size_opt is obtained in this manner, then the writer controller commander  41  executes transmission of data of the optimum data size size_opt per one-time transmission to each flash writer  2   1  to  2   5  as follows. 
         [0034]    As shown in  FIG. 6 , first, the writer controller commander  41  sets the variable n to 1 (step S 21 ). Then, if there is remaining data to be transmitted, the writer controller commander  41  commands the write processor  42  to prepare data of the data size size_opt to be transmitted to the flash writer  2   n  and transmit the prepared data to the flash writer  2   n  (step S 22 ). At the time that the writer controller commander  41  detects completion of the data transmission from the write processor  42  to the flash writer  2   n  (YES at step S 23 ), it determines whether n is greater than or equal to 5 (step S 24 ), and, if n&lt;5, adds 1 to n (step S 25 ) and then proceeds to step S 22 . On the other hand, if n·5, the writer controller commander  41  proceeds to the next step S 26  because a write data transmission process has been carried out with respect to each flash writer  2   1  to  2   5 . 
         [0035]    The writer controller commander  41  sets the variable n to 1 (step S 26 ) and determines whether a writing result indicative of writing completion has been received from the flash writer  2   n  (step S 27 ). If the write processor  42  has received the writing result from the flash writer  2   n , the writer controller commander  41  determines whether n is greater than or equal to 5 (step S 28 ), and, if n&lt;5, adds 1 to n (step S 29 ) and then proceeds to step S 27 . On the other hand, if n·5, because a writing result reception process has been carried out with respect to each flash writer  2   1  to  2   5 , the writer controller commander  41  determines whether there is data to be transmitted to at least one of the flash writers  2   1  to  2   5  (step S 30 ). If there is data to be transmitted to at least one of the flash writers  2   1  to  2   5 , the writer controller commander  41  returns to step S 21  to repeat the above steps S 21  to S 30  until the data transmission to all the flash writers  2   1  to  2   5  is completed. Also, although not shown in  FIG. 6 , with respect to a flash memory to which data to be transmitted is exhausted, the writer controller commander  41  does not perform steps S 22  and S 23  and performs step S 24  directly by bypassing those steps. Similarly, the writer controller commander  41  does not perform step S 27  and performs step S 28  directly by bypassing step S 27 . 
         [0036]    In the case where there is no data to be transmitted to at least one of the flash writers  2   1  to  2   5 , the data transmission has been completed with respect to all the flash writers  2   1  to  2   5  and the writing results have been received from all the flash writers  2   1  to  2   5 . 
         [0037]    As stated above, in the present embodiment, the write data transmission process and the writing result reception process are carried out based on a write data size obtained from measured values of the processing time Tt of the writer controller  4  and the write time Tw of each flash writer  2   1  to  2   5 . Therefore, it is possible to realize data writing into LSIs under the condition that communication efficiency and write speed are optimum. 
         [0038]    Also, the memory writing system of this embodiment can be inexpensively realized by modifying only a writer controller of a conventional system. In addition, the optimum write data size size_opt can be obtained at an actual write time. As a result, the optimum write data size size_opt can be obtained based on processing performance of each of the writer controller and flash writers, a communication speed of a communication channel and the number of flash writers connected, at the actual write time. Therefore, it is possible to realize data writing into LSIs in a more optimum state. 
         [0039]    Also, if the write processor  42  has received the writing result from the flash writer  2   n  at step S 27  of the above embodiment, the writer controller commander  41  may directly transmit data of the data size size_opt to the flash writer  2   n  when there is remaining data to be transmitted to the flash writer  2   n . In this case, after the data transmission, the writer controller commander  41  adds 1 to n, and proceeds to step S 27  if n&lt;5. 
         [0040]      FIG. 7  shows a memory writing system according to another embodiment of the present invention. In this memory writing system, a write size manager  42   a  is provided in a write processor  42  of a writer controller  4 . The write size manager  42   a  stores optimum data sizes size_opt( 1 ) to size_opt( 5 ) for respective flash writers  2   1  to  2   5 . 
         [0041]    Other components of the memory writing system of  FIG. 7  are the same as those of the system shown in  FIG. 4 . 
         [0042]    In this memory writing system of  FIG. 7 , first, steps S 1  to S 14  of  FIG. 5  are performed to set an optimum data size size_opt. 
         [0043]    If the optimum data size size_opt is set at step S 14 , as shown in  FIG. 8 , the writer controller commander  41  makes each of size_opt( 1 ) to size_opt( 5 ) equal to the set optimum data size size_opt (step S 31 ). 
         [0044]    Thereafter, the writer controller commander  41  sets a variable n to 1 (step S 32 ). Then, if there is remaining data to be transmitted, the writer controller commander  41  commands the write processor  42  to prepare data of the data size size_opt(n) to be transmitted to the flash writer  2   n  and transmit the data of the data size size_opt(n) to the flash writer  2   n  (step S 33 ). At the time that the writer controller commander  41  detects completion of the data transmission from the write processor  42  to the flash writer  2   n  (YES at step S 34 ), it determines whether n is greater than or equal to 5 (step S 35 ), and, if n&lt;5, adds 1 to n (step S 36 ) and then proceeds to step S 33 . On the other hand, if n·5, the writer controller commander  41  proceeds to the next step S 37  because the write data transmission process has been carried out with respect to each flash writer  2   1  to  2   5 . 
         [0045]    The writer controller commander  41  sets the variable n to 1 (step S 37 ) and determines whether a writing result indicative of writing completion has been received from the flash writer  2   n  (step S 38 ). This determination may be made at a certain time after the write transmission process is performed with respect to the flash writer  2   n . The certain time may be determined depending on the data size size_opt(n) and the correlation Tw(size_n) obtained by the method of least squares may be used as Tw(size_opt(n)). If the write processor  42  has received the writing result from the flash writer  2   n , the writer controller commander  41  increases the data size size_opt(n) by a predetermined value offset (step S 39 ) and then proceeds to step S 42 . On the other hand, if the write processor  42  has not received the writing result from the flash writer  2   n , the writer controller commander  41  decreases the data size size_opt(n) by the predetermined value offset (step S 40 ). The data sizes size_opt(n), which are results of the execution of steps S 39  and S 40 , are stored in the write size manager  42   a . After the execution of step S 40 , the writer controller commander  41  determines whether the writing result indicative of the writing completion has been received from the flash writer  2   n  (step S 41 ). If the writing result indicative of the writing completion has been received from the flash writer  2   n  at step S 41 , the writer controller commander  41  proceeds to step S 42 . 
         [0046]    The writer controller commander  41  determines at step S 42  whether n is greater than or equal to 5, and, if n&lt;5, adds 1 to n (step S 43 ) and then proceeds to step S 38 . On the other hand, if n·5, because the writing result reception process has been carried out with respect to each flash writer  2   1  to  2   5 , the writer controller commander  41  determines whether there is data to be transmitted to at least one of the flash writers  2   1  to  2   5  (step S 44 ). If there is data to be transmitted to at least one of the flash writers  2   1  to  2   5 , the writer controller commander  41  returns to step S 32  to repeat the above steps S 32  to S 44  until the data transmission to all the flash writers  2   1  to  2   5  is completed. 
         [0047]    Assuming that the optimum data size size_opt set at step S 14  is, for example, 520 Byte and the predetermined value offset is, for example, 80 Byte, the data size size_opt(n) is size_opt(n)=520+80=600 Byte when the writing result indicative of the writing completion has been received from the flash writer  2   n  at step S 38 . As a result, data of 600 Byte is transmitted in the next data transmission to the flash writer  2   n . On the other hand, in the case where the writing result indicative of the writing completion has not been received from the flash writer  2   n  at step S 38 , the data size size_opt(n) is size_opt(n)=520−80=440 Byte. As a result, data of 440 Byte is transmitted in the next data transmission to the flash writer  2   n . 
         [0048]    In this manner, by making the transmission size of write data smaller with respect to an LSI with a longer write time and larger with respect to an LSI with a shorter write time, it is possible to absorb a difference between write times resulting from a difference between inherent characteristics of LSIs. As a result, the write data transmission process and the writing result reception process are carried out based on a write data size which is obtained from measured values of the processing time Tt of the writer controller  4  and the write time Tw of each flash writer  2   1  to  2   5  and then optimized with respect to each flash writer  2   1  to  2   5 . Therefore, it is possible to realize data writing into LSIs under the condition that communication efficiency and write speed are optimum for each LSI. 
         [0049]    This memory writing system of  FIG. 7  can be inexpensively realized by modifying only a writer controller of a conventional system. In addition, it is also possible to cope with a variation in transmission state of the communication channel during data writing. 
         [0050]    Also, although the flash memories equipped in the LSIs  1   1  to  1   n  have been described as nonvolatile memories in the above-stated respective embodiments, the present invention is not limited thereto. For example, the nonvolatile memories may be ROMs, PROMs or other types of nonvolatile memories. 
         [0051]    As is apparent from the above description, according to a memory writing system and memory writing method of the present invention, a write data transmission process and a writing result reception process are carried out based on an optimum data amount obtained from measured values of a processing time of a writer controller required for data transmission to every memory writer and a data write time of each memory writer. Therefore, it is possible to realize data writing into nonvolatile memories under the condition that communication efficiency and write speed are optimum. 
         [0052]    This application is based on Japanese Patent Application 2010-034611 which is herein incorporated by reference.