Abstract:
A system comprising, a sense portion comprising a NAND logic gate that receives a first input logic signal associated with a lower voltage, wherein the sense portion outputs a sense logic signal, an intermediary portion comprising, a node operative to output an intermediary signal, a first pull down device, wherein the first pull down device receives a second input logic signal associated with the lower voltage complimentary with respect to the first input logic signal, a first pull up device that receives the sense logic signal, wherein the first pull up device is connected to a power supply at the higher operating voltage, and a second pull up device that receives the output logic signal associated with a higher voltage, an inverter portion, outputting the first output logic signal associated with the higher voltage responsive to a state of the intermediary signal.

Description:
BACKGROUND 
   This invention relates to a digital integrated circuits, and more specifically to a system for improved delay voltage level shifting. 
   CMOS-based (complementary metal-oxide semiconductor) integrated circuits operate at a voltage input supplied by voltage rails. Power consumption in the core logic of the integrated circuit may be minimized if low rail voltages are used. The output digital signals of the core logic typically switch between the rail voltage and ground. Sometimes the low rail voltages of the integrated circuit are insufficient to be used as output voltages for a CMOS signal that is sent from the core logic. The output voltage is increased in a level shifting input/output (IO) circuit to facilitate sending the CMOS signal. Previous level shifting IO circuits experience delays and may induce an undesirable DC current path through the circuit. 
   SUMMARY 
   The shortcomings of the prior art are overcome and additional advantages are achieved through an exemplary system comprising, a sense portion comprising a NAND logic gate that receives a first input logic signal associated with a lower voltage and an output logic signal associated with a higher voltage, wherein the sense portion outputs a sense logic signal responsive to the state of the NAND logic gate, an intermediary portion comprising, a node operative to output an intermediary signal, a first pull down device connected to the node, wherein the first pull down device receives a second input logic signal associated with the lower voltage complimentary with respect to the first input logic signal, a first pull up device that receives the sense logic signal, wherein the first pull up device is connected to a power supply at the higher operating voltage and the node, and a second pull up device that receives the output logic signal associated with a higher voltage, wherein the second pull up device is connected in parallel to the first pull up device to the power supply and the first node, an inverter portion having an input connected to the node, outputting the first output logic signal associated with the higher voltage responsive to a state of the intermediary signal. 

   
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       FIG. 1  illustrates a high-level block diagram of an exemplary embodiment of an integrated circuit. 
       FIG. 2  is a schematic diagram of an exemplary embodiment of a level shifting IO circuit. 
       FIG. 3  illustrates high/low states of portions of the level shifting IO circuit. 
       FIG. 4  is a table illustrating states of components of the level shifting IO circuit. 
   

   DETAILED DESCRIPTION 
   Systems involving IO circuits are provided. Several exemplary systems are described. 
     FIG. 1  illustrates a high level block diagram of an exemplary level shifting input/output (IO) circuit and a microprocessor. The microprocessor core logic  102  receives a low line voltage of, for example, 1.0 volts (V). The microprocessor core logic  102  outputs the digital signals A and ABAR that may represent a digital high signal at, for example, 3.3 V and a digital low signal of approximately 0 V. The ABAR signal is the logical compliment (NOT) of the A signal. The low line voltage used by the microprocessor core logic  102  allows the microprocessor core logic  102  to conserve power, however the low voltage does not meet the needed output voltage for CMOS output. 
   The IO circuit  104  receives the output signals from the microprocessor core logic  102 , and increases the voltage of the output signals to a high voltage. In this non-limiting example, the low voltage is 1.0 V and the high voltage is 3.3 V. By processing the output signals in the IO circuit  104 , the microprocessor core logic  102  may operate at the low voltage, conserving power, and the output signals may meet the needed high voltage output for CMOS output. The IO circuit  104  also no direct current paths exist between VDD or VDD 2  and VSS during steady states of the IO circuit  104 . If a direct current path exists, there is an undesirable loss of power. 
   The operation of the IO circuit  104  may best be described while referencing the input (A and ABAR), internal (I 1 ), and output signal (A 2 ) states as the input signal is at steady state and as the input signal transitions from a high to a low signal. 
     FIG. 2  illustrates a detailed circuit diagram of the IO circuit  104 . The IO circuit  104  includes a sense circuit portion  202 , an intermediary circuit portion  206 , an inverter circuit portion  204 , and a logic portion  208 . 
   In operation, the input signals A and ABAR are logical compliments (NOT) in that when A is low, ABAR is high, and when A is high, ABAR is low. The input signals are input at the low voltage (VDD). The output signal A 2  shares the same state (at steady state) as A, but is output at the high voltage (VDD 2 ). Transistors are represented by the nomenclature “T#” and may be NFET or PFET type transistors as indicated in  FIG. 2 . Hereinafter, the transistors will be referenced as illustrated in  FIG. 2 . 
   The detailed operation of the IO circuit  104  may best be described while referencing the input signals (A and ABAR), the internal signals (P 1  and I 1 ) and the output signal (A 2 ) states as the input signals are at steady state and as the input signals transition from a high to a low signal. The states of the signals are illustrated in  FIG. 3 . 
   Referring to  FIG. 2 , sense circuit portion  202  (NAND logic gate) will detect the state of the input signal (ABAR) and the output signal (A 2 ), and change the state of the signal P 1 . As P 1  changes, the intermediate signal I 1  will actively drive from low to high or from high to low to depending on the state of the input signal. The inverter circuit portion  204  will invert the state of the output signal to match the input signal and output A 2  at the high voltage. 
   Referring to  FIG. 3 , at time  0 , the input signals A and ABAR are at a first steady state represented by the graphs in the “I” portion. A is a low signal, VSS, of approximately 0V and ABAR is a high signal VDD (the line voltage of the microprocessor core logic  102  of  FIG. 1 ). 
   In steady state “I”, referring to the sense circuit portion  202 , ABAR is a high signal keeping T 2  enabled (on). A 2  is a feedback signal from the output signal A 2  and is low keeping T 3  disabled (off) (the status of A 2  will be further described below). A resistor R 1  pulls the voltage of P 1  to VDD 2  such that P 1  is high. T 3  disabled prevents any DC current path in circuit portion  202  during steady state “I”. 
     FIG. 3  shows a first transitive state “II” where A has become a high signal and ABAR has become a low signal. A 2  remains low until the completion of the transitive state “II”. Referring to the sense circuit portion  202 , the low ABAR signal disables T 2 . In the transitive state II, the signal A 2  remains low keeping T 3  disabled. P 1  remains high. 
   The intermediary circuit portion  206  controls the intermediary signal (I 1 ) and includes a node  205 . The operation of the intermediary circuit portion  206  in the first steady state “I” and the first transitive state “II” will be described below. 
   In the first steady state “I,” the P 1  signal is high. Referring to the intermediary circuit portion  206 , P 1  is high keeping T 5  disabled. T 1  receives the low A signal keeping T 1  disabled. The low signal A 2  keeps T 6  enabled driving the intermediary signal I 1  high. T 1  disabled, T 5  disabled and T 6  enabled prevents any DC current paths in circuit portion  206  during steady state “I”. 
   In the first transitive state “II,” the when A and ABAR switch states, A becomes high. The high A signal enables T 1 . Since T 1  is a stronger transistor than T 6 , T 1  pulls the intermediary signal (I 1 ) low. 
   Referring to the inverter circuit portion  204 , in the first steady state “I”, I 1  is high keeping T 7  disabled and T 4  enabled. A 2  is pulled low by VSS, which feeds back to T 3  and T 6  as described above. T 7  disabled in steady state “I” prevents any DC current paths in circuit portion  204 . In the first transitive state “II,” I 1  becomes low. When I 1  becomes low, T 7  is enabled and T 4  is disabled. A 2  becomes high, driven by VDD 2 . 
   When A 2  switches states, the sense circuit portion  202  receives the high A 2  signal. The high A 2  signal enables T 3 . The low ABAR signal disables T 2 . P 1  remains high. A 2  being high disables T 6 . At this point node  205  is only driven low by T 1 , and T 5  and T 6  are disabled. This concludes the first transitive state “II”. The sense circuit portion  202  in  FIG. 2  allows T 6  to be relatively small because T 6  does not have the role of actively driving I 1  high. This in turn allows T 1  to be smaller because driving I 1  low is easier due to the decreased strength of T 6 . 
   The second steady state “III” as illustrated in  FIG. 3 , is similar to the first steady state “I,” however the input signals (A and ABAR), the intermediary signal (I 1 ), and the output signal (A 2 ) have switched states. The second steady state “III” is described below. 
   In the second steady state “III”, circuit portion  202 , T 2  is disabled due to a low ABAR. A 2  is high, as described above from the conclusion of transitive state “II”, and this enables T 3 . P 1  is pulled high through R 1  to VDD 2 , as T 2  is disabled shutting off a path to VSS. High P 1  and high A 2  disables T 5  and T 6  of circuit portion  206 . Signal A being high enables T 1 , causing node  205  (I 1 ) to be low. Low I 1  causes T 7  to enable and T 4  to disable driving A 2  high. In all three circuit portions, as well as the overall circuit, no DC current paths exist in this steady state “III”. 
   If the input signals A and ABAR invert again from low to high, a second transitive state “IV” begins as illustrated in  FIG. 3 . Referring to the sense circuit portion  202 , ABAR becomes high enabling T 2 . During transient state “IV” A 2  maintains the same voltage from steady state “III”, high. A 2  being high enables T 3 . VSS pulls P 1  low through T 2  and T 3 , which are enabled by ABAR and A 2 . Referring to the intermediary circuit portion  206 , when P 1  is pulled low, P 1  enables T 5 . The low A signal disables T 1 . The enabled T 5  allows VDD 2  to drive the intermediary signal (I 1 ) high. 
   Referring to the inverter circuit portion  204 , In the second transitive state “IV,” I 1  becomes high. When I 1  becomes high, T 7  is disabled and T 4  is enabled. VSS pulls A 2  low. When the state of A 2  switches to low, A 2  disables T 3 , and R 1  drives P 1  high to VDD 2 . A 2  transitioning low enables T 6 , actively holding node  205  (I 1 ) high. When T 6  enables and T 5  disables, the second transitive state “IV” is complete, and the circuit has returned to the first steady state “I”. In the first steady state “I”, and the second steady state “II”, no direct current paths exist between VDD or VDD 2  and VSS. 
     FIG. 4  illustrates a reference table showing the signal states and the states of the transistors as described in above. 
   The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
   The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.