Abstract:
Semiconductor memory devices having hierarchical word line structures are provided. A block of sub-word line driver circuits (SWDB) are disposed between a first block of memory and a second block of memory. A SWDB includes a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each having four SWD circuits extending in a first direction between the first and second blocks of memory. Two adjacent SWD columns include a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application claims priority to Korean Patent Application No. 2006-0110329, filed on Nov. 9, 2006, which is incorporated herein by reference. 
   TECHNICAL FIELD OF THE INVENTION 
   The present invention relates generally to semiconductor memory devices having hierarchical word line structures and, in particular, semiconductor memory devices having sub-word line driver circuitry with layout patterns that enable increased integration density and high performance operation. 
   BACKGROUND 
   Technological innovations in semiconductor fabrication technologies are driving market demands for semiconductor memory devices providing higher storage capacity, higher speed, higher integration density, and lower power consumption. The downscaling of semiconductor memory devices to submicron design rules and beyond, however, coupled with increased storage capacity poses technological challenges with respect to maintaining performance and reliability. For instance, as memory capacity increases and the pitch between adjacent patterns are made narrower, the layout of the memory arrays and peripheral devices become more problematic, especially with regard to memory core layout. When designing memory circuits, it is desirable to minimize the length and loading of wordlines. Indeed, if wordlines are too long/narrow and/or have too many memory cells connected to each wordline (i.e., a large load), wordline enable driver circuits will consume more power to drive the wordlines, and the speed of driving wordlines can decrease. To mitigate the impact on device performance with line rule downscaling and increased memory density, various memory circuit architectures have been employed including, for example, hierarchical memory bank architectures and hierarchical word line driver structures with sub word line architectures. 
   For instance,  FIGS. 1A˜1C  are schematic illustrations of a semiconductor memory device having a conventional hierarchical memory bank architectures and hierarchical word line driver framework.  FIG. 1A  illustrates a semiconductor integrated circuit memory chip ( 10 ) having a memory cell array with a memory capacity of 1 Gb, which is divided into a plurality of memory banks, Bank A, B, C and D (or more generally, Bank-i) (e.g., 4 memory banks of 256 Mb). Each memory bank Bank-i can be independently operated with associated peripheral circuits including column decoders ( 11 ) and row decoders ( 12 ), and well as other I/O circuitry for outputting/inputting data via peripheral data I/O pads ( 13 ). Each memory bank Bank-i comprises decoder circuits and core circuits that are arranged in “unit blocks,” as depicted in  FIG. 1B . In particular,  FIG. 1B  schematically illustrates a conventional layout of each memory bank (Bank_i) in  FIG. 1A , wherein each memory bank (Bank-i) comprises a plurality of 256 unit blocks BL(i) including 16 unit blocks along an x-direction (bitline/column direction) and 16 unit blocks along a y-direction (wordline/row direction). 
     FIG. 1C  schematically illustrates a conventional layout pattern for each unit block BL-i in the memory bank Bank-i for a memory device utilizing a hierarchical sub-word line driver scheme. Each unit block BL-i includes a cell array ( 20 ), sub-word line driver (SWD) arrays ( 21 ), bit line sense amplifier (BSLA) arrays ( 23 ) and conjunction circuit blocks including PXiD driver blocks ( 22 ) and LA driver (LADRV) blocks ( 24 ). The unit block pattern BL-i depicted in  FIG. 1C  is repeated in both x and y directions over the memory bank Bank-i such that each memory cell array block ( 20 ) is disposed between two BLSA blocks ( 23 ) in the x (column) direction of bit lines and such that each memory cell array block ( 20 ) is disposed between two sub-word line drivers ( 21 ) in the y (wordline) direction. In one conventional hierarchical word line framework, each block sense amplifier ( 23 ) is shared by two memory cell array blocks ( 20 ) to the left and right of the BLSA ( 23 ) and each sub-word line driver ( 21 ) is shared by two memory cell array blocks ( 20 ) above and below the SWD block ( 21 ) using an interleaved layout framework, as is known in the art. 
   By way of specific example,  FIG. 2A  is a schematic illustration of one conventional framework of a unit block BL-i such as depicted in  FIG. 1C  in a semiconductor device having a hierarchical divided wordline scheme. As shown in  FIG. 2A , a memory cell array ( 200 ) includes an array of memory cells MC (each having a cell transistor and cell capacitor in a DRAM memory) located at the intersection of a bit line BL or BLB and a sub-word line WL. The bit lines are connected to the memory cells MC and to corresponding sense amplifiers SA in BLSA blocks ( 230 ) and ( 231 ) using an open bitline architecture, for example, as is known in the art. The BSLA blocks ( 230 ) and ( 231 ) are driven by control signals generated by drivers in respective LADRV blocks ( 240 ) and ( 241 ). In the hierarchical divided wordline scheme, a wordline is divided into a plurality of sub-wordlines WL that are driven using corresponding sub-wordline driver blocks ( 210 ) and ( 211 ) located above and below the memory cell array ( 200 ). In the exemplary embodiment of  FIG. 2A , there are 256 sub word lines WL that are connected to the memory cells in corresponding rows of memory cells (where the rows extend in the Y-direction). The SWD array ( 210 ) includes a plurality of sub word line driver SWD circuits that are connected to and drive the even sub wordlines (WLO, WL 2 , . . . WL 252 , WL 254 ) in the array ( 200 ) and a memory cell array of next lower unit block below. The SWD array ( 211 ) includes a plurality of sub word line driver circuits that are connected to and drive the odd sub wordlines WL 1 , WL 3 , . . . WL 253 , WL 255  in the array ( 200 ) as well as a memory cell array of a next upper unit block. 
   The SWDs in the SWD arrays ( 210 ) and ( 211 ) are connected to normal (main) wordlines NWE and sub wordline enable lines from respective PXiD drivers ( 220 ) and ( 221 ), respectively. Each SWD circuit in the even SWD array ( 210 ) drives a corresponding even sub word line in response to control signals input thereto via a corresponding normal wordline NWE (i) and a wordline enable signal generated by the PXiD drivers ( 220 ). Each SWD circuit in the odd SWD array ( 211 ) drives a corresponding odd sub word line in response to control signals input thereto via a corresponding normal wordline NWE (i) and a wordline enable signal generated by the PXiD drivers ( 221 ). The PXiD driver blocks ( 220 ) and ( 221 ) are connected to word lines PXI&lt;0:3&gt;, where each normal wordline NWE-i controls a group of 4 subwordlines, wherein a given subwordline in the group is activated in response to a corresponding one of the wordlines PXI ( 0 ,  1 ,  2 ,  3 ). For instance, NWE ( 0 ) controls subwordlines WL 0 , WL 1 , WL 2 , and WL 3  in response to wordline enable signals PXi&lt;0-3&gt;, NWE ( 1 ) controls subwordlines WL 4 , WL 5 , WL 6  and WL 7  in response to wordline enable signals PXi&lt;0-3&gt; and NWE ( 63 ) controls subwordlines WL 252 , WL 253 , WL 254 , and WL 255  in response to wordline enable signals PXi&lt;0-3&gt;. With reference to  FIG. 1B , there is a set of normal wordline enable lines NWE( 0 )-NEW( 63 ) that extends in the y-direction for each alternating even/odd column of 16 blocks (in the y direction) such that each odd and even SWD block in each even and odd column is connected to each NWE line of the corresponding set of normal wordline enable lines NWE( 0 )-NEW( 63 ). 
     FIG. 2B  schematically illustrates an exemplary embodiment of the PXiD driver ( 220 ) and the SWD array ( 210 ) of  FIG. 2A . The PXiD driver ( 220 ) comprises a PXiD generator ( 220   a ), a PXiDB generator ( 220   b ) and a PXiDG generator ( 220   c ). The SWD array ( 210 ) comprises a plurality of SWD circuits (SWD 0 ,  2 ,  4 , . . .  14 ) which are connected to and drive corresponding even subwordlines WL 0 , WL 2 , WL 4 , . . . , WL 14 ). Each NWE is connected to a pair of adjacent even SWDs in the even SWD array ( 220 ) as well as a corresponding pair of adjacent odd SWDs in the odd SWD array ( 211 ) (not specifically shown in  FIG. 2B ). The PXiD generator ( 220   a ), PXiDB generator ( 220   b ) and PXiDG generator ( 220   c ) generate word line activation control signals that are output on line PxID( 0 )/PXIDB( 0 )/PXiDG( 0 ) to activate the subword line drivers (SWD( 0 ), SWD( 4 ), SWD( 8 ), . . . ) in each group of 4 sub word lines, as well as word line activation control signals that are output on lines PxID( 2 )/PXIDB( 2 )/PXiDG( 2 ) to activate the subword drivers (SWD( 2 ), SWD( 6 ), SWD( 10 ), . . . ) in each group of 4 sub wordlines. 
     FIG. 3  is a flow chart that illustrates a method for accessing memory in a semiconductor memory device having a hierarchical wordline scheme such as described above. In general, for a given memory bank, Bank-I, a 12 bit address (A 0 , . . . A 11 ) is decoded to activate a sub wordline within one of the 256 memory cell arrays of the unit blocks. The upper four bits (A 8 , A 9 , A 10 , A 11 ) are decoded to select 1 of 16 of the adjacent vertical memory blocks (step  30 ) (n 4 =16). The next seven upper address bits A 2 ˜A 7  are decoded by a row decoder to generate one of 64 normal word line enable signals NWE&lt;0:63&gt;. The lower two address bits A 0 , A 1  are decoded by PXI decoders to drive a corresponding one of the sub word lines PXI&lt;0:3&gt;. As a result, one sub wordline out of the groups of 4 sub wordlines associated with the selected NWE is active where 4K bits of memory cells are enabled. 
     FIG. 4  illustrates a conventional sub word line driver circuit ( 40 ), which may be implemented for the SWDs in the even and odd SWD arrays ( 220 ) and ( 221 ) of  FIG. 2A , for example. In general, a sub-word line driving circuit ( 40 ) drives a sub-word line WL in response to control signals NWE, PXID, PXIDG and PXIDB, and includes NMOS transistors T 1 , T 2 , T 3  and T 4 . The sub word line driver ( 40 ) includes four control input nodes connecting to PXiD, PXiDG, PXiDB and NWE control signal lines, two power nodes for VPP and VSS and an output node N 5  connected to a subword line WL. The NMOS transistor T 3  has a channel connected between the NWE input (node N 4 ) and a node N 5  and a gate G 3  connected to the word line activation signal PXiDG. The NMOS transistor T 2  has a channel connected between control input node N 1  (signal PXiD) and the output node N 5  and a gate G 2  connected to a boosting node N 3 . The NMOS transistor T 1  has a channel connected between the gate G 2  of transistor T 2  and the NWE input node N 4  and a gate G 1  connected to the power voltage VPP input. The NMOS transistor T 4  has a channel connected between the output node N 5  and ground voltage node VSS and a gate G 4  connected to a control signal input node PXiDB. 
     FIG. 5  is a timing diagram that illustrates operation of the sub-word line driver ( 40 ) of  FIG. 4 . In particular,  FIG. 5  illustrates various voltage waveforms of control voltages NWEi, PXiD, PXiDB and PXiDG that are applied to drive a subwordline WLi. At time to, before an active operation, all of the signal lines shown in  FIG. 5  are at Vss except PXIDB, which is an active low level IVCC that is applied to the gate G 4  of transistor T 4  to cause the WL at node N 5  to be pulled down to VSS such that sub-word lines WL are precharged to Vss. At time t 1 , when a corresponding word line enable signal NWEi is activated, the boosting node N 3  is charged from VSS to VPP-Vth by an overlap capacitance existing between the gate G 2  and drain (N 1 ) of the transistor T 2  (where Vth denotes a threshold voltage of the NMOS transistor T 1 ). Therefore, the boosted voltage VPP is supplied to the sub-word line WL through the NMOS transistor T 2 . At time t 2 , the control voltage PXiDB transitions to VSS causing transistor T 4  to turn off. At time t 3 , the control signals PXID and PXIDG are asserted. The control signal PXiD is enabled to VPP, which causes the voltage at boosting node N 3  to increase to 2 Vpp-Vth. This causes the corresponding sub-word line driver SWD to drive the corresponding sub-word line to Vpp. The NMOS transistor T 3  serves to maintain the sub-word line WL in logic “low” state when the main word line driving signal NWE is in logic “low” state and the sub-word line driving signal PXID is in logic “high” state. After the access operation is complete, the sub-word line driver precharges the sub-word line WL to Vss. 
   Conventional semiconductor memory devices having a sub word line driver structure as described above may have an increased layout area due to the presence of the sub wordline driver arrays between the memory arrays. When designing semiconductor memory devices with sub word line driver framework, it is important to minimize the layout area required for the sub wordline drivers. Indeed, the layout area of the sub word line driving circuits has a significant influence upon the overall operating efficiency of the device memory device and the level of integration that may be achieved. 
   SUMMARY OF THE INVENTION 
   Exemplary embodiments of the invention generally include semiconductor memory devices having hierarchical word line structures and, in particular, semiconductor memory devices having sub-word line driver circuitry with layout patterns that enable increased integration density and high performance operation. 
   In one exemplary embodiment of the invention, a semiconductor memory device having a block of sub-word line driver circuits (SWDBs) disposed between a first block of memory and a second block of memory is provided. The SWDBs include a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each comprising four SWD circuits extending in a first direction between the first and second blocks of memory, wherein two adjacent SWD columns comprises a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory. In one exemplary embodiment, each SWD group drives even sub-wordlines extending into the first and second blocks of memory or odd sub-wordlines extending into the first and second blocks of memory. 
   In another exemplary embodiment, each SWD circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the first transistor of at least four SWD circuits of a given SWD group are arranged adjacent to each other and share an active region. The first transistors may have control gate electrodes that are substantially L-shaped. The second transistor of at least four SWD circuits of a given SWD group may be arranged adjacent to each other and share and a ground node. The second transistors may be arranged in a central region of the SWDB between the first and second memory blocks. 
   According to another aspect of the invention, a semiconductor DRAM (dynamic random access memory) device is provided, comprising: a plurality of separately controlled memory banks, wherein each memory bank comprises: a matrix of separate memory blocks extending in column and row directions over the memory bank; a block of row decoder circuits disposed along one side of the memory bank, a set of n normal wordlines extending from each block of row decoder circuits along each row of memory blocks of the memory bank; a block of sub-word line driver circuits (SWDB) disposed between each memory block in row direction of the memory band and connected to each set of n normal wordlines extending along the given row of memory blocks, wherein each SWDB comprises a plurality of sub-wordline driver (SWD) circuits arranged in a plurality of SWD columns each comprising four SWD circuits extending in a first direction between the first and second blocks of memory, wherein two adjacent SWD columns comprises a SWD group for driving a plurality of sub-word lines extending from the SWD group along the first direction into the first and second blocks of memory. 
   These and other exemplary embodiments, aspects, objects, features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For instance,  FIGS. 1A˜1C  are schematic illustrations of a semiconductor memory device having a conventional hierarchical memory bank architectures and hierarchical word line driver framework. 
       FIG. 2A  is a schematic illustration of one conventional framework of a unit block BL-i such as depicted in  FIG. 1C  in a semiconductor device having a hierarchical divided wordline scheme. 
       FIG. 2B  schematically illustrates a conventional embodiment of a PXiD driver and SWD array of  FIG. 2A . 
       FIG. 3  is a flow chart that illustrates a method for accessing memory in a semiconductor memory device having a hierarchical wordline scheme. 
       FIG. 4  is a schematic illustration of a conventional sub word line driver circuit. 
       FIG. 5  is a timing diagram that illustrates operation of the sub-word line driver of  FIG. 4 . 
       FIG. 6  schematically illustrates a layout pattern for sub word line drivers according to an exemplary embodiment of the invention. 
       FIG. 7  is a schematic circuit diagram of an SWD group according to an exemplary embodiment of the invention 
       FIG. 8  depicts a general layout pattern of a group of sub word line drivers SWD according to an exemplary embodiment of the invention, 
       FIG. 9  schematically illustrates an exemplary layout of the transistors for each of the SWD drivers in  FIG. 7  in each of the corresponding regions R depicted in  FIG. 8 . 
     FIGS.  10 A/ 10 B are exploded views of upper and lower halves of the SWD group of  FIG. 9   
       FIGS. 11A˜11H  schematically illustrate various levels of the FEOL circuitry and BEOL metallization patterns of the upper half of the SWD group of  FIG. 9 . 
   

   DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
   Exemplary embodiments of the invention will now be described more fully with reference to the accompanying drawings in which it is to be understood that the thickness and dimensions of the layers and regions are exaggerated for clarity. It is to be further understood that when a layer is described as being “on” or “over” another layer or substrate, such layer may be directly on the other layer or substrate, or intervening layers may also be present. Moreover, similar reference numerals used throughout the drawings denote elements having the same or similar functions. 
     FIG. 6  schematically illustrates a layout pattern for sub word line drivers according to an exemplary embodiment of the invention.  FIG. 6  illustrates a memory cell array ( 60 ) disposed between an odd SWD array ( 61 ) and even SWD array ( 62 ).  FIG. 6  illustrates a layout structure where each SWD array ( 61 ) and ( 62 ) comprises adjacent groups of four vertically stacked sub word line drivers (stacked in the y (row) direction) that extend in the x (bitline) direction over the array ( 60 ). In one exemplary embodiment of the invention, the SWD array ( 61 ) includes SWD drivers that drive odd numbered subword lines WL of the array ( 60 ) and the SWD array ( 62 ) includes SWD drivers that drive even numbered wordlines WL of the array ( 60 ). For instance, in  FIG. 6 , a first group of stacked SWDs in the SWD array ( 62 ) includes SWDs  0 ,  2 ,  4  and  6  that drive corresponding subwordlines WL  0 ,  2 ,  4 ,  6  of array ( 60 ) and a second group of stacked SWDs ( 8 ,  10 ,  12 ,  14 ) drive corresponding sub wordlines WL  8 ,  10 ,  12  and  14  of array ( 60 ). A first group of stacked SWDs in the SWD array ( 61 ) includes SWDs  1 ,  3 ,  5  and  7  that drive corresponding subwordlines WL  1 , 3 ,  5  and  7  of array ( 60 ) and a second group of stacked SWDs ( 9 ,  11 ,  13 ,  15 ) that drive corresponding subwordlines WL  9 ,  11 ,  13 ,  15 ) of array ( 60 ). With this exemplary layout, an increase in metal pitch is realized and more compact layout in x direction since every eight sub word lines WL of polysilicon are classified as respective groups and two normal word lines NWE metal line pass over the eight sub word line groups of poly-silicon. 
   Moreover, to minimize the space occupied by each SWD array ( 61 ) and ( 62 ) in the y direction, the SWD driver circuits are patterned such that two adjacent vertically stacked SWDs comprise a SWD set of eight SWDs that share signal nodes. For instance, in the even SWD array ( 62 ), the first two groups of 4 stacked SWDs ( 0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12 ,  14 ) form a set of 8 even SWDs that have a compact layout pattern, which is repeated in the X (direction of bit line) across the array ( 60 ). Moreover, in the odd SWD array ( 61 ), the first two groups of 4 stacked SWDs ( 1 ,  3 ,  5 ,  7 ,  9 ,  11 ,  13 ,  15 ) form a set of 8 odd SWDs that have a compact layout pattern, which is repeated in the X (direction of bit line) across the array ( 60 ). The layout patterns for the odd and even SWD sets are the same. 
     FIG. 7  is a schematic circuit diagram of the first even SWD set of the even SWD array ( 62 ) of  FIG. 6 . As shown, each SWD 0 ˜SWD 14  is connected to a respective sub word line WL 0 ˜WL 14 , and is controlled by two pairs of PXiD and PXiDG control signals. Each SWD 0 ˜SWD 14  is an NMOS type SWD as described above with reference to  FIG. 4 . As will be explained, the SWD group can have a layout pattern comprising two adjacent columns of 4 stacked SWDs where signal connections are shared to reduce space. For instance, in  FIG. 7 , the layout pattern of transistors T 1 , T 2 , T 3  and T 4  for the SWDs  0 ,  4 ,  8  and  12  is formed such that the PxID( 0 ) signal node is shared by the transistors T 2  of SWDs  0 ,  4 ,  8 ,  12  and such that the transistors T 4  share the PXiDB( 0 ) signal node and ground VSS node. Moreover, the layout pattern of transistors T 1 , T 2 , T 3  and T 4  for the SWDs  2 ,  6 ,  10  and  14  is formed such that the PXiD( 2 ) signal node is shared by the transistors T 2  of SWDs  2 ,  6 ,  10  and  14  and such that the transistors T 4  share the PXiDB( 2 ) signal node and ground VSS node. 
   An exemplary layout pattern for the schematic circuit of  FIG. 7  will now be discussed in further detail with reference to  FIGS. 8 ,  9 ,  10 A,  10 B and  11 A˜ 11 F. In general,  FIG. 8  is a schematic diagram of a layout pattern for a SWD set according to an exemplary embodiment of the invention. For purposes of illustration,  FIG. 8  depicts a general layout pattern of sub word line drivers SWD ( 0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12 ,  14 ) of  FIG. 7 .  FIG. 8  shows different regions R 0 , R 2 /R 2 ′, R 4 /R 4 ′, R 6 , R 8 /R 8 ′, R 10 , R 12  and R 14 /R 14 ′ in which the transistors T 1 ˜T 4  of respective SWD drivers  0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12  and  14  are formed.  FIGS. 9 ,  10 A and  10 B illustrate an exemplary layout of the transistors T 1 , T 2 , T 3  and T 4  for each of the SWD drivers in  FIG. 7  in each of the corresponding regions R depicted in  FIG. 8 , including the active transistor regions, polysilicon gate lines, and contacts (DC) locations of transistor gates and diffusion (drain/source) regions in the active regions. 
     FIGS. 11A˜11H  schematically illustrate various levels of the FEOL circuitry and BEOL metallization patterns of the upper SWD regions R 0 , R 4 , R 4 ′, R 8 , R 8 ′ and R 12  for SWD 0 , SWD 4 , SWD 8 , and SWD  12 .  FIG. 11A  illustrates an exemplary layout structure of active regions formed on a semiconductor substrate.  FIG. 11B  illustrates a gate line polysilicon layer that is formed on the active substrate surface.  FIG. 11C  illustrates an exemplary pattern of interlevel contacts to diffusion regions (drain/source) of the transistors and to poly gate lines.  FIG. 11D  illustrates an exemplary polysilicon pattern comprising sub word lines (WL  0 ,  2 , . . . ,  14 ) that are formed over the active components extending as well as pads for interlevel connections.  FIG. 11E  schematically illustrates a metal interlevel contact layer that is formed over the polysilicon pattern providing via contacts to certain points of the poly silicon pattern of  FIG. 11D .  FIG. 11F  schematically illustrates an exemplary metallic pattern (first level metallization) providing normal word line enable lines as well as contact pads.  FIG. 11G  schematically illustrates a pattern of via contacts providing interlevel connections between layers  11 F and  11 H.  FIG. 11H  schematically illustrates a second metal layer pattern formed over the via layer providing PXI control signal lines. 
   Referring to  FIGS. 9 ,  10 A/ 10 B and  11 A/ 11 B, the transistors T 1 ˜T 4  of each SWD circuit ( 0 ,  2 , ˜ 14 ) in  FIG. 7  are formed by corresponding active regions A(T 1 , T 3 ), A(T 2 ) and A(T 1 , T 3 , T 4 ) and gate lines G 1 , G 2 , G 3  and G 4 . In particular, the transistors T 1  and T 3  for SWDs  2 ,  4 ,  8 ,  14  include separate active regions A(T 1 ,T 3 ) within respective regions R 2 , R 4 , R 8  and R 14  and common gate lines G 1  and G 3  that are formed over the active regions A(T 1 , T 3 ) and which extend between regions R 4  and R 8  and between regions R 2  and R 14 . The transistors T 2  for SWDs  0 ,  4 ,  8  and  12  share a common active region A(T 2 ) and have separate gate lines G 2 . Similarly, the transistors T 2  for SWDs  2 ,  6 ,  10  and  14  share a common active region A(T 2 ) and have separate gate lines G 2 . 
   The transistors T 1 , T 3  and T 4  for SWDs  0 ,  12  include separate active regions A(T 1 ,T 3 , T 4 ) and common gate lines G 1 , G 3  and G 4  that extend over the separate active regions A(T 1 , T 3 , T 4 ). Similarly, the transistors T 1 , T 3  and T 4  for SWDs  6 ,  10  include active regions A(T 1 ,T 3 , T 4 ) and common gate lines G 1 , G 3  and G 4  that extend over the separate active regions. 
   The transistors T 4  for SWDs  2 ,  4 ,  8 , and  14  are formed in regions R 2 ′, R 4 ′, R 8 ′ and R 14 ′, respectively, separate from regions R 2 , R 4 , R 8  and R 14  in which transistors T 1 , T 2  and T 3  are formed. In particular, the transistors T 4  for SWDs  2 ,  4 ,  8 ,  14  include separate active regions (T 4 ) and common gate lines G 4 . The transistors T 4  for SWDs  4 ,  8  include a common gate line G 4  that extends over the separate active regions A(T 4 ) in regions R 4 ′ and R 8 ′ and the transistors T 4  for SWDs  2 ,  14  include a common gate line G 4  that extends over the separate active regions A(T 4 ) between regions R 2 ′ and R 14 ′. 
   The transistors T 2  of SWDs  0 ,  4 ,  8  and  12  share a common active region A(T 2 ) in abutting regions R 0 , R 4 , R 8  and R 12 , and have separate gate lines G 2 . The transistors T 2  of SWDs  2 ,  6 ,  10  and  14  share a common active region A(T 2 ) in adjacent regions R 2 , R 6 , R 10  and R 14  and have separate gate lines G 2 . As shown, the portions of the gate lines G 2  of transistors T 2  of SWD  0 ,  4 ,  8 ,  12  that overly the active region A(T 2 ) are substantially L-shaped and form a mirror image pattern over the boundaries between regions R 0 , R 4 , R 8  and R 12 . Similarly, the portions of the gate lines G 2  of transistors T 2  of SWD  2 ,  6 ,  10 ,  14  that overly the active region A(T 2 ) are substantially L-shaped and form a mirror image pattern over the boundaries between regions R 2 , R 6 , R 10  and R 14 . The L shaped gate patterns of G 2  enable the channel width of the transistors T 2  to be maximized, while minimizing the amount of space occupied by the gates G 2  in the y-direction. 
   The exemplary active device layout pattern of the SWDs  0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12 ,  14  form a compact layout in which corresponding transistors from different SWD circuits share diffusion regions and/or gate lines with contacts to common control signals in order to minimize space. For instance, with reference to  FIGS. 10A ,  10 B and  11 C, the common gate line G 1  for transistors T 1  in regions R 4  and R 8  provides a common VPP input for SWDs  4  and  8 . Similarly, the common gate line G 1  for transistors T 1  in regions R 0 -R 12  provides a common VPP input for SWDs  0  and  12 , The common gate line G 1  for transistors T 1  in regions R 6  and R 10  provides a common VPP input for SWDs  6  and  10 , and the common gate line G 1  for transistors T 1  in regions R 2  and R 14  provides a common VPP input for SWDs  2  and  14 . 
   Further, as shown in  FIG. 10A , the common gate line G 3  for transistors T 3  in regions R 4  and R 8  provides a common PXiDG( 0 ) input for SWDs  4  and  8 , and the common gate line G 3  for transistors T 3  in regions R 0  and R 12  provides a common PXiDG( 0 ) for SWDs  0  and  12 . Similarly, as shown in  FIG. 10B , the common gate line G 3  for transistors T 3  in regions R 6  and R 10  provides a common PXiDG( 2 ) input for SWDs  6  and  10 , and the common gate line G 3  for transistors T 3  in regions R 2  and R 14  provides a common PXiDG( 2 ) input for SWDs  2  and  14 . 
   The transistors T 1  and T 3  for each SWD ( 0 ,  2 ,  4 ,  6 ,  8 ,  10 ,  12 ,  14 ) share a common diffusion region (node N 4 ) between gates G 1  and G 3  wherein a contact CN 4  is formed. The contacts CN 4  in regions R 0  and R 2  form part of the interconnections from the diffusion regions of transistor T 1  and T 3  at node N 4  to the NWE( 0 ) lines in upper metal layers. The contacts CN 4  in regions R 4  and R 6  form part of the interconnections from the diffusion regions of transistor T 1  and T 3  at node N 4  to the NWE( 1 ) lines in upper metal layers. The contacts CN 4  in regions R 8  and R 10  form part of the interconnections from the diffusion regions of transistor T 1  and T 3  at node N 4  to the NWE( 2 ) lines in upper metal layers, and the contacts CN 4  in regions R 12  and R 14  form part of the interconnections from the diffusion regions of transistor T 1  and T 3  at node N 4  to the NWE( 3 ) lines in upper metal layers. 
   Further, as depicted in  FIG. 10A , the common gate line G 4  for transistors T 4  in regions R 4 ′ and R 8 ′ provides a common PXiDB( 0 ) input for SWDs  4  and  8 , and the common gate line G 4  for transistors T 4  in regions R 0  and R 12  provides a common PXIDB( 0 ) input for SWDs  0  and  12 . This layout allows the transistors T 4  of SWDs  0 ,  4 ,  8  and  12  to share a common diffusion region between the gate lines G 4  providing a common ground VSS node having contacts CVSS. Similarly, as depicted in  FIG. 10B , the common gate line G 4  for transistors T 4  in regions R 2 ′ and R 14 ′ provides a common PXiDB( 2 ) input for SWDs  2  and  14 , and the common gate line G 4  for transistors T 4  in regions R 6  and R 10  provides a common PXiDB( 2 ) input for SWDs  6  and  10 . This layout allows the transistors T 4  of SWDs  2 ,  6 ,  10 , and  14  to share a common diffusion region between the gate lines G 4  providing a common ground VSS node with contact CVSS. 
   As depicted in  FIG. 10A , the transistors T 2  for SWDs  0 ,  4 ,  8 , and  12  have gates G 2  that share common diffusion regions (node N 1 ) where a first contact CN 1  is formed on a portion of the common active diffusion region between the gate lines G 2  of transistors T 2  of SWDs  4  and  8 , and where a second contact CN 1  is formed on a portion of the common active diffusion region between the gate lines G 2  of transistors T 2  of SWDs  0  and  12 . The contacts CN 1  are commonly connected to a PXiD( 0 ) control signal line at upper level. As such, the SWDs  0 ,  4 ,  8  and  12  commonly share the PXiD( 0 ) signal. Similarly, as depicted in  FIG. 10B , the transistors T 2  for SWDs  2 ,  6 ,  10 , and  14  have gates G 2  that share common diffusion regions (node N 1 ) where a first contact CN 1  is formed on a portion of the common active diffusion region between the gate lines G 2  of transistors T 2  of SWDs  2  and  14 , and where a second contact CN 1  is formed on a portion of the common active diffusion region between the gate lines G 2  of transistors T 2  of SWDs  6  and  10 . Theses contacts CN 1  are commonly connected to a PXiD( 2 ) control signal line at upper level. As such, the SWDs  2 ,  6 ,  10  and  14  commonly share the PXiD( 2 ) signal. 
   Moreover, as depicted in FIGS.  10 A/ 10 B and  11 C, a plurality of contacts CN 3  are formed in regions R 0 , R 2 , R 4 , R 6 , R 8 , R 10 , R 12  and R 14  which enable upper level connections between the gate G 2  of the transistor T 2  and diffusion region of transistor T 1  in each SWD. In particular, in each SWD region, a pair of contacts CN 3  contact are formed on the diffusion region of the transistor T 1  next to the gate line G 1  and formed on an extended portion of the gate line G 2  of the transistor T 2  that does not overlap any portion of the active region A(T 2 ) and which is adjacent to the contact CN 3  on diffusion region. As explained below, each pair of contacts CN 3  is commonly connected at an upper level to providing a boosting node N 3  connection between the gate of T 2  and the source of T 1  in each SWD circuit. 
   Moreover, as depicted in FIGS.  10 A/ 10 B and  11 C, a plurality of contacts CN 5  are formed at various points in each of the regions R 0 , R 2 , R 2 ′ R 2 ′, R 4 , R 4 ′ R 6 , R 8 , R 8 ′ R 10 , R 12 , R 14  and R 14 ′ to provide connections (node N 5 ) between drain/source diffusion regions of transistors T 2 , T 3 , and T 4  of each SWD circuit to a corresponding subwordline in a poly layer pattern above the SWD regions. 
   In the SWD  4  circuit, two separate contacts CN 5  are formed in region R 4  at the diffusion regions of transistors T 2  and T 3  next to respective gate lines G 2  and G 3  and another contact CN 5  is formed in region R 4 ′ at the diffusion region of transistor T 4  next to the gate line G 4 . 
     FIG. 11D  schematically illustrates a layout pattern of a portion of the subwordlines (WL  0 ,  2  . . .  14 ) that are formed over the contact layer of  FIG. 11C  in SWD regions R 0 , R 4 /R 4 ′, R 8 /R 8 ′ and R 12 . In  FIG. 11D , the end portions of the upper level subwordlines WL ( 0 ,  2 ˜ 14 ) in  FIG. 11D  are connected to the end portions of the lower level subwordlines (WL ( 0 ,  2 ˜ 14 ) in  FIG. 11B  via respective contacts WC ( 0 ,  2 , ˜ 14 ) of  FIG. 11C . 
   The contacts CN 5  in regions R 4 /R 4 ′ provide connections between diffusion regions of transistors T 2 , T 3  and T 4  of SWD 4  to contact points P(N 5 ) along the sub wordline WL 4  in the upper poly layer as shown in  FIG. 11D . The contacts CN 5  in region R 0  provide connections between diffusion regions of transistors T 2 , T 3  and T 4  of SWD 0  to contact points P(N 5 ) along the sub wordline WL 0  in the upper poly layer as shown in  FIG. 11D . The contacts CN 5  in regions R 8 /R 8 ′ provide connections between diffusion regions of transistors T 2 , T 3  and T 4  of SWD 8  to contact points P(N 5 ) along the sub wordline WL 8  in the upper poly layer as shown in  FIG. 11D . The contacts CN 5  in region R 12  provide connections between diffusion regions of transistors T 2 , T 3  and T 4  of SWD 12  to contact points P(N 5 ) along the sub wordline WL 12  in the upper poly layer as shown in  FIG. 11D . Although not specifically shown, the contacts CN % in the SWD regions R 2 /R 2 ′, R 6 , R 10 , and R 14 /R 14 ′ providing connections between the diffusion region of the transistors T 2 , T 3 , and T 4  of each SWD  2 ,  6 ,  10  and  14  to contact points P(N 5 ) along respective portions of sub wordlines WL 2 ,  6 ,  10  and  14  extend in the upper poly layer above the SWD regions for SWDs  2 ,  6 ,  10  and  14 . 
   As further depicted in  FIG. 11D , the poly pattern includes isolated pad patterns PN 1 , PN 3 , PN 4 , and PVSS. In particular, the pad PN 1  in the poly layer of  FIG. 11D  is connected to both contacts CN 1  to provide a common connection between the drain diffusion regions of the transistors T 2  for SWDs  0 ,  4 ,  8  and  12 . The pad patterns PN 3  in each region R 0 , R 4 , R 8  and R 12  provide a common connection between the contact pairs CN 3  in each of the respective regions. The pad patterns PN 4  provide contact pads for the diffusion region contacts CN 4  that contact to common diffusion regions of transistors T 1 , T 3  in each SWD region Ro, R 4 , R 8  and R 12 . Moreover, the pads P(VSS) provide contact pads for the ground contacts CVSS that contact the common ground node diffusion region between the gate elements G 4  of region R 0 /R 12  and R 4 ′/R 8 ′. 
     FIG. 11E  illustrates a next layer of metal contacts that are formed over the polysilicon layer of  FIG. 11D  providing interlevel connections to conductive lines and pads of a first metallization level of  FIG. 11F . In particular, in  FIG. 11E , a plurality of contacts MC(N 1 ) are formed to provide interlevel contacts between the poly pad element PN 1  in  FIG. 11D  to a metal pad element MP(N 1 ) in  FIG. 11F . The metal pad element MP(N 1 ) is connected to a PXiD( 0 ) control signal line formed on a second metallization level ( FIG. 11H ) by interlevel via contacts V(N 1 ) as shown in  FIG. 11G ). As such, the control signal line PXiD( 0 ) is commonly connected to each drain region of transistor T 2  of SWDs  0 ,  4 ,  8  and  12 ). 
     FIG. 11F  illustrates a layout pattern of portions of normal wordlines NWE ( 0 ,  1 ,  2 ,  3 ) that are formed over the poly wordline layer of  FIG. 11D  in SWD regions R 0 , R 4 /R 4 ′, R 8 /R 8 ′ and R 12 . The normal wordlines NWE 0  and NWE 1  extend in the y-direction over the stacked SWD regions R 4 /R 0 /R 4 ′/R 2 ′/R 6 /R 2 , and the normal wordlines NWE 2  and NWE 3  extend in the y-direction over the stacked SWD regions R 8 /R 12 /R 8 ′/R 14 ′/R 10 /R 14 . The interlevel contact layer of  FIG. 11E  includes metal contact MCN 4  in regions RO, R 4 , R 8  and R 12  that connect the poly pad elements PN 4  in  FIG. 11D  in respective regions to portions MP(N 4 ) of the NWEs  0 ,  1 ,  2  and  3  in the metal layer of  FIG. 11F . Although not specifically shown, portions of the NWEs  0 ,  1 ,  2 ,  3  that extend over the SWD regions  2 ,  6 ,  10  and  14  are connected to MCN 4  and PN 4  contacts in the regions R 2 , R 6 , R 10  and R 14 . 
   In  FIG. 11E , a plurality of contacts MC(VSS) are formed to provide interlevel contacts between the poly pad element P(VSS) in  FIG. 11D  to a metal pad element MP(VSS) in  FIG. 11F . The metal pad element MP(VSS) is connected to a VSS signal line control signal line formed on the second metallization level ( FIG. 11H ) by interlevel via contacts V(VSS) as shown in  FIG. 11G . As such, the VSS power line is commonly connected to the VSS node between transistors T 4  of SWDs  0 ,  4 ,  8  and  12 ). 
   In  FIG. 11E , a plurality of contacts MC(N 1 ) are formed to provide interlevel contacts between poly pad element P(N 1 ) in  FIG. 11D  to a metal pad element MP(N 1 ) in  FIG. 11F . The metal pad element MP(N 1 ) is connected to a PXiD( 0 ) control signal line formed on the second metallization level ( FIG. 11H ) by interlevel via contacts V(N 1 ) as shown in  FIG. 11G . As such, the PXiD( 0 ) line is commonly connected to the diffusion contact nodes CN 1  in  FIG. 11C  between the gates G 2  of transistors T 2  of SWDs  0 ,  4 ,  8  and  12 ). 
   While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.