Abstract:
PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS  
       [0001]     This application relates to the patent application Ser. No. 11/317,653, titled “Trench Field Plate Termination For Power Devices,” filed Dec. 22, 2005, incorporated herein by reference in its entirety for all purposes. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     There continues to be a growing demand for semiconductor power devices (i.e., devices capable of carrying large currents at high voltages). Such devices include bipolar transistors, insulated gate bipolar transistors (IGBT), metal oxide semiconductor field effect transistors (MOSFET) and other types of field effect transistors. Notwithstanding significant advances in power device technology, there remains a need for still higher-performing and more cost-effective devices. As the complexity and sophistication of power devices increases, the number of process steps and masks in the manufacturing process also increases, significantly increasing the manufacturing costs. Thus, processing techniques which help reduce the number of process steps and/or masks while maintaining or even increasing the device performance would be desirable.  
         [0003]     Furthermore, it is desirable to increase the current density relative to the total die area of a device. One of the limiting factors to higher current ratings is the breakdown voltage, particularly in the edge termination region where array junctions terminate. Because semiconductor junctions include curvatures, numerous techniques are employed to avoid otherwise high concentration of electric field lines. It is conventional in power device design to incorporate edge termination structures with planar field plates along the outer periphery of the device in order to ensure that the breakdown voltage in this region of the device is not any lower than in the active region of the device. However, termination structures (particularly the planar field plate variety) occupy relatively large areas of the die and require additional masking and processing steps, thus resulting in increased costs.  
         [0004]     Thus, there is a need for improved power devices with enhanced trench termination structures and cost-effective methods of forming the same.  
       BRIEF SUMMARY OF THE INVENTION  
       [0005]     In accordance with an embodiment of the invention, a trench gate FET is formed as follows. The FET is formed in a semiconductor die comprising an active region for housing active transistor cells and a termination region surrounding the active region. A well region is formed in the active region and the termination region at the same time. The well region is formed in a silicon region having a conductivity type opposite that of the well region. A plurality of active gate trenches are formed in the active region simultaneously with a non-active termination trench formed in the termination region. The plurality of active gate trenches and the non-active termination trench extend into and penetrate through the well region to there by divide the well region into a plurality of active body regions in the active region and a termination body region in the termination region. Using a mask, an opening is formed over the termination body region and an opening is formed over the active region. Dopants are implanted into the active body regions through the opening over the active region and into the termination body region through the opening over the termination body region, thereby forming a first region in each active body region and in the termination body region. The first regions have a conductivity type opposite that of the well region. Exposed surfaces of all first regions are recessed using a silicon etch to form a bowl-shaped silicon recess having slanted walls and a bottom protruding through each first region such that portions of each first region remain in a corresponding active body region. The remaining portions of the first regions in the active body regions form source regions which are self-aligned to the active gate trenches.  
         [0006]     In one embodiment, dopants are implanted into the bowl-shaped silicon recesses to form a heavy body region in each active body region and in the termination body region. The heavy body regions have the same conductivity type as the well region.  
         [0007]     In another embodiment, a metal layer is formed over the semiconductor die. The metal layer is then patterned to form: (i) a source metal layer extending into each bowl-shaped silicon recess in the active region to electrically contact the source regions and the heavy body regions in the active region, and (ii) a field plate extending into the non-active termination trench and into the bowl-shaped silicon recess formed in the termination body region to electrically contact the heavy body region formed in the termination body region, wherein the source metal layer and the field plate are insulated from one another.  
         [0008]     In another embodiment, a termination dielectric layer is formed in the non-active termination trench. A field plate comprising conductive material is formed in the trench over the termination dielectric layer. The termination dielectric layer insulates all portions of the field plate inside the non-active termination trench from all silicon regions surrounding the non-active termination trench. The field plate is formed so as to extend out of the non-active termination trench and into the bowl-shaped silicon recess formed in the termination body region to thereby electrically contact the heavy body region formed in the termination body region.  
         [0009]     In yet another embodiment, the non-active termination trench extends to an edge of the semiconductor die such that the non-active termination trench forms a vertical wall at which the well region terminates.  
         [0010]     In yet another embodiment, non-active gate runner trenches are formed at the same time that the active gate trenches and the non-active termination trench are formed such that the non-active gate runner trench, the active gate trenches and the non-active termination trench extend to the same depth. A recessed gate electrode is formed in each active gate trench and a recessed gate runner electrode is formed in the non-active gate runner trench at the same time. The recessed gate electrode in each active gate trench is electrically connected to the recessed gate runner electrode in the non-active gate runner trench.  
         [0011]     In yet another embodiment, the active gate trenches are stripe shaped extending along a first direction, and the non-active gate runner trench extends, at least in part, along a direction perpendicular to and is contiguous with the active gate trenches.  
         [0012]     A better understanding of the nature and advantages of the present invention can be gained from the following detailed description and the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIGS. 1A-1K  are simplified cross-section views at various steps of a manufacturing process for forming a self-aligned MOSFET with improved trench termination structure, in accordance with an exemplary embodiment of the invention; and  
         [0014]      FIG. 2  is a simplified cross-section view showing a trench gate runner structure formed without requiring additional processing steps, in accordance with an exemplary embodiment of the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0015]     The present invention relates generally to semiconductor power device technology, and more particularly to improved power devices with enhanced termination structures, and methods of forming the same.  
         [0016]      FIGS. 1A-1K  are simplified cross-section views at various steps of a manufacturing process for forming a self-aligned MOSFET with a trench field plate termination structure, in accordance with an exemplary embodiment of the invention.  FIG. 2  is a simplified cross-section view showing a trench gate runner structure formed without requiring additional processing steps to those depicted by  FIGS. 1A-1K . All drawings described herein are merely illustrative and thus are not intended to unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many possible variations, modifications, and alternatives in view of this disclosure.  
         [0017]     In  FIG. 1A , a lightly doped N-type epitaxial layer  104  is formed over a highly doped N-type substrate using conventional techniques. A lightly doped P-type well region  106  is formed in an upper portion of epitaxial layer  104  using a conventional blanket implantation of p-type dopants into epitaxial layer  104 . A vertical line is used to show the border between the active region and the termination region of the die in which the FET is formed. As in conventional FETs, the active region of the die includes the active cell transistors, and the termination region surrounds the active region and includes the termination structure. In conventional processes, a mask is typically required to block the termination region from receiving the P-type implant. However, as will be seen, the structure and method of manufacture of the present invention allow the use of a blanket implant at this stage of the process thus eliminating the masking step that is typically required.  
         [0018]     A hard mask  108  (e.g., comprising oxide) is then formed over well region  106  and then patterned to form openings  110  using conventional techniques. In  FIG. 1B , silicon is removed through openings  110  to thereby form active gate trenches  116  in the active region, and to form a termination trench  120  in the termination region. Trenches  116  and  120  penetrate well region  106  such that well region  106  is divided into a number of active body regions  106 B and a termination body region  106 A. As shown, termination trench  120  extends to an edge of the die such that termination body region  106 A terminates at a vertical wall of termination trench  120 . The curvature of the P-type region present in the termination region of prior art structures is thus advantageously eliminated. While termination trench  120  is shown to extend into the street (i.e., regions separating adjacent dice on a wafer), termination trench  120  may also be formed so as to terminate before reaching the street. Also, while active trenches  116  and termination trench  120  are shown to terminate at a depth immediately below that of well region  106 , trenches  116  and  120  could instead be extended deeper into epitaxial layer  104  or even into substrate  102  depending on the design goals and the target performance characteristics.  
         [0019]     In  FIG. 1C , hard mask  108  is removed and then a relatively thick shield dielectric layer  122  (e.g., comprising oxide) extending into active trenches  116  and termination trench  120  and over the mesa regions is formed using known techniques. The thickness of shield dielectric layer  122  is generally greater than that of the gate dielectric, and is primarily dictated by the voltage rating of the device. In  FIG. 1D , shield dielectric layer  122  is masked and patterned in a photolithography step, and subsequently removed from the active region to yield shield dielectric layer  124  in the termination region. In this manner, a thick high quality dielectric layer is advantageously formed in termination trench  120 . In an alternate embodiment, no shield dielectric is formed thus eliminating the masking and process steps of  FIGS. 1C and 1D . In this alternate embodiment, the dielectric in termination trench  120  would comprise of a later formed gate dielectric layer (i.e., layer  126  in  FIG. 1E ) and a thicker dielectric layer (i.e., layer  127  in  FIG. 1H ) such as borophosphosilicate glass (BPSG) overlying the gate dielectric layer.  
         [0020]     In  FIG. 1E , a gate dielectric layer  126  is formed using conventional techniques such as oxidation of silicon. As shown, gate dielectric layer  126  is formed along all exposed silicon surfaces including the active gate trench sidewalls and bottom. In  FIG. 1F , a polysilicon layer  128  is formed over the gate dielectric layer  126  and shield dielectric  124 , filling active trenches  116  and extending into termination trench  120 . In  FIG. 1G , polysilicon layer  128  is recessed to a predetermined depth in active gate trenches  116  using known techniques. Gate electrodes  130  are thus formed. The polysilicon recessing results in complete removal of the polysilicon in termination trench  120 . While conventional techniques require a masking step to separately define the polysilicon in the termination and active regions, the manufacturing process and structure of the present invention eliminate this masking step. In an alternate embodiment, active body regions  106 B and termination body region  106 A are formed by implanting P-type dopants after recessing of the polysilicon rather than early in the process flow ( FIG. 1A ).  
         [0021]     In  FIG. 1H , a dielectric layer  127  is formed (e.g., using oxide deposition), and then patterned using a. contact mask, followed by a dielectric etch using silicon as an etch stop. Active trenches  116  are thus filled with dielectric material  127 , and openings  132  are formed to expose a surface portion of termination body region  106 A as well as the mesa surfaces in the active region. Also, dielectric  127  together with shield dielectric  124  form a thicker dielectric  125  in termination trench  120 . In  FIG. 1I , a blanket source implant and drive are carried out to form N-type regions  136  in active body regions  106 B and in termination body region  106 A through exposed silicon surfaces. Dielectric  125  and  127  serve as blocking layers preventing their underlying regions from receiving the source implant. In conventional termination structures, because termination body region  106 A is electrically tied to the source region, an additional masking step is required to prevent termination body region  106 A from receiving the source implant in order to eliminate latch-up concerns. However, in the embodiment described herein, source implant into termination body region  106 A can occur because termination body region  106 A can float. A masking step required by prior art processes is thus eliminated.  
         [0022]     In  FIG. 1J , a blanket dimple etch of silicon (e.g., an in-situ angled silicon etch) is carried out to recess all exposed silicon surfaces to below the bottom surface of N-type regions  136 , thus forming contact openings  144 . Contact openings  144  possess a sloped sidewall profile due to the angled etch process used. Triangular-shaped portions of the N-type regions  139  remaining in the array region form source regions  137  which are advantageously self-aligned to array trenches  116 . Also, of the N-type region  136  in the termination region, portions  139  remain. Next, a blanket implant of P-type dopants followed by a drive-in step are carried out to form heavy body regions  140  in active body regions  106 B and termination body region  106 A through contact openings  144 . Note that the heavy body region  140  in termination body region  106 A provides a low resistance contact between field plate  148  and termination body region  106 A. This is achieved without requiring additional processing steps.  
         [0023]     In  FIG. 1K , conventional metal deposition, photolithography, and etch steps are carried out to form source metal  146 , gate runner metal (layer  149  in  FIG. 2 ), and termination field plate metal  148 . The deposited metal fills in contact openings  144 . Source metal  146  contacts source regions  137  and heavy body regions  140  in the active area of the device, and field plate metal  148  contacts N-type regions  139  and heavy body region  140  in the termination region. Source metal  146 , field plate metal  148 , and gate runner metal  149  are separated by gaps created by the metal etch process. A backside drain metal layer  150  is formed using conventional techniques.  
         [0024]     In one embodiment, termination body region  106 A is left unbiased and thus electrically floats. This allows termination body region  106 A and field plate  148  to self-bias to a voltage greater than OV. This in turn prevents impact ionization and high fields around the last mesa trench  116  (i.e., the active trench which defines the left wall of termination body region  106 A). Since the last mesa region on the die (i.e., termination body region  106 A) is floating and there is no current flow present during operation, the potential for latch-up which is typically caused by bipolar transistor formed by N-type eptiaxial layer  104 , P-type termination body region  106 A, and N-type source region  137  is eliminated. In an alternate embodiment, termination body region  106 A is electrically biased to the same potential as the source regions.  
         [0025]     While  FIGS. 1A-1K  show a process sequence for forming a particular trench termination structure together with a self-aligned MOSFET cell array, modifying this process sequence to form other trench termination structures would be obvious to one skilled in this art in view of this disclosure. For example, the process sequence of  FIGS. 1A-1K  could be modified to form any one of the trench termination structures disclosed in the above-referenced patent application Ser. No. 11/317,653, titled “Trench Field Plate Termination For Power Devices,” filed on Dec. 22, 2005.  
         [0026]      FIG. 2  is a simplified cross section view illustrating a trench gate runner structure formed using the process sequence of  FIGS. 1A-1K . Gate runner trench  117  is formed at the same time active gate trenches  116  and termination trench  120  are formed (i.e., using the process steps corresponding to  FIG. 1B ). In one embodiment, the width of gate runner trench  117  is wider than active gate trenches  116  as dictated by photolithography limitations and the required size of contact opening  152  over gate runner  131 . Gate runner trench  117  is lined with the gate dielectric layer  126  during the same process steps carried out to line active trenches  116  with gate dielectric layer  126  (i.e., the process steps corresponding to  FIG. 1E ). In an alternative embodiment, gate runner trench  117  is lined with the thicker dielectric layer  124  during the same process steps carried out to line termination trench  120  with dielectric layer  124  (i.e., the process steps corresponding to  FIGS. 1C and 1D ). The thicker dielectric in the gate runner trench advantageously minimizes the gate-drain capacitance. Similarly, the recessed gate runner electrode  131  is formed during the same process steps carried out for forming gate electrodes  130  in the active trenches (i.e., the process steps corresponding to  FIGS. 1F and 1G ).  
         [0027]     Dielectric layer  150  and contact openings  152  are formed during the same process steps carried out for forming dielectric layer  127  and contact openings  132  (i.e., the process steps corresponding to  FIG. 1H ). Gate metal  149  electrically contacting gate runner electrode  131  through contact opening  152  is formed during the same metal deposition, photolithograpy, and metal etch process sequence carried out for forming source metal  146  and field plate metal  148  (i.e., the process steps corresponding to  FIG. 1K ). The remaining layers of the trenched gate runner structure in  FIG. 2  are similarly formed during corresponding process steps in  FIGS. 1H-1J . Gate runner trench  117  may extend along the periphery, along a central area of the die, and/or other areas of the die as needed. In a specific embodiment, gate runner trenches extend along a center of the die and additional gate runner trenches extend along sides of the die connect gate electrodes located within the active area of the device. In another embodiment, the cells in the active region are stripe shaped extending along a first direction, and a gate runner trench extends along a direction perpendicular to and is contiguous with the active gate trenches.  
         [0028]     In accordance with the invention, termination structures that are usually patterned separately from the active region are formed at the same time corresponding structures are formed in the array region, thus reducing the mask count and number of process steps. For example, in conventional implementations, separate ion implantation and masking steps are carried out to form the P-type well region in the termination area and the P-type well region in the active area of the die. By using a blanket implant (i.e., using no mask), the P-type well region in the termination area and the P-type well region in the active area of the die are formed simultaneously. Thus, both the number of process steps and the number of masks used are reduced. Similarly, by utilizing a trench embedded gate runner, the number of required masks is reduced. The same process steps can be used to simultaneously form: (i) the termination trench, (ii) the gate runner trenches, and (iii) the active gate trenches, thus reducing the number of fabrication steps and masking steps. Additionally, by embedding the gate runner in a trench (as opposed to the conventional planar gate runners) minimize silicon consumption. These advantages are achieved together with a trench-gate FET structure with self-aligned source and heavy body regions. In all, a highly compact, low cost trench gate FET with improved performance is achieved.  
         [0029]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the claims.