Abstract:
A host voltage monitor is provided for a transceiver. The host voltage monitor may include a comparator, which compares two voltages, one representative of the present host voltage, and the other representative of a threshold voltage level for the host voltage, that may indicate an imminent loss of power. Once the threshold is crossed, an alarm and/or a fault warning data packet may be automatically generated before the power fault causes the transceiver to shut down.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present invention claims priority from U.S. Patent Application No. 61/933,480 filed Jan. 30, 2014, which is incorporated herein by reference. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates to telecommunication equipment and methods, and in particular to power fault detection in transceivers. 
       BACKGROUND 
       [0003]    Transceivers are used in optical communications networks to retransmit optical signals or to convert signals between optical and electrical domains. Recently, digital data processors have been added to transceivers, enabling new functions beyond mere signal retransmission and conversion. Nowadays, transceivers may perform packet processing, filtering, as well as participate in network testing as inline probes. 
         [0004]    New functionalities of transceivers bring in additional requirements, such as an ability of a “graceful” shutdown in case of a power loss. This graceful shutdown may include a message that an electrical power loss is imminent, which is termed in the field as a “dying gasp” functionality. 
         [0005]    A transceiver is typically hosted by network communications device, such as a router, a switch, a gateway, a circuit pack, customer premises equipment (CPE) box, or some other type of networking equipment. Presently, a transceiver relies on its hosts to detect and report power interruptions. The transceiver remains powered by the host via a buffer capacitor having enough charge stored to enable a message to be sent out. The power loss detection circuitry, the message generation circuitry, as well as the buffer capacitor are all provided by the host. 
         [0006]    It may be advantageous to provide a shutdown warning capability in a transceiver device itself Unfortunately, transceivers rarely have enough room on their printed circuit boards (PCBs) to accommodate large and bulky elements, such as buffer capacitors for storing enough electrical charge for a graceful shutdown and/or for sending out a “dying gasp” message. 
       SUMMARY 
       [0007]    In one aspect of the present disclosure, a host voltage monitor may be provided in a transceiver. This host voltage monitor may not require a local energy storage component such as a capacitor. Instead, the host voltage monitor may include a comparator, which compares two voltages, one representative of the present host voltage, and the other representative of a threshold voltage level for the host voltage, that may indicate an imminent loss of power. Once the threshold is crossed, an alarm and/or a fault warning data packet may be automatically generated before the power loss causes the transceiver to shut down. 
         [0008]    In accordance with an aspect of the disclosure, there is provided a transceiver for being hosted by a network communications device, the transceiver comprising:
       a transmitter for transmitting first data packets, a receiver for receiving second data packets, and a packet processor coupled to the transmitter and the receiver for processing the first and second data packets;   a connector coupled to the packet processor for transmitting and receiving the first and second data packets in electrical domain to and from a host device, and for providing a host voltage from the host device; and   a host voltage monitor for providing a fault trigger signal for the packet processor to generate a fault data packet when the host voltage drops becomes equal to or below a predetermined threshold voltage;   wherein the host voltage monitor comprises a comparator for comparing a reference voltage, corresponding to the threshold voltage, to a variable voltage based on the host voltage, and for providing the fault trigger signal to the packet processor when the variable voltage becomes equal to or drops below the reference voltage.       
 
         [0013]    The packet processor may include a dedicated fault packet generator responsive to the fault trigger signal, for generating the fault packet upon receiving the fault trigger signal. The host voltage monitor may include a DC-DC voltage converter for generating the reference voltage from the host voltage. Such a DC-DC voltage converter may provide the reference voltage at a constant level, even when the host voltage drops during an imminent power loss. 
         [0014]    In one exemplary embodiment, the host voltage monitor may include a DC-DC voltage converter for generating a substantially constant operating voltage from the host voltage, e.g. for powering the comparator by the operating voltage. The DC-DC voltage converter may operate so that the operating voltage is below the host voltage. The host voltage monitor may further include a reference generator coupled to the DC-DC voltage converter for generating the reference voltage from the operating voltage. 
         [0015]    In accordance with the disclosure, there is further provided a method of reporting a host voltage loss by a transceiver hosted by a network communications device, the method comprising:
       (a) generating a variable voltage based on the host voltage;   (b) generating a reference voltage corresponding to a threshold voltage, wherein a reduction of the host voltage to a level equal to or below the threshold voltage indicates the host power failure;   (c) comparing the variable voltage to the reference voltage;   (d) upon determining in step (c) that the variable voltage is at a level equal to or below the reference voltage, generating a fault data packet before the host voltage becomes equal to or falls below the reference voltage.       
 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    Exemplary embodiments will now be described in conjunction with the drawings, in which: 
           [0021]      FIG. 1  illustrates a transceiver according to the present disclosure; 
           [0022]      FIG. 2A  illustrates an electric schematic of a host voltage monitor embodiment for the transceiver of  FIG. 1 ; 
           [0023]      FIG. 2B  illustrates electrical time traces of various voltages in the host voltage monitor embodiment of  FIG. 2A ; 
           [0024]      FIG. 3A  illustrates an electric schematic of a host voltage monitor embodiment for the transceiver of  FIG. 1 ; 
           [0025]      FIG. 3B  illustrates electrical time traces of various voltages in the host voltage monitor embodiment of  FIG. 3A ; 
           [0026]      FIG. 4  illustrates a block diagram of an embodiment of the transceiver of  FIG. 1 ; and 
           [0027]      FIG. 5  illustrates a flow chart of a method for the transceiver of  FIG. 1  or  FIG. 4  to monitor and report a voltage supplied by a host. 
       
    
    
     DETAILED DESCRIPTION 
       [0028]    While the present teachings are described in conjunction with various embodiments and examples, it is not intended that the present teachings be limited to such embodiments. On the contrary, the present teachings encompass various alternatives and equivalents, as will be appreciated by those of skill in the art. 
         [0029]    Referring to  FIG. 1 , a transceiver  10  may be provided as described below. For example, the transceiver  10  may include a transmitter  11  for transmitting first data packets  11 A, a receiver  12  for receiving second data packets  12 A, and a packet processor  13  coupled to the transmitter  11  and the receiver  12  for processing the first  11 A and second  12 A data packets, e.g. preparing the first data packets  11 A for transmission, and processing the received second data packets  12 A. A connector  14  may be coupled to the packet processor  13  via a bus  14 A for transmitting and receiving the first  11 A and second  12 A data packets in electrical domain, and for providing a host voltage V H  from a host device  15  for powering the elements of the transceiver  10 , e.g. the transmitter  11 , the receiver  12  and the packet processor  13 . A host voltage monitor  16  may be provided for generating a fault trigger signal  16 A for the packet processor  13  to generate a fault data packet  16 B when the host voltage V H  becomes equal to or drops below a predetermined threshold voltage V TH . The host voltage monitor  16  may include a comparator  17  for comparing a reference voltage V REF , corresponding to, but ideally less than, the threshold voltage V TH , to a variable voltage V VAR  based on, but ideally less than, the host voltage V H , and for providing the fault trigger signal  16 A to the packet processor  13  when the variable voltage V VAR  becomes equal to or drops below the reference voltage V REF . 
         [0030]    Referring to  FIG. 2A  with further reference to  FIG. 1 , a host voltage monitor  26  is a variant of the host voltage monitor  16  of  FIG. 1 . The host voltage monitor  26  ( FIG. 2A ) may include a comparator  27  and a DC-DC voltage converter  20  for generating the reference voltage V REF  from the host voltage V H . The reference voltage V REF  may be generated at a substantially constant level, which is maintained even though the host voltage V H  may vary. By way of a non-limiting example, the reference voltage V REF  may be generated at a level of 0.2 V H0  to 0.5 V H0  , where V H0  is the nominal value of the host voltage V H  at normal operating conditions. The comparator  27  is a variant of the comparator  17  of  FIG. 1 . The host voltage monitor  26  ( FIG. 2A ) may further include a host voltage divider  21  for generating the variable voltage V VAR  as a pre-determined portion p of the host voltage V H : V VAR =p•V H . By way of a non-limiting example, the portion p may be selected between 0.2 and 0.6. Referring now to  FIG. 2B  with further reference to  FIGS. 1 and 2A , the operation of the transceiver  10  ( FIG. 1 ) having the host voltage monitor  26  ( FIG. 2A ) may be illustrated as follows. During normal operation of the transceiver  10 , the host voltage V H  is supplied to the transceiver  10  via the connector  14 . The DC-DC voltage converter  20  may convert the host voltage V H  down to the reference voltage V REF . While the host voltage V H  may vary, the DC-DC voltage converter  20  keeps the reference voltage V REF  at a substantially constant value, for as long as V H  remains (approximately) larger than V REF . The host voltage divider  21  may generate the variable voltage V VAR  as a predetermined portion of the host voltage V H . 
         [0031]    When the power is lost in the host device  15  ( FIG. 1 ), the host voltage V H  begins to drop as indicated by a thin solid curve  22  in  FIG. 2B . The variable voltage V VAR , being a constant proportion of the host voltage V H , begins to drop as well, as indicated by a thin dashed line  23 . Yet, the reference voltage V REF  stays constant, as indicated by a thick solid horizontal line  24 . When the variable voltage V VAR  decreases to a level or below the reference voltage V REF , the comparator  27  generates the fault trigger signal  16 A. This moment is indicated at  25 . The reference voltage V REF  and a ratio of the variable voltage V VAR  to the host voltage V H  are selected so that the host voltage V H  becomes lower than the threshold voltage V TH  at approximately the same moment of time  25 . 
         [0032]    Comparing the reference voltage V REF  to the variable voltage V VAR , instead of directly comparing the host voltage V H  to the threshold voltage V TH , has a benefit of the host voltage monitor  26  being able to remain operational (e.g. being powered by the temporarily stabilized reference voltage V REF ) for as long as the host voltage V H  is still larger than the reference voltage V REF . This may provide enough time for a graceful shutdown of the transceiver  10 , including generation of the fault data packet  16 B. 
         [0033]    Turning to  FIG. 3A  with further reference to  FIGS. 1 and 2A , a host voltage monitor  36  is a variant of the host voltage monitor  16  of  FIG. 1 . The host voltage monitor  36  ( FIG. 3A ) may include a comparator  37  and a DC-DC voltage converter  30  for generating a substantially constant operating voltage V OP  from the host voltage V H , e.g. for powering the comparator  37  and/or the transmitter  11  and/or the receiver  12 , etc. by the operating voltage V OP . The comparator  27  is a variant of the comparator  17  of  FIG. 1 . Similarly to the host voltage monitor  26  of  FIG. 2A , the host voltage monitor  36  of  FIG. 3A  may include the host voltage divider  21  coupled to the comparator  37  for generating the variable voltage V VAR  as the predefined portion of the host voltage V H . The host voltage monitor  36  may further include a reference generator, e.g. a reference voltage divider  31 , coupled to the DC-DC voltage converter  30  for generating the reference voltage V REF  from the operating voltage V OP . A ratio of the reference voltage V REF  to the operating voltage V OP  may be selected between 0.4 and 0.6. 
         [0034]    Referring now to  FIG. 3B  with further reference to  FIGS. 1 and 3A , the operation of the transceiver  10  ( FIG. 1 ) having the host voltage monitor  36  ( FIG. 3A ) may be illustrated as follows. During normal operation of the transceiver  10 , the host voltage V H  is supplied to the transceiver  10  via the connector  14 . The DC-DC voltage converter  30  may convert the host voltage V H  down to the substantially constant operating voltage V OP . While the host voltage V H  may vary, the DC-DC voltage converter  30  keeps the operating voltage V OP  at a substantially constant value, for as long as V H  remains larger than the operating voltage V OP . The host voltage divider  21  may generate the variable voltage V VAR  as a pre-determined portion of the host voltage V H . The reference voltage divider  31  may generate the reference voltage V REF  as a pre-determined portion of the operating voltage V OP . The reference voltage V REF  is stable because the operating voltage V OP  is already stabilized. 
         [0035]    When a power loss event begins to occur in the host device  15 , the host voltage V H  begins to drop as indicated by a thin solid curve  32  in  FIG. 3B . The variable voltage V VAR , being a constant proportion of the decreasing host voltage V H , begins to drop as well as indicated by a thin dashed line  33 . Yet, the operating voltage V OP  stays constant as indicated by a thick dotted horizontal line  34 A. The reference voltage V REF  also stays constant as indicated by a thick solid horizontal line  34 B. When the variable voltage V VAR  decreases to a level or below the reference voltage V REF , the comparator  37  generates the fault trigger signal  16 A. The moment when it happens is indicated by a dashed line  35 . The ratios of the reference voltage V REF  to the operating voltage V OP ; and the variable voltage V VAR  to the host voltage V H  are selected so that the host voltage V H  becomes lower than the threshold voltage V TH  at the same moment of time indicated at  35 . 
         [0036]    A specific, non-limiting example of voltages involved may be given as follows. The host voltage V H =3.3V may be provided by the host device  15  via the connector  14  The DC-DC voltage converter  30  provides the operational voltage V OP =2.5V even when the host voltage V H  drops to 2.6V. The comparator  37  may be powered by the operational voltage V OP =2.5V. The fault trigger signal  16 A will be triggered when the host voltage V H  drops below a predetermined threshold, e.g. 3.3V-10% to 15%, e.g. 3.3V-12.5% threshold. This percentage drop is fixed, but may be adjusted if needed. 3.3V-5% is the specified minimum operating voltage for small form pluggable (SFP) transceivers. 
         [0037]    During normal use, the comparator  37  compares the reference voltage V REF , e.g. 1.2V, from the reference voltage divider  31 , to the variable voltage V VAR  provided by the host voltage divider  21 . The host voltage divider  21  may be set to output the variable voltage V VAR =1.37V when the host voltage V H =3.3V at the dividing ratio of 1.37/3.3≈0.415. At this dividing ratio, the variable voltage V VAR =1.2V when the host voltage V H =2.89V. As the host voltage V H  drops from the main input voltage of 3.3V to the predetermined threshold voltage of 2.89V, the output of the host voltage divider is reduced correspondingly until it reaches the reference voltage V REF =1.2 V, causing the fault trigger signal  16 A to be generated. While the host voltage V H  keeps dropping from 2.89V to about 2.6V, the transceiver  10  still remains operational, enabling the packet processor  13  to generate the fault data packet  16 B. 
         [0038]    The above example illustrates that comparing the reference voltage V REF  to the variable voltage V VAR , instead of comparing the host voltage V H  to the threshold voltage V TH , enables the host voltage monitor  16  to remain operational for as long as the host voltage V H  is still larger than the operating voltage V OP , by a small value e.g. 0.1V. This operational time interval may be sufficient for a graceful shutdown of the transceiver  10 , including generation of the fault data packet  16 B. Furthermore, the operating voltage V OP  generated by the DC-DC voltage converter  30  may be conveniently used for powering the comparator  37  ( FIG. 3A ) and/or the transmitter  11 , the receiver  12 , the packet processor  13 , etc. ( FIG. 1 ). As the above example illustrates, the operating voltage V OP  may remain at a substantially constant level as the host voltage V H  drops, thereby ensuring a stable operation of electronic components powered by the operating voltage V OP  during the graceful shutdown procedure. 
         [0039]    Referring to  FIG. 4  with further reference to  FIGS. 1 and 3A , a transceiver  40  is a variant of the transceiver  10  of  FIG. 1 . The transceiver  40  ( FIG. 4 ) may include optical  41 A and electrical  41 B transmitter portions, and optical  42 A and electrical  42 B receiver portions each coupled to the packet processor  13 . The electrical portions of the transmitter  41 B and the receiver  42 B may be coupled to the connector  14  for transmitting and receiving the first  11 A and second  12 A data packets in the electrical domain. 
         [0040]    In the embodiment shown, the packet processor  13  includes a fault packet generator (“dying gasp packet injector”)  43  responsive to the fault trigger signal  16 A by injecting the fault data packet  16 B into outgoing traffic e.g. using a left add module  45 A, thereby generating the fault data packet  16 B upon receiving the fault trigger signal  16 A. Similarly, the fault packet generator  43  may inject the fault data packet  16 B into incoming traffic e.g. using a right add module  45 B. An optical interface  46 A including the optical transmitter portion  41 A and the optical receiver portion  42 A; an electrical interface  46 B including the electrical transmitter portion  41 B and the electrical receiver portion  42 B; and/or the packet processor  13  may be powered via a host voltage V H  bus  47 , or via an operating voltage V OP  bus  48 . The packet processor  13  may include a digital signal processor (DSP) and/or a field programmable gate array (FPGA), not shown. The DSP or FPGA are preferably fast enough to generate the fault data packet  16 B within 25 microseconds of receiving the fault trigger signal  16 A from the comparator  37 . In one embodiment, the transmitter portions  41 A,  41 B; the receiver portions  42 A,  42 B; the packet processor  13 ; the connector  14 ; and the host voltage monitor  16  of the transceiver  40  of  FIG. 4  are disposed within, or supported by, a SFP package, not shown. The transceiver  10  of  FIG. 1  may also be implemented in an SFP package, not shown. 
         [0041]    Turning now to  FIG. 5  with further reference to  FIGS. 1 ,  2 A,  2 B,  3 A,  3 B, and  FIG. 4 , a method  50  ( FIG. 5 ) for the transceiver  10  ( FIG. 1 ) or  40  ( FIG. 40 ) to report a host voltage loss includes a step  51  of generating the variable voltage V VAR  based on the host voltage V H , for example, as a pre-defined portion of the host voltage V H . In a next step  52 , the reference voltage V REF  is generated. As explained above, the reference voltage V REF  corresponds to the threshold voltage V TH , a reduction of the host voltage below which indicates the host device  15  power failure. 
         [0042]    In a next step  53 , the variable voltage V VAR  is compared to the reference voltage V REF . Upon determining that the variable voltage V VAR  is equal to or below the reference voltage V REF , the fault data packet  16 B is generated in a step  54 . The fault data packet  16 B generation has been explained above with reference to  FIG. 4 . The method  50  may allow a quick generation of the fault data packet, for example during a time interval of 25 microseconds or less. 
         [0043]    The fault data packet  16 B may be generated before the host voltage V H  is at a level equal to or below the reference voltage V REF  ( FIG. 2B ), which may be generated at a substantially constant level from the host voltage V H . For embodiments where the reference voltage V REF  is obtained from the substantially constant operating voltage V OP  (e.g.  FIG. 3B ), the fault data packet  16 B may be generated before the host voltage V H  falls to a level of, or below the operating voltage V OP . The comparator  27  ( FIG. 2A ) or  37  ( FIG. 3A ) may be used to compare the variable voltage V VAR  to the reference voltage V REF . The comparator  37  of  FIG. 3A  may be powered with the operating voltage V OP . The operating voltage V OP  may also be used to power the transceiver  10  of  FIGS. 1 and 40  of  FIG. 4 . 
         [0044]    The hardware used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some steps or methods may be performed by circuitry that is specific to a given function. 
         [0045]    The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments and modifications, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.