Abstract:
An adaptive equalizer estimates a channel impulse response h in a channel impulse response estimator and outputs a result to a channel impulse response convertor. The channel impulse response convertor removes interference components from the channel impulse response h, outputs a channel impulse response h&#39; to an equalizer. The equalizer sets up, based on the channel impulse response vector h&#39;, internal parameters, and equalizes, based on the internal parameters, reception signals. By configuring as above, distortion by intersymbol interference and a deterioration of reception performance by co-channel interference waves can be prevented.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to an adaptive equalizer, and more specifically, an adaptive equalizer preventing deterioration of reception performance caused by intersymbol interference distortion and co-channel interference waves. 
     Conventionally, for example, when intersymbol interference and co-channel interference waves exist, a system to improve reception performance using space diversity and an equalizer is known, as disclosed in a paper titled &#34;Co-channel Interference Performance of Diversity Equalization in Mobile Radio&#34; by Hitoshi YOSHINO and Hiroshi SUZUKI, in 1992, The Autumn Meeting of The Electronic Data Academic Society on B-260. 
     As shown in FIG. 5, this system receives a plurality of signals from a plurality of antennas 500 and 510, equalizes and synthesizes these received signals in an equalizer 520, then performs demodulation. By using this system, reception performance despite co-channel interference waves is improved. 
     The improvement of reception performance despite co-channel interference waves, however, is obtained by space diversity. Therefore, in this case, there is a problem that the configuration of the receiver becomes complicated by the diversity. 
     On the other hand, in case of equalizing signals while estimating a channel impulse response, when a co-channel interference wave exists a channel impulse response estimator locks to the co-channel interference wave and estimates a different channel impulse response from the actual channel impulse response. As a result, the system equalizes reception signals with the wrong channel impulse response. Therefore, the reception performance of the system is greatly deteriorated. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an adaptive equalizer solving the above problems without complicating the configuration thereof. 
     Another object of the present invention is to provided an adaptive equalizer preventing distortion by intersymbol interference and deterioration of reception performance by co-channel interference waves, not using a diversity system. 
     The above objects are achieved by an adaptive equalizer comprising: 
     a channel impulse response vector calculator means for estimating a channel impulse response h from reception signals and calculating a channel impulse response vector h&#39; by removing interference components from the estimated path impulse response h; and 
     an equalizer means for receiving the reception signals and the channel impulse response vector h&#39;, setting an internal parameter using the channel impulse response vector h&#39; and then equalizing the reception signals based on the internal parameter. It is desirable that the adaptive equalizer comprises a maximum likelihood sequence estimator. 
     Moreover, it is desirable that the channel impulse response vector calculator means comprises means receiving the reception signals, equalizating the reception signals in the equalizer means, and estimating the channel impulse response h using the equalization result and the reception signals. 
     Further, it is desirable that the channel impulse response vector calculator means comprises: 
     a channel impulse response estimator means for receiving the reception signals and the equalization result and estimating a channel impulse response vector h; and 
     a channel impulse response convertor means for receiving the channel impulse response h and converting the channel impulse response h to the channel impulse response h&#39; from which the interference components are removed. 
     Moreover, it is desirable that the channel impulse response estimator means comprises a transversal filter. 
     Additionally, it is desirable that the channel impulse response estimator means comprises: 
     a channel impulse response estimator circuit receiving the reception signals and the equalization result and estimating the channel impulse response h; 
     a training signal detector means for detecting training signals from the input reception signals; 
     an equalization result output means for outputting the equalization result corresponding to the training signals; and 
     a switching means for receiving the equalization result from the equalization result output means and the equalization result of the reception signals and outputting an equalization result from the equalization result output means to the channel impulse response estimator circuit when training signals have been detected based on a detection signal from the training signal detector means, and outputting an equalization result of the reception signals to the channel impulse response estimator circuit when training signals have not been detected. 
     Moreover, it is desirable that the channel impulse response convertor means comprises: 
     a plurality of absolute value operation means for receiving each component of the channel impulse response h, and calculating and outputting an absolute value of each component; 
     a first maximum value detector means for detecting and outputting a first maximum value among absolute values output from the plurality of absolute value operation means and specifying an absolute value operation means that has output the first maximum value; 
     a gate means for inputting absolute values output from the plurality of absolute value operation means and passing absolute values except for the first maximum value based on a specification signal from the first maximum value detector means; 
     a second maximum value detector means for receiving the absolute values that have passed the gate means, detecting a second maximum value among the absolute values that have passed the gate means and outputting the second maximum value; 
     a divider means for receiving the first maximum value and the second maximum value and calculating a ratio of the first maximum value and the second maximum value; 
     a weight controller means for receiving the ratio calculated in the divider means and the specification signal from output from the first maximum value detector means and outputting a weight coefficient corresponding to each component of the channel impulse response h; and 
     a plurality of multiplier means for multiplying the weight coefficient that has been output from the weight controller means and the each component of the channel impulse response h. 
     Moreover, it is desirable that the weight controller means comprises: 
     a weight coefficient memory means for storing a plurality of weight coefficients; 
     a selector means for outputting only one weight coefficient among the plurality of weight coefficients; and 
     a controller means for receiving the specification signal from the first maximum value detector means and said ratio output from the divider section and outputting a control signal indicating a weight coefficient to be output to the selector. 
     Furthermore, it is desirable that the weight controller means comprises: 
     a threshold value memory means for storing a threshold value; 
     a weight coefficient memory section storing two weight coefficients; 
     a selector means for outputting a weight coefficient stored in the weight coefficient memory means; 
     a comparison section comparing the threshold value and the ratio output from the divider means and outputting a comparison; and 
     a controller means for receiving the comparison result and the specification signal from the first maximum value detector means and outputting a control signal indicating a weight coefficient to be output to the selector means. 
     By configuring as above, when transferring data via a communication path where co-channel interference waves exist and a distortion by intersymbol interference occurs, the problem that an equalizer is improperly-locked to co-channel interference waves when levels of reception signals decreased can be prevented and reception performance thereof can be improved without using a diversity system. 
     Also, because the present invention does not use a diversity system, the configuration of the receiver is simple. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing an embodiment of the present invention. 
     FIG. 2 is a block diagram showing a configuration of the channel impulse response convertor section of the present invention. 
     FIG. 3 is a block diagram of a weight controller of the present invention. 
     FIG. 4 is a block diagram of a weight controller of another embodiment of the present invention. 
     FIG. 5 is the block diagram showing a prior art. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The embodiments of the present invention are now explained with reference to the drawings. 
     FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, 100 is an input terminal receiving reception signals, 110 is an equalizer, 120 is a channel impulse response calculator, 130 is an output terminal outputting equalized reception signals. 
     The equalizer 110 is configured as a maximum likelihood sequence estimator as shown, for example, in the paper &#34;Digital Communications&#34; Second Edition, 1989 by J. G. Proakis and in a U.S. Pat. No. 5,127,025 &#34;Space Diversity TDMA Receiver&#34; by Mr. OKANOUE, one of the inventors of the present invention. In this configuration, reception signals input therein are equalized based on internal parameters. Moreover, each internal parameter is set by each component of a channel impulse response h&#39; described later on. 
     Based on reception signals and an equalization result of the reception signals, the channel impulse response calculator 120 calculates a channel impulse response h&#39; consisting of N components, from which all interference components are removed. 
     The channel impulse response calculator 120 is configured by a channel impulse response estimator 121, a training signal detector 122, a training sequence generating circuit 123, switching circuit 124 and a channel impulse response convertor 125. 
     The channel impulse response estimator 121 is configured as a transversal filter as shown, for example, in FIG. 6.7.5 in the paper &#34;Digital Communications&#34; Second Edition 1989, by J. G. Proakis. 
     Also, it is possible to estimate a channel impulse response h by an way to estimate based only on reception signals as shown, for example, in the paper &#34;A Study of Blind Viterbi Equalization Algorithm&#34; by FURUYA, USHIROKAWA, ISA and SATO, A-141 for The Spring Meeting of the Electronic data and communication Academic Society, 1991. However, to estimate more accurately the channel impulse response h, this invention is configured to use not only reception signals but also equalization results of reception signals and training signals. 
     Training signal detector 122 is configured to output a detection signal by detecting training signals in reception signals. 
     The training sequence generating circuit 123, which stores an equalization result of preset training signals, is configured to output the predetermind training sequence to the switching circuit 124. 
     The switching circuit 124 receives a predetermined training sequence from the training sequence generating circuit 123 and another equalization result of reception signals, and outputs one of them based on a detection signal from the training signal detector 122. 
     By the above configuration, the predetermined training sequence from the training sequence generating circuit 123 in the case that the training signal detector 122 has detected a training signal or an equalization result of reception signals in the case that the training signal detector 122 has not detected a training signal, is input to the channel impulse response estimator 121 by selection in switching circuit 124. 
     Based on these equalization results, the channel impulse response estimator 121 estimates a channel impulse response h consisting of N components, then outputs it to the channel impulse response convertor 125. 
     Next, a configuration of the channel impulse response convertor 125 is explained. 
     FIG. 2 is a block diagram showing a configuration of the channel impulse response convertor 125. In this figure, 200(1) to 200(N) are input terminals, 210(1) to 210(N) are absolute value operation circuits, 220 is a first maximum value detector, 230 is a second maximum value detector, 240 is a gate circuit, 250 is a divider, 260 is a weight controller, 270(1) to 270(N) are multipliers and 280(1) to 280(N) are output terminals. 
     The channel impulse response convertor 125 removes interference components from a received channel impulse response h and converts this to a channel impulse response h&#39;. 
     This channel impulse response convertor 125 is configured by input terminals 200(1) to 200(N), absolute value operation circuits 210(1) to 210(N), a first maximum value detector 220, a second maximum value detector 230, a gate circuit 240, a divider 250, a weight controller 260 and multipliers 270(1) to 270(N). 
     The input terminals 200(1) to 200(N) are configured to input each component of a channel impulse response h. 
     The absolute value operation circuits 210(1) to 210(N) are configured to receive each component of the channel impulse response h through the input terminals 200(1) to 200(N), calculate each absolute value of each component and output the results to the first maximum value detector 220 and the gate circuit 240. 
     The first maximum value detector 220 is configured to detect the first maximum value (h max ) among N absolute values received therein and output h max  to the divider 250. Moreover, it outputs an operation circuit specification signal specifying the absolute value operation section that has output the first maximum value to the gate circuit 240 and the weight controller 260. 
     The gate circuit 240 is configured to gate only one absolute value that is the first maximum value (h max ) among absolute values of respective components received therein based on the operation circuit specification signal, and output (N-1) absolute values to the second maximum value detector 230. 
     The second maximum value detector 230 is configured to detect the largest value that is the second maximum value (h NEXT ) among (N-1) absolute values received therein, and output it to the divider 250. 
     The divider 250 is configured to calculate a ratio of the first maximum value (h max ) and the second maximum value (h NEXT ) that is (h max  /h NEXT ), and output the result to the weight controller 260. 
     The weight controller 260 is configured to calculate each weight coefficient corresponding to each component of the channel impulse response h using the ratio (h max  /h NEXT ) and the operation circuit specification signal, and output the results to the multipliers 270(1) to 270(N). The configuration of the weight controller 260 is explained later in detail. 
     The multipliers 270(1) to 270(N) are configured to multiply each weight coefficient obtained in the weight controller 260 and each component of the channel impulse response h input through the input terminals 200(1) to 200(N), output the results to the output terminals 280(1) to 280(N). 
     By the channel impulse response convertor 125 thus configured, each component of the channel impulse response h is multiplied by each weight coefficient and interference components are removed, and thus a channel impulse response h&#39; is calculated. Then, the channel impulse response h&#39; is input to the equalizer 110. 
     The equalizer 110 sets up internal parameters based on the channel impulse response h&#39; input therein, and equalizes reception signals using the internal parameters. 
     Next, the configuration of the weight controller 260 mentioned above is explained in detail. 
     FIG. 3 is a block diagram of the weight controller 260. In this figure, 300 and 310 are input terminals, 320 is a weight coefficient memory, 330 is a controller, 340(1) to 340(N) are selectors and 350(1) to 350(N) are output terminals. 
     The input terminal 300 receives the ratio (h max  /h NEXT ) from the divider 250, and the input terminal 310 receives an operation circuit specification signal from the first maximum value detector 220. 
     The weight coefficient memory 320 is configured to store a plurality of weight coefficients and output these weight coefficients to the selectors 340(1) to 340(N). 
     The controller 330 is configured to estimate interference components based on the ratio (h max  /h NEXT ) received therein and output a control signal to the selectors 340(1) to 340(N) based on the operation circuit specification signal. 
     The selectors 340(1) to 340(N) are configured to output, based on the control signal from the controller 330, only one weight coefficient among weight coefficients received therein. 
     Next, the operation of the weight controller 260 thus configured is explained. 
     The controller 330 estimates magnitude of interference components based on the ratio (h max  /h NEXT ) received therein. That is, it decides that interference components are small when the ratio (h max  /h NEXT ) is large, or it decides that interference components are large when the ratio (h max  /h NEXT ) is small. On the other hand, it specifies, based on the operation circuit specification signal, a selector to be received the first maximum value (h max ). 
     Then, the controller outputs a control signal that indicates the selector to output the maximum value among the weight coefficients received from the weight controller 330. Additionally, it outputs a control signal that indicates each selector to output the smaller value among the weight coefficients received from the weight controller 330 when the ratio (h max  /h NEXT ) is large or the larger value among the weight coefficients input from the weight controller 330 when the ratio (h max  /h NEXT ) is small. 
     Thus, the respective weight coefficients corresponding to respective components of the channel impulse response h are output from the output terminals 350(1) to 350(N) and received to the multipliers 270(1) to 270(N). 
     Next, another embodiment of the weight controller 260 is explained. 
     FIG. 4 is a block diagram showing another embodiment of the weight controller 260. 
     In this figure, 400 and 410 are received terminals, 420 is a threshold value memory, 430 is a weight coefficient memory, 440 is a comparison circuit, 450 is a controller, 460(1) to 460(N) are selectors and 470(1) to 470(N) are output terminals. 
     The received terminal 400 receives the ratio (h max  /h NEXT ) from the divider 250, and the received terminal 410 receives the operation circuit specification signal from the first maximum value detector 220. 
     The threshold value memory 420 is configured to store a preset threshold value and output it to the comparison circuit 440. 
     The weight coefficient memory 430 is configured to store 1 and 0 as weight coefficients, output them to the selectors 460(1) to 460(N). 
     The comparison circuit 440 is configured to compare the threshold value and the ratio (h max  /h NEXT ) input from the divider 250 through the received terminal 400, and output the comparison result to the controller 450. 
     The controller 450 is configured to output, based on the comparison result and the operation circuit specification signal from the first maximum value detector 220, a control signal to the selectors 460(1) to 460(N). 
     Next, the operation of the weight controller 260 thus configured is explained. 
     Firstly, the controller 450 compares a ratio (h max  /h NEXT ) and a threshold value. 
     Then, it decides that interference components are small when the ratio (h max  /h NEXT ) is larger than the threshold value and outputs a control signal that indicates to output a weight coefficient not to convert each component of the channel impulse response h, that is 1, to the selectors 460(1) to 460(N). 
     On the other hand, it decides that interference components are large when the ratio (h max  /h NEXT ) input therein is smaller than the threshold value, and outputs, based on the operation circuit specification signal, a control signal that indicates to output the weight coefficient 1 to a selector corresponding to the specified absolute value operation and the weight coefficient 0 to the other selectors. 
     The selectors 460(1) to 460(N) received the control signal, and based on the control signal, outputs a weight coefficient corresponding to each component of the channel impulse response h to the output terminals 470(1) to 470(N). 
     Then, the weight coefficients output from the weight controller 260 configured as above are received to the multipliers 270(1) to 270(N).