Abstract:
An apparatus and method for detecting the period of a frequency signal having a period greater than a minimum period and within a period range. A clock frequency is generated such that when multiplied by the predetermined range the product is less than 2 N  and when multiplied by the minimum period of the product is less than 2 N+M . The resulting clock frequency is multiplied by the minimum period to generate an offset number. A counter is preset with the offset number in response to a detected edge transition of the frequency signal. The counter counts at the clock frequency from a complement of the offset number to a final count at a subsequent edge transition. The final count is contained within the first N bits and is related to the period of the frequency signal.

Description:
BACKGROUND OF THE INVENTION 
     The field of the invention relates to frequency or period to amplitude conversion for producing a signal having an amplitude corresponding to the output frequency of a sensor. 
     In many applications, such as automobile applications in particular, sensors provide a frequency signal having a frequency related to a measured parameter. For example, a speed sensor provides a signal having a frequency related to either the vehicular speed or engine speed, a manifold pressure sensor provides a signal having a frequency related to engine manifold pressure and so on. It is necessary to convert the frequency signal into an amplitude signal for signal processing. Examples of signal processing include onboard engine control and also diagnostic testing. The amplitude value may be either a voltage related to frequency or a digital word related to frequency. 
     In one approach to frequency to voltage conversion, as disclosed in Japanese patent application No. 0106276, one period of a frequency signal to be measured is integrated utilizing analog integrators and timing circuits In another approach as disclosed in U.S. Pat. No. 4,197,508 issued to Takaoka, the period of one frequency signal is applied to a frequency divider and a logic circuit to control the charging and discharging of capacitors. A voltage is thereby obtained proportional to the input signal. One disadvantage of these approaches is the inaccuracy caused by temperature dependent drift of the analog devices. 
     Still another approach is disclosed in U.S. Pat. No. 3,944,935 issued to Plant wherein generated pulses are counted for a time proportional to input signal frequency. The counter output is applied to a digital to analog converter for generating a dc voltage signal. A feedback signal is then derived from a comparison between the dc voltage signal and a reference signal such that, allegedly, the dc signal is directly proportional to the input signal frequency. 
     The inventor herein has recognized a disadvantage with all known prior approaches. More specifically, the frequency signal may vary across a frequency range. Prior known approaches are designed to convert any frequency signal from zero frequency to the maximum frequency of the frequency range. Accordingly, the sensitivity to noise of these prior approaches is limited. Further, in the case of digital processing, an excessive number of data bits are required with resulting disadvantages in transferring information and subsequent digital processing. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention described herein to provide period to amplitude conversion over the actual period range of a frequency signal. 
     The problems and disadvantages of prior approaches are overcome, and above object achieved by providing a circuit for determining a period of a frequency signal having a period both greater than a minimum period and within a period range. In one particular aspect of the invention, the circuit comprises: an edge detector for detecting edge transitions of the frequency signal in a predetermined direction; clock selection means for providing a clock signal; offset means for providing an offset signal by multiplying the minimum period by the clock signal; and counter means coupled to the edge detector and the clock selection means and being preset with a complement of the offset signal from the offset means for counting from the complement of the offset signal at the clock signal to provide a count related to the period of the frequency signal in response to the edge transitions. 
     In another aspect of the invention, the circuit comprises: detection means for detecting edge transitions of the frequency signal in a predetermined direction; counter means comprising a binary counter having N +M bits and clocked at a clock frequency; clock selection means for providing the clock frequency such that the clock frequency times the predetermined range is less than 2 N  and the clock frequency times the minimum period is less than 2 N+M  ; offset means for providing an offset number related to the clock signal times the minimum period and for providing a complement of the offset number having N+M bits; and the counter means being preset with the complement of the offset number in response to the edge transitions for counting from the complement of the offset number to zero and from zero to a final count at a subsequent edge transition, the final count being related to the period of the frequency signal and being contained within N bits. 
     By presetting the counter with a complement of the offset signal, the dynamic range of the counter is centered on the period range of the frequency signal. Accordingly, the dynamic range of the system is maximized. Stated another way, there is a maximum change in counter output for a given change in input frequency or period. An advantage is thereby obtained of having less sensitivity to noise than prior approaches. Another advantage is that the number of data bits required for a desired sensitivity is minimized thereby reducing the number of output data lines and also reducing subsequent data processing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The objects an advantages described herein will be more fully understood by reading the Description of the Preferred Embodiment with reference to the drawings wherein: 
     FIGS. 1A and 1B show an electrical schematic of an embodiment in which the invention is used to advantage; 
     FIG. 2 shows various steps performed by a portion of the embodiment shown in FIGS. 1A and 1B; 
     FIG. 3A-3E show various electrical waveforms associated with the embodiment shown in FIGS. 1A and 1B; and 
     FIG. 4 is an alternate embodiment of a portion of the embodiment shown in FIGS. 1A and 1B. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring first to FIGS. 1A and 1B, period to amplitude conversion circuit 10 is shown in this particular example providing voltage signal V p  proportional to the time period, and accordingly, frequency of signal P(f) from conventional manifold pressure sensor 12. Conversion circuit 10 is also shown in this example providing a digital word D p  (D 1  -D 10 ) proportional to the period of signal P(f) via multiplexer 16. Both D p  and V p  are suitable as inputs to either measuring circuits in diagnostic applications, or as inputs to a microcomputer such as microcomputer 18 for onboard engine control applications. In a typical engine control application,, microcomputer 18 computes the mass airflow inducted into an engine (not shown) in response to D f  and a signal related to engine speed (not shown) utilizing a conventional speed density algorithm. After calculating mass airflow, microcomputer 18 calculates a desired fuel charge signal (not shown) for maintaining engine operation at a desired air/fuel ratio. 
     Conversion circuit 10 is shown including optical isolator 22, available from Hewlett Packard as part no. 6N139, coupled to sensor 12 for providing signal P(f)&#39; directly related to, and electrically isolated from, signal P(f). One-shot circuit 24, available from RCA as part no. 74HC221, provides transfer pulse T p  each rising edge of signal P(f). Essentially identical one-shot circuit 26 provides preset pulse Pp following transfer pulse T p . 
     Counter 28 is shown in this example as a 12 bit counter formed by appropriately interconnecting three 4 bit counters 30, 32, and 34, each available from RCA as part no. 74HCT193. Each of the counters (30, 32, and 34) is shown having four outputs (Q1, Q2, Q3, and Q4), four preset inputs (Sl, S2, S3, S4), a preset enable input (E) coupled to preset pulse Pp, and a clock input coupled to clock signal C. Accordingly, counter 28 has 12 preset inputs for accepting a 112 bit preset upon actuation by preset pulse P p . Clock signal C is shown generated by conventional programmable oscillator 46 in response to high clock signal CH and low clock signal CL from programmer 36. Programmer 36 also provides the 12 bit preset input to counter 28 as described in greater detail herein below. 
     For the particular example shown herein, the ten least significant bits of counter 28 (D1, D2, D3, D4, D5, D6, D7, D8, D9, and D10) are shown coupled to 10 bit digital to analog (D/A) converter 38, available from Datel as part no. DAC-UP10B. These ten least significant bits are transferred to D/A converter 38 by transfer pulse T p . D/A converter 38 provide signal V p  having an amplitude directly related to the time period, and accordingly frequency, of signal P(f). For the example shown herein, signal V p  is filtered in conventional low pass filter 40 and buffered via operational amplifier circuitry 42 for noise filtering and electrical interface wit external circuitry. 
     In general terms, counter 28 is characterized herein as a N+M bit counter receiving a N+M bit preset and providing a N bit output to a N bit D/A converter. For the particular example described herein, N is shown as 10 bits and M is shown as 2 bits. 
     Programmer 36 is now described with reference to process steps 50, 54, 56, 58, 60, 62, and 64 shown in FIG. 2. It is noted that programmer 36 and the associated process steps may be performed by a microcomputer, such as microcomputer 18, or by discrete logic components such as integrated circuits or similar switching devices. For reasons described hereinafter, the period offset, which is the minimum period of frequency signal P(f), and period range of signal P(f) are first selected as illustrated instep 50. These values, which are the reciprocal of the minimum frequency and frequency range of signal P(f), are known from the characteristics of sensor12. For example, in applications wherein a capacitive manifold pressure sensor is represented by sensor 12, the time period of the frequency signal varies from 6.16 ms to 11.18 ms (89.42 Hz-162.25 Hz). Thus, in this illustrative example, the desired period range of signal P(f) would be 5.02 ms and the desired period offset 6.16 ms. 
     The product of the selected period range times a high clock frequency CH is then compared to 2 N  in process step 54. If this product is greater than 2 N , low clock signal CL is commanded in step 58 to prevent overflow of the first N bits of counter 28. In the event the product is less than 2 N , the product of the selected period offset times a high clock signal CH is compared to 2 N+M  in step 56. If this product is greater than 2 N+M , the low clock signal CL is commanded to prevent overflow of the N+M bits of counter 28. When this product is less than 2 N+M , high clock signal CH is commanded as shown in step 60. 
     A period offset number is then generated in step 62 which is a binary representation of the product of the selected period offset times the commanded clock signal. The complement of the period offset number is then read out of programmer 36, as represented by step 64, on output lines O 1 , O 2 , O 3 , O 4 , O 5 , O 6 , O 7 , O 8 , O 9 , O 10 , O 11 , and O 12  (FIGS. 1A and 1B) were O 1  represents the less significant bit (LSB) and O 12  represents the most significant bit (MSB). 
     Referring back to FIGS. 1A and 1B, and also referring to the associated electrical waveforms shown in FIGS. 3A-3E, the operation of conversion circuit 10 is now described. For illustrative purposes, three different time periods of frequency signal P(f) are shown in FIG. 3A. During the t 0  -t 2  time interval, frequency signal P(f) is sown at the maximum of the selected period range. During the t 2  -t 4  time interval, frequency signal P(f) is shown having an intermediate period which is less than the maximum period. During the t 4  -t 5  time interval, frequency signal P(f) is shown having the minimum period of the period range. Stated another way, signal P(f) is shown having shifted from its minimum frequency (t 0  -t 2  time period), to an intermediate frequency (t 2  -t 4  time period), to its maximum frequency (time period t 4  -t 5 ) Signal V p  from D/A converter 38 is shown in FIG. 3A as a voltage having an amplitude which directly tracks the frequency and time period of signal P(f). 
     After generation of the period offset number, as described previously herein with particular reference to FIG. 2, the complement of the N+M bit period offset number is preset into counter 28 by signal P p . More specifically, upon presentation of pulse P p  to the enable inputs of counters 30, 32, and 34, the four LSB&#39;s (O 1  -O 4 ) of the period offset number are preset via respective preset inputs S1-S4 of counter 30, the second four bits (0 are preset via respective preset inputs S 1  -S 4  of counter 32, and the four MSB are preset via respective preset inputs S 1  S 4  of counter 34. 
     Referring first to the maximum time period o signal P(f) shown in the t 0  -t 2  time interval, counter 28 counts up from the complement of the period offset number at clock frequency C. After counter 28 reaches its maximum count of all ones in each of its N+M bits, the next clock pulse rolls counter 28 over to all zeros as shown at time t 1  of FIG. 3D. Thus, at time t1 counter 28 has counted over a time period equal to the selected period offset. Between time t 1  and the end of the first period of frequency P(f), shown in FIG. 2 at time t 2 , counter 28 counts from all zeros at clock frequency C to a count correlated with the actual time period of frequency signal P(f). At the end of time t 2 , the count in counter 28 is directly related to the first period of frequency signal P(f) shown between t0 and t 2 . This count is loaded into D/A converter 38 with transfer pulse T p  following time t 2 . Thus, after time t 2 , voltage signal V.sub. p from D/A converter 38 is directly related to the period of frequency signal P(f) between t 1  and t 2 . 
     It is noted that in the above example wherein frequency signal P(f) is at its maximum period of the selected period range, the entire N bits of counter 28 is utilized to generate a binary representation of the time period, and accordingly frequency, of frequency signal P(f). These N bits are transferred to N bit D/A converter 38 on transfer pulse T p . Thus, the resolution has been optimized for converting the time period of frequency signal P(f) into a voltage signal V p . Further, the clock frequency has been optimized for selected period range as explained previously herein with particular reference to FIG. 2. 
     Reference is know made to the intermediate period of frequency signal (f) shown in the t 2  -t 4  time interval. As described above with reference to the t 0  -t 1  time interval, the complement of the period offset is preset into counter 28 on the first preset pulse P p  following time t 2 . The period offset is determined as previously described herein with reference to FIG. 2 and is the same period offset provided at time t 0 . Counter 28 again Counts at clock frequency C from the complement of the period offset to zero as shown at time t 3  in FIG. 3D. The time elapsed (t 2  -t 3 ) to count from the preset period offset to zero is equal to the selected period offset. Thereafter, counter 28 counts up at clock frequency C until the next rising edge of frequency signal P(f) at time t 4 . Thus the count in counter 28 at time t 4  is a binary representation of the period of frequency signal P(f) during the t 2  -t 4  time interval. The first N bits of counter 28 is then transferred to D/A converter 38 at the first transfer pulse T p  following t 4 . 
     As shown in FIG. 3D, the final count in counter 28 at t 4  is less then the final count at t 2  because signal P(f) is shown having a lower time period, and accordingly higher frequency, than during the t 0  -t 2  time interval. Similarly, the output of D/A converter 38, which is proportional to the period of signal P(f), is shown decreased at time t 4 . 
     During the t 4  t 5  time interval, signal P(f) is illustrated at near its minimum period within the selected period range. In this example, counter 28 is shown counting from the complement of the period offset number to a final count at time t 5 . At time t 5 , the count in counter 28 is near zero which correlates with a minimal period within the selected period range. 
     It is evident from the three illustrated examples presented with reference to FIGS. 3A-3E, that the dynamic range of counter 28 is centered on the selected period range of signal P(f). The number of data bits used (2 N ) for converting period to amplitude has therefore been minimized. The embodiment shown herein utilizes 2 N  bits whereas prior approaches required 2 N+M  bits. Accordingly, a greater signal to noise ratio is achieved than heretofore possible in translating the period of signal P(f) to an amplitude such as voltage signal V p . Further, with respect to prior approaches, the number of data lines to microcomputer 18 has been minimized and, therefore, any subsequent processing performed by microcomputer 18 has been minimized. 
     For the particular example presented herein, the period offset is shown being greater than the period range. In general, the period offset may be any number up to 2 M+N , and the period range may be any number up to 2 N . Thus, the period offset may be greater than the period range by a factor of 2 M . In the embodiment illustrated in FIGS. 1A and 1B, M was selected as 2 although other numbers may be used for applications requiring different period ranges and period offsets. 
     It is further noted with reference to FIGS. 1A and 1B, that a digital output D p  (D 1  -D 10 ) directly related to the period of frequency signal P(f) is also provided from counter 28. For the particular example shown in FIGS. 1A and 1B, digital output D p  is coupled to the data bus of microcomputer 18 through conventional multiplexer 16. Microcomputer 18 accepts the digital output from counter 28 for performing processing on signal P(f) such as, for example, conversion of manifold pressure into a measurement of mass airflow as previously described herein. A measurement of mass airflow is utilized in conventional automobile applications to regulate the air/fuel mixture inducted into an internal combustion engine. 
     It is also noted that conversion circuitry 10 may be incorporated directly in a microcomputer such as microcomputer 18. In such an application, the process steps performed by microcomputer 18 are shown in FIG. 4. More specifically, after generating the period offset number and clock frequency as previously described herein with reference to FIG. 2, both a transfer and preset command are generated with each rising edge of frequency signal P(f) as shown in process step 70. In response to the preset command, the complement of the period offset is preset into a counter or equivalent storage such as a RAM within microcomputer 18 as illustrated by step 72. During process step 74, the counter is clocked at either clock frequency CH or CL dependent upon the decision output from process steps 54, 56, 58, and 60 previously described with reference to FIG. 2. In process step 76, the count is then loaded into a D/A converter upon the transfer command. 
     This concludes the description of the preferred embodiment. The reading of it by those skilled in the art will being to mind many alterations and modifications without departing from the spirit and scope of the invention. For example, conversion circuit 10 may comprise discrete components as shown in FIGS. 1A and 1B or may be incorporated within a microcomputer performing the process steps illustrated in FIG. 4. Accordingly, it is intended that the scope of the invention be limited only by the following claims.