Abstract:
A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean Application No. 10-2009-0093599, filed on Sep. 30, 2009, which is incorporated by reference in its entirety as if set forth in full. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various aspects of the present disclosure generally relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus with a multi-chip package structure and a method for controlling the same. 
         [0004]    2. Related Art 
         [0005]    Semiconductor apparatuses are typically used in the form of multi-chip packages of at least two chips to improve integration efficiency. 
         [0006]    In the multi-chip packages, a plurality of chips are connected using signal transmission elements, such as metal lines, bonding wires and through-silicon vias, so that signal transmission can be implemented between the chips. 
         [0007]    In a semiconductor apparatus, it is important to implement power-up control, or control of determining whether a source voltage reaches a level capable of performing normal operations the semiconductor apparatus and thereby allowing various functions to be properly performed. 
         [0008]    In a semiconductor apparatus with a multichip package structure, various kinds of chips are electrically connected using signal transmission elements. When the operational characteristics of devices constituting the respective chips are different, abnormal current paths are likely to be formed so that current consumption increases, and the reliability of the entire multi-chip package can deteriorate due to erroneous operation of a certain chip among the plurality of chips. This occurrence can cause various problems. 
         [0009]    Therefore, the development of a technique for stable and efficient power-up control is demanded in the art. 
       SUMMARY OF THE INVENTION 
       [0010]    Accordingly, there is a need for an improved semiconductor apparatus which can prevent the formation of an abnormal current path and the operation of a chip in an abnormal power supply state and a method for controlling the same. 
         [0011]    An embodiment of the present invention may provide a semiconductor apparatus including a chip, the chip comprising: a power-up signal generation section configured to generate a power-up signal; a driver configured to drive and output the power-up signal; a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element. 
         [0012]    Another embodiment of the present invention may provide a semiconductor apparatus comprising: a master chip configured to generate a first power-up signal and inactivate the first power-up signal in response to a detection signal; a slave chip configured to generate a second power-up signal and generate the detection signal after detecting an inactivation of the second power-up signal. 
         [0013]    Another embodiment of the present invention may provide a semiconductor apparatus comprising: a master chip configured to generate a first power-up signal and inactivate the first power-up signal in response to a plurality of detection signals; a plurality of slave chips configured to respectively generate second power-up signals and respectively generate the plurality of detection signals by respectively detecting deactivations of the second power-up signals. 
         [0014]    Another embodiment of the present invention may provide a semiconductor apparatus comprising: a master chip configured to generate a first power-up signal and inactivate the first power-up signal in response to a detection signal; a slave chip configured to generate a second power-up signal and generate the detection signal after detecting an inactivation of the second power-up signal; a first through-silicon via connected between the master chip and the slave chip and supply the first power-up signal to the slave chip; and a second through-silicon via connected between the master chip and the slave chip and supply the detection signal to the master chip. 
         [0015]    Another embodiment of the present invention may provide a method for controlling a semiconductor apparatus comprising a master chip and a slave chip comprises determining whether a power-up abnormality occurs in the slave chip; and interrupting operations of the master chip and the slave chip when it is determined that the power-up abnormality occurs in the slave chip. 
         [0016]    Still another embodiment of the present invention may provide a method for controlling a semiconductor apparatus comprising a master chip and a plurality of slave chips, comprising: determining if one of power-up signals outputted from the plurality of slave chips is deactivated; and interrupting operations of the master chip and the plurality of slave chips when one of the power-up signals is deactivated. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0018]      FIG. 1  is a block diagram illustrating a semiconductor apparatus in accordance with an embodiment of the present disclosure; 
           [0019]      FIG. 2  is a block diagram illustrating a semiconductor apparatus in accordance with another embodiment of the present disclosure; and 
           [0020]      FIG. 3  is a block diagram illustrating a semiconductor apparatus in accordance with another embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Hereinafter, a semiconductor apparatus and a method for controlling the same according to the present disclosure will be described below with reference to the accompanying drawings through preferred embodiments. 
         [0022]      FIG. 1  is a block diagram illustrating a semiconductor apparatus in accordance with an embodiment of the present disclosure. Referring to  FIG. 1 , a semiconductor apparatus  1  according to the embodiment exemplifies a multi-chip package using three chips. One chip can comprise a master chip MAS and two remaining chips can comprise slave chips SLA 1  and SLA 2 . 
         [0023]    The master chip MAS comprises a power-up signal generation section  11 , drivers  12  and  13 , and a main circuit block  14 . 
         [0024]    The power-up signal generation section  11  is configured to output a power-up signal PWRUP_MAS that indicates whether the level of a source voltage VDD supplied from outside reaches a target level, or a voltage level appropriate for operations of the chips. 
         [0025]    The main circuit block  14  is configured to perform the functions of the master chip MAS, and perform normal operations when the power-up signal PWRUP_MAS is a high level. 
         [0026]    The drivers  12  and  13  are configured to transmit the power-up signal PWRUP_MAS to the main circuit block  14 . 
         [0027]    The slave chips SLA 1  and SLA 2  also comprise power-up signal generation sections  21  and  31 , drivers  22  and  23 , and  32  and  33 , and main circuit blocks  24  and  34 , respectively. 
         [0028]    Before constructing the multi-chip package by connecting the master chip MAS and the slave chips SLA 1  and SLA 2  together using a through-silicon via  10 , the master chip MAS and the slave chips SLA 1  and SLA 2  are separately tested. For this reason, each of the power-up signal generation sections  11  through  31  is necessary. 
         [0029]    Alternatively, a bonding wire or a metal line may be used in place of the through-silicon via  10 , depending upon the structure of a semiconductor apparatus. 
         [0030]    After the construction of the multi-chip package is completed, the master chip MAS takes over the management of power-up control. 
         [0031]    Accordingly, after all chip tests are completed separately, the output terminals of the drivers  12 ,  22  and  32  are connected together using the through-silicon via  10  such that the power-up signal PWRUP_MAS generated by the master chip MAS can be supplied commonly to the slave chips SLA 1  and SLA 2 . 
         [0032]      FIG. 2  is a block diagram illustrating a semiconductor apparatus  100  in accordance with another embodiment of the present disclosure. Referring to  FIG. 2 , the semiconductor apparatus  100  illustrates a multi-chip package comprising three chips. Here, the circuit components which will not be used after construction of the multi-chip package is completed are deactivated. One chip can comprise a master chip MAS and two remaining chips can comprise slave chips SLA 1  and SLA 2 . 
         [0033]    Since the master chip MAS takes over the management of power-up controls after the multi-chip package is manufactured, a power-up signal PWRUP_MAS generated by the master chip MAS should be transmitted to the slave chips SLA 1  and SLA 2 . Therefore, the master chip MAS and the slave chips SLA 1  and SLA 2  are connected using a through-silicon via  400  as a signal transmission element. The through-silicon via  400  is an example of the signal transmission element, and a metal line or a bonding wire may also be to used alternatively. 
         [0034]    The through-silicon via  400  is formed to commonly supply the power-up signal PWRUP_MAS generated by the master chip MAS to the slave chips SLA 1  and SLA 2 . 
         [0035]    The master chip MAS comprises a power-up signal generation section  110 , drivers  120  and  130 , and a main circuit block  140 . 
         [0036]    The power-up signal generation section  110  is configured to output a power-up signal PWRUP_MAS that indicates whether the level of a source voltage VDD supplied from outside reaches a target level, or a voltage level appropriate for operations of the chips. In this regard, it is assumed that the power-up signal generation section  110  outputs the power-up signal PWRUP_MAS at a high level when the level of the source voltage VDD is higher than the target level. 
         [0037]    The main circuit block  140  is a circuit element which is necessary to perform the functions of the master chip MAS, and performs normal operations when the power-up signal PWRUP_MAS is high. 
         [0038]    The drivers  120  and  130  are configured to transmit the power-up signal PWRUP_MAS to the main circuit block  140 . 
         [0039]    The slave chips SLA 1  and SLA 2  also comprise power-up signal generation sections  210  and  310 , drivers  220  and  230 , and  320  and  330 , and main circuit blocks  240  and  340 . 
         [0040]    The slave chip SLA 1  has fuses  250  and  260  between the power-up signal generation section  210  and the driver  220  and between the driver  220  and the main circuit block  240 , respectively. 
         [0041]    The slave chip SLA 2  has fuses  350  and  360  between the power-up signal generation section  310  and the driver  320  and between the driver  320  and the main circuit block  340 , respectively. 
         [0042]    Alternatively, metal options may also be used in place of the fuses  250 ,  260 ,  350  and  360 . 
         [0043]    In the semiconductor apparatus  100  according to the embodiment of the present disclosure, the slave chips SLA 1  and SLA 2  are separately tested when the fuses  250 ,  260 ,  350  and  360  are connected. 
         [0044]    The through-silicon via  400  is not formed at this time. 
         [0045]    After tests are completed, the fuses  250 ,  260 ,  350  and  360  are cut off and the through-silicon via  400  is formed, so that the multi-chip package is constructed. 
         [0046]    If the fuses  250 ,  260 ,  350  and  360  are cut, power-up signals PWRUP_SLA 1  and PWRUP_SLA 2  cannot be inputted to the drivers  220  and  320 . 
         [0047]    Therefore, during a normal operation after the construction of the multi-chip package, even when any one of the power-up signals PWRUP_MAS, PWRUP_SLA 1  and PWRUP_SLA 2  has a different level, it is possible to prevent the formation of an abnormal current path. 
         [0048]      FIG. 3  is a diagram of a semiconductor apparatus  101  in accordance with another embodiment of the present disclosure that exemplifies the case of constructing a multi-chip package using three chips in a manner such that operations of all chips are interrupted when a power-up abnormality is detected. Among the three chips, one chip can comprise a master chip MAS and two remaining chips can comprise slave chips SLA 1  and SLA 2 . At this time, the scheme as in the embodiment shown in  FIG. 2  can be adopted together such that circuit components which will not be used after construction of the multi-chip package is completed are deactivated. 
         [0049]    Since the master chip MAS should take over the management of power-up control after the manufacture of the multi-chip package is completed, a power-up signal PWRUP_MAS generated by the master chip MAS should be transmitted to the slave chips SLA 1  and SLA 2 . Therefore, the master chip MAS and the slave chips SLA 1  and SLA 2  are connected using a through-silicon via  400  as a signal transmission element. The through-silicon via  400  is merely an example of the signal transmission element, and a metal line or a bonding wire can be used alternatively. 
         [0050]    The through-silicon via  400  supplies the power-up signal PWRUP_MAS generated by the master chip MAS to the slave chips SLA 1  and SLA 2 . 
         [0051]    The master chip MAS comprises a power-up signal generation section  110 , drivers  120  and  130 , a main circuit block  140 , and a control section  150 . 
         [0052]    The power-up signal generation section  110  is configured to output a power-up signal PWRUP_MAS that indicates whether the level of a source voltage VDD supplied from outside reaches a target level, or a voltage level appropriate for operations of the chips. In this regard, it is assumed that the power-up signal generation section  110  outputs the power-up signal PWRUP_MAS at a high level when the level of the source voltage VDD is higher than the target level. 
         [0053]    The main circuit block  140  is configured to perform the functions of the master chip MAS, and performs normal operations when the power-up signal PWRUP_MAS is a high level. 
         [0054]    The drivers  120  and  130  are configured to transmit the power-up signal PWRUP_MAS to the main circuit block  140 . 
         [0055]    The control section  150  is configured to transit the power-up signal PWRUP_MAS to a deactivation level when the detection signal PWRERR_DET is activated. The control section  150  comprises a transistor M 1 . The source of the transistor M 1  is grounded, the gate receives the detection signal PWRERR_DET, and the drain is connected to node A between the power-up signal generation section  110  and the driver  120 . 
         [0056]    The slave chip SLA 1  comprises a power-up signal generation section  210 , drivers  220  and  230 , a main circuit block  240 , fuses  250  and  260 , and a detection section  270 . 
         [0057]    The power-up signal generation section  210 , the drivers  220  and  230 , the main circuit block  240 , and the fuses  250  and  260  can be configured in a similar manner as shown in  FIG. 2 . 
         [0058]    The detection section  270  is configured to detect a deactivation of the power-up signal PWRUP_SLA 1  and activate the detection signal PWRERR_DET. The detection section  270  can comprise a transistor M 2 . In the transistor M 2 , the source receives the source voltage VDD, the gate receives the power-up signal PWRUP_SLA 1 , and the drain is connected to a through-silicon via  500 . 
         [0059]    The slave chip SLA 2  comprises a power-up signal generation section  310 , drivers  320  and  330 , a main circuit block  340 , fuses  350  and  360 , and a detection section  370 . 
         [0060]    The power-up signal generation section  310 , the drivers  320  and  330 , the main circuit block  340 , and the fuses  350  and  360  can be configured in a similar manner as shown in  FIG. 2 . 
         [0061]    The detection section  370  is configured to detect aI deactivation of the power-up signal PWRUP_SLA 2  and activate the detection signal PWRERR_DET. The detection section  370  can comprise a transistor M 3 . In the transistor M 3 , the source receives the source voltage VDD, the gate receives the power-up signal PWRUP_SLA 2 , and the drain is connected to the through-silicon via  500 . 
         [0062]    Alternatively, metal options may also be used in place of the fuses  250 ,  260 ,  350  and  360 . 
         [0063]    The detection signal PWRERR_DET generated by the slave chips SLA 1  and SLA 2  may be transmitted to the master chip MAS. Thus, the detection sections  270  and  370  of the slave chips SLA 1  and SLA 2  are connected to the control section  150  of the master chip MAS by the through-silicon via  500 . A bonding wire may be used in place of the through-silicon via  500 . 
         [0064]    According to the embodiment of the present disclosure, the slave chips SLA 1  and SLA 2  in the semiconductor apparatus  101  are separately tested while the fuses  250 ,  260 ,  350  and  360  are connected. 
         [0065]    The through-silicon vias  400  and  500  are not formed at this time. 
         [0066]    After tests are completed, the fuses  250 ,  260 ,  350  and  360  are cut off and the through-silicon vias  400  and  500  are formed to construct the multi-chip package. 
         [0067]    When the fuses  250 ,  260 ,  350  and  360  are cut off, power-up signals PWRUP_SLA 1  and PWRUP_SLA 2  cannot be inputted to the drivers  220  and  320 . 
         [0068]    Hence, during a normal operation after the construction of the multi-chip package, even when any one of the power-up signals PWRUP_MAS, PWRUP_SLA 1  and PWRUP_SLA 2  has a different level, it is possible to prevent the formation of an abnormal current path. 
         [0069]    After the multi-chip package is constructed, the power-up signal PWRUP_MAS generated by the power-up signal generation section  110  of the master chip MAS is transmitted to the slave chips SLA 1  and SLA 2  by the through-silicon via  400 . 
         [0070]    That is to say, after the construction of the multi-chip package is finished, the operations of all the chips, that is, the master chip MAS and the slave chips SLA 1  and SLA 2  are controlled by the power-up signal PWRUP_MAS. 
         [0071]    At this time, differences are likely to exist in the operational characteristics of devices constituting the master chip MAS and the slave chips SLA 1  and SLA 2 . While the formation of an abnormal current path can be prevented by cutting off the fuses  250 ,  260 ,  350  and  360 , there is no method for compensating the differences in the operational characteristics of the devices constituting the master chip MAS and the slave chips SLA 1  and SLA 2 . 
         [0072]    Thus, while the level of the source voltage VDD can be a level capable of activating the power-up signal PWRUP_MAS, that is, a level capable of ensuring the stable operation of the master chip MAS, the level of the source voltage VDD may not be a level capable of ensuring the stable operations of the slave chips SLA 1  and SLA 2 . 
         [0073]    Hence power-up abnormalities of the slave chips SLA 1  and SLA 2  are detected, so the operations of all the chips constituting the multi-chip package can be controlled. 
         [0074]    When one of the power-up signals PWRUP_SLA 1  and PWRUP_SLA 2  outputted from the slave chips SLA 1  and SLA 2  is deactivated, or at a low level for example, it is assumed that the power-up signal PWRUP_SLA 1  is a high level and the power-up signal PWRUP_SLA 2  is a low level. 
         [0075]    Because the power-up signal PWRUP_SLA 2  is a low level, the high level signal outputted from the detection section  370  is supplied to the control section  150  of the master chip MAS by the through-silicon via  500  as the detection signal PWRERR_DET. 
         [0076]    Since the detection signal PWRERR_DET is high, the transistor M 1  of the control section  150  is turned on, and according to this, the power-up signal PWRUP_MAS transits to an inactivation level, that is, a low level. 
         [0077]    The deactivated power-up signal PWRUP_MAS is supplied to all the main circuit blocks  140 ,  240  and  340 . 
         [0078]    As a consequence, all the main circuit blocks  140 ,  240  and  340  interrupt the operations of all the chips constituting the multi-chip package, that is, the master chip MAS and the slave chips SLA 1  and SLA 2 , in response to the deactivated power-up signal PWRUP_MAS. 
         [0079]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the apparatus and method described herein should not be limited based on the described embodiments. Rather, the apparatus and method described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.