Abstract:
A switching mode power supply (SMPS) and a driving method thereof are provided. The SMPS includes a power supply block that includes a first switch coupled to a first coil of a primary side of a transformer for converting an input voltage, wherein the power supply block supplies power to a second coil and a third coil of a secondary side of the transformer according to operation of the first switch; and a PWM signal generator determines a turn-on time of the first switch according to the input voltage, and the turn-on time is determined regardless of a power magnitude of an output terminal connected to the second coil. Accordingly, screen noise due to a ripple can be eliminated and stress on the switch breakdown due to excessive power input can be reduced to enable an SMPS with stable driving.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to and the benefit of Korean Patent Application No. 10-2007-0030307 filed in the Korean Intellectual Property Office on Mar. 28, 2007, the entire contents of which are incorporated herein by reference. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a switching mode power supply (SMPS). More particularly, the present invention relates to a quasi-resonant switching type SMPS and a driving method thereof. 
         [0004]    2. Description of the Related Art 
         [0005]    An SMPS is a device that rectifies an input AC voltage to an input DC voltage (DC-link voltage) and converts the input DC voltage to an output DC voltage having a different level. The output DC voltage can be higher or lower than the input DC voltage. The SMPS is generally used for battery supplies that power electronic devices, in particular, digital televisions and computer displays. 
         [0006]    A quasi-resonant SMPS turns on a main switch at valleys of the drain-source voltage (Vds) of the switch. 
         [0007]      FIG. 1  is a diagram illustrating a relationship between the switching frequency fs and the output power (Po) of a conventional quasi-resonant SMPS when the input AC voltage is 110 V or 220V. 
         [0008]      FIG. 1  illustrates that the output power Po of the SMPS decreases as the switching frequency fs increases. Accordingly, as Po decreases, switching losses increase. As also shown, when the AC input voltage Vin increases, the switching frequency fs further increases. As a result, there may be an increase in switching losses and audible noise due to intermittent switching. 
         [0009]      FIG. 2  illustrates distributions of the input power limit Pin Lim  and the switching frequency fs as a function of the input voltage Vin of a conventional quasi-resonant SMPS. Pin Lim  depends upon the current limit I Lim  of the SMPS. In the operation of the conventional quasi-resonant SMPS, a current flowing from the drain to the source of the main switch Ids is prevented from exceeding I Lim . Accordingly, the input power Pin of the SMPS is limited not to exceed a predetermined level, the input power limit Pin Lim , to prevent excessive power input. 
         [0010]    However, even when Ids is limited to the current limit I Lim , the input power Pin is not necessarily limited to Pin Lim . As shown in  FIG. 2 , as Vin increases, the switching frequency fs can increase and the input power limit Pin Lim  increases. Accordingly, there may be excessive power input into the SMPS, placing stress on the main switch, possibly damaging the switch. 
         [0011]    A conventional quasi-resonant SMPS can solve this problem by turning on the main switch at a minimum of a second valley of the Vds voltage when the switching frequency fs exceeds a reference frequency. This is described with reference to  FIG. 3 . 
         [0012]      FIG. 3  is a diagram illustrating the switching of the main switch of a conventional quasi-resonant SMPS at a minimum of a minimum of a first valley or minimum of a second valley of the Vds voltage, depending upon the output power Po and the switching frequency fs. 
         [0013]    As shown in  FIG. 3 , the conventional quasi-resonant SMPS turns on the main switch at a minimum of a second valley of the Vds voltage if the switching frequency fs is greater than a reference frequency due to a small output power Po. However, the SMPS turns on the main switch at a minimum of a first valley of the Vds voltage if the switching frequency fs is smaller than a reference frequency due to a large output power Po. Accordingly, the SMPS turns on the main switch at a minimum of a second valley of the Vds voltage when output power Po is small to prevent the switching frequency fs from exceeding a predetermined level, thereby protecting the switch from excessive power input and stress. 
         [0014]    However, due to a change of the output power Po in the conventional quasi-resonant SMPS, a ripple is generated in the output voltage Vo when the turn-on time of the main switch changes from a minimum of a minimum of a first valley of the Vds voltage to a minimum of a second valley of the Vds voltage, or when the turn-on time of the main switch changes from a minimum of a second valley of the Vds voltage to a minimum of a minimum of a first valley. In particular, the ripple generates noise on a screen when the SMPS is used for an image display device such as a cathode ray tube (CRT) TV. The ripple may be even more pronounced for a high definition television (HDTV). 
         [0015]    The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art. 
       SUMMARY 
       [0016]    Briefly and generally, embodiments include an SMPS and a driving method thereof having the advantages of preventing excessive power input and eliminating screen noise caused by a ripple. 
         [0017]    In one aspect, an SMPS includes a power supply block having a first switch coupled to a first coil of a primary side of a transformer for converting an input voltage, wherein the power supply block supplies power to a second coil and a third coil of a secondary side of the transformer according to operation of the first switch; and a PWM signal generator that receives a feedback voltage corresponding to a first voltage generated in the second coil, a sensing signal corresponding to a current flowing to a first switching transistor, and a third voltage corresponding to a second voltage generated in the third coil to control on/off of the first switch, wherein the PWM signal generator determines a turn-on time of the first switch according to the input voltage, and the turn-on time is determined regardless of a power magnitude of an output terminal connected to the second coil. 
         [0018]    Another embodiment provides a method of driving an SMPS that supplies power to a second coil and a third coil of a secondary side of a transformer according to operation of a switch coupled to a first coil of a primary side of the transformer for converting an input voltage, including: a) comparing the input voltage with that of a predetermined first voltage; b) turning on the switch at a minimum of a minimum of a first valley of a voltage applied to the switch if the input voltage is lower than the first voltage; and c) turning on the switch at a minimum of a second valley of a voltage applied to the switch if the input voltage is higher than the first voltage. 
         [0019]    Yet another embodiment provides a method of driving an SMPS that supplies power to a second coil and a third coil of a secondary side of a transformer according to operation of a switch coupled to a first coil of a primary side of the transformer for converting an input voltage, including: a) generating a first signal for maintaining a first level during a first period from when the switch is turned on; b) comparing a length of the first period with that of a second period in which the switch maintains an ON state; c) turning on the switch if the first period is shorter than the second period at a minimum of a minimum of a first valley of a voltage applied to the switch; and d) turning on the switching element if the first period is longer than the second period at a minimum of a second valley of a voltage applied to the switch. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1  illustrates a relationship between a switching frequency fs and an output power Po of a conventional quasi-resonant SMPS when an input AC voltage is 110V and 220V. 
           [0021]      FIG. 2  illustrates distributions of an input power limit Pin Lim  and a switching frequency fs corresponding to a Vin of a conventional quasi-resonant SMPS. 
           [0022]      FIG. 3  illustrates the switching of the main switch of a conventional quasi-resonant SMPS at a minimum of a minimum of a first valley or minimum of a second valley of the Vds voltage, depending upon the output power Po and the switching frequency fs. 
           [0023]      FIG. 4  is a schematic circuit diagram of an SMPS. 
           [0024]      FIG. 5  is a schematic circuit diagram of an PWM signal generator  600 . 
           [0025]      FIG. 6  is a schematic circuit diagram of an exemplary valley selector  660 . 
           [0026]      FIG. 7  is a diagram illustrating an operation of an exemplary valley selector  660  as an input voltage Vin rises. 
           [0027]      FIG. 8  is a diagram illustrating an operation of an exemplary valley selector  660  as an output power Po increases when an input voltage Vin is high. 
           [0028]      FIG. 9  is a diagram illustrating an operation of a conventional quasi-resonant SMPS shown in  FIG. 3  as it turns on at a minimum of a minimum of a first valley or a minimum of a second valley of the drain-source voltage Vds of the switching transistor  140 , according to an input voltage Vin and an output power Po. 
           [0029]      FIG. 10  is a diagram illustrating an operation of an exemplary SMPS according to an embodiment of the present invention as it turns on at a minimum of a minimum of a first valley or a minimum of a second valley of the drain-source voltage Vds of the switching transistor  140 , according to an input voltage and an output power Po. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0030]    In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. 
         [0031]    Throughout this specification and the claims that follow, when it is described that an element is “coupled” to another element, the element may be “directly coupled” to the other element, or “electrically coupled” to the other element through one or more additional elements. 
         [0032]    Further, throughout this specification, after the main switch of an SMPS is turned off, the minimum of the drain-source voltage of the main switch is referred to as a “valley.” The first minimum of the drain-source voltage of the main switch is referred to as a “minimum of a minimum of a first valley” and the second minimum of the drain-source voltage of the main switch is referred to as a “minimum of a second valley”. 
         [0033]      FIG. 4  is a schematic circuit diagram of an SMPS. The SMPS may include a power supply block  100 , an output block  200 , a bias voltage supply block  300 , a sync voltage generator block  400 , a feedback circuit block  500 , and a PWM signal generator  600 . 
         [0034]    The power supply block  100  may include a bridge diode (BD)  110  for rectifying an AC input ACin, a capacitor (Cin)  120  for smoothing a rectified voltage, a primary coil (L 1 )  130  of a transformer having a first terminal connected to the capacitor  120 , a switching transistor (Qsw)  140 , also referred to as a main switch. The drain of the switching transistor  140  can be connected to a second terminal of the primary coil  130  of the transformer, and a detection resistor (Rsense)  150  connected between a source of the switching transistor  140  and a ground terminal to detect the current flowing from the drain to the source of the switching transistor  140  (Ids). The switching transistor  140  can be implemented as a metal oxide semiconductor field effect transistor (MOSFET). 
         [0035]    The power supply unit  100  can convert the input AC voltage ACin to a DC voltage Vin through the bridge diode  110  and the capacitor  120 , and can supply power to a secondary coil (L 2 )  210  of the transformer, which is a part of the output block  200 , according to the duty of the switching transistor  140 . 
         [0036]    The output unit  200  may include the secondary coil  210  of the transformer, a diode (D 1 )  220  having an anode connected to a first terminal of the secondary coil  210  of the transformer, a capacitor (C 1 )  230  connected between a cathode of the diode  220  and a ground, a resistor (R 1 )  240  having a first terminal connected to a cathode of the diode  220 , a photodiode (PD)  250  having an anode connected to a second terminal of the resistor  240 , and a zener diode (ZD)  260  having a cathode connected to a cathode of the photodiode  250  and having an anode connected to ground. Here, a voltage across the capacitor  230  is an output voltage V 0 , and the current of the photodiode  250  changes according to output voltage V 0 . The photodiode  250  and the phototransistor (PT)  510  of the feedback circuit block  500  constitute a photocoupler, which provides information corresponding to the output voltage V 0  to the feedback circuit block  500 . 
         [0037]    The bias voltage supply block  300  may include a tertiary coil (L 3 )  310  of the transformer, a diode (D 2 )  320  having an anode connected to a first terminal of the secondary coil  310  of the transformer, and a capacitor (C 2 )  330  connected between a cathode of the diode  320  and ground. The PWM signal generator  600  can generally be realized by using an IC, and the bias voltage supply block  300  can supply a bias voltage Vcc for operating the IC. When the switching transistor  140  starts switching, the secondary coil  310  of the transformer can generate a voltage Vaux to charge the capacitor  330  through the diode  320  with a bias voltage Vcc. 
         [0038]    The sync voltage generator block  400  may include a resistor (R 2 )  410  having a first terminal connected to the first terminal of the tertiary coil (L 3 )  310  of the transformer, a resistor (R 3 )  420  having a first terminal connected to a second terminal of the resistor  410  and a second terminal connected to ground, a capacitor (C 3 )  430  having a first terminal connected to a second terminal of the resistor  410  and a second terminal connected to ground, and a diode (D 3 )  440  having a cathode connected to the first terminal of the capacitor  430  and an anode connected to ground. The sync voltage generator block  400  can supply a sync voltage Vsync that changes linearly and has a smaller amplitude than that of Vaux. 
         [0039]    The feedback circuit block  500  may include a phototransistor (PT)  510  and a capacitor (C 4 )  520  connected in parallel to the phototransistor  510 . The phototransistor  510  and the photodiode  250  of the output block  200  constitute a photocoupler. The phototransistor  510  may be controlled by the current flowing through the photodiode  250  such that if the output voltage V 0  increases, a feedback voltage Vfb charged to the capacitor  520  decreases, and if the output voltage V 0  decreases, the feedback voltage Vfb charged to the capacitor C 4  increases. 
         [0040]    The PWM signal generator  600  can receive a feedback signal Vfb and a sense signal Vsense that senses the Ids. The PWM signal generator  600  may compare the feedback signal Vfb to the sense signal Vsense and generate a pulse width modulating signal, output as a gate control signal V GS  for controlling a switching operation of the transistor  140 . 
         [0041]      FIG. 5  is a schematic circuit diagram of an embodiment of the PWM signal generator  600 . The PWM signal generator  600  may include a comparator  610 , a constant current supply block  620 , a comparator  630 , an SR flip-flop  640 , a NOR gate  650 , a valley selector  660 , and a gate driver  670 . The comparator  610  can be implemented as a Schmidt trigger. 
         [0042]    The comparator  610  can receive the sync voltage Vsync through a non-inverting terminal (+), and reference voltages Vref 1  and Vref 2  through an inverting terminal (−). The comparator  610  may perform a logical operation on the input voltages and transmit a signal corresponding to the result of the logical operation to the valley selector  660 . The reference voltages Vref 1  are Vref 2  can be voltages predetermined by a circuit designer. For example, the reference voltage Vref 2  can be set higher than the reference voltage Vref 1 . The comparator  610  can output a high level signal if the sync voltage Vsync is higher than the reference voltage Vref 2 , and output a low level signal if the sync voltage Vsync is lower than the reference voltage Vref 1 . If the sync voltage Vsync is higher than the reference voltage Vref 1  but lower than the reference voltage Vref 2 , the comparator  610  can maintain its previous output signal. 
         [0043]    The constant current supply block  620  may include a current source IFB having a first terminal connected to a voltage source Vcc 1  and a second terminal connected to the feedback circuit block  500  and an inverting terminal (−) of the comparator  630 . The current generator IFB may be a constant current source, and the current flowing from the current source IFB to the feedback circuit block  500  can be inversely proportional to the feedback voltage Vfb, wherein the current flowing to ground through a resistor (R 4 )  680  is proportional to the feedback voltage Vfb. The voltage across the resistor (R 4 )  680  can be equal to the feedback voltage Vfb. 
         [0044]    The comparator  630  can receive the sense signal Vsense voltage through the non-inverting terminal (+) and the feedback voltage Vfb through the inverting terminal (−). The comparator  630  may perform a logical operation on the input voltages and transmit a signal corresponding to the result of the logical operation to a reset terminal R of the SR flip-flop  640 . 
         [0045]    The SR flip-flop  640  can receive a valley selection signal at a set terminal S and the output signal of the comparator  630  at the reset terminal R. The flip-flop  640  may perform a logical operation on the input signals and transmit a signal corresponding to the result of the logical operation at the inverting output terminal (/Q) to an input terminal of the NOR gate  650 . 
         [0046]    The NOR gate  650  can receive a valley selection signal at a first input terminal and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  at a second input terminal. The NOR gate may perform a logical operation on the input signals and transmit a signal corresponding to the result of the logical operation to the gate driver  670 . 
         [0047]    The valley selector  660  can receive the feedback voltage Vfb, the output signal of the comparator  610 , and the output signal of the NOR gate  650 . The valley selector  660  may generate a valley selection signal according to the input signals, and transmit the valley selection signal to the set terminal S of the SR flip-flop  640  and the first input terminal of the NOR gate  650 . 
         [0048]    The gate driver  670  can generate a high level gate control signal V GS  if the output signal of the NOR gate  650  is a high level and a low level gate control signal V GS  if the output signal of the NOR gate  650  is a low level, and transmit the gate control signal V GS  to the gate of the switching transistor  140  to control switching of the transistor. 
         [0049]      FIG. 6  is a schematic circuit diagram of a valley selector  660 . The valley selector  660  may include a Vc voltage generator  6601 , a comparator  6602 , an SR flip-flop  6603 , a one-shot vibrator  6604 , AND gates  6605  and  6606 , an SR flip-flop  6607 , a switch  6608 , a T flip-flop  6609 , and an OR gate  6610 . 
         [0050]    The Vc voltage generator  6601  may include a current source Ic connected to a voltage source Vcc 2 , a capacitor (C 5 )  66011  having a first terminal connected to the current source Ic and a second terminal connected to ground, and a transistor (Q 1 )  66012 . The transistor  66012  can be implemented as a BJT. The transistor  66012  can have a collector connected to the first terminal of the capacitor  66011  and to the non-inverting terminal (+) of the comparator, an emitter connected to ground, and a base connected to the inverting output terminal (/Q) of the SR flip-flop  6603 . While the transistor  66012  is turned on, the current flowing from the current source Ic flows to ground through the transistor  66012 , and no voltage is charged to the capacitor  66011 . If the transistor  66012  is turned off, the current flowing from the current source Ic flows to the capacitor  66011 , wherein the capacitor  66011  is charged to a voltage Vc. Accordingly, the Vc voltage generator  6601  can supply a Vc voltage corresponding to the turn-on/off times of the transistor  66012  to the non-inverting terminal (+) of the comparator  6602 . 
         [0051]    The comparator  6602  can receive the Vc voltage at the non-inverting terminal (+) and the feedback voltage Vfb at the inverting terminal (−). The comparator  6602  may perform a logical operation on the input voltages and transmit a signal corresponding to the result of the logical operation to the reset terminal R of the SR flip-flop  6603 . 
         [0052]    The SR flip-flop  6603  can receive an output signal S 4  of the AND gate  6605  at the set terminal S and the output signal of the comparator  6602  at the reset terminal R. The SR flip-flop  6603  may perform a logical operation on the input signals, transmit a signal S 1  corresponding to the result of the logical operation at the output terminal Q to a first input terminal of the AND gate  6606 , and transmit a signal S 2  at the inverting output terminal (/Q) to the control terminal of the transistor  66012 . 
         [0053]    The one-shot vibrator  6604  may include an AND gate  66041  driven by the output signal of the NOR gate  650 , a resistor (R 5 )  66042 , and a capacitor (C 6 )  66043 . The one-shot vibrator  6604  can transmit a signal S 3  corresponding to the output signal of the NOR gate  650  through the AND gate  66041  to the AND gate  6605 . The S3 signal can change to a high level at a rising edge of the output signal of NOR gate  650 , and it can change to a low level after sustaining a high level for a predetermined time. 
         [0054]    The AND gate  6605  can receive the S3 signal at a first input terminal and the output signal of the comparator  6602  at a second inverted input terminal. The AND gate  6605  may perform a logical operation on the input signals and transmit a signal S 4  corresponding to the result of the logical operation to the set terminal S of the SR flip-flop  6603 . 
         [0055]    The AND gate  6606  can receive the inverted output signal of the NOR gate  650  at a first input terminal and the S1 signal at a second input terminal. The AND gate  6606  may perform a logical operation on the input signals and transmit a signal S 5  corresponding to the result of the logical operation to the set terminal S of the SR flip-flop  6607 . 
         [0056]    The SR flip-flop  6607  can receive the S5 signal at the set terminal S and the output signal of the NOR gate  650  at the reset terminal R. The SR flip-flop  6607  may perform a logical operation on the input signals and transmit a signal SV corresponding to the result of the logical operation at the output terminal Q to turn on/off the switch  6608 . 
         [0057]    The switch  6608  can selectively supply an output signal of the comparator  610  to the T flip-flop  6609 . In detail, if the SV signal of the SR flip-flop  6607  is at a high level, the switch  6608  can be turned on, and if the SV signal is at a low level, the switch  6608  can be turned off. 
         [0058]    The T flip-flop  6609  may receive an output signal of the comparator  610  when the switch  6608  is turned on to output a signal CL 1  at its non-inverting output terminal Q. If the output signal of the comparator  610  is at a high level, the CL1 signal becomes an inverted signal of the previous state, and if an output signal of the comparator  610  is at a low level, the CL1 signal remains in the previous state. Further, if the switch  6608  is turned off, the CL1 signal remains in the previous state before the switch  6608  was turned off. 
         [0059]    The OR gate  6610  can receive the CL1 signal at a first input terminal and the output signal of the comparator  610  at a second input terminal. The OR gate may perform a logical operation on the input signals and transmit a valley selection signal Vsel corresponding to the result of the logical operation to the first input terminal of the NOR gate  650 . 
         [0060]    The PWM signal generator  600  shown in  FIG. 5  may determine the turn-on/off times of the switching transistor  140  using the Vsel signal output from the valley selector  660  shown in  FIG. 6  as follows. 
         [0061]    Equation 1 represents a relationship between the maximum value (Ipk) of the switching current and the time Ton during which the switching transistor  140  maintains an ON state. 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     pk 
                   
                   = 
                   
                     
                       
                         V 
                         in 
                       
                       
                         L 
                         m 
                       
                     
                      
                     
                       T 
                       on 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where Lm is the inductance of the primary coil L 1  of a transformer. 
         [0062]    The time Ton during which the switching transistor  140  maintains an ON state can be proportional to the feedback voltage Vfb. Accordingly, the Ipk can be proportional to the feedback voltage Vfb. 
         [0063]    The valley selector  660  can set the S1 signal to maintain a high level for a predetermined period of time in proportion to the Ipk from a time in which the V GS  signal becomes a high level, i.e., the time in which the switching transistor  140  is turned on. A time Ton TH  in which the S1 signal maintains a high level can be represented as: 
         [0000]        T   on   TH   =K·I   pk   (2) 
         [0000]    where K is a constant. 
         [0064]    If the time Ton in which the V GS  signal maintains a high is shorter than the Ton TH , the valley selector  660  can output a valley selection signal Vsel for turning on the switching transistor  140  at the minimum of a minimum of a first valley of the Vds voltage. If the Ton is longer than the Ton TH , the valley selector  660  can output a valley selection signal Vsel for turning on the switching transistor  140  at the minimum of a second valley of the Vds voltage. 
         [0065]    The condition that the Ton is shorter than the Ton TH  can be expressed using Equations 1 and 2 as: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       L 
                       m 
                     
                     K 
                   
                   &lt; 
                   
                     V 
                     in 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0066]    As Lm and K are predetermined values, the PWM signal generator  600  can turn on the switching transistor  140  at the minimum of a first valley of the Vds voltage if the input voltage Vin is lower than a predetermined level set by the Lm and K values. If the Ton is longer than the Ton TH , i.e., if the input voltage Vin is higher than a predetermined level set by the Lm and K values, the PWM signal generator  600  turns on the switching transistor  140  at a minimum of a second valley of the Vds voltage. 
         [0067]    Visibly, the PWM signal generator  600  can vary a turn-on time of the switching transistor  140  according to the input voltage Vin. However, the PWM signal generator  600  can determine a turn-on time of the switching transistor  140  by comparing the time Ton during which the V GS  signal maintains a high level with the time Ton TH  during which the S1 signal maintains a high level, without directly sensing the input voltage Vin. Hereinafter, selection of a turn-on time of the switching transistor  140  corresponding to the input voltage Vin and the Po of the PWM signal generator  600  will be described with reference to  FIGS. 7 and 8 . 
         [0068]      FIG. 7  is a diagram illustrating an operation of an embodiment of the valley selector  660  as an input voltage Vin rises. 
         [0069]    At a time T 1 , when the sync voltage Vsync falls to a voltage lower than the reference voltage Vref 1 , the output signal CL 2  of the comparator  610  can change to a low level. In this case, because the SV signal maintains a low level, the CL1 signal maintains a low level, and the Vsel signal changes to a low level. 
         [0070]    When the Vsel signal changes to a low level, the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  can maintain a low level, and the V GS  signal can change to a high level. Accordingly, the S3 signal input to the set terminal S of the SR flip-flop  6603  also changes from a low level to a high level, and the S1 signal becomes a high level and the S2 signal becomes a low level. As the S2 signal changes to a low level, the transistor  66012  of the Vc voltage generator  6601  turns off, and the Vc voltage of capacitor  66011  increases. As the V GS  signal changes to a high level, the switching transistor  140  turns on, the current Ids gradually increases, and the sync voltage Vsync and the drain-source voltage Vds of the switching transistor become 0. 
         [0071]    As the S5 signal input to the set terminal S of the SR flip-flop  6607  maintains a low level, the SV signal maintains a low level, and the CL1 signal maintains a low level. Further, because the sync voltage Vsync is 0, the CL2 signal becomes a low level and the Vsel signal also becomes a low level. Further, in the SR flip-flop  640 , the Vsel signal, which is an input signal of the set terminal S, changes to a low level. However, the input signal of the reset terminal R maintains a low level, thus the output signal of the inversion output terminal (/Q) of the SR flip-flop  640  still maintains a low level. Accordingly, the V GS  signal maintains a high level. 
         [0072]    The S3 signal changes to a low level after maintaining a high level only during a predetermined time from when the V GS  signal changes to a high level. Thus, the S4 signal also changes from a high level to a low level. However, when the S3 and S4 signals change, the S1 and S2 signals maintain a high level and a low level, respectively, and the S5, SV, and CL1 signals do not change. Accordingly, the V GS  signal also maintains a high level. 
         [0073]    At a time T 2 , as the Vc voltage that starts to increase from the time T 1  reaches a Vfb voltage, the output signal of the comparator  6602  changes to a high level, the S 1  signal changes to a low level, and the S 2  signal changes to a high level. If the S 2  signal changes to a high level, the output signal of the comparator  6602  changes to a low level. However, the S 1  and S 2  signals maintain a low level and a high level, respectively. Accordingly, when the S1 signal changes, the S5 signal does not change, and the SV and CL1 signals do not change. Accordingly, the V GS  signal maintains a high level. 
         [0074]    At a time T 3 , as the Ids that starts to increase from the time T 1  reaches a predetermined level, the Vsense voltage becomes higher than the feedback voltage Vfb, and the output signal of the comparator  630  changes to a high level. Thus, the output signal of the inversion output terminal (/Q) of the SR flip-flop  640  changes from a low level to a high level. Accordingly, the V GS  signal changes from a high level to a low level, and the switching transistor  140  turns off. When the switching transistor  140  turns off, the Ids and the Vsense voltage become 0, and the comparator  630  outputs a low level signal. Accordingly, the output signal of the inversion output terminal (/Q) of the SR flip-flop  640  maintains a high level, and the S1 to S5 signals do not change. As the switching transistor  140  turns off, a Vds voltage is generated, and the sync voltage Vsync starts to increase according to the Vds voltage. 
         [0075]    At a time T 4 , the sync voltage Vsync that starts to increase from the time T 3  becomes higher than the reference voltage Vref 2 . As the sync voltage Vsync becomes higher than a reference voltage Vref 2 , the output signal CL 2  signal of the comparator  610  changes to a high level. As the SV signal is still at a low level, the switch  6608  is off, and the CL1 signal still sustains a low level. As the CL2 signal changes to a high level, the Vsel signal that is input to the set terminal S of the SR flip-flop  640  changes to a high level, and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  changes to a low level. Accordingly, the V GS  signal maintains a low level. 
         [0076]    At a time T 5 , the Vds voltage is at a minimum of a first valley and the sync voltage Vsync falls to a voltage that is lower than a reference voltage Vref 1 . Thus, the output signal CL 2  of the comparator  610  changes to a low level, the Vsel signal changes to a low level, and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  changes to a high level. Accordingly, the V GS  signal changes to a high level and the switching transistor  140  turns on. As the V GS  signal changes to a high level, the S3 and S4 signals change to a high level, the S1 signal changed to a high level, and the S2 signal changes to a low level. Accordingly, the S5 signal and the SV signal maintain a low level. 
         [0077]    The S3 signal changes to a low level after maintaining a high level for a predetermined time from when the V GS  signal changes to a high level, and the S4 signal also changes from a high level to a low level. However, when the S3 and S4 signals change, the S1 and S2 signals maintain a high level and a low level, respectively, and the S5, SV, and CL1 signals do not change. Accordingly, because the CL2 signal is at a low level, the Vsel signal becomes a low level. However, as both the output signal of the comparator  610  and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  become a low level, the V GS  signal maintains a high level. As the switching transistor  140  turns on, the current Ids gradually increases, and the sync voltage Vsync and the drain-source voltage Vds of the switching transistor  140  become 0. Accordingly, due to an increase of the input voltage Vin, the current Ids rises with a slope greater than at the time T 1 . 
         [0078]    At a time T 6 , as the current Ids that starts to increase from the time T 5  reaches a predetermined level, the Vsense voltage becomes higher than the feedback voltage Vfb, and the output signal of the comparator  630  and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  change from a low level to a high level. Accordingly, the V GS  signal changes from a high level to a low level and the switching transistor  140  turns off. As the V GS  signal changes to a low level, all signals that are input to the first and second input terminals of the AND gate  6606  change to a high level. In this case, the input signal at the first input terminal of the AND gate  6606  directly changes to a high level while the S1 signal input at the second input terminal of the AND gate  6606  changes to a high level later due to a signal delay time through the one-shot vibrator  6604 , the AND gate  6605 , and the SR flip-flop  6603 . Accordingly, at the time at which the V GS  signal changes to a low level, the S5 signal, which is an output signal of the AND gate  6605 , changes to a high level after temporarily maintaining a low level, and the SV signal changes to a high level. When the SV signal changes to a high level, the output signal of the comparator  610  is at a low level, and the CL1 signal, the CL2 signal, and the Vsel signal maintain a low level. As the switching transistor  140  turns off, the Ids and the Vsense voltage become 0, and the output signal of the comparator  630  changes to a low level. However, the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  maintains a high level. Further, as the switching transistor  140  turns off, a Vds voltage is generated, and a sync voltage Vsync starts to increase according to the Vds voltage. 
         [0079]    At a time T 7 , the sync voltage Vsync that started to increase from the time T 6  becomes higher than a reference voltage Vref 2 . As the sync voltage Vsync becomes higher than the reference voltage Vref 2 , the output signal CL 2  signal of the comparator  610  changes to a high level. Accordingly, as the SV signal is at a high level, the switch  6608  is in an ON-state, and the CL1 signal changes to a high level. As the CL1 and CL2 signals change to a high level, the Vsel signal that is input to the set terminal S of the SR flip-flop  640  changes to a high level, and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  changes to a low level. Accordingly, the V GS  signal maintains a low level. 
         [0080]    At a time T 8 , as the Vc voltage that starts to increase from the time T 5  reaches a Vfb voltage, the output signal of the comparator  6602  changes to a high level, the S1 signal changes to a low level, and the S2 signal changes to a high level. When the S2 signal changes to a high level, the output signal of the comparator  6602  changes to a low level. When the S1 signal changes to a low level, the S5 signal changes to a low level, and the SV signal maintains a high level. Thus, the CL1 and Vsel signals maintain a high level, and the V GS  signal maintains a low level. 
         [0081]    At a time T 9 , the Vds voltage is at a minimum of a first valley and the sync voltage Vsync falls to a voltage lower than the reference voltage Vref 1 . Thus, the output signal CL 2  of the comparator  610  changes to a low level. As the SV signal is at a high level and the CL2 signal is at a low level, the CL1 signal maintains a high level. Accordingly, the Vsel signal maintains a high level and the V GS  signal maintains a low level. 
         [0082]    At a time T 10 , the sync voltage Vsync rises to a higher voltage than the reference voltage Vref 2  as the Vds voltage rises due to resonance. As the sync voltage Vsync becomes higher than the reference voltage Vref 2 , the output signal CL 2  of the comparator  610  changes to a high level. As the SV signal is at a high level, the CL 1  signal becomes a low level by inverting an output signal in a previous state, and the Vsel signal maintains a high level. Accordingly, the V GS  signal maintains a low level. 
         [0083]    At a time T 11 , the Vds voltage is at a minimum of a second valley, the sync voltage Vsync falls to a lower voltage than the reference voltage Vref 1 , and the output signal CL 2  of the comparator  610  changes to a low level. Accordingly, the CL1 signal maintains a low level and the Vsel signal changes to a low level. Even though the Vsel signal changes to a low level, the output signal of the inversion output terminal (/Q) of the SR flip-flop  640  maintains a low level. Thus, the V GS  signal changes to a high level, and the switching transistor  140  turns on. As the V GS  signal changes to a high level, the S3 and S4 signals change to a high level, the S1 signal changes to a high level, and the S2 signal changes to a low level. As the S2 signal changes to a low level, the transistor  66012  of the Vc voltage generator  6601  turns off, and the voltage Vc charged to the capacitor  66011  increases. As the switching transistor  140  turns on, the Ids gradually increases, and the sync voltage Vsync and the drain-source voltage Vds of the switching transistor  140  become 0. Accordingly, the current Ids rises with a slope greater than at time T 5  due to the rise of the input voltage Vin. 
         [0084]    In this case, the S5 signal maintains a low level, the SV signal changes to a low level, and the CL1 signal maintains a low level. As the sync voltage Vsync is 0, the CL2 signal and the Vsel signal also become a low level. Further, the Vsel signal input at the set terminal S of the SR flip-flop  640  changes to a low level, the input signal of the reset terminal R of the SR flip-flop  640  maintains a low level, and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  still maintains a low level. Accordingly, the V GS  signal maintains a high level. 
         [0085]    The S3 signal changes to a low level after maintaining a high level for a predetermined time when the V GS  signal changes to a high level, and the S4 signal also changes from a high level to a low level. However, when the S3 and S4 signals change, the S1 signal and the S2 signal maintain a high level and a low level, respectively, and the S5, SV, and CL1 signals do not changed such that the V GS  signal also maintains a high level. 
         [0086]    At a time T 12 , the operation of the valley selector  660  is repeated from time 
         [0087]    T 6 . 
         [0088]    As shown in  FIG. 7 , as the input voltage Vin rises, the rising slope of the Ids increases, and the period Ton in which the V GS  signal maintains a high level gradually shortens. As the feedback voltage Vfb is uniformly maintained, the period Ton TH  in which the S1 signal maintains a high level is uniformly maintained, and the turn-on/off times of the switching transistor  140  can be changed according to the input voltage Vin. 
         [0089]    The PWM signal generator  600  changes the S1 signal to a high level when the V GS  signal changes to a high level. After the S1 signal changes to a low level, if the V GS  signal changes to a low level, the minimum of a first valley of the Vds voltage turns on the switching transistor  140 . In contrast, the PWM signal generator  600  can immediately turn on the switching transistor  140  at the minimum of a first valley of the Vds voltage if the V GS  signal changes to a low level before the S1 signal changes to a low level. 
         [0090]    The SMPS can operate stably within the voltage range in which typical TVs and high definition HDTVs are driven. Accordingly, unlike the conventional quasi-resonant SMPS, when the turn-on time of the switching transistor  140  changes, no ripple is generated in the output voltage V 0  of the SMPS. Thus, HDTVs can be operated with negligible screen noise. 
         [0091]    Embodiments of the SMPS turn on the switching transistor  140  at the minimum of a second valley of the Vds voltage when the input voltage Vin is high to prevent an increase of the input power limit Pin Lim  due to the switching frequency fs increasing in proportion to the input voltage Vin. This is described with reference to  FIG. 8 . 
         [0092]      FIG. 8  is a diagram illustrating an operation of a valley selector  660  as the output power Po increases when an input voltage Vin is high. 
         [0093]    At a time T 1 , the sync voltage Vsync falls to a voltage lower than the reference voltage Vref 1  and the output signal CL2 signal of the comparator  610  changes to a low level. Accordingly, the SV signal changes to a low level, the CL1 signal maintains a low level and the Vsel signal changes to a low level. 
         [0094]    When the Vsel signal changes to a low level, the output signal of the inversion output terminal (/Q) of the SR flip-flop  640  maintains a low level, and the V GS  signal changes to a high level to turn on the switching transistor  140 . As the V GS  signal changes to a high level, the S3 and S4 signals change to a high level. Thus, the S1 signal changes to a high level while the S2 signal changes to a low level. As the S2 signal changes to a low level, the transistor  66012  of the Vc voltage generator  6601  turns off, and voltage Vc charged to the capacitor C 5  increases. As the switching transistor  140  turns on, the Ids gradually increases, and the sync voltage Vsync and the drain-source voltage Vds of the switching transistor  140  become 0. 
         [0095]    In this case, the S5 signal maintains a low level while the SV signal changes to a low level and the CL1 signal maintains a low level. Further, because the sync voltage Vsync is 0, the CL2 signal and the Vsel signal also become a low level. Further, in the SR flip-flop  640 , the Vsel signal, which is an input signal of the set terminal S, changes to a low level, but the input signal of the reset terminal R maintains a low level such that output signal of the inverting output terminal (/Q) of the SR flip-flop  640  maintains a low level. Accordingly, the V GS  signal maintains a high level. 
         [0096]    The S3 signal changes to a low level after maintaining a high level for a predetermined time from when the V GS  signal changes to a high level, and thus the S4 signal also changes from a high level to a low level. However, when the S3 and S4 signals change, the S1 and S2 signals maintain a high level and a low level, respectively, and the S5, SV, and CL1 signals do not change. Accordingly, the V GS  signal also maintains a high level. 
         [0097]    At a time T 2 , when the Ids that started to increase at time T 1  reaches a predetermined level, the Vsense voltage becomes higher than the feedback voltage Vfb, and the output signal of the comparator  630  and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  change from a low level to a high level. Accordingly, the V GS  signal changes from a high level to a low level, and the switching transistor  140  turns off. As the V GS  signal changes to a low level, all signals that are input to the first input terminal and the second input terminal of the AND gate  6606  change to a high level. In this case, the input signal of the first input terminal of the AND gate  6606  directly changes to a high level while the S1 signal that is input to the second input terminal of the AND gate  6606  changes to a high level later than the input signal of the first input terminal due to a signal delay time through the one-shot vibrator  6604 , the AND gate  6605 , and the SR flip-flop  6603 . Accordingly, when the V GS  signal changes to a low level, the S5 signal, which is an output signal of the AND gate  6605 , changes to a high level after temporarily maintaining a low level, and the SV signal changes to a high level. When the SV signal changes to a high level, the output signal of the comparator  610  is at a low level, and the CL1 signal, CL2 signal, and Vsel signal all maintain a low level. As the switching transistor  140  turns off, the Ids and the Vsense voltage become 0 and the output signal of the comparator  630  changes to a low level while the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  maintains a high level. Further, as the switching transistor  140  turns off, a Vds voltage is generated, and the sync voltage Vsync starts to increase according to the Vds voltage. 
         [0098]    At a time T 3 , as the Vc voltage that started to increase at time T 1  reaches the Vfb voltage, the output signal of the comparator  6602  changes to a high level, the S1 signal changes to a low level, and the S2 signal changes to a high level. As the S2 signal changes to a high level, the output signal of the comparator  6602  changes to a low level. As the S1 signal changes to a low level, the S5 signal changes to a low level and the SV signal changes to a high level. Accordingly, as the output signal of the comparator  610  is at a high level, the CL1 signal, CL2 signal, and Vsel signal all change to a high level, and the V GS  signal maintains a low level. 
         [0099]    At a time T 4  time point at a minimum of a first valley of the Vds voltage, the sync voltage Vsync falls to a voltage lower than the reference voltage Vref 1  and the output signal CL 2  signal of the comparator  610  changes to a low level. As the SV signal is at a high level and the CL2 signal is at a low level, the CL1 signal maintains a high level, and the Vsel signal maintains a high level. Accordingly, the V GS  signal maintains a low level. 
         [0100]    At a time T 5  at which the sync voltage Vsync rises to a voltage higher than the reference voltage Vref 2 , the Vds voltage rises due to resonance. As the sync voltage Vsync becomes higher than the reference voltage Vref 2 , the output signal CL 2  signal of the comparator  610  changes to a high level. As the SV signal is at a high level, the CL1 signal becomes a low level by inverting the output signal, and the Vsel signal maintains a high level. Accordingly, the V GS  signal maintains a low level. 
         [0101]    At a time T 6  at a minimum of a second valley of the Vds voltage, the sync voltage Vsync falls to a voltage lower than a reference voltage Vref 1  and the output signal CL 2  of the comparator  610  changes to a low level. Thus, the CL1 signal maintains a low level and the Vsel signal changes to a low level. When the Vsel signal changes to a low level, the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  maintains a low level and the V GS  signal changes to a high level to turn on the switching transistor  140 . As the V GS  signal changes to a high level, the S3 and S4 signals change to a high level, the S1 signal changes to a high level, and the S2 signal changes to a low level. As the S2 signal changes to a low level, the transistor  66012  of the Vc voltage generator  6601  turns off, and the voltage Vc charged to the capacitor C 5  increases. As the switching transistor  140  turns on, the Ids gradually increases, and the sync voltage Vsync and the drain-source voltage Vds of the switching transistor  140  become 0. 
         [0102]    In this case, the S5 signal maintains a low level while the SV signal changes to a low level and the CL1 signal maintains a low level. Further, because the sync voltage Vsync is 0, the CL2 signal and Vsel signal also become a low level. Further, in the SR flip-flop  640 , the Vsel signal changes to a low level while the input signal of the reset terminal R maintains a low level, and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  maintains a low level. Accordingly, the V GS  signal maintains a high level. 
         [0103]    The S3 signal changes to a low level after maintaining a high level for a predetermined time from when the V GS  signal changes to a high level. Thus, the S4 signal also changes from a high level to a low level. However, when the S3 and S4 signals change, the S1 and S2 signals maintain a high level and a low level, respectively, and the S5, SV, CL1 signals do not change. Accordingly, the V GS  signal maintains a high level. 
         [0104]    At a time T 7  when the Ids that starts to increase from time T 6  time reaches a predetermined level, the Vsense voltage becomes higher than the feedback voltage Vfb, and the output signal of the comparator  630  and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  changes from a low level to a high level. Thus, the V GS  signal changes from a high level to a low level and the switching transistor  140  turns off. As the V GS  signal changed to a low level, all signals that are input to the first input terminal and the second input terminal of the AND gate  6606  change to a high level. In this case, the input signal of the first input terminal of the AND gate  6606  directly changes to a high level while the S1 signal that is input to the second input terminal of the AND gate  6606  changes to a high level later than the first input terminal input signal due to a signal delay time through the one-shot vibrator  6604 , AND gate  6605 , and SR flip-flop  6603 . Accordingly, when the V GS  signal changes to a low level, the S5 signal changes to a high level after temporarily maintaining a low level, and the SV signal changes to a high level. When the SV signal changes to a high level, the output signal of the comparator  610  is at a low level, and the CL1 signal, CL2 signal, and Vsel signal all maintain a low level. As the switching transistor  140  turns off, the Ids and the Vsense voltage become 0, the output signal of the comparator  630  changes to a low level, and the output signal of the inverting output terminal (/Q) of the SR flip-flop  640  maintains a high level. Further, as the switching transistor  140  turns off, a Vds voltage is generated, and the sync voltage Vsync starts to increase according to the Vds voltage. 
         [0105]    At a time T 8 , as the Vc voltage that starts to increase from time T 6  reaches the Vfb voltage, the output signal of the comparator  6602  changes to a high level, the S1 signal changes to a low level, and the S2 signal changes to a high level. As the S2 signal changes to a high level, the output signal of the comparator  6602  changes to a low level. As the S1 signal changes to a low level, the S5 signal changes to a low level and the SV signal changes to a high level. Thus, as the output signal of the comparator  610  is at a high level, the CL1 signal, CL2 signal, and Vsel signal change to a high level. Accordingly, the V GS  signal maintains a low level. 
         [0106]    At a time T 9 , the operation of the described embodiment of the valley selector  660  is repeated from time T 4 . 
         [0107]    As shown in  FIG. 8 , as the output power Po increases, the feedback voltage Vfb increases. Thus, the rising slope of the current Ids is uniformly maintained while the peak value Ipk of the Ids gradually rises. Accordingly, both the period Ton in which the V GS  signal maintains a high level and the period Ton TH  in which the S1 signal maintains a high level are gradually lengthened by the same ratio, and the turn-on/off time of the switching transistor  140  can be changed according to the input voltage Vin regardless of the output power Po. 
         [0108]    An embodiment of the SMPS can turn on the switching transistor  140  at a minimum of a second valley of the Vds voltage when the input voltage Vin is high. Therefore, unlike a conventional SMPS, the input power limit Pin Lim  does not increase due to the switching frequency fs increasing in proportion to the input voltage Vin in the exemplary SMPS. Accordingly, excessive stress on the switching transistor  140  can be reduced to enable stable operation. 
         [0109]    Hereinafter, driving of a conventional quasi-resonant SMPS and driving of an embodiment of the present SMPS are compared, with reference to  FIGS. 9 and 10 . 
         [0110]      FIG. 9  is a diagram illustrating an operation of a conventional quasi-resonant SMPS shown in  FIG. 3  as it turns on at a minimum of a first valley or a minimum of a second valley of the drain-source voltage Vds of the switching transistor  140 , according to an input voltage Vin and the output power Po.  FIG. 10  is a diagram illustrating an operation of an embodiment of the present SMPS as it turns on at a minimum of a first valley or a minimum of a second valley of the drain-source voltage Vds of the switching transistor  140 , according to an input voltage and the output power Po. 
         [0111]    Unlike the conventional SMPS, the embodiments of the present SMPS can turn on the switching transistor  140  at the minimum of a first valley or the minimum of a second valley of the Vds voltage depending on the input voltage Vin and essentially regardless of the output power Po. 
         [0112]    The embodiments of the present SMPS can change the turn-on time of the switching transistor  140  according to the input voltage Vin essentially regardless of the output power. That is, the embodiments of the present SMPS can determine the turn-on time of the switching transistor  140  by comparing the time to maintain the V GS  signal at a high level corresponding to the increasing slope of the Ids with a Ton TH  corresponding to the peak value Ipk of the Ids without directly sensing the input voltage Vin. Accordingly, screen noise can be substantially reduced and stress on the switching transistor due to excessive power input can be reduced to enable an SMPS with stable operation. 
         [0113]    Embodiments of the present SMPS can substantially reduce screen noise by determining the turn-on time of the switching transistor  140  according to an input voltage Vin regardless of the output power Po. These embodiments of the present SMPS reduce the noise due to voltage ripples and limit stress on the transistor due to excessive power input. 
         [0114]    While this invention has been described in connection with specific embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.