Abstract:
A power combiner and divider device includes a first port electrically connected to a first impedance line and a second impedance line; a second port electrically connected to the first impedance line and a coupled line; a third port electrically connected to the second impedance line and the coupled line; a third impedance line electrically connected to the coupled line; and a fourth impedance line electrically connected to each of the third impedance line and the coupled line.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/340,919 filed on May 24, 2016, the contents of which, in its entirety, is herein incorporated by reference. 
     
    
     GOVERNMENT INTEREST 
       [0002]    The embodiments herein may be manufactured, used, and/or licensed by or for the United States Government without the payment of royalties thereon. 
     
    
     BACKGROUND 
     Technical Field 
       [0003]    The embodiments herein generally relate to electrical circuits, and more particularly to microwave combiner/divider circuits. 
       Description of the Related Art 
       [0004]    Radar systems include multiple high frequency electronic modules and circuits. A combiner/divider circuit is an important component of a radar system that allows for managing the distribution of the electronic signal power throughout the system. An electronic power divider may be made of multiple coupling circuits, which when operated in a reverse direction can function as a power combiner. It is desirable to design and implement combiner/divider circuits that can operate in broadband system and can handle high power signals. 
         [0005]    The Wilkinson divider is a commonly used power divider. However, a main limitation of the Wilkinson divider stems from its isolation resistor that poses two problems. First, it is assumed to have zero or very small electrical delay. Second, it joins two signal branches of the divider and does not connect to ground. Moreover, the requirement of having a very small electrical length is difficult to satisfy, especially, for discrete resistors (such as surface mount resistors). Even for Monolithic Microwave Integrated Circuits (MMICs), satisfying this requirement means the two signal branches have to be brought into close proximity with each other (which introduces coupling) and using a resistor with small physical dimensions. However, reducing the resistor&#39;s physical dimension reduces its power handling capability. Additionally, the fact that it is not grounded makes it difficult to dissipate the heat. 
         [0006]    The Gysel combiner/divider may solve both problems and can be used for combing high power signals. It may further provide improvements, such as operating the Gysel combiner/divider with equal/unequal power division and arbitrary terminal impedances. Additionally, a dual-frequency operation of the combiner/divider may be provided. Coupled lines may also be used with Gysel dividers, to introduce signal filtering or dual band operation. The use of coupled lines may lead to greater losses in the divider and complicate the design process as the circuit acquires more poles and zeros. 
       SUMMARY 
       [0007]    In view of the foregoing, an embodiment herein provides a power combiner and divider device, the device comprising a first port electrically connected to a first impedance line and a second impedance line; a second port electrically connected to the first impedance line and a coupled line; a third port electrically connected to the second impedance line and the coupled line; a third impedance line electrically connected to the coupled line; and a fourth impedance line electrically connected to each of the third impedance line and the coupled line. 
         [0008]    The third impedance line may be electrically connected to a first resistor at a first connection point where the third impedance line is electrically connected to the coupled line, and wherein the first resistor may be electrically connected to ground. The fourth impedance line may be electrically connected to a second resistor at a second connection point where the fourth impedance line is electrically connected to the coupled line, and wherein the second resistor may be electrically connected to ground. The first resistor may be approximately 50 ohms and the second resistor is approximately 50 ohms. 
         [0009]    An even mode equivalent impedance from the second port and the third port may be adjusted independent from an odd mode equivalent impedance from the second port and the third port by adjusting a coupling ratio of the coupled line. The even mode equivalent impedance may be greater than the odd mode equivalent impedance. The first port may be configured to be a first input and the second and third ports may be configured to be a first plurality of outputs when the device is used as a divider, and the second and third ports may be configured to be a second plurality of inputs, and the first port may be configured to be a second output when the device is used as a combiner. 
         [0010]    The coupled line may comprise a first microstrip line having a first width; and a second microstrip line having a second width, wherein the first width is approximately equal to the second width, and wherein the first microstrip is in parallel with the second microstrip. The device may be configured to operate in a frequency range from a lower frequency to a higher frequency, wherein the higher frequency is approximately four times higher than the lower frequency. 
         [0011]    Another embodiment herein provides a method comprising partitioning a combiner and divider circuit into an incident even mode section and a reflection odd mode section; and isolating an incident even-mode signal from a reflected odd-mode signal such that the incident even-mode signal travels in a different path from the reflected odd-mode signal, wherein the reflected signal is generated by an impedance mismatch of an electronic joint in the circuit, wherein the circuit is configured to operate in a frequency range from a lower frequency to a higher frequency, wherein the higher frequency is approximately four times higher than the lower frequency. 
         [0012]    The method may further comprise electrically connecting a first port to a first impedance line and a second impedance line; electrically connecting a second port to the first impedance line and a coupled line; electrically connecting a third port to the second impedance line and the coupled line; electrically connecting a third impedance line to the coupled line; electrically connecting a fourth impedance line to each of the third impedance line and the coupled line. 
         [0013]    The method may further comprise electrically connecting the third impedance line to a first resistor at a first connection point where the third impedance line is electrically connected to the coupled line; and electrically connecting the first resistor to ground. The method may further comprise electrically connecting the fourth impedance line to a second resistor at a second connection point where the fourth impedance line is electrically connected to the coupled line; and electrically connecting the second resistor to ground. 
         [0014]    The first resistor may be approximately 50 ohms and the second resistor may be approximately 50 ohms. The method may further comprise adjusting a coupling ratio of the coupled line to adjust an even mode equivalent impedance from the second port and the third port independently from an odd mode equivalent impedance from the second port and the third port. The method may further comprise adjusting the even mode equivalent impedance to be greater than odd mode equivalent impedance. The method may further comprise adjusting the odd mode equivalent impedance to be approximately 50 ohms. 
         [0015]    Another embodiment herein provides a power combiner and divider device, the device comprising a first port electrically connected to a first impedance line and a second impedance line; a second port electrically connected to the first impedance line and a coupled line; a third port electrically connected to the second impedance line and the coupled line; a third impedance line electrically connected to the coupled line; and a fourth impedance line electrically connected to each of the third impedance line and the coupled line, wherein the third impedance line is electrically connected to a first resistor at a first connection point where the third impedance line is electrically connected to the coupled line, and the first resistor is electrically connected to ground, and wherein the fourth impedance line is electrically connected to a second resistor at a second connection point where the fourth impedance line is electrically connected to the coupled line, and the second resistor is electrically connected to ground. 
         [0016]    The first resistor may be approximately 50 ohms and the second resistor is approximately 50 ohms, and wherein an even mode equivalent impedance from the second port and the third port may be adjusted independent from an odd mode equivalent impedance from the second port and the third port by adjusting a coupling ratio of the coupled line. The even mode equivalent impedance may be greater than odd mode equivalent impedance, and wherein the odd mode equivalent impedance may be approximately 50 ohms. 
         [0017]    These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which: 
           [0019]      FIG. 1A  illustrates a schematic diagram of a known Gysel combiner/divider circuit; 
           [0020]      FIG. 1B  illustrates a schematic diagram of an even mode equivalent circuit of the known Gysel combiner/divider circuit; 
           [0021]      FIG. 1C  illustrates a schematic diagram of an odd mode equivalent circuit of the known Gysel combiner/divider circuit; 
           [0022]      FIG. 2A  illustrates a schematic diagram of a combiner/divider according to an embodiment herein; 
           [0023]      FIG. 2B  illustrates a schematic diagram of an even mode equivalent circuit of the combiner/divider according to an embodiment herein; 
           [0024]      FIG. 2C  illustrates a schematic diagram of an odd mode equivalent circuit of the combiner/divider according to an embodiment herein; 
           [0025]      FIG. 3A  is a graph illustrating simulation results of scattering parameters S 11  and S 21  according to an embodiment herein; 
           [0026]      FIG. 3B  is a graph illustrating simulation results of scattering parameters S 22  and S 32  according to an embodiment herein; 
           [0027]      FIG. 4  illustrates a layout diagram of a combiner/divider covering 2.5-8 GHz according to an embodiment herein; 
           [0028]      FIG. 5  is a graph illustrating simulation and measured results of scattering parameters according to an embodiment herein; 
           [0029]      FIG. 6  is a graph illustrating simulation and measured results of scattering parameters according to an embodiment herein; and 
           [0030]      FIG. 7  is a flow diagram illustrating a method according to an embodiment herein. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein. 
         [0032]    A goal for next generation radar and electronic warfare systems is to consolidate multiple, single-frequency units into an affordable, flexible, modular, single system. An embodiment herein provides a broadband, high power combiner/divider circuit for a single transmitter. The embodiments herein provide a high performance, power combiner/divider circuit that supports the highest broadband frequency (such as 1:4 ratio) operation (e.g., 5-20 GHz, or 10-40 GHz) for high power amplifiers (hundreds of Watts). The embodiments herein provide for partitioning the circuit into an incident even-mode section, and a reflection odd mode section. Hence, incident even-mode signals are isolated from undesirable, reflected signals caused by impedance mismatch from the combined amplifiers. This results in providing efficient power division/combining (low signal loss) over broad frequency band. 
         [0033]    It is desirable to maintain the simplicity of the original Gysel structure (with its low loss, due to low impedance, lines) while introducing the minimum number of coupled lines. The embodiments herein may provide a coupled-Gysel, which utilizes a single coupled-line to significantly extend the bandwidth without increasing the insertion loss. Moreover, simulations and measurements are presented according to the embodiments herein for two cases: a 2.5-8 GHz (105% fractional bandwidth) combiner/divider with 0.1 dB loss, and a 3.4-10.2 GHz (100% fractional bandwidth) combiner/divider with 0.2 dB loss. This is one of the largest bandwidth demonstrated for a power combiner/divider. In the embodiments herein, the high bandwidth is accomplished while maintaining low RF loss and design simplicity. 
         [0034]    An embodiment herein provides using a single coupled line segment in the design of a divider/combiner. Significant improvement in bandwidth is realized in the embodiments herein, while maintaining low-loss, ease of design, and flexibility. Referring now to the drawings, where similar reference characters denote corresponding features consistently throughout the figures, there are shown exemplary embodiments. 
         [0035]      FIGS. 1A through 1C  illustrate a known Gysel combiner/divider circuit  100 , which is used as a framework circuit in accordance with the embodiments herein.  FIG. 1A  is a schematic diagram illustrating a Gysel combiner/divider circuit  100 .  FIG. 1B , with reference to  FIG. 1A , is a schematic diagram illustrating the even mode equivalent circuit of the Gysel combiner/divider circuit  100 .  FIG. 1C , with reference to  FIGS. 1A through 1B , is a schematic diagram illustrating the odd mode equivalent of the Gysel combiner/divider circuit  100 . The even mode of the circuit  100  refers to the equivalent circuit when it is excited with an in-phase excitation signal. The odd mode of the circuit  100  refers to the equivalent circuit when it is excited with an out-of-phase excitation signal. From port  1 , the signal divides equally (due to symmetry) forming an even mode which travels towards ports  2  and  3 . Any of the ports  1 ,  2 , and  3  may function as an input port and as an output port. For example, when the circuit  100  is used as a divider, port  1  is an input, and port  2  and port  3  are outputs. When the circuit  100  is used a combiner, port  2  and port  3  are inputs and port  1  is an output. 
         [0036]    The λ/4 Z 1 -fine  105  transforms the impedances of ports  2  and  3  from 50Ω to 100Ω to obtain a good match at port  1 . Additionally, the even mode sees a virtual open circuit at C which is transformed by the λ/4 Z 3 -line  107  into a short circuit at B 1  and B 2 . This, in turn, gets transformed by the λ/4 Z 2 -lines  110  into an open circuit at A 1  and A 2 . Hence, the even mode, at ports  2  and  3 , sees a 50Ω port impedance in parallel with an open circuit and it exits at ports  2  and  3 . 
         [0037]    On the other hand, the odd mode entering ports  2  and  3  sees a virtual short at D which is transformed into an open circuit by the λ/4 Z 1 -fine  105 . Meanwhile, the odd mode sees a virtual short at C which is transformed into an open circuit by the λ/4 Z 3 -line  107 . As such, the odd mode travels completely through the Z 2 -line  110  and gets directed towards, and absorbed by the resistors  114 . This happens perfectly at the center frequency, f o . The basic idea is that it is desirable for the even mode (entering port  1 ) to see a high impedance to the right of A 1  and A 2 , and the odd mode to see a low impedance to the right of A 1  and A 2 . This is achieved, in the Gysel combiner/divider circuit  100 , through the virtual opens/shorts and the associated λ/4 transformations. 
         [0038]    The bandwidth can be improved if the impedances of the odd/even modes can be controlled independently. At the same time, it is desirable to preserve the simplicity of the design and its low loss features. 
         [0039]      FIG. 2A , with reference to  FIGS. 1A through 1C , is a schematic diagram of a combiner/divider circuit  200  according to an embodiment herein. In an embodiment herein, the combiner/divider circuit  200  may be a coupled-Gysel circuit that replaces the Z 2 -lines  110  with a single coupled line  210 . Replacing the other lines (Z 1   105  and Z 3   107 ) with coupled lines increases complexity/loss is possible, however, doing so adds negligible benefits.  FIG. 2B , with reference to  FIGS. 1A through 2A , is a schematic diagram illustrating the even mode equivalent circuit  250  of the combiner/divider circuit  200  according to an embodiment herein.  FIG. 2C , with reference to  FIGS. 1A through 2B , is a schematic diagram illustrating an odd mode equivalent circuit  270  of the combiner/divider circuit  200 , according to an embodiment herein. 
         [0040]    In an embodiment herein, the even mode equivalent circuit  250  includes a Zeven  252 . In an embodiment herein, the odd mode equivalent circuit  270  includes a Zodd  272 . Since the even mode should see an open circuit to the right of A 1  and A 2 , in an embodiment herein Zeven is chosen to be as large as possible. 
         [0041]    The odd mode sees a shorted (at D) λ/4 Z 1 -fine in parallel with the Zodd  272 . Choosing a Zodd  272  equal to 50Ω gives a perfect match to the odd mode at f o , as expected, according to an embodiment herein. Choosing Zodd  272  greater than 50Ω is disadvantageous as it directs more energy towards the Z 1 -fine. Choosing Zodd  272  less than 50Ω reduces the match at f o  at the expense of a larger bandwidth. Choosing Zodd  272  between 25-50Ω increases the bandwidth while maintaining reasonable isolation (&gt;10-30 dB) across the band. 
         [0042]      FIGS. 3A and 3B , with reference to  FIGS. 1A through 2C , are diagrams illustrating results according to embodiments herein.  FIGS. 3A and 3B  illustrate the scattering parameter (S-parameter) of the combiner/divider circuits  100  and  200  versus frequency according to an embodiment herein.  FIG. 3A  illustrates S-parameter S 11  on the left axis, and S 21  on the right axis for the combiner/divider circuit  100  (in dotted lines) and for the combiner/divider circuit  200  (in solid lines).  FIG. 3B  illustrates S 22  and S 32 , both on the left axis, for the combiner/divider circuit  100  (in dotted lines) and for the combiner/divider circuit  200  (in solid lines). 
         [0043]    Assuming a center frequency of 10 GHz,  FIGS. 3A, and 3B  show a comparison between the combiner/divider circuit  100  and the combiner/divider circuit  200  where Zeven  252 =250Ω, and Zodd  272 =25Ω were used. If bandwidth is defined as a 1 dB drop in insertion loss, then the combiner/divider circuit  100  covers 7-13 GHz (60% fractional bandwidth), and the combiner/divider circuit  200  covers 3.3-16.7 GHz (133% fractional bandwidth). If bandwidth is defined by a minimum of 10 dB isolation, and input/output insertion loss, then the combiner/divider circuit  100  covers 7.12-12.88 GHz (57% fractional bandwidth), and the combiner/divider circuit  200  covers 4.95-15.05 GHz (101% fractional bandwidth). 
         [0044]    The embodiments herein provide implementations and test results of a 2.5-8 GHz combiner/divider circuit and a 3.4-10.2 GHz combiner/divider circuit.  FIG. 4 , with reference to  FIGS. 1A through 3B , is a diagram illustrating the layout of the fabricated 2.5-8 GHz combiner/divider  400  according to an embodiment herein. The fabricated combiner divider  400  may include the ports  1 ,  2 , and  3  (referring to the ports in  FIG. 2A ), impedance lines  407  (corresponding to the λ/4 Z 3 -line  107  in  FIG. 2A ), impedance lines  405  (corresponding to the λ/4 Z 1 -fine  105  in  FIG. 2A ), and resistors  414  (corresponding to the resistors  114  in  FIG. 2A ). In an exemplary embodiment herein, the combiner/divider  400  measures 0.2″×0.6″ only. In an embodiment herein, the coupled line  210  is implemented using two narrow microstrip lines  402  with a 3 mil width and a 2.1 mil gap (should support about 300 Watts continuous wave (CW) before air breakdown) and equivalent Zeven  252  and Zodd  272  impedances are Zeven=150Ω, and Zodd=40Ω, respectively. In other embodiments, instead of microstrip lines, the coupled line  210  might include a pair of striplines, co-planar waveguide lines or similar transmission line element(s). 
         [0045]      FIG. 5 , with reference to  FIG. 1A through 4 , is a graph illustrating the measured performance of the combiner/divider  400 , along with the simulation results, according to an embodiment herein. The bandwidth based on 1 dB insertion loss is 2.5-8 GHz (105% fractional bandwidth), and the insertion loss in the center of the band is 3.1 dB; hence the divider has 0.1 dB of loss. As illustrated by  FIG. 5 , close agreement between the simulation and measurement is observed. One of the contributing factors to the differences between the simulation and measurement results is that the surface mount technology (SMT) 50Ω termination resistors perform poorly at high frequency as their S 11  (line with circle symbols) shown in  FIG. 5 . 
         [0046]      FIG. 6 , with reference to  FIGS. 1A through 5 , is a graph illustrating the simulation and measurement for a high frequency 3.4-10.2 GHz combiner/divider, according to an embodiment herein. The bandwidth based on the 1 dB insertion loss is 3.4-10.2 GHz (100% fractional bandwidth), and the RF loss in the center of the band is 3.2 dB, where the combiner/divider&#39;s loss is 0.2 dB. As illustrated in  FIG. 5  and  FIG. 6 , close agreement between the simulation and measurement is observed. However, an important source to the differences is SMT 50Ω termination resistors. 
         [0047]      FIG. 7 , with reference to  FIGS. 1A through 6 , is a flow diagram illustrating a method  700  according to an embodiment herein. The method  700  may include partitioning ( 702 ) a combiner and divider circuit  200  into an incident even mode section  250  and a reflection odd mode section  270 ; and isolating ( 704 ) an incident even-mode signal from a reflected odd-mode signal such that the incident even-mode signal travels in a different path from the reflected odd-mode signal. 
         [0048]    The techniques provided by the embodiments herein may be implemented on next generation radar and communication systems, where multiple systems of different frequencies can be implemented with one output transmitter. The embodiments herein may also be used in electronic warfare (EW) applications, where broadband high power signals are required, and high power agile jamming radars where high amplifiers are combined. They can also be implemented on wireless commercial communications (5 G or faster), and under adverse conditions. 
         [0049]    The embodiments herein can provide a modified coupled-Gysel combiner/divider circuit exhibiting very broadband performance and low loss due to its simplicity and flexibility. Other embodiments may similarly provide a modified coupled-Wilkinson combiner/divider as the construction and operation of the Gysel combiner/divider circuit are similar to a Wilkinson combiner/divider circuit. The embodiments herein provide a 2.5-8 GHz (105% fractional bandwidth) divider, and a 3.4-10.2 GHz (100% fractional bandwidth). The embodiments herein provide compact size for a combiner/divider that makes it suitable for MMIC implementation. MMIC implementations show improved performance as a greater range of Zeven and Zodd impedances and more precise terminating resistors can be realized. 
         [0050]    The embodiments herein provide a new architecture that enables the realization of single transmitter for multifrequency radar systems, and very broadband EW systems. Power combining of high power amplifiers at microwave frequencies is challenging because achieving broadband isolation is difficult. Conventional approaches (e.g., Wilkinson combiner, rat-race combiner, and Lange coupler combiner) have limited bandwidth and/or low power handling capability. The embodiments herein provide a combiner/divider that can handle high power and support very broadband operation. A basic premise in embodiments herein relies on incorporating transmission lines that can behave differently for the odd/even mode, such that reflected signals (odd mode) can travel in a different path from incident signals (even mode). This enables the absorption of the reflected odd-mode signals over a broadband in grounded isolation resistors. The isolation resistors are not assumed to be electrically small herein. Hence, large, high-power resistors can be employed without performance degradation. 
         [0051]    The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.