Abstract:
A pulse width modulator (PWM) control system for a power converter achieves a fast transient response and low steady-state jittering. The control system manages the ADC sample timing to reduce noise susceptibility, and the ADC includes a regulation bin or dead band to minimize large phase corrections and thus eliminate limit cycling. The PWM module includes a dithering circuit to accumulate fractional PWM control signals to reduce period jitter by increasing the effective resolution of the pulse width modulator.

Description:
RELATED APPLICATIONS 
     This application claims the benefit, under 35 U.S.C. §119, of U.S. provisional application Ser. No. 61/096,543, filed Sep. 12, 2008, the entirety of which is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to the field of power converters controlled through digital pulse-width modulation (PWM). More particularly, the invention relates to a digital control scheme for PWM converters that enables a fast transient response to be achieved while maintaining very low steady-state jittering. 
     2. Description of Related Art 
     The use of pulse-width modulation (PWM) to control the output voltage of a power converter is well known.  FIG. 1  illustrates a simplified PWM control circuit for a buck-type power converter that is typical of the prior art. A primary voltage  106  is selectively applied to an inductor  114  by a switch  108 . When the switch  108  is closed, the diode  110  is reverse biased, and the current through the inductor  114  rises linearly as it stores magnetic energy. When the switch  108  is opened, the inductor energy is discharged to the output  112  as the inductor&#39;s magnetic field collapses. As the switching cycle is repeated, the output voltage thus achieves a level that is related to the input voltage  106  and is dependent on the duty cycle of the switch  108 . For a buck conversion circuit such as that shown in  FIG. 1 , the output voltage, V out , is related to the input voltage V in  by the expression V out =V in ×D, where D is the duty cycle, or the fraction of the switching period during which the switch is closed. In other words, the output voltage level is set by controlling the duty cycle of the switch  108 . 
     Controlling the duty cycle of switch  108  can be performed by an analog PWM control loop as illustrated in  FIG. 1 . The output voltage  112  is scaled and compared to a desired reference voltage  102 , and an error voltage signal  116  is produced, reflecting the deviation of the output voltage  112  from the desired regulation point  102 . The error voltage is then compared with a periodic ramp waveform  104 , and the resulting PWM voltage is used to drive the switch  108 . 
       FIG. 2  depicts the voltage ramp waveform  202 , an error voltage  204 , and the resulting PWM waveform  206  plotted as a function of time  208 . In this example, the error voltage  204  is relatively low compared to the center of the ramp voltage  202 , resulting in a PWM waveform  206  exhibiting a relatively large duty cycle that will cause the output voltage to rise, reducing the error voltage. While this example is described with respect to a particular buck converter topology, the same principles are employed for other types of switched power converters. 
     Moving from analog to digital PWM control systems provides a number of advantages including in situ programmability to fit a wide variety of applications, expanded control functionality, and adaptive control algorithms, among others.  FIG. 3  is a simplified block diagram, typical of the prior art, of a power converter employing a digital PWM control loop. A switching converter  304  operates in a manner similar to the circuit of  FIG. 1  to convert an input voltage  302  to an output voltage  306 . The output voltage  306  is then digitized by an analog-to-digital converter (ADC)  308  to produce a digital output voltage sample  324 . This digital output voltage sample is subtracted from a digital reference sample  312  to create a digital error sample  314 . The error sample is processed by a digital compensator filter  316 , which generally has a proportional-integral-differential (PID) character, to produce a digital control signal  318  that drives a digital PWM circuit, generally implemented as a digital counter or as a mixed-signal device. The PWM output waveform  322  is then used to drive the switching element of the switching converter  304  to provide closed-loop control of the output voltage  306 . The digital nature of the compensator  316  provides flexibility in the filtering operation that cannot be achieved in a purely analog system. In addition, the digital PWM circuit  320  is programmable and allows the converter to be used in a variety of applications. 
     However, digital control systems also raise certain performance issues that stem from the quantization of time and voltage amplitude. In particular, the resolution of output voltage control depends on the ratio of the PWM switching frequency to the sampling clock of the system. Measured in number of bits, the resolution is given by Log 2 (T SW /T DPWM ), where T SW  is the switching period of the digital PWM circuit and T DPWM  is the clock period used to implement the digital PWM. In typical point-of-load applications, the switching frequency can be as high as one megahertz, and the input-to-output voltage ratio can be ten, as in a typical 12 V-to-1.2 V conversion system. Given 1% regulation requirements, the PWM clock frequency is thus required to be in the range of several gigahertz. Implementing such a high-frequency clock adds complexity, power consumption, and cost and is thus undesirable. 
     An additional performance issue raised by digital PWM systems is a phenomenon known as limit cycling. When a digital PWM circuit does not have sufficient resolution, periodic low-frequency oscillation can be observed at the output. This low-frequency oscillation can result in excessive output voltage ripple, often in the range of a few percent, which is unacceptable for many applications. 
     A lack of sufficient resolution in the digital PWM can result in another phenomenon called jittering. Without sufficient DPWM resolution, the output error voltage cannot remain within the zero-error bin. When the error voltage is not inside the zero-error bin, a duty-cycle correction command will be initiated, resulting in a duty-cycle change. This duty-cycle change, observed at the phase node, is the jittering of the system. This measure is used by many customers to decide whether or not the power stage is in a good state of regulation. High jittering means the controller needs to employ frequent, large duty-cycle corrections, suggesting that the system is not in a very stable condition. In a system with lower jittering, the controller must make only small duty-cycle corrections, keeping the output voltage in a state of tight regulation. 
     Accordingly, it would be desirable to provide a digital PWM control system and method that addresses the issues discussed above. In particular, it would be desirable to provide a method of reducing phase-node jittering and output voltage ripple without requiring a very-high-resolution digital PWM circuit and very high clock rates. And it would be useful to decouple the transient response of the system from the jittering such that a fast transient response could be achieved without increasing the phase-node jittering. Finally, it would be useful to reduce the susceptibility of the digital PWM control system to noise within the regulation bin surrounding the operating point at which the output voltage is very close to its control value. 
     SUMMARY OF THE INVENTION 
     An embodiment of a power conversion system in accordance with the present invention includes a switching converter, such as a buck converter, boost converter, or other switching converter known in the art, including an input voltage port, an output voltage port, an output voltage filter, and at least one switch for selectively connecting the input voltage port to the output voltage filter. When the switch is opened and closed periodically, the output voltage takes on a value that is related to the input voltage and the duty cycle of the switch. 
     The power conversion system also includes an analog-to-digital converter (ADC) for sampling the output voltage of the switching converter. As described in more detail below, the ADC exhibits a non-uniform response function such that it includes a regulation bin or dead band surrounding the null output region so that a small change in the output voltage of the switching converter will not result in a change to the digital output of the ADC. This eliminates the problem of limit cycling in the power conversion system as discussed in more detail below. In some embodiments in accordance with the present invention, the width of the regulation bin is programmable. In one specific embodiment, the width of the regulation bin is set to extend from −4 millivolts to +4 millivolts. 
     An embodiment of a power conversion system in accordance with the present invention further includes an error circuit configured to calculate an error signal by taking a difference of the digital output of the ADC and a reference voltage. This error signal is sent to a compensator filter that processes the error signal to generate a pulse width modulation (PWM) control signal. In some embodiments of the power conversion system in accordance with the present invention, the compensator has a proportional, integral, and differential (PID) characteristic response function. This response function is described in some embodiments by the relation d[n]=d[n−1]+b 0 *e[n]−b 1 *e[n−1]+b 2 *e[n−2]. In this expression, d[n] is the PWM control signal at a current sample time t, d[n−1] is the PWM control signal at a sample time t−1, e[n] is the error signal at the current sample time t, e[n−1] is the error signal at the sample time t−1, e[n−2] is the error signal at a sample time t−2, b 0  is a first filter coefficient, b 1  is a second filter coefficient, and b 2  is a third filter coefficient. In one particular embodiment in accordance with the present invention, the filter coefficients take on the following values: b 0 =1, b 1 =1.8125, and b 2 =0.8203125. 
     The power conversion system further comprises a PWM module that is configured to receive the PWM control signal and to produce an output PWM waveform with a variable duty cycle that is used to drive the switch of the switching converter. The duty cycle of the PWM waveform is controlled by a numerically controlled oscillator or similar circuit in response to the PWM control signal. The PWM module further generates a timing strobe that is sent to the ADC to control the timing instant at which it samples the output voltage. In order to reduce ADC noise, the sampling instant is chosen to occur when the switch of the switching converter is in the off state. In some embodiments in accordance with the present invention, the sampling instant is further constrained to occur in the instant before the switch of the switching converter is turned on. 
     In some embodiments of a power conversion system, the PWM module is further adapted to include a dithering circuit to prevent large phase correction jumps from occurring when the PWM control signal includes a fractional portion. The PWM control signal will generally include a fractional portion when the resolution of the compensator filter is greater than that of the numerically controlled oscillator or similar circuit generating the PWM waveform. In order to capture the fractional portion of the PWM control signal, the dithering circuit includes a remainder accumulator that receives the fractional portion of the PWM control signal and accumulates it from sample to sample to create a rolling remainder sum. When the rolling remainder sum reaches or exceeds one, the duty cycle of the current PWM pulse is increased by one least-significant bit (LSB) time. It may be the case that the fractional portions of the PWM control word do not evenly add to an integer value after several cycles. In this case, some embodiments of the dithering circuit will simply retain the fractional portion of the rolling sum and discard the integer portion that was used to correct the duty cycle of the PWM waveform. This is equivalent to replacing the rolling sum with the rolling sum minus one whenever the rolling sum reaches or exceeds one. In other embodiments, the rolling sum may be reset to zero whenever the rolling sum reaches or exceeds one. 
     While the PWM control system of the present invention has been described above in the context of a voltage conversion system, it is equally applicable to other closed-loop control systems. Those skilled in the art will realize other applications and benefits of the invention described herein by a study of the detailed description below and the attached drawings, which will first be described briefly. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a typical buck converter controlled by an analog PWM circuit; 
         FIG. 2  is a diagram illustrating the waveform of a ramping circuit and the resulting PWM waveform; 
         FIG. 3  is a block diagram of a typical power converter employing a digital PWM control circuit; 
         FIG. 4  is a plot of a phase-node waveform and an output voltage of a digital PWM power converter circuit in accordance with an embodiment of the present invention; 
         FIG. 5  is a block diagram of an embodiment of a compensator filter used to drive a digital PWM synthesizer in accordance with the present invention; 
         FIG. 6  is a plot of several cycles of a PWM waveform illustrating a dithering technique in accordance with an embodiment of the present invention; and 
         FIG. 7  is a plot of a non-uniform ADC characteristic in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An embodiment of a digital PWM control system in accordance with the present invention provides low steady-state jittering that is limited to one cycle of the system clock while including a digital PWM circuit that is relatively low resolution and capable of being implemented using standard digital design and fabrication techniques. It also employs a non-uniform ADC characteristic that eliminates limit cycling and allows programmability of the regulation bin. It also includes a dithering function that effectively increases the resolution of the PWM circuit. 
     In one embodiment of a digital PWM system in accordance with the present invention, the sampling noise associated with measuring the output voltage of the power converter with the ADC is minimized by setting the sampling window strobe to occur just prior to the rising edge of the phase-node signal of a buck converter.  FIG. 4  illustrates how this sampling instant is selected. A representative phase-node waveform  408  comprises a train of pulses adapted to turn on and off the high-side FET in a buck converter. The voltage output trace  406  of the power converter shows increased noise during the time that the phase-node waveform is high. The time region of increased noise is indicated by the highlighted box  402 . A power converter in accordance with the present invention is adapted to prevent ADC samples of the output voltage from being acquired during this enhanced noise interval. Instead, the sampling is timed to occur during the quiet interval highlighted at  404 . Much of the circuit noise is thus eliminated from the ADC samples, leading to a cleaner calculation of the error signal fed into the compensator. 
     An embodiment of a compensator filter in accordance with the present invention is depicted in  FIG. 5 . An error sample  503  is processed by a digital filter to produce an output  518  suitable for driving the digital PWM circuit. As shown in  FIG. 5 , an example of such a filter includes two input-sample-delay stages  510  and  512  and three multipliers  504 ,  506 , and  508 , configured to scale the current error sample, the previous error sample, and the two-sample-previous error sample by programmable coefficients b 0 , −b 1 , and b 2 , respectively. The scaled error samples are then combined, along with the previous output sample to produce an output  518  that can be described as follows:
 
 d[n]=d[n− 1]+ b   0   *e[n]−b   1   *e[n− 1]+ b   2   *e[n− 2],
 
where e[n] is the current error sample, e[n−1] and e[n−2] are the error samples from one sample time and two sample times previously, respectively, d[n] is the current output sample, and d[n−1] is the previous output sample. Adjusting the coefficients b 0 , b 1 , and b 2  allows different transient responses of the compensator filter to be achieved. Note that multipliers  504 ,  506 , and  508  can be implemented as true multipliers for maximum flexibility in coefficient selection, or they can be implemented with a look-up table to conserve computation resources.
 
     The output d[n] is a measure of the calculated PWM duty cycle to be applied to the power converter in order to move the output voltage toward the regulation point. It should be appreciated that the resolution of the compensator calculation may be greater than that of the PWM synthesis circuit and thus may include a portion corresponding to a fraction of a least-significant bit of the PWM circuit. Prior art systems tend to address this problem by increasing the PWM resolution. However, this requires either a digital system with a clock frequency in the range of several gigahertz, or a mixed-signal system with a very-high-resolution DPWM. These techniques add complexity and often push the design of the PWM synthesizer to faster and more exotic semiconductor technologies that can increase price and power consumption and reduce yield. 
     By contrast, an embodiment of a digital PWM control system in accordance with the present invention employs a dithering technique that effectively increases the resolution of the DPWM while maintaining an affordable operating frequency and a purely digital design. The dithering technique includes a mechanism for retaining the fractional portion of the duty cycle calculated by the compensator filter. For example,  FIG. 6  illustrates this technique for representing a PWM duty cycle value of 34.25 units using a PWM synthesizer with a least-significant-bit value of one unit. In this case, the compensator calculates an ideal PWM value of 34.25. When this value is applied to the PWM synthesizer, the 0.25 fractional portion is retained in a remainder accumulator circuit, and the value of 34 is applied to the PWM synthesizer which then generates a pulse  602  having a duty cycle of 34. During the following cycle, an additional 0.25 remainder is accumulated, resulting in a retained value of 0.5, and the value of 34 is again applied resulting in a second pulse  604  of duty cycle  34 . The process is again repeated resulting in a third pulse  606  of duty cycle  34  and a remainder accumulator value of 0.75. Finally, during the fourth cycle, the remainder accumulator value reaches 1.0, and the value sent to the PWM synthesizer is 35, resulting in a pulse  608  with a slightly larger duty cycle of 35, as illustrated by the extra pulse length depicted at  612 . The remainder accumulator is cleared, and the following pulse  610  again has a duty cycle of 34. The result of this process is that an average duty cycle of 34.25 is obtained with predictable phase-node jittering of just one sampling clock cycle, as illustrated at  612 . Thus the effective resolution of the PWM modulator is increased by two bits (four states) without increasing the clock frequency of the PWM circuit. The remainder accumulator can be implemented using digital design techniques well-known in the art such as by implementing a simple digital accumulator circuit, by using a microprocessor, or by any other suitable technique. By making the jittering predictable and constraining its magnitude to one clock cycle, limit cycling due to insufficient PWM resolution is eliminated because the PWM synthesizer synthesizes the precise calculated value (on average) rather than relying on a very-high-frequency digital implementation. 
     While the dithering process has been described with respect to a fractional value of one quarter, resulting in one of every four pulses being slightly wider than the others, other fractional values can be similarly accommodated within the scope and spirit of the present invention. For example, a fractional value of one eighth would result in every eighth pulse&#39;s being wider by one clock cycle. Similarly, a fractional value of ⅔ would result in every third pulse&#39;s being one clock cycle narrower than the others. In some cases, the fractional portions after several cycles will not add exactly to one. In such a case, the duty cycle of the PWM waveform will be increased by one unit at the sample time at which the remainder accumulator rolling sum reaches or exceeds one. In one embodiment in accordance with the present invention, when this happens, the remainder accumulator will be reset to zero. In another embodiment in accordance with the present invention, the value of the remainder accumulator will be replaced by the value of the remainder accumulator minus one, i.e., only the fractional portion will be retained. 
     In all cases, the period jitter is constrained to be just one clock cycle, which is in many cases much smaller than the jitter that would result if a truncated duty cycle value were applied to the PWM processor and the loop were allowed to close through the ADC and compensator filter. For example, for a reasonable clock frequency of 200 MHz, well within the capabilities of standard digital processes, the jitter resulting from a system in accordance with the present invention would be limited to 5 ns, which is significantly lower than typical prior art systems. 
     However, even when the dithering technique described above is applied, ADC quantization noise can still produce unwanted jittering and corresponding output voltage noise. To solve this problem, an embodiment of a PWM control system in accordance with the present invention employs a non-uniform ADC characteristic function that defines a regulation bin spanning the region near which the error voltage is zero and inside which the ADC response is defined to be zero.  FIG. 7  depicts an exemplary ADC characteristic in accordance with the present invention that illustrates the operation of the regulation bin. The analog error voltage of the converter is plotted along the horizontal axis  704 , and the corresponding digital output of the ADC is plotted along the vertical axis  702 . Trace  708  relates the analog error voltage to the digital ADC output, and except for the region near zero, it exhibits a linear relationship. But within the regulation bin  706  surrounding zero, the ADC digital output is mapped to zero rather than following the analog error voltage. This has the effect of creating a zero-error bin in the output voltage when it is very close to the reference value. The zero-error bin not only prevents small variations in the output voltage from triggering changes in the PWM synthesizer, but also makes possible the one-clock-cycle jittering of the PWM signal within the zero-error bin. If the output voltage varies beyond the regulation bin, the ADC output feeds a normal error voltage into the compensator. It should be appreciated that the size of the regulation bin is programmable and can be adjusted according to the requirements of the application. 
     One embodiment of a digital PWM control system in accordance with the present invention is implemented using an input voltage of 12 V, an output voltage of 2 V, a clock frequency of 200 MHz, and a switching frequency of 500 kHz. The compensator filter function is described by the equation:
 
 d[n]=d[n− 1]+ e[n]− 1.8125* e[n− 1]+0.8203125* e[n− 2].
 
The regulation bin of the ADC response function is set to be ±4 mV, or about ±0.2% of the two-volt output voltage. Experimental results show that this system has a fast transient response with a steady-state phase-noise jittering that is limited to 5 ns, or one clock period of the DPWM, under all loading conditions.
 
     The foregoing description has disclosed several embodiments and many useful features of a novel design for a digital PWM controller that achieves low steady-state jittering without the need for a very-high-resolution digital PWM synthesizer. The selection of the error ADC sampling instant reduces noise in the error samples. A dithering scheme and a method of providing a zero-error band in the ADC eliminate the problem of limit cycling and reduce steady-state jittering to a single system clock cycle. Those skilled in the art will likely perceive other advantages and applications of the invention, and such would also fall within the scope and spirit of the present invention.