Abstract:
A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a method for fabricating a memory device, and more particularly to a method for fabricating a charge trapping memory device. 
     2. Description of the Related Art 
     In the process of fabricating a charge trapping memory device, such as a nitride charge storage device, a bottom oxide layer (BOX) is formed on a silicon (Si) substrate, and Si—O bonds are generated at the interface of the bottom oxide layer and silicon substrate as shown in  FIG. 1A . Subsequently, a buried diffusion (BD) implantation is performed through the first oxide layer to form BD regions in the substrate. After the BD implantation, a lot of silicon dangling bonds are generated at the BOX/Si interface as shown in  FIG. 1B . Afterwards, in a low-temperature metallization process, hydrogen (H) is introduced to form Si—H bonds at the BOX/Si interface as shown in  FIG. 1C . Therefore, when the band-to-band tunneling hot hole (BTBT-HH) erase is performed on the nitride charge storage device  100  as shown in  FIG. 1D , Si—H bonds at the BOX/Si interface are broken by hot holes (energy carried is about 4.7 eV), and an interface trap is generated at the interface of the BOX and the channel to carry negative charges Q IT . 
     Referring to  FIG. 1E , an I-V curve diagram of the device  100  is shown. Initially, there is no program-erase operation on the device  100 , and the device  100  has an I-V curve C 1 . After program, the device  100  increases its threshold voltage V T  to have an I-V curve C 2 . In a reliability test, the programmed device  100  is baked at a temperature of 150□ for about 24 hours to have an I-V curve C 3 . It can be seen from  FIG. 1E  that the I-V curve C 3  after baking is very similar to the I-V curve C 2  before baking, and thus the initial device  100  is stable. However, when the device  100  is programmed and erased by 10K cycles, the 10K-cycle programmed device  100  changes to have an I-V curve C 4  whose slope is smaller than the curve C 2  due to appearance of large amount of charges Q IT . When the 10K-cycle programmed device  100  is baked for reliability test, the device  100  turns up to have a new I-V curve C 5  whose threshold voltage V T  is smaller than that V T  of the curve C 2  for an initial state by a value ΔV T . 
     As shown in  FIG. 1F , when the cycle number of erase-program is increased, such as from 0 to 100K, the device  100  has an increasing sub-threshold swing S W , such as from 229.5 to 427 mV/dec due to the generation of the charges Q IT  at the BOX/Si interface whose density is increased from 0 to 1.6E−7coul/cm 2 , and the V T  difference between program and erase state contributed by Q IT  is also increased from 0 to 41.9%. Therefore, the interface trap generation leads to S W  degradation and thus reduces reliability of nitride charge storage products. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the invention to provide a method for fabricating a charge trapping memory device. A rapid thermal nitridation (RTIN) process is performed on the BOX layer and silicon substrate after BD implantation to form Si—N bonds at the BOX/Si interface. Therefore, the interface trap generation can be suppressed in a subsequent process, thereby improving reliability of the charge trapping memory device. 
     The invention achieves the above-identified object by providing a method for fabricating a charge trapping memory device. The method includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer. 
     Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a diagram of a BOX/Si interface of a conventional nitride charge storage device in an initial process. 
         FIG. 1B  is a diagram of a BOX/Si interface of a conventional nitride charge storage device after BD implantation. 
         FIG. 1C  is a diagram of a BOX/Si interface of a conventional nitride charge storage device in a metallization process. 
         FIG. 1D  is a diagram of the conventional nitride charge storage device forming interface trap. 
         FIG. 1E  is an I-V curve diagram of a conventional nitride charge storage device. 
         FIG. 1F  is a comparison table of the sub-threshold swing S W , the density of charges Q IT , and the V T  difference by Q IT  of a conventional nitride charge storage device for various erase-program cycle number. 
         FIG. 2A  to  FIG. 2J  are a process for fabricating a charge trapping memory device according to a preferred embodiment of the invention. 
         FIG. 3  is a diagram of an oxide/silicone interface with Si—N bonds. 
         FIG. 4  is an I-V curve diagram of the nitride charge storage device in  FIG. 2J . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 2A  to  FIG. 2J , a process for fabricating a charge trapping memory device according to a preferred embodiment of the invention is shown. For example, the charge trapping memory device is a nitride charge storage device, which performs an erase operation by BTBT-HH. First, in  FIG. 2A , a substrate  200 , such as a P-type silicone substrate, is provided. Next, in  FIG. 2B , a first oxide layer  210 , such as made of silicone dioxide (SiO 2 ) is formed on the substrate  200 . Then, in  FIG. 2C , a photoresist layer  220  is formed on the first oxide layer  210  and in  FIG. 2D , the photoresist layer  220  is exposed and etched to define a number of BD lines  230  on the first oxide layer  210 . In  FIG. 2C , only one BD line is shown for convenience of illustration. Following that, in  FIG. 2E , a BD implantation is performed on the substrate  200  through the BD lines  230  to form a number of BD regions  240 , such as n+ regions for bit lines (BL), in the substrate  200 . Similarly, only one BD region  240  is shown in  FIGS. 2E˜2I  for convenience of illustration. As mentioned in prior art, lots of silicone dangling bonds will be generated at the interface of the first oxide layer  210  adjacent to the BD region  240 . 
     Afterwards, in  FIG. 2F , the etched photoresist layer  220  is stripped from the first oxide layer  210  by dry etching, wet etching, or ISSG method, and the first oxide layer  210  is further cleaned by a remote chemical analysis cleaning (RCA CLN) process (published by Kern and Puotinen in 1970) to completely remove photoresist residue. Next, in  FIG. 2G , a RTN process is performed to nitridize the interface of the first oxide layer  210  and the substrate  200  such that the above-mentioned silicone dangling bonds can combine with nitrogen (N) to form strong Si—N bonds as shown in  FIG. 3 . For example, the RTN process is performed to nitridize the oxide/silicone interface by using NO, N2O or NH3 gas for at least 10 sec under a temperature of 750□-1050□. Preferably, the RTN process is performed for about 1 minute under a temperature of 975□. Therefore, in the RTN process, the oxide/silicone interface has enough time to form the Si—N bonds under high temperature, and the heating time for the substrate  200  is not too long to expand the BD regions  240 . 
     Following that, in  FIG. 2H , a charge trapping layer  250 , such as made of silicone nitride, hafnium oxide, or aluminum oxide, is formed on the first oxide layer  210 , and in  FIG. 2I , a second oxide layer  260 , such as made of silicone dioxide, is formed on the charge trapping layer  250 . Finally, a nitride charge storage device  200  is generated when a poly-silicone layer  270  for a gate (G) electrode is formed on the second oxide layer  260   a , and a charge trapping memory device  200  is formed with a gate  270 , a source  240 , a drain  240 , and an insulating stack of the layers  210 ,  250 ,  260  as shown in  FIG. 2J . 
     Owing that the strong Si—N bonds are formed at the oxide/silicone interface in the RTN process as shown in  FIG. 3 , when the BTBT-HH erase is performed on the nitride charge storage device  200  as shown in  FIG. 2J , Si—N bonds at the oxide/silicone interface are scarcely broken by hot holes (energy carried is about 4.7 eV), and the prior-art interface trap generation can be effectively suppressed and thus reliability of the nitride charge storage device  200  can be higher than prior art. 
     Referring to  FIG. 4 , an I-V curve diagram of the nitride charge storage device  200  is shown. Initially, there is no program-erase operation on the nitride charge storage device  200 , and the nitride charge storage device  200  has an I-V curve C 1 ′. After programming the initial device, the nitride charge storage device  200  has an I-V curve C 2 ′, and after 10K cycles of erase and program, the programmed nitride charge storage device  200  increases its threshold voltage V T to have an I-V curve C 3 ′. It can be seen from  FIG. 4  that the I-V curve C 3 ′ has smaller SW degradation than that value of the prior-art curve C 4  in  FIG. 1E , and thus the RTN nitride charge storage device  200  can have higher reliability than the prior-art nitride charge storage device  100  after a number of erase-program cycles. 
     In the method for fabricating a charge trapping memory device disclosed by the above-mentioned embodiment of the invention, a RTN process is performed to nitridize the oxide/silicone interface after the BD implantation and form strong Si—N bonds at the interface. Therefore, the interface trap generated in BTBT-HH erase can be reduced and the reliability of the nitride charge storage device can be improved. 
     While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.