Abstract:
An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims the benefit of Korean Patent Application No. 10-2009-0069494, filed on Jul. 29, 2009, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. 
     BACKGROUND 
     The inventive subject matter relates to an output driver of an electronic circuit, and more particularly, to an output driver operable over a wide range of voltages. 
     In general, there exist devices operating at various supply voltages in an electronic circuit. Accordingly, building an input/output interface circuit requires an output driver that can normally operate over a wide range of supply voltages. 
     SUMMARY 
     Some embodiments of the inventive subject matter provide an output driver including a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage. 
     In some embodiments, the pull-up circuit may be coupled between the output terminal and the power supply node and the drive circuit may include a PMOS transistor having a source terminal coupled to the power supply node, a drain terminal coupled to the first terminal of the capacitor and a gate terminal configured to receive a signal complementary to the drive signal. In further embodiments, the pull-up circuit is coupled between the output terminal and a first power supply node and the drive circuit includes a PMOS transistor having a source terminal coupled to a second power supply node, a drain terminal coupled to the first terminal of the capacitor and a gate terminal configured to receive a signal complementary to the drive signal. The second power supply node may have a voltage less than a voltage of the first power supply node. 
     In some embodiments, the pull-up circuit may include a first PMOS transistor having a source terminal coupled to a first power supply node and a second PMOS transistor having a source terminal coupled to a drain terminal of the first PMOS transistor and a drain terminal coupled to the output terminal. The capacitor may include a first capacitor having a first terminal coupled to a gate terminal of the first PMOS transistor and a second terminal configured to receive a first drive signal and a second capacitor having a first terminal coupled to a gate terminal of the second PMOS transistor and a second terminal configured to receive a second drive signal. The drive circuit may include a third PMOS transistor having a source terminal coupled to the first power supply node, a drain terminal coupled to the first terminal of the first capacitor and a gate terminal configured to receive a signal complementary to the first drive signal and a fourth PMOS transistor having a source terminal coupled to a second power supply node, a drain terminal coupled to the first terminal of the second capacitor and a gate terminal configured to receive a signal complementary to the second drive signal. The second power supply node may have a voltage less than a voltage of the first power supply node. 
     Some embodiments of the inventive subject matter provide an output driver that can operate over a wide range of supply voltages and protect devices against overvoltage. 
     The inventive subject matter also provides an output driver that can operate over a wide range of supply voltages and perform a tolerant function and a fail-safe function. 
     According to an aspect of the inventive subject matter, there is provided an output driver operable over a wide range of voltages, the output driver including: pull-up/pull-down circuits connecting one or more P-channel transistors between a first supply voltage terminal and an output terminal in a cascode configuration, connecting one or more N-channel transistors between the output terminal and a ground terminal in a cascode configuration, and determining a voltage of the output terminal according to voltages of signals applied to gate terminals of the one or more P-channel transistors and the one or more N-channel transistors; and a gate voltage adjusting circuit connecting at least one capacitor between a terminal to which a first signal swinging between a first voltage and a second supply voltage that is lower than a first supply voltage is applied and the gate terminals of the one or more P-channel transistors included in the pull-up/pull-down circuits, and changing the first signal to a second signal swinging between the first voltage and a second voltage that is higher than the first voltage and lower than the first supply voltage or to a third signal swinging between the second supply voltage and a third voltage that is higher than the first voltage and lower than the second supply voltage based on charge sharing between internal capacitors of the one or more P-channel transistors and the capacitor to apply the second signal or the third signal to the gate terminals of the one or more P-channel transistors included in the pull-up/pull-down circuits. 
     The gate voltage adjusting circuit may include: a first capacitor connected between a terminal to which the first signal is applied and a first node; and a P-channel transistor having a first terminal connected to the first supply voltage source terminal, a second terminal connected to the first node, and a gate terminal to which a fourth signal swinging between the first supply voltage and a fourth voltage that is higher than the first voltage and lower than the first supply voltage is applied, wherein the first node is connected to the gate terminals of the one or more P-channel transistor included in the pull-up/pull-down circuits, and the fourth signal and the first signal complementary. 
     The gate voltage adjusting circuit may include: a second capacitor connected between a terminal to which the first signal is applied and a second node; and a P-channel transistor having a first terminal connected to the second supply voltage source terminal, a second terminal connected to the second node, and a gate terminal to which a fifth signal swinging between the second supply voltage and a fifth voltage that is higher than the first voltage and lower than the second supply voltage is applied, wherein the second node is connected to the gate terminals of the one or more P-channel transistors included in the pull-up/pull-down circuits, and the fifth signal and the first signal are complementary. 
     The gate voltage adjusting circuit may include: a first circuit receiving the first signal to generate the first supply voltage at a third terminal when the first signal changes from the first voltage to the second supply voltage, to generate the second voltage, which is higher than the first voltage and lower than the first supply voltage, at the third terminal when the first signal changes from the second supply voltage to the first voltage, and making the third terminal float when the first signal is maintained in a direct current (DC) state; and a stabilizing circuit maintaining the third terminal at an initially set voltage in a floating state when the first signal is maintained in a DC state. 
     The pull-up/pull-down circuits may be configured such that a second supply voltage source terminal is connected to a gate terminal of at least one N-channel transistor from among the one or more N-channel transistors connected in the cascode configuration. 
     The pull-up/pull-down circuits may further include a P-channel transistor having a terminal connected to a gate terminal of at least one N-channel transistor from among the one or more N-channel transistors and a second supply voltage source terminal, and connected between a gate terminal and one terminal of the N-channel transistor connected to the second supply voltage terminal, wherein the second signal having the same phase as that of the first signal is applied to a gate terminal of the P-channel transistor further included in the pull-up/pull-down circuits. 
     The transistors may be designed to operate at the second supply voltage. The transistors may include metal oxide semiconductor (MOS) transistors. 
     According to another aspect of the inventive subject matter, there is provided an output driver operable over a wide range of voltages, the output driver including: a control signal generating circuit generating first, second, and third control signals according to an on/off state of a first supply voltage source and a second supply voltage source through current paths due to a plurality of transistors connected between a pad and a first supply voltage source terminal, wherein when both the first supply voltage source and the second supply voltage source are turned on, the first control signal generates a second supply voltage, the second control signal generates a first supply voltage, and the third control signal generates the first supply voltage if a voltage of the pad is higher than the first supply voltage and generates the same voltage as the voltage of the pad if the voltage of the pad is not higher than the first supply voltage, and when both the first supply voltage source and the second supply voltage source are turned off, each of the first and second control signals generates a voltage that is lower by an initially set voltage than the voltage of the pad, and the third control signal generates the same voltage as the voltage of the pad; pull-up/pull-down circuits connecting one or more P-channel transistors between the first supply voltage source terminal and the pad in a cascode configuration, connecting one or more N-channel transistors between the pad and a ground terminal in a cascode configuration, and determining the voltage of the pad according to voltages of signals applied to gate terminals of the one or more P-channel transistors and the one or more N-channel transistors; and a device protecting circuit including a plurality of switching units coupled to the pull-up/pull-down circuits, and preventing current from flowing to the first supply voltage source terminal from the pad when a voltage that is higher than the first supply voltage is applied to the pad or when the first supply voltage is applied to the pad in the state where the first and second supply voltage sources are turned off by turning on or turning off the plurality of switching units using the first, second, and third signals. 
     The output driver may further include a gate voltage adjusting circuit changing a first signal swinging between a first voltage and the second supply voltage that is lower than the first supply voltage to a second signal swinging between the first supply voltage and a second voltage that is higher than the first voltage and lower than the first supply voltage or to a third signal swinging between the second supply voltage and a third voltage that is higher than the first voltage and lower than the second supply voltage to apply the second signal or the third signal to the gate terminals of the one or more P-channel transistors included in the pull-up/pull-down circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Exemplary embodiments of the inventive subject matter will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a partial circuit diagram for explaining the operating principle of an output driver according to some embodiments of the inventive subject matter; 
         FIG. 2  is a complete circuit diagram of the output driver of  FIG. 1 ; 
         FIG. 3  is a circuit diagram illustrating a gate driver of the output driver of  FIG. 2 ; 
         FIG. 4  is a circuit diagram illustrating another gate driver of the output driver of  FIG. 2 ; 
         FIG. 5  is a circuit diagram illustrating a level shifter of the output driver of  FIG. 2 ; 
         FIG. 6  is a circuit diagram illustrating a stabilizing circuit of the gate driver of  FIG. 3 ; 
         FIG. 7  is a circuit diagram illustrating a stabilizing circuit of the gate driver of  FIG. 4 ; 
         FIG. 8  is a circuit diagram illustrating a circuit for generating control signals for a tolerant function and a fail-safe function of the output driver of  FIG. 2 , according to some embodiments of the inventive subject matter; 
         FIG. 9  is a circuit diagram of the output driver of  FIG. 2  which can perform a tolerant function and a fail-safe function using the control signals of  FIG. 8 ; and 
         FIG. 10  is a circuit diagram illustrating a gate driver of the output driver of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
     In order to fully understand operational advantages of the inventive subject matter and objects that may be attained by embodiments of the inventive subject matter, the accompanying drawings illustrating exemplary embodiments of the inventive subject matter and details described in the accompanying drawings should be referred to. 
     Some embodiments provide an output driver that includes devices designed to operate at a second supply voltage and can operate in a range from the second supply voltage to a first supply voltage that is higher than the second supply voltage. For example, the second supply voltage may be set to 1.8 V and the first supply voltage may be set to 3.3 V. In the drawings, the first supply voltage is denoted by VDD 1  and the second supply voltage is denoted by VDD 2 . However, the inventive subject matter is not limited thereto, and various other supply voltages may be used. For convenience of explanation, it is assumed that the first supply voltage VDD 1  is set to 3.3 V and the second supply voltage VDD 2  is set to 1.8 V. 
       FIG. 1  is a partial circuit diagram of an output driver according to some embodiments of the inventive subject matter. Metal oxide semiconductor (MOS) devices illustrated in  FIG. 1  may be designed to operate at the second supply voltage VDD 2  of 1.8 V. 
     Referring to  FIG. 1 , PMOS transistors P 0  and P 1  are connected between a first supply voltage terminal and a pad  10  in a cascode configuration, and NMOS transistors N 1  and N 0  are connected between the pad  10  and a ground terminal in a cascode configuration. The PMOS transistors P 0  and P 1  serve as pull-up transistors, and the NMOS transistors N 1  and N 0  serve as pull-down transistors. The PMOS transistors P 0  and P 1  are P-channel MOS transistors and the NMOS transistors N 1  and N 0  are N-channel MOS transistors. 
     A PMOS transistor P 3  has a drain terminal connected to a gate terminal PG 1  of the PMOS transistor P 0 , a source terminal connected to the first supply voltage terminal, and a gate terminal to which a signal, which swings between the first supply voltage VDD 1  and a voltage that is higher than a ground voltage of 0 V and lower than the first supply voltage VDD 1  and can turn on the PMOS transistor P 3 , is applied. For example, the signal applied to the gate terminal of the PMOS transistor P 3  may be a signal output from a level shifter  20  of  FIG. 3 . 
     A capacitor C 0  has a first terminal connected to the gate terminal PG 1  of the PMOS transistor P 0 , and a second terminal to which a signal that swings between the ground voltage of 0 V and the second supply voltage VDD 2  is applied as shown in  FIG. 1 . 
     The signal applied to the gate terminal of the PMOS transistor P 3  and the signal applied to the second terminal of the capacitor C 0  are complementary (i.e., one is inverted with respect to the other). 
     A PMOS transistor P 2  has a drain terminal connected to a gate terminal PG 2  of the PMOS transistor P 1 , a source terminal connected to a second supply voltage terminal, and a gate terminal to which a signal that swings between the second supply voltage VDD 2  and a voltage that is higher than the ground voltage of 0 V and lower than the second supply voltage VDD 2  and can turn on the PMOS transistor P 2  is applied. 
     A capacitor C 1  has a first terminal connected to the gate terminal PG 2  of the PMOS transistor P 1 , and a second terminal to which a signal that swings between the ground voltage of 0 V and the second supply voltage VDD 2  is applied as shown in  FIG. 1 . 
     The signal applied to the gate terminal of the PMOS transistor P 2  and the signal applied to the second terminal of the capacitor C 1  are complementary. 
     The operation of the output driver of  FIG. 1  will now be explained in detail. 
     Overvoltage can be prevented from being applied to a gate-oxide of the PMOS transistor P 1  and the NMOS transistor N 1  by applying the second supply voltage VDD 2  to the gate terminal PG 2  of the PMOS transistor P 1  and the gate terminal of the NMOS transistor N 1  near the pad  10 . However, if the second supply voltage VDD 2  is applied to the gate terminal PG 2  of the PMOS transistor P 1 , since a source-gate voltage Vsg of the PMOS transistor P 1  is determined by a potential difference between the first supply voltage VDD 1  and the second supply voltage VDD 2 , the source-gate voltage Vsg of the PMOS transistor P 1  is directly affected by a change in the first supply voltage VDD 1  and the second supply voltage VDD 2 . For example, if each of the first supply voltage VDD 1  and the second supply voltage VDD 2  has a change of ±10%, the source-gate voltage Vsg of the PMOS transistor P 1  is reduced to 0.99 V (2.97 V−1.98 V), thereby making it difficult to generate a sufficient amount of pull-up driving current. 
     For that reason, the second supply voltage terminal is not directly connected to the gate terminal PG 2  of the PMOS transistor P 1 , and a circuit including the PMOS transistor P 2  and the capacitor C 1  is used to generate a gate driving signal. 
     As described above, the signal swinging between the ground voltage of 0 V and the second supply voltage VDD 2  is applied to the second terminal of the capacitor C 1 , and the signal applied to the gate terminal of the PMOS transistor P 2  and the signal applied to the second terminal of the capacitor C 1  are complementary. 
     If the second supply voltage VDD 2  is applied to the second terminal of the capacitor C 1 , since the voltage that is higher than the ground voltage of 0 V and lower than the second supply voltage VDD 2  and can turn on the PMOS transistor P 2  is applied to the gate terminal of the PMOS transistor P 2 , the PMOS transistor P 2  is turned on and the second supply voltage VDD 2  is supplied to the gate terminal PG 2  of the PMOS transistor P 1 . 
     If the ground voltage of 0 V is applied to the second terminal of the capacitor C 1 , since the second supply voltage VDD 2  is applied to the gate terminal of the PMOS transistor P 2 , the PMOS transistor P 2  is turned off and a voltage PG 2 _LOW of the gate terminal PG 2  of the PMOS transistor P 1  becomes as follows:
 
 PG 2_LOW=[ VDD 2 −VDD 2 *C 1/( C 1 +Cg ( P 1))]  (1)
 
where Cg(P 1 ) is the value of an internal capacitor of the gate terminal of the PMOS transistor P 1 .
 
     Accordingly, instead of the signal swinging between the ground voltage of 0 V and the second supply voltage VDD 2 , a signal swinging between the voltage PG 2 _LOW and the second supply voltage VDD 2  is applied to the gate terminal PG 2  of the PMOS transistor P 1  as shown in  FIG. 1 . Accordingly, even if PMOS transistors designed to operate at the second supply voltage VDD 2  are used, overvoltage can be prevented from being applied to both the ends of the gate-oxide of the PMOS transistor P 1 . 
     Referring to Equation 1, a sufficient amount of pull-up driving current can be generated without causing the source-gate voltage Vsg of the PMOS transistor P 1  to exceed a rated voltage by adjusting the value of the capacitor C 1 . For example, as the first supply voltage VDD 1  decreases from 3.3 V to 2.5 V or 1.8 V, the voltage PG 2 _LOW may be further reduced in order to obtain the source-gate voltage Vsg of the PMOS transistor P 1  that can sufficiently drive the PMOS transistor P 1 . Accordingly, the voltage PG 2 _LOW is reduced by increasing the value of the capacitor C 1 . 
     Overvoltage can be prevented from being applied to the gate-oxide of the PMOS transistor P 0 . A gate driving signal is generated using a circuit including the PMOS transistor P 3  and the capacitor C 0  as shown in  FIG. 1 . As described above, the signal swinging between the ground voltage of 0 V and the second supply voltage VDD 2  is applied to the second terminal of the capacitor C 0 , and the signal applied to the gate terminal of the PMOS transistor P 3  and the signal applied to the second terminal of the capacitor C 0  are complementary: 
     If the second supply voltage VDD 2  is applied to the second terminal of the capacitor C 0 , since the voltage that is higher than the ground voltage of 0 V and lower than the first supply voltage VDD 1  and can turn on the PMOS transistor P 3  is applied to the gate terminal of the PMOS transistor P 3 , the PMOS transistor P 3  is turned on and the first supply voltage VDD 1  is applied to the gate terminal PG 1  of the PMOS transistor P 0 . Accordingly, the PMOS transistor P 0  is turned off. If the ground voltage of 0 V is applied to the second terminal of the capacitor C 0 , since the PMOS transistor P 3  is turned off when the first supply voltage VDD 1  is applied to the gate terminal of the PMOS transistor P 3 , a voltage PG 1 _LOW of the gate terminal of the PMOS transistor P 0  becomes as follows.
 
 PG 1_LOW=[ VDD 1 −VDD 2 *C 0/( C 0+ Cg ( P 0))]  (2)
 
where Cg(P 0 ) is the value of an internal capacitor of the gate terminal of the PMOS transistor P 0 .
 
     Accordingly, instead of the signal swinging between the ground voltage of 0 V and the first supply voltage VDD 1 , a signal swinging between the voltage PG 1 _LOW and the first supply voltage VDD 1  is applied to the gate terminal PG 1  of the PMOS transistor P 0  as shown in  FIG. 1 . Accordingly, even if PMOS transistors designed to operate at the second supply voltage VDD 2  are used, overvoltage can be prevented from being applied to gate-oxide of the PMOS transistor P 0 . Referring to Equation 2, a sufficient amount of pull-up driving current can be generated without causing a source-gate voltage Vsg of the PMOS transistor P 0  to exceed the rated voltage by adjusting the value of the capacitor C 0 . 
     If a signal swinging between the ground voltage of 0 V and the second supply voltage VDD 2  is applied to a node NG, that is, a gate terminal of the NMOS transistor N 0 , which is a pull-down transistor, normal operations can be performed. Also, when the NMOS transistor N 0  is driven, overvoltage is not applied to the gate-oxide of the NMOS transistor N 0 . 
     However, when the second supply voltage VDD 2  is applied to the node NG to drive the NMOS transistors N 0  and N 1 , which constitute a pull-down circuit, a gate length needs to be long enough to prevent deterioration of the characteristics of the NMOS transistor N 1  due to hot carriers. 
       FIG. 2  is a circuit diagram of the output driver of  FIG. 1 . Referring to  FIG. 2 , the output driver includes a level shifter  20 , two gate drivers PG_DRIVER 1  and PG_DRIVER 2 ; a plurality of inverters IN 1  through IN 4 , a plurality of PMOS transistors P 0  through P 4 , and a plurality of NMOS transistors N 0  and N 1 . The PMOS transistors P 0  through P 3  and the NMOS transistors N 0  and N 1  are respectively the same as the PMOS transistors P 0  through P 3  and the NMOS transistors N 0  and N 1  of  FIG. 1 . 
     The PMOS transistor P 4  is added to the pull-down circuit of  FIG. 1  in order to prevent overvoltage from being applied to the NMOS transistor N 1  of the pull-down circuit. 
     That is, since a voltage of a source terminal of the NMOS transistor N 1  is VDD 2 −Vtn when the NMOS transistor N 0  is turned off, a source-drain voltage Vds of the NMOS transistor N 1  may be higher than a rated voltage. Here, Vtn is a gate-source threshold voltage of the NMOS transistor N 1 . 
     Accordingly, as shown in  FIG. 2 , a source terminal and a drain terminal of the PMOS transistor P 4  are respectively connected to the gate terminal and the source terminal of the NMOS transistor N 1 , and an output terminal of the inverter IN 2  is connected to a gate terminal of the PMOS transistor P 4 . Accordingly, when the NMOS transistor N 0  is turned off, the PMOS transistor P 4  is turned on and a voltage of the source terminal of the NMOS transistor N 1  becomes the second supply voltage VDD 2 . Accordingly, the source-drain voltage Vds of the NMOS transistor N 1  can be prevented from exceeding the rated voltage. 
     The level shifter  20  is a circuit for shifting a supply voltage signal. The configuration of the level shifter  20  is shown in  FIG. 5 . 
       FIG. 5  is a circuit diagram of the level shifter  20  of the output driver of  FIG. 2 . Referring to  FIG. 5 , the level shifter  20  includes gate drivers PG_DRIVER 3  and PG_DRIVER 4 , inverters IN 9  and IN 10 , PMOS transistors P 3 , P 5  through P 8 , and NMOS transistors N 2  and N 3 . The gate drivers PG_DRIVER 3  and PG_DRIVER 4  constitute a circuit for changing a signal swinging between the ground voltage of 0 V and the second supply voltage VDD 2  to a signal swinging between the first supply voltage VDD 1  and a voltage that is higher than the ground voltage of 0 V and lower than the first supply voltage VDD 1  and can turn on a PMOS transistor by being applied to a gate terminal of the PMOS transistor. The circuit may be configured as shown in  FIG. 3 , and a detailed explanation thereof will be provided below. 
     Operations of the level shifter  20  of  FIG. 5  will now be explained. If a signal S 0  is 0 V, that is, a voltage of a low level, an output voltage of the inverter IN 9  is the second supply voltage VDD 2 , that is, a voltage of a high level, and an output voltage of the inverter IN 10  is the ground voltage of 0 V, that is, a voltage of a low level. Accordingly, the NMOS transistor N 3  is turned on and the NMOS transistor N 2  is turned off. The gate driver PG_DRIVE 3  generates a voltage that is higher than the ground voltage of 0 V and can turn on the PMOS transistors P 7  and P 3 . Accordingly, the PMOS transistors P 7  and P 3  are turned on, and the second supply voltage VDD 2  is applied to a gate terminal of the NMOS transistor N 5  to turn on the NMOS transistor N 5 . 
     Also, the gate driver PG_DRIVER 4  inputs the second supply voltage VDD 2 , and outputs the first supply voltage VDD 1  through an output terminal. Accordingly, the PMOS transistor P 8  is turned off. 
     Accordingly, since the PMOS transistor P 5  is turned off and the PMOS transistor P 6  is turned on, a voltage of a source terminal of the PMOS transistor P 3  becomes the first supply voltage VDD 1 . The PMOS transistor P 3  is turned on, and a voltage of a node B, that is, a drain terminal of the PMOS transistor P 3  becomes the first supply voltage VDD 1 . 
     If the signal S 0  is the second supply voltage VDD 2 , that is, a voltage of a high level, the output voltage of the inverter IN 9  becomes the ground voltage of 0 V, that is, a voltage of a low level, and the output voltage of the inverter IN 10  becomes the second supply voltage VDD 2 , that is, a voltage of a high level. Accordingly, the NMOS transistor N 3  is turned off and the NMOS transistor N 2  is turned on. A voltage of an output terminal of the gate driver PG_DRIVER 3  becomes the first supply voltage VDD 1 , and a voltage of the output terminal of the gate driver PG_DRIVER  4  becomes a voltage that is higher than the ground voltage of 0 V and can turn on the PMOS transistor P 8 . 
     Accordingly, the PMOS transistors P 7  and P 3  are turned off, and the transistors N 2  and P 8  are turned on. Of course, the second supply voltage VDD 2  is applied to the gate terminal of the NMOS transistor N 4 , and thus the NMOS transistor N 4  is turned on. Accordingly, the PMOS transistor P 5  is turned on, and the PMOS transistor P 6  is turned off. 
     The voltage of the output terminal of the gate driver PG_DRIVER 3  becomes the first supply voltage VDD 1 , and thus the PMOS transistor P 3  is turned off. Accordingly, the PMOS transistor P 3  is in a high impedance state, and the voltage of the node B is determined according to a circuit connected to the node B. 
     The gate driver PG_DRIVER 1  is a circuit for generating a signal to be applied to the gate terminal PG 1  of the PMOS transistor P 0  of a pull-up circuit. The configuration of the gate driver PG_DRIVER 1  is shown in  FIG. 3 . 
       FIG. 3  is a circuit diagram illustrating the gate driver PG_DRIVER 1  of the output driver of  FIG. 2 . Referring to  FIG. 3 , the gate driver PG_DRIVER 1  includes a plurality of PMOS transistors P 9  and P 10 , a plurality of NMOS transistors N 5 , N 6 , N 7 , and N 15 , a capacitor C 0 , inverters IN 5  and IN 6 , and a stabilizing circuit  30 - 1 . A first supply voltage source is connected to a source terminal of each of the PMOS transistors P 9  and P 10 . 
     The operation of the gate driver PG_DRIVER 1  of  FIG. 3  will now be explained. 
     A node A is connected to an output terminal of the inverter IN 1  of  FIG. 2 , and a node Y 1  is connected to a drain terminal of the PMOS transistor P 3  of  FIG. 2  and to the gate terminal PG 1  of the PMOS transistor P 0 . 
     When a signal of the node A changes from a low-level voltage (0 V) state to a high-level voltage (VDD 2 ) state, the NMOS transistors N 6  and N 7  are turned on until a voltage of an output terminal of the inverter IN 5  changes from a voltage of a high level (VDD 2 ) to a voltage of a low level (0 V). Since the NMOS transistor N 5  is always turned on, the PMOS transistor P 10  is turned on. Accordingly, the PMOS transistors P 10  and P 9  constitute a mirror circuit, the PMOS transistor P 9  is turned on, and a voltage of the node Y 1  becomes the first supply voltage VDD 1 . 
     When a signal of the node A changes from a high-level voltage (VDD 2 ) state to a low-level voltage (0 V) state, the NMOS transistor N 7  is turned off and the PMOS transistors P 10  and P 9  are turned off. 
     Since the PMOS transistor P 3  of  FIG. 2  is in an on state until a signal of the node A changes from a voltage of a high level (VDD 2 ) to a voltage of a low level (0 V), a voltage of the node A is still the second supply voltage VDD 2 . Of course, a voltage of a terminal of the capacitor C 0  connected to the node A becomes the second supply voltage VDD 2 . 
     Accordingly, when the signal of the node A changes from a high-level voltage (VDD 2 ) state to a low-level voltage (0 V) state, the voltage of the terminal of the capacitor C 0  connected to the node A is changed from the second supply voltage VDD 2  to the ground voltage of 0 V. Accordingly, a voltage of the node Y 1  is expressed as Equation 2 based on charge sharing between the capacitor C 0  and the internal capacitor Cg(P 0 ) of the PMOS transistor P 0  (see  FIG. 1  or  2 ) connected to the node Y 1 . 
     Without considering the stabilizing circuit  30 - 1 , a voltage suitable for driving the PMOS transistor P 0  is generated when a signal applied to the node A is in an alternating current (AC) state. However, the node Y 1  is floating when the signal applied to the node A is maintained in a direct current (DC) state, and a logic state of the node Y 1  is determined by a leakage current of a device connected to the node Y 1 . 
     The stabilizing circuit  30 - 1  is a circuit for preventing the node Y 1  from floating when the signal applied to the node A is maintained in the DC state. The configuration of the stabilizing circuit  30 - 1  is illustrated in  FIG. 6 . 
       FIG. 6  is a circuit diagram illustrating the stabilizing circuit  30 - 1  of the gate driver PG_DRIVER 1  of  FIG. 3 . Referring to  FIG. 6 , the stabilizing circuit  30 - 1  includes a logic gate circuit LG 1 , a PMOS transistor P 11 , and a plurality of NMOS transistors N 9  through N 14 , and is coupled to an NMOS transistor N 15  and an inverter IN 6 . 
     Elements other than the stabilizing circuit  30 - 1  of  FIG. 6  are the same as those illustrated in  FIG. 3 . 
     CV 1  and CV 2  are control signals for determining a voltage of the node Y 1 , which is an output terminal of the stabilizing circuit  30 - 1 , in a floating state. 
     For example, it is assumed that if the first supply voltage VDD 1  is 3.3 V, the control signal CV 1  is a signal having a low logic level and the control signal CV 2  is a signal having a low logic level, if the first supply voltage VDD 1  is 2.5 V, the control signal CV 1  is a signal having a low logic level and the control signal CV 2  is a signal having a high logic level, and if the first supply voltage VDD 1  is 1.8 V, the control signal CV 1  is a signal having a high logic level and the control signal CV 2  is a signal having a low logic level. 
     A terminal FB is connected to a node T 0  of a circuit of  FIG. 9 . Accordingly, when the first supply voltage VDD 1  is 3.3 V and a signal of the node A is maintained in a DC 0V state, the NMOS transistors N 10  and N 14  are turned off, and the logic gate circuit LG 1  outputs a signal having a low logic level. Accordingly, the transistors P 11  and N 8  are turned on, and a voltage of the node Y 1  becomes the second supply voltage VDD 2 . 
     When the first supply voltage VDD 1  is 2.5 V and a signal of the node A is maintained in a DC 0 V state, the logic gate circuit LG 1  outputs a signal having a high logic level and the PMOS transistor P 11  is turned off. The NMOS transistor N 10  is turned off, and the NMOS transistors N 14  and N 15  are turned on. Accordingly, a voltage of the node Y 1  becomes 3*Vtn. Here, Vtn is a threshold voltage of each of the diodes of the NMOS transistors N 11  through N 13 . 
     Likewise, when the first supply voltage is 1.8 V and a signal of the node A is maintained in a DC 0 V state, a voltage of the node Y 1  becomes Vtn. 
     Accordingly, the node Y 1  can be prevented from floating due to the stabilizing circuit  30 - 1  of  FIG. 6 . 
     Referring to  FIG. 2  again, the gate driver PG-DRIVER 2  is a circuit for generating a signal to be applied to the gate terminal PG 2  of the PMOS transistor P 1  of the pull-up circuit. The configuration of the gate driver PG-DRIVER 2  is shown in  FIG. 4 . 
       FIG. 4  is a circuit diagram illustrating the gate driver PG_DRIVER  2  of the output driver of  FIG. 2 . Referring to  FIG. 4 , the gate driver PG_DRIVER 2  includes a plurality of PMOS transistors P 12  and P 13 , a plurality of NMOS transistors N 16 , N 17 , N 18 , and N 26 , a plurality of capacitors C 1 , C 2 , and C 3 , inverters IN 7  and IN 8 , and a stabilizing circuit  30 - 2 . A second supply voltage source is connected to a source terminal of each of the PMOS transistors P 12  and P 13 . 
     The operation of the gate driver PG_DRIVER 2  of  FIG. 4  will now be explained. 
     The node A is connected to the output terminal of the inverter IN 1  of  FIG. 2 , and a node Y 2  is connected to the gate terminal PG 2  of the PMOS transistor P 1  and to the drain terminal of the PMOS transistor P 2  of  FIG. 2 . 
     When a signal of the node A changes from a low-level voltage (0 V) state to a high-level voltage (VDD 2 ) state, the NMOS transistors N 16  and N 17  are turned on until a voltage of an output terminal of the inverter IN 7  changes from a voltage of a high level (VDD 2 ) to a voltage of a low level (0 V). Accordingly, the PMOS transistors P 13  and P 12  constitute a mirror circuit, the PMOS transistors P 13  and P 12  are turned on, and a voltage of the node Y 2  becomes the second supply voltage VDD 2 . 
     When a signal of the node A changes from a high-level voltage (VDD 2 ) state to a low-level voltage (0 V) state, the NMOS transistor N 17  is turned off and the PMOS transistors P 13  and P 12  are turned off. 
     Since the PMOS transistor P 2  of  FIG. 2  is in an on state until a signal of the node A changes from a voltage of a high level (VDD 2 ) to a voltage of a low level (0 V), a voltage of the node A is still the second supply voltage VDD 2 . Of course, a voltage of a terminal of the capacitor C 1  connected to the node A becomes the second supply voltage VDD 2 . 
     Accordingly, when the signal of the node A changes from a high-level voltage (VDD 2 ) state to a low-level voltage (0 V) state, the voltage of the terminal of the capacitor C 1  connected to the node A is changed from the second supply voltage VDD 2  to the ground voltage of 0 V. Accordingly, a voltage of the node Y 2  is expressed as Equation 2 based on charge sharing between the capacitor C 1  and the internal capacitor Cg(P 1 ) of the PMOS transistor P 1  (see  FIG. 1  or  2 ) connected to the node Y 2 . 
     The capacitors C 2  and C 3  are used to adjust the voltage of the node Y 2  when the first supply voltage VDD 1  is changed. For example, if the first supply voltage VDD changes from 3.3 V to 2.5 V, an NMOS transistor N 19  is in an on state and the voltage of the node Y 2  is determined according to values of the capacitors C 1  and C 3 . 
     Without considering the stabilizing circuit  30 - 2 , a voltage suitable for driving the PMOS transistor P 1  is generated when a signal applied to the node A is in an AC state. However, the node Y 2  is floating when the signal applied to the node A is maintained in a DC state, and a logic state of the node Y 2  is determined by a leakage current of a device connected to the node Y 2 . If the first supply voltage VDD 1  changes from 3.3 V to 1.8 V, the NMOS transistor N 18  is turned on and thus the voltage of the node Y 2  is determined according to values of the capacitors C 1  and C 2 . 
     The stabilizing circuit  30 - 2  is a circuit for preventing the node Y 2  from floating when the signal applied to the node A is maintained in the DC state. The configuration of the stabilizing circuit  30 - 2  is illustrated in  FIG. 7 . 
       FIG. 7  is a circuit diagram illustrating the stabilizing circuit  30 - 2  of the gate driver PG_DRIVER  2  of  FIG. 4 . Referring to  FIG. 7 , the stabilizing circuit  30 - 2  includes a logic gate circuit LG 2 , a PMOS transistor P 14 , and a plurality of NMOS transistors N 20  through N 25 , and is coupled to an NMOS transistor N 26  and an inverter IN 8 . 
     Elements other than the stabilizing circuit  30 - 2  are the same as those illustrated in  FIG. 4 . 
     CV 1  and CV 2  are control signals for determining a voltage of the node Y 2 , that is, an output terminal of the stabilizing circuit  30 - 2 , in a floating state. 
     For example, it is assumed that if the first supply voltage VDD 1  is 3.3 V, the control signal CV 1  is a signal having a low logic level and the control signal CV 2  is a signal having a low logic level, if the first supply voltage VDD 1  is 2.5 V, the control signal CV 1  is a signal having a low logic level and the control signal CV 2  is a signal having a high logic level, and if the first supply voltage VDD 1  is 1.8 V, the control signal CV 1  is a signal having a high logic level and the control signal CV 2  is a signal having a low logic level. 
     When the first supply voltage is 3.3 V and a signal of the node A is maintained in a DC 0 V state, the NMOS transistors N 21  and N 25  are turned off and the logic gate circuit LG 2  outputs a signal having a low logic level. Accordingly, the PMOS transistor P 14  is turned on, and a voltage of the node Y 2  becomes the second supply voltage VDD 2 . 
     When the first supply voltage VDD 1  is 2.5 V and a signal of the node A is maintained in a DC 0 V state, the logic gate circuit LG 2  outputs a signal having a high logic level and the PMOS transistor P 14  is turned off. The NMOS transistor N 21  is turned off, and the NMOS transistors N 25  and N 26  are turned on. Accordingly, a voltage of the node Y 2  becomes 3*Vtn, where Vtn is a threshold voltage of each of diodes of the NMOS transistors N 22  through N 24 . 
     Likewise, when the first supply voltage VDD 1  is 1.8 V and a signal of the node A is maintained in a DC 0 V state, a voltage of the node Y 2  becomes Vtn. 
     Accordingly, the node Y 2  can be prevented from floating due to the stabilizing circuit  30 - 2  of  FIG. 7 . 
     Referring to  FIG. 2  again, if the signal S 0  is a signal swinging between the ground voltage of 0 V and the second supply voltage VDD 2 , the following operation is performed according to the configuration of the level shifter  20  of  FIG. 5  and the gate drivers PG_DRIVER 1  and PG_DRIVER 2  of  FIGS. 3 and 4 . 
     The following operation is performed when the signal S 0  changes to the ground voltage of 0 V, that is, a voltage of a low level. 
     A voltage that is higher than the ground voltage of 0 V and lower than the first supply voltage VDD 1  and can turn on the PMOS transistor P 3  is applied to the gate terminal of the PMOS transistor P 3  due to the level shifter  20 . Accordingly, the PMOS transistor P 3  is turned on, and the first supply voltage VDD 1  is applied to the gate terminal PG  1  of the PMOS transistor P 0 . Accordingly, the PMOS transistor P 0  is turned off. 
     The PMOS transistor P 2  is turned on, and the second supply voltage VDD 2  is applied to the gate terminal PG 2  of the PMOS transistor P 1 . 
     Also, the second supply voltage VDD 2  is applied to the gate terminal of the PMOS transistor P 4 , and the PMOS transistor P 4  is turned off. The second supply voltage VDD 2  is applied to a gate terminal of the NMOS transistor N 0 , the NMOS transistor N 0  is turned on, and the NMOS transistor N 1  is turned on, and the pad  10  is pulled down to the ground voltage of 0 V. 
     If the signal S 0  changes to the second supply voltage VDD 2 , that is, a voltage of a high level, the following operation is performed. 
     The first supply voltage VDD 1  is applied to the gate terminal of the PMOS transistor P 3  due to the level shifter  20 . Accordingly, the PMOS transistor P 3  is turned off and in a high impedance state. The voltage PG 1 _LOW of the gate terminal PG 1  of the PMOS transistor P 0  is expressed as Equation 2 due to the gate driver PG_DRIVER 1 . The PMOS transistor P 0  is turned on due to the voltage PG 1 _LOW. The voltage PG 2 _LOW of the gate terminal PG 2  of the PMOS transistor P 1  is expressed as Equation 1 due to the gate driver PG_DRIVER 2 . The PMOS transistor P 1  is turned on due to the voltage PG 2 _LOW. 
     Also, the NMOS transistor N 0  is turned off, and the pad  10  is pulled up to the first supply voltage VDD 1 . 
     Accordingly, as shown in Equations 1 and 2, a sufficient source-gate voltage for driving a PMOS transistor can be generated without causing overvoltage to the gate-oxide of the PMOS transistor by adjusting the values of the capacitors C 0  and C 1 . 
     The gate-oxide of the PMOS transistor P 0  does not suffer problems when a voltage of the gate terminal PG 1  of the PMOS transistor P 0 , that is, a node of the pull-up circuit, is in a range from (VDD 1 -VDD 2 ) to the second supply voltage VDD 2 , since a gate-source voltage difference of the PMOS transistor P 0  is the same as a gate-source voltage difference of the NMOS transistor N 0  and impedances of the pull-up circuit and the pull-down circuit can be maintained similar to each other. Referring to Equation 2, a value of the capacitor C 0  needs to be higher than that of the internal capacitor Cg(P 0 ). 
     A circuit for enabling a circuit to have a fail-safe function and a tolerant function necessary to prevent current from flowing from the pad  10  of the output driver to a supply voltage source terminal will now be explained. 
     A circuit for generating control signals VF 1 , VF 3 , and FW which are necessary for the output driver to have a fail-safe function and a tolerant function will be explained. 
     The circuit for generating the control signals VF 1 , VF 3 , and FW is illustrated in  FIG. 8 . 
       FIG. 8  is a circuit diagram illustrating a circuit for generating control signals for a tolerant function and a fail-safe function of the output driver of  FIG. 2 , according to some embodiments of the inventive subject matter. The operation of the circuit of  FIG. 8  when a first supply voltage source is turned on/off and when the first supply voltage VDD 1  is applied to the pad  10  will be explained. 
     If both the first supply voltage source and a second supply voltage source are turned on, an NMOS transistor N 0  is turned on, a PMOS transistor P 7  is turned off, and a voltage of a node VF 1  becomes the second supply voltage VDD 2 . The second supply voltage VDD 2  is applied to a gate terminal of a PMOS transistor P 4  to turn on the PMOS transistor P 4 , and a node VF 3  is charged with the first supply voltage VDD 1  through the PMOS transistor P 4  to make a voltage of the node VF 3  become the first supply voltage VDD 1 . Since the PMOS transistor P 2  is always in an off state in this case, even if the first supply voltage VDD 1  is applied to the pad  10 , the node VF 3  is not affected by the voltage of the pad  10 . If the voltage of the pad  10  is lower than the first supply voltage VDD 1 , PMOS transistors P 0  and P 1  are turned on, and thus a voltage of the node FW becomes the first supply voltage VDD 1 . If a voltage of the pad  10  is higher than the first supply voltage VDD 1 , the PMOS transistor P 1  is turned off, PMOS transistors P 2  and P 3  are turned on, and a voltage of the node FW becomes the same as the voltage of the pad  10 . 
     Second, if both the first supply voltage source and the second supply voltage source are turned off, since NMOS transistors N 1 , N 2 , N 3 , and N 4  are connected in a diode configuration when the first supply voltage VDD 1  is applied to the pad  10 , a voltage that is reduced by 4 times Vtn from a voltage V(PAD) of the pad  10  is applied to a drain terminal of a PMOS transistor P 6 . Here, Vtn is a diode threshold voltage. In this case, the PMOS transistors P 7  is turned on, a voltage of the node VF 1  becomes [V(PAD)−4*Vtn], and the same voltage as [V(PAD)−4*Vtn] is applied to the gate terminal of the PMOS transistor P 4  to turn off the PMOS transistor P 4 , thereby preventing overvoltage from being applied to an oxide. 
     A circuit for performing a fail-safe function and a tolerant function by applying the control signals VF 1 , VF 3 , and FW generated in the circuit of  FIG. 8  to the output driver will now be explained with reference to  FIG. 9 . 
       FIG. 9  is a circuit diagram illustrating the output driver of  FIG. 2  which can perform a fail-safe function and a tolerant function using the control signals VF 1 , VF 3 , and FW. 
     Referring to  FIG. 9 , NMOS transistors N 27  through N 30  and PMOS transistors P 15  through P 22  are added to the output driver of  FIG. 2 . 
     For reference, a pre-driver logic circuit  40  is also added to the output driver of  FIG. 2 . The pre-driver logic circuit  40  is a circuit for outputting a signal corresponding to a logic value of data DATA through different terminals when an output enable signal OE is applied to the pre-driver logic circuit  40 . 
     The operation of the output driver having the fail-safe function and the tolerant function will be explained in detail. 
     If a signal of a voltage that is higher than the first supply voltage VDD 1  is applied to the pad  10 , a voltage of the node VF 1  becomes the second supply voltage VDD 2 , a voltage of the node VF 3  becomes the first supply voltage VDD 1 , and a voltage of the node FW becomes a pad voltage. Accordingly, the PMOS transistors P 15  and P 16  are turned on, and a voltage of the gate terminal PG 2 , which is a node, of the PMOS transistor P 1 , becomes the pad voltage. Accordingly, the PMOS transistor P 1  is turned off, thereby preventing current from flowing to a first supply voltage source terminal. 
     If the first supply voltage source and the second supply voltage source are turned off and the first supply voltage VDD 1  is applied to the pad  10 , voltages of the nodes VF 1  and VF 3  become [V(PAD)−4*Vth] and a voltage of the node FW becomes the pad voltage. Accordingly, the PMOS transistors P 15  and P 16  are turned on and the voltage PG 2  becomes the pad voltage. Accordingly, the PMOS transistor P 1  is turned off, thereby preventing current from flowing to the first supply voltage source terminal. If a voltage of a node T 4  is about the ground voltage of 0 V, overvoltage may be applied to the oxide of the PMOS transistor P 1 . Accordingly, a voltage of the node T 4  is determined to be [V(PAD)−4*Vth]using the PMOS transistor P 19 . A voltage of the gate terminal PG 1 , which is a node, becomes [V(PAD)−4*Vth] using the PMOS transistor P 20  to turn off the transistor P 0 . A voltage of [V(PAD)−4*Vth] is applied to gate terminals of the PMOS transistors P 21  and P 22 , thereby preventing current from flowing to the first supply voltage source terminal. Accordingly, overvoltage can be prevented from being applied to both the ends of the oxide of each PMOS transistor. 
     As described above, current can be prevented from flowing to the first supply voltage source terminal due to a signal applied to the pad  10  using the PMOS transistor P 22  added to a gate driver T_PG_DRIVER 1  of  FIG. 10  and a transistor P 21  added to a level shifter  20 - 1 . 
     While the inventive subject matter has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive subject matter as defined by the following claims.