Abstract:
Disclosed herein is a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention The present invention relates to a test method for a semiconductor device, and more particularly relates to a test method for a semiconductor device including a plurality of stacked semiconductor chips that are bump-connected with each other. 
         [0002]    2. Description of Related Art 
         [0003]    Storage capacity required for semiconductor memory devices such as DRAM (Dynamic Random Access Memory) has been growing year by year. To satisfy the requirement, in recent years, a memory device called multi-chip package has been proposed. In the multi-chip package, a plurality of memory chips are stacked. However, in the case of the multi-chip package, a wire needs to be provided for each chip to connect each memory chip and a package substrate. Therefore, it is difficult to stack many memory chips. 
         [0004]    On the other hand, in recent years, a semiconductor device of a type in which a plurality of memory chips with penetrating electrodes are stacked has been proposed (See Japanese Patent Application Laid-Open No. 2005-136187). In the semiconductor device of the type, among penetrating electrodes provided on each memory chip, the penetrating electrodes that are provided on the same plane position when seen from a stacking direction are electrically short-circuited. Therefore, even if the number of chips stacked increases, the number of electrodes connected to the package substrate does not increase. Thus, it is possible to stack a larger number of memory chips. 
         [0005]    When semiconductor chips with penetrating electrodes are stacked, bump electrodes that are provided on upper and lower chips need to be in accurate contact with each other. Accordingly, compared with an operation of stacking chips in the multi-chip package, more accurate positioning is required. 
         [0006]    However, when the semiconductor chips having the penetrating electrodes are once stacked, connection states of the bump electrodes cannot be visually checked. Accordingly, to evaluate whether a connection failure occurs, a highly accurate load circuit or measurement circuit needs to be mounted on each of the semiconductor chips, which increases the chip area. Furthermore, an evaluation using a load circuit or a measurement circuit mounted on each semiconductor chip requires quite a long time when the number of bump electrodes is large. 
       SUMMARY 
       [0007]    In one embodiment, there is provided a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit. 
         [0008]    According to the present invention, a consumption current is purposefully increased by causing a so-called bus fight during a test mode. Therefore, connection states of bump electrodes can be evaluated only by observing a change in the consumption current. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a schematic cross-sectional view of a semiconductor device of the present invention; 
           [0010]      FIG. 2  is a cross-sectional view of a penetrating electrode TSV; 
           [0011]      FIG. 3  is a schematic diagram for explaining a structure of a bidirectional data bus DB; 
           [0012]      FIG. 4  is a block diagram showing a test circuit provided in a memory chip MC 0  shown in  FIG. 1 ; 
           [0013]      FIG. 5  is a block diagram showing a state where a test device is connected to the semiconductor device  10  shown in  FIG. 1 ; 
           [0014]      FIG. 6  is a flowchart for explaining a test method for a semiconductor device according to the present embodiment; 
           [0015]      FIG. 7  is a diagram for explaining a scan operation for driver circuits to output high-level data in turn; 
           [0016]      FIG. 8A  is a schematic diagram showing a current path P 0  in a case where a memory chip MC 0  is selected; 
           [0017]      FIG. 8B  is a schematic diagram showing a current path P 1  in a case where a memory chip MC 1  is selected; 
           [0018]      FIG. 8C  is a schematic diagram showing a current path P 2  in a case where a memory chip MC 2  is selected; 
           [0019]      FIG. 8D  is a schematic diagram showing a current path P 3  in a case where a memory chip MC 3  is selected; 
           [0020]      FIG. 9A  is an example of a monitoring result of the consumption current Im by a tester  30  and shows a monitoring result in a case where the memory chip MC 0  is selected; 
           [0021]      FIG. 9B  is an example of a monitoring result of the consumption current Im by a tester  30  and shows a monitoring result in a case where the memory chip MC 1  is selected; 
           [0022]      FIG. 10A  is a schematic diagram showing an example in which a bus fight is caused between the memory chip MC 0  and the memory chip MC 1 ; 
           [0023]      FIG. 10B  is a schematic diagram showing an example in which a bus fight is caused between the memory chip MC 1  and the memory chip MC 2 ; 
           [0024]      FIG. 10C  is a schematic diagram showing an example in which a bus fight is caused between the memory chip MC 2  and the memory chip MC 3 ; 
           [0025]      FIG. 11  is a circuit diagram showing an example in which a limiter circuit  70  is connected to a driver circuit D; 
           [0026]      FIG. 12  is a circuit diagram showing an example in which a loose contact occurring in an address bus AB can be detected; and 
           [0027]      FIG. 13  is a circuit diagram showing an example in which one driver circuit is commonly assigned to a plurality of address buses AB 0  to ABm. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0028]    Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. 
         [0029]    Referring now to  FIG. 1 , the semiconductor device  10  of the embodiment has a structure in which the following components are stacked: four memory chips MC 0  to MC 3 , which have the same functions and are produced with the use of the same production mask; one control chip CC, which is produced with the use of a different production mask from that of the memory chips MC 0  to MC 3 ; and one interposer IP. The memory chips MC 0  to MC 3  and the control chip CC are semiconductor chips for which a silicon substrate is used, and are stacked by a face-down method on the interposer IP. The face-down method means a method of mounting semiconductor chips in such a way that principal surfaces on which electronic circuits such as transistors are formed face downward, or that the principal surfaces face the interposer IP&#39;s side. 
         [0030]    However, the semiconductor device of the present invention is not limited to the above structure. The semiconductor chips each may be stacked by a face-up method. The face-up method means a method of mounting semiconductor chips in such a way that principal surfaces on which electronic circuits such as transistors are formed face upward, or that the principal surfaces face a side opposite to the interposer IP&#39;s side. Alternatively, the semiconductor chips stacked by the face-down method, and the semiconductor chips stacked by the face-up method may exist together. 
         [0031]    Among the semiconductor chips, the memory chips MC 1  to MC 3  and the control chip CC other than the memory chip MC 0  placed on the top layer are provided with large numbers of penetrating electrodes (through-substrate vias) TSV that pass through a substrate. Also, TSV may be called penetration electrodes, penetration vias, through electrode, or through-vias. In areas that overlap with the penetrating electrodes TSV when seen from a stacking direction in planar view, top-surface bumps FB are provided on the principal-surface sides of the chips, and back-surface bumps BB are provided on the back-surface sides of the chips. The back-surface bumps BB of a semiconductor chip placed on a lower layer are bonded to the top-surface bumps FB of a semiconductor chip placed on an upper layer. In this manner, the semiconductor chips that are adjacent to each other in the vertical direction are electrically connected. Incidentally, in the present invention, when it is not particularly necessary that the top-surface bumps FB and back-surface bumps BB are distinguished, these may be called “bump electrodes”. 
         [0032]    According to the present embodiment, the reason why no penetrating electrode TSV is provided on the top-layer memory chip MC 0  is because there is no need to form a bump electrode on the back-surface side of the memory chip MC 0  as the chips are stacked by the face-down method. If no penetrating electrode TSV is provided on the top-layer memory chip MC 0  as described above, the top-layer memory chip MC 0  can be made thicker than the other memory chips MC 1  to MC 3  to increase the mechanical strength of the memory chip MC 0 . However, according to the present invention, a penetrating electrode TSV may be provided on the top-layer memory chip MC 0 . In this case, all the memory chips MC 0  to MC 3  can be produced by the same process. 
         [0033]    Memory chip MC 0  to MC 3  is wide I/O SDRAM (Synchronous Dynamic Random Access Memory) whose data bus width is several hundred to several thousand bits. The control chip CC controls operation of the memory chip MC 0  to MC 3  and plays a function as an interface with the outside. Therefore, all access from the outside is performed through control chip CC, and input and output of data are also performed through control chip CC. 
         [0034]    The interposer IP is a circuit board made of resin. On a back surface IPb thereof, a plurality of external terminals (solder balls) SB are formed. The interposer IP ensures the mechanical strength of the semiconductor device  10  and functions as a redistribution substrate (or a rewiring substrate) to expand an electrode pitch. That is, substrate electrodes  91  that are formed on a top surface IPa of the interposer IP are led out to the back surface IPb via through-hole electrodes  92 ; rewiring layers  93  that are provided on the back surface IPb are designed to expand the pitch of the external terminals SB. The areas of the top surface IPa of the interposer IP where no substrate electrode  91  is formed are covered with resist  90   a . The areas of the back surface IPb of the interposer IP where no external terminal SB is formed are covered with resist  90   b .  FIG. 1  shows only five external terminals SB. However, a large number of external terminals are actually provided. 
         [0035]    The gaps between the memory chips MC 0  to MC 3  and control chip CC stacked are filled with underfill  94 . In this manner, the mechanical strength is ensured. The gap between the interposer IP and the control chip CC is filled with NCP (Non-Conductive Paste)  95 . The entire package is covered with mold resin  96 . In this manner, each chip is physically protected. 
         [0036]    Most of the penetrating electrodes TSV provided on the memory chips MC 0  to MC 3  are connected to the top-surface bumps FB and back-surface bumps BB that are provided at the same locations in planar view. 
         [0037]    Turning to  FIG. 2 , the penetrating electrode TSV is so provided as to pass through a silicon substrate  80 , an interlayer insulation film  81 , which is provided on a top surface of the silicon substrate  80 , and a passivation film  83 , which is provided on a back surface of the silicon substrate  80 . Although not specifically limited, the penetrating electrode TSV is made of Cu (copper). The top surface of the silicon substrate  80  serves as a device formation surface on which devices such as transistors are formed. Around the penetrating electrode TSV, insulation rings  82  are provided to insulate the penetrating electrode TSV from a transistor region. In the example shown in  FIG. 2 , two insulation rings  82  are provided. One insulation ring  82 , instead of two, may be provided. When two insulation rings  82  are provided, capacitance between the penetrating electrode TSV and the silicon substrate  80  can be reduced. 
         [0038]    An end portion of the penetrating electrode TSV that is closer to the back surface of the silicon substrate  80  is covered with a back-surface bump BB. In the memory chips MC 1  to MC 3 , the back-surface bumps BB are in contact with the top-surface bumps FB provided on upper-layer memory chips MC 0  to MC 2 , respectively. In the control chip CC, the back-surface bumps BB are in contact with the top-surface bumps FB provided on the memory chip MC 3 . Although not specifically limited, the back-surface bumps BB are made of SnAg solder, which covers the surfaces of the penetrating electrodes TSV made of Cu (copper). The top-surface bump FB is connected to an end portion of the penetrating electrode TSV via pads M 1  to M 4 , which are provided in wiring layers L 1  to L 4 , and a plurality of through-hole electrodes TH 1  to TH 3 , which connect the pads. In the memory chips MC 1  to MC 3 , the top-surface bumps FB are in contact with the back-surface bumps BB provided on the lower-layer memory chips MC 2  and MC 3  and the interface chips IF, respectively. In the control chip CC, the top-surface bumps FB are in contact with the substrate electrodes  91  on the interposer IP. Although not specifically limited, the top-surface bumps FB include a pillar portion  86  that is made of Cu (copper). A surface of the pillar portion  86  includes a structure in which layers of Ni (nickel) and Au (gold) are stacked. The diameter of the top-surface bumps FB and back-surface bumps BB is about 20 μm. 
         [0039]    According to the above configuration, the top-surface bumps FB and back-surface bumps BB that are provided at the same locations in planar view are being short-circuited via the penetrating electrodes TSV. The pillar portion  86  of a top-surface bump FB is so provided as to pass through a passivation film  84 . A top surface of the passivation film  84  except a region where the top-surface bump FB is formed is covered with a polyimide film  85 . Incidentally, the connection to internal circuits not shown in the diagram is realized via internal wires (not shown), which are led out from the pads M 1  to M 4  provided in the wiring layers L 1  to L 4 . 
         [0040]    Incidentally, in the control chip CC, this kind of the penetrating electrodes TSV which short-circuit the top-surface bumps FB and back-surface bumps BB are provided as part of a plurality of the penetrating electrodes TSV. Such penetrating electrodes TSV provided on the control chip CC are used mainly for supplying power supply potential VDD or ground potential VSS. 
         [0041]    Most of the other penetrating electrodes TSV provided on the control chip CC are connected to the back-surface bumps BB that are provided at the same locations in planar view, but not connected to the top-surface bumps FB that are provided at the same locations in planar view. Although not shown, this kind of the penetrating electrodes have a structure in which any of the through-hole electrodes TH 1  to TH 3  is omitted. 
         [0042]    Because the memory chips MC 0  to MC 3  and the control chip CC are stacked in such a manner that the top-surface bumps FB and the back-surface bumps BB facing each other are bonded as shown in  FIG. 1 , a plurality of signal paths commonly connected to these semiconductor chips are formed in the semiconductor device  10 . These signal paths include a bidirectional data bus for transmitting or receiving read data and write data, an address bus and a command bus for transmitting an address signal and a command signal, respectively, and the like. The address bus and the command bus are unidirectional buses from the control chip CC to the memory chips MC 0  to MC 3 . 
         [0043]    Turning to  FIG. 3 , the bidirectional data bus DB is commonly connected to the memory chips MC 0  to MC 3  and the control chip CC through four penetrating electrodes TSV 1  to TSV 3  and TSVC. The penetrating electrodes TSV 1  to TSV 3  are provided to pass through the memory chips MC 1  to MC 3 , respectively, and the penetrating electrode TSVC is provided to pass through the control chip CC. Reference characters FB 0  to FB 3  shown in  FIG. 3  denote top-surface bumps provided on the memory chips MC 0  to MC 3 , respectively, BB 1  to BB 3  denote back-surface bumps provided on the memory chips MC 1  to MC 3 , respectively, and BBC denotes a back-surface bump provided on the control chip CC. As mentioned above, the top-surface bump FB of a chip in an upper layer is bonded with the back-surface bump BB of a chip in the underlying layer, thereby constituting one bidirectional data bus DB commonly connected to the memory chips MC 0  to MC 3  and the control chip CC. 
         [0044]    With this configuration, read data output from an internal circuit  20  of the memory chip MC 0  is output to the bidirectional data bus DB via a driver circuit MD 0  and supplied to the control chip CC through the penetrating electrodes TSV 1  to TSV 3  and TSVC. The control chip CC supplies the read data on the bidirectional data bus DB to an internal circuit  24  via a receiver circuit CR. Write data output from the internal circuit  24  of the control chip CC is output to the bidirectional data bus DB via a driver circuit CD and supplied to the memory chip MC 0  through the penetrating electrodes TSVC and TSV 3  to TSV 1 . The memory chip MC 0  supplies the write data on the bidirectional data bus DB to the internal circuit  20  via a receiver circuit MR 0 . In transmission of these signals, the signals pass through four bonding points of the bump electrodes, that is, a bonding point of a top-surface bump FB 0  and a back-surface bump BB 1 , a bonding point of a top-surface bump FB 1  and a back-surface bump BB 2 , a bonding point of a top-surface bump FB 2  and a back-surface bump BB 3 , and a bonding point of a top-surface bump FB 3  and a back-surface bump BBC. 
         [0045]    Read data output from an internal circuit  21  of the memory chip MC 1  is output to the bidirectional data bus DB via a driver circuit MD 1  and supplied to the control chip CC through the penetrating electrodes TSV 2 , TSV 3 , and TSVC. Write data output from the internal circuit  24  of the control chip CC is output to the bidirectional data bus DB via the driver circuit CD and supplied to the memory chip MC 1  through the penetrating electrodes TSVC, TSV 3 , and TSV 2 . The memory chip MC 1  supplies the write data on the bidirectional data bus DB to the internal circuit  21  via a receiver circuit MR 1 . In transmission of these signals, the signals pass through three bonding points of the bump electrodes, that is, the bonding point of the top-surface bump FB 1  and the back-surface bump BB 2 , the bonding point of the top-surface bump FB 2  and the back-surface bump BB 3 , and the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. 
         [0046]    Furthermore, read data output from an internal circuit  22  of the memory chip MC 2  is output to the bidirectional data bus DB via a driver circuit MD 2  and supplied to the control chip CC through the penetrating electrodes TSV 3  and TSVC. Write data output from the internal circuit  24  of the control chip CC is output to the bidirectional data bus DB via the driver circuit CD and supplied to the memory chip MC 2  through the penetrating electrodes TSVC and TSV 3 . The memory chip MC 2  supplies the write data on the bidirectional data bus DB to the internal circuit  22  via a receiver circuit MR 2 . In transmission of these signals, the signals pass through two bonding points of the bump electrodes, that is, the bonding point of the top-surface bump FB 2  and the back-surface bump BB 3  and the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. 
         [0047]    Read data output from an internal circuit  23  of the memory chip MC 3  is output to the bidirectional data bus DB via a driver circuit MD 3  and supplied to the control chip CC through the penetrating electrode TSVC. Write data output from the internal circuit  24  of the control chip CC is output to the bidirectional data bus DB via the driver circuit CD and supplied to the memory chip MC 3  through the penetrating electrode TSVC. The memory chip MC 3  supplies the write data on the bidirectional data bus DB to the internal circuit  23  via a receiver circuit MR 3 . In transmission of these signals, the signals pass through one bonding point of the bump electrodes, that is, the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. 
         [0048]    Each of the internal circuits  20  to  23  included in the memory chips MC 0  to MC 3  is a functional block including a memory cell array. In a normal operation mode, the driver circuit CD in the control chip CC is deactivated while read data is output from the memory chips MC 0  to MC 3 . That is, the driver circuit CD is brought into a higher impedance state relative to the bidirectional data bus DB. Similarly, the driver circuits MD in the memory chips MC 0  to MC 3  are deactivated while write data is output from the control chip CC. That is, the driver circuits MD are brought into a higher impedance state relative to the bidirectional data bus DB. 
         [0049]    As described above, the bidirectional data bus DB that connects the internal circuits  20  to  23  in the memory chips MC 0  to MC 3  with the internal circuit  20  in the control chip CC has a plurality of bonding points of the bump electrodes. Accordingly, when at least one of these bonding points is constituted by an insufficient contact (loose contact), signal qualities of read data and write data transmitted or received via the bidirectional data bus DB are deteriorated. Incidentally, when a bonding point causes a completely open failure, that is, in a case where the top-surface bump FB and the back-surface bump BB are completely separated or an insulating foreign substance is located therebetween so that the bidirectional data bus DB is divided, transmission or reception of read data and write data becomes impossible and therefore such a failure can be easily detected by an operation test. Similarly, when a part of the bidirectional data bus DB causes a short-circuit failure, that is, in a case where the penetrating electrode TSV, the top-surface bump FB, or the back-surface bump BB is in contact with another line (a power supply line, for example), transmission or reception of read data and write data becomes impossible and therefore such a failure can be easily detected by an operation test. 
         [0050]    On the other hand, when a so-called loose contact occurs, whether transmission or reception of read data and write data is possible depends on operation environments or operation conditions and thus is not easy to detect. A bonding point where a loose contact occurs has a slightly higher resistance than normal bonding points and therefore can be detected by performing resistance measurement according to a so-called four-terminal method. However, to perform the resistance measurement according to a four-terminal method, a highly accurate load circuit or measurement circuit needs to be mounted on each semiconductor chip, which increases the chip area. Furthermore, because the resistance measurement according to the four-terminal method requires a certain time, quite a long time is required to check all signal paths when a data bus width is quite large as in a wide I/O DRAM. 
         [0051]    The semiconductor device  10  according to the present embodiment solves these problems and can easily detect a position where a loose contact occurs without a load circuit or a measurement circuit mounted thereon. A method of detecting a loose contact according to the present embodiment is explained below. 
         [0052]    Turning to  FIG. 4 , the memory chip MC 0  includes a plurality of driver circuits MD 00  to MD 0 N to which a bus-fight control circuit  50  and an output-data designation circuit  60  that constitute a test circuit are connected. The bus-fight control circuit  50  and the output-data designation circuit  60  are activated in a test mode and deactivated in a normal operation mode. The bus-fight control circuit  50  is a circuit that forcibly activates any one of the driver circuits MD 00  to MD 0 N and the activated driver circuit is forcibly activated regardless of whether driver circuits of other semiconductor chips connected to the corresponding bidirectional data bus are activated. A boundary scan circuit mounted on a general DRAM can be used as the bus-flight control circuit  50 . 
         [0053]    The output-data designation circuit  60  supplies output data to the driver circuit activated by the bus-fight control circuit  50 . The output data to be supplied to the driver circuit is a 1-bit binary signal and the driver circuit outputs either a signal at a VDD level (high potential level) or a signal at a VSS level (low potential level) to the corresponding bidirectional data bus according to the binary signal. 
         [0054]    Although not shown, the bus-fight control circuit  50  and the output-data designation circuit  60  are similarly provided in other memory chips MC 1  to MC 3  and the control chip CC, and the bus-fight control circuits  50  and the output-data designation circuits  60  provided in the semiconductor chips operate in conjunction with each other under control of a tester explained later. 
         [0055]    Turning to  FIG. 5 , the test device for the semiconductor device  10  includes a tester  30  and a power supply device  40 . The tester  30  is a device for controlling the operation of the semiconductor device  10  and the power supply device  40  is a device for supplying an operation power to the semiconductor device  10 . The tester  30  has a function of monitoring a consumption current Im flowing from the power supply device  40  to the semiconductor device  10 . The tester  30  controls operations of the bus-fight control circuits  50  and the output-data designation circuits  60  provided in the semiconductor chips and identifies a position where a loose contact occurs by monitoring the consumption current Im in synchronization with the operations of the bus-fight control circuits  50  and the output-data designation circuits  60 . This operation is specifically explained below. 
         [0056]    Turning to  FIG. 6 , the tester  30  first causes the semiconductor device  10  to enter into the test mode by issuing a test command (Step S 1 ). When the semiconductor device  10  enters into the test mode, the bus-fight control circuits  50  and the output-data designation circuits  60  provided in the semiconductor chips become active. At that time, in the control chip CC, the driver circuits to be tested are all activated and all the driver circuits output data at a low level, that is, the VSS level under control of the bus-fight control circuit  50  and the output-data designation circuit (Step S 2 ). 
         [0057]    The tester  30  then selects any one of the memory chips MC 0  to MC 3  (Step S 3 ). In the selected memory chip, all the driver circuits to be tested are activated under control of the bus-fight control circuit  50 . In unselected memory chips, all the driver circuits to be tested are deactivated under control of the bus-fight control circuit  50 , which brings these driver circuits into a higher impedance state relative to the corresponding bidirectional data bus. 
         [0058]    In the selected memory chip, the driver circuits output data at a high level, that is, a VDD level in turn under control of the output-data designation circuit  60  (Step S 4 ). Outputs of other driver circuits are kept at a low level. 
         [0059]    Turning to  FIG. 7 , the horizontal axis of a table represents the time and the vertical axis represents the driver circuit number. In an example shown in  FIG. 7 , at a time i (i=0 to N), high-level data is output from a driver circuit i and outputs from other driver circuits are kept at a low level. In this way, N+1 driver circuits output high-level data in turn. 
         [0060]    When such a scan operation is performed, a so-called bus fight occurs on a bidirectional data bus to which high-level data is output. That is, because high-level data is output from a selected memory chip MC and low-level data is output from the control chip CC, a through current flows through the corresponding signal path. The through current greatly increases the consumption current Im of the semiconductor device  10 . Such a change in the consumption current Im is measured by the tester  30 . 
         [0061]    Such a measurement operation is performed for each of the memory chips MC 0  to MC 3  (Steps S 3  to S 5 ) and, after the measurement operation is performed for all the memory chips MC 0  to MC 3 , a change in the consumption current Im is evaluated by the tester  30  (Step S 6 ). 
         [0062]    Turning to  FIG. 8A , when the memory chip MC 0  is selected, the current path P 0  through which a through current flows passes four penetrating electrodes TSV 1  to TSV 3  and TSVC. At that time, there are four bonding points of the bump electrodes on the current path P 0 . That is, there are the bonding point of the top-surface bump FB 0  and the back-surface bump BB 1 , the bonding point of the top-surface bump FB 1  and the back-surface bump BB 2 , the bonding point of the top-surface bump FB 2  and the back-surface bump BB 3 , and the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. Therefore, if a current amount of the through current flowing through the current path P 0  is small, at least one of these four bonding points is possibly in a loose contact. 
         [0063]    Turning to  FIG. 8B , when the memory chip MC 1  is selected, the current path P 1  through which a through current flows passes three penetrating electrodes TSV 2 , TSV 3 , and TSVC. At that time, there are three bonding points of the bump electrodes on the current path P 1 . That is, there are the bonding point of the top-surface bump FB 1  and the back-surface bump BB 2 , the bonding point of the top-surface bump FB 2  and the back-surface bump BB 3 , and the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. Therefore, if a current amount of the through current flowing through the current path P 1  is small, at least one of these three bonding points is possibly in a loose contact. 
         [0064]    Turning to  FIG. 8C , when the memory chip MC 2  is selected, the current path P 2  through which a through current flows passes two penetrating electrodes TSV 3  and TSVC. At that time, there are two bonding points of the bump electrodes on the current path P 2 . That is, there are the bonding point of the top-surface bump FB 2  and the back-surface bump BB 3  and the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. Therefore, if a current amount of the through current flowing through the current path P 2  is small, at least one of these two bonding points is possibly in a loose contact. 
         [0065]    Turning to  FIG. 8D , when the memory chip MC 3  is selected, the current path P 3  through which a through current flows passes one penetrating electrode TSVC. At that time, there is one bonding point of the bump electrodes on the current path P 3 . That is, there is the bonding point of the top-surface bump FB 3  and the back-surface bump BBC. Therefore, if a current amount of the through current flowing through the current path P 3  is small, this bonding point is possibly in a loose contact. 
         [0066]    Turning to in  FIG. 9A , as a result of successive scanning of a plurality of driver circuits at a high level, the consumption current Im greatly decreases at the time of driving a fifth driver circuit. A decrease in the consumption current Im results from an increase in resistance of the current path P 0 , which means that the current path P 0  corresponding to the fifth driver circuit includes a position where a loose contact occurs. 
         [0067]    On the other hand, turning to  FIG. 9B , a great decrease in the consumption current Im does not occur even when a plurality of driver circuits are successively scanned at a high level. This means that the current path P 1  corresponding to the driver circuits does not include any position where a loose contact occurs. 
         [0068]    Therefore, by synthesizing the measurement results shown in  FIGS. 9A and 9B , it is found that a bonding point included in the current path P 0  corresponding to the fifth driver circuit and not included in the current path P 1  corresponding to the fifth driver circuit, that is, the bonding point of the top-surface bump FB 0  and the back-surface bump BB 1  is in a loose contact. When such an evaluation is performed for all bonding points, all the positions where a loose contact occurs can be identified. After the evaluation of loose contacts is completed, an exit command is issued to cause the semiconductor device  10  to exit from the test mode (Step S 7 ). This completes a series of the test operation. 
         [0069]    As described above, with the test method for the semiconductor device according to the present embodiment, positions where a loose contact occurs can be easily identified only by monitoring the consumption current Im by the tester  30  while successively scanning a plurality of driver circuits. Accordingly, positions where a loose contact occurs can be rapidly identified without mounting a highly accurate load circuit or measurement circuit on each semiconductor chip. A bidirectional data bus including a loose contact can be replaced by an auxiliary bidirectional data bus to relieve a failure. 
         [0070]    While all the driver circuits in the control chip CC are set to a low level and the driver circuits in a selected memory chip MC are set to a high level in turn in the test method mentioned above, the test method according to the present invention is not limited thereto. It is also possible to conversely set all the driver circuits in a selected memory chip MC to a low level and to set the driver circuits in the control chip CC to a high level in turn. In this case, while a current flows in the opposite direction, an evaluation identical to that explained above can be performed. Also in this case, the driver circuits included in unselected memory chips need to be in a high impedance state. 
         [0071]    While a through current is caused to flow by causing a bus fight between the control chip CC and each of the memory chips MC in the test method mentioned above, a through current can be caused to flow by causing a bus fight between two of the memory chips MC. 
         [0072]    Turning to  FIG. 10A , because there is only one bonding point of the top-surface bump FB 0  and the back-surface bump BB 1  on the current path P 0  to be tested in this case, whether a loose contact occurs in this bonding point can be evaluated. Turning to  FIG. 10B , because there is only one bonding point of the top-surface bump FB 1  and the back-surface bump BB 2  on the current path P 1  to be tested in this case, whether a loose contact occurs in this bonding point can be evaluated. Turning to  FIG. 10C , because there is only one bonding point of the top-surface bump FB 2  and the back-surface bump BB 3  on the current path P 2  to be tested in this case, whether a loose contact occurs in this bonding point can be evaluated. 
         [0073]    Turning to  FIG. 11 , it is also preferable to connect the limiter circuit  70  to the driver circuit D. The limiter circuit  70  limits an amount of a current flowing through the driver circuit D and is activated by the bus-fight control circuit  50 . When the limiter circuit  70  is used, an amount of a through current flowing when a bus fight is caused in a test mode is substantially constant, which increases accuracy in the evaluation by the tester  30 . The limiter circuit  70  can be provided for each driver circuit D or can be commonly provided for a plurality of the driver circuits D. 
         [0074]    While the method of detecting a loose contact occurring in a so-called bidirectional data bus has been explained above, a loose contact can be detected even in a unidirectional data bus such as an address bus or a command bus by the same method as that explained in the present embodiment when a driver circuit for a bus-fight is added. Because the address bus and the command bus are buses for transmitting a signal (an address or a command) for accessing a memory cell array in a normal operation mode, these buses are unidirectional buses from the control chip CC to the memory chips MC 0  to MC 3 . 
         [0075]    Turning to  FIG. 12 , an internal circuit  24   a  included in the control chip CC is an address output circuit that outputs predetermined bits of an address signal. Internal circuits  20   a  to  23   a  included in the memory chips MC 0  to MC 3  are address input circuits that receive the predetermined bits of the address signal, respectively. Because the internal circuits  20   a  to  23   a  are circuits dedicated to reception, it suffices to connect receiver circuits MR 0  to MR 3  at the previous stage thereof, respectively. However, in the example shown in  FIG. 12 , bus-fight driver circuits BD 0  to BD 3  for detecting a loose contact occurring on the address bus are added thereto, thereby enabling a bus fight to occur. In this way, also in a unidirectional bus such as an address bus or a command bus, a loose contact can be detected by addition of the bus-fight driver circuits. 
         [0076]    It is unnecessary to provide the bus-fight driver circuit for each bus and one driver circuit can be commonly assigned to a plurality of address buses AB 0  to ABm as shown in  FIG. 13 . In an example shown in  FIG. 13 , one driver circuit BD is assigned to m+1 address buses AB 0  to ABm. By turning ON one of switches SW 0  to SWm with the bus-fight control circuit  50 , a bus fight can be caused on an arbitrary address bus in a test mode. Because this circuit configuration can reduce the number of driver circuits to be added for a bus fight, an increase in the chip area can be suppressed to the minimum. 
         [0077]    It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention. 
         [0078]    The present invention enables an evaluation in a case where two semiconductor chips are stacked on each other in such a manner that the bump electrodes are bonded as to whether a loose contact occurs in the corresponding bonding point. Therefore, a structure of a signal path including this bonding point is not particularly limited. Accordingly, while each signal path includes the penetrating electrodes TSV in the present embodiment, the present invention is not limited thereto. 
         [0079]    Furthermore, while the semiconductor device including the memory chips MC 0  to MC 3  and the control chips CC stacked on each other has been explained in the present embodiment as an example, types of the semiconductor chips to be stacked are not limited thereto.