Abstract:
Apparatus and method for eliminating cross conduction of self-driven synchronous rectifiers in power converters caused by non-idealized ringing of parasitic capacitances and inductors. In an exemplary embodiment, the apparatus includes synchronous rectifiers or some hybrid topology having at least one synchronous rectifier coupled to a damping circuit having at least one switching device. The switching device is activated (ON) at a time when at least one of the synchronous rectifiers is supposed to remain inactive (OFF). Accordingly, when the switching device is ON, the device effectively dampens any ringing present at the synchronous rectifier that may cause the rectifier to inappropriately transition ON. The damping circuit of the present invention utilizes the same signals present to control the synchronous rectifier(s) and requires no additional control circuitry. Additionally, the damping circuit dramatically improves the efficiency of self synchronous power converters and is topology independent.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to power converters, and more particularly, to power converters that employ self-driven synchronous rectifiers. 
     BACKGROUND OF THE INVENTION 
     Power converters that employ self-driven synchronous rectifiers are becoming increasingly popular in the power industry today, because of their compact size and high efficiency. For instance, one particular class of self-driven synchronous rectifier circuits employing active clamp topologies may attain conversion efficiencies exceeding 90%, (e.g., a 48 V to 5 V DC-to-DC converter). 
     Nevertheless, the efficiency of self-driven synchronous rectifiers, are often substantially reduced by non-idealized parasitic elements, such as: (1) stray inductances introduced by component interconnections, (2) transformer leakage inductances, (3) body capacitances of the synchronous rectifiers, (4) and other related parasitic phenomena. Such parasitic elements form high frequency resonant circuits which can oscillate (generating a &#34;ringing&#34;) as the synchronous rectifier gates transition between ON-and-OFF and OFF-and-ON. As result, during transition periods, the ringing creates a momentary short circuit of the synchronous rectifiers, allowing the synchronous rectifier to simultaneously &#34;cross conduct&#34; for brief periods of time. Such simultaneous conduction (i.e., cross conduction) can be a significant source of power loss and inefficiency for self-driven synchronous rectifiers. 
     Cross conduction and ringing is becoming more troublesome as power converter designs migrate to very low output voltages (e.g., 1.5 V to 2 V). Low output voltage converters often require the use of low-threshold-voltage type Metal Oxide Silicon Field Effect Transistors (MOSFETs) (typically less than &lt;2.5 volts), because voltages available at the winding terminals of such transformers are no longer sufficient to adequately drive traditional power MOSFETs, (e.g., 10 volt gate drive). Unfortunately, low threshold MOSFETs are considerably more susceptible to cross conduction than conventional 10 volt drive power MOSFETs. 
     What is needed, therefore, is way to substantially eliminate cross conduction of rectifiers in self-driven synchronous converters without introducing unnecessary circuit complexity or additional parasitic loss mechanisms. 
     SUMMARY OF THE INVENTION 
     The present invention is directed an apparatus and method for substantially eliminating unwanted cross conduction of self-driven synchronous rectifiers, in power converters, caused by parasitic ringing. 
     In a method exemplary embodiment, a self-driven rectifier power converter employs first and second self-driven synchronous devices each having respective activation terminals. During a first time period, when the first self-driven synchronous device is active and the second self-driven synchronous device is inactive, a switching device is activated to dampen any unwanted ringing on the activation terminal of the second self-driven synchronous device. In an other exemplary embodiment, a second switching device is employed to dampen any unwanted ringing on the activation terminal of the first self-driven synchronous device by activating the second switching device at the second time period when the first self-driven synchronous device is inactive. 
     In another exemplary embodiment, an apparatus includes synchronous rectifiers or some hybrid topology having at least one synchronous rectifier coupled to a damping circuit having at least one switching device. The switching device is activated at a time when at least one of the synchronous rectifiers is supposed to remain inactive. Accordingly, when the switching device is active, it effectively dampens any ringing present at the synchronous rectifier that may inadvertently transition the rectifier to activate. 
     One feature of the present invention is to provide improved efficiency to self-driven synchronous rectifiers, by actively damping unwanted parasitic ringing on the activating terminals of the self-driven synchronous rectifiers. This prevents the rectifiers from conducting at inappropriate times. 
     Another feature of the present invention is the ability to employ drive signals, already present in synchronous rectifiers, to control the switching device(s). Thus, power converters, that employ the present invention, do not require additional control circuitry and remain self commutating. 
     Still further, the present invention is topology independent and can be used to improve the performance of any power circuit topology employing self driven synchronous rectifiers with a minimum of added cost and complexity. 
     Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be described with reference to the accompanying drawings, wherein: 
     FIG. 1 is a simplified circuit diagram of an exemplary power converter with an active clamp topology. 
     FIG. 2 shows idealized voltage waveforms of gate drive voltages for the gate-to-source voltage V GS  of synchronous rectifiers of FIG. 1, as well as an idealized drain current, I DRAIN  of a particular rectifier of FIG. 1. 
     FIG. 3 shows one example of many possible parasitic elements introduced into a practical implementation of the power converter 100 circuit diagram of FIG. 1. 
     FIG. 4 shows non-idealized voltage waveforms of gate (or activation terminal) drive voltages for the gate-to-source voltage V GS  of synchronous rectifiers of FIG. 3 as well as a non-idealized drain current, I DRAIN  of one rectifier shown in FIG. 3. 
     FIG. 5 is a circuit diagram of an exemplary power converter with an active clamp topology and damping circuitry, according to an exemplary embodiment of the present invention. 
     FIG. 6 is a circuit diagram showing a converter with a resonant reset forward topology including synchronous rectifiers and a damping gate drive circuit, according to an alternative exemplary embodiment of the present invention. 
     FIG. 7 is a circuit diagram of a converter with an active clamp hybridge topology including self driven synchronous rectifiers and the active damping gate drive circuit, according to alternative exemplary embodiment of the present invention. 
     FIG. 8 is a circuit diagram of an asymmetrical half bridge converter including a hybridge rectifier and self driven synchronous rectifiers, according to alternative embodiment of the present invention. 
     FIG. 9 is a circuit diagram of a converter with two transformers, according to still another alternative exemplary embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed an apparatus and method for substantially eliminating unwanted cross conduction of self-driven synchronous rectifiers, in power converters, caused by parasitic ringing. FIGS. 5-9 illustrate various exemplary embodiments of the present invention. 
     Before referring to these Figures, the problem of cross conduction can be better understood by considering the operation of an example conventional power converter. FIG. 1 is a circuit diagram of an exemplary power converter 100 with an active clamp topology. The power converter 100 includes on the primary side of the transformer 110, an active clamp topology including two switches 104 and 106 and a clamp capacitor 102. The power converter 100 on the secondary side of the transformer 110 employs a center tapped output and includes self-driven synchronous rectifiers 116 and 118 cross connected by their gate G and drain D via lines 124 and 126. This cross connection scheme naturally prevents the two rectifiers 116 and 118 from conducting simultaneously, because as one rectifier 116 or 118 turns ON (its drain to source voltage V GS  becomes zero) it automatically shorts the gate G to source S terminals of the other rectifier 116 or 118, thus preventing it from conducting. Simultaneous conduction is therefore not possible in this idealized converter 100. For example, FIG. 2 shows idealized voltage waveforms of gate drive voltages for the gate-to-source voltage V GS  of synchronous rectifiers 116 and 118, as well as an idealized drain current, I DRAIN  of rectifier 118, shown in FIG. 1. Referring back to FIG. 1, also shown is an output inductor 120 and capacitor 122, but neither are germane to the discussion at hand and are readily understood by those skilled in the art. For a more detailed discussion of such a converter and its operation, please refer to U.S. Pat. No. 5,303,138, entitled Low Loss Synchronous Rectifier for Application to Clamped-Mode Power Converters, to Rozman, issued Apr. 12, 1994, commonly assigned and incorporated herein by reference in its entirety. 
     Unfortunately, practical circuits contain parasitic inductances and capacitances, which can dramatically alter the operation of a circuit from its idealized form. FIG. 3 shows one example of many possible parasitic elements 302, 304, 306, 308, 310, 312, 314, 316, introduced into a practical implementation of the power converter 100 circuit diagram of FIG. 1. It should be noted that the parasitic elements elements 302, 304, 306, 308, 310, 312, 314, 316 shown are most pertinent to the present discussion, but many others exist. Of particular importance are the inductances 302, 304, 306, 308, 310, 312 in series with the gate G, drain D and source S terminals, and the gate G to source S and gate G to drain D capacitances 314 and 316 of the rectifiers 116 and 118. 
     Accordingly, as the gate to source voltages V GS  of the rectifiers 116 and 118 transition from low to high (or high to low), the parasitic resonant elements 302, 304, 306, 308, 310, 312, 314, 316 are excited and a &#34;ringing&#34; (e.g., 402 of FIG. 4) occurs on the activation terminals (e.g., gates GS) of the rectifiers 116 and 118. For example, FIG. 4 shows a non-idealized voltage waveforms of gate (activation terminal) drive voltages for the gate-to-source voltage V GS  of synchronous rectifiers 116 and 118, as well as a non-idealized drain current, I DRAIN  of rectifier 118. While this type of ringing 402 naturally occurs in most power converters, ringing occurring after rectifier 118 turns OFF (inactive) causes the most concern, because the synchronous rectifier 118 can turn back ON (active) if the amplitude of the ring is high enough. Note the drain current I DRAIN  118 during the time a resonant peak 406 exceeds a threshold voltage V THRESHOLD  a current spike 408 is realized in the drain current I DRAIN  of rectifier 118. Current flow in rectifier 118 is particularly lossy at this time, because the drain voltage of rectifier 118 is at its maximum. As a result, the current spike 408 caused by parasitic ringing 402, and simultaneous conduction during the peaks 406 of the parasitic ringing excitation, can be a significant source of loss in a practical converter 100. 
     FIG. 5 is a circuit diagram of an exemplary power converter 500 with an active clamp topology and damping circuitry 501, according to an exemplary embodiment of the present invention. In this exemplary embodiment, the damping circuitry 501 is added to damp ringing associated with the parasitic elements in synchronous rectifiers described above with reference to FIGS. 3 and 4. 
     The damping circuitry 501, includes switches 502 and 504. Essentially, switches 502 and 504 form a second cross connected pair, where the drain D of switch 502 is connected to the gate G of switch 504, via line 506, and the drain D of switch 504 is connected to the gate G of switch 502, via line 508. The gate terminals of rectifier 116 and switch 502 are connected together and the gate terminals of rectifier 118 and switch 504 are also tied together. 
     Thus, whenever the gate G voltage of rectifier 116 is high, the gate G voltage of switch 502 is high, rendering switch 504 conducting and directly shorting the gate G terminal of rectifier 118. This action directly shorts out the gate-to-source capacitance of rectifier 118 (shown as 316 in FIG. 3) and dampens any parasitic oscillation on the gate G of rectifier 118. Therefore, rectifier 118 remains inactive (OFF) whenever rectifier 116 is active (ON), preventing any parasitic induced cross conduction and enhancing overall converter efficiency. As is readily apparent to those skilled in the art, a similar analysis can be carried out for the rectifier 118 and switch 502, showing how a positive gate voltage on rectifier 118 ensures a zero gate voltage on rectifier 116. 
     The damping circuit 501 is also self commutating. That is, no additional control circuitry is required to operate the active damping circuit 501. The circuit 501 uses drive signals already present in the converter 500 to also directly control the active damping circuit 501. Thus, a major efficiency advantage is achieved by circuit 501 with a minimum of added cost and complexity. 
     It is desirous when fabricating converter 500 to observe proper placement of the active damping switches 502 and 504. The problem of parasitic ringing arises in part because of parasitic interconnect inductance between rectifiers 116 and 118. If the interconnect length between the drain D of 116 and the gate G of 118 (and vice versa) were effectively zero, there would be no need for the active damping circuit 501. However, zero interconnect length is not possible in practical circuits. It is therefore extremely advantageous to place the switching devices 502 and 504 as close as possible to 116 and 118, respectively. A lengthy interconnect between switch 502 and rectifier 116, for example, would introduce the same parasitic inductances into the loop that switch 502 is intended to damp out. However, if proper attention is given to component placement, switches 502 and 504 then it is possible to effectuate damping of the previously described parasitic ringing. 
     The circuit 501 is very economical. Switches 502 and 504 can be very small when compared to rectifiers 116 and 118. For example, in a practical circuit rectifiers 116 and 118 are often realized with large die area MOSFETs packages such as a D 2  PAK, whereas switches 502 and 504 can be realized with much smaller SOT23 size packages. Very small transistors can be used for switches 502 and 504, because they are not required to carry any substantial power, nor are they required to charge and discharge the gates of rectifiers 116 and 118. Rather, switches 502 and 504 are only required to dissipate the energy in the parasitic resonant circuits and on the gate terminals G of rectifiers 116 and 118, which is typcially quite small. Thus, by employing the damping circuit 501 according to the present invention, a substantial improvement in overall converter efficiency is realized by adding only one or more, very small and inexpensive switches 502 and 504. 
     In FIG. 5, rectifiers 116 and 118 and switches 502 and 504 are shown as N-channel MOSFETs. While the use of MOSFETs provide a very economical embodiment of the active damping circuit, other switch technologies would also prove effective, as would be appreciated by those skilled in the relevant art For example, npn bipolar transistors could also be used in place of switches 502 and 504, provided that the appropriate value of base resistor were added. Other switch technologies, GaAs FETs or JFETs, for example, could also be used, provided proper drive considerations were addressed. Furthermore, the damping circuit 501 is not topology dependent and may be used with any type of self-driven synchronous rectifier. Still more, it should also be appreciated by those skilled in the relevant art, that only one switch 502 or 504 may be employed instead of the cross connected circuit 501, shown in FIG. 5, but with less efficiency. 
     To further appreciate the advantages of the present invention, testing of a converter substantially similar to the exemplary converter in FIG. 5 was conducted. The results of the testing yielded the essentially the following results: 
     
         ______________________________________Input voltage   Output voltage                Output current                           Output power______________________________________36 V-75 V   3.3 V        15 A       49.5 W______________________________________ 
    
     Efficiency and power dissipation was measured for the converter 500 both with the active damping gate drive circuit 501, and without it. The results are shown in Table A below. 
     
                       TABLE A______________________________________      Input      volt-           Output      age  current Efficiency                            Power dissipation______________________________________with damping circuit        36     15      88.5%  6.43 W&#34;            55     15      88%    6.75 W&#34;            75     15      86.8   7.52 Wwithout damping circuit        36     15      88     6.75 W&#34;            55     15      87%     7.4 W&#34;            75     15      85.5   8.39 W______________________________________ 
    
     Table B illustrates the savin GS  in internal power dissipation afforded by the use of the active damping gate drive circuit: 
     
                       TABLE B______________________________________Input voltage      Power savings                 % of total power dissipated______________________________________36         0.32 W     4.9%55         0.65 W     9.6%75         0.87 W     11.5%______________________________________ 
    
     Clearly, the improvement in efficiency is substantial, particularly at a 75 V input. This simple and inexpensive circuit 501 reduced internal power dissipation by 11.5%, which directly translates into better thermal performance, or perhaps more useable output power in a given thermal environment. The power savin GS  for lower output voltage converters may be even greater. 
     It is envisioned that the above described exemplary embodiment drive circuit 501 can be used with any self synchronous rectifier topology. For example, FIG. 6 is a circuit diagram showing a converter 600 with a resonant reset forward topology including synchronous rectifiers 604 and 606 and a damping date drive circuit 501, according to an alternative exemplary embodiment of the present invention. While this type of topology is generally less efficient than an active clamp topology, the described active damping circuit 501 is still applicable, as is appreciated by those skilled in the art. 
     Another topology is shown in FIG. 7, which is a circuit diagram of a converter 700 with an active clamp hybridge topology including self driven synchronous rectifiers 712 and 714 and the active damping gate drive circuit 501, according to alternative exemplary embodiment of the present invention. The converter 700 is simply an active clamp front end (capacitor 702 and MOSFETs 704 and 706) with a current doubler rectifier circuit configured as self driven synchronous rectifiers 712, 714. 
     Still another topology is shown in FIG. 8, which illustrates a circuit diagram of an asymmetrical half bridge converter 800 including a hybridge rectifier with self driven synchronous rectifiers 814 and 816, according to alternative embodiment of the present invention. The active damping gate drive circuit 501 could be used to improve the performance of this converter 800. 
     FIG. 9 is a circuit diagram of a converter 900 with two transformers 110A and 110B, according to still another alternative exemplary embodiment of the present invention. The gate drive signals for the synchronous rectifiers 916 and 918 of FIG. 9 are identical to those of FIG. 5, and as such the principles of the active damping gate drive circuit 501 apply equally. In addition, the active damping gate drive circuit 501 could be applied to the drive scheme described in U.S. Pat. No. 5,590,032 to Bowman et al., entitled Self Synchronized Drive Circuit for a Synchronous Rectifier in a Clamped-Mode Power Converter, issued Dec. 31, 1996, and commonly assigned (the &#39;032 patent), incorporated herein by reference in its entirety, as would be appreciated by those skilled in the relevant art, although a specific figure is not shown. In particular, the gate drive voltage limiting FETs described &#39;032 patent are completely compatible with the active damping gate drive circuit 501 described herein. 
     In summary, the active damping gate drive circuit 501 is topology independent and can be used to improve the performance of any power circuit topology employing self driven synchronous rectifiers. 
     For a more detailed example of alternative synchronous rectifier topologies that may employ the drive circuit 501 of the present invention, see the following patents, all incorporated herein in their entirety: (1) U.S. Pat. No. 5,528,482, to Rozman, entitled Low Loss Synchronous Rectifier for Application to Clamped-Mode Power Converters, issued Jun. 18, 1996 and commonly assigned; (2) U.S. Pat. No. 5,274,543 to Loftus, entitled, Zero Voltage Switching Power Converter Circuit with Lossless Synchronous Rectifier Gate Drive, issued Dec. 28, 1993 and commonly assigned; and (3) U.S. Pat. No. 5,291,382 to Cohen, entitled Pulse Width Modulated DC/DC Converter With Reduced Ripple Current Component Stress and Zero Voltage Switching Capability, issued Mar. 1, 1994. 
     While preferred embodiments have been set forth, various modifications, alterations, and changes may be made without departing from the spirit and scope of the present invention as defined in the specification and in the appended claims.