Abstract:
In a computer system capable of being configured in a multiprocessor system, a plurality of virtual machines are grouped by object of use to define a plurality of processor groups. Each processor has an identifier for a processor group to which it belongs. When an instruction which requires synchronous execution among the processors is executed, the processor identifies the processor group to which it belongs and requests the synchronous execution of the instruction to only the processors in the group. In another aspect, each processor which has a request for execution refers to its own identifier to determine if the request is from a processor of the same group in order to determine whether it should execute the instruction or not. When the processor completes the execution of the instruction, it sends an end signal to the requesting processor so that another instruction from other processors in the same group can be executed.

Description:
This application is a continuation of application Ser. No. 260,783, filed Oct. 21, 1988 now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a multiprocessor system of a computer, and more particularly to control method and apparatus suitable for constructing a virtual machine on a multiprocessor system. 
     In a conventional multiprocessor system such as System 370 of International Business Machines Corporation, when one of processors of the multiprocessor system executes an instruction which requires signaling of the processor, the signaling is effected to all processors of the system to synchronize the execution. Such instructions include a purge translation buffer extended (PTLBE) instruction, an invalidate page table entry (IPTE) instruction, a set storage key extended (SSKE) instruction, and a reset reference bit extended (RRBE) instruction. 
     The PTLBE instruction is an instruction for a multiprocessor system and it requests to all processors of the system to invalidate all entries in the address translation look-aside buffer which have been valid so far. Accordingly, when the PTLBE instruction is issued, the processor which has issued that instruction invalidates the address translation look-aside buffer of its own and signals to all other processors to invalidate their address translation look-aside buffers. The other processors of the system respond to the signal to invalidate the address translation look-aside buffers of their own. The invalidating processes are effected in synchronism in the system, and when the invalidation of the address translation look-aside buffers of all processors has been completed, an instruction next to the signaling instruction is executed. 
     The IPTE instruction is an instruction used when a correspondence relationship between a real page in a real memory and a virtual page in a virtual memory no longer exists because of page-out processing. This instruction sets an invalid bit (I bit) of an entry of a page table to be invalidated to &#34;1&#34;. Since the page to be invalidated may have already been registered in the address translation table, the content of the address translation look-aside buffer is checked, and the entry of the address translation look-aside buffer whose page field and page table start address used to register the entry of the address translation look-aside buffer are identical to a page field and a page table start address designated by the IPTE instruction and which is identical to the content of the page table entry designated by the IPTE instruction is invalidated. If the system is of multiprocessor configuration, the respective processors signal as they do for the PTLBE instruction to purge the entries of the address translation look-aside buffers of all processors. 
     The SSKE instruction designates a real address to modify a main storage key of the corresponding page. Since the real page address whose main storage key is to be modified and the corresponding main storage key may have already been stored in the address translation look-aside buffer, the main memory key of the entry corresponding to the real page address is updated when the SSKE instruction is issued. The SSKE instruction is also executed in synchronism among the processors of the multiprocessor as is done by the aforementioned instruction. 
     In a virtual machine system, when the above instruction is executed by a virtual machine (VM), a virtual machine control program (VMCP) which controls the virtual machine system grasps the event and simulates the instruction to execute the instruction. 
     When the virtual machine issues the IPTE instruction, the control program (VMCP) of the virtual machine system determines the contents of a page table entry based on the address translation table start address of the virtual machine, translates it to an absolute address of the virtual machine, further translates it to a real address of a real machine, and issues the IPTE instruction by utilizing a page table for the control program. When the control program issues the PTLBE instruction, the entire address translation look-aside buffer is purged. As a result, the entries of the address translation look-aside buffers related to the virtual machines other than the one which issued the IPTE instruction or the entries of the address translation look-aside buffers related to the control program are also invalidated. This may reduce performance of other virtual machines. In order to avoid it, the IPTE instruction is issued to invalidate the entry of the address look-aside translation buffer related to the virtual machine as much as possible. 
     The simulation by the VM control program (VMCP) of the IPTE instruction issued by an operating system (OS) on the VM has thus been described. Since an overhead of the VM is increased by this method, the IPTE instruction issued by the OS on the VM may be directly executed by hardware. Even in such a case, if the OS on the VM operates on only one of the processors of the system, the hardware cannot recognize it and it sends a signal to all processors of the multiprocessor system to request synchronous execution. Accordingly, the same problem as that described above takes place. 
     Where the virtual machine operates on a plurality of processors, it is possible for the virtual machine to occupy a specific processor for operation. In this case, if the IPTE instruction is issued by the virtual machine which occupies the processor, the address translation look-aside buffer related to the virtual machine is limited to the address translation look-aside buffer which belongs to the processor which has operated the virtual machine. However, in the prior art, when the entry of the address translation look-aside buffer is to be purged as a result of executing the IPTE instruction issued by the virtual machine, a signal is sent to other processors to unconditionally search corresponding entries in the address translation look-aside buffers of all the processors and to purge them if any. All processors execute the instruction synchronously and the next instruction is executed after the invalidation of the entries of the address translation look-aside buffers of all processors has been completed. 
     As described above, when the virtual machine operates on only one processor, the entry of the address translation look-aside buffer which the virtual machine may use is limited to the one belonging to that one processor but the signaling is effected to the entire system. As a result, excess purge of the entry of the address look-aside translation buffer due to the communication overhead among the processors and the execution of the IPTE instruction by other processors is possibly effected. This affects the efficiency of the overall system and lowers the system performance. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a multiprocessor system which groups processors in accordance with a desired system operation condition so that signaling among the processors is limited to those processors which need such signaling. 
     It is another object of the present invention to provide an instruction execution method to improve performance in a computer system which configures a virtual machine by a multiprocessor. 
     In accordance with a first conceptual feature of the present invention, a plurality of processors of a system are variably grouped in accordance with a desired configuration condition. Group identification information is set to each processor. A processor which received an instruction which requires signaling identifies a group to which it belongs based on the group identification information assigned thereto, and responds to the signaling related to the processor group to which it belongs but invalidates the signaling which is not related to its own group. Each processor has a group identification information hold mechanism and a signaling selective response mechanism. 
     In accordance with a second feature of the present invention, in a computer system having processors sharing a main memory, the processors are grouped and a group identifier representing a group to which each of the processors belongs is assigned to each processor. When a processor issues an instruction such as the IPTE instruction which needs synchronous execution, a signal for requesting synchronous execution of the instruction is sent to only the processors belonging to its own group. Each processor has a group identify mechanism and a selection mechanism for selectively sending the synchronous execution request signal. 
     In the multiprocessor system which configures the virtual machine system in accordance with the first feature, each processor has, as the group identification means, a processor group register for storing a processor group to which it belongs, and each processor can identify the processors within its group by referring the content of its own processor group register. 
     When each processor communicates with others, a sending processor sends the content of the processor group register together with the communication information. A receiving processor extracts the signal relating to the processor group from the signal information sent from the sending processor, compares it with the content of its own processor group register, and if they are equal, accepts the signal and responds to the signal. If they are not equal, the signal is not accepted. In this manner, the processor group for the signal is defined and the communication overhead among the processors is reduced, the excess purge of the address translation look-aside buffers of the processors are prevented and the system performance is enhanced. 
     In accordance with the second feature, the processors are grouped. Each processor has, as group identification means, a register for identifying a processor group to which it belongs. When each processor communicates with other processors to request processing, each processor refers the group register or group identification means and sends the execution request signal only to the processors belonging to its own group. The receiving processor stores the identification of the sending processor and sends back a signal required to the synchronous execution. Thus, the synchronous execution can be attained in the processor group. The groups may be changed as required. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A shows a diagram for explaining a basic concept of the present invention, 
     FIG. 1B shows a diagram illustrating an essential portion of a multiprocessor system according to one embodiment of the present invention, 
     FIG. 2 shows a basic block diagram of a hardware configuration for realizing a processor group of the present invention, 
     FIG. 3 shows a format of a parameter stored in a memory when synchronous execution is effected among processors, 
     FIG. 4 shows a block diagram of a hardware configuration for checking a parameter when a synchronous execution request signal is accepted, 
     FIG. 5 shows a block diagram of a parameter generation mechanism for sending the synchronous execution request signals, 
     FIG. 6 shows a conceptual view of a microprogram operated among the processors for the synchronous execution, 
     FIG. 7 shows a general flow by a microprogram in requesting the synchronous execution, 
     FIG. 8 shows a general flow by a microprogram in accepting the synchronous execution request signal, and 
     FIG. 9 shows a format of a control instruction for controlling the processor group. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1A illustrates a basic concept of the present invention. IP0, IP1, IP2 and IP3 denote processors which constitute a multiprocessor sharing a main storage 1. In FIG. 1A, four multiprocessors are shown although any number of processors may be included in the system. The main storage 1 stores a virtual machine control program (VMCP) which defines virtual machines VM 1 , VM 2 , VM 3 , VM 4 , VM 5  and VM n  and controls those VM&#39;s. When the multiprocessor system is operated, it may be desired to use the processors by object of use to improve the overall system operation efficiency. For example, in FIG. 1A, the processors IP0 and IP1 may be used for on-line processing, the processor IP2 may be used for batch processing, and the processor IP3 may be used for program development. In such a case, the processors are grouped and each group is assigned with a particular object of use. In each processor group, some virtual machine (VM&#39;s) are operated and an operating system (OS) which fits to the object of use is run on the VM&#39;s so that the object of use of the processor group is attained. The VM&#39;s are operated only in the processor group to which they belong. For example, in FIG. 1A, VM 1  and VM 2  are operated by only the on-line processing processor group IP0 and IP1, VM 3  is operated only by IP2, and VM 4 , VM 5  and VM n  are operated only by IP3. In other words, VM 1  and VM 2  occupy IP0 and IP1, VM 3  occupies IP2, and VM 4 , VM 5  and VM n  occupy IP3. Thus, the performance of each processor group is not affected by other processor groups. The method for defining the processor group and the method for defining the VM&#39;s which operate in the processor group are not fixed for the system, and they may be previously defined when the system is generated, or they may be defined or amended by the VMCP command after the system generation. 
     The present invention provides method and means for rapidly executing an instruction which requires synchronous execution among the processors, issued by the OS on the VM operating in the processor group. 
     One embodiment of the present invention is now explained with reference to FIG. 1B. A normal computer system comprises an instruction processor 100 for executing an instruction and a main storage 1 for storing the instructions. When the system is of multiprocessor configuration, an instruction processor is added to the system. The multiprocessor system generally comprises as shown in FIG. 2. In a multiprocessor system which shares the main storage 1, several instruction processors 100-103 for executing instructions are connected to a store control unit, and the main storage 1 is referred to by each of the instruction processors 100-103. In FIG. 2, two storage control units (SCU) 110 and 111 are provided for the main storage 1, and each storage control unit has two instruction processors 100, 101 and 102, 103 so that four processors are used in total to configure the multiprocessor system. A service processor 130 is provided, which is connected to each instruction processor through the respective SCU. When a virtual machine is constructed in such a multiprocessor system, it is possible to run the virtual machine on only a specific instruction processor. In this case, the address translation information of the virtual machine is stored only in the address translation look-aside buffers of the processors on which the virtual machine runs. Accordingly, if the processor group 120 is assigned to the instruction processors 100, 101 and 102, the synchronous execution may be effected for only the processors in the processor group 120 when the IPTE instruction, PTLBE instructions, SSKE instruction or RRBE instruction which requires the synchronous execution among the processors is executed. Thus, the system performance can be enhanced. 
     Turning back to FIG. 1B, the hardware mechanism for realizing the processor group is explained. When one of the processors of the system, for example, the processor 102 executes an instruction which requires communication among the processors (for example, IPTE instruction 610b), a signal informing it is sent to the execution unit 203a from the processor 102 through a signaling path 210. The path 210 is established between any two of IP&#39;s under control of at least one of the SCU&#39;s. The execution unit 203a responds to the signal to issue a command to the buffer unit 201 to request to fetch from the main storage 1 a parameter relating to the synchronous execution among the processors. The buffer unit 201 responds to the request to read parameter information from a specific area corresponding to the processor 102, of the system area (HSA)2 for the hardware in the storage 1, and transfers the parameter information to a signal check unit 270 where the processor group to which it belongs is compared with the processor group to which the synchronous execution requesting processor belongs. If they are equal, an equal signal is sent to the execution unit 203a through the path 230 where the instruction for the synchronous execution is executed. If the processor groups are not equal, the request signal is neglected and no execution of the requested instruction is effected. 
     When the processor 100 of its own requests the synchronous execution to other processors, it sends the synchronous execution request signal to the processor 102 other than the processor of its own through the path 210 and also sends a signal 250 to the parameter generation unit 290, which generates a parameter including information relating to the processor group necessary for the synchronous execution, transfers the signal to the buffer unit 201 through a signal line 260 and stores it in a specific area of the main storage 1. 
     The processor has a common area to store information relating to the processor group to which it belongs, and a processor group identification register 282 to store identification information of the processor group to which the processor belongs and a processor register 283 which stores the number N of processors belonging to the processor group. 
     The processor group identification register 282 includes a processor group identifier PGID. A format of the PGID may be a 31-bit register having bit addresses 0-30. For example, when bit i (0-30) is at a logical level &#34;1&#34;, the processor i belongs to the processor group, and when it is at a logical level &#34;0&#34;, the processor i does not belong to the processor group. Any format may be used so long as the processor group to which the processor belongs can be identified by referring to the content of the PGID. 
     FIG. 3 shows a content of the processing request parameter which is communicated among the processors when the synchronous execution of the processors is requested. 
     The parameter 300 is stored in the hardware system area (HSA)2 of the main storage 1 which can be referred to or updated only by the hardware. The parameter consists of an unconditional synchronization request bit 301, a destination code (DEST) 302, a valid flag 303, a processor group identifier (PGID) 304 and a data area 305. 
     The unconditional synchronization request bit 301 requests the synchronous execution to all processors of the multiprocessor system. When the bit 301 is &#34;1&#34;, the check of the CPU address and the check by the processor group are not effected. 
     The destination code 302 includes the CPU address of the destination processor for which the synchronous execution is requested. This field is used when the designation of the processor address is required by, for example, a signal processor (SIGP) instruction. 
     The valid flag 303 is used to request the synchronous execution to the processors which belong to the same processor group as that the requesting processor belongs to. When the flag is &#34;1&#34;, the communication by the processor group is limited. When the flag is &#34;0&#34;, only the check for the processor address is effected. 
     The processor group identifier 304 stores the processor group identifier to which the synchronous execution requesting processor belongs. 
     The data area 305 stores the data stored in the synchronous execution requesting processor. It stores a code and data representing the type of synchronous execution. 
     FIG. 4 illustrates a signal processing of the signal check unit 270 which checks the synchronous execution request signal for the processor group as to whether the request signal belongs to the processor group. The other processor 102 issues the instruction 610b which requires the synchronous execution and the synchronous execution request signal is accepted by the execution unit 203a through the signal line 210 and the request parameter 300 shown in FIG. 3 is stored into the buffer unit 201 from the hardware system area 2. In response to storing of the request parameter 300, the information excluding the data area of the request parameter is read from the buffer unit 201 through the signal line 220b and it is stored into the register 402, which functions to divide the information into the areas shown in FIG. 3 to divide the signal. 
     The destination code 302 in the register 402 is compared by the comparator 403 with the register 281 of the common unit 280 which stores the CPU address of itself. If the destination code and the CPU address are equal, a signal is sent to the gate 407 and a signal is sent to the execution unit 203a through the OR gate 408 and the signal line 230. The gate 407 uses, as a gate control signal, a signal which is an inversion of the valid bit 303 of the register 402 through the NOT gate 404. Accordingly, when the valid bit 303 is &#34;1&#34;, that is, when the processor group is specified to effect the synchronous execution among the processors, the designation by the destination code 302 is neglected. 
     If the valid bit 303 of the latch 402 is &#34;1&#34;, the gate 405 is open and the processor group identifier of the processor group register 282 in the common unit is sent to the comparator 406, which compares the information with the information in the processor group identifier (PGID) 304 of the register 402. When the processor group identifier of the processor which has issued the synchronous execution request is equal to the processor group identifier of the processor which has accepted the signal, a signal is sent to the OR gate 408 to instruct to the execution unit 203a through the signal line 230 to accept the request. 
     When the unconditional synchronization request bit 301 of the register 402 is &#34;1&#34;, a signal is sent to the OR gate 408 to request the unconditional acceptance of the synchronous execution. 
     FIG. 5 illustrates a signal processing by the synchronous execution parameter generation unit 290 when the synchronous execution is requested. Instructions stored in the storage 1 are fetched to the buffer unit 201 and executed by the execution unit 203a. When an instruction requesting the synchronous execution among the processors is executed, the execution unit 203a classifies the instruction into (1) an instruction which requires communication to all processors of the system, (2) an instruction which requires synchronous execution of specified processors, or (3) an instruction which requires synchronous execution within the processor group, and sets the information of the parameter prepared in the register 502 in accordance with the classification. 
     The content of the unconditional synchronization request bit is determined by the execution unit 203a in accordance with the classification of the instruction and it is set into the unconditional synchronization request bit 301 of the register 502. The destination code 302 is also set therein. 
     The valid bit 303 is determined by the content of the latch 501. The latch 501 is set to &#34;1&#34; when an instruction requesting the start of limited signaling by the processor group is issued, and reset to &#34;0&#34; when an instruction requesting to terminate the limited signaling by the processor group is issued. 
     The processor group identifier 304 includes the content of the processor group register 282 in the common unit 280 of the processor group mechanism. The content of the register 282 is set when the processor issues an instruction which sets the processor group to which the processor belongs. 
     The hardware mechanism for realizing the processor group has thus been explained. Now, the control system by the microprogram for transmitting and sending signals among the processors is explained. 
     Referring to FIG. 6, when the instruction processor 102 executes an instruction which requires the synchronous execution, the buffer unit 201b fetches the instructions 610 stored in the main storage 1 and the instructions are decoded by the decoder 202b. As a result, a control signal is sent from the decoder 202b to the execution unit 203b and the instruction is executed. 
     When the instruction 610 which requires the synchronous execution among the processors is to be executed, the signal 210b for requesting the synchronous execution is sent to the execution unit 203a by the microprogram 600b in the execution unit 203b. When the instruction processor 100 receives the signal, it executes the processing requested by the microprogram 600a for the requested processing in the execution unit 203a. At the end of the processing, the end signal 210a is sent to the requesting processor 102. 
     All of the signals from the processors are checked by the processor group mechanisms 270 (i.e. 270a, 270b, . . . ), 280 (i.e. 280a, 280b, . . . ) and 290 (i.e. 290a, 290b, . . . ) in the processors and the processing is not accepted for the signal which the processor is not requested to accept. 
     In this manner, the signals are transmitted and received. 
     A method for controlling the microprogram when the synchronous execution in the processor group is limited is now explained with reference to FIGS. 7 and 8. FIG. 7 illustrates microprogram control 600b when the instruction requesting the synchronous execution is executed. 
     When the processor 102 executes the instruction 610b which requires the synchronous execution: 
     (1) The processor 102 first executes the instruction on its own processor (701), and 
     (2) Then, it sets the parameter 300 shown in FIG. 3 on the memory to request the synchronous execution to the processors of the processor group and effect the signaling 210b to all other processors (702). 
     The transmission parameter shown in FIG. 3 is set in the following manner. 
     Unconditional synchronization request bit 301 . . . 0 
     Destination CPU address 302 . . . any value 
     Valid flag 303 . . . 1 
     Processor group identifier (PGID) 304 . . . identifier of the processor group to which the processor of its own belongs. 
     Data area 305 . . . software information. Any information for hardware. 
     (3) The processor 102 then reduces one from the processor register (which includes the number of processors in the processor group to which the processor of its own belongs), to determine the number N of other processors which belong to the processor group (703), 
     (4) The processor 102 clears to zero the counter K which counts the end signals from the other processors for the synchronization (704), 
     (5) After the above steps, the processor 102 stands by until the end signals from the other processors are accepted (705), 
     (6) When the processing in the other processors is completed and the end signals 210 are accepted, the processor 102 increments the counter K which counts the event (706). 
     (7) The counters K and N are compared (707), and if K&lt;N, if the end signals have not yet been received from all processors in the processor group, the processor 102 again stands by. 
     (8) When N≦K, that is, when the end signals are received from all processors in the group, the processor 102 sends a signal 210b to request the resumption of instruction fetching to all other processors (708). 
     (9) After the above steps, the processor 102 resumes the instruction fetching (709). 
     FIG. 8 illustrates microprogram control of the processor when it receives the synchronous execution request signal. The receiving processor detects the processor group identifier (PGID) 304 in the parameter shown in FIG. 3 set by the requesting processor, by the circuit shown in FIG. 4, and conducts the process 600a only when the requesting processor is in the same processor group. 
     (1) The processor fetches an instruction to be executed from the main storage by an instruction fetching step (801), 
     (2) The processor executes the instruction (802). 
     (3) The processor checks if the synchronous execution request signal has later been received (803), and if it has not been received, it continues the instruction fetching (801) and the instruction execution (802). 
     (4) If the synchronous execution request signal has been received, the processor analyzes the signal (804). 
     (5) The processor selects the requested process (805). 
     (6) The processor executes the requested process (806). 
     (7) After the above steps, the processor sends the signal 210a to the synchronous execution requesting processor to inform the end of process (807). 
     (8) The processor then stands by until it receives the resume signal from the synchronous execution requesting processor (808). When the synchronous execution requesting processor sends the resume signal 210b, the processor resumes the execution of the instruction of its own processor. 
     In the microprogram control shown in FIGS. 7 and 8, the requesting processor sends the request signal to all processors of the system, and the receiving processor checks if the requesting processor belongs to the same processor group, and only if it belongs to the same processor group, the receiving processor conducts the requested process. At the end of the process, the processor which ended the process informs the end of process to the requesting processor. In this manner, the synchronous execution is attained when the signal processing by the processor group is limited. 
     In addition to the embodiment described above, a second embodiment is described below. 
     (1) When the processor signals the process request to the other processors after it has executed the instruction, it signals only to the processors belonging to the processor group to which it belongs. 
     (2) The requesting processor receives all the end signals from the processors in the processor group and thereafter sends a signal to resume the other processors to the processors in the processor group. 
     In the second embodiment, the signaling from the requesting processor is effected only to the processors in the processor group. Accordingly, the determination of the processor group is not required for the receiving processor. 
     To this end, each processor should have a processor group identifier. The PGID 282 shown in FIG. 1B corresponds to the identifier. The requesting processor checks the PGID 282 and signal to the corresponding processor. 
     In the sending microprogram control, the signal is sent only to the processors in the processor group in steps 702 and 708 in FIG. 7. The receiving microprogram control is the same as that shown in FIG. 8. 
     FIG. 9 shows an instruction for controlling the processor group and a format thereof. 
     An SPGIP instruction 901 is used to set at the register 282 in FIG. 1B a processor group identifier to the processors in the processor group to which it belongs. A second operand of this instruction is not used for addressing and an effective address of the operand represents the processor group identifier (PGID). 
     Specifically, of the 32-bit second operand address which is a sum of the content of the register B2 and the content of D2, the bit mask 901a consisting of bits 1-31 is the PGID. When bit i (i=1-31) is &#34;1&#34;, it means that the processor i-1 (=0-30) is in the processor group. The processor group identifier PGID can be set directly to the register 282 from the service processor 130. 
     An SNPG instruction 902 sets the number of all processors in the processor group to which the processor of its own belongs into the processor register (283 in FIG. 1). Since the number of processors designated by this instruction is information needed for the synchronous execution, it is necessary to use this instruction to set the number of processors when the synchronous execution among the processors by the processor group is to be limited. The operand of this instruction is not used for addressing and the effective address of the operand represents the number of processors. 
     A CTLPG instruction 903 controls the start and stop of the limitation of the synchronous execution among the processors by the processor group. The operand of this instruction is not used for addressing, and when the bit 31 of the effective address of the instruction is &#34;1&#34;, the limitation of the signal by the processor group is started. When it is &#34;0&#34;, the limitation of the signal is stopped. 
     In the present embodiment, the above mechanism and method are used to realize the processor group and reduce the processor overhead in controlling the virtual machine system. 
     In the present embodiment, the information in the processor register used to count the end signals for the synchronous execution from the processors in the processor group set for the synchronous execution may be stored in the main storage. 
     In one embodiment, the timing to execute the next instruction is determined by counting the end signals from the processors in the same processor group. In the other embodiment, the bit map which stores the information of the processors in the same processor group is used. A requesting processor sets a corresponding bit to a logical &#34;1&#34; state when it receives an end signal from a requested processor, and the execution of instruction is resumed when the bit map of the same processor group is in the all-&#34;1&#34; state. 
     In the present embodiment, the processor group mechanism is controlled by the instruction which determines whether the synchronous execution by the processor group is to be limited or not. In addition to this function, a mechanism for indicating an operation condition of the virtual machine may be provided, and when the processor is operating as the virtual machine, the signaling by the processor group may be limited, and when the processor shifts from the virtual machine operation to the control program operation, the mode which does not effect the synchronous execution by the processor group may be established. 
     In accordance with the present invention, the synchronous execution by the processor group may be limited. Thus, in the virtual machine system, when the virtual machine runs only on a specific processor and an instruction relating to the address translation look-aside buffer is issued from the virtual machine, it is possible to prevent the overhead of the synchronization which heretofore has been caused by the synchronous execution by all of the processors in the system. Accordingly, 30-40% of the process time required for the instruction execution for the address translation look-aside buffer of the prior art system can be saved. 
     Since the processing is limited to only the portion relating to the virtual machine in the invalidation process for the entire address translation look-aside buffer and the entries, the other portions of the address translation buffer and the entries are not purged and hence the address translation overhead increase in the system can be avoided.