Abstract:
Described herein is a module for controlling a switching converter, which includes at least one inductor element and one switch element and generates an output electric quantity starting from an input electric quantity. The control module generates a command signal for controlling the switching of the switch element and includes an estimator stage, which generates an estimation signal proportional to the input electric quantity, on the basis of the command signal and of an input signal indicating a time interval in which the inductor element is demagnetized. The control module generates the command signal on the basis of the estimation signal.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a control module for a switching converter, which includes an estimator of an input electric quantity. In addition, the present disclosure relates to a method for controlling a switching converter. 
         [0003]    2. Description of the Related Art 
         [0004]    As is known, there exist various types of switching converters, amongst which there may, for example, be cited flyback, boost, and buck converters. 
         [0005]    In general, in the field of switching converters there is particularly felt the need to have available converters that are characterized by a high power factor, as well as a low total harmonic distortion (THD) and a low zero-load power dissipation. In order to obtain the aforementioned characteristics, switching converters are known that implement, for example, a circuit layout of the type illustrated in  FIG. 1 . 
         [0006]    In detail,  FIG. 1  shows a switching power supply  1  of a flyback type, referred to hereinafter as “flyback power supply  1 ”. 
         [0007]    In greater detail, the flyback power supply  1  includes a bridge rectifier  2 , which has two input terminals, designed to receive an a.c. voltage from a supply line, and a first output terminal and a second output terminal, which are connected, respectively, to a first ground and to a first terminal of a filtering capacitor C in , the second terminal of which is connected to the first ground. The bridge rectifier  2  supplies on its own second output terminal a voltage V in (θ), referred to hereinafter as “input voltage V in (θ)”, where θ is the phase of the a.c. voltage present on the supply line. 
         [0008]    The flyback power supply  1  further comprises a flyback converter  3 , which on the primary side includes, in addition to the filtering capacitor C in , a transformer  4 , which comprises a first inductor L p  and a second inductor L s , which function respectively as primary winding L p  and secondary winding L s  and share a same magnetic core, referred to hereinafter as “core of the transformer  4 ”. Furthermore, the transformer  4  comprises an auxiliary winding L aux . A first terminal of the primary winding L p  is connected to the first terminal of the filtering capacitor C in . 
         [0009]    The flyback converter  3  further comprises a control module  15 , a resistive divider  16 , which includes a first resistor R a  and a second resistor R b , and a transistor M formed, for example, by a power MOSFET. 
         [0010]    The first resistor R a  has a first terminal and a second terminal, which are connected, respectively, to the first terminal of the filtering capacitor C in  and to a first terminal of the second resistor R b , the second terminal of which is connected to the first ground. In practice, the second terminal of the first resistor R a  and the first terminal of the second resistor R b  form a node electrically coinciding with a first input terminal MULT of the control module  15 . 
         [0011]    The flyback converter  3  further comprises a third resistor R ZCD  and a fourth resistor R s . The first and second terminals of the third resistor R ZCD  are connected, respectively, to the first terminal of the auxiliary winding L aux , the second terminal of which is connected to the first ground, and to a second input terminal ZCD of the control module  15 . The first and second terminals of the fourth resistor R s  are connected, respectively, to the source terminal of the transistor M and to the first ground. Further, the first terminal of the fourth resistor R s  is connected to a third input terminal CS of the control module  15 . Once again with reference to the transistor M, the drain terminal is connected to the second terminal of the primary winding L p , whereas the gate terminal is connected to an output terminal GD of the control module  15 , which further includes a feedback terminal FB, described hereinafter, and a fourth input terminal GND, connected to the first ground. 
         [0012]    In practice, the fourth resistor R s  enables detection of the current that flows in the primary winding L p  when the transistor M is on. In  FIG. 1 , the current that flows in the fourth resistor R s  is designated by I p  (t,θ). 
         [0013]    The flyback converter  3  further comprises a clamping circuit  20 , which is arranged between the first and second terminals of the primary winding L p  for limiting the spikes of the voltage present on the drain terminal of the transistor M, caused, for example, by parasitic inductances. 
         [0014]    On its own secondary side, the flyback converter  3  comprises a feedback circuit  22 , a diode D, referred to hereinafter as “output diode D”, and a further capacitor C out , referred to hereinafter as “output capacitor C out ”; typically, the output capacitor C out  is of an electrolytic type. 
         [0015]    The anode of the output diode D is connected to a first terminal of the secondary winding L s , whereas the cathode is connected to a first terminal of the output capacitor C out , the second terminal of which is connected to a second ground, as on the other hand also the second terminal of the secondary winding L s . In general, the voltage across the output capacitor C out  is referred to hereinafter as “output voltage V out ”. Further, the output voltage V out  represents the voltage that is to be regulated by the flyback converter  3 . In  FIG. 1 , the current that flows in the output diode D is designated by I s (t,θ). 
         [0016]    The feedback circuit  22  is connected to the first terminal of the output capacitor C out  and to the feedback terminal FB of the control module  15 . In addition, the feedback circuit  22  is configured to generate an error signal proportional to the difference between the output voltage V out  and a reference voltage, as well as for transferring the error signal on the primary side of the flyback converter  3 , generally using an opto-coupler. This transfer entails generation of a control voltage V c  on the primary side, and in particular on the feedback terminal FB of the control module  15 . In this connection, the control module  15  generates on a own node an internal voltage V int , and further has a fifth resistor R c , which is arranged between the aforementioned node and the feedback terminal FB of the control module  15 . Furthermore, the control module  15  and the feedback circuit  22  are coupled in such a way that, at output from the feedback terminal FB of the control module  15 , a current I FB  is present that depends upon the aforementioned error signal. The current I FB  causes a voltage drop on the fifth resistor R c . The aforementioned control voltage V c  is, precisely, the voltage present on the feedback terminal FB of the control module  15  and depends upon the error signal in such a way as to regulate the output voltage V out . To a first approximation, the control voltage V c  may be considered constant because the band of the control loop is much lower than the frequency of the input voltage V in (θ). 
         [0017]    The control module  15  further comprises a multiplier  24 , a comparator  26 , a flip-flop  28  of a set-reset type, a driver  30 , a starter circuit  32 , a first logic gate  34  of an OR type, and a circuit  36  referred to hereinafter as “zero-current detection circuit  36 ”. 
         [0018]    In detail, the multiplier  24  has a first input, connected to the feedback terminal FB of the control module  15  for receiving the control voltage V c , and a second input, connected to the first input terminal MULT for receiving the voltage present thereon, which is proportional to the input voltage V in (θ) through the division ratio R 2 /(R 1 +R 2 ) introduced by the resistive divider  16 , where R 1  and R 2  are the values of resistance of the first and second resistors R a , R b . The multiplier  24  generates a voltage Vcs REF (θ) on an own output, which is connected to a negative input terminal of the comparator  26 . The voltage Vcs REF  (θ) has the form of a rectified sinusoid, the amplitude of which depends upon the control voltage V c  and the effective voltage present on the supply line. 
         [0019]    The positive input terminal of the comparator  26  is connected to the third input terminal CS of the control module  15  for receiving the voltage (designated by Vcs(t,θ)) present on the fourth resistor R s . The voltage Vcs(t,θ) is directly proportional to the current present in the primary winding L p  when the transistor M is in conduction, i.e., during magnetization of the primary winding L p  itself. 
         [0020]    The output of the comparator  26  is connected to the reset input of the flip-flop  28 , the output of which (designated by Q) is connected to the input of the driver  30 , the output of which forms the output terminal GD of the control module  15 . The output of the flip-flop  28  is further connected to the set input of the flip-flop  28  itself, by interposition of the starter circuit  32 . In particular, the input of the starter circuit  32  is connected to the output Q of the flip-flop  28 , whereas the output of the starter circuit  32  is connected to a first input of the first logic gate  34 . The second input and the output of the first logic gate  34  are connected, respectively, to the output of the zero-current detection circuit  36  and to the set input of the flip-flop  28 . The input of the ZCD circuit  36  is connected to the second input terminal ZCD of the control module  15 . 
         [0021]    In use, assuming that the transistor M is on, there occurs a linear growth of the current I p (t,θ) in the primary winding L p  and hence of the voltage Vcs(t,θ). When the voltage Vcs(t,θ) becomes equal to the voltage Vcs REF (θ), the comparator  26  resets the output of the flip-flop  28 , and the transistor M is turned off. Consequently, the voltage supplied by the resistive divider  16 , which has the form of a rectified sinusoid, determines the peak value of the current in the primary winding L p , which is thus enveloped by a rectified sinusoid. 
         [0022]    When the transistor M turns off, the energy stored in the primary winding L p  is transferred by magnetic coupling to the secondary winding L s , and hence in the output capacitor C out  until the secondary winding L s  demagnetizes. Furthermore, as long as a current flows in the secondary winding L s , the voltage of the drain terminal of the transistor M is equal to V in (θ)+V R , where V R  is the so-called reflected voltage, equal to n·V out , where n is the ratio between the number of the turns of the primary winding L p  and the number of the turns of the secondary winding L s  of the transformer  4 . 
         [0023]    Following upon demagnetization of the secondary winding L s , the output diode D opens, and the drain terminal of the transistor M becomes floating and tends to assume a voltage equal to the input voltage V in (θ) through damped oscillations caused by a parasitic capacitance resonating with the primary winding L p . However, the fast drop in voltage that takes place on the drain terminal of the transistor M following upon demagnetization of the transformer  4  is coupled to the second input terminal ZCD of the control module  15  through the auxiliary winding L aux  and the third resistor R ZCD . Furthermore, the zero-current detection circuit  36  generates a pulse whenever it detects that a falling edge of the voltage present on its own input drops below a threshold. This pulse forces a corresponding change of the output of the flip-flop  28  and consequently leads to turning-on of the transistor M and start of a new switching cycle. 
         [0024]    The starter circuit  32  enables start of the first switching cycle after turning-on of the flyback converter  3 , i.e., when no signal is yet present on the second input terminal ZCD of the control module  15 , and further prevents the flyback converter  3  from remaining blocked if for any reason the signal on the second input terminal ZCD of the control module  15  is lost. 
         [0025]    Examples of the signals that are generated in use within the flyback converter  3  are illustrated in  FIG. 2 , which, in addition to the aforementioned quantities I p  (t,θ), I s  (t,θ), Vcs(t,θ), Vcs REF  (θ), shows:
       the voltage V DS  between the drain and source terminals of the transistor M;   the voltage V in,pk  sin θ, where V in,pk  is the peak value of the input voltage V in ;   the voltage V aux  present on the auxiliary winding L aux ;   the voltage V ZCD  present on the second input terminal ZCD of the control module  15 ;   the thresholds V ZCDarm  and V ZCDtrig  of the voltage V ZCD  at which the zero-current detection circuit  36  is armed and generates a pulse, respectively;   the state ARM of the zero-current detection circuit  36 ;   the signal sS (of a logic type) present on the set input of the flip-flop  28 , and hence the pulses TRIGGER generated by the zero-current detection circuit  36 ;   the signal sR (of a logic type) present on the reset input of the flip-flop  28 ;   the signal sGD (of a logic type) present on the output Q of the flip-flop  28 , which governs turning-on of the transistor M (it is assumed that the driver  30  does not introduce any delay); and   a so-called “freewheel” state FW, corresponding to the period in which there occurs demagnetization of the transformer  4 .       
 
         [0036]    In general, it should be noted that, in indicating the quantities, the fact of not rendering any dependence upon parameters (in the case in point, the phase θ or the time t) explicit does not imply that the quantity in question is necessarily constant. 
         [0037]    In addition,  FIG. 2  represents the following periods:
       the period T ON , in which the transistor M is on, i.e., in conduction, and hence the period in which the core of the transformer  4  is magnetized;   the period T FW , in which demagnetization of the core of the transformer  4  occurs; and   the period T R , i.e., the delay that elapses between complete demagnetization of the core of the transformer  4  and next turning-on of the transistor M, i.e., start of new magnetization of the core of the transformer  4 .       
 
         [0041]    The resulting plots of the currents I p (t,θ), I s (t,θ), as well as the corresponding envelopes of the corresponding peaks I pkp (θ), I pks (θ) and the average, cycle by cycle, I in (θ) of the current in the primary winding L p  are illustrated in  FIG. 3 . For completeness, designating by T the switching period, we have T=T FW +T R +T ON . 
         [0042]    For practical purposes, the flyback converter  3  is of the quasi-resonant type. In fact, turning-on of the transistor M is synchronized with the instant of complete demagnetization of the transformer  4  (i.e., with the instant when the current in the secondary winding L s  becomes zero), albeit with a delay such that it occurs at a so-called “valley” of the voltage V DS . Turning-off of the transistor M is, instead, determined by detecting the moment when the current in the primary winding L p  reaches a given value. Furthermore, the flyback converter  3  is of the current-mode control type, and in particular of the peak-current-mode control type. In addition, since the peak envelope of the current that flows in the fourth resistor R s , and hence in the primary winding L p , is sinusoidal, a power factor higher than 0.9 is obtained. 
         [0043]    In practice, as illustrated in  FIG. 4 , the flyback converter  3  implements an electrical layout formed by a conversion stage  40 , which is operatively coupled to the control module  15 . In particular, the conversion stage  40  receives at input the input voltage V in (θ) and is controlled by the control module  15  in such a way as to supply the output voltage V out . As illustrated in  FIG. 4 , control of the conversion stage  40  occurs thanks to the aforementioned signal sGD (more precisely, thanks to the voltage V GA  present on the gate terminal of the transistor M), as well as thanks to the voltage V ZCD . Further, even though not illustrated in  FIG. 2 , the conversion stage  40  is controlled also on the basis of the feedback present between the output of the conversion stage  40  and the control module  15 . In addition, in order to control the conversion stage  40 , the control module  15  receives at input, through the resistive divider  16 , a fraction of the input voltage V in (θ), designated by V MULT  in  FIG. 4 . 
         [0044]      FIG. 5  shows a further example of converter, and in particular shows a boost converter  50 , which is here described just as regards the differences with respect to the flyback converter  3 . In  FIG. 5 , components already illustrated in  FIG. 1  have the same reference numbers, except where otherwise specified. The clamping circuit  20  is absent. 
         [0045]    In detail, instead of the transformer  4 , a coupled inductor  54  is present, which includes the primary winding and the auxiliary winding, designated, respectively, by L 1  and L aux , but not the secondary winding. The primary winding and the auxiliary winding L 1  and L aux  share a same magnetic core. The first terminal of the primary winding L 1  is still connected to the first terminal of the filtering capacitor C in , but the second terminal is connected to the anode of the output diode D. The auxiliary winding L aux  is electrically connected as in the case of the flyback converter  3  and performs the same electrical function. The drain terminal of the transistor M is still connected to the second terminal of the primary winding L 1 . Hence, it is now connected to the anode of the output diode D. 
         [0046]    The feedback circuit, designated by  52 , comprises a sixth resistor R d  and a seventh resistor R e , which form a corresponding resistive divider, which is arranged between the cathode of the output diode D and ground and the central node of which is connected to the feedback terminal FB of the control module, here designated by  55 . 
         [0047]    The control module  55  comprises, instead of the fifth resistor R c , an amplifier  58 , referred to hereinafter as “error amplifier  58 ”. The non-inverting terminal of the error amplifier  58  is connected to a reference node, which is set at an internal reference voltage V ref   _   int , whereas the non-inverting terminal forms the feedback terminal FB of the control module  55 . The output of the error amplifier  58  is connected to the first input of the multiplier  24 , the second input of which is still connected to the resistive divider  16 . The output of the multiplier  24  is connected to the negative input terminal of the comparator  26 , the positive input terminal of which is connected to the third input terminal CS of the control module  55 . 
         [0048]    The boost converter  50  further comprises a loop-compensation circuit  60 , which extends between a respective first node and a respective second node and includes an eighth resistor R f  and a ninth resistor R g , as well as a further capacitor  62 , referred to hereinafter as “additional capacitor  62 ”. In particular, the eighth resistor R f  is arranged between the aforementioned first and second nodes of the loop-compensation circuit  60  and is arranged in parallel to the series circuit formed by the additional capacitor  62  and by the ninth resistor R g . Furthermore, the first node of the loop-compensation circuit  60  is connected to the feedback terminal FB of the control module  55 , whereas the second node of the loop-compensation circuit  60  is connected to the output of the error amplifier  58 . 
         [0049]    In practice, the error amplifier  58  compares a portion of the output voltage V out  with the internal reference voltage V ref   _   int  and generates the control voltage V c , which depends upon an error signal proportional to the deviation between the aforementioned portion of the output voltage V out  and the internal reference voltage V ref   _   int  for regulating the output voltage V out . As explained previously, to a first approximation, the control voltage V c  may be considered constant. The subsequent operation of the boost converter  50  is similar to that of the flyback converter  3 . Examples of the time plots of the signals sS, sR, sGD and of the current I(t,θ) in the primary winding L 1  are illustrated in  FIGS. 6 a  and 6 b   . Further,  FIG. 6 a    shows a signal sZCD indicating the period in which the current i L  through the primary winding L 1  is zero. 
         [0050]    In greater detail, the boost converter  50  operates in the so-called “transition mode” (TM) since the current in the primary winding L 1  vanishes for a short period of time. 
         [0051]    This being said, irrespective of the topology of the switching converter considered (flyback, boost, buck, etc.), there occurs generation of a sinusoidal reference, by a sort of line-sensing circuitry that includes a resistive divider and enables detection of a percentage of the rectified line voltage. This entails a dissipation on the resistive divider, which, according to the application and the corresponding sizing of the switching converter, may range between about ten milliwatts and some tens of milliwatts. This loss is hence not negligible and the desire to reduce it as much as possible is particularly felt. 
       BRIEF SUMMARY 
       [0052]    One embodiment of the present disclosure is a control module for a switching converter that will overcome at least in part the drawbacks of the known art. 
         [0053]    One embodiment of the present disclosure is a module for controlling a switching converter, which includes an inductor element and one switch element and is configured to generate an output electric quantity starting from an input electric quantity. The control module includes a switch control circuit configured to generate a command signal for controlling switching of the switch element; and an estimator stage configured to generate an estimation signal proportional to the input electric quantity, based on the command signal and a first input signal indicating a time interval in which the inductor element is demagnetized. The switch control circuit is configured to generate the command signal based on the estimation signal. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0054]    For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example and with reference to the attached drawings, wherein: 
           [0055]      FIGS. 1 and 5  show circuit diagrams of switching converters of a known type; 
           [0056]      FIGS. 2 and 3  show time plots of signals generated within the switching converter illustrated in  FIG. 1 ; 
           [0057]      FIG. 4  shows a block diagram regarding the switching converter illustrated in  FIG. 1 ; 
           [0058]      FIGS. 6 a  and 6 b    show time plots of signals generated within the switching converter illustrated in  FIG. 5 ; 
           [0059]      FIGS. 7 and 10  show circuit diagrams of switching converters including the present control module; 
           [0060]      FIG. 8  shows a circuit diagram of a portion of the switching converter illustrated in  FIG. 7 ; 
           [0061]      FIG. 9  shows time plots of signals generated within the switching converter illustrated in  FIG. 7 ; 
           [0062]      FIGS. 11 a -11 d    show principle circuit diagrams of converters equivalent to the converter illustrated in  FIG. 10 ; 
           [0063]      FIGS. 12 and 13  show principle circuit diagrams of switching converters that are equivalent to one another; 
           [0064]      FIG. 14  shows a circuit diagram of a further switching converter including the present control module; 
           [0065]      FIGS. 15 a  and 15 b    show time plots of signals generated within the switching converter illustrated in  FIG. 14 ; and 
           [0066]      FIG. 16  shows a block diagram of a lighting system. 
       
    
    
     DETAILED DESCRIPTION 
       [0067]    The present Applicant has noted how, given a switching converter, it is possible to generate a signal proportional to the input voltage V in (θ), without resorting to a resistive divider, but rather implementing an estimator circuit, which receives at input signals generated in use by the switching converter. This being said, in what follows the present control module is described with reference to a boost converter, even though it may be used also in the case of converters of a different type. In particular, the present control module is described with reference to the boost converter  60  illustrated in  FIG. 7 , which in turn is described with reference to the differences with respect to the boost converter  50  illustrated in  FIG. 5 . Components of the boost converter  60  already present in the boost converter  50  are designated by the same reference numbers, except where otherwise specified. 
         [0068]    In detail, the control module of the boost converter  60 , designated by  65 , includes an estimator circuit  67  and is without the first input terminal MOLT. Further, the boost converter  60  is without the resistive divider  16 . 
         [0069]    In greater detail, the estimator circuit  67  comprises a current generator  68  and a first switch  70 , a second switch  72 , and a third switch  74 , as well as a respective resistor  76  and a respective capacitor  78 , referred to hereinafter as “estimation resistor  76 ” and the “estimation capacitor  78 ”, respectively. 
         [0070]    In particular, the current generator  68  is arranged between a first internal node N 1  and a second internal node N 2  and is configured to inject a constant current I into the second internal node N 2 . 
         [0071]    The first switch  70  is connected between the second internal node N 2  and a third internal node N 3 . 
         [0072]    The estimation capacitor  78  is connected between the third internal node N 3  and ground. The estimation resistor  76  is connected to the third internal node N 3  and to the second switch  72 , which is further connected to ground. In other words, the second switch  72  and the estimation resistor  76  form a sort of series circuit arranged in parallel to the estimation capacitor  78 . In addition, the third internal node N 3  is connected to the second input of the multiplier  24 . 
         [0073]    The third switch  74  is connected between the second internal node N 2  and ground. 
         [0074]    The first, second, and third switches  70 ,  72 ,  74  are controlled by a first command signal, a second command signal, and a third command signal, respectively. Further, the third command signal is equal to the logic negation of the first command signal. Consequently, it is possible to designate the first, second, and third command signals by A, B and Ā, respectively. 
         [0075]    In detail, when A=‘1’, the current generator  68  is electrically connected to the third internal node N 3 . Instead, when A=‘0’, the current generator  68  is connected to ground. Furthermore, when B=‘1’, the estimation capacitor  78  is connected in parallel to the estimation resistor  76 . Instead, when B=‘0’, the estimation resistor  76  is floating. 
         [0076]    It is thus possible to designate by T A  the period in which the estimation capacitor  78  is being charged, i.e., when A=‘1’ and B=‘0’. Likewise, it is possible to designate by T B  the period in which the estimation capacitor  78  is discharging, i.e., when A=‘0’ and B=‘1’. Once again, it is possible to designate by T AB  the period in which the estimation capacitor  78  is floating, i.e., when A=‘0’ and B=‘0’. In addition, assuming a switching period T(θ)=T A  (θ)+T B  (θ)+T AB (θ)&lt;&lt;R*C&lt;&lt;1/f line , where f line  is the frequency of the supply line, and R and C are, respectively, the resistance of the estimation resistor  76  and the capacitance of the estimation capacitor  78 , it is possible to ignore the ripple on the estimation capacitor  78 , and further it may be assumed that the voltage on the estimation capacitor  78  follows the waveform of the line voltage. This being said, by applying the charge balance on the estimation capacitor  78 , we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       IT 
                       A 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           V 
                           e 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       R 
                     
                      
                     
                       
                         T 
                         B 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where R is the resistance of the estimation resistor  76 . Consequently, the voltage V e (θ) on the estimation capacitor  78  itself is 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       e 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     RI 
                      
                     
                       
                         
                           T 
                           A 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           B 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0077]    This being said, the calculation of the balance of the magnetic flux on the primary winding L 1  yields: 
         [0000]        V   in (θ) T   ON (θ)=[( V   out   +V   F )− V   in (θ)] T   FW (θ)  (3)
 
         [0000]    where T FW (θ) is the period in which demagnetization of the core of the primary winding L 1  occurs, whereas T ON (θ) is the period in which the transistor M is in conduction, and hence the period in which magnetization of the core of the primary winding L 1  takes place. 
         [0078]    From Eq. (3) we have: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         
                           i 
                            
                           n 
                         
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     
                       
                         V 
                         out 
                       
                       + 
                       
                         V 
                         F 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           T 
                           FW 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           
                             T 
                             ON 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         + 
                         
                           
                             T 
                             FW 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                     
                     = 
                     
                       
                         
                           T 
                           FW 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where V out +V F  is, to a first approximation, constant, and V F  is the voltage drop on the output diode D. 
         [0079]    Once again with reference to Eq. (2), by imposing T A =T FW  and T B =T−T R , we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       e 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     RI 
                      
                     
                       
                         
                           T 
                           FW 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    i.e., the voltage V c (θ) has the same plot, but for a scale factor, as the input voltage V in (θ). In fact, from Eqs. (4) and (5) we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       e 
                     
                      
                     
                       ( 
                       0 
                       ) 
                     
                   
                   = 
                   
                     
                       RI 
                        
                       
                         
                           
                             V 
                             
                               i 
                                
                               n 
                             
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         
                           ( 
                           
                             
                               V 
                               out 
                             
                             + 
                             
                               V 
                               F 
                             
                           
                           ) 
                         
                       
                     
                     = 
                     
                       
                         KV 
                         
                           i 
                            
                           n 
                         
                       
                        
                       
                         ( 
                         0 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    which demonstrates the direct proportionality present between the voltage V e (θ) on the estimation capacitor  78 , and hence at input to the multiplier  24 , and the input voltage V in (θ). The voltage V e (θ) and the voltage V in (θ) hence have a same phase, and consequently a same time plot. 
         [0080]    For the boost converter of  FIG. 7 , the control module  65  includes a logic circuit  79  that provides the control signals A, Ā, and B based on the signals sZCD and sGD such that A=sFW and B= sZCD , where sFW is a signal that is equal to ‘1’ when there occurs demagnetization of the primary winding L 1 , and is equal to ‘0’ during the magnetization of the primary winding L 1  or when the signal sZCd is equal to ‘1’, whereas the signal  sZCD  is equal to the logic negation of the signal sZCD, which is equal to ‘1’ when the primary winding L 1  is completely demagnetized, i.e., when the current I(t,θ) in the primary winding L 1  is zero, and is equal to ‘0’ otherwise. 
         [0081]    In greater detail, the signal sZCD may be generated, for example, by the zero-current detection circuit  36 . In this case, the zero-current detection circuit  36  is provided not only with the aforementioned output connected to the first logic gate  34 , but also with a further output, on which it supplies the signal sZCD. In addition, the zero-current detection circuit  36  continues to provide, on the output connected to the logic gate  34 , a signal such that on the set input of the flip-flop  28  the aforementioned signal sS is present. 
         [0082]    As regards the signal sFW, it is generated, as illustrated in  FIG. 8 , on the basis of the signal sZCD and of the signal sGD, which, as has been said, is equal to ‘1’ when the transistor M is in conduction and is equal to ‘0’ when the transistor M is inhibited. In particular, even though not illustrated in  FIG. 7 , the logic circuit  79  of the control module  65  comprises a second logic gate  80  of a negated OR type, which receives at input the signals sGD and sZCD and generates the signal sFW, and logic inverters configured to generate the signals  sZCD  and  sFW , starting, respectively, from the signals sZCD and sFW. The electrical connections that involve the second logic gate  80  are not shown, as neither, on the other hand, are the logic inverters connected to the second switch  72  and the third switch  74  and designed to generate the signals  sZCD  and  sFW . Examples of the signals sFW, sGD and sZCD are represented in  FIG. 9 . 
         [0083]    As illustrated in  FIG. 10 , and as mentioned previously, the estimator circuit  67  may be used also in the case of a flyback converter, here designated by  90 . In this case, the estimator circuit  67  is again included in the control module, designated by  95 . Further, we have A=sFW and B=sGD, for the reasons described in what follows. In  FIG. 10 , the connections between the estimator circuit  67  and the zero-current detection circuit  36  and the output Q of the flip-flop  28 , as well as the second logic gate  80  and inverter for producing Ā, are not represented. 
         [0084]    In detail, the balance of the magnetic flux on the primary winding, designated by L p , yields: 
         [0000]        V   in (θ) T   ON (θ)= n ( V   out   +V   F ) T   FW (θ)  (7)
 
         [0000]    whence we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       
                         i 
                          
                         n 
                       
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       n 
                        
                       
                         ( 
                         
                           
                             V 
                             out 
                           
                           + 
                           
                             V 
                             F 
                           
                         
                         ) 
                       
                     
                      
                     
                       
                         
                           T 
                           FW 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
           
         
       
     
         [0085]    Recalling Eq. (2), from Eq. (8) it emerges how, by imposing T A =T FW  and T B =T ON , and hence A=sFW and B=sGD, we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       e 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       RI 
                        
                       
                         
                           
                             V 
                             
                               i 
                                
                               n 
                             
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         
                           n 
                            
                           
                             ( 
                             
                               
                                 V 
                                 out 
                               
                               + 
                               
                                 V 
                                 F 
                               
                             
                             ) 
                           
                         
                       
                     
                     = 
                     
                       
                         K 
                         1 
                       
                        
                       
                         
                           V 
                           in 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
         [0086]    Furthermore, the estimator circuit  67  may be used also in the case of converters of topologies equivalent to the flyback topology, i.e., converters having the same conversion ratio V out /V in  as the one that characterizes flyback converters. In this case, the first, second, and third command signals A, B and Ā are the same as what has been described with reference to  FIG. 10 . 
         [0087]    Examples of topologies equivalent to the flyback topology are illustrated synthetically in  FIGS. 11 a -11 d   . In  FIGS. 11 a -11 d   , components that have already been illustrated previously are designated by the same reference numbers. Further,  FIGS. 11 a -11 d    are described briefly, with reference just to the differences with respect to what has been described with reference to  FIG. 10 . In addition, the primary winding is referred to as “first inductor L 1 ”. Again, the circuit diagrams illustrated in  FIGS. 11 a -11 d    are principle circuit diagrams, and hence they are not complete, but rather are limited to showing some components and some electrical connections of the corresponding converters in order to highlight the type of the converters themselves, which substantially depends upon the arrangement of the reactive elements and of the transistor M. 
         [0088]    In particular,  FIG. 11 a    shows a buck-boost converter  111   a , where the anode of the output diode D is connected to the second terminal of the first inductor L 1 , whereas the output capacitor C out  is connected to the first terminal of the first inductor L 1  and to the cathode of the output diode. Furthermore, designated in  FIG. 11 a    is by  100  is a gate-driving stage, which includes the control module  95 . For the reason explained previously, the gate-driving stage  100  is illustrated as being without inputs, even though in actual fact it possesses the aforementioned inputs ZCD and CS, as well as the feedback terminal FB, connected in a per se known manner. 
         [0089]      FIG. 11 b    shows a Cuk converter  111   b , which further comprises an additional capacitor C 1 , which is connected to the second terminal of the first inductor L 1  and to the anode of the output diode D, the cathode of which is connected to the source terminal of the transistor M. In addition, the second inductor L 2  is present, which is connected between the anode of the output diode D and a first terminal of the output capacitor C out , the second terminal of which is connected to the source terminal of the transistor M. 
         [0090]      FIG. 11 c    shows a SEPIC converter  111   c , in which the positions of the output diode D and of the second inductor L 2  are reversed as compared to the Cuk converter  111   b . Consequently, the anode of the output diode D and a first terminal of the second inductor L 2  are connected to the terminal of the additional capacitor C 1  not connected to the first inductor L 1 . The second terminal of the second inductor L 2  is connected to the source terminal of the transistor M. The output capacitor C out  is arranged between the cathode of the output diode D and the source terminal of the transistor M. 
         [0091]      FIG. 11 d    shows a Zeta converter  111   d , also known as “inverted SEPIC”, where the drain and source terminals of the transistor M are connected, respectively, to a first terminal of the input capacitor C in  and to a first terminal of the first inductor L 1 , the second terminal of which is connected to the second terminal of the input capacitor C in . The additional capacitor C 1  is arranged between the first terminal of the first inductor L 1  and the cathode of the output diode D, the anode of which is connected to the second terminal of the first inductor L 1 . A first terminal of the second inductor L 2  is connected to the cathode of the diode D. The output capacitor C out  is arranged between the second terminal of the second inductor L 2  and the anode of the output diode D. 
         [0092]    As illustrated in  FIG. 12 , the estimator circuit  67  may be used also in the case of a buck converter  120 . In particular,  FIG. 12  shows a principle diagram of the buck converter  120 , in a way similar to the representation of  FIGS. 11 a -11 d   , i.e., without including all the components and the corresponding connections. 
         [0093]    In detail, the drain and source terminals of the transistor M are connected, respectively, to a first terminal of the input capacitor C in  and to the cathode of the output diode D, the anode of which is connected to the second terminal of the input capacitor C in . A first terminal of the first inductor L 1  is connected to the cathode of the output diode D, whereas a second terminal of the first inductor L 1  is connected to a first terminal of the output capacitor C out , the second terminal of which is connected to the anode of the output diode. 
         [0094]    In this case, the estimator circuit  67  is still included in the gate-driving stage  100 . Further, we have A= sZCD  and B=sGD, for the reasons given below. 
         [0095]    In detail, the balance of the magnetic flux on the first inductor L 1  yields: 
         [0000]      [ V   in (θ)− V   out   ]T   ON (θ)=( V   out   +V   F ) T   FW (θ)  (10)
 
         [0000]    whence, noting that V F &lt;&lt;V out , we obtain, to a first approximation, 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         V 
                         
                           i 
                            
                           n 
                         
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                     
                       V 
                       OUT 
                     
                   
                   = 
                   
                     
                       
                         
                           
                             T 
                             ON 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         + 
                         
                           
                             T 
                             FW 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                     = 
                     
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                       
                         
                           T 
                           ON 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
         [0096]    Recalling Eq. (2), from Eq. (11) it is highlighted how, by imposing T A =T−T R  and T B =T ON , and hence A= sZCD  and B=sGD, we obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       V 
                       e 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       RI 
                        
                       
                         
                           
                             V 
                             in 
                           
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         
                           V 
                           out 
                         
                       
                     
                     = 
                     
                       
                         K 
                         2 
                       
                        
                       
                         
                           V 
                           in 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
         [0097]    The estimator circuit  67  may be used also in the case of converters of topologies equivalent to the buck topology. In this case, the first, second, and third command signals A, B and Ā are the same as what has been described with reference to  FIG. 12 . 
         [0098]    An example of a topology equivalent to the buck topology is illustrated synthetically in  FIG. 13 . 
         [0099]    In particular,  FIG. 13  shows a reverse-buck converter  130 , where the cathode of the output diode D and a first terminal of the output capacitor C out  are connected to a first input terminal C in . The anode of the output diode D and the second terminal of the output capacitor C out  are connected, respectively, to a first terminal and a second terminal of the first inductor L 1 . The drain and source terminals of the transistor M are connected, respectively, to the first terminal of the first inductor L 1  and to the second terminal of the input capacitor C in . 
         [0100]      FIG. 14  shows a further embodiment, described in what follows as regards the differences from the embodiment illustrated in  FIG. 7 . 
         [0101]    In detail, the boost converter, designated by  160  is without the multiplier  24 . Furthermore, the current generator, designated by  168 , of the estimator circuit, designated by  167 , is of a variable type. 
         [0102]    In greater detail, the current generator  168  receives at input the control voltage V c  generated by the error amplifier  58 . Furthermore, in a per se known manner, the current generated by the current generator  168  is directly proportional to the control voltage V c . In other words, designating by I CH  the current generated by the current generator  168 , we have I CH =G M ·V c , with G M  constant and equal to the transconductance of the current generator  168 . 
         [0103]    The third internal node N 3  of the estimator circuit  167  is directly connected to the negative input terminal of the comparator  26 . 
         [0104]    This being said, and recalling that Eqs. (3) and (4) still apply, the charge balance on the estimation capacitor  78  yields: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       
                         I 
                         CH 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                      
                     
                       
                         T 
                         FW 
                       
                        
                       
                         ( 
                         θ 
                         ) 
                       
                     
                   
                   = 
                   
                     
                       
                         
                           Vcs 
                           REF 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       R 
                     
                      
                     
                       [ 
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                       ] 
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where V e  is set equal to Vcs REF . 
         [0105]    It follows that: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Vcs 
                       REF 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       RG 
                       M 
                     
                      
                     
                       V 
                       C 
                     
                      
                     
                       
                         
                           T 
                           FW 
                         
                          
                         
                           ( 
                           θ 
                           ) 
                         
                       
                       
                         
                           T 
                            
                           
                             ( 
                             θ 
                             ) 
                           
                         
                         - 
                         
                           T 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
         [0106]    Applying Eq. (4) and expressing V in (θ) as V in,pk ·sin (θ), where V in,pk  is the input peak voltage, we finally obtain: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       Vcs 
                       REF 
                     
                      
                     
                       ( 
                       θ 
                       ) 
                     
                   
                   = 
                   
                     
                       V 
                       c 
                     
                      
                     
                       
                         
                           G 
                           M 
                         
                          
                         R 
                       
                       
                         
                           V 
                           out 
                         
                         + 
                         
                           V 
                           F 
                         
                       
                     
                      
                     
                       V 
                       
                         
                           i 
                            
                           n 
                         
                         , 
                         pk 
                       
                     
                      
                     sin 
                      
                     
                         
                     
                      
                     
                       θ 
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
         [0107]    Considering the boost converter  60  of a known type illustrated in  FIG. 5 , and designating by Vcs REF ′ the voltage present on the output of the multiplier  24 , we have 
         [0000]        Vcs   REF ′(θ)= K   M   V   c MULT(θ)= K   M   K   P   V   c   V   in,pk  sin θ  (16)
 
         [0000]    where K P =R 2 /(R 1 +R 2 ), and K M  is the gain of the multiplier  24 . Consequently, considering Eqs. (15) and (16), it may be noted how Vcs REF =Vcs REF ′, if K M ·K p =(G M ·R)/(V out +V F ). Examples of signals generated within the boost converter  160  are illustrated in  FIGS. 15 a    and  15   b.    
         [0108]    In practice, by adopting a current generator variable in a way directly proportional to the control voltage V c , the voltage V e (θ) that is obtained on the estimation capacitor  78  may be equated to the voltage Vcs REF  generated traditionally by the multiplier  24 , which commonly generates a reference signal that is directly proportional to the control voltage V c  and has the same profile as the voltage present on the input capacitor C in . It is hence possible to remove the multiplier  24 , thus simplifying the control module and reducing the area thereof. Furthermore, even though  FIG. 14  refers purely by way of example to a boost converter, the current generator  168  of a variable type may be used in converters of any type, such as, for example, flyback converters or buck converters and/or equivalent converters. In this way, it is possible to remove the multiplier also in these converters. 
         [0109]    Irrespective of the presence or otherwise of the multiplier, any one of the switching converters previously described (hence, including the estimator circuit) may be used for supplying, for example, one or more solid-state lighting devices. For instance,  FIG. 16  shows a lighting system  200 , which, without any loss of generality, is connected to an a.c. voltage generator  202 . The lighting system  200  comprises the bridge rectifier  2  and a switching converter  204  according to any one of the embodiments previously described. Furthermore, the lighting system  200  comprises a load  206  formed, for example, by a LED or an array of LEDs. 
         [0110]    From what has been described and illustrated previously, the advantages that the present solution affords emerge clearly. 
         [0111]    In particular, the present control module enables generation of the voltage Vcs REF (θ) in such a way that it has the form of a rectified sinusoid and an amplitude that depends upon the control voltage V c , without any need to couple a resistive divider to the input capacitor C in , and hence eliminating the losses associated to the aforesaid resistive divider. 
         [0112]    Furthermore, the present control module may be applied also in the case where at input to the converter a d.c. voltage is present, instead of an a.c. voltage, as also in the case where the converter is configured to regulate an output current instead of an output voltage. In the latter case, the feedback circuit generates a signal proportional to the output current, instead of to the output voltage, in a per se known manner. 
         [0113]    In addition, in the case where the current generator of the estimator circuit is variable and directly proportional to the control voltage V c , the control module is without the traditional multiplier. 
         [0114]    In conclusion, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure. 
         [0115]    For instance, the third switch  74  may be connected not only to the second internal node N 2 , but also to the first internal node N 1 , instead of to ground. Furthermore, the positions within the series circuit of the estimation resistor  76  and of the second switch  72  may be reversed. 
         [0116]    Furthermore, the present control module may be included also in a switching converter controlled in the so-called “voltage mode”, or else also in a switching converter controlled in average-current mode. 
         [0117]    Finally, the present estimator circuit may be used also outside a control module of a switching converter, i.e., independently of subsequent use of the voltage V e  within a control loop of a switching converter. 
         [0118]    The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.