Abstract:
A test apparatus for testing an information processing apparatus includes a control unit connected to the control signal line through the connector unit to receive command information from the processing unit to execute the program, and a switching unit connected to the control unit to connect the second communication signal line and the fourth communication signal line under the control of the control unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims priority to prior Japanese Patent Application No. 2008-76390 filed on Mar. 24, 2008 in the Japan Patent Office, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    An embodiment of the invention discussed herein relates to a test apparatus, an information processing system and a test method. 
       BACKGROUND 
       [0003]    In the conventional method of fabricating an SVP (Service Processor) board in a factory, a yield of fabricated SVP boards is checked. The yield is checked by confirming an operation of, for example, a CPU (Central Processing Unit), a HUB, and an I2C (Inter-Integrated Circuit, a standard on an inter-IC bidirectional serial bus developed by Philips) controller mounted on the SVP board. 
         [0004]    Normally, the yield of SVP boards is checked by conducting a test utilizing the I2C function. With regard to an SVP board having no element having the I2C function, however, the test cannot be conducted utilizing the I2C function. 
         [0005]    If the test may not be conducted utilizing the I2C function, the operator conducts the test by a simple method in which a voltage is applied to the SVP board by contact with a terminal and a resulting output voltage confirmed thereby to check the yield of the SVP board. 
         [0006]    A technique for conducting an online loopback test has been disclosed. Also, a technique has been disclosed to conduct a connection test between end systems without installing a test program in the end systems. 
         [0007]    [Patent Document 1] Japanese Laid-open Patent Publication No. 2002-16664 
         [0008]    [Patent Document 2] Japanese Laid-open Patent Publication No. 5-204807 
       SUMMARY 
       [0009]    According to an aspect of the invention, a test apparatus for testing an information processing apparatus includes a control unit connected to the control signal line through the connector unit to receive the command information from the processing unit to execute the program, and a switching unit connected to the control unit to connect the second communication signal line and the fourth communication signal line under the control of the control unit. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]      FIG. 1  is a diagram depicting an example of the configuration of a backplane  10 ; 
           [0011]      FIG. 2  is a diagram for explaining the I2C sequence; 
           [0012]      FIG. 3  is a function block diagram depicting an SVP configuration according to an embodiment of the invention; 
           [0013]      FIG. 4  is a first flowchart depicting the steps of the process executed by the test jig and the SVP board according to the embodiment; 
           [0014]      FIG. 5  is a second flowchart depicting the continuing steps of the process following the first flowchart depicted in the  FIG. 4 , and the steps of the process is executed by the test jig and the SVP board according to the embodiment; and 
           [0015]      FIG. 6  is a diagram depicting the hardware configuration corresponding to the SVP board. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0016]    The test apparatus, the information processing system and the test method according to a preferred embodiment of the invention will be explained below with reference to the accompanying drawings. 
       First Embodiment  
       [0017]    First, the configuration of the backplane of the server constituting an information processing apparatus carrying the SVP board according to this embodiment will be explained.  FIG. 1  is a diagram depicting an example of the configuration of the backplane  10 . As depicted in  FIG. 1 , the backplane  10 , having a LAN path unit  11  and an I2C path unit  12 , is connected to connectors  70  to  78 . 
         [0018]    The connector  70  is connected to a KVM (Keyboard, Video, and Mouse) interface  20 . Also, the connectors  71  and  72  are connected to GbE switches  30  and  31 , respectively. The connectors  73  and  74  are connected to I/O units  40  and  41 , respectively. Further, the connectors  75  and  76  are connected to system boards  50  and  51 , respectively. The connector  77  is connected to a memory &amp; I/O interconnect system (XAI &amp; XDI board)  60 , and the connector  78  to an SVP board  100 . 
         [0019]    In the example depicted in  FIG. 1 , the LAN path unit  11  controls the boards including the GbE switches  30 ,  31 , the I/O units  40 ,  41 , and the SVP board  100  by a LAN (local area network) and also constitute a communication path. The I2C path unit  12 , on the other hand, controls the boards (the KVM  20 , the GbE switches  30 ,  31 , the I/O units  40 ,  41 , the system boards  50 ,  51 , the memory &amp; I/O interconnect system  60  and the SVP board  100  depicted in  FIG. 1 ) through the I2C buses and also constitutes a communication path. 
         [0020]    The I2C buses are each an inter-IC bidirectional serial bus developed by Philips. The I2C bus signal line includes a serial clock line (SCL) and a serial data line (SDA). Using these two lines and the I2C buses, the communication is conducted between the control side (master) and the IC side (slave). The data transfer through the I2C buses is started by a start condition and ended by a stop condition. 
         [0021]      FIG. 2  is a diagram for explaining the data transfer sequence along each I2C bus. Before starting the data transfer, as depicted in  FIG. 2 , the master issues the start condition and acquires the right to use the I2C bus, after which the data is transferred (step S 10 ). 
         [0022]    Then, the device address is transmitted, the read/write operation is controlled, and the ACK (acknowledgment) from the slave is received by the master (step S 11 ). Next, the master receives the memory address in the device and the ACK from the slave (step S 12 ). 
         [0023]    The data transfer is started by the master, and the ACK is received from the slave (step S 13 ). Upon complete data transfer, the master issues the stop condition to release the bus (step S 14 ). 
         [0024]    Returning to  FIG. 1 , the KVM  20  is a device functioning as an interface with various input devices (for example, the keyboard and the mouse not depicted). The GbE switches  30  and  31  are connected to the communication path meeting the Gigabit Ethernet (registered trademark) standard to switch the paths thus connected. 
         [0025]    The I/O units  40  and  41  are devices connected to the LAN card for communication through the LAN. Only the I/O units  40  and  41  are depicted for the convenience of explanation. Nevertheless, the backplane  10  may be equipped with other I/O units. 
         [0026]    The system boards  50  and  51  are devices carrying a CPU, a memory and the like to execute a specific process assigned to them. The system boards  50  and  51  execute the input/output process using the I/O unit  40  or  41 . For example, the system board  50  executes the input/output process by conducting the communication using the I/O unit  40  while the system board  51  executes the input/output process by conducting the communication using the I/O unit  41 . Although only the system boards  50  and  51  are depicted by way of explanation, the backplane  10  may also include other system boards. 
         [0027]    The memory &amp; I/O interconnect system  60  is a device to store information on the relation between the system board and the I/O unit. The memory &amp; I/O interconnect system  60 , for example, stores information indicating that the system board  50  utilizes the I/O unit  40  and the system board  51  utilizes the I/O unit  41 . The SVP board  100  will be explained below. 
         [0028]    The SVP board  100  is a device for executing the various control operations in the server by reading a program. The SVP board  100 , for example, conducts a diagnostic test on the server autonomously.  FIG. 3  is a function block diagram depicting the configuration of the SVP board according to this embodiment. As depicted in  FIG. 3 , the SVP board  100  includes a memory  110 , a CPU  120 , I2C control units  130   a,    130   b,  and HUBs  140   a  and  140   b.    
         [0029]    Also, the SVP board  100  is connected to a test jig  200  and terminal units  300   a  and  300   b  by a connector  78 . As depicted in  FIG. 3 , the test jig  200  includes relays  210   a,    210   b,  and GPIOs (general-purpose I/Os)  220   a  and  220   b.  The other parts of the configuration are similar to those of a typical SVP board and therefore not explained. 
         [0030]    The memory  110  is a storage unit to store the data and the programs needed for the various processes executed by the CPU  120 . The memory  110  stores, for example, the test program for conducting the self-diagnostic test. The procedure of the test program will be explained later with reference to a flowchart. 
         [0031]    The CPU  120  is an arithmetic operation unit for executing the various processes by reading the programs stored in the memory  110  as a storage unit. Especially, the CPU  120  conducts the self-diagnostic test of the SVP board  100  by reading the test program from the memory  110 . 
         [0032]    The I2C control units  130   a  and  130   b  are each connected to the CPU  120  through a control line. The I2C control units  130   a  and  130   b  are devices to open/close the relays  210   a  and  210   b  by writing a value of “0” or “1” in the channel held by the GPIOs  220   a  and  220   b  upon receipt of an open/close instruction for the relays  210   a  and  210   b  from the CPU  120 . 
         [0033]    The I2C control unit  130   a,  upon reception of an instruction from the CPU  120  to close the relay  210   a,  closes the relay  210   a  by writing a value of “1” in channel ch 1  of the GPIO  220   a.  By closing the relay  210   a,  the LAN  152  and the LAN  154  are connected to each other. 
         [0034]    Upon reception of an instruction from the CPU  120  to open the relay  210   a,  on the other hand, the I2C control unit  130   a  opens the relay  210   a  by writing a value of “0” in channel ch 1  of the GPIO  220   a.  By opening the relay  210   a,  the LAN  152  and the LAN  154  are disconnected from each other. 
         [0035]    The I2C control unit  130   b,  upon reception of an instruction from the CPU  120  to close the relay  210   b,  closes the relay  210   b  by writing a value of “1” in channel ch 0  of the GPIO  220   b.  By closing the relay  210   b,  the LAN  153  and the LAN  155  are connected. 
         [0036]    Upon reception of an instruction from the CPU  120  to open the relay  210   b,  on the other hand, the I2C control unit  130   b  opens the relay  210   b  by writing a value of “0” in channel ch 0  of the GPIO  220   a.  By opening the relay  210   b,  the LAN  153  and the LAN  155  are disconnected from each other. 
         [0037]    The HUBs  140   a  and  140   b  are devices for connecting the LANs. The HUB  140   a  is connected to the LANs  151  to  153 . The HUB  140   a  is also connected to the terminal unit  300   a  through the LAN  151 . Further, the HUB  140   a  is connected to the relays  210   a  and  210   b  through the LANs  152  and  153 . 
         [0038]    The HUB  140   b  is connected to the LANs  154  to  156 . The HUB  140   b  is also connected to the terminal unit  300   b  through the LAN  156 . Further, the HUB  140   b  is connected to the relays  210   a  and  210   b  through the LANs  154  and  155 . 
         [0039]    The GPIO  220   a  is connected to the I2C control unit  130   a  through the connector  78  via a control line. Also, the GPIO  220   a  closes the relay  210   a  when a value of “1” is written in channel ch 1  by the I2C control unit  130   a.  On the other hand, the GPIO  220   a  opens the relay  210   a  when a value of “0” is written in channel ch 1 . 
         [0040]    The GPIO  220   b,  on the other hand, is connected to the I2C control unit  130   b  through the connector  78  and a control line. Also, the GPIO  220   b  closes the relay  210   b  when a value of “1” is written in channel ch 2  by the I2C control unit  130   b.  The GPIO  220   b  opens the relay  210   b  when “0” is written in channel ch 2 . 
         [0041]    The relay  210   a  is connected to the GPIO  220   a  through the control line, and in response as an acknowledgement to an instruction from the GPIO  220   a,  connects or disconnects the LANs  152  and  154 . The relay  210   b,  on the other hand, is connected to the GPIO  220   b  through the control line, and in response as an acknowledgement to an instruction from the GPIO  220   b,  connects or disconnects the LANs  153  and  155 . 
         [0042]    Next, the process of the CPU  120  to execute the test program will be explained. A case to test a control system # 1 , a LAN system # 1 , a control system # 2 , and a LAN system # 2  shall be considered as an example. The control system # 1  includes the I2C control unit  130   a,  the GPIO  220   a,  the relay  210   a,  and a control line. The LAN system # 1  includes the LANs  152  and  154 . Also, the control system # 2  includes the I2C control unit  130   b,  the GPIO  220   b,  the relay  210   b,  and a control line. Further, the LAN system # 2  includes the LANs  153  and  155 . 
         [0043]    (Test on Control System # 1  and LAN System # 1 ) 
         [0044]    The CPU  120  controls the I2C control unit  130   a  to write “1” in channel ch 1  of the GPIO  220   a  thereby to close the relay  210   a  and connect the LANs  152  and  154 . 
         [0045]    If the relay  210   a  fails to be closed in the process, the CPU  120  judges that a fault has occurred in the control system # 1 . Then, the CPU  120  stores in the memory  110  the information indicating that a fault has occurred in the control system # 1 , while at the same time adding a value of “1” to the number of errors. The initial value of the number of errors may be 0. 
         [0046]    If the relay  210   a  is closed, on the other hand, the CPU  120  displays, on a display (not depicted in  FIG. 3 ) or the like, information indicating that the relay  210   a  is closed, and switches to a standby state waiting for the input of the completion confirmation by the operator. The operator accessing the display operates the terminal unit  300   a  and transmits to the terminal unit  300   b  a ping signal indicating that the communication of the network in the LAN system # 1  is confirmed. 
         [0047]    Upon completion of the transmission of the ping signal from the terminal unit  300   a  to the terminal unit  300   b,  the operator inputs the information indicating that the confirmation is complete, through an input unit (not depicted), and notifies the CPU  120 . 
         [0048]    The CPU  120 , having received the notification from the operator that the confirmation is completed, controls the I2C control unit  130   a  to write a value of “0” in channel ch 1  of the GPIO  220   a,  and by opening the relay  210   a,  disconnects the LANs  152  and  154 . 
         [0049]    The CPU  120 , on the other hand, upon failure to receive the information indicating that the confirmation is complete from the operator for longer than a specific time, stores in the memory  110  the information indicating that a fault has occurred in the LAN system # 1 , while at the same time adding 1 to the number of errors. Then, the CPU  120  controls the I2C control unit  130   a  to write a value of “0” in channel ch 1  of the GPIO  220   a,  and by opening the relay  210   a,  disconnects the LANs  152  and  154 . 
         [0050]    (Test of Control System # 2  and LAN System # 2 ) 
         [0051]    The CPU  120  controls the I2C control unit  130   b  to write “1” in channel ch 0  of the GPIO  220   b.  By thus closing the relay  210   b,  the LANs  153  and  155  are connected to each other. 
         [0052]    If the relay  210   b  fails to be closed in the process, the CPU  120  judges that the control system # 2  has developed a fault. The CPU  120  stores in the memory  110  the information indicating that the control system # 2  has developed a fault, while at the same time adding 1 to the number of errors. 
         [0053]    If the relay  210   b  is closed, on the other hand, the CPU  120  displays on a display (not depicted) the information indicating that the relay  210   b  is closed, and switches to the standby mode to wait for the input of a completion confirmation by the operator. The operator accessing the display operates the terminal unit  300   a,  and transmits to the terminal unit  300   b  a ping signal indicating that the network communication in the LAN system # 2  is confirmed. 
         [0054]    When the ping signal transmission is completed from the terminal unit  300   a  to the terminal unit  300   b,  the operator inputs, through an input unit (not depicted), the information indicating that the confirmation is complete and notifies the CPU  120 . 
         [0055]    The CPU  120 , upon reception of the information indicating that the confirmation is complete from the operator, controls the I2C control unit  130   b  to write “0” in channel ch 0  of the GPIO  220   b,  and by thus opening the relay  210   b,  disconnects the LANs  153  and  155 . 
         [0056]    If the CPU  120  fails to receive the information on the completion confirmation from the operator for longer than a specific time, on the other hand, the information indicating that the LAN system # 2  has developed a fault is stored in the memory  110 , while at the same time 1 is added to the number of errors. Then, the CPU  120  controls the I2C control unit  130   b  to write “0” in channel ch 0  of the GPIO  220   b,  and by thus opening the relay  210   b,  disconnects the LANs  153  and  155 . 
         [0057]    Upon completion of the test on the control system # 1  and the LAN system # 1  and the test on the control system # 2  and the LAN system # 2 , if any one of the control systems # 1  and  2  and/or the LAN systems # 1  and  2  has developed a fault, the information on the system which has developed the fault, which is stored in the memory  110 , is displayed on a display or the likeIf any one of the control systems # 1  and  2  and/or the LAN systems # 1  and  2  has developed a fault (the number of errors is 1 or more), the operator can confirm the point of the error. 
         [0058]    If neither the control systems # 1  and  2  nor the LAN systems # 1  and  2  has developed a fault (the number of errors is 0), on the other hand, the CPU  120  erases the test program stored in the memory  110  by writing in the memory  110  a program for a product registered in advance. In other words, the CPU  120  writes the product program or the like over the test program. 
         [0059]    Next, the steps of the process executed by the SVP board  100  and the test jig  200  according to this embodiment will be explained.  FIGS. 4 and 5  are flowcharts depicting the steps of the process executed by the SVP board  100  and the test jig  200  according to this embodiment. 
         [0060]    As depicted in  FIGS. 4 and 5 , by switching on power of the SVP board  100  (test jig  200 ) (step S 101 ), the test mode is started (step S 102 ). The CPU  120  controls the I2C control unit  130   a  to set “1” in channel ch 1  of the GPIO  220   a  to judge whether the relay  210   a  is connected or not (step S 103 ). 
         [0061]    If the relay  210   a  is not connected (NO in step S 104 ), the CPU  120  stores in the memory  110  the information indicating that the control system # 1  has developed a fault (step S 105 ), while at the same time adding 1 to the number of errors (step S 106 ). The process then proceeds to step S 107 . 
         [0062]    If the relay  210   a  is connected (YES in step S 104 ), on the other hand, the CPU  120  switches to the standby mode to wait for the input of the completion confirmation by the operator (step S 107 ) while at the same time judging whether the completion confirmation has been received from the operator or not (step S 108 ). 
         [0063]    If the completion of confirmation is not received from the operator (NO in step S 109 ), the CPU  120  stores in the memory  110  the information indicating that the LAN system # 1  has developed a fault (step S 110 ), while at the same time adding 1 to the number of errors (step S 111 ). Then the process proceeds to step S 112 . 
         [0064]    If the completion of confirmation is received from the operator (YES in step S 109 ), on the other hand, the CPU  120  controls the I2C control unit  130   a  to set “0” in channel ch 1  of the GPIO  220   a  and disconnects the relay  210   a  (step S 112 ). 
         [0065]    Then, the CPU  120  controls the I2C control unit  130   b  to set “1” in channel ch 1  of the GPIO  220   b  and judges whether the relay  210   b  is connected or not (step S 113 ). 
         [0066]    If the relay  210   b  is not connected (NO in step S 114 ), the CPU  120  stores in the memory  110  the information indicating that the control system # 2  has developed a fault (step S 115 ), while at the same time adding 1 to the number of errors (step S 116 ). The process then proceeds to step S 117 . 
         [0067]    If the relay  210   b  is connected (YES in step S 114 ), on the other hand, the CPU  120  switches to the standby mode to wait for input of the confirmation completion by the operator (step S 117 ) and judges whether the confirmation of completion from the operator has been received or not (step S 118 ). 
         [0068]    If no confirmation of completion is received from the operator (NO in step S 119 ), the CPU  120  stores in the memory  110  the information indicating that the LAN system # 2  has developed a fault (step S 120 ), while at the same time adding 1 to the number of errors (step S 121 ). The process then proceeds to step S 122 . 
         [0069]    The CPU  120 , upon reception of confirmation of completion from the operator (YES in step S 119 ), on the other hand, controls the I2C control unit  130   b  to set “0” in channel ch 0  of the GPIO  220   b  and disconnects the relay  210   b  (step S 122 ). 
         [0070]    Then, the CPU  120  judges whether the number of errors is 0 or not (step S 123 ), and if the number of errors is not 0 (NO in step S 124 ), outputs the fault information stored in the memory  110  (step S 125  If the number of errors is 0, on the other hand, the CPU  120  writes the product program in the memory  110  (step S 126 ). 
         [0071]    In this way, the CPU  120  reads the test program stored in the memory  110 , and autonomously conducts the self-diagnostic test by opening/closing the relays  210   a  and  210   b,  thereby reducing the burden on the operator. 
         [0072]    Next, an example of the hardware configuration of the SVP board  100  depicted in  FIG. 3  will be explained.  FIG. 6  is a diagram depicting the hardware configuration corresponding to the SVP board  100 . As depicted in  FIG. 6 , the SVP board  400  includes an FMEM (flash memory)  410 , a CPU  420 , a CPLD (complex programmable logic device)  425 , a switching HUB  430 , a Fast Ethernet (registered trademark)  440 , an EEPROM (Electrically Erasable Programmable Read-Only Memory)  440   a,  an I2C system  450 , and a LAN system  460 . The other parts of the configuration are similar to those of a typical SVP board and thus shall not be explained. 
         [0073]    The FMEM  410  is a storage unit corresponding to the memory  110  depicted in  FIG. 3 , and the CPU  420  is an arithmetic operation unit corresponding to the CPU  120  depicted in  FIG. 3 . The CPLD  425  outputs various control signals to the LAN system  460 . 
         [0074]    The switching HUB  430  is a hub for connecting the CPU  420  and the LAN system  460 . Also, the Fast Ethernet (registered trademark)  440  selects the main one of various Ethernets (registered trademark). The EEPROM  440   a  stores various information used by the Fast Ethernet (registered trademark)  440 . 
         [0075]    The I2C system  450  corresponds to the control systems # 1  and # 2  and includes a connector  451 , I2C/SMBus controllers  452   a  to  452   f,  multiplexers  454   a  to  454   d,  and bus switches  455   a  to  455   f.  Also, the I2C system  450  is connected with the CPU  420  through a control line. 
         [0076]    The connector  451  corresponds to the connector  78  depicted in  FIGS. 1 and 3 . Also, the I2C/SMBus controllers  452   a  to  452   f  correspond to the I2C control units  130   a  and  130   b  depicted in  FIG. 3 . 
         [0077]    The multiplexers  454   a  to  454   d  connect the I2C/SMBus controllers  452   a  to  452   f  and the bus switches  455   c  to  455   f.  Also, the bus switches  455   a  to  455   f  switch the connected bus. 
         [0078]    The LAN system  460  corresponding to the LAN systems # 1  and # 2  depicted in  FIG. 3  includes a connector  461 , switching HUBs  462   a  to  462   e,  a Fast Ethernet (registered trademark)  463 , and an EEPROM  463   a.  The connector  461 , the switching HUBs  462   a  to  462   e,  the Fast Ethernet (registered trademark)  463 , and the EEPROM  463   a  are each connected to the CPU  420  through a control line. 
         [0079]    The connector  461  corresponds to the connector  78  depicted in  FIGS. 1 and 3 . Also, the switching HUBs  462   a  to  462   e  correspond to the HUBs  140   a  and  140   b  depicted in  FIG. 3 . The Fast Ethernet (registered trademark)  463  selects the main one of the various Ethernets (registered trademark). The EEPROM  463   a  stores the various information used by the Fast Ethernet (registered trademark)  463 . 
         [0080]    As described above, in the SVP board  100  ( 400 ) according to this embodiment, the GPIOs  220   a  and  220   b  are connected to the CPU  120  through the I2C control units  130   a  and  130   b  by way of the connector  78  and the control line. The CPU  120  controls the GPIOs  220   a  and  220   b  to open/close the relays  210   a  and  210   b  based on the test program stored in the memory  110 . According to this embodiment, therefore, the diagnostic test time of the SVP board  100  is simplified and automated, thereby reducing the burden on the operator. 
         [0081]    Of all the processes described above as automatic ones in this embodiment, the whole or a part of the processes can be alternatively executed manually, or conversely, the whole or a part of the manual processes described above can alternatively be executed automatically by a well-known method. Further, the processing steps, the control procedure, the specific names and the information including the various data and parameters described herein above and the accompanying drawings can be arbitrarily modified unless otherwise specified. 
         [0082]    Each component element of the SVP boards  100  and  400  depicted in  FIGS. 3 and 6  is a conceptual function and do not need to be configured physically as depicted. The specific form of distribution or integration of each device is not limited to those depicted in the drawings, but the whole or a part thereof can be functionally or physically distributed or integrated in arbitrary units in accordance with the various loads and operating conditions.