Abstract:
A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.

Description:
FIELD 
     Embodiments of the present invention may relate to the field of integrated circuit fuses, and more specifically to a tamper resistant fuse design. 
     BACKGROUND 
     An integrated circuit device, for example a microprocessor, may contain sensitive information, such as encryption keys or manufacturer codes, for example, stored in programmed fuses. A concern with conventional fuse arrays, however, is that voltage contrasts between blown and un-blown fuses could be detectable by hackers or counterfeiters with malevolent motives. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention may become apparent from the following detailed description of arrangements, example embodiments, and the claims when read in connection with the accompanying drawings. While the foregoing and following written and illustrated disclosure focuses on disclosing arrangements and example embodiments of the invention, it should be clearly understood that the same is by way of illustration and example only and embodiments of the invention are not limited thereto. 
       The following represents brief descriptions of the drawings in which like reference numerals represent like elements and wherein: 
         FIG. 1  is a block diagram of an example electronic appliance suitable for implementing a tamper resistant fuse design, in accordance with one example embodiment of the invention; 
         FIG. 2  is a block diagram of an example microprocessor suitable for implementing a tamper resistant fuse design, in accordance with one example embodiment of the invention; 
         FIG. 3  is a block diagram of an example tamper resistant fuse design, in accordance with one example embodiment of the invention; and 
         FIG. 4  is a block diagram of an example tamper resistant fuse design, in accordance with one example embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
       FIG. 1  is a block diagram of an example electronic appliance suitable for implementing a tamper resistant fuse design, in accordance with one example embodiment of the invention. Electronic appliance  100  is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, cell phones, wireless communication subscriber units, personal digital assistants, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance  100  may include one or more of microprocessor  102 , memory controller  104 , system memory  106 , input/output controller  108 , network controller  110 , and input/output device(s)  112  coupled as shown in  FIG. 1 . 
     Microprocessor  102  may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, microprocessor  102  is an Intel® compatible processor. Microprocessor  102  may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system. Microprocessor  102  may include elements as described in greater detail in regards to  FIG. 2 . 
     Memory controller  104  may represent any type of chipset or control logic that interfaces system memory  106  with the other components of electronic appliance  100 . In one embodiment, a link which communicatively couples microprocessor  102  and memory controller  104 , may be a high speed/frequency serial link such as Intel® QuickPath Interconnect. In another embodiment, memory controller  104  may be incorporated along with microprocessor  102  into an integrated package. 
     System memory  106  may represent any type of memory device(s) used to store data and instructions that may have been or will be used by microprocessor  102 . Typically, though the invention is not limited in this respect, system memory  106  will consist of dynamic random access memory (DRAM). In one embodiment, system memory  106  may consist of Rambus DRAM (RDRAM). In another embodiment, system memory  106  may consist of double data rate synchronous DRAM (DDRSDRAM). 
     Input/output (I/O) controller  108  may represent any type of chipset or control logic that interfaces I/O device(s)  112  with the other components of electronic appliance  100 . In one embodiment, I/O controller  108  may be referred to as a south bridge. In another embodiment, I/O controller  108  may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003 and/or other revisions. 
     Network controller  110  may represent any type of device that allows electronic appliance  100  to communicate with other electronic appliances or devices. In one embodiment, network controller  110  may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller  110  may be an Ethernet network interface card. 
     Input/output (I/O) device(s)  112  may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance  100 . 
       FIG. 2  is a block diagram of an example microprocessor suitable for implementing a tamper resistant fuse design, in accordance with one example embodiment of the invention. Microprocessor  102  may include processing unit(s)  202  and fuse block  204 , which may include keys  206  and ID&#39;s  208  as shown. Microprocessor  102  may also incorporate components or functions not shown, for example, memory controller  104 . 
     Processing unit(s)  202  represent the logical and functional elements of microprocessor  102 . In some examples, processing units(s)  202  may include processor cores, floating point units, controllers, registers, pointers, etc. 
     Fuse block  204  represents hardwired values that are programmed by selectively blowing fuses or antifuses or other components that may benefit from the teachings of the present invention. While shown as including keys  206  and ID&#39;s  208 , fuse block  204  may include other fields or values that may benefit from a tamper resistant fuse design described herein. Keys  206  may represent secret encryption keys used by processing unit(s)  202  to implement secure communications. ID&#39;s  208  may represent manufacturer or system or other unique identification that may benefit from a tamper resistant fuse design described herein. 
       FIG. 3  is a block diagram of an example tamper resistant fuse design, in accordance with one example embodiment of the invention. Fuse block  204  may include unblown fuse  302 , blown fuse  304 , bit line  306 , bit line  308 , control voltage  310 , select signal  312  and parallel elements  314 . Fuses  302  and  304  may comprise a portion of keys  206  or ID&#39;s  208  and may have been programmed during a manufacturing process. Processing unit(s)  202  may access the values stored in fuses  302  and  304  by enabling select signal  312  and reading bit lines  306  and  308 , respectively. Control voltage  310  may propagate to bit line  306  since unblown fuse  302  serves as a closed circuit while control voltage  310  would not have a dissipation path (if not for parallel elements  314 ) to bit line  308  since blown fuse  304  serves as an open circuit, thereby creating a potentially observable voltage contrast between fuses  302  and  304 . 
     Parallel elements  314  may represent resistors or fuse elements in parallel to fuses  302  and  304  to provide a potential dissipation path around the fuses. Parallel elements  314  would have a resistance chosen to be considerably higher than unblown fuse  302 , so that blown fuse  304  would not be mistakenly sensed as being unblown. Parallel elements  314  would also not have so high a resistance that parallel elements  314  serves as an open circuit, such that there would be no effective dissipation path around blown fuse  304 . 
     In one embodiment, parallel elements  314  are metal wires of a same material as fuses  302  and  304 . In another embodiment, parallel elements  314  are metal wires of a different material than fuses  302  and  304 . Parallel elements  314  may comprise, but are not limited to being, metals such as platinum or tungsten, for example. 
       FIG. 4  is a block diagram of an example tamper resistant fuse design, in accordance with one example embodiment of the invention. Fuse block  204  may include antifuse  402  and parallel element  404 . Antifuse  402  may serve as an open circuit when unblown and may become a closed circuit when blown. Parallel element  404  may be the same as or different than parallel elements  314 . Parallel element  404  would have a resistance chosen to be considerably higher than antifuse  402  when blown (yet less than an open circuit), so that an unblown antifuse  404  would not be mistakenly sensed as being blown. 
     Although embodiments of the present invention have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this invention. More particularly, reasonable variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the foregoing disclosure, the drawings and the appended claims without departing from the spirit of the invention. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.