Abstract:
In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Description:
BACKGROUND  
       [0001]     The phase-locked loop (PLL) is a versatile electronic circuit used in a wide variety of applications, including frequency synthesis, clock recovery, clock multiplication, and clock regeneration. In large, high-speed integrated circuits (including application-specific integrated circuits, field-programmable gate arrays, network processors, and general purpose microprocessors), PLLs have become commonplace. On-chip PLL clock multipliers are used on these chips to generate a high-frequency clock signal that is a multiple of, and in phase with, a system clock or input/output (I/O) clock. PLLs may also be used on these chips to resynchronize and realign clocks in deep clock distribution trees to reduce clock skew.  
         [0002]      FIG. 1  illustrates an example block diagram of a PLL  100 . The PLL  100  includes a phase-frequency detector (PFD)  110 , a charge pump (CP)  120 , a filter (e.g., low pass filter (LPF))  130 , and an oscillator  140 . The output frequency of the oscillator  140  is controlled by one or more input control signals. In operation, the PLL  100  adjusts the oscillator  140  to match (in both frequency and phase) a reference input  160 . The PLL  100  may also include a divider  150  on a feedback loop from the oscillator  140  to the PFD  110 . The divider  150  takes PLL output  165  and divides it by N so that the divided signal  170  is compared to the reference input. This enables the PLL output  165  to be N times higher in frequency than the reference input  160 , allowing the PLL  100  to perform frequency multiplication.  
         [0003]     A self-biased PLL (SBPLL) is used to create on-chip PLLs that have low jitter and are relatively insensitive to integrated circuit process variations, supply voltage and operating temperature (PVT). However, a major weakness of the SBPLL is that the oscillator output is subject to amplitude variability and common mode disturbances during dynamic operation of the PLL (e.g., acquisition, locking). In particular, operational correction can lead to the front-end oscillator amplifier and the following amplifying stages (the so-called “post-oscillator amplifiers”) being biased out of their optimal range (sweet spot), causing pulse evaporation (truncation, or dropped output clocks) and functional failure. This problem manifests as a non-monotonic oscillator control surface (output frequency versus control inputs) which may lead to one or more of the following: long lock time or lock failure due to positive feedback, sensitivity to power supply noise, and functional sensitivity to large reference and/or feedback clock noise.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0004]     The features and advantages of the various embodiments will become apparent from the following detailed description in which:  
         [0005]      FIG. 1  illustrates an example phase-locked loop (PLL) circuit, according to one embodiment;  
         [0006]      FIG. 2  illustrates an example self-biased PLL (SBPLL) circuit, according to one embodiment;  
         [0007]      FIG. 3  illustrates a schematic of an example SBPLL, according to one embodiment;  
         [0008]      FIG. 4  illustrates a simplified schematic of an example SBPLL for reducing the oscillator common mode gain, according to one embodiment;  
         [0009]      FIG. 5  illustrates a simplified schematic of an example SBPLL for reducing oscillator common mode gain while providing improved stability through the decoupling of a portion of the NBias signal provided to the oscillator, according to one embodiment;  
         [0010]      FIG. 6  illustrates an example second NBias generator for varying proportion of the two NBias signals, according to one embodiment;  
         [0011]      FIG. 7  illustrates an example of a multi-stage oscillator, according to one embodiment; and  
         [0012]      FIG. 8  illustrates an example stage of an oscillator, according to one embodiment.  
     
    
     DETAILED DESCRIPTION  
       [0013]      FIG. 2  illustrates an example self-biased phase-locked loop (SBPLL)  200 . The SBPLL  200  includes a phase-frequency detector (PFD)  210 , a charge pump (CP)  220 , a filter (e.g., LPF)  230 , a bias generator (BG)  240 , and an oscillator  250 , and may include a divider  260 . The output frequency of the oscillator  250  is controlled by one or more control inputs. The control inputs may be voltages and the oscillator  250  may be a voltage controlled oscillator (VCO)). Alternatively, the control inputs may be currents or some combination of currents and voltages and the oscillator  250  may be current controlled or current/voltage controlled.  
         [0014]     The SBPLL  200  uses negative feedback to adjust the oscillator  250  such that the frequency of an oscillator output  255  or a divided oscillator output  265  matches (in both frequency and phase) a reference input  270 . The PFD  210  compares the frequency and phase difference between the reference signal  270  and the oscillator/divided oscillator output  255 / 265  and generates one or more output signals based on this difference. As illustrated, the PFD  210  may generate an UP signal  212  or a DOWN signal  214 . The PFD  210  generates UP signals  212  when the frequency (phase) of the oscillator/divided oscillator output  255 / 265  is lower than (lags) the reference signal  270 . The PFD  210  generates DOWN signals  214  when the frequency (phase) of the oscillator/divided oscillator output  255 / 265  is higher than (leads) the reference signal  270 . The UP and DOWN signals (charge pulses)  212 ,  214  generated are based on the amount of lag or lead respectively. The CP  220  and the LPF  230  smooth and condition the pulses from the PFD  210  and generate two control signals, a proportional control signal  232  and an integrating control signal  234 .  
         [0015]     The integrating control signal  234  represents the net accumulated (integrated) charge from the previously generated UP signals  212  and DOWN signals  214 . The integrating control signal  234  also represents the dominant pole of the transfer function for the PLL  200 . The proportional control signal  232  represents, more directly, the instantaneous UP signals  212  and DOWN signals  214 . The proportional control  232  also represents the zero of the transfer function for the PLL  200 . The proportional control signal  232  and the integrating control signal  234  are fed to the BG  240 . The BG  240  processes these signals and generates control/bias signals, PBias  242  and NBias  244 .  
         [0016]      FIG. 3  illustrates a schematic of an example SBPLL  300 . The SBPLL  300  includes a charge pump  310  (e.g.,  220  of  FIG. 2 ), a filter  320  (e.g.,  230 ), a bias generator  330  (e.g.,  240 ), and an oscillator  340  (e.g.,  250 ). The charge pump  310  includes an integrating charge pump (CP 1 )  312  for generating an integrating control signal and a proportional charge pump (CP 2 )  314  for generating a proportional control signal. The filter  320  includes capacitors  322 ,  324  to filter the integrating control signal and the proportional control signal respectively.  
         [0017]     The bias generator  330  includes an NBias generator  350  and a PBias generator  360  to generate NBias and PBias signals for the oscillator  340  respectively. The NBias generator  350  includes an operational amplifier  352  and transistors  354 ,  356 , and  358  connected in series. According to one embodiment, the transistors  354  and  356  may be NMOS FETs and the transistor  358  may be a PMOS FET connected as a diode. The integrating control signal from CP 1   312  is provided to the NBias generator  350  as one input of the operational amplifier  352 . A second input of the operational amplifier  352  is an output from the transistors  354 ,  356 , and  358 . An output of the amplifier  352  is provided to a gate of the transistor  354 . The amplifier output is a biased integrating control signal and is an output of the NBias generator  350 . The NBias output is provided to an “N” input of the oscillator  340 .  
         [0018]     The PBias generator  360  includes transistors  362 ,  364 , and  366  connected in series. According to one embodiment, the transistors  362  and  364  may be NMOS FETs and the transistor  366  may be a PMOS FET connected as a diode. The NBias output is provided to a gate of the transistor  362 . The proportional control signal from the CP 2   314  is provided to the PBias generator  360  and may be biased by the transistors  362 ,  364 , and  366 . The biased proportional control signal is an output of the PBias generator  360  and is provided to a “P” input of the oscillator  340 .  
         [0019]     The use of the NBias output (the biased proportional control signal) in the PBias generator  360  provides some amount of biasing balance in the oscillator oscillatory signals. However, the proportional control signal is fed only to the “P” input of the oscillator  340 . This tends to unbalance the oscillator bias during transitions in the proportional control. In fact, the oscillator  340  may act as a common mode amplifier to the “P” input, causing common mode shift and amplitude shrink in oscillator output, and stress to the post-oscillator path. Common mode shift and amplitude shrink in the oscillator output manifests as a non-monotonic oscillator control surface (output frequency versus control inputs). A non-monotonic oscillator control surface may lead to one or more of the following: pulse evaporation (truncation, or dropped output clocks), long lock time or lock failure due to positive feedback, sensitivity to power supply noise, and functional sensitivity to large reference and/or feedback clock noise.  
         [0020]      FIG. 4  illustrates a schematic of an example SBPLL  400  for reducing the oscillator common mode gain. The SBPLL  400  is similar to the SBPLL  300  in that it includes an integrating charge pump (CP 1 )  412  (e.g.,  312 ), a proportional charge pump (CP 2 )  414  (e.g.,  314 ), a filter (not illustrated), an NBias generator  470 , a PBias generator  460  (e.g.,  360 ) and an oscillator  440  (e.g.,  340 ).  
         [0021]     The NBias generator  470  includes an operational amplifier  452  (e.g.,  352 ), transistors  454 ,  456 ,  458  (e.g.,  354 ,  356 ,  358 ) and a transistor  472  (coupling transistor) in parallel to the transistor  458 . The transistor  472  receives the proportional control signal from the CP 2   414 , which provides a modified feedback path from the CP 2   414  to the “N” input of the oscillator  440 . The modified feedback reduces the oscillator common mode gain. The modified feedback path transfers a portion of the proportional control signal to the “N” input of the oscillator  440  via the NBias generator  470 . The proportional control signal is added in a direction, and with an amplitude, that minimizes the oscillator  440  signal attenuation to stabilize the common mode amplification. The portion of the proportional control signal coupled into the NBias generator  470  may be determined by a ratio of the number of coupling transistors to the total number of coupling transistors and diode-connected transistors (acting as resistive elements). As illustrated in  FIG. 4 , the portion of the proportional control signal coupled into the NBias generator  470  is approximately 50% based on the use of one coupling transistor  472  and one diode-connected transistor  458  (1 coupling divided by total of 2 (1 coupling plus 1 diode)).  
         [0022]     The feedback of the proportional control signal from the CP 2   414  into the NBias generator  470  stabilizes the behavior of the oscillator  440  during a perturbation in the phase-locked loop. During an event where the output of the CP 2   414  drops to a lower voltage, the oscillator  440  increase in frequency is accompanied by stable output common mode with little attenuation. However, the NBias signal provided to the N input of the oscillator  440  may not allow the use of significant decoupling because a large decoupling capacitor connected to the NBias signal would slow the propagation delay of the proportional control (zero), leading to a higher than desired loop damping factor and possible loop stability problems. Not enabling decoupling of the NBias signal may result in instability of the SBPLL  400 .  
         [0023]      FIG. 5  illustrates a simplified schematic of an example SBPLL  500  for reducing oscillator common mode gain while providing improved stability through the decoupling of a portion of the NBias signal provided to the oscillator. The SBPLL  500  includes an integral charge pump (CP 1 )  512 , a proportional charge pump (CP 2 )  514 , a filter (not illustrated), a first NBias generator  520 , a PBias generator  530 , a second NBias generator  540  and an oscillator  550 .  
         [0024]     The first NBias generator  520  include an operational amplifier  522  and transistors  524  and  526  connected in series with a diode  528  (pair of parallel transistors connected as diodes). According to one embodiment, the transistors  524  and  526  may be NMOS FETs and the transistor pair may be PMOS FETs. The integrating control signal from CP 1   512  is provided as one input of the operational amplifier  522 . A second input of the operational amplifier  522  is an output from the transistors  524 ,  526 , and  528 . An output of the amplifier  522  is provided to a gate of the transistor  524 . The amplifier output is a biased integrating control signal and is an output of the first NBias generator  520 . The output of the first NBias generator  520  may be decoupled using a capacitor  560  to reduce thermal noise. The decoupled first NBias output is provided to an “N 1 ” input of the oscillator  550 . The first NBias generator  520  uses only the integral control signal from CP 1   512  and does not receive the proportional control signal from CP 2   514 .  
         [0025]     The PBias generator  530  includes transistors  532  and  534  connected in series with a diode  536  (pair of parallel transistors connected as diodes). According to one embodiment, the transistors  532  and  534  may be NMOS FETs and the transistor pair may be PMOS FETs. The NBias output is provided to a gate of the transistor  532 . The proportional control signal from the CP 2   514  is provided to the PBias generator  530  and may be biased by the transistors  532 ,  534 , and the diode  536 . The biased proportional control signal is an output of the PBias generator  530  and is provided to a “P” input of the oscillator  550 .  
         [0026]     The second NBias generator  540  includes an operational amplifier  542  and transistors  544 ,  545 ,  546 ,  547 ,  548 . The transistor  547  is connected as a diode and the transistor  548  is a coupling transistor. According to one embodiment, the transistors  544 ,  545  and  546  may be NMOS FETs and the transistors  547  and  548  may be PMOS FETs. The integrating control signal from CP 1   512  is provided as one input of the operational amplifier  542 . A second input of the operational amplifier  542  is an output from the transistors  544 ,  545 ,  546 ,  547 ,  548 . The decoupled first NBias output is provided to a gate of transistor  544 . An output of the amplifier  542  is provided to a gate of the transistor  545 . The proportional control signal from the CP 2   514  is provided to a gate of transistor  548 .  
         [0027]     Receiving the proportional control signal provides a modified feedback path from the CP 2   514  to the “N 2 ” input of the oscillator  550 . The modified feedback reduces the oscillator common mode gain. The proportional control signal is added to the “N 2 ” input of the oscillator  550  in a direction, and with an amplitude, that minimizes the oscillator  550  signal attenuation to stabilize the common mode amplification. The portion of the proportional control signal coupled into the second NBias generator  540  may be determined by a ratio of the number of coupling transistors  548  to the total number of coupling transistors  548  and diode-connected transistors (acting as resistive elements)  547 .  
         [0028]     The amplifier output is a biased integrating control signal and is an output of the second NBias generator  540 . The second NBias output is provided to an “N 2 ” input of the oscillator  550 . The combination of the heavily decoupled first NBias output signal with only integral feedback (N 1  input) with the a second NBias output signal with integral and proportional feedback simultaneously (N 2  input) provides for reduced oscillator common mode gain and improved stability of the oscillator  550  by reducing thermal noise. The SBPLL  500  maximizes decoupling on the first NBias output to combat thermal noise without compromising the loop stability.  
         [0029]      FIG. 6  illustrates an example second NBias generator  600  (e.g.,  540  of  FIG. 5 ) where the proportion of each of the two NBias signals may be varied. The second NBias generator  600  includes an operational amplifier  610  receiving an integrated control signal (from CP 1 ), a coupling transistor  620  receiving a proportional control signal (from CP 2 ), a diode connected transistor  630 , and one or more transistor replica stacks  640 ,  650 ,  660 ,  670 . Each replica stack  640 ,  650 ,  660 ,  670  include a pair of transistors  642 ,  644 ,  652 ,  654 ,  662 ,  664 ,  672 ,  674  respectively. The top transistor  642 ,  652 ,  662 ,  672  of each replica stack may be coupled to control inputs BI 0 , BI 1 , BI 0 #, BI 1 # respectively. The control inputs BI 0 , BI 1 , BI 0 #, BI 1 # are used to control whether or not the particular stack is switched into the bias generator output circuit. The bottom transistors  644 ,  654  of the replica stacks  640 ,  650  are connected to the output of the first NBias generator. The bottom transistors  664 ,  674  of the replica stacks  660 ,  670  are connected to the output of the second NBias generator (operational amplifier  610 ).  
         [0030]     By controlling the control inputs BI 0 , BI 1 , BI 0 #, BI 2 # on each of the control transistors  642 ,  652 ,  662 ,  672 , the relative contribution of NBias  1  and Nbias  2  may be varied to achieve a desired balance of common mode gain and improved stability after fabrication. Although two replica stacks are shown connected to each NBias generator, any number of replica stacks may be used for each. A larger number of replica stacks provides for finer control of the two NBias signals provided to the oscillator.  
         [0031]      FIG. 7  illustrates an example VCO oscillator  700  (e.g.,  550  of  FIG. 5 ). The oscillator  700  includes a plurality of stages  710  (five stages are illustrated) organized as a ring oscillator. Each stage feeds its output to the input of the succeeding stage, with the output of the final stage feeding back to the input of the first stage. The oscillator receives a PBias input  720  (e.g., from  530  of FIG,  5 ), an NBias  1  input  730  (e.g., from  520 ) and an NBias  2  input  735  (e.g., from  540 , from  600  of  FIG. 6 ) and provides an output  740 .  
         [0032]      FIG. 8  illustrates an example oscillator stage  800  (e.g.,  710  of  FIG. 7 ). The oscillator stage  800  includes a differential pair of transistors  805 ,  810 , two current source (current tail) transistors  835  and  837 , transistor pairs  840  and  845  acting as voltage controlled resistors, transistors  850  and  855  acting as load capacitors, and elements  860  and  865  acting as metal options to provide a means for adjusting, during device fabrication, the maximum frequency of the oscillator. A PBias input  870  is provided to the transistor pairs  840  and  845 . An NBias  1  input  880  is provided to the current source transistors  835  and an NBias  2  input  885  is provided to the current source transistor  837 . Differential inputs  815  and  820  from a previous oscillator stage are provided to the differential transistor pair  805 ,  810 . Differential outputs  825  and  830  are provided to a next oscillator stage.  
         [0033]     Although the various embodiments have been illustrated by reference to specific embodiments, it will be apparent that various changes and modifications may be made. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.  
         [0034]     Different implementations may feature different combinations of hardware, firmware, and/or software. It may be possible to implement, for example, some or all components of various embodiments in software and/or firmware as well as hardware, as known in the art. Embodiments may be implemented in numerous types of hardware, software and firmware known in the art, for example, integrated circuits, including ASICs and other types known in the art, printed circuit broads, components, etc.  
         [0035]     The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.