Abstract:
A method of reducing jitter in a phase locked loop (PLL) includes receiving a first reference signal, quadrupling a frequency of the first reference signal to produce a second reference signal, and providing the second reference signal to a frequency phase detector of the PLL. The method may also include equalizing the second reference signal prior to providing the second reference signal to the frequency phase detector. The method can be accomplished by a circuit, wherein quadrupling the frequency of the first reference signal is performed by two frequency doublers arranged in series. The step of equalizing can be performed by two equalizers, each one configured to equalize an output of a respective frequency doubler.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates generally to reducing jitter in a phase locked loop (PLL), and more particularly to methods and apparatus for producing a reference frequency signal for a PLL using a reference frequency quadrupler. 
     A conventional phase locked loop (PLL) typically includes a frequency phase detector which receives a reference signal, a filter, a voltage-controlled oscillator (VCO), and a divider circuit. If the reference signal received by the frequency phase detector has a relatively low frequency, a large feedback divider ratio is required by the PLL. A large feedback divider ratio requires that the divider circuit have a relatively large number of dividers, which undesirably introduces phase “jitter” into the signals. The large feedback divider ratio also means that the loop gain of the PLL will be lower for a given supply voltage, which makes the gain distribution for noise less ideal and also increases jitter. 
     One solution to this problem is to increase the frequency of the reference signal received by the frequency phase detector. However, conventional XOR-based frequency doublers typically distort the duty cycle of reference signals due to integrated circuit (IC) process variations. This distortion may be severe enough to render the approach ineffective. 
     SUMMARY OF THE INVENTION 
     According to the present invention, a jitter reduction circuit for a phase locked loop (PLL) includes a first frequency doubler, a first equalizer having an input coupled to an output of the first frequency doubler, a second frequency doubler having an input coupled to an output of the first equalizer, a second equalizer having an input coupled to an output of the second frequency doubler, and a frequency phase detector having a first input coupled to an output of the second equalizer and a second input coupled to an output of a voltage controlled oscillator (VCO) of the PLL. 
     Each frequency doubler is configured to double a frequency of a reference signal provided thereto. The combination of the two frequency doublers in series quadruples the reference signal into the PLL. The first equalizer helps restore the duty cycle of the signal before it enters the second frequency doubler, and the second equalizer helps restore the duty cycle before the signal enters the PLL. The increased (quadrupled) reference frequency allows the PLL to have a smaller feedback divider ratio and therefore fewer dividers; fewer dividers result in less circuitry in the PLL feedback path which reduces jitter. A reduced divider ratio also allows a higher loop gain for a given supply voltage, which produces a more ideal gain distribution for noise and reduces jitter as well. Importantly as well, controls for the selection of the initial reference signal are advantageously provided. 
     The invention, embodied as a method, includes receiving a first reference signal, quadrupling a frequency of the first reference signal to produce a second reference signal, and equalizing the second reference signal to produce the PLL rat reference signal. The step of quadrupling a frequency of the first reference signal may include doubling a frequency of the first reference signal to produce an intermediate reference signal having a frequency that is twice that of the first reference signal. The step further may include doubling the frequency of the intermediate reference signal to produce a second reference signal having a frequency that is four times that of the first reference signal. The method further may include providing the second reference signal to the PLL. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of the present invention for use with a phase locked loop (PLL); 
     FIG. 2 is a schematic block diagram of a frequency doubler of FIG. 1; 
     FIGS. 3A-3C are graphs of reference signals at various locations in the diagram of FIG. 2; 
     FIG. 4 is a flowchart describing a method of producing a reference frequency signal using the circuitry shown in FIG.  1 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     According to the present invention, circuitry for a phase locked loop (PLL) includes a frequency quadrupler and an equalizer. In one embodiment, the frequency quadrupler includes a first frequency doubler and a second frequency doubler. The equalizer preferably includes a first equalizer and a second equalizer. 
     In a preferred embodiment, the circuitry includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each one of the frequency doublers includes a delay circuit having an input coupled to the input of the frequency doubler, and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler. The combination of the two frequency doublers in series quadruples the reference signal into the PLL, which allows the PLL to have a smaller feedback divider ratio and a higher loop gain for reducing jitter. A reference signal input is configured to provide one or more reference signals, having a large range of frequencies. Advantageously, controls for the selection of the initial reference signal are provided. 
     FIG. 1 is a schematic block diagram of circuitry  100  which includes a jitter reduction circuit  101  for a reference signal to a PLL  130 . Circuitry  100  may be embodied in an integrated circuit (IC) device. The jitter reduction circuit  101  includes a reference signal input  102 , a frequency doubler  104 , an equalizer  106 , a frequency doubler  108 , an equalizer  110 , and a frequency phase detector  112 . The frequency phase detector  112  is also a part of a phase locked loop (PLL), which further includes a filter/voltage controlled oscillator  114  and a divider  116 . Reference signal input  102  may include conventional circuitry, such as a crystal oscillator. 
     In the preferred embodiment, an input of frequency doubler  104  is coupled to an output of reference signal generator  102 , and an output of frequency doubler  104  is coupled to an input of equalizer  106 . Similarly, an input of frequency doubler  108  is coupled to an output of equalizer  106 , and an output of frequency doubler  108  is coupled to an input of equalizer  110 . Equalizer  110  has an output which is fed into an input of PLL  130 . Each one of frequency doublers  104  and  108  has the structure and functionality as shown and described in relation to FIGS.  2  and  3 A- 3 C. 
     The PLL of FIG. 1 includes a frequency phase detector  112 , a filter and voltage-controlled oscillator (VCO)  114 , and a divider  116 . Frequency phase detector  112  has a first input coupled to the output of equalizer  110  and an output coupled to an input of filter and VCO  114 . Although shown as a single block, filter and VCO  114  can include a filter coupled in series with a VCO where an output of the filter is coupled to an input of the VCO. An output of filter and VCO  114  is coupled to an input of divider  116 , which has an output coupled to a second input of frequency phase detector  112 . 
     Referring now to FIG. 2, a schematic block diagram of frequency doubler  104  of FIG. 1 is shown. The schematic block diagram of FIG. 2 may also apply to frequency doubler  108 , but illustrates only frequency doubler  104  for simplicity. Frequency doubler  104  includes a delay circuit  202  and an XOR circuit  210 . Delay circuit  202  is configured to provide a 90° delay for a particular frequency X. Delay circuit  202  has an input which is the input to frequency doubler  104 , and an output coupled a first input  214  of XOR circuit  210 . A second input  216  of XOR circuit  210  is coupled to the input of frequency doubler  104 . The delayed signal on input  214  is XOR&#39;d with the signal on input  216 , to effectively double the frequency of an input signal on input  118 , and produce the doubled frequency signal on output  120 . 
     Referring to FIG. 3A, a signal  302  representing the first reference signal at lines  118  and  216  is shown. In FIG. 3B, a signal  304  representing the first out-of-phase signal at line  214  is shown. Since delay circuit  202  of FIG. 2 is configured as a 90° delay circuit for frequency X, signal  304  of FIG. 3B is 90° out-of-phase with signal  302  of FIG.  3 A. In FIG. 3C, a resulting signal  306  at line  120  which is the XOR of the two aforementioned signals is shown. As illustrated, resulting signal  306  has a frequency 2*X. 
     FIG. 4 is a flowchart describing a method of producing a reference signal, which can be performed using circuitry  100  shown and described in relation to FIGS. 1, and  2 . In the following description, FIGS. 1 and 4 will be referred to in combination. Beginning at a start block  400  of FIG. 4, a reference signal having a frequency X is generated by reference signal input  102  (step  402 ). Frequency X may be, for example, about 155 MHz. Next, the frequency X of the reference signal is doubled by frequency doubler  104  to produce a signal having a frequency 2*X (step  404 ). Frequency 2*X may be, for example, about 210 MHz. This signal is equalized by equalizer  106  (step  406 ). 
     Steps  404  (frequency doubling) and  406  (equalizing) are basically repeated in steps  408  and  410 . More particularly, the equalized signal having frequency 2*X is doubled by frequency doubler  108  to produce a signal having a frequency 4*X (step  408 ). Frequency  4 *X may be, for example, about 622 MHz. This resulting signal is then equalized by equalizer  110  (step  410 ). Finally, the equalized signal having frequency 4*X is used in PLL  130  (step  412 ). The flowchart ends at a finish block  414 , but the method repeats continuously for a continuously applied reference signal from reference signal generator  102 . 
     Several advantages are conferred with use of the present invention. Conventional XOR-based frequency doublers typically distort the duty cycle of the signal waveform over the process corners of IC fabrication. In the present invention, however, the first equalizer helps restore the duty cycle of the signal before it enters the second frequency doubler, and the second equalizer helps restore the duty cycle before the signal enters the frequency phase detector of the PLL. This increased (quadrupled) reference frequency at the input of the frequency phase detector allows the PLL to have a smaller feedback divider ratio and therefore fewer dividers; fewer dividers result in less circuitry in the PLL feedback path and reduces jitter. A reduced divider ratio also allows a higher loop gain for a given supply voltage, which produces a more ideal gain distribution for noise and reduces jitter as well. 
     Thus, a novel reference jitter reduction circuit suitable for use with a PLL has been described herein. The jitter reduction circuit may include a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; a second equalizer having an input coupled to an output of the second frequency doubler; and an output of the second equalizer for coupling to an input of the PLL. The PLL may include a frequency phase detector having a first input coupled to the output of the second equalizer; a filter having an input coupled to an output of the frequency phase detector; a voltage-controlled oscillator (VCO) having an input coupled to an output of the filter; and a divider having an input coupled to an output of the VCO and an output coupled to a second input of the frequency phase detector. 
     In addition, an inventive method described herein includes receiving a first reference signal having a frequency X; doubling the frequency X of the first reference signal to produce an intermediate reference signal having a frequency 2*X; equalizing the intermediate reference signal to produce an equalized intermediate reference signal; doubling the frequency 2*X of the equalized intermediate reference signal to produce a second reference signal having a frequency 4*X; and equalizing the second reference signal to produce an equalized second reference signal, having a frequency that is approximately four times that of the original, or first, reference signal for use in a PLL. 
     It is to be understood that the above is merely a description of preferred embodiments of the invention and that various changes, alterations, and variations may be made without departing from the true spirit and scope of the invention as set for in the appended claims. None of the terms or phrases in the specification and claims has been given any special particular meaning different from the plain language meaning to those skilled in the art, and therefore the specification is not to be used to define terms in an unduly narrow sense.