Abstract:
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibilty in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions. The use of RFI in a processor containing multiple heterogeneous execution units which operate in parallel, such as VLIW or iVLIW processors, allows for efficient pipelining of algorithms across multiple execution units while minimizing the number of VLIW instructions required.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application claims the benefit of U.S. Provisional Application Ser. No. 60/077,766 filed Mar. 12, 1998 and entitled “Register File Indexing Methods and Apparatus for Providing Indirect Control of Register in a VLIW Processor.” 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to improvements in very long instruction word (VLIW) processing, and more particularly to advantageous register file indexing (RFI) techniques for providing indirect control of register addressing in a VLIW processor. 
     BACKGROUND OF THE INVENTION 
     One important processor model is that of vector processing. This model has been used in prior art super computers for many years. Typical features of this model are the use of specialized vector instructions, specialized vector hardware, and the ability to efficiently operate on blocks of data. It is this very ability to operate typically only on vector data types that makes the model inflexible and unable to efficiently handle diverse processing requirements. In addition, in prior art vector processors, support for control scalar processing was typically done in separate hardware or in a separate control processor. Another processor model is the prior art very long instruction word (VLIW) processor model which represents a parallel processing model based on the concatenation of standard uniprocessor type single function operations into a long instruction word with no specialized multicycle vector processing facilities. To efficiently operate a block-data vector pipeline, it is important to have an efficient interface to deliver the individual vector elements. For this purpose, a successful class of prior art vector machines have been register based. The register based vector processors provide high performance registers for the vector elements allowing efficient access of the elements by the functional execution units. A single vector instruction tied to an implementation specific vector length value causes a block data multicycle operation. In addition, many vector machines have provided a chaining facility where operations on the individual vector elements are directly routed to other vector functional units to improve performance. These previous features and capabilities provide the background for the present invention. It is an object of the present invention to incorporate scalar, VLIW, and flexible vector processing capabilities efficiently in an indirect VLIW processor. 
     In typical reduced instruction set computer (RISC) and VLIW processors, the access of register operands is determined from short instruction word (SIW) bit-fields that represent the register address of operands stored in a register file. In register-based vector processors, specialized hardware is used. This hardware is initiated by a single vector instruction and automates the accessing of vector elements (operand data) from the dedicated vector registers. The multicycle execution on the block of data is also automated. 
     In the prior art, there have also been specialized hardware techniques used to support the automatic accessing of register operand data. For example, U.S. Pat. No. 5,680,600 which describes a technique for accessing a register file using a loop or repeat instruction to automate the register file addressing. This approach ties the register addressing to a loop or repeat instruction which causes a load or store instruction to be repeated while directing the register address to increment through a register file&#39;s address space. An electronic circuit is specified for reducing controller memory requirements for multiple sequential instructions. Thus, this prior art approach appears to be applied only to load and store type operations invoked by a special loop or repeat instruction. As such, it is not readily applicable to indirect VLIW ManArray processors as addressed further below. 
     SUMMARY OF THE INVENTION 
     A ManArray family of processors may suitably consist of multiple “indirect VLIW” (iVLIW) processors and processor elements (PEs) that utilize a fixed length short instruction word (SIW) of 32-bits. An SIW may be executed individually by one of up to eight execution units per processor and in synchronism in multiple PEs in a SIMD mode of operation. Another type of SIW is able to reference a VLIW indirectly to cause the issuance of up to eight SIW instructions in parallel in each processor and in synchronism in multiple PEs to be executed in parallel. 
     Operands are stored in register files and each execution unit has one or more read and write ports connected to the register file or files. In most processors, the registers selected for each port are addressed using bit fields in the instruction. With the indirect VLIW technique employed in the ManArray processor, the SIWs making up a VLIW are stored in a VLIW memory. Since each SIW fixes a register operand field by definition for a single operation on register accessed operand data, multiple VLIWs are required whenever a single operand field must be different as required by a processing algorithm. Thus, a suitable register file indexing technique for operation on blocks of data for use in conjunction with such processors and extendible more generally to parallel array processors will be highly advantageous. 
     This operand-data fixed register specification problem is solved by the present invention by providing a compact means of achieving pipelined computation on blocks of data using indirect VLIW instructions. A double indirect method of accessing the block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction, nor to repeat or loop instructions. Rather, the present technique, termed register file indexing (RFI) allows full programmer flexibilty in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions, and without being limited to use only with repeat or loop instructions. Utilizing the present invention, chaining operations are inherently available without any direct routing between functional units further simplifying implementations. In addition, the present register file indexing architecture reduces the VLIW memory requirements which can be particularly significant depending on the types of algorithms to be coded. 
     Further, when expressed as unrolled loops of VLIW instructions, many computations exhibit clear register usage patterns. These patterns are characteristic of computational pipelines and can be taken advantage of with the ManArray indirect vector processing embedded in an indirect VLIW processor as adapted as described further herein. 
     Among its other aspects, the present invention provides a unique initialization method for generating an operand register address, a unique double-indirect execution mechanism, a unique controlling method, and allows a register file to be partitioned into independent circular buffers. It also allows the mixing of RFI and non-RFI instructions, and a scaleable design applicable to multiple array organizations of VLIW processing elements. As addressed in further detail below, the invention reduces both the VLIW memory and, as a consequence, SIW memory requirements for parallel instruction execution in an iVLIW array processor. 
     These and other features, aspects and advantages of the invention will be apparent to those skilled in the art from the following detailed description taken together with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A illustrates a 2×2 ManArray iVLIW processor suitable for use in conjunction with the present invention; 
     FIG. 1B illustrates a typical prior art register addressing mechanism; 
     FIG. 2A illustrates an XV instruction encoding with RFI enabling bits in accordance with the present invention; 
     FIG. 2B illustrates an XV syntax/operation description suitable for use in the present invention; 
     FIG. 3A illustrates a ManArray miscellaneous register file (MRF) identifying the location of the RFI control registers; 
     FIG. 3B illustrates the MRFX 1  extension registers; 
     FIG. 3C illustrates the MRFX 2  extension registers, and identifies the RFI registers used in the sequence processor (SP) and processing elements (PEs); 
     FIG. 4A illustrates an MRFXAR register which controls the selection of the extension register; 
     FIG. 4B illustrates the data format for MRFXDR 1  and MRFXDR 2  wherein the RFI control registers are mapped as specified by the MRFXAR register values of FIG. 4A; 
     FIG. 5 illustrates preferred RFI control registers for use in conjunction with the present invention; 
     FIG. 6 illustrates exemplary specific control encodings used for each RFI port; 
     FIG. 7A illustrates a suitable load immediate (LIM) instruction encoding which may be used for loading the RFI control values of the present invention; 
     FIG. 7B illustrates an LIM syntax/operation description; 
     FIG. 8 illustrates an exemplary RFI control block diagram for the arithmetic execution units in accordance with the present invention; 
     FIG. 9 illustrates an exemplary RFI control block diagram for the load and store execution units in accordance with the present invention; 
     FIG. 10 illustrates a conventional full adder for use in the update adder logic units in each RFI port logic in one embodiment in accordance with the present invention; and 
     FIG. 11 illustrates a reduced cost RFI control block diagram for the arithmetic execution units in one embodiment in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION 
     Further details of a presently preferred ManArray architecture for use in conjunction with the present invention are found in U.S. patent application Ser. No. 08/885,310 filed Jun. 30, 1997, U.S. patent application Ser. No. 08/949,122 filed Oct. 10, 1997, U.S. patent application Ser. No. 09/169,255 filed Oct. 9, 1998, U.S. patent application Ser. No. 09/169,256 filed Oct. 9, 1998, U.S. patent application Ser. No. 09/169,072 filed Oct. 9, 1998, U.S. patent application Ser. No. 09/187,539 filed Nov. 6, 1998, U.S. patent application Ser. No. 09/205,558 filed Dec. 4, 1998, U.S. patent application Ser. No. 09/215,081 filed Dec. 18, 1998, U.S. patent application Ser. No. 09/228,374 filed Jan. 12, 1999, and U.S. patent application Ser. No. 09/238,446 filed Jan. 28, 1999, as well as, Provisional Application Serial No. 60/092,130 entitled “Methods and Apparatus for Instruction Addressing in Indirect VLIW Processors” filed Jul. 9, 1998, Provisional Application Serial No. 60/103,712 entitled “Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray” filed Oct. 9, 1998, Provisional Application Serial No. 60/106,867 entitled “Methods and Apparatus for Improved Motion Estimation for Video Encoding” filed Nov. 3, 1998, Provisional Application Serial No. 60/113,637 entitled “Methods and Apparatus for Providing Direct Memory Access (DMA) Engine” filed Dec. 23, 1998, and Provisional Application Serial No. 60/113,555 entitled “Methods and Apparatus Providing Transfer Control” filed Dec. 23, 1998, respectively, and incorporated by reference herein in their entirety. 
     In a presently preferred embodiment of the present invention, a ManArray 2×2 iVLIW single instruction multiple data stream (SIMD) processor  100  shown in FIG. 1A contains a controller sequence processor (SP) combined with processing element- 0  (PE 0 ) SP/PE 0   101 , as described in further detail in U.S. application Ser. No. 09/169,072 entitled “Methods and Apparatus for Dynamically Merging an Array Controller with an Array Processing Element”. Three additional PEs  151 ,  153 , and  155  are also utilized to demonstrate register file indexing and its scalable nature in accordance with the present invention. It is noted that the PEs can be also labeled with their matrix positions as shown in parenthesis for PE 0  (PE 00 )  101 , PE 1  (PE 01 )  151 , PE 2  (PE 10 )  153 , and PE 3  (PE 11 )  155 . The SP/PE 0   101  contains a fetch controller  103  to allow the fetching of short instruction words (SIWs) from a 32-bit instruction memory  105 . The fetch controller  103  provides the typical functions needed in a programmable processor such as a program counter (PC), branch capability, digital signal processing loop operations, support for interrupts, and provides the instruction memory management control which could include an instruction cache if needed by an application. In addition, the SIW I-Fetch controller  103  dispatches 32-bit SIWs to the other PEs in the system by means of a 32-bit instruction bus  102 . 
     In this exemplary system, common elements are used throughout to simplify the explanation, though actual implementations are not so limited. For example, the execution units  131  in the combined SP/PE 0   101  can be separated into a set of execution units optimized for the control function, e.g., fixed point execution units, and the PE 0 , as well as the other PEs  151 ,  153  and  155 , can be optimized for a floating point application. For the purposes of this description, it is assumed that the execution units  131  are of the same type in the SP/PE 0  and the other PEs. In a similar manner, SP/PE 0  and the other PEs use a five instruction slot iVLIW architecture which contains a very long instruction word memory (VIM) memory  109  and an instruction decode and VIM controller function unit  107  which receives instructions as dispatched from the SP/PE 0 &#39;s I-Fetch unit  103  and generates the VIM addresses-and-control signals  108  required to access the iVLIWs, identified by the letters SLAMD in  109 , stored in the VIM. The ManArray pipeline design provides an indirect VLIW memory access mechanism without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for the indirect execute iVLIW (XV) instructions as described in further detail in U.S. patent application Ser. No. 09/228,374 entitled “Methods and Apparatus to Dynamically Reconfigure the Instruction Pipeline of an Indirect Very long Instruction Word Scalable Processor”. The loading of the iVLIWs is described in further detail in U.S. patent application Ser. No. 09/187,539 entitled “Methods and Apparatus for Efficient Synchronous MIMD Operations with iVLIW PE-to-PE Communication”. Also contained in the SP/PE 0  and the other PEs is a common PE configurable register file  127  which is described in further detail in U.S. patent application Ser. No. 09/169,255 entitled “Methods and Apparatus for Dynamic Instruction Controlled Reconfiguration Register File with Extended Precision”. 
     Due to the combined nature of the SP/PE 0 , the data memory interface controller  125  must handle the data processing needs of both the SP controller, with SP data in memory  121 , and PE 0 , with PE 0  data in memory  123 . The SP/PE 0  controller  125  also is the source of the data that is sent over the 32-bit broadcast data bus  126 . The other PEs  151 ,  153 , and  155  contain common physical data memory units  123 ′,  123 ″ and  123 ′″ though the data stored in them is generally different as required by the local processing done on each PE. The interface to these PE data memories is also a common design in PEs  1 ,  2 , and  3  and indicated by PE local memory and data bus interface logic  157 ,  157 ′ and  157 ″. Interconnecting the PEs for data transfer communications is the cluster switch  171  more completely described in U.S. patent application Ser. No. 08/885,310 entitled “Manifold Array Processor”, U.S. application Ser. No. 09/949,122 entitled “Methods and Apparatus for Manifold Array Processing”, and U.S. application Ser. No. 09/169,256 entitled “Methods and Apparatus for ManArray PE-to-PE Switch Control”. The interface to a host processor, other peripheral devices, and/or external memory can be done in many ways. The primary mechanism shown for completeness is contained in the DMA control unit  181  that provides a scalable ManArray data bus  183  that connects to devices and interface units external to the ManArray core. The DMA control unit  181  provides the data flow and bus arbitration mechanisms needed for these external devices to interface to the ManArray core memories via bus  185 . 
     All of the above noted patents are assigned to the assignee of the present invention and incorporated herein by reference in their entirety. 
     Turning now to specific details of the ManArray processor apparatus as adapted to the present invention, this approach advantageously provides an efficient and flexible block-data operation capability through a double indirect mechanism. 
     Register File Indexing Programming View 
     Register file indexing (RFI) in accordance with one aspect of the present invention refers to methods and apparatus in each processing element and in the array controller for addressing the operand register file through a double indirect mechanism rather than directly through fields of an SIW, or through specialized vector instructions and vector hardware or with a required repeat or loop instruction. Each execution unit operates read and write ports of one or more register files. A read or write port consists of register selection address and control lines supplied to the register file, a data bus for register data being read from the register file for a read port, and a data bus for register data being written to the register file for a write port. The inputs to the register selection logic of these ports typically came only from bit-fields of the instruction being executed as shown in the prior art apparatus of FIG.  1 B. In FIG. 1B, the instruction received in a processor&#39;s instruction register  10  typically contained register file addresses which were typically latched in port address registers, such as the registers  12 ,  14  and  16 , and then directly used to address the register file, such as register file  20 , to support the instruction execution by units, such as store unit  22 , load unit  24 , ALU  26 , MAU  28  and DSU  30  of FIG.  1 B. 
     In addition to this typical method for register selection, RFI operation in accordance with the present invention allows each register file port of each execution unit to also be independently controlled through a double indirect mechanism using simple control circuitry as addressed further below. 
     RFI Operation 
     RFI operation may advantageously be embedded in the ManArray iVLIW architecture and invoked by a double indirect mechanism. An exemplary execute VLIW (XV) instruction  200  having 32 bit encoding format  201  is shown in FIG. 2A. A syntax/operation table  203  summarizing instruction syntax, the parameters or operands, and the operations carried out by the instruction  200  is shown in FIG.  2 B. ManArray RFI operation uses bits  20  and  21 , RFI operation bits  202 , in the execute VLIW (XV) instruction  200  as shown in FIG. 2A to enable RFI operation. 
     In further detail, the XV instruction  200  is used to indirectly cause individual instruction slots of a specified SP or PE VLIW Memory (VIM) to be executed. The VIM address is computed as the sum of a base VIM address register Vb (V 0  or V 1 ) plus an unsigned 8-bit offset VIMOFFS. Any combination of individual instruction slots may be executed via the execute slot parameter ‘E={SLAMD}’, where S=Store Unit (SU), L=Load Unit (LU), A=Arithmetic Logic Unit (ALU), M=Multiply-Accumulate Unit (MAU), and D=Data Select Unit (DSU). A blank ‘E=’parameter does not execute any slots. The unit affecting flags (UAF) parameter ‘F=[AMDN]’ overrides the UAF specified for the VLIW when it was loaded via a load VLIW (LV) instruction. The override selects which arithmetic instruction slot (A=ALU, M=MAU, D=DSU) or none (N=NONE) is allowed to set condition flags for this execution of the VLIW. The override does not affect the UAF setting specified via the LV instruction. A blank ‘F=’ selects the UAF specified when the VLIW was loaded. The register file indexing (RFI) parameter ‘R=[01N]’ is used to enable or disable RFI for this XV&#39;s indirect execution of the instruction slots. With ‘R=0’ (the RFI operation bits  202 =00 in FIG.  2 A), RFI operation is enabled and the RFI control register group  0  is selected. With ‘R=1’ (the bits  202 =01), RFI operation is enabled and the RFI Control Register group  1  is selected. With ‘R=N’ (the bits  202 =11), RFI operation is disabled. 
     The XV instruction with RFI enabled causes a second indirect operation to be initiated. The second indirect operation comes into play on the next XV instruction that is executed, wherein the register port addresses are indirectly specified through automatically incrementing hardware controlled in a manner specified by separate RFI control parameters. The RFI operation is described below, in the context of the ManArray pipeline, primarily concerned with the decode and execute phases of the pipeline. RFI control consists of four parts: 1) RFI control specification; 2) RFI initialization control; 3) RFI update control; and 4) RFI instruction execution. 
     RFI Control Specification 
     RFI control specification is preferably performed through RFI control registers. Each control register specifies all the RFI control information for the register ports used by a particular execution unit. There is a control field in the control register for each port and this field specifies whether or not the RFI operation is enabled for that particular port and, if enabled, specifies the RFI register update policy. 
     The RFI control registers are accessed through a ManArray miscellaneous register file (MRF)  300  illustrated in FIG.  3 A. This register file is unique in that additional registers can be added within the restricted MRF address space by address mapping additional registers to a single MRF address. The MRF extension registers  305  and  315 , shown in FIGS. 3B and 3C respectively, are accessed using the MRF extension address register (MRFXAR)  301  and the MRF extension data registers (MRFXDR)  302  and  303 . The two MRF extension data registers  302  and  303  are provided to simplify the implementation, and to separate the intended uses of each set of extension registers. A register address is written to the half-word H 1  or H 0  portion of the 32-bit MRFXAR register  410  of FIG. 4 using a load immediate instruction as illustrated in FIGS. 7A and B. The relationships of the respective parts of FIGS. 3A-3C, and  4 A and  4 B are more fully set forth as follows: 
     
       
         
               
               
             
           
               
                   
               
             
             
               
                 MRFX Addr1 
                 MRF Extension Register Address-1. This field contains the address 
               
               
                 402 (FIG. 4A) 
                 of a register within the MRF extension register group-1 of FIG. 3B. 
               
               
                   
                 When the MRFXDR1 302 of FIG. 3A is read or written, the 
               
               
                   
                 MRFX1 register in FIG. 3B specified by this address is the target of 
               
               
                   
                 the read or write operation. 
               
               
                 MRFX Addr2 
                 MRF Extension Register Address-2. This field contains the address 
               
               
                 406 (FIG. 4A) 
                 of a register within the MRF Extension register group-2 of FIG. 3C. 
               
               
                   
                 When the MRFXD2 303 of FIG. 3A is read or written, the 
               
               
                   
                 MRFX2 register in FIG. 3C specified by this address is the target of 
               
               
                   
                 the read or write operation. 
               
               
                 AutoIncrement 
                 When set, this bit causes the MRFX Address field 1 402 or field 
               
               
                 (AI1 or AI2) 
                 2 406 of FIG. 4A to increment by 1 after each read or write access to 
               
               
                 404 or 408 (FIG. 4A) 
                 the MRFXDR1 302 or MRFXDR2 303 of FIG. 3A. 
               
               
                 MRFX Data 
                 A Load/Store or DSU operation (COPY, BIT op) which targets the 
               
               
                 (MRFX1 or MRFX2) 
                 MRFXDR1 302 or MRFXDR2 303 of FIG. 3A will access the 
               
               
                 420 (FIG. 4B) 
                 MRFX register whose address is contained in bits [2:0] of the 
               
               
                   
                 MRFXAR1 402 or bits [8:6] MRFXAR2 406 of FIG. 4A. If the 
               
               
                   
                 auto increment bit 404 or 408 of the selected MRFXAR is set, then 
               
               
                   
                 the access will also cause the address in the MRFXAR1 or 
               
               
                   
                 MRFXAR2 to be incremented after the access. 
               
               
                   
               
             
          
         
       
     
     In a presently preferred embodiment, five execution units have RFI control. FIG. 3C shows a summary of an exemplary set of RFI control registers. These MRFX 2  registers  510 ,  520 ,  530 ,  540 ,  550 ,  560 ,  570 , and  580  are shown in further detail in FIG. 5, with each control register assigned to the read/write ports for the specified execution units. These execution units include arithmetic logic unit (ALU), multiply accumulate unit (MAU), data select unit (DSU), load unit, and the store unit. 
     The registers are used in two control groups ( 510 - 540 ), two save and restore context registers ( 550  and  560 ), and one register  580  to control the initialization of the RFI controls for each control group. A reserved register  570  is also shown. The first control group  0  includes RFIDLS 0   310  and RFIAM 0   320  in FIG.  3 C. Further details are shown in registers  510  and  520  of FIG.  5 . The second control group  1  includes RFIDLS 1   330  and RFIAM 1   340  with further details in registers  530  and  540 . 
     When an iVLIW is executed, one of the control groups is specified in the XV instruction via bits  21  and  20 , the RFI bits  202  of instruction  200  of FIG. 2 to allow RFI control of any port used by instructions in that VLIW. It will be recognized that the invention does not preclude using another mechanism for specifying the control information, or a subset of the control information, such as directly in an instruction. 
     Specifically, in control group  0 , RFIDLS 0   510  in FIG. 5 contains the port control information for the single Load Rt port  501 , the single Store Rs port  502 , the three operand ports for the DSU Ry  503 , Rx  504 , and Rt  505 . The second register in control group  0  RFIAM 0   520  contains the port control information for the three operand ports for the MAU Ry  521 , Rx  522 , Rt  523  and the three operands ports for the ALU Ry  524 , Rx  525 , and Rt  526 . Associated with the two control groups are initialization start bits which are contained for both control groups  0  and  1  in the RFIStart register  380  of FIG.  3 C and in more detail in register  580  of FIG.  5 . For control group  0 , the initialization start bits are located in the H 0  halfword  581  with a single bit per execution unit as follows: Store ports Start  0  bit- 4   587 , Load ports Start  0  bit- 3   586 , ALU ports Start  0  bit- 2   585 , MAU ports Start  0  bit- 1   584 , and DSU ports Start  0  bit- 0   583 . In a similar manner, the control registers RFIDLS 1   530 , RFIAM 1   540  for the second control group  1  are set up as shown in FIG.  5 . The initialization start bits for control group  1  are located in H 1  halfword  582  of RFIStart  580 . The other two RFI registers RFIDLS 1   550  and RFIAM 1   560  store the port address values to save the values of the port addresses upon an interrupt in support of a context save and restore operation. 
     Note that the control parameters may have any format that allows a required set of control information to be represented, as the invention does not require a particular format. An exemplary format  600  for a register file port is shown in greater detail in FIG.  6 . The RFI parameters are encoded into 4-bits as shown in columns  601  and  602 . This control information specifies the type of update to be applied to generate the address of the next register to be selected on the next RFI instruction execution. In the presently preferred embodiment, the control parameters are used to select an update increment value  603  to be added to the register address, and to specify the maximum sequential (incrementing by one) register file address range (RFBS) that can be selected  604 . As described further below, the starting register along with these parameters determines the actual register set which may be selected by the index. Columns  605 - 611  are used to describe the operation of the indirect vector apparatus shown in FIGS. 8 and 9. In these columns  605 - 611 , an “x” represents a “don&#39;t care” state. Column  612 , the applicable units column, specifies to which execution units the control parameters apply. 
     RFI Initialization Control 
     RFI initialization takes place in two steps, which are best understood with reference to FIGS. 8 and 9. FIG. 8 shows an exemplary RFI apparatus  800  for the port logic in the arithmetic units. FIG. 9 shows an exemplary RFI apparatus  900  for the port logic in the load and store units. This exemplary description represents a low cost configuration which uses control group  0  for the ALU, MAU, and DSU units and both control groups  0  and  1  for the Load and Store units. This is a subset of the architecture description outlined in FIG.  5  and represents a programmer restriction, where all options are available for all execution units in control group  0  while control group  1  is used primarily for block move, save, and restore operations. When an RFI XV instruction selects the second control group  1  in implementations which allow for only control group  0  on the arithmetic units, the arithmetic units default to the control group  0  specification even when control group  1  is specified. This subset minimizes on implementation expense and is described in more detail as follows. 
     First, control information as illustrated in FIG. 6 for each register file port is written into an RFI control register  810  and  910  by use of a load immediate (LIM) instruction  700  whose encoding format is shown in FIG.  7 A and whose syntax/operation  710  is shown in FIG.  7 B. The LIM instruction  700  is first used to load MRFXAR halfword H 1   410  of FIG. 4 to set up the desired extension RFI control register to be mapped to MRFXDR 2   303  in FIG.  3 A. Then, the LIM instruction loads a data value to the desired control register by using the address for MRFXDR 2 . Each halfword section of a control register is loaded separately by definition of the LIM instruction. 
     For purposes of clarity, the LIM data path from instruction register  804  H 0  halfword bits  15 - 0  is not shown. This data path is selectively controlled to load the H 0  halfword of the LIM instruction to either the low or high halfword portion of any of the MRF extension registers listed in FIG.  5 . For example, a LIM instruction could cause the loading of its H 0  halfword to the H 1  portion of the RFIAM 0  register  520  of FIG.  5 . In reference to the common arithmetic RFI port control logic of FIG. 8, one of the three control portions of RFIAM 0  would be located in an update control register  0  for that port, such as  810 , for, in this case, the ALU  852 . In a similar manner, the other two port control values would be loaded into their own port update control register 0s contained in their own RFI port control logic. Other ManArray instructions can load the RFI control registers through use of the MRF data bus  809 . The MRF data bus  809  is also used for saving the RFI port registers, for example, during a context switch operation. The specific LIM instruction description is as follows. The halfword form of the LIM instruction loads a 16-bit immediate value into the upper halfword (H 1 ) or lower halfword (H 0 ) of an SP or PE target register Rt. The 16-bit immediate value is interpreted as a sign “neutral” value, meaning that any value in the range −32768 to 65535 is accepted. This covers the 2&#39;s complement signed value range of −32768 to +32767 and the unsigned value range of 0 to 65535. 
     The word form of the LIM instruction loads a signed-extended 17-bit immediate value into the target register. The 17-bit signed value may be any value in the range −65536 to 65535. The encoding for the word form of LIM puts the magnitude of the value into the IMM 16  field and the sign bit is the LOC field bits  23  and  22  shown in FIG.  7 A. LOC field determines if the upper halfword is filled with all one or all zero bits. 
     In the second step of RFI initialization, a start bit, e.g. bit  583  for the DSU  854 , is set in the RFI Start Register, RFIStart of FIG. 5, that is located in the start bit and mux control block  812  for each of the arithmetic execution unit&#39;s ports and block  912  for a load or store unit&#39;s port. Each start bit controls the initialization for all the ports belonging to an execution unit. While this is the presently preferred format, the invention is not restricted to this format. The operation of setting this bit is performed by any instruction capable of writing to this register. At least one instruction of this type is available. The next instruction which invokes RFI control for this particular group and execution unit after the setting of this bit, hereafter referred to as the “RFI instruction”, has its execution unit&#39;s operand registers first selected by fields in the instruction word and then, with the next RFI instruction for this group and execution unit, has its execution unit&#39;s operand registers selected under control of the RFI logic shown in FIGS. 8 and 9. With the RFI XV instruction, as described in FIGS. 2A and 2B, a VLIW set of SIWs is indirectly retrieved from a local VIM (five SIWs as described herein for a ManArray implementation as in FIG.  1 A). For example, one of the set of five SIWs is loaded into an instruction register  804  as shown in FIG.  8 . The port RFI logic for the fetched SIW Rt&#39;s port is also shown in FIG.  8 . For the first execution of the fetched instruction, the Rt port address  805  is the starting address for an RFI block operation. The Rt port address  805  is passed through a multiplexer  814 , as controlled by the start bit and mux control block  812  via control signal  813 , to the port address register  816  via multiplexer output  811 . The Rt port address, now contained on output  811 , is latched into the port address register  816  at the end of the decode pipeline stage. The output of the port address register  816  directly addresses the register file  818  over signal path  817 . The operands are selected from the register file  818  and the SIW operation is executed in the specified execution unit. 
     Upon the next issuance of an RFI XV instruction, the operands are indirectly specified from the RFI logic. This is the second indirect specification in the operational sequence. The first indirect specification is through the RFI XV instruction which indirectly specified the SIW and the second indirect specification is through the RFI logic as set up via the RFI control parameters. In order to accomplish this, operation update control register  0   810 , update adder logic  830 , indexed port look ahead register  820 , multiplexers  814  and  822 , and update control logic  824  are used to generate the updated port address to be used in following RFI instruction executions. 
     The basic concept is that the address output  811  of the multiplexer  814  is available early enough in the decode cycle so that the update adder logic  830  can update the address based upon the update control logic  824  signals. The updated address  819  is selected by mux control signals  815  to pass though multiplexer  822  and loaded into the index port look ahead register  820  at the end of decode at the same time the present port address  811  is loaded into the port address register  816 . On the next RFI instruction, the look ahead register value  821  is used in place of the fetched SIW operand port address value and latched into the port address register  816  for the next execute cycle, while the update adder logic is again preparing the next port address to be used. After the first RFI instruction following the setting of the RFI start bit(s), the start bit(s) are cleared causing subsequent RFI instructions to have their SIW operand registers selected by corresponding indexed port look ahead registers. The start bit and mux control block  812  provide the control for determining whether an instruction&#39;s registers are selected by instruction fields or by RFI indexed port look ahead registers. Its inputs come from the instruction opcode  807 , the update control register  0   810 , and an RFI enable signal  825 . These signals along with pipeline control signals (not shown) indicating an instruction&#39;s progress in the pipeline, determine the register selection source via the multiplexer  814 . 
     The use of the indexed port look ahead register  820  allows non-RFI instructions to be intermixed between RFI operations without affecting the RFI register address sequence. When a non-RFI instruction is detected, the RFI logic preserves the required RFI state while the non-RFI instructions are executing. 
     RFI Update Control 
     When an RFI operation is invoked, the address of one or more registers in the register file  818  is supplied by the RFI logic. This logic updates the register address for the next cycle by adding or subtracting a constant from an address available in the early stages of the decode cycle while maintaining the generated port address within a particular set of register addresses. In the presently preferred embodiment, this is done by specifying an increment value and a register file block size (RFBS)  604  as shown in FIG. 6 for each port to be controlled. In the preferred embodiment, the RFBS value is an integer power of 2, such as 1,2,4,8, etc., and logically causes the register file to be partitioned into blocks of registers with RFBS sequentially addressed registers per block. Assume a starting register Rs (R current =Rs on the first update), an RFBS value M, a floor quotient Q=└Rs/M┘, and a positive update increment k, then the next register number, R next , in a sequence is given by: 
     
       
           R   next =(( R   current   +k )mod  M ) +Q*M.   
       
     
     Because the remainder of Rs/M is ignored due to the floor operation, the value of Q*M≠Rs. 
     As an example, assume that the starting register port address is 5, i.e. Rs=R 5  which also equals R current  for the first operation. Also, assume the update increment is k=2, and the RFBS is M=8. In FIG. 6, this exemplary setting corresponds to the row  620  which lists for FIG. 8 the corresponding signal values as follows: G 3 =x  606  and  831 , G 2 =0  607  and  832 , G 1 =1  608  and  833 , G 0 =1  609  and  834 , X 1 =1  610  and  835 , and X 0 =0  611  and  836 . The signals X 1  and X 0  provide the increment by 2 input to update adder logic  830 . The gate signals G 3 , G 2 , G 1 , and G 0  maintain the block size given an arbitrary starting register. The update adder logic  830  is made up of five standard full adders  861 ,  862 ,  863 ,  864  and  865 , shown in further detail in FIG.  10 . The carry out signal C i+1    1005  of full adder  1000  of FIG. 10 corresponds to the carry out signals  841 - 844  from each stage of the update adder  830 . These carry out signals are gated by AND gates  845 - 848  and gate signals  831 - 834  effectively creating the modulo-adder required by the specified control description of FIG.  6 . Under these assumptions, the successive instructions which specify this port using RFI will access registers in the following order: R 5 , R 7 , R 1 , R 3 , R 5 , R 7 , and so on. If the starting register is R 8 , then the sequence is; R 8 , R 10 , R 12 , R 14 , R 8 , R 10 , and so on. The present invention does not preclude using non-power of 2 increments and/or RFBSs, nor does it preclude using another mechanism of specifying a register address sequence within which to operate. For example, a read only memory can be used to replace the update control logic  824  and update adder logic  830  to provide any desired register port address sequences desired. Since using memory blocks may cause implementation wiring problems, being able to implement the update function in discrete logic is the presently preferred method. 
     FIG. 9 depicts the RFI logic  900  for the load and store units which have been identified to use two control register groups  910  and  950 , respectively. The XV instruction specifies which group is to be used via the bits  21 - 20   202  of FIG.  2 . In the exemplary system, when control register group  1  is indirectly specified, the load and store SIWs fetched from the VIM use update control register  1   950  as selected via mux control signal  951  through multiplexer  952  while the arithmetic units default to using control register group  0 . In alternative implementations, the RFI port logic of FIG. 9 can be used for each arithmetic execution unit providing two RFI contexts for all of the execution units. 
     In a VLIW processor, it is possible to have all ports of the register file under RFI control for a single instruction, such as the presently described XV instruction. Since the RFI port logic is independent between execution units, the ports can be individually controlled by SIW execution-unit-specific instructions. This means that if another instruction or group of instructions requires independent RFI control (i.e. a different set of control parameters) in addition to the XV instruction, another group of control registers could be assigned. Since the RFI set up latency is relatively small, the control register set as described in FIG. 5 can be easily shared with other RFI instructions. 
     Another register file indexing apparatus  1100  is shown in FIG.  11 . This RFI mechanism still uses the double indirect mechanism outlined in the other RFI approaches discussed relative to FIGS. 8 and 9. In the approach of FIG. 11, however, a programming restriction is enforced requiring that for the block of data being processed, RFI operations cannot be mixed with non-RFI operations. This approach is different than the approach used in FIGS. 8 and 9 which allows RFI and non-RFI instructions to be mixed. For some product definitions, this is not a problem and the simplified hardware approach of FIG. 11 can be used. 
     The operation of the apparatus  1100  of FIG. 11 is similar to the operation of the previous RFI approach. For example, the start bit for RFI initialization is used as previously described. The main difference in FIG. 11 is that no indexed port look ahead register, like register  820  of FIG. 8 is used. Rather, a port address register  1116  still addresses a register file  1118 , but update adder logic  1130  operation is displaced in time, as compared to the approach used in FIG. 8, operating on the latched port address register output  1117  during the execute cycle. In preparation for the next execute cycle, the update adder logic  1130  updates the output  1117  of the port address register  1116  as specified by an RFI update control register  1110  for this port. By the end of the present execute cycle, multiplexer  1114  is controlled via control input  1113  to select an update adder logic output  1119  to pass through multiplexer  1114  to output  1111 . The multiplexer  1114  output  1111  is then latched in the port address register  1116  at the start of the next execute cycle thereby updating the register file port address as specified by the RFI control set up previously. 
     In addition to the XV RFI enabling apparatus, other means of enabling RFI are used. The purpose of this additional mechanism is to decouple the RFI sequencing from only being used in the VLIW (XV) programming model. It is desirable to support block load, block store, and block move operations with single instruction execution, which can be independently done in the SP or concurrently in the PEs. Rather than use additional bits in SIWs to specify this operation, though this is not precluded by this invention, an alternate indirect mechanism to enable RFI is used. This savings in bits in the SIWs allows better use of the instruction format for standard operation encoding while not precluding the ability to achieve the RFI functionality provided by the present invention. This alternative mechanism operates with any SIW that can address a specific location in the MRF. Though multiple locations in the MRF could be provided for this purpose, there are other uses in specific implementations which may preclude this. For the purposes of describing this alternate RFI enabling mechanism, one location in the MRF is used, as shown for RFILSD  304  in FIG.  3 A. 
     To use the RFI enabling mechanism, the hardware decode logic is extended to generate the RFI enable signal not only when an XV RFI instruction is received but also whenever a load, store, or DSU instruction is received in the SP or PE instruction register which specifies the RFILSD address as the load Rt, store Rs, or DSU Rt or Rs operands. Prior to using this alternate RFI enabling mechanism, the RFI control registers are required to be set up specifying the initial registers to be used in a block load, store, or DSU operation. No start bit is used in this alternate RFI enabling mechanism as the starting address of the block sequence is stored in the port control registers. Upon receiving a load, store, or DSU instruction, which uses the RFILDS bits as an operand address, the RFI mode is enabled and each register operand address is substituted with the pre-setup port (operand) addresses by the RFI port logic as shown in the representative RFI logic of FIGS. 8,  9 , and  11 . RFI and non-RFI operations can be mixed when using the hardware of FIGS. 8 and 9. In fact, by using two contexts for the load, store, and DSU control registers, groups  0  and  1 , as shown in FIG. 9, then, RFI XV operations on a first block of data, RFI operations using RFILSD on a second block of data, and non-RFI operations can be mixed. It can be appreciated that by proper extension of an arithmetic port register operand address range, an arithmetic instruction could, by referencing the RFILSD address, cause RFI to be invoked for the arithmetic instruction execution. 
     RFI Instruction Execution 
     RFI operation is enabled through control information contained in instruction words. This control information is used to specify whether conventional register address selection fields (operand address fields contained in the instruction) are to be used or whether the RFI selection of registers is to be used. In the presently preferred embodiment, the control information in the instruction, indirect VLIW XV instruction bits  21  and  20   202  of FIG. 2, indirectly specifies a control register or set of registers which are to be used to control RFI operation. One or more of these control register groups are available for RFI control as seen in FIG.  5 . The XV RFI instruction both enables RFI mode and selects a control register group for controlling the RFI operation. The group of RFI control registers  510 - 580  shown in FIG. 5 allow all of the register ports to be RFI controlled, meaning that every execution unit may operate in RFI mode concurrently. 
     It is noted that the ManArray processor finishes the execution phase of its pipeline with a write back to the register file. This approach allows the next cycle after the write-back cycle to use the results in the next operation. By judicious programming, chaining of vector operations is then inherent in the architecture. No separate bypass paths need be provided in the execution units to support chaining. 
     A discussion concerning an exemplary use of RFI in accordance with the present invention is now presented to illustrate several advantageous aspects of the invention. Assuming an increment value of 1, RFBS value (M) a power of 2, starting register R 2 , the register addresses alternate between two registers, an even register R 2  and its corresponding odd register (address+1) R 3 . For RFBS=4, the register addresses cycle among 4 values with an increment of 1. The following table shows some address sequences. 
     
       
         
               
               
               
               
             
           
               
                   
               
               
                   
                   
                 Register 
                   
               
               
                 Start 
                   
                 File 
               
               
                 Register 
                 Increment 
                 Block Size 
                 Sequence 
               
               
                   
               
             
             
               
                 R2 
                 1 
                 2 
                 R2, R3, R2, R3, . . . 
               
               
                 R2 
                 1 
                 4 
                 R2, R3, R0, R1, R2, . . . 
               
               
                 R5 
                 1 
                 4 
                 R5, R6, R7, R4, R5, . . . 
               
               
                 R5 
                 2 
                 4 
                 R5, R7, R5, R7 . . . 
               
               
                 R5 
                 2 
                 8 
                 R5, R7, R1, R3, R5 . . . 
               
               
                 R6 
                 2 
                 8 
                 R6, R0, R2, R4, R6, . . . 
               
               
                 R0 
                 1 
                 1 
                 R0, R1, R2, R3, . . . , R31, R0, R1 . . . 
               
               
                   
                   
                   
                 for non-Load/Store units 
               
               
                   
                   
                   
                 R0, R1, R2, R3, . . . R63 (cycles ALL 
               
               
                   
                   
                   
                 registers) for Load/Store units 
               
               
                   
               
             
          
         
       
     
     Assume it is desired to calculate a simple matrix-vector multiplication on a 4-PE SIMD VLIW ManArray processor such as processor  100  of FIG.  1 A. Further assume that the following instruction types are available: 
     
       
         
               
               
             
           
               
                   
               
               
                 Pseudo 
                   
               
               
                 Instructions 
                 Operation 
               
               
                   
               
             
             
               
                 LDB R N , P J + 
                 Load Broadcast: Loads from a memory location speci- 
               
               
                   
                 fied by the address register P J  in SP memory and stores 
               
               
                   
                 the value into register R N  of each PE (all receive the 
               
               
                   
                 same value. P J  is post-incremented by 1. 
               
               
                 MAC R T , R X , R Y   
                 Multiply-Accumulate: All PEs execute in SIMD 
               
               
                   
                 fashion the operation R T  = R T  + (R X  * R Y ) 
               
               
                 ST R S , P J + 
                 Store: All PEs store source register R S  to local PE 
               
               
                   
                 memory location specified by P J . P J  is post- 
               
               
                   
                 incremented by 1. 
               
               
                 REP N, M 
                 Execute the following N instruction M times 
               
               
                   
               
             
          
         
       
     
     Also, assume that a 4×4 matrix A is distributed to the 4 PEs, PE 0 , PE 1 , PE 2  and PE 3 , such that each PE contains a row of the matrix in registers R 4 , R 5 , R 6  and R 7  (PE 0  gets row  0 , PE 1  gets row  1 , etc.) as shown in the following table. 
     
       
         
               
               
               
               
               
             
           
               
                   
               
               
                 Register → 
                 R4 
                 R5 
                 R6 
                 R7 
               
               
                   
               
             
             
               
                 PE0 
                 a00 
                 a01 
                 a02 
                 a03 
               
               
                 PE1 
                 a10 
                 a11 
                 a12 
                 a13 
               
               
                 PE2 
                 a20 
                 a21 
                 a22 
                 a23 
               
               
                 PE3 
                 a30 
                 a31 
                 a32 
                 a33 
               
               
                   
               
             
          
         
       
     
     If a sequence of 4×1 vectors are read in from main (SP) memory  105 , multiplied by the matrix and the results stored in local PE memory  123 ,  123 ′,  123 ″ and  123 ′″, an appropriate sequential algorithm might appear as follows if it is assumed R 2  is zero initially: 
     
       
         
               
               
             
           
               
                   
               
             
             
               
                 LDB R0, P0+ 
                 ;load first element of input vector, x0 
               
               
                 MAC R2,R4,R0 
                 ;accumulate product: a i 0 * x0 (I is row index and 
               
               
                   
                 PE ID) 
               
               
                 LDB R0, P0+ 
                 ;load second element of input vector, x1 
               
               
                 MAC R2,R5,R0 
                 ; accumulate product: a i 1 * x1 
               
               
                 LDB R0, P0+ 
                 ;load third element ofinput vector, x2 
               
               
                 MAC R2,R6,R0 
                 ; accumulate product: a i 2 * x2 
               
               
                 LDB R0, P0+ 
                 ;load last element of input vector, x3 
               
               
                 MAC R2,R7,R0 
                 ; accumulate product: a i 3 * x3 
               
               
                 ST R2, P1+ 
                 ;store results: each local memory gets an element 
               
               
                   
                 of ;output vector 
               
               
                   
               
             
          
         
       
     
     Performing this algorithm with VLIW instructions yields: 
     
       
         
               
               
               
               
             
           
               
                   
               
               
                 VLIW 
                 SIW 
                 SIW 
                 Execute Action 
               
               
                   
               
             
             
               
                   
                 LDB R0, P0+ 
                   
                 ;Load 
               
               
                 1 
                 LDB R0, P0+ 
                 MAC R2, R4, R0 
                 ;Load PEs and MAC x0 * 
               
               
                   
                   
                   
                 a[i][0] 
               
               
                 2 
                 LDB R0, P0+ 
                 MAC R2, R5, R0 
                 ;Load PEs and MAC x1 * 
               
               
                   
                   
                   
                 a[i][1] 
               
               
                 3 
                 LDB R0, P0+ 
                 MAC R2, R6, R0 
                 ;Load PEs and MAC x2 * 
               
               
                   
                   
                   
                 a[i][2] 
               
               
                 4 
                 LDB R0, P0+ 
                 MAC R2, R7, R0 
                 ;Load PEs and MAC x3 * 
               
               
                   
                   
                   
                 a[i][3] 
               
               
                   
                 ST R2,P1+ 
                   
                 ;All PEs store Store result 
               
               
                   
               
             
          
         
       
     
     This requires 4 VLIW-type instructions, plus a single load LDB and a single store ST instruction, even though the only difference between these VLIW instructions is the second register specification of the MAC instruction. 
     Now if the example is performed using RFI, the process is as follows: Assume R 2  and R 0  are both initialized to zero and register file indexing is used with the following parameters associated with the VLIW indirectly executed by an XV instruction: 
     
       
         
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Execution Unit Register Port 
                 Increment 
                 RFBS 
               
               
                   
                   
               
             
             
               
                   
                 Load Write Port 
                 0 
                 1 
               
               
                   
                 MAU Rx Readport 
                 1 
                 4 
               
               
                   
                   
               
             
          
         
       
     
     Now the code can be written in compact VLIW form where the second register RFI sequence starts with R 7 →R 4 →R 5 →R 6 →R 7 , etc. 
     
       
         
               
               
               
               
             
           
               
                   
               
             
             
               
                 VLIW 
                 LD RFIC, P1,ctrl 
                   
                 ;Initialize RFI control for 
               
               
                   
                   
                   
                 MAU reg port 
               
               
                   
                 REP 1, 5 
                   
                 ;Repeat 1 instruction 5 
               
               
                   
                   
                   
                 times 
               
               
                 1 
                 LDB R0, P0+ 
                 MAC R2, R7, R0 
                 ;Load and MAC: first 
               
               
                   
                   
                   
                 ;MAC is 0 and last 
               
               
                   
                   
                   
                 ;load reads into next 
               
               
                   
                   
                   
                 ;vector (or garbage) 
               
               
                   
                 ST 
                 R2, P1+ 
                 ;Store results 
               
               
                   
               
             
          
         
       
     
     The net effect is to reduce 9 instructions to 4 instructions. The fact that fewer VLIWs are used, reduces the number of iVLIWs executed and also the number of VLIWs that must be loaded in the ManArray architecture. These savings are indirect, but not insignificant since the VLIW memory (VIM) represents an expensive on chip resource. The RFI operation reduces the amount of VLIW memory needed, thus allowing for less-expensive chips. 
     While the present invention has been disclosed in the context of various aspects of presently preferred embodiments, it will be recognized that the invention may be suitably applied to other environments and applications consistent with the claims which follow.