Abstract:
A novel fully differential analog comparator having cascaded gain stages powered by two buses. The two buses are powered by a current source and a variable gain current mirror responsive to the current source. The current source and the current mirror isolate the buses from external power and ground to achieve high power supply noise immunity. True and complementary outputs of the comparator are provided having an adjustable output common mode voltage to optimize the driving of subsequent logic gates responsive to the comparator.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a companion application of Ser. No. 267,957, having a common assignee and filed simultaneously herewith, titled &#34;Analog Comparator&#34;, by J. P. Hein and T. R. Viswanathan. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to an integrated circuit technique for producing an accurate high-speed analog comparator with low power consumption. 
     2. Description of the Prior Art 
     An analog comparator is a basic functional unit utilized in analog circuit design, as, for example, in analog-to-digital converters (ADCs). The relative performance of analog comparators is measured by their specifications, such as input offset voltage, offset current, propagation delay, skew, power consumption, etc. In some applications, the input offset voltage and offset current specification can be relaxed (traded off) when other performance criteria are critical. For example, in optical and digital data receivers or in high speed medium resolution ADCs having embedded analog comparators, e.g., those used in video applications (eight or nine bit resolution with ten megahertz conversion rates), low propagation delay through the analog comparators is the most important criteria. Alternatively, in low speed medium resolution ADCs having embedded analog comparators, e.g., ADCs used in telephone (voice) applications where many thousands thereof are employed in channel banks and line cards of switching systems (eight to twelve bits resolution, eight kilohertz conversion rates), the power consumption of the analog comparators is of primary importance. Hence, it is desirable to have a single analog comparator design easily adaptable for any application. 
     SUMMARY OF THE INVENTION 
     We have invented a fully differential analog comparator having substantially identical propagation delay from either one of two inputs. The comparator has very low sensitivity to power supply noise and the gain of the comparator can be scaled as needed. Additionally, the comparator can be adapted such that the average differential output voltage (output common mode voltage) can be adjusted for optimally driving subsequent amplifier stages, such as digital inverters. Further, the average differential input voltage (input common mode voltage) can be compensated for to provide precise control of the output common mode voltage with varying input common mode voltage 
     These and other advantages are obtained generally by having a first and second plurality of cascaded gain stages powered by first and second buses, input to the first plurality of cascaded gain stages coupling to a first voltage input to the comparator and input to the second plurality of cascaded gain stages coupling to a second voltage input to the comparator; a first current source coupling to the first bus; a second current source coupling to the second bus and providing substantially the same current as the first current source; and at least one digital inverter responsive to at least one of the outputs of the first and second plurality of cascaded gain stages. Each of the cascaded gain stages comprises two transistors of differing polarity, each transistor having two output terminals and an input terminal, the input terminals of the two transistors coupling together to form the input to the gain stage, two corresponding output terminals from the two transistors coupling together to form the output of the gain stage, and the remaining output terminals of the two transistors from the corresponding first and second power terminals of the gain stage. 
     The output common mode voltage is adjusted to a predetermined voltage by adapting the second current source to be a current mirror. The current mirror is a unity gain current mirror, further adapted to vary its gain in response to a predetermined voltage and the output common mode voltage from the output of the first and second plurality of gain stages. This arrangement forces the output common mode voltage to approximate that of the predetermined voltage. 
     Further, to compensate for the input common mode voltage forcing the output common mode voltage to deviate from the predetermined voltage, a third transistor network is disposed between the first current source and the current mirror. The third transistor network is responsive to either another predetermined voltage source, having a voltage substantially that of the input common mode voltage, or to the first and second input voltages of the comparator. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The foregoing features of this invention, as well as the invention itself, may be more fully understood from the following detailed description of the drawings, in which: 
     FIG. 1 is an analog comparator of the prior art; 
     FIG. 2 is a schematic of the analog comparator according to the invention; and 
     FIGS. 3, 4 and 5 are improvements to the analog comparator of FIG. 2. 
    
    
     DETAILED DESCRIPTION 
     In FIG. 1, a schematic of analog comparator 10 is shown as known in the prior art. A differential input stage 11 is formed by a differential input amplifier having field-effect transistors (FETs) 12, 13 and current source 14 driving a conventional current mirror of FETs 15, 16. The output of stage 11 drives an amplifier 17 formed by FET 18 and current source 19 as a load for FET 18. Output of the comparator 10 is taken from the amplifier 17. This design suffers from a propagation delay skew, i.e., the propagation delay from the comparator input going from greater than the voltage reference input V ref  to less than V ref  is different from going from less than V ref  to greater than V ref . For the most part, this propagating delay skew is a result of the asymmetric design of the differential input stage 11. The most notable asymmetry being the path from the comparator input through FET 12, through the current mirror of FETs 15, 16 to amplifier 17. In contrast, the path from V ref  to the amplifier 17 is only through FET 13. Overall propagation delay through the comparator 10 is high due to the number of FETs a signal propagates through to reach the output of comparator 10 from the comparator input. Further, this structure suffers from poor noise immunity from the V DD  power supply. Still further, the overall gain of the comparator 10 will be limited when short-channel FETs are used. Short channel FETs suffer from reduced gain due to increased output conductance, which increases the loading of all nodes in the stage 11 and in the amplifier 17, reducing the overall gain. 
     A novel, fully-differential analog comparator 20 is shown schematically in FIG. 2 for integration into a common substrate. Two strings 21, 21&#39; of cascaded gain stages 22 provide a predetermined amount of voltage gain for corresponding inputs V+ and V- of comparator 20. Output from each string 21, 21&#39; couples to corresponding node 35, 35&#39;. Each string 21, 21&#39; has the same number of stages 22, and, typically, no more than one or two stages 22 in each string 21, 21&#39; are necessary. Each gain stage 22 resembles a conventional CMOS inverter, having an input terminal 23, an output terminal 24 and two power supply terminals 25, 26. In an exemplary stage 22, a P-channel FET 30 and an N-channel FET 31 are shown having common gates coupling to the input terminal 23 and common drains coupling to output terminal 24. Although shown here as P- and N- channel FETs, it is understood that the P- and N- channel FETs can be interchanged with a corresponding change in power supply polarity. The source of FET 30 couples to power terminal 25, while the source of FET 31 couples to power terminal 26. The ratio of the sizes of FET 30 to FET 31 will be discussed in more detail below, but it is sufficient to state here that the conventional sizing ratio of FET 30 to FET 31, being approximately two- or three-to-one, will produce a comparator 20 having substantially zero propagation delay skew. 
     The power terminals 25, 26, of cascaded gain stages 22 couple to corresponding buses 32, 33. Buses 32, 33 are powered by current mirrors 40, 50, respectively. Mirrors 40, 50 are correspondingly powered by V DD , the most positive power supply, and V SS , the most negative power supply, which is typically at ground or zero volts. The current mirrors 40, 50 serve to isolate the buses 32, 33 from V DD  and V SS , reducing the susceptibility of the comparator 20 to electrical noise on the power supplies V DD , V SS . 
     Current mirror 40 is shown here as a conventional Widlar current mirror with multiple outputs, but it is understood that other types of current mirrors, such as Wilson or compound current mirrors, may be used. FET 42 of mirror 40 couples to a current source 44, setting the amount supplied by mirror 40 and the overall power current consumption of the comparator 20. Typical current supplied by the current source 44 is 100 microamperes to 1 milliamperes depending on output load capacitance on nodes 35, 35&#39; and the desired speed of the comparator 20. FETs 48, 46, 47 of source 40 are sized that the currents flowing out of the FETs&#39; 48, 46, 47 are substantially the same. FET 48 supplies current to bus 32. 
     Current mirror 50, shown here as a compound current mirror formed by FETs 51, 52, 53, 54, 55, accepts current from the outputs of the current mirror 40 into control current input nodes 56 of the mirror 50. The resulting mirrored current is inputed from bus 33 into serially connected FETs 54, 55 through mirrored current input node 57. Control current output from control current output nodes 58 of the mirror 50 passes through FETs 61, 62 to the most negative power supply, V SS . As will be discussed in greater detail below, FETs 61, 62 are operated in the triode, or ohmic, region and have substantially the same size. Likewise, mirrored current output from mirrored current output node 59 of mirror 50 passes through paralleled FETs 65, 66 to V SS . Again, as will be discussed in greater detail below, FETs 65, 66 operate in the triode, or ohmic, region and have substantially the same size. As stated above, the current mirror 50 is a compound current mirror for the accurate mirroring of current and is preferably a unity gain current mirror with FETs 51, 53, 54, 55 having substantially the same size. Operation of current mirror 50 is described in detail in U.S. Pat. No. 4,477,782,  issued on Oct. 16, 1984 to E. J. Swanson and assigned to the assignee of the present application. However, for purposes here, operation of the current mirror 50 is described briefly herein. FET 52 of the mirror 50 establishes a stable gate voltage for FETs 51 and 54 and is typically one-quarter or less the sizes of FETs 51, 53, 54, 55. Further, FET 52 has a sufficiently high threshold voltage to ensure that FETs 51, 53, and correspondingly, FETs 54, 55, are saturated. FET 51 equalizes the drain-to-source voltages on FET 55 and FET 53, substantially eliminating offset currents in the mirror 50. The serially coupled FETs 54, 55 provide a high impedance current sink at node 57 for current from bus 33. Although a simpler current mirror can be used for current mirror 50, such as a Widlar mirror, the more precise the current is mirrored and the higher the impedance of the mirrored current input node 57 is, the better the accuracy of the comparator 20. Therefore, a suitably adapted Wilson current mirror could be used as mirror 50. 
     Voltage source 68, coupling to the common gate of FETs 61, 62, is a reference voltage for the average voltage on the output nodes 35, 35&#39; of the strings 21, 21&#39; to achieve, and is referred to here as the output common mode voltage level set. The desirability of adjusting the output common mode voltage strings 21, 21&#39; will be discussed below, but for purposes here, the interface of the strings 21, 21&#39; to a load can be optimized for the characteristics of the load, e.g., digital inverter stages coupled to nodes 35, 35&#39;. Similarly, the paralleled FETs 65, 66, responsive to the voltages on the output nodes 35, 35&#39; of strings 21, 22 are combined so that the paralleled resistances of the FETs 65, 66 correspond to the average of the voltages on the output nodes 35, 35&#39;, the output common mode voltage. Put another way, the paralleled resistances of FETs 65, 66 represent the output common mode voltage of the cascaded stages 22 of strings 21, 21&#39;. For the purposes of this discussion, it is assumed that the input voltages to comparator 20 (V+, V-) are substantially the same, the threshold &#34;trip point&#34; of the comparator 20. This corresponds to a zero voltage differential input to inputs V+, V- and is useful for examining the biasing and operation of comparator 20. It is understood however, that the following also applies when the voltage of inputs V+, V- are not substantially the same. It is desired that the output common mode voltage of the strings 21, 21&#39; be substantially the same as the voltage from source 68. To do so, the resistances of FETs 65, 66 and 61, 62 deviate the current gain of the mirror 50 from unity when the output common mode voltage is not substantially the same as the voltage of source 68. As such, the resistances of FETs 61, 62 are substantially the same and are invariant since the voltage of source 68, for purposes here, is invariant. However, the combined resistances of FETs 65, 66 vary inversely proportionally with the voltages on the output nodes 35, 35&#39; of the strings 21, 21&#39;, which are dependent on the voltage on the bus 33, hence dependent on the current flowing through the current mirror 50. Since the current through the control current input nodes 56 and through the control current output nodes 58 does not vary, for the comparator 20 to be in equilibrium, there must be substantially equal current flow in the mirrored current and the control current, i.e., unity current gain of the mirror 50. For unity current gain, the combined resistances of the FETs 65, 66 must be substantially the same as the resistances of FETs 61, 62. Hence the average of the voltages on the gates of FETs 65, 66 must be substantially the same as the voltage from voltage source 68, i.e., the output common mode voltage from the cascaded gain stages 22 is substantially the same as the voltage from source 68. 
     The output nodes 35, 35&#39; couple to corresponding buffers 45, operating as a conventional CMOS digital inverter. Although only one buffer 45 is shown corresponding to each string 21, 21&#39;, it is understood that multiple, cascaded buffers 45 can be used. Output terminals 24 of buffers 45 are the outputs for the comparator 20, OUTPUT and OUTPUT&#39;. Buffers 45 are similar in structure to gain stage 22 but with as small a device as possible to reduce capacitive loading of the strings 21, 21&#39;. Power supply terminals 25, 26 of buffers 45 couple to power sources V DD  and V SS  instead of buses 32, 33. As will be discussed in more detail below, the sizing of the FETs in each buffer 45, corresponding to FETs 30, 31 in stage 22, is typically two- or three-to-one, respectively, for minimum propagation delay skew and a threshold voltage of substantially one-half the voltage difference between V DD  and V SS . 
     The ability to adjust the output common mode voltage of strings 21, 21&#39; can be used advantageously by recognizing that optimal operation of the comparator 20 requires that, when the voltage on V+ is approximately the same as the voltage on V-, the voltage on nodes 35, 35&#39; should be approximately the threshold voltages of buffers 45. The threshold voltage of the buffer 45 is the input voltage at which the output of the buffer 45 transitions from V DD  to V SS , and vice versa. This minimizes propagation delay skew through comparator 20. Therefore, the output common mode voltage of strings 21, 21&#39; should be approximately the threshold voltage of buffers 45. This is accomplished by having the voltage of voltage source 68 be substantially that of the threshold voltage of buffers 45. Referring temporarily to FIG. 3, source 68 (FIG. 2) is shown having a buffer 75, substantially similar to the buffers 45 in FIG. 2 and preferably integrated on the same substrate therewith, with input terminal 23 coupling to output terminal 24 and with power terminals 25, 26 coupling to corresponding power sources V DD  and V SS . Having buffer 75 operating with input 23 coupled to output 24, the voltage on input terminal 23 is substantially the threshold voltage of the buffer 75. Hence the voltage of voltage source 68 (FIG. 2) is substantially the threshold voltage of buffers 45 (FIG. 2). By having buffer 75 on the same chip as buffers 45 (FIG. 2), variations in threshold voltage of buffers 45 due to temperature and processing variations will be compensated for by variations in threshold voltage of buffer 75. 
     Returning to FIG. 2, it is recognized that due to the finite output resistances of FETs, the output common mode voltage of strings 21, 21&#39; will not precisely match that of voltage source 68 when inputs V+ and V- are substantially the same, i.e., when the input voltages are at the comparator threshold. As noted above, when the V+ and V- inputs are substantially the same, by virtue of the disclosed invention, the output common mode voltage of nodes 35, 35&#39; should be substantially equal to the voltage of source 68. However, the voltage on bus 32 is different from the voltage on the drains of FETs 46, 47, hence the voltage across FET 48 is different from the voltage across FETs 46, 47. This results in differing current flow through FETs 46, 47 from that through FET 48 due to the voltage across FETs 46, 47 being different from the voltage across FET 48 with the inherent output resistances of the FETs 46, 47, 48. Furthermore, the voltage on bus 32 varies with the average voltage of the inputs V+, V-, referred to here as the input common mode voltage. To compensate for the different current flow, the gain of the current mirror must decrease. This is accomplished by the output common mode voltage changing from the desired voltage until equilibrium is reached. To equalize the currents through FETs 46, 47, 48, and thus make the output common mode voltage on nodes 35, 35&#39; more closely equal to the voltage of voltage source 68, at breakpoints 70, 70&#39; and 71, 71&#39;, the circuit in FIG. 4 is substituted. In FIG. 4, two FETs 76, 77 have common gates coupling to a voltage source 78, referred to here as the input common mode voltage set. The FETs 76, 77, are each sized to be substantially 2N times the size of FET 30 in a gain stage 22 (FIG. 2), N being the number of gain stages 22 in a string 21, 21&#39; and disposed on the same substrate as FET 30. This assures that the voltage across FETs 46, 47 is substantially the same as the voltage across FET 48 (FIG. 2) when the input common mode voltage of inputs V+, V- of comparator 20 (FIG. 2) is known. However, if the input common mode voltage is not known, then the circuit in FIG. 5 can be used to derive the input common mode voltage from inputs V+, V- by having FETs 79, 80, 81, 82 in the arrangement shown disposed between breakpoints 70, 70&#39; and 71, 71&#39; in FIG. 2 and preferably integrated onto a substrate common with the circuitry in FIG. 2. The sizes of FETs 79, 80, 81, 82 are each N times the size of FET 30 (FIG. 2), N being the number of stages 22 in a string 21, 21&#39;. This will assure that the voltage across FETs 46, 47 is substantially the same as the voltage across FET 48 with varying input common mode voltage, thus ensuring that the output common mode voltage on nodes 35, 35&#39; remains substantially the same as the voltage from voltage source 68. 
     As stated above, the sizing of the FETs 30, 31 in stages 22 and, correspondingly, in buffers 45 and 75 (FIG. 3), are an exemplary two- or three-to-one to yield a threshold voltage approximately one-half the voltage between power supply terminals 25, 26 and for minimum propagation delay skew. However, it is understood that the sizing of the FETs 30, 31 can be one-to-one for minimum propagation delay through stages 22, buffers 45, or any combination thereof. 
     Having described the preferred embodiment of this invention, it will now be apparent to one of skill in the art that other embodiments incorporating the concepts disclosed herein may be used. It is felt, therefore, that this invention should not be limited to the disclosed embodiment, but rather should be limited only by the spirit and scope of the appended claims.