Abstract:
A switching boost regulator, including auxiliary circuitry having an auxiliary switch and inductor connected to operate the regulator in a zero-voltage transition mode, achieves substantial efficiency improvement by limiting losses in the auxiliary circuitry dedicated to achieving zero-voltage transition operation. Loss reduction circuitry included with the auxiliary circuitry cooperatively operates to limit turn-on and conduction losses and to suppress ringing of the components of the auxiliary circuit.

Description:
FIELD OF THE INVENTION 
     This invention relates to switching mode regulators and in particular highly efficient switching mode regulators in which the losses of switching components are minimized. 
     BACKGROUND OF THE INVENTION 
     Switching mode regulators have wide application as low loss power supplies. One particular application is at the front end of power rectifiers where they are controlled, by pulse width modulation techniques, to provide enhanced power factor at the input AC power line feed. Regulators are chosen which are highly efficient so that the overall power processing system is highly efficient. Accordingly switching regulators are designed using controlled wave forms and careful timing to minimize losses at the switching transitions of the various non-linear switching components. These regulators are embodied in circuit topologies that emphasize near zero or zero-voltage switching. In zero voltage switching the conductivity transition to the conducting state of the active power switch occurs when the voltage of the power switch is at a substantially zero level. In some arrangements other switching components of the circuit may be controlled to switch at a zero or near zero voltage. 
     A particular example of such a circuit is a boost regulator designed to achieve zero or near zero voltage switching. Such a circuit may indeed achieve the low loss or lossless switching criteria for at least the active power switch but the very circuitry added for achieving near zero or zero-voltage switching induces other transient phenomena that reduces the efficiency gains of zero voltage switching and further induces undesirable stress on other circuit components of the power regulator. 
     SUMMARY OF THE INVENTION 
     A switching boost regulator, including auxiliary circuitry having an auxiliary switch and inductor connected to operate the regulator in a near zero or zero-voltage switching mode (herein after designated ZVS), achieves substantial efficiency improvement by limiting losses in the auxiliary circuitry dedicated to achieving ZVS operation. Loss reduction circuitry included with the auxiliary circuitry cooperatively operates to limit turn-on and conduction losses and to suppress ringing of the components of the auxiliary circuit. 
     The loss reduction circuitry includes circuitry for limiting conductive and switching losses in passive switching devices of the auxiliary circuit used for clamping and rectification. Circuitry for limiting ringing and peak inverse voltages of the auxiliary switch include circuitry for absorption of transient energy of a clamping circuit and circuitry for dissipating energy stored in magnetic storage elements included in the auxiliary circuit. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic of a conventional switching boost type voltage regulator; 
     FIG. 2 is a schematic of a switching boost type voltage regulator with reduced loss ZVS circuitry; 
     FIG. 3 is a graph of a plurality of operating waveforms of the switching boost regulator of FIG. 2; 
     FIG. 4 is a schematic of another switching boost type voltage regulator with reduced loss ZVS circuitry. 
    
    
     DETAILED DESCRIPTION 
     A typical prior art boost switching voltage regulator, shown in FIG. 1, is operative to convert an input DC voltage, such as V g , supplied at the input terminal connected to inductor L 1  to a DC output voltage at a higher DC voltage level at the output terminal V out . This voltage level transformation is accomplished by periodically biasing the power switch Q 1  into a conducting state to establish a current flow through the inductor L 1 . The power switch Q 1  is periodically biased non conducting, following each periodic conducting interval, and the inertial current characteristics of the inductor L 1  at this time biases the rectifying diode D 1  conducting to couple the stored energy in the inductor L 1  to the output terminal at a higher DC voltage level than the voltage level of the input DC voltage V g . The boost regulator in the form shown in FIG. 1 experiences significant switching loss in the power switch Q 1  and the rectifying diode D 1 . In many applications this reduced efficiency is not acceptable. 
     A boost type switching voltage regulator can be designed to employ ZVS switching techniques. This significantly increases efficiency by operating both passive and active switching components to change their respective conductive states during a transition period in which the switching component voltage is held essentially to a zero value. 
     In the boost regulator shown in the FIG. 2 an auxiliary network including the FET auxiliary switch Q 2  and inductor L 2  is operative to enable ZVS switching of the power switch Q 1  and is further operative to absorb energy associated with the switching of the rectifying diode D 1 . The diode energy induced by the switching of the diode D 1 , and absorbed by the network, is that energy associated with the current flow occurring during its reverse recovery when the diode transitions from a conducting to a blocking mode. The power switch Q 1  has an energy loss due to non-zero voltage/current dissipation and is partly due to the charge stored by its inherent capacitance C Q1 . Application of this ZVS network circuitry typically reduces these losses occurring in the primary power train by about one-half. 
     The auxiliary network of the ZVS regulator, comprising the auxiliary switch Q 2 , and the inductor L 2  suffers considerable turn-on and conduction loss, on its own behalf. This loss detracts from the energy savings achieved in the main power train circuitry. Further losses are incurred in the auxiliary network by ringing of the voltage of the auxiliary switch Q 2  occurring at switching transitions. This ringing adversely affects the EMI performance of the overall circuit. 
     A modification of the auxiliary network to improve the efficiency of the ZVS circuitry includes addition of an inductor T 1  having two windings, T W1  and T W2 , inductively coupled and further with the winding T W1  electrically connected in series with the winding T W2 . Winding T W1  is electrically connected in series with the auxiliary switch Q 2  in order to significantly reduce the current level switched by the auxiliary switch Q 2 . The second winding T W2  is connected to the output V out  by a clamping diode D 2 . The reverse recovery of this diode D 2  induces added significant switching and conduction losses into the regulator. 
     Further loss reduction circuitry is added to the auxiliary network in order to increase the overall efficiency of the regulator by reducing the currents conducted by the auxiliary network to a level significantly less than the output current of the regulator and by eliminating or at least significantly reducing reverse recovery losses of diodes in the regulator. Additional circuitry is also included in the auxiliary network to absorb losses and reduce ringing induced by the switching action of the auxiliary network components. 
     In the basic operation of the regulator of FIG. 2 current is initially flowing from the voltage source V g  through the inductor L 1  and diode D 1  to the output terminal V out  before either of the active switches, Q 1  or Q 2 , is biased conducting. The first switch turned on in each cycle of operation is the auxiliary switch Q 2 . The switch Q 2  is biased conducting, at timing mark T 0 , by a pulse identified as waveform V GS2  in FIG. 3, just prior to turn-on of the power switch Q 1 . The conducting interval of auxiliary switch Q 2  is coincident with the duration of the driving pulse voltage V GS2  which determines the conducting interval of switch Q 2 . The voltage pulse driving power switch Q 1 , as shown by waveform V GS2  in FIG. 3, has a duration extending from T 1  to T 3 . The corresponding duration of conductivity of the auxiliary switch Q 2  is, as shown, timed to fully cover the turn-on transition interval of the power switch Q 1 . 
     The conduction of the auxiliary switch Q 2  causes a first current to build up in the inductor L 2 . This first current is shown by the waveform I LR  shown in the FIG. 3 at the timing mark T 0 . The inductively coupled windings T W1  and T W2 , of the magnetic device T 1 , cause a second current proportional to the first current to flow in the forward biased diode D 2 . When the sum of the first and second currents (shown by waveforms I LR  and I TS2  in FIG. 3) equals or exceeds the input current the voltage at the node N 1  decays to zero. This enables the full discharge of the inherent capacitance C R  of the power switch Q 1 . The diode D 1  is reverse biased and the reverse recovery energy of the diode D 1  is absorbed by the inductor L 2 . With the voltage at node N 1  at essentially zero the power switch Q 1  is biased conducting without switching loss. The auxiliary switch Q 2  is subsequently biased non-conducting at timing mark T 3 , shortly after the power switch Q 1  becomes conducting. With the auxiliary switch Q 2  non-conducting the energy stored in the inductor L 2  is returned to the output terminal V out . Its conduction path, to the terminal V out , includes the current flow through the diode D 3 , and also current flow via the inductive coupling provided by the winding T W1  and passing through the diode D 2 . The subsequent biasing of the power switch Q 1 , to a non-conducting state, at the timing mark T 5 , is in response to regulation control circuitry to regulate the voltage at the output. 
     The voltage across the auxiliary switch Q 2  must be limited to its peak voltage rating. Clamping of this voltage is provided by the diode D 3  connecting the auxiliary switch drain to the output V out . The voltage of auxiliary switch Q 2  is hence clamped to the output voltage. The current in the diode D 3  must be reduced to substantially zero when the auxiliary switch Q 2  is biased non-conducting, to avoid efficiency reducing reverse-recovery losses in the diode D 3 . The resistor R 1  connected in series with the diode D 3  absorbs these reverse recovery losses. The value of the resistor R 1 , connected in series with the diode D 3 , is idealy of a resistance with a value roughly equal to one-half of the square root of L 2  /C, where C is the total capacitance appearing between the drain and source terminals of the auxiliary switch Q 2 . A practical value of resistor R 1  is of the order of a hundred ohms. 
     The resetting of the magnetizing inductance of the magnetic device T 1  places voltage stress on the diode D 2 . The reset energy is controlled with a dissipative network, comprising the resistor R 2  and the diode D 4 , for dissipating the energy of the magnetizing inductance This energy is shown by the current waveform I TS2  shown in FIG. 3 between the timing marks T 3  and T 7 . A practical value of resistor R 2  is of the order of several kilohms. 
     The energy associated with the reverse recovery of the diode D 3 , when the auxiliary switch Q 2  is turned on, is absorbed by a sub-network, including the diode D 5  connected in parallel with the resistor R 3 . This sub-network is connected in series with the auxiliary switch Q 2 . This sub-network absorbs the reverse recovery energy of the diode D 3  and further eliminates the tendency of the ZVS circuitry to ring following turn off of the auxiliary switch Q 2 . A practical value of the resistor R 3  is of the order of several hundreds of ohms. 
     The operation of the circuit may be readily understood by considering its operation as a sequence of seven distinct operational modes in combination with an examination of the wave forms of FIG. 3 associated with the circuit of FIG. 2. All the waveforms are keyed to the common timing marks T x  where x is designated 0 through 8. Each waveform in FIG. 2 is designated as V for voltage and I for current and I and V are accompanied by subscripts identifying the component having that particular waveform characteristic. Waveforms V GS1  and V GS2  represent the voltage pulses applied to the power switch Q 1  and the auxiliary switch Q 2  respectively. I LR , I TS1  and I TS2  are the current waveforms of current through inductor L 2  and winding T W1  and winding T W2 , respectively. Voltage waveform V DS1  is the voltage across the drain-source electrodes of power switch Q 1 . The voltage waveform V D2  is the the voltage across the drain-source electrodes of the auxiliary switch Q 2 . The voltage waveform V D2  is the voltage across the diode D 2 . Voltage waveform V T  is the voltage occurring across the winding T W1 . The current through diode D 3  is shown by waveform I D3 . These waveforms when taken in connection with the following description will enable those skilled in the art to understand the operation of the circuit of FIG. 2. 
     The initial operating conditions, prior to the timing mark T 0 , are that the power switch Q 1  and the auxiliary switch Q 2  are both non conducting. Power supplied by energy stored in the circuit is being transmitted to the output through the dioded D 1 . 
     The initial operating stage encompasses the time interval between the timing marks T 0  and T 1 . The auxiliary switch Q 2  turns on at timing mark T 0  and in response the current flow I L2  through the inductor L 2  begins to increase linearly. The output current I D1  continues to flow in the output diode D 1  and operates to clamp the the voltage across the coupled winding of the inductive component T 1  to a zero voltage. The current, shown by waveform I L2 , flowing through the inductor L 2  continues to increase linearly. This same current appears in the coupled winding t W1  of the magnetic device T 1 . This rate of this increase is scaled in response to the winding ratio N:1 of the coupled windings of the magnetic device T 1 . The current flow in the diode D 1  decreases at the same rate as the sum of currents through the two windings of the magnetic device T 1  increases. At the timing mark T 1  the sum of the currents flowing through the windings of the magnetic device T 1  becomes equal to the magnitude input current I IN  flowing through the inductor L 1 . Hence the diode D 1  turns off in a soft manner (i.e., with mild reverse recovery characteristics). 
     In the next operational stage, comprising the time interval between the timing marks T 1  and T 2 , the diode D 1  is reverse biased at the timing mark T 1 . The sum of the currents through the windings of the magnetic device T 1  continue to increase causing charge to be removed in a resonant manner from the capacitor C Q1  which is in parallel with the power switch Q 1  and which may comprise the inherent capacitance or an external capacitance or a combination of both. The energy stored on this capacitor is eventually transferred to the output. With the diode D 1  nonconducting, a voltage is developed across the windings of the magnetic device T 1 . When the capacitance C Q1  is fully discharged the the power switch Q 1  is turned on with a zero-voltage transition from non-conducting to conducting state. 
     At the beginning of the next stage of operation, covered by the interval from timing mark T 2  to timing mark T 3 , the power switch Q 1  is conducting. The reflected output voltage appears across the winding T 1  of the magnetic device T 1 . This voltage resets the inductor L 2  whose current is linearly decreasing. The current through the inductor L 2  attains a zero value at the timing mark T 3  resulting in a zero current turn-off of the auxiliary switch Q 2 . At this time all the input current has been commutated to the power switch Q 1 . 
     During the subsequent operational stage encompassing a time interval between the timing marks T 3  and T 4 , the core of the magnetic device T 1  resets through a network comprising the diode D 4  and a resistor R 2 . This network is connected in parallel with the winding T 1  and provides a controlled reset which limits stresses appearing across the diode D 2 . 
     The power switch Q 1  is turned off at the timing mark T 4 . The voltage across power switch Q 1  then increases linearly as the input current charges the capacitance C Q1 . The inherent capacitance associated with the auxiliary switch Q 2  is charged during the time interval bracketed by the timing marks T 5  and T 6 . The charging current flows through the winding T W1  and the inductor L 2 , and a current is established in the winding T W2 . 
     As the voltage across the power switch Q 1  increases to the value of the output voltage, the voltage across the auxiliary switch Q 2  clamps to the value of the output voltage as the diode D 2  conducts. The inductor L 2  must be reset to avoid continued current flow through the diodes D 2  and D 4  during the non-conducting interval of the power switch Q 1 . A resistor R 1  is included to insure the reset of inductor L 2 . R 1  further drives the currents in the diodes D 4  and D 2  to zero to prevent a damaging reverse recovery when the auxiliary switch Q 2  is turned on to initiate the next switching cycle. By the occurrence of the timing mark T 6 , the voltage across the power switch Q 1  has increased to the value of the output voltage and the diode D 1  has been biased conducting and the inductor L 2  has been fully reset. 
     During the final interval between the timing marks T 6  and T 7  both the switches Q 1  and Q 2  are biased non-conducting and the input current is delivered to the load, via the diode D 1 . The subsequent switching cycle is initiated at timing mark T 8  when the auxiliary switch Q 2  is biased conducting. 
     The diode D 3  is an essential component for minimizing the negative effects caused by resonant interaction of the inherent capacitance of the diode D 2  and the inherent capacitance of the auxiliary switch Q 2  and the inductor L 2  at the turn-off of the power switch Q 2  (at the timing mark T 3 ). 
     The dashed lines appearing in the waveforms of FIG. 2 represent a different trajectory of waveforms that appear in the auxiliary network which do not incorporate the resistors R 1 , R 2  and R 3  and the diodes D 3  and D 5 . 
     An alternative version of the circuit of FIG. 2 is shown in the FIG. 4. While similar in operation to the circuit of FIG. 2 the semiconductor voltage breakdown devices D 6  and D 7  are used to achieve the objectives of reducing transients in the circuitry associated with the auxiliary switch Q 2 .