Abstract:
A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.

Description:
FIELD OF THE INVENTION 
     This invention relates generally to electronic systems having selective application of a clock signal to multiple circuits. More particularly, the invention relates to an integrated circuit design which conserves power by gating the generation of the clock signal when none of its multiple circuits requires a clock signal. 
     BACKGROUND OF THE INVENTION 
     Within each integrated circuit of a computer system are many circuits or functional blocks which all work together to perform operations required by the CPU. Each synchronous circuit within the integrated circuit is supplied a clock signal from either the external system clock or a clock internal to the integrated circuit. This clock signal is used to synchronize the operation of the integrated circuit and to toggle a response signal through the functional blocks, integrated circuit or system. For all synchronous functional blocks the clock is used as the timing reference to ensure that each synchronous functional block will execute its operations in the sequence that they are to occur. 
     For certain types of circuits, including CMOS circuits, power consumption is increased as a result of the circuit being exercised, e.g., by a clock signal. Typical digital systems employ multiple integrated circuit chips. As is well understood, each chip typically performs a limited number of functions for the system, for example, to control a semiconductor memory, to control a hard disk, to control a screen display and other related functions. Periodically, each of these circuits is not needed and is idle insofar as system functionality is concerned. Unfortunately, because these circuits continue to receive a clock signal, their respective internal circuits continue to be exercised and consume significant electric power, even while idle. 
     Lower power consumption is desirable for all electronic systems, but especially for portable computers which are supplied power from a battery with a finite lifetime. Conserving power in a portable computer will mean that the user can use their computer for a longer period of time before it is necessary to replace or recharge the battery, which supplies power to the portable computer. 
     What is needed is an apparatus and method which allows an integrated circuit to turn off the clock signal provided to its circuits during the time when the circuits are not required for operation and allows the clock signal to be restored very rapidly when the circuits are necessary to the operation of the integrated circuit. What is also needed is an apparatus and method which can turn off the clock signal to circuits of an integrated circuit or system and keep the fact that the clock signal is turned off to those circuits transparent to both the system bus and the user. 
     SUMMARY OF THE INVENTION 
     A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates a schematic diagram of the low power clocking apparatus of the present invention. 
     FIG. 2 illustrates a timing diagram of the outgoing clock signal in response to the incoming clock signal, the Kill --  Clock signal lines and the control lines. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The low power clocking apparatus of the present invention is illustrated in FIG. 1. The clock signal 15 is provided to the sub-circuits 11-14 until they have completed their operations and no longer require the clock signal. The clock signal 15 is disabled when each of the sub-circuits 11-14 raise their respective Kill --  Clock signal line outputs 16-19 to a logical high voltage level and the Start --  Clock signal line 10 is also at a logical high voltage level, causing the output 21 of the NAND gate 20 to switch from a logical high voltage level to a logical low voltage level. The central arbiter 1 and the comparison circuitry 2 then monitor the system bus 9 for addresses within the range controlled by the central arbiter 1 or for specific commands, whose completion will require the operation of the electronic system or integrated circuit. When an address within the controlled range and a corresponding command is detected, the central arbiter 1 pulls the Start --  Clock signal line 10 to a logical low voltage level, causing the output 21 of the NAND gate 20 to switch from a logical low voltage level to a logical high voltage level. The clock signal 15 is then re-enabled to all of the sub-circuits 11-14 and is provided to those circuits until they have all completed their operations and no longer require the clock signal. 
     The system bus 9 is coupled as an input to the central arbiter 1. The central arbiter 1 is coupled to the comparison circuitry 2 through the address lines 7 which provide the address from the system bus 9 to the comparison circuitry 2. The comparison circuitry 2 is also coupled to the central arbiter 1 through the control line 8 which informs the central arbiter 1 when the address on the address lines 7 is in the range of addresses controlled by the central arbiter 1. The central arbiter 1 is coupled to the NAND gate 20 by the Start --  Clock signal line 10 which is used to restore the clock signal to the circuits controlled by the central arbiter 1 after the clock signal 15 has been disabled. 
     The Kill --  Clock line output 16 of the sub-circuit 11 is coupled as an input to the NAND gate 20 to signal when the sub-circuit 11 no longer requires a clock signal. The Kill --  Clock line output 17 of the sub-circuit 12 is coupled as an input to the NAND gate 20 to signal when the sub-circuit 12 no longer requires a clock signal. The Kill --  Clock line output 18 of the sub-circuit 13 is coupled as an input to the NAND gate 20 to signal when the sub-circuit 13 no longer requires a clock signal. The Kill --  Clock line output 19 of the sub-circuit 14 is coupled as an input to the NAND gate 20 to signal when the sub-circuit 14 no longer requires a clock signal. It should be obvious to one of reasonable skill in the art that any number of sub-circuits having a Kill --  Clock line output can be coupled as inputs to the NAND gate 20. 
     The external clock signal 5 is provided as an input to the multiplexer 4 and to the frequency synthesizer 3. The output of the frequency synthesizer is also provided as an input to the multiplexer 4. The clock select signal line 6 is coupled as an input to the multiplexer 4 and can be used to select between the external clock signal 5 or the clock signal which is output from the frequency synthesizer 3. The frequency synthesizer 3 can be used to multiply or divide the external clock signal. In the preferred embodiment of the present invention, the frequency synthesizer multiplies the external clock signal by the value of 7/4. 
     The output 21 of the NAND gate 20 is coupled to the D input of the flip-flop 22. The output 23 of the flip-flop 22 is coupled as an input to the NAND gate 26. The clock output signal 24 from the multiplexer 4 is provided as an input to the inverter 25 and to the clock signal input of the NAND gate 26. The output signal 29 from the inverter 25 is coupled to the clock input of the flip-flop 22. The output 27 from the NAND gate 26 is coupled to the input of the inverter 28 and the output signal 15 from the inverter 28 is provided as the clock signal input to the sub-circuits 11-14. 
     The input lines 10 and 16-19 to the NAND gate 20 notify the NAND gate 20 when any of the sub-circuits 11-14 still require the clock signal for their operations. As long as any of the inputs to the NAND gate 20 are at a logical low voltage level the output from the NAND gate 20 will be at a logical high voltage level and the clock signal 15 will be provided to all of the sub-circuits 11-14. As each of the sub-circuits 11-14 complete their operations and no longer require the clock signal 15 they will raise their respective Kill --  Clock signal lines 16-19 to a logical high voltage level. Until all of the Kill --  Clock signal lines 16-19 have been raised to a logical high voltage level, all of the sub-circuits 11-14 are still provided with the clock signal 15. If one of the sub-circuits 11-14 which has already raised its Kill --  Clock signal line to a logical high voltage level is subsequently involved in an operation for which it will need the clock signal 15, then while the clock signal 15 is still active, that sub-circuit can pull its Kill --  Clock signal line to a logical low voltage level and keep the clock signal 15 active. As soon as all of the Kill --  Clock signal lines 16-19 and the Start --  Clock signal line 10 are at a logical high voltage level, the output 21 of the NAND gate 20 switches from a logical high voltage level to a logical low voltage level and the clock signal 15 is then disabled or pulled to a constant logical low voltage level. 
     The clock signal 15 remains disabled until the central arbiter 1 is notified by the comparison circuitry 2 that any one of the circuits 11-14 will require the clock signal. The comparison circuitry 2 uses the address value on the system bus 9 and compares that address value to lookup tables or to hard-wired internal chip registers to determine if the address value on the system bus 9 is within the range of addresses controlled by the central arbiter 1. If the address value specified on the system bus 9 is within the range of addresses controlled by the central arbiter 1 and a corresponding command is present then the control line 8 is raised to a logical high voltage level and the central arbiter 1 is notified that it should provide a clock signal to the sub-circuits 11-14. The central arbiter 1 then pulls the Start --  Clock signal line 10 to a logical low voltage level causing the output of the NAND gate 20 to rise to a logical high voltage level. The clock signal 15 is then re-enabled, or coupled to match the output 24 of the multiplexer 4, and the sub-circuits 11- 14 are provided with the clock signal 15. The central arbiter 1 also will re-enable the clock signal 15 when specific commands are present on the system bus 9. In the preferred embodiment of the invention, the central arbiter 1 specifically monitors the system bus 9 for commands involving any bus transactions to a register, including Input/Output Read or Write and Memory Read or Write commands, within the electronic system or integrated circuit or any transaction to circuitry controlled by the system. When an address within the range controlled by the central arbiter 1 and one of these specific commands are detected, then the clock signal 15 will be re-enabled to the sub-circuits 11-14. 
     Once the command on the system bus 9 is not one of the specific commands that the central arbiter 1 is looking for and the address specified on the system bus 9 is no longer in the address range controlled by the central arbiter 1, the central arbiter 1 will then raise the Start --  Clock signal line 10 to a logical high voltage level to signal that it no longer requires the clock signal for any one of the sub-circuits 11-14. The clock signal 15 will remain active however, until all of the sub-circuits 11-14 have completed their tasks and have raised their respective Kill --  Clock signal lines 16-19 to a logical high voltage level. The clock signal 15 will then be disabled until the comparison circuitry 2 instructs the central arbiter 1 that the address specified on the system bus 9 is within the range of addresses which the central arbiter 1 is controlling and one of the corresponding commands is detected. 
     The system bus used in the preferred embodiment of the invention is an ISA bus which has a 16 bit wide data path and a 24 bit wide address bus. The ISA bus is asynchronous and operates with system clock rates from 6 MHz to 12 MHz. 
     FIG. 2 illustrates a timing diagram which shows the timing of the operation of the low power clocking apparatus of the present invention. The output clock signal 24 from the multiplexer 4 is illustrated at the top of FIG. 2 by the Clk --  in waveform, the clock signal line 15 output from the inverter 28 is illustrated as the Clk --  out waveform, the D input to the flip-flop 22 is illustrated as the D waveform, the Q output from the D flip-flop 22 is illustrated as the Q waveform and the control line signal 8 from the comparison circuitry 2 is illustrated as the Control waveform. 
     Upon startup the integrated circuit of the preferred embodiment is brought up in its low power clock mode, with the clock signal 15 to the sub-circuits 11-14 disabled. When the integrated circuit is required for operation of the system, the central arbiter 1 pulls the Start --  Clock signal line 10 to a logical low voltage level, causing the Clk --  out signal to be activated and the clock signal 15 to be provided to the sub-circuits 11-14. The central arbiter 1 will then raise the Start --  Clock signal line 10 to a logical high voltage level if the address specified on the system bus 9 is not within the range of addresses controlled by the central arbiter 1 and the command on the system bus 9 is not one of the specific commands that the central arbiter 1 is looking for. Then, once the sub-circuits 11-14 have completed their required operations and no longer need the clock signal 15, they each raise their respective Kill --  Clock signal lines 16-19 to a logical high voltage level. After all the sub-circuits 11-14 have raised their Kill --  Clock signal lines 16-19 to a logical high voltage level, the output 21 of the NAND gate 20 and the D input of the flip-flop 22 switches from a logical high voltage level to a logical low voltage level as is illustrated in FIG. 2 at the time 50. In response to the D input of the flip-flop 22 changing, the Q output of the flip-flop 22 then switches from a logical high voltage level to a logical low voltage level on the next negative clock edge of the Clk --  in signal, illustrated in FIG. 2 at the time 51. At this same clock edge, the Clk --  out signal is disabled so that the sub-circuits 11-14 are not provided with a clock signal. Because the operation of the flip-flop 22 is controlled by the negative edge of the clock signal Clk --  in, the clock signal Clk --  out is disabled when it is already at a logical low voltage level, allowing disabling of the clock signal to occur without glitches or noise pulses. 
     When the Clk --  out signal is disabled, the central arbiter 1 and the comparison circuitry 2 continuously monitor all of the addresses and commands on the system bus 9, until one of the addresses within the range controlled by the central arbiter 1 and one of the specific corresponding commands appears on the system bus 9. When an address within the range controlled by the central arbiter 1 and one of the specific commands appears on the system bus 9, the central arbiter 1 pulls the Start --  Clock signal line 10 to a logical low voltage level and the Clk --  out signal is re-enabled. When one of the addresses within the range controlled by the central arbiter 1 appears on the system bus 9 the comparison circuitry 2 raises the control signal line 8 to a logical high voltage level, as is illustrated at the time 52, notifying the central arbiter 1 an address within its control has been detected. If a corresponding command is also present on the system bus 9, the central arbiter 1 then pulls the Start --  Clock signal line 10 to a logical low voltage level and in response, the output 21 of the NAND gate 20 switches from a logical low voltage level to a logical high voltage level, causing the D input to the flip-flop 22 to do the same, as illustrated at the time 53 in FIG. 2. On the next negative clock edge of the Clk --  in signal, the Q output from the flip-flop 22 switches from a logical low voltage level to a logical high voltage level, as illustrated at the time 54 in FIG. 2. In response to the Q output of the flip-flop 22 changing, the Clk --  out signal will be re-enabled, beginning at the next positive clock edge as illustrated at the time 55. Because the clock signal Clk --  out is at a logical low voltage level when the clock signal is disabled, the present invention is designed so that the clock signal will always restart on the next positive edge of the clock signal Clk --  in. 
     The signal Clk --  out stays enabled until the central arbiter 1 raises the Start --  Clock signal line 10 to a logical high voltage level and all of the sub-circuits 11-14 raise their respective Kill --  Clk signal lines 16-19 to a logical high voltage level, signalling that they all have completed their required operations and that they no longer require the clock signal 15. When this happens, the output 21 of the NAND gate 20 switches from a logical high voltage level to a logical low voltage level causing the D input of the flip-flop 22 to do the same. In response to the D input changing, on the next negative clock signal edge, the Q output is pulled to a logical low voltage level and the Clk --  out signal is disabled as illustrated in FIG. 2 at the time 56. The clock then remains disabled until the central arbiter 1 pulls the Start --  Clock signal line 10 to a logical low voltage level. 
     After the clock signal 15 to the sub-circuits 11-14 has been disabled, the clock signal 15 cannot be re-enabled and provided to those sub-circuits until the central arbiter 1 pulls the Start --  Clock signal line 10 to a logical low voltage level. The sub-circuits 11-14 can only signal that they no longer require the clock signal 15, but cannot signal that they need the clock signal 15, once it has been disabled. Once the clock signal 15 has been disabled, the central arbiter 1 must then monitor the system bus 9 and the comparison circuitry 2 so that it knows when the sub-circuits 11-14 are required for operation and will need the clock signal 15. 
     In order for the central arbiter 1 and the comparison circuitry to monitor the system bus, they must either be provided with a clock signal at all times or designed to be asynchronous. In the preferred embodiment of the present invention, the output clock signal 24 from the multiplexer 4 is always provided to the inverter 25, to the flip-flop 22 and to the NAND gate 26. The output clock signal 24 from the multiplexer 4 is also coupled to always be provided to the central arbiter 1 for the parts of the central arbiter 1 which are synchronous and require the clock signal in order to monitor the system bus and the comparison circuitry. The comparison circuitry 2 is designed to be asynchronous so that it does not require a clock signal to make its comparisons of the addresses on the system bus 9 and to notify the central arbiter 1 when the address on the system bus 9 is within the range of addresses controlled by the central arbiter 1. 
     The preferred embodiment of the present invention is incorporated within a PCMCIA Host Adapter. 
     An Advance Data Sheet, dated October 1993, for PCMCIA Host Adapters, part Nos. CL-PD6710/PD672X, published by Cirrus Logic, Inc. of 3100 West Warren Ave., Fremont, Calif. 94538 which includes the low power clocking apparatus and method of the present invention, is included as Appendix A and attached hereto, beginning at page 12. A VHDL code listing for the preferred embodiment of the central arbiter and the low power clocking apparatus is included as Appendix B and attached hereto as a microfiche appendix. 
     The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiment chosen for illustration without departing from the spirit and scope of the invention. For example, the preferred embodiment is directed to a low power clocking apparatus and method for a PCMCIA Host Adapter. However, the low power clocking apparatus and method may be incorporated into any integrated circuit which utilizes a clock signal. ##SPC1##