Abstract:
A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    The present application is a continuation of U.S. patent application Ser. No. 11/456,858, filed Jul. 12, 2006, which claimed priority to Taiwan application number 094123565, filed Jul. 12, 2005. The contents of these applications are incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention generally relates to a multimedia data stream, and more particularly, to a method and an apparatus for synchronizing a multimedia data stream. 
         [0004]    2. Description of the Prior Art 
         [0005]    When processing a multimedia data stream, it is crucial that the synchronization of data included in the multimedia data stream be accurately controlled. Digital television (DTV) for example, comprises a video data stream, an audio data stream, and a plurality of program clock reference (PCR) values within its multimedia data stream. The PCR values included in the multimedia data stream are utilized by a DTV receiver as a reference basis. The DTV receiver further refers to decoding time stamps (DTS) and presentation time stamps (PTS) included in the video data stream to process the video data stream. Similarly, the DTV receiver also refers to presentation time stamps (PTS) included in the audio data stream to process the audio data stream. 
         [0006]    In the prior art, a phase lock loop (PLL) is utilized to generate a local clock. Counter values accumulated through counting the local clock are used as a local clock reference for approaching the program clock reference (PCR) of the multimedia data stream. However, the local clock reference does not accurately approach the PCR of the multimedia data stream, and problems will occur in the synchronization process for the video and audio data streams of the multimedia data stream. 
       SUMMARY OF THE INVENTION 
       [0007]    One of the objectives of the present invention is to provide a method and an apparatus for synchronizing a multimedia data stream. 
         [0008]    According to the embodiments of the present invention, a method for synchronizing a data stream is disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing. 
         [0009]    According to the embodiments of the present invention, an apparatus for synchronizing a data stream is disclosed. The apparatus comprises: a decoder for generating a decoded data stream, and a plurality of program clock references; a timing control module for generating a simulated clock reference according to the program clock references and the local clock reference, and for comparing the local clock reference with the simulated clock reference to produce a comparison result; and a processor for adjusting a processing timing of the decoded data stream according to the comparison result, and for processing the decoded data stream according to the processing timing. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  shows an apparatus for processing a multimedia data stream according to an embodiment of the present invention. 
           [0012]      FIG. 2  shows a table illustrating the relationship between the simulated clock reference value Yi″ and the program clock reference value Y. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]      FIG. 1  shows an apparatus  100  for processing a multimedia data stream according to an embodiment of the present invention. The video and audio data generated by the apparatus  100  can be further sent to other devices, such as a video display and speakers for performing the playback process. 
         [0014]    The apparatus  100  comprises a decoder  120 , a processor  140 , and a timing control module  160 . The decoder  120  decodes the multimedia data stream to generate a decoded data stream. In this example, the decoded data stream includes a video data stream and an audio data stream. The video data stream and audio data stream are then sent to the processor  140 . The decoder  120  further extracts the clock reference values, including the program clock reference (PCR) values, and sends the extracted program clock reference values to the timing control module  160 . The program clock reference values extracted from the multimedia data stream help constitute a program clock reference for the timing control module  160 . 
         [0015]    The timing control module  160  comprises a clock generator  162 , a counter  164 , a calculating unit  166 , and a controller  168 . The clock generator  162  which can be implemented by a phase lock loop (PLL) or a delay lock loop (DLL) or a clock synthesizer generates a local clock. If the multimedia data stream received by the apparatus  100  conforms to DTV specifications, the frequency of the local clock is approximately 27 MHz. The counter  164  generates a local counter value (LC) by counting on the local clock. The local counter value constitutes a local clock reference. Also worth note is that a timer could also be used to generate the local clock reference. The processor  140  comprises a video processor  142  and an audio processor  144 , both utilized for respectively processing the video data stream and the audio data stream according to the local clock reference. For example, using the local clock reference as a basis, the video processor  142  processes the video data stream by referring to the decoding time stamps (DTS) and presentation time stamps (PTS) included in the multimedia data stream. The audio processor  144  would also processes the audio data stream by referring to the presentation time stamps (PTS) included in the multimedia data stream while using the local clock reference as a basis. 
         [0016]    The calculating unit  166  generates a simulated clock reference according to the local clock reference and the program clock reference (PCR) values extracted from the multimedia data stream. The simulated clock reference is utilized to approach the PCR provided by the DTV transmitter, which transmits the PCR values intermittently. In the following equations, the variable x is used to represent the local clock reference, the variable y is used to represent the program clock reference provided by the DTV transmitter, and the variable y′ is used to represent the simulated clock reference. For each local clock reference value Xi, the calculating unit  166  determines a value Yi′ for the simulated clock reference according to the following equation: 
         [0000]    
       
      
       y′=m·x+B  
      
     
         [0017]    System designers can then decide what kind of algorithm should be used in determining the two parameters m and B. For example, using the received program clock reference values Yi and the local clock reference values Xi, the calculating unit  166  can determine the parameters m and B to minimize the root mean square (RMS) of sum[(Yi−m·Xi−B)̂2]. The simulated clock reference values Yi′ corresponding to the local clock reference values Xi can then be determined according to the above equation. It is desired to have the system operate in such a way that counter  164  is reset by the timing control module  160  when a first program clock reference value Y 1  is received. The first program clock reference value Y 1  is then utilized as an offset for the simulated clock reference value corresponding to a subsequently generated local clock reference value. In theory, the variation rate of the simulated clock reference should be the same as the variation rate of the local clock reference.  FIG. 2  shows a table illustrating the relationship between the simulated clock reference value Yi′ and the program clock reference value Y. 
         [0018]    In this embodiment, the controller  168  compares the local clock reference with the simulated clock reference, and directs the processor  140  to adjust the processing timing of the decoded data stream accordingly. More specifically, if it detects that the variation rate of the local clock reference is faster than the variation rate of the simulated clock reference, the controller  168  will direct the processor  140  to delay the processing timing of the decoded data stream. For the video data stream, the controller  168  can use the video processor  142  to insert at least one additional video sample (e.g. at least one video pixel or at least one horizontal line) in the blanking area of a frame of the video data stream. For the audio data stream, the controller  168  can use the audio processor  144  to insert at least one additional audio sample in the audio data stream. The controller  168  can also make use of the audio processor  144  to decrease the frequency of processing in the audio data stream within a period (i.e. processing k-n audio samples in the period originally for processing k audio samples). The additional audio and video sample(s) inserted can be generated through an interpolation algorithm. 
         [0019]    On the other hand, if it is found that the variation rate of the local clock reference is slower than the variation rate of the simulated clock reference, the controller  168  directs the processor  140  to advance the processing timing of the decoded data stream. For the video data stream, the controller  168  can use the video processor  142  to skip at least one vertical line or horizontal line in the blanking area of the video data stream. For the audio data stream, the controller  168  can use the audio processor  144  to skip at least one audio sample in audio data stream. The controller  168  can also use the audio processor  144  to increase the frequency of processing in the audio data stream within a period (i.e. processing k+n audio samples in the period originally for processing k audio samples). The advancing or delaying of the processing timing in the video data stream and audio data stream must be performed such that the synchronization requirements are satisfied. 
         [0020]    In addition, the audio processor  144  can further comprise a first-in-first-out (FIFO) buffer  145 . The timing control module  160  can further control the processor  140  to adjust the processing timing of the decoded data stream according to the buffer occupancy of buffer  145 . As an example, if the buffer occupancy of buffer  145  is large, the timing control module  160  directs the processor  140  to advance the processing timing of the multimedia data stream. If the buffer occupancy of buffer  145  is small, the timing control module  160  would direct the processor  140  to delay the processing timing of the multimedia data stream. 
         [0021]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.