Abstract:
In this process, a capacitor core is formed on a semiconductor device with a first conductive sublayer in contact with a plug. First form a stack of alternately doped and undoped oxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Then form a mask over the stack and etch through the mask to pattern the oxide layers to form cavities in the stack of oxide layers reaching down through the stack to the sublayer. Then perform differential etching of the oxide layers in the cavities. Form undercut edges in the doped oxide layers with the undoped oxide layers having cantilevered ribs projecting from the stacks into the cavities to complete the cavities. Deposit a bulk/thick film monolithic conductive layer into the cavities to form a monolithic capacitor core with counterpart cantilevered ribs.

Description:
This application is a divisional of application Ser. No. 09/192,457 filed on Nov. 16, 1998, now U.S. Pat. No. 6,344,392 B1. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to capacitors for DRAMs and more particularly to lower electrodes of crown capacitors with fins or to lower electrodes of stack capacitors. 
     2. Description of Related Art 
     U.S. Pat. No. 5,208,180 of Gonzalez shows a “Method of Forming a Capacitor” using a oxide etching process. 
     U.S. Pat. No. 5,532,182 of Woo for a “Method for Fabricating Stacked Capacitor of a DRAM Cell” shows a fin type capacitor using doped and undoped amorphous Si layers. 
     U.S. Pat. No. 5,573,967 of Tseng describes a “Method for Making Dynamic Random Access Memory with Fin-type Stacked Capacitor”. 
     U.S. Pat. No. 5,631,184 of Ikemasu et al. describes a “Method of Producing a Semiconductor Device Having a Fin-type Capacitor.” 
     U.S. Pat. No. 5,637,523 of Fazan describes a “Method for Forming a Capacitor and a Capacitor Structure” shows a in type capacitor formed by etching doped and undoped polysilicon layers. 
     U.S. Pat. No. 5,656,536 of Wu describes a “Method of Manufacturing a Crown Shaped Capacitor with Horizontal Fins for High Density DRAMS.” 
     SUMMARY OF THE INVENTION 
     A fin structure can be made by alternately depositing silicon nitride (Si 3 N 4 ) and silicon dioxide (SiO 2 ) and dipping back and then filling with a polysilicon layer which is a complicated process. 
     A crown or stack capacitor with a fin structure is made with a different silicon dioxide etching rate in a vapor of hydrogen fluoride HF acid environment. 
     This invention teaches a method of forming a fin structure using a combination of both doped and undoped silicon dioxide layers with a bulk or a thin film second conductive layer formed into a capacitor core. The core can be composed of a monolithic body of conductive material. 
     In accordance with this invention, a process of forming an electrode comprises the steps of formation of a capacitor core formed on a semiconductor device which contains doped regions in the surface thereof blanketed with a dielectric layer which contains a conductive plug extending therethrough which contacts one of the doped regions in the semiconductor substrate. 
     First, form a sublayer comprising a first conductive layer in contact with a plug which contacts one of the doped regions in the semiconductor substrate. Form a mold from a stack of silicon dioxide layers which are alternatingly an undoped layer covered with a doped layer on the sublayer comprising the first conductive layer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold. Deposit a layer of polysilicon into the cavity forming a capacitor core with counterpart ribs cantilevered (projecting) with a complementary pattern to the mold and the capacitor core having a top surface. Polish the capacitor core to remove the top surface of the core, and remove the mold. 
     Preferably, the mold is etched with a combination of hydrogen fluoride vapor and water vapor. 
     In one embodiment, the core is formed of a solid deposit of a second conductive layer which fills the cavity. The dopant comprises boron and phosphorus and the mold is etched with a combination of hydrogen fluoride vapor and water vapor. 
     Preferably, the dopant comprises boron and phosphorus, and the mold is etched with a combination of hydrogen fluoride vapor and water vapor. 
     The core is planarized by a CMP process which removes a top undoped layer of the mold whereby the core has a flat upper surface with a rib located on top of the core, and etch back the sublayer comprising a first thin conductive layer to separate the core from adjacent cores. 
     Alternatively one can deposit a thin layer of a second conductive layer such as polysilicon into the cavity. Then, form a thin capacitor core with an array of counterpart cantilevered (projecting) ribs with a pattern which is complementary to the pattern of the mold. The capacitor core has a top surface. 
     In the case of the thin layer of the second conductive layer, next deposit a photoresist layer into the inner cavity filling the inner cavity. Then polish the capacitor core to remove the top surface of the core, and remove the photoresist and remove the mold. 
     Then etch back the sublayer comprising a first thin conductive layer to separate the core from adjacent cores. 
     Preferably, the core is a monolithic core. 
     In accordance with another aspect of this invention, a monolithic capacitor core is formed on a semiconductor device. A sublayer comprising a first conductive layer is formed in contact with a plug which contacts a doped first conductive region in the semiconductor substrate. A second conductive layer is formed into a monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of the monolithic core. The monolithic capacitor core has a cantilevered top surface projecting from the exterior sidewall of the monolithic core. 
     Preferably the second conductive layer is formed into a hollow monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of the monolithic core and a base covering the first conductive layer. It that case it is preferred that the second conductive layer formed into a monolithic core is composed of a material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride, and said second conductive layer has a thickness from about 500 Å to about 1,000 Å. 
     Alternatively, the second conductive layer is formed as a solid monolithic capacitor core having cantilevered ribs projecting from exterior sidewalls of the monolithic core and the core covering the first conductive layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which: 
     FIG. 1 shows a sectional vertical elevation of a fragment of a semiconductor device with a first conductive layer formed on the top surface in an intermediate stage of fabrication of a device in accordance with this invention. 
     FIG. 2 shows the device of FIG. 1 after formation of sacrificial structures which are to serve as molds with monolithic capacitor core cavities formed of stacks of laminated, blanket layers formed over the first conductive layer. 
     FIG. 3 shows a first embodiment of the device of FIG. 2 after thin film monolithic crown capacitor cores have been formed in the cavities on the sidewalls of the stacks of laminated, blanket layers formed over the first conductive layer. Photoresist fills the hollow spaces within the monolithic capacitor cores. 
     FIG. 4 shows the device of FIG. 3 after the monolithic capacitor cores have been polished down, the molds have been removed, and the first conductive layer has been etched in a self-aligned etch. 
     FIG. 5 shows a second embodiment of the device of FIG. 2 after solid stack monolithic capacitor cores have been formed in the cavities over the first conductive layer. 
     FIG. 6 shows the device of FIG. 5 after the monolithic capacitor cores have been polished down, the molds have been removed, and the first conductive layer has been etched in a self-aligned etch. 
    
    
     DESCRIPTION OF STRUCTURE ANCILLARY TO THE PREFERRED EMBODIMENT 
     FIG. 1 shows a sectional vertical elevation of a fragment of a semiconductor device in an intermediate stage of fabrication of a device in accordance with this invention. A P-doped silicon semiconductor substrate  12  is shown with N+ doped regions  14  and  14 ′ formed in the surface of the substrate  12  and spaced on opposite ends of the portion of substrate  12  shown in FIG.  1 . Four gate electrode/conductor stacks  21 A- 21 D are shown on the surface of substrate  12  with the stack  21 A formed on the surface of an N+ doped region  14  and stack  21 D formed on the surface of an N+ doped region  14 ′. 
     The stacks  21 A- 21 D include gate oxide regions GOX on which polysilicon conductor/gate electrode layers  16  are formed on the surface of substrate  12 . On each of the polysilicon conductor/gate electrode layers  16  is a refractory metal silicide layer  19  such as tungsten silicide (WSi 2 ), a cap layer usually composed of silicon dioxide (SiO 2 ) layer  20  and a silicon nitride (Si 3 N 4 ) layer  22  which can be implemented, as is well understood by those skilled in the art and as is described in the U.S. Pat. No. 5,792,689 of Fu-Lian Yang and Erik S. Jeng for “Method for Manufacturing Double Crown Capacitors Self-Aligned to Node Contacts on Dynamic Random Access”. 
     Silicon dioxide sidewall spacers SP are formed on the sidewalls of the layers  16 ,  19 ,  20  and  22  of stacks  21 A- 21 D as described in Liaw et al U.S. Pat. No. 5,712,202. Layers  20 ,  22  and spacers SP insulate the layers  16 / 19  from the polysilicon plugs PL which are formed between stacks  21 A/ 21 B and  21 C/ 21 D which reach the capacitor node contacts where plugs PL are formed on the surface of P-substrate  12 . 
     There are doped regions  14  and  14 ′ in the surface of the substrate  12  having top surfaces to which the plugs PL 1  and PL 2  respectively make electrical and mechanical contact, as in Liaw et al U.S. Pat. No. 5,712,202 and in Yang et al U.S. Pat. No. 5,792,689. 
     A planarizing insulating layer  24  composed of BPSG has been formed as described in Liaw et al U.S. Pat. No. 5,712,202 covering the stacks  21 A- 21 D and the substrate  12 , but capacitor node contact openings have been formed between the sidewall spacers SP of stacks  21 A and  21 B on the left and between the sidewall spacers SP of stacks  21 C and  21 D on the right and those openings have been filled with metal, conductive plugs PL 1 /PL 2  extending from contact with the N+ doped regions  14 / 14 ′ respectfully on the surface of the substrate  12  between the stacks  21 A/ 21 B and between the stacks  21 C/ 21 D to the top surface of the BPSG layer  24 . 
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Step 1 
     Above the BPSG layer  24  and plugs PL 1 /PL 2  a doped, thin first conductive layer/sublayer SL composed of doped polysilicon is formed on the surface of the device of FIG.  1 . In step 1, after the capacitor node contact and polysilicon plugs PL 1 /PL 2  are formed a thin polysilicon sublayer comprising a first conductive layer SL Is deposited which can be implanted with arsenic with a dose in the range from about 1E20 to 1E22 Ions/cm 2  and an energy between 30 keV and 45 keV thus giving the first conductive layer SL a dopant concentration from about 1E20 ions/cm 3  to 1E22 Ions/cm 3 . Preferably, the first conductive layer SL has a thickness from about 5000 Å to about 10,000 Å with a preferable thickness of about 8,000 Å. 
     Step 2 
     Referring to FIG. 2, the device of FIG. 1 is shown after formation of molds (sacrificial structures) SS 1 , SS 2  and SS 3  formed of a stack of laminated, blanket layers formed over first conductive layer SL. The molds SS 1 , SS 2  and SS 3  comprise undoped silicon dioxide (SiO 2 ) layers  28 A- 28 D alternating with SiO 2  layers  30 A- 30 C which are doped with Boron/Phosphorus (B/P) dopant to form a doped glass dielectric, i.e. BPSG. The sequence is to form an undoped SiO 2  layer  28 A on the bottom, then form a BPSG layer  30 A, covered in turn with an undoped SiO 2  layer  28 B, followed by a BPSG layer  30 B and topped with an undoped SiO 2  layer  28 C. The alternating laminated layers  28 A- 28 D and  30 A- 30 C are formed in situ in a CVD chamber alternately, by depositing one of the undoped oxide layers  28 A- 28 D, followed by depositing one of the BSPG layers  30 A- 30 C in the same chamber of the CVD equipment in a continuous, uninterrupted process by periodically opening and closing the B/P dopant source in a CVD chamber as is described below, and as will be well understood by those skilled in the art. 
     Step 2 involves depositing undoped oxide blanket layers  28 A/ 28 B/ 28 C/ 28 D and boron/phosphorous doped silicon oxide blanket layers  30 A/ 30 B/ 30 C alternately in the same chamber of the CVD equipment by opening and closing the B/P dopant source in a periodic way to form SiO 2  layers  28 A/ 28 B/ 28 C/ 28 D alternating with BPSG glass layers  30 A/ 30 B/ 30 C. 
     Step 3 
     Then patterning mask sections PR 1 /PR 2 /PR 3  with windows W 1  and W 2  therebetween are formed over the layer  28 D on top of the blanket laminated layers  28 A/ 30 A/ 28 B/ 30 B/ 28 C/ 30 C/ 28 D of SiO 2  alternating with BPSG glass layers. The layers  28 A/ 30 A/ 28 B/ 30 B/ 28 C/ 30 C/ 28 D are then patterned by forming a mask and etching through the windows W 1 /W 2  to form cavities CC 1 /CC 2  to form sacrificial molds SS 1 -SS 3 . In other words, the windows W 1 /W 2  through the mask sections PR 1 /PR 2 /PR 3  were used to form molds to shape the cores of capacitor crowns that are patterned by etching in step 4 below to produce the result shown in FIG. 2 with a set of intercore, capacitor-core-shaping cavities CC 1 /CC 2  formed below windows W 1  and W 2  respectively (to serve as molds for capacitor cores) in FIG. 2, by plasma dry etching between sacrificial structures SS 1 , SS 2  and SS 3 . 
     The laminated, sacrificial molds SS 1 , SS 2  and SS 3  are shown protected by patterning photoresist mask sections PR 1 /PR 2 /PR 3  which were formed for the purpose of protecting the molds SS 1 , SS 2  and SS 3  during patterning of the alternating laminated layers  28 A- 28 D and  30 A- 30 C by etching of those laminated layers to form intercore, capacitor-core-shaping cavities CC 1  and CC 2  above the plugs PL 1  and PL 2  respectively in complementary patterns to the capacitor crowns which are to be formed subsequently as indicated by FIGS. 3 and 4 for the first embodiment and by FIGS. 5 and 6 for the second embodiment. 
     Then the intercore cavities CC 1 /CC 2  (which are to be used as sacrificial molds for shaping capacitor cores seen in FIGS. 4 and 6) are formed in the shape of the photoresist mask elements PR 1 , PR 2 , and PR 3  by plasma dry etching (sacrificial structures) SS 1 -SS 3  as described in step 3 above. 
     Next, the device is etched again in step 4 to produce the undercuts UC seen in FIG.  2 . 
     Step 4 
     A differential rate of etching back the undoped silicon dioxide layers  28 A/ 28 B/ 28 C/ 28 D (slowly) and the doped BPSG layers  30 A/ 30 B/ 30 C (more rapidly) is performed to enlarge the intercore, capacitor-core-shaping CC 1 /CC 2  with a vapor solution of hydrogen fluoride (HF). The silicon dioxide and BPSG are etched in an atmosphere of water vapor and hydrogen fluoride (HF) which provides a vapor etchant. The BPSG layers  30 A/ 30 B/ 30 C are etched back at a greater rate than the undoped silicon dioxide layer providing an undercut UC in BPSG glass layers  30 A/ 30 B/ 30 C leaving cantilevered ribs CR of SiO 2  layers  28 A/ 28 B/ 28 C/ 28 D which now project into the intercore cavities CC 1 /CC 2 . 
     One can tune doped/undoped selectivity by varying the concentration of hydrogen fluoride HF and water vapor. 
     First Embodiment 
     The first embodiment of the process continues after step 4 comprising the following steps: 
     Step 5A 
     FIG. 3 shows the device of FIG. 2 after thin film crown capacitor cores  42 A/ 42 B have been formed in the cavities CC 1  and CC 2  on the sidewalls of stacks SS 1 -SS 3 . The cores  42 A/ 42 B are preferably monolithic in the sense that they are formed of a single homogeneous, conductive, core layer  40 . 
     Then a filler layer  41  of a material such as photoresist fills the hollow spaces within the capacitor cores  42 A/ 42 B. 
     In the case of the crown capacitor cores  42 A/ 42 B In FIGS. 3, deposit a conformal, thin polyslilcon, second conductive, core layer  40  into cavity blanketing the top of first conductive layer SL and coating the walls of the molds SS 1 , SS 2  and SS 3 , as shown in FIG. 3 to form crown capacitor cores  42 A/ 42 B from conductive core layer  40 , leaving the openings  44  only partially filled by the thin layer of conductive material  40 . Conductive core layer  40  can be composed of an electrically conductive material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride. Conductive material  40  has a thickness from about 500 Å to about 1,000 Å. 
     Step 6A 
     FIG. 4 shows the device of FIG. 3 after the capacitor cores  42 A/ 42 B have been polished down and the molds have been removed. 
     As can be seen in FIG. 4 counterpart cantilevered ribs  40 A,  40 B,  40 C have been formed where the cores extend out into the space where the undercut regions UC had been located in the molds SS 1 , SS 2  and SS 3 . 
     The crown capacitor cores  42 A/ 42 B in FIG. 4 are shown after the openings  44  which were filled with filler (photoresist) layer  41  have been polished by a CMP (Chemical Mechanical Planarization) process to remove polysilicon layer  28 D and a portion of the core layer  40  above the rib  40 C. 
     Thus, the cores have been planarized by the CMP process which removes a top undoped layer  28 D of the molds SS 1 -SS 3  whereby the cores  42 A/ 42 B have a flat upper surface with a rib  40 C located on top of each of the cores  42 A/ 42 B. 
     Step 7A 
     The first part of Step 7A is to remove the filler layer  41  (photoresist) in the conventional manner. 
     Then, remove the mold formed by silicon dioxide/BPSG layers  28 A/ 30 A/ 28 B/ 30 B/ 28 C/ 30 C/ 28 D from the inside and the outside of the crown capacitor cores  42 A/ 42 B subtractively in a process which removes the SiO 2  layers  28 A/ 28 B/ 28 C/ 28 D and the BPSG glass layers  30 A/ 30 B/ 30 C by a step with a Buffered Oxide Etching (BOE) solution which leaves the crown shape with the horizontal fins which consists of the first conductive layer SL and the second conductive, core layer  40 . 
     Then dry etch back polysilicon first conductive layer SL between the cores  42 A/ 42 B in a self-aligned etch using the crown capacitor cores  42 A/ 42 B as masks to isolate the individual capacitor cores  42 A/ 42 B leaving the remainder of the first conductive layer SL′ beneath each of the crown capacitor cores  42 A/ 42 B. 
     Second Embodiment 
     The process continues after step 4 comprising the following steps: 
     Step 5B 
     FIG. 5 shows a second embodiment of the device of FIG. 2 after solid stack capacitor cores  52 A/ 52 B have been formed in the cavities over the first conductive layer SL. The cores  52 A/ 52 B are preferably monolithic in the sense that they are formed of a single homogeneous material. The capacitor cores  52 A/ 52 B of FIGS. 5 are formed from a thick polysilicon layer  50  blanketing the top of device  10  as shown in FIGS. 5 and 6 to form a set of solid stack conductive capacitor cores  52 A/ 52 B formed by of a core layer  50  of conductive material. Layer  50  can be composed of an electrically conductive material selected from the group consisting of aluminum, copper, tungsten, doped polysilicon, and titanium nitride. 
     As can be seen in FIG. 6 counterpart cantlilevered ribs  50 R have been formed where the cores extend out into the space where the undercut regions UC had been located in the molds SS 1 , SS 2  and SS 3 . 
     Step 6B 
     FIG. 6 shows the device of FIG. 5 after the capacitor cores have been polished down, the molds have been removed, and the first conductive layer has been etched in a self-aligned etch. 
     In the case of the thick core layer  50  of FIG. 6 the CMP can be applied directly to the top of the cores  50  of stack capacitor cores  52 A/ 52 B to produce the planarized structures  52 A/ 52 B, as shown in FIG. 6 to remove the portion of core layer  50  above the top rib  50 R. 
     Thus, the cores  52 A/ 52 B have been planarized by the CMP process which removes a top undoped layer  28 D of the molds SS 1 -SS 3  whereby the cores  52 A/ 52 B have a flat upper surface with a rib  50 R located on top of each of the cores  52 A/ 52 B. 
     Step 7B 
     Next, remove the mold comprising the layers  28 A/ 30 A/ 28 B/ 30 B/ 28 C/ 30 C/ 28 D of silicon dioxide and BPSG from the inside and the outside of the capacitor structures  52 A/ 52 B by a subtractive process which removes the SiO 2  layers  28 A/ 28 B/ 28 C/ 28 D by the steps of a BOE process and the BPSG glass layers  30 A/ 30 B/ 30 C with by the steps of a BOE process. 
     Then etch back the polysilicon first conductive layer SL between the capacitor structures  52 A/ 52 B in a dry etching process, such as an RIE process, using the capacitor structures  52 A/ 52 B as self-aligned masks to isolate the individual capacitor structure  52 A/ 52 B, while leaving the remainder of the first conductive layer SL″ beneath each of the crown capacitor structures  52 A/ 52 B. 
     While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.