Abstract:
Method and apparatus for reducing intra-channel distortions of received data resulting from non-linear signal propagation includes parallel detection subcircuits for determining output values of sequentially provided optical data bits such that each of the sequentially provided optical data bits is processed by only one of the parallel detection subcircuits. Two parallel detection subcircuits process the input optical data bits according to even valued and odd valued clock signals. Each subcircuit has first and second signal analyzers to detect the value of the input optical data bit and a first memory unit and a second memory unit connected to the first and second signal analyzers. The input value of clock information provided to the first and second memory units of the first parallel subcircuit are 180° out of phase with input values indicative of a clock speed provided to the second parallel subcircuit.

Description:
FIELD OF INVENTION  
         [0001]    This invention relates to the field of optical transmission systems and, more specifically, to improving the data recovery in such optical transmission systems via electrical decision feedback.  
         BACKGROUND OF INVENTION  
         [0002]    The maximum reach of long haul on-off keying transmission systems (such as a wavelength division multiplexed (WDM) transmission system operating at 20 Gbits/s or above) is typically limited by three types of signal distortion. Examples of such distortions are optical-to-signal noise ratio (OSNR) degradation, cross-talk and intersymbol interference (ISI). For the purposes of this discussion, ISI-related distortion are of further interest. ISI occurs when received data pulses are altered by pulse broadening or multi-path propagation (e.g., reflections) in the channel in which they travel. Pulse broadening can occur because of chromatic or polarization mode dispersions or receiver bandwidth limitations as described below. The results of such interference result in poor transmission characteristics.  
           [0003]    One specific transmission characteristic that can drastically limit transmission in high-bit-rate systems, particularly for standard single-mode fibers (SSMF), is pulse-spreading type of ISI. This condition is shown in FIGS. 1 a  and  1   b . Specifically, FIG. 1 a depicts a graph  100  of the signal intensity I over time T for an input fiber of a WDM transmission system. The graph  100  is broken up into bit slots (denoted by sections  102 ,  104  and  106 , respectively) which define the time slots available for data to be transmitted in such a system. At a first bit slot, bit slot  102 , a “1” data bit (encoded in a non-return to zero (NRZ) format) is being transmitted followed by a “0” data bit in a second bit slot, bit slot  104 . In a perfect WDM transmission system with perfectly formed fibers, the output intensity of these data pulses would be identical to the input data pulses shown in graph  100 . Unfortunately, due to the above-identified interference conditions (pulse-spreading and the like), the signal sent to the output fiber is not identical to the signal sent to the input fiber.  
           [0004]    More specifically, a graph of the signal intensity at the output fiber is seen in graph  120  of FIG. 1 b . The graph  120  shows the same bit slots  102 ,  104  and  106  after the “1” and “0” data bits have passed through the transmission system. The resultant data stream is more rounded and not as well defined in the first bit slot  102  for the “1” data bit and furthermore extending into the second bit slot  104  which must represent the “0” data bit. ISI occurs when pulses propagating in the fiber spread out and overlap with each other. This condition can occur due to any of the above-described dispersion (or other) phenomena or by the bandwidth of a particular receiver being smaller than the system data rate (i.e., a 10 Gbits/s signal received by a 8 Gbit/s bandwidth limited receiver). The overlap, along with fiber nonlinearity, creates the ISI at locations of the “0” bits in a sequence of pulses, representing logical “ 1 &#39;s” and “0&#39;s”. If the ISI becomes too large, it is detected by a receiver as logical “1&#39;s”, which can lead to transmission errors. These deleterious transmission characteristics are evidenced at the 10 Gbit/s transmission rate. As the bit rates of such a WDM transmission system increases, (i.e., for 20 Gbit/s, 40 Gbit/s and higher), the pulse broadening and subsequent ISI severely restricts the usable bandwidth of the system.  
           [0005]    Methods of mitigating ISI and the effects it has on circuitry is found in various references including J. H. Winters, R. D. Gitlin, “Electrical Signal Processing Techniques in Long-haul Fiber-optic Systems”, IEEE Transactions on Communications, Vol. 38, Issue 9, September 1990, pp.1439-1453; L. Möller, A. Thiede, S. Chandrasekhar, W. Benz, M. Lang, T. Jakobus, M. Schlechtweg, “ISI Mitigation Using Decision Feedback Loop Demonstrated with PMD Distorted 10 Gbit/s signals”, Electronics Letters, Nov. 25, 1999, Vol. 35, No. 24, pp. 2092-2093; H. Bülow, F. Buchali, W. Baumert, R. Ballentin, T. Wehren, “PMD Mitigation at 10 Gbit/s Using Linear and Nonlinear Integrated Electronic Equaliser Circuits”, Electronics Letters, Jan. 20, 2000, Vol. 36, No. 2, pp.163-164; and J. H. Winters, S. Kasturia, “Adaptive Nonlinear Cancellation for High-speed Fiber-optic Systems”, IEEE Journal of Lightwave Technology, Vol. 10, No. 7, July 1992, pp. 971-977. However, as bit rates increase, such solutions will not be able to adequately compensate for the inevitable signal distortions.  
           [0006]    As such, there remains a need for optical fiber transmission systems that can handle high-capacity communications while reducing the deleterious consequences of linear and/or non-linear distortions and PMD.  
         SUMMARY OF THE INVENTION  
         [0007]    The present invention advantageously provides an apparatus for reduction of intra-channel distortions of received data resulting from linear and/or non-linear signal propagation. In one embodiment of the invention, the apparatus includes a plurality of parallel detection subcircuits for determining output values of a plurality of sequentially provided input optical data bits such that each of said sequentially provided input optical data bits is processed by only one of said plurality of parallel detection subcircuits. Such an embodiment may further contain two parallel detection subcircuits that respectively process the input optical data bits according to even valued and odd valued clock signals. Each subcircuit of the apparatus has first and second signal analyzers to detect the value of the input optical data bit. Each subcircuit includes a first memory unit and a second memory unit connected respectively to its first and second signal analyzers. The memory units are also provided with an input value indicative of a circuit clock speed. In one embodiment, input value of clock information provided to the first and second memory units of the first parallel subcircuit are 180° out of phase with input values indicative of a clock speed provided to the second parallel subcircuit. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:  
         [0009]    [0009]FIG. 1 a  depicts a graph of input power versus time for a data signal of the prior art;  
         [0010]    [0010]FIG. 1 b  depicts a graph of output power versus time for a data signal of the prior art;  
         [0011]    [0011]FIG. 2 a  depicts a circuit diagram of an apparatus for improved data recovery in accordance with the subject invention;  
         [0012]    [0012]FIG. 2 b  depicts a block diagram of an optical receiver comprising the apparatus of the subject invention;  
         [0013]    [0013]FIG. 3 a  is a graph of the bit error rate versus received power for a first type of receiver in an optical transmission system that is recovering data in accordance with the subject invention;  
         [0014]    [0014]FIG. 3 b  is a graph of bit error rate versus received power for a second type of receiver in an optical transmission system that is recovering data in accordance with the subject invention; and  
         [0015]    [0015]FIG. 4 depicts an eye diagram of an ISI distorted signal that is improved by the subject invention. 
     
    
       [0016]    To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0017]    [0017]FIG. 2 a  depicts a circuit diagram of a decision feedback equalizer (DFE)  200  in accordance with the subject invention. The DFE  200  of the subject invention is capable of accepting electrical input data signals V in  based upon optical data signals, appropriately converted, and analyzing such data at a variety of circuit elements to output an appropriately recovered data signal component V out1  or V out2 . More specifically, the DFE  200  compares the incoming data V in  to reference voltages denoting threshold detection points for data analysis. Dependent upon clock signaling and the prior data bit value, the DFE  200  will output the data signal component at either a first data output line V out1  or a second data output line V out2 . The configuration of the DFE  200  is such that it facilitates processing of a data pulse stream (i.e., the incoming data signal V in ) of 10 Gbits/s and higher (e.g., 20 Gbits/s, 40 Gbits/s and the like) by splitting the incoming signal V in  into odd and even clock valued bits. As such, corresponding odd and even clock value actuated detection subcircuits are operating at only half of the transmission system data rate. The reader should note that FIG. 2 a  represents a simplified drawing of the circuit of the subject invention. Specifically, each line that connects circuit elements actually represents two lines, each of which carry complementary values of the signal traveling along the depicted line. Additional details are provided in the following description where necessary.  
         [0018]    The DFE  200  comprises a plurality of parallel detection subcircuits  210   n  for processing incoming data pulses V in . In one embodiment of the subject invention, a first parallel subcircuit  210   1  and a second parallel subcircuit  210   2  are provided. Each subcircuit  210   n  further comprises a plurality of input analyzers  202   n . The signal analyzers  202   n  compare the incoming data V in  to threshold references (V ref+  and V ref− ) in order to accurately recover data from V in . As discussed above, each line in the depicted circuit represents two lines of complementary input. Accordingly, each signal analyzer  202   n  has four actual inputs that are represented by the two depicted inputs. For example, the line carrying V in  to first signal analyzer  202   1  is actually one line connecting V in  to a non-inverting input (V in+ ) and a second line connecting V in  to an inverting input on the first signal analyzer  202   1  (V in− ). The line carrying V ref+  on the first signal analyzer  202   1  is actually one line connecting V ref+  to a non-inverting input on the first signal analyzer  202   1  (V ref+ )+and a second line connecting V ref+  to an inverting input on the first signal analyzer  202   1  (V ref+ )−for a total of four inputs. Similar connections are made to the second, third and fourth signal analyzers  202   2 ,  202   3  and  202   4 , respectively. The results of the signal analyzers  202   n  are passed on to a plurality of memory devices  204   n .  
         [0019]    In the first subcircuit  210   1 , the first signal analyzer  202   1  receives data V in  and compares it to an upper detection threshold (V ref+ ) and sends the results to first memory unit  204   1 . A second signal analyzer  202   2  receives input from V in  and compares it to a lower detection threshold reference (V ref− ). The result of the second signal analyzer  202   2  is passed on to second memory device  204   2 . More specifically, each signal analyzer  202   n  has two outputs (represented by the single output line shown). Each memory device  204   n  has a non-inverting input D+ to accept one of the signal analyzer outputs and an inverting input D− to accept another of the signal analyzer outputs. Each of the plurality of memory devices  204   n  is also provided with input that is correlated to the timing of the transmission system. In one embodiment, the memory devices  204   n  are provided with input timing pulses at timing intervals that are half of the system clock rate (CLK/ 2 ).  
         [0020]    The single CLK/ 2  line represents two clock inputs (CLK/ 2 )+ and (CLK/ 2 )− applied to each memory device  204   n . The specific and strategic reason for designing the circuit with a complementary line configuration is that at the high operational speed of the circuit, it is easier to decide about the difference between two voltages (applied signals) than to decide about their absolute value. In other words, common mode distortions are more easily suppressed with the described configuration. The output of each of the plurality of memory units  204   n  is provided to a selector unit  206   n . Specifically, and in one embodiment, the output from first memory device  204   1  and the output of second memory device  204   2  is provided to first selector  206   1 .  
         [0021]    The second subcircuit  210   2  is similarly configured and wired as the first subcircuit  210   1 . Specifically, a third signal analyzer  202   3  receives inputs from V in  and upper threshold reference V ref+  and outputs the results to third memory device  204   3 . Similarly, fourth signal analyzer  202   4  is provided with input from V in  and the lower detection threshold (V ref− ). The output of fourth signal analyzer  202   4  is provided as input to a fourth memory device  204   4 . Each of the third and fourth memory devices  204   3  and  204   4  are also provided with timing pulses that are correlated to the transmission system timing. Specifically, and in one embodiment, second subcircuit  210   2  is provided with input timing pulses at timing intervals that are half of the system clock. However, these timing pulses are opposite or 180° out of phase with pulses provided to the first subcircuit  210   1  (i.e., {overscore (CLK)}/ 2 ). Outputs from the third and fourth memory units  204   3  and  204   4  are provided to a second selector  206   2 .  
         [0022]    The selector  206  from each subcircuit  210   n  is crosswired to its counterpart in the other subcircuit. In this manner, each subcircuit  210   n  is connected to its parallel counterpart so that each subcircuit controls the selection for the next bit in the other subcircuit  210   n . The output from each selector  206   1  and  206   2  is provided as input to first and second secondary memory units  208   1  and  208   2 , respectively. First secondary memory unit  208   1  is provided with an input clock signal one half the clock rate of the transmission system (CLK/ 2 ). Second secondary memory unit  208   2  is provided with an input clock signal one half the clock rate of the transmission system but at 180° out of phase with the first subcircuit  210   1  ({overscore (CLK)}/ 2 ). Accordingly, if the input data pulse at V in  is an odd clock valued data pulse, its recovered output can be found at V out1 . If incoming data V in  is an even clock valued data pulse, the output can be found out at V out2 . Effectively, each subcircuit  210   n  divides the data recovery tasks so that each subcircuit  210   n  is only working at one half the system clock rate (CLK typically 10, 20 Gbits/s or higher).  
         [0023]    The DFE 200 of FIG. 2 a , is created using a plurality of switching and logic components. In one embodiment, the DFE  200  is realized using an enhancement-depletion AlGaAs/GaAs HEMT technology with a 0.2 μ gate length and a threshold frequency of about 60 GHz. Optionally, the DFE  200  is built in source-coupled FET logic for better common-mode noise rejection and high speed circuit operation. Differential coplanar waveguides are implemented on a single chip for providing both clock pulses and data pulses to the circuit  200 . In one particular example, the entire DFE circuit  200  comprises approximately 310 FETs on a chip area of approximately 2.5 mm 2  and operates at a power consumption level of approximately 1.9 W. Accordingly, the subject invention has the capabilities of providing differential feedback equalization to a 20 Gbits/s signal. This design takes advantage of parallel signal processing which reduces electrical bandwidth requirements of the circuit while increasing the gain of a received signal with greater accuracy then previously realizable. One skilled in the art can also understand that since the typical delays associated with a basic feedback loop configuration have been eliminated, incoming signal rates of up to 20 Gbits/s and higher can be processed with the same or better results than the processing of slower signals in the conventional manner.  
         [0024]    Another embodiment of the invention is seen in FIG. 2 b  depicting an optical receiver  250  incorporating the DFE  200 . Specifically, optical receiver  250  receives a train of broad spectrum (WDM) optical data pulses from transmission,line  252 . The pulses are provided to a demultiplexer  254  which segregates the broad spectrum pulses into individual wavelength pulses. The optical receiver may or may not incorporate a single broad spectrum or individual wavelength amplifiers (not shown, but understood by those skilled in the art) to improve incoming pulse quality prior to further processing. Subsequent to demultiplexing, the individual wavelength pulses are provided to a plurality of converters  256  which convert the optical signal into an electrical signal (a logical “1” or “0”). These electrical signals are then provided to a plurality of DFE&#39;s  200  for analysis and data recovery as described to provide a plurality of data recovered electrical signals  258 .  
         [0025]    There are several types of optical data receivers, which can benefit from the above-identified DFE. More specifically, two basic types of optical data receivers are a PIN receiver and an optically pre-amplified receiver. Typically, PIN receivers include, among other components, a photodiode for receiving optical data signals from a transmission line followed by an electrical amplifier. Such a receiver configuration introduces a certain amount of terminal noise into the received signal prior to threshold detection (or recovery); hence, such a receiver requires a relatively higher degree of received power than an optically pre-amplified receiver. The optically pre-amplified receiver contains, among other components, an optical amplifier which receives optical data signals from a transmission line and amplifies them. Subsequent to optical pre-amplification, the received data signal is passed through a band-pass filter (BPF) so as to filter undesirable optical components and sharpen the received signal. Subsequent to band-pass filtering, the received signal is passed to a photodiode which converts the optical signal into an electrical signal.  
         [0026]    The performance gain of a PIN and optically pre-amplified receivers with implemented DFE is described as follows. For PIN receivers, symbol independent thermal noise is the main noise source. For optically pre-amplified receivers, the signal-ASE beat noise becomes dominant. Consequently there will be different performance gains for DFE operation in both receiver types. The amount of InterSymbol Interference (ISI) in both receivers in the examples was the same. For the purpose of equalization gain estimation, FIG. 4 shows an eye diagram  400  of an ISI distorted NRZ signal. For a PIN receiver, the Q factor of the unequalized signal is given by  
       Q   ≈     (         I   max     -     I   min         2                   σ   th         )                           
 
         [0027]    where I max , I min  and σ th  stand for the inner eye borders (traces) and the variance of the thermal noise respectively. Perfect cancellation of the trace representing I min  by means of the DFE would improve the receiver sensitivity by a penalty reduction of  
       Δ   =         -   20                   log        ⌊       Q   DFE       Q   ISI       ⌋       =       -   20                   log        ⌊         I   max     -     I   min         I   max       ⌋                               
 
         [0028]    In the case of an optically pre-amplified receiver, the noise variance becomes symbol dependent. Good approximations for Q factors with and without DEE operation are then given by  
             Q   ≈         I   max     -     I   min             X   ASE            I   max         +       X   ASE            I   min                           Q   DFE     ≈       I   max   ′           X   ASE            I   max   ′         +       X   ASE            I   min   ′                         Δ   =       10                 log        ⌊       I   max       I   max   ′       ⌋            |       Q   DFE     =   Q                                     
 
         [0029]    where X ASE  is a parameter that describes the signal ASE beat noise. When assuming that I Imax  and I min  are proportional to each other, the penalty reduction in the case of the optically pre-amplified receiver is expected to be twice than that for the PIN receiver. Also the ISI amount can be estimated after the penalty is measured.  
         [0030]    In one example, a 20 Gb/s signal was generated by polarization multiplexing of two orthogonally polarized and de-correlated 10 Gb/s 33% RZ data streams. By time interleaving of the 2 31 −1 PRBS data streams with 50 ps phase offset the ISI was minimized. A lightwave converter with relative small electrical bandwidth was used to detect the 20 Gb/s signal. After launching the signal to the decision circuit that included a 2:1 electrical de-mux, the bit error rate measurement was performed at 10 Gb/s data rate. FIG. 3 depicts graphs denoting the characteristics of each type of receiver described above. Specifically, FIG. 3 a  shows a graph  300  plotting received power of a PIN receiver versus the bit error rate (in logarithmic scale). FIG. 3 b  depicts a graph  310  plotting received power of an optically pre-amplified receiver versus the bit error rate (in logarithmic scale). First line  302  (corresponding to the star data points) denote the received power versus bit error rate with a DFE equipped PIN receiver, while a line at  304  (corresponding to the square data points) reflects the same characteristics without DFE. Inspection readily reveals that it is possible to lower the power of a transmitted data signal to the PIN receiver simply by virtue of DFE recovery techniques as described in the subject invention. Similarly, FIG. 3 b  shows similar lines for a pre-amplified receiver. That is, line  306  (corresponding to the star data points) reveals a lower power of a transmitted signal to the optically pre-amplified receiver with DFE than that of a line at  308  (corresponding to the square data points) of such receiver not using DFE. Specifically, the gain from feedback equalization from the subject invention was about 3 DB for the PIN receiver and about twice that for the optically pre-amplified receiver. This is in good agreement with the derivations. The experimental result estimates the ISI to be about 50% (0.5 I max ≈I min ) in front of the decision element without feedback operation. From this we conclude the overall electrical bandwidth of the front end to be around 10 GHz. Accordingly, the results shown herein indicate that there is an improvement in systems using the DFE of the subject invention in that the received power of a transmitted data signal can be reduced and yet still maintain accurate data recovery.  
         [0031]    Although various embodiments that incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.