Abstract:
A data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch.

Description:
TECHNICAL FIELD OF THE INVENTION 
       [0001]    The present invention relates to the synchronization of transmitted data, and more particularly relates to the synchronization of MPEG-2 data. 
       BACKGROUND OF THE INVENTION 
       [0002]    A widely used coding and compression standard for audio and video is the MPEG-2 standard. MPEG-2 is actually the designation for a group of such standards, promulgated by the Moving Picture Experts Group (“MPEG”) as the ISO/IEC 13818 international standard. A typical use of MPEG-2 is to encode audio and video for broadcast signals, including signals transmitted by satellite and cable. 
         [0003]    An MPEG-2 transport stream (“MPEG-2 TS”) is data in a format specified in Part 1, Systems, of ISO/IEC 13818-1. The purpose of the format is to allow the multiplexing of digital video and audio data, and the synchronizing of the resulting output. The basic unit of data in an MPEG-2 TS is the packet. Packets are usually 188 bytes long, but can be 204 bytes long. 
         [0004]    An MPEG-2 TS may be transmitted in Packet Synchronous mode or Packet Asynchronous mode. In Packet Synchronous mode, the clock rate is same as the MPEG-2 data rate, as shown in  FIG. 1 , which is a graph showing signal level versus time for four signals found in a Packet Synchronous mode system. The four signals are a data valid (“DVALID”) signal, a packet synchronization (“PSYNC”) signal, a data signal and a clock signal. The respective signals are vertically displaced, but horizontally (time) aligned to show relative timings of the signals. As can be seen, because the clock and data are synchronous, with the beginning of the clock cycle (in this case, the rising edge of the clock) being made to coincide with approximately the middle of a data bit, at the beginning of each clock cycle there is valid MPEG-2 data. For this reason, DVALID is simply maintained high during the entire packet, after the occurrence of a PSYNCH signal that signals the beginning of the packet, as shown in the figure. 
         [0005]    In contrast, in Packet Asynchronous mode, the clock rate is fixed at some frequency that is higher than MPEG-2 data rate, as shown in  FIG. 2 , which is a graph similar to that of  FIG. 1 , but showing signals found in a Packet Asynchronous mode system. At each clock period, the data may or may not be valid, so each valid bit of data needs to be accompanied by a DVALID signal to inform the system that valid data does, in fact, exist at the beginning of the associated clock cycle. Otherwise, DVALID is not asserted, to inform the system that valid data does not exist at the beginning of a clock cycle. 
         [0006]    Some MPEG-2 TS receiving equipment may be limited to receiving only Packet Synchronous data. Therefore, before providing a Packet Asynchronous data stream to such equipment, the data stream needs to be converted into a Packet Synchronous data stream. This procedure is called Packet Synchronization or sometimes Packet Smoothing. 
         [0007]    In general, to achieve data synchronization, a first-in-first-out (“FIFO”) buffer memory is typically used, since incoming data and outgoing data may have different clocks. The output clock frequency needs to be matched with the average data rate. This matching is normally achieved by using a dedicated PLL  30  which monitors either data rate or the fill status of a FIFO  32 , as shown in  FIG. 3 . Now, it is known that the locking time of a PLL is dominated by its loop filter bandwidth which is designed to be slow to minimize the noise contribution of the phase detector and maintain the PLL stability. However, as a result, it takes many clock cycles to respond to an input data rate shift. To guarantee that no data is lost when a data rate shift does happen, the FIFO length, i.e., the memory size of the FIFO, needs to be much larger than the packet size. 
         [0008]    However, the larger a FIFO that must be provided, the more expensive the circuit incorporating it. Therefore, it would be desirable to have a way of providing for MPEG-2 TS Packet Synchronization with a minimal FIFO size. 
       SUMMARY OF THE INVENTION 
       [0009]    The following summary presents a simplified description of the invention, and is intended to give a basic understanding of one or more aspects of the invention. It does not provide an extensive overview of the invention, nor, on the other hand, is it intended to identify or highlight key or essential elements of the invention, nor to define the scope of the invention. Rather, it is presented as a prelude to the Detailed Description, which is set forth below, wherein a more extensive overview of the invention is presented. The scope of the invention is defined in the Claims, which follow the Detailed Description, and this section in no way alters or affects that scope. 
         [0010]    The present invention provides a data synchronizer that receives an input stream of asynchronous digital data in packets, and provides an output stream of synchronous data in packets. The synchronizer includes a first memory unit and a second memory unit, each having a data input, a data output, a write clock input and a read clock input. A first switch is provided for switching connection of the input in alternating manner between the first memory unit input and the second memory unit input, and a second switch is provided for switching connection of the data synchronizer output in alternating manner between the first memory unit output and the second memory unit output. A write clock is provided to write clock inputs of the first and second memory units. The average data rate of the received valid data during the reception of the packet is determined, and a read clock is generated and provided to the first and second memory units at a rate corresponding to the average data rate of the received valid data bits during the reception of the packet being read. The switching of the first and second switches is controlled such that the switches switch between adjacent packets, with the second switch switching in opposite phase to that of the first switch. 
         [0011]    These and other aspects and features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a signal timing diagram for representative signals found in a synchronous MPEG-2 packet system. 
           [0013]      FIG. 2  is a a signal timing diagram for representative signals found in an asynchronous MPEG-2 packet system. 
           [0014]      FIG. 3  is a high level diagram of a prior art packet data synchronizer. 
           [0015]      FIG. 4  is a high level diagram of a data packet synchronizer according to a preferred embodiment of the invention. 
           [0016]      FIG. 5  is a diagram of the digital frequency synthesizer  42  of  FIG. 4 . 
           [0017]      FIG. 6  is a diagram of the packet counter of  FIG. 5 . 
           [0018]      FIG. 7  is a state diagram showing the conditions for writing data using the data packet synthesizer of  FIG. 4 . 
           [0019]      FIG. 8  is a state diagram showing the conditions for reading data using the data packet synthesizer of  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0020]    The making and use of the various embodiments are discussed below in detail. However, it should be appreciated that the present invention provides many applicable inventive concepts which can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. 
         [0021]    A preferred embodiment of a Packet Synthesizer  40  according to the present invention is shown in  FIG. 4 . This embodiment utilizes a digital phase locked loop (“DPLL”) that is modified to function as a digital frequency synthesizer (“DFS”)  42 , and that has essentially instantaneous response time so the FIFO length may be reduced to that of only two packets. “Essentially instantaneous” in this context means that the frequency is updated within one clock cycle after the update command is sent. The write clock is the supplied clock from input gated by the valid signal. 
         [0022]    Referring now to  FIG. 4 , the Packet Synchronizer  40  is an electronic circuit, preferably implemented in CMOS, that has a Gated Data In input, a Write Clock input, and a Data Out output. Two FIFO buffers, FIFO  1   44  and FIFO  2   46 , each with one MPEG-2 packet length, are shown. Also shown is a Packet Counter  48  having its input connected to Data In and its output connected to the input of the DFS  42 . The output of the DFS is used as a Read Clock. The Write Clock input is provided to the write clock inputs of both FIFO buffers, while the Read Clock from the DFS is provided to the read clock inputs of both FIFO buffers. A first switch SW 1  alternates connection of the Gated Data In input between FIFO  1   44  and FIFO  2   46 . A second switch SW 2  alternates connection of the Data Out output between FIFO  1   44  and FIFO  2   46 , in opposite phase to the connections of the first switch. Thus, while one FIFO buffer is writing the data from Gated Data In, the other FIFO is reading out the data continuously to Data Out. 
         [0023]    The Packet Counter  48  counts the number of write clock cycles and the number of valid data bits during a valid MPEG-2 packet and calculates the correct frequency for the read clock. For example, assuming a packet length of 188 bytes, after the number of bits in 188 valid bytes are counted by the Packet Counter  48  (1 byte=8 bits; thus 188 bytes=8·188=1,504 bits), it determines the number N of input clock cycles counted in the duration of the packet, and sets the read frequency, fr, at 188·fc/N, where fc is the input clock frequency. 
         [0024]    As is explained in detail below in conjunction with  FIG. 5 , the system clock PLL shares the same analog phase locked loop (“APLL”) with the read clock. Therefore, since the write clock frequency is typically same as or related to the system clock, accurate calculation of the read clock frequency is possible. The Packet Counter  48  calculates a frequency code word corresponding to the calculated read clock frequency fr. The resulting frequency code word is then used to update the DFS  42  frequency at the very beginning of reading the next buffer. Because the DFS  42  response is substantially instantaneous, the reading clock frequency matches the writing data rate of the previous packet. No extra buffer length is required. 
         [0025]      FIG. 5  is a simplified diagram of an exemplary DFS  42  implementation. The DFS  42  includes an analog PLL  50  and a digital frequency and phase synthesizer (“FPS”)  51 . The DFS  42  is similar to one described in detail in U.S. Pat. No. 6,329,850, which issued on Dec. 11, 2001 to Hugh Mair, et al., which is commonly assigned and is incorporated herein by reference. The APLL  50  includes a phase detector  52  receiving at one input a reference frequency Fref. The other input receives a feedback signal, described below. The output of the phase detector  52  is provided to the input of a charge pump  53 , the output of which is provided to a low pass filter  54 , the output of which is provided to the control input of a voltage controlled oscillator (“VCO”)  55 , and controls the frequency of a clock generated therein. 
         [0026]    The output of VCO  55  is an M+1 bus PH&lt; 0 :M&gt;, each line of which provides one of M+1 uniformly delayed phases of the VCO  55  clock. All lines of bus PH&lt; 0 :M&gt; are provided to one input of the frequency and phase synthesizer FPS  51 , while the phase  0  line PH 0  only is provided as an output of the APLL  50 , after being divided by M in a frequency divider  56 . The FPS  51  also receives the frequency code word on a B+1 wide bus CW&lt;B: 0 &gt;. The FPS  51  provides an output read clock signal at a frequency determined by the value of CW&lt;B: 0 &gt;. The phase  0  line PH 0  only is also provided to a divide by N divider  57 , the output of which is provided as the feedback signal, mentioned above, to phase detector  52 . APLL  50  operates according to well known principles. 
         [0027]    The specific digital value of the frequency code word on bus CW&lt;B: 0 &gt; corresponds to a multiple of the frequency of the clock signal generated by APLL  50 . Thus, the calculation of the frequency code word in Packet Counter  48  ( FIG. 4 ) is calculated to be equal to fr·P, where P is a factor relating the read clock frequency to the APLL  50  frequency. As explained in detail in the &#39;850 patent, the value of B is greater than log 2  M, and is selected by the designer to be greater than the number required to uniquely select individual phase signals on bus PH&lt; 0 :M&gt; by an amount providing desired additional precision in selection of the time-averaged frequency of the output clock signal from APLL  50 , thereby ensuring that only two packet length FIFOs are needed in the hardware implementation. 
         [0028]      FIG. 6  is a simplified diagram of an exemplary Packet Counter  48  ( FIG. 4 ) implementation. The read clock, fr, is provided to the input of a first counter, counter  1   60 , that has a nine bit wide count output. The PSYNCH signal is provided to the reset input of counter  1   60 . The counter  1   60  output is provided to the D input of a 9-bit wide flip-flop  61  (nine flip-flops in parallel, each receiving one bit line of the counter  1   60  output) and to one input of a first comparator  62 . The other input of comparator  62  is a higher limit value, H, also nine bits. Comparator  62  provides a 1 output when the count output of counter  1   60  is less than H, but a 0 output otherwise. The output of comparator  62  is provided to a first input of a 4-input AND gate  63 , the output of which is a Packet Valid signal. The 9-bit wide Q output of flip-flop  61  is the clock count output, being the number of clock cycles counted in a packet. The PSYNCH signal, provided at the beginning of every packet, is provided to the clock input of flip-flop  61 . The 9-bit wide Q output of flip-flop  61  is also provided to one input of a second comparator  64 . The other input of comparator  64  is a lower limit value, L, also nine bits. Comparator  64  provides a 1 output when the clock count output is greater than L, but a 0 otherwise. The output of comparator  64  is provided to the second input of 4-input AND gate  63 . 
         [0029]    The gated input clock is provided to the input of a second counter, counter  2   65 , that has an eight bit wide count output. The PSYNCH signal is provided to the reset input of counter  2   65 . The counter  2   65  output is provided to the D input of an 8-bit wide flip-flop  66  (eight flip-flops in parallel, each receiving one bit line of the counter  2   65  output) and to one input of a third comparator  67 . The other input of comparator  67  is a packet size value, PS, also eight bits. Comparator  67  provides a 1 output when the count output of counter  2   65  is less than PS+1, but a 0 output otherwise. The output of comparator  65  is provided to the third input of 4-input AND gate  63 . The 8-bit wide Q output of flip-flop  66  is the packet count output, being the number of valid data bits counted in a packet. The PSYNCH signal is provided to the clock input of flip-flop  66 . The 8-bit wide Q output of flip-flop  66  is also provided to one input of a fourth comparator  68 . The other input of comparator  68  is the value PS. Comparator  68  provides a 1 output when the packet count output is equal to PS, but a 0 otherwise. The output of comparator  68  is provided to the fourth input of 4-input AND gate  63 . 
         [0030]    In operation, counter  1   60  of the Packet Counter  48  begins counting read clock cycles immediately after the PSYNCH signal is asserted, and provides the current count value, in bytes, as it is counting as a 9-bit output. Comparator  62  monitors this output, and so long as it remains below the higher limit value, H, asserts a 1 to its input to AND gate  63 . When the next PSYNCH signal is asserted, signaling the end of the current packet and the beginning of the next packet, flip-flop  61  provides the count value, again, in bytes, at its D input, being the final count of clock cycles in the packet, at its Q output. This is the clock count output, and it can be seen that it is a value that is updated once every packet. Comparator  64  monitors the clock count output, and once it goes above the lower limit value, L, asserts a 1 to its input to AND gate  63 . The value L is provided by the designer or user, and is determined in accordance with system requirements and/or limitations. 
         [0031]    Counter  2   65  begins counting gated data bits immediately after the PSYNCH signal is asserted, and provides the current count value, in bytes, as it is counting as a 8-bit output. Comparator  67  monitors this output, and so long as it remains below or equal to the packet size value, PS, asserts a 1 to its input to AND gate  63 . For example, in MPEG-2 systems the value of PS will usually be 188. When the next PSYNCH signal is asserted, signaling the end of the current packet and the beginning of the next packet, flip-flop  66  provides the count value, again, in bytes, at its D input, being the final count of valid data bits in the packet, at its Q output. This is updated once every packet. Comparator  68  monitors the valid data byte count output, and if it is equal to PS, asserts a 1 to its input to AND gate  63 . In this way, comparator  67  continuously monitors the valid bit count, and if it ever exceeds the architected size of a packet, immediately asserts a 0, thereby blocking the assertion of the packet valid signal, thus signaling that an error has occurred in the receipt of the current packet. Likewise, comparator  68  monitors the final count of valid data bytes, and if this count is anything other than the architected size of a packet, asserts a 0, thereby blocking the assertion of the packet valid signal, thus signaling that an error has occurred in the receipt of the current packet. It will be appreciated that for final counts of greater than PS, this action by comparator  68  will be redundant to that of comparator  67 , so that its essential function is to supplement the function of comparator  67  to block the packet valid signal when the final packet count is less than the architected value. 
         [0032]    The specific timing of the controls for the operation of the Packet Synchronizer  40  of  FIG. 4  will now be described, with reference to  FIGS. 7 and 8 .  FIG. 7  is a state diagram showing the conditions for a write operation to FIFOs  44  and  46  ( FIG. 4 ), i.e., the conditions defining the control of switch SW 1  ( FIG. 4 ). In the figure, the following Write Rules apply to the paths in the state diagram: 
         [0033]    a: if not (packet valid  1 ) 
         [0034]    b: if (packet valid  1 ) and PSYNCH occurs 
         [0035]    c: if not (packet valid  2 ) 
         [0036]    d: if (packet valid  2 ) and PSYNCH occurs. 
         [0000]    In this terminology, packet valid  1  means that the packet valid signal ( FIG. 6 ) is being asserted during a packet that is to be written to FIFO  1   44 . Likewise, packet valid  2  means that the packet valid signal is being asserted during a packet that is to be written to FIFO  2   46 . Reset byte counter occurs when the PSYNCH signal is asserted during the start of the next new packet. With this understood, it can be seen that Write Rule a, above, means keep on writing to FIFO  1 . Write Rule b means complete writing to FIFO  1  and Jump to FIFO  2  for the next packet writing. Write Rule c means keep on writing to FIFO  2 . Write Rule d means complete writing to FIFO  2  and Jump to FIFO  1 . Thus, the Packet Synthesizer  40  alternates, packet by packet, between writing to FIFO  1   44  and to FIFO  2   46 , with alternations being signaled by the PSYNCH signal, so long as the packet valid signal is asserted. 
         [0037]      FIG. 8  is a state diagram showing the conditions for a read operation from FIFOs  44  and  46  ( FIG. 4 ), i.e., the conditions defining the control of switch SW 2  ( FIG. 4 ). In the figure, the following Read Rules apply to the paths in the state diagram: 
         [0038]    a: if (not(packet valid  1 ) and not(packet valid  2 )) 
         [0039]    b: if packet valid  1   
         [0040]    c: if read packet  1  complete and not (packet valid  2 )) 
         [0041]    d: if packet valid  2   
         [0042]    e: if (read packet  2  complete and not(packet valid  1 )) or reset 
         [0043]    f: if packet valid  1   
         [0044]    g: if packet valid  2 . 
         [0000]    In this terminology, read packet  1  complete means that the reading of a packet from FIFO  1   44  is complete, while read packet  2  complete means that the reading of a packet from FIFO  1   44  is complete, which are determined from the state of the write packet valid  1  and write packet valid  2  signals, respectively. This is signaled by monitoring a count of the read clock, and signaling complete when a number equal to the packet size (usually 188 bytes in MPEG-2) occurs. With this understood, it can be seen that Read Rule a, above, means that there is no valid data to be read, therefore wait. Read Rule b means start reading packet  1 , since that packet has been completely written. Read Rule c means that there is no data to be read, therefore wait. Read Rule d means start reading packet  2 , since that packet has been completely written. Read Rule e means that there is no valid data to be read, therefore wait. Read Rules f and g show the “ping pong” alternating reading between FIFO  1  and FIFO  2  when data is coming in and going out in a continuously synchronous fashion. In this condition, the Packet Synthesizer  40  alternates, packet by packet, between reading from FIFO  1   44  and to FIFO  2   46 , in opposite phase with the writing to those FIFOs, with alternations being signaled by the PSYNCH signal, so long as the packet valid signal is asserted for the packet in that FIFO. 
         [0045]    Thus, the present invention provides a synchronizer for MPEG-2 TS that uses a substantially instantaneous response PLL. It requires only two packet length buffers, and no dedicated analog PLL is necessary. 
         [0046]    Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be appreciated that, while the memory units employed in the preferred embodiment disclosed herein are FIFOs, because of the precision available in applying the principles of the present invention, other types of memories may be employed in embodiments of the invention, as well.