Abstract:
A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to Static Random Access Memories (&#34;SRAMs&#34;). In particular, it relates to a circuit which can be incorporated into a SRAM to simplify the detection of power supply short circuits within arrays of SRAM memory cells. 
     2. Description of the Relevant Art 
     A generic SRAM memory cell is shown in FIG. 1a. The construction and operation of such cells is known. In the illustrated cell, transistor T 1  is the driver and transistor T 3  the load for an inverter that is cross-coupled to a second inverter formed from transistors T 2  and T 4 , the two inverters forming a storage flip-flop. When transistor T 2  is on and transistor T 1  is off, output Q is a logic 1 (herein, +5 V). With the row-select line low (0 V), transistors T 5  and T 6  are off, and the cell is isolated from both bit lines. When the memory cell is read, as soon as the row-select line goes high (+5 V), transistors T 5  and T 6  couple the bit lines to the cell and output Q appears on bit line D. 
     As shown in FIG. 1b, a sense amplifier is connected to the bit line to provide output buffering, and the proper logic level appears on the sense output line. In a write operation, the selected row of cells is connected to the bit lines, and Q or Q is set or reset by a logic 1 (+5 V) placed on bit line D or D by the write amplifiers while a logic 0 (0 V) is placed on the complement bit line. In this SRAM with nondestructive readout, the state of the flip-flop persists as long as power is supplied to the chip, and it is not altered by the read operation. It should be understood that an SRAM chip will comprise many thousands of such memory cells. 
     In normal operations, transistors T 1  and T 2  have a certain amount of capacitance, shown in FIG. 1a as capacitors C 1  and C 2 . If V dd  were shorted to V ss , due to a manufacturing error, a certain amount of time would be required before the charge present on either C 1  and C 2  (the nature of the flip-flop requires that either Q or Q be high (+5 V), but not both) is drained through transistors T 3  and T 4  to V ss . This discharge time is often large in comparison to the amount of time required to access the memory cell and the frequency of such access. It is therefore quite possible to read data several times from a cell with such a short circuit before the charge is dissipated sufficiently to detect the presence of the short. 
     This long dissipation time makes testing for this type of short circuit a long, tedious and costly process. A method and/or an apparatus which can speed the process of testing for and detecting such power supply short circuits is needed. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method to test an array of SRAM memory cells for power supply short circuits. It also provides a circuit for detecting such short circuits in conjunction with the testing method. According to one embodiment, each row of memory cells is individually activated and scanned. Each row select line is coupled to a common current sense line, which in turn is coupled to a current sense circuit. In operation, each successive row of memory cells is activated. If the voltage supply (V dd ) for that row of cells is shorted to ground (V ss ) or any lower voltage for any reason a current will flow through the current sense line and will be detected by the current sense circuit. 
     The circuit which selects individual rows of memory cells for testing also provides a means for uniquely identifying the memory chip. Certain fuses within the select circuit can be selectively blown, the pattern of open fuses providing the identification information. 
     The present invention will now be described in detail with reference to the following figures. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1a shows a typical SRAM memory cell; 
     FIG. 1b shows the write and sense amplifiers coupled to the cell; 
     FIG. 2 shows the current sense row selector circuit; 
     FIG. 3 is a detailed schematic of the row selector circuit; 
     FIG. 4 is a detailed schematic of the current sensing circuit. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1a shows how each prior art SRAM memory cell is individually coupled to a row select line and to V dd , herein, by example only, +5 V. In the present invention, as shown in FIG. 2, the SRAM cell receives V dd  &#39;, V dd  being first coupled to R 1  which resistor limits the amount of current which can flow through the voltage supply lines to the memory cell. Each cell is coupled to a row line, shown in FIG. 2 as row lines N and N+1. As the particular workings of the memory cells is not relevant to an understanding of the present invention, the cells are not illustrated in FIG. 2. For the purposes of this description, it suffices to state that each cell is coupled to the current sense row selector circuit shown in FIG. 2 by means of the memory cell&#39;s row select line and its V dd  &#39; voltage supply line. There can be any arbitrary number of rows of memory cells. 
     Row line N and memory cell supply V dd  &#39;N are coupled respectively to the gates of PMOS transistors T 8  and T 9 . Similarly, the gates of transistors T 10  and T 11  are coupled respectively to memory cell supply V dd  &#39;N+1 and row line N+1. 
     In this type of SRAM array, voltage supply V dd  &#39; to the cell can be inadvertently shorted to either V ss  or, possibly, to a row line which is active low (0 V) as a result of a manufacturing defect. Such short circuits can be detected by using this invention in a test mode. When the present invention is used in its test mode, each consecutive row of memory cells is scanned. When a row becomes active (row N, for example), PMOS transistor T 8  turns on. If V dd  &#39; is shorted low for any reason, transistor T 9  will also turn on. Current will then flow through current sense line 20 (FIG. 2) to current sense circuit 30. The current sense circuit, as will be explained, detects even small current flows through the current sense line when the SRAM is being tested. It outputs a logic signal to indicate if such a flow is detected. 
     A detailed schematic of the row select circuit is shown in FIG. 3. As discussed, transistors T 8  and T 9 , whose gates are respectively coupled to the row select signal and V dd  &#39;, the isolated memory matrix supply voltage, act to detect shorts in the matrix between V dd  &#39; and either V ss  or the row select signal, which is active low. This is done by selecting a particular row, whereby that row&#39;s select signal goes low and transistor T 8  turns on. It will be obvious to those skilled in the art that selection of a particular row occurs in response to commands received from a computer to which the SRAM is coupled. Further, it is to be understood that each row select line is coupled to the current detector circuit 30 in response to signals generated by the computer coupled to the SRAM. If V dd  &#39; is low, the result of a short circuit, transistor T 9  will turn on and current will flow along current sense line 20 to current sensing circuit 30 (FIG. 2) during the supply short circuits test mode. Transistor T 12  is a pull-up transistor for the row select signal which maintains a high voltage level of V dd  for nonselected row select lines. 
     Another feature of the row select circuit is that it provides a circuit ID encoding scheme. This is done in a similar fashion to the voltage supply short circuit test. The row select signal selects the appropriate row. If fuse F 1  is not open, current will flow through the IDSENS signal line. There is one fuse per row of memory cells and it can be blown or not blown to encode the chip lot and wafer number or other desired information. Resistors R 2 , R 3  and R 4  are used to isolate the memory cell top supply V dd  &#39; from the external supply V dd . Doing so limits the current that can flow if a short circuit occurs to approximately 1 ma. If fuse F 2  opens, the flow of current stops completely. 
     A detailed schematic drawing of current sensing circuit 30 is shown in FIG. 4. The MODE signal is used to turn the sensing circuit on during test mode. In the test mode, node A is set at V dd  -2 V be  (transistor T 22  and T 24  providing the requisite 2 V be  drops) as a reference voltage level for the gate of PMOS transistor T 26 . T 26  serves as a cascode device coupled to the bottom rail of circuit 30. 
     When not in the matrix voltage supply short circuit test mode, the MODE signal is low. Transistor T 23  is off and transistor T 21  is on, holding node A at the supply voltage V dd . In turn, transistor T 26  turns off, allowing resistor R 1  to hold node B low. Transistor pairs T 29  /T 31 , T 32  /T 34  and T 35  /T 37  act as inverters so when node B is low, the output (`OUT`) of the circuit is high. 
     In the test mode, the MODE signal is high. This turns off transistors T 21  and T 25  and turns transistor T 23  on. With transistor T 23  on, node A is biased to V dd  -2V be , the voltage drop through T 22  and T 24 . Node B will change voltage as current modulation occurs along the current sense line 20 signal in test mode. When current is sensed, node B will rise, tripping the three inverters that drive the OUT output signal. The beta ratio for the first inverter (T 29  /T 31 ) is low to allow node B, which has a small voltage swing, to trip the three inverters. Bipolar transistors T 27  and T 28  are used to clamp the low level voltage to a certain minimum on the current sense line 20 signal line to prevent SENSLINE voltage from coupling around. Transistor T 26  will clamp the high level of the current sense line 20 signal to V dd  -2V be  +V tp . 
     Although the present invention has been described in the specific environment of a BiCMOS SRAM, its utility is not limited thereto. Its use in any type of SRAM or even in a dynamic random access memory is easily envisioned. Therefore, this application should not be read in a limited sense.