Abstract:
A current squaring cell is provided for producing an output current that correlates to the square of an input signal current. The current squaring cell comprises a first circuit portion, which receives a first tail current that is positively proportional to the input signal current, and a second circuit portion, which connects to the first circuit portion and receives a second tail current that is negatively proportional to the input signal current.

Description:
RELATED APPLICATION  
   This application contains subject matter related to U.S. application Ser. No. 11/166,089 now U.S. Pat. No. 7,259,620, Ser. No. 11/166,279 now U.S. Pat. No. 7,262,661 and Ser. No. 11/206,070 now U.S. Pat. No. 7,268,608, filed Jun. 27, 2005, Jun. 27, 2005 and Aug. 18, 2005, respectively of Min Z. Zou, the disclosures of which are hereby incorporated in the present disclosure. 
   TECHNICAL FIELD 
   The subject matter presented herein relates to a circuit architecture for squaring an input current. 
   BACKGROUND 
   A circuit for current multiplication is illustrated in  FIG. 1 . Based on translinear loop equations, the following relationships hold:
 
 V   be1   +V   be2    +V   be3   =V   be4   +V   be5   +V   be6 ,  (1)
 
 I   c1   *I   c2   *I   c3   =I   c4   *I   c5   *I   c6 , and  (2)
 
 I   out   =I   c6   =I   c1   *I   c2   /I   c5   (3)
 
where V be1  represents the voltage measured between the anode terminal and cathode of a first diode  110  (Q 1 ); V be2  represents the voltage between the base and emitter of a first transistor  120  (Q 2 ); V be3  represents the voltage between the base and emitter of a second transistor  130  (Q 3 ); V be4  represents the voltage between the anode and the cathode of a second diode  140  (Q 4 ); V be5  represents the voltage between the base and emitter electrode of a third transistor  150  (Q 5 ); and V be6  represents the voltage between the base and emitter of a fourth transistor  160  (Q 6 ). In addition, I c6  represents the current measured at the cathode of the first diode  110  (Q 1 ); I c2  represents the current at the collector electrode of the first transistor  120  (Q 2 ); I c3  represents the current at the collector of the second transistor  130  (Q 3 ); I c4  represents the current at the cathode of the second diode  140  (Q 4 ); I c5  represents the current at the collector of the third transistor  150  (Q 5 ); and I c6  represents the current at the collector of the fourth transistor  160  (Q 6 ).
 
   Although the circuit presented in  FIG. 1  produces an output current I out  that is a multiple of its input current, its output current is not necessarily a squared input current. Having a circuit that produces a squared input current has a number of practical applications. For example, a logarithmic amplifier for measuring the power of an RF signal often requires that the amplifier exhibit conformity to the known true square law over a broad dynamic range and be relatively independent of temperature. The subject matter described herein presents circuitry having these characteristics. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The inventions claimed and/or described herein are further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein: 
       FIG. 1  (Prior Art) depicts a circuit for current multiplication; 
       FIG. 2  depicts an exemplary construct of a current squaring cell, according to an embodiment of the present invention; 
       FIG. 3  depicts a first embodiment of a current squaring cell according to the present invention; 
       FIG. 4  depicts an exemplary circuit implementation of the first embodiment of current squaring cell; 
       FIG. 5  depicts a second embodiment of a current squaring cell; 
       FIG. 6  depicts an exemplary circuit implementation of the second embodiment; 
       FIGS. 7A-7D  provide plots of current waveforms at different locations of a current squaring cell with respect to an input signal at a rate of 200 MHz; and 
       FIGS. 8A-8D  provide plots of current waveforms at different locations of a current squaring cell with respect to an input signal at a rate of 2 GHz. 
   

   DETAILED DESCRIPTION 
     FIG. 2  depicts an exemplary circuit construct of a current squaring cell  200 , according to an embodiment of the present invention. The circuit construct  200  receives, as an input, a current i  210  and produces, as an output, a current I out    260  corresponding to a function of the squared input current or f(i 2 ). The circuit construct  200  comprises a first circuit  220 , having a first tail current  240  of a magnitude I B +i, and a second circuit  230 , having a second tail current  250  of a magnitude I B −i. In this construct, the current I B  represents a constant current source such as a DC quiescent current and i represents a dynamic input current signal. This is illustrated in  FIGS. 7A and 8A , where the constant line at the level of 1.0 mA represents a constant current source I B  and the waveforms in these figures represent the input current signal i. The first circuit  220  and the second circuit  230 , the content of which will be described later, are interconnected as shown. 
     FIG. 3  depicts a current squaring cell  200  according to a first embodiment  300  of the present invention. Embodiment  300  comprises a first circuit  320 , having a first tail current  340  of a magnitude I B +i, and a second circuit  330 , having a second tail current  350  of a magnitude I B −i, where an output current, I out    360 , is produced by the second circuit  330  and is a function of squared input current i at input  310 . 
     FIG. 4  depicts an exemplary circuit implementation of embodiment  300  of current squaring cell  200 . Circuit  320  of embodiment  300  includes a first component  410  (Q 1 ), which may be realized using a diode having its anode terminal connected to a source of reference voltage Vcc and its cathode terminal connected to the tail current  340  of I B +i, as shown in  FIG. 4 . Alternatively, the component  410  may be realized using a transistor (not shown) having its base electrode and collector electrode coupled together to connect to the reference voltage Vcc source and its emitter electrode connected to the tail current  340 . 
   Circuit  330  of embodiment  300  comprises a first transistor  420  (Q 2 ), a second transistor  430  (Q 3 ), a second component  440  (Q 4 ), a third transistor  460  (Q 6 ), and a fourth transistor  450  (Q 5 ) interconnected as shown. Similarly, the second component  440  may be realized using either a diode (as shown) or a transistor. When a diode is utilized, its anode terminal may serve as the positive terminal of the second component  440  and its cathode terminal may serve as the negative terminal of the second component  440 . When a transistor is utilized, its base electrode and its collector electrode are coupled together connecting to the reference voltage source Vcc and its emitter electrode serve as the negative terminal of the second component  440 . 
   The base electrode of the first transistor  420  is connected to the negative terminal of the first component  410 . The collector electrode of the first transistor  420  is connected to the reference voltage source Vcc and the emitter electrode of the first transistor  420  is connected to both the tail current source  350  of I B −i and the base electrode of the second transistor  430 . The collector electrode of the second transistor  430  is connected to the negative terminal of the second component  440 , whose positive terminal is connected to the reference voltage source Vcc. 
   The emitter electrode of the second transistor  430  is coupled with the emitter electrode of the fourth transistor  460  and together are connected to a third tail current  470  that has a constant magnitude of 2*I B . 
   The base electrode of the third transistor  450  is connected to the negative terminal of the second component  440 . The emitter electrode of the third transistor  450  is coupled with the base electrode of the fourth transistor  460  and together connecting to a fourth tail current source  480  that has a constant magnitude of I B . The collector electrode of the third transistor  450  is connected to the source of reference voltage Vcc. The collector electrode of the fourth transistor  460  serves as a terminal for the output current  360  I out . 
   The output current I out  is a function of the squared input current i. This can be shown from the translinear loop equations as follows. Since the following equalities hold:
 
 V   be1   +V   be2   +V   be3   =V   be4   +V   be5   +V   be6 ,  (4)
 
 I   c1   *I   c2   *I   c3   =I   c4   *I   c5   *I   c6 , and  (5)
 
 I   out   =I   c6   =I   c1   *I   c2   /I   c5   (6)
 
where V be1  represents the voltage between the positive and the negative terminals of component  410  (Q 1 ); V be2  represents the voltage between the base electrode and the emitter electrode of the first transistor  420  (Q 2 ); V be3  represents the voltage between the base electrode and the emitter electrode of a second transistor  430  (Q 3 ); V be4  represents the voltage between the positive and negative terminals of component  440  (Q 4 ); V be5  represents the voltage between the base electrode and the emitter electrode of a third transistor  450  (Q 5 ); and V be6  represents the voltage between the base electrode and the emitter electrode of a fourth transistor  460  (Q 6 ). In addition, I c1  represents the current at the negative terminal of component  410  (Q 1 ); I c2  represents the current at the collector electrode of the first transistor  420  (Q 2 ); I c3  represents the current at the collector electrode of the second transistor  430  (Q 3 ); I c4  represents the current at the negative terminal of the second component  440  (Q 4 ); I c5  represents the current at the collector electrode of the third transistor  450  (Q 5 ); and I c6  represents the current at the collector electrode of the fourth transistor  460  (Q 6 ). Since I c1 =I B +i, I c2 =I B −i, and I c5 =I B , by substitution, one can derive the following:
 
 I   out =( I   B   +i )*( I   B   −i )/ I   B =( I   B   −i   2 )/ I   B   =I   B   −i   2   /I   B .  (7)
 
That is, the output current of the second circuit  330  is a function of squared input current i. In addition, when I B  is a zero-TC current source, the output current I out  is also independent of temperature.
 
   The above characteristics hold when the frequency of the input signal i is within a certain frequency range. When frequency increases, the negative terminal of the first component  410  (Q 1 ) connected to the first tail current (I B +i) and the emitter electrode of the first transistor  420  (Q 2 ) connected to the second tail current (I B −i) may observe different impedances. Consequently, the current flow to component  410  (I c1 ) may differ from the current flow to the first transistor  420  (I c2 ) in terms of both amplitude and in phase delays. The higher the frequency, the larger the difference may be. This can be seen from the following. The input signal i may generally take a form of i=I 0 *cos(ωt) and the expressions of I c1 =I B +i and I c2 =I B −i may then be expanded as:
 
 I   c1   =a*{I   B   +I   0 *cos(ω t+Φ   1 )},  (8)
 
 I   c2   =b*{I   B   +I   0 *cos(ω t+Φ   2 )},  (9)
 
where Φ 1  and Φ 2  represent the phase of the signals.
 
   As a consequence, the product of I c1  and I c2  may include both a fundamental frequency as well as an additive DC current component which is a function of both the amplitude of the input signal i (I 0 ) and the phase difference (Φ 1 −Φ 2 ) occurring at a certain frequency. That is,
 
 I   c1   *I   c2   =a*b *( I   2   B   −i   2 )+ c*i +additive DC current ( I   0 , Φ 1 −Φ 2 )  (10)
 
   In addition to this discrepancy, the assumed condition I c3 =I c4  may not hold at a high frequency. When the frequency of the input signal i is increased, the current observed at the negative terminal of the second component  440  may be delayed compared with the current at the collector electrode of the second transistor  430 . This may also result in bleeding of a signal at the fundamental frequency into the output signal  360 . 
   Furthermore, when the input signal i has a magnitude that is comparable to that of I B , component  410  (which has the first tail current I B +i) and the first transistor  420  (whose emitter electrode is connected to the second tail current I B −i) may behave quite differently during both positive and negative cycles of the input current i. This may be due to the difference in resistance measured between the negative terminal of the first component  410  and the emitter electrode of the first transistor  420 . 
   Although embodiment  300  may produce an output current  360  as a function of the squared input current i, it may not behave as such when the above conditions no longer hold in high frequency input situations. In situations where the input current signal is of high frequency, another embodiment  500  of current squaring cell  200 , described below, may be employed. 
   Referring to  FIG. 5 , embodiment  500  comprises a first circuit  510 , having a first tail current  540  of magnitude I B +i and a first output current  515  I +   out , a second circuit  530 , having a second tail current  545  of magnitude I B −i and a second output current  535  I −   out , and a sum circuit  550 . The first circuit  510  receives an input current signal i  505  and produces the output current I +   out , which is a function of the squared input current signal i. Similarly, circuit  530  receives an input current signal i  505  and produces output current I −   out , which is a function of the squared input current signal i. 
   The sum circuit  550  receives both the first output current  515  I +   out  of the circuit  510  and the second output current  535  I −   out  of circuit  530  and produces an output current  560  I out . The output current  560  may be represented as I out =g(I 30   out , I −   out ) and the function g may be designed so that the output current  560  I out  remains a function of the squared input current signal, e.g., g(I +   out , I −   out )=I +   out +I −   out  which is the sum of the two inputs. 
   Circuit  510  and circuit  530  may be coupled through connections  520  and  525 . Circuit  510  and circuit  530  may be realized using symmetric circuitry, each of which has two connecting terminals. For example, circuit  510  has a first connecting terminal  520 - a  and a second connecting terminal  525 - a.  Similarly, circuit  530  has a first connecting terminal  525 - b  and a second connecting terminal  520 - b.  When circuit  510  is coupled with circuit  530 , the first connecting terminal  520 - a  of circuit  510  is coupled with the second connecting terminal  520 - b  of circuit  530  and the second connecting terminal  525 - a  of circuit  510  is coupled with the first connecting terminal  525 - b  of circuit  530 . This cross connection is shown in  FIG. 5  and is made more clear in  FIG. 6 . 
     FIG. 6  depicts an exemplary implementation of circuit  510  and circuit  530 . The left portion in  FIG. 6  shows an exemplary circuitry that implements circuit  510 , the right portion of  FIG. 6  shows an exemplary circuitry that implements circuit  530 . In this embodiment, the internal construct of circuit  510  is a mirror image of the construct of circuit  530  except that the tail current of circuit  510  (I B +i) is different from the tail current of circuit  530  (I B −i). 
   Circuit  510  comprises a first component  645  (Q 3b ), a first transistor  640  (Q 4b ), a second transistor  635  (Q 5b ), a third transistor  625  (Q 6b ), a second component  630  (Q 7b ), a fourth transistor  620  (Q 9b ), a fifth transistor  610  (Q 8b ), and a sixth transistor  605  (Q 10b ), interconnected as shown. The first and/or the second components  645  and  630  may be realized using a diode (as shown in  FIG. 6 ) with its anode terminal serving as the positive terminal and its cathode terminal serving as the negative terminal of first and second components  645  and  630 . Alternatively, a transistor may be employed to realize the first and/or second components  645  and  630  (not shown), where the base electrode and the collector electrode of such a transistor are coupled together to serve as the positive terminal and its emitter electrode serves as the negative terminal of the first and/or second components  645  and  630 . 
   The positive terminal of the first component  645  is connected to a reference voltage Vcc source and the negative terminal of the first component  645  is connected to the collector electrode of the first transistor  640 . The emitter electrode of the first transistor  640  is connected to the first tail current (I B +i)  540  as well as the base electrode of the second transistor  635 . The collector electrode of the second transistor  635  is connected to the negative terminal of the second component  630  whose positive terminal is connected to the reference voltage Vcc  600 . The emitter electrode of the second transistor  635  is coupled with the emitter electrode of the third transistor  625  and together connected to a third tail current  650  with a current strength of 2*I B . The third transistor  625  is connected with the fourth transistor  620  in a serial fashion with the collector electrode of the third transistor  625  coupled with the emitter electrode of the fourth transistor  620 . The collector electrode of the fourth transistor  620  corresponds to the first output current  515  I +   out . 
   The fifth transistor  610  and the sixth transistor  605  are connected in a serial manner between the reference voltage Vcc  600  and a fourth tail current  615  with a current strength of I B . As shown in  FIG. 6 , the collector electrode of the fifth transistor  610  is coupled with the emitter electrode of the sixth transistor  605 , whose collector electrode is connected to the reference voltage Vcc  600 . The base electrode of the fifth transistor  610  is connected to the collector electrode of the second transistor  635  and the base electrode of the sixth transistor  605  is coupled both with its own collector electrode and with the base electrode of the fourth transistor  620 . 
   Circuit  530  comprises a third component  660  (Q 3a ), a seventh transistor  655  (Q 4a ), an eighth transistor  670  (Q 5a ), a ninth transistor  675  (Q 6a ), a fourth component  665  (Q 7a ), a tenth transistor  680  (Q 9a ), an eleventh transistor  695  (Q 8a ), and a twelfth transistor  690  (Q 10a ). As mentioned, circuit  530  is a mirror image of circuit  510 . The third component  660  corresponds to the first component  645  and the fourth component  665  corresponds to the second component  630 . Similarly, the seventh transistor  655  corresponds to the first transistor  640  except that the emitter of the seventh transistor is connected to the second tail current (I B −i)  545 ; the eighth transistor  670  corresponds to the second transistor  635 ; the ninth transistor  675  corresponds to the third transistor  625 ; the tenth transistor  680  corresponds to the fourth transistor  620 ; the eleventh transistor  695  corresponds to the fifth transistor  610 ; the twelfth transistor  690  corresponds to the sixth transistor  605 . The corresponding parts of circuit  510  and circuit  530  are also similarly connected. 
   Circuit  510  and circuit  530 , the contents of which are described later, are interconnected as shown. The collector electrode of the first transistor  640  (which also connects to the negative terminal of the first component  645 ) serves as the first connection terminal  520 - a  of circuit  510  ( FIG. 5 ). The base electrode of the first transistor  640  serves as the second connection terminal  525 - a  of circuit  510 . Similarly, the collector electrode of the seventh transistor  655  (which also connects to the negative terminal of the third component  660 ) serves as the first connection terminal  525 - b  of circuit  530  and the base electrode of the seventh transistor  655  serves as the second connection terminal  520 - b  of circuit  530 . 
   The exemplary implementation circuitry  500  has the following characteristics, referring to its translinear loop equations:
 
 V   Q3a   +V   Q4b   +V   Q5b   =V   Q7b   +V   Q8b   +V   Q6b ,  (11)
 
 V   Q3b   +V   Q4a   +V   Q5a   =V   Q7a   +V   Q8a   +V   Q6a ,  (12)
 
 I   Q3a   *I   Q4b   *I   Q5b   =I   Q7b   *I   Q8b   *I   Q9b ,  (13)
 
 I   Q3b   *I   Q4a   *I   Q5a   =I   Q7a   *I   Q8a   *I   Q9a ,  (14)
 
That is, circuit  510 , when considered together with the third component  660 , the seventh transistor  655 , and the second tail current (I B −i)  545 , has the same properties as the circuit shown in  FIG. 4 . Similarly, circuit  530 , when considered together with the first component  645 , the first transistor  640 , and the first tail current (I B +i)  540 , has the same properties as the circuit shown in  FIG. 4 . Therefore, the first output current  515  I +   out  and the second output current  535  I +   out  are both a function of the squared input current i.
 
   The sum circuit  550  may linearly combine the first and second output currents, for example, using a summation. Such a linear combination of the first output current  515  I +   out  of circuit  510  and the second output current  535  I −   out  of circuit  530  produces the output current  560  I out , which is also a function of the squared input current signal i. 
   As can be seen, in the second embodiment  500  of current squaring cell, by using balanced or symmetric current squaring cells, the additive DC current and the signal at the fundamental frequency at the first output current I +   out  and the second output current I −   out , although having the same amplitudes, are out of phase with respect to each other. The impact of high frequencies on the additive DC current and the signal at the fundamental frequency are canceled out when the first output current I +   out  and the second output current I −   out  are combined at the sum circuit  550 . In this way, the expected relationship under the square law is maintained even under high frequency situations. Notably, in the exemplary implementation as shown in  FIG. 6 , the first tail current source (I B +i)  540  and the second tail current source (I B −i)  545  are loaded by the same impedance. In addition, the impact of positive and negative cycles (that exist when the amplitude of input current i is comparable to that of I B ) on circuit  510  and circuit  530  is also canceled out when I +   out  and I −   out  are combined. 
   In addition, it is known that the square law relationship, as discussed above, holds when the effect of limited early voltages is assumed to be negligible. This assumption, however, may not hold when input signal frequency is high, in which case a voltage may not arise high enough in a short period of time to avoid the early voltage impact. The second embodiment  500  of current squaring cell also exhibits the characteristic of canceling such early voltage impact. This is due to the additional use of the fourth and the sixth transistors  620  and  605  in circuit  510  as well as the tenth and the twelfth transistors  680  and  690  in circuit  530 . 
   In the exemplary circuit implementation shown in  FIG. 4 , assuming V ce1 =1*V be , where V ce1  represents the voltage between the collector and emitter electrodes of the first electronic component (Q 1 ) (in the circuit shown, it is between the anode terminal and cathode terminal of a diode), the following relationships exist:
 
 V   ce1 =1 *V   be ;  (15)
 
 V   ce2 =2 *V   be ;  (16)
 
 V   ce3 =2 *V   be ;  (17)
 
 V   ce4 =1 *V   b ;  (18)
 
 V   ce5 =2 *V   be ;  (19)
 
where the voltage V ce6  between the collector and emitter electrodes of Q 6  (or the fourth transistor  450 ) depends on output loading. However, based on part of the circuit as shown in  FIG. 6 , we now have:
 
 V   ce3b =1 *V   be ;  (20)
 
 V   ce4a =1 *V   be ;  (21)
 
 V   ce5a =2 *V   be ;  (22)
 
 V   ce7a =1 *V   be ;  (23)
 
 V   ce8a =1 *V   be ;  (24)
 
 V   ce6a =2 *V   be   (25)
 
where V ce3b  represents the voltage between the two terminals of component Q 3b  (the first component  645 ), V ce4a  represents the voltage between the collector and emitter electrodes of Q 4a  (the seventh transistor  655 ), etc. As can be seen, within the translinear loop formed by Q 3b , Q 4a , Q 5a , Q 7a , Q 8a , and Q 6a , corresponding components pairs (Q 3b -Q 7a , Q 4a -Q 8a , and Q 5a -Q 6a ) all have matched voltages. Notably, the voltage V ce6  now no longer depends on the output loading. Therefore, the impact of limited Early voltage may be eliminated.
 
     FIGS. 7A-7D  provide plots of current measurements made at different locations of the current squaring cell circuit shown in  FIG. 6  when the input signal i has a frequency of 200 MHz.  FIG. 7A  shows the waveforms of the first tail current (I B +i) and the second tail current (I B −i), where I B  is shown at a constant level of 1.0 mA and the amplitude of the input current signal i is around |0.5 mA|. 
     FIG. 7B  shows that the current flowing through the fourth component  665  and the current measured at the collector electrode of the eighth transistor  670  are almost identical when the frequency is 200 MHz. In  FIG. 7B , the first plotted curve (marked by a square) represents the ratios of the current flowing through the fourth component  665  to that of the eighth transistor  670  and it can be seen that the ratios on the curve are quite close to 1.0. Similarly, the second plotted curve (marked by a diamond shape) represents the ratios of the current flowing through the second component  630  to that of the second transistor  635  and it can be seen that the ratios on the curve are also quite close to 1.0. 
     FIG. 7C  shows two plotted curves representing the amplitudes of the first output current I +   out  and that of the second output current I −   out , respectively. It can be seen that at a low frequency, the two output currents present similar circuit behavior, having substantially the same amplitudes and phases.  FIG. 7D  shows a curve representing the combined output current I out  that is a sum of the two output currents and is a function of the squared input current signal. 
     FIGS. 8A-8D  provide plots of current measurements made at different locations of the current squaring cell circuit shown in  FIG. 6  when the input signal i has a high frequency of 2 GHz.  FIG. 8A  shows the curves representing both the first tail current (I B +i)  540  and second tail current (I B −i)  545 . 
     FIG. 8B  shows two curves. The one marked with a square represents ratios of the current flowing through the fourth component  665  to that of the eighth transistor  670 . It can be seen that most of the ratio values along the first curve are not close to 1.0. That is, at a high frequency of 2 GHz, the currents measured at the positive terminal of the fourth component  665  and at the collector electrode of the eighth transistor  670  no longer have the same phase and amplitude with respect to a given time. The second curve (marked by a diamond shape) represents ratios of the current flowing through the second component  630  to that measured at the collector electrode of the second transistor  635 . Similarly, at a high frequency of 2 GHz, the current measured at the positive terminal of the second component  630  and that measured at the collector electrode of the second transistor  635  differ in phases and amplitudes. 
     FIG. 8C  shows two plotted curves representing the amplitudes of the first output current I +   out  and that of the second output current I −   out , respectively. It can be seen that at a high frequency, circuit  510  and circuit  530  behave quite differently because of the impact of positive and negative cycles of the input current signal i. For example, the impact of the I B +i is quite different from the impact of I B −i. This is especially evident from the observation that neither of the first output current I +   out  or the second output current I −   out  maintains a proper waveform as a function of the input waveform as shown in  FIG. 8A . 
     FIG. 8D  shows a curve representing the combined output current I out  that is a sum of the two output currents and is a function of the squared input current signal. As seen in  FIG. 8D , by combining the first output current I +   out  and the second output current I −   out , the negative impact on both the first output current I +   out  and the second output current I −   out  is canceled out so that the overall output current I out  still presents a proper behavior as a function of the squared input current signal i. 
   While the disclosure has been made with reference to the certain illustrated embodiments, the words that have been used herein are words of description, rather than words of limitation. Changes may be made, within the purview of the appended claims, without departing from the scope and spirit of the invention in its aspects. Although the inventions have been described herein with reference to particular structures, acts, and materials, the invention is not to be limited to the particulars disclosed, but rather can be embodied in a wide variety of forms, some of which may be quite different from those of the disclosed embodiments, and extends to all equivalent structures, acts, and, materials, such as are within the scope of the appended claims.