Abstract:
A testing apparatus includes one or more trace banks. Each trace bank includes (1) an input switch operable to couple an input port to one of multiple output ports, (2) an output switch operable to couple one of multiple input ports to one output port, and (3) transmission lines of different lengths coupled between the output ports of the input switch and the input ports of the output switch. The trace banks can be cascaded using cables to connect their output and input ports. The input and output switches in the trace banks are controlled to provide a transmission path of the desired length.

Description:
DESCRIPTION OF RELATED ART 
     Jitter is the deviation of an event from its ideal time. Jitter consists of deterministic jitter and random jitter. Deterministic jitter is the jitter component that is bounded in amplitude. Random jitter is the jitter component that is unbounded in amplitude and follows a Gaussian probability distribution. Deterministic jitter includes data-dependent jitter, which is caused by frequency-dependent losses in transmission links. 
     It is valuable to generate data-dependent jitter for various transmission path lengths. This helps to accurately simulate a primary source of signal degradation in real applications, provide data as to trace lengths that work across various media distances, and realistically test receiver equalization schemes being used in newer serializer/deserializer (SERDES). 
     SUMMARY 
     In one embodiment of the invention, a testing apparatus includes one or more trace banks. Each trace bank includes (1) an input switch operable to couple an input port to one of multiple output ports, (2) an output switch operable to couple one of multiple input ports to one output port, and (3) transmission lines of different lengths coupled between the output ports of the input switch and the input ports of the output switch. The trace banks can be cascaded using cables to connect their output and input ports. The input and output switches in the trace banks are controlled to provide a transmission path of the desired length. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a block diagram of a testing apparatus for providing transmission paths of variable lengths in one embodiment of the invention. 
         FIG. 2  illustrates a block diagram of trace banks in a transmission path of the apparatus of  FIG. 1  in one embodiment of the invention. 
         FIGS. 3 and 4  illustrate top and side views of a trace bank of  FIG. 2  in one embodiment of the invention. 
         FIG. 5  illustrates a placement of the trace banks and switches of  FIG. 2  on a printed circuit board (PCB) in one embodiment of the invention. 
         FIG. 6  illustrates a layout of the traces in a trace bank of  FIG. 5  on a PCB in one embodiment of the invention. 
         FIG. 7  illustrates another trace bank of  FIG. 2  in another embodiment of the invention. 
     
    
    
     Use of the same reference numbers in different figures indicates similar or identical elements. 
     DETAILED DESCRIPTION 
     There is a need for a testing apparatus that generates various levels of deterministic jitter, or more specifically, to add deterministic jitter to a serial data signal. The intent of the testing apparatus is to generate up to 0.5 UI (unit interval, or bit period) of deterministic jitter at data rates of 1 Gbps (gigabits per second) and to generate deterministic jitter with incremental (step size) control of 0.02 UI at data rates of 10 Gbps. 
       FIG. 1  illustrates a testing apparatus  100  in one embodiment of the invention. Apparatus  100  provide a transmission path  102  between ports A 1  and A 2 , and a transmission path  104  between ports B 1  and B 2 . Transmission paths  102  and  104  have variable lengths set through a control interface  106 . During testing, a user sets transmission paths  102  and  104  to a desired length, provides differential test signals at ports A 1  and B 1 , and measures the deterministic jitter added to the transmitted signals at ports A 2  and B 2 . In one embodiment, the test signals have a data rate from 1 Gbps to 10 Gbps. 
       FIG. 2  illustrates transmission path  102  in one embodiment of the invention. Although not shown, transmission path  104  is implemented in the same way as transmission  102 . 
     Transmission path  102  includes trace banks  202 ,  204 , and  206 , and a de-skew bank  208 . Any combination of trace banks  202 ,  204 , and  206  can be cascaded to form a transmission path  102  with the desired length. De-skew bank  208  may be cascaded with trace banks  202 ,  204 , and  206  to correct any length mismatches between transmission paths  102  and  104 . Length mismatches between transmission paths  102  and  104  may be caused by variations in the manufacturing process. 
     In one embodiment, each trace bank includes six traces  210  connected between switches  212  and  214 . In each trace bank, switches  212  and  214  select one of traces  210 . In one embodiment, traces  210  for trace banks  202 ,  204 , and  206  have the following lengths. 
     
       
         
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 Trace bank 202 
                 Trace bank 204 
                 Trace bank 206 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Trace 1 
                 0.7″ 
                 0.7″ 
                 0.7″ 
               
               
                   
                 Trace 2 
                 1.4″ 
                 4.9″ 
                 25.9″ 
               
               
                   
                 Trace 3 
                 2.1″ 
                 9.1″ 
                 51.1″ 
               
               
                   
                 Trace 4 
                 2.8″ 
                 13.3″ 
                 76.3″ 
               
               
                   
                 Trace 5 
                 3.5″ 
                 17.5″ 
                 101.5″ 
               
               
                   
                 Trace 6 
                 4.2″ 
                 21.7″ 
                 126.7″ 
               
               
                   
                   
               
             
          
         
       
     
     In one embodiment, de-skew bank  208  includes six traces  220  connected between switches  212  and  214 . Switches  212  and  214  select one of traces  220 . Traces  220  have a smaller length increment (e.g., 0.07″) than traces  210  (e.g., 0.7″, 4.2″, and 25.2″). In one embodiment, traces  220  for de-skew banks  208  have the following lengths. 
     
       
         
               
               
             
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 De-skew bank 208 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Trace 1 
                 3.00″ 
               
               
                   
                 Trace 2 
                 3.07″ 
               
               
                   
                 Trace 3 
                 3.14″ 
               
               
                   
                 Trace 4 
                 3.21″ 
               
               
                   
                 Trace 5 
                 3.28″ 
               
               
                   
                 Trace 6 
                 3.35″ 
               
               
                   
                   
               
             
          
         
       
     
       FIGS. 3 and 4  illustrate top and side views of trace bank  202  in one embodiment of the invention. Although not illustrated, banks  204 ,  206 , and  208  are implemented in the same way but for the lengths of the traces between switches  212  and  214 . 
     Traces 1, 2, 3, 4, 5, and 6 are formed on a printed circuit board (PCB)  302 . In one embodiment, traces 1 to 6 are 50 ohm, 10 millimeter wide striplines. 
     Switch  212  has output ports  311 ,  312 ,  313 ,  314 ,  315 , and  316  connected by SMA barrel connectors  318  to respective traces 1 to 6. Switch  212  further has an input port  319  that can be coupled to one of output ports  311  to  316 . Switch  214  has input ports  321 ,  322 ,  323 ,  324 ,  325 , and  326  connected by SMA barrel connectors  328  to respective traces 1 to 6. Switch  214  further has an output port  329  that can be coupled to one of input ports  321  to  326 . Switches  212  and  214  are mounted to a housing  330  for apparatus  100 . In one embodiment, microwave switches  212  and  214  are single-pole, six-throw (SP6T) switches 87106C from Agilent Technologies, Inc. of Palo Alto, Calif. 
     Input port  319  can be coupled by a cable to (1) a testing equipment to receive test signals (whereby input port  319  becomes input port A 1 ), or (2) an output port  329  of another bank to receive cascaded test signals. Similarly, output port  329  can be coupled by a cable to (1) an input port  319  of another bank or (2) a test equipment to provide cascaded test signals (whereby output port  329  becomes output port A 2 ). With six trace lengths in each bank and three trace banks, a combination of 6 to the power of 3 ( 216 ) length steps can be achieved. 
       FIG. 5  illustrates a placement of banks  202 ,  204 ,  206 , and  208  for transmission paths  102  and  104  on PCB  302  in one embodiment of the invention. Shaded boxes  502  indicate areas consumed by the traces for each bank. Note that the layout of transmission paths  102  and  104  on PCB  302  are symmetrical in order to better match transmission paths  102  and  104 . If PCB  302  has multiple stripline layers, traces 1 to 6 for all the banks are formed on the same layer to better match transmission paths  102  and  104 . Furthermore, traces 1 to 6 in corresponding banks in transmission paths  102  and  104  are placed as close as possible to better match transmission paths  102  and  104 . 
       FIG. 6  illustrates a layout of traces 1 to 6 for banks  206  in transmission paths  102  and  104  in one embodiment of the invention. Due to their lengths, both sets of traces 1 to 6 have serpentine patterns to minimize their footprints. Both sets of serpentine traces 1 to 6 have the same layer orientation (e.g., left to right) for corresponding banks in transmission paths  102  and  104  to better match transmission paths  102  and  104 . 
       FIG. 7  illustrates a transmission path  102  in another embodiment of the invention. Transmission path  104  is implemented in the same way as transmission path  102 . 
     Input port A 1  is coupled by a coupling capacitor  706  to a node  708 . A voltage source A with a biasing resistor is connected to node  708 . Output port A 2  is coupled by a coupling capacitor  712  to a node  714 . A voltage source H with a biasing resistor is connected to node  714 . Switched links  716 ,  718 , and  720  are connected in series between nodes  708  and  714 . In one embodiment, switched links  716 ,  718 , and  720  are binary weighted so that link  716  has a total trace length that is twice of link  718  and four times of link  720 . Although only three binary weighted switched links are shown, any number of binary weighted switched links can be added to get 2 to the n power of length steps, where n is the total number of switched links. 
     Link  716  has an input terminal  718  and an output terminal  720 . Input terminal  718  is connected to node  708 . Output terminal  720  is coupled to an input terminal  818  of link  718 . 
     A series path diode  722  has its anode connected to input terminal  718  and its cathode connected to output terminal  720 . A link diode  724  has its anode coupled to input terminal  718  and its cathode connected to a trace  726 . A voltage source B with a biasing resistor is connected to trace  726 . A coupling capacitor  728  couples trace  726  to a trace  730 . A voltage source C with a biasing resistor is connected to trace  730 . A second link diode  732  has its anode connected to trace  730  and its cathode connected to output terminal  720 . In one embodiment, all the diodes are PIN (positive-intrinsic-negative) diodes. 
     Links  718  and  720  are implemented in the same way as link  716 . Corresponding parts in link  718  have been given the same reference number in the 800&#39;s while corresponding parts in link  720  have been given the same reference number in the 900&#39;s. 
     In link  718 , a voltage source D with a biasing resistor is connected to trace  826  and a voltage source E with a biasing resistor is connected to trace  830 . Input terminal  818  is connected to output terminal  720  of link  716 . Output terminal  820  is connected to input terminal  918  of link  720 . 
     In link  720 , a voltage source F is connected to trace  926  and a voltage G is connected to trace  930 . Output terminal  920  is connected to node  714 . 
     In a link, the diodes act as switches. To bypass the link, the series path diode is turned on and the link diodes are turned off. To add the link to the transmission path between ports  704  and  710 , the series path diode is turned off and the link diodes are turned on. The series path diodes and the link diodes are turned on and off by applying the appropriate DC (direct current) biasing voltages with voltage sources A to H. In one embodiment, the resistance of all the biasing resistors is 1 kilo Ohms, the capacitance of all blocking capacitors is 0.01 microfarad, and the applied voltages and the resulting length are as follows: 
     
       
         
               
               
               
               
               
               
               
               
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                   
                 Links 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 Total 
                 switched 
               
               
                 length 
                 in 
                 A 
                 B 
                 C 
                 D 
                 E 
                 F 
                 G 
                 H 
               
               
                   
               
             
             
               
                 0 
                 None 
                 +10 V 
                 +50 V 
                 −50 V 
                  +50 V 
                  −50 V 
                  +50 V 
                  −50 V 
                  −10 V 
               
               
                 1× 
                 720 
                 +10 V 
                 +50 V 
                 −50 V 
                  +50 V 
                  −50 V 
                  −10 V 
                  +60 V 
                  +40 V 
               
               
                 2× 
                 718 
                 +10 V 
                 +50 V 
                 −50 V 
                  −10 V 
                  +60 V 
                 +100 V 
                   0 V 
                  +40 V 
               
               
                 3× 
                 718, 720 
                 +10 V 
                 +50 V 
                 −50 V 
                  −10 V 
                  +60 V 
                  +40 V 
                 +110 V 
                  +90 V 
               
               
                 4× 
                 716 
                 +10 V 
                 −10 V 
                 +60 V 
                 +100 V 
                   0 V 
                 +100 V 
                   0 V 
                  +40 V 
               
               
                 5× 
                 716, 720 
                 +10 V 
                 −10 V 
                 +60 V 
                 +100 V 
                   0 V 
                  +40 V 
                 +110 V 
                  +90 V 
               
               
                 6× 
                 716, 718 
                 +10 V 
                 −10 V 
                 +60 V 
                  +40 V 
                 +110 V 
                 +150 V 
                  +50 V 
                  +90 V 
               
               
                 7× 
                 716, 
                 +10 V 
                 −10 V 
                 +60 V 
                  +40 V 
                 +110 V 
                  +90 V 
                 +160 V 
                 +140 V 
               
               
                   
                 718, 720 
               
               
                   
               
             
          
         
       
     
     Assuming ideal diodes are used (zero forward voltage drop, zero reverse leakage the voltages in Table 3 provide up to 10 milliamps of forward current for all “on” diodes and 50 volts of reverse bias voltage for all “off” diodes. Note that more coupling capacitors and biasing resistors could be used to isolate each switched link and make the voltage voltage scheme more straightforward. However, the minimum number of coupling capacitors and biasing resistors are used to provide the “cleanest” possible transmission paths with a more complex biasing voltage scheme. 
     Various other adaptations and combinations of features of the embodiments disclosed are within the scope of the invention. Numerous embodiments are encompassed by the following claims.