Abstract:
A chip testing circuit is disclosed. The chip testing circuit uses a judging circuit to switch the connection of the data compressing circuit between data compressing base units which compresses 4 XIOs, so as to obtain testing data by one single interface circuit and to increase the testing throughput.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    (a) Field of the Invention 
         [0002]    The invention relates to a chip data compressing test multiplexing circuit, particularly to a chip data compressing test multiplexing circuit for increasing testing throughput. 
         [0003]    (b) Description of the Related Art 
         [0004]    An integrate circuit (IC) is one of essential electronic elements for an information appliance because of its great functionality and compact size. In order to assure the functionality of a chip, the chip is required to pass comprehensive tests. Generally, the test method is to input a known testing signal into the circuit in the chip and acquire a feedback signal from the circuit of the chip to thereby determine whether the chip functions normally or not. 
         [0005]    However, in order to correctly test a chip, the architecture of the chip testing circuit according to the prior art, for example one cycle IO compress  8  read circuit to test 8 signals at once, should have two pins only for testing and two interface circuits connecting to two probes of the chip testing system. Thus, the number of pins for testing is increased and thereby the cost of the chip testing circuit is also increased. If the chip testing rate is to be increased, the number of probes should be increased as well. It results in the increase of the whole production cost. 
       BRIEF SUMMARY OF THE INVENTION 
       [0006]    In light of the above-mentioned problems, one object of the invention is to provide a chip testing circuit to decrease the usage of the number of pins and increase the chip testing rate to decrease the production cost. 
         [0007]    In order to achieve the above purpose, one embodiment of the invention provides a chip testing circuit, comprising a plurality of write units, a first interface circuit, a first switch, a plurality of read units, a first compressing circuit, a second compressing circuit, a judging circuit and an interface circuit. The write units are coupled to at least one circuit in the chip and divided into a first group of write units and a second group of write units. The first interface circuit, coupled to the write units, receives a testing signal and transmits the testing signal to the write units to input the testing signal to the circuit in the chip. The first switch is provided between the first group of write units and the second group of write units and is selectively coupled to the first group of write units and the second group of write units. The read units are coupled to at least one circuit in the chip to receive and output the feedback signals of the circuit of the chip and are divided into a first group of read units and a second group of read units. The first group of read units outputs the first group of feedback signals and comprises at least one first feedback signal; and the second group of read units outputs the second group of feedback signals and comprises at least one second feedback signal. The first compressing circuit is coupled to the read units of the first group of read units and compresses the first group of feedback signals outputted by the first group of read units to generate a first compressing signal. The second compressing circuit is coupled to the read units of the second group of read units and compresses the second group of feedback signals outputted by the second group of read units to generate a second compressing signal. The judging circuit is coupled to the first and the second compressing circuits and generates a judging signal selectively according to one of the following signal or combination thereof: the first compressing signal, the second compressing signal, the first feedback signal, and the second feedback signal. The interface circuit is coupled to the judging circuit and generates a test result according to the judging signal to determine whether the chip has defect or not. 
         [0008]    The chip testing circuit according to the present invention utilizes the judging unit to do allocation and control without additional interface circuits and connecting points to achieve the purpose of increasing testing throughput per unit time so as to decrease the production cost and increase the testing efficiency. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1A  shows a schematic diagram illustrating a write circuit of the chip testing circuit according to one embodiment of the invention. 
           [0010]      FIG. 1B  shows a schematic diagram illustrating a read circuit of the chip testing circuit according to one embodiment of the invention. 
           [0011]      FIG. 2  shows the operation truth table of  FIG. 1B . 
           [0012]      FIG. 3  shows a schematic diagram illustrating the chip testing circuit according to another embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0013]      FIG. 1A  and  FIG. 1B  show schematic diagrams illustrating the chip testing circuit (chip data compressing test multiplexing circuit) according to one embodiment of the invention. The chip testing circuit  100  according to one embodiment of the invention comprises a write circuit portion to input the testing signal TS to the chip or the other internal circuit  10   a , as shown in  FIG. 1A  and a read circuit portion to receive the feedback signal FS from the chip or the other internal circuit  10   a , as shown in  FIG. 1B . 
         [0014]    As shown in  FIG. 1A , the write circuit of the chip testing circuit  100  according to one embodiment of the invention comprises a first write compressing circuit  101 , a second write compressing circuit  102 , a first interface circuit  103 , and a first switch  104 . 
         [0015]    In this embodiment, the first write compressing circuit  101  and the second write compressing circuit  102  separately comprise four write units, that is, the first group of write units  101   a  and the second group of write units  102   a . But, the present invention is not limited to this example. The number of write units included in the first write compressing circuit  101  and the second write compressing circuit  102  can be adjusted according to the designer. Besides, in one embodiment, the first write compressing circuit  101  and the second write compressing circuit  102  can comprise the same or different number of write units. Each write unit  101   a ,  102   a  is coupled to at least one circuit of the chip or the other internal circuit  10   a.    
         [0016]    The first interface circuit  103  is separately coupled to the write units  101   a ,  102   a  in the first write compressing circuit  101  and the second write compressing circuit  102 . The first interface circuit  103  receives a testing signal TS inputted by the chip testing system (such as probe card) and transmits the testing signal TS to the write units  101   a ,  102   a  to input the testing signal TS to the chip or the other internal circuit  10   a.    
         [0017]    The first switch  104  is provided between the first write compressing circuit  101  and the second write compressing circuit  102  to be selectively coupled to the first write compressing circuit  101  and the second write compressing circuit  102 . In other words, the first switch  104  can be individually coupled to the write unit of the first write compressing circuit  101  or the second write compressing circuit  102 . The first switch  104  can also be coupled to the write units of the first write compressing circuit  101  and the second write compressing circuit  102  at the same time. 
         [0018]    In one embodiment, the operation method of the write circuit portion according to the invention is as follows. At first, the chip testing system  210  inputs the testing signal TS to the write circuit of the chip testing circuit  100 . The first interface circuit  103  receives the testing signal TS and at the same time the chip testing system  210  provides a control signal (not shown) to the first switch  104  to control the first switch  104  to be coupled to the first and the second write compressing circuits  101 ,  102 . In one embodiment, the chip testing system  210  can use the redundancy address to provide the control signal to the first switch  104  to control the operation of the first switch  104 . Then, the write units  101   a ,  102   a  of the first and the second write compressing circuits  101 ,  102  separately receive the testing signal TS and write the testing signal TS into the chip or the other internal circuit  10   a.    
         [0019]      FIG. 1B  shows a schematic diagram illustrating a read circuit portion of the chip testing circuit  100  according to one embodiment of the invention. The read circuit of the chip testing circuit  100  comprises a chip or other internal circuit  10   a , a first read compressing circuit  202 , a second read compressing circuit  203 , a first compressing circuit  204 , a second compressing circuit  205 , a judging circuit  206 , and an interface circuit  207 . 
         [0020]    The first read compressing circuit  202  comprises N read units  202   a  and is to receive and output the first group of feedback signals transmitted by the chip where N is a positive integer and less than infinity. The second read compressing circuit  203  comprises M read units and is to receive and output the second group of feedback signals transmitted by the chip where M is a positive integer and less than infinity. In this embodiment, the first read compressing circuit  202  and the second read compressing circuit  203  separately comprise four read units, that is, the first group of read units  202   a  and the second group of read units  203   a . But, the present invention is not limited to this example. The number of read units  202   a ,  203   a  included in the first read compressing circuit  202  and the second read compressing circuit  203  can be adjusted according to the designer. Besides, in one embodiment, the first read compressing circuit  202  and the second read compressing circuit  203  can comprise the same or different number of read units. 
         [0021]    The first read compressing circuit  202  is coupled to the chip or other circuit  10   a  and is used to read the first group of feedback signals FS transmitted by the chip or other circuit  10   a , number the feedback signals to be i 0 , i 1 , i 2 , i 3 , and then output these feedback signals. The feedback signals i 0 , i 1 , i 2 , i 3  are defined as the first feedback signal. The first compressing circuit  204  is coupled to the first read compressing circuit  202  and compresses the first group of feedback signals i 0 , i 1 , i 2 , i 3  to generate the first compressing signal CS 1 . 
         [0022]    The second read compressing circuit  203  is coupled to the chip or other circuit  10   a  and is used to read the second group of feedback signals FS transmitted by the chip or other circuit  10   a , number the feedback signals to be i 4 , i 5 , i 6 , i 7 , and then output these feedback signals. The feedback signals i 4 , i 5 , i 6 , i 7  are defined as the second feedback signal. The second compressing circuit  205  is coupled to the second read compressing circuit  203  and compresses the second group of feedback signals i 4 , i 5 , i 6 , i 7  to generate the second compressing signal CS 2 . 
         [0023]    The judging circuit  206  is coupled to the first compressing circuit  204  and the second compressing circuit  205  and is used to generate a judging signal JS 2  selectively according to one of the following signal or combination thereof: the first compressing signal CS 1 , the second compressing signal CS 2 , the first feedback signal, and the second feedback signal. The judging circuit  206  comprises a first calculator  208  and a second calculator  209 . The first calculator  208  receives the first feedback signal and the second feedback signal and performs a logic operation on the first feedback signal and the second feedback signal to generate an output signal JS 1 . The second calculator  209  receives the first compressing signal CS 1 , the second compressing signal CS 2 , and the output signal JS 1  and performs a logic operation on the first compressing signal CS 1 , the second compressing signal CS 2 , and the output signal JS 1  to generate the judging signal JS 2 . 
         [0024]    In one embodiment, the first calculator  208  is an exclusive OR gate logic circuit and the second calculator  209  is an OR gate logic circuit. The exclusive OR gate  208  receives any one of the feedback signals in the first group of feedback signals and any one of the feedback signals in the second group of feedback signals generated by the first read compressing circuit  202  and the second read compressing circuit  203  and performs a logic operation to generate the output signal JS 1 . In this embodiment, the exclusive OR gate  208  receives the first feedback signal i 3  and the second feedback signal i 7  to perform the logic operation and then generates the output signal JS 1 . But, the present invention is not limited to this example. 
         [0025]    The OR gate  209  is coupled to the first compressing circuit  204 , the second compressing circuit  205 , and the exclusive OR gate  208  and is used to perform the logic operation on the first compressing signal CS 1 , the second compressing signal CS 2 , and the output signal JS 1  to generate the judging signal JS 2 . 
         [0026]    Simultaneously referring to  FIGS. 1B and 2 ,  FIG. 2  shows the operation truth table of the chip testing circuit of  FIG. 1B  according to one embodiment of the invention. According to one embodiment of the invention, from the truth table, when the logic values of the feedback signals i 0 , i 1 , i 2 , i 3  are the same, that is all 0 or all 1, the logic value of the first compressing signal CS 1  is logic 0. When the logic values of the feedback signals i 4 , i 5 , i 6 , i 7  are the same, that is all 0 or all 1, the logic value of the second compressing signal CS 2  is logic 0. On the other hand, when the logic value of at least one feedback signal in the feedback signals i 0 , i 1 , i 2 , i 3  is different from that of the other feedback signal, that is the logic values of the feedback signals i 0 , i 1 , i 2 , i 3  are not all 0 or all 1, the logic value of the first compressing signal CS 1  is logic 1. When the logic value of at least one feedback signal in the feedback signals i 4 , i 5 , i 6 , i 7  is different from that of the other feedback signal, that is the logic values are not all 0 or all 1, the logic value of the second compressing signal CS 2  is 1. 
         [0027]    For illustration convenience, it is assumed that the chip testing system  210  writes the testing signal with logic 0 into the chip or other internal circuit for testing. Thus, if the chip or other internal circuit functions normally, the logic value returned by the chip or other internal circuit should be also 0 since the logic value of the write-in data is also 0. The following describes the five cases showing the chip testing systems  210  writes the testing signal with logic 0 into the chip or other internal circuit for testing. 
         [0028]    In the first case, the test result of the chip or other internal circuit is normal and has no error. When the logic values of the feedback signals i 0 , i 2 , i 3 , i 4 , i 5 , i 6 , i 7  returned by the chip or other internal circuit  10   a  are all 0, the logic values of the first compressing signal CS 1  and the second compressing signal CS 2  are also 0. Since the output of the exclusive OR gate  208  is based on the feedback signal i 3 =0 and the feedback signal i 7 =0, the logic value of the generated output signal JS 1  is also 0 after comparing the two data. Then, the OR gate  209  performs the logic operation on the first compressing signal CS 1 , the second compressing signal CS 2 , and the output signal JS 1 . Since the logic values of the first compressing signal CS 1 , the second compressing signal CS 2 , and the output signal JS 1  are all 0, the logic value of the judging signal JS 2  is 0. Finally, the chip testing system  210  receives the judging signal J 52  via the interface circuit  207  and realizes that the chip or other internal circuit  10   a  is normal and has no error. 
         [0029]    In the second case, the test result of the chip or other internal circuit  10   a  has error(s). When the logic values of the feedback signals i 0 , i 1 , i 2 , i 3  returned by the chip or other internal circuit  10   a  are all 0 but the logic values of the feedback signals i 4 , i 5 , i 6 , i 7  are not all 0 and not all 1 (that is, there is data error in the feedback signals i 0 , i 1 , i 2 , i 3 , i 4 , i 5 , i 6 , i 7 ), the logic value of the first compressing signal CS 1  is 0 and the logic value of the second compressing signal CS 2  is 1. In the meantime, no matter what the output signal JS 1  generated by the exclusive OR gate  208  is, the logic value of the judging signal JS 2  generated by the OR gate  209  will always be 1 because the logic value of the second compressing signal CS 2  is 1. The interface circuit  207  outputs the data of logic 1 to the chip testing system  210 . Therefore, the chip testing system  210  realizes that the chip or other internal circuit  10   a  has error(s). 
         [0030]    In the third case, the test result of the chip or other internal circuit  10   a  also has error(s). When the logic values of the feedback signals i 0 , i 1 , i 2 , i 3  returned by the chip or other internal circuit  10   a  are not all 0 and not all 1 (that is, there is data error in the feedback signals i 0 , i 1 , i 2 , i 3 ) but the logic values of the feedback signals i 4 , i 5 , i 6 , i 7  are all 0, the logic value of the first compressing signal CS 1  is 1 and the logic value of the second compressing signal CS 2  is 0. In the meantime, no matter what the output signal JS 1  generated by the exclusive OR gate  208  is, the logic value of the judging signal JS 2  generated by the OR gate  209  will always be 1 because the logic value of the first compressing signal CS 1  is 1. The interface circuit  207  outputs the data of logic 1 to the chip testing system  210 . Therefore, the chip testing system  210  realizes that the chip or other internal circuit  10   a  has error(s). 
         [0031]    In the fourth case, the test result of the chip or other internal circuit  10   a  also has error(s). When the logic values of the feedback signals i 0 , i 2 , i 3  returned by the chip or other internal circuit  10   a  are all 0 but the logic values of the feedback signals i 4 , i 5 , i 6 , i 7  are all 1 (that is, the feedback signals i 4 , i 5 , i 6 , i 7  are all incorrect), the logic value of the first compressing signal CS 1  is 0 and the logic value of the second compressing signal CS 2  is 0. Generally, if the logic values of the first compressing signal CS 1  and the second compressing signal CS 2  are both 0, the chip testing system  210  determines that the result of the chip or other internal circuit  10   a  is correct. But, the chip testing circuit  100  uses the exclusive OR gate  208  of the judging circuit  206  to generate the output signal JS 1  with logic 1 according to the logic value 0 of the first compressing signal CS 1  and the second compressing signal CS 2  and thereby the judging signal J 52  outputted by the OR gate  209  becomes logic 1. Thus, the chip testing system  210  realizes that the chip or other internal circuit  10   a  has error(s) so that correctly judging the chip or other internal circuit  10   a  can be achieved. 
         [0032]    In the fifth case, the test result of the chip or other internal circuit  10   a  also has error(s). When the logic values of the feedback signals i 0 , i 1 , i 2 , i 3  returned by the chip or other internal circuit  10   a  are all 1 and the logic values of the feedback signals i 4 , i 5 , i 6 , i 7  are all 1, the logic value of the first compressing signal CS 1  is 0 and the logic value of the second compressing signal CS 2  is 0. Since the output of the exclusive OR gate  208  is based on the feedback signal i 3 =1 and the feedback signal i 7 =1, the logic value of the generated output signal JS 1  is 0. Generally, if the logic values of the first compressing signal CS 1 , the second compressing signal CS 2 , and the output signal JS 1  are all 0, the chip testing system  210  determines that the result of the chip or other internal circuit  10   a  is correct. However, the chip testing circuit  100  uses the interface circuit  207  to compare the logic values of the feedback signal i 7  and the judging signal JS 2 . Since the feedback signal i 7 =1 and the judging signal JS 2 =0, the interface circuit  207  generates the logic value 1 after comparison. Thus, the chip testing system  210  realizes that the chip or other internal circuit  10   a  has error(s). 
         [0033]    Through the above method, the chip testing circuit according to the embodiments of the invention does not need to increase the number of interface circuits and connecting points to achieve the purpose of increasing the testing throughput per unit time so that the production cost can be reduced and the testing efficiency can be increased. 
         [0034]    Furthermore, the chip testing circuit according to the embodiments of the invention can be developed to have a N-terminal input signal compressing method. For example, as shown in  FIG. 3 , the read circuit of the chip testing circuit uses a 16-terminal input signal compressing method. The chip testing circuit uses two exclusive OR gates and three OR gates to perform logic operations to separately process the data read by the read units of the four read compressing circuits and thereby to determine the state of the circuits in the chip. It should be noted that those who are skilled in the art should understand the architecture of the write circuit portion of the chip testing circuit can be implemented by allocating three switches from the above description and  FIG. 3 . By the above method, the chip testing circuit only needs to use one interface circuit and one pin to connect to the probe of the chip testing system to achieve the purpose of receiving 16 feedback signals. Thus, the chip testing efficiency can be increased and the chip testing cost can be reduced. 
         [0035]    It should be noted that the chip according to the embodiments of the invention can be a memory element, a semiconductor device comprising a memory element, or a logic element. In addition, the chip can be of a wafer form, a die form, or a chip package form. The chip testing circuit according to the embodiments of the invention is complied with a repair algorithm. 
         [0036]    Although the present invention has been fully described by the above embodiments, the embodiments should not constitute the limitation of the scope of the invention. Various modifications or changes can be made by those who are skilled in the art without deviating from the spirit of the invention.