Abstract:
A power on reset circuit (POR) includes a first reset circuit for delivering a first reset signal when a supply voltage of the POR circuit is between a first low threshold and a first high threshold, and a second reset circuit for delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is less than the first high threshold. The POR circuit further includes at least one electrically erasable and programmable non-volatile memory cell. A delivery circuit outputs the first reset signal or the second reset based upon on whether the at least one electrically erasable and programmable non-volatile memory cell is in an erased or programmed state. The POR circuit has a threshold for outputting the first or second reset signal that is programmable according to the intended application.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a circuit that resets to zero upon the occurrence of a supply voltage. This circuit is generally referred to as a power on reset (POR) circuit.  
         BACKGROUND OF THE INVENTION  
         [0002]    When powered on, most integrated circuits comprising logic circuits, registers and flip-flops need to be reset to insure that their internal nodes do not have indeterminate logic states. This reset is done by a POR circuit, which delivers a signal RESET when the supply voltage is between two thresholds V 1  and V 2 .  
           [0003]    A POR circuit intervenes upon power-up (rise in the supply voltage) to deliver the signal RESET when the supply voltage reaches the threshold V 1  and releases the signal RESET when the supply voltage reaches the threshold V 2 . The active value of the signal RESET may be 1 or 0 and the release of the signal RESET may therefore correspond to it being set to 0 or to 1.  
           [0004]    A POR circuit also intervenes upon power-down (drop in the supply voltage) to deliver the signal RESET when the supply voltage becomes lower than the threshold V 2 . In fact, it is important to reset the logic circuits of an integrated circuit when the supply voltage drops below a determined minimum threshold, below which the proper operation of the integrated circuit is not insured. Below this threshold, certain elements may prove to be unstable or have indeterminate logic states. Certain operations can also be marred with errors, erasing or programming memory cells, for example.  
           [0005]    Therefore, it is preferable to reset the integrated circuit to zero. The threshold V 2  of the POR circuit is chosen to correspond to this minimum security threshold. Thus, the signal RESET is delivered each time the supply voltage goes below the threshold V 2 , whether it is when the integrated circuit is switched off or upon unintentional power-down.  
           [0006]    When designing a POR circuit, the threshold V 2  is generally chosen according to the characteristics of the application in which the integrated circuit is intended to be implemented. These characteristics are established by the user. For example, certain users may want the signal RESET to be sent when the voltage Vcc drops below a threshold V 2  on the order of 2.5V while other users may want the signal RESET to be sent when the voltage Vcc drops below a threshold V 2  on the order of 1.5 V. This requirement depends on the constraints imposed by the application. It can occur, for example, that the application comprises other integrated circuits that communicate with the integrated circuit concerned, and are likely to send invalid commands below a determined threshold V 2 . This is why it is preferable to reset the integrated circuit to zero below the threshold V 2 , even if the latter is capable of supporting lower supply voltages without malfunctioning.  
           [0007]    The need to change the threshold V 2  for sending the signal RESET according to the intended application leads to a diversification of the POR circuits and a corresponding diversification of the integrated circuits. Integrated circuits are often provided that can operate in a wide range of supply voltages, such as from 1.8 V to 5.5 V for example, but they need to be manufactured in two different versions. Each version includes a specific POR circuit having a threshold V 2  compatible with the intended application.  
         SUMMARY OF THE INVENTION  
         [0008]    In view of the foregoing background, an object of the present invention is to provide a POR circuit that can be incorporated into integrated circuits that can receive different supply voltages.  
           [0009]    This and other objects, advantages and features in accordance with the present invention are provided by a POR circuit having a switching threshold that is programmable by a non-volatile memory cell.  
           [0010]    More particularly, the present invention provides a POR circuit comprising means for delivering a first reset signal when the supply voltage of the POR circuit is between a first low threshold and a first high threshold, and means for delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is lower than the first high threshold. At least one electrically erasable and programmable non-volatile memory cell can be put into an erased state or into a programmed state. The POR circuit may further comprise means for delivering the first or the second reset signal to the output of the POR circuit, depending on whether the memory cell is in the erased state or in the programmed state.  
           [0011]    The POR circuit may further comprise a select circuit for selecting one of the reset signals at the output of the POR circuit depending on the value of a select signal applied to the select circuit. The POR circuit may also further comprise a select control circuit for delivering the select signal, wherein the value of the select signal depends on the erased or programmed state of the memory cell.  
           [0012]    The select control circuit may have a differential architecture, and may comprise two memory cells. Each memory cell is in either an erased or a programmed state, and is opposite the state of the other memory cell.  
           [0013]    The select control circuit may comprise two PMOS transistors, for example. Each PMOS transistor has its gate connected to the drain of the other PMOS transistor, and its drain linked to one of the two memory cells. The select control circuit may further comprise a latch linked to the two memory cells. The select control circuit may also comprise a transistor for balancing the latch, and insulation transistors for enabling the latch to be insulated from the memory cells. The POR circuit may further comprise means for causing the balancing transistor to conduct while blocking the insulation transistors, and for blocking the balancing transistor and causing the insulation transistors to conduct.  
           [0014]    The POR circuit may comprise means for logically combining the first and second reset signals. The means for delivering the first reset signal or the means for delivering the second reset signal may be arranged to be in an inhibited state or in an active state depending on the on or off state of the memory cell. The first and second reset signals may be combined by an AND logic function.  
           [0015]    The means for delivering the second reset signal may be in an inhibited state or in an active state depending on the on or off state of the memory cell. The reset signal delivered by the POR circuit may be equal to the second reset signal when the means for delivering the second reset signal is not in the inhibited state, or equal to the first reset signal when the means for delivering the second reset signal is in the inhibited state.  
           [0016]    The POR circuit may comprise a logic gate having a ground terminal linked to ground through the memory cell. The logic gate may be inhibited when the memory cell is in a state, either erased or programmed, corresponding to an off state of the memory cell. The logic gate is operational when the memory cell is in a state, either programmed or erased, corresponding to an on state of the cell. The output of the logic gate may be linked to the input of a latch. The output of the latch may be driven by an element arranged to force the output to a predetermined value when the logic gate is inhibited.  
           [0017]    The memory cell in the POR circuit may comprise several floating-gate transistors arranged in parallel and having their floating gates interconnected. Alternatively, the memory cell in the POR circuit may comprise at least one erase and program accessible floating-gate transistor, and at least one floating-gate transistor that is read only accessible. The floating gate of the transistor that is read only accessible and the floating gate of the erase accessible transistor may be interconnected.  
           [0018]    Another aspect of the present invention is directed to a method for delivering a reset signal to an integrated circuit, comprising the step of delivering a first reset signal when the supply voltage of the integrated circuit is between a first low threshold and a first high threshold. The method may further comprise delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is lower than the first high threshold. At least one electrically erasable and programmable non-volatile memory cell that can be put into an erased state or into a programmed state is provided. The first or the second reset signal is delivered depending on whether the memory cell is in the erased state or in the programmed state.  
           [0019]    The at least one memory cell may comprise a pair of memory cells to determine which of the reset signals is delivered to the output of the POR circuit. Each memory cell of the pair is in a state, either erased or programmed, which is the opposite of the state of the other memory cell.  
           [0020]    The method may comprise logically combining the first and second reset signals, and inhibiting delivery of the first reset signal or delivery of the second reset signal depending on the on or off state of the memory cell. The method may comprise logically combining the first and second reset signals using an AND logic function.  
           [0021]    Inhibiting delivering of a reset signal may be performed by not electrically supplying a logic gate when the memory cell is in a state, either erased or programmed, corresponding to an off state of the memory cell. The method may further comprise arranging the memory cell between ground and a ground terminal of the logic gate. The logic gate may no longer be supplied when the memory cell is in a state, either erased or programmed, corresponding to an off state of the memory cell. The logic gate may be operational when the memory cell is in a state, either programmed or erased, corresponding to an on state of the memory cell. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    These and other objects, features and advantages of the present invention shall be explained in greater detail in the following description of example embodiments of POR circuits according to the present invention, given in relation with, but not limited to, the following figures:  
         [0023]    [0023]FIG. 1 is a circuit diagram of a first POR circuit according to the prior art;  
         [0024]    [0024]FIG. 2 is a circuit diagram of a second POR circuit according to the prior art;  
         [0025]    [0025]FIG. 3 is a graph representing reset signals delivered by the first POR circuit illustrated in FIG. 1;  
         [0026]    [0026]FIG. 4 is a graph representing reset signals delivered by the second POR circuit illustrated in FIG. 2;  
         [0027]    [0027]FIG. 5 is a circuit diagram of a first embodiment of a POR circuit according to the present invention;  
         [0028]    [0028]FIGS. 6A and 6B are circuit diagrams of two different embodiments of the select control circuit illustrated in FIG. 5;  
         [0029]    [0029]FIGS. 7 and 8 are circuit diagrams of two different embodiments of a memory cell in the select control circuit according to the present invention;  
         [0030]    [0030]FIG. 9 is a graph illustrating operation of the select control circuit according to the present invention; and  
         [0031]    [0031]FIG. 10 is a circuit diagram of a second embodiment of a POR circuit according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]    [0032]FIGS. 1 and 2 represent two prior art POR circuits, respectively POR 1  and POR 2 , to be arranged in an integrated circuit receiving a supply voltage Vcc. The circuit POR 1  delivers a reset signal RSTH and has a high switching threshold V 2 H. The circuit POR 2  delivers a reset signal RSTL and has a high switching threshold V 2 L lower than V 2 H. According to the present invention, these two circuits POR 1 , POR 2  are combined to form a circuit POR 3  with a programmable switching threshold that will be described below.  
         [0033]    The structure of the circuits POR 1 , POR 2  will be described first, as a non-restrictive example. In the following description, PMOS enhancement transistors are designated by TPx (x being a figure) and NMOS enhancement transistors are designated by TNx. Native-type PMOS transistors (with undoped channels) are designated by TPnx and native-type NMOS transistors are designated by TNnx.  
         [0034]    The circuit POR 1  comprises a switching stage S 1  supplied by the voltage Vcc, and delivers a signal NRSTH. This signal is applied to the input of an inverting gate INV 1 , the output of which delivers the signal RSTH. The stage S 1  comprises transistors TP 1 , TPn 2 , TNn 1  in series. The transistor TP 1  receives the voltage Vcc at its source. Its gate is connected to its drain that is connected to the source of the transistor TPn 2 . The transistor TPn 2  has its drain connected to the drain of the transistor TNn 1  and its gate is connected to ground. The transistor TNn 1  receives the voltage Vcc at its gate and its source is connected to ground. The signal NRSTH is taken on the node that is common to the drains of the transistors TPn 2 , TNn 1 .  
         [0035]    The gate INV 1  is supplied by the voltage Vcc and comprises two transistors TP 3 , TN 2  in series, each receiving the signal NRSTH at their gates and having their drains interconnected. The output signal RSTH is taken on the node that is common to the drains of these transistors.  
         [0036]    The circuit POR 2  comprises a switching stage S 1 ′ delivering a signal NRSTL. This signal is applied to the input of an inverting gate INV 1 ′ that is identical to the gate INV 1  and the output of which delivers the signal RSTL. The stage S 1 ′ is identical to the stage S 1  already described. The same elements are designated by the same references, except for the transistor TP 1  that is removed. In this switching stage S 1 ′, the voltage Vcc is therefore applied to the source of the transistor TPn 2 .  
         [0037]    In FIG. 3, part A represents the shape of the signal RSTH upon power-up, and part B represents the shape of the signal RSTH upon power-down. As a numerical example, it will be assumed that Vtn=0.8V, Vtp=1V, Vtnn=0.4V, and Vtpn=1.5V. Vtp is the threshold voltage of the PMOS enhancement transistors, Vtn is the threshold voltage of the NMOS enhancement transistors, Vtpn is the threshold voltage of the native PMOS transistors, and Vtnn is the threshold voltage of the native NMOS transistors.  
         [0038]    At an instant t 0 , the voltage Vcc starts to rise. At an instant t 0 ′, the voltage Vcc reaches 0.4V (Vtnn) and the transistor TNn 1  goes to an on state. The signal NRSTH at the input of the gate INV 1  goes to 0 (ground). At an instant t 1 , the voltage Vcc reaches 1V (Vtp) and the transistor TP 3  of the gate INV 1  goes to an on state, and the signal RSTH goes to 1. The threshold voltage Vtp therefore forms the low switching threshold V 1  of the circuit POR 1 . At an instant t 2 , the voltage Vcc reaches 2.5 V (Vtp+Vtpn) and the two transistors TP 1 , TPn 2  go to an on state. The transistor TP 1  is arranged as a diode and the transistor TPn 2  has its gate connected to ground. The signal RSTH goes back to 0. The sum of the threshold voltages Vtp+Vtpn of the PMOS transistors TP 1 , TPn 2  therefore forms the high switching threshold V 2 H of the circuit POR 1 , here equal to 2.5 V.  
         [0039]    Part B of FIG. 3 shows that the signal RSTH also goes to 1 when the voltage Vcc becomes lower than the threshold V 2 H. With reference to FIG. 3, part A, the circuit POR 2  has the same low threshold V 1  as the circuit POR 1 , but its high switching threshold V 2 L is equal to 1.5 V. In fact, the input of the gate INV 1 ′ goes to 1 (Vcc) and the signal RSTL goes to 0 when the voltage Vcc becomes higher than the threshold voltage Vtpn of the transistor TPn 2 , the latter then being in the on state (FIG. 2). Upon power-down, FIG. 3 part B, the input of the gate INVI′ goes to 0 (ground) and the signal RSTL goes to 1 when the voltage Vcc becomes lower than the threshold voltage Vtpn of the transistor TPn 2 .  
         [0040]    [0040]FIG. 5 represents a circuit POR 3  according to the present invention delivering a reset signal RESET. The circuit POR 3  comprises the circuits POR 1 , POR 2  described above, a select circuit MUX and a select control circuit SCT. The select control circuit SCT delivers a signal SEL applied to the circuit MUX. The select circuit MUX comprises three NAND-type gates NA 1 , NA 2 , NA 3  each with two inputs, and an inverting gate INV 2 . The gate NA 1  receives the signal SEL and the signal RSTH delivered by the circuit POR 1  at its inputs. The gate INV 2  receives the signal SEL and delivers an inverted signal NSEL. The gate NA 2  receives the signal NSEL and the signal RSTL delivered by the circuit POR 2 . The outputs of the gates NA 1 , NA 2  are applied to the gate NA 3 , which delivers the signal RESET. The signal RESET is therefore equal to: 
         RESET=RSTH*SEL+RSTL*NSEL 
         [0041]    The operator * represents the logic AND and the operator + represent the logic OR.  
         [0042]    Thus, the signal RESET copies the signal RSTH when SEL=1 (NSEL=0) and copies the signal RSTL when NSEL=1 (SEL=0). In other terms, the circuit POR 3  has a high switching threshold V 2 H of 2.5 V when SEL=1 and a high switching threshold V 2 L of 1.5 V when SEL=0.  
         [0043]    [0043]FIG. 6A represents one embodiment of the select control circuit SCT according to the present invention. The circuit SCT is of a differential type and comprises two inverting gates INV 3 , INV 4  head-to-tail connected and forming a latch, and two nonvolatile memory cells CELL 1 , CELL 2 . Each memory cell CELL 1 , CELL 2  has one read input IN 1 , one erasing programming input IN 2  and one source line SL to be connected to ground. The gate INV 3  delivers a signal L 1  and the gate INV 4  delivers a signal L 2 . The input of the gate INV 3 , corresponding to the output of the gate INV 4 , is linked to the input IN 1  of the cell CELL 1  through a transistor TN 3 . The output of the gate INV 3 , corresponding to the input of the gate INV 4 , is linked to the input IN 1  of the cell CELL 2  through a transistor TN 4 . A transistor TN 5  is arranged between the input and the output of the gate INV 3 . The gates INV 3 , INV 4  receive the voltage Vcc on their supply terminal and their ground terminal is linked to ground through a transistor TN 6 . The transistors TN 3 , TN 4  are driven by a signal PASS, the transistor TN 5  is driven by a signal EQ and the transistor TN 6  is driven by a signal LATCH. The signal SEL is delivered by a NOR-type gate NOR 1  receiving the signal L 1  or L 2 , here the signal L 1  on one input and a signal VALIDN on another input.  
         [0044]    The signals PASS, EQ, LATCH, VALIDN are delivered by a control circuit that is not represented here, such as the central processing unit of a microprocessor or a hard-wired logic sequencer, for example. This control circuit is programmed to load into the latch INV 1 /INV 3  differential data logged in the cells CELL 1 , CELL 2 . Once the latch is loaded, the signal SEL is maintained by the latch and the transistors TN 6 , TN 7  enable the memory cells CELL 1 , CELL 2  to be insulated by taking the signal PASS to 0.  
         [0045]    The circuit SCT is preferably configured before the integrated circuit, in which the circuit POR 3  is arranged, such as during the final test phase prior to marketing the integrated circuit, for example. The cells CELL 1 , CELL 2  are put into complementary states, one erased and the other programmed. This configuration is done according to the voltage Vcc that the integrated circuit is intended to receive.  
         [0046]    It will be assumed that the cell CELL 1  is programmed and that the cell CELL 2  is erased. The cell CELL 1  is therefore electrically conductive between its input IN 1  and ground (source line SL), while the cell CELL 2  is not conductive. When the voltage Vcc occurs, the input of the gate INV 3  is pulled down so that the signal L 1  goes to 1 (Vcc). In these conditions, the signal SEL goes to 1 if the gate NOR 1  is transparent (VALIDN=0) and the signal RESET delivered by the circuit POR 3  is the signal RSTH, that has a high switching threshold of 2.5 V in the example described above.  
         [0047]    Conversely, if the cell CELL 1  is erased and the cell CELL 2  is programmed, it is the cell CELL 2  that is electrically conductive. When the voltage Vcc occurs, the input of the gate INV 4  is pulled down and the signal L 1  goes to 0. In these conditions, the signal SEL goes to 0 if the gate NOR 1  is transparent (VALIDN=0) and the signal RESET delivered by the circuit POR 3  according to the present invention is the signal RSTL, which has a high switching threshold of 1.5 V in the example described above.  
         [0048]    The advantage of this embodiment is that the memory cells CELL 1 , CELL 2  are only used during a very short period of reading these cells and of loading the latch. The memory cells are therefore protected from spurious erasing that could occur if they were permanently exposed to a read voltage.  
         [0049]    Since the voltage Vcc is necessary to load the latch, the circuit SCT can only be used to program the threshold V 2  of the circuit POR 3  after establishing the voltage Vcc. The choice of the high switching threshold V 2 H or V 2 L therefore only relates here to the generation of the signal RESET in a power-down phase. In a power-up phase the signal SEL is maintained on 0 by the gate NOR 1  and of the signal VALIDN, which is maintained on 1.  
         [0050]    The activation of the circuit SCT, corresponding to the reading of the memory cells and the loading of the latch, comprises more particularly three phases shown in FIG. 9. These phases are as follows: Phase T 1 : LATCH=0, PASS=1, EQ=1, and VALIDN=1; Phase T 2 : LATCH=0, PASS=1, EQ=0, and VALIDN=1; and Phase T 3 : LATCH=1, PASS=0, EQ=0, and VALIDN=0.  
         [0051]    The phase T 1  is a phase of balancing the signals L 1 , L 2 . When transistor TN 5  is on, L 1  and L 2  move towards the same value.  
         [0052]    The phase T 2  is a precharge phase that enables each signal to move towards its logic value, 1(Vcc) or 0 (ground), imposed by the differential data loaded into the memory cells. The signal L 1  (SEL) moves towards 1 if the cell CELL 1  is programmed and the cell CELL 2  erased, and moves towards 0 in the opposite case. The signal L 2  moves towards the opposite logic value.  
         [0053]    The phase T 3  is a loading and locking phase in which the cells CELL 1 , CELL 2  are insulated from the rest of the circuit (TN 3 , TN 4  off) while the latch is made active by the change to 1 of the signal LATCH (transistor TN 6  on). The gate NOR 1  is made transparent during the phase T 3 , by taking the signal VALIDN to 0 immediately after the latch is made active. The signal SEL sets to a logic value that depends on the data loaded into the latch.  
         [0054]    These three phases are triggered by the control circuit after the rise in the supply voltage Vcc (power-up). The signal RESET delivered to the integrated circuit when the voltage Vcc rises is the signal RSTL, as the default value of the signal SEL is 0. The activation of the select control circuit SCT can be caused, for example, in response to a select command received by the integrated circuit. The latch then receives the data that depends on the differential configuration of the memory cells CELL 1 , CELL 2  and the signal VALIDN is set to 0. The circuit POR 3  according to the present invention then reacts to a power-down according to the value of the signal SEL, to deliver the signal RESET when the voltage Vcc goes below the threshold V 2 H (signal RSTH) or the threshold V 2 L (signal RSTL).  
         [0055]    The wiring diagram of the circuit SCT is represented in FIG. 6B. The gate INV 3  comprises two transistors TP 7 , TN 7  in series, respectively of the PMOS and NMOS type, and the gate INV 4  comprises two transistors TP 8 , TN 8  in series, respectively of the PMOS and NMOS. In a precharge phase, the transistors TN 3 , TN 4  are on and the transistors TN 5  and TN 6  are off. The transistors TN 7 , TN 8  are floating. In the precharge phase, the circuit SCT therefore only comprises, as active elements, the PMOS transistors TP 7 , TP 8  and the cells CELL 1 , CELL 2 . Each PMOS transistor has its gate G connected to the drain D of the other PMOS transistor, and its drain D connected to the input IN 1  of a memory cell.  
         [0056]    [0056]FIG. 7 represents an example of memory cell CELL A  architecture applicable to each cell CELL 1 , CELL 2  of the circuit SCT. The cell CELL A  has a structure that is well known in itself, such as an EEPROM type. It comprises floating-gate transistors FGT 1 , FGT 2 , FGT 3 , FGT 4 , access transistors AT 1 , AT 2 , AT 3 , AT 4  and a gate control transistor CGT. The floating-gate transistors FGT 1  to FGT 4  have their floating gates interconnected.  
         [0057]    The erasing programming input IN 2  of the cell CELL A  comprises three inputs IN 21 , IN 22 , IN 23 . The control gates of the transistors FGT 1  to FGT 4  are linked to the input IN 22  through the transistor CGT. The gates of the transistors AT to AT 4  and the gate of the transistor CGT are linked to the input IN 23 . The drains of the transistors FGT 2 , FGT 3 , FGT 4  are linked to the input IN 1  through the access transistors, respectively AT 2 , AT 3 , AT 4 , while their sources are linked to a source line SL. The drain of the transistor FGT 1  is linked to the input IN 21  through the access transistor AT 1 , while its source is linked to the source line SL.  
         [0058]    The operations of erasing and programming the memory cell CELL A  comprise the injection or the extraction of electric charges in the floating gates by the tunnel effect. For this purpose, a high voltage Vpp on the order of 8 to 15 V (depending on the technology) is applied to the transistor FGT 1 . The erasing or the programming of the transistor FGT 1  leads to the erasing or the programming of the transistors FGT 2  to FGT 4 , the floating gates of which are connected to that of the transistor FGT 1 . The transistor FGT 1  is, for example, programmed by applying the voltage Vpp to its drain through the access transistor AT 1  while its gate is taken to ground through the transistor CGT. The transistor FGT 1  is, for example, erased by applying the voltage Vpp to its gate while its source is taken to ground. Various other methods of erasing or programming may be provided by those skilled in the art.  
         [0059]    Preferably, these operations of erasing and programming are not made available to the end user. They are performed by the manufacturer during a test phase of the integrated circuit, before it is fielded.  
         [0060]    Once the operations of erasing and programming have been performed, the cell is put into a read configuration. The input IN 21  is taken to a high impedance. The input IN 22  is connected to ground. The input IN 23  receives a bias voltage equal or proportional to Vcc. The source line SL is connected to ground. In this configuration, the cell is on or off between the input IN 1  and the source line (ground) depending on whether it has been programmed or erased.  
         [0061]    The connections enabling the read configuration to be implemented are of a dynamic type and are controlled by a specific element provided in the integrated circuit, such as one part of an EEPROM memory decoder, for example. In this case, the cell only becomes read accessible after the rise in the voltage Vcc, when the specific element is operational. The choice of the threshold V 2 H or V 2 L for sending the signal RESET relates to the power-down phases. In practice, this only has a relative importance since, as explained above, the need to choose a high switching threshold V 2  corresponding to the intended application mainly corresponds to a need to reset to zero during the power-down phase. The value 0 is imposed by default on the signal SEL upon power-up, by the signal VALIDN, as described above.  
         [0062]    [0062]FIG. 8 represents another example of a memory cell CELL B  architecture applicable to the cells CELL 1 , CELL 2  of the circuit SCT. The cell CELLS is of the FLASH type and does not comprise access transistors and gate control transistors. The floating-gate transistors FGT 1 , FGT 2 , FGT 3 , FGT 4  are linked to the read input IN 1 . The erasing/programming input IN 2  of the cell CELL B  comprises one input IN 21  and one input IN 22 . The drain of the transistor FGT 1  is linked to the input IN 21 . The control gates of the transistors FGT 1  to FGT 4  are linked to the input IN 22 . The programming of the transistor FGT 1  is performed by hot carrier injection instead of by the tunnel effect, while it is erased by the tunnel effect. As the floating gates of the other transistors FGT are connected as above for the transistor FGT 1 , the erasing or the programming of the transistor FGT 1  leads to the erasing or the programming of the other transistors FGT.  
         [0063]    Preferably, the transistors TN 3 , TN 4  of the circuit SCT (FIG. 6A, 6B) are used as cascode transistors to prevent the application of an excessively high voltage to the drains of the floating-gate transistors of the cells CELL A  or CELL B . Such a voltage could, in fact, lead to them being spuriously erased (if they are in the programmed state). For that purpose, a specific bias circuit can be provided to control the value in voltage of the signal PASS applied to the gates of the transistors TN 3 , TN 4 , which must not exceed a certain value, such as 2V, for example.  
         [0064]    Variations of the memory cells CELL 1 , CELL 2  of the circuit POR 3  according to the present invention may be made. The provision in each cell of several floating-gate transistors connected in parallel to the read input IN 1  allows a current of sufficient intensity to switch the latch INV 3 /INV 4  to be drained. However, it remains possible to provide a memory cell that only comprises a single floating-gate transistor connected to the read input IN 1 , if this transistor is provided to drain a substantial current.  
         [0065]    The cells CELL 1 , CELL 2  can be integrated into an EEPROM or FLASH memory array comprising various other memory cells. The cells CELL 1 , CELL 2  may also be elements of an integrated circuit configuration register, comprising other non-volatile memory cells used to define the parameters of certain electrical characteristics of the integrated circuit.  
         [0066]    It will be understood by those skilled in the art that variations of the circuit POR 3  according to the present invention may be made. Therefore, in the description above, the signal RESET is obtained by selecting the two signals SRTH, RSTL by the circuit MUX. However, the signal RESET can also be obtained by logically combining the two signals RSTH, RSTL and inhibiting one of the signals according to the state of the memory cell.  
         [0067]    [0067]FIG. 10 represents a circuit POR 4  showing this other embodiment. The circuit POR 4  comprises the two switching stages S 1 , S 1 ′ described above, respectively delivering the signals NRSTH and NRSTL. It also comprises a NOR-type gate A 4  with two inputs E 1 , E 2 , the output of which delivers the signal RESET. The signal NRSTH is applied to the input E 1  of the gate A 4  while the signal NRSTL is applied to an inverting gate INV 5 . The output of the gate INV 5  is applied to the input of a latch comprising two inverting gates INV 6 , INV 7  connected head-to-tail. The output of the latch is applied to the input E 2  of the gate A 4 .  
         [0068]    The gates INV 5  to INV 7  are all supplied by the voltage Vcc. However, the ground terminal of the gate INV 5  is linked to ground through a memory cell CELL 3 . The memory cell CELL 3  is of the type described above, and conforms to one of the cells CELL A or CELL B , for example. It has a read input IN 1  connected to the ground terminal of the gate INV 5  and an erasing programming input IN 2 .  
         [0069]    When the cell is programmed and is therefore on, the gate INV 5  is electrically supplied. The signal NRSTL is copied via the gate INV 5  and the latch INV 6 /INV 7  on the input E 2  of the gate A 4 . In this case, the signal RESET delivered by the circuit POR 4  is equal to: 
         RESET=/(NRSTH+NRSTL)=/NRSTH*/NRSTL 
         [0070]    i.e.: 
         RESET=RSTH*RSTL 
         [0071]    The signal RESET is therefore the result of combining, by an AND function, the two reset signals RSTH and RSTL.  
         [0072]    Referring now to FIGS. 3 and 4, it can be seen that in the presence of a positive or negative ramp of the voltage Vcc, the duration of the signal RSTL is shorter than the signal RSTH, since it has a high switching threshold V 2 L that is lower than the threshold V 2 H of the signal RSTH. Hence, the signal RESET copies the signal RSTL since the signal RESET cannot be on 1 while the signal RSTL is not on 1 itself. In other terms, the signal RESET is equal to the signal RSTL when the memory cell CELL 3  is programmed.  
         [0073]    When the memory cell CELL 3  is in the erased state and is therefore not on, the gate INV 5  is not supplied and its output is at high impedance. To force the input E 2  of the gate A 4  to zero, a transistor TN 10  is provided between the output of the latch INV 6 /INV 7  and ground. This transistor is driven by the output of an inverting gate INV 8  supplied by the voltage Vcc, which receives the signal NRSTL at its input. Thus, when the signal NRSTL goes to 1, the transistor TN 10  goes into an on state and forces the output of the latch and the input E 2  of the gate A 4  to zero. The signal RESET delivered by the circuit POR 4  is in this case equal to: 
         RESET=/(NRSTH+0)=/NRSTH*/0=/NRSTH*1=/NRSTH 
         [0074]    i.e.: 
         RESET=RSTH 
         [0075]    In summary, the signal RESET is equal to the signal RSTH when the memory cell CELL 3  is erased, and is equal to the signal RSTL when the memory cell CELL 3  is programmed.  
         [0076]    It should be noted that the selection between the two levels V 2 L, V 2 H of triggering the signal RESET can be performed in this embodiment not only during the power-down phase, but also during the power-up phase. In this case, the source line SL of the memory cell CELL 3  is connected to ground and the cell is in the selected state. The cell is selected by applying determined voltages to the inputs IN 22  and IN 23  in FIG. 7, or to the input IN 22  in FIG. 8. This selection can be performed automatically by the decoders of a memory array in which the cell CELL 3  can be arranged. This can be done easily by controlling the signal RESET itself using a source line switch and a line decoder. In this case, when the signal RESET goes back to 0, the memory cell CELL 3  is no longer selected but the state of the cell remains stored by the latch INV 6 /INV 7 .  
         [0077]    It will be understood by those skilled in the art that variations of the circuits POR 3  and POR 4  that have just been described may be made, particularly as far as the active value of the signal RESET, the logic gates used, the structure of the switching stages S 1 , S 1 ′, the structure of the memory cell or of the memory cells used, as well as the other components of these circuits are concerned.