Abstract:
In one embodiment, a level shifter has a cascade voltage-switching logic (CVSL) structure having two pull-up networks connected in a positive feedback arrangement, each pull-up network connected in series with a corresponding pull-down network. The effective transistor sizes of the two pull-up networks are different such that, at power on, if a level-shifter node connected to an output inverter initially has an in-between voltage level (e.g., at or near the midpoint between the output voltage-domain power-supply voltage and ground), the node voltage will quickly be driven either high or low (depending on the level-shifter design and other initial conditions), thereby reducing leakage current through the output inverter that could otherwise be maintained if the pull-up networks had the same effective transistor size. In addition, one of the pull-down networks has an additional pull-down transistor to accelerate node-voltage driving away from the midpoint to ensure proper operation of the level shifter.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to electronics and, more specifically but not exclusively, to level shifters. 
         [0003]    2. Description of the Related Art 
         [0004]    This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art. 
         [0005]      FIG. 1  shows a schematic circuit diagram of a prior-art level shifter  100  having a conventional cascade voltage-switching logic (CVSL) structure that converts an input signal in in an input voltage domain defined by input power supply voltage vccq 1  into an output signal out in an output voltage domain defined by output power supply voltage vccq 2 , where vccq 2  is different from vccq 1 . 
         [0006]    When input signal in is low (e.g., ground), inverted signal in 2   b  is high (e.g., vccq 1 ), and double-inverted signal in 2   bb  is low. As such, n-type transistor (e.g., NMOS) n 1  will be on, and n-type transistor n 2  will be off. In that case, node nd 1  will be driven towards ground through n 1 , which turns on p-type transistor (e.g., PMOS) p 2 , which in turn drives node nd 2  towards vccq 2 , which ensures that p-type transistor p 1  is off. With node nd 1  driven low, output inverters inv 3  and inv 4  will operate to drive output signal out low. 
         [0007]    When input signal in is high (e.g., vccq 1 ), inverted signal in 2   b  is low, and double-inverted signal in 2   bb  is high. As such, transistor n 1  will be off, and transistor n 2  will be on. In that case, node nd 2  will be driven towards ground through n 2 , which turns on transistor p 1 , which in turn drives node nd 1  towards vccq 2 , which ensures that transistor p 2  is off. With node nd 1  driven towards vccq 2 , inverters inv 3  and inv 4  will drive output signal out towards vccq 2 . 
         [0008]    Thus, when input signal in is low in the vccq 1  voltage domain, the output signal out is low in the vccq 2  voltage domain, and, when input signal in is high in the vccq 1  voltage domain, the output signal out is high in the vccq 2  voltage domain. In this way, level shifter  100  converts input signal in in the vccq 1  voltage domain into output signal out in the vccq 2  voltage domain. 
         [0009]    Transistors p 1  and p 2  are considered to be part of two pull-up networks connected in a positive feedback arrangement, while transistors n 1  and n 2  are considered to be part of two pull-down networks, wherein the pull-down network of n 1  is connected in series with the pull-up network of p 1 , and the pull-down network of n 2  is connected in series with the pull-up network of p 2 . When level shifter  100  is operating properly, when input signal in is low, the pull-down network of n 1  and the pull-up network of p 2  are on, and the pull-down network of n 2  and the pull-up network of p 1  are off, and, when input signal in is high, the pull-down network of n 1  and the pull-up network of p 2  are off, and the pull-down network of n 2  and the pull-up network of p 1  are on. 
         [0010]    When an integrated circuit containing level shifter  100  is initially powered on, it is possible for the power supply voltages vccq 1  and vccq 2  to rise at different rates and at different times towards their desired (i.e., normal) operating levels. In some circumstances, this can lead to certain undesirable operations of level shifter  100 . In particular, undesirable operations can occur when vccq 2  approaches its normal operating level faster than vccq 1  approaches its normal operating level. 
         [0011]    Assume the extreme situation in which vccq 2  has reached its normal operating level, while vccq 1  is still at ground (e.g., 0 volts). In that case, inverters inv 1  and inv 2  will not be operating. With input signal in low, both inverted signals in 2   b  and in 2   bb  will also be low, and transistors n 1  and n 2  will both be off. As a result, the voltages at nodes nd 1  and nd 2  will be indeterminate (i.e., the voltages could independently be high, low, or in between). If the voltages at both nodes nd 1  and nd 2  are between vccq 2  and ground (e.g., about ½ of vccq 2 ), then those voltages could stay at those in-between levels for an extended period of time, during which inverter inv 3  might not operate properly and could result in an undesirably large leakage current for an undesirable length of time from vccq 2  to ground through inverter inv 3 . 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    Other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
           [0013]      FIG. 1  shows a schematic circuit diagram of a prior-art level shifter; and 
           [0014]      FIGS. 2-4  show schematic circuit diagrams of level shifters according to different embodiments of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    In a conventional level shifter, such as level shifter  100  of  FIG. 1 , the sizes of the transistors in the two pull-down networks are the same (i.e., n 1  equals n 2 ), and the sizes of the transistors in the two pull-up networks are the same (i.e., p 1  equals p 2 ). According to certain embodiments of the disclosure, however, the effective sizes of the two pull-up networks are different. 
         [0016]      FIG. 2  shows a schematic circuit diagram of a level shifter  200  according to one embodiment of the disclosure. Like level shifter  100  of  FIG. 1 , level shifter  200  converts an input signal in in an input voltage domain defined by input power supply voltage vccq 1  (e.g., 0.6V in one exemplary embodiment) into an output signal out in an output voltage domain defined by output power supply voltage vccq 2  (e.g., 0.8V in the one exemplary embodiment), where vccq 2  is different from vccq 1 . 
         [0017]    Level shifter  200  is identical to level shifter  100  of  FIG. 1 , except for the inclusion of p-type transistor p 3  and n-type transistor n 3  in level shifter  200 . As shown in  FIG. 2 , transistor p 3  is connected in parallel with transistor p 2  with the source, drain, and gate of p 3  connected to the same respective nodes as the source, drain, and gate of p 2 . Since transistors p 1  and p 2  have the same size, the addition of p 3  makes the effective size of the pull-up network of transistors p 2  and p 3  larger than the effective size of the pull-up network of transistor p 1 . 
         [0018]    When power-supply voltages vccq 1  and vccq 2  are at their respective normal operating voltage levels, level shifter  200  will operate as described previously for the normal operations of level shifter  100  of  FIG. 1 . If, however, for example, during power up, vccq 2  approaches its normal voltage level sooner than vccq 1  approaches its normal voltage level, level shifter  200  will not suffer the same undesirable operations as level shifter  100 . 
         [0019]    In particular, assume again the extreme situation in which vccq 2  has reached its normal operating level, while vccq 1  is still at ground. In that case, inverters inv 1  and inv 2  will again not be operating, and, with input signal in low, both inverted signals in 2   b  and in 2   bb  will also be low, and transistors n 1  and n 2  will both be off. Here, too, as a result, the voltages at nodes nd 1  and nd 2  will be initially indeterminate (i.e., the voltages could independently be high (e.g., at or near vccq 2 ), low (e.g., at or near ground), or in between (e.g., at or near ½ of vccq 2 ). There are nine different possible initial, power-up situations corresponding to the nine different possible combinations of (i) nd 1  being high, in between, or low and (ii) nd 2  being independently high, in between, or low. 
         [0020]    If nd 1  and nd 2  are both initially high, then p 1 , p 2 , and p 3  will be off, and n-type transistor n 3  will turn on, which will drive nd 1  low, which will turn on p 2  and p 3 , thereby ensuring that nd 2  stays high, that p 1  stays off. With nd 1  low, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0021]    If nd 1  is initially high, but nd 2  is initially in between, then p 2  and p 3  will be off, but p 1  could be partially on. With p 1  partially on, nd 1  will stay high, thereby keeping p 2  and p 3  off. With nd 1  high, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0022]    If nd 1  is initially high, but nd 2  is initially low, then p 2  and p 3  will be off, but p 1  will be on. With p 1  on, nd 1  will stay high, thereby keeping p 2  and p 3  off. With nd 1  high, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0023]    If nd 1  is initially in between, but nd 2  is initially high, then p 2  and p 3  could be partially on, while p 1  is off. With p 2  and p 3  partially on, nd 2  will stay high, and n 3  will turn on, which will drive nd 1  from in between to low, which will turn p 2  and p 3  fully on, thereby ensuring that nd 2  stays high, that p 1  stays off, and that nd 1  stays low. With nd 1  low, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0024]    If both nd 1  and nd 2  are initially in between, then p 1 , p 2 , and p 3  could all be partially on. Since the pull-up network of p 2  and p 3  is larger than the pull-up network of p 1 , nd 2  will be driven high through both p 2  and p 3  faster than nd 1  will be driven high through smaller p 1 . As such, n 3  will begin to turn on, thereby driving nd 1  low and turning p 2  and p 3  fully on, which drives nd 2  high even faster, which turns p 1  off and n 3  fully on, which drives nd 1  low even faster. With nd 1  low, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0025]    If nd 1  is initially in between, but nd 2  is initially low, then p 1  will be on. With p 1  on, nd 1  will be driven high, which ensures that p 2  and p 3  will be off. With nd 1  high, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0026]    If nd 1  is initially low, but nd 2  is initially high, then p 2  and p 3  will be on and p 1  will be off. With p 2  and p 3  on, nd 2  will be driven high, thereby ensuring that p 1  will stay off and turning on n 3 , which ensures that p 2  and p 3  stay on and nd 1  stays low. With nd 1  low, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0027]    If nd 1  is initially low, but nd 2  is initially in between, then p 2  and p 3  will be on, which will drive nd 2  high, thereby ensuring that p 1  is off. With nd 2  high, n 3  will turn on, thereby ensuring that nd 1  stays low and that p 2  and p 3  stay on. With nd 1  low, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0028]    If nd 1  and nd 2  are both initially low, then p 1 , p 2 , and p 3  will all be initially on. Because the pull-up network of p 2  and p 3  is larger than the pull-up network of p 1 , nd 2  will be driven high faster than nd 1  is driven high. As a result, n 3  will turn on, thereby driving nd 1  low, thereby ensuring that p 2  and p 3  will stay on and nd 2  stays high, turning off p 1 . With nd 1  low, inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0029]    Note that, if, during power up, vccq 1  approaches its normal voltage level sooner than vccq 2  approaches its normal voltage level, level shifter  200  will also ensure that node nd 1  is quickly driven either high or low. Assume, here, the extreme situation that vccq 1  is at its normal voltage level, while vccq 2  is at ground. 
         [0030]    In that case, if input signal in is low, then in 2   b  will be high and in 2   bb  will be low, and n 1  will be on and n 2  will be off. With n 1  on, node nd 1  will be driven low, and inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0031]    Similarly, if input signal in is high, then in 2   b  will be low and in 2   bb  will be high, and n 1  will be off and n 2  will be on. With n 2  on, node nd 2  will be driven low, which will keep n 3  off and eventually turn p 1  on, thereby driving node nd 1  high, such that inverters inv 3  and inv 4  will both operate properly without any unreasonably high and lengthy leakage currents. 
         [0032]    In this way, the inclusion of transistors p 3  and n 3  in level shifter  200  ensures that the voltage at node nd 1  will (i) stay low if it is initially low and (ii) be driven quickly to one of high and low if it is initially in between or high, depending on the initial voltage at node nd 2 . In particular, the inclusion of transistor p 3 , which results in the pull-up network of p 2  and p 3  being larger than the pull-up network of p 1 , ensures that the voltage at node nd 1  will not stay in between ground and vccq 2  for very long, thereby avoiding undesirably high and lengthy leakage current through inverter inv 3 . Transistor n 3  can be considered to be part of the pull-down network of transistor n 1 , since both n 1  and n 3  are connected to pull down node nd 1 . 
         [0033]    Adding a second transistor (i.e., p 3 ) to the pull-up network of p 2  is one way to create a level shifter in which the pull-up network of p 2  is larger than the pull-up network of p 1 . Another way to effectively achieve the same result is to replace transistor p 2 , which has the same size as transistor p 1 , with a larger transistor. 
         [0034]      FIG. 3  shows a schematic circuit diagram of a level shifter  300  according to another embodiment of the disclosure. Like level shifter  200  of  FIG. 2 , level shifter  300  converts an input signal in in the vccq 1  voltage domain into an output signal out in the vccq 2  voltage domain, where vccq 2  is different from vccq 1 . Level shifter  300  is identical to level shifter  200 , except that transistors p 2  and p 3  of  FIG. 2  are replaced by a single transistor p 2 ′ having a size equivalent to the effective combination of transistors p 2  and p 3 . Note that transistor n 3  of  FIG. 3  is identical to transistor n 3  of  FIG. 2 . As such, level shifter  300  operates in a substantially identical manner as level shifter  200 . 
         [0035]    One goal of the present disclosure is to provide a level shifter that ensures that, when node nd 1  happens to be at an in-between voltage level at or soon after power on, it does not stay at that in-between voltage level for very long, but is instead quickly driven either high or low to avoid unreasonably high and lengthy leakage currents through the level shifter&#39;s output inverters. Level shifters  200  and  300  of  FIGS. 2 and 3  achieve that goal by having the pull-up network of transistor p 1  be smaller than the level-shifter&#39;s other pull-up network. Another way to achieve that same goal is to implement level shifters in which the pull-up network of transistor p 1  is larger than the level-shifter&#39;s other pull-up network. 
         [0036]      FIG. 4  shows a schematic circuit diagram of a level shifter  400  according to yet another embodiment of the disclosure. Like level shifters  200  and  300  of  FIGS. 2 and 3 , level shifter  400  converts an input signal in in the vccq 1  voltage domain into an output signal out in the vccq 2  voltage domain, where vccq 2  is different from vccq 1 . Level shifter  400  is identical to level shifter  200 , except that (i) the extra p-type transistor p 3  is added to the pull-up network of transistor p 1  (instead of to the pull-up network of transistor p 2 ) and (ii) the extra n-type transistor n 3  is configured such that its source is connected to node nd 1  and its gate is connected to node nd 2  (instead of the other way around as with transistor n 3  of  FIG. 2 ). 
         [0037]    Level shifter  400  will operate in a similar manner as level shifters  200  and  300 , except that, because the pull-up network of p 1  (and p 3 ) is larger than the pull-up network of p 2 , there are certain situations in which node nd 1  will be driven high instead of low as in  FIGS. 2 and 3 . Significantly, however, as with the other two level shifters, when node nd 1  happens to be at an in-between voltage level at or soon after power on, it does not stay at that in-between voltage level for very long, but is instead quickly driven either high or low to avoid unreasonably high and lengthy leakage currents through the level shifter&#39;s output inverters. 
         [0038]    Although not shown explicitly in a figure, those skilled in the art will understand that, in another embodiment, transistors p 1  and p 3  of  FIG. 4  can be replaced by a single, equivalent transistor p 1 ′ that is larger than the size of transistor p 2 . Such alternative embodiment will operate identically to level shifter  400 . 
         [0039]    Level shifters of the present disclosure can be implemented for applications in which the output voltage domain is smaller than the input voltage domain (i.e., vccq 2 &lt;vccq 1 ) as well as applications in which the output voltage domain is greater than the input voltage domain (i.e., vccq 2 &gt;vccq 1 ). 
         [0040]    Level shifters of the present disclosure can be implemented in any suitable integrated circuit, such as (without limitation) field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and general-purpose microprocessors. 
         [0041]    Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. 
         [0042]    Also, for purposes of this disclosure, it is understood that all gates are powered from a fixed-voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources. 
         [0043]    Signals and corresponding nodes, ports, or paths may be referred to by the same name and are interchangeable for purposes here. 
         [0044]    Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors. 
         [0045]    As used in this specification and claims, the term “channel node” refers generically to either the source or drain of a metal-oxide semiconductor (MOS) transistor device (also referred to as a MOSFET), the term “channel” refers to the path through the device between the source and the drain, and the term “control node” refers generically to the gate of the MOSFET. Similarly, as used in the claims, the terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bi-polar device when an embodiment of the invention is implemented using bi-polar transistor technology. 
         [0046]    Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value or range. 
         [0047]    It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims. 
         [0048]    In this specification including any claims, the term “each” may be used to refer to one or more specified characteristics of a plurality of previously recited elements or steps. When used with the open-ended term “comprising,” the recitation of the term “each” does not exclude additional, unrecited elements or steps. Thus, it will be understood that an apparatus may have additional, unrecited elements and a method may have additional, unrecited steps, where the additional, unrecited elements or steps do not have the one or more specified characteristics. 
         [0049]    The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
         [0050]    Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
         [0051]    The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to non-statutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.