Abstract:
A sequential linear LED driver circuit is provided. The sequential linear LED driver circuit may include a plurality of current sinks, wherein each of the plurality of current sinks is configured to be coupled to a segment of a string of light-emitting diodes (LEDs), and a voltage divider that generates a plurality of reference voltages, wherein each of the plurality of reference voltages is applied to a respective current sink of the plurality of current sinks. The output of each current sink of the plurality of current sinks may be connected at a summing node.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit of U.S. Provisional Patent Application No. 62/234,081, filed on Sep. 29, 2015, which is incorporated herein by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present disclosure relates generally to a sequential linear LED driver circuit. 
       SUMMARY 
       [0003]    A sequential linear LED driver, or “driver” for short, provides means for driving an LED string from a rectified AC line voltage. The driver lights the LED string either in part or in full depending on the magnitude of the rectified voltage. The driver includes a set of linear current sinks for coupling to the LED string and to taps located within the LED string. Accordingly, the LED string is divided into a set of LED segments. 
         [0004]    The division of the LED string into a set of LED segments allows the driver to light the LED string in part or in full. As the rectified AC voltage rises or falls, a respectively increasing or decreasing number of segments is energized by commuting current flow from one current sink to an adjacent current sink. The driver generally enables the current sink which maximizes the number of LED segments that can be energized with a given magnitude of the rectified AC line voltage, thereby maximizing utilization of the LED string and minimizing power dissipation within a current sink. 
         [0005]    However, a problem occurs when the commutation of current between current sinks is not timed properly. Poor timing results in spikes or gaps in the current drawn from the AC line, thereby potentially generating excess electromagnetic interference (EMI). For example, the line current spikes upward when two adjacent current sinks briefly conduct current simultaneously, as shown in the left-most current waveform of  FIG. 1 . Similarly, the line current spikes downward when two adjacent current sinks briefly do not conduct during commutation, as shown in the right-most current waveform of  FIG. 1 . Accordingly, a circuit is needed, which enables a smooth commutation of the line current from one current sink to the next, as shown for example in the center current waveform of  FIG. 1 . 
         [0006]    According to an aspect of one or more exemplary embodiments, there is provided a circuit that coordinates the commutation of current between two adjacent current sinks by forcing all current sink currents to pass through a summing node. The summing of all current sink currents facilitates smooth commutation of current between current sinks and results in an AC line current without spikes and gaps. According to one or more exemplary embodiments, the commutation circuit may rely only on the current sink currents for coordinating the commutation of the line current between current sinks. The commutation circuit according to one or more exemplary embodiments, may not need to rely on knowledge of the rectified AC line voltage or the voltage at the LED string taps, thereby avoiding improper timing due to voltage measurement inaccuracy. Furthermore, the cost of measuring and processing high voltages may be avoided. 
         [0007]    According to one or more exemplary embodiments, a sequential liner LED driver circuit may include a plurality of current sinks, wherein each of the plurality of current sinks is configured to be coupled to a string of light-emitting diodes (LEDs) and to taps located within the LED string, and a voltage divider that generates a plurality of reference voltages, wherein each of the plurality of reference voltages is applied to a respective current sink of the plurality of current sinks. The output of each current sink of the plurality of current sinks may be connected at a summing node for establishing the sum of the currents flowing by way of the plurality of current sinks. 
         [0008]    Each current sink may include a control amplifier having a reference or positive input terminal, a feedback or negative input terminal, an output terminal, and a field effect transistor (FET) having a gate terminal, a source terminal, and a drain terminal (or a bipolar transistor with like terminals). The output of the control amplifier of each current sink may be coupled to the gate terminal of the FET in the respective current sink. Each of the plurality of reference voltages may be applied to the reference terminal of the control amplifier of a respective current sink. The source terminal of each FET may be coupled to the feedback terminal of the control amplifier of the respective current sink. The drain terminal of each FET may be coupled to the LED string or a tap located within the LED string. The source terminal of each FET may be coupled to the summing node. 
         [0009]    According to one or more exemplary embodiments, the reference terminal of each control amplifier may be connected to a first reference voltage. The feedback terminal of each control amplifier may be connected to one of the plurality of reference voltages. The feedback terminal of a first control amplifier of a first current sink may be coupled to the summing node. A first end of the voltage divider is coupled to the summing node, and a second end of the voltage divider is connected to ground. The sequential LED driver circuit may also include a resistor having a first end coupled to the summing node and a second end coupled to ground. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0010]      FIG. 1  illustrates a series of tap current waveform showing unacceptably high, ideal, and unacceptably low tap current in the tap current from one tap to another tap. 
           [0011]      FIG. 2  illustrates a sequential linear LED driver circuit according to an exemplary embodiment. 
           [0012]      FIG. 3  illustrates a timing diagram showing the operation of the sequential linear LED driver circuit according to the exemplary embodiment of  FIG. 2 . 
           [0013]      FIG. 4  illustrates a sequential linear LED driver circuit according to another exemplary embodiment. 
           [0014]      FIG. 5  illustrates a sequential linear LED driver circuit according to yet another exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0015]    Reference will now be made in detail to the following exemplary embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The exemplary embodiments may be embodied in various forms without being limited to the exemplary embodiments set forth herein. Descriptions of well-known parts are omitted for clarity. 
         [0016]      FIG. 2  depicts a sequential linear LED driver circuit according to an exemplary embodiment. Referring to  FIG. 2 , the circuit according to the exemplary embodiment may include a first current sink  100 , a second current sink  105 , a third current sink  110 , and a fourth current sink  115 . Each of the current sinks may include a control amplifier and field effect transistor (FET). The reference input of each control amplifier may be connected to a resistive voltage divider  120 . The control amplifiers may be connected to the resistive voltage divider  120  at various points, such that V REF4 &gt;V REF3 &gt;V REF2 &gt;V REF1 , where V REF4  is connected to the reference input of control amplifier  116  of fourth current sink  115 , V REF3  is connected to the reference input of control amplifier  111  of third current sink  110 , V REF2  is connected to the reference input of control amplifier  106  of second current sink  105 , and V REF1  is connected to the reference input of control amplifier  101  of first current sink  100 . The output of each control amplifier  101 ,  106 ,  111 , and  116  may be respectively connected to the gate terminals of FETs  102 ,  107 ,  112 , and  117  of first current sink  100 , second current sink  105 , third current sink  110 , and fourth current sink  115 , respectively. The source terminals of FETs  102 ,  107 ,  112 , and  117  may be connected to the feedback input of control amplifier  101 ,  106 ,  111 , and  115 , respectively. The drain terminal of each FET may be connected between two segments of an LED string. For example, the drain of FET  102  may be connected between a first segment of LEDs SEG 1  and a second segment of LEDs SEG 2 . The drain of FET  107  may be connected between second segment of LEDs SEG 2  and a third segment of LEDs SEG 3 . The drain of FET  112  may be connected between third segment of LEDs SEG 3  and a fourth segment of LEDs SEG 4 . The drain of FET  117  may be connected to an output of the fourth segment of LEDs SEG 4 . The sources of FETs  102 ,  107 ,  112 , and  117  may be connected at to each other at a single summing node CS. 
         [0017]      FIG. 3  depicts the operation of the circuit according to the exemplary embodiment of  FIG. 2 . At time  0 , input voltage V RAC  is equal to 0V, which is insufficient voltage to forward bias the first segment of LEDs SEG 1 . At time  1 , V RAC  reaches a level which is sufficient to forward bias the first segment of LEDs SEG 1 , but insufficient to enable current regulation. Going forward in time, the voltage V CS  at the summing node CS begins to rise, as does the current sink current I TAP1  through FET  102 . At time  2 , the first current sink  100  begins to regulate current as voltages V CS  and V REF1  are in approximate equilibrium. 
         [0018]    At time  3 , V RAC  rises to the level which is sufficient to forward bias the second segment of LEDs SEG 2 , causing current I TAP2  to flow through FET  107 . Current I TAP2  increases the voltage V CS  at the summing node CS. In response to the increased voltage V CS , the first current sink  100  decreases the current I TAP1  so that V CS  and V REF1  remain in approximate equilibrium. Current I TAP2  increases at roughly the same rate at which current I TAP1  decreases, causing the total current I SUM  at summing node CS to remain approximately constant. At time  4 , V RAC  reaches a level that causes current I TAP2  to increase to the point where current I TAP1  is zero. At this point, the first current sink  100  falls out of regulation, and V CS  rises above V REF1  causing the first current sink  100  to shut off. At time  5 , V RAC  rises to a level where the second current sink  105  begins regulating, and V CS  and V REF2  are in approximate equilibrium. The process then repeats for the third and fourth current sinks  110  and  115  as input voltage V RAC  rises further, and also operates in reverse as V RAC  passes the peak and starts decreasing. 
         [0019]      FIG. 4  depicts a sequential linear LED driver circuit according to another exemplary embodiment. The circuit of  FIG. 4  is similar to the circuit of  FIG. 2 , except that the reference input of each control amplifier  101 ,  106 ,  111 , and  116  is connected to the same reference voltage V REF , as opposed to differing voltages created by resistive voltage divider  120 . In the circuit of  FIG. 4 , the feedback is attenuated, as the feedback input of each control amplifier  101 ,  106 ,  111 , and  116  is connected to a different point in a resistive voltage divider. One end of the resistive voltage divider is connected to the summing node CS, to which the feedback input of the first current sink  100  is connected, while the other end of the resistive voltage divider is connected to ground. 
         [0020]      FIG. 5  depicts a sequential linear LED driver circuit according to yet another exemplary embodiment. In the exemplary embodiment of  FIG. 5 , the circuit is similar to the circuit of  FIG. 2 , except that the feedback divider is combined with resistor R SET . The circuit of the exemplary embodiment shown in  FIG. 5  includes four resistors R SET1 , R SET2 , R SET3 , and R SET4 . The feedback input of control amplifier  101  is connected to R SET1 , the feedback input of control amplifier  106  is connected between R SET1  and R SET2 , the feedback input of control amplifier  111  is connected between R SET2  and R SET3 , and the feedback input of control amplifier  116  is connected between R SET3  and R SET4 . Although current sense points CS 1 , CS 2 , CS 3 , and CS 4  are different for each current sink, all tap currents are summed at a summing node. 
         [0021]    Although the inventive concepts of the present disclosure have been described and illustrated with respect to exemplary embodiments thereof, it is not limited to the exemplary embodiments disclosed herein and modifications may be made therein without departing from the scope of the inventive concepts.