Abstract:
A semiconductor package comprising multiple stacked substrates having flip chips attached to the substrates with chip-on-board assembly techniques to achieve dense packaging. The substrates are preferably stacked atop one another by electric connections which are column-like structures. The electric connections achieve electric communication between the stacked substrates, must be of sufficient height to give clearance for the components mounted on the substrates, and should preferably be sufficiently strong enough to give support between the stacked substrates.

Description:
BACKGROUND OF THE INVENTION 
     Cross Reference to Related Application 
     This application is a continuation of application Ser. No. 09/233,997, filed Jan. 19, 1999 pending, which is a divisional of application Ser. No. 08/813,467, filed Mar. 10, 1997, now U.S. Pat. No. 5,994,166, issued Nov. 30, 1999. 
    
    
     FIELD OF THE INVENTIN 
     The present invention relates to an apparatus and a method for increasing semiconductor device density. In particular, the present invention relates to a stacked multi-substrate device using a combination of flip chips and chip-on-board assembly techniques to achieve densely packaged semiconductor devices. 
     STATE OF THE ART 
     Chip-On-Board techniques are used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding (“TAB”). Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally, the flip chip has an active surface having one of the following electrical connectors: Ball Grid Array (“BGA”)—wherein an array of minute solder balls is disposed on the surface of a flip chip that attaches to the substrate (“the attachment surface”); Slightly Larger than Integrated Circuit Carrier (“SLICC”)—which is similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (“PGA”)—wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip. The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto. With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J&#39;s are soldered to pads on the surface of the circuit board. 
     Wirebonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape, such as a polyamide, are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination. 
     Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of devices used to fabricate them tends to decrease due to advances in technology even though the functionality of these products increases. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality. 
     In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board despite the reduction of the number of components. This results in more compact designs and form factors and a significant increase in integrated circuit density. However, greater integrated circuit density is primarily limited by the space or “real estate” available for mounting dice on a substrate, such as a printed circuit board. 
     One method of further increasing integrated circuit density is to stack semiconductor dice vertically. U.S. Pat. No. 5,012,323, issued Apr. 30, 1991 to Farnworth, teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative film layer. The wirebonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die must be slightly larger than the upper die such that the die pads are accessible from above through a bonding window in the lead frame such that gold wire connections can be made to the lead extensions. This arrangement has a major disadvantage from a production standpoint as the same size die cannot be used. 
     U.S. Pat. No. 5,291,061, issued Mar. 1, 1994 to Ball (“Ball”), teaches a multiple stacked dice device containing up to four stacked dice supported on a die-attach paddle of a lead frame, the assembly not exceeding the height of current single die packages, and wherein the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice. However, Ball requires long bond wires to electrically connect the stacked dice to the lead frame. These long bond wires increase resistance and may result in bond wire sweep during encapsulation. Also, Ball requires the use of spacers between the dice. 
     U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. (“Fogal”) teaches a multi-chip module that contains stacked die devices, the terminals or bond pads of which are wirebonded to a substrate or to adjacent die devices. However, as discussed with Ball, Fogal requires long bond wires to electrically connect the stacked die bond pads to the substrate. Fogal also requires the use of spacers between the dice. 
     U.S. Pat. Nos. 5,422,435 and 5,495,398 to Takiar et al. (“Takiar”) teach stacked dice having bond wires extending to each other and to the leads of a carrier member such as a lead frame. However, Takiar also has the problem of long bond wires, as well as, requiring specific sized or custom designed dice to achieve a properly stacked combination. 
     U.S. Pat. No. 5,434,745 issued Jul., 18, 1995 to Shokrgozar et al. (“Shokrgozar”) discloses a stackable packaging module comprising a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The substrate/die/spacer combinations are stacked one atop another to form a stacked assembly. The outer edge of the spacer frame has grooves in which a conductive epoxy is disposed. The conductive epoxy forms electric communication between the stacked layers and/or to the final substrate to which the stacked assembly is attached. However, Shokrgozar requires specialized spacer frames and a substantial number of assembly steps, both of which increase the cost of the final assembly. 
     U.S. Pat. No. 5,128,831 issued Jul. 7, 1992 to Fox, III et al. (“Fox”) also teaches a standard die attached to a substrate with a spacer frame placed on the substrate to surround the die. The stacked layers and/or the final substrate are in electric communication with conductive vias extending through the spacer frames. However, Fox also requires specialized spacer frames, numerous assembly steps, and is limited in its flexibility to utilize a variety of dice. 
     U.S. Pat. No. 5,513,076 issued Apr. 30, 1996 to Wether (“Wether”) teaches the use of interconnecting assemblies to connect integrated circuits in an integrated manner. 
     As has been illustrated, none of the cited prior art above uses or teaches flip chip manufacturing methods for attaching dice together in a stacked manner to form a stacked die assembly. 
     Therefore, it would be advantageous to develop a stacking technique and assembly for increasing integrated circuit density using a variety of non-customized die configurations in combination with commercially-available, widely-practiced semiconductor device fabrication techniques. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention relates to a stacked multi-substrate device using combined flip chips and chip-on-board assembly techniques to achieve densely packaged semiconductor devices, and a method for making same. In this invention, multiple substrates are stacked atop one another. The substrates can include a plurality of semiconductor dice disposed on either surface of the substrates. The substrates can be structures of planar non-conductive material, such as fiberglass material used for PCBs, or may even be semiconductor dice. For the sake of clarity, the term “substrate”, as used hereinafter, will be defined to include planar non-conductive materials and semiconductor dice. The substrates are preferably stacked atop one another by electric connections which are ball or column-like structures. Alternately, solder bumps or balls may be formed on the substrate. The electric connections achieve electric communication between the stacked substrates. The electric connections can be formed from industry standard solder forming techniques or from other known materials and techniques such as conductive adhesives, Z-axis conductive material, flex-contacts, spring contacts, wire bonds, TAB tape, and the like. The electric connections must be of sufficient height to give clearance for the components mounted on the substrates and should be sufficiently strong enough to give support between the stacked substrates. 
     A preferred embodiment comprises a base substrate, having first and opposing surfaces, and means for electrical connection with external components or substrates, wherein the electrical connection means extends at least from the first surface of the base substrate. The base substrate opposing surface, the other side of the substrate, also includes a plurality of bond pads disposed thereon. Additionally, at least one semiconductor component may be attached to the opposing surface of the base substrate. The semiconductor components are preferably flip chips that are in electrical communication with electrical traces on or within the base substrate with any convenient known chip-on-board (COB) or direct-chip-attachment (DCA) technique (i.e., flip chip attachment, wirebonding, and TAB). Other techniques, such as the use of two-axis materials or conductive epoxies, can also be used for connections between either substrates or substrates and semiconductor chips. The electrical traces form a network of predetermined electrical connections between the base substrate electrical connection means, the base substrate bond pads, and/or the base substrate semiconductor components. 
     The preferred embodiment further comprises a stacked substrate. The stacked substrate has a first surface and an opposing surface. A plurality of bond pads may be disposed on the stacked substrate first surface and/or the stacked substrate opposing surface. At least one semiconductor component is attached to each of the stacked substrate first surface and the stacked substrate opposing surface. The semiconductor components are preferably flip chips which are in electrical communication with electrical traces on or within the first stacked substrate. The electrical traces form a network of predetermined electrical connections between the stacked substrate first surface bond pads, the stacked substrate opposing surface bond pads, and/or the stacked substrate semiconductor components. 
     The stacked substrate is attached to the base substrate through a plurality of electric connections. The electric connections can be column-like structures or spherical structures (balls) that support and form electrical communication between the base substrate bond pads and either the stacked substrate first surface bond pads or the stacked substrate opposing surface bond pads (depending upon which stacked substrate surface faces the base substrate first surface). The electric connections are preferably distributed evenly around a periphery of the base and stacked substrates. However, the electric connections may be of any distribution so long as adequate mechanical support exists between the base substrate and the stacked substrate. 
     In the manner discussed for the stacked substrate, additional stacked substrates may be attached to and stacked above the stacked substrate. Thus, with this technique, a multiple stacked substrate component may be formed. It is, of course, understood that the electrical connection means extending from the base substrate first surface for communication with an outside substrate may not be necessary if the multiple stacked substrate is in and of itself a complete component. 
     An alternative embodiment comprises substrates of varying size in a single assembly. The variable size substrate assembly is constructed in the manner discussed above. However, the variable size substrate assembly includes smaller sized substrates than the previously discussed base and stacked substrate. The smaller substrate is essentially identical to the previously discussed stacked substrate. The smaller substrate comprises a first surface and an opposing surface with a plurality of bond pads which may be disposed on the smaller substrate first surface and/or the smaller substrate opposing surface. At least one semiconductor component may be attached to the smaller substrate first surface and/or the smaller substrate opposing surface. The semiconductor components are in electrical communication with electrical traces on or within the first stacked substrate. The electrical traces form a network of predetermined electrical connections between the smaller substrate first surface bond pads, the smaller substrate opposing surface bond pads, and/or the smaller substrate semiconductor components. 
     The smaller substrate may be disposed between the base substrate and the stacked substrate. The smaller substrate is attached to either the base substrate or the stacked substrate through a plurality of electric connections. The electric connections form electrical communication between the base substrate bond pads and the smaller substrate bond pads or between the stacked substrate bond pads and the smaller substrate bond pads (depending upon whether the smaller substrate is attached to the base substrate or the stacked substrate). The smaller substrate may also be attached to the opposite surface of the stacked substrate and multiple smaller substrates may be attached in various positions on any substrate in the variable size substrate assembly. 
     Thus, the present invention offers the advantages of and achieves superior and improved electrical properties and speed of submodules and the entire module assembly, achieves higher density input/output configurations and locations (array), achieves higher density of devices or complexities of integrated circuits because of optimum input/output locations, results in improved thermal performance, allows easier repair and reusability, and allows easier modification of the package. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which: 
     FIG. 1 is a side cross-sectional view of a first stacked assembly of the present invention; 
     FIG. 2 is a perspective view of a substrate of the present invention which has uniform periphery bond pads; 
     FIG. 3 is a perspective view of a substrate of the present invention which has non-uniform bond pads; 
     FIG. 4 is a side cross-sectional view of a variable stack size assembly of the present invention; 
     FIG. 5 is a perspective view of a variable stack size assembly of the present invention; and 
     FIG. 6 is a cross-sectional view of a variable stack size assembly of the present invention using flip chip bonding techniques. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a first stacked assembly  100  of the present invention. The stacked assembly  100  comprises a base substrate  102  having a first surface  104  with a plurality of bond pads  106  disposed thereon and a second surface  108  with a plurality of bond pads  110  disposed thereon. Each of the base substrate first surface bond pads  106  is in electrical communication with its respective base substrate second surface bond pads  110  via a plurality of lead traces  112  extending through the base substrate  102 . A plurality of electric connections  114  extends from the base substrate first surface bond pads  106 . The base substrate electric connections  114  make contact with the other components or substrates. 
     The stacked assembly  100  further includes a first stacked substrate  116  having a first surface  118  with a plurality of bond pads  120  and a second surface  122  with a plurality of bond pads  124  disposed thereon. The first stacked substrate  116  is in electrical communication with the base substrate second surface  108  via a plurality of first electric connections  126 . The first electric connections  126  extend between each first stacked substrate first surface bond pad  120  and its respective base substrate second surface bond pad  110 . The bond pads of both the first stacked substrate  116  and base substrate  102  are preferably located such that each respective bond pad pair aligns perpendicularly. 
     A plurality of first semiconductor dice  128  each having a face side  130  and a back side  132  is attached to each of the first stacked substrate first surface  118  and the first stacked substrate second surface  122  with a first layer of adhesive  134  applied to the first semiconductor die back sides  132 . The first semiconductor dice  128  are in electrical contact with a plurality of first stacked substrate electrical traces  136  via TAB bonds  138 . The first stacked substrate electrical traces  136  extend in or on the first stacked substrate  116  and may contact the first stacked substrate first surface bond pad  120 , the first stacked substrate second surface bond pad  124 , and/or another first semiconductor die  128 . 
     The stacked assembly  100  still further includes a second stacked substrate  140  having a first surface  142  with a plurality of bond pads  144  thereon and a second surface  146 . The second stacked substrate  140  is in electrical communication with the first stacked substrate second surface  122  via a plurality of second electric connections  148 . The second electric connections  148  extend between each second stacked substrate first surface bond pad  144  and its respective first stacked substrate second surface bond pad  124 . The bond pads of both the second stacked substrate  140  and first stacked substrate  116  are preferably located such that each respective bond pad pair aligns perpendicularly. 
     A plurality of second semiconductor dice  150  each having a face side  152  and a back side  154  is attached to the second stacked substrate first surface  142  with a second layer of adhesive  156  applied to the second semiconductor die back sides  154 . The second semiconductor dice  150  are in electrical contact with a plurality of second stacked substrate electrical traces  158  via wirebonds  160 . A plurality of third semiconductor dice  162  each having a face side  164  is attached to the second stacked substrate second surface  146  with a plurality of flip chip contacts  166 , such as BGA, PGA or the like. The flip chip contacts  166  are in electrical contact with the second stacked substrate electrical traces  158 . The second stacked substrate electrical traces  158  extend in or on the second stacked substrate  140  and may contact the second stacked substrate first surface bond pads  144 , the second semiconductor dice  150  and/or another third semiconductor die  162 . 
     A flip chip dielectric material  168  may be disposed between the third semiconductor dice face side  164  and the second stacked substrate second surface  146 . Additionally, a dielectric material  170  may be disposed between the base substrate  102  and the first stacked substrate  116 , and/or the first stacked substrate  116  and the second stack substrate  140 . Furthermore, an encapsulation material  172  may cover the stack dice portion of the stacked assembly  100 . 
     It is, of course, understood that any available substrate surface, such as the base substrate second surface  108 , may have semiconductor dice attached thereto. 
     FIG. 2 illustrates a substrate assembly  200  having a uniform bond pad arrangement, such as shown as the first surface  142  of the second stacked substrate  140  in FIG.  1 . The substrate assembly  200  comprises a substrate  202  with a plurality of bond pads  204  distributed about a periphery  206  of a surface  208  of the substrate  202 . A plurality of semiconductor dice  210  is disposed on the substrate surface  208  within the bond pads  204 . The semiconductor dice  210  have a face side  212  and a back side  214 . The semiconductor dice  210  are attached by an adhesive layer  216  applied to the semiconductor dice back side  214  and make electrical contact with the substrate surface  208  by a plurality of bond wires  218 . Such an arrangement of bond pads  204  yields a strong, well-supported structure. 
     The distribution of the bond pads and the semiconductor dice need not be uniform, so long as the distribution allows adequate support between substrates. FIG. 3 illustrates a substrate assembly  300  having a non-uniform bond pad arrangement. The substrate assembly  300  comprises a substrate  302  with a plurality of bond pads  304  distributed in a non-uniform pattern across a surface  306  of the substrate  302 . A plurality of semiconductor dice  308  is disposed on the substrate surface  306 . The semiconductor dice  308  have a face side  310  and a back side  312 . The semiconductor dice  308  are attached by an adhesive layer  314  applied to the semiconductor dice back side  312  and make electrical contact with the substrate surface  306  by a plurality of bond wires  316 . 
     FIG. 4 illustrates a variable stack size assembly  400  of the present invention. The variable stack size assembly  400  comprises a first stacked substrate  402  having a surface  404  with a plurality of first bond pads  406  and second bond pads  408  disposed thereon. A plurality of first semiconductor dice  410  each having a face side  412  and a back side  414  is attached to the first stacked substrate surface  404  with a first layer of dielectric adhesive  416  applied to the first semiconductor die back sides  414 . The first semiconductor dice  410  are in electric communication with a plurality of first stacked substrate electrical traces (not shown) via wirebonds  418 . 
     The variable stack size assembly  400  further includes a first small stacked substrate  420  having a first surface  422  with a plurality of bond pads  424  disposed thereon and a second surface  426 . The first small stacked substrate  420  is in electrical communication with the first stacked substrate surface  404  via a plurality of first small stacked substrate electric connections  428 . The first small stacked substrate electric connections  428  extend between each first stacked substrate surface first bond pad  406  and its respective first small stacked substrate first surface bond pad  424 . The bond pads of both the first stacked substrate  402  and first small stacked substrate  420  are preferably located such that each respective bond pad pair aligns perpendicularly. At least one second semiconductor die  430  having a face side  434  and a back side  432  is attached to the first small stacked substrate second surface  426  with a second layer of dielectric adhesive  436 . The second semiconductor die  430  is in electric communication with a plurality of first small stacked substrate electrical traces (not shown) via wirebonds  438 . 
     The variable stack size assembly  400  still further includes a second stacked substrate  440  having a first surface  442  with a plurality of bond pads  444  thereon and a second surface  446  with a plurality of bond pads  448 . The second stacked substrate  440  is in electrical communication with the first stacked substrate surface  404  via a plurality of first electric connections  450 . The first electric connections  450  extend between each second stacked substrate first surface bond pad  444  and its respective first stacked substrate second surface bond pad  408 . The bond pads of both the second stacked substrate  440  and first stacked substrate  402  are preferably located such that each respective bond pad pair aligns perpendicularly. 
     A plurality of third semiconductor dice  452  each having a face side  454  and a back side  456  is attached to the second stacked substrate second surface  446  with a third layer of dielectric adhesive  458  applied to the third semiconductor die back sides  456 . The third semiconductor dice  452  are in electric communication with a plurality of second stacked substrate electrical traces (not shown) via wirebonds  460 . 
     The variable stack size assembly  400  still further includes a third stacked substrate  462  having a first surface  464  with a plurality of bond pads  466  thereon and a second surface  468  with a plurality of bond pads  470  thereon. The third stacked substrate  462  is in electrical communication with the second stacked substrate second surface  446  via a plurality of second electric connections  472 . The second electric connections  472  extend between each third stacked substrate first surface bond pad  466  and its respective second stacked substrate second surface bond pad  448 . The bond pads of both the third stacked substrate  462  and second stacked substrate  440  are preferably located such that each respective bond pad pair aligns perpendicularly. 
     A plurality of fourth semiconductor dice  474  each having a face side  476  and a back side  478  is attached to the third stacked substrate first surface  464  with a fourth layer of dielectric adhesive  480  applied to the fourth semiconductor die back sides  478 . The fourth semiconductor dice  474  are in electrical contact with a plurality of third stacked substrate electrical traces (not shown) via wirebonds  482 . A plurality of fifth semiconductor dice  484  each having a face side  486  and a back side  488  is attached to the third stacked substrate second surface  468  with a fifth layer of dielectric adhesive  490  applied to the fifth semiconductor die back sides  488 . The fifth semiconductor dice  484  are in electric communication with a plurality of third stacked substrate electrical traces (not shown) via wirebonds  492 . 
     The variable stack size assembly  400  further includes a second small stacked substrate  494  having a first surface  496  with a plurality of bond pads  498  disposed thereon and a second surface  500 . The second small stacked substrate  494  is in electrical communication with the third substrate second surface  468  via a plurality of second small substrate electric connections  502 . The second small substrate electric connections  502  extend between each second small stacked substrate first surface bond pad  498  and its respective third stacked substrate second surface bond pad  470 . The bond pads of both the second small stacked substrate  494  and third stacked substrate  462  are preferably located such that each respective bond pad pair aligns perpendicularly. At least one sixth semiconductor die  504  having a face side  506  and a back side  508  is attached to the second small stacked substrate first surface  496  with a sixth layer of dielectric adhesive  510 . The sixth semiconductor die  504  is in electric communication with a plurality of second small stacked substrate electrical traces (not shown) via wirebonds  512 . At least one seventh semiconductor die  514  having a face side  516  and a back side  518  is attached to the second small stacked substrate second surface  500  with a seventh layer of dielectric adhesive  520 . The seventh semiconductor die  514  is in electric communication with a plurality of second small stacked substrate electrical traces (not shown) via wirebonds  522 . Although the electrical traces of the substrates have not been illustrated, it is understood that electrical traces make electrical connections in the same manner as described for FIG.  1 . 
     FIG. 5 illustrates a substrate assembly  600  having a smaller substrate  602  on a larger substrate  604 , such as shown as third stacked substrate  462  and second small stacked substrate  494  in FIG.  4 . The substrate assembly  600  comprises the larger substrate  604  having a plurality of first semiconductor dice  606  and the smaller substrate  602  disposed on a surface  608  of the larger substrate  604 . The first semiconductor dice  606  have a face side  612  and a back side  614 . The first semiconductor dice  606  are attached by a first layer of adhesive  616  applied to the semiconductor dice back side  614  and make electrical contact with the substrate surface  608  by a plurality of first bond wires  618 . The smaller substrate  602  has a first surface  620  and a second surface  622 . The smaller substrate  602  has a plurality of electrical contacts  624  extending between a plurality of bond pads  626  on the smaller substrate first surface  620  and a plurality of bond pads  628  on the larger substrate surface  608 . A plurality of second semiconductor dice  630  (only one shown) is disposed on the smaller substrate second surface  622 . The second semiconductor dice  630  have a face side  634  and a back side  636 . The second semiconductor dice  630  are attached by a second layer of adhesive  638  applied to the second semiconductor dice back side  636  and make electrical contact with the smaller substrate second surface  622  by a plurality of bond wires  640 . Although the electrical traces of the smaller substrate have not been illustrated, it is understood that electrical traces make electrical connections in the same manner as described for FIG.  1 . 
     FIG. 6 illustrates a substrate assembly  700  having a plurality of semiconductor devices mounted on substrates using known flip chip attachment techniques. The substrate assembly  700  comprises a first substrate  704  having a plurality of first semiconductor dice  702  disposed thereon and a second substrate  708  having a plurality of second semiconductor dice  706  disposed thereon. The first semiconductor dice  702  each have a surface or face side  710  having a plurality of bond pads (not shown) thereon and a back side  712 . The first semiconductor dice  702  make electrical contact with the traces (not shown) on the first substrate surface  714  by a plurality of first conductive material balls  716  extending between the bond pads (not shown) on the face surface  710  of the dice  702  and the traces (not shown) on the first substrate surface  714 . The balls  716  may be made of any suitable conductive material to connect the semiconductor dice  702  to the conductive traces on first substrate  704 , such as solder, conductive epoxy, etc. The balls  716  are shown as generally spherical in shape, although they may be any suitable geometric shape and size for bonding purposes. Further, z-axis connectors may be substituted for the balls  716  if so desired. The second substrate  708  has a surface  718  having a plurality of conductive traces (not shown) thereon. The second plurality of semiconductor dice  706  each have a face side  720  having a plurality of bond pads (not shown) thereon and a back side  722 . The second plurality of semiconductor dice  706  make electrical contact with the second substrate surface  718  by a plurality of second conductive material balls  724  extending between the bond pads of the dice  706  and the conductive traces on the second substrate surface  718 . The balls  724  may be made of any suitable conductive material to connect the semiconductor dice  706  to the conductive traces on second substrate  708 , such as solder, conductive epoxy, etc. The balls  724  are shown as generally spherical in shape, although they may be any suitable geometric shape and size for bonding purposes. Further, z-axis connectors may be substituted for balls  724  if so desired. The desired conductive traces on the surface  714  of the first substrate  704  are connected to the desired conductive traces on the surface  718  of the second substrate  708  by larger conductive balls  726 . The larger conductive balls  726  may be of any suitable conductive material, such as solder, conductive epoxy, etc. The larger conductive balls are also used for connecting the surface  728  of the first substrate  704  to any other desired substrate. Further, z-axis connectors may be substituted for balls  726  if so desired. It should be understood that the conductive traces which have only been referred to on the surfaces  714  and  718  of the substrates may be formed on either side of the first substrate  704  or the second substrate  708  and, as such, have not been illustrated. Also, any connectors extending through the first substrate  704  and second substrate  708  for connection purposes have not been shown. Similarly, the bond pads on the first semiconductor dice  702  and second semiconductor dice  706  have not been illustrated. The first semiconductor dice  702  are attached to the first substrate  704  and the second semiconductor dice  706  are attached to the second substrate  708  by well known flip-chip bonding techniques, depending upon the type of conductive balls  716  and  724  used for connection purposes. 
     FIGS. 4,  5  and  6 , as shown, illustrate complete electrical components. As an example, the smaller stacked substrates (i.e., first small stacked substrate  420  and second small stacked substrate  494  of FIG. 4, and smaller substrate  602  of FIG. 5) could be memory modules containing a plurality of memory chips. These smaller stacked substrates or semiconductor devices are connected to the larger substrates (i.e., first stacked substrate  402  and third stacked substrate  462  of FIG. 4, larger substrate  604  of FIG. 5 or first semiconductor dice  702  stacked on first substrate  704  and second semiconductor devices  706  stacked on second substrate  708  of FIG.  6 ), which could be the motherboard portions with control logic circuits and a central processing unit(s). Thus, the combination of these example components could constitute a complete component. However, it is, of course, understood that the embodiments shown in FIGS. 4,  5  and  6  could include electric connections (such as electric connections  114  of FIG. 1) to connect to other components or other substrates. 
     Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.