Abstract:
An apparatus comprising an amplifier and a coupling circuit. The amplifier may be configured to generate an amplified output signal in response to a first input signal and a second input signal. The coupling circuit may be configured to generate the second input signal in response to the first input signal. The coupling circuit may be configured to increase a speed of propagation of the first input signal.

Description:
This is a continuation of U.S. Ser. No. 09/723,298, filed Nov. 27, 2000 now U.S. Pat. No. 6,480,067. 
     CROSS-REFERENCE TO RELATED APPLICATION(S) 
     The present invention may relate to application Ser. No. 09/723,037, filed Nov. 27, 2000, now U.S. Pat. No. 6,373,346, which is hereby incorporated by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a method and/or architecture for wide band amplifiers generally and, more particularly, to a method and/or architecture for laser driver amplifiers that employ a method of shaping or equalizing a high data rate output signal waveform that may be used in fiber optic transmitter applications. 
     BACKGROUND OF THE INVENTION 
     The need for broadband integrated circuits (ICs) that incorporate peaking control is becoming a necessity rather than a luxury as the data rates and traffic of fiber optic systems increase. Peaking control in wideband integrated circuits is useful for adjusting gain and amplitude peaking in the frequency domain. Fiber optic data links require adjusting signal overshoot in the time domain for shaping the waveform of transmit and receive signals to achieve lower bit error rates. The need for adjustment of signal overshoot becomes more imperative for 10 gigabit per second fiber optic applications that require high volume-high IC yield with low tolerance to semiconductor process variations. Such applications include the emerging 10 gigabit Ethernet datacom systems. 
     A broadband IC which can modulate lasers or vertical cavity surface emitting lasers (VCSELs) at data rates up to 10 Gb/s and maintain low bit error rates is coveted by engineers building high speed Ethernet systems. In practice, laser driver ICs require pre-emphasis circuits or some type of control circuit which can compensate for the distortion introduced by the nonlinear laser or VCSEL. The signal passing through a linear laser driver modulator operating at 10 Gb/s can become distorted in the process of converting from electrical to optical energy as the laser diode or VCSEL is modulated by the linear electrical driver circuit. When conversion distortion occurs, it is desirable to drive the laser or VCSEL with a pre-distorted signal which compensates for the distortion produced by the nonlinear behavior of the VCSEL or laser. The pre-distortion may be implemented by a pre-emphasis or peaking function which superimposes a weighted peaking signal on the original signal to speed up the rise and falling edges of the original data waveform. The superimposed peaking signal enhances the data transition rise and fall times as well as reshapes the signal for low bit error rates (BER), inter-symbol interference (ISI), and maximum eye pattern opening. 
     Several conventional approaches for employing such pre-distortion comprise [1] dynamic current source switching (e.g., Rainer H. Derksen, Novel Switched Current Source for Increasing Output Signal Edge Steepness of Current Switches Without Generating Large Overshoot, IEEE JSSC, vol. 30, no. 5, May 1995) and [2] pre-emphasis (digital peaking) (e.g., Ramin Farjad-Rad, et. al., A 0.4-um CMOS 10-Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter, IEEE JSSC, vol. 34, no. 5, May 1999), each of which is incorporated by reference in its entirety. Additionally, analog peaking techniques may be employed. The first two techniques are common-types of approaches which have had practical implementations at low data rates (i.e., 2.5 Gb/s and below). However, the implementations of these techniques at higher data rates is challenging. The effectiveness of these techniques can be marginal at 10 Gb/s and higher due to the quality of the raw data signal which provides a clock or trigger for the technique. 
     The analog peaking technique approach does not rely on using the raw data waveform as a clock or synchronizing signal for the technique to be effective and is therefore more suitable for higher data rate applications. Due to the recent availability of long and short wave VCSEL technology for 10 Gb/s, an effective device for employing pre-emphasis or peaking control is desired. 
     Additionally, a device which is amenable to high volume-high yield manufacturing for 10 Gb/s VCSEL driver applications is needed. 
     SUMMARY OF THE INVENTION 
     The present invention concerns an apparatus comprising an amplifier and a coupling circuit. The amplifier may be configured to generate an amplified output signal in response to a first input signal and a second input signal. The coupling circuit may be configured to generate the second input signal in response to the first input signal. The coupling circuit may be configured to increase a speed of propagation of the first input signal. 
     The objects, features and advantages of the present invention include providing a method and/or architecture for implementing laser driver amplifiers that may (i) provide shaping or equalizing of a high data rate output signal waveform; (ii) be used in fiber optic transmitter applications; (iii) employ a switched architecture for switching between a regenerative peaking amplifier and a conventional amplifier; (iv) implement a switching circuit that may allow variable weighted employment of the peaking amplifier; (v) provide AC coupling of the peaking amplifier with a speedup capacitor and resistor which may allow a degree of freedom to set up a decay time constant; (vi) implement variability in AC coupling, and/or (vii) implement a tap point that may optimize the time superposition of the peak and unpeaked signals at the output. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 2 is a detailed block diagram of a preferred embodiment of the present invention; 
     FIG. 3 is a detailed block diagram of a preferred embodiment of the present invention which incorporates a delay function; 
     FIG. 4 is a plot illustrating the gain peaking operation of the present invention; 
     FIG. 5 is a schematic of a preferred embodiment of the present invention; 
     FIG. 6 is a plot illustrating the unpeaking gain-frequency operation of the present invention; 
     FIG. 7 is a plot illustrating 20% gain peaking operation of the present invention; 
     FIG. 8 is a plot illustrating 50% gain peaking operation of the present invention; 
     FIG. 9 is a plot illustrating 100% gain peaking operation of the present invention; 
     FIG. 10 is a plot illustrating unpeaked time domain operation of the present invention; 
     FIG. 11 is a plot illustrating 20% peaking time domain operation of the present invention; 
     FIG. 12 is a plot illustrating 50% peaking time domain operation of the present invention; 
     FIG. 13 is a plot illustrating 100% peaking time domain operation of the present invention; and 
     FIG. 14 is a plot illustrating the unpeaking differential output voltage performance in response to a data stream operation of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention describes an analog peaking control circuit which can provide significant performance benefits for data rates in excess of 10 Gb/s. The present invention may provide enough tuning latitude to compensate for process manufacturing variations. 
     Referring to FIG. 1, a block diagram of a system (or circuit)  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  may be implemented, in one example, as a monolithic integrated circuit. The circuit  100  may have an input  102   a  that generally receives an input signal (e.g., IN 0 ). and an input  102   b  that generally receives the input signal (e.g., IN 1 ). The circuit  100  may have an output  104   a  that presents an output signal (e.g., OUT 0 ) and an output  104   b  that presents an output signal (e.g., OUT 1 ). The circuit  100  may also have an input  106  that receives a voltage reference signal (e.g., VREF) and an input  108  that generally receives a control signal (e.g., VCONTROL). The input signals IN 0  and IN 1  are generally differential input signals. The output signals OUT 0  and OUT 1  are generally differential output signals. 
     The circuit  100  may be particularly suitable for implementing peaking control for wideband laser driver applications. The peaking control technique of the circuit  100  may be implemented, for example, in a 10 Gb/s laser driver IC for datacom and telecom applications or 10 Gb/s limiter amplifier applications. 
     Referring to FIG. 2, a more detailed diagram of the circuit  100  is shown. The circuit  100  generally comprises a circuit  110 , a circuit  112 , a circuit  114 , and a circuit  115 . The circuit  110 , the circuit  112  and the circuit  114  make up an amplifier circuit  117 . The circuit  115  may be implemented as an AC coupling speed-up circuit. The circuit  115  generally comprises a capacitor (e.g., CSPEEDUP 1 ), a capacitor (e.g., CSPEEDUP 2 ), a resistor (e.g., RSPEEDUP 1 ), a resistor (e.g., RSPEEDUP 2 ) and a bias signal (e.g., VBIAS). The circuit  110  may be implemented, in one example, as a laser modulator circuit. The circuit  112  may be implemented, in one example, as a peaking (or regenerative) amplifier circuit. The circuit  114  may be implemented as a control circuit. In one example, the circuit  114  may be implemented as a current source switch. 
     The laser modulator  110  may have a first input that may receive the input signal IN 0  and a second input that may receive the signal IN 1 . The peaking amplifier circuit  112  may have a first input that may receive the signal IN 0  through the capacitor CSPEEDUP 1 . The first input of the peaking amplifier  112  may also be connected to the bias signal VBIAS through the resistor RSPEEDUP 1 . The laser modulator circuit  110  may also receive a control signal (e.g, CTR 1 ) from the circuit  114 . 
     The peaking amplifier  112  may have a second input that may receive the signal IN 1  through the capacitor CSPEEDUP 2  and the signal VBIAS through the resistor RSPEEDUP 2 . The peaking amplifier  112  may also receive a control signal (e.g., CTR 2 ) from the circuit  114 . A first output of the laser modulator  110  and a first output of the peaking amplifier  112  are combined to present the signal OUT 0 . Similarly, a second output of the laser modulator  110  and a second output of the peaking amplifier  112  are combined to present the signal OUT 1 . The first and second output signals OUT 1  and OUT 2  may be derived (i) completely from the laser modulator  110 , (ii) completely from the peaking amplifier  112 , or (iii) as a combination of the laser modulator  110  and the peaking amplifier  112 . 
     The circuit  114  generally comprises a transistor (e.g., QS 1 ), a transistor (e.g., QS 2 ), a resistor (e.g., Rlee 1 ), a resistor (e.g., Rlee 2 ) and a current source (e.g., ICS 1 ). The circuit  114  generates the signals CTR 1  and CTR 2  via the transistors QS 1  and QS 2 . The circuit  114  may allow the circuit  100  to provide peaking control of the signals OUT 0  and OUT 1  by setting the ratio of signals presented from the laser modulator  110  and the peaking amplifier  112 . 
     The amplifier  110  and the amplifier  112  may be implemented as differential topologies. For example, the circuit  114  may be employed for switching the bias tail currents such that a weighted ratio between amplified modulator  110  and peaking amplifier  112  may be set to obtain varying degrees of peaking response. In one example, the circuit  114  may be configured as an emitter degenerated differential amplifier. However, the circuit  114  may be implemented as other appropriate type devices in order to meet the criteria of a particular implementation. The resistors Rlee 1  and Rlee 2  may be implemented as emitter degeneration resistors. The current source ICS 1  may effectively become the peak modulation current that drives a laser from the outputs OUT 0  and OUT 1 . 
     By varying the signal VCONTROL, various degrees of peaking may be superimposed on the modulating signal (e.g., OUT 0  and OUT 1 ). The degeneration resistors Rlee 1  and Rlee 2  may be implemented to control the sensitivity of the amount of current switched in response to an adjustment of the signal VCONTROL. The sensitivity control can be useful in closed loop applications where the output detected signal is used as a feedback to the voltage control adjustment VCONTROL. In one example, the control circuit  114  may be replaced by two independent fixed current sources which could be set once without any current switch (steering) capabilities. In such an example, the independent current sources could be programmed by a digital to analog converter (DAC) controlled by a microprocessor. 
     The inputs of the peaking amplifier  112  are generally AC coupled with the capacitors CSPEEDUP 1  and CSPEEDUP 2  which form a high pass filter response with the resistors RSPEEDUP 1  and RSPEEDUP 2 . The capacitance values of the capacitors CSPEEDUP 1  and CSPEEDUP 2  and the resistors RSPEEDUP 1  and RSPEEDUP 2  generally set a high pass pole which determines the peaking response of the circuit  100 . 
     Referring to FIG. 3, an alternate embodiment of the circuit  100 ′ is shown. The circuit  100 ′ may be similar to the circuit  100 . The circuit  100 ′ further comprises a delay element  120  that may be inserted just before the laser modulator output stage  110 ′. The delay element  120  may superimpose the peaking signal earlier with respect to the unpeaked signal waveform. The delay element  120  may be implemented as a simple emitter follower, a transmission line, a lumped inductor/resistor/capacitor (LRC) network or other appropriate delay to meet the design criteria of a particular implementation. 
     FIG. 4 illustrates the gain-frequency peaking response of the complete modulator driver circuit  100  for various values of the capacitors CSPEEDUP 1  and CSPEEDUP 2  ranging from 0 to 2.5 pF. The control circuit  114  may be set for balanced operation or the peaking circuit  112  is sourcing 50% of the current ICS 1  and the other 50% of the current is biasing the main modulator driver amplifier  110 . The AC coupling can be tapped at various stages preceding the output modulator stage  110 . The peak amplified waveform can be skewed in time with respect to the original unpeaked signal in order to optimize the predistortion waveform. For example, the peak amplifier stage  112  may be coupled at the input of the laser modulator stage  110  in order to superimpose the peak-amplified signal earlier (in time) with respect to unpeaked modulator output waveform. The circuit  100  may speed up the rise and fall edges of the signals OUT 1  and OUT 2 . The circuit  100  may provide an optimum delay that may improve overall performance of the circuit  100 . 
     Referring to FIG. 5, a detailed diagram of the circuit  100  is shown. The current switch  114  and the AC coupling speed up circuit  115  may be identical in function and component to that shown in the general conceptual diagram of FIG.  2 . The implementation of the main laser modulator amplifier  110  and the peaking amplifier  112  is shown in more detail. The laser modulator circuit  110  generally comprises a differential amplifier formed by a transistor (e.g., Q 3 ) and a transistor (e.g., Q 4 ) and a load formed by a resistor (e.g., RL 1 ) and a resistor (e.g., RL 2 ). The peaking amplifier  112  is topologically connected in parallel with the laser modulator amplifier  110 . The amplifier  112  generally comprises a differential amplifier with a transistor (e.g., Q 1 ) and a transistor (e.g., Q 2 ) that may have bases that are AC coupled to the inputs of the driver circuit IN 0  and IN 1 . The amplifier  112  also comprises a transistor (e.g., Qc 1 ) and a transistor (e.g., Qc 2 ) that may be cross coupled. The transistors Qc 1  and Qc 2  may provide regenerative capacitive feedback through respective collector-base capacitances. 
     The size (e.g., emitter area) of the transistors Qc 1  and Qc 2  may set the amount of regenerative feedback (e.g., peaking response). In general, the transistors Qc 1  and Qc 2  are substantially identical in area in order to obtain a symmetrically enhanced signal. However, the circuit  100  may be implemented where the transistors Qc 1  and Qc 2  are not symmetrical in area, such as in an active balun application. The collectors of the current source switch  114  are connected to the common-emitters of the transistors Q 1  and Q 2  and the transistors Q 3  and Q 4  and may change the amount of effective peaking provided by the peaking amplifier  112 . In the frequency domain, the peaking circuit  112  may aid in broadening the gain bandwidth of the amplifier, peaking the gain response at the upper band edge. 
     FIGS. 6-9 illustrate the peaking control response as the amount of peak amplifier source (bias) current is increased (measured in % of Ics 1 , e.g., 20% UI indicates 20% of the current is steered through the peak amplifier  112  while 80% of the current is steered through the laser modulator amplifier  110 ) for the capacitors CSPEEDUP 1  and CSPEEDUP 2  and the resistors RSPEEDUP 1  and RSPEEDUP 2  of 0.3 pF and 100 ohms, respectively. In one example, the circuit  100  may be implemented in a commercially available HBT process with a typical cut-off frequency of 35 GHz. However, other processes technologies (e.g., SiGe, GaAs, etc.) may be used to meet the design criteria of a particular implementation. 
     FIG. 6 illustrates the gain response with no peaking employed (0% Ics 1  current is sourced through the peak amplifier  112  and all the current Ics 1  is sourced through the laser modulator amplifier  110 ). FIG. 6 illustrates a flat gain and butterworth low pass roll off response. The gain is 15 dB and the 3-dB bandwidth is 7 GHz. 
     FIG. 7 illustrates the gain response case where the peak amplifier  112  is biased with 20% of Ics 1  (80% of Ics 1  is sourced through the laser modulator amplifier  110 ). The gain is 15.3 dB and the 3-dB bandwidth increased to 9 GHz. 
     FIG. 8 illustrates the case for 50% Ics 1  peak amplifier bias. The gain is 13 dB and the bandwidth has increased even further to 10 GHz. 
     FIG. 9 illustrates the case where 100% of Ics 1  is biasing the peak amplifier  112 . This response demonstrates that excessive amount of peaking can be achieved. The resulting tuning latitude can more than accommodate or equalize the gain bandwidth variations due to process manufacture variations. 
     The adjustable peak control has a corresponding effect on the time domain output current waveform as illustrated in FIGS. 10-12. FIG. 10 shows a 10 Gb/s output modulation current data stream in response to the input data stream pattern “01010101110110” after it has been amplified by the laser driver with no peaking employed. This illustrates the NO PEAKING case where there is no bias current running through the regenerative peaking amplifier and where all the current Ics 1  is running through the main laser modulator amplifier  110 . This figure reflects the minimal peaking or overshoot response case of the output current waveform. 
     FIG. 11 illustrates the case where the current source switch  114  is adjusted for 20% peaking (20% of Ics 1  is steered through the peak amplifier  112  with the remainder being sourced from the laser modulator amplifier  110 ). In this case there is a slight peaking response that is evident on the rising edge of the  111  and  11  patterns. This additional peaking, which has been superimposed on the amplified data signal, can be adjusted to just cancel the nonlinear RC slewing characteristic imposed by the nonlinear laser or VCSEL diode in order to improve the overall BER and intersymbol interference. From a qualitative standpoint, an improvement in the rise-fall time and eye opening of the eye diagram may result. 
     FIG. 12 illustrates the case where the current source switch  114  is adjusted for 50% peaking (current) and illustrates an even more pronounced overshoot response which could compensate yet a poorer VCSEL distortion characteristic. 
     FIG. 13 illustrates the case where the current switch  114  is adjusted for 100% Ics 1  current sourced through the peak amplifier  112  and represents the maximum overshoot (peaking) attainable for this given example. For implementation reasons, the case of 100% peaking may not be practical. However, the degree of tuning may more than compensate for manufacture process variations. 
     FIG. 14 illustrates the complementary output response to the same input bit stream used in the above example and illustrates symmetrical and unambiguous complementary output data waveforms. FIG. 14 exhibits that the peaking response is effective on both rising and falling signal edges and may have a symmetrical impact on the peaked output data stream. 
     The circuit  100  may provide a unique peaking control which may improve the bandwidth of amplifiers used in wideband applications. Specifically, the circuit  100  may be implemented in fiber optic transmit and receive applications where operation is extended to 10 Gb/s and beyond. The peaking device may apply to transimpedance amplifiers, limiter amplifiers, and laser driver amplifiers, and more specifically bipolar amplifier implementations using heterojunction bipolar transistor technology. It should be understood that this invention is not limited to the exact construction illustrated and described above, but that various changes may be made without departing from the spirit and scope of the invention. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.