Abstract:
A control method controlling a display panel comprising a pixel unit. The pixel unit is coupled to a data line and comprises a capacitor, a transistor, and a luminiferous device. The capacitor comprises a first terminal coupled to the data line and a second terminal coupled to the transistor. The voltage of the first terminal is increased and the voltage of the second terminal is reduced during a first period. The voltage of the first and the second terminals are controlled during a second period subsequent to the first period. The luminiferous device is lit according to the voltage of the capacitor during a third period subsequent to the second period. The voltage of the data line is maintained during the third period.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a control method, and more particularly to a control method for controlling a display panel. 
         [0003]    2. Description of the Related Art 
         [0004]    Because cathode ray tubes (CRTs) are inexpensive and provide high definition, they are utilized extensively in televisions and computers. With technological development, new flat-panel displays are continually being developed. When a larger display panel is required, the weight of the flat-panel display does not substantially change when compared to CRT displays. Generally, flat-panel displays comprises liquid crystal displays (LCD), plasma display panels (PDP), field emission displays (FED), and electroluminescent (EL) displays. 
         [0005]    Electroluminescence (EL) display devices include organic light emitting diode (OLED) displays and polymeric light emitting diode (PLED) displays. In accordance with associated driving methods, an OLED can be an active matrix type or a positive matrix type. An active matrix OLED (AM-OLED) display typically is thin and exhibits lightweight characteristics, spontaneous luminescence with high luminance efficiency and low driving voltage. Additionally, an AM-OLED display provides the perceived advantages of increased viewing angle, high contrast, high-response speed, full color and flexibility. 
         [0006]    An AM-OLED display is driven by electric current. Specifically, each of the pixel units of an AM-OLED display includes a driving transistor and an OLED. The driving transistor provides a driving current such that the OLED is lit. The brightness of the OLED is determined by the driving current. Due to manufacturing procedures, different driving transistors comprise different threshold voltages. Thus, conventional OLEDs generate abnormal brightness. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    A control method and display panels are provided. The control method controls a display panel comprising a pixel unit. The pixel unit is coupled to a data line and comprises a capacitor, a transistor, and a luminiferous device. The capacitor comprises a first terminal coupled to the data line and a second terminal coupled to the transistor. An exemplary embodiment of a control method is described in the following. The voltage of the first terminal is increased and the voltage of the second terminal is reduced during a first period. The voltage of the first and the second terminals are controlled during a second period subsequent to the first period. The luminiferous device is lit according to the voltage of the capacitor during a third period subsequent to the second period. The voltage of the data line is maintained during the third period. 
         [0008]    An exemplary embodiment of a display panel comprises a pixel unit and a cathode switch. The pixel unit comprises a capacitor, a first transistor, and a luminiferous device. The capacitor comprises a first terminal coupled to a data line and a second terminal. The voltage of the first terminal is increased and the voltage of the second terminal is reduced during a first period. The voltage of the first and the second terminals are controlled during a second period subsequent to the first period. The first transistor is coupled to the second terminal. The luminiferous device is lit according to the voltage of the capacitor during a third period subsequent to the second period. The voltage of the data line is maintained during the third period. The cathode switch is coupled to the luminiferous device. 
         [0009]    Electronic systems are also provided. An exemplary embodiment of an electronic system comprises a display panel and a power converter. The power converter provides a power signal to the display panel. The display panel comprises a pixel unit and a cathode switch. The pixel unit comprises a capacitor, a first transistor, and a luminiferous device. The capacitor comprises a first terminal coupled to a data line and a second terminal. The voltage of the first terminal is increased and the voltage of the second terminal is reduced during a first period. The voltage of the first and the second terminals are controlled during a second period subsequent to the first period. The first transistor is coupled to the second terminal. The luminiferous device is lit according to the voltage of the capacitor during a third period subsequent to the second period. The voltage of the data line is maintained during the third period. The cathode switch is coupled to the luminiferous device. 
         [0010]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein: 
           [0012]      FIG. 1  is a schematic diagram of an exemplary embodiment of an electronic system; 
           [0013]      FIG. 2  is a schematic diagram of an exemplary embodiment of a display panel; 
           [0014]      FIG. 3  is a schematic diagram of an exemplary embodiment of a pixel unit; 
           [0015]      FIG. 4  is a timing chart of an exemplary embodiment of a control method; and 
           [0016]      FIG. 5  is a timing chart of another exemplary embodiment of a control method. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0017]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0018]      FIG. 1  is a schematic diagram of an exemplary embodiment of an electronic system. The electronic system  100  is a personal digital assistant (PDA), a cellular phone, a notebook or a personal computer (PC). The electronic system  100  comprises a power converter  110  and a display panel  120 . The power converter  110  provides a power signal SPW to the display panel  120  such that the display panel  120  displays an image. In one embodiment, the power converter  110  transforms an alternating current (AC) signal into a direct current (DC) signal to serve as the power signal S pw . In another embodiment, the power converter  110  transforms the level of a DC signal for generating the power signal S pw . 
         [0019]      FIG. 2  is a schematic diagram of an exemplary embodiment of a display panel. The display panel  120  comprises a gate driver  122 , a source driver  124 , a cathode switch  126 , a controller  128 , and pixel units P 11 ˜P mn . The gate driver  122  provides scan signals to the pixel units P 11 ˜P mn  via scan lines S 1 ˜S n . The source driver  124  provides data signals to the pixel units P 11 ˜P mn  via data lines D 1 ˜D m . The cathode switch  126  is coupled to luminiferous devices of the pixel units P 11 ˜P mn . 
         [0020]    In this embodiment, the cathode switch  126  comprises transistors Q 1 ˜Q 3  connected in parallel. Each of transistors Q 1 ˜Q 3  comprises a gate receiving a luminiferous signal S EMIT . The transistor number of the cathode switch  126  is not limited. In some embodiments, the cathode switch  126  comprises one transistor. The controller  128  provides control signals or voltage to the pixel units P 11 ˜P mn . In this embodiment, the controller  128  provides one or more control signals according to the structures of the pixel units P 11 ˜P mn . In some embodiments, the controller  128  is integrated into the gate driver  122  or the source driver  124 . 
         [0021]      FIG. 3  is a schematic diagram of an exemplary embodiment of a pixel unit. Since the structures of the pixel units P 11 ˜P mn  are the same, the pixel units P 11  and P 12  are given as an example. The pixel unit P 11  comprises a capacitor  312 , transistors  314 ,  318 , and a luminiferous device  316 . The gate of the transistor  318  is coupled to the scan line S 1 . In some embodiments, the transistor  318  is an N-type transistor. The pixel unit P 12  comprises a capacitor  322 , transistors  324 ,  328 , and a luminiferous device  326 . The gate of the transistor  328  is coupled to the scan line S 2 . 
         [0022]    A charge switch  330  is a P-type transistor. The P-type transistor comprises a source receiving a voltage signal PVDD, a drain coupled to the capacitors  312 ,  322  and the data line D 1 , and a gate receiving a charge signal S Pre . A power switch  340  is a P-type transistor. The P-type transistor comprises a source receiving the voltage signal PVDD, a drain coupled to the transistors  314  and  324 , a gate receiving a driving signal S EL     —     pw . In this embodiment, the charge switch  330  and the power switch  340  are disposed in the display panel. The controller  128  shown in  FIG. 2  provides control signals, such as the voltage signal PVDD, the charge signal S Pre , or the driving signal S EL     —     pw , to the charge switch  330  and the power switch  340 . In some embodiment, the power switch  340  can be omitted or be replaced by an N-type transistor. When the power switch  340  is omitted , the sources of the transistors  314  and  324  receive the voltage signal PVDD. 
         [0023]    Additionally, the cathode switch  126  is coupled to the luminiferous devices  316  and  326 . Each of the luminiferous devices  316  and  326  is an Organic Light-Emitting Diode (OLED). The OLED comprises a cathode coupled to the drains of the transistors Q 1 ˜Q 3 . The sources of the transistors Q 1 ˜Q 3  receive a voltage signal PVEE and the gates of the transistors Q 1 ˜Q 3  receives the luminiferous signal S EMIT . In this embodiment, the controller  128  shown in  FIG. 2  provides the luminiferous signal S EMIT  and the voltage signal PVEE is less than the voltage signal PVDD. 
         [0024]      FIG. 4  is a timing chart of an exemplary embodiment of a control method. The control method can be applied in the pixel units shown in  FIG. 3  or applied in other pixel structures. Referring to  FIGS. 2 and 3 , an exemplary embodiment of the control method is described in the following. Assuming the display panel requires 16.6 ms to display a frame. Thus, the cycle of a start signal STV is 16.63 ms. 
         [0025]    During a period T 41 , the driving signal S EL     —     PW  is in a high level. Thus, the power switch  340  is turned off. Since the scan signal S SCAN1  of the scan line S 1  is in a low level and the luminiferous signal S EMIT  is in the high level, transistors  318  and Q 1 ˜Q 3  are turned on. Thus, the voltage of a node B is reduced. Since the charge signal S pre  is in the low level, the voltage of a node A is increased. 
         [0026]    During a period T 42 , the scan sing S SCAN1  is in the high level such that the transistor  318  is turned off. Thus, the voltage of the node B is maintained at a fixed value. At this time, the driving signal S EL     —     PW  is in the low level such that the power switch  340  is turned on. Thus, the transistor  314  is turned on. Since the source driver  124  provides the data signal S DATA  via the data line D 1 , the voltage of the node A is reduced. At this time, the voltage of the node A relates to the data signal S DATA . 
         [0027]    During a period T 43 , the luminiferous signal S EMIT  is in the low level. Thus, the transistors Q 1 ˜Q 3  are turned off. The charge signal S Pre  is in the high level such that the charge switch  330  is turned off. Since the source driver  124  does not provide the data signal S DATA , the voltage of the node A is maintained. The scan signal S SCAN1  and the driving signal S EL     —     PW  are in the low level such that the transistor  318  and the power switch  340  are turned on. Thus, the voltage of the node B is increased. At this time, the voltage of the node B not only relates to the threshold voltage of the transistor  314 , but also relates to the voltage signal PVDD. 
         [0028]    In this embodiment, the transistor  314  is a driving transistor. The driving transistor generates a driving current according to the voltage of the capacitor  312 . The luminiferous device  316  is lit according to the driving current. The driving transistors in different pixel units comprise different threshold voltages due to manufacturing procedures. Thus, when the voltage of the node B relates to the threshold voltage of the corresponding driving transistor during the period T 43 , the different threshold voltage problem can be compensated. Additionally, since the voltage of the node B relates to the voltage signal PVDD, when the pixel units receive the different voltage signals, the luminiferous devices still displays at normal brightness. 
         [0029]    During a period T 44 , a scan signal S SCAN2  is in the high level such that the transistor  328  is turned off. Thus, the voltage of the node D is maintained. Since the driving signal S EL     —     PW  is in the low level, the power switch  340  and the transistor  324  are turned on. At this time, because the source driver  124  provides the data signal S DATA  via the data line D 1 , the voltage of a node C is increased or reduced according to the data signal S DATA . Thus, the voltage of the node C relates to the data signal S DATA . 
         [0030]    During a period T 45 , the luminiferous signal S EMIT  is in the low level. Thus, the transistors Q 1 ˜Q 3  are turned off. The charge signal S Pre  is in the high level such that the charge switch  330  is turned off. Since the data lines D 1  does not provide the data signal S DATA , the voltage of the node C is maintained at a fixed value. 
         [0031]    Since the scan signal S SCAN2  and the driving signal S EL     —     PW  are in the low level, the transistor  328  and the power switch  340  are turned on. Thus, the voltage of a node D is increased. At this time, the voltage of the node D not only relates to the threshold voltage of the transistor  324 , but also relates the voltage signal PVDD. 
         [0032]    During a period T 46 , the charge signal S Pre , the scan signals S SCAN1  and S SCAN2  are in the high level such that the charge switch  330 , the transistors  318  and  328  are turned off. Since the luminiferous signal S EMIT  is in the high level and the driving signal S EL     —     PW  is in the low level, the transistors  314  and  324  are operated in a saturation region. The transistor  314  generates a driving current according to the voltage of the capacitor  312 . The luminiferous device  316  is lit according to the driving current generated by the transistor  314 . The transistor  324  generates a driving current according to the voltage of the capacitor  322 . The luminiferous device  326  is lit according to the driving current generated by the transistor  324 . When the driving current is higher, the brightness of the luminiferous device is higher. Additionally, the data signal S DATA  is maintained during the period T 46 . In one embodiment, the data signal S DATA  can be maintained in grounding. 
         [0033]      FIG. 5  is a timing chart of another exemplary embodiment of a control method. Referring to  FIGS. 2 and 3 , the control method is described in the following. Assuming the power switch  340  is omitted and the source of the transistor  314  receives the voltage signal PVDD. Since the source of the transistor  314  receives the voltage signal PVDD, the transistor  314  is turned on. In this embodiment, if the display panel requires 16.6 ms to display a frame, the cycle of the start signal STV is 16.63 ms. 
         [0034]    During a period T 51 , the charge signal S Pre  and the scan signal S SCAN1  are in the low level and the luminiferous signal S EMIT  is in the high level such that the charge switch  330 , the transistors  318  and Q 1 ˜Q 3  are turned on. Thus, the voltage of the node A is increased and the voltage of the node B is reduced to a fixed value. 
         [0035]    During a period T 52 , the luminiferous signal S EMIT  is in the low level such that the transistors Q 1 ˜Q 3  are turned off. The charge signal S Pre  is in the high level such that the charge switch  330  is turned off. Thus, the voltage of the node A is maintained at a fixed value. Since the scan signal S SCAN1  is in the low level, the transistor  318  is still turned on. Thus, the voltage of the node B is increased. At this time, the voltage of the node B relates to the threshold voltage of the transistor  314 . Thus, the different threshold voltage problem can be compensated. 
         [0036]    Additionally, if the controller  128  provides the voltage signal PVDD, when the distance between the controller  128  and the pixel unit is longer, the voltage signal PVDD may be reduced. Since the voltage of the node B relates the voltage signal PVDD during the period T 52 , when the different pixel units receive the different voltage signals, the different voltage signals problem can be compensated. 
         [0037]    During the first portion of a period T 53 , since the scan signal S SCAN1  is in the low level, the transistor  318  is turned on. Thus, the voltage of the node B is increased. During the second portion of the period T 53 , since the scan signal S SCAN1  is in the high level, the transistor  318  is turned off. Thus, the voltage of the node B is maintained at a fixed value. When the source driver  124  provides the data signal S DATA  via the data line D 1 , the voltage of the node A is reduced. At this time, the voltage of the node A relates to the data signal S DATA . 
         [0038]    During the first portion of a period T 54 , since the charge signal S Pre  and the scan signal S SCAN2  are in the high level and the luminiferous signal S EMIT  is in the low level, the charge switch  330 , transistors  328  and Q 1 ˜Q 3  are turned off. Thus, the voltage of the node D is maintained at a fixed value. Since the data line D 1  does not provide the data signal S DATA , the voltage of the node C is maintained at a fixed value. During the second portion of the period T 54 , since the charge signal S Pre  and the scan signal S SCAN2  are in the low level and the luminiferous signal S EMIT  is in the high level, the charge switch  330 , transistors  328  and Q 1 ˜Q 3  are turned on. Thus, the voltage of the node D is reduced to a fixed value. Since the data line D 1  does not provide the data signal S DATA , the voltage of the node C is maintained at a fixed value. 
         [0039]    During a period T 55 , the luminiferous signal S EMIT  is in the low level such that the transistors Q 1 ˜Q 3  are turned off. The charge signal S Pre  is in the high level such that the charge switch  330  is turned off. Thus, the voltage of the node C is maintained. Since the scan signal S SCAN2  is in the low level, the transistor  328  is still turned on. Thus, the voltage of the node D is increased. At this time, the voltage of the node D not only relates to the threshold voltage of the transistor  324 , but also relates to the voltage signal PVDD. 
         [0040]    During a first portion of a period T 56 , since the scan signal S SCAN2  is in the low level such that the transistor  328  is turned on. Thus, the voltage of the node D is increased. During a second portion of the period T 56 , since the scan signal S SCAN2  is in the high level such that the transistor  328  is turned off. Thus, the voltage of the node D is maintained at a fixed value. When the source driver  124  provides the data signal S DATA  via the data line D 1 , the voltage of the node C is reduced or increased according to the data signal S DATA . At this time, the voltage of the node C relates to the data signal S DATA . 
         [0041]    During the period T 57 , the charge signal S Pre , the scan signals S SCAN1  and S SCAN2  are in the high level such that the charge switch  330 , the transistors  318  and  328  are turned off. Since the luminiferous signal S EMIT  is in the high level, the transistors  314  and  324  are operated in a saturation region. The transistor  314  generates a driving current according to the voltage of the capacitor  312 . The luminiferous device  316  is lit according to the driving current generated by the transistor  314 . The transistor  324  generates a driving current according to the voltage of the capacitor  322 . The luminiferous device  326  is lit according to the driving current generated by the transistor  324 . When the driving current is higher, the brightness of the luminiferous device is higher. Additionally, the data signal S DATA  is maintained during the period T 57 . 
         [0042]    While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.