Abstract:
A configurable circuit array that includes a matrix of cells, where each cell includes interconnected analog and/or digital circuit elements. The cells are fabricated on a common semiconductor substrate, and are electrically isolated from each other. The circuit elements in the cells are electrically coupled to circuit elements in other cells, and are electrically coupled to bonding pads by coaxial transmission lines capable of transmitting extremely high frequency signals. The transmission lines include a center conductor and first and second shield conductors, where the shield conductors prevent cross-talk interference. The transmission lines extend vertically from the substrate until they are a suitable distances above the circuit elements in the cell. From there, the transmission lines extend horizontally relative to the substrate to the opposite end connection point, where they again extend vertically down to the substrate.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to a configurable circuit array for high frequency applications and, more particularly, to a configurable circuit array employing a matrix of cells including active circuit elements that are interconnected by coaxial high speed transmission lines. 
     2. Discussion of the Related Art 
     Modern high speed digital communications systems transmitting very high data rates, 10–40 Gbps, typically transmit optical signals carrying digital data down a fiber optic cable to transfer the data. The fiber optic cable includes a waveguide core having one index of refraction that is surrounded by a cladding layer having another, lower, index of refraction. Optical signals propagating down the core at a certain angle of incidence are reflected off of the core/cladding transition to be contained therein. 
     The optical signals propagating through the fiber optic cable are distorted by the waveguide medium. This distortion may cause loss of data when the optical signal is demodulated at the receiver to remove the information therefrom. Optical distortion typically comes from two sources, chromatic dispersion and polarization modulation dispersion. Polarization modulation dispersion occurs because the light in the optical signal having one polarization orientation travels faster than the light in the signal at other polarization orientations. In other words, regardless of whether the polarization of the signal is circular, elliptical, linear, etc., the axis of the polarization rotates so that when the signal is oriented along one particular axis it will travel faster than when it is oriented along another axis. 
     Chromatic dispersion is related to the frequency of the optical signal, where chromatic dispersion increases the farther the signal propagates and the wider the signal bandwidth. Further, light at higher frequencies propagates faster than light at lower frequencies. Chromatic dispersion occurs because as the optical signal propagates through the fiber optic cable and is reflected off of the transition between the core and cladding layer, some parts of the signal have a different path length than other parts of the signal and thus travel a different distance. Because the optical signal may travel through the fiber cable several thousand miles between a transmitter and a receiver, the distortion may be significant. 
     Both chromatic dispersion and polarization dispersion cause the digital coded bits in the signal to be at different places (forward or backward) in the signal than would be expected, thus affecting the ability to recover the bits in the receiver. Particularly, some of the several parts of a bit may be included in the symbol of a previous or next symbol. Thus, the distortion affects the reliability of decoding the bits to remove the information. Because the distortion is linear, the process that distorted the signal can be inverted to provide a corrected signal. 
     It is known in the art to employ equalizers in the receiver of a fiber optic communications systems for reconstructing the corrupted signal before it is decoded to correct for distortions caused by chromatic and polarization dispersion. Generally, the equalizer restores the waveform of the signal by inversion of the transform of the distortions caused by the fiber optic cable. The equalizer defines a transform that is the inverse of the distortion process caused by the fiber cable. Equalizers known in the art include a finite impulse response (FIR) equalizer, sometimes called a feed forward equalizer (FFE) processor, and an infinite impulse response (IIR) equalizer, sometimes called a decision feedback equalizer (DFE) processor when a decision circuit is employed. The DFE processor is different than the FFE processor because it employs a feedback loop. However, as is understood in the art, FFE processors and DFE processors have different advantages and drawbacks. 
     The optical signal is converted to an RF analog signal prior to being applied to the equalizer. For very high frequency applications, the wavelength of the signal is short enough that it easily fits on small integrated circuit chips. The equalizer samples the RF analog signal at spatial locations along the signal waveform. The signal is multiplied by a weight value applied to a tap at each sample location to provide the distortion correction. Each weighted signal is summed with the weighted signals from the other sample locations. Thus, the distortions in the signal are corrected through the dot product of the signal and weight vectors. 
     The equalizers known in the art are effective for correcting signal distortions in optical communications systems. However, as the processor speeds and data rate speeds increase, it becomes increasingly more difficult to sample the signals by the known techniques to provide the signal reconstruction because the electronic elements, such as analog-to-digital converters, multipliers, summers, etc., would need to be too large, require too much power and would be unable to operate fast enough. For example, to correct a 40 Gbps signal, the signal would need to be sampled at the Nyquist sampling rate or greater, which could be about 120 giga-samples per second. At this data rate, the sampled signal would have to be delayed, multiplied and summed in each sample stage of the equalizer in about 8.3 picoseconds which is currently unattainable. Thus, it is necessary to provide different techniques than are currently known to sample and weight the distorted signals in an equalizer with state of the art techniques. 
     SUMMARY OF THE INVENTION 
     In accordance with the teachings of the present invention, a configurable circuit array is disclosed that includes a matrix of cells, where each cell includes interconnected analog and/or digital circuit elements. The cells are fabricated on a common semiconductor substrate, and are electrically isolated from each other. Circuit elements in the cells are electrically coupled to circuit elements in other cells and are electrically coupled to bonding pads by coaxial transmission lines capable of transmitting extremely high frequency signals. The transmission lines include a center conductor and first and second shield conductors, where the shield conductors prevent cross-talk interference. The transmission lines are electrically connected to traces on the substrate, and extend vertically from the substrate until they are a suitable distance above the circuit elements in the cell. From there, the transmission lines extend horizontally relative to the substrate to the opposite end connection point, where they again extend vertically down to the substrate. In addition to providing electrical coupling, the length of the transmission line provides a desirable functional signal delay. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an equalizer for correcting wave distortions in a signal, where the equalizer includes an adaptive weight processor, according to an embodiment of the present invention; 
         FIG. 2  is a schematic block diagram of the equalizer shown in  FIG. 1  where the adaptive weight processor includes a correlative error detection system, according to an embodiment of the present invention; 
         FIG. 3  is a schematic diagram of the correlative error detection system removed from the equalizer shown in  FIG. 2 ; 
         FIG. 4  is a graph showing simulation data for the correlative error detection system shown in  FIG. 3 ; 
         FIG. 5  is a schematic block diagram of an equalizer including a feed forward equalizer processor and a decision feedback equalizer processor both employing micro-electromechanical devices for providing weight tap controls, according to an embodiment of the present invention; 
         FIG. 6  is a cross-sectional view of the feed forward equalizer processor shown in  FIG. 5 ; 
         FIG. 7  is a top view of a circuit array configuration employing a cell architecture, according to an embodiment of the present invention; 
         FIG. 8  is printed tape coaxial transmission line employed in the circuit array configuration shown in  FIG. 7 ; and 
         FIG. 9  is a cross-sectional view of a portion of the circuit array configuration shown in  FIG. 7 . 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The following discussion of the invention directed to a configurable circuit array employing coaxial transmission lines is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses. 
       FIG. 1  is a general block diagram of an equalizer  10 , according to an embodiment of the present invention, employing an FFE processor  12  and a DFE processor  14 . The FFE processor  12  receives a distorted RF signal. In one embodiment, the RF signal is a converted optical signal in an optical communications system. The processors  12  and  14  sample the signal at predetermined spatial tap locations to provide a measure of the signal and a correction of the distortion in the signal based on a processor transform. The sampled signal from the processors  12  and  14  are applied to a summer  16  that sums the sampled and weighted signal from the processor  12  with the sampled and weighted signal from the processor  14 . The summed signal is applied to an adaptive weight processor  18  that provides weight values to control taps at the spatial sample locations in the processors  12  and  14  to correct the distortion in the signal. Thus, by providing the weight values to the taps along the signal path in both the processors  12  and  14 , the distortion in the RF signal can be corrected to provide an equalized output signal from the processor  18 . The operation of DFE and FFE processors for this purpose is well understood to those skilled in the art. 
       FIG. 2  is a schematic block diagram of the equalizer  10 . The FFE processor  12  and the DFE processor  14  include a plurality of stages  32  that spatially sample and weight the analog input signal, as will be discussed in more detail below. The consecutive stages  32  allow the sampling to be performed spatially as the signal propagates through the processors  12  and  14 . The stages  32  are separated by a predetermined distance to provide a tapped delay line, where the distance between the stages is a tightly controlled delta t. Only one of the stages  32  will be discussed herein with the understanding that the other stages  32  operate in the same manner. The particular operation of each stage  32  and how it applies a weight value to the signal is well understood to those skilled in the art. In this example, the FFE processor  12  includes five stages  32  and the DFE processor  14  includes three stages  32 . However, this is by way of a non-limiting example in that other FFE and DFE processors may employ other numbers of stages. 
     Each stage  32  includes a weighting junction  42  and a coding system  44 . The input signal to the processor  12  or  14  is applied to an isolation amplifier  34  in the weighting junction  42 . The amplified input signal is applied to the next stage  32  and to a multiplier  36  in the current stage  32 . The multiplier  36  multiplies the signal by a weight value from the coding system  44  to convolve the signal with the weight value. The coding system  44  generates a unique coded weight value received from a weight computer  40 . The weight computer  40 , discussed in more detail below, employs any one of several known algorithms to generate the weight values in response to detected or measured distortions in the input signal. 
     In one embodiment, the coding system  44  employs code division multiple access (CDMA) so that each stage  32  is defined by a unique code. A CDMA system of this type for this environment is disclosed in U.S. Pat. No. 6,167,024, assigned to the assignee of this application, and herein incorporated by reference. Each of the coding systems  44  allow the weight signals to be multiplexed through the several stages  32 . The specific application of using the weighting junctions  42  and the coding systems  44  is by way of example in that other types of FFE and DFE implementations can be employed within the scope of the present invention. 
     The signal applied to the multiplier  36  from the coding system  44  is the tap weight value for the stage  32 . The multiplied signal from the multiplier  36  is then applied to a summer  38  that is summed with the multiplied signal from all of the following stages  32 . Thus, each stage  32  provides a sample of the signal at a spatial location, where all of the signals from the stages  32  are summed. According to convention, each weighted signal from all of the weighting junctions  42  are summed by the following equation: 
                     ∑     t   =   1     m     ⁢           ⁢       s   ⁡     (   t   )       ·     w   ⁡     (   t   )                 (   1   )               
where s(t) is the input signal at a particular tap, w(t) is the weight value that is multiplied by the signal at that tap and m is the number of stages  32 . The weighted signals from the FFE processor  12  and the DFE processor  14  are applied to the summer  16  that combines the signals in the manner that is known in the art.
 
     Eye chart analysis, known to those skilled in the art, is used to determine whether the optical signal waveform is transmitting a one bit or a zero bit at a particular point in time. An “open eye” state allows a threshold to be used to determine whether the magnitude of the waveform identifies a one or a zero bit. As the eye closes, it becomes more difficult to reliably identify the bit. Therefore, error detection devices are employed in equalizers to insure that the signal has a certain magnitude when a one bit is detected and a certain magnitude when a zero bit is detected. The adaptive weight processor  18  continually adjusts the weight values applied to the junctions  42  to keep the eye open. 
     In known equalizers, a voltage comparator operating as a regenerative high gain amplifier generally detected the error. Because the data rates are so high and the voltages are so small in state of the art communications system, the decision time to determine whether an error exists is very small, possibly on the order of 6 picoseconds, and has a sensitivity on the order of 1% full scale. Therefore, the known technique of error detection is not effective. 
     According to the invention, a correlative error detection process is performed to set the weight value applied to each of the weighting junctions  42  to minimize the distortion in the input signal.  FIG. 3  is a block diagram of a correlative error detection system  60 , according to the invention, separated from the equalizer  10 . The error detection system  60  provides error detection at very high data rates, using minimal power, with the desired accuracy and within a very small time window. Generally, the system  60  looks for a random series of bits (symbol), and provides a correlative signal peak when the series of bits is detected. Thus, the system  60  operates as a sliding window correlator. For example, the system  60  may be programmed to provide the correlative signal peak if a 1010 bit stream is detected at a predetermined time. Because the bit sequence is four bits in length, the 1010 sequence will occur on average once every sixteen times (2 n ) in a random data stream. By adjusting the weight values applied to the tap junctions  42 , the peaks will modulate in amplitude. Thus, the error detection system  60  operates as a discriminator to identify when the waveform of the predetermined series of bits has the desired shape (open eye). 
     To perform the above described auto-correlation process, it is necessary to convert the bit symbol to a numerical value suitable for arithmetic functions. For example, the bit sequence  1010  is converted to 1, −1, 1, −1 and represents the condition for the ideal weight values for the equalizer  10 . This sequence of correlation values can be changed in length and number in other embodiments, however, four values provides good amplitude resolution above the distortion floor and good transitions between values. Further, the four value sequence provides a processing gain of 6 dB in voltage. In the convolving process, points in the signal are multiplied by each weight value and then added together. Thus, a maximum signal output (peak) occurs when the points in the corrected signal match the desirable weight value sequence. The operation of the system  60  thus acts as a matched filter. 
     The signal from the summer  16  is applied to a differential amplifier  62  that splits the signal into itself and its compliment. The negative part of the signal is the input to the DFE processor  14 , although, in alternate embodiments, the positive part of the signal can be used for the input to the DFE processor  14 . Splitting the signal in this manner reduces the hardware downstream. Both the signal and the compliment of the signal are applied to a series of delay devices  64  that delay the signal for a predetermined period of time. The signal and its compliment are tapped four times, once for each of the four correlation values (1, −1, 1, −1). Particularly, a first tap  50  taps the signal directly from the amplifier  62 , a second tap  52  taps the compliment of the signal after it has been delayed by one delay device  64 , a third tap  54  taps the signal after it has been delayed by two delay devices  64  and a fourth tap  56  taps the compliment of the signal after it has been delayed by three delay devices  64 . Thus, a partial correlation of the signal is provided every delay period. The delay devices  64  could allow the signal to be correlation processed at four separate locations in the signal at the same time. 
     The tapped signals are applied to a summing network  66  that sums the tapped signals to provide the summation portion of a dot product for the correlation process. When the signal components match the sequence of values, the correlator output of the summing network  66  is a maximum amplitude. Lesser amplitudes are output from the network  66  depending on how close the signal components are to the values. 
     Because the duration of the peaks in the correlated signal is very small, less than a picosecond, it is necessary to hold the peak for a longer duration of time for subsequent processing. To perform the peak hold, the correlated signal from the system  60  is applied to a positive peak detector  72  and a negative peak detector  74 . The positive peak detector  72  compares the correlated signal to a predetermined threshold to detect when a positive peak of a certain magnitude occurs in the signal, and holds the peak for some longer period of time. The negative peak detector  74  compares the correlated signal to a predetermined threshold to detect when a negative peak of a certain magnitude occurs in the signal, and holds the peak value for a longer period of time. 
     The peak detectors  72  and  74  can be any peak detector suitable for the purposes described herein. In  FIG. 2 , the peak detectors  72  and  74  are shown as a capacitor and diode circuit  76 , sometimes referred to as an envelope detector. The combination of a positive peak detector and a negative peak detector is employed because there is equal significance if the signal components are exactly opposite to the correlation value sequence (−1, 1, −1, 1). So, either the positive or negative peak can be used for the error correction, and both peaks can be differentiated for offset control. 
     The detected peaks values from the peak detectors  72  and  74  are sent to the weight computer  40 . The weight computer  40  analyzes the frequency at which the peaks are received to make a determination that the signal is properly corrected. The weight computer  40  provides the weight values that are coded by the coding systems  44  and then applied to the multipliers  36 . The weight computer  40  continuously changes the weight values to search for the proper peak value as the metric of distortion in the signal. The weight computer  40  can employ any of the well known algorithms for the purpose, such as tau dither algorithms, hypothesis searching algorithms, gradient searching algorithms, steepest decent algorithms, zero-forcing algorithms, etc. 
       FIG. 4  is a graph with magnitude on the vertical axis and time on the horizontal axis showing simulation data for the correlative error detector system  60  of the invention. The graph includes a graph line  80  showing signal and noise, a graph line  82  showing signal, noise and distortion, a graph line  84  showing an un-distorted correlation signal and a graph line  86  showing a distorted correlation signal. 
       FIG. 5  is a schematic diagram of an equalizer  92  that performs the same function as the equalizer  10  discussed above, but employs micro-electromechanical (MEM) devices in the FFE and the DFE to reduce power consumption, according to an embodiment of the invention. The equalizer  92  includes an FFE processor  94 , a DFE processor  96  and an adaptive weight processor  98 . The FFE processor  94  and the DFE processor  96  process differential signals in this embodiment. A differential signals has two complimentary parts that are opposite in amplitude, the signal being the difference between them. As is known in the art, differential signals are sometimes used in communications systems to provide greater noise immunity. 
       FIG. 6  is a cross-sectional view of the processor  94 . The processor  96  would look the same. To accommodate the differential signals, the FFE processor  94  includes a negative signal portion  106  and a positive signal portion  108 . If the input signal was not differential, then only one of the portions  106  or  108  would be required. The negative portion  106  includes a forward transmission line rail  112  and a return transmission line rail  114  formed on an MEM substrate  116 , where the rails  112  and  114  are parallel and spaced apart from each other, as shown. Likewise, the positive portion  108  includes a forward transmission line rail  118  and a return transmission line rail  120  also formed on the substrate  116 , where the rails  118  and  120  are parallel and spaced apart from each other, as shown. Each of the rails  112 ,  114 ,  118  and  120  are electrically connected at one end to a separate load resistor  124  that is coupled to ground. 
     The negative portion  106  includes a cantilever stanchion rail  130  mounted along one edge of the substrate  116 . A plurality of spaced apart cantilevers  132  are pivotally mounted to the cantilever stanchion rail  130  by any suitable MEM fabrication technique. The cantilevers  132  extend over the transmission line rails  112  and  114  to form a gap therebetween, as shown. Likewise, the positive portion  108  includes a cantilever stanchion rail  134  mounted along an opposite edge of the substrate  116 . A plurality of cantilevers  138  are pivotally mounted to the cantilever stanchion rail  134  and extend over the transmission line rails  118  and  120  to form a gap therebetween. The transmission line rails  112  and  118  and the series of cantilevers  132  and  138  provide the required delay for the tapped delay line of the FFE processor  94 . 
     The substrate  116  can be any suitable material for the purposes described herein, such as InP, GaAs, etc. The transmission line rails  112 ,  114 ,  118  and  120  can be any suitable metal that propagates an electrical signal therethrough, and can be formed on the substrate  116  by any suitable fabrication technique. The cantilever rails  130  and  134  can be any suitable dielectric material formed on the substrate  116 , and the cantilevers  132  and  138  can be any suitable metal that flexes in response to a DC bias. The sizes of the various elements of the equalizer  92  discussed herein would be readily recognizable to those skilled in the art for a particular environment. 
     The distance between the particular cantilever  132  or  138  and the associated rail  112 ,  114 ,  118  or  120  determines the electrical coupling therebetween. Particularly, the narrower the gap, the more of the electrical signal is transferred from the transmission line rail  112 ,  114 ,  118  or  120  to or from the cantilever  132  or  138 . The cantilevers  132  and  138  pivot on the respective cantilever stanchion rails  130  and  134 . Each cantilever  132  and  138  includes a weight tap  144  electrically coupled thereto. By providing a DC bias to the tap  144 , the gap between the respective cantilever  132  or  138  and the transmission line rail  112 ,  114 ,  118  or  120  can be controlled. The more bias that is applied to the cantilever  132  and  138  so as to increase the electrostatic repulsion, the wider the gap becomes. 
     An error output signal from the adaptive weight equalizer  98  provides the bias signal to the taps  144  to provide the weight value. A distorted RF input signal is applied to sequential differential amplifiers  148  and  150  in the adaptive processor  98 . The positive differential signal from the amplifier  150  is applied to the forward transmission line rail  118 , and the negative differential signal from the amplifier  150  is applied to the forward transmission line rail  112 . The signal propagates down the transmission line rails  112  and  118  to the load resistors  124 . Each time the signal in the transmission line rail  112  and  118  travels beneath the respective cantilever  132  or  138 , a portion of the signal is coupled onto the cantilever  132  or  138 . The width of the gap determines how much of the signal is coupled onto the cantilever  132  or  138 . Thus, a portion of the signal is transferred from the rail  118  through the particular cantilever  138  to the return transmission line rail  120 , and from the rail  112  through the particular cantilever  132  to the return transmission line rail  114 . Therefore, each time the return signal gets to a cantilever  132  or  138  on the return rail  114  or  120 , that signal is added to the signal coupled from the forward transmission line  112  or  118  at that cantilever  132  or  138 . Each cantilever  132  and  138  provides the addition of the signal to the signal traveling on the return rail  114  and  120  in the same manner as the summers  38  to provide the signal summing of equation (1). The DFE processor  96  also includes the same MEM cantilever structure as the FFE processor  94 . 
     The positive summed signal on the return rail  120  is applied to a summer  154 , and the negative summed signal on the return rail  114  is applied to a summer  156 . Likewise, the positive summed signal from a positive return transmission line rail  160  of the DFE processor  96  is applied to the summer  154 , and the negative summed signal from a negative return transmission line rail  162  of the DFE processor  96  is applied to the summer  156 . The summers  154  and  156  sum the differential signals from the FFE processor  94  and the DFE processor  96 , and apply the summed signals to a differential amplifier  158 . The positive part of the differential signal from the amplifier  158  is applied to a positive forward transmission line rail  164  of the DFE  96  through a delay device  166 . Likewise, the negative part of the differential signal from the amplifier  158  is applied to a negative forward transmission line rail  168  through a delay device  170 . A delay control is applied to the delay devices  166  and  170  to set the amount of delay, as would be understood by those skilled in the art. Thus, the DFE processor  96  provides the feedback. Additionally, the positive and negative parts of the differential signal from the amplifier  158  are applied to an output differential amplifier  172  to provide the reconstructed signal for subsequent processing. 
     The equalizer  92  includes an error detection circuit  180  that is an alternative to the correlative error detection system  60 , discussed above. For very high data rates, the error detection circuit  180  can be replaced with the system  60 . A decision threshold signal and the negative part of the differential output signal from the amplifier  158  are applied to a comparator  182  to determine whether the signal is above or below a threshold, at a particular instant in time, to determine if the eye is open, as discussed above. If the output signal from the amplifier  158  is above the threshold, a digital high signal is provided from the comparator  182  as a D input to a latch  186 . A clock signal from a latch  184  provides the clock input to the latch  186  at a lower frequency. When the input to the latch  186  is high, it is transferred to the output Q at the next clock signal. A compliment of the output Q is provided at Q-bar so that high signals are provided for when the output signal is both above and below the threshold. The error output signal is then sent to a weight computer (not shown) that can be the weight computer  40  discussed above, where the weight computer sets the bias signal applied to the taps  144  in both the FFE processor  94  and the DFE processor  96  to perform the distortion correction as discussed herein. 
     The equalizers  10  and  92  can be used in various devices in fiber optic and RF communications systems. For example, the equalizers can be employed in, but not limited to, sliding window correlators used in cable and RF modems and codecs; general filtering processors such as high pass, low pass, band pass and notch filters; and matched filters used in data recognizers. 
     Specialized circuit element layouts on an integrated circuit board are typically necessary for high frequency electronic systems, such as the equalizers  10  and  92  discussed above. Because the frequencies are very high in these applications, the size of the circuit elements can be made very small, and can be provided in a compact design on an integrated circuit board. However, when metallized traces and the like are provided on such a compact circuit board, the element interconnects cause serious problems with parasitic inductances and capacitances and cross-talk that significantly degrades the performance of the device. Therefore, specialized designs are required for such compact circuits operating at extremely high frequencies. 
       FIG. 7  is a top view of a configurable circuit array  200 , according to an embodiment of the present invention. The circuit array  202  includes a circuit matrix of element cells  202 , where each cell  202  includes interconnected analog and/or digital circuit elements and devices, such as amplifiers, multipliers, summers, differential comparators, detectors, passive and active filters, digital-to-analog and analog-to-digital converters, mixers, latches, etc. In one non-limiting embodiment, the cells  202  are square cells as shown in  figure 7 . The various circuit elements configured in the cells  202  are patterned on an integrated circuit or semiconductor substrate  204  in this matrix design. A series of ribbon or wire bonding metal pads  206  are provided along opposing edges of the substrate  204  that provide a location where the input and output signals of the various elements in the cells  202  are transferred on and off chip. 
     According to the invention, shielded coaxial transmission lines  208  are used to interconnect the various circuit elements in the different cells  202  to each other and to the bonding pads  206 .  FIG. 8  is a plan view of one of the transmission lines  208  separated from the array  200 . The transmission line  208  includes a center conductor  212  that is coupled to solder bumps  214  at opposite ends. The center conductor  212  is shielded by a first shield conductor  216  that is coupled to solder bumps  218  at opposite ends, and a second shield conductor  220  coupled to solder bumps  222  at opposite ends. The center conductor  212  and the shield conductors  216  and  220  are encased in a dielectric medium  224  that keeps them electrically isolated from each other. Two center conductors can be provided for differential signals. 
       FIG. 9  is broken-away, cross-sectional view of the configurable array  200  showing the substrate  204  and a portion of one of the cells  202 . A plurality of active circuit elements  230  are formed on the substrate  204  in the cell  202 . A transmission line  232  is connected to electrical contacts in the cell  202  to provide the various electrical connections. The transmission line  232  includes a center conductor  234 , a top shield layer  236  and a bottom shield layer  238 . The top and bottom shield layers  236  and  238  and the center conductor  234  are connected to solder bumps  240  on the substrate  204 . The center conductor  234  and the shield layers  236  and  238  are formed in a dielectric medium  248  so that they extend away from the substrate  204  a certain distance before they extend horizontal to the substrate  204 . This prevents the radiation from the active elements from affecting the signal on the conductor  234 . Via conductors  242  are coupled to a top shield layer  244  and to a solder bump  246  on the substrate  204 . 
     The array  200  employing the transmission lines  208  has particular application for the equalizers  10  and  92  discussed above. The transmission lines  208  provide the desired delays and the necessary shielding between the circuit elements without appreciable losses or distortion. The various parameters of the transmission lines  208 , i.e., length, width, conductor size, etc., are tightly controlled to provide the desired performance. Further, the transmission lines  208  are terminated into their characteristic impedance. Also, the transmission lines  208  are designed to have matched capacitance and inductance to have only a real component. The array  200  has other circuit applications beyond equalizers, including, but not limited to, sliding window correlators, high pass, low pass, band pass, notch and matched filters, serial-to-parallel and parallel-to-serial converters, sample and holds, multiplexers, clock and date recovery, etc. 
     The foregoing discussion discloses and describes merely exemplary embodiments of the present invention. One skilled in the art will readily recognize from such discussion and from the accompanying drawings and claims that various changes, modifications and variations can be made therein without departing from the spirit and scope of the invention as defined in the following claims.