Abstract:
The disclosure generally relates to a method and apparatus for providing high-speed, low signal power amplification. In an exemplary embodiment, the disclosure relates to a method for providing a wideband amplification of a signal by forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The disclosure generally relates to wideband distributed amplifiers. More specifically, the disclosure relates to a method and apparatus for providing high-speed, low signal power amplification using superconducting technology. 
         [0003]    2. Description of Related Art 
         [0004]    A well-known wideband amplifier known as a distributed amplifier amplifies the incoming signal to an output signal commensurate with the desired amplification level. Distributed amplifier architecture introduces delay to achieve wideband characteristics. Conventional distributed amplifiers include a pair of transmission lines, each having a characteristic impedance, for independently connecting the inputs and outputs of several active devices. 
         [0005]      FIG. 1  shows the circuit diagram for a conventional distributed amplifier (“DA”). In  FIG. 1 , input signal  100  is directed to a first transmission line  110  having impedances Z I-1  to Z I-5 . The amplified output signal  190  is provided by the transmission line  120  which includes impedances Z O-1  to Z O-5 . In the embodiment of  FIG. 1 , active devices are modeled as field effect transistors (“FET”) Q 1 , Q 2 , Q 3  and Q 4 . As the input signal  100  propagates down the input transmission line  100 , each FET responds to the forward-traveling input step by inducing an amplified forward-traveling wave on the output transmission line  120 . The number of active devices defines the number of stages for the DA. The amplifier of  FIG. 1 , shows 4 stages. 
         [0006]    The gain of the distributed amplifier is additive rather than multiplicative. The gain is determined, in part, by the number of stages. This property enables the distributed amplifier to provide a gain at frequencies beyond that of the unity-gain frequency of any individual stage. The delays of the input transmission line  110  and the output transmission line  120  can be made equal through the selection of propagation constants and line lengths to ensure that the output signals from each individual device sums in phase. Both input and output lines must be resistively terminated, by resistors  130  and  140 . A major drawback of the conventional distributed amplifier is poor efficiency because power matching and phasing cannot be achieved at the same time. 
         [0007]    A conventional distributed amplifier is also inoperable with high-speed superconducting systems. Superconductor digital circuits feature high clock rates (i.e., 10-40 GHz) and extremely low signal power levels (i.e., 2-8 nW). Superconductor circuits are ideally suited for mixed-signal applications such as analog to digital conversion due to high sample rates and quantum accurate feedback distributed amplifiers, which use the same operating principles as the metrological voltage standard. However, because signal levels are so low and data rates are so high, establishing data links to conventional electronics, at low bit error rate, has been proved difficult. 
         [0008]    Therefore, there is a need for a method and apparatus to provide a distributed amplifier adapted to high clock rates and low signal power. 
       SUMMARY 
       [0009]    In one embodiment, the disclosure relates to a method for providing a wideband amplification of a signal, the method comprising: forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines to provide a wideband amplification of an input signal. 
         [0010]    In another embodiment, the disclosure relates to a distributed amplifier circuit comprising: a first transmission line and a second transmission line, each of the first transmission line and the second transmission line having a plurality of Josephson Transmission lines (“JTLs”), each JTL having a Josephson transmission delay; a plurality of resonant circuits connected in series and including a voltage source controlled with at least one of the first transmission line or the second transmission line, one of the plurality of the resonant circuits having a resonant transmission delay; wherein the resonant transmission delay is substantially matched to the Josephson transmission delay of at least one of the plurality of JTLs. 
         [0011]    In still another embodiment, the disclosure relates to a superconductor driver for high throughput data amplification, comprising: a first amplification stage having a first Josephson transmission line (JTL) and a second Josephson transmission line with a resonant circuit interposed therebetween, the first Josephson transmission line having a first transmission line delay and the second Josephson transmission line having a second transmission line delay, the resonant circuit configured to have a resonant circuit delay substantially matching the first transmission line delay. 
         [0012]    In yet another embodiment, the disclosure relates to a superconducting amplifier comprising: a first transmission line having a plurality of Josephson transmission lines (JTLs) connected in series, each JTL having a respective JTL delay; a plurality of voltage sources arranged in series with a plurality of resonant circuits, each of the plurality of voltage sources electro-magnetically communicating with at least one JTL; and wherein each voltage source defines a SQUID which is set and reset through an inductive coupling with one of the JTLs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    These and other embodiments of the disclosure will be discussed with reference to the following exemplary and non-limiting illustrations, in which like elements are numbered similarly, and where: 
           [0014]      FIG. 1  shows the circuit diagram for a conventional distributed amplifier; 
           [0015]      FIG. 2  schematically illustrates a distributed amplifier according to one embodiment of the disclosure; 
           [0016]      FIG. 3  schematically illustrates the device-level detail of the distributed amplifier of  FIG. 2 ; and 
           [0017]      FIG. 4  schematically illustrates a distributed amplifier according to another embodiment of the disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]      FIG. 2  schematically illustrates a distributed amplifier according to one embodiment of the disclosure. Circuit  200  of  FIG. 2  illustrates a 12 stage amplifier represented by stages  1 ,  2  . . .  12 . For brevity, only stages,  1 ,  2  and  12  are shown. Each stage is shown as having a voltage source. Thus, the first stage includes voltage source  201 ; the second stage is shown with voltage source  202 . Amplification stage  12  is shown with voltage source  212 . Each stage may optionally include a lumped resonant circuit connected to the voltage source. In  FIG. 2 , voltage source  202  is connected to inductor  203  and capacitor  204 . Inductor  203  and capacitor  204  form a lumped resonant circuit. Similarly, voltage source  12  is connected to inductor  213  and capacitor  214 . 
         [0019]      FIG. 2  also shows bias  254  connected in parallel with resistor  253 . In an exemplary application, termination resistor  255  was matched to resistor  253  and each was provided with 50 Ω resistance. A lumped circuit comprising inductor  251  and capacitor  252  are connected in series with bias  253 . Circuit  200  terminates in the 50 Ohm resistor  255 .  254  and  253  are not explicit parts of the amplifier, but are external power supply and load. Resistor  255  may be an explicit part of the amplifier, or it may also be an external load. 
         [0020]    In  FIG. 2 , a combination of an inductor and a capacitor forms a lumped LC circuit having a characteristic transmission delay. Determining the value of the transmission delay through the lumped circuit is well-known in the art and is not discussed here. In one embodiment of the disclosure, inductors  203 ,  213  and other inductors in circuit  200 , are selected to have an identical inductance. In another embodiment of the disclosure, inductors for each stage can be selected to have a unique inductance value independent of the inductors in other amplification stages. Similarly, capacitors  204 ,  214  can be selected to provide substantially identical capacitance with the other capacitors of different amplification stages. In another embodiment, a capacitor can be selected to have a unique capacitance value independent of the capacitors of the other amplification stages. 
         [0021]    Transmission lines  230  and  240  are formed in parallel and communicate set/reset signals to each amplification stage. In the embodiment of  FIG. 2 , transmission line  230  provides set signal  232  to amplification stages  1 - 12  while transmission line  240  provides reset signal  242  to amplification stages  1 - 12 . 
         [0022]    In one embodiment of the disclosure, transmission lines  230  and  240  are configured to have one or more Josephson transmission lines (“JTLs”) for transmitting the set/reset signals. Josephson transmission lines are advantageous for providing high clock rates and low signal power. Each JTL has a characteristic transmission delay. Referring to  FIG. 2 , JTLs  233  and  235  are serially connected along transmission line  230  and JTLs  243  and  245  are serially connected along transmission lines  240 . 
         [0023]    According to one embodiment of the disclosure, an amplification stage comprises two JTLs connected in parallel with a voltage source and a resonant circuit interposed therebetween. Referring to exemplary embodiment of  FIG. 2 , JTL  233  and JTL  243  are connected to voltage source  202 . JTL  233  provides set signal  232  to voltage source  202  while JTL  243  provides reset signal to voltage source  202 . The second amplification stage also includes inductor  203  and capacitor  204  connected in series with voltage source  202 . While the exemplary embodiment of  FIG. 2  shows inductor  203  and capacitor  204  as the resonant circuit, it should be noted that the disclosure is not limited exclusively to an inductor and a capacitor connected to the voltage source. Indeed, any active or passive circuit configuration having a characteristic delay can be used in place of a resonant circuit. For example, the delay could be provided by a passive transmission line circuit. 
         [0024]    The set signal  232  and reset signal  242  provide extremely small, single flux quantum (“SFQ”) voltage pulses to each amplification. An exemplary set/reset signal may be about 0.5 mV high and 4 pS wide, FWHM. The SFQ signals are distributed on the active JTLs and turn ON and OFF the voltage sources connected in series. In one embodiment, each JTL was built to provide about 6 pS delay. The resonant circuit was selected to have a resonant delay of about 6 pS, thereby matching the resonant delay of the JTLs. Thus, the resonant circuit delay was matched to a JTL delay of about 6 pS. The resonant circuit also provided 50 Ohm impedance and the circuit provided 20 GHz bandwidth, supporting 10 Gb/S NRZ data. The amplifier bandwidth-gain product was substantially higher than that of the conventional distributed amplifiers, and substantially higher than other amplifiers of SFQ input signals. 
         [0025]      FIG. 3  schematically illustrates the device-level detail of the distributed amplifier of  FIG. 2 . More specifically,  FIG. 3  provides a detailed drawings of a distributed amplifier having an exemplary voltage source. The distributed amplifier of  FIG. 3  illustrates a 12 stage amplifier. For brevity, only stages  1 ,  2  and  12  are shown. In  FIG. 3 , bias  354  is connected to resistor  353  and a lumped LC circuit comprising inductor  351  and capacitor  352 . 
         [0026]    Voltage sources  301 ,  302  . . .  312  include two Josephson junctions arranged in a superconducting-quantum-interference-device (“SQUID”). Each voltage source is set and reset through inductive coupling with transmission lines  330  and  340 . SQUID  312  comprises Josephson junctions  315  and  316 , as well as inductor  313  and shunt resistor  314 . The shunt resistor in each SQUID (applied asymmetrically to the right junction, as shown) enforces the out-of-phase voltage mode required to reset the circuit. During operation, inductor  360  is energized by an SFQ Pulse from Set/Reset gates  332 / 342 . The inductive coupling energizes inductor  313  of SQUID  312 . Shunt resistor  314  provides out-of-phase voltage mode which enables resetting SQUID circuit  312 . The application of shunt resistor  314  with SQUID  312  is exemplary and non-limiting. Other circuit configurations which enable resetting of the SQUID circuit can be used without departing from the principles disclosed herein. 
         [0027]    Similar to  FIG. 2 , transmission lines  330  and  340  comprise JTLs  333 ,  335 ,  345  and  343  (additional JTLs are omitted for brevity). In addition, each voltage source is serially connected to a resonant circuit including an inductor and a capacitor. Thus, voltage source  312  is connected to inductor  321  and capacitor  322 , which cumulatively form resonant circuit (interchangeably, lumped LC circuit)  323 . 
         [0028]    In one embodiment of the disclosure, the active Josephson transmission delay on the input is matched to lumped LC transmission line delay on the output. Thus, transmission delay through JTL  335  can be matched to transmission delay of lumped LC circuit  323 . In another embodiment, transmission delay through JTL  345  can be matched to transmission delay of lumped LC circuit  323 . In still another embodiment, each of JTLs  335 ,  345  is selected to have a transmission line delay matching that of lumped circuit  323 . In still another embodiment, lump circuit  323  has a characteristic delay matching transmission line delay through JTL  333  or  343 . 
         [0029]    Each voltage source shown in  FIG. 3  was externally loaded by  355  and  353  according to the following Equation: 
         [0000]      (50 Ω+50 Ω)/12=8 Ω  (1) 
         [0030]    In one embodiment of  FIG. 3 , shunt resistor  314  is selected to be smaller than the value of Equation 1. That is, shunt resistor  314  can be selected to be smaller than 8 Ω. 
         [0031]      FIG. 4  schematically illustrates a distributed amplifier according to another embodiment of the disclosure. Circuit  400  of  FIG. 4  comprises bias  454  connected in parallel with resistor  453 . In an exemplary implementation of circuit  400 , resistor  453  was selected as 50 Ω resistor. As with  FIGS. 2 and 3 , the embodiment of  FIG. 4  comprises of 12 voltage sources corresponding to 12 amplification stages. For brevity, only the first, second and twelfth voltage sources are shown. 
         [0032]    In  FIG. 4 , set/reset signal  432  is provided to transmission line  430 . The set and reset signals have opposite polarity so that the reset pulse annihilates the signal generated by the set pulse. The set and reset pulse can each define an SFQ signal. Thus, the set and reset pulses  432  are applied to transmission line  430  input. Propagation of signals of opposite polarity requires AC power source on the JTL instead of DC power as shown in  FIG. 4 . 
         [0033]    Transmission line  430  comprises a plurality of JTLs, with each JTL matched to an amplification stage such that a circuit with n amplification stages has n−1 JTLs. As discussed, each JTL has a characteristic delay associated therewith. 
         [0034]    In contrasts with circuits of  FIGS. 2 and 3 , each voltage source of circuit  400  communicates with only one transmission line (transmission line  430 ). Thus, voltage sources  401 ,  402  and  412  are connected to transmission line  432  and are grounded through lines  470 ,  471  and  478  respectively. Because the set and reset signals can be SFQ signals of opposite polarity, circuit  400  can be directly connected to “flux-powered signal-flux-quantum circuits,” as described in patent filing XXX for signal amplification and readout. 
         [0035]    As with flux-powered single-flux-quantum logic gates, such an amplifier configuration can avoid static power dissipation in the JTL by elimination of the associated bias resistors. 
         [0036]    Inductor  451  and capacitor  452  complete circuit  400  by forming a resonant circuit which communicates with voltage source  412 . In one exemplary embodiment, resistor  455  was matched to resistor  453  and each was provided a 50 Ω resistance. 
         [0037]    While the principles of the disclosure have been illustrated in relation to the exemplary embodiments shown herein, the principles of the disclosure are not limited thereto and include any modification, variation or permutation thereof.