Abstract:
A segmented digital-to-analog converter (DAC) is disclosed. In the present invention, the segmented DAC of the present invention comprises a signal component processing stage and a plurality of noise component processing stages cascaded with the signal component processing stage. A noise component of an input word for the DAC is split into a plurality of portions to be processed. By doing so, effect due to gain mismatch(es) in an analog portion of the DAC can be effectively reduced without significantly increasing DAC cells used in the DAC.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention relates to a digital-to-analog converter (DAC), more particularly, to a nose-shaped segmented DAC. 
     BACKGROUND OF THE INVENTION 
     Digital-to-analog converters (DACs) are widely used in various fields. Among different types of DACs, a sigma-delta, or noise shaped DAC is applied to widespread use. To reduce the required number of analog elements used in the DAC, a plurality of sub-DACs are used rather than a signal DAC with 2 N  levels. That is, a segmented DAC is used. The DAC converts N binary-weighted bits into M equally-weighted bits, where M=2 N . 
       FIG. 1  is a block diagram schematically showing a prior art segmented DAC  10 . As shown, an input word Xin of 20 bits is quantized by a digital modulator  12  into a low-bit word Xm. In this example, the digital modulator  10  is implemented by a 6-bit sigma-delta modulator, so that the input word Xin is modulated into a 6-bit word Xm. The 6-bit word Xm is split into three most significant bits (MSBs) and three least significant bits (LSBs). The three LSBs are converted into eight equally-weighted bits by a thermometer encoder  21  and randomly scrambled by a scrambler  25 . The three MSBs are converted into eight equally-weighted bits by a thermometer encoder  31  and the equally-weighted bits are randomly scrambled into scrambled bits by a scrambler  35 . Since one MSB bit is equivalent to 8 times of one LSB bit, the MSBs and LSBs are respectively converted by a DAC  29  (8×) and a DAC  39  (1×). That is, a bit weight ratio of the outputs of the DAC  29  and DAC  39  is 8:1. Then the outputs of the DAC  29  and the DAC  39  are summed by a summing unit  40 . Ideally, the output of the summing unit  40  should be an analog value that equals to the 6-bit digital word Xm. 
     However, since the outputs of the DAC  29  and DAC  39  are summed in an analog manner, errors resulting from gain mismatch between the DAC  29  and the DAC  39  cause in-band noise and distortion. Therefore, an in-band signal-to-noise ratio (SNR) and total-harmonic-distortion (THD) of the DAC will be degraded. 
     SUMMARY OF THE INVENTION 
     The present invention is to provide a segmented digital-to-analog converter (DAC), in which effect due to gain mismatch(es) in an analog portion of the DAC can be effectively reduced without significantly increasing analog elements (i.e. DAC cells) used in the DAC. 
     The segmented DAC of the present invention comprises a signal component processing stage and a plurality of noise component processing stages cascaded with the signal component processing stage. The signal component processing stage is a preceding stage with respect to the first one of the noise component processing stages. The signal component processing stage has a digital modulator for generating a signal word (Xm) in response to an input word (Xin) and a DAC unit for converting the signal word to generate an analog value. Each noise component processing stage comprises a digital modulator for generating a noise word (Rm) in response to a residue word (R) obtained by subtracting an output of the digital modulator of the preceding stage from an input of a preceding stage, and a DAC unit for converting the noise word to generate an analog value, while the last one of the noise component processing stages further comprises another DAC unit for converting a residue obtained by subtracting an output of the digital modulator of the preceding stage from an input of the preceding stage to generate an analog value. The segmented DAC further has a summing unit for summing all the analog values to generate an output analog value. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be described in detail in conjunction with the appending drawings, in which: 
         FIG. 1  is a block diagram schematically showing a prior art segmented DAC; 
         FIG. 2  is a block diagram schematically showing a segmented DAC in accordance with a first embodiment of the present invention; and 
         FIG. 3  is a block diagram schematically showing a segmented DAC in accordance with a second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  is a block diagram schematically showing a segmented DAC  100  in accordance with a first embodiment of the present invention. In the present embodiment, a 10-bit segmented DAC  100  is described as an example. A 10-bit input word Xin is passed through a first digital modulator  102  to be noise shaped. The first digital modulator  102  quantizes the input word Xin into a 4-bit noise shaped word Xm, which is referred to as a signal word or a first word, by using M 1   th  order noise transfer function (NTF). The 4-bit signal word Xm includes a signal component S and a noise N 1  due to the first digital modulator  102 . That is, the signal word Xm includes S and N 1 . Then the 4-bit signal word Xm is subtracted from the input word Xin (i.e. Xin−Xm) by a summing unit  110  to obtain a first residue word (or simply referred to as “first residue”) R 1 . The first residue R 1  will have a length of 7 bits. That is, the 10-bit input word Xin is split into a 4-bit signal word Xm and a 7-bit residue R 1  with one bit overlapped. The first residue R 1  comprises an inverse of the noise N 1  generated by the first digital modulator  102 . That is, the first residue R 1  comprises  N 1   . 
     The 7-bit first residue R 1  is further processed by a second digital modulator  112  to be quantized into a 4-bit noise shaped output Rm 1 , which is referred to as a noise word or a second word. The second digital modulator  112  quantizes the 7-bit first residue R 1  into the 4-bit noise word Rm 1  by using M 2   th  order NTF. Preferably, M 1  is greater than M 2  since the signal component is processed by the first digital modulator  102 . However, the relationship between M 1  and M 2  is not limited to this. It is possible that M 1 =M 2  or M 1 &lt;M 2 . As can be known, the output Rm 1  of the second digital modulator  112  comprises the inversed noise  N 1    and a noise N 2  generated by the second digital modulator  112 . That is, the noise word Rm 1  comprises  N 1    and N 2 . The output Rm 1  of the second digital modulator  112  is subtracted from the first residue R 1  (i.e. R 1 −Rm 1 ) by a summing unit  115  to obtain a second residue R 2  of a length of 4 bits. That is, the 7-bit first residue R 1  is further split into the 4-bit noise word Rm 1  and the 4-bit second residue R 2  with one bit overlapped. As can be seen, the second residue R 2  comprises an inverse of the noise N 2  of the second digital modulator  112 . That is, the second residue R 2  comprises  N 2   . 
     In this architecture, the 10 bit input word Xin is split into the 4-bit signal word Xm, the 4-bit noise word Rm 1  and the 4-bit residue word R 2  by three paths  120 ,  130  and  140 . The 4-bit signal word Xm is processed by a thermometer encoder  121  and a scrambler  125  to be converted into 16 equally-weighted bits. The 4-bit noise word Rm 1  is processed by a thermometer encoder  131  and a scrambler  135  to be converted into 16 equally-weighted and scrambled bits. The 4-bit residue word R 2  is processed by a thermometer encoder  141  and a scrambler  145  to be converted into 16 equally-weighted bits. Then the above mentioned 16-bit words are respectively processed by DACs  129  (1×),  139  (8×) and  149  (64×) to generate corresponding analog values. For the DAC  129 , the word length is quantized from 10-bit to 4-bit, so a 64× DAC is used. For the DAC  139 , the word length is quantized from 7-bit to 4-bit, so an 8× DAC is used. For the DAC  149 , a 1× DAC is used. 
     Each of the DACs  129 ,  139  and  149  is a 16-cell DAC since the word length is 16 bits. That is, each of the DACs  129 ,  139  and  149  comprises 16 DAC cells such as current sources or other analog elements. The DAC  100  only uses 48 (=16+16+16) DAC cells (e.g. current sources), which are analog elements, in all. It should be noted that when the bit numbers of signal word (such as Xm), the noise word (such as Rm 1 ), and the second residue (R 2 ) are more even, the amount of the DAC cell can be further reduced. 
     The output analog values of the three DACs  129 ,  139  and  149  are summed by a summing unit  160  to generate an analog output Yout. The gain mismatch between the DAC  129  and the DAC  139  is shaped by the M 1   th  order NTF of the first digital modulator  102 , and the gain mismatch between the DAC  139  and the DAC  149  is shaped by the M 2   th  order NTF of the second digital modulator  112 . Therefore, the impact on the in-band signal due to the gain mismatch can be reduced to the minimum. 
     If downlink current-steering DACs are used as the DACs  129 ,  139 ,  149  of such an architecture, assumed that an oversampling ratio (OSR) is 16, M 1 =M 2 =1, and the DAC ratio of the DACs  129 ,  139 ,  149  is adjusted as 1:7:49 on purpose for 1× DAC:8× DAC:64× DAC, we found performance of the DAC  100  is qualified in 1.92 MHz bandwidth by behavior simulation. The segmented DAC in accordance with the present invention has a great tolerance for gain mismatch. 
     As shown and described, the DAC  100  of the first embodiment includes three cascading stages with two digital modulators  102  and  112 . In the first stage, the signal component is processed, and the noise component is further split into two portions to be respectively processed by the second and third stages. The first stage dealing with the signal component can be deemed as a preceding stage of the second stage dealing with the noise component. Thus, the first stage can be referred to as a signal component processing stage, while the second and third stages can be referred to as noise component processing stages. However, it is possible to use more stages to deal with the noise component so that the required number of the DAC cells can be further reduced. 
       FIG. 3  is a block diagram schematically showing a segmented DAC  200  in accordance with a second embodiment of the present invention. The architecture of the DAC  200  comprises four cascading stages. In the present example, a 10-bit word is split into 3 bits, 3 bits, 3 bits and 4 bits. 
     In the present embodiment, a 10-bit segmented DAC  200  is described as an example. A 10-bit input word Xin is passed through a first digital modulator  202 . The first digital modulator  202  quantizes the input word Xin into a 3-bit word Xm, which is referred to as a signal word by using M 1   th  order noise transfer function (NTF). The 3-bit signal word Xm includes a signal component S and a noise N 1  due to the first digital modulator  202 . That is, the signal word Xm includes S and N 1 . Then the 3-bit signal word Xm is subtracted from Xin (i.e. Xin−Xm) by a summing unit  210  to obtain a first residue R 1 . The first residue R 1  will have a length of 8 bits. That is, the 10-bit input word Xin is split into a 3-bit signal word Xm and an 8-bit residue R 1  with one bit overlapped. The first residue R 1  comprises an inverse of the noise N 1  generated by the first digital modulator  202 . That is, R 1  comprises  N 1   . 
     The 8-bit first residue R 1  is further processed by a second digital modulator  212  to be quantized into a 3-bit output Rm 1 , which is referred to a noise word. The second digital modulator  212  quantizes the 8-bit first residue R 1  into the 3-bit noise word Rm 1  by using M 2   th  order NTF. Preferably, M 1  is greater than M 2  since the signal component is process by the first digital modulator  202 . However, the relationship between M 1  and M 2  is not limited to this. It is possible that M 1 =M 2  or M 1 &lt;M 2 . As can be known, the output Rm 1  of the second digital modulator  212  comprises the inversed noise  N 1    and a noise N 2  generated by the second digital modulator  212 . That is, the noise word Rm 1  comprises  N 1    and N 2 . The output Rm 1  of the second digital modulator  212  is subtracted from the first residue R 1  (i.e. R 1 −Rm 1 ) by a summing unit  214  to obtain a second residue R 2  of a length of 6 bits. That is, the 8-bit first residue R 1  is further split into the 3-bit noise word Rm 1  and the 6-bit second residue R 2  with one bit overlapped. As can be seen, the second residue R 2  comprises an inverse of the noise N 2  of the second digital modulator  212 . That is, the second residue R 2  comprises  N 2   . 
     The 6-bit second residue R 2  is further processed by a third digital modulator  222  to be quantized into a 3-bit output Rm 2 . The third digital modulator  222  quantizes the 6-bit second residue R 2  into the 3-bit noise word Rm 2  by using M 3   th  order NTF. Preferably, M 1  is greater than M 3  since the signal component is process by the first digital modulator  202 . However, the relationship between M 1  and M 3  is not limited to this. It is possible that M 1 =M 3  or M 1 &lt;M 3 . As can be known, the output Rm 2  of the third digital modulator  222  comprises the inversed noise  N 2    and a noise N 3  generated by the third digital modulator  222 . That is, the noise word Rm 2  comprises  N 2    and N 3 . The output Rm 2  of the third digital modulator  222  is subtracted from the second residue R 2  (i.e. R 2 −Rm 2 ) by a summing unit  218  to obtain a third residue R 3  of a length of 4 bits. That is, the 6-bit second residue R 2  is further split into the 3-bit noise word Rm 2  and the 4-bit second residue R 3  with one bit overlapped. As can be seen, the third residue R 3  comprises an inverse of the noise N 3  of the third digital modulator  222 . That is, the third residue R 3  comprises  N 3   . 
     In this architecture, the 10 bit input word is split into the 3-bit signal word Xm, the 3-bit noise word Rm 1 , the 3-bit noise word Rm 2  and the 4-bit residue word R 3  by four paths  220 ,  230 ,  240  and  250 . The 3-bit signal word Xm is processed by a thermometer encoder  221  and a scrambler  225  to be converted into 8 equally-weighted bits. The 3-bit noise word Rm 1  is processed by a thermometer encoder  231  and a scrambler  235  to be converted into 8 equally-weighted bits. The 3-bit noise word Rm 2  is processed by a thermometer encoder  241  and a scrambler  245  to be converted into 8 equally-weighted bits. The 4-bit residue word R 3  is processed by a thermometer encoder  251  and a scrambler  255  to be converted into 16 equally-weighted bits. Then the above mentioned words are respectively processed by DACs  229  (1×),  239  (8×),  249  (32×) and  259  (128×) to generate corresponding analog values. For the DAC  229 , the word length is quantized from 10-bit to 3-bit, so a 128× DAC is used. For the DAC  239 , the word length is quantized from 8-bit to 3-bit, so a 32× DAC is used. For the DAC  249 , the word length is quantized from 6-bit to 3-bit, so an 8× DAC is used. For the DAC  259 , a 1× DAC is used. 
     Each of the DACs  229 ,  239  and  249  is an 8-cell DAC since the word length is 8 bits. The DAC  259  is a 16-cell DAC since the word length is 16 bits. That is, each of the DACs  229 ,  239  and  249  comprises 8 DAC cells while the DAC  259  comprises 16 DAC cells such as current sources or other analog elements. The DAC  200  only uses 40 (=8+8+8+16) DAC cells in all. 
     The output analog values of the DACs  229 ,  239 ,  249  and  259  are summed by a summing unit  260  to generate an analog output Yout. The gain mismatch between the DAC  229  and the DAC  239  is noise shaped by the M 1   th  order NTF of the first digital modulator  202 , the gain mismatch between the DAC  239  and the DAC  249  is shaped by the M 2   th  order NTF of the second digital modulator  212 , and the gain mismatch between the DAC  249  and the DAC  259  is shaped by the M 3   th  order NTF of the third digital modulator  222 . Therefore, the impact on the in-band signal due to the gain mismatch can be significantly reduced. 
     While the preferred embodiments of the present invention have been illustrated and described in detail, various modifications and alterations can be made by persons skilled in this art. The embodiment of the present invention is therefore described in an illustrative but not restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications and alterations which maintain the spirit and realm of the present invention are within the scope as defined in the appended claims.