Abstract:
A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This is a divisional of application Ser. No. 11/048,845, filed Feb. 3, 2005, which is incorporated herein by reference in its entirety. 

   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor device and to a method of fabricating the same. More specifically, the present invention is directed to a semiconductor device having a non-volatile memory cell and to a method of fabricating the same. 
   2. Description of the Related Art 
   Non-volatile memory cells continuously hold their stored data even when their power supplies are interrupted. Typically, a non-volatile memory cell has a gate stack structure. Specifically, a non-volatile memory cell has a gate stack and a source/drain formed at opposite sides of the gate stack. The gate stack includes a gate insulation layer, a floating gate, an intergate dielectric, and a control gate which are sequentially stacked on a substrate. Charges are introduced to the floating gate through a tunnel insulation layer to be stored therein. The stored charges set a threshold voltage of the cell. A non-volatile memory cell stores data using the cell threshold voltage. 
   The fabricating a non-volatile memory device includes a photolithographic process following the formation of the intergate dielectric. Specifically, the photolithographic process is carried out to form the control gate on the intergate dielectric. In this case, the intergate dielectric may be damaged during the photolithographic process. Also, the intergate dielectric may be additionally damaged during a subsequent process in which a spacer is formed. Damage to the intergate dielectric degrades the reliability of the non-volatile memory device because if charges stored in the floating gate migrate through the damaged intergate dielectric during operation of the cell, the threshold voltage of the cell fluctuates. Hence, the data stored in the cell is altered. 
   Also, it might be desirable to produce a semiconductor device in which a logic transistor is integrated with the non-volatile memory cell. Conventionally, logic transistors may include a silicide layer to enhance the operating speed thereof. However, a silicide layer can not withstand the high program voltage of a non-volatile memory cell. 
   SUMMARY OF THE INVENTION 
   An object of the present invention is to provide a semiconductor device that includes a highly reliable non-volatile memory cell. 
   Another object of the present invention is to provide a semiconductor device that includes both a non-volatile memory cell and a logic transistor which can operate at a high speed. 
   According to one aspect of the present invention, a method of fabricating a semiconductor device includes (a) preparing a substrate including a first area where a logic transistor is to be formed and a second area where a non-volatile memory cell is to be formed, and (b) forming a logic transistor and a non-volatile memory cell at the first and second areas, respectively, 
   wherein the forming of the non-volatile memory cell includes forming an insulation layer as an outermost portion of the non-volatile memory cell to enhance the charge retention capability of the cell, and the forming of the logic transistor includes selectively forming a silicide layer at the first area of the substrate. 
   The non-volatile memory cell and the logic transistor may be formed by forming a first gate insulation layer and a second gate insulation on the first and second areas of the substrate, respectively, forming a first (floating) gate and an intergate dielectric on the first gate insulation layer, and forming a second gate on the first gate insulation layer and a second (control) gate on the intergate dielectric. The silicide layer is formed on the substrate adjacent opposite sides of the gate formed at the first area of the substrate and on the gate itself at the first area. The insulation layer covers the gate structure and the substrate at the second area to prevent the formation of a silicide layer at the second area and to enhance the function of the intergate dielectric. 
   The silicide layer may be formed by forming a metal layer over the entire surface of the substrate and performing a silicide heat-treating process. A silicide layer is not formed at the second area, i.e., the area where the non-volatile memory cell is formed, because the insulation layer covers the second area. On the other hand, the gate at the first area, and the silicon exposed adjacent opposite sides of the gate, react with the metal layer to form a silicide layer at the first area, i.e., the area where the logic transistor is formed. 
   According to another aspect of the present invention, an I/O transistor is formed at a third area of the substrate. In this case, the gate insulation layer is also formed at the third area of the substrate, and a gate of the I/O transistor is formed on the third area of the substrate. Preferably, the gate of the I/O transistor is formed at the time the gate of the logic transistor is formed on the second area of the substrate, and the (control) gate of the non-volatile memory cell is formed on the integrate dielectric at the third area of the substrate. In this case, the insulation layer is formed over the second and third areas of the substrate. 
   According to yet another aspect of the present invention, the present invention provides a semiconductor device including a first gate formed on a gate insulation at an upper portion of a substrate, an intergate dielectric disposed on the first gate, a second gate overlying only a portion of the intergate dielectric such that another portion of the first gate is left exposed by the second gate, and an insulation layer extending over at least that portion of the intergate dielectric left exposed by the second gate. Accordingly, the insulation layer protects the integrate dielectric and enhances the function thereof. 
   According to another aspect of the present invention, the insulation layer may include an oxide or silicon oxynitride. Preferably, the enhancing insulation layer is a multi-layered film including both an oxide and a nitride. For example, the enhancing insulation layer may be an oxide-silicon oxynitride-silicon nitride film, a silicon-silicon oxynitride-oxide film, an oxide-silicon nitride-silicon oxynitride-silicon nitride film, or an oxide-silicon nitride-oxide film. The aforementioned materials appear stacked in the films in the order named. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a plan view of a semiconductor device according to the present invention. 
       FIG. 2  through  FIG. 7  are cross-sectional views of a substrate, corresponding to cross-sectional views taken along lines I-I′, II-II′, and III-III′ in  FIG. 1 , and illustrating a method of fabricating a semiconductor device according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Also, like numbers refer to like elements throughout the specification. Still further, when a layer is referred to as being “on” or “over” another layer or substrate, such a description may refer to either the layer in question being disposed directly on the other layer or substrate or may refer to intervening layers being present therebetween. 
   Referring to  FIG. 1 , a semiconductor device according to the present invention includes a logic transistor  180   a , an input/output transistor (hereinafter referred to as “I/O transistor”)  180   b , and a non-volatile memory cell  180   c . In  FIG. 1 , characters ‘a’, ‘b’, and ‘c’ denote a logic transistor forming area in which the logic transistor is formed, an input/output transistor forming area (hereinafter referred to as “I/O transistor forming area”) in which the I/O transistor is formed, and a memory cell forming area in which the non-volatile memory cell is formed, respectively. 
   Also, in  FIG. 1 , reference numerals  100   a - 100   c  denote active regions, reference numeral  120  denotes a floating gate of the non-volatile memory cell  180   c , reference numeral  130  denotes an intergate dielectric of the non-volatile memory cell  180   c , reference numeral  150   c  denotes a control gate of the non-volatile memory cell  180   c , reference numeral  150   a  denotes a gate of the logic transistor  180   a , reference numeral  150   b  denotes a gate of the I/O transistor  180   b , and reference numerals  110 Sa- 110 Sc and  110 Da- 110 Dc denote source/drain regions formed at opposite sides (active regions) of the gates  150   a ,  150   b  and  120 . Although not shown in this figure, a gate insulation layer is disposed between the gates  150   a ,  150   b ,  120  and a substrate. 
   The logic transistor  180   a  also has silicide layers  170 S/ 170 D and  170 G on the source/drain region  110 Sa/ 100 Da and the gate  150   a . The control gate  150   c  of the non-volatile memory cell  180   c  is smaller than the floating gate  120  so as to provide a high coupling ratio and margin for the photolithographic process used to produce the gates. The control gate  150   c  overlies the floating gate  120  outside the active region  100   c . Also, the non-volatile memory cell  180   c  includes an insulation layer for enhancing the charge retention of the intergate dielectric  130  (not shown in this figure). The insulation layer is formed at least on an intergate dielectric exposed by the control gate  150   c.    
   A method of fabricating the semiconductor device shown in  FIG. 1  will now be described with reference to  FIG. 2  through  FIG. 7 . 
   As illustrated in  FIG. 2 , a substrate  200 , which includes a logic transistor forming area ‘a’, an I/O transistor forming area ‘b’, and a non-volatile memory cell forming area ‘c’, is prepared. Next, a conventional device isolation process is carried out to form a device isolation layer  202 . Regions surrounded by the device isolation layer  202  become the active regions. Gate insulation layers  204   a - 204   c  are formed on the substrate  200  in the active regions using conventional techniques. The gate insulation layers  204   a - 204   c  have thicknesses that are suited to the characteristics required of the device. A floating gate  206  and an intergate dielectric  208  are sequentially formed on the gate insulation layer  204   c  at the memory cell forming area ‘c’. Specifically, a gate layer made of, for example, polysilicon, and then a multi-layered film are formed over the entire surface of the substrate. The multi-layered film is an oxide-nitride-oxide (ONO) film. The multi-layered film and gate layer are then patterned using a photolithographic process to form the gate  206  and intergate dielectric  208  at the memory cell forming area ‘c’. Subsequently, an ion implanting process is carried out to form an impurity diffusion region, e.g., source/drain regions, at opposite sides of the floating gate  206 . 
   As illustrated in  FIG. 3 , a second gate layer  210  is formed over the entire surface of the substrate  200 . The second gate layer  210  is made of, for example, polysilicon. 
   As illustrated in  FIG. 4 , a photolithographic process is carried out to form a logic gate  212   a , an I/O gate  212   b , and a control gate  212   c  at the logic transistor forming area ‘a’, I/O transistor forming area ‘b’, and memory cell forming area ‘c’, respectively. The control gate  212   c  is smaller than the floating gate  206 . An ion implanting process is carried out to form impurity diffusion regions at opposite sides of the logic gate  212   a  in the logic transistor forming area ‘a’, and at opposite sides of the I/O gate  212   b  in the I/O transistor forming area ‘b’. The memory cell area ‘c’ is covered with a mask during this process. 
   Next, a spacer insulation layer is formed over the entire surface of the substrate  200 . An etch-back process is then carried out to form spacers  214   a  and  214   b  on sidewalls of the logic gate  212   a  and I/O gate  212   b , and to form spacers  214   c   1  and  214   c   2  on sidewalls of the floating gate  206  and control gate  212   c . The sidewall spacers may be made of, for example, a nitride or oxide. Although an upper oxide layer of the intergate dielectric  208  is etched, the insulation layer mitigates the etching of the oxide, as will be described later. 
   As illustrated in  FIG. 5 , an insulation layer  216  is formed on the substrate  200  over the I/O transistor forming area ‘b’ and the memory cell forming area ‘c’. More specifically, an insulation layer is first formed over the entire surface of the substrate  200 , and then a photolithographic process is carried out to remove the insulation layer from the logic transistor forming area ‘a’ while leaving the remainder of the insulation layer in the I/O transistor forming area ‘b’ and the memory cell forming area ‘c’. 
   The insulation layer  216  comprises an oxide or a nitride. Also, the insulation layer  216  may be a multi-layered film comprising, for example, oxide  216   a , oxynitride  216   b , and oxide  216  layers that are stacked in the foregoing order. Alternatively, the insulating layer  216  may be a multi-layered film comprising oxide-silicon nitride-silicon oxynitride-silicon nitride and oxide-silicon nitride-oxide layers that are stacked in the foregoing order. In the case in which the insulation layer  214  is a multi-layered film, its lowest layer preferably comprises an oxide. 
   As illustrated in  FIG. 6 , a metal layer  218  is formed over the entire surface of the substrate  200 . The metal layer  218  may be of a material which can react with silicon to form a silicide, i.e., a material having a low resistivity. The metal layer  216  may comprise a material having a high fusion point such as cobalt, nickel, or titanium. The metal layer  218  does not contact the substrate  200  or gates at the I/O transistor forming area ‘b’ and the memory cell forming area ‘c’ because the areas ‘b’ and ‘c’ are covered with the insulation layer  216 . 
   As illustrated in  FIG. 7 , a silicide heat-treating process is carried out to form silicide layers  220 S,  220 D, and  220 G at the logic transistor forming area ‘a’. That is, a silicide layer is selectively formed on an impurity diffusion region and a gate. Subsequently, the non-reacted metal layer is removed from the I/O transistor forming area ‘b’ and the memory cell forming area ‘c’. 
   According to the present invention as described above, an insulation layer enhances the charge retention capability of the memory cell. Furthermore, a silicide layer is selectively formed at the logic transistor to enhance the operating speed of the logic transistor. Such a silicide layer, though, is not durable to the high program voltage of a non-volatile memory cell. However, according to the present invention, the insulation layer prevents the forming of a silicide layer on the control gate of the memory cell. Therefore, a highly integrated semiconductor device having a reliable memory cell can be fabricated by performing a relatively simple process. 
   Finally, although the present invention been described above with reference to the preferred embodiments thereof, it is to be understood that the present invention is not limited to those precise embodiments. Rather, various changes and modifications may be made to those embodiments by one of ordinary skill in the art without departing from the true scope or spirit of the invention as defined by the appended claims.