Abstract:
A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure. In response to detecting the failure of the first clock source, the switching logic is configured to cause the input clock signal from a second clock source to be provided to the phase detector. This configuration may advantageously maintain lock in the PLL circuit while switching between clock sources for the input clock signal. The phase detector may further include a pulse width limiting circuit. The pulse width limiting circuit is configured to shorten each phase error output signal by a predetermined amount.

Description:
This application is a continuation application of U.S. patent application Ser. No. 09/236,865, filed Jan. 25, 1999 now U.S. Pat. No. 6,359,945. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to phase-locked loop (PLL) circuits, and, more particularly, to a PLL that is configured to fail-over from one input clock signal to another input clock signal without losing lock. 
     DESCRIPTION OF THE RELATED ART 
     The need to generate a local signal which is synchronized with an external reference signal is critical in many electronics applications such as frequency synthesis, clock recovery, clock generation and frequency demodulation. This coherence between the reference signal and the local replica is referred to as “phase synchronization”. This implies either that local signal is typically either in phase with the external reference signal or is offset from the reference signal by some phase constant. 
     At the heart of any such synchronization circuit is some form of a phase locked loop (PLL). Phase-locked loops are feedback control loops, whose controlled parameter is the phase of a locally generated replica of an incoming reference signal. Phase-locked loops have three basic components: a phase detector, a loop filter, and a voltage-controlled oscillator. 
     FIG.  1 —Basic PLL 
     A basic schematic diagram of a typical PLL  100  is presented in FIG.  1 . As shown, PLL  100  is configured to generate an output signal  120  in response to an input signal  112 . PLL  100  includes a phase detector  114 , a loop filter  116 , and a voltage-controlled oscillator (VCO)  118 . Phase detector  114  is coupled to receive input clock signal  112  and to produce output clock signal  120 . Phase detector  114  measures the phase difference between signals  112  and  120 , and generates a phase error signal  115 , which may be a voltage indicative of this phase difference. In some instances, phase detector  114  may also generate a signal even when there is no difference between signals  112  and  120 . As signals  112  and  120  change with respect to each other, signal  115  becomes a time-varying signal into loop filter  116 . This phase comparison is necessary to prevent output signal  120  from drifting with respect to reference signal  112 . As shown, the feedback signal  121  is an internal part of the PLL  100 . It is noted, as is shown below, that the feedback signal  121  may be a signal external to the PLL  100 . 
     Loop filter  116  governs the response of PLL  100  to the error detected between signals  112  and  120 . A well-designed loop filter  116  should be able to track changes in the incoming signal&#39;s phase but should not be overly responsive to signal noise. Loop filter  116  generates an error correction signal  117 , which is the input to VCO  118 . In one embodiment, a zero voltage on signal  117  causes the output of VCO  118 , output signal  120 , to oscillate at a predefined frequency, ω 0 , which is the “center” frequency of the oscillator. On the other hand, a positive voltage on error correction signal  117  causes output signal  120  to oscillate at a frequency which is greater than ω 0 . Conversely, a negative voltage on error correction signal  117  causes output signal  120  to oscillate at a frequency less than ω 0 . In another embodiment, described below, either a positive voltage or a negative voltage on error correction signal  117  is generated. In this embodiment, even when there is no difference between signals  112  and  120 , an error correction signal  117  is output. In still another embodiment, the error correction signal  117  is scaled such that although the error correction signal  117  is always of one sign, such as always positive, the error correction signal  117  corrects for oscillation either above or below the predefined frequency. 
     Generally speaking, in many embodiments, the output frequency of VCO  118  is a linear function of its input voltage over some range of input and output. “Phase lock” is achieved by feeding the output of VCO  118  back to phase detector  114  so that continual error correction may be performed. It is noted that PLL  100  may not achieve phase lock if reference signal  112  is outside of some predetermined range. 
     In its simplest form, loop filter  116  is simply a conductor; that is, phase error signal  115  is equal to error correction signal  117 . Such a filter  116  allows PLL  100  to generate an output signal  120  which matches reference signal  112  in frequency and phase only if reference signal  112  is equal to the center frequency of VCO  118 . If reference signal  112  oscillates at a different frequency from the center frequency of VCO  118 , output signal  120  may match reference signal  112  in frequency but not phase. This “wire filter” is an example of a first-order PLL, which means that the denominator of the loop filter transfer function has no exponent value greater than one. In another embodiment of a first-order PLL, loop filter  116  includes an amplifier. 
     FIG.  2 —PLL with Multiple Clock Inputs 
     Second-order PLLs, such as shown in FIG. 2, are more commonly used than first-order PLLs  100 . The second-order PLL  200 , as shown, also incorporates a mechanism for switching input clock signals between a first clock source  222 A and a second clock source  222 B. It is noted that the first clock source  222 A and the second clock source  222 B are preferably synchronized in frequency and in phase. The selection of the input clock signal from the first clock source  222 A or the second clock source  222 B may be made by a SEL_CLK input or by the switching logic  230 . Switching logic  230  receives CONTROL inputs and outputs STATUS information. The input clock signal is provided to a phase detector  214 . The phase detector outputs a phase error signal  215  as a combination of UP and/or DOWN pulses. These UP and DOWN pulses are typically digital signals indicative of the phase difference between the input clock signal and the feedback signal  221 . The UP pulse is indicative of a phase difference between the feedback signal  221  and the input clock signal when an edge of the feedback signal  221  occurs after a corresponding edge of the input clock signal. The DOWN pulse is indicative of a phase difference between the feedback signal  221  and the input clock signal when an edge of the feedback signal  221  occurs before a corresponding edge of the input clock signal. 
     One difference between the first-order PLL  100  and the second-order PLL  200  is that the second-order PLL has an integrating loop filter  216 . A second order loop filter  216  performs an integration function, such as that typically found in a low-pass filter. This functionality allows the second-order PLL  200  to generate an output signal  220  which matches reference signal  212  in phase and frequency when reference signal  222  is not identical to the center frequency of VCO  218 . This is possible since the second-order loop filter is configured to generate a non-zero error correction signal even when signals  222  and  220  match in phase. This non-zero error correction signal allows VCO  218  to oscillate at above or below its center frequency while remaining in phase with reference input clock signal  222 . 
     It is noted that third-order (and possibly higher-order) PLLs exist and are commonly used in circuits such as those used in cellular and satellite communications. Third-order PLLs include third-order loop filters configured to perform double integration, which allows frequency and phase synchronization to occur even with a Doppler shift between the reference clock signal and output signal. It is also noted that multipliers and/or dividers are also used to generate an output signal, which is different, such as in frequency or phase, than the reference input signal. 
     An important feature of the PLL  200  of FIG. 2 is the ability to switch between an input clock signal  222 A from a first clock source and the input clock signal  222 B from a second clock source. The switching logic  230  is configured to detect a failure of the input clock signal  222 A from the first clock source and to cause the input clock signal  222 B from the second clock source to be provided to phase detector  214  in the place of the input clock signal  222 A. 
     Although the switching logic  230  responds fairly quickly to the failure of the clock source, by the time the new clock source is switched in, the effects of the “bad” clock (or loss of clock) has propagated through the PLL  200  and has modified the feedback signal  221  such that the PLL  200  can no longer maintain the phase synchronization between the input clock signal and the feedback signal (i.e. the PLL  200  loses phase lock). What is needed is a PLL system and method of operation thereof that switches between the input clock signals from a first clock source and a second clock source without losing lock. 
     SUMMARY OF THE INVENTION 
     The problems outlined above are in large part solved by a phase locked loop (PLL) and controller that provide fail-over redundant clocking. The PLL switches between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a PLL circuit. In one embodiment, the phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing the input clock signal from a first clock source failure. The phase detector is coupled to receive an input clock signal from a first clock source and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL. The feedback signal is indicative of the output signal of the PLL. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure. In response to detecting the failure of the first clock source, the switching logic is configured to cause the input clock signal from a second clock source to be provided to the phase detector. Also in response to detecting the failure of the first clock source, the supplemental error correction signal is injected. This configuration may advantageously maintain lock in the PLL circuit while switching between clock sources for the input clock signal. 
     In a further embodiment, the phase detector further includes a pulse width limiting circuit. The pulse width limiting circuit is configured to shorten each phase error output signal by a predetermined amount. In one embodiment, the phase error signals are digital signals comprising an UP signal and a DOWN signal. The pulse widths of the UP and the DOWN signal are each shortened by the pulse width limiting circuit. In one embodiment, failure of the clock source is defined as an absence of three or more clock edges of the input clock signal. In another embodiment, the failure results in a maximum length DOWN pulse. In still another embodiment, the supplemental correction signal comprises a maximum length UP pulse. The shortened phase error output signal may advantageously result in slower PLL output drift upon the failure of the input clock signal. 
     A method is likewise contemplated for operating a PLL circuit. The method comprises, in one embodiment, detecting a phase difference between an input clock signal from a first clock source and a feedback signal. The method further outputs a phase error signal indicative of the phase difference. The phase error signal is converted into an error correction signal. The method produces oscillations in response to the error correction signal, with the feedback signal indicative of the oscillations. The method further monitors the input clock signal from the first clock source for a failure. In response to the failure, the method provides the input clock signal from a second clock source in place of the input clock signal from the first clock source. The method further outputs a supplemental correction signal in response to the failure. The method may advantageously maintain lock in the PLL circuit while switching between clock sources for the input clock signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: 
     FIG. 1 is a block diagram of a generalized prior art phase locked loop (PLL); 
     FIG. 2 is a block diagram of an embodiment of a prior art PLL including switching logic configured to switch between input clock signals; 
     FIG. 3 is a block diagram of a PLL with switching logic as well as a supplemental correction pulse generator and a pulse limiting circuit; 
     FIG. 4 is an embodiment of the switching logic of FIG. 3; 
     FIGS. 5A and 5B are block diagrams of embodiments of the phase detector of FIG. 3, which incorporate the supplemental correction pulse generator and the pulse limiting circuit; 
     FIGS. 6A and 6B are timing diagrams illustrating basic operation of the PLL of FIG. 3; and 
     FIG. 7 is a timing diagram of advanced operation of the PLL of FIG. 3, including switchover to a backup clock source, limited width phase error signal pulses, and a supplemental error correction pulse. 
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG.  3 —PLL with Switching Logic and Supplemental Error Correction 
     Turning to FIG. 3, a block diagram of a phase locked loop (PLL) circuit is illustrated. Preferably implemented as a monolithic integrated circuit, PLL  300  includes a first multiplexer coupled to receive a first input clock signal  322 A from a first clock source and a second input clock signal  322 B from a second clock source. The multiplexer is controlled by a signal from an OR block coupled to receive a select clock input SEL_CLK and the output of switching logic  330 . The select clock input sets the identity of the primary clock input. Switching logic  330  receives CONTROL inputs  332  and outputs STATUS outputs  331 . 
     The output of the input multiplexer is the input clock signal provided to the phase detector  314  and to an output multiplexer. The phase detector  314  receives the input clock signal  322  from the input multiplexer and a feedback signal  321  from a feedback multiplexer. The phase detector is configured to produce a phase error signal  315  indicative of the difference between the input clock signal and the feedback signal  321 . As shown, the phase error signal  315  comprises an UP pulse and a DOWN pulse, each preferably being digital signals. The UP pulse is indicative of a phase difference between the feedback signal  321  and the input clock signal  322  when an edge of the feedback signal  321  occurs after a corresponding edge of the input clock signal  322 . The DOWN pulse is indicative of a phase difference between the feedback signal  321  and the input clock signal  322  when an edge of the feedback signal  321  occurs before a corresponding edge of the input clock signal  322 . 
     A loop filter  316  is coupled to receive the phase error signal and to output an error correction signal to a voltage controller oscillator (VCO)  318 . In a preferred embodiment, the loop filter comprises an active low-pass filter configured as an integrator. The VCO  318  is coupled to receive the an error correction signal from the loop filter  316  and to produce oscillations indicative of the error correction signal. The oscillating signal is presented as a second input to the output multiplexer. A PLL enable signal PLL_EN is provided to either select the output of the VCO or the input clock signal  322  to output. In the illustrated embodiment, the output of the output multiplexer is divided in a divider circuit  319 , either by 2 or 4 as shown, to produce one or more PLL output signals  320  A/B. The feedback signals  321 A and  321 B are shown coupled to the output signals of the PLL  320 A/B. 
     FIG.  4 —Switching Logic 
     Turning now to FIG. 4, an embodiment of the switching logic  330  is illustrated. The input clock signals  322 A and  322 B are provided to the switching logic  330 . Also provided are CONTROL signals  332 , including an alarm reset ALARM_RESET  402  and a manual override MAN_OVERRIDE  404 . The switching logic  330  outputs STATUS signals  331 , including an indication of which input clock signal is selected CLK_SELECTED  408 , and an indication if either input clock has failed, INP 0 _BAD  406 A and INP 1 _BAD  406 B. The PLL  300  will use the second input clock  322 B upon the failure of the first input clock  322 A until the alarm reset signal  402  is received. The manual override operates to disable the switching logic  330 . 
     It is noted that in various embodiments, the switching logic  330  may also be configured to monitor the phase error signal  315  or other signals, as desired, in order to detect a failure of the input clock signal  322  or the feedback signal  321 . Likewise, additional CONTROL signals  332  and STATUS signals  331  are also contemplated. 
     FIGS.  5 A and  5 B—Phase Detectors  314 A and  314 B 
     Turning now to FIGS. 5A and 5B, embodiments of the phase detector  314  are illustrated. In FIG. 5A, the input clock signal  322  and the feedback signal  321  are provided to phase comparison logic  520  of phase detector  314 A. The phase comparison logic  520  provides a signal indicative of the phase difference between the input clock signal  322  and the feedback signal  321  to output logic  530 . The output logic  530  further receives the manual override signal MAN_OVERRIDE  404  and the failure notification signal INP#_BAD  406 . In a preferred embodiment, as shown, the output logic  530  includes a supplemental correction pulse generator  535  and a pulse width limiting circuit  537 . The output logic  530  provides the phase error signal  315  to the loop filter  316 . It is noted that in the embodiment illustrated in FIG. 5A, the phase error signal  315  comprises a digital UP signal and a digital DOWN signal. 
     In FIG. 5B, one specific embodiment of phase detector  314 B is shown. It is noted that a variety of circuits and components may be substituted for those shown, as suggested in FIG.  5 A. The input clock signal  322  and the feedback signal  321  are provided to the clock inputs of a pair of flip-flops  524 A and  524 B, respectively, which has the data input lines held HIGH. Upon the receipt of a respective clock edge, the flip-flops  524 A and  524 B each output a logical “1”. The output is maintained at logical “1”until both output lines are high. The output lines of the flip-flops  524 A and  524 B are combined by a logical AND, with the result provided to the RESET inputs of both flip-flops  524 A and  524 B. Thus, the flip-flops  524 A and  524 B reset when both flip-flops  524 A and  524 B output a logical “1”. The outputs of the flip-flops  524 A and  524 B are provided to logical ANDs on the output of the phase detector  314 B, both directly and through delay elements  512 A and  512 B, respectively. 
     The supplemental correction pulse generator  535  coupled in series on the UP side of the phase detector  314 B is configured to output a maximum UP pulse upon receiving notification of a failure of the input clock signal  322  from the present source. As shown, the supplemental correction pulse generator  535  also receives the manual override MAN_OVERRIDE signal  404  and the clock source failure notification signal(s) INP#_BAD  406 . In one embodiment, the supplemental correction pulse generator  535  includes a resettable one-shot. Other circuits capable of providing a pulse are also contemplated. 
     The output of the phase detector  314 B includes the phase error signal  315  comprising in this embodiment, a digital UP pulse and a digital DOWN pulse. The UP pulse results from the clock edge of the input clock signal  322  being provided to the phase detector  314 B ahead of the corresponding clock edge of the feedback signal  321 . Thus, flip-flop  524 A outputs a logical “1” before flip-flop  524 B outputs a logical “1”. The length of the UP pulse is limited by the pulse limitation of the delay  512 A. The minimum and maximum pulse width of the UP pulse may be predetermined by the length of time of the delay provided by delay element  512 A and by the reset time of the flip-flop  524 A, relative to the clock period of the input clock signal  322 . In a similar manner, the DOWN pulse results from the clock edge of the input clock signal  322  being provided to the phase detector  314 B after the corresponding clock edge of the feedback signal  321 . Thus, flip-flop  524 B outputs a logical “1” before flip-flop  524 A outputs a logical “1”. The length of the DOWN pulse is limited by the pulse limitation of the delay  512 B. The minimum and maximum pulse width of the DOWN pulse may be predetermined by the length of time of the delay provided by delay element  512 B and by the reset time of the flip-flop  524 B, relative to the clock period of the input clock signal  322 . 
     It is noted that in a preferred implementation of phase detector  314 B, at least a minimum UP pulse and a minimum DOWN pulse are generated for each rising edge of the input clock signal  322 . It is also noted that the supplemental correction pulse generator  535  may also be located in series with the DOWN pulse or in series with both the UP pulse and the DOWN pulse. For example, in an embodiment with the supplemental correction pulse generator  535  in series with the DOWN pulse, a runaway input clock signal  322  is determined to have failed. The supplemental correction pulse generator  535  is notified of the failure and generates a maximum pulse width DOWN pulse. 
     FIGS.  6 A and  6 B—Timing Diagrams 
     An example of the method of operation of the PLL  300  is illustrated in the timing diagrams of FIGS. 6A and 6B. It is contemplated that a variety of embodiments of PLL circuits may be designed to operate using the method disclosed herein. Broadly speaking, FIG. 6A illustrates the PLL  300  speeding up to match the input clock signal, while FIGS. 6B 6 A illustrates the PLL  300  slowing down to match the input clock signal. 
     The input clock signal  322 , used as a timing reference, and feedback signal  321  are compared to detect a phase difference. The phase difference is output as a pair of digital pulses UP  315 A and DOWN  315 B that are indicative of the phase difference. The phase difference signals UP  315 A and DOWN  315 B are converted into an error correction signal used to produce oscillations. The feedback signal  321  is indicative of the oscillations. In time period  620 , the rising edge of the input clock signal  322  is detected ahead of the corresponding rising edge of the feedback signal  321 . A relatively wide UP pulse  315 A and a minimum DOWN pulse  315 B are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . 
     The relatively wide UP pulse  315 A of time period  620  shortens the period of the feedback signal  321  such that the next rising edge of the feedback signal  321  is detected during time period  621  a shorter time after the corresponding rising edge of the input clock signal  322 . In time period  621 , a narrower UP pulse  315 A (relative to the UP pulse  315 A of time period  620 ) and a minimum DOWN pulse  315 B are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . The narrower UP pulse  315 A is wider than the minimum DOWN pulse  315 B. 
     The narrower UP pulse  315 A of time period  621  shortens the period of the feedback signal  321  such that the next rising edge of the feedback signal  321  is detected during time period  622  only a short period of time after the corresponding rising edge of the input clock signal  322 . In time period  622 , an even narrower UP pulse  315 A (relative to the UP pulse  315 A of time period  621 ) and a minimum DOWN pulse  315 B are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . The even narrower UP pulse  315 A is only slightly wider than the minimum DOWN pulse  315 B. 
     The effect of the even narrower UP pulse  315 A of time period  622  just shortens the period of the feedback signal  321  such that the next rising edge of the feedback signal  321  is detected during time period  623  substantially concurrently with the corresponding rising edge of the input clock signal  322 . In time period  623 , a minimum UP pulse  315 A and a minimum DOWN pulse  315 B are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . The minimum UP pulse  315 A is substantially the same width as the minimum DOWN pulse  315 B in a preferred embodiment. Other pulse width minimums are, however, contemplated. 
     In FIG. 6B, the input clock signal  322  is again used as a timing reference and is compared to feedback signal  321  to detect a phase difference. The phase difference is output as a pair of digital pulses UP  315 A and DOWN  315 B that are indicative of the phase difference. The phase difference signals UP  315 A and DOWN  315 B are converted into an error correction signal used to produce oscillations. The feedback signal  321  is indicative of the oscillations. In time period  670 , the rising edge of the input clock signal  322  is detected a substantial period of time after the corresponding rising edge of the feedback signal  321 . A relatively wide DOWN pulse  315 B and a minimum UP pulse  315 A are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . 
     The relatively wide DOWN pulse  315 B of time period  670  lengthens the period of the feedback signal  321  such that the next rising edge of the feedback signal  321  is detected during time period  671  only a short time before the corresponding rising edge of the input clock signal  322 . In time period  671 , a relatively narrow DOWN pulse  315 B (relative to the DOWN pulse  315 B of time period  670 ) and a minimum UP pulse  315 A are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . The relatively narrow DOWN pulse  315 B is wider than the minimum UP pulse  315 A. 
     The relatively narrow DOWN pulse  315 B of time period  671  shortens the period of the feedback signal  321  such that the next rising edge of the feedback signal  321  is detected during time period  672  slightly after the corresponding rising edge of the input clock signal  322 . In time period  672 , a relatively narrow UP pulse  315 A and a minimum DOWN pulse  315 B are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . The relatively narrow UP pulse  315 A is only slightly wider than the minimum DOWN pulse  315 B. 
     The effect of the relatively narrow UP pulse  315 A of time period  672  just shortens the period of the feedback signal  321  such that the next rising edge of the feedback signal  321  is detected during time period  672  substantially concurrently with the corresponding rising edge of the input clock signal  322 . In time period  672 , a minimum UP pulse  315 A and a minimum DOWN pulse  315 B are generated in response to the phase difference between the input clock signal  322  and the feedback signal  321 . The minimum UP pulse  315 A is substantially the same width as the minimum DOWN pulse  315 B in a preferred embodiment. Other pulse width minimums are, however, contemplated. 
     FIG.  7 —Timing Diagram with Clock Switchover 
     In FIG. 7, a timing diagram of several advanced operations of the PLL of FIG. 3, including switchover to a backup clock source, limited width phase error signal pulses, and a supplemental error correction pulse are illustrated. The first reference clock signal REF 1  is shown as input clock signal  322 A from a first clock source. The second reference clock signal REF 2  is shown as input clock signal  322 B from a second clock source. The feedback signal  321  and the input clock signal  322  are compared, as in FIGS. 6A and 6B, to produce a phase error signal. An UP pulse  315 A and a DOWN pulse  315 B are shown as comprising the phase error signal. 
     In time period  720 , the first input clock signal  322 A and the feedback signal  321  are in phase. A minimum width UP pulse  315 A and a minimum width DOWN pulse  315 B are shown. Note that the first input clock signal  322 A fails  780  during time period  780 . The first input clock signal  322 A is monitored for a failure. However, as shown, the failure may not be recognized until time period  721 , when three clock edges are missed  781 . 
     During clock period  721 , with no input clock signal  322 A being provided, the feedback signal  321  shows a longer period in response to the lack of an UP pulse  315 A and the extremely width DOWN pulse  315 B. Note that the pulse width of the DOWN pulse  315 B is limited to a predetermined maximum width  790 . The unlimited pulse width is shown as  791 . In addition, during clock period  721 , the input clock source failure is recognized and the input clock is switched over to a second input clock source  322 B in response. In addition, in response to the input clock failure, the supplemental error correction pulse  792  is injected as a maximum length UP pulse. 
     During clock period  722 , the backup input clock signal  322 B is now the reference clock signal. The supplemental error correction pulse  792  results in the feedback signal  321  having a shorter period than in clock period  721 , closer to the correct phase alignment with the reference clock signal that would occur without the supplemental error correction pulse  792 . Note that the missing UP pulse  315 A from clock period  721  may occur in clock period  722 . It is not seen in clock period  722  due to the supplemental error correction pulse  792 . In one embodiment, the supplemental error correction pulse  792  is in addition to the UP pulse  315 A. In another embodiment, the supplemental error correction pulse  792  replaces the UP pulse  315 A. 
     During clock periods  723  and  724 , the PLL circuit aligns the reference clock signal  322 B and the feedback signal  321  in a manner similar to that shown in FIGS. 6A and 6B. Note that in clock period  725 , the input clock signal  322 B and the feedback signal  321  are in phase. It is noted that a failure of a clock source may be defined as the loss of as few as one clock edge, either rising or falling. 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.