Abstract:
A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs.

Description:
BACKGROUND 
     This invention relates to a multi-level high-voltage ultrasound transmit pulser integrated circuit for medical ultrasound scanning image system, and more particularly, to an array of high voltage switches for a high-voltage output pulse generator for exciting the piezoelectric or capacitive-electrostatic elements in the ultrasound transducer probe in an ultrasound medical B-scan and a color image system. 
     Ultrasound medical imaging applications have a growing demand for more sophisticated excitation waveforms and sequential scanning methods for large number of piezoelectric or capacitive-electrostatic element arrays. The commonly used ultrasound transmit pulse generator generally consists of three or more pairs of P-type and N-type high voltage power MOSFETs driven by a very fast and powerful gate driver circuit. Each channel of the pulse generator needs to produce high voltage and high current to charge or discharge the load capacitance at ultrasound frequency or speed. The load capacitance of the piezoelectric or capacitive-electrostatic elements and the cable equivalent capacitance together usually are quite large, and the ultrasound frequency is in 1 to 20 MHz or higher frequency range. The transmitter pulser requires large output current; therefore it requires large MOSFET sizes. The advanced color Doppler ultrasound imaging systems further require that the waveform generated from this pulse generator contain multiple voltage-levels, in clouding the zero-level or near zero voltage levels. Further each IC has to built-in multiple channels of pulse generators. For examples, the dual, quad, octal-channel, even 16 or 32 channels need to be built-in one IC package. 
     Therefore, it would be desirable to provide a system and method that overcomes the above issues. It would further be desirable to provide a high-voltage transmit pulse generating circuit topology and method that uses the lower-voltage, low-cost but high-current, higher-speed large scale integrating semiconductor process. 
     SUMMARY 
     A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary MOSFETs is controlled by the digital control interface circuit. A pair of supply voltage rails is provided, wherein one of the pair of supply voltage rails is connected to each of the pair of complementary MOSFETs. A pair of Zener diodes is provided, wherein one of the pair of Zener diodes is connected to each of the pair of complementary MOSFETs. A pair of resistors is provided, wherein one of the pair of resistors is connected in parallel with each of the pair of Zener diodes. A pair of complementary voltage blocking-MOSFETs having predetermined gate bias voltages is provided, wherein each of the pair complementary voltage blocking-MOSFETs is attached to a corresponding one pair of complementary MOSFETs. 
     The features, functions, and advantages can be achieved independently in various embodiments of the disclosure or may be combined in yet other embodiments. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the disclosure will become more fully understand from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  is a schematic diagram illustrating a conventional prior art complementary MOSFETs ultrasound transmitter pulse generator in a typical ultrasound B-scan image system; 
         FIG. 2  is a schematic diagram illustrating the proposed new circuit architecture topology of the transmit pulse generate channels for the basic two-level ultrasound transducer excitation waveform integrated device circuit using lower-voltage MOSFETs; 
         FIG. 3  is the schematic diagram illustrating the proposed new circuit architecture topology of a single channel of the 5-level, AC-coupling gate driving ultrasound transmit pulser generator integrated device circuit; 
         FIG. 4  is a schematic detail diagram illustrating the further proposed new circuit architecture topology of the ultrasound pulse generator use floating gate drivers. 
         FIG. 5  is a schematic detail diagram illustrating the further proposed new circuit architecture topology of the ultrasound pulse generator with independent voltage-blocker MOSFETs and the floating gate drivers. 
         FIG. 6  is a schematic detail diagram illustrating the further proposed new circuit architecture topology of the ultrasound pulse generator with 2-order cascode voltage blocker MOSFETs and the floating gate drivers. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , a schematic diagram illustrating a conventional prior art complementary MOSFETs ultrasound transmitter pulse generator  100  (hereinafter generator  100 ) is shown. In the generator  100 , the sources of P-type MOSFET  104  and N-type MOSFET  111  may be connected to the positive and negative high voltage power supply rail  105  and  110  respectively. The gates of the P-type MOSFET  104  and N-type MOSFET  111  may be connected to the gate coupling capacitors  115  and  124  respectively. The gate coupling capacitors  115  and  124  may be driven by the control waveforms  116  and  122  respectively which may be generated by gate-driver circuits. 
     Between the gates of the P-type MOSFET  104  and N-type MOSFET  111  and the supply voltage rails  105  and  110  there are Zener diodes  101  and  114 , and in paralleled with the gate-source DC bias voltage resistors  102  and  113 . The forward direction of the Zener diodes  101  and  114  are severed as the fast DC restoring diodes function for the AC capacitor coupling, while the Zener diodes break-down direction protecting the possible over voltage of MOSFET gate to source voltages. The switching diodes  109  and  123  block the revise voltage as well as isolate the ultrasound receiver from the transmitter. In the 2-level transmit pulse generator circuit the resistor  108  in parallel with the transducer  107 , discharge the capacitance of the transducer after the waveform transmitted. A typical waveform  106  is shown in the  FIG. 1 . The voltage rating of the MOSFETs  104  and  111  in this prior art have to be at least the same voltage range of from +V to −V. 
     In the advanced ultrasound medical imaging system, it is required to generate a high-voltage and multiple voltage-levels, including the zero or a near-zero voltage level pulses. It also requires providing such a circuit of multiple channels in a single IC package. Therefore it is a challenge to provide a semiconductor process to design and manufacture a high-voltage (+/−100V to +/−200V or higher) and high speed (sub nanosecond to 10 s nanosecond pulse rising and falling time), and to meet the low cost, small in size ICs for the medical ultrasound image system needs. Normally the maximum-speed and maximum-voltage of a given process are limited. And further more, the processes can work with higher-voltage (higher BV) but usually come with lower-speed and/or larger in size. So there is need of a circuitry topology or method to use the lower BV semiconductor process or technology to design and manufacture the high speed integrated circuits (ICs) with higher voltage pulses output and with relatively high integration density. 
     Referring to  FIG. 2 , a novel circuit topology is shown for a 2-level high voltage ultrasound-transmit pulser integrated circuit  200 . As shown in  FIG. 2 , the sources of the P-type MOSFET  204  and N-type MOSFET  211  may be connected to the positive  205  and negative  210  high voltage power supply rails respectively. The gates of the P-type MOSFET  204  and N-type MOSFET  211  may be connected to the gate coupling capacitors  215  and  224  respectively. The gate coupling capacitors  215  and  224  may be driven by the control waveforms  216  and  222  respectively. The control waveforms  216  and  222  may be generated by the gate-driver circuits. Between the gates of the P-type MOSFET  204  and N-type MOSFET  211  and the supply voltage rails  205  and  210  respectively may be Zener diodes  201  and  214 , and in paralleled with the gate-source DC bias voltage resistors  202  and  213 . The Zener diodes  201  and  214  may served the same function as they do in  FIG. 1 . 
     Similar to  FIG. 1 , the output of circuit  200  may have switching diodes  209  and  223 , and a resistor  208  in parallel with the transducer  207 . A typical waveform  206  is shown in the  FIG. 1 . 
     In  FIG. 2  two depletion or enhance or enhance complementally P &amp; N-type of low-voltage blocking MOSFET devices  212  and  213 , are added in serial with the drains of MOSFETs  204  and  211  respectively and the output circuit. Thus the drains of MOSFET drains  204  and  211  may be connected to the sources of MOSFETs  212  and  213  respectively while the drains of MOSFETs  212  and  213  may be coupled to the output circuit. The gates of the MOSFET  212  and  213  may be connected to zero voltage ground or a predetermined near-zero voltages. 
     This new configuration or circuit topology provides higher break-down voltage (BV) of the pulse-generator circuit  200 . For example, by using +/−50V BV IC process, one can design near +/−100V of output pulse generate circuit. 
     Referring now to  FIG. 3 , a 5-level ultrasound transmit pulse generator circuit  300  (hereinafter circuit  300 ) is illustrated. The circuit  300  uses the supply voltage rails of  305   a  and  310   a , together with the supply voltage rails of  305   b  and  310   b  and the ground level  305   c  and  310   c , to generate the 5 voltage levels in the 5-level waveforms. 
     As shown in  FIG. 3 , a plurality of pairs of MOSFETs may be used. In the embodiment shown in  FIG. 3 , the circuit  300  uses three pairs of MOSFETS P-type MOSFETs  304   a ,  304   b , and  304   c  and N-type MOSFETs  311   a ,  311   b , and  311   c . The sources of the P-type MOSFETs  304   a ,  304   b , and  304   c  may be connected to the positive voltage rails  305   a ,  305   b , and  305   c  respectively and the sources of N-type MOSFETs  311   a ,  311   b , and  311   c  may be connected to negative voltage rails  310   a ,  310   b , and  310   c  respectively. The gates of the P-type MOSFETs  304   a ,  304   b  and  304   c  may be connected to the gate coupling capacitors  315   a ,  315   b  and  315   c  respectively. While the gates of the N-type MOSFETs  311   a ,  311   b  and  311   c  may be connected to the gate coupling capacitors  324   a ,  324   b  and  324   c  respectively. The gate coupling capacitors  315   a ,  315   b ,  315   c ,  324   a ,  324   b  and  324   c  may be driven by the control waveforms  316   a ,  316   b ,  316   c ,  322   a ,  322   b  and  322   c  respectively. The control waveforms  316   a ,  316   b ,  316   c ,  322   a ,  322   b  and  322   c  may be generated by the gate-driver circuits. 
     Between the gates of the P-type MOSFETs  304   a ,  304   b  and  304   c  and their respective supply voltage rails  305   a ,  305   b  and  305   c  may be Zener diodes  301   a ,  301   b  and  301   c  respectively in parallel with the gate-source DC bias voltage resistors  302   a ,  302   b  and  302   c  respectively. The gates of the N-type MOSFETs  311 ,  311   b  and  31   c  and their respective supply voltage rails  310   a ,  310   b  and  310   c  may be Zener diodes  314   a ,  314   b  and  314   c  respectively in parallel with the gate-source DC bias voltage resistors  313   a ,  313   b  and  313   c  respectively. 
     Diodes  309   a ,  309   b ,  309   c ,  323   a ,  323   b , and  323   c  may be connected to the drains of MOSFETS  304   a ,  304   b ,  304   c ,  311   a ,  311   b  and  311   c  respectively. 
     When the MOSFETs  304   c  and  311   c  are turned on, the circuit load  307  and  308  may be discharged to zero level and the “return to zero” (RTZ) or damping function is provided. It is because the sources of  304   c  and  305   c  MOSFETs may both connect to zero volt (ground). Furthermore the drain of MOSFET  304   c  via the diode  309   c  may be directly connected to the output. MOSFETs  304 C and  311 C drain to source voltage rating only need be half of the maximum voltage rating of output pulse peak to peak voltages. The drain of  311   c  via diode  323   c  may be directly connected to the output. The typical waveform this circuit can be generated is shown as waveform  306  in the  FIG. 3 . 
     It is obverse that the complementary pair  313  P-type and  312  N-type depletion or enhance or enhance MOSFETs, the gate to source break-down voltages may be required to be high enough for the maximum peak to peak voltages. Therefore all the drain to source voltage rating of every MOSFET in  FIG. 3  only need be the half of the output waveform maximum swing peak to peak voltage ranges. 
     Referring now to  FIG. 4 , an alternative multi-level high voltage ultrasound transmit pulser integrated circuit  400  (hereinafter circuit  400 ) is shown. The circuit  400  is similar to that in  FIG. 3  but element reference numbers are now  400  series instead of  300  series. In the present embodiment direct-coupling gate drivers  416   a ,  416   b ,  416   c ,  417   a ,  417   b , and  417   c  may be used for each of the MOSFETs  404   a ,  404   b ,  404   c ,  411   a ,  411   b  and  411 C respectively. Besides the coupling circuits  416   a ,  416   b ,  416   c ,  417   a ,  417   b , and  417   c , the main output and cascode voltage blocker depletion or enhance MOSFETs circuitry are same as in the  FIG. 3 . 
     Referring now to  FIG. 5 , an alternative gate-coupling method of the proposed novel multi-level high voltage ultrasound transmit pulser integrated circuit  500  (hereinafter circuit  500 ) is shown. The circuit  500  is similar to that in  FIG. 4  but element reference numbers are now  500  series instead of  300  series. Circuit  500  use independent high voltage blocker MOSFET pairs  513   a  &amp;  512   a ,  513   b  &amp;  512   b  and  513   c  &amp;  512   c . Under the power supply condition of (+V 2 &gt;+V 1 &gt;0) and (−V 2 &lt;−V 2 &lt;0), the diode pair  509   a  and  523   a  could be eliminated. Only the  509   b ,  523   b ,  509   c  and  523   c  are needed. The cascode circuits with voltage-double capability have provide by the case-code MOSFETs  504   a,b  &amp;  513   a,b  and  511   a,b  &amp; 512   a,b . The gate bias voltage of MOSFETs  512   a,b  and  513   a,b  may all be using zero volt. If the output swing is symmetric and the maximum output waveform voltages of the proposed circuit are supplied by the +/−V 2 , then all the MOSFETs voltage rating only need be half of the voltage from +V 2  to −V 2 . 
     Referring now to  FIG. 6 , a multi-level high voltage ultrasound transmit pulser integrated circuit  600  (hereinafter circuit  600 ) is shown. The circuit  600  is similar to previous embodiments but element reference numbers are now  600  series. The circuit  600   s  uses a 2-order cascode circuit with even higher peak to peak output capability. The case-code MOSFETs  618  &amp;  613  may be using the zero volte and +/−V 2 G gate bias voltages  620  and  621 . If the output swing is symmetric and the maximum output waveform voltages of the proposed circuit are supplied by the +/−V 3 , then the MOSFETs voltage rating of  604   a ,  604   b ,  618 ,  613 ,  612 ,  619 ,  611   a  and  611   b  only need be one third of the voltage from +V 3  to −V 3 . The voltage rating of the MOSFETs  604   c  and  611 C only need be half of the voltage from +V 3  to −V 3 . In above condition, the gate bias voltages of MOSFETs  618  and  619  should be about two-third of the +V 3  and −V 3  from ground respectively. 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process, may be implemented by one skilled in the art in view of this disclosure.