Abstract:
A circuit for transforming memory address is disclosed. A first memory address is transformed into a second memory address with more bits than the first memory address for providing a memory. The memory space is an even multiple of the maximum of the first memory address. Therefore a large memory can be used as a small memory.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention is generally related to a circuit for transforming address, and more particularly to a circuit for transforming address for flash memory. 
   2. Description of the Prior Art 
   At present, flash memory is a common storage device for many electronic products. Accompany the advance of technology and the increase of production, the storage capacity of single-die flash memory becomes larger. Small capacity dies become expansive with time or are eliminated. 
   However, many electronic products have long service life to thereby have users be unable to find suitable memory. Therefore, one method to solve such problem is that a cheap memory with large storage capacity can be used as the original memory with small storage capacity. 
   SUMMARY OF THE INVENTION 
   In light of the above background, in order to fulfill the requirements of the industry, the present invention provides a circuit for transforming address. A first memory address is transformed into a second memory address with more bits than the first memory address for providing a memory. The memory space is an even multiple of the maximum of the first memory address. Therefore a large memory can be used as a small memory. Therefore, a cheap memory with large storage capacity can be used as the original memory with small storage capacity. 
   One object of the present invention is to provide a circuit for transforming memory address. The circuit comprises a buffering module, an address transforming module, and an output module. The number of storage bits of the buffering module is a first bit of a first memory address. The address transforming module transforms the first memory address into a second memory address. The number of storage bits of the address transforming module is a second bit of the second memory address. The second bit is larger than the first bit. The output module outputs the second memory address to a bus where the second memory address is transmitted to a memory via the bus and one byte in the memory is addressed according to the second memory address. The storage space of the memory is a multiple of the addressing space of the processor. 
   Another object of the present invention is to provide a circuit for transforming memory address, comprising a plurality of buffering circuits, a plurality of output circuits, a plurality of address transforming circuits, at least one address input circuit, and a memory. The plurality of input buffering circuits store the zeroth bit to the seventh bit and the ninth bit to the twenty-second bit of the first memory address. The plurality of output circuits output the second memory address that at least comprises the zeroth bit to the seventh bit and the ninth bit to the twenty-third bit. The plurality of output circuits output the values stored in the plurality of buffering circuits through the address transforming circuits. The zeroth bit to the seventh bit, the ninth bit to the eleventh bit, and the thirteenth bit to the twenty-third bit of the second memory address are the zeroth bit to the seventh bit, the ninth bit to the eleventh bit, and the twelfth bit to the twenty-second bit of the first memory address, respectively. The at least one address input circuit provides the value for the twelfth bit of the second memory address. Moreover, one of 2 23  bytes in the memory is addressed according to the second memory address and the storage space of the memory is not less than 2 24  bytes. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  shows a schematic diagram illustrating the circuit according to the invention; 
       FIG. 2  shows a schematic diagram illustrating the circuits of the input buffering module and the address transforming module according to the invention; 
       FIG. 3  shows a schematic diagram illustrating the circuit of the output module according to the invention; 
       FIG. 4  shows a schematic diagram illustrating the circuit of the output module according to the invention; 
       FIG. 5  shows a schematic diagram illustrating the protecting circuit according to the invention; 
       FIG. 6  shows a schematic diagram illustrating the protecting circuit according to the invention; and 
       FIG. 7  shows a schematic diagram illustrating the time sequence according to the invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   What is probed into the invention is a circuit for transforming address. Detail descriptions of the structure and elements will be provided in the following in order to make the invention thoroughly understood. Obviously, the application of the invention is not confined to specific details familiar to those who are skilled in the art. On the other hand, the common structures and elements that are known to everyone are not described in details to avoid unnecessary limits of the invention. Some preferred embodiments of the present invention will now be described in greater detail in the following. However, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, that is, this invention can also be applied extensively to other embodiments, and the scope of the present invention is expressly not limited except as specified in the accompanying claims. 
   As shown in  FIG. 1 , the invention provides a circuit for transforming address, comprising an input buffering module  10 , an address transforming module  20 , an output module  30 , at least one address input circuit  40  (not shown in the figure), and a memory  50 . 
   In one embodiment of the present invention, as shown in  FIG. 2 , the input buffering module  10  comprises a plurality of input buffering circuits for storing the zeroth bit to the seventh bit and the ninth bit to the twenty-second bit of the first memory address  12 . Besides, the output module  30  comprises a plurality of output circuits (not shown in  FIG. 2 ) for outputting a second memory address  22 . The second memory address  22  at least comprises the zeroth bit to the seventh bit and the ninth bit to the twenty-third bit. Furthermore, the address transforming module  20  comprises a plurality of address transforming circuits. The plurality of output circuits output the values stored in the plurality of buffering circuits through these address transforming circuits. The zeroth bit to the seventh bit, the ninth bit to the eleventh bit, and the thirteenth bit to the twenty-third bit of the second memory address  22  are the zeroth bit to the seventh bit, the ninth bit to the eleventh bit, and the twelfth bit to the twenty-second bit of the first memory address  12 , respectively. Moreover, the at least one address input circuit  40  is electrically coupled to the plurality of output circuits and at least provides the value for the thirteen bit of the second memory address  22 . Moreover, one of 2 23  bytes in the memory  50  is addressed according to the second memory address  22  and the memory space is not less than 2 24  bytes. 
   The plurality of output circuits of the output module  30  can comprise a plurality of multiplexers. The input comprises a command character  32  and a data character  34 . They are electrically coupled to the memory  50  via a bus  36 . One embodiment of the invention, as shown in  FIG. 3 , comprises eight multiplexers. A first multiplexer  31  uses the zeroth bit of the command character  32 , the zeroth, the ninth, and the seventeenth bits of the second memory address  22 , and the zeroth bit of the data character  34  as input. A second multiplexer  32  uses the first bit of the command character  32 , the first, the tenth, and the eighteenth bits of the second memory address  22 , and the first bit of the data character  34  as input. A third multiplexer  33  that uses the second bit of the command character  32 , the second, the eleventh, and the nineteenth bits of the second memory address  22 , and the second bit of the data character  34  as input. A fourth multiplexer  34  uses the third bit of the command character  32 , the third, the twelfth, and the twentieth bits of the second memory address  22 , and the zeroth bit of the data character  34  as input. A fifth multiplexer  35  uses the fourth bit of the command character  32 , the fourth, the thirteenth, and the twenty-first bits of the second memory address  22 , and the fourth bit of the data character  34  as input. A sixth multiplexer  36  uses the fifth bit of the command character  32 , the fifth, the fourteenth, and the twenty-second bits of the second memory address  22 , and the fifth bit of the data character  34  as input. A seventh multiplexer  37  uses the sixth bit of the command character  32 , the sixth, the fifteenth, and the twenty-third bits of the second memory address  22 , and the sixth bit of the data character  34  as input. An eighth multiplexer  38  uses the seventh bit of the command character  32 , the seventh, the sixteenth, and the twenty-fourth bits of the second memory address  22 , and the seventh bit of the data character  34  as input. Thus, when the storage space of the memory  50  is 2 24  bytes or 2 25  bytes, the values of the thirteenth bit and the twenty-fourth bit of the second memory address  22  are zeros. The address input circuit  40  provides the values (0) of the thirteenth bit and the twenty-fourth bit of the second memory address  22 . That is, in the embodiment of the invention, a large memory, such as having the memory space of 2 24  bytes or 2 25  bytes or even larger, can be used as a small memory, such as having the memory space of 2 23  bytes. 
   Accordingly, in another embodiment of the invention, the memory space can be 2 26  bytes or 2 33  bytes. The plurality of output circuits of the output module  30  can comprise a plurality of multiplexers, as shown in  FIG. 4 . It comprises eight multiplexers. A first multiplexer  31  uses the zeroth bit of the command character  32 , the zeroth, the ninth, the seventeenth, and twenty-fifth bits of the second memory address  22 , and the zeroth bit of the data character  34  as input. A second multiplexer  32  uses the first bit of the command character  32 , the first, the tenth, the eighteenth, and the twenty-sixth bits of the second memory address  22 , and the first bit of the data character  34  as input. A third multiplexer  33  uses the second bit of the command character  32 , the second, the eleventh, the nineteenth, and the twenty-seventh bits of the second memory address  22 , and the second bit of the data character  34  as input. A fourth multiplexer  34  uses the third bit of the command character  32 , the third, the twelfth, the twentieth, and the twenty-eighth bits of the second memory address  22 , and the zeroth bit of the data character  34  as input. A fifth multiplexer  35  uses the fourth bit of the command character  32 , the fourth, the thirteenth, the twenty-first, and the twenty-ninth bits of the second memory address  22 , and the fourth bit of the data character  34  as input. A sixth multiplexer  36  uses the fifth bit of the command character  32 , the fifth, the fourteenth, the twenty-second, and the thirtieth bits of the second memory address  22 , and the fifth bit of the data character  34  as input. A seventh multiplexer  37  uses the sixth bit of the command character  32 , the sixth, the fifteenth, the twenty-third, the thirty-first bits of the second memory address  22 , and the sixth bit of the data character  34  as input. An eighth multiplexer  38  uses the seventh bit of the command character  32 , the seventh, the sixteenth, the twenty-fourth, and the thirty-second bits of the second memory address  22 , and the seventh bit of the data character  34  as input. Thus, when the storage space of the memory  50  is 2 24  bytes, 2 25  bytes, 2 26  bytes, 2 27  bytes, 2 28  bytes, 2 29  bytes, 2 30  bytes, 2 31  bytes, 2 32  bytes, or 2 33  bytes, the values of the thirteenth bit and the twenty-fourth bit to the thirty-second bit of the second memory address  22  are zeros. The address input circuit  40  provides the values (0) of the thirteenth bit and the twenty-fourth bit to the thirty-second bit of the second memory address  22 . 
   The invention further comprises a protecting circuit  60 . The protecting circuit  60  outputs an enable signal  62  and one of 2 23  bytes in the memory  50  is addressed according to the second memory address  22  after receiving the enable signal  62 . It is known by those who are skilled in the art that the protecting circuit  60  is utilized to ensure the input voltage of the memory  50  being higher than a threshold value (standard voltage) before the writing data operation. In a better example of the invention, the protecting circuit  60  comprises a counter  64  and a comparator  66 . The counter  64  accumulates the input of a clock  70  and then outputs a counting value  68 . The comparator  66  compares the counting value  68  with a preset value and then outputs the enable signal  62  when the counting value  68  matches the preset value. In other words, the time needed for the input voltage reaching the threshold value can be calculated and then a preset value can be obtained according to the clock  70 . The writing operation of the memory  50  is delayed until the counter  64  counts to the preset value.  FIGS. 5 and 6  are schematic diagrams illustrating the counter  64  and the comparator  66  as an example. For those who are skilled in the art, other methods can also be applied and will not be described in details. 
     FIG. 7  shows a schematic diagram illustrating the time sequence according to one embodiment of the invention. The output module  30  is electrically coupled to the memory  50  via the bus  36 . In this embodiment, the output of the output module  30  is controlled by an output enable signal  OE  and a selection signal  381 . The command character  32 , the second memory address  22 , the data character  34  are outputted sequentially according to the selection of the selection signal  381 . 
   Obviously many modifications and variations are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims the present invention can be practiced otherwise than as specifically described herein. Although specific embodiments have been illustrated and described herein, it is obvious to those skilled in the art that many modifications of the present invention may be made without departing from what is intended to be limited solely by the appended claims.