Abstract:
The present invention provides a serial data decoder without capacitor that can be made in the form of an integrated circuit without any additional external device. The integrated serial data decoder comprises a clock generator, a frame detector and a channel decoder. Demodulated serial data are inputted for being converted into parallel data periodically and repeatedly.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a serial data decoder, and more particularly to an integrated serial data decoder without any external device.  
       BACKGROUND OF THE INVENTION  
       [0002]     Referring to  FIG. 1 , which is a circuit diagram of a conventional serial data decoder. A receiver  1  at left side of the circuit diagram serves to receive and demodulate the signal, and then input a demodulated signal A (serial data) to the serial data decoder  2  that includes a buffer circuit  21 ; a charging circuit  22  and a decoding circuit  23 .  
         [0003]     The signal A, as shown in  FIG. 2 , is a serial data that serves to transmit the previously parallel data periodically in series. In each frame, many previously parallel data are transmitted in series. As shown at the top of  FIG. 2 , after the signal A of CH 1 , CH 2 , CH 3 , CH 4 . are transmitted in series, there will be a relative long period of idle time that is called “frame-ending section”, and then another frame of serial data transmission will be carried out again.  
         [0004]     The signal A of CH 1 , CH 2 , CH 3 , CH 4  . . . are inputted to the serial data decoder  2  and reshaped by the buffer circuit  21  and then transmitted to the charging circuit  22 . The charging circuit  22  includes resistors, diode and capacitor C 1 . The signal at point B as shown in  FIG. 2  shows the discharging of the capacitor C 1 . During transmission of the serial data CH 1 , CH 2 , CH 3 , CH 4  . . . , the signal at point B keeps staying at a relative high level, while during the frame ending, the capacitor C 1  will be completely discharged due to no serial data. After that, another frame of serial data transmission will be carried out again.  
         [0005]     The signal at point B is transmitted to the decoding circuit  23  and is converted into the parallel data CH 1 , CH 2 , CH 3 , and CH 4  by several D flip-flops  231 ,  232 ,  233  and  234 . The waveforms of the outputs Q 1 , Q 2 , Q 3  and Q 4  of the D flip-flops  231 ,  232 ,  233  and  234  and the waveforms of the parallel data CH 1 , CH 2 , CH 3 , CH 4  are shown in  FIG. 2 .  
         [0006]     The defects of this conventional serial data decoder are that the capacitor C 1  is too big, and the buffer circuit  21 , the charging circuit  22  and the decoding circuit  23  are independent devices external to the receiver  1  and are not easy to be integrated with the receiver  1 . Therefore, the circuit is not only big but also high cost.  
         [0007]     The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.  
       SUMMARY OF THE INVENTION  
       [0008]     The primary objective of the present invention is to provide a serial data decoder without capacitor that can be made in the form of an integrated circuit without any additional external device.  
         [0009]     The integrated serial data decoder comprises a clock generator, a frame detector and a channel decoder, but no capacitor. Demodulated serial data are inputted to the channel decoder, and the channel decoder serves to convert the serial data into parallel data periodically and repeatedly;  
         [0010]     The structure of the demodulated serial data includes a data-transmission section and a frame-ending section, periods of the respective serial data signals in data-transmission section are similar and less than a given period of time N, while the time of the frame-ending section is longer than the given period of time N;  
         [0011]     The frame detector serves to receive output of the clock generator and the demodulated serial data, and to detect the period of the respective serial data, if the period of the respective serial data is less than the period of time N, it means that the serial data are being transmitted, if no serial data is detected and the period is found to be equal to the given period of time N, that means it is in the frame-ending, therefore, a reset signal will be generated to reset the channel decoder, starting another round of serial data transmission;  
         [0012]     The channel decoder comprises a plurality of shift registers, after the demodulated serial data are inputted to the plurality of shift registers, the outputs of two consecutive shift registers will be taken out, and then, after passing through an inverter and an AND gate, a set of parallel data will be generated;  
         [0013]     Outputs of the last two shift registers pass through an inverter and an AND gate to take out a time period B 4 R of the frame-ending section before the reset signal R.  
         [0014]     The frame detector includes a counter clear circuit, a frame-ending detector and a counter.  
         [0015]     The present invention will become more obvious from the following description when taken in connection with the accompanying drawings, which show, for purpose of illustrations only, the preferred embodiment in accordance with the present invention. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]      FIG. 1  is a circuit diagram of a conventional serial data decoder;  
         [0017]      FIG. 2  shows the relative waveforms of the conventional serial data decoder;  
         [0018]      FIG. 3  is a block diagram of a serial data decoder in accordance with the present invention;  
         [0019]      FIG. 4  shows the arrangement and control of the serial data in accordance with the present invention;  
         [0020]      FIG. 5  is a circuit diagram of the serial data decoder in accordance with the present invention;  
         [0021]      FIG. 6  shows the relative waveforms of the integrated serial data decoder in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0022]     Referring to  FIG. 3 , which is a block diagram of a serial data decoder in accordance with the present invention, which includes a clock generator  31 , a frame detector  32  and a channel decoder  33 . A demodulated serial data A is inputted from the left to the channel decoder  33 , and then is converted into parallel data CH 1 , CH 2 , CH 3 , CH 4  by the clock generator  31  and the frame detector  32  periodically and repeatedly.  
         [0023]     Referring to  FIG. 4 , which shows the arrangement and control of the serial data in accordance with the present invention, no charge and/or discharge waveform is shown, since the serial data decoder of the present invention is not provided with capacitor. The signal A of CH 1 , CH 2 , CH 3 , CH 4  are serial data, and the period T of the respective serial data CH 1 , CH 2 , CH 3 , CH 4  are similar and less than a given period of time N that is used to detect whether it is in the frame-ending section. If the period T of the respective serial data CH 1 , CH 2 , CH 3 , CH 4  is less than the given period of time N, this means that the serial data is still being transmitted. If there is no serial data and the detected period T is equal to the given period of time N, that means it is in the frame-ending section, so a reset signal R will be generated to restart another round of serial transmission.  
         [0024]      FIG. 5  is a circuit diagram of the serial data decoder in accordance with the present invention. The demodulated signal A is inputted from the output terminal of the receiver  1  into the frame detector  32  and the channel decoder  33 .  
         [0025]     The channel decoder  33  comprises six shift registers  331 ,  332 ,  333 ,  334 ,  335  and  336 . After the demodulated-signal A is inputted into the channel decoder  33 , the outputs of two consecutive shift registers will be taken out, and then, after passing through an inverter and an AND gate, the parallel data CH 1 , CH 2 , CH 3 , CH 4  will be generated, as shown in  FIG. 5 . The outputs of the shift registers  335  and  336  pass through an inverter and an AND gate to take out the time period B 4 R of the frame-ending section before the reset signal R. The wavefroms of the outputs Q 5 , Q 6 , Q 7 , Q 8  and Q 9  of the shift resistors  331 ,  332 ,  333 ,  334  and  335  and the waveforms of signals CH 1 , CH 2 , CH 3 , CH 4  and B 4 R are shown in  FIG. 6 .  
         [0026]     The frame detector  32  includes a counter clear circuit  321 , a frame-ending detector  322  and a counter  323 .  
         [0027]     The frame-ending detector  322  comprises an OR gate  3221  and an AND gate  3222  that are connected as shown. The outputs CH 1 , CH 2 , CH 3  and CH 4  of the channel decoder  33  and the time period B 4 R are inputted to the OR gate  3221 , therefore, in the transmission of the data CH 1 , CH 2 , CH 3  and CH 4  and the time period B 4 R, the output of the clock generator  31  are inputted to the counter  323 . After the reset signal R appears, the output of the clock generator  31  cannot be inputted to the counter  323  due to the data CH 1 , CH 2 , CH 3  and CH 4  and the time period B 4 R at this moment are zero (as shown in  FIG. 6 ), in this case, the output of the OR gate  3221  and that of the AND gate  3222  are zero.  
         [0028]     The counter  323  serves to record time by counting the signal generated by the clock generator  31 . The counter  323  includes a plurality of divide-by-two flip-flops  3231 ,  3232 ,  3233 ,  3234 ,  3235  and  3236  that are connected as shown in  FIG. 5 , and the number of the divide-by-two flip-flops is determined by the given period of time N shown in  FIG. 4 . The outputs of the divide-by-two flip-flops  3235  and  3236  are transmitted to a D flip-flop  3237 , an inverter  3239  and a NAND gate  3240  after passing through an AND gate  3238 , and then a reset signal R is generated and inputted to the clear terminal (CLR) of the shift registers  331 ,  332 ,  333 ,  334 ,  335  and  336  of the channel decoder  33 . When the counter  323  detects the period of time N, this means it is in the time period B 4 R of frame-ending section, the divide-by-two flip-flops  3235  and  3236  will generate an output that can produce a reset signal R after passing through the AND gate  3238 , the D flip-flop  3237 , the inverter  3239  and the NAND gate  3240 , so that the shift registers  331 ,  332 ,  333 ,  334 ,  335  and  336  of the channel decoder  33  will be reset by the reset signal R, waiting for the next round of serial data input.  
         [0029]     The counter clear circuit  321  includes two D flip-flops  3211  and  3212  and an inverter  3213  and is used to generate clear signal by making use of the data CH 1 , CH 2 , CH 3  and CH 4 , so as to reset the flip-flops  3231 ,  3232 ,  3233 ,  3235 ,  3236  and  3237 . The waveforms of the output QA and QB of the D flip-flops  3211  and  3212  and the waveforms of the output CLR_CH of the inverter  3213  are shown in  FIG. 6 .  
         [0030]     While we have shown and described various embodiments in accordance with the present invention, it should be clear to those skilled in the art that further embodiments may be made without departing from the scope of the present invention.