Abstract:
The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of pending U.S. patent application Ser. No. 11/858,382, filed on Sep. 20, 2007 and entitled “System and method for serial-peripheral-interface data transmission”, which claims priority of Taiwan Patent Application No. TW 96120487, filed on Jun. 7, 2007. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to data transmission, and more particularly to Serial-Peripheral-Interface (SPI) data transmission. 
     2. Description of the Related Art 
       FIG. 1  is a block diagram of a conventional system  100  for Serial-Peripheral-Interface (SPI) data transmission. System  100  includes an SPI controller  110  and an SPI slave  120 . The SPI controller  110  is also referred to as an SPI master. After the SPI controller  110  receives data from a Peripheral Component Interconnect (PCI) bus, the SPI controller  110  transmits the received data to the SPI slave  120  according to SPI standard. 
     A data signal, a clock signal, and a chip select signal are transmitted between the SPI controller  110  and the SPI slave  120 . The data signal comprises data transmitted from the SPI controller  110  to the SPI slave  120  according to SPI standard. The SPI slave  120  operates according to the clock signal, and operation of the SPI slave  120  is suspended if the clock signal is halted. The SPI controller  110  may control multiple SPI slaves and must specify the SPI slave  120  as the transmission target in advance. Thus, the SPI controller  110  enables the chip select signal to select the SPI slave  120  before data transmission between the SPI controller  110  and the SPI slave  120  is started. 
     The SPI controller  110  includes a buffer  112 , and the SPI slave  120  includes a buffer  122  and a memory  124 .  FIG. 2  is a schematic diagram of signals communicated between the SPI controller  110  and the SPI slave  120  of  FIG. 1 . The SPI controller  110  first enables the chip select signal corresponding to the SPI slave  120 , as shown by mark  210  of  FIG. 2 . The SPI controller  110  first stores data received from a PCI bus in the buffer  112 . The SPI controller  110  then transmits an access command  202  and an address  204  through the data signal, wherein the access command  202  may be a write command and the address  204  specifies the writing address of data. 
     The SPI controller  110  then outputs data stored in the buffer  112  to the SPI slave  120  through the data signal  206 . When the SPI slave  120  receives the data output by the SPI controller  110 , the SPI slave  120  temporarily stores the received data in the buffer  122 . When the SPI controller  110  estimates that the buffer  122  of the SPI slave  120  is full or when the SPI controller  110  wants to end the transmission, the SPI controller  110  disables the chip select signal, as shown by mark  220  in  FIG. 2 . When the chip select signal is disabled, the SPI slave  120  moves data stored in the buffer  122  to a memory  124  thereof. Thus, a data-transmission cycle between the SPI controller  110  and the SPI slave  120  is complete. 
     The SPI slave  120  stores data of the buffer  122  into the memory  124  when the SPI controller  110  disables the chip select signal. Storing data into memory  124 , however, requires time and delays data transmission. Thus, the SPI controller  110  disables the chip select signal when the buffer  122  of the SPI slave  120  is full to save the transmission time. To fill the buffer  122  of the SPI slave  120  in one data-transmission cycle, the size of the buffer  112  of the SPI controller  110  is the same as that of the buffer  122  of the SPI slave  120 . The buffer sizes of the buffers  112  and  122  are both assumed to be 256 bytes. If the SPI controller  110  disables the chip select signal when 1-byte data is transmitted, the transmission of 256-byte data requires 211.98 seconds. If the SPI controller  110  disables the chip select signal after 256-byte data is transmitted to fill the buffer  122  of the SPI slave  120 , transmission of 256-byte data only takes 2.58 seconds. 
     Although the buffer sizes of the buffers  112  and  122  are the same, the conventional SPI data transmission still presents some drawbacks, such as the larger the memory  124  of the SPI slave  120  is, the larger the buffer  122  is required. It means an SPI controller  110  should comply with a buffer of the same size. In other words, SPI slaves with buffers of different sizes require different SPI controllers with buffers of different sizes for data transmission, and an SPI controller with fixed buffer size cannot control multiple SPI slaves with buffers of different sizes. If an SPI controller  110  controls an SPI slave  120  with a buffer size exceeding that of the SPI controller, the SPI controller  110  enables the chip select signal when data of the buffer  112  is completely transmitted, but the transmitted data cannot fill the buffer  122  of the SPI slave  120 , causing extra delays in data transmission. Thus, a method for solving the problem of SPI data transmission is required. 
     BRIEF SUMMARY OF THE INVENTION 
     The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating. 
     The invention further provides a method for serial data transmission. First, a clock signal is discontinuously provided to a device selected by a chip select signal for serial data transmission. A plurality of portions of serial data is then transmitted with the clock signal. A clock signal is then halted before subsequent portion of serial data transmission. 
     The invention also provides a system for serial data transmission. In one embodiment, the system comprises a controller for discontinuously providing a clock signal to a device selected by a chip select signal for serial data transmission, wherein the controller transmits a plurality of portions of serial data with the clock signal, the controller halts the clock signal before subsequent portion of serial data transmission. 
     The invention also provides an integrated chip for serial data transmission. In one embodiment, the integrated chip comprises a chip select and a clock. The chip select is configured to select a device for serial data transmission. The clock is configured to discontinuous oscillating for serial data transmission. The integrated chip transmits a plurality of portions of serial data with the clock, and the integrated chip halts the clock before subsequent portion of serial data transmission. 
     The invention also provides a link for serial data transmission. In one embodiment, the link comprises a chip select signal and a clock signal. The chip select signal is configured to select a device for serial data transmission. The clock signal is configured to discontinuous oscillating for serial data transmission, wherein a plurality of portions of serial data is transmitted with the clock signal, and the clock signal is halted before subsequent portion of serial data transmission. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is a block diagram of a conventional system  100  for SPI data transmission; 
         FIG. 2  is a conventional schematic diagram of signals communicated between an SPI controller and an SPI slave of  FIG. 1 ; 
         FIG. 3  is a block diagram of a system for SPI data transmission according to the invention; 
         FIG. 4  is a schematic diagram of signals transmitting between an SPI controller and an SPI slave of  FIG. 3  according to the invention; and 
         FIG. 5  is a block diagram of a portion of an SPI controller according to the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 3  is a block diagram of a system  300  for Serial-Peripheral-Interface (SPI) data transmission according to the invention. The system  300  includes an SPI controller  310  and an SPI slave  320 . After receiving data from a Peripheral Component Interconnect (PCI) bus, the SPI controller  310  implements transmission of received data to the SPI slave  320 . The SPI slave  320  operates according to a clock signal. 
     The SPI controller  310  includes a buffer  312 . The SPI slave  320  includes a buffer  322  and a memory  324 , wherein the size of the buffer  322  greatly exceeds the size of the buffer  312 . In one embodiment, the size of the buffer  312  is 2 I  bytes, the size of the buffer  322  is 2 J  bytes, and the size of the buffer  322  is 2 (J-I)  times of the size of the buffer  312 , wherein I and J are natural numbers. For example, the size of the buffer  322  is 256 bytes, while the size of the buffer  312  can only be 16 bytes, and the size of the buffer  322  is 16 times the size of the buffer  312 . 
       FIG. 4  is a schematic diagram of signals transmitting between the SPI controller  310  and the SPI slave  320  according to the invention. The SPI controller  310  first enables a chip select signal corresponding to the SPI slave  320  at time T 1 , as shown by mark  410  of  FIG. 4 . Thus, the SPI slave  320  is selected from the multiple SPI slaves controlled by the SPI controller  310  as the data transmission target. After the SPI controller  310  receives 16-byte data from a PCI bus, it stores the received data in the 16-byte buffer  312 . Then the SPI controller  310  transmits an access command  402  and an address  404  to the SPI slave  320 , wherein the access command  402  is write command and the address  404  specifies the writing address of the data. Then the 16-byte data  432  is then transmitted to the SPI slave  320 , which stores the received 16-byte data in the 256-byte buffer  322 . When the 16-byte data is completely transmitted at time T 2 , the SPI controller  310  halts the clock signal. Thus, the SPI salve  320  does not operate while the clock signal is halted just like the clock signal does not oscillate anymore during T 2  and T 3 , and the SPI controller  310  starts to refresh the buffer  312  with new data received from the PCI bus. It is assumed that the SPI controller  310  finishes the refreshment at time T 3 , then the clock signal does not oscillate during T 2  and T 3 , thus the SPI salve  320  stops operating as shown in  FIG. 4 . 
     When the buffer  312  is completely refreshed at time T 3 , the SPI controller  310  restarts the clock signal and the SPI slave  320  continues to operate at time T 3 . Because the SPI slave  320  operates after the clock signal restarts, the SPI controller  310  can transmit refreshed data of the buffer  312  to the buffer  322  of the SPI slave  320  at time T 3 . When the SPI controller  310  has completely transmitted the refreshed data at time T 4 , the SPI controller  310  halts the clock signal again to stop operation of the SPI slave  320 . The SPI controller  310  then receives new data from the PCI bus to refresh data content of the buffer  312 . Halting of the clock signal, refreshing of the buffer  312 , restarting of the clock signal and transmitting of the data are recursively repeated until the SPI controller completes the transmission of all data or the buffer  322  of the SPI slave  320  is full. Because the size of the buffer  322  is 256 bytes and the size of the buffer  312  is 16 bytes, the buffer  322  is full after the 16 th  data transmission cycle. 
     When the SPI controller  310  determines that the buffer  322  of the SPI slave  320  is full, or the SPI controller  310  has no more data for transmission, the SPI controller  310  disables the chip select signal at time T 8 , as shown by the mark  420  of  FIG. 4 . When the SPI slave  320  detects that the chip select signal is disabled, it moves data stored in the buffer  322  to the memory  324 . Thus, one data transmission cycle between the SPI controller  310  and the SPI slave  320  is completed. 
     The clock signal is repeatedly halted for constant intervals during a data transmission cycle, such as periods  442  and  444  of  FIG. 4 . While the clock signal does not oscillate, the buffer  312  of the SPI controller  310  is refreshed with data received from the PCI bus. While the clock signal oscillates, data stored in the buffer  312  is transmitted to the buffer  322  of the SPI slave  320 . Because the frequency of PCI bus is 33 MHz and the size of the buffer  312  is 16 bytes, refreshing of the buffer  312  requires only 240 ns. Thus, the clock signal is halted for only a very short time, which could almost be ignored. 
     Because the buffer  312  of the SPI controller  310  is small, the SPI controller  310  can repeatedly transmit data to fill a buffer of an SPI slave  320 , regardless of the buffer size of the SPI slave  320 . When the buffer  322  of the SPI slave  320  is full, the chip select signal corresponding to the SPI slave  320  is disabled to move data of the buffer  322  into a memory  324  of the SPI slave  320 . Thus, the frequency of moving data from the buffer  322  to the memory  324  is reduced to the lowest to reduce delay of transmission. Additionally, the SPI controller  310  can control SPI slaves with buffers of different sizes, and a system designer is not required to design multiple SPI controllers with buffers of different sizes for controlling the multiple SPI slaves with buffers of different sizes. 
       FIG. 5  is a block diagram of a portion of an SPI controller  500  according to the invention. Data received from a PCI bus is first stored into a buffer  502 . When the SPI controller  500  intends to output data signals, a MUX  504  is used to select which of an access command, an address, or data stored in the buffer  502  is output to an SPI slave as a data signal according to a data select signal. When the SPI controller  500  intends to halt a clock signal of the SPI slave, a MUX  506  is used to select which of an oscillating clock signal or a logic low voltage is output to the SPI slave as the clock signal according to a clock select signal. If the logic low voltage is selected, the clock of the SPI slave is halted. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.