Abstract:
A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based on and claims priority under U.S.C. §119 from Japanese Patent Application No. 2008-280169 filed on Oct. 30, 2008. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The invention relates to a manufacturing method for a semiconductor device embedded substrate in which a semiconductor device is embedded. 
         [0004]    2. Related Art 
         [0005]    Hitherto, a wiring substrate (hereinafter referred to as a semiconductor device embedded substrate), in which a semiconductor device is embedded, has been known. For example, the following method (see, e.g., Patent Document 1) has been known as a manufacturing method for a semiconductor device embedded substrate. That is, bumps serving as connection terminals to be electrically connected to a semiconductor integrated circuit which a semiconductor device has are formed in the semiconductor device. Then, the bumps are embedded in a wiring substrate. An insulating layer is applied around the semiconductor device. Subsequently, the bumps are exposed by drilling the insulating layer with a laser. Then, a wiring pattern (rewiring-wire) is formed on the exposed bumps. 
         [0006]    In addition, another method (see, e.g., Patent Document 2) has been known, which comprises a first step of forming bumps serving as connection terminals to be electrically connected to a semiconductor integrated circuit that a semiconductor device has, a second step of forming an insulating layer on bumps, a third step of drilling the insulating layer with laser to thereby form via-holes that reach the bumps, and a fourth step of forming a via wire, with which each via hole is filled, and a wiring pattern (rewiring-wire) to be connected to the via wire. This method uses the bumps as laser stopper layers when via-holes are formed. 
       [Patent Document 1] Japanese Patent No. 2842378 
     [Patent Document 2] JP-A-2005-332887 
       [0007]    However, according to the conventional manufacturing methods for a semiconductor device, an insulating layer is formed on a semiconductor device to hide bumps serving as connection terminals which connect a wiring pattern (rewiring-wire) with a semiconductor integrated circuit that the semiconductor device has. Then, the semiconductor device is embedded in the substrate. In addition, the bumps are exposed by drilling the insulating layer with a laser. Thus, the conventional manufacturing methods have problems that it takes time to perform the step of drilling the insulating layer with a laser, and that the manufacturing cost of the semiconductor device embedded substrate is increased. 
         [0008]    The conventional manufacturing methods have another problem that because laser beams having a predetermined spot diameter (the diameter is about, e.g., 70 μm) are irradiated, the interval of the bumps serving as connection terminals for electrically connecting the wiring pattern (rewiring-wire) to the semiconductor integrated circuit that the semiconductor device has is reduced only to about 150 μm. 
       SUMMARY OF THE INVENTION 
       [0009]    In view of the above respects, the problem that the invention is to resolve is to provide a manufacturing method for a semiconductor device embedded substrate, which can suppress increase of the manufacturing cost thereof and extremely reduce the interval of connection terminals for electrically connecting a wiring pattern (rewiring-wire) to a semiconductor integrated circuit that the semiconductor device has. 
         [0010]    According to a first aspect of the invention, there is provided a manufacturing method for a semiconductor device embedded substrate, including: 
         [0011]    a first step of preparing a semiconductor device that has a semiconductor integrated circuit, a connection terminal electrically connected to the semiconductor integrated circuit, a first insulating layer configured to expose a part of the connection terminal; 
         [0012]    a second step of preparing a support body, and arranging the semiconductor device on one surface of the support body so that an exposed portion of the connection terminal, which is exposed from the first insulating layer, faces the one surface of the support body; 
         [0013]    a third step of forming a second insulating layer on the one surface of the support body to fill at least a space portion adjoining a side surface of the semiconductor device arranged on the one surface of the support body; 
         [0014]    a fourth step of removing the support body; 
         [0015]    a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer, each of which is set so that the surface thereof is opposite to the exposed portion; 
         [0016]    a sixth step of preparing a wiring substrate which has the first wiring pattern, and fixedly mounting the wiring substrate on a surface of each of the semiconductor device and the second insulating layer, each of which is set so that the surface thereof is opposite to the exposed portion, via the third insulating layer; 
         [0017]    a seventh step of forming a first via-hole, from which the first wiring pattern is exposed, in the second insulating layer and the third insulating layer; and 
         [0018]    an eighth step of forming a second wiring pattern to be electrically connected via the first via-hole between the exposed portion and the first wiring pattern on a surface of each of the first insulating layer and the second insulating layer which are set so that the surface thereof is at the side of the exposed portion. 
         [0019]    According to a second aspect of the invention, there is provided the manufacturing method for a semiconductor device embedded substrate according to the first aspect, further including: 
         [0020]    a ninth step of forming a fourth insulating layer on a surface of each of the first insulating layer and the second insulating layer which are set so that the surface thereof is at the side of the exposed portion, to cover the second wiring pattern; 
         [0021]    a tenth step of forming a second via-hole, from which the second wiring pattern is exposed, in the fourth insulating layer; and 
         [0022]    an eleventh step of forming, on the fourth insulating layer, a third wiring pattern which is electrically connected via the second via-hole to the second wiring pattern. 
         [0023]    According to a third aspect of the invention, there is provided the manufacturing method for a semiconductor device embedded substrate according to the second aspect, further including: 
         [0024]    a twelfth step of alternately forming an insulating layer and a wiring pattern so as to cover the third wiring pattern. 
         [0025]    According to a forth aspect of the invention, there is provided the manufacturing method for a semiconductor device embedded substrate according to any one of the first to third aspects, wherein 
         [0026]    the first step comprises the steps of: 
         [0027]    forming the connection terminal on an electrode pad formed on the semiconductor integrated circuit; 
         [0028]    forming the first insulating layer on the semiconductor integrated circuit to cover the connection terminal; 
         [0029]    providing a plate-like body on the first insulating layer, a surface of the plate-like body which is opposite to the first insulating layer, having a rough surface; 
         [0030]    exposing a part of the connection terminal from the first insulating layer by attaching the rough surface of the plate-like body to the first insulating layer by pressure; and 
         [0031]    removing the plate-like body. 
         [0032]    According to the disclosed manufacturing method, there can be provided a manufacturing method for a semiconductor device embedded substrate, which can suppress increase of the manufacturing cost thereof and extremely reduce the interval of connection terminals for electrically connecting a wiring pattern (rewiring-wire) to a semiconductor integrated circuit that the semiconductor device has. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0033]      FIG. 1  is a sectional view of a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0034]      FIG. 2  is an illustration (No.  1 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0035]      FIG. 3  is an illustration (No.  2 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0036]      FIG. 4  is an illustration (No.  3 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0037]      FIG. 5  is an illustration (No.  4 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0038]      FIG. 6  is an illustration (No.  5 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0039]      FIG. 7  is an illustration (No.  6 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0040]      FIG. 8  is an illustration (No.  7 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0041]      FIG. 9  is an illustration (No.  8 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0042]      FIG. 10  is an illustration (No.  9 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0043]      FIG. 11  is an illustration (No.  10 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0044]      FIG. 12  is an illustration (No.  11 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0045]      FIG. 13  is an illustration (No.  12 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0046]      FIG. 14  is an illustration (No.  13 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0047]      FIG. 15  is an illustration (No.  14 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0048]      FIG. 16  is an illustration (No.  15 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0049]      FIG. 17  is an illustration (No.  16 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0050]      FIG. 18  is an illustration (No.  17 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0051]      FIG. 19  is an illustration (No.  18 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0052]      FIG. 20  is an illustration (No.  19 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0053]      FIG. 21  is an illustration (No.  20 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0054]      FIG. 22  is an illustration (No.  21 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0055]      FIG. 23  is an illustration (No.  22 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0056]      FIG. 24  is an illustration (No.  23 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
           [0057]      FIG. 25  is an illustration (No.  24 ) showing a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0058]    Hereinafter, a best mode for carrying out the invention is described by referring to the drawings. 
       [Structure of Semiconductor Device Embedded Substrate According to Embodiment of the Invention] 
       [0059]    First, the structure of a semiconductor device embedded substrate according to an embodiment of the invention is described below.  FIG. 1  is a cross-sectional view illustrating a semiconductor device embedded substrate according to the embodiment of the invention. Referring to  FIG. 1 , a semiconductor device embedded substrate  20  includes a semiconductor device  10 , a wiring substrate  70 , wiring patterns  14  and  44 , a solder resist layer  16 , an external connection terminal  17 , and insulating layers  41 ,  42  and  43 . 
         [0060]    The semiconductor device  10  includes a semiconductor chip  11 , a connection terminal  12 , and an insulating layer  13 . In the semiconductor device  10 , the semiconductor chip  11  includes a semiconductor substrate  21 , a semiconductor integrated circuit  22 , a plurality of electrode pads  23 , and a protection film  24 . The semiconductor substrate  21  is a substrate for forming the semiconductor integrated circuit  22 . The semiconductor substrate  21  is laminated. The thickness T 1  of the semiconductor substrate  21  can be set to range from, e.g., 50 μm to 500 μm. For example, the semiconductor substrate  21  is obtained by individualizing a laminated silicon (Si) wafer. 
         [0061]    The semiconductor integrated circuit  22  is provided on one surface of the semiconductor substrate  21 . The semiconductor integrated circuit  22  includes a diffusion layer (not shown) formed on the semiconductor substrate  21 , an insulating layer (not shown) stacked on the semiconductor substrate  21 , via-holes (not shown) provided in the stacked insulating layer (not shown), and wiring (not shown). 
         [0062]    A plurality of electrode pads  23  are provided on the semiconductor integrated circuit  22 . The plurality of electrode pads  23  are electrically connected to wiring (not shown) provided in the semiconductor integrated circuit  22 . For example, aluminum (Al) can be used as the material of the electrode pads  23 . A material obtained by forming an Al-layer on a copper (Cu) layer, or a material obtained by forming a Si-layer on a Cu-layer and then forming an Al-layer on the Si-layer can be used. 
         [0063]    The protection film  24  is provided on the semiconductor integrated circuit  22 . The protection film  24  is a film for protecting the semiconductor integrated circuit  22 . Sometimes, the protection film  24  is called “a passivation film”. For example, a silicon nitride (SiN) film, and a phosphorous silicate glass (PSG) film can be used as the protection film  24 . Alternatively, a material obtained by stacking a layer made of polyimide or the like on a layer formed of a SiN film, a PSG film or the like can be used as the protection film  24 . 
         [0064]    The connection terminal  12  is provided on the electrode pad  23 . The connection terminal  12  has a shape having a projection portion. A surface  12 A of the connection terminal  12  is exposed from a surface  13 A of the insulating layer  13  and electrically connected to the wiring pattern  14 . That is, the connection terminal  12  has a function of electrically connecting the wiring pattern  14  via the electrode pad  23  to the semiconductor integrated circuit  22  that the semiconductor device  10  has. 
         [0065]    The height H 1  of the connection terminal  12  can be set to range, e.g., from 10 μm to 60 μm. For example, a gold (Au) bump, a Au-plated film, and a metal film constituted by a nickel (Ni)-film, which is formed by an electroless plating method, and a Au-film that covers the Ni-film can be used as the connection terminal  12 . For example, the Au-bump can be formed by a bonding wire using a wire bonding apparatus. Alternatively, the Au-bump can be formed by a plating method. 
         [0066]    The insulating layer  13  seal-protects a circuit formation surface (main surface) of the semiconductor chip  11  and serves as a part of a base material at the time of forming the wiring pattern  14 . The insulating layer  13  is provided to cover the connection terminal  12 , except for the surface  12 A thereof, and the semiconductor chip  11 . The surface  13 A of the insulating layer  13  is set to be substantially flush with the surface  12 A of the connection terminal  12 . 
         [0067]    Either of a photosensitive material and a non-photosensitive material can be used as the material of the insulating layer  13 . For example, an adhesive sheet-like insulating resin (e.g., non-conductive film (NCF)) in a B-stage state (i.e., a semi-cured state), a paste-like insulating resin (e.g., a non-conductive paste (NCP)), an adhesive sheet-like anisotropic conductive resin (e.g., an anisotropic conductive film (ACF)), a paste-like anisotropic conductive resin (e.g., an anisotropic conductive paste (ACP)), a build-up resin (an epoxy resin containing a filler or an epoxy resin without a filler), and a liquid crystal polymer can be cited as the insulating layer  13 . The ACP and the ACF are resins that are obtained by dispersing small-diameter spherically shaped resins coated with Ni/Au into an epoxy-based insulating resin, and that have an electrical-conductivity in a vertical direction and an electrical-insulation-property in a horizontal direction. The thickness T 2  of the insulating layer  13  can be set to range, e.g., from 10 μm to 60 μm. 
         [0068]    The insulating layer  41  is provided to fill a space portion adjoining each side surface of the semiconductor device  10 . The insulating layer  41  is a part of the base material when the wiring pattern  14 , the insulating layer  42  and the insulating layer  43  are formed. Resin materials, such as an epoxy-based resin and a polyimide-based resin, can be used as the material of the insulating layer  41 . 
         [0069]    The insulating layer  42  is provided among the rear surface portion  10 B of the semiconductor device  10 , the surface  41 B of the insulating layer  41 , and the wiring substrate  70 . Either of a photosensitive material and a non-photosensitive material can be used as the material of the insulating layer  42 . For example, an adhesive sheet-like insulating resin (e.g., non-conductive film (NCF)) in a B-stage state (i.e., a semi-cured state), a paste-like insulating resin (e.g., a non-conductive paste (NCP)), an adhesive sheet-like anisotropic conductive resin (e.g., an anisotropic conductive film (ACF)), a paste-like anisotropic conductive resin (e.g., an anisotropic conductive paste (ACP)), a build-up resin (an epoxy resin containing a filler or an epoxy resin without a filler), and a liquid crystal polymer can be cited as the insulating layer  42 . The ACP and the ACF are resins that are obtained by dispersing small-diameter spherically shaped resins coated with Ni/Au into an epoxy-based insulating resin, and that have an electrical-conductivity in a vertical direction and an electrical-insulation-property in a horizontal direction. 
         [0070]    The wiring substrate  70  includes an insulating layer  71 , a via-hole  71 X, wiring patterns  72  and  73 , and solder resist layers  74  and  75 . On the wiring substrate  70 , the wiring pattern  72  is provided on a surface  71 A of the insulating layer  71 . The wiring pattern  73  is provided on a surface  71 B of the insulating layer  71 . The wiring pattern  72  is electrically connected to the wiring pattern  73  via a via-hole  71 X penetrating through the insulating layer  71 . 
         [0071]    The solder resist layer  74  is provided on the surface  71 A of the insulating layer  71  to cover the wiring pattern  72 . The solder resist layer  74  has an opening portion  74 X from which apart of the wiring pattern  72  is exposed. The solder resist layer  75  is provided on the surface  71 B of the insulating layer  71  to cover the wiring pattern  73 . The solder resist layer  75  has an opening portion  75 X from which a part of the wiring pattern  73  is exposed. The part of the wiring pattern  72 , which is exposed from the opening portion  74 X, functions as an electrode pad for being connected to another substrate or the like. The part of the wiring pattern  73 , which is exposed from the opening portion  75 X, functions as an electrode pad for being connected to another substrate or the like. 
         [0072]    The wiring pattern  14  is provided on a surface  13 A of the insulating layer  13  and a surface  41 A of the insulating layer  41  so as to be contacted with a surface  12 A of the connection terminal  12 . The wiring pattern  14  is electrically connected to a semiconductor integrated circuit  22  via the connection terminal  12  and the electrode pad  23 . The wiring pattern  14  is also electrically connected to the wiring pattern  72  of the wiring board  70  via a via-hole  41 X. The wiring pattern  14  is sometimes called what is called a rewiring-wire. The wiring pattern  14  is provided to differentiate the position of the electrode pad  23  from that of an external connection terminal  17  (so as to perform what is called a “fan-out” and the arrangement of terminals at given locations, i.e., what is called a pitch conversion). 
         [0073]    The wiring pattern  14  includes the metal layers  26  and  27 . For example, a layered body including a Cu-layer, another Cu-layer and a chromium (Cr) layer, and a layered body including Cu-layer and a titanium (Ti) layer can be used as the metal layer  26 . Alternatively, an electroless Cu-plating layer can be used as the metal layer  26 . Further alternatively, a metal thin film layer formed by a vapor-deposition method, a coating method, or a chemical vapor deposition (CVD) method can be used as the metal layer  26 . Alternatively, a metal thin film layer formed by a combination of the aforementioned methods of forming a metal layer can be used as the metal layer  26 . The thickness T 6  of the metal layer  26  can be set at, e.g., 2 μm. For example, a Cu-layer can be used as the metal layer  27 . The thickness T 7  of the metal layer  27  can be set at, e.g., 10 μm. 
         [0074]    The insulating layer  43  is provided on the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41  to cover the wiring pattern  14 . Resin materials, such as an epoxy-based resin and a polyimide-based resin, can be used as the material of the insulating layer  43 . The wiring pattern  44  is provided on the surface  43 A of the insulating layer  43 . The wiring pattern  44  is electrically connected to the wiring pattern  14  via the via-hole  43 X formed in the insulating layer  43 . 
         [0075]    The wiring pattern  44  includes the metal layers  46  and  47 . For example, a layered body including a Cu-layer, another Cu-layer and a Cr-layer, and a layered body including Cu-layer and a Ti-layer can be used as the metal layer  46 . Alternatively, an electroless Cu-plating layer can be used as the metal layer  46 . Further alternatively, a metal thin film layer formed by a vapor-deposition method, a coating method, or a chemical vapor deposition (CVD) method can be used as the metal layer  46 . Alternatively, a metal thin film layer formed by a combination of the aforementioned methods of forming a metal layer can be used as the metal layer  46 . The thickness T 8  of the metal layer  46  can be set at, e.g., 2 μm. For example, a Cu-layer can be used as the metal layer  47 . The thickness T 9  of the metal layer  47  can be set at, e.g., 10 μm. 
         [0076]    The solder resist layer  16  is provided on a surface  43 A of the insulating layer  43  to cover the wiring pattern  44 . The solder resist layer  16  has an opening portion  16 X from which a part of the wiring pattern  44  is exposed. The material of the solder resist layer  16  is, e.g., a photosensitive resin composition. 
         [0077]    The external connection terminal  17  is provided on the wiring pattern  44  exposed into the opening portion  16 X of the solder resist layer  16  and/or on the wiring pattern  73  exposed into the opening portion  75 X of the solder resist layer  75 . The external connection terminal  17  is a terminal to be electrically connected to the pad provided on a mounting substrate (not shown), e.g., a motherboard. For example, a solder bump can be used as the external connection terminal  17 . For example, an alloy including Pb, an alloy of tin (Sn) and Cu, an alloy including Sn and silver (Ag), and an alloy including Sn, Ag, and Cu can be used as the material of the external connection terminal  17 . Alternatively, a solder ball (Sn-3.5Ag), which uses a resin (e.g., divinylbenzene) as a core, can be used as the material of the external connection terminal  17 . 
         [0078]    The above is the structure of the semiconductor device embedded substrate according to the embodiment of the invention. 
       [Manufacturing Method for Semiconductor Device Embedded Substrate According to Embodiment of the Invention] 
       [0079]    Next, a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the invention is described below.  FIGS. 2 to 25  exemplify a process of manufacturing a semiconductor device embedded substrate according to the first embodiment of the invention. In  FIGS. 2 to 25 , the same components as those of the semiconductor device embedded substrate  20  illustrated in  FIG. 1  are designated with the same reference characters. The description of some of such components is omitted. In  FIGS. 2 to 11 , reference character “C” designates a position (hereinafter referred to as a “substrate cutting position C”), at which a dicing blade cuts the semiconductor substrate  31 . Reference character “A” denotes a plurality of semiconductor device formation regions (hereinafter referred to as “semiconductor device formation regions A”). Reference character “B” represents a scribe region (hereinafter referred to as a “scribe region B”) including a substrate cutting position C for separating the plurality of semiconductor device formation regions A. 
         [0080]    First, in steps respectively illustrated in  FIGS. 2 and 3 , a semiconductor substrate  31  is prepared, which has a plurality of semiconductor device formation regions A and a scribe region B including a substrate cutting position C for separating a plurality of semiconductor device formation regions A from one another.  FIG. 2  is a cross-sectional view exemplifying a semiconductor substrate.  FIG. 3  is a plan view exemplifying the semiconductor substrate. The semiconductor substrate  31  illustrated in  FIGS. 2 and 3  is laminated, and cut at the substrate cutting positions C. Thus, the semiconductor substrate  31  is formed into the aforementioned semiconductor substrate  21  (see  FIG. 1 ). For example, a Si-wafer can be used as the semiconductor substrate  31 . The thickness T 3  of the semiconductor substrate  31  can be set to range, e.g., from 500 μm to 775 μm. 
         [0081]    Next, in a step illustrated in  FIG. 4 , the semiconductor chip  11  having the semiconductor integrated circuit  22 , the electrode pad  23 , and the protection film  24  is formed in one of the surface portions of the semiconductor substrate  31 , which corresponds to each of the semiconductor device formation regions A. For example, Al can be used as the material of each of the electrode pads  23 . A material obtained by forming an Al-layer on a Cu-layer, a material obtained by forming a Si-layer on a Cu-layer and then forming an Al-layer thereon can be used as the material of each of the electrode pads  23 . For example, a SiN-film and a PSG-film can be used as the protection film  24 . Alternatively, a layer including a polyimide layer can be stacked on a layer including a SiN-film and a PSG-film. 
         [0082]    Next, in a step illustrated in  FIG. 5 , the connection terminals  12  are formed on the plurality of electrode pads  23  provided in the semiconductor device formation regions A, respectively. For example, Au-bumps, Au-plating films, and metal films including a Ni-film formed by an electrolytic plating method or what is called an Al-zincate method and an Au-film stacked on the Ni-film can be used as the connection terminals  12 . The Au-bump can be formed of a bonding wire using a wire bonding apparatus. Alternatively, the Au-bump can be formed by a plating method. There is variation in height among the plurality of connection terminals  12  formed in the step illustrated in  FIG. 5 . 
         [0083]    Next, in a step illustrated in  FIG. 6 , the insulating layer  13  is formed to cover a plurality of semiconductor chips  11  formed on a side, on which the connection terminals  12  are provided, and the connection terminals  12 . Either of a photosensitive material and a non-photosensitive material can be used as the material of the insulating layer  13 . For example, an adhesive sheet-like insulating resin (e.g., non-conductive film (NCF)) in a B-stage state (i.e., a semi-cured state), a paste-like insulating resin (e.g., a non-conductive paste (NCP)), an adhesive sheet-like anisotropic conductive resin (e.g., an anisotropic conductive film (ACF)), a paste-like anisotropic conductive resin (e.g., an anisotropic conductive paste (ACP)), a build-up resin (an epoxy resin containing a filler or an epoxy resin without a filler), and a liquid crystal polymer can be cited as the insulating layer  13 . The ACP and the ACF are the resins that are obtained by dispersing small-diameter spherically shaped resins coated with Ni/Au into an epoxy-based insulating resin, and that have an electrical-conductivity in a vertical direction and an electrical-insulation-property in a horizontal direction. 
         [0084]    In the case of using an adhesive sheet-like insulating resin as the insulating layer  13 , the sheet-like insulating resin is attached to one surface side of a structure illustrated in  FIG. 5 . On the other hand, in the case of using a paste-like insulating resin as the insulating layer  13 , the paste-like insulating resin is formed on one surface side of the structure illustrated in  FIG. 5  by a print method. Subsequently, the insulating resin is semi-cured by being prebaked. The semi-cured insulating resin has adhesiveness. The thickness T 4  of the insulating layer  13  can be set to range, e.g., from 20 μm to 100 μm. 
         [0085]    Next, in a step illustrated in  FIG. 7 , a plate-like body  25  is provided on a surface  13 A of the insulating layer  13 . The plate-like body  25  is such that a surface  25 B thereof, which faces the surface  13 A of the insulating layer  13 , is a rough surface. The thickness T 5  of the plate-like body  25  can be set at, e.g., 10 μm. For example, a metal foil, e.g., a Cu-foil can be used as the plate-like body  25 . Alternatively, a temporary film formed of a polyethylene-terephtalate (PET) can be used as the plate-like body  25 . Further, a resin film with single side copper foil, in which copper foil is previously provided on the single side of the resin film can be used. Hereinafter, the following steps are described below by taking, as an example, the case of using a metal foil as the plate-like body  25 . 
         [0086]    Next, in a step illustrated in  FIG. 8 , in a state in which a structure illustrated in  FIG. 7  is heated, the plate-like body  25  is pushed from the side of a surface  25 A of the plate-like body  25  so as to be attached to the insulating layer  13  by pressure. Consequently, the insulating layer  13  is pressed, so that the surface  12 A of the connection terminal  12  is exposed from the surface  13 A of the insulating layer  13 . In addition, the rough surface, i.e., the surface  25 B of the plate-like body  25  is transferred onto the surface  13 A of the insulating layer  13 . The insulating layer  13  is hardened by heating the structure illustrated in  FIG. 7 . The thickness T 2  of the insulating layer  13  after attaching the plate-like body  25  thereto by pressure can be set to range, e.g., from 10 μm to 60 μm. 
         [0087]    Next, in a step illustrated in  FIG. 9 , the entire plate-like body  25  is removed by etching or the like. As a result of performing processing in the steps respectively illustrated in  FIGS. 7 to 9 , the adhesiveness between the metal layer  26  and the connection terminal  12  can be enhanced in a step which is described below and illustrated in  FIG. 19 . 
         [0088]    Next, in a step illustrated in  FIG. 10 , the semiconductor substrate  31  is polished or grounded from the side of the rear surface of the semiconductor substrate  31 . Thus, the semiconductor substrate  31  is laminated. For example, a back-side grinder or the like is used for the lamination of the semiconductor substrate  31 . The thickness T 1  of the laminated semiconductor substrate  31  can be set to range, e.g., from 50 μm to 500 μm. Sometimes, the step illustrated in  FIG. 10  is eliminated. 
         [0089]    Next, in a step illustrated in  FIG. 11 , the semiconductor substrate  31  corresponding to the scribe region B is cut along the substrate cutting positions C. Thus, a plurality of semiconductor devices  10  are manufactured. The cutting of the semiconductor substrates  31  is performed by, e.g., dicing. 
         [0090]    Next, in a step illustrated in  FIG. 12 , a support body  40  is prepared. Then, a plurality of semiconductor devices  10  are arranged on a surface  40 A of the support body  40  such that the surface  12 A of the connection terminal  12  faces the surface  40 A of the support body  40 . The surface  40 A of the support body  40  has, e.g., adhesiveness. The arranged semiconductor devices  10  are fixed. In a case where the surface  40 A of the support body  40  does not have adhesiveness, the arranged semiconductor devices  10  are fixed by, e.g., an adhesion tape. For example, a PET film, a polyimide film, a metal plate, and a glass plate can be used as the support body  40 . 
         [0091]    Next, in a step illustrated in  FIG. 13 , the insulating layer  41  is formed on the surface  40 A of the support body  40  to fill at least a space portion between opposed side surfaces of the adjacent semiconductor devices  10 . Resin materials, such as an epoxy-based resin and a polyimide-based resin, can be used as the material of the insulating layer  41 . An example of a method of forming the insulating layer  41  is as follows. First, a resin film made of an epoxy-based resin, a polyimide-based resin, or the like is laminated onto the surface  40 A of the support body  40 . Subsequently, the resin film is pressed (pushed). Then, the resin film is hardened by being subjected to a heat treatment at a temperature of, e.g., about 190° C. Thus, the insulating layer  41  can be obtained. Alternatively, first, a liquid resin, such as an epoxy-based resin or a polyimide-based resin, is applied onto the surface  40 A of the support body  40 . Subsequently, the liquid resin is hardened by being subjected to a heat treatment at a temperature of, e.g., about 190° C. Thus, the insulating layer  41  can be obtained. Next, in a step illustrated in  FIG. 14 , the support body  40  illustrated in  FIG. 13  is eliminated. 
         [0092]    Next, in a step illustrated in  FIG. 15 , the wiring substrate  70  manufactured by a known method is prepared. Next, in a step illustrated in  FIG. 16 , the insulating layer  42  is formed on the rear surface portion  10 B of the semiconductor device  10  and a surface  41 B of the insulating layer  41 . Either of a photosensitive material and a non-photosensitive material can be used as the material of the insulating layer  42 . For example, an adhesive sheet-like insulating resin (e.g., non-conductive film (NCF)) in a B-stage state (i.e., a semi-cured state), a paste-like insulating resin (e.g., a non-conductive paste (NCP)), an adhesive sheet-like anisotropic conductive resin (e.g., an anisotropic conductive film (ACF)), a paste-like anisotropic conductive resin (e.g., an anisotropic conductive paste (ACP)), a build-up resin (an epoxy resin containing a filler or an epoxy resin without a filler), and a liquid crystal polymer can be cited as the insulating layer  42 . The ACP and the ACF are the resins that are obtained by dispersing small-diameter spherically shaped resins coated with Ni/Au into an epoxy-based insulating resin, and that have an electrical-conductivity in a vertical direction and an electrical-insulation-property in a horizontal direction. 
         [0093]    In the case of using an adhesive sheet-like insulating resin as the insulating layer  42 , the sheet-like insulating resin is attached to one surface side of a structure illustrated in  FIG. 14 . On the other hand, in the case of using a paste-like insulating resin as the insulating layer  42 , the paste-like insulating resin is formed on one surface side of the structure illustrated in  FIG. 14  by a print method. Subsequently, the insulating resin is semi-cured by being prebaked. The semi-cured insulating resin has adhesiveness. 
         [0094]    Next, in a step illustrated in  FIG. 17 , the wiring substrate  70  and the structure illustrated in  FIG. 16  are bonded to each other so that the solder resist layer  74  of the wiring substrate  70  faces the insulating layer  42  of the structure illustrated in  FIG. 16 . Subsequently, the insulating layer  42  is hardened by heating the wiring substrate  70  and the structure illustrated in  FIG. 16 . 
         [0095]    Next, in a step illustrated in  FIG. 18 , a via-hole  41 X which is a through hole penetrating through the insulating layer  41  and the insulating layer  42  is formed using a laser processing method or the like so that the wiring pattern  72  is exposed. For example, a CO 2  laser and a YAG laser can be used as the laser. 
         [0096]    Next, in a step illustrated in  FIG. 19 , each wiring pattern  14  having the metal layer  26  and the metal layer  27  is formed on the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41  so as to be contacted with the surface  12 A of the connection terminal  12 . Each wiring pattern  14  is electrically connected to the semiconductor integrated circuit  22  via the connection terminal  12  and the electrode pad  23 . The thickness of the wiring pattern  14  can be set at, e.g., 12 μm. 
         [0097]    More specifically, the wiring pattern  14  is formed as follows. First, each metal layer  26  is formed the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41  by a sputtering method or the like. Each metal layer  26  and the connection terminal  12  are electrically connected to each other. For example, a layered body including a Cu-layer, another Cu-layer and a Cr-layer, and a layered body including Cu-layer and a Ti-layer can be used as the metal layer  26 . Alternatively, an electroless Cu-plating layer can be used as the metal layer  26 . Further alternatively, a metal thin film layer formed by a vapor-deposition method, a coating method, or a chemical vapor deposition (CVD) method can be used as the metal layer  26 . Alternatively, a metal thin film layer formed by a combination of the aforementioned methods of forming a metal layer can be used as the metal layer  26 . The thickness T 6  of the metal layer  26  can be set at, e.g., 2 μm. 
         [0098]    Next, each metal layer  27  is formed by an electrolytic plating method using the metal layer  26  as an electrical-power feeding layer so as to cover the surface of the metal layer  26 . For example, a Cu-layer can be used as the metal layer  27 . The thickness T 7  of the metal layer  27  can be set at, e.g., 10 μm. Then, resist is applied onto the surface of the metal layer  27 . This resist is exposed and developed by a photolithography method. Thus, a resist film is formed on the top portion of the metal layer  27 , which corresponds to a region in which the wiring pattern  14  is formed. 
         [0099]    Next, the metal layers  26  and  27  are etched using the resist films as masks. Thus, a part of the metal layers  26  and  27 , which corresponds to a portion on which no resist film is formed, is removed to thereby form the wiring pattern  14 . Subsequently, the resist film is removed. Then, the roughening of the wiring pattern  14  is performed. The roughening of the wiring pattern  14  can be performed by a method, such as a blackening method or a roughening etching method. The roughening aims at enhancement of the adhesiveness between the wiring pattern  14  and the insulating layer  43  formed on each of the top surface and the side surface of the wiring pattern  14 . 
         [0100]    Next, in a step illustrated in  FIG. 20 , the insulating layer  43  is formed on the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41  so as to cover the wiring pattern  14  shown in  FIG. 19 . Resin materials, such as an epoxy-based resin and a polyimide-based resin, can be used as the material of the insulating layer  43 . An example of a method of forming the insulating layer  43  is as follows. First, a resin film made of an epoxy-based resin, a polyimide-based resin, or the like is laminated onto the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41  so as to cover the wiring pattern  14 . Subsequently, the resin film is pressed (pushed). Then, the resin film is hardened by being subjected to a heat treatment at a temperature of, e.g., about 190° C. Thus, the insulating layer  43  can be obtained. Alternatively, first, a liquid resin, such as an epoxy-based resin or a polyimide-based resin, is applied onto the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41  so as to cover the wiring pattern  14 . Subsequently, the liquid resin is hardened by being subjected to a heat treatment at a temperature of, e.g., about 190° C. Thus, the insulating layer  43  can be obtained. 
         [0101]    Next, in a step illustrated in  FIG. 21 , a via-hole  43 X which is a thorough hole penetrating through the insulating layer  43  is formed using a laser processing method or the like so that the wiring pattern  14  is exposed. For example, a carbon dioxide (CO 2 ) laser and a yttrium aluminum garnet (YAG) laser can be used as the laser. Alternatively, another method can be employed, by which photosensitive resin films are used as the insulating layer  43 , and which via-hole  43 X are formed by performing patterning according to photolithography. Alternatively, another method can be employed, by which via-hole  43 X are formed by performing patterning on resin films that are provided with opening portions by screen-printing. 
         [0102]    Next, in a step illustrated in  FIG. 22 , the wiring pattern  44  having the metal layer  46  and the metal layer  47  is formed on the surface  43 A of the insulating layer  43 . The wiring pattern  44  is electrically connected to the wiring pattern  14  via the via-hole  43 X. The thickness of each of the wiring pattern  44  can be set at, e.g., 12 μm. 
         [0103]    More specifically, the wiring pattern  44  is formed as described below. First, the metal layer  46  is formed in the surface  43 A of the insulating layer  43  and the via-hole  43 X. The metal layer  46  is electrically connected to the wiring pattern  14 . For example, a layered body including a Cu-layer, another Cu-layer and a Cr-layer, and a layered body including Cu-layer and a Ti-layer can be used as the metal layer  46 . Alternatively, an electroless Cu-plating layer can be used as the metal layer  46 . Further alternatively, a metal thin film layer formed by a vapor-deposition method, a coating method, or a chemical vapor deposition (CVD) method can be used as the metal layer  46 . Alternatively, a metal thin film layer formed by a combination of the aforementioned methods of forming a metal layer can be used as the metal layer  46 . The thickness T 8  of the metal layer  46  can be set at, e.g., 2 μm. 
         [0104]    Next, each metal layer  47  is formed by an electrolytic plating method using the metal layer  46  as an electrical-power feeding layer so as to cover the surface of the metal layer  46 . For example, a Cu-layer can be used as the metal layer  47 . The thickness T 9  of the metal layer  47  can be set at, e.g., 10 μm. Then, resist is applied onto the surface of the metal layer  47 . This resist is exposed and developed by a photolithography method. Thus, a resist film is formed on the top portion of the metal layer  47 , which corresponds to a region in which the wiring pattern  44  is formed. 
         [0105]    Next, the metal layer  46  and the metal layer  47  are etched using the resist films as masks. Thus, a part of the metal layer  46  and the metal layer  47 , which corresponds to a portion on which no resist film is formed, is removed to thereby form the wiring pattern  44 . Subsequently, the resist film is removed. Then, the roughening of the wiring pattern  44  is performed. The roughening of the wiring pattern  44  can be performed by a method, such as a blackening method or a roughening etching method. The roughening aims at enhancement of the adhesiveness between the wiring pattern  44  and the solder resist layer  16  formed on each of the top surface and the side surface of the wiring pattern  44 . 
         [0106]    Next, in a step illustrated in  FIG. 23 , the solder resist layer  16  having the opening portion  16 X, from which a part of the wiring pattern  44  is exposed, is formed to cover the wiring pattern  44  and the surface  43 A of the insulating layer  43 . 
         [0107]    More specifically, e.g., a photosensitive resin composition is first applied to cover the wiring pattern  44  and the surface  43 A of the insulating layer  43 . Then, the photosensitive resin composition is exposed and developed according to a photolithography method. The photosensitive resin composition corresponding to the external connection terminal  17  is removed by etching. Thus, the opening portion  16 X, from which a part of the wiring pattern  44  is exposed, is formed to thereby form the solder resist layer  16  having the opening portion  16 X. 
         [0108]    Next, in a step illustrated in  FIG. 24 , the external communication terminal  17  is formed on the wiring pattern  44 , which is exposed in the opening portion  16 X, and/or on the wiring pattern  73 , which is exposed in the opening portion  75 X. For example, each solder bump or the like can be used as the external connection terminal  17 . For examples, an alloy including lead (Pb), an alloy including Sn and Cu, an alloy including Sn and Ag, and an alloy including Sn, Ag, and Cu can be used as the material of the external connection terminal  17 . Alternatively, solder balls (Sn-3.5 Ag) using a resin (e.g., divinylbenzene) as a core can be used. Consequently, a plurality of structures respectively corresponding to the semiconductor device embedded substrates  20  are formed. 
         [0109]    Next, in a step illustrated in  FIG. 25 , each of the structures illustrated in  FIG. 24  is cut substantially at the center of the insulating layer  41 . Thus, a plurality of semiconductor device embedded substrates  20  are formed. The cutting of each of the structures illustrated in  FIG. 24  is performed by, e.g., dicing. 
         [0110]    The above is a manufacturing method for a semiconductor device embedded substrate according to the embodiment of the invention. 
         [0111]    According to the embodiment of the invention, first, each semiconductor device  10 , in which the surface  12 A of the connection terminal  12  is exposed from the insulating layer  13 , is manufactured. Then, the insulating layer  41  is formed to fill at least a side surface portion of each semiconductor device  10 . In addition, the wiring substrate  70  having the wiring pattern manufactured by a known method is fixedly mounted on the rear surface portion  10 B of each semiconductor device  10  and the surface  41 B of the insulating layer  41  via the insulating layer  42 . Then, the via-hole  41 X, from which the wiring pattern  72  is exposed, is formed in the insulating layers  41  and  42 . The wiring pattern  14  for electrically connecting the surface  12 A of the connection terminal  12  to the wiring pattern  72  via the via-hole  41 X is formed on the surface  13 A of the insulating layer  13  and the surface  41 A of the insulating layer  41 . Consequently, a step of drilling the insulating layer with laser to thereby expose the connection terminal is unnecessary. Accordingly, increase in the manufacturing cost of the semiconductor device embedded substrate  20  can be restrained. 
         [0112]    In addition, because the step of drilling the insulating layer with a laser to thereby expose the connection terminal is unnecessary, the intervals of the connection terminals  12  is not restricted by the spot diameter (e.g., the diameter is about 70 μm) of laser-light. Consequently, the interval of the connection terminals  12  for electrically connecting the wiring pattern (wiring-wire)  14  to the semiconductor integrated circuit  22  that the semiconductor device  10  has can be extremely reduced. The interval of the connection terminals  12  can be extremely reduced to a value comparable with the line width (set to be equal to the space width) determined by an L/S (line/space) of the wiring pattern (e.g., the interval is equal to or less than 100 μm, and the minimum interval is about 1 μm). 
         [0113]    In the foregoing description, preferred embodiments of the invention have been described in detail. However, the invention is not limited to the aforementioned embodiments. Various modifications and substitutions can be added to the aforementioned embodiments without departing from the scope of the invention. 
         [0114]    In the foregoing description of the embodiment of invention, the example of using a double-sided (bi-layer) wiring substrate, on both surfaces of which wiring patterns are formed, as the wiring substrate has been described. The wiring substrate according to the invention is not limited thereto. Various wiring substrates can be used. To take one example, a multilayer wiring substrate having a core portion, which is manufactured by a build-up industrial method, a coreless multilayer wiring substrate manufactured by the build-up industrial method, a penetration multilayer wiring substrate which connect wiring patterns formed respectively on layers by through-via-holes, or an interstitial via hole (IVH) multilayer wiring substrate, in which the wiring patterns of specific layers are connected by IVHs, can be used. 
         [0115]    In addition, the insulating layers and the wiring patterns are alternately formed on the side of the surface  43 A of the insulating layer  43 , and/or the side of the surface  71 B of the insulating layer  71 . Thus, a semiconductor device embedded substrate having a multilayer wiring pattern (build-up wiring layer) can be implemented. 
         [0116]    Alternatively, the insulating layers  41  can be formed on a side surface portion or a rear surface portion of the semiconductor device  10 .