Abstract:
A method of manufacturing a coreless substrate having filled via pads, including: forming a first insulating layer on one side of a carrier forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; removing the carrier, and forming via-holes in the first and second insulating layers; and conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a U.S. divisional application filed under 37 CFR 1.53(b) claiming priority benefit of U.S. Ser. No. 12/320,284, filed on Jan. 22, 2009, now allowed, which claims earlier foreign priority benefit to Korean Patent Application No. 10-2008-0102626, filed Oct. 20, 2008, entitled “CORELESS SUBSTRATE HAVING FILLED VIA PAD AND A MANUFACTURING METHOD THE SAME”, the above being incorporated by reference in their entirety into this application. 
     
    
     BACKGROUND 
       [0002]    1. Field 
         [0003]    The present invention relates to a coreless substrate having filled via pads and a method of manufacturing the same, and more particularly to a coreless substrate having filled via pads in which a filled via having the same height as that of an insulating layer is used as a pad and a method of manufacturing the same. 
         [0004]    2. Description of the Related Art 
         [0005]    These days, with developments in the electronics industry, demands for the miniaturization and increased functionality of electronic components have rapidly increased, and printed circuit boards incorporating such electronic components therein also are requiring high density circuit and thin substrates. 
         [0006]    In particular, a typical build-up printed circuit board is manufactured in a manner such that a build-up layer is formed on a core substrate, and thus the resulting build-up printed circuit board product still containing the core substrate therein is used. Unfortunately, this causes an increase in the total thickness of the printed circuit board. If a thickness of the printed circuit board increases, the length of the circuit is elongated, and thus an increased amount of time is required for signal processing. 
         [0007]    To solve the above problems, a coreless substrate rather than a core substrate having a thick thickness has been proposed.  FIGS. 1 to 5  show a process of manufacturing the conventional coreless substrate. 
         [0008]    Hereinafter, a process of manufacturing the conventional coreless substrate is described with reference to  FIGS. 1 to 5 . 
         [0009]    As shown in  FIG. 1 , a lower insulating layer  12  is first formed on a metal carrier  11  for supporting a coreless substrate. 
         [0010]    As shown in  FIG. 2 , a build-up layer  13 , which includes a circuit layer  13   b  composed of a plurality of build-up insulating layers  13   a  and a plurality of circuit layers  13   b  having vias  13   c , is formed on the lower insulating layer  12 , and an upper insulating layer  14  is formed on the build-up layer  13 . 
         [0011]    Subsequently, as shown in  FIG. 3 , upper openings  14   a  are formed in the upper insulating layer  14  such that upper pads of the uppermost circuit layer  13   b  contained in the build-up layer  13  are exposed through the upper openings  14   a . In this process, the openings  14   a  may be formed using a drilling machining or a laser radiation. 
         [0012]    As shown in  FIG. 4 , the metal carrier  11  is eliminated using etching. 
         [0013]    Finally, as shown in  FIG. 5 , lower openings  12   a  are formed in the lower insulating layer  12  such that lower pads of the lowermost circuit layer  13   b  contained in the build-up layer  13  are exposed through the lower openings  12   a , and then solder balls  15  are formed on the upper and lower pads for the connection with exterior connecting terminals. 
         [0014]    Through the above-described process, the conventional coreless substrate  10  is manufactured. 
         [0015]    However, the conventional coreless substrate  10  and the method of manufacturing the coreless substrate have the following disadvantages. 
         [0016]    First, since the conventional coreless substrate  10  is configured such that the upper and lower pads are exposed through the upper openings  14   a  and the lower openings  12   a , respectively, as shown in  FIG. 5 , the coreless substrate may have stepped portions which deteriorate matching accuracy between the solder balls  15  and the upper/lower pads and also deteriorate the reliability of bonding. 
         [0017]    Furthermore, since the conventional method of manufacturing a coreless substrate  10  involves the use of a metal carrier  11  to support the coreless substrate  10  during the manufacturing process, manufacturing costs are increased. In addition to this, since the method involves an etching process of eliminating the metal carrier  11 , manufacturing time is increased. 
         [0018]    Also, since the build-up layer  13  is provided only at one side with respect to the metal carrier  11 , productivity thereof is decreased. In addition, when the process of forming the build-up layer is conducted only at one side, products become seriously warped during the manufacturing process. 
         [0019]    In addition, during drilling or laser machining when forming the upper openings  14   a  and the lower openings  12   a  in the upper insulating layer  14  and the lower insulating layer  12  so as to expose the upper and lower pads through the upper and lower openings, the coreless substrate  10  become warped, and stepped portions are inevitably generated between the pads and the openings  12   a  and  14   a  due to the thicknesses of the upper insulating layer  14  and the lower insulating layer  12 . 
         [0020]    Furthermore, when the metal mask and the thin coreless substrate  10  are bonded to each other in the screen printing process of forming solder balls or bumps for connecting the coreless substrate  10  with an electronic component, a clearance occurs therebetween, thus hindering an even application of solder onto the coreless substrate  10 . Because of the above problems, uniformities of heights and diameters of solder balls or bumps are decreased in the reflow and coining processes, thus decreasing the production yield. 
       SUMMARY 
       [0021]    Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and the present invention provides a coreless substrate having filled via pads in which filled vias are used as pads without need of forming additional openings for exposing the pads therethrough. 
         [0022]    The present invention also provides a method of manufacturing a coreless substrate having filled via pads, which does not use a metal carrier requiring high manufacturing costs and a longer time for elimination. 
         [0023]    The present invention also provides a method of manufacturing a coreless substrate having filled via pads, which increases the production yield and reduces the warp of products by conducting a build-up process on both sides of the a carrier. 
         [0024]    The present invention also provides a method of manufacturing a coreless substrate having filled via pads, which obviates the need for a drilling or laser machining process to be conducted to expose the pads, by adopting filled vias as pads, thus preventing generation of warp and stepped portions. 
         [0025]    The present invention also provides a coreless substrate having filled via pads and a method of manufacturing the same, which facilitates formation of solder balls or bumps and improves uniformity of heights and diameters of the solder balls or bumps. 
         [0026]    In an aspect, the present invention provides a coreless substrate having filled via pads, including: a build-up layer including a build-up layer and a build-up circuit layer having a build-up via; first and second insulating layers disposed on both sides of the build-up layer; and first and second filled via pads formed in the first and second insulating layers, respectively. 
         [0027]    The first and second filled via pads may be embedded in the first and second insulating layers such that a surface of each of the filled via pads is flush with a surface of a corresponding insulating layer. 
         [0028]    The first and second filled via pads may have shapes facing each other. 
         [0029]    The second filled via pads and the build-up via have shapes corresponding to each other. 
         [0030]    The coreless substrate may further include solder balls bonded to the first and second filled via pads. 
         [0031]    In another aspect, the present invention provides a method of manufacturing a coreless substrate having filled via pads, including: (A) forming a first insulating layer on one side of a carrier; (B) forming a build-up layer including a build-up insulating layer and a build-up circuit layer having a build-up via on the first insulating layer, and forming a second insulating layer on the build-up layer; (C) removing the carrier, and forming via-holes in the first and second insulating layers; and (D) conducting a filled plating process in the via-holes of the first and second insulating layers thus forming first and second filled via pads therein. 
         [0032]    The method may further includes, after (D) conducting the filled plating process, (E) subjecting surfaces of the first and second filled via pads to an organic solderability preservative (OSP) treatment or a formation of an electroless nickel immersion gold (ENIG) layer thereon. 
         [0033]    The method may further include, after (D) conducting the filled plating process, (E) forming solder balls on the first and second filled via pads. 
         [0034]    In the method, the carrier may include a copper clad laminate including an insulating resin layer and a thin copper layer formed on at least one side of the insulating resin layer, and a release layer disposed on the copper clad laminate. 
         [0035]    In the method, (D) conducting the filled plating process may include: (D1) forming seed layers on the first and second insulating layers including the via-holes; (D2) applying a resist layer on the first and second insulating layers and patterning the resist layer to form openings through which the via-holes are exposed; (D3) forming filled plating layers on the via-holes exposed through the openings; (D4) eliminating the resist layers; and (D5) eliminating the seed layers and the filled plating layers on the first and second insulating layers to form first and second filled via pads. 
         [0036]    In (D1) forming seed layers, the seed layers may be formed through an electroless plating process or a sputtering process. 
         [0037]    In the method, (D5) eliminating the seed layers and the filled plating layers may include eliminating the seed layers and the filled plating layers such that surfaces of the first and second filled via pads are flush with surfaces of the first and second insulating layers. 
         [0038]    In the method, the first and second filled via pads may have shapes facing each other. 
         [0039]    In the method, the second filled via pads and the build-up via have shapes corresponding to each other. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0040]    The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0041]      FIGS. 1 to 5  are cross-sectional views showing a conventional process of manufacturing a coreless substrate; 
           [0042]      FIG. 6  is a schematic cross-sectional view of a coreless substrate having filled via pads according to an embodiment of the present invention; 
           [0043]      FIG. 7  is a cross-sectional view showing the coreless substrate shown in  FIG. 6  in which solder balls are bonded to the filled via pads; 
           [0044]      FIGS. 8 to 16  are cross-sectional views showing a process of manufacturing a coreless substrate having filled via pads according to a first embodiment of the present invention; and 
           [0045]      FIGS. 17 to 26  are cross-sectional views showing a process of manufacturing a coreless substrate having filled via pads according to a second embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0046]    Various objects, advantages and features of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings. 
         [0047]    The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to best describe the method he or she knows for carrying out the invention. 
         [0048]    In the following detailed description, it should be noted that the terms “first”, “second” and the like are not intended to indicate a specific amount, sequence or significance but are intended to differentiate constituent elements. Furthermore, concerning the designations of reference numerals, it should be noted that the same reference numerals are used throughout the different drawings to designate the same or similar components. Also, in the description of the present invention, when it is considered that the detailed description of a related prior art may obscure the gist of the present invention, such a detailed description is omitted. 
         [0049]    Hereinafter, embodiments of the present invention will be described in greater detail with reference to the following drawings. 
         [0050]      FIG. 6  is a schematic cross-sectional view of a coreless substrate having filled via pads according to an embodiment of the present invention,  FIG. 7  is a cross-sectional view showing the coreless substrate shown in  FIG. 6  in which solder balls are bonded to the filled via pads,  FIGS. 8 to 16  are cross-sectional views showing a process of manufacturing a coreless substrate having filled via pads according to a first embodiment of the present invention, and  FIGS. 17 to 26  are cross-sectional views showing a process of manufacturing a coreless substrate having filled via pads according to a second embodiment of the present invention. 
         [0051]    Coreless Substrate having Filled Via Pads 
         [0052]    Referring to  FIGS. 6 and 7 , a structure of a coreless substrate  100  having filled via pads according to an embodiment of the present invention is described below. 
         [0053]    The coreless substrate  100  according to the embodiment has a characteristic in that first filled via pads  152   a  and second filled via pads  152   b  are formed in a first insulating layer  120  and a second insulating layer  140  formed on both sides of a build-up layer  130 , respectively. In this coreless substrate, the build-up layer  130  comprises a build-up insulating layer  131  and a build-up circuit layer  132  including a build-up via  133 . 
         [0054]    In this embodiment, each of the first filled via pads  152   a  and the corresponding second via pad  152   b  have shapes facing each other. In this regard, the expression “having shapes facing each other” indicates that the shapes (cross-sectional shapes) are configured to be plane-symmetrical to each other. For example, as shown in  FIG. 6 , the first filled via pad  152   a  having a trapezoidal section and the first filled via pad  152   b  having an inverted trapezoidal section may be referred to as having shapes facing each other. 
         [0055]    Furthermore, the second filled via pad  152   b  and the build-up via  133  of the build-up layer  130  have shapes corresponding to each other. In this regard, the expression “having shapes corresponding to each other” indicates that the shapes (the cross-sectional shapes) are identical to each other. For example, as shown in  FIG. 6 , the second filled via pad  152   b  and the build-up via  133  having an inverted trapezoidal section may be referred to as having shapes corresponding to each other. 
         [0056]    The first filled via pads  152   a  and the second filled via pads  152   b  are embedded in the respective first and second insulating layers  120  and  140  such that the outer surfaces of the pads are flush with the outer surfaces of the insulating layers. 
         [0057]    The first filled via pads  152   a  and the second filled via pads  152   b  are provided with solder balls  170   a  and  170   b , respectively, for the connection with exterior connecting terminals. 
       First Embodiment 
       [0058]    Process of Manufacturing a Coreless Substrate having Filled Via Pads 
         [0059]    Referring to  FIGS. 8 to 16 , a process of manufacturing a coreless substrate having filled via pads according to an embodiment of the present invention is described below. 
         [0060]    First, as shown in  FIG. 8 , a carrier  110 , which serves as a support for preventing the coreless substrate from being warped during the manufacturing process, is prepared. 
         [0061]    The carrier  110  according to this embodiment is configured such that double-sided copper clad laminate which is composed of an insulating resin layer  111  and thin copper layers  112  formed on the both sides of the insulating resin layer  111  is provided at both sides with release layers  113 . 
         [0062]    In this embodiment, the double-sided copper clad laminate contains glass material in the insulating layer  111  and has a thickness of about 100-800 μm in order to have a predetermined rigidity. 
         [0063]    The release layer  113  may have a length and an area less than those of the thin copper layer  112 , and may be formed on the thin copper layer  112  except for the margin areas of both sides thereof. The provision of the release layer  113  is intended to facilitate the detachment of the carrier  110 , which will be described in greater detail in the following description of  FIG. 11  in which the carrier  110  is separated from a substrate section P. In this regard, the release layer  113  may be formed from typical release material through a thin film coating or sputtering process. 
         [0064]    Subsequently, as shown in  FIG. 9 , a first insulating layer  120  is formed on the carrier  110 . 
         [0065]    At this point, a peripheral area of the first insulating layer  120  is formed on the thin copper layer  112  of the carrier  110 , and the remaining central area of the first insulating layer  120  is formed on the release layer  113  of the carrier  110 . In this regard, an adhesive force between the first insulating layer  120  and the thin copper layer  112  are higher than that between the first insulating layer  120  and the release layer  113 . 
         [0066]    Although  FIG. 9  shows the first insulating layer  120  which is formed only on one side of the carrier  110 , this is merely provided for the convenience of illustration and explanation. In addition to this, a configuration in which the first insulating layers  120  are formed on both sides of the carrier  110  also falls within the scope of the present invention. Furthermore, it is to be understood that a configuration in which a build-up process is conducted on both sides of the carrier  110  to thus manufacture the coreless substrate also falls within the scope of the present invention. 
         [0067]    As shown in  FIG. 10 , a build-up layer  130  which is composed of a plurality of build-up insulating layers  131  and a plurality of build-up circuit layers  132  is formed on the first insulating layer  120  using a typical build-up technology, and then a second insulating layer  140  is formed on the uppermost layer of the build-up layer  130 . 
         [0068]    In this case, the build-up circuit layer  132  includes build-up vias  133  for the interlayer connection, and the build-up vias  113  are produced in a manner such that via-holes are formed in the build-up layer  131  using laser machining and then a plating process is conducted in the via-holes. In this regard, since the via-holes are formed using the laser machining, they have a cross-sectional shape tapered downwards (an inverted trapezoidal section) (on the basis of  FIG. 10 ). 
         [0069]    Thereafter, as shown in  FIG. 11 , lateral side portions A of a substrate section P and the carrier  110  are cut and eliminated through a routing process, and then the carrier  110  is also eliminated. At this point, the routing process refers to a process of mechanically cutting/trimming workpieces using a routing bit. 
         [0070]    By the process of cutting and eliminating the lateral side portions A of the substrate section P and the carrier  110 , the lateral side portions of the thin copper layer  112  of the carrier  110  and the lateral side portions of the first insulating layer  120 , which are attached to each other by a predetermined adhesive force, are eliminated, thus allowing the substrate section P and the carrier  110  to be easily separated from each other. In other words, after the elimination of the substrate section P and the carrier  110 , the substrate section P is in a state of being attached to the release layer  113 . Consequently, the adhesive force therebetween is weakened, allowing thereby for their easy separation. 
         [0071]    Subsequently, as shown in  FIG. 12 , first via-holes  122  and second via-holes  142  are formed in the first insulating layer  120  and the second insulating layer  140 , respectively. 
         [0072]    At this point, the via-holes  122  and  142  are formed using, for example, a CO 2  laser or a YAG laser. The second via-holes  142 , which are formed in the second insulating layer  140 , have a cross-sectional shape tapered downwards (an inverted trapezoidal section) whereas the first via-holes  122 , which are formed in the first insulating layer  120 , have a cross-sectional shape tapered upwards (a trapezoidal section) (on the basis of  FIG. 12 ). 
         [0073]    As shown in  FIG. 13 , seed layers  150   a  and  150   b  are formed on the first insulating layer  120  and the second insulating layer  140  including internal walls of the via-holes  122  and  142 . At this point, the seed layers  150   a  and  150   b  are formed through an electroless plating process or a sputtering process. 
         [0074]    As shown in  FIG. 14 , resist layers  160   a  and  160   b  such as a dry film are applied to the first insulating layer  120  and the second insulating layer  140 , the resist layers  160   a  and  160  are patterned to form openings  161   a  and  161   b  through which the via-holes  122  and  142  are exposed, and then filled plating layers  151   a  and  151   b  are formed in the via-holes  122  and  142  through an electrolytic plating process. 
         [0075]    As shown in  FIG. 15 , the resist layers  160   a  and  160   b  are removed, and the portions of the seed layers  150   a  and  150   b  and the filled plating layers  151   a  and  151   b  which protrude above surfaces of the first and second insulating layers  120  and  140  are eliminated, so that first filled via pads  152   a  and second filled via pads  152   b  remain in the via-holes. 
         [0076]    In this regard, the seed layers  150   a  and  150   b  and the filled plating layers  151   a  and  151   b  are eliminated using flash etching or a polishing brush. 
         [0077]    The first filled via pads  152   a  and the second filled via pads  152   b  may be subjected to OSP treatment and/or a formation of electroless nickel immersion gold (ENIG) layers thereon. At this point, the OSP treatment is conducted in a manner such that organic material is applied onto surfaces of the filled via pads  152   a  and  152   b  to prevent contact between air and copper surfaces and oxidation of the copper. It is also referred to as a pre-flux treatment because the organic material applied to the surfaces is almost the same as a flux. In the OSP treatment, since the thin copper layers may be oxidized due to contact between air and the copper surfaces if the organic material is not evenly applied to the filled via pads  152   a  and  152   b , the coreless substrate product should be used as soon as possible after opening of the vacuum packaging. 
         [0078]    Finally, as shown in  FIG. 16 , solder balls  170   a  and  170   b  are formed on the first filled via pads  152   a  and the second filled via pads  152   b  for connection with external connecting terminals. 
       Second Embodiment 
       [0079]    Process of Manufacturing a Coreless Substrate having Filled Via Pads 
         [0080]    Referring to  FIGS. 17 to 26 , a process of manufacturing a coreless substrate having filled via pads according to an embodiment of the present invention is described below. In the following description, it should be noted that components which are similar to or identical to those of the first embodiment are designated by the same reference numerals, and detailed descriptions thereof are omitted. 
         [0081]    First, as shown in  FIG. 17 , a carrier  110 , which functions to prevent problems such as warp of the coreless substrate occurring during a build-up process, is prepared. 
         [0082]    Subsequently, as shown in  FIG. 18 , a first insulating layer  120 ′ is formed on the carrier  110 . 
         [0083]    At this point, the first insulating layer  120 ′ is characterized in that it has a thickness which is different and thinner than the first insulating layer  120  of the first embodiment. In this case, the first insulating layer  120 ′ may be a solder resist, and the solder resist may be a film-shaped solder resist rather than a liquid solder resist. 
         [0084]    As shown in  FIG. 19 , a build-up layer  130  which is composed of a plurality of build-up insulating layers  131  and a plurality of build-up circuit layers  132  is formed on the first insulating layer  120 ′ using a typical build-up technology. 
         [0085]    Thereafter, as shown in  FIG. 20 , lateral side portions A of a substrate section P and the carrier  110  are cut and eliminated through a routing process, and then the carrier  110  is also eliminated. 
         [0086]    As shown in  FIG. 21 , a lower insulating layer  121  and a second insulating layer  140  which are thin in thickness are formed on the first insulating layer  120 ′ and the build-up layer  130 , respectively. 
         [0087]    As shown in  FIG. 22 , first via-holes  122  are formed in the first insulating layer  120 ′ and the lower insulating layer  121 , and second via-holes  142  are formed in the second insulating layer  140 . 
         [0088]    In this context, since the first insulating layer  120 ′, the lower insulating layer  121  and the second insulating layer  140  are thinner than the first embodiment, warp of the coreless substrate during the process of machining the via-holes can be minimized. 
         [0089]    Subsequently, as shown in  FIG. 23 , seed layers  150   a  and  150   b  are formed on the first insulating layer  120 ′, the lower insulating layer  121  and the second insulating layer  140  including internal walls of the via-holes  122  and  142 . 
         [0090]    As shown in  FIG. 24 , resist layers  160   a  and  160   b  such as a dry film are applied to the first insulating layer  120 ′, the lower insulating layer  121  and the second insulating layer  140 , the resist layers  160   a  and  160  are patterned to form openings  161   a  and  161   b  through which the via-holes  122  and  142  are exposed, and then filled plating layers  151   a  and  151   b  are formed in the via-holes  122  and  142  through an electrolytic plating process. 
         [0091]    As shown in  FIG. 25 , the resist layers  160   a  and  160   b  are removed, and the portions of the seed layers  150   a  and  150   b  and the filled plating layers  151   a  and  151   b  which protrude above surfaces of the first and second insulating layers  120  and  140  are eliminated, so that first filled via pads  152   a  and second filled via pads  152   b  remain in the via-holes. 
         [0092]    Finally, as shown in  FIG. 26 , solder balls  170   a  and  170   b  are formed on the first filled via pads  152   a  and the second filled via pads  152   b  for connection with external connecting terminals. 
         [0093]    As described above, the coreless substrate according to the present invention includes filled via pads which are configured to be flush with a surface of an insulating layer. Accordingly, reliability of the pads and flatness of bumps are increased, separation of the pads from the substrate is prevented, and bonding of flip chips is easily achieved. 
         [0094]    Also, since the present invention uses a carrier which is composed of a double-sided copper clad laminate and a release layer formed on the double-sided copper clad laminate, manufacturing costs are lowered. In addition, since the present invention does not perform the etching process, manufacturing time is shortened. 
         [0095]    Furthermore, since the present invention executes a build-up process on both sides of a carrier, efficiency of process is improved and warp of products is further reduced. 
         [0096]    Since the present invention uses filled vias as pads, a drilling or laser machining process for exposing the pads is not required. Consequently, generations of warp and stepped regions are prevented, and reliability is increased because there is no problem of void generation in the case of underfill. 
         [0097]    In addition, the present invention has advantages of easy formation of solder balls or bumps and uniform heights and diameters of solder balls or bumps. 
         [0098]    Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Accordingly, such modifications, additions and substitutions should also be understood to fall within the scope of the present invention.