Abstract:
A transmission circuit includes: a first transistor, having a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit; a second transistor, having a source terminal coupled to a gate of the first transistor, and a drain terminal coupled to the first output terminal of the transmission circuit; and a third transistor, having a drain terminal coupled to the first output terminal of the transmission, a source terminal coupled to a second reference voltage terminal of the transmission, and a gate terminal for receiving a first input signal; wherein the first and second transistors are of a first conducting type, and the third transistor is of a second conducting type different from the first conducting type.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The disclosed embodiments of the present invention relate to the field of circuit design, and more particularly, to transmission circuits featuring leakage prevention. 
         [0003]    2. Description of the Prior Art 
         [0004]    In special cases, current may flow through a leakage path from a receiving end such as a front-end receiving circuit of a High Definition Multimedia Interface (HDMI) port of a monitor or television, across a transmission line (e.g. an HDMI cable), to a transmission end such as a front-end transmission circuit of an HDMI port of a notebook or a computer. Ina typical case, the receiving end is powered on before the transmission end. Even disregarding the power consumption issue, this is harmful to a circuit because electrode migration may take place, which will damage the circuit to some degree when the circuit remains in such a state for a period of time. 
         [0005]      FIG. 1  is a circuit diagram illustrating a transmission end  10  connected to a receiving end  11 . The transmission end  10  is a conventional design. When a voltage source V DDRX  of the receiving end  11  is powered on but a voltage source V DDTX  of the transmission end  10  is not powered on, the voltage source V DDTX  will be pulled close to 0v for a period of time. The logical value of a control signal V A  is determined by a logical circuit  102 , and transistors  18  and  19  are turned on in response to low input voltages V K  and V Q . The non-powered voltage source V DDTX  slowly pulls a control voltage V A  to 0v, and finally transistors  14  and  15  are turned on although they should remain cut-off. Normally, equivalent impedances of resistors R 1 , R 2  and transistors  14 ,  15  are small, so the path from the voltage source V DDRX  of the receiving end  11  to the voltage source V DDTX  of the transmission end  10  has low impedance. In this situation, current leakage may occur in the receiving end  11  as a result of the transmission end  10  extracting a large current from the receiving end  11 , which can be determined by Ohm&#39;s law. 
         [0006]    In light of the above, there is a need for a novel design to solve this leakage issue. 
       SUMMARY OF THE INVENTION 
       [0007]    One of the objectives of the present invention is to provide transmission circuits featuring leakage prevention in order to solve the aforementioned issues. 
         [0008]    According to a first aspect of the present invention, a transmission circuit is disclosed. The transmission circuit comprises a first transistor, a second transistor and a third transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The second transistor has a source terminal coupled to a gate of the first transistor, and a drain terminal coupled to the first output terminal of the transmission circuit. The third transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to a second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first and second transistors are of a first conducting type, and the third transistor is of a second conducting type different from the first conducting type. 
         [0009]    Preferably, the first transistor and the second transistor of the first conducting type are P-channel MOS transistors, and the third transistor of the second conducting type is an N-channel MOS transistor. 
         [0010]    According to a second aspect of the present invention, a transmission circuit is disclosed. The transmission circuit comprises a first transistor, a first current source and a second transistor. The first transistor has a source terminal coupled to a first reference voltage terminal of the transmission circuit and a drain terminal coupled to a first output terminal of the transmission circuit. The first current source is coupled between a gate terminal of the first transistor and a second reference voltage terminal of the transmission circuit. The second transistor has a drain terminal coupled to the first output terminal of the transmission circuit, a source terminal coupled to the second reference voltage terminal of the transmission circuit, and a gate terminal for receiving a first input signal. The first transistor is of a first conducting type, and the second transistor is of a second conducting type different from the first conducting type. 
         [0011]    Preferably, the first transistor and the second transistor of the first conducting type are P-channel MOS transistors, and the second transistor of the second conducting type is an N-channel MOS transistor. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  is a circuit diagram illustrating a transmission end connected to a receiving end. 
           [0014]      FIG. 2  is a circuit diagram illustrating a transmission circuit with a leakage prevention circuit according to a first embodiment of the present invention. 
           [0015]      FIG. 3  is a circuit diagram illustrating a transmission circuit with a leakage prevention circuit according to a second embodiment of the present invention. 
           [0016]      FIG. 4  is a circuit diagram illustrating a transmission circuit with a leakage prevention circuit according to a third embodiment of the present invention. 
           [0017]      FIG. 5  and  FIG. 6  respectively illustrate single-ended versions of the transmission ends  20  and  30  of  FIG. 2  and  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but same in functions. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is electrically connected to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
         [0019]      FIG. 2  is a circuit diagram illustrating a transmission circuit with a leakage prevention circuit according to a first embodiment of the present invention. A transmission end  20  is powered by a voltage source V DDTX , and a receiving end  11  (which is the same as that illustrated in  FIG. 1 ) is powered by a voltage source V DDRX . The transmission end  20  is biased by a current source I BIAS . The concept of the invention is to alleviate the leakage current issue occurring in the conventional transmission end. For convenience, the transmission end  20  is illustrated as a front-end transmission circuit of a High Definition Multimedia Interface (HDMI) port; and the receiving end  11  is illustrated as a front-end receiving circuit of an HDMI port in this embodiment. The transmission end  20  communicates with the receiving end  11  via output pads  22 ,  23  and an HDMI cable or a wire on a printed circuit board (PCB). Resistors R 1  and R 2  are termination resistors for, respectively, the transmission end  20  and the receiving end  11 . Transistors  24  and  25  are P-channel Metal Oxide Semiconductors (PMOS) in charge of switching the termination resistor R 1 . The transistors  24  and  25  are controlled by a control signal V A . In a normal mode, when the control signal V A  is logic 0, the transistors  24  and  25  will be turned on; else when the control signal V A  becomes logic 1, the transistors  24  and  25  will remain cut-off. Further, the logical value of the control signal V A  is determined by a logical circuit  202 . For brevity, the logical circuit  202  is powered by the voltage source V DDTX  in this embodiment, but this is not a limitation of the invention. Transistors  26  and  27  are N-channel Metal Oxide Semiconductors (NMOS). A differential input signal pair V P  and V N  of the transmission end  20  are respectively fed to gate particular terminals of the transistors  26  and  27 . Note that the invention is not limited to the field of HDMI differential transmission circuits. 
         [0020]    A particular case is when the receiving end  11  is powered on but the transmission end  20  is not. In order to avoid the transistors  24  and  25  from being turned on and forming a leakage path from the voltage source V DDRX  of the receiving end  11  to the voltage source V DDTX  of transmission end  20 , transistors  28 ,  29  and a resistor R 3  are employed as a leakage prevention circuit. Specifically, when said particular case remains for a period of time, a gate terminal voltage V C  of the transistor  29  and a gate terminal voltage V B  of the transistor  28  will be pulled close to 0v. At that point, when seen from the output terminals  22  and  23 , two paths may be obtained: a first path from the output terminals  22  and  23 , via the resistor R 1 , the transistors  24  or  25 , to the voltage source V DDTX ; and a second path from the output terminals  22  and  23 , via the resistor R 3 , the transistor  29 , to the transistor  28 . Since a capacitor is usually configured as a regulator between the voltage source V DDTX  and the ground voltage, and taking into account the parasitic capacitance effects, the equivalent capacitance of the voltage source V DDTX  is much larger than the parasitic capacitance formed at the path from the output terminals  22  or  23  to the transistor  28  via the resistor R 3  and the transistor  29 . As a result, the RC time constant of the first path is much larger than that of the second path. A gate terminal voltage V B  of the transistor  28  and a gate terminal voltage V C  of the transistor  29  will be pulled close to 0v after the transmission end  20  remains at the particular case for a period of time. Once the transistors  28  and  29  are turned on, the voltage source V DDRX  of the receiving end  11  will pull the voltage V A  up to a high voltage level, which will turn the transistors  24  and  25  off. The first path is open and therefore avoids a leakage situation. 
         [0021]    It may be operable to turn off the transistor  28  in the normal mode in order to separate the control signal V A  and the voltage source V DDRX . The resistor R 3  may be designed to provide impedance matching and/or electrostatic discharge (ESD) protection in order to preserve the transistor  29 . In practice, any similar means may be adopted, i.e., the transistor  28  is an essential component, but the resistor R 3  and the transistor  29  are optional components. 
         [0022]    Referring to  FIG. 2  in conjunction with  FIG. 1  it can be seen that, compared to the prior art, the logical circuit  202  for generating the control signal V A  is different from the logical circuit  102  by including an extra NMOS transistor  200 . When the voltage source V DDTX  is powered off, the control signal V EN  of the NMOS transistor  200  will be close to logic 0. A weak pull down circuit may be adopted on the control signal V EN  of the NMOS transistor  200 . The transistor  200  is for avoiding a situation where the leakage path is formed between the voltage source V DDRX  and the voltage source V DDTX  via the second path and the transistors  18  and  19  when the receiving end  11  is powered on and the transmission end  20  is not. In order to meet different requirements, different designs of the logical circuit  202 , other than that is explicitly shown in  FIG. 2 , are also contemplated. For example, despite of the differential architecture of the transmission end  20 , a logical circuit having single-ended architecture is also available for use in controlling the transmission end  20 . 
         [0023]      FIG. 3  is a circuit diagram illustrating a transmission circuit with a leakage prevention circuit according to a second embodiment of the present invention. A transmission end  30  is powered by a voltage source V DDTX , and a receiving end  11  (the same as that illustrated in  FIG. 1 ) is powered by a voltage source V DDRX . The transmission end  30  is biased by a current source I BIAS . The concept of the invention is also to alleviate the leakage current issue occurring in the conventional transmission end. For convenience, the transmission end  30  is illustrated as a front-end transmission circuit of an HDMI port; and the receiving end  11  is illustrated as a front-end receiving circuit of an HDMI port in the embodiment. The transmission end  30  communicates with the receiving end  11  via output pads  32 ,  33  and an HDMI cable or a wire on a PCB. Resistors R 1  and R 2  are termination resistors for the transmission end  30  and the receiving end  11 , respectively. Transistors  34  and  35  are PMOS transistors in charge of switching the termination resistor R 1 . The transistors  34  and  35  are controlled by control signals V X  and V Y , respectively. In a normal mode, when the control signal V X  and the control signal V Y  are both logic 0, the transistors  34  and  35  will be turned on; else when the control signal V A  and the control signal V Y  both become logic 1, the transistors  34  and  35  will remain cut-off. Transistors  36  and  37  are NMOS transistors. A differential input signal pair V P  and V N  of the transmission end  30  are respectively fed to gate terminals of the transistors  36  and  37 . Note that the invention is not limited to the field of HDMI differential transmission circuits. 
         [0024]    A particular case is when the receiving end  11  is powered on but the transmission end  30  is not. In order to prevent the transistors  34  and  35  from being turned on and forming a leakage path from the voltage source V DDRX  of the receiving end  11  to the voltage source V DDTX  of the transmission end  30 , at least a power source I B  is employed as a leakage prevention circuit. Specifically, when said particular case remains for a period of time, the power source I B  is unable to provide a current and is regarded as floating. The capacitor C is then charged by the voltage source V DDRX  so that the voltage source V DDRX  of the receiving end pulls the voltages of the control signals V X  and V Y  to logic 1. The transistors  34  and  35  will be turned off and a first path passing through the resistor R 1  and transistors  34  or  35  to voltage source V DDTX  is open. In this way, the first path is open and can avoid a leakage situation. 
         [0025]    When the voltage source V DDTX  of the transmission end  30  is powered on, the current I B  will produce a small current and the voltage levels of the control signals V X  and V Y  will be pulled low, turning on the transistors  34  and  35 . The conduction of the transistors  34  and  35  may be determined by controlling the current source I B , thus avoiding the leakage situation. Designs of the resistor R 4  and the capacitor C may depend on practical implementations.  FIG. 4  is a circuit diagram illustrating a transmission circuit with a leakage prevention circuit according to a third embodiment of the present invention. A transmission end  40  is an alternative design of  FIG. 3 . Specifically, the control signals V X  and V Y  are combined together. In this way, only one set of current source I B  and capacitor C is required in the transmission end  40  instead of using two sets, as shown in  FIG. 3 . 
         [0026]    Single-ended versions of the transmission ends  20  and  30  are also contemplated according to various embodiments of the present invention.  FIG. 5  and  FIG. 6  respectively illustrate single-ended versions  40  and  50  of transmission ends  20  and  30 . Such transmission ends can be applied in a single-ended signaling data communication system. 
         [0027]    In particular, it is envisaged that the aforementioned inventive concept can be applied by a semiconductor manufacturer to any integrated circuit. It is further envisaged that, for example, a semiconductor manufacturer may employ the inventive concept in the design of a stand-alone device, or application-specific integrated circuit (ASIC) and/or any other sub-system element. 
         [0028]    Although the present invention has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present invention is limited only by the accompanying claims. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in accordance with the invention. In the claims, the term ‘comprising’ does not exclude the presence of other elements or steps. 
         [0029]    Thus, an improved electronic device has been described, wherein the aforementioned disadvantages of the prior art arrangements have been substantially alleviated. 
         [0030]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.