Abstract:
Disclosed is a method for fabricating a semiconductor device. The method includes the steps of: forming a plurality of conductive patterns on a substrate; depositing an insulation layer on the substrate; recessing the insulation layer until a vertical height of the insulation layer becomes lower than that of the plurality of conductive patterns; forming an etch stop layer in the form of sidewalls of the conductive patterns; forming a mask pattern over the etch stop layer; and forming a plurality of contact holes such that etch profiles of the plurality of contact holes are aligned with the plurality of conductive patterns and the substrate is exposed by etching the insulation layer by using the mask pattern as an etch mask.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a contact plug of a semiconductor device.  
       DESCRIPTION OF RELATED ARTS  
       [0002]     As a scale of integration of a semiconductor device has increased, a design rule has decreased. Accordingly, due to a lack in a dose, a focus and an alignment margin of a photolithography process and a limitation in an etch selectivity of an etching process, it is gradually difficult to form a fine pattern.  
         [0003]     Furthermore, as a semiconductor device with a plurality of structures is formed and a distance between neighboring patterns decreases, an insulation property is deteriorated. Thus, a charge coupling is generated between insulation layers for insulating inter-layers from each other, and between the neighboring patterns. The charge coupling makes it impossible to obtain an operation property required by a device.  
         [0004]     In order to improve the aforementioned problems, a self align contact (SAC) etching process using a difference in an etch selectivity of bottom layers and obtaining an etch profile to make a bottom pattern structure automatically aligned is widely used at the present time.  
         [0005]     During performing the SAC etching process, a difference between an etch selectivity of a nitride based layer used as a material to form a hard mask or an etch stop layer and that of an oxide based layer used as a material to form an inter-layer insulation layer is used.  
         [0006]     However, due to an increase in an aspect ratio based on an increase of the scale of integration, it becomes difficult to produce a desirable pattern by only using the SAC etching process.  
         [0007]      FIG. 1  is a photograph of scanning electron microscopy (SEM) illustrating a SAC fail.  
         [0008]     Referring to  FIG. 1 , a field oxide layer  101  is formed on a substrate, thereby defining an active region  102 . A plurality of gate electrode patterns formed by stacking a gate oxide layer  103 , a polysilicon layer  104 , a tungsten layer  105  and a hard mask  106  are formed on the substrate.  
         [0009]     A plurality of cell contact plugs  107  electrically contacted to an impurity diffusion region (not shown) of the substrate are formed between each of the gate electrode patterns. Some portions of the cell contact plugs  107  are electrically contacted to a bit line  109  and other portions of the cell contact plugs  107  are electrically contacted to a contact plug  110  for a storage node.  
         [0010]     However, as described above, as a scale of integration increases, an etch target increases during performing the SAC etching process due to an increase in the aspect ratio.  
         [0011]     Accordingly, an attack is generated in shoulder portions of the gate electrode patterns, i.e., the hard mask  106 .  
         [0012]     The attack generated in the hard mask  106  brings degradation of an insulation property between a gate conductive layer and the cell contact plug  107 , between the gate conductive layer and the bit line  109 , or between the gate conductive layer and the contact plug  110  for the storage node. Also, the excessive attack exposes the gate conductive layer, thereby inducing an electric short between the aforementioned layers.  
         [0013]     A reference numeral  108  shown in  FIG. 1  illustrates the electric short generated between the tungsten layer  105  used as the gate conductive layer and the contact plug  110  for the storage node.  
       SUMMARY OF THE INVENTION  
       [0014]     It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device capable of preventing degradation from being generated in an insulation property between neighboring patterns due to a self align contact (SAC) fail.  
         [0015]     In accordance with one aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a plurality of conductive patterns on a substrate; depositing an insulation layer on the substrate; recessing the insulation layer until a vertical height of the insulation layer becomes lower than that of the plurality of conductive patterns; forming an etch stop layer in the form of sidewalls of the conductive patterns; forming a mask pattern over the etch stop layer; and forming a plurality of contact holes such that etch profiles of the plurality of contact holes are aligned with the plurality of conductive patterns and the substrate is exposed by etching the insulation layer by using the mask pattern as an etch mask.  
         [0016]     In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of: forming a plurality of conductive patterns on a substrate; forming a first etch stop layer along a profile provided with the plurality of conductive patterns; depositing an insulation layer on the first etch stop layer; recessing the insulation layer whose vertical height is lower than the plurality of conductive patterns; forming a second etch stop layer in the form of sidewalls of the conductive patterns; forming a mask pattern over the second etch stop layer; and forming a plurality of contact holes by etching the insulation layer and the first etch stop layer by using the mask pattern as an etch mask such that etch profiles of the plurality of contact holes are aligned with the plurality of conductive patterns and the substrate is exposed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]     The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0018]      FIG. 1 a  photograph of scanning electron microscopy (SEM) illustrating a conventional self align contact (SAC) fail; and  
         [0019]      FIGS. 2A  to  2 F are cross-sectional views illustrating a process for forming a cell contact hole in accordance with the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0020]     Hereinafter, detailed descriptions of preferred embodiments of the present invention will be provided with reference to the accompanying drawings.  
         [0021]      FIGS. 2A  to  2 F are cross-sectional views illustrating a process for forming a cell contact hole in accordance with the present invention.  
         [0022]     As shown in  FIG. 2A , a field oxide layer  201  is partially formed on a substrate  200 , thereby defining a field region and an active region  202 .  
         [0023]     Subsequently, a plurality of gate electrode patterns G 1 , G 2 , G 3  and G 4  formed by stacking a gate insulation layer  203 , a gate conductive layer  204  and a gate hard mask  205  are formed on the substrate  200  provided with various elements such as a well.  
         [0024]     Herein, the gate insulation layer  203  is made of a typical oxide based layer such as a silicon oxide layer and the gate conductive layer  204  is formed in single or in combination of polysilicon, tungsten (W), tungsten nitride (WN), tungsten silicide (WSi x ).  
         [0025]     The gate hard mask  205  serves a role in preventing an attack caused by the gate conductive layer  204  during a self align contact (SAC) etching process for forming a subsequent contact and making it possible to form a SAC etch profile. Thus, the gate hard mask  205  uses a material whose etch speed is greatly different from that of an inter-layer insulation layer. For instance, in case of using an oxide based layer for forming the inter-layer insulation layer, a nitride based layer such as a silicon nitride (SiN) layer or a silicon oxynitride (SiON) layer is used. In case of using a polymer based low-k dielectric layer for forming the inter-layer insulation layer, an oxide based layer is used.  
         [0026]     An impurity diffusion region (not shown) such as a source/drain junction is formed on the substrate  200  between the gate electrode patterns G 1 , G 2 , G 3  and G 4 .  
         [0027]     Next, spacers (not shown) are formed along a profile provided with the gate electrode patterns G 1 , G 2 , G 3  and G 4 . Then, a first etch stop layer  206  is formed on an entire surface where the spacers are formed. The first etch stop layer  206  serves a role in preventing an attack on a lower structure such as the spacers and the gate electrode patterns G 1 , G 2 , G 3  and G 4  during an etching process employing a subsequent SAC process. At this time, it is preferable to form the first etch stop layer  206  along the profile of the lower structure and a nitride based material layer is used for forming the first etch stop layer  206 .  
         [0028]     The first etch stop layer  206  is deposited in a different thickness according to a contact critical dimension (CD). However, it is preferable to deposit the first etch stop layer  206  in a thickness ranging from approximately 100 Å to approximately 300 Å.  
         [0029]     Next, an oxide based inter-layer insulation layer  207  is formed on an upper portion provided with the first etch stop layer  206 .  
         [0030]     In case of using the oxide based layer for forming the inter-layer insulation layer  207 , a material selected from a group consisting of a borosilicateglass (BSG) layer, a borophosphosilicateglass (BPSG) layer, a phosphosilicateglass (PSG) layer, a tetraethylorthosilicate (TEOS) layer, a high density plasma (HDP) oxide layer, a spin-on-glass (SOG) layer and an advanced planarization layer (APL) is used. In addition to the oxide based layer, an inorganic or organic based low-k dielectric layer can be used.  
         [0031]     As shown in  FIG. 2B , a planarization process performed for a removal of a height difference in an upper portion of the inter-layer insulation layer  207  and a planarization of the inter-layer insulation layer  207  is excessively employed, thereby recessing the inter-layer insulation layer  207  to reduce a vertical height of the inter-layer insulation layer  207  compared with that of the gate electrode patterns G 1 , G 2 , G 3  and G 4 .  
         [0032]     At this time, a blanket-etch process or a chemical mechanical polishing (CMP) process is employed. Also, there is another possibility that the CMP process is first performed and then, the inter-layer insulation layer  207  is recessed by using one of a diluted solution of hydrogen fluoride (HF) and a solution of buffered oxide etchant (BOE).  
         [0033]     During employing the blanket-etch process, it is possible to employ a plasma etch to recess a predetermined portion of the inter-layer insulation layer  207 .  
         [0034]     In case of recessing the predetermined portion of the inter-layer insulation layer  207 , the inter-layer insulation layer  207  is additionally recessed in a depth ranging from approximately 200 Å to approximately 1,000 Å from surfaces of the gate patterns.  
         [0035]     Along an entire profile where the inter-layer insulation layer  207  is recessed, a second etch stop layer  208 A is deposited in a thickness ranging from approximately 50 Å to approximately 500 Å.  
         [0036]     The second etch stop layer  208 A includes a nitride based insulation layer selected from a group consisting of a silicon nitride (SiN) based insulation layer, a silicon oxynitride (SION) layer and a silicon-rich oxynitride (SRON) layer.  
         [0037]     It is preferable to employ one of a low pressure chemical vapor deposition (LPCVD) method, an atomic layer deposition (ALD) method and a plasma enhanced chemical vapor deposition (PECVD) method to maximize an etch selectivity of the second etch stop layer  208 A to an oxide based layer.  
         [0038]     As shown in  FIG. 2C , a blanket-etch process is employed to the second etch stop layer  208 A. Herein, the etch stop layer  208 A subjected to the blanket-etch process is denoted as a reference numeral  208 B. Thus, the second etch stop layer  208 B becomes to have a spacer type which the second etch stop layer  208 B is expanded into the recessed inter-layer insulation layer  207  at each shoulder portion of the gate electrode patterns G 1 , G 2 , G 3  and G 4 .  
         [0039]     At this time, a dry etch employing a plasma is used. The first etch stop layer  206  is etched and thus, the gate hard mask  205  can be exposed or some portions of the first etch stop layer  206  can remain.  
         [0040]     As shown in  FIG. 2D , a material layer  209  for a sacrificial hard mask is deposited on the second etch stop layer  208 B in the form of spacer. A photoresist pattern  210  for a cell contact plug formation is formed on the material layer  209  for the sacrificial hard mask.  
         [0041]     The material layer  209  for the sacrificial hard mask is used for the purpose of securing an etch tolerance of the photoresist pattern due to a limitation in a resolution during performing a photolithography process and preventing a pattern deformation. A material selected from a group consisting of a tungsten layer, a polysilicon layer, an amorphous carbon layer, an oxynitride layer and a nitride layer is mainly used as the sacrificial hard mask.  
         [0042]     Meanwhile, during forming the photoresist pattern  210 , an anti-reflective coating layer can be used between the photoresist pattern  210  and a lower structure of the photoresist pattern  210  for the purpose of preventing an undesirable pattern formation from a scattered reflection due to a high degree of light reflection during a photo-exposure process for a pattern formation and improving an adhesiveness between the photoresist pattern  210  and the lower structure of the photoresist pattern  210 . At this time, the anti-reflective coating layer mainly uses an organic based material having a similar etch property with the photoresist pattern  210 . However, according to a process, the anti-reflective coating layer can be omitted.  
         [0043]     More specific to the process for forming the photoresist pattern  210 , a photoresist for ArF or F 2  light source, e.g., COMA or acrylaid which is the photoresist for ArF light source, is coated on the lower structure of the anti-reflective coating layer or the material layer  209  for the sacrificial hard mask in a predetermined thickness by performing a spin coating method. Afterwards, predetermined portions of the photoresist are selectively photo-exposed by using ArF or F 2  light source and a predecided reticle (not shown) for defining a width of a contact hole. Thereafter, a developing process proceeds by making a photo-exposed portion or a non-photo-exposed portion remain, and a cleaning process is then performed to remove etch remnants, thereby forming the photoresist pattern  210  which is a cell contact open mask.  
         [0044]     As shown in  FIG. 2E , the material layer  209  for the hard mask is etched by using the photoresist pattern  210  as an etch mask, thereby forming a sacrificial hard mask  209 A defining a contact hole region for a storage node. Subsequently, the photoresist pattern  210  is removed.  
         [0045]     In case of using an organic based anti-reflective coating layer, the anti-reflective coating layer is simultaneously removed during performing a photoresist strip process for a removal of the photoresist pattern  210 .  
         [0046]     A self align contact (SAC) etching process etching the inter-layer insulation layer  207  by using the sacrificial hard mask  209 A as an etch mask is performed and then, the SAC etching process is stopped at the first etch stop layer  206 . Afterwards, the first etch stop layer  206  is removed, thereby forming a plurality of contact hole  211  exposing an impurity diffusion region of the substrate  200   
         [0047]     During performing the SAC etching process, a typical recipe for the SAC etching process is employed. That is, a fluoride based plasma, e.g., C x F y  (x and y range from approximately 1 to approximately 10) gas such as tetrafluoroethylene (C 2 F 4 ), hexafluoroethane (C 2 F 6 ) octofluoropropane (C 3 F 8 ), hexafluorobutadiene (C 4 F 6 ), octafluorocyclopentene (C 5 F 8 ) or perfluorocyclopentane (C 5 F 10 ) is used as a main etch gas along with an additional C a H b F c  (a, b and c range from approximately 1 to approximately 10) gas such as difluoromethane (CH 2 F 2 ), trifluoromethyl acetylene (C 3 HF 5 ) or trifluoromethane (CHF 3 ). At this time, an inert gas such as helium (He), neon (Ne), argon (Ar) or xenon (Xe) is used as a carrier gas.  
         [0048]     In case of the sacrificial hard mask  209 A, the sacrificial hard mask  209 A is removed after a contact open process or during a plug isolation process.  
         [0049]     During performing the SAC etching process, an etch target increases and thus, although the SAC etching process is excessively employed, the spacer type second etch stop layer  208 B performs a role of an etch stop. Accordingly, an attack is not generated on each of the shoulder portions  212  of the gate electrode patterns G 1 , G 2 , G 3  and G 4 .  
         [0050]     Next, in order to expand a critical dimension (CD) in a lower portion of the contact hole  211 , an additional etching process is employed for approximately 10 seconds to approximately 5 minutes. At this time, a solution of HF diluted with a solution of BOE or pure water by approximately 100-fold to approximately 1,000-fold is used.  
         [0051]     Subsequently, to remove the interface oxide layer formed on a lower portion of the contact hole  211  and the foreign body, a cleaning process is performed before the conductive layer for forming the plug is deposited. At this time, a solution of BOE or HE is used. It is necessary to use the solution of HF diluted with the pure water by approximately 100-fold to approximately 1,000-fold.  
         [0052]     As shown in  FIG. 2F , a conductive layer for forming a plug is deposited on an entire surface, thereby filling the plurality of contact holes  211 . Afterwards, a plug planarization process is employed until the inter-layer insulation layer  207  and the gate hard mask  205  are exposed, thereby forming a plurality of cell contact plugs  213 .  
         [0053]     As described above, in accordance with the present invention, the inter-layer insulation layer is recessed to make a height of the inter-layer insulation layer lower than that of the gate electrode patterns and the second etch stop layer with the spacer type expanded into the recessed inter-layer insulation layer fro the upper portion of the gate electrode patterns is formed, thereby protecting the shoulder portions of the gate electrode patterns. Accordingly, during the SAC etching process, it should be noted that the attack generated on the shoulder portions of the gate electrode patterns can be prevented.  
         [0054]     In accordance with the present invention, although it is exemplified that the mask pattern for the contact hole for the storage node is either a line type or T-type, other various types such as a hole type can also be applied to the present invention.  
         [0055]     Furthermore, in accordance with the present invention, although the process for forming the cell contact plug contacted to the substrate between the plurality of gate electrode patterns is exemplified, a process for forming various types of contact plugs such as a contact plug for a storage node can also be applied to the present invention.  
         [0056]     As described above, the present invention prevents the attack generated on the shoulder portions of the conductive patterns due to the SAC fail during forming the contact plug, thereby providing an effect of improving yields of devices.  
         [0057]     The present application contains subject matter related to the Korean patent application No. KR 2004-0079348, filed in the Korean Patent Office on Oct. 6, 2004, the entire contents of which being incorporated herein by reference.  
         [0058]     While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.