Abstract:
The present invention relates to an interconnect structure for an integrated circuit ( 1 ) having a first interconnect (B 1 ; B 1 ′; B 1 ″), which is composed of a plurality of interconnect sections (A 11 -A 16 ; A 11 ′-A 16 ′; A 11 ″-A 14 ″) lying in a first and a second interconnect plane (M 0 , M 1 ); and a second interconnect (B 2 ; B 2 ′; B 2 ″), which runs adjacent to the first interconnect (B 1 ; B 1 ′; B 1 ″) and which is composed of a plurality of interconnect sections (A 21 -A 25 ; A 21 ′-A 25 ′; A 21 ″-A 23 ″) lying in the first and second interconnect planes (M 0 , M 1 ); the first and second interconnects (B 1 ; B 1 ′; B 1 ″; B 2 ; B 2 ′; B 2 ″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A 12 , A 14 , A 16 ; A 12 ′, A 14 ′, A 16 ′; A 12 ″, A 14 ″) of the first interconnect (B 1 ; B 1 ′; B 1 ″) which lie in the first interconnect plane (M 0 ) run at least in sections beside the interconnect sections (A 22 , A 24 ; A 22 ′; A 24 ′; A 21 ″, A 23 ″) of the second interconnect (B 2 ; B 2 ′; B 2 ″) which lie in the second interconnection plane (M 1 ), and that the interconnect sections (A 11 , A 13 , A 15 ; A 11 ′, A 13 ′, A 15 ′; A 11 ″, A 13 ″) of the first interconnect (B 1 ; B 1 ′; B 1 ″) which lie in the second interconnect plane (M 1 ) run at least in sections beside the interconnect sections (A 21 , A 23 , A 25 ; A 21 ′, A 23 ′, A 25 ′; A 22 ″) of the second interconnect (B 2 ; B 2 ′; B 2 ″) which lie in the first interconnect plane (M 0 ). The invention also provides a corresponding fabrication method.

Description:
TECHNICAL FIELD 
     The present invention relates to an interconnect structure for an integrated circuit and to a corresponding fabrication method. 
     BACKGROUND ART 
     Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to the bit lines of integrated memory circuits using silicon technology. 
     In integrated semiconductor memory circuits, the individual memory cells are usually arranged in matrix form and connected to word lines running in a first direction and bit lines running perpendicularly thereto in a second direction. The addressing is effected by activation of the desired word line and the bit selection by activation of a relevant bit line. 
     A critical factor for the speed of the information transfer in such integrated memory circuits is the coupling capacitance between the individual bit lines. In particular, if such a coupling capacitance is high, it causes signal distortions, signal attenuations and crosstalk. In customary integrated memory circuits, in which the bit lines all lie in a single interconnect plane, so-called bit line entanglement is employed in order to reduce the signal coupling caused by the coupling capacitances. 
     A further possibility for reducing the coupling capacitances is to increase the distance between the individual bit lines by reducing the width/distance ratio. This possibility of improvement is limited, however, by the rise in resistance which is brought about by the narrowing of the bit lines. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the present invention to provide an improved interconnect structure for an integrated circuit and a corresponding fabrication method which has a lower coupling capacitance between adjacent interconnects. 
     According to the invention, this object is achieved by means of the interconnect structure for an integrated circuit according to claim  1 . 
     The idea on which the present invention is based consists in dividing the individual interconnects of an interconnect structure of at least two interconnects into sections which lie in different interconnect planes. Thus, in the case of the interconnect structure according to the invention, a second interconnect plane is introduced which makes it possible to shift adjacent interconnect sections of the bit lines in a matrix vertically with respect to one another, in order thus to reduce the coupling capacitances through the distance that is increased in sections. 
     In this case, in particular, a first and second interconnect are offset with respect to one another in the longitudinal direction in such a way that the interconnect sections of the first interconnect which lie in the first interconnect plane run at least in sections beside the interconnect sections of the second interconnect which lie in the second interconnect plane, and that the interconnect sections of the first interconnect which lie in the second interconnect plane run at least in sections beside the interconnect sections of the second interconnect which lie in the first interconnect plane. 
     The subject-matters according to the invention have the advantage, inter alia, over the known solution approaches that the disturbing coupling capacitances can be significantly reduced. 
     Advantageous developments and improvements of the respective subject-matter of the invention can be found in the subclaims. 
     In accordance with one preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect which lie in the first interconnect plane are in each case directly connected, one to the other, to the interconnect sections of the first interconnect and, respectively, the interconnect sections of the second interconnect which lie in the second interconnect plane. 
     In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect which lie in the first interconnect plane are preferably connected in their ends or in their center via respective first contacts to terminals integrated underneath. 
     In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect which lie in the second interconnect plane are preferably connected in their center via respective second contacts to terminals integrated underneath. 
     In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect all have an identical length. 
     In accordance with a further preferred development, the interconnect sections of the first interconnect and the interconnect sections of the second interconnect are offset with respect to one another approximately by the length or approximately by half the length. 
     In accordance with a further preferred development, a multiplicity of first and second interconnects arranged parallel to one another are provided, which are offset with respect to one another in a regular pattern. 
     In accordance with a further preferred development, the multiplicity of first and second interconnects arranged parallel to one another are bit lines of an integrated memory circuit. 
     Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the description below. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the figures: 
     FIG. 1 shows a diagrammatic sectional illustration of a bit line structure of an integrated memory circuit using silicon technology in accordance with a first embodiment of the present invention; 
     FIG. 2 shows a diagrammatic plan view of the bit line structure of the integrated memory circuit using silicon technology in accordance with the first embodiment of the present invention; 
     FIGS. 3 a - 3   g  show diagrammatic sectional illustrations along the line A-A′ in FIG. 2 for elucidating a first embodiment of a fabrication method for fabricating the bit line structure in accordance with FIGS. 1 and 2; 
     FIG. 4 shows a diagrammatic sectional illustration along the line B-B′ in FIG. 2 in accordance with the process status of FIG. 3 g  for elucidating the first embodiment of the fabrication method for fabricating the bit line structure in accordance with FIGS. 1 and 2; 
     FIG. 5 shows a diagrammatic sectional illustration of a bit line structure of an integrated memory circuit using silicon technology in accordance with a second embodiment of the present invention; 
     FIG. 6 shows a diagrammatic plan view of the bit line structure of the integrated memory circuit using silicon technology in accordance with the second embodiment of the present invention; 
     FIGS. 7 a - 7   g  show diagrammatic sectional illustrations along the line C-C′ in FIG. 6 for elucidating a second embodiment of a fabrication method for fabricating the bit line structure in accordance with FIGS. 5 and 6; 
     FIG. 8 shows a diagrammatic sectional illustration along the line B-B′ in FIG. 2 in accordance with the process status of FIG. 7 g  for elucidating the second embodiment of the fabrication method for fabricating the bit line structure in accordance with FIGS. 5 and 6; and 
     FIG. 9 shows a diagrammatic plan view of the bit line structure of the integrated memory circuit using silicon technology in accordance with a third embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the figures, identical reference symbols designate identical or functionally identical constituents. 
     FIG. 1 shows a diagrammatic sectional illustration of a bit line structure of an integrated memory circuit using silicon technology in accordance with a first embodiment of the present invention. 
     In FIG. 1, reference symbol B 1  designates a first bit line, which is a part of the bit line structure in accordance with the first embodiment of the invention. Reference symbol  1  generally designates an integrated memory circuit whose generally known circuitry details are not shown, except for bit line terminals C 11 , C 12 , C 13 , C 14 , C 15  of the individual memory cells. In particular, the bit line terminals C 11  to C 15  are embedded in an insulation plane I at the surface of the integrated memory circuit  1 . A 11 , A 12 , A 13 , A 14 , A 15 , A 16  designate interconnect sections of the bit line B 1  which lie in two different interconnect planes M 0 , M 1 , the interconnect planes being directly connected to one another via the ends of the individual interconnect sections A 11  to A 16  without an intervening contact plane. 
     The bit line B 1  is alternately composed of interconnect sections of the first (lower) metalization plane M 0  and of the second (upper) metalization plane M 1 . Contacts K 11 , K 12 , K 13 , K 14 , K 15  are provided at the ends of the interconnect sections A 12 , A 14 , A 16  of the first interconnect plane M 0 , which contacts are connected to respective bit line terminals C 11  to C 15  of the memory cells of the memory circuit  1 . In the example shown, all the interconnect sections A 11  to A 16  have the same length L. 
     FIG. 2 shows a diagrammatic plan view of the bit line structure of the integrated memory circuit using silicon technology in accordance with the first embodiment of the present invention. 
     In FIG. 2, B 1 , B 2 , B 3 , B 4  designate four bit lines of the bit line structure in accordance with the first embodiment of the invention, which bit lines run next to one another or adjacent and parallel. All the bit lines B 1  to B 4  have the same width b, which corresponds to the distance d between adjacent bit lines projected onto the first metalization plane M 0 . In the present exemplary embodiment, this is intended to be the minimum design width of the technology used. 
     In accordance with the description of the first bit line B 1  effected above with reference to FIG. 1, the bit line B 2  correspondingly has contacts K 21 , K 22 , K 23 , K 24  and interconnect sections A 21 , A 22 , A 23 , A 24 , A 25 . 
     The bit line B 3  correspondingly has contacts K 31 , K 32 , K 33 , K 34 , K 35  and bit line sections A 31 , A 32 , A 33 , A 34 , A 35 , and the bit line B 4  correspondingly has contacts K 41 , K 42 , K 43 , K 44  and bit line sections A 41 , A 42 , A 43 , A 44 , A 45 . 
     The interconnect sections A 12 , A 14 , A 16 , A 21 , A 23 , A 25 , A 32 , A 34 , A 36 , A 41 , A 43 , A 45  depicted in hatched fashion in FIG. 2 lie in the first interconnect plane or metalization plane M 0 , and the interconnect sections A 11 , A 13 , A 15 , A 22 , A 24 , A 31 , A 33 , A 35 , A 42 , A 44  depicted without hatching lie in the second metalization plane or interconnect plane M 1 . 
     As can be seen from FIG. 2, the bit line terminals of the memory cells of the integrated memory circuit  1  which correspond to the contacts K 11 -K 44  are arranged in rows at the same distance X, respectively adjacent rows being displaced with respect to one another by half the distance X/2 between the bit line terminals. Accordingly, the interconnect sections of adjacent bit lines are also displaced with respect to one another by this distance X/2, as indicated in FIG.  2 . 
     What is thereby achieved is that in the partial sections in which an interconnect section in the first interconnect plane M 0  is adjacent to an interconnect section in the second interconnect plane M 1 , the distance between these two interconnect sections is enlarged, namely by the vertical displacement, and the coupling capacitance is thus reduced compared with the case where all the interconnect sections lie in the same interconnect plane. 
     It should be mentioned in this connection that the ideal case occurs, of course, when interconnect sections of the first interconnect plane are adjacent to corresponding interconnect sections of the second interconnect plane over their entire length. In practice, however, with regard to the position of the bit line terminals of the memory cells and the required contacts connected thereto, it is often necessary to make a compromise with regard to reducing the coupling capacitance and the complexity of the fabrication process. 
     In FIG. 2, finally, the reference symbols A-A′ and B-B′ designate sectional lines through the first and second bit lines B 1 , B 2 , the fabrication process for the bit line structure in accordance with the first embodiment being explained below using the corresponding sectional illustration with reference to FIGS. 3 and 4. 
     FIGS. 3 a-g  show diagrammatic sectional illustrations along the line A-A′ in FIG. 2 for elucidating a first embodiment of a fabrication method for fabricating the bit line structure in accordance with FIGS. 1 and 2. 
     In accordance with FIG. 3 a , firstly the integrated memory circuit  1  is provided, which has the upper insulation plane I, in which the bit line terminals of the memory cells, for example the bit line terminal C 21  in FIG. 3 a , are provided. 
     In a first process step in accordance with FIG. 3 b , depressions V 12 , V 21  are then provided in the upper region of the insulation plane I in an etching process, which depressions correspond to the interconnect sections of the first interconnect plane M 0 . In FIG. 3 b , the depressions V 12  and V 21 , in particular, correspond to the interconnect sections A 12  and A 21  in FIG.  2 . 
     In a further process step, which is explained with reference to FIG. 3 c , contact holes, such as, for example, the contact hole L 21  in FIG. 3 c , are then formed at the corresponding end points of the interconnect sections of the first metalization plane M 0 . 
     In the embodiment described here, the depressions V 12 , V 21 , etc. and also the contact holes L 21 , etc. are formed by a so-called dual Damascene process. 
     In the process step in accordance with FIG. 3 d , the first interconnect plane M 0 , which is a tungsten metalization plane, for example, is deposited over the whole area of the resulting structure. During this deposition, the contact holes L 21 , etc. are filled with tungsten, and the surface of the structure is also covered with tungsten to a specific thickness. 
     In the subsequent process step, which is explained with reference to FIG. 3 e , a chemical mechanical polishing step is carried out which polishes away the tungsten provided on the surface of the structure, so that only the interconnect sections of the first metalization plane M 0  remain in the depressions V 12 , V 21 , etc., in order to form the interconnect sections A 12 , A 21 , etc. of the first metalization plane M 0 . 
     After this, with reference to FIG. 3 f , the second interconnect plane or metalization plane M 1 , here likewise tungsten, is deposited over the whole area of the resulting structure planarized by the CMP process. 
     The second interconnect plane M 1  is then patterned by a customary photolithographic etching step, in order to obtain the interconnect sections A 22 , etc. of the second interconnect plane M 1 , as illustrated in FIG.  2 . This last leads to the structure shown in FIG. 3 g.    
     FIG. 4 is a diagrammatic sectional illustration along the line B-B′ in FIG. 2 in accordance with the process status of FIG. 3 g  for elucidating the first embodiment of the fabrication method for fabricating the bit line structure in accordance with FIGS. 1 and 2. 
     As can be seen from the section along the line B-B′ as shown in FIG. 4, in the regions in which interconnect sections A 12  of the first interconnect plane M 0  lie next to interconnect sections A 22  of the second interconnect plane M 1 , the intervening distance is increased from the distance d in the planar case to the distance d′, which lowers the coupling capacitance between the two interconnect sections A 12  and A 22  and correspondingly reduces the disturbances that occur. 
     FIG. 5 shows a diagrammatic sectional illustration of a bit line structure of an integrated memory circuit using silicon technology in accordance with a second embodiment of the present invention. 
     In FIG. 5, B 1 ′ designates a bit line of the bit line structure in accordance with the second embodiment of the present invention. 
     In a manner identical to that in the case of the first embodiment explained above, the interconnect sections A 11 ′, A 12 ′, A 13 ′, A 14 ′, A 15 ′ and A 16 ′ are alternately arranged in the different interconnect planes M 0  and M 1 , respectively, and all have an identical length L. 
     In contrast to the first embodiment, in the case of the second embodiment, the distances between the bit line terminals C 11 ′, C 12 ′, C 13 ′, C 14 ′, C 15 ′, C 16 ′, C 17 ′, C 18 ′, C 19 ′ of the memory cells of the integrated memory circuit  1  are illustrated in differently scaled fashion and the contact connections are altered. Moreover, in the case of the second embodiment, some of the contacts K 11 ′ to K 19 ′ are also provided in the center of the interconnect sections of the first interconnect plane M 0 , namely the contacts K 12 ′ and K 16 ′ here. Moreover, contacts to the interconnect sections of the second interconnect plane M 1  are provided here, namely the contacts K 14 ′ and K 18 ′ leading to the interconnect sections A 13 ′ and A 15 ′, respectively. 
     FIG. 6 shows a diagrammatic plan view of the bit line structure of the integrated memory circuit using silicon technology in accordance with the second embodiment of the present invention. 
     FIG. 6 shows bit lines B 1 ′, B 2 ′, B 3 ′, B 4 ′ according to the bit line structure in accordance with the second embodiment of the present invention. 
     The bit line B 1 ′ in FIG. 6 has already been explained with reference to FIG.  5 . The remaining bit lines B 2 ′, B 3 ′, B 4 ′ are constructed analogously, and adjacent bit lines are offset with respect to one another by a length of X′/2, as indicated in FIG. 6, X′ being the distance between two bit line terminals. 
     In accordance with the designations of the bit line B 1 ′ in FIG. 5, in the case of the bit line B 2 ′, the reference symbols K 21 ′ to K 29 ′ designate contacts and the reference symbols A 21 ′ to A 25 ′ designate interconnect sections. 
     In the case of the bit line B 3 ′, K 31 ′ to K 39 ′ designate contacts and the reference symbols A 31 ′ to A 35 ′ designate interconnect sections. Finally, in the case of the bit line B 4 ′, the reference symbols K 41 ′ to K 49 ′ designate contacts and the reference symbols A 41 ′ to A 45 ′ designate interconnect sections. 
     It is also the case with the second embodiment shown in FIG. 6 that, by virtue of the fact that in each case approximately half of an interconnect section of the first metalization plane M 0  lies next to half of a further interconnect section of the second metalization plane M 1 , the advantage is afforded that the coupling capacitances [lacuna] considerably relative to the planar state, in which all the interconnect sections or of [sic] all the interconnects lie in one metalization plane, [lacuna] a significantly reduced coupling capacitance. 
     In FIG. 6, finally, the reference symbols C-C′ and D-D′ designate sectional lines through the first and second bit lines B 1 ′, B 2 ′, the fabrication process for the bit line structure in accordance with the first embodiment being explained below using the corresponding sectional illustration with reference to FIGS. 7 and 8. 
     FIGS. 7 a-g  show diagrammatic sectional illustrations along the line C-C′ in FIG. 6 for elucidating a second embodiment of a fabrication method for fabricating the bit line structure in accordance with FIGS. 5 and 6. 
     In accordance with FIG. 7 a , firstly the integrated memory circuit  1  with the insulation plane I located at the surface is provided, the section C-C′ depicting the bit line terminals C 12 ′ and C 22 ′, but not the complete integrated memory circuit  1  for reasons of clarity. 
     In accordance with FIG. 7 b , in a first step, depressions V 12 ′ and V 21 ′ are formed in the surface of the insulation plane I by etching, which depressions correspond to interconnect sections A 12 ′, A 21 ′ of the first interconnect plane M 0 . 
     As elucidated in FIG. 7 c , corresponding contact holes L 12 ′, L 22 ′ leading to the bit line terminals C 12 ′, C 22 ′, etc. are then formed, as is revealed clearly in FIG. 6, in particular. 
     In accordance with the illustration of FIG. 7 d , the first interconnect plane M 0 , here in the form of a tungsten metalization plane, is then deposited over the resulting structure over the resulting structure [sic], as a result of which the contact holes K 12 ′, K 22 ′, etc. are filled, and the first interconnect plane M 0  covering the surface of the structure with a certain height. 
     In a subsequent chemical mechanical polishing step, which is illustrated with reference to FIG. 7 e , the first interconnect plane M 0  is then polished back, thereby completing the interconnect sections A 12 ′, A 21 ′, etc. of the first metalization plane M 0 , to be precise in such a way that they are embedded in the surrounding insulating layer. 
     In the next process step, which is illustrated with reference to FIG. 7 f , the second metalization plane M 1  is deposited over the whole area of the resulting planarized structure. 
     On this, as in the case of the first embodiment, a photolithographic etching step is carried out in order to form the interconnect sections A 22 ′, etc. of the second metalization plane M 1 , which leads to the state shown in FIG. 7 g.    
     FIG. 8 is a diagrammatic sectional illustration along the line B-B′ in FIG. 2 in accordance with the process status of FIG. 7 g  for elucidating the second embodiment of the fabrication method for fabricating the bit line structure in accordance with FIGS. 5 and 6. 
     What can be gathered from FIG. 8 is that the contact holes K 23 ′, etc. leading directly to the interconnect sections A 22 ′, etc. of the second metalization plane M 1  are formed in the same process step as the contacts leading from the interconnect sections A 12 ′ of the first interconnect plane M 0  to the corresponding bit line terminals of the memory cells of the integrated memory circuit  1 . In other words, the contacts K 23 ′, etc. are formed by the metal of the first metalization plane M 0 . 
     FIG. 9 shows a diagrammatic plan view of the bit line structure of the integrated memory circuit using silicon technology in accordance with a third embodiment of the present invention. 
     FIG. 9 shows bit lines B 1 ″, B 2 ″, B 3 ″, B 4 ″, which have the contact-connection pattern according to FIG. 5, although, in contrast to FIG. 6, the contacts are offset with respect to one another from row to row in accordance with the arrangement of FIG.  2 . 
     The bit line [sic] B 1 ″, B 2 ′, B 3 ′, B 4 ′ are constructed analogously, and adjacent bit lines are offset with respect to one another by a length of X″/2, as indicated in FIG. 6, X″ being the distance between two bit line terminals. 
     The reference symbols K 11  to K 44  are the contacts corresponding to the illustration of FIG. 2, and the reference symbols A 11 ″ to A 43 ″ designate interconnect sections which have approximately twice the length in relation to the interconnect sections of the first two embodiments. 
     It is also the case with the third embodiment shown in FIG. 9 that, by virtue of the fact that in each case approximately one quarter of an interconnect section of the first metalization plane M 0  lies next to half of a further interconnect section of the second metalization plane M 1 , the advantage is afforded that the coupling capacitances [lacuna] considerably relative to the planar state, in which all the interconnect sections or of [sic] all the interconnects lie in one metalization plane, [lacuna] a significantly reduced coupling capacitance. 
     In FIG. 9, finally, the reference symbols A-A′ and B-B′ designate sectional lines through the first and second bit lines B 1 ″, B 2 ″, which have been explained above with reference to FIGS. 3 and 4. 
     Although the present invention has been described above using a preferred exemplary embodiment, it is not restricted thereto, but rather can be modified in diverse ways. 
     In particular, the explanation of the embodiments in connection with bit lines of integrated memory circuits using silicon technology is only by way of example. 
     Moreover, the alternating pattern of interconnect sections in the first and second metalization planes can be varied as desired. 
     LIST OF REFERENCE SYMBOLS 
       1  Circuit substrate 
     B 1 -B 4 ; B 1 ′-B 4 ′ Bit lines 
     K 11 -K 44 , K 11 ′-K 49 ′ Contacts 
     A 11 -A 45 , A 11 ′-A 45 ′ 
     A 11 ″-A″-A 43 ″ Interconnect sections 
     C 11 -C 15 , C 21 , C 11 ′-C 15 ′, 
     C 12 ′, C 22 ′, C 13 ′, C 23 ′ Bit line terminals 
     I Insulations plane 
     L Length of the sections 
     M 0 , M 1  First, second metalization 
     plane 
     X, X′, X″ Distance between the bit lines 
     d′ Distance between the bit lines 
     b Width of the bit lines 
     V 12 , V 21 , V 12 ′,V 21 ′ Depressions 
     L 21  Contact Hole