Abstract:
Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second logic gate generates a second signal based on the input signal in response to the selection signal. The third logic gate generates a third signal based on either a return signal or an output signal of the second logic gate.

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATION 
   This application claims priority to Korean Patent Application No. 10-2005-0121498, filed on Dec. 12, 2005, the contents of which are herein incorporated by reference in its entirety. 
   BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present disclosure relates to electronic circuits and, more particularly, to delay cells capable of improving characteristics of an output signal and delay line circuits having the delay cells. 
   2. Discussion of Related Art 
   A delay line circuit introduces a predetermined delay into the transmission of a signal. A delay line circuit generally includes a plurality of delay cells connected in series. A delay line circuit is widely used as a delay-locked loop circuit for generating clock signals synchronized to a reference clock signal. A typical delay-locked loop circuit uses a phase comparator to compare the phase of the reference clock signal with that of the delayed clock signal, and feeds back the comparison result to a delay controller that varies the delay of the delayed clock signal. 
     FIG. 1  is a block diagram of a conventional delay line. Referring to  FIG. 1 , the delay line includes a plurality of delay cells  10  connected in series and having the same operation. The delay line is controlled by a control signal SEL[N−1:0] comprising N bits, where N is equal to the number of delay cells, of which N−1 bits are “0” bits and one-out-of-N bits is “1”. 
     FIG. 2  is a circuit diagram of a delay cell of  FIG. 1 . Referring to  FIG. 2 , the delay cell  10  includes a buffer  21 , a multiplexer  22 , a plurality of terminals IN, PS, RT and OT for inputting and outputting data, and a control terminal SEL receiving a control signal input. 
   The data input to the IN terminal is transmitted to the PS terminal. The multiplexer  22  transmits data according to the data input to the SEL terminal. For example, when logic 0 is input to the SEL terminal, the data input to the RT terminal is transmitted to the OT terminal. When logic 1 is input to the SEL terminal, the data input to the IN terminal is transmitted to the OT terminal through the buffer  21 . 
   The delay T 1  is the time for transmitting the data from the IN terminal to the PS terminal, the delay T 2  is the time for transmitting the data from the PS terminal to the OT terminal, and the delay T 3  is the time for transmitting the data from the RT terminal and the OT terminal. When “0” is input to the SEL terminal, the step delay of the delay cell  10  becomes equal to the sum of the delays T 1  and T 3 . When “1” is input to the SEL terminal and when T 2  is the same as T 3 , the step delay of the delay cell  10  becomes equal to the sum of the delays T 2  and T 1 . 
   In conventional delay line circuits, the improvement of the characteristics of the output signal often requires a complex design or results in undesirably high power consumption. On the other hand, the reduction of power consumption or circuit size often degrades the characteristics of the output signal. Therefore, the need exists for a delay cell for use in a delay line circuit to provide improved performance with reduced power consumption. 
   SUMMARY OF THE INVENTION 
   According to an exemplary embodiment of the present invention, a delay line circuit includes a plurality of delay cells connected in series, wherein each of the delay cells comprises: a first logic gate generating a first signal based on an input signal in response to a selection signal; a second logic gate generating a second signal based on an input signal in response to the selection signal; and a third logic gate generating a third signal based on either a return signal or an output signal of the second logic gate. 
   Each of the delay cells may further comprise a fourth logic gate inverting the output signal of the third logic gate in response to an enable signal. 
   According to an exemplary embodiment of the present invention, a first to an N th  delay cell having a pass terminal of a i th  delay cell that is connected to an input terminal of a (i+1) th  delay cell, and having an output terminal of the (i+1) th  delay cell that is connected to a return terminal of the i th  delay cell, where i is an integer from 1 to N−1 and where N is integer greater than 2, wherein, each of the first to the N th  delay cells comprises a gate, and wherein each of the N th  delay cells transmits a signal based on the input signal to the pass terminal and transmits a signal based on the return signal to the output terminal when the selection signal is at a first logic level, and transmits a signal based on the input signal to the output terminal when the selection signal is at a second logic level. 
   The present invention will become readily apparent to those of ordinary skill in the art when descriptions of exemplary embodiments thereof are read with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a conventional delay line. 
       FIG. 2  is a circuit diagram of a delay cell of  FIG. 1 . 
       FIG. 3  is a circuit diagram of a delay cell according to an exemplary embodiment of the present invention. 
       FIG. 4  is a circuit diagram of a delay cell according to an exemplary embodiment of the present invention. 
       FIG. 5  is a circuit diagram of a delay cell according to an exemplary embodiment of the present invention. 
       FIG. 6  is a circuit diagram of a delay cell according to an exemplary embodiment of the present invention. 
       FIG. 7  is a circuit diagram of a delay line according to an exemplary embodiment of the present invention. 
   

   DESCRIPTION OF EXEMPLARY EMBODIMENTS 
   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to similar or identical elements throughout the description of the figures. 
     FIG. 3  is a circuit diagram of a delay cell  30  according to an exemplary embodiment of the present invention. Referring to  FIG. 3 , the delay cell  30  includes logical NOR gates NR 1 , NR 2 , NR 3 , an inverter IV, terminals IN, PASS, RETURN, OUT for inputting and outputting the data, and a direction-selecting terminal SEL controlling a direction for transmitting the data. When a logic low level signal ‘0’ is input to the direction-selecting terminal SEL, the data input to the input terminal IN is inverted through the NOR gate NR 1  and transmitted to a pass terminal PASS. The data input to a return terminal RETURN is inverted through the NOR gate NR 3  and transmitted to an output terminal OUT. When a logic high level signal ‘1’ is input to the direction-selecting terminal SEL, the data input to the input terminal IN is transmitted to the output terminal OUT through NOR gates NR 2 , NR 3 . In an exemplary embodiment of the present invention, the pass terminal PASS is set to a predetermined value. For example, the pass terminal PASS may be set to 0. 
   The first NOR gate NR 1  NORs the selection signal, which is the input signal to the direction selection terminal SEL, and the input signal, which is the input signal to the input terminal IN. The second NOR gate NR 2  NORs a signal inverting the selection signal, and the input signal. The third NOR gate NR 3  NORs the output signal from the second NOR gate NR 2  and a return signal, which is a signal input to the return terminal RETURN. 
     FIG. 4  is a circuit diagram of the delay cell according to an exemplary embodiment of the present invention. Referring to  FIG. 4 , the delay cell  400  includes NAND gates ND 1 , ND 2 , ND 3 , and the inverter IV, the terminals IN, PASS, RETURN, OUT for inputting and outputting data, and the direction-selecting terminal SEL controlling the direction for transmitting data. When ‘0’ is input to the direction-selecting terminal SEL, the data input to the input terminal IN is inverted through the NAND gate ND 1  and transmitted to the pass terminal PASS, and the data input to the return terminal RETURN is inverted through the NAND gate ND 3  and transmitted to the output terminal OUT. When ‘1’ is input to the direction-selecting terminal SEL, the data input to the input terminal IN is transmitted to the output terminal OUT through the NAND gates ND 2 , ND 3 . In an exemplary embodiment of the present invention, the pass terminal PASS is set to a predetermined value. For example, the pass terminal PASS may be set to 1. 
   The first NAND gate ND 1  NANDs a signal inverting the selection signal, which is the input signal of the direction-selecting terminal SEL, and the input signal, which is the input signal to the input terminal IN. The second NAND gate ND 2  NANDs the selection signal and the input signal. The third NAND gate ND 3  NANDs the output signal from the second NAND gate ND 2  and the return signal, which is an input signal input to the return terminal RETURN. 
     FIG. 5  is a circuit diagram of the delay cell  500  according to an exemplary embodiment of the present invention. Referring to  FIG. 5 , the delay cell  500 , as compared to the delay cell  300  shown in  FIG. 3 , further includes a NOR gate NR 4 , a inversion output terminal OUTB, and an enable terminal OEN. For example, NOR gate NR 4  is a dummy gate equalizing the load condition when the delay cell  500  is connected in a plurality of series. When ‘0’ is input to the enable terminal OEN, the inversion signal of the output signal (i.e., the output terminal OUT signal) of the NOR gate NR 3  is output to the inversion output terminal OUTB. The NOR gate NR 4  NORs the enable signal, which is an input signal to the enable terminal OEN, and an output signal from the third NOR gate NR 3 . When ‘0’ is input to the enable terminal OEN, a signal having a different phase from that of the output terminal OUT signal may be additionally obtained through the inversion output terminal OUTB. 
     FIG. 6  is a circuit diagram of the delay cell  600  according to an exemplary embodiment of the present invention. Referring to  FIG. 6 , the delay cell  600 , as compared to the delay cell  400  of  FIG. 4 , further includes a NAND gate ND 4 ; the inversion output terminal OUTB, and the enable terminal OEN. For example, NAND gate ND 4  is a dummy gate equalizing the load condition when the delay cell  600  is connected in a plurality of series. When ‘1’ is input to the enable terminal OEN, the inversion signal of the output signal (i.e., the output terminal signal) of the NAND gate ND 3  is output to the inversion output terminal OUTB. The NAND gate ND 4  NANDs and outputs the enable signal, which is an input signal to the enable terminal OEN, and the output signal of the third NAND gate ND 3 . Therefore, if ‘1’ is input to the enable terminal OEN, the signal having a different phase from a signal of the output terminal OUT may be obtained through the inversion output terminal OUTB. 
     FIG. 7  is a circuit diagram of the delay line  700  according to an exemplary embodiment of the present invention. The delay line  700  is implemented by connecting N delay cells  70 _ 1  to  70 _N in series. For example, each of the delay cells  70 _ 1  to  70 _N has the same configuration as the delay cells  600  of  FIG. 6 . 
   Each of the delay cells  70 _ 1  to  70 _N transmits or returns the input data in response to the SEL[ ] input to the direction selection terminal. For the purposes of this disclosure, “transmission” means transmitting the signal that is input to the input terminal IN to the pass terminal PASS, and transmitting the signal that is input to the return terminal RETURN to the output terminal OUT. For the purposes of this disclosure, ‘return’ means to transmit the signal input to the input terminal IN to the output terminal OUT. 
   In this exemplary case, every SEL[N−1:3] is 1 and SEL[2:0] is 0. As illustrated by the dotted line in  FIG. 7 , the signal (hereinafter, “input signal”), which is input to the input terminal IN of the first delay cell  70 _ 1 , is output to the output terminal OUT of the first delay cell  70 _ 1  through  8  NAND gates. Since a transmission of a signal occurs at the first to the third delay cells  70 _ 1 ,  70 _ 2 ,  70 _ 3 , and a return of the signal occurs at the fourth delay cell  70 _ 4 , the input signal that goes through the first to the third delay cells  70 _ 1 ,  70 _ 2 ,  70 _ 3  is returned at the fourth delay cell  70 _ 4 , and the returned signal is output through the third to the first delay cells  70 _ 3 ,  70 _ 2 ,  70 _ 1 . The input signal, which is input to the input terminal IN of the first delay cell  70 _ 1 , is output to the output terminal OUT of the first delay cell  70 _ 1  through the NAND gates ND 1  of the first to the third delay cell  70 _ 1 ,  70 _ 2 ,  70 _ 3 , the NAND gates ND 2 , ND 3  of the fourth delay cell, and the NAND gates ND 3  of the third to the first delay cell. 
   In an exemplary embodiment of the present invention, delay cells  70 _ 5  to  70 _N after the fourth tap (the fourth delay cell,  70 _ 4 ) output a set value of 1 or 0 to the pass terminal PASS. Therefore, no level transition occurs at an output signal of the pass terminal PASS. 
   In this exemplary case, every SEL[k−1:0] is 0 and every SEL[N−1:k] is 1. In such case, the input signal to the input terminal IN of the first delay cell  70 _ 1  is output to the output terminal OUT of the first delay cell  70 _ 1  through 2 k NAND gates. Here, the NAND gate ND 1  and the NAND gate ND 3  at each of the delay cells  70 _ 1  to  70 _N are equally driving two NAND gate loads. For example, the third delay cell  70 _ 3 , an output of the NAND gate ND 1  of the third delay cell  70 _ 3  is connected to the two NAND gates ND 1 , ND 2  of the fourth delay cell  70 _ 4 , and an output of the NAND gate ND 3  of the third delay cell  70 _ 3  is connected to the NAND gate ND 4  of the third delay cell  70 _ 3  and the NAND gate ND 3  of the second delay cell  70 _ 2 . 
   According to an exemplary embodiment of the present invention, the input signal is output through an even number of NAND gates, and the output signal maintains the duty cycle of the input signal. In an exemplary embodiment of the present invention, as a level transition does not occur in the delay cells after a k th  delay cell, i.e., a (k+1) th  to an N th  delay cell, power consumption is minimized. 
   When a predetermined signal (for example, 1) is input to the enable terminal OEN of any delay cell, the delay signal may be obtained from the inversion output terminal OUTB of the delay cell. The delay cells, according to an exemplary embodiment of the present invention, may be used as a DLL phase detector. For example, the delay line may comprise the delay cells of  FIG. 6  connected in series. 
   One of ordinary skill in the art can readily appreciate that the above described delay cell can be implemented using NAND gates, NOR gates, or gates that are logically equivalent. In an exemplary embodiment of the present invention, the input signal is output through an even number of gates, the output signal maintains the duty of the input signal, characteristics of the output signal may be improved, and the timing margin may be improved. 
   According to exemplary embodiments of the present invention, the characteristics of an output signal of the delay cell or the delay line circuit, such as for example, the duty characteristic may be improved and the power consumption may be decreased. 
   Although the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings for the purpose of illustration, it is to be understood that the inventive processes and apparatus should not be construed as limited thereby. It will be readily apparent to those of reasonable skill in the art that various modifications to the foregoing exemplary embodiments can be made without departing from the scope of the invention as defined by the appended claims, with equivalents of the claims to be included therein.