Abstract:
A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 99104480, filed on Feb. 11, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a package structure, in particular, to a stacked type semiconductor device package structure. 
     2. Description of Related Art 
     In today&#39;s information society, users all seek electronic products with high speed, high quality and multiple functions. In terms of the product exterior appearance, electronic product designs reveal a trend of light weight, thinness and compactness. Therefore, various semiconductor device package techniques such as stacked-type stacked type semiconductor device package technique are proposed. 
     In the stacked-type semiconductor device package technique, several semiconductor devices are perpendicularly stacked together to form a package structure so that the package density is improved and the dimension of the package is decreased. Furthermore, by using three-dimensional stacking method to decrease the path length of the signal transmission between the semiconductor devices, rate of the signal transmission is improved and the semiconductor devices with different functions can be combined in the same package. 
     A conventional stacked-type semiconductor device package technique stacks chips on a wafer carrier having through silicon vias (TSV) to perform a wafer level package, and cutting off the wafer carrier with a molding compound thereon to form plural individual package units. Each of the individual package units may be connected to an external circuit board through solder balls formed on the bottom surface of the wafer. 
     However, the conventional stacked-type semiconductor device package technique first forms the solder balls on the bottom surface of the wafer, and then directly disposes the wafer carrier with the solder balls on the carrier and embeds the solder balls into an adhesive layer on the carrier. And, after the steps of a wafer level package is completed and the wafer carrier and the carrier are separated, the solder balls on the bottom surface of the wafer carrier are exposed. Therefore, when a solder ball having a larger size is formed on the bottom surface of the wafer carrier, it is difficult to firmly bond the solder ball in large size to the adhesive layer on the carrier, and thus the reliability of the package process is inferior. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a package process capable of effectively preventing an issue of the reliability of the package process due to a bad bonding, which is caused by using a solder ball having a larger size, between the wafer carrier and the carrier. 
     To embody the present invention, a package process is provided as follows. A semiconductor substrate is disposed on a carrier, wherein the semiconductor substrate has a first surface facing the carrier and plural contacts on the first surface. The semiconductor substrate is thinned from a back side of the semiconductor substrate in opposite to the first surface, wherein the thinned semiconductor substrate has a second surface opposite to the first surface. Plural through silicon vias are formed in the thinned semiconductor substrate. The through silicon vias respectively correspond to and connect to the contacts. Plural first pads are formed on the second surface of the semiconductor substrate, wherein the first pads respectively correspond to and connect to the through silicon vias. Plural chips are bonded to the second surface of the semiconductor substrate, wherein the chips respectively electrically connect to the corresponding first pads. A molding compound is formed on the second surface of the semiconductor substrate, wherein the molding compound covers the chips and the first pads. The semiconductor substrate and the carrier are separated, and plural solder balls are formed on the first surface of the semiconductor substrate, wherein the solder balls respectively electrically connect to the corresponding contacts. And, the molding compound and the semiconductor substrate are simultaneously sawed to form a plurality of package units. 
     In one embodiment of the prevent invention, the aforementioned package process further comprises forming a redistribution layer on the first surface of the semiconductor substrate before the semiconductor substrate is disposed on the carrier. A surface of the redistribution layer has plural second pads and the second pads respectively electrically connect to the contacts. Additionally, the aforementioned package process further comprises forming an under bump metallurgy layer on each of the second pads. 
     In one embodiment of the prevent invention, the aforementioned package process further comprises forming a redistribution layer on the first surface of the semiconductor substrate after the semiconductor substrate and the carrier are separated and before the solder balls are formed on the first surface of the semiconductor substrate. A surface of the redistribution layer has plural second pads and the second pads respectively electrically connect to the contacts. Additionally, the aforementioned package process further comprises forming an under bump metallurgy layer on each of the second pads. 
     In one embodiment of the prevent invention, the aforementioned package process further comprises forming an under bump metallurgy layer on each of the first pads. 
     In one embodiment of the prevent invention, the aforementioned step of bonding the chips to the second surface of the semiconductor substrate includes bonding each of the chips to the corresponding first pads through plural conductive bumps by a flip chip bonding technology. 
     In one embodiment of the prevent invention, the aforementioned package process further comprises forming an underfill between each of the chips and the semiconductor substrate after the chips are bonded to the second surface of the semiconductor substrate and before the molding compound is formed on the second surface of the semiconductor substrate, wherein the underfill encapsulates the conductive bumps. 
     As described above, in the embodiment of the prevent invention, the semiconductor substrate first is disposed on the carrier, and the solder balls are formed on the first surface of the semiconductor substrate after the wafer level package is completed and the semiconductor substrate and the carrier are separated. Therefore, the present invention can effectively prevent the bad bonding, which is caused by using a solder ball having a larger size, between the wafer carrier and the carrier, thereby increasing the reliability of the package process. 
     In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIGS. 1A˜1K  illustrate a package process according to an embodiment of the present invention. 
         FIGS. 2A˜2K  illustrate a package process according to another embodiment of the present invention. 
         FIGS. 3A˜3E  illustrate a portion of a package process according to an embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Compared to the conventional stacked-type semiconductor device package technique, in which the solder balls first are formed on the bottom surface of the wafer carrier, and then the wafer carrier with the solder balls is disposed on the carrier such that the solder balls are embedded into the adhesive layer on the carrier, in the invention, the semiconductor substrate is bonded to the carrier, and the solder balls are formed on the first surface of the semiconductor substrate after the wafer level package has completed and the semiconductor substrate and the carrier are separated. In the following, several embodiments are provided to explain the package processes in the present invention. 
       FIGS. 1A˜1K  illustrate a package process according to an embodiment of the present invention. 
     First, referring to  FIG. 1A , a semiconductor substrate  110  is provided. The semiconductor substrate may be a silicon wafer substrate or other semiconductor material substrate. The semiconductor substrate  110  has a first surface  110   a  and a plurality of contacts  112  on the first surface  110   a . An interconnect structure may be fabricated inside the semiconductor substrate  110 , or active or passive devices (not shown) may be embedded into the semiconductor substrate  110  according to a conventional technique. Additionally, the first surface  110   a  of the semiconductor substrate  110  may be covered by a passivation layer  114  for protecting the contacts  112 . 
     It should be noted that the semiconductor substrate  110  of the prevent embodiment is used for a carrier of a wafer level package and may be packaged with one or more chips. However, because it is limited to the size of the drawings, only a portion of the semiconductor substrate  110  is shown in the present embodiment. 
     Then, as shown in  FIG. 1B , in some situations, a redistribution layer  120  may be formed selectively on the first surface  110   a  of the semiconductor substrate  110 , i.e., the passivation layer  114 . A surface of the redistribution layer  120  has plural second pads  122 , and the second pads  122  electrically connect to the contacts  112  on the first surface  110   a  of the semiconductor substrate  110  through internal circuits inside the redistribution layer  120 , respectively, for re-adjusting positions of external contacts of the semiconductor substrate  110 . Herein, an under bump metallurgy layer (UBM layer)  122   a  may be formed on the second pads  112  for increasing an attachment effect between solder balls, which are formed subsequently, and the second pads  122 . 
     The following steps in the embodiment will be explained with a case where the redistribution layer  120  is formed on the surface of the semiconductor substrate  110 . 
     Based on the above, next, as shown in  FIG. 1C , the first surface  110   a  of the semiconductor substrate  110  is faced to a carrier  130  and disposed on the carrier  130 . For example, an adhesion layer  132  is coated on the surface of the carrier  130 , and the semiconductor substrate  110  is fixed on the carrier  130  by the adhesion layer  132 . Herein, the second pads  122  on the surface of the redistribution layer  120  directly contact with the adhesion layer  132 . Meanwhile, the semiconductor substrate  110  is thinned from a back side of the semiconductor substrate  110  in opposite to the first surface  110   a , such that the thinned semiconductor substrate  110  has a second surface  110   b  opposite to the first surface  110   a.    
     After that, as shown in  FIG. 1D , plural through silicon vias (TSVs)  140  are formed in the semiconductor substrate  110 . The through silicon vias  140  respectively correspond to and connect to the contacts  112 , and respectively connect to the second pads  122  through the internal circuits of the redistribution layer  120 . 
     Then, as shown in  FIG. 1E , plural first pads  116  are formed on the second surface  110   b  of the semiconductor substrate  110 . The first pads  116  respectively correspond to and connect to the through silicon vias  140 . Additionally, an under bump metallurgy layer  116   a  may be formed selectively on the first pads  116  for increasing an attachment effect between bumps on chips, which are bonded subsequently, and the first pads  116 . 
     After that, as shown in  FIG. 1F , plural chips  150  are bonded to the second surface  110   b  of the semiconductor substrate  110  such that the chips  150  electrically connect to the first pads  116  on the second surface  110   b . In present embodiment, for example, the chips  150  are bonded to the corresponding first pads  116  through plural conductive bumps  152  on the bottom thereof by a flip chip bonding technique, respectively. 
     Afterwards, as shown in  FIG. 1G , an underfill  160  is formed selectively between the each of the chips  150  and the semiconductor substrate  110  for encapsulating the bumps  152  in the present embodiment. However, the following processes may be performed directly without forming the underfill  160  in another embodiment of the prevent invention. 
     As shown in  FIG. 1H , after the chips  150  are bonded to the semiconductor substrate  110 , a molding compound  170  is formed on the second surface  110   b  of the semiconductor substrate  110  for covering all the chips  150 , the conductive bumps  152  and the first pads  116  on the semiconductor substrate  110 . If the underfill  160  is formed selectively between the chips  150  and the semiconductor substrate  110  before the molding compound  170  is formed in the present embodiment, then the formed molding compound  170  covers the underfill  160 . On the other hand, if the step shown in  FIG. 1G  is not performed in the present embodiment, then the formed molding compound  170  replaces the underfill  160  to directly fill in gaps between the conductive bumps  152 . 
     Then, as shown in  FIG. 1I , the semiconductor substrate  110  and the carrier  130  are separated to expose the second pads  122  on the redistribution layer  120 . And, as shown in  FIG. 1J , plural solder balls  180  are formed on the second pads  122  of the redistribution layer  120  for electrically connecting to the corresponding contacts  112  through the redistribution layer  120 , respectively, after the semiconductor substrate  110  and the carrier  130  are separated. 
     After that, as shown  FIG. 1K , a singulation process is executed. That is, the molding compound  170  and the semiconductor substrate  110  are simultaneously sawed to form a plurality of package units  102 . Because the molding compound  170  and the semiconductor substrate  110  are simultaneously sawed, a side  179  of the molding compound  170  is aligned to a side  119  of the semiconductor substrate  110 , and the chips  150  are encapsulated inside the molding compound  170 . 
     As described above, in the embodiment, the semiconductor substrate  110  first is disposed on the carrier  130 , and the solder balls  180  are formed on the first surface  110   a  of the semiconductor substrate  110  after the steps of the wafer level package, shown in  FIGS. 1D˜1I , have completed. Therefore, the present embodiment does not need to consider the issue of the bad bonding, which is caused by fabricating the solder ball  180  having a larger size on the bottom of the semiconductor substrate  110 , between the semiconductor substrate  110  and the carrier  130 , thereby increasing the reliability and the selectivity of the package process. 
     In the foregoing embodiment, the redistribution layer is formed on the semiconductor substrate before the semiconductor substrate is disposed on the carrier. However, the invention is not limited thereto. For example, in another embodiment of the prevent invention, the redistribution layer may be formed on the semiconductor substrate after the wafer level package has completed and the semiconductor substrate and the carrier are separated. This would be illustrated in the following embodiment. 
       FIGS. 2A˜2K  illustrate a package process according to another embodiment of the present invention. 
     First, referring to  FIG. 2A , a semiconductor substrate  210  is provided. The semiconductor substrate may be a silicon wafer substrate or other semiconductor material substrate. The semiconductor substrate  210  has a first surface  210   a  and a plurality of contacts  212  on the first surface  210   a . An interconnect structure may be fabricated inside the semiconductor substrate  210 , or active or passive devices (not shown) may be embedded into the semiconductor substrate  210  according to a conventional technique. Additionally, the first surface  210   a  of the semiconductor substrate  210  may be covered by a passivation layer  214  for protecting the contacts  212 . 
     It should be noted that the semiconductor substrate  210  of the prevent embodiment is used for a carrier of a wafer level package and is packaged with one or more chips. However, because it is limited to the size of the drawings, only a portion of the semiconductor substrate  210  is shown in the present embodiment. 
     After that, as shown in  FIG. 2B , the first surface  210   a  of the semiconductor substrate  210  is faced to a carrier  230  and disposed on the carrier  230 . For example, an adhesion layer  232  is coated on the surface of the carrier  230 , and the semiconductor substrate  210  is fixed on the carrier  230  by the adhesion layer  232 . Herein, the contacts  212  on the first surface  210   a  of the semiconductor substrate  210  directly contact with the adhesion layer  232 . Meanwhile, the semiconductor substrate  210  is thinned from a back side of the semiconductor substrate  210  in opposite to the first surface  210   a , such that the thinned semiconductor substrate  210  has a second surface  210   b  opposite to the first surface  210   a.    
     After that, as shown in  FIG. 2C , plural through silicon vias  240  are formed in the semiconductor substrate  210 . The through silicon vias  240  respectively correspond to and connect to the contacts  212 . 
     Then, as shown in  FIG. 2D , plural first pads  216  are formed on the second surface  210   b  of the semiconductor substrate  210 . The first pads  216  respectively correspond to and connect to the through silicon vias  240 . Additionally, an under bump metallurgy layer  216   a  may be formed selectively on the first pads  216  for increasing an attachment effect between bumps on chips, which are bonded subsequently, and the first pads  216 . 
     After that, as shown in  FIG. 2E , plural chips  250  are bonded to the second surface  210   b  of the semiconductor substrate  210  such that the chips  250  electrically connect to the first pads  216  on the second surface  210   b . In present embodiment, for example, the chips  250  are bonded to the corresponding first pads  216  through plural conductive bumps  252  on the bottom thereof by a flip chip bonding technique, respectively. 
     Afterwards, as shown in  FIG. 2F , an underfill  260  is formed selectively between the each of the chips  250  and the semiconductor substrate  210  for encapsulating the bumps  252  in the present embodiment. However, the following processes may be executed directly without forming the underfill  160  in another embodiment of the prevent invention. 
     As shown in  FIG. 2G , after the chips  250  are bonded to the semiconductor substrate  210 , a molding compound  270  is formed on the second surface  210   b  of the semiconductor substrate  210  for covering the chips  250 , the conductive bumps  252  and the first pads  216 . If the underfill  260  is formed selectively between the chips  250  and the semiconductor substrate  210  before the molding compound  270  is formed in the present embodiment, then the formed molding compound  270  covers the underfill  260 . On the other hand, if the step shown in  FIG. 2F  is not executed in the present embodiment, then the formed molding compound  270  replaces the underfill  260  to directly fill in gaps between the conductive bumps  252 . 
     Then, as shown in  FIG. 2H , the semiconductor substrate  210  and the carrier  230  are separated to expose the contacts  212  on the first surface  210   a  of the semiconductor substrate  210 . And, as shown in  FIG. 2I , in some situations, a redistribution layer  220  may be formed selectively on the first surface  210   a  of the semiconductor substrate  210 , i.e., the passivation layer  214 . A surface of the redistribution layer  220  has plural second pads  222 , and the second pads  222  electrically connect to the contacts  212  on the first surface  210   a  of the semiconductor substrate  210  through internal circuits of the redistribution layer  220 , respectively, for re-adjusting positions of external contacts of the semiconductor substrate  210 . Herein, an under bump metallurgy layer  222   a  may be formed on the second pads  222  for increasing an attachment effect between solder balls which are formed subsequently and the second pads  222 . 
     The following steps in the embodiment will be explained with a case where the redistribution layer  220  is formed on the surface of the semiconductor substrate  210 . 
     Then, as shown in  FIG. 2J , plural solder balls  280  are formed on the second pads  222  of the redistribution layer  220  for electrically connecting to the corresponding contacts  212  through the redistribution layer  220 , respectively, after the semiconductor substrate  210  and the carrier  230  are separated. 
     After that, as shown  FIG. 2K , a singulation process is executed. That is, the molding compound  270  and the semiconductor substrate  210  are simultaneously sawed to form a plurality of package units  202 . Because the molding compound  270  and the semiconductor substrate  210  are simultaneously sawed, a side  279  of the molding compound  270  is aligned to a side  219  of the semiconductor substrate  210 , and the chips  250  are encapsulated inside the molding compound  270 . 
     As described above, in the present embodiment, the semiconductor substrate  210  first is disposed on the carrier  230 , and then the solder balls  280  are formed on the first surface  210   a  of the semiconductor substrate  210  after the steps of the wafer level package, shown in  FIGS. 2C˜2I , have completed. Therefore, the present embodiment does not need to consider the issue of the bad bonding, which is caused by fabricating the solder balls  280  having a larger size on the bottom of the semiconductor substrate  210 , between the semiconductor substrate  210  and the carrier  230 , thereby increasing the reliability and the selectivity of the package process. On the other hand, compared to the foregoing embodiment, the redistribution layer is formed selectively on the semiconductor substrate after the wafer level package has completed and the semiconductor substrate and the carrier are separated in the present embodiment. 
     In the foregoing embodiments, the semiconductor substrate first is thinned, and then plural through silicon vias are formed in the semiconductor substrate. However, in another embodiment of the present invention, conductive vias first are formed in the semiconductor substrate and then the semiconductor substrate is thinned, such that conductive vias are exposed from the semiconductor substrate to form a plurality of through silicon vias. 
       FIGS. 3A˜3E  illustrate a portion of a package process according to an embodiment of the present invention. 
     First, referring to  FIG. 3A , a semiconductor substrate  310  is provided. The semiconductor substrate may be a silicon wafer substrate or other semiconductor material substrate. The semiconductor substrate  310  has a first surface  310   a  and plurality of contacts  312  on the first surface  310   a . The semiconductor substrate  310  has a plurality of conductive vias  342  inside, and the conductive vias  342  respectively correspond to and connect to the contacts  312 . An interconnect structure may be fabricated inside the semiconductor substrate  310 , or active or passive devices (not shown) may be embedded into the semiconductor substrate  310  according to a conventional technique. Additionally, the first surface  310   a  of the semiconductor substrate  310  may be covered by a passivation layer  314  for protecting the contacts  312 . 
     It should be noted that the semiconductor substrate  310  of the prevent embodiment is used for a carrier of a wafer level package and is packaged with one or more chips. However, because it is limited to the size of the drawings, only a portion of the semiconductor substrate  310  is shown in the present embodiment. 
     Then, as shown in  FIG. 3B , a redistribution layer  320  may be formed on the first surface  310   a  of the semiconductor substrate  310 , i.e., the passivation layer  314 , selectively. A surface of the redistribution layer  320  has plural pads  322 , and the pads  322  electrically connect to the contacts  312  on the first surface  310   a  of the semiconductor substrate  310  through internal circuits of the redistribution layer  320 , respectively, for re-adjusting positions of external contacts of the semiconductor substrate  310 . Herein, an under bump metallurgy layer  322   a  may be formed on the pads  322  for increasing an attachment effect between solder balls, which are formed subsequently, and the pads  322 . 
     The following steps in the embodiment will be explained with a case where the redistribution layer  320  is formed on the surface of the semiconductor substrate  310 . 
     Based on the above, next, as shown in  FIG. 3C , the first surface  310   a  of the semiconductor substrate  310  is faced to a carrier  330  and disposed on the carrier  330 . For example, an adhesion layer  332  is coated on the surface of the carrier  330 , and the semiconductor substrate  310  is fixed on the carrier  330  by the adhesion layer  332 . Herein, the pads  322  on the redistribution layer  320  directly contact with the adhesion layer  332 . 
     And, as shown in  FIG. 3D , the semiconductor substrate  310  is thinned from a back side of the semiconductor substrate  310  in opposite to the first surface  310   a , wherein the thinned semiconductor substrate  310  has a second surface  310   b  opposite to the first surface  310   a  and a terminal  342   a  of each of the conductive vias  342  protrudes from the second surface  310   b  to form a through silicon via  340 . The through silicon vias  340  respectively connect to the pads  322  through internal circuits of the redistribution layer  320 . 
     Then, as shown in  FIG. 3E , a plurality of chips  350  are bonded to the exposed through silicon vias  340 . In present embodiment, for example, the chips  350  are bonded to the corresponding through silicon vias  340  through plural conductive bumps  352  on the bottom thereof by a flip chip bonding technique, respectively. For example, the conductive bumps  352  connect to the corresponding through silicon vias  340  through solder  370 . The conductive bumps  352  may be cylindrical bumps as shown in  FIG. 1D  or other types. 
     Afterwards, the steps as shown in  FIG. 1G˜1K  are executed to form the package units  102  as shown in  FIG. 1K . The technology details have been described in the embodiments described above so the details will not be described here again. 
     Additionally, referring to  FIG. 2A˜2K , besides the technology solution in which the redistribution layer is formed on the semiconductor substrate before the semiconductor substrate is disposed on the carrier, the redistribution layer may formed on the semiconductor substrate with the foregoing method of fabricating the through silicon vias after the wafer level package has completed and the semiconductor substrate and the carrier are separated in another embodiment of the present invention. 
     Although the invention has been described in considerable detail with reference to certain preferred embodiments thereof, the disclosure is not for limiting the scope of the invention. Persons having ordinary skill in the art may make various modifications and changes without departing from the scope and spirit of the invention. Therefore, the scope of the appended claims should not be limited to the description of the preferred embodiments described above.