Abstract:
Embodiments relate to a method of manufacturing a semiconductor device that may simplify a manufacturing process and may reduce process costs. According to embodiments, the method may include simultaneously forming a first gate of a first device area and a second gate of a second device area, patterning a PMD layer to form a first contact hole exposing the first gate, depositing and planarizing a high dielectric constant material and first and second metallic materials on the semiconductor substrate to expose PMD layer, forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer to form a second contact hole exposing the second gate, and depositing a third metallic material on the semiconductor substrate and planarizing it such that the PMD layer is exposed, thereby forming a contact in the second contact hole.

Description:
[0001]    The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2005-0133397 (filed on Dec. 29, 2005), which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    Semiconductor devices may be divided into various categories, including memory devices and non-memory devices. In memory devices, information may be stored, and in non-memory devices, information may not be stored. 
         [0003]    Memory devices may be generally divided into volatile memory devices, in which recorded information may be erased and new information may be stored, and non-volatile memory devices, in which information recorded once may be permanently stored. 
         [0004]    Volatile memory devices may include RAM (Random Access Memory), which may allow information to be written and read. Non-volatile memory may include ROM (Read Only Memory), EPROM (Erasable Programmable ROM), and EEPROM (Electrically Erasable Programmable ROM), which may allow information to be read. 
         [0005]    Memory and non-memory devices may be simultaneously designed in accordance with a various known layouts on a semiconductor substrate. 
         [0006]      FIG. 1  is an example sectional diagram showing a semiconductor device having memory and non-memory devices. 
         [0007]    Referring to  FIG. 1 , memory and non-memory devices  1  and  2  may be formed on a semiconductor substrate  3 . 
         [0008]    Memory device  1  may include gate insulating layer  6   a,  floating gate  7 , interlayer dielectric layer  8 , and control gate  9 . These elements may be stacked. Source and drain areas  4   a  and  4   b  may be formed at both side areas of control gate  9 . 
         [0009]    Interlayer dielectric layer  8  may be an ONO (Oxide-Nitride-Oxide) layer. Floating gate  7  may be an area in which information is written. Gate insulating layer  6   a  may be formed to isolate semiconductor substrate  3  and floating gate  7 . Control gate  9  may be formed to control floating gate  7 , for example to write or delete information. Interlayer dielectric layer  8  may be formed to isolate floating gate  7  and control gate  9 . 
         [0010]    Spacer  10   a  may be formed at sides of gate insulating layer  6   a,  floating gate  7 , interlayer dielectric layer  8  and control gate  9 . 
         [0011]    In non-memory device  2 , gate insulating layer  6   b  and general gate  9   a  may be stacked. Source and drain areas  5   a  and  5   b  may be formed at both side areas of general gate  9   a.  General gate  9   a  may conduct and cut off a channel area between source and drain areas  5   a  and  5   b  such that signals may be transmitted therebetween. 
         [0012]    Further, gate insulating layer  6   b  may be formed to isolate semiconductor substrate  3  and general gate  9   a.  Spacer  10   b  may be formed at sides of gate insulating layer  6   b  and general gate  9   a.    
         [0013]    PMD (Pre-Metallic Dielectric) layer  12  may be formed on semiconductor substrate  3 . PMD layer  12  may include contact holes for electrical connections to general gate  9   a,  control gate  9 , source areas  4   a  and  5   a,  and drain areas  4   b  and  5   b.  Metal interconnection  13  may be formed through each of the contact holes, and tungsten (W)  11  may be filled in the contact hole. 
         [0014]    Control gate  9  may include a material substantially identical to a material forming general gate  9   a.    
         [0015]    Therefore, control gate  9  and general gate  9   a  may be formed through a one-time mask process in a semiconductor process. 
         [0016]    However, since a step difference may exist between control gate  9  and general gate  9   a , focuses for exposure may be different from each other when performing an exposure process, for example to form a photoresist pattern. For this reason, it may not be possible to simultaneously form control gate  9  and general gate  9   a  through a one-time mask process. 
         [0017]    For example, since control gate  9  may be formed on floating gate  7  and interlayer dielectric layer  8 , control gate  9  may be positioned higher than general gate  9   a  by a height of floating gate  7  and interlayer dielectric layer  8 . 
         [0018]    Accordingly, a step difference may be formed as high as floating gate  7  and interlayer dielectric layer  8  between control gate  9  and general gate  9   a.    
         [0019]    Thus, if a focus for exposure is adjusted on a photoresist on interlayer dielectric layer  8  to deposit the photoresist on semiconductor substrate  3  including interlayer dielectric layer  8  and then expose the photoresist, the focus may not be properly adjusted on the photoresist in an area in which general gate  9   a  will be formed. 
         [0020]    If an exposure is then performed, an exact photoresist pattern may be formed on interlayer dielectric layer  8 , while the precise photoresist pattern may not formed on an area in which general gate  9   a  will be formed. 
         [0021]    Thus, since a general gate having an inexact CD (Critical Dimension) may be formed where patterning is performed using an inexact photoresist as a mask, an inexact operation may be accomplished by such a general gate. 
         [0022]    Therefore, it may be necessary for a control gate and a general gate, which may have the same material, to be formed through a two-time mask process and not through a one-time mask process. Such a process may be complicated, expensive, and time consuming. 
       SUMMARY 
       [0023]    Embodiments relate to a semiconductor device. Embodiments relate to a method of manufacturing a semiconductor device that may simplify a process and reduce process costs. 
         [0024]    Embodiments relate to a method of manufacturing a semiconductor device, in which a general gate of a non-memory device and a floating gate of a memory device may be simultaneously formed so that a process may be simplified and process costs can be reduced. 
         [0025]    Embodiments relate to a method of manufacturing a semiconductor device, in which a control gate may include a metallic material so that the performance of the control gate may be enhanced. 
         [0026]    According to embodiments, a method of manufacturing a semiconductor device in which first and second areas may be defined on a semiconductor substrate, and first and second devices may respectively be formed in the first and second areas, may include simultaneously forming a first gate of the first device area and a second gate of the second device area, depositing a PMD layer on the semiconductor substrate and then patterning it, thereby forming a first contact hole such that the first gate may be exposed, depositing a high dielectric constant material and first and second metallic materials on the semiconductor substrate and then planarizing them such that the PMD layer may be exposed, thereby forming an insulating layer, a metal layer and a third gate in the first contact hole, patterning the PMD layer, thereby forming a second contact hole such that the second gate may be exposed, and depositing a third metallic material on the semiconductor substrate and then planarizing it such that the PMD layer may be exposed, thereby forming a contact in the second contact hole. 
         [0027]    According to embodiments, a method of manufacturing a semiconductor device in which first and second areas may be defined on a semiconductor substrate, and first and second devices may be respectively formed in the first and second areas, may include simultaneously forming a first gate of the first device area and a second gate of the second device area, depositing a first PMD layer on the semiconductor substrate and then patterning it, thereby forming a first contact hole such that the first gate may be exposed, depositing a high dielectric constant material and first and second metallic materials on the semiconductor substrate and then planarizing them such that the first PMD layer may be exposed, thereby forming an insulating layer, a metal layer and a third gate in the first contact hole, depositing a second PMD layer on the semiconductor substrate and then patterning it, thereby forming a second contact hole such that second and third gates may be exposed, and depositing a third metallic material on the semiconductor substrate and then planarizing it such that the second PMD layer may be exposed, thereby forming a contact in the second contact hole. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0028]      FIG. 1  is an example sectional diagram illustrating a semiconductor device having memory and non-memory devices; 
           [0029]      FIGS. 2   a  to  2   i  are example sectional diagrams illustrating a semiconductor and a process of manufacturing a semiconductor according to embodiments; and 
           [0030]      FIGS. 3   a  to  3   h  are example sectional diagrams illustrating a semiconductor and a process of manufacturing a semiconductor according to embodiments. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0031]    Referring to  FIG. 2   a,  semiconductor substrate  21  may include areas in which memory and non-memory devices will be formed. A plurality of memory and non-memory devices may be formed on semiconductor substrate  21 . 
         [0032]    Memory devices, non-memory devices, and memory and non-memory devices may be isolated by a field oxide layer (not shown). Thus, a region of each of the devices may be defined by the field oxide layer. 
         [0033]    General gate (as distinguished from floating and control gates)  23   b  and first source and drain regions  26   a  and  26   b  may be formed in a non-memory device area on semiconductor substrate  21 . Further, floating gate  23   a  and second source and drain areas  25   a  and  25   b  may be formed in the memory device area. 
         [0034]    First gate oxide layer  22   b  may be formed between general gate  23   b  and semiconductor substrate  21 . First gate oxide layer  22   b  may provide isolation between general gate  23   b  in substrate  21 . Second oxide layer  22   a  may be formed between the floating gate  23   a  and semiconductor substrate  21 , and may provide isolation therebetween. 
         [0035]    First spacers  24   b  may be formed at both side surfaces of first gate oxide layer  22   b  and general gate  23   b,  and second spacers  24   a  may be formed at both side surfaces of second gate oxide layer  22   a  and the floating gate  23   a.    
         [0036]    General gate  23   b  may include a material substantially identical to a material used to form floating gate  23   a.  General gate  23   b  and floating gate  23   a  may be simultaneously formed through a one-time mask process. 
         [0037]    In embodiments, a gate oxide layer and a poly-silicon layer may be deposited on the semiconductor substrate, and a photoresist may be coated on the poly-silicon. A photoresist pattern may then be formed, for example through an exposure and development process. A patterning process may then be performed, for example using the photoresist pattern as a mask. General gate  23   b  and floating gate  23   a  may thereby respectively be formed in the non-memory and memory device areas. 
         [0038]    First source and drain areas  26   a  and  26   b  of the non-memory device may be formed through an ion implantation process, for example by using general gate  23   b  and first spacers  24   b  as a mask. 
         [0039]    Second source and drain regions  25   a  and  25   b  of the memory device may be formed through an ion implantation process, for example by using floating gate  23   a  and second spacers  24   a  as a mask. 
         [0040]    Referring to  FIG. 2   b,  a PMD layer  27  may be deposited on semiconductor substrate  21  having general gate  23   b  and floating gate  23   a.    
         [0041]    Referring to  FIG. 2   c,  first contact hole  28  may be formed by patterning PMD layer  27  such that floating gate  23   a  and second spacers  24   a  of the memory device may be exposed. According to embodiments, first contact hole  28  may be formed through an RIE process. 
         [0042]    Referring to  FIG. 2   d,  high dielectric constant (high k) material (e.g., Al 2 O 3  or the like)  29  and barrier metal (e.g., Ti, TiN or the like)  30  may be sequentially deposited on semiconductor substrate  21 . 
         [0043]    Referring to  FIG. 2   e,  metallic material  31 ′ such as tungsten (W) may be deposited on barrier metal  30 . 
         [0044]    Referring to  FIG. 2   f,  metallic material  31 ′ may be planarized, for example through a CMP process. PMD layer  27  may thus be exposed. Accordingly, metallic material  31 ′ may be formed only in first contact hole  28 , and control gate  31  may be formed by metallic material  31 ′ formed in first contact hole  28 . 
         [0045]    High dielectric constant material  29  and barrier metal  30  may be stacked on side and bottom surfaces of first contact hole  28 . Control gate  31  may be formed on barrier metal  30 . High dielectric constant material  29  may induce higher capacitance so that more information may be recorded. Barrier metal  30  may be formed, and may increase the adhesion of control gate  31 . 
         [0046]    In general, a control gate may include poly-silicon. According to embodiments, control gate  31  may include a metallic material such as tungsten. Current loss may thereby be minimized since a resistance of the metallic material may be lower than that of the poly-silicon. In embodiments, exact operational control may be possible and a performance of control gate  31  may be enhanced. 
         [0047]    Referring to  FIG. 2   g,  PMD layer  27  may be patterned through an RIE process, and second contact holes  33  and  34  may thus be formed. First source and drain areas  26   a  and  26   b  and general gate  23   b  of the non-memory device are may be respectively exposed through second contact holes  33  and  34 . Third contact holes  32  may also be formed, through which second source and drain areas  25   a  and  25   b  may be respectively exposed. 
         [0048]    Referring to  FIG. 2   h,  a metallic material such as tungsten may be deposited on PMD layer  27  having the second and third contact holes  32 ,  33  and  34 , and then planarized, for example through a CMP process. PMD layer  27  may thus be exposed, thereby forming contacts  36  in the second and third contact holes  32 ,  33  and  34 . Contact  36  may include a metallic material (e.g., tungsten) identical to or different from a material forming barrier metal  30 . 
         [0049]    Referring to  FIG. 2   i,  a metallic material such as Al or Cu may be deposited on PMD layer  27  and may be patterned, thereby forming metal interconnections  38  on contacts  36 . 
         [0050]    According to embodiments, a plurality of memory and non-memory devices  35  and  37  may be simultaneously formed on semiconductor substrate  21 . 
         [0051]    According to embodiments, general gate  23   b  of non-memory device  37  and floating gate  23   a  of memory device  35  may be simultaneously formed. Hence, a manufacturing process may be simplified, and costs may be reduced. 
         [0052]    In addition, according to embodiments, control gate  31  may include a metallic material, which may increase conductivity, for example as compared with related art techniques. Hence, and exact operation may be controlled. 
         [0053]      FIGS. 3   a  to  3   h  are example sectional diagrams illustrating a semiconductor and a process of manufacturing a semiconductor according to embodiments. 
         [0054]      FIGS. 3   a  to  3   f  illustrate the same components as to  FIGS. 2   a  to  2   f,  and will accordingly be only briefly described for convenience of explanation. 
         [0055]    Referring to  FIG. 3   a,  general gate  23   b  and first source and drain areas  26   a  and  26   b  may be formed in a non-memory device area of semiconductor substrate  21 . Floating gate  23   a  and second source and drain areas  25   a  and  25   b  may be formed in a memory device area of semiconductor substrate  21 . First and second gate insulating layers  22   a  and  22   b  may be formed between respective gates  23   a  and  23   b  and semiconductor substrate  21 , and first and second spacers  24   a  and  24   b  may be formed on side surfaces of respective gates  23   a  and  23   b.    
         [0056]    Referring to  FIG. 3   b,  first PMD film  27  may be deposited on semiconductor substrate  21 . Referring to  FIG. 3   c,  first contact hole  28  may be formed, for example through an RIE process such that floating gate  23   a  and second spacer  24   a  in the memory device area may be exposed. 
         [0057]    Referring to  FIG. 3   b,  high dielectric constant material  29  such as Al 2 O 3  and barrier metal  30  such as Ti or TiN may be sequentially deposited. 
         [0058]    Referring to  FIG. 3   e,  metallic material  31 ′ such as tungsten may be deposited on barrier metal  30  and planarized through a CMP process. 
         [0059]    Referring to  FIG. 3   f,  control gate  31  in first contact hole  28  may thus be formed. 
         [0060]    Referring to  FIG. 3   g,  after forming control gate  31 , second PMD layer  41  may be deposited on semiconductor substrate  21 . Second contact holes  43  may be formed such that respective gates  23   b  and  31 , first and second source areas  25   a  and  26   a,  and first and second drain areas  25   b  and  26   b  may be exposed. Thus second contact holes  43  may be formed in the non-memory device area such that general gate  23   b  and first source and drain areas  26   a  and  26   b  may be exposed, and second contact holes  43  may be formed in the memory device area such that floating gate  23   a  and second source and drain areas  25   a  and  25   b  may be exposed. 
         [0061]    Second PMD film  41  may include a dielectric material identical to or different from a material used to form first PMD film  27 . 
         [0062]    Referring to  FIG. 3   h,  a metallic material such as tungsten may be deposited on semiconductor substrate  21  and planarized, for example through a CMP process. Contacts  45  may thus be formed in contact holes  43 . A metallic material such as Al or Cu may be deposited on contacts  45  and then patterned. Metal interconnections may thus be formed on contacts  45 . Contacts  45  may include a metallic material (e.g., tungsten) identical to barrier metal  30  or a metallic material different therefrom. 
         [0063]    Accordingly, a plurality of memory and non-memory devices  50  and  55  may be simultaneously formed on semiconductor substrate  21 . 
         [0064]    According to embodiments, general gate  23   b  of the non-memory device  55  and floating gate  23   a  of the memory device  50  may be simultaneously formed, and a manufacturing process may thus be less complicated and less expensive. 
         [0065]    Further, according to embodiments, control gate  31  may include a metallic material, which may increase conductivity, for example as compared to related are techniques. An exact operation may therefore be controlled. 
         [0066]    Furthermore, in embodiments, second PMD layer  41  may be added. Hence, control gate  31  may not exposed directly to the outside, and an occurrence of a short circuit due to metal interconnections intersecting each other may be prevented. 
         [0067]    According to embodiments, a general gate of a non-memory device and a floating gate of a memory device may be simultaneously formed, and a process can be simplified and process costs may be reduced. 
         [0068]    According to embodiments, a control gate  31  may include a metallic material, and may have a high conductivity. Hence, an operation may be better controlled. 
         [0069]    According to embodiments, a second PMD layer may also be formed. A control gate may not be exposed directly to the outside. A short circuit due to metal interconnections intersecting each other may be therefore be prevented. 
         [0070]    According to embodiments, an interlayer dielectric layer may include a high dielectric constant material such as Al 2 O 3  rather than an existing ONO layer. Accordingly, a process may be simplified and costs may be reduced. For example, since an ONO layer may be prepared as three layers, three-time deposition, one-time exposure, RIR, and wet etching processes may be added, and may cause a process to be very complicated. On the contrary, according to embodiments, an interlayer dielectric layer may simply include a high dielectric constant material such as Al 2 O 3 , and a process may be simplified and costs may be reduced. 
         [0071]    It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims. It is also understood that when a layer is referred to as being “on” or “over” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.