Abstract:
A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to a clock generator, and more specifically to a programmable phase shift clock generator. 
     2. Description of Related Art 
     Clock synthesizers are ubiquitous, taking on many forms ranging from phase-locked loops to delay line loops. The general theme in clock synthesis is the reconstitution of a clock signal which is a harmonic or integer multiple of a fundamental or &#34;base&#34; input clock. Synthesizing non-integer multiple frequencies however, poses a more difficult situation. 
     Known problems with phase-locked loop systems include falling out-of-lock and excessive lock times. Known problems with delay line loop systems include open loop variations in delay elements and delay quantization. 
     With specific reference to delay line loop systems, synthesized waveforms generally rely on input clock edges and fixed delays to approximate &#34;quadrature&#34; clocks (i.e. clocks shifted mid-phase, usually 90 degrees) to reconstitute clock signals of higher frequency than the fundamental or &#34;base&#34; input clock. Consequently, a certain amount of ambiguity is induced into the quadrature clocks based on, inter alia, variations in delay elements and delay quantization. 
     It can be seen from the foregoing therefore, that there is a need for systems and methods of clock synthesis that can accurately parse and dismantle an input clock in order to accurately generate ancillary clock signals of varying phase and frequency. 
     SUMMARY OF THE INVENTION 
     To overcome the limitations of the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a programmable phase shift clock generator having a phase comparator for generating a difference between an input clock signal and a feedback signal, an up-down counter responsive to the phase comparator, for generating an n-bit count, a ring oscillator responsive to the up-down counter, for generating a loop clock signal as an output and as feedback to the phase comparator, and an adjustable delay line to provide a phase shifted clock signal from the loop clock output signal. 
     A feature of the present invention is providing a digital signature of an input clock for further utilization in generating ancillary clock signals. 
     Another feature of the present invention is the ability to precisely adjust the duty cycle of an output clock independent of the input clock frequency. 
     These and various other objects, features, and advantages of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and forming a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying descriptive matter, in which there is illustrated and described a specific example of a programmable phase shift clock generator practiced in accordance with the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a preferred embodiment for a clock generator/multiplier in combination with an adjustable delay line to form a programmable phase shift clock generator practiced in accordance the principles of the present invention; 
     FIG. 2 is a block diagram of a preferred embodiment for the programmable phase shift clock generator practiced in accordance with the principles of the present invention; 
     FIG. 3 is a block diagram of a specific implementation for the programmable phase shift clock generator depicted in FIG. 2; 
     FIG. 4 is a schematic diagram of the adjustable delay line depicted in FIGS. 1-3; 
     FIG. 5 is a schematic diagram of a clock doubling circuit practiced in accordance with the principles of the present invention; 
     FIG. 6 is a timing diagram of signals generated in the diagrams of FIGS. 3 and 5; 
     FIG. 7 is a timing diagram of signals generated in the diagrams of FIGS. 2 and 5; and, 
     FIG. 8 is a block diagram of an alternative preferred embodiment for the programmable phase shift clock generator practiced in accordance with the principles of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In the following description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In order not to obscure the disclosure with structural details which will be readily apparent to those skilled in the art having the benefit of the description herein, the structure, control, and arrangement of conventional circuits have been illustrated in the drawings by readily understandable block representations and schematic diagrams, showing and describing details that are pertinent to the present invention. Thus, the block diagram illustrations in the figures do not necessarily represent the physical arrangement of the exemplary system, but are primarily intended to illustrate the major structural components in a convenient functional grouping, wherein the present invention may be more readily understood. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. 
     Referring to FIG. 1, a block diagram is depicted of the preferred embodiment for a delay line loop clock generator/multiplier 10 in combination with an adjustable delay line 16&#39; and an optional arithmetic divider 24 to form a programmable phase shift clock generator practiced in accordance with the principles of the present invention. The clock multiplier 10 includes a phase comparator 12 to compare an input clock signal to a feedback signal and to generate up/down error pulses in response thereto. The up/down error pulses drive an up/down counter 14 which produces a five bit error count (Delay --  adj&lt;4:0&gt;). The five bit error count (Delay --  adj&lt;4:0&gt;) drives a ring oscillator 20 formed by an adjustable delay line 16 (described in more detail hereinbelow) having an inverter 18 coupled between its output and input. The output of the ring oscillator 20 provides a loop clock signal which is further processed as discussed in more detail hereinbelow. The loop clock signal is also fed back to the phase comparator 12 for comparison with the input clock. An optional clock divider 22 maybe inserted between the loop clock signal and the phase comparator 12 to scale the loop clock frequency by a factor of &#34;n&#34; wherein &#34;n&#34; is the divisor of the divider 22. Those skilled in the art will recognize many well known expedients for the phase comparator 12, up/down counter 14, ring oscillator 20, and clock divider 22, without departing from the scope of the present invention. 
     Reference is now made to FIGS. 2 and 3 which depict block diagrams of the preferred embodiments for the programmable phase shift clock generator practiced in accordance with the principles of the present invention. FIG. 2 is a general case while FIG. 3 depicts a specific case. In FIG. 3, delay δ2 is generated by adjustable delay line 16&#34; which is one-half the delay δ1 generated by adjustable delay line 16 in FIG. 1. It should be noted in the specific example of FIG. 3 however, that adjustable delay line 16&#34; has only four data bits ADJ&lt;3:0&gt; to set the delay and that the four most significant bits (Delay --  adj &lt;4:1&gt;) from up/down counter 14 are coupled thereto having the effect of dividing the count by a factor of two. 
     In the general case of FIG. 2, an arithmetic divider 24 is interposed between the output of counter 14 (Delay --  adj &lt;4:0&gt;) and the adjustment input of adjustable delay line 16&#39;. The arithmetic divider 24 having a programmable divisor of &#34;n&#34; has the effect of producing a variable delay δ3 in delay line 16&#39;. Expressed simply, the loop clock is shifted by 180°/n wherein &#34;n&#34; is the programmable divisor of arithmetic divider 24. Alternatively as depicted in FIG. 8, the loop clock output could be inverted 180° before coupling it to delay line 16&#39; thus giving the effect of generating a shifted clock shifted by (360°-180°/n). 
     Before moving along to the explanatory discussion below on waveforms generated by the circuits in FIGS. 1-3, reference is made to FIG. 4 which depicts a more detailed block diagram of the preferred embodiment for the adjustable delay line 16. In the preferred embodiment, delay lines 16-16&#34; are substantially identical (with the notable exception that 16&#34; has one less stage), therefore for purposes of discussion, only 16 is described. It should be understood however, that with the aid of the present disclosure, those skilled in the art will readily recognize other configurations for the adjustable delay lines 16-16&#34; without departing from the scope of the present invention. 
     Delay line 16 is a five bit (D 4  -D 0 ) digitally programmable delay. The five bits selectably induce one of thirty-two delay values into the data path between the loop clock input and the shifted clock output. The five bits (D 4  -D 0 ) are dynamically altered by the output of up/down counter 14 (Delay --  adj &lt;4:0&gt;). 
     The least significant bit (D 0 ) selects the minimum discrete delay value (0.5δ), by switching pass gate 34 on to introduce capacitor 33 to the data path. The capacitor 33 delays the loop clock input signal on the data path by a predetermined value (0.5δ). In the preferred embodiment, the Applicant has tuned the value of capacitor 33 so that 0.5δ equals the delay of a single inverter. 
     The next increment in delay is δ (32a-32o) which is schematically depicted as two cascaded inverters in 32g. Data bit D 1  controls a first multiplexer 36 having a first input coupled to the data path and a second input coupled to the data path delayed by one δ (32a). Hence, data bit D 2  either selects a single delay (32a) into the data path or allows the clock signal on the data path to flow through to pass gate 34. 
     Data bit D 2  controls a second multiplexer 38 having a first input coupled to the data path and a second input coupled to the data path delayed by two δs (32b-32c). The output of multiplexer 38 drives both the first input on multiplexer 36 and the second input on multiplexer 36 delayed by single delay (32a). Hence, data bit D 2  either inserts two delays (32b-32c) into the data path or allows the signals on the data path to flow through to the first and the second (delayed) inputs on multiplexer 36. 
     Data bit D 3  controls a third multiplexer 40 having a first input coupled to the data path and a second input coupled to the data path delayed by four δs (32d-32g). The output of multiplexer 40 drives both the first input on multiplexer 38 and the second input on multiplexer 38 delayed by two δs (32b-32c). Hence, data bit D 3  either inserts four delays (32d-32g) into the data path or allows the signal on the data path to flow through to the first and second (delayed) inputs on multiplexer 38. 
     Data bit D 4  controls a fourth multiplexer 41 having a first input coupled to the data path and a second input coupled to the data path delayed by eight δs (32h-32o). The output of multiplexer 41 drives both the first input on multiplexer 40 and the second input on multiplexer 40 delayed by four δs (32d-32g). Hence, data bit D 4  either inserts eight delays (32h-32o) into the data path or allows the signal on the data path to flow through to the first and second (delayed) inputs on multiplexer 40. 
     It should be understood therefore, that any one of thirty-two cumulative delays can be induced into the data path by choosing an appropriate pattern for D 4  -D 0 . These delays and relationship to data bits D 4  -D 0  are depicted in Table 1. 
     
                       TABLE 1______________________________________D.sub.4  D.sub.3          D.sub.2    D.sub.1                         D.sub.0  Delay______________________________________0        0     0          0   0        None0        0     0          0   1        .5δ0        0     0          1   0        δ0        0     0          1   1        1.5δ0        0     1          0   0        2δ0        0     1          0   1        2.5δ0        0     1          1   0        3δ0        0     1          1   1        3.5δ0        1     0          0   0        4δ0        1     0          0   1        4.5δ0        1     0          1   0        5δ0        1     0          1   1        5.5δ0        1     1          0   0        6δ0        1     1          0   1        6.5δ0        1     1          1   0        7δ0        1     1          1   1        7.5δ1        0     0          0   0        8δ1        0     0          0   1        8.5δ1        0     0          1   0        9δ1        0     0          1   1        9.5δ1        0     1          0   0        10δ1        0     1          0   1        10.5δ1        0     1          1   0        11δ1        0     1          1   1        11.5δ1        1     0          0   0        12δ1        1     0          0   1        12.5δ1        1     0          1   0        13δ1        1     0          1   1        13.5δ1        1     1          0   0        14δ1        1     1          0   1        14.5δ1        1     1          1   0        15δ1        1     1          1   1        15.5δ______________________________________ 
    
     It should be understood that those skilled in the art, with the aid of the present disclosure, will be able to expand or contract the delay line 16 to more or less than five bits without departing from the scope of the present invention. 
     Reference is now made to FIG. 5 which depicts a clock doubling circuit practiced in accordance with the principles of the present invention. XOR gate 43 and XNOR gate 44 have a first input coupled to the loop clock output from adjustable delay line 16 (δ1) and a second input coupled to the phase shifted clock (e.g. clock90) from the second adjustable delay line 16&#34; (δ3). The outputs of XOR gate 43 and XNOR gate 44 provide Clock2x and Clock 2x signals which have a frequency twice that of the loop clock and a duty cycle dependent on phase shift of the phase shifted clock input. 
     Reference is now made to FIGS. 6 and 7 which depict timing diagrams of signals generated in FIG. 5 in accordance with the principles of the present invention. FIG. 7 depicts the general case whereas FIG. 6 depicts the specific case where δ2=0.5 δ1. In both FIGS. 6 and 7, the period of loop clock is set by delay δ1. In the specific case depicted in FIG. 6, the duty cycle (i.e. the percentage of time remaining high) is 50%. The high time is set by δ2 and since δ2 is 0.5 δ1, the time remaining low is also δ2. In the general case depicted in FIG. 7, the high time is set by δ3 and the time remaining low is δ1-δ3. 
     Conclusion 
     Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.