Abstract:
One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present invention relates generally to electrical circuits. More particularly, the present invention relates to reducing voltage jitter in data transmission. 
         [0003]    2. Description of the Background Art 
         [0004]    Serial links may be used to communicate between devices in a system. Typically, it is the intention for the transmitter in such a system to transmit a digital (binary) signal having two distinctive levels and well-defined (i.e., very steep) transitions from either of these levels to the other level. However, the medium that conveys the signal from the transmitter to the receiver usually imposes losses on the signal being transmitted. These losses generally include diminished signal amplitude and reduced transition steepness. 
         [0005]    To maintain accurate, high-speed data transmission, it is necessary for the circuitry to compensate for these losses. One compensation technique is to use what is called pre-emphasis at the transmitter. Another compensation technique is to perform equalization at the receiver. 
         [0006]    It is highly desirable to improve transceiver circuits for high-speed serial interfaces and other applications. 
       SUMMARY 
       [0007]    One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. 
         [0008]    Another embodiment relates to a transmitter circuit which includes a plurality of current sources, a plurality of filters, and a driver switch circuit. A first filter is coupled between a first current source and a first node, and a second filter is coupled between the first current source and a second node. A third filter is coupled between the second current source and a third node, and a fourth filter is coupled between the second current source and a fourth node. A driver switch circuit coupled to the first, second, third and fourth nodes. The driver switch circuit may include a main driver circuit connected to the first and third nodes and a pre-emphasis driver circuit connected to the second and fourth nodes. 
         [0009]    Another embodiment relates to an integrated circuit. The integrated circuit includes a transmitter which is configured to receive a digital data signal and generate a pre-emphasis signal which is a phase shifted and scaled version of the digital data signal. A driver switch circuit for the transmitter is configured to add the pre-emphasis signal to the digital data signal so as to generate an output signal. In addition, a plurality of low-pass filters are advantageously connected between current sources and the driver switch. 
         [0010]    Other embodiments, aspects and features are also disclosed. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  shows transient eye diagrams for a conventional transmitter and receiver. 
           [0012]      FIG. 2  shows transient eye diagrams for a transmitter and receiver with reduced voltage jitter in accordance with an embodiment of the invention. 
           [0013]      FIG. 3  is a circuit diagram of a transmitter with pre-emphasis circuitry. 
           [0014]      FIG. 4  is a system diagram of a transmitter with pre-emphasis circuitry. 
           [0015]      FIGS. 5A and 5B  are circuit diagrams illustrating the source of the data-dependent variations that applicants have determined occur in the transmitter due to pre-emphasis switching. 
           [0016]      FIG. 6  is a block diagram showing filtering to suppress the modulation of current sources in accordance with an embodiment of the invention. 
           [0017]      FIG. 7  is a graph of voltage versus time demonstrating the reduction in jitter noise with the filtering in place in accordance with an embodiment of the invention. 
           [0018]      FIG. 8A  is a transient eye diagram for a transmitter without the filtering in place. 
           [0019]      FIG. 8B  is a transient eye diagram for a transmitter with the filtering in place in accordance with an embodiment of the invention. 
           [0020]      FIG. 9  is a simplified partial block diagram of a field programmable gate array (FPGA) that may be configured to implement an embodiment of the present invention. 
           [0021]      FIG. 10  shows a block diagram of an exemplary digital system that may be configured to utilize an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    As data rates and bandwidth requirements of serial links continue to increase, so does the demand and complexity placed on transceiver designs to deliver solutions to maximize the signal integrity between integrated circuits (ICs). 
         [0023]    As mentioned above, pre-emphasis is one technique to minimize the effects of high-frequency losses caused by the channel medium. Pre-emphasis typically boosts the high frequencies in the transmit data signal since the high-frequency signal components generally suffer greater attenuation as the signal is transmitted over the medium. However, as described further below, applicants have determined that the variation in frequency response caused by the pre-emphasis results in data-dependent jitter and other inter symbol interference (ISI) effects. 
         [0024]    The present disclosure describes a technique used to effectively suppress pre-emphasis voltage noise in a high-speed transceiver. The technique also helps to prevent the driver switches from hitting an overstress condition by suppressing voltage spikes on the current source (Vtp and Vtn) nodes. The suppression of the voltage noise is accomplished by filtering the modulation on the current source nodes. A low pass (RC) filter may be inserted between the nodes and the current sources to attenuate the high-frequency modulation. 
         [0025]    Embodiments disclosed herein provide numerous benefits and advantages. First, the amount of voltage variations on the output of the transmitter driver is reduced when pre-emphasis is enable for high data rates. Second, performance of the high-speed transmitter buffer is increased. Third, the signal integrity of the transmitter buffer at high data rates is improved by reducing inter-symbol interference caused by data-dependent jitter. Fourth, by minimizing voltage spikes, the driver switches are less likely to enter overstress conditions. Fifth, data-dependent voltage modulation is suppressed. 
         [0026]      FIG. 1  shows transient eye diagrams for a conventional transmitter and receiver. The transient eye diagram for the transmitter is shown at the top, and the transient eye diagram for the receiver is shown at the bottom. 
         [0027]    The eye diagram for the transmitter shows relatively large voltage jitter in the superimposed transitions. Applicants have determined that voltage jitter is caused, in large part, by data-dependent pre-emphasis variations. The corresponding eye diagram for the receiver shows a relatively small eye opening  102 . The small eye opening is a result of the large voltage jitter at the transmitter. 
         [0028]      FIG. 2  shows transient eye diagrams for a transmitter and receiver with reduced voltage jitter in accordance with an embodiment of the invention. As in  FIG. 1 , the transient eye diagram for the transmitter is shown at the top, and the transient eye diagram for the receiver is shown at the bottom. 
         [0029]    The eye diagram for the transmitter in  FIG. 2  shows substantially less voltage jitter in the superimposed transitions compared with the corresponding eye diagram in  FIG. 1 . As described further below, the reduction in voltage jitter is due to a dampening of data-dependent pre-emphasis variations in accordance with an embodiment of the invention. The corresponding eye diagram for the receiver shows a relatively large eye opening  202 . The larger eye opening is a result of the smaller voltage jitter at the transmitter. 
         [0030]      FIG. 3  is a circuit diagram of a transmitter with pre-emphasis circuitry. The transmitter includes a circuit block  302  with driver switches in an H-tree buffer architecture. 
         [0031]    A main driver circuit includes the four transistors (MP 1 A, MP 1 B, MN 1 A, and MN 1 B) and main pull-up and pull-down current drivers (Ip_main and In_main, respectively). The main pull-up current driver (Ip_main) may be connected in series between power supply voltage source (VDD) and the node Vtp. The main pull-down current driver (In_main) may be connected in series between ground and the node Vtn. 
         [0032]    PMOS transistor MP 1 A and NMOS transistor MN 1 A are connected in series between nodes Vtp and Vtn. In particular, node Vtp is connected to the source of MP 1 A, the drain of MP 1 A is connected to the source of MN 1 A at node TXN, and the drain of MN 1 A is connected to the node Vtn. 
         [0033]    PMOS transistor MP 1 B and NMOS transistor MN 1 B are also connected in series between nodes Vtp and Vtn. In particular, node Vtp is connected to the source of MP 1 B, the drain of MP 1 B is connected to the source of MN 1 B at node TXP, and the drain of MN 1 B is connected to the node Vtn. 
         [0034]    Nodes Vop and Von are connected to differential outputs TXP and TXN, respectively, such that the final output signal is the differential signal (Vop−Von). Resistors RA and RB are connected in series between nodes Vop and Von. The resistances of RA and RB may be equal (RA=RB=R). Common mode voltage node Vcm is located between resistors RA and RB and may be driven by a common mode driver connected between VCM and ground. 
         [0035]    A pre-emphasis driver circuit includes the four transistors (MP 2 A, MP 2 B, MN 2 A, and MN 2 B) and pre-emphasis pull-up and pull-down current drivers (Ip_pre and In_pre, respectively). The pre-emphasis pull-up current driver (Ip_pre) may be connected in series between power supply voltage source (VDD) and the node Vtp_pre. The pre-emphasis pull-down current driver (In_pre) may be connected in series between ground and the node Vtn_pre. 
         [0036]    PMOS transistor MP 2 A and NMOS transistor MN 2 A are connected in series between nodes Vtp_pre and Vtn_pre. In particular, node Vtp_pre is connected to the source of MP 2 A, the drain of MP 2 A is connected to the source of MN 2 A at node TXN, and the drain of MN 2 A is connected to the node Vtn_pre. 
         [0037]    PMOS transistor MP 2 B and NMOS transistor MN 2 B are also connected in series between nodes Vtp_pre and Vtn_pre. In particular, node Vtp_pre is connected to the source of MP 2 B, the drain of MP 2 B is connected to the source of MN 2 B at node TXP, and the drain of MN 2 B is connected to the node Vtn_pre. 
         [0038]      FIG. 4  is a system diagram of a transmitter with pre-emphasis circuitry. The system diagram of  FIG. 4  may be considered in view of the circuit diagram of  FIG. 3 . As shown, a main signal  402  is input and a pre-emphasis signal  404  is generated based on the main signal  402 . In this implementation, the Z −1  transform provides a delay such that the pre-emphasis signal  404  is slightly delayed in phase relative to the main signal  402 . In other words, in this implementation, the pre-emphasis signal  404  is a post-tap signal. In an alternative implementation, the pre-emphasis signal  404  may be a pre-tap signal. The main signal  402  and a scaled version of the pre-emphasis signal  404  is added together to create the output signal  406 . 
         [0039]      FIGS. 5A and 5B  are circuit diagrams illustrating the source of the data-dependent variations that applicants have determined occur in the transmitter due to pre-emphasis switching. Output nodes Vop and Von in  FIGS. 5A and 5B  correspond respectively to output nodes Vop and Von in  FIG. 3 . Resistance  2 R in  FIGS. 5A and 5B  corresponds to the resistors RA and RB in series in  FIG. 3 . The switches in  FIGS. 5A and 5B  correspond to the transistors in  FIG. 3  as follows. 
         [0000]    
       
         
               
               
               
             
           
               
                   
                   
               
               
                   
                 Switch in 
                 Transistor 
               
               
                   
                 FIGS. 5A and 5B 
                 in FIG. 3 
               
               
                   
                   
               
             
             
               
                   
                 S0 
                 MP1B 
               
               
                   
                 S1 
                 MP1A 
               
               
                   
                 S2 
                 MN1B 
               
               
                   
                 S3 
                 MN1A 
               
               
                   
                 Sp0 
                 MP2A 
               
               
                   
                 Sp1 
                 MP2B 
               
               
                   
                 Sp2 
                 MN2A 
               
               
                   
                 Sp3 
                 MN2B 
               
               
                   
                   
               
             
          
         
       
     
         [0040]    Both  FIGS. 5A and 5B  depict the current flow when the main switches are in the positive differential (true or 1) output state. In this state, main switches S 0  and S 3  are closed (conducting), and main switches S 1  and S 2  are not. This causes a main current  502  to flow in series through Ip_main, node Vtp, switch S 0 , two resistors RB and RA, switch S 3 , node Vtn, and In_main. Due to the current  502  flowing through the two resistors, the output voltage at node Vop is higher than the output voltage at node Von (thus generating the positive differential output). 
         [0041]    While the main switches are configured the same in  FIGS. 5A and 5B , the pre-emphasis switches are not. The pre-emphasis switches are configured to contribute a negative differential to the output in  FIG. 5A , while they are configured to contribute a positive differential to the output in  FIG. 5B . 
         [0042]    In  FIG. 5A , pre-emphasis switches Sp 0  and Sp 3  are closed (conducting), while the pre-emphasis switches Sp 1  and Sp 2  are open. This causes the pre-emphasis current  504  to flow in series through Ip_pre, node Vtp_pre, switch Sp 0 , resistors RA and RB, switch Sp 3 , node Vtn_pre, and In_pre. This results in the negative differential contribution to the output. 
         [0043]    In  FIG. 5B , pre-emphasis switches Sp 1  and Sp 2  are closed (conducting), while the pre-emphasis switches Sp 0  and Sp 3  are open. This causes the pre-emphasis current  504  to flow in series through Ip_pre, node Vtp_pre, switch Sp 1 , resistors RB and RA, switch Sp 2 , node Vtn_pre, and In_pre. This results in the positive differential contribution to the output. 
         [0044]    Depending on the pre-emphasis data signal (which is a phase shifted version of the main data signal), the pre-emphasis signal may make either a positive or negative differential contribution to the output. Applicants have determined that this switching of the pre-emphasis current flow between negative and positive differential contributions that leads to the undesirable data-dependent voltage jitter in the final differential output signal. This is because the voltages on the nodes Vtp and Vtn are modulated to some degree by the direction of the pre-emphasis current flow. 
         [0045]    In addition to determining the cause of the data-dependent voltage jitter, applicants hereby disclose filter placements to reduce or eliminate it. In accordance with an embodiment of the invention, low-pass filters may be placed at strategic points in the circuitry to suppress the voltage modulation of the current sources. The placement of the low-pass filters is depicted in  FIG. 6 . 
         [0046]    The driver switch block  602  in  FIG. 6  corresponds to the circuit block  302  in  FIG. 3 . The PMOS current source  604 -P in  FIG. 6  is a pull-up current source which is configured to drive the current Ip_main and the current Ip_pre in  FIG. 3 . The NMOS current source  604 -N in  FIG. 6  is a pull-down current source which is configured to drive the current In_main and the current In_pre in  FIG. 3 . 
         [0047]    A termination  606  is connected between the differential voltage output nodes Vop and Von. The pre-driver block  608  receives pre-driver inputs and outputs the driver inputs to the driver switch block  602 . The gates of the transistors within the driver switch block  602  are driven by the driver inputs. 
         [0048]    In accordance with an embodiment of the invention, four low-pass (LP) filters may be advantageously configured between the current sources and the driver switch. A first LP filter  610 -P may be configured between the PMOS current source  604 -P and the node Vtp. A second LP filter  610 -N may be configured between the NMOS current source  604 -N and the node Vtn. A third LP filter  612 -P may be configured between the PMOS current source  604 -P and the node Vtp. Finally, a fourth LP filter  612 -N may be configured between the NMOS current source  604 -N and the node Vtn. 
         [0049]      FIG. 7  is a graph of voltage versus time showing jitter noise without and with the filtering in place. The jitter noise on the Vtp nodes without filtering (No Filter)  702  is seen to be substantially reduced when filtering is in place (Filter Nodes)  704 . Hence, it is seen that the LP filters ( 610 -P,  610 -N,  612 -P and  612 -N) placed as shown in  FIG. 6  are surprisingly effective in reducing unwanted jitter. 
         [0050]      FIG. 8A  is a transient eye diagram for a transmitter without the filtering in place. In comparison,  FIG. 8B  is a transient eye diagram for a transmitter with the filtering in place in accordance with an embodiment of the invention. As seen, the eye diagram for the transmitter with filtering in  FIG. 8B  shows substantially less voltage jitter in the superimposed transitions in comparison to the eye diagram for the transmitter without filtering in  FIG. 8A . This much reduced level of transmitter voltage jitter is a surprising result from the strategic insertion of the LP filters shown in  FIG. 6 . Referring to  FIGS. 1 and 2 , this reduction of voltage jitter at the transmitter will translate to a corresponding reduction in voltage jitter and a substantially increased eye opening at the receiver. 
         [0051]      FIG. 9  is a simplified partial block diagram of a field programmable gate array (FPGA)  900  that can include aspects of the present invention. It should be understood that embodiments of the present invention can be used in numerous types of integrated circuits such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), programmable logic arrays (PLAs), digital signal processors (DSPs) and application specific integrated circuits (ASICs). 
         [0052]    FPGA  900  includes within its “core” a two-dimensional array of programmable logic array blocks (or LABs)  902  that are interconnected by a network of column and row interconnect conductors of varying length and speed. LABs  902  include multiple (e.g., ten) logic elements (or LEs). 
         [0053]    An LE is a programmable logic block that provides for efficient implementation of user defined logic functions. An FPGA has numerous logic elements that can be configured to implement various combinatorial and sequential functions. The logic elements have access to a programmable interconnect structure. The programmable interconnect structure can be programmed to interconnect the logic elements in almost any desired configuration. 
         [0054]    FPGA  900  may also include a distributed memory structure including random access memory (RAM) blocks of varying sizes provided throughout the array. The RAM blocks include, for example, blocks  904 , blocks  906 , and block  908 . These memory blocks can also include shift registers and FIFO buffers. 
         [0055]    FPGA  900  may further include digital signal processing (DSP) blocks  910  that can implement, for example, multipliers with add or subtract features. Input/output elements (IOEs)  912  located, in this example, around the periphery of the chip support numerous single-ended and differential input/output standards. Each IOE  912  is coupled to an external terminal (i.e., a pin) of FPGA  900 . A transceiver (TX/RX) channel array may be arranged as shown, for example, with each TX/RX channel circuit  920  being coupled to several LABs. A TX/RX channel circuit  920  may include, among other circuitry, the transmitter circuitry described herein. 
         [0056]    It is to be understood that FPGA  900  is described herein for illustrative purposes only and that the present invention can be implemented in many different types of PLDs, FPGAs, and ASICs. 
         [0057]    The present invention can also be implemented in a system that has a FPGA as one of several components.  FIG. 10  shows a block diagram of an exemplary digital system  1000  that can embody techniques of the present invention. System  1000  may be a programmed digital computer system, digital signal processing system, specialized digital switching network, or other processing system. Moreover, such systems can be designed for a wide variety of applications such as telecommunications systems, automotive systems, control systems, consumer electronics, personal computers, Internet communications and networking, and others. Further, system  1000  may be provided on a single board, on multiple boards, or within multiple enclosures. 
         [0058]    System  1000  includes a processing unit  1002 , a memory unit  1004 , and an input/output (I/O) unit  1006  interconnected together by one or more buses. According to this exemplary embodiment, FPGA  1008  is embedded in processing unit  1002 . FPGA  1008  can serve many different purposes within the system  1000 . FPGA  1008  can, for example, be a logical building block of processing unit  1002 , supporting its internal and external operations. FPGA  1008  is programmed to implement the logical functions necessary to carry on its particular role in system operation. FPGA  1008  can be specially coupled to memory  1004  through connection  1010  and to I/O unit  1006  through connection  1012 . 
         [0059]    Processing unit  1002  may direct data to an appropriate system component for processing or storage, execute a program stored in memory  1004 , receive and transmit data via I/O unit  1006 , or other similar function. Processing unit  1002  may be a central processing unit (CPU), microprocessor, floating point coprocessor, graphics coprocessor, hardware controller, microcontroller, field programmable gate array programmed for use as a controller, network controller, or any type of processor or controller. Furthermore, in many embodiments, there is often no need for a CPU. 
         [0060]    For example, instead of a CPU, one or more FPGAs  1008  may control the logical operations of the system. As another example, FPGA  1008  acts as a reconfigurable processor that may be reprogrammed as needed to handle a particular computing task. Alternately, FPGA  1008  may itself include an embedded microprocessor. Memory unit  1004  may be a random access memory (RAM), read only memory (ROM), fixed or flexible disk media, flash memory, tape, or any other storage means, or any combination of these storage means. 
         [0061]    In the above description, numerous specific details are given to provide a thorough understanding of embodiments of the invention. However, the above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. One skilled in the relevant art will recognize that the invention can be practiced without one or more of the specific details, or with other methods, components, etc. 
         [0062]    In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications may be made to the invention in light of the above detailed description.