Abstract:
An integrated circuit device includes a liquid crystal display (LCD) driver circuit. This LCD driver circuit includes a decoder and a multi-stage sample-hold circuit coupled to an output of the decoder. The LCD driver circuit supports different contrasts for the red, blue and green color signals. In particular, the LCD driver circuit is configured to convert red, blue and green data input signals having equivalent digital values into red, blue and green data output signals having unequal analog values (corresponding to different contrast levels).

Description:
REFERENCE TO PRIORITY APPLICATION  
       [0001]     This application claims priority to Korean Patent Application No. 2004-95891, filed Nov. 22, 2004, the disclosure of which is hereby incorporated herein by reference.  
         [0002]     1. Field of the Invention  
         [0003]     The present invention relates to display devices and, more particularly, to liquid crystal display (LCD) devices and methods of operating same.  
         [0004]     2. Description of the Related Art  
         [0005]      FIG. 1  is a block diagram of a conventional source driving IC  10 . Referring to  FIG. 1 , the source driving IC  10  includes an analog voltage generator  11 , registers REG 1  through REG 3 Q, latch circuits L 1  through L 3 Q, decoders D 1  through D 3 Q, and amplifiers M 1  through M 3 Q. The analog voltage generator  11  generates analog voltages AV 1  through AVN (N is an integer) on the basis of external gamma voltages EV 1  through EVK (K is an integer). The registers REG 1  through REG 3 Q store R, G and B color signals r 1  through r 3 Q, g 1  through g 3 Q and b 1  through b 3 Q of a digital data signal S_DAT, which are continuously received, in response to an input control signal DIO and outputs the stored R, G and B color signals r 1  through r 3 Q, g 1  through g 3 Q and b 1  through b 3 Q, respectively. The latch circuits L 1  through L 3 Q simultaneously latch and output the R, G and B color signals r 1  through r 3 Q, g 1  through g 3 Q and b 1  through b 3 Q in response to a control signal CTL. The decoders D 1  through D 3 Q each select one of the analog voltages AV 1  through AVN in response to the latched R, G and B color signals r 1  through r 3 Q, g 1  through g 3 Q and b 1  through b 3 Q and output the selected analog voltages.  
         [0006]     To convert the R, G and B color signals r 1  through r 3 Q, g 1  through g 3 Q and b 1  through b 3 Q into analog data signals respectively, the source driving IC  10  includes the decoders D 1  through D 3 Q. Thus, the chip size and current consumption of the source driving IC  10  can be high. Furthermore, the analog voltage generator  11  generates the analog voltages AV 1  through AVN based on the external gamma voltages EV 1  through EVK having a single transmissivity-to-voltage curve as shown in  FIG. 2 . Accordingly, the source driving IC  10  cannot represent the R, G and B color signals with different contrasts.  
       SUMMARY OF THE INVENTION  
       [0007]     The present invention provides a source driving IC for an LCD, which converts digital data signals into analog data signals using only a small number of decoders to reduce the chip size and current consumption and display images corresponding to R, G and B color signals with different contrasts using a plurality of external gamma voltages having different transmissivity-to-voltage curves. The present invention also provides a driving method of the source driving IC for an LCD.  
         [0008]     According to an aspect of the present invention, there is provided a source driving integrated circuit arranged along one side of an LCD panel to drive the LCD panel, which includes a decoder, a sample-hold unit, and an amplification unit. The decoder continuously outputs analog data signals in response to continuously received digital data signals. The sample-hold unit continuously latches the analog data signals and simultaneously outputs the latched analog data signal in response to an output strobe signal. The amplification unit increases the currents of the latched analog data signals and outputs the analog data signals as analog video signals. Preferably, the source driving integrated circuit further includes a data storage unit that receives and stores digital data signals corresponding to one horizontal line of the LCD panel in response to an input control signal, selects the stored digital data signals one at a time in response to control signals and continuously outputs the selected digital data signals to the decoder. Preferably, the source driving integrated circuit further includes an additional sample-hold unit and an analog voltage generator. The additional sample-hold unit latches gamma voltages and outputs the latched gamma voltages. The analog voltage generator generates a plurality of analog voltages based on the latched gamma voltages.  
         [0009]     According to another aspect of the present invention, there is provided a driving method of a source driving integrated circuit for driving an LCD panel, which includes (a) generating analog voltages based on gamma voltages; (b) receiving and storing digital data signals corresponding to one horizontal line of the LCD panel in response to an input control signal, selecting the stored digital data signals one at a time in response to control signals and continuously outputting the selected digital data signals; (c) continuously outputting analog data signals in response to the digital data signals continuously received and the analog voltages; (d) continuously latching the analog data signals and simultaneously outputting the latched analog data signals in response to an output strobe signal; and (e) increasing the currents of the latched analog data signals and outputting the analog data signals as analog video signals. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0011]      FIG. 1  is a block diagram of a conventional source driving IC;  
         [0012]      FIG. 2  shows a transmissivity-to-voltage curve of external gamma voltages input to the source driving IC of  FIG. 1 ;  
         [0013]      FIG. 3  is a block diagram of a source driving IC according to the present invention;  
         [0014]      FIG. 4  shows transmissivity-to-voltage curves of gamma voltages input to the second sample-hold unit shown in  FIG. 3 ;  
         [0015]      FIG. 5  is a circuit diagram of the second sample-hold unit shown in  FIG. 3 ;  
         [0016]      FIG. 6  is a circuit diagram of the first and second sample-hold circuits shown in  FIG. 3 ;  
         [0017]      FIG. 7  is a timing diagram of signals required for the operation of the source driving IC shown in  FIG. 3 ; and  
         [0018]      FIG. 8  shows a sampling period of analog data signals corresponding to the first horizontal line of the LCD panel shown in  FIG. 7  in more detail. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0019]     The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Throughout the drawings, like reference numerals refer to like elements.  
         [0020]      FIG. 3  is a block diagram of a source driving IC  100  according to the present invention. Referring to  FIG. 3 , the source driving IC  100  includes a data storage unit  110 , a decoder  120 , a first sample-hold unit  130 , an amplification unit  140 , a second sample-hold unit  150 , and an analog voltage generator  160 . The data storage unit  110  includes a plurality of data registers RG 1  through RG 3 L (L is an integer). The data registers RG 1  through RG 3 L store a digital data signal S_DAT corresponding to one horizontal line of an LCD panel (not shown) in response to an input control signal DIO. The digital data signal S_DAT includes R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL. Specifically, the data register RG 1  stores the R color signal r 1 , the data register RG 2  stores the G color signal g 1 , and the data register RG 3  stores the B color signal b 1 . The data registers RG 4  through RG 3 L sequentially store the color signals r 2 , g 2 , b 2 , . . . , rL, gL and bL, respectively. Furthermore, the data registers RG 1  through RG 3 L output the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL stored therein in response to control signals P 1  through P 3 L, respectively. Here, one of the data registers RG 1  through RG 3 L outputs one of the R color signals r 1  through rL, one of the G color signals g 1  through gL or one of the B color signals b 1  through bL because each of the control signals P 1  through P 3 L can be independently enabled. For example, when the control signal P 1  is enabled and the control signals P 2  through P 3 L are disabled, the data register RG 1  outputs the R color signal r 1 . Here, each of the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL includes multiple bits.  
         [0021]     The decoder  120  outputs an analog data signal (one of FAS 1  through FASL, one of SAS 1  through SASL, or one of TAS 1  through TASL) in response to the values of the bits of one of the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL, received from one of the data registers RG 1  through RG 3 L. More specifically, the decoder  120  selects one of first analog voltages FAV 1  through FAVN (N is an integer) in response to the values of the bits of an R color signal (one of the signals r 1  through rL) received from one of the data registers RG 1 , RG 4 , RG 7 , . . . , RG( 3 L- 2 ) and outputs the selected analog voltage as the analog data signal (one of FAS 1  through FASL). For example, when the R color signal r 1  is an 8-bit signal, the decoder  120  selects one of 256 first analog voltage levels FAV 1  through FAV 256  in response to the values of the bits of the R color signal r 1  and outputs it as the analog data signal FAS 1 .  
         [0022]     The decoder  120  selects one of second analog voltages SAV 1  through SAVN (N is an integer) in response to the values of the bits of a G color signal (one of the signals g 1  through gL) received from one of the data registers RG 2 , RG 5 , RG 8 , . . . , RG( 3 L- 1 ) and outputs the selected analog voltage as the analog data signal (one of SAS 1  through SASL). For example, when the G color signal g 1  is an 8-bit signal, the decoder  120  selects one of 256 second analog voltage levels SAV 1  through SAV 256  in response to the values of the bits of the G color signal g 1  and outputs it as the analog data signal SAS 1 . Furthermore, The decoder  120  selects one of third analog voltages TAV 1  through TAVN (N is an integer) in response to the values of the bits of a B color signal (one of the signals b 1  through bL) received from one of the data registers RG 3 , RG 6 , RG 9 , . . . , RG 3 L and outputs the selected analog voltage as the analog data signal (one of TAS 1  through TASL). For example, when the B color signal b 1  is an 8-bit signal, the decoder  120  selects one of 256 third analog voltage levels TAV 1  through TAV 256  in response to the values of the bits of the B color signal b 1  and outputs it as the analog data signal TAS 1 .  
         [0023]     The first sample-hold unit  130  includes first sample-hold circuits FSH 1  through FSH 3 L (L is an integer) and second sample-hold circuits SSH 1  through SSH 3 L (L is an integer). The first sample-hold circuits FSH 1  through FSH 3 L latch (or sample) the analog data signals FAS 1  through FASL, SAS 1  through SASL and TAS 1  through TASL, received from the decoder  120 , in response to switching control signals W 1  through W 3 L (L is an integer), respectively. Here, when one of the first sample-hold circuits FSH 1  through FSH 3 L is operated, other first sample-hold circuits stop their latching operations because the switching control signals W 1  through W 3 L are enabled one at a time. For instance, when the switching control signal W 1  is enabled and the switching control signals W 2  through W 3 L are disabled, the first sample-hold circuit FSH 1  latches the first analog data signal FAS 1  and outputs the latched first analog data signal FSH 1 ′. When the switching control signal W 2  is enabled, the first sample-hold circuit FSH 2  latches the second analog data signal SAS 1  and outputs the latched second analog data signal SAS 1 ′. When the switching control signal W 3  is enabled, the first sample-hold circuit FSH 3  latches the third analog data signal TAS 1  and outputs the latched third analog data signal TAS 1 ′. In this manner, the first sample-hold circuits FSH 4  through FSH 3 L latch the analog data signals FAS 2 , SAS 2 , TAS 2 , . . . , FASL, SASL and TASL and output the latched analog data signals FAS 2 ′, SAS 2 ′, TAS 2 ′, FASL′, SASL′ and TASL′, respectively.  
         [0024]     The second sample-hold circuits SSH 1  through SSH 3 L simultaneously latch (or sample) the latched analog data signals FAS 1 ′, SAS 1 ′, TAS 1 ′, . . . , FASL′, SASL′ and TASL′, received from the first sample-hold circuits FSH 1  through FSH 3 L, in response to an output strobe signal OCTL and respectively output the latched analog data signals FAS 1 ″, SAS 1 ″, TAS 1 ″, . . . , FASL″, SASL″ and TASL″. When the first sample-hold circuits FSH 1  through FSH 3 L latch analog data signals corresponding to the second horizontal line of the LCD panel, the second sample-hold circuits SSH 1  through SSH 3 L output previously latched analog data signals corresponding to the first horizontal line of the LCD panel.  
         [0025]     The amplification unit  140  includes amplifiers A 1  through A 3 L. The amplifiers A 1  through A 3 L increase the quantity of current of the latched analog data signals FAS 1 ″, SAS 1 ″, TAS 1 ″, . . . , FASL″, SASL″ and TASL″ while maintaining the voltage levels of the latched analog data signals FAS 1 ″, SAS 1 ″, TAS 1 ″, . . . , FASL″, SASL″ and TASL″ and output the analog data signals FAS 1 ″, SAS 1 ″, TAS 1 ″, FASL″, SASL″ and TASL″ as analog video signals R 1 , R 2 , B 1 , . . . , BL, respectively.  
         [0026]     The second sample-hold unit  150  latches first gamma voltages FGV 1  through FGVK (K is an integer), second gamma voltages SGV 1  through SGVK (K is an integer) or third gamma voltages TGV 1  through TGVK (K is an integer) in response to switching control signals S 1  through SK (K is an integer). More specifically, when the first gamma voltages FGV 1  through FGVK are received, the second sample-hold unit  150  latches the first gamma voltages FGV 1  through FGVK and outputs the latched first gamma voltages FGV 1 ′ through FGVK′. When the second gamma voltages SGV 1  through SGVK are received, the second sample-hold unit  150  latches the second gamma voltages SGV 1  through SGVK and outputs the latched second gamma voltages SGV 1 ′ through SGVK′. When the third gamma voltages TGV 1  through TGVK are received, the second sample-hold unit  150  latches the third gamma voltages TGV 1  through TGVK and outputs the latched third gamma voltages TGV 1 ′ through TGVK′. Here, the first, second and third gamma voltages FGV 1  through FGVL, SGV 1  through SGVK and TGV 1  through TGVK are generated by an external gamma voltage generator (not shown) and form different transmissivity-to-voltage curves GM 1 , GM 2  and GM 3 , respectively, as shown in  FIG. 4 . Since the first, second and third gamma voltages FGV 1  through FGVK, SGV 1  through SGVK and TGV 1  through TGVK form the different transmissivity-to-voltage curves GM 1 , GM 2  and GM 3 , respectively, the analog video signals R 1  through RL, G 1  through GL and B 1  through BL, which correspond to the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL, respectively, can be displayed with different contrasts.  
         [0027]     When the latched first gamma voltages FGV 1 ′ through FGVK′ are received, the analog voltage generator  160  generates the first analog voltages FAV 1  through FAVN based on the latched first gamma voltages FGV 1 ′ through FGVK′. When the latched second gamma voltages SGV 1 ′ through SGVK′ are received, the analog voltage generator  160  generates the second analog voltages SAV 1  through SAVN based on the latched second gamma voltages SGV 1 ′ through SGVK′. When the latched third gamma voltages TGV 1 ′ through TGVK′ are received, the analog voltage generator  160  generates the third analog voltages TAV 1  through TAVN based on the latched third gamma voltages TGV 1 ′ through TGVK′. Here, N is larger than K. That is, the analog voltage generator  160  generates a larger number of analog voltages than the number of received gamma voltages. For example, the analog voltage generator  160  generates 256 first analog voltages FAV 1  through FAV 256  based on 18 latched first gamma voltages FGV 1 ′ through FGV 18 ′. The composition and operation of the analog voltage generator  160  can be understood by those skilled in the art, and thus, a detailed explanation therefor is omitted.  
         [0028]     Alternatively, only gamma voltages GV 1  through GVK (not shown) having a single transmissivity-to-voltage curve can be continuously input to the second sample-hold unit  150 . In this case, the second sample-hold unit  150  latches the gamma voltages GV 1  through GVK and outputs the latched gamma voltages GV 1 ′ through GVK′. The analog voltage generator  160  generates analog voltages ALV 1  through ALVN based on the latched gamma voltages GV 1 ′ through GVK′. The decoder  120  selects one of the analog voltages ALV 1  through ALVN in response to each of the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL. Consequently, all of the analog data signals FAS 1  through FASL, SAS 1  through SASL and TAS 1  through TASL corresponding to the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL have the voltage level of one of the analog voltages ALV 1  through ALVN. Accordingly, the analog video signals R 1  through RL, G 1  through GL and B 1  through BL corresponding to the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL can be displayed with the same contrast.  
         [0029]      FIG. 5  is a circuit diagram of the second sample-hold unit  150  shown in  FIG. 3 . Referring to  FIG. 5 , the second sample-hold unit  150  includes a plurality of sample-hold circuits SH 1  through SHK (K is an integer). The sample-hold circuits SH 1  through SHK include switches SW 1  through SWK, capacitors C 1  through CK and operational amplifiers OP 1  through OPK, respectively. The switches SW 1  through SWK are turned on or off in response to the switching control signals S 1  through SK. Here, the switches SW 1  through SWK are simultaneously turned on or off because the switching control signals S 1  through SK are simultaneously enabled or disabled. When the switches SW 1  through SWK are on, the capacitors C 1  through CK are charged with the first gamma voltages FGV 1  through FGVK, second gamma voltages SGV 1  through SGVK or third gamma voltages TGV 1  through TGVK, respectively. The operational amplifiers OP 1  through OPK output the first, second or third gamma voltages FGV 1 ′ through FGVK′, SGV 1 ′ through SGVK′ or TGV 1 ′ through TGVK′in response to the first gamma voltages FGV 1  through FGVK, second gamma voltages SGV 1  through SGVK or third gamma voltages TGV 1  through TGVK with which the capacitors C 1  through CK, respectively, are charged.  
         [0030]      FIG. 6  is a circuit diagram of the first sample-hold circuit FSH 1  and the second sample-hold circuit SSH 1  shown in  FIG. 3 . The compositions and operations of the first sample-hold circuits FSH 2  through FSH 3 L are similar to those of the first sample-hold circuit FSH 1 , and the compositions and operations of the second sample-hold circuits SSH 2  through SSH 3 L are similar to those of the second sample-hold circuit SSH 1 . The first sample-hold circuit FSH 1  includes a switch SWF, a capacitor C f  and an operational amplifier OPF. The second sample-hold circuit SSH 1  includes a switch SWS, a capacitor C s  and an operational amplifier OPS. The switch SWF is turned on or off in response to the switching control signal W 1 . When the switch SWF is on, the capacitor C f  is charged to the voltage level of the analog data signal FAS 1 . Subsequently, when the switch SWS is on, the operational amplifier OPF outputs the analog data signal FAS 1 ′ in response to the voltage of the analog data signal FAS 1 , with which the capacitor C f  is charged, and the capacitor C s  is charged to the voltage level of the analog data signal FAS 1 ′. The operational amplifier OPS outputs the analog data signal FAS 1 ′ in response to the voltage of the analog data signal FAS 1 ′, charged in the capacitor C s .  
         [0031]     The operation of the source driving IC  100  will now be explained. First of all, the second sample-hold unit  150  latches the gamma voltages FGV 1  through FGVK, SGV 1  through SGVK or TGV 1  through TGVK in response to the switching control signals S 1  through SK and outputs the latched gamma voltages FGV 1 ′ through FGVK′, SGV 1 ′ through SGVK′ or TGV 1 ′ through TGVK′. The analog voltage generator  160  generates the analog voltages FAV 1  through FAVN, SAV 1  through SAVN or TAV 1  through TAVN based on the latched gamma voltages FGV 1 ′ through FGVK′, SGV 1 ′ through SGVK′ or TGV 1 ′ through TGVK′. The data registers RG 1  through RG 3 L of the data storage unit  110  store the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL of the digital data signal S_DAT for one horizontal line of the LCD panel in response to the input control signal DIO and continuously output the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL one at a time in response to the control signals P 1  through P 3 L.  
         [0032]     Referring to  FIG. 7 , when the input control signal DIO is firstly enabled, the data registers RG 1  through RG 3 L store the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL of the digital data signal S_DAT corresponding to the first horizontal line HL 1  of the LCD panel and continuously output the stored signals one at a time. In this manner, the data registers RG 1  through RG 3 L store the R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL of the digital data signal S_DAT corresponding to each horizontal line of the LCD panel in the order of HL 2 , HL 3  and HL 4  and output the stored signals one at a time whenever the input control signal DIO is enabled.  
         [0033]     Then, the decoder  120  selects the analog voltage (one of FAV 1  through FAVN, one of SAV 1  through SAVN or one of TAV 1  through TAVN) corresponding to bit values of the continuously received R, G and B color signals r 1  through rL, g 1  through gL and b 1  through bL and outputs an analog data signal (one of FAS 1  through FASL, one of SAS 1  through SASL or one of TAS 1  through TASL).  
         [0034]     The first sample-hold circuits FSH 1 , FSH 4 , FSH 7 , . . . , FSH( 3 L- 2 ) latch the analog data signals FAS 1  through FASL in response to the switching control signals W 1 , W 4 , W 7  , . . . , W( 3 L- 2 ) and output the latched analog data signals FAS 1 ′ through FASL′. The first sample-hold circuits FSH 2 , FSH 5 , FSH 8 , . . . , FSH( 3 L- 1 ) latch the analog data signals SAS 1  through SASL in response to the switching control signals W 2 , W 5 , W 8 , . . . , W( 3 L- 1 ) and output the latched analog data signals SAS 1 ′ through SASL′. The first sample-hold circuits FSH 3 , FSH 6 , FSH 9 , . . . , FSH 3 L latch the analog data signals TAS 1  through TASL in response to the switching control signals W 3 , W 6 , W 9 , . . . , W 3 L and output the latched analog data signals TAS 1 ′ through TASL′.  
         [0035]     The second sample-hold circuits SSH 1  through SSH 3 L simultaneously latch the latched analog data signals FAS 1 ′ through FASL′, SAS 1 ′ through SASL′ and TAS 1 ′ through TASL′ in response to the output strobe signal OCTL and respectively output the latched analog data signals FAS 1 ′ through FASL′, SAS 1 ′ through SASL′ and TAS 1 ′ through TASL′. As shown in  FIG. 7 , the second sample-hold circuits SSH 1  through SSH 3 L latch the analog data signals FAS 1 ′ through FASL′, SAS 1 ′ through SASL′ and TAS 1 ′ through TASL′ corresponding to each horizontal line in the order of HL 1 , HL 2 , HL 3  and HL 4  and output the latched analog data signals FAS 1 ′ through FASL′, SAS 1 ′ through SASL′ and TAS 1 ′ through TASL′ whenever the output strobe signal OCTL is enabled.  
         [0036]     Subsequently, the amplification unit  140  increases the currents of the latched analog data signals FAS 1 ′ through FASL′, SAS 1 ′ through SASL′ and TAS 1 ′ through TASL′ corresponding to each horizontal line in the order of HL 1 , HL 2 , HL 3  and HL 4  and outputs the latched analog data signals as analog video signals R 1  through RL, G 1  through GL and B 1  through BL of an output video signal ANL_OUT.  
         [0037]     As described above, the process of storing the digital data signal S_DAT corresponding to one horizontal line of the LCD panel, the process of sampling the analog data signals FAS 1  through FASL, SAS 1  through SASL and TAS 1  through TASL corresponding to the horizontal line, and the process of displaying the analog video signals R 1  through RL, G 1  through GL and B 1  through BL corresponding to the horizontal line are each executed at independent points of time. Accordingly, a period of time required for the first sample-hold circuits FSH 1  through FSH 3 L to latch (or sample) the analog data signals FAS 1  through FASL, SAS 1  through SASL and TAS 1  through TASL can be sufficiently secured, and thus there is no need for the first sample-hold circuits FSH 1  through FSH 3 L to operate at a high speed.  
         [0038]      FIG. 8  shows a sampling period TD of the analog data signals corresponding to the first horizontal line of the LCD panel shown in  FIG. 7  in detail. Referring to  FIG. 8 , the second sample-hold unit  150  latches the first gamma voltages FGV 1  through FGVK and outputs the latched first gamma voltages FGV 1 ′ through FGVK′ during a period T 1 . During a period T 2 , the first sample-hold circuits FSH 1 , FSH 4 , FSH 7 , . . . , FSH( 3 L- 2 ) sequentially latch the analog data signals FAS 1  through FASL corresponding to the R color signals r 1  through rL. Here, the data registers RG 1 , RG 4 , RG 7 , . . . , RG( 3 L- 2 ) sequentially output the R color signals r 1  through rL, respectively, in response to the sequentially enabled control signals P 1 , P 4  , P 7 , . . . , P( 3 L- 2 ).  
         [0039]     During a period T 3 , the second sample-hold unit  150  latches the second gamma voltages SGV 1  through SGVK and outputs the latched second gamma voltages SGV 1 ′ through SGVK′. During a period T 4 , the first sample-hold circuits FSH 2 , FSH 5 , FSH 8 , . . . , FSH( 3 L- 1 ) sequentially latch the analog data signals SAS 1  through SASL corresponding to the G color signals g 1  through gL. Here, the data registers RG 2 , RG 5 , RG 8 , . . . , RG( 3 L- 1 ) sequentially output the G color signals g 1  through gL, respectively, in response to the sequentially enabled control signals P 2 , P 5 , P 8 , . . . , P( 3 L- 1 ). During a period T 5 , the second sample-hold unit  150  latches the third gamma voltages TGV 1  through TGVK and outputs the latched third gamma voltages TGV 1 ′ through TGVK′. During a period T 6 , the first sample-hold circuits FSH 3 , FSH 6 , FSH 9 , . . . , FSH 3 L sequentially latch the analog data signals TAS 1  through TASL corresponding to the B color signals b 1  through bL. Here, the data registers RG 3 , RG 6 , RG 9 , . . . , RG 3 L sequentially output the B color signals b 1  through bL, respectively, in response to the sequentially enabled control signals P 3 , P 6 , P 9 , . . . , P 3 L. In  FIG. 8 , a period T 7  is a remaining interval.  
         [0040]     While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.