Abstract:
A digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing comprises a first inverter stage for generating an inverted signal from an input signal, the inverted signal having a voltage swing between a core voltage and ground, and a second inverter stage for producing an anti-phase signal from the inverted input signal, the anti-phase signal having a voltage swing between the core voltage and ground. The first and second inverters each drive a respective thin gate NMOS transistor connected in cascode with a respective NMOS transistor. The sources of the first and second thin gate NMOS transistors are connected to ground. The gates of the NMOS transistors are connected to the output of the respective inverters through a respective capacitor and are referenced to the core voltage through a respective resistor. The drains of the NMOS transistors are connected to an output circuit to provide an output signal having a voltage higher than the core voltage.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing.  
       BACKGROUND OF THE INVENTION  
       [0002]     In VLSI integrated circuits, particularly in the more complex circuits such as microprocessors or digital signal processors, it is often necessary to transfer signals from one voltage domain (range) to another. This may be required to be achieved at high speed and without damage to the transistors involved. The problem becomes more difficult as CMOS technology moves to lower supply voltages for the main logic of the chip, together with smaller geometries. Existing solutions generally require reference voltage supplies which must be either supplied externally or generated within the chip and therefore consume power.  
         [0003]     In view of the foregoing problems requirements, a need exists for a method and/or system for which does not suffer from the above disadvantages.  
       SUMMARY OF THE INVENTION  
       [0004]     In general, the present invention relates to a digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing comprising one or more protection transistors each having a gate, wherein the drive to the gates of the one or more protection transistors is obtained from an input stage via an R-C network, the resistor in the R-C network being referenced to a predetermined voltage.  
         [0005]     According to a first aspect of the present invention there is provided a digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing, the digital voltage level shifter comprising:  
         [0006]     a first inverter stage for generating an inverted signal from an input signal, said inverted signal having an input voltage swing between a core voltage and ground;  
         [0007]     a second inverter stage for producing an anti-phase signal from the inverted input signal, the anti-phase signal having an input voltage swing between the core voltage and ground;  
         [0008]     said first inverter driving a first thin gate NMOS transistor connected in cascode with a first NMOS transistor, said first thin gate NMOS transistor and said first NMOS transistor each having a respective gate, source and drain;  
         [0009]     said second inverter driving a second thin gate NMOS transistor connected in cascode with a second NMOS transistor, said second thin gate NMOS transistor and said second NMOS transistor each having a respective gate, source and drain;  
         [0010]     said sources of the first and second thin gate NMOS transistors being connected to ground; wherein the gate of the first NMOS transistor is connected to the output of the first inverter through a first capacitor and referenced to a predetermined voltage; the gate of the second NMOS transistor is connected to the output of the second inverter through a second capacitor and referenced to the predetermined voltage; and  
         [0011]     the drains of the NMOS transistors being connected to an output stage to provide an output signal having an output voltage swing higher than said input voltage swing.  
         [0012]     Preferably, the gate of the first NMOS transistor is referenced to the predetermined voltage through a first resistor or a first MOS transistor; and the gate of the second NMOS transistor is referenced to the predetermined voltage through a second resistor or a second MOS transistor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     Embodiments of the invention will now be described, by way of example, and with reference to the accompanying drawings, in which:  
         [0014]      FIG. 1  is a circuit diagram of a conventional system for shifting voltage signal levels to a higher range (domain); and  
         [0015]      FIG. 2  is a circuit diagram of system according to an embodiment of the invention for shifting voltage signal levels to a higher range (domain). 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0016]      FIG. 1  shows a circuit diagram of a conventional system for shifting voltage signal levels to a higher range (domain). The system comprises an inverter stage  2  comprising two CMOS transistors  4 ,  6 . The output of the inverter stage  2  is coupled to the gate of a thin gate NMOS transistor N 1 . The input signal L IN  is also coupled to the gate of a further thin gate NMOS transistor N 2 . The sources of transistors N 1  and N 2  are coupled to ground (V SSP ) and the drains of transistors N 1  and N 2  are coupled to the sources of two further NMOS transistors N 3  and N 4  respectively. The gates of transistors N 3  and N 4  are connected to a reference voltage V REF .  
         [0017]     The drain of N 3  is connected to the source of a further transistor  8  which, together with another transistor  10 , forms a second inverting stage, the output of which is coupled to a bistable circuit  12  formed by two cross-coupled transistors  14 ,  16 . The drain of N 4  is coupled to the other input to the bistable stage  12 , to the drain of a further PMOS transistor  18 , and also to an inverter stage  20  which is comprised of an NMOS transistor  21  and a PMOS transistor  22  connected in series. The output of the inverter stage  20  provides the output voltage L OUT  at the new voltage level. The output voltage L OUT  is applied to the gate of the transistor  18  which is connected to the drain of transistor N 4  and is applied to the input to the inverter stage formed by transistors  8  and  10 .  
         [0018]     The operation of the system of  FIG. 1  is as follows. The input signal L IN  is inverted in the inverter stage  2  and swings between the voltages V DDCORE , which is the voltage of the main logic supply for the system, and V SSCORE  which is ground. The output of the inverter stage  2  switches transistor N 1 . The input signal Lin also switches transistor N 2  in anti-phase to transistor N 1 . The sources of transistors N 3  and N 4  are maintained at a voltage of around (V REF -V GS ), where V GS  is the threshold potential of the protection NMOS transistors N 3  and N 4  and V REF  is a reference voltage applied from an external source.  
         [0019]     When the input signal L IN  is high, transistor N 2  is turned on, current flows through N 4  pulling the drain of transistor N 4 , which is the input to the inverter stage, to voltage V SSP  which is ground, thereby making the output L OUT  high.  
         [0020]     PMOS transistors  10 ,  18  are not conducting when L OUT  is high. Also, the gate of PMOS transistor  14  is coupled to the drain of N 4 , which is low when L IN  is high, thereby making transistor  14  conduct resulting in drain of the transistor N 8  rising to voltage supply level V DDP . The drain of N 8  is coupled to PMOS transistor  16  thereby turning it off. Also NMOS transistor  8  is conducting when L OUT  is high.  
         [0021]     However, when the input signal L IN  is high, transistor N 1  is switched off, thus there is no current path through transistors N 3 ,  8  and  10  to V SSP  which is ground. In this situation, transistor N 3  prevents the drain of transistor N 1  from rising above (V REF -V GS ), thus protecting transistor N 1  from damage due to gate-oxide stress.  
         [0022]     When the input signal L IN  changes from high to low, transistor N 1  turns on, transistor N 2  switches off and there is no current path through transistors N 4  and N 2 . As transistor N 1  turns on, current flows through transistors  8 , N 3  and  10 , thereby pulling the drain of transistor  8  to voltage level V SSP , which is ground, thereby making PMOS transistor  16  conducting and pulling the drain of transistor N 4  to voltage supply level V DDP , which is the input to the inverter stage  20 . The output of the inverter stage  20 , L OUT , is pulled down to voltage V SSP , which is ground.  
         [0023]     In this condition, when L IN  is low and L OUT  is low, PMOS transistor  18  conducts and holds the input to the inverter stage  20  to voltage supply level V DDP . Transistor N 4  prevents the drain of N 2  from rising above (V REF -V GS ) thereby protecting N 2  from damage due to gate-oxide stress. Also, transistor  8  switches off when L OUT  is low, disabling the current path through transistors  8 , N 3  and N 1  to V SSP  which is ground. PMOS transistor  10 , the gate of which is coupled to the output of inverter stage  20 , conducts and pulls the drain of the transistor  8  up to the voltage supply level V DDP .  
         [0024]     V REF  has the value equal to the sum of the smaller voltage V DDPCORE  of the main logic supply for the system plus the threshold potential V GS  of the protection NMOS transistors N 3  and N 4 . Thus, transistors N 3  and N 4  protect the transistors N 1  and N 2  from damage due to gate oxide stress.  
         [0025]      FIG. 2  shows a circuit diagram of system according to an embodiment of the invention for shifting voltage signal levels to a higher range (domain). The input signal L IN  is fed to an inverter  30  comprising two transistors  32 ,  34  which drives a further inverter  36 . The outputs of the inverters  30 ,  36  are coupled to the gates of two transistors N 1  and N 2  respectively. The sources of two protection NMOS transistors N 3  and N 4  are connected to the drains of the two transistors N 1  and N 2  respectively. The gate of the transistor N 3  is coupled to the inverted signal from the inverter stage  30  via a high-pass network comprising a capacitor C 1  and a resistor R 1  and is referenced to V DDCORE  through resistor R 1 . The signal from the inverter  30  swings between a voltage V DDCORE , which is voltage of the main logic supply for the system, and ground (V SSCORE ). In a preferred embodiment, the voltage V DDCORE  is around 0.9 Volts.  
         [0026]     Similarly, the gate of transistor N 4  is referenced to the voltage V DDCORE  via a resistor R 2  which, with a capacitor C 2 , forms a high-pass network, the further side of C 2  being coupled to the output of the inverter  36 .  
         [0027]     In this embodiment, the inverter stage  36  comprises two CMOS transistors  44 ,  46 . The output of inverter  36  is coupled to the gate of transistor N 2 . The sources of transistors N 1  and N 2  are coupled to ground (V SSP ) and the drains of transistors N 1  and N 2  are coupled to the sources of two further NMOS transistors N 3  and N 4  respectively.  
         [0028]     The drain of transistor N 3  is connected to the source of a further transistor  8  which, together with another transistor  10 , forms a further inverting stage, the output of which is coupled to a bistable circuit  12  formed by two cross-coupled transistors  14 ,  16 . The drain of transistor N 4  is coupled to the other input to the bistable stage  12 , to the drain of a further PMOS transistor  18 , and also to an inverter stage  20  which is comprised of an NMOS transistor  21  and a PMOS transistor  22  connected in series. The output of the inverter stage  20  provides the output at the new voltage level L OUT .  
         [0029]     The output voltage L OUT  is applied to the gate of the transistor  18  connected to the drain of the transistor N 4  and to the input to the inverter stage formed by transistors  8  and  10 .  
         [0030]     The operation of the system of  FIG. 2  is as follows. The input signal L IN  is inverted in the inverter stage  30  and swings between the voltages V DDCORE  and V SSCORE . The output of the inverter stage  30  switches transistor N 1 . The output of the inverter  30  is further inverted in the inverter  36  and switches transistor N 2  in anti-phase to transistor N 1 . The sources of transistors N 3  and N 4  are maintained at a voltage of approximately (V DDCORE -V GS ), where V GS  is the threshold potential of the protection NMOS transistors N 3  and N 4 .  
         [0031]     Thus, when the output of the inverter  30  rises positively, the gate of transistor N 3  rises by an amount equal to around (V DDCORE -V SSCORE ). By selection of the values of the components C 1  and R 1 , this provides the shift voltage and protection required without the need for an external reference voltage.  
         [0032]     Similarly, when L IN  rises, the output of inverter stage  36  will also rise turning transistor N 2  on and driving the gate of transistor N 4  positively via capacitor C 2  and resistor R 2  thus providing the required shift voltage and protection without the need for an external reference voltage.  
         [0033]     When the input signal L IN  is high, transistor N 2  is turned on, current flows through N 4  pulling the drain of transistor N 4 , which is the input to the inverter stage, to voltage V SSP  which is ground, thereby making the output L OUT  high.  
         [0034]     PMOS transistors  10 ,  18  are not conducting when L OUT  is high. Also, the gate of PMOS transistor  14  is coupled to the drain of N 4 , which is low when L IN  is high, thereby making transistor  14  conduct resulting in drain of the transistor N 8  rising to voltage supply level V DDP . The drain of N 8  is coupled to PMOS transistor  16  thereby turning it off. Also NMOS transistor  8  is conducting when L OUT  is high. In a preferred embodiment, V DDP  is around 2.5 Volts.  
         [0035]     However, when the input signal L IN  is high, transistor N 1  is switched off, thus there is no current path through transistors N 3 ,  8  and  10  to V SSP  which is ground. In this situation, transistor N 3  prevents the drain of transistor N 1  from rising above (V DDCORE -V GS ), thus protecting transistor N 1  from damage due to gate-oxide stress.  
         [0036]     When the input signal L IN  changes from high to low, transistor N 1  turns on, transistor N 2  switches off and there is no current path through transistors N 4  and N 2 . As transistor N 1  turns on, current flows through transistors  8 , N 3  and  10 , thereby pulling the drain of transistor  8  to voltage level V SSP , which is ground, thereby making PMOS transistor  16  conducting and pulling the drain of transistor N 4  to voltage supply level V DDP , which is the input to the inverter stage  20 . The output of the inverter stage  20 , L OUT , is pulled down to voltage V SSP , which is ground.  
         [0037]     In this condition, when L IN  is low and L OUT  is low, PMOS transistor  18  conducts and holds the input to the inverter stage  20  to voltage supply level V DDP . Transistor N 4  prevents the drain of N 2  from rising above (V DDCORE -V GS ) thereby protecting N 2  from damage due to gate-oxide stress. Also, transistor  8  switches off when L OUT  is low, disabling the current path through transistors  8 , N 3  and N 1  to V SSP  which is ground. PMOS transistors  10 , the gate of which is coupled to the output of inverter stage  20 , conducts and pulls the drain of the transistor  8  up to the voltage supply level V DDP .  
         [0038]     In summary, if either of the protection transistors N 3  or N 4  are turned off, the drain at that transistor is pulled to the higher voltage level V DDP  and the voltage at the gate of the transistor connected to the drain of that transistor goes to V SSP , thus setting the conditions of the bistable stage  12  so that the output line is pulled between a high level, namely V DDP , and V SSP  thereby enabling a high level voltage swing.  
         [0039]     In a further preferred embodiment, resistors R 1  and R 2  may be omitted and replaced by MOS transistors which are kept in the ON state. The operation of the system according to this embodiment is the same as that described above with reference to  FIG. 2 .  
         [0040]     The systems and methods according to the present invention may be particularly useful in devices having very low core voltages and to provide high speed protection to the low voltage transistors in the circuit from damage due to gate oxide stress. A quick voltage shift may be achieved without the requirement for an external reference voltage, and without static power dissipation.  
         [0041]     Various modifications to the embodiments of the present invention described above may be made. For example, other components and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to the skilled reader, without departing from the spirit and scope of the invention.