Abstract:
An integrated circuit includes a volatile memory, a central processing unit that normally operates on a first clock, and an input-output circuit that transfers data in synchronization with a second clock having a lower frequency than the first clock. The integrated circuit has a power-saving mode in which the volatile memory loses its data and the central processing unit stops operating. The power-saving mode is preceded and followed by transitional periods during which the central processing unit uses the input-output circuit to save data from the volatile memory to an external memory device and restore the data from the external memory device to the volatile memory. During these transitional periods, the central processing unit operates on the second clock to conserve power.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to the reduction of power consumption in a microelectronic system integrated onto a single chip.  
         [0003]     2. Description of the Related Art Referring to  FIG. 1 , a single-chip system  10  of this type conventionally comprises a central processing unit (CPU)  11 , a read-only memory (ROM)  12 , a random-access memory (RAM)  13 , a serial input-output interface (SIO)  14 , a clock divider (DIV)  15 , and various on-chip peripheral circuits (not shown).  
         [0004]     The CPU  11  carries out prescribed computations and control processing according to a program stored in the chip&#39;s memory (the ROM  12  and/or RAM  13 ). The ROM  12  is a nonvolatile memory that retains its data even after power is switched off. Programs stored in the ROM  12  include a bootstrap program or initial program loader (IPL), interrupt handlers that handle external interrupts, and other programs. The RAM  13  is a volatile memory that loses its data when power is switched off. The RAM  13  is used to store application programs and data being processed.  
         [0005]     The serial input-output interface  14  is used to transfer data between the CPU  11  and an external device (in this case, an external memory device  30  such as a flash memory). The serial input-output interface  14  converts parallel data received from the CPU  11  to serial data and sends the data to the external device, and converts serial data received from the external device to parallel data and supplies the data to the CPU  11 . The clock divider  15  divides the frequency (for example, 10 MHz) of a system clock SCK received from an external source to obtain a high-speed clock signal CKH (with a frequency of, for example, 5 MHz), which is supplied to the CPU  11 , and a low-speed clock signal CKL (with a frequency of, for example, 1 MHz), which is supplied to the serial input-output interface  14  and used for serial data transfer.  
         [0006]     The operation of this integrated circuit during transitions between its normal mode and a power-saving mode will now be described.  
         [0007]     When the CPU  11  has finished executing a series of processes and is ready to power down into the power-saving mode, the CPU  11  reads out the data stored in the RAM  13  and supplies the data one byte at a time to the serial input-output interface  14 . The serial input-output interface  14  converts the data received from the CPU  11  to serial data synchronized with the low-speed clock signal CKL and transfers the data to the external memory device  30 . When one byte of data has been transferred, the serial input-output interface  14  sends a transfer completion signal DON to the CPU  11 . The CPU  11  then supplies the next byte of data to the serial input-output interface  14 . When all the, necessary data have been transferred to the external memory device  30 , the CPU  11  powers off prescribed circuits, including the RAM  13 , and goes into the power-saving mode. Even in this power-saving mode, the CPU  11 , ROM  12 , and clock divider  15  remain powered so that they can detect an external interrupt INT and execute a transition from the power-saving mode to the normal mode.  
         [0008]     Upon detection of an external interrupt INT in the power-saving mode, the CPU  11  powers up the circuits that were powered off, operating according to a program stored in the ROM  12 . The CPU  11  then sends a byte data read command to the serial input-output interface  14 . The serial input-output interface  14  retrieves one byte of data from the external memory device  30  in response to the instruction, and sends a transfer completion signal DON to the CPU  11 . The CPU  11  stores the retrieved data in the RAM  13 . The CPU  11  continues to issue data read commands to the serial input-output interface  14  until all necessary data have been stored in the RAM  13 . When the necessary data have been stored in the RAM  13 , the CPU  11  resumes normal operation.  
         [0009]     A microelectronic system in which a uniform transmission speed is maintained between the microelectronic system and peripheral units even when the clock frequency is changed to conserve power is described in Japanese Patent Application Publication No. 8-234865.  
         [0010]     A problem with the integrated circuit described above is that during the transitions between the normal mode and the power-saving mode, while data are being transferred between the serial input-output interface  14  and the external memory device  30  in synchronization with the low-speed clock signal CKL supplied to the serial input-output interface  14 , the CPU  11  continues to receive the high-speed clock signal CKH. The CPU  11  therefore operates on a clock signal with a higher speed than necessary, consuming power needlessly.  
         [0011]     Moreover, the CPU  11  has to wait for an external interrupt INT and carry out a transition from the power-saving mode to the normal mode, so the high-speed clock signal CKH cannot be halted, limiting the reduction of power consumption.  
       SUMMARY OF THE INVENTION  
       [0012]     An object of the present invention is to conserve power during transitions of an integrated circuit between its normal operating mode and a power-saving mode, while data are being transferred between a volatile memory in the integrated circuit and an external memory device.  
         [0013]     The invented integrated circuit thus includes a central processing unit and a volatile memory and is connected to an external memory device. Normally, the central processing unit operates on a first clock signal and executes logic processing while the volatile memory stores data. In the power-saving mode, the central processing unit halts and the volatile memory loses its stored data. During a transition from the normal mode to the power-saving mode, the central processing unit saves data from the volatile memory to the external memory device. During a transition from the power-saving mode to the normal mode, the central processing unit restores the data from the external memory device to the volatile memory.  
         [0014]     The integrated circuit also includes a data input-output circuit that the central processing unit uses to transfer data between the volatile memory and the external memory device, and a clock divider. The clock divider divides the frequency of the first clock signal to obtain a second clock signal and supplies the second clock signal to the data input-output circuit as a data transfer clock signal.  
         [0015]     The integrated circuit also includes an interrupt detector, a selector, and a clock supply circuit. The interrupt detector detects an external interrupt. The selector selects the second clock signal in the power-saving mode and during the transitions between the power-saving mode and the normal mode, and selects the first clock signal in the normal mode. The clock supply circuit supplies the clock signal selected by the first selector to the central processing unit in the normal mode and during the transitional periods, and halts the clock supply in the power-saving mode.  
         [0016]     More specifically, during a transition from the normal mode to the power-saving mode, the clock supply circuit supplies the second clock signal to the central processing unit until it finishes saving data from the volatile memory to the external memory unit. The clock supply circuit then halts the clock supply to the central processing unit until the interrupt detector detects the external interrupt, at which point the clock supply circuit resumes supply of the second clock signal while the central processing unit restores data from the external memory device to the volatile memory. When the data restoring process is finished, the first selector selects the first clock again and the central processing unit resumes normal operation.  
         [0017]     During the transitional periods, accordingly, the central processing unit operates on the second clock signal, conserving power because the second clock signal has a lower frequency than the first clock signal. The lower frequency is adequate because during the transitional periods the central processing unit only has to keep pace with the data input-output circuit, which always operates on the second clock signal. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     In the attached drawings:  
         [0019]      FIG. 1  is a block diagram of a conventional integrated circuit;  
         [0020]      FIG. 2  is a block diagram of an integrated circuit illustrating a first embodiment of the invention;  
         [0021]      FIG. 3  is a signal waveform diagram illustrating the operation of the integrated circuit in  FIG. 2 ;  
         [0022]      FIG. 4  is a flowchart illustrating the operation of the integrated circuit in  FIG. 2  during a transition from the normal mode to the power-saving mode;  
         [0023]      FIG. 5  is a flowchart illustrating the operation of the integrated circuit in  FIG. 2  during a transition from the power-saving mode to the normal mode; and  
         [0024]      FIG. 6  is a block diagram of an integrated circuit illustrating a second embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0025]     Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.  
       First Embodiment  
       [0026]     Referring to  FIG. 2 , the integrated circuit  10  in the first embodiment has a CPU  11 , ROM  12 , RAM  13 , serial input-output interface  14 , and clock divider  15 .  
         [0027]     The CPU  11  carries out prescribed computation and control processing according to a program stored in the ROM  12  or RAM  13  in synchronization with a clock signal CLK. The ROM  12  stores a bootstrap program or IPL, interrupt handlers that handle external interrupts, and other programs, while the RAM  13  is used to store application programs and data being processed.  
         [0028]     The serial input-output interface  14  carries out data transfers between the CPU  11  and the external memory device  30  (in this case, a flash memory or the like). The serial input-output interface  14  converts the parallel data received from the CPU  11  to serial data and supplies the data to the CPU  11 . The serial input-output interface  14  sends a transfer completion signal DON to the CPU  11  upon completion of one byte of data transfer.  
         [0029]     The clock divider  15  divides the frequency of the system clock SCK (for example, 10 MHz) received from an external source to obtain a high-speed clock signal CKH (with a frequency of for example 5 MHz) and further divides the frequency of the high-speed clock signal CKH to obtain a low-speed clock signal CKL (with a frequency of, for example, 1 MHz). The low-speed clock signal CKL is supplied to the serial input-output interface  14  as a timing signal for serial data transfer.  
         [0030]     The integrated circuit  10  further comprises a selector (SEL)  16 , a logical OR gate  17 , an interrupt detector (INT DET)  18 , a set/reset type flip-flop  19 , and various peripheral circuits (not shown).  
         [0031]     The selector  16  selects one of the two clock signals CKL and CKH generated by the clock divider  15 , in response to a mode select signal PSM received from the CPU  11 . The output terminal of the selector  16  is connected to one of the input terminals of the logical OR gate  17 .  
         [0032]     The interrupt detector  18  is used to detect an external interrupt INT. The output terminal of the interrupt detector  18  is connected to the reset terminal R of the flip-flop  19 . The set terminal S of the flip-flop  19  receives a completion signal FIN from the CPU  11 , and the output terminal of the  19  is connected to the other input terminal of the logical OR gate  17 . The output signal of the logical OR gate  17  is supplied to the CPU  11  as its clock signal (CLK). The logical OR gate  17  and flip-flop  19  constitute the clock supply circuit for the CPU  11 .  
         [0033]     The operation of the integrated circuit  10  in  FIG. 2  will now be described with reference to the signal waveform diagram in  FIG. 3  and the flowcharts in  FIGS. 4 and 5 .  
       Normal Operation  
       [0034]     In normal operation, the flip-flop  19  is reset, and the signal S 19  output from the flip-flop  19  is at the low logic level (L in  FIG. 3 ). The mode select signal PSM supplied to the selector  16  from the CPU  11  is set (to the high logic level, H in  FIG. 3 , for example) to select the normal operation mode, and the high-speed clock signal CKH generated by the clock divider  15  is selected and supplied to the logical OR gate  17 . Thus the 5-MHz clock signal CKH is supplied to the CPU  11  as its clock signal CLK. The 1-MHz clock signal CKL is supplied to the serial input-output interface  14  as the data transfer clock signal.  
       Transition to Power-Saving Mode  
       [0035]     When the CPU  11  has finished executing a series of processes and is ready to power down into the power-saving mode (step  41  in  FIG. 4 ), the CPU  11  switches the mode select signal PSM (to the low logic level, for example) to select the power-saving mode (step  42 ). The low-speed clock signal CKL is selected by the selector  16  and supplied to the CPU  11  through the logical OR gate  17  as the clock signal CKL (step  43 ). Thus the frequency of the clock signal CLK supplied to the CPU  11  is reduced from 5 MHz to 1 MHz, as shown in  FIG. 3 .  
         [0036]     Operating on the 1-MHz clock signal, the CPU  11  reads one byte of the data stored in the RAM  13  (step  44 ), supplies the data to the serial input-output interface  14  (step  45 ), and gives a serial transfer command (step  46 ). Also operating on the 1-MHz clock signal, the serial input-output interface  14  converts the data received from the CPU  11  to serial data and transfers the data to the external memory device  30  (step  47 ). When the transfer of one byte of data is completed, the serial input-output interface  14  sends a completion signal DON to the CPU  11  (step  48 ). The CPU  11  then supplies the next byte of data to the serial input-output interface  14  (step  44 ). When all the necessary data have been transferred to the external memory device  30  (step  49 ), the CPU  11  sends a completion signal FIN to the flip-flop  19  (step  50 ) and powers off the RAM  13 , the serial input-output interface  14 , and other prescribed circuits (not shown) to enter the power-saving mode (step  51 ).  
       Power-Saving Operation  
       [0037]     The circuits that have been powered off stop operating and lose their stored information. When the flip-flop  19  is set by the completion signal FIN, the S 19  signal goes high, and the clock signal CLK output from the logical OR gate  17  is held fixed at the high level, as shown in  FIG. 3 . The CPU  11  then stops operating, but as its power is not switched off, the CPU  11  remains in the state it was in just before it stopped operating. The mode select signal PSM output from the CPU  11  therefore remains low. Meanwhile, the interrupt detector  18  is kept constantly powered to await the input of an external interrupt INT.  
         [0038]     Transition from Power-Saving Mode to Normal Mode Upon detection of an external interrupt INT in the power-saving mode (step  61  in  FIG. 61 ), the interrupt detector  18  resets the flip-flop  19 . The signal S 19  then goes low, and the clock signal CKL selected by the selector  16  is supplied to the CPU  11  as its clock signal CLK (step  62 ).  
         [0039]     The CPU  11  resumes operation from the state it was in before it stopped operating, and provides power to the circuits, such as the RAM  13 , that were powered off to reduce power consumption.  
         [0040]     The CPU  11  then sends a byte data read command to the serial input-output interface  14  (step  63 ). The serial input-output interface  14  retrieves one byte of data from the external memory device  30  (step  64 ), and sends a transfer completion signal DON to the CPU  11  (step  65 ). The CPU  11  stores the retrieved data in the RAM  13  (steps  66  and  67 ). The CPU  11  continues to issue data read commands to the serial input-output interface  14  (step  63 ) until all necessary data have been retrieved and stored in the RAM  13 . When the necessary data have been stored (step  68 ), the CPU  11  switches the mode select signal PSM to the normal level (step  69 , the high level in  FIG. 3 ). The high-speed clock signal CKH is then selected by the selector  16  and supplied to the CPU  11  as the clock signal CLK (step  70 ), and the CPU  11  resumes normal operation.  
         [0041]     As described above, the integrated circuit  10  in the first embodiment has a selector  16  that switches the clock signal CLK supplied to the CPU  11  to the low-speed clock signal CKL during the transitions between the power-saving mode and the normal mode. Power consumption by the CPU  11  is thereby reduced during the transfer of data between the RAM  13  and the external memory device  30 .  
         [0042]     The integrated circuit  10  also has a logical OR gate  17  that halts the clock signal CLK supplied to the CPU  11  in the power-saving mode. The CPU  11  therefore stops operating in the power-saving mode, and the power consumption of the CPU  11  is further reduced.  
         [0043]     The data transfer carried out between the integrated circuit  10  and the external memory device  30  is a serial transfer, but the invention can also be practiced with an external memory device that carries out parallel data transfer. In that case, a parallel input-output circuit should be used in place of the serial input-output interface  14 .  
         [0044]     The clock divider  15  divides the frequency of the system clock SCK by two to generate the high-speed clock signal CKH, and by ten to generate the low-speed clock signal CKL, but the invention can be practiced with other frequency division ratios. For example, it is possible to use the system clock SCK directly as the high-speed clock signal CKH without dividing the frequency.  
       Second Embodiment  
       [0045]     Referring to the block diagram in  FIG. 6 , the second embodiment adds a register (REG)  20  and a second selector  21  to the integrated circuit in the first embodiment, and uses a different clock divider  15 A, which divides the frequency of the system clock SCK to generate a plurality of low-speed divided clock signals, as well as the high-speed clock signal CKH.  
         [0046]     Selector  21  selects one of the plurality of low-speed divided clock signals generated by the clock divider  15 A according to the value set in the register  20  and outputs the selected clock signal as the low-speed clock signal CKL. The value in the register  20  is set by the CPU  11 . The high-speed clock signal CKH generated by the clock divider  15 A and the low-speed clock signal CKL selected by selector  21  are supplied to selector  16 , which selects one of the two clock signals according to the mode select signal PSM received from the CPU  11 . In other respects, the second embodiment has the same configurations as the first embodiment illustrated in  FIG. 2 .  
         [0047]     The integrated circuit in  FIG. 6  operates in the same way as the integrated circuit in  FIG. 2 , with the exception that the low-speed clock signal CKL is selected according to the value set in the register  20 .  
         [0048]     The integrated circuit in the second embodiment has a first selector  16  that switches the clock signal CLK supplied to the CPU  11  to a low-speed clock signal CKL during the transitions between the power-saving mode and the normal mode, and a logical OR gate  17  that halts the clock signal CLK supplied to the CPU  11  in the power-saving mode. Therefore, the second embodiment provides the same advantages as the first embodiment.  
         [0049]     Furthermore, the integrated circuit in the second embodiment has a register  20  and a second selector  21  for selecting the low-speed clock signal CKL. This offers the advantage that the optimal frequency of the data transfer clock signal CKL can be selected according to the data transfer rate of the external memory device.  
         [0050]     The integrated circuit in  FIG. 6  is configured to have the CPU  11  set a value in the register  20 , but it is also possible to have the value set by the external memory device, using signals from a connector connecting the serial input-output interface  14  and the external memory device, or to replace the register  20  with an external switch.  
         [0051]     Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.