Abstract:
A phase-frequency detection system and method for enhancing performance of the frequency detector in a phase-frequency detection system. Filtering of the frequency detector inputs makes operation of the frequency detector more robust in the presence of intersymbol interference within the incoming data signal and other non-ideal characteristics such as noise and crosstalk.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to data clock recovery circuits, and in particular, to phase-frequency detectors for use in detecting a clock signal associated with an incoming data signal. 
         [0003]    2. Related Art 
         [0004]    Data signals transmitted over a high speed data link, such as a backplane or cable, are often processed by receiver circuits in which a clock signal must be recovered from the binary signal. Such data signals are often transmitted using the well known non-return-to-zero (NRZ) signal format. 
         [0005]    Referring to  FIG. 1 , the clock recovery circuit often used is a phase-locked loop (PLL)  10 , implemented substantially as shown. The incoming data signal  11  is processed by a phase-frequency detector  12  which is clocked in accordance with multiple clock signals  21  (discussed in more detail below) to recover and provide the data signal  13   d , along with the associated clock signal  21   c . The phase-frequency detector  12  also provides a detection signal  13   f  related to the phase and frequency difference between the incoming data signal and the locally generated clock signal  13   c . This signal  13  (which is a combination, e.g., a linear sum, of the respective output signals of the phase detector and frequency detector that together form the phase-frequency detector  12 ) typically drives a charge pump circuit  14  which provides a voltage signal  15  which, in turn, is filtered by a low pass filter  16 . The resulting filtered signal  17  provides a control voltage for a voltage controlled oscillator (VCO)  18 , the output signal  19  of which is processed by a clock generator  20  to produce the clock signals  21  for the phase-frequency detector  12 . Depending upon the actual implementation of the phase-frequency detector  12 , many forms of which are well known in the art, the clock signals  21  will include two quadrature clock signals (i.e., having a mutual phase difference of 90 degrees), or alternatively, four clock signals, two of which have mutually quadrature phases, and two more of which also have mutually quadrature phases. (For example, one pair of clock signals will include a clock signal having a zero degree phase and another clock signal having a 90 degree phase, while the other pair of clock signals will include a clock signal having a phase of 45 degrees and another clock signal having a phase of 135 degrees.) 
       SUMMARY 
       [0006]    In accordance with the presently claimed invention, a phase-frequency detection system and method are provided for enhancing performance of the frequency detector in a phase-frequency detection system. Filtering of the frequency detector inputs makes operation of the frequency detector more robust in the presence of intersymbol interference within the incoming data signal and other non-ideal characteristics such as noise and crosstalk. 
         [0007]    In accordance with one embodiment of the presently claimed invention, a phase-frequency detector for use in detecting a clock signal associated with an incoming data signal includes: 
         [0008]    a data electrode to convey a binary data signal having a clock signal associated therewith; 
         [0009]    a plurality of clock electrodes to convey a plurality of clock signals having a like plurality of mutually dissimilar clock signal phases; 
         [0010]    phase detection circuitry coupled to the data electrode and the plurality of clock electrodes, and responsive to the binary data signal and the plurality of clock signals by providing first and second beat signals corresponding to first and second samples of one or more of the binary data signal and plurality of clock signals; 
         [0011]    filter circuitry coupled to the phase detection circuitry and responsive to the first and second beat signals by providing corresponding first and second filtered signals; and 
         [0012]    frequency detection circuitry coupled to the filter circuitry and responsive to the first and second filtered signals by providing a detection signal having a value indicative of a frequency difference between the binary data signal and at least one of the plurality of clock signals. 
         [0013]    In accordance with another embodiment of the presently claimed invention, a phase-frequency detector for use in detecting a clock signal associated with an incoming data signal includes: 
         [0014]    phase detector means for detecting a binary data signal having a clock signal associated therewith and a plurality of clock signals having a like plurality of mutually dissimilar clock signal phases to provide first and second beat signals corresponding to first and second samples of one or more of the binary data signal and plurality of clock signals; 
         [0015]    filter means for filtering the first and second beat signals to provide corresponding first and second filtered signals; and 
         [0016]    frequency detector means for detecting the first and second filtered signals to provide a detection signal having a value indicative of a frequency difference between the binary data signal and at least one of the plurality of clock signals. 
         [0017]    In accordance with still another embodiment of the presently claimed invention, a method of phase-frequency detection for use in detecting a clock signal associated with an incoming data signal includes: 
         [0018]    detecting a binary data signal having a clock signal associated therewith and a plurality of clock signals having a like plurality of mutually dissimilar clock signal phases to provide first and second beat signals corresponding to first and second samples of one or more of the binary data signal and plurality of clock signals; 
         [0019]    filtering the first and second beat signals to provide corresponding first and second filtered signals; and 
         [0020]    detecting the first and second filtered signals to provide a detection signal having a value indicative of a frequency difference between the binary data signal and at least one of the plurality of clock signals. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0021]      FIG. 1  is a function block diagram of a conventional PLL for recovering data and clock signals. 
           [0022]      FIG. 2 , is a functional block diagram of a conventional phase-frequency detector. 
           [0023]      FIG. 3  is a functional block diagram of a phase-frequency detector in accordance with a preferred embodiment of the presently claimed invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]    The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
         [0025]    Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. 
         [0026]    Referring to  FIG. 2 , one example of a conventional phase-frequency detector  12   a  includes two binary phase detectors  32   a ,  32   b  and a frequency detector  34 , interconnected substantially as shown. The phase detectors  32   a ,  32   b  are driven by the incoming data signal  11  and clock signals  21   a ,  21   b . The phase detector outputs  33   a ,  33   b  contain binary data indicating the phase of the clock signals with respect to the data signal (i.e., earlier or later in phase in the case of binary phase detectors). In some designs, the data signal  11  is sampled by the clock signals  21   a ,  21   b , while in other designs, the clock signals  21   a ,  21   b  are sampled by the data signal  11 . The resulting phase detection signals  33   a ,  33   b , which are indicative of phase differences between the incoming data signal  11  and the respective clock signals  21   a ,  21   b , are further detected by the frequency detector  34  which provides the frequency detection signal  13   f  indicative of the frequency difference between the data and clock signals. 
         [0027]    The phase detection signals  33   a ,  33   b  are beat signals. These beat signals  33   a ,  33   b  have frequencies equal to the frequency differences between the incoming data signal  11  and respective clock signals  21   a ,  21   b . However, as a practical matter, these signals  33   a ,  33   b  are not ideal beat signals due to jitter induced by intersymbol interference within the input data signal or non-ideal circuit operations due to inherent non-ideal characteristics of the circuit devices within the phase detector circuits  32   a ,  32   b . This jitter causes the outputs  33   a ,  33   b  of the phase detectors  32   a ,  32   b  to have “glitches” as a result of erroneous phase detection. For example, as the edge of the data signal approaches the edge of the clock signal in a binary phase detector, the phase detector output signal transitions between states (i.e., early and late states). However, because of the jittery nature of the edge of the data signal (due to noise and channel intersymbol interference), the phase detector signal includes glitches, e.g., although the average edge of the signal may be late, the data jitter causes the phase detector to detect the data as being early. This, in turn, causes erroneous frequency detection by the frequency detector  34  which needs to use both beat signals  33   a ,  33   b  to determine the polarity of the frequency difference between the incoming data signal  11  and clock signals  21   a ,  21   b.    
         [0028]    Referring to  FIG. 3 , a phase-frequency detector  112  in accordance with one embodiment of the presently claimed invention includes two-phase detectors  132   a ,  132   b , two low pass filter circuits  136   a ,  136   b , and a frequency detector  134 , interconnected substantially as shown. The phase detectors  132   a ,  132   b  and frequency detector  134  operate in accordance with well known principles, as discussed above, to produce phase detection signals  133   a ,  133   b . The low pass filters  136   a ,  136   b  filter out, or significantly reduce, high frequency signal transients, or glitches, in the phase detection signals  133   a ,  133   b . The filtered signals  137   a ,  137   b  are processed by the frequency detector  134 , as discussed above. Accordingly, the frequency detector  134  is now provided with substantially ideal beat signals  137   a ,  137   b , thereby producing a more stable and accurate frequency detection signal  113   f . In other words, the filtered beat signals  137   a ,  137   b  more accurately represent the average edges of the incoming data signal  11 , thereby producing a more robust frequency detection signal  113   f . Such filters  136   a ,  136   b  can be implemented in analog or digital form, and as linear or nonlinear filters, in accordance with well known principles. 
         [0029]    One form of nonlinear filtering that can be used is often referred to as “majority vote” in which the outputs  133   a ,  133   b  of the phase detectors  132   a ,  132   b  are stored in memories which retain data about a selected number of prior phase detections (i.e., early or late detections). For example, if the stored data indicates that four of the previous five phase detections were late, then the phase detector output will be late too. In other words, the linear lowpass filters  136   a ,  136   b  could be replaced by circuitry performing a moving “majority vote” operation. It will be understood that a combination of linear and nonlinear (e.g., “majority vote”) filtering operations could be used to remove the glitches from the phase detector signals. 
         [0030]    Various other modifications and alternations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.