Abstract:
A thermal shut-down circuit is provided that is monolithically integrated in a power BIMOS process wherein a vertical power PNP output transistor comprises a P-type substrate as a collector. The circuit compensates for vertical currents injected from the P-substrate into lateral transistors. A first PNP transistor has an emitter connected to a first resistor and conducts a first current. A second PNP transistor has an emitter connected to a second resistor and conducts a second current. A third resistor has one terminal coupled to the emitter of the second transistor. A fourth resistor is coupled in series with an output means, the combination thereof being coupled in parallel with the second and third resistors.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates generally to a thermal shutdown circuit and, more particularly to a monolithically integrated thermal shut-down circuit for power BiMOS processes. 
     2. Background Art 
     Many applications, e.g., automotive electronics, exist wherein an integrated circuit die is subjected to high temperatures due to on-chip power dissipation and high ambient temperatures. These integrated circuits may comprise a vertical power structure having a P-type substrate and an N-type epitaxial layer overlying the substrate. P-type regions are diffused into the epitaxial layer. PNP vertical transistors may be formed between a P-region and the substrate. Lateral PNP transistors may be formed using the P-regions and the epitaxial layer. This structure is well understood by those skilled in the art. 
     The large currents drawn through these vertical power transistors, especially during fault conditions, e.g., shorted output, can cause the integrated circuit die temperature to rise excessively. A typical method of sensing overheating of an integrated circuit die and for providing a switch function to shut down the heat generating circuitry is to compare the base-emitter voltage, V BE , of a bipolar transistor having a negative temperature coefficient with a circuit generated ΔV BE  voltage having a positive temperature coefficient. 
     This comparison may be accomplished by several different methods using bipolar transistors. One method comprises a bandgap voltage cell which generates a voltage proportional to ΔV BE  and compares it with V BE  for providing a shut-down signal. The cell comprises first and second PNP transistors having collectors coupled to ground by first and second resistors, respectively, with the resistors having identical values. The collectors are also connected to the inverting input and noninverting input, respectively, of an amplifier. The output of the amplifier is connected to the bases of both transistors. The emitter of the first transistor is coupled to a node by a third resistor and the emitter of the second transistor is connected directly to the node. A fourth resistor is coupled between the node and a supply voltage. The first transistor has its emitter scaled to some multiple value greater than the emitter of the second transistor. In a manner known to those skilled in the art, and described in detail hereinafter, a voltage across the fourth resistor is proportional to the ΔV BE  between the first and second transistors and can be used for comparison to a V BE  to accomplish a thermal shutdown function. The current through the fourth resistor however, when the cell is used in vertical output power transistor circuits, is subject to unknown quantities that causes the voltage across the fourth resistor to be an unkown quantity. 
     Any lateral PNP transistor, as used for the first and second transistor in the bandgap cell described above, can have a vertical current component collected from the P-type substrate. This occurs when the substrate is switched to a voltage level substantially equal to V CC  supplied to the P-type regions serving as emitters of the PNP transistors. This vertical current is uncontrollable and unknown in value, substantially reducing the confidence level in predicting the voltage across the fourth resistor. Furthermore, if the ΔV BE  across the fourth resistor is compared to some ΔV BE , then the bases of the first and second transistors must be two V BE  voltages below V CC  which cannot occur when the substrate is switched to V CC  and the PN diode from the substrate to any N-type epitaxial region constrains all PNP bases to be only one V BE  below V CC . Additionally, if the substrate is not switched to V CC , an unpredictable current exists due to a vertical component from the lateral emitters which is collected by the substrate in the absence of a buried layer. 
     Thus, a need exists for an improved thermal shut-down circuit that compensates for any vertical current component supplied to or from the substrate. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide an improved thermal shut-down circuit. 
     Another object of the present invention is to provide a thermal shut-down circuit that substantially eliminates any error caused by unwanted vertical current collected by or from the substrate. 
     Still another object of the present invention is to provide a thermal shutdown circuit having a well regulated current source. 
     In carrying out the above and other objects of the present invention in one form, there is provided an improved thermal shut-down circuit fabricated in monolithic integrated circuit form having a vertical structure including a P-type substrate serving as a collector of a vertical output PNP transistor. An N-type epitaxial layer overlies the substrate and serves as a base of the vertical output PNP transistor. A first lateral transistor has an emitter connected to a first resistor and conducts a first current. A second lateral transistor is scaled to some multiple value of the first transistor and has its emitter connected to a second resistor and conducts a second current, said first and second currents being substantially identical in value. A third resistor has one terminal coupled to the emitter of the second lateral transistor and conducts a third current. A fourth resistor is connected in series with a PNP transistor. The PNP transistor and fourth resistor are coupled in parallel with the second and third resistors for providing an output signal. 
     The above and other objects, features, and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates in schematic form the previously known bandgap voltage cell. 
     FIG. 2 illustrates in schematic form the preferred embodiment of the present invention. 
     FIG. 3 illustrates a top plan view of an integrated circuit die layout of one transistor in the present invention. 
     FIG. 4 illustrates a top plan view of an integrated circuit die showing another transistor in the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, the previously known bandgap voltage cell comprises PNP transistor 11 having an emitter coupled to node 12 by resistor 13, and a collector coupled to supply voltage terminal 14 by resistor 15 and also connected to the inverting input of amplifier 16. PNP transistor 17 has an emitter connected to node 12 and a collector coupled to supply voltage terminal 14 by resistor 18 and also connected to the noninverting input of amplifier 16. The output of amplifier 16 is connected to the bases of transistors 11, 17. Node 12 is coupled to supply voltage terminal 19 by resistor 20. 
     Transistor 11 is scaled in a manner known to those skilled in the art so as to carry a lower current density than transistor 17. For example, the emitter area of transistor 11 may be four times the emitter area of transistor 17. Resistors 15 and 18 have equal value. Amplifier 16 provides negative feedback in a manner well known by those skilled in the art, forcing the collector voltages of transistors 11, 17 to be equal. For these collector voltages to be equal, the current through both transistors 11, 17 must be equal. Therefore, resistor 13 will develop ΔV BE  across it corresponding to the difference in V BE  voltages of transistors 11 and 17. The current through transistors 11, 17 are summed through resistor 20, and the voltage across resistor 20 will be two ΔV BE  times the ratio of resistor 20 over resistor 13. In other words, a thermally responsive signal is provided at node 12 that is proportional to the ΔV BE  generated by the circuit. 
     In applications where the cell is monolithically integrated with a vertical power transistor structure having a P-type substrate and an N-type epitaxial layer overlying the P-type substrate, the voltage across resistor 20 becomes an unkonwn quantity. As the P-type substrate rises to a voltage substantially equivalent to that of V CC , additional unwanted current is injected from the P-substrate into the epitaxial layer. This current is then collected by P-regions diffused into the epitaxial layer. This action causes circuit imbalance and uncontrolled current through resistor 20, making the voltage at node 12 unpredictable. 
     Referring to FIG. 2, a thermal shut-down circuit in accordance with the present invention is shown which is suitable to be fabricated in monolithic integrated circuit form. PNP transistor 21 has an emitter coupled to supply voltage terminal 22 by resistor 23. PNP transistor 24 has an emitter coupled to supply voltage terminal 22 by resistor 25. Transistor 21 is scaled in a manner known to those skilled in the art so that it will carry a lower current density than transistor 24. For example, the emitter area of transistor 21 may be four times the emitter area of transistor 24. 
     PNP transistor 26 has an emitter connected to supply voltage terminal 12 and both its base and collector coupled to supply voltage terminal 27 by current source 28. The bases of transistors 21, 24, 26 are interconnected. Transistor 26 establishes a current that is mirrored by transistors 21, 24. 
     NMOS transistor 29 has a source connected to supply voltage terminal 27 and a drain connected to the collector of transistor 24. NMOS transistor 31 has a source connected to supply voltage terminal 27 and a drain connected to the collector of transistor 21. The gates of transistors 29, 31 are both connected to the collector of transistor 24. Transistors 29, 31 function as a current mirror, thereby insuring that transistors 21, 24 carry identical currents. 
     Output PNP transistor 32 has an emitter coupled to supply voltage terminal 22 by resistor 33, a collector connected to thermal shut-down signal terminal 34, and a base coupled to the emitter of transistor 21 by resistor 35. DMOS transistor 36 has a drain connected to the base of transistor 32, a gate connected to the collector of transistor 21, and a source connected to controlled current reference terminal 38 and both the gate and drain of DMOS transistor 37. The source of transistor 37 is connected to supply voltage terminal 27. Transistor 37 functions as a diode and provides a bias level for the controlled current reference signal on terminal 38. 
     NMOS transistor 39 has a drain connected to terminal 34, a source connected to supply voltage terminal 27, and a gate connected to the collector of transistor 24. Transistor 39 sets the voltage level at terminal 34 and may be any type of resistive device. 
     Since resistors 23 and 25 are substantially equal in value and transistor 21 is scaled to some multiple value greater than transistor 24, and if the currents through transistors 21, 24 are equal, then V BE  of transistor 21 must be less than V BE  of transistor 24 by ΔV BE . ΔV BE  is defined as 
     
         ΔV.sub.BE =(KT/q)1n n, 
    
     where n is the ratio of emitter area of transistors 21, 24, K is Boltzman&#39;s constant, T is absolute temperature, and q is the charge of an electron. If ΔV BE  did not occur, then the current through transistor 21 would be greater than that through transistor 24. Thus, the current through transistor 31 would be less than that through transistor 21 and the voltage on the collector of transistor 21 would rise. Transistor 36 would turn on, pulling current through resistors 23, 35 and lowering V BE  of transistor 21. 
     Equating the voltages in the circuit of FIG. 2 gives: 
     
         I.sub.24 R.sub.25 +V.sub.BE24 =I.sub.21 R.sub.23 +V.sub.BE21 +I.sub.36 R.sub.23 
    
     where, 
     I 24  is the current through transistor 24 
     I 21  is the current through transistor 21 
     I 36  is the current through transistor 36 
     R 25  is the resistance of resistor 25 
     R 23  is the resistance of resistor 23 
     V BE24  is the base-emitter voltage of transistor 24 
     V BE21  is the base-emitter voltage of transistor 21. 
     However, 
     
         R.sub.23 =R.sub.25 and I.sub.24 =I.sub.21. 
    
     Therefore, 
     
         V.sub.BE24 =V.sub.BE21 +I.sub.36 R.sub.23 
    
     and 
     
         V.sub.BE24 -V.sub.BE21 =I.sub.36 R.sub.23, 
    
     or 
     
         ΔV.sub.BE =I.sub.36 R.sub.23 , 
    
     or 
     
         KT/q1n n=I.sub.36 R.sub.23. 
    
     Now 
     
         (I.sub.21 +I.sub.36)R.sub.23 +I.sub.36 R.sub.35 =V.sub.BE32 +I.sub.32 R.sub.33, 
    
     where 
     R 35  is the resistance of resistor 35 
     R 33  is the resistance of resistor 33 
     V BE32  is the base-emitter voltage of transistor 32 
     I 32  is the current through transistor 32. 
     However 
     
         R.sub.33 =R.sub.23 and I.sub.21 =I.sub.32. 
    
     Therefore 
     
         I.sub.36 (R.sub.23 +R.sub.35)=V.sub.BE32, 
    
     but 
     
         I.sub.36 =(ΔV.sub.BE /R.sub.23). 
    
     Therefore 
     
         V.sub.BE32 =ΔV.sub.BE (R.sub.23 +R.sub.35 /R.sub.23) 
    
     or 
     
         V.sub.BE32 =ΔV.sub.BE (1+R.sub. 35 /R.sub.23). 
    
     Referring to FIGS. 3 and 4, it may be seen how transistor 21 may be scaled to some multiple value greater than transistor 24. A plurality of base regions 41 comprises an N-type epitaxial layer overlying a P-type substrate (not shown). A P-type collector region 42 and a plurality of P-type emiter regions 43 are diffused into the epitaxial layer 41. This multi-emitter structure is well known to those skilled in the art. Referring to FIG. 4, transistor 24 includes a base region 44 comprising an N-type exitaxial layer. A P-type collector region 45 and a single P-type emitter region 46 is diffused into the epitaxial layer 44. Transistor 24 may have any number of emitter regions 46, even though only one is shown. transistor 21 is understood to have any integral multiple emitter regions to that of transistor 24. 
     Collector regions 42 and 45 are shown to have a box matrix configuration. However, any type of configuration would be sufficient as long as the area of the collector regions 42, 45 are substantially identical. These collector regions 42 and 45 would collect electrons injected into epitaxial layers 41, 44 by the P-substrate when the voltage on the P-substrate rises to V CC . This process is disclosed in application Ser. No. 582,356 filed concurrently with this application. 
     Referring again to FIG. 2, the following analysis will demonstrate that any current injected into the circuit from the P-substrate will have no effect on the thermal shut-down signal at terminal 34. With the feedback circuit in equilibrium, the lateral collector currents of transistors 21, 24 through transistors 31, 29, respectively, are forced to be equal. The substrate currents to collector regions 42, 45 will also be equal due to their identical configuration, even though of unknown value. 
     Equating the voltages gives: 
     
         (I.sub.L24 +I.sub.S24) R.sub.25 +V.sub.BE24 =(I.sub.L21 +I.sub.S21) R.sub.23 +I.sub.R35 R.sub.35 +V.sub.BE21 
    
     where 
     I L24  is the lateral current through transistor 24 
     I L21  is the lateral current through transistor 21 
     I S24  is the vertical (substrate) current through transistor 24 
     I S21  is the vertical (substrate) current through transistor 21 
     R 23  is the resistance of resistor 23 
     R 25  is the resistance of resistor 25 
     R 35  is the resistance of resistor 35 
     V BE24  is the base-emitter voltage of transistor 24 
     V BE21  is the base-emitter voltage of transistor 21 
     I R35  is the current through resistor 35. Cancelling the (I L24  +I S24 ) and (I L21  +I S21 ) terms since the lateral and vertical currents are equal and R 25  and R 23  are equal and simplifying gives 
     
         I.sub.R35 R.sub.35 =V.sub.BE24 -V.sub.BE21. 
    
     Therefore 
     
         I.sub.R35 R.sub.35 =ΔV.sub.BE 
    
     and since 
     
         ΔV.sub.BE =(kT/q)1n n, 
    
     then 
     
         I.sub.R35 R.sub.35 =(KT/q)1n n. 
    
     Now 
     
         (I.sub.L21 +I.sub.S21 +I.sub.36)R.sub.23 +I.sub.36 R.sub.35 =V.sub.BE32 +I.sub.32 R.sub.33 
    
     where 
     I 36  is the current through transistor 36 
     I 32  is the current through transistor 36 
     R 33  is the resistance of resistor 33 
     V BE32  is the base-emitter voltage of transistor 32. 
     However 
     
         R.sub.33 =R.sub.23 and I.sub.L24 +I.sub.S21 =I.sub.32. 
    
     Therefore 
     
         V.sub.BE =I.sub.36 (R.sub.23 +R.sub.35), 
    
     but 
     
         I.sub.36 =(ΔV.sub.BE /R.sub.23). 
    
     Therefore 
     
         V.sub.BE32 =ΔV.sub.BE (R.sub.23 +R.sub.35 /R.sub.23) 
    
     or 
     
         V.sub.BE32 =ΔV.sub.BE (1+(R.sub.35 /R.sub.23 ). 
    
     Therefore, when the voltage 
     
         (R.sub.23 +R.sub.35)KT/(R.sub.23)q1n n 
    
     increases with temperature and becomes equal to the decreasing V BE  of transistor 32, a signal at the collector of transistor 32 goes to a high state, initiating a shut-down of heat generating circuitry, i.e. the output power transistor. 
     Since the current through resistor 35 is independent of PNP parasitic substrate current, lateral current and the magnitude of the supply voltage, the circuit also provides an excellent well controlled bias current reference for other chip functions. The current through resistor 35 flows through transistors 36, 37, and provides a well regulated current reference at terminal 38. This current may be used to drive other chip functions. Transistor 37 sets the voltage level at terminal 38 and may be any type of resistive device. 
     By now it should be appreciated that there has been provided an improved thermal shut-down circuit that is monolithically integrated in a configuration including a P-type substrate as the collector of a power output transistor. The thermal shut-down circuit is self compensating for electrons injected into an N-type epitaxial layer by the substrate when a substrate voltage approaches V CC .