Abstract:
A high voltage generating circuit is described that includes, a control signal generating circuit for generating a first control signal in a first time period, and for generating second, third and fourth control signals in second, third and fourth time periods in this order; first, second and third pre-charge circuit for pre-charging first, second and third nodes in response to the first control signal; first and second step-up and charge transferring circuits for stepping up the first and third nodes in response to the second control signal and for performing a charge sharing operation between the first and second nodes and between the third and fourth nodes; a third step-up and charge transferring circuit for stepping up the second node in response to the third control signal and for performing a charge sharing operation between the second and fourth nodes; a pre-charge and charge supplying circuit for pre-charging the fourth node and for supplying charges to the fourth node; and a fourth step-up and charge transferring means for stepping up the fourth node in response to the fourth control signal and for transferring charges of the fourth node to a high voltage generating terminal.

Description:
[0001]    This application claims priority from Korean Priority Document No. 2001-65522, filed on Oct. 23, 2001, which is hereby incorporated by reference in its entirety.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Technical Field  
           [0003]    This disclosure relates to a high voltage generating circuit, and more particularly, to a high voltage generating circuit for a semiconductor memory device.  
           [0004]    2. Background  
           [0005]    A high voltage generating circuit for a semiconductor memory device generally generates a high voltage this is higher than a power voltage that is externally provided. The high voltage generating circuit is used to transfer a signal having a power voltage level without causing a threshold voltage loss when a high voltage generated therefrom is applied to a gate of an NMOS transistor that is a component of circuits such as a word line driver, a bit line isolation circuit, or a data output buffer.  
           [0006]    A memory cell of a conventional dynamic semiconductor memory device includes a capacitor for storing a data and an NMOS transistor that turns on in response to a signal applied to a word line to transfer data between a bit line and the capacitor. However, the NMOS transistor has a disadvantage in that a threshold voltage loss occurs when a signal having a power voltage level is transferred. Hence, a high voltage is applied to the word line in response to an active command in order to transfer data without causing a threshold voltage loss.  
           [0007]    [0007]FIG. 1 is a circuit diagram illustrating a conventional high voltage generating circuit. The high voltage generating circuit of FIG. 1 includes a pulse signal generating circuit  10 , NMOS transistors N 1 , and N 2 −1 to N 2 −n, and CMOS capacitors C 11  to C 1 n.  
           [0008]    The pulse signal generating circuit  10  repeatedly generates pulse signals P 1  and P 2  which have a phase opposite to each other. Each of the capacitors C 11  to C 1 n steps up nodes n 1  to nn in response to the pulse signals P 1  and P 2 . The NMOS transistor N 1  is diode connected and transfers a voltage VDD−VT to the node n 1 . The NMOS transistors N 2 - 1  to N 2 −n transfer voltages of the nodes n 1  to nn to the nodes n 2  to nn and a high voltage generating terminal in response to voltages applied to the nodes n 1  to nn, respectively.  
           [0009]    Operation of the high voltage generating circuit of FIG. 1 is described with reference to a timing diagram of FIG. 2.  
           [0010]    The node n 1  is pre-charged to a voltage level VDD−VT. Here, the voltage VT represents a threshold voltage level of the NMOS transistor N 1 .  
           [0011]    During a time period T 1 , the odd nodes n 1  and n(n−1) are boosted to a voltage level VDD−VT in response to the pulse signal P 1  having a logic “high” level. The boosted voltage is transferred to the even nodes n 2  and nn through the NMOS transistors N 2 −1 to N 2 −(n−1). The even nodes n 2  and nn become pumped to a voltage level 2 VDD−2 VT.  
           [0012]    During a time period T 2 , the even nodes n 2  and nn are boosted to a voltage level 3 VDD−2 VT. The boosted voltage is transferred to the nodes n 3  (not shown) to n(n−1) and the high voltage generating terminal through the NMOS transistors N 2 −2 to N 2 −n. The nodes n 3  to n(n−1) and the high voltage generating terminal become a voltage level 3 VDD−3 VT.  
           [0013]    However, the high voltage generating circuit of FIG. 1 has to experience an n-number of stages so as to boost a high voltage VPP. Therefore, power consumption is increased, and the high voltage cannot be generated fast within a desired time.  
           [0014]    [0014]FIG. 3 is a schematic view illustrating another conventional high voltage generating circuit. The high voltage generating circuit of FIG. 3 includes a control signal generating circuit  20 , pre-charge circuits  22  and  24 , capacitors C 2  and C 3 , level shifters  26  and  28 , and NMOS transistors N 3  and N 4 .  
           [0015]    The high voltage generating circuit of FIG. 3 shows a configuration illustrating a two-stage step-up circuit having a pre-charge circuit.  
           [0016]    The control signal generating circuit  20  generates a pulse signal P 3  having a phase opposite to an active command ACT, and generates pulse signals P 4  and P 5  which have a phase opposite to each other when the active command ACT having a logic “high” level is applied. The pre-charge circuits  22  and  24  pre-charge nodes A and B in response to the pulse signal P 3 , respectively. The capacitors C 2  and C 3  step up the nodes A and B in response to the pulse signals P 4  and P 5 , respectively. The NMOS transistors N 3  and N 4  are turned on in response to output signals of the level shifters  26  and  28  to transfer voltages of the nodes A and B.  
           [0017]    Operation of the high voltage generating circuit of FIG. 3 is described with reference to a timing diagram of FIG. 4.  
           [0018]    During a time period T 3 , when the active command ACT having a logic “low” level is applied, the pulse signal P 3  having a logic “high” level is generated from the control signal generating circuit  20 . The pre-charge circuits  22  and  24  pre-charge the nodes A and B to a voltage level VDD when the pulse signal P 3  having a logic “high” level is generated.  
           [0019]    During a time period T 4 , when the active command ACT having a logic “high” level is applied, the control signal generating circuit  20  generates the pulse signal P 4  having a logic “high” level. When the pulse signal P 4  having a logic “high” level is generated, a voltage of the node A is boosted to a voltage level 2 VDD by the capacitor C 2 . The level shifter  26  shifts a voltage level of the pulse signal P 4  from a power voltage (VDD) level to a high voltage level. The NMOS transistor N 3  is turned on in response to the high voltage level. As a result, a charge sharing operation is performed between the nodes A and B so that the voltages of the nodes A and B become a voltage level 1.5 VDD.  
           [0020]    During a time period T 5 , the pulse signal P 4  having a logic “low” level and the pulse signal P 5  having a logic “high” level are generated from the control signal generating circuit  20 . When the pulse signal P 5  having a logic “high” level is generated, a voltage of the node B is boosted to a voltage level 2.5 VDD by the capacitor C 3 . The level shifter  28  shifts a voltage level of the pulse signal P 5  from the power voltage level to the high voltage level. The NMOS transistor N 4  is turned on in response to the high voltage level. As a result, the charge sharing operation is performed between the node B and the high voltage generating terminal so that a level of the high voltage is boosted.  
           [0021]    The high voltage generating circuit of FIG. 3 can boost a voltage of the node B, which is a voltage-boosting node, to a voltage level 2.5 VDD. That is, the high voltage generating circuit of FIG. 3 can boost a voltage of the voltage-boosting node higher than that of FIG. 1 and is faster in voltage-boosting timing than that of FIG. 1.  
           [0022]    The high voltage generating circuit of FIG. 3 has no problem when the power voltage is high. However, as a level of a power voltage VDD of the semiconductor memory device is decreased due to lower power level requirements, a level of the high voltage VPP is decreased. Therefore, since the decreasing of the power voltage VDD is greater than the decreasing of the high voltage VPP, it is not easy to generate a high voltage VPP having a desired level by the high voltage generating circuit of FIG. 3.  
         SUMMARY OF THE INVENTION  
         [0023]    Embodiments of the present invention provide a high voltage generating circuit and method which can quickly boost the high voltage to a desired level even though a level of a power voltage is lowered.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]    For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which:  
         [0025]    [0025]FIG. 1 is a circuit diagram illustrating a conventional high voltage generating circuit;  
         [0026]    [0026]FIG. 2 is a timing diagram illustrating an operation of the high voltage generating circuit of FIG. 1;  
         [0027]    [0027]FIG. 3 is a schematic view illustrating another conventional high voltage generating circuit;  
         [0028]    [0028]FIG. 4 is a timing diagram illustrating an operation of the high voltage generating circuit of FIG. 3;  
         [0029]    [0029]FIG. 5 is a schematic view illustrating a high voltage generating circuit according to an embodiment of the present invention;  
         [0030]    [0030]FIG. 6 is a timing diagram illustrating an operation of the high voltage generating circuit of FIG. 5;  
         [0031]    [0031]FIG. 7 is a circuit diagram illustrating a high voltage generating circuit according to another embodiment of the present invention;  
         [0032]    [0032]FIG. 8 is a timing diagram illustrating an operation of the high voltage generating circuit of FIG. 7;  
         [0033]    [0033]FIG. 9 is a circuit diagram illustrating a high voltage generating circuit according to another embodiment of the present invention; and  
         [0034]    [0034]FIG. 10 is a timing diagram illustrating an operation of the high voltage generating circuit of FIG. 9. 
     
    
     DETAILED DESCRIPTION  
       [0035]    Reference will now be made in detail to preferred embodiments of the present invention, example of which is illustrated in the accompanying drawings.  
         [0036]    [0036]FIG. 5 is a schematic view illustrating a high voltage generating circuit according to an embodiment of the present invention. The high voltage generating circuit includes a control signal generating circuit  30 , pre-charge circuits  32 - 1  to  32 - 3 , capacitors C 4  to C 7 , level shifters  34 - 1  to  34 - 4 , and NMOS transistors N 5  to N 9 .  
         [0037]    The control signal generating circuit  30  generates a pulse signal P 6  having a phase opposite to a phase of an active command ACT, and generates pulse signals P 7  to P 9  having a logic “high” level in different phase while the active command ACT having a logic “high” level is applied. The pre-charge circuits  32 - 1  to  32 - 3  pre-charge nodes C to E to a voltage level VDD in response to the pulse signal P 6  having a logic “high” level, respectively. The NMOS transistor N 9  pre-charges a node F to a voltage level VDD−VT at the initial stage, and makes the node F become a level of a high voltage VPP by the pulse signal P 9  having a logic “high” level. Here, the voltage VT represents a threshold voltage of the NMOS transistor N 9 . Thereafter, the pulse signal P 9  transits to a logic “low” level, the node F goes to a voltage level VPP-VDD. That is, the NMOS transistor N 8  is turned on to step up the high voltage VPP, and then a voltage of the node F is lowered to a voltage level VPP−VDD. Here, when a voltage level VPP−VDD of the node F is lower than a voltage level VDD, a charge loss of the node F is compensated. The capacitors C 4  and C 6  step up the nodes C and E to a voltage level 2 VDD in response to the pulse signal P 7  having a logic “high” level. The capacitor C 5  steps up the node D to a voltage level 2 VDD in response to the pulse signal P 8  having a logic “high” level. The capacitor C 7  steps up the node F to a voltage level 2 VDD in response to the pulse signal P 9  having a logic “high” level. The level shifters  34 - 1  and  34 - 3  shift a voltage level of the pulse signal P 7  from a voltage level VDD having a logic “high” level to a voltage level VPP. The level shifter  34 - 2  shifts a voltage level of the pulse signal P 8  from a voltage level VDD having a logic “high” level to a high voltage level VPP. The NMOS transistor N 5  is turned on in response to a high voltage level VPP output from the level shifter  34 - 1  to make a charge sharing operation be formed between the nodes C and D. The NMOS transistor N 6  is turned on in response to a high voltage level VPP output from the level shifter  34 - 2  to make a charge sharing operation be formed between the nodes D and F. The NMOS transistor N 7  is turned on in response to a high voltage level VPP output from the level shifter  34 - 3  to make a charge sharing operation be formed between the nodes E and F.  
         [0038]    The NMOS transistor N 8  is turned on in response to a high voltage level VPP output from the level shifter  34 - 4 . Charges of the node F are transferred to a high voltage generating terminal to step-up the high voltage VPP.  
         [0039]    Operation of the high voltage generating circuit of FIG. 5 is described with reference to a timing diagram of FIG. 6.  
         [0040]    When the active command ACT is applied, the control signal generating circuit  30  generates the pulse signal having a phase opposite to a phase of the active command ACT. When the active command having a logic “high” level is applied, the pulse signal P 7  having a power voltage level VDD, the pulse signal P 8  having a power voltage level VDD, and the pulse signal P 9  having a power voltage level VDD are generated in time periods T 7 , T 8 , and T 9 , respectively, in this order.  
         [0041]    When the active command ACT having a logic “low” level is applied in a time period T 6  after the operation is repeatedly performed by several times to tens of times, the pulse signal P 6  having a logic “high” level is generated from the control signal generating circuit  30 . Thus, the pre-charge circuits  32 - 1  to  32 - 3  operate to pre-charge the nodes C, D and E and make the node F become a voltage level VPP−VDD.  
         [0042]    When the pulse signal P 7  of a power voltage level VDD having a logic “high” level is generated in the time period T 7 , the node C is stepped up to a voltage level 2 VDD by the capacitor C 4 . The level shifter  34 - 1  shifts a voltage level of the pulse signal P 7  from the power voltage level VDD to a high voltage level VPP. Thus, the NMOS transistor N 5  is turned on so that the charge sharing operation is performed between the nodes C and D. As a result, a voltage level of the nodes C and D go to a voltage level 1.5 VDD. The node E is stepped up to a voltage level 2 VDD by the capacitor C 6 . The level shifter  34 - 3  shifts a voltage level of the pulse signal P 7  from a power voltage level VDD to a high voltage level VPP. The NMOS transistor N 7  is turned on so that the charge sharing operation is performed between the nodes E and F. As a result, the nodes E and F become a voltage level 0.5 VPP+0.5 VDD.  
         [0043]    When the pulse signal P 8  of a power voltage level VDD having a logic “high” level is generated in the time period T 8 , the nodes D and E are stepped up to a voltage level 2.5 VDD by the capacitor C 5 . The level shifter  34 - 2  shifts a voltage level of the pulse signal P 8  from the power voltage VDD to a high voltage level VPP. The NMOS transistor N 6  is turned on so that the charge sharing operation is performed between the nodes D and F. As a result, the nodes D and F become a voltage level 0.25 VPP+1.5 VDD.  
         [0044]    When the pulse signal P 9  of a power voltage level VDD having a logic “high” level is generated in the time period T 9 , the node F is stepped up to a voltage level 0.25 VPP+2.5 VDD by the capacitor C 7 . The level shifter  34 - 4  shifts a voltage level of the pulse signal P 9  from the power voltage VDD to a high voltage level VPP. The NMOS transistor N 8  is turned on so that charges of the node F are transferred to a high voltage generating terminal to thereby generate a high voltage VPP.  
         [0045]    The high voltage VPP is generated by repeatedly performing the above-described operation.  
         [0046]    The high voltage generating circuit of FIG. 5 can step up a high voltage level VPP to a desired voltage level by stepping up a voltage level of the node F to a voltage level 0.25 VPP+2.5 VDD even though a power voltage level VDD is lowered. That is, the conventional high voltage generating circuit of FIG. 3 steps up the voltage-boosting node to a voltage level 2.5 VDD, whereas the high voltage generating circuit of FIG. 5 can boost the voltage-boosting node to a voltage level 0.25 VPP+2.5 VDD.  
         [0047]    [0047]FIG. 7 is a circuit diagram illustrating a high voltage generating circuit according to another embodiment of the present invention. The high voltage generating circuit of FIG. 7 is configured such that a pre-charge circuit  32 - 4  is added to and the NMOS transistor N 9  is removed from a circuit configuration of the high voltage generating circuit of FIG. 5.  
         [0048]    The pre-charge circuit  32 - 4  serves to pre-charge the node F at the time when the nodes C, D and E are pre-charged.  
         [0049]    Like reference numerals of FIGS. 5 and 7 denote like parts. Operation of the high voltage generating circuit of FIG. 7 is described with reference to a timing diagram of FIG. 8.  
         [0050]    Pulse signals P 6  to P 9  of FIG. 8 are generated in the same way as those of FIG. 6. When the active command ACT having a logic “low” level is applied in a time period T 6 , the control signal generating circuit  30  generates the pulse signal P 6  having a logic “high” level so that the pre-charge circuits  32 - 1  to  32 - 4  pre-charge the nodes C to F.  
         [0051]    When the pulse signal P 7  of a power voltage level VDD having a logic “high” level is generated in the time period T 7 , the node C is stepped up to a voltage level 2 VDD by the capacitor C 4 . The level shifter  34 - 1  shifts a voltage level of the pulse signal P 7  from the power voltage level VDD to a high voltage level VPP. Thus, the NMOS transistor N 5  is turned on so that the charge sharing operation is performed between the nodes C and D. As a result, a voltage level of the nodes C and D go to a voltage level 1.5 VDD. The node E is stepped up to a voltage level 2 VDD by the capacitor C 6 . The level shifter  34 - 3  shifts a voltage level of the pulse signal P 7  from a power voltage level VDD to a high voltage level VPP. The NMOS transistor N 7  is turned on so that the charge sharing operation is performed between the nodes E and F. As a result, the nodes E and F become a voltage level 1.5 VDD.  
         [0052]    When the pulse signal P 8  of a power voltage level VDD having a logic “high” level is generated in the time period T 8 , the nodes D and E are stepped up to a voltage level 2.5 VDD by the capacitor C 5 . The level shifter  34 - 2  shifts a voltage level of the pulse signal P 8  from the power voltage VDD to a high voltage level VPP. The NMOS transistor N 6  is turned on so that the charge sharing operation is performed between the nodes D and F. As a result, the nodes D and F become a voltage level 2 VDD.  
         [0053]    When the pulse signal P 9  of a power voltage level VDD having a logic “high” level is generated in the time period T 9 , the node F is stepped up to a voltage level 3 VDD by the capacitor C 7 . The level shifter  34 - 4  shifts a voltage level of the pulse signal P 9  from the power voltage VDD to a high voltage level VPP. The NMOS transistor N 8  is turned on so that charges of the node F are transferred to a high voltage generating terminal, whereby a high voltage VPP is stepped up.  
         [0054]    The high voltage generating circuit of FIG. 7 can step up a high voltage level VPP to a desired voltage level by stepping up a voltage level of the node F to a voltage level 3 VDD. That is, the high voltage generating circuit of FIG. 7can step up the high voltage higher than that of FIG. 3.  
         [0055]    The high voltage generating circuits of FIGS. 5 and 7 can step up a high voltage to a desired level even though a power voltage level VDD is lowered. However, the high voltage generating circuits of FIGS. 5 and 7 cannot perform a step up operation faster than that of FIG. 3 because a step-up operation is performed through three steps per time period that the active command ACT having a logic “high” level is applied. That is, as shown in FIGS. 6 and 8, since the high voltage step-up operation is performed in the time period, the inventive high voltage generating circuit cannot perform a step-up operation faster than that of FIG. 3.  
         [0056]    [0056]FIG. 9 is a circuit diagram illustrating a high voltage generating circuit according to another embodiment of the present invention. The high voltage generating circuit includes a control signal generating circuit  40 , an inverter INV, pre-charge circuits  42 - 1  to  42 - 3 , capacitors C 8  to C 11 , level shifters  44 - 1  to  44 - 4 , and NMOS transistors N 10  to N 14 .  
         [0057]    The control signal generating circuit  40  generates a pulse signal P 10  having a phase opposite to a phase of an active command ACT, and generates pulse signals P 11  and P 12  having a logic “high” level in different phase while the active command ACT having a logic “high” level is applied. The inverter INV inverters the pulse signal P 10  to generate a pulse signal P 10 B. The pre-charge circuits  42 - 1  and  42 - 2  pre-charge nodes G and I in response to the pulse signal P 10 B, respectively. The pre-charge circuit  42 - 3  pre-charges a node H in response to the pulse signal P 12 . The NMOS transistor N 14  pre-charges a node J to a voltage level VDD−VT at the initial stage, and supplies charges to the node J when a voltage level of the node J is lower than a power voltage level. The capacitor C 8  steps up a node G in response to the pulse signals P 10 . The level shifter  44 - 1  shifts a voltage level of the pulse signal P 10  from a voltage level VDD having a logic “high” level to a voltage level VPP. The NMOS transistor N 10  is turned on in response to an output signal of the level shifter  44 - 1  to make a charge sharing operation be formed between the nodes G and H. The capacitor C 9  steps up a node H in response to the pulse signal P 11 . The level shifter  44 - 2  shifts a voltage level of the pulse signal P 11  from a voltage level VDD having a logic “high” level to a voltage level VPP. The NMOS transistor N 11  is turned on in response to an output signal of the level shifter  44 - 2  to make a charge sharing operation be formed between the nodes H and J. The capacitor C 10  steps up the node I in response to the pulse signal P 10 . The level shifter  44 - 3  shifts a voltage level of the pulse signal P 10  from a voltage level VDD having a logic “high” level to a voltage level VPP. The NMOS transistor N 12  is turned on in response to an output signal of the level shifter  44 - 3  to make a charge sharing operation be formed between the nodes I and J. The capacitor C 11  steps up the node J in response to the pulse signal P 12 . The level shifter  44 - 4  shifts a voltage level of the pulse signal P 12  from a voltage level VDD having a logic “high” level to a voltage level VPP. The NMOS transistor N 13  is turned on in response to an output signal of the level shifter  44 - 4  to transfer the boosted voltage of the node J to a high voltage generating terminal.  
         [0058]    Operation of the high voltage generating circuit of FIG. 9 is described with reference to a timing diagram of FIG. 10.  
         [0059]    When the active command ACT is applied, the control signal generating circuit  40  generates the pulse signal P 10  having a phase opposite to a phase of the active command ACT and the pulse signal P 10 B having the same phase as a phase of the active command ACT. Also, the pulse signal P 11  having a power voltage level VDD is generated in a time period T 11 , and the pulse signal P 12  having a power voltage level VDD having a power voltage level VDD is generated in a time period T 12 .  
         [0060]    In the time period T 10  after the operation is repeatedly performed by several times to tens of times, the capacitors C 8  and C 10  perform a step-up operation in response to the pulse signal P 10  having a power voltage level to step up the nodes G and I to a voltage level 2 VDD. The level shifters  44 - 1  and  44 - 3  shift a voltage level of the pulse signal P 10  from a power voltage level to a high voltage level. The NMOS transistors N 10  and N 12  are turned on in response to a signal having a high voltage level VPP to perform a charge sharing operation of the nodes G and H, and I and J. Therefore, the nodes G and H become a voltage level 1.5 VDD, and the nodes I and J become a voltage level 0.5 VDD+0.5 VPP.  
         [0061]    In the time period T 11 , the capacitor C 9  performs a step-up operation in response to the pulse signal P 11  having a power voltage level VDD to step up the node H to a voltage level 2.5 VDD. The level shifter  44 - 2  shifts a voltage level of the pulse signal P 11  from a power voltage level to a high voltage level. The NMOS transistor N 11  is turned on in response to a signal having a high voltage level VPP to perform a charge sharing operation of the nodes H and J. Therefore, the nodes H and J become a voltage level 1.5 VDD+0.25 VPP.  
         [0062]    In the time period T 12 , the capacitor C 11  performs a step-up operation in response to the pulse signal P 12  having a power voltage level VDD to step up the node J to a voltage level 2.5 VDD+0.25 VPP. The level shifter  44 - 4  shifts a voltage level of the pulse signal P 12  from a power voltage level to a high voltage level. The NMOS transistor N 13  is turned on in response to a signal having a high voltage level VPP to perform a charge sharing operation between the node J and a high voltage generating terminal. Therefore, the node J becomes a high voltage level VPP.  
         [0063]    The high voltage VPP is generated by repeatedly performing the above-described operation.  
         [0064]    The high voltage generating circuit of FIG. 9 can step up a high voltage level VPP to a desired voltage level even though a power voltage level VDD is lowered because it is possible to step up a voltage level of the node J, which is a voltage-boosting node, to a voltage level 2.5 VDD+0.25 VPP.  
         [0065]    In addition, the high voltage generating circuit of FIG. 9 performs a step-up operation one time in the time period that the active command ACT having a logic “low” level is applied and two times in the time period T 12  that the active command ACT having a logic “high” level is applied. Therefore, the voltage generating circuit of FIG. 9 performs a step-up operation total three times. Therefore, as shown in FIG. 10, the high voltage generating circuit of FIG. 9 performs a step-up operation two times in the time period that the active command is applied, and can perform a step-up operation faster than those of FIGS. 5 and 7 by setting the time period T 11  to be longer than the time period T 12 .  
         [0066]    As described above, even though a power voltage level is lowered, the inventive high voltage generating circuit and method can generate a high voltage having a desired voltage level. In addition, the inventive high voltage generating circuit and method can perform a high voltage step-up operation faster.  
         [0067]    While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.