Abstract:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of multiple, polysilicon mesa structures, as well as polysilicon spacers, on the sides of the polysilicon mesas, with the polysilicon spacers protruding above the top surface of the polysilicon mesas. This is accomplished by initially creating a composite mesa structure, of an insulator layer, on a partially etched polysilicon layer. After creation of the polysilicon spacer, on the sides of the composite, mesa structure, the insulator is selectively removed, resulting in polysilicon mesas, with protruding polysilicon spacers. This storage node configuration results in an significant increase of surface area, when compared to storage nodes fabricated with flat topographies.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     The present invention relates to methods used for fabrication of high density, semiconductor memory cells, and more specifically to a process used to create a stacked capacitor, DRAM structure, with increased capacitance resulting from an increased surface capacitor surface area. 
     (2) Description of the Prior Art 
     The objectives of the semiconductor industry are to continually improve device performance, while still attempting to decrease the manufacturing cost of specific semiconductor chips. These objectives have been in part realizedby the ability of the semiconductor industry to produce chaps with sub-micron features, or mtcro-miniaturization. Smaller features allow the reduction in performance degrading capacitances and resistances to be realized. In addition smaller features result in a smaller chip, however possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip. 
     The use of smaller features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, and thus limiting the amount of area the overlying STC structure can occupy, without interfering with neighboring cells. 
     Solutions to the shrinking design area, assigned to STC structures, have been addressed via novel semiconductor fabrication processes which result in an increase in surface area for only the lower, or storage electrode, of the STC structure, while maintaining the area original design area of the STC structure. One method for achieving this objective been accomplished by creating lower electrodes with pillars, or protruding shapes of polysilicon, thus resulting in a greater electrode surface area then would have been achieved with conventional flat surfaces. Kim, in U.S. Pat. No. 5,447,882, describes such an STC structure, comprised of a lower electrode, formed by creating protruding polysilicon features, via patterning of a polysilicon layer. This invention will describe a process in which a lower electrode of an STC structure is fabricated using multiple polysilicon mesas, each featuring protruding polysilicon spacers, thus offering greater increases in lower electrode surface area, of an STC structure, then for structures described in prior art. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to create a DRAM device, with an STC structure, in which the surface area of the lower electrode, of the STC structure is increased, without increasing the width of the STC structure. 
     It is another object of this invention to form the lower electrode of the STC structure by initially defining the capacitor area in a composite layer of insulator layer, overlying a polysilicon layer. 
     It is yet another object of this invention to create a lower electrode featuring a mesa pattern, defined by etching a pattern in the insulator layer, and continuing to etch the mesa pattern into only a portion of the underlying polysilicon layer, leaving an unetched portion of polysilicon, underlying the multiple mesas. 
     It is still another object of this invention to form polysilicon spacers on the sidewalls of the mesas, followed by removal of the meas insulator layer, resulting in a lower electrode of multiple mesas, comprised of protruding polysilicon features. 
     In accordance with the present invention a method for fabricating increased capacitance DRAM devices, via use of an STC structure, comprised of a lower electrode with increased surface area, has been developed. A transfer gate transistor comprised of: a thin gate insulator; a polysilicon gate structure; lightly doped source and drain regions; insulator spacers on the sidewalls of the polysilicon gate structure; and heavily doped source and drain regions; is formed on a semiconductor substrate. An insulator layer is deposited and an opening in the insulator layer is made to expose the source region of the transfer gate transistor. A contact plug, of conductive material, is formed in the opening to the source region, followedby the deposition of a polysilicon layer, and an overlying insulator layer. The insulator layer and underlying polysilicon layer are patterned to form the desired width of the lower electrode of the STC structure. A pattern of multiple mesas are then etched in the insulator layer, and partially into the polysilicon layer, resulting in multiple mesas of insulator--polysilicon, on a continuous, underlying polysilicon layer. Another deposition of polysilicon is performed, followed by an anisotropic, reactive ion etching procedure, producing polysilicon spacers on the sidewalls of the insulator-polysilicon mesas. The insulator, of the insulator-polysilicon mesas, is then removed, resulting in a polysilicon lower electrode, with multiple mesas featuring protruding polysilicon spacers, on the sidewalls of the mesas. A capacitor dielectric layer is next formed on the polysilicon lower electrode, followed by the creation of an upper polysilicon electrode, completing the processing of the STC structure. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The object and other advantages of this invention are best explained in the preferred embodiment with reference to the attached drawings that include: 
     FIGS. 1-7, which schematically shows, in crosssectional style, the key fabrication stages used in the creation of a DRAM device, with a STC structure, with an increased surface area, resulting from a lower electrode comprised of polysilicon spacers on the sides of polysilicon mesas. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The method of forming a DRAM device, with increased capacitance, resulting from the use of a STC structure that features a lower electrode, comprised of polysilicon spacers, on the sides of polysilicon mesas, will now be described. The transfer gate transistor, used for this DRAM device, in this invention, will be an N channel device. However the STC structure, with the increased surface area described in this invention, can also be applied to P channel, transfer gate transistor. 
     Referring to FIG. 1, a P type, semiconductor substrate, 1, with a &lt;100&gt;, single crystalline orientation, is used. Field oxide, (FOX), regions, 2, are used for purposes of isolation. Briefly the FOX regions, 2, are formed via thermal oxidation, in an oxygen-steam ambient, at a temperature between about 850° to 1050° C., to a thickness between about 3000 to 5000 Angstroms. A patterned oxidation resistant mask of silicon nitride-silicon oxide is used to prevent FOX regions, 2, from growing on areas of substrate, 1, to be used for subsequent device regions. After the growth of the FOX regions, 2, the oxidation resistant mask is removed via use of a hot phosphoric acid solution for the overlying, silicon nitride layer, and a buffered hydrofluoric acid solution for the underlying silicon oxide layer. After a series of wet cleans, a gate insulator layer, 3, of silicon oxide is thermally grown in an oxygen-steam ambient, at a temperature between about 850° to 1050° C., to a thickness between about 50 to 200 Angstroms. A first polysilicon layer is next deposited using low pressure chemical vapor deposition, (LPCVD), procedures, at a temperature between about 500° to 700° C., to a thickness between about 1500 to 4000 Angstroms. The polysilicon can either be grown intrinsically and doped via ion implantation of arsenic or phosphorous, at an energy between about 30 to 80 KeV, at a dose between about 1E13 to 1E16 atoms/cm 2 , or grown using in situ doping procedures, via the incorporation of either arsine or phosphine to the silane ambient. Conventional photolithographic and reactive ion etching, (RIE), procedures, using Cl 2  as an etchant, are used to pattern the polysilicon layer, creating polysilicon gate structure, 4, shown schematically in FIG. 1. Photoresist removal is accomplished via plasma oxygen ashing and careful wet cleans. 
     A lightly doped source and drain region, 5, is next formed via ion implantation of phosphorous, at an energy between about 20 to 50 KeV, at a dose between about 1E13 to 1E14 atoms/cm 2 . A first insulator layer of silicon oxide is then deposited using either LPCVD or PECVD procedures, at a temperature between about 400° to 700° C., to a thickness between about 1500 to 4000 Angstroms, followed by an anisotropic RIE procedure, using CHF 3  as an etchant, creating insulator spacer, 6, on the sidewalls of polysilicon gate structure, 4. A heavily doped source and drain region, 7, is then formed via ion implantation of arsenic, at an energy between about 30 to 80 KeV, at a dose between about 1E15 to 1E16 atoms/cm 2 . The result of these procedures are schematically shown in FIG. 1. 
     A second insulator layer of silicon oxide, 8, is next deposited using LPCVD or PECVD procedures, at a temperature between about 400° to 700° C., to a thickness between about 4000 to 6000 Angstroms. Conventional photolithographic and RIE procedures, using CHF 3  as an etchant, are used to open contact hole, 9, in silicon oxide layer, 9, exposing the top surface of heavily doped source and drain region, 7. Photoresist removal is performed via use of plasma oxygen ashing and careful wet cleans. A conductive contact plug, 10, schematically shown in FIG. 2, is next formed. Several options of forming contact plug, 10, are available. The preferred option is the selective LPCVD deposition of tungsten, performed at a temperature between about 300° to 500° C., to a thickness equal to the thickness of silicon oxide layer, 8, between about 4000 to 6000 Angstroms, using WF 6  and silane as reactants. This deposition results in a tungsten contact plug, 10, in contact hole, 9, formed by selectively depositing only on exposed silicon surfaces, therefore eliminating the need for etchback or planarization. A second option is to deposit tungsten via r.f. sputtering, or non-selective LPCVD procedures, to a thickness great enough to allow complete filling of contact hole 9, and followed by an planarization procedure, either RIE or chemical mechanical polishing, used to remove unwanted tungsten from areas outside the contact hole to form tungsten contact plug, 10. A third option is to deposit polysilicon via LPCVD procedures, to a thickness again great enough to completely fill contact hole, 9, and followed again by planarization procedures, either RIE or chemical mechanical polishing, to result in a polysilicon contact plug, 10, only in contact hole, 9. 
     A second layer of polysilicon, 11a, is next deposited, via LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 3000 to 6000 Angstroms. Polysilicon layer, 11a, can be deposited intrinsically and doped via ion implantation of either phosphorous or arsenic, at an energy between about 25 to 75 KeV, at a dose between about 1E13 to 1E15 atoms/cm 2 , or polysilicon layer, 11a, can be deposited using in situ doping procedures, via the addition of either phosphine or arsine, to a silane ambient. A third insulator layer of silicon oxide, 12a, is next deposited using either LPCVD or plasma enhanced chemical vapor deposition, (PECVD), procedures, at a temperature between about 650° to 750° C., to a thickness between about 3000 to 6000 Angstroms. Insulator layer, 12a, can also be silicon nitride, again obtained via either LPCVD or PECVD procedures. Insulator layer, 12a, can also be a BPSG or PSG layer, obtained via addition of either PH 3  and B 2  H 6 , or just PH 3 , to a TEOS, (tetraethylorthosilicate), ambient. FIG. 3, shows the result of a first photolithographic and RIE procedure, using CHF 2  as an etchant for silicon oxide layer, 12a, and Cl 2  as an etchant for polysilicon layer, 11a. This procedure defines the width of the lower electrode, of a subsequent STC structure. Photoresist removal is accomplished via plasma oxygen ashing and careful wet cleans. 
     A second photolithographic and RIE procedure is next used to create a pattern of multiple, silicon oxide, 12b,--polysilicon, 11b, mesas, schematically illustrated in FIG. 4. First, photoresist shapes, 13, are used as a mask to transfer photoresist shape, 13, to the underlying silicon oxide layer, 12a, of the lower electrode, via RIE procedures using CHF 3  as an etchant. Next polysilicon layer, 11a, of the lower electrode shape is patterned, via RIE etching, using Cl 2  as an etchant, and again using photoresist shape, 13, as a mask. However in this procedure polysilicon layer, 11a, is only etched to remove between about 1500 to 3000 Angstroms, therefore leaving between about 1500 to 3000 Angstroms of polysilicon layer, 11a, unetched, and maintaining the continuity of polysilicon layer, across the width of the lower electrode, and underlying the multiple, silicon oxide, 12b, polysilicon, 11b, mesas. Photoresist shapes, 13, are then removed via plasma ashing and careful wet cleans. 
     A third layer of polysilicon is next deposited, using LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 500 to 2000 Angstroms. This polysilicon layer is grown using in situ doping procedures, by the addition of phosphine to the silane ambient. An anisotropic RIE procedure, using Cl 2  as an etchant is next employed to create polysilicon spacers, 14, on the sidewalls of the multiple, silicon oxide, 12b polysilicon, 11b, mesas. This is shown schematically in FIG. 5. The height of polysilicon spacers, 14, is the sum of the thickness of silicon oxide mesa, 12b, and the amount of polysilicon layer, 11a, removed during the formation of the multiple, silicon oxide, 12b,--polysilicon, 11b, mesas. FIG. 6. schematically shows the lower electrode structure after selective removal of silicon oxide layer, 12b, using a dilute, or buffered, hydrofluoric acid solution. The lower electrode, or storage node electrode, is comprised of polysilicon mesas, 11b, and protruding polysilicon spacers, 14. 
     The polysilicon mesa, polysilicon spacer, lower electrode structure, can be used for high density, DRAM designs, such as 64 Mb densities or greater. For high density designs, less available space is given for the STC structure, and therefore less mesas can be used. However the desired capacitances, or surface area, can be still be maintained by increasing the height of the polysilicon spacer. This can be accomplished via the use of mesas with either a thicker silicon oxide layer, a thicker polysilicon layer, or a deeper etching of the polysilicon, used for mesa creation. 
     FIG. 7, schematically shows the completion of the STC structure. First a dielectric layer, 15, is formed, overlying the polysilicon mesa, lower electrode, 11b, with protruding polysilicon spacers, 14. Dielectric layer, 15, can be an insulator layer possessing a high dielectric constant, such as Ta 2  O 5 , obtained via r.f sputtering techniques, at a thickness between about 10 to 100 Angstroms. Dielectric layer, 15, can also be ONO, (Oxidized--silicon Nitride--silicon Oxide). The ONO layer is formed by initially growing a silicon dioxide layer, between about 10 to 50 Angstroms, followed by the deposition of a silicon nitride layer, between about 10 to 20 Angstroms. Subsequent thermal oxidation of the silicon nitride layer results in the formation of a silicon oxynitride layer on silicon oxide, at a silicon oxide equivalent thickness of between about 40 to 80 Angstroms. Finally another layer of polysilicon is deposited, via LPCVD procedures, at a temperature between about 500° to 700° C., to a thickness between about 1000 to 3000 Angstroms. Doping of this polysilicon layer is accomplished via the in situ deposition procedure, again via the addition of phosphine, to a silane ambient. Photolithographic and RIE procedures, using Cl 2  as an etchant, are next employed to create polysilicon upper electrode, or plate electrode, 16, shown schematically in FIG. 7. Photoresist is again removed via plasma oxygen ashing and careful wet cleans. 
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.