Abstract:
In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
   This application claims priority under 35 USC 119(e) to the following provisional patent applications: 60/592,836, filed Jul. 29, 2004; and 60/611,042, filed on Sep. 17, 2004; which are incorporated by reference herein in their entirety. 

   BACKGROUND OF INVENTION 
   1. Technical Field 
   The invention relates to display devices. More specifically, the invention relates to calibration of analog to digital converters used in digital displays. 
   2. Background 
     FIG. 1  illustrates a broad schematic of an arrangement to generate images and to display the images in digital form. In particular, a host  102  (for example, a personal computer) generates an image in digital format. Digital to analog converter (DAC) circuitry  104  associated with the host  102  converts the digital image data generated by the host  102  into analog image data (typically, in RGB format) to be sent out over a connection  106  to digital display circuitry  108 . Analog to digital converter (ADC) circuitry  110  associated with the digital display circuitry  108  converts the analog image data back into digital image data, which is then provided to a display  112  such as a liquid crystal (LCD). The operation of the digital display circuitry  108  is typically under the control of a processor (not shown) that is either “on-board” (or otherwise relatively tightly coupled to the circuitry of the digital display circuitry  108 ) or “off board” (or otherwise less tightly coupled to the circuitry of the digital display circuitry  108 ). 
   With particular respect to the ADC circuitry  110 , variation in silicon process may result in internal offset voltages of the ADC circuitry  110  varying with temperature. As a result, when temperature varies, the RGB output data through the ADC circuitry  110  may show data drift. 
   The internal offset voltages depend on factors such as threshold voltage mismatch, overdrive voltage and transistor mismatches. The internal offset voltages are cancelled out depending on the values of OFFSET1 and OFFSET2 registers for each of the RGB colors, associated with the ADC circuitry  110 . The OFFSET1 and OFFSET2 registers both have the same general effect, but the OFFSET1 register provides a relatively gross adjustment, while the OFFSET2 register provides a relatively finer adjustment. In one example, each one bit adjustment of the OFFSET1 register provides 1.7 bits of least significant bit (LSB) adjustment to the ADC circuitry  110  for a color channel, while each one bit adjustment of the OFFSET2 register provides 0.8 bits of LSB adjustment to the ADC circuitry  110  for the color channel. By appropriately setting the values in the OFFSET1 and OFFSET2 registers for each channel, the result is that the colors (RGB) will be balanced as a whole. 
   However, the terms in the equation for determining the offset values for the OFFSET1 and OFFSET2 registers have different temperature coefficients. It is thus difficult to predetermine how to vary these values with temperature change to achieve a perfect cancellation of these different temperature variations. Also, the temperature dependence varies with process, making it even more difficult to predetermine how to correlate the offset values to temperature. 
   Conventionally, offset values and gain values are initialized at the power up of the digital display circuitry  108  (including the ADC circuitry  110 ) and stored in a non-volatile RAM (NVRAM). Thus, color balance is achieved, at least initially. However, the output data from one or more channels of the ADC circuitry  110  may shift based on changes in operating conditions, such as changes in operating temperature. 
   It is thus desirable to respond to such changes in operating conditions and, in particular, to respond in a way that is not nominally visible to a typical viewer of images on the display  112 . 
   SUMMARY OF INVENTION 
   In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  is a broad schematic illustration of circuitry to generate images and to display the images in digital form. 
       FIG. 2  broadly illustrates processing to operate the  FIG. 1  circuitry to account for changes in operating conditions of the ADC circuitry  110 . 
       FIG. 3  is a flowchart illustrating initialization processing relative to the ADC calibration processing shown in  FIG. 2 . 
       FIG. 4  is a flowchart illustrating the ADC calibration processing shown in  FIG. 2 . 
   

   DETAILED DESCRIPTION 
   In general, a method is described to operate digital display circuitry such that the ADC circuitry  110  of the  FIG. 1  digital display circuitry  108  is calibrated during vertical blanking intervals of the analog display signal sent over connection  106 . 
   For example, with reference to  FIG. 2 , it can be seen that step  202  (which is outside the vertical blanking interval, or VBI) includes processing to display an image on display  112 . The step  202  processing may be entirely conventional. Steps  204  and  206  are during the VBI. At step  206 , processing occurs to adjust the operation of the ADC circuitry  110  for changes in operating conditions. At step  204 , nominal (e.g., conventional) VBI processing occurs. Thereafter, processing returns to step  202 . 
     FIG. 3  is a flowchart illustrating an example of the ADC calibration processing  206 , using an internal DAC as input to the ADC circuitry  110 . By using the internal DAC as input for the ADC circuitry  110  during calibration, extraneous influences can be minimized or eliminated. For example, interferences such as change of amplitude and external analog noise from the external ADC circuitry  110  inputs can be minimized or eliminated. 
   Turning now to  FIG. 3 , reference numeral  300  merely indicates an entry point into the  FIG. 3  processing. At step  302 , the internal DAC enabled as input to the ADC circuitry  110 . The output of the internal DAC is programmed to ADC_TEST_DACVALUE (a user-programmable parameter to the processing). Also, the ADC circuitry  110  bandwidth is set to zero, which eliminates high frequency band interference. 
   At step  304 , the ADC Data registers (output) are read. In the illustrated example, each ADC Data register is read multiple times. As discussed immediately below, this provides an opportunity for better ensuring the quality of the read ADC output data. 
   For example, in some examples, apparently aberrant output values of the ADC circuitry  110  are discarded. In a particular example, if values in adjacent (in time) readings of a particular ADC Data register differ by greater than ADC_GLITCH_THRESHOLD, then the values are not considered in the ADC calibration processing. 
   Furthermore, as shown at step  306 , a moving average of the ADC output data is determined, and this moving average is used as input to the ADC calibration processing. By using the moving average, slow moving random noise exhibited in the ADC output data can be “averaged out.” In a particular implementation of moving average processing, each ADC Data register is read OFFSET_ARRAY times, an average value is determined from the OFFSET_ARRAY read values, and then this average value is rounded to the nearest integer. 
   At step  308 , the rounded, averaged value that is the result of step  306  is compared to a previously-saved result of step  306  (i.e., from a previous execution of the  FIG. 3  ADC Calibration processing, in a previous VBI). If the difference between the current step  306  result and the previous step  306  result exceed ADC_THRESHOLD, then processing goes to step  310 . At step  310 , the new ADC data is saved and the OFFSET2 value is adjusted. 
   In one example, the processing at step  310  is such that the OFFSET2 value is adjusted only slightly (e.g., by one bit) each time the  FIG. 3  processing is executed. In this example, if further adjusting of the OFFSET2 value is required to bring the ADC circuitry  110  to calibration, then the further adjusting would occur naturally as a result of subsequent executions of the  FIG. 3  processing, on subsequent VBI&#39;s. 
   At step  312 , the operational GAIN value is restored to the ADC circuitry  110  in place of the zero GAIN value used during  FIG. 3  calibration processing. Then ADC calibration processing exits at step  314 . 
   If the difference between the current step  306  result and the previous step  306  result do not exceed ADC_THRESHOLD, then the OFFSET2 value is not adjusted. Processing then continues at step  312  to restore the operational GAIN value, and the ADC calibration processing exits at step  314 . 
   We now turn to  FIG. 4 , which is a flowchart illustrating initialization processing for the ADC calibration of  FIG. 3 . Portions of the  FIG. 4  processing are the same as processing of  FIG. 3 , and these same portions are denoted by identical reference numerals. The  FIG. 4  processing is typically executed upon power up of the digital display circuitry  108 , and may be executed at other times as appropriate, such as when called by an on-screen display setup function. 
   Reference numeral  400  merely indicates an entry point into the  FIG. 4  processing. At step  402 , it is determined whether the ADC circuitry  110  has been previously calibrated and the determined ADC OFFSET1 value has been stored into NVRAM. If so, then processing at step  404  executes to perform missing code calibration. Missing code calibration handles the case where there is an apparent discontinuity in the output function of the ADC circuitry  110 . 
   For example, the ADC output function may be such that there are 255 different output digital codes, in steps of one, if the input is varied by one. Sometimes, due to internal ADC characteristics, there may not be a true one-to-one correspondence between the input and the output of the ADC circuitry  110 . In missing code calibration, the input code at which the discontinuities occur are remembered, as well as the “fix” for the discontinuity. Then, in operation of the ADC circuitry  110 , when such an input code is detected, the appropriate offset adjustments are made. For example, if an output code of sixty four was expected based on the input, and sixty five is seen at the output, then the next time an input code of sixty four is detected, one is subtracted from the output, to calibrate for the missing code. 
   If the ADC circuitry  110  has not been previously calibrated and the determined ADC OFFSET1 value stored into NVRAM, then processing at step  408  executes to calibrate the ADC circuitry  110  to determine a suitable OFFSET1 value. By performing the OFFSET1 calibration multiple times and averaging (i.e., referring to  FIG. 4 , AUTO_ADC_INIT_AVG times), there is a greater probability of minimizing the effect of glitches or other wrong values being recorded and stored into NVRAM. At step  410 , the averaged OFFSET1 value is rounded to the nearest integer and stored into NVRAM. 
   At step  302  (like in  FIG. 3 ), the DAC is enabled and programmed to output a desired test output value as input the ADC circuitry  110 . At step  412 , new OFFSET2 and GAIN values are calculated for each color channel of the ADC circuitry  110 . 
   At step  304 , the ADC data registers are read, accounting for the potential of glitches in the reading, as in the  FIG. 3  processing. At step  306  the data values are averaged, as in the  FIG. 3  processing. Finally, at step  414 , the new ADC DATA and OFFSET2 values are stored, to be used as initial values in subsequent  FIG. 3  processing during VBI intervals. 
   In accordance with some examples, there are events of higher priority than ADC calibration that should be service during VBI&#39;s. One such event is communication of data between the digital display circuitry  108  and the host device  102 . When such events are detected, in some examples, ADC calibration is not performed for at least a predetermined number of consecutive VBI&#39;s. In one particular example, this is implemented by initializing a HOLDOFF counter upon detection of the higher priority event, decrementing the HOLDOFF counter at each VBI, and discontinuing ADC calibration processing during each consecutive VBI until a VBI in which the HOLDOFF counter has reached zero. 
   In addition, in some examples, the  FIG. 3  processing will take more than the amount of time that is available for such processing during a VBI. In this case, the  FIG. 3  processing is made re-entrant, e.g., by utilizing a timer interrupt to save the state of the  FIG. 3  processing on an alternate stack between VBI&#39;s, and the  FIG. 3  processing is carried out over multiple VBI&#39;s. It is determined during a particular VBI whether to initiate the calculating control processing of  FIG. 3  or whether to continue executing a previously initiated calibrating control processing. 
   Using the timer interrupt, the amount of time during which the calibrating processing is executed during a particular VBI is limited, such that the calibrating processing is terminated and the state of  FIG. 3  processing saved on the alternate stack upon occurrence of the timer interrupt.