Abstract:
A chopper-stabilized telescopic differential amplifier circuit with an input signal switching matrix and an output signal switching matrix. Complementary nonoverlapping chop control signals for the switching matrices cause the inverse and noninverse input and output terminals of the circuit to alternately connect to the inverse and noninverse terminals of the internal differential amplifier. Common mode feedback is also provided in the form of synchronized switched capacitances coupling the output terminals of the circuit to a bias circuit for the internal differential amplifier. The internal differential amplifier includes a secondary bias circuit which maintains respective portions of the two circuit branches of the differential amplifier in constantly on bias states.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to chopper-stabilized amplifiers, and in particular, to differential amplifiers that are chopper-stabilized. 
     2. Description of the Related Art 
     Cellular telephones typically operate in a standby mode in which most active receiver circuitry is powered up, or enabled, only long enough to detect the presence of an incoming call. This so-called “power-up” time is typically in the range of 20 percent. Added to this 20 percent “power-up” time is the overhead time needed to initialize the system, e.g., the time needed to achieve phase lock within the phase lock loops of the system and to compensate for receiver circuit offsets. Hence, if the overhead time is 5 percent, then the average power dissipation during standby mode has increased by 25 percent (0.25/0.2=1.25). Accordingly, it follows that if the overhead time can be reduced then the average power dissipation during standby operation can also be reduced. For example, one conventional CDMA (code division multiple access) spread spectrum cellular system has a typical overhead time of approximately four milliseconds (ms), and it has been a goal to reduce such overhead time by a factor of four to approximately 1 ms. 
     Referring to FIG. 1, cellular telephones, as with most communication systems, require high gain baseband filters within the receive signal path. In such applications, the in-band signal is amplified and conveyed to subsequent stages for processing, e.g., to an analog-to-digital converter (ADC). This analog filtering serves two purpoes reducing the magnitude of interfering signals outside the band of intereste providing anti-aliasing. With respect to the former purpose, reducing the magnitude of interfering signals outside of the band of interest prevents large out-of-band signals rom reducing the dynamic range of the system. However, it is important that the power dissipated within the filter be less than the power that would be required for an ADC with sufficient resolution to handle such out-of-band interference. For examples, if the out-of-band interference is 40 decibels (dB) higher than the in-band signals, the resolution of the ADC, without such filtering, would increase from four bits to 11 bits. 
     Referring to FIG. 2, and with respect to the latter purpose, providing anti-aliasing is achieved by causing the frequency selectivity of the filter to reduce the magnitude of signals beyond the Nyquist rate of the ADC to prevent such signals from “aliasing” back into the passband as a result of the sampling process and thereby further reducing the dynamic range. 
     The DC offsets in the receive signal path cause performance of the system to degrade in at least two ways. Offsets near the front end of the system get amplified by the active filter circuit and thereby reduce the available dynamic range of the ADC at the output. Additionally, referring to FIG. 3, offsets create errors in the two receiver signal paths commonly referred to as “in-phase” (I) and “quadrature” (Q) signal paths, thereby creating constellation distortion. The magnitude of the error E equals the difference between the ideal I and Q signal vectors. These errors decrease the available signal-to-noise (SNR) ratio, thereby further reducing the system performance. For example, in one conventional type of cellular telephone, the receiver input data is encoded using quadrature phase shift keying (QPSK). The offsets create an error vector E which causes the constellation points to shift. (The ideal constellation vectors are identified by dashed lines, while the actual resultant constellation vectors are identified with bold lines.) The magnitude of the error vector is computed according to Equation (1) 
     
       
         |E|={square root over (Vos I   2 +L +Vos Q   2 +L )}≅2·{square root over (Vos MAX +L )}  (1) 
       
     
     In one typical cellular telephone receiver, the four-bit ADC within the received signal path operates with a nominal peak-to-peak signal range of 12 digital counts. A maximum offset of one LSB (least significant bit) results in an error vector of 17 percent. Accordingly, in order to reduce this error to 10 percent, it is necessary that the offset be kept to less than one LSB. 
     Referring to FIG. 4, offset within the quadrature signal paths has been removed in conventional systems by using a low frequency feedback loop to cancel such offset component. In a conventional CDMA spread spectrum cellular telephone system, for example, the baseband information bandwidth extends from one to 630 kilohertz (kHz). So as to not attenuate the low frequency baseband information, the offset cancellation loop bandwidth must be kept well below 1 kHz. So as to maintain signal integrity, low frequency phase response and group delay matching between the I and Q channels is just as important as magnitude matching. The offset cancellation loop bandwidth is typically set to approximately 100 hertz (Hz) to satisfy such requirements. 
     This conventional design provides offset compensation feedback by way of a pulse density modulated (PDM) output signal generated by a modulator/demodulator (MODEM) chip. This digital signal is filtered by a first order resistive-capacitive (RC) network. The output of this filter is fed into the analog receive filter with a nominal gain of −50% full scale for every +1 volt change in the control voltage. In the worst of cases, the offset values for the transconductive-capacitive (gm C) filters used in conventional systems are approximately 50% of full scale, e.g., eight counts of a four-bit ADC. As a result of this large potential initial offset error, these loops can take up to 4 ms to converge within 0.5 LSB (2.5 time constants of a 100 Hz filter). 
     SUMMARY OF THE INVENTION 
     A circuit containing an embodiment of the present invention provides an offset compensation technique for high gain switched capacitor filters, such as those providing a voltage gain of at least 30 dB, thereby reducing bit error rates caused by such offsets in digital communication systems. Chopper stabilization is used in the amplifier within the filter to reduce offsets. The signal, or tone, at the chopper signal frequency is filtered out with a switched capacitor filter having a cosine filter response. Such a combination of chopper stabilization and switched capacitor cosine filtering virtually eliminates offsets without creating extraneous frequency components in the output of the high gain filter circuit. 
     In accordance with one embodiment of the present invention, a chopper-stabilized telescopic differential amplifier circuit includes inverse and noninverse signal input and output terminals, a telescopic differential amplifier circuit, and input and output signal switching circuits. The inverse and noninverse signal input terminals are configured to convey a differential input signal with inverse and noninverse input signal phases. The inverse and noninverse signal output terminals are configured to convey a differential output signal with inverse and noninverse output signal phases which correspond to the noninverse and inverse input signal phases. The telescopic differential amplifier circuit includes first and second amplifier input terminals configured to receive the inverse and noninverse input signal phases and further includes first and second amplifier output terminals configured to provide the inverse and noninverse output signal phases. The input signal switching circuit is coupled between the inverse and noninverse signal input terminals and the first and second amplifier input terminals and is configured to receive at least one switch control signal and in accordance therewith alternately couple the inverse and noninverse signal input terminals to the first and second amplifier input terminals. The output signal switching circuit is coupled between the first and second amplifier output terminals and the inverse and noninverse signal output terminals and is configured to receive the at least one switch control signal and in accordance therewith alternately couple the first and second amplifier output terminals to the inverse and noninverse signal output terminals. 
     These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a functional block diagram of a conventional digital communication system receive signal path with low pass filtering and analog-to-digital conversion. 
     FIG. 2 is a series of signal spectrum representations illustrating signal aliasing for the circuit of FIG.  1 . 
     FIG. 3 is a QPSK constellation diagram showing offset errors for the circuit of FIG.  1 . 
     FIG. 4 is a functional block diagram of a conventional offset compensation loop for use with the circuit of FIG.  1 . 
     FIG. 5 is a functional block diagram of a signal filter circuit in which the present invention is suitable for use. 
     FIG. 6 is a schematic diagram of a chopper-stabilized telescopic differential amplifier circuit in accordance with one embodiment of the present invention. 
     FIG. 7 is a schematic diagram and associated signal timing diagram for a switched capacitor integrator circuit in which the amplifier circuit of FIG. 6 is suitable for use. 
     FIG. 8 is a series of spectral response diagrams for the circuit of FIG. 7 when used with a cosine filter stage. 
     FIG. 9 is a schematic diagram and associated signal timing diagram for a switched-capacitor cosine filter circuit suitable for use with the circuit of FIG.  7 . 
     FIG. 9A is a schematic diagram for a fully differential switched-capacitor cosine filter circuit in accordance with another embodiment of the present invention. 
     FIG. 10 illustrates the difference in convergence time between a conventional compensation feedback loop and one embodiment of a compensation feedback loop using the present invention. 
     FIG. 11 is a functional block diagram of an offset compensation technique for a digital communications receiver using the present invention. 
     FIG. 12 is a functional block diagram of an offset compensation technique for a digital communications receiver using the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 5, a switched capacitor filter circuit  100  implemented in accordance with one embodiment of the present invention includes a signal summing circuit  102 , a receive filter circuit (with gain)  104 , a cosine filter circuit  106  and an ADC circuit  108 . The sampled data signal  101   a  is received and differentially summed with a feedback signal  101   b  by subtracting the feedback signal  101   b  from the data signal  101   a . A differential summation signal  103  is provided with noninverse  103   a  and inverse  103   b  signal phases. These signals  103   a ,  103   b  are amplified and filtered by the receive filter stage  104  to produce a differential output voltage  105  with noninverse  105   a  and inverse  105   b  signal phases. The cosine filter stage  106  filters the signals  105   a ,  105   b  and produces a filtered analog signal  107  which is then converted to a digital signal  109  by the ADC  108 . (The receive filter  104  and cosine filter  106  stages are discussed in more detail below.) 
     Referring to FIG. 6, the receive filter stage  104  includes a chopper-stabilized telescopic differential amplifier circuit  120 . Among known fully differential operational amplifier designs, so-called telescopic, or unfolded cascode, amplifiers are known to have a high bandwidth-to-power ratio, albeit at the cost of a somewhat more complicated biasing requirement due to the smaller common mode signal range at the input as compared to the output. However, the reduced common mode input signal range does not present a significant problem for switched capacitor integrators, and any disadvantages of the more complex bias circuitry are generally offset by the reduced power dissipation of the telescopic amplifier design. 
     Chopper stabilization is achieved by providing switches at both the input and output terminals of the amplifier  120 . These switches act as multiplexors to alternate which branch of the differential amplifier is connected to the inverting and noninverting input and output terminals. 
     The actual differential amplifier  140  includes two circuit branches: PMOS transistors M 3  and M 4  and NMOS transistors M 1  and M 2  form one branch; PMOS transistors M 13  and M 14  and NMOS transistors M 11  and M 12  form the second branch. Both circuit branches are biased by NMOS transistors M 7 , M 7 A and M 7 B. Transistor M 7  is sized to be N-times larger than each of transistors M 7 A and M 7 B. Transistor M 7  provides biasing for both branches of the differential amplifier  140 , while transistor M 7 A provides a trickle bias for transistors M 2 , M 3  and M 4  when transistor M 1  is turned off, and transistor M 7 B provides a trickle bias for transistors M 12 , M 13  and M 14  when transistor M 11  is turned off. This improves the signal settling characteristics of the differential amplifier  140  in at least two ways. 
     First, the drain currents of transistors M 7 A and M 7 B maintain a bias for signal path cascode transistors M 2  and M 12 , respectively, even when their respective input transistors M 1  and M 11  are turned off during slewing. This minimizes recovery time problems that may otherwise occur if the cascode transistors M 2 , M 12  were allowed to be turned off completely. Second, common mode feedback is provided through transistors M 7 A and M 7 B even when the input transistors M 1  and M 11 , respectively, are turned off during slewing. If common mode feedback were only available to one side of the amplifier at one time, it would result in a differential signal error that would increase the amplifier settling time. (Additional description of this trickle biasing technique and advantages it provides can be found in commonly owned, co-pending U.S. patent application No. 08/772,011, entitled “High Speed Fully Differential Operational Amplifier With Fast Settling Time for Switched Capacitor Applications,” the disclosure of which is incorporated herein by reference.) 
     A set  142  of input signal switches  122   a ,  122   b ,  124   a ,  124   b  is connected between the noninverting  121   a  and inverting  121   b  input terminals and the gate terminals of transistors M 1  and M 11 . A set  144  of output signal switches  126   a ,  126   b ,  128   a ,  128   b  is connected between the drain terminals of transistors M 2  and M 12  and the noninverting  105   a  and inverting  105   b  output terminals. During the time period that the chop signal CHOP is asserted (and {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)} is not asserted), the noninverting  121   a  and inverting  121   b  input terminals are connected to the gate terminals of transistors M 11  and M 1 , respectively, and the noninverting  105   a  and inverting  105   b  output terminals are connected to the drain terminals of transistors M 2  and M 12 , respectively. Conversely, during the time period that signal {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)} is asserted (and signal CHOP is not asserted) the noninverting  121   a  and inverting  121   b  input terminals are connected to the gate terminals of transistors M 1  and M 11 , respectively, and the noninverting  105   a  and inverting  105   b  output terminals are connected to the drain terminals of transistors M 12  and M 2 , respectively. 
     During the initial portions of the asserted states of signals CHOP and {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)}, another signal φ 1  is asserted, while during the last portions of signals CHOP and {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)}, yet another control signal φ 2  is asserted. The asserted signal states of these control signals φ 1 , φ 2  are mutually exclusive in time and nonoverlapping. (These signals are illustrated in FIG. 7.) Accordingly, during the initial portions of the CHOP and {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)} signals, common mode capacitive feedback between the output terminals  105   a ,  105   b  and the biasing transistors M 7 , M 7 A, M 7 B is provided by capacitors Cfa and Csa and capacitors Cfb and Csb. During the last portions of the CHOP and {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)} signals, capacitors Csa and Csb are discharged and capacitors Cfa and Cfb are precharged by a bias voltage Vb 4 . (Bias voltages Vb 1 , Vb 2 , Vb 3  and Vb 4  can be generated using conventional replica bias circuit techniques, such as diode-connected transistors driven by current sources.) 
     Therefore, as the amplifier circuit  120  changes from the CHOP state to the {overscore (C)}{overscore (H)}{overscore (O)}{overscore (P)} state, the compensation capacitors Cfa, Cfb, Csa, Csb are effectively disconnected from the output terminals  105   a ,  105   b . Hence, the slewing of the circuit  120  becomes very fast and is limited substantially only by the parasitic capacitances present at the drain terminals of output transistors M 2  and M 12 . Accordingly, due to such fast slewing, the chopped amplifier circuit  120  exhibits virtually no residual memory of the preceding CHOP clock state. 
     Referring to FIG. 7, one embodiment of the receive filter circuit  104  (FIG. 5) can be implemented as a switched capacitor integrator circuit using a chopper-stabilized telescopic differential amplifier circuit  120  (FIG. 6) with feedback capacitors CF and switched input capacitors αCF. This circuit  104  is switched using a clock signal with two nonoverlapping phases φ 1 , φ 2  which, as discussed above, are also used in the differential amplifier circuit  120 . This switched capacitor technique reduces signal-dependent charge injection effects. 
     During clock phase φ 1 , the noninverse  103   a  and inverse  103   b  phases of the summation signal  103  (FIG. 5) are capacitively coupled through the input capacitors αCF to the inverting  121   b  and noninverting  121   a  terminals, respectively, of the differential amplifier circuit  120 . During clock signal phase φ 2 , the noninverse  103   a  and inverse  103   b  signals are capacitively coupled to circuit ground. 
     Referring to FIG. 8, the effects of this switched-capacitor integration is represented. As shown in graphs (A) and (B), as a result of the chopper stabilization of the switched capacitor integrator circuit  104 , the DC offset, as well as the 1/f noise, of the operational amplifier  120  is modulated up to the frequency of the chopping signal CHOP. Qualitatively, this chopper stabilization causes the offset of the operational amplifier  120  to appear as a square wave at the output terminals  105   a ,  105   b  of the amplifier  120 . This square wave has an amplitude which is proportional to the product of the original, i.e., non-chopped, operational amplifier offset and the switched-capacitor filter magnitude response at the fundamental frequency of the chopping signal CHOP. The frequency of this square wave is equal to the frequency of the chopping signal CHOP. Accordingly, notwithstanding the reduced magnitude of this signal component  160  due to the filtering action of the switched-capacitor integrator circuit  104 , such signal component  160  can still cause problems later in this system if left unfiltered. 
     Referring to graphs (C) and (D), one way to eliminate this unwanted signal component  160  is to use a cosine filter circuit with a sampling rate which is synchronized to the chopper stabilization signal CHOP. Doing so will cause this signal component  160  to be “notched” out due to the narrow bandstop filter characteristics of the cosine filter response. This filtering action can be represented by Equation (2).                       (     1   +     z     -   1         )     2          =         cos        (       π   ·     f   signal         F   clock       )       ≡     0                 if                   f   signal         =       F   signal     2               (   2   )                                
     Since the frequency of the chopping signal CHOP is set equal to one-half of the clock frequency (F clock / 2 ), the spurious filter output due to the modulated DC offset (and 1/f noise) will be nulled out if the filter is convolved with (1−z −1 ). 
     Referring to FIG. 9, one embodiment  106   a  of the cosine filter circuit  106  (FIG. 5) can be implemented as shown. Four additional switch control signals φA, φB, φC, φD are used, along with the original CHOP signal and clock signals φ 1  and φ 2 . The operational amplifier  170   a  has a grounded noninverting input terminal and an inverting input terminal which is coupled to its output terminal by a feedback capacitor C 1 . An additional feedback capacitor βC 1  and input capacitors αC 1   a , αC 1   b  are switched using switches  172   a ,  172   b ,  174   a ,  174   b ,  176   a ,  176   b ,  176   c  in accordance with the control signals φ 1 , φ 2 , φA, φB, φC, φD. For example, when signals φ 2 , φA and φC are asserted (i.e., at a logic high), the noninverse input signal Vo+ (at terminal  105   a ) is capacitively coupled to circuit ground with capacitor C 1   a  and to the inverting input terminal of the operational amplifier  170   a  with capacitor αC 1   b  and feedback capacitors C 1 , βC 1  are connected in parallel. (During assertion of signal φ 1 , feedback capacitor βC 1  is discharged.) 
     With the switched-capacitor integrator circuit  104  of FIG. 7 providing the input signals  105   a ,  105   b  for the switched-capacitor cosine filter circuit  106   a  of FIG. 9, the overall transfer function is defined by Equation (3).                H        (     z     -   1       )       =           2   ·     α        (     1   +     z     -   1         )             (     1   +   β     )     -     z     -   1                         if                 α                 C1a     =       α                 C1b     ≡     α                 C1                 (   3   )                                
     The operation of the switched-capacitor cosine filter circuit  106   a  of FIG. 9 can be explained as follows. For purposes of this discussion, it is assumed that the offset of the preceding stage, i.e., the switched-capacitor integrator circuit  104  of FIG. 7, is positive with respect to the output common mode voltage of such circuit  104  during the relevant clock signal phase (φA, φB, φC, φD). 
     During clock phase φA, input capacitor αC 1   a  is used to sample the noninverting input signal Vo+ as noninverting integrator. Subsequently, during clock phase φB, capacitor αC 1   a  is used to sample the inverting input signal Vo− as an inverting integrator. It should be understood that during clock phase φB the chopper clock signal CHOP has switched states and the offset of the integrator circuit  104  has now become negative. Therefore, the offset sampled during clock phase φB by capacitor αC 1   a  at the inverting output terminal  105   b  will be positive with respect to the output common mode voltage of the preceding stage  104 . 
     Based upon the foregoing, an important sequence of events should be evident. Input capacitor αC 1   a  is used to sample the noninverse signal Vo+ as a noninverting integrator and sample the inverse signal Vo− (delayed by one clock cycle) as an inverting integrator, plus capacitor αC 1   a  receives the positive offset value during both sampling signal phases. Accordingly, the offset voltage received by capacitor αC 1   a  is the same during both clock signal phases and, therefore, does not cause a charge transfer event for capacitor αC 1   a.    
     Similarly, capacitor αC 1   b  is used to sample the noninverse signal Vo+ as a noninverting integrator and sample the inverse signal Vo− (delayed by one clock cycle) as an inverting integrator, plus capacitor αC 1   b  receives the negative offset voltage during both sampling signal phases. Accordingly, the offset voltage received by capacitor αC 1   b  is the same during both clock signal phases and, therefore, does not cause a charge transfer event for capacitor αC 1   b.    
     One advantage of this circuit implementation is that cancellation of the DC offset voltage from the preceding stage  104  does not depend upon the matching between capacitors αC 1   a  and αC 1   b . Rather, cancellation of the offset depends upon the error, if any, of the RC switch time constant at the end of the clock signal phases. 
     Any remaining residual error is then due to the offset from the operational amplifier  170   a  within the cosine filter circuit  106   a . Any such error is amplified by the ratio of the capacitors (αC 1 /βC 1 +1). For example, with five millivolts (mV) of offset in the operational amplifier  170   a , this residual error is less than ¼ of an LSB. It should also be understood that since the duty cycles of clock signals φA and φB are each 25 percent, this circuit  106   a  can also be used, without modification, if the switched-capacitor integrator circuit  104  of FIG. 7 is reconfigured as a “double-sampled” integrator circuit. 
     Based on the foregoing, it should be understood that using chopper stabilization combined with a switched-capacitor cosine filter significantly improves offset of the overall filter circuit, even if no further correction techniques are applied. With reduced offsets, less time is required by the system to settle, thereby reducing the overhead time needed for a system to acquire offset when powering up. Additionally, the use of the cosine filter prevents any spurious frequency components from being introduced into the filter output spectrum that might degrade overall receiver performance. 
     Referring to FIG. 9A, another embodiment  106   b  of the cosine filter circuit  106  (FIG. 5) can be implemented as shown. Unlike the embodiment  106   a  of FIG. 9 in which a single-ended output signal  107  is provided, this implementation is fully differential and provides a differential output signal  107   a / 107   b . This circuit  106   b  includes an operational amplifier  170   b  with a differential output and uses the same input capacitors αC 1   a , αC 1   b , feedback capacitors C 1 , βC 1 , switch control signals φA, φB, φC, φD, CHOP signal and clock signals φ 1 , φ 2  (per timing diagram portion of FIG.  9 ). A portion of the switched-capacitor input circuit is connected to an input common mode bias potential Vcmi (e.g., circuit ground) and portions of the switched-capacitor feedback circuit are connected to an output common mode bias potential Vcmo (e.g., circuit ground). The switching elements (e.g., pass transistors, transmission gates or other well known switching circuits) are represented in the form of boxes with the designators “ 1 ,” “ 2 ,” “A,” “B,” “C” and “D” and function as switches which are closed during the assertion, or logical high state, of signals φ 1 , φ 2 , φA, φB, φC, φD, respectively, and open otherwise. Hence, just as the circuit  106   a  of FIG. 9, this circuit  106   b  samples the inverse  105   b  and noninverse  105   a  differential input signal phases as a noninverting integrator circuit during one state of such signals φ 1 , φ 2 , φA, φB, φC, φD, and as an inverting integrator circuit during another state of such signals φ 1 , φ 2 , φA, φB, φC, φD. 
     Referring to FIG. 10, with a chopper-stabilized operational amplifier, the switched-capacitor filter output offset is reduced to within +/−1 LSB with a relatively fast time constant set by the receive filter bandwidth (e.g., 630 kHz). This “coarse” offset correction provided by the chopper stabilization occurs within less than 10 microseconds. (With one conventional receive filter circuit, the initial offset can be equal to or greater than eight LSBs.) When such a chopper-stabilized filter circuit is combined with a cosine filter circuit, as discussed above, the offset compensation occurs in approximately 0.5 time constants as compared to 2.5 time constants with the conventional circuit. (The time constant of the external RC filter network (FIG. 4) is fixed in accordance with the bandwidth of the subject baseband signal.) 
     Referring to FIG. 11, the switched capacitor filter circuit having reduced offsets and providing offset compensation when used in a closed feedback loop includes the switched capacitor filter circuit  100  (FIG. 5) connected in a feedback loop with a digital subsystem  200 . The subsystem  200  includes a digital signal processor (DSP)  202 , such as that used in a MODEM, which processes the digital output signal  109  to produce a processed digital signal  201 . The DSP  202  also produces a digital feedback signal  203  from which an offset calculation circuit  204  determines the magnitude of any offset present in the input digital signal  109 . A signal  205  representing the calculated offset is used to produce a PDM signal with a digital-to-analog convertor (DAC)  206 . The resulting analog PDM signal is filtered with a low pass filter circuit to produce the feedback signal  101   b  for the signal summation circuit  102 . As discussed above, the circuit settles significantly faster than conventional designs due to the significantly reduced offsets produced by the filter circuit  100 . 
     Referring to FIG. 12, with the offset produced by the filter circuit  100  being significantly reduced, as compared to the conventional designs, a modified filter circuit  100   a  can be used in which the signal summation circuit  102  is omitted since no feedback signal  101   b  is required. Instead, the digital subsystem  300  can compensate for any offsets while operating strictly in a digital domain. 
     In this embodiment, an offset calculation circuit  304  within the digital subsystem  300  computes the amount of offset contained within the digital input signal  109  from the filter circuit  100   a . A signal  305  representing this computed offset is integrated using a digital integrator circuit  306 . The resulting digital integrated signal  307  is differentially added with the original digital signal  109  in an adder circuit  302 . The resulting sum signal  303  is then processed by a DSP  308  to produce a processed signal  309  as desired. 
     The digital integrator  306  can be implemented with a counter and implements a low pass filter type of function. For example, if the “unity gain” frequency of the digital integrator  306  is set equal to the inverse of the product of the external resistance Rext and capacitance Cext of the low pass feedback filter in the circuit of FIG. 11, the dynamic performance of the loop in the circuit of FIG. 12 will be equivalent to the dynamic performance of the circuit of FIG.  11 . This all-digital implementation of an offset compensation loop has the further advantage of a “perfect memory” between power-up cycles of the system, such as those which occur during alternating active and standby modes of operation. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.