Abstract:
A non-volatile memory device with a sensing amplifier ( 10 ) that includes a current mirror comprising a pair of resistors ( 20,30 ) and an operational amplifier ( 40 ) is disclosed.

Description:
TECHNICAL FIELD 
       [0001]    A non-volatile memory cell with an improved sensing amplifier is disclosed. 
       BACKGROUND OF THE INVENTION 
       [0002]    Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type. 
         [0003]    Read operations usually are performed on floating gate memory cells using sensing amplifiers. A sensing amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “&#39;158 Patent”), which is incorporated herein by reference for all purposes. The &#39;158 Patent discloses using a reference cell that draws a known amount of current. The &#39;158 Patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current minor to minor the current drawn by the selected memory cell. The current in each current mirror is then compared, and the value stored in the memory cell (e.g., 0 or 1) can be determined based on which current is greater. 
         [0004]    Another sensing amplifier is disclosed in U.S. Pat. No. 5,910,914 (the “&#39;914 Patent”), which is incorporated herein by reference for all purposes. The &#39;914 Patent discloses a sensing circuit for a multi-level floating gate memory cell or MLC, which can store more than one bit of data. It discloses the use of multiple reference cells that are utilized to determine the value stored in the memory cell (e.g., 00, 01, 10, or 11). Current mirrors are utilized in this approach as well. 
         [0005]    The current minors of the prior art utilize PMOS transistors. One characteristic of PMOS transistors is that a PMOS transistor can only be turned “on” if the voltage applied to the gate is less than the voltage threshold of the device, typically referred to as V TH . One drawback of using current minors that utilize PMOS transistors is that the PMOS transistor causes a V TH  drop. This hinders the ability of designers to create sensing amplifiers that operate at lower voltages. 
         [0006]    Another drawback of the prior art design is that PMOS transistors are relatively slow when the gate transitions from high to low (i.e., when the PMOS transistor turns on). This results in delay of the overall sensing amplifier. 
         [0007]    What is needed is an improved sensing circuit that operates using a lower voltage supply than in the prior art. 
         [0008]    What is further needed is an improved sensing circuit where the voltage supply can be turned off when not in use to save power, but where the sensing circuit can become operational without a significant timing penalty once the voltage supply is turned back on. 
       SUMMARY OF THE INVENTION 
       [0009]    The aforementioned problems and needs are addressed by providing a sensing circuit that utilizes a resistor pair instead of a transistor pair as a current mirror. The use of a resistor pair instead of a transistor pair enables the use of a lower voltage supply with a shorter startup time. 
         [0010]    In one embodiment, a reference cell current is applied to a current mirror. The mirrored current is coupled to the selected memory cell. The mirrored current is compared to the selected memory cell current, and a sense output is generated that indicates the state of the memory cell (e.g., 0 or 1) and that is directly related to the relative size of the current through the selected memory cell compared to the reference current. 
         [0011]    In another embodiment, a mirror pair block is added between the current mirror and the selected memory cell. 
         [0012]    Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  depicts a block diagram of a sensing circuit embodiment that includes a current mirror that comprises a pair of resistors. 
           [0014]      FIG. 2  depicts a block diagram of another sensing circuit embodiment that includes a current mirror that comprises a pair of resistors. 
           [0015]      FIG. 3  depicts an embodiment of a minor pair block. 
           [0016]      FIG. 4  depicts an embodiment of a reference circuit. 
           [0017]      FIG. 5  depicts another embodiment of a reference circuit. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0018]    An embodiment will now be described with reference to  FIG. 1 . Sensing circuit  10  is shown. A power supply, V DD , is provided to resistor  20  and resistor  30 . Resistor  20  is coupled to one positive terminal of operational amplifier  40 . Resistor  30  is coupled to another terminal of operational amplifier  40 . Operational amplifier  40  acts as a clamp loop. The output of operational amplifier  40  is coupled to the gate of PMOS transistor  70 . The gate of PMOS transistor  70  is coupled to resistor  30 . The drain of PMOS transistor  70  is coupled to memory cell  60 . Resistor  20  is also coupled to reference circuit  50 . As can be seen, resistor  20  and resistor  30  each have a first terminal and a second terminal. The source, drain, and gate of PMOS transistor  70  also are terminals. 
         [0019]    Reference circuit  50  will draw a set amount of current, i REF . The current through resistor  20  will be i REF . Because operational amplifier  40  acts as a clamp loop, the voltage drop across resistor  20  and resistor  30  will be the same, and they therefore will form a current mirror, and the current through resistor  30  also will be i REF  (or a multiple thereof, if the values of resistor  20  and resistor  30  are not equal). 
         [0020]    In operation, memory cell  60  will draw a level of current, i S , that depends upon the value stored in the memory cell. For example, memory cell  60  might draw a low amount of current if it is storing a “0” and a high amount of current if it is storing a “1.” 
         [0021]    In this example, if i REF &gt;i S , then sense output  80  will have a relatively high voltage. If i REF &lt;i S , then sense output  80  will have a relatively low voltage. Thus, if the value stored in memory cell  60  is “0,” then i S  will be relatively low and i REF  will be greater than i S , meaning that sense output  80  will have a high voltage representing a “1.” If the value stored in memory cell  60  is “1,” then i S  will be relatively high and i REF  will be less than i S , meaning that sense output  80  will have a low voltage representing a “0.” Thus, sense output  80  is the inverse of the value stored in memory cell  60 . Optionally, sense output  80  can be coupled to an inverter (not shown), where the inventor would then output a value that directly corresponds to the value stored in memory cell  60 . 
         [0022]    In this example, because the current mirror is created using paired resistors instead of paired transistors, V DD  can be a lower voltage than in a system using paired transistors. This design allows V DD  to be able to operate at a voltage of less than 1.0V. For example, the disclosed embodiments can operate at a minimum voltage of around 0.9V. 
         [0023]    A different embodiment will now be described with reference to  FIG. 2 . Sensing circuit  110  is shown. A power supply, V DD , is provided to resistor  120  and resistor  130 . Resistor  120  is coupled to the positive terminal of operational amplifier  140 . Resistor  130  is coupled to the negative terminal of operational amplifier  140 . Operational amplifier  140  acts as a clamp loop. The output of operational amplifier  140  is coupled to the gate of PMOS transistor  170 . The gate of PMOS transistor  170  is coupled to resistor  130 . The drain of PMOS transistor  70  is coupled to minor pair block  190 . Minor pair memory block  190  is coupled to memory cell  160 . Sense output  180  is the output of sensing circuit  110  and is a port by which the output can be obtained. As can be seen, resistor  120  and resistor  130  each have a first terminal and a second terminal. The source, drain, and gate of PMOS transistor  170  also are terminals. 
         [0024]    Reference circuit  150  will draw a set amount of current, i REF . The current through resistor  120  will be i REF . Because operational amplifier  140  acts as a clamp loop, the voltage drop across resistor  120  and resistor  130  will be the same, and they therefore will form a current mirror, and the current through resistor  130  also will be i REF  (or a multiple thereof, depending upon the values of resistor  120  and resistor  130 ). 
         [0025]    In operation, memory cell  160  will draw a level of current, i S , that depends upon the value stored in the memory cell. For example, memory cell  60  might draw a low amount of current if it is storing a “0” and a high amount of current if it is storing a “1.” 
         [0026]    Additional detail on minor pair block  190  will now be described with reference to  FIG. 3 . Here, we again see resistor  130  and PMOS transistor  170  as we did in  FIG. 2 . The drain of PMOS transistor  170  is coupled to the input of mirror pair block  190 . The input will be current i REF . Minor pair block  190  comprises NMOS transistor  191  and NMOS transistor  192 , which are configured as a current mirror. The gates of NMOS transistor  191  and NMOS transistor  192  are coupled together to the gate of NMOS transistor  191 , and the drains of NMOS transistor  191  and NMOS transistor  192  are coupled to ground. The voltage drop from gate to drain will be the same for NMOS transistor  191  and NMOS transistor  192 , and the current through NMOS transistor  192  therefore also will be i REF  (or a multiple thereof, depending on the characteristics of NMOS transistor  191  and NMOS transistor  192 ). 
         [0027]    Minor pair block  190  comprises PMOS transistor  193  and PMOS transistor  194 . The sources of PMOS transistor  193  and PMOS transistor  194  are connected to V DD . The gates of PMOS transistor  193  and PMOS transistor  194  are connected together and to the drains of PMOS transistor  193 , which in turn connects to the source of NMOS transistor  192 . The voltage drop from the source-to-gate junction in PMOS transistor  193  and PMOS transistor  194  will be the same. Therefore, PMOS transistor  193  and PMOS transistor  194  will act as a current minor, and the current through PMOS transistor  194  also will be i REF  (or a multiple thereof, depending on the characteristics of PMOS transistor  193  and PMOS transistor  194 ). The drain of PMOS transistor  194  is coupled to sense output  180 , which in turn is connected to memory cell  160 . 
         [0028]    The current through sense output  180  will be i REF −i S . If i S &gt;i REF , then this value will be negative, and sense output  180  will detect a low voltage (i.e., a “0”). If i S &lt;i REF , then this value will be positive, and sense output  180  will detect a high voltage (i.e., a “1”). Thus, sense output  180  is the inverse of the value stored in memory cell  160 . Optionally, sense output  180  can be coupled to an inverter (not shown), where the inventor would then output a value that directly corresponds to the value stored in memory cell  160 . 
         [0029]      FIG. 4  shows an embodiment of a reference circuit, shown as reference circuit  200 . Reference circuit  200  can be used for reference circuit  50  or  50 , discussed previously. Reference circuit  200  comprises operation amplifier  210 . The negative node of operational amplifier  210  is connected to a voltage source (not shown) generating a voltage V REF . V REF  can be, for example, 0.8 volts. The output of operational amplifier  210  is connected to the gate of NMOS transistor. The drain of NMOS transistor  220  is the input of the reference circuit  200 . The source of NMOS transistor  220  connects to reference memory cell  230 . 
         [0030]      FIG. 5  shows another embodiment of a reference circuit, shown as reference circuit  300 . Reference circuit  300  can be used for reference circuit  50  or  50 , discussed previously. Reference circuit  300  comprises inverter  310 . The output of inverter  310  is connected to the gate of PMOS transistor  320 . The source of PMOS transistor is the input of the reference circuit  200 . The drain of PMOS transistor is connected to reference memory cell  330  and is the input to inverter  310 . 
         [0031]    Optionally, reference circuit  50  or reference circuit  150  could each comprise a current source circuit. Examples of current source circuits suitable for this purpose are well-known to those of ordinary skill in the art 
         [0032]    References to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.