Abstract:
An charge pump architecture capable of generating ultra high DC voltages but implemented in low voltage CMOS technology uses a cascade of NMOS stages with the bulk terminal of the latter stages biased to a voltage just below the reverse breakdown of the parasitic bulk diode. The bias voltage is tapped from a lower voltage point within the charge pump. The upper limit of the output voltage is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage.

Description:
RELATED APPLICATIONS 
     This application claims priority to U.S. Provisional Patent Application Ser. No. 61/877,539 filed on Sep. 13, 2013, entitled, Ultrahigh Voltage Charge Pump Apparatus Implemented In CMOS Technology, the entire subject matter of which is incorporated herein by this reference for all purposes. 
    
    
     FIELD OF THE INVENTION 
     The disclosure relates to electronic circuitry, and, more particularly, to high voltage charge pumps. 
     BACKGROUND 
     High voltage charge pumps are needed in a variety of applications. One known prior art architecture is the Dickson charge pump, illustrated schematically  FIG. 1 , which must be implemented with high voltage components in order to achieve ultra high voltage levels. Such architecture requires extra die area and expensive fabrication costs to implement in a high voltage technology in an integrated circuit. 
     Accordingly, a need exists for a technique to achieve ultra high DC output voltage levels, higher than the output voltage levels traditionally available from a Dickson charge pump architecture. 
     A further need exists for a charge pump architecture capable of producing ultra high output voltage levels but implemented with standard low voltage technology components. 
     SUMMARY OF THE INVENTION 
     Disclosed herein is an ultra high voltage charge pump architecture capable of generating ultra high DC voltages but implemented in standard low voltage CMOS technology. “Ultra” as used herein means that the voltage level exceeds the reverse breakdown voltage of the parasitic diode to bulk substrate for the particular fabrication technology. The disclosed charge pump uses a cascade of NMOS stages with the bulk terminal of the latter stages biased to a voltage just below the reverse breakdown of the parasitic bulk diode. This bias voltage is tapped from a lower voltage point within the charge pump. The upper limit of the output voltage is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage. 
     According to one aspect of the disclosure, a charge pump apparatus comprises: a plurality of stages sequentially interconnected between an input node and an output node, each of the plurality of stages implemented with a transistor having a bulk diode with a reverse breakdown voltage, wherein one of the plurality of stages has a bulk diode at an operational voltage below the reverse breakdown voltage, wherein the bulk diodes of others of the plurality of stages between said one stage and the output node are biased with a voltage below their respective reverse breakdown voltages. 
     According to another aspect of the disclosure, a charge pump apparatus comprises: a plurality of stages serially interconnected in a sequence between an input node and an output node, each of the plurality of stages implemented with a transistor having a bulk diode with a reverse breakdown voltage; and wherein at least one stage in a latter portion of the sequence has a bulk diode biased with a bias voltage from an earlier stage of the sequence. In one embodiment, such bias voltage is below the reverse breakdown voltage. In one embodiment, a plurality of stages in the latter portion of the sequence have bulk diodes biased with a bias voltage from an earlier stage of the sequence. 
     According to still another aspect of the disclosure, a method of generating ultrahigh voltages low voltage comprises: a) providing a plurality of stages interconnected in a sequence between an input node and an output node, each of the plurality of stages implemented with a transistor having a bulk diode with a reverse breakdown voltage; and b) biasing the bulk diode of at least one stage in a latter portion of the sequence with a voltage below the reverse breakdown voltage. In one embodiment b) comprises: b1) biasing the bulk diodes of a plurality of stages in the latter portion of the sequence. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the disclosed subject matter are described in detail below with reference to the following drawings in which: 
         FIG. 1  illustrates schematically a prior art three stage Dickson charge pump circuit; 
         FIG. 2  illustrates schematically a NMOSFET transistor configuration which may be used with the charge pump of  FIG. 4  in accordance with the disclosure; 
         FIG. 3  illustrates conceptually a cross-sectional layout of the semiconductor materials used to implement the NMOSFET transistor of  FIG. 2  in accordance with the disclosure; and 
         FIG. 4  illustrates a multi-stage charge pump in accordance with the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates schematically a prior art three stage Dickson charge pump using diodes and pumping capacitors alternately driven by a clock signal, φ, and the inverse of the clock signal. The voltage output of the Dickson charge pump illustrated in  FIG. 1  will typically not exceed the breakdown voltage of the last diode in the sequence before the circuit output node. 
       FIG. 2  illustrates schematically a N-type Metal-Oxide-Semiconductor Field Effect Transistor (NMOSFET) transistor  10  which may be used to implement the stages of the charge pump  30  of  FIG. 4 . As illustrated, transistor  10  has a drain node  12 , gate node  14 , source node  16 , bulk node  18 , and a diode  15  coupled intermediate node  18  and ground, as illustrated. In the illustrative embodiment, the diode  15  is a parasitic bulk diode, as illustrated in  FIG. 3 , having a reverse breakdown voltage that functions to limit the maximum charge pump output. 
       FIG. 3  illustrates conceptually a cross-sectional diagram of the NMOSFET transistor  10  of  FIG. 2  as may be implemented with Complementary Metal Oxide (CMOS) fabrication technology and materials for a single stage of the charge pump  35  in accordance with the disclosure. As illustrated, transistor  10  may be implemented with a pair of n+ doped regions  20  and  22  serving as drain node  12  and source node  16 , respectively, which are isolated from each other and from deep N well region  24  by a P well region  26 . A p substrate region  28  surrounds deep N well region  24 . Oxide layer  25  is disposed intermediate regions  20  and  22  and serves as gate node  14  which is electrically coupled to drain node  12 . Bulk node  18  is electrically coupled to both deep N well region  24  and a P well region  26 . Note that deep N well region  24  may be comprise a pair of sections  24 A and  24 B which couple the main body of the deep N well region  24  to the surface of the transistor. Diode  15  comprises the juncture between deep N well region  24  and p substrate region  28 . 
       FIG. 4  illustrates schematically a multistage charge pump  35  which comprises a plurality of sequentially interconnected, alternatingly clocked stages extending intermediate a charge pump input node  32  and a new charge pump output node  34 . In the illustrative embodiment, the multiple stages of charge pump  35  can be subdivided into a first plurality of stages  30 A-N and a second plurality of stages  40 A-N. All of stages  40 A-N may be implemented with transistors fabricated with deep n-wells, e.g. “twin well” technology, similar to those illustrated in  FIGS. 2-3  herein. As illustrated, except for the first and last stages of charge pump  35 , the source node  16  of a stage y is connected to the drain node  12  of the next sequential adjacent stage y+1, with signal flow moving sequentially through the interconnected stages from the charge pump input node  32  to the charge pump output node  34 . Also as illustrated in  FIG. 4 , the interconnected source and drain nodes of adjacent stages are coupled to one of the plurality of pumping capacitors  36 . As illustrated, capacitors  36  are coupled to either clock signal so or the inverse thereof, so that adjacent capacitors are simultaneously driven by opposite phased clock signals. In this manner, depending on the phase of the clock signal, only half of the total number stages within charge pump  35  are being driven and actively increasing the charge between input node  32  and output node  34  at any given clock signal phase. 
     Referring again to  FIG. 4 , the first plurality of stages  30 A-N are arranged in a sequential cascade so that, during operation, the bulk diode  15  of stage  30 N is below its respective breakdown voltage. Thereafter, the second plurality of stages  40 A-N, also arranged in a sequential cascade, have their respective bulk nodes  18  biased to a voltage just beneath the reverse breakdown voltage of their respective diodes  15  by taking a bias voltage from earlier transistor stage  30 N of the first plurality of stages, thereby enabling the output voltage of charge pump  35  to exceed the reverse bias breakdown voltage of the parasitic bulk diode  15  in each of the second plurality of stages. Such biasing of the second plurality of stages is achieved with a filter  38  having an input coupled to the source node  16  of stage  30 N. The filtered signal present at the output node of filter  38  is then provided to the bulk node  18  of each of the subsequent stages  40 A-N in parallel. The filter  38  may be implemented with a simple resistor capacitor design, the exact filtering characteristics of which may depend on the noise characteristics of the signal provided thereto. By biasing the bulk nodes  18  of each of the second plurality of stages  40 A-N, the upper limit of the output voltage for the charge pump  35  is then increased to the maximum allowable oxide voltage plus the parasitic diode reverse breakdown voltage that is present on all stages. In a 3V technology implementation of the illustrative embodiment, the sum of the maximum allowable oxide voltage plus the parasitic diode reverse bias breakdown voltage has been shown to be approximately 50% higher than just the diode reverse bias breakdown voltage, which is typically the limit for high voltage charge pumps implemented with standard low voltage CMOS technology. 
     The reader will appreciate that the disclosed charge pump achieves ultra high output voltage levels while still using standard low voltage CMOS technology, thereby avoiding the extra die area and expensive fabrication costs that would be incurred if implemented with high voltage technology. 
     It will be obvious to those reasonably skilled in the art that modifications to the apparatus and process disclosed here in may occur, including substitution of various component values or nodes of connection, without parting from the true spirit and scope of the disclosure. For example, the circuit described herein may be implemented on an ASIC or formed with discrete components or any combination thereof to realize the system disclosed herein. In addition, although the illustrative embodiment of the multistage charge pump disclosed herein has been described with reference to an NMOS or CMOS fabrication technologies, other semiconductor fabrication technologies or discrete electronic technologies may be utilized to implement equivalent architectures to obtain similar results.