Abstract:
To provide a storage system partitioned into logical partitions. A storage system includes: a plurality of disk drives; and a disk controller that is connected to the disk drives and reads/writes data from/into the disk drives, wherein the disk controller includes: a disk control unit that exchanges data with the disk drives; a channel control unit that exchanges data with another computer; a switch unit that is connected to the disk control unit and the channel control unit and exchanges data therewith; and a control unit that controls the disk control unit, the channel control unit, and the switch unit, and wherein the disk controller is partitioned into a plurality of logical partitions, the control unit controls the partitioning into the logical partitions, and the switch unit controls a data transmission band width of each logical partition by obtaining, for each piece of data to be exchanged, information indicating a logical partition to which the data belongs, and arbitrating data transmission for the logical partition.

Description:
CLAIM OF PRIORITY  
       [0001]     The present application claims priority from Japanese application P2004-265031 filed on Sep. 13, 2004, the content of which is hereby incorporated by reference into this application.  
       BACKGROUND  
       [0002]     This invention relates to a storage system, in particular, a logically partitioned storage system.  
         [0003]     In order to reduce the cost of storage system management, there exists a storage consolidation technique with which plural storage systems are consolidated into a single large-scale storage system.  
         [0004]     This storage consolidation has the following problem that concerns the running of a business.  
         [0005]     Even after storage consolidation is performed, it is required to run a business as smoothly as before the consolidation, although a storage system is accessed by host computers in various forms and the processing capability required of the storage system varies depending on which access form is used. For instance, when the storage system is used as a database, a capability is required with which it is possible to process a large number of requests. Also, when the storage system is used to back up data that is accumulated from day to day, a capability of processing a large size of data is required.  
         [0006]     As described above, the processing capability required of a storage system varies depending on which access form is used by host computers, so at the time of consolidation, a system administrator who is familiar with the configurations of old and new storage systems has to make the settings of the system. For instance, a storage system is proposed in which a certain service level selected by each customer is guaranteed to the customer through a service level guarantee contract and, when its storage performance is likely to drop, access is distributed by, for instance, migrating data stored in a storage volume, on which access is concentrated (see JP 2002-182859 A, for instance).  
         [0007]     According to the invention described in JP 2002-182859 A, in a data center business undertaking out-sourcing of data management, it becomes possible to guarantee a certain service level based on a service level agreement(SLA) selected by each customer.  
       SUMMARY  
       [0008]     This invention provides a storage system where it is possible to perform storage consolidation without exerting any influences on storage system configuration information, thereby making it possible to continue a business.  
         [0009]     With the invention described in JP 2002-182859A, however, a certain service level is guaranteed to each customer based on the average usage ratio, capacity concerning disk drives, and the like but no consideration is given to service level guaranteeing that supports various access forms.  
         [0010]     It is therefore an object of this invention to provide a storage system where resources have been logically partitioned, thereby achieving SLA guaranteeing that supports various access forms.  
         [0011]     A storage system according to the present invention includes: a plurality of disk drives; and a disk controller that is connected to the disk drives and reads/writes data from/into the disk drives, wherein the disk controller includes: a disk control unit that exchanges data with the disk drives; a channel control unit that exchanges data with another computer; a switch unit that is connected to the disk control unit and the channel control unit and exchanges data therewith; and a control unit that controls the disk control unit, the channel control unit, and the switch unit, wherein the disk controller is partitioned into a plurality of logical partitions, the control unit controls the partitioning into the logical partitions, and the switch unit controls a data transmission band width of each logical partition by obtaining, for each piece of data to be exchanged, information indicating a logical partition to which the data belongs, and arbitrating transmission of the data to be exchanged for the logical partition.  
         [0012]     According to this invention, band width is allocated to each LPAR in an internal switch unit  330  of a disk controller  300 , thereby guaranteeing the band width of an internal network to the LPAR. With this configuration, arbitration between usage ratios of the band width of the internal network in a post-consolidation system, in which plural systems have been consolidated, becomes easy. As a result, it becomes possible that processes using various access forms are consolidated.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is a block diagram showing a configuration of a storage system according to a first embodiment of this invention.  
         [0014]      FIG. 2  is an explanatory diagram of LPAR information inputted from an SVP according to the first embodiment of this invention.  
         [0015]      FIG. 3  is a flowchart of LPAR allocation information calculation processing according to the first embodiment of this invention.  
         [0016]      FIG. 4  is a block diagram showing a configuration of a processor unit according to the first embodiment of this invention.  
         [0017]      FIG. 5  is a block diagram showing a configuration of a channel control unit according to the first embodiment of this invention.  
         [0018]      FIG. 6  is a block diagram showing a configuration of an internal switch unit according to the first embodiment of this invention.  
         [0019]      FIG. 7A  is an explanatory diagram of internal switch unit LPAR information according to the first embodiment of this invention.  
         [0020]      FIG. 7B  is an explanatory diagram of the internal switch unit LPAR information according to the first embodiment of this invention.  
         [0021]      FIG. 8  shows an example of a packet according to the first embodiment of this invention.  
         [0022]      FIG. 9  is a block diagram showing a configuration of an internal switch unit according to a second embodiment of this invention.  
         [0023]      FIG. 10  shows an example of the contents of a memory according to the second embodiment of this invention.  
         [0024]      FIG. 11  is a block diagram showing a configuration of an internal switch unit according to a third embodiment of this invention.  
         [0025]      FIG. 12  shows an example of the contents of a memory according to the third embodiment of this invention.  
         [0026]      FIG. 13  is a block diagram showing a configuration of a storage system according to a fourth embodiment of this invention.  
         [0027]      FIG. 14  is a block diagram showing a configuration of a channel control unit according to the fourth embodiment of this invention.  
         [0028]      FIG. 15  is an explanatory diagram showing an example of an LPAR table according to the fourth embodiment of this invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     Hereinafter, a first embodiment of this invention will be described with reference to the drawings.  
         [0030]      FIG. 1  is a block diagram showing a configuration example of a system including a storage system according to the first embodiment of this invention. The system shown in  FIG. 1  includes plural host computers  100  and a storage system. The storage system includes a disk controller  300  and plural disk drives  200 .  
         [0031]     The plural host computers  100  and the plural disk drives  200  are connected to the disk controller  300 .  
         [0032]     The disk controller  300  includes plural channel control units  310 , plural disk control units  320 , plural internal switch units  330 , plural processor units  340 , plural cache memory units  350 , and plural shared memory units  360 . Each of those units is connected to a service processor (SVP)  380  through a management network  370 .  
         [0033]     The channel control units  310  are interfaces that establish connection with the host computers  100 .  
         [0034]     The disk control units  320  are interfaces that establish connection with the disk drives  200 .  
         [0035]     The internal switch units  330  connect the channel control units  310 , the disk control units  320 , the processor units  340 , the cache memory units  350 , and the shared memory units  360  to each other and transmits/receives data, such as packets, exchanged between these units. It should be noted that an internal network is formed by the internal switch units  330 .  
         [0036]     The processor units  340  control of each unit of the disk controller  300 .  
         [0037]     The cache memory units  350  temporarily hold data exchanged between the channel control units  310  and the disk control units  320 .  
         [0038]     The shared memory units  360  hold control information such as the configuration information of the host computers  100 , the disk drives  200 , and the disk controller  300  and the directory information of the caches.  
         [0039]     The management network  370  is a network that connects the SVP  380  and each unit of the disk controller  300  to each other.  
         [0040]     The SVP  380  is a terminal used to change the setting and configuration of each unit of the disk controller  300 . In particular, as will be described later, the SVP  380  sets logical partitions (LPARs) of each unit. In this embodiment, the SVP  380  is connected to each unit through the management network  370 , although this connection may be established through also a network outside the disk controller  300 .  
         [0041]     The internal switch units  330  include internal switch unit LPAR information  331 , the processor units  340  include processor unit LPAR information  341 , and the shared memory units  360  include cache memory LPAR information  361 . It should be noted that the channel control units  310  may include channel control unit LPAR information.  
         [0042]     According to those LPAR information, each of the channel control units  310 , the disk control units  320 , the internal switch units  330 , the processor units  340 , the cache memory units  350 , and the shared memory units  360  is partitioned into logical units. As a result of the partitioning into the logical units (LPARs), the disk controller  300  performs as plural logical disk controllers.  
         [0043]     The processor unit LPAR information  341  is information indicating a ratio of processing of the processor units  340  allocated to each LPAR obtained through the partitioning. The allocation of the processing is realized using a time sharing, for instance. It should be noted that the logical partitioning may be performed by executing firmware called the “hypervisor”. In this case, guest OSs are executed on logical processors provided by the hypervisor and the plural logical processors are mapped to the physical processors by the hypervisor.  
         [0044]     The internal switch unit LPAR information  331  is information indicating a ratio of a band width allocated to each partitioned LPAR. More specifically, for each LPAR number, the internal switch unit LPAR information  331  shows a ratio of the band width allocated to its corresponding LPAR.  
         [0045]     The cache memory unit LPAR information  361  is information indicating a ratio of a cache memory capacity to be used by each partitioned LPAR. The processor units  340  know the cache memory capacity that each LPAR can use by referring to the cache memory unit LPAR information  361  and use an area of the cache memory.  
         [0046]     The disk drives  200  are each composed of plural hard disks or the like. In those plural hard disks, plural logical units (LUs) that are logical areas are set.  
         [0047]     The storage system according to this embodiment configured in the manner described above performs processing in a manner described below.  
         [0048]     A host computer  100  sends an access request to the storage system.  
         [0049]     The channel control unit  310  of the storage system receives this request. Then, the channel control unit  310  analyzes the request and determines an LPAR that should process the request. Then, the channel control unit  310  adds information indicating the determined LPAR to the received request and sends it to each processor unit  340 . The processor unit  340  performs processing based on the received request. During this processing, the internal switch unit  330  controls a communication band width based on the information indicating the LPAR corresponding to the request.  
         [0050]     Next, a setting of the LPARs of the disk controller  300  will be described.  
         [0051]     In the disk controller  300  according to this embodiment, a setting as to how to perform the logical partitioning has been made by an administrator. Information indicating the setting is held in the processor unit LPAR information  341 , the internal switch unit LPAR information  331 , the cache memory unit LPAR information  361 , or the like.  
         [0052]     At the time of consolidation where plural systems are consolidated, the administrator sets pre-consolidation performance information of each system in the LPAR information  341  or the like of the disk controller  300 . As a result, the disk controller  300  logically operates as the plural systems that operated before the consolidation.  
         [0053]      FIG. 2  shows an example of LPAR information inputted through the SVP  380  at the time of the setting of the LPARs of the disk controller  300 .  
         [0054]     The administrator inputs performance information into the SVP  380 . The inputted performance information contains the number of IOs per second (IOPS (processing capability)), a cache hit ratio [%], a block size, a cache capacity [GB], a disk drive capacity, a throughput [MB/s], and the like. It should be noted that the throughput is not necessarily required to be explicitly inputted and may be automatically computed by multiplying the IOPS by the block size. The administrator inputs this performance information for each set LPAR. It should be noted that it is also possible to create LPARs whose performance information is not inputted and whose performance is not designated. When performance is not designated for every LPAR, LPARs having the same performance are created based on a predetermined certain value, for instance. Also, when performance is not designated for some LPARs, after LPARs whose performance is designated are set, remaining LPARs are automatically created using resources which are not allocated, for instance.  
         [0055]     Next, LPAR allocation information is calculated from the performance information inputted by the administrator.  
         [0056]      FIG. 3  is a flowchart of LPAR allocation information calculation processing performed by the SVP  380 .  
         [0057]     First, from the IOPS of the inputted performance information, the SVP  380  calculates a processor execution ratio to be allocated to its corresponding LPAR. The processor execution ratio is calculated by dividing the IOPS by the maximum IOPS per processor. It should be noted that when the execution ratio exceeds 100%, a setting is made so that the processing of the LPAR is allocated to plural processors ( 1001 ).  
         [0058]     Next, a lower limit is determined for the number of disk drives to be used by the LPAR( 1002 ).  
         [0059]     The number of disk drives determines the IOPS of a corresponding LU formed by the disk drives. In other words, when the LU is formed by plural disk drives, as the number of drives used is increased, the parallelism of disk drive access is enhanced and the IOPS of the LU that is a collection of disk drives is improved.  
         [0060]     The lower limit of the number of disk drives is calculated by obtaining a cache miss ratio (%) through subtraction of a cache hit ratio (%) from a value “100”, multiplying the IOPS by the cache miss ratio, and dividing a result of the multiplication by the maximum IOPS per disk drive. It should be noted that when the total capacity of the calculated number of disk drives is below the disk drive capacity shown in the performance information inputted by the administrator, the disk drive capacity set by the administrator is given a higher priority. Therefore, the number of drives satisfying the set disk drive capacity is re-computed.  
         [0061]     Next, a cache capacity is set for the LPAR from the value of the cache capacity shown in the inputted performance information ( 1003 ).  
         [0062]     Next, a ratio of a band width of the internal network to be allocated to the LPAR is set with reference to a throughput value obtained by multiplying the processor IOPS by the block size. More specifically, a calculation is made in which the throughput value is divided by the total band width of the internal network ( 1004 ).  
         [0063]     Next, the operations in the steps  1001  through  1004  are executed for other LPARs ( 1005 ).  
         [0064]     Next, after the setting of the allocation information for the LPARs whose performance information has been inputted, remaining resources are allocated to LPARs whose performance information is not inputted ( 1006 ). Alternatively, when the setting for every LPAR is finished, the allocation is normalized so that every resource of the disk controller  300  is used up by the LPAR. For instance, when the execution ratio of the processor units  340  does not reach  100 % in total even after the setting for every LPAR, the execution ratio is re-computed for each LPAR so that the execution ratio becomes 100% in total.  
         [0065]     Through the processing described above, the LPAR allocation information of the disk controller  300  is set.  
         [0066]     It should be noted that the set information is sent from the SVP  380  to the channel control units  310 , the disk control units  320 , the internal switch units  330 , the processor units  340 , and the shared memory units  360  and is held therein. In the channel control units  310 , correspondences between the LPARs and the LUs after the allocation are held. The processor units hold a ratio of the processor processing to be used by each LPAR. The internal switch units  330  hold a ratio of the band width to be used by each LPAR. The shared memory units  360  hold a capacity of the cache memories  350  to be used by each LPAR and the configuration information (disk drive capacity, number of drives, block size, and the like) of an LU of the disk drive  200  to be used by each LPAR.  
         [0067]     Next, the configurations and operations of the processor units  340 , the channel control units  310 , and the internal switch units  330  of the disk controller  300  according to this embodiment will be described. It should be noted that in the following description, the LPARs are executed through time sharing.  
         [0068]     A host computer  100  sends a read request or a write request to the disk controller  300 . On receiving the request from the host computer, each channel control unit  310  finds a logical unit (LU) in the disk controller  300  with respect to which the request has been issued.  
         [0069]     The channel control unit  310  refers to a table (LPAR table  312  shown in  FIG. 5 ) showing correspondences between the LUs and the LPARs and finds an LPAR that is in charge of the LU with respect to which the request has been issued. Then, the channel control unit  310  sends the request to each processor unit  340  through each internal switch unit as processing of the LPAR. Following this, at a timing at which the LPAR processing should be performed, the processor unit  340  processes the request and performs access processing to the disk drives  200  by issuing an instruction to each cache memory unit  350  or each disk control unit  320  through the internal switch unit  330 .  
         [0070]      FIG. 4  is a block diagram showing a configuration of the processor unit  340 .  
         [0071]     A processor  342  is composed of a CPU and the like. It should be noted that in  FIG. 4 , only one processor  342  is shown, although the processor unit  340  may be provided with plural processors.  
         [0072]     An internal network interface (I/F) unit  343  is an interface that establishes connection between the processor unit  340  and the internal switch unit  330  and achieves data exchange therebetween.  
         [0073]     An LPAR instruction unit  344  instructs the processor  342  to perform allocation processing for each LPAR. In the LPAR instruction unit  344 , the LPAR number of an LPAR that is currently under processing is indicated. The processor unit LPAR information  341  stores information indicating a ratio of processing allocated to each LPAR as described above. The LPAR instruction unit  344  obtains the ratio of each LPAR from the processor unit LPAR information  341  and allocates an execution time to the LPAR.  
         [0074]     As a concrete example, a case where two LPARs, an “LPAR 1” and an “LPAR 2”, are set will be described.  
         [0075]     First, the LPAR instruction unit  344  allocates an execution time (ratio of the LPAR  1 ) to the LPAR  1  and instructs the processor  342  to start the processing of the LPAR  1 . Under this state, the LPAR under processing becomes the LPAR  1 . The LPAR instruction unit  344  counts a timer from a point in time when the processing of the LPAR  1  is started and, when the allocated execution time has expired, instructs the processor  342  to end the processing by the LPAR  1  and saves the data and register used in the processing by the LPAR  1 .  
         [0076]     Next, the LPAR instruction unit  344  allocates an execution time (ratio of the LPAR  2 ) to the LPAR  2  and instructs the processor  342  to start the processing of the LPAR  2 . Under this state, the LPAR under processing becomes the LPAR  2 . The LPAR instruction unit  344  counts the timer from a point in time when the processing of the LPAR  2  is started and, when the allocated execution time has expired, instructs the processor  342  to end the processing by the LPAR  2  and saves the data and register used in the processing by the LPAR  2 .  
         [0077]     Next, the LPAR instruction unit  344  allocates an execution time to the LPAR  1 . Hereafter, the processing of the LPAR  1  and the LPAR  2  is repeated.  
         [0078]     A main memory  345  is a memory used by the processor unit  340 . The main memory  345  is composed of a program area  346  storing programs and data area  347  storing data.  
         [0079]     The data area  347  is divided into plural areas that are respectively used by the LPARs. In each area, data and a communication queue used by its corresponding LPAR are held.  
         [0080]      FIG. 5  is a block diagram showing a configuration of the channel control unit  310 .  
         [0081]     A protocol conversion unit  311  is connected to each host computer  100  through a network or the like. The protocol conversion unit  311  performs conversion of each protocol used inside or outside the disk controller  300  and transmits/receives data.  
         [0082]     An internal network interface (I/F)  313  is an interface that is connected to each internal switch unit  330  and exchanges data with each unit of the disk controller  300 .  
         [0083]     An LPAR table  312  is a table showing the LPARs and the logical units (LUs) allocated to and used by the LPARs.  
         [0084]     As to the LUs used by the respective LPARs, after a disk capacity to be allocated to each LPAR is determined through the processing described with reference to  FIG. 3 , the administrator allocates an LU corresponding to the disk capacity to the LPAR and sets it using the SVP  380 . The protocol conversion unit  311  refers to this LPAR table  312  and knows an LPAR that is in charge of the LU with respect to which a request has been issued.  
         [0085]     When a request to an LU numbered “2” is issued by a host computer  100 , for instance, the protocol conversion unit  311  refers to the LPAR table  312  and knows that the LPAR corresponding to the LU numbered “2” is “1”. Then, the protocol conversion unit  311  adds the obtained number of the LPAR to the request and sends the request to each internal switch unit  330  through the internal network I/F unit  313 .  
         [0086]      FIG. 6  is a block diagram showing a configuration of the internal switch unit  330 .  
         [0087]     The internal switch unit  330  includes transmission units  332 , switching units  333 , and reception units  334 . The number of the switching units  333  is set equal to the number of the set LPARs. The number of the transmission units  332  and the number of the reception units  334  are each set equal to the number of the paths connected to the internal switch unit  330 .  
         [0088]     Each transmission unit  332  includes a TX interface (TX I/F)  3331 , LPAR transmission buffers  3332  ( 3332 - 0  through  3332 -n), an LPAR arbitration unit  3333 , and internal switch unit LPAR information  331 .  
         [0089]     The TX I/F  3331  is an output-side interface of the internal switch.  
         [0090]     The LPAR transmission buffers  3332 - 0  through  3332 -n are transmission buffers provided for the respective LPARs and the number of those buffers is set equal to the number of the set LPARs (O through n (n+1 buffers are provided)).  
         [0091]     The LPAR arbitration unit  3333  arbitrates the transmission of packets by the TX I/F  3331  for each LPAR. The internal switch unit LPAR information  331  stores information about a ratio of the band width of the internal switch unit  330  allocated to each LPAR.  
         [0092]     The number of the switching units  333 - 0  through  333 - n  is set equal to the number of the set LPARs and each switching unit sends packets passed from the reception units  334  to intended transmission units  332  based on transmission destination addresses.  
         [0093]     Each reception unit  334  includes an RX interface (RX I/F)  3341 , an LPAR judgment unit  3342 , and LPAR reception buffers  3343 - 0  through  3343 - n.    
         [0094]     The RX I/F  3341  is an input-side interface of the internal switch.  
         [0095]     The LPAR judgment unit  3342  finds, for each packet received by the RX I/F  3341 , an LPAR, to which the packet belongs, and sends the received packet to a reception buffer (LPAR reception buffer  3343 ) corresponding to the LPAR.  
         [0096]     The LPAR reception buffers  33 . 43 - 0  through  3343 -n are reception buffers provided for the respective LPARs and the number of these buffers is set equal to the number of the set LPARs ( 0  through n i.e. n+1 buffers are provided).  
         [0097]     Next, an operation of the internal switch unit  330  will be described.  
         [0098]     First, the RX I/F  3341  of the reception unit  334  sends each received packet to the LPAR judgment unit  3342 . The LPAR judgment unit  3342  refers to the header portion of the packet which has been sent and obtains the LPAR number of an LPAR to which the packet belongs. Then, the LPAR judgment unit  3342  sends the packet to an LPAR reception buffer  3343  corresponding to the obtained LPAR number. After receiving the packet, the LPAR reception buffer  3343  sends the packet to the switching unit  333  at a predetermined timing.  
         [0099]     The switching unit  333  refers to the header of the received packet, obtains the transmission destination address of the packet, and sends the packet to an LPAR transmission unit  332  corresponding to the address. In the transmission unit  332 , the packet is received by the LPAR transmission buffer  3332  corresponding to the LPAR number.  
         [0100]     The packet received by the LPAR transmission buffer  3332  is sent to the TX I/F  3331  and is transmitted therefrom according to an instruction from the LPAR arbitration unit  3333 .  
         [0101]     The LPAR arbitration unit  3333  refers to the internal switch unit LPAR information  331  and determines how to transmit the packet. As described above, the internal switch unit LPAR information  331  stores information indicating a ratio of the band width allocated to each LPAR.  
         [0102]      FIG. 7A  shows an example of the internal switch unit LPAR information  331 . In the example shown in  FIG. 7A , a ratio of the band width allocated to the LPAR numbered “0” is set at 30%, a ratio of the band width allocated to the LPAR numbered “1” is set at 20%, a ratio of the band width allocated to the LPAR numbered “2” is set at 40%, . . . , and a ratio of the band width allocated to the LPAR numbered “n” is set at 10%.  
         [0103]     The LPAR arbitration unit  3333  refers to the internal switch unit LPAR information  331  and determines a ratio of the band width to be used to send the packet to its corresponding LPAR.  
         [0104]     In actuality, as shown in  FIG. 7B , an “arbitration winner table” and an “arbitration winner pointer” stored in the internal switch unit LPAR information  331  are used, for instance. In the arbitration winner table, information instructing how to select the LPARs for packet transmission is stored in advance based on the band width allocation to the LPARs. More specifically, the arbitration winner table is composed of index numbers and LPAR numbers corresponding to the index numbers. The arbitration winner pointer is information that determines which LPAR is to be selected from the arbitration winner table. With the arbitration winner table in the example shown in  FIG. 7B , the LPARS numbered “0”, “1”, and “2” are respectively selected at ratios of 3/10, 2/10, and 5/10.  
         [0105]     The LPAR arbitration unit  3333  increments the arbitration winner pointer (adds “1” to the pointer at a time) at the time of start of arbitration. Then, the LPAR arbitration unit  3333  obtains an LPAR number corresponding to an index number in the arbitration winner table that has the same value as the pointer. Following this, a packet corresponding to the LPAR number obtained in this manner is transmitted.  
         [0106]      FIG. 8  shows an example of a packet  400  used by the disk controller  300  according to this embodiment.  
         [0107]     The packet  400  includes a packet type  401 , an LPAR number  402 , a transmission destination address  403 , a transmission source address  404 , and data  405 .  
         [0108]     The packet type  401  shows the type of the packet (whether the packet is a command or a response, for instance). The LPAR number  402  shows the number of an LPAR that is to deal with the packet. The transmission destination address  403  and the transmission source address  404  respectively show the transmission destination address and the transmission source address of the packet. The data  405  is the contents of data that the packet transmits.  
         [0109]     In the storage system according to the first embodiment configured in the manner described above, in the internal switch unit  330  of the disk controller  300 , a band width is allocated to each LPAR. As a result, arbitration between usage ratios of the band width of an internal network in a post-consolidation system, in which plural systems have been consolidated, becomes easy.  
         [0110]     Next, a second embodiment will be described.  
         [0111]     The second embodiment differs from the first embodiment in the configuration and processing of the internal switch unit. It should be noted that each component that is the same as that in the first embodiment is given the same reference numeral and the description thereof will be omitted.  
         [0112]      FIG. 9  is a block diagram showing a configuration of an internal switch unit  600  according to the second embodiment.  
         [0113]     The internal switch unit  600  includes transmission units  601 , a switching unit  602 , and reception units  603 . The number of the transmission units  601  and the number of the reception units  603  are each set equal to the number of paths connected to the internal switch unit  600 . Also, at least one switching unit  602  is provided in the internal switch unit  600 .  
         [0114]     Each transmission unit  601  includes a TX interface (TX I/F)  6011 , a transmission instruction unit  6012 , a memory controller  6013 , and a memory  6014 .  
         [0115]     The TX I/F  6011  is an output-side interface of the internal switch.  
         [0116]     The transmission instruction unit  6012  instructs the transmission of each packet held in the memory  6014  based on a ratio of a band width set for each LPAR.  
         [0117]     The memory controller  6013  controls the writing/reading of each packet into/from the memory  6014 .  
         [0118]     The memory  6014  temporarily holds each packet. Also, the memory  6014  stores information indicating a ratio of the band width allocated to each LPAR obtained through logical partitioning.  
         [0119]     The switching unit  602  sends packets passed from the reception units  603  to intended transmission units  601  based on transmission destination addresses.  
         [0120]     Each reception unit  603  includes an RX interface (RX I/F)  6031  and a reception buffer  6032 .  
         [0121]     The RX I/F  6031  is an input-side interface of the internal switch.  
         [0122]     The reception buffer  6032  temporarily holds each packet received by the RX I/F  6031 .  
         [0123]     Next, an operation of the internal switch unit  600  according to the second embodiment will be described.  
         [0124]     The RX I/F  6031  of the reception unit  603  sends each received packet to the reception buffer  6032 . After receiving the packet, the reception buffer  6032  sends the packet to the switching unit  602  at a predetermined timing.  
         [0125]     The switching unit  602  refers to the header of the received packet and sends the packet to an intended transmission unit  601 . This packet is held in the memory  6014  through the memory controller  6013  of the transmission unit  601 .  
         [0126]     The packet held in the memory  6014  is sent to the TX I/F  6011  and is transmitted therefrom according to an instruction from the transmission instruction unit  6012 .  
         [0127]      FIG. 10  shows an example of the contents of the memory  6014 .  
         [0128]     The memory  6014  is divided into internal switch unit LPAR information  6015  and a data area  6016 .  
         [0129]     As described above, the internal switch unit LPAR information  6015  is information indicating a ratio of the band width allocated to each LPAR obtained through the logical partitioning. In this example, the internal switch unit LPAR information  6015  is composed of pairs of LPAR numbers and pointers indicating addresses in the data area.  
         [0130]     Each packet sent from the switching unit  602  is stored in the data area  6016  under control by the memory controller  6013 . When doing so, the memory controller  6013  stores an address, at which the packet is stored, in a pointer of the internal switch unit LPAR information  6015  corresponding to an LPAR number obtained from the header information of the packet.  
         [0131]     Next, the transmission instruction unit  6012  sequentially refers to the internal switch unit LPAR information  6015  at predetermined time intervals, obtains packets held at addresses indicated by the pointers, sends the packets to the TX I/F  6011 , and instructs transmission of the packets.  
         [0132]     As a result, the packets are transmitted according to the ratios of the LPARs set in the internal switch unit LPAR information  6015 .  
         [0133]     In the storage system according to the second embodiment configured in the manner described above, like in the first embodiment, a ratio of a band width is allocated to each LPAR in the internal switch unit  330  of the disk controller  300 . As a result, arbitration between usage ratios of a path band width in a post-consolidation system, in which plural systems have been consolidated, becomes easy. In addition, it becomes sufficient that reception buffers, whose number is equal to the number of the paths connected to the internal switch unit, are provided and a configuration having no transmission buffer is realized. As a result, a situation is prevented in which the number of buffers is limited by the number of LPARs, which makes it possible to perform system configuration with more flexibility.  
         [0134]     Next, a third embodiment will be described.  
         [0135]     The third embodiment differs from the first embodiment in the configuration and processing of the internal switch unit. It should be noted that each component that is the same as that in the first embodiment is given the same reference numeral and the description thereof will be omitted.  
         [0136]      FIG. 11  is a block diagram showing a configuration of an internal switch unit  700  according to the third embodiment.  
         [0137]     The internal switch unit  700  includes transmission units  701 , connection units  702  and  705 , a memory controller  703 , a memory  704 , and reception units  706 . The number of the transmission units  701  ( 701 - 0  through  701 - m ) and the number of the reception units  706  ( 706 - 0  through  706 - m ) are each set equal to the number of physically set ports (reception ports and transmission ports) (m+1 transmission units and m+1 reception units are provided).  
         [0138]     Each transmission unit  701  includes a TX interface (TX I/F)  7011 , a packet transmission unit  7012 , and a memory controller  7013 .  
         [0139]     The TX I/F  7011  is an output-side interface of the internal switch.  
         [0140]     The packet transmission unit  7012  transmits each packet held in the memory  704  based on information stored in the internal switch unit LPAR information  7013  and indicating a ratio of the band width of the internal switch unit  700  allocated to each LPAR.  
         [0141]     The connection unit  702  connects the memory controller  703  and the respective transmission units  701 - 0  through  701 - m  to each other.  
         [0142]     The memory controller  703  controls the writing/reading of each packet into/from the memory  704 .  
         [0143]     The memory  704  temporarily holds each packet.  
         [0144]     The connection unit  705  connects the memory controller  703  and the respective reception units  706 - 0  through  706 -m to each other.  
         [0145]     Each reception unit  706  includes an RX interface (RX I/F)  7061 , a packet reception unit  7062 , and a transfer table  7063 .  
         [0146]     The RX I/F  7061  is an input-side interface of the internal switch. The packet reception unit  7062  holds each packet received by the RX I/F  7061  in the memory  704  through the memory controller  703 . In the transfer table  7063 , and the transmission destination address of the packet and the corresponding port number of a transmission unit  701  are stored in advance. The packet reception unit  7062  obtains an LPAR number and the transmission destination address from the header of the packet received by the RX I/F  7061  and stores the packet in a data area of the memory  704  corresponding to the port number.  
         [0147]     Next, an operation of the internal switch unit  700  according to the third embodiment will be described.  
         [0148]     Each packet received by the RX I/F  7061  of the reception unit  706  is passed to the memory controller  703  by the packet reception unit  7062 . When doing so, the packet reception unit  7062  obtains a transmission destination address contained in the packet and obtains a port number corresponding to the obtained transmission destination address from the transfer table  7063 . Then, the packet reception unit  7062  informs the memory controller  703  of the port number. Also, the packet reception unit  7062  determines an area of the memory  704  from the LPAR number of the received packet and the transmission destination port number of the packet.  
         [0149]     The memory controller receives the packet from the packet reception unit  7062  and holds it in the area of the memory  704  determined by the packet reception unit.  
         [0150]      FIG. 12  shows an example of the contents of the memory  704 .  
         [0151]     The memory  704  is divided into a reception entry  7041 , a reception data area  7042 , and a transmission entry  7043 .  
         [0152]     The reception entry  7041  includes entries corresponding to respective reception port numbers and each reception port entry includes entries corresponding to the respective set LPARs.  
         [0153]     The transmission entry  7043  includes entries corresponding to respective transmission port numbers and each transmission port entry includes entries corresponding to the respective set LPARs.  
         [0154]     The memory controller  703  searches the reception entry  7041  for a free entry by referring to an LPAR area corresponding to a received packet in an entry corresponding to the port number of a reception unit  706  that received the packet. The memory controller  703  judges each entry, in whose “valid” field a pointer is written, as an entry that is already used and judges each entry, in whose “valid” field a value “false” is written, as a free entry.  
         [0155]     Next, the received packet is held in the reception data area  7042 . Then, an address, at which the packet is held, is written in the free entry found as a result of the search described above.  
         [0156]     Next, the memory controller  703  obtains a transmission port number sent along with the packet from the reception unit  706  and stores a pointer to the entry, in which the address has been written, in an LPAR area corresponding to the packet in an entry corresponding to the transmission port number in the transmission entry  7043 .  
         [0157]     As described above, each packet received by the reception unit  706  is sequentially held in an entry of the reception entry  7041  corresponding to its reception port number and LPAR number and a pointer to the entry is sequentially written in the transmission entry  7043 .  
         [0158]     It should be noted that the transmission entry  7043  is held in a first-in first-out (FIFO) manner for each port number and each LPAR number.  
         [0159]     Each packet held in this manner is transmitted by the transmission unit  701 .  
         [0160]     First, the packet transmission unit  7012  refers to the internal switch unit LPAR information  7013  and obtains band width allocation to each LPAR. Then, the packet transmission unit  7012  reads each packet and transmits it according to the obtained allocation.  
         [0161]     In the packet reading, the transmission unit  701  refers to a transmission entry  7043  corresponding to the port number of itself and the LPAR number of an LPAR that should transmit the packet, obtains an entry in the reception entry  7041  by referring to a pointer held in the transmission entry  7043 , and obtains a pointer in the entry in the reception entry  7041  that indicates an address in the reception data area  7042 . Then, the transmission unit  701  reads the packet according to the obtained address.  
         [0162]     As to the band width allocation, a configuration is conceivable in which like in the first embodiment described by referring to  FIG. 7 , a arbitration winner table and a arbitration winner pointer are stored in advance in the internal switch unit LPAR information  7013  and the packet transmission unit  7012  transmits a packet having an LPAR number corresponding to the arbitration winner pointer.  
         [0163]     In the storage system according to the third embodiment configured in the manner described above, like in the first embodiment, a ratio of a band width is allocated to each LPAR in the internal switch unit  330  of the disk controller  300 . As a result, arbitration between usage ratios of a path band width in a post-consolidation system, in which plural systems have been consolidated, becomes easy. In addition, reception buffers or transmission buffers are not provided for each LPAR thus set, which makes it possible to perform system configuration with more flexibility.  
         [0164]     Next, a fourth embodiment will be described.  
         [0165]     The fourth embodiment differs from the first embodiment in the configuration and processing of the disc control device  300 . It should be noted that each component that is the same as that in the first embodiment is given the same reference numeral and the description thereof will be omitted.  
         [0166]      FIG. 13  is a block diagram showing a configuration of a storage system according to the fourth embodiment.  
         [0167]     The fourth embodiment differs from the first embodiment shown in  FIG. 1  in that the processor unit  340  does not exist and a channel control unit  800  is used in place of the channel control unit  310 . Other components are the same as those in  FIG. 1 .  
         [0168]     In the fourth embodiment, the channel control unit  800  achieves the function of the processor unit  340  in the first embodiment. It should be noted that a configuration may be used instead in which the disk control unit  320  achieves the function of the processor unit  340  instead of the channel control unit  800 . Also, the processor unit may be contained in both of the channel control unit  800  and the disk control unit  320 , thereby distributing the function of the processor.  
         [0169]      FIG. 14  is a block diagram showing a configuration of the channel control unit  800  according to the fourth embodiment.  
         [0170]     In the channel control unit  800  according to the fourth embodiment, the function of the processor unit  340  shown in  FIG. 4  is contained in the channel control unit  310  shown in  FIG. 5  according to the first embodiment.  
         [0171]     A protocol conversion unit  810  is connected to each host computer  100  through a network or the like. The protocol conversion unit  810  performs conversion of each protocol used in the host computer  100  or the disk controller  300  and transmits/receives data.  
         [0172]     An internal network interface (I/F)  850  is an interface that is connected to each internal switch unit  330  and exchanges data with each unit of the disk controller  300 .  
         [0173]     A processor  820  is composed of a CPU and the like. It should be noted that in  FIG. 14 , only one processor  820  is shown, although plural processors may be provided in the channel control unit  800 .  
         [0174]     An LPAR instruction unit  830  instructs the processor  820  to perform LPAR allocation processing. In the LPAR instruction unit  830 , the LPAR number of an LPAR that is currently under processing is indicated. Channel control unit LPAR information  831  stores information indicating a ratio of processing allocated to each LPAR, as described above. The LPAR instruction unit  830  obtains the ratio of each LPAR from the channel control unit LPAR information  831  and allocates an execution time to each LPAR.  
         [0175]     A main memory  840  is a memory used by the channel control unit  800 . The main memory  840  is composed of a program area  841  storing programs, a data area  842  storing data, and an LPAR table  844 .  
         [0176]     The LPAR table  844  is a table showing the LPARs and LUs allocated to and used by the LPARs.  
         [0177]     The data area  842  includes plural areas  842 - 0  through  842 -n used by the respective LPARs and a protocol conversion unit communication queue  843 . In each LPAR area  842 , data and a communication queue used by its corresponding LPAR are held.  
         [0178]     The protocol conversion unit communication queue  843  is a communication queue used by the protocol conversion unit  810 . On receiving a request from a host computer, the protocol conversion unit  810  temporarily holds the contents of the request in the protocol conversion unit communication queue  843 .  
         [0179]     Before starting processing of each LPAR, the processor  820  first refers to the protocol conversion unit communication queue  843 . When any data is held in the protocol conversion unit communication queue  843 , the processor transfers the data to the communication queue in a corresponding LPAR area.  
         [0180]     On the other hand, as to each packet received by the internal network I/F unit  850 , the internal network I/F unit  850  obtains an LPAR number by referring to the header of the packet and holds the packet in the communication queue in an LPAR area corresponding to the obtained LPAR number.  
         [0181]      FIG. 15  shows an example of the LPAR table  844 .  
         [0182]     The LPAR table  844  is composed of a “port ID” column showing the identifiers of ports that received host commands, a “host group” column showing host groups to which hosts that have issued the host commands belong, an “LU” column showing the LU numbers of LUs with respect to which the host commands have been issued, and an “LPAR” column showing the LPAR numbers of the host commands.  
         [0183]     On receiving a request (host command) from a host computer  100 , the processor  820  of the channel control unit  800  finds a host group, to which the host belongs, with reference to the host ID of the host. The processor  820  obtains “a port ID”, “a host group”, and “an LU number” by referring to the contents of the host command. The processor  820  obtains a corresponding LPAR number by referring to the LPAR table  844  using each obtained piece of information as keys. Then, the processor  820  adds the obtained LPAR number to the header information of the packet and holds it in a corresponding LPAR area of the main memory  840 .  
         [0184]     As described in the first embodiment, after a disk capacity to be allocated to each LPAR is determined through the processing described with reference to  FIG. 3 , the LPAR table is set by the SVP  380  through the allocation of an LU corresponding to the disk capacity by the administrator.  
         [0185]     It should be noted that in the LPAR table  312  of the channel control unit  320  according to the first embodiment, the processing shown in  FIG. 15  may be performed. In this case, the protocol conversion unit  311  obtains an LPAR number by referring to the contents of a host command.  
         [0186]     In the storage system according to the fourth embodiment configured in the manner described above, a ratio of the band width is allocated to each LPAR in the internal switch unit  330  of the disk controller  300 . As a result, the arbitration between the usage ratios of a path band width in a post-consolidation system, in which plural systems have been consolidated, becomes easy.  
         [0187]     It should be noted that as the internal switch unit according to the fourth embodiment, it is possible to use any one of the internal switch unit according to the first embodiment shown in  FIG. 6 , the internal switch unit according to the second embodiment shown in  FIG. 9 , and the internal switch unit according to the third embodiment shown in  FIG. 11 .  
         [0188]     While the present invention has been described in detail and pictorially in the accompanying drawings, the present invention is not limited to such detail but covers various obvious modifications and equivalent arrangements, which fall within the purview of the appended claims.