Abstract:
A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    Priority is claimed to Korean patent application number 10-2011-0137331 filed on Dec. 19, 2011, the entire disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field of Invention 
         [0003]    Embodiments of the present invention relate to a semiconductor device, a memory system and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device, and a memory system and a manufacturing method of the same. 
         [0004]    2. Description of Related Art 
         [0005]    A non-volatile memory device retains data even in the absence of power supply. Two-dimensional memory devices in which memory cells are fabricated in a single layer over a silicon substrate have reaches physical limits in increasing their degree of integration. Accordingly, three-dimensional non-volatile memory devices in which memory cells are stacked in a vertical direction over a silicon substrate have been proposed. 
         [0006]    Hereinafter, the structure of a three-dimensional (3-D) non-volatile memory device is described with reference to  FIG. 1 . 
         [0007]      FIG. 1  is a perspective view illustrating the structure of a conventional 3-D non-volatile memory device. 
         [0008]    As shown in  FIG. 1 , the conventional 3-D non-volatile memory device may include channel structures C, vertical gates  14  and word lines WL. The channel structures C may extend in parallel along a first direction I-I′. The vertical gates  14  may be located between adjacent channel structures C and protrude from the substrate  10 . The word lines WL may be coupled to the vertical gates  14  and extend in parallel along a second direction II-II′. 
         [0009]    Here, each of the channel structures C may include interlayer insulating layers  11  and channel layers  12  that are alternately stacked over the substrate  10 . In addition, a tunnel insulating layer  13 A, a charge trap layer  13 B and a charge blocking layer  13 C may be interposed between the vertical gates  14  and the channel structures C. 
         [0010]    According to the above-described structure, a string may be arranged in a horizontal direction against the substrate  10 . These strings may be stacked over the substrate  10 . Therefore, as compared to a two-dimensional structure memory device, an integration degree of the 3-D memory device having the above structure may be increased. However, because a well region is not provided in a 3-D memory device, the 3-D memory device may have a low operating speed. 
       BRIEF SUMMARY 
       [0011]    An embodiment of the present invention relates to a three-dimensional non-volatile memory device with improved operating speed, and a memory system and a manufacturing method of the same. 
         [0012]    A three-dimensional (3-D) non-volatile memory device according to an embodiment of the present invention includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pickup line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures. 
         [0013]    A memory system according to another embodiment of the present invention includes a three-dimensional (3-D) non-volatile memory device including channel structures each having channel layers that are stacked over a substrate and includes respective well regions, vertical gates located and spaced from each other between the channel structures, and a well pickup line contacting on the well regions the channel layers and extending in a direction crossing the channel structures, and a memory controller configured to control the 3-D non-volatile memory device. 
         [0014]    A method of manufacturing a three-dimensional (3-D) non-volatile memory device according to yet another embodiment of the present invention includes forming channel structures each including channel layers and interlayer insulating layers stacked alternately over a substrate, wherein the channel layers include well regions, respectively, forming vertical gates spaced from each other between the channel structures, and a well pickup line contacting on the well regions of the channel layers and extending in a direction crossing the channel structures. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a perspective view illustrating the structure of a conventional three-dimensional (3-D) non-volatile memory device; 
           [0016]      FIGS. 2A to 5B  are views illustrating a method of manufacturing a 3-D non-volatile memory device according to an embodiment of the present invention; 
           [0017]      FIG. 6  is a block diagram illustrating a memory system according to an embodiment of the present invention; and 
           [0018]      FIG. 7  is a block diagram illustrating a computing system according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0019]    Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The figures are provided to enable those of ordinary skill in the art to make and use the present invention according to the embodiments of the present invention. 
         [0020]      FIGS. 2A to 5B  are views illustrating a method of manufacturing a three-dimensional (3-D) non-volatile memory device according to an embodiment of the present invention.  FIGS. 2A to 5A  are perspective views.  FIGS. 2B to 4B  are plan views taken along line A-A′ of  FIGS. 2A to 4A , respectively, and  FIG. 5B  is a top plan view of  FIG. 5A . 
         [0021]    As illustrated in  FIGS. 2A and 2B , an interlayer insulating layer  21  and a channel layer  22  may be formed over a substrate  20 . Here, the interlayer insulating layer  21  may comprise an oxide layer. The channel layer  22  may comprise a semiconductor layer such as a polysilicon layer, or a polysilicon layer doped with P type impurities at a low concentration. 
         [0022]    According to an embodiment of the present invention, channel structures C may be formed in subsequent processes. The channel structures C may include channel layers stacked over the substrate  20 . Memory cells MC may be formed along sidewalls of the channel structures C. In addition, each of the channel layers may be doped with impurities to form a well region W and a source region S. For example, the well region W may be located at one end of each of the channel layers included in the channel structure C. The source region S may be located between the well region W and a region MC in which memory cells are formed. In  FIG. 2B , positions of corresponding regions are indicated by dotted lines for illustration purposes. 
         [0023]    A portion of the channel layer  22  may be doped with impurities to form the well region W. For example, a mask pattern (not shown) that exposes the portion of the channel layer  22  may be formed over the channel layer  22 . Subsequently, the channel layer  22  may be doped with impurities by using the mask pattern as a barrier to thus form the well region W. The mask pattern may expose a portion of the channel layer  22  in which the well region W is formed, while the mask pattern may cover other portions of the channel layer  22  in which the source region S and the memory cells MC are formed. The channel layer  22  may be doped with impurities by using an ion implantation process or a plasma doping process. For example, the channel layer  22  may be doped with P-type impurities such as Boron (B). In this case, a P type well region W having a high impurity concentration may be defined in a P type channel having a low impurity concentration. More specifically, the well region W may include the same type of impurities as the channel layer  22 , and the well region W may have a higher impurity concentration than the channel layer  22 . 
         [0024]    As illustrated in  FIGS. 3A and 3B , the processes of forming the interlayer insulating layer  21 , the channel layer  22  and the well region W may be repeated a number of times. In other words, the interlayer insulating layers  21  and the channel layers  22  may be alternately formed. Each time the channel layer  22  is formed, a portion of the channel layer  22  may be doped with impurities to form the well region W. 
         [0025]    After the interlayer insulating layers  21  and the channel layers  22  are alternately formed by the number of strings to be stacked, the interlayer insulating layers  21  and the channel layers  22  that are alternately stacked may be etched to form the channel structures C. The channel structures C may extend in parallel along one direction. Therefore, the channel structures C may include channel layers  22 A that are stacked over the substrate  20 . Each of the channel layers  22 A may include the well region W. Here, interlayer insulating layers  21 A may be interposed between the channel layers  22 A that are stacked. 
         [0026]    For reference, after the channel structures C are formed, the well regions W of the channel layers  22 A may be formed at the same time. For example, after the interlayer insulating layers  21  and the channel layers  22  may be alternately formed and subsequently etched to form the channel structures C, a mask pattern that exposes the well regions W may be formed. Subsequently, exposed regions of the channel layers  22 A may be doped with impurities by using a tilting ion implantation process or a plasma doping process by using a mask pattern as a barrier. In this manner, the well regions W of the channel layers  22 A stacked upon one another may be formed at the same time. 
         [0027]    Here, since the well regions W are formed by doping the channel layers  22 A exposed on sidewalls of the channel structures C with impurities, conditions of an impurity doping process may be controlled so that the center area of the channel layers  22  may be doped sufficiently. 
         [0028]    As illustrated in  FIGS. 4A and 4B , memory layers  23  may be formed. Each of the memory layers  23  may be formed over an entire surface of a resultant structure including the channel structures C. The memory layer  23  may be formed to store data by injecting/discharging charges. For example, the memory layer  23  may include a tunnel insulating layer, a charge trap layer and a charge blocking layer. 
         [0029]    Subsequently, conductive layers  24  may be formed on the memory layers  23 . The conductive layer  24  may have such a thickness that the conductive layer  24  may be filled between the channel structures C and may be formed on the top of the channel structures C. Subsequently, a mask pattern (not shown) in the form of lines that extend in parallel along a direction crossing the channel structures C may be formed over the conductive layer  24 . Subsequently, the conductive layer  24  and the memory layer  23  may be etched by using the mask pattern as a barrier. 
         [0030]    As a result, vertical gates and word lines WL may be formed. The vertical gates may be located between the channel structures C. The word lines WL may couple the vertical gates and extend in a direction crossing the channel structures C. Here, the memory layers  23  may be interposed between the word lines WL and the channel structures C. The memory cells MC may be formed along the sidewalls of the channel structures C. 
         [0031]    Subsequently, a mask pattern  25  used to form a junction and a source region may be formed over a resultant structure having the word lines WL. For example, the mask pattern  25  may be a photoresist pattern. The mask pattern  25  may prevent the well regions W from being doped with impurities in subsequent impurity doping processes. The mask pattern  25  may have a large area enough to completely cover the well regions W. In addition, the mask pattern  25  may completely expose the source regions S and the region MC in which the memory cells MC are formed. 
         [0032]    Subsequently, the channel layers  22 A exposed between the mask pattern  25  and the word lines WL may be doped with impurities. For example, the channel layers  22 A may be doped with N type impurities such as phosphorous (P) or phosphorous (As). In this case, N type junctions  26  and N type source regions S may be formed in P type channel layers  22 A. 
         [0033]    Here, sidewalls of the channel layers  22 A exposed on both sidewalls of the channel structures C may be doped with impurities to form the junctions  26  and the source regions S. Here, the junctions  26  may be formed in each of the channel layers  22 A exposed between the vertical gates  24 . The source regions S may be formed on portions of the channel layers  22 A. For example, each of the source regions S may be formed between the word lines WL and the well region W. 
         [0034]    The sidewalls of the channel layers  22 A may be doped with impurities by using a plasma doping process or a tilting ion implantation process in which ions are implanted while tilting the substrate. Here, the channel layers  22 A may be doped with impurities from surfaces of both sidewalls thereof to a given depth. Conditions of an impurity doping process may be controlled to separate the junctions  26 , the source regions S and the well regions W from each other. 
         [0035]    As illustrated in  FIGS. 5A and 5B , after the mask pattern  25  is removed, an interlayer insulating layer (not illustrated) may be formed over a resultant structure having the junctions  26 . Here, the interlayer insulating layer may comprise an oxide layer. 
         [0036]    Subsequently, the interlayer insulating layer may be etched to form a source line trench that exposes the source regions S of the channel structures C and a well pickup line trench that exposes the well regions W of the channel structures C. Subsequently, the source line trench and the well pickup line trench may be filled with conductive layers. Therefore, a source line SL and a well pickup line Well_PL may be formed. The source line SL may extend in the direction crossing the channel structures C and contact on the source regions S of the channel layers  22 A. The well pickup line Well_PL may contact on the well regions W of the channel layers  22 A. 
         [0037]    Here, the source line SL and the well pickup line Well_PL may have structures substantially similar to the word line WL. The source line SL and the well pickup line Well_PL each may have vertical gate portions located between the channel structures C and line portions coupling the vertical gate portions. 
         [0038]    A three-dimensional (3-D) non-volatile memory device according to an embodiment of the present invention may be manufactured by performing the aforementioned processes. The 3-D non-volatile memory device may include the channel structures C, the vertical gates  24 , the junctions  26 , the source line SL and the well pickup line Well_PL. The channel structures C may include the channel layers  22 A stacked over the substrate  20 . Each of the channel layers  22 A may have the source region S and the well region W. The vertical gates  24  may be located between the channel structures C. The junctions  26  may be formed within the channel layer  22 A exposed between the vertical gates  24 . The source line SL may contact on the source regions S of the channel layers  22 A and extend in the direction crossing the channel structures C. The well pickup line Well_PL may contact on the well regions W of the channel layers  22 A and extend in the direction crossing the channel structures C. 
         [0039]    In particular, source and drain regions of memory cells may be easily formed. In addition, the source region S and the well region W may be easily formed in each of the channel layers  22 A stacked over the substrate  20 . Therefore, a program speed of the memory device may be increased, and cell current may be increased, thus ensuring a sensing margin. In addition, contact resistance between the source line and the source region and between the well pickup line and the well region may be reduced to improve an erase speed. 
         [0040]      FIG. 6  is a diagram illustrating a memory system according to an embodiment of the present invention. 
         [0041]    As illustrated in  FIG. 6 , a memory system  100  according to an embodiment of the present invention includes a non-volatile memory device  120  and a memory controller  110 . 
         [0042]    The non-volatile memory device  120  may have the structure described in connection with  FIGS. 2A to 5B . In addition, the non-volatile memory device  120  may be a multi-chip package composed of a plurality of flash memory chips. 
         [0043]    The memory controller  110  is configured to control the non-volatile memory device  120 . The memory controller  110  may include SRAM  111 , a CPU  112 , a host interface  113 , an ECC  114  and a memory interface  115 . The SRAM  111  may function as an operation memory of the CPU  112 . The CPU  112  may perform the general control operation for data exchange of the memory controller  110 . The host interface  113  may include a data exchange protocol of a host being coupled to the memory system  100 . In addition, the ECC  114  may detect and correct errors included in data read from the non-volatile memory device  120 . The memory interface  115  may perform to interface with the non-volatile memory device  120 . The memory controller  110  may further include RCM that stores code data to interface with the host. 
         [0044]    The memory system  100  having the above-described configuration may be a solid state disk (SSD) or a memory card in which the memory device  120  and the memory controller  110  are combined. For example, when the memory system  100  is an SSD, the memory controller  110  may communicate with the outside (e.g., a host) through one of the interface protocols including USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI and IDE. 
         [0045]      FIG. 7  is a block diagram illustrating a computing system according to an embodiment of the present invention. 
         [0046]    As shown in  FIG. 7 , a computing system  200  according to an embodiment of the present invention may include a CPU  220 , RAM  230 , a user interface  240 , a modem  250  and a memory system  210  that are electrically coupled to a system bus  260 . In addition, when the computing system  200  is a mobile device, a battery may be further included to apply operating voltage to the computing system  200 . The computing system  200  may further include application chipsets, a Camera Image Processor (CIS), and mobile DRAM. 
         [0047]    As described above with reference to  FIG. 6 , the memory system  210  may include a non-volatile memory  212  and a memory controller  211 . 
         [0048]    A 3-D non-volatile memory device may have a well region defined in each channel layer and have a junction formed between memory cells. Therefore, a program speed may be improved, and cell current may be increased, thus ensuring sensing margin. In addition, contact resistance between a source line and a source region and between a well pickup line and a well region may be reduced to thus improve an erase speed.