Abstract:
The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of semiconductor packaging, and, more particularly, to a 3-D semiconductor device and semiconductor process for manufacturing the same. 
     2. Description of the Related Art 
     In stacked-chip packaging, multiple integrated circuit chips can be packaged in a single package structure in a vertically stacked manner. This increases stack density, making the package structure smaller, and often reduces the length of the path that signals must traverse between chips. Thus, stacked-chip packaging tends to increase the speed of signal transmission between or among chips. Additionally, stacked-chip packaging allows chips having different functions to be integrated in a single package structure. Use of through silicon vias (TSV) has been a key technology in realizing stacked-chip packaging integration due to the ability to provide short vertical conductive paths between chips. 
     SUMMARY OF THE INVENTION 
     One aspect of the disclosure relates to a semiconductor device. In one embodiment the semiconductor device comprises a substrate; a conductive via formed in the substrate, the conductive via having a first end substantially coplanar with an inactive surface of the substrate; a circuit layer, disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via; a redistribution layer disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end and electrically connected thereto, and a second portion positioned upward and away from the first portion; and a die, disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer. The semiconductor device can further include a dielectric layer disposed between the inactive surface of the substrate and the second portion of the redistribution layer, and a protection layer covering the redistribution layer and the dielectric layer, the protection layer having openings to expose portions of the redistribution layer. which facilitate the electrical connection between the die and the redistribution layer. Additionally, the semiconductor device can include a plurality of under bump metallurgies (UBMs), disposed adjacent to the active surface of the substrate and electrically connected to the circuit layer. The circuit layer and the die can each include one or more integrated passive device (IPD). The conductive via can include a conductive via that comprises a seed layer comprising an annular portion disposed vertically and a base portion contiguous with the annular portion and adjacent and substantially parallel to the active surface and a second metal layer disposed on interior surfaces of the seed layer. In other embodiments, the conductive via can be a solid pillar. 
     In another embodiment, the conductive via formed in the substrate of the substrate can protrude from the inactive surface of the substrate. In this case, the redistribution layer can be disposed on all surfaces (including the side surfaces) of the protruding tip of the conductive via, to provide enhanced electrical contact and a more secure attachment. 
     Another aspect of the disclosure relates to manufacturing a semiconductor device. In one embodiment, a method of making a semiconductor device comprises (a) providing a wafer having a substrate and a circuit layer, wherein the substrate has an active surface and a inactive surface, and the circuit layer is disposed adjacent to the active surface; (b) forming a plurality of under bump metallurgies (UBMs) on the circuit layer; (c) attaching a carrier to the wafer, wherein the under bump metallurgies (UBMs) face the carrier; (d) forming a redistribution layer on the inactive surface; (e) attaching a die adjacent to the inactive surface, wherein the die is electrically connected to the redistribution layer; and (f) forming a molding compound adjacent to the inactive surface to encapsulate the die. In step (a), the circuit layer can comprise a plurality of first pads, a plurality of second pads, a first protection layer and a first dielectric layer; the first dielectric layer is disposed on the active surface of the substrate; the first pads and the second pads are disposed on the first dielectric layer; the first protection layer covers the first pads and has a plurality of openings to expose the second pads. In step (b), the under bump metallurgies (UBMs) can be formed in the openings of the first protection layer to contact the second pads. After step (c), the semiconductor process can comprise the steps of: (c1) forming a plurality of interconnection metals in the substrate to electrically connect the circuit layer; and (c2) is forming a redistribution layer adjacent to the inactive surface, wherein the redistribution layer is electrically connected to the interconnection metals. Additionally, step (c1) can comprise the steps of (c11) forming a plurality of cylindrical cavities from the inactive surface of the substrate, wherein the cylindrical cavities expose a part of the circuit layer; (c12) forming the interconnection metals in the cylindrical cavities; (c13) forming a plurality of circular grooves from the inactive surface of the substrate, wherein each of the circular grooves surrounds each of the interconnection metals; and (c14) forming an insulation circular layer in each of the circular grooves. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present invention; 
         FIG. 2(   a ) illustrates a partially enlarged cross-sectional view of the semiconductor device of  FIG. 1 ; 
         FIG. 2(   b ) illustrates a partially enlarged cross-sectional view of a semiconductor device according to another embodiment of the present invention; 
         FIG. 3  illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present invention; 
         FIGS. 4 to 19  illustrate a semiconductor process for manufacturing a semiconductor device according to an embodiment of the present invention; and 
         FIGS. 20 to 23  illustrate a semiconductor process for manufacturing a semiconductor device according to another embodiment of the present invention. 
     
    
    
     Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements. The present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 1 , a cross-sectional view of a semiconductor device  1 , according to an embodiment of the present invention, is illustrated. The semiconductor device  1  comprises a substrate  11 , a first dielectric layer  12 , a circuit layer  13 , a plurality of under bump metallurgies (UBMs)  24 , a plurality of interconnection metals  35 , a central insulation material  36 , an insulation circular layer  361 , a second dielectric layer  40 , a redistribution layer  48 , a second protection layer  50 , a die  2 , a plurality of bonding wires  21 , a plurality of solder balls  54  and a molding compound  3 . 
     The substrate  11  has an active surface  111 , an inactive surface  112  and a plurality of through holes  115 . In this embodiment, the material of the substrate  11  is a semiconductor material such as silicon or germanium. However, in other embodiments, the material of the substrate  11  may be glass. 
     The first dielectric layer  12  is disposed on the active surface  111  of the substrate  11 . In this embodiment, the material of the first dielectric layer  12  is silicon oxide or silicon nitride. However, in other embodiments, the first dielectric layer  12  may include a polymer, such as polyimide (PI) or polypropylene (PP). 
     The circuit layer  13  is disposed adjacent to the active surface  111  of the substrate  11 . In this embodiment, the circuit layer  13  is disposed on the first dielectric layer  12 , and includes a plurality of first pads  14   a , a plurality of second pads  14   b  and a first protection layer  16 . The first pads  14   a , the second pads  14   b  and the first protection layer  16  are disposed on the first dielectric layer  12 . The first pads  14  and the second pads  14   b  are parts of one of the metal layers (not shown) of the circuit layer  13 . In this embodiment, the material of the metal layers is copper. The first protection layer  16  covers the first pads  14  and has a plurality of openings  161  to expose the second pads  14   b . In this embodiment, the first protection layer  16  includes a polymer such as polyimide (PI) or polypropylene (PP). However, in other embodiments, the material of the first protection layer  16  can be silicon oxide or silicon nitride. 
     In this embodiment, the circuit layer  13  further includes at least one first integrated passive device (IPD)  15  disposed on the first dielectric layer  12  and covered by the first protection layer  16 . Therefore, the first integrated passive device (IPD)  15  is adjacent to the active surface  111  of the substrate  11 . In this embodiment, the first integrated passive device (IPD)  15  is an inducer. However, the first integrated passive device (IPD)  15  may be include a capacitor, a resistor, or a combination of a inducer, a capacitor and a resistor. 
     Each of the under bump metallurgies (UBM)  24  is disposed in each of the openings  161  of the first protection layer  16  to contact the second pads  14   b , so that the under bump metallurgies (UBMs)  24  are electrically connected to the circuit layer  13 . In this embodiment, the under bump metallurgy (UBM)  24  comprises a first metal layer  22  and a first seed layer  18 . The first metal layer  22  is a single layer or multi-layer structure. The material of the first seed layer  18  is tantalum nitride, and the material of the first metal layer  22  is a mixture of nickel (Ni), palladium (Pd), and gold (Au); nickel (Ni) and gold (Au); or nickel (Ni) and palladium (Pd). However, the first seed layer  18  may be omitted. The solder balls  54  are disposed on the under bump metallurgies (UBM)  24 . 
     Each of the interconnection metals  35  is disposed in each of the respective through holes  115  of the substrate  11 , and electrically connects the circuit layer  13  and the redistribution layer  48 . In the present embodiment, the interconnection metal  35  further extends through the first dielectric layer  12  to contact the first pad  14   a . The interconnection metal  35  has a second metal layer  34  and a second seed layer  32  surrounding the second metal layer  34 , and the base of the second seed layer  32  contacts the first pad  14   a . The second seed layer  32  comprises an annular portion disposed vertically (with respect to the through holes  115 ) and the base of the second seed layer  32  is contiguous with the annular portion and adjacent and substantially parallel to the active surface  111 . In the present embodiment, the central insulation material  36  is disposed in the interior portion  351 . It is to be understood that the interconnection metal  35  may be a solid pillar instead, and the central insulation material  36  would then be omitted. The material of the second seed layer  32  is tantalum nitride or tantalum tungsten, and the material of the second metal layer  34  is copper. However, the second seed layer  32  may be omitted. 
     In this embodiment, the insulation circular layer  361  is disposed in the through hole  115  and surrounds the interconnection metal  35 . As shown in  FIG. 1 , the insulation circular layer  361  has a bottom surface and the bottom surface contacts the first dielectric layer  12 ; that is, the insulation circular layer  361  does not extend into the first dielectric layer  12  and the interconnection metal  35  extends partly to the circuit layer  13 . Therefore, the bottom surface of the interconnection metal  35  is not coplanar with the bottom surface of the insulation circular layer  361 , and the length of the interconnection metal  35  is greater than that of the insulation circular layer  361 . The material of the central insulation material  36  can be a polymer, which is the same as the insulation circular layer  361 . 
     The second dielectric layer  40  is disposed on the inactive surface  112  of the substrate  11 , and has a plurality of openings  401  to expose the interconnection metals  35 . In this embodiment, the second dielectric layer  40  includes a polymer such as polyimide (PI) or polypropylene (PP). However, in other embodiments, the material of the second dielectric layer  40  can be silicon oxide or silicon nitride. 
     The redistribution layer  48  is disposed adjacent to the inactive surface  112  of the substrate  11 . In this embodiment, the redistribution layer  48  is disposed on the second dielectric layer  40  and in the openings  401  of the second dielectric layer  40  to contact the interconnection metals  35 . In this embodiment, the redistribution layer  48  comprises a third seed layer  42  and a third metal layer  46 . The material of the third seed layer  42  is tantalum nitride or tantalum tungsten, and the material of the third metal layer  46  is copper. However, the third seed layer  42  may be omitted. 
     The second protection layer  50  covers the redistribution layer  48  and the second dielectric layer  40 , and has a plurality of openings  501  to expose a part of the redistribution layer  48 . In this embodiment, a surface finish layer  52  is plated on the exposed part of the redistribution layer  48 . 
     The die  2  is disposed adjacent to the inactive surface  112  of the substrate  11  and electrically connected to the redistribution layer  48 . In this embodiment, the die  2  has an active surface  202 , an inactive surface  203 , a plurality of pads  204  and at least one second integrated passive device (IPD)  29 . The pads  204  and the second integrated passive device (IPD)  29  are disposed adjacent to the active surface  202  of the die  2 . In this embodiment, the second integrated passive device (IPD)  29  is an inducer. However, the second integrated passive device (IPD)  29  may be a capacitor, a resistor, or a combination of a inducer, a capacitor and a resistor. In this embodiment, the first integrated passive device (IPD)  15  is disposed adjacent to the active surface  111  of the substrate  11  and the second integrated passive device (IPD)  29  is disposed adjacent to the active surface  202  of the die  2 . The interference of magnetic field between first IPD  15  and second IPD  29  is inversely proportional to the distance. Therefore, if the die  2  is disposed adjacent to the inactive surface  112  of the substrate  11 , it will have a larger distance than the die which is disposed on the active surface  111  of the substrate  11 . Based on the following formula: 
             Q   =       1   R     ⁢       L   C               
The frequency Q-factor is related to the inductance (L), and is proportional to the inductance (L) if the resistance (R) and capacitance (C) are constant. For this reason, this embodiment with enhanced inductances has an enhanced frequency Q-factor.
 
     The inactive surface  203  of the die  2  is adhered on the second protection layer  50 . The pads  204  are electrically connected to the surface finish layer  52  on the exposed part of the redistribution layer  48  through the bonding wires  21 . That is, the bonding wires  21  connect the die  2  and the redistribution layer  48 . In this embodiment, the bonding type of the bonding wires  21  is a reverse bond. The first step of the reverse bond is forming a first wire ball  211  on the pad  204  of the die  2 . Then, the tip of the wire  21  is formed another wire ball and is bonded on the surface finish  52 . Finally, the wire  21  is cut off after it is drawn to contact the first wire ball  211 . 
     The molding compound  3  is disposed adjacent to the inactive surface  112  of the substrate  11 , and encapsulates the die  2  and the bonding wires  21 . In this embodiment, the molding compound  3  is disposed on the second protection layer  50 . 
     Referring to  FIG. 2(   a ), a partially enlarged cross-sectional view of the semiconductor device  1  is illustrated. As shown, the conductive via (comprising the interconnection metals  35 , central insulation material  36 , and insulation circular layer  361  which are disposed in the through hole  115 ) has a first end  37  substantially coplanar with the inactive surface  112  of the substrate  11 . Additionally, the insulation circular layer  361  isolates the conductive via from the substrate  11 . The insulation circular layers  361  are hollow cylinders formed in the substrate  11 . The second seed layer  32  is disposed on inboard sidewalls of the insulation circular layer  361 . The second metal layer  34  is disposed on inboard sidewalls of the second seed layer  32 . The second seed layer  32  and the second metal layer  34  are also hollow cylinders similar to the insulation circular layer  361 . Within the second metal layer  34 , the central insulation material  36  is disposed. Thus, the conductive via is comprised of the outer insulation circular layer  361 , the second seed layer  32 , the second metal layer  34  and the central insulation material  36  formed in a concentric, annular design. 
     In this embodiment, the die  2  is disposed adjacent to and electrically connected to the inactive surface  112  of the substrate  11 , and signals from the die  2  are transmitted to the circuit layer  13  on the active surface  111  of the substrate  11  through the interconnection metals  35 . That is, the bonding wires  21  are also disposed adjacent to the inactive surface  112  of the substrate  11 , thereby preventing the circuit layer  13  on the active surface  111  of the substrate  11  from being damaged during the wire bonding process and the die attaching process. In addition, as is well known, bonding wire is pressed to a bonding pad and ultrasonic friction therebetween is applied to finish the wire bonding process. The thickness of the second pads  14   b  is about 0.3 um˜1 um and the thickness of the redistribution layer  48  is about 2 um˜5 um. However, the thickness of the second pads  14   b  is less than that of the redistribution layer  48  or the surface finish layer  52 . Thus, if the wire bonding process is performed on the second pads  14   b  of the active surface  111  of the substrate  11 , the second pads  14   b  are easily damaged. 
     In this embodiment, the second integrated passive device (IPD)  29  are disposed adjacent to the active surface  202  of the die  2 , and the first integrated passive device (IPD)  15  is adjacent to the active surface  111  of the substrate  11 . Further, the inactive surface  203  of the die  2  is adhered on the second protection layer  50 , and is adjacent to the inactive surface  112  of the substrate  11 . Thus, the inactive surface  203  of the die  2  and the inactive surface  112  of the substrate  11  are disposed between the active surface  202  of the die  2  and the active surface  111  of the substrate  11 . Therefore, the distance between the second integrated passive device (IPD)  29  and the first integrated passive device (IPD)  15  is relatively large, which results in high frequency Q-factor. 
     Referring to  FIG. 2(   b ), a partially enlarged cross-sectional view of a semiconductor device  1   a , according to another embodiment of the present invention, is illustrated. The semiconductor device  1   a  of this embodiment is substantially similar to the semiconductor device  1  of  FIG. 1 , and the same elements are designated with the same reference numerals. The difference between the semiconductor device  1   a  of this embodiment and the semiconductor device  1  of  FIG. 1  is that the first end  37  protrudes from the inactive surface  112  of the substrate  11 . In this case, the insulation circular layer  361  is substantially coplanar with the inactive surface  112  but the interconnection metals  35  and central insulation material  36  protrude from the inactive surface  112 . In this embodiment, the redistribution layer  48  is disposed on lateral and end surfaces of the first end  37  of the conductive via, as shown, to provide enhanced electrical contact with the interconnection metals  35  and provide more secure attachment with the first end  37 . 
     Referring to  FIG. 3 , a cross-sectional view of a semiconductor device according to another embodiment of the present invention is illustrated. The semiconductor device  1   b  of this embodiment is substantially similar to the semiconductor device  1  of  FIG. 1 , and the same elements are designated with the same reference numerals. The difference between the semiconductor device  1   b  of this embodiment and the semiconductor device  1  of  FIG. 1  is described as follows. In this embodiment, the bonding type of the bonding wires  21  is a forward bond. The first step of the forward bond is bonding the wire  21  to the pad  204  of the die  2 . Then, the wire  21  is cut off after it is drawn to contact the surface finish  52 . 
     Referring to  FIGS. 4 to 19 , a semiconductor process for manufacturing a semiconductor device according to an embodiment of the present invention is illustrated. 
     Referring to  FIG. 4 , a wafer  10  is provided. The wafer  10  has a substrate  11 , a first dielectric layer  12  and a circuit layer  13 . In general, the first dielectric layer  12  and the circuit layer  13  would already be disposed on the substrate  11  after the foundry&#39;s process. The substrate  11  has an active surface  111  and a inactive surface  112 . In this embodiment, the material of the substrate  11  is a semiconductor material such as silicon or germanium. However, in other embodiments, the material of the substrate  11  may be glass. The first dielectric layer  12  is disposed on the active surface  111  of the substrate  11 . In this embodiment, the material of the first dielectric layer  12  is silicon oxide or silicon nitride. However, in other embodiments, the first dielectric layer  12  may include a polymer, such as polyimide (PI) or polypropylene (PP). 
     The circuit layer  13  is disposed adjacent to the active surface  111  of the substrate  11 . In this embodiment, the circuit layer  13  is disposed on the first dielectric layer  12 , and includes a plurality of first pads  14   a , a plurality of second pads  14   b  and a first protection layer  16 . The first pads  14   a  and the second pads  14   b  are parts of one of the metal layers (not shown) of the circuit layer  13 . In this embodiment, the material of the metal layers is copper. The first protection layer  16  covers the first pads  14   a  and has a plurality of openings  161  to expose the second pads  14   b . In this embodiment, the first protection layer  16  includes a polymer such as polyimide (PI) or polypropylene (PP). However, in other embodiments, the material of the first protection layer  16  can be silicon oxide or silicon nitride. It is to be noted that if only the substrate  11  is provided at this initial step, then the process further comprises the steps of forming the first dielectric layer  12  and the circuit layer  13 . 
     In this embodiment, the circuit layer  13  further includes at least one first integrated passive device (IPD)  15  disposed on the first dielectric layer  12  and covered by the first protection layer  16 . Therefore, the first integrated passive device (IPD)  15  is adjacent to the active surface  111  of the substrate  11 . In this embodiment, the first integrated passive device (IPD)  15  is an inducer, however, the first integrated passive device (IPD)  15  may be a capacitor, a resistor, or a combination of a inducer, a capacitor and a resistor. 
     Referring to  FIG. 5 , a first seed layer  18  is formed on the first protection layer  16  and its openings  161 . The first seed layer  18  contacts the second pads  14   b  in the openings  161 . Then, a photoresist layer  20  is formed on the first seed layer  18 , and has a plurality of openings  201  to expose a part of the first seed layer  18 . The material of first seed layer  18  is tantalum nitride. Then, a first metal layer  22  is formed in the openings  201  of the photoresist layer  20 . The first metal layer  22  is a single layer or multi-layer structure and the material of the first metal layer  22  is a mixture of nickel (Ni), palladium (Pd) and gold (Au); nickel (Ni) and gold (Au); or nickel (Ni) and palladium (Pd). 
     Referring to  FIG. 6 , the photoresist layer  20  is removed. Then, the first seed layer  18  that is not covered by the first metal layer  22  is removed so as to form a plurality of under bump metallurgies (UBM)  24 . 
     Referring to  FIG. 7 , the wafer  10  is attached to a carrier  26  by using an adhesive layer  28 , wherein the under bump metallurgies (UBM)  24  face the carrier  26 . 
     Referring to  FIG. 8 , a photoresist layer  30  is formed on the inactive surface  112  of the substrate  11 , and has a plurality of openings  301  to expose a part of the inactive surface  112  by etching process, such as wet etching or dry etching. Then, a plurality of cylindrical cavities  113  are formed from the inactive surface  112  of the substrate  11  corresponding to the openings  301  of the photoresist layer  30 . The cylindrical cavities  113  extend through the substrate  11  and the first dielectric layer  12 , so that the first dielectric layer  12  has a plurality of openings  121 . That is, each of the openings  121  is a part of each of the cylindrical cavities  113 , and penetrates through the first dielectric layer  12 . It is to be noted that the positions of the cylindrical cavities  113  must correspond to that of the first pads  14   a , so that the first pads  14   a  are exposed by the cylindrical cavities  113 . 
     Referring to  FIG. 9 , a plurality of interconnection metals  35  are formed in the cylindrical cavities  113  to electrically connect the circuit layer  13 . In this embodiment, a second seed layer  32  is formed in the cylindrical cavities  113  and contacts the first pads  14   a . Then, a second metal layer  34  is formed on the second seed layer  32 . The material of the second seed layer  32  is tantalum nitride or tantalum tungsten, and the material of the second metal layer  34  is copper. The second seed layer  32  and the second metal layer  34  forms the interconnection metal  35 . However, the second seed layer  32  may be omitted, that is, the second metal layer  34  at this position is the interconnection metal  35 . In this embodiment, the interconnection metal  35  defines an interior portion  351 . 
     Referring to  FIG. 10 , a central insulation material  36  is filled in the interior portion  351 . In other embodiments, the second metal layer  34  in  FIG. 7  may fill up the cylindrical cavity  113 , that is, the interconnection metal  35  may be a solid pillar, and the central insulation material  36  can be omitted. 
     Referring to  FIG. 11 , a photoresist layer  38  is formed on the inactive surface  112  of the substrate  11 , and has a plurality of openings  381  to expose the interconnection metals  35 . Then, a plurality of circular grooves  114  are formed from the inactive surface  112  of the substrate  11  according to the openings  381 , wherein the circular grooves  114  surround the interconnection metals  35 . In this embodiment, the circular grooves  114  only extend through the substrate  11  to form a plurality of through holes  115 . 
     Referring to  FIG. 12 , an insulation circular layer  361  is formed in the circular grooves  114  to surround the interconnection metals  35 . In this embodiment, the material of the central insulation material  36  is a polymer, which is the same as that of the insulation circular layer  361 . In this embodiment, the insulation circular layer  361  does not extend into the first dielectric layer  12 ; therefore, the bottom surface of the interconnection metal  35  is not coplanar with the bottom surface of the insulation circular layer  361 . 
     Referring to  FIG. 13 , a second dielectric layer  40  is formed on the inactive surface  112  of the substrate  11 , and has a plurality of openings  401  to expose the interconnection metals  35 . In this embodiment, the second dielectric layer  40  includes a polymer such as polyimide (PI) or polypropylene (PP). However, in other embodiments, the material of the second dielectric layer  40  can be silicon oxide or silicon nitride. Then, a third seed layer  42  is formed on the second dielectric layer  40  and its openings  401  to contact the interconnection metals  35  in the openings  401 . The material of the third seed layer  42  is tantalum nitride or tantalum tungsten. 
     Referring to  FIG. 14 , a photoresist layer  44  is formed on the third seed layer  42 , and has a plurality of openings  441  to expose a part of the third seed layer  42 . Then, a third metal layer  46  is formed in the openings  441  of the photoresist layer  44 . The material of the third metal layer  46  is copper. 
     Referring to  FIG. 15 , the photoresist layer  44  is removed. Then, the third seed layer  42  that is not covered by the third metal layer  46  is removed so as to form a redistribution layer  48 . However, the third seed layer  42  may be omitted, that is, third metal layer  46  at this position is the redistribution layer  48 . 
     Referring to  FIG. 16 , a second protection layer  50  is formed on the second dielectric layer  40  and the redistribution layer  48 , and has a plurality of openings  501  to expose a part of the redistribution layer  48 . The material of the second protection layer  50  may be the same as that of the second dielectric layer  40 . Then, a surface finish layer  52  is plated on the exposed part of the redistribution layer  48 . 
     Referring to  FIG. 17 , a die  2  is attached adjacent to the inactive surface  112  of the substrate  11 , and electrically connected to the under bump metallurgies (UBMs)  24 . In this embodiment, the die  2  has an active surface  202 , a inactive surface  203 , a plurality of pads  204 , and at least one second integrated passive device (IPD)  29 . The pads  204  and the second integrated passive device (IPD)  29  are disposed adjacent to the active surface  202  of the die  2 . In this embodiment, the second integrated passive device (IPD)  29  is an inducer, however, the second integrated passive device (IPD)  29  may be a capacitor, a resistor, or a combination of a inducer, a capacitor and a resistor. The inactive surface  203  of the die  2  is adhered on the second protection layer  50 . The pads  204  are electrically connected to the surface finish layer  52  on the exposed part of the redistribution layer  48  through the bonding wires  21 . That is, the bonding wires  21  connect the die  2  and the redistribution layer  48 . In this embodiment, the bonding type of the bonding wires  21  is a reverse bond. The first step of the reverse bond is forming a wire ball  211  on the pad  204  of the die  2 . Then, on the tip of the wire  21  another wire ball is formed and is bonded on the surface finish  52 . Finally, the wire  21  is cut off after it is drawn to contact the wire ball  211 . 
     In this embodiment, the die  2  and the bonding wires  21  are disposed adjacent to the inactive surface  112  of the substrate  11 , thereby preventing the circuit layer  13  on the active surface  111  of the substrate  11  from being damaged during the wire bonding process and the die attaching process. As is well known, bonding wire is pressed to a bonding pad and ultrasonic friction applied to finish wire bonding. However, the thickness of the second pads  14   b  is less than that of the redistribution layer  48  or the surface finish layer  52 , so that if the wire bonding process were to be performed on the second pads  14   b  of the active surface  111  of the substrate  11 , the second pads  14   b  would be easily damaged. Next, the molding compound  3  is formed adjacent to the inactive surface  112  of the substrate  11  to encapsulate the die  2  and the bonding wires  21 . In this embodiment, the molding compound  3  is disposed on the second protection layer  50 . 
     Referring to  FIG. 18 , the carrier  26  and the adhesive layer  28  are removed. 
     Referring to  FIG. 19 , a plurality of solder balls  54  are formed on the under bump metallurgies (UBM)  24 . Then, the wafer  10  is cut to form the plurality of semiconductor devices  1 , as shown in  FIG. 1 . 
     As is well known, bonding and de-bonding are high risk processes for a thin wafer. Therefore, if a thin wafer undergoes repeated bonding and de-bonding processes, the possibility of cracking or breaking is relative high. In this embodiment, only one carrier  26  is used in the process, and the wafer  10  is bonded to the carrier  26  and de-bonded from the carrier  26  only once so as to prevent the wafer  10  from cracking or breaking. That is, this embodiment has only one de-bonding step, and the molding compound  3  has already formed on the wafer  10  before the de-bonding step, thus, the wafer  10  is strengthened and not easily damaged during the de-bonding step. Thus, the yield is greatly raised. In addition, the semiconductor process of this embodiment is simplified, so that the manufacturing cost is reduced. 
     Referring to  FIGS. 20 to 23 , a semiconductor process for manufacturing a semiconductor device according to another embodiment of the present invention is illustrated. The initial steps of the semiconductor process of this embodiment are the same as the steps of  FIGS. 1 to 7 . 
     Referring to  FIG. 20 , a photoresist layer  56  is formed on the inactive surface  112  of the substrate  11 , and has a plurality of ring openings  561  to expose the inactive surface  112  of the substrate  11  by etching process, such as wet-etching or dry-etching. Then, a plurality of circular grooves  114  are formed from the inactive surface  112  of the substrate  11  according to the ring openings  561 , wherein each of the circular grooves  114  surrounds a central portion  116  which is a part of the substrate  11 . In this embodiment, the circular grooves  114  only extend through the substrate  11  to form a plurality of through holes  115 . 
     Referring to  FIG. 21 , an insulation circular layer  361  is formed in the circular grooves  114  to surround the central portion  116 . 
     Referring to  FIG. 22 , the central portions  116  are removed to form a plurality of cylindrical cavities  113 . The cylindrical cavities  113  extend through the substrate  11  and the first dielectric layer  12 , so that the first dielectric layer  12  has a plurality of openings  121 . That is, each of the openings  121  is a part of each of the cylindrical cavities  113 , and penetrates through the first dielectric layer  12 . It is to be noted that the positions of the cylindrical cavities  113  must correspond to that of the first pads  14   a , so that the first pads  14   a  are exposed by the cylindrical cavities  113 . 
     Referring to  FIG. 23 , a plurality of interconnection metals  35  are formed in the cylindrical cavities  113  to electrically connect the circuit layer  13 . In this embodiment, a second seed layer  32  is formed in the cylindrical cavities  113  and contacts the first pads  14   a . Then, a second metal layer  34  is formed on the second seed layer  32 . The material of the second seed layer  32  is tantalum nitride or tantalum tungsten, and the material of the second metal layer  34  is copper. The second seed layer  32  and the second metal layer  34  forms the interconnection metal  35 . However, the second seed layer  32  may be omitted, that is, the second metal layer  34  at this position is the interconnection metal  35 . In this embodiment, the interconnection metal  35  defines an interior portion  351 . Then, a central insulation material  36  is filled in the interior portion  351 , as shown in  FIG. 12 . In other embodiments, the second metal layer  34  in  FIG. 23  may fill up the cylindrical cavity  113 , that is, the interconnection metal  35  may be a solid pillar, and the central insulation material  36  can be omitted. The subsequent steps of this embodiment are the same as the steps of  FIGS. 12 to 19 . 
     While the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present invention which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the invention.