Abstract:
A data I/O circuit of a semiconductor memory device employing clock synthesizing means for inputting synthesized clock signals of clock signals of two nodes of a metal line transmitting the clock signals to the corresponding data buffer in order to decrease a time difference of the clock signals for driving the plurality of data buffers. As a result, the data I/O circuit of a semiconductor memory device performs an operation of the semiconductor memory device at a high speed by reducing a data setup/hold time, by equalizing an enable time of a plurality of data buffers.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a data I/O (input/output) circuit for a semiconductor memory device, and in particular to an improved data I/O circuit for a semiconductor memory device which can perform operations at a high speed by means of a method of reducing data setup/hold time by equalizing the enable time of a plurality of data buffers.  
           [0003]    2. Description of the Background Art  
           [0004]    [0004]FIG. 1 is a block diagram illustrating a conventional data I/O circuit of a semiconductor memory device.  
           [0005]    The conventional data I/O circuit includes: a clock synchronization unit  1  for synchronizing an internal clock signal ICLK with an external clock signal ECLK by using a delay locked loop DLL or a phase locked loop PLL; a clock driving unit  2  for transferring the internal clock signal ICLK to a clock signal transmission line (metal line) CL; a memory block  3  for storing data; a plurality of data buffers DBUF 0 -DBUF 15  for buffering the data according to the internal clock signal ICLK; and a plurality of data pads DQ 0 -DQ 15  for outputting the data from the data buffers DBUF 0 -DBUF 15  or externally receiving data.  
           [0006]    The operation of the conventional data I/O circuit is described with reference to a timing diagram of FIG. 2.  
           [0007]    Initially, the clock synchronization unit  1  synchronizes the internal clock signal ICLK with the external clock signal ECLK.  
           [0008]    The internal clock signal ICLK is transmitted to the data buffers DBUF 0 -DBUF 15  through the clock signal transmission line CL made of metal. Here, the clock driving unit  2  is employed to drive the internal clock signal ICLK in order to prevent delay of the internal clock signal ICLK.  
           [0009]    As illustrated in FIG. 2, the internal clock signals C 7 , C 8  inputted to the data buffers DBUF 7  and DBUF 8  closest to the clock driving unit  2  are delayed as long as the internal clock signal ICLK. However, the internal clock signals C 0  and C 15  inputted to the data buffers DBUF 0  and DBUF 15  farthest from the clock driving unit  2  are delayed longer than the internal clock signal ICLK by a delay time DT.  
           [0010]    Accordingly, there is a time difference DT between the data output timing of the data buffers DBUF 7  and DBUF 8  closest to the clock driving unit  2  and a data output timing of the data buffers DBUF 0  and DBUF 15  farthest from the clock driving unit  2 , thereby generating a data error.  
           [0011]    The data setup/hold time should be increased to prevent the data error. However, the increased data setup/hold time decreases operation speed of the semiconductor memory device.  
         SUMMARY OF THE INVENTION  
         [0012]    Accordingly, it is an object of the present invention to provide a data I/O circuit of a semiconductor memory device which can perform operations at a high speed by means of a method of outputting clock signals having an identical timing to a plurality of data buffers, by connecting a clock synthesizing means to a clock signal transmission line.  
           [0013]    In order to achieve the above-described object of the invention, there is provided a data I/O circuit of a semiconductor memory device, including: a memory means for storing data; a clock synchronization means for synchronizing an internal clock signal with an external clock signal; a clock driving means for driving the internal clock signal; a clock signal transmission line wherein the internal clock signal is transmitted; a plurality of clock synthesizing means for synthesizing clock signals of corresponding nodes of the clock signal transmission line; a plurality of data buffers for buffering data according to the clock signals from the plurality of clock synthesizing means; and a plurality of data pads for externally outputting the data from the plurality of data buffers, or externally receiving data. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein:  
         [0015]    [0015]FIG. 1 is a block diagram illustrating a conventional data I/O circuit of a semiconductor memory device;  
         [0016]    [0016]FIG. 2 is a timing diagram showing delay of clock signals for the data I/O circuit in FIG. 1;  
         [0017]    [0017]FIG. 3 is a block diagram illustrating a data I/O circuit of a semiconductor memory device in accordance with a first embodiment of the present invention;  
         [0018]    [0018]FIG. 4 is a detailed circuit diagram illustrating a clock synthesizing unit of FIG. 3;  
         [0019]    [0019]FIG. 5 is a timing diagram showing delay of clock signals for the data I/O circuit in FIG. 3; and  
         [0020]    [0020]FIG. 6 is a block diagram illustrating a data I/O circuit of a semiconductor memory device in accordance with a second embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]    A data I/O circuit of a semiconductor memory device in accordance with preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.  
         [0022]    [0022]FIG. 3 is a block diagram illustrating a data I/O circuit of a semiconductor memory device in accordance with a first embodiment of the present invention.  
         [0023]    The data I/O circuit includes: a clock synchronization unit  10  for synchronizing an internal clock signal ICLK with an external clock signal ECLK; a clock driving unit  20  for transferring the internal clock signal ICLK to a clock signal transmission line CL; a plurality of clock synthesizing units  100 - 115  for synthesizing the internal clock signals of corresponding nodes N 11 -N 18 , N 21 -N 28 , N 31 -N 38  and N 41 -N 48  in the clock signal transmission line CL and outputting clock signals C 100 - 115 ; a plurality of data buffers DBUF 10 -DBUF 115  for buffering data according to the synthesized clock signals C 100 -C 115 ; and a plurality of data pads DQ 100 -DQ 115  for externally outputting the data from the plurality of data buffers DBUF 100 -DBUF 115 , or receiving data from external devices.  
         [0024]    At this time, the clock signal transmission line CL is connected at a node NO to the clock driving unit  20  and at nodes N 11 ˜N 18 , N 21 ˜N 28 , N 31 ˜N 38 , and N 41 ˜N 48  to the plurality of clock synthesizing units  100 ˜ 115  to a node NO to which the clock driving unit  20  is connected.  
         [0025]    The clock synchronization unit  10  consists of a delay locked loop or a phase locked loop.  
         [0026]    [0026]FIG. 4 is a detailed circuit diagram illustrating the clock synthesizing unit  100 .  
         [0027]    As illustrated in FIG. 4, the clock synthesizing unit  100  includes: inverters INV 1  and INV 2  for respectively driving the clock signals of the corresponding nodes N 18  and N 28 ; and an inverter INV 3  for synthesizing and driving phases of the output signals from the inverters INV 1  and INV 2 .  
         [0028]    The operation of the data I/O circuit of the semiconductor memory device in accordance with the first embodiment of the present invention will now be described with reference to FIG. 5.  
         [0029]    The clock synchronization unit  10  synchronizes the internal clock signal ICLK with the external clock signal ECLK.  
         [0030]    The internal clock signal ICLK driven by the clock driving unit  20  is transmitted to the data buffers DBUF 100 -DBUF 115  through the clock signal transmission line CL. The clock signal transmission line CL is connected to the plurality of clock synthesizing units  100 ˜ 115 .  
         [0031]    The clock synthesizing units  100 - 115  receive the internal clock signals of the corresponding nodes and synthesize phases of the internal clock signals. The clock synthesizing units  100 ˜ 115  output the synthesized clock signals to the data buffers DBUF 100 -DBUF 115 .  
         [0032]    That is, the clock signals N 18  and N 28  shown in FIG. 5 are inputted to the inverters INV 1  and INV 2  of the clock synthesizing unit  100  shown in FIG. 4. The clock signals N 18  and N 28  are driven in the inverters INV 1  and INV 2 , and inputted to the inverter INV 3 . Referring to FIG. 5, the clock synthesizing unit  100  generates a clock signal C 100  having an intermediate value of time differences of the inputted clock signals.  
         [0033]    In the same manner, the clock synthesizing unit  107  generates a clock signal C 107  having an intermediate value of time differences of the clock signals of the corresponding nodes N 11  and N 21 .  
         [0034]    In addition, the other clock synthesizing units  101 - 106  and  108 - 115  respectively generate clock signals having intermediate values of time differences of the clock signals of the corresponding nodes.  
         [0035]    Accordingly, all the data buffers DBUF 100 -DBUF 115  have an identical data output time.  
         [0036]    At this time, the clock signal transmission line CL is symmetrically connected from the clock driving unit  20 . Both parts of the clock signal transmission line CL consist of an identical metal line and have an identical length in the same conditions. Therefore, the data buffers DBUF 100 -DBUF 107  and the data buffers DBUF 108 -DBUF 115  which are symmetrically aligned have the same data output time.  
         [0037]    [0037]FIG. 6 is a block diagram illustrating a data I/O circuit of a semiconductor memory device in accordance with a second embodiment of the present invention.  
         [0038]    As shown in FIG. 6, the data I/O circuit of the semiconductor memory device includes a clock synchronization unit  11 , a main clock driving unit  21 , a plurality of sub clock driving units  22  and  23 , a plurality of clock synthesizing units  200 ˜ 215 , a plurality of data buffers DBUF  200 ˜DBUF 215  and a plurality of data pads DQ 200 ˜DQ 215 . The clock synchronization unit  11  synchronizes an internal clock signal ICLK with an external clock signal ECLK. The main clock driving unit  21  transfers the internal clock signal ICLK to a main clock signal transmission line MCL. The plurality of sub clock driving units  22  and  23  drive the internal clock signals transmitted to the main clock signal transmission line MCL and re-transferring the driven clock signals to a sub clock signal transmission line. The plurality of clock synthesizing units  200 ˜ 215  synthesizes clock signals of corresponding nodes in the sub clock signal transmission line. The plurality of data buffers DBUF 200 ˜DBUF 215  buffer data according to the clock signals C 200 ˜C 215  from the plurality of clock synthesizing units  200 ˜ 215 . The plurality of data pads DQ 200 ˜DQ 215  externally output the data from the plurality of data buffers DBUF 200 ˜DBUF 215 , or externally receiving data.  
         [0039]    The data buffers DBUF 200 -DBUF 207  and the data buffers DBUF 208 -DBUF 215  are symmetrically aligned with respect to the clock driving unit  21 . The sub clock driving units  22  and  23  are aligned at the center portions of the data buffers DBUF 200 -DBUF 207  and the data buffers DBUF 208 -DBUF 215 , for transmitting the internal clock signal ICLK driven by the main clock driving unit  21  to the sub clock signal transmission lines SCL 1  and SCL 2 .  
         [0040]    The operation of the data I/O circuit of the semiconductor memory device in accordance with the second embodiment of the present invention will now be described.  
         [0041]    The clock synchronization unit  11  synchronizes the external clock signal ECLK, thereby outputting the internal clock signal ICLK.  
         [0042]    The main clock driving unit  21  drives the internal clock signal ICLK, and transmits the driven internal clock signal ICLK to the main clock signal transmission line MCL.  
         [0043]    The sub clock driving units  22  and  23  drive the clock signals transmitted to the main clock signal transmission line MCL, and transmit the driven clock signals to the sub clock signal transmission lines SCL 1  and SCL 2 , respectively. Here, the sub clock signal transmission line SCL 1  is connected to both ends of the data buffers DBUF 200 -DBUF 207 , and extended to the node N 1  to which the sub clock driving unit  22  is connected. In the same manner, the sub clock signal transmission line SCL 2  is connected to both ends of the data buffers DBUF 208 -DBUF 215 , and extended to the node N 2  to which the sub clock driving unit  23  is connected.  
         [0044]    The clock synthesizing units  200 - 215  receive the clock signals of the corresponding nodes N 101 -N 174  of the sub clock signal transmission lines SCL 1  and SCL 2 , synthesize the phases of the clock signals, and output the resultant clock signals to the data buffers DBUF 200 -DBUF 215 , respectively.  
         [0045]    Accordingly, the phases of the clock signals C 200 -C 215  synthesized by the clock synthesizing units  200 - 215  are equalized, and thus the clock signals C 200 -C 215  do not have a time difference.  
         [0046]    The succeeding operations of the second embodiment are identical to the above-described operations of the first embodiment, and therefore detailed explanations thereof are omitted.  
         [0047]    As discussed earlier, in accordance with the present invention, the clock synthesizing units equalize the phases of the clock signals so as to reduce the time difference of the clock signals generated in the clock signal transmission line according to position of the data buffers. Therefore, the data buffers have an identical enable time, thereby decreasing the data setup/hold time. As a result, it is possible to operate the semiconductor memory device at a high speed.  
         [0048]    As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.