Abstract:
A programmable metal-oxide-semiconductor (MOS) memory circuit and the method for programming same and disclosed. The circuit comprises a first N-type transistor having a gate region tied with a drain region and connectable to a first control voltage level, and a source region connected to a second voltage level; and a second N-type transistor having a gate region tied with a drain region and connectable to the first control voltage level, and a source region connected to the second voltage level, wherein the first and second control voltage levels are imposed to program either the first or second N-type transistor by causing a voltage difference between the drain region and the source region (Vds) and voltage difference between the gate region and the source region (Vgs) to be bigger than a predetermined threshold voltage to induce a hot carrier effect.

Description:
BACKGROUND OF THE DISCLOSURE 
   The present invention relates generally to the field of semiconductor devices, and more particularly to memory devices. Still more particularly, the invention relates to methods for programming semiconductor memory devices by stressing metal oxide semiconductor field effect transistors (MOSFETs) devices to cause hot carrier effect. 
   Typically, a MOSFET device may be fabricated upon a semiconductor substrate by forming a gate oxide, on top of which a gate electrode resides, and a pair of source/drain electrodes which adjoin the gate oxide and the gate electrode. The method by which a MOSFET device may be fabricated may vary from time to time, as understood by those skilled in the art. 
   Hot carrier effect is a phenomenon resulting from the injection of charge carriers into gate dielectric layers typically formed of silicon oxide formed beneath gate electrode edges within MOSFET devices. Along with other characteristics, the hot carrier effect within a MOSFET device is manifested by transistor parameters such as sub-threshold current and threshold voltage. In particular, when a MOSFET device is stressed under hot carrier effect, sub-threshold current typically increases while threshold voltage drifts. These drifts in device parameters are caused by the injection of charge carriers from the semiconductor substrate, on top of which a MOSFET device is formed, into the gate oxide of the MOSFET device. Depending on the design parameters of the MOSFET device, the injected charge carriers may generate more interface states within the gate oxide or they may be trapped by mid-gap states of the gate oxide. 
   Typically, many factors can affect the extent to which hot carrier effect is exhibited in MOSFET devices. These factors include but are not limited to the polarity of the MOSFET device, the hardness of the interface to the injected charge carriers, the trap density within the gate oxide and the potential barrier to charge carrier injection provided by the semiconductor substrate/gate oxide interface. Hot carrier effect can also be enhanced in MOSFET devices where gate dielectric layer thickness as well as channel widths are reduced while operating voltage is maintained. The reduction in gate dielectric layer thickness and channel widths within MOSFET devices at constant operating voltage typically provides an increase in electric field gradients at gate electrode edges within the devices. This increase in electric field gradients allow more charge carriers to be injected into and trapped in the semiconductor substrate and the gate oxide regions beneath gate electrode edges, or the gate dielectric layers. 
   When charge carriers are fully injected into and trapped in the semiconductor substrate and gate dielectric layers of the MOSFET device, the device is said to be stressed. In a condition wherein hot carrier effect is enhanced and amplified by adjusting the factors mentioned hitherto, electric charge builds up to a point where the semiconductor substrate and gate dielectric layers in the MOSFET device become stressed. As the MOSFET device becomes more stressed, the conductance of the device reduces, thereby exhibiting higher resistance. This resistance remains high until the electrons trapped in the semiconductor substrate and gate dielectric layers in the MOSFET device are removed. 
   Desirable in the art of semiconductor memory design are additional methods and materials through which one-time programming of non-volatile data can be achieved. 
   SUMMARY OF THE DISCLOSURE 
   In view of the foregoing, this disclosure provides a programmable metal-oxide-semiconductor (MOS) memory circuit and the method for programming the same. 
   In one example, the circuit comprises a first N-type transistor having a gate region tied with a drain region and connectable to a first control voltage level, and a source region connected to a second voltage level; and a second N-type transistor having a gate region tied with a drain region and connectable to the first control voltage level, and a source region connected to the second voltage level, wherein the first and second control voltage levels are imposed to program either the first or second N-type transistor by causing a voltage difference between the drain region and the source region (Vds) and voltage difference between the gate region and the source region (Vgs) to be bigger than a predetermined threshold voltage to induce a hot carrier effect. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a memory device in accordance with one example of the present disclosure. 
       FIG. 2A  illustrates a timing diagram showing the voltage at two nodes during a write operation in accordance with a first example of the present disclosure. 
       FIG. 2B  illustrates a timing diagram showing the voltage at various nodes during a read operation in accordance with the first example of the present disclosure. 
       FIG. 3A  illustrates a timing diagram showing the voltage at two nodes during a write operation in accordance with a second example of the present disclosure. 
       FIG. 3B  illustrates a timing diagram showing the voltage at various nodes during a read operation in accordance with the second example of the present disclosure. 
   

   DETAILED DESCRIPTION 
   In the present disclosure, a memory device using hot carrier effect to program two N-type metal-oxide-semiconductor (MOS) devices is disclosed.  FIG. 1  shows a memory device  100  that can be programmed by utilizing the hot carrier effect. The device  100  includes a latch  102 , two thick gate oxide P-type devices PM 0  and PM 1  that perform write operations, two thick gate oxide N-type devices NM 0  and NM 1  that perform read operations, and two one-time programmable thin gate oxide N-type devices NM 2  and NM 3 . The latch  102  includes four transistors, two P-type devices PM 2  and PM 3 , and two N-type devices NM 4  and NM 5 . Thick gate devices are used in this memory device because the devices have to withstand a voltage typically higher than a regular operating voltage in order to successfully inject enough carrier charges into the two thin gate oxide devices NM 2  and NM 3  to achieve the hot carrier effect. If PM 0  and PM 1  break down before enough carrier charges are injected to NM 2  and NM 3 , programming cannot be performed. The gate oxide devices have shorter channel than the thick gate oxide devices with a high electric field when stressed by the hot carrier effect. 
   The sources of PM 0  and PM 1  are connected to a high operating voltage VDDH, which is typically higher than a regular operating voltage, for the reason previously described. For example, VDDH is 3.3V and the threshold voltage to achieve hot carrier effect is 1.2V, while regular operating voltage is less than 1V. The drains of PM 0  and PM 1  are connected to both the gates and drains of NM 2  and NM 3 , respectively, and further connected to the sources of NM 0  and NM 1 , respectively. For illustration purposes, control voltage levels/references at the drains of PM 0  and PM 1  are referred to as V 0  and V 1 , respectively. Similarly, the two nodes VW 0  and VW 1  represent the gates of PM 0  and PM 1 , respectively, for programming the memory device. 
   The sources of NM 2  and NM 3  are connected to a control voltage level such as VSS which, depending on circuit setup, may or may not be directly connected to ground. The gates of NM 0  and NM 1  are connected together, the connection of which has a voltage reference VR. The drain of NM 0  connects to the gates of PM 2  and NM 4 , while the drain of NM 1  connects to the gates of PM 3  and NM 5 . NM 0  and NM 1  can be together viewed as a connection module which passes V 0  and V 1  as two inputs to the latch  102  when VR is set at an appropriate level. The sources of PM 2  and PM 3  are connected to an operating voltage VDDL, while the drains of PM 2  and PM 3  are connected to the drains of NM 4  and NM 5 , respectively. The sources of NM 4  and NM 5  are connected to VSS. The gates of PM 2  and NM 4  are connected to the drains of PM 3  and the drain of NM 5 , whereupon this connection has an output voltage reference OUT. The gates of PM 3  and NM 5  are connected to the drain of PM 2  and the drain of NM 4 , whereupon this connection has an output voltage reference OUTz. 
   For illustration purposes, in a first example, the memory device  100  will be programmed with a “ 1 .”  FIG. 2A  illustrates a timing diagram showing the voltage at various nodes in  FIG. 1  during an operation to program the memory device with a “ 1 .” With reference to both  FIGS. 1 and 2A , when the circuit is powered up, both VW 0  and VW 1  are at VDDH whereas VR is at VSS. When a write operation occurs, VW 0  is temporarily switched to  0  from VDDH, thereby allowing PM 0  to conduct while VW 1  stays at VDDH. The switch at VW 0  is represented by a falling edge  202 . V 0  is then built up to VDDH, as represented by a rising edge  204 , thereby building up carrier charges in NM 2  until there is a high electric field between the drain and source of NM 2 . When a voltage difference between the drain region and the source region (Vds) and a voltage difference between the gate region and the source region (Vgs) is bigger than a predetermined threshold voltage, the hot carrier effect is caused. Due to hot carrier effect, the current (Ids) going through NM 2  becomes lower relative to that going through NM 3 . NM 2  will now have a low conductance and a high resistance, and is considered “programmed”. When VW 0  is switched back to VDDH, as represented by a rising edge  206 , PM 0  ceases to conduct. Throughout this period, since VW 1  remains at VDDH, PM 1  does not conduct and therefore no hot carrier charges are built up in NM 3 . As such, the thin gate oxide devices function as one-time programmable fuses due to the hot carrier effect. 
     FIG. 2B  illustrates a timing diagram showing the voltage at various nodes in  FIG. 1  during a read operation. With reference to both  FIGS. 1 and 2B , when a read operation occurs, VR rises, which is represented by a rising edge  208 . It is noted that before a reading operation occurs, both OUT and OUTz are still indeterminate. When VR rises enough, NM 0  and NM 1  conduct, thereby sending V 0  and V 1  to OUT and OUTz, respectively. In this example, OUT, which carries V 0 , is higher than OUTz, which carries V 1 . As such, OUT will move to as high a voltage as VDDL, as represented by a rising edge  212 , while OUTz stays at VSS. The data of the memory device can be obtained by reading OUT, which essentially carries the “ 1 ” that is originally programmed into NM 2 . Based on the function of the latch  102  in this configuration, it can be viewed as a comparison circuit which compares V 0  and V 1 , and produces an output on OUT node accordingly. 
   When the VR signal is turned off, both NM 0  and NM 1  stop conducting, thereby disconnecting OUT from V 0  and OUTz from V 1 . At this point, the latch  102  will force OUT to move to VDDL if it is higher than OUTz. Conversely, the latch  102  will force OUT to move to VSS if it is lower than OUTz. In this example, since the voltage potential at OUT is higher than the voltage potential at OUTz just prior to when the VR signal is turned off, the latch  102  will force OUT to VDDL and OUTz to VSS. 
   Since the latch  102  will always move OUT away from OUTz after a read operation, OUTz is essentially a negation of OUT after a read operation. It is also noted that before a read operation, the states of OUT and OUTz are indeterminate. Since the latch  102  will also hold the information of the memory device at OUT after a read operation is completed, the latch  102  in effect is a memory cell that either holds a “ 1 ” or “ 0 ” at OUT. 
   In a second example, the memory device will be programmed with a “ 0 .”  FIG. 3A  illustrates a timing diagram showing the voltage at various nodes in  FIG. 1  during an operation to program the memory device with a “ 0 .” With reference to both  FIGS. 1 and 3A , when the circuit is powered up, both VW 0  and VW 1  are at VDDH, whereas VR is at VSS. When a write operation occurs, VW 1  is temporarily switched to  0  from VDDH, thereby allowing PM 1  to conduct while VW 0  stays at VDDH. The switch at VW 1  is represented by a falling edge  302 . V 1  is then built up to VDDH, as represented by a rising edge  304 , thereby building up carrier charges in NM 3  until there is a high electric field between the drain and source of NM 3 . Due to hot carrier effect, the current going through NM 3  becomes lower relative to that going through NM 2 . NM 3  will now have a low conductance and a high resistance, and is considered “programmed.” When VW 1  is switched back to VDDH, as represented by a rising edge  306 , PM 1  ceases to conduct. Throughout this period, since VW 0  remains at VDDH, PM 0  does not conduct and therefore no hot carrier charges are built up in NM 2 . 
     FIG. 3B  illustrates a timing diagram showing the voltage at various nodes in  FIG. 1  during a read operation in the second example. With reference to both  FIGS. 1 and 3B , when a read operation occurs, VR rises, which is represented by a rising edge  308 . It is noted that before a reading operation occurs, both OUT and OUTz are still indeterminate. When VR rises enough, NM 0  and NM 1  conduct, thereby sending V 0  and V 1  to OUT and OUTz, respectively. In this example, OUT, which carries V 0 , is lower than OUTz, which carries V 1 . As such, OUTz will move to as high a voltage as VDDL, as represented by a rising edge  314 , while OUT stays at VSS. The data of the memory device can be obtained by reading OUT, which as represented by a falling edge  316  essentially carries the “ 0 ” since V 0  is lower relative to V 1  because the resistance at NM 3  is higher relative to NM 2 . 
   When the VR signal is turned off, NM 0  and NM 1  stop conducting, thereby disconnecting OUT from V 0  and OUTz from V 1 . At this point, since the voltage potential at OUT is lower than the voltage potential at OUTz just prior to when the VR signal is turned off, the latch  102  will force OUTz to VDDL and OUT to VSS. 
   The above disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components, and processes are described to help clarify the disclosure. These are, of course, merely examples and are not intended to limit the disclosure from that described in the claims. 
   Although illustrative embodiments of the disclosure have been shown and described, other modifications, changes, and substitutions are intended in the foregoing disclosure. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the disclosure, as set forth in the following claims.