Abstract:
An integrated circuit package includes a first memory die having a first set of connections, a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate having a first opening and a second opening, the first substrate having a third set of connections to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect to the second set of connections of the second memory die via the second opening, and a second substrate having a first integrated circuit disposed thereon. The first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 61/526,586, filed on Aug. 23, 2011, and U.S. Provisional Application No. 61/548,344, filed on Oct. 18, 2011. 
     This application is related to U.S. application Ser. No. 12/565,430, filed on Sep. 23, 2009, which claims the benefit of U.S. Provisional Application Nos. 61/099,355, filed on Sep. 23, 2008 and 61/121,018, filed on Dec. 9, 2008. 
     The disclosures of the above applications are incorporated herein by reference in their entirety. 
    
    
     FIELD 
     The present disclosure relates generally to integrated circuits and more particularly to packaging dynamic random access memory (DRAM) and a system-on-chip (SOC) in a single integrated circuit (IC) package. 
     BACKGROUND 
     The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
     The dynamic random access memory (DRAM) industry has been trying to resolve issues related to high-performance DRAM that is used in high-end application processors such as smartphone or tablet processors. Today the industry is using low-power (LP) double-data-rate (DDR) DRAM such as LP-DDR2 and DDR3 DRAM. Throughout the present disclosure, the term DDR or DDRx, where x is an integer greater than or equal to 1, will be used to denote DDR DRAM or DDRx DRAM, respectively. The abbreviation DRAM will be omitted to improve readability. 
     The Joint Electron Devices Engineering Council (JEDEC) is presently discussing LP-DDR3 and DDR4 as well as ultra-wide I/O DRAM. Ultra-wide I/O DRAM is supposed to address bandwidth challenge but at the expense of requiring expensive through-silicon via (TSV) technology. In addition to the cost, for each generation of ultra-wide I/O DRAM, the customers would need to redesign the TSV and/or the system-on-chip (SOC) utilizing the ultra-wide I/O DRAM. 
     SUMMARY 
     An integrated circuit package comprises a first memory die having a first set of connections, a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate having a first opening and a second opening, the first substrate having a third set of connections to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect to the second set of connections of the second memory die via the second opening, and a second substrate having a first integrated circuit disposed thereon. The first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate. 
     In other features, the connections of each of the third set and the fourth set of connections are arranged in three rows at a pitch of less than or equal to 0.4 millimeters. 
     In other features, the first integrated circuit is a system-on-chip. The first and second memory dies are disposed on top of the first substrate. The first substrate is disposed on top of the second substrate. 
     In other features, the integrated circuit package further comprises a heat sink disposed on top of the first and second memory dies. 
     In other features, the third set of connections are connected to the first set of connections by bond wires, and the second set of connections are connected to the fourth set of connections by bond wires. 
     In other features, the integrated circuit package is configured to connect to connections on a printed circuit board or connections of a second integrated circuit. 
     In other features, the first and second memory dies are double-data-rate dynamic random access memories. 
     In other features, the integrated circuit package is incorporated into a computing device. The computing device includes a smartphone, a tablet, a laptop, a personal computer, a television, or a setup box. 
     In other features, the integrated circuit package further comprises a third memory die having a fifth set of connections, a fourth memory die arranged adjacent to the third memory die, the fourth memory die having a sixth set of connections, a third substrate having a third opening and a fourth opening, the third substrate having a seventh set of connections to connect to the fifth set of connections of the third memory die via the third opening and an eighth set of connections to connect to the sixth set of connections of the fourth memory die via the fourth opening. 
     In other features, the third substrate is disposed on top of the first substrate, and the first and second memory dies are disposed between the first and third substrate. 
     In other features, the integrated circuit package further comprises a plurality of pillars that are used to secure the third substrate on top of the first substrate and provide connections between the first and third substrates. 
     In other features, the third and fourth memory dies are disposed on top of the third substrate. 
     Further areas of applicability of the present disclosure will become apparent from the detailed description, the claims and the drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein: 
         FIG. 1  depicts an integrated circuit (IC) package including a dynamic random access memory (DRAM) package arranged on top of a system-on-chip (SOC) using package-on-package (POP) technology; 
         FIG. 2  depicts an IC package including a DRAM package and a SOC arranged in a flip-chip configuration on a package substrate; 
         FIG. 3A  depicts an IC package including a DRAM package and a SOC, where solder balls connecting the DRAM package to a package substrate are pushed towards the edges of the DRAM package; 
         FIG. 3B  depicts a DRAM package including three rows of 0.8 mm pitch balls on each side of the DRAM package; 
         FIG. 3C  a DRAM package including three rows of 0.4 mm pitch balls on a single side of the DRAM package; 
         FIG. 3D  depicts an arrangement of the 0.4 mm pitch balls one ball is removed for every two balls in an inner row; 
         FIG. 4A  depicts an IC package including an interposer arranged between a DRAM package and a package substrate with a SOC arranged on the package substrate; 
         FIG. 4B  depicts an IC package including a DRAM package and a SOC arranged in a flip-chip configuration in a window on a package substrate; 
         FIG. 4C  depicts an IC package including an interposer arranged between a DRAM package and a package substrate with a SOC arranged in a window on the package substrate; 
         FIG. 5A  depicts a plan view of an IC package including a SOC arranged on two DRAM dies; 
         FIG. 5B  depicts an IC package including a dual DRAM package stacked on top of a SOC arranged on a package substrate; 
         FIG. 6  depicts the IC package of  FIG. 5B  in detail; and 
         FIG. 7  depicts an IC package including a plurality of dual DRAM packages stacked on top of a SOC arranged on a package substrate and including a heat sink. 
     
    
    
     DESCRIPTION 
     Low-power (LP) double-data-rate (DDR) LP-DDR3 dynamic random access memory (DRAM) may double the bandwidth of LP-DDR2 DRAM. Most application processors cannot reach the maximum promised performance of LP-DDR2 because LP-DDR2 pin-out was derived from LP-DDR1, where originally the speed requirement was less important. An important feature, however, is the ability to stack DRAM on top of a system-on-chip (SOC) using package-on-package (POP) packaging. To stack DRAM on top of the SOC using POP packaging, the pins of the LP-DDR1 must be spread around the periphery of the package to allow the SOC to be placed directly under the center of the LP-DDR1 package. Spreading the pins, however, creates a longer signal trace relative to standard DDR2 or DDR3. 
     When the industry moved from LP-DDR1 to LP-DDR2, the industry did not realize that maintaining the pin-out of LP-DDR1 will aggravate the challenge of getting good signal integrity. The industry did not follow the pin-out styling of DDR3 when it moved to LP-DDR2 because standard DDR3-style packaging makes it impossible to do POP-style DRAM/SOC integration. Fundamentally, the only space available under the DDR3 is about 2 mm or so in width. Furthermore, the center of the DDR3 has a protrusion for wire bonding the DDR3 die to the DDR3 substrate. Accordingly, most SOCs cannot fit in the space available using traditional DDR3 package. 
     The present disclosure relates to various packaging configurations and architectures that allow stacking DRAM and an SOC in a single IC package. Additionally, the packaging systems and methods disclosed herein reduce the package size when 32-bit (x32) DDR is used and allow for using 64-bit (x64) DDR without requiring design changes. 
     Referring now to  FIG. 1 , an integrated circuit (IC) package  100  includes a DDRx package  102  arranged on top of a SOC  104  using package-on-package (POP) technology. The SOC  104  is arranged on a package substrate  106 . The DDRx package  102  is connected to the package substrate  106  using solder balls  108 . The IC package  100  can be encapsulated and arranged on a printed circuit board (PCB) or attached to another IC using bonding pads  110  and/or solder balls  112 . The solder balls  108  surround the SOC  104  and limit the width and height of the SOC  104 . 
     Referring now to  FIG. 2 , an IC package  150  includes the DDRx package  102  and the SOC  104  arranged in a flip-chip configuration on the package substrate  106 . While  FIG. 2  shows that the package substrate  106  uses ball grid array (BGA) type packaging, any other type of packaging such as quad flat package (QFP) or quad flat no-leads (QFN) packaging may be used instead. 
     Referring now to  FIGS. 3A-3D , an IC package  200  includes a DDRx package  202  and a SOC  204 . In  FIG. 3A , balls  208  used to connect the DDRx package  202  to the package substrate  106  are pushed towards the edges of the DDRx package  202  so that the SOC  204  can be wider than the SOC  104  shown in  FIGS. 1 and 2 . In  FIG. 3B , a standard DDRx package has three rows of 0.8 mm pitch balls on each side of the DDRx package, which leaves little space (shown dotted) for SOC. In  FIG. 3C , the three rows of 0.8 mm pitch balls can be reduced to two rows of 0.4 mm pitch balls, which leaves more space (shown dotted) than that shown in  FIG. 3B . Accordingly, in  FIG. 3B , the balls  208  can be arranged at 0.4 mm pitch. In  FIG. 3D , the balls in the inner row (row adjacent to the SOC) can be arranged farther apart than the balls in the outer row (row adjacent to the edge of the DDRx package). For example, one or more alternate balls in the inner row can be removed to allow extra space for routing connections. 
     Accordingly, if 0.4 mm pitch balls are used, about 30 balls can be included in a row for a 12 mm high DRAM package (i.e., about 120 balls can be included in 4 rows). One of the advantages of using this modified ball arrangement is that future high-speed mobile-class DRAM (e.g., LP-DDR3 used in mobile devices) could use the same layout topology of PC-class DRAM (e.g., DDR3) using centered I/O placement. This can provide performance similar to PC-class DRAM in a package that will be suitable for POP-mounting of mobile application processors. 
     Further, since 120 balls are normally unnecessary for a typical x32 wide I/O DRAM, the inner rows of balls can be arranged slightly sparser. For example, one ball for every two balls can be removed. This will result in about 20 balls for each inner row having 0.4 mm pitch. As a result, only 100 pins are necessary for a 12 mm high package. This should be sufficient for x32 LP-DDR3 requirement. If insufficient, a few balls can be allocated on the top and bottom edges so long as the balls do not get close to the center of the package since the center of the package is used for opening for the wire bonding of the DRAM die to the substrate. 
     Referring now to  FIGS. 4A-4C , an interposer may be used between the DDRx package  102  and the package substrate  106  to create additional space for the SOC  204 . For example, in  FIG. 4A , an IC package  250  includes an interposer  252  arranged between the DDRx package  102  and the package substrate  106 . Instead of pushing the balls  108  of the DDRx package  102  out toward the edges of the IC package  250 , the interposer  252  includes the balls  208  that are pushed out toward the edges of the IC package  250 . Pushing the balls  208  out toward the edges of the IC package  250  creates additional space for the SOC  204 . The interposer  252  provides connections between the balls  108  and the balls  208 . 
     In  FIG. 4B , instead of using an interposer, the package substrate  106  can include a window in which the SOC  204  is arranged. For example, in an IC package  300  shown, a package substrate  106 - 1  includes a window  302 . The window  302  is arranged along a first surface  304  of the package substrate  106 - 1  that is opposite to a second surface  306  of the package substrate  106 - 1 , where the first surface  304  is adjacent to the bottom of the IC package  300 , and where the second surface  306  is adjacent to the DDRx package  102 . 
     In  FIG. 4C , an IC package  350  includes the interposer  252  and a package substrate  106 - 2 . The package substrate  106 - 2  includes a window  352 . The window  352  is arranged along a first surface  354  of the package substrate  106 - 2 , where the first surface  354  is adjacent to the interposer  252  and opposite to a second surface  356  of the package substrate  106 - 2 , where the second surface  356  is adjacent to the bottom of the IC package  350 . 
     Referring now to  FIGS. 5A and 5B , a dual DDRx package can be stacked on top of a SOC. Typically, in  FIG. 5A , an IC package  400  includes two DRAM dies  402 - 1  and  402 - 2  and a SOC  404 . The DRAM dies  402 - 1  and  402 - 2  are cut as a pair and are used as a substrate on top of which the SOC  404  is stacked. Each of the DRAM dies  402 - 1  and  402 - 2  includes three rows of 0.8 mm pitch balls on each side. 
     Instead, in  FIG. 5B , an IC package  450  includes a dual DDRx package  452  stacked on top of a SOC  454 . The SOC  454  is arranged on a package substrate  456 . The dual DDRx package  452  includes two DRAM dies  458 - 1  and  458 - 2 . The DRAM dies  458 - 1  and  458 - 2  can be separated before packaging. In the dual DDRx package  452 , the DRAM dies  458 - 1  and  458 - 2  can be arranged closer to each other or farther apart from each other. 
     Each of the DRAM dies  458 - 1  and  458 - 2  includes only three rows of 0.4 mm pitch balls  460 - 1  and  460 - 2  on one side instead of three rows of 0.8 mm pitch balls on each side. Since the pitch of the balls  460 - 1  and  460 - 2  is half of the pitch of the balls shown in  FIG. 5A , the number of balls in the IC package  450  can be doubled in the same amount of space. Accordingly, while the total number of balls per DRAM is the same in  FIGS. 5A and 5B , the balls corresponding to a DRAM can be arranged only on one side of the IC package  450 . The connections from the DRAM die  458 - 1  to the balls  460 - 1  can be arranged on the left side of the IC package  450 , and the connections from the DRAM die  458 - 2  to the balls  460 - 2  can be arranged on the right side of the IC package  450 . The SOC  454  can be arranged on the package substrate  456  in the space between the balls  460 - 1  of the DRAM  458 - 1  and the balls  460 - 2  of the DRAM die  458 - 2 . 
     Referring now to  FIG. 6 , the IC package  450  is shown in detail. In the dual DDRx package  452 , the DRAM dies  458 - 1  and  458 - 2  are arranged on a package substrate  470 . The DRAM dies  458 - 1  and  458 - 2  may be integrated in a single chip or alternatively implemented as separate chips. The package substrate  470  of the dual DDRx package  452  includes two windows  472 - 1  and  472 - 2 . The window openings are not centered but instead slightly offset in such a way that the window openings are placed approximately at a quarter distance of away from the edge of the die (toward inner direction). This can be pictured as if two almost identical DDR3 dies  458 - 1  and  458 - 2  are placed next to each other in horizontal direction (assuming existing pins are placed vertically). 
     Bonding wires  474 - 1  and  474 - 2  respectively connect the DRAM dies  458 - 1  and  458 - 2  to the package substrate  470 . This arrangement, in combination with moving the balls  460 - 1  and  460 - 2  respectively to the left and right edges of the package substrate  470  (explained above with reference to  FIG. 3A ), decreases wiring distances from the DRAM dies  458 - 1  and  458 - 2  to the respective balls  460 - 1  and  460 - 2 . This in turn decreases inductance and parasitic capacitances on high speed signal traces, especially on data pins. 
     In order to get maximum possible flexibility and speed, control and address (C/A) buses can be allocated around the center of the IC package  450  while the data buses can be allocated at the outer corners of the IC package  450 . Accordingly, for an x32 (i.e., 32-bit) configuration, 8 data pins can be allocated on each corner, and for an x64 (i.e., 64-bit) configuration, 16 data pins can be allocated on each corner. Further, the extra 8 pins (plus each associated control pin) for supporting the x64 configuration can be arranged at the outer most locations. This results in a smaller DRAM package for the x32 configuration while preserving forward compatibility with the x64 configuration. This allows the x32 configuration to use a smaller package to save cost. 
     Referring now to  FIG. 7 , an IC package  500  including stacked DRAM dies is shown. For example, in the IC package  500 , the DRAM dies  458 - 1  and  458 - 2  are arranged on a package substrate  470 - 1 , and DRAM dies  458 - 3  and  458 - 4  are arranged on a package substrate  470 - 2 . The DRAM dies  458 - 1  and  458 - 2  arranged on the package substrate  470 - 1  are stacked vertically on top of the DRAM dies  458 - 3  and  458 - 4  arranged on the package substrate  470 - 2 . Additional DRAM dies can be stacked vertically on top of the DRAM dies  458 - 3  and  458 - 4 . A heat spreader  508  is arranged on top of the DRAM dies  458 - 3  and  458 - 4 . A heat sink  510  is arranged on top of the heat spreader  508 . 
     The package substrate  470 - 1  includes bonding pads  501 - 1  and  501 - 2  on lower and upper surfaces of the package substrate  470 - 1 , respectively. The balls  460 - 1  and  460 - 2  connect the bonding pads  501 - 1  of the package substrate  470 - 1  to the package substrate  456 . Through-silicon vias  502 - 1  connect the bonding pads  501 - 1  to the bonding pads  501 - 2 . 
     The package substrate  470 - 2  includes bonding pads  501 - 3  and  501 - 4  on lower and upper surfaces of the package substrate  470 - 2 , respectively. Through-silicon vias  502 - 2  connect the bonding pads  501 - 3  to the bonding pads  501 - 4 . Pillars  504  connect the bonding pads  501 - 2  of the package substrate  470 - 1  to the bonding pads  501 - 3  of the package substrate  470 - 2 . Other types of connections such as balls may be used instead of the pillars  504 . 
     Using the above approach with x64 (or x72) configuration, DIMM packaging can be eliminated altogether from future PC DRAM requirement. This would be extremely important as the industry moves to DDR4 speed for PC applications. Another major benefit of the above approach is that only a single DRAM in the DRAM stack is active during normal operation since each DRAM can supply all 64 signal pins. Further, the address and command pins (the C/A pins) are effectively point-to-point as far as the connection to the main CPU (in the SOC  454 ) is concerned, thus allowing the C/A pins to operate at a much higher clock frequency. The C/A pins can also have on-chip termination for at least one of the DRAMs in the stack (e.g., in the top of the stack) to allow very high speed operation. This will reduce power dissipation drastically. Finally, while the entire DRAM needs to be cooled for PC applications (at very high speed), only a single stack of DRAM needs to be cooled with a single heat sink  510 , thus lowering heat sink cost as well. 
     The IC packages disclosed above may be used in a variety of computing devices including, but not limited to, a smartphone, a tablet, a laptop, a personal computer, a television, and a setup box. 
     The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure.