Abstract:
The invention provides a synchronizer incorporating a Δ-Σ modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked loop, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Placement of the Δ-Σ modulator outside the frequency-locked loop allows selectable adjustment of the frequency offset measurement block&#39;s frequency. A mapper incorporating the Δ-Σ modulator interprets the pulse train output by the Δ-Σ modulator as stuff/null/de-stuff commands.

Description:
TECHNICAL FIELD 
   This invention pertains to minimization of low frequency jitter during bit stuff mapping of plesiochronous data signals into synchronized data signals. 
   BACKGROUND 
   “Bit stuffing” is a well known technique used in synchronizing data signals by “mapping” such signals from one data rate to a different data rate. For example, as shown in  FIG. 1 , plesiochronous signals, such as DS-1, DS-2 or DS-3 signals respectively characterized by 1.544 Mb/s, 6.312 Mb/s or 44.736 Mb/s clock rates, are commonly mapped from a plesiochronous link  10  to a SONET/SDH link  12  having a different characteristic clock rate, such as the 1.728 Mb/s rate of the SONET VT1.5 signal. An electronic device known as a “mapper”  14  performs the mapping operation. After transmission over SONET/SDN link  12 , the signal is desynchronized (demapped) by “demapper”  16  which reconverts the SONET/SDH signal to a plesiochronous signal for transmission over another plesiochronous link  18 . 
   The bit stuffing technique involves insertion (“stuffing”) of positive or negative bits into the data stream during the mapping operation. If these bit “stuffs” are performed in a regular and efficient manner they impose unacceptable low frequency jitter on the mapped data stream. It is very difficult to remove such low frequency jitter when the data stream is desynchronized (demapped), particularly in older “legacy” systems utilizing 40 Hz jitter filters. Consequently, the prior art has evolved various bit stuffing techniques for minimizing low frequency jitter by translating jitter energy to higher frequencies at which it is more easily removed. 
   One prior art technique utilizes phase lock loops (PLLs) incorporating voltage controlled oscillators (VCOs) having frequency characteristics governed by the level of a FIFO buffer (sometimes called an “elastic store”) through which the data stream is processed. However, VCO-based PLL techniques involve comparatively expensive analog circuitry. 
   In another prior art technique known as “threshold modulation” the sawtooth-like characteristic of the FIFO buffer fill level is monitored and used to perform dithering of the bit stuffing operation. This requires monitoring of the FIFO buffer depth, and access to the FIFO buffer pointers. Moreover, the frequency of the aforementioned sawtooth characteristic affects the higher frequency band into which the jitter energy is translated, constraining circuit design if the sawtooth frequency is fixed. Stuff requests are produced on the basis of phase comparisons relative to a threshold level which is cyclically varied or modulated with a waveform having the same period as the stuffing “superframe.” The phase comparison is governed by the elastic store write and read address pointers. 
   U.S. patent application Ser. No. 09/641,980 filed 21 Aug. 2000 and assigned to the assignee of the present invention (the &#39;980 application), discloses a jitter frequency shifting “delta-sigma” (Δ-Σ) modulated signal synchronization mapper which utilizes a deltasigma synchronizer (DSS) containing a Δ-Σ modulator that functions as a notional voltage controlled oscillator (VCO) to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, thereby simplifying attenuation of the jitter energy when the data stream is desynchronized (demapped). The &#39;980 application&#39;s Δ-Σ modulator is integrally coupled within a frequency-locked loop (FLL)—a leading lowpass filter and the Δ-Σ modulator form a coupled loop control circuit. 
   The &#39;980 application&#39;s DSS is constrained in that the Δ-Σ modulator is inside the loop of the PLL. This does not allow flexibility in selecting the frequency offset measurement frequency. This may present a problem in systems that employ a relatively slow bit-stuffing clock, as the waiting time jitter generated by the phase detector (frequency offset measurement block) could become significantly large. 
   This invention seeks to address or at least ameliorate the foregoing problems. Unlike the aforementioned threshold modulation technique, this invention (like that described in the &#39;980 application) utilizes direct measurement of the frequency offset between a recovered line clock and a system clock, with no threshold modulation based on generation of bit stuff commands. 
   SUMMARY OF INVENTION 
   In a broad form, the invention utilizes a synchronizer which includes a Δ-Σ modulator (i.e. a stuffing generator), coupled in series with a frequency offset measurement block and a measurement low pass filter, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Frequency offset is measured by counting the number of excess or missing line clock edges within a measurement period. The measured frequency offset is then filtered by a digital frequency-locked loop (DFLL), which attenuates jitter. More particularly, the Δ-Σ modulator produces stuff/null/de-stuff commands based on the DFLL&#39;s output. Pulse-stuffing/waiting time jitter (caused by quantization introduced by the frequency offset measurement) is attenuated by the DFLL, which functions as a measurement filter. 
   In a preferred form of the invention the Δ-Σ modulator is not part of any FLL, thereby allowing greater design flexibility. The Δ-Σ modulator (i.e. stuffing generator) generates an accurate pulse train which a mapper incorporating the Δ-Σ modulator interprets as stuff/null/de-stuff commands. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
       FIG. 1  schematically depicts prior art mapping of signals from a plesiochronous link for transmission on a SONET/SDH link and subsequent demapping of the signals on the SONET/SDH link for transmission on another plesiochronous link. 
       FIG. 2  is a block diagram representation of a mapper incorporating a synchronizer in accordance with the invention. 
       FIG. 3  graphically depicts an example of the pulse stuffing/waiting time jitter. The solid line represents the phase ramp; the dotted line represents quantization of the phase ramp; and, the dashed-dotted line represents the quantization error as a function of time. 
       FIG. 4  graphically depicts an exemplary input quantization power spectrum for the invention, showing the amplitude of the quantization jitter (dB) as a function of frequency (Hz) in a linear vs. logarithmic plot. 
       FIG. 5  is a block diagram representation of the measurement low pass filter of the synchronizer in accordance with the invention. 
       FIG. 6  is a block diagram representation of the Δ-Σ modulator (i.e. stuffing generator) of the synchronizer in accordance with the invention. 
   

   DESCRIPTION 
   Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense. In the Figures, incorporated to illustrate features of the present invention, like reference numerals are used to identify like parts throughout. 
     FIG. 2  depicts the architecture of mapper  20  in block diagram form. Mapper  20  incorporates a novel Δ-Σ synchronizer (DSS)  21  for controlling the level of FIFO buffer  22 . 
   DSS  21  in turn incorporates frequency offset measurement block (FOMB)  23 , measurement low pass filter  24  (i.e. a digital frequency-locked loop—DFLL) and Δ-Σ modulator  25  (i.e. bit stuffing command generator) in a series arrangement. FOMB  23  measures the relative difference (frequency offset) between the frequency of measurement (i.e reference) clock  26  and the frequency of the clock signal derived by clock recovery circuit  29  from the signal input on line  28 . The quantizing nature of FOMB  23 &#39;s frequency offset measurement necessarily introduces jitter, which is reduced by measurement low-pass filter  24 . Filter  24  also prevents aliasing when the frequency offset measurement is translated into stuffing commands. Δ-Σ modulator  25  compensates for the frequency offset between the system (i.e. reference) and recovered clocks, as well as for any other frequency offset caused by the mapping operation. Δ-Σ modulator  25  quantizes its commands to produce valid stuffing integers without any bias in roundoff error. FIFO buffer adjuster  32  forces correction of DSS  21 &#39;s accounting as FIFO buffer  22  approaches its full (or empty) level. Such correction is unnecessary if DSS  21  is operating within a pre-determined tracking range, but may be useful to attain fast synchronization in an extreme case, if DSS  21  loses its frequency lock. Measurement clock  26  and stuffing clock  27  are derived from the same network system clock and hence are synchronized. 
   Plesiochronous input data line  28  is coupled to FIFO buffer  22 . Clock recovery circuit  29  derives a recovered clock signal representative of the frequency of the signal input on line  28 , as previously explained. The recovered clock signal is passed to write address generator  30  and to FOMB  23 . Write address generator  30  and read address generator  31  are coupled to FIFO buffer  22  and to FIFO adjuster  32 . The output of FIFO adjuster  32  is applied to adder  33 , which also receives the output signal produced by FOMB  23 . DSS  21  outputs stuff/null/destuff commands to timing controller  34 , based on the signal output by DFLL  24 . Timing controller  34  forwards the commands to read address generator  31  and to framer  35 . Data is read out of FIFO buffer  22  and passed to framer  35 , which outputs synchronized data  36 . 
   Adder  33  normally outputs  0 . But, if DSS  21  is unable to track the frequency offset between the recovered and reference clocks, adder  33  outputs a value representative of the offset between the read and write pointers, which may be substantial. The FIFO level is thus controlled so that it neither rises above nor drops below pre-defined thresholds. If the FIFO level is not within those thresholds (which is unusual), FIFO adjuster  32  outputs a number which is added to DFLL  24 &#39;s internal integrator (formed by adder  52  and delay element  53  shown in  FIG. 5 ) in order to reflect the FIFO fill level. 
   FOMB  23  measures the input frequency offset by counting the number of excess or missing line clock edges within a measurement period. A simple interval counter can be used to perform this function. The measured frequency offset is then filtered by DFLL  24 , to attenuate jitter as aforesaid. Note that unlike the invention described in the &#39;980 application, which places the Δ-Σ modulator inside a phase-locked loop, this invention cascades Δ-Σ modulator  25  after the DFLL loop. 
   Quantization error introduced by FOMB  23  (i.e. pulse stuffing/waiting time jitter) has a sawtooth characteristic, represented by the dashed-dotted line in  FIG. 3 . More particularly, pulse stuffing/waiting time jitter is caused by the quantization error of a phase ramp measured in Units Intervals (UIs) of the sampling clock. The phase ramp (solid line in  FIG. 3 ) is a consequence of the frequency offsets between the recovered and reference clocks. The pulse stuffing/waiting time jitter constitutes the subtraction of the phase ramp from its quantized version (dotted line in  FIG. 3 ). The jitter signal&#39;s sawtooth characteristic can be described in terms of a Fourier series having a fundamental frequency dependant on the frequency offset and the line clock rate f 1 . DSS  21  samples the sawtooth signal at FOMB  23 &#39;s sampling rate f s . A frequency offset measured in parts-per-million (ppm) produces a sawtooth signal with a fundamental period T given by: 
   
     
       
         
           
             
               
                 T 
                 = 
                 
                   
                     10 
                     6 
                   
                   
                     ppm 
                     · 
                     
                       f 
                       1 
                     
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
   
   A sawtooth waveform saw 1 (t) can be represented in continuous time as a Fourier series: 
                     saw   1     ⁡     (   t   )       =       -     1   π       ⁢       ∑     n   =   1     ∞     ⁢           (     -   1     )     n     n     ⁢     sin   ⁡     (       2   ⁢   n   ⁢           ⁢   π   ⁢           ⁢   t     T     )                     (   2   )               
having an amplitude measured in UIs where one UI=1/f 1  seconds.
 
   The sawtooth pattern spectrum decays slowly as the frequency increases. Since the sawtooth waveform is sampled at a rate determined by FOMB  23 , which is not related to the fundamental frequency, the decay of the Fourier series will alias “in band” as shown in  FIG. 4 . 
   The quantization jitter (also known as “pulse stuffing” or “waiting time” jitter) spectrum shown in  FIG. 4  is for a 50 ppm frequency offset with a sampling rate of 1.44 MHz. Equation (1) thus yields a fundamental frequency of 15.5 kHz. Note the 20 dB-per-decade decay of the spectrum and the aliasing back of the jitter spectrum. 
   To minimize the aliased spectrum, the measurement frequency should be as high as possible. The approach taken in the &#39;980 application is to equate the measurement frequency to that of the stuffing command generator (Δ-Σ modulator). In some applications, the frequency of stuffing clock  27  is sufficiently high that the resultant waiting time jitter is small. This invention allows the frequency of FOMB  23  to be selectably increased, which is advantageous. 
   As previously explained, DFLL  24  filters (attenuates) pulse-stuffing/waiting time jitter caused by FOMB  23 &#39;s quantizing frequency offset measurement. The effectiveness of DFLL  24 &#39;s filtration depends on the ppm offset. Very small offsets are not filtered out well, especially if the fundamental falls between the cutoff frequency of the DFLLs in mapper  20  and the corresponding demapper (not shown). 
     FIGS. 5 and 6  respectively depict in greater detail a DFLL  24  and a second order Δ-Σ modulator  25  (i.e. bit stuffing command generator) suitable for use in DSS  21 . 
   DFLL  24  shown in  FIG. 5  receives as input from FOMB  23  a frequency offset signal  50  that is input to adder  51 . A feedback signal produced by delay element  58  is also input to adder  51 , as illustrated, forming a first feedback loop. Adder  52  and delay element  53  together form an accumulator (i.e. integrator) the output of which reflects the FIFO fill level. The output signal produced by adder  52  is input to delay element  53 , forming a second feedback loop. Adder  52 &#39;s output signal is also input to scaler (i.e. amplifier)  54 . The output signal produced by scaler  54  is input to downsampler register  55 , which is triggered by downsampler timer  56 —a simple wrapping timer. A measurement low pass filter output signal  57  is produced at the output of DFLL  24 . Output signal  57  is fed back to delay element  58 , which in turn sends its output signal to adder  51  as aforesaid. 
   DFLL  24  shown in  FIG. 5  filters low-frequency jitter caused by FOMB  23 &#39;s quantization operation, as aforesaid. Downsampler register  55  removes any biasing due to round-off errors caused by fixed-point processing. A limiter (not shown) within downsampler register  55  prevents application to the input of Δ-Σ modulator  25  of values exceeding the Δ-Σ parameter M (explained below). Such excess values could drive Δ-Σ modulator  25  outside its desired mode of operation. 
   The downsampler formed by downsampler register  55  and downsampler timer  56  synchronizes DFLL  24  and Δ-Σ modulator  25 , taking into account the fact that DFLL  24 &#39;s timing signal is supplied by measurement clock  26  whereas Δ-Σ modulator  25 &#39;s timing signal is supplied by stuffing clock  27 . These two clocks output different clock signals, although they are both synchronized with the system reference clock (not shown). For example, if the signal output by measurement clock  26  is 8 times higher than that output by stuffing clock  27  then downsampler register  55  selects every 8th signal output of scaler  54  in accordance with to a value determined by timer  56 . 
   DFLL  24 &#39;s transfer function H(z), and the cutoff frequency f cutoff  of DSS  21  are given by: 
                   H   ⁡     (   z   )       =       1   K     *     z     z   -     K     K   -   1                     (   3   )                 f   cutoff     =         f   s       2   ⁢   π       *     1   K               (   4   )               
where f s  is the measurement clock frequency, and the gain, G, of scaler (i.e. amplifier)  54  is G=1/K.
 
   Referring now to  FIG. 6 , Δ-Σ modulator  25  incorporates subtracter  60 ; adders  61 ,  62 ,  63 ; delay elements  64 ,  65 ,  66 ; quantizer  67  and multiplier  68 . Multiplier  68  multiplies Δ-Σ modulator  25 &#39;s output signal  69  by a factor M. The resultant M-multiplied signal is applied to the “−” input of subtracter  60  to establish the interval over which subtracter  60  integrates the input signal  70  output by DFLL  24 , resulting in output of a signal val by subtracter  60 . Adder  61  adds the val signal output by subtracter  60  to the A0 signal output by delay element  64 , resulting in output of a signal A 0 +val by adder  61 . Adder  62  adds the A0+val signal output by adder  61  to the A1 signal output by delay element  65 , resulting in output of a signal A 0 +A 1 +val by adder  62 . Adder  63  adds the A0+A1+val signal output by adder  62  to the A0+val signal output by adder  61 , resulting in output of a signal  2 A 0 +A 1 + 2 val by adder  63 . Quantizer  67  outputs −1, 0, or +1 depending on whether the signal  2 A 0 +A 1 + 2 val output by adder  63  is respectively less than, between, or greater than the quantizer&#39;s threshold values ±[(M/2)+K s ], where M, K s  are constants as hereinafter explained. 
   In a preferred embodiment K s =36 and M=4,094. Therefore, ±[(M/2)+K s ]=±2,083. If the value output by adder  63  (i.e. 2A0+A1+2val) exceeds 2,083 then quantizer  67  outputs the value +1. If (2A0+A1+2val)&lt;−2,083 then quantizer  67  outputs the value −1. If −2,083≦(2A0+A1+2val)≦2,083 then quantizer  67  outputs the value 0. See Riley et al “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”,  IEEE Journal of Solid - State Circuits  Vol. 28, No. 5, May 1993, pp. 553-559 for further details of (Δ-Σ) modulators, particularly factors affecting stability and overflow characteristics thereof. 
   The −1, 0, or +1 signals output by quantizer  67  are processed by delay element  66  which in turn outputs either a phase increment (pll_inc) command signal to insert a stuff bit into the mapped VC-11 or VC-12 in the output SONET/SDH data stream; or, a phase decrement (pll_dec) command signal to remove a stuff bit from the output data stream. Only one or the other of pll_inc or pll_dec can be asserted at one time to either speed up or slow down the output data stream. If neither pll_inc nor pll_dec are asserted then a null operation is performed, such that the output data stream&#39;s rate remains unaffected. 
   As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example, different DFLLs and Δ-Σ modulators blocks may be used in substitution for those of  FIGS. 5 and 6 . As a further example, the foregoing description assumes a protocol which allows only one bit to be “stuffed” during each bit stuff/destuff opportunity. The invention is readily adapted to use with protocols allowing a plurality of bits to be stuffed during each bit stuff/destuff opportunity. This can be accomplished by replacing tri-level quantizer  67  with a multi-level quantizer, since stability and accuracy issues affecting the operation of multi-level quantizers in Δ-Σ modulators affect only analog implementations. The scope of the invention is to be construed in accordance with the substance defined by the following claims.