Abstract:
According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.

Description:
BACKGROUND 
     I. Definition 
     As used herein, the phrase “group III-V” to a compound semiconductor that includes at least one group III element and at least one group V element. By way of example, a group III-V semiconductor may take the form of a III-Nitride semiconductor. “III-Nitride” or “III-N” refers to a compound semiconductor that includes nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (Al x Ga (1−x) N), indium gallium nitride (In y Ga (1−y) N), aluminum indium gallium nitride (Al x In y Ga (1−x−y) N), gallium arsenide phosphide nitride (GaAs a P b N (1−a−b) ), and aluminum indium gallium arsenide phosphide nitride (Al x In y Ga (1−x−y) As a P b N (1−a−b) ), for example. III-Nitride also refers generally to any polarity including but not limited to Ga-polar, N-polar, semi-polar, or non-polar crystal orientations. A III-Nitride material may also include either Wurtzitic, Zincblende, or mixed polytypes, and may include single-crystal, monocrystalline, polycrystalline, or amorphous structures. Gallium nitride or GaN, as used herein, refers to a III-Nitride compound semiconductor wherein the group III element or elements include some or a substantial amount of gallium, but may also include other group III elements in addition to gallium. 
     In addition, as used herein, the phrase “group IV” refers to a semiconductor that includes at least one group IV element such as silicon (Si), germanium (Ge), and carbon (C), and may also include compound semiconductors such as silicon germanium (SiGe) and silicon carbide (SiC), for example. Group IV also refers to semiconductor materials which include more than one layers of group IV elements, or doping of group IV elements to produce strained group IV materials, and may also include group IV based composite substrates such as silicon on insulator (SOI), separation by implantation of oxygen (SIMOX) process substrates, and silicon on sapphire (SOS), for example. 
     II. Background Art 
     A group heterostructure field-effect transistor (group III-HFET), such as group III-V high electron mobility transistor (group III-V HEMT), can include III-Nitride films formed on a non-native substrate, such as group IV substrate e.g., silicon). Epitaxial growth or deposition of the III-Nitride films he non-native substrate often results in excessive wafer warpage and bow. Also, deleterious cracking and delamination of the III-Nitride films and/or the non-native substrate may occur. These undesirable results are typically caused by lattice constant mismatches between the III-Nitride films and the non-native substrate, as well as differences in coefficients of thermal expansion between the III-Nitride films and the non-native substrate. 
     Various approaches have been proposed to accommodate for stresses associated with depositing III-Nitride films on a non-native substrate. One such approach is the use of a compositionally graded transition layer as disclosed in U.S. Pat. No. 6,649,287, entitled “Gallium Nitride Materials and Methods,” and issued on Nov. 18, 2003, the disclosure of which is hereby incorporated fully by reference into the present application. Another approach is the use of compositionally graded transition layers as disclosed in U.S. Pat. No. 7,365,374, entitled “Gallium Nitride Material Structures Including Substrates and Methods Associated with the Same,” and issued on Apr. 29, 2008, the disclosure of which is hereby incorporated fully by reference into the present application. 
     An approach that has been proposed to accommodate for stresses associated with epitaxial growth of III-Nitride films on a non-native substrate is to modify the surface of the non-native substrate prior to the epitaxial growth. One such approach is to employ grid arrays or control joints formed in the non-native substrate of a wafer prior to growth of the III-Nitride films. These control joints can be aligned with saw streets for dies and prevent large area coalescence across entirety of the wafer. The total stress built up across the wafer is thereby reduced, as disclosed in U.S. Pat. No. 8,557,681, entitled “III-Nitride Wafer Fabrication,” and issued on Oct. 15, 2013, the disclosure of which is hereby incorporated fully by reference into the present application. 
     SUMMARY 
     Delamination and crack prevention in III-Nitride wafers, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a top plan view of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 2A  illustrates a top plan view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 2B  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 3A  illustrates a top plan view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 3B  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 4A  illustrates a top plan of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 4B  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 5  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 6  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
         FIG. 7  illustrates a cross-sectional side view of a III-Nitride die of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
     
    
    
     DETAILED DESCRIPTION 
     The following description contains specific information pertaining to various implementations in the present disclosure. The drawings in the present application their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are it intended to correspond to actual relative dimensions. 
       FIG. 1  illustrates a top plan view of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. In particular,  FIG. 1  shows a top plan view of semiconductor wafer  100  having grid array trenches  102  etched across semiconductor wafer  100 , and edge trench  104  around a perimeter of semiconductor wafer  100 . In an implementation of the present disclosure, semiconductor wafer  100  may be a processed III-Nitride wafer having a III-Nitride body disposed over a semiconductor substrate, such as a group IV substrate (not explicitly shown in  FIG. 1 ). In addition, one or more device layers, such as one or more post epitaxial device layers (e.g., field dielectric layers, other dielectric layers, and/or metal layers) may be formed over the III-Nitride body (not explicitly shown in  FIG. 1 ). 
     In accordance with various implementations of the present disclosure, grid array trenches  102  may be aligned with saw streets for forming  111 -Nitride dies on semiconductor wafer  100 . In one implementation, grid array trenches  102  may be approximately ten micrometers (10 um) wide or greater, by way of example. Edge trench  104  may he formed on the edge of semiconductor wafer  100 . In the present implementation, edge trench  104  may be approximately two millimeters (2 mm) wide or greater, by way of example. Also shown in  FIG. 1  are regions  106  and  108 , which will be described in greater detail below. 
     Referring now to  FIGS. 2A and 2B ,  FIG. 2A  illustrates a top plan view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application.  FIG. 2B  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
     In particular,  FIGS. 2A and 2B  show respective top and cross-sectional side views of region  206  having grid array trenches  210 , which may correspond to an enlarged view of region  106  of semiconductor wafer  100  in  FIG. 1 . Region  206  includes substrate  201 , III-Nitride body  220  (or more generally “group III-body body  220 ”), and device layer  222  (e.g., one or more post epitaxial device layers, such as field dielectric layers, and/or other dielectric layers). Region  206  may also include grid array trenches  210  corresponding to grid array trenches  102  of  FIG. 1 . 
     Substrate  201  may be a group IV substrate that includes at least one group IV element such as silicon (Si), germanium (Ge), and carbon (C), and may also include compound semiconductors such as silicon germanium (SiGe) and silicon carbide (SiC), for example. Substrate  201  may also be a group IV substrate that includes more than one layer of group IV elements, and/or doped group IV elements to produce strained group IV materials. Substrate  201  may also be a group IV substrate that is a composite substrate, such as a silicon-on-insulator (SOI) substrate, a separation by implantation of oxygen (SIMOX) substrate, or a silicon-on-sapphire (SOS) substrate, for example. 
     III-Nitride body  220 , which is formed on substrate  201 , may include multiple III-Nitride films, such as an intermediate layer (e.g., an aluminum nitride (AlN) intermediate layer), a transition layer (e.g., an aluminum gallium nitride (AlGaN) transition layer), and III-Nitride device layers forming a heterojunction near an interface therebetween (e.g., a heterojunction formed by an interface of aluminum gallium nitride (AlGaN) gallium nitride (GaN)). III-Nitride body  220  can be grown over substrate  201  (e.g. a group IV substrate). For example, III-Nitride body  220  can be epitaxially grown on substrate  201 . 
     As illustrated in  FIG. 213 , device layer  222  may be formed over III-Nitride body  220 . In one implementation, device layer  222  includes one or more post epitaxial device layers, such as field dielectric layers, other dielectric layers, metal layers, and/or semiconductor layers. For example, device layer  222  can include dielectric layers and/or metal layers used in back end process steps of a semiconductor wafer. 
     As shown in  FIGS. 2A and 2B , grid array trenches  210  are formed in III-Nitride body  220  defining a plurality of III-Nitride dies in a semiconductor wafer (e.g. semiconductor wafer  100  of  FIG. 1 ). For example, grid array trenches  210  can be etched in III-Nitride body  220 . Grid array trenches  210  can be etched in III-Nitride body  220  to form a plurality of III-Nitride dies, as shown in  FIGS. 2A and 2B . Device layer  222  is formed over each of the plurality of III-Nitride dies The plurality of III-Nitride dies can be seperated by cutting the semiconductor wafer (e.g. semiconductor wafer  100  of  FIG. 1 ) approximately along grid array trenches  210 , thereby forming separate dies. 
     Grid array trenches  210  may include trenches of width  212 . In accordance with an implementation of the present disclosure, width  212  may be approximately 10 urn or greater. In, one implementation, grid array trenches  210  are substantially aligned with the dicing streets across the III-Nitride wafer (e.g. semiconductor wafer  100  of  FIG. 1 ). By way of example, dicing streets associated with mechanical sawing may have a width of 50 microns or more depending on the kerf width of the saw blade. As such, width  212  of grid array trenches  210  may be less than the width of the dicing streets, may be approximately equal to the dicing street width, or may be greater than the dicing street width. In another implementation, grid array trenches  210  are not entirely aligned with the dicing streets. Additional trenches or control joints may also be included in the III-Nitride wafer. 
     As can be seen in  FIG. 2B , according to the present implementation, grid array trenches  210  extends down through device layer  222  and III-Nitride body  220 , and terminates at a top surface of substrate  201 . In another implementation, grid array trenches  210  may not terminate on the top surface of substrate  201 , but rather may extend down into substrate  201 . In yet another implementation, grid array trenches  210  may terminate within III-Nitride body  220  (e.g., at an underlying AlGaN transition layer or AlN intermediate layer fixated below the III-Nitride device layers). 
     As shown in  FIG. 2B , grid array trenches  210  may begin at a top surface of device layer  222  and extend into III-Nitride body  220 . It may be advantageous or desirable to form device layer  222 , such as one or more post epitaxial device layers (e.g., field dielectric layers, other dielectric layers, metal layers, and/or semiconductor layers) or a combination of layers, prior to forming grid array trenches  210 . In another implementation, grid array trenches  210  may be formed at a top surface of Ill-Nitride body  220  prior to the formation of device layer  222 , where device layer  222  is formed after grid array trenches  210  are etched in III-Nitride body  220 . In still other implementations, grid array trenches  210  may be formed through one or more layers in device layer  222  and prior to the deposition or formation of additional layers in device layer  222 . 
     The formation and processing of device layer  222  may increase the total stress on III-Nitride films of III-Nitride body  220  due to added mismatches in thermal expansion. Moreover, in some implementations, device layer  222  requires elevated deposition or annealing temperatures, as well as rapid changes in temperature that increases the total stress on the III-Nitride films. Increasing the total stress on the III-Nitride films can cause delamination and or cracking during subsequent processing and handling f a semiconductor wafer (e.g. semiconductor wafer  100  of  FIG. 1 ), including dicing of the semiconductor wafer and die singulation. 
     Various implementations of the present disclosure alleviate an increase in the total stress on the III-Nitride films that can be caused by the formation and processing of device layer  222 . In various implementations, the increase in the total stress is alleviated utilizing grid array trenches  210 . Grid array trenches  210  may be aligned with the dicing streets that define the plurality of III-Nitride dies with III-Nitride body  220 . Such grid trenches may act to prevent or otherwise inhibit the propagation of stress induced cracks across the wafer, such as semiconductor wafer  100  in  FIG. 1 . 
     Referring now to  FIGS. 3A and 3B ,  FIG. 3A  illustrates a top plan view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application.  FIG. 3B  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
     In particular,  FIGS. 3A and 313  show respective top and cross-sectional side views of region  308  having, in part, an edge trench, which may correspond to an enlarged view of region  108  of semiconductor wafer  100  in  FIG. 1 . Region  308  may include substrate  301 , III-Nitride body  320 , and device layer  322 . Region  308  may also include grid, array trenches  310  and edge trench  330  corresponding respectively to grid array trenches  102  and edge trench  104  in  FIG. 1 . 
     In one implementation, substrate  301  may be a group IV substrate, substantially similar to substrate  201  in  FIG. 2B . III-Nitride body  320  may include multiple III-Nitride layers (not explicitly shown in  FIGS. 3A and 3B ). In one implementation, III-Nitride body  320  may be substantially similar to III-Nitride body  220  in  FIG. 2B . As illustrated in  FIG. 3B , device layer  322  may be formed over III-Nitride body  320 . In one implementation, device layer  322  may include one or more post epitaxial device layers, such as field dielectric layers, other dielectric layers, metal layers, and/or semiconductor layers. 
     As illustrated in  FIGS. 3A and 3B , width  312  of grid array trenches  310  is significantly less than width  332  of edge trench  330 . In accordance with an implementation of the present disclosure, width  332  of edge trench  330  may be approximately 2 mm or greater, whereas width  312  of grid array trenches  310  may be approximately 10 um or greater. Thus, width  312  of grid array trenches  310  is significantly less than width  332  of edge trench  330 . 
     As illustrated in  FIG. 3B , edge trench  330  may extend down through device layer  322  and III-Nitride body  320 , and terminate at a top surface of substrate  301 . However, in another implementation, edge trench  330  does not terminate on the top surface of substrate  301 , but rather may extend down into substrate  301 . In yet another implementation, edge trench  330  may terminate within III-Nitride body  320  (e.g., at an underlying AlGaN transition layer or AlN intermediate layer formed below the III-Nitride device layers). In some implementations, the termination of grid array trenches  310  and edge trench  330  may be substantially coplanar. However, in other implementations, the termination of grid array trenches  310  occurs on a different plane or on a different III-Nitride layer than the termination of edge trench  330 . 
     As shown in  FIG. 3B , edge trench  330  may begin at a top surface of device layer  322  and extend into III-Nitride body  320 . It may be advantageous or desirable to form device layer  322 , such as one or more post epitaxial device layers (e.g., field dielectric layers, other dielectric layers, metal layers, and/or semiconductor layers) or a combination of layers, prior to forming edge trench  330 . In another implementation, edge trench  330  may be etched from a top surface of II-Nitride body  320  prior to forming device layer  322  over III-Nitride body  320 . In still other implementations, edge trench  330  may be formed through one or more layers in device layer  222  and prior to the deposition or formation of additional layers in device layer  222 . 
     Referring now to  FIGS. 4A and 4B ,  FIG. 4A  illustrates a top plan view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application.  FIG. 4B  illustrates a cross-sectional side view of a region of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. 
     In particular,  FIGS. 4A and 4B  show respective top and cross-sectional side views of region  406  having id array trenches  410 , which may correspond to an enlarged view of region  106  of semiconductor wafer  100  in  FIG. 1 . Region  406  may include substrate  401 , III-Nitride body  420 , and device layer  422 , corresponding respectively to substrate  201 , III-Nitride body  220 , and device layer  222  of  FIGS. 2A and 2B . As can be seen in  FIG. 4B , according to the present implementation, grid array trenches  410  can extend down through device layer  422  and III-Nitride body  420 , and into substrate  401 . For example, grid array trenches  410  can be etched in substrate  401 , such that grid array trenches  410  are formed in substrate  401 . 
     Thus, as described above with respect to  FIGS. 1, 2A, 2B, 3A .,  3 B,  4 A, and  4 B, various implementations of the present application provide for semiconductor wafers having grid array trenches in a III-Nitride body that includes III-Nitride films. The grid array trenches can substantially reduce or prevent stress in the III-Nitride films. In particular, the grid array trenches can substantially reduce or prevent additional stress buildup that may result from device fabrication post epitaxial growth, and can thereby prevent delamination and/or cracking during subsequent processing steps and handling of the semiconductor wafers. Such grid trenches may act to prevent or otherwise inhibit the propagation of stress induced cracks across the wafer epitaxial wafer. 
     From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described above, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure. 
     Referring now to  FIG. 5 ,  FIG. 5  illustrates a cross-sectional side view of region  506  having, in part, grid array trenches  510  of an exemplary semiconductor wafer, according to an implementation disclosed in the present application. As shown in  FIG. 5 , region  506  may correspond to an enlarged view of region  106  of semiconductor wafer  100  in  FIG. 1 . Region  506  may include substrate  501 , III-Nitride body  520 , and device layer  522 , corresponding respectively to substrate  201 , III-Nitride body  220 , and device layer  222  of  FIGS. 2A and 2B . As can be seen in  FIG. 5 , according to the present implementation, grid array trenches  510  having trench width  515  can extend down through device layer  522  and III-Nitride body  520  and terminate at a top surface of substrate  501 . However, in another implementation, grid array trenches  510  do not terminate on the top surface of substrate  501 , but rather may extend down into substrate  501 . Also shown in  FIG. 5  are dicing streets  530  having street width  535 . As shown in  FIG. 5 , trench width  515  of grid array trenches  510  is wider than Street width  535  of dicing streets  530 . In certain other implementations shown), it may be advantageous or desirable to form trench width  515  narrower than or approximately equal to street width  535 . 
     In an implementation, it may be preferable to form grid array trenches  510  using etching techniques commonly known in the art (wet or dry etching, photochemical assisted etching, ion assisted etching, and plasma assisted etching for example). In certain other implementations, it may be preferred to form grid array trenches  510  using either mechanical (sawing) or laser assisted dicing or scribing techniques. In yet another implementation, a combination of etching and laser scribing techniques may be used to form grid array trenches  510 . 
     In another aspect of the present implementation, dicing streets  530  may be formed using a different technique than that used to form grid array trenches  510 . For example, in an implementation where substrate  501  is a silicon substrate, it may be preferable to use mechanical dicing (sawing) methods commonly used in volume die singulation processes for manufacturing of silicon based semiconductor engineering and to use an III-Nitride wet etching technique to form grid array trenches  510 . 
     Referring now to  FIG. 6 ,  FIG. 6  illustrates a cross-sectional side view of region  606  having, in part, grid array trenches  610   a  and  610   b  of an exemplary semiconductor wafer, according to another implementation disclosed in the present application. As shown in  FIG. 6 , region  606  may include substrate  601 , III-Nitride body  620 , and device layer  622 , corresponding respectively to substrate  201 , III-Nitride body  220 , and device layer  222  of  FIGS. 2A and 2B . As can be seen in  FIG. 6 , according to the present implementation, grid array trenches  610   a  and  610   b  having trench width  615  can extend down through device layer  622  and III-Nitride body  620  and terminate at a top surface of substrate  601 . However, in another implementation (not shown), grid array trenches  610   a  and  610   b  do not terminate on the top surface of substrate  601 , but rather may extend down into substrate  601 . Also shown in  FIG. 6  is dicing street  630  having street width  635 . In particular, the present implementation shown in  FIG. 6 , dicing street  630  spans street width  635  defined by endpoints  640   a  and  640   b . Endpoint  640   a  of dicing street  630  is aligned such that it is located within trench width  615  of grid array trench  610   a . Endpoint  640   b  of dicing street  630  is aligned such that it is located within trench width  615  of grid array trench  610 . As shown in  FIG. 6 , trench width  615  of grid array trenches  610   a  and  610   b  is significantly narrower than street width  635  of dicing street  630 . As also shown in  FIG. 6 , dicing street  630  may include a region which includes substrate  601  as well as sacrificial III-Nitride body  640  and sacrificial device layer  642 . In the present implementation, sacrificial III-Nitride body  640  and sacrificial device layer  642  may be formed simultaneously with III-Nitride body  620  and device layer  622 . However, sacrificial III-Nitride body  640  and sacrificial device layer  642  are not components of III-Nitride devices  624 . Each III-Nitride device  624  includes III-Nitride body  620  and device layer  622 . 
     Referring now to  FIG. 7 ,  FIG. 7  illustrates a cross-sectional side view of region  706  having III-Nitride device  724 , according to an implementation disclosed in the present application. III-Nitride device  724  may correspond to III-Nitride device  624  of region  606  in  FIG. 6 . As shown in  FIG. 7 , substrate  701 , III-Nitride body  720 , and device layer  722  may correspond respectively to substrate  201 , III-Nitride body  220 , and device layer  222  of  FIGS. 2A and 2B . III-Nitride device  724  may have device width  770 , and die width  780 . Specifically, device width  770  is narrower than die width  780 .