Abstract:
There is disclosed a sample-and-hold circuit. An operational amplifier includes an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. First and second groups of capacitors are operated in first to third modes periodically. Positive and negative input signals are input to charge an electric charge in the first mode, electric charge are held while positive and negative output signals are output from the operational amplifier by connecting between the inverting input terminal and the non-inverting output terminal and by connecting between the non-inverting input terminal and the inverting output terminal in the second mode, and electric charge are discharged in the third mode. Second group of capacitors shifts to the third mode when first group of capacitors is in the first or second mode, and shift to the first or second mode when first group of capacitors is in the third mode.

Description:
CROSSREFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-135758, filed on May 23, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a sample-and-hold circuit and a pipeline analog-to-digital converter. 
         [0004]    2. Description of the Related Art 
         [0005]    A sample-and-hold (S/H) circuit is a circuit to sample and hold a input signal from a input stage. The S/H circuit includes a switch, a capacitor, and an operational amplifier. The S/H circuit samples and holds the input signal by switching. One terminal of the capacitor is connected to an input terminal of the operational amplifier, and the other terminal of the capacitor is connected to either the input stage which supplies the input signal or an output terminal of the operational amplifier through the switch. 
         [0006]    The other terminal of the capacitor is connected to the input stage through the switch during sampling the input signal (hereinafter, referred to as “sample mode”). The capacitor is charged according to a voltage of the input signal from the input stage. On the other hand, the other terminal of the capacitor is connected to the output terminal of the operational amplifier holding the input signal (hereinafter, referred to as “hold mode”). During the hold mode, the capacitor keeps to hold the electric charge which is charged in the sample mode. The sample mode and the hold mode are switched alternately in the S/H circuit. It means that the S/H circuit samples and holds the input signal periodically. 
         [0007]    A pipeline analog-to-digital converter (hereinafter, referred to as “pipeline A/D converter”) includes the S/H circuit and cascaded convert stages. Each convert stage has a multiplying digital-to-analog converter (hereinafter, referred to as “MDAC”). The MDAC is also one of the S/H circuits. The MDAC has almost same circuit architecture as the S/H circuit, which includes a switch, a capacitor, and an operational amplifier. The MDAC samples and holds an analog input signal from a previous convert stage as same as the S/H circuit. In addition to the MDAC, each convert stage also has a comparator to convert the analog input signal to a digital input signal. 
         [0008]    Both the S/H circuit in the pipeline A/D converter and the S/H circuit in each convert stage (MDAC) realize a sampling of the input signal by charging the capacitor. For example, the operational amplifier in the MDAC of a convert stage is used to charge the capacitor in the MDAC of the next convert stage. It is known that the consumption power of the operational amplifier is relatively large in the total consumption of the pipeline A/D converter. 
         [0009]    Because the S/H circuit in the pipeline A/D converter and the S/H circuit in each convert stage (MDAC) sample and hold the input signal continuously, the electric charge which have been held during the hold mode may still remain in the capacitor when the sample mode starts. Therefore, in each sample mode, the capacitor may be charged or discharged an amount of electric charge according to a voltage of the input signal which has a range from minimum to maximum or from maximum to minimum. 
         [0010]    One of the conventional pipeline A/D converters is disclosed by K. Honda et Al. “A 14b Low-power Pipelined A/D Converter Using a Pre-charging Technique”, Dig. Symp. VLSI Circuits, pp. 196-197, June 2007. In this reference, a pipeline A/D converter does not sample and hold an input signal continuously, and discharge the electric charge which has been held in the capacitors before sampling the input signal. Since the pipeline A/D converter discharge the electric charge to half amount of the maximum capacitance of each capacitor once, it may not need to charge from 0 volt to maximum voltage or discharge from maximum voltage to 0 volt in the next sample mode. This means the pipeline A/D converter may charge or discharge only half amount of the maximum capacitance of each capacitor. Therefore, the pipeline A/D converter can decrease amount of the electric charge which is required to charge to each capacitor at once in the sample mode. 
         [0011]    However, the pipeline A/D converter in the reference needs a time to discharge the electric charge from the capacitors in addition to the time to be required for sampling and holding the input signal. Therefore, the time for sampling and holding is shortened to keep the time for discharging the electric charge. As a result, the capacitors have to discharge the electric charge in a short time before sampling the input signal. 
       SUMMARY OF THE INVENTION 
       [0012]    According to one aspect of the invention, a sample-and-hold circuit comprises: 
         [0013]    an operational amplifier including an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal; and 
         [0014]    a first and second groups of capacitors each being operated in first to third modes periodically, wherein 
         [0000]    positive and negative input signals being input to charge an electric charge in the first mode,
 
the electric charge being held while positive and negative output signals being output from the operational amplifier by connecting between the inverting input terminal and the non-inverting output terminal and by connecting between the non-inverting input terminal and the inverting output terminal in the second mode, and the electric charge being discharged in the third mode;
 
         [0015]    wherein 
         [0000]    the second group of capacitors shifts to the third mode when the first group of capacitors is in the first or second mode, and shift to the first or second mode when the first group of capacitors is in the third mode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIG. 1  is a block diagram showing a S/H circuit in the first phase according to the first embodiment. 
           [0017]      FIG. 2  is a block diagram showing the S/H circuit in the second phase. 
           [0018]      FIG. 3  is a block diagram showing the S/H circuit in the third phase. 
           [0019]      FIG. 4  is a block diagram showing the S/H circuit in the fourth phase. 
           [0020]      FIG. 5  is a figure explaining a technical point of the S/H circuit shown in  FIGS. 1-4 . 
           [0021]      FIG. 6  is another figure explaining a technical point of the S/H circuit shown in  FIGS. 1-4 . 
           [0022]      FIG. 7  is a block diagram showing an A/D converter according to the second embodiment. 
           [0023]      FIG. 8  is a block diagram showing a convert stage of the A/D converter in the first phase. 
           [0024]      FIG. 9  is a block diagram showing the convert stage of the A/D converter in the second phase. 
           [0025]      FIG. 10  is a block diagram showing the convert stage of the A/D converter in the third phase. 
           [0026]      FIG. 11  is a block diagram showing the convert stage of the A/D converter in the fourth phase. 
           [0027]      FIG. 12  is a figure explaining a technical point of the convert stage shown in  FIGS. 8-11 . 
           [0028]      FIG. 13  is another figure explaining a technical point of the convert stage shown in  FIGS. 8-11 . 
           [0029]      FIG. 14  is a block diagram showing alternate switches for them inside dotted frames in  FIGS. 8-11 . 
           [0030]      FIG. 15  is a block diagram showing a S/H circuit in the first phase according to the third embodiment. 
           [0031]      FIG. 16  is a block diagram showing the S/H circuit in the second phase. 
           [0032]      FIG. 17  is a block diagram showing the S/H circuit in the third phase. 
           [0033]      FIG. 18  is a block diagram showing the S/H circuit in the fourth phase. 
           [0034]      FIG. 19  is a block diagram showing the S/H circuit in the fifth phase. 
           [0035]      FIG. 20  is a block diagram showing the S/H circuit in the sixth phase. 
           [0036]      FIG. 21  is a block diagram showing an A/D converter according to the fourth embodiment. 
           [0037]      FIG. 22  is a block diagram showing a convert stage of the A/D converter in the first phase. 
           [0038]      FIG. 23  is a block diagram showing the convert stage of the A/D converter in the second phase. 
           [0039]      FIG. 24  is a block diagram showing the convert stage of the A/D converter in the third phase. 
           [0040]      FIG. 25  is a block diagram showing the convert stage of the A/D converter in the fourth phase. 
           [0041]      FIG. 26  is a block diagram showing the convert stage of the A/D converter in the fifth phase. 
           [0042]      FIG. 27  is a block diagram showing the convert stage of the A/D converter in the sixth phase. 
           [0043]      FIG. 28  is a block diagram showing another A/D converter according to the fourth embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0044]    The embodiments of the invention will be explained with reference to the accompanying drawings. 
       Description of the First Embodiment 
       [0045]    The first embodiment will explain a S/H circuit (MDAC) in each convert stage. As shown in  FIG. 1 , a S/H circuit in each convert stage includes capacitors  111 A,  112 A (hereinafter, referred to as “first capacitor set”), switches  121 A- 129 A, other capacitors  111 B,  112 B (hereinafter, referred to as “second capacitor set”), other switches  121 B- 129 B, and an operational amplifier  130 . Each of capacitors  111 A,  112 A,  111 B, and  112 B has a same capacitance. 
         [0046]    The S/H circuit realizes several behaviors (such as, a sample mode and a hold mode) by switching due to the switches  121 A- 129 A and  121 B- 129 B. These behaviors are classified in four phases based on connection status of switches as shown in  FIGS. 1-4 , respectively. 
         [0047]    The first phase shown in  FIG. 1  is the sample mode using the first capacitor set. The second phase shown in  FIG. 2  is the hold mode using the first capacitor set. The third phase shown in  FIG. 3  is the sample mode using the second capacitor set. The forth phase shown in  FIG. 4  is the hold mode using the second capacitor set. The S/H circuit in the first embodiment performs the first to fourth phases periodically to sample and hold the input signals Vin+, Vin−. 
         [0048]    The S/H circuit samples input signals Vin+ and Vin− from a input stage (not shown) in the first and third phases. Also, the S/H circuit holds these sampled input signals Vin+, Vin−, and outputs output signals Vout+, Vout− in the second and fourth phase. The signals Vin+, Vin−, Vout+, and Vout− are all analog. Moreover, the minimum voltage of these signals is Vrefm (Vreference-minus), and the maximum voltage is Vrefp (Vreference-plus). The common-mode voltage of the input signals Vin+, Vin− is Vcom (Vcommon-mode=(Vin++Vin−)/2). 
         [0049]    One terminal of the capacitor  111 A is connected to a terminal of the capacitor  112 A through the switches  123 A,  124 A in the first, third and fourth phases, and connected to an inverting input terminal of the operational amplifier  130  through the switch  127 A in the second phase. 
         [0050]    The other terminal of the capacitor  111 A is input the input signal Vin+ through the switch  121 A in the first phase, and connected to a non-inverting output terminal of the operational amplifier  130  through the switch  125 A in the second phase. Also, the other terminal of the capacitor  111 A is connected to the other terminal of the capacitor  112 A through the switch  129 A in the third and fourth phases. 
         [0051]    One terminal of the capacitor  112 A is connected to a terminal of the capacitor  111 A through the switches  124 A,  123 A in the first, third and fourth phases, and connected to a non-inverting input terminal of the operational amplifier  130  through the switch  128 A in the second phase. 
         [0052]    The other terminal of the capacitor  112 A is input the input signal Vin− through the switch  122 A in the first phase, and connected to a inverting output terminal of the operational amplifier  130  through the switch  126 A in the second phase. Also, the other terminal of the capacitor  112 A is connected to the other terminal of the capacitor  111 A through the switch  129 A in the third and fourth phases. 
         [0053]    One terminal of the capacitor  111 B is connected to a terminal of the capacitor  112 B through the switches  123 B,  124 B in the first, second and third phases, and connected to an inverting input terminal of the operational amplifier  130  through the switch  127 B in the fourth phase. 
         [0054]    The other terminal of the capacitor  111 B is input the input signal Vin+ through the switch  121 B in the third phase, and connected to a non-inverting output terminal of the operational amplifier  130  through the switch  125 B in the fourth phase. Also, the other terminal of the capacitor  111 B is connected to the other terminal of the capacitor  112 B through the switch  129 B in the first and second phases. 
         [0055]    One terminal of the capacitor  112 B is connected to a terminal of the capacitor  111 B through the switches  124 B,  123 B in the first, second and third phases, and connected to a non-inverting input terminal of the operational amplifier  130  through the switch  128 B in the fourth phase. The other terminal of the capacitor  112 B is input the input signal Vin− through the switch  122 B in the third phase, and connected to an inverting output terminal of the operational amplifier  130  through the switch  126 B in the fourth phase. Also, the other terminal of the capacitor  112 B is connected to the other terminal of the capacitor  111 B through the switch  129 B in the first and second phases. 
         [0056]    The operational amplifier  130  is a fully differential operational amplifier, including an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The inverting input terminal and the non-inverting output terminal of the operational amplifier  130  are connected each other through the switch  127 A, the capacitor  111 A, and the switch  125 A in the second phase. Also, they are connected each other through the switch  127 B, the capacitor  111 B, and the switch  125 B in the fourth phase. On the other hand, the inverting input terminal and the non-inverting output terminal of the operational amplifier  130  are unconnected by turning off the switches  127 A,  125 A,  127 B,  125 B in the first and third phases. The non-inverting input terminal and the inverting output terminal of the operational amplifier  130  are connected each other through the switch  128 A, the capacitor  112 A, and the switch  126 A in the second phase. Also, they are connected each other through the switch  128 B, the capacitor  112 B, and the switch  126 B in the fourth phase. On the other hand, the non-inverting input terminal and the inverting output terminal of the operational amplifier  130  are unconnected by turning off the switches  128 A,  126 A,  128 B,  126 B in the first and third phases. 
         [0057]    The behaviors of the S/H circuit in the first embodiment will be explained according to each phase. As shown in  FIG. 1 , the S/H circuit in the first phase is operating in the sample mode. The capacitors  111 A,  112 A sample the input signals Vin+, Vin− by turning on the switches  121 A- 124 A and turning off the switches  125 A- 129 A. 
         [0058]    On the other hand, the capacitors  111 B,  112 B do not sample the input signals Vin+, Vin−. Both terminals of each of capacitors  111 B,  112 B are connected by turning on the switches  123 B,  124 B,  129 B and turning off the switches  121 B,  122 B,  125 B- 128 B. As a result, the voltages at both terminals of each of capacitors  111 B,  112 B become equal. Because the capacitances of the capacitors  111 B,  112 B are equal, electric charge in the capacitors  111 B,  112 B are discharged to be an average voltage at all terminals of capacitors  111 B,  112 B. The effect of this discharge will be described later. 
         [0059]    As shown in  FIG. 2 , the S/H circuit in the second phase is operating in the hold mode. The capacitors  111 A,  112 A hold the input signals Vin+, Vin− which are sampled in the first phase by turning off the switches  121 A- 124 A,  129 A. Moreover, these held input signals Vin+, Vin− are output as output signals Vout+, Vout− by turning on the switches  125 A- 128 A. Other switches  121 B- 128 B operate as same as the first phase. 
         [0060]    As shown in  FIG. 3 , the S/H circuit in the third phase is operating in the sample mode. The capacitors  111 B,  112 B sample the input signals Vin+, Vin− by turning on the switches  121 B- 124 B and turning off the switches  125 B- 129 B. 
         [0061]    On the other hand, the capacitors  111 A,  112 A do not sample the input signals Vin+, Vin−. Both terminals of each of capacitors  111 A,  112 A are connected by turning on the switches  123 A,  124 A,  129 A and turning off the switches  121 A,  122 A,  125 A- 128 A. As a result, electric charge in the capacitors  111 A,  112 A are discharged to be an average voltage at all terminals of capacitors  111 A,  112 A. For example, the capacitor  111 A holds more or less electric charge than the capacitor  112 A in the second phase, the voltage at all terminals of capacitors  111 A,  112 A become equal to the common-mode voltage Vcom of the input signals Vin+ and Vin−. 
         [0062]    As shown in  FIG. 4 , the S/H circuit in the fourth phase is operating in the hold mode. The capacitors  111 B,  112 B hold the input signals Vin+, Vin− which are sampled in the third phase by turning off the switches  121 B- 124 B,  129 B. Moreover, these held input signals Vin+, Vin− are output as output signals Vout+, Vout− by turning on the switches  125 B- 128 B. Other switches  121 A- 128 A operate as same as the third phase. 
         [0063]    The S/H circuit in the first embodiment performs the first to fourth phases periodically to sample and hold the input signals Vin+, Vin−. As mentioned above, the capacitors  111 B,  112 B in the first and second phases and the capacitors  111 A,  112 A in the third and fourth phases do not sample and hold the input signals Vin+, Vin−. This means that the first capacitor set (including capacitors  111 A,  112 A) and the second capacitor set (including capacitors  111 B,  112 B) are alternately used to sample and hold the input signals Vin+, Vin− in the S/H circuit. 
         [0064]    Next, we will describe the effect of the using two sets of the capacitors, and performing sampling, holding, and discharging, periodically. 
         [0065]    As shown in  FIG. 5  and  FIG. 6 , a conventional S/H circuit has one set of capacitors including capacitors  11 ,  12 . The conventional S/H circuit samples and holds input signals Vin+, Vin− using the set of capacitors continuously. As shown in  FIG. 5 , in the sample mode, one terminal of the capacitor  11  is connected to one terminal of capacitor  12  through the switches  23 ,  24 . The other terminal of the capacitor  11  is input the input signal Vin+ through the switch  21 , and the other terminal of the capacitor  12  is input the input signal Vin− through the switch  22 . The capacitors  11 ,  12  have a same capacitance. 
         [0066]    As shown in  FIG. 6 , in the hold mode, the other terminal of the capacitor  11  is unconnected with the input signal Vin+ by turning off the switch  21 , and the other terminal of the capacitor  12  is also unconnected with the input signal Vin− by turning off the switch  22 . The inverting input terminal of the operational amplifier  30  is connected to the non-inverting output terminal through the capacitor  11  and the switch  25 . Also, the non-inverting input terminal of the operational amplifier  30  is connected to the inverting output terminal through the capacitor  12  and the switch  26 . The output signal Vout+ is output from the inverting input terminal of the operational amplifier  30 , which is almost same as the input signal Vin+ sampled by the capacitor  11  in the sample mode. The output signal Vout− is output from the non-inverting input terminal of the operational amplifier  30 , which is almost same as the input signal Vin− sampled by the capacitor  12  in the sample mode. 
         [0067]    Because the conventional S/H circuit has only one set of the capacitors, the electric charge which have been held during the hold mode may still remain in the capacitors  11 ,  12  when the next sample mode starts. An example case, that the input signal Vin+ is Vrefp and Vin− is Vrefm in the sample mode (Vrefm&lt;Vrefp), will be considered. The capacitor  11  is charged electric charge from the input stage to be Vcom at a terminal and Vrefp at the other terminal. The capacitor  12  is also charged electric charge from the input stage to be Vcom at a terminal and Vrefm at the other terminal. The electric charge in the capacitors  11 ,  12  are held during the next hold mode. 
         [0068]    In the next sample mode, for example, the input signal Vin+ is Vrefm, and Vin− is Vrefp. The capacitor  11  is charged electric charge from the input stage to be Vcom at a terminal and Vrefm at the other terminal. The capacitor  12  is also charged electric charge from the input stage to be Vcom at a terminal and Vrefp at the other terminal. Because the electric charge in the capacitors  11 ,  12  are held during the previous hold mode, the capacitor  11  needs to discharge to be Vrefm from Vrefp at the other terminal. Also, the capacitor  12  needs to charge to be Vrefp from Vrefm at the other terminal. 
         [0069]    On the other hand, the S/H circuit in the first embodiment discharges the capacitors once before the sample mode. For example, the capacitors  111 A,  112 A in the third and forth phases discharge electric charge which have been held during the second phase by connecting between both terminals of the capacitors  111 A and  112 A. Then, the next first phase will start. Moreover, the capacitors  111 B,  112 B in the first and second phases discharge electric charge switch have been held during the fourth phase by connecting between both terminals of the capacitors  111 B and  112 B. Then, the next third phase will start. The voltages at all terminals of capacitors  111 A,  112 A,  111 B,  112 B become Vcom before the sample mode, that is first and third phases, starts. 
         [0070]    Therefore, the amount of electric charge which is required to charge the capacitors  111 A,  112 A,  111 B,  112 B are almost half compared with the conventional S/H circuit. For example, when the capacitors  11 ,  12 ,  111 A,  112 A,  111 B,  112 B have all same capacitance “C”, the amount of electric charge for charging the capacitors  11 ,  12  in the conventional S/H circuit could be “C|Vrefp−Vrefm|”. On the other hand, the amount of electric charge for charging the capacitors  111 A,  112 A,  111 B,  112 B in the S/H circuit of the first embodiment could be “C|Vrefp−Vcom|”. Since the common-mode voltage. Vcom equals to an average of Vrefp and Vrefm, the amount of electric charge for charging may be “C|Vrefp−Vrefm|/2” in the S/H circuit of the first embodiment. 
         [0071]    As described above, the S/H circuit in the first embodiment has two sets of capacitors. One set of capacitors discharges while the other set of capacitors are performing sampling and holding. Therefore, the S/H circuit in the first embodiment decreases the amount of electric charge to be used for charge compared with the conventional S/H circuit. As a result, the S/H circuit in the first embodiment decreases the consumption power. 
       Description of the Second Embodiment 
       [0072]    The second embodiment will explain an A/D converter using a S/H circuit (MDAC) of the first embodiment. As shown in  FIG. 7 , an A/D converter in the second embodiment is a pipeline A/D converter. The pipeline A/D converter includes a S/H circuit  100  and cascaded N convert stages  200 - 1 , . . . ,  200 -K, . . . ,  200 -N 
         [0073]    The S/H circuit  100  may be same as the S/H circuit in the first embodiment. An analog input signal is sampled by the S/H circuit  100 . Then, the S/H circuit  100  inputs the sampled analog input signal into the first convert stage  200 - 1 . The first convert stage  200 - 1  compares the voltage of the analog input signal with threshold voltages, and converts the analog input signal to a digital output signal obtained according to a result of the comparison between the voltage of the analog input signal and the threshold voltages. The digital output signal may have n bit-wide  1 ) including redundancy bits. For example, n=2 in the second embodiment. Since these digital bits includes 1 bit for redundancy every 2 convert stages in the second embodiment, the digital output signal has 1.5 bit-wide information for each convert stage. Generally, it is expressed as 1.5 bit/stage. In the case of 1.5 bit/stage, value of the digital output signal is any one of “00”/“01”/“11”. To judge a value of digital output signal by comparing the voltage of the analog input signal with threshold voltages, two threshold voltages are used in the second embodiment. Moreover, the first convert stage  200 - 1  outputs an analog residual signal to the second convert stage  200 - 2 . The analog residual signal is also obtained according to the result of the comparison between the voltage of the analog input signal and the threshold voltages. The second convert stage  200 - 2  converts the analog residual signal from the first convert stage  200 - 1  to a digital output signal, and inputs an analog residual signal into the third convert stage  200 - 3 . Other convert stages  200 - 3 , . . . ,  200 -N work as same as the first and second convert stages  200 - 1 ,  200 - 2 . At last, these digital output signals from  200 - 1 , . . . ,  200 -N are combined to obtain a digital signal with Mbit-wide (N≦M≦n×N) without redundancy bits, which means that the pipeline A/D converter has finished an analog to digital conversion. 
         [0074]    Next, we will explain the Kth convert stage  200 -K, which is one of the convert stages  200 - 1 , . . . ,  200 -N in the A/D converter. As shown in  FIG. 8 , the convert stage  200 -K includes capacitors  241 A- 244 A (hereinafter, referred to as “first capacitor set”), other capacitors  241 B- 244 B (hereinafter, referred to as “second capacitor set”), switches  251 A- 264 A, other switches  251 B- 264 B, an operational amplifier  270 , and a comparator  280 . Each of capacitors  241 A- 244 A and  241 B- 244 B has a same capacitance. The capacitors  241 A- 244 A,  241 B- 244 B, the switches  251 A- 264 A,  251 B- 254 B, and the operational amplifier  270  provide for a S/H circuit (MDAC). In  FIGS. 8-11 , input signals Vin+, Vin− are the analog residual signal from the previous convert stage  200 -(K−1), and output signals Vout+, Vout− are the analog residual signal to the next convert stage  200 -(K+1). Vd from the comparator  280  is a digital output signal. The threshold voltages (not shown) are set in the comparator  280 . Moreover, actually, the comparator  280  is connected (not shown in  FIGS. 8-11 ) to the switches  259 A,  260 A,  259 B and  260 B to indicate value of the digital output signal Vd. 
         [0075]    The convert stage  200 -K realizes several behaviors (such as, a sample mode and a hold mode) by switching due to the switches  251 A- 264 A and  251 B- 264 B. These behaviors are classified in four phases based on connection status of switches as shown in  FIGS. 8-11 , respectively. The first phase shown in  FIG. 8  is the sample mode using the first capacitor set. The second phase shown in  FIG. 9  is the hold mode using the first capacitor set. The third phase shown in  FIG. 10  is the sample mode using the second capacitor set. The forth phase shown in  FIG. 11  is the hold mode using the second capacitor set. The convert stage in the second embodiment performs the first to fourth phases periodically to sample and hold the input signals Vin+, Vin−. 
         [0076]    The convert stage  200 -K samples the input signals Vin+, Vin− in the first and third phases. Moreover, the convert stage  200 -K converts input signals Vin+, Vin− from the previous convert stage  200 -(K−1) to a digital output signal Vd by comparing with the threshold voltages in the comparator  280  in the first and third phases. 
         [0077]    On the other hand, the convert stage  200 -K holds the input signals Vin+, Vin−, which are sampled in the first and third phases, in the second and forth phases. Also, the convert stage  200 -K outputs the output signals Vout+, Vout− into the next convert stage  200 -(K+1) in the second and forth phases. These output signals Vout+, Vout− are analog residual signals between the input signals Vin+, Vin− and the reference voltages from the switches  259 A,  260 A,  259 B, and  260 B. The reference voltages are determined according to the value of the digital output signal Vd from the comparator  280 . Adjacent convert stages are in different phases at a given time. For example, when the convert stage  200 -K is in the first or third phase, the previous convert stage  200 -(K−1) and the next convert stage  200 -(K+1) are in the second or fourth phase. Then, when the convert stage  200 -K is in the second or fourth phase, the previous convert stage  200 -(K−1) and the next convert stage  200 -(K+1) are in the first or third phase. 
         [0078]    The signals Vin+, Vin−, Vout+, and Vout− are all analog. Moreover, the minimum voltage of these signals is Vrefm (Vreference-minus), and the maximum voltage is Vrefp (Vreference-plus). The common-mode voltage of the input signals Vin+, Vin− is Vcom (Vcommon-mode=(Vin++Vin−)/2). 
         [0079]    One terminal of the capacitor  241 A is connected to a terminal of the capacitor  243 A. Similarly, one terminal of the capacitors  242 A is connected to a terminal of the capacitor  244 A. The connection point of the capacitors  241 A and  243 A is connected to the connection point of the capacitors  242 A and  244 A through the switches  253 A,  254 A in the first, third and fourth phases. Also, the connection point of the capacitors  241 A and  243 A is connected to an inverting input terminal of the operational amplifier  270  through the switch  261 A in the second phase. The other terminal of the capacitor  241 A is input the input signal Vin+ through the switch  251 A in the first phase, and connected to a non-inverting output terminal of the operational amplifier  270  through the switch  255 A in the second phase. Also, the other terminal of the capacitor  241 A is connected to the other terminal of the capacitor  242 A through the switch  264 A in the third and fourth phases. The other terminal of the capacitor  243 A is input the input signal Vin+ through the switch  257 A in the first phase, and input a reference voltage through the switch  259 A in the second phase. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  259 A according to the value of digital output signal Vd. Since the digital output signal Vd could be three different values “00”/“01”/“11”, the reference voltage has three choices Vrefp, Vcom, Vrefm. Also, the other terminal of the capacitor  243 A is connected to the other terminal of the capacitor  244 A through the switch  263 A in the third and fourth phases. 
         [0080]    The connection point of the capacitors  242 A and  244 A is connected to the connection point of the capacitors  241 A and  243 A through the switches  254 A,  253 A in the first, third and fourth phases. Also, the connection point of the capacitors  242 A and  244 A is connected to a non-inverting input terminal of the operational amplifier  270  through the switch  262 A in the second phase. The other terminal of the capacitor  242 A is input the input signal Vin− through the switch  252 A in the first phase, and connected to a inverting output terminal of the operational amplifier  270  through the switch  256 A in the second phase. Also, the other terminal of the capacitor  242 A is connected to the other terminal of the capacitor  241 A through the switch  264 A in the third and fourth phases. 
         [0081]    The other terminal of the capacitor  244 A is input the input signal Vin− through the switch  258 A in the first phase, and input the reference voltage through the switch  260 A in the second phase. Also, the other terminal of the capacitor  244 A is connected to the other terminal of the capacitor  243 A through the switch  263 A in the third and fourth phases. 
         [0082]    One terminal of the capacitor  241 B is connected to a terminal of the capacitor  243 B. Similarly, one terminal of the capacitors  242 B is connected to a terminal of the capacitor  244 B. The connection point of the capacitors  241 B and  243 B is connected to the connection point of the capacitors  242 B and  244 B through the switches  253 B,  254 B in the first, second and third phases. Also, the connection point of the capacitors  241 B and  243 B is connected to an inverting input terminal of the operational amplifier  270  through the switch  261 B in the fourth phase. The other terminal of the capacitor  241 B is connected to the other terminal of the capacitor  242 B through the switch  264 B in the first and second phases, and input the input signal Vin+ through the switch  251 B in the third phase. Also, the other terminal of the capacitor  241 B is connected to a non-inverting output terminal of the operational amplifier  270  through the switch  255 B in the fourth phase. The other terminal of the capacitor  243 B is connected to the other terminal of the capacitor  244 B through the switch  263 B in the first and second phases, and input the input signal Vin+ through the switch  257 B in the third phase. Also, the other terminal of the capacitor  243 B is input a reference voltage through the switch  259 B in the fourth phase. 
         [0083]    The connection point of the capacitors  242 B and  244 B is connected to the connection point of the capacitors  241 B and  243 B through the switches  254 B,  253 B in the first, second and third phases. Also, the connection point of the capacitors  242 B and  244 B is connected to a non-inverting input terminal of the operational amplifier  270  through the switch  262 B in the fourth phase. The other terminal of the capacitor  242 B is connected to the other terminal of the capacitor  241 B through the switch  264 B in the first and second phases, and input the input signal Vin− through the switch  252 B in the third phase. Also, the other terminal of the capacitor  241 B is connected to an inverting output terminal of the operational amplifier  270  through the switch  256 B in the fourth phase. 
         [0084]    The other terminal of the capacitor  244 B is connected to the other terminal of the capacitor  243 B through the switch  263 B in the first and second phases, and input the input signal Vin− through the switch  258 B in the third phase. Also, the other terminal of the capacitor  244 B is input a reference voltage through the switch  260 B in the fourth phase. 
         [0085]    The operational amplifier  270  is a fully differential operational amplifier, including an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The inverting input terminal and the non-inverting output terminal of the operational amplifier  270  are connected each other through the switch  261 A, the capacitor  241 A, and the switch  255 A in the second phase. Also, they are connected each other through the switch  261 B, the capacitor  241 B, and the switch  255 B in the fourth phase. On the other hand, the inverting input terminal and the non-inverting output terminal of the operational amplifier  270  are unconnected by turning off the switches  261 A,  255 A,  261 B,  255 B in the first and third phases. The non-inverting input terminal and the inverting output terminal of the operational amplifier  270  are connected each other through the switch  262 A, the capacitor  242 A, and the switch  256 A in the second phase. Also, they are connected each other through the switch  262 B, the capacitor  242 B, and the switch  256 B in the fourth phase. On the other hand, the non-inverting input terminal and the inverting output terminal of the operational amplifier  270  are unconnected by turning off the switches  262 A,  256 A,  262 B,  256 B in the first and third phases. 
         [0086]    The comparator  280  in the first and third phases compares the difference voltage between the input signals Vin+ and Vin− from the previous convert stage with the threshold voltages, and outputs a digital output signal Vd according to the result of the comparison between the difference voltage between the input signals Vin+, Vin− and the threshold voltages. One of the voltages Vrefp, Vcom, Vrefm is selected as a reference voltage in each of switches  259 A,  260 A,  259 B,  260 B according to value of the digital output signal Vd in the second and fourth phases. The reference voltages of the switches  259 A,  260 A are added to at the other terminals of the capacitors  243 A,  244 A, respectively, in the second phase. Also, the reference voltages of the switches  259 B,  260 B are added to at the other terminals of the capacitors  243 B,  244 B, respectively, in the fourth phase. 
         [0087]    Next, the behaviors of the convert stage  200 -K will be explained according to each phase. As shown in  FIG. 8 , the convert stage  200 -K in the first phase is operating in the sample mode. The convert stage  200 -K samples the input signals Vin+, Vin− from the previous convert stage  200 -(K−1) in the first phase. The capacitors  241 A,  243 A sample the input signal Vin+, and the capacitors  242 A,  244 A sample the input signal Vin− by turning on the switches  251 A- 254 A,  257 A,  258 A and turning off the switches  255 A,  256 A,  259 A- 264 A. Moreover, the comparator  280  compares the difference voltage between the input signals Vin+ and Vin− with the threshold voltages to obtain the digital output signal Vd (n bit) in the first phase. 
         [0088]    On the other hand, the capacitors  241 B- 244 B do not sample the input signals Vin+, Vin− during the first phase. One terminal of each of capacitors  241 B- 244 B is connected to other three by turning on the switches  253 B,  254 B and turning off the switches  261 B,  262 B. The other terminals of the capacitors  241 B,  242 B are connected each other by turning on the switch  264 B and turning off the switches  251 B,  252 B,  255 B- 260 B. The other terminals of the capacitors  243 B,  244 B are connected each other by turning on the switches  263 B and turning off the switches  251 B,  252 B,  255 B- 260 B. As a result, the voltages at both terminals of each of capacitors  241 B,  242 B,  243 B,  244 B become equal. Because the capacitances of the capacitors  241 B,  242 B,  243 B,  244 B are equal, electric charge in the capacitors  241 B,  242 B are discharged to be an average voltage at all terminals of capacitors  241 B,  242 B. Similarly, electric charges in the capacitors  243 B,  244 B are discharged to be an average voltage at all terminals of capacitors  243 B,  244 B. At last, since the voltages at all terminals of capacitors  241 B- 244 B become equal, electric charge in the capacitors  241 B- 244 B are all discharged to be an average voltage at all terminals of capacitors  241 B- 244 B. The effect of these discharges will be described later. 
         [0089]    As shown in  FIG. 9 , the convert stage  200 -K in the second phase is operating in the hold mode. The capacitors  241 A- 244 A hold the input signals Vin+, Vin− which are sampled in the first phase by turning off the switches  251 A,  252 A,  257 A,  258 A. Moreover, reference voltages are input to the other terminals of capacitors  243 A,  244 A through the switches,  259 A,  260 A in the second phase. One of the reference voltages are selected according to the digital output signal Vd generated in the first phase. Therefore, flows of the electric charge from the capacitors  241 A- 244 A are caused, and the residual signals are output as output signals Vout+, Vout−. The residual signal is a signal which is generated by voltage difference between the input signals Vin+, Vin− and the reference voltages. These output signals Vout+, Vout− are used as the input signals Vin+, Vin− in the next convert stage  200 -(K+1). Other switches  251 B- 264 B operate as same as the first phase. 
         [0090]    As shown in  FIG. 10 , the convert stage  200 -K in the third phase is operating in the sample mode. The convert stage  200 -K samples the input signals Vin+, Vin− from the previous convert stage  200 -(K−1) in the third phase. The capacitors  241 B,  243 B sample the input signal Vin+, and the capacitors  242 B,  244 B sample the input signal Vin− by turning on the switches  251 B- 254 B,  257 B,  258 B and turning off the switches  255 B,  256 B,  259 B- 264 B. Moreover, the comparator  280  compares the difference voltage between the input signals Vin+ and Vin− with the threshold voltages to obtain the digital output signal Vd. 
         [0091]    On the other hand, the capacitors  241 A- 244 A do not sample the input signals Vin+, Vin−. All terminals of capacitors  241 A- 244 A are connected by turning on the switches  253 A,  254 A,  263 A,  264 A and turning off the switches  251 A,  252 A,  255 A- 262 A. As a result, electric charges in the capacitors  241 A- 244 A are discharged to be an average voltage at all terminals of capacitors  241 A- 244 A. Although any one of the capacitors  241 A- 244 A holds more or less electric charge than other three capacitors in the second phase, the voltage at all terminals of capacitors  241 A- 244 A become equal to the common-mode voltage Vcom of the input signals Vin+ and Vin−. 
         [0092]    As shown in  FIG. 11 , the convert stage  200 -K in the fourth phase is operating in the hold mode. The capacitors  241 B- 244 B hold the input signals Vin+, Vin− which are sampled in the third phase by turning off the switches  251 B,  252 B,  257 B,  258 B. Moreover, the reference voltages are input to other terminals of capacitors  243 B,  244 B through the switches  259 B,  260 B in the fourth phase. The reference voltages are according to the digital output signal Vd generated in the third phase. Therefore, flows of the electric charge from the capacitors  241 B- 244 B are caused, and the residual signals are output as output signals Vout+, Vout−. The residual signal is a signal which is generated by voltage difference between the input signals Vin+, Vin− and the reference voltages. These output signals Vout+, Vout− are used as the input signals Vin+, Vin− in the next convert stage  200 -(K+1). Other switches  251 A- 264 A operate as same as the third phase. 
         [0093]    The convert stage  200 -K in the second embodiment performs the first to fourth phases periodically to sample and hold the input signals Vin+, Vin−, and to output the digital output signal Vd. Moreover, the convert stage  200 -K outputs the residual signals as the output signals Vout+, Vout− into next convert stage  200 -(K+1). As mentioned above, the capacitors  241 B- 244 B in the first and second phases and the capacitors  241 A- 244 A in the third and fourth phases do not sample and hold the input signals Vin+, Vin−. This means that the first capacitor set (including capacitors  241 A- 244 A) and the second capacitor set (including capacitors  241 B- 244 B) are alternately used to sample and hold the input signals Vin+, Vin− in the convert stage  200 -K 
         [0094]    Next, we will describe the effect of the using two sets of the capacitors, and performing sampling, holding, and discharging, periodically. 
         [0095]    As shown in  FIG. 12  and  FIG. 13 , a conventional convert stage has one set of capacitors including capacitors  41 - 44 . The conventional convert stage samples the input signals Vin+, Vin− using the set of capacitors continuously. As shown in  FIG. 12 , in the sample mode, one terminal of each of the capacitors  41 - 44  is connected to one terminal of other capacitors. The other terminal of each of the capacitors  41 ,  43  is input the input signal Vin+ through the switches  51 ,  57 , and the other terminal of each of the capacitors  42 ,  44  is input the input signal Vin− through the switches  52 ,  58 . The capacitors  41 - 44  have a same capacitance. A comparator  80  compares the input signals Vin+, Vin− with threshold voltages, and outputs the digital output signal Vd. 
         [0096]    As shown in  FIG. 13 , when the conventional convert stage  200 -K outputs the output signals Vout+, Vout− to the next convert stage  200 -(K+1), the other terminal of each of the capacitors  41 ,  43  is unconnected with the input signal Vin+ by turning off the switches  51 ,  57 , and the other terminal of each of the capacitors  42 ,  44  is also unconnected with the input signal Vin− by turning off the switches  42 ,  44 . The inverting input terminal of the operational amplifier  70  is connected to the non-inverting output terminal through the capacitor  41  and the switch  55 . Also, the non-inverting input terminal of the operational amplifier  70  is connected to the inverting output terminal through the capacitor  42  and the switch  56 . The reference voltages, which are selected according to the digital output signal Vd, is input to the capacitors  43 ,  44  through the switches  59 ,  60 . The output signal Vout+ is output from the inverting input terminal of the operational amplifier  70 . The output signal Vout− is output from the non-inverting input terminal of the operational amplifier  70 . These output signals Vout+, Vout− are residual signals generated by voltage difference between the input signals Vin+, Vin− and the reference voltages, and input into the next convert stage  200 -(K+1). 
         [0097]    Because the conventional convert stage has only one set of the capacitors, the electric charge which have been held during the hold mode may still remain in the capacitors  41 - 44  when the next sample mode starts. An example case, that the input signal Vin+ is Vrefp and Vin− is Vrefm in the sample mode (Vrefm&lt;Vrefp), will be considered. The capacitors  41 ,  43  are charged electric charge from an operational amplifier in the previous convert stage to be Vcom at a terminal and Vrefp at the other terminal. The capacitors  42 ,  44  are also charged electric charge from the operational amplifier in the previous convert stage to be Vcom at a terminal and Vrefm at the other terminal. Therefore, the output signal Vout+ is Vrefp, and the output signal Vout− is Vrefm in  FIG. 13 . 
         [0098]    In the next sample mode, for example, the input signal Vin+ is Vrefm, and Vin− is Vrefp from the previous convert stage. The capacitors  41 ,  43  are charged electric charge from the operational amplifier in the previous convert stage to be Vcom at a terminal and Vrefm at the other terminal. The capacitors  42 ,  44  are also charged electric charge from the operational amplifier in the previous convert stage to be Vcom at a terminal and Vrefp at the other terminal. Because the electric charge in the capacitors  41 - 44  are held during the previous hold mode, the capacitors  41 ,  43  needs to discharge to be Vrefm from Vrefp at the other terminal. Also, the capacitors  42 ,  44  need to charge to be Vrefp from Vrefm at the other terminal. 
         [0099]    The convert stage of the A/D converter in the second embodiment discharges the capacitors once before the sample mode. For example, the capacitors  241 A- 244 A in the third and forth phases discharge electric charge which have been held during the second phase. Moreover, the capacitors  241 B- 244 B in the first and second phases discharge electric charge which have been held during the fourth phase. The voltages at all terminals of capacitors  241 A- 244 A,  241 B- 244 B become Vcom before the sample mode, that is first and third phases, starts. Therefore, the amount of electric charge which is required to charge the capacitors  241 A- 244 A,  241 B- 244 B are almost half compared with the conventional convert stage. 
         [0100]    As described above, the convert stage of the A/D converter in the second embodiment has two sets of capacitors. One set of capacitors discharges while the other set of capacitors are performing sampling and holding. Therefore, the A/D converter in the second embodiment decreases the amount of electric charge to be used for charge compared with the conventional A/D converter. As a result, the A/D converter in the second embodiment decreases the consumption power. 
         [0101]    The switches  263 A,  264 A inside the dotted frame in  FIGS. 8-11  could be replaced with the switches  263 - 264  inside the dotted frame in  FIG. 14 . Similarly, the switches  263 B,  264 B inside the dotted frame in  FIGS. 8-11  could also be replaced with the switches  263 - 264  inside the dotted frame in  FIG. 14 . All switches  263 - 266  are turned on/off simultaneously. The advantages of using switches  265 ,  266  in addition to switches  263 ,  264  are described below. 
         [0102]    In the second embodiment, all capacitors  241 - 244  have a same capacitance. However, actually, the capacitances of the capacitors  241 - 244  may not be equal because of a distortion in the manufacturing process. Because the amounts of electric charge in the capacitors  241 - 244  are different when they have different capacitances, it may be difficult to discharge to completely average the electric charges in the capacitors  241 - 244 . Since all capacitors  241 - 244  are connected with more branches through switches  265 ,  266 , the electric charges in the capacitors  241 - 244  are averaged more easily by using switches  265 ,  266 . 
       Description of the Third Embodiment 
       [0103]    While we explained a S/H circuit which samples and holds one analog input signal in the first embodiment, we will explain a S/H circuit which samples and holds two analog input signals in the third embodiment. Generally, using two S/H circuits in the first embodiment may be considered to sample and hold two analog input signals. This means that two sets of capacitors are required for each S/H circuit. Therefore, total four sets of capacitors are required. On the other hand, a S/H circuit in the third embodiment uses only three sets of capacitors to sample and hold two analog input signals. 
         [0104]    As shown in  FIG. 15 , a S/H circuit in the third embodiment includes capacitors  311 A,  312 A (hereinafter, referred to as “first capacitor set”), switches  321 A- 329 A, other capacitors  311 B,  312 B (hereinafter, referred to as “second capacitor set”), other switches  321 B- 329 B, other capacitors  311 C,  312 C (hereinafter, referred to as “third capacitor set”), other switches  321 C- 329 C, and an operational amplifier  330 . Each of capacitors  311 A,  312 A,  311 B,  312 B,  311 C, and  312 C has a same capacitance. 
         [0105]    The S/H circuit samples and holds two analog input signals. The S/H circuit realizes several behaviors (such as, a sample mode and a hold mode) by switching due to the switches  321 A- 329 A,  321 B- 329 B and  321 C- 329 C. These behaviors are classified in six phases based on connection status of switches as shown in  FIGS. 15-20 , respectively. The first phase shown in  FIG. 15  is the sample mode for the input signals Vin_ 1 +, Vin_ 1 − using the first capacitor set, and the hold mode for the input signals Vin_ 2 +, Vin_ 2 − using the second capacitor set. The second phase shown in  FIG. 16  is the hold mode for the input signals Vin_ 1 +, Vin_ 1 − using the first capacitor set, and the sample mode for the input signals Vin_ 2 +, Vin_ 2 − using the third capacitor set.  FIG. 17  is the sample mode for the input signals Vin_ 1 +, Vin_ 1 − using the second capacitor set, and the hold mode for the input signals Vin_ 2 +, Vin_ 2 − using the third capacitor set. The fourth phase shown in  FIG. 18  is the hold mode for the input signals Vin_ 1 +, Vin_ 1 − using the second capacitor set, and the sample mode for the input signals Vin_ 2 +, Vin_ 2 − using the first capacitor set. The fifth phase shown in  FIG. 19  is the sample mode for the input signals Vin_ 1 +, Vin_ 1 − using the third capacitor set, and the hold mode for the input signals Vin_ 2 +, Vin_ 2 − using the first capacitor set. The sixth phase shown in  FIG. 20  is the hold mode for the input signals Vin_ 1 +, Vin_ 1 − using the third capacitor set, and the sample mode for the input signals Vin_ 2 +, Vin_ 2 − using the second capacitor set. The S/H circuit in the first embodiment performs the first to sixth phases periodically to sample and hold the input signals Vin_ 1 +, Vin_ 1 −, Vin_ 2 +, Vin_ 2 −. 
         [0106]    The S/H circuit performs sampling the first input signals Vin_ 1 +, Vin_ 1 − and holding the second input signals Vin_ 2 +, Vin_ 2 −, simultaneously, in the first, third and fifth phases. Also, the S/H circuit performs holding the first input signals Vin_ 1 +, Vin_ 1 − and sampling the second input signals Vin_ 2 +, Vin_ 2 −, simultaneously, in the second, fourth and sixth phases. The first input signals and the second input signals can share an operational amplifier  330  in the S/H circuit, because the first input signals and the second input signals are processed in different modes at a given time. The signals Vin_ 1 +, Vin_ 1 −, Vin_ 2 +, Vin_ 2 −, Vout_ 1 +, Vout_ 1 −, Vout_ 2 +, and Vout_ 2 − are all analog. Moreover, the minimum voltage of these signals is Vrefm, and the maximum voltage is Vrefp. The common-mode voltage of the input signals Vin+, Vin− is Vcom (=(Vin_ 1 +Vin_ 1 −)/2=(Vin_ 2 +Vin_ 2 −)/2). 
         [0107]    One terminal of the capacitor  311 A is connected to a terminal of the capacitor  312 A through the switches  323 A,  324 A in the first, third, fourth and sixth phases, and connected to an inverting input terminal of the operational amplifier  330  through the switch  327 A in the second and fifth phases. The other terminal of the capacitor  311 A is input the input signal Vin_ 1 + through the switch  321 A in the first phase, and connected to a non-inverting output terminal of the operational amplifier  330  through the switch  325 A in the second and fifth phase. Also, the other terminal of the capacitor  311 A is connected to the other terminal of the capacitor  312 A through the switch  329 A in the third and sixth phases, and input the input signal Vin_ 2 + through the switch  321 A in the fourth phase. 
         [0108]    One terminal of the capacitor  312 A is connected to a terminal of the capacitor  311 A through the switches  324 A,  323 A in the first, third, fourth and sixth phases, and connected to a non-inverting input terminal of the operational amplifier  330  through the switch  328 A in the second and fifth phases. The other terminal of the capacitor  312 A is input the input signal Vin_ 1 − through the switch  322 A in the first phase, and connected to a inverting output terminal of the operational amplifier  330  through the switch  326 A in the second and fifth phases. Also, the other terminal of the capacitor  312 A is connected to the other terminal of the capacitor  311 A through the switch  329 A in the third and sixth phases, and input the input signal Vin_ 2 − through the switch  322 A in the fourth phase. 
         [0109]    One terminal of the capacitor  311 B is connected to an inverting input terminal of the operational amplifier  330  through the switch  327 B in the first and fourth phases, and connected to a terminal of the capacitor  312 B through the switches  323 B,  324 B in the second, third, fifth and sixth phases. The other terminal of the capacitor  311 B is connected to a non-inverting output terminal of the operational amplifier  330  through the switch  325 B in the first and fourth phases, and connected to the other terminal of the capacitor  312 B through the switch  329 B in the second and fifth phases. Also, the other terminal of the capacitor  311 B is input the input signal Vin_ 1 + through the switch  321 B in the third phase, and input the input signal Vin_ 2 + through the switch  321 B in the sixth phase. 
         [0110]    One terminal of the capacitor  312 B is connected to a non-inverting input terminal of the operational amplifier  330  through the switch  328 B in the first and fourth phases, and connected to a terminal of the capacitor  311 B through the switches  324 B,  323 B in the second, third, fifth and sixth phases. The other terminal of the capacitor  312 B is connected to an inverting output terminal of the operational amplifier  330  through the switch  326 B in the first and fourth phases, and connected to the other terminal of the capacitor  311 B through the switch  329 B in the second and fifth phases. Also, the other terminal of the capacitor  312 B is input the input signal Vin_ 1 − through the switch  322 B in the third phase, and input the input signal Vin_ 2 − through the switch  322 B in the sixth phase. 
         [0111]    One terminal of the capacitor  311 C is connected to a terminal of the capacitor  312 C through the switches  323 C,  324 C in the first, second, fourth and fifth phases, and connected to an inverting input terminal of the operational amplifier  330  through the switch  327 C in the third and sixth phases. The other terminal of the capacitor  311 C is connected to the other terminal of the capacitor  312 C through the switch  329 C in the first and fourth phases, and input the input signal Vin_ 2 + through the switch  321 C in the second phase. Also, the other terminal of the capacitor  311 C is connected to a non-inverting output terminal of the operational amplifier  330  through the switch  325 C in the third and sixth phases, and input the input signal Vin_ 1 + through the switch  321 C in the fifth phase. 
         [0112]    One terminal of the capacitor  312 C is connected to a terminal of the capacitor  311 C through the switches  324 C,  323 C in the first, second, fourth and fifth phases, and connected to a non-inverting input terminal of the operational amplifier  330  through the switch  328 C in the third and sixth phases. The other terminal of the capacitor  312 C is connected to the other terminal of the capacitor  311 C through the switch  329 C in the first and fourth phases, and input the input signal Vin_ 2 − through the switch  322 C in the second phase. Also, the other terminal of the capacitor  312 C is connected to an inverting output terminal of the operational amplifier  330  through the switch  326 C in the third and sixth phases, and input the input signal Vin_ 1 − through the switch  322 C in the fifth phase. 
         [0113]    The operational amplifier  330  is a fully differential operational amplifier, including an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The inverting input terminal and the non-inverting output terminal of the operational amplifier  330  are connected each other through the switch  327 B, the capacitor  311 B, and the switch  325 B in the first and fourth phases. Also, they are connected each other through the switch  327 A, the capacitor  311 A, and the switch  325 A in the second and fifth phases. Moreover, they are connected each other through the switch  327 C, the capacitor  311 C, and the switch  325 C in the third and sixth phases. 
         [0000]    On the other hand, the non-inverting input terminal and the inverting output terminal of the operational amplifier  330  are connected each other through the switch  328 B, the capacitor  312 B, and the switch  326 B in the first and fourth phases. Also, they are connected each other through the switch  328 A, the capacitor  312 A, and the switch  326 A in the second and fifth phases. Moreover, they are connected each other through the switch  328 C, the capacitor  312 C, and the switch  326 C in the third and sixth phases. 
         [0114]    The behaviors of the S/H circuit in the third embodiment will be explained according to each phase. Note that the behaviors of the S/H circuit in the fourth to sixth phases in  FIGS. 18-20  are same as these in the first to third phases in  FIGS. 15-17 , except that the signals Vin_ 1 +, Vin_Vout_ 1 +, and Vout_ 1 − in the first to third phases are replaced with the signals Vin_ 2 +, Vin_ 2 −, Vout_ 2 +, and Vout_ 2 − in the fourth to sixth phases. Therefore, explanations for the fourth to sixth phases are skipped. 
         [0115]    As shown in  FIG. 15 , the S/H circuit in the first phase is operating in the sample mode for the input signals Vin_ 1 +, Vin_ 1 −. The capacitors  311 A,  312 A sample the input signals Vin_ 1 +, Vin_ 1 − by turning on the switches  321 A- 324 A and turning off the switches  325 A- 329 A. 
         [0116]    At the same time, the S/H circuit in the first phase is operating in the hold mode for the input signals Vin_ 2 +, Vin_ 2 −, which are sampled by the capacitors  311 B,  312 B in the previous sixth phase. The input signals Vin_ 2 +, Vin_ 2 − are held by turning off the switches  321 B- 324 B,  329 B. Then, these held signals Vin_ 2 +, Vin_ 2 − are output as the output signals Vout_ 2 +, Vout_ 2 − by turning on the switches  325 B- 328 B. 
         [0117]    Both terminals of each of capacitors  311 C,  312 C are connected by turning on the switches  323 C,  324 C,  329 C and turning off the switches  321 C,  322 C,  325 C- 328 C. As a result, electric charges in the capacitors  311 C,  312 C are discharged to be an average voltage at all terminals of capacitors  311 C,  312 C. The effect of this discharge has already described in the first embodiment. 
         [0118]    As shown in  FIG. 16 , the S/H circuit in the second phase is operating in the sample mode for the input signals Vin_ 2 +, Vin_ 2 −. The capacitors  311 C,  312 C sample the input signals Vin_ 2 +, Vin_ 2 − by turning on the switches  321 C- 324 C and turning off the switches  325 C- 329 C. 
         [0119]    At the same time, the S/H circuit in the second phase is operating in the hold mode for the input signals Vin_ 1 +, Vin_−, which are sampled by the capacitors  311 A,  312 A in the previous first phase. The input signals Vin_ 1 +, Vin_ 1 − are held by turning off the switches  321 A- 324 A,  329 A. Then, these held signals Vin_ 1 +, Vin_ 1 − are output as the output signals Vout_ 1 +, Vout_ 1 − by turning on the switches  325 A- 328 A. 
         [0120]    Both terminals of each of capacitors  311 B,  312 B are connected by turning on the switches  323 B,  324 B,  329 B and turning off the switches  321 B,  322 B,  325 B- 328 B. As a result, electric charges in the capacitors  311 B,  312 B are discharged to be an average voltage at all terminals of capacitors  311 B,  312 B. 
         [0121]    As shown in  FIG. 17 , the S/H circuit in the third phase is operating in the sample mode for the input signals Vin_ 1 +, Vin_ 1 −. The capacitors  311 B,  312 B sample the input signals Vin_ 1 +, Vin_ 1 − by turning on the switches  321 B- 324 B and turning off the switches  325 B- 329 B. 
         [0122]    At the same time, the S/H circuit in the third phase is operating in the hold mode for the input signals Vin_ 2 +, Vin_ 2 −, which are sampled by the capacitors  311 C,  312 C in the previous second phase. The input signals Vin_ 2 +, Vin_ 2 − are held by turning off the switches  321 C- 324 C,  329 C. Then, these held signals Vin_ 2 +, Vin_ 2 − are output as the output signals Vout_ 2 +, Vout_ 2 − by turning on the switches  325 C- 328 C. 
         [0123]    Both terminals of each of capacitors  311 A,  312 A are connected by turning on the switches  323 A,  324 A,  329 A and turning off the switches  321 A,  322 A,  325 A- 328 A. As a result, electric charges in the capacitors  311 A,  312 A are discharged to be an average voltage at all terminals of capacitors  311 A,  312 A. 
         [0124]    The S/H circuit in the third embodiment discharges the capacitors once before the sample mode. It is same as the S/H circuit in the first embodiment. For example, before sampling the input signals Vin_ 1 +, Vin_ 1 − in the first phase, the capacitors  311 A,  312 A have discharged electric charge which had been held during the fifth phase by connecting between both terminals of the capacitors  311 A and  312 A in the sixth phase. Similarly, before sampling the input signals Vin_ 2 +, Vin_ 2 − in the second phase, the capacitors  311 C,  312 C have discharged electric charge which had been held during the sixth phase by connecting between both terminals of the capacitors  311 C and  312 C in the first phase. Moreover, before sampling the input signals Vin_ 1 +, Vin_ 1 − in the third phase, the capacitors  311 B,  312 B have discharged electric charge which had been held during the first phase by connecting between both terminals of the capacitors  311 B and  312 B in the second phase. Therefore, the S/H circuit in the third embodiment can decreases the consumption power as same as the first embodiment. In addition to the effect, the S/H circuit in the third embodiment realizes reduction of the circuit size. Because the S/H circuit samples and holds two analog input signals with using three sets of capacitors. It can be eliminated one set of capacitors compared with the case of using two S/H circuits which include four sets of capacitors in the first embodiment for two analog input signals. 
       Description of the Fourth Embodiment 
       [0125]    While we explained an A/D converter using a S/H circuit (MDAC) for an analog input signal in the second embodiment, we will explain an A/D converter using a S/H circuit (MDAC) for two analog input signals in the fourth embodiment. An A/D converter in the fourth embodiment is a pipeline A/D converter. As shown in  FIG. 21 , generally, using two A/D converters in the second embodiment may be considered for two analog input signals. The pipeline A/D converter includes a S/H circuit  300 - 1 , cascaded N convert stages  400 - 1 - 1 , . . . ,  400 -K−1, . . . ,  400 -N- 1 , another S/H circuit  300 - 2 , and another cascaded N convert stages  400 - 1 - 2 , . . . ,  400 -K- 2 , . . . ,  400 -N- 2 . The S/H circuit  300 - 1  and the cascaded N convert stages  400 - 1 - 1 , . . . ,  400 -K−1, . . . ,  400 -N- 1  are used for an analog to digital conversion of a first analog input signal. The S/H circuit  300 - 2  and the cascaded N convert stages  400 - 1 - 2 , . . . ,  400 -K- 2 , . . . ,  400 -N- 2  are used for an analog to digital conversion of a second analog input signal. For example, if each convert stage has two sets of capacitors, total four sets of capacitors are required for convert stages  400 -K−1,  400 -K- 2 . On the other hand, A/D converter in the fourth embodiment uses only three sets of capacitors for two analog input signals. Although the convert stages  400 - 1 - 1 , . . . ,  400 -N- 1 , and  400 - 1 - 2 , . . . ,  400 -N- 2  are drawn separately in  FIG. 21 , actually, these convert stages shared a part of components as shown in  FIGS. 22-27 . 
         [0126]    The S/H circuits  300 - 1 ,  300 - 2  may be same as the S/H circuit in the first or third embodiment. In the time=t, the first analog input signal is sampled by the S/H circuit  300 - 1 . Moreover, the S/H circuit  300 - 1  supplies the sampled first analog input signal into the first convert stage  400 - 1 - 1 . The first convert stage  400 - 1 - 1  compares the voltage of the first analog input signal with threshold voltages, and converts the first analog input signal to a first digital output signal obtained according to a result of the comparison between the voltage of the first analog input signal and the threshold voltages. The digital output signal may have n bit-wide (n≧1) including redundancy bits. In the next time=t+1, the first convert stage  400 - 1 - 1  outputs the first analog residual signal to the second convert stage  400 - 2 - 1 . The analog residual signal is also obtained according to the results of the comparison between the voltage of the first analog input signal and the threshold voltages. Similarly, the second analog input signal is sampled by the S/H circuit  300 - 2 . Moreover, the S/H circuit  300 - 2  supplies the sampled second analog input signal into the first convert stage  400 - 1 - 2 . The first convert stage  400 - 1 - 2  compares the voltage of the second analog input signal with threshold voltages, and converts the second analog input signal to a second digital output signal obtained according to a result of the comparison between the voltage of the second analog input signal and the threshold voltages. The digital output signal may also have n bit-wide (n≧1) including redundancy bits. In the same time=t+1, the second convert stage  400 - 2 - 1  converts the first analog residual signal from the first convert stage  400 - 1 - 1  to first digital output signal. Similarly, the first convert stage  400 - 1 - 2  outputs the second analog residual signal to the second convert stage  400 - 2 - 2 . In the next time=t+2, the second convert stage  400 - 2 - 1  outputs the first analog residual signal to the third convert stage  400 - 3 - 1 . Similarly, the second convert stage  400 - 2 - 2  converts the second analog residual signal from the first convert stage  400 - 1 - 2  to second digital output signal. Other convert stages  400 - 3 - 1 , . . . ,  400 -N- 1 , and  400 - 3 - 2 , . . . ,  400 -N- 2  work as same as the first and second convert stages  400 - 1 - 1 ,  400 - 2 - 1 , and  400 - 1 - 2 ,  400 - 2 - 2 . At last, these digital output signals from  400 - 1 - 1 , . . . ,  400 -N- 1 , and  400 - 1 - 2 , . . . ,  400 -N- 2  are combined to obtain first and second digital signals with Mbit-wide (N≦M≦n×N). This means that the pipeline A/D converter has finished analog to digital conversion for the first and second analog input signals. 
         [0127]    Next, we will explain the Kth convert stages  400 -K−1,  400 -K- 2 , which are one of the convert stages  400 - 1 - 1 , . . . ,  400 -N- 1 , and  400 - 1 - 2 , . . . ,  400 -N- 2 , respectively, in the A/D converter. Although the convert stages  400 - 1 - 1 , . . . ,  400 -N- 1 , and  400 - 1 - 2 , . . . ,  400 -N- 2  are separated in  FIG. 21 , actually, these convert stages shared a part of components as shown in  FIGS. 22-27 . Hereinafter, “convert stage  400 -K” means both of “convert stage  400 -K−1” and “convert stage  400 -K- 2 ”. 
         [0128]    As shown in  FIG. 22 , the convert stage  400 -K includes capacitors  441 A- 444 A (hereinafter, referred to as “first capacitor set”), other capacitors  441 B- 444 B (hereinafter, referred to as “second capacitor set”), other capacitors  441 C- 444 C (hereinafter, referred to as “third capacitor set”), switches  451 A- 464 A, other switches  451 B- 464 B, other switches  451 C- 464 C, an operational amplifier  470 , and comparators  481 ,  482 . Each of capacitors  441 A- 444 A,  441 B- 444 B, and  441 C- 444 C has a same capacitance. The capacitors  441 A- 444 A,  441 B- 444 B,  441 C- 444 C, the switches  451 A- 464 A,  451 B- 454 B,  451 C- 464 C and the operational amplifier  470  provide for a S/H circuit (MDAC). In  FIGS. 22-27 , input signals Vin_ 1 +, Vin_Vin_ 2 +, Vin_ 2 − are the analog residual signal from the previous convert stage  400 -(K−1), and output signals Vout_ 2 +, Vout_ 2 −, Vout_ 1 +, Vout_ 1 − are the analog residual signal to the next convert stage  400 -(K+1). Vd_ 1  from the comparator  481  and Vd_ 2  from the comparator  482  are digital output signals. The threshold voltages (not shown) are set in the comparators  481 ,  482 . Moreover, actually, the comparators  481 ,  482  are connected (not shown in  FIGS. 22-27 ) to the switches  459 A,  460 A,  459 B,  460 B,  459 C, and  460 C to indicate value of the digital output signals Vd_ 1 , Vd_ 2 . 
         [0129]    The convert stage  400 -K realizes several behaviors (such as, a sample mode and a hold mode) by switching due to the switches  451 A- 464 A,  451 B- 464 B and  451 C- 464 C. These behaviors are classified in six phases based on connection status of switches as shown in  FIGS. 22-27 , respectively. The first phase shown in  FIG. 22  is the sample mode for the input signals Vin_ 1 +, Vin_ 1 − using the first capacitor set, and the hold mode for the input signals Vin_ 2 +, Vin_ 2 − using the second capacitor set. The second phase shown in  FIG. 23  is the hold mode for the input signals Vin_ 1 +, Vin_ 1 − using the first capacitor set, and the sample mode for the input signals Vin_ 2 +, Vin_ 2 − using the third capacitor set.  FIG. 24  is the sample mode for the input signals Vin_ 1 +, Vin_ 1 − using the second capacitor set, and the hold mode for the input signals Vin_ 2 +, Vin_ 2 − using the third capacitor set. The fourth phase shown in  FIG. 25  is the hold mode for the input signals Vin_ 1 +, Vin_ 1 − using the second capacitor set, and the sample mode for the input signals Vin_ 2 +, Vin_ 2 − using the first capacitor set. The fifth phase shown in  FIG. 26  is the sample mode for the input signals Vin_ 1 +, Vin_ 1 − using the third capacitor set, and the hold mode for the input signals Vin_ 2 +, Vin_ 2 − using the first capacitor set. The sixth phase shown in  FIG. 27  is the hold mode for the input signals Vin_ 1 +, Vin_ 1 − using the third capacitor set, and the sample mode for the input signals Vin_ 2 +, Vin_ 2 − using the second capacitor set. The convert stage in the fourth embodiment performs the first to sixth phases periodically to sample and hold the input signals Vin_ 1 +, Vin_ 1 −, Vin_ 2 +, Vin_ 2 −. 
         [0130]    The convert stage  400 -K samples the input signals Vin_ 1 +, Vin_ 1 − in the first, third and fifth phases. Moreover, the convert stage  400 -K converts input signals Vin_ 1 +, Vin_ 1 − from the previous convert stage  400 -(K−1) to a digital output signal Vd_ 1  by comparing with the threshold voltages in the comparator  281 . Simultaneously, the convert stage  400 -K in the first, third and fifth phases holds the signals Vin_ 2 +, Vin_ 2 −, which were sampled in the second, fourth and sixth phases. Also, the convert stage  400 -K outputs the output signals Vout_ 2 +, Vout_ 2 − to the next convert stage  400 -(K+1) in the first, third and fifth phases. 
         [0131]    On the other hand, the convert stage  400 -K samples the input signals Vin_ 2 +, Vin_ 2 − in the second, fourth and sixth phases. Moreover, the convert stage  400 -K converts input signals Vin_ 2 +, Vin_ 2 − from the previous convert stage  400 -(K−1) to a digital output signal Vd_ 2  by comparing with the threshold voltages in the comparator  282 . Simultaneously, the convert stage  400 -K in the second, fourth and sixth phases holds the signals Vin_ 1 +, Vin_ 1 −, which were sampled in the first, third and fifth phases. Also, the convert stage  400 -K outputs the output signals Vout_ 1 +, Vout_ 1 − to the next convert stage  400 -(K+1) in the second, fourth and sixth phases. 
         [0132]    The first input signals Vin_ 1 +, Vin_ 1 − and the second input signals Vin_ 2 +, Vin_ 2 − can share an operational amplifier  470  in the convert stage  400 -K, because the first input signals Vin_ 1 +, Vin_ 1 − and the second input signals Vin_ 2 +, Vin_ 2 − are processed in different modes at a given time. The signals Vin_ 1 +, Vin_ 1 −, Vin_ 2 +, Vin_ 2 −, Vout_ 1 +, Vout_ 1 −, Vout_ 2 +, and Vout_ 2 − are all analog. Moreover, the minimum voltage of these signals is Vrefm, and the maximum voltage is Vrefp. The common-mode voltage of the input signals Vin+, Vin− is Vcom=(Vin_ 1 ++Vin_ 1 −)/2=(Vin_ 2 ++Vin_ 2 −)/2). 
         [0133]    Adjacent convert stages are in different phases at a given time. For example, when the convert stage  400 -K is in the first or third or fifth phase, the previous convert stage  400 -(K−1) and the next convert stage  400 -(K+1) are in the second or fourth or sixth phase. Then, when the convert stage  400 -K is in the second or fourth or sixth phase, the previous convert stage  400 -(K−1) and the next convert stage  400 -(K+1) are in the first or third or fifth phase. 
         [0134]    One terminal of the capacitor  441 A is connected to a terminal of the capacitor  443 A. Similarly, one terminal of the capacitors  442 A is connected to a terminal of the capacitor  444 A. The connection point of the capacitors  441 A and  443 A is connected to the connection point of the capacitors  442 A and  444 A through the switches  453 A,  454 A in the first, third, fourth, and sixth phases. Also, the connection point of the capacitors  441 A and  443 A is connected to an inverting input terminal of the operational amplifier  470  through the switch  461 A in the second and fifth phases. The other terminal of the capacitor  441 A is input the input signal Vin_ 1 + through the switch  451 A in the first phase, and connected to a non-inverting output terminal of the operational amplifier  470  through the switch  455 A in the second and fifth phases. Also, the other terminal of the capacitor  441 A is connected to the other terminal of the capacitor  442 A through the switch  464 A in the third and sixth phases, and input the input signal Vin_ 2 + through the switch  451 A in the fourth phase. The other terminal of the capacitor  443 A is input the input signal Vin_ 1 + through the switch  457 A in the first phase, and input a reference voltage through the switch  459 A in the second and fifth phases. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  459 A according to either of digital output signals Vd_ 1 , Vd_ 2 , which is obtained in the previous first or fourth phase. Since the digital output signals Vd_ 1 , Vd_ 2  could be three different values “00”/“01”/“11”, the reference voltage has three choices Vrefp, Vcom, Vrefm. Also, the other terminal of the capacitor  443 A is connected to the other terminal of the capacitor  444 A through the switch  463 A in the third and sixth phases, and input the input signal Vin_ 2 + through the switch  457 A in the fourth phase. 
         [0135]    The connection point of the capacitors  442 A and  444 A is connected to the connection point of the capacitors  441 A and  443 A through the switches  454 A,  453 A in the first, third, fourth, and sixth phases. Also, the connection point of the capacitors  442 A and  444 A is connected to a non-inverting input terminal of the operational amplifier  470  through the switch  462 A in the second and fifth phases. The other terminal of the capacitor  442 A is input the input signal Vin_ 1 − through the switch  452 A in the first phase, and connected to an inverting output terminal of the operational amplifier  470  through the switch  456 A in the second and fifth phases. Also, the other terminal of the capacitor  442 A is connected to the other terminal of the capacitor  441 A through the switch  464 A in the third and sixth phases, and input the input signal Vin_ 2 − through the switch  452 A in the fourth phase. 
         [0136]    The other terminal of the capacitor  444 A is input the input signal Vin_through the switch  452 A in the first phase, and input a reference voltage through the switch  460 A in the second and fifth phases. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  460 A according to either of digital output signals Vd_ 1 , Vd_ 2 , which is obtained in the previous first or fourth phase. Also, the other terminal of the capacitor  444 A is connected to the other terminal of the capacitor  443 A through the switch  463 A in the third and sixth phases, and input the input signal Vin_ 2 − through the switch  452 A in the fourth phase. 
         [0137]    One terminal of the capacitor  441 B is connected to a terminal of the capacitor  443 B. Similarly, one terminal of the capacitors  442 B is connected to a terminal of the capacitor  444 B. The connection point of the capacitors  441 B and  443 B is connected to the connection point of the capacitors  442 B and  444 B through the switches  453 B,  454 B in the second, third, fifth and sixth phases. Also, the connection point of the capacitors  441 B and  443 B is connected to an inverting input terminal of the operational amplifier  470  through the switch  461 B in the first and fourth phases. The other terminal of the capacitor  441 B is connected to a non-inverting output terminal of the operational amplifier  470  through the switch  455 B in the first and fourth phases, and connected to the other terminal of the capacitor  442 B through the switch  464 B in the second and fifth phases. Also, the other terminal of the capacitor  441 B is input the input signal Vin_ 1 + through the switch  451 B in the third phase, and input the input signal Vin_ 2 + through the switch  451 B in the sixth phase. The other terminal of the capacitor  443 B is input a reference voltage through the switch  459 B in the first and fourth phases, and connected to the other terminal of the capacitor  444 B through the switch  463 B in the second and fifth phases. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  459 B according to either of digital output signals Vd_ 1 , Vd_ 2 , which is obtained in the previous sixth or third phase. Also, the other terminal of the capacitor  443 B is input the input signal Vin_ 1 + through the switch  457 B in the third phase, and input the input signal Vin_ 2 + through the switch  457 B in the sixth phase. 
         [0138]    The connection point of the capacitors  442 B and  444 B is connected to a non-inverting input terminal of the operational amplifier  470  through the switch  462 B in the first and fourth phases. Also, the connection point of the capacitors  442 B and  444 B is connected to the connection point of the capacitors  441 B and  443 B through the switches  454 B,  453 B in the second, third, fifth and sixth phases. The other terminal of the capacitor  442 B is connected to an inverting output terminal of the operational amplifier  470  through the switch  456 B in the first and fourth phases, and connected to the other terminal of the capacitor  441 B through the switch  464 B in the second and fifth phases. Also, the other terminal of the capacitor  442 B is input the input signal Vin_ 1 − through the switch  452 B in the third phase, and input the input signal Vin_ 2 − through the switch  452 B in the sixth phase. 
         [0139]    The other terminal of the capacitor  444 B is input a reference voltage through the switch  460 B in the first and fourth phases, and connected to the other terminal of the capacitor  443 B through the switch  463 B in the second and fifth phases. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  460 B according to either of digital output signals Vd_ 1 , Vd_ 2 , which is obtained in the previous sixth or third phase. Also, the other terminal of the capacitor  444 B is input the input signal Vin_ 1 − through the switch  452 B in the third phase, and input the input signal Vin_ 2 − through the switch  452 B in the sixth phase. 
         [0140]    One terminal of the capacitor  441 C is connected to a terminal of the capacitor  443 C. Similarly, one terminal of the capacitors  442 C is connected to a terminal of the capacitor  444 C. The connection point of the capacitors  441 C and  443 C is connected to the connection point of the capacitors  442 C and  444 C through the switches  453 C,  454 C in the first, second, fourth, and fifth phases. Also, the connection point of the capacitors  441 C and  443 C is connected to an inverting input terminal of the operational amplifier  470  through the switch  461 C in the third and sixth phases. The other terminal of the capacitor  441 C is connected to the other terminal of the capacitor  442 C through the switch  464 C in the first and fourth phases, and input the input signal Vin_ 2 + through the switch  451 C in the second phase. Also, the other terminal of the capacitor  441 C is connected to a non-inverting output terminal of the operational amplifier  470  through the switch  455 C in the third and sixth phases, and input the input signal Vin_ 1 + through the switch  451 C in the fifth phase. The other terminal of the capacitor  443 C is connected to the other terminal of the capacitor  444 C through the switch  463 C in the first and fourth phases, and input the input signal Vin_ 2 + through the switch  457 C in the second phase. Also, the other terminal of the capacitor  443 C is input a reference voltage through the switch  459 C in the third and sixth phases, and input the input signal Vin_ 1 + through the switch  457 C in the fifth phase. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  459 C according to either of digital output signals Vd_ 1 , Vd_ 2 , which is obtained in the previous second or fifth phase. 
         [0141]    The connection point of the capacitors  442 C and  444 C is connected to the connection point of the capacitors  441 C and  443 C through the switches  454 C,  453 C in the first, second, fourth, and fifth phases. Also, the connection point of the capacitors  442 C and  444 C is connected to a non-inverting input terminal of the operational amplifier  470  through the switch  462 C in the third and sixth phases. The other terminal of the capacitor  442 C is connected to the other terminal of the capacitor  442 C through the switch  464 C in the first and fourth phases, and input the input signal Vin_ 2 − through the switch  452 C in the second phase. Also, the other terminal of the capacitor  442 C is connected to an inverting output terminal of the operational amplifier  470  through the switch  456 C in the third and sixth phases, and input the input signal Vin_ 1 − through the switch  452 C in the fifth phase. 
         [0142]    The other terminal of the capacitor  444 C is connected to the other terminal of the capacitor  443 C through the switch  463 C in the first and fourth phases, and input the input signal Vin_ 2 − through the switch  452 C in the second phase. Also, the other terminal of the capacitor  444 C is input a reference voltage through the switch  460 C in the third and sixth phases, and input the input signal Vin_ 1 − through the switch  452 C in the fifth phase. One of the voltages Vrefp, Vcom, Vrefm is selected as the reference voltage in the switch  460 C according to either of digital output signals Vd_ 1 , Vd_ 2 , which is obtained in the previous second or fifth phase. 
         [0143]    The operational amplifier  470  is a fully differential operational amplifier, including an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The inverting input terminal and the non-inverting output terminal of the operational amplifier  470  are connected each other through the switch  461 B, the capacitor  441 B, and the switch  455 B in the first and fourth phases. Also, they are connected each other through the switch  461 A, the capacitor  441 A, and the switch  455 A in the second and fifth phases. Moreover, they are connected each other through the switch  461 C, the capacitor  441 C, and the switch  455 C in the third and sixth phases. 
         [0144]    The comparator  281  in the first, third and fifth phases compares the difference voltage between the input signals Vin_ 1 + and from the previous convert stage with the threshold voltages, and outputs a digital output signal Vd_ 1  according to the result of the comparison between the difference voltage between the input signals Vin_ 1 +, and the threshold voltages. One of the voltages Vrefp, Vcom, Vrefm is selected as a reference voltage in each of switches  459 A,  460 A,  459 B,  460 B,  459 C,  460 C according to value of the digital output signal Vd_ 1  in the second, fourth and sixth phases. The reference voltages of the switches  459 A,  460 A are added to at the other terminals of the capacitors  443 A,  444 A, respectively, in the second phase. Also, the reference voltages of the switches  459 B,  460 B are added to at the other terminals of the capacitors  443 B,  444 B, respectively, in the fourth phase. Moreover, the reference voltages of the switches  459 C,  460 C are added to at the other terminals of the capacitors  443 C,  444 C, respectively, in the sixth phase. 
         [0145]    The comparator  282  in the second, fourth and sixth phases compares the difference voltage between the input signals Vin_ 2 + and Vin_ 2 − from the previous convert stage with the threshold voltages, and outputs a digital output signal Vd_ 2  according to the result of the comparison between the difference voltage between the input signals Vin_ 2 +, Vin_ 2 − and the threshold voltages. One of the voltages Vrefp, Vcom, Vrefm is selected as a reference voltage in each of switches  459 A,  460 A,  459 B,  460 B,  459 C,  460 C according to value of the digital output signal Vd_ 2  in the first, third and fifth phases. The reference voltages of the switches  459 B,  460 B are added to at the other terminals of the capacitors  443 B,  444 B, respectively, in the first phase. Also, the reference voltages of the switches  459 C,  460 C are added to at the other terminals of the capacitors  443 C,  444 C, respectively, in the third phase. Moreover, the reference voltages of the switches  459 A,  460 A are added to at the other terminals of the capacitors  443 A,  444 A, respectively, in the fifth phase. 
         [0146]    Next, the behaviors of the convert stage  400 -K will be explained according to each phase. Note that the behaviors of the convert stage  400 -K in the fourth to sixth phases in  FIGS. 25-27  are same as these in the first to third phases in  FIGS. 22-24 , except that the signals Vin_ 1 +, Vin_ 1 −, Vout_ 1 +, and Vout_ 1 − in the first to third phases are replaced with the signals Vin_ 2 +, Vin_ 2 −, Vout_ 2 +, and Vout_ 2 − in the fourth to sixth phases. Therefore, explanations for the fourth to sixth phases are skipped. 
         [0147]    As shown in  FIG. 22 , the convert stage  400 -K in the first phase is operating in the sample mode for the input signals Vin_ 1 +, Vin_ 1 −. The convert stage  400 -K samples the input signals Vin_ 1 +, Vin_ 1 − from the previous convert stage  400 -(K−1) in the first phase. The capacitors  441 A,  443 A sample the input signal Vin_ 1 +, and the capacitors  442 A,  444 A sample the input signal Vin_ 1 − by turning on the switches  451 A- 454 A,  457 A,  458 A and turning off the switches  455 A,  456 A,  459 A- 464 A. Moreover, the comparator  481  compares the difference voltage between the input signals Vin_ 1 + and Vin_ 1 − with the threshold voltages to obtain the digital output signal Vd_ 1  (n bit) in the first phase. 
         [0148]    At the same time, the convert stage  400 -K in the first phase is operating in the hold mode for the input signals Vin_ 2 +, Vin_ 2 −, which were sampled by the capacitors  441 B- 444 B in the previous sixth phase. The input signals Vin_ 2 +, Vin_ 2 − are held by turning off the switches  451 B,  452 B,  457 B and  458 B. Moreover, the reference voltages are input into the other terminals of capacitors  443 B,  444 B in the first phase. The reference voltages are according to the digital output signal Vd_ 2  generated in the previous sixth phase. Therefore, flows of the electric charge from the capacitors  441 B- 444 B are caused, and the residual signals are output as output signals Vout_ 2 +, Vout_ 2 −. The residual signal is a signal which is generated by voltage difference between the input signals Vin_ 2 +, Vin_ 2 − and the reference voltages. These output signals Vout_ 2 +, Vout_ 2 − are used as the input signals Vin_ 2 +, Vin_ 2 − in the next convert stage  400 -(K+1). 
         [0149]    On the other hand, one terminal of each of capacitors  441 C- 444 C is connected to other three by turning on the switches  453 C,  454 C and turning off the switches  461 C,  462 C. The other terminals of the capacitors  441 C,  442 C are connected each other by turning on the switch  464 C and turning off the switches  451 C,  452 C,  455 C- 460 C. The other terminals of the capacitors  443 C,  444 C are connected each other by turning on the switches  463 C and turning off the switches  451 C,  452 C,  455 C- 460 C. As a result, the voltages at both terminals of each of capacitors  441 C,  442 C,  443 C,  444 C become equal. Because the capacitances of the capacitors  441 C,  442 C,  443 C,  444 C are equal, electric charge in the capacitors  441 C,  442 C are discharged to be an average voltage at all terminals of capacitors  441 C,  442 C. Similarly, electric charges in the capacitors  443 C,  444 C are discharged to be an average voltage at all terminals of capacitors  443 C,  444 C. At last, since the voltages at all terminals of capacitors  441 C- 444 C become equal, electric charge in the capacitors  441 C- 444 C are all discharged to be an average voltage at all terminals of capacitors  441 C- 444 C. The effect of these discharges will be described later. 
         [0150]    As shown in  FIG. 23 , the convert stage  400 -K in the second phase is operating in the sample mode for the input signals Vin_ 2 +, Vin_ 2 −. The convert stage  400 -K samples the input signals Vin_ 2 +, Vin_ 2 − from the previous convert stage  400 -(K−1) in the second phase. The capacitors  441 C,  443 C sample the input signal Vin_ 2 +, and the capacitors  442 C,  444 C sample the input signal Vin_ 2 − by turning on the switches  451 C- 454 C,  457 C,  458 C and turning off the switches  455 C,  456 C,  459 C- 464 C. Moreover, the comparator  482  compares the difference voltage between the input signals Vin_ 2 + and Vin_ 2 − with the threshold voltages to obtain the digital output signal Vd_ 2  (n bit) in the second phase. 
         [0151]    At the same time, the convert stage  400 -K in the second phase is operating in the hold mode for the input signals Vin_ 1 +, Vin_ 1 −, which were sampled by the capacitors  441 A- 444 A in the previous first phase. The input signals Vin_ 1 +, Vin_ 1 − are held by turning off the switches  451 A,  452 A,  457 A and  458 A. Moreover, the reference voltages are input into the other terminals of capacitors  443 A,  444 A in the second phase. The reference voltages are according to the digital output signal Vd_ 1  generated in the previous first phase. Therefore, flows of the electric charge from the capacitors  441 A- 444 A are caused, and the residual signals are output as output signals Vout_ 1 +, Vout_ 1 −. The residual signal is a signal which is generated by voltage difference between the input signals Vin_ 1 +, Vin_ 1 − and the reference voltages. These output signals Vout_ 1 +, Vout_ 1 − are used as the input signals Vin_ 1 +, Vin_ 1 − in the next convert stage  400 -(K+1). 
         [0152]    On the other hand, one terminal of each of capacitors  441 B- 444 B is connected to other three by turning on the switches  453 B,  454 B and turning off the switches  461 B,  462 B. The other terminals of the capacitors  441 B,  442 B are connected each other by turning on the switch  464 B and turning off the switches  451 B,  452 B,  455 B- 460 B. The other terminals of the capacitors  443 B,  444 B are connected each other by turning on the switches  463 B and turning off the switches  451 B,  452 B,  455 B- 460 B. As a result, the voltages at both terminals of each of capacitors  441 B,  442 B,  443 B,  444 B become equal. Because the capacitances of the capacitors  441 B,  442 B,  443 B,  444 B are equal, electric charge in the capacitors  441 B,  442 B are discharged to be an average voltage at all terminals of capacitors  441 B,  442 B. Similarly, electric charges in the capacitors  443 B,  444 B are discharged to be an average voltage at all terminals of capacitors  443 B,  444 B. At last, since the voltages at all terminals of capacitors  441 B- 444 B become equal, electric charge in the capacitors  441 B- 444 B are all discharged to be an average voltage at all terminals of capacitors  441 B- 444 B. 
         [0153]    As shown in  FIG. 24 , the convert stage  400 -K in the third phase is operating in the sample mode for the input signals Vin_ 1 +, Vin_ 1 −. The convert stage  400 -K samples the input signals Vin_ 1 +, Vin_ 1 − from the previous convert stage  400 -(K−1) in the third phase. The capacitors  441 B,  443 B sample the input signal Vin_ 1 +, and the capacitors  442 B,  444 B sample the input signal Vin_ 1 − by turning on the switches  451 B- 454 B,  457 B,  458 B and turning off the switches  455 B,  456 B,  459 B- 464 B. Moreover, the comparator  481  compares the difference voltage between the input signals Vin_ 1 + and Vin_ 1 − with the threshold voltages to obtain the digital output signal Vd_ 1  (n bit) in the third phase. 
         [0154]    At the same time, the convert stage  400 -K in the third phase is operating in the hold mode for the input signals Vin_ 2 +, Vin_ 2 −, which were sampled by the capacitors  441 C- 444 C in the previous second phase. The input signals Vin_ 2 +, Vin_ 2 − are held by turning off the switches  451 C,  452 C,  457 C and  458 C. Moreover, the reference voltages are input into the other terminals of capacitors  443 C,  444 C in the third phase. The reference voltages are according to the digital output signal Vd_ 2  generated in the previous second phase. Therefore, flows of the electric charge from the capacitors  441 C- 444 C are caused, and the residual signals are output as output signals Vout_ 2 +, Vout_ 2 −. The residual signal is a signal which is generated by voltage difference between the input signals Vin_ 2 +, Vin_ 2 − and the reference voltages. These output signals Vout_ 2 +, Vout_ 2 − are used as the input signals Vin_ 2 +, Vin_ 2 − in the next convert stage  400 -(K+1). 
         [0155]    On the other hand, one terminal of each of capacitors  441 A- 444 A is connected to other three by turning on the switches  453 A,  454 A and turning off the switches  461 A,  462 A. The other terminals of the capacitors  441 A,  442 A are connected each other by turning on the switch  464 A and turning off the switches  451 A,  452 A,  455 A- 460 A. The other terminals of the capacitors  443 A,  444 A are connected each other by turning on the switches  463 A and turning off the switches  451 A,  452 A,  455 A- 460 A. As a result, the voltages at both terminals of each of capacitors  441 A,  442 A,  443 A,  444 A become equal. Because the capacitances of the capacitors  441 A,  442 A,  443 A,  444 A are equal, electric charge in the capacitors  441 A,  442 A are discharged to be an average voltage at all terminals of capacitors  441 A,  442 A. Similarly, electric charges in the capacitors  443 A,  444 A are discharged to be an average voltage at all terminals of capacitors  443 A,  444 A. At last, since the voltages at all terminals of capacitors  441 A- 444 A become equal, electric charge in the capacitors  441 A- 444 A are all discharged to be an average voltage at all terminals of capacitors  441 A- 444 A. 
         [0156]    The A/D converter in the fourth embodiment discharges the capacitors once before the sample mode. It is same as the A/D converter in the second embodiment. For example, before sampling the input signals Vin_ 1 +, Vin_ 1 − in the first phase, the capacitors  441 A- 444 A have discharged electric charge which had been held during the fifth phase by connecting between both terminals of the capacitors  441 A- 444 A in the sixth phase. Similarly, before sampling the input signals Vin_ 2 +, Vin_ 2 − in the second phase, the capacitors  441 C- 444 C have discharged electric charge which had been held during the sixth phase by connecting between both terminals of the capacitors  441 C- 444 C in the first phase. Moreover, before sampling the input signals Vin_ 1 +, Vin_ 1 − in the third phase, the capacitors  441 B- 444 B have discharged electric charge which had been held during the first phase by connecting between both terminals of the capacitors  441 B- 444 B in the second phase. Therefore, the A/D converter in the fourth embodiment can decreases the consumption power as same as the second embodiment. In addition to the effect, the A/D converter in the fourth embodiment realizes reduction of the circuit size. Because each convert stage in the A/D converter samples and holds two analog input signals with using three sets of capacitors. It can be eliminated one set of capacitors compared with the case of using two A/D converters which include four sets of capacitors in the second embodiment for two analog input signals. 
         [0157]    The A/D converter in the fourth embodiment could be applied not only for two analog input signals but also for an analog input signal as shown in  FIG. 28 . In this case, a digital output signal with higher sample rate can be obtained compared with the A/D converter in the second embodiment. 
         [0158]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.