Abstract:
A delay locked loop includes a forward path for receiving an input signal to provide an output signal, a feedback path for providing a feedback signal based on the output signal, and a controller responsive to a timing relationship between the feedback signal and the input signal for adjusting a timing of the output signal. The feedback path includes an adjustable delay circuit for adjusting a timing of the feedback signal.

Description:
This application is a Divisional of U.S. application Ser. No. 10/147,645, filed May 16, 2002, now U.S. Pat. No. 6,900,685, which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to signal processing, and in particular, to delay circuits. 
     BACKGROUND OF THE INVENTION 
     Delay circuits delay an input signal to generate an output signal which is a delayed version of the input signal. Most delay circuits have a specified delay between the input and output signals. In some applications, some delay circuits cause the actual delay between the input and output signals to be different from the specified delay because of changes in operating conditions such as operating voltage and temperature. Therefore, some of these delay circuits are unsuitable for some applications when the operating condition changes. 
     For these and other reasons stated below, and which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for an improved delay circuit. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention provide a delay circuit that can be configured to adjust a delay between an input signal and an output signal. 
     In one aspect, the delay circuit has a comparator connected to a reference generator. The comparator includes a first stage for receiving an input signal, and a second stage connected to the first stage for receiving a reference signal to output an output signal. The input and output signals have a delay which is based on a signal relationship between the input and reference signals. The reference generator includes a plurality of configurable devices configured to vary the reference signal to adjust the delay between the input and output signals. 
     In another aspect, a method includes receiving an input signal and a reference signal. The method also includes producing an output signal. The input and output signals have a delay. Further, the method includes varying the reference signal to adjust the delay. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a delay circuit according to an embodiment of the invention. 
         FIG. 2  shows an example of a signal relationship between input and output signals of the delay circuit of  FIG. 1 . 
         FIG. 3  shows a delay circuit according to another embodiment of the invention. 
         FIGS. 4–6  show examples of signal relationships of signals of the delay circuit of  FIG. 3 . 
         FIG. 7  shows a delay circuit according to another embodiment of the invention. 
         FIG. 8  shows a signal relationship of the delay circuit of  FIG. 7 . 
         FIG. 9  shows a reference generator according to an embodiment of the invention. 
         FIG. 10  shows a delay circuit according to another embodiment of the invention. 
         FIG. 11  shows an example of a signal relationship among the signals of the delay circuit of  FIG. 10 . 
         FIG. 12  shows a delay system according to an embodiment of the invention. 
         FIG. 13  shows an example of a signal relationship among some signals of the delay system of  FIG. 12 . 
         FIG. 14  shows an example of a signal relationship between an input signal and an output signal of the delay system of  FIG. 12 . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice it. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the full ambit of the claims and all available equivalents. 
       FIG. 1  shows a delay circuit according to an embodiment of the invention. Delay circuit  100  includes a comparator  102  and a reference generator  104 . Comparator  102  has an input node  106  and an output node  108 . Node  106  receives an input signal IN. Node  108  outputs an output signal OUT. Reference generator  104  has an output connected to node  110  to provide a reference signal REF. Both comparator  102  and reference generator  104  connect to a supply node  111  to receive a supply voltage, Vcc. Comparator  102  compares the IN and REF signals and outputs the OUT signal as a delayed version of the IN signal. 
       FIG. 2  shows an example of a signal relationship among the REF, IN and OUT signals. In  FIG. 2 , the IN signal has a rising edge  206  and a falling edge  207 . The OUT signal has a rising edge  208  and a falling edge  209 . Edge  206  is delayed from edge  208  a time delay (or a delay) indicated by D 1 . Edge  207  is delayed from edge  209  a time delay indicated by D 2 . In some embodiments, reference generator  104  is configured to adjust D 1  to change the signal relationship (or the delay) between the IN and OUT signals. For example, in some embodiments, reference generator  104  is configured in one configuration to decrease D 1  based on one condition of voltage and temperature. As another example, reference generator  104  is configured in another configuration based on another condition of voltage and temperature to increase D 1 . 
     In some embodiments, reference generator  104  is configured such that at certain condition of temperature, D 1  is decreased when Vcc is at a first value, and increased when Vcc is at a second value. In other embodiments, reference generator  104  is configured such that at certain condition of temperature, D 1  is decreased when the first value of Vcc is lower than the second value of Vcc. In some other embodiments, reference generator  104  is configured such that at certain condition of temperature, D 1  is decreased when the first value of Vcc is higher than the second value of Vcc. 
     Reference generator  104  is configured to vary the REF signal to adjust D 1  to change the signal relationship between the IN and OUT signals. In some embodiments, the voltage level (or signal level) of the REF is varied to adjust D 1 . For example, in some embodiments, the voltage level of the REF signal is decreased to decrease D 1  and increased to increase D 1 . As another example, in other embodiments, the voltage level of the REF signal is increased to decrease D 1  and decreased to increase D 1 . 
     In some embodiments, reference generator  104  is configured to adjust D 2  in a similar manner as that of the configuration for adjusting D 1  as described above. 
       FIG. 3  shows a delay circuit according to an embodiment of the invention. Delay circuit  300  includes a comparator  302 , and a reference generator  304 . Comparator  302  represents comparator  102  ( FIG. 1 ). Reference generator  304  represents reference generator  104  ( FIG. 1 ). 
     Comparator  302  includes a first stage  320 , a second stage  322 , a pullup device  324 , and a pulldown device  326 . First and second stages  320  and  322  connect in parallel with each other and in between a pullup node  328  and a pulldown node  330 . Pullup device  324  connects between node  328  and a supply node  333 . Pulldown device  326  connects between node  330  and another supply node  344 . Both pullup device  324  and pulldown device  326  connect to first stage  320  at node  336 . 
     First stage  320  has an input node  306  to receive an input signal IN. Second stage  322  has an input node connected to a comparator reference node  310  to receive a reference input signal REF. Second stage  322  also has an output node  308  to produce an output signal OUT. The IN, OUT, and REF signals are similar in both  FIG. 1  and  FIG. 3 . 
     Reference generator  304  includes a plurality of configurable devices  352 . 0  through  352 .X ( 352 . 0 – 352 .X). In some embodiments, configurable devices  352 . 0 – 352 .X include fuse devices. In other embodiments, configurable devices  352 . 0 – 352 .X include fuseable devices such as electrical fuse and laser fuse. In some other embodiments, configurable devices  352 . 0 – 352 .X include transistors having metal options. Further, in alternative embodiments, configurable devices  352 . 0 – 352 .X include a combination of fusable devices, and transistors having metal options. Configurable devices  352 . 0 – 352 .X are configured to vary the REF signal to adjust the signal relationship between the IN and OUT signals. 
     Pullup device  324 , first stage  320 , and pulldown device  326  form a first current path  341  between supply nodes  333  and  344 . Pullup device  324 , second stage  322 , and pulldown device  326  form a second current path  342  between supply nodes  333  and  344 . The amount of current flowing in each of the current paths  341  and  342  depends on the IN and REF signals. The signal level of the OUT signal depends on the difference in the IN and REF signals. For example, when the IN signal is lower than the REF signal, the OUT signal has a low signal level. When the IN signal is higher than the REF signal, the OUT signal has a high signal level. 
       FIG. 4  shows an example of the signal relationship among the IN, OUT, and REF signals of  FIG. 3 .  FIG. 4  shows an example when the IN signal is lower than the REF signal, the OUT signal has a low signal level, and when the IN signal is higher than the REF signal, the OUT signal has a high signal level. As shown in  FIG. 4 , before time T 0 , the IN signal has signal level that is lower than signal level (Vref ) of the REF signal, and the OUT signal has a low signal level. After time T 0 , the signal level of the IN signal is higher than signal level of the REF signal, and the OUT signal has a high signal level. In some embodiments, the low signal level and the high signal level correspond to logic  0  and logic  1  in digital circuits. 
     In  FIG. 4 , D 4  indicates the delay between rising edges of the IN and OUT signals. D 4  can be adjusted by varying the REF signal based on certain temperature and the voltage level of node  333  ( FIG. 3 ). In some embodiments, configurable devices  352 . 0 – 352 .X of reference generator  304  are configured such that the REF signal is decreased to decrease D 4  and such that the REF signal is increased to increase D 4 . In other embodiments, configurable devices  352 . 0 – 352 .X are configured such that the REF signal is increased to decrease D 4  and such that the REF signal is decreased to increase D 4 . 
       FIG. 4  also shows DL 4  to indicate a delay between falling edges of the IN and OUT signals. DL 4  can also be adjusted by varying the REF signal based on certain temperature and the voltage level of node  333  ( FIG. 3 ). 
       FIG. 5  and  FIG. 6  show examples of a signal relationship among the IN, OUT, and REF signals when the REF signal of  FIG. 4  is varied. For comparison purposes, T 0  in all  FIGS. 4–6  is chosen as a reference time and  FIG. 4  is chosen as a reference starting point. In  FIGS. 4–6 , D 4 , D 5 , and D 6  are delays between the IN and OUT signals. In  FIG. 5 , varying the signal level of the REF signal from Vref to VrefA decreases the delay between the IN and OUT signals to D 5 , which is relatively smaller than D 4 . Thus, varying the REF signal from Vref to VrefA changes the signal relationship between the IN and OUT signals. In  FIG. 6 , varying the signal level of the REF signal from Vref to VrefB increases the delay between the IN and OUT signals becomes D 6 . Thus, varying the REF signal from Vref to VrefB changes the signal relationship between the IN and OUT signals. 
     In  FIGS. 4–6 , Vref, VrefA, and VrefB are drawn to illustrate various signal levels; they do not represent absolute values. In some embodiments, VrefA is lower than Vref. In other embodiments, VrefA is higher than Vref. In some embodiments, VrefB is lower than Vref. In other embodiments, VrefB is higher than Vref. 
       FIG. 7  shows a delay circuit according to another embodiment of the invention. Delay circuit  700  includes a comparator  702  and a reference generator  704 . Comparator  702  represents comparator  102  ( FIG. 1 ) and comparator  302  ( FIG. 3 ). Reference generator  704  represents reference generator  104  ( FIG. 1 ) and reference generator  304  ( FIG. 3 ). 
     Comparator  702  includes transistor  721 ,  723 ,  724 ,  725 ,  726 , and  727 . Transistors  721  and  723  form a transistor pair  720  which forms an input stage corresponding to first stage  320  ( FIG. 3 ). Transistors  725  and  727  form a transistor pair  722  which forms an input stage corresponding to second stage  322  ( FIG. 3 ). Transistor  724  forms a pullup device corresponding to pullup device  324  ( FIG. 3 ). Transistor  726  forms a pulldown device corresponding to pulldown device  326  ( FIG. 3 ). 
     Transistors  721  and  723  have a common gate connected to node  706  to receive the IN signal, and a common drain connected to node  736 . Transistors  725  and  727  have a common gate connected to a comparator reference node  710 , and a common drain connected to node  708  to generate the OUT signal. Transistor  724  has a source connected to node  733 , a drain connected to node  728 , and a gate connected to node  736 . Transistor  726  has a source connected to node  744 , a drain connected to node  730 , and a gate connected to node  736 . 
     Reference generator  704  includes transistors  751 ,  752 ,  753 ,  754 ,  755  ( 751 – 755 ), and configurable elements  761 ,  762 ,  763 ,  764 ,  765 ,  766 ,  767 ,  768 ,  769 , and  770  ( 761 – 770 ). Transistors  751 – 755  connect in series between supply nodes  733  and  744 . Transistors  751 – 755  and configurable elements  761 – 770  form a plurality of configurable devices corresponding to configurable devices  352 . 0 – 352 .X ( FIG. 3 ). 
     Transistors  751  and  752  form a plurality of configurable load transistors connected between nodes  733  and  710 . Transistors  751  and  752  form a plurality of configurable output transistors connected between nodes  710  and  744 . 
     Each of the configurable elements  761 – 770  is located between a drain and source, or between a gate and source of each of the transistors  751 – 755 , or between the gates of two transistors. Each of the configurable elements  761 – 770  can be configured to connect (close) or to disconnect (open) the drain and source, or the gate and source of each of the transistors  751 – 755 , or the gates of two transistors. Thus, each of the transistors  751 – 755  has a configurable drain-to-source connection, or a configurable gate-to-source connection, or both configurable drain-to-source and configurable gate-to-source connections. And transistors  751 – 755  also have configurable gate-to-gate connections. For example, configurable element  763  is located between the drain and source of transistor  753 ; configurable element  764  is located between the gates of transistors  753  and  754 ; and configurable element  766  is located between the gate and drain of transistor  754 . Drain and source of a transistor are used interchangeably in this specification. 
     Transistors  751 – 755  and configurable elements  761 – 770  are configured as one of many different possible configurations. In the configuration shown in  FIG. 7 , configurable elements  761 ,  766 ,  769 , and  770  are in a “closed” (connected or shorted) position, and configurable elements  762 ,  763 ,  764 ,  765 , and  767  are in an “opened” (disconnected) position. This configuration gives one signal level for the REF signal. In other embodiments, transistors  751 – 755  and configurable elements  761 – 770  can be configured in other configurations by choosing other “closed” and “opened” combinations of configurable elements  761 – 770  to obtain other signal levels for the REF signal. 
     Configurable elements  761 – 770  represent any configurable elements known to those skilled in the art. For example, configurable elements  761 – 770  can be metal options which can be configured by different opened and closed combinations. In other embodiments, configurable elements  761 – 770  can be fuses which can be configured by blowing the fuses using any known method. In some other embodiments, configurable elements  761 – 770  can be anti-fuses which can be configured by programming the anti-fuses devices using any known method. Other types of configurable elements can be used in alternative embodiments of the present invention. 
     Transistors  721 ,  724 ,  725 ,  751 , and  752  are p-channel metal oxide semiconductor field effect transistors (PMOSFET), also referred to as “PFET” or “PMOS”. Transistors  723 ,  726 ,  727 ,  753 ,  754 , and  755  are n-channel metal oxide semiconductor field effect transistors (NMOSFET) also referred to as “NFET” or “NMOS”. In other embodiments, the types of transistors can be reversed. For example, transistors  721 ,  724 ,  725 ,  751 , and  752  can be NMOS transistors and transistors  723 ,  726 ,  727 ,  753 ,  754 , and  755  can be PMOS transistors. 
     Other types of transistors can also be used in place of the NMOS and PMOS transistors of  FIG. 7 . For example, embodiments exist that use bipolar junction transistors (BJTs) and junction field effect transistors (JFETs.) One of ordinary skill in the art will understand that many other types of transistors and other elements can be used in alternative embodiments of the present invention. 
     In  FIG. 7 , the signal level of the OUT signal depends on the signal relationship between the IN and REF signals. When the IN signal is lower than the REF signal, the voltage level at node  708  is low. When the IN signal is higher than the REF signal, the voltage level at node  708  is high. 
       FIG. 8  shows a signal relationship of the delay circuit of  FIG. 7 . In  FIG. 8 , D 8  indicates a delay between the IN and OUT signals. This delay can be adjusted by varying the REF signal of  FIG. 7 . In  FIG. 7 , the REF signal can be varied by configuring transistors  751 – 755  and configurable elements  761 – 770  in different ways. For example, to increase the signal level of the REF signal, configurable  767  would be closed and configurable element  769  would be opened. With that configuration, an additional voltage drop exists between the source and drain of transistor  755 , thereby increasing the voltage level at node  710  and also the signal level of the REF signal. As another example, to decrease the signal level of the REF signal, configurable element  766  would be opened and configurable element  768  would be closed. In this example, the voltage drop between the source and drain of transistor  754  disappears, thereby decreasing the voltage level at node  710  and also the signal level of the REF signal. 
       FIG. 9  shows a reference generator according to an embodiment of the invention. Reference generator  904  can be used as an embodiment for reference generators  104  ( FIG. 1 ),  304  ( FIG. 3 ), or  704  ( FIG. 7 ). Reference generator  904  includes load transistors  920 , and  922 , a bias transistor  924 , an output transistor  926 , and a reference output node  910 . Transistors  920  and  924  form a bias stage  921 . Transistor  922  and  926  form an output stage  923 . Each of the transistors  920  and  922  is a diode-connected transistor. A diode-connected transistor has a gate connected to a drain such that the gate-to-source voltage and the drain-to-source voltage are equal. 
     Transistor  920  has a source connected to a supply node  933 , and a gate and a drain connected together at node  928 . Transistor  922  has a source connected to node  933 , and a gate and a drain connected together at an output node  910 . Transistor  924  has a drain connected to node  928 , a source connected to a supply node  944 , and a gate connected to node  933 . Transistor  926  has a gate connected to node  928 , a source connected to node  944 , and a drain connected to node  910 . 
     Each of the transistors  920 ,  922 ,  924 , and  926  has a channel width (W), a channel length (L), and a channel width to channel length (W/L) ratio. In  FIG. 9 , W 920 /L 920 , W 922 /L 922 , W 924 /L 924 , and W 926 /L 926  indicate the channel width to channel length ratios of transistors  920 ,  922 ,  924 , and  926 , respectively. 
     Reference generator  904  generates a reference signal REF on node  910 . The REF signal can be varied by configuring (or selecting) the W and the L of each of the transistors  920 ,  922 ,  924 , and  926 , or each of the W 920 /L 920 , W 922 /L 922 , W 924 /L 924 . For example, in some embodiments, transistors  920 ,  922 ,  924 , and  926  are configured in a first configuration such that reference generator  904  outputs the REF signal having a first signal level. As another example, in other embodiments, transistors  920 ,  922 ,  924 , and  926  are configured in a second configuration such that reference generator  904  outputs the REF signal having a second signal level. In some other embodiments, other configurations of transistors  920 ,  922 ,  924 , and  926  generate other reference signals having other values unequal to the first value or the second value. 
       FIG. 10  shows a delay circuit according to another embodiment of the invention. Delay circuit  1000  includes a comparator  1002  and a reference generator  1004 . 
     Comparator  1002  represents comparator  102  ( FIG. 1 ). In some embodiments, comparator  1002  includes embodiments of comparator  302  ( FIG. 3 ) and comparator  702  ( FIG. 7 ). Comparator  1002  includes an input node  1006  to receive an input signal IN, and an output node to output an output signal OUT. 
     Reference generator  1004  includes a plurality of selectable level generators  1004 . 0  through  1004 .N ( 1004 . 0 – 1004 .N) and a multiplexor (MU)  1012  (or selector  1012 ). Signal level generators  1004 . 0 – 1004 .N and MUX  1012  connect together via nodes  1011 . 0  through  1011 .N ( 1011 . 0 – 1011 .N). 
     Each of the selectable level generators  1004 . 0 – 1004 .N includes a selectable output node connected to one of nodes  1011 . 0 – 1011 .N to provide one of selectable signals REF. 0  through REF.N (REF. 0 –REF.N). For example, selectable level generator  1004 . 0  includes a selectable output node connected to node  1011 . 0  to provide the REF. 0  signal; selectable level-generator  1004 .N includes a selectable output node connected to node  1011 .N to provide the REF.N signal. 
     In some embodiments, each of the selectable signals REF. 0 –REF.N has a different signal level. In some embodiments, each of the selectable level generators  1004 . 0 – 1004 .N includes embodiments of reference generator  704  ( FIG. 7 ) or embodiments of reference generator  904  ( FIG. 9 ). In some of these embodiments, each of the selectable level generators  1004 . 0 – 1004 .N is configured in a different configuration to output a different selectable output signal. Therefore, in some of these embodiments, a selectable output signal of one selectable level generator is unequal to a selectable output signal of another selectable level generator. 
     MUX  1012  includes a plurality of input nodes connected to nodes  1011 . 0 – 1011 .N to receive the REF. 0 –REF.N signals. MUX  1012  has an output connected to node  1010  to provide a reference signal REF. MUX  1012  also has a plurality of select nodes  1013 . 0  through  1013 .M ( 1013 . 0 – 1013 .M) to receive a plurality of select signals S 0  through SM (S 0 –SM). A combination of the S 0 –SM signals selects one of the REF. 0 –REF.N signals as the REF signal. 
       FIG. 11  shows an example of a signal relationship among the IN, OUT, REF signals of the delay circuit  1000  of  FIG. 10 . In  FIG. 11 , D 11  indicates the delay between the IN and OUT signals. D 11  can be adjusted to change the signal relationship between the IN and OUT signals by varying the REF signal. 
     In  FIG. 10 , the REF signal can be varied to adjust D 11  by selecting different combinations of the S 0 –SM signals. D 11  depends on the REF signal which is one of the REF. 0 –REF.N signals selected by a combination of the S 0 –SM signals. Since the REF. 0 –REF.N signals have different signal levels, a different combination of the S 0 –SM signals can be selected to select a different one of the REF. 0 –REF.N signals to be the REF signal to adjust D 11 . 
     In some embodiments, each of the selectable level generators  1004 . 0 – 1004 .N includes embodiments of reference generator  704  ( FIG. 7 ). In other embodiments, each of the selectable level generators  1004 . 0 – 1004 .N includes embodiments of reference generator  904  ( FIG. 9 ). 
       FIG. 12  shows a delay system according to an embodiment of the invention. Delay system  1200  includes an input buffer  1202 , a delay line  1203 , an output buffer  1206 , a controller  1208 , an ouput model circuit  1210 , an input model circuit  1211 , and a delay circuit  1204 . Input buffer  1202 , delay line  1203 , and output buffer  1206  form a forward path  1215 . Ouput model circuit  1210 , input model circuit  1211 , and delay circuit  1204  form a feedback path  1217 . 
     Delay system  1200  also includes an input node  1230  to receive an input signal XCLK. The XCLK signal passes through forward path  1215  and becomes an output signal CLKDLL at output node  1233 . The CLKDLL signal is a delayed version of the XCLK signal. In some embodiments, the XCLK and the CLKDLL signal are synchronized. 
     Two other signals exist on forward path  1215 , a delayed input signal CLKIN signal at node  1221  and a delayed signal CLKOUT at node  1223 . The CLKIN is a delayed version of the XCLK signal and is delayed by a delay DL 1  of input buffer  1202 . The CLKOUT is a delayed version of the CLKIN signal and is delayed by a delay of delay line  1203 . Further, CLKDLL signal is a delayed version of the CLKOUT signal and is delayed by a delay DL 2  of output buffer  1206 . 
     Feedback path  1217  receives the CLKOUT signal and provides a feedback signal CLKFB. The CLKFB signal is the CLKOUT signal delayed by a delay DL 3 . In some embodiments, input model circuit  1211  and input buffer  1202  have identical construction. In other embodiments, input model circuit  1211  and input buffer  1202  have equal delays. In some embodiments, output model circuit  1210  and output buffer  1206  have identical construction. In other embodiments, output model circuit  1210  and output buffer  1206  have equal delays. In  FIG. 12 , the combination of ouput model circuit  1210 , input model circuit  1211 , and delay circuit  1204  is constructed to be a model of the combination of input buffer  1202  and output buffer  1206  such that DL 3 =DL 1 +DL 2 . 
     Delay circuit  1204  includes an input connected to input model  1211  to receive an input signal IN and output connected to controller  1208  to provide an output signal OUT. The IN signal is a delayed version of the CLKOUT signal. The OUT signal is the same as the CLKFB signal. Delay circuit  1204  also includes a plurality of select nodes  1213 . 0  through  1213 .M ( 1213 . 0 – 1213 .M) to receive a plurality of select signals S 0 –SM. Delay circuit  1204  represents embodiments of a delay circuit corresponding to delay circuit  1000  ( FIG. 10 ). The IN and OUT signals are similar in both  FIG. 12  and  FIG. 10 . Select node  1213 . 0 – 1213 .M are similar to select nodes  1013 . 0 – 1013 .M ( FIG. 10 ). The S 0 –SM signals are similar in both  FIG. 12  and  FIG. 10 . In some embodiments, delay circuit  1204  adjusts a signal relationship between the IN and OUT signals to keep the XCLK and CLKDLL signals synchronized by selecting a combination of the S 0 –SM signals. 
     In some embodiments, delay line  1203  includes a plurality of delay cells connected in series. Each delay cell can delay a signal for a predetermined amount of time. The amount of delay applied to the CLKIN signal varies according to the number of delay cells selected. 
     In some embodiments, controller  1208  includes a phase detector that detects and compares a difference between the edges of two signals. In  FIG. 12 , controller  1208  compares the CLKIN and CLKFB signals. When the CLKIN and CLKFB signals are not synchronized, controller  1208  performs a shifting operation to adjust the amount of delay applied to the CLKIN signal by delay line  1203 . When the CLKIN and CLKFB signals are synchronized, controller  1208  stops the shifting operation and puts delay system  1200  in a locked position. When the CLKIN and the CLKFB signals are synchronized during the locked position, the XCLK and CLKDLL signals are also synchronized because feedback path  1217  is a model of input buffer  1202  and output buffer  1206  in which DL 3 =DL 1 +DL 2 . In some embodiments, the XCLK and CLKDLL signals are synchronized within a predetermined lock window (or a predetermined delay). In some embodiments, the predetermined lock window is less than or equal to the delay of one delay cell. 
       FIG. 13  shows an example of the XCLK and CLKDLL signals when they are synchronized while delay system  1200  is in the locked position. DW indicates the predetermined lock window. 
     In some cases, when delay system  1200  is in the locked position, the XCLK and CLKDLL signals may be out of the predetermined lock window because of changes in operating conditions such as process, voltage, and temperature. 
       FIG. 14  shows an example of a signal relationship between the XCLK and CLKDLL signals being out of the predetermined lock window when delay system  1200  is in the locked position. DW 1  indicates a delay between the XCLK and CLKDLL when delay system  1200  is in a locked position. DW 1  is relatively greater than DW. In this example, DW 1  can be adjusted so that the XCLK and CLKDLL are synchronized within DW by selecting a combination of the S 0 -SM. When a proper combination of the S 0 –SM signals is selected, delay circuit  1204  adjusts the OUT signal. Since the OUT signal is the CLKFB signal, adjusting the OUT signal also adjusts the signal relationship between the CLKIN and CLKOUT signals. When the signal relationship between the CLKIN and CLKOUT signals is adjusted, signal relationship between the XCLK and CLKDLL signals is also adjusted.