Abstract:
An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to non-linear electronic devices, such as non-linear capacitors. More specifically, but not exclusively, the present invention relates to an electronic device integrated on a semiconductor substrate, with the electronic device being integrated or used in association with a circuit network including non-linear devices. 
     BACKGROUND OF THE INVENTION 
     Data detection for transmission channels is based on the use of a network of non-linear devices, as readily understood by those skilled in the art. Data detection with non-linear devices is becoming more popular because of the simplicity of the circuit networks, including such non-linear devices, and because of a corresponding lower production cost. 
     A circuit network including non-liner devices requires that the non-linearity of such devices be well controlled and follow a well-defined rule. Once these conditions are met, then the resulting network provides some advantages in data detection when compared with other more complex approaches. 
     The devices used in this kind of network are usually capacitors and inductors that have a non-linear relation between capacitance and voltage for the capacitors, and a non-linear relation between inductance and current for the inductors. One of the main difficulties for manufacturing an integrated circuit network including non-linear devices is that the non-linear components are to be provided as discrete elements. An integrated non-linear capacitor or inductor is hard to form based upon current technology. 
     For instance, U.S. Pat. No. 6,166,604 relates to a semiconductor amplifier including a distortion compensation circuit. The disclosed amplifier comprises a non-linear amplifying element connected to an integrated capacitor that prevents a direct current from flowing through a passive circuit. The integrated capacitor is formed in a known manner. 
     Up to now, there have not been any straightforward approaches for easily integrating an electronic circuit that includes non-linear passive components. Consequently, there is a need for implementing non-linear passive devices into a semiconductor electronic circuit, thus allowing the construction of a network of non-linear devices for data detection in transmission channels. 
     SUMMARY OF THE INVENTION 
     The scope of the present invention is to provide a method for integrating a non-linear passive device, such as a non-linear capacitor, and to provide a corresponding circuit. 
     More specifically, the present invention may provide a non-linear capacitor with the following relationship:        C   =       C   0     ·     1     1   -     k   ·     V   c   2                                    
     The present invention is based on the fact that non-linear passive devices are formed by using active components connected in a feedback loop for emulating the same behavior of the non-linear passive device. In other words, the present invention utilizes active devices operating in a feedback loop to implement the function of a non-linear capacitor. 
     Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     A more complete understanding of the present invention may be had by reference to the following detailed description when taken in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a block diagram of a first embodiment of an electronic circuit in accordance with the present invention; 
     FIG. 2 is a detailed schematic diagram of the electronic circuit in accordance with the present invention; 
     FIG. 3 is a graph showing a capacitance value versus voltage for the electronic circuit illustrated in FIG. 2; and 
     FIG. 4 is a graph showing a charge value versus voltage for the electronic circuit illustrated in FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, a block diagram of an embodiment of an integrated electronic circuit  1  in accordance with the present invention is shown. The integrated electronic circuit  1  implements a non-linear capacitor Ceq, and more specifically, a non-linear capacitor having the following relationship:        C   =       C   0     ·     1     1   -     k   ·     V   c   2                                    
     where V c  is an input voltage; k is a gain factor of the quadratic term (i.e., the term that defines the non-linearity value), and C o  is the value of the capacitor when the input voltage in null (i.e., V c =0). 
     The electronic circuit  1  includes a first logarithmic amplifier block  2  receiving an input current Iin at an input terminal  3 . The amplifier block  2  has an output  4  connected to an input of a derivative block  5  performing a d/dt function on the input current signal. A final gain block  6  is connected in cascade downstream of the derivative block  5 . 
     A feedback connection  7  closes a feedback loop between the output of the gain block  6  and the input terminal  3 . The present invention is implemented by interconnecting several blocks into a feedback loop as shown in FIG. 1, thus forming a non-linear capacitor. 
     The implemented function will be explained by starting with the relationship between voltage and current at the input terminals of the electronic circuit  1 :          I   in     =       gm   ·             t              (     log        (       1   +     V   in         1   -     V   in         )       )                              
     As may be appreciated, the gain term gm represents the function of the gain block  6 , the d/dt portion in parenthesis is the operative result presented by the output of the derivative block  5  while the logarithmic block  2  works on the input voltage signal Vin. 
     Solving the derivative term:                    t            (     log        (       1   +     V   in         1   -     V   in         )       )       =       1     (       1   +     V   in         1   -     V   in         )       ·                  V   in            t       ·     (     1   -     V   in       )       +              V   in            t       ·     (     1   +     V   in       )             (     1   -     V   in       )     2                                
     and simplifying:                     V   in            t       ·     (     1   -     V   in     +   1   +     V   in       )           (     1   +     V   in       )     ·     (     1   -     V   in       )         =       2   ·            V   in            t           (     1   -     V   in   2       )                              
     a final result according to the following relationship (Eq. 1) is obtained:                I   in     =         gm   ·             t              (     log        (       1   +     V   in         1   -     V   in         )       )       =     gm   ·     2     (     1   -     V   in   2       )       ·            V   in            t                   Eq.  1                                
     The relationship between voltage and current for a non-linear capacitor is the following:                I   c     =       C        (     V   C     )       ·            V   c            t                 Eq.  2                                
     By comparing equations 1 and 2, a new relationship may be obtained (Eq. 3):                C        (     V   C     )       =     gm   ·     2     (     1   -     V     i                 n     2       )                 Eq.  3                                
     This equation (Eq. 3) gives a relationship between current and voltage that follows the required behavior, except for a k factor that could be easily added by inserting a gain stage before the logarithmic amplifier  2 . 
     One possible embodiment of the circuit  1  is shown in the schematic diagram of FIG.  2 . The logarithmic amplifier block  2  is implemented by a transconductance differential cell  9  having differential current inputs  3 ′,  3 ″ and corresponding current outputs  4 ′,  4 ″. The cell  9  has two symmetric transistors branches  9 ′,  9 ″ each coupled to a first voltage supply reference Vd through a current generator Ix, and to a second voltage reference GND through a resistor R 9 , or as an alternative, a current generator. 
     The transistors of each branch  9 ′,  9 ″ could be bipolar transistors, or a bipolar transistor and a MOS transistor. More specifically, two input MOS transistors and two out bipolar transistors are used in this embodiment. The current inputs  3 ′,  3 ″ are set between the current generator Ix and the gate electrode of the first transistor of each branch  9 ′,  9 ″ according to FIG.  2 . This is while the current outputs  4 ′,  4 ″ are set between the first and the second transistor of each branch. 
     Each current output  4 ′,  4 ″ is connected to the driving terminal of a bipolar transistor  5 ′,  5 ″ having the first conduction terminal respectively coupled to the first voltage reference Vd and to the second voltage reference GND. The second conduction terminal of each transistor  5 ′,  5 ″ is coupled to the second voltage reference GND through a resistor or a current generator. 
     The second conduction terminal of each transistor  5 ′,  5 ″ is also coupled through a capacitor C to a corresponding input terminal  10 ′,  10 ″ of a double ended gain stage  10  having a resistor R feedback connected between each output  11 ′,  11 ″ and each input. Both the output terminals  11 ′,  11 ′ of the gain stage  10  are connected to a double ended final gain block  16  having a gain factor G M . The outputs of the gain block  16  are feedback connected to the inputs terminals  3 ′,  3 ″ thus closing the feedback loop  7 . 
     A resistor Rx is connected between the source electrodes of the first transistors, and an input voltage Vs is applied to the driving terminals of the input MOS transistors of the first logarithmic amplifier block  2 . The activity of the electronic circuit  1  shown in FIG. 2 may be summarized by the following relationship:        Is   =           G   M     ·   R   ·   C   ·     V   T                    T            {     ln        (       1   +       V   s     RxIx         1   -     Vs   RxIx         )       }       =     Ceq             Vs          t                                  
     where Is is the input current, G M  is the gain value of the gain block  16 , Vs is the input voltage, Rx is the input resistance, Ix is the biasing current and Ceq is the equivalent capacitance value of the whole circuit  1  according to the following formula:        Ceq   =       C   ·           G   M     ·   R   ·   2          V   T         RxIx        [     1   -       (     Vs   RxIx     )     2       ]           =     Co     [     1   -       (     Vs   RxIx     )     2       ]                                
     The corresponding charge value is:        Q   =       ∫     Is   ·        t         =       C   ·   R   ·     G   H     ·     V   T                     ln        {       1   +     Vs   IxRx         1   -     Vs   IxRx         }                                
     Thus, the capacitance value when the voltage Vs=0 is:        Co   =     C   ·       aV   T     IxRx     ·     G   M     ·   R                            
     The graphs in FIGS. 3 and 4 show the evolution of the capacitance value Ceq and the charge value Q versus the voltage input Vs for the circuit as described above. 
     Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. We claim all modifications and variations within the scope of the following claims.