Abstract:
This invention is an implementation of a host channel adapter and method for transferring packet data over a network. When packets are distributed by a packet-switching system, a control unit and a plurality of header buffers allow the packet transmission to be carried out efficiently in executing the actions of reading and moving the packets. This reduces repetitions in reading and moving the packets, which enables the host channel adapter to use the bandwidth of the memory efficiently through the help of the control unit.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This present invention relates to a method and device for transceiving data packets via a communication network, and more specifically to a host channel adapter (HCA) and a method therefore that utilizes a plurality of header buffers and a control unit to enhance the efficiency of packet transceiving.  
           [0003]    2. Description of the Prior Art  
           [0004]    Under a data communication network environment, the host channel adapter (HCA) is used to receive packet information transmitted by peripheral devices to the packet-switching network. The information is then transferred to memory connected with a CPU. The hardware module within the HCA supports various interfaces by using static random access memory (SRAM) as packet buffer for packet-switching and storage between the host lines interface and the network. As packets transmitted by the physical layer transfers from the HCA to the host memory, packets are temporarily stored in SRAM and read by dynamic random access memory (DRAM) later. Since the bandwidth of SRAM is shared by direct access memory and transceiving links, repeated memory accessing between SRAM and DRAM will increase the time in reading and moving the packet data and further affect the overall transmission process.  
           [0005]    Therefore, an object of the present invention is to provide a HCA and a method for efficient processing of packet headers during packet-switching by using a plurality of header buffers under a multi-port transmission network.  
           [0006]    Another object of the present invention is to provide a HCA and a method for dynamic management of packet transceiving under a multi-port transmission network.  
         SUMMARY OF THE INVENTION  
         [0007]    In prior arts, repeated memory accessing between SRAM and DRAM during packet-switching will not only increase the time in reading and moving the packet data but also affect the overall transmission process. This results in a low level of system load efficiency. Moreover, even SRAM and DRAM are replaced by other higher speed memories, the defects induced by repeated memory accessing still are unavoidable.  
           [0008]    The present invention provides a HCA and a packet transceiving method under multi-port transmission network. The method for receiving packet is implemented in a HCA of a packet-switching system. The HCA enables the connection of CPU to InfiniBand fabric network. The packet transceiving method includes the following steps: storing received packets in memory (such as SRAM); copying packet headers into header buffers in HCA, waiting for local processor (such as receiving processor) to process the packet headers; and transmitting packet headers of unprocessed packets in memory header into buffers when the header buffers are not full.  
           [0009]    In one of the preferred embodiments of the present invention, a HCA is implemented in a packet-switching system, which enables the connection of CPU to the InfiniBand fabric network. The HCA supports Multi-port PHY interface, a SRAM interface, a DRAM interface and a processor interface. The HCA includes header buffers for temporary storage of packet headers. The header buffers increase the speed of the processor in dealing with packet loading. The HCA also includes a control unit for monitoring the load transceiving of the header buffers and controlling that headers of unprocessed packets are stored in unfull (which means empty or partially full) header buffers. This allows the HCA to dynamically adjust the mechanism of packet transceiving which leads to an optimal load transceiving and efficient packet receiving. 
       
    
    
       [0010]    The advantages and features of the HCA device and its relevant method are further explained in the following detailed descriptions and figures.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a block diagram of the host channel adapter (HCA) packet receiving device according to the prior art.  
         [0012]    [0012]FIG. 2 is a block diagram of packet receiving according to a preferred embodiment of the present invention.  
         [0013]    [0013]FIG. 3 is the block diagram of packet receiving according to another preferred embodiment of the present invention.  
         [0014]    [0014]FIG. 4 is a block diagram of packet receiving according to the other preferred embodiment of the present invention.  
         [0015]    [0015]FIG. 5 is a state mechanism table of packet header transmission.  
         [0016]    [0016]FIG. 6 is a state mechanism table of the control unit in dynamic management.  
         [0017]    [0017]FIG. 7 is a schematic diagram of the implementation in packet receiving according to the present invention.  
         [0018]    [0018]FIG. 8 is a circuit diagram of packet receiving control unit according to the present invention.  
         [0019]    [0019]FIG. 9 is a state diagram of packet receiving control unit according to the present invention. 
     
    
     REFERENCE NUMERALS DESCRIPTION  
       [0020]    [0020] 1 —Host channel adapter (HCA)  
         [0021]    [0021] 2 —Physical layer device  
         [0022]    [0022] 3 —Static random access memory (SRAM)  
         [0023]    [0023] 4 —Dynamic random access memory (DRAM)  
         [0024]    [0024] 5 —Read selector  
         [0025]    [0025] 7 —Receiving processor  
         [0026]    [0026] 8 —Transmitting processor  
         [0027]    [0027] 9 —Header buffers  
         [0028]    [0028] 10 —Control unit  
         [0029]    [0029] 101 —IDLE  
         [0030]    [0030] 102 —FIFO ACT  
         [0031]    [0031] 103 —FIFO FULL  
         [0032]    [0032] 104 —BUF 2  FIFO  
         [0033]    [0033] 105 —BUF FULL  
       DETAILED DESCRIPTION OF THE INVENTION  
       [0034]    Although some preferred embodiments are given in detailed description with appropriate figures, it will be apparent to those skilled in the art that the implementation may be altered in many ways without departing from the scope of the invention. Further, the scope of the invention should be only decided by the following claims.  
         [0035]    Please refer to FIG. 1 which illustrates a block diagram of a HCA ( 1 ) in packet receiving. The hardware module in the HCA ( 1 ) supports two-port or multi-port PHY interface that receives packets from the physical layer device. The SRAM interface is coupled to a DRAM ( 3 ) and is used for packet-switching and storage between a host lines interface and a network. The processor interface is coupled to a receiving processor ( 7 ) and a transmitting processor ( 8 ) for managing packet receiving and transmission. The DRAM interface is coupled to a DRAM ( 4 ) which is shared by the receiving processor ( 7 ) and the transmitting processor ( 8 ). Thence, the HCA ( 1 ) makes use of the high-speed feature of SRAM as data buffers.  
         [0036]    Continuing from FIG. 1, the hardware module in the HCA ( 1 ) consists of multiple DMA engines. The DMA engines controlled by the local processor handle data transmission between SRAM ( 3 ) and DRAM ( 4 ). Each physical layer port has two corresponding hardware engines, one for transmission and another for receiving. The functionality of the HCA ( 1 ), as an example, is to enable the connection of the host CPU to the InfiniBand fabric network.  
         [0037]    The packet transceiving device and method are mainly used in the environment of InfiniBand fabric network. The InfiniBand fabric network covers the first physical layer, second data link layer, third network layer, and fourth transport layer in the protocol of the seven layer OSI (open system interconnect) reference model. The purpose is to completely remove complex I/O data streams and signal distribution/exchange from the server and replace it with a node to node management. This reduces the required resource and eliminates the repetitions in decoding, encoding, and parsing of packet headers on many medium/large internet servers or clustered system operations. The result leads to a more efficient and faster internet service. InfiniBand fabric network performs one-to-one or one-to-many I/O access management by using the node to node management. Some of the nodes can be defined as subnets and authorized to control any information streams and configurations below. From the specifications, InfiniBand fabric network can achieve a speed of 2.5 Gbps with a single node, 10 Gbps with four nodes, and theoretically 30 Gbps with a maximum of twelve nodes. InfiniBand fabric network consists of internal crossbar switch architecture that supports cut-through switching. It can be used in copper wire and optical fiber medians. The supported products and applications range from server, switch, router, interface card, to end-point manager software . . . etc.  
         [0038]    Please refer to FIG. 2 in conjunction with FIG. 1 for the block diagram of an embodiment herein. The packet receiving device and method are used to resolve the increase of packet access between SRAM ( 3 ) and DRAM ( 4 ) when the receiving processor ( 7 ) performs packet transceiving after the HCA receives the packets in FIG. 1. FIG. 2 depicts the novel architecture of the present invention: at least the pocket headers of the packets are copied to DRAM( 4 ) while the packets are appeared on the PHY interface and received by the HCA( 1 ). Therefore, when the receiving processor ( 7 ) performs data access, the number of accesses to the SRAM ( 3 ) can be effectively reduced for the existence of the packet headers (or even other portions of the packets).  
         [0039]    Please refer to FIG. 3 in conjunction with FIG. 2 for the block diagram of another preferred embodiment herein. As shown by the architecture in FIG. 2, the HCA ( 1 ) has several (two in this implementation) header buffers ( 9 ) for temporary storage of packet headers in order to increase the load transceiving speed of the processor. When a packet arrives, the HCA ( 1 ) will duplicate the header of the packet and store it in priority to the header buffers ( 9 ). This provides fast transceiving of the receiving processor ( 7 ) through packet access of the processor interface. At the same time, the packet will be saved temporarily in SRAM ( 3 ). Moreover, once the header buffers ( 9 ) are full, new packet headers will only be stored in DRAM. The hardware architecture of the header buffers ( 9 ) can be static random access units, latches, or flip-flops... etc. Moreover, only packet headers need to be stored, which requires very little space and therefore the executing speed is fast. This will prevent the receiving processor ( 7 ) from taking up the bandwidth of SRAM ( 3 ) when accessing packet headers. Hence, the overall packet transceiving efficiency is increased.  
         [0040]    Please refer to FIG. 4 in conjunction with FIG. 3 for the block diagram of the other preferred embodiment herein. In order to solve the problem that occurs when the header buffers are full in FIG. 3, a control unit ( 10 ) can be used. This control unit ( 1 ) is able to dynamically manage the packet headers received by the header buffers ( 9 ). When the header buffers ( 9 ) have a space after the receiving processor ( 7 ) fetching packet headers, the control unit ( 1 ) will automatically signal the SRAM ( 3 ) and temporarily store headers of unprocessed packets from the SRAM ( 3 ) into the header buffers ( 9 ). This allows the receiving processor ( 7 ) to process the packets in an efficient and timely fashion through dynamic management of the header buffers by the control unit ( 10 ).  
         [0041]    Please refer to FIG. 5 in conjunction with FIG. 4 for a state mechanism table of the packet header transmission herein. When packets enter the HCA ( 1 ) from the physical layer device ( 2 ), there are four kinds of status. The first status, labeled as 0 in FIG. 5, is when both the header buffers ( 9 ) and the SRAM are empty. Received packets will be stored temporarily in both the header buffers ( 9 ) and the SRAM ( 3 ). The second status, labeled as 1 in FIG. 5, is when only the header buffers ( 9 ) are full. In this case, packet headers will not longer be sent to the header buffers ( 9 ) but stored in the SRAM ( 3 ) directly. The third status is when the header buffers ( 9 ) become unfull after transceiving previously stored packet headers. Unprocessed packet headers stored in SRAM ( 3 ) will be processed in priority because the header buffers ( 9 ) were previously full. Therefore, in order to maintain the sequence, when new packets arrive, they will be sent to SRAM ( 3 ) only. The last status occurs when both the header buffers ( 3 ) and SRAM ( 3 ) are full. Received packets will be discarded in this case.  
         [0042]    In short, for the prior arts, because packets have different lengths, they need to be completely stored in SRAM ( 3 ) before the headers can be fetched and processed. Apparently, this occupies a certain amount of bandwidth from SRAM ( 3 ). In contrast, for this invention, a plurality of header buffers can be used to store and directly provide the headers for fetching and processing. Hence, the present invention effectively overcomes the problem of storing packets completely in SRAM ( 3 ) before they can be processed.  
         [0043]    Please refer to FIG. 6 in conjunction with FIG. 4 and FIG. 5 for a state mechanism table of the control unit in dynamic management of packets. Under different conditions, the header buffers ( 9 ) can access packet headers from the physical layer device ( 2 ) or SRAM ( 3 ). The first status is when the physical layer device ( 2 ) has not received any packets and the SRAM ( 3 ) has no packets. In this case, the control unit ( 10 ) is idle. The second status occurs when the physical layer device ( 2 ) starts to receive packets and the SRAM ( 3 ) does not need to process packets in priority because of the header buffers ( 9 ) are not full. In this case, the control unit ( 10 ) allows packet headers from the physical layer device ( 2 ) to be stored directly into the header buffers ( 9 ). The third status is when the header buffers were previously full and unprocessed packets still reside in SRAM ( 3 ). Now that the header buffers ( 9 ) are unfull, the control unit ( 10 ) will automatically send the unprocessed packet headers from the SRAM ( 3 ) to the header buffers ( 9 ). The last status is when both the header buffers ( 9 ) and the SRAM ( 3 ) are full. The control unit ( 10 ) will not signal the SRAM ( 3 ) to fetch new packet headers and instead the packets are discarded. Please refer to FIG. 7 in conjunction with FIG. 4 for an illustration of transmission and related signals between the header buffers, the SRAM, and the physical layer. Each header buffer usually has a FIFO architecture. When the receiving processor ( 7 ) reads packet headers, the header buffers ( 9 ) will send its packet headers received in priority to the receiving processor ( 7 ). The header buffers ( 9 ) can be static random access units, latches, flip-flops or other memory. For example, the header buffers ( 9 ) can receive FIFO_Pop and FIFO_Push signals for executing the pop actions of reading packet headers and the push action of writing packet headers, respectively. The buffers will also output a FIFO_Full signal when header buffers ( 9 ) are full. The control unit ( 10 ) manages the source of packet headers received by the header buffers ( 9 ) through a read selector ( 5 ) which is responsible for selecting packet headers from either the SRAM ( 3 ) or the physical layer device ( 2 ).  
         [0044]    At the beginning, when packets enter the physical layer device ( 2 ), the control unit ( 10 ) stores the packet headers temporarily in the header buffers ( 9 ). Meanwhile, packet data is stored temporarily in SRAM ( 3 ). At this time, the read selector ( 5 ) enables the packet headers to be transferred from the physical layer device ( 2 ) to the header buffers ( 9 ). When the header buffers ( 9 ) become full, the control unit ( 1 ) no long sends packet headers to the buffers but directly to the SRAM ( 3 ). After the header buffers ( 9 ) finish transceiving previous packet headers, the read selector ( 5 ) will access in priority the packet headers sent to the SRAM ( 3 ) because the header buffers were previously full. Packets received afterwards will be sent to the SRAM ( 3 ) in order to maintain a transceiving sequence. When both the header buffers ( 9 ) and the SRAM ( 3 ) are full, the packets will be dropped.  
         [0045]    Please refer to FIG. 8 in conjunction with FIG. 7 for a circuit diagram of the control unit. Besides FIFO_Full and FIFO_Push signals to the header buffers ( 9 ), the control unit ( 10 ) also receives a Packet_Arriving signal to the physical layer device ( 2 ) for indicating packets have arrived at the physical layer device. The control unit ( 10 ) also sends in Buf_Full and Buf_Empty signals to the SRAM ( 3 ) for indicating the full status and the empty status respectively. The control unit ( 10 ) also outputs Buf_Read and Buf Write signals for controlling the SRAM ( 3 ) in reading packet headers and writing packet data. Furthermore, the control unit ( 10 ) outputs a FIFO_DIN_SEL signal to control the read selector ( 5 ) in choosing the source of packet headers to the header buffers ( 9 ) from either the SRAM ( 3 ) or the physical layer device ( 2 ).  
         [0046]    Please refer to FIG. 9 in conjunction FIG. 7 for a state diagram of the control unit. The state diagram has the following input and output signals:  
         [0047]    Input={Packet_Arriving, FIFO_Full, Buf_Full, Buf_Empty} 
         [0048]    Output={FIFO_Push, Buf_Read, Buf_Write, FIFO_DIN_SEL} 
         [0049]    As shown in FIG. 9, the implementation has the following state transitions:  
         [0050]    State  101 : IDLE  
         [0051]    When both the physical layer device ( 2 ) and the SRAM ( 3 ) are empty and no packets have been received, the control unit ( 10 ) inputs {0,0,0,0}. Once packets arrive at the physical layer device ( 2 ), the control unit inputs {1,0,X,X} (X: don&#39;t care) and transition to state  102  occurs. The control unit ( 10 ) will control the read selector ( 5 ) in choosing packet headers from the physical layer device ( 2 ), make a copy in the header buffers ( 9 ), and store the packet data temporarily in SRAM ( 3 ). The corresponding output is {1,0,1,0} in this case.  
         [0052]    State  102 : FIFO ACT  
         [0053]    State  102  indicates the operating status of the header buffer ( 9 ). When the input is kept as {1,0,X,X}, the control unit ( 10 ) controls the read selector ( 5 ) in choosing packet headers from the physical layer device ( 2 ) and stores the packet headers temporarily in the header buffers ( 9 ). At the same time, packet data will be replicated and stored temporarily in the SRAM ( 3 ), and then the output signal is {1,0,1,0}. When the input is {0,X,X,X}, it indicates no packets are present and the control unit ( 10 ) will remain in state  102 , and then the output signal is {0,0,0,0}. When the input is {X,1,X,X}, it indicates the header buffers ( 9 ) are full and transition to state  103  occurs. At this time, the output signal is {0,0,1,1}.  
         [0054]    State  103  : FIFO FULL  
         [0055]    State  103  indicates whether the header buffers ( 9 ) are full or not. When the input is {1,1,0,X}, the header buffers ( 9 ) are full. Packet data received afterwards will be sent directly to the SRAM ( 3 ) with an output of {0,0,1,1}. If the header buffers ( 9 ) become unfull after the receiving processor ( 7 ) fetches the packet headers, the input would be {X,0,0,X} and transition to state  104  occurs with an output of {1,1,1,1}. This allows packet headers stored in SRAM ( 3 ) are sent to the header buffers ( 9 ) because the header buffers were previously full. If the SRAM ( 3 ) becomes unfull after the packets are processed, the input is {0,X,0,1} and transition to state  102  occurs with an output of {0,0,0,0}. Lastly, if both the header buffers ( 9 ) and the SRAM ( 3 ) are full, the input would be {X,X,1,X} and transition to state  105  occurs with an output of {0,0,0,1}.  
         [0056]    State  104 : BUF 2  FIFO  
         [0057]    After a state transition from state  103  to state  104 , the header buffers ( 9 ) become unfull and the input is {0,0,X,0}. Since packet headers left in SRAM ( 3 ) when header buffers ( 9 ) were previously full are processed in priority, the corresponding output is {1,1,0,1}. As a result, packet headers will be sent from the SRAM ( 3 ) to the header buffers ( 9 ). When new packets arrive at the physical layer device ( 2 ) and the header buffers ( 9 ) are unfull, the input is {1,0,X,X} and the output of the control unit is {1,1,1,1}. This allows unprocessed packet headers in the SRAM ( 3 ) to be stored temporarily in the header buffers ( 9 ) and processed in priority. At the same time, packets received by the physical layer device ( 2 ) are written into SRAM ( 3 ) and the status is kept at State  104 . This continues until the header buffers ( 9 ) are full again, which produces input and output of {X,1,X,X} and {0,1,1,1} respectively at the control unit ( 10 ). Transition to state  103  occurs in this case.  
         [0058]    State  105 : BUF FULL  
         [0059]    State  105  occurs when the SRAM ( 3 ) is full. After a state transition from state  103  to state  105 , the input is {1,1,1,X} which indicates both the header buffers ( 9 ) and the SRAM ( 3 ) are full. The control unit ( 10 ) will not signal the SRAM ( 3 ) to read packet headers and packets received afterwards will be discarded, which means the output is {0,0,0,1}. When the input is {1,0,1,0}, it indicates the SRAM ( 3 ) is full but the header buffers ( 9 ) are unfull. In this case, when a packet header is transferred from the. SRAM ( 3 ) to the header buffers ( 9 ), a new packet can be stored in the SRAM ( 3 ); therefore, the corresponding output is {1,1,1,1}. When the input is {0,0,0,X}, which indicates the header buffers ( 9 ) are unfull and the SRAM ( 3 ) becomes unfull after being read, the corresponding output is {0,0,0,1} and transition moves back to state  103 . Finally, when the input is {X,X,X,1}, the similar discussion can find that the output is {0,0,0,1}.  
         [0060]    The packet transceiving device and method of the present invention provide many advantages and uniqueness. Specifically, the HCA ( 1 ) along with a plurality of header buffers can increase the efficiency of packet reading and transferring, which reduces the repetitions in transmission. Another advantage of the invention is the process of packet-switching in a multi-port transmission network. This includes the using of a control unit for dynamically managing the transceiving of packet headers, which leads to an optimal efficiency.  
         [0061]    As described above, this invention has many advantages and it resolves problems from conventional prior arts in both practice and application. The proposed methods are effective and can be implemented as a reliable system that achieves originality with great economical value.  
         [0062]    Although preferred embodiments are given in detailed description with appropriate figures, it will be apparent to those skilled in the art that the implementation may be altered in many ways without departing from the scope of the invention. Accordingly, the scope of the invention should be determined by the following claims and their legal equivalents.