Abstract:
The invention concerns a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration.

Description:
FIELD 
     The present disclosure relates to a memory device comprising non-volatile data storage elements, and to a method of storing data by programming non-volatile data storage elements of a memory device. 
     BACKGROUND 
     It has been proposed to use programmable resistive elements in memory cells to provide non-volatile data storage. Such resistive elements are programmable to adopt one of a plurality of different resistive states. The programmed resistive state is maintained even when a supply voltage of the memory cell is disconnected, and thus data can be stored by such elements in a non-volatile fashion. 
     Various types of resistive elements have been proposed, some of which are capable of being programmed by the direction of a current that is passed through them. An example of such a current-programmable resistive element is an STT (spin transfer torque) element, which is based on magnetic tunnel junctions (MTJs). 
     Such non-volatile elements are generally associated with a minimum data retention duration during which the data stored by these elements can be reliably retrieved. While it is possible to provide non-volatile elements with relatively long data retention durations, for example of several years or more, the longer the retention duration, the more energy consuming a write operation of the elements tends to be. 
     There is a need in the art for a memory device providing improved energy efficiency during write operations. 
     SUMMARY 
     It is an aim of embodiments of the present description to at least partially address one or more problems in the prior art. 
     According to one aspect, there is provided a memory device comprising: a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second resistive memory cell comprising a second non-volatile data storage element programmable to store a second bit of data; wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration. 
     According to one embodiment, the second data retention duration is at least 50 percent shorter or longer than the first data retention duration. 
     According to one embodiment, the second data retention duration is at least 10 times shorter or longer than said first data retention duration. 
     According to one embodiment, a physical characteristic of the first resistive element is different from a corresponding physical characteristic of the second resistive element. 
     According to one embodiment, at least one dimension of said first resistive element is different from a corresponding dimension of said second resistive element. 
     According to one embodiment, the first memory cell comprises a first data latch coupled to said first resistive element; and the second memory cell comprises a second data latch coupled to the second resistive element and to the first data latch. 
     According to one embodiment, a data storage node of the first data latch is coupled to an input node of the memory device for receiving an input data signal, and a data storage node of the second data latch is coupled to an output node of the memory device. 
     According to one embodiment, the first resistive element is programmable to have one of at least two resistive states and the first memory cell comprises a third resistive element, the first bit of data being represented by the relative resistances of the first and third resistive elements; and the second resistive element is programmable to have one of at least two resistive states and the second memory cell comprises a fourth resistive element, the second bit of data being represented by the relative resistances of the second and fourth resistive elements. 
     According to one embodiment, the first resistive element is coupled between a first storage node of the first data latch and a first intermediate node, and the third resistive element is coupled between a second storage node of the first data latch and a second intermediate node, the first memory cell further comprising: a first transistor of the first latch coupled between the first storage node and a first supply voltage; a second transistor of the first latch coupled between the second storage node and the first supply voltage, wherein a control node of the first transistor is coupled to the second storage node and a control node of said second transistor is coupled to said first storage node; a third transistor coupled between the first and second intermediate nodes; and control circuitry configured to active said third transistor while applying a second supply voltage to said first or second storage node to generate a programming current in a selected direction through said first and third resistive elements to program the resistive state of at least one of said elements. 
     According to one embodiment, the memory device further comprises: a fourth transistor coupled between said first intermediate node and said second supply voltage; and a fifth transistor coupled between said second intermediate node and said second supply voltage, wherein said control circuitry is further configured to transfer the data value represented by the resistive states of said first and third resistive elements to said first and second storage nodes by activating said fourth and fifth transistors. 
     According to one embodiment, the first and second memory cells are each coupled to read-write circuitry comprising a latch and configured to transfer data between said first and second memory cells. 
     According to one embodiment, the first memory cell is coupled to the read-write circuitry via first and second bit lines, and wherein the second memory cell is coupled to the read-write circuitry via third and fourth bit lines. 
     According to one embodiment, each of the first and second resistive elements is one of: a spin transfer torque element with in-plane anisotropy; a spin transfer torque element with perpendicular-to-plane anisotropy; a thermally assisted switching element; a reduction oxide (RedOx) element; a ferro-electric element; and a phase change element. 
     According to one embodiment, the first and second resistive elements are each spin transfer torque elements with in-plane anisotropy or perpendicular-to-plane anisotropy and formed of a plurality of stacked layers, wherein the volume of at least one of the layers of said first resistive element is different from a corresponding layer of said second resistive element. 
     According to one aspect, there is provided a method of storing an input data value in non-volatile storage of a memory device, the memory device comprising a first memory cell comprising a first resistive non-volatile data storage element programmable to store a first bit of data; and a second memory cell comprising a second resistive non-volatile data storage element programmable to store a second bit of data, wherein said first resistive element is configured to have a first data retention duration, and said second resistive element is configured to have a second data retention duration different from said first data retention duration, the method comprising: selecting, based on a data retention duration associated with said input data value, one of said first and second resistive elements; and programming the selected resistive element to store the input data value. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other features and advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation with reference to the accompanying drawings, in which: 
         FIG. 1A  schematically illustrates a memory device according to an embodiment of the present disclosure; 
         FIG. 1B  is a timing diagram illustrating data stored by the device of  FIG. 1  according to an example embodiment; 
         FIG. 2  schematically illustrates the device of  FIG. 1A  in more detail according to an example embodiment of the present disclosure; 
         FIGS. 3A and 3B  are timing diagrams representing signals in the circuit of  FIG. 2  during a data transfer phase according to an example embodiment of the present disclosure; 
         FIGS. 4A and 4B  are timing diagrams representing signals in the circuit of  FIG. 2  during a write phase according to an example embodiment of the present disclosure; 
         FIG. 5  schematically illustrates the device of  FIG. 1A  in more detail according to a further example embodiment of the present disclosure; 
         FIG. 6A  is a timing diagram representing signals in the circuit of  FIG. 5  during a write phase according to an example embodiment of the present disclosure; 
         FIG. 6B  is a timing diagram representing signals in the circuit of  FIG. 5  during a data transfer phase according to an example embodiment of the present disclosure; 
         FIGS. 7A and 7B  illustrate resistive elements based on magnetic tunnel junctions according to example embodiments of the present disclosure; 
         FIG. 8  schematically illustrates the device of  FIG. 1A  in more detail according to a further example embodiment of the present disclosure; 
         FIGS. 9A and 9B  are flow diagrams illustrating steps in methods of transferring data in the device of  FIG. 8 ; and 
         FIG. 10  schematically illustrates the device of  FIG. 1A  in more detail according to yet a further example embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Throughout the following description, specific embodiments are described in which the resistive states of non-volatile resistive elements of the memory cells are programmed by the direction of a current that is passed through them. It will however be apparent to those skilled in the art how the principles described herein could be equally applied to other types of non-volatile elements, such as those programmed by the direction of a magnetic field or by the magnitude of a current passed through them, and elements storing data in other forms than a programmed resistance. 
       FIG. 1  schematically illustrates a memory device  100  according to an example embodiment. 
     Device  100  comprises memory cells  102  and  104 . Memory cell  102  has inputs for receiving a data signal D 1  and a write phase signal W 1 , and an output for providing output data OUT 1 . Memory cell  104  has inputs for receiving a data signal D 2  and a write phase signal W 2 , and an output for providing output data OUT 2 . 
     The device  100  for example receives input data D, and provides output data OUT. The value of the input data values D 1  and D 2  to the memory cells may be equal to the input data D, or one or both of data values D 1 , D 2  may be independent of this data value. 
     The memory cell  102  comprises at least one non-volatile data storage element  106 A that stores a bit of data D NV1  in a non-volatile fashion. Similarly, the memory cell  104  comprises at least one non-volatile data storage element  106 B that stores a bit of data D NV2  in a non-volatile fashion. As will become apparent from the specific embodiments described below, the values of the data bits D NV1  and D NV2  may be entirely independent of each other. 
     The elements  106 A,  106 B are any type of non-volatile storage element. For example they can be a type of resistance switching element for which the resistance is programmable, for example by the direction of a current passed through them. In some embodiments, the resistive elements  106 A,  106 B are the same type of element as each other, but in other embodiments it would be possible to use different types of non-volatile elements to implement each of them. 
     The elements  106 A,  106 B are for example based on magnetic tunnel junctions (MTJs), such as field-induced magnetic switching (FIMS) elements, thermally assisted switching (TAS) elements, STT (spin-torque-transfer) elements, or those of Toggle MRAM. FIMS-MRAM (magnetic random access memory) are for example discussed in more detail in the publication titled “Magnetoresistive random access memory using magnetic tunnel junctions”, S. Tehrani, Proceedings of IEEE, 91(5):3707-714, May 2003. TAS-MRAM are for example discussed in more detail in the publication titled “Thermally Assisted MRAM”, Prejbeanu et al. 
     In another example described in more detail below with reference to  FIGS. 7A and 7B , the elements  106 A,  106 B are spin transfer torque elements with in-plane or perpendicular-to-plane anisotropy, as described in more detail in the publication entitled “Magnonic spin-transfer torque MRAM with low power, high speed, and error-free switching”, N. Mojumder et al., IEDM Tech. Digest (2010), and in the publication entitled “Electric toggling of magnets”, E. Tsymbal, Natural Materials Vol 11, January 2012. 
     Alternatively, the elements  106 A,  106 B could be other types of non-volatile storage elements such as resistance switching memory devices, including those used in programmable metallization cells (PMC), such as oxide resistive RAM (OxRRAM), conductive bridging RAM (CBRAM), FeRAM (Ferro-Electric RAM) or phase change RAM (PCRAM). As a further example, the elements  202 ,  204  could be those used in RedOx RAM (reduction oxide RAM), which are for example described in more detail in the publication entitled “Redox-Based Resistive Switching Memories—Nanoionic Mechanisms, Prospects and Challenges”, Rainer Waser et al., Advanced Materials 2009, 21, pages 2632 to 2663. 
     The write phase signal W 1  controls a write phase of the data D NV1  stored by the element  106 A, and the write phase signal W 2  controls a write phase of the data D NV2  stored by the element  106 B. 
     Each of the memory cells  102 ,  104  for example comprises circuitry implementing a data latch (not illustrated in  FIG. 1A ), and a clock signal CLK 1  may additionally be provided to the memory cell  102  to control the timing of when the input data signal D 1  is latched into the memory cell  102 , and a clock signal CLK 2  may additionally be provided to the memory cell  104  to control the timing of when the input data D 2  is latched into the memory cell  104 . 
     Each of the elements  106 A,  106 B is associated with a retention duration, corresponding to the duration that the data D NV1 , D NV2  is reliably stored by the respective element  106 A,  106 B. At the end of the retention duration, there is a significant probability that it will no longer be possible to retrieve the original data value. As will now be described in more detail with reference to  FIG. 1B , the resistive elements  106 A and  106 B have physical differences with respect to each other, meaning that the retention duration of element  106 A is not the same as the retention duration of element  106 B. 
       FIG. 1B  is a timing diagram illustrating the write signals W 1  and W 2 , and the data D NV1  and D NV2  of the memory cells  102  and  104  respectively according to an example embodiment. 
     As illustrated, a high pulse  110  of the write signal W 1  for example corresponds to a write phase of the memory cell  102  during which a data value D 1  is written to the element  106 A, such that the value of D NV1  becomes D 1  at the end of the high pulse  110 . It is then assumed that there is no new write phase, the resistive element  106 A maintaining the value D 1  until the end of its retention duration t 1 , which is for example between several seconds and several years. 
     A high pulse  112  of the write signal W 2  shortly after the high pulse  110  for example corresponds to a write phase of the memory cell  104  during which the data value D 2  is written to the element  106 B, such that the value of D NV2  becomes D 2  at the end of the high pulse  110 . It is again assumed that there is no new write phase, and the resistive element  106 B maintains the value D 2  until the end of its retention duration t 2 . As illustrated, the retention duration t 2  is longer than t 1 , but in alternative embodiments it could be shorter. For example the duration t 2  is at least 50 percent longer or shorter than t 1 . In some embodiments, the duration t 2  is at least 10 times longer or shorter than t 1 . In one example, t 1  is equal to 1 month or less and t 2  is equal to 12 months or more, or vice versa. 
     In some embodiments, a method of selecting the data retention duration of an input data value to be stored in a non-volatile fashion involves selectively programming the elements  106 A or  106 B with the input data value based on a desired retention duration. For example, a control signal is provided to the memory device  100  indicating the desired data retention duration for a given bit of data. For data values that are only needed to be stored for relatively short periods, the element having the lowest retention period can be selected, thereby economizing energy. 
     The memory device  100  of  FIG. 1  is for example any type of non-volatile memory device comprising a plurality of memory cells, and could be implemented as a sequential, combinational, synchronous or asynchronous memory device. For example, device  100  coupled correspond to a single memory array comprising the memory cells  102  and  104  as two of its addressable cells. Alternatively, one or more of the addressable cells of a memory device could comprise the memory device  100 . 
       FIG. 2  schematically illustrates the memory device  100  of  FIG. 1A  in more detail according to an example embodiment, in the case that device  100  is a synchronous device. In particular, in the example of  FIG. 2 , the memory cells  102 ,  104  are coupled together to form a flip-flop. 
     Each of the memory cells  102 ,  104  comprises a pair of resistive elements, labelled  202 A and  204 A in memory cell  102 , and  202 B and  204 B in memory cell  104 , forming the non-volatile data storage elements. A bit of data is for example stored in each memory cell in a non-volatile manner by setting one of the elements at a relatively high resistance R max , and the other at a relatively low resistance R min . In  FIG. 2 , the element  202 A and  204 B are shown programmed to have a resistance R max  and the elements  204 A and  202 B a resistance R min , and as shown by the references R min  and R max  in brackets, the opposite programming of the resistance values would be possible. 
     Each of the resistive elements  202 A,  204 A,  202 B,  204 B for example has just two resistive states corresponding to the high and low resistances R max  and R min , but the exact values of R min  and R max  may vary depending on conditions such as process, materials, temperature variations etc. 
     The non-volatile data bit represented by the resistive elements  202 A,  204 A, or by the resistive elements  202 B,  204 B, depends on which of the resistive elements is at the resistance R max  and R min , in other words on the relative resistances. The resistive elements are for example selected such that R max  is always significantly greater than R min , for example at least 20 percent greater. In general, the ratio between the resistance R max  and the resistance R min  is for example between 1.2 and 10000. R min  is for example in the region of 2 k ohms or less, and R max  is for example in the region of 6 k ohms or more, although many other values are possible 
     It will be apparent to those skilled in the art that in some embodiments, rather than both of the resistive elements  202 A,  204 A of the memory cell  102  being programmable, only one can be programmable. Similarly, rather than both of the resistive elements  202 B,  204 B of the memory cell  104  being programmable, only one can be programmable. In such cases, the other resistive element of each memory cell for example has a fixed resistance at an intermediate level around halfway between R min  and R max , for example equal, within a 10 percent tolerance, to (R min +(R max −R min )/2). For example, one of the resistive elements  202 A,  204 A and/or  202 B,  204 B, could correspond to a resistor of fixed resistance. Alternatively, one of the resistive elements  202 A,  204 A and/or  202 B,  204 B could be formed of a pair of programmable resistive elements coupled in parallel with each other and in opposite orientations, such that irrespective of the sense in which each element is programmed, the resistance value remains relatively constant at the intermediate level. 
     Referring now to the memory cell  102 , the resistive element  202 A is coupled between a storage node  206 A and an intermediate node  208 A. The resistive element  204 A is coupled between a storage node  210 A and an intermediate node  212 A. The storage nodes  206 A and  210 A store voltages Q 1  and  Q 1    respectively. A pair of inverters is cross-coupled between the storage nodes  206 A and  210 A to form a data latch. Each inverter is formed by a single transistor  214 A,  216 A respectively. Transistor  214 A is for example an n-channel MOS (NMOS) transistor coupled by its main current nodes between node  206 A and ground. Transistor  216 A is for example an NMOS transistor coupled by its main current nodes between the storage node  210 A and ground. A control node of transistor  214 A is coupled to the storage node  210 A, and a control node of transistor  216 A is coupled to the storage node  206 A. The intermediate nodes  208 A and  212 A are coupled together via the main current nodes of an NMOS transistor  220 A. Transistor  220 A receives at its control node a signal AZ 1  described in more detail below. 
     The node  208 A is further coupled to a supply voltage V DD  via the main current nodes of a p-channel MOS (PMOS) transistor  222 A. Similarly, the node  212 A is coupled to the supply voltage V DD  via the main current nodes of a PMOS transistor  224 A. Control nodes of the PMOS transistors  222 A and  224 A are coupled together to a transfer signal TR 1  described in more detail below. 
     The memory cell  102  for example further comprises an inverter  225 A coupled between the storage node  206 A and the storage node  210 A, although in some embodiments this inverter could be omitted. 
     The memory cell  104  is for example substantially identical to the memory cell  102 , and the components have been labelled with like reference numerals, except that the “A” of each reference has been replaced by a “B”. As with the memory cell  102 , in some embodiments the inverter  225 B could be omitted. The voltage at storage nodes  206 B,  210 B are labelled Q 2  and  Q 2    respectively. Transistor  220 B is controlled by a signal AZ 2  and transistors  222 B and  224 B are controlled by a signal TR 2 . 
     The storage node  206 A receives an input data signal D via an NMOS transistor  228 . The storage node  210 A of memory cell  102  is for example coupled to the storage node  206 B of memory cell  104  via an NMOS transistor  230 . Transistor  228  is for example controlled by the clock signal CLK 1 , and transistors  230  and  226 B are for example controlled by the clock signal CLK 2 . 
       FIG. 2  also illustrates a control block  232 , providing the control signals TR 1 , TR 2 , AZ 1 , AZ 2 , CLK 1  and CLK 2  to the corresponding transistors of the memory cells  102 ,  104 . As illustrated, these control signals are for example generated based on the write signals W 1 , W 2  and transfer phase signals T 1  and T 2 . 
     In the memory cell  102 , each inverter of the data latch is implemented by a single transistor  214 A,  216 A, and the high state of Q 1  or  Q 1    is maintained by leakage current passing through the PMOS transistors  222 A or  224 A. The threshold voltages of the PMOS transistors  222 A and  224 A are chosen to be lower than those of NMOS transistors  214 A and  216 A respectively, such that when in the non-conducting state, the current leakage through transistors  222 A or  224 A is greater than through transistor  214 A or  216 A respectively, thereby keeping the corresponding node  206 A or  210 A at a voltage high enough to be seen as a high logic state. In other words, the leakage current I offP  flowing through PMOS transistor  222 A,  224 A when a high voltage is applied to the corresponding gate nodes is greater that the leakage current I offN  flowing through the corresponding NMOS transistor  214 A,  216 A when a low voltage is applied to its gate node. The particular threshold voltages will depend on the technology used. As an example, the threshold voltages of PMOS transistors  222 A,  224 A are chosen to be in the range 0.3 to 0.5 V, while the threshold voltages of NMOS transistors  214 A,  216 A are chosen to be in the range 0.4 to 0.6 V. In any case, the ratio I Offp /I Offn  is selected for example to be greater than 25, and preferably greater than 100. The above applies mutatis mutandis to the memory cell  104 . 
     Operation of the circuit of  FIG. 2  will now be described in more detail with reference to  FIGS. 3A and 3B , and  4 A and  4 B. 
     First, it should be noted that each of the memory cells  102 ,  104  is capable of storing, in a volatile fashion, a data bit that is independent of the programmed resistive states of the elements  202 A and  204 A or of elements  202 B and  204 B. Indeed, the latch formed by transistors  214 A/ 214 B and  216 A/ 216 B will maintain any stored state. 
       FIGS. 3A and 3B  are timing diagrams showing signals in the memory cell of  FIG. 2  during a transfer phase of the memory cells  102  and  104  respectively. 
       FIG. 3A  illustrates the data signals Q 1  and  Q 1    present at the storage nodes  206 A and  210 A, the transfer phase signal T 1 , the transfer signal TR 1 , and the signal AZ 1  during a transfer phase of the memory cell  102 . The transfer phase corresponds to an operation for transferring the data represented by the programmed resistive states of the resistive elements  202 A and  204 A to the storage nodes  206 A,  210 A. Thus, the data is transformed from being represented by programmed resistive states to being represented by voltage levels at the storage nodes  206 A and  210 A. The transfer phase involves setting the levels of the voltages Q 1  and  Q 1    based on the programmed resistive states. 
     In the example of  FIG. 3A , it is assumed that the resistive element  202 A has been programmed to have a high resistance R max , and the resistive element  204 A a low resistance R min . While not shown in  FIGS. 3A and 3B , during the transfer phase, the clock signals CLK 1  and CLK 2  for example remain low. It is also assumed that Q 1  and  Q 1    are initially at a high state and low state respectively. The term “high state” is used herein to designate a voltage level close to or at the level of the supply voltage V DD , while the term “low state” is used herein to designate a voltage level close to or at the ground voltage. The transfer signal TR 1  is for example initially high, such that transistors  222 A and  224 A are non-conducting. The signal AZ 1  is for example initially low, such that transistor  220 A is non-conducting. 
     The transfer phase signal T 1 , which is for example initially low, is asserted as shown by a rising edge  302 , triggering shortly thereafter a falling edge of the transfer signal TR 1 , and a rising edge of the signal AZ 1 , for example shortly after the falling edge of the transfer signal TR 1 . Thus the transistors  220 A,  222 A and  224 A are all activated, inducing a current in the left-hand and right-hand branches of the memory cell  102 . However, due to the difference in the resistances of the resistive elements  202 A and  204 A, the current in the left-hand branch is lower than the current in the right-hand branch. Thus these currents for example cause the voltage at storage node  206 A to fall and settle at a level V 1  below a level of metastability M, and the voltage at storage node  210 A to rise to a level V 2  above the level of metastability M. The level of metastability M is a theoretical voltage level approximately halfway between the high and low voltage states, representing the level from which there would be equal probability of Q 1  flipping to the high or low states. Asserting the signal AZ 1  to turn on transistor  220 A has the effect of speeding up the descent of the voltage level Q 1 , and the rise of the voltage level  Q 1   . 
     The signal AZ 1  is then brought low, and the transfer signal TR 1  is brought high again at a rising edge  304 , such that the levels of Q 1  and  Q 1    go to their closest stable state, which in the example of  FIG. 3A  corresponds to the low Q 1 , high  Q 1    state. However, it will be apparent to those skilled in the art that the levels V 1  and V 2 , and the final stable state, will depend on factors such as the on resistances of the transistors  214 A,  216 A,  222 A and  224 A. Finally, the transfer phase signal T 1  goes low to complete the transfer phase. 
       FIG. 3B  illustrates the data signals Q 2  and  Q 2    present at the storage nodes  206 B and  210 B, the transfer phase signal T 2 , the transfer signal TR 2 , and the signal AZ 2  during a transfer phase of the memory cell  104 . In the example of  FIG. 3B , it is assumed that the resistive element  202 B has been programmed to have a high resistance R max , and the resistive element  204 B a low resistance R min , and that the voltages Q 2  and  Q 2    are initially at a low state and high state respectively. The transfer phase signal T 2 , transfer signal TR 2  and the signal AZ 2  have the same forms as the corresponding signals in  FIG. 3A , and will not be described again. The difference with respect to  FIG. 3A  is that, when the signal TR 2  is brought low and the signal AZ 2  is brought high, the voltage Q 2  rises to the level V 1 , and the voltage  Q 2    falls to the level V 2 . After that, the levels of Q 2  and  Q 2    go to their closest stable state, which in the example of  FIG. 3B  corresponds to the low Q 2 , high  Q 2    state. Again it will be apparent to those skilled in the art that the levels V 1  and V 2 , and the final stable state, will depend on factors such as the on resistances of the transistors  214 B,  216 B,  222 B and  224 B. 
       FIG. 4A  is a timing diagram illustrating examples of the signals D, W 1 , AZ 1 , CLK 1 , Q 1  and  Q 1    in the memory cell  102  during a write phase of the resistive states of the resistive elements  202 A and  204 A. While not shown in  FIG. 4A  during the write phase, the transfer signal TR 1  for example remains high such that transistors  222 A and  224 A are non-conducting. 
     The write phase involves passing a current through each of the resistive elements  202 A,  204 A via the transistor  220 A, either in the direction from the storage node  206 A to the storage node  210 A, or the opposite direction. The resistive elements  202 A and  204 A are each orientated such that, for a given direction of current, they will be programmed to have opposite resistances. In particular, each resistive element  202 A,  204 A can be orientated in one of two ways between the corresponding storage node  206 A,  210 A and corresponding intermediate node  208 A,  212 A. In the case of an STT element, the orientation is determined by the order of a pinned layer and storage layer, as will be described in more detail below. The elements  202 A,  204 A are both for example orientated in the same way between these corresponding nodes, for example each having their pinned layer closest to the corresponding storage node  206 A,  210 A, such that they have opposite orientations with respect to a write current flowing from the storage node  206 A to storage node  210 A or vice versa. 
     Initially the signals AZ 1  and CLK 1  are low, and it is assumed that Q 1  is initially low, and  Q 1    is initially high. The data signal D at the input of the memory cell  102  is for example set to the value that is to be programmed in the memory cell, which in the example of  FIG. 4A  is a logic “1” after a rising edge  402 . 
     The write phase signal W 1  then goes high at a rising edge  404 , initiating the start of the write phase. This triggers, a short time later, a rising edge of the signal AZ 1 , such that the transistor  220 A is activated, coupling together the nodes  208 A and  212 A. Furthermore, shortly thereafter, the clock signal CLK 1  is asserted, such that Q 1  becomes equals to the data signal D. This causes a current to flow through the resistive elements  202 A and  204 A in a direction that will program their resistances in accordance with the logic “1” data value that is to be programmed. In the example of  FIG. 2 , a high state of a data value D for example corresponds to a high value of voltage Q 1 , and a resistance R min  of element  202 A, and a resistance R max  of element  204 A. After the current has been applied for a sufficiently long time to set the resistive states of elements  202 A and  204 A, for example for a duration t W  of between 0.1 ns and 20 ns, the signal AZ 1  is brought low, stopping the write current, and the signals W 1  is then for example brought low, ending the write phase. 
       FIG. 4B  is a timing diagram illustrating examples of the signals  Q 1   , W 2 , AZ 2 , CLK 2 , Q 2  and  Q 2    in the memory cell  104  during a write phase of the resistive states of the resistive elements  202 B and  204 B, in which the data value to be programmed is the logic “0” stored at the storage node  210 A during the write phase of the memory cell  102  illustrated in  FIG. 2 . A rising edge  408  of the write signal W 2  triggers a rising edge of the signal AZ 2  and CLK 2 , in order to generate a current from the storage node  210 B through the resistive elements  204 B and  202 B, to the storage node  206 B, for the duration t W . This programs a resistance R min  of element  202 B, and a resistance R max  of element  204 B. 
     The transistor  220 A is for example dimensioned such that the write current generated by activating this transistor is high enough to program the resistive states of elements  202 A and  204 A. Similarly, the transistor  220 B is for example dimensioned such that the write current generated by activating this transistor is high enough to program the resistive states of elements  202 B and  204 B. The dimensions of transistors  220 A and  220 B, and in particular at least their widths, are for example different from each other. For example, the width of transistor  220 A is for example at least 10 percent greater or less than the width of transistor  220 B. Indeed, in view of the different retention durations of the resistive elements  202 A,  204 A compared with the resistive elements  202 B,  204 B, the write currents in each of the memory cells  102 ,  104  are for example different. For example, a minimum programming current in each of the memory cells  102 ,  104  could for example by anything from 20 μA to 1.5 mA, and the programming current used in memory cell  102  is for example at least 10 percent greater or less than the programming current used in memory cell  104 . 
     Transistors  214 A,  216 A,  222 A and  224 A in memory cell  102  are for example dimensioned such that, during a transfer phase when the transfer signal TR 1  is activated, the level of current flowing through the resistive elements  202 A and  204 A is lower than that needed to program their resistive states, for example a level between 10 and 90 percent lower than the corresponding write current. Similarly, transistors  214 B,  216 B,  222 B and  224 B in memory cell  104  are for example dimensioned such that, during a transfer phase when the transfer signal TR 2  is activated, the level of current flowing through the resistive elements  202 B and  204 B is lower than that needed to program their resistive states, for example a level between 10 and 90 percent lower than the corresponding write current. 
       FIG. 4A  illustrates the case in which the data value of the data signal D at the input of the memory cell  102  is written to the resistive elements  202 A,  204 A by asserting the clock signal CLK 1 , and  FIG. 4B  illustrates the case in which the data value  Q 1    at the storage node  210 A is written to the resistive elements  202 B,  204 B by asserting the clock signal CLK 2 . In alternative embodiments, the clock signals CLK 1  and/or CLK 2  could remain inactive, and separate write circuitry (not illustrated in  FIG. 2 ) could be used to selectively apply a high voltage to the storage node  206 A or  210 A, and/or to the storage node  206 B or  210 B, to create the corresponding write current. 
       FIG. 5  schematically illustrates the device  100  of  FIG. 1A  in more detail according to a further example embodiment in the case that the memory device is a flip-flop. 
     In the embodiment of  FIG. 5 , the memory cell  102  comprises resistive elements  202 A,  204 A each having one terminal coupled to a common node  502 A, which is in turn coupled to ground via an NMOS transistor  504 A controlled by a signal  WR 1   . The other terminal of resistive element  202 A is coupled to an intermediate node  506 A, which is in turn coupled to a supply voltage V DD  via an NMOS transistor  508 A and a PMOS transistor  510 A coupled in series and forming an inverter. Similarly, the other terminal of resistive element  204 A is coupled to an intermediate node  512 A, which is in turn coupled to a supply voltage V DD  via an NMOS transistor  514 A and a PMOS transistor  516 A coupled in series and forming an inverter. The transistors  508 A,  510 A,  514 A and  516 A together form a data latch. The node  518 A between transistors  508 A and  510 A forms a storage node of the data latch storing a voltage Q 1 , and is coupled to the control nodes of transistors  514 A and  516 A. The node  520 A between transistors  512 A and  516 A forms another storage node of the latch storing a voltage  Q 1   , and is coupled to the control nodes of transistors  508 A and  510 A. The nodes  518 A,  520 A are further coupled together via an NMOS transistor  522 A controlled by a signal AZ 1 . 
     The memory cell  104  is for example substantially identical to the memory cell  102 , and the components have been labelled with like reference numerals, except that the “A” of each reference has been replaced by a “B”. The transistor  504 B is controlled by a signal  WR 2    and the transistor  522 B is controlled by a signal AZ 2 . The voltage at node  518 B is labelled Q 2 , and the voltage at node  520 B is labelled  Q 2   . 
     The storage node  518 A of memory cell  102  receives an input data signal D via an NMOS transistor  524  controlled by a clock signal CLK 1 . The storage node  520 A of memory cell  102  is coupled to the storage node  518 B of memory cell  104  via an NMOS transistor  526  controlled by a clock signal CLK 2 . A control block  526  is for example provided, which receives write phase signals W 1  and W 2 , and transfer phase signals T 1  and T 2 , and generates the control signals AZ 1 , AZ 2 ,  WR 1   ,  WR 2   , CLK 1  and CLK 2 . 
     The operation of the circuit of  FIG. 5  is similar to that of the circuit of  FIG. 2 , except that the data value D NV1  to be written to the resistive elements  202 A,  204 A is supplied via dedicated write circuitry (not illustrated in  FIG. 5 ) coupled to the nodes  506 A and  512 A during a write phase, and the data value D NV2  to be written to the resistive elements  202 B,  204 B is supplied via dedicated write circuitry (also not illustrated in  FIG. 5 ) coupled to the nodes  506 B,  512 B. 
     The operation of the circuit of  FIG. 5  during write and transfer phases will now be described in more detail with reference to  FIGS. 6A and 6B . 
       FIG. 6A  is a timing diagram illustrating the signals W 1 ,  WR 1    and D NV1  during a write phase of the resistive states of the resistive elements  202 A and  204 A of the memory cell  102  of  FIG. 5 . 
     The write phase signal W 1  for example goes high at a rising edge  602  at the start of the write phase, triggering a falling edge  604  of the signal  WR 1   , thereby deactivating transistor  504 A. Shortly afterwards, the data signal D NV1  is for example applied to the node  506 A, and its inverse to node  512 A, to generate a write current in a direction through the resistive elements  202 A and  204 A based on the data to be programmed. In the example of  FIG. 6A , a high voltage level is applied to node  506 A for a write period t w . For example, as represented by the letters NS, no signal is applied to the nodes  506 A and  512 A before and after the write period. At the end of the write period t w , the write phase signal W 1  for example goes low, which triggers rising edge of the signal  WR 1    to reactivate transistor  504 A. 
     A write phase of the resistive elements  202 B,  204 B of the memory cell  104  is for example implemented in the same fashion as that of the memory cell  102 . 
       FIG. 6B  is a timing diagram illustrating the signals T 1 , AZ 1  and CLK 2  during a transfer phase of the data represented by the resistive elements  202 A,  204 A in the memory cell  102  to the output OUT of the device. 
     During the transfer phase, the transistor  504 A for example remains activated. A transfer phase is for example initiated by a rising edge  602  of the transfer phase signal T 1 . This triggers, shortly thereafter, a rising edge of the signal AZ 1 , thereby activating transistor  522 A. This has the effect of equalizing to some extent the voltages at the storage nodes Q 1  and  Q 1   , and causing a current to flow through the left-hand and right-hand branches of the memory cell  102 . When the signal AZ 1  is brought low by a falling edge  608 , the storage nodes Q 1  and  Q 1    will go to their closest stable state based on the relative resistances of the elements  202 A and  204 A. The transfer phase signal T 1  then for example goes low, ending the transfer phase. 
     The transferred data is then for example provided at the output of the device by asserting the clock signal CLK 2  to write the value at the storage node  520 A to the storage node  518 B. 
       FIGS. 7A and 7B  illustrate examples of the structures of resistive spin transfer torque (STT) elements having different retention times according to an example embodiment. For example, the resistive elements  106 A,  202 A and  204 A described herein each has a structure corresponding to that of  FIG. 7A , and the resistive elements  106 B,  202 B,  204 B described herein each has a structure corresponding to that of  FIG. 7B , or vice versa. 
       FIG. 7A  illustrates an STT resistive element  700  with in-plane magnetic anisotropy. The element  700  is for example substantially cylindrical, but has a cross-section which is non-circular, for example oval, with a maximum diameter d max1  greater than a minimum diameter d min1 . The element  700  comprises bottom and top electrodes  702  and  704 , each being substantially disc-shaped, and sandwiching a number of intermediate layers between them. The intermediate layers comprise, from bottom to top, a pinned layer  706 , an oxidation barrier  708 , and a storage layer  710 . 
     The oxidation barrier  708  is for example formed of MgO or Al x O y . The pinned layer  706  and storage layer  710  are for example ferromagnetic materials, such as CoFe. The spin direction in the pinned layer  706  is fixed, as represented by an arrow from left to right in  FIG. 7A . Of course, in alternative embodiments the spin direction could be from right to left in the pinned layer  706 . However, the spin direction in the storage layer  710  can be changed, as represented by arrows in opposing directions in  FIG. 7A . The spin direction is programmed by the direction of the write current I passed through the element, such that the spin direction in the storage layer is parallel, in other words in the same direction, or anti-parallel, in other words in the opposite direction, to that of the pinned layer  706 . 
       FIG. 7B  illustrates an STT resistive element  720  also with in-plane magnetic anisotropy. Again, element  720  is substantially cylindrical, but for example has a cross-section which is non-circular, for example oval, with a maximum diameter d max2  greater than a minimum diameter d min2 . Otherwise, the layers forming the element  720  are the same as those forming the element  700 , and have been labelled with like reference numerals and will not be described again in detail. 
     The ratio between the minimum and maximum diameters d max1 /d min1  of element  700  is for example greater than the corresponding ratio d max2 /d min2  of element  720 . In other words, d max1  is greater than d max2  and/or d min1  is less than d min2 . This leads to a longer data retention duration of element  700  when compared to element  720 . 
     While in the examples of  FIGS. 7A and 7B , the resistive elements  700  and  720  are illustrated as having cross-sections that are oval in shape, in alternative embodiments other forms would be possible, such as rectangular. 
     It will be apparent to those skilled in the art that it would be possible to achieve a difference in the retention duration between the memory cells  102  and  104  in alternative ways to the examples of  FIGS. 7A and 7B , depending on the particular technology employed for forming the elements. In general, the retention duration of a resistive element is a function of the product KV, where K is specific to the material or to its aspect ratio for the magnetic layers of an element with in-plane magnetic anisotropy, and V is the volume of the storage layer. Thus the retention duration of a resistive element is dependent on the size, shape, thickness of its storage layer and the types of materials used to form its layers. In some embodiments, the difference between the retention duration of the memory cell  102 ,  104  is brought about by providing a difference in one or more corresponding dimensions of the resistive elements of each memory cell, such as the thickness and/or volume of the storage layer. Additionally or alternatively, the difference in the retention durations could be achieved by a difference in the material used to form one or more of the layers of the resistive elements of each cell. For example, a pinned and/or storage layer of the resistive elements of each memory cell  102 ,  104  could be formed by a different appropriate combination of materials selected among the list: Co, Pt, Cr, Pd, Ni, Ta, Fe, B, MgO and AlOx. 
     For example, in another embodiment, the non-volatile data storage elements  106 A,  106 B are implemented by STT resistive elements with perpendicular-to-plane magnetic anisotropy. Such a type of programmable resistive element has a layered structured very similar to the in-plane elements of  FIGS. 7A and 7B , but is advantageous as it may in general be programmed by a lower write current. For this type of resistive element, the difference in the retention duration between the memory cells  102  and  104  is for example achieved by a difference in the volume of at least one of the layers forming the resistive elements. For example, the thicknesses of the storage layers of the STT elements are different from each other. 
       FIG. 8  schematically illustrates the memory device  100  of  FIG. 1A  in more detail according to a further example embodiment, in the case that device  100  is a memory array. 
     In the device of  FIG. 8 , the memory cell  102  comprises a resistive element  802 A forming the non-volatile data storage element of the cell and for example having a relatively low retention duration LR, and the memory cell  104  comprises a resistive element  802 B forming the non-volatile data storage element of the cell and for example having a relatively high retention duration HR. 
     The elements  802 A,  802 B are each coupled in series with a respective selection transistor  804 A,  804 B between bit lines  806  and  808 . While only two memory cells  102 ,  104  are illustrated in  FIG. 8 , there could be any number of such cells coupled between the bit lines  806 ,  808 . In some embodiments, there are an equal number of LR cells  102  and HR cells  104 . In some embodiments there could also be other cells having yet another retention duration, for example between that of the LR and HR cells. Furthermore, the circuit of each cell  102  shown in  FIG. 8  is merely one example, many other arrangements being possible, including differential arrangements with two resistive elements similar to the cells illustrated in  FIG. 2 . 
     The bit lines  806 ,  808  are each coupled to read-write circuitry  810 , which allow data to be written to and read from the memory cells  102 ,  104 . The read-write circuitry  810  for example comprises a comparator  812 , having an input coupled to the bit line  808 , and an output coupled to a latch  814 . The latch  814  for example receives a data signal D, representing data to be stored in the memory array, and outputs data Q read from a memory cell. The latch  814  is in turn coupled to drive elements  816 ,  818 , that have their outputs coupled to the bit lines  806  and  808  respectively. 
     A control block  820  controls the latch  814  and generates selection signal C 1  and C 2  for controlling the selection transistors  804 A,  804 B respectively. The control block  820  for example receives a signal “SAVE”, indicating when data is to be transferred from one or more LR cells  102  to one or more HR cells  104 , and a signal “LOW P” indicating when data is to be transferred from one or more HR cells  104  to one or more LR cells  102 . 
     In operation, during a write phase, data can be written to an LR or HR cell, as determined by the signal W 1  and W 2 . 
     When the write signal W 1  is asserted, the data signal D is stored in the latch  814 , and then for example written to the LR cell  102 . This is for example achieved by activating the selection transistor  804 A, and applying by the drive elements  816 ,  818  a current of a magnitude and/or direction for programming the element  802 A based on the data stored in the latch. 
     When the write signal W 2  is asserted, the data signal D is stored in the latch  814 , and then for example written to the HR cell  104 . This is for example achieved by activating the selection transistor  804 B, and applying by the drive elements  816 ,  818  a current of a magnitude and/or direction for programming the element  802 B based on the data stored in the latch. 
     During a read phase, a cell to be read is selected by activating the corresponding selection transistor, and a voltage is for example applied to the bit line  806  by the drive element  816 . The current I READ  at the input of the comparator  812  is thus proportional to programmed resistance of the storage element, and by comparing this current to a reference current I REF , the programmed state of the resistive element of the cell can be detected by the comparator  812 , and stored in the latch  814 . The reference current I REF  is for example generated by applying a voltage to an element of resistance equal to a mid-value between the resistances R min  and R max  of the resistive elements, which could be implemented by coupling a pair of the storage elements in parallel with each other, but in opposite directions. 
     In addition to the write and read operations described above, data may also be transferred between LR and HR cells, as will now be described with reference to  FIGS. 9A and 9B . 
       FIG. 9A  illustrates steps in a save operation. 
     In an initial step  902 , the “SAVE” signal is asserted, or an automatic save operation is triggered. For example, the memory array may be configured to periodically save the data stored in one or more LR cells to one or more HR cells, in order to back up the data. Alternatively, the control block  820  may automatically trigger the save operation based on a determined average retention duration of the low retention elements. For example, the control block  820  comprises a counter that estimates the average retention duration of the low retention duration elements in each sector of the memory, for example each column, line or bank of memory elements. This information is then used to determined how frequently the save operation should be conducted, while allowing a suitable margin such that data is not lost. 
     In a subsequent step  904 , data is read from the LR cell  102  to the latch  814 , this operation being similar to the read operation described above. 
     In a subsequent step  906 , the data read to the latch  814  is written to an HR cell, this operation being similar to a write operation as described above. 
     The steps  904  and  906  may be repeated for other LR cells in the column of memory cells. 
       FIG. 9B  illustrates steps in an operation for reverting to a low power mode. 
     In an initial step  912 , the low power signal LOW P is asserted. 
     In a subsequent step  914 , data is read from the HR cell  104  to the latch  814 , this operation being similar to the read operation described above. 
     In a subsequent step  916 , the data is written from the latch  814  to the LR cell  102 , this operation being similar to a write operation as described above. 
     The steps  914  and  916  may be repeated for other HR cells in the column of memory cells. 
       FIG. 10  schematically illustrates the memory device  100  of  FIG. 1A  in more detail according to a further example embodiment very similar to that of  FIG. 8 , and like features have been labelled with like reference numerals and will not be described again in detail. 
     In the device of  FIG. 10 , two separate banks of memory cells are provided, each coupled to read-write circuitry  1010 , which is common to both banks of memory cells. 
     The memory cell  102  forms part of a bank B 1 , along with another LR cell  102 ′, which comprises a resistive element  1002 A and a selection transistor  1004 A coupled in series between the bit lines  806 ,  808 . Of course, the bank B 1  may comprise many more memory cells, all of which are for example LR cells. 
     The memory  104  forms part of another bank B 2 , along with another HR cell  104 ′. Both of the memory cells  104  and  104 ′ are coupled between bit lines  1006  and  1008 , rather than between the bit lines  806 ,  808 . The cell  104 ′ comprises a resistive element  1002 B and a selection transistor  1004 B coupled in series between the bit lines  1006 ,  1008 . 
     The read-write circuitry  1010  is similar to the circuitry  810 , except that it additionally comprises a multiplexers  1022 , and demultiplexers  1024  and  1026 . Multiplexer  1022  has two inputs respectively coupled to the bit lines  808  and  1008 , and an output providing the input to the comparator  812 . Demultiplexer  1024  has an input coupled to the output of the drive element  816 , and a two outputs coupled to the bit lines  806  and  1006  respectively. Demultiplexer  1026  has an input coupled to the output of the drive element  818 , and two outputs coupled to the bit lines  808  and  1008  respectively. The multiplexer  1022  is controlled by a selection signal S, and the demultiplexers  1024 ,  1026  for example by the inverse of this selection signal. 
     Operation of the device of  FIG. 10  during a write or read operation is very similar to that of the device of FIG.  8 , except that that the demultiplexers  1024  and  1026 , as well as the selection signals C 1 , C 1 ′ etc., are controlled in order to select a memory cell to be written or read. 
     Operation of the device of  FIG. 10  during a transfer operation is also very similar to that of the device of  FIG. 8 , except that when data is to be read, the multiplexer  1022  is controlled to select the appropriate bit line  808  or  1008 . Furthermore, data transfers can be performed more quickly because data can be read from one of the banks of memory cells at the same time as data is written to the other. 
     An advantage of the embodiments described herein is that, by providing programmable resistive elements of different data retention durations in separate memory cells of a synchronous memory device, the most energy efficient resistive element for a desired retention duration can be selected for a given data value, thereby economizing energy. For example, the resistive element with the lowest retention time can be used most frequently, and the resistive element with a long retention time could be used sporadically to provide long term data backup. 
     Having thus described at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. 
     For example, it will be apparent to those skilled in the art that the supply voltage V DD  in the various embodiments could be at any level, for example between 1 and 3 V, and rather that being at 0 V, the ground voltage can also be considered as a supply voltage that could be at any level, such as a negative level. 
     Furthermore, it will be apparent to those skilled in the art that, in any of the embodiments described herein, all of the NMOS transistors could be replaced by PMOS transistors and/or all of the PMOS transistors could be replaced by NMOS transistors. It will be apparent to those skilled in the art how any of the circuits could be implemented using only PMOS or only NMOS transistors. Furthermore, while transistors based on MOS technology are described throughout, in alternative embodiments other transistor technologies could be used, such as bipolar technology. 
     Furthermore, it will be apparent to those skilled in the art that the various features described in relation to the various embodiments could be combined, in alternative embodiments, in any combination.