Abstract:
Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to detecting and correcting errors in arrays after successful ABIST testing, where diagnostic testing is performed upon the array after ABIST testing, and the detected error or fault is isolated. 
         [0003]    2. Background Art 
         [0004]    The problem of past s390-processors was, that whenever a PU (processor unit) has an array with errors found by abist-tests, there was no possibility to disable part or all of this array. In this cases the PU couldn&#39;t be used at all since the abist-tests didn&#39;t pass IML. 
         [0005]    Especially the sensitive PCAMs used in Bluefire did often fail and decrease the yield heavily, and therefore we looked for a solution to get also PUs with defect array sets running. 
         [0006]    Because the yield-problem will most likely get bigger with new technologies and having more cores on a chip, it might be useful to have also partial good chips with failing arrays for spare PUs or at least for chip and system bring-up. 
         [0007]    Actually array fails occurring during normal operation mode (after abist-tests did run successfully) leads in deletion of the failing array set. This ensures, that the PU can be used also after an upcoming fail, but with less array sets (results in slightly decreased performance, but w/o showing functional problems). The problem is, that PUs with defective arrays found on the tester cannot be used in a system. 
         [0008]    Because of the given performance delta it also implies that such a processor can not be shipped the same as a processor without any array sets disabled for the performance delta between the two is readily measurable. 
       SUMMARY OF THE INVENTION 
       [0009]    The DANU-Processor has a TLB2 which is a 4 set, associative, hierarchical lookaside buffer (2 levels of hierarchy). Each of the sets has a RAM part (random access memory) and a CAM part (content access memory). Especially the CAM-part is very sensitive to fails with the new technology, and therefore a solution was necessary which enables a processor to disable one or more defect sets of the TLB2. This makes it possible (especially during the bring-up process) to use also the processors with defective TLB2 arrays which increases the yield during bring-up dramatically. Since now processors with one or more failing TLB2 array sets must be configured out and cannot be used. 
         [0010]    The functional logic could delete sets already in the Freeway-system, but this works only for fails occurring after the IML sequence, because during IML the ABIST do check the arrays, and fails being present already at that point didn&#39;t pass the ABIST-test (MISR signature fails) and therefore this processor having a defect TLB2-set couldn&#39;t be used, even though the processor would work properly with one or even all TLB2-sets being defect. 
         [0011]    The solution is to use e-fuses (one fuse for each of the sets) and to have separate misr latch busses for each set of the array. This new array misr latch structure enable the abist engine to handle the disabled sets from the array. The abist engine can analyze each set unique from each other. 
         [0012]    If a set is failing in the fab, the fuse for this set will be blown and the chip can used. 
         [0013]    PU&#39;s having defective array sets can be used in the system, either for bring-up or shipping. The yield is dramatically increased with the new array delete mechanisms. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0015]      FIG. 1  is a simplified schematic diagram showing a processor unit with three arrays, e.g., translation look aside buffers, one of which is shown as defective. The processor includes associated ABIST test units. The output is “anded.” 
           [0016]      FIG. 2  is a simplified schematic diagram showing a processor unit with three arrays, e.g., translation look aside buffers, one of which is shown as defective. The processor includes associated ABIST test units, and fused inputs to take defective arrays out of service. The output is “anded.” 
           [0017]      FIG. 3  illustrates several associated arrays with an E-fuse isolating a defective array. An E-fuse indicates a bad PCAM set that will disable the clocking and force a constant value to the MISR latches for the master and slave PCAMS. 
           [0018]      FIG. 4  illustrates an overall processor with an input latch bank, dynamic PCAM array, deselect quad control line, and array and data logic. 
       
    
    
     DETAILED DESCRIPTION 
       [0019]    The steps of the method are as follows: 
         [0020]    The first step is checking for failing array sets during fabrication, that is ABIST testing. As part of or after testing, appropriate fuses are blown to deactivate failing array set. For example, during bring-up only performance degradation will be noticed but no functional degradation and no ABIST-fail will occur. 
         [0021]    As to ABIST-fails found during bring-up:
       a) Analyze reported ABIST-fail;   b) Blow appropriate e-fuse to deactivate failing array set;   c) Rerun ABIST with standard setup,   d) The fail will not occur, because the MISR signature will be good due to the masking by the described built-in hardware, i.e., blowing the fuse.       
 
         [0026]    In system run:
       a) The system starts and runs the ABIST tests   b) The activated fuses will force “good” MISR-signatures in order to pass the ABIST test during IML   c) SE reads out the fuse values and sets the delete-latches (via scan-chain) for each fused array set. This is necessary to tell the translator logic not to use the defective array set.   d) The system runs with less performance, but functionally correct       
 
         [0031]    For future designs this logic delete latches can be set directly by the fuses instead of doing this SE controlled. 
         [0032]    This is illustrated in the Figures, Starting with  FIG. 1 ,  FIG. 1  is a simplified schematic diagram showing a processor unit  101  with three arrays, e.g., translation look aside buffers  103 , one of which is shown as defective  105 . The processor includes associated ABIST test units  107 . The output is “anded”  109 . 
         [0033]      FIG. 2  is tracks  FIG. 1 , but in addition it shows how the e-fuse values are read-out by the SE (Service Element) in order to set the “ignore Data latches” with the appropriate values. 
         [0034]      FIG. 3  illustrates several associated arrays with an E-fuse isolating a defective array. An E-fuse  111  indicates a bad PCAM set that will disable the clocking and force a constant value to the MISR latches for the master and slave PCAMS. It is to be noted that read data from a deselected set or quad must not get into the MISR or array data out latches for both master and slave PCAMs. 
         [0035]      FIG. 4  illustrates the implementation of the deselection inside a PCAM-set.  201  is the input latch bank of a PCAM,  205  the dynamic PCAM array,  209  the deselect quad control line switch and  213  the MISR logic. 
       BHT 
       [0036]    The branch prediction takes the deletion logic a step further where as the performance impact is around 1/1000 th  of 1% of PU performance. The branch prediction logic consist of a BTB, branch target buffer, which has 8 k entries. The array is 4-way set associative and is 2 k deep. Each entry in this table is 64 bits. This places the array at over ½ million array bits which were priority required to be perfectly designed in the manufacturing process. 
         [0037]    As per the TLB2, the BTB contains a mechanism at run time to detect an array failure, which could have developed over time, and to delete the appropriate set such that the processor unit could continue running without encountering further failure encounters from the given set of the BTB array. Such a deletion process required entries to 1) no longer be written to this set of the array and 2) ignore any future errors detected from this set of the given array as data from this set is no longer in use. 
         [0038]    When the ABIST engine checks for the validity of an array, it is checking cell by cell for functional compliance. It is therefore possible to not only detect which set of the given array is bad, but also which precise entry of the array is bad for the exact bad cell is known. Fuses are not only contained for the given set but also the given index for the entry of the bad cell. For a given bad array cell, this now allows disable actions to take place on 1/8192 nd  of the array entries over ¼ th  of the array entries. 
         [0039]    When a write is to take place to the index value which contains a bad cell in one of the sets, logic which determines the set to write a given entry into makes it appear that the set with the bad cell is disabled. This prevents the given set with the bad cell from being written to. Upon moving array from the index with a bad entry, in respect to a write, the given set no longer looks as though it is deleted. 
         [0040]    The invention may be implemented, for example, by having the system for testing the array and enabling the abist engine to handle disabled sets from the array. The abist engine can analyze each set unique from each other so that if a set is failing under test, the fuse for this set will be blown, and the processing unit used PU&#39;s having defective array sets can be used in the system, and executing the method as a software application, in a dedicated processor or set of processors, or in a dedicated processor or dedicated processors with dedicated code. The code executes a sequence of machine-readable instructions, which can also be referred to as code. These instructions may reside in various types of signal-bearing media. In this respect, one aspect of the present invention concerns a program product, comprising a signal-bearing medium or signal-bearing media tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform a method for isolating defective cells in a processing unit. 
         [0041]    This signal-bearing medium may comprise, for example, memory in a server. The memory in the server may be non-volatile storage, a data disc, or even memory on a vendor server for downloading to a processor for installation. Alternatively, the instructions may be embodied in a signal-bearing medium such as the optical data storage disc. Alternatively, the instructions may be stored on any of a variety of machine-readable data storage mediums or media, which may include, for example, a “hard drive”, a RAID array, a RAMAC, a magnetic data storage diskette (such as a floppy disk), magnetic tape, digital optical tape, RAM, ROM, EPROM, EEPROM, flash memory, magneto-optical storage, paper punch cards, or any other suitable signal-bearing media including transmission media such as digital and/or analog communications links, which may be electrical, optical, and/or wireless. As an example, the machine-readable instructions may comprise software object code, compiled from a language such as “C++”, Java, Pascal, ADA, assembler, and the like. 
         [0042]    Additionally, the program code may, for example, be compressed, encrypted, or both, and may include executable code, script code and wizards for installation, as in Zip code and cab code. As used herein the term machine-readable instructions or code residing in or on signal-bearing media include all of the above means of delivery. 
         [0043]    While the foregoing disclosure shows a number of illustrative embodiments of the invention, it will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the scope of the invention as defined by the appended claims. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.