Abstract:
A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Technical Field  
           [0002]    The present invention relates generally to electronic packaging, and more particularly, to an organic semiconductor chip carrier and method of forming the same.  
           [0003]    2. Related Art  
           [0004]    As the demand grows in the industry for miniaturized high performance semiconductor packages, the need to manufacture a reliable device having high density connections becomes increasingly important. In other words, producing a device having the largest number of chip connections over the smallest possible area is one of the primary objectives. It is also important to produce a structure capable of providing adequate “wireout” capabilities to take advantage of the high density connections.  
           [0005]    [0005]FIG. 1 shows a cross-sectional view of a related art semiconductor chip carrier  10 . The carrier  10  includes a ground plane  12 , a first dielectric layer  14  on each side of the ground plane  12 , a signal layer  16  over each first dielectric layer  14 , a second dielectric layer  18  over each signal layer  16 , a power core  20  over each second dielectric layer  18 , and a third dielectric layer  22  over each power core  20 . The carrier  10  has a plurality of copper plated through holes  24 , wherein the copper plating forms a “dogbone” connection pad  28  on the surface of the carrier  10 . A redistribution layer  30  covers the surface of the carrier  10 . The redistribution layer  30  contains contact areas  34 , which facilitate electrical connection of semiconductor chips (not shown), through interconnections (also not shown), to the dogbone connection pads  28  of the plated through holes  24 .  
           [0006]    [0006]FIG. 2 shows a top view of the related art semiconductor chip carrier  10 . The dogbone connection pads  28  consume a large portion of the surface area on the carrier  10 . This is because the interconnection contact area  34 , the area upon which the interconnection is mounted, is offset from the plated through hole  24 . As a result, the density of plated through holes  24  and interconnections for each carrier  10  is limited.  
           [0007]    Additionally, due to differences in the coefficient of thermal expansion between the chip carrier, the chips and the interconnections therebetween, internal stresses develop within the semiconductor package during thermal cycling, which may eventually lead to device failure.  
           [0008]    As a result, there exists a need in the industry for a more reliable, compact semiconductor device.  
         SUMMARY OF THE INVENTION  
         [0009]    The present invention provides a more reliable semiconductor chip carrier, having high density plated through hole spacing and chip connections, and a method of forming the same. The first general aspect of the present invention provides an interconnect structure comprising: a substrate; a plated through hole positioned within the substrate; a redistribution layer on a first and a second surface of the substrate; and a via within the redistribution layer, selectively positioned over and electrically connecting the plated through hole. This aspect allows for a semiconductor chip carrier having an increased plated through hole and chip connection density. This aspect provides vias, containing chip connection pads therein, positioned directly over the plated through holes, which eliminate the conventional dogbone construction. This aspect also provides additional wireout capabilities to take advantage of the increased plated through hole and chip connection density, namely, an additional pair of signal planes and an additional pair of power planes. This aspect also provides a redistribution layer which is made fatigue resistant due to the material choice, as well as locating the second pair of power planes directly underneath the redistribution layer. Due to the roughened surface of the second pair of power planes, the adhesion strength of the redistribution layer to the underlying substrate is increased. In addition, the second pair of power planes act as a redundant layer, preventing cracks originating within the redistribution layer from propagating through the carrier. Furthermore, this aspect provides for direct via connections, which eliminate the need for plated through holes.  
           [0010]    A second general aspect of the present invention provides a method of forming a semiconductor chip carrier, comprising the steps of: providing a substrate, having a plated through hole therein; depositing a redistribution layer on a first and a second surface of the substrate; and forming a via within the redistribution layer, selectively positioned over and electrically contacting the plated through hole. This aspect provides a method of forming a semiconductor chip carrier having similar advantages as those associated with the first aspect.  
           [0011]    A third general aspect of the present invention provides a semiconductor chip carrier comprising: a substrate having a plated through hole therein; and a fatigue resistant redistribution layer on a first and second surface of the substrate. This aspect provides similar advantages as those associated with the first aspect.  
           [0012]    The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    Specific embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:  
         [0014]    [0014]FIG. 1 depicts a cross-sectional view of a related art semiconductor chip carrier;  
         [0015]    [0015]FIG. 2 depicts a top view of the related art semiconductor chip carrier;  
         [0016]    [0016]FIG. 3 depicts a cross-sectional view of a semiconductor chip carrier in accordance with a first embodiment of the present invention;  
         [0017]    [0017]FIG. 4 depicts a cross-sectional view of the semiconductor chip carrier having through holes therein in accordance with a first embodiment of the present invention;  
         [0018]    [0018]FIG. 5 depicts a cross-sectional view of the semiconductor chip carrier having plated through holes therein in accordance with a first embodiment of the present invention;  
         [0019]    [0019]FIG. 6 depicts a cross-sectional view of the semiconductor chip carrier having a combined power core thereon in accordance with a first embodiment of the present invention;  
         [0020]    [0020]FIG. 7 depicts a cross-sectional view of the semiconductor chip carrier having a redistribution layer thereon in accordance with a first embodiment of the present invention;  
         [0021]    [0021]FIG. 8A depicts a cross-sectional view of the semiconductor chip carrier having connection pads thereon in accordance with a first embodiment of the present invention;  
         [0022]    [0022]FIG. 8B depicts an enlarged cross-sectional view of a plated through hole having a connection pad thereon in accordance with a first embodiment of the present invention;  
         [0023]    [0023]FIG. 8C depicts an enlarged cross-sectional view of a plated through hole having a connection pad thereon in accordance with an alternate embodiment of the present invention;  
         [0024]    [0024]FIG. 9 depicts a top view of the semiconductor chip carrier in accordance with a first embodiment of the present invention; and  
         [0025]    [0025]FIG. 10 depicts a cross-sectional view of the semiconductor chip carrier having a buried plated through hole therein in accordance with a second embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]    Although certain embodiments of the present invention will be shown and described in detail, it should be understood that various changes and modifications may be made without departing from the scope of the appended claims. The scope of the present invention will in no way be limited to the number of constituting components, the materials thereof, the shapes thereof, the relative arrangement thereof, etc., and are disclosed simply as an example of the embodiment. Although the drawings are intended to illustrate the present invention, the drawings are not necessarily drawn to scale.  
         [0027]    Referring to the drawings, FIG. 3 shows a substrate  100 , including a ground plane  112 , preferably comprising copper-Invar-copper (CIC). A first dielectric layer  114  is laminated to each side of the ground plane  112 , using conventional lamination techniques. A pair of first controlled impedance signal planes  116  are formed, one over each of the first dielectric layers  114 , using a conventional method known and used in the industry. The first signal planes  116  are preferably copper. A second dielectric layer  118  is formed over each of the first signal planes  116 , using conventional lamination techniques. A pair of first power planes  120  are formed, one over each of the second dielectric layers  118 , using conventional techniques. The first power planes  120  are preferably copper. A third dielectric layer  122  is laminated over each of the power planes  120 . A pair of second controlled impedance signal planes  124  are formed, one over each of the third dielectric layers  122 , using techniques similar to those used to form the first signal planes  116 . The second signal planes  124  are preferably copper. A fourth dielectric layer  126  is laminated over each of the second signal planes  124 , using conventional lamination techniques. In this example, the first, second, third and fourth dielectric layers  114 ,  118 ,  122 ,  126  comprise Rogers&#39; 2300™ (Roger&#39;s Inc.). In particular, Rogers&#39; 2300™ is a dielectric comprising a PTFE (polytetrafluroethylene) material filled with silicon particles. In the alternative, the first, second, third and fourth dielectric layers  114 ,  118 ,  122 ,  126  may be any other similar electronics laminate material, such as, epoxy resins, polyimide, polyphenylene ethers, etc.  
         [0028]    As shown in FIG. 4, a pair of second power planes  128  are laminated, one over each of the fourth dielectric layers  126  using conventional techniques. The surfaces of the second power planes  128  are etched to a thickness of approximately 2-9 microns, preferably using a fluid head etch process, to maintain a copper thickness suitable for laser drilling and electroplating an additional copper layer. It should be noted that the thickness of the second power planes  128 , illustrated in the figures, is disproportionately large for the purpose of illustration only.  
         [0029]    A plurality of through holes  130  are formed within the substrate  100 , preferably using a laser drill process commonly used in the industry (FIG. 4). The through holes  130  are then cleaned to eliminate any debris which could prevent proper electrical connection. The surface of the second power planes  128  and the through holes  130  are then electroless plated with a conductive material, preferably copper. The through holes  130 , and the second power planes  128  are then acid copper electroplated, forming plated through holes (PTH&#39;s)  132 , as shown in FIG. 5. The thickness of the copper plating within the PTH&#39;s  132  is approximately 5-20 microns, while the composite copper thickness on the power planes  128  (composite thickness of the fluid head etched copper foil and subsequent acid copper electroplate) is approximately 7-29 microns.  
         [0030]    As shown in FIG. 6, the power cores  128  are circuitized to electrically isolate the power cores  128  from the PTH pads  134 ,  136 . The resultant surfaces are called the top surface metallurgy (TSM)  133  and the bottom surface metallurgy (BSM)  135 . The TSM  133  and BSM  135  copper surfaces are preferably chlorited copper. Chlorited copper is copper that has been treated with chlorite to produce a roughened surface, thereby enhancing the adhesion strength of the redistribution layer (discussed infra). A redistribution layer  138  is then laminated over the TSM and BSM surfaces  133 ,  135  of the substrate  100 , covering the power cores  128 , and filling the PTH&#39;s  132 , as shown in FIG. 7.  
         [0031]    The redistribution layer  138  is preferably a dielectric material, such as Dynavia 2000™ (Shipley Ronal), polyimide, PSR-4000 (Taiyo Ink Co. Ltd.), Vialux™ (DuPont), and other similar materials made by Arlon, Asahi Chemical, and other similar companies. The use of a flexible redistribution layer  138  tends to increase the overall flexibility of the substrate  100 , thereby decreasing the internal stresses associated with thermal cycling.  
         [0032]    As shown in FIG. 8A, a plurality of blind vias or microvias  140  are laser drilled into the redistribution layer  138 , directly over the PTH&#39;s  132 . FIG. 8B shows an enlarged view of the placement of a microvia  140  with respect to the PTH  132 , and particularly, the PTH pads  134 . As illustrated, the microvias  140  may be placed directly over the PTH&#39;s  132 . In the alternative, the microvias  140  may be drilled slightly off-set from the PTH&#39;s  132 , as illustrated in FIG. 8C. In this case, the microvias  140  may extend partially into the through holes  130  of the PTH&#39;s  130 , but typically should not extend beyond the PTH pads  134 .  
         [0033]    The microvias  140  are then cleaned of excess debris using known cleaning techniques. The microvias  140  are electroless plated with a conductive material, preferably copper, then acid copper plated to form chip connection pads  142 . Typically, Controlled Collapse Chip Connector (C4) pads are formed through the redistribution layer  138  as part of and connected to the microvias  140  on the first surface  149  of the substrate  100 . The Ball Grid Array (BGA) pads  148  (FIG. 8A) are formed on the second surface  150  of the substrate  100 .  
         [0034]    [0034]FIG. 9 shows a top view of the substrate  100 , having PTH&#39;s  132  therein. The vias  140  of the chip connection pads  142  may be formed directly over and in line with the PTH&#39;s  132 , thereby allowing the semiconductor chips (not shown) to be mounted; directly over and physically contacting the PTH&#39;s  132 . This construction eliminates the conventional dogbone construction, shown in related art FIG. 2. As a result, the density of the chip connection pads  142 , as well as PTH&#39;s  132 , may be increased. It should be understood that the configuration, quantity, size and arrangement of the PTH&#39;s  132  are used only as an example, and is in no way intended to limit the scope of the present invention.  
         [0035]    It should be noted that the pair of second signal planes  124  and the pair of second power planes  128  provide additional “wireout” capabilities, to compensate for the increased density of PTH&#39;s  132  and chip connection pads  142 . Heretofore, a single layer of “tri-plate” circuitry has been used. Tri-plate circuitry refers to a controlled impedance circuit consisting of a single ground, a pair of signal planes, and a pair of power planes, as illustrated in related art FIG. 1. The present invention, however, provides an additional pair of signal layers  124  and an additional pair of power planes  128 . This increases the controlled impedance wireout capabilities of the substrate  100 , thereby taking full advantage of the increased PTH  132  and chip connection pad  142  density. Layer thicknesses may be separately adjusted to obtain desirable electrical values.  
         [0036]    It should be noted that the present invention eliminates the additional dielectric layer  22  conventionally used, which separated the redistribution layer  30  from the underlying power plane  16  (shown in related art FIG. 1). By eliminating this extra dielectric layer, the overall size of the carrier is reduced. In addition, elimination of the extra dielectric layer, in the present invention, allows for the application of the redistribution layer  138  directly onto the second pair of power planes  128 , as shown in FIGS. 7, 8A and  10 . This provides several benefits. For example, the roughened surfaces of the second power planes  128  enhance the adhesion strength of the redistribution layer  138  to the substrate  100 . Placing the second power planes  128  directly underneath the redistribution layer  138  also controls strains imposed on the redistribution layer  138 , thereby reducing the potential for fatigue cracks, and other stress related problems, during thermal cycling. In addition, the second power planes  128  moderate the effective coefficient of thermal expansion within the redistribution layer  138 , thereby further reducing the potential for fatigue cracks within the redistribution layer  138 . Further, the second power planes  128  are redundant layers. Fatigue cracks that originate within the redistribution layer  138  are not likely to propagate through the second power planes  128 , thereby reducing the likelihood of device failure. The extent and amount of circuitry patterned as part of the second pair of power planes  128  and the power core  134  may be adjusted to provide a balance to copper pads  148 , so warpage of the device is minimized.  
         [0037]    In a second embodiment of the present invention, FIG. 10 shows a buried PTH  146  formed within the substrate  100 . The buried PTH  146  is formed in a manner similar to the PTH&#39;s  132  described above. To form the buried PTH  146 , however, the PTH formation process described above is performed before the outer layers of the substrate  100  are deposited. For example, after the lamination of the first power planes  120 , the substrate  100  is laser drilled to form through hole  145 . The through hole  145  and power planes  120  are then cleaned, electroless plated, preferably with copper, then acid copper electroplated, and circuitized to form the buried PTH  146 . The third dielectric layer  122  is laminated over the first power planes  120 , which also fills and covers the ends of the buried PTH  146 . The process described above in association with the first embodiment may then be continued to form the remaining PTH&#39;s  132 , if so desired. The buried PTH  146  provides the substrate  100  with enhanced internal electrical connection.  
         [0038]    It should be noted that the buried PTH  146  described in the second embodiment may be used in conjunction with the PTH&#39;s  132  described in the first embodiment. In the alternative, the buried PTH  146  may have other applications, separate and distinct from the first embodiment. It should also be noted that formation of the buried PTH  146  described in the second embodiment is only meant to be an example, and is in no way intended to limit the scope of the present invention. For instance, more than one buried PTH  146  may be formed within a carrier. In addition, the buried PTH  146  is not limited to formation between the first power planes  120 .  
         [0039]    While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.