Abstract:
The invention relates to a two state phase modulator with minimum amplitude modulation. The modulator assumes two phase states differing by Θ where Θ is a sub-multiple of 180° which permits a phase variation of 180° for phase coded transmissions when the frequency of the phase modulated carrier wave is multiplied by the reciprocal of the sub-multiple. Three equal components are derived in the phase modulator: an in-phase, an out of phase, and a quadrature phase component. The out of phase component is delayed in relation to the in-phase component by Θ/2, while the quadrature phase component is delayed Θ/4. The in-phase and out of phase components are then reduced by a factor (2 sin Θ/2) selected such that when added to the quadrature component, the resultants have a magnitude equal to that of the quadrature component and differ in phase from the quadrature comonent by ±Θ/2. The modulator output is formed of the resultants supplied in alternation with the quadrature component at zero phase being supplied during the transitions. Amplitude variation during the phase modulation process is reduced to a fraction of a decibel.

Description:
The United States Government has rights in this invention pursuant to Contract No. N00024-88-C-5407, awarded by the United States Navy. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to phase modulators which are operated between two phase states, and more particularly to a phase modulator suitable for use in a frequency multiplication chain to produce an in-phase state (i.e. at 0° reference phase) and an out of phase state (i.e. 180° from reference phase) upon a carrier wave, or equivalently ±90° from reference phase. 
     2. Prior Art 
     Phase modulators have been used for some time to provide phase coding in a transmitted wave. In radar systems, the phase modulation will assume an in-phase state, corresponding to a &#34;1&#34; and an out of phase state corresponding to a &#34;0&#34;. (The two phase states may also be regarded as plus or minus 90° from a reference phase state.) The duration of one bit of the phase coding is typically many cycles, 200 nanoseconds in a typical system, and it is desirable that the change in phase state take place in a relatively short duration, typically 20 nanoseconds. 
     In a typical phase modulation system, there is frequently a very significant variation in amplitude during the transition from one phase state to the other. In a known bi-phase modulator circuit, the amplitude of the carrier is reduced 23 dB in the transition from one phase state to the other phase state, and then reduced again by 23 dB in the transition from the other phase state back to the original phase state. 
     This very substantial amplitude modulation produces a number of undesirable side effects in the utilization circuitry, and for that reason efforts have been directed to reducing the amplitude modulation to a much lower level. One such approach has been to allow the phase modulation to produce a small fraction of the ±90° phase modulation on a low frequency carrier, after which the carrier is multiplied by the reciprocal of the fraction to achieve ±90° phase modulation in the final high frequency carrier. In a known example, reducing the phase modulation to ±45° and multiplying the frequency by a factor of two reduces the amplitude variation to approximately 1.5 dB. Reducing the phase modulation angle to approximately ±22.5° reduces the amplitude modulation to approximately 0.6 dB and requires that the frequency be multiplied by a factor of four. 
     The approach of reducing the phase modulation angle and multiplying the frequency to get ±90° phase modulation at the final carrier frequency with rectangular phasor combinations is accordingly useful, however these combinations can be modified using some of the same components to reduce the residual ripple even more. 
     SUMMARY OF THE INVENTION 
     Accordingly it is an object of the present invention to provide an improved phase modulator for switching between two phase states. 
     It is another object of the present invention to provide a phase modulator for switching between two phase states in which amplitude modulation is greatly reduced. 
     It is still another object of the present invention to provide a phase modulator of an economic design for switching between two phase states with minimum amplitude modulation. 
     These and other objects of the invention are achieved in a novel phase modulator which may be switched between two phase states with an angular separation of Θ. The phase modulator comprises means to form three carrier frequency waves of equal magnitude, respectively wave I o  which is at reference phase; wave Q o  which is in phase quadrature (-90°); and wave J o  which is out of phase (-180°). These three waves are formed by a first quadrature hybrid (HY 1 ) connected for power division, the in-phase output of which produces the wave I o , a second quadrature hybrid (HY 2 ), supplied from the quadrature output of the first hybrid (HY 1 ), and which is also connected for power division, and which derives the waves J o  and Q o . The in-phase wave from hybrid HY 1  is supplied to a 3 dB attenuator (ATT 1 ) to equalize the magnitude of I o  to J o  and Q o , making all three equal. 
     The wave J o  is next delayed in relation to the wave I o  by one half the phase modulation angle (Θ), and the two waves, now denominated I 2  and J 2  are coupled to the first and second terminals of a single pole double throw switch, which selects one for transmission to a second attenuator ATT 2 . 
     The second attenuator ATT 2  is provided to bring the waves I 2  and J 2  into a prescribed magnitude relationship to Q o  prior to addition in a summation hybrid HY 3 . This entails reducing the magnitudes of the waves I 2  and J 2  by a factor of at least 2(sin Θ/2), the attenuated waves being denominated I 3  and J 3 . 
     The wave Q o  from hybrid HY 2  is now coupled to a delay line designed to bring the resulting phase shifted wave Q 1  into the prescribed phase with the waves I 3  and J 3 . Assuming a first order correction, the summation hybrid forms two congruent isosceles triangles from the component phasors whose central angle is Θ/2. In one triangle, the equal sides are phasors Q 1  and Q 2  with Q 2  being formed by addition of phasors Q 1  and J 3 , and in the other triangle the equal sides are phasors Q 1  and Q 3  with Q 3  being formed by the addition of phasors Q 1  and I 3 . In the case where Θ is 60° (and eventual multiplication by three is contemplated), the central angle of the isosceles triangle is 30° and the angle between Q 1  and J 3  and between Q 1  and I 3  in the summation diagram is 75°. 
     The effect of the foregoing geometrical relationship is that as the phase is being changed from one state to the other, the first phasor (e.g. Q 2 ) which represents the in-phase output wave has a magnitude equal to Q 1 , and after the phase has changed, the second phasor (e.g. Q 3 ) which represents the phase shifted output wave also has a magnitude equal to phasor Q 1 . Since the wave represented by the phasor Q 1  is continuously supplied, the output wave also has a magnitude equal to the phasor Q 1  at the mid point of the transition between phase states. The effect is to reduce the amplitude ripple in the output wave to two shallow valleys, less than a fraction of a dB (e.g. 0.301 dB) as the modulator is switched between ±30°. If Θ is selected to be 45°, for eventual multiplication by four, the ripple is reduced by almost one-half (e.g. 0.169 dB). 
     The summation hybrid may either be a quadrature hybrid or an in-phase hybrid provided that the required symmetry between the phasors Q 1 , I 3  and J 3  for addition is preserved. The in-phase hybrid may be preferred because of a reduction in the delay required of the phasor Q 1 . 
     A somewhat smaller ripple may be achieved if the continuously supplied wave represented by the phasor (Q 1 ) is made larger than the phasor resultants Q 2  and Q 3  by the error δ which exists at the valleys. This equal ripple adjustment, if an increase in the phasor Q 1  relative to the resultants Q 2  and Q 3  can be tolerated, further reduces the ripple in the case where Θ =60° to approximately 0.2 dB and in the case where Θ=45° to approximately 0.1 dB. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The inventive and distinctive features of the invention are set forth in the claims of the present application. The invention itself, however, together with further objects and advantages thereof may best be understood by reference to the following description and accompanying drawings, in which: 
     FIG. 1 is a simplified block diagram of a phase modulated CW radar system containing a novel two state phase modulator which exhibits minimum amplitude modulation in transitioning between phase states; 
     FIG. 2 shows waveforms descriptive of the output of a phase modulated CW radar system; 
     FIGS. 3A through 3E are phasor diagrams of the voltages at specific nodes in the phase modulator of FIG. 1, corresponding to an adjustment in which amplitude modulation is minimized in transitioning between phase states by a first order correction; and 
     FIG. 4 is a phasor diagram illustrating an equal ripple amplitude adjustment of the FIG. 1 embodiment in which a further reduction in amplitude modulation between phase states is achieved. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a simplified block diagram of a phase modulated CW radar system containing a novel two state phase modulator in which amplitude variation is reduced between the two phase states and in the transition between states. 
     The PM CW radar system includes a source 1 of a 400 MHz CW carrier wave, and the two state phase modulator 2, which produces a phase modulation of 22.5° in one state and of -22.5° in another state or a phase difference of 45° between states. The radar system further includes a frequency multiplier (3) which multiplies the carrier frequency by a factor of four, which has the effect of multiplying the phase difference by a factor of four, to produce a &#34;1&#34; state at reference phase and a &#34;0&#34; state delayed 180° (i.e. at -180°) from reference phase. The multiplier supplies the digitally phase modulated carrier to the radar transmitter (4). A multiple of four was used for the frequency multiplier because it is easier to make using even numbered multipliers. However for purposes of illustration, a 30° angle will be used in the following description and it will require multiplication by a factor of three. 
     The phase coding is illustrated in FIG. 2. The phase is digitally encoded into &#34;bits&#34; of 250 nanosecond duration, and thus there are tens of waves (e.g. 100), the exact number depending upon the carrier frequency, (which are not individually illustrated) during each coding bit. The unmodulated CW waveform which is the uppermost waveform in FIG. 2 shows a single sinusoid for each bit rather than the higher number actually transmitted. The binary phase coding is illustrated immediately below. In the example, the binary sequence is 1110010 (reading from left to right). The phase coded waveform (going from left to right) includes three digital bits in which each RF cycle is of reference phase, two digital bits in which each RF cycle is 180° out of phase, a single bit in which each RF cycle is of reference phase, and a last single bit in which each RF cycle is 180° out of phase. 
     While a large number of cycles of the carrier are being transmitted during each phase encoded bit, it is desirable that the waves during both states be of equal amplitude and that the amplitude not change significantly in the relatively fast (˜20 nanosecond) transitions between states. The phase modulator illustrated in FIG. 1 preserves this constancy of amplitude to a high degree. 
     The novel two state phase modulator, illustrated in FIG. 1, which produces minimum phase modulation, comprises as its principal elements three reciprocal hybrids (HY 1 , HY 2  and HY 3 ), two attenuators (ATT 1 , ATT 2 ), two delay lines (DL 1 , DL 2 ), and a GaAs SPDT MMIC switch (SW 1 ). These elements are interconnected as shown in FIG. 1, and the waveforms at the critical nodes of the FIG. 1 diagram are illustrated in FIGS. 3A-3E. 
     As a first step in producing the two phase states, the hybrids HY 1  and HY 2 , which are quadrature hybrids and the attenuator ATT 1  of the phase modulator are arranged to derive three waves of equal magnitude respectively at reference phase (0°); out of phase (-180°) and in quadrature phase (-90°) from the unmodulated 400 MHz carrier supplied from the source 1. The three waves are represented in FIG. 3A by the phasors I o , J o  and Q o  respectively. 
     As shown in FIG. 1, the 400 MHz carrier wave from the source 1 is coupled to the phase modulator input terminal P 1 , which is connected to the B port of the quadrature hybrid HY 1 . The hybrid HY 1 , a reciprocal device, is connected for power division. The A port of the hybrid HY 1 , which is not shown, is terminated. The wave supplied to the B port is propagated with approximately equal (3 dB) power division to the output ports C and D. The wave propagated to the in-phase port C is at nominally at reference phase (0°), and the wave propagated to the quadrature port D is nominally at -90° from reference phase. There is, of course, some accumulated delay for both waves in passage through the hybrid. 
     Continuing, the wave at the quadrature port D of the hybrid HY 1  is then coupled to the A port of the quadrature hybrid HY 2 , also connected for power division. The B port of the hybrid HY 2 , which is not shown, is terminated. The wave supplied to the A port is propagated with an approximately equal (3 dB) power division to the output ports C and D. The wave propagated to the in-phase port D is nominally at reference phase (0°) in hybrid HY 2  while the wave propagated to the quadrature port C, and which experiences a second delay of -90° in hybrid HY 2 , is nominally out of phase (-180°) with respect to reference phase. 
     The waves appearing at the C and D ports of the hybrid HY 2 , are of equal magnitude but, having experienced a second power division both are of reduced amplitude in relation to the wave appearing at the C port of the hybrid HY 1 , which has experienced only one power division. The wave appearing at the C port of the hybrid HY 1  is coupled to the 3 dB attenuator ATT 1  to bring it into equality with the other two waves at the C and D ports of HY 2 . Thus three waves of equal magnitude, respectively nominally in-phase (0°), out of phase (-180°) and in quadrature phase (-90°) are created. 
     These three waves, now denominated &#34;I o  &#34;, &#34;J o  &#34;, &#34;Q o  &#34; have been indicated at the respective circuit nodes where they appear in FIG. 1. They are also shown, using conventional phasor notation, in FIG. 3A. In particular, the wave I o  at the output of attenuator ATT 1  is nominally at reference phase; the wave J o  at the port C of hybrid HY 2  is nominally out of phase (-180° from reference phase), while the wave Q o  at the D port of hybrid HY 2  is nominally at quadrature phase (-90° from reference phase), and all three phasors are of substantially equal magnitude. 
     As a second step in producing the two phase states, the delay line DL 1 , the GaAs MMIC switch SW 1 , and the 7 dB attenuator ATT 2  are arranged to derive two alternately available waves I 3  /J 3  from the waves I o  and J 0 . (As will be shown, the waves I 3  /J 3  are then combined in the hybrid HY 3  with a third wave derived from the wave Q o  to form the two phase states of the phase modulator 2.) 
     Assuming that the two phase states of the phase modulator will alternate between plus or minus 30°, the phasor J o  is delayed 30° with respect to the phasor I o  prior to application to the switch SW 1 . In addition to the stated 30° differential delay, both phasors are subject to an incidential 10° delay. The switch SW 1 , which is electrically equivalent to a single pole double throw (SPDT) switch, is of a GaAs MMIC design having two fixed terminals RF 1  and RF 2 , and a common terminal RF 3  selectively connected to the first or the second terminal in response to a control signal from a driver circuit. 
     The phasors coupled to the fixed terminals RF 1  and RF 2  of the switch are denominated I 2  and J 2 , respectively, the subscripts indicating the change in-phase that the two phasors have experienced. The phasors denominated I 2  and J 2  have been indicated at the respective circuit nodes where they appear in FIG. 1. They are also shown in FIG. 3B, using conventional phasor notation. 
     The solid state switch SW 1  is operated between the two conductive states by the application of a control potential. The drive circuit, which applies the control potential to terminal C 1  of switch 1, is timed such that conduction is being terminated between terminals RF 1  and RF 3  as conduction is being initiated between terminals RF 2  and RF 3 . 
     Thus the waveforms appearing at the common terminal RF 3 , alternate between I 2  and J 2 . Assuming a rise time for initiating conduction comparable to the fall time for terminating conduction, the phasors transition simultaneously with rise/fall times on the order of 20 nanoseconds. 
     After passage through the SPDT switch SW 1 , the two alternately available waveforms I 2  and J 2 , are coupled to the attenuator ATT 2  which produces an attenuation set exactly equal to 2(sin Θ/2) times the unit phasor (e.g. Q o ), for a first order correction of the amplitude modulation. The angle Θ is 30°, assuming that the output states of the phase modulator are ±30°. 
     The new phasors I 3  /J 3  in the case of ±30° phase modulation are thus reduced by a factor of 0.518. They appear at the output node of the attenuator ATT 2 , and are illustrated in FIG. 3D. 
     A third step in producing the two phase states of the modulator entails providing the required delay to the phasor Q o  for symmetry with the phasors I 3  /J 3  when they are summed in the hybrid HY 3  to form two equal amplitude output phasors of the two state phase modulator. 
     The quadrature phase component Q o  appearing at the D port of hybrid HY 2 , represented by a phasor of unit length in FIG. 3A, is subjected to a delay of approximately 25°, set in relation to the phasors, I 3  and J 3 . After passage through the delay line DL 2  the phasor, which is illustrated in FIG. 3C, is denominated &#34;Q 1  &#34;. Should the phasor Q 1  from FIG. 3C be superimposed on the axis of FIG. 3D, it would bisect the angle between J 3  and I 3 . 
     The output of the phase modulator is formed in the hybrid HY 3  from the phasors Q 1 , I 3  and J 3 . The hybrid HY 3  may be a quadrature hybrid like HY 1  and HY 2 , or an in-phase hybrid. In either event, the hybrid is connected for power summation. Using the quadrature hybrid notations, the phasor Q 1  derived from the delay line DL 2  is coupled to the C port, and the phasor I 3  /J 3  derived from the attenuator ATT 2  is coupled to the D port. The A port (not shown) is terminated, and the summed phasors defining the two phase output states appear at the B port which is coupled to the output terminal P 2  of the phase modulator. The connections for using an in-phase hybrid are interchangeable between the input ports, and the terminated port may not be accessible. 
     When the delay DL 2  has the proper value, the phasors for the in-phase hybrid will be related as shown in FIG. 3E. Neither the in-phase hybrid which is illustrated, nor the quadrature hybrid combine phasors Q 1 , I 3 , and J 3  efficiently. More power will be dissipated in the termination for the isolation port than is transmitted to the output. However, the additional insertion loss is of little concern. For Θ=30° as in FIG. 3E, the voltage ratio will be 0.876/0.707 and it will be exactly the same for either the in-phase or the quadrature hybrid. For the in-phase hybrid the Q 1  phasor must be delayed by DL 2  by Θ/4 degrees and in the quadrature hybrid Q 1  must be delayed by 90°+Θ/4 degrees. In either hybrid the output having the smaller amplitude is used to keep the phasors on the circumference of a circle. For the in-phase hybrid this connection can be confirmed by reversing the input terminals, while for the quadrature hybrid, the output from the opposite terminal can be used. 
     A graphical representative of the summation process where the in-phase hybrid is used is provided in the FIG. 3E phasor diagram. Here all vectors have been rotated an additional 10° to account for delay in the connecting wiring. The graph further illustrates the reduction in amplitude modulation as the modulator switches between the two phase output states. During the &#34;one bit&#34; when the switch SW 1  makes contact with terminal RF 1 , the phasor I 3  is supplied to the D port of hybrid HY 3 . Throughout the operation of the modulator, the Q 1  phasor is supplied to the C port. The two phasors are not in quadrature for exact summation in the hybrid, but approximate addition takes place to form a resultant Q 3 . The effect of adjusting the magnitude of I 3  to the 2 sin Θ/2 value done in attenuator ATT 2 , is to bring the phasors (Q 1 , I 3 , Q 3 ) into the relation of sides of an isosceles triangle, in which the central angle is 30° and the equal angles are each 75°. Under these conditions, Q 3  equals Q 1 . 
     Similarly during the &#34;zero&#34; bits when the SW 1  makes contact with terminal RF 2 , the phasor J 3  is supplied to the D port of hybrid HY 3 . Since the phasor J 3  is of equal length to the phasor I 3 , and also make an angle of 75° to the phasor Q 1 , a second isosceles triangle is created by the phasors (Q 1 , J 3 , Q 2 ). The resultant Q 2  is the phasor for the 0 state, and its phase differs from Q 3  by 60°. Under these conditions Q 2  equals Q 1 . 
     Thus when the phase modulator is in operation, the magnitude of the output of the phase modulator may be represented by phasors Q 1 , Q 2  and Q 3 . When the switch SW 1  is in the &#34;one&#34; state, the phasor Q 3  represents the output of the phase modulator at +30° from reference phase. When the switch is in the &#34;zero&#34; state, the phasor Q 2  represents the output of the phase modulator at -30° from reference phase. The sequence of phase resultants Q 1 , Q 2 , and Q 3  will always be Q 3 , Q 1 , to Q 2  or as the sequence is reversed Q 2 , Q 1  to Q 3 . In this sequence Q 3  corresponds to 30°, Q 2  corresponds to -30°, and Q 1  corresponds to 0° in a momentary position between Q 3  and Q 2  where I 3  and J 3  are in a transitory state. 
     When switching occurs between states, the quantity Q 1 , which is always being fed to the summation hybrid and which is of equal magnitude to Q 2  or Q 3 , permits only a very small ripple, representable by two valleys to either side of the unit vector Q 1 , during the transition between states. 
     Using the phasor relationships illustrated in FIG. 3E, the amplitude modulation or ripple of the FIG. 1 embodiment, assuming that Q is 60°, may be read from the graph or calculated from geometrical considerations. 
     When the quadrature hybrid is installed, the phasor Q 1  must be rotated an additional 90° to provide the proper input. The phasor diagram corresponding to FIG. 3E with this hybrid will be rotated 90° clockwise and show the same summation of phasors. 
     In the graph of FIG. 3E, the ripple is represented by the difference between the distance from the origin to the circumference of the circle and the distance from the origin to the center of the applicable chord. Assuming the above conditions, the points a, b and c are at the tips of the three pertinent phasors, and the chords connecting a and b, and connecting b and c are the applicable chords. The distances in FIG. 3E representing the resulting ripple are thus the differences between the lines R 3  and Q 1  and between R 2  and Q 1 . At the center of the transition there is no ripple since Q 1  is a unit phasor equal to Q 2  and Q 3 . 
     Numerically the relationship between R 1 , R 2  and R 3  and Q 1  are cosines of the appropriate angles: 
     
         |R.sub.1 /Q.sub.1 |=cos Θ/2 (e.g. 30°, 22.5°) 
    
     
         |R.sub.3 /Q.sub.1 |=|R.sub.2 /Q.sub.1 |cos Θ/4 (e.g. 15°, 11.25°) 
    
     The numerical ratio representing the ripple ratio for the Θ=60° example is 0.966 and in dB, -0.301 dB. Should the angle Θ be reduced to 45° (and the frequency multiplication increased from 3 to 4 to obtain ±90° phase shifts), the numerical ratio representing the ripple ratio is 0.981 and in dB, -0.169 dB. 
     The ripple, assuming that one only supplies Q 2  and Q 3 , which is the prior art approach, is represented by the distance between the chord a c and the arc. The distance representing the ripple in the prior art approach is thus the difference between Q 1  and R 1 . With a phase angle Θ of 60° the ripple ratio is 0.866, and in dB, -1.25 dB. The ripple performance is improved by a factor of four by use of the sustained phasor Q 1 , supplied to the summation hybrid HY 3 . With a phase angle Θ of 45°, the ripple ratio for the prior art approach is 0.924, and in db -0.688 dB. Here also the ripple performance is improved by a factor of four by use of the sustained phasor Q 1  supplied to the summation hybrid HY 3 . 
     The ripple present in prior art arrangements is well known. In a practical case where a phase modulation of ±90° is directly obtained an amplitude reduction in the transition of 23 dB is typical. Where the phase modulation is reduced to ±25°, the amplitude reduction falls to 0.6 dB. The use of the sustained phasor would reduce these ripples substantially. 
     The foregoing approach represents a first order correction. An equal ripple correction illustrated in FIG. 4 may be preferable, if an increase in the peak value of the phasor is acceptable. Assuming that an equal ripple approach is used, which is achieved by increasing the length of phasor Q 1  to (Q 1  +δ) in relation to Q 2  and Q 3  (Q 1 , Q 2  and Q 3  all previously being treated as unit phasors). The increase is to the amount required to equalize the excess &#34;δ&#34; of phasor (Q 1  +δ) to the excess (also &#34;δ&#34;) of the phasors Q 2  or Q 3  over the newly drawn line H, now a secant. The new secant H is drawn between Q 2  or Q 3  and Q 1  +δ. The ripple &#34;δ&#34;, drawn to the secant, equals R 4  -Q 1 . The calculated improvement in ripple is the ratio between R 4  /Q 1  =20 log 10  (1-δ/Q 1 ). In the case of Θ=60°, the ripple ratio is reduced to 0.976, or in dB -0.208 dB representing a 0.1 dB improvement in ripple over the corresponding first order correction, and in the case of Θ=45° the ripple ratio is reduced to 0.987 or in dB -0.116 dB, representing an 0.05 dB improvement over the corresponding first order correction. 
     The relationships for calculating the performance of an equal ripple adjustment, using the graph of FIG. 4, may be derived in the following manner. 
     
         Θ/2=β+β+α 
    
     
         Q-δ=Q cos β 
    
     
         ∴β=cos.sup.-1 (1-δ/Q) 
    
     
         Q-δ=(Q+δ) cos (α+β) 
    
     
         ∴α+β=cos.sup.-1 (1-δ/Q)/(1+δ/Q) 
    
     
         Θ/2=cos.sup.-1 (1-δ/Q)+cos .sup.-1 (1-δ/Q)/(1+δ/Q) 
    
     If we solve for δ/Q knowing Θ (e.g. 60°, 45°), then: 
     
         R.sub.4 /Q=1-δ/Q, or 
    
     
         R.sub.4 /Q=20 log.sub.10 (1-δ/Q). 
    
     The phasors Q, Q+δ and H (the secant) must then close. The closure may require a small angular readjustment of the component phasors I 3  or J 3  making up Q 2  and Q 3 . 
     The switch SW 1  may take the form of a GaAs SPDT MMIC switch, for instance model SW-233 or SW-236 by the Adams Russell Components Group. The indicated switch contains an internal drive circuit. One may also use a GaAs switch requiring an external drive circuit. 
     In addition, the attenuator ATT 2  which follows the switch SW 1 , may combine a limiting amplifier and additional attenuation so as to bring the nominal net gain to -7 dB. The limiting amplifier may be used to further reduce small differences between the waves I 2  and J 2 , and to further reduce the dip which normally occurs as the switch SW 1  goes from one state to the other. The limiting amplifier design must avoid the creation of spurious signals and must not introduce phase distortion. 
     Instead of a GaAs MMIC switch one may use a dc switched double balanced modulator, in which the switch position is controlled by the polarity of an applied dc bias voltage. This variety normally uses diodes in a ring configuration.