Abstract:
A sigma-delta-type converter comprises: a sigma-delta modulator having a digital output having a first prefixed bit number; a randomizer including a circular memory; an analogical reconstruction filter comprising a branch number equal to said first default number including sampling capacitors and a low-pass filter; characterized in that said circular memory comprises a number of elements equal to said first default number of bits less one and receives in input said first default number of bits less one, and in that a bit of said first default number of bits is applied to one of said branches of said reconstruction filter.

Description:
[0001]    This application claims priority from Italian patent application No. MI2002A000459, filed Mar. 6, 2002, which is incorporated herein by reference. 
     
    
     
       TECHNICAL FIELD  
         [0002]    The present invention refers to an analog-to-digital (ADC) or digital-to-analog (DAC) sigma-delta-type converter and to a method to carry out a sigma-delta-type conversion; it refers particularly to a randomizer for a sigma-delta-type converter.  
         BACKGROUND  
         [0003]    In the last few years, high-resolution digital-to-analog sigma-delta-type (ΣΔ) converters (DAC) have become very popular in audio applications. In particular,in order to reduce the silicon area and power consumption, multi-bit lower-order modulators are largely used. But they have however the drawback to have to use a random-number generating structure (randomizer) to interface the quantizer output levels with the following reconstruction filter. In fact, the reconstruction filter if realized with switching capacitors requires sampling capacitors whose values are subject to errors related to the technological process used to manufacture the converter, and these errors heavily influence the converter performance. However, the cumulative error, due to the presence of the capacitors, becomes equal to zero when all the capacitors have been selected for the same number of times.  
           [0004]    Different types of randomizers are known, such as, for example, that described in the article by Rex T. Baird and Terri S. Fiez, “Linearity Enhancement of Multibit DS A/D and D/A Converters Using Weighted Averaging”, IEEE Trans. On Circuits and Systems, vol.42, No. 12, December 1995. This article is one of the best from the point of view of the simplicity of the circuit realization, because only one circular memory supplied by the digital output of the modulator is enough to determine which capacitors will be used at every synchronization cycle.  
           [0005]    One of the most important limitations of this kind of structure is the fact that it does not have a good performance if applied to structures requiring an odd number of quantization levels. On the other hand (see I. Fujimori, T. Sugimoto, “A 1.5 V, 4.1 mW Dual-Channel Audio Delta-Sigma D/A Converter”, IEEE Journal Of Solid-state Circuits, vol. 33, No. 12, December 1998) it is important to use an odd number of levels of the quantizer to avoid the free tones produced by the low-order modulators.  
           [0006]    Another problem is the fact that, when a signal is applied to the modulator having a low dynamic, the circular memory saturates easily.  
           [0007]    In fact, for example in the case of a circular memory with 12 elements and with a low-level input signal, a logical word having 6 consecutive identical logic levels will frequently be used. In the presence of a high number of 6 consecutive values, the action of the randomizer will not be efficient because every two synchronization cycles the same capacitors of the reconstruction filter will be selected, nullifying the presence of the randomizer. In such a situation, tones at a frequency equal to half the synchronization frequency will be produced that will disturb the signal to be converted.  
           [0008]    For this reason, a second-order randomizer is often used. But as is known, this often increases the complexity of the circuitry, the area occupied by the circuitry, and the power dissipated by the circuitry.  
         SUMMARY  
         [0009]    In view of the state of the art described, an embodiment of the present invention provides a sigma-delta converter that does not have the drawbacks of the known art.  
           [0010]    According to this embodiment, the sigma-delta-type converter comprises: a sigma-delta modulator having a digital output having a first prefixed number of bits; a randomizer including a circular memory; an analogic reconstruction filter comprising a branch number equal to said first prefixed number and including sampling capacitors and a low-pass filter; characterized in that said circular memory comprises a number of elements equal to said first prefixed number of bits less one and receives at an input said first prefixed number of bits less one, and in that a bit of said first prefixed number of bits is applied to one of said branches of said reconstruction filter.  
           [0011]    According to another embodiment of the invention, a method for carrying out a sigma-delta-type conversion comprises the steps of providing at the output of a multi-bit sigma-delta modulator a prefixed number of bits; applying at a randomizer a number of bits equal to said prefixed number of bits less one; applying the outputs of said randomizer to corresponding inputs of a converter with capacitors; applying a bit provided by said sigma-delta modulator to an input of said converter with capacitors.  
           [0012]    Thanks to these embodiments, it is possible to avoid the saturation of the circular memory, to obtain a reduction of the quantization noise, and to avoid the generation of free tones. It is possible to use a sigma-delta modulator of low order and/or at a low frequency of operation. Furthermore, a reduction of the circuit area and a reduction of the dissipated power are obtained. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]    The features and the advantages of the present invention will be made more evident by the following detailed description of a particular embodiment, illustrated as a non-limiting example in the annexed drawings, wherein:  
         [0014]    [0014]FIG. 1 is a schematic diagram of a sigma-delta-type digital-to-analog converter according to an embodiment of the present invention;  
         [0015]    [0015]FIG. 2 is a schematic diagram of a sigma-delta modulator according to an embodiment of the invention;  
         [0016]    [0016]FIG. 3 a  shows a repetitive sequence of values in the case of a circular memory with 12 elements according to the prior art;  
         [0017]    [0017]FIG. 3 b  shows a repetitive sequence of values in the case of a circular memory with 11 elements according to an embodiment of the present invention;  
         [0018]    [0018]FIG. 4 is a schematic diagram of a sigma-delta-type analog-to-digital converter according to an embodiment of the present invention; 
     
    
     DESCRIPTION OF THE INVENTION  
       [0019]    Referring now to FIG. 1, which is a schematic diagram of a sigma-delta-type ADC that includes a DAC that, for representative simplicity, has 5 analog output levels. A sigma-delta modulator  10  receives an analog signal, and it produces at its output a digital signal having preferably 2n bits (even) for 2n+1 analog-output levels (odd), where n in this case is equal to 2. The sigma-delta modulator  10  is followed by a structure for generating random numbers (randomizer)  20  that includes a circular memory  21  having 2n−1 elements and by an output selector  22 . The structure  20  receives 2n−1 bits from the sigma-delta modulator  10  and it provides 2n −1 outputs.  
         [0020]    The 2n−1 outputs of the sigma-delta modulator  10  are applied to respective inputs of a reconstruction filter having 2n branches  30  including sampling capacitors (defined also switched capacitors)  31 - 34  followed by a low-pass filter  40 .  
         [0021]    The 2n branches  30  including the sampling capacitors  31 - 34  have 2n inputs respectively connected to a terminal of the switches  310 ,  320 ,  330  and  340 . The other terminal of the switches  310 ,  320 ,  330  and  340  is connected to a terminal of the capacitors  31 - 34  and to a terminal of the switches  312 ,  322 ,  332  and  342 . The other terminal of the capacitors  31 - 34  is connected to a terminal of the switches  311 ,  321 ,  331 ,  341 ,  313 ,  323 ,  333  and  343 . The other terminal of the switches  312 ,  322 ,  332 ,  342 ,  313 ,  323 ,  333  and  343  is connected to a reference voltage Vref.  
         [0022]    The switches  310 ,  320 ,, 330 ,  340 ,  313 ,  323 ,  333  and  343  are controlled by a synchronism signal, and the switches  311 ,  321 ,  331 ,  341 ,  312 ,  322 ,  332  and  342  are controlled by the complement of the synchronism signal.  
         [0023]    Of the 2n branches  30 , 2n−1 branches (those that contain the capacitors  32 - 34 ) are connected to the output of the randomizer  20  while a remaining branch (which contains the capacitor  31 ) is connected directly to the sigma-delta modulator  10 .  
         [0024]    The branches  30  can be also considered as the elements to realize the DAC with capacitors.  
         [0025]    [0025]FIG. 2 shows a schematic diagram of the sigma-delta modulator  10  of FIG. 1 according to an embodiment of the invention. It is constituted by an integrator  100  connected to a quantizer  110  that provides at its output 2n bits connected to a circuit  120  able to produce a parallel output having a thermometric coding of the signal at its input. The 2n bits at the output of the quantizer  110  are also connected to a conversion circuit  130 , whose output signal is algebraically added with the input signal by the adder node  140  (note that the output of the circuit  130  is coupled to an inverting input of the node  140 ). The output of the adder node  140  is applied to the input of the integrator  100 .  
         [0026]    A basic goal of this embodiment of the present invention is not to effect the random choice of an input of the reconstruction filter  30 ,  40 . Particularly, directly connecting the most significant bit (MSB) in the thermometric coding to a branch  30  results in asymmetrical randomness. In fact, in FIG. 3 a , where with e 1 -e 12  the elements of the circular memory and consequently the inputs of the reconstruction filter are represented, in the case of the known art it can be seen that with n=6, that is with 12 elements of the circular memory, with a repetitive sequence of 6 values, the action of the randomizer will not be efficient because every two synchronization cycles the same input of the reconstruction filter will be selected, frustrating the presence of the randomizer. In this case, instead of FIG. 3 b , according to an embodiment of the present invention, with n=6, and with 11 elements of the circular memory  21 , it occurs that with a repetitive sequence of 6 values, the choice of the inputs of the branches  30  is variable.  
         [0027]    In this embodiment, the choice of the bit that is not random (here, the bit coupled to the switch  310  is FIG. 1) has been optimized for the purpose of determining the linearity losses. In fact, if only 11 random elements of 12 are considered, an angle in the straight line can appear that represents the characteristic of linearity. Particularly the most significant bit (MSB) has been selected because, referring to a statistic analysis of a signal of 22 kHz, at the limit of the audio band, it occurred 42 times out of a total of 65536. This means that for this kind of application the linearity loss is very low and the distortion problems are not meaningful, further considering that at high dynamic levels the reconstruction filter gives the greatest distortion contribution.  
         [0028]    According to an embodiment of the present invention, a converter is realized and it has been compared, as regards the signal to noise ratio (SNR), with one without a randomizer and with one with a randomizer according to the known art, and the results are shown in Table 1. The input signal was an audio signal with an audio band of 22 kHz.  
                           TABLE 1                                   SNR with               SNR with a   randomizer           SNR without   randomizer of   according to the present           randomizer (dB)   the known art (dB)   invention (dB)       Amplitude of   Minimum value-   Minimum value-   Minimum value-       the input signal (dB)   typical value   typical value   typical value                   0-−1   55-65   105-107    96-107       −1-−25   56-65   105-108   106-108       −25-−35   75-85    98-104   107-110       −35-−50   75-84   90-98   106-109       −50-−65   75-84   100-104   106-109       −65→   75-85   106-109   105-109                  
 
         [0029]    [0029]FIG. 4 shows a schematic diagram of a sigma-delta-type ADC converter according to an embodiment of the present invention. It includes a sigma-delta modulator  10  that receives an analog signal and provides a digital signal. The sigma-delta modulator  10  is connected to a generating structure of random numbers (randomizer)  20 , that comprises a circular memory  21  and a selector  22  of the outputs. The randomizer  20  receives 2n−1 bits from the sigma-delta modulator  10  and it provides 2n−1 outputs.  
         [0030]    The 2n−1 outputs of the sigma-delta modulator  10  are applied to the respective inputs of a reconstruction filter  30 ,  40  composed by 2n branches  30  including sampling capacitors  31 - 34  followed by a low-pass filter  40  (see FIG. 1 ).The adder node  140  adds the output signal of the filter  40  to the input signal (note that the output signal of the filter  40  is coupled to an inverting terminal of the adder node  140 ). The output of the adder node  140  is applied to the input of the sigma-delta modulator  10 .  
         [0031]    The various blocks of FIGS. 1, 2, and  4  have not been described in detail because they are conventional.  
         [0032]    The sigma-delta-type converter to which the randomizer  20  is applied can be both of the switched-capacitor type or of the switched-current-generator type. However the above-described solution can be applied whenever some elements subject to variation in the values due to the technological process have to be chosen in a random way.  
         [0033]    From the foregoing, it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.