Abstract:
First and second networks, for example Controller Area Networks (CANs), of different physical layers are interfaced by applying signals of the busses of the two networks to respective transceivers. A dominant state of one of the busses is sensed and data is transferred between the two transceivers in a direction from the dominant bus. The two busses are interfaced by a logic circuit interposed between the transceivers. A control circuit is coupled to the first and second logic units for mutually exclusively activating and deactivating the first and second logic units to control the direction of data transfer between the busses.

Description:
TECHNICAL FIELD  
       [0001]     The present disclosure relates to the control of data transfer between bus systems having different physical layer characteristics, more particularly to controlling the direction of data transfer between single wire and dual wire busses.  
       BACKGROUND  
       [0002]     A Controller Area Network (CAN) is a serial network using a protocol that defines the data link and part of the physical layer in the OSI model. A CAN bus is a broadcast bus that can link to a plurality of transceiver nodes. The bits in a CAN message can be sent as either high or low. Data messages conventionally are in Non-Return To Zero (NRZ) bit coding with bit stuffing used to complete message frames.  
         [0003]     A dominant bus state, conventionally logical 0, and a recessive bus state, conventionally logical 1, correspond to electrical levels that depend on the physical layer used. If a communication node connected to the bus is driving the bus to the dominant state, the whole bus is in that state regardless of the number of nodes transmitting a recessive state. Before sending a message bit, a CAN node checks if the bus is busy to avoid collision. As low bits are always dominant, if one node tries to send a low and another node tries to send a high, the result on the bus will be a low. This functionality corresponds to a logical AND since the recessive state (logically high level) is obtained only when all nodes output a logically high level. A transmitting node always checks on the bus while transmitting. A node that sends a high in the arbitration field and detects a low knows that it has lost arbitration. It stops transmitting, letting the other node, with a higher priority message, continue uninterrupted.  
         [0004]     Data messages transmitted from any node on the CAN bus do not contain addresses of either the transmitting node or intended receiving node(s). A message, instead, is labeled with an identifier. Each of the other nodes on the network receive the message and check the identifier to determine if the message is relevant to the particular receiving node. Two nodes on the network are not allowed to send messages with the same identifier. If two nodes attempt to send a message with the same identifier at the same time, one of the transmitting nodes will detect that its message is distorted outside of the arbitration field.  
         [0005]     Under ISO/SAE CAN standards, CAN bus systems may employ dual wire busses for higher speeds, up to 1 Mbit/second, or single wire busses for lower speeds of up to 50 kbit/second. Various transceivers, such as the Philips AU5790 single wire transceiver, the Linear Technology LT1796 dual wire transceiver, and the Philips 82C250, are commercially available as well as protocol controllers.  
         [0006]     Dual wire CAN bus systems and currently also single wire CAN bus systems have been employed in automotive systems. Typically, a plurality of diagnostic and control modules are provided in a vehicle and linked by a CAN bus. A technician can access the CAN network, and thus the modules, through a coupling to an external network. Various testing and diagnostic functions can then be performed through bidirectional data communications between the two networks.  
         [0007]     Incompatibility problems are presented if the physical layer components of the vehicle CAN bus system and the external network are different. If the external network employs a dual wire CAN configuration while the vehicle bus system is a single wire CAN configuration, for example, an interface is needed to permit data communication between the two dissimilar busses. The interface must also control the direction of data transfer between the two busses in accordance with dominant bit signals issued on the busses. Transitions between data transfer directions should take place without incurring closed loop oscillations. Similar incompatibility issues require resolution when interfacing dual wire bus systems of different physical level properties.  
       SUMMARY OF THE DISCLOSURE  
       [0008]     The subject matter described herein fulfills the above-described needs of the prior art. First and second CAN networks of different physical layers are interfaced by applying signals of the CAN busses of the two networks to respective transceivers. A dominant state of one of the busses is sensed and data is transferred between the two transceivers in a direction from the dominant bus.  
         [0009]     The first and second CAN networks may comprise, respectively, a single wire bus and a dual wire bus. The two busses are interfaced by a logic circuit interposed between the transceivers. A first logic unit is operable as a unidirectional switch for passing signals between the CAN busses in a first direction. A second logic unit is operable as a unidirectional switch for passing signals between the CAN busses in a second direction. A control circuit is coupled to the first and second logic units for mutually exclusively activating and deactivating the first and second logic units to control the direction of data transfer between the CAN busses.  
         [0010]     In one configuration, the direction of current in one of the busses is sensed and activation and deactivation signals are applied to the first and second logic units in response to the sensed direction. The current direction may be sensed by a comparator having a pair of inputs coupled to voltage nodes on one of the busses and an output coupled in reciprocal logical states, respectively, to the first and second logic units.  
         [0011]     In a variation of this configuration, upon receipt of a dominant signal from a bus previously in a recessive state, transition of the data transfer direction is delayed. An output of the first logic unit is coupled to an input of the second logic unit and an output of the second logic unit is coupled to an input of the first logic unit. A delay logic unit has an output coupled to the second transceiver and a first input connected to the output of the first logic unit. A delay circuit is coupled between a second input of the delay logic unit and the output of the first logic unit. An inverter is coupled to the output of the first logic circuit and an inverter is coupled to the output of the second logic circuit.  
         [0012]     Additional aspects and advantages will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the disclosed concepts are applicable to other and different embodiments, and the disclosed details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     In the figures of the accompanying drawings, like reference numerals refer to similar elements.  
         [0014]      FIG. 1  is a schematic diagram of an interface arrangement between dissimilar CAN networks in accordance with the present invention.  
         [0015]      FIG. 2  is a schematic diagram that is a variation of the arrangement of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION  
       [0016]      FIG. 1  illustrates an arrangement for interfacing between a dual-wire CAN bus system  10  and a single-wire CAN bus system  20 . CAN bus wires  12  and  14  link a plurality of CAN nodes  16  with dual-wire transceiver  18 . The dual-wire transceiver  18 , which may comprise a commercially available unit such as the Philips PCA82C250, is connected to logic interface  40  by send (T×D) line  42  and receive (R×D) line  44 .  
         [0017]     CAN bus wire  22  links a plurality of CAN nodes  26  to single-wire transceiver  28 . The single-wire transceiver  28 , which may comprise a commercially available unit such as the Philips AU5790D, is connected to logic interface  40  by send (T×D) line  46  and receive (R×D) line  48 .  
         [0018]     Logic circuit  40  comprises OR gates  50 ,  52  and  54 , inverters  56  and  58 , resistor  60  and capacitor  62 . A first input of OR gate  50  is connected to line  44 . A second input of OR gate  50  is connected to the output of inverter  56 . A first input of OR gate  52  is connected to line  48 . A second input of OR gate  52  is connected to the output of inverter  58 . The output of OR gate  52  is connected to the input of inverter  56  and to line  42 .  
         [0019]     Resistor  60  and capacitor  62  are connected in series between the output of OR gate  50  and ground. The output of OR gate  50  is also connected to the input of inverter  58  and a first input of OR gate  54 . The second input of OR gate  54  is connected to the junction between resistor  60  and capacitor  62 . The output of OR gate  54  is connected to line  46 .  
         [0020]     OR gate  50  and inverter  56  function as a unidirectional directional switch that passes data from the output of transceiver  18  to the input of transceiver  28  and thus to wire  22  of the single-wire CAN network  20 . This path will be in place if a dominant bit is sent by a CAN node  16  on the dual-wire bus before a dominant bit is sent by a CAN node  26  on the single wire bus. OR gate  52  and inverter  58  function as a unidirectional directional switch that passes data from the output of transceiver  28  to the input of transceiver  18  and thus to wires  12  and  14  of dual-wire CAN network  10 . This path will be in place if a dominant bit is sent by a CAN node  26  on the single-wire bus before a dominant bit is sent by a CAN node  16  on the dual-wire bus.  
         [0021]     OR gates  50  and  52  are in closed switch states when their output logic levels follow the logic input levels on the receive lines  44  and  48 , respectively, at their first inputs. These states are in effect when the logic levels are low at the second inputs, respectively. When one of the transceivers is in a dominant state, the switch states of OR gates  50  and  52  are mutually exclusive, as the output of each gate is fed to the second input of the other gate through an inverter. When a dominant bus becomes recessive, another CAN node can become dominant and take over the transmit direction.  
         [0022]     OR gate  54  prevents oscillation in the transition of transmission direction that could occur if the output of OR gate  50  were directly connected to the input line  46  of transceiver  28 . For example, it is assumed that transceiver  28  is in a dominant state (logic level low) and is about to go recessive (logic level high). Prior to the transition, the low logic level output by transceiver  28  will have been reflected as a low logic level on the dual bus linked to transceiver  18 . In the absence of the delay circuit and OR gate  54 , in response to the occurrence of a high level at line  48  received from transceiver  28 , a low level signal is applied to the second input of OR gate  50  via inverter  56 . As there is a finite time delay, t off , in the transceiver  18  for transition to the high logic level received at line  42 , a low logic level will continue to be applied to the first input of OR gate  50  until the delay period t off  has expired. If the low logic level output of OR gate  50  is directly fed to transceiver  28 , bus  22  will be driven to the low logic level. Transceiver  28 , which briefly transitioned to the recessive state by a high logic level bit at bus  22 , will again attempt to assert a dominant state. The assertion of the dominant state will oscillate between the two transceivers. Data transmission will be precluded during the time in which neither transceiver can gain dominance. A similar oscillation effect would occur when the transceiver  18  relinquishes its dominant state.  
         [0023]     The oscillation effects are eliminated by the delay circuit and OR gate  54 . Upon receipt of a high logic level signal at line  48  from transceiver  28 , a low level logic signal similarly will be output by OR gate  50  and immediately applied to the first input of OR gate  54 . However, the second input of OR gate  54  will remain at the high logic level until capacitor  62  has sufficiently discharged. This time delay, determined by the values of resistor  60  and capacitor  62 , is set to equal or exceed the t off  delay period of transceiver  18 . During this time, the logic level output of transceiver  28  remains high to open the state of OR gate  52 . The low logic level signal output by OR gate thereafter will not change back the direction of data transmission as inverter  58  will maintain a high level input to OR gate  52 .  
         [0024]     In the embodiment of  FIG. 1 , the delay circuit and OR gate  54  are configured to couple the output of OR gate  50  to transceiver  28 . Alternatively, these elements may be configured between the output of OR gate  52  and the input of transceiver  18  while the output of OR gate  50  is directly connected to transceiver  28 . The time delay of resistor  60  and capacitor  62  would then be set to equal or exceed the t off  delay period of transceiver  28 . Oscillation would again be prevented. As the dual wire high speed transceiver  18 , exemplified in  FIG. 1 , incurs a shorter t off  delay period than that of the slower speed single wire transceiver  28 , the illustrated configuration is preferable for this example.  
         [0025]      FIG. 2  illustrates a variation of the interface shown in  FIG. 1 . A first input of OR gate  50  is connected to receive line  44  from transceiver  18 . The output of OR gate  50  is connected to the send line  46  to transceiver  28 . A first input of OR gate  52  is connected to receive line  48  from transceiver  28 . The output of OR gate  52  is connected to the send line  42  to transceiver  28 . A bias circuit, comprising resistors  70  and  72 , are coupled to the transceiver  18 . Resistor  70  is serially connected to bus line  12 . Resistor  72  is connected across lines  12  and  14 . A first node of resistor  70  is connected to ground through resistor  74 . The second node of resistor  70  is connected to the voltage supply through resistor  76 . Each node of resistor  70  is also connected to a respective input terminal of comparator  80 . The second input of OR gate  52  is directly connected to the output of comparator  80 . The second input of OR gate  50  is connected to the output of comparator  80  via inverter  82 .  
         [0026]     In operation, if all CAN nodes are recessive, lines  12  and  14  will float at a voltage level, for example, at 2.5 v. A small bias voltage is created across resistor  70  via the source to ground serial circuit. The bias voltage creates a low logic level at the output of comparator  80 . The low logic level signal is thus applied to the second input of OR gate  52 , while the inverted signal of high logic level is applied to the second input of OR gate  50 . The default data transfer direction is thus set to transmit from transceiver  28  to transceiver  18 .  
         [0027]     If a CAN node  26  transmits a low logic level (dominant) bit, the bit is copied to the dual wire bus through OR gate  52  and transceiver  18 . At this time, both busses become dominant. The output of the comparator  80  does not change logic state because the polarity of the voltage across resistor  70  does not change. If, instead, a CAN node  16  transmits a low logic level bit, line  12  will be driven high and line  14  will be driven low. Current will flow through resistor  70  in the opposite direction. That is, current will flow from bus line  12 , through resistors  70  and  72 , to bus line  14 . The output of comparator  80  will now be at a high logic level to change the OR gate to an open state and to change the OR gate  50 , via invertor  82 , to a closed state. Data transmission is thus set to the direction from transceiver  18  to transceiver  28 . Dominant bits from a CAN node  16  will be copied by transceiver  28  to the bus  22 .  
         [0028]     If a CAN node  16  at the dual wire bus and a CAN  26  at the single wire bus  22  output a dominant bit at approximately the same time, both busses will achieve a dominant state. The direction of current flow through resistor may not be readily discernable as it depends upon which of node  16  or transceiver  18  imposes the highest voltage. Thus the logic level of the output of comparator  80  may be in either state. Such a situation does not cause a problem because both busses are in a dominant state and the data transfer direction is not relevant. The logic circuit would merely make a bus dominant that is already dominant.  
         [0029]     In this disclosure there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein. Although CAN bus systems have been exemplified above, the invention is beneficial in other communication systems in which busses of different physical layers are to be interfaced. Aspects of the invention are also applicable for interfacing two dual wire bus systems having different physical characteristics and for interfacing two single wire bus systems having different physical characteristics.