Abstract:
A liquid crystal display device and a fabricating method thereof enabling an optimized process by forming metal samples having various line widths on a circumference of a cell. The metal samples enable the measurement of a specific resistance of a data line formed by an ashing process. The specific resistance measurements are useful for designing the device. The invention includes a substrate divided into active and dummy areas, in which gate lines and data lines formed in the active area in directions perpendicular to each other. A plurality of metal samples are formed in the dummy area in which the metal samples have differing line widths in order to monitor the etch rate when forming the data line and the source/drain electrodes of the display device.

Description:
RELATED DATA  
         [0001]    This application claims benefit under 35 U.S.C. §119 of Korean Application No. P2001-88453 filed on Dec. 29, 2001, which is hereby incorporated by reference herein.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a liquid crystal display device and a fabricating method thereof enabling to monitor an ashing rate just to carry out the process of forming a data line and source/drain electrodes uniformly using Mo.  
           [0004]    2. Discussion of the Prior Art  
           [0005]    Generally, a liquid crystal display has characteristics of low-voltage driving, low power consumption, full-color realization, lightness and compact size, and the like. These characteristics enable the widespread use of liquid crystal displays in devices such as televisions, airplane monitors, PDAs, mobile phones, and the like as well as calculators, watches, notebook computers, and personal computers.  
           [0006]    Liquid crystal displays mainly include a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel. Liquid crystal panels also include first and second glass substrates bonded to each other with a space therebetween and a liquid crystal layer injected in the space between the first and second glass substrates.  
           [0007]    On the first glass substrate (TFT array substrate), a plurality of gate lines are arranged in one direction at a predetermined distance from each other. A plurality of data lines are arranged in a direction perpendicular to the gate lines at a predetermined distance from each other. A plurality of pixel electrodes are formed in a matrix pattern in pixel areas defined at locations where the gate and data lines cross each other. A plurality of thin film transistors are switched by signals from the gate lines and transfer signals from the data lines to the pixel electrodes.  
           [0008]    The second glass substrate (color filter substrate) supports a black matrix layer for cutting off light to areas other than the pixel areas, an R/G/B color filter layer for representing colors, and a common electrode for realizing an image.  
           [0009]    The first and second substrates are bonded to each other by a sealant having a liquid crystal injection inlet for forming a predetermined space between the substrates. Liquid crystals are injected through the inlet between the first and second substrates.  
           [0010]    One method of injecting the liquid crystals includes the steps of maintaining a vacuum state between the two substrates bonded to each other through the sealant and dipping the liquid crystal injection inlet in the liquid crystals so that injection between the two substrates takes place by capillary action. Once the liquid crystals are injected, the liquid crystal injection inlet is sealed using a sealing agent.  
           [0011]    In another method of fabricating a liquid crystal display a ‘liquid crystal dropping’ process is carried out where the substrates are bonded to each other after a proper amount of liquid crystals have been dropped on the first or second substrate.  
           [0012]    Conventionally, a thin film transistor array having the gate line, data line, pixel electrode, and thin film transistor formed on the first substrate (TFT array substrate) is fabricated using 5˜8 masks. More recently, a new fabrication technique using four masks has been developed. In the new fabrication method, a 4-mask process, is used in the four mask process, a separate mask is used for a gate line forming process, a process of forming a data line having source/drain electrodes and an active layer, a process of forming a contact hole in a passivation layer, and a process of forming a pixel electrode, respectively.  
           [0013]    In the 4 mask process, molybdenum (Mo) is used to form the data line instead of chromium (Cr) in the process of forming the data line and active layer. In this process, however, the etch rate variation of Mo is greater than that of Cr.  
           [0014]    A method for fabricating a thin film transistor array in a liquid crystal display using four masks according to the prior art will now be explained by referring to FIGS. 1 and 2 of the drawings.  
           [0015]    [0015]FIG. 1 illustrates a layout of a liquid crystal display using four masks according to a prior art process. FIGS. 2A to  2 G illustrate cross-sectional views of a process along cutting lines I-I′, II-II′, and III-III′ at various stages of the prior art process.  
           [0016]    Referring to FIG. 1, a liquid crystal display by the  4 -masks process includes a gate line  101  arranged in one direction and a data line  105   d  arranged in a direction perpendicular to the gate line  101 . A pixel area is defined by the gate line  101  and the data line  105   d . As will subsequently be described, a semiconductor layer  103  and a metal layer are stacked on the gate line  101 .  
           [0017]    A pixel electrode  107   a  is formed in the pixel area, and a thin film transistor is formed at an intersection between the gate line  101  and data line  105   d . A contact hole  109   a  is formed at a drain electrode of the thin film transistor in order to connect the drain electrode to the pixel electrode  107   a.    
           [0018]    Other contact holes  109   b  and  109   c  are formed on areas of a pad  101   a  of the gate line  101  and a pad  105   a  of the data line  105   d  just to have pad electrodes  110  formed thereon with the same material of the pixel electrode  107   a , respectively.  
           [0019]    Referring to FIG. 2A, after a substrate  100  has been cleaned, a gate metal is deposited on the substrate  100  by sputtering. A first photoresist layer is coated on the gate metal, and then exposure and development to form a first photoresist pattern P/R 1 . Then, the gate metal is selectively removed using the first photoresist pattern as a mask to form a gate line  101  and a gate pad  101   a . The photoresist pattern P/R 1  is then stripped.  
           [0020]    Referring to FIG. 2B, a gate insulating layer  102 , a semiconductor layer  103 , an ohmic contact layer  104 , and a data metal layer  105  having low resistance are sequentially formed on an entire surface of the substrate including the gate line and pad  101  and  101   a . A second photoresist layer is then coated on the data metal layer  105 . In this case, the data metal layer  105  having the low resistance is formed of Mo.  
           [0021]    Referring to FIG. 2C, a second photoresist pattern P/R 2  for a data line pattern is formed by exposure and development using a second mask(half-tone mask). In this case, the second mask(half-tone mask) is formed to cut off light corresponding to the data line completely as well as transmit the light of a predetermined quantity to a portion corresponding to a channel area of a thin film transistor. Hence, the developed second photoresist pattern maintains its originally-deposited thickness on a data line forming area but is formed relatively thin on the channel area of the thin film transistor.  
           [0022]    Subsequently, the low-resistance data metal layer  105 , ohmic contact layer  104 , and semiconductor layer  103  except portions in the data line (including pad) and thin film transistor forming areas, are removed by wet or dry etching using the second photoresist pattern P/R 2  as a mask.  
           [0023]    Referring to FIG. 2D, ashing is carried out on the second photoresist pattern P/R 2  in order to remove a portion of the second photoresist pattern corresponding to the channel area of the thin film transistor. In this case, an overall thickness of the second photoresist pattern is decreased as well as a width thereof. Hence, widths of the data line and the source/drain electrodes that will be formed later will be varied.  
           [0024]    Referring to FIG. 2E, the low resistance data metal layer  105  and ohmic contact layer  104  corresponding to the channel area of the thin film transistor are etched using the ashed second photoresist pattern P/R 2 . The etching process forms a data line  105   d  including a final pad and a thin film transistor including source and drain electrodes  105   a  and  105   b . The second photoresist pattern P/R 2  is then stripped.  
           [0025]    Referring to FIG. 2F, a passivation layer  106  is deposited over an entire surface of the substrate including the source and drain electrodes  105   a  and  105   b . Then, a third photoresist P/R 3  is coated on the passivation layer  106 . The photoresits is exposed and developed to form a third photoresist pattern P/R 3  exposing a portion of the drain electrode  105   b  and the gate and data pads  101   b  and  105   c . The passivation layer  106  is then selectively etched using the third photoresist pattern as a mask to form contact holes  109   a ,  109   b , and  109   c  on the drain electrode  105   b , gate pad  101   b , and data pad  105   c , respectively. Then, the third photoresist pattern P/R 3  is stripped.  
           [0026]    Referring to FIG. 2G, a transparent electrode (ITO)  107  is deposited on an entire surface and connected to the drain electrode  105   b , gate pad  101   b , and data pad  105   c  through the contact holes  109   a ,  109   b , and  109   c  and fourth photoresist P/R 4  is coated on the transparent electrode  107 . Then the photoresist is exposed and developed to form a fourth photoresist pattern P/R 4  for patterning a pixel electrode and each pad electrode.  
           [0027]    A pixel electrode  107   a  is formed by removing a portion of the transparent electrode selectively using the fourth photoresist pattern as a mask, and simultaneously pad electrodes  110  are formed on the pads. The fourth photoresist pattern is then stripped.  
           [0028]    The prior art liquid crystal display and fabricating method art have the following disadvantages or problems. First, when the liquid crystal display is fabricated using the four masks, when the data metal layer and semiconductor layer are initially patterned, ashing is carried out on the photoresist. Then, the data line metal is etched again to form the final data line. Hence, if Mo is used for the data line metal, the MO etch rate varies at each location. Thus, it is difficult to provide a data line having a precise pattern. Secondly, since it is difficult to provide a precisely patterned data line, the specific resistance of the data line varies. A resistance variation in the data lines increases the possibility of failure of the liquid crystal display.  
         SUMMARY OF THE INVENTION  
         [0029]    The present invention is directed to a liquid crystal display device and a fabricating method that substantially addresses one or more problems associated with the limitations and disadvantages of the prior art.  
           [0030]    An object of the present invention is to provide a liquid crystal display device and a fabricating method in which the process is optimized by forming metal samples for data line patterns having various widths respectively on a circumference of a cell just to measure a specific resistance of data lines formed by an ashing process. Additionally, the measured specific resistance provides information for improving the design of the device.  
           [0031]    Additional advantages, objects, and features of the invention will be set forth in the description which follows and will become apparent to those of ordinary skill in the art.  
           [0032]    To achieve these objects and advantages in accordance with the invention, as embodied and broadly described herein, a liquid crystal display device according to the present invention includes a substrate divided into active and dummy areas. Gate and data lines are formed in the active area in directions perpendicular to each other and a plurality of metal samples are formed in the dummy area.  
           [0033]    Preferably, the line width of the metal samples differ from each other.  
           [0034]    More preferably, the line widths of the metal samples differ by about 1 μm to about 12 μm.  
           [0035]    Preferably, the metal samples are formed of the same material as the data lines.  
           [0036]    Preferably, the data lines and the metal samples are formed by a stacked semiconductor layer and metal layer.  
           [0037]    More preferably, the data line and metal samples are formed of a material including Mo.  
           [0038]    In another aspect of the present invention, a liquid crystal display device includes a substrate divided into active and dummy areas. A gate line besides on the substrate in the active area, and includes a pad. A gate insulating layer overlies the entire surface of the substrate including the gate line. A data line besides on the gate insulating layer in the active area in a direction substantially perpendicular to the gate line. A plurality of metal samples reside on the gate insulating layer in the dummy area and a passivation layer overlies the entire surface of the data line and respective metal samples. A transparent electrode overlies the passivation layer in a pixel area as well as the pads of the gate line, data line, and metal sample.  
           [0039]    Preferably, a plurality of the metal samples differ in widths in order to monitor the etch rate when forming the data line and source/drain electrodes.  
           [0040]    More preferably, a plurality of the metal samples differ in widths by about 1 μm to about 12 μm.  
           [0041]    Preferably, the metal samples are formed with the same material of the data line.  
           [0042]    Preferably, the data line and metal samples are formed by a stacked semiconductor layer and metal layer.  
           [0043]    More preferably, the data line and metal samples are formed of a material including Mo.  
           [0044]    In a further aspect of the present invention, a method of fabricating a liquid crystal display device includes forming a gate line on a substrate to create a gate electrode and forming a gate insulating layer on an entire surface on the substrate. A data line having source/drain electrodes on the gate insulating layer is formed in an active area of the substrate and a plurality of metal samples are simultaneously formed on the gate insulating layer in a dummy area of the substrate. A passivation layer is formed on an entire surface including the data line and metal samples, and a contact hole is formed on the drain electrode and a pixel electrode is formed in a pixel area over the passivation layer.  
           [0045]    Preferably, a plurality of the metal samples are formed having line widths that differ from each other.  
           [0046]    More preferably, a plurality of the metal samples are formed to have line widths that differ by about 1 μm to about 12 μm.  
           [0047]    Preferably, the method includes sequentially forming a semiconductor layer and a metal layer on the gate insulating layer. The metal and semiconductor layers are patterned such that portions thereof remain on areas where the data line, a thin film transistor, and the metal samples are formed. Then, the metal layer is patterned to form a portion thereof corresponding to a channel area of the thin film transistor.  
           [0048]    More preferably, the semiconductor layer includes an active layer and an ohmic contact layer and the ohmic contact layer is patterned together with the metal layer.  
           [0049]    More preferably, the metal layer includes a metal of Mo.  
           [0050]    More preferably, an etch rate when patterning the metal layer is monitored by measuring a thickness of the metal sample.  
           [0051]    More preferably, an etch rate when patterning the metal layer is monitored by measuring a specific resistance of the metal sample.  
           [0052]    Preferably, the gate line and data line and metal samples include contact pads, wherein contact holes are formed at the contact pads of gate line and data line and metal samples and pad electrodes are formed on the pads with the same material as the pixel electrode.  
           [0053]    It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0054]    [0054]FIG. 1 illustrates a layout of a liquid crystal display using four masks according to the prior art;  
         [0055]    [0055]FIGS. 2A to  2 G illustrate cross-sectional views of a process along cutting lines I-I′, II-II′, and III-III′ in FIG. 1 according to the prior art;  
         [0056]    [0056]FIG. 3 illustrates a layout in accordance with the invention of metal samples for measuring an ashing rate arranged on a dummy area;  
         [0057]    [0057]FIG. 4 illustrates a magnified view of metal samples according to the present invention;  
         [0058]    [0058]FIG. 5 illustrates a layout of a unit cell of a liquid crystal display device formed in an active area according to the present invention;  
         [0059]    [0059]FIGS. 6A to  6 G illustrate cross-sectional views of an active area at various stages of processing according to the present invention taken along reference lines IV-IV′, V-V′, and VI-VI′ of FIG. 5; and  
         [0060]    [0060]FIGS. 7A to  7 G illustrate cross-sectional views of a process for forming metal samples in a dummy area according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0061]    Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts.  
         [0062]    [0062]FIG. 3 illustrates a layout of metal samples for measuring an ashing rate arranged on a dummy area and FIG. 4 illustrates a magnified view of the metal samples according to the present invention.  
         [0063]    In contrast to the prior art, a liquid crystal display, in accordance with the invention, includes a plurality of panels on a single substrate. A plurality of panels are simultaneously formed and then the mother substrate is cut into respective panels for a plurality of unit panels. Hence, a portion where each panel is formed is designated as an active area and a circumferential area of each of the active areas is referred to as a dummy area.  
         [0064]    Referring to FIG. 3, a liquid crystal display device according to the present invention includes a plurality of active areas  410  arranged on a mother substrate  400 . A plurality of metal samples  401  are arranged on a dummy area around each of the active areas  410 .  
         [0065]    Each of the metal samples  401 , illustrated in FIG. 4, includes an electrode portion  405  and pad portions  403  formed at both ends of the electrode portion  405 . As noted, the width of the electrode portions  405  differ from each other. Each of the electrode portions  405  have substantially the same length. In the illustrated embodiment, the electrode portions have a length of about 1 mm. Consequently, the widths of the electrode portions  405  differ from each other by at least about 1 μm. In accordance with the invention, the width difference can vary over a range of about 2 μm to about 12 μm. Each of the pad portions  403  has a pad electrode  404  formed thereon with a transparent conductive layer having the same shape as the pad, gate, or data line that will be formed in the active area  410 .  
         [0066]    In accordance with the invention, a plurality of the metal samples  401  having differing widths are formed simultaneously under the same processing conditions as that used to form the active areas  410 . After fabrication, the width and specific resistance of each metal sample  401  is measured and the data is used to design the device.  
         [0067]    A liquid crystal display device having metal samples formed in the active areas according to the present invention will now be described.  
         [0068]    Referring to FIG. 5, a liquid crystal display device fabricated by a  4  masks process according to the present invention includes a gate line  301  arranged in one direction gate electrode  301   a  and a data line  305   d  arranged in a direction perpendicular to the gate line  301 . A semiconductor layer  303  and a metal layer are stacked to form source/drain electrodes  305   a  and  305   b . A pixel area is defined by the gate lines  301  and the data lines  301  and  305   d.    
         [0069]    A pixel electrode  307   a  (shown in FIG. 6G) is formed in the pixel area, and a thin film transistor is formed at an intersection between the gate  301  and the data line  305   d . A contact hole  309   a  is formed at the drain electrode  305   b  (shown in FIGS. 6E and 6G) of the thin film transistor in order to connect the drain electrode  305   b  to the pixel electrode  307   a  electrically.  
         [0070]    A method of fabricating the above-constituted liquid crystal display device using the four masks according to the present invention will now be described.  
         [0071]    Referring to FIG. 6A and FIG. 7A, after a substrate  300  has been cleaned, a gate metal (shown in silhouette) is deposited on the substrate  300  by sputtering. A first photoresist layer is coated on the gate metal and exposed and developed to form a first photoresist pattern P/R 1  for forming a gate line. The gate metal is selectively removed using the first photoresist pattern to form a gate line  301  having a gate electrode  301   a  and a gate pad  301   b  in an active area. The photoresist pattern P/R 1  is then stripped.  
         [0072]    Referring to FIG. 6B and FIG. 7B, a gate insulating layer  302 , a semiconductor layer  303 , an ohmic contact layer  304 , and a low-resistance data metal layer  305  are sequentially formed over the entire surface of the active and dummy areas having the gate line  301  and pad  301   a  formed thereon. A second photoresist P/R 2  is then coated on the data metal layer  305 . In this case, the low-resistance data metal layer  305  is formed of Mo.  
         [0073]    Referring to FIG. 6C and FIG. 7C, a second photoresist pattern P/R 2  for a data line pattern and a second photoresist pattern P/R 2  for a metal sample pattern are formed in the active and dummy areas, respectively, by exposure and development using a second mask (half-tone mask). In this case, the second mask (half-tone mask) is formed to cut off light corresponding to the data line completely as well as transmit the light of a predetermined quantity to a portion corresponding to a channel area of a thin film transistor. Hence, the developed second photoresist pattern maintains its originally-deposited thickness on the data line and metal sample forming areas, but is formed relatively thin on the channel area of the thin film transistor. Subsequently, the low-resistance data metal layer  305 , ohmic contact layer  304 , and semiconductor layer  303  (except portions in the data line (including pad), thin film transistor, and metal sample forming areas) are removed by wet or dry etch using the second photoresist pattern P/R 2  as a mask. In this case, the metal sample  401 , as illustrated in FIG. 4, are formed to have differing line widths.  
         [0074]    Referring to FIG. 6D and FIG. 7D, an ashing process is carried out on the second photoresist pattern P/R 2  just to remove a portion of the second photoresist pattern corresponding to the channel area of the thin film transistor. In this case, the overall thickness of the second photoresist pattern is decreased as well as a width thereof. Hence, the widths of data line and source/drain electrodes that will be formed later will be reduced.  
         [0075]    Referring to FIGS. 6E and 7E, the low resistance data metal layer  305  and ohmic contact layer  304  corresponding to the channel area of the thin film transistor are etched using the ashed second photoresist pattern P/R 2 . The etching process forms a data line  305   d  including a data pad  305   c  in the active area, a thin film transistor including source and drain electrodes  305   a  and  305   b  in the active area, and a metal sample in the dummy area. The second photoresist pattern P/R 2  is then stripped. In the embodiment illustrated in FIG. 6E, the reference numeral ‘ 304   a ’ refers to the patterned ohmic contact layer.  
         [0076]    Referring to FIG. 6F and FIG. 7F, a passivation layer  306  is deposited over an entire surface of the substrate including the source electrodes  305   a , data line  305   d  having the drain electrode  305   b  and data pad  305   c , and metal sample  401 . A third photoresist layer is then coated on the passivation layer  306  and exposure and development are carried out using a third mask just to form a third photoresist pattern P/R 3 . The third photoresist pattern P/R 3  exposes a portion of the drain electrode  305   b , the gate pad  301   b , and the data pad  305   c  in the active area and a predetermined portion of a pad area  403  of the metal sample  401  in the dummy area. The passivation layer  306  is then selectively etched using the third photoresist pattern as a mask to form contact holes  309   a ,  309   b , and  309   c  on the drain electrode  305   b , gate pad  301   b , and data pad  305   c  in the active area, respectively. As illustrated in FIG. 7E, a contact hole  402  on the pad area  403  of the metal sample  401  in the dummy area is also formed. After completing the etching process, the third photoresist pattern P/R 3  is stripped.  
         [0077]    Referring to FIG. 6G and FIG. 7G, a transparent electrode (ITO)  307  is deposited on an entire surface and is connected to the drain electrode  305   b , gate pad  301   b , and data pad  305   c  through the contact holes  309   a ,  309   b , and  309   c , respectively. The transparent electrode  307  is also formed on the pad of the metal sample  401  through the contact hole  402  (shown in FIG. 7F). A fourth photoresist layer is coated on the transparent electrode  307 , and exposed and developed to form a fourth photoresist pattern P/R 4  for patterning a pixel electrode and each pad electrode. For purposes of illustration, the fourth photoresist pattern P/R 4  is shown only in FIG. 7G.  
         [0078]    A pixel electrode  307   a  is formed in the pixel area by selectively removing a portion of the transparent electrode using the fourth photoresist pattern as a mask, and simultaneously pad electrodes  310  and  404  are formed on the pads, respectively. The fourth photoresist pattern P/R 4  is then stripped.  
         [0079]    Thus, by the above-explained 4-masks process, a thin film transistor array and a metal sample are formed in the active and dummy areas, respectively. Further, a probe is connected to each pad of the metal samples  401  to measure the resistance of each corresponding metal sample  401 .  
         [0080]    When the data line is formed to have a width of about 1.5 μm, it is judged that the ashing process has been carried out normally if the metal sample having a width of 3 μm is removed by the ashing process. Hence, the uniformity of the ashing can be known if the metal sample is uniformly removed in each portion.  
         [0081]    Accordingly, the liquid crystal display device and fabricating method thereof according to the present invention have the following effects or advantages.  
         [0082]    First, when the data line and source/drain electrodes are formed, a width of the source/drain metal which is being etched can be measured using the sample that is formed simultaneously with the source/drain electrodes. Thus, the corresponding thickness can be checked precisely and used in the later design.  
         [0083]    Second, when the data line and source/drain electrodes are formed, a specific resistance of the source/drain metal that is being etched can be measured using the sample that is formed simultaneously with the source/drain electrodes. Thus, the corresponding specific resistance can be checked precisely and used in the later design.  
         [0084]    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention include those modifications and variations within the scope of the appended claims and their equivalents.