Abstract:
Disclosed are a capacitor for semiconductor devices capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. The capacitor for semiconductor memory devices according to the present invention includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline Ta x O y N z  layer, and the total of x, y, and z in the crystalline Ta x O y N z  layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device capable of increasing storage capacitance and preventing leakage current and method of manufacturing the same.  
         BACKGROUND OF THE INVENTION  
         [0002]    Along with the recent progress in the semiconductor manufacturing technology, the demand for memory device has increased dramatically. Consequently, a memory device having higher capacitance per small dimension is required. Capacitance of the capacitor is increased by using an insulator having high dielectric constant or enlarging the surface area of a lower electrode. Those conventional capacitors have been made with tantalum-oxide (Ta 2 O 5 ) layer having a dielectric constant higher than that of nitride-oxide (NO) layer, thereby forming the lower electrode having 3-Dimensional structure.  
           [0003]    [0003]FIG. 1 is a cross-sectional view of a capacitor in a conventional semiconductor memory device. Referring to FIG. 1, a field oxide layer  11  is also formed at a predetermined portion of the substrate  10 . A gate electrode  13  including a gate insulating layer  12  at a lower portion thereof is formed by a known technique at a predetermined portion of a semiconductor substrate  10 . A junction region  14  is formed on the semiconductor substrate  10  at each end of the gate electrode  13 , thereby forming a MOS transistor. A first interlevel insulating layer  16  and a second interlevel insulating layer  18  are formed on the semiconductor substrate  10 . A storage-node contact hole h is formed in the first and the second interlevel insulating layers  16 ,  18  so that the junction region  14  is exposed. A cylinder type lower electrode  20  is formed by a known technology with in the storage-node contact hole h to contact the exposed junction region  14 . A HSG (hemi-spherical grain) layer  21  is formed on a surface of the lower electrode  20  in order to increase the surface area of the lower substrate  20 . A Ta 2 O 5  layer  23  is formed on the surface of the HSG layer  21 . At this time, the Ta 2 O 5  layer  23  is formed as follows. First, a surface of the HSG layer  21  is cleaned before the Ta 2 O 5  layer  23  is formed, and then the RTN (rapid thermal nitridation) process is performed ex situ thereby forming a silicon-nitride layer  22  on the HSG layer  21 . Next, a first Ta 2 O 5  layer is formed at temperature of approximately 400-450° C. with thickness of 53-57 Å. Afterward, an annealing process is performed at low temperature, and then there is formed a second Ta 2 O 5  layer with the same thickness and by the same process as in the first Ta 2 O 5  layer. Annealing processes at low temperature and at high temperature are continued in series thereby forming a single Ta 2 O 5  layer  23 . An upper electrode  24  is deposited on upper portions of the Ta 2 O 5  layer  23  and the second interlevel insulating layer  18 , thereby completing the formation of a capacitor.  
           [0004]    However, the conventional capacitor according to the above method using the Ta 2 O 5  layer as a dielectric layer has the following problems.  
           [0005]    First, a difference in the composition rate of Ta and O results since Ta 2   0   5  generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms, are generated in the Ta 2 O 5  layer. Since those vacancy atoms are oxygen vacancy, leakage current result. The amount of vacancy atoms in the dielectric layer can be controlled depending on the contents and the bond strength of components in the Ta 2 O 5  layer; however, it is difficult to eliminate them completely.  
           [0006]    in order to stabilize the unstable stoichiometry of Ta 2 O 5 , the Ta 2 O 5  layer is oxidized so as to remove the substitutional Ta atoms in the Ta 2 O 5  layer. However, when the layer is oxidized, an oxide layer having low dielectric constant is formed at an interface between the Ta 2 O 5  layer and the lower electrode or the Ta 2 O 5  layer and the upper electrode since Ta 2 O 5  easily oxidizes with the lower and the upper electrode made of polysilicon or TiN., thereby degrading the homogeneity of the interface.  
           [0007]    Further, due to the reaction between an organic substance such as Ta(OC 2 H 5 ) 5  used as a precursor and O 2  (or N 2 O) gas as a reaction gas, impurities result, such as carbon atoms C, carbon compounds(CH 4 , C 2 H 4 ) and H 2 O in the Ta 2 O 5  layer. These impurities increase leakage current in the capacitor and degrade the dielectric characteristics of the Ta 2 O 5  layer. Accordingly, a capacitor having a large capacitance is difficult to obtain.  
           [0008]    Moreover, the use of the Ta 2 O 5  layer as a dielectric layer generates extra ex-situ steps, one before formation of Ta 2 O 5  layer and one after the cleaning step. Also, two thermal processes, at low and high temperatures, preferably is performed after the Ta 2 O 5  layer has been formed. Therefore, forming a dielectric layer with Ta 2 O 5  using the conventional method is cumbersome.  
         SUMMARY OF THE INVENTION  
         [0009]    Accordingly, it is one object of the present invention to provide a capacitor for semiconductor device capable of obtaining a great capacitance by providing a dielectric layer having low leakage current and high dielectric constant.  
           [0010]    Furthermore, the other object of the present invention is to provide a method of manufacturing capacitor for semiconductor device capable of simplifying its manufacturing process.  
           [0011]    According to one aspect of the present invention, a capacitor for semiconductor memory device includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline Ta x O y N z  layer, and the total of x, y, and z in the crystalline Ta x O y N z  layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.  
           [0012]    In another aspect of the present invention, a method of manufacturing a capacitor on a semiconductor substrate includes the steps of: forming a lower electrode on the semiconductor substrate; depositing an amorphous Ta x O y N 2  layer as a dielectric layer on the lower electrode; crystallizing the amorphous Ta x O y N z  layer; and forming an upper electrode on the crystalline Ta x O y N z  layer, wherein the total of x, y and z in the Ta x O y N z  layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.  
           [0013]    Still other aspect of the present invention, a method of manufacturing a capacitor on a semiconductor substrate includes the steps of: forming a lower electrode on the semiconductor substrate; surface-treating to prevent a natural oxide layer generation on the surface of the lower electrode; depositing an amorphous Ta x O y N z  layer as a dielectric layer on the lower electrode; crystallizing the amorphous Ta x O y N z  layer; and forming an upper electrode on the crystalline Ta x O y N z  layer, wherein the total of x, y and z in the Ta x O y N z  layer is 1, y is 0.3 to 0.5, and z is 0.1 to 0.3, and the amorphous Ta x O y N z  layer is obtained by supplying Ta chemical vapor obtained from a precursor, O 2  gas and NH 3  gas with pressure of 0.1 to 100 Torr at temperature of 300 to 600° C. in an LPCVD chamber and by a surface chemical reaction thereof.  
           [0014]    Herein, O 2  gas is supplied by 50 to 150 sccm and NH 3  is supplied by 30 to 70 sccm. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]    [0015]FIG. 1 is a cross-sectional view for showing a conventional capacitor on a semiconductor device.  
         [0016]    [0016]FIGS. 2A to  2 C are cross-sectional views for illustrating a capacitor for a semiconductor device according to the embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0017]    Referring to FIG. 2A, a field oxide layer  31  is formed on a selected portion of a semiconductor substrate  30  having a selected conductivity by a known method. A gate electrode  33  having a gate insulating layer  32  at a lower portion thereof is formed on a selected portion of the semiconductor substrate  30 , and a spacer  34  is formed at both side-walls of the gate electrode  33  by a known method. A junction region  35  is formed on the semiconductor substrate  30  of both sides of the gate electrode  33 , thereby forming a MOS transistor. A first interlevel insulating layer  36  and a second interlevel layer  38  are formed on the semiconductor substrate  30  in which the MOS transistor is formed. Afterward, the second and the first interlevel insulating layers  38 , 36  are patterned to expose a selected portion of the junction region  35 , thereby forming a storage node contact hole H. A lower electrode  40  is formed to be in contact with the exposed junction region  35 . At this time, the lower electrode of the present embodiment is formed as one of the various types such as stack, cylinder. A HSG layer  41  is formed on the lower electrode  40  by a known method so that the surface area of the lower electrode  40  is increased. Afterwards, the lower electrode  40  and the second interlevel insulating layer  38  are cleaned using HF vapor, HF solution or a compound containing HF to prevent the generation of a low dielectric natural oxide layer at the surface of the HSG layer  41 , i.e. the interface between the lower electrode  40  including the HSG layer  41  and a dielectric layer(not illustrated) which will be formed later. The cleaning step may be performed h in situ or ex situ. Furthermore, the surface of the HSG layer  41  can be interface-treated by NH 4 OH solution or H 2 SO 4  solution to more improve the interfacial homogeneity before or after cleaning the low dielectric natural oxide layer.  
         [0018]    Referring to FIG. 2B, as a dielectric, an amorphous Ta x O y N z  layer  43  is formed in situ or ex situ at an upper portion of the surface-treated lower electrode  40  with thickness of 50 to 150 Å. Here, the total of x, y, and z in the amorphous Ta x O y N z  layer  43  is 1, y is 0.3 to 0.5, preferably 0.4, and z is 0.1 to 0.3, preferably 0.2. The amorphous Ta x O y N z  layer  43  is formed by a chemical reaction of Ta chemical vapor obtained from a precursor, O 2  gas and NH 3  gas in a low pressure chemical vapor deposition (LPCVD) chamber. Here, when depositing the Ta x O y N z  layer  43 , a chemical reaction is occurred only on the wafer surface under a condition that a gas phase reaction within a chamber is extremely restrained to minimize particle generation in the inside thereof. At this time, it is desirable that the temperature in the LPCVD chamber is 300 to 600° C. with pressure of 0.1 to 10 Torr. And, an organic metal containing tantalum, for example Ta(OC 2 H 5 ) 5  (tantalum ethylate), and Ta(N(CH 3 ) 2 ) 5  (penta-dimethyl-amino-tantalum), is used as the precursor. Here, the precursor such as Ta(OC 2 H 5 ) 5 , and Ta(N(CH 3 ) 2 ) 5  is in liquid state, as known in the art, so the precursor is preferably supplied in the LPCVD chamber after it has been converted to vapor state. That is, a selected amount of the precursor in liquid state is flowed using a flow controller such as MFC (mass flow controller) and then evaporated in an evaporizer or evaporation tube including an orifice or nozzle, thereby generating a Ta chemical vapor. At this time, the precursor is preferably supplied into the evaporizer or the evaporation tube at a rate of 100 to 200 mg/min. And, the temperature of the evaporizer and a conduit coupled to the chamber, a flow path of the Ta vapor is maintained preferably at temperature of 150-200° C. to prevent condensation of the Ta chemical vapor. In addition, O 2  gas is injected by 50-150 sccm to satisfy y as to 0.3-0.5, and NH 3  gas is injected by 30-70 sccm to satisfy z as to 0.1-0.3.  
         [0019]    Afterward, as shown in FIG. 2C, the amorphous Ta x O y N 2  layer  43  is crystallized by an annealing step for obtaining further stable state. At this time, the crystallizing step is performed as an RTP in situ or ex situ in a chamber of N 2 O or O 2  atmosphere with temperature of 600-950° C. for 30 seconds-10 minutes. According to this crystallizing step, the amorphous Ta x O y N z  layer  43  becomes a crystalline Ta x O y N z  layer  43   a  and then impurities therein are removed, thereby improving dielectric constant of the Ta x O y N z  layer  43   a . And, the amorphous Ta x O y N z  layer  43  can be crystallized in a furnace having N 2 O, O 2  or N 2  gas atmosphere at temperature of 600-950° C. Moreover, the crystallizing step can be performed by the RTP or in a furnace under nitrogen containing gas, for example NH 3 , N 2  or N 2 /H 2  gas atmosphere and at temperature of 600-950° C. At this time, when an annealing step is performed under nitrogen atmosphere, the amorphous Ta x O y N z  layer  43  is crystallized and impurities therein are all diffused. As a result, a reaction between an upper electrode and the Ta x O y N z  layer  43   a  is prevented due to the surface nitrification. Afterward, a conduction barrier  44  is formed on an upper portion of the crystallized Ta x O y N z  layer  43   a  and is formed of a TiN layer. The upper electrode  45  is formed of a doped polysilicon layer and is formed on an upper portion of the conduction barrier layer  44 .  
         [0020]    Furthermore, the surface treatment of a lower electrode before depositing an amorphous Ta x O y N z  layer, can be replaced with a plasma NH 3  gas annealing process or the RTN process.  
         [0021]    As described above, advantages using Ta x O y N 2  layer (x+y+z=1, 0.3□y□0.5, 0.1□z□0.3) as a dielectric are as follows.  
         [0022]    Since the Ta x O y N z  layer has a high dielectric constant of 25-30 and a stable Ta—O—N structure, also the dielectric property thereof is superior to that of the NO layer. Moreover, the Ta x O y N z  layer has more stable stoichiometry than that of the Ta 2 O 5  layer. Therefore, the Ta x O y N z  layer  43  has a superior tolerance against external electric impacts and high breakdown voltage and very low leakage current.  
         [0023]    In addition, since the substitutional Ta atoms as existing in the Ta x O y N z  layer are not exist inside the Ta x O y N 2  layer, an extra oxidation process may be omitted. Moreover, since the Ta x O y N z  layer has very low oxidation reactivity, oxidation with the lower electrodes  40 , 41  and the upper electrode  44  of the capacitor hardly occurs. Therefore, the thickness of the equivalent dielectric layer can be controlled to less than 30 Åthin.  
         [0024]    And, impurities in the Ta x O y N z  layer are removed and crystallized by performing a thermal process after forming the Ta x O y N z  layer. Therefore, the dielectric constant of the Ta x O y N z  layer is increased and leakage current thereof is decreased.  
         [0025]    In the aspect of manufacturing method, the Ta x O y N 2  layer in the present embodiment is formed in a single layer, and then an annealing step for out-diffusing impurities is once performed after the Ta x O y N z  layer is deposited. Consequently, the manufacturing process of this embodiment is simpler than that of the conventional tantalum oxide layer.  
         [0026]    Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of the present invention.