Abstract:
An architecture for oversampled delta-sigma (Δ--Σ) analog-to-digital (A/D) conversion of high-frequency, narrow-band signals includes multistage Δ--Σ modulators that incorporate band-reject noise shaping centered at an arbitrary center frequency F bp . These modulators cascaded with a bandpass digital filter centered at the arbitrary center frequency F bp  perform A/D conversion for high-frequency, narrow-band signals having the same arbitrary frequency. The bandpass modulators are implemented by use of resonators which provide a substantially large gain at the arbitrary frequency.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates in general to analog-to-digital (A/D) converters and, more particularly, to a new architecture for oversampled delta-sigma (Δ--Σ) A/D conversion of high frequency, narrow band signals using cascaded low order stages with an arbitrary center frequency to obtain high overall order of noise shaping. 
     Single-loop bandpass delta-sigma (Δ--Σ) modulation is described by R. Schreier and M. Snelgrove in &#34;Bandpass Sigma Delta Modulation,&#34; Electronics Letters, Vol. 25, Nov. 9, 1989, pp. 1560-1561. Z. X. Zhang, G. C. Temes and Z. Czamul in &#34;Bandpass ΔΣ A/D Converter Using Two-Path Multibit Structure&#34;, Electronics Letters, Vol. 27, Oct. 24, 1991, pp. 2008-2009, citing Schreier et al., supra, describe a modification of the basic structure using N-path switched capacitor circuits. Subsequently, R. Schreier, G. C. Temes, A. G. Yesilyurt, Z. X. Zhang, Z. Czarnul, and A. Hairapetian in &#34;Multibit Bandpass Delta-Sigma Modulators Using N-Path Structures&#34;, IEEE International Symposium on Circuits and Systems, May 1992, pp. 593-596, describe simulation results of two switched-capacitor circuits for use in a multi-bit bandpass sigma-delta modulator. 
     Typically, cascaded low-order delta-sigma stages have been used to implement higher order delta-sigma modulators for A/D conversion of low-pass signals. See, for example, D. B. Ribner, &#34;A Comparison of Modulator Networks for High-Order Oversampled Sigma-Delta Analog-to-Digital Converters,&#34; IEEE Trans. Circuits and Systems, Vol. CAS-38, No. 2, pp. 145-159, Feb. 1991. Those cascades comprise combinations of first and second-order individual stages and thereby avoid the stability problem prone to single-loop modulators of third-order and higher. See also D. B. Ribner U.S. Pat. Nos. 5,084,702, 5,103,229, and 5,148,166, all assigned to the present assignee, for further background on plural-order sigma-delta analog-to-digital converters. U.S. Pat. Nos. 5,084,702, 5,103,229 and 5,148,166 are hereby incorporated by reference. 
     U.S. Pat. No. 5,283,578, issued Feb. 1, 1994, by D. B. Ribner and D. H. K. Hoe, assigned to the present assignee and herein incorporated by reference, provides an architecture for multistage delta-sigma (Δ--Σ) bandpass modulators that provide band-reject noise shaping at one fourth the sampling frequency F s . Although the foregoing multistage architecture, advantageously overcomes many of the problems of previous single stage high order architectures, such as stability, component spread and design complexity, the center frequency of the bandpass modulators therein is limited to one fourth of the sampling frequency F s . 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a new architecture for oversampled delta-sigma (Δ--Σ) analog-to-digital (A/D) conversion of high-frequency, narrow-band signals which is not limited to a single center frequency. 
     Briefly, in accordance with a preferred embodiment of the invention, an architecture for multistage delta-sigma (Δ--Σ) bandpass modulators having an arbitrary bandpass frequency F bp  situated below at least one half of the sampling frequency Fs is provided. The bandpass modulators of the present invention may be implemented with a resonator having z domain transfer function ##EQU1## which when cascaded with a bandpass digital filter centered at the arbitrary center frequency F bp  can perform A/D conversion for high-frequency, narrow-band signals centered at the same arbitrary frequency. In the above equations, z is the discrete time frequency variable. As used herein θ is an arbitrary phase angle defined by 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of the invention with reference to the accompanying drawings where like numerals represent like elements and in which: 
     FIGS. 1 and 2 are block diagrams of respective architectures for band-pass multistage Δ--Σ A/D converters which operator a single center frequency; 
     FIG. 3 is a functional block diagram of the discrete time resonator employed in the present invention; 
     FIG. 4 is a block diagram of one stage of a band-pass Δ--Σ A/D converter in accordance with the present invention; 
     FIG. 5A is a block diagram in a modulation stage of a resonator employing integrators according to one aspect of the invention, and FIG. 5B is a schematic diagram of a switched-capacitor implementation of the circuitry of FIG. 5A; 
     FIG. 6A is a block diagram in modulation stage of a resonator employing integrators according to another aspect of the invention, and FIG. 6B is a schematic diagram of a switched-capacitor implementation of the circuitry of FIG. 6A; and 
     FIGS. 7 and 8 are block diagrams of a multistage Δ--Σ A-D converter implemented in accordance with the teachings of the present invention and based on the architectures shown in FIGS. 1 and 2, respectively. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1 and 2 illustrate examples of band-pass modulators having a center frequency limited to one fourth of the sampling frequency F s . More particularly, FIG. 1 illustrates a Multiple Second-Order Cascade (MSOC) modulator that is capable of cosinusoidal noise shaping of order 2N so as to suppress quantization noise about the aforementioned center frequency. The MSOC modulator generates a sampled-data digital response y(nT) to a sampled-data input voltage x(nT), which response is supplied to a decimation filter (not shown) that provides the ultimate analog-to-digital (A/D) conversion result. The MSOC modulator is illustrated as having N stages, although such modulator typically is implemented with no more than three stages since mismatches and low gain cause leakage of lower order quantization noise to the output and thereby limit performance. 
     Stage 1, the first Δ--Σ stage 10, includes a two-input adder 11 to which the analog sampled-data input voltage x(nT) is supplied as an input signal to a first input of adder 11. Adder 11 is also supplied with a first analog feedback signal as the input signal to its second input. The resulting combined output signal from adder 11 constitutes a first error signal, which is scaled in a scaling element 12 by a scaling coefficient k 1  and then processed by a first resonator 13 to generate a resonator output voltage I 1 . Specifically, as disclosed in U.S. Pat. No. 5,283,578, the resonator transfer function ##EQU3## provides an infinite gain at a frequency F s  /4 which allows the Δ--Σ modulator stage to have a center frequency corresponding to F s  /4. Integrator output voltage I 1  is digitized in an A/D converter 14 to generate, for the first Δ--Σ modulator stage 10, a digital output signal V 1  that corresponds to the sampled-data input signal x(nT). A digital-to-analog (D/A) converter 15 converts the A/D converter 14 output voltage V 1  into the aforementioned first analog feedback signal which is supplied to adder 11 as the input signal at its second input for completing the first feedback loop. The first analog feedback signal voltage from D/A converter 15 is also supplied to a first input of another two-input adder 16. Adder 16 receives at its second input the resonator output signal I 1  scaled by a scaling coefficient h 1  in a scaling element 17. Adder 16 generates a combined signal -Q 1  that corresponds to the negative of the quantization noise of the first Δ--Σ modulator stage 10 and, after scaling by a scaling coefficient j 1  of a scaling element 18, is used as an input signal for the second Δ--Σ modulator stage which, in the illustration, is ith Δ--Σ modulator stage 20. 
     The ith Δ--Σ modulator stage 20 includes a two-input adder 21 receiving at its first input, the scaled negative quantization noise of a preceding (i-1)th Δ--Σ modulator stage which, in the embodiment illustrated, is the first Δ--Σ modulator stage 10. Adder 21 is supplied with the analog feedback signal of the ith Δ--Σ modulator stage 20 as the input signal to its second input. The resulting combined output signal from adder 21 is the ith error signal, which is scaled in a scaling element 22 by a scaling coefficient k i  and then processed by a resonator 23 to generate ith resonator output signal I i . The resonator output signal I i  is digitized in an A/D converter 24 to generate a digital output signal V i  that corresponds to the negative of the scaled quantization noise of the preceding Δ--Σ modulator stage which, in the embodiment illustrated, is the first Δ--Σ modulator stage 10. A D/A converter 25 converts the A/D converter 24 output signal V i  to an analog signal constituting the ith analog feedback signal supplied to adder 21 at its second input, completing the ith feedback loop. The ith analog feedback signal is also supplied to another two-input adder 26 at its first input. Adder 26 receives at its second input the ith integrator output signal I i  scaled by a scaling element 27 with scaling coefficient h i . Adder 26 generates a combined signal -Q i  that corresponds to the negative of the quantization noise of the ith Δ--Σ modulator stage 20 and, after scaling by a scaling element 28 with scaling coefficient j i , is used as an input signal voltage for the (i+1)th Δ--Σ modulator stage or, in the embodiment illustrated, Nth Δ --Σ modulator stage 30. 
     The Nth Δ--Σ modulator stage 30 includes a two-input adder 31 receiving at its first input, the negative of the scaled quantization noise of the preceding (N-1)th modulator stage or, in the embodiment illustrated, the ith Δ--Σ modulator stage 20. Adder 31 is supplied with the analog feedback signal of the Nth Δ--Σ modulator stage 30 at its second input. The resulting combined output signal from adder 31 is the Nth error signal, which is scaled in a scaling element 32 by a scaling coefficient k N  and then processed by a resonator 33 to generate Nth resonator output signal I N . The resonator output signal I N  is digitized in an A/D converter 34 to generate a digital output signal V N  that corresponds to the negative of the scaled quantization noise of the preceding Δ--Σ modulator or, in the embodiment illustrated, the ith Δ--Σ modulator 20. A D/A converter 35 converts the A/D converter 34 output signal V N  to an analog signal as the Nth analog feedback signal which is supplied to adder 31 at its second input completing the Nth feedback loop. 
     The output signals of the ith and Nth Δ--Σ modulator stages 20 and 30 are scaled by multipliers 41 and 42, respectively, with scaling coefficients g i-1  and g N-1 , respectively. The V 1  output signal of the first Δ--Σ modulator stage 10 is delayed by a delay element 43 to compensate for the delay in the V N  output signal of the Nth Δ--Σ modulator stage 30. The V i  output signal of the ith Δ--Σ modulator stage 20 is likewise delayed and additionally digitally filtered in a delay and cosine filter 44. Finally, the V N  output signal of the Nth Δ--Σ modulator 30 is filtered in a cosine filter element 45. The output signals of elements 43, 44 and 45 are combined by a digital adder 46 to generate the digital output signal y(nT). 
     The type of Δ--Σ MSOC modulator shown in FIG. 1 uses the difference between A/D and D/A signals of each stage as the input signal to the following stage and is termed a quantization cascaded modulator, designated MSOC1. The scaling coefficients g i , h i , j i , and k i , where i=1 . . . N for this and the following prior art modulators of FIG. 2, are discussed in the Ribner paper, supra. In FIG. 1, however, ##EQU4## for stage i, and ##EQU5## for stage N, while h i  =1/k i  for stage i, (where i=1 . . . N), where k 1  through k N  are arbitrary coefficients, typically equal to or less than unity. For example, such k coefficients are typically equal to unity if respective multi-bit A/D and D/A converters are used. However, it is generally preferred to use respective one-bit A/D and D/A converters so as to obtain superior linearity in any given modulation stage, and in this case such k coefficients are usually less than unity without affecting the transfer function of any individual modulation stage. Similarly, j 1  through j N-1  are also arbitrary and typically equal to unity. These coefficients are used for signal scaling. 
     FIG. 2 shows a Multiple Second Order Cascade modulator, designated MSOC2, which differs from the MSOC1 modulator shown in FIG. 1 in that the resonator output signal of a stage is taken directly as the input signal to the following stage; this is termed a resonator cascaded modulator. Again, practical implementations have been limited to three stages or less due to matching and finite gain constraints. In FIG. 2, ##EQU6## for stage i ##EQU7## for stage N, and k 1  through k N   are arbitrary coefficients and typically equal to or less than unity, while j 1  through j N-1  are also arbitrary and typically equal to unity, as discussed in the context of FIG. 1. 
     The multistage modulators shown in FIGS. 1 and 2 use digital networks to combine the individual output signals from the multiple stages into a single output signal that is supplied to the input of a subsequent digital decimation filter (not shown). In each case, the resulting output signal from any of these modulators is of the form 
     
         Y(z)=z.sup.-2N X(z)+g.sub.N-1 (1+z.sup.-2).sup.N Q.sub.N (z) (2) 
    
     for MSOC1 and MSOC2, where Q N  is the quantization noise of stage N. 
     Bandpass modulators of the present invention may be implemented by utilizing a resonator 200, as shown in FIG. 3, instead of the resonator of the type shown in FIGS. 1 and 2. Specifically, instead of employing the z domain transfer function ##EQU8## the following resonator transfer function ##EQU9## is employed. The transfer function of Eq. 4 differs from the transfer function of Eq. 3 in that the pair of complex conjugate poles at z=e.sup.±jπ /2 is advantageously transformed to a pair of complex conjugate poles at z=e.sup.±jθ. Thus the original resonator with infinite DC gain at a single frequency of F s  /4 is replaced by a resonator with infinite gain at an arbitrary frequency F bp , preferably situated at least one half below the sampling frequency F s  in order to satisfy the Nyquist sampling rate requirement. As used herein θ=2πF bp  /F s . 
     The above transformation may be illustrated by the modulation stage representation of FIG. 4. Specifically, a Δ--Σ modulator stage 100 which has an arbitrary center frequency F bp  can be implemented when the input signal, e.g., x(nT), is supplied to an input delay unit 202 to generate a delayed analog input signal. A two-input adder 204 whose output is coupled to resonator 200 receives the delayed analog input signal at its first input and a suitable feedback analog signal at its second input. Resonator 200 as illustrated in FIG. 4, includes a scaling coefficient k 1 , usually less than unity, without affecting the overall characteristics of resonator 200 illustrated in FIG. 3 with scaling equal to unity. The feedback signal supplied to adder 204 is generated in feedback generator 206, as will be explained shortly hereafter, in response to the output signal of D/A converter 15 which is coupled to A/D converter 14 and which in turn receives the output signal of resonator 200. 
     One modulation stage 100&#39; implementation using a resonator constructed with basic integrating units in accordance with one aspect of the invention is illustrated in FIG. 5A. In particular, resonator 200&#39; includes an analog subtracter 210 which receives a minuend input analog signal and a feedback subtrahend signal for producing a difference output signal. An integrator 212 receives the difference output signal to generate a first integrated output signal in response thereto. A delayed integrator 214 delays and integrates the first integrated output signal to generate a second integrated output signal in response thereto. The second integrated output signal is the output signal of resonator 200&#39;. For the embodiments shown in FIGS. 4 and 5A the k scaling coefficients can be conveniently selected such that h 1  =1/k 1  (FIG. 4) or h 1  =1/k la  k lb  (FIG. 5). In each case, as suggested in the context of FIGS. 1 and 2, such k coefficients cooperate to provide an overall scaling coefficient which can be equal to or less than unity depending on the particular modulation stage design. In contrast, the following coefficients are specifically chosen such that a 1  =-k 1  2Cosθ; a 2  =k 1  ; and b 1  =2(1-Cos θ) so as to provide suitable scaling regardless of the value of the arbitrary bandpass frequency at which the Δ--93 modulator stage is operated. Further, it will be appreciated from FIGS. 4 and 5A that feedback generator 206 comprises, by way of example and not of limitation,both a scaling unit and a delay unit which cooperate to generate the analog feedback signal supplied to the second input of adder 204. 
     A practical implementation for the modulation stage of FIG. 5A employs switched capacitor (SC) integrators, as shown in FIG. 5B. In particular, the analog sampled-data input voltage, e.g., x(nT), is supplied to one pole of a single-pole, double throw (SPDT) sampling switch 110. This switch in practice is implemented with semiconductor switching devices but, for simplicity of illustration, is shown as a mechanical switch. The analog sampled-data input voltage x(nT) is supplied by switch 110 to a capacitor 111 having a capacitance value g 1  C 1  to charge capacitor 111 to the input voltage level during a first switching period when the other side of capacitor 111 is connected by SPDT switch 112 to ground. Also during the first switching period, switch 112 connects a capacitor 113 to ground. Switch 112, like switch 110 or any of the switches illustrated in FIG. 5B, is preferably implemented with a suitable semiconductor switching device. During a second switching period, switches 110 and 112 reverse the positions shown in FIG. 5B so that the respective electrical charges in capacitors 111 and 113 are summed and applied to the inverting input of an operational amplifier 114. Operational amplifier 114 is configured as an integrator with a feedback capacitor 115 having a capacitance value C 1  coupled between its output and its inverting input. The output signal of operational amplifier 114 is supplied to one pole of a SPDT sampling switch 116. The integrated output voltage of operational amplifier 115 is supplied by switch 116 to a capacitor 117 having a capacitance value  g5  C.sub. 2 to charge capacitor 117 to the integrated output voltage during the first switching period when the other side of capacitor 117 is connected by a SPDT switch 118 to ground. During the second switching period, switches 116 and 118 reverse the positions shown in FIG. 5B so that the electrical charge in capacitor 117 is applied to the inverting input of an operational-amplifier 119. Operational amplifier 119 is also configured as an integrator with a feedback capacitor 126 having a capacitance value C 2  coupled between its output and its inverting input. The output signal of operational amplifier 119 is supplied from an inverter 120 to one pole of a double-pole, double throw (DPDT) switch 121 which in the second switching period is connected to a capacitor 122 having a capacitance value  g2  C 1  to charge capacitor 122 to the input voltage level during the second switching period when the other side of capacitor 122 is connected by a SPDT switch 123 to ground. During the first switching period any electrical charge in capacitor 122 is supplied to the inverting terminal of operational amplifier 114 thus completing the feedback path internal to resonator 200&#39; as shown in FIG. 5A. The output signal of operational amplifier 119 is also supplied to A/D converter 14 and then to D/A converter 15 such that the output of D/A converter 14 is supplied to the other pole of switch 121. During the first switching period, any charge in a capacitor 124 having a capacitance value of  g3  C 1  is directly supplied to the inverting terminal of operational amplifier 114 thereby providing the scaled signal supplied by the scaling unit of feedback generator 206, as shown in FIG. 5A. During the first switching period, the output signal of D/A converter 15 also charges capacitor 113 when the other side of capacitor 113 is connected to ground. During the second switching period, the electrical charge in capacitor 113 is supplied to the inverting terminal of operational amplifier 114 thereby providing the signal corresponding to the delayed signal by the delay unit in feedback generator 206, as shown in FIG. 5A. The following capacitance ratios make the SC circuit implementation of FIG. 5B fully consistent with the embodiment of FIG. 5A 
     
         g1g5=k.sub.1 ; 
    
     
         g2g5=2(1-Cosθ); 
    
     
         g4g5=k.sub.1 ; and 
    
     
         g3g5=2k.sub.1 Cosθ 
    
     and wherein k 1  =k 1a  k lb . 
     Although FIG. 5B illustrates, by way of example and not of limitation, a single-ended circuit, a fully differential implementation capable of operating in a mode suitable for handling differential signals is generally preferred in actual practice due to its improved power supply noise immunity and rejection of even-order nonlinearities. An example of such fully differential implementation is described by D. B. Ribner, et al in &#34;A third-Order Multistage Sigma-Delta Modulator with Reduced Sensitivity to Nonlinearities&#34;, IEEE, Journal of Solid State Circuits, Vol. 26, No. 12, Dec., 1991, pp. 1764-1773, which is herein incorporated by reference. In a fully differential implementation, inverter 120 is simply implemented by reversal of the balanced signal path. 
     Another modulation stage 100&#34; implementation using a resonator constructed with basic integrating units in accordance with another aspect of the invention is illustrated in FIG. 6A. Like resonator 200&#39; of FIG. 5A, resonator 200&#34; includes an analog subtracter 210 which receives a minuend input analog signal and a feedback subtrahend signal for producing a difference output signal. An integrator 212 receives the difference output signal to generate a first integrated output signal in response thereto. Unlike resonator 200&#39; of FIG. 5A, resonator 200&#34; includes a two-input adder 218 for receiving the first integrated output signal as an input signal to its first input and for receiving at its second input a compensation signal for producing a combined output signal which is produced in a compensation signal generator 220 in response to the output signal from D/A converter 15. Delayed integrator 214 delays and integrates the combined output signal to generate a second integrated output signal in response thereto. The second integrated output signal is the output signal of resonator 200&#34;. For the embodiment shown in FIG. 6A the scaling coefficients can be selected such that h 1  =1/k la  k lb  ; a 1  =1-2Cosθ; a 2  =-2Cosθ and b 1  =2(1-Cosθ) so as to provide suitable scaling regardless of the value of the arbitrary bandpass frequency at which the Δ--Σ modulator stage is operated. It is noted that feedback generator 206 used in the embodiment of FIG. 6A comprises only a unit delay path whereas feedback generator 206 used in the embodiment of FIG. 5A comprises a combined path made up of a unit delay path and a nondelayed path. In each case, the overall response is consistent with a resonator as depicted in FIG. 3 which allows for implementation of delta-sigma (Δ--Σ) bandpass modulators having an arbitrary bandpass frequency F bp . 
     A practical implementation for the modulation stage of FIG. 6A employs switched capacitor (SC) integrators as shown in FIGS. 6B. In particular, the analog sampled-data input voltage (e.g., x(nT)) is supplied to one pole of a single-pole, double throw (SPDT) sampling switch 301. This switch in practice is implemented with semiconductor switching devices, but for simplicity of illustration, is shown as a mechanical switch. The analog sampled-data input voltage x(nT) is supplied by switch 301 to a capacitor 302 having a capacitance value  g1  C 1  to charge capacitor 302 to the input voltage level during a first switching period when the other side of capacitor 302 is connected by SPDT switch 303 to ground. Also during the first switching period, switch 303 connects a capacitor 305 having a capacitance value of  g3  C 1  to ground. Switch 303, like switch 110 or any of the switches illustrated in FIG. 6B, is preferably implemented with a suitable semiconductor switching device. During a second switching period, switches 301 and 303 reverse the positions shown in FIG. 6B so that the respective electrical charges on capacitors 302 and 305 are summed and applied to the inverting input of an operational amplifier 304. Operational amplifier 304 is configured as an integrator with a feedback capacitor 306 having a capacitance value C 1  coupled between its output and its inverting input. The output signal of operational amplifier 304 is supplied to one pole of a SPDT sampling switch 307. The integrated output voltage of operational amplifier 306 is supplied by switch 307 to a capacitor 308 having a capacitance value  g5  C 2  to charge capacitor 308 to the integrated output voltage level during the first switching period when the other side of capacitor 308 is connected by a SPDT switch 309 to ground. Also during the first switching period, switch 309 connects a capacitor 312 having a capacitance value of  g4  C 2  to ground. During a second switching period, switches 307 and 309 reverse the positions shown in FIG. 6B so that the respective electrical charges in capacitors 308 and 312 are summed and applied to the inverting input of an operational amplifier 310. Operational amplifier 310 is also configured as an integrator with a feedback capacitor 311 having a capacitance value C 2  coupled between its output and its inverting input. The output signal of operational amplifier 310 is supplied through an inverter 320 to one pole of a SPDT switch 313 which, in the second switching period, is connected to a capacitor 314 having a capacitance value  g2  C 1  to charge capacitor 314 to the input voltage level during the second switching period when the other side of capacitor 314 is connected by a SPDT switch 315 to ground. During the first switching period any electrical charge in capacitor 314 is supplied to the inverting terminal of operational amplifier 304, thus completing the feedback path internal to resonator 200&#34; as shown in FIG. 6A. The output signal of operational amplifier 310 is also supplied to A/D converter 14 and then to D/A converter 15. The analog output signal of D/A converter 15 is supplied to one pole of a SPDT switch 316. During the second switching period, any charge on capacitor 3 12 is supplied to the inverting terminal of operational amplifier 310, thereby providing the compensation signal supplied by compensation signal generator 220 shown in FIG. 6A. During the first switching period, the output signal of D/A converter 15 is also supplied to charge capacitor 305 when the other side of capacitor 305 is connected by switch 303 to ground. During the second switching period, the electrical charge on capacitor 305 is supplied to the inverting terminal of operational amplifier 304,thereby providing the sole delayed signal supplied by the unit delay in feedback generator 206 shown in FIG. 6A. The following capacitance ratios make the SC circuit implementation of FIG. 6B fully consistent with the embodiment of FIG. 6A: 
     
         g1g5=k.sub.1 ; 
    
     
         g2g5=2(1-Cosθ); 
    
     
         g3g5=k.sub.1 (1-2Cosθ); and 
    
     
         g4=-2k.sub.1 Cos θ 
    
     and wherein k 1  =k la  k lb . 
     Although FIG. 6B illustrates a single-ended circuit, a fully differential implementation is preferably in practice, as suggested in the discussion of FIG. 5B. 
     The new bandpass modulators of the invention, shown in FIGS. 7 and 8, are improvements over the prior art modulators of FIGS. 1 and 2, respectively. FIG. 7 shows a Multiple Second-Order Arbitrary Frequency Cascade modulator which is designated MSOAFC1 using an extension to the terminology introduced in the Ribner paper, supra, which is hereby incorporated by reference. The MSOAFC1 implementation uses quantization signals rather than resonator signals as input signals to successive stages, using the approach explained in the context of FIG. 1. The various g, h, j and k scaling coefficients in this modulator have the same values as the same respective coefficients in the modulator of FIG. 1. This modulator differs from the modulator of FIG. 1 in that it handles bandpass signals centered at an arbitrary frequency instead of bandpass signals at a single bandpass frequency and is therefore suitable for a wide array of applications. Comparing FIGS. 1 and 7, it will be noted that the bandpass modulator of FIG. 1 which has a bandpass limited to one fourth of the sampling frequency has been replaced with a bandpass modulator having an arbitrary center frequency and which may take the form of any of the embodiments shown in FIGS. 4 through 6. The V 1  output signal of the first stage 10&#39; is delayed by a delay element 43&#39; to compensate for the delay in the V N  output signal of the Nth Δ--Σ modulator stage 30&#39;. The V i  output signal of the ith Δ--Σ modulator stage 20&#39; is likewise delayed, and is additionally digitally filtered by a notch filter 44&#39; with z domain transfer function (1-2cosθ z   -2 ) i-1 . The V N  output signal of the Nth Δ--Σ modulator 30&#39; is filtered by a notch filter with transfer function (1-2 cosθ z   -1  +z -2 ) N-1  in filter element 45&#39;. 
     The Multiple Second-Order Arbitrary Frequency Cascade modulator designated MSOAFC2, shown in FIG. 8, employs integrator signal cascading using the approach explained in the context of FIG. 2. The various g, j and k scaling coefficients in the MSOAFC2 modulator of FIG. 8 have the same values as the same respective coefficients in the modulator of FIG. 2. Contrasting FIGS. 2 and 8, delay/cosine filter elements 44 of FIG. 2 have been replaced by delay/notch filter elements 44&#39; and cosine filter element 45 of FIG. 2 has been replaced by notch filter 45&#39; having the aforementioned transfer function. 
     The output equation for each of the new bandpass modulators is 
     
         Y(z)=z.sup.-2N x(z)+g.sub.N (1-2cosθ.sub.z.sup.-1 +z.sup.-2).sup.N Z.sub.N(Z).                                               (5) 
    
     The corresponding magnitude noise transfer functions for each of the new bandpass modulators is ##EQU10## 
     One of the motivations for using cascaded modulators is that stability is insured if each stage is of order two or lower. Therefore, the MSOAFC1 and MSOAFC2 modulators are unconditionally stable since they are comprised of second-order stages. This is a significant advantage over prior art single-loop bandpass implementations in R. Schreier and M. Snelgrove, supra. 
     As to performance of the invention using conventional one micron CMOS (complementary metal-oxide-semiconductor) technology, it is expected that 16-bit A/D conversion of signals centered at 2.5 MHz with 150 kHz bandwidth is feasible, as is 12-bit conversion of signals centered at 10 MHz with 1.25 MHz bandwidth. Conventional A/D conversion in one micron CMOS is capable of only 16-bit and 12-bit resolution up to 80 kHz and 1 MHz signal frequencies, respectively. 
     While the invention has been described in terms of several preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.