Abstract:
A method for manufacturing a semiconductor device is provided, which comprises forming a first metal wiring layer above a semiconductor substrate, forming an inorganic insulating film above the first metal wiring layer, forming an organic insulating film on the inorganic insulating film, forming a recess in the organic insulating film, forming a reactive layer on the side surface of the recess, the reactive layer being capable of reaction under heat with the organic insulating film, applying a heat treatment to the reactive layer so as to permit the reactive layer to react with the organic insulating film while leaving an unreacted reactive layer, thereby allowing the reaction layer to grow on the side surface of the recess, the recess being diminished by the growth of the reaction layer, and removing the unreacted reactive layer to obtain a diminished recess.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-180728, filed Jun. 21, 2005, the entire contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a method for manufacturing a semiconductor device, particularly, to a method for manufacturing a semiconductor device having a dual damascene wiring structure using an interlayer insulating film which has a low dielectric constant and is formed of an organic insulating film.  
         [0004]     2. Description of the Related Art  
         [0005]     Miniaturization of a metal wiring is being promoted in an attempt to comply with the demands for the further improvement in the switching speed of a semiconductor device. In addition, miniaturization of the via hole for connecting the adjacent metal wiring layers and the lowering in the dielectric constant of the interlayer insulating film are said to be critical for further improving the switching speed of the semiconductor device.  
         [0006]     However, the size that can be obtained by the processing is limited if the processing size is to be miniaturized by simply improving the capability of the lithography technology employed for forming a trench in which the metal wiring is to be buried and for forming a via hole for connecting the adjacent metal wiring layers. In such the situation, the processing with a desired small size is being made difficult. It should also be noted that a hybrid structure including an organic insulating film and an inorganic insulating film is employed as an insulating film formed between the adjacent metal wiring layers, and a laminate structure is employed in the hard mask that is used for performing the dry etching. In addition, a cap insulating film is formed on the metal wiring layer and on the insulating film having a low dielectric constant. As a result, the construction of semiconductor device is made more complex. Under the circumstances, the nonuniformity of the size caused by the fluctuation of the etching rate has come to be attracted attention as a problem to be solved in applying a dry etching to various insulating films.  
       BRIEF SUMMARY OF THE INVENTION  
       [0007]     A method for manufacturing a semiconductor device according to one aspect of the present invention comprises forming a first metal wiring layer above a semiconductor substrate; forming an inorganic insulating film above the first metal wiring layer; forming an organic insulating film on the inorganic insulating film; forming a recess in the organic insulating film; forming a reactive layer on a side surface of the recess, the reactive layer being capable of reaction under heat with the organic insulating film; applying a heat treatment to the reactive layer so as to permit the reactive layer to react with the organic insulating film while leaving an unreacted reactive layer, thereby allowing the reaction layer to grow on the side surface of the recess, the recess being diminished by the growth of the reaction layer; and removing the unreacted reactive layer to obtain a diminished recess.  
         [0008]     A method for manufacturing a semiconductor device according to another aspect of the present invention comprises forming a first metal wiring layer above a semiconductor substrate; forming an inorganic insulating film above the first metal wiring layer; forming an organic insulating film on the inorganic insulating film; forming a via pattern as a recess in the organic insulating film; forming a reactive layer on a side surface of the via pattern, the reactive layer being capable of reaction under heat with the organic insulating film; applying a heat treatment to the reactive layer so as to permit the reactive layer to perform a reaction with the organic insulating film while leaving an unreacted reactive layer, thereby allowing a reaction layer to grow on the side surface of the via pattern, the via pattern being diminished by the growth of the reaction layer; removing the unreacted reactive layer to obtain a diminished via pattern; transferring the diminished via pattern formed in the organic insulating film into the inorganic insulating film so as to expose the first metal wiring, thereby forming the via hole; and forming a wiring trench in the organic insulating film to remove the reaction layer.  
         [0009]     A method for manufacturing a semiconductor device according to another aspect of the present invention comprises forming a first metal wiring layer above a semiconductor substrate; forming an inorganic insulating film above the first metal wiring layer; forming an organic insulating film on the inorganic insulating film; forming a via hole in the inorganic insulating film so as to expose the first metal wiring; forming a wiring trench as a recess in the organic insulating film; forming a reactive layer on a side surface of the wiring trench, the reactive layer being capable of reaction under heat with the organic insulating film; applying a heat treatment to the reactive layer so as to permit the reactive layer to react with the organic insulating film while leaving an unreacted reactive layer, thereby allowing a reaction layer to grow on the side surface of the wiring trench, the wiring trench being diminished by the growth of the reaction layer; and removing the unreacted reactive layer to obtain a diminished wiring trench. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0010]      FIG. 1  is a cross sectional view showing a step of a manufacturing method of a semiconductor device according to one embodiment of the present invention;  
         [0011]      FIG. 2  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 1 ;  
         [0012]      FIG. 3  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 2 ;  
         [0013]      FIG. 4  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 3 ;  
         [0014]      FIG. 5  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 4 ;  
         [0015]      FIG. 6  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 5 ;  
         [0016]      FIG. 7  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 6 ;  
         [0017]      FIG. 8  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 7 ;  
         [0018]      FIG. 9  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 8 ;  
         [0019]      FIG. 10  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 9 ;  
         [0020]      FIG. 11  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 10 ;  
         [0021]      FIG. 12  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 11 ;  
         [0022]      FIG. 13  is a cross sectional view showing a step of a manufacturing method of a semiconductor device according to another embodiment of the present invention;  
         [0023]      FIG. 14  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 13 ;  
         [0024]      FIG. 15  is a cross sectional view showing a manufacturing step of the semiconductor device following the step shown in  FIG. 14 ; and  
         [0025]      FIG. 16  is an APC (Auto Process Control) flow chart. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]     Examples of the present invention will now be described. Needless to say, the technical scope of the present invention is not limited to the following Examples.  
       EXAMPLE 1  
       [0027]     In the first step, a first metal wiring layer  12  is formed on a Si substrate  10 , as shown in  FIG. 1 . The first metal wiring layer  12  can be formed by the following method. A resist pattern having a trench pattern is formed on an insulating film  11  that is formed on an element (not shown) formed on the Si substrate  10 , followed by applying a dry etching treatment to the insulating film  11 , with the resist pattern used as a mask, so as to form a wiring trench in the insulating film  11 . Then, a barrier metal material is deposited on the entire surface including the wiring trench formed in the insulating film  11 , followed by depositing a wiring material on the entire surface of the barrier metal layer by the sputtering method and a plating method. It is possible to use, for example, Cu as the wiring material. Alternatively, Au or W can also be used as the wiring material in place of Cu. Finally, the wiring material layer and the barrier metal material layer formed on the insulating film  11  are removed by CMP to bury the wiring trench with the first metal wiring  12 .  
         [0028]     In the next step, a cap insulating film  13  such as a SICN film is formed on the entire surface by a P-CVD method, followed by forming a hybrid insulating film  16  on the cap insulating film  13 . It is desirable for the hybrid insulating film  16  to include an insulating film having a low dielectric constant, i.e., having a relative dielectric constant not higher than 3.5. In this Example, the hybrid insulating film  16  is of a laminate structure comprising an inorganic insulating film  14  formed of SiOC and an organic insulating film  15  formed of PAE (polyarylene ether). The hybrid structure of the insulating film  16  makes it possible to increase the etching selectivity to 2.0 or more in the subsequent step of forming a via hole. Incidentally, the organic insulating film  15  contains a carboxylic acid as an acid component.  
         [0029]     Further, a cap insulating film  17 , a first hard mask  18  and a second hard mask  19  are formed successively in the order mentioned on the hybrid insulating film  16 . The cap insulating film  17  is formed by depositing SiH 4 . The first hard mask  18  is formed by using SiN and the second hard mask  19  is formed by using SiO 2 . In this fashion, the structure as shown in  FIG. 2  is obtained.  
         [0030]     In the next step, a resist film is formed by the ordinary method on the second hard mask  19 , followed by forming a trench pattern  21  having a width of 130 nm in the resist film by the lithography method so as to form a resist pattern  20 . Then, a dry etching is applied to the second hard mask  19  by using the resist pattern  20  as a mask so as to selectively remove by etching the second hard mask  19  as shown in  FIG. 3 .  
         [0031]     Further, the resist pattern  20  is removed by using an O 2  asher, followed by forming a resist film on the entire surface. Then, a via pattern  23  is formed in the resist film by the lithography method so as to form a resist pattern  22 . The via pattern  23  is sized to a diameter of 120 nm. Further, a dry etching is applied to the first hard mask  18  and the cap insulating film  17  by using the resist pattern  22  as a mask, thereby selectively removing the first hard mask  18  and the cap insulating film  17  as shown in  FIG. 4 .  
         [0032]     Further, a dry etching is applied to the organic insulating film  15  so as to form the via pattern  23  in the shape of a recess having a diameter of 120 nm into the organic insulating film  15  as shown in  FIG. 5 .  
         [0033]     In the next step, the entire surface is coated with a water soluble pattern shrinking agent so as to form a reactive layer  24 . The reactive layer  24  is formed on at least a side surface of the via pattern  23 . It is possible to use, for example, RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) material as the pattern shrinking agent. Then, a heat treatment is applied to the reactive layer  24  by using a hot plate at 130° C. for 3 minutes under the air atmosphere. As a result, a reaction is carried out between the RELACS material and the acid component contained in the organic insulating film  15  so as to form a reaction layer  25  on the side surface of the via pattern  23 . Formation of the particular reaction layer  25  is called a shrinking treatment. It is possible to change the temperature of the heat treatment within a range of 100 to 170° C., and the time for the heat treatment can be set at about 1 to 5 minutes. The unreacted reactive layer  24  is removed as shown in  FIG. 7  by performing a rinsing treatment with water. By the formation of the reaction layer  25  on the side surface of the via pattern  23 , the diameter of the via pattern is decreased to 100 nm, thereby forming a diminished via pattern  26 . It is confirmed that the reaction layer  25  grown on the inner surface of the via pattern  23  has a thickness of about 10 nm. It is possible to obtain the via pattern  26  diminished to a desired size by increasing the thickness of the reaction layer  25  grown on the inner surface of the via pattern  23 . It is possible to control the thickness of the reaction layer  25  by controlling the temperature, time, etc. of the heat treatment. Further, a dry etching is applied to the first hard mask  18  so as to transfer the trench pattern  21  into the first hard mask  18  as shown in  FIG. 8 .  
         [0034]     In the next step, a dry etching is applied selectively to the inorganic insulating film  14  so as to form a via hole  27  in the inorganic insulating film  14  as shown in  FIG. 9 . Further, an additional dry etching is applied to the cap insulating film  17  so as to form a wiring trench  28  in the cap insulating film  17 . The second hard mask  19  is removed simultaneously in the stage of selectively etching the inorganic insulating film  14 .  
         [0035]     Then, the cap insulating film  13  at the bottom of the via hole  27  is removed by selectively applying a dry etching treatment to the cap insulating film  13  so as to expose the first metal wiring layer  12  to the outside as shown in  FIG. 10 . In this etching stage, the first hard mask  18  is also removed simultaneously.  
         [0036]     In the next step, a dry etching is applied selectively to the organic insulating film  15  so as to transfer the wiring trench  28  into the organic insulating film  15  as shown in  FIG. 11 . In this etching stage, a RIE treatment is carried out under the NH 3  gas condition in order to remove the reaction layer  25 , with the result that the reaction layer  25  is removed simultaneously in the stage of transferring the wiring trench  28  into the organic insulating film  15 . Because of application of this particular RIE treatment, the thickness of the cap insulating film  17  is also decreased as shown in the drawing.  
         [0037]     Further, a barrier metal layer (not shown) is formed on the side wall and the bottom of the via hole and the wiring trench thus formed, followed by depositing a wiring material on the barrier metal layer so as to form a plug  29  and a second metal wiring layer  30  as shown in  FIG. 12 . It is possible to select the wiring material from the group consisting of, for example, Cu, Al and W.  
         [0038]     In Example 1 described above, a shrinking treatment is performed in forming the via hole so as to make it possible to form a very small via hole having a diameter of 100 nm or less.  
       EXAMPLE 2  
       [0039]     The construction as shown in  FIG. 11  is obtained by a method similar to that in Example 1. As shown in  FIG. 11 , a wiring trench  28  is formed as a recess in the organic insulating film  15 . Incidentally, the via hole is formed to extend through the inorganic insulating film  14  and the cap insulating film  13  by a method similar to that described above. In the next step, the entire surface is coated with a water soluble pattern shrinking agent so as to form a reactive layer  24  as shown in  FIG. 13 . It is possible to use, for example, RELACS material referred to previously as the pattern shrinking agent. Then, a heat treatment is applied to the reactive layer  24  by using a hot plate at 130° C. for 3 minutes under the air atmosphere. As a result, the RELACS material is allowed to react with the acid component contained in the organic insulating film  15  so as to form a reaction layer  25  on the side surface of the wiring trench  28 .  
         [0040]     In the next step, the unreacted reactive layer  24  is removed as shown in  FIG. 14  by applying a rinsing treatment with water. The diameter of the wiring trench  28  is decreased to 100 nm by the formation of the reaction layer  25  on the side surface of the wiring trench  28  so as to form a diminished wiring trench  31 . It is confirmed that the reaction layer  25  grown on the inner surface of the wiring trench  28  has a thickness of about 15 nm. As in the case of the via pattern  23  referred to in Example 1, it is possible to obtain the wiring trench  31  diminished to a desired size by increasing the thickness of the reaction layer  25  grown on the inner surface of the wiring trench  28 . As described previously, the thickness of the reaction layer  25  can be controlled by controlling the temperature and time of the heat treatment.  
         [0041]     In the next step, a barrier metal layer (not shown) is formed on the side wall and the bottoms of the via hole  27  and the diminished wiring trench  31  thus formed, followed by depositing a wiring material on the barrier metal layer so as to form a plug  29  and a second metal wiring layer  30  as shown in  FIG. 15 .  
         [0042]     In Example 2, a shrinking treatment is applied to the wiring trench formed in the organic insulating film so as to make it possible to form a very small metal wiring layer having a width of 100 nm or less.  
       EXAMPLE 3  
       [0043]     In each of Examples 1 and 2 described above, the sizes of the via hole and the wiring trench are measured in advance before application of the shrinking treatment to the organic insulating film. The sizes of the via hole and the wiring trench are deviated by the application of an etching treatment such as RIE to each of the insulating films. The reaction layer having a desired thickness is formed by changing the heating temperature for the shrinking treatment in accordance with the amount of the deviation. In this fashion, the deviation of the size generated in the via hole and the wiring trench is corrected.  
         [0044]     Where the heating temperature in the stage of the shrinking treatment is high, i.e., not lower than 170° C., the reaction layer is allowed to have a thickness of about 15 nm. In Example 3, the heating temperature is changed within a range of 100 to 170° C. so as to form a reaction layer having a desired thickness.  
         [0045]     In the next step, the wiring trench and the via hole are formed by an ordinary method of a dry etching process, followed by burying the wiring material in the wiring trench and the via hole, with a barrier metal layer formed below the wiring material layer. Further, CMP is applied to the laminate structure consisting of the barrier metal layer and the wiring material layer so as to form a dual damascene wiring structure. By employing the aforementioned method, it is possible to decrease the nonuniformity in the sizes of the wiring trench for the second metal wiring layer and the diameter of the via hole.  
         [0046]     The technique for Example 3 is effective as APC (Auto Process Control).  FIG. 16  is a flow chart showing the APC flow. As shown in the drawing, the via patterning, the hard mask processing, the cap insulating film processing, the organic insulating film processing and the size SEM measurement are carried out successively, followed by feeding back the via size. In other words, the shrinking treatment is applied by changing the treating (heating) temperature in accordance with the via size. In the subsequent steps, the via hole formation and the wiring trench formation are carried out successively.  
         [0047]     As described above, the present invention makes it possible to form a fine metal wiring and a fine via hole, the fineness exceeding the limits in the case of employing the lithography technique. Further, it is possible to form a dual damascene wiring having a suppressed nonuniformity of the size by correcting the deviation of the size generated by the dry etching in the steps of forming the wiring trench and the via hole.  
         [0048]     According to an embodiment of the present invention, provided is a method of manufacturing a semiconductor device that permits forming a fine metal wiring and a fine via hole without giving rise to a nonuniformity of the size so as to manufacture a semiconductor device having a decreased nonuniformity of the size.  
         [0049]     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.