Abstract:
The DC level of the output of an amplifier may be dynamically adjusted depending on the operating conditions of the amplifier by comparing the output of the amplifier to a set reference value using a comparator. The output of the comparator is then fed to a state machine which adjusts the DC level of the amplifier output in an autocalibration process until the DC level of the output of the amplifier is substantially equal to the reference value. An undervoltage lockout circuit detects a power supply to the amplifier and causes the calibration to be initiated only when the power supply meets certain requirements. A change in the gain setting in the amplifier is also detected for automatically initiating the calibration process.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a system for cancelling offsets in amplifiers. The invention is particularly useful for conditioning a transducer signal. 
     In Digital Versatile Disc (DVD) and Compact Disc-Read Only Memory (CD-ROM), a photodetector is used for reading information from a disc. The photodetector output current is typically amplified by an amplifier before it is sent to the next stage. &#34;Amplifier offset&#34; is defined as the difference between the DC level of the amplifier output and a reference voltage when no signal (from the photodetector) is applied to the amplifier. Due to the &#34;unipolar&#34; characteristics of the photodetector output current, conventional auto-zeroing circuit may not be used to optimize the amplified output. In existing systems, the amplifier offset is optimized during the wafer sort stage in integrated circuit fabrication by means of a trimming scheme. The integrated circuits for the DVD/CD-ROM systems employ polysilicon or metal fuses. The DC level of the amplifier outputs in such systems are set by applying a high trimming current to burn one or more fuses. 
     Thus, in a conventional trimming scheme for cancelling the amplifier offset, the cancellation may only be performed once, since after the optimization by burning one or more fuses, the DC level of the amplifier output can no longer be changed. Since different operating conditions may result in different amplifier output DC levels, the above-described conventional trimming scheme is quite limited, since the DC level of the amplifier output cannot be changed with the operating conditions. Thus, the operating conditions may change as a function of the gain setting of the amplifier, the condition of the power supply voltage and temperature, as well as backward or forward compatibility to other devices downstream or upstream in the signal path from the amplifier. 
     The requirement of the trimming step during the wafer sort stage will add additional testing costs due to the extra testing time required. Moreover, the application of a high trimming current to burn a fuse may, in some situations, affect product reliability. It is, therefore, desirable to provide an improved system for offset optimization where the above-described drawbacks are alleviated or eliminated. 
     SUMMARY OF THE INVENTION 
     One aspect of the invention is directed towards an apparatus for cancelling offsets in amplifiers, comprising a comparator comparing an output of at least one amplifier to a reference, where no external signal is applied to the at least one amplifier, to provide an output; and means responsive to the comparator output for generating a correction signal applied to the at least one amplifier to adjust DC level of the output of the at least one amplifier until the DC level is essentially equal to the reference. 
     Another aspect of the invention is directed towards a method for cancelling offsets in amplifiers, comprising comparing an output of at least one amplifier to a reference, where no external signal is applied to the at least one amplifier, to provide a comparison output; and generating, in response to the comparison output, a correction signal and applying the correction signal to the at least one amplifier to adjust the DC level of the output of the at least one amplifier until the DC level is substantially equal to the reference. 
     One more aspect of the invention is directed towards an apparatus for conditioning a transducer signal, comprising at least one amplifier for conditioning the transducer signal, said at least one amplifier having an output; comparator means for comparing the output of the at least one amplifier to a reference, where no external signal is applied to the at least one amplifier, to provide an output; and means responsive to the comparator output for generating a correction signal and applying it to the at least one amplifier to adjust the DC level of the output of the at least one amplifier until the DC level is substantially equal to the reference. 
     Yet another aspect of the invention is directed towards a method for conditioning a transducer signal, comprising comparing an output of at least one amplifier to a reference, when no external signal is applied to the at least one amplifier, to provide a comparison output; generating, in response to the comparison output, a correction signal and applying the correction signal to the at least one amplifier to adjust the DC level of the output of the at least one amplifier until the DC level is substantially equal to the reference; and amplifying the transducer signal by means of said at least one amplifier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a system for cancelling offsets in amplifiers to illustrate the preferred embodiment of the invention. 
     FIGS. 2-6 are flow charts illustrating the operation of the state machine in the system of FIG. 1 to illustrate the preferred embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 is a block diagram of a system for cancelling offsets of transimpedence amplifiers for six channels to illustrate the preferred embodiment of the invention. In each of the six channels (A, B, C, D, E, F), a corresponding photodetector, such as photodetector PD-A for channel A, provides a current to a transimpedence amplifier core 12 also having six channels to be amplified, before the amplified output O A  for channel A is provided to the next stage of the system (not shown). Similarly, amplifier core 12 amplifies the output of the other five photodetectors PD-B through PD-F and provides, together with O A , a total of six outputs (O A , O B , . . . O F ). 
     The DC level of the output of amplifier core 12 for each of the six channels may change depending on the gain setting, power supply voltage applied to amplifier core 12 from power terminal 14, temperature and other factors. Also, for backward compatibility with existing compact disc-audio, CD-ROM, CD-R, and CD-RW as well as forward compatibility with DVD-RAM, it is desirable to be able to adjust the DC level of the output of amplifier core 12 for each of the six channels on an as needed basis, or periodically. This is not possible with the conventional technique of trimming, which can only be performed once, after which the DC level of the amplifier output can no longer be changed. 
     For this purpose, the six outputs O A , . . . O F  are selected by an analog multiplexer 16, one at a time, for comparison by comparator 18. Comparator 18 compares each of the six selected outputs of amplifier core 12 to a voltage reference VREF, when the photodetector is applying no signal to the core 12, so that the output of each of the channels is a DC level. Comparator 18 then supplies a comparison output signal to state machine 20. For example, the comparator compares output O A  to the voltage reference. In response to the comparison output or signal, state machine 20 provides an output, which in the preferred embodiment is a five bit binary output, to a corresponding set among six sets of latches 22, where each set includes 5 latches, each latch storing one bit. Such corresponding set of latches (corresponding to output O A ) stores the 5 bit state machine output for adjusting the DC level of the amplifier core output to yield output O A . The stored value is converted by one of six corresponding digital to analog converters 24 into an analog signal and this analog signal is applied to transimpedence amplifier core 12 for adjusting the DC level of the output of the particular channel amplifier core that gives output O A . The above process is applied when the photodetector PD-A (or any other device external to the offset cancellation apparatus) of the channel A is not applying any signals to the amplifier core 12 for such channel, so that the difference between the reference value VREF and the output (a DC level) of the amplifier core 12 for such channel is the offset. After the offset adjustment, the amplifier core for such channel would provide a new output O A  &#39;. The new output O A  &#39; of amplifier core 12 for such channel is again compared by comparator 18 to the voltage reference and the updated comparison output of comparator 18 is used by state machine 20 to provide an updated output for further adjustment of the DC level of the output of the amplifier core 12 for such channel to provide yet another updated output. This process is repeated until the DC level of the output of the amplifier core for such channel is substantially the same as the voltage reference VREF, at which point the state machine applies a next channel calibration signal along path 32 to analog multiplexer 16, causing the multiplexer to select a different output channel of amplifier core 12 than channel A for calibration. 
     The above-described process is then carried out for the remaining five channels so that offsets are adjusted until the DC levels of the outputs of all of the six channels in amplifier core 12 are substantially equal to the voltage reference VREF. 
     The state machine 20 is operated by means of a reference clock from an oscillator 34. After the DC level of the outputs of all channels in amplifier core 12 have been calibrated as described above, state machine 20 sends an end of calibration signal to oscillator 34, causing oscillator 34 to go into a &#34;sleep mode.&#34; By shutting off the oscillator after the completion of the autocalibration process, any reference clock related glitch and/or noise will be eliminated and the performance of the low noise transimpedence amplifier 12 will be enhanced. 
     System 10 may form a part of a typical DVD/CD-ROM head amplifier. When power is first turned on to such typical head amplifier, system 10 will initiate a calibration process for adjusting the offsets of amplifier core 12. However, when power is first turned on, the voltage level applied may be unsteady. If the above-described autocalibration process is carried out when the power supply voltage is still fluctuating, or not at the right voltage, the calibration results may be invalid. To prevent this from happening, an under voltage lock out circuit 42 is employed which senses the power supplied to amplifier core 12. If the voltage level at terminal 14 is still unsteady or at the wrong voltage level, circuit 42 will not generate an enable signal to enable oscillator 34. But if circuit 42 senses that the voltage at terminal 14 is at the proper level or state, circuit 42 will generate an enable signal through logic 44 to oscillator 34, causing oscillator 34 to generate a reference clock for state machine 20, thereby causing state machine 20 to start to operate. 
     The gain of the amplifier core 12 may be altered after the DVD/CD-ROM head amplifier has been operating. Even if the DC levels of the outputs for the different channels of amplifier core 12 were at the proper values prior to the gain change, after the change in gain, the DC level of the outputs of these channels may be off from desired values, so that it is desirable to repeat the calibration process after an alteration in gain of the amplifier core 12. For this purpose, an autosense circuit 52 senses a change in the gain at terminals 54, 56, 58. When circuit 52 senses that there is a change in gain, it applies an enable signal through logic 44 to oscillator 34, causing the oscillator to generate a reference clock to initiate the operation of the state machine 20. State machine 20 will then operate in the manner described above in conjunction with multiplexer 16, comparator 18, latches 22 and converters 24 to perform the autocalibration as described above. The construction of the under voltage lockout circuit 42 and of the autosense circuit 52 may be of conventional design and will not be described in detail here. Logic 44 may simply be an OR-gate. 
     In the preferred embodiment, state machine 20 is used to more accurately calibrate the DC levels of the output of the different channels in amplifier core 12; it will be understood that other circuits may be used instead and are within the scope of the invention. 
     The operation of state machine 20 in the calibration process will now be described in reference to FIGS. 2-6. State machine 20 operates by a process of successive approximation. In reference to FIG. 2, state machine 20 detects whether the comparator 18 output is positive or negative. A positive comparator output indicates that the DC level output (referred to below simply as &#34;output&#34;) of the particular amplifier channel being calibrated is lower than VREF so that it should be increased whereas a negative comparator output indicates that the output of the particular amplifier channel being calibrated is at a higher voltage level compared to VREF so that it should be lowered. First the state machine 20 is reset to all zeros. 
     In the preferred embodiment illustrated in FIGS. 2-6, the state machine 20 has a six bits resolution. Thus, all six bits of the state machine are initially reset to &#34;0&#34; as shown in block 102. The statuses of the bits of state machine 20 are indicated within the ellipses in FIGS. 2-6, where the hexadecimal equivalent state of such binary states are indicated immediately on top of the corresponding ellipse. Thus, as shown in and near ellipse 102, the initial state of the state machine 20 is all zeros, or 00H in hexadecimal. If the comparator output is positive, the most significant bit is set to a &#34;1&#34;, indicating that the amplifier core output for the channel needs to be increased; whereas if the output of the comparator is negative, indicating that such output needs to be decreased, a &#34;0&#34; is indicated for the most significant bit (MSB). Therefore, even though initially and temporarily, the MSB is set to a &#34;1&#34; in ellipse 104, a detection of the comparator output will cause the MSB to be changed to &#34;0&#34; if the comparator output is negative and to remain &#34;1&#34; if the comparator output is positive. 
     For the purpose of illustration, it is assumed that the output of a particular channel of amplifier core 12 being calibrated is at 1.8 volts whereas VREF is at 2.5 volts. Thus, the comparator output will be positive and the MSB will remain a &#34;1.&#34; State machine 20 proceeds to ellipse 106 and automatically sets the next or second MSB bit to a &#34;1&#34; as shown in ellipse 106. The state machine now must test to see if the next or the second MSB bit should be a &#34;1&#34; or a &#34;0.&#34; For this purpose, the state machine sends five bits, that is all six bits except for the MSB, to the corresponding latches 22. In other words, in the particular example here, the binary value &#34;10000&#34; is sent to latches 22. This digital value is then converted by convertor 24 into an analog voltage value and applied to the particular channel being calibrated in amplifier core 12. Convertor 24 may be controlled to select the proper voltage steps. In this example, it is assumed that a binary value of &#34;10000&#34; is converted to 0.5 volts by the convertor, and this step would apply a 0.5 volt adjustment. Thus a &#34;10000&#34; binary value translates into adding a 0.5 volts to the output, resulting in an output of the channel of 2.3 volts. 
     Such 2.3 volts output passes through multiplexer 16 to comparator 18 which detects that such output is still lower than VREF of 2.5 volts. This confirms the correctness of adding the 0.5 volts in ellipse 106 so that the &#34;1&#34; value of the next or second most significant bit is retained and the state machine proceeds to ellipse 108 to set the next or third most significant bit to a &#34;1&#34;, so that ellipse 108 now contains &#34;111000.&#34; The output of state machine 20 is therefore &#34;11000&#34; which is applied to latches 22. This latched binary value translates to a 0.75 volts and the convertor 24 adds a 0.75 volts adjustment to the output of 1.8 volts of the channel being calibrated, resulting in a 2.55 volts output. Comparator 18 detects that such output would be greater than VREF of 2.5 volts, so that the third most significant bit of the state machine 20 is changed from a &#34;1&#34; to a &#34;0&#34;. This is shown in FIG. 5 where the state machine 20 then proceeds to ellipse 110 and the next or the fourth most significant bit is set to a &#34;1&#34;, so that ellipse 110 now contains the value &#34;1 10100&#34; and the binary value &#34;10100&#34; is applied to latches 22. This value is converted by convertor 24 to 0.625 volts which is added to the 1.8 volt output of the channel calibrated, resulting in an output of 2.425 volts which is less than VREF. This means that the fourth most significant bit should retain the value &#34;1&#34; and state machine 20 proceeds to ellipse 112 and so on until all six bits of the state machine are determined. At this point, the DC level of the output of the channel being calibrated has been adjusted to be as close to VREF as permitted by the resolution of the state machine. 
     The state machine then causes the multiplexer 16 to select another channel for calibration unless all the channels have been calibrated. Thus, the latches corresponding to the channel just calibrated will store the value arrived at by the state machine which in turn, causes convertor 24 to apply the appropriate voltage correction to the channel being calibrated in order to adjust the output to the desired value VREF. In this manner, the six sets of latches and the six converters together apply the desired voltage corrections to their corresponding amplifier channels so that these channels have minimal offsets. 
     While in the preferred embodiment, state machine 20 employs six bits, it will be understood that state machine 20 may employ more bits for a more accurate offset adjustment or fewer bits to speed up the calibration process; such and other variations are within the scope of the invention. The conversion of the digital values to analog voltages may be selected to be different from the example used above; such variations are within the scope of the invention. 
     While the embodiment above has been illustrated in reference to an amplifier core and corresponding digital to analog convertors and six sets of latches for six channels, it will be understood that any number of channels may be employed and are within the scope of the invention. While in the embodiment described, the amplifier core 12 is used for amplifying signals from photodetectors for devices such as DVD and CD-ROM, it will be understood that the amplifier core 12 may be used for applying signals from magnetic heads in hard disk drives, or from other transducers, such as those in other mass storage systems and communication systems. In such event, the photodetectors in FIG. 1 would be simply replaced by magnetic heads or other transducers; in such cases, no signals are applied by external devices such as these heads or transducers during the calibration process. Amplifier core 12 in the above embodiment converts current to a voltage. It will be understood that the same calibration scheme may be applied to amplifiers which convert voltage to voltage, voltage to current or current to current as well. 
     While the invention has been described by reference to preferred embodiments, it will be understood that various changes and modifications may be made without departing from the scope of the invention which is to be defined only by the appended claims and their equivalents.