Abstract:
A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

Description:
BACKGROUND OF THE INVENTION 
   1. Technical Field 
   The present invention relates to well isolation trenches (WIT), and more particularly, to well isolation trenches for CMOS (Complementary Metal Oxide Semiconductor) devices (for example SRAM-Static Random Access Memory). 
   2. Related Art 
   In a conventional CMOS device including an N channel and a P channel transistor, the N channel transistor is formed on a P well, and the P channel is formed on an N well. There is always a need for a well isolation trench structure (and a method for forming the same) that provides improved electrical properties of the CMOS device. 
   SUMMARY OF THE INVENTION 
   The present invention provides a semiconductor fabrication method, comprising providing a semiconductor structure which includes: (a) a semiconductor substrate, and (b) a patterned hard mask layer on top of the semiconductor substrate; etching the semiconductor substrate using the patterned hard mask layer as a mask, resulting in a well isolation trench, a first shallow trench, and a second shallow trench; after said etching the semiconductor substrate is performed, covering the first and second shallow trenches without covering the well isolation trench; and after said covering the first and second shallow trenches is performed, etching the semiconductor substrate through the well isolation trench, resulting in the well isolation trench becoming deeper such that when going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function. 
   The present invention provides a semiconductor structure, comprising (a) a semiconductor substrate; (b) a P well and an N well in the semiconductor substrate, wherein the P well comprises a first shallow trench isolation (STI) region, and wherein the N well comprises a second STI region; and (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well, wherein a bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions, and wherein when going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function. 
   The present invention provides a well isolation trench (and a method for forming the same) that provides improved electrical properties of the CMOS device. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1A-12A  show top views of a semiconductor structure  100  going through a fabrication process, in accordance with embodiments of the present invention. 
       FIGS. 1B-12B  show cross section views of the semiconductor structure  100  of  FIGS. 1A-12A , respectively, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1A-12A  show top views of a semiconductor structure  100  going through a fabrication process, in accordance with embodiments of the present invention.  FIGS. 1B-12B  show cross section views of the semiconductor structure  100  of  FIGS. 1A-12A , respectively, in accordance with embodiments of the present invention. 
   More specifically, with reference to  FIG. 1A  and  FIG. 1B  (a cross section view of  FIG. 1A  along a line  1 B- 1 B), in one embodiment, the fabrication process starts out with a semiconductor substrate  110  (such as silicon substrate). Next, in one embodiment, a pad oxide layer  120  is formed on top of the semiconductor substrate  110  by, illustratively, thermal oxidation. Alternatively, the pad oxide layer  120  can be formed by using a deposition technique such as CVD (Chemical Vapor Deposition) method. 
   Next, with reference to  FIG. 2A  and  FIG. 2B  (a cross section view of  FIG. 2A  along a line  2 B- 2 B), in one embodiment, a pad nitride layer  210  is formed on top of the structure  100  of  FIG. 1A  using CVD method. Illustratively, the pad nitride layer  210  comprises silicon nitride. 
   Next, with reference to  FIG. 3A  and  FIG. 3B  (a cross section view of  FIG. 3A  along a line  3 B- 3 B), in one embodiment, a hard mask layer  260  is deposited on top of the structure  100  of  FIG. 2A  using CVD method. Illustratively, the hard mask layer  260  comprises silicon dioxide or any other suitable material. 
   Next, in one embodiment, a first photo resist layer  310  is formed on top of the hard mask layer  260  using a conventional method. 
   Next, in one embodiment, the first photo resist layer  310  is patterned using a conventional lithography process resulting in a first patterned photo resist layer  310  as shown in  FIG. 4A  and  FIG. 4B  (a cross section view of  FIG. 4A  along a line  4 B- 4 B). 
   Next, in one embodiment, the pattern of the first patterned photo resist layer  310  is transferred in turn to the hard mask layer  260 , the pad nitride layer  210 , and the pad oxide layer  120 , resulting in the structure  100  of  FIG. 4A  and  FIG. 4B . Illustratively, the patterning process is performed by a conventional etching process, resulting in openings  410   a,    410   b,    415 ,  410   c,  and  410   d  in the layers  120 ,  210 , and  260 ,  310 . 
   Next, in one embodiment, the first photo resist layer  310  is removed, resulting in the structure  100  of  FIG. 5A  and  FIG. 5B  (a cross section view of  FIG. 5A  along a line  5 B- 5 B). Illustratively, the first photo resist layer  310  is removed using a conventional method. 
   Next, in one embodiment, the semiconductor substrate  110  is etched via the openings  410   a,    410   b,    415 ,  410   c,  and  410   d.  Illustratively, the semiconductor substrate  110  is etched by RIE (Reactive Ion Etching) process, resulting in shallow trenches  410   a′,    410   b′,    415 ′,  410   c′,  and  410   d′,  respectively, as shown in  FIG. 6A  and  FIG. 6B  (a cross section view of  FIG. 6A  along a line  6 B- 6 B). 
   Next, with reference to  FIG. 7A  and  FIG. 7B  (a cross section view of  FIG. 7A  along a line  7 B- 7 B), in one embodiment, a second patterned photo resist layer  710  is formed on top of the structure  100  of  FIG. 6A . More specifically, the second patterned photo resist layer  710  is formed by using a conventional lithography process. It should be noted that portions of the trenches  410   a′,    410   b′,    410   c′,  and  410   d′  and the entire trench  415 ′ are not covered by the second patterned photo resist layer  710 , as shown in  FIG. 7A  and  FIG. 7B . 
   Next, with reference to  FIG. 8A  and  FIG. 8B  (a cross section view of  FIG. 8A  along a line  8 B- 8 B), in one embodiment, the second patterned photo resist layer  710  and the hard mask layer  260  are used as masks for directionally etching the semiconductor substrate  110 , resulting in structure  100  of  FIG. 8A  and  FIG. 8B . In other words, sections of the trenches  410   a′,    410   b′,    410   c′,    410   d′,  and  415 ′ of  FIG. 7A  and  FIG. 7B , which are not covered by the masks, become deeper, resulting in the trenches  410   a″,    410   b″,    410   c″,    410   d″,  and a well isolation trench  415 ″, respectively, as shown in  FIG. 8A  and  FIG. 8B . 
   It should be noted that the process of forming the trench  415 ′ ( FIG. 7A ,  FIG. 7B ) and the process of making the trench  415 ′ deeper, resulting in the well isolation trench  415 ″, uses the same hard mask  260 . As a result, when going from top to bottom of the well isolation trench  415 ″, an area of a horizontal cross section of the well isolation trench  415 ″ does not change abruptly. In other words, when going from top to bottom of the well isolation trench  415 ″, an area of a horizontal cross section of the well isolation trench  415 ″ is essentially a continuous function (i.e., either varies essentially continuously or remains essentially unchanged). The position and the width of the well isolation trench  415 ″ are identical to the initial shallow trench  415 ′. 
   Next, with reference to  FIG. 9A  and  FIG. 9B  (a cross section view of  FIG. 9A  along a line  9 B- 9 B), in one embodiment, the second patterned photo resist layer  710  ( FIG. 8A  and  FIG. 8B ) is removed by a conventional method, and then the hard mask layer  260  ( FIG. 8A  and  FIG. 8B ) is removed using wet etching. 
   Next, with reference to  FIG. 10A  and  FIG. 10B  (a cross section view of  FIG. 10A  along a line  10 B- 10 B), in one embodiment, STI (Shallow Trench Isolation) regions  1010   a,    1010   b,    1010   c,  and  1010   d  are formed in the trenches  410   a′  and  410   a″,    410   b′  and  410   b″,    410   c′  and  410   c″,  and  410   d′  and  410   d″,  respectively, and a well isolation region  1015  is formed in the well isolation trench  415 ″. Illustratively, the STI regions  1010   a,    1010   b,    1010   c,    1010   d  and the well isolation region  1015  comprise silicon dioxide. In one embodiment, the STI regions  1010   a,    1010   b,    1010   c,    1010   d  and the well isolation region  1015  are formed by (i) CVD of a silicon dioxide layer (not shown) everywhere on top of the structure  100  (including in the trenches) of  FIG. 10  and then (ii) CMP (Chemical Mechanical Polishing) the deposited silicon dioxide layer until the pad nitride layer  210  is exposed to the surrounding ambient, resulting in the STI regions  1010   a,    1010   b,    1010   c,    1010   d  and the well isolation region  1015 , as shown in  FIG. 10A  and  FIG. 10B . As a result, when going from top to bottom of the well isolation region  1015 , an area of a horizontal cross section of the well isolation region  1015  does not change abruptly. 
   Next, in one embodiment, the STI regions  1010   a,    1010   b,    1010   c,    1010   d  and the well isolation region  1015  are recessed to approximately the top surface of the pad oxide  120 . Next, in one embodiment, the pad nitride layer  210  is removed by wet etching followed by a CMP process resulting in the structure  100  of  FIG. 11A  and  FIG. 11B  (a cross section view of  FIG. 11A  along a line  11 B- 11 B). Next, with reference to  FIG. 11A  and  FIG. 11B , in one embodiment, a P-region  1110   a  and an N-region  1110   b  are formed in the semiconductor substrate  110  to the north and south of the trench  1015 , respectively. Illustratively, the P-region  1110   a  is formed by ion implantation with P-type dopants, and the N-region  1110   b  is formed by ion implantation with N type dopants, resulting in structure  100  of  FIG. 11A  and  FIG. 11B . Hereafter, the P-region  1110   a  is referred to as a P-well region  1110   a  and the N-region  1110   b  is referred to as an N-well region  1110   b.  In one embodiment, an N-band  1110   c  is also formed by ion implantation under the P-well. The N-band is connected to the N-well. 
   Next, with reference to  FIG. 12A  and  FIG. 12B  (a cross section view of  FIG. 12A  along a line  12 B- 12 B), in one embodiment, doped regions  1220 ,  1230 ,  1240 ,  1250 ,  1260 ,  1270 ,  1280 , and  1290  and gate stacks  1211  and  1212  are formed in the semiconductor substrate  1100 . In one embodiment, the gate stacks  1211  and  1212  are formed by a conventional method. In one embodiment, the doped regions  1220 ,  1230 ,  1240 ,  1250 ,  1260 ,  1270 ,  1280 , and  1290  are formed by ion implantation. Illustratively, the doped regions  1220 ,  1240 ,  1250 , and  1280  are doped with N type dopants, and the doped regions  1230 ,  1260 ,  1270 , and  1290  are doped with P type dopants. In one embodiment, the gate stack  1211  and the doped regions  1240  and  1250  form an N-channel transistor  1211 + 1240 + 1250 ; whereas the gate stack  1212  and the doped regions  1260  and  1270  form a P-channel transistor  1212 + 1260 + 1270 . In one embodiment, the N-channel transistor  1211 + 1240 + 1250  and the P-channel transistor  1212 + 1260 + 1270  are connected so as to form a CMOS device. The doped regions  1280  and  1230  and for the N-well and the P-well contacts, respectively. 
   As can be seen in  FIG. 12A  and  FIG. 12B , the N-channel transistor  1211 + 1240 + 1250  is formed on top of the P-well region  1110   a,  and the P-channel transistor  1212 + 1260 + 1270  is formed on top of the N-well region  1110   b.  These two transistors are separated by the well isolation region  1015  (which is formed in the well isolation trench  415 ″ of  FIG. 9A  and  FIG. 9B ) wherein the well isolation region  1015  is deeper than the STI regions  1010   a,    1010   b,    1010   c,    1010   d.  Therefore, the CMOS device has better device properties. 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.