Abstract:
Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region of the first semiconductor region is formed at a distance from the field oxide film near an end portion remote from the gate electrode, and desirably the feeding region is intermittently formed at intervals in the longitudinal direction.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority of Japanese Patent Application No. 2012-149002 filed Jul. 3, 2012, which is incorporated herein by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device, and more particularly to a structure of a high withstand voltage MOSFET and a high withstand voltage diode each having a high reverse recovery withstand. 
     2. Background Art 
     As an element configuring a switching operation circuit having a high withstand voltage, there is a high withstand voltage LDMOSFET (Laterally Diffused MOS FET). 
       FIG. 1  illustrates a configuration diagram of an output driver circuit as an applied example of the LDMOSFET. In this circuit, the respective gate voltages of a switch element  1 - 1  (frequently configured by an n-type channel LMOSFET) and a switch element  1 - 2  (frequently configured by a p-type channel LDMOSFET) are controlled by a logic circuit  2  so that the switch element  1 - 1  and the switch element  1 - 2  alternately conduct switching operation. 
       FIG. 2  schematically illustrates a voltage change at an output point  3  in a normal operation. When the switch element  1 - 2  is on, and the switch element  1 - 1  is off, the voltage across the output point  3  rises to a positive potential applied to a power line  4 - 2 , and when the switch element  1 - 1  is on, and the switch element  1 - 2  is off, the voltage across the output point  3  falls to a negative potential applied to a power line  4 - 1 . Hence, the voltage across the output point  3  operates so that the potentials of the high voltage power lines  4 - 1  and  4 - 2  rise and fall at on/off timing of the switch elements  1 - 1  and  1 - 2 . 
     From the viewpoint of the above-mentioned operational principle, this circuit is applied to a device having a large gain, and using a high voltage power supply such as an ultrasound pulse IC, and whether this circuit can be realized, or not, largely depends on the performance of the LDMOSFETs configuring this circuit. 
       FIG. 3  illustrates a cross-sectional structure of a related art p-type channel LDMOSFET. The features of the LDMOSFET reside in that, in order to withstand a high potential difference between drain and source regions, a drift layer  6  having a low concentration is disposed between the drain and the source regions, and at this portion, an electric field when a high voltage is applied to the p-type channel LDMOSFET is reduced to provide a high withstand voltage. 
     Also, the feature of this element resides in that a pn junction diode configured by the p-type drift layer  6  and an n-type semiconductor substrate  5  is parasitically present. Due to this diode, electric charge flows from a drain region  17  into a source region  16  when a source potential becomes higher than a drain potential. In an output driver circuit illustrated in  FIG. 1 , a capacitance and an inductance are connected to the output point  3  in a general use environment. When the switch element  1 - 2  transitions from off to on, due to the capacitance and the inductance, the drain potential of the switch element  1 - 2  may rise to the source potential or higher. In this situation, the above-mentioned parasitic diode operates, and a forward current flows into the switch element  1 - 2 . 
       FIG. 4  schematically illustrates a voltage change at the output point  3  in this operation. In a period  101 , a parasitic diode of the switch element  1 - 2  is in a forward state, and in a period  102 , the parasitic diode of the switch element  1 - 2  is in a reverse state. Because the switch element  1 - 2  transitions from on to off immediately after the forward state, a reverse voltage is rapidly applied to the parasitic diode. In this situation, a current flows into the parasitic diode in a reverse direction for a while. This is because a minority carrier stored within the diode by a conductivity modulation of the carrier is pulled back with a high energy by rapid application of the reverse voltage. The reverse current is called “reverse recovery current” of the diode. When this current exceeds a given threshold value, the diode is broken down by heat generation caused by an eddy current. For that reason, a forward current that can flow into the parasitic diode is restricted, and a maximum forward current that does not break down the diode is generally called “reverse recovery withstand”. For the purpose of improving the reverse recovery withstand of the pn junction diode, as the related art, as disclosed in JP-A-2011-003727, there is a technique in which a region having a Schottky contact interface is disposed on a surface on an anode side of the pn junction diode, and the implantation of the minority carrier is restricted at the time of the forward state to reduce the amount of reverse current and improve the withstand at the time of the reverse state. Also, as disclosed in JP-A-2003-224133, there is a technique in which, in the high withstand voltage diode in which the anode region and the cathode region are selectively formed on a semiconductor surface, an anode length and a cathode length are made different from each other so that the amount of current that flows around an anode end portion at the time of the reverse recovery is reduced, and breakdown caused by the concentration of the current is prevented to substantially improve the breakdown withstand. 
     SUMMARY OF THE INVENTION 
     The present inventors have examined problems concerning the reverse recovery withstand of the parasitic diode of the LDMOS through a device simulation. 
       FIG. 5  illustrates a profile distribution of a calculation target which simulates a plan layout site related to parasitic diode operation in the related art LDMOSFET. An anode region formed of a p-type feeding layer  20  and a cathode region formed of an n-type feeding layer  21  are partially formed inside of an n-type drift layer  18 . In this example, the n-type drift layer  18  is formed by diffusing phosphorus of 2.0E 15  cm −2  into a p-type semiconductor substrate doped with boron of 6.0E 13  cm −2 , a p-type drift layer  19  is formed by diffusing boron of 1.0E 16  cm −2  thereinto, and the p-type feeding layer  20  is formed by diffusing boron of 1.0E 16  cm −2  thereinto. Also, the n-type feeding layer  21  is obtained by diffusing phosphorous of 1.0E 19  cm −2  into the p-type semiconductor substrate. An interval between the p-type feeding layer  20  and the n-type feeding layer  21  is set to 12.0 μm. 
     An equipotential line, a hole distribution, and a temperature distribution calculated for the high withstand voltage diode illustrated in  FIG. 5  at the time of the reverse recovery are illustrated in  FIGS. 6 ,  7 , and  8 , respectively. 
     The reverse recovery state is evaluated by raising a voltage across a cathode electrode  46  to 100V at 100 ns from a state in which a forward current is allowed to flow into the diode by allowing −3 V to be applied to the cathode electrode  46  connected to the n-type feeding layer  21  in a state where voltages across an anode electrode  47  connected to the p-type feeding layer  20 , and a peripheral electrode  48  are fixed to 0V. 
     As illustrated in  FIG. 7 , holes flow toward an end portion of the p-type feeding layer  20  in a long side direction thereof. 
     Also, as illustrated in  FIG. 6 , a potential gradient is steep in a region from the end portion of the p-type feeding layer  20  in the long side direction toward an element separation region  22 , and an electric field intensity become higher. This is because the region between the p-type feeding layer  20  and the element separation region  22  is not completely depleted. With the above configuration, a current is concentrated on the end portion of the p-type feeding layer  20  in the long side direction to generate heat. 
     As illustrated in  FIG. 8 , a rise in temperature is concentrated on the end portion of the p-type feeding layer  20  in the long side direction, and it is conceivable that this site is liable to be broken down. 
     From the above results, the present inventors have found out that the suppression in the amount of holes implanted from the anode, and a reduction in the charge amount of holes on the anode region end portion are effective in improvement of the reverse recovery withstand of the parasitic diode. 
     Therefore, it is conceivable that the techniques disclosed in JP-A-2011-003727 and JP-A-2003-224133 for the diode are applied to the parasitic diode of the LDMOS might have the effect of the withstand improvement. 
     However, the related art induces the degradation of a current performance of the MOSFET as an adverse effect. Specifically, when the anode site is subjected to a Schottky junction, a resistance of the feeding portion is raised to increase an on-state resistance of the MOSFET, thereby leading to adverse effects such as the deterioration of the performance per unit size, and an increase in the element size. Also, when the anode length is different from the cathode length, a site disposed between the anode or cathode, and the element separation region, which does not contribute to the performance (that is, a dead space region) is increased, resulting in adverse effects such as the deterioration of the performance per unit size, and the increase in the element size. 
     An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which substantially avoid the adverse effects on the current performance of the LDMOSFET, suppress the amount of carrier implantation from the anode layer of the LDMOS parasitic diode, and improve the reverse recovery withstand of the parasitic diode. 
     The LDMOSFET according to the present invention includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conduction type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conduction type which is an opposite conduction type, feeding regions of the first conduction type and the second conduction type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film. The feeding region of the first semiconductor region is formed at a distance from the field oxide film near an end portion of the field oxide film remote from the gate electrode, and desirably the feeding region intermittently formed at given intervals in the longitudinal direction. 
     According to the present invention, the degradation of the current performance of the high withstand voltage LDMOSFET can be suppressed, and the reverse recovery withstand of the parasitic diode can be improved. Also, as compared with the related art, the element size can be reduced. 
     Further, when the present invention is applied to the high withstand voltage diode, the reverse recovery withstand can be improved likewise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a high voltage output driver; 
         FIG. 2  is a schematic diagram of a voltage change at an output point in a normal operation of the high voltage output driver circuit; 
         FIG. 3  is a cross-sectional view illustrating a related art p-type channel LDMOSFET structure; 
         FIG. 4  is a schematic diagram of a voltage change at the output point in a specific operation of the high voltage output driver circuit; 
         FIG. 5  is a plan view of the related art p-type channel LDMOSFET structure at a portion conducting parasitic diode operation; 
         FIG. 6  is a diagram illustrating a potential distribution at the time of reverse recovery of a parasitic diode in the related-art p-type channel LDMOSFET; 
         FIG. 7  is a diagram illustrating a hole distribution at the time of the reverse recovery of the parasitic diode in the related-art p-type channel LDMOSFET; 
         FIG. 8  is a diagram illustrating an element temperature distribution at the time of the reverse recovery of the parasitic diode in the related-art p-type channel LDMOSFET; 
         FIG. 9  is a plan view illustrating a structure of a p-type channel LDMOSFET according to a first embodiment of the present invention; 
         FIGS. 10A and 10B  are diagrams illustrating the structure of the p-type channel LDMOSFET according to the first embodiment of the present invention, in which  FIG. 10A  illustrates a cross-sectional view (A-A′) of  FIG. 9 , and FIG.  10 B illustrates a cross-sectional view (B-B′) of  FIG. 9 ; 
         FIG. 11  is a circuit diagram of an evaluation circuit that actually measures the reverse recovery withstand of the parasitic diode of the LDMOSFET in the cross-sectional views of  FIGS. 10A and 10B ; 
         FIG. 12  is a diagram illustrating actual measurement results exhibiting the effects of the p-type channel LDMOSFET structure according to the first embodiment of the present invention; 
         FIG. 13  is a diagram illustrating the actual measurement results exhibiting points where there is no adverse effect in the characteristics of the p-type channel LDMOSFET according to the first embodiment of the present invention; 
         FIG. 14  is a plan view illustrating a structure of a p-type channel LDMOSFET according to a second embodiment of the present invention; 
         FIGS. 15A and 15B  are cross-sectional views of  FIG. 14  illustrating the structure of the p-type channel LDMOSFET according to the second embodiment of the present invention, in which  FIG. 15A  illustrates a cross-sectional view (A-A′), and  FIG. 15B  illustrates a cross-sectional view (B-B′); 
         FIG. 16  is a diagram illustrating actual measurement results exhibiting the effects of the p-type channel LDMOSFET structure according to the second embodiment of the present invention; 
         FIG. 17  is a diagram illustrating the actual measurement results exhibiting points where there is no adverse effect in the characteristics of the p-type channel LDMOSFET according to the second embodiment of the present invention; 
         FIG. 18  is a plan view illustrating a structure of an n-type channel LDMOSFET according to a third embodiment of the present invention; 
         FIGS. 19A and 19B  are cross-sectional views of  FIG. 18  illustrating the structure of the n-type channel LDMOSFET according to the third embodiment of the present invention, in which  FIG. 19A  illustrates a cross-sectional view (A-A′), and  FIG. 19B  illustrates a cross-sectional view (B-B′); 
         FIG. 20  is a plan view illustrating a structure of a diode according to a fourth embodiment of the present invention; 
         FIGS. 21A and 21B  are cross-sectional views of  FIG. 20  illustrating the structure of the diode according to the fourth embodiment of the present invention, in which  FIG. 21A  illustrates a cross-sectional view (A-A′), and  FIG. 21B  illustrates a cross-sectional view (B-B′); 
         FIG. 22  is a plan view illustrating a structure of an n-type channel LDMOSFET according to a fifth embodiment of the present invention; and 
         FIGS. 23A and 23B  are cross-sectional views of  FIG. 22  illustrating the structure of the n-type channel LDMOSFET according to the fifth embodiment of the present invention, in which  FIG. 23A  illustrates a cross-sectional view (A-A′), and  FIG. 23B  illustrates a cross-sectional view (B-B′). 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A conduction type described below is exemplary, and the same advantages can be expected even if an n-type and a p-type in the respective embodiments are reversed. 
     First Embodiment 
       FIG. 9  is a plan view illustrating a structure of a high withstand voltage LDMOSFET according to a first embodiment of the present invention, and  FIGS. 10A and 10B  are cross-sectional views illustrating the structure of the high withstand voltage LDMOSFET according to the first embodiment of the present invention (a cross-sectional view of  FIG. 9 ). A field oxide film  11  is selectively formed on a surface of an n-type substrate  23  to form a p-type drift layer  24  low in concentration through implantation and diffusion. 
     Subsequently, a gate oxide film  32  and a gate electrode  29  are patterned to form a gate region. 
     Further, an n-type well layer  26  is implanted and diffused in the gate region in a self-alignment manner to form a channel region. Further, an n-type feeding layer  27  of the n-type well layer  26 , a source p-type feeding layer  28 , and a drain p-type feeding layer  25  (p+ layer) are formed through implantation and diffusion. 
     In this example, the drain p-type feeding layer  25  is formed through implantation with a drain end portion masked to provide a region  36  (hereinafter also called “space”) as a space in which there is no p-type feeding layer between the drain p-type feeding layer  25  and the field oxide film  11 . Also, an element separation layer  30  is formed. 
     Finally, a source electrode  33  is formed over a source plug that is electrically connected to the n-type well feeding layer  27  and the source p-type feeding layer  28 , and a drain electrode  31  is formed over a drain plug that is electrically connected to the drain p-type feeding layer  25 , to thereby complete a p-type channel LDMOSFET according to the present invention. 
       FIG. 12  illustrates results confirmed by actual measurement of the reverse recovery withstand. 
       FIG. 11  illustrates a measuring method. In the LDMOSFET having a distance between a feeding region of a drain region end portion and a field oxide film as a parameter, a pulse voltage is applied to a drain terminal from a power supply  39 . On the other hand, a voltage of 150V is applied to a source terminal short-circuiting a gate terminal by a DC power supply  40 . In this measurement, a parasitic diode  38  of the LDMOSFET becomes in a forward state at the time of applying a pulse voltage, and a forward current flows in the parasitic diode  38 . The parasitic diode  38  transitions to a reverse direction, that is, comes to a reverse recovery state, when the pulse voltage falls. 
     Then, in this measurement, a maximum forward current allowed to flow immediately before breakdown is regarded as a reverse recovery withstand. It is found that the reverse recovery withstand is increased as the distance between the feeding region of the drain region end portion and the field oxide film is increased. 
     The results exhibit the advantages that when the concentration of the feeding p +  layer end portion of the drain region which operates as the anode of the parasitic diode is decreased, the amount of holes implanted from this site at the time of the forward state is decreased, and the amount of holes concentrated on this site at the time of the reverse recovery is decreased, to thereby avoid the concentration of the current. 
       FIG. 13  illustrates the actual measurement results of the current performance of the LDMOSFET according to the present invention. It is confirmed that even if the drain p-type feeding layer is formed at a distance from the drain end portion field oxide film, an FET current performance is not changed. This is because a ratio of a resistance of the feeding site of the drain end portion to the on-state resistance of the overall FET is very small. From the above viewpoint, according to the present embodiment, the reverse recovery withstand of the parasitic diode can be improved without adversely affecting the current performance of the high withstand voltage LDMOSFET. 
     Second Embodiment 
       FIG. 14  is a plan view illustrating a structure of a high withstand voltage LDMOSFET according to a second embodiment of the present invention.  FIGS. 15A and 15B  are cross-sectional views (cross-sectional views of  FIG. 14 ) illustrating the structure of the high withstand voltage LDMOSFET according to the second embodiment of the present invention. 
     A field oxide film  11  is selectively formed on a surface of an n-type substrate  23  to form a p-type drift layer  24  low in concentration through implantation and diffusion. 
     Subsequently, a gate oxide film  32  and a gate electrode  29  are patterned to form a gate region. 
     Then, an n-type well layer  26  is implanted and diffused in the gate region in a self-alignment manner to forma channel region. 
     Further, an n-type feeding layer  27  of the n-type well layer  26 , a source p-type feeding layer  28 , and a drain p-type feeding layer  25  are formed through implantation and diffusion. 
     In this example, the drain p-type feeding layer  25  is formed through implantation with a drain end portion masked to provide a space region  36  in which there is no p-type feeding layer between the drain p-type feeding layer  25  and the field oxide film  11 . 
     Further, the center of the drain region is also masked at given intervals, and formed through the implantation so that sites in which the p-type feeding layer is present and sites in which the p-type feeding layer is not present are alternately disposed with an interval  37 . Then, the element separation layer  30  is formed. Finally, a source electrode  33  is formed over a source plug that is electrically connected to the n-type well feeding layer  27  and the source p-type feeding layer  28 , and a drain electrode  31  is formed over a drain plug that is electrically connected to the drain p-type feeding layer  25 , to thereby complete a p-type channel LDMOSFET according to the present invention. 
       FIG. 16  illustrates results confirmed by actual measurement of the reverse recovery withstand. 
     In this example, the measurement is implemented with a width/interval ratio of the drain feeding layer  25  as a parameter. It is found that in a drain feeding region center portion, the reverse recovery withstand is increased as ratio of the width to the interval is reduced (that is, the space is increased). The results exhibit the advantages that when the concentration of the feeding p +  layer of the drain region which operates as the anode of the parasitic diode is decreased, the amount of holes implanted at the time of the forward state is decreased, and the amount of holes returned to the feeding layer at the time of the reverse recovery is decreased, to thereby reduce the concentration of the current. Also, the results exhibit the advantages that the number of end portions of the anode where the current is liable to be concentrated is increased by intermittently forming the feeding layer so that the concentrated amount of current per one end portion is decreased to improve the breakdown withstand. 
       FIG. 17  illustrates the actual measurement results of the current performance of the LDMOSFET according to the present embodiment. It can be confirmed that even if the drain p-type feeding layer is intermittently formed, the FET current performance is not changed. This is because a ratio of a resistance of the feeding site of the drain to the on-state resistance of the overall FET is very small. From the above viewpoint, it is found that the current performance of the high withstand voltage LDMOSFET is not substantially adversely affected. According to this embodiment, the reverse recovery withstand of the parasitic diode is improved. 
     Third Embodiment 
       FIG. 18  is a plan view illustrating a structure of a high withstand voltage LDMOSFET according to a third embodiment of the present invention.  FIGS. 19A and 19B  are cross-sectional views (cross-sectional views of  FIG. 18 ) illustrating the structure of the high withstand voltage LDMOSFET according to the third embodiment of the present invention. 
     A field oxide film  11  is selectively formed on a surface of an n-type substrate  23 . 
     Subsequently, a gate oxide film  32  and a gate electrode  29  are patterned to form a gate region. 
     Then, a p-type well layer  41  is implanted and diffused in the gate region in a self-alignment manner to form a channel region. Further, a p-type feeding layer  28  of the p-type well layer  41 , a source n-type feeding layer  27 , and a drain n-type feeding layer  38  are formed through implantation and diffusion. In this example, the p-type feeding layer  28  of the source region is formed through implantation with a source end portion masked to provide a space  36  in which there is no p-type feeding layer between the source n-type feeding layer  27  and the gate electrode  29 . 
     Further, the center of the drain region is also masked at given intervals, and formed through the implantation so that sites in which the p-type feeding layer is present and sites in which the p-type feeding layer is not present are alternately formed. 
     Then, the element separation layer  30  is formed. Finally, a source electrode  33  is formed over a source plug that is electrically connected to the p-type well feeding layer  28  and the source n-type feeding layer  27 , and a drain electrode  31  is formed over a drain plug that is electrically connected to the drain n-type feeding layer  38 , to thereby complete an n-type channel LDMOSFET according to the present invention. 
     Fourth Embodiment 
       FIG. 20  is a plan view illustrating a structure of a high withstand voltage diode according to a fourth embodiment of the present invention.  FIGS. 21A and 21B  are cross-sectional views (cross-sectional views of  FIG. 20 ) illustrating the structure of the high withstand voltage diode according to the fourth embodiment of the present invention. A field oxide film  11  is selectively formed on a surface of an n-type substrate  23 , and a p-type drift layer  24  low in concentration is formed through implantation and diffusion. 
     Subsequently, a gate oxide film  32  and a gate electrode  29  are patterned and formed. Then, an n-type well layer  26  is implanted and diffused in the gate electrode  29  in a self-alignment manner. Further, an n-type feeding layer  27  of the n-type well layer  26 , and an anode p-type feeding layer  25  are formed through implantation and diffusion. In this example, the anode p-type feeding layer  25  is formed through implantation with an anode end portion masked to provide a space  36  in which there is no p-type feeding layer between the anode p-type feeding layer  25  and the field oxide film  11 . Further, the center of the anode region is also masked at given intervals, and formed through the implantation so that sites in which the p-type feeding layer is present and sites in which the p-type feeding layer is not present are alternately formed. 
     Then, the element separation layer  30  is formed. Finally, a cathode electrode  42  is formed over a cathode plug that is electrically connected to the n-type well feeding layer  27 , an anode electrode  44  is formed over an anode plug that is electrically connected to the anode p-type feeding layer  25 , and the gate electrode  29  is electrically connected to the cathode electrode  42  to thereby form a high withstand voltage diode according to the present invention. 
     Fifth Embodiment 
       FIG. 22  is a plan view illustrating a structure of a high withstand voltage LDMOSFET according to a fifth embodiment of the present invention.  FIGS. 23A and 23B  are cross-sectional views (cross-sectional views of  FIG. 22 ) illustrating the structure of the high withstand voltage LDMOSFET according to the fifth embodiment of the present invention. 
     A field oxide film  11  is selectively formed on a surface of an n-type substrate  23 . 
     Subsequently, a gate oxide film  32  and a gate electrode  29  are patterned to form a gate region. 
     Then, a p-type well layer  41  is implanted and diffused in the gate region in a self-alignment manner to forma channel region. Further, a p-type feeding layer  28  of the p-type well layer  41 , a source n-type feeding layer  27 , and a drain n-type feeding layer  38  are formed through implantation and diffusion. In this example, the p-type feeding layer  28  of the source region is formed through implantation with a source end portion masked to provide a space  36  in which there is no p-type feeding layer between the source n-type feeding layer  27  and the gate electrode  29 . 
     Then, an element separation layer  30  is formed. Finally, a source electrode  33  is formed over a source plug that is electrically connected to the p-type well feeding layer  28  and the source n-type feeding layer  27 , and a drain electrode  31  is formed over a drain plug that is electrically connected to the drain n-type feeding layer  38 , to thereby complete an n-type channel LDMOSFET according to the present invention.