Abstract:
A process for forming an optical package comprises at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, mounting at least one optical semiconductor device on the molded leadframe strip, at least partially encasing the molded leadframe strip, and singulating the molded leadframe strip to form discrete packages for optical applications. An apparatus for forming an optical package comprises means for at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, means for mounting at least one optical semiconductor device on the at least one molded leadframe strip, means for at least partially encasing the molded leadframe strip, and means for singulating the molded leadframe strip to form discrete and grid array packages.

Description:
RELATED APPLICATIONS 
     This application is a Divisional Application of the co-pending application Ser. No. 12/002,186 filed Dec. 14, 2007 and titled MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” hereby incorporated in its entirety. 
     RELATED APPLICATIONS 
     This application claims benefit of priority under 35 U.S.C. section 119(e) of U.S. Provisional Patent Application 60/875,162 filed Dec. 14, 2006, entitled MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE and U.S. Provisional Patent Application 60/877,274 filed Dec. 26, 2006, entitled MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE, which are both incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention is in the field of semiconductor packaging and is more specifically directed to package with heat transfer. 
     BACKGROUND 
     Optical semiconductor devices are found in many common appliances, such as digital cameras, digital camcorders, laptop computers, cellular phones, and many other devices. Generally, optical devices comprise charge coupled devices along with an image or video processor to compress and transmit data. 
       FIG. 1  shows optical semiconductor device  10  in current practice. The device  10  is a leadframe based device wherein an optical die  11  is mounted on a leadframe  12 . The leadframe  12  is partially encased in a mold compound  13  leaving an opening  14  for the optical die  11 . Optionally, a light permeable covering (not shown) is placed over the optical die  11  for protection. Although such devices  10  offer a high degree of reliability, they are generally limited to a low input output (I/O) count. As devices with optical die  11  increase in complexity and consumers demand items such as cameras having more image capturing capability, die sizes and I/O counts increase. In such applications with dozens or hundreds of I/O, such devices  10  are not an option. In one current example, every prominent manufacturer of high definition televisions offers a rear projection display option. This is commonly marketed by Sony as SXRD and Samsung as DLP, licensed from Texas Instruments. The complexity of such an optical application requires dozens to hundreds of I/O. 
     To overcome the issues mentioned above, the semiconductor industry has moved toward Ball Grid Array (BGA) packages. The BGA is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern. These pins are used to conduct electrical signals from the integrated circuit (IC) to the printed circuit board (PCB) it is placed on. In a BGA, the pins are replaced by balls of solder stuck to the bottom of the package. The device is placed on a PCB having copper pads in a pattern that matches the solder balls. The assembly is then heated, either in a reflow oven or by an infrared heater, causing the solder balls to melt. Surface tension causes the molten solder to hold the package in alignment with the circuit board, at the correct separation distance, while the solder cools and solidifies. The BGA is a solution to the problem of producing a miniature package for an IC with many hundreds of I/O. As pin grid arrays and dual-in-line (DIP) surface mount (SOIC) packages are produced with more and more pins, and with decreasing spacing between the pins, difficulties arose in the soldering process. As package pins got closer together, the danger of accidentally bridging adjacent pins with solder grew. BGAs do not have this problem, because the solder is factory-applied to the package in exactly the right amount. Alternatively, solder balls are able to be replaced by solder landing pads, forming a Land Grid Array (LGA) package. 
       FIG. 2  shows a cutaway image of a generic BGA package  20 . Generally, an IC  21  has bondpads  22  to which bondwires  23  are affixed. The IC  21  is mounted on a substrate  24 . In current practice, the substrate  24  is a laminate, such as polyimide. Generally, the substrate  24  is of a similar construction to a PCB. The substrate  24  has copper patterns  25  formed thereon. The bondwires  23  effectuate electrical contact between the IC  21  and the copper patterns  25 . The copper patterns  25  are electrically connected to solder balls  26  through via holes  27  in the substrate  24 . In most embodiments of BGA packages, the IC  21  is encapsulated by a mold compound  28 . In optical applications, an opening  29  is formed over the IC  21 . Optionally, a light permeable covering, such as glass, is mounted in the opening  29  to protect the die  21 . Although BGA packages effectuate large I/O count devices in small areas, they are susceptible to moisture. Generally, moisture seeps into packages while awaiting assembly into a finished product, such as a computer. When the package is quickly heated to solder the device into its end application, moisture trapped within the device turns into vapor and cannot escape quickly enough, causing the package to burst open. This phenomenon is known as the “popcorn” effect. What is needed is a semiconductor package that is robust to both structural stressors and moisture. 
     SUMMARY OF THE DISCLOSURE 
     A process for forming a semiconductor package for optical applications comprises at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, mounting at least one optical semiconductor device on the molded leadframe strip, mounting bondwires on the at least one semiconductor die to effectuate electrical contact between the at least one semiconductor die and the at least one molded leadframe, mounting at least one cap on the molded leadframe strip, at least partially encasing the molded leadframe strip, the at least one semiconductor device, at least one cap, and bondwires and singulating the molded leadframe strip to form discrete packages for optical applications. The cap is configured to allow light to permeate to the optical semiconductor device. The cap comprises at least one of the following materials: glass, silicon, ceramic, metal, epoxy, and plastic. In some embodiments, the process further comprises embossing at least one step cavity into the molded leadframe strip for encapsulating the at least one semiconductor device. Optionally, the process further comprises coupling the first leadframe strip to a second leadframe strip, thereby forming a dual leadframe strip. The first leadframe strip and the second leadframe strip are coupled by a soft metal which comprises at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds are able to be identical or differing compounds. 
     An apparatus for forming an semiconductor package for optical applications comprises means for at least partially encasing a first leadframe strip in a first mold compound thereby forming a molded leadframe strip, means for mounting at least one optical semiconductor device on the at least one molded leadframe strip, means for mounting bondwires on the at least one semiconductor die to effectuate electrical contact between the at least one semiconductor die and the molded leadframe, means for mounting a cap thereby forming a full cavity into the molded leadframe strip for encapsulating the at least one semiconductor device, means for at least partially encasing the molded leadframe strip, the at least one semiconductor device, cap, and bondwires in a second mold compound, and means for singulating the molded leadframe strip to form discrete and grid array packages. The cap is configured to allow light to permeate to the optical semiconductor device. The cap comprises at least one of the following materials: glass, silicon, ceramic, metal, epoxy, and plastic. In some embodiments, the apparatus further comprises an embossing surface for forming a step cavity into the molded leadframe strip for encapsulating the at least one semiconductor device. Optionally, the apparatus further comprises means for coupling the first leadframe to a second leadframe by a soft metal. The soft metal comprises at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds are able to be identical or differing compounds. 
     A semiconductor package for optical applications comprises a first leadframe, a substrate for supporting the leadframe, at least one semiconductor die mounted on the leadframe, a plurality of bondwires to effectuate electrical contact between the leadframe and the at least one semiconductor die, a cap mounted on the leadframe configured for allowing light to permeate to the at least one semiconductor die and a second mold compound for at least partially encasing the leadframe, the substrate, the at least one semiconductor device and the plurality of wirebonds. In some embodiments, the substrate comprises a first mold compound. Optionally, the first leadframe is coupled to a second leadframe by a soft metal. The soft metal is comprised of at least one of the following materials: gold, silver, lead and tin. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. 
         FIG. 1  is a prior art optical semiconductor package. 
         FIG. 2  is a prior art optical Ball Grid Array package in cross section. 
         FIG. 3  is a process for forming a molded leadframe per an embodiment of the current invention. 
         FIG. 4A  is a process for forming a molded leadframe per an embodiment of the current invention. 
         FIG. 4B  is a process for forming a molded leadframe per an embodiment of the current invention. 
         FIG. 4C  illustrates two exemplary processes for forming a molded leadframe of the current invention. 
         FIG. 5  is a process for forming individual packages per an embodiment of the current invention. 
         FIG. 6A  is a semiconductor package per an embodiment of the current invention. 
         FIG. 6B  is apparatus for realizing the package depicted in  FIG. 6A . 
         FIG. 6C  is an alternate process for forming a package in  FIG. 6A . 
         FIG. 6D  is the remainder of the process for forming the package  FIG. 6A . 
         FIG. 6E  is an alternate apparatus for realizing the package depicted in  FIG. 6A . 
         FIG. 7  is a process for forming a semiconductor package having a light penetrable opening for optical applications. 
         FIG. 7A  is block diagram of a semiconductor package per an embodiment of the current invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous details and alternatives are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. For example, it is commonly known in the art of semiconductor device assembly that assembly is generally done on a matrix array of leadframes, often referred to as leadframe strips, each strip having a plurality of individual positions that will be processed in various ways to form individual packaged semiconductor devices. A position can have one or more semiconductor die within. One of ordinary skill in the art will readily ascertain whether a single leadframe or a matrix of leadframes is being referred to depending on the reference. 
     A process  300  for forming semiconductor packages is detailed in  FIG. 3 . A leadframe strip  301  is shown in cross section. In some embodiments, a top mold  302  and a bottom mold  303  are placed to effectuate the injection therein of a mold compound  304 . The top and bottom molds  302 ,  303  are able to be metal, ceramic, or any material having an appropriate thermal characteristic to withstand the temperatures of the mold compound  304  in its liquid state. It is commonly known by those of ordinary skill in the art of semiconductor device manufacturing that a wide variety of mold compounds  304  can be used, each having advantages, disadvantages, and characteristics appropriate for a given application. By way of example, in high temperature applications such as microprocessors which generate a significant amount of heat, a high thermal conductivity mold compound  304  can be used. What is formed is a molded lead frame  305 . Advantageously, the molded leadframe strip  305  will display enhanced rigidity and robust reliability characteristics. The use of a mold compound  304  further enhances encapsulation and protection from external moisture that standard PCB substrates such as polyimide or FR4 cannot provide. 
     For more predictable molding results, carrier tape is able to be used effectuate the molding process.  FIG. 4A  details another embodiment of the invention. A process  400  includes applying tape  405  on its adhesive side to a leadframe strip  401 . The leadframe strip  401  is then placed in a top mold  412  by the top surface of the leadframe  401 . On the opposite side of the leadframe strip  401 , non-adhesive tape  406  is prepared in a tape loader  407  at the bottom mold  413 . Once the leadframe strip  401  is in place between the top mold  412  and the bottom bold  413 , mold compound  404  is injected and fills all empty cavities. When removed from the mold, a molded leadframe strip  410  is formed. Optionally, a de-gate/de-runner step removes excess mold compound  411 . 
       FIG. 4B  shows alternate embodiments for the process detailed in  FIG. 4A . In some embodiments, the leadframe strip  401  is able to be placed between the top mold  412  and bottom mold  413  with adhesive tape  405  applied to the bottom.  FIG. 4C  shows embodiments wherein the leadframe strip  401  is able to be placed between the top mold  412  and bottom mold  413  without the use of adhesive tape. In an exemplary embodiment, non adhesive tape  406  is able to be provided by a tape loader  407  on the bottom surface of the leadframe strip  401 . In another exemplary embodiment, two tape loaders  407  are provided to effectuate the molding of the leadframe strip  401 . It will be appreciated by those of ordinary skill in the art of semiconductor manufacturing that several embodiments exist to place a leadframe strip  401  between a top mold  412  and a bottom mold  413  and the embodiments discussed herein are written solely to be exemplary and non limiting. 
       FIG. 5  shows a process  500  for the completion of the semiconductor packaging process. Semiconductor devices  501  are mounted on the molded leadframe strip  502 . In some embodiments, multiple semiconductor devices  501  are mounted in each individual position on the molded leadframe strip  502 . Such devices are known as multi chip modules (MCM). Bondwires  503  are mounted on the semiconductor devices  501  to effectuate electrical contact between the molded leadframe strip  502  and the semiconductor devices  501 . In some embodiments where multiple semiconductor devices  501  are placed in each position, bondwires  503  can be placed to effectuate electrical contact between them as applications require. Next, a second mold compound  505  is applied to the molded leadframe strip  502 . The second mold  505  encases the semiconductor devices  501  and bondwires  503  to protect them from harsh outer environments. In some embodiments, the second mold compound  505  and the first mold compound described in  FIGS. 3 and 4  are the same. Alternatively, the first and second mold compound  505  are able to be different to meet the demands of particular applications. By way of example, the semiconductor device  501  and the leadframe  401  in  FIG. 4  can have different coefficients of expansion in response to heat, and different mold compounds having different thermal characteristics such as thermal resistivity and thermal expansion are able to offset such effects. The molded leadframe strip  502  are then singulated by saw blades  515  to form singulated semiconductor packages  520 ,  530  and  540 . The singulated devices  520   530  and  540  are generally tested, subjected to stress, and tested again to ensure reliability and to filter out non passing or non standard units. 
     In some applications, it is advantageous for greater height clearance within the semiconductor package.  FIG. 6A  shows a singulated semiconductor package  600  in cross section. Within the package, a step cavity  601  is capable of receiving a thicker semiconductor die  602 , larger bondwires  603  or in certain embodiments multiple stacked die.  FIG. 6B  shows an exemplary surface  610  of the mold  412  or  413  shown in  FIG. 4B . Elevated protrusions  611  are placed to coincide with a leadframe strip to emboss a recessed area  601  into the leadframe. In an exemplary embodiment, adhesive tape  621  is applied to the back surface of the leadframe strip  622  as shown in  FIG. 6C . The leadframe is flipped over such that its top surface is embossed by the surface  610  of the mold  412  or  413  having the protrusions  611 . 
       FIG. 6D  shows the leadframe strip  622  with a first mold compound  623  to fon a molded leadframe  630  having recessed areas  601 . To form singulated packages, semiconductor devices  602  and bondwires  603  are affixed onto the molded leadframe  630 . The devices  602 , bondwires  603  and molded leadframe  630  are encased in a second mold compound  650 . The second mold compound  650  and the first mold compound  623  are able to be the same compound or different compounds depending on the application. Saw blades  655  then singulate the molded leadframe strip  630  into individual semiconductor packages  690 . As shown in  FIG. 6E , in the case of thick leadframes, the non adhesive tape  610  is able to have pre-formed holes  660  configured to receive protrusions  670  on a mold surface  675 . The mold surface  675  can be the surface of the top mold  412  or the bottom bold  413 . The mold is able to be formed of metal, ceramic, hard impact rubber, or any other suitable material. 
     In another aspect of the invention, a semiconductor package having a light permeable exposed surface and a process for producing the same is disclosed in  FIG. 7 . A leadframe strip  701  is mounted to adhesive tape  702 . In some embodiments, the leadframe  701  is a half etched leadframe. The leadframe strip  701  is molded with a first mold compound  703 . By way of example, the first mold compound is able to be a thermoset compound or a thermoplastic compound. In some embodiments, step cavities  704  are formed by the embossing procedure described in  FIGS. 6A-6D . The adhesive tape  702  is removed forming a molded step cavity leadframe strip  705 . At least one semiconductor device  706  is mounted within each cavity  704 . Wirebonds  707  effectuate electrical contact between the semiconductor device and molded step cavity leadframe strip  705 . In some embodiments where multiple semiconductor devices  706  are mounted in each step cavity  704 , wirebonds  707  are able to effectuate electrical contact between the multiple devices  706  as applications require;  FIG. 7A  shows a block diagram representing of such a semiconductor package. A cap  708  is affixed to the molded cavity leadframe strip forming a full cavity  709 . The cap  708  is able to be comprised of silicon, glass, metal, ceramic, or any other convenient material or combination of materials that are light permeable. A second mold compound  710  is formed over the molded step cavity leadframe strip  705 , semiconductor devices  706  and wirebonds  707 . Preferably, the second mold compound is applied to allow light to permeate the cap  708 . The second mold compound  710  is able to be identical to or different from the first mold compound  703  as applications require. Saw blades  715  singulate the molded step cavity leadframe strip  705  into individual optical packaged devices  720 . The devices  720  are then able to be marked, tested and shipped to customers. In some applications, multiple hundreds of I/O are required, and more than one leadframe is required to effectuate contact between a semiconductor device and its application. Furthermore, flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) is able to be used. A second leadframe is able to couple to the first leadframe by use of a soft metal. The second leadframe is able to be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns. 
     While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.