Abstract:
An apparatus for detecting misalignment of a test pad and a probe card includes: a test pad unit; a guard unit configured to surround the test pad unit, and formed to maintain a predetermined interval with the test pad unit; and a power supply unit configured to supply a predetermined voltage to the guard unit.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2013-0047251, filed on Apr. 29, 2013, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments generally relate to a semiconductor integrated circuit device, and more particularly, to an apparatus for detecting misalignment of a test pad. 
         [0004]    2. Related Art 
         [0005]    Recently, as semiconductor devices become highly integrated, the importance of inspection technology for inspecting the functions of semiconductor devices multiplexed according thereto has increased. 
         [0006]    In general, the inspection of a semiconductor device is performed after a basic inspection of each unit process in the unit process has been performed, and the electrical inspection of an entire semiconductor chip is performed at a wafer level using a tester and a probe station after the semiconductor chip has been manufactured. 
         [0007]    Such wafer level tests use different test schemes depending on the respective types and functions of semiconductors, and can be roughly classified into a disconnection and short test (i.e. open short test), a functional test, a current-voltage characteristic test using direct current (i.e. DC test), a speed test using alternating current (i.e. AC test), and the like. 
         [0008]    Such a wafer level test functions to improve the overall process capability and yield by selecting and removing a semiconductor device having a defect and by solving a problem through a root cause analysis of the defect of the selected semiconductor device in the final step of a semiconductor manufacturing process 
         [0009]    Such a wafer level test is a process of measuring the electrical characteristics of elements constituting a semiconductor chip, through the use of a needle of a probe card mounted on a probe station. 
         [0010]    The needle of the probe card is contacted with a semiconductor chip, i.e. with a test pad electrically coupled to a pad which is formed on a scribe line of a wafer; an electric signal is applied through the needle; and then whether or not the semiconductor chip includes a fault, i.e. the electrical characteristics of elements constituting the semiconductor chip, are determined according to a signal checked from the applied electric signal. 
         [0011]    However, because semiconductor devices are high-integrated, misalignment is frequently generated at an alignment process between a test needle and a test pattern. Accordingly, a wafer level test result becomes to inaccurate to reduce a test yield. 
       SUMMARY 
       [0012]    In an embodiment of the present invention, a misalignment detection apparatus includes: a test pad unit; a guard unit configured to surround the test pad unit, and formed to maintain a predetermined interval with the test pad unit; and a power supply unit configured to supply a predetermined voltage to the guard unit. 
         [0013]    In an embodiment of the present invention, a misalignment detection apparatus includes: a test pad unit; first guard patterns formed in parallel with a long axis of the test pad unit, and disposed at one side and another side of the test pad unit with respect to the long axis of the test pad unit; second guard patterns formed in parallel with a short axis of the test pad unit, and disposed at one side and another side of the test pad unit with respect to the short axis of the test pad unit; and power supply units configured to supply mutually different voltages to the first guard patterns and second guard patterns, respectively, which are formed at said one sides and another sides of the test pad unit. 
         [0014]    In an embodiment of the present invention, a misalignment detection apparatus includes: a test pad unit; a guard unit spaced by a predetermined distance from the test pad unit, and configured with a plurality of patterns which are formed to surround the test pad unit; and a power supply unit configured to supply the plurality of patterns of the guard unit with mutually different power voltages, respectively, wherein the misalignment detection apparatus is configured to detect whether misalignment is generated and a direction thereof by current detected by a probe card when the test pad unit of the guard unit and a needle of the probe card are misaligned. 
         [0015]    In an embodiment of the present invention, a misalignment detection apparatus includes: a test pad unit; a guard unit located adjacent the test pad unit at a predetermined distance from the test pad unit; and a power supply unit configured to supply a predetermined voltage to the guard unit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0017]      FIG. 1  is a block diagram schematically illustrating the configuration of a misalignment detection apparatus according to an embodiment of the present invention; 
           [0018]      FIG. 2  is a detailed circuit diagram illustrating the configuration of a misalignment detection apparatus according to an embodiment of the present invention; 
           [0019]      FIG. 3  is an enlarged plane view of the test pad unit illustrated in  FIG. 1 ; 
           [0020]      FIG. 4  is a plane view illustrating the configuration of a test pad unit according to an embodiment of the present invention; and 
           [0021]      FIGS. 5 to 7  are detailed circuit diagrams illustrating the configurations of misalignment detection apparatuses according to other embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Hereinafter, an apparatus for detecting misalignment of a test pad according to the present invention will be described below with reference to the accompanying drawings through various embodiments. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0023]    Referring to  FIG. 1 , an alignment fault detection apparatus  100  may include a first power supply unit  110 , a second power supply unit  130 , and a fault detection unit  150 . 
         [0024]    The first power supply unit  110  supplies the fault detection unit  150  with a first-level voltage VDD 1  (hereinafter, referred to as a “first power voltage”), and the second power supply unit  130  supplies the fault detection unit  150  with a second-level voltage VSS 1  (hereinafter, referred to as a “second power voltage”) which is different from the first-level voltage. 
         [0025]    The fault detection unit  150  receives the first and second power voltages VDD 1  and VSS 1  from the first and second power supply units  110  and  130 , respectively, and checks whether or not a needle (not shown) of a probe card and a test pad (not shown) are accurately aligned. 
         [0026]    According to an embodiment of the present invention, the fault detection unit  150  can include a test pad unit, and can be configured to output current according to the first and second power voltages VDD 1  and VSS 1  when the needle of the probe card and the test pad are not accurately aligned. 
         [0027]    In more detail (see  FIG. 2 ) about the alignment fault detection apparatus  100  according to an embodiment of the present invention, the first power supply unit  110  can be configured to include a first switching element N 1 , a first resistor R 1 , and a second resistor R 2 . The first switching element N 1  can be configured with, for example, an NMOS transistor, each of the gate and drain of which is electrically coupled to a first power terminal VDD corresponding to a high level, so that the first switching element N 1  is maintained in a turn-on state. The first resistor R 1  is electrically coupled between the first power terminal VDD and the gate of the first switching element N 1 , and supplies a stable voltage to the first switching element N 1 . The second resistor R 2  is electrically coupled between the first switching element N 1  and the fault detection unit  150 , and supplies a stabilized first power voltage VDD 1  to the fault detection unit  150 . 
         [0028]    The second power supply unit  130  can be configured to include a second switching element P 1 , a third resistor R 3 , and a fourth resistor R 4 . The second switching element P 1  can be configured with, for example, a PMOS transistor, each of the gate and source of which is electrically coupled to a second power terminal VSS corresponding to a low level, so that the second switching element P 1  is also maintained in a turn-on state. The third resistor R 3  is electrically coupled between the second power terminal VSS and the gate of the second switching element P 1 , and supplies a stable voltage to the second switching element P 1 . The fourth resistor R 4  is electrically coupled between the second switching element P 1  and the fault detection unit  150 , and supplies a stabilized second power voltage VSS 1  to the fault detection unit  150 . 
         [0029]    The fault detection unit  150  can include a test pad unit  1510  and a guard unit  1550 . The fault detection unit  150  constituted by the test pad unit  1510  and the guard unit  1550  can be formed within a scribe line of a wafer and can be formed in a process of manufacturing a semiconductor device. 
         [0030]    Referring to  FIG. 3 , the test pad unit  1510  can be configured to be a plurality of stripe patterns. The plurality of stripe patterns can be aligned in parallel to each other, and can be all configured as conductive patterns. 
         [0031]    The guard unit  1550  can be disposed on an outside portion of the test pad unit  1510 . The guard unit  1550  can have the shape of an actual ring surrounding the test pad unit  1510 , or can include a pair of first guard patterns  1560 a and  1560 b and a pair of second guard patterns  1570   a  and  1570   b.  The pair of first guard patterns  1560   a  and  1560   b  can be disposed in substantially parallel to each other at a predetermined interval. The first guard patterns  1560   a  and  1560   b  can be extended in substantially parallel with a plurality of stripe patterns which constitute the test pad unit  1510 . The pair of first guard patterns  1560   a  and  1560   b  are spaced apart by a first distance d 1  from an outside of the test pad unit  1510 , e.g. from the edge of the test pad unit  1510  (i.e. the end of a long axis of a stripe pattern). In addition, the first guard patterns  1560   a  and  1560   b  can be formed to have a length longer than those of the plurality of stripe patterns. The first guard patterns  1560   a  and  1560   b  can both be appropriately and electrically coupled with the first power supply unit  110 , and the second guard patterns  1570   a  and  1570   b  can be appropriately and electrically coupled with the second power supply unit  130 . 
         [0032]    The pair of second guard patterns  1570   a  and  1570   b  can be disposed to be substantially perpendicular to the first guard patterns  1560   a  and  1560   b . For example, the second guard patterns  1570   a  and  1570   b  can be disposed between the first guard patterns  1560   a  and  1560   b  which face each other. In addition, the second guard patterns  1570   a  and  1570   b  can be spaced by a second distance d 2  from the edge portion of the test pad unit  1510  (i.e. from the end of a short axis of a stripe pattern). In this case, the first distance d 1  and the second distance d 2  can be, for example, equal to each other. 
         [0033]    A wafer which has been subjected to a wafer level process is mounted on a probe test apparatus. Thereafter, a probe card of the probe test apparatus is aligned with a test pad of a wafer, and then a needle  200  of the probe card is contacted with a predetermined portion of the test pad unit  1510 . 
         [0034]    When the probe card and the test pad unit  1510  are normally aligned and contacted with each other, the probe test apparatus detects a voltage or current representing a floating state through the needle  200  of the probe card. 
         [0035]    That is to say, the test pad unit  1510  is constituted by a plurality of stripe patterns configured as a conductive layer and is spaced from the first guard patterns  1560   a  and  1560   b  and second guard patterns  1570   a  and  1570   b  without an electrical connection, as described above, so that the test pad unit  1510  is maintained at a floating state. Therefore, when a normal alignment is achieved, the probe test apparatus detects a voltage or current suitable for the floating state. 
         [0036]    However, when the probe card and the test pad unit  1510  are misaligned, the needle  200  of the probe card is contacted with the first guard patterns  1560   a  and  1560   b  or the second guard patterns  1570   a  and  1570   b . In this case, since the first guard patterns  1560   a  and  1560   b  are coupled to the first power supply unit  110 , and the second guard patterns  1570   a  and  1570   b  are coupled to the second power supply unit  130 , the probe test apparatus detects a voltage or current corresponding to the first power voltage VDD or second power voltage VSS according to the contact position of the needle  200 . 
         [0037]    Therefore, with one test pad unit, a direction in which the overall probe test pads are aligned can be predicted by current detected by the probe test apparatus. 
         [0038]    In this case, the fault detection unit  150  is not limited to the structure illustrated in  FIG. 3 , and a test pad unit  1510   a  can be configured in the shape of a plate, as illustrated in  FIG. 4 . In addition, first guard patterns  1560   a  and  1560   b  can be configured to have substantially the same length as that of the long axis of the test pad unit  1510   a , and second guard patterns  1570   a  and  1570   b  can be configured to have a length to overlap all of the test pad unit  1510   a  and first guard patterns  1560   a  and  1560   b.    
         [0039]    Also, it is possible to supply different voltages to the pair of first guard patterns  1560   a  and  1560   b  and the pair of second guard patterns  1570   a  and  1570   b , respectively. 
         [0040]    That is to say, as illustrated in  FIG. 5 , one-side first guard pattern  1560   a  of the pair of first guard patterns  1560   a  and  1560   b  is electrically coupled to the first power supply unit  110  described above, and receives the first power voltage VDD 1 . The other-side first guard pattern  1560   b  can be electrically coupled to a third power supply unit  160  which supplies a third power voltage VPP 1  having a level higher than that of the first power voltage VDD 1 . Similarly to the first power supply unit  110 , the third power supply unit  160  can be constituted by a third switching element N 2 , a fifth resistor R 5 , and a sixth resistor R 6 . The third switching element N 2  can be configured with an NMOS transistor, and the gate and drain of the third switching element N 2  is electrically coupled to a third power terminal VPP corresponding to a high level. Accordingly, the third switching element N 2  also is always turned on. In this case, since the third switching element N 2  can be supplied with the third power voltage which is higher than the first power voltage, the third switching element N 2  can be designed to have higher tolerance to a high voltage than the first switching element N 1 . In addition, the fifth resistor R 5  is electrically coupled between the third power terminal VPP and the gate of the third switching element N 2 , and supplies a stable voltage to the third switching element N 2 . The sixth resistor R 6  is electrically coupled between the third switching element N 2  and the other-side first guard pattern  1560   b  of the fault detection unit  150 , and supplies a stable third power voltage VPP 1  to the other-side first guard pattern  1560   b.    
         [0041]    In addition, the one-side second guard pattern  1570   a  is supplied with the second power voltage VSS 1  from the second power supply unit  130 , and the other-side second guard pattern  1570   b  can be electrically coupled to a fourth power supply unit  170  which supplies a fourth power voltage VBB 1  lower than the second power voltage VSS 1 . 
         [0042]    The fourth power supply unit  170  can have a structure similar to that of the second power supply unit  130 , and can include, for example, a fourth switching element P 2 , a seventh resistor R 7 , and an eighth resistor R 8 . The fourth switching element P 2  can be configured with, for example, a PMOS transistor, each of the gate and source of which is electrically coupled to a fourth power terminal VBB corresponding to a substantial low level, so that the fourth switching element P 2  also is always turned on. The seventh resistor R 7  is electrically coupled between the fourth power terminal VBB and the gate of the fourth switching element P 2 , and supplies a stable voltage to the fourth switching element P 2 . The eighth resistor R 8  also is electrically coupled between the fourth switching element P 2  and the other-side second guard pattern  1570   b , and supplies a stabilized fourth power voltage VBB 1  to the other-side second guard pattern  1570   b.    
         [0043]    When the one-side first guard pattern  1560   a , the other-side first guard pattern  1560   b , the one-side second guard pattern  1570   a , and the other-side second guard pattern  1570   b  are configured to receive mutually different voltages, as described above, current or voltages detected by the probe test apparatus become also different to each other when the needle  200  is misaligned. Accordingly, it is possible to accurately predict a direction, of up, down, left and right directions, in which misalignment is caused. 
         [0044]    Also, as illustrated in  FIG. 6 , a third power supply unit  160   a  can be coupled to the first power voltage terminal VDD, instead of being coupled to the third power voltage terminal VPP (i.e., see  FIG. 5 ), and can output a modified first power voltage VDD 2  by adjusting the size of a third switching element N 2   a  and the resistance values of fifth and sixth resistors R 5   a  and R 6   a,  which constitute the third power supply unit  160   a . Since the modified first power voltage VDD 2  has a level different from that of the first power voltage VDD 1 , the pair of first guard patterns  1560   a  and  1560   b  facing each other can be supplied with mutually different voltages. 
         [0045]    Similarly, a fourth power supply unit  170   a  can be coupled to the second power voltage terminal VSS, instead of being coupled to the fourth power voltage terminal VBB (i.e., see  FIG. 5 ), and can output a modified second power voltage VSS 2  by adjusting the size of a fourth switching element P 2   a  and the resistance values of seventh and eighth resistors R 7   a  and R 8   a,  which constitute the fourth power supply unit  170   a . Since the modified second power voltage VSS 2  has a level different from that of the second power voltage VSS 1 , the pair of second guard patterns  1570   a  and  1570   b  facing each other can be supplied with mutually different voltages. 
         [0046]    In addition, as illustrated in  FIG. 7 , a guard unit  1555  can be configured in the shape of a ring without disconnection, wherein the guard unit  1555  can be electrically coupled to the first power supply unit  110  or the second power supply unit  130 . 
         [0047]    As described in detail above, according to the present invention, an alignment fault detection apparatus capable of detecting misalignment between the needle of a probe card and test pads is provided in a scribe line having the test pads mounted thereon. Accordingly, it is possible to easily predict not only whether or not misalignment is generated, but also the direction in which the misalignment is generated. 
         [0048]    While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the apparatus described herein should not be limited based on the described embodiments.