Abstract:
A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode. the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present invention is related to U.S. patent application Ser. No. 10/821,047, filed Apr. 8, 2004, entitled “AN INTERFACE CIRCUIT FOR COUPLING BETWEEN LOGIC CIRCUIT DOMAINS,” 
         [0002]     U.S. patent application Ser. No. 10/821,048, filed Apr. 8, 2004, entitled “BUFFER/DRIVER CIRCUITS,” and  
         [0003]     U.S. patent application Ser. No. 10/835,501, filed Apr. 29, 2004, entitled “SELF LIMITING GATE LEAKAGE DRIVER,” which are incorporated by reference herein. 
     
    
     GOVERNMENT RIGHTS  
       [0004]     This invention was made with Government support under NBCH30390004 awarded by PERCS. The Government has certain rights in this invention. 
     
    
     TECHNICAL FIELD  
       [0005]     The present invention relates in general to complementary metal oxide semiconductor (CMOS) circuits and, in particular, to circuit methodologies for implementing power-gating to control power and leakage.  
       BACKGROUND INFORMATION  
       [0006]     Oxide tunneling current in metal oxide silicon (MOS) field effect transistors (FET) is a non-negligible component of power consumption as gate oxides get thinner, and may in the future become the dominant leakage mechanism in sub-100 nm complementary MOS (CMOS) circuits. The gate current is dependent on various conditions for a single transistor and three main static regions of operation may be identified for a MOSFET. The amount of gate-leakage current differs by several orders of magnitude from one region to another. Whether a transistor leaks significantly or not is also affected by its position in relation to other transistors within a CMOS circuit structure as this affects the voltage stress to which a particular device is subjected.  
         [0007]     The three regions of operation are a function of applied bias if one only considers the parameters that affect the magnitude of gate current in a MOSFET as it operates in relation to other MOSFETs. Assuming that the supply voltage (Vdd) and the threshold voltage (Vt) are fixed, then a MOSFET in a static CMOS logic gate operates in one to the three regions, each with a significantly different amount of gate leakage.  
         [0008]     The first region is called “strong inversion” and is the region where a MOSFET operates with the absolute value of the gate to source voltage (|VGS|) equal to Vdd. The gate-leakage current density for an N-channel FET (NFET) in strong inversion may be as high as 10 3  amperes square centimeter (A/cm 2 ) for an oxide thickness of 1.5 nanometers (nm) at Vdd equal to 3 volts (V). For such a thin oxide, a more realistic value for Vdd is 1.2 V, in which case the gate-leakage current would more likely be 20 A/cm 2 .  
         [0009]     The second region is called the “threshold” region where |VGS|=Vt. A MOSFET operating in the threshold region will leak significantly less than one operating in the strong inversion region, typically 3 to 6 orders of magnitude less depending on Vdd and the oxide thickness.  
         [0010]     The third region is called the “Off” region where |VGS|=0.0 V. For an NFET operating in the Off region, there is no leakage if the drain voltage (Vd)=0.0 V. However, if Vd is equal to Vdd, then a small leakage current in the reverse direction (drain to gate) may be present due to gate-drain overlap area. Of course this current depends on transistor geometry and is typically 10 orders of magnitude less than the gate-leakage current in the strong inversion region.  
         [0011]     The above three regions represent three distinct conditions or states for the channel of a MOSFET. Whether an “ON” transistor operates at strong inversion or at threshold is determined by its position inside a logic circuit structure as well as by the state of other transistors in the circuit structure.  
         [0012]     Both NFETs and P-channel FETs (PFETs) in a logic circuit structure operate in one of the three regions described above. However, the main tunneling current in a PFET device in strong inversion is due to hole tunneling from the valence band and the main tunneling current in an NFET device in strong inversion is due to electron tunneling from the conduction band. Because of this, PFET gate currents are about 10 times smaller than equivalent sized NFET devices. This fact is important in assessing gate-leakage in a static CMOS circuit.  
         [0013]     Since gate leakage currents are measured as current density, it follows that the gate-leakage current in a MOSFET is directly proportional to the gate area (width times length). Transistor sizing, therefore, has a direct impact on the amount of gate-leakage in a CMOS logic circuit.  
         [0014]     As CMOS circuits become smaller, leakage current that results when voltage is applied to the gate of the field effect transistors becomes a significant portion of the power dissipation. Leakage power may become the limiting factor in how small devices may be manufactured. As devices are made smaller, the power supply voltage is correspondingly reduced. However, this may not achieve an adequate reduction in leakage power dissipation. Alternate techniques are being employed to reduce leakage power. One popular technique is to use power-gating to isolate the power supply voltage in groups of circuits at controlled times. These circuits are sometimes referred to as being part of a power-gated domain. Other circuits may be evaluating a logic function and may not be in a power-gated domain. Interfacing between circuits in a power-gated domain and circuits in a non-power-gated domain may prove difficult. The state of an output from a power-gated domain may be uncertain during the time period of power-gating. While the benefits of power-gating are known, there is no consensus on strategies to preserve logic states of outputs in the power-gated domains. Since power-gated domains may be variable, the method of preserving output logic states from circuits in a power-gated domain are controlled by the power-gating control signals themselves.  
         [0015]     The current drive capability of a CMOS buffer depends on the channel size of devices used to drive outputs or to drive many other logic gate inputs. Therefore, one would expect the large devices to exhibit large gate-leakage current when the technology has gate oxides that are very thin. Likewise, logic regions with a high number of logic gates may exhibit a large gate-leakage current due to the large number of devices that are in strong inversion at any one static time (between clock transitions). Logic regions with a high number of logic gates may employ power supply gating whereby the power to the logic devices are decoupled by the action MOSFETs, PFETs for the positive power supply voltage and NFETs for the negative power supply voltage. These regions where power supply gating is employed is sometimes referred to as “cuttable” regions. When a cuttable region is interfaced with a non-cuttable region, then logic states at the interface outputs may become indeterminate when power is decoupled.  
         [0016]     Pipeline circuits are configured such that data proceeds from an input latch point through sequential circuits to an output latch point. Because data proceeds through the sequential circuits in a time sequence, it would be advantageous to partition the sequential circuits in a pipeline such that different levels of power-gating may be employed that would allow performance to be maintained while also allowing selected circuit partitions to be “shut-down” using power gating depending on the validity of the input data and when the circuits will be needed for a valid pipeline process.  
         [0017]     There is, therefore, a need for a power-gating circuit to control selected power-gating devices coupled to partitions in a pipeline such that the partitions may be dynamically powered or shut-down to control leakage power dissipation while maintaining pipeline performance.  
       SUMMARY OF THE INVENTION  
       [0018]     A pipeline circuit is partitioned and has a plurality of sequential power-gated regions between an input latch point and an output latch point. Since data proceeds from the input latch point through circuitry in time sequence, the first pipeline circuit partition (closest to the input latch point) is not power-gated as it would take too much time to charge the power rail if a signal indicating a valid pipeline process was received. The second pipeline circuit has power-gating devices that allow the power rail to be either fully ON or softly ON. Since leakage is proportional to the applied voltage, a power device may be applied to the rail that drops the voltage on the rail a threshold voltage below its normal value. The main power gating device would be OFF in this mode allowing the “soft” power-gating to reduce leakage while allowing fast turn-ON of the power rail in the event a valid signal is received. The third pipeline circuit has complete power-gating that allows the power rail to be completely shut OFF. Since the third pipeline circuit has more time to turn ON, it can be fully power-gated. Latching circuitry may be employed on the valid signal to ensure the valid state is maintained. In one embodiment, the soft power gating device is controlled by a control signal from the power-gating control circuit. In another embodiment, the soft power-gating device is self-biased ON all the time. Registers are employed between the partitions to hold data during periods of power-gating where outputs of power-gated logic may have indeterminate outputs.  
         [0019]     The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:  
         [0021]      FIG. 1  is a circuit block diagram illustrating a basic topology of embodiments of the present invention for power-gating a virtual ground rail;  
         [0022]      FIG. 2  is a circuit block diagram illustrating a basic topology of embodiments of the present invention for power-gating a virtual positive voltage rail;  
         [0023]      FIG. 3  is a circuit block diagram of pipeline power-gating according to embodiments of the present invention;  
         [0024]      FIG. 4  is a circuit block diagram of pipeline power-gating according to another embodiment of the present invention;  
         [0025]      FIG. 5  is a circuit block diagram of pipeline power-gating according to another embodiment of the present invention; and  
         [0026]      FIG. 6  is a data processing system suitable for practicing embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION  
       [0027]     In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing, and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.  
         [0028]     In the following, power supply voltage potentials are distributed to circuits on circuit traces or printed wires which may be referred to interchangeably as power supply rails, grids or buses. Power supply voltage potentials are coupled to the buses or grids to activate various logic circuitry. The power supply voltage potentials may be referred to simply as positive potential or ground potential. The “voltage” term may be dropped for simplicity with the understanding that all the potentials are voltage potentials. Embodiments of the present invention employ power-gating circuitry for generating “virtual” power supply rails (power rails) where switching devices couple and decouple the power rails from the power supply potential. The term virtual may be dropped to simplify circuit descriptions.  
         [0029]     Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.  
         [0030]      FIG. 1  is a block circuit diagram of power-gating according to embodiments of the present invention. A logic circuit domain  101  has a virtual low (ground) power supply rail or bus (VGR)  103  that is coupled to the ground nodes  130 - 132  of selected circuits  110 ,  111 , and  113  in domain  101 . Logic circuit  113  illustrates the FETs making up its logic function. Power supply  115  has positive voltage potential  116  coupled directly to bus  112  and ground voltage potential  117 . The VGR  103  is selectively coupled to the power supply ground voltage potential  117  with parallel N channel field effect transistor (NFET) devices  105 ,  107 , and  109  operating as electronic switches. NFETs  105 ,  107 , and  109  have nodes  150 - 152 , respectively, coupled to VGR  103  and nodes  153 - 154 , respectively, coupled to ground voltage potential  117 . The NFETs  105 ,  107 , and  109  are controlled by logic signals  104 ,  106 , and  108 , respectively. Logic signals  104 ,  106 , and  108  are generated in logic domain  102  with non power-gated circuitry. In this manner, VGR  103  may be coupled to ground potential  117  with various degrees of conductivity.: Large devices have higher conductivity but generally display higher leakage. Smaller devices have lower conductivity but display lower leakage. In this manner, some or all of parallel connected NFETs  105 ,  107 , and  109  may be gated ON when there is a high degree of switching in domain  101  requiring speed in arriving at a logic output in response to logic inputs. Once an output is determined in domain  101 , selective ones of NFETs  105 ,  107 , and  109  may be gated OFF thus reducing leakage power.  
         [0031]      FIG. 2  is a block circuit diagram of power-gating according to embodiments of the present invention. A logic circuit domain  201  has a virtual high (positive) power supply rail or bus (VPR)  203  that is coupled to a positive power bus in selected circuits  210 . Ground bus  211  of logic gates  210  is coupled directly to ground potential  117  of power supply  115 . VPR  203  is coupled to the positive potential  116  of power supply with parallel P channel field effect transistor (PFET) devices  205 ,  207 , and  209  operating as electronic switches. PFETs  205 ,  207 , and  209  have nodes  252 - 254 , respectively, coupled to positive voltage potential  116  and nodes  250 - 251 , respectively, coupled to VPR  203 . The PFETs  205 ,  207 , and  209  are gated by logic signals  204 ,  206 , and  208 , respectively. Logic signals  204 ,  206 , and  208  are generated in logic domain  202  with non-power-gated circuitry. In this manner, VPR  203  may be coupled to the positive potential  116  with various degrees of conductivity. Large devices have higher conductivity but display higher leakage. Smaller devices have lower conductivity but display lower leakage. Some or all of PFETs  205 ,  207 , and  209  may be gated ON when there is a high degree of switching in domain  201  requiring speed in arriving at a logic output in response to logic inputs. Once an output is determined in domain  201 , selective ones of PFETs  205 ,  207 , and  209  may be gated OFF thus reducing leakage power.  
         [0032]      FIGS. 1 and 2  show partitioned power-gating applied to only one power supply potential at a time, however, it is understood that embodiments of the present invention may employ partitioned power-gating simultaneously to both power supply potentials for logic circuits in a logic domain (e.g., domain  201 ).  
         [0033]     The following  FIGS. 3-5  show embodiments of the present invention applied to one power supply bus at a time for simplicity. Likewise, NFETs and PFETs are used as electronic switches to couple power supply potentials to virtual power buses. These NFETs and PFETs have nodes that may not have specific designators as used in  FIGS. 1 and 2  for simplicity of the drawings.  
         [0034]      FIG. 3  is a circuit block diagram of pipeline power-gating  300  according to embodiments of the present invention. Data  313  is latched into register  314  by clock  312 . Processing of data  313  proceeds through the pipeline stage  320  comprising partitions A, B, and C. Partitions A, B, and C are not internally clocked but process data in a ripple through mode. In this embodiment, only the input and output of pipeline stage  320  are clocked. Finally the processed data  313  is latched into register  318  with clock  312 . Pipeline  320  is partitioned to allow power-gating according to embodiments of the present invention. It is obvious that logic in partition A processes data  313  before partition B and likewise partition B is needed to process the output of partition A before partition C. Since partition A must act on data  313  first, its logic is not power gated. Partition B has a power bus  323  that is power gated by the action of PFET  305  and NFET  308  and partition C has power bus  324  that is power-gated by PFET  309 .  
         [0035]     Power gating control  302  receives a valid signal  301  which indicates if the data  313  is valid and can be launched into pipeline stage  320 . Partition A can begin processing data  313  immediately upon receipt of a valid signal  301  as its power buses are not power gated. Since there is some time before partition B is needed, its power bus  323  has two levels of power-gating. Since there is not much time to charge its power bus  323 , NFET  308  acts as a soft power-gate. When NFET  308  is turned ON by a logic one on control  307 , it sets bus  323  at a threshold voltage (Vt) below the voltage potential of power rail  326 . Keeping power rail  323  at a slightly lower voltage potential improves leakage while allowing power rail  323  to be quickly charged to the power supply voltage potential when PFET  305  is turned ON by a logic zero on control  304 . In this embodiment, control  307  transitions to a logic one before control  304  transitions to a logic one. Partition C is needed last and more time is available to charge power rail  324  from a lower voltage potential so power rail  324  is fully power-gated. Feedback signals  306  and  310  are used to signal power gating control  302  that partition B  316  and partition C  317  have completed processing and may set to their appropriate power-gating states.  
         [0036]      FIG. 4  is a circuit block diagram of pipeline power-gating  400  according to another embodiment of the present invention. Data  413  is latched into register  414  by clock  412 . Processing of data  413  proceeds through the pipeline stage  420  comprising partition A, B, and C and registers  421  and  422 . Registers  422  and  421  are used to hold outputs of partitions A and B. Partitions A, B, and C are not internally clocked but each process data in a ripple through mode. In this embodiment, only the inputs and outputs of the partitions A, B, and C are clocked. Finally the processed data  413  is latched into register  418  with clock  412 . Pipeline  420  is partitioned to allow power-gating according to embodiments of the present invention. It is obvious that logic in partition A processes data  413  before partition B and likewise partition B is needed to process the output of partition A before partition C. Since partition A must act on data  413  first, its logic is not power gated. Partition B has a power bus  423  that is power gated by the action of PFET  405  and NFET  408  and partition C has power bus  424  that is power-gated by PFET  409 .  
         [0037]     Power gating control  402  receives a valid signal  401  which indicates if the data  413  is valid and can be launched into pipeline stage  420 . Partition A  415  can begin processing data  413  immediately upon receipt of a valid signal  401  as its power buses are not power gated. Since there is some time before partition B  416  is needed, its power bus  423  has two levels of power-gating. Since there is not much time to charge its power bus  423 , NFET  408  acts as a soft power-gate. When NFET  408  is turned ON by a logic one on control  407 , it sets bus  423  at a threshold voltage (Vt) below the voltage potential of power rail  426 . Keeping power rail  423  at a slightly lower voltage potential improves leakage while allowing power rail  423  to be quickly charged to the power supply voltage potential when PFET  405  is turned ON by a logic zero on control  404 . Once processed data has been latched into register  421 , partition B,  416  can be power-gated knowing that the output states are latched into a non power-gated register. In this embodiment, control  407  transitions to a logic one before control  404  transitions to a logic one. Partition C  417  is needed last and more time is available to charge power rail  424  from a lower voltage potential so power rail  424  is fully power-gated. Likewise, once the data from partition C  417  has been latched in to register  418 , it can be fully power-gated. Feedback signals  406  and  410  are used to signal power gating control  402  that partition B  416  and partition C  417  have completed processing and may set to their appropriate power-gating states.  
         [0038]      FIG. 5  is a circuit block diagram of pipeline power-gating  500  according to another embodiment of the present invention. Data  513  is latched into register  514  by clock  512 . Processing of data  513  proceeds through the pipeline stage  520  comprising partition A, B, and C and registers  521  and  522 . Registers  522  and  521  are used to hold outputs of partitions A and B. Partitions A, B, and C are not internally clocked but each process data in a ripple through mode. In this embodiment, only the inputs and outputs of the partitions A, B, and C are clocked. Finally the processed data  513  is latched into register  518  with clock  512 . Pipeline  520  is partitioned to allow power-gating according to embodiments of the present invention. It is obvious that logic in partition A processes data  513  before partition B and likewise partition B is needed to process the output of partition A before partition C. Since partition A must act on data  513  first, its logic is not power gated. Partition B has a power bus  523  that is power gated by the action of PFET  505  and NFET  508  and partition C has power bus  524  that is power-gated by PFET  509 .  
         [0039]     Power gating control  502  receives a valid signal  501  which indicates if the data  513  is valid and can be launched into pipeline stage  520 . Partition A  515  can begin processing data  513  immediately upon receipt of a valid signal  501  as its power buses are not power gated. Since there is some time before partition B  516  is needed, its power bus  523  has two levels of power-gating. Since there is not much time to charge its power bus  523 , NFET  508  acts as a soft power-gate that is self biased ON all the time. NFET  508  is always on and it sets bus  523  at a threshold voltage (Vt) below the voltage potential of power rail  526  when PFET  505  is turned OFF by a logic one on control  504 . Keeping power rail  523  at a slightly lower voltage potential improves leakage while allowing power rail  523  to be quickly charged to the power supply voltage potential when PFET  505  is turned ON by a logic zero on control  504 . Once processed data has been latched into register  521 , partition B  516  can be power-gated knowing that the output states are latched into a non power-gated register. Partition C  517  is needed last and more time is available to charge power rail  524  from a lower voltage potential so power rail  524  is fully power-gated by PFET  509  which also is controlled by control  504 . Likewise, once the data from partition C  517  has been latched in to register  518 , it can be fully power-gated.  
         [0040]     When Valid  533  is a logic one and Clk  512  transitions to a logic one, NFETs  531  and  532  turn ON pulling the input to inverter  502  to a logic zero and the output of inverter  503  to a logic zero turning ON both PFET  505  and  509  thereby charging power rails  523  and  524  to full power supply potential. Since power rail  524  may be fully discharged it takes longer to charge. When Clk  512  transitions to a logic zero, it turns ON PFET  530  and pulls input of inverter  502  to a logic one causing its output to transition to a logic zero turning ON keeper PFET  501  which latches the logic one state at the input of inverter  502  and at the output of inverter  503 . This turns OFF both PFET  505  and PFET  509 . Power rail  523  is soft power-gated as NFET  508  is biased ON setting power rail  523  at threshold voltage Vt below the full power supply potential at power rail  526  and power rail  524  is turned fully OFF.  
         [0041]      FIG. 6  is a high level functional block diagram of a representative data processing system  600  suitable for practicing the principles of the present invention. Data processing system  600  includes a central processing system (CPU)  610  operating in conjunction with a system bus  612 . System bus  612  operates in accordance with a standard bus protocol, such as the ISA protocol, compatible with CPU  610 . CPU  610  operates in conjunction with electronically erasable programmable read-only memory (EEPROM)  616  and random access memory (RAM)  614 . Among other things, EEPROM  616  supports storage of the Basic Input Output System (BIOS) data and recovery code. RAM  614  includes DRAM (Dynamic Random Access Memory) system memory and SRAM (Static Random Access Memory) external cache. I/O Adapter  618  allows for an interconnection between the devices on system bus  612  and external peripherals, such as mass storage devices (e.g., a hard drive, floppy drive or CD/ROM drive), or a printer  640 . A peripheral device  620  is, for example, coupled to a peripheral control interface (PCI) bus, and  110  adapter  618  therefore may be a PCI bus bridge. User interface adapter  622  couples various user input devices, such as a keyboard  624  or mouse  626  to the processing devices on bus  612 . Display  638  which may be, for example, a cathode ray tube (CRT), liquid crystal display (LCD) or similar conventional display units. Display adapter  636  may include, among other things, a conventional display controller and frame buffer memory. Data processing system  600  may be selectively coupled to a computer or telecommunications network  641  through communications adapter  634 . Communications adapter  634  may include, for example, a modem for connection to a telecom network and/or hardware and software for connecting to a computer network such as a local area network (LAN) or a wide area network (WAN). CPU  610  and other components of data processing system  600  may contain pipeline circuitry that is pipeline power-gated according to embodiments of the present invention to manage leakage current and thus leakage power.