Abstract:
The adverse affects of using out-of-bounds texels for bilateral interpolation may be reduced by redefining the valid texel domain as having four corners defined at the centers of four corner texels. As a result, the texels around the periphery of the valid texture domain are partial texels, with the corner texels being one quarter of a texel and the edges being half of a texel.

Description:
BACKGROUND 
       [0001]    When using tiled resources or sparse textures, an application managed paging system takes an address space that covers a very large texture that cannot be loaded at once. But instead of loading the whole texture, only portions thereof called tiles are loaded. While the address space covers a very large area, only a small part of the address space is actually close to the viewer. Then usually only the smaller mip levels and a tiny part of the larger mip levels are used. 
         [0002]    The application decides which chunks of the address space get mapped to memory. Then the system translates from tiled resource address space into physical or virtual address space. As a result, when a page is accessed, it may or may not be mapped to memory. Near an edge, filtering may overlap over into unmapped areas. This may result, for example, in returning zeros and causing the image to fade to black. 
         [0003]    With anisotropic filtering, it is hard to know which tiles will be touched. However, using data from unmapped tiles may result in visually perceptible artifacts. 
         [0004]    In texture sampling, texel values are specified at the centers of the texel grid. This means that any linearly interpolating sampling operation near the border (i.e. in the outermost half texel-wide region) will access texels both inside and outside the valid texel domain. 
         [0005]    This is a problem since the out-of-bounds texel(s) may be ill-defined, i.e., either assigned an incorrect color by wrapping, or belong to a null tile in a tiled resource. Even if sample taps for out-of-bounds texels are discarded, a half texel-wide region of incorrectly interpolated color remains. This is visually distracting and prevents current texture filtering from being used for multi-texturing (Ptex). 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Some embodiments are described with respect to the following figures: 
           [0007]      FIG. 1  is a depiction of texel corner addressing according to one embodiment; 
           [0008]      FIG. 2  is a depiction of sampling near an edge of a texture (u=1.0) by selecting between texels #0 and #3; 
           [0009]      FIG. 3  shows wrap mode diagrams for one embodiment; 
           [0010]      FIG. 4  shows mipmap level overlap for some embodiments; and 
           [0011]      FIG. 5  is a flow chart for one embodiment. 
           [0012]      FIG. 6  is a block diagram of a processing system according to one embodiment; 
           [0013]      FIG. 7  is a block diagram of a processor according to one embodiment; 
           [0014]      FIG. 8  is a block diagram of a graphics processor according to one embodiment; 
           [0015]      FIG. 9  is a block diagram of a graphics processing engine according to one embodiment; 
           [0016]      FIG. 10  is a block diagram of another embodiment of a graphics processor; 
           [0017]      FIG. 11  is a depiction thread execution logic according to one embodiment; 
           [0018]      FIG. 12  is a block diagram of a graphics processor instruction format according to some embodiments; 
           [0019]      FIG. 13  is a block diagram of another embodiment of a graphics processor; 
           [0020]      FIG. 14A  is a block diagram of a graphics processor command format according to some embodiments; 
           [0021]      FIG. 14B  is a block diagram illustrating a graphics processor command sequence according to some embodiments; 
           [0022]      FIG. 15  is a depiction of an exemplary graphics software architecture according to some embodiments; 
           [0023]      FIG. 16  is a block diagram illustrating an IP core development system according to some embodiments; and 
           [0024]      FIG. 17  is a block diagram showing an exemplary system on chip integrated circuit according to some embodiments. 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    A texel addressing mode places texels in a sampling area defined by the centers of four corner texels, in a texel grid. In one embodiment, the tile size and valid texel domain remains the same while the sampling region is reduced by one texel. The sampling region is measured in normalized coordinates that span from 0.0 on the left/top edges of the sampling region, to 1.0 on its right/bottom edges. Then, a half texel width region, within the valid texel domain, remains around the periphery and catches any filtering operations, from within the sampling area, but using portions of texels outside the sampling area. 
         [0026]    With this mode, any linear filtering operation inside the sampling area accesses only valid texels, as shown in  FIG. 1 . The two crosses in  FIG. 1  are two different sampling coordinates for a texel, indicated as a square with a dot at its center. The dashed boxes show the four texels that are accessed for bilinear interpolation for the sampling coordinates at texels at (1,1) and (4,3). 
         [0027]    In the standard mode (i.e. without texel corner addressing), for texels along the edge of the valid texture domain, texels needed for bilinear interpolation/filtering lie outside the valid texture domain when sampling near the border and as a result, texels of different tiles or texels computed by applying a wrap mode can be accessed. These different tiles may be null tiles, in some cases. Null tiles have not been allocated to memory. Accessing null tiles may result in user visible artifacts. Similarly texels computed by application of a wrap mode may represent incorrect colors and result in user visible artifacts. 
         [0028]    With corner texel addressing, only valid texels (i.e. texels within the valid texel domain) are accessed during filtering. This feature, combined with sample tap discard, supports smooth anisotropic sampling across multiple textures and/or all the way to the edge of a null tile in a tiled resource, in one embodiment. It also improves wrap modes such as mirror, wrap, and border wrap modes. 
         [0029]    The unnormalized texel coordinate grid changes so that texel values are specified at integral positions instead of at half-texel offsets, as in current application program interfaces (APIs). Since the hardware is changed to place texels at corners, in some embodiments extra coding and null tile fallback to access a lower mip level to fill in missing data is not needed. 
         [0030]    Under this corner texel placement, conventional texture wrap modes are redefined to handle out-of-bounds coordinates without replicating edge texels. Discarding of out-of-bounds sample taps handles anisotropic filtering smoothly across multiple textures and/or at the border of null tiles in tiled resources in some embodiments. This may eliminate the need for a more elaborate null tile fallback. 
         [0031]    Without the corner texel addressing feature, a border of incorrect color may result, and there may be visible seams whenever textures meet or at the edges of null tiles in a tiled resource. 
         [0032]    With standard linear sampling of tiled resources, one or more sample taps may belong to null tiles (i.e., tiles that are not yet created or loaded from memory). A null tile fallback is thus required in standard linear sampling to fill in missing data, e.g., by accessing a lower mip level that has been loaded or by returning a predefined color for missing texels. These linear sampling operations will there therefore interpolate between valid texels and invalid texels provided by the null tile fallback, resulting in a border region of incorrect color. 
         [0033]    In some embodiments, any linear sampling operation within a valid tile (i.e. valid texel domain) always accesses texels only within that tile, i.e., without triggering the null tile fallback. 
         [0034]    For anisotropic sampling, the texture sampler computes a weighted sum of bilinear filtering operations along the main axis of anisotropy. With a corner texel addressing mode, each such bilinear filter is either valid or invalid. With sample tap discard, the invalid ones are discarded and the result renormalized. Hence, filtering is smooth all the way to the edge of the null tile, which gives an improvement in image quality. 
         [0035]    Corner texel addressing can be implemented for linear and point sampling in one dimension (1D). This extends to higher dimensions by applying the same rules along each dimension. Anisotropic sampling is typically done by a number of linear filtering operations along the main direction of anisotropy, so the rules for linear sampling apply. 
         [0036]    Consider the task of linear sampling an element from a particular mip level of a one-dimensional texture (Texture1D), given a scalar floating point texture coordinate in normalized space. Linear sampling in 1D selects the nearest two texels and weights the texels based on the proximity of the sample location to them. These operations are performed in sequence:
       1. Given a 1D texture coordinate in normalized space U, assumed to be any float32 value.   2. U is scaled by the Texture1D size-1 because the sampling region is one texel smaller than with center texel addressing. Call this scaledU.   3. ScaledU is converted to at least 16.8 fixed point. Call this fxpScaledU.   4. The integer part of fxpScaledU is the chosen left texel. Call this tFloorU. Note that the conversion to fixed point is basically accomplished by: tFloorU=floor(scaled).   5. The right texel, tCeilU, is simply tFloorU+1.   6. The weight value wCeilU is assigned the fractional part of fxpScaledU, converted to float (although using less than full float32 precision for computing and processing wCeilU and wFloorU is permitted).   7. The weight value wFloorU is 1.0f−wCeilU.   8. If tFloorU or tCeilU are out of range of the texture, a texture wrap mode (in one embodiment defined by D3D11_SAMPLER_STATE&#39;s AddressU mode) is applied to each individually.   9. Since more than one texel is chosen, the single sample result is computed as: texelFetch(tFloorU)*wFloorU+texelFetch(tCeilU)*wCeilU.       
 
         [0046]    For point sampling, the address computation is modified so that the normalized texture coordinate is scaled by the texture dimension minus 1, and then a 0.5 offset is added before truncating to round to the nearest texel:
       1. Given a 1D texture coordinate in normalized space U, assumed to be any float32 value.   2. U is scaled by the Texture1D size−1, and 0.5f is added. Call this scaledU.   3. ScaledU is converted to at least 16.8 Fixed Point. Call this fxpScaledU.   4. The integer part of fxpScaledU is the chosen texel. Call this t. Note that the conversion to Fixed Point basically accomplished: t=floor(scaledU).   5. If t is outside [0 . . . numTexels−1] range, the texture wrap mode (in one embodiment defined by D3D11_SAMPLER_STATE&#39;s AddressU mode) is applied.       
 
         [0052]    Texture wrap modes specify what value to assign to out-of-bounds texels. In current APIs, the following wrap modes are commonly defined: BORDER (use fixed border color), CLAMP (clamp texel coordinates to the edge), MIRROR (every odd repetition of the texture is flipped), MIRROR_ONCE (repeat with flipping once around zero, and use clamping beyond that), and WRAP (wrap texel coordinates to the valid domain by a modulo operation). 
         [0053]    In a corner texel addressing mode, texels are placed at integral texel coordinates including the edges of the texture domain [0,1] in normalized coordinates. Thus the texture wrap modes may be redefined to select which texel to use at the edges of the domain. For example, in WRAP mode, the texels may be placed (in 1D) as shown in  FIG. 2  for a 4-texel wide 1D texture. 
         [0054]    In one embodiment, the texture wrap modes are defined as shown in  FIG. 3  that illustrates the wrapping behavior in one dimension for the different wrapping modes with corner addressing. The lower squares indicate the texel colors.  FIG. 3  shows different wrap modes for both corner texel addressing (on the left) and center texel addressing (on the right) as labeled. For center texel addressing, a five texels wide texture with colors: yellow, blue, purple, green, and orange is used, where the leftmost texel #0 is yellow, and the rightmost texel #4 is orange. For illustrating center texel addressing, a four texels wide texture with colors yellow, blue, purple, and green, is used. 
         [0055]    The first wrap mode called WRAP mode is illustrated in connection with a border at coordinate 0 on the u axis. As shown, the colors orange (0), and yellow (Y) are split right at the sampling region border marked by the coordinate 0. In one embodiment, sampling exactly at the border returns texel #0 (yellow). The behavior is repeated at every border, i.e., normalized sampling coordinate that is a whole integer (positive or negative). However in center addressing, the green (G) and yellow texel colors are on either side of the border marked by coordinate 0 and thus mixing occurs in between. 
         [0056]    In the CLAMP mode shown next, the yellow color is aligned directly at the border while it is split across the border in the center texel addressing mode. Sampling at any coordinate outside the border returns yellow. For corner texel addressing, sampling at a coordinate just inside the border results in mixing in between the border and interior texels, while for center addressing, mixing does only occur for coordinates more than half texel inside the border (thus resulting in a half texel wide region of constant color). 
         [0057]    In BORDER mode, the border, indicated by gray color, splits precisely at the sampling region edge marked by coordinate 0 on the left, but the gray color and the yellow color are split apart in the center texel mode, resulting in bleeding in between so that a precisely colored border is not achieved. 
         [0058]    Similarly in the MIRROR mode, the yellow colors border precisely at the edge 0 but not so in the center texel addressing mode. In corner addressing mode, sampling at any coordinate to the left or right of the border results in mixing the colors of the neighboring texels at each respective side, while in center addressing mode, sampling at a coordinate within a half texel wide region on either side of the border results in a constant color (yellow), which is undesirable in some applications. 
         [0059]    For BORDER and WRAP modes logic decides between the two edge texels when crossing borders of the sampling region. 
         [0060]    Since corner texel addressing changes how a texture would be authored, the addressing mode (corner vs center) may be part of the texture resource and not the sampler state. The addressing mode may be selected by a bit (flag) associated with each resource in one embodiment. 
         [0061]    Computing mipmaps for a texture with corner addressing may involve a different mipmap reduction filter than standard center addressing. For standard addressing and power-of-two textures, each texel lies directly under 2×2 texels on the next lower mipmap level and many implementations thus use a simple box filter (averaging the four texels). 
         [0062]    For corner addressing using the default mipmap sizes, this is no longer true, as shown in the  FIG. 4 . In this example using corner addressing, texel (1,1) at the coarser level (L+1) overlaps 3×3 texels in the next lower mip level (L). A wider reduction filter may be used. Thus a larger mipmap reduction kernel may be used with individually computed weights. The same situation also occurs for non-power-of-two textures using standard addressing. 
         [0063]    The feature changes the effective number of texels that map to the [0,1] domain from N to N−1 at each miplevel. Hence, with the standard selection of mipmap sizes (i.e. for center addressing) and default level of detail (LOD) computation that finds the (fractional) miplevel to sample from, texture filtering will be slightly overblurred (smaller texel to pixel ratio than LOD suggests). In practice, the difference is minimal and can usually be ignored (i.e. mipmap sizes and LOD kept as is). 
         [0064]    In one embodiment, mipmap sizes are modified with corner texel addresses to account for the reduction in effective resolution. In current APIs, mipmap sizes are chosen as: mipslice L+1 size=floor(mipslice L size/2). To keep the same effective resolution with corner addressing, this equation may be changed with corner addressing to: mipslice L+1 size=floor((mipslice L size−1)/2)+1. 
         [0065]    For example, starting with a base resolution that is a power-of-two plus one, i.e., 2 K +1 where K is a positive integer, this scheme results in a chain of mipmaps that are each of size 2 K-L +1, where L is the mip level (0 is the highest resolution mip level), i.e., the effective resolution is a power-of-two at each level. 
         [0066]    In another embodiment, the level of detail (LOD) computation is modified in corner addressing mode to account for the slight reduction in effective resolution. In practice, this results in a negative LOD bias (when a lower LOD value refers to a higher resolution mip level). The LOD bias may either be computed directly in the texture sampler, or in user space by additional shader code. One possible LOD modification is given by: 
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         [0000]    where M is the base resolution of the texture in texels, and X is the standard fractional LOD and Y is the modified LOD accounting for the reduction in effective resolution. This can be extended to a 2D texture of base resolution M×N texels by using, for example, the maximum max(M,N) or geometric mean √{square root over (MN)} in the equation above. 
         [0067]    A sequence  20 , shown in  FIG. 5 , for corner addressing may be implemented in software, firmware and/or hardware. In software and firmware embodiments computer executed instructions may be stored in one or more non-transitory computer readable media such as magnetic, optical or semiconductor storage. For example, a graphics processor may implement the sequence. 
         [0068]    The sequence  20  begins by determining whether corner addressing has been selected as indicated in diamond  22 . A bit may be set or reset to select corner addressing versus conventional texel addressing. 
         [0069]    If corner addressing was selected, then the texel values are specified at integral positions as indicated in block  24 . Out-of-bounds coordinates are handled without replicating edge texels as pointed out in block  26 . 
         [0070]    Redefined texture wrap modes are used to select which texels to use at edges of the valid texel domain as indicated in block  28 . Out-of-bounds sample taps may be discarded as indicated in block  30 . 
         [0071]      FIG. 6  is a block diagram of a processing system  100 , according to an embodiment. In various embodiments the system  100  includes one or more processors  102  and one or more graphics processors  108 , and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors  102  or processor cores  107 . In on embodiment, the system  100  is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. 
         [0072]    An embodiment of system  100  can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments system  100  is a mobile phone, smart phone, tablet computing device or mobile Internet device. Data processing system  100  can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, data processing system  100  is a television or set top box device having one or more processors  102  and a graphical interface generated by one or more graphics processors  108 . 
         [0073]    In some embodiments, the one or more processors  102  each include one or more processor cores  107  to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores  107  is configured to process a specific instruction set  109 . In some embodiments, instruction set  109  may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores  107  may each process a different instruction set  109 , which may include instructions to facilitate the emulation of other instruction sets. Processor core  107  may also include other processing devices, such a Digital Signal Processor (DSP). 
         [0074]    In some embodiments, the processor  102  includes cache memory  104 . Depending on the architecture, the processor  102  can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor  102 . In some embodiments, the processor  102  also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores  107  using known cache coherency techniques. A register file  106  is additionally included in processor  102  which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor  102 . 
         [0075]    In some embodiments, processor  102  is coupled to a processor bus  110  to transmit communication signals such as address, data, or control signals between processor  102  and other components in system  100 . In one embodiment the system  100  uses an exemplary ‘hub’ system architecture, including a memory controller hub  116  and an Input Output (I/O) controller hub  130 . A memory controller hub  116  facilitates communication between a memory device and other components of system  100 , while an I/O Controller Hub (ICH)  130  provides connections to I/O devices via a local I/O bus. In one embodiment, the logic of the memory controller hub  116  is integrated within the processor. 
         [0076]    Memory device  120  can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device  120  can operate as system memory for the system  100 , to store data  122  and instructions  121  for use when the one or more processors  102  executes an application or process. Memory controller hub  116  also couples with an optional external graphics processor  112 , which may communicate with the one or more graphics processors  108  in processors  102  to perform graphics and media operations. 
         [0077]    In some embodiments, ICH  130  enables peripherals to connect to memory device  120  and processor  102  via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller  146 , a firmware interface  128 , a wireless transceiver  126  (e.g., Wi-Fi, Bluetooth), a data storage device  124  (e.g., hard disk drive, flash memory, etc.), and a legacy I/O controller  140  for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. One or more Universal Serial Bus (USB) controllers  142  connect input devices, such as keyboard and mouse  144  combinations. A network controller  134  may also couple to ICH  130 . In some embodiments, a high-performance network controller (not shown) couples to processor bus  110 . It will be appreciated that the system  100  shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, the I/O controller hub  130  may be integrated within the one or more processor  102 , or the memory controller hub  116  and I/O controller hub  130  may be integrated into a discreet external graphics processor, such as the external graphics processor  112 . 
         [0078]      FIG. 7  is a block diagram of an embodiment of a processor  200  having one or more processor cores  202 A- 202 N, an integrated memory controller  214 , and an integrated graphics processor  208 . Those elements of  FIG. 7  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor  200  can include additional cores up to and including additional core  202 N represented by the dashed lined boxes. Each of processor cores  202 A- 202 N includes one or more internal cache units  204 A- 204 N. In some embodiments each processor core also has access to one or more shared cached units  206 . 
         [0079]    The internal cache units  204 A- 204 N and shared cache units  206  represent a cache memory hierarchy within the processor  200 . The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units  206  and  204 A- 204 N. 
         [0080]    In some embodiments, processor  200  may also include a set of one or more bus controller units  216  and a system agent core  210 . The one or more bus controller units  216  manage a set of peripheral buses, such as one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express). System agent core  210  provides management functionality for the various processor components. In some embodiments, system agent core  210  includes one or more integrated memory controllers  214  to manage access to various external memory devices (not shown). 
         [0081]    In some embodiments, one or more of the processor cores  202 A- 202 N include support for simultaneous multi-threading. In such embodiment, the system agent core  210  includes components for coordinating and operating cores  202 A- 202 N during multi-threaded processing. System agent core  210  may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores  202 A- 202 N and graphics processor  208 . 
         [0082]    In some embodiments, processor  200  additionally includes graphics processor  208  to execute graphics processing operations. In some embodiments, the graphics processor  208  couples with the set of shared cache units  206 , and the system agent core  210 , including the one or more integrated memory controllers  214 . In some embodiments, a display controller  211  is coupled with the graphics processor  208  to drive graphics processor output to one or more coupled displays. In some embodiments, display controller  211  may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor  208  or system agent core  210 . 
         [0083]    In some embodiments, a ring based interconnect unit  212  is used to couple the internal components of the processor  200 . However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor  208  couples with the ring interconnect  212  via an I/O link  213 . 
         [0084]    The exemplary I/O link  213  represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module  218 , such as an eDRAM module. In some embodiments, each of the processor cores  202 - 202 N and graphics processor  208  use embedded memory modules  218  as a shared Last Level Cache. 
         [0085]    In some embodiments, processor cores  202 A- 202 N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores  202 A- 202 N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores  202 A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores  202 A- 202 N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor  200  can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components. 
         [0086]      FIG. 8  is a block diagram of a graphics processor  300 , which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor  300  includes a memory interface  314  to access memory. Memory interface  314  can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory. 
         [0087]    In some embodiments, graphics processor  300  also includes a display controller  302  to drive display output data to a display device  320 . Display controller  302  includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. In some embodiments, graphics processor  300  includes a video codec engine  306  to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &amp; Television Engineers (SMPTE) 421 M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats. 
         [0088]    In some embodiments, graphics processor  300  includes a block image transfer (BLIT) engine  304  to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE)  310 . In some embodiments, graphics processing engine  310  is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations. 
         [0089]    In some embodiments, GPE  310  includes a 3D pipeline  312  for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline  312  includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system  315 . While 3D pipeline  312  can be used to perform media operations, an embodiment of GPE  310  also includes a media pipeline  316  that is specifically used to perform media operations, such as video post-processing and image enhancement. 
         [0090]    In some embodiments, media pipeline  316  includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine  306 . In some embodiments, media pipeline  316  additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system  315 . The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system  315 . 
         [0091]    In some embodiments, 3D/Media subsystem  315  includes logic for executing threads spawned by 3D pipeline  312  and media pipeline  316 . In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem  315 , which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem  315  includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data. 
         [0092]      FIG. 9  is a block diagram of a graphics processing engine  410  of a graphics processor in accordance with some embodiments. In one embodiment, the GPE  410  is a version of the GPE  310  shown in  FIG. 8 . Elements of  FIG. 9  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. 
         [0093]    In some embodiments, GPE  410  couples with a command streamer  403 , which provides a command stream to the GPE 3D and media pipelines  412 ,  416 . In some embodiments, command streamer  403  is coupled to memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer  403  receives commands from the memory and sends the commands to 3D pipeline  412  and/or media pipeline  416 . The commands are directives fetched from a ring buffer, which stores commands for the 3D and media pipelines  412 ,  416 . In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The 3D and media pipelines  412 ,  416  process the commands by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to an execution unit array  414 . In some embodiments, execution unit array  414  is scalable, such that the array includes a variable number of execution units based on the target power and performance level of GPE  410 . 
         [0094]    In some embodiments, a sampling engine  430  couples with memory (e.g., cache memory or system memory) and execution unit array  414 . In some embodiments, sampling engine  430  provides a memory access mechanism for execution unit array  414  that allows execution array  414  to read graphics and media data from memory. In some embodiments, sampling engine  430  includes logic to perform specialized image sampling operations for media. 
         [0095]    In some embodiments, the specialized media sampling logic in sampling engine  430  includes a de-noise/de-interlace module  432 , a motion estimation module  434 , and an image scaling and filtering module  436 . In some embodiments, de-noise/de-interlace module  432  includes logic to perform one or more of a de-noise or a de-interlace algorithm on decoded video data. The de-interlace logic combines alternating fields of interlaced video content into a single fame of video. The de-noise logic reduces or removes data noise from video and image data. In some embodiments, the de-noise logic and de-interlace logic are motion adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the de-noise/de-interlace module  432  includes dedicated motion detection logic (e.g., within the motion estimation engine  434 ). 
         [0096]    In some embodiments, motion estimation engine  434  provides hardware acceleration for video operations by performing video acceleration functions such as motion vector estimation and prediction on video data. The motion estimation engine determines motion vectors that describe the transformation of image data between successive video frames. In some embodiments, a graphics processor media codec uses video motion estimation engine  434  to perform operations on video at the macro-block level that may otherwise be too computationally intensive to perform with a general-purpose processor. In some embodiments, motion estimation engine  434  is generally available to graphics processor components to assist with video decode and processing functions that are sensitive or adaptive to the direction or magnitude of the motion within video data. 
         [0097]    In some embodiments, image scaling and filtering module  436  performs image-processing operations to enhance the visual quality of generated images and video. In some embodiments, scaling and filtering module  436  processes image and video data during the sampling operation before providing the data to execution unit array  414 . 
         [0098]    In some embodiments, the GPE  410  includes a data port  444 , which provides an additional mechanism for graphics subsystems to access memory. In some embodiments, data port  444  facilitates memory access for operations including render target writes, constant buffer reads, scratch memory space reads/writes, and media surface accesses. In some embodiments, data port  444  includes cache memory space to cache accesses to memory. The cache memory can be a single data cache or separated into multiple caches for the multiple subsystems that access memory via the data port (e.g., a render buffer cache, a constant buffer cache, etc.). In some embodiments, threads executing on an execution unit in execution unit array  414  communicate with the data port by exchanging messages via a data distribution interconnect that couples each of the sub-systems of GPE  410 . 
         [0099]      FIG. 10  is a block diagram of another embodiment of a graphics processor  500 . Elements of  FIG. 10  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. 
         [0100]    In some embodiments, graphics processor  500  includes a ring interconnect  502 , a pipeline front-end  504 , a media engine  537 , and graphics cores  580 A- 580 N. In some embodiments, ring interconnect  502  couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system. 
         [0101]    In some embodiments, graphics processor  500  receives batches of commands via ring interconnect  502 . The incoming commands are interpreted by a command streamer  503  in the pipeline front-end  504 . In some embodiments, graphics processor  500  includes scalable execution logic to perform 3D geometry processing and media processing via the graphics core(s)  580 A- 580 N. For 3D geometry processing commands, command streamer  503  supplies commands to geometry pipeline  536 . For at least some media processing commands, command streamer  503  supplies the commands to a video front end  534 , which couples with a media engine  537 . In some embodiments, media engine  537  includes a Video Quality Engine (VQE)  530  for video and image post-processing and a multi-format encode/decode (MFX)  533  engine to provide hardware-accelerated media data encode and decode. In some embodiments, geometry pipeline  536  and media engine  537  each generate execution threads for the thread execution resources provided by at least one graphics core  580 A. 
         [0102]    In some embodiments, graphics processor  500  includes scalable thread execution resources featuring modular cores  580 A- 580 N (sometimes referred to as core slices), each having multiple sub-cores  550 A- 550 N,  560 A- 560 N (sometimes referred to as core sub-slices). In some embodiments, graphics processor  500  can have any number of graphics cores  580 A through  580 N. In some embodiments, graphics processor  500  includes a graphics core  580 A having at least a first sub-core  550 A and a second core sub-core  560 A. In other embodiments, the graphics processor is a low power processor with a single sub-core (e.g.,  550 A). In some embodiments, graphics processor  500  includes multiple graphics cores  580 A- 580 N, each including a set of first sub-cores  550 A- 550 N and a set of second sub-cores  560 A- 560 N. Each sub-core in the set of first sub-cores  550 A- 550 N includes at least a first set of execution units  552 A- 552 N and media/texture samplers  554 A- 554 N. Each sub-core in the set of second sub-cores  560 A- 560 N includes at least a second set of execution units  562 A- 562 N and samplers  564 A- 564 N. In some embodiments, each sub-core  550 A- 550 N,  560 A- 560 N shares a set of shared resources  570 A- 570 N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in the various embodiments of the graphics processor. 
         [0103]      FIG. 11  illustrates thread execution logic  600  including an array of processing elements employed in some embodiments of a GPE. Elements of  FIG. 11  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. 
         [0104]    In some embodiments, thread execution logic  600  includes a pixel shader  602 , a thread dispatcher  604 , instruction cache  606 , a scalable execution unit array including a plurality of execution units  608 A- 608 N, a sampler  610 , a data cache  612 , and a data port  614 . In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logic  600  includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache  606 , data port  614 , sampler  610 , and execution unit array  608 A- 608 N. In some embodiments, each execution unit (e.g.  608 A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit array  608 A- 608 N includes any number individual execution units. 
         [0105]    In some embodiments, execution unit array  608 A- 608 N is primarily used to execute “shader” programs. In some embodiments, the execution units in array  608 A- 608 N execute an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). 
         [0106]    Each execution unit in execution unit array  608 A- 608 N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units  608 A- 608 N support integer and floating-point data types. 
         [0107]    The execution unit instruction set includes single instruction multiple data (SIMD) instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible. 
         [0108]    One or more internal instruction caches (e.g.,  606 ) are included in the thread execution logic  600  to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g.,  612 ) are included to cache thread data during thread execution. In some embodiments, sampler  610  is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler  610  includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit. 
         [0109]    During execution, the graphics and media pipelines send thread initiation requests to thread execution logic  600  via thread spawning and dispatch logic. In some embodiments, thread execution logic  600  includes a local thread dispatcher  604  that arbitrates thread initiation requests from the graphics and media pipelines and instantiates the requested threads on one or more execution units  608 A- 608 N. For example, the geometry pipeline (e.g.,  536  of  FIG. 10 ) dispatches vertex processing, tessellation, or geometry processing threads to thread execution logic  600  ( FIG. 11 ). In some embodiments, thread dispatcher  604  can also process runtime thread spawning requests from the executing shader programs. 
         [0110]    Once a group of geometric objects has been processed and rasterized into pixel data, pixel shader  602  is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, pixel shader  602  calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel shader  602  then executes an application programming interface (API)-supplied pixel shader program. To execute the pixel shader program, pixel shader  602  dispatches threads to an execution unit (e.g.,  608 A) via thread dispatcher  604 . In some embodiments, pixel shader  602  uses texture sampling logic in sampler  610  to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing. 
         [0111]    In some embodiments, the data port  614  provides a memory access mechanism for the thread execution logic  600  output processed data to memory for processing on a graphics processor output pipeline. In some embodiments, the data port  614  includes or couples to one or more cache memories (e.g., data cache  612 ) to cache data for memory access via the data port. 
         [0112]      FIG. 12  is a block diagram illustrating a graphics processor instruction formats  700  according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction format  700  described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed. 
         [0113]    In some embodiments, the graphics processor execution units natively support instructions in a 128-bit format  710 . A 64-bit compacted instruction format  730  is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format  710  provides access to all instruction options, while some options and operations are restricted in the 64-bit format  730 . The native instructions available in the 64-bit format  730  vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field  713 . The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit format  710 . 
         [0114]    For each format, instruction opcode  712  defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control field  714  enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For 128-bit instructions  710  an exec-size field  716  limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field  716  is not available for use in the 64-bit compact instruction format  730 . 
         [0115]    Some execution unit instructions have up to three operands including two source operands, src 0   722 , src 1   722 , and one destination  718 . In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC 2   724 ), where the instruction opcode  712  determines the number of source operands. An instruction&#39;s last source operand can be an immediate (e.g., hard-coded) value passed with the instruction. 
         [0116]    In some embodiments, the 128-bit instruction format  710  includes an access/address mode information  726  specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction  710 . 
         [0117]    In some embodiments, the 128-bit instruction format  710  includes an access/address mode field  726 , which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction  710  may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction  710  may use 16-byte-aligned addressing for all source and destination operands. 
         [0118]    In one embodiment, the address mode portion of the access/address mode field  726  determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction  710  directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction. 
         [0119]    In some embodiments instructions are grouped based on opcode  712  bit-fields to simplify Opcode decode  740 . For an 8-bit opcode, bits  4 ,  5 , and  6  allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group  742  includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group  742  shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group  744  (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group  746  includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group  748  includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group  748  performs the arithmetic operations in parallel across data channels. The vector math group  750  includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands. 
         [0120]      FIG. 13  is a block diagram of another embodiment of a graphics processor  800 . Elements of  FIG. 13  having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. 
         [0121]    In some embodiments, graphics processor  800  includes a graphics pipeline  820 , a media pipeline  830 , a display engine  840 , thread execution logic  850 , and a render output pipeline  870 . In some embodiments, graphics processor  800  is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor  800  via a ring interconnect  802 . In some embodiments, ring interconnect  802  couples graphics processor  800  to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect  802  are interpreted by a command streamer  803 , which supplies instructions to individual components of graphics pipeline  820  or media pipeline  830 . 
         [0122]    In some embodiments, command streamer  803  directs the operation of a vertex fetcher  805  that reads vertex data from memory and executes vertex-processing commands provided by command streamer  803 . In some embodiments, vertex fetcher  805  provides vertex data to a vertex shader  807 , which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher  805  and vertex shader  807  execute vertex-processing instructions by dispatching execution threads to execution units  852 A,  852 B via a thread dispatcher  831 . 
         [0123]    In some embodiments, execution units  852 A,  852 B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units  852 A,  852 B have an attached L1 cache  851  that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions. 
         [0124]    In some embodiments, graphics pipeline  820  includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader  811  configures the tessellation operations. A programmable domain shader  817  provides back-end evaluation of tessellation output. A tessellator  813  operates at the direction of hull shader  811  and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to graphics pipeline  820 . In some embodiments, if tessellation is not used, tessellation components  811 ,  813 ,  817  can be bypassed. 
         [0125]    In some embodiments, complete geometric objects can be processed by a geometry shader  819  via one or more threads dispatched to execution units  852 A,  852 B, or can proceed directly to the clipper  829 . In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shader  819  receives input from the vertex shader  807 . In some embodiments, geometry shader  819  is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled. 
         [0126]    Before rasterization, a clipper  829  processes vertex data. The clipper  829  may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer/depth  873  in the render output pipeline  870  dispatches pixel shaders to convert the geometric objects into their per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic  850 . In some embodiments, an application can bypass the rasterizer  873  and access un-rasterized vertex data via a stream out unit  823 . 
         [0127]    The graphics processor  800  has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units  852 A,  852 B and associated cache(s)  851 , texture and media sampler  854 , and texture/sampler cache  858  interconnect via a data port  856  to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler  854 , caches  851 ,  858  and execution units  852 A,  852 B each have separate memory access paths. 
         [0128]    In some embodiments, render output pipeline  870  contains a rasterizer and depth test component  873  that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache  878  and depth cache  879  are also available in some embodiments. A pixel operations component  877  performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine  841 , or substituted at display time by the display controller  843  using overlay display planes. In some embodiments, a shared L3 cache  875  is available to all graphics components, allowing the sharing of data without the use of main system memory. 
         [0129]    In some embodiments, graphics processor media pipeline  830  includes a media engine  837  and a video front end  834 . In some embodiments, video front end  834  receives pipeline commands from the command streamer  803 . In some embodiments, media pipeline  830  includes a separate command streamer. In some embodiments, video front-end  834  processes media commands before sending the command to the media engine  837 . In some embodiments, media engine  337  includes thread spawning functionality to spawn threads for dispatch to thread execution logic  850  via thread dispatcher  831 . 
         [0130]    In some embodiments, graphics processor  800  includes a display engine  840 . In some embodiments, display engine  840  is external to processor  800  and couples with the graphics processor via the ring interconnect  802 , or some other interconnect bus or fabric. In some embodiments, display engine  840  includes a 2D engine  841  and a display controller  843 . In some embodiments, display engine  840  contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller  843  couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector. 
         [0131]    In some embodiments, graphics pipeline  820  and media pipeline  830  are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct3D library from the Microsoft Corporation, or support may be provided to both OpenGL and D3D. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor. 
         [0132]      FIG. 14A  is a block diagram illustrating a graphics processor command format  900  according to some embodiments.  FIG. 14B  is a block diagram illustrating a graphics processor command sequence  910  according to an embodiment. The solid lined boxes in  FIG. 14A  illustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format  900  of  FIG. 14A  includes data fields to identify a target client  902  of the command, a command operation code (opcode)  904 , and the relevant data  906  for the command. A sub-opcode  905  and a command size  908  are also included in some commands. 
         [0133]    In some embodiments, client  902  specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcode  904  and, if present, sub-opcode  905  to determine the operation to perform. The client unit performs the command using information in data field  906 . For some commands an explicit command size  908  is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word. 
         [0134]    The flow diagram in  FIG. 14B  shows an exemplary graphics processor command sequence  910 . In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence. 
         [0135]    In some embodiments, the graphics processor command sequence  910  may begin with a pipeline flush command  912  to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline  922  and the media pipeline  924  do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command  912  can be used for pipeline synchronization or before placing the graphics processor into a low power state. 
         [0136]    In some embodiments, a pipeline select command  913  is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command  913  is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command is 912 is required immediately before a pipeline switch via the pipeline select command  913 . 
         [0137]    In some embodiments, a pipeline control command  914  configures a graphics pipeline for operation and is used to program the 3D pipeline  922  and the media pipeline  924 . In some embodiments, pipeline control command  914  configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command  914  is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands. 
         [0138]    In some embodiments, return buffer state commands  916  are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state  916  includes selecting the size and number of return buffers to use for a set of pipeline operations. 
         [0139]    The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination  920 , the command sequence is tailored to the 3D pipeline  922  beginning with the 3D pipeline state  930 , or the media pipeline  924  beginning at the media pipeline state  940 . 
         [0140]    The commands for the 3D pipeline state  930  include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based the particular 3D API in use. In some embodiments, 3D pipeline state  930  commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used. 
         [0141]    In some embodiments, 3D primitive  932  command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive  932  command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive  932  command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive  932  command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline  922  dispatches shader execution threads to graphics processor execution units. 
         [0142]    In some embodiments, 3D pipeline  922  is triggered via an execute  934  command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations. 
         [0143]    In some embodiments, the graphics processor command sequence  910  follows the media pipeline  924  path when performing media operations. In general, the specific use and manner of programming for the media pipeline  924  depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives. 
         [0144]    In some embodiments, media pipeline  924  is configured in a similar manner as the 3D pipeline  922 . A set of media pipeline state commands  940  are dispatched or placed into in a command queue before the media object commands  942 . In some embodiments, media pipeline state commands  940  include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, media pipeline state commands  940  also support the use one or more pointers to “indirect” state elements that contain a batch of state settings. 
         [0145]    In some embodiments, media object commands  942  supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command  942 . Once the pipeline state is configured and media object commands  942  are queued, the media pipeline  924  is triggered via an execute command  944  or an equivalent execute event (e.g., register write). Output from media pipeline  924  may then be post processed by operations provided by the 3D pipeline  922  or the media pipeline  924 . In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations. 
         [0146]      FIG. 15  illustrates exemplary graphics software architecture for a data processing system  1000  according to some embodiments. In some embodiments, software architecture includes a 3D graphics application  1010 , an operating system  1020 , and at least one processor  1030 . In some embodiments, processor  1030  includes a graphics processor  1032  and one or more general-purpose processor core(s)  1034 . The graphics application  1010  and operating system  1020  each execute in the system memory  1050  of the data processing system. 
         [0147]    In some embodiments, 3D graphics application  1010  contains one or more shader programs including shader instructions  1012 . The shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions  1014  in a machine language suitable for execution by the general-purpose processor core  1034 . The application also includes graphics objects  1016  defined by vertex data. 
         [0148]    In some embodiments, operating system  1020  is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. When the Direct3D API is in use, the operating system  1020  uses a front-end shader compiler  1024  to compile any shader instructions  1012  in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application  1010 . 
         [0149]    In some embodiments, user mode graphics driver  1026  contains a back-end shader compiler  1027  to convert the shader instructions  1012  into a hardware specific representation. When the OpenGL API is in use, shader instructions  1012  in the GLSL high-level language are passed to a user mode graphics driver  1026  for compilation. In some embodiments, user mode graphics driver  1026  uses operating system kernel mode functions  1028  to communicate with a kernel mode graphics driver  1029 . In some embodiments, kernel mode graphics driver  1029  communicates with graphics processor  1032  to dispatch commands and instructions. 
         [0150]    One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein. 
         [0151]      FIG. 16  is a block diagram illustrating an IP core development system  1100  that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system  1100  may be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility  1130  can generate a software simulation  1110  of an IP core design in a high level programming language (e.g., C/C++). The software simulation  1110  can be used to design, test, and verify the behavior of the IP core. A register transfer level (RTL) design can then be created or synthesized from the simulation model  1100 . The RTL design  1115  is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design  1115 , lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary. 
         [0152]    The RTL design  1115  or equivalent may be further synthesized by the design facility into a hardware model  1120 , which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3 rd  party fabrication facility  1165  using non-volatile memory  1140  (e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection  1150  or wireless connection  1160 . The fabrication facility  1165  may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein. 
         [0153]      FIG. 17  is a block diagram illustrating an exemplary system on a chip integrated circuit  1200  that may be fabricated using one or more IP cores, according to an embodiment. The exemplary integrated circuit includes one or more application processors  1205  (e.g., CPUs), at least one graphics processor  1210 , and may additionally include an image processor  1215  and/or a video processor  1220 , any of which may be a modular IP core from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic including a USB controller  1225 , UART controller  1230 , an SPI/SDIO controller  1235 , and an I 2 S/I 2 C controller  1240 . Additionally, the integrated circuit can include a display device  1245  coupled to one or more of a high-definition multimedia interface (HDMI) controller  1250  and a mobile industry processor interface (MIPI) display interface  1255 . Storage may be provided by a flash memory subsystem  1260  including flash memory and a flash memory controller. Memory interface may be provided via a memory controller  1265  for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine  1270 . 
         [0154]    Additionally, other logic and circuits may be included in the processor of integrated circuit  1200 , including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores. 
         [0155]    The following clauses and/or examples pertain to further embodiments: 
         [0156]    One example embodiment may be a method comprising defining, in hardware, a sampling region that is one texel smaller than a valid texel domain, and filtering a valid texel domain by always accessing only texels within the domain. The method may also include specifying texel values at texel corners. The method may also include computing an address for point sampling by scaling a normalized texture coordinate by a texture dimension minus 1 and then adding a 0.5 offset before truncating to the nearest texel. The method may also include defining a texture wrap mode to handle out-of-bounds coordinates without replicating edge texels. The method may also include implementing wrap modes by discerning between edge texels when crossing borders. The method may also include implementing a wrap mode by selecting which texel within the valid texel domain to use for out-of-bounds coordinates. The method may also include adjusting for a resolution reduction with corner addressing. The method may also include modifying mipmap sizes to account for a resolution reduction due to corner addressing. The method may also include calculating mipmap size L+1 by taking the half of a quantity floor of mipmap size L minus one and then adding one to the floor. The method may also include modifying the level of detail computation to account for a resolution reduction due to corner addressing. 
         [0157]    In another example embodiment one or more non-transitory computer readable media storing instructions executed by a processor to perform a sequence comprising defining a sampling region that is one texel smaller than a valid texel domain, and linearly filtering a valid texel domain by always accessing only texels within the domain. The media may also include said sequence including specifying texel values at texel corners. The media may also include said sequence including defining a texture wrap mode to handle out-of-bounds coordinates without replicating edge texels. The media may also include said sequence including computing an address for point sampling by scaling a normalized texture coordinate by a texture dimension minus 1 and then adding a 0.5 offset before truncating to the nearest texel. The media may also include said sequence including implementing a wrap mode by selecting which texel within the valid texel domain to use at the edges of the domain. The media may also include said sequence including adjusting for a resolution reduction with corner addressing. The media may also include said sequence including modifying mipmap sizes to account for a resolution reduction due to corner addressing. The media may also include said sequence including calculating mipmap size L+1 by taking the half of a quantity floor of mipmap size L minus one and then adding one to the floor. The media said sequence including modifying the level of detail computation to account for a resolution reduction due to corner addressing. The media may also include said sequence including implementing wrap modes by discerning between edge texels when crossing borders. 
         [0158]    Another example embodiment may be an apparatus comprising a processor to define a sampling region that is one texel smaller than a valid texel domain and linearly filter a valid texel domain by always accessing only texels within the domain, and a storage coupled to said processor. The apparatus may include said processor to specify texel values at texel corners. The apparatus may include said processor to define a texture wrap mode to handle out-of-bounds coordinates without replicating edge texels. The apparatus may include said processor to compute an address for point sampling by scaling a normalized texture coordinate by a texture dimension minus 1 and then add a 0.5 offset before truncating to the nearest texel. The apparatus may include said processor to implement a wrap mode by selecting which texel within the valid texel domain to use at the edges of the domain. The apparatus may include said processor to adjust for a resolution reduction with corner addressing. The apparatus may include said processor to modify mipmap sizes to account for a resolution reduction due to corner addressing. The apparatus may include said processor to calculate mipmap size L+1 by taking the half of a quantity floor of mipmap size L minus one and then add one to the floor. The apparatus may include said processor to modify the level of detail computation to account for a resolution reduction due to corner addressing. The apparatus may include said processor to implement wrap modes by discerning between edge texels when crossing borders. 
         [0159]    The graphics processing techniques described herein may be implemented in various hardware architectures. For example, graphics functionality may be integrated within a chipset. Alternatively, a discrete graphics processor may be used. As still another embodiment, the graphics functions may be implemented by a general purpose processor, including a multicore processor. 
         [0160]    References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present disclosure. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application. 
         [0161]    While a limited number of embodiments have been described, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this disclosure.