Abstract:
A discrete-time, single-amplifier, second-order, delta-sigma analog-to-digital converter (DT-SADS ADC) and a method of operating the same. The DT-SADS ADC combines switched-capacitor input sampling with switched-capacitor feedback and passive summing junction capacitor integration.

Description:
TECHNICAL FIELD OF THE INVENTION 
   The invention is directed, in general, to analog-to-digital converters (ADCs) and, more specifically, to a discrete-time, single-amplifier, second-order, delta-sigma ADC (DT-SADS ADC) and a method of operating the same. 
   BACKGROUND OF THE INVENTION 
   Mobile telephone technology has greatly advanced in recent years, as evident by the higher performance digital mobile telephones now available. To a large extent, these advances stem from the widespread deployment of modern digital wireless modulation technologies, such as time division multiple access (TDMA), code division multiple access (CDMA) technologies including conventional CDMA, wideband CDMA (WCDMA) and CDMA2000 standards and personal communications service (PCS) modulation. The carrier frequencies for these modulated signals ranges from on the order of 800 MHz to as high as 2.0 GHz. These and other digital modulation and communications techniques have greatly improved wireless telephone services, at reduced cost to the consumer. All of the aforementioned technologies require that signals be converted from analog to digital form. 
   An analog input signal can be converted into a digital output word using an analog-to-digital converter (ADC), which contains a mixture of analog and digital circuitry. The speed, resolution and linearity of the conversion affect the accuracy with which the digital output word represents the analog input signal. The conversion speed must be high enough to sample the shortest analog input signal period (highest analog signal frequency) at least twice. The number of bits in the digital output word determines the conversion resolution and has to be large enough to resolve the maximum peak-to-peak analog input signal into a required degree of granularity. The conversion linearity has to be sufficient to operate at or preferably below a required maximum level of distortion associated with the conversion process. 
   Several different algorithms and architectures exist that may be employed to accomplish a conversion. These include delta-sigma, successive approximation, pipeline and flash ADCs in increasing order of bandwidth capability but typically decreasing order of resolution capability. Of particular interest is the delta-sigma ADC, which typically provides a reasonable trade-off between sampling rate and bits of resolution while providing a low component count that benefits cost of production, size and reliability. 
   The delta-sigma (or sigma-delta) ADC employs delta-sigma modulation techniques that digitize an input signal using very low resolution (one-bit) and a very high sampling rate (often in the megahertz range). Oversampling and the use of digital filters increases the resolution to as many as twenty or more bits. It is especially useful for high resolution conversion of low to moderate frequency signals as well as low distortion conversion of signals containing audio frequencies due to its inherent qualities of good linearity and high accuracy. 
   Delta-sigma ADCs may operate in discrete time or continuous time. In either case, the delta-sigma ADC employs an input modulator and an output digital filter and decimator. The input modulator operates by accepting an input signal through an input summing junction, which feeds a loop filter. The loop filter basically provides an integrated value of this signal to a quantizer, which is typically implemented as a comparator. The quantizer output signal is fed back to the input summing junction through a circuit that acts as a one-bit digital-to-analog converter (DAC). This feedback loop forces the average of the feedback signal to be substantially equal to the input signal. The number of feedback loops in the loop filter (which is the same as the number of integrators) determines the order of the delta-sigma ADC. In the case of a one-bit quantizer, the density of “ones” in the quantizer output signal is proportional to the value of the input signal. The input modulator oversamples the input signal by clocking the comparator at a rate that is much higher than the Nyquist rate. Then, the output digital filter and decimator produce output data words at a data rate appropriate to the conversion. 
   Without careful optimization, existing discrete-time second-order order delta-sigma ADC designs that employ an amplifier in each integrator (a total of two amplifiers) often consume excessive integrated circuit (IC) chip area and power. Careful optimization can be time consuming and may require a mature process technology that has been thoroughly characterized. Reducing the number of amplifiers can result in reduced chip area and power consumption. Unfortunately, existing discrete-time second-order order delta-sigma ADC designs that employ fewer than two amplifiers are often vulnerable to real-world operating conditions, or “non-idealities,” such as mismatch, noise and non-linearity. 
   One existing discrete-time second-order order delta-sigma ADC design is the passive delta-sigma modulation (PDSM) ADC (see, e.g., Chen, et al., “A 0.25 mW 13-bit passive SD modulator for a 10 MHz IF input,” in ISSCC Dig. Tech. Papers, February 1996; and Chen, et al., “A 1.5V 1 mA 80 dB Passive SD ADC in 0.13 mm Digital CMOS Process,” in ISSCC Dig. Tech. Papers, February 2003). PSDM ADCs are subject to comparator offset and flicker-noise and excess delay in the feedback loop. Comparator offset and flicker-noise are typically reduced using offset storage cancellation, chopping or correlated double-sampling. Thermal noise must also be reduced, resulting in large high-current preamplifiers. Offset reduction techniques can consume too much power and area. Further, the timing the offset reduction techniques require may limit the maximum sample rate (F s ). Excess loop delay is avoided by requiring each preamplifier 3 dB-bandwidth to be greater than F s . Then, the feedback delay must be fixed and less than or equal to half of the sample period (T s =1/F s ). 
   Another existing discrete-time second-order order delta-sigma ADC design is the active-passive delta-sigma modulation (APDSM) ADC (see, e.g., U.S. Patent Publication No. 20050116850, “Continuous Time Fourth Order Delta Sigma Analog-to-Digital Converter;” and Das, et al., “A 4th-order 86 dB CT SD ADC with Two Amplifiers in 90 nm CMOS,” in ISSCC Dig. Tech. Papers, February 2005). APSDM ADCs are subject to resistor and capacitor absolute value variances and excess loop delay and parasitic poles. Variances in resistor and capacitor absolute value tend to cause large absolute ADC gain variations and the movement of poles and zeros, which degrades performance and stability. Counteracting these vulnerabilities requires extra circuitry to control the reference voltage so that the absolute gain of the ADC does not vary substantially, typically less than ±1 dB. Without this circuitry, the absolute gain may vary by as much as ±6 dB. Excess loop delay and parasitic poles vulnerabilities require the amplifier, comparator, and DAC to meet delay requirements over an expected range of F s . The feedback delay must be fixed and less than or equal to half of T s . Further, a loop delay compensation circuit may be required to reduce sensitivity to quantizer metastability, latch clock-to-Q time, and feedback DAC propagation delay. 
   Both PSDM and APSDM ADCs may require that the input common mode voltage be level-shifted for proper operation and reliability. This requires additional circuits for level-shifting, which consume additional chip area and power. 
   Yet another existing discrete-time second-order order delta-sigma ADC design is the single-amplifier delta-sigma modulation (SASD) ADC (see, e.g., U.S. Patent Publication No. 20040169596, “Higher Order Delta-sigma Analog-to-Digital Converter Based on Finite Impulse Response Filter;” and Koh, et al., “A 66 dB DR 1.2V 1.2 mW Single-Amplifier Double-Sampling second-order SD ADC for WCDMA in 90 nm CMOS” in ISSCC Dig. Tech. Papers, February 2005). SASD ADCs are subject to non-idealities in the linearity of amplification and gain, DC offset, limits on DC gain, gain-bandwidth product and slew rate, high input referred noise and sensitivity to capacitor mismatch, a data-dependent offset at the amplifier input in cases involving double sampling and increased total harmonic distortion. All of these can cause high-frequency noise to fold into the signal band and ultimately limit the achievable signal-to-noise ratio (SNR) and signal to noise-plus-distortion ratio (SNDR). 
   SUMMARY OF THE INVENTION 
   To address the above-discussed deficiencies of the prior art, one aspect of the invention provides a discrete-time, single-amplifier, second-order, delta-sigma ADC (DT-SADS ADC). In one embodiment, the converter includes: (1) a passive integrator unit having a passive input sampling circuit and a first passive feedback sampling circuit and a first passive summing junction coupling the passive input sampling circuit and the first passive feedback sampling circuit, (2) an active integrator unit coupled to an output of the passive integrator unit and having an active sampling circuit, a second passive feedback sampling circuit and a second passive summing junction coupling the active sampling circuit and the second passive feedback sampling circuit, (3) a quantizer coupled to an output of the active integrator unit, (4) a digital-to-analog converter coupled to an output of the quantizer and (5) a clock generator coupled to an output of the quantizer and configured to generate clock signals: (5a) concurrently to cause the passive input sampling circuit to gather samples from an input of the converter, cause the active sampling circuit to gather samples from the output of the passive integrator unit and cause the first and second passive feedback sampling circuits to gather samples from an output of the digital-to-analog converter and (5b) thereafter concurrently to cause the passive input sampling circuit and the first passive feedback sampling circuit to transfer the samples to the first passive summing junction and cause the active sampling circuit and the second passive feedback sampling circuit to transfer the samples to the second passive summing junction. 
   In another embodiment, the converter includes: (1) a passive integrator unit having an input capacitor and a first feedback capacitor and a first passive summing junction coupling the input capacitor and the first feedback capacitor, (2) an active integrator unit coupled to an output of the passive integrator unit and having an operational transconductance amplifier, a second feedback capacitor and a second passive summing junction coupling the operational transconductance amplifier and the second feedback capacitor, (3) a quantizer coupled to an output of the active integrator unit, (4) a digital-to-analog converter coupled to an output of the quantizer and (5) a clock generator coupled to an output of the quantizer and configured to generate clock signals: (5a) concurrently to cause the input capacitor to gather samples from an input of the converter, cause the operational transconductance amplifier to gather samples from the output of the passive integrator unit and cause the first and second feedback capacitors to gather samples from an output of the digital-to-analog converter and (5b) thereafter concurrently to cause the input capacitor and the first feedback capacitor to transfer the samples to the first passive summing junction and cause the operational transconductance amplifier and the second feedback capacitor to transfer the samples to the second passive summing junction. 
   Another aspect of the invention provides a method of operating a DT-SADS ADC having: (1) a passive integrator unit having a passive input sampling circuit and a first passive feedback sampling circuit and a first passive summing junction coupling the passive input sampling circuit and the first passive feedback sampling circuit, (2) an active integrator unit coupled to an output of the passive integrator unit and having an active sampling circuit, a second passive feedback sampling circuit and a second passive summing junction coupling the active sampling circuit and the second passive feedback sampling circuit, (3) a quantizer coupled to an output of the active integrator unit and (4) a digital-to-analog converter coupled to an output of the quantizer. In one embodiment, the method includes: (1) concurrently causing the passive input sampling circuit to gather samples from an input of the converter, the active sampling circuit to gather samples from the output of the passive integrator unit and the first and second passive feedback sampling circuits to gather samples from an output of the digital-to-analog converter and (2) thereafter concurrently causing the passive input sampling circuit and the first passive feedback sampling circuit to transfer the samples to the first passive summing junction and the active sampling circuit and the second passive feedback sampling circuit to transfer the samples to the second passive summing junction. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1A  is a block diagram of one embodiment of a DT-SADS ADC; 
       FIG. 1B  is a block diagram of the DT-SADS ADC of  FIG. 1A  setting forth schematic diagrams for one embodiment of passive and active integrator units therein; 
       FIG. 2  is a circuit diagram of one embodiment of the DT-SADS ADC of  FIG. 1A  further including one embodiment of a clock generator for the ADC and one embodiment of clock signal timing diagrams for the clock generator; 
       FIG. 3  is a circuit diagram of one embodiment of an operational transconductance amplifier for the DT-SADS ADC of  FIG. 1A ; 
       FIG. 4  is a flow diagram of one embodiment of a method of operating a DT-SADS ADC; 
       FIG. 5  sets forth Bode magnitude and phase plots of an approximate noise transfer function power spectral density for a simulation of a DT-SADS ADC using predetermined parameter values; 
       FIG. 6  is a Z-plane pole-zero plot for the DT-SADS ADC of  FIG. 5 ; and 
       FIG. 7  is a Bode magnitude plot of the output power spectral density of the DT-SADS ADC of  FIG. 5 . 
   

   DETAILED DESCRIPTION 
   Various embodiments to be illustrated and described are directed to a DT-SADS ADC in which switched-capacitor input sampling is combined with switched-capacitor feedback and passive summing junction capacitor integration. 
     FIG. 1A  is a block diagram of one embodiment of a DT-SADS ADC. The DT-SADS ADC receives an input signal X that has been low-pass filtered with a filter  102 . The DT-SADS ADC includes a passive integrator unit  110 , an active integrator unit  120 , a quantizer  130  and a DAC  140 . The passive integrator unit  110  contains a passive input sampling circuit  112  that receives and samples the input signal. The passive input sampling circuit  112  provides the sampled input signal to a first summing junction  114 . The output of the first summing junction  114  is stored in a first summing junction integrator  116 . A loop filter (which includes the DAC  140 ) contains first and second feedback loops. The first feedback loop feeds a feedback signal back to the passive integrator unit  110  through a first passive feedback sampling circuit  118 , where it is sampled and subtracted from the sampled input signal provided to the first summing junction  114  by the passive input sampling circuit  112 . 
   The active integrator unit  120  contains an active sampling circuit  122  that receives and samples the output of the passive integrator unit  110 . The active sampling circuit  122  provides the sampled output to a second summing junction  124 . The output of the second summing junction  124  is stored in a second summing junction integrator  126 . The second feedback loop of the loop filter feeds the feedback signal back to the active integrator unit  120  through a second passive feedback sampling circuit  128 , where it is sampled and subtracted from the sampled output provided to the second summing junction  124  by the active sampling circuit  122 . 
   The quantizer  130  is a single-bit quantizer. The quantizer  130  quantizes the output from the active integrator unit  120  into a one-bit output signal Y. In addition to constituting the output of the DT-SADS ADC, the output signal is provided to the DAC  140 , which provides the feedback signal that is fed back to the passive and active integrator units  110 ,  120 . As stated above, the density of “ones” in the output signal Y is proportional to the value of the input signal X. 
   In an alternative embodiment, the quantizer  130  is a multi-bit quantizer. The quantizer  130  quantizes the output from the active integrator unit  120  into a multi-bit output signal Y. As above, the output signal not only constitutes the output of the DT-SADS ADC, but is provided to the DAC  140 , which provides the feedback signal that is fed back to the passive and active integrator units  110 ,  120 . In this embodiment, Dynamic-Element-Matching (DEM) may be required to noise-shape or suppress any non-linear error due to capacitive mismatch with the DAC  140 . Two conventional DEM capacitive-matching techniques are Individual Level-Averaging (ILA) and Data-Weighted-Averaging (DWA). ILA is addressed in Leung, “Architectures for Multi-bit Oversampling A/D Converter Employing Dynamic Element Matching Techniques,” 1991 IEEE International Symposium on Circuits and Systems, pp. 1657-1660 (May, 1991). DWA is addressed in Baird, et al., “Improved ΔΣ DAC Linearity Using Data Weighted Averaging,” IEEE International Symposium on Circuits and Systems, pp. 13-16 (May, 1995), incorporated herein by reference. 
     FIG. 1B  is a block diagram of the DT-SADS ADC of  FIG. 1A  setting forth schematic diagrams for one embodiment of passive and active integrator units therein. The embodiment of  FIG. 1B  is single-ended. However, those skilled in the pertinent art will recognize that a differential DT-SADS ADC would typically be expected to provide superior rejection of common-mode noise and exhibit greater linearity. 
   The filter  102 , quantizer  130  and DAC  140  are represented the same as in  FIG. 1A . The passive integrator unit  110  and the active integrator unit  120  are instead illustrated as containing specific components that perform the functions described in conjunction with  FIG. 1A . 
   Regarding the passive integrator unit  110 , an input capacitor C S  acts as the passive input sampling circuit  112 . A summing junction capacitor C I1  acts as the first summing junction integrator  116 . A first feedback capacitor C DAC1  acts as the first passive feedback sampling circuit  118 . The output voltage, V o1 , of the passive integrator unit  110  is given by:
 
 V   o1 =1/(1 −L   1   z   −1 )·[ A   1   ·V   i1   −B   1   ·V   f ],
 
where L 1  is the leakage in the first summing junction integrator  116 , A 1  is an input coefficient, V i1  is the voltage of the filtered input signal X, B 1  is a feedback coefficient, and V f  is the reference voltage for the DAC  140 . L 1 , A 1  and B 1  are given as follows:
 
 L   1   =C   I1 /( C   I1   +C   S   +C   DAC1 ),
 
 A   1   =C   S   /C   I1 , and
 
 B   1   =C   DAC1   /C   I1 .
 
   The absolute gain, ABSG, of the passive integrator unit  110  is approximately the ratio of the feedback coefficient, B 1 , divided by the input coefficient, A 1 . Thus:
 
 ABSG≈C   DAC1   /C   S .
 
   The value of the passive integrating capacitor C I1  establishes the pole of the first feedback loop and removes the need for an amplifier in the passive integrator unit  110 . The transfer function of the first feedback loop is:
 
 H   1 ( z )=1/(1 −C   I1 /( C   I1   +C   S   +C   DAC1 )· z   −1 )
 
If C I1 &gt;&gt;C S +C DAC1 , then:
 
 H   1 ( z )≈1/(1 −z   −1 ).
 
   Turning to the active integrator unit  120 , an operational transconductance amplifier (OTA) G m  along with an integrating capacitor C I2  forms a transconductance-capacitance, (G m −C) integrator, which acts as the second summing junction integrator  126 . A second feedback capacitor C DAC2  acts as the second passive feedback sampling circuit  128 . The output voltage, V o2 , of the active integrator unit  120  is given by:
 
 V   O2 =1/(1 −L   2   z   −1 )·[ A   2   ·V   i2   −B   2   ·V   f ],
 
where L 2  is the leakage in the second summing junction integrator  126 , A 2  is an input coefficient, V i2 =V o1 , and B 2  is a feedback coefficient. L 2 , A 2  and B 2  are given as follows:
 
 L   2   =C   I2 /( C   I2   +C   Gm   +C   DAC2 ),
 
 A   2   =C   Gm   /C   I2 , and
 
 B   2   =C   DAC2   /C   I2 .
 
   The ABSG of the active integrator unit  120  is approximately the ratio of the feedback coefficient B 2  over the input coefficient A 2 . Thus:
 
 ABSG≈C   DAC2   /C   Gm .
 
   The OTA G m  of the illustrated embodiment does not experience significant input or output variations, even when the input signal X is full-scale. Consequently, G m  is not required to have a high slew-rate or a fast settling time. Instead, G m  has only to establish a non-dominant pole greater than the maximum sample rate, F s . In one embodiment, the input common mode of G m  is biased, e.g., using a switched-capacitor. 
   The transfer function of the first feedback loop is:
 
 H   2 ( z )= C   Gm   /C   I2 /(1−1/(1 +C   DAC2   /C   I2 ) z   −1 ).
 
If C I2 &gt;&gt;Cz, then:
 
 H   2 ( z )≈ C   Gm   /C   I2 /(1 −z   −1 ).
 
   One embodiment employs a relatively large summing junction capacitor, C I1 , and a large integration capacitor, C I2 , to reduce the input and output variation of the OTA G m  to decrease distortion. An alternative embodiment employs relatively small C I1  and C I2  to increase the input signal bandwidth the DT-SADS ADC can accommodate. 
   The signal transfer function (STF) for the DT-SADS ADC of  FIG. 2  is: 
             S   ⁢           ⁢   T   ⁢           ⁢   F     =           A   2     ·     A   1     ·     Z     -   1           1   +       (         A   2     ·     B   1       +     B   2     -     L   1     -     L   2       )     ⁢     z     -   1         +       (         L   1     ·     L   2       -       L   1     ·     B   2         )     ⁢     z     -   2             .           
The DC STF is:
   STF   DC   =ABSG =( A   1   ·A   2 )/(1+( A   2   ·B   1   +B   2   −L   1   −L   2 )+( L   1   ·L   2   −L   1   ·B   2 )) 
The noise transfer function (NTF) for the DT-SADS ADC of  FIG. 2  is:
 
             N   ⁢           ⁢   T   ⁢           ⁢   F     =         (     1   -       L   1     ·     z     -   1           )     ⁢     (     1   -       L   2     ·     z     -   1           )         1   +       (         A   2     ·     B   1       +     B   2     -     L   1     -     L   2       )     ⁢     z     -   1         +       (         L   1     ·     L   2       -       L   1     ·     B   2         )     ⁢     z     -   2                   
The STF and NTF poles for the loop filter of the DT-SADS ADC of  FIG. 2  are:
 
               P   1     =               -     (         A   2     *     B   1       +     B   2     -     L   1     -     L   2       )       -                     (         A   2     ·     B   1       +     B   2     -     L   1     -     L   2       )     2     -     4   ⁢     (         L   1     ·     L   2       -       L   1     ·     B   2         )                 2       ,   and                 P   2     =                 -     (         A   2     *     B   1       +     B   2     -     L   1     -     L   2       )       +                     (         A   2     ·     B   1       +     B   2     -     L   1     -     L   2       )     2     -     4   ⁢     (         L   1     ·     L   2       -       L   1     ·     B   2         )                 2     .           
The NTF zeroes for the loop filter of the DT-SADS ADC of  FIG. 2  are:
   Z   1   =L   1   =C   I1 /( C   I1   +C   S   +C   DAC1 ), and   Z   2   =L   2   =C   I2 /( C   I2   +C   DAC2 ). 
   As stated above, the DT-SADS ADC combines switched-capacitor input sampling with switched-capacitor feedback and passive summing junction capacitor integration. Accordingly, a first plurality of unreferenced switches interposes the input capacitor C S , the input of the passive integrator unit  110 , the first summing junction  114  and static voltage references. A second plurality of unreferenced switches interpose the first feedback capacitor C DAC1 , the DAC  140 , the first summing junction  114  and static voltage references. A third plurality of unreferenced switches interpose the second feedback capacitor C DAC2 , the DAC  140 , the second summing junction  124  and static voltage references. Though not shown in  FIG. 1B , a fourth plurality of switches are coupled to control inputs the OTA G m .  FIG. 4  will show the fourth plurality of switches. 
   The first, second and third pluralities of switches are labeled “ 1 ” and “ 2 ” to designate whether a clock signal Φ 1  or Φ 2 , or a variant of Φ 1  or Φ 2 , drives them. The clock signals Φ 1  and Φ 2  are non-overlapping. When Φ 1  is asserted, the first plurality of switches close to couple the input capacitor C S  between V i1  (the voltage of the filtered input signal X) and a static voltage reference, the second plurality of switches close to couple the first feedback capacitor C DAC1  between −V f  (the voltage of the feedback signal) and a static voltage reference, the third plurality of switches close to couple the second feedback capacitor C DAC2  between −V f  and a static voltage reference and the fourth plurality of switches close to couple an input of the OTA G m  to V i2 . While Φ 1  is asserted, C S  samples V i1 , G m  samples V i2 , and C DAC1  and C DAC2  sample −V f . The pluralities of switches driven by Φ 2  are of course open during assertion of Φ 1 . 
   When Φ 2  is asserted, the first plurality of switches close to couple the input capacitor C S  between the first summing node  114  and a static voltage reference, the second plurality of switches close to couple the first feedback capacitor C DAC1  between the first summing node  114  and a static voltage reference, the third plurality of switches close to couple the second feedback capacitor C DAC2  between the second summing node  124  and a static voltage reference and the fourth plurality of switches close to couple an output of the OTA G m  to the second summing node  124 . While Φ 2  is asserted, C S  delivers its sample of V i1  to the first summing node  114 , C DAC1  delivers its sample of −V f  to the first summing node  114 , C DAC2  delivers its sample of −V f  to the second summing node  124  and G m  delivers its sample of V i2  to the integrating capacitor C I2 . The pluralities of switches driven by Φ 1  are of course open during assertion of Φ 2 . 
   Thus, while Φ 2  is asserted, C I1  integrates the difference between the V i1  and V f  samples to yield V o1 , and C I2  integrates the difference between the sampled V i2  and V f  samples to yield V o2 . These integrated differences are passed on through the DT-SADS ADC: V o1  passes to the active integrator unit  120 , and V o2  passes to the quantizer  130 . 
     FIG. 2  is a circuit diagram of one embodiment of the DT-SADS ADC of  FIG. 1A  further including one embodiment of a non-overlapping clock generator  250  for the ADC and one embodiment of clock signal timing diagrams for the clock generator.  FIG. 2  shows a differential DT-SADS ADC having positive and negative rails. Therefore, V i1  becomes V i1+  and V i1−  and V f  becomes V f+  and V f− . Counterparts of C S , C I1  and C I2  are provided for each rail. 
   The clock generator  250  produces non-overlapping clock signals Φ 1 , Φ 1   d , Φ 2 , Φ 2   d , Φ 2 Y and Φ 2 Yz based on the output signal Y received from the quantizer  130  and a master clock signal MCLK.  FIG. 2  shows sample timing diagrams for Φ 1 , Φ 1   d , Φ 2  and Φ 2   d . It can be seen that Φ 1  and Φ 2  are non-overlapping. The rising edges of Φ 1   d  (a variant of Φ 1 ) coincide with those of Φ 1 , but the falling edges of Φ 1   d  are delayed with respect to those of Φ 1 . Likewise, the rising edges of Φ 2   d  (a variant of Φ 2 ) coincide with those of Φ 2 , and the falling edges of Φ 2   d  are delayed with respect to those of Φ 2 . The falling edges of Φ 1   d  and Φ 2   d  are delayed to ensure that samples are substantially transferred from C S , C DAC1  and C DAC2  forward through the DT-SADS ADC. 
   While Φ 1  is asserted, the input capacitors Cs sample V i1+  and V i1− , the OTA G m  samples the voltage of the summing junction capacitors C I1 , the first feedback capacitors C DAC1  sample V f+  and V f− , and the second feedback capacitors C DAC2  sample V f+  and V f− . While Φ 2  is asserted, the input capacitors C S  delivers their samples of V i1+  and V i1−  to the first summing node  114 , the first feedback capacitors C DAC1  delivers their samples of V f+  and V f−  to the first summing node  114 , the second feedback capacitors C DAC2  delivers their samples of V f+  and V f−  to the second summing node  124  and G m  delivers its samples of the voltage of the summing junction capacitors C I1  to the integrating capacitors C I2 . 
   Although not shown in  FIG. 2 , Φ 2 Y and Φ 2 Yz are always inverse to one another. Φ 2 Y is the same as Φ 2  if the output of the quantizer  130  is one, and Φ 2 Yz is the same as Φ 2  if the output of the quantizer  130  is zero. An asserted Φ 2 Y directly couples the positive-rail C DAC1  to the positive rail of the first summing junction  114 , the negative-rail C DAC1  to the negative rail of the first summing junction  114 , the positive-rail C DAC2  to the positive rail of the second summing junction  124  and the negative-rail C DAC2  to the negative rail of the second summing junction  124 . An asserted Φ 2 Yz cross-couples the positive-rail C DAC1  to the negative rail of the first summing junction  114 , the negative-rail C DAC1  to the positive rail of the first summing junction  114 , the positive-rail C DAC2  to the negative rail of the second summing junction  124  and the negative-rail C DAC2  to the positive rail of the second summing junction  124 . Φ 2 Y and Φ 2 Yz therefore ensure that the sign of the feedback signal is correct at the first and second summing nodes  114 ,  124 . 
     FIG. 3  is a circuit diagram of one embodiment of an OTA for the DT-SADS ADC of  FIG. 1A . The OTA has positive- and negative-rail inputs VIP and VIN and positive- and negative-rail outputs OUTP and OUTN.  FIG. 4  shows the fourth plurality of switches coupled to control inputs the OTA G m  and labeled to indicate that clock signals Φ 1  and Φ 2  drive them. 
   The OTA of  FIG. 3  employs a negative feedback loop to regulate its transconductance to the switched-capacitor conductance set by the switch-capacitor source-degeneration circuit. Thus, the effective transconductance of the OTA is equal to the sample rate, F S , multiplied by the capacitor C Gm , that is, G m =F S ·C Gm . The OTA therefore functions essentially as a G m −C integrator, which as stated above establishes the pole of the second feedback loop. 
   Capacitor ratios set the G m /C I2  frequency and OTA output variation. The OTA of  FIG. 3  operates according to the following relationships:
 
 G   m   =F   s   ·C   Gm  
 
 G   m   /C   I2   =F   s   ·C   Gm   /C   I2  
 
 H   2 ( s )= G   m /( s·C   I2 )= F   s   ·C   Gm /( s·C   I2 )= C   Gm   /C   I2 /( s·T   s )
 
 H   2 ( z )= G   m /( F   s   −C   I2 )/(1 −z   −1 )
 
 H   2 ( z )= F   s   ·C   Gm /( F   s   ·C   I2 )/(1 −z   −1 )
 
 H   2 ( z )= C   Gm   /C   I2 ·1/(1 −z   −1 )
 
     FIG. 4  is a flow diagram of one embodiment of a method of operating a DT-SADS ADC. The method begins in a start step  410 . In a step  420 , clock signals are generated, including Φ 1  and Φ 2  or variants thereof (i.e., Φ 1   d  and Φ 2   d ). In a step  430 , the passive input sampling circuit is caused to gather samples from an input of the converter. In a step  440 , the active sampling circuit is concurrently (with the step  430 ) caused to gather samples from the output of the passive integrator unit. In a step  450 , the first and second passive feedback sampling circuits are concurrently (with the steps  430  and  440 ) caused to gather samples from an output of the DAC. In a step  460 , the passive input sampling circuit and the first passive feedback sampling circuit are thereafter (after the steps  430 ,  440 ,  450 ) caused to transfer the samples to the first passive summing junction and the active sampling circuit. In a step  470 , the active sampling circuit and the second passive feedback sampling circuit are concurrently (with the step  460 ) caused to transfer the samples to the second passive summing junction. The method ends in an end step  480 . 
   A particular embodiment of the DT-SADS ADC was simulated using Simulink, which is commercially available from The MathWorks of Natick, Mass. Table 1 sets forth parameter values used in the simulation: 
   
     
       
             
           
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               Parameter Values Used in Simulation 
             
           
        
         
             
                 
               Parameter Name 
               Parameter Value 
               Units 
             
             
                 
                 
             
             
                 
               C S   
               100  
               fF 
             
             
                 
               C I1   
               20 
               pF 
             
             
                 
               C DAC1   
               100  
               fF 
             
             
                 
               C I2   
               10 
               pF 
             
             
                 
               C DAC2   
               50 
               fF 
             
             
                 
               C Gm   
               10 
               pF 
             
             
                 
               F S   
               500  
               MHz 
             
             
                 
               G m  = F S  * C Gm   
                5 
               mA/V 
             
             
                 
               N 
                   2 16   
               Samples 
             
             
                 
               fin1 
               66 * F S /N 
               kHz 
             
             
                 
               vref 
                1 
               V peak-differential 
             
             
                 
               Ain1 
               10 (−6/20)  · vref 
               V peak-differential 
             
             
                 
                 
             
           
        
       
     
   
     FIG. 5  sets forth Bode magnitude and phase plots of an approximate NTF power spectral density (PSD) for the simulation.  FIG. 6  is a Z-plane pole-zero plot for the simulation. 
     FIG. 7  is a Bode magnitude plot of the output power spectral density of the DT-SADS ADC of  FIG. 5 . No significant near harmonics (e.g., third harmonics) are apparent. The simulated DT-SADS ADC appears substantially linear. Table 2, below, sets forth SNDR for the simulated DT-SADS ADC for several input signal bandwidths. The SNDR appears good, even at wide bandwidths. 
   
     
       
             
           
             
             
             
           
             
             
             
           
         
             
               TABLE 2 
             
           
           
             
                 
             
             
               SNDR for Several Input Signal Bandwidths 
             
           
        
         
             
                 
               Signal Bandwidth (kHz) 
               SNDR (dB) 
             
             
                 
                 
             
           
        
         
             
                 
               200 
               110.16 
             
             
                 
               2500 
               79.23 
             
             
                 
               5000 
               64.79 
             
             
                 
               10000 
               49.82 
             
             
                 
               20000 
               35.21 
             
             
                 
                 
             
           
        
       
     
   
   Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the invention.