Abstract:
Switching mode power supplies and associated methods of control are disclosed herein. In one embodiment, a method for controlling a switching mode power supply includes determining whether the switching mode power supply is in a burst mode. If the switching mode power supply is in the burst mode, the method includes recording a switching time with and without switching pulses to obtain a current value of an equivalent frequency and generating a peak current limit that decreases as a load becomes lighter based on the equivalent frequency, thereby maintaining the equivalent frequency at the current value above an audible range. If the switching mode power supply is not in the burst mode, the method includes continuing to monitor whether the switching mode power supply is in the burst mode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
       [0001]    This application claims priority from Chinese Patent Application No. 200910306436.2, filed Sep. 1, 2009, which is incorporated herein by reference in its entirety. 
       TECHNICAL FIELD 
       [0002]    The present disclosure relates generally to switching mode power supplies and associated methods of control. 
       BACKGROUND 
       [0003]    Switching mode power supplies are used in various applications. Multi-mode control is widely adopted in switching mode power supplies because of the high conversion efficiency. Generally, the multi-mode control comprises a pulse skip mode, i.e., the so-called burst mode. However, if the switching mode power supply is under burst mode, the equivalent frequency becomes very low, which may generate audible noise if the equivalent frequency is lower than 20 kHZ. Thus there is a need to provide an improved switching mode power supply that can at least reduce or eliminate the audible noise under burst mode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0004]      FIG. 1  is a schematic diagram of a switching mode power supply in accordance with several embodiments of the technology. 
           [0005]      FIG. 2  is a schematic diagram of a controller suitable for use in the switching mode power supply of  FIG. 1  in accordance with several embodiments of the technology. 
           [0006]      FIG. 3  is a graph illustrating an example of multi-mode operation of the controller in  FIG. 2 . 
           [0007]      FIG. 4  shows a waveform of a switching signal used to control the switching circuit when the switching mode power supply in  FIG. 2  is in burst mode. 
           [0008]      FIG. 5  shows an example of a light load peak current processor suitable for use in the controller of  FIG. 2 . 
       
    
    
     DETAILED DESCRIPTION 
       [0009]    The present disclosure describes switch mode power supplies and associated methods of control. It will be appreciated that several of the details set forth below are provided to describe the following embodiments in a manner sufficient to enable a person skilled in the relevant art to make and use the disclosed embodiments. Several of the details and advantages described below, however, may not be necessary to practice certain embodiments of the invention. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to  FIGS. 1-5 . 
         [0010]      FIG. 1  is a schematic diagram of a switching mode power supply  100  in accordance with several embodiments of the technology. In one embodiment, the switching mode power supply  100  is configured as a flyback converter. The switching mode power supply  100  includes a rectifier bridge  101 , a transformer  102 , a feedback circuit  103 , a controller  104 , and a current sense resistor (R S ). 
         [0011]    The transformer  102 , in one embodiment, includes a primary winding  102 - 1 , a main secondary winding  102 - 2 , and an auxiliary secondary winding  102 - 3 . In operation, the rectifier bridge  101  receives an AC input signal (V IN ), and converts it into a DC signal received by the primary winding  102 - 1  of the transformer  102 . The transformer  102  is controlled by the controller  104  to generate DC output voltages on the secondary windings  102 - 2 ,  102 - 3  of the transformer  102 . The controller  104  controls the current flow through the primary winding  102 - 1  of the transformer to effectively switch the transformer  102  on and off. The main secondary winding  102 - 2  provides a DC output voltage (V OUT ) at the output node via a first diode (D 1 ) and an output capacitor (C OUT ). The auxiliary secondary winding  102 - 3  provides a DC voltage source (V CC ) to supply the controller  104  via a second diode (D 2 ), a resistor (R C ) and a capacitor (C 1 ). Also illustrated in  FIG. 1  is an input capacitor (C IN ) that stores and filters the DC input voltage. 
         [0012]    The feedback circuit  103  generates a feedback signal (V FB ) that is inversely proportional to the output voltage (V OUT ) on the main secondary winding  102 - 2  of the transformer  102 . In one embodiment, the feedback circuit  103  comprises an opto-coupler, a first feedback resistor (R FB1 ), a Zener diode (D 3 ), and a second feedback resistor (R FB2 ). As described in more detail below, the feedback signal is used by the controller  104  to control the switching frequency and the peak current of the switching regulator  100  as a function of the output voltage (V OUT ). The opto-coupler includes a photodiode  103 - 1  and a phototransistor  103 - 2 . In operation, the intensity of the light emitted by the photodiode  103 - 1  is inversely proportional to the output voltage (V OUT ). As the intensity of the photodiode  103 - 1  increases, so does the current flowing through the phototransistor  103 - 2 , which generates the feedback signal (V FB ) across the second feedback resistor (R FB2 ). Therefore, the feedback signal (V FB ) is inversely proportional to the output voltage (V OUT ), i.e., it increases as the output voltage (V OUT ) becomes lower and decreases as the output voltage (V OUT ) becomes higher. It should be understood, however, that in other embodiments the feedback circuit  103  and controller  104  may be configured such that the feedback signal (V FB ) is proportional to the output voltage (V OUT ) or otherwise varies in relation to the output voltage (V OUT ). 
         [0013]    The controller  104  includes a switching circuit that controls current flow through the primary winding  102 - 1  of the transformer  102 . The power supplied to the output node may thus be controlled by varying the frequency at which the switching circuit switches the current through the primary winding  102 - 1  on and off. This is commonly referred to as the switching frequency of the transformer. The controller  104  further includes a frequency control circuit that controls the switching frequency as a function of the feedback signal (V FB ), which is inversely proportional to the output voltage (V OUT ) on the transformer&#39;s main secondary winding  102 - 2 . In addition, the controller  104  includes a current limiting circuit that sets a peak current limit that may be proportional to the output voltage (V OUT ) by causing the switching circuit to suspend current flow through the primary winding  102 - 1  when the current reaches the peak current limit. In this way, both the switching frequency and the peak current limit may be regulated based on the output voltage (V OUT ) in order to improve system performance. For instance, the controller  104  may be configured to cause the switching frequency to decrease as the output voltage (V OUT ) becomes lower, and set the lowest switching frequency when the switching mode power supply enters burst mode. And the peak current limit may further decrease as the load becomes lighter when the switching mode power supply enters burst mode. The controller  104  may be further configured to set the peak current limit proportionally to the output voltage (V OUT ) so that a high efficiency at lighter loads and a high average efficiency is achieved and noises are eliminated in burst mode. 
         [0014]      FIG. 2  is a schematic diagram of a controller  200  suitable for use in the switching mode power supply  100  of  FIG. 1  in accordance with several embodiments of the technology. The controller  200  includes a switching circuit  230  (e.g., a MOSFET switch); a frequency control circuit  201 , a subtracter  202 , a burst mode control circuit  205 , a logical circuit  206 , a driver  207 , a mode transition circuit  209 , and a current limiting circuit  208 ,  210 . 
         [0015]    In one embodiment, the frequency control circuit  201  includes a current source (I S ), an electronic switch (S 1 ), a comparator (U 1 ), a Zener diode (D 4 ), and a resistor (R). The frequency control circuit  201  also includes an external capacitor (C 0 ) shown in  FIG. 1 . The electronic switch (S 1 ) is controlled to be on and off by the logical circuit  206 . When the electronic switch (S 1 ) is on, the voltage drop across the external capacitor (C 0 ) is reset to zero. When the electronic switch (S 1 ) is off, voltage drop across the external capacitor (C 0 ) increases because of the charge effect of the current source (I S ). When the voltage drop across the external capacitor (C 0 ) reaches the voltage at the inverting input terminal of the comparator (U 1 ), the comparator (U 1 ) outputs a high level signal to the logical circuit  206 , which will provide a logic signal to turn on the electronic switch (S 1 ). Thus the voltage drop across the external capacitor is reset again. 
         [0016]    In one embodiment, the burst mode control circuit  205  comprises a hysteresis comparator which receives a voltage reference (V ref ) at one input terminal and receives the output signal (V SUB −V FB ) of the subtracter  202  at the other input terminal. The logical circuit  206  comprises a RS flip-flop (U 5 ), which receives the output signal of the frequency control circuit  201  at its set terminal (S), and receives the output signal of the current limiting circuit at its reset terminal (R). The logical circuit  206  further comprises an AND gate (U 0 ) which receives the output signal (Q) of the RS flip-flop at its first input terminal, and receives a burst mode signal provided by the burst mode control circuit  205  at its second input terminal. 
         [0017]    In one embodiment, the current limiting circuit  208  includes an oscillator (U 2 ) which provides oscillation signals, a pulse processor (U 3 ), and a light load peak current processor (U 4 ). In one embodiment, the oscillator (U 2 ) provides oscillation signals only when the switching mode power supply enters burst mode. The pulse processor (U 3 ) receives the oscillation signals and the logical signal, and provides pulse processed signal (V CL ) based thereupon. The light load peak current processor (U 4 ) receives the pulse processed signal (V CL ), and provides a light load peak current processed signal (V th ) based thereupon. The current limiting circuit  210  includes a comparator  204 , which is coupled to the switch circuit  230  via a leading edge blanking circuit (LEB); a peak current reference judging circuit  203 , which receives a voltage reference (V sense ) in one input terminal, and receives the light load peak current processed signal (V th ) or the output signal (V SUB −V FB ) of the subtracter  202  via a status switch (S 2 ) at the other input terminal, and provides a peak current limit (V ir ) based thereupon. 
         [0018]    In one embodiment, the LEB circuit is a known circuit that reduces spikes in the signal by introducing a short delay. It should be understood, however, that in other embodiments there could be no LEB circuit. In one embodiment, the peak current reference judging circuit  203  compares the two input signals and selects the lower one to be its output signal, i.e., the peak current limit (V ir ). The mode transition circuit  209  receives the burst mode signal and provides a mode control signal to control the status switch (S 2 ) to be coupled to the output of the light load peak current processor (U 4 ) or to the output of the subtracter. In one embodiment, when the burst mode signal indicates that the switching mode power supply enters burst mode, the status switch (S 2 ) is controlled to be coupled to the output of the light load peak current processor (U 4 ); when the burst mode signal indicates that the switching mode power supply is not under burst mode, the status switch (S 2 ) is controlled to be coupled to the output of the subtracter. 
         [0019]    During operation of the switching mode power supply, if the load varies, i.e., the output voltage (V OUT ) varies, the feedback signal (V FB ) varies accordingly which is inversely proportional to the output voltage (V OUT ) as illustrated hereinbefore. As a result, when the load becomes lighter, the switching mode power supply will enter the following modes as depicted in  FIG. 3 : 
         [0020]    (1): when the load is heavy, the feedback signal is low. The feedback signal increases as the load decreases. However, at first the feedback signal (V FB ) may be lower than the Zener diode (D 4 ) breakdown voltage (V D4 ), and the output signal (V SUB −V FB ) of the subtracter  202  may be higher than the voltage reference (V sense ) and the low limit (V BRL ) of the hysteresis comparator, i.e., V FB &lt;V D4 , V SUB −V FB &gt;V sense , V SUB −V FB &gt;V BRL . As a result, the burst mode control circuit  205  indicates that the switching mode power supply is not under burst mode. 
         [0021]    On one hand, the status switch (S 2 ) is controlled to be coupled to the output of the subtracter  202 . Because VSUB−VFB&gt;Vsense, the peak current reference judging circuit  203  selects the voltage reference (Vsense) as the peak current limit (Vir). Thus the peak current limit (Vir) is constant during this mode. On the other hand, the voltage at the inverting input terminal of the comparator (U 1 ) of the frequency control circuit  201  is the feedback signal (VFB). So the switching frequency (fs) of the switching mode power supply is: 
         [0000]    
       
         
           
             
               f 
               s 
             
             = 
             
               
                 1 
                 
                   T 
                   charge 
                 
               
               = 
               
                 
                   1 
                   
                     
                       
                         C 
                         0 
                       
                       × 
                       
                         V 
                         FB 
                       
                     
                     
                       I 
                       s 
                     
                   
                 
                 = 
                 
                   
                     I 
                     s 
                   
                   
                     
                       C 
                       0 
                     
                     × 
                     
                       V 
                       FB 
                     
                   
                 
               
             
           
         
       
     
         [0022]    As a result, the switching frequency (f s ) of the switching mode power supply decreases as the feedback signal (V FB ) increases, i.e., as the load becomes lighter. The switching mode power supply is under mode I when the switching frequency varies as a function of the feedback signal and the peak current limit is constant. 
         [0023]    (2): the load continues to be lighter, so the feedback signal (V FB ) keeps increasing. When the output signal (V SUB −V FB ) of the subtracter  202  is lower than the voltage sense (V sense ), but still higher than the low limit (V BRL ) of the hysteresis comparator, and the feedback signal (V FB ) is still lower than the Zener diode (D 4 ) break down voltage (V D4 ), i.e., V FB &lt;V D4 , V SUB −V FB &lt;V sense , V SUB −V FB &gt;V BRL , the switching mode power supply enters mode II. The status switch (S 2 ) is still coupled to the output of the subtracter  202 . In this mode, because the output signal (V SUB −V FB ) of the subtracter  202  is lower than the voltage sense (V sense ), the peak current reference judging circuit  203  selects the output signal (V SUB −V FB ) of the subtracter  202  as the peak current limit (V ir ). As a result, the peak current limit (V ir ) decreases as the load becomes lighter. The voltage at the inverting input terminal of the comparator (U 1 ) of the frequency control circuit  201  is still the feedback signal (V FB ). So the switching frequency (f s ) of the switching mode power supply also decreases as the load becomes lighter. That is, in mode II, both the switching frequency and the peak current limit vary as a function of the feedback signal. 
         [0024]    (3): the load continues to be further lighter, the feedback signal (V FB ) keeps increasing. When the feedback signal (V FB ) goes higher than the Zener diode (D 4 ) break down voltage (V D4 ), and the output signal (V SUB −V FB ) of the subtracter  202  is lower than the voltage sense (V sense ), but still higher than the low limit (V BRL ) of the hysteresis comparator, i.e., V FB &gt;V D4 , V SUB −V FB &lt;V sense , V SUB −V FB &gt;V BRL , the switching mode power supply enters mode III. The status switch (S 2 ) is still coupled to the output of the subtracter  202  because V SUB −V FB &gt;V BRL . In this mode, because the output signal (V SUB −V FB ) of the subtracter  202  is lower than the voltage sense (V sense ), the peak current reference judging circuit  203  selects the output signal (V SUB −V FB ) of the subtracter  202  as the peak current limit (V ir ). As a result, the peak current limit (V ir ) decreases as the load becomes lighter. The voltage at the inverting input terminal of the comparator (U 1 ) of the frequency control circuit  201  changes to the Zener diode (D 4 ) break down voltage (V D4 ). So the switching frequency (f s ) of the switching mode power supply is: 
         [0000]    
       
         
           
             
               f 
               s 
             
             = 
             
               
                 1 
                 
                   T 
                   charge 
                 
               
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                   1 
                   
                     
                       
                         C 
                         0 
                       
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                         V 
                         
                           D 
                            
                           
                               
                           
                            
                           4 
                         
                       
                     
                     
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                       s 
                     
                   
                 
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                     s 
                   
                   
                     
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                       0 
                     
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                       V 
                       
                         D 
                          
                         
                             
                         
                          
                         4 
                       
                     
                   
                 
               
             
           
         
       
     
         [0000]    As a result, the switching frequency (f s ) of the switching mode power supply keeps constant and the load becomes lighter during this mode. That is, in mode III, the peak current limit varies as a function of the feedback signal and the switching frequency is constant. 
         [0025]    (4): the load continues to be further lighter, the feedback signal (V FB ) keeps increasing. When the feedback signal (V FB ) goes higher than the Zener diode (D 4 ) break down voltage (V D4 ), and the output signal (V SUB −V FB ) of the subtracter  202  is lower than the voltage sense (V sense ) and the low limit (V BRL ) of the hysteresis comparator, i.e., V FB &gt;V D4 , V SUB −V FB &lt;V sense , V SUB −V FB &lt;V BRL , the burst mode control circuit  205  indicates that the switching mode power supply enters burst mode. Accordingly, the status switch (S 2 ) is controlled to be coupled to the output of the light load peak current processor (U 4 ). During this mode, the lowest value of the switching frequency of the switching mode power supply is limited, and the peak current limit (V ir ) decreases as the load becomes lighter as described in more detail below. 
         [0026]      FIG. 4  shows a waveform of the switching signal used to control the switching circuit  230  when the switching mode power supply in  FIG. 2  is in burst mode. In  FIG. 4 , the y-axis represents the switching signal, and the x-axis represents time (t). In addition, Ts is the switching cycle of the switching mode power supply, X is the switching number when there is switching cycles, while Y is the switching number when there is no switching cycles. Thus, the equivalent frequency (f eq ) of the switching mode power supply is: 
         [0000]    
       
         
           
             
               f 
               eq 
             
             = 
             
               
                 X 
                 
                   X 
                   + 
                   Y 
                 
               
               × 
               
                 1 
                 
                   T 
                   s 
                 
               
             
           
         
       
     
         [0027]    For traditional burst mode control, X decreases and Y increases as the load becomes lighter. As a result, the equivalent frequency (f eq ) becomes lower as the load becomes lighter. When it falls into the audible frequency (i.e., 20 kHZ), noise is introduced. However, the embodiments in the technology can at least reduce or prevent the equivalent frequency (f eq ) from dropping into the audible range by further reducing the peak current limit when the switching mode power supply is in burst mode. 
         [0028]    Specifically, when the switching mode power supply enters burst mode, the oscillator (U 2 ) outputs a series of instructions to the pulse processor (U 3 ), so that the pulse processor (U 3 ) starts to sense the switching signals, and record X and Y to get the equivalent frequency (f eq ). The pulse processor (U 3 ) further compares X, Y, and the equivalent frequency (f eq ) with preset X set , Y set , and f eqset . In one embodiment, if the equivalent frequency f eq  is lower than the preset frequency f eqset , the pulse processed signal (V CL ) increases; if the equivalent frequency f eq  is higher than the preset frequency f eqset , the pulse processed signal (V CL ) decreases. The pulse processor (U 3 ) then provides the pulse processed signal (V CL ) to the light load peak current processor (U 4 ), so as to get the light load peak current processed signal (V th ) which varies inversely to the pulse processed signal (V CL ). By such regulation, X is regulated to the preset X set , Y is regulated to the preset Y set , and f eq  is regulated to the preset f eqset  when the load is rather light. The operation of the light load peak current processor (U 4 ) will be described in more detail below. 
         [0029]      FIG. 5  depicts an example of a light load peak current processor  300  suitable for use in the controller  200  of  FIG. 2 . In one embodiment, the light load peak current processor  300  comprises a first amplifier (A 1 ), a second amplifier (A 2 ), six transistors (Q 1 ˜Q 6 ), and three resistors (R 1 ˜R 3 ). Wherein the first transistor (Q 1 ), the second transistor (Q 2 ), the third transistor (Q 3 ), and the fourth transistor (Q 4 ) are p-channel transistors; the fifth transistor (Q 5 ) and the sixth transistor (Q 6 ) are n-channel transistors. The non-inverting input terminal of the first amplifier (A 1 ) is coupled to the pulse processed signal (V CL ), the inverting input terminal of the first amplifier (A 1 ) is coupled to the emitter of the fifth transistor (Q 5 ), and the output terminal of the first amplifier (A 1 ) is coupled to the base of the fifth transistor (Q 5 ). The first resistor (R 1 ) is coupled between the inverting input terminal of the first amplifier (A 1 ) and ground. That is, the first amplifier (A 1 ), the first resistor (R 1 ), and the fifth transistor (Q 5 ) form a voltage follower. The collector of the fifth transistor (Q 5 ) is coupled to the collector of the first transistor (Q 1 ). The first transistor (Q 1 ) and the second transistor (Q 2 ) form a first current mirror, wherein the current ratio of the current flow through the first transistor (Q 1 ) and the second transistor (Q 2 ) is 1:m. 
         [0030]    The third transistor (Q 3 ) and the fourth transistor (Q 4 ) form a second current mirror, wherein the current ratio of the current flow through the third transistor (Q 3 ) and the fourth transistor (Q 4 ) is 1:n. The second amplifier (A 2 ), the sixth transistor (Q 6 ), and the second resistor (R 2 ) forms a second voltage follower. The non-inverting input terminal of the second amplifier (A 2 ) is coupled to a second voltage reference (V R ). The collector of the sixth transistor (Q 6 ) is coupled to the collectors of the second transistor (Q 2 ) and the third transistor (Q 3 ). The third resistor (R 3 ) is coupled between the collector of the fourth transistor (Q 4 ) and ground. The voltage drop across the third resistor (R 3 ) is the output signal of the light load peak current processor  300 , i.e., it is the light load peak current processed signal (V th ). 
         [0031]    As shown in  FIG. 5 , the current flow through the first transistor (Q 1 ) is equal to the current flow through the first resistor (R 1 ), i.e., 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     1 
                   
                   = 
                   
                     
                       V 
                       CL 
                     
                     
                       R 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0000]    The current flow through the sixth transistor (Q 6 ) is the sum of the current flow through the second transistor (Q 2 ) and the current flow through the third transistor (Q 3 ), i.e., 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       I 
                       6 
                     
                     = 
                     
                       
                         
                           V 
                           R 
                         
                         
                           R 
                           2 
                         
                       
                       = 
                       
                         
                           I 
                           2 
                         
                         + 
                         
                           I 
                           3 
                         
                       
                     
                   
                    
                   
                     
 
                   
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                   And 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     2 
                   
                   = 
                   
                     m 
                     × 
                     
                       I 
                       1 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       I 
                       4 
                     
                     = 
                     
                       n 
                       × 
                       
                         I 
                         3 
                       
                     
                   
                    
                   
                     
 
                   
                    
                   Then 
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     th 
                   
                   = 
                   
                     
                       
                         I 
                         4 
                       
                       × 
                       
                         R 
                         3 
                       
                     
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                         n 
                         × 
                         
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                           3 
                         
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                           3 
                         
                       
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                         × 
                         
                           ( 
                           
                             
                               
                                 V 
                                 R 
                               
                               
                                 R 
                                 2 
                               
                             
                             - 
                             
                               m 
                               × 
                               
                                 
                                   V 
                                   CL 
                                 
                                 
                                   R 
                                   1 
                                 
                               
                             
                           
                           ) 
                         
                         × 
                         
                           R 
                           3 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0000]    If the resistance of the first resistor (R 1 ), the second resistor (R 2 ), and the third resistor (R 3 ) are same, i.e., R 1 =R 2 =R 3 , and assume m=1, n=1, the equation (5) becomes: 
         [0000]        V   th   =V   R   −V   CL   (6)
 
         [0032]    From equation (6), it can be seen that the light load peak current processed signal (V th ) is inversely proportional to the pulse processed signal (V CL ). As illustrated hereinbefore, the pulse processed signal (V CL ) is inversely proportional to the equivalent frequency (f eq ). So the light load peak current processed signal (V th ) is proportional to the equivalent frequency (f eq ). If the equivalent frequency (f eq ) becomes lower, so does the light load peak current processed signal (V th ). 
         [0033]    In addition, the light load peak current processed signal (V th ) is lower than the voltage reference (V sense ) at this time. So the peak current reference judging circuit  203  selects the light load peak current processed signal (V th ) as the peak current limit (V ir ). That is, the peak current limit of the switching mode power supply decreases as the load becomes further lighter. In this way, the equivalent frequency (f eq ) increases, which avoids audible noises. When the switching mode power supply exits burst mode, the status switch (S 2 ) is controlled to be coupled to the output of the subtracter  202  by the mode transition circuit  209 . Then the switching mode power supply enters mode I, mode II, or mode III. 
         [0034]    From the foregoing, it will be appreciated that specific embodiments of the disclosure have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, many of the members of one embodiment may be combined with other embodiments in addition to or in lieu of the members of the other embodiments. Accordingly, the disclosure is not limited except as by the appended claims.