Abstract:
Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. In some embodiments, a memory cell comprises a silicon carbide structure including a charge reservoir configured to store an amount of charge carriers constituting a charge cloud. The amount of charge carriers in the charge cloud can represent a data value. Further, the memory cell includes a resistive element in communication with the charge reservoir and is configured to provide a resistance as a function of the amount of charge carriers in the charge reservoir. The charge reservoir is configured to modulate the size of the charge cloud to change the data value.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/138,505, filed Dec. 17, 2008 and entitled “Memory Cell Reading Using a Charge Controlled Resistor,” and is related to U.S. Pat. No. 7,362,609, issued Apr. 22, 2008, and entitled “Memory Cell,” U.S. Non-provisional application Ser. No. 12/543,473, filed Aug. 18, 2009, entitled “Substrates and Methods of Fabricating Epitaxial Silicon Carbide Structures With Sequential Emphasis,” and U.S. Non-provisional application Ser. No. 12/543,478, filed Aug. 18, 2009, entitled “Substrates and Methods of Fabricating Doped Epitaxial Silicon Carbide Structures With Sequential Emphasis,” all of which are incorporated herein by reference for all purposes. 
     
    
     FIELD 
       [0002]    Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods for using silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. 
       BACKGROUND 
       [0003]    A variety of conventional memory cells structures have been developed in various memory technologies. Silicon carbide has been identified recently as a material that can be used in structures that can retain data in a non-volatile manner. While silicon carbide and methods of implementing the same have been used in conventional semiconductor devices, such as in light emitting devices (“LEDs”) devices and high power switching devices, the traditional techniques and structures of using silicon carbide may not be well-suited for non-volatile memory devices that implement memory cells based on silicon carbide material. So while conventional memory array and memory cell structures are functional, they may not be well-suited to create memory arrays and cells based on silicon carbide material. 
         [0004]    It is desirable to provide improved techniques, systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with devices, integrated circuits, substrates, and methods of retaining data in memory cells and array structures using conventional techniques. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0005]    The various embodiments of the invention are more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which: 
           [0006]      FIG. 1  is a diagram depicting an example of a charge-controlled resistor with a silicon carbide-based memory element, according to various embodiments of the invention; 
           [0007]      FIG. 2A  is a diagram depicting an example of a functional model of a charge-controlled resistor configured to provide read data stored therein, according to at least some embodiments of the invention; 
           [0008]      FIGS. 2B and 2C  are diagrams depicting examples of functional models to describe the modulation of a charge cloud, according to at least some embodiments of the invention; 
           [0009]      FIG. 3  is a diagram depicting an example of a diode structure as a charge storage portion of a memory element, according to at least some embodiments of the invention; 
           [0010]      FIGS. 4A to 4C  depict the modification of at least one barrier in a diode structure to transition from an equilibrium state to a non-equilibrium state, according to some embodiments of the invention; 
           [0011]      FIG. 5  is a diagram depicting an example of a charge-controlled resistor based on a silicon carbide-based memory element, according to various embodiments of the invention; 
           [0012]      FIGS. 6A and 6B  depict examples of the charge-controlled resistor of  FIG. 5  in a non-equilibrium state and an equilibrium state, respectively, according to some embodiments of the invention; 
           [0013]      FIGS. 7A and 7B  depict examples of the charge-controlled resistor of  FIG. 5  transitioning between a non-equilibrium state and an equilibrium state, according to some embodiments of the invention; 
           [0014]      FIG. 8  depicts an example of a memory cell including multiple charge-controlled resistors, according to some embodiments of the invention; 
           [0015]      FIG. 9  depicts an example of a portion of a memory array that includes the memory cell of  FIG. 8 , according to some embodiments of the invention; 
           [0016]      FIG. 10  is a top view depicting an example for a portion of a memory array that includes the memory cell of  FIG. 8 , according to some embodiments of the invention; 
           [0017]      FIG. 11A  is a schematic diagram of a portion of an array including charge-controlled resistors, according to some embodiments; 
           [0018]      FIGS. 11B and 11C  depict schematic representations of a charge-controlled resistor, according to some embodiments; and 
           [0019]      FIG. 12  is a diagram of configurations for programming and erasing charge-controlled resistors, according to various embodiments. 
       
    
    
       [0020]    Like reference numerals refer to corresponding parts throughout the several views of the drawings. Note that most of the reference numerals include one or two left-most digits that generally identify the figure that first introduces that reference number. 
       DETAILED DESCRIPTION 
       [0021]    Various embodiments or examples of the invention may be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical, electronic, or wireless communication links. In general, operations of disclosed processes may be performed in an arbitrary order, unless otherwise provided in the claims. 
         [0022]    A detailed description of one or more examples is provided below along with accompanying figures. The detailed description is provided in connection with such examples, but is not limited to any particular example. The scope is limited only by the claims, and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided as examples and the described techniques may be practiced according to the claims without some or all of the accompanying details. For clarity, technical material that is known in the technical fields related to the examples has not been described in detail to avoid unnecessarily obscuring the description. 
         [0023]      FIG. 1  is a diagram depicting an example of a charge-controlled resistor with a silicon carbide-based memory element, according to various embodiments of the invention. In the example shown in diagram  100 , a charge-controlled resistor  110  includes a resistive element  120  and a memory element  130  composed of silicon carbide, and has three terminals: a terminal  102 , a terminal  104 , and a terminal  106 . Note that while  FIG. 1  depicts three terminals, the charge-controlled resistor is not limited to three terminals, according to various other embodiments. Memory element  130  is coupled between terminals  102  and  106  and includes a charge reservoir  132  and a charge cloud modulator  134 . Charge reservoir  132  is a portion of a silicon carbide structure configured to store an amount of charge carriers (i.e., mobile charge carriers) in the form of a charge cloud (“cloud”)  136 . Charge cloud modulator  134  is configured to modulate the size of the charge cloud  136  to, for example, change the amount of charge carriers in charge cloud  136 . In various embodiments, charge cloud  136  represents a memory state and the size of charge cloud  136  can be representative of a data value stored in memory element  130 . The term “size” can refer to a spatial volume of charge carriers, a density of charge carriers in charge reservoir  132 , an amount of charge carriers, and the like, according to various embodiments. Resistive element  120  is coupled to memory element  130  and is configured to provide a resistance as function of the amount of charge carriers in charge cloud  136 . To illustrate, consider that resistive element  120  can provide a first resistance (“R 1 ”)  122  and a second resistance (“R 2 ”)  124  as a function of a first size of charge cloud  136  and a second size of charge cloud  136 , respectively. As an example, the first size of charge cloud  136  is greater than the second size, whereby the first size provides for first resistance  122 , which is indicative of a first memory state. The second size of charge cloud  136  provides for second resistance  124 , which is indicative of a second memory state. In some instances, first resistance  122  is greater than second resistance  124 . Thus, multiple resistance states of resistive element  120  can indicate multiple memory states stored in association with charge reservoir  132 . 
         [0024]    In some embodiments, memory element  130  can be implemented using a silicon carbide diode structure  140 , which can be a PN structure, a PNP structure, or an equivalent thereof. In examples that include a PNP structure, diode structure  140  includes a diode  142   a  and a diode  142   b , both of which include silicon carbide. For example, diode  142   a  can be formed to include a p-type silicon carbide structure and an n-type silicon carbide structure with a P-N junction formed in between, and diode  142   b  can include the n-type silicon carbide structure common with diode  142   a  and another p-type silicon carbide structure to form a P-N junction in between. One or more P-N junctions and/or energy barrier heights or widths of diode structure  140  can be configured to provide at least one barrier configured to substantially prevent charge carrier transport in association with charge reservoir  132  to maintain the data value in a first mode of operation. During the first mode of operation, a read voltage level can be applied to terminal  102  and a current indicative of the memory state (i.e., the size of charge cloud  136 ) stored in memory element  130  can be detected at terminal  104 . In some embodiments, the first mode of operation can be an “off” mode of operation whereby the one or more barriers (and barrier heights) are maintained to prevent charge carriers from leaving or entering charge cloud  136 . 
         [0025]    Charge cloud modulator  134  includes the structures and/or functionalities of at least the barriers and/or P-N junctions, according to some embodiments. Charge cloud modulator  134  is configured to modulate the amount of charge carriers in charge cloud  136  in a second mode of operation. In some embodiments, the second mode of operation can be an “on” mode of operation whereby the one or more barriers are reduced to facilitate transport of charge carriers to enter or leave charge cloud  136 . Charge cloud modulator  134  can operate responsive to potential differences applied across terminals  102  and  106 . To store a first memory state in memory element  130 , a negative voltage programming potential difference is applied across terminals  102  and  106  (e.g., a negative voltage is applied to terminal  102  relative to terminal  106 ) to add charge carriers for increasing the size of charge cloud  136 . By contrast, a positive voltage programming potential difference is applied across terminals  102  and  106  (e.g., a positive voltage is applied to terminal  102  relative to terminal  106 ) to remove charge carriers for reducing the size of charge cloud  136 . Note that while the above-referenced memory element  130  is described as having two memory states, memory element  130  can be configured to store more than two memory states (i.e., memory element  130  can store more than two logical data values), according to at least some embodiments. 
         [0026]    In some embodiments, resistive element  120  can be implemented as resistive element  150 , which can include resistive material  154  disposed between contacts  152   a  and  152   b . The resistive material  154  can include a homogenous semiconductor material, such as a layer of polysilicon. For example, the homogenous semiconductor material includes the same type of doping, such as n-type doping, and a relatively consistent doping concentration in resistive material  154 . As such, a homogenous semiconductor material including a layer of n-type polysilicon excludes doped regions, such as doped source and drain regions, according to at least some embodiments. Contacts  152   a  and  152   b  can coincide with terminals  103  and  104 , respectively. In the example shown, terminals  102  and  103  are a common terminal. As such, terminal  102  can be configured to couple to a bit line of a memory array (not shown), terminal  106  can be configured to couple to a word line, and terminal  104  can be configured to couple to a source line, according to some embodiments. 
         [0027]      FIG. 2A  is a diagram depicting an example of a functional model of a charge-controlled resistor configured to provide read data stored therein, according to at least some embodiments of the invention. Charge-controlled resistor  200  is shown to include a diode device (e.g., a PNP diode) including P-N structures  204   a  and  204   b . Terminal  202  is used to apply either a negative or a positive voltage programming potential difference across P-N structures  204   a  and  204   b  to modulate an amount of charge stored in at least one of P-N structures  204   a  and  204   b . The amount of stored charge influences the resistance of resistive element  206 . Therefore, charge-controlled resistor  200  can generate a first current (“I 1 ”)  208   a  to indicate a first memory state and a second current (“I 2 ”)  208   b  to indicate a second memory state. 
         [0028]      FIGS. 2B and 2C  are diagrams depicting examples of functional models to describe the modulation of a charge cloud, according to at least some embodiments of the invention.  FIG. 2B  illustrates that a charge-controlled resistor (and/or a memory element) can be modeled as functional model  220  during an “on” mode of operation in which charge carriers, q, are added to a charge cloud. As shown, functional model  220  includes a silicon carbide diode  224  having a terminal  222  (e.g., a word line terminal coupled to a word line) at which a first voltage is applied to add charge carriers, q, to capacitor  226  (e.g., a metal-oxide semiconductor, or “MOS” capacitor, or an equivalent thereof). In some cases, capacitor  226  models the functionality of a charge cloud. In  FIG. 2B , diode  224  is operating in a “forward on” mode in accordance with some embodiments.  FIG. 2C  illustrates that the charge-controlled resistor (and/or the memory element) can be modeled as functional model  240  during an “on” mode of operation in which charge carriers, q, are removed from a charge cloud. As shown, functional model  240  includes a silicon carbide diode  244  having a terminal  242  (e.g., a word line terminal coupled to a word line) at which a second voltage is applied to remove charge carriers, q, from capacitor  246 . In some cases, capacitor  246  models the functionality of a charge cloud. Note that while in some examples, capacitors  226  and  246  are MOS capacitors and are elements of charge-controlled resistors, capacitors  226  and  246  of models  220  and  240  also can represent the charge storing functionalities of charge-controlled resistors, according to some embodiments. As such, capacitors  226  and  246  can model the functionality of, for example, p-type silicon carbide material operating as a charge reservoir. 
         [0029]      FIG. 3  is a diagram depicting an example of a diode structure as a charge storage portion of a memory element, according to at least some embodiments of the invention. Diode structure  300  is shown as a PNP diode structure disposed between a terminal  301   a  and a terminal  301   b . The PNP structure includes a p-type silicon carbide structure  306 , which can be formed upon a substrate (e.g., a silicon substrate, such as a p-type silicon substrate), according to some embodiments. Further, an n-type silicon carbide structure  304  is formed on top of p-type silicon carbide structure  306 , and another p-type silicon carbide structure  302  is formed on top of n-type silicon carbide structure  304 . PNP diode structure  300  also includes two P-N junctions  340  and  342  that can facilitate the formation of barriers (e.g., energy barriers) configured to prevent charge carriers from traversing within the diode structure, as well as into or out from the diode structure. A barrier can prevent charge carrier transport either between terminals  301   a  and  301   b  or between n-type and p-type silicon carbide structures, according to some embodiments. Further, a barrier can prevent charge carrier transport into or out from diode structure  300 , according to some embodiments. Thus, a barrier in PNP diode structure  300  can provide for storage of memory states in association with charge clouds  310  and  312 . In some embodiments, one or both of P-N junctions  340  and  342 , and/or one or more barriers operate as a charge cloud modulator  134  of  FIG. 1 . 
         [0030]    Charge clouds  310  and  312  can be referred to as “hole clouds” as the charge clouds are formed in PNP diode structure  300 . Charge cloud  310  is established by adding holes as charge carriers, q, to p-type silicon carbide structure  302  by placing PNP diode structure  300  in a “forward on” mode of operation. In the “forward on” mode, holes can be added to the storage region by applying a negative voltage to terminal  301   a  relative to terminal  301   b . In some cases, recombination and thermal emission are absent, and, as such, the tunneling of holes out of the storage region can be minimized or eliminated so as not to disturb the memory state. That is, the energy-barrier widths (or heights) can be configured to minimize or avoid tunneling. 
         [0031]    With negative voltage applied to terminal  301   a , the barriers are reduced to enable charge carriers (“q”)  370  to traverse P-N junctions  340  and  342  and/or the barriers. Charge carriers  370  can originate, for example, in a p-type silicon substrate (not shown). Once charge cloud  310  accepts as many holes as it can or until PNP diode structure  300  otherwise is transitioned out from “forward on” mode, then PNP diode structure  300  can be place into an “equilibrium” state. 
         [0032]    Charge cloud  312  is established by removing holes as charge carriers, q, from p-type silicon carbide structure  302  by placing PNP diode structure  300  in a “reverse on” mode of operation. In the “reverse on” mode, holes can be removed from the storage region by applying a positive voltage to terminal  301   a  relative to terminal  301   b . In some cases, recombination and thermal emission are absent, and, as such, the tunneling of holes into the storage region can be minimized or eliminated so as not to disturb the memory state. For instance, the energy-barrier widths (or heights) can be configured to minimize or avoid tunneling. With positive voltage applied to terminal  301   a , the barriers are reduced to enable charge carriers (“q”)  372  to traverse P-N junctions  340  and  342  and/or the barriers. Charge carriers  372  can be transported via terminal  301   b  into, for example, a p-type silicon substrate (not shown). Once charge cloud  312  loses as many holes as it can or until PNP diode structure  300  otherwise is transitioned out from “reverse on” mode, then PNP diode structure  300  is placed into a “non-equilibrium” state. As charge cloud  310  is larger than charge cloud  312 , charge cloud  310  has a greater amount of hole carriers than does charge cloud  312 . 
         [0033]    In some embodiments, p-type silicon carbide structure  302 , n-type silicon carbide structure  304 , and p-type silicon carbide structure  306  are formed using 3C Silicon Carbide. Note that the n-type and p-type silicon carbide structures need not be limited to 3C SiC, and can implement other types of silicon carbide (e.g., 4H or 6H SiC) in other implementations. P-type silicon carbide structures  302  and  306  can be formed with doping concentrations of p-type carriers between, for example, 10 15  to 10 19  per cm 3 . In one example, doping concentrations of p-type carriers can be between, for example, 6×10 16  to 2×10 17  per cm 3 . Further, the thicknesses of p-type silicon carbide structures  302  and  306  can have thicknesses within a range of 20 nm to 600 nm, or greater. N-type silicon carbide structure  304  can be formed with doping concentrations of n-type carriers between, for example, 10 15  to 10 19  per cm 3 , and can have a thickness within a range of 20 nm to 600 nm, or greater. In some embodiments, p-type silicon carbide structures  302  and  306  and n-type silicon carbide structure  304  can be formed as set forth in one or more of the following: U.S. patent application Ser. No. 12/543,473, filed on Aug. 18, 2009, and titled “Substrates and Methods of Fabricating Epitaxial Silicon Carbide Structures with Sequential Emphasis,” and U.S. patent application Ser. No. 12/543,478, filed on Aug. 18, 2009, and title “Substrates and Methods of Fabricating Doped Epitaxial Silicon Carbide Structures with Sequential Emphasis,” both of which are hereby incorporated by reference. 
         [0034]    In some embodiments, PNP diode structure  300  is formed to provide at least one barrier of about 1.6 eV, or greater, in an “off” mode of operation to reduce the thermal emission to a level that corresponds, for example, to duration of approximately 10 years at 85° C. during which a memory state is retained. The holes in 3C SiC can be separated from the electrons in metals, such as a control gate (e.g., a bit line) and n-type 3C SiC in n-type silicon carbide structure  304  by barriers that are greater than 1.6 eV. Among other things, the p-type and n-type doping concentrations and thicknesses can be established in a manner that minimizes or eliminates hole current by way of tunneling, according to some embodiments. Note that in one embodiment, a current (e.g., a leakage current) can flow along the sides (e.g., internally and/or externally) of PNP diode structure  300  along a current path  330 , or any current path in a path region  390 . The magnitude of the current is a function of the amount of charge stored in p-type silicon carbide structure  302 , and, as such, can be indicative of the memory state. In one embodiment, PNP diode structure  300  can be implemented as a portion of a two-terminal memory cell. While  FIG. 3  depicts a PNP diode structure, the various embodiments of the invention are not so limited and can include an NPN diode or equivalent diode structures. 
         [0035]      FIGS. 4A to 4C  depict the modification of at least one barrier in a diode structure to transition from an equilibrium state to a non-equilibrium state, according to some embodiments of the invention. Note that the band energy diagrams shown in  FIGS. 4A to 4C  are for discussion purposes to illustrate examples of modifying barriers to prevent charge carrier transport. The band energy diagrams are not intended to be limiting and are illustrative of the operation of a silicon carbide diode; there are many other band energy diagrams for different PNP and NPN silicon carbide diode configurations. In  FIG. 4A , diagram  400  shows a PNP diode structure  401  in an equilibrium state and a corresponding band energy diagram  410  for band energies associated with the portions of PNP diode structure  401 , according to some embodiments. Band energy diagram  410  shows energies (“Ec”)  412  of the conduction levels, Fermi energy levels (“Ef”)  411 , and energies (“Ev”)  414  of the valence levels for the portions of PNP diode structure  401 . PNP diode structure  401  is formed between terminals  402   a  and  402   b , and includes a p-type silicon carbide structure (“P-SiC”)  408 , an n-type silicon carbide structure (“N-SiC”)  406 , and a p-type silicon carbide structure (“P-SiC”)  404 . Note that PNP diode structure  401  can be coupled directly or indirectly (e.g., via an oxide or a substrate) to terminals  402   a  and  402   b . Also formed are P-N junctions  405  and  407 . Further, p-type silicon carbide structure  404  has a thickness  422 , n-type silicon carbide structure  406  has a thickness  424 , and p-type silicon carbide structure  408  has a thickness  426 . Omitted from  FIG. 4A  are a gate dielectric or oxide (“Ox”) having a thickness of  420  formed upon the top PNP diode structure  401 , and a substrate having at least a partial thickness  428 . In a specific embodiment, and by way of example only, the substrate can be formed as a p + -type silicon substrate having a p-type doping concentration of 10 18  per cm 3 , and p-type silicon carbide structure  408  can be formed to have a thickness of 50 nm and a p-type doping concentration of 5×10 17  per cm 3 , or greater. Further, n-type silicon carbide structure  406  can be formed to have a thickness of 240 nm and an n-type doping concentration from 2×10 17  to 3×10 17  per cm 3 , and p-type silicon carbide structure  404  can be formed to have a thickness of 200 nm and a p-type doping concentration of 5×10 17  per cm 3 , or greater. 
         [0036]    As shown, at least p-type silicon carbide structure  404  includes a charge cloud  403  having a size indicative of being in an equilibrium state. In some examples, when PNP diode structure  401  is in an equilibrium state, PNP diode structure  401  is considered “programmed.” Further to the example shown in  FIG. 4A , consider that PNP diode structure  401  is in an “off” mode of operation. As such, at least one energy barrier is formed as the difference, X eV, between a valence energy level  417  (for n-type silicon carbide structure  406 ) and a valence energy level  415  (for p-type silicon carbide structure  404 ). As the difference X eV is greater than 1.6 eV, at least one barrier in PNP diode structure  401  is sufficient to retain charge in charge cloud  403  for approximately 10 years at 85 degrees Centigrade, as an example. In one example, X eV is 2.0 eV, which is greater than a barrier height of 1.6 eV. Note that in some embodiments, p-type silicon carbide structure  408  can include another charge cloud  370  that need not modulate as described herein. 
         [0037]      FIG. 4B  is a diagram  430  showing PNP diode structure  401  transitioning from an equilibrium state to a non-equilibrium state, according to some embodiments. In particular, a negative voltage is being applied to terminal  402   a  relative to terminal  402   b  in an “on” mode of operation, which, in turn, reduces the size of charge cloud  433 .  FIG. 4B  also includes a band energy diagram  440  of band energies associated with the portions of PNP diode structure  401  in “on” mode, according to some embodiments. Band energy diagram  440  shows energies (“Ec”)  442  of the conduction levels, Fermi energy levels (“Ef”)  441   a  and  441   b , and energies (“Ev”)  444  of the valence levels for portions of PNP diode structure  401 . The negative programming voltage alters the band energies to reduce a barrier height having a barrier difference, Y eV, which corresponds to a difference between a valence energy level  447  for n-type silicon carbide structure  406  and a valence energy level  445  for p-type silicon carbide structure  404 . As the difference Y eV is less than 1.6 eV, a barrier in PNP diode structure  401  is reduced sufficiently to remove hole carriers  439  from charge cloud  433 . In one example, Y eV is 1.0 eV, which is less than a barrier height of 1.6 eV. 
         [0038]      FIG. 4C  is a diagram  460  showing PNP diode structure  401  in a non-equilibrium state, according to some embodiments. In particular, the negative voltage that had been previously applied in  FIG. 4B  is absent at terminal  402   a , and PNP diode structure  401  in  FIG. 4C  is returned to an “off” mode of operation.  FIG. 4C  also includes a band energy diagram  470  of band energies associated with the portions of PNP diode structure  401  when PNP diode structure  401  is in an “off” mode operation and in a non-equilibrium state. In the non-equilibrium state, or “erased” state, charge cloud  463  has a reduced size, and p-type silicon carbide structure  404  includes a depleted region of negative acceptors  490 , which are immobile charge ions (i.e., negatively charged ions). Such immobile charge ions are configured to facilitate generation of an electric field. Band energy diagram  470  shows energies (“Ec”)  472  of the conduction levels, Fermi energy levels (“Ef”)  471   a  and  471   b , and energies (“Ev”)  474  of the valence levels for portions of PNP diode structure  401 . At least one energy barrier is formed to have a barrier difference, Z eV, which corresponds to a difference between a valence energy level  477  for n-type silicon carbide structure  406  and a valence energy level  475  for p-type silicon carbide structure  404 . As the difference, Z eV, is greater than 1.6 eV, a barrier in PNP diode structure  401  has a sufficient barrier height to retain charge in charge cloud  463  for approximately 10 years at 85 degrees Centigrade, as an example. In one example, Z eV is 2.8 eV, which is greater than a barrier height of 1.6 eV. Further to this example, another difference between valence energy level  477  for n-type silicon carbide structure  406  and a valence energy level  479  for a silicon substrate is greater than 1.6 eV, according to some embodiments. As such, a hole carrier  469  from the silicon substrate may face a barrier at either the P-SiC/Si Substrate interface  480  or at the P-SiC/N-SiC interface  407 , or both. Thus, the hole carrier  469  does not traverse to charge cloud  463 . In other embodiments, diode structure  401  can transition from the non-equilibrium state in  FIG. 4C  to the equilibrium state in  FIG. 4A  in a similar, but reverse manner. 
         [0039]      FIG. 5  is a diagram depicting an example of a charge-controlled resistor based on a silicon carbide-based memory element, according to various embodiments of the invention. Charge-controlled resistor  500  includes a PNP diode structure formed to include a p-type silicon carbide structure (“P-type SiC”)  516  having a charge cloud  580  that need not modulate as described herein, an n-type silicon carbide structure (“N-type SiC”)  514 , and a p-type silicon carbide structure (“P-type SiC”)  512  having a charge cloud  510 . Also formed are P-N junctions  513  and  515 . Charge-controlled resistor  500  is shown also to reside on a terminus region  590 , which can be a semiconductor substrate (e.g., an n-type or p-type silicon substrate, or any other kind of suitable substrate) or any other semiconductor-related surface, including a word line. Further, an oxide  506  is formed on the PNP structure, and, in turn, a polysilicon layer  504  is formed thereon. In some embodiments, oxide  506  operates as a gate dielectric and is formed as a silicon dioxide (SiO 2 ) layer. In at least some embodiments, oxide  506  can be referred to as a charge-controlled resistor (“CCR”) gate. Charge cloud  510  is configured to modify the resistance of a conductive path  580  between a first contact  502   a  (e.g., a bit line) and a second contact  502   b  (e.g., a source line). In some embodiments, metal contacts  502   a  and  502   b  to polysilicon  504  are sufficient, thereby obviating a requirement for doped source and drain regions. As such, doped source and drain regions are optional. A homogeneous polysilicon layer reduces or eliminates an increase in the “off” mode current and variability of the current that might otherwise be caused by lateral diffusion of source and drain dopants in, for example, a structure similar to a Thin Film Transistor (“TFT”). 
         [0040]      FIGS. 6A and 6B  depict examples of the charge-controlled resistor of  FIG. 5  in a non-equilibrium state and an equilibrium state, respectively, according to some embodiments of the invention.  FIG. 6A  depicts charge-controlled resistor  500  being in a non-equilibrium state (e.g., an erased state) in which a charge cloud  610  has a reduced size. The relatively small size of charge cloud  610  gives rise to a depleted region of negative acceptors  605   b  (e.g., negatively-charged immobile ions) in p-type silicon carbide structure  512 . The depleted region of negative acceptors  605   b  induces an electric field  608  that crosses oxide  506  into a depleted region of positive donors  605   a  (e.g., positively-charged immobile ions) in poly-silicon  504 . By forming electric field  608  with negative acceptors  605   b  and positive donors  605   a  disposed on different sides of oxide  506 , interface-related issues and leakage through oxide  506  may be minimized or eliminated. The depleted region of positive donors  605   a  in poly-silicon  504  increases the resistance of the conductive path  580  of  FIG. 5 , thereby placing charge-controlled resistor  500  in a high resistance state. Thus, poly-silicon  504 , as a resistive element, has a relatively high resistance between contacts  502   a  and  502   b  responsive to the memory state associated with charge cloud  610 . A read voltage applied to contact  502   a  generates a current at contact  502   b  indicative of the memory state. In some embodiments, a read voltage is less than the “on” mode voltages, such as the negative and positive programming voltages that reduce the barriers in the PNP diode structure. In at least one embodiment, induced electric field  608  in polysilicon  504  may also deplete mobile charges in grain boundaries, thereby creating a lower current in an “off” mode of operation of charge-controlled resistor  500 . 
         [0041]      FIG. 6B  depicts charge-controlled resistor  500  being in an equilibrium state (e.g., a programmed state) in which a charge cloud  660  has an enhanced size. The relatively large size of charge cloud  660  reduces or eliminates the depleted region of negative acceptors  605   b  in p-type silicon carbide structure  512 , thereby reducing the resistance of the conductive path  580  of  FIG. 5 . Therefore, charge-controlled resistor  500  of  FIG. 6B  is in a low resistance state as poly-silicon  504 , as a resistive element, has a relatively low resistance between contacts  502   a  and  502   b.    
         [0042]      FIGS. 7A and 7B  depict examples of the charge-controlled resistor of  FIG. 5  transitioning between a non-equilibrium state and an equilibrium state, according to some embodiments of the invention.  FIG. 7A  depicts charge-controlled resistor  500  being transitioned from an equilibrium state (e.g., a programmed state) to a non-equilibrium state (e.g., an erased state) in “reverse on” mode by applying a positive programming voltage, +V, to contact  502   a  (e.g., a bit line) relative to terminus region  590  (e.g., a word line) to remove holes  719  from charge cloud  710  until the size is reduced sufficiently to change the memory state.  FIG. 7B  depicts charge-controlled resistor  500  being transitioned from a non-equilibrium state (e.g., an erased state) to an equilibrium state (e.g., a programmed state) in “forward on” mode by applying a negative programming voltage, −V, to contact  502   a  relative to terminus region  590  to add holes  759  to charge cloud  760  from, for example, a silicon substrate until the size is enhanced to change the memory state. 
         [0043]      FIG. 8  depicts an example of a memory cell including multiple charge-controlled resistors, according to some embodiments of the invention. In the example shown, memory cell  800  includes a charge-controlled resistor  802   a  and another charge-controlled resistor  802   b . Charge-controlled resistor  802   a  is formed between a bit line  810   a  and a source line  812 , and charge-controlled resistor  802   b  is formed between source line  812  and a bit line  810   b . Charge-controlled resistor  802   a  includes a memory element  880   a  disposed on a substrate  890 , and a channel  811   a  of polysilicon  814  as a resistive element. Charge-controlled resistor  802   b  includes a memory element  880   b  disposed on substrate  890 , and a channel  811   b  of polysilicon  814  as another resistive element. Memory element  880   a  includes a portion of an oxide  816  and a PNP diode structure including a p-type silicon carbide structure (“P-SiC”)  822   a  having a charge cloud (“CC”)  840 , an n-type silicon carbide structure (“N-SiC”)  824   a , and a p-type silicon carbide structure (“P + -SiC”)  826   a  having a charge cloud (“CC”)  842  and a word line  818   a  formed as a part of p-type silicon carbide structure  826   a . Similarly, memory element  880   b  includes a portion of oxide  816  and a PNP diode structure including a p-type silicon carbide structure (“P-SiC”)  822   b  having a charge cloud (“CC”)  844 , an n-type silicon carbide structure (“N-SiC”)  824   b , and a p-type silicon carbide structure (“P + -SiC”)  826   b  having a charge cloud (“CC”)  846  and a word line  818   b  formed as a part of p-type silicon carbide structure  826   b . As charge cloud (“CC”)  844  is relatively large, charge-controlled resistor  802   b  is an equilibrium state, and, therefore, conductive path  813   b  has a relatively low resistance, whereas conductive path  813   a  has a relatively high resistance as charge cloud  840  is relatively small and charge-controlled resistor  802   b  is a non-equilibrium state. 
         [0044]      FIG. 9  depicts an example of a portion of a memory array that includes the memory cell of  FIG. 8 , according to some embodiments of the invention. Array portion  900  includes charge-controlled resistors  950  disposed on a substrate  990 . Array portion  900  also includes memory cell  800  that includes charge-controlled resistors  802   a  and  802   b  of  FIG. 8 , which includes word lines  918   a  and  918   b , respectively. Memory cell  800  is coupled to source line (“SL”)  912   b  and to bit lines contacts  910   b  and  910   c . Bit line contact  910   b  is coupled to an odd bit line (e.g., 2n−1), and is not shown, whereas bit line contact  910   c  is coupled to an even bit line (e.g., 2n)  913 , which is formed on an insulator  915 . Another bit line contact  910   a  is also coupled to bit line  913 . Other source lines  9112   a  and  912   c  are formed on top of polysilicon  914 . Charge-controlled resistors  950  include a portion of polysilicon  914 , an oxide  916 , and a PNP diode structure including a p-type silicon carbide structure (“P-SiC”)  922 , an n-type silicon carbide structure (“N-SiC”)  924 , and a p-type silicon carbide structure (“P-SiC”)  926 . 
         [0045]      FIG. 10  is a top view depicting an example of a portion of a memory array that includes the memory cell of  FIG. 8 , according to some embodiments of the invention. Memory cell  800  includes a source line contact (“SL”)  1024  coupled to source line  1004   a . Source line contact  1024  corresponds to source line (“SL”)  912   b  of  FIG. 9 . Contacts  1022   a  and  1022   b  for respective charge-controlled resistors (“CCR”)  802   a  and  802   b  are coupled to word lines  1002   a  and  1002   b , respectively. A contact  1026  couples bit line  1010   a  to bit line contact  910   c  of  FIG. 9 , whereas a contact  1020  couples bit line  1010   b  to bit line contact  910   b  of  FIG. 9 . As is observed in  FIGS. 9 and 10 , memory cell  800  corresponds to a cell area of 4F 2 , according to some embodiments. 
         [0046]      FIG. 11A  is a schematic diagram for a portion of an array including charge-controlled resistors, according to some embodiments. Array portion  1100  is a NOR-type array and includes a number of word lines (“WL”)  1102   a  to  1102   d , a number of bit lines (“BL”)  1110   a  to  1110   d , and a number of source lines (“SL”)  1004   a  and  1004   b . Charge-controlled resistors  1122  are disposed at the intersections of a word line  1102 , a bit line  1110  and a source line  1004 .  FIG. 11B  depicts a schematic representation of a charge-controlled resistor  1130  having a word line (“WL”) terminal  1132 , a bit line (“BL”) terminal  1134 , and a source line terminal  1136 , whereas  FIG. 11C  depicts another schematic representation of a charged-controlled resistor  1140  including a word line (“WL”) terminal  1142 , a bit line (“BL”) terminal  1144  and a source line terminal  1146 . 
         [0047]      FIG. 12  is a diagram of configurations for programming and erasing charge-controlled resistors, according to various embodiments. To program charged-controlled resistor  1122   a , programming voltages can be applied as described in programming legend  1230 , whereas charged-controlled resistor (“CCR”)  1122   a  can be erased by applying erasing voltages in programming legend  1232 . The programming and erasing voltages are supplied to charged-controlled resistor  1122   a  via word line (“WL”)  1202  and bit line (“BL”)  1210   c . An example of a voltage, V F , is shown in programming legend  1234 . 
         [0048]    The various embodiments of the invention can be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical or electronic communication links. In general, the steps of disclosed processes can be performed in an arbitrary order, unless otherwise provided in the claims. 
         [0049]    The foregoing description, for purposes of explanation, uses specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. In fact, this description should not be read to limit any feature or aspect of the present invention to any embodiment; rather features and aspects of one embodiment can readily be interchanged with other embodiments. Notably, not every benefit described herein need be realized by each embodiment of the present invention; rather any specific embodiment can provide one or more of the advantages discussed above. In the claims, elements and/or operations do not imply any particular order of operation, unless explicitly stated in the claims. It is intended that the following claims and their equivalents define the scope of the invention.