Abstract:
A variable frequency oscillator is disclosed which is electronically and periodically swept from one frequency to another. Prior to the beginning of each sweep, the variable frequency oscillator is phase locked to a reference signal source and the error voltage in the phase lock loop is stored. When the sweep begins the phase lock loop is opened and the error voltage is summed with a sweep voltage to provide for correction of oscillator drift on a sweep by sweep basis.

Description:
BACKGROUND OF THE INVENTION 
     Many electronic devices such as spectrum analyzers use swept frequency oscillators as local oscillators in order to repeatedly tune over a particular band of frequencies. One of the drawbacks of analog sweep oscillators is that they drift in frequency, and this lack of stability in the local oscillator is reflected in the lack of stability in the frequency readout of the spectrum analyzer. This problem has been solved in the past by using a local oscillator which is synthesized or digitally swept in discreet steps. This, however, has the disadvantage that it is much more expensive than an analog swept oscillator and the sweep has a number of steps in it rather than being one, smooth, continuous curve. 
     Other prior art spectrum analyzers have attempted to overcome the problem of instability in the first local oscillator by phase locking the first local oscillator to a fixed reference and then sweeping one of the lower frequency local oscillators over a narrower band. Since the lower frequency local oscillator has greater stability than the broad frequency range first local oscillator frequency instabilities are reduced. An example of this technique is shown in U.S. Pat. No. 3,482,181. 
     Another technique for stabilizing a swept frequency oscillator is shown in U.S. Pat. No. 3,144,623 in which the sweeping oscillator is injection locked at the start of the sweep and nulls are counted during the sweep for correction of the oscillator frequency. One of the disadvantages of this technique is that because no error voltage is stored there is a discontinuity at the start of the sweep until the loop corrects the oscillator. This closed loop sweeping technique uses a considerable amount of circuitry for linearity correction which, with some oscillators and for some applications, is unnecessary and thus unjustifiably expensive. 
     SUMMARY OF THE INVENTION 
     According to a preferred embodiment of the present invention an electronically tunable variable frequency oscillator is provided which can be phase locked to a reference frequency oscillator which is much more stable then the variable frequency oscillator. The outputs of both oscillators are connected to a phase detector whose output is fed through a sample and hold circuit and a summing amplifier back to the control input of the variable frequency oscillator. A sweep signal from a sweep generator is also supplied to the summing amplifier. 
     Before the beginning of each sweep, the sample and hold circuit is closed to establish phase lock between the reference frequency oscillator and the variable frequency oscillator, and the error signal from the phase detector is stored on a capacitor. Next, the sample and hold circuit is opened, opening the phase lock loop; and then the sweep signal begins to change value linearly sweeping the voltage controlled oscillator. Since the error voltage that was established at the beginning of the sweep is stored on the capacitor and is continuously summed with the sweep voltage, the voltage controlled oscillator is compensated for any frequency drifts that might have taken place before the sweep began. The only frequency drift that can affect the accuracy of the sweep oscillator output are those drifts that take place during the sweep itself. 
     At the end of the sweep, the sweep generator is reset, returning the voltage controlled oscillator to its original frequency, plus or minus the amount it has drifted during the sweep. Then the sample and hold circuit is again closed. Phase lock is once again established and the drift during the last sweep is compensated. At this point the sweep cycle begins once again. 
     This system allows for the correction of drifts in a first local oscillator in a spectrum analyzer without the expense of having a digitally swept oscillator or having to rely on narrower band oscillator or the complexity of closed loop sweeping. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a simplified block diagram of the preferred embodiment of the present invention. 
     FIG. 2 shows a schematic diagram of the apparatus of FIG. 1. 
     FIG. 3 shows a flow chart of the operation of the preferred embodiment. 
     FIG. 4 shows a graph of several of the signals in the circuit of FIG. 2. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 shows an electronically controlled variable frequency oscillator, such as a voltage controlled oscillator 10 having a signal output 12 and a control input 14. A reference oscillator 16 has a signal output 18 which is connected to a phase comparator 20. Reference oscillator 16 may be simply a fixed frequency, high stability oscillator such as a crystal oscillator or it may be a synthesized frequency source. Signal output 12 from voltage controlled oscillator 10 is also connected to phase comparator 20, and the phase difference between the output signals from the two oscillators appears on output 22. Output 22 is connected to a sample and hold circuit 24 which in turn is connected to a summing circuit 26. The output of summing circuit is connected to control input 14 of the voltage controlled oscillator. 
     A sweep generator 28 is connected to a second input of the summing circuit 26. A control circuit 30 is connected to sweep generator 28, sample and hold circuit 24 and phase comparator 20 to control the sweep generator and the sample and hold circuit. 
     Circuitry implementing the block diagram of FIG. 1 is shown in greater detail in FIG. 2. Here sample and hold circuit 24 is shown as having a relay 32 between the input and output thereof, with a capacitor 34 connected between ground and the output side of the circuit. When relay 32 is closed, capacitor 34 will store the value of the signal at the output of phase detector 20. 
     Summing circuit 26 comprises an operational amplifier 36 with appropriate input and feedback resistors connecting the amplifier to the output of sample and hold circuit 24 and sweep generator 28. 
     Sweep generator 28 includes a current source 38 feeding a capacitor 40 to create a linearly increasing ramp or sweep voltage. The capacitor is connected to a relay 42 which shorts the capacitor to ground when the relay is closed in order to reset the sweep. Also connected to the capacitor is a comparator 44 to compare the voltage on the capacitor with a reference voltage established by voltage source 46 for determining the end of the sweep and producing an end of sweep signal which appears on comparator output 48. Control circuit 30 comprises a four-bit shift register 50 having four &#34;D&#34; flip-flops 51 through 54. NOR gate 55 assures that only one of the D flip-flops has a &#34;1&#34; or high output at any given time. A system clock 56 provides periodic clock pulses to the shift register through AND gate 58 to drive the shift register. 
     The operation of control circuit 30 is illustrated in the flow diagram of FIG. 3. The four rectangles in the flow diagram represent the four states of shift register 50 and a separate function is performed in each of the states as represented by the labeling in the rectangles. Thus, a high output on flip-flop 51 corresponds to state 1, a high output on flip-flop 52 to state 2, etc. In state 1 the sweep reset switch, relay 42, is opened by applying a signal to the relay coil via flip-flop 60. At this point, current from current source 38 will be applied to capacitor 40 and the voltage on the capacitor will increase linearly producing a voltage ramp. This ramp is illustrated as signal V 3  in FIG. 4. At the end of the sweep an end-of-sweep signal V 4  will be produced by comparator 44 to cause the shift register to advance to the next state, 2, where the sweep reset switch is closed causing the sweep voltage V 3  to return to zero. 
     After the sweep voltage has returned to zero, the shift register will shift to state 3 and the sample and hold switch, relay 32 will be closed by flip-flop 62 with the application of signal V 5  to the coil of the relay. 
     Since relay 32 has closed the phase lock loop around voltage controlled oscillator 10, the oscillator frequency will be phase locked to the frequency of reference oscillator 16. The error voltage, V 1 , from the phase detector will become constant in value when this is accomplished, as illustrated in FIG. 4. In addition, the phase detector produces a &#34;phase locked&#34; signal, V 7 , to indicate that lock has been accomplished. At this point, the shift register will advance to the next state, 4, and the sample and hold switch will be opened. The error signal, V 1 , has been stored in capacitor 34 as signal V 2  and that value will remain constant during the sweep, as shown in FIG. 4. The shift register is now ready to return to state 1 where the sweep reset switch is opened and another sweep can be started. 
     Control circuit 30 has been illustrated as hardwired logic in the form of gates and flip-flops. However, it will be understood by those skilled in the art that the control function can also be executed in other ways such as, for example, by using a ROM programmed micro-processor which may be part of an overall system control circuit.