Abstract:
A method is provided for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is pattered to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the dopes silicon layer is converted to a porous silicon layer. Following the last step, the silicon shell is tensily stressed, making it a good candidate for use as a channel feature in an n-type field effect transistor.

Description:
BACKGROUND 
     The present invention relates to the electrical, electronic and computer arts, and, more particularly, to methods for forming field effect transistors in integrated circuits. 
     The inclusion of strained channels in modern metal-oxide-semiconductor field effect transistor (MOSFET) devices holds the promise of increased charge carrier mobilities and transistor device currents. Unfortunately, however, electron mobility and hole mobility benefit from different strain characteristics. The performance of an n-type field effect transistor (NFET) is typically improved if its channel is tensily strained. In contrast, the performance of a p-type field effect transistor (PFET) is typically improved if its channel is compressively strained. These opposite responses to different types of strain have made strain engineering in complementary metal-oxide-semiconductor (CMOS) processing quite challenging. 
     BRIEF SUMMARY 
     Embodiments of the invention provide methods for forming tensily strained silicon features suitable for use as channels in NFET devices in a manner that is easily integrated with the formation of compressively strained channel features in PFET devices on the same integrated circuit. 
     Aspects of the invention are directed to a method for forming an integrated circuit. A doped silicon layer is formed on a silicon substrate. A silicon-germanium layer is subsequently formed on the doped silicon layer. The silicon-germanium layer is patterned to form a silicon-germanium feature. A silicon shell is formed on the silicon-germanium feature. At least a portion of the doped silicon layer is converted to a porous silicon layer. 
     Additional aspects of the invention are directed to an integrated circuit formed using a method comprising the steps set forth in the previous paragraph. 
     Even additional aspects of the invention are directed to an integrated circuit comprising an oxide layer, a silicon-germanium feature, and a silicon shell. The silicon-germanium feature is disposed on the oxide layer. The silicon shell is disposed on the silicon-germanium feature. The silicon shell is tensily strained. 
     These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The following drawings are presented by way of example only and without limitation, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and wherein: 
         FIG. 1  shows a flow diagram of a method for forming a base structure of an integrated circuit, in accordance with an illustrative embodiment of the invention; 
         FIGS. 2-7  show sectional views of intermediate film stacks formed when performing the  FIG. 1  method; and 
         FIG. 8  shows a sectional view of an exemplary PFET base structure that may be integrated into the same integrated circuit as the  FIG. 1  base structure. 
     
    
    
     It is to be appreciated that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown in order to facilitate a less hindered view of the illustrated embodiments. 
     DETAILED DESCRIPTION 
     The present invention will be described with reference to illustrative embodiments. For this reason, numerous modifications can be made to these embodiments and the results will still come within the scope of the invention. No limitations with respect to the specific embodiments described herein are intended or should be inferred. 
       FIG. 1  shows a flow diagram of a method  100  in accordance with an illustrative embodiment of the invention for forming a base structure for an NFET in a CMOS integrated circuit.  FIGS. 2-7 , in turn, show sectional views of intermediate film stacks formed during the processing. Although the method  100  and the structures formed thereby are entirely novel, the individual processing steps required to implement the method  100  may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. Moreover, details of the individual processing steps used to fabricate semiconductor devices described herein may be found in a number of publications, for example, S. Wolf and R. N. Tauber,  Silicon Processing for the VLSI Era, Volume  1, Lattice Press, 1986; S. Wolf,  Silicon Processing for the VLSI Era, Vol.  4:  Deep - Submicron Process Technology , Lattice Press, 2003; and S. M. Sze,  VLSI Technology, Second Edition , McGraw-Hill, 1988, all of which are incorporated by reference herein. It is also emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to successfully form a functional device. Rather, certain processing steps that are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning steps, are purposefully not described herein for economy of description. However one skilled in the art will readily recognize those processing steps omitted from this more generalized description. 
     The method  100  starts in step  105  with the formation of a doped silicon layer  200  (doped Si) on a silicon substrate  205  (Si substrate). The silicon substrate  205  may be in the form of a silicon wafer. In the present illustrative embodiment, boron is used as the dopant to make the doped silicon layer  200  p-type. The doped silicon layer  200  may be formed, by for example, boron ion implantation into the surface region of the silicon substrate  205 , followed by annealing to diffuse and activate the dopant. Preferably, the dopant concentration in the doped silicon layer  200  is between 1E19/cm 3  to 1E21/cm 3 . The resultant film stack is shown in  FIG. 2 . In another embodiment, the doped silicon layer  200  can be formed by epitaxially growing silicon with in-situ boron doping instead of by ion implantation/annealing. This epitaxial growth may be integrated with the subsequent epitaxy of silicon-germanium if so desired (see next paragraph). 
     Subsequently, in step  110 , a silicon-germanium layer  210  (SiGe layer) is formed on the doped silicon layer  200  to yield the film stack shown in  FIG. 3 . Deposition may be by vapor-phase epitaxial growth in either a multi-wafer or a single-wafer reactor. When using a multi-wafer reactor, any native oxide on the surface of the doped silicon layer  200  may be initially removed by dipping the wafer in diluted hydrofluoric acid. In addition to removing the native oxide, this wet etch also acts to terminate the surface of the wafer in hydrogen. The wafer may then be introduced into the multi-wafer reactor, where it is exposed to silane, germanium, and hydrogen in the milli-torr total pressure range and at about 500-700° C. Single-wafer processing may be performed in a single-wafer reactor with similar processing parameters, but the wet etch to remove the native oxide may be replaced by an in-situ high temperature anneal by rapid thermal processing (RTP) to sublimate that oxide. Single-wafer reactors capable of depositing silicon-germanium are available from, for example, Applied Materials (Santa Clara, Calif., USA). Optionally, an additional silicon layer (not shown) may be grown on top of the silicon-germanium layer  210 . The optional additional silicon layer, if present, can be used to facilitate the forming of a silicon shell in later processing (see step  120  below). 
     Because germanium is larger than silicon, the incorporation of germanium into the silicon-germanium layer  210  creates a lattice mismatch between that layer and the underlying doped silicon layer  200 . This mismatch causes the silicon-germanium layer  210  to be compressively strained. The amount of this strain may be modulated somewhat by incorporating greater or smaller atomic percentages of germanium into the silicon-germanium layer  210 , as well as by varying that percentage over the thickness of the silicon-germanium layer  210 . In one or more embodiments in accordance with aspects of the invention, the silicon-germanium layer  210  may be characterized by a straight or graded germanium concentration profile with a germanium concentration maintained in the 10-40 atomic percent range, although this range is meant to be purely illustrative and is not intended to limit the scope of the invention. 
     In step  115 , the silicon-germanium layer  210  is patterned to form a silicon-germanium feature  215 . Here, processing may be accomplished by, for example, lithography followed by reactive-ion etching (RIE). The RIE of the silicon-germanium layer  210  to define the silicon-germanium feature  215  is preferably somewhat selective to the doped silicon layer  200 , meaning that it etches the silicon-germanium layer  210  faster than the doped silicon layer  200 . This allows the RIE process to be easily stopped on the doped silicon layer  200  to yield the film stack shown in  FIG. 4 . Suitable RIE chemistries may include, for example, carbon tetrafluoride (CF 4 ) with argon because germanium normally has a higher chemical etching characteristic with fluorine than does silicon, thus allowing some selectivity in the etch. The etch rate of silicon-germanium relative to silicon in carbon tetrafluoride may typically be increased by increasing carbon tetrafluoride concentrations, increasing total pressure, and decreasing plasma power. 
     With the silicon-germanium feature  215  formed as shown in  FIG. 4 , the method  100  then proceeds to step  120 , wherein a silicon shell  220  is formed on the top and sidewalls of the silicon-germanium feature  215 . The result of this processing is shown in  FIG. 5 . Here, processing may occur by depositing a silicon layer by silicon epitaxy at elevated temperature (e.g., above 600° C.) utilizing a gaseous source of silicon (e.g., silane, silicon tetrachloride, dichlorosilane), and hydrogen as gaseous reactants. In one embodiment, the silicon epitaxy process is tuned to grow at a much faster rate on exposed silicon-germanium than on boron-doped silicon. Epitaxy followed by etch back may be performed to remove any silicon deposited on the top of the doped silicon layer  200 . In another embodiment, the silicon layer is deposited around the silicon-germanium feature  215  as well as on the top of the doped silicon layer  200 . A RIE process is then used to remove the just-deposited silicon layer from the top of the doped silicon layer  200 . To ensure that silicon remains on top of the silicon-germanium feature  215  after RIE, the additional silicon layer set forth above may be epitaxially grown on top of the silicon-germanium layer  210  in step  110 . 
     Step  125  of the method  100  involves converting the doped silicon layer  200  to a porous silicon layer  225 , yielding the film stack shown in  FIGS. 6A and 6B  (where  FIG. 6B  shows a second sectional view of the film stack along the plane indicated in  FIG. 6A ). In one or more embodiments, an anodization process may be used to perform this conversion. In such a process, an electrical potential is induced in the doped silicon layer by, for example, illumination, while the wafer is immersed in dilute hydrogen fluoride. The anodization process is believed to be dependent on hole concentrations, thus accounting for a preference that the doped silicon layer  200  be doped so as to be p-type when formed during step  105 . It is noted however, that, in one or more alternative embodiments, an n-type dopant (e.g., phosphorous) may be utilized in the doped silicon layer  200  in step  105 , so long as adequate illumination is provided during anodization in step  125  to produce the required number of holes to drive the conversion to the porous silicon layer  225 . 
     The conversion of the doped silicon layer  200  to the porous silicon layer  225  has a significant effect on the silicon-germanium feature  215  and the overlying silicon shell  220 . Porous silicon has a relatively low Young&#39;s Modulus when compared to non-porous crystalline silicon. As a result, the porous silicon layer  225 , now being somewhat elastic, allows the silicon-germanium feature  215  to stretch in response to the compressive strain that was induced therein during its deposition in step  110 . The relaxation of the silicon-germanium feature  215 , in turn, stretches the silicon shell  220  and induces a tensile strain in the silicon shell  220 . The stretching of the porous silicon layer  225 , the silicon-germanium feature  215 , and ultimately the silicon shell  220  during step  120  is diagrammatically represented in  FIG. 6B  by an arrow  230 . 
     Thus, to summarize steps  105 - 125 , a tensily strained silicon shell is formed by first forming a compressively strained silicon-germanium feature on an underlying doped silicon layer and then covering that silicon-germanium feature with silicon. Subsequently, the underlying doped silicon layer is converted to porous silicon, which allows the silicon-germanium feature to relax (i.e., stretch), inducing a tensile strain in the silicon shell. The method  100  thereby becomes a viable method for forming a tensily strained silicon feature on a crystalline silicon substrate. 
     Returning to  FIG. 1 , in step  130  of the method  100 , the porous silicon layer  225  is oxidized to form a silicon dioxide layer  235  in the place of the porous silicon layer  225 . Processing may be by a mild thermal oxidation in a water (wet) or oxygen (dry) ambient. Because of the porosity of the porous silicon layer  225 , its rate of oxidation will be significantly faster than that of the exposed silicon shell  220 . The resultant film stack is shown in  FIG. 7 . 
     So formed, the silicon shell  220 , now tensily strained, becomes an excellent channel feature for use in an NFET, particularly a FinFET with a gate that is capacitively coupled to three sides of the channel feature. That is, the film stack in  FIG. 7  forms an excellent base structure upon which to form NFETs with tensily strained channels by additional CMOS processing. Advantageously, PFETs with compressively strained channels may be formed on the same integrated circuit as these NFETs simply by placing a block mask over the regions of the silicon substrate  205  slated for those PFETs while performing the method  100 .  FIG. 8  shows an exemplary base structure well suited for a PFET that, through the use of a block mask, may be placed on the same integrated circuit as the base structure shown in  FIG. 7 . The base structure in  FIG. 8  includes the silicon substrate  205  with a patterned, compressively strained silicon-germanium channel feature  240 . 
     It should again be emphasized that the above-described embodiments of the invention are intended to be illustrative only. Other embodiments may, for example, utilize different processing steps from those expressly set forth above to also achieve embodiments falling within the scope of the invention. 
     The method  100  as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor. 
     All the features disclosed herein may be replaced by alternative features serving the same, equivalent, or similar purposes, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
     Any element in a claim that does not explicitly state “means for” performing a specified function or “step for” performing a specified function is not to be interpreted as a “means for” or “step for” clause as specified in AIA 35 U.S.C. §112(f). In particular, the use of “steps of” in the claims herein is not intended to invoke the provisions of AIA 35 U.S.C. §112(f).