Abstract:
A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory structures formed using the methods described herein. In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer by remote plasma nitrogen (RPN).

Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The invention relates generally to non-volatile semiconductor memory devices, and more particularly to a non-volatile semiconductor memory structure comprising a multi-trapping layer comprising a plurality of silicon-rich, silicon nitride charge-trapping layers.  
         [0003]     2. Background of the Invention  
         [0004]     Electrically erasable programmable read only memories (EEPROM) rely on charge injection and removal to establish a stored logic state. This is in contrast to conventional dynamic random access memory (DRAM), which requires periodic refresh pulses in order to maintain the logic state in a capacitive storage element. Conventional EEPROM devices generally comprise a field effect transistor (FET), wherein the gate electrode is formed over a portion of the silicon substrate between two diffusion regions. The diffusion regions act as the source and gate for the FET. The gate electrode in conventional EEPROM devices comprises some form of injection layer into which charges are injected from a channel induced in the silicon substrate below the gate electrode.  
         [0005]     In practice, it is difficult to precisely control the extent of charge injection from the induced channel region. A silicon oxide layer separating the channel region from the injection layer must be thin enough to allow charge transfer and yet thick enough to allow the injection layer to retain and store the injected charge. These characteristics are very sensitive to changes in the thickness and/or stoichiometry of the oxide film.  
         [0006]     In order to surmount these difficulties, researchers have attempted to construct EEPROM cells that do not rely upon charge injection from an induced channel region. One such device makes use of a non-conductive charge-trapping structure formed from silicon-rich, silicon nitride (Si 3 N 4 ). The silicon-rich, silicon nitride-trapping layer of one such device is fabricated using LPCVD with different flow rate ratios (R) of dichlorosilane and ammonia.  
         [0007]     Such a device provides a non-conductive charge-trapping structure that is not dependent on carrier injection in order to establish a stored logic state. Further, such a device provides a charge-trapping structure that is not overly sensitive to small variations and thickness and/or stoichiometry; however, a drawback to such device is that it only comprises a single trapping layer and therefore can only store a single logic state, orbit.  
       SUMMARY  
       [0008]     A non-volatile memory structure comprises a trapping layer that includes a plurality of silicon-rich, silicon nitride charge trapping layers. Each of the plurality of silicon-rich, silicon nitride layers can trap charge and thereby increase the density of memory devices formed using the non-volatile memory structure described herein.  
         [0009]     In one aspect, the plurality of silicon-rich, silicon nitride layers are fabricated by converting an amorphous silicon layer via remote plasma nitrogen (RPN).  
         [0010]     These and other features, aspects, and embodiments of the invention are described below in the section entitled “Detailed Description.” 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]     Features, aspects, and embodiments of the inventions are described in conjunction with the attached drawings, in which:  
         [0012]      FIG. 1  is graph illustrating the relationship between a flow ratio (R) of SiH 2 Cl 2 /NH 3  used to produce a silicon-rich, silicon nitride film and the refractive index for the film thus generated; (prior art)  
         [0013]      FIG. 2  is graph illustrating the flat band (FB) shift produced fro a silicon, nitride film at an applied electric field, in MV/cm, of either polarity when stressed for a fixed time duration at any field strength; (prior art)  
         [0014]      FIG. 3  is a diagram illustrating a first step in forming a multi-layer trapping layer in accordance with one embodiment;  
         [0015]      FIG. 4  is a diagram illustrating a second step in forming a multi-layer trapping layer in accordance with one embodiment;  
         [0016]      FIG. 5  is a diagram illustrating a third step in forming a multi-layer trapping layer in accordance with one embodiment;  
         [0017]      FIG. 6  is a diagram illustrating a multi-layer trapping layer formed using the method of  FIGS. 3-5 ;  
         [0018]      FIG. 7  is a graph of the Si(2p) binding energy for a silicon-rich, silicon nitride trapping layer formed using the process of  FIGS. 3-5 ;  
         [0019]      FIG. 8  is a graph of the N(1s) binding energy for a silicon-rich, silicon nitride trapping layer formed using the process of  FIGS. 3-5 ; and  
         [0020]      FIG. 9  is a diagram illustrating a non-volatile memory structure comprising a multi-layer trapping layer such as that illustrated in  FIG. 6 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0021]     It has been shown that silicon nitride charge-trapping layers deposited by LPCVD using various ratios (R) of dichlorosilane and ammonia can produce a charge-trapping layer that can be use in non-volatile memory cells. Specifically, it has been shown that low additional silicon content, silicon-rich, silicon nitride films exhibit appreciably enhanced trapping characteristics as compared to stoichiometric silicon nitride, without exhibiting appreciably enhanced conductivity characteristics.  
         [0022]     It has been shown that a flow rate (R) that results in a silicon nitride film with a refractive index around 2.1 produces the low additional silicon content, silicon-rich, silicon nitride films exhibiting the enhanced trapping characteristics and without appreciably enhanced conductivity characteristics that prove useful in non-volatile memory cells. As illustrated in  FIG. 1 , a ratio (R) in the range of 3 to 5 can produce a silicon nitride layer with a refractive index in the range of 2.1.  
         [0023]      FIG. 2  is a graph illustrating a plot of the flat band (FB) shift produced at an applied electric field, in MV/cm, of either polarity when stressed for a fixed time duration at any field strength. The test structure used to produce the graph of  FIG. 2  consisted of 70 A of thermal silicon oxide grown on a P-type silicon substrate, 100 A of deposited nitride or silicon-rich, silicon nitride (R=0.1 and 5), 45 A of oxide thermally grown on the silicon nitride or silicon-rich, silicon nitride layer, and a 1 micron layer of aluminum. The graph illustrates that the stoichiometric silicon nitride exhibits a positive flat band shift for E-fields of either polarity, and that the difference between the two shifts is only approximately 1.5 volts at E=±7.5×10 6  v/cm. The silicon-rich, silicon nitride film of R=5, however, exhibits positive and negative flat band shifts as a function of the E-field polarity. Thus, both holes and electrons are being trapped. The difference between the two voltage shifts is approximately between 3.5V at E=7.5×10 6  V/cm. This difference in flat band voltage shift is addition to provide a manufacturable EEPROM storage cell.  
         [0024]     Thus, what has been shown by previous experiments is that silicon-rich, silicon nitride films with an associated refractive index in the range of 2.1, e.g. 2.1-2.17, will provide the charge storage function normally provided by polysilicon floating gates of EEPROM cells. In general, it has been shown that silicon-rich, silicon nitride films having a refractive index between approximately 2 and 2.4 will provide appreciably enhanced charge-trapping without providing appreciably enhanced conduction.  
         [0025]     As mentioned, a drawback to conventional devices that use silicon-rich, silicon nitride films for charge trapping is that only a single-charge trapping layer can be formed, which limits the charge-trapping density.  
         [0026]     The memory cell described herein uses RPN to convert amorphous silicon into a silicon-rich, silicon nitride trapping layer; however, the trapping layer can actually comprise a plurality of silicon-rich, silicon nitride layers. Each trapping layer can be used to trap charge and therefore increase the trapping density.  
         [0027]      FIGS. 3-5  can be used to illustrate the process for fabricating a trapping layer comprising multiple silicon-rich, silicon nitride layers. In  FIG. 3 , a silicon oxide (SiO 2 ) layer  101  can be grown on a silicon substrate  102 . Silicon oxide layer  101  can, for example, be thermally grown on silicon substrate  102 . In  FIG. 4 , an amorphous silicon layer  112  can be deposited on top of silicon oxide layer  101 . For example, in one embodiment, an amorphous silicon layer  112  can comprise 5 A to 25 A of amorphous silicon deposited by SiH 4  with gas flow equal to 16 sccm at 580° C. and 200 Torr for 10 to 20 seconds.  
         [0028]     Once amorphous silicon layer  112  is deposited, it can be converted into a silicon-rich, silicon nitride layer via RPN. RPN techniques are well documented and it will be appreciated that any suitable RPN technique can be used to convert amorphous silicon layer  112  into a silicon-rich, silicon nitride layer. For example, thermal RPN techniques using microwave plasma to excite the nitrogen molecules into the process environment can be used as can high-density plasma RPN techniques.  
         [0029]     In one embodiment, amorphous silicon layer  112  is exposed to RPN radicals  113  with Ar equal to 1200 sccm, and N 2  equal to 50 to 100 sccm, at 400° C. and 1.6 Torr for 150 to 300 seconds. By applying RPN radicals  113  on layer  112 , amorphous silicon layer  112  can be converted to a silicon-rich, silicon nitride layer  114  as illustrated in  FIG. 5 . This silicon-rich, silicon nitride layer  114  can then be used to trap charge in a non-volatile memory structure as described below.  
         [0030]     By implementing the process illustrated in  FIGS. 4 and 5  repeatedly, i.e., growing a silicon oxide layer  101 , depositing an amorphous silicon layer  112 , and exposing the amorphous silicon layer to RPN radical  113  in order to convert the amorphous silicon layer into a silicon-rich, silicon nitride layer  114 , a multi-layer structure can be generated as illustrated in  FIG. 6 .  
         [0031]     As illustrated in  FIG. 6 , a plurality of silicon-rich, silicon nitride layers  117  can be generated by repeating the process described above. The stoichiometry of trapping layers  117  would generally not be uniform from layer to layer. As a result, silicon-rich, silicon nitride can exist on the upper regions of layers  117  that can provide sufficient recess silicon for charge-trapping in each interface. As a result, a multi-trapping layer  115  for use in a non-volatile memory device comprising a high density of deep level trapping layers can be obtained using the methods described herein.  
         [0032]     Using the method described herein a silicon-rich, silicon nitride film with a refractive index in the range of 2.3 can be obtained. As mentioned above, silicon-rich, silicon nitride layers with refractive indexes in this range prove useful for storing charge sufficient for EEPROM, or non-volatile memory type applications. Further, the silicon-rich, silicon nitride layer produced using the methods described herein produces a multi-Si binding energy as illustrated in  FIG. 7 .  FIG. 7  illustrates the binding energy for silicon oxide as well as multiple binding energies for the silicon-rich, silicon nitride. The two binding energies illustrated in  FIG. 7  are for Si(2p).  
         [0033]      FIG. 8  is a diagram illustrating the binding energy for silicon-rich, silicon nitride produced using the methods described herein. The binding energy illustrated in  FIG. 8  is the binding energy of N(1s).  
         [0034]     The thickness of multi-trapping layer  115  can effect whether layer  115  will have an index of refraction in the correct range. Experiments have shown that a thickness of between 100 A and 200 A can produce an index of refraction greater than approximately 2.1, which can be sufficient for non-volatile memory applications. For example, a thickness of approximately 100 A, with a silicon Oxide thickness of approximately 1200 A can produce an index of refraction of greater than 2.1, e.g., about 2.3.  
         [0035]     This can for example correspond to a multi-trapping layer film  115  comprising 10 silicon-rich, silicon nitride layers  117 , each with a thickness of about 10 A. Thus, thicknesses in the range of 10 A to 20 A for silicon-rich, silicon nitride layers  117  can produce a film  115  with the correct index of refraction.  
         [0036]      FIG. 9  is a diagram illustrating an example of non-volatile memory structure with a multi-trapping layer  119  produced in accordance with the methods described above. As can be seen, non-volatile memory structure  130  comprises a silicon substrate  116 . Drain/source regions  132  can then be implanted in substrate  116 . A silicon oxide layer  118  can then be grown over substrate  116 . A multi-trapping layer  119  can then be formed using repeated RPN cycles as described above, and poly silicon layer  120  can then be deposit on top of structure  119 .  
         [0037]     Thus, multi-trapping layer  119  can comprise multiple silicon rich, silicon nitride layers  117  as in  FIG. 6 . These multiple layers can provide a high density of deep level trappings in contrast to conventional memory devices that use a single silicon-rich, silicon nitride trapping layer.  
         [0038]     While certain embodiments of the inventions have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the inventions should not be limited based on the described embodiments. Rather, the scope of the inventions described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.