Abstract:
A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to memories, and particularly to non-volatile memories such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memories.  
         [0003]     The present invention applies more particularly to memories accessible by a serial bus such as an SPI (Serial Peripheral Interface) or an I2C bus.  
         [0004]     2. Description of the Related Art  
         [0005]     One example of a memory accessible by a serial bus is represented in  FIG. 1 . The memory MEM represented in  FIG. 1  comprises a memory array MA, a control device CTL, a booster circuit HVCT, an address register ADR, a data register DTB, an input/output register IOSR, a status register STR, a line decoder RDEC and a column decoder CDEC.  
         [0006]     The control device CTL receives from the external environment a selection signal CS for selecting the memory MEM and a clock signal CK. The device CTL controls the register IOSR and the status register STR, and supplies a control signal VC for controlling the circuit HVCT. The circuit HVCT supplies a high voltage Vpp required to program and erase memory cells of the memory array MA. The register IOSR receives commands and exchanges data with the external environment of the memory through a serial bus DB. The register IOSR is paced by the clock signal CK and receives the commands, data and addresses transmitted by the bus. In write mode, the register ADR receives from the external environment through the serial bus DB and the register IOSR an address of memory cells to be read, programmed or erased, and the register DTB receives data to be stored in the memory array MA. The status register contains information concerning the status of the memory MEM. The address contained in the register ADR is used to control the decoders RDEC and CDEC that enable memory cells to be programmed, to be erased or to be read to be selected according to the address supplied by the address register.  
         [0007]     The memory is accessible through read and write commands. The commands applied to the memory are decoded using a finite state machine integrated into the control device CTL.  
         [0008]     An example of a control device CTL is represented in  FIG. 2 . In  FIG. 2 , the control device CTL comprises a clock signal input CK, a main state machine MFSM, a write state machine WFSM and a detector circuit PRDT for detecting the switching on of the memory MEM and generating an initialization signal POR when the memory is switched on.  
         [0009]     The state machine MFSM particularly decodes the commands applied to the memory, and activates the write state machine WFSM when the command received is a write command. The state machine WFSM supplies the signal VC that particularly drives the booster circuit HVCT during the phases of writing the memory. The circuit PRDT activates the signal POR following the switching on of the memory (when the supply voltage exceeds a certain threshold value). The state machine MFSM receives the selection signal CS for selecting the memory MEM, and the serial control signal DT transmitted by the bus DB for accessing the memory. The state machine MFSM also receives, through an OR-type logic gate OG 1 , the initialization signal POR and another initialization signal RST. The signal RST comprises one pulse upon each falling edge of the signal CS. The state machine MFSM supplies the state machine WFSM with a start-write signal SP upon the execution of a write command.  
         [0010]     The state machine WFSM is also initialized by the signal POR and supplies the state machine MFSM with a busy signal RB indicating when a write phase is in progress. The signal RB is applied to an activation input En of the state machine MFSM. When the signal RB is active, the state machine MFSM is blocked, but can nonetheless receive and process a command applied to the memory.  
         [0011]     The state machines MFSM and WFSM are generally produced using programmable logic arrays PLA. The state machines are initialized using the signal POR when the memory MEM is switched on. In addition, the programmable logic array of the state machine MFSM is initialized by the signal RST at the start of each access to the memory so as to always start in a same well-defined state. The logic circuit around the state machines must also be initialized in a same well-defined state to operate properly.  
         [0012]     However, due to certain protocol requirements in particular, certain parts of the device CTL cannot be initialized at the start of the receipt of a command. Thus, the initialization signal RST cannot be applied to the state machine WFSM given that the write commands in the memory are executed following the deselection of the memory (rising back up of the signal CS).  
         [0013]     If, for any reason (disturbance on the supply voltage, an electrostatic discharge, failure of the memory cells, etc.), the device CTL is put into an inhibited state, the memory can no longer operate correctly and the reliability of the subsequent accesses to the memory is affected.  
         [0014]     In particular, when the memory is write-controlled, the state machine WFSM sends the busy signal RB that blocks the main state machine MFSM while the writing operation is in progress. While the busy signal RB is active, the initialization of the control device CTL, which is normally performed upon each new access to the memory, is not executed following a change of state of the signal CS (the signal RST is not generated). If an operation of writing in the memory has not taken place correctly, the busy signal RB can remain active. Then the result is that the memory is blocked. The only way to restore the memory to a normal state is to temporarily cut off the power supply of the memory. In applications such as motor cars, it is not acceptable to have to cut off the power supply to reset the circuits. Even if the memory is no longer functional, it must still be able to execute read commands.  
         [0015]     Thus, it is desirable to reduce the risks of improper operation of the control device of a memory by providing for performing an initialization of the control device which is as complete as that obtained by switching off the circuit.  
       BRIEF SUMMARY OF THE INVENTION  
       [0016]     One embodiment of the present invention provides a memory with a control device that can be completely initialized without switching off the circuit.  
         [0017]     Another embodiment of the present invention provides a memory with a control device that is capable of executing a full initialization command, while remaining compatible with the communication protocol between the memory and the external environment.  
         [0018]     One embodiment provides a method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory.  
         [0019]     According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.  
         [0020]     According to one embodiment of the present invention, the method comprises a step of initializing an initialization circuit detecting the specific event, following the initialization of the control device.  
         [0021]     According to one embodiment of the present invention, the specific event is an initialization command received by the memory.  
         [0022]     According to one embodiment of the present invention, the specific event is a write or read command for reading or writing in the memory, not associated with a write or read address.  
         [0023]     According to one embodiment of the present invention, a write or read command received by the memory is considered to be an initialization command if a selection signal for selecting the memory changes state before a write or read address is received by the memory, following the receipt of the read or write command.  
         [0024]     According to one embodiment of the present invention, the method comprises a step of at least partially initializing the control device if a write command for writing in the memory is still being executed at the end of a maximum write period.  
         [0025]     According to one embodiment of the present invention, the at least partial initialization of the control device comprises initializing a main state machine and a write state machine.  
         [0026]     One embodiment of the present invention also relates to a memory comprising a control device for executing commands for accessing the memory, received in a control signal applied to the memory, and a detector circuit for detecting the switching on of the memory at least partially initializing the control device following the switching on of the memory.  
         [0027]     According to one embodiment of the present invention, the memory comprises an initialization circuit detecting a specific event in the control signal, and at least partially initializing the control device, following the detection of the specific event.  
         [0028]     According to one embodiment of the present invention, the initialization circuit is reset at least partially following the initialization of the control device.  
         [0029]     According to one embodiment of the present invention, the specific event is an initialization command received by the memory.  
         [0030]     According to one embodiment of the present invention, the specific event is a command for writing or reading in the memory, not associated with a write or read address.  
         [0031]     According to one embodiment of the present invention, the memory comprises a circuit for detecting the receipt of a write or read command by the memory, followed by a state change in a selection signal for selecting the memory, before a write or read address is received by the memory.  
         [0032]     According to one embodiment of the present invention, the memory comprises a time delay circuit that is triggered at the start of the execution of a write command in the memory and which at least partially initializes the control device at the end of a maximum write period.  
         [0033]     According to one embodiment of the present invention, the part of the control device that is initialized comprises a main state machine and a write state machine.  
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS  
       [0034]     These and other features and advantages of the present invention will be explained in greater detail in the following description of embodiments of the present invention, given in relation with, but not limited to the following figures, in which:  
         [0035]      FIG. 1  already described represents in block form an EEPROM memory accessible by a serial bus,  
         [0036]      FIG. 2  already described represents in block form a classic device for controlling the memory,  
         [0037]      FIG. 3  represents in block form a control device for controlling a memory, according to the present invention,  
         [0038]      FIGS. 4 and 5  are wiring diagrams of initialization signal generating circuits, of the control device according to the present invention,  
         [0039]      FIGS. 6 and 7  are timing diagrams of electric signals showing the operation of the control device according to the present invention,  
         [0040]      FIG. 8  is a wiring diagram of an initialization signal generating circuit, of the control device according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0041]      FIG. 3  represents a control device according to one embodiment of the present invention, for controlling the memory MEM represented in  FIG. 1 . In  FIG. 3 , the control device CTL comprises a clock signal input CK, a main state machine MFSM, a write state machine WFSM and a detector circuit PRDT for detecting the switching on of the memory MEM and generating an initialization signal POR.  
         [0042]     The state machine MFSM particularly decodes the commands applied to the memory. The state machine WFSM supplies the signal VC driving the booster circuit HVCT during the phases of writing the memory. The circuit PRDT activates the signal POR following the switching on of the memory (when the supply voltage Vdd exceeds a certain threshold value). The state machine MFSM receives the selection signal CS for selecting the memory MEM, and the serial control signal DT transmitted by the bus DB for accessing the memory. The state machine MFSM also receives, through an OR-type logic gate OG 1 , the initialization signal POR and another initialization signal RST used to initialize a programmable logic array PLA of the state machine MFSM at the start of each access to the memory MEM. The signal RST comprises one pulse upon each falling edge of the signal CS. The state machine MFSM supplies the state machine WFSM with a start-write signal SP upon the execution of a write command.  
         [0043]     The state machine WFSM is also initialized by the signal POR and supplies the state machine MFSM with a busy signal RB indicating that a write phase is in progress. The signal RB is applied to an activation input En of the state machine MFSM. When the signal RB is active, the state machine MFSM is blocked, but can nonetheless receive a command sent to the memory after the activation of the signal RB.  
         [0044]     According to one embodiment of the present invention, the control device CTL comprises an initialization signal generating circuit SRCT, which applies an initialization signal RDW to the state machines MFSM and WFSM.  
         [0045]     More precisely, the circuit SRCT generates the initialization signal RDW following the receipt of a control signal WC. The signal RDW is applied to the state machines MFSM and WFSM through an OR-type logic gate OG 2  another input of which receives the output signal POR of the circuit PRDT. The output signal PR 2  of the gate OG 2  is applied to an initialization input RS of the state machines MFSM and WFSM. The signal WC is sent by the state machine MFSM when a specific event is detected in the serial control signal DT.  
         [0046]     For example, if the commands applied to the memory are transmitted in accordance with the SPI protocol, the commands comprise 8 bits, and are listed in the following table:  
                       TABLE 1                       Command   Command code   Description                   WREN   06h   Write authorization       RDSR   05h   Reading of the status register SR       WRDI   04h   Writing prohibited       READ   03h   Reading of a datum in the memory       WRITE   02h   Writing of a datum in the memory       WRSR   01h   Writing in the state register SR                  
 
         [0047]     Table 1  
         [0048]     The commands for writing WRITE and reading READ in the memory are followed by a write or read address, then by the datum to be written in the case of a write command. The command for writing in the status register SR is followed by the datum to be written in the status register. The commands, the addresses and the data are transmitted starting with the most significant bit. The transmissions start when a change to 0 of the selection signal CS appears and end when the signal CS goes back to 1.  
         [0049]     To trigger an initialization of the control device CTL, one embodiment of the present invention uses a command normally followed by an address or a datum, without this command being followed by an address or a datum to be written. In Table 1, the commands that may be used to trigger an initialization are WRITE, READ and WRSR. In other words, if the control device receives such a command and the selection signal CS changes back to 1 at the end of the receipt of the eight bits of the command, the control device considers this to be an initialization command.  
         [0050]     Thus, one embodiment of the present invention provides an extra initialization command while remaining compatible with the protocol for transmitting the commands to the memory MEM.  
         [0051]     In the example of the SPI protocol, the signal WC generated by the state machine MFSM is synchronous with the command received. If the command received by the state machine is the command chosen for the initialization of the circuit, the signal WC is identical to the first seven bits of the command received. Thus, if the initialization command selected is the WRITE (=02h) command, the signal WC is on 0 for the five first falling edges of the clock signal CK and comprises a pulse on 1 between the sixth and seventh falling edges of the clock signal if the first 6 bits (bits  7  to  2 ) of the command received are on 0 and if the seventh bit (bit  1 ) of the command received is on 1.  
         [0052]      FIG. 4  represents an example of an embodiment of the generating circuit PRDT. The circuit PRDT comprises an OR gate OG 3  receiving the selection signal CS for selecting the memory, previously inverted by an inverter  11 . The output of the gate OG 3  is connected to the gate of an N-channel MOS transistor MN 1 . The source of the transistor MN 1  is connected to the ground. The circuit PRDT comprises a comparator for comparing the supply voltage Vdd with a voltage threshold. For this purpose, the comparator comprises a diode D 1  defining the voltage threshold and the anode of which is connected to the supply voltage source Vdd. The cathode of the diode is linked to the ground through a capacitor C 1 , and is connected to the drain of the transistor MN 1 , to the gate of a P-channel MOS transistor MP 2 , and to the gate of an N-channel MOS transistor MN 2 . The source of the transistor MP 2  receives the supply voltage Vdd. The source of the transistor MN 2  is connected to the ground. The drains of the transistors MN 2  and MP 2  are connected to the input of an inverter  13  the output of which supplies the initialization signal POR through another inverter  14 . The initialization signal POR is applied to an input of the gate OG 3 . The voltage threshold is determined by the threshold voltage of the diode D 1 .  
         [0053]     The signal POR generated by the circuit PRDT has an initialization pulse when the supply voltage Vdd of the memory exceeds the voltage threshold. The gate OG 3  and the inverters  13  and  14  enable the width of the initialization pulse of the signal POR to be reduced.  
         [0054]     It shall be noted that the diode D 1  can be replaced by several diodes mounted in series to adjust the voltage threshold.  
         [0055]      FIG. 5  represents an example of an initialization signal generating circuit SRCT when the initialization command chosen is the WRITE command. The circuit SRCT comprises an AND-type logic gate AG 1  receiving the serial control signal DT applied to the memory, the selection signal CS previously inverted by an inverter  16 , and the signal WC coming from the state machine MFSM and indicating whether or not a specific event is detected in the serial control signal. In the case of the SPI protocol, if this event is detected (receipt of a WRITE command), the signal WC is on 0 and comprises a pulse between the sixth and the seventh falling edge of the clock signal CK, starting from the change to 0 of the signal CS.  
         [0056]     The output of the gate AG 1  is connected to the D input of a D flip-flop F 1 . The flip-flop F 1  is initialized by the signal CS inverted at output of the inverter  16 . The Q output of the flip-flop F 1  is connected to the input of a latch LT. The output of the latch LT is connected to the input of an AND-type logic gate AG 2  receiving at another input the control signal DT previously inverted by an inverter  15 . The output of the gate AG 2  is connected to the D input of a D flip-flop F 2  the Q output of which supplies a signal DSL. The flip-flops F 1  and F 2  and the latch LT are paced by the clock signal CK previously inverted by an inverter  17 .  
         [0057]     The signal DSL is applied with the signal CS to an inverted AND-type logic gate AG 3 . The signal SLC at output of the gate AG 3  is applied to the input of an inverted OR-type logic gate OG 4 . The signal SLC is also applied to a circuit RC through an inverter  18 . The circuit RC comprises a resistor R 1  connected on one side to the output of the inverter  18  and on the other side to an input of the gate OG 4  and to a capacitor C 2  also connected to the ground. The output of the gate OG 4  is connected to the input of a falling edge delay circuit DLF 1  the output of which supplies the signal RDW. The circuit DLF 1  applies a delay to the falling edges of the signal applied at input.  
         [0058]     The signal RDW is applied to the input of an inverted OR-type gate OG 5  and to a circuit RC through an inverter  19 . The circuit RC comprises a resistor R 2  connected on one side to the output of the inverter  19  and on the other side to an input of the gate OG 5  and to a capacitor C 3  also connected to the ground. The output of the gate OG 5  is connected to the input of a falling edge delay circuit DLF 2  the output of which is connected to the input of an inverted OR-type gate OG 6 . The signal POR is applied to another input of the gate OG 6 . The output of the gate OG 6  supplies an initialization signal RS 2  that is applied to the initialization inputs of the latch LT and of the flip-flop F 2 .  
         [0059]     The operation of the control device CTL is shown by timing diagrams represented in  FIGS. 6 and 7 .  FIGS. 6 and 7  represent the timing diagrams of the signals Vdd, CS, CK, DT, POR, DSL, SLC, RDW, RS 2  and PR 2  when an initialization command is received by the control device CTL.  
         [0060]      FIG. 6  shows an initialization of the memory following the switching on thereof. Upon the switching on, the supply voltage Vdd increases gradually until it reaches its nominal value. The selection signal CS is on 1. The control signal DT is on 0. The increase in the supply voltage Vdd (memory MEM switched on), while the selection signal CS is on 1, triggers the appearance of a pulse in the signal POR emitted by the circuit PRDT.  
         [0061]      FIGS. 6 and 7  show the receipt of an initialization command by the memory. If the command sent by the signal DT is an initialization command, i.e., a WRITE (=02h) command not followed by an address and a datum, it remains on 0 up to the sixth falling edge of the clock signal CK and comprises a pulse upon the seventh falling edge of the signal CK before changing back to 0 upon the eighth falling edge of the signal CK, preceding the rising back up of the signal CS. As a result, during the first six falling edges of the clock signal CK, the output of the gate AG 1  remains on 0. The result is that, during this period, the flip-flop F 1  remains in the state  0  and the value stored by the latch LT is 0. If the signal WC has a pulse (upon the sixth falling edge of the clock signal), the signal DT is also on 1 at this instant. The output of the gate AG 1  therefore goes to 1. The flip-flop F 1  then changes state and supplies a signal on 1 at output. This signal value is stored by the latch LT. As the signal DT is on 1 and is inverted by the inverter  15 , the output of the gate AG 2  remains on 0. The state of the flip-flop F 2  is also on 0. Then, the last bit of the command is applied at input of the inverter  15 . If the last bit of the command received is on 0, the output of the gate AG 2  changes to 1, just like the flip-flop F 2 . In the opposite case, the flip-flop F 2  remains in the state  0 . As a result, the output signal DSL of the flip-flop F 2  is on 1 when the command applied at input is equal to 02h. The signal DSL remains on 1 up to the rising edge of the clock signal CK following the change to 1 of the selection signal CS. In the time interval between the rising of the signal CS and the falling of the signal DSL, the output signal SLC of the gate AG 3 , normally on 1, changes to 0. The result is that the output of the gate OG 4  changes to 1 up to a certain charge threshold of the capacitor C 2 . The signal RDW changes to 1 at the same time as the output signal of the gate OG 4 . The change to 0 of the signal RDW is delayed by the circuit DLF 1  in relation to the change to 1 of the signal SLC. The delay applied by the circuit DLF 1  is adjusted to obtain a certain width of the pulse of the signal RDW.  
         [0062]     The circuit formed by the gate OG 4 , the inverter  18  and the circuit RC R 1 , C 2  therefore enables a pulse to be generated at output upon a state change of the signal SLC. The signal RDW thus comprises an initialization pulse if the command received is a write command immediately followed (upon the ninth bit of the command) by the rising back up of the signal CS. The initialization signal PR 2  generated from the signal RDW in particular, is therefore active following the rising back to 1 of the selection signal CS.  
         [0063]     It shall be noted that the flip-flop F 1  is initialized upon the rising back up of the signal CS. This initialization has no impact on the value of the signal RDW as the latter is determined using the state of the latch LT and of the flip-flop F 2  which are not yet initialized.  
         [0064]     The signal RDW is used to generate the initialization signal RS 2 . When the signal RDW is on 0, the signal RS 2  is on 1. When the signal RDW changes to 1, the output of the gate OG 5  remains on 0 and therefore the signal RS 2  remains on 1. When the signal RDW changes back to 0, the output of the gate OG 5  changes to 1 and therefore the signal RS 2  changes to 0 with a certain delay applied by the circuit DLF 2  and remains on 0 for the charge time of the capacitor C 3 .  
         [0065]     The circuit formed by the gate OG 5 , the inverter  19  and the circuit RC R 2 , C 3  enables an initialization pulse to be generated immediately after the initialization pulse of the signal RDW. The signal RS 2  thus generated comprises a pulse enabling the latch LT and the flip-flop F 2  to be initialized immediately after the initialization of the control circuit CTL. The delay applied by the circuit DLF 2  is adjusted to increase the width of the initialization pulse of the signal RS 2  and so that this pulse only appears following the fall back of the signal RDW.  
         [0066]     It shall be noted that upon the switching on of the circuit SRCT, pulses appear in the signals RDW and RS 2 . These pulses do not disturb the operation of the circuit since they are generated during a period in which the memory MEM is not selected, and before the generation of the initialization signal POR.  
         [0067]      FIG. 7  shows in particular the case in which the clock signal CK remains in the high state following the rising back up of the selection signal CS, i.e., upon the eighth clock stroke following the change to 0 of the signal CS.  FIG. 7  shows that the absence of the ninth clock stroke does not prevent the generation of an initialization pulse in the signal RDW. Indeed, the change to 1 of the signal RDW is triggered by the eighth clock stroke and the change to 0 of the signal RDW is linked to the deselection of the memory (change to 1 of the signal CS).  
         [0068]     In a preferred embodiment of the present invention shown by  FIG. 3 , the control device comprises a time delay circuit TMR. The time delay circuit is triggered at the start of the execution of a write command in the memory MEM by the change to 1 of the signal RB. The duration of the delay is chosen to be slightly higher than the time for writing a word in the memory, for example 10 ms. If the delay ends before the signal RB changes to 0, the circuit TMR sends a signal RT that is applied to an input of the gate OG 2  to trigger an initialization of the control device CTL.  
         [0069]     An example of a time delay circuit is represented in  FIG. 8 . The time delay circuit TMR comprises a diode-mounted N-channel MOS transistor MN 3 , i.e., the gate of which is connected to the drain. The drain of the transistor MN 3  is also linked to the supply voltage source Vdd through a resistor R 3 , and the source of this transistor is connected to the ground. The drain of the transistor MN 3  is also connected to the gate of an N-channel MOS transistor MN 4  the source of which is connected to the ground. The drain of the transistor MN 4  is linked to the ground through a capacitor C 4  and to the supply voltage source Vdd through a switch IT. The switch IT is controlled by the signal RB and is closed when the signal RB is on 0. The drain of the transistor MN 4  is connected to the gate of a P-channel MOS transistor MP 5  and to the gate of an N-channel MOS transistor MN 5 . The source of the transistor MP 5  is connected to the supply voltage source Vdd. The source of the transistor MN 5  is connected to the ground. The drains of the transistors MP 5  and MN 5  are connected to the input of an AND-type logic gate AG 4  another input of which receives the signal RB and the output of which supplies the initialization signal RT.  
         [0070]     When the circuit is initialized, the signal RB is on 0 and therefore the switch IT is closed. The result is that the capacitor C 4  is charged. Therefore, the output signal of the inverter formed by the transistors MP 5  and MN 5  is on 0. As a result, the signal RT is on 0.  
         [0071]     When the signal RB changes to 1 at the start of the execution of a read command, the switch IT is open. The result is that the capacitor C 4  discharges through the transistor MN 4 . The duration of the discharge of the capacitor is adjusted by the bias of the transistor MN 3 . If the signal RB changes to 0 before the voltage at the terminals of the capacitor C 4  drops below the threshold voltage of the transistor MN 5 , the switch IT closes and the capacitor is charged again. In the opposite case, the signal applied to the gate AG 4  by the inverter formed by the transistors MP 5 , MN 5  changes to 1. If the signal RB is still on 1, the signal RT sent by the time delay circuit TMR changes to 1, which triggers the initialization of the state machines MFSM and WFSM. The result is that the signal RB changes back to 0, which cancels the signal RT.  
         [0072]     Providing the time delay circuit TMR avoids the cases of blocking the memory which would not be avoided with the circuit SRCT.  
         [0073]     It will be understood by those skilled in the art that various alternative embodiments and applications of the present invention are possible. In particular, the present invention is not limited to memories accessible by an SPI bus. It applies more generally to any memory accessible by a serial bus.  
         [0074]     The event triggering the initialization of the control circuit is not necessarily included in the data signal applied to the memory. This event can be detected in another signal applied to the memory to trigger an initialization of the memory equivalent to the one performed upon the switching on. When this event is detected in the data signal, any event other than the receipt of a write or read command can be used to trigger the initialization of the control circuit. This may, for example, be a specific command. For example, as the commands provided in the SPI protocol start with a 0 for five clock cycles, provision can be made for the initialization command to start with a 1 for one or more clock cycles.  
         [0075]     Furthermore, it shall be noted that the partial initialization of the initialization circuit SRCT, following the initialization of the state machines of the control circuit is only provided due to the nature of the initialization command to be detected. Indeed, this initialization of the circuit SRCT is only necessary due to the presence of the flip-flop F 2  and of the latch LT which can only be initialized after having generated the initialization signal RDW.