Abstract:
A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This Utility Patent Application is a continuation application of U.S. application Ser. No. 11/438,450, filed May 22, 2006, which is incorporated herein by reference. 
         [0002]    This Utility Patent Application is related to U.S. patent application Ser. No. 10/918,335 entitled “INTEGRATED MEMORY DEVICE AND PROCESS”, filed Aug. 13, 2004, which is incorporated herein by reference. 
     
    
     BACKGROUND 
       [0003]    One type of non-volatile memory is resistive memory. Resistive memory utilizes the resistance value of a memory element to store one or more bits of data. For example, a memory element programmed to have a high resistance value may represent a logic “1” data bit value, and a memory element programmed to have a low resistance value may represent a logic “0” data bit value. The resistance value of the memory element is switched electrically by applying a voltage pulse or a current pulse to the memory element. One type of resistive memory is phase change memory. Phase change memory uses a phase change material for the resistive memory element. 
         [0004]    Phase change memories are based on phase change materials that exhibit at least two different states. Phase change material may be used in memory cells to store bits of data. The states of phase change material may be referred to as amorphous and crystalline states. The states may be distinguished because the amorphous state generally exhibits higher resistivity than does the crystalline state. Generally, the amorphous state involves a more disordered atomic structure, while the crystalline state involves a more ordered lattice. Some phase change materials exhibit more than one crystalline state, e.g. a face-centered cubic (FCC) state and a hexagonal closest packing (HCP) state. These two crystalline states have different resistivities and may be used to store bits of data. 
         [0005]    Phase change in the phase change materials may be induced reversibly. In this way, the memory may change from the amorphous state to the crystalline state and from the crystalline state to the amorphous state in response to temperature changes. The temperature changes to the phase change material may be achieved in a variety of ways. For example, a laser can be directed to the phase change material, current may be driven through the phase change material, or current can be fed through a resistive heater adjacent the phase change material. In any of these methods, controllable heating of the phase change material causes controllable phase change within the phase change material. 
         [0006]    A phase change memory including a memory array having a plurality of memory cells that are made of phase change material may be programmed to store data utilizing the memory states of the phase change material. One way to read and write data in such a phase change memory device is to control a current and/or a voltage pulse that is applied to the phase change material. The level of current and/or voltage generally corresponds to the temperature induced within the phase change material in each memory cell. 
         [0007]    For data storage applications, reducing the physical memory cell size is a continuing goal. Reducing the physical memory cell size increases the storage density of the memory and reduces the cost of the memory. 
         [0008]    For these and other reasons, there is a need for the present invention. 
       SUMMARY  
       [0009]    One embodiment of the present invention provides a memory. The memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
           [0011]      FIG. 1  is a diagram illustrating one embodiment of an array of resistive memory cells. 
           [0012]      FIG. 2  is a diagram illustrating one embodiment of a phase change memory cell. 
           [0013]      FIG. 3  is a diagram illustrating another embodiment of a phase change memory cell. 
           [0014]      FIG. 4  is a diagram illustrating another embodiment of a phase change memory cell. 
           [0015]      FIG. 5  is a diagram illustrating another embodiment of a phase change memory cell. 
           [0016]      FIG. 6  is a diagram illustrating another embodiment of a phase change memory cell. 
           [0017]      FIG. 7  is a diagram illustrating another embodiment of a phase change memory cell. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
         [0019]      FIG. 1  is a diagram illustrating one embodiment of an array of resistive memory cells  100 . In one embodiment, the resistive memory cells are phase change memory cells. In another embodiment, the resistive memory cells are conductive-bridging random access memory (CBRAM) cells, magneto-resistive random access memory (MRAM) cells, electrolyte memory cells, or other suitable memory cells that store data as resistance values. While the invention will be described with reference to resistive memory cells including phase change elements, the invention also applies to resistive memory cells including CBRAM elements, MRAM elements, or electrolyte elements. 
         [0020]    Memory array  100  includes a plurality of phase change memory cells  104   a - 104   f  (collectively referred to as phase change memory cells  104 ), a plurality of bit lines (BLs)  112   a - 112   b  (collectively referred to as bit lines  112 ), a plurality of word lines (WLs)  110   a - 110   c  (collectively referred to as word lines  110 ), and a ground plate  114 . Memory cells  104  use tunneling field effect transistors (TFETs). TFETs are similar to metal-oxide-semiconductor field effect transistors (MOSFETs) except for the doping of the source extension. For n-channel MOSFETs, the drain and source extensions are n+ doped. In contrast, for TFETs the drain extension is n+ doped and the source extension is p+ doped. A positive gate bias applied to a TFET forms a reverse biased tunneling junction (i.e., a Zener diode) at the source to channel interface. After both regions are degenerated, carrier generation by band-to-band tunneling starts. TFET devices are compatible with complementary metal-oxide-semiconductor (CMOS) processing techniques. 
         [0021]    Adjacent TFETs for adjacent memory cells share a source extension. The shared source extension is coupled to a global p+ region, which acts as a source node or ground plate. With the shared source extension coupled to the ground plate, a contact to the shared source extension to connect source lines or ground lines of adjacent memory cell is not used. Therefore, the distance between adjacent TFETs and word lines  110  coupled to the TFETs can be reduced. The reduced distance between word lines  110  reduces the overall memory array size and increases the storage density of the memory array. 
         [0022]    In addition, in an off-state, a smaller static leakage current flows through a TFET as compared to a standard MOSFET with the same dimensions. The leakage current is reduced since the TFET operates differently from a MOSFET in the off-state. The MOSFET presents a reverse biased n+p diode that is controlled by the gate bias. For short channel lengths, several mechanisms arise increasing the static leakage current (e.g. DIBL, direct tunneling, etc.). For TFETs, a reverse biased junction diode limits the static leakage current since the absence of carriers determines the static leakage current of the diode. 
         [0023]    As used herein, the term “electrically coupled” is not meant to mean that the elements must be directly coupled together and intervening elements may be provided between the “electrically coupled” elements. 
         [0024]    Each phase change memory cell  104  in memory array  100  is electrically coupled to a word line  110 , a bit line  112 , and ground plate  114 . For example, phase change memory cell  104   a  is electrically coupled to bit line  112   a,  word line  110   a,  and ground plate  114 . Phase change memory cell  104   b  is electrically coupled to bit line  112   a,  word line  110   b,  and ground plate  114 . Phase change memory cell  104   c  is electrically coupled to bit line  112   a,  word line  110   c,  and ground plate  114 . Phase change memory cell  104   d  is electrically coupled to bit line  112   b,  word line  110   a,  and ground plate  114 . Phase change memory cell  104   e  is electrically coupled to bit line  112   b,  word line  110   b,  and ground plate  114 , and phase change memory cell  104   f  is electrically coupled to bit line  112   b,  word line  110   c,  and ground plate  114 . 
         [0025]    Each phase change memory cell  104  includes a phase change element  106  and a TFET  108 . In other embodiments, each memory cell  104  includes a CBRAM element  106 , MRAM element  106 , electrolyte element  106 , or other suitable resistive memory element  106 . Phase change memory cell  104   a  includes phase change element  106   a  and TFET  108   a.  One side of phase change element  106   a  is electrically coupled to bit line  112   a,  and the other side of phase change element  106   a  is electrically coupled to the drain of TFET  108   a.  The source of TFET  108   a  is electrically coupled to ground plate  114 . The gate of TFET  108   a  is electrically coupled to word line  110   a.  Phase change memory cell  104   b  includes phase change element  106   b  and TFET  108   b.  One side of phase change element  106   b  is electrically coupled to bit line  112   a,  and the other side of phase change element  106   b  is electrically coupled to the drain of TFET  108   b.  The source of TFET  108   b  is electrically coupled to ground plate  114 . The source of TFET  108   b  is shared with the source of TFET  108   a.  The gate of TFET  108   b  is electrically coupled to word line  110   b.    
         [0026]    Phase change memory cell  104   c  includes phase change element  106   c  and TFET  108   c.  One side of phase change element  106   c  is electrically coupled to bit line  112   a,  and the other side of phase change element  106   c  is electrically coupled to the drain of TFET  108   c.  The source of TFET  108   c  is electrically coupled to ground plate  114 . The source of TFET  108   c  is shared with the source of an adjacent TFET (not shown). The gate of TFET  108   c  is electrically coupled to word line  110   c.    
         [0027]    Phase change memory cell  104   d  includes phase change element  106   d  and TFET  108   d.  One side of phase change element  106   d  is electrically coupled to bit line  112   b,  and the other side of phase change element  106   d  is electrically coupled to the drain of TFET  108   d.  The source of TFET  108   d  is electrically coupled to ground plate  114 . The gate of TFET  108   d  is electrically coupled to word line  110   a.  Phase change memory cell  104   e  includes phase change element  106   e  and TFET  108   e.  One side of phase change element  106   e  is electrically coupled to bit line  112   b,  and the other side of phase change element  106   e  is electrically coupled to the drain of TFET  108   e.  The source of TFET  108   e  is electrically coupled to ground plate  114 . The source of TFET  108   e  is shared with the source of TFET  108   d.  The gate of TFET  108   e  is electrically coupled to word line  110   b.    
         [0028]    Phase change memory cell  104   f  includes phase change element  106   f  and TFET  108   f.  One side of phase change element  106   f  is electrically coupled to bit line  112   b,  and the other side of phase change element  106   f  is electrically coupled to the drain of TFET  108   f.  The source of TFET  108   f  is electrically coupled to ground plate  114 . The source of TFET  108   f  is shared with the source of an adjacent TFET (not shown). The gate of TFET  108   f  is electrically coupled to word line  110   c.    
         [0029]    Each phase change element  106  comprises a phase change material that may be made up of a variety of materials in accordance with the present invention. Generally, chalcogenide alloys that contain one or more elements from group VI of the periodic table are useful as such materials. In one embodiment, the phase change material of phase change element  106  is made up of a chalcogenide compound material, such as GeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase change material is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. In other embodiments, the phase change material is made up of any suitable material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, and S. 
         [0030]    During a set operation of phase change memory cell  104   a,  a set current or voltage pulse is selectively enabled and sent through bit line  112   a  to phase change element  106   a  thereby heating it above it&#39;s crystallization temperature (but usually below it&#39;s melting temperature) with word line  110   a  selected to activate TFET  108   a.  In this way, phase change element  106   a  reaches its crystalline state during this set operation. During a reset operation of phase change memory cell  104   a,  a reset current or voltage pulse is selectively enabled to bit line  112   a  and sent to phase change element  106   a.  The reset current or voltage quickly heats phase change element  106   a  above its melting temperature. After the current or voltage pulse is turned off, phase change element  106   a  quickly quench cools into the amorphous state. Phase change memory cells  104   b - 104   f  and other phase change memory cells  104  in memory array  100  are set and reset similarly to phase change memory cell  104   a  using a similar current or voltage pulse. 
         [0031]      FIG. 2  is a diagram illustrating one embodiment of phase change memory cell  104   a  and a portion of phase change memory cell  104   b.  In one embodiment, each phase change memory cell  104  in memory array  100  is similar to the embodiment of phase change memory cell  104   a  illustrated in  FIG. 2 . Phase change memory cell  104   a  includes bit line  112   a,  phase change element  106   a,  contact  120 , TFET  108   a  including source  122   a  and drain  124 , word line  110   a,  and a substrate including p region  126 , p+ source or ground plate region  114 , and p region  128 . The portion of memory cell  104   b  illustrated includes a portion of TFET  108   b  including source  122   a,  and word line  110   b.  Bit line  112   a  is electrically coupled to one side of phase change element  106   a.  The other side of phase change element  106   a  is electrically coupled to one side of contact  120 . The other side of contact  120  is electrically coupled to drain  124  of TFET  108   a.  Source  122   a  of TFET  108   a  is shared with TFET  108   b.  Word line  110   a  is electrically coupled to the gate of TFET  108   a,  and word line  110   b  is electrically coupled to the gate of TFET  108   b.  TFET  108   a  and TFET  108   b  are formed in p region  126 . Source  122   a  is p+ doped and drain  124  is n+ doped. P+ ground plate region  114  is adjacent p region  126 , and p region  128  is adjacent p+ ground plate region  114 . 
         [0032]    Source  122   a  of TFET  108   a  and TFET  108   b  extends to and contacts p+ region  114 . P+ region  114  acts as a source node or ground plate such that no additional source line or ground line and the associated contact to source  122   a  is used between word line  110   a  and word line  110   b  for coupling adjacent sources. Therefore, word lines  110   a  and  110   b  can be positioned closer together to reduce the overall memory array size and increase the storage density for the memory array. 
         [0033]      FIG. 3  illustrates another embodiment of phase change memory cell  104   a  and a portion of phase change memory cell  104   b.  In one embodiment, each phase change memory cell  104  in memory array  100  is similar to the embodiment of phase change memory cell  104   a  illustrated in  FIG. 3 . This embodiment is similar to the embodiment previously described and illustrated with reference to  FIG. 2 , except that in this embodiment, source  122   b  does not contact p+ ground plate region  114 . The distance between source  122   b  and p+ ground plate region  114  across p region  126  adds a series resistance between source  122   b  and p+ ground plate region  114 . 
         [0034]      FIG. 4  is a diagram illustrating another embodiment of phase change memory cell  104   a  and a portion of phase change memory cell  104   b.  In one embodiment, each phase change memory cell  104  in memory array  100  is similar to the embodiment of phase change memory cell  104   a  illustrated in  FIG. 4 . This embodiment is similar to the embodiment previously described and illustrated with reference to  FIG. 2 , except that in this embodiment, an n+region  130  is positioned between p+ ground plate region  114  and p region  128 . N+ region  130  isolates p+ ground plate region  114  from p region  128  to prevent noise from passing to p region  128  of the semiconductor wafer. In one embodiment, n+ region  130  also isolates TFETs  108  from source regions of periphery transistors outside memory array  100 , such as bit line selection transistors, which may have a different source bias. 
         [0035]      FIG. 5  is a diagram illustrating another embodiment of phase change memory cell  104   a  and a portion of phase change memory cell  104   b.  In one embodiment, each phase change memory cell  104  in memory array  100  is similar to the embodiment of phase change memory cell  104   a  illustrated in  FIG. 5 . This embodiment is similar to the embodiment previously described and illustrated with reference to  FIG. 4 , except that in this embodiment, source  122   b  does not contact p+ ground plate region  114 . The distance between source  122   b  and p+ ground plate region  114  across p region  126  adds a series resistance between source  122   b  and p+ ground plate region  114 . 
         [0036]      FIG. 6  is a diagram illustrating another embodiment of phase change memory cell  104   a  and a portion of phase change memory cell  104   b.  In one embodiment, each phase change memory cell  104  in memory array  100  is similar to the embodiment of phase change memory cell  104   a  illustrated in  FIG. 6 . This embodiment is similar to the embodiment previously described and illustrated with reference to  FIG. 2 , except that in this embodiment, an oxide/isolation region  132  is positioned between p+ ground plate region  114  and p region  128 . Oxide/isolation region  132  comprises SiO 2 , boro-phosphosilicate glass (BPSG), borosilicate glass (BSG), low-k material, or other suitable dielectric material. Oxide/isolation region  132  isolates p+ ground plate region  114  from p region  128  to prevent noise from passing to p region  128  of the semiconductor wafer. In one embodiment, oxide/isolation region  130  also isolates TFETs  108  from source regions of periphery transistors outside memory array  100 , such as bit line selection transistors, which may have a different source bias. 
         [0037]    In another embodiment, the doping types are reversed to provide p-channel TFETs  108  instead of n-channel TFETs  108 . In this embodiment, source  122   a  and source or ground plate region  114  are switched from p+ doping to n+ doping, drain  124  is switched from n+ doping to p+ doping, and region  126  is switched from p doping to n doping. 
         [0038]      FIG. 7  is a diagram illustrating another embodiment of phase change memory cell  104   a  and a portion of phase change memory cell  104   b.  In one embodiment, each phase change memory cell  104  in memory array  100  is similar to the embodiment of phase change memory cell  104   a  illustrated in  FIG. 7 . This embodiment is similar to the embodiment previously described and illustrated with reference to  FIG. 6 , except that in this embodiment, source  122   b  does not contact p+ ground plate region  114 . The distance between source  122   b  and p+ ground plate region  114  across p region  126  adds a series resistance between source  122   b  and p+ ground plate region  114 . 
         [0039]    Embodiments of the present invention provide TFET based resistive memory cells. Adjacent TFETs share a source region that is coupled to adjacent memory cells via a p+ ground plate region within the semiconductor wafer. Without source or ground lines and their associated contacts to the source regions of the TFETs, the word lines between adjacent memory cells can be positioned closer together. With the word lines positioned closer together, the memory cell size can be reduced thereby increasing the storage density of the memory. In addition, the TFETs reduce the static leakage current of the memory cells compared to memory cells that use MOSFETs, thereby reducing the power consumption of the memory. 
         [0040]    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.