Abstract:
A gate driver includes a gate driving logic circuit for generating a plurality of switch signals, a plurality of output modules each including a modulation circuit for responding to one of the plurality of switch signals to generate an intermediate signal at an intermediate terminal, a buffer for responding to the intermediate signal to generate a gate driving signal at an output terminal, and a modulation switch for determining an electric connection between the intermediate terminal and the output terminal. The modulation switch is turned on during a modulation period of the gate driving signal to modulate a waveform of the gate driving signal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a gate driver and a display apparatus using the same, and more particularly, to a gate driver and a display apparatus modulating a waveform of the gate driving signal by providing a discharging path. 
         [0003]    2. Description of the Prior Art 
         [0004]    A liquid crystal display (LCD) has advantages of light weight, low power consumption, low radiation contamination, etc., and is widely used in various information products, such as computer systems, cell phones, personal digital assistants (PDAs), etc. In an LCD monitor, incident light produces different polarization or refraction effects when the alignment of liquid crystal molecules is altered. Thus, the alignment of the liquid crystal molecules is utilized to control the light transmittance, and produce lights with different intensities and colors, such as red, green and blue lights. 
         [0005]    Please refer to  FIG. 1 , which illustrates a schematic diagram of a conventional thin film transistor (TFT) LCD apparatus  10 . The LCD apparatus  10  includes an LCD panel  100 , a source driver  102 , a gate driver  104  and a voltage generator  106 . The LCD panel  100  includes two substrates, and an LCD layer is filled between these two substrates. One substrate is disposed with a plurality of data lines  108 , a plurality of scan lines (gate lines)  110  perpendicular to the data lines  108 , and a plurality of TFTs  112 , while the other substrate is disposed with a common electrode for providing a common voltage Vcom generated by the voltage generator  106 . The TFTs  112  are disposed on the LCD panel  100  in matrix. Each data line  108  is corresponding to a column of the LCD panel  100 , each scan line  110  is corresponding to a row of the LCD panel  100 , and each TFT  112  is corresponding to a pixel. Besides, circuit characteristics of the two substrates of the LCD panel  100  can be seen as an equivalent capacitor  114 . 
         [0006]    In  FIG. 1 , the gate driver  104  sequentially generates gate driving signals VG_ 1 -VG_M for turning on each row of the plurality of TFTs  112 , so as to refresh pixel data stored in the equivalent capacitors  114 . In detail, please refer to  FIG. 2 , which illustrates a schematic diagram of the gate driver  104 . The gate driver  104  includes a logic circuit  105  and buffers  107 _ 1 - 107 _M. Load modules  109 _ 1 - 109 _M are equivalent circuits of each loads. The logic circuit  105  controls switches of transistors in the buffers  107 _ 1 - 107 _M, to connect the load modules  109 _ 1 - 109 _M to a high voltage source VGG and to a low voltage source VEE in turn, as square waves in the gate driving signals VG_ 1 -VG_M. 
         [0007]    However, due to parasitic capacitors existing between the equivalent capacitors  114  and the TFTs  112 , when the square waves are located at the trailing edges of the gate driving signals VG_ 1 -VG_M, voltage changes of the gate driving signals VG_ 1 -VG_M are coupled to the equivalent capacitors  114  via the parasitic capacitors, such that offset images are stored in the equivalent capacitors  114 . In order to improve coupling effects of the trailing edges, the gate driver  104  can re-arrange waveforms to adjust waveforms of the square waves in the gate driving signals VG_ 1 -VG_M, as shown in  FIG. 3 , where the trailing edges of the gate driving signals VG_ 1 -VG_M are modulated to avoid rapid changes of the gate driving signals VG_ 1 -VG_M affecting the stored pixel data. Certainly, in order to generate the modulated waveforms shown in  FIG. 3 , the gate driver  104  must include additional control circuits. 
         [0008]    Therefore, how to use an economical method to modulate the waveforms of the gate driver has become an important issue in the art. 
       SUMMARY OF THE INVENTION 
       [0009]    It is therefore an objective of the disclosure to provide a gate driver and a display apparatus using the same. 
         [0010]    In one aspect, a gate driver is disclosed, comprising a gate driving logic circuit for generating a plurality of switch signals, and a plurality of output modules, each comprising a modulation circuit, coupled between a first power supply and a second power supply, for responding to one of the plurality of switch signals, to generate an intermediate signal at an intermediate terminal, a buffer, coupled between the first power supply and the second power supply, for responding to the intermediate signal to generate a gate driving signal at an output terminal, and a modulation switch, coupled between the output terminal and the intermediate terminal, for controlling an electric connection between the output terminal and the intermediate terminal, wherein the modulation switch is turned on during a modulation period of the gate driving signal. 
         [0011]    In another aspect, a display apparatus is further disclosed, comprising the gate driver and a panel, for receiving controls of the gate driver to display images. 
         [0012]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  illustrates a schematic diagram of a conventional thin film transistor (TFT) LCD apparatus. 
           [0014]      FIG. 2  illustrates a schematic diagram of a gate driver of the TFT LCD apparatus shown in  FIG. 1 . 
           [0015]      FIG. 3  illustrates a sequence diagram of a gate driving signal. 
           [0016]      FIG. 4  illustrates a schematic diagram of a display apparatus according to the embodiment of the present invention. 
           [0017]      FIG. 5A  illustrates a schematic diagram of the gate driver shown in  FIG. 4  according to an embodiment of the present invention. 
           [0018]      FIG. 5B  illustrates a schematic diagram of the gate driver shown in  FIG. 4 . 
           [0019]      FIG. 5C  illustrates an operating sequence diagram of a switch signal, a control signal of a breaking switch, a control signal of a modulation switch and the gate driving signal of any output module in the gate driver shown in  FIG. 5B . 
           [0020]      FIG. 5D  illustrates a sequence diagram of related signals of the gate driver shown in  FIG. 5A . 
           [0021]      FIG. 6A  illustrates a schematic diagram of an alternation embodiment of the gate driver shown in  FIG. 5A . 
           [0022]      FIG. 6B  illustrates a sequence diagram of related signals of the gate driver shown in  FIG. 6A . 
           [0023]      FIG. 7A  and  FIG. 7B  illustrate schematic diagrams of an alternation embodiment of the gate driver shown in  FIG. 5A . 
           [0024]      FIG. 8  illustrates a sequence diagram of related signals of the gate driver shown in  FIG. 7A . 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    Please refer to  FIG. 4 , which illustrates a schematic diagram of a display apparatus  40  according to an embodiment of the present invention. The display apparatus  40  includes a panel  400  and a gate driver  410 . The gate driver  410  is utilized to generate a plurality of gate driving signals VG_ 1 -VG_M, to indicate sequences for updating display contents of pixels in each row of the panel  400 . Since the gate driving signals VG_ 1 -VG_M can scan thin film transistors (TFTs) of the panel  400  row by row, the gate driving signals VG_ 1 -VG_M can sequentially carry square waves. Detailed description will show how the gate driving signals VG_ 1 -VG_M are modulated to make trailing edges of each square wave gradually descend, thus having a cutting angle shape. After such modulating operation, coupling effects of the descending trailing edges of the gate driving signals VG_ 1 -VG_M can be improved, to solve offset images. 
         [0026]    Please refer to  FIG. 5A , which illustrates a schematic diagram of the gate driver  410  according to an embodiment of the present invention. The gate driver  410  includes a gate driving logic circuit  500  and output modules  510 _ 1 - 510 _M. The gate driving logic circuit  500  is utilized to generate switch signals SW 1 -SWM. The output modules  510 _ 1 - 510 _M include modulation circuits  512 _ 1 - 512 _M, buffers  514 _ 1 - 514 _M and modulation switches  516 _ 1 - 516 _M, respectively. The modulation circuits  512 _ 1 - 512 _M are utilized to respond to the switch signals SW 1 -SWM, respectively, to generate intermediate signals VM 1 -VM- 1 . The buffers  514 _ 1 - 514 _M are utilized to respond to the intermediate signals VM 1 -VM- 1 , respectively, to generate the gate driving signals VG_ 1 -VG_M. The modulation switches  516 _ 1 - 516 _M are utilized to provide discharging paths between output terminals NO 1 -NOM and intermediate terminals NM 1 -NMM, respectively. Besides, the gate driver  410  further includes a breaking switch  530  coupled between a first power supply  520  and each of the output modules  510 _ 1 - 510 _M. 
         [0027]    During a modulation period of each of the gate driving signals VG_ 1 -VG_M, the corresponding modulation switches SW 1 -SWM are turned on, respectively, to couple the output terminals NO 1 -NOM to a second power supply  522  via the modulation circuits  512 _ 1 - 512 _M, so as to modulate waveforms of the gate driving signals VG_ 1 -VG_M. Furthermore, during the modulation periods of the gate driving signals VG_ 1 -VG_M, the breaking switch  530  simultaneously turns off power supply paths from the first power supply  520  to the modulation circuits  512 _ 1 - 512 _M and the buffers  514 _ 1 - 514 _M. 
         [0028]    As can be seen, in comparison with the gate driver  104  shown in  FIG. 2 , the gate driver  410  additionally includes the modulation circuits  512 _ 1 - 512 _M and the modulation switches  516 _ 1 - 516 _M, to modulate the waveforms of the gate driving signals VG_ 1 -VG_M. At the trailing edges of the square waves in the gate driving signals VG_ 1 -VG_M, i.e. during the modulation periods, charges of load capacitors CL 1 -CLM in the panel  400  can discharge to the second power supply  522  via the modulation switches  516 _ 1 - 516 _M and the modulation circuits  512 _ 1 - 512 _M. Since such a discharging operation is a gradual process, the trailing edges of the square waves in the gate driving signals VG_ 1 -VG_M can gradually change, so as to alleviate the coupling effects. 
         [0029]    Please refer to  FIG. 5B , which illustrates a schematic diagram of the gate driver  410 , to show the detail circuit structure according to the modulation circuits  512 _ 1 - 512 _M and the output modules  510 _ 1 - 510 _M. Specifically, each of the modulation circuits  512 _ 1 - 512 _M includes a voltage pull-up block and a voltage pull-down block, such as first-type field effect transistors  513 _ 1 - 513 _M and second-type field effect transistors  515 _ 1 - 515 _M. The voltage pull-up block and the voltage pull-down block are controlled by the switch signals SW 1 -SWM, to output different voltage levels of the intermediate signals VM 1 -VMM, respectively. 
         [0030]    Furthermore, in the embodiment shown in  FIG. 5B , the modulation circuits  512 _ 1 - 512 _M have similar structures with the output modules  510 _ 1 - 510 _M. Each of the output modules  510 _ 1 - 510 _M includes a voltage pull-up block and a voltage pull-down block, such as first-type field effect transistors  518 _ 1 - 518 _M and second-type field effect transistors  519 _ 1 - 519 _M. The voltage pull-up block and the voltage pull-down block are controlled by the intermediate signals VM 1 -VMM, to output different voltage levels of the gate driving signals VG_ 1 -VG_M, respectively. Noticeably, although the modulation circuits  512 _ 1 - 512 _M and the output modules  510 _ 1 - 510 _M have similar structures, the present invention is not limited thereto. Any available structure can be used to implement the modulation circuits  512 _ 1 - 512 _M as long as they are able to provide the discharging paths from the gate driving signals VG_ 1 -VG_M to the second power supply  522  during the modulation period. 
         [0031]    Please refer to  FIG. 5C , which illustrates an operating sequence diagram of related signals of an arbitrary output module  510   —   i  (wherein i=1−M) in the gate driver  410  shown in  FIG. 5B  according to the embodiment of the present invention, which include a switch signal SWi, a control signal SWA_i of the breaking switch  530 , a control signal SWB_i of a modulation switch  516   —   i  and a gate driving signal VG_i. As shown in  FIG. 5C , at a period P 1 , the breaking switch  530  is turned on, the modulation switch  516   —   i  is turned off, the first-type field effect transistor  518   —   i  is turned on and the second-type field effect transistor  519   —   i  is turned off. At this moment, the first voltage V 1  controlling the first power supply  520  is charging the gate driving signal VG_i, such that the gate driver  410  charges the i-th line of the panel  400 . Next, at a period P 2 , the breaking switch  530  switches to off, the modulation switch  516   —   i  maintains off, the first-type field effect transistor  518   —   i  maintains on and the second-type field effect transistor  519   —   i  maintains off. At this moment, the breaking switch  530  can disconnect the first voltage V 1  of the first power supply  520 . Next, at a period P 3 , the breaking switch  530  maintains off, the modulation switch  516   —   i  switches to on, the first-type field effect transistor  518   —   i  is irrelevant and the second-type field effect transistor  519   —   i  maintains off. At this moment, the gate driving signal VG_i can be discharged by the modulation switch  516   —   i  and the second-type field effect transistor  515   —   i , a conducting period of the modulation switch  516   —   i  can be able to simultaneously adjusted to modulate the output waveform. 
         [0032]    Next, at a period P 4 , the breaking switch  530  maintains off, the modulation switch  516   —   i  switches to on, the first-type field effect transistor  518   —   i  is turned off and the second-type field effect transistor  519   —   i  switches on. Next, at a period P 5 , the breaking switch  530  maintains off, the modulation switch  516   —   i  switches to off, the first-type field effect transistor  518   —   i  maintains off and the second-type field effect transistor  519   —   i  maintains on. At this moment, the gate driving signal VG_i achieves a voltage level the same as the voltage level of the second power supply  522 , to finish the output waveform modulation. 
         [0033]    Next, at a period P 6 , the breaking switch  530  switches to on, the modulation switch  516   —   i  is turned off, the first-type field effect transistor  518   —   i  is turned off and the second-type field effect transistor  519   —   i  is turned on. At this moment, the first power supply  520  supplies the buffer  514   —   i  again, and the modulating operation continues as the sequence from the period P 1  to the period P 6 , to finish the subsequent driving operation. 
         [0034]    Noticeably, in order to isolate the first power supply  520 , as long as any of the modulation switches  516 _ 1 - 516 _M is ready for modulation, the breaking switch  530  has to be disconnected accordingly. Because the breaking switch  530  is shared by the output modules  510 _ 1 - 510 _M, the breaking switch  530  has to be disconnected during the modulation period of each of the gate driving signals VG_ 1 -VG_M. For example, please refer to  FIG. 5D , which illustrates a sequence diagram of the switch signals SWX, SWX+1, the breaking switch  530 , the modulation switches  516 _X,  516 _X+1 and the gate driving signals VG_X, VG_X+1 when modulating the gate driving signal VG_X, VG_X+1. The breaking switch  530  is disconnected at the period between t 1  and t 4  as well as at the period between t 5  and t 8 , the modulation switch  516 _X is disconnected at the period between t 2  and t 3 , and the modulation switch  516 _X+1 is disconnected at the period between t 6  and t 7 . As a result, the gate driving signals VG_X and VG_X+1 gradually descend from the level of the first voltage V 1  of the first power supply  520  at the period between t 2  and t 3  as well as the period between t 6  and t 7 . 
         [0035]    The breaking switch  530  shown in  FIG. 5A  is shared by the output modules  510 _ 1 - 510 _M, and the present invention is not limited thereto. In other embodiments, the output modules  510 _ 1 - 510 _M can include individual breaking switches  630 _ 1 - 630 _M, as shown in  FIG. 6A . In such a circumstance, the breaking switches  630 _ 1 - 630 _M are sequentially disconnected at the corresponding modulation periods of the source driving signals VG_ 1 -VG_M, i.e. during the turn-on periods of the modulation switches  516 _ 1 - 516 _M, as shown in  FIG. 6B . Noticeably, the modulation switches  516 _ 1 - 516 _M, shown in either  FIG. 5A  or  FIG. 6A , are controlled by the modulation signal generated by the gate driving logic circuit  500 . The modulation signal is at a turn-on control mode at the corresponding modulation period of the gate driving signal, which is a well-known skill in the art, and is not narrated hereinafter. 
         [0036]    Moreover, the output modules  510 _ 1 - 510 _M, shown in  FIG. 5A  or in  FIG. 6A , can further include local modulation switches  718 _ 1 - 718 _M, respectively, as shown in  FIG. 7A  and  FIG. 7B . Preferably, the local modulation switches  718 _ 1 - 718 _M are controlled by the local modulation signals, respectively, and the local modulation signals can be inversion signals of the corresponding gate driving signals VG_ 1 -VG_M. For example, when modulating the gate driving signals VG_X and VG_X+1, controls of the local modulation signals LM_X and LM_X+1 of the local modulation switches  718 _X and  718 _X+1 are the inversion phase signals of the gate driving signals VG_X and VG_X+1, as shown in  FIG. 8 . In such a circumstance, the modulation switches  516 _ 1 - 516 _M are control by an universal modulation signal. The universal modulation signal is at a turn-on controlled mode during all the modulation periods of the gate driving signals. 
         [0037]    In the prior art, voltage changes of the gate driving signals VG_ 1 -VG_M are coupled to the equivalent capacitors  114  via parasitic capacitors, making the equivalent capacitors  114  store the offset images, such that waveform re-arrangement is needed to alleviate the coupling effects. In comparison, the embodiments use switches to turn off the power supply at the trailing edges of the gate driving signals VG_ 1 -VG_M, and provide a discharging path for the load capacitors CL 1 -CLM via the modulation circuits  510 _ 1 - 510 _M and the modulation switches  516 _ 1 - 516 _M, such that the gate driving signals VG_ 1 -VG_M gradually descend to alleviate the coupling effects. 
         [0038]    In summary, the embodiments can, on a premise that no additional complex control circuits are required, provide a discharging path for the load capacitors, so as to allow the trailing edge of the gate driving signal to descend gradually. Therefore, the embodiments can realize modulation in an economic and power-saving way. 
         [0039]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.