Abstract:
A bandgap reference circuit that uses reduced substrate area while requiring relatively low voltage. The circuit may include a bipolar transistor with a resistor electrically connected across the emitter-base of the bipolar transistor. The resistor sums a first current with a second current and also generates a fractional V EB . The bandgap reference circuit may have a first current proportional to V EB , and a second current proportional to a PTAT current. An impedance booster may be incorporated into the circuit. Also disclosed is a method of regulating a voltage level using embodiments of the bandgap reference circuit.

Description:
This application is based on provisional application having Ser. No. 60/247,367, having a filing date of Nov. 9, 2000, and entitled Bandgap Reference Circuit for V DD =0.75 V in a 0. 16 μm Digital CMOS. 
    
    
     BACKGROUND OF THE INVENTION 
     As CMOS technologies continue to migrate into deep submicron region, the power supply voltage will likewise scale to below 1.5 V for reliable operation of devices. In various hand-held and/or wireless devices it is advantageous for the supply voltage to be reduced even further to keep power consumption and weight low. As an essential and integral part of more and more very large scale integration circuit systems, a temperature-compensated (or commonly called bandgap) reference circuit that works with supply voltages below 1.5 V is desired. 
     FIG. 1 shows a simplified diagram of a conventional CMOS bandgap reference circuit. The closed loop of on operational amplifier A 0  forces the voltages at nodes PT and Q 2 E to be equal, resulting in a bandgap reference voltage            V   REF     =           R   0       R   PT            ln        (       a   E          m   2       )            V   T       +     V   EB2         ,                          
     where a E  is the ratio of emitter areas of Q 1  over Q 2 , and M 2  is the current ratio, I 2 /I 1 . V τ =kT/q, the thermal voltage, has a positive temperature coefficient and V EB  has a negative temperature coefficient of about −2MV/°C. Satisfying the condition dV REF /dT=0 for T=T 0  usually results in V RFF ≈1.2 V with a E =8, M 2  =1. Allowing some voltage drop across the current sources M 1  and M 2 , the minimum supply voltage will typically be V DD ≧1.5 V. 
     The minimum supply voltage required to properly operate this circuit is V DD ≧V REF +V SD  since V REF &gt;V EB2 . A common technique to lower the minimum V DD  is to generate a Proportional To Absolute Temperature (“PTAT”) current and a current proportional to V EB , and then sum the two currents into a resistor to generate a bandgap voltage that may contain only a fraction of a V EB  instead of a whole V EB  voltage. This is commonly referred as a fractional V EB  bandgap reference. 
     Bandgap a reference circuits with minimum supply voltages of V DD ≧0.9 V have been achieved. A first technique results in a bandgap reference voltage V REF &gt;V EB , which limits the supply voltage to V DD ≧0.9 V. A second technique predicted a lowering of supply voltage to V DD ≧0.85 V, but achieves only V DD ≧2.1 V due to technology limitations. The second technique requires that two resistors be connected across the emitter-base terminals of two separate PNP transistors to generate a whole V EB  current and sum it with a PTAT current. It then forces the resultant current through a third resistor to produce an appropriate bandgap reference voltage. For a given voltage drop, V 0 , across a resistor having a current, I 0 , flowing through, the resistance of the resistor is R 0 =V EB /I 0 . Therefore, the total resistance of the two resistors connected across the emitter-base terminals of two separate PNP transistors is            R   t     =     2          V   EB       I   0           ,                          
     whee I 0  is the current flowing through each resistor. For example, I 0 =1 μA (10 −6 A) and V EB =0.7 V results in R 1 =1,400,000Ω. In integrated circuit technologies, chip area needed to implement a resistor is directly proportional to the total resistance of the resistor. Therefore, additional resistors or resistances requires additional chip area. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention provide a bandgap reference circuit that may use reduced substrate area compared to prior art bandgap reference circuits, while requiring relatively low voltage. A first embodiment of the invention includes a bipolar transistor with a resistor electrically connected across the emitter-base of the bipolar transistor. The resistor sums a first current with a second current and also generates a fractional V EB . 
     In an illustrative embodiment of the invention the bandgap reference circuit has a first current is proportional to V EB , and a second current proportional to a PTAT current. 
     In a further embodiment of the invention the bandgap reference circuit has an impedance booster. 
     The present invention also includes a method of regulating a voltage level using embodiments of the bandgap reference circuit. 
    
    
     DESCRIPTION OF THE FIGURES 
     The invention is best understood from the following detailed description when read with the accompanying drawings. 
     FIG. 1 shows a diagram of a prior art CMOS bandgap reference circuit. 
     FIG. 2 depicts a CMOS bandgap reference circuits according to an illustrative embodiment of the invention. 
     FIGS. 3 a-c  depict illustrative circuit diagrams of a simple current source, a cascoded current source, and a cascoded current source with impedance boosting, respectively, that may be used in embodiments of the invention. 
     FIG. 4 depicts a circuit with impedance boosting according to an illustrative embodiment of the invention. 
     FIG. 5 depicts an illustrative operational amplifier that may be used in an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Embodiments of the invention provide a bandgap reference circuit with a supply voltage lower than that of the prior art, and capable of being fabricated using less area than prior art circuits. The area savings is achieved by having a single resistor consisting of at least two segments connected in series across the emitter-base terminals of a PNP transistor to generate a fractional V EB  current and also to sum it with a PTAT current to generate a bandgap reference voltage. This is in contrast to prior art circuits that requires two separate PNP transistors to accomplish both of these tasks. 
     FIG. 2 depicts a CMOS bandgap reference circuit using a fractional V BE  for low V DD  applications according to an illustrative embodiment of the invention. The left hand portion of FIG. 2 represents a bandgap reference circuit  200  which functions in an analogous manner to that which is depicted in FIG.  1 . FIG. 2 further depicts circuitry providing a fractional V BE  bandgap reference. The circuit may be configured to use less chip area because only one resistor, preferably consisting of two segments, R B  and R E , in series is required to be connected across the emitter-base terminals of a PNP transistor, Q 3 , and this resistor both generates a fractional V EB . current and sums it with a PTAT current to produce a bandgap reference voltage. The total resistance of this resistor is R B +R E . If current I 0 =1 μA (10 −6 A) is required to flow through it, and V EB =0.7 V, then the total resistance is R t   =7OO,OOO  Ω, which is half of the resistance required in prior art circuits without considering the third resistor also needed in the prior circuits. The fractional V EB  bandgap reference additionally includes PMOS device M 3 , the gate of which is connected to the gate of PMOS device M 4  and to the gates of PMOS devices M 1  and M 2 . M 3  and M 4  are commonly referred to as current mirrors of M 1  or M 2 . M 4  supplies the PTAT current to the node V REF  to be summed with a fractional V EB  current by the resistor segment R B , and therefore, the mirroring action must be accurate to guarantee low-sensitivity to temperature variation. M 3  only needs to supply sufficient current to node Q 3 E. The base terminal of the PNP transistor Q 3  is connected to V SS  as are also the base terminals of Q 1  and Q 2 . The source terminals of PMOS devices M 1 , M 2 , M 3 , and M 4  are all connected to the voltage supply node, V DD . 
     The single resistor consisting of two segments R E  and R B in series is connected between the emitter and base terminals of PNP transistor Q 3 . By injecting a PTAT current, I 4 , directly into the node V REF  the resistors R B  and R E  perform both tasks of the generation of a fractional V EB  current and the summation of two currents, with opposite temperature coefficients. 
     The voltage across R B  is            V   REF     =           M   3       χ     BE   +   1                R   B       R   PT            In        (       a   E          m   2       )            V   T       +         χ   BE       χ     BE   +   1              V   BE3           ,                          
     where X BE =R B /R E  is the resistor ratio. The efficient use of resistors R B  and R E  means only one resistor of a total resistance (R B +R E ) is connected across a single V EB  voltage, as compared to two such configurations in prior art circuits. Considering that the resistance elements usually take up {fraction (b  1 / 4 )} to ⅓ of the area of a bandgap reference circuit in digital CMOS technologies. 
     The minimum supply voltage for proper operation of the circuit is V DD ≧V EB +V SD  if the V REF &lt;V EB  is chosen for the lower portion of the interested temperature range where V EB  is large enough by choosing proper values of X BE . In order to lower V DD  further, one needs to reduce either V EB  or V SD , or both. Since lowering V EB  requires increasing the emitter area and/or lowering I PTAT  by increasing R PT , the silicon area required increases dramatically because V EB ∝lnI 0 /A. Reducing V SD  of PMOS transistors that implement the current mirrors runs the risk of increased mismatch among the PTAT currents I 1 , I 2 , and I 4  because of the decreased output resistance of the current sources. For this reason, the minimum supply voltage for the circuit has been limited at V DD ≧0.85 V for V EB ≦0.7 V. 
     To overcome the mismatch problem in the current sources, an impedance boosting technique may be used. FIGS. 3 a-c  show illustrative circuit diagrams of a simple current source, a cascoded current source, and a cascoded current source with impedance boosting, respectively. The expressions for their output impedances are provided in FIGS. 3a-c as R oa , R ob  and R oc respectively. V BP1  and V BP2  are bias voltages. In the embodiment depicted in FIG. 3 c , a gain stage increases the output impedance of the circuit by the gain of the operational amplifier A 1 , compared to the current source in FIG. 3 b . For a given output voltage V A . There may be situations of R o1a &gt;R o1b , R o2b , R o1c , R o2c , or even R oa &gt;R ob . With the additional gain stage A 1  inserted as in FIG.  3 ( c ), however, R oc &gt;&gt;R ob , R oa  can be achieved by the gain, A 1 . This enables the reduction of the total voltage drop across the cascoded current source, and therefore, further lowering of the supply voltage, V DD , while still maintaining good matching of the PTAT currents I 1 , I 2 , and I 4 . With V EB2 &lt;0.7 V, a bandgap reference circuit with a minimum V DD ≧0.75 V can be designed. 
     An illustrative circuit diagram with impedance boosting is shown in FIG. 4 (the start-up circuit is not shown). An illustrative operational amplifier is shown in FIG.  5 . There are slight differences between operational amplifiers A 1  and A 2  due to different gain and offset requirements, but the basic topology may be the same. The folded-cascode operational amplifier topology allows low voltage implementation. In an exemplary embodiment of invention, the bandgap reference circuit and/or the independence booster is implemented in 0.16 μm digital CMOS technology. 
     The illustrative circuit of FIG. 4 may be described as follows. Voltage supply V DD  is connected to sources of CMOS devices M 1 , M 2 , M 3  and M 4 . Drains of CMOS devices M 1  and M 2  are connected to the negative terminals of operational amplifiers A 1  and A 2 , respectively. Outputs of operational amplifiers A 1  and A 2  are connected to the gates of CMOS devices M 5  and M 6 , respectively. Voltage V BP  is connected to the gate of CMOS device M 1  and the output of operational amplifier A 4 . Voltage V X is provided to the positive terminals of operational amplifiers A 1 , A 2  and A 3 . Drains of CMOS devices M 5  and M 6  are connected to nodes PT and Q 2E . respectively. Resistor R PT  is connected to the emitter of transistor Q 1  and node PT. Voltage V SS  is connected to the base of transistors Q 1 , Q 2  and Q 3 . The non-inverting terminal of operational amplifier A 4  is connected to node Q 2 E, as are also the drain of device M 6  and emitter of transistor Q 2 . A drain of CMOS device M 3  is connected to the source of CMOS device M 7 . The drain of CMOS device M 7  is connected to node Q 3 E, as are also resistor R E  and the emitter of transistor Q 3 . A node at V REF  is connected to resistors R E  and R B , and the drain of CMOS device M 8 . The gate of CMOS device M 8  is connected to the output of operational amplified A 3 . The negative terminal of operational amplifier A 3  is connected to the source of CMOS device M 8  and the drain of CMOS device M 4 . Resistor R B  is further connected to the base of transistor M 3 . 
     The operational amplifier circuit diagram of FIG. 5 may be described as follows. Voltage supply V DD  is connected to the sources of CMOS devices M 15  and M 16 . Gates of CMOS devices M 15  and M 1   16  are connected to one another and further to voltage V BP1 . Drains of CMOS devices M 15  and M 16  are connected to the drains of CMOS devices M 11  and M 12 . CMOS devices M 11  and M 12  have sources connected to one another and further to the source of CMOS device M 10 . Voltage V SS  is connected to the sources of CMOS devices M 10 , M 13  and M 14 . The gate of CMOS device Mio is connected to V 2N1 , V BP2  is connected to the gates of CMOS devices M 17  and M 18 . Voltage V OUT  is connected to CMOS devices M 17  and M 13 . 
     FIG. 4 shows plots of the measured bandgap voltage vs. temperature for V DD =0.75 and 1.0 V. It shows a stable reference voltage at about 0.57 V over a temperature range −45° to 125° C. The resistor ratio, X BE =1 and current ratios m 2 =m 4 =1 are chosen. The variation of the reference voltage over the temperature range is 17 mVolts. The power supply rejection is about 20 dB at 100 kHz for V DD =0.75 V. Measurements of devices from several wafers have shown quite consistent results. 
     In an illustrative embodiment of the invention, the bandgap reference circuit has a supply voltage of less than about 0.80 V. More preferably the supply voltage is less than about 0.75 V, and most preferably less than about 0.70 V. 
     Further embodiments include a method of regulating a voltage level using the techniques and circuits described above. 
     While the invention has been described by illustrative embodiments, additional advantages and modifications will occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to specific details shown and described herein. Modifications, for example, to circuit configurations and components, may be made without departing from the spirit and scope of the invention. Accordingly, it is intended that the invention not be limited to the specific illustrative embodiments but be interpreted within the full spirit and scope of the appended claims and their equivalents.