Abstract:
A simplified tri-layer process for forming a thin film transistor matrix for a liquid crystal display is disclosed. By using a backside exposure technique, the masking step for patterning an etch stopper layer can be omitted. After forming an active region including a gate electrode and a scan line on the front side of a substrate, and sequentially applying an etch stopper layer and a photoresist layer over the resulting structure, the backside exposure is performed by exposing from the back side of the substrate. A portion of photoresist is shielded by the active region from exposure so that an etch stopper structure having a shape similar to the shape of the active region is formed without any photo-masking and lithographic procedure. Therefore, the above self-aligned effect allows one masking step to be reduced so as to simplify the process.

Description:
FIELD OF THE INVENTION 
     The present invention relates to a process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), and more particularly to a simplified tri-layer process for forming the TFT matrix with reduced masking steps. 
     BACKGROUND OF THE INVENTION 
     For conventional manufacturing processes of a TFTLCD, a tri-layer process and a back channel etch (BCE) process are main streams for forming the TFT matrix. Compared to a BCE structure, a tri-layer structure additionally includes an top nitride over the semiconductor layer as an etch stopper so that the etching step for defining a source/drain and channel region can be well controlled. Accordingly, the thickness of the active layer can be made to be thinner in the tri-layer structure than in the BCE structure, which is advantageous for the stability of resulting devices and performance in mass production. However, the provision of the additional etch stopper layer needs an additional masking step, thereby making the tri-layer process relatively complicated. 
     Conventionally, six to nine masking steps are required for either a BCE process or a tri-layer process. As known, the count of photo-masking and lithography steps directly affects not only the production cost but also the manufacturing time. Moreover, for each photo-masking and lithography step, the risks of mis-alignment and contamination may be involved so as to affect the production yield. Therefore, many efforts have been made to improve the conventional processes to reduce masking steps. 
     For example, for a BCE structure, U.S. Pat. Nos. 5,346,833 and 5,478,766 issued to Wu and Park et al., respectively, disclose 3 and/or 4-mask processes for making a TFTLCD, which are incorporated herein for reference. By the way, it is to be noted that the 3-mask process for each of Wu and Park et al. does not include the step of forming and patterning of a passivation layer. If a passivation layer is required to assure of satisfactory reliability, the count of photo-masking and lithography steps should be four. 
     As for the tri-layer structure, a conventional 6-mask process is illustrated as follows with reference to FIGS.  1 A˜ 1 G which are cross-sectional views of intermediate structures at different stages. The conventional process includes steps of: 
     i) applying a first conductive layer onto a glass substrate  10 , and using a first photo-masking and lithography procedure to pattern and etch the first conductive layer to form an active region  11  consisting of a scan line and a gate electrode of a TFT unit, as shown in FIG. 1A; 
     ii) sequentially forming tri-layers including an insulation layer  121 , a semiconductor layer  122  and an etch stopper layer  123 , and a photoresist  124  on the resulting structure of FIG. 1A, as shown in FIG.  1 B. 
     iii) using a second photo-masking and lithography procedure to pattern and etch the etch stopper layer  123  to form an etch stopper  13  which have a shape similar to the shape of the gate electrode, as shown in FIG. 1C; 
     iv) using a third photo-masking and lithography procedure to pattern and etch the semiconductor layer  122  to form a channel structure  14 , as shown in FIG. 1D; 
     v) sequentially applying a doped semiconductor layer and a second conductive layer on the resulting structure of FIG. 1D, and using a fourth photo-masking and lithography procedure to pattern and etch them to form source/drain regions  15  and data and connection lines  16 , as shown in FIG. 1E; 
     vi) applying a passivation layer  17  on the resulting structure of FIG. 1E, and using a fifth photo-masking and lithography procedure to pattern and etch the passivation layer  17  to create tape automated bonding (TAB) openings (not shown), and create a contact window  18 , as shown in FIG. 1F; and 
     vii) applying a transparent electrode layer on the resulting structure of FIG. 1F, and using a sixth photo-masking and lithography procedure to pattern and etch the transparent electrode layer to form a pixel electrode  19 , as shown in FIG.  1 G. 
     Six masking steps, however, are still too complicated. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a reduced mask process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which the count of photo-masking and lithography steps can be reduced to five, or even four. 
     According to a first aspect of the present invention, a process for forming a TFT matrix for an LCD includes steps of: providing a substrate made of an insulating material; forming a first conductive layer on a first side of the substrate, and using a first masking and patterning procedure to remove a portion of the first conductive layer to define a scan line and a gate electrode of a TFT unit; successively forming an insulation layer, a semiconductor layer, an etch stopper layer, and a photoresist layer on the substrate with the scan line and the gate electrode; providing an exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as a shield to obtain an exposed area and an unexposed area; removing the photoresist, and the etch stopper layer of the exposed area so that the remaining portion of the etch stopper layer in the unexposed area has a specific shape substantially identical to the shape of the scan line together with the gate electrode; successively forming a doped semiconductor layer and a second conductive layer on the substrate with the etch stopper layer of the specific shape, and using a second masking and patterning procedure to remove a portion of the second conductive layer to define data and connection lines; removing a portion of the doped semiconductor layer with a remaining portion of the second conductive layer as a shield to define source/drain regions and a channel region; forming a passivation layer on the substrate, and using a third masking and patterning procedure to remove a portion of the passivation layer to define a contact window; and forming a transparent conductive layer on the substrate, and using a fourth masking and patterning procedure to remove a portion of the transparent conductive layer to define a pixel electrode region. 
     When the exposing source is a light radiation, the insulating material is a light-transmitting material such as glass. 
     Preferably, the first conductive layer is formed of chromium, tungsten molybdenum, tantalum, aluminum or copper. 
     Preferably, the insulation layer is formed of silicon nitride, silicon oxide, silicon oxynitride, tantalum oxide or aluminum oxide. 
     Preferably, the etch stopper layer and the semiconductor layer have a high etching selectivity for respective etching gases. For example, the semiconductor layer is formed of intrinsic amorphous silicon, micro-crystalline silicon or polysilicon. An etching gas for the semiconductor layer is selected from a group consisting of carbon tetrafluoride, boron trichloride, chlorine, sulfur hexafluoride, and a mixture thereof. The etch stopper layer is formed of silicon nitride, silicon oxide or silicon oxynitride. The etching gas for the etch stopper layer is selected from a group consisting of carbon tetrafluoride/hydrogen, trifluoromethane, sulfur hexafluoride/hydrogen, and a mixture thereof. 
     Preferably, the doped semiconductor layer is formed of highly amorphous silicon, highly micro-crystalline silicon or highly polysilicon. 
     Preferably, the second conductive layer is a Cr/Al or a Mo/Al/Mo composite layer. 
     Preferably, the transparent conductive layer is formed of indium tin oxide, indium zinc oxide or indium lead oxide. 
     Preferably, the passivation layer is formed of silicon nitride or silicon oxynitride. 
     Preferably, after removing the another portion of the second conductive layer after the fourth masking and patterning procedure, a remaining portion of the second conductive layer surrounds the pixel electrode region as black matrix. 
     According to a second aspect of the present invention, a process for forming a TFT matrix for an LCD includes steps of: providing a substrate made of an insulating material; forming a first conductive layer on a first side of the substrate, and using a first masking and patterning procedure to remove a portion of the first conductive layer to define a scan line and a gate electrode of a TFT unit; successively forming an insulation layer, a semiconductor layer, an etch stopper layer, and a photoresist layer on the substrate with the scan line and the gate electrode; providing an exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as a shield to obtain an exposed area and an unexposed area; removing the photoresist and the etch stopper layer of the exposed area so that the remaining portion of the etch stopper layer in the unexposed area has a specific shape substantially identical to the shape of the scan line together with the gate electrode; using a second masking and patterning procedure to remove another portion of the etch stopper layer of the specific shape, and then removing a portion of the semiconductor layer to define a channel region; successively forming a doped semiconductor layer and a second conductive layer on the substrate, and using a third masking and patterning procedure to remove a portion of the second conductive layer to define data and connection lines; removing a portion of the doped semiconductor layer with the remaining portion of the second conductive layer and the etch stopper layer as a shield to define source/drain regions; forming a passivation layer on the substrate, and using a fourth masking and patterning procedure to remove a portion of the passivation layer to define a contact window; and forming a transparent conductive layer on the substrate, and using a fifth masking and patterning procedure to remove a portion of the transparent conductive layer to define a pixel electrode region which is connected to the data and connection lines through the contact window. 
     Preferably, the insulating material is glass; the first conductive layer is selected from a chromium, a tungsten molybdenum, a tantalum, an aluminum and a copper layers; the second conductive layer is selected from a Cr/Al and a Mo/Al/Mo composite layers; the insulation layer is formed of a material selected from silicon nitride, silicon oxide, silicon oxynitride, tantalum oxide and aluminum oxide; the semiconductor layer is formed of a material selected from amorphous silicon, micro-crystalline silicon and polysilicon; the etch stopper layer is formed of a material selected from silicon nitride, silicon oxide and silicon oxynitride; the doped semiconductor layer is formed of a material selected from highly doped amorphous silicon, micro-crystalline silicon and polysilicon; the passivation layer is formed of a material selected from silicon nitride and silicon oxynitride; and the transparent conductive layer is formed of a material selected from indium tin oxide, indium zinc oxide and indium lead oxide. 
     According to a third aspect of the present invention, a process for forming a TFT matrix for an LCD includes steps of: providing a glass substrate; forming a first conductive layer on a first side of the substrate, and using a first masking and patterning procedure to remove a portion of the first conductive layer to define a scan line and a gate electrode of a TFT unit; successively forming a lower silicon nitride layer, an intrinsic amorphous silicon layer, an upper silicon nitride layer, and a photoresist layer on the substrate with the scan line and the gate electrode; providing an exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as a shield to obtain an exposed area and an unexposed area; removing the photoresist and the upper nitride silicon layer of the exposed area so that the remaining portion of the upper silicon nitride layer in the unexposed area has a specific shape substantially identical to the shape of the scan line together with the gate electrode, and functions as an etch stopper structure; successively forming a highly doped n + -microcrystalline silicon layer and a second conductive layer on the substrate, and using a second masking and patterning procedure to remove a portion of the second conductive layer to define data and connection lines and an isolation window area; removing a portion of the highly doped n + -microcrystalline silicon layer and a portion of the intrinsic amorphous silicon layer with the remaining portion of the second conductive layer and the etch stopper structure as a shield to define source/drain regions and a channel region; forming a further silicon nitride layer as a passivation layer on the substrate, and using a third masking and patterning procedure to remove a portion of the passivation layer to define a contact window and to expose the isolation window area; removing a portion of the etch stopper structure and another portion of the intrinsic amorphous silicon layer in the isolation window area with the remaining portion of the passivation layer as a shield to form an isolation window for cutting off the connection of the TFT unit with the data line through the intrinsic amorphous silicon layer; and forming a transparent conductive layer on the substrate, and using a fourth masking and patterning procedure to remove a portion of the transparent conductive layer to define a pixel electrode region which is connected to the data and connection lines through the contact window. There exists a proper etching selectivity between the upper silicon nitride layer and the intrinsic amorphous silicon layer so that the etching procedure of the upper silicon nitride layer will not damage the intrinsic amorphous silicon layer. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The present invention may best be understood through the following description with reference to the accompanying drawings, in which: 
     FIGS.  1 A˜ 1 G are cross-sectional views of intermediate structures of a conventional TFTLCD, which schematically show the formation of the TFT matrix; 
     FIGS.  2 A˜ 2 K are cross-sectional views of intermediate structures of a TFTLCD according to the present invention, which schematically show a first preferred embodiment of a process for forming the TFT matrix; 
     FIGS.  3 A˜ 3 C are partial top plane views corresponding to the structures of FIGS. 2B,  2 E and  2 H, respectively; 
     FIGS.  4 A˜ 4 K are cross-sectional views of intermediate structures of a TFTLCD according to the present invention, which schematically show a second preferred embodiment of a process for forming the TFT matrix; and 
     FIGS.  5 A˜ 5 C are partial top plane views corresponding to the structures of FIGS. 4B,  4 G and  4 I, respectively;. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following description of the preferred embodiment of this invention is presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed. 
     A first preferred embodiment of a process for forming a TFT matrix of a TFTLCD according to the present invention directs to a five-mask process, and it is illustrated with reference to FIGS.  2 A˜ 2 H. It is to be noted that the division of steps and the provision of serial numbers as below are for corresponding to the drawings, and for easy illustration and understanding, instead of critically indicating the separation or the integration of steps. The preferred embodiment of the process includes steps of: 
     i) applying a Cr layer  21  onto a front side  201  of a glass substrate  20  as a first conductive layer, as shown in FIG. 2A; 
     ii) using a first photo-masking and lithography procedure to pattern and etch the Cr layer  21  to form an active region  31  consisting of a scan line  311  and a gate electrode  312  of a TFT unit, as shown in FIGS. 2B and 3 wherein FIG. 2B is a cross-sectional view taken along the A—A line of FIG. 3A; 
     iii) consecutively and sequentially forming a silicon nitride layer  221  as an insulation layer, an intrinsic amorphous silicon (i-a-Si) layer  222  as a semiconductor layer, a top silicon nitride layer  223  as an etch stopper layer, and a photoresist  224  on the resulting structure of FIG. 2B, as shown in FIG. 2C, and exposing the resulting structure from the back side  202  of the substrate  20 , as indicated by arrows, wherein a portion of the photoresist  224  above the region  31  is shielded by the region  31  from exposure so as to exhibit a self-aligned effect; 
     iv) etching off the exposed photoresist  224 , a portion of the top silicon nitride layer  223  thereunder, and the remaining photoresist so that the remaining etch stopper structure  23  has a shape substantially identical to the region  31 , as shown in FIG.  2 D and with reference to FIG. 3B; 
     v) using a second photo-masking and lithography procedure to remove the portion of the etch stopper structure  23  outside a second masking region and then a portion of the i-a-Si layer  222  to define a channel structure  24 , as shown in FIG. 2E, wherein the second masking region is schematically shown in FIG. 3B; 
     vi) sequentially applying an n +  amorphous silicon layer  225  and a Cr/Al composite layer  226  on the resulting structure of FIG. 2E as a highly doped semiconductor layer and a second conductive layer, respectively, as shown in FIG. 2F; 
     vii) using a third photo-masking and lithography procedure to pattern and etch the Cr/Al composite layer  226  to define data and connection lines including a data line  26   a , a first connection line  26   b  and a second connection line  26   c , as shown in FIG. 2G; 
     viii) using the remaining Cr/Al layer and etch stopper structure as a shield to etch off a portion of the n +  amorphous silicon layer  225  to define source/drain regions  25 , as shown in FIG.  2 H and FIG. 3C, where the TFT unit  32  is formed and connected to the data line  26   a  via the connection line  26   b;    
     ix) applying a silicon nitride layer  227  on the resulting structure of FIG. 2H as a passivation layer, and using a fourth photo-masking and lithography procedure to pattern and etch the passivation layer  227  to create a contact window  27  to expose a portion of the connection line  26   c , as shown in FIG. 2I, and also to define a tape automated bonding (TAB) openings (not shown); 
     x) applying an ITO layer  229  on the resulting structure of FIG. 2I as a transparent conductive layer, as shown in FIG. 2J; and 
     xi) using a fifth photo-masking and lithography procedure to pattern and etch the ITO layer  229  to form a pixel electrode  29  which is connected to the TFT unit  32  through the connection line  26   c , as shown in FIG.  2 K. 
     In the step i) of the above embodiment, the first conductive layer  21  can be applied by any suitable conventional technique which is not to be redundantly described here. In this embodiment, the substrate  20  is formed of glass which is transparent for allowing light type of exposing source to transmit therethrough. The substrate  20 , however, can also be made of another transparent, translucent or opaque material, depending on the type of the exposing source. On the other hand, the first conductive layer  21  can also be formed of tungsten molybdenum, tantalum, aluminum or copper. 
     In the step ii) of the above embodiment, the photo-masking and lithography procedure can be performed by any suitable conventional technique which is not to be redundantly described here. 
     In the step iii) of the above embodiment, the insulation layer  221 , semiconductor layer  222 , etch stopper layer  223  and photoresist  224  can be applied by any suitable conventional techniques which are not to be redundantly described here. The insulation layer  221  can also be formed of silicon oxide, silicon oxynitride, tantalum oxide or aluminum oxide. The semiconductor layer  222  can also be formed micro-crystalline silicon or polysilicon. The etch stopper layer  223  can also be formed of silicon oxide or silicon oxynitride. It is to be noted that the there preferably exists a high etching selectivity between the silicon nitride etching stopper layer  223  and the semiconductor layer  222  so that the etching procedure of the etch stopper layer will not damage the semiconductor layer. The etching gas for the semiconductor layer is selected from a group consisting of carbon tetrafluoride (CF 4 ), boron trichloride (BCl 3 ), chlorine (Cl 2 ), sulfur hexafluoride (SF 6 ), and a mixture thereof. The etching gas for the etch stopper layer is selected from a group consisting of carbon tetrafluoride/hydrogen (CF 4 /H 2 ), trifluoromethane (CHF 3 ), sulfur hexafluoride/hydrogen (SF 6 /H 2 ), and a mixture thereof. 
     In the step iv) of the above embodiment, the etching procedure can be performed by any suitable conventional technique which is not to be redundantly described here. 
     In the step v) of the above embodiment, the photo-masking and lithography procedure can be performed by any suitable conventional technique which is not to be redundantly described here. 
     In the step vi) of the above embodiment, the highly doped semiconductor layer  225  and the second conductive layer  226  can be applied by any suitable conventional techniques which are not to be redundantly described here. In this embodiment, the highly doped semiconductor layer  225  can also be formed of n +  micro-crystalline silicon or n +  polysilicon. The second conductive layer  226  can also be a Mo/Al/Mo layer. 
     In the step vii) of the above embodiment, the photo-masking and lithography procedure and the etching procedure can be performed by any suitable conventional techniques which are not to be redundantly described here. 
     In the step viii) of the above embodiment, the etching procedure can be performed by any suitable conventional technique which is not to be redundantly described here. 
     In the step ix) of the above embodiment, the passivation layer  227  can be applied by any suitable conventional technique which is not to be redundantly described here. The passivation layer  227  can also be formed of silicon oxynitride. On the other hand, the photo-masking and lithography procedure can be performed by any suitable conventional technique which is not to be redundantly described here. 
     In the step x) of the above embodiment, the transparent conductive layer  229  can be applied by any suitable conventional technique. The transparent conductive layer can also be formed of indium zinc oxide or indium lead oxide. 
     In the step xi) of the above embodiment, the photo-masking and lithography procedure can be performed by any suitable conventional technique which is not to be redundantly described here. 
     According to the process mentioned above, the formation of the etch stopper structure  23  is performed by a backside exposure technique as disclosed in the step iii), which uses the existent active region as a shield so that one masking step is omitted, and only five masking and patterning procedures are required. 
     A second preferred embodiment of a process for forming a TFT matrix of a TFTLCD according to the present invention directs to a four-mask process, and it is illustrated with reference to FIGS.  4 A˜ 4 K. It is to be noted that the division of steps and the provision of serial numbers as below are for corresponding to the drawings, and for easy illustration and understanding, instead of critically indicating the separation or the integration of steps. The preferred embodiment of the process includes steps of: 
     i) applying a first conductive layer  420  onto a front side  401  of a glass substrate  40 , as shown in FIG. 4A; 
     ii) using a first photo-masking and lithography procedure to pattern and etch the first conductive layer  420  to form an active region  41  consisting of a scan line  411  and a gate electrode  412  of a TFT unit, as shown in FIGS. 4B and 5A wherein FIG. 4B is a cross-sectional view taken along the B—B line of FIG. 5A; 
     iii) consecutively and sequentially forming an insulation layer  421 , a semiconductor layer  422 , an etch stopper layer  423 , and a photoresist  424  on the resulting structure of FIG. 4B, as shown in FIG. 4C, and exposing the resulting structure from the back side  402  of the substrate  40 , as indicated by arrows, wherein a portion of the photoresist  424  above the region  41  is shielded by the region  41  from exposure so as to exhibit a self-aligned effect; 
     iv) etching off the exposed photoresist  424 , a portion of the etch stopper layer  423  thereunder, and the remaining photoresist so that the remaining etch stopper structure  43  has a shape substantially identical to the region  41 , as shown in FIG.  4 D and with reference to FIG. 5A; 
     v) successively applying a highly doped semiconductor layer  425  and a second conductive layer  426  on the resulting structure of FIG. 4D, as shown in FIG. 4E; 
     vi) using a second photo-masking and lithography procedure to pattern and etch the second conductive layer  426  to define data and connection lines including a data line  46   a , a first connection line  46   b  and a second connection line  4   c , and also to define an isolation window area  48 , as shown in FIG. 4F; 
     vii) removing a portion of the highly doped semiconductor layer  425  and a portion of the semiconductor layer  422  with the data and connection lines  46   a ˜ 46   c  and the etch stopper structure  43  as a shield to define source/drain regions  45  and a channel structure  44 , respectively, as shown in FIG.  4 G and FIG. 5B, where the TFT unit  32  is formed and connected to the data line  46   a  via the connection line  46   b;    
     viii) applying a passivation layer  427  on the resulting structure of FIG. 4G, and using a third photo-masking and lithography procedure to pattern and etch the passivation layer  427  to create a contact window  47  to expose the connection line  46   c , as shown in FIG. 4H, to expose the isolation window area  48 , and also to define a tape automated bonding (TAB) openings (not shown); 
     ix) removing a portion of the etch stopper structure  43  and another portion of the semiconductor layer  422  in the isolation window area  48  with the remaining portion of the passivation layer  427  as a shield to form an isolation window  481  for cutting off the connection of the TFT unit  32  with the data line  46   a  through the semiconductor layer  422 , as shown in FIG.  41  and FIG. 5C; 
     x) applying a transparent conductive layer  429  on the resulting structure of FIG. 4I, as shown in FIG. 4J; and 
     xi) using a fourth photo-masking and lithography procedure to pattern and etch the transparent conductive layer  429  to form a pixel electrode  49 , which is connected to the TFT unit  32  through the connection line  46   c , as shown in FIG.  4 K. 
     The applying methods and etching methods of all the above layers used in this embodiment can be any suitable conventional techniques which are not to be redundantly described here. On the other hand, the materials of the substrate, the first conductive layer, the insulation layer, the semiconductor layer, the etch stopper layer, the highly doped semiconductor layer, the second conductive layer, the passivation layer, and the transparent conductive layer used in this embodiment can be those respectively exemplified in the first embodiment. By the way, if the substrate is made of quartz which is relatively resistant to heat, the semiconductor layer and the highly doped semiconductor layer can be made of intrinsic polysilicon and highly doped polysilicon, respectively, which are formed in higher temperatures but exhibit better electric properties. 
     Similar to the first embodiment, the formation of the etch stopper structure  43  is also performed by a backside exposure technique as disclosed in the step iii), which uses the existent active region as a shield so that one masking step is omitted. Furthermore, due to the rearrangement of steps, the semiconductor layer does not need to be patterned and etched in advance. Therefore, only four masking and patterning procedures are required. 
     In the second embodiment, the formation of the isolation window  481  and thus the definition of the isolation window area  48  are not essential to the TFT matrix. The high impedance of the channel  44  may exhibit an isolation effect to some extent. Another isolation window  482  (FIG. 5C) is also optionally existent. 
     While the invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.