Abstract:
A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a phase adjustment apparatus, a clock generator and a method for adjusting a phase of a clock. 
       BACKGROUND OF THE INVENTION 
       [0002]    Current televisions or communication products retrieve transmission signals from carriers. Therefore, a receiving end needs to generate an extremely precise local oscillation signal or a clock signal for demodulating the carriers. In addition, for the clock signal, precision is required not only in frequency, but also in phase. 
         [0003]    Conventionally, a phase-locked loop (PLL) is capable of generating an original clock signal having a same frequency as that of a reference signal. However, a phase of the original signal may differ from a desired phase. To obtain a clock signal with precision in both phase and frequency, an adjustment on the phase of the original clock signal may be required. 
       SUMMARY OF THE INVENTION 
       [0004]    A phase adjustment apparatus for providing a clock signal to a core circuit is disclosed according to an embodiment of the present invention. The core circuit is powered by a core voltage. The phase adjustment apparatus comprises two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess two different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit, powered by a first voltage lower than the core voltage, generates the clock signal according to the phase selection signals and the two original clock signals. 
         [0005]    A clock generator comprising a phase-locked loop and a phase adjustment apparatus is disclosed according to an embodiment of the present invention. The phase-locked loop comprises a voltage-controlled oscillator (VCO) and a loop filter. The VCO generates two original clock signals having a same frequency and different phases according to a control voltage. The loop filter generates the control voltage for controlling frequencies of the two original clock signals. The phase adjustment apparatus, powered by a first voltage, generates a clock signal according to a ratio and the two original clock signals. The clock signal is provided to a core circuit, which is powered by a core voltage. The first voltage is smaller than the core voltage. 
         [0006]    A phase adjustment method for providing a clock signal to a core circuit is further disclosed by the present invention. The core circuit is powered by a core voltage. The method comprises: generating a clock signal by synthesizing two original clock signals and according to a ratio. The two original clock signals have a same frequency while the two original clock signals possess different phases. An amplitude of the clock signal is smaller than that of the core voltage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which: 
           [0008]      FIG. 1  is an operating system; 
           [0009]      FIG. 2A  shows a phase adjustment apparatus in  FIG. 1 ; 
           [0010]      FIG. 2B  shows a driving circuit in  FIG. 2A ; 
           [0011]      FIGS. 3A and 3B  respectively show relationships between the clock signal Clk 0  and signals S m  and S m+1  under two different frequencies; 
           [0012]      FIG. 4  shows another operating system; 
           [0013]      FIG. 5  shows a phase adjustment apparatus in  FIG. 4 ; 
           [0014]      FIGS. 6A and 6B  respectively show relationships between the clock signal Clk 0  and signals T m  and T m+1  under two different frequencies; and 
           [0015]      FIGS. 7 and 8  show another two operating systems. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0016]    The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. 
         [0017]      FIG. 1  shows an operating system comprising a clock generator  10  and a core circuit  12 . The clock generator  10  comprises a phase adjustment apparatus  28  and a phase-locked loop  11 . The phase-locked loop  11  comprises a phase detector  14  for receiving a reference signal Clk REF , a charge pump  16 , a loop filter  18 , a voltage buffer  20 , a voltage-controlled oscillator (VCO)  22  and a frequency divider  24 . 
         [0018]    The phase detector  14  generates a phase difference between the reference signal Clk REF  and a frequency divided clock Clk DIV  to drive the charge pump  16 . A current sent or drawn by the charge pump  16  forms a control voltage V CTL  after passing through the loop filter  18 . 
         [0019]    As shown in  FIG. 1 , after passing through the voltage buffer  20 , the control voltage V CTL  becomes an adjusting control voltage V RNG . Alternatively, the control voltage V CTL  may directly serve as the adjustment control voltage V RNG  for controlling frequencies of a plurality of original clocks Cl 1  to Cl K  generated by the VCO  22 . The original clocks Cl 1  to Cl K  are common in frequency, but different in phase. One of the original clock signals Cl 1  to Cl K  is frequency divided by the frequency divider  24  to generate the frequency divided clock Clk DIV  fed back to the phase detector  14 . 
         [0020]    The phase adjustment apparatus  28  receives the original clock signals Clk 1  to Cl K , and further receives phase selection signals P 1  to P N . The digital signals P 1  to P N  are for controlling the phase adjustment apparatus  28  to generate a clock signal Clk 0  by synthesizing a part of the original clock signals Cl 1  to Cl K . The clock signal Clk 0  is transmitted to the core circuit  12  to control the timing of the core circuit  12 . A core voltage V CORE1  and a core voltage V CORE2  are respectively supplied to the core circuit  12  and the phase adjustment apparatus  28 . The core voltage V CORE1  may equal to the core voltage V CORE2 . 
         [0021]      FIG. 2A  shows another example of the phase adjustment apparatus  28 . The phase adjustment apparatus  28  further comprises two driving circuits  30  and  32 . Through interpolation, the phase adjustment apparatus  28  generates the clock signal Clk 0  by synthesizing two of the original clock signals Clk m  and Clk m+1 . The phase adjustment apparatus  28  comprises a synthesizing circuit for adjusting weightings of the original clock signals Clk m  and Clk m+1  to generate the Clk 0  according to the original clock signals Clk m  and Clk m+1 . 
         [0022]    More specifically, the phase selection signals P 1  to P N  are for determining driving capabilities of the two driving circuits  30  and  32 ; the phase adjustment apparatus  28  adjusts weightings of the original clock signals Clk m  and Clk m+1  according to a ratio of the driving capability of the driving circuit  30  and that of the driving circuit  32  to generates the clock signal Clk 0 . 
         [0023]    For example, supposing the ratio of the driving capability of the driving circuit  30  to that of the driving circuit  32  is determined as 5:5 by the current phase selection signals P 1  to P N , the respective weightings of the original clock signals Clk m  and Clk m+1  are then 5:5. Thus, a phase of the clock signal Clk 0  is approximately right in the middle between phases of the original clock signals Clk m  and Clk m+1 . 
         [0024]      FIG. 2B  shows the driving circuit  30  in  FIG. 2A . The driving circuit  30  comprises identical driving cells D 1  to D N , each of which has a unit of driving capability. Switches SW 1  to SW N  are respectively controlled by the phase selection signals P 1  to P N , with each switch determining whether a corresponding driving cell drives the clock signal Clk 0 . For example, when the switches SW 1  to SW 3  are shorted by the phase selection signals P 1  to P N  while other switches in  FIG. 2B  are open, the current driving capability of the driving circuit  30  is 3 units. The driving circuit  32  may have circuits similar to those in the driving circuit  30 , and shall not be further described. 
         [0025]      FIGS. 3A and 3B  respectively show relationships between the clock signal Clk 0  and signals S m  and S m+1  under two different frequencies. The signal S m  represents a waveform of the clock signal is Clk 0  when the ratio of the driving capability of the driving circuit  30  to that of the driving circuit  32  is 10:0, and it approximately corresponds to the original clock signal Clk m . The signal S m+1  represents a waveform of the clock signal is Clk 0  when the ratio of the driving capability of the driving circuit  30  to that of the driving circuit  32  is 0:10, and it approximately corresponds to the original clock signal Clk m+1 . The amplitudes of the signals S m  and S m+1  are determined by a power supply, which are approximately the core voltage V CORE2 . 
         [0026]    As observed from  FIG. 3A , the clock signal Clk 0  is roughly synthesized from 50% of S m  and 50% of S m+1 . Although the clock signal Clk 0  is not exactly rail-to-rail, the phase of the clock signal Clk 0  is almost right in the middle between the two phases of the signals S m  and S m+1 , which means it is almost right in the middle between the two original signals Clk m  and Clk m+1 . 
         [0027]    In  FIG. 3B , the clock signal Clk 0  is also approximately synthesized from 50% of S m  and 50% of S m+1 ; however, frequencies of the signals S m  and S m+1  are relatively lower. As observed from  FIG. 3B , due to flat peaks and flat valleys occurring in the signals S m  and S m+1 , a level of the clock signal Clk 0  maintains at a fixed value at a middle range for a period of time, such that the phase of the clock signal Clk 0  is likely unidentifiable or unlikely to be utilized. Therefore, the phase adjustment apparatus  28  needs to adjust for different clock frequencies in order to prevent the complications occurring in  FIG. 3B . 
         [0028]      FIG. 4  shows another operating system comprising a clock generator  10   a  and a core circuit  12  according to an embodiment of the present invention. A main difference between the clock generator  10   a  in  FIG. 4  and the clock generator  10  in  FIG. 1  is that, a phase adjustment apparatus  28   a  is powered by an adjusting control voltage V RNG . The adjusting control voltage V RNG  is lower than a core voltage V CORE  by a ratio, which is a value sufficient to allow a slope of signals T m  and a slope of T m+1  to render predetermined characteristics, which will be detailed later. The core circuit  12  comprises an amplifier  66  for amplifying a clock signal Clk 0  to generate a rail-to-rail clock signal Clk adj  having an amplitude of the core voltage V CORE . 
         [0029]      FIG. 5  shows the phase adjustment apparatus  28   a  according to an embodiment of the present invention. Operations of the phase adjustment apparatus  28   a  are quite similar to those of the phase adjustment apparatus  28 . That is, the two original clock signals Clk m  and Clk m+1  received at the two clock receiving ends are synthesized into the clock signal Clk 0  by interpolation, and a ratio of a driving capability of a driving circuit  30   a  to that of a driving circuit  32   a  is determined by using the phase selection signals P 1  to P N  received at the digital receiving ends. 
         [0030]    For example, supposing the ratio of the driving capability of the driving circuit  30   a  to that of the driving circuit  32   a  determined by the phase selections signals P 1  to P N  is 5:5, the phase of the clock signal Clk 0  is approximately right in the middle between the phases of the original clock signals Clk m  and Clk m+1 . In addition, supposing the ratio determined by the phase selections signals P 1  to P N  is 7:3, the phase of the clock signal Clk 0  is closer to the original clock signal Clk m . 
         [0031]      FIGS. 6A and 6B  respectively show relationships between the clock signal Clk 0  and signals T m  and T m+1  under two different clock frequencies. Similar to the signals S m  and S m+1  in  FIGS. 3A and 3B , the signal T m  represents a waveform of the clock signal is Clk 0  when the ratio of the driving capability of the driving circuit  30   a  to that of the driving circuit  32   a  is 10:0, and it approximately corresponds to the original clock signal Clk m . The signal T m+1  represents a waveform of the clock signal is Clk 0  when the ratio of the driving capability of the driving circuit  30   a  to that of the driving circuit  32   a  is 0:10, and it approximately corresponds to the original clock signal Clk m+1 . It should be noted that, since the phase adjustment apparatus  28   a  is powered by the adjusting control voltage V RNG , the amplitudes of the signals T m  and T m+1  approximately equal to the adjusting control voltage V RNG , and the amplitude of the clock signal Clk 0  is, as a result, no greater than the adjusting control voltage V RNG . 
         [0032]    As observed from  FIG. 6A , the clock signal Clk 0  is roughly synthesized from 50% of T m  and 50% of T m+1 . In other words, the phase of the clock signal Clk 0  is almost right in the middle between the two original signals Clk m  and Clk m+1 . Except for the sizes of the amplitudes, the clock signal Clk 0  in  FIG. 6A  and the clock signal Clk 0  in  FIG. 3A  are not much different as far as the waveform is concerned. On the other hand, the differences between waveforms of the signal Clk 0  in  FIG. 6B  and  FIG. 3B  are significant. 
         [0033]    In  FIG. 6B , the clock signal Clk 0  is also roughly synthesized from 50% of T m  and 50% of T m+1 ; however, in  FIG. 6B , the frequencies of the signals T m  and T m+1  are relatively lower. A main difference between  FIGS. 6B and 3B  is that, the clock signal Clk 0  in  FIG. 6B  does not hover at the middle range, and thus its phase is more identifiable or more likely to be utilized. One of the reasons shall be described below. 
         [0034]    As previously stated, the phase adjustment apparatus  28   a  is powered by the adjusting control voltage V RNG . Compared to the core voltage V CORE  independent form the original clock signals Clk m  and Clk m+1 , the adjusting control voltage V RNG  decreases along with decreases in the frequencies of the original clock signals Clk m  and Clk m+1 . Accordingly, the reduced adjusting control voltage V RNG  renders smaller driving capabilities of the driving circuits  30   a  and  32   a  to correspondingly decrease the slopes of the signals T m  and T m+1 , so that the flat peaks and flat valleys in the signals S m  and S m+1  are less likely to occur. Therefore, the clock signal Clk 0  synthesized from the signals T m  and T m+1  do not hover at the middle range. 
         [0035]    In  FIG. 4 , the phase adjustment apparatus  289   a  is directly powered by the adjusting control voltage V RNG , and with the adjusting control voltage V RNG  decreasing as the original clock signals Clk m  and Clk m+1  decrease, the situation that the level of the waveform of the clock signal Clk 0  hovering at fixed value at the middle range can be prevented. It is to be noted that directly powering by the adjusting control voltage V RNG  is merely an exemplary embodiment rather than an essential characteristic of the present invention. 
         [0036]    The details below are given with reference to  FIGS. 7 and 8 .  FIG. 7  shows another operating system. A voltage buffer  60  generates a supply voltage V SPLY  according to the adjusting control voltage V RNG  to power the phase adjustment apparatus  28   a .  FIG. 8  shows yet another operating system. A voltage buffer  62  generates a V SPLY  according to the control voltage V CTL  to power the phase adjustment apparatus  28   a . Preferably, the supply voltage V SPLY  is not greater than the core voltage V CORE  of the core circuit  12 . 
         [0037]    In conclusion, the control voltage V CTL , the adjusting control voltage V RNG  and the supply voltage V SPLY  are positively correlated. The adjusting control voltage and the supply voltage V SPLY  increase as the control voltage V CTL  gets greater. An essence of the present invention is that, through a voltage interlinked with the frequencies of the original clock signals Clk m  and Clk m+1  or through a voltage lower than the core voltage V CORE  that powers the phase adjustment apparatus  28   a , a situation that the level of the waveform of the clock signal Clk 0  hovering at a fixed value in the middle range is prevented. In an embodiment, the control voltage V CTL : the adjusting control voltage V RNG : the supply voltage V SPLY  equals 1:1:1. In another embodiment, values of the control voltage V CTL , the adjusting control voltage V RNG  and the supply voltage V SPLY  do not equal to one another. 
         [0038]    While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.