Abstract:
A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor&#39;s parasitics and reduces a transistor&#39;s thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, providing for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit and priority of U.S. Provisional Application No. 61/615,078, filed on Mar. 23, 2012. Thus, the entire disclosure of U.S. Provisional Application No. 61/615,078 is hereby incorporated by reference herein. 
    
    
     STATEMENT REGARDING GOVERNMENT RIGHTS 
     This invention was made with Government support under Contract Nos. N66001-06-C-2025 and W911NF-08-C-0050, both awarded by the Department of Defense. The Government has certain rights in this invention. 
    
    
     BACKGROUND 
     1. Field 
     The present invention relates generally to a transistor and more particularly to a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. 
     2. Description of Related Art 
     A transistor is a semiconductor device used to amplify or switch electronic signals and power. Thus, a function of a transistor is its ability to amplify a small signal to a larger signal. Alternatively, another function of a transistor is its ability to serve as a switch to turn current on or off. 
     Generally, there are two types of transistors. A bipolar junction transistor (BJT) has terminals labeled base, collector, and emitter. A current flowing from the base to the emitter controls (or switches) a larger current between the collector and the emitter. A heterojunction bipolar transistor is a form of a BJT that incorporates a hetero-junction that uses two different materials, with different band gaps, for one or both junctions. A field effect transistor (FET) has terminals labeled gate, drain, and source. A voltage at the gate controls a current between the drain and the source. A high electron mobility transistor (HEMT) is a form of FET that incorporates a hetero-junction that uses two different materials, with different band gaps, on either side of the channel. Typically, a HEMT provides low noise figure and high levels of performance at microwave, mm-wave and sun-mm-wave frequencies. Typically a HBT provides higher gain and a larger operating voltage for performance at microwave, mm-wave, and sub-mm-wave frequencies. Thus, HEMT and HBT technologies are widely used in RF designs where high performance is required at high RF frequencies. 
     Thus, it is advantageous for a transistor to generate higher transistor bandwidths and higher output power. However, increasing transistor bandwidths requires reductions to the device parasitics to reduce transit delays and increase gain. Device parasitics decrease the speed at which a transistor operates and how much power the transistor can dissipate. The configuration of a transistor strongly influences how much heat it generates for a given power dissipation. Significant challenges exist when scaling the gate resistance and inductance of a FET (or HEMT) or the base resistance and inductance of a BJT (or HBT) because the physical dimension associated with the gate feed resistance and inductance, or the base metal resistance and inductance, can change little. Moreover, physical scaling of the transistor increases the power handling demands it must support before thermal effects degrade its RF performance. The limited physical dimensions associated with the gate feed resistance and inductance, or the base metal resistance and inductance, effectively sets an upper limit to the higher device bandwidth and/or gain achievable for a given technology. 
     SUMMARY 
     The present invention is an improvement to existing designs by providing for a method and an apparatus that reduces a transistor&#39;s parasitics and reduces a transistor&#39;s thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, the present invention also provides for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance. 
     In one embodiment, the present invention is a dual-base, single-finger common-emitter HBT. This HBT comprises a thin-film microstrip wiring using low-loss benzocyclobutene (BCB) with a multi-metal layer interconnect, stacked-via technology for compact layout. This dual-base connection reduces the base-metal resistance by approximately 75 percent. Alternatively, this common-emitter HBT can also be a multi-finger common-emitter HBT, having improved thermal impedance. 
     In another embodiment, the present invention is a dual-base, single-finger common-base HBT. This HBT comprises a thin-film microstrip wiring using low-loss BCB with a multi-metal layer interconnect, stacked-via technology for compact layout. This dual-base connection reduces the base-metal resistance by approximately 75 percent. Alternatively, this common-base HBT can also be a multi-finger common-base HBT, having improved thermal impedance. 
     In yet another embodiment, the present invention is a dual-gate, double-finger common-source configuration HEMT. This HEMT comprises a thin-film microstrip wiring using low-loss BCB with a multi-metal layer interconnect, stacked via technology for compact layout. This dual-gate connection reduces the rate resistance by more than 50 percent. 
     By applying more than one connection to a FET (or HEMT) gate or a BJT (or HBT) base, the resistance and inductance of these features are reduced by at least 50 percent. Specifically, for a FET, the effective input gate feed resistance (R feed, 1 ) is reduced by approximately 50 percent or completely, and the effective gate-head resistance (R feed, 2 ) along the active FET region is reduced by approximately 75 percent. For a HEMT, the effective gate finger metal inductance is reduced by more than 50 percent. For a HBT, the effective base metal resistance along the emitter finger is reduced by approximately 75 percent, and the effective base metal inductance along the emitter is reduced by more than 50 percent. 
     This multiple input connections approach to a FET (or HEMT) gate or a BJT (or HBT) base surpasses the physical scaling limits of traditional transistors that typically have a single input connection to a HT (or HEMT) gate or a BJT (or Hal) base. Specifically, for a FET (or HEMT), this multiple input connections approach surpasses such physical scaling limits, resulting in greater device bandwidths (f max ) that would otherwise not be achievable with a traditional single input connection. For a BJT (or HBT), this multiple input connections approach reduces the undesired impact of increased BJT (or HBT) base resistance and inductance which results from a narrower base metal contact, required to make narrower the base-collector semiconductor mesa and increase the device bandwidths. 
     Moreover, the multi-finger device layout reduces the thermal impedance of the transistor. This lower thermal impedance is achieved by using a transistor with fewer fingers, but fingers greater in length. A lower thermal impedance results in higher operating power densities. More particularly, multi-finger transistors with lower thermal impedance can be used for amplifiers to generate a higher output power, which reduces the complexity of or need for, corporate power combining and the losses that come from such structures. This increases the power added efficiency (PAE) of the amplifier, which is a critical figure-of-merit for power amplifiers. 
     The present invention can be applied to solid-state power amplifiers (SSPA) in all semiconductor technologies (Si, SiGe, GaN, GaAs, InP, among others) at all frequencies, but is of significant value at the low-mm, mm-, and sub-mm wave regime. Similarly, the present invention can be applied to low-noise amplifiers (LNA), at all operating frequencies. Additionally, the present invention improves upon existing technologies by way of (a) reduced device noise for LNAs, (b) switches with shorter response time, and (c) greatly improved low DC power amplifier gain and bandwidth. 
    
    
     
       BRIEF DESCRIPTION OF TUE DRAWINGS 
       Other systems, methods, features and advantages of the present invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. Component parts shown in the drawings are not necessarily to scale, and may be exaggerated to better illustrate the important features of the present invention. In the drawings, like reference numerals designate like parts throughout the different views, wherein: 
         FIG. 1  is an angled-view of an exemplary embodiment of the present invention&#39;s dual-gate, two-gate finger, common-source configuration HEMT. 
         FIG. 2  is a top-view of an exemplary embodiment of the present invention&#39;s dual-gate, two-gate finger, common-source configuration HEMT. 
         FIG. 3  is a first angled-view of an exemplary embodiment of the present invention&#39;s dual-base, common-emitter configuration HBT. 
         FIG. 4  is a second angled-view of an exemplary embodiment of the present invention&#39;s dual-base, common-emitter configuration HBT. 
         FIG. 5  is a third angled-view of an exemplary embodiment of the present invention&#39;s dual-base, common-emitter configuration HBT. 
         FIG. 6  is an angled-view of an exemplary embodiment of the present invention&#39;s dual-emitter, common-base configuration HBT. 
         FIG. 7  is a top-view of an exemplary embodiment of the present invention&#39;s dual-emitter, common-base configuration HBT. 
         FIG. 8  is a first angled-view of an exemplary embodiment of the present invention&#39;s four-finger, common-emitter configuration HBT. 
         FIG. 9  is a second angled-view of an exemplary embodiment of the present invention&#39;s four-finger, common-emitter configuration HBT. 
         FIG. 10  is a third angled-view of an exemplary embodiment of the present invention&#39;s four-finger, common-emitter configuration HBT. 
         FIG. 11  is a top-view of an exemplary embodiment of the present invention&#39;s four-finger, common-emitter configuration HBT. 
         FIG. 12  is a first angled-view of an exemplary embodiment of the present invention&#39;s dual-emitter, two-finger, common-base configuration HBT. 
         FIG. 13  is a second angled-view of an exemplary embodiment of the present invention&#39;s dual-emitter, two-finger, common-base configuration HBT. 
         FIG. 14  is a top-view of an exemplary embodiment of the present invention&#39;s dual emitter, two-finger, common-base configuration HBT. 
         FIG. 15  is a top-view of an exemplary embodiment of a traditional layout for a four finger common-emitter HBT. 
         FIG. 16  is a top-view of an exemplary embodiment of a traditional layout for a dual-emitter, four-finger, common-base HBT. 
         FIG. 17  is a top-view of another exemplary embodiment of the present invention&#39;s dual-gate, two-gate finger, common-source configuration HEMT. 
         FIG. 18  is a first angled-view of another exemplary embodiment of the present invention&#39;s dual-gate, two-gate finger, common-source configuration HEMT. 
         FIG. 19  is a second angled-view of another exemplary embodiment of the present invention&#39;s dual-gate, two-gate finger, common-source configuration HEMT. 
     
    
    
     DETAILED DESCRIPTION 
     Methods and apparatus that implement the embodiments of the various features of the disclosure will now be described with reference to the figures below. The figures and the associated descriptions are provided to illustrate embodiments of the present invention and not to limit the scope of the present invention. Reference in the specification to “one embodiment” or “an embodiment” is intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an embodiment of the present invention. The appearances of the phrase “in one embodiment” or “an embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Throughout the figures, reference numbers are re-used to indicate correspondence between referenced elements. 
       FIGS. 1 and 2  depict an exemplary embodiment of the present invention&#39;s dual-gate, two-finger, common-source configuration HEMT.  FIG. 1  is an angled-view while  FIG. 2  is a top-view of this embodiment. The reference numbers in  FIG. 1  are re-used in  FIG. 2  to indicate correspondence between referenced elements. Typically, in a common-source HEMT configuration, an input is applied at a gate, an output is applied at a drain, and RF ground is applied to a source. In this embodiment, there are five metal layers and interconnect vias positioned between consecutive metal layers. As shown in  FIGS. 1-2 , from top to bottom, there is a first metal layer comprising  101   a  and  101   b , interconnect vias  102   a  and  102   b , a second metal layer comprising  103   a  and  103   b , interconnect vias  104   a  and  104   b , a third metal layer comprising  105   a  and  105   b , interconnect vias  106   a  and  106   b , a fourth metal layer comprising  107   a ,  107   b  and  107   c , interconnect vias  108   a ,  108   b , and  108   c , and a transistor metal layer comprising  109   a ,  109   b , and  109   c . Additionally, there are two gate fingers  110 . As shown in  FIGS. 1-2 , each of these metal layers and vias are configured differently. Each metal layer or via can be made of gold, copper, aluminum, or any metal exhibiting high conductivity and low loss for a DC and/or RE signal. 
     Each metal layer  101   a  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  101   b  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  103   a  is 13.5-μm in the x-axis, 14.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  103   b  is 11.5-μm in the x-axis, 7.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  105   a  is 3.0-μm in the x-axis, 8.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  105   b  is 11.5-μm in the x-axis, 3.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  107   a  is 4.0-μm in the x-axis, 6.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  107   b  is 17.5-μm in the x-axis, 7.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  107   c  is 1.0-μm in the z-axis. Each metal layer  109   a  is 5.0-μm in the x-axis, 5.0-μm in the y-axis, and 0.25-μm in the z-axis. Each metal layer  109   b  is 19.0-μm in the x-axis, 9.0-μm in the y-axis, and 0.25-μm in the z-axis. Each metal layer  109   c  is 19.0-μm in the x-axis, 4.0-μm in the y-axis, and 0.25-μm in the z-axis. 
     Collectively, as shown in  FIGS. 1-2 , this embodiment comprises (a) two interconnect vias  102   a  (each interconnect via  102   a  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  101   a  and second metal layer  103   a , and two interconnect vias  102   b  (each interconnect via  102   b  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  101   b  and second metal layer  103   b ; (b) four interconnect vias  104   a  (each interconnect via  104   a  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  103   a  and third metal layer  105   a , and two interconnect vias  104   b  (each interconnect via  104   b  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  103   b  and third metal layer  105   b ; (c) four interconnect vias  106   a  (each interconnect via  106   a  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  105   a  and fourth metal layer  107   a , and two interconnect vias  106   b  (each interconnect via  106   b  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-tun in the z-axis) between third metal layer  105   b  and fourth metal layer  107   b ; and (d) four interconnect vias  108   a  (each interconnect via  108   a  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 0.7-μm in the z-axis) between fourth metal layer  107   a  and transistor metal layer  109   a , eight interconnect vias  108   b  (each interconnect via  108   b  is 3.5-μm in the x-axis, 1.5-μm in the y-axis, and 0.7-μm in the z-axis) between fourth metal layer  107   b  and transistor metal layer  109   b , and eight interconnect vias  108   c  (each interconnect via  108   c  is 3.0-μm in the x-axis, 1.5-μm in the y-axis, and 0.7-μm in the z-axis) between fourth metal layer  107   c  and transistor metal layer  109   c . Additionally, as shown in  FIGS. 1-2 , there are two gate fingers  110  (each gate finger  110  is 25.0-μm in the x-axis, 0.4-μm in the y-axis, and 0.4-μm in the z-axis), whereby each gate finger connects one gate feed&#39;s transistor metal layer  109   a  to the other gate feed&#39;s transistor metal layer  109   a.    
     First metal layer  101   a  provides connections thr an input at the gate, while first metal layer  101   b  provides connections for an output at the drain. The input or output can be a DC or RF signal. Transistor metal layer  109   a ,  109   b , and  109   c  provides connections to the transistor semiconductor. As shown in  FIGS. 1-2 , the gate input at first metal layer  101   a  connects to the transistor semiconductor at transistor metal layer  109   a  by way of the following components: first metal layer  101   a , two interconnect vias  102   a , second metal layer  103   a , four interconnect vias  104   a , third metal layer  105   a , four interconnect vias  106   a , fourth metal layer  107   a , four interconnect vias  108   a , and transistor metal layer  109   a . More particularly, in this embodiment, the gate input at first metal layer  101   a  connects with the transistor semiconductor at transistor metal layer  109   a  via two gate feeds, as shown in  FIGS. 1-2 , hence the dual-gate configuration. Thus, each gate feed allows the input at first metal layer  101   a  to connect with the transistor semiconductor at transistor metal layer  109   a  by way of the following path: first metal layer  101   a , one interconnect via  102   a , second metal layer  103   a , two interconnect vias  104   a , third metal layer  105   a , two interconnect vias  106   a , fourth metal layer  107   a , two interconnect vias  108   a , and transistor metal layer  109   a.    
     As shown in  FIGS. 1-2 , the drain output at first metal layer  1011  connects to the transistor semiconductor at transistor metal layer  109   b  by way of the following components: first metal layer  101   b , two interconnect vias  102   b , second metal layer  103   b , two interconnect via  104   b , third metal layer  105   b , two interconnect vias  106   b , fourth metal layer  107   b , eight interconnect vias  108   b , and transistor metal layer  109   b . Finally, as shown in  FIGS. 1-2 , the connection at fourth metal layer  107   c  connects with the transistor semiconductor at transistor metal layer  109   c  by way of the following components: fourth metal layer  107   c , eight interconnect vias  108   c , and transistor metal layer  109   c . As shown in  FIGS. 1-2 , the eight interconnect vias  108   c  are divided into two sets of four interconnect vias  108   c.    
     As shown in  FIGS. 1-2 , the novel spatial arrangement of said HEMT&#39;s vertical interconnect, comprising (a) metal layers  101   a ,  101   b ,  103   a ,  103   b ,  105   a ,  105   b ,  107   a ,  107   b ,  107   c ,  109   a ,  109   b , and  109   c , and (b) vias  102   a ,  102   b ,  104   a ,  104   b ,  106   a ,  106   b ,  108   a ,  108   b ,  108   c , and  110 , reduces the gate finger metal inductance by more than 50 percent, reduces the effective input gate feed resistance (R feed, 1 ) by approximately 50 percent or completely, and reduces the effective gate-head resistance (R feed, 2 ) along the active FET region is by approximately 75 percent. 
       FIGS. 3-5  depict an exemplary embodiment of the present invention&#39;s dual-base, common-emitter configuration HBT.  FIGS. 3-5  are different angled views of this embodiment. The reference numbers in  FIG. 3  are re-used in  FIGS. 4 and 5  to indicate correspondence between referenced elements. Typically, in a common-emitter HBT configuration, an input is applied at a base, an output is applied at a collector, and RF ground is applied at an emitter, in this embodiment, there are five metal layers and interconnect vias positioned between consecutive metal layers. As shown in  FIGS. 3-5 , from top to bottom, there is a first metal layer comprising  201   a  and  201   b , interconnect vias  202   a  and  202   b , a second metal layer comprising  203   a  and  203   b , interconnect vias  204   a  and  204   b , a third metal layer comprising  205   a  and  205   b , interconnect vias  206   a  and  206   b , a fourth metal layer comprising  207   a ,  207   b  and  207   c , interconnect vias  208   a  and  208   b , and a transistor metal layer comprising  209   b . The transistor metal layer  209   b  serves as contacting metal to the transistor collector. Additionally, there is a transistor base-contact metal  210  and an emitter finger  212 . Transistor base-contact metal  210  provides connections to the transistor semiconductor, and the emitter finger  212  serves as the emitter. As shown in  FIGS. 3-5 , each of these metal layers and vias are configured differently. Each metal layer, via, or emitter finger can be made of gold, copper, aluminum, or any metal exhibiting high conductivity and low loss for a DC and/or RF signal. 
     Each metal layer  201   a  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 3.0-μm in the z-axis. Each metal layer  201   b  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 3.0-μm in the z-axis. Each metal layer  203   a  is 3.0-μm in the x-axis, 4.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  203   b  is 3.0-μm in the x-axis, 4.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  205   a  is 2.6-μm in the x-axis, 2.6-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  205   b  is 2.6-μm in the x-axis, 2.6-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  207   a  is 3.0-μm in the x-axis, 2.5-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  207   b  is 3.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  207   c  is 1.0-μm in the z-axis. Each metal layer  209   b  is 3.7-μm in the x-axis, 2.6-μm in the y-axis, and 0.3-μm in the z-axis. 
     Collectively, as shown in  FIGS. 3-5 , this embodiment comprises (a) two interconnect vias  202   a  (each interconnect via  202   a  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  201   a  and second metal layer  203   a , and one interconnect vias  202   b  (each interconnect via  202   b  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  201   b  and second metal layer  203   b ; (b) two interconnect vias  204   a  (each interconnect via  204   a  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  203   a  and third metal layer  205   a , and one interconnect via  204   b  (each interconnect via  204   b  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  203   b  and third metal layer  205   b ; (c) two interconnect vias  206   a  (each interconnect via  206   a  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  205   a  and fourth metal layer  207   a , and one interconnect via  206   b  (each interconnect via  206   b  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  205   b  and fourth metal layer  207   b ; and (d) two interconnect vias  208   a  (each interconnect via  208   a  is 0.8-μm in the x-axis, 008-μm in the y-axis, and 0.8-μm in the z-axis) between fourth metal layer  207   a  and a transistor base-contact metal  210 , and one interconnect via  208   b  (each interconnect via  208   a  is 2.2-μm in the x-axis, 1.0-μm in the y-axis, and 0.6-μm in the z-axis) between fourth metal layer  207   b  and transistor metal layer  209   b . As shown in  FIGS. 3-5 , transistor base-contact metal  210  (each transistor base-contact metal  210  is 8.0-μm in the x-axis, 1.6-μm in the y-axis, and 0.06-μm in the z-axis) connects to each base&#39;s interconnect via  208   a . Additionally, emitter finger  212  (each emitter finger  212  is 0.25-μm in the x-axis, 4.0-μm in the y-axis, and 0.8-μm in the z-axis) is positioned inside and surrounded by transistor base-contact metal  210 . 
     First metal layer  201   a  provides connections for an input at the base, while first metal layer  201   b  provides connections for an output at the collector. The input or output can be a DC and/or RE signal. Fourth metal layer  207   c  provides connections to emitter linger  212  of the transistor, which is exposed above the BCB and accessible. As shown in  FIGS. 3-5 , the base input at first metal layer  201   a  connects to the transistor semiconductor at transistor base-contact metal  210  via the components: first metal layer  201   a , two interconnect vias  202   a , second metal layer  203   a , two interconnect vias  204   a , third metal layer  205   a , two interconnect vias  206   a , fourth metal layer  207   a , two interconnect vias  208   a , and transistor base-contact metal  210 . 
     More particularly, in this embodiment, the base input at first metal layer  201   a  connects to the transistor semiconductor at transistor base-contact metal  210  via two base feeds, as shown in  FIGS. 3-5 , hence the dual-base configuration. Thus, each base feed allows the input at first metal layer  201   a  to connect to the transistor semiconductor at transistor base-contact metal  210  by way of the following path: first metal layer  201   a , one interconnect via  202   a , second metal layer  203   a , one interconnect via  204   a , third metal layer  205   a , one interconnect via  206   a , fourth metal layer  207   a , one interconnect via  208   a , and transistor base-contact metal  210 . 
     As shown in  FIGS. 3-5 , the transistor collector output at first metal layer  201   b  connects to the transistor semiconductor at transistor metal layer  209   b  by way of the following path: first metal layer  201   b , one interconnect via  202   b , second metal layer  203   b , one interconnect via  204   b , third metal layer  205   b , one interconnect vias  206   b , fourth metal layer  207   b , one interconnect via  208   b , and transistor metal layer  209   b.    
     As shown in  FIGS. 3-5 , this novel spatial arrangement of said HBT&#39;s vertical interconnect, comprising (a) metal layers  201   a ,  201   b ,  203   a ,  203   b ,  205   a ,  205   b ,  207   a ,  207   b ,  207   c , and  209   b , (b) vias  202   a ,  202   b ,  204   a ,  204   b ,  206   a ,  206   b ,  208   a ,  208   b , and  210 , (c) emitter finger  212 , reduces the effective base metal resistance along the emitter finger by approximately 75 percent, and reduces the effective base metal inductance along the emitter by more than 50 percent. 
       FIGS. 6-7  depict an exemplary embodiment of the present invention&#39;s dual-emitter, common-base configuration HBT.  FIG. 6  is an angled-view while  FIG. 7  is a top-view of this embodiment. The reference numbers in  FIG. 6  are re-used in  FIG. 7  to indicate correspondence between referenced elements. Typically, in a common-base HBT configuration, an input is applied at an emitter, an output is applied at a collector, and RF ground is applied at a base. In this embodiment, there are five metal layers and interconnect vias positioned between consecutive metal layers. As shown in  FIGS. 6-7 , from top to bottom, there is a first metal layer comprising  301   a  and  301   b , interconnect vias  302   a  and  302   b , a second metal layer comprising  303   a  and  303   b , interconnect vias  304   a  and  304   b , a third metal layer comprising  305   a  and  305   b , interconnect vias  306   a  and  306   b , a fourth metal layer comprising  307   a ,  307   b  and  307   c , interconnect vias  308   a  and  308   b , and a transistor metal layer comprising  309   a  and  309   b . Additionally, there are two transistor base-contact metals  310  and two emitter fingers. Emitter fingers  312  and  313  serve as the emitters. Each metal layer, via, or emitter finger can be made of gold, copper, aluminum, or any metal exhibiting high conductivity and low loss for a DC and/or RE signal. 
     Each metal layer  301   a  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  301   b  is 12.5-μm in the x-axis, more than 10.0-μm in the) y-axis, and 1.0-μm in the z-axis. Each metal layer  303   a  is 4.0-μm in the x-axis, 6.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  303   b  is 3.0-μm in the x-axis, 6.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  305   a  is 2.6-μm in the x-axis, 2.6-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  307   a  is 3.6-μm in the x-axis, 3.2-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  307   b  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  307   c  is 1.0-μm in the z-axis. Each metal layer  309   a  is 5.8-μm in the x-axis, 3.7-μm in the y-axis, and 0.3-μm in the z-axis. Each metal layer  309   b  is 5.8-μm in the x-axis, 3.7-μm in the y-axis, and 0.3-μm in the z-axis. 
     Collectively, as shown in  FIGS. 6-7 , this embodiment comprises (a) two interconnect vias  302   a  (each interconnect via  302   a  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  301   a  and second metal layer  303   a , and one interconnect via  302   b  (each interconnect via  302   b  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  301   b  and second metal layer  303   b ; (b) two interconnect vias  304   a  (each interconnect via  304   a  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  303   a  and third metal layer  305   a , and one interconnect via  304   b  (each interconnect via  304   b  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  303   b  and third metal layer  305   b ; (c) two interconnect vias  306   a  (each interconnect via  306   a  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  305   a  and fourth metal layer  307   a , and one interconnect via  306   b  (each interconnect via  306   b  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  305   b  and fourth metal layer  307   b , and one interconnect via  308   b  (each interconnect via  308   b  is 1.5-μm in the x-axis, 4.2-μm in the y-axis, and 0.6-μm in the z-axis) between fourth metal layer  307   b  and transistor metal layer  309   b , and four interconnect vias  308   c  (each interconnect via  308   c  is 0.8-μm in the x-axis, 0.8-μm in the y-axis, and 0.8-μm in the z-axis) between fourth metal layer  307   c  and transistor base-contact metals  310 . There are two transistor base-contact metals  310  (each transistor base-contact metal  310  is 8.0-μm in the x-axis, 1.6-μm in the y-axis, and 0.06-μm in the z-axis) and emitter fingers  312  and  313  (each emitter finger  312  and  313  is 0.25-μm in the x-axis, 4.0-μm in the y-axis, and 0.8-μm in the z-axis) with each emitter finger positioned inside and surrounded by transistor base-contact metal  310 . 
     First metal layer  301   a  provides connections for an input to the emitter, while first metal layer  301   b  provides connections for an output at the collector. The input or output can be a DC and/or RF signal. Transistor base-contact metals  310  provide connections to the transistor semiconductor. As shown in  FIGS. 6-7 , the input at first metal layer  301   a  connects with the emitter fingers  312  and  313  via following components: first metal layer  301   a , two interconnect vias  302   a , second metal layer  303   a , two interconnect vias  304   a , third metal layer  305   a , two interconnect vias  306   a , fourth metal layer  307   a , and emitter fingers  312  and  313  that are above the BCB and accessible. More particularly, in this embodiment, the input at first metal layer  301   a  connects to the emitter fingers  312  and  313 , as shown in  FIGS. 6-7 , hence the dual-emitter configuration. Thus, each feed allows the input at first metal layer  301   a  to connect with emitter fingers  312  and  313  by way of the following path: first metal layer  301   a , one interconnect via  302   a , second metal layer  303   a , one interconnect via  304   a , third metal layer  305   a , one interconnect via  306   a , fourth metal layer  307   a  and emitter fingers  312  and  313 . 
     As shown in  FIGS. 6-7 , the transistor collector output at first metal layer  301   b  connects to the transistor semiconductor at transistor metal layer  309   b  by way of the following components: first metal layer  301   b , one interconnect via  302   b , second metal layer  303   b , one interconnect via  304   b , third metal layer  305   b , one interconnect via  3061 , fourth metal layer  307   b , one interconnect via  308   b , and transistor metal layer  309   b . Finally, as shown in  FIGS. 6   7 , DC and/or RF ground potential at fourth metal layer  307   c  connects to the transistor semiconductor by way of the following components: fourth metal layer  307   c , interconnect vias  308   c , and transistor base-contact metals  310 . 
     As shown in  FIGS. 6-7 , this novel spatial arrangement of said HBT&#39;s vertical interconnect, comprising (a) metal layers  301   a ,  301   b ,  303   a ,  303   b ,  305   a ,  305   b ,  307   a ,  307   b ,  307   c ,  309   a , and  309   b , (b) vias  302   a ,  302   b ,  304   a ,  304   b ,  306   a ,  306   b ,  308   a ,  308   b , and  310 , (c) emitter fingers  312  and  313 , reduces the effective base metal resistance along the emitter finger by approximately 75 percent, and reduces the effective base metal inductance along the emitter by more than 50 percent. 
       FIGS. 8-11  depict an exemplary embodiment of the present invention&#39;s four-finger, common-emitter configuration HBT.  FIGS. 8-10  are different angled-views, while  FIG. 11  is a top-view of this embodiment. The reference numbers in  FIG. 8  are re-used in  FIGS. 9-11  to indicate correspondence between referenced elements. Typically, in a common-emitter HBT configuration, an input is applied at a base, an output is applied at a collector, and RF ground is applied at an emitter. In this embodiment, there are five metal layers and interconnect vias positioned between consecutive metal layers. As shown in  FIGS. 8-11 , from top to bottom, there is a first metal layer comprising  401   a  and  401   b , interconnect vias  402   a  and  402   b , a second metal layer comprising  403   a  and  403   b , interconnect vias  404   a  and  404   b , a third metal layer comprising  405   a  and  405   b , interconnect vias  406   a  and  406   b , a fourth metal layer comprising  407   a ,  407   b  and  407   c , interconnect vias  408   a ,  408   b , and  408   c , and a transistor metal layer comprising  409   a  and  409   b . Additionally, there are four transistor base-contact metals  410  and four emitter fingers. Transistor base-contact metals  410  provide connections to the transistor semiconductor, and the emitter fingers  412 ,  413 ,  414 , and  415  serve as the emitters. As shown in  FIGS. 8-11 , each of these metal layers and vias are configured differently. Each metal layer, via, or emitter finger can be made of gold, copper, aluminum, or any metal exhibiting high conductivity and low loss for a DC and/or RF signal. 
     Each metal layer  401   a  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 3.0-μm in the z-axis. Each metal layer  401   b  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 300-μm in the z-axis. Each metal layer  403   a  is 3.0-μm in the x-axis, 6.3-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  403   b  is 3.0-μm in the x-axis, 5.8-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  405   a  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  405   b  is 2.6-μm in the x-axis, 2.6-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  407   a  is 4.9-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  407   b  is 4.8-μm in the x-axis, 6.7-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  407   c  is 1.0-μm in the z-axis. Each metal layer  409   a  is 5.8-μm in the x-axis, 3.7-μm in the y-axis, and 0.3-μm in the z-axis. 
     Collectively, as shown in  FIGS. 8-11 , this embodiment comprises (a) two interconnect vias  402   a  (each interconnect via  402   a  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  401   a  and second metal layer  403   a , and one interconnect via  402   b  (each interconnect via  402   b  is 2.4-μm in the x-axis, 204-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  401   b  and second metal layer  403   b ; (b) two interconnect vias  404   a  (each interconnect via  404   a  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-m in the z-axis) between second metal layer  403   a  and third metal layer  405   a , and one interconnect via  404   b  (each interconnect via  404   b  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  403   b  and third metal layer  405   b ; (c) two interconnect vias  406   a  (each interconnect via  406   a  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  405   a  and fourth metal layer  407   a , and one interconnect via  406   b  (each interconnect via  406   b  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  405   b  and fourth metal layer  407   b ; and (d) two interconnect vias  408   a  (each interconnect via  408   a  is 4.0-μm in the x-axis, 1.5-μm in the y-axis, and 0.6-μm in the z-axis) between fourth metal layer  407   a  and transistor collector metal layer  409   a , and four interconnect vias  408   b  (each interconnect via  408   b  is 0.8-μm in the x-axis, 0.8-μm in the y-axis, and 0.8-μm in the z-axis) between fourth metal layer  407   b  and transistor metal layer  410 . Additionally, emitter fingers  412 ,  413 ,  414 , and  415  (each emitter finger  412 - 415  is 0.25-μm in the x-axis, 6.0-μm in the y-axis, and 0.8-μm in the z-axis) are each positioned inside and surrounded by each of the four transistor base-contact metals  410  (each transistor base-contact metal  410  is 8.5-μm in the x-axis, 1.6-μm in the y-axis, and 0.06-μm in the z-axis). 
     First metal layer  401   a  provides connections for an output at the collector, while first metal layer  401   b  provides connections for an input at the base. The input or output can be a DC and/or RF signal. As shown in  FIGS. 8-11 , the base input at first metal layer  401   b  connects to the transistor at transistor base-contact metals  410  by way of the following components: first metal layer  401   b , one interconnect via  402   b , second metal layer  403   b , one interconnect via  404   b , third metal layer  405   b , one interconnect via  406   b , fourth metal layer  407   b , one interconnect via  408   b , and transistor base-contact metals  410 . 
     As shown in  FIGS. 8-11 , the transistor collector output at first metal layer  401   a  connects to the transistor semiconductor at transistor metal layer  409   a  via the components: first metal layer  401   a , two interconnect via  402   a , second metal layer  403   a , two interconnect vias  404   a , third metal layer  405   a , two interconnect vias  406   a , fourth metal layer  407   a , four interconnect vias  408   a , and transistor metal layer  409   a . Fourth metal layer  407   c  provides connections to emitter fingers  412 ,  413 ,  414 , and  415  of the transistor, which are exposed above the BCB and accessible. Thus, as shown in  FIGS. 8-11 , fourth metal layer  407   c  connects to emitters by way of the following components: fourth metal layer  407   c  and emitter fingers  412 ,  413 ,  414 , and  415  of the transistor, which are exposed above the BCB and accessible. 
     As shown in  FIGS. 8-11 , this novel spatial arrangement of said HBT&#39;s vertical interconnect, comprising (a) metal layers  401   a ,  401   b ,  403   a ,  403   b ,  405   a ,  405   b ,  407   a ,  407   b ,  407   c , and  409   a , (b) vias  402   a ,  402   b ,  404   a ,  404   b ,  406   a ,  406   b ,  408   a ,  408   b , and  410 , (c) emitter fingers  412   413 ,  414 , and  415 , reduces the effective base metal resistance along the emitter finger by approximately 75 percent, and reduces the effective base metal inductance along the emitter by more than 50 percent. Additionally, emitter fingers  412 ,  413 ,  414 , and  415  are each approximately 6-μm in length. Based on both x-lines and y-lines of symmetry, emitter fingers  412  and  413  effectively constitute one long emitter finger, and emitter fingers  414  and  415  effectively constitute another long emitter finger. Hence, this embodiment effectively has two long emitter fingers. These two long emitter fingers result in a significant reduction in thermal impedance, as compared to a traditional layout of a four-finger, common-emitter HBT. In addition, the connection of emitters  412 ,  413 ,  414 , and  415  directly to the large forth metal layer  407   c  provides an effective secondary path for heat flow from the transistor, which decreases and improves the transistor thermal impedance by 20-25 percent.  FIG. 15  depicts a traditional layout for a four-finger, common-emitter HBT. 
       FIGS. 12-14  depict an exemplary embodiment of the present invention&#39;s dual-emitter, two-finger, common-base configuration HBT.  FIGS. 12-14  are different angled-views of this embodiment. The reference numbers in  FIG. 12  are re-used in  FIGS. 13-14  to indicate correspondence between referenced elements. Typically, in a common-base HBT configuration, an input is applied at an emitter, an output is applied at a collector, and RF ground is applied at a base. In this embodiment, there are five metal layers and interconnect vias positioned between consecutive metal layers. As shown in  FIGS. 12-14 , from top to bottom, there is a first metal layer comprising  501   a  and  501   b , interconnect vias  502   a  and  502   b , a second metal layer comprising  503   a  and  50 M, interconnect vias  504   a  and  504   b , a third metal layer comprising  505   a  and  505   b , interconnect vias  506   s  and  506   b , a fourth metal layer comprising  507   a ,  507   b  and  507   c , interconnect vias  508   a ,  508   b , and  508   c , and a transistor metal layer comprising  509   b . Additionally, there are two transistor base-contact metals  510  and two emitter fingers  512  and  513 . Emitter fingers  512  and  513  serve as the emitters. As shown in  FIGS. 12-14 , each of these metal layers and vias are configured differently. Each metal layer, via, or emitter finger can be made of gold, copper, aluminum, or any metal exhibiting high conductivity and low loss for a DC and/or RF signal. 
     Each metal layer  501   a  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 3.0-μm in the z-axis. Each metal layer  501   b  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 3.0-μm in the z-axis. Each metal layer  503   a  is 3.5-μm in the x-axis, 11.4-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  503   h  is 8.0-μm in the x-axis, 15.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  505   a  is 2.6-μm in the x-axis, 8.2-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  505   b  is 3.0-μm in the x-axis, 11.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  507   a  is 3.6-μm in the x-axis, 11.2-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  507   b  is 3.0-μm in the x-axis, 11.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  507   c  is 1.0-μm in the z-axis. Each metal layer  509   h  is 5.8-μm in the x-axis, 11.7-μm in the y-axis, and 0.3-μm in the z-axis. 
     Collectively, as shown in  FIGS. 12-14 , this embodiment comprises (a) two interconnect vias  502   a  (each interconnect via  502   a  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  501   a  and second metal layer  503   a , and two interconnect vias  502   b  (each interconnect via  502   b  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  501   b  and second metal layer  503   b ; (b) four interconnect vias  504   a  (each interconnect via  504   a  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  503   a  and third metal layer  505   a , and three interconnect vias  504   b  (each interconnect via  504   b  is 2.0-μm in the x-axis, 2.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  503   b  and third metal layer  505   b ; (c) four interconnect vias  506   a  (each interconnect via  506   a  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  505   a  and fourth metal layer  507   a , and three interconnect vias  506   b  (each interconnect via  506   b  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  505   b  and fourth metal layer  507   b ; and (d) one interconnect via  508   b  (each interconnect via  508   b  is 1.5-μm in the x-axis, 10.2-μm in the y-axis, and 0.6-μm in the z-axis) between fourth metal layer  507   b  and transistor metal layer  509   b , and four interconnect vias  508   c  (each interconnect via  508   c  is 0.8-μm in the x-axis, 0.8-μm in the y-axis, and 0.8-μm in the z-axis) between fourth metal layer  507   c  and transistor base-contact metals  510  (each transistor base-contact metal  510  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 0.06-μm in the z-axis). Additionally, each emitter finger  512  and  513  (each emitter finger  512 - 513  is 0.25-μm in the x-axis, 12.0-μm in the y-axis, and 0.8-μm in the z-axis) is positioned inside and surrounded by transistor base-contact metal  510 . 
     First metal layer  501   a  provides connections for an input to the emitter, while first metal layer  501   b  provides connections for an output at the collector. The input or output can be a DC and/or RF signal, Fourth metal layer  507   a  provides connections to emitter fingers  512  and  513 , which are exposed above the BCB and accessible. As shown in  FIGS. 12-14 , the input at first metal layer  501   a  connects with the emitter fingers  512  and  513  via the following components: first metal layer  501   a , two interconnect vias  502   a , second metal layer  503   a , four interconnect vias  504   a , third metal layer  505   a , four interconnect vias  506   a , fourth metal layer  507   a , and emitter fingers  512  and  513 , which are exposed above the BCB and accessible. More particularly, in this embodiment, the emitter input at first metal layer  501   a  connects to the transistor emitters  512  and  513  symmetrically along the y-axis of the transistor, as shown in  FIGS. 12-14 , hence the dual-emitter configuration. Thus, each emitter feed allows the input at first metal layer  501   a  to connect with the transistor emitters  512  and  513  by way of the following path: first metal layer  501   a , two interconnect vias  502   a , second metal layer  503   a , four interconnect vias  504   a , third metal layer  505   a , four interconnect vias  506   a , fourth metal layer  507   a , and emitter fingers  512  or  513 . 
     As shown in  FIGS. 12-14 , the transistor collector output at first metal layer  501   b  connects to the transistor semiconductor at transistor metal layer  509   b  by way of the following components: first metal layer  501   b , two interconnect vias  502   b , second metal layer  503   b , three interconnect vias  504   b , third metal layer  505   b , three interconnect vias  506   b , fourth metal layer  507   b , one interconnect via  508   b , and transistor metal layer  509   b . Transistor base-contact metals  510  provide connections to the transistor semiconductor. Thus, as shown in  FIGS. 12-14 , fourth metal layer  507   c  connects to the transistor semiconductor via the following path: transistor metal layer  507   c , interconnect vias  508   c , and transistor base-contact metals  510 . As shown in  FIGS. 12-14 , this novel spatial arrangement of said HBT&#39;s vertical interconnect, comprising (a) metal layers  501   a ,  501   b ,  503   a ,  503   b ,  505   a ,  505   b ,  507   a ,  507   b ,  507   c , and  509   b , (b) vias  502   a ,  502   b ,  504   a ,  504   b ,  506   a ,  506   b ,  508   a ,  508   b , and  510 , (c) emitter fingers  512  and  513 , reduces the effective base metal resistance along the emitter finger by approximately 75 percent, and reduces the effective base metal inductance along the emitter by more than 50 percent. Additionally, emitter fingers  512  and  513  are each approximately 12-μm in length. Emitter fingers  512  and  513  are arranged along both x-lines and y-lines of symmetry, resulting in a significant reduction in thermal impedance, as compared to a traditional layout which would be a dual-emitter, four finger, common-base HBT.  FIG. 16  depicts a traditional layout for a dual-emitter, four-finger, common-base HBT. 
       FIG. 15  is a top-view of an exemplary embodiment of a traditional layout for a four finger common-emitter HBT.  FIG. 15  is provided to show the advantages and novelties of the present invention&#39;s four-finger, common-emitter configuration HBT, as shown in  FIGS. 8-11 . Thus, of interest in  FIG. 15  are the four emitter fingers referenced as emitter fingers  612 . As shown in  FIG. 15 , each emitter finger  612  is approximately 6-μm in length and arranged parallel to each other. More particularly, each emitter finger  612  is 0.5-μm in the x-axis, 6.0-μm in the y-axis, and 0.8-μm in the z-axis. By contrast, as discussed and shown in  FIGS. 8-11 , the four emitter fingers, referenced as emitter fingers  412 ,  413 ,  414 , and  415 , in the present invention&#39;s four-finger, common-emitter configuration HBT are arranged in a manner that results effectively in two long emitter fingers. More particularly, each emitter finger  412 - 415  is 0.25-μm in the x-axis, 6.0-μm in the y-axis, and 0.8-μm in the z-axis. Thus, when emitter finger  412 - 415  are arranged in the manner shown in  FIGS. 12-14  (i.e. the pair of (a) emitter fingers  412  and  413 , and (b) emitter fingers  414  and  415 ), there are effectively two long emitter fingers having 12.0-μm in the y-axis. These two long emitter fingers result in a significant reduction in thermal impedance, as compared to a traditional layout of a four-finger, common-emitter HBT, as shown in  FIG. 15 . 
       FIG. 16  is a top-view of an exemplary embodiment of a traditional layout for a dual emitter, four-finger, common-base HBT.  FIG. 16  is provided to show the advantages and novelties of the present invention&#39;s two-finger, common-base configuration HBT, as shown in  FIGS. 12-14 . Thus, of interest in  FIG. 16  are the emitter fingers referenced as emitter fingers  712 . As shown in  FIG. 16 , each emitter finger  712  is approximately 6-μm in length and arranged parallel to each other. More particularly, each emitter finger  712  is 0.5-μm in the x-axis, 6.0-μm in the y-axis, and 0.8-μm in the z-axis. By contrast, as discussed and shown in  FIGS. 12-14 , the two emitter fingers, referenced as emitter fingers  512  and  513 , in the present invention&#39;s two-finger, common-base configuration HBT are each approximately 12-μm in length and arranged in a manner that results in a significant reduction in thermal impedance, as compared to a traditional layout of a four-finger, common-base HBT, as shown in  FIG. 16 . More particularly, each emitter finger  512 - 513  is 0.25-μm in the x-axis, 12.0-μm in the y-axis, and 0.8-μm in the z-axis. 
       FIG. 17  depict another exemplary embodiment of the present invention&#39;s dual-gate, two-finger, common-source configuration HEMT.  FIG. 17  is a top-view while  FIGS. 18-19  are angled-views of this embodiment. The reference numbers in  FIG. 17  are re-used in  FIGS. 18-19  to indicate correspondence between referenced elements. Typically, in a common-source HEMT configuration, an input is applied at a gate, an output is applied at a drain, and RF ground is applied at the source. In this embodiment, there are five metal layers and interconnect vias positioned between consecutive metal layers. As shown in  FIGS. 17-19 , from top to bottom, there is a first metal layer comprising  801   a  and  801   b , interconnect vias  802   a  and  802   b , a second metal layer comprising  803   a  and  803   b , interconnect vias  804   a  and  804   b , a third metal layer comprising  805   a  and  805   b , interconnect vias  806   a  and  806   b , a fourth metal layer comprising  807   a ,  807   b  and  807   c , interconnect vias  808   b  and  808   c , and a transistor metal layer comprising  809   a ,  809   b , and  809   c . Additionally, there are two gate fingers  810 . As shown in  FIGS. 17-19 , each of these metal layers and vias are configured differently. Each metal layer or via can be made of gold, copper, aluminum, or any metal exhibiting high conductivity and low loss for a DC and/or RF signal. 
     Each metal layer  801   a  is 12.5-μm to 21.0-μm in the x-axis, more than 10.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  801   b  is 12.5-μm in the x-axis, more than 10.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  803   a  is 3.7-μm in the x-axis, 13.8-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  803   b  is 8.8-μm in the x-axis, 10.4-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  805   a  is 2.8-μm in the x-axis, 2.8-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  805   b  is 8.6-μm in the x-axis, 3.6-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  807   a  is 19.1-μm in the x-axis, 2.6-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  807   b  is 9.4-μm in the x-axis, 5.0-μm in the y-axis, and 1.0-μm in the z-axis. Each metal layer  807   c  is 1.0-μm in the z-axis. Each metal layer  809   a  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 0.25-μm in the z-axis. Each metal layer  809   b  is 19.0-μm in the x-axis, 9.0-μm in the y-axis, and 0.25-μm in the z-axis. Each metal layer  809   c  is 19.0-μm in the x-axis, 4.0-μm in the y-axis, and 0.25-μm in the z-axis. 
     Collectively, as shown in  FIGS. 17-19 , this embodiment comprises (a) two interconnect vias  802   a  (each interconnect via  802   a  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  801   a  and second metal layer  803   a , and two interconnect vias  802   b  (each interconnect via  802   b  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between first metal layer  801   b  and second metal layer  803   b ; (b) four interconnect vias  804   a  (each interconnect via  804   a  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  803   a  and third metal layer  805   a , and two interconnect vias  804   b  (each interconnect via  804   b  is 3.0-μm in the x-axis, 3.0-μm in the y-axis, and 1.0-μm in the z-axis) between second metal layer  803   b  and third metal layer  805   b ; (c) four interconnect vias  806   a  (each interconnect via  806   a  is 1.6-μm in the x-axis, 1.6-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  805   a  and fourth metal layer  807   a , and two interconnect vias  806   b  (each interconnect via  806   b  is 2.4-μm in the x-axis, 2.4-μm in the y-axis, and 1.0-μm in the z-axis) between third metal layer  805   b  and fourth metal layer  807   b ; and (d) four interconnect vias  808   b  (each interconnect via  808   b  is 3.0-μm in the x-axis, 1.5-μm in the y-axis, and 0.7-μm in the z-axis) between fourth metal layer  807   b  and transistor metal layer  809   b , and eight interconnect vias  808   e  (each interconnect via  808   b  is 3.0-μm in the x-axis, 1.5-μm in the y-axis, and 0.7-μm in the z-axis) between fourth metal layer  807   c  and transistor metal layer  809   c . Additionally, as shown in  FIGS. 17-19 , there are two gate fingers  810  (each gate finger  810  is 25.0-μm in the x-axis, 0.4-μm in the y-axis, and 0.8-μm in the z-axis), whose top is exposed above the BCB dielectric and is directly accessible, whereby each gate finger is directly connected to fourth metal layer  807   a  Whereby each gate finger connects one gate feed&#39;s transistor layer  809   a  to the other gate feed&#39;s transistor metal layer  809   a.    
     First metal layer  801   a  provides connections for an input at the gate, while first metal layer  801   b  provides connections for an output at the drain. The input or output can be a DC or RF signal. Transistor metal layer  810 ,  809   b , and  809   c  provide connections to the transistor semiconductor. As shown in  FIGS. 17-19 , the gate input at first metal layer  801   a  connects to the transistor semiconductor at transistor metal layer  810  by way of the following components: first metal layer  801   a , two interconnect vias  802   a , second metal layer  803   a , four interconnect vias  804   a , third metal layer  805   a , four interconnect vias  806   a , fourth metal layer  807   a , and two gate fingers  810 . More particularly, in this embodiment, the gate input at first metal layer  801   a  connects with the transistor semiconductor at transistor metal layer  810  via two gate feeds, as shown in  FIGS. 17-19 , hence the dual-gate configuration. Thus, each gate feed allows the input at first metal layer  801   a  to connect with the transistor semiconductor at transistor metal layer  810  by way of the following path: first metal layer  801   a , one interconnect via  802   a , second metal layer  803   a , two interconnect visa  804   a , third metal layer  805   a , two interconnect vias  806   a , fourth metal layer  807   a , and one gate finger  810 . 
     As shown in  FIGS. 17-19 , the drain output at first metal layer  801   b  connects to the transistor semiconductor at transistor metal layer  809   b  by way of the following components: first metal layer  101   b , two interconnect vias  802   b , second metal layer  803   b , two interconnect via  804   b , third metal layer  805   h , two interconnect vias  806   b , fourth metal layer  807   b , four interconnect vias  808   b , and transistor metal layer  809   b . Finally, as shown in  FIGS. 17-19 , the connection at fourth metal layer  807   c  connects with the transistor semiconductor at transistor metal layer  809   c  by way of the following components: fourth metal layer  807   e , eight interconnect vias  808   c , and transistor metal layer  809   c . As shown in  FIGS. 17-19 , the eight interconnect vias  808   c  are divided into two sets of four interconnect vias  808   c.    
     As shown in  FIGS. 17-19 , the novel spatial arrangement of said HEMT&#39;s vertical interconnect, comprising (a) metal layers  801   a ,  801   b ,  803   a ,  803   b ,  805   a ,  805   b ,  807   a ,  807   b ,  807   c ,  809   a ,  809   b , and  809   c , and (b) vias  802   a ,  802   b ,  804   a ,  804   b ,  806   a ,  806   b ,  808   b ,  808   c , and  810 , reduces the gate finger metal inductance by more than 75 percent, completely removes the effective input gate feed resistance (R feed, 1 ), and the effective gate-head resistance (R feed, 2 ) along the active FET region is reduced by approximately 90 percent. 
     Exemplary embodiments of the invention have been disclosed in an illustrative style. Accordingly, the terminology employed throughout should be read in a non-limiting manner. Although minor modifications to the teachings herein will occur to those well versed in the art, it shall be understood that what is intended to be circumscribed within the scope of the patent warranted hereon are all such embodiments that reasonably fall within the scope of the advancement to the art hereby contributed, and that that scope shall not be restricted, except in light of the appended claims and their equivalents.