Abstract:
A parallel test device for testing a DUT includes a controller that has a test procedure useful for both sequential and parallel testing, a test regimen that includes a parallel procedure, and a parallel wrapper applied to the test procedure to provide the parallel procedure; and a plurality of test instruments that test the DUT in response to the controller.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to the parametric testing of semiconductor wafers and, in particular, to the contemporaneous performance of such tests. 
   As semiconductor wafer size has increased (e.g., 200 mm to 300 mm), the number of test measurements has also increased (e.g., doubled). It has become very desirable to perform more tests in less time as testing time corresponds closely to testing costs. Unfortunately, the time for individual tests has already been reduced to minimums constrained by such factors as settling time. 
   Performing multiple tests contemporaneously, or in parallel, allows more tests to be performed in the same time. However, including parallel test procedures in a testing regimen greatly increases the overall complexity of the regimen. This has heretofore greatly limited the use of parallel testing, because the test writer had to not only decide what tests to perform, but also, deal with the complex issues of multithreaded programming. 
   SUMMARY OF THE INVENTION 
   A parallel test device for testing a DUT includes a controller that has a test procedure useful for both sequential and parallel testing, a test regimen that includes a parallel procedure, and a parallel wrapper applied to the test procedure to provide the parallel procedure; and a plurality of test instruments that test the DUT in response to the controller. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram of a device according to the invention. 
       FIG. 2  is a flow chart of a method according to the invention. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Referring to  FIG. 1 , a parallel test device  10 , includes a controller  12 , test instruments  14 ,  16 ,  18 ,  20  and a device under test (DUT)  22 . The controller  12  may be, for example, a computer workstation. The instruments  14 ,  16 ,  18 ,  20  may be, for example, source measure units, capacitance meters, or other measurement devices. The instruments  14 ,  16 ,  18 ,  20  may also include, for example, individual or common controllers of their own (e.g., microprocessors, programmable controllers, personal computers and ancillary circuitry/mechanisms) for such functions as measurement control, timers, positioning, selection, switching and data communications. The DUT  22  may be, for example, a semiconductor wafer, or other specimen(s) or device(s) to be tested. 
   A master thread  24  of a control program in the controller  12  controls the testing of the DUT  22 . The tests may include conventional sequential tests directly controlled by the master thread  24 . In the illustrated embodiment, the instrument  14  is being used in a sequential test. In addition, the master thread  24  controls parallel threads  26 ,  28 ,  30  that can be performed contemporaneously with each other. In the illustrated embodiment, the instruments  16 ,  18 ,  20  are being controlled by the parallel threads  26 ,  28 ,  30 , respectively. It is of course to be understood that the correspondence between threads and instruments may change as a test regimen proceeds. Sequential tests should wait until any currently executing group of parallel tests complete before continuing in sequence. 
   Various issues arise in a parallel test. For example, it may not be possible to share the same instrument contemporaneously, routing/connection states as provided by switching matrix cannot be changed by one parallel test if it will interfere with another parallel test, performing certain tests will effect the results of other tests. In addition, there are various issues related to the use of parallel software threads themselves, such as allocating the threads themselves, monitoring and synchronizing the threads, and scheduling resources for each thread. 
   Referring to  FIG. 2 , the present invention separates the details of parallel programming from the test designer/user. The designer creates the desired tests (e.g., use instrument nn to measure the voltage between two defined points A, B on the DUT  24 ), including tests that may be performed either sequentially or in parallel. The controller  12  then creates the necessary instructions to perform this test in a sequential manner and also creates additional instructions or code to allow the test to be performed in a parallel manner. This additional code or parallel wrapper includes the additional parameters that must be passed to a parallel process so that a master thread can control it and, also, may include the additional constraints that may exist on performing a test in parallel. 
   To design a test regimen, the designer chooses from the test procedures that have been designed. If the designer does not desire a parallel test, the procedure is just added to the test regimen. If one or more procedures are to be performed in parallel, a parallel wrapper is added to the test by the controller  12  for use in the test regimen. The process continues until the test regimen is finished. 
   Real time, multithreaded programming is well-known, but it is not something a test designer should be required to deal with. The present invention, allows the test designer to concentrate on designing test regimens, while details of performing parallel tests are taken care of by the controller. 
   When the controller generates the wrapper code for a test procedure it essentially hides the details and complexities from the test designer so it is not necessary to understand anything more about multithreaded programming. 
   At run time, access to the instruments  14 ,  16 ,  18 ,  20  is controlled by the threading context of the calling routine. The controller  12  maintains a separate control context for each parallel thread. When a group of parallel threads are completed the master thread continues sequentially until another parallel group is encountered. 
   It should be evident that this disclosure is by way of example and that various changes may be made by adding, modifying or eliminating details without departing from the fair scope of the teaching contained in this disclosure. The invention is therefore not limited to particular details of this disclosure except to the extent that the following claims are necessarily so limited.