Abstract:
A computer processor includes a plurality of storage elements, such as logic gates and flip-flops, that are interconnected in a first configuration during normal operation of the processor. A plurality of selector elements connected to the storage elements are used to rearrange the storage elements into a second configuration upon entry into a low-power mode of operation. In general, the storage elements, when rearranged into the second configuration, form a chain through which data passes serially for storage in a storage device, such as a memory device or a hard drive.

Description:
TECHNICAL FIELD 
     The invention relates to power management in a computer system. 
     BACKGROUND 
     The manufacturers of personal computers, particularly portable computers, strive to reduce both component size and power consumption in these computers. The sizes of the transistors used to form computer components tend to decrease by approximately 70% every 18 months. However, as component sizes decrease, the leakage current increases. This can increase total power consumption associated with these components increases. In general, the power consumption caused by leakage current increases by a factor of approximately ten with each 70% decrease in component size. 
     One technique for reducing power consumption in a computer involves reducing the frequency at which the computer&#39;s processor is clocked when the processor is idle. Using current manufacturing techniques, the amount of leakage current in a processor is very small in comparison to the amount of power consumed in clocking the processor&#39;s storage elements. Therefore, reducing the processor&#39;s clocking frequency leads to a comparable reduction in power consumption. However, as the components in the processor become even smaller, leakage current will account for a much greater portion of power consumption. As a result, reducing the processor&#39;s clocking frequency will produce smaller gains in power consumption than are possible today. 
     SUMMARY 
     A computer processor includes a plurality of storage elements, such as logic gates and flip-flops, that are interconnected in a first configuration during normal operation of the processor. A plurality of selector elements connected to the storage elements are used to rearrange the storage elements into a second configuration upon entry into a low-power mode of operation. 
     In general, the storage elements, when rearranged into the second configuration, form a chain through which data passes serially for storage in a storage device, such as a memory device or a hard drive. 
     Other embodiments and advantages will become apparent from the description and claims that follow. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a computer system in which the processor loses power when idle. 
     FIGS. 2 and 3 are schematic diagrams illustrating techniques for quickly storing and restoring a processor&#39;s operating state upon removing power from and restoring power to the processor. 
     FIGS. 4 and 5 are flow charts illustrating techniques for quickly storing and restoring a processor&#39;s operating state upon removing power from and restoring power to the processor. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1 shows a computer system  100  that reduces power consumption by removing power from its processor  105  at times when the processor  105  is idle. In addition to the processor  105 , the computer  100  includes a volatile storage device, such as random access memory (RAM) device  110 , and a non-volatile storage device, such as a hard disk  115 , both coupled to the processor  105  through one or more data buses  120 . A memory controller  125  and a hard drive controller  130  control the flow of data into and out of the memory device  110  and the disk drive  115 , respectively. 
     A power supply  135  connects to the processor  105  through a switching element  140 . Control circuitry  145  in the computer  100  controls the state of the switch  140 . In many embodiments, at least some portion of the control circuitry resides in the processor  105  itself. 
     In general, the computer  100  removes power from the processor  105  any time that the processor  105  has remained idle for some minimum time interval. Reducing the duration of this interval increases the computer&#39;s overall power savings. The computer  100  stores the processor&#39;s operating state before removing power from the processor  105 . This ensures that processing resumes where halted when power is restored. To minimize the impact of this power-saving technique on the computer user, the computer must store and restore the processor state as quickly as possible upon removing and restoring power to the processor  105 . 
     FIG. 2 shows a block diagram of a structure that allows for quickly storing the processor state when entering a reduced-power mode. The processor  105  includes a plurality of storage elements  150 - 1 ,  150 - 2 , . . . ,  150 -N, such as logic gates and flip-flops, that process incoming data and generate corresponding output. These storage elements are interconnected in a manner that allows the processor  105  to carry out its normal functions. Each storage element normally receives input from at least one of the other storage elements over a corresponding primary input line  155 - 1 ,  155 - 2 , . . . ,  155 -N. 
     Each storage element  150 - 1 ,  150 - 2 , . . . ,  150 -N also includes a switching element  160 - 1 ,  160 - 2 , . . . ,  160 -N that is connected to an input source of a corresponding storage element. The connection to the storage element is changed just before power is removed from the processor  105 . In particular, the computer connects the storage elements in a chain by connecting the input of each storage element to the output of an adjacent storage element. Another switching element  170  connects the last storage element in the chain,  150 -N to a storage device  165 , such as RAM or a hard disk. This allows the storage elements in the processor to function like a shift register, passing their contents serially through the chain and into the storage device  170 . 
     The state of each of the storage elements is stored just before power is removed from the processor  105 . The control circuitry  145  (FIG. 1) asserts a signal on a control line  175  to force the switching elements to change states. A clock line  180  provides a clocking signal that causes each storage element to pass its contents to the next element in the chain. 
     When power is restored to the processor  105 , the switching elements again connect the storage elements to form a chain. The first storage element  150 - 1  in the chain is connected to receive the stored data from the storage device  165  and to pass it serially through the chain, as described below. 
     FIG. 3 shows another configuration, in which the storage elements are arranged into parallel chains. The last storage element  150 -X,  150 -N in each chain connects to the storage device  165 . This configuration increases the speed of storing and retrieving the state, by separating the contents of the storage elements into smaller streams and storing these streams in parallel. 
     FIG. 4 illustrates a sequence for use in removing power from the processor. Upon receiving a power-down event, such as a signal indicating that the processor has been idle for a particular amount of time or a general instruction to enter a reduced-power mode (step  200 ), the control circuitry checks the state of a flag that indicates whether the processor state has changed since the last restore operation (step  205 ). In general, the flag is cleared at the end of each store operation and is set when the processor next changes states. If the processor has remained idle since the last restore, the control circuitry asserts a control signal that causes the removal of power from the processor (step  210 ). 
     If the processor state has changed since the last restore operation, the control circuitry arranges the storage elements into a serial chain (step  215 ). The data contained in each storage element then propagates through the chain and into a storage device (step  220 ). In general, the data is stored at a prescribed memory location so that the processor can retrieve the data quickly and easily when power is restored. The control circuitry then clears the flag that indicates whether the processor has changed states since the last restore operation (step  225 ). 
     FIG.  5 . illustrates a sequence for use in restoring power to the processor. Upon detecting the restoration of power to the processor (step  230 ), the control circuitry arranges the storage elements into a serial chain (step  235 ). The processor also connects the first storage element in the chain to receive the stored data from the storage device. The stored data is read from the specified storage location and passed through the chain to the appropriate storage elements (step  240 ). The control circuitry then monitors the storage elements for a change in processor state and, upon detecting a change in state, sets the flag (step  245 ). 
     A number of embodiments have been described. Nevertheless, one of ordinary skill will understand that variations are possible. For example, some embodiments use clocking signals of particular frequencies instead of switching elements to pass data from the storage elements to the storage device. Also, some embodiments use standard tables in the processor, such as the standard “branch history table” (BHT), to distinguish between essential and non-essential data and to store only the essential data upon entering the reduced-power mode. Accordingly, other embodiments are within the scope of the following claims.