Abstract:
A display device is set forth that comprises a display panel having a plurality of pixels arranged in a matrix. A data driver supplies pixel drive signals to data lines that are connected to drive the individual pixels of at least one row of pixels with corresponding pixel drive signals. The display device also includes a gate driver that supplies gate drive signals to the gate lines of the matrix. Each gate line may be connected to concurrently drive at least one row of pixels with a respective gate drive signal. The gate driver may comprise a sequence of shift registers that are connected in cascade with one another and two or more phase clocks that are connected to drive the sequence of shift registers. The shift registers of the gate driver may be interconnected with one another so that a shift register to which a given phase clock is applied is reset using an output signal from a next occurring shift register in the sequence of shift registers that is also connected to the given phase clock.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a gate driver. More particularly, the present invention relates to a gate driver capable of providing a reliable output signal and a display device that employs the gate driver. 
     2. Description of the Related Art 
     Display devices for displaying an image by controlling pixels arranged in a matrix have been widely used. Examples of such display devices are liquid crystal display devices (LCD) and organic light emitting diode devices (OLED). Such display devices typically include a display panel having pixels arranged in a matrix, a gate driver for selectively providing a drive signal to rows of pixels on a line by line basis, and a data driver for providing drive signals to the pixels. 
     Display devices having a gate driver and/or a data driver embedded on the display panel have been developed. Such display devices attempt to achieve the advantages of a low manufacturing cost, a process simplification, lightness and slimness. When manufacturing the display panel, the gate diver and/or the data driver are/is concurrently manufactured. To this end, a plurality of thin film transistors (TFTs) are provided to control each of the pixels in the display panel, and the gate driver and/or the data driver can be manufactured through the same semiconductor process as the TFT. 
     The gate drivers of the display device typically include a plurality of shift registers for providing the requisite output signals used to drive individual rows of pixels. There may be a one-to-one correspondence between each gate line and driver. For example, when the display panel has ten gate lines, at least ten shift registers are provided to provide the corresponding output signals to the ten gate lines, respectively. 
       FIG. 1  is a block diagram of one embodiment of a known gate driver. As shown, the gate driver includes a plurality of shift registers SRC 1  through SRC[N+1] connected in cascade to each other. In this cascade arrangement, the output terminal OUT of each shift register is connected to the set terminal SET of the next shift register. The shift registers include N shift registers SRC 1  through SRC[N] corresponding to N gate lines, and a dummy shift register SRC[N+1] that is used to reset the last shift register SRC[N]. 
     The first shift register SRC 1  is set by a pulse start signal STV. The pulse start signal is synchronized with a vertical synchronization signal Vsync. Each of the shift registers SR 2  through SRC[N+1] is set by the output signal of the immediately preceding shift register in the shift register sequence. When there are N gate lines, output signals GOUT 1  through GOUT[N] of the shift registers are connected to the corresponding gate lines, and an output signal GOUT[N+1] of the dummy shift register SRC[N+1] is not connected to any gate line. 
     A first clock CKV is supplied to the odd-numbered shift registers SRC 1 , SRC 3 , . . . , and a second clock CKVB is supplied to the even-numbered shift registers SRC 2 , SRC 4 , . . . . Here, the phase of the first clock CKV is opposite to that of the second clock CKVB. The first clock CKV is connected to drive the odd-numbered shift registers SRC 1 , SRC 3 , . . . , and the second clock CKVB is connected to drive the even-numbered shift registers SRC 2 , SRC 4 , . . . . The pulse start signal STV is applied to the first shift register SRC 1  when the second clock CKVB is high. 
     The shift registers SRC 1  through SRC[N] provide the respective output signals GOUT 1  through GOUT[N] in synchronization with the first clock CKV or the second clock CKVB. Each of the shift registers SRC 1  through SRC[N] is reset by the output signal of the shift register that immediately follows it in the shift register sequence. However, since there is no shift register subsequent to the dummy shift register SRC[N+1], the dummy shift register SRC[N+1] is reset by its own output signal GOUT[N+1]. 
       FIG. 2  is a circuit diagram of the first and second shift registers illustrated in  FIG. 1 , while  FIG. 3  is a waveform diagram showing the signals used to drive the first shift register of  FIG. 2 . Since each of the shift registers illustrated in  FIG. 1  is identical in structure with the other, only the first shift register SRC 1  is described in connection with  FIGS. 2 and 3  for convenience. 
     When the pulse start signal STV is high, the first clock CKV and the second clock CKVB are low and high, respectively. Referring to  FIGS. 2 and 3 , the first shift register SRC 1  is set by a high state of the pulse start signal STV during a cycle of the second clock (CKVB) period. More particularly, when the pulse start signal STV is applied, a node Q is charged to the voltage of the pulse start signal STV. A first transistor M 1  is turned on by the voltage of the node Q. The node QB is then discharged by the voltage difference (VDD−VSS) that exists between a first power supply voltage and a second power supply voltage. As a result, the node QB is driven to and maintained at a low voltage level corresponding to the ratio of a resistance Rl of the first transistor M 1  and a resistance R 6  of a sixth transistor M 6 . 
     During a first clock (CKV) period, the first output signal GOUTl is provided in response to the first clock CKV signal. More particularly, when the first clock CKV is applied to the second transistor M 2 , a voltage boost results from pumping the drain-gate capacitance Cgd of the second transistor M 2 . Thus, the node Q is charged to a voltage level that is higher than the voltage level of the charged pulse start signal STV. Accordingly, the second transistor M 2  is turned on and the first clock CKV is provided as the first output signal GOUT 1 . 
     During the second clock (CKVB) period, the first shift register SRC 1  is reset by the output signal GOUT 2  of the next shift register SRC 2  in the shift register sequence. More particularly, when the fifth transistor MS is turned on by the second output signal GOUT 2  of the shift register SRC 2 , the node Q is discharged by the first power supply voltage VSS through the fifth transistor M 5 . Additionally, the first transistor M 1  is driven to a nonconductive state by the voltage now found at node Q. The node QB is charged using the second supply voltage VDD connected to the node QB through the sixth transistor M 6 . This causes the third and fourth transistors M 3  and M 4  to enter a conductive state. Accordingly, node Q is discharged to the first supply voltage VSS through the conductive fourth transistor M 4 . In this case, most of the output signal GOUT 1  is discharged through the source-drain path of the second transistor M 2 , and the remaining output signal GOUTl is discharged to the first power supply voltage VSS through the conductive third transistor M 3 . 
     However, an undesired output signal may be generated from each of the shift registers SRC 1  through SRC[N] in this known gate driver arrangement. As illustrated in  FIG. 4 , when a gate drive signal GOUT[N] is provided from the Nth shift register SRC[N] by the second clock CKVB, spurious drive signals are also provided from the second and fourth output signals GOUT 2  and GOUT 4  as well as from all even-numbered shift registers SRC 2  and SRC 4  to which the second clock CKVB is applied. More particularly, in addition to the desired drive signal, a plurality of undesired drive signals may be provided during one clock period. 
     The shift registers SRC 1  through SRC[N] output drive signals at the corresponding output GOUT 1  through GOUT[N] once a frame. For example, the fourth shift register SRC 4  provides the fourth output signal GOUT 4  during a period of the second clock signal (CKVB), but does not output the drive signal during the remaining period (90%) of one frame. To drive the fourth shift register in this manner, the third transistor M 3  of the fourth shift register SRC 4  must be turned on and, thus, node QB, which is connected to the third transistor M 3 , always maintains a high state during the remaining frame period. When this operation is repeated for each frame, the third and fourth transistors M 3  and M 4  are degraded. Accordingly, the threshold voltages of the third and fourth transistors M 3  and M 4  are shifted and, thus, the transistors M 3  and M 4  cannot be readily driven to a non-conductive state. In serious cases, the fourth transistor M 4  is not driven to a non-conductive state and, thus, node Q is not reset. The output signals from the shift register therefore provide spurious drive signals at undesired times in response to the first or second clock CKV or CKVB. 
     Taking this into consideration for all the shift registers SRC 1  through SRC[N], when the sixth drive signal GOUT 6  is provided from the sixth shift register SRC 6  as a result of the second clock signal CKVB, spurious drive signals are also provided at the second and fourth outputs GOUT 2  and GOUT 4  as well as from each of the even-numbered shift registers SRC 2 , SRC 4 , SRC 8 , SRC 10 , . . . to which the second clock CKVB is applied. This causes the display device to malfunction (i.e., screen flickering, etc.) thereby degrading the reliability of the product. 
     SUMMARY OF THE INVENTION 
     A display device is set forth that comprises a display panel having a plurality of pixels arranged in a matrix. A data driver supplies pixel drive signals to data lines that are connected to drive the individual pixels of at least one row of pixels with corresponding pixel drive signals. The display device also includes a gate driver that supplies gate drive signals to the gate lines of the matrix. Each gate line may be connected to concurrently drive at least one row of pixels with a respective gate drive signal. The gate driver may comprise a sequence of shift registers that are connected in cascade with one another and two or more phase clocks that are connected to drive the sequence of shift registers. The shift registers of the gate driver may be interconnected with one another so that a shift register to which a given phase clock is applied is reset using an output signal from a next occurring shift register in the sequence of shift registers that is also connected to the given phase clock. 
     Various embodiment of the display device are set forth that employ a number N shift registers in the sequence of shift registers. In one embodiment, two phase clocks are employed, and the (N−2)th shift register of the sequence of shift registers is reset by an output signal of the Nth shift register. In another embodiment, three phase clocks are employed and the (N−3)th shift register of the sequence of shift registers is reset by an output signal of the Nth shift register. In a still further embodiment, four phase clocks are employed and the (N−4)th shift register of the sequence of shift registers is reset by an output signal of the Nth shift register. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings: 
         FIG. 1  is a block diagram of one embodiment of a known gate driver; 
         FIG. 2  is a circuit diagram of a shift register that may be used in the gate driver shown in  FIG. 1 ; 
         FIG. 3  is a waveform diagram of various input and output signals associated with the shift register of  FIG. 2 ; 
         FIG. 4  is a waveform diagram illustrating a plurality of spurious drive signals that may occur in connection with the gate driver shown in  FIG. 1 ; 
         FIG. 5  is a block diagram of a first embodiment of a gate driver constructed in accordance with the teachings of the present invention; 
         FIG. 6  is a waveform diagram showing various input and output signals associated with the embodiment of the gate driver shown in  FIG. 5 ; 
         FIG. 7  is a block diagram of a second embodiment of a gate driver constructed in accordance with the teachings of the present invention; 
         FIG. 8  is a waveform diagram showing various input and output signals associated with the embodiment of the gate driver shown in  FIG. 7 ; 
         FIG. 9  is a block diagram of a third embodiment of a gate driver constructed in accordance with the teachings of the present invention; 
         FIG. 10  is a waveform diagram showing various input and output signals associated with the embodiment of the gate driver shown in  FIG. 9 ; 
         FIG. 11  is a waveform diagram of four phase clocks whose pulses partially overlap one another; and 
         FIG. 12  is a circuit diagram of one embodiment of a shift register constructed in accordance with teachings of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
     A number of different gate driver embodiments are set forth below. In each embodiment, the gate driver includes a plurality of shift registers that are connected in cascade with one another as part of a sequence of shift registers. Each sequence of shift registers is driven by two or more phase clocks signals. A unique reset arrangement is employed for each shift register of the sequence of shift registers to reduce and/or eliminate the spurious drive signals noted in connection with the existing gate driver constructions. The following gate driver embodiments show implementations that use two phase clocks, as well as higher order phase clocks such as three phase clocks and four phase clocks. The phase clocks of each embodiment may be synchronized to one or more horizontal synchronization signals that are used to provide the timing necessary to generate an image on the corresponding display. 
     First Embodiment: Two Phase Clocks 
       FIG. 5  is a block diagram of a first embodiment of a gate driver, while  FIG. 6  is a waveform diagram of various input and output signals associated with the embodiment of the gate driver of  FIG. 5 . As shown, the gate driver of this embodiment includes N shift registers SRC 1  through SRC[N] arranged in a cascading sequence and dummy shift registers SRC[N+1] and SRC[N+2]. The shift registers SRC 1  through SRC[N] are respectively connected to one of two phase clocks. The two phase clocks include a first clock signal C 1  and a second clock signal C 2 . More particularly, the first clock C 1  is commonly connected to and concurrently applied to the odd-numbered shift registers SRC 1 , SRC 3 , . . . . The second clock C 2  is commonly connected to and concurrently applied to the even-numbered shift registers SRC 2 , SRC 4 , . . . . 
     The shift registers SRC 1  through SRC[N] provide corresponding gate drive signals GOUT 1  through GOUT[N]. The gate drive signal GOUT 1  through GOUT[N] of each shift register is also provided to the input of a set terminal of the next shift register in the shift register sequence, a reset terminal of the immediately preceding shift register in the shift register sequence, and a reset terminal of the second preceding shift register in the shift register sequence. In this example, the gate drive signal GOUT 3  of the third shift register SRC 3  is provided to the set terminal of the fourth shift register SRC 4 , the reset terminal of the second shift register SRC 2 , and the reset terminal of the first shift register SRC 1 . Accordingly, the gate drive signal of the current shift register is used to set the next shift register in the shift register sequence and to reset the preceding shift register and the second preceding shift register in the shift register sequence. 
     A first power supply voltage VSS and a second power supply voltage VDD are supplied to the shift registers SRC 1  through SRC[N+2]. When each shift register is set, a node Q connected to the output terminal OUT of the shift register is charged using the second power supply voltage VDD. In contrast, when the shift register is reset, the node Q is discharged using the first power supply voltage VSS. 
     The first and second clocks C 1  and C 2  serve as two phase clocks. The first and second clocks C 1  and C 2  are alternately applied to the shift registers SCR 1  through SCR[N]. In operation, the gate drive signal of the Nth shift register is used to reset the (N−2)th shift register in the shift register sequence. In the illustrated embodiment, the gate drive signal from the current shift register connected to the first clock Cl is provided to and resets the preceding shift register to which the first clock C 1  is also applied. Similarly, the gate drive signal provided from the first of the previous registers connected to the second clock C 1  is used to reset the third of the preceding shift registers, which is also connected to receive the second clock C 2 . Accordingly, the first, second and third of the preceding shift registers do not provide spurious output signals when the current shift register provides its gate drive signal since the (N−2)th shift register is reset in response to the gate drive signal of the Nth shift register. In this case, the (N+1)th shift register and the (N+2)th shift register may be connected with one another so as to reset the (N−1)th shift register and the Nth shift register. 
     As illustrated in  FIG. 6 , the gate drive signal GOUT 3  provided from the third shift register SRC 3  in response to the first clock C 1  is used as an input signal to reset the first shift register SRC 1 , which is also connected to receive the first clock Cl. In this case, the node Q connected to the output terminal OUT of the first shift register SRC 1  is discharged to the first power supply voltage VSS. 
     Similarly, the gate drive signal GOUT 4  provided from the fourth shift register SRC 4  in response to the second clock C 2  is used as an input signal to reset the second shift register SRC 2 , which is also connected to receive the second clock C 2 . In this case, the node Q connected to an output terminal OUT of the second shift register SRC 2  is discharged to the first power supply voltage VSS. 
     By extension of the above operation, the (N−2)th shift register can be reset using the output signal of the Nth shift register. 
     Accordingly, when two phase clocks are employed, no spurious output signal are provided from the next shift register at the time when the gate drive signal is generated by the current shift register. Therefore, even when each shift register is degraded due to extended operation of the gate driver, spurious output signals from shift registers other than the one that is to be activated are reduced and/or eliminated, thereby enhancing the reliability of the product. 
     Second Embodiment: Three Phase Clocks 
       FIG. 7  is a block diagram of a second embodiment of a gate driver, while  FIG. 8  is a waveform diagram illustrating various input and output signals associated with the gate driver of  FIG. 7 . In describing the second embodiment, a description of the same content found in the first embodiment will be omitted for clarity. 
     Referring to  FIG. 7 , the shift registers SRC 1  through SRC[N+3] are connected to one of three phase clocks, including a first clock C 1 , a second clock C 2  and a third clock C 3 . More particularly, the first clock C 1  is commonly connected to and concurrently applied to the first shift register SRC 1 , the fourth shift register SRC 4 , etc. The second clock C 2  is commonly connected to and concurrently applied to the second shift register SRC 2 , the fourth shift register SRC 5 , etc. The third clock C 3  is commonly connected to and concurrently applied to the third shift register SRC 3 , the fourth shift register SRC 6 , etc. The shift registers SRC 1  through SRC[N] provide corresponding gate drive signals GOUT 1  through GOUT[N]. 
     The first gate drive signal GOUT 1  is provided from the first shift register SRC 1  in response to the first clock signal C 1 . The first gate drive signal GOUT 1  is used as an input signal to a set terminal of the second shift register SRC 2 . 
     The second gate drive signal GOUT 2  is provided from the second shift register SRC 2  in response to the second clock signal C 2 . The second gate drive signal GOUT 2  is provided as an input signal to a set terminal of the third shift register SRC 3  and to a reset terminal of the first shift register SRC 1 . Therefore, the third shift register SRC 3  is set and the first shift register SRC 1  is reset by the second gate drive signal GOUT 2 . 
     The third gate drive signal GOUT 3  is provided from the third shift register SRC 3  in response to the third clock signal C 3 . The third gate drive signal GOUT 3  also is used as an input signal to a set terminal of the fourth shift register SRC 4  and to a reset terminal of the second register SRC 2 . Therefore, the fourth shift register SRC 4  is set and the second shift register SRC 2  is reset by the third gate drive signal GOUT 3 . 
     Next, the fourth gate drive signal GOUT 4  is provided from the fourth shift register SRC 4  in response to the first clock signal C 1 . The fourth gate drive signal GOUT 4  is used as an input signal to a set terminal of the fifth shift register SRC 5 , a reset terminal of the first shift register SRC 1  and a reset terminal of the third shift register SRC 3 . And therefore, the fourth shift register SRC 5  is set and the first and third shift registers SRC 1  and SCR 3  are reset by the fourth gate drive signal GOUT 4 . 
     The fifth gate drive signal GOUT 5  is provided from the fifth shift register SRC 5  in response to the second clock signal C 2 . The fifth gate drive signal GOUT 5  is used as an input signal to a set terminal of the sixth shift register SRC 6 , a reset terminal of the second shift register SRC 2 , and a reset terminal of the fourth shift register SRC 4 . Therefore, the sixth shift register SRC 6  is set and the second and fourth shift registers SRC 2  and SRC 4  are reset by the fifth gate drive signal GOUT 5 . 
     The sixth gate drive signal GOUT 6  is provided from the sixth shift register SRC 6  in response to the third clock signal C 3 . The sixth gate drive signal GOUT 6  also is used as an input signal to a set terminal of the seventh shift register SRC 7 , a reset terminal of the third shift register SRC 3 , and a reset terminal of the fifth register SRC 5 . Therefore, the seventh shift register SRC 7  is set and the third and fifth shift registers SRC 3  and SRC 5  are reset by the sixth gate drive signal GOUT 6 . 
     The foregoing interconnection sequence is repeated for the remaining shift registers of the shift register sequence. In the illustrated embodiment, the interconnection sequence is repeated up to the (N+3)th shift register SRC[N+3]. 
     The first, second and third clocks C 1 , C 2  and C 3  operate as three phase clocks that are alternately applied to the shift registers. When three phase clock signals are employed, the gate drive signal of the Nth shift register is used to the reset the (N−3)th shift register in the shift register sequence. Meanwhile, (N+1)th, (N+2)th and (N+3)th shift registers also may be used to reset the (N−2)th, (N−1)th and Nth shift registers, respectively. 
     As illustrated in  FIG. 8 , a gate drive signal GOUT 4  provided from the fourth shift register SRC 4  in response to the first clock C 1  is used as an input signal to reset the first shift register SRC 1 , which is also connected to receive the first clock C 1 . In this case, the node Q connected to the output terminal OUT of the first shift register SRC 1  is discharged to the first power supply voltage VSS. 
     Similarly, a gate drive signal GOUT 5  provided from the fifth shift register SRC 5  in response to the second clock C 2  is used as an input signal that resets the second shift register SRC 2 , which is also connected to receive the second clock C 2 . In this case, the node Q connected to the output terminal OUT of the second shift register SRC 2  is discharged to the first power supply voltage VSS. 
     Also, a gate drive signal GOUT 6  provided from the sixth shift register SRC 6  in response to the third clock C 3  is used as an input signal that resets the third shift register SRC 3 , which is also connected to receive the third clock C 3 . In this case, the node Q connected to an output terminal OUT of the third shift register SRC 3  is discharged to the first power supply voltage VSS. 
     Through an extension of the foregoing operation, it can be seen that the (N−3)th shift register can be reset using the output signal of the Nth shift register. Accordingly, in the case of three phase clocks, spurious output signals from the next shift register at the time when an output signal is generated from the current shift register are substantially reduced and/or eliminated. Therefore, even when each shift register is degraded due to extended operation of the gate driver, the desired output signal is generated only from the corresponding shift register, thereby enhancing the reliability of the product. 
     Third Embodiment: Four Phase Clocks 
       FIG. 9  is a block diagram of a third embodiment of a gate driver, while  FIG. 10  is a waveform diagram showing various input and output associated with the gate driver of  FIG. 9 . In describing the third embodiment, a description of the same content as the first and second embodiments will be omitted for clarity. 
     Referring to  FIG. 9 , the shift registers SRC 1  through SRC[N+4] are connected to four phase clocks including a first clock C 1 , a second clock C 2 , a third clock C 3  and a fourth clock C 4 . More particularly, the first clock C 1  is commonly connected to and concurrently applied to the first shift register SRC 1 , the fifth shift register SRC 5 , etc. The second clock C 3  is commonly connected to and concurrently applied to the second shift register SRC 2 , the sixth shift register SRC 6 , etc. The third clock C 3  is commonly connected to and concurrently applied to the third shift register SRC 3 , the seven shift register SRC 7 , etc. The fourth clock C 4  is commonly connected to and concurrently applied to the fourth shift register SRC 4 , the eighth shift register SRC 8 , etc. 
     The shift registers SRC 1  through SRC[N] output corresponding gate drive signals GOUTl through GOUT[N]. The first gate drive signal GOUT 1  is provided from the first shift register SRC 1  in response to the first clock signal C 1 . The first gate drive signal GOUT 1  also is provided as an input signal to a set terminal of the second shift register SRC 2 . The second shift register SRC 2  is thus set by the first gate drive signal GOUT 1 . 
     The second gate drive signal GOUT 2  is provided from the second shift register SRC 2  in response to the second clock signal C 2 . The second gate drive signal GOUT 2  also is provided as an input signal to a set terminal of the third shift register SRC 3  and to a reset terminal of the sixth shift register SRC 6 . Therefore, the third shift register SRC 3  is set and the sixth shift register SRC 6  is reset by the second gate drive signal GOUT 2 . 
     The third gate drive signal GOUT 3  is provided from the third shift register SRC 3  in response to the third clock signal C 3 . The third gate drive signal GOUT 3  also is used as an input signal to a set terminal of the fourth shift register SRC 4  and to a reset terminal of the seventh shift register SRC 7 . Therefore, the fourth shift register SRC 4  is set and the seventh shift register SRC 7  is reset by the third gate drive signal GOUT 3 . 
     The fourth gate drive signal GOUT 4  is provided from the fourth shift register SRC 4  in response to the fourth clock signal C 4 . The fourth gate drive signal GOUT 4  also is used as an input signal to a set terminal of the fifth shift register SRC 5  and a reset terminal of the eighth shift register SRC 8 . Therefore, the fifth shift register SRC 5  is set and the eighth shift register SRC 8  is reset by the fourth gate drive signal GOUT 4 . 
     Next, the fifth gate drive signal GOUT 5  is provided from the fifth shift register SRC 5  in response to the first clock signal C 1 . The fifth gate drive signal GOUT 5  also is provided as an input signal to a set terminal of the sixth shift register SRC 6 , a reset terminal of the first shift register SRC 1  and a reset terminal of the fourth shift register SRC 4 . Therefore, the sixth shift register SRC 6  is set and the first and fourth shift registers SRC 1  and SCR 4  are reset by the fifth gate drive signal GOUT 5 . 
     The sixth gate drive signal GOUT 6  is provided from the sixth shift register SRC 6  in response to the second clock signal C 2 . The sixth gate drive signal GOUT 6  also is used as an input signal to a set terminal of the seventh shift register SRC 7 , a reset terminal of the second shift register SRC 2 , and a reset terminal of the fifth shift register SRC 5 . Therefore, the seventh shift register SRC 7  is set and the second and fifth shift register SRC 2  and SRC 5  are reset by the sixth gate drive signal GOUT 6 . 
     The seventh gate drive signal GOUT 7  is provided from the seventh shift register SRC 7  in response to the third clock signal C 3 . The seventh gate drive signal GOUT 7  also is used as an input signal to a set terminal of the eighth shift register SRC 8 , a reset terminal of the third shift register SRC 3 , and a reset terminal of the sixth register SRC 6 . Therefore, the eighth shift register SRC 8  is set and the third and sixth shift registers SRC 3  and SRC 6  are reset by the seventh gate drive signal GOUT 7 . 
     The eighth gate drive signal GOUT 8  is provided from the eighth shift register SRC 8  in response to the fourth clock signal C 4 . The eighth output signal GOUT 8  also is used as an input signal to a set terminal of the ninth shift register SRC 9 , a reset terminal of the fourth shift register SRC 4 , and a reset terminal of the seventh register SRC 7 . Therefore, the ninth shift register SRC 9  is set and the fourth and seventh shift registers SRC 4  and SRC 7  are reset by the eighth gate drive signal GOUT 8 . 
     The foregoing interconnection sequence is repeated for the remaining shift registers of the shift register sequence. In the illustrated embodiment, the interconnection sequence is repeated up to the (N+4)th shift register SRC[N+4]. 
     The first, second, third and fourth clocks C 1 , C 2 , C 3  and C 4  serve as four phase clocks and are alternately applied to the shift registers of the shift register sequence. When four phase clocks are employed, the gate drive output signal of the Nth shift register may be used to reset the (N−4)th shift register. Meanwhile, (N+1)th, (N+2)th, (N+3)th and (N+4)th shift registers may be further provided to reset the (N−3)th, (N−2)th, (N−1)th and Nth shift registers, respectively. 
     As illustrated in  FIG. 10 , the gate drive signal GOUT 5  provided from the fifth shift register SRC 5  in response to the first clock C 1  is used to reset the first shift register SRC 1 , which is also connected to receive the first clock C 1 . In this case, the node Q connected to the output terminal OUT of the first shift register SRC 1  is discharged to the first power supply voltage VSS. 
     The gate drive signal GOUT 6  provided from the sixth shift register SRC 6  in response to the second clock C 2  is used to reset the second shift register SRC 2 , which is also connected to receive the second clock C 2 . In this case, the node Q connected to the output terminal OUT of the second shift register SRC 2  is discharged to the first power supply voltage VSS. 
     The gate drive signal GOUT 7  provided from the seventh shift register SRC 7  in response to the third clock C 3  is used to reset the third shift register SRC 3 , which is also connected to receive the third clock C 3 . In this case, the node Q connected to the output terminal OUT of the third shift register SRC 3  is discharged to the first power supply voltage VSS. 
     The gate drive signal GOUT 8  provided from the eighth shift register SRC 8  in response to the fourth clock C 4  is used to reset the fourth shift register SRC 4 , which is also connected to receive the fourth clock C 4 . In this case, the node Q connected to the output terminal OUT of the fourth shift register SRC 4  is discharged to the first power supply voltage VSS. 
     By extension of the above operation, it can be seen that the (N−4)th shift register can be reset in response to the gate drive signal provided by the Nth shift register. 
     Accordingly, in case of four phase clocks, spurious output signals from the next shift register are reduced and/or eliminated at the time when the gate signal is provided from the current shift register. Therefore, even when each shift register is degraded due to extended operation of the gate driver, the desired output signal is generated solely from the proper shift register in the shift register sequence, thereby enhancing the reliability of the product. 
     When three or more phase clocks are employed, the clocks may be generated such that their high-state pulses partially overlap one another in time. One such example employing four phase clocks is illustrated in  FIG. 11 . As shown, the first and second clocks overlap each other, the second and third clocks overlap each other, and the third and fourth clocks overlap each other. The overlapping area between the clocks may be selected based on design criterion. If the clocks overlap each other by half of a clock period, the first and third clocks will be synchronized with each other and the second and fourth clocks will be synchronized with each other. 
       FIG. 12  is a circuit diagram of one embodiment of the shift registers that may be used to construct the embodiment of the gate drivers noted above. All of the shift registers of a single gate driver embodiment may have the same structure. For convenience of description, the fifth shift register SRC 5  using the four phase clocks is used in the example of  FIG. 12 . 
     Referring to  FIG. 12 , the fifth shift register SRC 5  includes second and third transistors M 2  and M 3  for controlling the fifth gate drive signal GOUT 5 . The second transistor M 2  includes a gate connected to a node Q, a drain connected to the first clock C 1 , and a source connected to the fifth gate drive signal GOUT 5 . The third transistor M 3  includes a gate connected to a node QB, a drain connected to the fifth gate drive signal GOUT 5 , and a source connected to the first power supply voltage VSS. Accordingly, the second transistor M 2  is switched between a conductive and non-conductive state in response to the charge/discharge of the node Q, and the third transistor M 3  is switched between a conductive and non-conductive state in response to the charge/discharge of the node QB. 
     The node Q is charged by the fourth gate drive signal GOUT 4  of the fourth shift register SRC 4 . Also, the Q node is discharged by the voltage VSS provided by the first power supply. As shown, voltage VSS is provided through a fifth transistor M 5  when the fifth transistor is driven to a conductive state by the sixth gate drive signal GOUT 6  of a sixth shift register SRC 6  and through a fourth transistor M 4  when it is driven to a conductive state by the voltage at node QB. The fifth transistor M 5  includes a gate that is connected to the gate drive signal GOUT 6  of the sixth shift register SRC 6 , a drain that is connected to node Q, and a source connected to receive the voltage VSS from the first power supply. The fourth transistor M 4  includes a gate connected to node QB, a drain connected to node Q, and a source connected to the receive the voltage VSS from the first power supply. When the fifth transistor M 5  is driven to a conductive state by the gate drive signal GOUT 6  of the sixth shift register SRC 6 , node Q is discharged approximately to the first power supply voltage VSS. When node QB is charged using the second power supply voltage VDD, the fourth transistor M 4  is driven to a conductive state through the charging of node QB, while node Q is discharged approximately to the first power supply voltage VSS. 
     Also, node Q can be discharged using the first power supply voltage VSS when the sixth transistor M 6  is driven to a conductive state by the first gate drive signal GOUT 1  of the first shift register SRC 1 . The sixth transistor M 6  includes a gate connected to the gate drive signal GOUT 9  of the ninth shift register SRC 9 , a drain connected to node Q, and a source connected to receive the first power supply voltage VSS. 
     The shift register circuit may be manufactured in a monolithic substrate. In such instances the width of the sixth transistor M 6  optionally may be greater or smaller than the width of the fifth transistor M 5 . For example, the sixth transistor M 6  may have 0.5˜1.5 times the width of the fifth transistor M 5 . 
     The charge at node Q of this embodiment is reset in response to the gate drive signal GOUT 9  of the ninth shift register SRC 9 . More particularly, the fifth shift register SRC 5  to which the first clock C 1  is applied is reset by the gate drive signal GOUT 9  that is generated by the ninth shift register SRC 9  in response to the first clock C 1 . When the gate drive signal (e.g., GOUT 1 ) is generated by the shift register (e.g., the first shift register SRC 9 ) before the fifth shift register SRC 5  in response to the first clock C 1 , the fifth gate drive signal GOUT 5  is inhibited from being provided from the fifth shift register SRC 5  (to which the first clock is also applied), even under extended operation of the gate driver. Since all the shift registers following the current shift register in the shift register sequence are reset, the next shift register in the sequence that is connected to the same phase clock does not generate any output signal at the time when the current shift register provides its gate drive signal. 
     Node QB is charged approximately to the second power supply voltage VDD, and is discharged approximately to the first power supply voltage VSS that is supplied through the first transistor M 1  switched on by the Q node. The first transistor M 1  includes a gate connected to node Q, a drain connected to node QB, and a source connected to receive the first power supply voltage VSS. When node Q is charged in response to a positive voltage of the fourth gate drive signal GOUT 4  of the fourth shift register SRC 4 , the first transistor M 1  is driven to a conductive state. Similarly, a positive voltage of the fourth gate drive signal GOUT 4  discharges node QB to a voltage level that is approximately equal to the first power supply voltage VSS. 
     Node QB is discharged to a voltage level approximately equal to voltage VSS when a ninth transistor M 9  is driven to a conductive state by the fourth gate drive signal GOUT 4  of the fourth shift register SRC 4 . The ninth transistor M 9  includes a gate connected to the fourth gate drive signal GOUT 4  of the fourth shift register SRC 4 , a drain connected to node QB, and a source connected to receive the first power supply voltage VSS. 
     A seventh transistor M 7  is also employed. The seventh transistor M 7  includes a gate and a drain connected to the gate drive signal GOUT 4  of the fourth shift register SRC 4  and a source connected to node Q. Transistor M 7  may be provided to prevent a reverse current flow from the Q node to the gate drive signal GOUT 4  of the fourth shift register SRC 4 . 
     Also, an eighth transistor M 8  may be employed. The eighth transistor M 8  may include a gate and a drain connected commonly to the second power supply voltage VDD and a source connected to node QB. Transistor M 8  may be provided to prevent a reverse current flow from node QB to the second power supply voltage VDD. 
     Accordingly, by an output signal outputted by a predetermined clock, the previous shift register to which the predetermined clock is also applied can be reset. Accordingly, an output signal can be outputted only at a desired time by the predetermined time. 
     As described above, the gate driver includes a plurality of shift registers, and the previous shift resister to which a predetermined clock is applied is reset using an output signal that is outputted from the next shift register by the predetermined clock. Accordingly, a plurality of output signals can be prevented from being simultaneously outputted from the shift registers to which the identical clock is applied. Therefore, a corresponding output signal can be outputted from the gate driver only at a desired time. Accordingly, the reliable output signal can be obtained. 
     Consequently, the malfunction of the device can be prevented and the lifetime of the device can be extended. 
     Also, the screen flickering that may occur due to a plurality of output signals can be prevented and thus the image quality can be enhanced. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.