Abstract:
Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

Description:
[0001]     This application relies for priority upon Korean Patent Application No. 2003-0088282 filed on Dec. 5, 2003, the contents of which are herein incorporated by reference in their entirety.  
       BACKGROUND  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a circuit for controlling a pulse width, and more particularly to, a circuit for controlling a pulse width of a column address select signal.  
         [0004]     2. Discussion of Related Art  
         [0005]     Recently, a high speed DRAM or DDR has been used in a graphic field. A pulse width, especially a pulse width of a column address select signal remarkably influences an operation of the device.  
         [0006]     It is thus very important to control an appropriate pulse width of the column address select signal according to various conditions such as a low frequency to a high frequency. In general, the pulse width of the column address select signal is preset as a predetermined value or controlled by an external clock.  
         [0007]     A method for setting a pulse width of a column address select signal as a predetermined value generates a predetermined width of pulse regardless of tCK, namely a frequency. However, a standard for controlling the pulse width is ambiguous. When the pulse width is set at a low frequency, tCCD or tWTR is generated in a high frequency operation, to cause operation failure. Conversely, when the pulse width is set at a high frequency, the pulse width is too narrow to deteriorate tWR. Accordingly, data are not sufficiently written on a DRAM cell.  
         [0008]     A method for controlling a column address select signal according to an external clock is not sensitive to variations of a process, voltage and temperature, and thus is relatively stable at a high frequency. However, the column address select signal has a narrow pulse width corresponding to half of a pulse width of the external clock. Differently from a DDR1, a DDR2 SDRAM maintains 2tCK of tCCD, and thus the column address select signal has a pulse width larger than half of the pulse width of the external clock (maximally, two times). Therefore, the DDR2 SDRAM cannot increase an operational margin. In addition, when the column address select signal is controlled according to the external clock, the pulse width of the column address select signal is large enough at a low frequency to cause problems in a normal operation or a test.  
       SUMMARY OF THE INVENTION  
       [0009]     The present invention is directed to a pulse width control circuit for controlling a pulse width by using a delay time according to a CAS latency set in a mode register set MRS  
         [0010]     One aspect of the present invention is to provide a circuit for controlling a pulse width which can solve the above problems by generating a pulse width varied in response to an operation frequency.  
         [0011]     Here, a DRAM for a desktop or a DRAM for a graphic field which has been used requires a high speed operation and supplies many number of CAS latencies (hereinafter, referred as to CL) as an external clock gets fast. In case of a high frequency DRAM, the CL has been supplied for 2˜9, and may be supplied more than that henceforth. Here, as an operation is performed in a high speed, the CL is larger.  
         [0012]     In the present invention, an operation frequency of DRAM is analogized by using the CL set in the mode register set MRS, and the CL is inputted in a pulse delay unit of a column address select signal generation circuit. During this, the CL has a fixed value which isn&#39;t varied until the next MRS is set for the level signal. The CLs inputted in the pulse delay unit have their own delay time for each, and the pulse width control unit can control a pulse with an appropriate width by using a delay pulse outputted according to the delay time. As a result, the column address select signal can have an optimized pulse width for the CLs. Accordingly, it can improve stabilization of an asynchronous signal in the DRAM.  
         [0013]     A pulse width control circuit in accordance with the present invention includes: a means for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse with a variable width by using a delay time according to the plurality of CAS latencies.  
         [0014]     The pulse generation circuit includes: a pulse generation unit for generating a pulse according to a plurality of control signals; a latch for latching the pulse generated from the pulse generator; a pulse width control unit for controlling a pulse width by delaying a signal outputted from the latch by using a delay time according to the plurality of CAS latencies; and a logic unit for combining the output signal of the latch and an output signal of the pulse delay unit.  
         [0015]     The pulse generation circuit further includes a plurality of delay means for delaying the pulse generated from the signal generation unit.  
         [0016]     The pulse generation unit includes: a NAND gate for receiving a first control signal and a second control signal; and a NOR gate for generating a pulse by receiving an output signal from the NAND gate and third and fourth control signals.  
         [0017]     The pulse width control unit includes: a plurality of delay means for delaying the pulse outputted from the latch; and a plurality of switching means connected respectively to output terminals of the plurality of delay means and driven by each CAS latency inputted from the mode register set, for setting a delay path.  
         [0018]     The switching means are comprised of: an inverter for inverting the plurality of CAS latencies, respectively; and a plurality of transmission gates driven by the plurality of CAS latencies and output signals of the plurality of inverters.  
         [0019]     The logic means is a NAND gate.  
         [0020]     In addition, the pulse width control circuit in accordance with the present invention includes: a means for setting the plurality of CAS latencies according to a command inputted from a chip set; a pulse generation unit for generating a pulse by a plurality of control signals; a latch for latching the pulse generated from the pulse generation unit; a pulse width control unit for controlling the pulse with a variable width according to an operation frequency by delaying the signal outputted from the latch, by using the delay time according to the plurality of CAS latencies; and a logic means for combining a signal outputted from the latch and an output signal of the pulse width control unit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]     A more complete understanding of the present invention may be had by reference to the following description when taken in conjunction with the accompanying drawings in which:  
         [0022]      FIG. 1  is a schematic diagram of a pulse width control circuit in accordance with an embodiment of the present invention;  
         [0023]      FIGS. 2A and 2B  are circuit diagrams illustrating a pulse generation circuit in accordance with embodiments of the present invention; and  
         [0024]      FIG. 3  is a circuit diagram of a pulse width control unit of  FIG. 2 . 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0025]     Hereinafter, it will be described about the present invention with reference to the accompanying drawings in detail.  
         [0026]      FIG. 1  is a block diagram for controlling a pulse width of a column address select signal according to an embodiment of the present invention, which will be described as follows.  
         [0027]     When a corresponding MRS code is inputted in an external chip set  100 , a CL corresponding to the code is set in a mode register set  200 . For instance, the CL is approximately 2˜9 in a high frequency DRAM for a graphic so that it is assumed the CL as 2˜9 in the present invention. The set CL is inputted to a pulse width control unit  3   1   0  of a column address signal generation circuit  300  for generating a column address select signal. The CLs inputted in the pulse width control unit  310  have their own delay time, respectively and then a delay pulse outputted thereof is generated as the column address select signal having an optimized pulse width in the pulse width control unit  310 .  
         [0028]      FIGS. 2A and 2B  are circuit diagrams of a column address select signal generation circuit in accordance with the present invention, which will be described as follows.  
         [0029]     A first inverter I 301  inverts a read column pulse casp 6 _rd, and a second inverter I 302  inverts an output of the first inverter I 301 . Moreover, a third inverter I 303  inverts a write column pulse casp 6 _wt, and a fourth inverter I 304  inverts an output of the third inverter I 303 . Furthermore, a first NAND gate  301  inputs an internal column access pulse icasp 6  and a column activation pulse cast 12   x  and then logically combines the two signals, and a fifth inverter I 305  inverts an output of the first NAND gate  301 . A first NOR gate  302  inputs outputs of the second, fourth, and fifth inverters I 302 , I 304 , I 305  and then logically combines them. A delay time for an output signal S 301  of the first NOR gate  302  is decided by a plurality of delay means  303 ,  304 ,  305  alternatively operated by a plurality of switches SW 301  to SW 304 . A first latch  308  comprised of a second NAND gate  306  and a third NAND gate  307  latches the output signal S 301  of the first NOR gate  302  and an output signal yi_width of the pulse width control unit  310 . Here, the second NAND gate  306  inputs the output signal S 301  of the first NAND gate  302  and an output signal S 303  of the third NAND gate  307 , and the third NAND gate  307  inputs an output signal S 302  of the second NAND gate  306 , the output signal yi_width of the pulse width control unit  310 , and a power-up signal pwrup. The pulse width control unit  310  inputs the plurality of CLs applied from the mode register set  200  and controls a pulse width of the output signal S 302  of the second NAND gate  306  according to the delay time by the CLs. As a result, the output signal yi_width is outputted. The fourth NAND gate  309  inputs the output signal S 302  of the first latch  308  and the output signal yi_width of the pulse width control unit  310  and then logically combines them. Sixth to eighth inverters  1306  to  1308  invert and delay an output signal of the fourth NAND gate  308 , to output a column address select signal yi.  
         [0030]     It will be explained of a method for driving the column address signal generation circuit according to the present invention constructed as described above.  
         [0031]     When the read column pulse casp 16 _rd or the write column pulse casp 6 _wt is applied to a high state, or the internal column access pulse icasp 6  and the column activation pulse cast 12   x  are applied to a high state at the same time, the first NOR gate  302  logically combines them, to output a low state pulse S 301 . The output pulse S 301  of the first NOR gate  302  maintaining a low state is inputted into the second NAND gate  306  of the first latch  308 , and the second NAND gate  306  outputs a high state output signal S 302 . The output signal S 302  of the second NAND gate  306  maintaining a high state is inputted into the third NAND gate  307  and the pulse width control unit  310 . When the output signal S 302  of the first latch  308  is inputted, the pulse width control unit  310  sets a corresponding path according to the CL inputted from the mode register set. Accordingly, the output signal yi_width of which the pulse width is controlled by passing through an appropriate delay time according to the CL, is outputted. In addition, the fourth NAND gate  309  receives the output signal S 302  of the first latch  308  and the output signal yi_width of the pulse width control unit  310  and logically combines them to output a low state pulse. The output pulse of the fourth NAND gate  309  maintaining a low state outputs a high state column address select signal yi through the sixth to eighth inverters I 306  to I 308 . On the other hand, the output signal of the pulse width control unit  310  is inputted into the third NAND gate  307  with the output signal S 302  of the second NAND gate  306  and the power-up signal pwrup and then is logically combined. The output signal S 303  of the third NAND gate  307  is inputted into the second NAND gate  306 .  
         [0032]      FIG. 3  is a circuit diagram of the pulse width control unit of  FIG. 2 .  
         [0033]     The pulse width control unit according to the present invention is comprised of: a plurality of delay means  311  to  318  connected in series for delaying an input signal IN; a plurality of transmission gates T 311  to T 318  as a plurality of switching means for setting a delay path by being driven according to each CL which is inverted by each CL and inverters I 311  to I 318 ; and an inverter I 319  for inverting a signal delayed through each delay means  211  to  214 .  
         [0034]     The pulse width control unit constructed as described above controls a delay time of an output signal out by deciding a delay path according to the CL. For instance, when the CL set in the mode register set is  6 , only CL 6  is applied to a high state, and the other CLs are all applied to a low state. The fourth transmission gate T 314  is turned on by the CL 6  applied to a high state and a signal inverted to a low state by the fourth inverter I 314 . Accordingly, the input signal IN is delayed through the first to fourth delay means  311  to  314 , and the delayed signal is inverted through the inverter I 319 , to be outputted as the output signal out. As the CL is decreased, the delay time is longer, which results in an increase of the pulse width.  
         [0035]     As aforementioned, it is possible to generate the pulse with a variable width according to the operation frequency by analogizing the operation frequency of the DRAM by means of using the CL set in a mode register set, and controlling the pulse width by means of a delay time according to the CL. Therefore, the circuit for controlling the pulse width can be applied to a next generation standard DRAM such as a high speed DDR 2  or DDR 3  as well as a high speed graphic DRAM for supporting various CLs.  
         [0036]     Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention.