Abstract:
A voltage adjusting circuit includes a half VCC generator that generates a first voltage of a half VCC level or the like in accordance with a precharge input signal, and voltage compensator coupled respectively to output terminals of the half VCC generator. The voltage compensator compensates for a variation of the first voltage generated due to variations of a power supply voltage and a load. The first voltage is increased by supplying electric charges to the output terminals if the first voltage is less than a predetermined level, and the first voltage is decreased by sending the electric charges of the output terminal to the ground if the first voltage is greater than a predetermined level.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage adjusting circuit, and in particular, to a voltage adjusting circuit capable of stabilizing a voltage used as a cell plate voltage and a bit line precharge voltage for a dynamic random access memory (DRAM). 
     2. Background of the Related Art 
     In the related art, a half VCC voltage is used as a cell plate voltage V CP  for a capacitor electrode to determine a quantity of electric charge of a signal, or as a bit line precharge voltage V BLP  to determine a standard of signal detection. Accordingly, a half VCC generating circuit must rapidly respond to variations of a power supply voltage VCC and a load to maintain precision of the half VCC voltage. 
     FIG. 1 illustrates a block diagram of a related art half VCC generating circuit  100  that generates the bit line precharge voltage V BLP  and the cell plate voltage V CP  in accordance with a bit line precharge signal BLP. 
     FIG. 2 illustrates a first example of the related art half VCC generating circuit  100  consisting of first and second resistors R 1 , R 2  and having an output voltage Vout represented by: 
     
       
         Vout=(R 1 /(R 1 +R 2 ))*VCC.  (1)  
       
     
     When the first resistor R 1  and the second resistor R 2  have substantially equal resistances, the power supply voltage VCC is divided equally by the first and second resistors R 1 , R 2 . Thus, the output voltage Vout becomes a half VCC voltage. The first example of the related art half VCC generating circuit  100  includes only the first and second resistors R 1 , R 2 , and is thus quite simple. 
     However, the first related art example has various disadvantages. For example, the related art first example circuit consumes much current. 
     FIG. 3 illustrates a second example of the related art half VCC generating circuit  100 , having a bias circuit  10  that reduces current consumption and a push-pull output circuit  11  that enhances a driving force. The bias circuit  10  includes first and second transistors QN 1 , QP 1  and first and second resistors R 1 , R 2 . The first transistor QN 1  is of a diode NMOS type, and has a first electrode and a control electrode commonly connected to the first resistor R 1  at a first node N 1 . The first transistor QN 1  has a second electrode commonly connected to a first electrode and a control electrode of the second transistor QP 1  at a second node N 2 , wherein the second transistor is of a diode PMOS type. A second electrode and the control electrode of the second transistor QP 1  are commonly connected to the second resistor R 2  at a third node N 3 . The first resistor R 1  is connected between the first node N 1  and the power supply voltage VCC, and the second resistor R 2  is connected between the third node N 3  and the ground VSS. 
     The push-pull circuit  11  includes a third NMOS transistor QN 2  and a fourth PMOS transistor QP 2 . The third transistor QN 2  has a first electrode connected to the power supply voltage VCC, a control electrode connected to the first node N 1 , and a second electrode commonly connected to the output voltage Vout and a first electrode of the fourth transistor QP 2 . The fourth transistor QP 2  also has a control electrode connected to the third node N 3  and a second electrode connected to the ground VSS. 
     If the resistances of the first and second resistors R 1 , R 2  are sufficiently large in the bias circuit  10 , a voltage of the second node N 2  becomes the half VCC voltage, as described above. When threshold voltages of the first through fourth transistors QN 1 , QP 1 , QN 2 , QP 2  are equally set at Vt, voltages of the first and third nodes N 1 , N 3  are equal to (VCC/2)+Vt and (VCC/2)−Vt, respectively. As a result, a stable half VCC voltage is generated as the output voltage Vout. A gate-source voltage V GS  of the third and fourth transistors QN 2 , QP 2  in the push-pull output circuit  11  is also set at Vt, and thus, the third transistor QN 2  and the fourth transistor QP 2  are at a state just before being fully transited to the “ON” position, and a through current flows therein. 
     Accordingly, when the output voltage Vout is varied from the half VCC voltage, one of the third and fourth transistors QN 2 , QP 2  is transited to the “ON” position, and the other is fully transited to the “OFF” position, to rapidly restrict variation of the half VCC voltage. Since N-well bias voltages of the second and fourth transistors QP 1 , QP 2  are a half VCC voltage and a full VCC voltage, respectively, the fourth transistor QP 2  receives more back gate effects than the second transistor QP 1 , and thus, a threshold voltage Vtp 2  of the fourth transistor QP 2  becomes greater than a threshold voltage Vtp 1  of the second transistor QP 1 . As a result, when the output voltage Vout maintains a half VCC level, the second transistor QP 2  is always transited to the “ON” position, and thus the through current does not flow in the push-pull output circuit  11 . 
     Even if the third transistor QN 2  and the fourth transistor QP 2  are sufficiently increased in size to have a large load capacity, the consumption of power at the push-pull output circuit  11  is not increased. In addition, the current flowing in the bias circuit  10  can be reduced by increasing the values of the first and second resistors R 1 , R 2 . 
     However, the related art half VCC generating circuit has various problems and disadvantages. The cell plate voltage V CP  depends on the VCC voltage, especially at a low voltage. Thus, the transient property of the related art circuit can result in various problems. For example, an absolute value difference of the threshold voltages of the NMOS type transistor and the PMOS the transistor becomes a setting error of the half VCC voltage generating circuit. When the NMOS transistor and PMOS transistor each have a process error of ±0.1V, respectively, the absolute value of the error of the half VCC voltage generating circuit equals 0.2V. Further, if the external power supply voltage is decreased, the relative error increases. 
     In addition, when a capacitance of the cell plate electrode or the bit line is increased four times in accordance with a generation of a dynamic random access memory DRAM, the driving capacity of the half VCC voltage generating circuit does not improve significantly, thereby worsening a transient response property of the half VCC generating circuit. A significant amount of time is thus required to obtain the stable half VCC voltage when the power supply voltage is applied. Furthermore, the half VCC generating circuit cannot rapidly respond to a sharp variation of the load or a VCC variation during operation of the DRAM. 
     FIG. 4 graphically illustrates a variation of the half VCC voltage according to the load variation in an active mode and a standby mode that results in various problems and disadvantages. The half voltage outputted from the half VCC voltage generating circuit  100  maintains a constant level at an initial operation, but decreases due to the current consumption in the active mode, including a read/write operation and a sense amp operation. If the half VCC voltage becomes lower than ΔV, a defect may occur in a cell data. 
     Additionally, the half VCC voltage cannot maintain a predetermined level and causes voltage bouncing when the standby mode (i.e., a refresh operation) has a load. This phenomenon often takes place during an auto refresh operation, thus influencing the DRAM operation. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a voltage adjusting circuit that stably maintains a voltage, regardless of variations of an external voltage and a load. 
     It is another object of the present invention to provide a voltage adjusting circuit that can respond rapidly to a sharp variation in the load or VCC during operation, and improve a transient response property of the voltage adjusting circuit. 
     In order to achieve the above-described object of the present invention, there is provided a voltage adjuster circuit including a half VCC circuit configured to output a first voltage of a half VCC level in accordance with a precharge signal, and at least one voltage compensator coupled to an output terminal of the half VCC circuit configured to compensate for a variation of the first voltage. When the first voltage is lower than a predetermined level, the voltage compensating unit increases a level of the first voltage by supplying electric charges to the output terminal. If the first voltage is higher than a predetermined level, the voltage compensating unit decreases the level of the first voltage by taking out the electric charges of the output terminal to the ground. 
     A voltage adjusting circuit is provided that comprises a reference voltage generator circuit configured to divide a first prescribed voltage, and generate first and second reference voltages. The voltage adjusting circuit also includes a comparing circuit coupled to the reference voltage generator circuit, configured to compare the first and second reference voltages generated by the reference voltage generator circuit with an inputted first voltage, and configured to generate first and second control signals. Further, the voltage adjusting circuit includes an output circuit coupled to the comparing circuit, configured to stabilize the first voltage based on the first and second control signals. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements, and wherein: 
     FIG. 1 illustrates a block diagram of a related art half VCC generating circuit; 
     FIG. 2 illustrates a first example of the related art half VCC generating circuit having a plurality of resistors; 
     FIG. 3 illustrates a second example of the related art half VCC generating circuit having a bias circuit and a push-pull output circuit; 
     FIG. 4 illustrates a variation of the related art half VCC voltage resulting from a load variation in an active mode and a standby mode in the configurations of FIGS. 2 and 3; 
     FIG. 5 illustrates a block diagram of a voltage adjusting circuit according to a preferred embodiment of the present invention; 
     FIG. 6 illustrates additional details of the voltage compensating circuit according to the preferred embodiment of the present invention; and 
     FIG. 7 illustrates a variation of the half VCC voltage resulting from a load variation in an active mode and a standby mode according to a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     FIG. 5 illustrates a voltage adjusting circuit according to a preferred embodiment of the present invention. The voltage adjusting circuit includes a half VCC generating circuit  100  that receives a bit line precharge signal BLP, and first and second voltage compensating circuits  101 ,  102  coupled to first and second output terminals  50 ,  51  of the half VCC generating circuit  100  that stabilizes a bit line precharge voltage V BLP  and a cell plate voltage V CP , respectively. 
     In the preferred embodiment, the bit line precharge voltage V BLP  and the cell plate voltage V CP  generated by the half VCC generating circuit  100  are received by the first and second voltage compensating circuits  101 ,  102 , respectively, through the first and second output terminals  50 ,  51 , respectively. The first voltage compensating circuit  101  compares the first and second reference voltages Vref 1 , Vref 2  with the bit line precharge voltage V BLP , and compensates for a variation (i.e., bouncing) of the bit line precharge voltage V BLP . The second voltage compensating circuit  102  compares the first and second reference voltages Vref 1 , Vref 2  with the cell plate voltage V CP , and compensates for a variation (i.e., bouncing) of the cell plate voltage V CP . 
     The first and second voltage compensating circuits  101 ,  102  are substantially identical in constitution and operation, and thus the discussion of the first voltage compensating circuit  101  can be applied to the second voltage compensating circuit  102 , wherein the cell plate voltage V CP  instead of the bit line precharge voltage V BLP  is received from the half VCC generating circuit  100 . 
     Because the first and second voltages compensating circuits  101 ,  102  are substantially similar, FIG. 6 illustrates a detailed diagram of the first voltage compensating circuit  101 . A reference voltage generating circuit  20  divides the power supply voltage, and generates first and second reference voltages Vref 1 , Vref 2  and comparing circuit  21  compares the first and second reference voltages Vref 1 , Vref 2  with the bit line precharge voltage V BLP . The comparing circuit  21  generates first and second control signals CS 1 , CS 2  that are received by an output circuit  22  that stabilizes the bit line precharge voltage V BLP  from the first output terminal  50  in accordance with the first and second control signals CS 1 , CS 2 . 
     The reference voltage generating circuit  20  illustrated in FIG. 6 includes first and second transistors QP 10 , QP 11 , first and second resistors R 10 , R 12 , and a variable resistor R 11 . The first and second transistors QP 10 , QP 11  are substantially similar in size and are of a diode PMOS type, and the first and second resistors R 10 , R 12  have a resistance substantially higher than that of the variable resistor R 11 . The first resistor R 11  and the second resistor R 12  also have substantially similar resistances. Further, the variable resistor R 11  preferably includes a plurality of small resistors coupled in series, and is fuse- or option-processed. 
     The first transistor QP 10  is coupled in series between the power supply voltage VCC and the first resistor R 10 , and has a first electrode coupled to the power supply voltage VCC, a second electrode coupled in series to the first resistor R 10 , and a control electrode commonly coupled to the first resistor R 10 . The first resistor R 10  is also coupled in series to the variable resistor R 11  at a first node N 10  where the first reference voltage Vref 1  is generated. 
     The second transistor QP 11  is coupled in series between the ground VSS and the second resistor R 12 , wherein a control electrode is commonly coupled to the ground VSS, a first electrode is coupled in series to the ground, and a second electrode is coupled in series to the second resistor R 12 . The second resistor R 12  is also coupled in series to the variable resistor R 11  at a second node N 11 , where the second reference voltage Vref 2 . 
     The comparing circuit  21  includes first and second differential amplifiers DA 1 , DA 2 . The first differential amplifier DA 1  has first and second inputs coupled to the first node N 10  and the bit line precharge voltage V BLP  or the like. The first differential amplifier DA 1  compares the first reference voltage Vref 1  at an inverted terminal with the bit line precharge voltage V BLP  or the like, from the first output terminal  50  or the cell plate voltage V CP  from the second output terminal  51 , or the like, at a non-inverted terminal and generates the first control signal CS 1 . The second differential amplifier DA 2  has first and second inputs coupled to the second node N 11  and the bit line voltage V BLP  from the first output terminal  50 . The second differential amplifier DA 2  compares the second reference voltage Vref 2  at an inverted terminal with the bit line precharge voltage V BLP  or the like at a non-inverted terminal and generates the second control signal CS 2 . 
     The output circuit  22  includes a third transistor QP 12  of the PMOS type and a fourth transistor QN 10  of the NMOS type coupled in series between the power supply voltage VCC and the ground VSS, and controlled according to the first and second control signals CS 1 , CS 2 . A control electrode of the third transistor QP 12  receives the second control signal CS 2  and a control electrode of the fourth transistor QN 10  receives the first control signal CS 1 . First electrodes of the third and fourth transistors QP 12 , QN 10  are coupled to the power supply voltage VCC and ground Vss, respectively. Second electrodes of the third and fourth transistors QP 12 , QN 10  are commonly coupled at a third node N 12  to the bit line precharge voltage V BLP  or the like, in the case of the first voltage compensating circuit  101 . 
     Further, the above-discussed features of the first voltage compensating circuit  101  are substantially similar to the features of the second voltage compensating circuit  102 , except that the first voltage compensating circuit  101  receives the bit line precharge voltage V BLP  from the first output terminal  50 , whereas the second voltage compensating circuit  102  receives the cell plate voltage from the second output terminal  51 . Thus, the above-discussed features of the first voltage compensating circuit  101  apply to the second voltage compensating circuit  102 , with the substitution of the cell plate voltage V CP  from the second output terminal  51  for the bit line precharge voltage V BLP  from the first output terminal  50  in the second voltage compensating circuit  102 . 
     In operations of the first voltage compensating circuit  101 , when the power supply voltage VCC is applied to the reference voltage generating circuit  20 , the first reference voltage Vref 1  having a value of VCC/2+ΔV is applied to the first node N 10 , and the second reference voltage Vref 2  having a value of VCC/2−ΔV is applied to the second node N 11 . The values of the first and second references voltages Vref 1 , Vref 2  are based on the first and second resistances R 10 , R 12  having an identical resistance value, and first and second resistors R 10 , R 12  having a substantially larger value than the variable resistance R 11 . 
     When the first and second reference voltages Vref 1 , Vref 2  are generated from the reference voltage generating circuit  20 , the first differential amplifier DA 1  of the comparing circuit  21  differentially amplifies the first reference voltage precharge Vref 1  received at the inverted terminal, and the bit line precharge voltage V BLP  received at the non-inverted terminal. The second differential amplifier DA 2  differentially amplifies the second reference voltage Vref 2  received at the inverted terminal, and the bit line precharge voltage V BLP  received at the non-inverted terminal. 
     If the bit line precharge voltage V BLP  is less than the first reference voltage Vref 1 , and greater than the second reference voltage Vref 2 , the first and second control signals CS 1 , CS 2  generated by the first and second differential amplifiers DA 1 , DA 2 , respectively are transited to a “LOW” and a “HIGH” level, respectively. As a result, the third transistor QP 12  and the fourth transistor QN 10  of the output circuit  22  are transited to the “OFF” position based on the first and second control signals CS 1 , CS 2 . Thus, the bit line precharge voltage V BLP  is not varied. 
     If the bit line precharge voltage V BLP  is less than the second reference voltage Vref 2 , the first and second control signals CS 1 , CS 2  generated by the first and second differential amplifiers DA 1 , DA 2  are transited to a “LOW” level. Accordingly, the third transistor QP 12  is transited to the “ON” position, and the fourth transistor QN 10  is transited to the “OFF” position. As a result, the current flows to the third node N 12  through the third transistor QP 12  which is in the “ON” position, thereby stably maintaining the level of the bit line precharge voltage V BLP . 
     Alternatively, when the level of the bit line precharge voltage V BLP  is greater than the first reference voltage Vref 1 , the first and second control signals CS 1 , CS 2  generated by the first and second differential amplifiers DA 1 , DA 2  are transited to a “HIGH” level. Accordingly, the third transistor QP 12  is transited to the “OFF” position, and the fourth transistor QN 10  is transited to the “ON” position. As a result, the current flows to the ground VSS via the fourth transistor QN 10  which is in the “ON” position, thereby stably maintaining the level of the bit line precharge voltage V BLP . 
     As shown in FIG. 7, even if the bit line precharge voltage V BLP  (e.g., the cell plate voltage V CP  or the like) is varied because of variations such as in an external power supply voltage VCC and/or a load, the preferred embodiment of a voltage adjusting circuit in accordance with the present invention can obtain the stabilized bit line precharge voltage V BLP , as compared with the related art. In the preferred embodiment of the present invention shown in FIG. 7, the first voltage compensating circuit  101  is exemplified. When the second voltage compensating circuit  102  is employed, a substantially similar result may be obtained for the cell plate voltage V CP . That is, the cell plate voltage V CP  may be maintained at the half VCC level. 
     However, the present invention is not intended to be so limited. For example, additional voltages in the DRAM can be stabilized other than the bitline precharge V BLP , the cell plate voltage V CP  or the like. Further, the stabilized voltage can have other values than the half VCC level such as one third ({fraction (1/3+L )}) VCC or one quarter ({fraction (1/4+L )}) VCC. 
     As described above, preferred embodiments of a voltage adjusting circuit according to the present invention have various advantages. For example, the voltage adjusting circuit in accordance with the preferred embodiment of the present invention can stably maintain the cell plate voltage V CP  and the bit line precharge voltage V BLP  that can vary due to the variations of the external power supply voltage and the load, by rapidly responding to such variations. 
     The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures.