Abstract:
A semiconductor device is fabricated by a method that includes forming a conductive pattern on a semiconductor substrate, covering the conductive pattern with a dielectric layer, and planarizing the dielectric layer by chemical-mechanical polishing. To avoid global height differences, a dummy pattern is added to the conductive pattern if a predetermined condition is satisfied. The condition is based on the calculated density of the conductive pattern in a region including the region in which the dummy pattern is to be added. The calculated density may be adjusted according to the type of equipment used to deposit the dielectric layer, and the dummy pattern dimensions may be adjusted according to the calculated density. Such calculations avoid the need for human judgment and lead to more uniform planarization.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a method of fabricating a semiconductor device. In particular, it relates to a method of deciding whether to add a dummy pattern to a conductive pattern such as a metal wiring pattern formed on a semiconductor substrate, in order to planarize a dielectric layer covering the conductive pattern.  
           [0003]    2. Description of the Related Art  
           [0004]    The deposition of a layer of dielectric material to cover a conductive pattern on a semiconductor substrate is a common step in the fabrication of semiconductor devices. This step is often carried out by chemical vapor deposition (CVD).  
           [0005]    In a semiconductor device having a multilayer wiring structure, another conductive pattern is formed on the dielectric layer as an upper wiring layer. Before this conductive pattern is formed, the surface of the dielectric layer is planarized by, for example, chemical-mechanical polishing (CMP). CMP produces a flat surface provided the conductive pattern buried within the dielectric layer has a substantially even density.  
           [0006]    It is not easy, however, to design a semiconductor device so that the conductive pattern formed on the substrate has an even density, and if density differences exist, the surface of the polished dielectric layer will show global height differences between areas of high pattern density and areas of low pattern density. These global height differences lead to reduced precision when photolithography is used to form the upper wiring layer on the dielectric layer.  
           [0007]    A known way to reduce global height differences is to add dummy patterns to the low-density areas, to increase the pattern density in these areas. Conventionally, the circuit designer uses visual estimation to decide where to place dummy patterns.  
           [0008]    Estimating by eye where it is necessary to place dummy patterns, however, is a method that depends greatly on the designer&#39;s judgment. It may happen, for example, that although the actual density of the conductive pattern in a certain area is comparatively high, the designer perceives the density as low and decides to add a dummy pattern to the area. The pattern density in the area is then further increased, and in the device as a whole, global height differences are aggravated instead of being reduced.  
           [0009]    In addition, each designer&#39;s judgment differs, and no two designers will decide to form dummy patterns in the same places, so a suitable reduction of global height differences is difficult to achieve.  
         SUMMARY OF THE INVENTION  
         [0010]    An object of the present invention is to provide a method of deciding where to form dummy patterns that can effectively reduce global height differences, thereby enabling semiconductor devices to be fabricated with higher precision than before.  
           [0011]    The present invention provides a method of fabricating a semiconductor device in which a conductive pattern formed on a semiconductor substrate is covered by a dielectric layer, and a dummy pattern is added to the conductive pattern so that the dielectric layer can be more flatly planarized. To decide whether to form a dummy pattern in a given region on the semiconductor substrate, the proportion of a prescribed region, including the given region, that is covered by the conductive pattern is calculated, and the decision is based on the calculated proportion (the conductive pattern density). After the conductive pattern and dummy pattern have been formed, the dielectric layer is deposited and planarized by chemical-mechanical polishing. The conductive pattern typically projects above the semiconductor substrate and is electrically connected to circuit elements formed in the semiconductor substrate, while the dummy pattern, which also projects above the semiconductor substrate, is electrically disconnected from the circuit elements.  
           [0012]    According to the invented method, the dummy pattern is formed according to a fixed rule, without relying on a designer&#39;s judgment. For example, the proportion of the prescribed region covered by conductive pattern may be compared with a predetermined threshold, a dummy pattern being added if the density is equal to or less than the threshold value. Since a fixed rule is followed, an appropriate combined pattern density is consistently obtained, so that when the dielectric layer is planarized, global height differences are consistently reduced.  
           [0013]    The semiconductor substrate may be one part of a semiconductor wafer, and may be partitioned into square or rectangular sections, the given region being one of the square or rectangular sections and the prescribed region comprising one or more of the square or rectangular sections. If composed of two or more of the square or rectangular sections, the prescribed region itself may have a square or rectangular shape.  
           [0014]    The decision as to whether to form the dummy pattern may be based on an adjusted proportion different from the actual proportion of the prescribed region covered by the conductive pattern. The adjustment may be made to allow for a difference between the area of the conductive pattern and the area of the raised portions of the dielectric layer formed above the conductive pattern. For example, if a parallel-plate type of plasma CVD apparatus is used to deposit the dielectric layer, the raised portions of the dielectric layer are larger than the conductive pattern; the adjusted proportion then preferably exceeds the actual proportion. If a high-density plasma CVD apparatus is used, the raised portions of the dielectric layer are smaller than the conductive pattern, and the adjusted proportion is preferably less than the actual proportion.  
           [0015]    The dimensions of the dummy pattern may be varied according to proportion of the prescribed region covered by the conductive pattern. For example, the dummy pattern dimensions may be increased as the proportion of the prescribed region covered by the conductive pattern decreases. In particular, the dimensions may be varied so that the sum of the dummy pattern density in the given region and the conductive pattern density in the prescribed region exceeds a predetermined threshold.  
           [0016]    The present invention also provides a method of deciding whether to form a dummy pattern in a given region on a semiconductor substrate. The ratio of the area of the conductive pattern in the prescribed region to the area of a prescribed region including the given region is calculated, and the dummy pattern is formed if the ratio is less than a predetermined threshold. The calculated area of the conductive pattern may differ from the actual area. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0017]    In the attached drawings:  
         [0018]    [0018]FIG. 1 is a plan view of a semiconductor substrate partitioned into sections according to a first embodiment of the invention;  
         [0019]    [0019]FIG. 2 is a side view of a semiconductor device having a dielectric layer formed without a dummy pattern;  
         [0020]    [0020]FIG. 3 is a sectional view of a semiconductor device having a dielectric layer formed with a dummy pattern as in the first embodiment;  
         [0021]    [0021]FIG. 4 is a plan view, similar to FIG. 1, of a semiconductor substrate, illustrating a method of calculating a pattern density according to a second embodiment of the invention;  
         [0022]    [0022]FIG. 5 is a side view of a semiconductor device with a dielectric layer formed by use of a parallel-plate type of plasma CVD apparatus;  
         [0023]    [0023]FIG. 6 is a side view of a semiconductor device with a dielectric layer formed by use of a high-density plasma CVD apparatus;  
         [0024]    [0024]FIG. 7 is a plan view of a conductive pattern illustrating a sizing adjustment made according to a third embodiment of the invention; and  
         [0025]    [0025]FIG. 8 is a table of dummy pattern dimensions in a fourth embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0026]    Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.  
         [0027]    In a first embodiment of the invented method of fabricating a semiconductor device, a semiconductor wafer is divided by grid lines into a plurality of chip areas, and a separate semiconductor device is formed in each chip area. FIG. 1 shows one chip area  10   a  and its surrounding grid lines  10   b  on the semiconductor wafer  10 .  
         [0028]    [0028]FIG. 2 illustrates the deposition of a dielectric layer  12  to cover a conductive pattern  11  such as a well-known type of metal wiring pattern which is formed in each chip area  10   a  on the semiconductor wafer  10 ; as noted earlier, the deposition of such a dielectric layer  12  is a common step in the fabrication of semiconductor devices. The conductive pattern  11  projects above the chip area  10   a  and is electrically connected to circuit elements formed in the semiconductor substrate. The dielectric layer  12  may be deposited by a parallel-plate type of plasma CVD apparatus, for example, or a high-density plasma CVD apparatus. In either case, raised portions  12   a  of the dielectric layer  12  are formed above the conductive pattern  11 .  
         [0029]    When sparse areas (I) in which the density of the conductive pattern  11  is comparatively low and dense areas (II) in which the density of the conductive pattern  11  is comparatively high coexist on the chip area  10   a , the tops of raised portions  12   a  have different shapes in the sparse areas than in the dense areas. In the dense areas (II) , the cross sections of the tops of the raised portions  12   a  have a comparatively flat profile; in the sparse areas (I), these have a more steeply varying profile, as shown in FIG. 2.  
         [0030]    The dielectric layer  12  is planarized by a CMP apparatus that pushes a rotating pad against the tops of the raised portions  12   a . The pad is formed from an elastic material such as foam polyurethane and has a flat polishing surface. The polishing action removes the raised portions  12   a  and some of the underlying dielectric material, down to line  12   p,  for example. Since the cross section of the tops of the raised portions  12   a  is steeper in the sparse areas (I) than in the dense areas (II), the polishing pressure of the pad tends to be concentrated more intensely on the tops of the raised portions  12   a  in the sparse areas. The dielectric layer is therefore polished more rapidly in the sparse areas than that in the dense areas, and this yields a global height difference  12   b  in the surface of the polished dielectric layer  12 .  
         [0031]    A known way to reduce the global height difference  12   b  is, as shown in FIG. 3, to add dummy patterns  13  projecting above the substrate area left uncovered by the conductive pattern  11  on the chip area  10   a . A dummy pattern  13  is similar to the conductive pattern  11  described above, but is not electrically connected to the circuit elements formed on the chip area  10   a . The dummy patterns  13  may be designed after the conductive pattern that is to be used as interconnection wiring has been designed, for example. In the following description, all of the dummy patterns  13 , or all of the dummy patterns  13  in a given region, will sometimes be referred to collectively as a single dummy pattern.  
         [0032]    In the first embodiment of the invented method, when the dummy pattern is designed, as shown in FIG. 1, the entire surface of the semiconductor wafer  10 , including a plurality of chip areas  10   a , is divided into square or rectangular sections. In the following description, the semiconductor wafer  10  is partitioned by grid lines that divide each chip area, e.g., the chip area  10   a  in FIG. 1, into square sections  14  measuring one hundred micrometers (100 μm) on a side.  
         [0033]    Needless to say, the invention is not limited to this dimension. The sections may have any suitable size, provided each chip area  10   a  is divided into a plurality of sections.  
         [0034]    In the first embodiment, each section  14  is treated as both a given region and a prescribed region. Dummy patterns  13  are added on a section-by-section basis, according to the ratio of the area of the conductive pattern  11  in each section  14  to the area of the section  14  itself. This ratio, which is equal to the density of the conductive pattern  11  in the section  14 , is calculated when the conductive pattern is designed.  
         [0035]    In the first embodiment, whether to form a dummy pattern  13  or not in a given section  14  is determined according to a density threshold of, for example, twenty-five percent (25%). If the calculated value of the pattern density is equal to or less than 25%, the section  14  is regarded as a sparse area in which a dummy pattern  13  needs to be formed. If the value of the pattern density is greater than the 25% threshold (if the pattern density is 50%, for example), the section  14  is regarded as a dense area in which it is not necessary to form a dummy pattern  13 . After this decision has been made, a suitable dummy pattern  13  is laid out if the result of the decision is that a dummy pattern is needed.  
         [0036]    The dummy pattern can be laid out by, for example, simulation on a computer. In the simulation process, a dummy pattern model or template is superposed on the section  14 , and the dummy pattern layout is copied from the template into the areas not overlapping the conductive pattern  11 . In plan view, the template comprises, for example, dummy squares measuring two micrometers (2 μm) on a side, separated from one another by equal intervals of 2 μm. When the dummy pattern is laid out, if necessary, this simulation can be performed for each section  14  of the chip area  10   a , thereby determining the layout of the dummy pattern  13  in the entire chip area  10   a.    
         [0037]    After that, the conductive pattern  11  and the dummy pattern  13  are formed simultaneously on the semiconductor wafer  10 , in each chip area  10   a , by well-known photolithographic techniques, using a photo-resist mask that defines both the conductive pattern  11  and the dummy pattern  13 . After the conductive pattern  11  and the dummy pattern  13  are formed, CVD apparatus is used to deposit the dielectric layer  12  on the semiconductor wafer  10  to cover the conductive pattern  11  and dummy pattern  13 , and CMP apparatus is used to planarize the dielectric layer.  
         [0038]    In the invented method, since dummy patterns  13  are formed only in areas which are determined by strict criteria to be sparse, the density difference between the sparse areas (I) and the dense areas (II) is reduced, and since the addition of a dummy pattern increases the pattern density in the sparse areas, the tops of the raised portions  12   a  of the dielectric layer  12  in the sparse areas are flatter than they would be without dummy pattern formation. As a result, and the global height difference  12   b ′ left in FIG. 3 after CMP planarization of the dielectric layer is smaller than the global height difference  12   b  in FIG. 2.  
         [0039]    In the first embodiment of the invented method, the dummy pattern  13  is added according to a simple and direct rule, by deciding whether to form a dummy pattern  13  together with the conductive pattern  11  in each section  14  of the chip area  10   a  according to the density of the conductive pattern  11  in the section  14 . The decision is made according to a density threshold, without relying on a designer&#39;s judgment. This prevents the dummy pattern  13  from being formed inappropriately in dense parts (II) of the chip area  10   a . When the dielectric layer  12  covering the conductive pattern  11  and the dummy pattern  13  is planarized, global height differences are consistently reduced.  
         [0040]    In a second embodiment of the invented method of fabricating a semiconductor device, whether to form a dummy pattern  13  in a given section  14  of the chip area  10   a  is determined by finding the density of the conductive pattern  11  in a prescribed region  14 a that includes a plurality of sections surrounding the given section  14 , as shown in FIG. 4.  
         [0041]    The prescribed region  14   a  is a square measuring four thousand seven hundred micrometers (4700 μm) on a side, centered on the given section  14  as illustrated. The size of the square may be varied according to the type of CMP apparatus used for planarization and the polishing conditions, such as the material of the polishing pad and its rotational speed. When the given section  14  is located near the boundary of a chip area  10   a  on the semiconductor wafer  10 , the prescribed region  14   a  may overlap the boundary, so that the prescribed region  14   a  includes part of the adjacent chip area on the semiconductor wafer  10 .  
         [0042]    In the second embodiment of the invented method, for each section  14  of the chip area  10   a , the ratio of the area of the conductive pattern  11  in the prescribed region  14   a  surrounding the section  14  to the area of the prescribed region  14   a  is calculated. That is, the density of the conductive pattern  11  in the prescribed region  14   a  is obtained to decide whether to form a dummy pattern  13  in the section  14 . The decision is thus based on the local density of the conductive pattern  11  in a locality that surrounds and is centered on the given section  14  for which the decision is being made, by comparing the local pattern density with a threshold.  
         [0043]    The same threshold can be used as in the first embodiment, (e.g., 25%). If the result of the comparison is that the local pattern density is equal to or less than the threshold, a dummy pattern  13  is laid out in the section  14  located at the center of the prescribed region  14   a . If the local pattern density is greater than the threshold, no dummy pattern  13  is laid out in the section  14 .  
         [0044]    After the conductive pattern  11  and, where necessary, the dummy pattern  13  have been formed, a dielectric layer  12  is deposited covering them, and the dielectric layer  12  is planarized by use of a CMP apparatus in the same way as in the first embodiment.  
         [0045]    In the second embodiment of the invented method, since whether to form a dummy pattern  13  is determined for each section  14  of the chip area  10   a  according to the local pattern density in a prescribed region surrounding the section  14 , the decision is more accurate than in the first embodiment, because it takes account of density interactions between the section  14  and the surrounding area.  
         [0046]    In a third embodiment of the invented method of fabricating a semiconductor device, the local pattern density in a prescribed region  14   a  that surrounds each section  14  of the chip area  10   a  is used as in the second embodiment, as shown in FIG. 4, in order to decide whether to form a dummy pattern  13  in the prescribed region  14 , but the local pattern density is calculated from adjusted dimensions of the conductive pattern.  
         [0047]    When a dummy pattern is designed as described in the first and second embodiments, the pattern density or local pattern density is calculated from pattern dimensions that correspond to the actual dimensions of the top of the conductive pattern  11 .  
         [0048]    When CVD apparatus is used to deposit the dielectric layer  12 , the cross-sectional shape of the raised portions  12   a  formed where the dielectric layer  12  covers the conductive pattern  11  has different features depending on the type of CVD apparatus used.  
         [0049]    If the dielectric layer  12  is deposited by use of a parallel-plate type of plasma CVD apparatus, for example, the cross section of the raised portion  12   a  usually has a top part  12   a ′ that is wider than the top part  11   a  of the conductive pattern  11 , as seen in FIG. 5. The area of the top part  12   a ′ of the raised portion  12   a , that is, the area of contact between the raised portion  12   a  of the dielectric layer  12  and the polishing pad of the CMP apparatus is, therefore, actually larger than the area of the top part  11   a  of the conductive pattern  11 .  
         [0050]    If the dielectric layer  12  is deposited by use of a high-density plasma CVD apparatus, in the cross section of the raised portion  12   a  of the dielectric layer  12 , the top part  12   a ′ is narrower than the top part  11   a  of the conductive pattern  11 , as shown in FIG. 6, and the area of the top part of the raised portion  12   a  is actually smaller than that of the conductive pattern  11 .  
         [0051]    In the third embodiment of the invented method, when the area of the top of the raised portion  12   a  of the dielectric layer  12  differs from the area of the top of the conductive pattern  11  in this way, before the local pattern density of the conductive pattern  11  is calculated, the area of the conductive pattern  11  is adjusted to reduce the difference. That is, a sizing adjustment is performed.  
         [0052]    If a parallel-plate type of plasma CVD apparatus is used to deposit the dielectric layer  12 , the sizing adjustment is performed by plotting an imaginary enlarged periphery around the conductive pattern  11  that is to be formed as an interconnection wiring pattern, as shown in FIG. 7, in order to increase the calculated area of the conductive pattern  11  in the section  14   a  to that of the top part  12   a ′ of the raised portion  12   a  of the dielectric layer  12  in the prescribed region  14   a . The amount (Δx) by which the periphery is enlarged is, for example, +0.40 μm.  
         [0053]    If a high-density plasma CVD apparatus is used for deposition of the dielectric layer  12 , as described above, since the area of the top part  12   a ′ of the raised portion  12   a  of the dielectric layer  12  is smaller than the area of the top part  11   a  of the conductive pattern  11 , a negative value may be used for the sizing adjustment dimension.  
         [0054]    The amount (Δx) is +0.40 μm in FIG. 7, but of course the invention is not limited to this dimension. The amount may have any suitable size, according to the cross-sectional shape and area of the raised portion  12   a  of the deposited dielectric layer  12 .  
         [0055]    In each given section  14  of the chip area  10   a , the local pattern density in the prescribed region  14   a  is calculated according to the enlarged or reduced conductive pattern  11 ′ resulting from the sizing adjustment, and whether to form a dummy pattern in the given section  14  is determined according to the local pattern density obtained in this way. After that, the dielectric layer  12  is deposited and planarized as in the second embodiment.  
         [0056]    Since the sizing adjustment is performed according to the cross-sectional shape characteristics of the dielectric layer  12  to be deposited, when the local pattern density is calculated it reflects the density of the tops of the raised portions  12   a  of the dielectric layer  12 , that is, the density of the parts of the dielectric layer  12  that will be attacked by the polishing pad during planarization. This is a more rational criterion than the density of the conductive pattern  11 , so global height differences can be reduced still further.  
         [0057]    In the third embodiment, as in the preceding embodiments, whether to form the dummy pattern  13  is determined according to a density threshold in each section  14  of the substrate, without relying on a designer&#39;s judgment. Moreover, since the local pattern density used in the decision is obtained by taking account of the cross-sectional shape of the raised portion  12   a  of the dielectric layer  12  that will be formed by the particular type of CVD apparatus that will be used, the global height differences can be reduced with a high degree of accuracy.  
         [0058]    In a fourth embodiment of the invented method of fabricating a semiconductor device, when dummy patterns  13  are laid out on the chip area  10   a , the plan-view dimensions of the dummy patterns  13  and the spaces between them are determined according to the local pattern density, which is obtained as described in the third embodiment.  
         [0059]    In the fourth embodiment, the threshold value is 40%. A dummy pattern  13  is laid out in the section  14  located at the center of any prescribed region  14   a  in which the calculated local pattern density is equal to or less than 40%. The dummy pattern  13  comprises squares having dimensions and spacing that depend on the local pattern density as shown in the table in FIG. 8. In this table, although the size of the dummy squares varies according to the local pattern density, the number of dummy squares in a given region does not vary, since the sum of the width of the squares and the space between the squares is always 4 μm (one square is formed every 4 μm).  
         [0060]    In the fourth embodiment, as shown in FIG. 8, when the calculated local pattern density is greater than 30% but equal to or less than 40%, the dummy pattern  13  consists of squares measuring 2 μm on a side, spaced at equal intervals of 2 μm. The density of the dummy pattern  13  is thus 25%. When this density is added to the local pattern density (the density of the conductive pattern  11  in the prescribed region  14   a ), the sum is greater than the 40% threshold value.  
         [0061]    When the local pattern density is greater than 20% but equal to or less than 30%, the dummy pattern  13  consists of squares measuring 2.5 μm on a side, spaced at equal intervals of 1.5 μm. The density of the dummy pattern  13  is then 39%, and when this density is added to the local pattern density, the sum is again greater than the 40% threshold value.  
         [0062]    When the local pattern density is equal to or less than 20%, the dummy pattern  13  consists of squares measuring 3 μm on a side, spaced at equal intervals of 1 μm. The density of the dummy pattern  13  is now 56%, which is greater than the 40% threshold value even without addition of the local pattern density.  
         [0063]    Thus in the fourth embodiment, the lower the local pattern density is in the prescribed region  14   a  surrounding a section  14 , the greater the dimensions of the dummy pattern  13  laid out in the section  14  become. Regardless of how low the calculated local pattern density is, sufficient dummy pattern  13  is added to make the sum of the dummy pattern density and the local density of the conductive pattern  11  exceed the 40% threshold value. Variations in the combined density of the conductive pattern  11  and dummy pattern  13  are therefore reduced, as compared with the preceding embodiments, leading to a still greater reduction of global height differences.  
         [0064]    Furthermore, since the dimensions of the dummy pattern squares are varied without varying the number of squares, the dummy pattern density can be increased efficiently, without increasing the number of dummy pattern squares that have to be laid out, or the amount of memory space devoted to the dummy pattern layout in the design file.  
         [0065]    The four embodiments described above can be modified in numerous ways. The dimensions and threshold values given above can be modified, for example. In the third embodiment, the calculated pattern density can be adjusted by a mathematical formula, without performing a sizing adjustment on the periphery of the conductive pattern. In the fourth embodiment, the dummy pattern dimensions can be varied continuously according to the local pattern density, instead of being varied in steps.  
         [0066]    In a semiconductor device with multiple dielectric layers covering respective conductive pattern layers, the invented method can be applied to the formation of dummy patterns in each of the conductive pattern layers.  
         [0067]    Those skilled in the art will recognize that further variations are possible within the scope claimed below.