Abstract:
A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate having the line patterns. A pad contact hole is located between the line patterns within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening defined by the barrier layer.

Description:
This U.S. nonprovisional patent application claims priority from Korean Patent Application No. 2003-6023, filed on Jan. 29, 2003, the contents of which are incorporated herein by reference in their entirety. 
   BACKGROUND OF INVENTION 
   1. Field of the Invention 
   The present invention relates to a semiconductor device and fabrication method thereof, and more particularly, to a semiconductor device having a landing pad and a fabrication method thereof. 
   2. Description of Related Art 
   Generally, semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices include a DRAM (Dynamic RAM) and a SRAM (Static RAM). Generally, the DRAM has an integration density higher than the SRAM, which is the reason that the DRAM has been widely used as a memory device for a computer. A unit cell on the cell array region of the DRAM includes a single cell capacitor and a single access transistor. 
   In response to the increase in the integration density of the DRAM, a DRAM cell having a structural configuration comprising a capacitor over bit line (COB) has been widely employed in order to increase the capacitance of a DRAM capacitor. In this structural configuration, more specifically, the cell capacitor is placed above the bit line. Therefore, the more the integration density of the DRAM is increased, the more difficult it is to form a storage node contact hole for connecting the storage node (lower electrode) of the cell capacitor to the source region of the access transistor. 
   Recently, in order to increase the ease of formation of the storage node contact hole in a semiconductor fabrication process, a landing pad has been widely employed. The landing pad is interposed between the storage node and the source region. 
     FIGS. 1 through 4  illustrate a method of forming DRAM cells having landing pads according to the conventional prior art. 
   Referring to  FIG. 1 , a trench isolation layer  3  is formed on an active region  3   a  of a semiconductor substrate  1 . A gate insulating layer  5  is also formed on the active region  3   a . A conductive layer and a capping layer are sequentially formed on the overall surface of the semiconductor substrate having a gate insulating layer  5 . The capping layer and the conductive layer are etched to form a plurality of word line patterns  10  across the upper part of the active region  3   a . Accordingly, each of the word lines patterns  10  includes a word line (gate electrode)  7  and a capping layer pattern  9  stacked thereon. Impurity ions are implanted in the active region  3   a  of the semiconductor substrate  1  using the word line pattern  10  and the trench isolation layer  3  as ion implantation masks to form a first and a second source region  11   s ′,  11   s ″ together with one common drain region  11   d . Spacers  13  are formed on the side walls of the word line patterns  10 . The capping layer patterns  9  and the spacers  13  are formed of a silicon nitride layer. 
   Referring to  FIG. 2 , an interlayer insulating layer  15  is formed on the overall surface of the semiconductor substrate. Then, a bit line pad contact hole  17   d , and first and second storage node pad contact holes  17   s ′,  17   s ″, are formed in the interlayer insulating layer  15  to expose the common drain region  11   d  and the first and the second source regions  11   s ′,  11   s ″, respectively. The interlayer insulating layer  15  is generally formed of a silicon oxide layer. During the formation of the pad contact holes  17   d ,  17   s ′,  17   s ″, the capping layer pattern  9  and the spacers  13  function as an etching stop layer. At this time, separation layers  15   a , which are formed from the interlayer insulating layer  15 , are formed between the pad contact holes  17   d ,  17   s ′,  17   s″.    
   Referring to  FIG. 3 , in order to remove the polymer and the natural oxide layer remaining inside the pad contact holes  17   d ,  17   s ′,  17   s ″, an oxide layer etching solution is applied on the semiconductor substrate  1  to clean the inside portions of the pad contact holes  17   d ,  17   s ′,  17   s ″. As a result, the width of the separation layer  15   a  is reduced. In the event that the cleaning process is performed for an extended time, or for several times, a through hole  15   a ″ may be formed in a predetermined region of the separation layers  15   a , or alternatively, the separation layers  15   a  can be removed. Then, a conductive layer  19  is formed on the overall surface of the semiconductor substrate having the through hole  15   a″.    
   Referring to  FIG. 4 , the conductive layer  19  is planarized to expose the upper surface of the interlayer insulating layer  15 , and to form a bit line pad  19   d , a first storage node pad  19   s ′ and a second storage node pad  19   s ″. The bit line pad  19   d , the first storage node pad  19   s ′ and the second storage node pad  19   s ″ are called “landing pads”. If the cleaning process is performed severely, the landing pads  19   d ,  19   s ′,  19   s ″ are connected to one another as shown in FIG.  4 . As described above, it has been difficult to perform the cleaning process of the prior art sufficiently enough to remove the polymer and the natural oxide layer before forming the landing pads. That is, since the severity of the cleaning process is reduced, it is difficult to improve the contact resistance of each of the landing pads. 
   On the other hand, U.S. Pat. No. 6,117,757 to Chuan-fu Wang and Benjamin Szu-Min Lin (“U.S. &#39;757”) is related to a method of forming landing pads for bit line and node contact. As set forth in U.S. &#39;757, gate patterns having a multi-layer are formed on the semiconductor substrate, and first spacers are formed on the side walls of the gate patterns. Next, a first dielectric layer is deposited on the semiconductor substrate having the gate patterns and the first spacers. Contact openings are then formed in the first dielectric layer using a self-aligned method to expose the semiconductor substrate. Next, a second dielectric layer is conformally formed on the overall surface of the semiconductor substrate, and the second dielectric layer is etched back to form second spacers on the side walls of the contact openings. Subsequently, a conductive layer is formed on the overall surface of the semiconductor substrate and patterned to expose the upper portions of the second spacers and to form bit lines and landing pads. 
   However, with the pitch of the gate patterns being fixed, the formation of the second spacers causes the width of the contact opening to be narrowed. Thus, the contact resistance is increased between the bit lines and the semiconductor substrate, together with between the landing pads and the semiconductor substrate. Furthermore, the method of U.S. &#39;757 may cause a short circuit between the bit lines and the landing pads as the design rule of the semiconductor device is further reduced. 
   SUMMARY OF THE INVENTION 
   According to one embodiment of the present invention, a semiconductor device comprises a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a line capping layer pattern stacked thereon. A material layer covers the upper surface of the semiconductor substrate between adjacent line patterns. A pad contact hole is located between the line patterns along within a region of the material layer. The pad contact hole includes a lower opening between the line patterns and an upper opening located above the lower opening. A barrier layer is formed on a side wall defining the upper opening. A landing pad substantially fills the lower opening and the upper opening and defined by the barrier layer. The semiconductor device can further include line spacers which are formed on the side walls of the line patterns. Preferably, the line patterns and the line spacers are word lines and word line spacers, the line patterns are bit lines, and the line spacers are bit line spacers. 
   The material layer preferably includes a separation insulating layer and a separation etching stop layer stacked thereon. Moreover, the material layer can include an oxide layer and a nitride layer stacked thereon. 
   Furthermore, each respective barrier layer and line capping layer pattern is preferably a nitride layer. More preferably, the barrier layers, the line spacers and the capping layer patterns are nitride layers. 
   In a preferred method of manufacturing a semiconductor device of the present invention, a plurality of adjacent line patterns are formed on the semiconductor substrate. Line spacers are then formed on the side walls of the line patterns, and a material layer is formed on the upper surface of the semiconductor substrate between the adjacent line patterns. Next, a predetermined portion of the material layer is etched to form an upper opening in the material layer between the line patterns, and a barrier layer is formed on a side wall defining the upper opening. Then, the material layer is etched below the upper opening defined by the barrier layer to form a lower opening within the material layer exposing the line spacers between the line patterns. The subject landing pad can then be formed by filling the upper opening and the lower opening, respectively. 
   In the method of this invention, the formation of the line patterns can comprise sequentially forming a conductive layer and a capping insulating layer on the semiconductor substrate, and sequentially patterning the capping insulating layer and the conductive layer. The material layer can also be formed of a separation insulating layer and a separation etching stop layer stacked thereon. This separation insulating layer is preferably formed of an oxide layer. Moreover, the barrier layer can be formed of an insulating layer. Preferably, if a natural oxide layer and a polymer layer are formed and are present in the lower opening, they are preferably removed prior to forming the landing pad. In the method herein the upper opening can be formed so that it&#39;s bottom surface no higher than the upper surface of each of the line patterns. 
   A preferred method of manufacturing a DRAM cell array region can also be provided. In this method a predetermined region of the semiconductor substrate is filled with a trench isolation layer to form an active region. Then, a plurality of first line patterns are formed on an upper portion of the active region, and a plurality of second line patterns, substantially simultaneously with the formation of the first line patterns, are formed on an upper portion of the trench isolation layer adjacent to at least one side of the active region. At least one second line pattern is formed in parallel with the first line pattern and on a side opposite to the first line pattern. Then, line spacers are formed on side walls of the first and second line patterns, and a material layer is formed covering the upper surface of the semiconductor substrate. A portion of the material layer is then etched to form an upper bit line opening located in a first region between the first line patterns, a first upper storage opening located in a second region between the first and the second line patterns, and a second upper storage opening located in a third region between the first and the second line patterns, respectively. Barrier layers are formed on the side walls defining the upper bit line opening, the first upper storage opening, and the second upper storage opening. Etching of the material layer is provided below the upper bit line opening, the first upper storage opening, and the second upper storage opening defined by the barrier layers, to form respectively a lower bit line opening, a first lower storage opening, and a second lower storage opening, by penetrating the first region, the second region, and the third region to expose the first and second line patterns. A bit line landing pad, a first storage landing pad, and a second storage landing pad are formed by filling the lower and upper bit line openings, the first lower and upper storage openings, and the second lower and upper storage openings, respectively. In the above-described DRAM manufacturing method, the upper bit line opening, the first upper storage opening, and the second upper storage opening can be configured so that their respective bottom surfaces are no higher than the upper surface of each of the first and second line patterns. The material layer can include an oxide layer having a nitride layer stacked thereon, each of the first and second line patterns can include a line having a capping layer pattern stacked thereon, and the barrier layers, the line spacers and the capping layer patterns can be nitride layers. 
   This invention also relates to a DRAM cell array region. The DRAM cell array region comprises a semiconductor substrate, and a predetermined region of the semiconductor substrate filled with a trench isolation layer to form an active region. A plurality of first line patterns are located on an upper portion of the active region. Moreover, a plurality of second line patterns are formed on an upper portion of the trench isolation layer adjacent to at least one side of the active region. At least one second line pattern is formed in parallel with the first line pattern and on a side opposite to the first line pattern. Line spacers are formed on side walls of the first and second line patterns. A material layer is provided covering the upper surface of the semiconductor substrate. 
   An upper bit line opening is located in a first region between the first line patterns, a first upper storage opening located in a second region between the first and the second line patterns, and a second upper storage opening located in a third region between the first and the second line patterns. Barrier layers are typically formed on the side walls defining the upper bit line opening, the first upper storage opening, and the second upper storage opening. A lower bit line opening, a first lower storage opening, and a second lower storage opening are formed which penetrate the first region, the second region, and the third region to expose the first and second line patterns. A bit line landing pad, a first storage landing pad, and a second storage landing pad fill the lower and upper bit line openings, the first lower and upper storage openings, and the second lower and upper storage openings respectively. 
   A DRAM cell array region can be produced in which the material layer includes an oxide layer having a nitride layer stacked thereon. It can also be fabricated so that each of the first and second line patterns include a line having a capping layer pattern stacked thereon. Preferably, the barrier layers, the line spacers and the capping layer patterns are nitride layers. In a further preferred form of this invention, the upper bit line opening, the first upper storage opening, and the second upper storage opening are formed so that their respective bottom surfaces are no higher than the upper surface of each of the first and second line patterns. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Exemplary embodiments of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows when taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which: 
       FIGS. 1  to  4  are schematic sectional views to illustrate a method of forming DRAM cells having landing pads according to the prior art; 
       FIG. 5  is a schematic plane view of a DRAM cell array region according to one embodiment of the present invention; and 
       FIGS. 6  to  12  are sectional views to illustrate the processes of a fabrication method of a DRAM cell array region taken along line I-I′ of  FIG. 5  according to another embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
   Reference will now be made in detail to exemplary embodiments of a DRAM cell array region and fabrication method of the present invention, which are illustrated in the accompanying drawings. 
     FIG. 5  is a schematic plan view of a part of the DRAM cell array region according to the present invention, and  FIG. 6  is a sectional view taken along by line I-I′ of FIG.  5 . Referring to  FIGS. 5 and 6 , a trench isolation layer  102  is formed on a predetermined region of a semiconductor substrate  100 . The trench isolation layer  102  defines an active region  101 . First through fourth respective parallel line patterns  115   a ,  115   b ,  115   c ,  115   d  are placed across the active region  101 . The first and the second line patterns  115   a ,  115   b  extend over the upper part of the active region  101 , and the third and the fourth line patterns  115   c ,  115   d  are located on the trench isolation layer  102  adjacent to the active region  101 . The third line pattern  115   c  is disposed adjacent to the first line pattern  115   a , and on the opposite side of first line pattern  115   a  as second line pattern  115   b . Further, the fourth line pattern  115   d  is located adjacent to the second line pattern  115   b , and on the opposite side of second line pattern  115   b  as first line pattern  115   a.    
   N-type regions  116  are disposed in the semiconductor substrate  100  having the first through fourth line patterns  115   a ,  115   b ,  115   c ,  115   d , each of N-type region  116  overlapping the edge of each of the first through fourth line patterns  115 ,  115   b ,  115   c ,  115   d . Line spacers  112  are disposed on the side walls of the first through fourth line patterns  115   a ,  115   b ,  115   c ,  115   d . Next, a material layer  126 ′ is formed on the semiconductor substrate  100  including the line spacers  112 . The material layer  126 ′ comprises the separation insulating layer  118  and the separation etching stop layer  121 . 
   Pad contact holes  137  are introduced in predetermined regions between the first through the fourth line patterns  115   a ,  115   b ,  115   c ,  115   d  (corresponding to the first to the third regions B, A, C of the material layer  126 ′). The pad contact holes  137  include a bit line pad contact hole  137   b  having a lower bit line opening  135   b  and an upper bit line opening  130   b  in the first region B, a first storage pad contact hole  137   a  having a first lower storage opening  135   a  and a first upper storage opening  130   a  in the second region A, and a second storage pad contact hole  137   c  having a second lower storage opening  135   c  and a second upper storage opening  130   c  in the third region C. There are barrier layers  133   a  covering the side walls of the upper bit line opening  130   b , the first upper storage opening  130   a , and the second upper storage opening  130   c.    
   The bit line pad contact hole  137   b , the first storage pad contact hole  137   a , and the second storage pad contact hole  137   c  have a bit line landing pad  138   b , a first storage landing pad  138   a , and a storage landing pad  138   c , respectively. 
     FIGS. 7  to  12  are sectional views to illustrate a fabrication method of a DRAM cell array region taken along line I-I′ of  FIG. 5  according to one embodiment of the present invention. Referring to  FIGS. 7 and 8 , a semiconductor substrate having the trench isolation layer  102  to define an active region  101  is prepared. A doped polysilicon layer  103 , a WSi layer  106  and a capping insulating layer  109  are formed in sequence on the semiconductor substrate having the active region  101 , as well as on the trench isolation layer  102 . Then, the capping insulating layer  109 , the WSi layer  106  and the doped polysilicon layer  103  in sequence are patterned to form line patterns  115 . The doped polysilicon layer  103  and the WSi layer  106  function as line patterns, and the capping insulating layer  109  functions as capping layer patterns. The capping insulating layer  109  is formed of a nitride layer. The line patterns  115  are separately formed on the semiconductor substrate  100  as shown in  FIG. 5. A  first and a second respective line pattern  115   a ,  115   b  is formed which traverses the upper surface of the active region  101 . A third line pattern  115   c  is formed across the upper surface of a trench isolation layer  102  adjacent to a side of the active region  101 , in parallel with the first line pattern  115   a , and on the opposite side of first line pattern  115   a  as the second line pattern  115   b . A fourth line pattern  115   d  is formed across the upper surface of another trench isolation layer  102 , adjacent to the other side of the active region  101 , in parallel with the second line pattern  115   b , and on the opposite side of second line pattern  115   b  as the first line pattern  115   a . In the embodiment of the present invention, the line patterns  115  are preferably word line patterns. 
   A spacer insulating layer (not shown) is conformally formed on the semiconductor substrate having the line patterns  115 . The spacer insulating layer is preferably formed of a nitride layer. Then, the spacer insulating layer is etched to form line spacers  112  on the side walls of the line patterns  115 . In the embodiment of the present invention, the line spacers  112  are preferably word line spacers. The line patterns  115  and the line spacers  112  may preferably be bit line patterns and bit line spacers. 
   A material layer  126  is formed on the semiconductor substrate having the line patterns  115  and the line spacers  112 . The material layer  126  is formed of a separation insulating layer  118 , a separation etching stop layer  121 , and an interlayer insulating layer  124 , respectively. The separation etching stop layer  121  preferably has an etching selectivity with respect to the separation insulating layer  118 . Preferably, the separation insulating layer  118  is formed of an oxide layer and the separation etching stop layer  121  is formed of a nitride layer. The thickness of the separation insulating layer  118  is preferably formed to be greater than that of the interlayer insulating layer  124 . The separation insulating layer  118  is formed to the thickness sufficient to cover the line patterns  115  and the line spacers  112 , and extends upwardly from the top surface of the line pattern  115 . 
   Referring to  FIG. 9 , a photoresist layer (not shown) is deposited on the semiconductor substrate having the material layer  126  of FIG.  8 . Photoresist patterns are formed on the photoresist layer by using the known photo process to align between the first to the fourth line patterns  115   a ,  115   b ,  115   c ,  115   d  corresponding to the first to the third regions B, A, C. The material layer  126  exposed through the photoresist patterns is partially etched to form upper openings  130 , wherein a predetermined portion of each of the top surfaces of the line patterns  115  is exposed through the upper openings  130 . 
   The upper openings are separately formed as follows: An upper bit line opening  130   b is formed on a predetermined region between the first and the second line patterns  115   a ,  115   b corresponding to the first region B of the material layer  126 . At the same time, a first upper storage opening  130   a  is formed on a predetermined region between the first and the third line patterns  115   a ,  115   c  corresponding to the second region A of the material layer  126 . With the formation of the upper bit line opening  130   b  and the first upper storage opening  130   a , a second upper storage opening  130   c  is formed on a predetermined region between the second and the fourth line patterns  115   b ,  115   d  corresponding to the third region C of the material layer  126 . Further, the upper bit line opening  130   b , the first upper storage opening  130   a , and the second upper storage opening  130   c  are formed to have a bottom surface of the same height or less as the upper surface of each of the line patterns  115   a ,  115   b ,  115   c ,  115   d.    
   Each of the upper openings  130  is separated into an isolation layer  126   a  with a width W which is formed of the material layer  126 , on the top surface of each of the line patterns  115   a - 115   c . At this time, insulating layer patterns  118   a  are formed between the line patterns  115   a - 115   c  under the upper openings  130   a ,  130   b ,  130   c . The insulating layer patterns  118   a  are formed by partially etching the separation insulating layer  118  of FIG.  8 . The insulating layer patterns  118   a  are preferably recessed to a depth L, toward the semiconductor substrate  100 , below the upper surfaces of the line patterns  115   a - 115   c . The purpose of this recessed depth L is to prevent the increase of the contact resistance of each of pad contact holes  137  of  FIG. 5  formed by the sequential etching of the insulating layer patterns  118   a  during the semiconductor formation process. Therefore, the thickness T and the depth L of the insulating layer patterns  118   a  can be measured for the purpose of checking the contact resistances of the pad contact holes  137 . 
   Referring to  FIGS. 10 and 11 , a barrier insulating layer  133  is conformally formed on the surface of the semiconductor substrate having the upper openings  130 . The barrier insulating layer  133  is etched back to form barrier layers  133   a  on the side walls of the respective upper bit line opening, the first upper storage opening, and the second upper storage opening  130   b ,  130   a ,  130   c . Sequentially insulating layer patterns  118   a  are etched to form lower openings  135  between the line patterns  115   a - 115   c  which exposes the semiconductor substrate  100 , and further forms the barrier layers  133   a.    
   The lower openings  135  are formed of a lower bit line opening  135   b , a first lower storage opening  135   a  and a second lower storage opening  135   c . The lower bit line opening  135   b  is formed by etching the insulating layer pattern  118   a  under the upper bit line opening  130   b  to penetrate the region between the first and the second line patterns  115   a ,  115   b . The first lower storage opening  135   a  is formed by etching the insulating layer pattern  118   a  under the first upper storage opening  130   a  to penetrate the region between the first and the third line patterns  115   a ,  115   c . The second lower storage opening  135   c  is formed by etching the insulating layer pattern  118   a  under the second upper storage opening  130   c  to penetrate the region between the second and the fourth line patterns  115   b ,  115   d , along with the formation of the lower bit line opening  135   b  and the first lower storage opening  135   a.    
   Further, the upper openings  130  in  FIG. 9  are separately by a material layer  126  and an isolation layer  126   a  including an interlayer insulating layer  124 . However, after the formation of the lower openings  135   a ,  135   b ,  135   c , the respective upper openings  130   a ,  130   b ,  130   c  are separately by a material layer  126 ′ and an isolation layer  126   a ′ in which the interlayer insulating layer  124  is removed together with the insulating layer pattern  118   a . The separation etching stop layer  121  is a buffer layer for preventing the separation insulating layer  118  from being etched during the formation of the lower openings  135   a ,  135   b ,  135   c . Therefore, the lower openings  135   a ,  135   b ,  135   c  are formed through the self alignment method using the upper openings  130   a ,  130   b ,  130   c  of FIG.  9  and the barrier insulating layers  133  of FIG.  10 . 
   The diameter D 1  of each of the upper openings  130   a ,  130   b ,  130   c  is greater than the diameter D 2  of each of the lower openings  135   a ,  135   b ,  135   c  measured across the line patterns  115   a ,  115   b ,  115   c ,  115   d . And the upper openings  130  are formed to overlap between the line patterns  115 . Preferably, the residue existing between the line spacers  112 , after the formation of the lower openings  135   a ,  135   b ,  135   c , needs to be cleaned in order to reduce the electrical resistance. 
   The reason for recessing the insulating layer pattern  118   a  by the thickness L as shown in  FIG. 9 , is to prevent the residue of the barrier insulating layer  133  from being generated in the junction of the side wall of each of the line spacers  112 , and on the upper surface of each of the insulating layer patterns  118   a  during the formation of the barrier layer  133   a . The residue of the barrier insulating layer  133  can cause the diameter D 2  of each of the lower openings  135   a ,  135   b ,  135   c  to be reduced. 
   Referring to  FIG. 12 , pad contact hole  137  is formed of a bit line pad contact hole, a first storage pad contact hole and a second storage pad contact hole  137   b ,  137   a ,  137   c , respectively, as follows. The bit line pad contact hole  137   b  is formed of the lower bit line opening  135   b  and the upper bit line opening  130   b , between the first and the second line patterns  115   a ,  115   b , which corresponding to the first region B of FIG.  5 . The first storage pad contact hole  137   a  is formed of the first lower storage opening  135   a  and the first upper storage opening  130   a  between the first and the third line patterns  115   a ,  115   c , which corresponds to the second region A of FIG.  5 . With the formation of the bit line pad contact hole  137   b  and the first storage pad contact hole  137   a , respectively, a second storage pad contact hole  137   c  is formed of a second lower storage opening  135   c  and the second upper storage opening  130   c  between the second and the fourth line patterns  115   b ,  115   d , which corresponds to the third region C of FIG.  5 . 
   Further, a doped pad layer (not shown) is formed to a predetermined thickness on the semiconductor substrate having the pad contact holes  137 . The doped pad layer is etched by using the known chemical mechanical polishing method to form landing pads  138   a - 138   c  filling the pad contact holes  137 . 
   The landing pads  138   a - 138   c  comprise a bit line landing pad  138   b , a first storage landing pad  138   a , and a second storage landing pad  138   c  as follows. That is, the bit line landing pad  138   b , the first storage landing pad  138   a , and the second storage landing pad  138   c  fill the bit line pad contact hole  137   b , the first storage pad contact hole  137   a , and the second storage pad contact hole  137   c , respectively. The separation etching stop layer  121  is used as an etching buffer layer. Each of the landing pads  138   a - 138   c  are controlled to be lower than the height of the isolation layer  126   a ′ or the height of the material layer  126 ′. The landing pads  138   a - 138   c  are preferably controlled to be lower than the bottom surface of the separation etching stop layer  121  in order to prevent from making the short circuit between the landing pads  138   a - 138   c.    
   Further, a wet etching process for cleaning the semiconductor substrate  100  is performed between the formation step of the pad contact holes  137  and the deposition step of the pad layer. The wet etching process can remove the by-products and particles generated when etching the insulating layer pattern  118   a  of  FIG. 10 , and a natural oxide layer, etc. generated in the lower openings  135   a ,  135   b ,  135   c . The isolation layer  126   a ′ and/or the material layer  126 ′ may be etched by using a conventional wet etching process. 
   However, the barrier layers  133   a  function as buffer layers during the wet etching process so that the separation etching stop layer  121  and the separation insulating layer  118  are not etched. The use of the barrier layers  133   a  and the separation etching stop layer  121  makes the isolation layer  126   a ′ maintain substantially the same width W as the isolation layer  126   a  of FIG.  9 . 
   As described above, according to the semiconductor device and the cell array region, and the fabrication method thereof of the present invention, the separation etching stop layer along with the barrier layers prevent the separation insulating layer from being etched between the formation step of the pad contact holes and the deposition step of the pad layer. Accordingly, the semiconductor device includes the landing pad free of the short circuit through the barrier layers and the separation etching stop layer. Therefore, the DRAM cell array region having the barrier layers and the separation etching stop layer can maintain the width W uniformly between the pad contact holes, so that the semiconductor device of this invention has the ability to retain the cell data for a much longer time than in conventional semiconductors. As a result, the data retention characteristics of the subject semiconductor device are significantly improved. 
   While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the present invention.