Abstract:
The present invention discloses a capacitor of a semiconductor device and a method for forming the same which has sufficient capacitance for high integration of the semiconductor device. A stack structure of a first capacitor and a second capacitor is formed to be connected to a semiconductor substrate. Here, the first and second capacitors are vertically spaced apart and electrically insulated from each other, and the adjacent capacitors are formed on different layers. Accordingly, sufficient capacitance for high integration of the semiconductor device is obtained to improve reliability of the semiconductor device and achieve high integration thereof.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor device comprising capacitors and a method for forming the same, and in particular to a semiconductor device comprising capacitors and a method for forming the same which provide increased projection area of a cell capacitor ranging from 3F 2  to 12F 2  by forming a multi stack type capacitor.  
           [0003]    2. Description of the Background Art  
           [0004]    One of the important factor in the embodiment of giga level DRAMs is to form a capacitor provides sufficient capacitance for high integration.  
           [0005]    In particular, in the DRAM wherein a unit cell includes a MOS transistor and a capacitor, a capacitance of the capacitor needs to be increased and an area occupied by the capacitor needs to be decreased to achieve high integration.  
           [0006]    Therefore, in order to increase the capacitance of the capacitor which follows the equation (Eo×Er×A)/T (where Eo denotes a vacuum dielectric constant, Er denotes a dielectric constant of a dielectric film, A denotes an area of the capacitor and T denotes a thickness of the dielectric film), a method of increasing a surface area of a storage node which is a lower electrode has been proposed.  
           [0007]    The capacitance required for reading stored information is 25 to 30fF per cell regardless of DRAM generation. However, an area of region allocated for capacitors has been reduced due to increase of an integration density of the DRAM.  
           [0008]    The foregoing problem is in a giga level DRAM region. Researches have been made on structures of the capacitor and development of insulating film materials for increasing the capacitance.  
           [0009]    Factors for determining the capacitance of the DRAM include an area of a capacitor, a dielectric constant of a dielectric material and an equivalent oxide thickness (EOT).  
           [0010]    [0010]FIG. 1 is a layout view illustrating a conventional semiconductor device, wherein a general 5F 2  folded bit line structure DRAM cell is shown as an example. Here, F denotes ts a minimum pitch size.  
           [0011]    5F by 1F rectangular active regions  12  are alternately arranged on a semiconductor substrate  10 . Word lines  14  having a width of 1F are arranged vertical to the active regions  12  at an interval of 1F. Capacitors  16  having a length of 3F are formed at both sides of one active region  12 . Here, the capacitors  16  are electrically connected to the semiconductor substrate  10  through contacts  18 .  
           [0012]    [0012]FIG. 2 is a graph showing accumulated electric charges according to a height of a storage node and an EOT. The graph illustrates the storage node height and the EOT of the capacitor required for obtaining the capacitance of 25 to 30fF per cell when the capacitor of FIG. 1 has a simple stacked structure and F is 0.7 nm. A surface area is calculated in consideration of edge rounding effects in a storage node patterning process of the cell.  
           [0013]    When an aspect ratio of the storage node height is 10, the EOT must at least be about 0.5 nm, and when the aspect ratio is 20, the EOT must at least be 1 nm in order to form the capacitor having a capacitance of 25 fF. It is thus necessary to use a high dielectric constant material.  
           [0014]    However, most of the high dielectric constant materials are difficult to be used in processes.  
           [0015]    In particular, when a metal electrode such as Ru is used as a storage node and a plate electrode when a thin film having a high dielectric constant is used. In such cases, characteristics of the device is deteriorated due to thermal budget.  
           [0016]    In addition, the characteristics of a high dielectric constant material is degraded in subsequent thermal annealing process, or a gap filling property is degraded due to the high aspect ratio.  
         SUMMARY OF THE INVENTION  
         [0017]    Accordingly, it is an object of the present invention to provide a capacitor of a semiconductor device which has sufficient capacitance and occupies small area, by forming adjacent capacitors on different layers without increasing the height of a storage node.  
           [0018]    Another object of the present invention is to provide a method for forming a capacitor of a semiconductor device which has sufficient capacitance for high integration of the semiconductor device without increasing a storage node height.  
           [0019]    In order to achieve the above-described objects of the invention, there is provided a semiconductor device having a folded bit line structure in which a first capacitor and a second capacitor are connected to one active region, wherein the first capacitor and the second capacitor are respectively formed at a different altitude, being electrically isolated from each other.  
           [0020]    In addition, the first and the second capacitors are 5F 2  respectively and overlaps each other by 1F 2 .  
           [0021]    According to another aspect of the invention, a capacitor of a semiconductor device includes: a 5F by 1F rectangular active region; two word lines of 1F, running across one active region; and two capacitors in one active region formed at a different altitude with being electrically isolated from each other, wherein the second capacitors have a size of 5F 2  respectively and overlap by a predetermined size.  
           [0022]    Here, the two capacitors overlap each other by F 2 .  
           [0023]    According to yet another aspect of the invention, a capacitor of a semiconductor device includes: a 5F by 1F rectangular active region; two word lines of 1F, running across one active region; and two 2F by 6F capacitors connected to one active region, wherein the two capacitors are formed at a different altitude with being electrically isolated and overlap by a predetermined width.  
           [0024]    Here, the two capacitors overlap each other by 2F×2F.  
           [0025]    According to yet another aspect of the invention, a method for forming a capacitor of a semiconductor device includes the steps of: forming a device isolation oxide film defining active regions on a semiconductor substrate; forming a first interlayer insulating film on the entire surface of the resulting structure; selectively patterning the first interlayer insulating film to form a first and a second contact plugs contact to the active region; forming a third contact plug contacting the second contact plug; forming a first insulating spacer on the sidewalls of the third contact plug, whereby a first contact hole exposing the first contact plug is generated; forming a first capacitor having a storage node, a dielectric film and a plate electrode in the first contact hole; forming a fourth contact plug connected to the plate electrode of the first capacitor on the resultant structure; forming a second insulating spacer on the sidewalls of the fourth contact plug so that the second insulating spacer covers the exposed surface of the first capacitor, whereby a second contact hole exposing the third contact plug is generated; and forming a second capacitor in the second contact hole.  
           [0026]    In addition, the method further comprises, after forming the first capacitor, a step of forming a second insulating film on the resultant structure to isolate the first capacitor from the second capacitor.  
           [0027]    The principle of the present invention lies in that a multi stacked cell capacitor is provided to increase the capacitance of DRAM. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0028]    The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus-are not limitative of the present invention, wherein:  
         [0029]    [0029]FIG. 1 is a layout view illustrating a conventional semiconductor device;  
         [0030]    [0030]FIG. 2 is a graph showing accumulated charges according to a height of a storage node height and an equivalent oxide thickness;  
         [0031]    [0031]FIG. 3 is a layout view illustrating a semiconductor device in accordance with a first embodiment of the present invention;  
         [0032]    [0032]FIG. 4 a  is a cross-sectional view taken along line A-A of FIG. 3;  
         [0033]    [0033]FIG. 4 b  is a cross-sectional view taken along line B-B of FIG. 3;  
         [0034]    [0034]FIG. 5 is a layout view illustrating a semiconductor device in accordance with a second embodiment of the present invention;  
         [0035]    [0035]FIGS. 6 a  to  6   g  are cross-sectional views illustrating sequential steps of a method for forming a capacitor in accordance with the present invention;  
         [0036]    [0036]FIG. 7 is a cross-sectional view illustrating a semiconductor device in accordance with a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0037]    A capacitor of a semiconductor device and a method for forming the same in accordance with preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.  
         [0038]    [0038]FIG. 3 is a layout view illustrating a semiconductor device in accordance with a first embodiment of the present invention, capacitor having an area of 5F 2  in a folded bit line structure.  
         [0039]    5F by 1F rectangular active regions  22  are arranged on a semiconductor substrate  20  at an interval of 1F. A plurality of word lines  24  are arranged vertical to the active region  22  wherein two word lines cross one active region  22 . Two rectangular shaped capacitors  25  and  26  having a width of 1F and a length of 5F are formed on two different layers in one active region  22 . Here, the capacitors  25  and  26  are electrically connected to the active region  22  through contacts  27  and  28 .  
         [0040]    [0040]FIGS. 4 a  and  4   b  are cross-sectional views illustrating the capacitor, taken along lines A-A and B-B of FIG. 3, wherein a device isolation oxide films and word lines are not shown.  
         [0041]    As shown in FIG. 4 a , a device isolation oxide film  21  defining the active regions on the semiconductor substrate  20  is formed in a shallow trench type. First capacitors  25  having a size of 1×F 2  are formed on a first interlayer insulating film  23  to contact the active region  22  through a contact  27  A second interlayer insulating film  23 - 1  is formed to fill the space between the first capacitors  25 , and a third interlayer insulating film  29  is formed on the first capacitor  25  and the second interlayer insulating film  23 - 1 . A second capacitor  26  is formed on the third interlayer insulating film-  29  to contact the active region  22  through a contact  28 . Here, the long axis direction end of the second capacitor  26  overlaps with that of the first capacitors  25  by 1F 2 .  
         [0042]    As depicted in FIG. 4 b , the first and the second capacitors  25  and  26  are formed at a width of 1F to be separated from adjacent capacitors. It should be noted that these capacitors are formed according to conventional damascene and patterning processes.  
         [0043]    [0043]FIG. 5 is a layout view illustrating a semiconductor device in accordance with a second embodiment of the present invention, wherein capacitor has an area of 12F 2  larger than the capacitor of FIG. 3.  
         [0044]    5F by 1F rectangular active regions  32  are arranged on a semiconductor substrate  30  at an interval of 1F. A plurality of word lines  34  are arranged vertical to the active region  22  wherein two word lines cross one active region  32 . The first and the second capacitors  35  and  36  having a width of 2F and a length of 6F are formed on two different layers in one active region  32 . Here, the first and second capacitors  35  and  36  are electrically connected to the active region  32  through contacts  37  and  38 . Sections of the first capacitor  35  and the second capacitor  36  correspond to FIGS. 4 a  and  4   b , but are larger in size.  
         [0045]    Since intervals between contact portions of the first capacitors  35  and the second capacitor  36  are less than 1F, conventional patterning processes cannot be used. A process using a spacer is required for patterning.  
         [0046]    [0046]FIGS. 6 a  to  6   g  are cross-sectional views illustrating sequential steps of a method for forming a capacitor of FIG. 5 in accordance with the present invention.  
         [0047]    Referring to FIG. 6 a , a lower structure including active regions (not shown), a device isolation oxide film  51  and a gate electrode (not shown) is formed on a semiconductor substrate  50 , preferably a silicon wafer. A first interlayer insulating film  52  including first contact plugs  53 - 1  and a second contact plugs  53 - 2  for storage node is formed thereon.  
         [0048]    A first etch stop layer  54  and a second interlayer insulating film  55  which are composed of oxide films are sequentially formed on the entire surface of the resulting structure.  
         [0049]    As shown in FIG. 6 b , a portion of the second interlayer insulating film  55  and a portion of the first etch stop layer  54  are removed to form an opening exposing the second contact plug  53 - 2 , and the opening is then filled with a contact plug material to form a third contact plug  53 - 3 .  
         [0050]    As depicted in FIG. 6 c , the second interlayer insulating film  55  is removed so that the third contact plug  53 - 3  protrudes, and a first insulating spacer  57  is then formed on the sidewalls of the third contact plug  53 - 3 . Here, a width of the first insulating spacer is smaller than 1F and larger than 0.5F. When the width of the first insulating spacer  57  is smaller than 0.5F, a short may occur between the adjacent upper and lower capacitors, and when the width of the first insulating spacer  57  is larger than 1F, a size of the adjacent capacitor is reduced. In addition, the upper portion of the first contact plug  53 - 1  is exposed by the spacer formation process.  
         [0051]    As illustrated in FIG. 6 d , a first capacitor  61  including a storage node electrode  58 , a dielectric film  59  and a plate electrode  60  is formed to contact the exposed first contact plug  53 - 1 . Here, the first capacitor  61  has the same height as the third contact plug  53 - 3 .  
         [0052]    Referring to FIG. 6 e , a second etch stop layer  62  and a third interlayer insulating film  63  are sequentially formed on the entire surface of the resulting structure, and a contact hole  64  for external connection of the plate electrode  64  is then formed therein.  
         [0053]    As shown in FIG. 6 f , a fourth contact plug  65  for plate electrode is formed to fill the contact hole  64 . The third interlayer insulating film  63  is then removed to expose the second etch stop layer  62 , and a second insulating spacer  66  is formed on the sidewalls of the fourth contact plug  65 . Here, the second insulating spacer  66  has the same size restriction as the first insulating spacer  57 . In addition, the upper portion of the third contact plug  53 - 3  is exposed by the spacer formation process.  
         [0054]    As depicted in FIG. 6 g , a second capacitor  70  including a storage node  67 , a dielectric film  68  and a plate electrode  69  is formed to contact the third contact plug  53 - 3 .  
         [0055]    Each of the first capacitors  61  and the second capacitor  70  has a width of 2F and a length of 6F.  
         [0056]    [0056]FIG. 7 is a cross-sectional view illustrating a semiconductor device in accordance with a third embodiment of the present invention.  
         [0057]    Referring to FIG. 7, in insulation between the upper and lower capacitors using the first and second insulating spacers  57  and  66  is embodied by an additional photoetching process to remove a portion of the etch stop layer  62  to expose the upper portion of the contact plug  56  for second capacitor, and then performing subsequent processes.  
         [0058]    As discussed earlier, in accordance with the present invention, the capacitor of the semiconductor device and the method for forming the same provide improved cell capacitance four times as large as those of conventional capacitors although the aspect ratio is maintained by stacking the cell capacitors, thereby lowering a data read/write error rate to improve yield, and increasing refresh time to reduce power consumption.  
         [0059]    Moreover, it is possible to manufacture a low voltage, low power and high performance DRAM. When the structure in accordance with the present invention is employed to form a capacitor having the same capacitance as the conventional capacitors, the aspect ratio is reduced to 1/4, and the formation process of the device is simplified to improve the yield of the device.  
         [0060]    As a result, the capacitor of the semiconductor device and the method for forming the same provides improved operational characteristics of the device, and thus increase the yield and productivity of the device, which results in a high integration density of the device.  
         [0061]    As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.