Abstract:
An arbiter in a communication system including a plurality of request shapers in communication with a plurality of requestors. Each request shaper is configured to receive a request for access to a resource of the communication system, initially assign a priority level to the request upon receipt of the request, increase an age of the request, after increasing the age of the request, compare the age of the request to a delta period value associated with the respective requestor, and repeatedly increase the priority level of the request based on the comparison. Each of the plurality of requestors has a corresponding delta period value that is different from that of other ones of the plurality of requestors. An arbiter core is configured to grant one of the plurality of requestors access to the resource based on the priority level of each request and the age of each request.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 11/390,627, filed Mar. 28, 2006, which is a continuation of U.S. patent application Ser. No. 10/390,431 (now U.S. Pat. No. 7,062,582), filed Mar. 14, 2003. The disclosures of the above applications are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to arbitration of access to a shared resource. More particularly, the present invention relates to bus arbitration using dynamic priorities based on the waiting periods of the requests for the bus. 
     In many technologies, and especially in the arena of electronic computers, a scarce resource is shared among competing interests. For example, a shared bus in a computer is shared among several requestors. In such an environment, an efficient and simple arbitration scheme is desirable in order to increase the utilization of the bus, to increase bus access for the requestors, and to reduce the cost of the computer. 
     One conventional arbitration scheme simply assigns a fixed priority to each requestor. According to this scheme, access to the bus is always granted to the requestor having the highest priority. One disadvantage of this approach is that the low-priority requestors rarely, if ever, gain access to the bus. 
     SUMMARY OF THE INVENTION 
     In general, in one aspect, the invention features an arbitration circuit for granting access to a shared resource among requestors, comprising a plurality of request shapers each comprising an input unit to receive a request from one of a plurality of the requestors, a priority unit to assign a respective predetermined one of a plurality of priority levels to each of the requests, and an age unit to assign an age to each of the requests when the request is received by the request shaper; and an arbiter core to receive the requests from the request shapers, and to grant access to the shared resource to each of the requestors corresponding to the requests; wherein each of the age units increases the age of a respective one of the requests when the corresponding one of the requestors is not granted access to the shared resource; and wherein each of the priority units increases the priority level of a respective one of the requests, when the corresponding one of the requestors is not granted access to the shared resource, according to the age of the respective one of the requests. 
     Particular implementations can include one or more of the following features. The arbiter core comprises grant logic to grant access to the shared resource to one of the requestors according to the priority levels and the ages of the requests, comprising a priority encoder to select the one or more of the requests having the highest of the priority levels of the requests, and an arbitration unit to select the one, of the one or more of the requests selected by the priority encoder, having the greatest of the ages. Each of the requests has one of a plurality of delta periods of time, and each of the request shapers further comprises a priority adjuster to cause the respective priority unit to increase the priority level of the respective one of the requests when the age of the request has increased by the delta period of the request and the requestor corresponding to the request has not been granted access to the shared resource. The requests are received during a first interval, wherein the arbiter core further comprises a mask circuit to grant access to the shared resource to all of the requestors corresponding to the requests having one of the priority levels before granting access to the shared resource to requestors corresponding to any further requests having the one of the priority levels and received during a subsequent second interval. The mask circuit comprises a plurality of mask registers each corresponding to a respective one of the priority levels; wherein each of the mask registers stores a plurality of mask bits each corresponding to a respective one of the requestors; and a mask logic to set each of the mask bits when no corresponding request has been received having a corresponding one of the priority levels and the corresponding requestor has not been granted access to the shared resource; wherein the mask logic clears each of the mask bits when a corresponding request is received having a corresponding one of the priority levels. The arbiter core further comprises level filter logic to pass each of the requests to the grant logic only when the mask bit corresponding to the request is set. The shared resource is a shared communication bus; and wherein the requestors are communication units sharing the communication bus to exchange data. 
     In general, in one aspect, the invention features a method and computer-readable media for granting access to a shared resource among requestors. It comprises receiving a request from each of a plurality of the requestors; assigning a respective predetermined one of a plurality of priority levels to each of the requests; assigning an age to each of the requests when the request is received; and granting access to the shared resource to each of the requests, comprising granting access to the shared resource to the requestor corresponding to the one of the requests having the highest priority level and the greatest age, increasing the age of each of the requests corresponding to requestors that were not granted access to the shared resource, and increasing the priority level of each of the requests corresponding to requestors that were not granted access to the shared resource according to the age of the request. 
     Particular implementations can include one or more of the following features. Granting access to the shared resource to each of the requests comprises, when only one of the requests has a highest one of the priority levels of the requests, granting access to the shared resource to the requestor corresponding to the one of the requests having the highest priority level of the requests, and when more than one of the requests has the highest one of the priority levels of the requests, granting access to the shared resource to the requestor corresponding to the one of the requests having the highest one of the priority levels of the requests and the greatest age. Each of the requests has one of a plurality of delta periods of time, and wherein increasing the priority level of each of the requests corresponding to requestors that were not granted access to the shared resource according to the age of the request comprises increasing the priority level of each of the requests corresponding to requestors that were not granted access to the shared resource when the age of the request has increased by the delta period of the request. The requests are received during a first interval, and implementations further comprise receiving one or more further requests during a subsequent second interval; and granting access to the shared resource to all of the requestors corresponding to the requests having one of the priority levels before granting access to the shared resource to any of the requestors corresponding to the further requests having the one of the priority levels. 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 
     Further areas of applicability will become apparent from the description provided herein. It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way. 
         FIG. 1  shows a communication system comprising a plurality of requestors sharing a shared bus under the control of an arbiter. 
         FIG. 2  shows an arbiter that can serve as arbiter in the communication system of  FIG. 1  according to a preferred embodiment. 
         FIG. 3  shows a process performed by the arbiter of  FIG. 2  according to a preferred embodiment. 
         FIG. 4  shows an arbiter that can serve as the arbiter in the communication system of  FIG. 1  according to a preferred embodiment. 
         FIG. 5  shows a request shaper that can serve as a request shaper of  FIG. 4 . 
         FIG. 6  shows an arbiter core that can serve as the arbiter core of  FIG. 2 . 
         FIG. 7  shows a mask store that can serve as the mask store of  FIG. 6 . 
         FIG. 8  shows a level filter logic that can serve as the level filter logic of  FIG. 6 . 
         FIG. 9  shows a mask logic that can serve as the mask logic of  FIG. 6 . 
         FIG. 10  shows a grant logic that can serve as the grant logic of  FIG. 6 . 
     
    
    
     The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears. 
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1  shows a communication system  100  comprising a plurality of requestors  102 A through  102 N sharing a shared bus  104  under the control of an arbiter  106 . In a preferred embodiment, the requestors are communication units sharing the communication bus to exchange data. However, while embodiments of the invention are described with reference to communication system  100 , other embodiments apply to other sorts of systems. 
       FIG. 2  shows an arbiter  200  that can serve as arbiter  106  in communication system  100  of  FIG. 1  according to a preferred embodiment. 
     Arbiter  200  comprises a plurality of registers  204 A through  204 N, a plurality of counters  206 A through  206 N, and a logic circuit  208 . 
       FIG. 3  shows a process  300  performed by arbiter  200  according to a preferred embodiment. Arbiter  200  receives a plurality of requests from requestors  102  (step  302 ). Each request has one of a plurality of priority levels. The priority level of each request is stored in a respective one of registers  204 . When a request is received, an age is preset in a respective one of counters  206  (step  304 ). Preferably the preset age is zero, although other values can be used. Each counter  206  increments the value stored therein according to a clock signal CLK, thereby increasing the age of each request as time passes. 
     Logic circuit  208  grants access to bus  104  to one of requestors  102  in the following manner. Logic circuit  208  examines registers  204  to select the request having the highest priority level among the received requests (step  306 ). If only one of the requests has the highest priority of the received requests (step  308 ), logic circuit  208  grants access to bus  104  to the requestor  102  corresponding to the selected request (step  310 ). However, if more than one of the requests has the highest priority of the received requests (step  308 ), logic circuit  208  examines the counters  206  for those requests to select the request having greatest age among the received requests having the highest priority level (step  312 ). Logic circuit  208  then grants access to bus  104  to the requestor  102  corresponding to the selected request (step  310 ). 
     Arbiter  200  of  FIG. 2  is a very efficient arbiter, but requires a significant amount of logic that is limited in speed. In general, arbiter  200  therefore introduces an extra bus cycle, thus slowing the operation of communications system  100  of  FIG. 1 . 
       FIG. 4  shows an arbiter  400  that can serve as arbiter  106  in communication system  100  of  FIG. 1  according to a preferred embodiment. Arbiter  400  comprises an arbiter core  402  and a plurality of request shapers  404 A through  404 N. Each of request shapers  404  receives a request signal REQ from a respective one of the N requestors  102 . When a signal REQ goes high, the respective request shaper  404  passes the REQ signal to arbiter core  402 , along with a priority level signal PRI that represents a priority level of the request. The request shaper  404  initially determines the priority level of the request based on a base priority signal BASPRI. However, request shaper  404  increases the priority level, and therefore modifies the corresponding priority level signal PRI based on the passage of time with reference to a delta period signal DP. Each requestor  102  can have a different base priority and delta period. 
     Arbiter core  402  selects one of the requestors  102  based on the REQ and PRI signals, and sends a GRANT signal to the selected requestor  102 , and to the corresponding request shaper  404 , which clears the request. 
       FIG. 5  shows a request shaper  500  that can serve as a request shaper  404  of  FIG. 4 . Request shaper  500  comprises up-counters  502  and  508 , equality comparator  504 , rising-edge detector  506 , and OR gate  510 . Counter  502  has a reset input that receives the output of OR gate  510 , which receives the output of equality comparator  504  and the GRANT(N) signal. When arbiter core  402  receives a request signal REQ(N), the request signal enables counter  502 , thereby causing counter  502  to age the request by counting cycles of clock signal CLK. Rising-edge detector  506  loads counter  508  according to the base priority signal BASPRI(N) on receipt of the request signal. The base priority signal represents the initial priority assigned to requests received from the corresponding requestor. The initial priority is programmable. 
     Equality comparator  504  compares the count in counter  502  to the delta period signal DP(N), which represents a value that is programmable. When the count in the counter  502  reaches the delta period, the output of equality comparator  504  goes high, resetting counter  502  and incrementing counter  508 . Thus with the expiration of each delta period, the priority of a request is increased by one, up to the maximum priority level. Of course, the priority can be increased by other values instead. The count of counter  508  is output as signal PRI(N). 
     When the request is granted, counter  508  is reset. 
       FIG. 6  shows an arbiter core  600  that can serve as arbiter core  402  of  FIG. 2 . Arbiter core  600  comprises a mask store  602 , level filter logic  604 , mask logic  606 , grant logic  608 , and a bus monitor  610 . Level filter logic  604  receives the REQ and PRI request signals from requestors  102 , filters those request signals according to the contents of mask store  602 , and generates signals LVLREQ and LVLACTV in accordance with the contents of mask store  602 . Signal LVLREQ comprises N×I signals LVLREQ(N,I) where N is the number of requestors  102  and I is the number of priority levels. When high, each signal LVLREQ(N,I) indicates that arbiter core  402  is receiving a request signal from requestor  102 N having a priority level I, and that the request has not been masked, as discussed in detail below. The LVLACTV signal comprises I signals LVLACTV(I). When high, each LVLACTV(I) signal indicates that arbiter core  402  is receiving a request from at least one of requestors  102  that has a priority level I. 
     In response to signals GRANT, LVLREQ and LVLACTV, mask logic  606  modifies the contents of mask store  602 , as described in detail below. The contents of mask store  602  are provided to level filter logic  604 . 
     Bus monitor  610  monitors the status of bus  104 . When bus  104  is idle, bus monitor  610  causes a signal ALLOW_NEXT_ARB to be high. Signal LVLREQ is also provided to grant logic  608 . When signal ALLOW_NEXT_ARB is high, and in response to signal LVLREQ, grant logic  608  modifies the GRANT signal, which comprises N signals GRANT(N), one for each requestor  102 , thereby granting bus  104  to one of the requestors  102 . When signal ALLOW_NEXT_ARB is low, indicating that bus  104  is not idle, grant logic  608  does not modify the GRANT signal. This method prevents the interruption of a current bus access by the requestor  102  previously granted access to bus  104 . 
       FIG. 7  shows a mask store  700  that can serve as mask store  602  of  FIG. 6 . Mask store  700  comprises I N-bit registers  702 A through  702 I. Each register  702  corresponds to one of the I priority levels, and stores a mask bit for each of the N requestors  102 . When a mask bit is clear (that is, zero), arbiter core  402  will not accept a new request from the requester represented by that mask bit at the priority level represented by the mask register  702  storing that mask bit. 
       FIG. 8  shows a level filter logic  800  that can serve as level filter logic  604  of  FIG. 6 . Level filter logic  800  comprises I level filters  802 A through  802 I, each corresponding to one of the I priority levels. To avoid repetition, only one  802 A of level filters  802  is described. The remaining level filters  802  are similar to level filter  802 A. 
     Level filter  802 A corresponds to the lowest priority level (PRI=0) and comprises N equality comparators  804 A through  804 N and N AND gates  806 A through  806 N, each pair representing one of the N requestors  102 , and an OR gate  808 . Each equality comparator  804  receives a LVL signal that indicates the priority level I served by that level filter. Each equality comparator also receives a respective one of the PRI signals. When arbiter core  402  receives a request having PRI=0, the output of the equality comparator  804  in level filter  802 A (which corresponds to PRI=0) that corresponds to the requestor  102  sending the request goes high. If the REQ signal for that requestor  102  and the mask bit MASK(N,I) for that request are also high, the output of the corresponding AND gate  806  goes high. For example, if arbiter core  402  receives from requestor  102 N a request (REQ(7)=1) with a priority level of 0 (PRI(7)=0), and the corresponding mask bit MASK(7,0) is set, then the output of AND gate  806 N of level filter  802 A, which is a signal LVLREQ(7,0) goes high, indicating that arbiter core  402  has received a request from requestor  102 N at priority level 0 that is not masked. 
     All of the signals LVLREQ(N,I) produced by level filter  802 A are fed to OR gate  808 , which outputs a signal LVLACTV(0) that goes high when arbiter core  402  receives a request having a priority level of PRI=0. 
       FIG. 9  shows a mask logic  900  that can serve as mask logic  606  of  FIG. 6 . Mask logic  900  comprises N×I logic units  902 , each of which corresponds to one of the N requestors and one of the I priority levels. To avoid repetition, only one  902 (N,I) of logic units  902  is shown and described. The other logic units  902  are similar. 
     Logic unit  902 (N,I) comprises inverters  904 A,  904 B, and  904 C, AND gates  906 A and  906 B, NOR gate  908 , OR gate  912 , and flip-flops  910 A and  910 B, which are clocked by a clock signal CLK. Flip-flop  910 A receives signal LVLACTV(I) and provides a delayed version of that signal to inverter  904 B, which provides its output to AND gate  906 A. AND gate  906 A also receives signal LVLACTV(I), and receives signal LVLREQ(N,I) after inversion by inverter  904 C. NOR gate  908  receives the GRANT(I) signal and the output of AND gate  906 A. AND gate  906 B receives the outputs of NOR gate  908  and flip-flop  910 B, and receives the signal LVLACTV(I) after inversion by inverter  904 A. OR gate  912  receives the output of AND gate  906 B and signal LVLACTV(I). The output of flip-flop  910 B is the signal LVLMASK(N,I), which sets and clears the corresponding mask bit MASK(N,I) in mask store  602 . On a system reset, the SYSTEM_RESET signal is asserted, which resets all of the flip-flops  910 B in mask logic  900 . This causes all of the LVLMASK signals to go high, which sets all of the mask bits in mask store  602 , thereby permitting all requests to pass through level filter logic  604  to grant logic  608  until the mask bits are modified by level filter logic  604 . 
       FIG. 10  shows a grant logic  1000  that can serve as grant logic  608  of  FIG. 6 . Grant logic  1000  comprises an arbitration unit  1006 , a priority encoder  1002 , and a multiplexer (MUX)  1004 . 
     MUX  1004  receives I signals LVLREQ(I), where each signal LVLREQ(I) is an N-bit signal comprising the corresponding N signals LVLREQ(N,I). For example, in a system having 8 requestors and 16 priority levels, signal LVLREQ(5) for priority level 3 is an 8-bit signal comprising the corresponding 8 signals LVLREQ(0,5) through LVLREQ(7,5). 
     Priority encoder  1002  receives the I signals LVLACTV(0) through LVLACTV(I). As described above, each LVLACTV signal when high indicates that there is a pending request (that is, a request received and not masked, but not yet granted) of the corresponding priority level. Priority encoder  1002  selects the highest priority having a pending request, and passes that selection to MUX  1004  as signal LVLSEL, which causes MUX  1004  to pass to arbitration unit  1006  the signal LVLREQ(I) corresponding to the priority level I selected by priority encoder  1002 . Priority encoder  1002  is preferably implemented as a conventional logic circuit according to well-known techniques. 
     The signal LVLREQ(I) received by arbitration unit  1006  represents all of the pending requests having the highest priority of the pending requests. Arbitration unit  1006  selects one of those requests according to a conventional priority scheme such as a fixed priority scheme, a fairness priority scheme, and the like, and issues a GRANT signal to the requestor  102  corresponding to the selected request. Arbitration unit  1006  is preferably implemented as a conventional logic circuit according to well-known techniques. 
     Arbiter  400  of  FIG. 4  is an efficient arbiter, and requires substantially less logic than arbiter  200  of  FIG. 2 . In a 0.15-micron CMOS logic implementation, arbiter  400  of  FIG. 4  requires approximately 8,000 gates, and can operate at clock rates above 150 MHz. 
     The invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits). 
     A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.