Abstract:
An open loop half-bridge LLC power converter includes circuitry to reliably increase hold-up time without sacrificing efficiency. An LLC resonant circuit includes resonant inductance, a primary transformer winding, and resonant capacitance. An auxiliary circuit includes an auxiliary transformer winding, an inductor, and a third switching element coupled in series. A controller is coupled across a voltage sensor and effective thereby to determine a holdup time condition. In a “normal” operating condition the controller generates switch driver signals to turn OFF the third switching element and disable the auxiliary circuit, and in a hold-up time condition the controller turns ON the third switching element and enables the auxiliary circuit wherein the output voltage is increased via current supplied from the auxiliary winding. In various embodiments the auxiliary winding may be an auxiliary primary or secondary, or a secondary to an auxiliary primary winding of a second transformer.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This application claims benefit of the following patent application(s) which is/are hereby incorporated by reference: U.S. Provisional Application No. 61/622,862 dated Apr. 11, 2012. 
     
    
       [0002]    A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the reproduction of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 
       BACKGROUND OF THE INVENTION 
       [0003]    The present invention relates generally to power converters. More particularly, the present invention relates to gain enhancement circuitry for LLC resonant power converters wherein a hold-up time may be increased with minimal effect on efficiency. 
         [0004]    As market requirements for high efficiency have become more demanding, LLC resonant converters have correspondingly grown in popularity due to their high efficiency performance and their ability to achieve high power density. The 80 Plus Platinum certification standard requires greater than 94% efficiency at half load (50%) conditions. The 80 Plus Titanium standard requires 96% efficiency at half load conditions. 
         [0005]    However, there is a trade-off between the high efficiency and long hold-up time performance in a resonant converter. Generally speaking, the hold-up time of a converter is the amount of time (typically in milliseconds) that a power converter can continue to generate output within a specified range after an input power interruption. Efficiency can be increased significantly with, for example, an increase in magnetizing inductance to reduce switching losses. However, the hold-up time will consequently decrease by a significant amount as well. And likewise, efficiency may be sacrificed for long hold-up time performance. 
         [0006]    One solution that is known in the art for maintaining high efficiency performance while achieving long hold-up time is to increase the bulk capacitance. However, this results in problems of low power density and also higher cost. 
         [0007]    It would therefore be desirable to provide power converters with circuitry for balancing high efficiency and long hold-up time, while addressing the power density issues which would otherwise result from solutions in power converters as are presently known to those of skill in the art. 
       BRIEF SUMMARY OF THE INVENTION 
       [0008]    An open loop half-bridge LLC resonant power converter according to one aspect of the present invention includes circuitry to reliably increase hold-up time without increasing bulk capacitance or sacrificing efficiency. 
         [0009]    In an exemplary embodiment, an LLC resonant circuit includes resonant inductance, a primary transformer winding, and resonant capacitance. An auxiliary circuit includes an auxiliary transformer winding, an inductor, and a third switching element coupled in series. A controller is coupled across a voltage sensor and effective thereby to determine a holdup time condition. In a “normal” operating condition the controller generates switch driver signals to turn OFF the third switching element and disable the auxiliary circuit, and in a hold-up time condition the controller turns ON the third switching element and enables the auxiliary circuit. 
         [0010]    Generally stated, when the auxiliary circuit is enabled, current flows through the second inductor and the current is further coupled to the main transformer, wherein the gain of the resonant converter is increased and the output voltage maintained for a lower bulk voltage. Hence, increasing the hold-up time and maintaining high efficiency is achieved without requiring a larger, more expensive bulk capacitor in accordance with an objective of the present invention. 
         [0011]    In some embodiments the auxiliary winding may be an auxiliary primary winding of the transformer. 
         [0012]    In other embodiments the auxiliary winding may be an auxiliary secondary winding of the transformer. 
         [0013]    In still other embodiments the converter may further include a second transformer having a primary winding coupled in parallel with the primary winding of the first transformer, and the auxiliary winding of the hold-up circuit may be an auxiliary primary winding of the second transformer. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0014]      FIG. 1  is a circuit block diagram representing an exemplary LLC resonant converter with a first embodiment of a gain enhancement circuit according to the present invention. 
           [0015]      FIGS. 2(   a ),  2 ( b ),  2 ( c ),  2 ( d ) are graphical illustrations representing exemplary results from a simulation performed on the embodiment of  FIG. 1 . 
           [0016]      FIG. 3  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a second embodiment of a gain enhancement circuit according to the present invention. 
           [0017]      FIG. 4  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a third embodiment of a gain enhancement circuit according to the present invention. 
           [0018]      FIG. 5  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a fourth embodiment of a gain enhancement circuit according to the present invention. 
           [0019]      FIG. 6  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a fifth embodiment of a gain enhancement circuit according to the present invention. 
           [0020]      FIG. 7  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a sixth embodiment of a gain enhancement circuit according to the present invention. 
           [0021]      FIG. 8  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a seventh embodiment of a gain enhancement circuit according to the present invention. 
           [0022]      FIG. 9  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with an eighth embodiment of a gain enhancement circuit according to the present invention. 
           [0023]      FIG. 10  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a ninth embodiment of a gain enhancement circuit according to the present invention. 
           [0024]      FIG. 11  is a circuit block diagram representing the exemplary LLC resonant converter of  FIG. 1  with a tenth embodiment of a gain enhancement circuit according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0025]    Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” may include plural references, and the meaning of “in” may include “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. 
         [0026]    The term “coupled” means at least either a direct electrical connection between the connected items or an indirect connection through one or more passive or active intermediary devices. 
         [0027]    The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. 
         [0028]    The term “signal” as used herein may include any meanings as may be understood by those of ordinary skill in the art, including at least an electric or magnetic representation of current, voltage, charge, temperature, data or a state of one or more memory locations as expressed on one or more transmission mediums, and generally capable of being transmitted, received, stored, compared, combined or otherwise manipulated in any equivalent manner. 
         [0029]    The terms “switching element” and “switch” may be used interchangeably and may refer herein to at least: a variety of transistors as known in the art (including but not limited to FET, BJT, IGBT, JFET, etc.), a switching diode, a silicon controlled rectifier (SCR), a diode for alternating current (DIAC), a triode for alternating current (TRIAC), a mechanical single pole/double pole switch (SPDT), or electrical, solid state or reed relays. Where either a field effect transistor (FET) or a bipolar junction transistor (BJT) may be employed as an embodiment of a transistor, the scope of the terms “gate,” “drain,” and “source” includes “base,” “collector,” and “emitter,” respectively, and vice-versa. 
         [0030]    The terms “power converter” and “converter” unless otherwise defined with respect to a particular element may be used interchangeably herein and with reference to at least DC-DC, DC-AC, AC-DC, buck, buck-boost, boost, half-bridge, full-bridge, H-bridge or various other forms of power conversion or inversion as known to one of skill in the art. 
         [0031]    Terms such as “providing,” “processing,” “supplying,” “determining,” “calculating” or the like may refer at least to an action of a computer system, computer program, signal processor, logic or alternative analog or digital electronic device that may be transformative of signals represented as physical quantities, whether automatically or manually initiated. 
         [0032]    The terms “controller,” “control circuit” and “control circuitry” as used herein may refer to a processor-readable and non-transitory medium such as may be embodied by or included within a general microprocessor, application specific integrated circuit (ASIC), microcontroller, or the like as may be designed and programmed to cause specific functions as further defined herein to be performed upon execution by a processing unit, either alone or in combination with a field programmable gate array or various alternative blocks of discrete circuitry as known in the art. 
         [0033]    Referring generally to  FIGS. 1-11 , various embodiments of an LLC resonant power converter with hold-up time enhancement circuitry according to the present invention may now be described. Where the various figures may describe embodiments sharing various common elements and features with other embodiments, similar elements and features are given the same reference numerals and redundant description thereof may be omitted below. 
         [0034]    For example, each of  FIGS. 1-11  refer generally to a common configuration for an LLC resonant power converter  10 , with the individual figures referring more particularly to embodiments that vary depending on the position and configuration of a hold-up time enhancement circuit  12  according to the present invention. Generally stated, an exemplary such power converter  10  may include a power source V 1  which may typically be, for example, the output from a power factor correction (PFC) circuit, but may be any form of DC input as would be known to those of skill in the art. At least a first pair of switching elements Q 1 , Q 2  are coupled in series across the input power terminals of the power source V 1  to define a half bridge configuration. An LLC resonant circuit  14  is defined by a resonant inductor L 1 , a magnetizing inductance in the primary winding P 1  of a main transformer TX 1 , and resonant capacitors C 1 , C 2 . 
         [0035]    An output circuit  16  may be defined by secondary windings S 1 , S 2  of the main transformer TX 1 . Opposing ends of the secondary windings S 1 , S 2  are coupled via diodes D 1 , D 2  to a first end of output capacitor C 3  defining a first output terminal. A center tap between the secondary windings S 1 , S 2  is coupled to a second end of the output capacitor C 3  defining a second output terminal. Other configurations of the output circuit  16  may certainly be contemplated within the scope of the present invention, but the center tapped winding configuration may be desirable to increase the efficiency of the converter. 
         [0036]    A voltage sensor R 1  is coupled to a controller  18  whereby the controller may monitor an appropriate status of the power converter and determine the presence of a hold-up time condition. The sensor R 1  may be positioned in any of various locations throughout the power converter circuit  10 , whether proximate the output circuit, the input power source, or the like, and may further take various forms. As but one alternative example, an output inductor (not shown) may be coupled along the first branch of the output circuit between the diode D 1  and the output capacitor C 3 , with nodes on opposing sides of the output inductor being coupled to the controller via, for example, a resistive network. 
         [0037]    Referring more particularly now to  FIG. 1 , in a particular embodiment of the power converter  10   a  according to the present invention, a hold-up time enhancement circuit  12   a  includes an auxiliary primary winding P 2 , an auxiliary inductor L 2 , a diode D 3  and an auxiliary switching element Q 3  coupled in series. The auxiliary switching element Q 3  is driven on and off by signals provided from the controller  18 . 
         [0038]    During a normal condition (i.e., wherein the input power is ON or as may for example be determined by comparison of the input voltage to a predetermined threshold), the controller  18  turns off (or maintains off) the auxiliary switching element Q 3 , either by disabling control signals to the gate of the switching element Q 3  or by reducing the magnitude of the control signals to below the internal threshold for the switch Q 3 . 
         [0039]    However, when there is a temporary failure in the input power source, or any equivalent condition that would prompt the voltage across the bulk capacitor to drop (e.g., below the predetermined threshold), the controller  18  is programmed to thereby identify the presence of a hold-up time condition, and subsequently generates control signals to turn on the auxiliary switching element Q 3 . 
         [0040]    Alternatively, the controller  18  may continuously provide drive signals to the auxiliary switching element Q 3 , the drive signals of a voltage corresponding inversely to the detected signals from the voltage sensor. The auxiliary switching element Q 3  is only turned on when its gate-source voltage exceeds the internal threshold voltage for the switch Q 3 , which may correspond by design approximately to the desired point based on the voltage drop across the bulk capacitor. 
         [0041]    The auxiliary winding P 2  is coupled with voltage from primary winding P 1  having a value approximately proportional to the turn ratio of P 2  and P 1 . When the auxiliary switching element Q 3  is turned on, this voltage acts on the auxiliary inductor L 2  and a current sourced through the auxiliary inductor L 2  is further coupled to the primary winding P 1 . The additional current on the primary winding increases P 1  the gain of the LLC resonant converter, and the output voltage is maintained for an extended hold-up time. 
         [0042]    Referring generally to the graphical diagrams represented in  FIG. 2 , an exemplary operation of the embodiment in  FIG. 1  is now described. Component values may be as follows: 
         [0043]    resonant inductance (L 1 )=27 uH; 
         [0044]    resonant capacitance (C 1 , C 2 )=22 nF 
         [0045]    main transformer (TX 1 )=gapped to 150 uH; 
         [0046]    turn ratio for main transformer (TX 1 )=P 1 :P 2 :S 1 :S 2 =15:5:1:1; 
         [0047]    output voltage (Vout)=14V 
         [0048]    output current/load (Iout)=55 A 
         [0049]    When the signal CTL_Q 3  is provided in  FIG. 2(   d ), it may be demonstrated that the primary resonant current Ip increases and the voltage swing across the resonant capacitors Vc_res becomes larger. Hence, the total converter gain is boosted and a longer hold-up time is achieved. Note that the output voltage Vout further increased from 14V to 20V in this exemplary operation. 
         [0050]    In various embodiments as described herein, it may be further possible to boost converter efficiency by increasing the magnetization inductance to reduce switching losses on the auxiliary switching element Q 3 . 
         [0051]    In another exemplary embodiment of the LLC converter  10   b  as represented in  FIG. 3 , a hold-up time enhancement circuit  12   b  of the present invention may alternatively be located on the secondary side of the circuit. More particularly, the auxiliary winding may alternatively be an auxiliary secondary winding S 3 . Otherwise, the configuration and operation of the embodiment  10   b  of  FIG. 3  would be substantially identical to that of the embodiment  10   a  of  FIG. 1  and as described in more detail above. 
         [0052]    In another exemplary embodiment of the LLC converter  10   c  as represented in  FIG. 4 , a hold-up time enhancement circuit  12   c  of the present invention may be coupled to a second transformer TX 2 . A primary winding P 21  of the second transformer TX 2  is a magnetizing inductance coupled in parallel with the magnetizing inductance of the primary winding P 11  of the first transformer TX 1 , and an auxiliary winding of the hold-up time enhancement circuit  12   c  is a secondary winding S 21  with respect to the primary winding P 21 . Otherwise, the configuration and operation of the embodiment  10   c  of  FIG. 4  would be substantially identical to that of the embodiment  10   a  of  FIG. 1  and as described in more detail above. 
         [0053]    In another exemplary embodiment of the LLC converter  10   d  as represented in  FIG. 5 , a hold-up time enhancement circuit  12   d  of the present invention may be located on the secondary side of the circuit in similar fashion to that of the embodiment  10   b  in  FIG. 3 , wherein the auxiliary winding may be an auxiliary secondary winding S 3 , but one end of the auxiliary winding S 3  is now coupled to the output voltage rather than to the secondary ground, or otherwise stated is now coupled to a first output voltage terminal rather than a second output voltage terminal as in  FIG. 3 . Otherwise, the configuration and operation of the embodiment  10   d  of  FIG. 5  would be substantially identical to that of the embodiment  10   a  of  FIG. 1  and as described in more detail above. 
         [0054]    In another exemplary embodiment of the LLC converter  10   e  as represented in  FIG. 6 , a hold-up time enhancement circuit  12   e  of the present invention may be coupled to a second transformer TX 2  in similar fashion to that of embodiment  12   c  in  FIG. 4 , wherein a primary winding P 21  of the second transformer TX 2  is a magnetizing inductance coupled in parallel with the magnetizing inductance of primary winding P 11  of the first transformer TX 1 , and an auxiliary winding of the hold-up time enhancement circuit  12   e  is a secondary S 21  with respect to the primary winding P 21 . The primary difference of note is that one end of the auxiliary winding S 21  is coupled to the output voltage rather than to primary circuit ground as in  FIG. 4 . Otherwise, the configuration and operation of the embodiment  10   c  of  FIG. 4  would be substantially identical to that of the embodiment  10   a  of  FIG. 1  and as described in more detail above. 
         [0055]    Referring now to  FIG. 7 , an embodiment of the hold-up time enhancement circuit  12   f  may be positioned again in the primary side of the circuit, but now including a diode bridge D 4 , D 5 , D 6 , D 7  coupled between the auxiliary winding P 2  and the auxiliary switching element Q 3 . 
         [0056]    Referring to  FIG. 8 , another embodiment of the hold-up time enhancement circuit  12   g  may have substantially the same configuration as that of  FIG. 7 , with the exception of the circuit  12   g  being positioned on the secondary side of the main transformer TX 1 . 
         [0057]    Referring to  FIG. 9 , another embodiment of the hold-up time enhancement circuit  12   h  may have substantially the same configuration as that of  FIG. 7 , with the exception of the circuit  12   h  being positioned with respect to a second transformer TX 2 . 
         [0058]    Referring to  FIG. 10 , another embodiment of the hold-up time enhancement circuit  12   i  may include first and second auxiliary switching elements Q 3 , Q 4 . The controller  18  provides control signals to each of the auxiliary switching elements Q 3 , Q 4  during a hold-up time condition to perform substantially the same operation as in the configurations described above, namely, sourcing current through the auxiliary inductor L 2  to provide such current to the primary winding P 1  and further to generate a higher output voltage Vout. 
         [0059]    The embodiment of a hold-up time enhancement circuit  12   j  as represented in  FIG. 11  is substantially the same as the embodiment  12   i  in  FIG. 11 , except that it is now positioned in the secondary side of the circuit  10   j.    
         [0060]    The previous detailed description has been provided for the purposes of illustration and description. Thus, although there have been described particular embodiments of the present invention of a new and useful “Hold-up Time Enhancement Circuit for LLC Resonant Converter,” it is not intended that such references be construed as limitations upon the scope of this invention except as set forth in the following claims.