Abstract:
A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2013-0119074, filed on Oct. 7, 2013, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device supporting a training mode and a semiconductor system with the same. 
         [0004]    2. Description of the Related Art 
         [0005]    A semiconductor device becomes more integrated and of higher speed depending on demands. A semiconductor device uses a plurality of clocks according to target elements due to a high-speed operation. 
         [0006]    For example, a dynamic random access memory (DRAM) uses a data clock and a command clock, which synchronizes a command. That is, a memory device such as the DRAM receives or outputs data using the data clock, and receives a command and an address using the command clock. The data clock has a high frequency, for example 2 GHz, and the command clock has a relatively lower frequency, for example, 1 GHz. A high-speed memory device with an operation speed of 4 Gbps is realized with the data clock and the command clock. 
         [0007]    When the plurality of clocks are not synchronized or arranged, the semiconductor device cannot perform normal operations due to a time skew between the clocks. The semiconductor device performs a training mode in order to arrange or synchronize the plurality of clocks. The training mode is a process of training before entering a normal mode for optimized operation performance in the normal mode. 
         [0008]    The training mode will be described with a conventional memory device as an example. 
         [0009]      FIG. 1  is a block diagram illustrating a conventional memory device. 
         [0010]    Referring to  FIG. 1 , the conventional memory device  10  includes a command pad HCK, a command clock buffer unit  11 , a data pad WCK, a data clock input unit  13 , a phase information provision unit  15 , and a phase information pad EDC. 
         [0011]    An external command clock eHCK having a low frequency, for example 1 GHz, is received through the command pad HCK. The command clock buffer unit  11  generates an internal command clock iHCK in response to the external command clock eHCK. An external data clock eWCK having a high frequency, for example 2 GHz, is received through the data pad WCK. The data clock input unit  13  generates an internal data division clock iWCK_DVD having the same frequency as the internal command clock iHCK in response to the external data clock eWCK. The phase information provision unit  15  generates a phase information signal ePD between the internal command clock iHCK and the internal data division clock iWCK_DVD in response to a training mode signal TM. The phase information pad EDC outputs the phase information signal ePD to the external device. 
         [0012]    The data clock input unit  13  includes a data clock buffer unit  13 A and a dividing unit  13 B. 
         [0013]    The data clock buffer unit  13 A generates an internal data clock iWCK in response to the external data clock eWCK. The dividing unit  13 B generates the internal data division clock iWCK_DVD by dividing the internal data clock iWCK. The internal data division clock iWCK_DVD is one of first to fourth internal data division clocks (not illustrated) respectively corresponding to 4 phases of 0°, 90°, 180° and 270° to the internal data clock iWCK. 
         [0014]    The phase information provision unit  15  includes a replica delay unit  15 A, a phase comparing unit  156  and an output driver unit  15 C. 
         [0015]    The replica delay unit  15 A outputs a delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by a preset delay amount. The phase comparing unit  15 B compares phases of the delay division clock iWCK_DLY and the internal command clock iHCK. The output driver unit  15 C drives a phase comparison signal iPD output from the phase comparing unit  158  to the phase information pad EDC. 
         [0016]    The replica delay unit  15 A is provided in order to synchronize an internal delay amount reflected in the internal command clock iHCK with an internal delay amount reflected in the internal data division clock iWCK_DVD. Even though not illustrated in  FIG. 1 , the internal delay amount reflected in the internal command clock iHCK is greater than the internal delay amount reflected in the internal data division clock iWCK_DVD. If the internal delay amount reflected in the internal command clock iHCK is less than the internal delay amount reflected in the internal data division clock iWCK_DVD, the replica delay unit  15 A would be disposed on a transmission line of the internal command clock iHCK. 
         [0017]    An operation of the memory device  10  will be described reference to  FIG. 2 . 
         [0018]      FIG. 2  is a timing diagram illustrating a training process of the conventional memory device  10 . 
         [0019]    Referring to  FIG. 2 , an external controller (not illustrated) generates and provides the external command clock eHCK and the external data clock eWCK to the conventional memory device  10  at an initial operation. The conventional memory device  10  internally generates the internal command clock iHCK corresponding to the external command clock eHCK and the internal data division clock iWCK_DVD corresponding to the external data clock eWCK and enters the training mode under the control of the external controller. 
         [0020]    After entering the training mode in response to an activation of the training mode signal TM, the conventional memory device  10  samples one of the internal command clock iHCK and the internal data division clock iWCK_DVD based on the other one of the internal command clock iHCK and the internal data division clock iWCK_DVD, and generates and provides the phase information signal ePD in response to a sampling result to the external controller. 
         [0021]    In detail, the replica delay unit  15 A outputs the delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by the preset delay amount. The phase comparing unit  15 B compares the phases of the delay division clock iWCK_DLY and the internal command clock iHCK and outputs the phase comparison signal iPD in response to the comparison result. The output driver unit  15 C drives the phase information signal ePD corresponding to the phase comparison signal iPD to the phase information pad EDC. 
         [0022]    For example, the phase comparing unit  15 B generates the phase comparison signal iPD of a logic high level or a logic low level according to a phase relationship between the delay division clock iWCK_DLY and the internal command clock iHCK, and the output driver unit  15 C provides the phase information signal ePD of the logic high level or the logic low level to the external controller through the phase information pad EDC in response to the phase comparison signal iPD. 
         [0023]    The external controller adjusts one of phases of the external command clock eHCK and the external data clock eWCK in response to the phase information signal ePD. For example, the external controller shifts the phase of the external data clock eWCK backward when the phase of the delay division clock iWCK_DLY leads the phase of the internal command clock iHCK, and shifts the phase the external data clock eWCK forward when the phase of the internal command clock iHCK leads the phase of the delay division clock iWCK_DLY. 
         [0024]    The process of moving forward and backward is repeated until the phases of the internal command clock iHCK and the delay division clock iWCK_DLY are identical to each other. For example, the external controller shifts backward the phase of the external data clock eWCK by a preset amount of level when the phase of the delay division clock iWCK_DLY leads the phase of the internal command clock iHCK, and then stops the training operation when the phase of the internal command clock iHCK leads the phase of the delay division clock iWCK_DLY. 
         [0025]    Accordingly, optimal operation circumstance in the normal mode may be provided to the memory device  10  by making the phases of the internal command clock iHCK and the delay division clock iWCK_DLY identical to each other. 
         [0026]    However, the conventional memory device  10  has a concern as follows. 
         [0027]    The memory device  10  generates the phase information signal ePD according to the phase relationship between the delay division clock iWCK_DLY corresponding to the external data clock eWCK and the internal command clock iHCK corresponding to the external command clock eHCK. The memory device  10  provides simple phase information denoting which one of phases of the internal command clock iHCK and the delay division clock iWCK_DLY leads to the other, and generates the phase information signal ePD of single bit having the logic high level or the logic low level. 
         [0028]    The external controller adjusts one of the phases of the external command clock eHCK and the external data clock eWCK in response to the phase information signal ePD. The external controller adjusts one of the phases of the external command clock eHCK and the external data clock eWCK step by step by the preset amount of level, which means that there are more steps to adjust one of the phases of the external command clock eHCK and the external data clock eWCK as a phase difference between the external command clock eHCK and the external data clock eWCK becomes greater. Thus, there needs more time for the training operation as the phase difference between the external command clock eHCK and the external data clock eWCK becomes greater. 
       SUMMARY 
       [0029]    Various exemplary embodiments of the present invention are directed to a semiconductor device capable of generating various phase information in a training mode and semiconductor system with the same. 
         [0030]    In accordance with an exemplary embodiment of the present invention, a semiconductor device may include a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device. 
         [0031]    In accordance with an exemplary embodiment of the present invention, a semiconductor device may include a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock having a first frequency; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock having a second frequency higher than the first frequency, wherein the second internal clock has the same frequency as the first internal clock; and a delay amount information provision unit suitable for providing delay amount information, which indicates where a delay amount corresponding to a phase difference between the first internal clock and the second internal clock falls in among a plurality of preset delay amount ranges, to an external device in a training mode. 
         [0032]    In accordance with an exemplary embodiment of the present invention, a semiconductor system may include a controller suitable for generating a first source clock having a first frequency and a second source clock having a second frequency higher than the first frequency, and adjusting one of phases of the first source clock and the second source clock by a plurality of level units based on delay amount information in a training mode; and a semiconductor device suitable for generating a first internal clock, in which a first internal delay amount is reflected, in response to the first source clock, and a second internal clock, in which a second internal delay amount is reflected, in response to the second source clock, and providing the delay amount information, which indicates where a delay amount corresponding to a phase difference between the first internal clock and the second internal clock falls in among a plurality of preset delay amount ranges, to the controller in the training mode. 
         [0033]    In accordance with the exemplary embodiments of the present invention, in a training mode to make phases of two clocks identical to each other, a semiconductor system may adjust one of the phases of two clocks in units of a coarse level or a fine level according to various phase information between two clocks, and thus minimize time in the training mode. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0034]      FIG. 1  is a block diagram illustrating a conventional memory device. 
           [0035]      FIG. 2  is a timing diagram illustrating a training process of the conventional memory device. 
           [0036]      FIG. 3  is a block diagram illustrating a semiconductor system in accordance with an exemplary embodiment of the present invention. 
           [0037]      FIG. 4  is a block diagram illustrating a semiconductor device shown in  FIG. 3 . 
           [0038]      FIG. 5  is a block diagram illustrating a phase difference calculation unit shown in  FIG. 4 . 
           [0039]      FIG. 6  is a timing diagram illustrating a training process of the semiconductor system shown in  FIGS. 3 to 5 . 
           [0040]      FIG. 7  is a block diagram illustrating a semiconductor system in accordance with another exemplary embodiment of the present invention. 
           [0041]      FIG. 8  is a block diagram illustrating a semiconductor device shown in  FIG. 7 . 
           [0042]      FIG. 9  is a block diagram illustrating a phase difference calculation unit shown in  FIG. 8 . 
           [0043]      FIG. 10  is a timing diagram illustrating a training process of the semiconductor system shown in  FIGS. 7 to 9 . 
           [0044]      FIG. 11  is a block diagram illustrating a semiconductor system in accordance with an exemplary embodiment of the present invention. 
           [0045]      FIG. 12  is a block diagram illustrating a semiconductor device shown in  FIG. 11 . 
           [0046]      FIG. 13  is a block diagram illustrating a semiconductor system in accordance with an exemplary embodiment of the present invention. 
           [0047]      FIG. 14  is a block diagram illustrating a semiconductor device shown in  FIG. 13 . 
       
    
    
     DETAILED DESCRIPTION 
       [0048]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. Throughout the disclosure, reference numerals correspond directly to the like numbered parts in the various figures and embodiments of the present invention. It is also noted that in this specification, “connected/coupled” refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence. 
         [0049]    In the description, an external clock and an internal clock are divided based on a semiconductor device, and a memory device is taken as an example of the semiconductor device. 
         [0050]      FIG. 3  is a block diagram illustrating a semiconductor system in accordance with an exemplary embodiment of the present invention. 
         [0051]    Referring to  FIG. 3 , the semiconductor system may include a controller  100  and a memory device  200 . 
         [0052]    The controller  100  may generate an external command clock eHCK and an external data clock eWCK, and adjust one of phases of the external command clock eHCK and the external data clock eWCK by a plurality of level units based on an external delay amount information eDIF_SERI in a training mode. 
         [0053]    The memory device  200  may generate the external delay amount information eDIF_SERI in response to the external command clock eHCK and the external data clock eWCK at every preset period in the training mode. 
         [0054]    The controller  100  may be a control unit for controlling overall operations of the memory device  200  and include a processor such as a graphic processing unit (GPU). In the training mode, the controller  100  may adjust one of the phases of the external command clock eHCK and the external data clock eWCK in units of a coarse level or a fine level based on the external delay amount information eDIF_SERI provided from the memory device  200  at every preset period. 
         [0055]    For example, in the training mode, the controller  100  may shift backward the phase of the external data clock eWCK in units of a coarse level or a fine level based on the external delay amount information eDIF_SERI. 
         [0056]    The controller  100  may generate the external command clock eHCK having a first frequency, for example 1 GHz, and the external data clock eWCK having a second frequency higher than the first frequency, for example 2 GHZ, since data may be input or output with a higher speed than a command. Even though not illustrated in  FIG. 3 , the controller  100  may provide a command and/or an address synchronized with the external command clock eHCK and data synchronized with the external data clock eWCK to the memory device  200 . 
         [0057]    The memory device  200  may generate a first internal clock by delaying the external command clock eHCK by an amount of internal delay reflected in a first internal clock path, and a second internal clock by delaying the external data clock eWCK by an amount of internal delay reflected in a second internal clock path, and provide the external delay amount information eDIF_SERI to the controller  100  in the training mode. The external delay amount information eDIF_SERI may indicate an amount of delay corresponding to a phase difference between the first and second internal clocks and may indicate where the amount of delay falls in among a plurality of preset delay amount ranges. The first internal clock may correspond to an internal command clock iHCK, and the second internal clock may correspond to an internal data division clock iWCK_DVD. 
         [0058]      FIG. 4  is a block diagram illustrating the memory device  200  shown in  FIG. 3 . 
         [0059]    Referring to  FIG. 4 , the memory device  200  may include a command pad HCK, a command clock buffer unit  210 , a data pad WCK, a data clock input unit  220 , a delay amount information provision unit  230  and a delay amount information pad EDC. 
         [0060]    The external command clock eHCK may be received through the command pad HCK. The command clock buffer unit  210  may generate the internal command clock iHCK in response to the external command clock eHCK. The external data clock eWCK may be received through the data pad WCK. The data clock input unit  220  may generate the internal data division clock iWCK_DVD having the same frequency as the internal command clock iHCK in response to the external data clock eWCK. The delay amount information provision unit  230  may generate the external delay amount information eDIF_SERI corresponding to a phase difference between the internal command clock iHCK and the internal data division clock iWCK_DVD in response to a training mode signal TM. The delay amount information pad EDC outputs the external delay amount information eDIF_SERI to the controller  100 . 
         [0061]    The data clock input unit  220  may include a data clock buffer unit  221  and a dividing unit  223 . 
         [0062]    The data clock buffer unit  221  may generate an internal data clock iWCK in response to the external data clock eWCK. The dividing unit  223  may generate the internal data division clock iWCK_DVD by dividing the internal data clock iWCK. The internal data division clock iWCK_DVD is one of first to fourth internal data division clocks (not illustrated) respectively corresponding to 4 phases of 0°, 90°, 180° and 270° of the internal data clock iWCK. 
         [0063]    The delay amount information provision unit  230  may include a replica delay unit  231 , a phase difference calculation unit  233 , a serializing unit  235 , and an output driver unit  237 . 
         [0064]    The replica delay unit  231  may output a delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by a modelled delay amount. The phase difference calculation unit  233  may output first and second delay amount information signals DIF&lt;0:1&gt; corresponding to a phase difference between the delay division clock iWCK_DLY and the internal command clock iHCK in parallel. The serializing unit  235  may serialize the first and second delay amount information signals DIF&lt;0:1&gt; and output an internal delay amount information iDIF_SERI. The output driver unit  237  may drive the internal delay amount information iDIF_SERI output in series from the serializing unit  235  as the external delay amount information eDIF_SERI. 
         [0065]    The replica delay unit  231  may be provided in order to synchronize an internal delay amount reflected in the internal command clock iHCK with an internal delay amount reflected in the internal data division clock iWCK_DVD. Even though not illustrated in  FIG. 4 , the internal delay amount reflected in the internal command clock iHCK is greater than the internal delay amount reflected in the internal data division clock iWCK_DVD. If the internal delay amount reflected in the internal command clock iHCK is less than the internal delay amount reflected in the internal data division clock iWCK_DVD, the replica delay unit  231  would be disposed on a transmission line of the internal command clock iHCK. 
         [0066]      FIG. 5  is a block diagram illustrating the phase difference calculation unit  233  shown in  FIG. 4 . 
         [0067]    Referring to  FIG. 5 , the phase difference calculation unit  233  may include a first phase comparison unit  233 _ 1 , a first output unit  233 _ 3 , a reference delay unit  233 _ 5 , a second phase comparison unit  233 _ 7  and a second output unit  233 _ 9 . 
         [0068]    The first phase comparison unit  233 _ 1  may compare phases of the internal command clock iHCK and the delay division clock iWCK_DLY. The first output unit  233 _ 3  may output an output signal of the first phase comparison unit  233 _ 1  as the first delay amount information signal DIF&lt; 0 &gt;. The reference delay unit  233 _ 5  may delay the delay division clock iWCK_DLY by a preset delay amount and may output an additional delay division clock iWCK_DD. The second phase comparison unit  233 _ 7  may compare phases of the internal command clock iHCK and the additional delay division clock iWCK_DD. The second output unit  233 _ 9  may output an output signal of the second phase comparison unit  233 _ 7  as the second delay amount information signal DIF&lt; 1 &gt;. 
         [0069]    The delay amount information pad EDC may be an unused pad in the training mode. For example, the delay amount information pad EDC may be a pad for providing a Cyclic Redundancy Check (CRC) code to the controller  100  in a normal mode. The delay amount information pad EDC may be a common pad providing different signals respectively in different operation modes. The command pad HCK and the data pad WCK are dedicated pads for the external command clock eHCK and the external data clock eWCK, respectively. 
         [0070]    An operation of the semiconductor system described above will be described with reference to  FIG. 6 . 
         [0071]      FIG. 6  is a timing diagram illustrating a training process of the semiconductor system shown in  FIGS. 3 to 5 . 
         [0072]    Referring to FIG,  6 , the controller  100  may generate and provide the external command clock eHCK having a low frequency, for example 1 GHz, and the external data clock eWCK having a high frequency, for example 2 GHz, to the memory device  200  at an initial operation. The memory device  200  may internally generate the internal command clock iHCK corresponding to the external command clock eHCK and the internal data division clock iWCK_DVD corresponding to the external data clock eWCK, and may enter the training mode under the control of the controller  100 . 
         [0073]    For example, the memory device  200  may enter the training mode when the training mode signal TM, which is stored in a mode register set (MRS), is activated in response to a preset address and a preset command output from the controller  100 . 
         [0074]    After entering the training mode in response to an activation of the training mode signal TM, the memory device  200  may provide the external delay amount information eDIF_SERI, which may indicate where the amount of delay corresponding to a phase difference between the internal command clock iHCK and the internal data division clack iWCK_DVD falls in among a plurality of preset delay amount ranges, to the controller  100 . 
         [0075]    In detail, the replica delay unit  231  may output the delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by the modelled delay amount. The modelled delay amount may be referred to as a fixed amount of delay corresponding to a difference between the internal delay amount reflected in the internal command clock iHCK and the internal delay amount reflected in the internal data division clock iWCK_DVD. 
         [0076]    The phase difference calculation unit  233  may sample the phase of the delay division clock iWCK_DLY based on the phase of the internal command clock iHCK, may and generate the first delay amount information signal DIF&lt; 0 &gt; in response to the sampling result. The phase difference calculation unit  233  may sample the phase of the additional delay division clock iWCK_DD based on the phase of the internal command clock iHCK, and may generate the second delay amount information signal DIF&lt; 1 &gt; in response to the sampling result. 
         [0077]    For example, the phase difference calculation unit  233  may generate the first delay amount information signal DIF&lt; 0 &gt; having a logic high level when the phase of the delay division clock iWCK_DLY leads the phase of the internal command clock iHCK. The phase difference calculation unit  233  may generate the second delay amount information signal DIF&lt; 1 &gt; having a logic high level when the phase of the additional delay division clock iWCK_DD leads the phase of the internal command clock iHCK. 
         [0078]    The serializing unit  235  may serialize the first and second delay amount information signals DIF&lt;0:1&gt; and may output the internal delay amount information iDIF_SERI. The output driver unit  237  may drive the external delay amount information eDIF_SERI in response to the internal delay amount information iDIF_SERI output from the serializing unit  235  to the delay amount information pad EDC. 
         [0079]    The memory device  200  may provide the external delay amount information eDIF_SERI including the first and second delay amount information signals DIF&lt;0:1&gt; to the controller  100 . 
         [0080]    Accordingly, the controller  100  may adjust one of the phases of the external command clock eHCK and the external data clock eWCK in units of the coarse level or the fine level based on the external delay amount information eDIF_SERI. 
         [0081]    In case that both of the first and second delay amount information signals DIF&lt;0:1&gt; included in the external delay amount information eDIF_SERI have the logic high levels, it is determined that a delay amount corresponding to the difference between the phases of the internal command clock iHCK and the delay division clock iWCK_DLY falls in a first delay amount range. Accordingly, the controller  100  may shift backward the phase of the external data clock eWCK in units of the coarse level. 
         [0082]    In case that the first delay amount information signal DIF&lt; 0 &gt; included in the external delay amount information eDIF_SERI has the logic high level and the second delay amount information signal DIF&lt; 1 &gt; included in the external delay amount information eDIF_SERI has the logic low level, it is determined that a delay amount corresponding to the difference between the phases of the internal command clock iHCK and the delay division clock iWCK_DLY falls in a second delay amount range. Accordingly, the controller  100  may shift backward the phase of the external data clock eWCK in units of the fine level. 
         [0083]    The controller  100  and the memory device  200  may repeat the process of moving backward at every preset period. That is, the memory device  200  may provide the external delay amount information eDIF_SERI corresponding to the phase difference between the internal command clock iHCK and the delay division clock iWCK_DLY to the controller  100  at every preset period. The controller  100  may adjust one of the phases of the external command clock eHCK and the external data clock eWCK in units of the coarse level or the fine level based on the external delay amount information eDIF_SERI at every preset period. 
         [0084]    In case that both of the first and second delay amount information signals DIF&lt;0:1&gt; included in the external delay amount information eDIF_SERI have the logic high levels for some preset periods, the controller  100  may shift backward the phase of the external data clock eWCK in units of the coarse level. After that, in case that the first delay amount information signal DIF&lt; 0 &gt; included in the external delay amount information eDIF_SERI has the logic high level and the second delay amount information signal DIF&lt; 1 &gt; included in the external delay amount information eDIF_SERI has the logic low level during the next preset periods, the controller  100  may shift backward the phase of the external data clock eWCK in units of the fine level. 
         [0085]    After that, when it is determined in response to the external delay amount information eDIF_SERI that the phases of the external command clock eHCK and the external data clock eWCK are identical to each other, the controller  100  may stop adjusting the phase of the external data clock eWCK. For example, in case that both of the first and second delay amount information signals DIF&lt;0:1&gt; included in the external delay amount information eDIF_SERI have the logic low levels, the controller  100  may fix the phase of the external data clock eWCK. 
         [0086]    According to the exemplary embodiment described above, the semiconductor system may adjust the phase in units of the coarse level for some periods based on the phase information in the training mode, thereby minimizing time in the training mode. 
         [0087]      FIG. 7  is a block diagram illustrating a semiconductor system in accordance with another exemplary embodiment of the present invention. 
         [0088]    In accordance with the exemplary embodiment of the present invention, the semiconductor system may further shift forward as well as backward the phase of the clocks. 
         [0089]    Referring to  FIG. 7 , the semiconductor system may include a controller  300  and a memory device  400 . 
         [0090]    The controller  300  may generate an external command clock eHCK and an external data clock eWCK, and adjust one of phases of the external command clock eHCK and the external data clock eWCK by a plurality of level units based on an external delay amount information eDIF_SERI in a training mode. 
         [0091]    The memory device  400  may generate the external delay amount information eDIF_SERI in response to the external command clock eHCK and the external data clock eWCK at every preset period in the training mode. 
         [0092]    The controller  300  may be a control unit for controlling overall operations of the memory device  400  and include a processor such as a graphic processing unit (GPU). In the training mode, the controller  300  may adjust one of the phases of the external command clock eHCK and the external data clock eWCK in units of a coarse level or a fine level based on the external delay amount information eDIF_SERI provided from the memory device  400  at every preset period. 
         [0093]    For example, in the training mode, the controller  300  may shift backward the phase of the external data clock eWCK in units of a coarse level or a fine level based on the external delay amount information eDIF_SERI. 
         [0094]    Further, the controller  300  in the training mode may shift forward the phase of the external data clock eWCK in units of a coarse level or a fine level based on the external delay amount information eDIF_SERI. 
         [0095]    The controller  300  may generate the external command clock eHCK having a first frequency, for example 1 GHz, and the external data clock eWCK having a second frequency higher than the first frequency, for example 2 GHZ, since data may be input or output with a speed higher than a command. Even though not illustrated in  FIG. 7 , the controller  300  may provide a command and/or an address synchronized with the external command clock eHCK and data synchronized with the external data clock eWCK to the memory device  400 . 
         [0096]    The memory device  400  may generate a first internal clock by delaying the external command clock eHCK by an amount of internal delay reflected in a first internal clock path, and a second internal clock by delaying the external data clock eWCK by an amount of internal delay reflected in a second internal clock path, and provide the external delay amount information eDIF_SERI to the controller  300  in the training mode. The external delay amount information eDIF_SERI may indicate where an amount of delay corresponding to a phase difference between the first and second internal clocks falls in among a plurality of preset delay amount ranges. The first internal clock may correspond to an internal command clock iHCK, and the second internal clock may correspond to an internal data division clock iWCK_DVD. 
         [0097]      FIG. 8  is a block diagram illustrating the memory device  400  shown in  FIG. 7 . In  FIGS. 4 and 8 , like reference numerals are used to refer to the same elements. 
         [0098]    Referring to FIG,  8 , the memory device  400  may include a command pad HCK, a command clock buffer unit  210 , a data pad WCK, a data clock input unit  220 , a delay amount information provision unit  430  and a delay amount information pad EDC. 
         [0099]    The external command clock eHCK may be received through the command pad HCK. The command clock buffer unit  210  may generate the internal command clock iHCK in response to the external command clock eHCK. The external data clock eWCK may be received through the data pad WCK. The data clock input unit  220  may generate the internal data division clock iWCK_DVD having the same frequency as the internal command clock iHCK in response to the external data clock eWCK. The delay amount information provision unit  430  may generate the external delay amount information eDIF_SERI corresponding to a phase difference between the internal command clock iHCK and the internal data division clock iWCK_DVD in response to a training mode signal TM. The delay amount information pad EDC outputs the external delay amount information eDIF_SERI to the controller  300 . 
         [0100]    The memory device  400  shown in  FIG. 8  may have the same elements as the memory device  200  shown in  FIG. 4  except for the delay amount information provision unit  430 . 
         [0101]    The delay amount information provision unit  430  may include a replica delay unit  431 , a phase difference calculation unit  433 , a serializing unit  435 , and an output driver unit  437 . 
         [0102]    The replica delay unit  431  may output a delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by a modelled delay amount. The phase difference calculation unit  433  may output first to third delay amount information signals DIF&lt;0:2&gt; corresponding to a phase difference between the delay division clock iWCK_DLY and the internal command clock iHCK in parallel. The serializing unit  435  may serialize the first to third delay amount information signals DIF&lt;0:2&gt; and output an internal delay amount information iDIF_SERI. The output driver unit  437  may drive the internal delay amount information iDIF_SERI output in series from the serializing unit  435  as the external delay amount information eDIF_SERI. 
         [0103]    The replica delay unit  431  may be provided in order to synchronize an internal delay amount reflected in the internal command clock iHCK with an internal delay amount reflected in the internal data division clock iWCK_DVD. Even though not illustrated in  FIG. 8 , the internal delay amount reflected in the internal command clock iHCK is greater than the internal delay amount reflected in the internal data division clock iWCK_DVD. If the internal delay amount reflected in the internal command clock iHCK is less than the internal delay amount reflected in the internal data division clock iWCK_DVD, the replica delay unit  431  would be disposed on a transmission line of the internal command clock iHCK. 
         [0104]      FIG. 9  is a block diagram illustrating the phase difference calculation unit  433  shown in  FIG. 8 . 
         [0105]    Referring to  FIG. 9 , the phase difference calculation unit  433  may include a first phase comparison unit  433 _ 1 , a first output unit  433 _ 2 , a first reference delay unit  433 _ 3 , a second phase comparison unit  433 _ 4 , a second output unit  433 _ 5 , a second reference delay unit  433 _ 6 , a third phase comparison unit  433 _ 7 , and a third output unit  433 _ 8 . 
         [0106]    The first phase comparison unit  433 _ 1  may compare phases of the internal command clock iHCK and the delay division clock iWCK_DLY. The first output unit  433 _ 2  may output an output signal of the first phase comparison unit  433 _ 1  as the first delay amount information signal DIF&lt; 0 &gt;. The first reference delay unit  433 _ 3  may delay the delay division clock iWCK_DLY by a preset delay amount, and may output an additional delay division clock iWCK_DD. The second phase comparison unit  433 _ 4  may compare phases of the internal command clock iHCK and the additional delay division clock iWCK_DD output from the first reference delay unit  433 _ 3 . The second output unit  433 _ 5  may output an output signal of the second phase comparison unit  433 _ 4  as the second delay amount information signal DIF&lt; 1 &gt;. The second reference delay unit  433 _ 6  may delay the internal command clock iHCK by a preset delay amount, and may output a delay command clock iHCK_D. The third phase comparison unit  433 _ 7  may compare phases of the delay command clock iHCK_D output from the second reference delay unit  433 _ 6  and the delay division clock iWCK_DLY. The third output unit  433 _ 8  may output an output signal of the third phase comparison unit  433 _ 7  as the third delay amount information signal DIF&lt; 2 &gt;. 
         [0107]    An operation of the semiconductor system described above will be described with reference to  FIG. 10 . 
         [0108]      FIG. 10  is a timing diagram illustrating a training process of the semiconductor system shown in  FIGS. 7 to 9 . 
         [0109]    Referring to  FIG. 10  the controller  300  may generate and provide the external command clock eHCK having a low frequency, for example 1 GHz, and the external data clock eWCK having a high frequency, for example 2 GHz, to the memory device  400  at an initial operation. The memory device  400  may internally generate the internal command clock iHCK corresponding to the external command clock eHCK and the internal data division clock iWCK_DVD corresponding to the external data clock eWCK, and may enter the training mode under the control of the controller  300 . 
         [0110]    For example, the memory device  400  may enter the training mode when the training mode signal TM, which is stored in a mode register set (MRS), is activated in response to a preset address and a preset command output from the controller  300 . 
         [0111]    After entering the training mode in response to an activation of the training mode signal TM, the memory device  400  may provide the external delay amount information eDIF_SERI, which may indicate where the amount of delay corresponding to a phase difference between the internal command clock iHCK and the internal data division clock iWCK_DVD falls in among a plurality of preset delay amount ranges, to the controller  300 . 
         [0112]    In detail, the replica delay unit  431  may output the delay division clock iWCK_DLY by delaying the internal data division clock iWCK_DVD by the modelled delay amount. The modelled delay amount may be referred to as a fixed amount of delay corresponding to a difference between the internal delay amount reflected in the internal command clock iHCK and the internal delay amount reflected in the internal data division clock iWCK_DVD. 
         [0113]    The phase difference calculation unit  433  may sample the phase of the delay division clock iWCK_DLY based on the phase of the internal command clock iHCK, and may generate the first delay amount information signal DIF&lt; 0 &gt; in response to the sampling result. The phase difference calculation unit  433  may sample the phase of the additional delay division clock iWCK_DD based on the phase of the internal command clock iHCK, and may generate the second delay amount information signal DIF&lt; 1 &gt; in response to the sampling result. The phase difference calculation unit  433  may sample the phase of the delay division clock iWCK_DLY based on the phase of the delay command clock iHCK_D, and generate the third delay amount information signal DIF&lt; 2 &gt; in response to the sampling result. 
         [0114]    For example, in a first case (CASE I), the phase difference calculation unit  433  may generate the first delay amount information signal DIF&lt; 0 &gt; having a logic high level when the phase of the delay division clock iWCK_DLY leads the phase of the internal command clock iHCK. The phase difference calculation unit  433  may generate the second delay amount information signal DIF&lt; 1 &gt; having a logic high level when the phase of the additional delay division clock iWCK_DD leads the phase of the internal command clock iHCK. The phase difference calculation unit  433  may generate the third delay amount information signal DIF&lt; 2 &gt; having a logic high level when the phase of the delay division clock iWCK_DLY leads the phase of the delay command clock iHCK_D. 
         [0115]    On the other hand, in a second case (CASE II), the phase difference calculation unit  433  may generate the first delay amount information signal DIF&lt; 0 &gt; having a logic low level when the phase of the internal command clock iHCK leads the phase of the delay division clock iWCK_DLY. The phase difference calculation unit  433  may generate the second delay amount information signal DIF&lt; 1 &gt; having a logic low level when the phase of the internal command clock iHCK leads the phase of the additional delay division clock iWCK_DD. The phase difference calculation unit  433  may generate the third delay amount information signal DIF&lt; 2 &gt; having a logic low level when the phase of the delay command clock iHCK_D leads the phase of the delay division clock iWCK_DLY. 
         [0116]    The serializing unit  435  may serialize the first to third delay amount information signals DIF&lt;0:2&gt; and output the internal delay amount information iDIF_SERI. The output driver unit  437  may drive the external delay amount information eDIF_SERI in response to the internal delay amount information iDIF_SERI output from the serializing unit  435  to the delay amount information pad EDC. 
         [0117]    The memory device  400  may provide the external delay amount information eDIF_SERI including the first to third delay amount information signals DIF&lt;0:2&gt; to the controller  300 . 
         [0118]    Accordingly, the controller  300  may adjust one of the phases of the external command clock eHCK and the external data clock eWCK in units of the coarse level or the fine level based on the external delay amount information eDIF_SERI. 
         [0119]    In the first case (CASE I) where all of the first to third delay amount information signals DIF&lt;0:2&gt; included in the external delay amount information eDIF_SERI have the logic high levels, it is determined that a delay amount corresponding to the difference between the phases of the internal command clock iHCK and the delay division clock iWCK_DLY falls in a first delay amount range. Accordingly, the controller  300  may shift backward the phase of the external data clock eWCK in units of the coarse level. 
         [0120]    Thereafter, when the second delay amount information signal DIF&lt; 1 &gt; included in the external delay amount information eDIF_SERI becomes the logic low level in a state that the first delay amount information signal DIF&lt; 0 &gt; and the third delay amount information signal DIF&lt; 2 &gt; included in the external delay amount information eDIF_SERI have the logic high levels, it is determined that a delay amount corresponding to the difference between the phases of the internal command clock iHCK and the delay division clock iWCK_DLY falls in a second delay amount range. Accordingly, the controller  300  may shift backward the phase of the external data clock eWCK in units of the fine level. 
         [0121]    In the second case (CASE II) that all of the first to third delay amount information signals DIF&lt;0:2&gt; included in the external delay amount information eDIF_SERI have the logic low levels, it is determined that a delay amount corresponding to the difference between the phases of the internal command clock iHCK and the delay division clock iWCK_DLY falls in a third delay amount range. Accordingly, the controller  300  may shift forward the phase of the external data clock eWCK in units of the coarse level. 
         [0122]    Thereafter, when the third delay amount information signal DIF&lt; 2 &gt; included in the external delay amount information eDIF_SERI becomes the logic high level in a state that the first delay amount information signal DIF&lt; 0 &gt; and the second delay amount information signal DIF&lt; 1 &gt; included in the external delay amount information eDIF_SERI have the logic low levels, it is determined that a delay amount corresponding to the difference between the phases of the internal command clock iHCK and the delay division clock iWCK_DLY falls in a fourth delay amount range. Accordingly, the controller  300  may shift forward the phase of the external data clock eWCK in units of the fine level. 
         [0123]    The controller  300  and the memory device  400  may repeat the process of moving forward and backward at every preset period. That is, the memory device  400  may provide the external delay amount information eDIF_SERI corresponding to the phase difference between the internal command clock iHCK and the delay division clock iWCK_DLY to the controller  300  at every preset period. The controller  300  may adjust one of the phases of the external command clock eHCK and the external data clock eWCK in units of the coarse level or the fine level based on the external delay amount information eDIF_SERI at every preset period. 
         [0124]    In the first case (CASE I) that all of the first to third delay amount information signals DIF&lt;0:2&gt; included in the external delay amount information eDIF_SERI have the logic high levels for some preset periods, the controller  300  may shift backward the phase of the external data clock eWCK in units of the coarse level. After that, when the second delay amount information signal DIF&lt; 1 &gt; included in the external delay amount information eDIF_SERI becomes the logic low level in a state that the first delay amount information signal DIF&lt; 0 &gt; and the third delay amount information signal DIF&lt; 2 &gt; included in the external delay amount information eDIF_SERI have the logic high levels during the next preset periods, the controller  300  may shift backward the phase of the external data clock eWCK in units of the fine level. 
         [0125]    In the second case (CASE II) that all of the first to third delay amount information signals DIF&lt;0:2&gt; included in the external delay amount information eDIF_SERI have the logic low levels for some preset periods, the controller  300  may shift forward the phase of the external data clock eWCK in units of the coarse level. After that, when the third delay amount information signal DIF&lt; 2 &gt; included ire the external delay amount information eDIF_SERI becomes the logic high level in a state that the first delay amount information signal DIF&lt; 0 &gt; and the second delay amount information signal DIF&lt; 1 &gt; included in the external delay amount information eDIF_SERI have the logic low levels during the next preset periods, the controller  300  may shift forward the phase of the external data clock eWCK in units of the fine level. 
         [0126]    After that, when it is determined in response to the external delay amount information eDIF_SERI that the phases of the external command clock eHCK and the external data clock eWCK are identical to each other, the controller  300  may stop adjusting the phase of the external data clock eWCK. For example, in the first case (CASE I) that both of the first and second delay amount information signals DIF&lt;0:1&gt; included in the external delay amount information eDIF_SERI have the logic high levels, the controller  300  may fix the phase of the external data clock eWCK. In the second case (CASE II) that both of the first and third delay amount information signals DIF&lt; 0 &gt; and DIF&lt; 2 &gt; included in the external delay amount information eDIF_SERI have the logic high levels, the controller  300  may fix the phase of the external data clock eWCK. 
         [0127]      FIG. 11  is a block diagram illustrating a semiconductor system in accordance with still another exemplary embodiment of the present invention.  FIG. 12  is a block diagram illustrating a semiconductor device shown in  FIG. 11 . 
         [0128]    Referring to  FIG. 11 , the semiconductor system may include a controller  500  and a memory device  600 . 
         [0129]    The controller  500  may generate an external command clock eHCK and an external data clock eWCK and may adjust one of phases of the external command clock eHCK and the external data clock eWCK by a plurality of level units based on an external delay amount information eDIF&lt;0:1&gt; in a training mode. 
         [0130]    The memory device  600  may generate the external delay amount information eDIF&lt;0:1&gt; in response to the external command clock eHCK and the external data clock eWCK at every preset period in the training mode. 
         [0131]    The controller  500  shown in  FIG. 11  may have the same elements as the controller  100  shown in  FIG. 3  except that the controller  500  may receive first and second external delay amount information eDIF&lt;0:1&gt; as delay amount information through corresponding channels. 
         [0132]    The memory device  600  shown in  FIGS. 11 and 12  may have the same elements as the memory device  200  shown in  FIGS. 3 and 4  except that the first and second external delay amount information eDIF&lt;0:1&gt; are provided to first and second delay amount information pads EDC 0  and EDC 1  from a phase difference calculation unit  633  through first and second output driver units  635  and  637  as shown in  FIG. 12 . 
         [0133]    The delay amount information pads EDC 0  and EDC 1  may be common pads providing different signals respectively in different operation modes. For example, the delay amount information pads EDC 0  and EDC 1  may be pads for providing CRC codes per region to the external device in a normal mode. Two or more common pads may be used as the delay amount information pads EDC 0  and EDC 1  in the training mode. 
         [0134]    An operation of the semiconductor system shown in  FIGS. 11 and 12  may be substantially the same as the semiconductor system shown in  FIGS. 3 to 6 . 
         [0135]      FIG. 13  is a block diagram illustrating a semiconductor system in accordance with still another exemplary embodiment of the present invention.  FIG. 14  is a block diagram illustrating a semiconductor device shown in  FIG. 13 . 
         [0136]    Referring to  FIG. 13 , the semiconductor system may include a controller  700  and a memory device  800 . 
         [0137]    The controller  700  may generate an external command clock eHCK and an external data clock eWCK, and may adjust one of phases of the external command clock eHCK and the external data clock eWCK by a plurality of level units based on an external delay amount information eDIF&lt;0:2&gt; in a training mode. 
         [0138]    The memory device  800  may generate the external delay amount information eDIF&lt;0:2&gt; in response to the external command clock eHCK and the external data clock eWCK at every preset period in the training mode. 
         [0139]    The controller  700  shown in  FIG. 13  may have the same elements as the controller  400  shown in  FIG. 7  except that the controller  700  may receive first to third external delay amount information eDIF&lt;0:2&gt; as delay amount information through corresponding channels. 
         [0140]    The memory device  800  shown in  FIGS. 13 and 14  may have the same elements as the memory device  400  shown in  FIGS. 7 and 8  except that the first to third external delay amount information eDIF&lt;0:2&gt; are provided to first to third delay amount information pads EDC 0  to EDC 2  from a phase difference calculation unit  833  through first to third output driver units  835  to  839  as shown in  FIG. 14 . 
         [0141]    The delay amount information pads EDC 0  to EDC 2  may be common pads providing different signals respectively in different operation modes. For example, the delay amount information pads EDC 0  to EDC 2  may be pads for providing CRC codes per region to the external device in a normal mode. Three or more common pads may be used as the delay amount information pads EDC 0  to EDC 2  in the training mode. 
         [0142]    An operation of the semiconductor system shown in  FIGS. 13 and 14  may be substantially the same as the semiconductor system shown in  FIGS. 7 to 10 . 
         [0143]    While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 
         [0144]    For example, the exemplary embodiments of the present invention may adjust the phase of the clocks in units of a coarse level or a fine level in the description. However, in different embodiments, three or more levels may be used to adjust the phase of the clocks.