Abstract:
Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to semiconductor fabrication, and more particularly, to precut metal lines. 
       BACKGROUND 
       [0002]    As the fabrication techniques for semiconductor devices has progressed, manufacturers have been placing an increasingly larger number of devices on a chip by increasing the integration density of semiconductor devices. Accordingly, a critical dimension (CD) in a design rule is gradually reduced in order to increase the circuit density. 
         [0003]    In order to increase the circuit density, it is necessary to reduce the sizes of elements inside the semiconductor devices and reduce the lengths and widths of interconnections which couple the elements together. Moreover, the resistances of interconnections must be small so that electric signals can be transferred with minimal loss within the semiconductor devices through interconnections having narrow widths. 
         [0004]    In a typical integrated circuit, there may be many metallization layers and interconnecting via layers formed in a back end of line (BEOL) interconnect structure. The BEOL interconnect structure connects various devices (e.g. transistors, capacitors, etc.) to form functional circuits. During fabrication, it is necessary to form cuts and connections of metal lines to create the desired connectivity to implement a given design. As critical dimensions continue to shrink, this can be challenging. It is therefore desirable to have improvements to address the aforementioned challenges. 
       SUMMARY 
       [0005]    Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus, embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. 
         [0006]    In a first aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a plurality of sacrificial Mx+1 lines over a plurality of metal Mx lines; depositing a dielectric layer over the plurality of sacrificial Mx+1 lines; forming a cut cavity in one sacrificial Mx+1 line of the plurality of sacrificial Mx+1 lines; forming a dielectric region in the cut cavity; removing the plurality of sacrificial Mx+1 lines to form a plurality of Mx+1 line cavities; and filling the plurality of Mx+1 line cavities with a metal to form a plurality of metal Mx+1 lines. 
         [0007]    In a second aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a plurality of sacrificial Mx+1 lines over a plurality of metal Mx lines; depositing a dielectric layer over the plurality of sacrificial Mx+1 lines; depositing an organic planarization layer on the dielectric layer; depositing a resist layer on the organic planarization layer; forming a cavity in the resist layer and organic planarization layer; removing the resist layer; depositing a conformal spacer layer on the organic planarization layer; performing an anisotropic etch on the conformal spacer layer to form an aperture spacer; forming a cut cavity in one sacrificial Mx+1 line of the plurality of sacrificial Mx+1 lines; forming a dielectric region in the cut cavity; removing the plurality of sacrificial Mx+1 lines to form a plurality of Mx+1 line cavities; and filling the plurality of Mx+1 line cavities with a metal to form a plurality of metal Mx+1 lines. 
         [0008]    In a third aspect, embodiments of the present invention provide a method of forming a semiconductor structure, comprising: forming a plurality of sacrificial Mx+1 lines over a plurality of metal Mx lines; depositing a dielectric layer over the plurality of sacrificial Mx+1 lines; forming a cut cavity in one sacrificial Mx+1 line of the plurality of sacrificial Mx+1 lines; forming a dielectric region in the cut cavity; removing the plurality of sacrificial Mx+1 lines to form a plurality of Mx+1 line cavities; depositing a via cut lithography stack; patterning an opening in the via cut lithography stack; forming a via cavity that exposes one Mx metal line of the plurality of metal Mx lines; removing the via cut lithography stack; and filling the plurality of Mx+1 line cavities and via cavity with a metal to form a plurality of metal Mx+1 lines and a via. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the present teachings and, together with the description, serve to explain the principles of the present teachings. 
           [0010]    Certain elements in some of the figures may be omitted, or illustrated not-to-scale, for illustrative clarity. The cross-sectional views may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a “true” cross-sectional view, for illustrative clarity. 
           [0011]    Often, similar elements may be referred to by similar numbers in various figures (FIGs) of the drawing, in which case, typically the last two significant digits may be the same, the most significant digit being the number of the drawing figure (FIG). Furthermore, for clarity, some reference numbers may be omitted in certain drawings. 
           [0012]      FIG. 1  is a semiconductor structure at a starting point for embodiments of the present invention. 
           [0013]      FIG. 2  is a semiconductor structure after a subsequent process step of depositing a sacrificial layer. 
           [0014]      FIG. 3  is a semiconductor structure after subsequent process steps of depositing a resist layer and patterning the resist layer. 
           [0015]      FIG. 4  is a semiconductor structure after subsequent process steps of patterning the sacrificial layer and removing the resist layer. 
           [0016]      FIG. 5  is a side view of a semiconductor structure after a subsequent process step of depositing a dielectric layer over the sacrificial Mx+1 lines. 
           [0017]      FIG. 6  is a side view of a semiconductor structure after a subsequent process step of planarizing the dielectric layer. 
           [0018]      FIG. 7  is a semiconductor structure after subsequent process steps of depositing and patterning a line cut lithography stack. 
           [0019]      FIG. 8  is a semiconductor structure after a subsequent process step of forming a cut cavity in a sacrificial Mx+1 line. 
           [0020]      FIG. 9  is a semiconductor structure after a subsequent process step of removing the line cut lithography stack. 
           [0021]      FIG. 10  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of removing the resist layer. 
           [0022]      FIG. 11  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of depositing a conformal spacer layer. 
           [0023]      FIG. 12  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of performing an anisotropic etch to form an aperture spacer. 
           [0024]      FIG. 13  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of forming a cut cavity in a sacrificial Mx+1 line. 
           [0025]      FIG. 14  is a semiconductor structure after a subsequent process step of forming a dielectric region in the cut cavity. 
           [0026]      FIG. 15  is a semiconductor structure after a subsequent process step of removing the sacrificial Mx+1 lines. 
           [0027]      FIG. 16  is a semiconductor structure after subsequent process steps of depositing and patterning a via cut lithography stack. 
           [0028]      FIG. 17  is a semiconductor structure after a subsequent process step of forming a via cavity that exposes an Mx metal line. 
           [0029]      FIG. 18  is a semiconductor structure after a subsequent process step of removing the via cut lithography stack. 
           [0030]      FIG. 19  is a semiconductor structure after a subsequent process step of forming metal Mx+1 lines. 
           [0031]      FIG. 20  is the semiconductor structure of  FIG. 19  as viewed along line B-B′. 
           [0032]      FIG. 21  is a flowchart indicating process steps for embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0033]    Exemplary embodiments will now be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. It will be appreciated that this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. 
         [0034]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. For example, as used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms “a”, “an”, etc., do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. It will be further understood that the terms “comprises” and/or “comprising”, or “includes” and/or “including”, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
         [0035]    Reference throughout this specification to “one embodiment,” “an embodiment,” “embodiments,” “exemplary embodiments,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” “in embodiments” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment. 
         [0036]    The terms “overlying” or “atop”, “positioned on” or “positioned atop”, “underlying”, “beneath” or “below” mean that a first element, such as a first structure, e.g., a first layer, is present on a second element, such as a second structure, e.g. a second layer, wherein intervening elements, such as an interface structure, e.g. interface layer, may be present between the first element and the second element. 
         [0037]      FIG. 1  is a semiconductor structure  100  at a starting point for embodiments of the present invention. Semiconductor structure  100  shows a back-end-of-line (BEOL) wiring structure having a plurality of metal lines  106 , which are formed in a dielectric layer  102 . In embodiments, dielectric layer  102  may be comprised of SiOC (silicon oxycarbide). In embodiments, the metal lines  106  are comprised of copper. In embodiments, each metal line  106  is surrounded on the sides and bottom by a barrier layer  104 . This serves to prevent diffusion of the metal. In embodiments, the barrier layer  104  is comprised of tantalum and/or tantalum nitride. A capping layer  105  may be deposited on the tops of the metal lines  106 . In embodiments, the capping layer  105  may be comprised of SiN (silicon nitride). The metal lines  106  are referred to as Mx lines, where “x” denotes a particular metallization level. Below metal lines  106  are metal lines  103 . Thus, metal lines  103  are referred to as Mx−1 metal lines. The metal lines may be formed using industry-standard techniques, including, but not limited to, barrier deposition, metal seed layer deposition, and a metal plating process, followed by a planarization process. In embodiments, an etch stop layer  110  is deposited over the dielectric layer  102 , covering the metal lines  106 . In embodiments, the etch stop layer  110  is comprised of aluminum oxide (Al2O3). 
         [0038]      FIG. 2  is semiconductor structure  100  after a subsequent process step of depositing a sacrificial layer  112  over the semiconductor structure. The sacrificial layer  112  is deposited on the etch stop layer  110 . In embodiments, the sacrificial layer  112  may be comprised of SiN, and may be deposited by plasma enhanced chemical vapor deposition (PECVD). Amorphous silicon can also be used as a sacrificial material. 
         [0039]      FIG. 3  is semiconductor structure  100  after subsequent process steps of depositing and patterning a resist layer (lithography stack)  114 , thus forming a patterned lithography stack. The patterning may be accomplished using industry-standard lithographic methods, including, but not limited to, self-aligned double patterning (SADP), or self-aligned quad patterning (SAQP). 
         [0040]      FIG. 4  is semiconductor structure  100  after subsequent process steps of patterning the sacrificial layer and removing the resist layer. This forms sacrificial “dummy” Mx+1 lines  116  on the semiconductor structure. This may be achieved by anisotropically etching the sacrificial layer  112  of  FIG. 3 , stopping on etch stop layer  110 , as to remove the portion of the sacrificial layer that is not covered by the patterned resist layer in order to form sacrificial “dummy” lines  116 , and then removing the resist layer  114 . In some embodiments, etch stop layer  110  may also be removed. Note that both Mx and Mx+1 are illustrated as a regular set of unidirectional parallel lines at each level, with Mx+1 perpendicular to Mx. 
         [0041]      FIG. 5  is a side view of semiconductor structure  100  after a subsequent process step of depositing a dielectric layer  118  over the sacrificial Mx+1 lines as viewed along line A-A′ of  FIG. 4 . In embodiments, the dielectric layer  118  may be comprised of silicon oxycarbide (SiOC). The dielectric layer may be deposited using a plasma-enhanced chemical vapor deposition (PECVD) process. In embodiments, due to the conformal nature of the dielectric layer  118 , air gaps  120  may be formed in between each sacrificial line  116 . The air gaps have a dielectric constant of approximately 1, and thus can serve to improve circuit performance in regards to high speed signals that propagate through BEOL layers. 
         [0042]      FIG. 6  is a side view of semiconductor structure  100  after a subsequent process step of planarizing the dielectric layer  118  such that it is substantially flush with the sacrificial lines  116 . In embodiments, the planarization is performed with a chemical mechanical polish (CMP) process. The air gaps  120  may be preserved during this process (as shown), or in some embodiments, may be partially opened (not shown). 
         [0043]      FIG. 7  is semiconductor structure  100  after subsequent process steps of depositing and patterning a line cut lithography stack  122 . The line cut lithography stack  122  may include an organic planarization layer (OPL) followed by a layer of photoresist (referred to as “resist”). In embodiments, the OPL can include a photo-sensitive organic polymer comprising a light-sensitive material that, when exposed to electromagnetic (EM) radiation, is chemically altered and thus configured to be removed using a developing solvent. For example, the photo-sensitive organic polymer may be polyacrylate resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylenether resin, polyphenylenesulfide resin, or benzocyclobutene (BCB). 
         [0044]    A plurality of voids  124  are patterned in the lithography stack  122 . The voids  124  each expose a region of a sacrificial line  116 , as well as some of the dielectric region  118 . The dielectric layer  118  and the sacrificial lines  116  are comprised of different materials, allowing selective etch techniques to remove the portions of the sacrificial lines  116  that are exposed through the voids  124 , without removing the exposed dielectric regions  118 . Thus, the tolerances of the position and sizing of each void  124  is relaxed, enabling easier manufacturing and improved product yield. 
         [0045]      FIG. 8  is semiconductor structure  100  after a subsequent process step of forming a cut cavity  126  in a sacrificial Mx+1 line. As stated previously, the dielectric layer  118  and the sacrificial lines  116  are comprised of different materials, allowing selective etch techniques to remove the portions of the sacrificial lines  116 . Thus, exposed regions of sacrificial lines  116  are removed, exposing the etch stop layer  110  below, and forming a cut cavity  126 . 
         [0046]      FIG. 9  is semiconductor structure  100  after a subsequent process step of removing the line cut lithography stack ( 122  in  FIG. 7 ). The lithography stack may be removed using industry-standard techniques, thus revealing the pattern of sacrificial lines  116  with cut cavities  126  at locations where the replacement (metal) lines are to be separated. 
         [0047]      FIG. 10  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of removing the resist layer of line cut lithography stack  122  (see  FIG. 7 ), exposing an underlying organic planarization layer (OPL). Thus  FIG. 10  follows from  FIG. 7 , but provides additional process steps to further control the size of the cut cavities, as will be shown in the following figures. Voids  124  are formed in the OPL  128  to expose regions sacrificial lines  116 . 
         [0048]      FIG. 11  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of depositing a conformal spacer layer  130 . In embodiments, the conformal spacer layer  130  is comprised of carbon, and may be deposited via an atomic layer deposition process. In embodiments, the conformal spacer layer has a thickness ranging from about 2 nanometers to about 5 nanometers. A recessed portion  132  is formed over the voids  124  in the OPL. 
         [0049]      FIG. 12  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of performing an anisotropic etch to form an aperture spacer  134 . In embodiments, the anisotropic etch may include a reactive ion etch (RIE) process. The anisotropic etch removes most of the conformal spacer layer, except for the remaining portion, which is aperture spacer  134 . The aperture spacers  134  have a segment thickness D 1 . In embodiments, D 1  ranges from about 2 nanometer to about 8 nanometers. The aperture spacers further restrict the opening prior to removing a portion of the sacrificial lines  116  to have a length D 2 , thus enabling smaller cut cavities. In embodiments, D 2  may range from about 5 nanometers to about 30 nanometers. 
         [0050]      FIG. 13  is a semiconductor structure in accordance with an alternative embodiment of the present invention after a subsequent process step of forming a cut cavity in a sacrificial Mx+1 line. As stated previously, the dielectric layer  118  and the sacrificial lines  116  are comprised of different materials, allowing selective etch techniques to remove the portions of the sacrificial lines  116 . The carbon spacer may then be selectively etched away. 
         [0051]      FIG. 14  is a semiconductor structure after a subsequent process step of forming a dielectric region  118 A in the cut cavity. From  FIG. 14  forward, the process is similar for both the embodiment shown in  FIGS. 1-9 , and for the alternative embodiment with additional steps shown in  FIGS. 10-13 . As shown in  FIG. 14 , additional dielectric material  118 A is deposited in each cut cavity. A planarization process may follow, such that the dielectric regions  118 A are substantially planar with sacrificial lines  116  and dielectric regions  118 . This can be accomplished by a chemical mechanical polish (CMP) process and/or an anisotropic RIE etch back. Dielectric regions  118 A and dielectric regions  118  are preferably comprised of the same material. Hence, in embodiments, dielectric regions  118 A may also be comprised of SiOC. 
         [0052]      FIG. 15  is a semiconductor structure after a subsequent process step of removing the sacrificial Mx+1 lines. This may be accomplished using a selective etch process, such that dielectric regions  118  and  118 A remain intact. 
         [0053]      FIG. 16  is a semiconductor structure after subsequent process steps of depositing and patterning a via cut lithography stack  136 . The via cut lithography stack  136  may contain an OPL layer, antireflective layer, and a resist layer. Using patterning, voids  138  are formed in the via cut lithography stack  136 . The voids are formed over an area where the sacrificial lines  116  have been removed, thus revealing a portion of capping layer  105  of a perpendicularly oriented Mx line disposed in the metallization layer below. Depending on a given design, it is desirable to, at certain locations, form vias that interconnect to neighboring metallization levels. Thus, voids are formed where it is desirable to form a via between an Mx line and an Mx+1 line. 
         [0054]      FIG. 17  is a semiconductor structure after a subsequent process step of forming a via cavity that exposes an Mx metal line. The region of capping layer (see  105  of  FIG. 16 ) is removed using a selective etch process. For example, if the dielectric layer  118  is SiOC, and the capping layer  105  is SiN, then a variety of selective etch techniques can be used to selectively remove the capping layer  105 . Embodiments of the present invention may use other materials for the dielectric and capping layer, so long as selective etching of the materials to each other is possible. 
         [0055]      FIG. 18  is a semiconductor structure after a subsequent process step of removing the via cut lithography stack ( 136  of  FIG. 17 ). This exposes capping regions  105  where no via is to be formed, while Mx line  106  is exposed in an area where a via is to be formed. 
         [0056]      FIG. 19  is a semiconductor structure after a subsequent process step of forming metal Mx+1 lines. In embodiments, this may include an electroplating process. The process may include depositing one or more barrier layers and/or seed layers (not shown). Then, a fill metal (such as copper) is deposited in the location where the sacrificial Mx+1 lines previously occupied, forming metallization lines  142 . The dielectric region  118 A separates metallization line  142 A from metallization line  142 A′. Thus, metallization lines  142 A and  142 A′ are precut, as they are formed with the cuts already in place, and so metal cutting is avoided. Metallization line  142 B has a via that connects to the Mx level, as will be further described in the next figure. 
         [0057]      FIG. 20  is the semiconductor structure of  FIG. 19  as viewed along line B-B′. As can be seen, Mx+1 metal line  142 B connects to Mx metal line  106 . When Mx+1 metal line  142 B was formed, the Mx line  106  was exposed, since its capping layer was removed (see  106  in  FIG. 18 ). Hence, the process in accordance with embodiments of the present invention simplifies fabrication by avoiding metal cuts, and also integrates via connectivity into the metallization process. 
         [0058]      FIG. 21  is a flowchart  200  indicating process steps for embodiments of the present invention. In process step  250 , sacrificial lines are formed. In embodiments, the sacrificial lines are comprised of silicon nitride. In process step  252 , a dielectric layer is deposited. In embodiments, the dielectric layer is comprised of SiOC. In process step  254 , a line cut lithography stack is deposited (see  122  of  FIG. 7 ). In process step  256 , the sacrificial lines are cut (see  FIG. 9 ). In process step  258 , additional dielectric is deposited in the cut cavities (see  118 A of  FIG. 14 ). In process step  260 , the sacrificial lines are removed (see  FIG. 15 ). In embodiments, the etch stop layer ( 110  in  FIG. 1 ) is also removed. In process step  262 , a via cavity lithography stack is deposited (see  136  of  FIG. 16 ). In process step  264 , selected M(x) lines are opened in locations where a via between the M(x) and M(x+1) levels is to be formed (see  140  of  FIG. 17 ). In process step  266 , M(x+1) metal lines are formed (see  142  of  FIG. 19 ). The processes disclosed herein may then be repeated to make multiple metallization levels. In some embodiments, there may be 10 or more levels. Once the BEOL stack is complete, industry-standard techniques for additional processes such as packaging and test may be used to complete fabrication of the integrated circuit. 
         [0059]    While the invention has been particularly shown and described in conjunction with exemplary embodiments, it will be appreciated that variations and modifications will occur to those skilled in the art. For example, although the illustrative embodiments are described herein as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events unless specifically stated. Some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the invention.