Abstract:
An image sensor includes an array of pixels arranged into two or more subarrays and each subarray captures charge; and an output charge-coupled device that receives charge from the array of pixels; wherein the output charge-coupled device is divided into substantially two equal first and second portions in which either one portion receives charge from only one subarray or both portions receive charge respectively from a subarray, and the first portion of the charge-coupled device is a charge-multiplying charge-coupled device in which charge is amplified, and the second portion of the charge-coupled device does not amplify charge.

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates generally to the field of image sensors and, more particularly, to an image sensor with a charge multiplying charge-coupled device (CCD).  
       BACKGROUND OF THE INVENTION  
       [0002]      FIG. 1  shows an example of an image sensor  10  with a charge multiplying CCD  40 . The image sensor  10  consists of a pixel array  20  which may be of the well-known CCD types of full frame or interline. The pixel array  20  shifts row of charge into a horizontal serial CCD  30 . The row of charge in the horizontal serial CCD  30  is shifted through a charge multiplying CCD  40  that amplifies the size of a charge packet by a factor 1 to 100. At the end of the charge multiplying CCD  40  is an output amplifier  50  that converts a charge packet into a measurable voltage.  
         [0003]      FIG. 2  illustrates the operation of a prior art charge multiplying CCD. It consists of a repeating set of four control gates H 1 , H 2 , H 3 , and H 4  separated from a silicon substrate  70  by a gate dielectric  60 . The channel potential in the silicon substrate  70  is also drawn on  FIG. 2 . A large voltage is applied to gate H 4  to produce a large channel potential. Gate H 1  is at a low voltage to prevent two charge packets from mixing together. Gate H 3  is held at a constant intermediate voltage while the voltage on gate H 2  is decreased to a lower voltage. As the gate H 2  voltage decreases the channel potential under gate H 2  also decreases. This pushes the charge packet from under H 2  through the gate H 3  region where electrons enter the large channel potential region under gate H 4 . The large channel potential difference between gates H 3  and H 4  creates a large electric field in the silicon that accelerates the electrons to high enough energy to liberate additional electrons  80  from the silicon lattice. This is often called avalanche charge multiplication. This effect has a long history and details regarding its use in CCDs may be found in U.S. Pat. Nos. 4,912,536; 5,337,340; 5,656,835; 6,278,142; and 6,444,968; as well as U.S. patent publications 2002/0126213A1; 2002/0191093A1; 2003/0035057A1; 2003/0042400A1; 2003/0223531A1; and 2004/0150737A1.  
         [0004]     The common aspect of all the prior art is the requirement that a CCD be specially designed to implement a charge multiplying CCD. The present invention described hereinbelow shows how to operate an existing CCD as a charge multiplying CCD. The invention applies to commercially available CCD image sensors such as Eastman Kodak Company part numbers KAI-2020, KAI-2093, and KAI-4021. Use of existing image sensors as charge-multiplying CCDs costs less because there is no additional design or development required.  
       ADVANTAGEOUS EFFECT OF THE INVENTION  
       [0005]     The present invention includes the advantage of operating existing CCD image sensors as charge-multiplying CCDs without fabrication of specially designed image sensors. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0006]      FIG. 1  is a prior art image sensor;  
         [0007]      FIG. 2  is prior art charge multiplying CCD;  
         [0008]      FIG. 3  is a view of a typical image sensor that is also reconfigured according to the present invention;  
         [0009]      FIG. 4  is an illustration of typical horizontal CCD operation without charge multiplication;  
         [0010]      FIG. 5  is an illustration of charge multiplication horizontal CCD operation of present invention;  
         [0011]      FIG. 6  is a timing diagram for charge multiplication horizontal CCD operation of the present invention;  
         [0012]      FIG. 7  is an illustration of an alternative embodiment of an image sensor capable of charge multiplication of the present invention; and  
         [0013]      FIG. 8  is a side view of a digital camera for illustrating a typical commercial embodiment for the image sensor of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0014]      FIG. 3  shows the image sensor structure common to Eastman Kodak Company part numbers KAI-2020, KAI-2093, and KAI-4021. The image sensor  100  is an interline CCD comprised of an array of photodiodes  110 . The photodiodes  110  receive photons that are converted to electrons and stored at the photodiode site  110  until the end of the image capture time. After image capture is complete, the electrons stored in the photodiode  110  are transferred to the parallel vertical CCDs  115 . The vertical CCDs  115  are light shielded so that the electron charge packets may be read out of the CCDs without being corrupted by additional exposure to light. The vertical CCDs  115  shift the charge packets in parallel one row at a time towards the horizontal CCDs  130  and  140 . In between the horizontal CCDs  130  and  140  and the vertical CCDs  115  is a fast dump row  160 . The fast dump row  160  provides a means of discarding an entire row of charge packets without reading them out of the horizontal CCDs  130  and  140 . Discarding rows of charge packets allows for faster image readout by skipping some rows if desired.  
         [0015]     There are two horizontal CCDs;  130  is for the left half of the pixel array and  140  is for the right half of the pixel array. The horizontal CCDs are of the pseudo-2-phase type that allows the direction of charge transfer to be reversed. They both transfer charge to the left to read out the entire pixel array through only the left side output amplifier  120 . Alternatively, the left horizontal CCD  130  can transfer charge to the left output amplifier  120 , and the right horizontal CCD  140  can transfer charge to the right output amplifier  150 . Using two outputs almost cuts the read out time in half. Each horizontal CCD has its own independent set of charge transfer voltage control inputs H 1 S, H 1 B, H 2 S, and H 2 B. This dual horizontal CCD design is important for implementing charge multiplication. First, it is instructive to note normal horizontal CCD operation without charge multiplication.  
         [0016]      FIG. 4  shows the horizontal CCD structure. The horizontal CCD consists of a repeating sequence of charge transfer control gates H 1 S, H 1 B, H 2 S, and H 2 B. The gates are separated from the silicon surface by an insulating dielectric  400 . The horizontal CCD implants consist of an n-type buried channel  410  in a p-type well or substrate  420 . Underneath the gates H 1 B and H 2 B there is an extra light p-type implant  430 . The implant  430  causes the channel potential under the H 1 B and H 2 B gates to be less than the channel potential under the H 1 S and H 2 S gates even though they may have the same gate voltage. The implant  430  is often called a barrier implant and is present to facilitate control of the direction of charge transfer.  
         [0017]     The normal clocking sequence of the horizontal CCD without charge multiplication is also shown in  FIG. 4 . At time T 1  the H 1 S and H 1 B gates are at 0 V and the H 2 S and H 2 B gates are at −5 V. The charge packet always flows to the gates with the highest gate voltage (deepest channel potential). When the gate voltages are swapped at time T 2  the charge packet advances forward by two gates. This is the normal low voltage operation of the horizontal CCD without charge multiplication.  
         [0018]      FIG. 5  shows how the same horizontal CCD shown in  FIG. 4  may be operated as a charge multiplying CCD. The horizontal CCD in  FIG. 5  has the same set of control gates H 1 S, H 1 B, H 2 S, and H 2 B as well as the same buried channel  410 , barrier implants  430 , and p-well  420 . One of the significant differences is the timing and gate voltages. The charge multiplication process begins at time step T 1  where H 1 B, H 2 S and H 2 B are all set at a low voltage of −−5 V. The barrier implants  430  under H 1 B and H 2 B confine the charge packet to gate H 2 S until the gate H 1 S reaches its maximum voltage of +10 V. Then at time step T 2  the H 1 B gate voltage is increased to +0 V to allow the charge packet to flow across the high electric field between gates H 1 B and H 1 S. The high electric field accelerates the electrons in the charge packet to high enough energy to liberate additional electrons from the silicon lattice and increase the size of the charge packet.  
         [0019]     The timing diagram for the gate voltages is shown in  FIG. 6 . The rising clock edges of H 1 B and H 2 B are delayed until the H 1 S and H 2 S rising edge transition is completed. The H 1 S and H 2 S clock amplitudes are +15V. This amplitude is adjusted to select how much charge multiplication is to take place. Lower clock amplitudes will yield less charge multiplication.  
         [0020]     The clocking of  FIGS. 5 and 6  is only applied to the left half horizontal CCD  130 . The clocking of  FIG. 4  is applied to the right half horizontal CCD  140 . Charge from the left half vertical CCDs  115  that is transferred into the left half horizontal CCD  130  is read out but not used. The charge from the entire left half of the image sensor  100  will experience a non-uniform charge multiplication. This is because the left most pixel in the horizontal CCD  130  only passes through one charge multiplication transfer. While the right most pixel in the horizontal CCD  130  passes through many charge multiplication transfers, all of the charge in the right horizontal CCD  140  passes through the same number of charge multiplication transfers in the left horizontal CCD  130 . Thus only the right side of the image sensor is used. This cuts the total resolution in half when the image sensor is operated in charge multiplication mode. This still provides an image sensor with a cost advantage over the specially designed image sensor of  FIG. 1  because the full resolution image sensor of  FIG. 3  is sold to other market segments that do not require charge multiplication. The larger volume of sales allows for lower net cost.  
         [0021]      FIG. 7  shows an alternative embodiment of the standard image sensor shown in  FIG. 3  that is also reconfigured by the present invention. This image sensor  200  has an array of photodiodes  210  adjacent to vertical CCDs  215 . There are left  230  and right  240  horizontal CCDs with their corresponding left  220  and right  250  output amplifiers. One of the primary differences between the image sensor  200  of  FIG. 7  and the image sensor  100  of  FIG. 3  is the fast dump row  160  is split into two halves  270  and  260 . This is done so that when the left horizontal CCD  230  is operated in charge multiplication mode the left half fast dump  270  would be activated to prevent charge from transferring from the left half vertical CCDs  215  into the left horizontal CCD  230 . The right half fast dump  260  would be deactivated. Therefore only the right half of each row can be transferred in to the right horizontal CCD  240 . Now the right horizontal CCD  240  only has to be clocked for half the number of normal clock cycles. The number of clock cycles used is only enough to move the row of charge horizontally into the charge multiplying register  230 . When the entire row is contained in the left half horizontal CCD  230 , the next row may be transferred into the right half horizontal CCD  240  at which point there will be two rows of charge stored in the total length of the horizontal CCDs  230  and  240 .  
         [0022]      FIG. 8  shows a digital camera  310  using an image sensor  100  or  200  in the charge-multiplying mode described above. The camera  310  would also include a means of switching between mode  1  which is full resolution normal readout without charge multiplication, and mode  2  which is half resolution readout with charge multiplication.  
         [0023]     The invention has been described with reference to a preferred embodiment. However, it will be appreciated that variations and modifications can be effected by a person of ordinary skill in the art without departing from the scope of the invention.  
       PARTS LIST  
       [0000]    
       
           10  image sensor  
           20  pixel arrays  
           30  horizontal serial CCD  
           40  charge multiplying CCD  
           50  output amplifier  
           60  gate dielectric  
           70  silicon substrate  
           80  charge packets/electrons  
           100  image sensor  
           110  photodiodes  
           115  parallel vertical CCDs  
           120  left output amplifier  
           130  left horizontal CCD  
           140  right horizontal CCD  
           150  right output amplifier  
           160  fast dump row  
           200  image sensor  
           210  photodiodes  
           215  vertical CCDs  
           220  left output amplifier  
           230  left horizontal CCD  
           240  right horizontal CCD  
           250  right output amplifier  
           260  right half fast dump row  
           270  left half fast dump row  
           310  digital camera  
           400  insulating dielectric  
           410  n-type buried channel  
           420  p-type well or substrate  
           430  extra light p-type implant  
          H 1  control gates  
          H 2  control gates  
          H 3  control gates  
          H 4  control gates  
          H 1 S charge transfer voltage control input/gate  
          H 1 B charge transfer voltage control input/gate  
          H 2 S charge transfer voltage control input/gate  
          H 2 B charge transfer voltage control input/gate