Abstract:
A leakage current detection circuit is provided comprising a first field effect transistor, the transistor configured to be biased to provide a leakage current, and a first current mirror in communication with the transistor operable to detect the leakage current from the transistor when the transistor is biased to provide the leakage current.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority to provisional patent application Ser. No. 60/587,668, filed Jul. 14, 2004, the entirety of which is hereby incorporated by reference herein.  
         [0002]     This application is related to the following commonly-assigned, co-pending U.S. patent applications Ser. No. 10/840,098, entitled “Dynamic Random Access Memory Cell Leakage Current Meter” filed on May 6, 2004; and patent application Ser. No. 10/696,291, entitled “Circuit and Method for Self-Refresh of DRAM Cell”, filed on Oct. 29, 2003, the contents of each being fully incorporated by reference herein. 
     
    
     FIELD OF THE INVENTION  
       [0003]     The present invention is related to semiconductor devices and more specifically to devices and methods of measuring leakage current in transistor devices.  
       BACKGROUND OF THE INVENTION  
       [0004]     Although used extensively in integrated circuits, CMOS devices are not ideal switches for logic functions because there exists a small leakage current. Various forms of leakage current are shown in  FIG. 1   a - 3   b.    FIGS. 1   a  and  1   b  illustrate the generation of “sub-threshold” leakage current between the source and drain nodes that exists even when the transistor is in the “off” state when the voltage between gate and source node (V GS ) is lower than a threshold voltage (V T ) of the transistor, i.e., when |V GS |&lt;|V T |. Generally, the sub-threshold current depends strongly on the voltage difference between drain and source nodes (V DS ), the threshold voltage (V T ) and temperature.  
         [0005]     Another leakage source also exists, as shown in  FIGS. 2   a  and  2   b,  between the drain/source nodes and the bulk of a MOS device. This current, referred to as a junction leakage current, strongly depends on the source-bulk voltage (V SB ) and the drain-bulk voltage (V DB ), the source/drain implant and the junction temperature.  
         [0006]     A third leakage current, as shown in  FIGS. 3   a  and  3   b,  is gate node leakage current that exists between the gate to bulk node and the gate to source/drain nodes. This gate node leakage current, which is referred to as gate leakage current, depends on the cross voltage between gate and bulk nodes (V GB ), the cross voltage between gate and source/drain nodes (V GS /V GD ) and the gate oxide thickness. These leakages may exist singularly or, more typically, concurrently in a MOS transistor and effect the performance of the devices fabricated from the MOS transistors.  
         [0007]     Hence, there is a need in the industry for a current monitoring means that can measure these leakage currents individually or in combination.  
       SUMMARY OF THE INVENTION  
       [0008]     A leakage current detection circuit is provided comprising a first field effect transistor, the transistor configured to be biased to provide a leakage current, and a first current mirror in communication with the transistor operable to detect the leakage current from the transistor when the transistor is biased to provide the leakage current.  
         [0009]     The above and other features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention that is provided in connection with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0010]     The accompanying drawings illustrate preferred embodiments of the invention, as well as other information pertinent to the disclosure, in which:  
         [0011]      FIGS. 1   a  and  1   b  illustrate sub-threshold leakage current associated with conventional n-channel and p-channel MOS devices, respectively;  
         [0012]      FIGS. 2   a  and  2   b  illustrate junction leakage current associated with conventional n-channel and p-channel MOS devices, respectively;  
         [0013]      FIGS. 3   a  and  3   b  illustrate gate leakage current associated with conventional n-channel and p-channel MOS devices, respectively;  
         [0014]      FIGS. 4   a  and  4   b  illustrate two exemplary leakage current detectors for determining sub-threshold leakage current associated with a conventional n-channel MOS device;  
         [0015]      FIGS. 5   a  and  5   b  illustrate two exemplary leakage current detectors for determining sub-threshold leakage current associated with a conventional p-channel MOS device;  
         [0016]      FIGS. 6   a  and  6   b  illustrate exemplary current detectors for determining junction leakage current associated with conventional n-channel and p-channel MOS devices, respectively;  
         [0017]      FIGS. 7   a  and  7   b  illustrate exemplary current detectors for determining gate node leakage current associated with conventional n-channel and p-channel MOS devices, respectively;  
         [0018]      FIGS. 8   a  and  8   b  illustrate exemplary current detectors for determining total leakage current associated with conventional n-channel and p-channel MOS devices, respectively; and  
         [0019]      FIG. 9  illustrates an exemplary current detector combining the leakage current detectors shown in the figures herein. 
     
    
       [0020]     It is to be understood that these drawings are solely for purposes of illustrating the concepts of the invention and are not intended as a definition of the limits of the invention. The embodiments shown in herein and described in the accompanying detailed description are to be used as illustrative embodiments and should not be construed as the only manner of practicing the invention. Also, the same reference numerals, possibly supplemented with reference characters where appropriate, have been used to identify similar elements.  
       DETAILED DESCRIPTION  
       [0021]      FIGS. 4   a  and  4   b  illustrate two embodiments,  400 ,  450 , respectively, of a current detector for measuring, determining and/or extracting sub-threshold leakage current for n-channel MOS devices, such as MOS transistor  110 . Referring first to  FIG. 4   a,  MOS transistor  110  is connected at its source terminal  112  to current mirror  415 , which, in one embodiment, comprises two MOS transistors  420 ,  425 , electrically connected at their respective gate nodes  421 ,  426 . As is also illustrated, the source node  440  of transistor  420  is electrically connected to the commonly connected gate nodes  421 ,  426  of transistors  420 ,  425 . In this illustrated case, the gate node  116  of n-channel MOS device  110  is biased at a voltage V SS  that maintains device  110  in a “turned-off” state, as V GS  is less than or equal to zero voltage (0V). V SS  should be less than Vt, and preferably ground (0V) or close to ground. The cross voltage, V DS , of device  110  is the difference between the voltage at the drain node  114  and the source node  112 , i.e., V DDP −V N1 , where V N1  is the voltage of source node  440  of device  420 . As one skilled in the art would recognize, the voltage at source node  440  is maintained around the threshold voltage of device  420  by properly choosing the size of NMOS device  420  such that it operates within its saturation region. As is known in the art, the size of NMOS device  425  may be selected as a multiple of NMOS device  420  in order to amplify or magnify the extracted sub-threshold leakage current to provide current Inoff representative of the leakage current of NMOS  110 .  
         [0022]     In this embodiment  400 , only sub-threshold leakage current is measured as the cross voltages V GS  and V BS  of device  110  are small such that the contribution of junction leakage and gate leakage currents is negligible. Voltage V DDP  coupled to drain terminal  114  of NMOS  110  may be set to V DD , the power supply voltage, or selected to provide a desired V DS  across NMOS  110 , i.e., a power supply voltage greater than VDD could be provided to enhance sub-threshold leakage current.  
         [0023]     he embodiment  450  of  FIG. 4   b  is identical to embodiment  400  of  FIG. 4   a  only embodiment  450  illustrates that device  410  may alternatively be held in a “turned-off” condition by maintaining gate node  116  at the same voltage as the source node  112 .  
         [0024]      FIGS. 5   a  and  5   b  illustrate two embodiments  500 ,  550 , respectively, of a current detector for extracting sub-threshold leakage current for p-channel MOS devices. Referring to  FIG. 5   a,  in this illustrated embodiment, the source node  162  of PMOS device  160  is connected to current monitor  515 . Current monitor  515  comprises two p-channel MOS devices  520 ,  525  electrically connected at their respective gate nodes  521 ,  526 . Gate node  166  of p-channel device  160  is biased at a voltage V DD  so that device  160  is kept in an “off state,” as V GS  is greater than or equal to zero volts (0V). The cross voltage V DS  of device  160  is determined as V N1 −V SS , where the voltage V N1  at node  540  is in the order of (V DDP −V TP ), where V TP  the threshold voltage of PMOS  520 . Voltage V DDP  may be selected as V DD  or chosen to meet a required value for V DS  of device  160 . The operation of mirror  515  is similar to that described above with respect to mirror  415  shown in  FIG. 4   a  and is not repeated. The sub-threshold current of PMOS  160  is reflected in current Ipoff.  
         [0025]     With respect to embodiment  550  of  FIG. 5   b,  the gate node  166  and the source node  162  of device  160  are electrically connected to node  540  in a manner similar to that described with regard to the embodiment  450  of  FIG. 4   b.  As with the embodiment of  FIG. 5   a,  the gate node  166  of embodiment  550  is thereby set at a voltage that maintains device  160  of embodiment  550  in a “turned-off” condition.  
         [0026]      FIGS. 6   a  and  6   b  illustrate two embodiments  600 ,  650 , respectively, of a detector for measuring, determining and/or extracting junction leakage current for n-channel and p-channel MOS devices,  110 ,  160 , respectively. Referring first to  FIG. 6   a,  NMOS device  110  is connected to a PMOS based current mirror  515 , as described above and shown in  FIGS. 5   a  and  5   b.  To extract junction leakage current, the terminal of device  110  are biased to create cross voltages between the bulk and source and bulk and drain, and preferably to eliminate gate node leakage. In one embodiment, the bulk material of transistor  110  is coupled to voltage V SS , which is preferably at a ground or near ground, i.e., 0 volts, and source node  112  is electrically connected to drain node  114 , which is coupled to node  540 , thereby providing cross voltages V BS  and V BD . Further, gate node  116  is maintained at a voltage V DDP  to eliminate the gate current contribution to node  540 . Because the voltage at node  540  equals V DDP −V TP , the gate to source and gate to drain voltages of transistor  110  are very small. As noted, this structure can establish the cross voltage on the junction of NMOS  110 , including V SB  between node  112  and bulk node  118  and V DB  between node  114  and bulk node  118 , to collect the junction leakage contributed from the source, drain and bulk. The representative current Injun is provided by current mirror  515  in embodiment  600 .  
         [0027]     With regard to the embodiment  650  of  FIG. 6   b,  the drain terminal  164  of device  160  is electrically connected to an NMOS-based current mirror  415 , as described above and shown in  FIGS. 4   a  and  4   b.  The bulk terminal  168  of device  160  is biased at voltage V DDP  and gate node  166  is set at a lower voltage, preferably, at ground or near ground (e.g., V SS ) to limit the gate node leakage current. Source node  162  is electrically connected to drain node  164  and preferably also to ground or near ground (e.g., V SS ). This structure establishes the proper cross voltage on the junction of PMOS  160 , including V SB  between node  162  and node  168  and V DB  between node  164  and node  168 , to collect the junction leakage contributed from the source, drain and bulk. The representative current Ipjun is provided by current mirror  415  in embodiment  650 .  
         [0028]      FIGS. 7   a  and  7   b  illustrate two embodiments  700 ,  750 , respectively, of a detector for measuring, determining and/or extracting gate leakage current for n-channel and p-channel MOS devices,  110 ,  160  respectively.  FIG. 7   a  illustrates gate node  116  of NMOS  114  is electrically connected to mirror circuit  515 , and source node  112 , drain node  114  and bulk node  118  are electrically connected. A voltage V SS  is applied to the common source, drain and bulk nodes. Cross voltages V GS , V GD  and V GB  are established such that the leakage current collected at the gate node is contributed from the source, drain and bulk of the NMOS  110 . In this case there is little or no contribution of junction or sub-threshold leakage current to effect the determination of gate leakage current reflected as current Ingate by mirror  515  because there are no cross voltages between the drain, source and bulk nodes, which are electrically coupled together. The gate leakage current is shown as Ingate provided by PMOS current mirror circuit  515 .  
         [0029]      FIG. 7   b  illustrates a similar embodiment  650  for determining gate leakage current for PMOS device  160 . In this embodiment, the gate terminal  166  is coupled to an NMOS current mirror circuit  415  at node  440 . The bulk node  168 , source node  162  and drain node  164  are electrically coupled together and to voltage V DDP  to establish the cross voltages V GS , V GD  and V GB  such that the leakage current collected at the gate node is contributed from the source, drain and bulk of the PMOS  160 . The gate leakage current is shown as Ipgate by NMOS current mirror circuit  415 .  
         [0030]      FIGS. 8   a  and  8   b  illustrate two embodiments  800 ,  850 , respectively, of the detectors for measuring, determining and/or detecting total leakage current for n-channel and p-channel MOS devices,  110 ,  160  respectively. With regard to  FIG. 8   a,  drain node  114  of n-channel MOS device  110  is connected to current mirror  515  at node  540 , which has been described above with respect to  FIGS. 5   a,    5   b,    7   a  and  7   b.  Gate node  116 , source node  112  and bulk node  118  are electrically connected to a common voltage. In one embodiment, this voltage may be a zero voltage, i.e., ground, or a voltage V SS . Voltage V SS  may be a voltage lower than V DDP , preferably close to ground. This structure can establish the cross voltage V DS  between drain node  114  and source node  112  needed to collect sub-threshold leakage current, V DG  between drain node  114  and gate node  116  to collect gate leakage current, and V DB  between drain node  114  and bulk node to collect the junction leakage current. The leakage current from the gate node, bulk node and source node are provided at node  540 . This total leakage current is reflected in current Inleak by mirror  515   
         [0031]     With regard to  FIG. 8   b,  drain node  114  of p-channel MOS device  160  is connected to current mirror  415 , which has been described with regard to  FIGS. 4   a,    4   b,    6   a  and  6   b.  Gate node  166 , source node  162  and bulk node  168  are electrically connected to a common voltage. In one embodiment, this voltage may be a source voltage such as V DD  or V DDP . Voltage V DDP  may be a power supply voltage higher than V SS . This structure can establish the cross voltage V DS  between drain node  164  and source node  162  to collect sub-threshold leakage, V DG  between drain node  164  and gate node  166  to collect gate leakage, and V DB  between drain node  164  and bulk node  168  to collect junction leakage, the total of which is reflected in current Ipeak by mirror  415 .  
         [0032]      FIG. 9  illustrates an exemplary embodiment  900  of a leakage current detector combining two current detectors as discussed above, specifically current detectors  450  shown in  FIG. 4   a  and  850  shown in  FIG. 8   b.  In this embodiment, current monitor  900  may determine a total leakage current (Ipleak) associated with monitor  850  and/or sub-threshold junction leakage current (Inoff) provided by monitor  450 . The combined current may be recovered as Ipleak+Inoff. In one embodiment, the combined current may be used as a reference current for the Current Source of  FIG. 9 , which may comprise a constant current source, as should be familiar to those in the art. Although a single embodiment of a combined current leakage current detector is shown, those skilled in the art would have sufficient knowledge from the information provided herein to formulate addition embodiments of current monitors, similar to that shown in  FIG. 9 , using either the individual monitors shown herein in  FIGS. 4   a - 8   b  or other current monitors.  
         [0033]     The current detectors described herein allow for the detection of the various leakage currents either separately or in total. The circuit approach is also very flexible, allowing for various combinations of the circuit detectors as desired. The circuit detectors can be utilized to provide integrated circuit (IC) operating environment information, such as supply voltages, process deviations and temperature. For example, junction leakage is very sensitive to temperature and gate leakage current is indicative of the gate oxide thickness of device. Also sub-threshold current can be used as indicative of supply voltage. Further, the detectors can be used as static power dissipation meters of a system in nature. The static power of a system is contributed from “off state” NMOS and PMOS devices. Therefore, the sub-threshold current detector can be used to monitor the static power. The current monitor circuit could be used in test ICs and/or in production ICs.  
         [0034]     Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention that may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.