Abstract:
A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority under 35 U.S.C. §119 from Korean Patent Application 10-2007-0097644, filed on Sep. 28, 2007, the contents of which are hereby incorporated by reference in their entirety for all purposes as if fully set forth herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to a multiprocessor system, and more particularly, but without limitation, to a direct access boot utility in a multipath architecture. 
     2. Description of the Related Art 
     Some electronic instruments, such as portable multimedia players (PMPs), handheld phones (HHPs), and personal digital assistants (PDAs) include multiple processors within one system to achieve high-speed operation. In such a system, a semiconductor memory device must be adapted for multiprocessor access. For example, the memory device may have multiple access ports, and it may be required to simultaneously input/output data through the multiple access ports. 
     One type of semiconductor memory device having two access ports is called a dual-port memory. A known dual-port memory used for image processing applications includes a random access memory (RAM) port accessible in a random sequence and a sequential access memory (SAM) port accessible only in a serial sequence. Dual-port memory has limited application, however. 
     A Dynamic Random Access Memory (DRAM) that does not employ an SAM port, and for which a shared memory area is accessible by processors through multiple access ports, is called herein a multiport semiconductor memory device or multipath-accessible semiconductor memory device to distinguish from the dual-port memory. An example of a conventional art multiport semiconductor memory is disclosed in U.S. Publication No. 2003/0093628. As disclosed therein, a memory array is constructed of first, second and third portions. The first portion of the memory array is accessed only by a first processor, the second portion is accessed only by a second processor, and the third portion is a shared memory area accessed by the first and the second processors. Some known multiprocessor systems include a multiport DRAM memory device and a single flash memory device. 
     Multiprocessor systems present many technical challenges, however. One such issue is multiprocessor access to a single flash memory device, for example, to quickly obtain boot code in each of the multiple processors. For this and other reasons, improved multiprocessor architectures are needed. 
     BRIEF SUMMARY OF THE INVENTION 
     Embodiments of the invention provide a multiprocessor system capable of simplifying a booting procedure and increasing a booting speed in an initial boot of the multiprocessor system. 
     According to an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention will become more fully understood from the detailed description below and the accompanying drawings, which are given by way of illustration only, and wherein: 
         FIG. 1  is a block diagram of multiprocessor system; 
         FIG. 2  is a block diagram of multiprocessor system having a direct access boot operation according to an embodiment of the invention; 
         FIG. 3  is a block diagram further detailing the multiprocessor system in  FIG. 2 , according to an embodiment of the invention; 
         FIG. 4  is a block diagram of the multiport semiconductor memory device shown in  FIG. 2 , according to an embodiment of the invention; 
         FIGS. 5A and 5B  are diagrams of the control unit shown in  FIG. 4 , and timings for operation thereof, according to an embodiment of the invention; 
         FIG. 6  is a memory map of the multiport semiconductor memory device and internal register shown in  FIG. 4 , according to an embodiment of the invention; 
         FIG. 7  is a detailed block diagram of a portion of the multiport semiconductor memory device shown in  FIG. 4 , according to an embodiment of the invention; and 
         FIG. 8  is a circuit diagram of the address multiplexer shown in  FIG. 7 , according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the invention now will be described more fully hereinafter with reference to the drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a block diagram of a multiprocessor system. The multiprocessor system illustrated therein and described below may be suitable, for example, in a mobile communication system. 
     As shown in  FIG. 1 , the multiprocessor system includes first and second processors  100  and  200 , a multiport DRAM  400 , and a flash memory  300 . The multiport DRAM  400  is coupled to the first and second processors  100  and  200 , and the flash memory  300  is coupled to the second processor  200 . The first processor  100  may function, for example, as a communication signal Modulator/Demodulator (MODEM), and the second processor  200  may execute a game or other high-level application program. 
     The flash memory  300  may be an NOR flash memory or a NAND flash memory. NOR flash memory and NAND flash memory are nonvolatile memory devices constructed of MOS transistors with floating gates. Such nonvolatile memory devices are adapted to store instructions or data that must not be deleted even if power is turned off. Such instructions or data may be or include, for example, boot codes or other preservation data. 
     The multiport DRAM  400  functions as a main memory for data associated with processors  100  and  200 . The multiport DRAM includes two ports (not shown). A first port (not shown) is coupled to system bus B 1  and a second port (not shown) is coupled to system bus B 2 . The multiport DRAM  400  is coupled to the first processor  100  via the system bus B 1 , and is further coupled to the second processor  200  via the system bus B 2 . 
     In the multiport DRAM  400  of  FIG. 1 , a memory cell array  14  includes four memory areas  10 ,  11 ,  12  and  13 . The first bank  10  may only be accessed by the first processor  100  via system bus B 1 , and the third and fourth banks  12  and  13  may only be accessed by the second processor  200  via the system bus B 2 . The second bank  11  may be accessed by the first processor  100  via the system bus B 1  and also by the second processor  200  via the system bus B 2 . In other words, in the multiport DRAM  400 , the second bank  11  may be a shared memory area, and the first, third and fourth banks  10 ,  12  and  13  may be dedicated memory areas. Each of the first, second, third, and fourth banks  10 ,  11 ,  12 , and  13  may include, for instance, 64 Mb, 128 Mb, 256 Mb, 512 Mb or 1024 Mb of memory. 
     Link L 1  couples the first processor  100  with the second processor  200 , and bus B 3  couples the flash memory  300  to the second processor  200 . 
     In the multiprocessor system illustrated in  FIG. 1 , the first processor  100  is not directly linked to the flash memory  300 . Accordingly, there are at least three ways the multiprocessor system can be configured to supply the boot code to the first processor  100 . First, second processor  200  may read the boot code from the flash memory  300  and transfer the boot code to the shared memory area  11 . Then the first processor  100  may read the boot code from the shared memory area  11 . Second, the second processor  200  could be configured to read the boot code from the flash memory  300  and transmit the boot code to the first processor  100 . Third, the first processor  100  could include or be coupled to its own flash memory (not shown), for example on-chip non-volatile memory, or a dedicated non-volatile memory device, that contains boot code for the first processor  100 . 
     In the first and second case, the boot of the first processor  100  may be unreliable due to the time delay in routing boot code for the first processor  100  through the second processor  200 . The third case may be acceptable for at least some applications so long as device or board-level packaging allows for the addition of non-volatile memory that is dedicated to the first processor  100 . 
       FIG. 2  is a block diagram of multiprocessor system having a direct access boot operation according to an embodiment of the invention. The multiprocessor system in  FIG. 2  is configured like the multiprocessor system in  FIG. 1  except as described below. 
     In the multiprocessor system of  FIG. 2 , the first processor  100  is directly connected to the flash memory  300  through a bus B 4 . Thus, in an initial boot, the first processor  100  directly receives boot code through the flash memory  300 , and booting speed is increased compared with boot-up processes that route boot code for the first processor  100  through the second processor  200 . In addition, in the multiprocessor system illustrated in  FIG. 2 , the link L 1  is omitted. Instead, data can be transmitted between the first processor  100  and the second processor  200  via the multiport DRAM  400 . 
       FIG. 3  is a block diagram further detailing the multiprocessor system in  FIG. 2 , according to an embodiment of the invention. In the illustrated example, the second processor  200  is an Application-Specific Integrated Circuit (ASIC). As illustrated in  FIG. 3 , the flash memory  300  may be divided into multiple areas. A boot code storage area  310  is dedicated to the first processor  100 , and an ASIC storage area  320  is dedicated to the second processor  200 . The first processor  100  can indirectly access data in the storage area  320  via a DRAM interface in a normal operating mode. The boot code storage area  310  can be further divided into a first boot code (BC) storage area  312 , a second boot code (BC) storage area  314 , and an operating system (OS) storage area  316 . 
     In  FIG. 3 , the portion of the multiprocessor system that includes the multiport DRAM memory device  400 , the second processor  200 , and the flash memory  300  forms a Memory Link Architecture (MLA)  500 . The first processor  100  is outside of the MLA  500 . Thus, the first processor  100  directly accesses the boot code storage area  310  of the flash memory device  300  via the bus B 4 . Such access advantageously improves the speed and reliability of a booting operation in the first processor  100 . In embodiments of the invention, bus B 4  is only used for booting operations; thereafter, the processor  100  accesses data in the multiport DRAM device  400  via bus B 1  in normal operation. 
       FIG. 4  is a block diagram of the multiport semiconductor memory device shown in  FIG. 2 , according to an embodiment of the invention. As shown therein, the multiport semiconductor memory device  400  includes at least one shared memory area  11 . The first processor  100  can access the shared memory area  11  through the first port  60 , and the second processor  200  can access the shared memory area  11  through the second port  61 . A dedicated memory area A,  10  is accessed by first processor  100  through the first port  60 . Dedicated memory areas B,  12  and  13  are accessed by second processor  200  through the second port  61 . 
     In  FIG. 4 , internal register  50  provides an interface to the first and second processors  100  and  200 , and may be or include, for instance, a flip-flop, data latch or SRAM cell. The internal register  50  includes a semaphore (SMP) area  51 , first mailbox area (MA→B)  52 , second mailbox area (MB→A)  53 , check bit (CHK) area  54 , and reserve (Rvd) area  55 . 
     The SMP  51  controls access to the shared memory area  11 . The first and second mailboxes  52  and  53  store, for example, a shared memory address, data, or commands being transmitted between processors. For example, the first mailbox area  52  may store data and commands being sent from the first processor  100  to the second processor  200 , and the second mailbox area  53  may store data and commands being sent from the second processor  200  to the first processor  100 . 
     A control unit  30  couples the shared memory area  11  to one of the first and second processors  100  and  200 . A signal line R 1  connected between the first port  60  and the control unit  30  transfers a first external signal applied through bus B 1  from the first processor  100 . A signal line R 2  connected between the second port  61  and the control unit  30  transfers a second external signal applied through bus B 2  from the second processor  200 . The first and second external signals may include a row address strobe signal RASB, write enable signal WEB and bank selection address BA individually applied through the first and second ports  60  and  61 . 
     Signal line C 1  transfers a path decision signal MA from the control unit  30  to the multiplexer (MUX)  40  to couple the shared memory area  11  to the first port  60 . Signal line C 2  transfers a path decision signal MB from the control unit  30  to the MUX  41  to couple the shared memory area  11  to the second port  61 . The first path unit  20  couples the MUX  40  and the dedicated memory area  10  to the first port  60 . The second path unit  21  couples the MUX  41  and dedicated memory areas  12  and  13  to the second port  61 . 
       FIGS. 5A and 5B  are diagrams of the control unit shown in  FIG. 4 , and timings for operation thereof, according to an embodiment of the invention. As shown therein, a gating part  30   a  receives a bank selection address BA_A, BA_B, a write enable signal WEB_A, WEB_B and a row address strobe signal RASB_A, RASB_B from the corresponding first and second ports  60  and  61 . The gating part  30   a  outputs gating signals PA and PB. 
     When a row address strobe signal RASB is received from one of the ports, the gating part  30   a  assigns the shared memory area  11  to the corresponding port. When the row address strobe signals RASB_A and RASB_B are applied simultaneously, the gating part  30   a  provides access to the shared memory area  11  based on a predetermined priority specification. 
     The control unit  30  also includes inverters  30   b ,  30   c ,  30   j  and  30   k , a latch LA constructed of NAND gates  30   d  and  30   e , delay devices  30   f  and  30   g , and NAND gates  30   h  and  30   i , coupled as illustrated in  FIG. 5A . The path decision signal MA is a delayed and latched variant of the gating signal PA. The path decision signal MB is a delayed and latched variant of the gating signal PB. An example of such relationship is illustrated in the timing diagram of  FIG. 5B . 
       FIG. 6  is a memory map of the multiport semiconductor memory device and internal register shown in  FIG. 4 , according to an embodiment of the invention. As shown in  FIG. 6 , the areas  51 - 55  of the internal register  50  may be enabled in common by a specific row address, and may be individually accessed by an applied column address. For example, when a row address 0×7FFFFFFFh˜0×8FFFFFFFh associated with area  121  of the shared memory area  11  is received in the multiport DRAM  400 , area  121  of the shared memory area  11  is disabled, and the internal register  50  is enabled. As a result, the semaphore area  51  and mailbox areas  52  and  53  are accessed by using a direct address mapping method. A command associated with a disabled address is decoded and mapped to a DRAM internal register. The semaphore area  51 , the first mailbox area  52  and the second mailbox area  53  may be each assigned 16 bits, and the check bit area  54  may be assigned 4 bits. Other register sizes could also be used, according to design choice. 
       FIG. 7  is a detailed block diagram of a portion of the multiport semiconductor memory device shown in  FIG. 4 , according to an embodiment of the invention.  FIG. 8  is a circuit diagram of the address multiplexer shown in  FIG. 7 , according to an embodiment of the invention.  FIG. 8  is described first. 
       FIG. 8  illustrates an example of the row address multiplexer  71  and column address multiplexer  70  shown in  FIG. 7 . The same circuit can function as either a row address multiplexer or a column address multiplexer, according to the input signal. The address multiplexer includes two clocked-CMOS inverters constructed of PMOS transistors P 1 -P 4  and NMOS transistors N 1 -N 4 , and an inverter latch LA 1  constructed of inverters INV 1  and INV 2 . The clocked CMOS inverters each receive an address (for example A_CADD and B_CADD, in the case of a column address multiplexer) at an input port, and select one of two inputs according to a logic state of the path decision signals MA and MB. The address multiplexer outputs the selected address (for example, a selected column address SCADD). An NMOS transistor N 5  and a NOR gate NOR 1  are adapted to provide a discharge path between an input terminal of the inverter latch LA 1  and ground. Inverters IN 1  and IN 2  are adapted to invert a logic state of the path decision signals MA and MB. 
     As an example of operation, when the path decision signal MA is applied with a logic low level, column address A_CADD received through the first port  60  is inverted through an inverter constructed of PMOS transistor P 2  and NMOS transistor N 1 , is again inverted through the inverter INV 1 , and then is output as the selected column address SCADD. In this case, the path decision signal MB is applied with a logic high level. Thus column address B_CADD received through the second port  61  is not provided to an input terminal of the latch LA 1  since the inverter constructed of PMOS transistor P 4  and NMOS transistor N 3  has an inactive state. As a result, column address B_CADD, is not output as the selected column address SCADD. When an output of the NOR gate NOR 1  becomes a high level, the NMOS transistor N 5  is turned on and a logic level latched to the latch LA 1  is set to a low level. 
     Turning now to the portion of the multiport DRAM device  400  illustrated in  FIG. 7 , a memory cell MC ( 4 ) is a memory cell belonging to the shared memory area  11  in  FIGS. 2 ,  4 , and  6 . The S-MUX  40  and S-MUX  41  are disposed symmetrically on the shared memory area  11 . Likewise, an input/output sense amplifier (IOSA) and driver (DRV)  22  is disposed near the S-MUX  40 , and an IOSA and DRV  23  is disposed near the S-MUX  41 . 
     Within the shared memory area  11 , the memory cell MC ( 4 ) includes an access transistor AT and a storage capacitor C. The memory cell MC ( 4 ) is connected to a word line WL and bit line BLi. In particular, the word line WL is disposed between a gate of access transistor AT of the memory cell MC ( 4 ) and a row decoder  75 . The row decoder (RD)  75  applies a decoded row signal to the word line WL or the internal register  50  in response to a selection row address SADD of the row address multiplexer  71 . A bit line BLi constituting a bit line pair is coupled to a drain of the access transistor AT and a column selection transistor T 1 . A complementary bit line BLBi is coupled to a column selection transistor T 2 . PMOS transistors P 1  and P 2  and NMOS transistors N 1  and N 2  coupled to the bit line pair BLi, BLBi constitute a bit line sense amplifier  5 . Sense amplifier driving transistors PM 1  and NM 1  each receive a corresponding drive signal LAPG, LANG, and drive the bit line sense amplifier  5 . A column selection gate  6  constructed of the column selection transistors T 1  and T 2  is coupled to a column selection line CSL transferring a decoded column signal of the column decoder  74 . The column decoder  74  outputs a decoded column signal to the column selection line CSL and the internal register  50  in response to a selected column address SCADD of the column address multiplexer  70 . 
     With further reference to  FIG. 7 , a local input/output line pair LIO, LIOB is coupled to a first multiplexer  7 . When transistors T 10  and T 11  included in the first multiplexer  7  are turned on in response to a local input/output line control signal LIOC, the local input/output line pair LIO, LIOB is coupled to a global input/output line pair GIO, GIOB. Then, data of the local input/output line pair LIO, LIOB is transferred to the global input/output line pair GIO, GIOB in a data read operating mode. On the other hand, write data applied to the global input/output line pair GIO, GIOB is transferred to the local input/output line pair LIO, LIOB in a data write operating mode. The local input/output line control signal LIOC may be a signal generated in response to a decoded signal output from the row decoder (RD)  75 . 
     When the path decision signal MA output from control unit  30  has an active state, read data transferred to the global input/output line pair GIO, GIOB is transferred to the input/output sense amplifier (IOSA) and driver  22  through the S-MUX  40 . The IOSA  22  amplifies data whose level has weakened according to the transfer procedure through several data paths. Read data output from the IOSA  22  is transferred to the first port  60  through MUX and driver  26 . At this same time, the path decision signal MB is in an inactive state. Thus the S-MUX  41  is disabled and the second processor  200  cannot access the shared memory area  11 . However, in this case, the second processor  200  can still access the dedicated memory areas  12  and  13  through the second port  61 . 
     When path decision signal MA output from the control unit  30  has an active state, write data received through the first port  60  is transferred to the global input/output line pair GIO, GIOB, sequentially passing through the MUX and driver  26 , IOSA and driver  22 , and the S-MUX  40 . When the multiplexer  7  is activated, the write data is transferred to local input/output line pair LIO, LIOB and then is stored in a selected memory cell, for example MC( 4 ). 
     An output buffer and driver  60 - 1  and input buffer  60 - 2  shown in  FIG. 7  may correspond to or be included in the first port  60 . An output buffer and driver  61 - 1  and input buffer  61 - 2  shown in  FIG. 7  may correspond to or be included in the second port  61 . 
     The first and second processors  100  and  200  commonly use circuit devices and lines that are adapted between global input/output line pair GIO, GIOB and memory cell MC ( 4 ) in an access operation, and independently use input/output related circuit devices and lines adapted between the corresponding port and S-MUX devices  40  and  41 . 
     Accordingly, flash memory  300  directly provides the boot code in a boot operation of first processor  100 , and is accessed by the second processor  200  in a normal operating mode. In the normal operating mode, the first processor  100  can indirectly access data stored in the flash memory through the multiport DRAM device  400  with the assistance of the second processor  200 . 
     In one embodiment of the invention, the second processor  200  is configured to boot first from the flash memory  300  upon power-up. At a first predetermined time, the multiport DRAM device  400  outputs a reset enable signal to the first processor  100 . In response, the first processor  100  then boots directly from the flash memory  300  (i.e., without routing the boot code associated with the first processor through the second processor). At a second predetermined time, the multiport DRAM device  400  outputs a reset disable signal to the first processor  100 . 
     In one embodiment, the first and/or the second predetermined time may be associated with the start (or a predetermined delay from the start) of a boot sequence associated with the second processor. In the alternative, or in combination, the first and/or the second predetermined time may be associated with the completion (or a predetermined delay from the completion) of a boot sequence associated with the second processor. 
     It will be apparent to those skilled in the art that modifications and variations can be made in the present invention without deviating from the spirit or scope of the invention. For example, the configuration for a shared memory bank of multiport semiconductor memory device or the configuration and access method of an internal register circuit may be varied, according to design choice. In addition, the multiprocessor system architectures described herein are applicable to multiprocessor systems having three or more processors. Moreover, in the multiprocessor system, one or more processors may be a microprocessor, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a micro-controller, a reduced-command set computer, a complex command set computer, or the like. Furthermore, the scope of the invention is not limited to any special combination of processors or applications used in the above-described embodiments. And although embodiments of the invention illustrated nonvolatile memory with reference to flash memory devices and volatile memory with reference to DRAM devices, the invention could be adapted to other memory device types. Thus, it is intended that the present invention cover any such modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.