Abstract:
A hiccup-mode short circuit protection circuit and method for a linear voltage regulator using a FET pass transistor uses the capacitance of the pass transistor&#39;s gate as a timing element. The regulator&#39;s output voltage is monitored, and when it droops below a voltage indicative of a short-circuit condition, the regulator&#39;s drive signal is disconnected from the pass transistor. While the short-circuit condition persists, a first current is provided to charge the pass transistor&#39;s gate capacitance. When the gate voltage rises above a first predetermined threshold, a second current is provided to further charge the gate capacitance. When the gate voltage rises above a second predetermined threshold, the gate capacitance is discharged. The gate capacitance is cyclically charged and discharged in this way unless the output voltage rises to indicate that the short-circuit condition has cleared, in which case the regulator&#39;s drive signal is restored to the pass transistor&#39;s gate. To reduce average power consumption, the magnitudes of the first and second currents and the values of the threshold voltages are chosen such that the pass transistor&#39;s ON duty cycle is about 10%.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the field of linear voltage regulators, and particularly to short-circuit protection circuits and methods for such regulators. 
     2. Description of the Related Art 
     A linear voltage regulator includes an error amplifier and a “pass” transistor. The error amplifier inputs a setpoint voltage and a feedback signal representing the regulator&#39;s output voltage, and outputs a drive signal which varies with the error between its inputs. The pass transistor&#39;s gate (assuming the pass transistor is a field-effect transistor (FET)) is connected to receive the drive signal, and its drain-source circuit is connected between an input voltage and the regulator&#39;s output voltage terminal. The error amplifier&#39;s drive signal causes the pass transistor to conduct a current to the output voltage terminal which maintains the output voltage at a desired level. 
     One problem which may afflict a linear voltage regulator is a short-circuit between the output voltage terminal and ground. When this occurs, the output voltage droops, and the error amplifier responds by increasing the drive signal. This results in the pass transistor carrying a high current, which may damage or destroy the transistor. 
     To prevent damage to the pass transistor, many linear regulators employ some form of short-circuit protection. Many protection methods require the use of an external sensing element such as a resistor to detect a short. However, this approach increases the regulator&#39;s cost, complexity, and power dissipation, and requires an extra pin on the integrated circuit (IC) containing the regulator circuitry. 
     One method which avoids the need for an external resistor is referred to as “hiccup mode” short-circuit protection, which operates as follows: once a short-circuit condition is detected, closed-loop operation of the regulator is suspended. The pass transistor is turned on briefly, and the output voltage measured. If the output voltage is below a predetermined threshold voltage, indicating that the short-circuit persists, the pass transistor is turned off. After a longer period the pass transistor is turned on again, and the output voltage again measured and compared with the threshold voltage. This pattern is repeated indefinitely, unless the short-circuit clears and the output voltage recovers. 
     The ratio of the pass transistor&#39;s on-time to off-time while the regulator is in hiccup mode is typically controlled by some sort of timing circuit. One approach is illustrated in the ADM1050 voltage regulator controller from Analog Devices, Inc., which employs an internal digital timer and oscillator to handle hiccup mode timing. However, this approach can be silicon intensive, particularly when the integrated circuit (IC) is fabricated using analog processes which are not optimized for digital circuitry. Another implementation is used in the UCC3837 linear regulator controller from Unitrode Corp., which requires the use of an external timing capacitor to provide the necessary timing. However, the external capacitor introduces an extra cost, as well as requiring a dedicated IC package pin. 
     SUMMARY OF THE INVENTION 
     A hiccup-mode short circuit protection circuit and method suitable for use with a linear voltage regulator which employs a FET pass transistor is presented. The invention avoids the problems discussed above, requiring neither an internal timer nor an extra pin for a timing capacitor. 
     The invention uses the capacitance of the FET pass transistor&#39;s gate as a hiccup-mode timing element. The regulator&#39;s output voltage is monitored, and when it droops below a first predetermined threshold indicative of a short-circuit condition, the amplifier&#39;s drive signal is essentially disconnected from the pass transistor. While the short-circuit condition persists, a first current is provided to charge the pass transistor&#39;s gate capacitance. When the gate voltage rises above a second predetermined threshold, a second current is provided to further charge the gate capacitance. When the gate voltage rises above a third predetermined threshold, the gate capacitance is discharged. The gate capacitance is cyclically charged and discharged in this way indefinitely, unless the output voltage rises enough to indicate that the short-circuit condition has cleared—in which case the amplifier&#39;s drive signal is reconnected to the pass transistor&#39;s gate and normal operation resumed. 
     In a preferred embodiment, a first current source charges the gate capacitance slowly until the pass transistor&#39;s turn-on voltage is reached, at which point a second, larger current source is connected to quickly ramp up the gate voltage. To reduce average power consumption, the magnitudes of the first and second currents and the values of the second and third predetermined threshold voltages are chosen such that the ON duty cycle for the pass transistor is about 10%. 
     Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram illustrating the basic principles of the present invention. 
     FIG. 2 depicts the pass transistor drive signal waveform provided by the invention during a short-circuit condition. 
     FIG. 3 is a schematic diagram of a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The basic principles of a hiccup-mode short circuit protection circuit suitable for use with a linear voltage regulator which employs a FET pass transistor are illustrated in FIG. 1. A typical linear voltage regulator  10  consists of an error amplifier  12  which produces a drive signal DRV at an output  14 . During normal operation, the drive signal is connected to the gate of a FET pass transistor MN 1 , the drain-source circuit of which is connected between an input voltage V in  and an output voltage terminal  15 ; MN 1  conducts a current which varies with DRV to output voltage terminal  15 , thereby producing the regulator&#39;s output voltage V out . Amplifier  12  receives two inputs: a voltage V set  which represents a desired output voltage, and a feedback signal FB representing the V out  voltage. Drive signal DRV varies with the error between these inputs, and acts to drive MN 1  as necessary to eliminate the error and achieve the desired output voltage. 
     FET pass transistor MN 1  may be integrated with amplifier  12 , or be external to the IC containing the regulator circuitry. When pass transistor MN 1  is external, amplifier  12  provides drive signal DRV to MN 1  via a drive terminal  16 , and the feedback signal is received via a feedback terminal  18 . 
     Output voltage V out  will droop if it becomes shorted to ground for some reason, and error amplifier  12  will attempt to compensate by driving MN 1  to conduct more current. This process can result in MN 1  being damaged or destroyed. To prevent this from happening, a hiccup-mode short-circuit protection circuit  20  is used. Hiccup-mode protection requires that, once a short-circuit condition is detected, normal closed-loop operation is suspended and the voltage on the pass transistor&#39;s gate periodically ramps up and down to turn MN 1  on and off. Output voltage V out  is continuously monitored, and if at any time V out  exceeds a voltage which indicates that the short-circuit condition has cleared, hiccup-mode is terminated and normal closed-loop operation restored. 
     The invention implements hiccup-mode protection in a novel and extremely efficient manner. A first comparator CMP 1  receives V out  (or a signal representing V out ) at one input, and a threshold voltage V thr1  at its second input. The output  22  of CMP 1  toggles high when V out  falls below V thr1 , which is chosen to indicate the occurrence of a short-circuit condition. A switch S 1  is actuated and de-actuated in response to a control signal  24 . S 1  is connected such that when actuated, the DRV signal provided by amplifier  12  to MN 1  is reduced to zero or near zero; when de-actuated, the DRV signal is restored to MN 1 . CMP 1  output  22  provides control signal  24 : when V out  falls below V thr1 , CMP 1  toggles high and actuates S 1 , thereby essentially disconnecting amplifier  12  from MN 1  and terminating closed-loop operation of the regulator. This action initiates hiccup-mode operation, which the protection circuit remains in as long as V out  remains below V thr1 . 
     While in hiccup-mode, a first current source circuit  26  is activated to provide a fixed current I 1  to the gate of MN 1 . As with all FETs, MN 1  has an inherent gate capacitance C g , which is charged by current I 1 . A second comparator CMP 2  monitors the voltage V gate  on the gate of MN 1 , which ramps up as the gate capacitance is charged. CMP 2  receives V gate  at one input, a threshold voltage V thr2  at its second input, and produces an output which toggles high when V gate  rises above V thr2 . When the output of CMP 2  goes high, a second current source circuit  28  is activated to provide a fixed current I 2  to the gate of MN 1 , further charging the gate capacitance and increasing the ramp rate for V gate . 
     Third and fourth comparators CMP 3  and CMP 4  also monitor V gate , with each comparator receiving V gate  at one input and threshold voltages V thr3  and V thr4  at their respective second inputs. CMP 3  produces an output which toggles high when V gate  rises above V thr3 , and CMP 4  produces an output which toggles high when V gate  falls below V thr4 . A switch circuit  30  is connected to discharge gate capacitance C g  when the output of CMP 3  goes high, and to stop discharging C g  when the output of CMP 4  goes high. 
     In operation, when CMP 1  detects that V out  has drooped below V thr1 , its output actuates S 1  and essentially disconnects amplifier output  14  from MN 1 , thereby entering hiccup-mode. The waveform of V gate  during hiccup-mode is shown in FIG. 2; for the exemplary waveform shown, V thr2  is 2 volts, V thr3  is 6 volts, and V thr4  is 0.2 volts. As hiccup-mode is initiated, current I 1  begins to charge C g , causing V gate  to ramp up (region A) at a rate that depends on the values of I 1  and C g . When V gate  increases above V thr2  (2 volts), CMP 2  activates current source circuit  28 , and current I 2  further charges C g  (region B), at a rate determined by I 1 , I 2  and C g . V gate  is allowed to increase up to V thr3  (6 volts), at which point the output of CMP 3  actuates switch circuit  30  to discharge the capacitance (region C). CMP 4  detects when the gate voltage drops below V thr4  (0.2 volts), and de-actuates switch circuit  30 . At this point, current I 1  begins charging C gate  again, and the cycle described above is repeated. If V out  rises above V thr1  at any time (indicating that the short-circuit condition has cleared), hiccup-mode is terminated: CMP 1  de-actuates S 1  such that amplifier output  14  is restored to MN 1 , I 2  and switch circuit  30  are disabled, and normal regulator operation is resumed. 
     The value of C g , in combination with the values of I 1  and I 2 , sets the period of each hiccup-mode cycle. In this way, the regulator&#39;s pass transistor is used for two purposes: as the regulator&#39;s pass device, and as the timing element for the regulator&#39;s hiccup-mode short circuit protection. This novel approach eliminates the need for an internal timing circuit, an external timing capacitor, or an extra IC pin as are required by various prior art hiccup-mode circuits. Note, however, that an external timing capacitor could be connected in parallel with C g  (e.g., C g2  in FIG.  1 ), if it is desired to slow down the ramp rate of V g . 
     When MN 1  is turned on as V gate  ramps up, it conducts a high current and dissipates a considerable amount of power. If on too long, MN 1  can overheat and become damaged. To avoid this, the present invention is preferably arranged to keep the average power dissipation in MN 1  during hiccup-mode small. This is accomplished by having MN 1  turned on for only a small portion of each hiccup-mode cycle: preferably about 10% of the total duty cycle. This can be done by selecting V thr2  to be in the range of MN 1 &#39;s turn-on voltage (i.e., within about ±0.5 volts of the turn-on voltage), making I 1  a small current, and making I 2  much larger than I 1 . The V thr2  and I 1  values produce the slow ramp portion (region A) of the V gate  waveform, during most or all of which MN 1  is off. The higher I 2  value produces the fast ramp portion (region B) of the V gate  waveform, during which MN 1  is turned on, voltage V thr3  is quickly reached, and MN 1  is turned off again. With MN 1  on for only a brief portion of each cycle, the desired small ON duty cycle, defined as the percentage of a hiccup-mode cycle period during which MN 1  is on, can be achieved. 
     Use of a single current source to charge C g  would necessarily result in a much higher ON duty cycle, due to the constant rate at which V gate  would ramp. For example, if MN 1  turns on at 2 volts, and V thr2  and V thr3  are 2 volts and 6 volts, respectively, MN 1  will have an ON duty cycle of 66% if V gate  ramps from 0 to 6 volts at a single, constant rate. As a specific example, assume that MN 1  carries 5 amps and has a voltage of 3.3 volts across it when on. With an ON duty cycle of 66%, the average power dissipation in MN 1  would be (66%×5 amps)×3.3 volts≈11 watts. This amount of power is likely to damage or destroy MN 1 . However, when two current sources are used as described above to provide an ON duty cycle of 10%, the average power dissipation is only (10%×5 amps)×3.3 volts≈1.65 watts. 
     With the above considerations in mind, the value of V thr2  is preferably chosen (as noted above) to be in the range of the pass transistor&#39;s threshold voltage. The value of V thr3  needs to be high enough to turn MN 1  fully on, but less than the absolute maximum voltage specification for the FET. V thr4  should be low enough to indicate that the gate capacitance is substantially discharged. As noted above, V thr1  is selected to indicate the presence of a short-circuit condition at the regulator&#39;s output terminal. 
     Referring back to FIG. 1, switch S 1  is preferably connected in series between the output  14  of amplifier  12  and the gate of pass transistor MN 1 . When so configured, S 1  is “opened” and disconnects amplifier  12  from MN 1  when CMP 1  detects that V out  has fallen below V thr1 . S 1  is preferably implemented with a FET switch, but other switch types—such as an electro-mechanical relay—could be used as well, as long as the chosen switch substantially reduces the drive signal delivered to MN 1  when actuated, and is responsive to a control signal. 
     It is not essential that S 1  be connected as shown in FIG.  1 . For example, S 1  might be employed within amplifier  12  such that the amplifier is disabled when S 1  is actuated. Note that the state of S 1  when “actuated” is dependent on how it is used. When configured as shown in FIG. 1, S 1  is opened when actuated by CMP 1 . If used in an alternative manner, however, it may be necessary that S 1  close when actuated by CMP 1 . 
     It should also be noted that the polarities of the comparator outputs need not be identical to those described above. In addition, the circuits that respond to the comparator outputs may be configured to respond to different logic levels than those described above. For example, though the output of CMP 1  is described as toggling from low to high when V out  falls below V thr1 , and that S 1  is thereby actuated, CMP 1  might also be arranged to toggle from high to low when V out  falls below V thr1 , and S 1  can be correspondingly arranged to respond appropriately. This is similarly true for the outputs of CMP 2 -CMP 4  and the operation of current source circuit  28  and switch circuit  30 . 
     A preferred embodiment of the present protection circuit  20  is shown in FIG.  3 . Elements common to both FIGS. 1 and 3 share the same reference numbers. Here, current source circuit  26  includes an inverter  50 , a switch S 2  which is controlled by the inverter output, and a fixed current source  52  which produces current I 1  connected in series with S 2 . When the output  22  of CMP 1  goes high (indicating a short-circuit condition), S 1  is opened, and the output of inverter  50  goes low and closes S 2 , which allows current I 1  to be delivered to drive terminal  16  (and the gate of pass transistor MN 1 , not shown). 
     Note that it is not essential that the protection circuit include inverter  50  and switch S 2 . The output of fixed current source  52  may be connected directly to drive terminal  16  such that I 1  is delivered to the pass transistor even during normal operation—as long as the magnitude of I 1  is such that it does not inhibit normal closed-loop control of the regulator&#39;s output voltage. 
     Another possibility is to make current I 1  switchable, but to do so with circuitry internal to current source  52  which is responsive to the output of CMP 1  or inverter  50 , rather than with a discrete switch. 
     Current source  28  preferably comprises an AND gate  54 , a switch S 3  which is controlled by the AND gate output, and a fixed current source  56  which produces current I 2  connected in series with S 3 . When the output of CMP 2  goes high (indicating that V gate  has exceeded V thr2 ), and the output of CMP 1  is still high (indicating that a short-circuit condition still exists) the output of AND gate  54  goes high and closes S 3 , which allows current I 2  to be delivered to drive terminal  16 . Due to the duty cycle and closed-loop operation considerations discussed above, it is essential that I 2  be switchable. However, as with current circuit  26 , I 2  may be made switchable using means other than a discrete switch. 
     Switch circuit  30  preferably comprises a set-reset (SR) latch  58  which receives the outputs of CMP 3  and CMP 4  at its set and reset inputs, respectively, an AND gate  60  which receives the output of latch  58  and CMP 1 , and a switch S 4  which is controlled by the AND gate output. S 4  is connected between drive terminal  16  and circuit common, such that when actuated, the gate of MN 1  is horted to common and its capacitance discharged. Switch circuit  30  operates as follows: when the output of CMP 3  goes high (indicating that V gate  has exceeded V thr3 ), the SR latch is set and its output goes high. Since a short-circuit condition still exists, the output of CMP 1  is high. These two logic “highs” cause the output of AND gate  60  to go high, which actuates S 4  and discharges the gate capacitance. As the capacitance is discharged, V gate  starts to fall. When V gate  falls below threshold voltage V thr4 , selected to indicate that C g  is substantially discharged, the output of CMP 4  goes high and resets latch  58 , causing S 4  to be de-actuated and the discharging of C g  to cease. 
     After C g  is discharged, V gate  is below V thr2  and V thr3 . This results in current source  28  being disabled, S 4  remaining open, and another hiccup-mode cycle being started. As long as V out  remains below V thr1 , the hiccup-mode cycle will repeat indefinitely. However, if V out  exceeds V thr1  at any time, the output of CMP 1  will go low, disabling the protection circuit and causing the output  14  of amplifier  12  to be restored to the gate of MN 1 , allowing normal closed-loop regulator operation to resume. 
     Note that the implementation shown in FIG. 3 is but one possible embodiment of the invention; many other configurations could be conceived to provide a hiccup-mode cycle as described herein. 
     It should also be noted that, although the pass transistor is shown as an N-type FET in the figures, the invention is equally applicable to use with a P-type FET. In this case, the hiccup-mode short-circuit protection circuit is arranged such that the waveforms of FIG. 2 cycle between 0 volts and a negative V gate  voltage. 
     While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.