Abstract:
Techniques pertaining to a voltage regulator with a current limiting circuit having low quiescent current are disclosed. According to one aspect of the present invention, a current limiting circuit is provided for limiting a current passing through an output pass circuit of a voltage regulator, the current limiting circuit comprises: a current sampling circuit for sampling the current passing through the output pass circuit to obtain a duplicated current being proportional to the current passing through the output pass circuit; a current mirror circuit for producing a mirror current being proportional to the duplicated current with the duplicated current as a reference current; a current to voltage converter for producing a voltage being proportional to the mirror current; and a voltage comparator for comparing the voltage produced by the current to voltage converter with a threshold voltage and turning off the output pass circuit when the voltage produced by the current to voltage converter is larger than or equal to the threshold voltage.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to integrated circuit design techniques, more particularly to a voltage regulator with a current limiting circuit having low quiescent current. 
         [0003]    2. Description of Related Art 
         [0004]    With more uses of portable electronic devices, we start to pay more and more attention to design of standby power consumption of the portable electronic devices. The standby power consumption directly influences a work time of the portable electronic devices. Battery capacity of the portable electronic devices is very limited, so it needs to reduce quiescent currents of various electronic components of the portable electronic device as much as possible. Hence, various power management integrated circuits are used in the portable electronic devices, such as low dropout voltage regulators or DC-DC converters etc., to continuously reduce the quiescent current during light loading. 
         [0005]    A low dropout voltage regulator is taken as an example for illustration hereafter. The voltage regulator comprises a reference voltage source, an error amplifier, an output pass circuit, a sampling resistor and a bypass circuit. The error amplifier may be a comparator. A reference voltage provided by the reference voltage source is coupled to an inverse input of the comparator. A sampling voltage obtained by sampling an output voltage of the output pass circuit via the sampling resistor is coupled to a non-inverse of the comparator, thereby a negative feedback loop is formed. A difference between the reference voltage and the sampling voltage is amplified by the error amplifier to control the output pass circuit until the output voltage of the output pass circuit goes to stabilization. The output pass circuit may be implemented by a bipolar transistor or a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET). 
         [0006]    Additionally, it is necessary for the low dropout voltage regulator or the DC-DC converter to employ a current protection circuit, also referred as a current limiting circuit, which can effectively limit the current passing through the output pass circuit of the low dropout voltage regulator or the DC-DC converter during short circuit or overload. However, the conventional current limiting circuit may have a great quiescent current when the power management IC, such as the low dropout voltage regulator or the DC-DC converter, is under no load condition. 
         [0007]    Referring to  FIG. 1 , a circuit diagram shows a prior art low dropout voltage regulator  100  with a current limiting circuit, either the current limiting circuit or a current source  18  therein may introduce a great quiescent current. 
         [0008]    Thus, improved techniques for the current limiting circuit are desired to overcome at least the above disadvantages. 
       SUMMARY OF THE INVENTION 
       [0009]    This section is for the purpose of summarizing some aspects of the present invention and to briefly introduce some preferred embodiments. Simplifications or omissions in this section as well as in the abstract or the title of this description may be made to avoid obscuring the purpose of this section, the abstract and the title. Such simplifications or omissions are not intended to limit the scope of the present invention. 
         [0010]    In general, the present invention is related to a voltage regulator with a current limiting circuit having low quiescent current. According to one aspect of the present invention, a current limiting circuit is provided for limiting a current passing through an output pass circuit of a voltage regulator, the current limiting circuit comprises: a current sampling circuit for sampling the current passing through the output pass circuit to obtain a duplicated current being proportional to the current passing through the output pass circuit; a current mirror circuit for producing a mirror current being proportional to the duplicated current with the duplicated current as a reference current; a current to voltage converter for producing a voltage being proportional to the mirror current; and a voltage comparator for comparing the voltage produced by the current to voltage converter with a threshold voltage and turning off the output pass circuit when the voltage produced by the current to voltage converter is larger than or equal to the threshold voltage. 
         [0011]    Other objects, features, and advantages of the present invention will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where: 
           [0013]      FIG. 1  is a circuit diagram showing a low dropout voltage regulator with a current limiting circuit in the prior art; 
           [0014]      FIG. 2  is a circuit diagram showing a current limiting circuit according to one embodiment of the present invention; 
           [0015]      FIG. 3  is a circuit diagram showing the current limiting circuit in another embodiment of the present invention; 
           [0016]      FIG. 4  is a circuit diagram showing a low dropout voltage regulator with the current liming circuit shown in FIG.; 
           [0017]      FIG. 5  is a circuit diagram showing the current limiting circuit in still another embodiment of the present invention; 
           [0018]      FIG. 6  is a circuit diagram showing the low dropout voltage regulator with the current liming circuit shown in  FIG. 5 ; and 
           [0019]      FIG. 7  is a circuit diagram showing the current limiting circuit in yet another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]    The detailed description of the present invention is presented largely in terms of procedures, steps, logic blocks, processing, or other symbolic representations that directly or indirectly resemble the operations of devices or systems contemplated in the present invention. These descriptions and representations are typically used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. 
         [0021]    Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Further, the order of blocks in process flowcharts or diagrams or the use of sequence numbers representing one or more embodiments of the invention do not inherently indicate any particular order nor imply any limitations in the invention. 
         [0022]    Embodiments of the present invention are discussed herein with reference to  FIGS. 2-7 . However, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes only as the invention extends beyond these limited embodiments. 
         [0023]    A current limiting circuit provided according to one embodiment of the present invention can be applied in various voltage regulators, such as a DC-DC converter or low dropout voltage regulator etc., which employs an output pass circuit implemented by transistor such as a bipolar transistor or a MOS field effect transistor etc. 
         [0024]      FIG. 2  is a circuit diagram showing a current limiting circuit  200  in one embodiment of the present invention. Referring to  FIG. 2 , the current limiting circuit  200  comprises a current sampling circuit which includes a MOS field effect transistor MP 1 . The MOSFET MP 1  is configured to sample a current passing through the output pass circuit MPass of the low dropout voltage regulator or a DC-DC converter (as shown in  FIG. 4 ), thereby a current passing through the MOSFET MP 1  is proportional to that passing through the output pass circuit MPass. In this embodiment, the MOSFET MP 1  and the output pass circuit both are P-channel MOS field effect transistors. Referring to  FIG. 4 , the output pass circuit  400  is connected between an input voltage VCC and an output voltage Vo. A control terminal, namely a gate MPG, of the output pass circuit MPass is coupled to an output terminal of an error amplifier. A source terminal of the output pass circuit MPass is coupled to the input voltage VCC, and a drain terminal of the output pass circuit MPass is coupled to the output voltage Vo. A gate terminal of the MOSFET MP 1  is coupled to the gate terminal MPG of the output pass transistor MPass, and a source terminal of the MOSFET MP 1  is coupled to the source terminal the output pass transistor MPass. 
         [0025]    According to the inherent current characteristic of the MOS field effect transistor, the ratio of the current passing through the MOSFET MP 1  to the current passing through the output pass circuit MPass is equal to the ratio of a channel width to length ratio (W/L) MP1  of the MOSFET MP 1  to a channel width to length ratio (W/L) MPass  of the output pass circuit MPass when the MOSFET MP 1  and the output pass circuit MPass have a same threshold voltage V GS(th) . Thus, it is relatively easy to change the ratio of the current passing through the MOSFET MP 1  to the current passing through the output pass circuit MPass by selecting physical sizes of the MOSFET MP 1  and the output pass circuit MPass. In one preferred embodiment, the current passing through the MOSFET MP 1  is designed to be equal to or less than 1/1000 of the current passing through the output pass circuit MPass by selecting proper physical sizes. 
         [0026]    Referring to  FIG. 2 , the current limiting circuit further comprises a current mirror circuit, a current to voltage converter and a voltage comparator. The current mirror circuit is coupled to the current sampling circuit for generating a mirror current being proportional to the current passing through the current sampling circuit with the current passing through the current sampling circuit as a reference current. The current to voltage converter is coupled to the current mirror circuit for generating a voltage being proportional to the mirror current. The voltage comparator is coupled to the current to voltage converter and the control terminal MPG of the output pass circuit MPass for comparing the voltage generated by the current to voltage converter with a threshold voltage. When the voltage generated by the current to voltage converter is larger than the threshold voltage, the voltage comparator pulls a voltage on the control terminal MPG of the output pass circuit MPass up to a predetermined voltage value. 
         [0027]    In the embodiment shown in  FIG. 2 , the current mirror circuit is formed by a pair of N-channel MOS field effect transistors MN 1 , and MN 3 . The current to voltage converter is formed by a resistor R 1 . The voltage comparator is formed by a P-channel MOS field transistor MP 4 . A drain terminal of the MOSFET MN 1  is coupled to the drain terminal of the MOSFET MP 1 , a source terminal of the MOSFET MN 1  is grounded, and a gate terminal of the MOSFET MN 1  is coupled to a gate terminal of the MOSFET MN 2  and the drain terminal of the MOSFET MN 1 . A source terminal of the MOSFET MN 3  is grounded, and a drain terminal of the MOSFET MN 3  is coupled to one terminal of the resistor R 1  and a gate terminal of the MOSFET MP 4 , the other terminal of the resistor R 1  is coupled to the input voltage VCC. A source terminal of the MOSFET MP 4  is coupled to the input voltage VCC, and a drain terminal of the MOSFET MP 4  is coupled to the control terminal MPG of the output pass circuit MPass. 
         [0028]    In operation, the current passing through the MOSFET MN 1  is equal to the current passing through the MOSFET MP 1 . The ratio of the current passing through the MOSFET MN 3  to the current passing through the MOSFET MN 1  is equal to the ratio of a channel width to length ratio (W/L) MN3  of the MOSFET MN 3  to a channel width to length ratio (W/L) MN 1  of the MOSFET MN 1 . A voltage drop is formed on the resistor R 1  when the current passing through the MOSFET MN 3  passes through the resistor R 1 . The voltage drop on the resistor R 1  is provided as a bias voltage between the gate terminal and the source terminal of the MOSFET MP 4 . The MOSFET MP 4  compares the voltage drop on the resistor R 1  with an absolute value |V GS(th)MP4 | of the threshold voltage and determines whether the voltage on the control terminal MPG should be pulled up according to a comparison result. When the voltage drop on the resistor R 1  goes up to the absolute value |V GS(th)MP4 | of the threshold voltage, the MOSFET MP 4  turns on, thereby the voltage on the drain terminal of the MOSFET MP 4  (the gate terminal MPG of the output pass circuit MPass) is pulled up to approximate to the input voltage VCC because the voltage drop on the MOSFET MP 4  is very small. Thereby, the maximum allowable output current I Limit  of the current limiting circuit about is: 
         [0000]    
       
         
           
             
               I 
               Limit 
             
             = 
             
               
                 
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                     V 
                     
                       
                         GS 
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         [0029]    Wherein |V GS(th)MP4 | is the absolute value of the threshold voltage of the MOSFET MP 4 , R 1  is a resistance value of the resistor R 1 , (W/L) MN1  is the channel width to length ratio of the MOSFET MN 1 , (W/L) MN3  is the channel width to length ratio of the MOSFET MN 3 , (W/L) MP1  is the channel width to length ratio of the MOSFET MP 1 , and (W/L) MPass  is the channel width to length ratio of the output pass circuit MPass. 
         [0030]    The absolute value |V GS(th)MP4 | usually has a negative temperature coefficient. The resistor R 1  having a negative temperature coefficient is preferably selected for temperature compensation purpose, whereby the influence on the current limiting circuit introduced by changes of temperature is substantially eliminated. In another embodiment, two or more resistors with different temperature coefficients may be provided to constitute the resistor R 1 . For example, the resistor R 1  may be constituted by one polycrystal resistor with the negative temperature coefficient and one N-cell resistor with the positive temperature coefficient. 
         [0031]    The term of 
         [0000]    
       
         
           
             
               
                 
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         [0000]    in the maximum allowable output current I Limit  is only relative to the channel width to length ratios of the MOSFET MN 1 , MN 3 , MP 3  and MP 3  and hasn&#39;t any relation to the manufacturing process, power voltage and temperature. The change of the other term of 
         [0000]    
       
         
           
             
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         [0000]    in the maximum allowable output current I Limit  is equivalent with that of most bias currents. However, there are only a few times of current duplications by the mirror current circuit in the present invention, and the deviation caused thereby is decreased as much as possible. Hence, the accuracy of the current limiting circuit is enhanced. As a result, the manufacturing process almost has no influence on the current limiting circuit of the present invention, and different current limiting circuits of the present invention have better consistency. Furthermore, a terminal may be led out from the resistor R 1  for trimming the resistance of the resistor R 1  after production in order to enhance accuracy of the current limiting circuit. 
         [0032]    As described above, when the current passing through the output pass circuit MPass is zero, the current passing through the MOSFET MP 1  should be zero too, the currents respectively passing through the MOSFETs MN 1  and MN 3  both are zero correspondingly, so the voltage drop on the resistor R 1  should be zero and the MOSFET MP 4  is in off state. As a result, the current limiting circuit has no any current consumption. However, the low dropout voltage regulator or the DC-DC converter usually comprises a feed back circuit, such as a pair of resistors R f1  and R f2  shown in  FIG. 4 . Even if the load current of the low dropout voltage regulator or the DC-DC converter is zero, the current passing through the output pass circuit MPass isn&#39;t zero yet. But the current passing through the output pass circuit MPass is very small at this time and equal to a current consumed by the feed back circuit. Provided that the current consumed by the feed back circuit is 1 μA, the ratio of (W/L) MP1  to (W/L) MPass  is 1/1000, and the ratio of (W/L) MN3  to (W/L) MN1  is 1/10, so the current passing through the MOSFET MP 1  is 1 nA, the current passing through the MOSFET MN 3  is 0.1 nA and the total quiescent current consumption of the current limiting circuit is 1.1 nA. The current of nanoampere order can be neglected in most applications. In some embodiments, the total quiescent current consumption of the current limiting circuit can be further reduced by decreasing the ratio of (W/L) MP1  to (W/L) MPass  and the ratio of (W/L) MN3  to (W/L) MN1 . For example, the ratio of (W/L) MP1  to (W/L) MPass  may be designed to be 1/10000, and the ratio of (W/L) MN3  to (W/L) MN1  may be designed to be 1/10, thus the total quiescent current consumption of the current limiting circuit is 0.11 nA. 
         [0033]    In one embodiment, the channel length of the MOSFET MN 1  and MN 3  is designed to be larger, and it helps to reduce the channel length modulation effect. Thus, the proportional relation between the currents passing through the MOSFET MN 1  and MN 3  may become more accurate. For better current matching in design, the MOS field effect transistors MN 1  and MN 3  consist of single unit devices having uniform width and length. The number of the single unit devices in the MOSFET MN 1  may be different from that in the MOSFET MN 3 . For example, the width and the length of the single unit device respectively are W=20 μm, L=4 μm, the number of the single unit devices in the MOSFET MN 1  is m MN1 =40, the number of the single unit devices in the MOSFET MN 1  is m MN3 =1. Thus, the current passing through the MOSFET MN 1  is 40 times than that passing through the MOSFET MN 3 . 
         [0034]    For further improving the response speed of the current limiting circuit, the channel length of the MOSFET MP 4  usually is designed to be smaller so that the channel width to length ratio of the MOSFET MP 4  is a larger value. For example, the width and the length of the MOSFET MP 4  respectively are W=10 μm, L=0.5 μm, so the channel width to length ratio of the MOSFET MP 4  is 20. 
         [0035]      FIG. 3  is a circuit diagram showing the current limiting circuit in another embodiment of the present invention.  FIG. 4  is a circuit diagram showing a low dropout voltage regulator with the current liming circuit shown in  FIG. 3 . The current limiting circuit shown in  FIG. 3  is identical with that shown in  FIG. 2  except that the former introduces a pair of P-channel MOS field effect transistors MP 2  and MP 3 , and a N-channel MOS field effect transistor MN 2 . A source terminal of the MOSFET MP 2  is coupled to the drain terminal of the MOSFET MP 1 , a drain terminal of the MOSFET MP 2  is coupled to the drain terminal of the MOSFET MN 1 , and a gate terminal of the MOSFET MP 2  is coupled to a gate terminal of the MOSFET MP 3 . A source terminal of the MOSFET MP 3  is coupled to the drain terminal (namely the output voltage Vo) of the output pass circuit shown in  FIG. 4 , a drain terminal of the MOSFET MP 3  is coupled to the gate terminal of the MOSFET MP 3  and a drain terminal of the MOSFET MN 2 . A gate terminal of the MOSFET MN 2  is coupled to the gate terminal of the MOSFET MN 1 , and a source terminal of the MOSFET MN 2  is coupled to the source terminal of the MOSFET MN 1 . The MOSFET MN 2  and the MOSFET MN 1  form another current mirror circuit to provide a bias current for the MOSFET MP 3 . The MOSFET MP 3  and the MOSFET MP 2  are configured for ensuring that the voltage on the drain terminal of the MOSFET MP 1  is equal to that on the drain terminal of the output pass circuit MPass, thereby the proportional relation between the currents passing through the MOSFET MP 1  and the output pass circuit MPass may become more accurate. 
         [0036]    Normally, it designs that (W/L) MP2 /(W/L) MP3 =(W/L) MN1 /(W/L) MN2 , wherein (W/L) MP2  is the channel width to length ratio of the MOSFET MP 2 , and (W/L) MP3  is the channel width to length ratio of the MOSFET MP 3 . 
         [0037]    Besides the current limiting circuit, the low dropout voltage regulator shown in  FIG. 4  further comprises an error amplifier, an output pass circuit MPass mentioned above, and a feed back circuit. The source terminal of the output pass circuit MPass is coupled to the input voltage VCC, and the drain terminal of the output pass circuit MPass is coupled to the output voltage Vo. The feedback circuit comprises a pair of resistor Rf 1  and Rf 2  connected in series between the output voltage Vo and the ground. An inverse input of the error amplifier is coupled to a reference voltage Ref, a non-inverse input of the error amplifier is coupled to a feedback voltage Vf provided by the feedback circuit Rf 1  and Rf 2 . An output of the error amplifier is coupled to the gate terminal MPG of the output pass circuit MPass. Additionally, a load resistor RL and an output capacitor Co are connected in series between the output voltage Vo and the ground. The ordinary people skilled in the art will readily appreciate how to control the output pass circuit MPass to produce the proper output voltage Vo, so it is omitted hereafter for simplicity. 
         [0038]      FIG. 5  is a circuit diagram showing the current limiting circuit in still another embodiment of the present invention.  FIG. 6  is a circuit diagram showing the low dropout voltage regulator with the current liming circuit shown in  FIG. 5 . The current limiting circuit shown in  FIG. 5  can be used in the low dropout voltage regulator or the DC-DC converter, which employs the output pass circuit implemented by the bipolar transistor PNP 2 . Comparing with the current limiting circuit shown in  FIG. 2 , the current limiting circuit shown in  FIG. 5  employs PNP transistors PNP 4  and PNP 1  to replace the P-channel MOS field effect transistors MP 1  and MP 4  respectively, and employs NPN transistors NPN 1  and NPN 3  to replace the N-channel MOS field effect transistors MN 1  and MN 3  respectively. The resistor R 1 , the bipolar transistors PNP 1 , PNP 4 , NPN 1  and NPN 3  shown in  FIG. 5  and  FIG. 6  correspond to the resistor R 1 , the MOS field effect transistors MP 1 , MP 4 , MN 1  and MN 3  shown in  FIG. 2 , respectively. Specifically, a base, an emitter and a collector of the bipolar transistor correspond to the gate terminal, the source terminal and the drain terminal of the MOS field effect transistor, respectively. As shown in  FIG. 5  and  FIG. 6 , the bipolar transistor PNP 1  works as the current sampling circuit, the bipolar transistors NPN 1  and NPN 3  forms the current mirror circuit, the bipolar transistor PNP 4  works as the voltage comparator, and the resistor R 1  works as the current to voltage converter. Likewise, the voltage drop on the resistor R 1  is provided as a bias voltage between the base and the emitter of the bipolar transistor PNP 4 . The bipolar transistor PNP 4  compares the voltage drop on the resistor R 1  with an absolute value |V bePNP4 | of the threshold voltage thereof and determines whether the voltage on the control terminal MPG should be pulled up according to a comparison result. 
         [0039]    With reference of the relative description regarding to  FIGS. 2 and 4  and the current characteristic of the bipolar transistor, the ratio of the current passing through the bipolar transistor PNP 1  to the current passing through the output pass circuit PNP 2  is equal to the ratio of the emitter area of the bipolar transistor PNP 1  to the emitter area of the output pass circuit PNP 2 , the current passing through the bipolar transistor NPN 1  is equal to the current passing through the bipolar transistor PNP 1 , and the ratio of the current passing through the bipolar transistor NPN 3  to the current passing through the current passing through the bipolar transistor NPN 1  is equal to the ratio of the emitter area of the bipolar transistor NPN 3  to the emitter area of the output pass circuit NPN 1 . A voltage drop is formed on the resistor R 1  when the current passing through the bipolar transistor NPN 3  passes through the resistor R 1 . When the dropout voltage on the resistor R goes up to the absolute value |V bePNP4 | of the threshold voltage of the bipolar transistor PNP 4 , the voltage on the control terminal MPG will be pulled up. 
         [0040]    The circuits and relative considerations in  FIG. 5  and  FIG. 6  are same or similar to that in  FIG. 2  and  FIG. 4  in other aspects. Hence, it is omitted hereafter for simplicity. 
         [0041]      FIG. 7  is a circuit diagram showing the current limiting circuit  700  in yet another embodiment of the present invention. The current limiting circuit shown in  FIG. 7  is identical with that shown in  FIG. 2  except that the former employs a current source I 1  to replace the resistor R 1 . In this embodiment, the MOSFET MP 4  works as a current comparator rather than the voltage comparator as mentioned above. 
         [0042]    A positive terminal of the current source is coupled to the source terminal of the MOSFET MP 4 , and a negative terminal of the current source is coupled to the gate terminal of the MOSFET MP 4 . The MOSFET MP 4  is configured for comparing the mirror current passing through the MOSFET MN 3  with the current of the current source and pulling up the voltage on the control terminal MPG to a predetermined voltage value when the mirror current passing through the MOSFET MN 3  is larger than the current of the current source. When the current passing through the MOSFET MN 3  is less than that of the current source I 1 , the gate voltage of the MOSFET MP 4  is pulled up to the input voltage VCC by the current source, and the MOSFET MP 4  is in off state. At this time, the current passing through the output pass circuit has not any limitation. When the current passing through the MOSFET MN 3  is larger than that of the current source I 1 , the gate voltage of the MOSFET MP 4  is pulled down to the ground by the current source. As a result, the MOSFET MP 4  turns on to pull the control terminal MPG up to approximate to the input voltage VCC, and the current passing through the output pass circuit is limited. Thereby, the maximum allowable output current I Limit  of the current limiting circuit shown in  FIG. 7  about is: 
         [0000]    
       
         
           
             
               I 
               Limit 
             
             = 
             
               I 
                
               
                   
               
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                 1 
                 · 
                 
                   
                     
                       ( 
                       
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                         / 
                         L 
                       
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                       MN 
                        
                       
                           
                       
                        
                       1 
                     
                   
                   
                     
                       ( 
                       
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                         / 
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                        
                       
                           
                       
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                       3 
                     
                   
                 
                 · 
                 
                   
                     
                       ( 
                       
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         [0043]    wherein I 1  is the current value of the current source. 
         [0044]    In order to make a temperature compensation for the current limiting threshold, the current source drifting smaller along with changes of the temperature is employed. Additionally, the term of I 1  in the maximum allowable output current I Limit  may drift greatly due to changes of the manufacturing process. For improving accuracy of the current limiting threshold, a terminal may be led out from the current source I 1  for trimming after production. Usually, the change of ±30% of the current limiting threshold may be acceptable for most applications, thereby a reference current source in a normal integrated circuit also can satisfy the accuracy requirement of the current limiting threshold of the present invention. 
         [0045]    The circuits and relative considerations in  FIG. 7  are same or similar to that in  FIG. 2  in other aspects. Hence, it is omitted hereafter for simplicity. 
         [0046]    For improving the accuracy of the proportional relation between the currents passing through the MOSFET MP 1  and the output pass circuit MPass, a pair of P-channel MOS field effect transistors MP 2  and MP 3 , and a N-channel MOS field effect transistor MN 2  are introduced into the circuit limiting circuit shown in  FIG. 7  as that shown in  FIG. 3 . 
         [0047]    Thus, the current limiting circuit of the present invention doesn&#39;t employ a complex current limiting loop circuit as the conventional current limiting circuit, thereby greatly saving the area of the integrated circuit. Additionally, the current limiting circuit of the present invention doesn&#39;t employ a base bias current as the conventional current limiting circuit, thereby having no influence on the design of the base bias current circuit of other circuits. 
         [0048]    The present invention has been described in sufficient details with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.