Abstract:
Disclosed is a semiconductor device that comprises a first semiconductor layer of one conductivity type provided on a substrate; a second semiconductor layer of the one conductivity type provided on the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; an isolation region extending from one principal face of the second semiconductor layer to reach the substrate; a first region in an element region of the second semiconductor layer isolated by the isolation region and having an opposite conductivity type; a second region of the one conductivity type provided in the element region extending from the one principal face to reach the first semiconductor layer and having an impurity concentration higher than the second semiconductor layer; and an insulation region extending from the one principal face to the first semiconductor layer, kept away from the substrate, and provided between the first and the second regions.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority under 35 USC 119 from Japanese Patent Application No. 2010-035315 filed on Feb. 19, 2010, the disclosure of which is incorporated by reference herein. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a high withstand voltage MOS transistor device and a manufacturing method thereof. 
         [0004]    2. Related Art 
         [0005]    Some of high withstand voltage MOS transistor devices have a structure in which an epitaxial layer is provided on an embedded layer laid on a substrate, a high withstand voltage MOS transistor element is provided in the epitaxial layer, and a diffusion layer is provided which supplies an electric potential from the surface of the epitaxial layer to the embedded layer (refer to Japanese Patent Application Laid-Open (JP-A) No. 2002-190591). 
         [0006]    A conventional high withstand voltage MOS transistor having the above-described structure is explained below with reference to  FIG. 4 . 
         [0007]    An N-type embedded layer  13  is provided on a p-type silicon substrate  11 , and an n − -type epitaxial layer  15  is provided on the n-type embedded layer  13 . Field oxide films  21 ,  23 ,  25  are provided at one principal face  10  of the n − -type epitaxial layer  15 . A high withstand voltage MOS transistor  75  is provided at the one principal face  10  of the n − -type epitaxial layer  15  of an element region  71  isolated by an isolation trench  50 . An n-type sinker  17  that supplies an electric potential to the n-type embedded layer  13  is provided in such a manner as to extend from the one principal face  10  of the n − -type epitaxial layer  15 , which is exposed in an opening  24  between the field oxide films  23 ,  25  within the element region  71 , to the n-type embedded layer  13 . An n + -type contact area  19  is provided at the one principal face  10  of the n − -type epitaxial layer  15 , which is exposed in the opening  24 . A p + -type drain contact area  37  that is to come into contact with the a p −  drain region  35  of the high withstand voltage MOS transistor  75  is provided on a part of the p −  drain region  35 , which is exposed in an opening  22  between the field oxide films  21 ,  23 . 
         [0008]    In the high withstand voltage MOS transistor having the above-described structure, a high voltage is applied to the drain, and therefore, when a depletion layer that extends from the drain region  35  having a relatively high concentration and the n-type sinker  17  having a relatively high concentration come into contact with each other, an electric field concentrates at a place where the areas of high concentration come into contact with each other, and element breakage would be caused starting from the place, thereby leading to deterioration of withstand voltage. 
         [0009]    In order to deal with the above-described problem, conventionally, the drain region  35  and the n-type sinker  17 , which greatly differ from each other in electric potential, are separated from each other to relax electric field. However, in this practice, the element region increases, which runs counter to the technical field of the tendency that the element region decreases. The distance between the drain region  35  and the n-type sinker  17  does not adversely affect the element performance of the MOS transistor, and therefore, it is desired that the diatance is made to as small as possible insofar as withstand voltage of the element is not affected. 
       SUMMARY 
       [0010]    A main object of the present invention is to provide a semiconductor device in which an element region is small and withstand voltage of the element is high, and a manufacturing method thereof. 
         [0011]    According to a first aspect of the present invention, there is provided a semiconductor device comprising: 
         [0012]    a first semiconductor layer of one conductivity type provided on a substrate; 
         [0013]    a second semiconductor layer of the one conductivity type provided on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; 
         [0014]    an isolation region that extends from one principal face of the second semiconductor layer to reach the substrate, the one principal face being located at a side opposite to the first semiconductor layer; 
         [0015]    a first region provided in an element region of the second semiconductor layer isolated by the isolation region, the first region having an opposite conductivity type to the one conductivity type; 
         [0016]    a second region of the one conductivity type provided in the element region, the second region extending from the one principal face to reach the first semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; and 
         [0017]    an insulation region provided between the first region and the second region, the insulation region extending from the one principal face of the second semiconductor layer to the first semiconductor layer and being kept away from the substrate. 
         [0018]    According to a second aspect of the present invention, there is provided a manufacturing method of a semiconductor device, comprising: 
         [0019]    preparing a semiconductor substrate that has a substrate, a first semiconductor layer of one conductivity type that is provided on the substrate, and a second semiconductor layer of the one conductivity type that is provided on the first semiconductor layer, the first semiconductor layer having an impurity concentration higher than that of the second semiconductor layer; 
         [0020]    forming a first region by implanting first impurities of an opposite conductivity type to the one conductivity type into a surface of the semiconductor substrate from a side of the second semiconductor layer; 
         [0021]    forming a second region extending from the surface of the semiconductor substrate to reach the first semiconductor layer by implanting second impurities of the one conductivity type into the surface from the side of the second semiconductor layer, the second region having an impurity concentration higher than that of the second semiconductor layer; 
         [0022]    forming a first trench that surrounds the first region and the second region, and extends from the surface of the semiconductor substrate to reach the substrate; 
         [0023]    forming a second trench between the first region and the second region, the second trench extending from the surface of the semiconductor substrate to reach the first semiconductor layer; 
         [0024]    forming a first insulator in the first trench; and 
         [0025]    forming a second insulator in the second trench. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]    An exemplary embodiment of the present invention will be described in detail based on the following figures, wherein: 
           [0027]      FIG. 1  is a schematically longitudinal sectional view for explaining a semiconductor device according to a preferred embodiment of the present invention. 
           [0028]      FIG. 2  is a diagram for explaining a relationship between a trench opening and a trench depth. 
           [0029]      FIG. 3  is a graph for explaining a relationship between a trench opening and a trench depth. 
           [0030]      FIG. 4  is a schematically longitudinal sectional view for explaining a conventional semiconductor device. 
       
    
    
     DETAILED DESCRIPTION 
       [0031]    A preferred embodiment of the present invention will be described hereinafter with reference to the attached drawings. 
         [0032]    Referring to  FIG. 1 , in a preferred semiconductor device  100  of the present invention, an n-type embedded layer (NBL)  13  is provided on a p-type silicon substrate  11 , and an n − -type epitaxial layer  15  is provided on the n-type embedded layer  13 . The n − -type epitaxial layer  15  has a low impurity concentration compared to the n-type embedded layer  13 . Field oxide films  21 ,  23  and  25  are provided on one principal face of the n − -type epitaxial layer  15 . 
         [0033]    An isolation trench  50  is provided below the field oxide film  25 . The isolation trench  50  is provided so as to extend from the one principal face  10  of the n − -type epitaxial layer  15  into the p-type silicon substrate  11 . A channel stopper  57  is formed around the bottom portion of the isolation trench  50  in the p-type silicon substrate  11 . The isolation trench  50  includes an insulator comprised of a trench  59  that extends from the one principal surface  10  of the n − -type epitaxial layer  15  into the p-type silicon substrate  11 , a thermally oxidized film  51  provided within the trench  59 , an LP-TEOS (Low Pressure TEOS; TEOS is an abbreviated name of Si(OC 2 H 5 ) 4 ) oxide film  53 , and an LP-TEOS oxide film  55 . An isolation area  73  is formed by the field oxide film  25  and the isolation trench  50 . 
         [0034]    A high withstand voltage MOS transistor  75  is provided on the one principal face  10  of the n − -type epitaxial layer  15  of the element region  71 , which is isolated by the isolation trench  50 . The high withstand voltage MOS transistor  75  includes a gate electrode  43  that is provided on the one principal face  10  of the n − -type epitaxial layer  15  via a gate insulating film  41 , and a p −  source region  31  and a p −  drain region  35 , which are provided at the both sides of the gate electrode  43 . The p + -type drain contact area  37  that is to come into contact with the p −  drain region  35  is provided on the p −  drain region  35  that is exposed at the opening  22  between the field oxide films  21  and  23 . A p + -type source contact area  33  that is to come into contact with the p −  source region  31  is provided on the p −  source region  31  that is exposed at the opening  20  between the field oxide films  21 . 
         [0035]    An n-type sinker (n-type body)  17  that supplies an electric potential to the n-type embedded layer  13  is provided so as to extend from the one principal face  10  of the n − -type epitaxial layer  15  that is exposed at the opening  24  between the field oxide films  23 ,  35  in the element region  71  to reach the n-type embedded layer  13 . An n + -type contact area  19  is provided on the one principal face  10  of the n − -type epitaxial layer  15  that is exposed at the opening  24 . A bottom portion of the n-type sinker  17  does not reach the p-type silicon substrate  11 . The impurity concentration of the n-type sinker  17  is higher than that of the n − -type epitaxial layer  15 . The n-type embedded layer  13  is provided so as to electrically insulate the n − -type epitaxial layer  15  from the p-type silicon substrate  11 . The n-type sinker  17  is provided so as to prevent the n-type embedded layer  13  from being brought into a floating state, thereby preventing electric properties of the high withstand voltage MOS transistor  74  from being adversely affected. 
         [0036]    An insulation trench  60  is provided between the p −  drain region  35  of the high withstand voltage MOS transistor  75 , and the n-type sinker  17  in such a manner as to extend from the one principal face  10  of the n − -type epitaxial layer  15  to reach the n-type embedded layer  13 . The insulation trench  60  does not reach an interface between the n-type embedded layer  13  and the p-type silicon substrate  11 . The insulation trench  60  is provided below the field oxide film  23 . The isolation trench  60  includes an insulator comprised of a trench  67  that extends from the one principal face  10  of the n − -type epitaxial layer  15  to the n-type embedded layer  13 , a thermally oxidized film  61  provided in the trench  67 , an LP-TEOS oxide film  63  and an LP-TEOS oxide film  65 . 
         [0037]    In the present embodiment, the isolation trench  60  is provided between the p −  drain region  35  of the high withstand voltage MOS transistor  75 , and the n-type sinker  17  in such a manner as to extend from the one principal face of the n − -type epitaxial layer  15  to reach the n-type embedded layer  13 . Due to the above-described structure, electric insulation between the p −  drain region  35  and the n-type sinker  17  is realized. Further, a depletion layer that extends from the p −  drain region  35  does not extend to the n-type sinker  17 , and therefore, compared to a conventional system in which electrical interference is suppressed by gaining a distance between the p −  drain region  35  and the n-type sinker  17 , an increase in the element size may be restrained. 
         [0038]    In the present embodiment, the isolation trench  60  does not electrically isolate adjacent elements like a conventional trench used for element isolation, but is formed in consideration of electrical interference in the same element region. The lower end of the insulation trench  60  is disposed in the n-type embedded layer  13 , and does not reach the lower surface of the n-type embedded layer  13 . Therefore, even in a case in which the insulation trench  60  is formed, the n-type sinker  17  can provide electric potential to the n-type embedded layer  13  below the high withstand voltage MOS transistor  75 . The lower end of the insulation trench  60  preferably comes into contact with the upper face of the n-type embedded layer  13 . If doing so, it is possible to gain an electrical path between the n-type sinker  17  and the n-type embedded layer  13  below the high withstand voltage MOS transistor  75  to the maximum. In this manner, the depth of the insulation trench  60  is determined in consideration of the n-type embedded layer  13 . The above-described structure is apparently different from a trench used for isolation of elements, which extends beyond the n-type embedded layer  13  to reach the p-type silicon substrate  11 . 
         [0039]    Next, a manufacturing method of a semiconductor device  100  according to the present embodiment is described. 
         [0040]    A trench process of forming trenches allows formation of trenches having different depths at the same time, by varying the widths of the trenches without using an additional mask and an additional process. In the present embodiment, using the findings, the isolation trench  60  is formed by forming a trench whose depth is shallower than the isolation trench  50  between the p −  drain region  35  of the high withstand voltage MOS transistor  75 , and the n-type sinker  17 . 
         [0041]    As shown in  FIG. 2  and  FIG. 3 , a depth of the trench depends on an opening width of the trench. Therefore, by changing the opening widths of the trenches, trench structures having different depths can be formed at the same time without using an additional mask and an additional process. In the present embodiment, utilizing the findings, in the structure in which the n-type embedded layer  13  having a thickness “a” (=2 μm) is provided on the p-type silicon substrate  11 , and the n − -type epitaxial layer  15  having a thickness “b” (=7 μm) is provided on the n-type embedded layer  13 , for example, as shown in  FIG. 1 , a trench  59  having a trench opening width “c” (=1.8 μm), and a trench  67  having a trench opening width “e” (=0.4 μm), which is narrower than the trench  59 , are formed at the same time. The trench  59  having a trench opening width “c” (=1.8 μm) becomes a trench having a depth “d” (=10.8 μm) and reaching the p-type silicon substrate  11 , and the trench  67  having a trench opening width “e” (=0.4 μm) becomes a trench whose bottom isolates the surface connected by the n-type embedded layer  13  at the depth “f” (=7.18 μm). The shallow trench  67  is formed between the p −  drain region  35  of the high withstand voltage p-type MOS transistor  75  and the n-type sinker  17 , and thereafter, the trench is embedded with an insulator to form the insulation trench  60 . 
         [0042]    Next, a manufacturing method of a semiconductor device  100  according to the present embodiment is described in order of processes. 
         [0043]    First, the n-type embedded layer  13  of 1×10 18  cm −3  is formed on the p-type silicon substrate  11 . Then, an n − -type silicon (Si) semiconductor is epitaxially grown to form the n − -type epitaxial layer  15 . Subsequently, in order to provide the n-type embedded layer  13  with an electric potential, the sinker (DN)  17  that connects the n-type embedded layer  13  and the one principal face  10  is formed by photolithography and ion implantation techniques. Then, the field oxide films  21 ,  23  and  25  are formed by a well-known LOCOS technique. 
         [0044]    Thereafter, the insulation trench  60  and the isolation trench  50  are formed. The forming method is described below. The thickness “a” of the n-type embedded layer  13  is 2.0 μm, and the thickness “b” of the n − -type epitaxial layer  15  is 7.0 μm. 
         [0045]    First, the field oxide film  25  of the isolation region  73  used for the element isolation, and a silicon (Si) portion (including the n − -type epitaxial layer  15 , the n-type embedded layer  13 , and the p-type silicon substrate  11 ) therebelow are etched, and the field oxide film  23  of the element region  71  and a silicon portion (including the n − -type epitaxial layer  15 , the n-type embedded layer  13 , and the p-type silicon substrate  11 ) therebelow are etched, whereby the trench  59  and the trench  67  are formed at the same time. In this case, the opening width “c” of the trench  59  is 1.8 μm and the depth “d” thereof is 10.8 μm, while the opening width “e” of the trench  67  is 0.4 μm and the depth “f” thereof is 7.18 μm. 
         [0046]    Thereafter, a thermally oxidized film  51  is formed by thermal oxidation on an inner wall of the trench  59 , and a thermally oxidized film  61  is formed by thermal oxidation on an inner wall of the trench  67 . 
         [0047]    Then, 3×10 13 /cc of boron is implanted in the bottom portion of the trench  59  for preventing leakage, whereby a channel stopper  57  is formed. 
         [0048]    Then, the inner portions of the trenches  59 ,  67  are each embedded with an oxide film, and therefore, the LP-TEOS oxide films  53 ,  63  are formed at the same time, and thereafter, annealing is performed at 1000° C. in the atmosphere of nitrogen. 
         [0049]    Then, the LP-TEOS oxide films  55 ,  65  are further formed at the same time, and annealing is performed again at 1000° C. in the atmosphere of nitrogen. 
         [0050]    Then, a BPSG (Boron Phosphorus Silicon Glass) film is formed and the surface thereof is planarized, and thereafter, an etch back treatment of the oxide film is performed, whereby the insulation trench  60  and the isolation trench  50  are formed. 
         [0051]    Then, a transistor or the like (in this case, a high withstand voltage p-type MOS transistor  75 ) is formed in the element region  71  at the inner side of the isolation trench formed in the above-described manner. 
         [0052]    In the conventional structure as shown in  FIG. 4 , the distance “j” between the p + -type drain contact area  37  of the drain region  35  and the n + -type contact area  19  of the sinker  17  is, for example, 6 μm. However, in the present embodiment, by providing the isolation trench  60  between the p −  drain region  35  of the high withstand voltage p-type MOS transistor  75  and the n-type sinker  17 , the distance “i” between the p + -type drain contact area  37  of the drain region  35  and the N + -type contact area  19  of the sinker  17  can be reduced to, for example, 1.4 μm (0.4 μm (the opening width “e” of the trench  67 ) +0.5 μm (the width “g” of the field oxide film  23  at the side of the p −  drain region  35 ) +0.5 μm (the width “h” of the field oxide film  23  at the side of the n-type sinker  17 )=1.4 μm). As a result, the element region can be reduced by about 40% at the maximum without using an additional process and an additional mask. Further, the trench  59  for element isolation and the trench  67  for the insulation trench  60  formed between the drain region  35  and the sinker  17  can be formed at the same time by adjusting the respective opening widths “c”, “e” of the both trenches, and the number of manufacturing processes is reduced compared to a case in which the trenches are formed separately. Moreover, an insulator to be formed in the trench  59  and an insulator to be formed in the trench  67  can also be formed at the same time, which leads to reduction in the number of manufacturing processes.