Abstract:
A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip, a second semiconductor package stacked on the first semiconductor package, the second semiconductor package having at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip, and at least one signal connection member disposed in the first sealing member of the first semiconductor package, the at least one signal connection member electrically connecting the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority to Korean Patent Application No. 10-2009-0022748, filed on Mar. 17, 2009, the disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to a stack type semiconductor package apparatus, and more particularly, to a stack type semiconductor package apparatus having a signal connection member. 
         [0004]    2. Discussion of Related Art 
         [0005]    Package on Package (PoP) is an integrated circuit packaging technique to allow vertically combining discrete logic and memory ball grid array (BGA) packages. In PoP, semiconductor packages having various functions are stacked in a multi-layer structure. PoP may include a solder joint to electrically connect the semiconductor packages. 
         [0006]    In PoP, an upper surface and a lower surface of respective semiconductor packages may have different thermal expansion coefficients. Thus, when a temperature deviation caused by, for example, a high temperature, occurs to PoP, a semiconductor substrate of the PoP can be deformed. Then, an outer wall or a center part of the PoP becomes irregular due to the deformation of the semiconductor substrate. As a result, a defect of a solder joint disposed between semiconductor packages in a PoP may occur. 
       SUMMARY OF THE INVENTION 
       [0007]    According to an exemplary embodiment, a semiconductor device comprises a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip, a second semiconductor package stacked on the first semiconductor package, the second semiconductor package having at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip, and at least one signal connection member disposed in the first sealing member of the first semiconductor package, the at least one signal connection member electrically connecting the at least one first semiconductor chip with the leads of the at least one second semiconductor chip. 
         [0008]    The first semiconductor package may further comprise a circuit board receiving the at least one first semiconductor chip on a first surface of the circuit board, and the circuit board comprises joining pads formed thereon to receive the at least one signal connection member 
         [0009]    The circuit board may further comprise solder balls formed on a second surface, wherein the first surface and the second surface are substantially parallel with respect to a major axis of the circuit board. 
         [0010]    The at least one signal connection member can be vias formed through the first sealing member and formed on the joining pads. 
         [0011]    The vias may comprise via holes, and conductive paste can be filled in the via holes. 
         [0012]    Front end parts of the leads may contact with the vias. 
         [0013]    The circuit board may comprise wire connection pads connected to wires of the at least one first semiconductor chip. 
         [0014]    The at least one signal connection member can be a socket formed in the first sealing member and formed on each of the joining pads to receive a first end of each of the leads. 
         [0015]    The first semiconductor package may further comprise a redistribution layer formed on the at least one first semiconductor chip, and the redistribution layer may comprise joining pads formed thereon to receive the at least one signal connection member. 
         [0016]    The at least one signal connection member can be a via disposed in the first sealing member and can be formed on each of the joining pads. 
         [0017]    The at least one signal connection member can be a socket disposed in the first sealing member and can be formed on each of the joining pads to receive a first end of each of the leads. 
         [0018]    The socket may include a round space receiving a round-shaped first end of each of the leads. 
         [0019]    According to an exemplary embodiment of the present invention, a method of forming a semiconductor device comprises forming a first semiconductor chip on a first portion of a circuit board disposed in a first semiconductor package, forming joining pads on a second portion of the circuit board, forming a first sealing member on the first semiconductor chip and the joining pads, removing a portion of the first sealing member to expose the joining pads, filling the removed portion of the first sealing member with a conductive material, stacking a second semiconductor package having a lead on the first semiconductor package, wherein a first end of the lead is disposed in the second semiconductor package and a second end of the lead extends outwardly beyond the second semiconductor package, and inserting the second end of the lead into the conductive material of the first semiconductor package. 
         [0020]    Removing the portion of the first sealing member may include at least one of a laser perforation method, a perforation by molding method, a perforation by drilling method, or an etching perforation method using gas or chemicals. 
         [0021]    Inserting the second end of the lead into the conductive material may comprise a reflow process at high temperature. 
         [0022]    The conductive material may comprise a socket, and a method of inserting the second end of the lead into the conductive material may comprise inserting the second end into the socket. 
         [0023]    According to an exemplary embodiment of the present invention, a method of forming a semiconductor device comprises forming a first semiconductor chip on a circuit board disposed in a first semiconductor package, forming a redistribution layer on a top surface of the first semiconductor chip, forming a joining pad on the redistribution layer, forming a first sealing member on the first semiconductor chip, the redistribution layer, and the joining pad, removing a portion of the first sealing member to expose the joining pad, filling the removed portion of the first sealing member with a conductive material, stacking a second semiconductor package having a lead on the first semiconductor package, wherein a first end of the lead is disposed in the second semiconductor package and a second end of the lead extends outwardly beyond the second semiconductor package, and inserting the second end of the lead into the conductive material of the first semiconductor package. 
         [0024]    Removing the portion of the first sealing member may include at least one of a laser perforation method, a perforation by molding method, a perforation by drilling method, or an etching perforation method using gas or chemicals. 
         [0025]    Inserting the second end of the lead into the conductive material may comprise a reflow process at high temperature. 
         [0026]    The conductive material may comprise a socket, and a method of inserting the second end of the lead into the conductive material may comprise inserting the second end into the socket. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0027]    Exemplary embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0028]      FIG. 1  is a cross-sectional view of a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention; 
           [0029]      FIGS. 2 through 5  are cross-sectional views illustrating a method of manufacturing a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention; 
           [0030]      FIG. 6  is a cross-sectional view illustrating a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention; 
           [0031]      FIG. 7  is an enlarged cross-sectional view illustrating a signal connection member according to an exemplary embodiment of the present invention; 
           [0032]      FIG. 8  is a cross-sectional view of a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention; 
           [0033]      FIGS. 9 through 12  are cross-sectional views illustrating a method of manufacturing a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention; and 
           [0034]      FIG. 13  is a cross-sectional view of a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0035]    The present invention will now be described more fully with reference to the accompanying drawings in which example embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. 
         [0036]      FIG. 1  is a cross-sectional view of a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention.  FIGS. 2 through 5  are cross-sectional views illustrating a method of manufacturing a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention. 
         [0037]    Referring to  FIG. 1 , the stack type semiconductor package apparatus according to an exemplary embodiment includes a first semiconductor package  100 , a second semiconductor package  200  stacked on the first semiconductor package  100 , and signal connection members  10 . 
         [0038]    The first semiconductor package  100  includes first semiconductor chips  1  stacked in a multi-layer, a first sealing member  101  protecting the first semiconductor chips  1 , and a circuit board  103  where the first semiconductor chips  1  are disposed. 
         [0039]    The first semiconductor chips  1  are electrically connected to the circuit board  103  through, for example, wires  3 . In exemplary embodiments, various other signal transmission members are used to electrically connect the first semiconductor chips  1  with the circuit board  103 . 
         [0040]    Joining pads  105  and wire connection pads  106  are formed on the circuit board  103 . The wire connection pads  106  are connected to the wires  3  extended from the first semiconductor chips  1 . Solder balls  104  may be formed on the lower surface of the circuit board  103 . 
         [0041]    Referring to  FIG. 1 , the second semiconductor package  200  includes second semiconductor chips  2 , leads  202  electrically connected to the second semiconductor chips  2 , a second sealing member  201  covering the second semiconductor chips  2 . 
         [0042]    The second semiconductor chips  2  are electrically connected to each other through the leads  202  and the wires  3 . In exemplary embodiments, various other signal transmission members are used to electrically connect the second semiconductor chips  2  to each other. 
         [0043]    The signal connection members  10  are disposed in the first sealing member  101  of the first semiconductor package  100  to connect the first semiconductor chips  1  with the leads  202  of the second semiconductor chips  2  so that the second semiconductor package  200  may be stacked on the first semiconductor package  100 . In exemplary embodiments, various forms of signal connection members may be applied. For example, as illustrated in  FIG. 1 , vias  102 , which penetrate the first sealing member  101  and are formed on the joining pads  105 , may be applied. 
         [0044]    A method of manufacturing the vias  102  is described with reference to  FIGS. 2 through 5 . Referring to  FIG. 2 , the first semiconductor package  100  is prepared. Referring to  FIG. 3 , via holes  101   a  can be formed through the first sealing member  101  using, for example, a laser perforation method, a perforation by molding method, a perforation by drilling method, or an etching perforation method using gas or chemicals. 
         [0045]    The via holes  101   a  are positioned above the previously formed joining pads  105  so that the joining pads  105  are exposed before the via holes  101   a  are filled with a conductive material. 
         [0046]    Referring to  FIG. 4 , conductive paste is filled in the via holes  101   a . Referring to  FIG. 5 , front end parts of the leads  202  contact the vias  102  by, for example, a reflow process at high temperature. The front end parts of the leads  202  are substantially inserted into the vias  102 . In an exemplary embodiment, the front end parts of the leads  202  contact the joining pads  105 . As such, the second semiconductor package  200  is stacked on the first semiconductor package  100 . 
         [0047]      FIG. 6  is a cross-sectional view illustrating a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention. 
         [0048]    Referring to  FIG. 6 , sockets  302  are used as signal connection members  30 . 
         [0049]    The sockets  302  are formed on joining pads  305  by penetrating a first sealing member  301  and correspond to leads  402  so that the sockets  302  are forcibly engaged with the leads  402 . The shape of the leads  402  may vary according to exemplary embodiments of the present invention. For example, the leads  402  can be stick type leads. 
         [0050]      FIG. 7  is an enlarged cross-sectional view illustrating signal connection members according to an exemplary embodiment of the present invention. 
         [0051]    Referring to  FIG. 7 , a front end part of a lead  407  may be round in correspondence with the shape of a round hole formed in a socket  307  so that the lead  407  is forcibly engaged with the round hole formed in the socket  307 . 
         [0052]    The stack type semiconductor package apparatus described above with reference to  FIGS. 1 through 5  has a fan-out type package on package (POP) structure in which the signal connection members  10  are expanded to the outside beyond the size of the first semiconductor chips  1 . 
         [0053]    In an exemplary embodiment, the stack type semiconductor package apparatus may have a fan-in type POP structure in which a signal connection member is disposed within first semiconductor chips. 
         [0054]      FIG. 8  is a cross-sectional view of a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention.  FIGS. 9 through 12  are cross-sectional views illustrating a method of manufacturing a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention. 
         [0055]    Referring to  FIG. 8 , a first semiconductor package  500  includes a redistribution layer  507  formed on the first semiconductor chips  1 , wherein the redistribution layer  507  includes joining pads  508  formed thereon to connect to signal connection members  50 . 
         [0056]    As the signal connection members  50 , vias  502  are used. Vias  502  are formed through a first sealing member  501 . The vias  502  are formed on the joining pads  508 . In an exemplary embodiment, as illustrated in  FIG. 6 , the sockets  302  may be used as the signal connection members  50 . Referring to  FIG. 6 , the sockets  302  are formed on the joining pads  305  by penetrating the first sealing member  301  and correspond to the front end parts of the leads  402 , thereby being forcibly engaged with the leads  402 . 
         [0057]    A method of manufacturing the vias  502  is described with reference to  FIGS. 9 through 12 . Referring to  FIG. 9 , the first semiconductor package  500  including the redistribution layer  507  and the joining pads  508  are prepared. Referring to  FIG. 10 , via holes  501   a  are formed through the first sealing member  501  using, for example, a laser perforation method, a perforation by molding method, a perforation by drilling method, or an etching perforation method using gas or chemicals. 
         [0058]    The via holes  501   a  are positioned above the previously formed joining pads  508  so that the joining pads  508  are exposed before the via holes  501   a  are filled with a conductive material in a subsequent process. 
         [0059]    Referring to  FIG. 11 , conductive paste is filled in the via holes  501   a . Referring to  FIG. 12 , front end parts of leads  602  of a second semiconductor package  600  contact and are received by the vias  502  by, for example, a reflow process at high temperature. In an exemplary embodiment, the front end parts of leads  602  contact joining pads  508 . 
         [0060]      FIG. 13  is a cross-sectional view of a stack type semiconductor package apparatus according to an exemplary embodiment of the present invention. 
         [0061]    Referring to  FIG. 13 , leads  802  are bent several times and are extended to connect to a center portion of joining pads  708  on a redistribution layer  707 . In exemplary embodiments, various shapes of leads can be formed to electrically connect the first semiconductor package  700  with the second semiconductor package  800 . 
         [0062]    According to exemplary embodiments of the present invention, a defect of a solder joint occurring due to deformation of a substrate generated according to temperature deviation while stacking semiconductor packages can be prevented. 
         [0063]    According to exemplary embodiments of the present invention, a stack type semiconductor package apparatus includes signal connection members disposed between semiconductor packages. 
         [0064]    According to exemplary embodiments of the present invention, a joining pad is disposed on a circuit board and thus conductivity thereof is improved, and a socket is applied thereto and thus the semiconductor packages are easily coupled and detached from each other. 
         [0065]    Although the exemplary embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the present invention should not be limited to those precise embodiments and that various other changes and modifications may be affected therein by one of ordinary skill in the related art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.