Abstract:
A method to reduce a peak power consumption of an optical transceiver including a thermoelectric cooler (TEC) is disclosed. The transceiver includes three power units, one of which powers the temperature control unit including the TEC driver and the TEC, second one of which powers the transmitter unit including an LD and an LD driver, and the last of which powers the receiver unit. Once the transceiver is set in the host system, the transceiver first activates the first and second power units to start up the temperature control unit and the transmitter unit, and subsequently, the transceiver sets up the third power unit after the temperature of the LD is stabilized at a target temperature.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Filed of the Invention 
         [0002]    The present invention relates to an optical transceiver, in particular, the invention relates to a configuration that reduces the peak power consumption. 
         [0003]    2. Related Prior Art 
         [0004]    Recent optical transceiver installs a thermo-electric controller (TEC) to control a temperature of a semiconductor laser diode (LD). A Japanese Patent Application published as JP-2006-054316A has disclosed an optical apparatus that provides a plurality of optical modules. When respective modules in the apparatus begins their operation, a larger driving current for the TEC installed in the module flows as the temperature of the LD shows a large different with respect to the target temperature requested from the condition of the apparatus. The prior art above has disclosed an optical apparatus, in which respective modules begin to operate one by one with a substantial delay. Accordingly, the optical apparatus may reduce the peak power consumption. 
         [0005]    However, even the method disclosed in the prior art, the power consumption of each module is not decreased yet, so the total power consumption in the optical apparatus still remains in high. 
       SUMMARY OF THE INVENTION 
       [0006]    An aspect of the present invention relates to an optical transceiver, which is hot-pluggable with a host system, includes a temperature unit, transmitter unit, and a receiver unit each powered with first to third power units independently operated to each other, respectively. These three power units are powered with the host system when the transceiver is installed therein, and a feature of the transceiver of the invention is that these three power units have timings different from each other to be,activated, or at least one of the power units is delayed its operation from the begging of the operation of the other two power units. Because the power units have different timings to operate, or at least one of power unit is delayed its operation, the peak power consumption of the transceiver may be reduced. 
         [0007]    Preferably, the third power unit that powers the receiver unit delays its operation from the other two power units. Further preferably, the third power unit operates after the first power unit stabilizes its current output that powers the temperature control unit. That is, the third power unit preferably begins to operate after the first power unit stabilizes the temperature of the laser diode in the transmitter unit. 
         [0008]    Further, the transceiver may include a controller powered with one of the first or the second power unit. This controller may control the third power unit so as to delay the operation thereof from the operation of the other two power units. The first power unit powers the temperature control unit that consumes relatively larger current compared with the transmitter unit and the receiver unit because the first power unit is necessary to stabilize the temperature of the laser diode. While, the third power unit powers the receiver unit that consumes relatively small current. Therefore, by delaying the operation of the third power unit from the first power unit; the peak power consumption of the transceiver may be reduced by the power provided to the receiver unit. 
         [0009]    Moreover, the controller of the invention may control the temperature of the laser diode by monitoring a current temperature, comparing it with a target temperature, and sending a command to the third power unit when the controller decides the current temperature becomes the target temperature within a preset range. Thus, in the present transceiver, because the controller delays the operation of the third power unit until the temperature of the LD becomes the target temperature, the peak power consumption at the beginning of the operation of the transceiver may be reduced. 
         [0010]    Another aspect of the invention relates to a method to start the operation of the optical transceiver that provides a temperature control nit, a transmitter unit, and a receiver unit each powered with an independent power unit. When the transceiver is installed on the host system and the host system powers these power units simultaneously, the transceiver activates these power units sequentially; or at least one of the power units is delayed its operation from the other two power units. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]      FIG. 1  schematically illustrates a block diagram of an optical transmitter; 
           [0012]      FIG. 2  illustrates a circuit diagram of the first and second power unit; 
           [0013]      FIG. 3  illustrates a circuit diagram of the third power unit; 
           [0014]      FIG. 4  illustrates a procedure until activating the third power unit; 
           [0015]      FIG. 5  illustrates a time charts of voltage signals in the transmitter; and 
           [0016]      FIG. 6  illustrates a time charts of current signals in the transmitter. 
       
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0017]    Next, preferred embodiments according to the present invention will be described as referring to accompanying drawings. In the drawings, the same numerals or the same symbols will refer to the same elements without overlapping explanations. 
         [0018]      FIG. 1  schematically illustrates a block diagram of an optical transceiver  1 . This transceiver  1  provides a function of, what is called, the hot-pluggable with respect to the host system, which is not involved in  FIG. 1 , where the optical transceiver  1  is able to electrically couple with the host system without shutting the host system down. The optical transceiver comprises an electrical connector  2 , power unit,  31  to  33 , a transmitter unit  41  and a receiver unit  42 . 
         [0019]    The connector  2  provides terminals,  2   a  and  2   d,  to receive the electrical power from the host system, a terminal  2   f  to output an electrical signal to the host system, a terminal  2   c  to receive another electrical signal from the host system, and ground terminals,  2   b  and  2   e,  for the transmitter unit  41  and the receiver unit  42 , respectively. Two power units,  31  and  32 , provide the electrical power to the temperature control unit and the transmitter unit  41 , while, the last power unit  33  supplies the electrical power to the receiver unit  42 . 
         [0020]    The first and second power units,  31  and  32 , are connected with the Tx power terminal  2   a  through which the power units,  31  and  32 , are powered from the host system. While, the third power unit  33  is connected with the Rx power terminal  2   d  through which the power unit  33  is powered from the host system. As described later in this specification, the third power unit  43  for the receiver unit delays its operation from the operation of the other two power units,  31  and  32 . 
         [0021]    The transmitter unit  41  includes a transmitter optical sub-assembly (TOSA), an LD driver  9 , a TEC driver  10 , a comparator  12 , a digital-to-analogue converted (D/A-C)  14 , and a central processing unit (CPU)  16 . The TEC driver  10  and the comparator  12 , where they constitutes a temperature control unit, are connected with the first power unit  31 , while, the LD driver  8 , the D/A-C  14  and the CPU  16  are connected with the second power unit  32 . 
         [0022]    The TOSA  6  may optically couple with an optical fiber to is transmit signal light to this optical fiber. The TOSA  6  installs an LD  6   a,  a thermistor  6   b,  and a TEC  6   c.  The thermistor  6   b  senses a temperature of the LD  6   a.  The TEC  6   c,  which is connected with the TEC driver  10 , controls the temperature of the LD  6   a.  The LD driver  8  drives the LD  6   a,  that is, the LD driver  8  controls an optical emission of the LD  6   a  by providing the driving current that corresponds to the transmission signal sent from the host system through the signal terminal  2   c.    
         [0023]    The TEC driver  10 , connected with the TEC  6   c  and the comparator  12 , drives the TEC  6   c,  in other words, controls a temperature of the TEC  6   c,  depending on a signal sent from the amplifier  16 . The comparator  12 , connected with the thermistor  6   b,  the TEC driver  10  and the D/A-C  14 , and configured with the differential circuit, compares a signal A 1  that indicates a current temperature of the LD  6   a  output from the thermistor  6   b  with a reference signal A 3  that indicates a target temperature of the LD  6   a,  which is output from the CPU  16  through the D/A-C  14 , and outputs a control signal to the TEC driver  10  so as to set the temperature of the LD  6   a  to the target temperature within a preset range. 
         [0024]    The CPU  16 , connected with the D/A-C  14  and the third power unit  33 , outputs a command to activate the third power unit  33  after the CPU  16  is powered with the second power unit  32 . That is, the CPU  16  advances the procedure shown in  FIG. 4  after it is powered with the second power unit  32 . The CPU  16  monitors the current temperature of the LD  6   a  by the signal A 1  and decides whether the temperature of the LD  6   a  becomes the target temperature within the preset range. The CPU  16  sends the signal A 2  to the third power unit  33  to power the receiver unit  42  after the CPU decides that the temperature LD  6   a  becomes stable within the present range around the target temperature. The CPU  16  provides an output port  16   a  through which the signal A 2  is sent to the third power unit  33 . This port  16   a  is held in high-impedance until the initializing procedure of the CPU  16  is completed. 
         [0025]    The receiver unit  42  includes a receiver optical sub-assembly (ROSA), a main amplifier  22 , another D/A-C.  24  and a DC/DC converter  26 . The ROSA  26  includes an avalanche photodiode (APD) and a trans-impedance amplifier (TIA)  20   b.  The main amplifier  22  has a function of a limiting amplifier. The TIA  20   b,  the main amplifier  22  and the DC/DC converter  26  are powered with the thirdpower unit  33 , while, the D/A-C  24  is powered with the second power unit  32 . 
         [0026]    The ROSA  20  may optically couple with an optical fiber, which is not illustrated in  FIG. 1 , to receive an optical signal therefrom. The APD  20   a,  connected with the TIA 20   b  and he DC/DC converter  26 , detects the optical signal by being supplied with a bias from the DC/DC converter  26 , a magnitude of which is controlled by the CPU  16  through the D/A converter  24 . The APD  20   a  outputs a photocurrent corresponding to a magnitude of the optical signal to the TIA  20   b.    
         [0027]    The TIA  20   b,  connected with the APD  20   a  and the main amplifier  22 , converts this photocurrent into a voltage signal and outputs this voltage signal to the main amplifier  22 . The main amplifier  22  amplifies the voltage signal, but the output thereof is limited to a preset voltage. The main amplifier outputs this limited signal to the terminal  2   f  of the connector  2 . 
         [0028]    Next, the first power unit  31  will be described in detail as referring to  FIG. 2 . The configuration of the second power unit  32  is is the same with the first one  31  shown in  FIG. 2 . This power unit  31  includes a capacitor  3   a,  a resistor  3   b,  and a p-type MOSFET  3   c.  The p-MOSET  3   c  is connected between the input and the output terminals of the power unit  31 , that is, the source terminal of the p-MOSFET is connected to the input terminal that receives the power from the Tx power terminal  2   a,  while the drain terminal of the p-MOSFET is connected with the output teminal. The capacitor  3   a  is connected between the input terminal and the gate terminal of the p-MOSFET  3   c,  while, the resistor  3   b  is connected between the gate terminal of the p-MOSFET and the ground. 
         [0029]    When the transceiver  1  is installed in the host system, the first power unit  31  receives a step-like power through the Tx power terminal  2   a.  The source terminal and the gate terminal of the p-MOSFET follow this step-like power; subsequently, only the gate terminal decreases its voltage level because the gate terminal is coupled with the input terminal through the capacitor  3   a.  That is, the capacitor  3   a  and the resistor  3   b  operate as a differentiator circuit. Following this decrease of the gate level, the p-MOSFET  3   c  gradually turns on and increases the current flowing from the source to the drain terminals thereof. Thus, even the step-like power is applied, the first power unit  31  may gradually increase the electric power, namely the output current, for the transmitter unit  41 , which may effectively suppress the rush current appeared in the transmitter unit  41 . 
         [0030]    Next, the third power unit  33  will be described in detail as referring to  FIG. 3 . The third power unit  33  includes two resistors,  33   a  and  33   b,  a capacitor  33   c,  an n-type MOSFET  33   d,  a resistor  33   e,  and a p-type MOSFET  33   f.  The p-MOSFET  33   f  is connected between the input and the output terminals of the power unit  33 , while, the n-MOSFET  33   d  operates as an inverter to amplify the command A 2  output from the port  16   a  of the CPU  16 . The n-MOSFET is biased with the Rx power terminal  2   d  thorough the resistor  33   e  and drives the p-MOSFET  33   d  by thus amplified command. The resistor  33   b  and the capacitor  33   c  constitute an integrating circuit to integrate the command A 2 . The resistor  33   a  is a pull-down resistor to ground the gate of the n-MOSFET when the output port  16   a  of the CPU is high-impedance. In this state, the n-MOSFET  33   d  is turned off and the gate level of the p-MOSFET  33   f  is pulled up to the power terminal  2   d  by the resistor  33   e,  so the p-MOSFET  33   f  is also turned off. 
         [0031]    When the transceiver  1  is set on the host system and the step-like power appears at the Rx power terminal  2   d  but the initial procedure of the transmitter unit  41  is uncompleted, in which the CPU  16  does not send the command A 2  to the third power unit  33  from the port  16   a,  the gate terminal of the n-MOSFET  33   d  is pulled down to the ground, while, the gate terminal of the p-MOSFET is pulled up to the Rx power supply. Accordingly, the receiver unit  42  is not powered with the third power unit  33 . Completing the initial procedure in the transmitter unit  41  and the CPU enables its output port  16   a,  whose level becomes the HIGH level; the gate level of the n-MOSFET  33   d  gradually increases by the integrating circuit of the resistor  33   b  and the capacitor  33   c.  Following the increase of the gate level, the current flowing between the drain and source terminals of the n-MOSFET  33   d  gradually increases, the drain level thereof, which is equivalent to the gate level of the p-MOSFET  33   f,  gradually decreases by the voltage drop at the resistor  33   e.  Finally, the p-MOSFET turns on and the third power unit  33  powers the receiver unit  42 . 
         [0032]    Thus, even when the third power unit  33  is powered through the power terminal  2   d  of the connector  2 , the power unit  33  is held inactive until the third power unit  33  receives the command A 2  from the CPU  16 . Setting the transceiver  1  on the host system and stabilizing the outputs of the first and the second power unit,  31  and  32 , and receiving the command A 2  from the CPU  16 , the third power unit  33  gradually powers the receiver unit  42 . 
         [0033]    Next, the initial procedure carried out by the CPU  16  will be described as referring to  FIG. 4 . The CPU  16 , after being powered with the second power unit  32  (step S 1 ), outputs a reference signal A 3  to the comparator  12  through the D/A-C  14  at step S 2 . This reference signal corresponds to the target temperature of the LD  6   a.  Then, the CPU  16  receives a monitored signal A 1  that indicates a current temperature of the LD  6   a  sensed by the thermistor  6   b  and compares this monitored signal A 1  with the reference signal A 3  at step S 4 . In the case that the CPU  16  judges the current temperature of the LD  6   a  is within a preset range around the target temperature, the CPU outputs the command A 2  to the third power unit  33  to operate it, which is indicated as YES in  FIG. 4 . The third power unit  33 , as described above, activates its output to power the receiver unit  42 . 
         [0034]    On the other hand, in the case the CPU judges the current temperature of the LD  16   a  is out of the preset range, the CPU iterates the procedures to receive the current temperature of the LD  6   a  from the thermistor  6   b,  step S 3 , and compares it with the target temperature, step S 4 , until the current temperature becomes the target temperature within the preset range. 
         [0035]    Next, the operation of the transceiver  1  will be described as referring to  FIGS. 5 and 6 .  FIG. 5  is time charts of voltage signals within the transceiver  1 , while,  FIG. 6  is time charts of current signals. The behavior L 1  in  FIG. 6  corresponds to the power supplied from the host system through the Tx power terminal  2   a  and the Rx power terminal  2   d  in step-like, the behavior L 2  denotes the current output from the third power unit  33  to the receiver unit  42 , the behavior L 3  denotes the current output from the second power unit  32  to the transmitter unit  41 , the behavior L 4  corresponds to the current output from the first power unit  31  to the temperature control unit in the transmitter unit  41 , and the behavior L 5  denotes the total current that sums the currents from L 2  to L 4 . 
         [0036]    First, at the timing T 1  when the transceiver  1  is set on the host system and the power is supplied in step-like to the transceiver  1  through the terminals,  2   a  and  2   d,  the output of the third power unit  33  is held zero, because the gate level of the n-MOSFET  33   d  is set low, while that of the p-MOSFET  33   f  is set high. On the other hand, the current output from the first and second power units,  31  and  32 , which corresponds to the currents indicated by L 4  and L 3 , respectively, gradually increases from the timing T 1 . As illustrated in  FIG. 6 , the current L 4  output from the first power unit  31  is larger than that from the second power unit  32 , because the first power unit  31  supplies the power to the TEC driver  10  and the comparator  12 , where these units,  10  and  12 , consume relatively larger power until the temperature of the LD  6   a  becomes the target temperature within the preset range and is stabilized thereat. 
         [0037]    At the timing T 2 , the current L 3  output from the second power unit  32  becomes stable, for instance around 80 mA, the CPU  32 , which is powered with the second power unit  32 , begins its initial routine, is but the output port  16   a  thereof is still held in high-impedance and the gate level of the n-MOSFET  33   d  is set low even after the timing T 2  because the temperature of the LD  6   a  is not stabilized at the target temperature. 
         [0038]    After the timing T 2 , the temperature of the LD  6   a  becomes stable around the target temperature, which stabilizes the current output from the first power unit  31  around 130 mA, the CPU  16  sets the output  16   a  thereof in HIGH level at the timing T 3 . This output signal from the port  16   a  corresponds to the command A 2 . Steps from S 1  to S 3  in  FIG. 4  are carried out after the timing T 2 , when the CPU  16  begins its normal operation, and step S 5  in  FIG. 4  is carried out at the timing T 3 . 
         [0039]    The gate level of the n-MOSFET  33   d  gradually increases responding to the transition of the port  16   a  from the high impedance to the HIGH level, and the output of the third power unit  33  gradually increases responding to the decrease of the gate level of the p-MOSFET  33   d  after the timing T 3 . After the gate level of the n-MOSFET  33   d  becomes stable in HIGH level and the gate level of the p-MOSFET becomes in LOW level, the output current L 2  from the third power unit  33  becomes stable around 60 mA at the timing T 4 . Thus, the power unit  33  becomes active after the timing T 3  and stabilizes its output at the timing T 4 . 
         [0040]    In the present optical transceiver, the timing when the third power unit  33  becomes active is delayed from the timing when the first power unit  31  and the second power unit  32  operate. That is, the third power unit  33  powers the receiver unit  42  after the first and second power units,  31  and  32 , power the transmitter unit  41 . Specifically, the third unit  33  operates after (1) the first power unit  31  powers the transmitter unit  41  and stabilizes its current around 130 mA and (2) the temperature of the LD  6   a  becomes the target temperature within the preset range. 
         [0041]    In a conventional transceiver, the unit to power the transmitter unit and the other unit to power the receiver unit begin their operation at the same time just after the transceiver is set in the host system. The current supplied to the transceiver shows a peak just after the timing when the transceiver  1  is set in the host system. While, the transceiver according to the present invention, because the CPU  16  delays the operation of the power unit  33  from the operation of the first and second power units,  31  and  32 , as shown in  FIG. 6 , the peak power necessary for the host system when the transceiver  1  is set thereon may be reduced. 
         [0042]    While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.