Abstract:
Method and system for facilitating testing of multiple time-division-duplex (TDD) data packet signal transceivers. Replicas of a data packet signal are transmitted by a tester to multiple TDD devices under test (DUTs), where the replicated signal is either a null or TDD data packet signal. In one embodiment, replica null data packet signals are transmitted for a predetermined time interval sufficient for the DUTs to synchronize with the tester. In another embodiment, following successful and unsuccessful receptions of responsive signals from respective DUTs indicating successful reception of their respective replica TDD data packet signals and, therefore, synchronization with the tester, corresponding replica TDD data packet signals are provided with data packet signal characteristics causing such replica data packet signals to fail to conform or to conform, respectively, with a predetermined data packet signal standard. Following synchronization, test and responsive data packet signals can be exchanged between the tester and DUTs.

Description:
BACKGROUND 
     The present invention relates to testing of data packet signal transceivers, and in particular, to systems and methods for parallel testing of multiple such devices. 
     Many of today&#39;s electronic devices use wireless technologies for both connectivity and communications purposes. Because wireless devices transmit and receive electromagnetic energy, and because two or more wireless devices have the potential of interfering with the operations of one another by virtue of their signal frequencies and power spectral densities, these devices and their wireless technologies must adhere to various wireless technology standard specifications. 
     When designing such devices, engineers take extraordinary care to ensure that such devices will meet or exceed each of their included wireless technology prescribed standard-based specifications. Furthermore, when these devices are later being manufactured in quantity, they are tested to ensure that manufacturing defects will not cause improper operation, including their adherence to the included wireless technology standard-based specifications. 
     For testing these devices following their manufacture and assembly, current wireless device test systems employ a subsystem for analyzing signals received from each device. Such subsystems typically include at least a vector signal analyzer (VSA) for analyzing signals produced by the device, and a vector signal generator (VSG) for generating signals to be received by the device. The analyses performed by the VSA and the signals generated by the VSG are generally programmable so as to allow each to be used for testing a variety of devices for adherence to a variety of wireless technology standards with differing frequency ranges, bandwidths and signal modulation characteristics. 
     Among the wireless technologies being tested are those where the transmitters and receivers of the devices operate on the same frequency. One such operation is time-division-duplex (TDD), with one increasingly common example known as Bluetooth. When performing simultaneous testing of two or more such devices employing TDD technologies, there is a possibility of error caused during testing due to variations in the start times of the devices. For example, in one scenario, one or more devices may synchronize to a response data packet generated by another device under test (DUT) rather than responding to the intended test data packet generated by the tester (e.g., by the VSG). As a result, a DUT that becomes synchronized to the wrong signal will remain so and, therefore, produce erroneous or invalid test results. 
     Accordingly, a method for synchronizing multiple TDD DUTs that avoids such improper synchronization scenarios would advantageously reduce faulty device synchronization and test time, and thereby reduce overall testing costs on a per device basis. 
     SUMMARY 
     In accordance with the presently claimed invention, a method and system are provided for facilitating testing of multiple time-division-duplex (TDD) data packet signal transceivers. Replicas of a data packet signal are transmitted by a tester to multiple TDD devices under test (DUTs), where the replicated signal is either a null or TDD data packet signal. In one embodiment, replica null data packet signals are transmitted for a predetermined time interval sufficient for the DUTs to synchronize with the tester. In another embodiment, following successful and unsuccessful receptions of responsive signals from respective DUTs indicating successful reception of their respective replica TDD data packet signals and, therefore, synchronization with the tester, corresponding replica TDD data packet signals are provided with data packet signal characteristics causing such replica data packet signals to fail to conform or to conform, respectively, with a predetermined data packet signal standard. Following synchronization, test and responsive data packet signals can be exchanged between the tester and DUTs. 
     In accordance with an exemplary embodiment of the presently claimed invention, a method of facilitating testing of multiple time-division-duplex (TDD) data packet signal transceivers includes: 
     providing a plurality of outgoing data packet signals for a plurality of TDD data packet signal transceivers, wherein each one of said plurality of outgoing data packet signals corresponds to a common data packet signal comprising at least one of
         a null data packet signal, and   a TDD data packet signal with a data packet signal characteristic;       

     when said common data packet signal comprises a null data packet signal, continuing to provide said plurality of outgoing data packet signals for a predetermined time interval; and 
     when said common data packet signal comprises a TDD data packet signal, responding to successful and unsuccessful receptions of respective ones of a plurality of responsive signals from said plurality of TDD data packet signal transceivers by providing one or more of said plurality of outgoing data packet signals, wherein
         each one of said plurality of responsive signals is indicative of a successful reception of a valid data packet by a corresponding one of said plurality of TDD data packet signal transceivers, and   following a successful reception of one of said plurality of responsive signals from a corresponding one of said plurality of TDD data packet signal transceivers, a corresponding one of said plurality of outgoing data packet signals is provided with said data packet signal characteristic such that said corresponding one of said plurality of outgoing data packet signals fails to conform with a predetermined data packet signal standard, and   following an unsuccessful reception of one of said plurality of responsive signals from a corresponding one of said plurality of TDD data packet signal transceivers, a corresponding one of said plurality of outgoing data packet signals is provided with said data packet signal characteristic such that said corresponding one of said plurality of outgoing data packet signals conforms with said predetermined data packet signal standard.       

    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a conventional test environment for testing multiple DUTs in parallel. 
         FIG. 2  depicts a testing environment for testing multiple DUTs in parallel in accordance with an exemplary embodiment of the presently claimed invention. 
         FIG. 3  depicts a testing environment for testing multiple DUTs in parallel in accordance with another exemplary embodiment of the presently claimed invention. 
         FIG. 4  depicts a testing environment for testing multiple DUTs in parallel in accordance with another exemplary embodiment of the presently claimed invention. 
         FIG. 5  depicts a testing environment for testing multiple DUTs in parallel in accordance with another exemplary embodiment of the presently claimed invention. 
         FIG. 6  depicts an exemplary embodiment of the signal characteristic control circuitry of  FIGS. 4 and 5 . 
         FIG. 7  depicts another exemplary embodiment of the signal characteristic control circuitry of  FIGS. 4 and 5 . 
         FIG. 8  depicts another exemplary embodiment of the signal characteristic control circuitry of  FIGS. 4 and 5 . 
         FIG. 9  depicts circuitry for conveying test signals to and confirmation signals from the DUTs in accordance with an exemplary embodiment of the presently claimed invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is of example embodiments of the presently claimed invention with references to the accompanying drawings. Such description is intended to be illustrative and not limiting with respect to the scope of the present invention. Such embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the subject invention, and it will be understood that other embodiments may be practiced with some variations without departing from the spirit or scope of the subject invention. 
     Throughout the present disclosure, absent a clear indication to the contrary from the context, it will be understood that individual circuit elements as described may be singular or plural in number. For example, the terms “circuit” and “circuitry” may include either a single component or a plurality of components, which are either active and/or passive and are connected or otherwise coupled together (e.g., as one or more integrated circuit chips) to provide the described function. Additionally, the term “signal” may refer to one or more currents, one or more voltages, or a data signal. Within the drawings, like or related elements will have like or related alpha, numeric or alphanumeric designators. Further, while the present invention has been discussed in the context of implementations using discrete electronic circuitry (preferably in the form of one or more integrated circuit chips), the functions of any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed. Moreover, to the extent that the figures illustrate diagrams of the functional blocks of various embodiments, the functional blocks are not necessarily indicative of the division between hardware circuitry. 
     In accordance with exemplary embodiments of the presently claimed invention, a method is provided for testing TDD devices simultaneously while avoiding improper tester-DUT synchronization. In one exemplary embodiment, using a test system, or tester, capable of replicating VSG signals simultaneously for sending to multiple TDD devices, and a demultiplexing subsystem for receiving response signals from the multiple TDD devices using a single VSA, the VSG sends sets of null data packets to the multiple TDD devices until a predetermined synchronization time interval has elapsed. This synchronization time interval is chosen to allow properly operating TDD devices to become ready for testing. Once this synchronization time interval has elapsed, the tester can begin sending sets of predefined test data packets to the devices and begin receiving response data packets from the devices, or, alternatively, the TDD devices can begin sending sets of predefined test data packets to the tester and receiving response data packets from the tester. 
     In another exemplary embodiment, the tester replicates the VSG signal for simultaneous transmission to multiple TDD devices and imparts signal characteristic control such that individual data packet signals can be corrupted so as to make them non-receivable by their corresponding TDD devices, e.g., by reducing the power level of a replicated VSG signal below a threshold level. Also included is a multiplexing subsystem for receiving the response signals from the multiple TDD devices for conveyance to the VSA of the tester, and for detecting reception of null data packets from the devices and communicating with the signal characteristic control subsystem for controlling the power levels of the respective replicated VSG signals. 
     As discussed in more detail below, the tester sends a set of replicated predefined synchronization data packets to the multiple TDD devices. Those devices ready to receive such data packets respond by returning null data packets. The tester detects which devices have returned such null data packets and communicates the status of returned and non-returned null data packets to the signal characteristic control subsystem. As a result, subsequent sets of the predefined synchronization data packets are sent to the TDD devices as before, but those synchronization data packets being sent to the TDD devices that have identified their readiness for testing by returning a null data packet are corrupted (e.g., by markedly reducing signal power following initiation of the data packet transmission and prior to termination of data packet transmission). Meanwhile, the replicated data packets sent to those TDD devices that had not yet identified their readiness for testing by sending a null data packet are transmitted in accordance with the applicable signal standard, i.e., they are not corrupted. As a result, those TDD devices that are not yet ready for testing continue to receive synchronization data packets until they do indicate readiness for testing, and, therefore, will not improperly synchronize to responsive null data packets generated by another DUT indicating its readiness for testing, since the DUTs that are ready for testing are receiving corrupted data packets and will, therefore, produce no responsive null data packets. Once all DUTs have indicated their readiness for testing by having replied with a null data packet, synchronization is complete and the tester may now begin sending predefined test data packets to and receiving responsive data packets from the DUTs, or, alternatively, the DUTs can begin sending sets of predefined test data packets to and receiving response data packets from the tester. 
     Exemplary embodiments of the presented claimed invention are discussed below in the context of a testing environment in which a single tester is used for testing multiple devices under test (DUTs). In the particular examples discussed, the testing environment includes three DUTs. However, it should be readily understood that the testing of three DUTs is merely exemplary and that the presently claimed invention can be practiced for any multiple (i.e., two or more) of DUTs. 
     Referring to  FIG. 1 , a conventional testing environment includes a test system, or “tester”,  100  for testing multiple DUTs  200 , e.g., three DUTs  200   a ,  200   b ,  200   c . The tester  100  includes a VSG  102  and VSA  104  for providing a VSG test signal  101  and receiving a multiplexed DUT signal  115 , respectively. Also included is signal routing or replication circuitry  112  (e.g., a power splitter) for replicating the VSG signal  101  to provide multiple replicated VSG signals  113   a ,  113   b ,  113   c  for the DUTs  200 . The responsive signals  201   a ,  201   b ,  201   c  from the DUTs  200  are conveyed to the VSA  104  via additional signal routing circuitry  114 , e.g., a multiplexor, which can be controlled by one or more control signals (not shown) provided by the tester  100  or an external controller (not shown). 
     As will be readily appreciated by one of ordinary skill in the art, and as discussed in more detail below, the respective signal paths for the replicated VSG signals  113   a ,  113   b ,  113   c  and responsive DUT signals  201   a ,  201   b ,  201   c  are shared, e.g., a single wired signal path is used to convey a test signal  113   a / 113   b / 113   c  to a DUT  200   a / 200   b / 200   c  and also convey the DUT signals  201   a / 201   b / 201   c.    
     In accordance with well known principles, the testing system begins transmitting the replicated VSG signals  113   a ,  113   b ,  113   c  and, at various subsequent points in time, the various DUTs  200   a ,  200   b ,  200   c  become ready for testing and indicate such readiness by responding with a null data packet. In this example, the first DUT  200   a  is the first one to become ready  203   a  for testing, followed soon thereafter by the second DUT  200   b  becoming ready for testing  203   b . Accordingly, after a first time slot  205   a  the first  200   a  and second  200   b  DUTs transmit responsive null data packets, thereby indicating their respective states of readiness for testing. However, when the third DUT  200   c  is finally ready for testing  203   c , the first signal it sees is an attenuated version of one of the response null data packets from one of the other DUTs  200   a ,  200   b  (e.g., due to some form of signal leakage). However, since the third DUT  200   c  is expecting to receive a TDD data packet, but instead receives an attenuated null data packet, its responsive signal  201  c does not indicate readiness by the third DUT  200   c  for testing. Hence, while the other DUTs  200   a ,  200   b  have properly synchronized with the tester  100  and are properly responding to TDD data packets  113   a ,  113   b  with responsive null data packets  201  a,  201   b , the third DUT  200   c , though ready for testing, is improperly synchronized with a leaked null data packet signal instead of its TDD data packet signal  113   c.    
     Referring to  FIG. 2 , in accordance with an exemplary embodiment of the presently claimed invention, VSG  102  provides a VSG signal  101  containing sets of null data packets during a predetermined synchronization time interval  207   a . During this time interval  207   a , the DUTs  200   a ,  200   b ,  200   c  receive a number of the replicated null data packets  113   a ,  113   b ,  113   c  and become ready for testing  203   a ,  203   b ,  203   c . Though now ready for testing, the null data packets  113   a ,  113   b ,  113   c  from the tester  100  evoke no responses  201   a ,  201   b ,  201   c  from the DUTs  200   a ,  200   b ,  200   c . Following this time interval  207   a , the tester  100  can begin sending predefined test data packets during a receive test interval  209   r , in response to which the DUTs  200   a ,  200   b ,  200   c  return null data packet signals  201   a ,  201   b ,  201   c . Alternatively, the DUTs  200   a ,  200   b ,  200   c  can begin sending sets of test data packets to the tester  100  and receive responsive data packets from the tester  100  in return (not shown). 
     Referring to  FIG. 3 , in accordance with another exemplary embodiment, following the synchronization time interval  207   a , the tester  100  can perform a transmit test  209   t  in which the replicated VSG signals  113   a ,  113   b ,  113   c  contain TDD data packets, in response to which the DUTs  200   a ,  200   b ,  200   c  return duplicates of such data packets, i.e., loop-back data packets. 
     Referring to  FIG. 4 , in accordance with another exemplary embodiment, the signal routing circuitry  124  in the receive path for the VSA  104  of the tester  100  includes null signal detection circuitry (e.g., in addition to the multiplexing circuitry) which detects the presence of null data packets in the return signals  201   a ,  201   b ,  201   c  from the DUTs  200   a ,  200   b ,  200   c . When a null data packet is detected, one or more control signals  125  to the signal characteristic control circuitry  122  in the transmit path (discussed in more detail below) cause such circuitry  122  to alter one or more signal characteristics of the replicated VSG signals  123   a ,  123   b ,  123   c . For example, as shown for time interval  211 , two of the DUTs  200   a ,  200   b  have become ready for testing  203   a ,  203   b  and respond by transmitting null data packets as part of their return signals  201   a ,  201   b . These null data packets are detected by the null detection circuitry within the return signal routing circuitry  124  and the one or more control signals  125  cause the signal characteristic control circuitry  122  to corrupt the corresponding replicated VSG control signals  123   a ,  123   b , e.g., by reducing signal power during the data packet interval. 
     Meanwhile, the third DUT  200   c , now ready for testing  203   c , initially receives a null data packet signal from one of the other DUTs  203   a ,  203   b  that had been transmitted to indicate its readiness for testing. However, since the other DUTS  203   a ,  203   b  are no longer receiving valid, e.g., non-corrupted, data packet signals, they no longer transmit null data packets in return. As a result, the third DUT  200   c  now begins receiving valid test data packets  123   c  and responds accordingly with null data packets  201   c . Following this time interval  211 , the tester can then perform a receive test  213   r  in which predefined test data packets  123   a ,  123   b ,  123   c  can be transmitted for reception by the DUTs  200 , in response to which the DUTs  200  transmit null data packet signals  201 ,  201   b ,  201   c.    
     Referring to  FIG. 5 , in accordance with another exemplary embodiment, following the time interval  211  in which synchronization occurs, the tester  100  can perform a transmit test  213   t  in which replicated test data packets  123   a ,  123   b ,  123   c  can be transmitted, duplicated within the DUTs  200   a ,  200   b ,  200   c  and returned as their responsive signals  201   a ,  201   b ,  201   c , i.e., as loop-back data packet signals. 
     Referring to  FIG. 6 , in accordance with an exemplary embodiment, corruption of the replicated data packet signal  113  can be achieved by switching open the signal path using a switch  122   a  in accordance with a control signal  125  to significantly reduce the signal power of the replicated data packet signal  123 . 
     Referring to  FIG. 7 , in accordance with another exemplary embodiment, corruption of the data packet signal  113  can be achieved using a programmable signal attenuator  122   b . In accordance with the control signal  125 , signal attenuation can be increased such that the signal power of the replicated data packet signal  123  is reduced below a threshold value necessary for the signal to be deemed to be in conformance with the applicable signal standard. 
     Referring to  FIG. 8 , in accordance with another exemplary embodiment, instead of switching  122   a  or attenuation  122   b  circuitry, signal mixing circuitry  122   c  can be used. Corruption of the data packet signal  113  is achieved by altering the frequency of the replicated data packet signal  123  by mixing it with another radio frequency (RF) signal  131  from a local RF signal source  130  controlled by a control signal  125 . 
     Hence, it can be seen that signal corruption can be achieved by altering virtually any data packet signal characteristic, including signal power and signal frequency. 
     Referring to  FIG. 9 , in accordance with exemplary embodiments of the presently claimed invention, the wired signal paths for testing the DUTs  200  are typically in the form single wired connection for each DUT  200   a ,  200   b ,  200   c , as noted above. For example, for the first DUT  200   a , the test data packet signal  123   a   2  and return null data packet signal  201   a   1  are conveyed via a shared, or common, wired signal path  202   a . (Similarly, the test data packet signals  123   b   2 ,  123   c   2  to and responsive null data packet signals  201   b   1 ,  201   c   1  from the remaining DUTs  200   b ,  200   c  are conveyed via respective shared wire signal paths  202   b ,  202   c .) Each of the replicated VSG signals  123   a   1 ,  123   b   1 ,  123   c   1  from the data corruption circuitry  122  is conveyed via a respective wired signal path  142   a ,  142   b ,  142   c  to additional signal routing circuitry  140  (discussed in more detail below) to be conveyed over the wired DUT signal paths  202   a ,  202   b ,  202   c  as the respective replicated VGA signals  123   a   2 ,  123   b   2 ,  123   c   2 . The responsive null data packet signals  201   a   1 ,  201   b   1 ,  201   c   1  are conveyed in return via the wired DUT signal paths  202   a ,  202   b ,  202   c  to the routing circuitry  140  for conveyance via a respective output signal path  144   a ,  144   b ,  144   c  to the null detection and multiplexing circuitry  124 . 
     The additional signal routing circuitry  140  can be implemented in a variety of forms, in accordance with techniques well known in the art. For example, such routing circuitry  140  can be implemented as a 1:2 signal divider, or splitter, in which case the responsive null data packet signals  201   a   1 ,  201   b   1 ,  201   c   1  are divided and provided via the corresponding output signal path  144   a ,  144   b ,  144   c  as lower powered versions  201   a   2 ,  201   b   2 ,  201   c   2  of the original null data packet signals. Alternatively, such routing circuitry  140  can be implemented as a signal coupler providing a coupled version of the responsive null data packet signals  201   a   1 ,  201   b   1 ,  201   c   1  at the corresponding output signal port  144   a ,  144   b ,  144   c . Further alternatively, such routing circuitry  140  can be implemented as a signal switch controlled in accordance with a control signal (not shown) from the tester  100  or an external controller (not shown) such that, during transmission of the replicated VSG test signals  123   a   1 ,  123   b   1 ,  123   c   1 , corresponding signal paths  142   a ,  142   b ,  142   c  and  202   a ,  202   b ,  202   c  are connected. Similarly, during the time intervals in which the DUTs  200  are expected to respond, corresponding signal paths  202   a ,  202   b ,  202   c  and  144   a ,  144   b ,  144   c  are connected. 
     Based upon the discussion above, it can be seen that when simultaneously testing TDD devices, there is a possibility that one or more TDD devices will start at such time relative to the other TDD devices as to improperly synchronize to another TDD device response data packet rather than a tester test data packet. Typically, multiple DUTs will not become synchronized at the same time once a test process begins. Therefore, when the replicated test data packets are transmitted, the DUTs ready for testing will respond with null data packet signals, while those that are not yet ready for testing will not respond until they become ready. Transmitting test data packets before a DUT is ready may be done during bit error ratio (BER) testing where one need only test a minimum number of bits, in which case, sending more data packets to some DUTs than others is not critical so long as the DUT receiving the smallest number of bits receives the minimum number of bits required for test purposes. However, it is possible that a DUT becomes ready after the tester has sent its set of data packet signals, in which case, instead of receiving a tester data packet, the now-ready DUT receives leaked null data packet signal sent by another DUT. Meanwhile, the tester will have no way of knowing that this has occurred. Hence, as the tester continues to send its predefined test data packets to the multiple DUTs, the properly synchronized DUTs will receive those test data packets, while those that have not been properly synchronized will not. 
     With reference to  FIGS. 2 and 3 , in accordance with these exemplary embodiments, the tester sends null data packets at the beginning of the test sequence. The DUTs will not respond to those null data packets. The tester continues to send null data packets until the synchronization time interval has elapsed. This interval is chosen such that properly operating DUTs will be ready before it elapses. During that time interval, since the tester is sending null data packets, the DUTs are sending no responses. Therefore, no leaked response data packets can cause another DUT to erroneously synchronize to them. 
     With reference to  FIGS. 4 and 5 , in accordance with these other exemplary embodiments, a shorter test time can be achieved because the synchronization time period is dynamic rather than static, or fixed. As discussed above, as the tester transmits replicated test data packets, the DUTs that become ready for testing respond by transmitting null data packet signals. These responsive null data packet signals are detected and the corresponding DUTs are identified, following which, subsequent transmissions of the corresponding replicated test data packet signals will be altered, e.g., corrupted, so as to not be in conformance with the applicable signal standard. The DUTs receiving such corrupted signals will no longer send responsive null data packet signals thereby preventing an erroneous synchronization of a DUT not yet ready for testing to a responsive null data packet signal instead of a replicated VSG signal. 
     Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and the spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.