Abstract:
A heavily-doped semiconductor region and a channel stopper region, which are disposed under a memory cell in a memory cell region, are simultaneously formed after formation of a field insulator film, thereby preventing the channel stopper region from oozing out into the channel region, and thus obtaining a semiconductor memory device which is resistant to α-rays and therefore free from soft errors caused by α-rays. Also disclosed is a method of producing said semiconductor memory device.

Description:
This application is a continuation application of application Ser. No. 07/063,110, filed Jun 17, 1987, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device and, more particularly, to element isolation and α-ray soft error prevention techniques for dynamic random-access memories (hereinafter referred to as &#34;DRAM&#39;s&#34;). 
     Isolation of semiconductor elements from each other is generally effected by a combination of a field insulator film defined by a silicon oxide film formed by oxidation of the surface of a semiconductor substrate and a channel stopper region. An impurity for forming a channel stopper region is introduced by ion implantation before formation of a field insulator film, and the introduced impurity is diffused by making use of heat which is applied to the semiconductor substrate when thermal oxidation is effected in order to form a field insulator film. A technique similar to that described above is used in isolation of elements in a DRAM. It should be noted that techniques related to element isolation are described, for example, in &#34;VLSI Device Handbook&#34;, Science Forum, Nov. 28, 1983, page 63. 
     Soft errors in DRAM&#39;s are mainly caused by generation of electron-hole pairs by α-rays. As known techniques used to prevent generation of soft errors by α-rays, there is one example in which a heavily-doped semiconductor region which serves as a potential barrier against the electron-hole pairs is formed under a region on a semiconductor substrate in which memory cells are to be formed. An impurity for forming the heavily-doped semiconductor region is introduced under an active region in a memory cell region, after the formation of a field insulator film defined by a silicon oxide film formed by oxidation of the surface of the semiconductor substrate, by ion implantation using the field insulator film as a mask. Such a DRAM soft error preventing technique is described, for example, in the specification of Japanese Patent Laid-Open No. 94451/1984. 
     A channel stopper region is formed prior to the formation of a field insulator film defined by a silicon oxide film formed by oxidation of the surface of the semiconductor substrate, and after the formation of the field insulator film, a heavily-doped semiconductor region (hereinafter also referred to as an &#34;impurity-introduced region&#34; for convenience) on the semiconductor substrate and under a region in which a Metal Insulator Semiconductor Field Effect Transistor (MISFET: hereinafter referred to as a &#34;MISFET&#34;) is to be formed for the purpose of lowering the substrate resistance in order to prevent latchup of a Complementary Metal Oxide Semiconductor (CMOS: hereinafter referred to as &#34;CMOS&#34;). An impurity for forming the heavily-doped semiconductor region is introduced under the region in which a MISFET is to be formed by ion implantation carried out through the field insulator film. The channel stopper region formed as described above and the heavily-doped semiconductor region are connected together under the field insulator film and formed in such a manner as to surround the region in which a MISFET is to be formed. Such a technique is described, for example, in the specification of Japanese Patent Laid-Open No. 10268/1986. 
     SUMMARY OF THE INVENTION 
     The present inventors examined the above-described techniques and found the following problems. 
     The step of introducing an impurity for forming a channel stopper region is carried out before the formation of a field insulator film, while the step of introducing an impurity for forming a heavily-doped semiconductor region for the purpose of preventing generation of soft errors is carried out after the formation of the field insulator film. In other words, these steps are executed independently of each other, which results in an increase in the number of steps. If a channel stopper region is formed before the formation of the field insulator film, the channel stopper region oozes out into the channel region of the MISFET by the heat applied to the substrate at the time of formation of the field insulator film, causing said channel region to be narrowed, and resulting in an increase in the threshold value of the MISFET. 
     The way in which the above-described channel stopper region oozes out into the channel region of the MISFET will be explained below with reference to FIGS. 15 and 16 FIG. 15 is a plan view of a part of a region in which a MISFET is formed, and FIG. 16 is a sectional view taken along the line A&#39;--A&#39; of FIG. 15. It should be noted that FIG. 15 illustrates no insulator films other than a field insulator film (the pattern configuration of which is shown alone) in order to facilitate understanding of the arrangement of the MISFET. As shown in FIG. 15, a MISFET consists of a gate electrode 18&#39; (WL) and source and drain diffused regions 19&#39; which are formed at both ends, respectively, of the gate electrode 18: The MISFET is surrounded with an field insulator film pattern 9&#39;, and a channel stopper 10A&#39; is formed under the field insulator film pattern 9&#39;. The channel stopper 10A&#39; is oozed out from the vicinities of regions Z of the channel stopper region 10A&#39; into the channel region Y of the MISFET as shown in FIG. 16 by the heat applied to the substrate at the time of formation of the field insulator film. For this reason, the channel region is narrowed, and the threshold value of the MISFET is increased. 
     It is an object of the present invention to provide a semiconductor memory device having improved reliability, for example, a semiconductor memory device which is resistant to α-rays, together with a method of producing such a semiconductor memory device. 
     It is another object of the present invention to provide a semiconductor memory device having improved electrical characteristics, for example, a semiconductor memory device in which a MISFET has a lowered threshold value, together with a method of producing such a semiconductor memory device. 
     The following is a brief summary of a representative one of the inventions disclosed in this application. 
     Namely, after formation of a field insulator film, an impurity for forming a channel stopper region is introduced through the field insulator film and, at the same time, an impurity for forming a heavily-doped semiconductor region serving as a potential barrier under a memory cell is introduced. 
     According to the above-described means, it is possible to prevent the channel stopper region from oozing out into the channel region of the MISFET and, at the same time, to form a heavily-doped semiconductor region serving as a potential barrier under the active region in the memory cell region, so that it is possible to provide a semiconductor memory device having improved electrical characteristics and enhanced reliability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1 to 10 are sectional views showing a memory cell region and a peripheral circuit region of a semiconductor memory device in accordance with the embodiment I in successive steps of the process for producing the same; 
     FIG. 11 is a graph showing concentration profiles of semiconductor regions; 
     FIG. 12 is a plan view of a memory cell in a semiconductor memory device in accordance with the embodiment II; 
     FIG. 13 is a sectional view taken along the line A--A of FIG. 12; 
     FIG. 14 is a sectional view taken along the line B--B Of FIG. 12; 
     FIG. 15 is a plan view of a part of a MISFET forming region in which a channel stopper is formed using a conventional technique; and 
     FIG. 16 is a sectional view taken along the line A&#39;--A&#39; of FIG. 15. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     One embodiment of the present invention will be described hereinunder in accordance with the process for producing a dynamic RAM. 
     Referring to FIGS. 1 to 10, which are views employed to describe the process for producing a dynamic RAM, the region A is a sectional view of a memory cell region, and the region B is a sectional view of a peripheral circuit region for forming a peripheral circuit such as a decoder, an address buffer or a sense amplifier. 
     As shown in FIG. 1, a silicon oxide film 2 which serves as a ground film is formed by oxidizing the whole surface of a semiconductor substrate 1 formed from p -  -type single crystal silicon in order to form an n -  -type well region 3 in the region B of the semiconductor substrate 1. Then, a mask 4 which is defined by a resist film is formed. The mask 4 has an opening above a region in the region B in which the n -  -type well region 3 is to be formed. Then, an n-type impurity, for example, phosphorus (P), is introduced by ion implantation. Thereafter, the mask 4 is removed, and the semiconductor substrate 1 is annealed to diffuse the impurity and to thereby form the n -  -type well region 3. 
     Referring next to FIG. 2, an oxidation resistance mask 5 which is defined by a silicon nitride film for thermal oxidation carried out to form a field insulator film 9 (see FIG. 6) is formed on the semiconductor substrate 1 by, for example, Chemical Vapor Deposition (hereinafter referred to as &#34;CVD&#34;). Then, the oxidation resistance mask 5, which is located in a portion of the surface of the n -  -type well region 3 among regions in the region B in which the field insulator film 9 is to be formed, is removed by etching using a mask (not shown) defined by a resist film to form an opening 7. A portion of the surface of the n -  -type well region 3 is exposed in the opening 7. The mask (not shown) defined by a resist film employed to provide the opening 7 in the oxidation resistance mask 5 is removed after the formation of the opening 7. Then, the portion of the surface of the n -  -type well region 3 which is exposed from the oxidation resistance mask 5 is oxidized to form a silicon oxide film 6 having a thickness of about 500 Å. The film 6 serves as a mask used when ion implantation is carried out to form a channel stopper region 10 (see FIG. 6) in the region B, and the film 6 is to become a part of the field insulator film 9 afterward. 
     Next, as shown in FIG. 3, a portion of the mask 5 in the region B, which was not removed in the step shown in FIG. 2 but is left covering the region in which the field insulator film 9 is to be formed, is removed by etching using a mask (not shown) defined by a resist film to enlarge the opening 7. 
     Then, as shown in FIG. 4, a p-type impurity 8, for example, boron (B), for forming a channel stopper region 10 (see FIG. 6) in the region B is introduced by ion implantation using the mask 5 and the silicon oxide film 6 as a mask. The energy for implantation of the p-type impurity is, for example, about 60 KeV. At this time, the p-type impurity for forming a channel stopper is not introduced into the region A (memory cell region). 
     Thus, in accordance with this embodiment, the impurity 8 for forming the channel stopper region 10 is introduced into the peripheral circuit region (region B) before the formation of the field insulator region 9. 
     Referring next to FIG. 5, that portion of the oxidation resistance mask (silicon nitride film) 5 which is on a region in the region A in which the field insulator film 9 is to be formed, is removed by etching using a mask (not shown) defined by a resist film to form an opening 7 in the region A. The mask (not shown) defined by a resist film is removed after the etching. 
     Then, as shown in FIG. 6, in the regions A and B, the surface of the semiconductor substrate 1 and the surface of the n -  -type well region 3 which are exposed through the oxidation resistance mask 5 are subjected to thermal oxidation to form a field insulator film 9 defined by a silicon oxide film. The thickness of the field insulator film 9 is set at about 4500 Å. The thickness of the field insulator film 9 formed by thermal oxidation of the surface of the n -  -type well region 3 is slightly larger than 4500 Å, although this is not discernibly illustrated in FIG. 6. During this thermal oxidation, the p-type impurity, e.g., boron (B), which has been introduced in the region B is diffused to form a p-type channel stopper region 10 in the region B. In this step, no channel stopper region 10 is formed in the region A. After the formation of the field insulator film 9, the oxidation resistance mask 5 defined by a silicon nitride film is removed. 
     Referring next to FIG. 7, a mask 11 defined by a resist film is formed in the region B in order to carry out ion implantation for forming a channel stopper region 10 in the region A. All the memory cell array region, that is, the region A, is exposed through the mask 11. Then, a p-type impurity, for example, boron (B), is introduced into the region A by ion implantation carried out through the field insulator film 9, and annealed to simultaneously form a channel stopper region 10A and a p-type semiconductor region 10B. The implantation energy is set at about 200 KeV, and the dose is set at about 5×10 12  atoms/cm 2 . The above-described annealing is effected for the purpose of diffusing and activating the introduced p-type impurity. The mask 11 defined by a resist film is removed after the ion implantation. 
     The impurity for forming the channel stopper region 10A and the p-type semiconductor region 10B is introduced into the surface region of the semiconductor substrate 1 under the field insulator film 9 in the region A through the same film 9. Further, the impurity, which is introduced into the principal surface portion of the semiconductor substrate 1 which is exposed through the field insulator film 9, is implanted into a region in the semiconductor substrate 1 which is deeper than the impurity introduced under the field insulator film 9 so that the peak of the concentration distribution is about 5000 Å under the surface of the semiconductor substrate 1. 
     Thus, in the memory cell region, that is, the region A, the channel stopper region 10A is formed after the formation of the field insulator film 9. In this way, the heat applied at the time of thermal oxidation carried out to form the field insulator film 9 is prevented from being applied to the channel stopper region 10A in the region A, thereby suppressing diffusion of the channel stopper region 10A. The p-type semiconductor region 10B, which is formed simultaneously with the channel stopper region 10A, serves as a potential barrier against electron-hole pairs generated by α-rays entering the semiconductor substrate 1. It should be noted that the annealing, which is carried out in order to diffuse and activate the p-type impurity introduced for forming the channel region 10A and the p-type semiconductor region 10B in the region A, may be effected by, for example, annealing of an impurity for forming source and drain regions of a MISFET which is to be formed afterward. Further, in order to increase the storage capacity, the field insulator film 9 in the memory cell region may slightly be etched before the introduction of the p-type impurity so that the field insulator film 9 is further thinner than the field insulator film 9 in a high-voltage circuit portion of a peripheral circuit having a channel stopper region 10 (see FIG. 6). Since the above-described etching enables a reduction in the width of the field insulator film 9 in the memory cell region, the element forming region can be enlarged, so that it is also possible to enlarge the area of the storage capacity region. 
     Then, as shown in FIG. 8, the silicon oxide film 2, which serves as a ground film and has been contaminated by ion implantation and other treatments, is removed by etching, and the surface of the semiconductor substrate 1 exposed through the field insulator film 9 is oxidized to form a dielectric film 12 defined by a silicon nitride film. The dielectric film 12 is provided in order to constitute a capacitance element of a memory cell and formed so as to have a thickness of about 70 Å. In this step, the dielectric film 12 is formed not only in the region A (memory cell region) but also in the region B (peripheral circuit region). Then, a mask 13 which is defined by a resist film is formed over a part of the region A and over the region B for the purpose of carrying out ion implantation for forming an n +  -type semiconductor region 14 in a predetermined portion in the region A, the semiconductor region 14 serving as one of the electrodes of the capacitance element. The mask 13 covers the selecting MISFET region in the region A and covers the whole of the region B. An n-type impurity, for example, arsenic (As), is introduced by ion implantation into the surface of the semiconductor substrate 1 in the region A exposed through the mask 13, and annealed in a nitrogen (N 2 ) atmosphere to form an n +  -type semiconductor region 14. The energy for implantation of the n-type impurity (As) is set at about 80 KeV, and the dose is set at about 2×10 14  atoms/cm 2 . The mask 13 defined by a resist film is removed after the ion implantation. 
     Referring next to FIG. 9, a polycrystalline silicon film is formed all over the regions A and B by, for example, CVD, for the purpose of forming a conductive plate 15 serving as the other electrode of the capacitance element. The polycrystalline silicon film is patterned by etching using a mask (not shown) defined by a resist film to form a conductive plate 15. The mask employed for the etching is removed after the formation of the plate 15. Then, the exposed surface of the conductive plate 15 defined by the polycrystalline silicon film is oxidized to form an insulator film 16 defined by a silicon oxide film. That portion of the dielectric film 12 which is exposed through the field insulator film 9 and the insulator film 16 is removed to expose the surface of the semiconductor substrate 1, and the exposed surface is oxidized to form a gate insulator film 17 defined by a silicon oxide film. The thickness of the gate insulator film 17 is set at about 200 Å. Then, a polycrystalline silicon film is formed all over the semiconductor substrate 1 by, for example, CVD, and patterned by etching using a mask (not shown) defined by a resist film to form gate electrodes 18 and word lines WL in the region A and gate electrodes 18 in the region B. It should be noted that the gate electrodes 18 and the word lines WL may be formed from a film of a refractory metal such as Mo, W, Ta or Ti, or a film of a silicide of such a refractory metal, or a multilayer film formed by laminating the above-described refractory metal film or silicide film on a polycrystalline silicon film. 
     Then, as shown in FIG. 10, in the regions A and B are formed an n-type semiconductor region 19 as a part of each of the source and drain regions of each N-channel MISFET, side wall spacers 20 formed from a silicon oxide film, an n +  -type semiconductor region 21 as a part of each of the source and drain regions of each N-channel MISFET, p +  -type semiconductor regions 22 as the source and drain regions of each P-channel MISFET, an insulator film 23 defined by a phosphosilicate glass (PSG) film formed by, for example, CVD, contact holes 24, and data lines DL as well as conductor layers 25 formed from an aluminum film by, for example, sputtering. A method of producing a peripheral circuit is described in the specification of U.S. patent application Ser. No. 731,975 filed on May 8, 1985. NMOS&#39;s in the memory cell region are formed in a process similar to that for producing NMOS&#39;s in the peripheral circuit. 
     As has been described above, in the region A a p-type impurity, for example, boron (B), for forming the channel stopper region 10A is introduced after the formation of the field insulator film 9, thereby reducing the degree to which the channel stopper region 10A oozes out into the channel region. Thus, the threshold value of the selecting MISFET of each memory cell can be lowered, and therefore the speed of read and write operations of the device can be increased. 
     Further, in the region A the p-type semiconductor region 10B, which is formed under the n +  -type semiconductor region 14 serving as one electrode of the capacitance element, serves as a barrier against minority carriers in the semiconductor substrate 1. Further, impurity ions which are implanted to form a p-type semiconductor region are distributed around a position which is 0.5 μm deep from the surface of the semiconductor substrate as shown in FIG. 11, thus increasing the PN junction capacitance between the p-type semiconductor region and the n +  -type semiconductor region 14. 
     The impurity concentration in the p-type channel stopper region 10A in the surface of the semiconductor substrate 1 at the bird&#39;s beak portion of the field insulator film 9 is lower than that in the p-type channel stopper region 10A in the surface of the substrate 1 at portions of the field insulator film 9 other than the bird&#39;s beak portion. This is because, the peak of the p-type impurity concentration at the bird&#39;s beak portion is located deeper than the surface of the semiconductor substrate 1. Accordingly, the dielectric strength at the junction between the n +  -type semiconductor region 14 and the p-type channel stopper region 10A is higher than that in the case where the channel stopper region is formed by ion implantation of an impurity of the same concentration carried out before the formation of the field insulator film. 
     Further, the p-type semiconductor region 10B is provided under the n-type semiconductor regions 19 and the n +  -type semiconductor regions 21 which define the source and drain regions of the selecting MISFET. The p-type semiconductor region 10B serves as a barrier against minority carriers which would otherwise enter the n-type semiconductor regions 19 or the n +  -type semiconductor regions 21. 
     On the other hand, in the region B no p-type semiconductor region 10B is formed under the n-type semiconductor regions 19 and the n +  -type semiconductor regions 21 which define the source and drain regions of the N-channel MISFET. Thus, it is possible to suppress the increase in the junction capacitance at the source and drain regions of the N-channel MISFET in the region B, and therefore it is possible to increase the operating speed of the device. 
     It should be noted that the ion implantation for forming the p-type channel stopper region 10A and the p-type semiconductor region 10B may be carried out in two steps. For example, the first ion implantation may be carried out at about 200 KeV, and the second ion implantation may be effected at about 300 KeV. The alternative ion implantation method enables prevention of the concentration profile from becoming steep. 
     Further, the process may be modified in such a manner that, after the step shown in FIG. 7, the mask 11 defined by a resist film is removed, and a new mask, which is defined by a resist film having a pattern whereby the capacitance element region alone is exposed, is formed on the semiconductor substrate 1 to introduce a p-type impurity into the capacitance element region again. This alternative procedure enables adjustment of the impurity concentration distribution in the p-type semiconductor region 10B under the n +  -type semiconductor region 14 in the capacitance element region. 
     Also, the process may be modified in such a manner that, after the step shown in FIG. 7, the mask 11 is removed, and a new mask, which is defined by a resist film having a pattern whereby the field insulator film 9 in the region A is exposed alone, is formed on the semiconductor substrate 1 to introduce a p-type impurity under the field insulator film 9 in the region A again. This alternative procedure enables adjustment of the impurity concentration in the channel stopper region 10A in the region A. 
     FIG. 12 is a plan view of a memory cell in a dynamic RAM in accordance with the embodiment II, while FIG. 13 is a sectional view taken along the line A--A of FIG. 12, and FIG. 14 is a sectional view taken along the line B--B of FIG. 12. It should be noted that FIG. 12 illustrates no insulator films other than the field insulator film 9 in order to facilitate understanding of the arrangement of the memory cell. 
     In this embodiment, a field insulator film 9A which is located at one side of a selecting MISFET of a memory cell, that is, under a word line WL, is formed so as to be relatively thick, i.e., about 4500 Å, while a field insulator film 9B which is located between adjacent capacitance elements is formed so as to be relatively thin, i.e., about 2500 to about 3000 Å. 
     A p-type channel stopper region 10 in this embodiment is formed by a method similar to that in the embodiment I,,wherein an impurity is introduced after the formation of the field insulator film 9. 
     If it is so set that the peak of concentration profile of the p-type channel stopper region 10A is located at the surface of the semiconductor substrate 1 under the thick field insulator film 9A, the surface impurity concentration of the p-type channel stopper region 10A under the thin field insulator film 9B is lowered but can be set at such a level that it is possible to adequately isolate adjacent cells from each other. This structure can be achieved in a single ion implantation without using a mask defined by a resist film. 
     Since the concentration in the p-type channel stopper region 10A under the thin field insulator film 9B is lowered, it is possible to reduce the width of the isolating region and ensure an increased storage capacity while maintaining the PN junction dielectric strength at a relatively high level. 
     Although the present invention has practically been described above on the basis of the embodiments, it should be noted here that the present invention is not necessarily limited to the described embodiments and various changes and modifications may, of course, be imparted thereto without departing from the gist and spirit of the invention. 
     For example, the present invention may be applied to static RAM&#39;s (S-RAM&#39;s) and may also be applied to mask-programmed ROM&#39;s, EPROM&#39;s (Electrically Programmable ROM&#39;s) and EEPROM&#39;s (Electrically Erasable and Programmable ROM&#39;s). 
     In addition, the gate electrodes 18 and the word lines WL may be formed from a film of a refractory metal such as Mo, W, Ta or Ti, or a film of a silicide of such a refractory metal, or a multilayer film formed by laminating said refractory metal film or silicide film on a polycrystalline silicon film. Thus, a p-type impurity for forming the p-type channel stopper region 10A is prevented from readily entering a region under the channel region of a selecting MISFET, so that it is possible to lower the threshold value of the MISFET.