Abstract:
A stable, low power consumption signal detecting circuit may include: a delay circuit, which receives a base clock signal and generates multiple versions thereof having time delay relationships thereto, respectively; dual amplifiers, which detect valid ones of input signals by comparing the input signals with reference voltage signals in response to the multiple versions of the base clock signal, respectively; a combining unit, which generates a combination signal in response to output signals of the dual amplifiers; and a sampling circuit, which samples the combination signal according to the base clock signal and generates an output signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This U.S. nonprovisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2003-30903 filed on May 15, 2003, the entire contents of which are hereby incorporated by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    In general, in a high speed communication for data transmission in the GHz range, a differential serial interface has been used to avoid crosstalk and noise coupling generated in a parallel interface. The differential serial interface is mainly constructed with a comparator circuit.  
           [0003]    Typically, the comparator circuit receives two input signals, compares voltages thereof, and generates an output signal in response to a comparison result. A differential voltage comparator is a type of comparator for comparing two differential input signal voltages and outputting a differential output.  
           [0004]    For example, the differential comparator may be used to detect squelch or un-squelch of a receiving unit for receiving input signals. The receiving unit is connected to a communication line or a bus, and determines whether a real signal exists on the communication line. Referring to the Serial ATA Specification, a signal speed and a signal threshold range should be 1.5 Gbps and 50˜200 mV, respectively. In signal detection according to the Serial ATA specification, since the signal speed is high and the signal voltage is small, it is difficult to implement the comparator circuit by conventional techniques. Although this can be achieved, the implementation results in high power consumption, which is worsened when the signal speed is increased to 2, 3, and 10 Gbps.  
         SUMMARY OF THE INVENTION  
         [0005]    At least one embodiment of the present invention provides a low power consumption signal detecting circuit capable of stable detection even a high data rate signal; and at least one embodiment provides a corresponding method of detecting a signal.  
           [0006]    According to at least one embodiment of the present invention, there is provided a stable, low power consumption signal detecting circuit. Such a signal detecting circuit may include: a delay circuit, which receives a base clock signal and generates multiple versions thereof having time delay relationships thereto, respectively; dual amplifiers, which detect valid ones of input signals by comparing the input signals with reference voltage signals in response to the multiple versions of the base clock signal, respectively; a combining unit, which generates a combination signal in response to output signals of the dual amplifiers; and a sampling circuit, which samples the combination signal according to the base clock signal and generates an output signal.  
           [0007]    Additional features and advantages of the invention will be more fully apparent from the following detailed description of example embodiments, the accompanying drawings and the associated claims. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]    The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:  
         [0009]    [0009]FIG. 1 is a schematic view illustrating a signal detecting circuit according to at least one embodiment of the present invention;  
         [0010]    [0010]FIG. 2 is a schematic view illustrating in more detail a delay circuit of FIG. 1, according to at least one embodiment of the present invention;  
         [0011]    [0011]FIG. 3 is a schematic view illustrating in more detail a dual amplifier of FIG. 1, according to at least one embodiment of the present invention;  
         [0012]    [0012]FIG. 4 is a schematic view illustrating in more detail a clocked amplifier of FIG. 3, according to at least one embodiment of the present invention;  
         [0013]    [0013]FIGS. 5A and 5B are wave forms illustrating aspects of input signal detecting/checking operations according to at least one embodiment of the present invention;  
         [0014]    [0014]FIG. 6 is a schematic view illustrating in more detail a sampling circuit of FIG. 1, according to at least one embodiment of the present invention; and  
         [0015]    [0015]FIGS. 7 and 8 are views illustrating simulation results obtained by using an example signal detecting circuit implementation according to at least one embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0016]    The present invention and operational advantages thereof can be fully understood by referring to the accompanying drawings and explanations of example embodiments thereof. In the drawings, the same reference numerals indicate the same elements.  
         [0017]    [0017]FIG. 1 is a schematic view illustrating a signal detecting circuit according to at least one embodiment of the present invention. Referring to FIG. 1, a signal detecting circuit  100  responds to a clock signal CK and detects whether input signals AP and AN signals are real signals (as contrasted to noise and/or crosstalk) by respectively comparing the input signals AP and AN with reference signals BP and BN.  
         [0018]    The signal detecting circuit  100  comprises: dual amplifiers  102 ,  104 ,  106 ,  108 ,  110 , and  112 , to which the input signals AP and AN and the reference signals BP and BN are input; a delay circuit  114 , to which the clock signal CK is input; buffers  116 ,  120 , and  124 ; inverters  118 ,  122 , and  126 , to which output signals d 1 , d 2 , and d 3  of the delay circuit  114  are respectively input; a logical NOR gate  128 , to which output signals Y 1 , Y 2 , and Y 3  of the dual amplifiers  102 ,  106 , and  110  (used as clock buffers) are respectively input; an inverter  130 , to which the clock signal CK is input; a sampling circuit  132  to which an output YNR 3  of NOR gate  128  and an output CKDM inverter  130  are input; a logical NOR gate  134 , to which a power down signal PD and an output signal YDM of the sampling circuit  132  are input; an inverter  136 ; and a buffer  138 , to which an output signal of the NOR gate  134  is input.  
         [0019]    In FIG. 1, no outputs of dual amplifiers  104 ,  108  and  112  are depicted, for simplicity of illustration. The outputs of dual amplifiers  104 ,  108  and  112  are provided to similar componentry and in a similar manner as are the outputs of dual amplifiers  102 ,  106  and  110 .  
         [0020]    [0020]FIG. 2 illustrates the delay circuit  114  in more detail, according to at least one embodiment of the present invention. The delay circuit  114  comprises buffers  201  to  210 , which are serially connected. The output signals d 1  of the first buffer  201  to which the clock signal CK is input, the output signal d 2  of the fifth buffer  205 , and the output signal d 3  of the ninth buffer  209  are generated at separate intervals. The output signals d 1 , d 2 , and d 3  of the delay circuit  114  are applied to pairs of dual amplifiers  102  and  104 ,  106  and  108 , and  110  and  112  through buffers  116 ,  120 , and  124  (respectively emerging as clock signals CK 1 , CK 2  and CK 3 ) and inverters  118 ,  122 , and  126  (respectively emerging as clock signals CK 1 B, CK 2 B and CK 3 B), respectively.  
         [0021]    The first dual amplifier  102  out of the dual amplifier  102 ,  104 ,  106 ,  108 ,  110 , and  112  is representatively illustrated in more detail in FIG. 3, according to at least one embodiment of the present invention. Construction of the other dual amplifiers  104 - 112  can be the same or substantially the same. The first dual amplifier  102  includes: clocked amplifiers  302  and  306 , to which the clock signal CK 1 , the input signals AP and AN, and the reference voltage signals BP and BN are input; an S-R latch  304 , to which is provided output signals of the first clocked amplifiers  302 , an S-R latch  308 , to which is provided output signals of the second clocked amplifiers  306 ; and a logical NAND gate  310 , to which output signals of the S-R latches  304  and  308  are input.  
         [0022]    [0022]FIG. 4 illustrates the clocked amplifier  302  of FIG. 3 in detail, according to at least one embodiment of the present invention. The clocked amplifier  302  includes: a PMOS transistor  401 , whose source is connected to a power source voltage VDD and whose gate is connected to the inverted clock signal CK 1 ; NMOS transistors  415  and  421 , each of whose source is connected to a ground voltage VSS and each of whose gate is connected to the inverted clock signal CK 1 ; PMOS transistors  405  and  407 , each of whose sources are connected to the drain of the PMOS transistor  401  and whose gates are connected to the input signals AP and AN, respectively; PMOS transistors  403  and  409 , each of whose sources are connected to the drain of the PMOS transistor  401  and whose gates are connected to the reference voltage signals BP and BN, respectively; a PMOS transistor  411 , whose source is connected to the drains of the PMOS transistors  403  and  405 ; a PMOS transistor  413 , whose source is connected to the drains of the PMOS transistors  407  and  409 ; and NMOS transistors  417  and  419 , whose sources are connected to the ground voltage VSS and whose drains are connected to the drains of the PMOS transistors  411  and  413 , respectively. The PMOS and NMOS transistors  411  and  417  together represent an inverter  423 , and the PMOS and NMOS transistors  413  and  419  together represent an inverter  425 . The inverters  423  and  425  are cross-coupled to each other. The outputs YP 1  and YN 1  of inverters  423  and  425  are provided to inverters  427  and  429 , each of which has a similar construction to inverters  423  and  425 . The outputs of the inverters  427  and  429  are output as the output signals YPB and YNB.  
         [0023]    The operation of the clocked amplifier  302  of FIG. 4 is as follows.  
         [0024]    The clocked amplifier  302  is enabled in response to the logic low level of the inverted clock signal CK 1 . When the voltage levels of the first reference voltage signal BP and the first input signal AP are higher than those of the second reference voltage signal BN and the second input signal AN, than the first and second output signals YPB and YNB are driven to the logic low level and the logic high level, respectively. When the voltage levels of the first reference voltage signal BP and the first input signal AP are lower than those of the second reference voltage signal BN and the second input signal AN, then the first and second output signals YPB and YNB are driven to the logic high level and the logic low level, respectively.  
         [0025]    If, and only if, the difference between the first and second input signals AP and AN is larger than the difference between the first and second reference voltage signals BP and BN, then the clocked amplifier  302  decides that the input signals are valid real signals. If the difference between the first and second input signals AP and AN is smaller than the difference between the first and second reference voltage signals BP and BN, then the clocked amplifier  302  decides that the input signals are not real signals (and instead are noise and/or crosstalk).  
         [0026]    Operation of the dual amplifier  102  of FIG. 3 depends on the operation of the clocked amplifier  302 , as follows.  
         [0027]    Firstly, if the difference between the first and second input signals AP and AN is larger than the difference between the first and second reference voltages BP and BN, then the first and second output signals YPB and YNB of the first clocked amplifier  302  are driven to the logic low level and the logic high level, respectively, and the output Q of the S-R latch  304  is driven to the logic high level. Also, in that circumstance, the first and second output signals YPB and YNB of the second clocked amplifier  306  are driven to the logic high level and the logic low level, respectively, and the output Q of the S-R latch  308  is driven to the logic low level. Accordingly, the output signal of the NAND gate  310  is driven to the logic high level.  
         [0028]    On the other hand, if the voltage levels of the first reference voltage signal BP and the first input signal AP are lower than the voltage levels of the second reference voltage BN and the second input signal AN, then the first and second output signals YPB and YNB of the first clocked amplifier  302  are driven to the logic high level and the logic low level, respectively, and the output Q of the S-R latch  304  is driven to the logic low level. Also in that circumstance, the first and second output signals YPB and YNB of the second clocked amplifier  306  are driven to the logic low level and the logic high level, respectively, and the output Q of the S-R latch  308  is driven to the logic high level. Accordingly, the output signal of the NAND gate  310  is driven to the logic high level.  
         [0029]    Secondly, if the difference between the first and second input signals AP and AN is smaller than the difference between the first and second reference voltages BP and BN, then the first and second output signals YPB and YNB of the first clocked amplifier  302  are driven to the logic low level and the logic high level, respectively, and the output Q of the S-R latch  304  is driven to the logic high level. Also in that circumstance, the first and second output signals YPB and YNB of the second clocked amplifier  306  are driven to the logic low level and the logic high level, respectively, and the output Q of the S-R latch  308  is driven to the logic high level. Accordingly, the output signal of the NAND gate  310  is driven to the logic low level.  
         [0030]    In summary, the operation of the dual amplifier  102  of FIG. 3 is as follows. If the difference between the first and second input signals AP and AN is larger than the difference between the first and second reference signals BP and BN, then the dual amplifier  102  decides that the input signals AP and AN are valid real signals, and thus, the output signal of the NAND gate  310  is driven to the logic high level. If the difference between the first and second input signals AP and AN is smaller than the difference between the first and second reference signals BP and BN, then the dual amplifier  102  decides that the input signals AP and AN are not real signals, and thus, the output signal of the NAND gate  310  is driven to the logic low level.  
         [0031]    Referring to FIG. 1, the operation of the signal detecting circuit  100  is described based on the aforementioned operation of the dual amplifier  102 , as follows. The signal detecting circuit  100  decides the validity of the input signals AP and AN three times. A first detection is carried out by the first dual amplifier  102  in response to the first clock signal CK 1 . A second detection is carried out by the third dual amplifier  106  in response to the second clock signal CK 2 , which is delayed in time relative to the first clock signal CK 1 . A third detection is carried out by the fifth dual amplifier  110  in response to the third clock signal CK 3 , which is delayed in time relative to the second clock signal CK 2 . The signal detecting circuit  100  inputs the three detection results about the validity of the input signals AP and AN, that is, the output signals Y 1 , Y 2 , and Y 3  of the first, second, and third dual amplifiers  102 ,  106 , and  110  to the NOR gate  128 . If any of the output signals Y 1 , Y 2 , and Y 3  of the first, second, and third dual amplifiers  102 ,  106 , and  110  is the logic high level, then the output signal YNR 3  of the NOR gate  128  becomes the logic low level.  
         [0032]    An advantage achieved by making multiple, e.g., three detections on the input signals AP and AN is described with reference to FIGS. 5A-5B, according to at least one embodiment of the present invention. FIG. 5A depicts wave forms that illustrate the best case and worst case points in time at which to detect the input signals AP and AN. At the best case point in time, since there is sufficient voltage difference between the input signals AP and AN, the detection of the input signals is stable. On the other hand, at the worst case point in time, since there is little voltage difference between the input signals AP and AN, the detection of the input signals is unstable. In order to reduce the instability, according to at least one embodiment of the present invention, the input signal detection can be carried out via multiple, e.g., three detections.  
         [0033]    As depicted in FIG. 5B, making multiple (e.g., 3) detections times yields at least one detection (e.g., 2 for the assumption of a total of 3 detections) that does not occur at the worst case point in time. Selection of a sufficiently fast rate for the detections depends upon the frequency of AP and AN, e.g., according to known sampling theory.  
         [0034]    On the other hand, the second, fourth, and sixth dual amplifier  104 ,  108 , and  112  of the signal detecting circuit  100  respond to the first, second, and third inverted clock signals CK 1 B, CK 2 B, and CK 3 B, while the first, third, and fifth dual amplifier  102 ,  106 , and  110  of the signal detecting circuit  100  respond to the first, second, and third non-inverted clock signals CK 1 , CK 2 , and CK 3 . The second, fourth, and sixth dual amplifier  104 ,  108 , and  112  are provided in order to reduce a bouncing phenomena of the input signals AP and AN and the reference voltage signals BP and BN due to the operations of the first, third, and fifth dual amplifiers  102 ,  106 , and  110 .  
         [0035]    The sampling circuit  132  shown in FIG. 1 performs a predetermined number of sampling operations on the output signal YNR 3  of the NOR gate  128 . The sampling circuit  132  is used to delay the transition time of the output signals Y and YB of the signal detecting circuit  100  in order to prevent an error of detecting the case in which the voltage levels of input signals AP and AN are lower than the reference voltage signals BP and BN and then restored to the original level as a no-signal case.  
         [0036]    [0036]FIG. 6 illustrates the sampling circuit  132  in more detail, according to at least one embodiment of the present invention.  
         [0037]    Referring to FIG. 6, the sampling circuit  132  comprises: five cascade-connected D flip-flops  601 ,  603 ,  605 ,  607 , and  609 , which respond to the buffered clock signal CKDM and the output signal YNR 3  of the NOR gate  128  of FIG. 1; a logical NAND gate  611 ; a logical NOR gate  613 , to which the outputs of the D flip-flops  601 ,  603 ,  605 ,  607 , and  609  are input; and an S-R latch  615 , which responds to the outputs of the NAND gate  611  and the NOR gate  613 .  
         [0038]    The operation of the sampling circuit  132  of FIG. 6 is as follows.  
         [0039]    If the input signals AP and AN of FIG. 1 are normally detected to be valid and the output signal YNR 3  of the NOR gate  128  of FIG. 1 is at the logic low level during the five clock cycles of the clock signal CK, then the outputs of the NAND gate  611  and NOR gate  613  are driven to the logic high level and the logic low level, respectively. Accordingly, the output Y of the S-R latch  615  is driven to the logic low level.  
         [0040]    If the input signals AP and AN of FIG. 1 are real signals and abnormally reduced due to noise, etc., and thus, the output signal YNR 3  of the NOR gate  128  of FIG. 1 varies from the logic low level to the logic high level during the five clock cycles of the clock signal CKDM and the output signal YNR 3  is finally low, then the outputs of the NAND gate  611  and NOR gate  613  are driven to the logic high level and the logic low level, respectively. Accordingly, the output Y of the S-R latch  615  is driven to the logic low level.  
         [0041]    If the input signals AP and AN of FIG. 1 are not real signals, and thus, the output signal YNR 3  of the NOR gate  128  of FIG. 1 is at the logic high level during the five clock cycles of the clock signal CKDM, then the outputs of the NAND gate  611  and NOR gate  613  are driven to the logic low level and the logic high level, respectively. Accordingly, the output Y of the S-R latch  615  is driven to the logic high level.  
         [0042]    That is, the sampling circuit  132  of FIG. 6 sequentially samples signal YNR 3  (which indirectly represents the input signals AP and AN of FIG. 1) during the five clock cycles needed for a given signal to propagate through the five stages of D flip-flop  601 - 609  in order to better detect the validity of the input signals. If the input signals AP and AN are not real signals during consecutive five clock cycles of the clock signals CKDM, then the output signal Y is driven to the logic high level.  
         [0043]    Referring to FIG. 1, if the power down signal PD is at the logic low level, then the output YDM of the stage sampling circuit  132  becomes the final output signal Y of the signal detecting circuit  100 . If the power down signal PD is at the logic high level, then the final output signal Y of the signal detecting circuit  100  is set to be the logic high level. Therefore, since the signal detecting circuit  100  can adjust its operation by using the power down signal PD, unnecessary power consumption can be reduced.  
         [0044]    [0044]FIGS. 7 and 8 illustrate simulation results obtained by using an example implementation of the signal detecting circuit  100 , according to at least one embodiment of the present invention.  
         [0045]    Referring to FIG. 7, the first, second, and third clock signals CK 1 , CK 2 , and CK 3  (which are delayed relative to the clock signal CK, respectively) are generated. In the first period (1), when the voltage levels of the first and the second input signals AP and AN are higher than threshold levels of the first and second reference voltage signals BP and BN, the output signals Y 1 , Y 2 , and Y 3  of the first, second, and third dual amplifiers  102 ,  106 , and  110  are driven to the logic high level, and the output signal YNR 3  of the NOR gate  128  of FIG. 1 is driven to the logic low level. The final output signal Y of the signal detecting circuit  100  of FIG. 1 is driven to the logic low level.  
         [0046]    In the second period (2), when the voltage levels of the first and the second input signals AP and AN are lower than threshold levels of the first and second reference voltage signals BP and BN, the output signals Y 1 , Y 2 , and Y 3  of the first, second, and third dual amplifiers  102 ,  106 , and  110  are driven to the logic low level and the output signal YNR 3  of the NOR gate  128  of FIG. 1 is driven to the logic high level. During the five clock cycles of the clock signal CKDM, the output signal YNR 3  of the NOR gate  128  of FIG. 1 is sampled, and at the fifth clock of the clock signal CKDM, the output signal YDM of the sampling circuit  132  of FIG. 1 is transitioned to the logic high level. The final output signal Y of the signal detecting circuit  100  of FIG. 1 is driven to the logic high level.  
         [0047]    In the third period (3), when the first and second input signals AP and AN are detected not to be valid, the final output signal Y of the signal detecting circuit  100  of FIG. 1 is driven to the logic high level.  
         [0048]    [0048]FIG. 8 illustrates the simulation results in a wider period including the simulation results of FIG. 7. In the first period (1), when the input signals AP and AN are received, the output of the signal detecting circuit  100  of FIG. 1 is driven to the logic low level. In the second period (2), which corresponds to the five clock cycles from the time that the input signals AP and AN are not received, the output of the signal detecting circuit  100  of FIG. 1 is driven to the logic low level. In the third period (3), when the input signals AP and AN are not received after the five clock cycles, the output of the signal detecting circuit  100  of FIG. 1 is driven to the logic high level. In the fourth period (4), which corresponds to the five clock cycles from the time that the input signals AP and AN are received again, the output of the signal detecting circuit  100  of FIG. 1 is driven to the logic high level. In the fifth period (5), when the input signals AP and AN are received after the five clock cycles, the output of the signal detecting circuit  100  of FIG. 1 is driven to the logic low level.  
         [0049]    According to at least one embodiment of the present invention, since the input signals are detected through the input signal detection process over three clock cycles and the signal sampling process over five clock cycles, the input signal can be stably detected. In addition, since the operation of the signal detecting circuit can be adjusted in accordance with the power down signal, unnecessary power consumption can be reduced.  
         [0050]    While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.