Abstract:
A method and system for signal reception and processing, and more particularly for reducing the effects of random additive impulse interference is provided.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims priority from Russian Patent Application No. 2011150834, filed on Dec. 14, 2011, which is incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates generally to digital systems for signal reception and processing, and more particularly for reducing the effects of random additive impulse interference. 
         [0003]    Radio communication and location systems are susceptible to various forms of noise that can disrupt signal reception. Random impulse noise, which comprises one or more pulses with relatively high amplitude and short duration, is a commonly encountered noise. Generally speaking, sources of random impulse noise include microwave ovens, washing machines, light switches, car engines, and other electrical machines. Severe impulse noise can degrade signal reception quality and cause burst errors to occur. To ensure quality signal reception, system designers often install an apparatus in the receiving path of a receiver to detect impulse noise and remove it. However, since impulse noise can have various different properties, detection of impulse noise is a complex task. In the related art, there are known methods and apparatuses designed for negating random impulse interference. For example, in U.S. Pat. No. 7,706,542 the device contains a Noise Extraction Unit, a Hold Unit, a Noise Smoothing Unit, a Hold Control Signal Generation Unit, a Low Pass Filter, a Comparator, and an Absolute Value Circuit; however, the device is intended for removing impulse noise whose duration is much less than the period of the carrier or intermediate frequency. In addition, the device cannot be directly used in radio systems with digital modulation. Further, U.S. Pat. No. 7,103,122 discloses a noise canceller which includes a Noise Detector, a Switch, a Hold Circuit, and other components. In this patent the duration of noise is assumed to be much less than the period of the carrier oscillation. Strobe and impulse noise processing units of a Synchronous Code Division Multiple Access (SCDMA) system (Chip Blanking and Processing in SCDMA to Mitigate Impulse and Burst Noise and/or Distortion), described in U.S. Pat. Nos. 7,573,959 and 7,236,545, contain a Delay Block and a Impulse Noise Detection Block; however, such units are designed to remove impulse noise with a limited duration. 
       SUMMARY OF THE INVENTION 
       [0004]    The present disclosure relates generally to digital systems for signal reception and processing, and more particularly for reducing the effects of random additive impulse interference. Specifically, the present disclosure is directed at receiving, by a first low pass filter, an input in-phase signal comprising a predetermined in-phase signal and first impulse noise; generating, by the first low pass filter, a filtered input in-phase signal; receiving, by a second low pass filter, an input quadrature signal comprising a predetermined quadrature signal and second impulse noise; generating, by the second low pass filter, a filtered input quadrature signal; receiving, by a noise detection unit, the filtered in-phase signal and the filtered quadrature signal; based on the filtered in-phase signal and the filtered quadrature signal, generating, by the noise detection unit, a control signal; receiving, by a first channel impulse noise remover, the filtered in-phase signal and the control signal; based on the control signal, removing, by the first channel impulse noise remover, the first impulse noise from the filtered in-phase signal and output the predetermined in-phase signal; receiving, by a second channel impulse noise remover, the filtered quadrature signal; receiving, by the second channel impulse noise remover, the control signal; and based on the control signal, removing, by the second channel impulse noise remover, the first impulse noise from the filtered quadrature signal and output the predetermined quadrature signal. 
         [0005]    These and other advantages of the invention will be apparent to those of ordinary skill in the art by reference to the following detailed description and the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]      FIG. 1  illustrates an impulse noise remover, according to a first embodiment; 
           [0007]      FIG. 2  illustrates an impulse noise remover, according to a second embodiment; 
           [0008]      FIG. 3  illustrates an embodiment of a channel impulse noise remover; 
           [0009]      FIG. 4  illustrates an embodiment of a controlled impulse generator; 
           [0010]      FIG. 5  illustrates an embodiment of a controlled interpolator; 
           [0011]      FIG. 6  illustrates an embodiment of a channel impulse noise remover; 
           [0012]      FIG. 7  illustrates an embodiment of a noise detection unit; 
           [0013]      FIG. 8  illustrates an embodiment of an impulse generator; 
           [0014]      FIG. 9  illustrates an embodiment of a delay unit; 
           [0015]      FIG. 10  illustrates an embodiment of a front edge generator; 
           [0016]      FIG. 11  illustrates an embodiment of a back edge generator; and 
           [0017]      FIG. 12  illustrates exemplary signal profiles illustrating operation of a quadrature impulse noise remover. 
       
    
    
     DETAILED DESCRIPTION 
       [0018]    Modern digital radio communication, location and navigation systems include an impulse-noise-removing system to mitigate the effects of random impulse interference within an in-phase channel and within a quadrature channel. An in-phase signal is a signal multiplied by a reference signal. A quadrature signal is a signal multiplied by a reference signal shifted 90° out of phase. In an embodiment of the invention, the reference signal within the in-phase channel is a cosine signal; the reference signal within the quadrature channel is a sine signal. 
         [0019]      FIG. 1  illustrates a quadrature impulse noise remover system  1000 , according to a first embodiment of the invention. System  1000  includes low pass filter (LPF)  1100  of in-phase channel, LPF  1200  of quadrature phase channel, impulse noise remover  1300  of in-phase channel, impulse noise remover  1400  of quadrature phase channel and a noise detection unit  1500 . To suppress impulse interference in an in-phase signal, an in-phase signal is processed by system  1000  as follows: signal  1050  is fed, via port  1001 , to LPF  1100  which attenuates signal  1050  if signal  1050  has frequency higher than the cutoff frequency. Filtered signal  1052  is then outputted from LPF  1100  via output port  1003  and fed, in parallel, to input port  1005  of the impulse noise remover  1300  of in-phase channel and to input port  1007  of the noise detection unit  1500 . In an embodiment, impulse noise removers are configured to suppress impulse noise with impulse duration less than the duration of channel impulses of the desired signal, so the bandwidth of respective LPFs are selected considering minimal distortion of noise impulses and maximal filtration of additive white Gaussian noise (WGN). In other words, the LPF bandwidth is required to match the spectrum of expected impulse interference. 
         [0020]    Based on the analysis of the received in-phase signal  1052 , the noise detection unit  1500  generates a control signal  1054  which is synchronized in time with detected noise impulses. The control signal  1054  is then outputted from the noise detection unit  1500  via output port  1009  and fed to input port  1010  of the impulse noise remover  1300  of in-phase channel and to input port  1011  of the impulse noise remover  1400  of quadrature phase channel  1400 . In the impulse noise remover  1300  of in-phase channel, signals fed via ports  1005  and  1010  are compared and the detected noise is suppressed. Then, signal  1058  with suppressed impulse interference is outputted, via output port  1012 , from the impulse noise remover  1300  of in-phase channel. Further details of the impulse noise remover  1300  of in-phase channel and noise detection unit  1500  are discussed below. 
         [0021]    To suppress impulse interference in a quadrature phase signal, a quadrature phase signal is processed by system  1000  as follows: signal  1051  is fed, via port  1002 , to LPF  1200  which attenuates signal  1051  if signal  1051  has frequency higher than the cutoff frequency. Filtered signal  1053  is then outputted from LPF  1200  via output port  1004  and fed, in parallel, to input port  1006  of the impulse noise remover  1400  of quadrature phase channel and to input port  1008  of the noise detection unit  1500 . 
         [0022]    Based on the analysis of the received quadrature phase signal  1053 , the noise detection unit  1500  generates a control signal  1054  which is synchronized in time with detected noise impulses. The control signal  1054  is then outputted, via output port  1009 , from the noise detection unit  1500  and fed to input port  1010  of the impulse noise remover  1400  of in-phase channel and to input port  1011  of the impulse noise remover  1400  of quadrature phase channel. In the impulse noise remover  1400  of quadrature phase channel, signals fed via ports  1007  and  1011  are compared and the detected noise is suppressed. Then, signal  1057  with suppressed impulse interference is outputted, via output port  1013 , from the impulse noise remover  1300  of quadrature phase channel. Further details of the impulse noise remover  1400  of quadrature phase channel are discussed below. 
         [0023]    It is to be understood that the system  1000  of  FIG. 1  can process the in-phase signal and the quadrature phase signal either asynchronously or synchronously. It is to be understood that, generally pulse interference may occur in both in-phase channel and in quadrature channel simultaneously; however, as a level of interference can be different in both channels, the interference can be detected in each channel independently. Accordingly, in an embodiment of the present invention, an interference compensation is implemented in both in-phase channel and in quadrature channel notwithstanding the fact that interference may be detected only in one of the two channels. 
         [0024]      FIG. 2  illustrates a second embodiment of the quadrature impulse noise remover system  2000  which includes LPF  2100  of in-phase channel, LPF  2200  of quadrature phase channel, impulse noise remover  2300  of in-phase channel, impulse noise remover  2400  of quadrature phase channel, a noise detection unit  2500 , and a control impulse generator  2600 . 
         [0025]    To suppress impulse interference in an in-phase signal, an in-phase signal is processed by system  2000  as follows: signal  2050  is fed, via port  2001 , to LPF  2100  which attenuates signal  2050  if signal  2050  has frequency higher than the cutoff frequency. Attenuated signal  2052  is then outputted, via output port  2003 , from LPF  2100  and fed, in parallel, to input port  2005  of the impulse noise remover  2300  of in-phase channel and to input port  2007  of the noise detection unit  2500 . 
         [0026]    Based on the analysis of the received in-phase signal  1052 , the noise detection unit  2500  generates a control signal  2054  which is synchronized in time with detected noise impulses. The control signal  2054  is then outputted, via output port  2009 , from the noise detection unit  2500  and fed to the impulse noise remover  2300  of in-phase channel via input port  2010 , to the impulse noise remover  2400  of quadrature phase channel input port  2011 , and to a control impulse generator  2600  via input port  2012 . The control impulse generator  2600  generates additional control signal  2056  which is outputted from the control impulse generator  2600  via output port  2013  and fed, via input  2014 , to the impulse noise remover  2300  of the in-phase channel and to the impulse noise remover  2400  of the quadrature phase channel. 
         [0027]      FIG. 3  illustrates an embodiment of an impulse noise remover  1300  of  FIG. 1 . The impulse noise remover  1300  includes two sequentially-connected units: a delay circuit  3100  and a controlled interpolator  3200  where signal  3050  is fed to the impulse noise remover  1300  via input port  3001  of the delay circuit  3100 . Signals are processed in the impulse noise remover  3000  as follows: signal  3052  is outputted from the delay circuit  3100  via output port  3002  and fed to input port  3003  of the controlled interpolator  3200 . Further, signal  3054  is inputted to the impulse noise remover  1300  via input port  3004  of the controlled interpolator  3200 . Signal  3058  is outputted from the impulse noise remover  1300  via output port  3005  of the controlled interpolator  3200 . It is to be understood the similar signal processing is applicable for impulse noise remover  1400  of  FIG. 1 . 
         [0028]    In an embodiment, delay time in the delay circuit  3100  is selected equal to the signal delay in the noise detection unit  1500  of  FIG. 1 . The controlled interpolator  3200  generates the impulse interference of a finite duration in accordance with the control signal being fed to impulse noise remover, via the delay circuit  3100  and the controlled interpolator  3200 . During impulse interference the behavior of the signal is determined by interpolating the received signal using a zero-order interpolator. In an embodiment, zero or first order interpolators are used to determine the behavior of the signal. 
         [0029]      FIG. 4  illustrates a controlled impulse generator  2600  of  FIG. 2 . According to an embodiment, the controlled impulse generator  2600  includes sequentially connected smoothing filter  4100  and relay circuit  4200  where input signal  2054  is imputed to the controlled impulse generator via input port  4001  of the smoothing filter  4100 . Signals are processed in the controlled impulse generator  2600  as follows: Signal  4052  is outputted from the smoothing filter  4100  via output port  4002  and fed to input port  4003  of the relay circuit  4200 . Signal  4056  is outputted from the controlled impulse generator  2600  via output port  4004  of the relay circuit  4200 . In an embodiment, the controlled impulse generator  2600  is configured to generate a “window” where or during which a fragment of the received signal is replaced by a function obtained from the smoothed signal. In this smoothed signal the impulse interference has been compensated by a zero-order interpolator. In an embodiment, a rectangular impulse, duration of which is equal to the duration of the window where a fragment of the received signal has been replaced by the signal from the output of the smoothing filter  4100 , is generated at the output port  4004  of the relay circuit  4200 . 
         [0030]      FIG. 5  illustrates a controlled interpolator  3200  of  FIG. 3 . The controlled interpolator  3200  includes a sample and hold unit  5100  and a switch  5200 . The signal is processed by the controlled interpolator  3200  as follows: input signal  3052  is inputted, in parallel, to the controlled interpolator through input port  5001  of the sample and hold circuit  5100  and to input port  5005  of the switch  5200 . Input signal  5054  is inputted to the controlled interpolator  5000  via input port  5030  and fed, in parallel, to the sample and hold circuit  5100  via input port  5002  and to the switch  5200  via input port  5006 . Signal  5052  is outputted from the sample and hold circuit  5100  via output port  5003  and fed to the switch  5200  via input port  5004 . Signal is outputted from the controlled interpolator  3200  via output port  5020  of the switch  5200  and corresponds to a signal  1058  of  FIG. 1 . 
         [0031]    In an embodiment, when a zero-order interpolation algorithm is applied, the input signal  1054  of  FIG. 1  comprising a mixture of the desired signal (for example, Binary Phase Shift Keying (BPSK)—modulated, Additive White Gaussian Noise (AWGN)) and random impulse noise are fed to the channel impulse noise remover  1300  of  FIG. 1  via input port  5005  of the switch  5200  and to the input port  5001  of the Sample and Hold Unit  5100  of the controlled interpolator  3200 . With the absence of impulse noise, the received signal is fed, via input port  5005  of the switch  5200 , to output port  5056  of the switch  5200 . 
         [0032]    When the control signal is fed to input port  3004  of controlled interpolator  3200 , a processor of the sample and hold unit  5100  stores the value of the received signal and transmits it to input port  5004  of the switch  5200  (input port  5004  being set to “reading” mode). Once the control signal at input port  3003  of controlled interpolator  3200  is re-set to “logic zero” (i.e., switched off), the switch  5200  is reset to have its input port  5005  to be set to “reading” mode. Thus, during noise impulse the level of the signal at the output port  3005  of controlled interpolator  3200  remains fixed and thereby impulse noise effects become essentially reduced. 
         [0033]      FIG. 6  illustrates the impulse noise remover  2300  of  FIG. 2 . The impulse noise remover  2300  includes delay circuit  6100 , delay circuit  6400 , controlled interpolator  6200 , smoothing filter  6300 , and a switch  6500 . Signal is processed by the impulse noise remover  2300  as follows: input signal  2052  is inputted to the impulse noise remover  2300  via input port  6002  of the delay circuit  6100 . Signal  6052  is outputted from the delay circuit  6100  and fed, in parallel, to the delay circuit  6400  via input port  6006  and to the controlled interpolator  6200  via input port  6004 . Input signal  2054  is inputted to the impulse noise remover  2300  via input port  6012  of the controlled interpolator  6200 . Output signal  6056  is outputted from the controlled interpolator  6200  via output port  6011  and fed to the smoothing filter  6300  via input port  6005 . Output signal  6060  is outputted from the smoothing filter  6300  via output port  6009  and fed to the switch  6500  via input port  6008 . Input signal  2056  is inputted to the impulse noise remover  2300  via input port  6013  of the switch  6500 . Output signal  6058  is outputted from the delay circuit  6400  via output port  6010  to the switch  6500  via input port  6007 . Output signal  2058  is outputted from the impulse noise interpolator  2300  via output port  6014  of the switch  6500 . 
         [0034]    In an embodiment, the controlled interpolator  6200  transmits the impulse interference of a finite duration (strobes) in accordance with the control signal being fed, through the delay circuit  6100 , as well as being fed to the controlled interpolator  6200 . During impulse interference the behavior of the signal is determined by interpolating the received signal using a zero-order interpolator. In an embodiment, zero or first order interpolators are used to interpolate the received signal. The smoothing filter  6300  of the channel impulse noise remover  2300  is utilized as an LPF, the characteristics of which can be selected based on required order of a final signal interpolation during noise impulse. In an embodiment the delay circuit  6400  delays a signal  6052  by the time equal to the signal delay of the signal  6056  in the smoothing filter  6300 . 
         [0035]    In an embodiment, the impulse noise remover  2300  transmits, through the switch  6500 , a signal from the delay circuit  6400  when the control signal is equal to “logic zero.” Alternatively, the impulse noise remover  2300  transmits, through the switch  6500 , a signal from the smoothing filter  6300  when the control signal is equal to “logic unit”. In an embodiment, the switch  6500  is similar to the switch  5200  in controlled interpolator  3200  of  FIG. 5 . One skilled in the art will recognize that the system configuration of  FIG. 6  is non-limiting and may include additional and/or desired components and/or configurations. 
         [0036]      FIG. 7  illustrates noise detection unit  1500  of  FIG. 1 . The noise detection unit  1500  can be implemented as an embodiment of noise detection unit  2500  of  FIG. 2 . The noise detection unit  1500  includes two parallel channels. A first channel includes sequentially connected modulus (absolute value) calculation unit  7100  to calculate the absolute value, comparator  7500 , and impulse generator  7700 . A second channel includes sequentially connected modulus (absolute value) calculation unit  7200  to calculate the absolute value, comparator  7400 , and impulse generator  7600 . The noise detection unit  1500  also includes a threshold generation unit  7300  whose output  7007  is connected to a second input (input  7009 ) to the comparator  7500  and to a second input (input  7008 ) to the comparator  7400 . 
         [0037]    In an embodiment, modulus calculation units  7100  and  7200  calculate absolute values for signals received from each channel through respective inputs  7020  and  7030 . Signals are processed in the noise detection unit  1500  as follows: input signal  1052  is fed to the noise detection unit  1500  via input port  7001  of the modulus calculation unit  7100 . Output signal  7052 , which includes values calculated in the modulus calculation unit  7100 , is outputted via output port  7003  and fed to comparator  7500  via input port  7005 . A threshold generation unit  7300  generates a signal  7058  which is outputted from the threshold generation unit  7300  via output port  7007  and fed, in parallel, to the comparator  7500  via input port  7009  and to the comparator  7400  via input port  7008 . In the comparator  7500  a value within the signal  7052  is compared with the predetermined threshold value within the signal  7058  and is set in the comparator unit  7500 . 
         [0038]    In an embodiment, the threshold value generated by the threshold generation unit  7300  is normalized to the root-mean-square value of the binary signal. For example, the threshold can be calculated as 
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         [0039]    Where T s  is the duration of the channel symbol, τ p  is the average duration of noise impulse, h sn   2  is the symbol signal-to-noise ratio SNR (current or predicted), U n  is the coefficient dependent on SNR h sn   2 . U n  can be within a range from 3 to 6 when SNR varies from 0 to 20 dB. 
         [0040]    Output signal  7054  is outputted from the comparator  7500  via output port  7011  and fed to the impulse generator  7700 . 
         [0041]    The impulse duration at the output port  7011  of the comparator unit  7500  can be determined by the time of exceeding the predetermined threshold value by the noise impulse; therefore, the duration of these impulses is less than the actual duration of the noise impulse. To fully compensate for noise impulses in the impulse generator  7700 , the duration of the impulses can be increased. Subsequently, generated control impulse  7056  is outputted from the impulse generator  7700  via output port  7015  and fed to the logic unit OR  7800  via input port  7017 . 
         [0042]    Similarly, input signal  1053  is fed to the noise detection unit  1500  via input port  7002  of the modulus calculation unit  7200 . Output signal  7053 , which includes values calculated in the modulus calculation unit  7200 , is outputted via output port  7004  and fed to comparator  7400  via input port  7006 . In the comparator  7400  a value within the signal  7053  is compared with the predetermined threshold value within the signal  7058  outputted by the threshold generation unit  7300  and is set in the comparator unit  7400 . 
         [0043]    Output signal  7055  is outputted from the comparator  7400  via output port  7010  and fed to the impulse generator  7600  via input port  7012 . Subsequently, generated control impulse  7057  is outputted from the impulse generator  7600  via output port  7014  and fed to the logic unit OR  7800  via input port  7016 . The output signal  1054  of the noise detection unit  1500  is then outputted from output port  7018  of the logic unit OR  7800 . 
         [0044]      FIG. 8  illustrates an impulse generator  7700 . The impulse generator  7700  can also be implemented as an embodiment of impulse generators  7600  of  FIG. 7 . In an embodiment, the impulse generator  7700  includes back edge generator  8100 , delay unit  8200 , logic block AND  8400 , logic block NO  8300 , and a trigger  8500 . Signal is processed by the impulse generator  7700  as follows: input signal  7054  is inputted to the impulse generator  7700 , in parallel, via input port  8001  of the back edge generator  8100 , input port  8005  of the logic block NO  8300 , and input port  8011  of the trigger  8500 . The output signal  8052  is outputted from the back edge generator  8100  via output port  8002  and fed to the delay unit  8200  via input port  8003 . The output signal  8056  is outputted from the delay unit  8200  via output port  8004  and fed to the logic unit AND  8400  via input port  8008 . The output signal  8054  is outputted from the logic unit NO  8300  via output port  8006  and fed to the logic unit AND  8400  via input port  8007 . The logic unit AND  8400  outputs signal  8058  via output port  8009 , where signal  8058  is fed to the trigger  8500  via input port  8010 . The output signal  7056  is outputted from the impulse generator  7700  via output port  8012  of the trigger  8500 . 
         [0045]    In an embodiment, the trigger  8500  is set to the “logic unit” mode by the front edge of the input impulse. The back edge generator  8100  generates a short impulse corresponding to the back edge of the input impulse. This impulse is delayed by a predetermined time interval by the delay unit  8200  and resets the setting trigger  8500  to “logic zero” mode. In an embodiment, the logic units NO  8300  and AND  8400  are required to prevent the setting trigger  8500  from being reset at close input impulses, i.e., when the delayed back edge of one impulse overlaps the duration of the subsequent impulse. 
         [0046]      FIG. 9  illustrates an embodiment of a delay unit  8200 . The delay unit  8200  can be implemented as the embodiment of the delay unit  8200  of  FIG. 8 . The delay unit  8200  includes two triggers  9400  and  9700 , two logic blocks OR  9200  and  9800 , a back edge generator  9900 , two front edge generators  9300  and  9500 , and two delay circuits  9100  and  9600 . Signals in the delay unit  8200  are processed as follows: signal  8052  is inputted to the delay unit  8200  via input port  9001  of the trigger  9700  and to the trigger  9400  via input port  9019 . The output signal  9052  is outputted from the trigger  9700  via output port  9002  and fed, in parallel, to the logic block OR  9800  via input port  9004  and to the front edge generator  9500  via input port  9009 . The output signal  9071  is outputted from the front edge generator  9500  via output port  9025  and fed, in parallel, to the delay circuit  9600  via input port  9020  and to the logic block OR  9200  via input port  9016 . 
         [0047]    Output signal  9061  is outputted from the trigger  9400  via output port  9010  and fed, in parallel, to the logic block OR  9800  via input port  9005  and to the front edge generator  9300  via input port  9011 . Output signal  9053  is outputted from the front edge generator  9300  via output port  9012  and fed to the delay circuit  9100  via input port  9013 . Output signal  9055  is outputted from the delay circuit  9100  via output port  9014  and fed to the logic block OR  9200  via input port  9015 . Output signal  9057  is outputted from the logic block OR  9200  via output port  9017  and fed to the trigger  9400  via input port  9018 . Finally, output signal  8056  is outputted from the delay unit  8200  via output port  9008  of the back edge generator  9900 . 
         [0048]    In an embodiment, the input signal  8052  sets triggers  9700  and  9400  into “logic unit” mode. The front edge generator  9500  generates a short impulse corresponding to the front edge of the impulse at the output  9002  of trigger  9700 . Said impulse with a delay assigned by the delay circuit  9600  resets the trigger  9700 . It is to be understood that the value of delay in delay circuit  9600  can be selected greater or equal to the average noise impulse duration. 
         [0049]    Since impulses with the following interval less than the delay value in the delay circuit  9600  can present at the input  9030  of the delay unit  8200 , there is an additional parallel channel including trigger  9400 , the front edge generator  9300 , the delay circuit  9100 , and logic unit OR  9200 . The delay in the second delay circuit  9100  can be set being equal to the delay in first delay circuit  9600 . Said channel, along with logic unit OR  9800  and the back edge generator  9900 , provides generation of the output impulse delayed by an assigned value relative to the last of the closest pair of the input impulses. 
         [0050]      FIG. 10  illustrates an embodiment of a front edge generator  9300  of  FIG. 9 . The front edge generator  9300  can be implemented as the embodiment of the front edge generator  9500  of  FIG. 9 . The front edge generator  9300  includes a delay circuit  10100 , a logic block XOR  10200 , and a logic block AND  10300 . In an embodiment, signals are processed in the front edge generator  9300  as follows: the signal  9052  is inputted to the front edge generator  9300  via input port  10001  of the delay circuit  10100 , via input port  10004  of the logic block XOR  10200 , and via input port  10060  of the logic block AND  10300 . Signal  10052  is outputted from the delay circuit  10100  via output port  10002  and fed to the logic block XOR  10200  via input port  10003 . Signal  10054  is outputted from the logic block XOR  10200  via output port  10005  and fed to the logic block AND  10300  via input port  10008 . Output signal  8060  from the logic block AND  10300  and the output signal from the front edge generator  9300 . One skilled in the art will recognize that the system configuration of  FIG. 9  is non-limiting and may include additional and/or desired components and/or configurations. 
         [0051]      FIG. 11  illustrates a back edge generator  9900  of the delay unit  8200 . The back edge generator  9900  can be implemented as the embodiment of the back edge generator  8100  of  FIG. 8 . The back edge generator  9900  includes a delay circuit  11100 , a logic block XOR  11200 , and a logic block AND  11300 . It is to be understood that, in discrete systems, delay circuit  11100  provides a one-clock delay. 
         [0052]    In an embodiment, signals are processed in the back edge generator  9900  as follows: signal  9054  is inputted to the back edge generator  9900  via input port  11001  of the delay circuit  11100  and via input port  11004  of the logic block XOR  11200 . The delay circuit  11100  outputs signal  11052 , in parallel, to the logic block XOR  11200  via input port  11003  and to the logic block AND  11300  via input port  11007 . The logic block XOR  11200  outputs signal  11054  via output port  11005  to the logic block AND  11300  via input port  11006 . The logic block AND  11300 . The output signal  8056  from the logic block AND  11300  via output port  11008  is the output signal from the back edge generator  9900 . 
         [0053]      FIG. 12  shows examples of signal profiles. These profiles illustrate the operation of impulse noise remover  2  ( FIG. 6 ). The signal profiles are provided for the signals designated as  6052 ,  2054 , and  2058  in  FIG. 6 . These signals represent respectively: the received signal before compensating for impulse noise (signal  6052 ), the signal at the output of noise detection unit  1500  (point  2054 ), and signal at the output of impulse noise remover  2300  (point  2058 ). The profiles in  FIG. 12  are provided for one of quadrature signals. It can be observed that the proposed apparatus efficiently removes impulse interference present in the channel. 
         [0054]    The foregoing Detailed Description is to be understood as being in every respect illustrative and exemplary, but not restrictive, and the scope of the invention disclosed herein is not to be determined from the Detailed Description, but rather from the claims as interpreted according to the full breadth permitted by the patent laws. It is to be understood that the embodiments shown and described herein are only illustrative of the principles of the present invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention. Those skilled in the art could implement various other feature combinations without departing from the scope and spirit of the invention.