Abstract:
Power supplies and related methods capable of reducing output voltage ripple. A power supply provides an output voltage to a load and controls the output voltage to approach a target voltage. The output voltage is compared with the target voltage to generate a control signal, which controls an output current of the power supply. When the control signal causes an increase in the output current, the target voltage is reduced.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to power supplies and related methods of reducing output voltage ripple. 
         [0003]    2. Description of the Prior Art 
         [0004]    For some electronic devices that are very sensitive to supply voltage, e.g. central processing units (CPUs) or optical sensors of digital cameras, variations in voltage provided by a power supply must always be kept within very tight tolerances, or the electronic device may be damaged or have errors in operation. 
         [0005]      FIG. 1  shows a power supply  10  and a load  12 . Load  12  is shown as a current source  14  which draws a load current I LOAD  representing how light or heavy load  12  is, as well as output current I OUT  of power supply  10  under stable conditions. 
         [0006]    Power supply  10  typically is designed so that its output voltage V OUT  can be rapidly stabilized to a fixed voltage regardless of changes in size of load  12 . As shown in  FIG. 2 , when load current I LOAD  goes from low to high, because output current I OUT  cannot immediately increase with load current I LOAD , output voltage V OUT  temporarily drops . However, as power supply  10  increases output current I OUT , output voltage V OUT  quickly rises to return to voltage V TAR0 . Similarly, when load current I LOAD  drops from high to low, output voltage V OUT  temporarily exceeds voltage V TAR0 , but rapidly drops back to the same voltage V TAR0 . 
         [0007]    However, some electronic devices have stringent requirements for peak-to-peak output voltage variation of power supply  10 , which is shown in  FIG. 2  as peak-to-peak variation ΔV OUT1 . As shown in  FIG. 2 , peak-to-peak variation ΔV OUT1  comprises overshoot and undershoot of output voltage V OUT . 
         [0008]    Peak-to-peak variation of output voltage is known as output voltage ripple, which circuit designers have always had difficulty reducing. 
       SUMMARY OF THE INVENTION 
       [0009]    According to an embodiment, a method of reducing ripple is for use in a power supply. The power supply provides an output voltage to a load, and causes the output voltage to approach a target voltage. The method comprises comparing the output voltage and the target voltage to generate a control signal, and changing the target voltage according to the control signal. The target voltage is lowered when the control signal indicates that output current increases. 
         [0010]    According to an embodiment, a power supply provides an output voltage to a load, and causes the output voltage to approach a target voltage. The power supply comprises a compensation circuit for comparing the output voltage and the target voltage to generate a control signal, and a bias circuit for changing the target voltage according to the control signal. The target voltage is lowered when the control signal indicates that the output current increases. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  illustrates a power supply and a load. 
           [0013]      FIG. 2  illustrates peak-to-peak output voltage variation of power supply. 
           [0014]      FIG. 3  shows two relationships between output current and target voltage. 
           [0015]      FIG. 4  shows a possible waveform of output voltage generated by variation of load current as generated by a power supply corresponding to line  18  of  FIG. 3 . 
           [0016]      FIG. 5A  shows a current mode booster according to an embodiment . 
           [0017]      FIG. 5B  shows a current mode booster according to another embodiment. 
           [0018]      FIG. 6A  shows an LDO according to an embodiment. 
           [0019]      FIG. 6B  shows an LDO according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Two lines in  FIG. 3  show two relationships between output current I OUT  and target voltage V TARGET . Target voltage V TARGET  is a desired target for output voltage V OUT  of power supply. Line  16  corresponds to a traditional power supply having target voltage V TARGET  that is unrelated to variations in output current I OUT , approximately staying at fixed voltage V TAR0 . Line  18  corresponds to a power supply according to an embodiment, which has target voltage V TARGET  that drops with increased output current I OUT .  FIG. 4  shows a possible waveform of output voltage V OUT  generated by variation of load current I LOAD  as generated by a power supply corresponding to line  18  of  FIG. 3 . It can be seen from  FIG. 4  and  FIG. 3  that when load current I LOAD  instantaneously increases from I OUT1    to I   OUT2 , target voltage V TARGET  drops from V OUT1  to V OUT2  as output current I OUT  increases from I OUT1  to I OUT2 . Thus, when load current I LOAD  is I OUT2 , output voltage V OUT  settles to V OUT2 . Conversely, when load current I LOAD  drops sharply from I OUT2  to I OUT1 , output voltage V OUT  starts changing from V OUT2 , and ultimately settles at V OUT1 . 
         [0021]    Comparing  FIG. 4  with  FIG. 2 , it can be seen that, through appropriate design, because only one of overshoot and undershoot need be considered, peak-to-peak variation ΔV OUT2  in  FIG. 4  may be reduced to half of peak-to-peak variation ΔV OUT1  of  FIG. 2 , making it easier to meet requirements of some electronic devices that are sensitive to peak-to-peak output voltage variation. 
         [0022]    Line  18  of  FIG. 3  represents target voltage V TARGET  dropping with increasing output current I OUT . This concept may be used in all kinds of power supplies, e.g. switching mode power supplies (SMPS) or low dropout (LDO) regulators. In the following, two boosters (a type of SMPS) and two LDOs act as embodiments. However, the present invention is not limited to SMPS and LDO architectures, and could be realized in other power supply types not described herein. 
       &lt;Booster  1 &gt; 
       [0023]      FIG. 5A  shows a current mode booster  20   a  according to an embodiment. Inductor  28 , diode  30 , power switch  32 , current sense resistor  34 , voltage divider  24 ,  26 , and power supply controller  46   a  are interconnected in a typical booster architecture. This power supply architecture is well known in the art, and not described again herein. 
         [0024]    Power supply controller  46   a  periodically switches power switch  32  to make output voltage V OUT  approach a target voltage V TARGET,  and this target voltage V TARGET  is determined by power supply controller  46   a.  In the embodiment shown in  FIG. 5A , error amplifier  38  compares voltages at a positive input node and negative input node thereof. Equivalently, error amplifier  38  compares target voltage V TARGET  and output voltage V OUT  to generate compensation voltage V COM  at output node, which is one node of compensation circuit  36 . Compensation voltage V COM  can be seen as a control signal for controlling peak value of current sense voltage V CS , and correspondingly controlling output current I OUT  flowing through diode  30 . High compensation voltage V- COM  simultaneously implies peak current sense voltage V CS  and high output current I OUT . In an embodiment, the higher the compensation voltage V COM , the higher the peak of current sense voltage V CS , and the higher the duty cycle of power switch  32 . Duty cycle is percentage of one switching cycle for which power switch  32  is closed. 
         [0025]    Power supply controller  46  has a voltage-controlled current source  40   a,  which generates offset current I OFFSET-a  according to compensation voltage V COM , which is extracted from positive input node of error amplifier  38 . The higher compensation voltage V COM  is, the larger the offset current I OFFSET-a . Power supply controller  46   a  has a feedback mechanism that adjusts output voltage V OUT  to approach target voltage V TARGET,  causing positive input node and negative input node of error amplifier  38  to be a virtual short-circuit (have the same voltage). Thus, target voltage V TARGET  and fixed reference voltage V REF  have a relationship described by equation (1): 
         [0000]        V   TARGET   *R   26 /( R   24   +R   26 )= V   REF   −I   OFFSET-a   *R   42a   (1)
 
         [0000]    where R X  represents resistance of resistor X. It can be seen from equation (1) that as compensation voltage V COM  increases, output current I OUT  increases, offset current I OFFSET-a  increases, and target voltage V TARGET  decreases. In this way, a relationship between target voltage V TARGET  and output current I OUT  similar to that shown by line  18  of  FIG. 3  can be generated, which may reduce output voltage ripple. 
       &lt;Booster II&gt; 
       [0026]      FIG. 5B  shows a current mode booster  20   b  according to another embodiment. Similarities between the architectures shown in  FIG. 5B  and  FIG. 5A  are familiar to those skilled in the art, and are not repeated here.  FIG. 5B  differs from  FIG. 5A  in interconnections related to positive and negative input nodes of error amplifier  38 . Similarly, based on the concept of virtual short-circuits, relationship between target voltage V TARGET  of output voltage V OUT  and reference voltage V REF  can be derived as equation (2): 
         [0000]        V   TARGET   *R   26 /( R   24   +R   26 )+ I   OFFSET-b *( R   42b   +R   24   *R   26 /( R   24   +R   26 ))= V   REF   (2)
 
         [0027]    From equation (2), it can be seen that when output current I OUT  increases, it implies that compensation voltage V COM  increases, offset current I OFFSET-b  increases, and target voltage V TARGET  decreases. 
         [0028]    Similar to booster  20   a  of  FIG. 5A , booster  20   b  of  FIG. 5B  can generate a similar relationship between target voltage V TARGET  and output current I OUT  to that shown by line  18  of  FIG. 3 . 
         [0029]    In  FIG. 5A , offset current I OFFSET-a  generated by voltage-controlled current source  40   a  is extracted from positive input node of error amplifier  38 . In  FIG. 5B , offset current I OFFSET-b  generated by voltage-controlled current source  40   b  is injected into negative input node of error amplifier  38 . In other embodiments, an offset current may be extracted from positive input node of error amplifier  38 , and another offset current may simultaneously be injected into negative input node. 
       &lt;LDO I&gt; 
       [0030]      FIG. 6A  shows an LDO  60   a  according to an embodiment. An input power supply node of power component P-type Metal-Oxide-Semiconductor (PMOS) MPO receives input voltage V IN , and an output power supply node provides output voltage V OUT . Central node of voltage divider resistors R 1 , R 2  generates feedback voltage V FB , which equivalently represents output voltage V OUT  . Error amplifier  64  can be seen as a compensation circuit, and has comparator  62  and buffer stage  66 . Comparator  62  compares reference voltage V REF  and feedback voltage V FB , and generates a differential signal from two differential output nodes (PN and NN). Buffer stage  66  generates control signal V G  at power component PMOS MPO according to differential signal. Control signal V G  approximately determines output current I OUT . Circuit operation of error amplifier  64  is known to those skilled in the art, and not repeated here. 
         [0031]    PMOS  70  can be seen as a shifter circuit, and generates offset current I OFFSET1  according to control signal V G . PMOS  70  and PMOS MPO can approximately be seen as a current mirror, so that offset current I OFFSET1  roughly reflects output current I OUT . Offset current I OFFSET1  is injected into differential output node PN. When offset current I OFFSET1  is 0, LDO  60   a  causes output voltage V OUT  to approach a target voltage V TARGET , and this target voltage V TARGET  causes feedback voltage V FB  to equal reference voltage V REF . However, when offset current I OFFSET1  increases, feedback voltage V FB  needs to drop to keep the same differential signal that existed prior to offset current I OFFSET1  increasing. Thus, it can be seen that when offset current I OFFSET1  increases, output current I OUT  increases, and target voltage V TARGET  decreases. In this way, a relationship between target voltage V TARGET  and output current I OUT  similar to that shown by line  18  of  FIG. 3  can be generated, which may reduce output voltage ripple. 
       &lt;LDO II&gt; 
       [0032]      FIG. 6B  shows an LDO  60   b  according to an embodiment. Similarities and differences between  FIG. 6B  and  FIG. 6A  are apparent to those skilled in the art, and not repeated here. Different from  FIG. 6A , shifter circuit of  FIG. 6B  comprises PMOS  70 , N-type Metal-Oxide-Semiconductor (NMOS)  72  and NMOS  74 . Offset current I OFFSET1  of  FIG. 6B  is not injected into differential output node PN, but flows through current mirror formed by NMOS  72  and NMOS  74  to generate offset current I OFFSET2  extracted through differential output node NN. 
         [0033]    According to circuit description of  FIG. 6A , those with basic circuit knowledge can arrive at the following conclusion about  FIG. 6B . When offset current I OFFSET1  increases, output current I OUT  increases, offset current I OFFSET2  increases, and target voltage V TARGET  decreases. Thus, LDO  60   b  can generate a relationship between target voltage V TARGET  and output current I OUT  similar to that shown by line  18  of  FIG. 3 , which may reduce output voltage ripple. 
         [0034]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.