Abstract:
The present invention purports to provide a novel B-class complementary circuit of direct-coupling type having good characteristics of low dispersions of voltage gain and low temperature dependency. The apparatus of the present invention can perform the above-mentioned excellent characteristics by utilizing several current-mirror circuits in a direct coupled circuit which comprises 
     an output stage driving circuit, 
     a B-class complementary connected output stage, and 
     a bias-stabilization circuit, formed as a differential amplifier working as a pre-drive stage for driving the output stage driving circuit; and 
     by utilizing further current-mirror circuits for constant current feeding to a load circuit of the driving circuit and for the bias stabilizing circuit.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an improvement in a B-class complementary circuit made in an IC providing stable performance despite temperature variation and variation of electric characteristics of various components in IC. 
     2. Prior Art 
     Hitherto a B-class complementary circuit for use, for example, as a vertical deflection circuit in a television receiver has been constituted as shown in FIG. 1. In the conventional circuit of FIG. 1, vertical oscillator 1 issues synchronizing output signals to a sawtooth-wave generator 2, which generates sawtooth-wave voltage signal synchronized by the output of the circuit 1. Numeral 3 designates a stabilized voltage source. The circuit of the transistors Q 1  and Q 2  is a bias stabilization circuit for stabilizing the operating point of output stage NPN transistors Q 10  and Q 11 . Current to the bias stabilization circuit of Q 1 , and Q 2  is fed through the emitter of a transistor Q 3  and a resistor R 1 . The sawtooth-wave voltage input to the base (A) of the transistor Q 1  is amplified by the differential amplifier Q 1  -Q 2  and fed to the base (C) of a driving transistor Q 8 . A transistor Q 7  is a load of the driving transistor Q 8  which is fed of the collector current therethrough. And at the same time, the transistor Q 7  and transistors Q 5  -Q 6  constitute a current mirror circuit. By means of this current mirror circuit, mean value of the collector current of the transistor Q 7  (whose collector current is controlled by the current-mirror circuits) is equivalent to that of the transistor Q 4 , since the latter is connected by collector-to-collector in series to the transistor Q 5 . A PNP transistor Q 9  and the output transistor Q 11  form a composite Darlington transistor-circuit, and diodes D 2  and D 3  compensate the base-emitter threshold voltages of transistors Q 9  and Q 10 . 
     In the conventional circuit of FIG. 1, the output provided at the output terminal E is fed to a deflection coil L as a load. C 2  designates output coupling capacitor, R 10  designates a resistor through which a part of the sawtooth-wave voltage is taken out from a current of the deflection coil L in order to improve linearity of the sawtooth-wave voltage. The voltage taken out through the resistor R 7  is smoothed by a capacitor C 3 , divided by a dividing network R 7 , R 8 , and then this smoothed voltage is fed back to the base (A) of the transistor Q 1  through R 9 . At the point F, an output signal of a parabola-shaped wave form having a mean value of the outputs of the transistors Q 10  and Q 11  appears. The differential circuit Q 1  -Q 2  compares the signal at the point A with the reference voltage at the point B, so that the voltage at the point A is controlled to become equal to the reference potential at the point B. The operation of the output sawtooth-wave of the output stage Q 10  -Q 11  is stabilized by the negative feed-back through the register R 9 , in such a manner that the mean voltage of point E is at a predetermined value. 
     The above-mentioned conventional circuit has the following three defects: 
     (1) Firstly, the output signal amplitude of the output stage Q 10  -Q 11  does not respond to increases and decreases in the source voltage V cc  of the power source. Accordingly upon increase and decrease of the source voltage V cc , the output signal becomes saturated at its ground level side or its source voltage level side, thereby causing vertical shrinkage at the upper end parts or lower end parts of the image. 
     (2) Secondly, spread of the voltage gain from point A to point E due to the spread of resistances value of the circuit becomes large. 
     (3) Thirdly, temperature dependency of the voltage gain between the point A and point E is undesirably large. 
     The above-mentioned defects of the conventional apparatus of FIG. 1 are elucidated more in detail in the following 
     With respect to the first defect, the mean value V o  at the point E of the output stage Q 10  -Q 11  is given by the following equation (1). ##EQU1## where: V s  is stabilized output voltage of the stabilized voltage source 3, 
     V BE4  is base-emitter forward voltage of the transistor Q 4 , and 
     R 3 , R 4 , R 7  and R 8  are the values of resistors of the same respective designations. 
     In the circuit, the voltage V s  is independent from changes in the power source voltage Vcc. On the other hand, output voltage of the sawtooth-wave generator 2, to be supplied at the point A (the base of the transistor Q 1 ) generally changes roughly proportional to changes in the source voltage V cc . FIG. 2 shows relation between various voltages to the power source voltage plotted on the abscissa. In FIG. 2: 
     curve a shows the source voltage V cc , 
     curve b shows the saturation level at the power source voltage side (higher side) of the output stage Q 10  -Q 11 . 
     curve c shows the saturation level at the ground voltage side (lower side) of the output stage Q 10  -Q 11 , 
     curve d shows the mean voltage V o  of the output signal at the point E, 
     curve e shows upper end voltage of the output signal, and 
     curve f shows lower end voltage of the output signal. 
     Now, the V cc  is set at such an appropriate operation point V cc1 , where a voltage difference between the curve b and curve e and a voltage difference between the curve c and curve f is equal. Then the curve c and curve f cross at V cc  =V cc3 , and the curve b and curve e cross at V cc  =V cc2  as shown in FIG. 2. This means that as the power source voltage V cc  goes down, when V cc  becomes lower than V cc2  the upper end of the sawtooth-wave becomes saturated thereby forming upper-end shrinkage of reproduced images. On the other hand, as the power source voltage V cc  goes up and when V cc  becomes higher than V cc3  the lower ends of the sawtooth-wave becomes saturated thereby forming lower-end shrinkage of reproduced images. Accordingly, for instance, a battery voltage drops in a battery operated television set, the lower end of the picture shrinks when the power source voltage becomes low. 
     The second and the third defects are elucidated below: 
     The voltage gain G v  from the point A to point E of the circuit of FIG. 1 is represented as follows: ##EQU2## where: g m1  is transfer admittance of the differential amplifier of Q 1  and Q 2 . 
     h FE8  is DC current amplification factor of the driving transistor Q 8 , and it is provided that h FE8  &gt;&gt;1. 
     h FEO  is DC current amplification factor of the output transistors Q 10  +Q 11 , 
     R 07  is output impedance of the transistor Q 7   
     R L  is the impedance of the load L, and 
     R 2  and R 5  are the resistance value of the resistors of the same designations. 
     (The above-mentioned equation (2) is described in detail in a book entitled &#34;IC Kyoshitsu&#34; (IC classroom) published by NHK shuppan (Publishing department of the Japan Broadcasting Corporation), page 180-184.) 
     The transfer admittance g m1  can be represented by the following equation (3): 
     
         g.sub.m1 =A·(q/4kT)·I.sub.o1             ( 3) 
    
     where: 
     A is a factor of the transfer admittance g m1  for the difference of two input voltages to the two bases of the differential amplifier Q 1  -Q 2 , 
     I o1  is the current through the current source Q 3  -R 1  to the differential amplifier Q 1  -Q 2 , 
     k is the Boltzman&#39;s constant, 
     T is the absolute temperature, and 
     q is the charge of an electron. 
     Now, A and I o1  are calculated below: 
     By selecting the collector current of the transistor Q 7  to be sufficiently larger than the base current of the output stage transistors Q 10  and Q 11 , the mean collector current i c8  of the transistor Q 8  is made substantially equal to the collector current of the transistor Q 7 . By selecting the current flow through resistor R 2  to be sufficiently larger than the base current of the driving transistor Q 8 , the mean collector current i c2  necessitated for the transistor Q 2  is given by the following equation (4): 
     
         i.sub.C2 ≈(1/R.sub.2) (V.sub.BE8 +R.sub.5 ·i.sub.c7) (4), 
    
     where: 
     V BE8  is base-emitter forward voltage of the driving transistor Q 8 , and 
     i c7  is the mean value of the collector current of the transistor Q 7 . 
     The current i c7  is given by the following equation (5): ##EQU3## where: I C4  is the collector current of the transistor Q 4 . 
     R 3  and R 4  are resistances of the resistors of the same respective designations. 
     V BE4  is a base-emitter forward voltage of the transistor Q 4 . 
     Hereinafter in the circuit of FIG. 1, collector current represented by a mark i cj  is the mean value of pulsating collector current of a transistor marked Q j , and the collector current represented by the mark i Ck  is the DC collector current of a transistor marked Q k . And I o1  is given by the following equation (6): ##EQU4## where: R 1 , R 3  and R 4  are resistances of the resistors of the same designations, and 
     V BE2 , V BE3  and V BE4  are base-emitter forward voltages of the transistors Q 2 , Q 3  and Q 4 , respectively. 
     Since the mean collector current i C1  is given by 
     
         i.sub.C1 ≈I.sub.o1 -i.sub.C2                       ( 7), 
    
     the mean collector current i C2  is derived as follows from the equations (4) and (5): ##EQU5## and therefore, further from the equation (7), ##EQU6## 
     As is observed from the equations (2), (3), (6), (8) and (9), the apparatus of the prior art of FIG. 1 has a large number of components which have relevancy to the voltage gain G v  and therefore the spread of the electric values such as resistances, current amplification factors, etc., due to temperature change greatly influences the voltage gain G v . Therefore, for example, the voltage gain decreases as a result of the spread of the constants of the components, and, further, the amplitude of the vertical deflection voltage changes considerably with temperature, thereby the height of the image shrinks. If a strong negative AC feed back is applied to the circuit by selecting the voltage gain to be very high, the height change of the image due to temperature change is small, but undesirable high frequency oscillation is likely to occur; accordingly, the voltage gain G v  is necessary to have desired value in spite of the existence of spreads of values of components. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention provides a novel B-class complementary circuit of direct-coupling type having good characteristics of narrow spread of voltage gain and low temperature dependency. The apparatus of the present invention provides the above-mentioned excellent characteristics by utilizing several current-mirror circuits in a direct coupled circuit which comprises 
     an output stage driving circuit, 
     a B-class complementary connected output stage, and 
     a bias-stabilization circuit, constituted as a differential amplifier working as a predrive stage for driving the output stage driving circuit; and 
     by utilizing further current-mirror circuits for constant current feeding to a load circuit of the driving circuit and for the bias stabilizing circuit. 
    
    
     BRIEF EXPLANATION OF THE DRAWING 
     FIG. 1 is a circuit diagram of a conventional B-class complementary circuit. 
     FIG. 2 is a graph showing operation of the conventional circuit of FIG. 1. 
     FIG. 3 is a circuit diagram of an example embodying the present invention. 
     FIG. 4 is another example embodying the present invention. 
     FIG. 5 is another example embodying the present invention. 
     FIG. 6 is a circuit diagram of another circuit of the current-mirror circuits of FIGS. 3 to 5, 
     FIG. 7 is a circuit diagram of another circuit of the current-mirror circuit of FIG. 3 to 5. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     Apparatus of the B-class complementary circuit in accordance with the present invention comprises a B-class complementary circuit output stage, a driving stage for driving said output stage and having a constant-current load circuit and a predriving circuit including a differential amplifier. The present invention is characterized in that, the differential amplifier is connected to a reference voltage means by its first input terminal, to a sawtooth-wave voltage signal generator by its second input terminal and to an input end of the driving stage of current-mirror connection by its output terminal. 
     The differential amplifier is fed with a constant current from a first current-mirror circuit controlled by a stabilized voltage source, and the constant-current load circuit is connected, through at least one stage of other current-mirror circuits, to a second current-mirror circuit which has the same construction as the first current-mirror circuit. 
     FIG. 3 shows a preferred example embodying the present invention. In FIG. 3, vertical oscillator 1 oscillates a signal having the frequency of vertical scanning. A sawtooth-wave generator 2 generates sawtooth-wave voltage signals necessary for vertical scanning, based on the input signal from the vertical oscillator 1. The sawtooth-wave voltage signal is applied through a capacitor C 1  to the base of the transistor Q 1  of a differential amplifier formed by the transistor Q 1  and another transistor Q 2 . The transistor Q 2  receives a reference voltage produced by a voltage divider formed by resistors R 13  and R 14  and a voltage-compensation diode D 4  at its base. An emitter-grounded primary transistor Q 12  and an emitter-grounded secondary transistor Q 14 , together with an auxiliary transistor Q 13 , form a first current-mirror circuit. The auxiliary transistor Q 13  is collector-grounded and is connected by its emitter commonly to the bases of the transistors Q 12  and Q 14  and by its base to the collector of the primary transistor Q 12 . Accordingly, the collector currents of the primary and secondary transistors Q 12  and Q 14  are maintained equal by the mirror function and maintained constant by means of the stabilized voltage source 3. Therefore, the differential amplifier formed by the transistors Q 1  and Q 2  receives constant-controlled current through the transistor Q 14 . At the same time, the transistors Q 12  and Q 15  together with Q 13  form another current-mirror circuit which maintains the collector current of the transistor Q 15  constant. The collector of the transistor Q 15  is connected to the collector of another current-mirror circuit consisting of the transistors Q 16 , Q 18  and Q 17 , and therefore the collector current of the transistor Q 18  is controlled constant. The collector of the transistor Q 18  is further connected to the collector of a transistor Q 5  of another current-mirror circuit formed by the transistors Q 5  and Q 7  together with Q 6 . Therefore, the collector current of the transistor Q 7  is constant and equal to that of the transistor Q 12 . 
     The collector of the transistor Q 2  is connected to the collector of the transistor Q 19 , which forms a current-mirror circuit with the transistor Q 21  (and counter part transistor formed with Q 22 , the same emitter-area as Q 21 ), together with auxiliary transistor Q 20 . The transistors Q 21  and Q 22  are parallel connected and are driving stage for the complementary connected output stage transistors Q 10  and Q 11 . A transistor Q 9  is an inverter transistor of the complementary connection Q 10  -Q 11 . The transistor Q 7  serves as a load for the driving stage transistors Q 21  and Q 22 . The load L of the output stage is connected through a capacitor C 2  and a resistor R 10  to the ground. The voltage obtained across the resistor R 10  is fed back to the sawtooth generator 2 to improve linearity of the sawtooth output wave. The potential obtained at the junction point F between the load L and the capacitor C 2  is smoothed by a low-pass filter formed by a resistor R 7  and a capacitor C 3 , and divided by a dividing circuit of R 7  and R 8  and through a resistor R 9  is given to the base A of the differential amplifier as a mean level of the sawtooth-wave input signal. 
     In summary, the features of the circuit of FIG. 3 is as follows: 
     The mean collector current of the transistor Q 7  and mean collector current of the transistors Q 21  and Q 22  are controlled by the collector current I C12  of the transistor Q 12 , which is fed through several current-mirror circuits, and collector current I C12  is maintained constant by means of the stabilized voltage source 3. Therefore, both constant equilization of the mean collector currents of transistor Q 1  and Q 2 , and designing the transfer conductance of the differential amplifier Q 1  and Q 2  at the optimum point become possible. In order to obtain a large transfer admittance g m2  of the differential amplifier Q 1  -Q 2  and a small change in the voltage gain G v , a ratio between a first total multiplying factor of the current-mirror circuits, (which is from the second current-mirror circuit Q 12  +Q 13  +Q 15  to the constant current load circuit Q 7 ), and a second total multiplying factor of the other current-mirror circuits (which is from the first current-mirror circuit Q 12  +Q 13  +Q 15  to the driving stage Q 19  +Q 20  +Q 21  +Q 22 ), should be preferably 1:2 or a number around it. Therefore, two parallel connected transistors Q 21  and Q 22  are used as the output stage. 
     Besides, by use of the current-mirror circuit for the driving stage transistors Q 21  and Q 22 , the scattering and temperature dependency of the voltage gain of the circuit is minimized. Therefore, the undesirable shrinkage of the image hitherto observed due to distortion of sawtooth-wave form at source voltage changes can be eliminated. 
     The detailed operation is as follows: 
     Since, as a result of current mirror circuit chain the mean collector current i c7  of the transistor Q 7  is equal to the mean collector currents I C18 , I C15 , I C14  and I C12  respectively of the transistors Q 18 , Q 15 , Q 14  and Q 12 , the following equation (10) holds: ##EQU7## where: V S  is stabilized output voltage of the stabilized voltage source 3, 
     V BE13  and V BE12  are base-emitter forward voltage of the transistors Q 13  and Q 12 , respectively, 
     R 11  is resistance of the resistor R 11 . 
     Hereinafter in the circuit of FIG. 3, collector current represented by a mark &#34;i cj  &#34; is the mean value of pulsating collector current of a transistor marked &#34;Q j  &#34;, and the collector current represented by the mark &#34;I ck  &#34; is the DC collector current of a transistor marked &#34;Q k  &#34;. 
     On the other hand, since the collector of the transistors Q 7  is connected to those of the transistors Q 21  and Q 22 , the following equation (11) holds: 
     
         i.sub.C7 =i.sub.C21 +i.sub.C22 =2i.sub.C21                 (11). 
    
     By means of mirror circuit of the transistors Q 21  and Q 19  the following equation (12) holds: 
     
         i.sub.C21 =i.sub.C19 =i.sub.C2                             (12), 
    
     and accordingly, from the equations (10), (11) and (12), 
     
         i.sub.C2 =i.sub.C21 =1/2I.sub.C14                          (13), 
    
     where i c21 , ic22, i c19  and i c2  are mean value of collector currents of the transistors Q 21 , Q 22 , Q 19  and Q 2 , respectively. 
     The equation (13) implies that the mean collector currents i c1  and i c2  of each of the transistors Q 1  and Q 2  of the differential amplifier are half of the constant current I C14  given by the constant current transistor Q 14 , regardless of scattering of the circuit component and temperature dependency, and therefore the transfer conductance g m2  becomes the optimum value attainable for a predetermined constant current of the constant current means Q 14 . 
     On the other hand, the voltage gain G V  and transfer conductance g m2  of the differential amplifier is represented by the following equations: (14) and (15): ##EQU8## where: h FEO  is DC current amplification factor of transistors of output stage Q 10 , Q 11 , 
     R 07  is output impedance of transistor Q 7 , 
     R L  is impedance of load L, 
     R iO  is input impedance of output stage transistors Q 10  and Q 11 , 
     k is Boltzman&#39;s constant, 
     T is absolute temperature, 
     q is charge of electron, 
     I C12  is collector current of transistor Q 12 , 
     V S  is output voltage of stabilized voltage source 3, 
     V BE12 , V BE13  are base-emitter forward voltages of transistors Q 12 , Q 13 , respectively. 
     By comparing the equation (14) to the equation (2), as is elucidated in detail below, it is observed that the equation (14) for the circuit of FIG. 3 has less elements to influence the voltage gain G V , than that of the equation (2) for FIG. 1 and accordingly, voltage gain deviation due to deviations of the characteristics of the components of the circuit is smaller in FIG. 3 than in FIG. 1. 
     Also, by comparing the equation (14) to the equation (2), as is elucidated in detail below, it is observed that the equation (14) for the circuit of FIG. 3 has less temperature dependency of the voltage gain G V  than that of the equation (2) for FIG. 1. 
     Firstly, the degree of deviation of both equations (14) and (2) are examined. For the simplicity, we can withdraw the terms of ##EQU9## from the consideration, since these are common in both equations (14) and (2). 
     First, with respect to the circuit of FIG. 1, let us provide that the circuit constants are as follows: 
     R 1  =15KΩ, 
     R 2  =5.6KΩ, 
     R 3  =7.5KΩ, 
     R 4  =1.8kΩ, 
     R 5  =200Ω, 
     V S  =6.2V, 
     V BFn  =0.7 V, 
     and that variations of absolute values of the resistances are 20%, 
     and that variations of relative values of the resistances are 5%, 
     and h FE  of transistors vary within 50-200, then the variations become as follows: 
     I 01  varies bout ±22%, 
     A varies about ±15%, 
     hence 
     g ml  varies about ±37%, ##EQU10##  varies about ±19%, accordingly the total of variation excluding the effect of the term of ##EQU11## is about ±56%. 
     However, in the circuit of FIG. 3, the only variation noticeable is that of I 02 , which is based on the variation of the resistance of the resistor R 11 , and this scattering is about ±20%. Therefore, the spread of voltage gain G v  of FIG. 3 embodying the present invention is reduced by 36% in comparison to that of the conventional circuit of FIG. 1. 
     Secondly, distortion of the output stage Q 10 , Q 11 , with respect to change of the power source voltage V cc  is examined. In the circuit of FIG. 3 embodying the present invention, the distortion is eliminated by impressing a voltage which is substantially proportional to the power source voltage V cc  on the base of the transistor Q 2 . The advantage of the circuit of FIG. 3 is that, even when the base voltage of the transistor Q 2  varies in response to a change of the power source voltage V cc , mean collector currents of the transistors Q 1 ,Q 2 , Q 21 , Q 22  and Q 7  do not change, and thus a stable current of the driving stage Q 21 ,Q 22  is obtainable. Even when a pulsating component is included in the power source V cc , such pulsating component can be smoothed by connecting a capacitor C x  as shown by the dotted line in FIG. 3, therefore no undesirable effects are caused by the pulsating component. 
     In FIG. 3, a diode D 4  is connected for compensation of voltage differences between the saturation voltage of the higher side (i.e. power source voltage side=higher voltage side) and the low side saturation voltage of the output stage. The high side saturation voltage is the sum of collector-emitter saturation voltage of the transistor Q 7  and the base-emitter forward voltage of the transistor Q 10 . The lowside (i.e. ground side=lower voltage side) saturation voltage is the collector-emitter saturation voltage of the transistor Q 11 . The high side saturation voltage is larger by almost one diode voltage, and hence, to compensate for this voltage difference the diode D 4  is inserted. If the output stage transistors Q 10  and Q 11  were of known Darlington connection, two diode in series should be inserted in place of D 4 . 
     Another example is shown in FIG. 4. In this example, almost parts are the same as those of FIG. 3, but in place of the transistors Q 16  and Q 17  of FIG. 3, a diode D 6  is used, and in place of the transistors Q 19  and Q 20  of FIG. 3 a diode D 5  is used, but the same current-mirror circuit functions are obtainable as is known in the art of current-mirror circuits. 
     Another example is shown in FIG. 5, wherein almost parts are the same as those of FIG. 3, but in place of the transistor Q 18  of FIG. 3 parallel connected pair of transistors Q 23  and Q 24  is used, thereby doubling the total multiplying factor of the current-mirror circuit of Q 16  in comparison with the circuit of FIG. 3. Furthermore, of the current-mirror circuit of the transistor Q 19  to Q 22  of FIG. 3, two transistors Q 21  and Q 22  are replaced by four transistors Q 25 , Q 26 , Q 27  and Q 28 , thereby the total multiplying factor of the current-mirror circuit is doubled from 1:2 of FIG. 3 to 1:4 of FIG. 5. Thus, multiplying factors of the first series of current-mirror circuits from the transistor Q 12  through the transistor Q 15  to the transistor Q 7  and of the second series of current-mirror circuits from the transistor Q 12  through the transistor Q 14  to the transistor Q 28  are doubled. Therefore, the ratio between the total multiplying factors of the first series of the current-mirror circuit and the second series of the current-mirror circuits is still 1:2, which is the same as that of the examples of FIGS. 3 and 4. 
     As a result of the above-mentioned improvements the voltage gain G v  is doubled in comparison with that of equation (14) as shown by the following equation (16): ##EQU12## The operation characteristics are the same as those of FIG. 3. 
     In the examples of FIG. 3, FIG. 4 and FIG. 5, the amount of the output current of a particular current-mirror circuit is determined by the number of transistors and diodes, and by making the emitter junction area of the transistors or the p-n junction area of the diode equal to the input transistor. However, another method of determining the amount of the output current of the current-mirror circuit is illustrated in the circuit of FIG. 6 and/or FIG. 7, where resistors R A  and R B  of selected resistances are inserted in series to the emitters of the primary and secondary transistors, or input and output terminals, thereby any desired amount of output current is obtainable. The smoothing capacitance C 3  can be omitted when the capacitor of the output coupling capacitor C 2  is large (and hence pulsating voltage component appearing at the point F is small, the capacitance of the input coupling capacitor C is large and the AC output impedance of the sawtooth voltage generator is small.