Abstract:
A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.

Description:
FIELD OF THE INVENTION 
     The present invention relates to phase-locked loops (PLLs) generally and, more particularly, to a charge pump that may be used in a PLL. 
     BACKGROUND OF THE INVENTION 
     Phase-locked loop (PLL) based clock recovery systems often employ charge pumps as internal circuitry. A low static phase offset in the PLL leads to longer possible transmission lengths due to the more ideal sampling point of the incoming data. 
     Referring to FIG. 1, a circuit  10  illustrating a typical charge pump is shown. The circuit  10  receives a signal PUMPUP and PUMPDN, which can be divided into pairs of signals PUMPUPP and PUMPUPN, and PUMPDND and PUMPDNN, respectively. The non-filter drain of the current steering differential pairs is tied to a fixed voltage (i.e., VMID) which is most likely different from the other drain of the differential pair (i.e., FILTU and FILTD). When the signal PUMPUP and the signal PUMPDN transition, the sources of the differential pairs (i.e., NSRC_P_U, NSRC_N_U, NSRC_P_D, and NSRC_N_D) move from one voltage to another, based upon the difference between the signals FILTU and FILTD and the signal VMID. The greater the difference between the signals FILTU/FILTD and the signal VMID, the more the source nodes move. The net result is a mismatch between the signal FILTU_PUMP and the signal FILTD_PUMP. The common mode correction circuit (i.e., the transistors connected to the signals CM_PBIAS and CM_BIAS) may cancel some not all the mismatch. The rest of the mismatch results in static phase offset. 
     Another disadvantage with the circuit  10  is the lack of cascoded current sources. Due to the low output impedance of a single device, noticeable current variations can occur with changes in the signals FILTU and FILTD. This can also result in static phase offset. The use of the signal VMID on the gate of one side of the differential pair reduces the operating frequency of the pump, which becomes significant at lower voltages. Using differential switching increases the operating frequency of the device, or allows the same operating frequency at lower operating voltages. In addition, two common mode signals are needed (i.e., CM 13  PBIAS and CM_NBIAS). This increases the complexity of the common mode control circuit. 
     Referring to FIG. 2, a circuit  50  is shown illustrating another conventional buffering method. The circuit  50  comprises a voltage source  52 , a voltage source  54 , a switch S 1 , a switch S 2 , a switch S 3 , a switch S 4  and a comparator  56 . The circuit  50  is a single-ended system, which is more sensitive to voltage supply noise and has a smaller dynamic range of operation when compared with the circuit of FIG.  1 . The smaller dynamic range of operation requires a voltage controlled oscillator (VCO) to have a higher gain, which in turn increases the noise sensitivity. 
     SUMMARY OF THE INVENTION 
     The present invention concerns a circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs. 
     The objects, features and advantages of the present invention include a charge pump that may be used in a phase-locked loop that may provide (i) reduced static phase offset,(ii) fewer noise sources, (iii) an increased operating frequency that may compensate for lower supply voltages, (iv) lower voltage operation, and (v) may be implemented using a smaller die area. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which: 
     FIG. 1 is a circuit diagram of a conventional charge pump; 
     FIG. 2 is a circuit diagram of a conventional buffering scheme; 
     FIG. 3 is a block diagram of a preferred embodiment of the present invention; 
     FIG. 4 is a circuit diagram of an example of the charge pump of FIG. 3; 
     FIG. 5 is a circuit diagram of an example of the unity gain buffer of FIG. 3; and 
     FIG. 6 is a circuit diagram of an example of the common mode control circuit of FIG.  3 . 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 3, a block diagram of a circuit  100  is shown in accordance with a preferred embodiment of the present invention. The circuit  100  generally comprises a phase detector block (or circuit)  102 , a common mode control block (or circuit)  104 , a charge pump block (or circuit)  106 , a voltage controlled oscillator (VCO) block (or circuit)  108  and a loop filter block (or circuit)  110 . The phase detector  102  generally comprises an input  112  that may receive a data signal (e.g., CLOCK/DATA), an input  114  that may receive a clock signal (e.g., VCO_CLK) from the VCO block  108 , an output  116  that may present a first control signal (e.g., PUMPUP) and an output  118  that may present a second control signal (e.g., PUMPDN). The charge pump  106  generally comprises an input  120  that may receive the signal PUMPUP, an input  122  that may receive the signal PUMPDN, an output  124  that may present a control signal (e.g., FILTU) and an output  126  that may present a control signal (e.g., FILTD). The charge pump  106  may also comprise a number of input  128   a - 128   n  that may receive a number of bias signals. For example, the input  128   a  may receive a bias signal (e.g., CM 13  PBIAS) that may be generated by the common mode control block  104 . The input  128   b  may receive a bias signal (e.g., PBIAS), the input  128   c  may receive a bias signal (e.g., PBIASC), the input  128   d  may receive a bias signal (e.g., NBIASC) and the input  128   n  may receive a bias signal (e.g., NBIAS). 
     The common mode control block  104  generally comprises an output  130  that may present the signal CM_PBIAS, an input  132  that may receive the signal NBIAS, an input  134  that may receive the signal FILTU and an input  136  that may receive the signal FILTD. The voltage controlled oscillator block  106  generally comprises an input  138  that may receive the signal FILTU, an input  140  that may receive the signal FILTD and an output  142  that may present the signal VCO_CLK. The loop filter block  110  generally comprises an input/output  144  that may be connected to the output  124  of the charge pump  106  and an input/output  146  that may be connected to the output  126  of the charge pump  106 . 
     The signals NBIAS, PBIAS, NBIASC and PBIASC may be generated by an external circuit, such as an analog bias circuit. 
     The signal CM_PBIAS may be a common mode bias signal that may be presented to the charge pump  106 . The loop filter  108  may comprise a number of resistors and/or capacitors. 
     Referring to FIG. 4, a more detailed diagram of the charge pump circuit  106  is shown. The charge pump circuit  106  generally comprises a first differential element  160  and a second differential element  162 . The first differential element  160  generally presents the signal FILTU at the output  124 , while the second differential element  162  generally presents the signal FILTD at the output  126 . The first differential element  160  generally comprises a transistor  164   a,  a transistor  166   a,  a transistor  168   a,  a transistor  170   a,  a transistor  172   a,  a transistor  174   a,  a transistor  176   a,  a transistor  178   a,  a transistor  180   a  and a unity gain buffer circuit  200   a.  The transistors  170   a  and  180   a  generally form a differential pair  171   a.  The transistors  172   a  and  178   a  generally form a differential pair  173   a.  The transistors  170   b  and  180   b  generally form a differential pair  171   b.  The transistors  172   b  and  178   b  generally form a differential pair  173   b.    
     The unity gain buffer circuit  200   a  has an input  202   a  and an output  204   a  and will be described in more detail in connection with FIG.  5 . The transistor  164   a  generally comprises a gate that may receive the signal PBIAS. The transistor  166   a  generally has a gate that may receive the signal CM_PBIAS. The transistor  168   a  generally has a gate that may receive the signal PBIASC. The transistor  170   a  may have a gate that may receive the signal PUMPUPN. The transistor  172   a  generally comprises a gate that may receive the signal PUMPDNP. The transistor  174   a  generally comprises a gate that may receive the signal NBIASC. The transistor  176   a  generally comprises a gate that may receive the signal NBIAS. The transistor  178   a  generally comprises a gate that may receive the signal PUMPDNN. The transistor  180   a  generally comprises a gate that may receive the signal PUMPUPP. The signal PUMPUPN and PUMPUPP generally comprise a differential input that may be presented to the transistors  170   a  and  180   a,  respectively, of the differential pair  171   a.  Similarly, the signals PUMPDNP and PUMPDNN generally comprise a differential input that is presented to the transistors  172   a  and  178   a,  respectively, of the differential pair  173   a.    
     The differential element  162 , generally comprises a transistor  164   b,    166   b,    168   b,    170   b,    172   b,    174   b,    176   b,    178   b,    180   b  and a unity gain buffer  200   b.  The transistors  164   b - 180   b  and the unity gain buffer  200   b  have similar connections to the transistors  164   a - 180   a  and the unity gain buffer  200   a  of the differential element  160 . However, the transistor  170   b  generally receives the signal PUMPDNN, the transistor  172   b  generally receives the signal PUMPUPP, the transistor  178   b  generally receives the signal PUMPUPN and the transistor  180   b  generally receives the signal PUMPDNP. 
     The unity gain buffers  200   a  and  200   b  generally force the drains at both sides of the individual differential transistor pairs (e.g.,  173   a  or  173   b ) to be equal. This generally minimizes the switching transients on the source nodes of the differential pairs (e.g., the pairs  171   a,    171   b ,  173   a  and  173   b ) that may be created when the signals PUMPUP and PUMPDN transition from one side to the other. This may lead to a mismatch between the signal FILTU and the signal FILTD, which may result in lower static phase offset. To compensate, the cascoded current sources may increase the output impedance of the current sources (e.g., the transistors  168   a  and  168   b ), which may reduce variation in current due to differences in the signals FILTU and FILTD, which may, in turn, reduce the static phase offset. The simplified common mode biasing may result in smaller die area and fewer noise sources. Driving the differential pairs (e.g., the pairs  171   a,    171   b ,  173   a  and  173   b ) with differential signals increases the operating frequency of the device, compensating for performance loss at lower voltage operation (e.g., 3.3V or less). 
     Referring to FIG. 5, a circuit diagram of the unity gain buffer  200   a  is shown. The unity gain buffer  200   b  may have similar connections. The unity gain buffer  200   a  generally comprises a transistor  210 , a transistor  212 , a transistor  214 , a transistor  216 , a transistor  218 , a transistor  220 , a transistor  222 , a transistor  224  and a transistor  226 . The transistors  210  and  212  generally receive the signal PBIAS. The transistors  214  and  220  generally receive the signal PBIASC. The transistor  216  generally receives the signal FILTU. The gate of the transistor  222  as well as the drain of the transistors  220  and  224  generally present the signal OUT at the output  204   a.  The transistor  218  is generally connected between the transistor  214  and ground. The transistor  224  is generally coupled between the transistor  220  and ground. The transistor  226  is generally coupled between the sources of the transistors  216  and  222  and ground. While the circuit  200  shows one example of a unity gain buffer, other buffers that provide similar functioning (e.g., providing a uniform voltage) may be used accordingly to meet the design criteria of a particular implementation. 
     Referring to FIG. 6, a more detailed diagram of the common mode circuit  104  is shown. The common mode circuit  104  generally comprises a transistor  250 , a transistor  252 , a transistor  254 , a transistor  256 , a transistor  258 , a transistor  260 , a transistor  262  and a transistor  264 . The transistor  254  may receive the signal FILTU and the transistor  260  may receive the signal FILTD. The gates of the transistors  256  and  258  may receive the signal CM_VREF. The transistors  262  and  264  may receive the signal NBIAS. The drains of the transistors  256  and  258  as well as the drain and gate of the transistor  252  may present the signal CM_PBIAS. The transistor  250  may be coupled between a supply voltage and the drains of the transistors  254  and  260 . The transistor  252  may be connected between the supply voltage and the drains of the transistors  256  and  258 . The transistors  262  and  264  may be connected between ground and the sources of the transistors  254  and  256  and the sources of the transistors  258  and  260 , respectively. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.