Abstract:
The self-bias adjustment circuit is provided on the previous stage of an internal circuit. This self-bias adjustment circuit adjusts a bias of an input signal and supplies an appropriate signal to the internal circuit. The self-bias adjustment circuit includes a detection circuit  11   a  that detects the bias voltage of the input signal, and a superposing circuit  11   b  that superposes a correction voltage for correcting the bias voltage to a predetermined value on the input signal on the basis of the bias voltage detected by the detection circuit. The result signal is supplied to the internal circuit.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a self-bias adjustment circuit, arranged on a previous stage of an internal circuit, for supplying an appropriate signal to an internal circuit.  
         BACKGROUND OF THE INVENTION  
         [0002]    As a conventional self-bias adjustment circuit, for example, a self-bias adjustment circuit disclosed in a reference “Design Considerations for Very-High-Speed Si-Bipolar IC&#39;s Operating up to 50 Gb/s”, H. -M. rein (IEEE Journal of Solid-State Circuits, vol. 31, no. 8, pp. 1076-1090, August 1996). FIG. 6 is a schematic diagram showing the configuration of an integrated circuit including the conventional self-bias adjustment circuit. This integrated circuit  82  comprises an input terminal  87  which receives a signal current I 80  from an output circuit  84  of another integrated circuit  81  through a signal transmission line  86 , a terminal resistor  88  (resistance RS 80 ) arranged between a high-potential side  82   a  of the power supply of the integrated circuit  82  and the input terminal  87 , and an internal circuit  89 .  
           [0003]    A potential difference VGAP 80  is generated across the low-potential side  81   b  of the power supply of the another integrated circuit  81  and a low-potential side  82   b  of the power supply of the integrated circuit  82 . The output circuit  84  of the another integrated circuit  81  has a signal current source  85  to output the signal current I 80  from the signal current source  85  to the signal transmission line  86 . The terminal resistor  88  constitutes a self-bias adjustment circuit  91 . The power supply voltage of the integrated circuit  81  and the power supply voltage of the integrated circuit  82  are equal to each other. More specifically, equation (1) is established:  
           ( VCC 81− VEE 81)=( VCC 82− VEE 82)  (1)  
           [0004]    In this equation, VCC 81  denotes the voltage of a high-potential voltage side  81   a  of the power supply of the integrated circuit  81 , VEE 81  denotes the voltage of the low-potential side  81   b  of the power supply of the integrated circuit  81 , VCC 82  denotes the voltage of the high-potential side  82   a  of the power supply of the integrated circuit  82 , and VEE 82  denotes the voltage of the low-potential side  82   b  of the power supply of the integrated circuit  82 . The internal circuit  89  may be an internal circuit having a single-phase output or an internal circuit having a differential output. The output impedance of the output circuit  84  is equal to the impedance of the signal transmission line  86 . The impedance of the terminal resistor  88  is equal to the impedance of the signal transmission line  86 . The internal circuit  89  has a high-input impedance of several kΩ or more.  
           [0005]    The signal current I 80  output from the output circuit  84  is flowed into the high-potential side  82   a  of the power supply of the integrated circuit  82  through the input terminal  87  and the terminal resistor  88 . If a potential difference VGAP 80  is 0 volt, a DC voltage VDC 80  across the input terminal  87  and an input terminal  90  can be expressed by equation (2). A signal amplitude (amplitude of signal voltage) VAC 80  between the input terminals  87  and  90  can be expressed by equation (3).  
             VDC 80= VCC 82−( I 80× RS 80)/2  (2)  
             VAC 80= I 80× RS 80  (3)  
           [0006]    When bias design for the internal circuit  89  is performed in accordance with signal voltages expressed by equation (2) and equation (3), the internal circuit  89  can be normally operated. In this manner, a self-bias adjustment circuit can be constituted by a simple circuit obtained by the terminal resistor  88  having the function of impedance matching and the function of terminating.  
           [0007]    The integrated circuit  81  and the integrated circuit  82  are not necessarily mounted on the same substrate or in the same housing. In addition, even though the integrated circuit  81  and the integrated circuit  82  are mounted on the same substrate, voltage drop caused by a pattern resistor may occur because a pattern is drawn on the substrate. For this reason, the potential difference VGAP 80  may not be 0 volt. The DC voltage VDC 80  and the signal amplitude VAC 80  can be expressed by equations (4) and (5), respectively, using the voltage VEE 82 :  
             VDC80   =                VCC82   -       (     I80   ×   RS80     )     /   2     +   VGAP80             (   4   )                     VAC80   =                (     VCC82   -     (       (     VCC82   -       (     I80   ×   RS80     )     /   2       )     +                                      VGAP80   )     )     ×   2                   =                  (       (     I80   ×   RS80     )     /   2     )     -   VGAP80       )     ×   2               =                  (     I80   ×   RS80     )     -     2      VGAP80                     (   5   )                               
 
           [0008]    According to equation (4), the DC voltage VDC 80  across the input terminals  87  and  90  is shifted from a design value at which the internal circuit  89  can be normally operated by volts corresponding to the potential difference VGAP 80 .  
           [0009]    According to equation (5), the signal amplitude VAC 80  across the input terminals  87  and  90  is shifted from a design value by (−2×VGAP 80 ) volts.  
           [0010]    As a conventional self-bias adjustment circuit for avoiding a signal voltage from being shifted by the potential difference VGAP 80 , a self-bias adjustment circuit in which a capacitor is inserted on a signal line for transmitting an input signal, a signal component passes through the capacitor, and a DC voltage expressed by equation (2) is superposed on the signal component is known. In this self-bias adjustment circuit, the influence of the potential difference VGAP 80  is suppressed by the capacitor inserted on the signal line.  
           [0011]    However, according to the above-described conventional self-bias adjustment circuit (Design Considerations for Very-High-Speed Si-Bipolar IC&#39;s Operating up to 50 Gb/s″), since the self-bias adjustment circuit has no function of suppressing the influence of the potential difference VGAP 80 , a shift between a bias voltage and a signal amplitude at the input terminal  90  of the internal circuit  89  is generated, and the internal circuit  89  may not be appropriately operated. In addition, the signal amplitude is disadvantageously deteriorated.  
           [0012]    According to the conventional self-bias adjustment circuit having the capacitor, since a capacitor is inserted on a signal line for transmitting an input signal, when the input signal has a frequency component of a wide band, the low-frequency component of the input signal is attenuated, and the input signal is disadvantageously degraded. When the capacitance of the capacitor is set large (e.g., 1 nF or more) to pass the signal components of the wide band, the capacitor increases in size. For this reason, the capacitor is not easily formed in the integrated circuit, and the capacitor must be formed out of the integrated circuit. Therefore, peripheral devices increases in size, and the cost disadvantageously increase.  
         SUMMARY OF THE INVENTION  
         [0013]    It is an object of this invention to obtain a self-bias adjustment circuit which can appropriately operate the internal circuit while suppressing the size and cost of the device from being increased and which can reduce a deterioration of a signal amplitude.  
           [0014]    In the self-bias adjustment circuit according to the present invention, a detection unit detects the bias voltage of the input signal, and a superposing unit superposes the correction voltage for correcting the bias voltage to the predetermined voltage on the input signal to output the signal to the internal circuit.  
           [0015]    Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]    [0016]FIG. 1 is a diagram showing the schematic configuration of an integrated circuit according to a first embodiment of the present invention.  
         [0017]    [0017]FIG. 2 is a diagram showing the schematic configuration of the detection circuit and the superposing circuit shown in FIG. 1.  
         [0018]    [0018]FIG. 3 is a diagram showing the schematic configuration of the DC current output circuit shown in FIG. 2.  
         [0019]    [0019]FIG. 4 is a diagram showing the schematic configuration of an integrated circuit according to a second embodiment of the present invention.  
         [0020]    [0020]FIG. 5 is a diagram showing the schematic configuration of the DC current output circuit shown in FIG. 4.  
         [0021]    [0021]FIG. 6 is a diagram showing the configuration of an integrated circuit including a conventional self-bias adjustment circuit. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments.  
         [0023]    [0023]FIG. 1 is a diagram showing the schematic configuration of an integrated circuit according to a first embodiment of the present invention. This integrated circuit  2  comprises the input terminal  7  which receives a signal from the output circuit  4  of another integrated circuit  1  through the signal transmission line  6 , the terminal resistance  8  (resistance RS 1 ) arranged between a high-potential side  2   a  of the power supply of the integrated circuit  2  and the input terminal  7 , the input terminal  9 , the detection circuit  11   a  for detecting a bias voltage of an input signal input through the input terminal  7 , and the superposing circuit  11   b , arranged between the input terminal  7  of the integrated circuit  2  and an input terminal  10  of the internal circuit  9 , for superposing a correction voltage for correcting the bias voltage to a predetermined value on the input signal on the basis of a detection result of the detection circuit  11   a.    
         [0024]    A potential difference VGAP 1  is generated between a low-potential side  1   b  of the power supply of the integrated circuit  1  and a low-potential side  2   b  of the power supply of the integrated circuit  2 . The output circuit  4  of the integrated circuit  1  has a signal current source  5  to output the signal current II from the signal current source  5  to the signal transmission line  6 . The terminal resistance  8 , the detection circuit  11   a , and the superposing circuit  11   b  constitute a self-bias adjustment circuit  11 . The power supply voltage of the integrated circuit  1  and the power supply voltage of the integrated circuit  2  are equal to each other. More specifically, equation (6) is established:  
         ( VCC 1− VEE 1)=( VCC 2− VEE 2)  (6)  
         [0025]    In this equation, reference symbol VCC 1  denotes a voltage of a high-potential side  1   a  of the power supply of the integrated circuit  1 , reference symbol VEE 1  denotes a voltage of the low-potential side  1   b  of the power supply of the integrated circuit  1 , reference symbol VCC 2  denotes a voltage of the high-potential side  2   a  of the power supply of the integrated circuit  2 , and reference symbol VEE 2  denotes a voltage of the low-potential side  2   b  of the power supply of the integrated circuit  2 . The internal circuit  9  may have a single-phase output or a differential output. The output impedance of the output circuit  4  is equal to the impedance of the signal transmission line  6 . The impedance of the terminal resistance  8  is equal to the impedance of the signal transmission line  6 . The internal circuit  9  has a high input impedance of several kΩ or more.  
         [0026]    The signal current I 1  output from the output circuit  4  is flowed into the high-potential side  2   a  of the power supply of the integrated circuit  2  through the signal transmission line  6 , the input terminal  7 , and the terminal resistance  8 . If the potential difference VGAP 1  is 0 volt, a DC voltage VDC 1  at the input terminal  7  can be expressed by equation (7). A signal amplitude VAC 1  at the input terminal  7  can be expressed by equation (8).  
           VDC 1= VCC 2−( I 1× RS 1)/2  (7)  
           VAC 1= I 1× RS 1  (8)  
         [0027]    In accordance with the signal voltages expressed by equations (7) and (8), bias design for the internal circuit  9  is performed. However, as in the conventional integrated circuit described above, the potential difference VGAP 1  may not be 0 volt. In this case, with reference to the voltage VEE 2 , the DC voltage VDC 1  and the signal amplitude VAC 1  can be expressed by equations (9) and (10), respectively.  
           VDC 1= VCC 2−( I 1× RS 1)/2+ VGAP 1  (9)  
           VAC 1=( I 1× RS 1)−2 VGAP 1  (10)  
         [0028]    The detection circuit  11   a  has a high input impedance, and detects a bias voltage of an input signal to the input terminal  7 . The superposing circuit  11   b  superposes a correction voltage for correcting the bias voltage to a predetermined value on the input signal on the basis of a detection result of the detection circuit  11   a . More specifically, the superposing circuit  11   b  superposes the voltage of (−VGAP 1 ) volt which is equal to the opposite of the potential difference VGAP 1  on the input signal. In this manner, even though the potential difference VGAP 1  is generated, the bias voltage of the input signal is corrected to make it possible to output a signal having a bias voltage which satisfies equation (7) to the internal circuit  9 , and the internal circuit  9  can be appropriately operated.  
         [0029]    When a voltage is superposed on an input signal, the superposing circuit  11   b  is set at a high input impedance such that the bias voltage of the input signal at the input terminal  7  is prevented from being changed. However, the superposing circuit  11   b  is set at a low input impedance with respect to a high-frequency component to prevent a pass band from being deteriorated. The input impedance of the integrated circuit  2  is determined by the resistance RS 1  of the terminal resistance  8 , impedance matching for the signal transmission line  6  is established, and low-reflective characteristics can be obtained at the input terminal  7 . In this manner, the self-bias adjustment circuit  11  can also be applied to a signal having a high-frequency signal component.  
         [0030]    [0030]FIG. 2 is a diagram showing the schematic configuration of the detection circuit  11   a  and the superposing circuit  11   b  shown in FIG. 1. The detection circuit  11   a  comprises resistors  22  and  23  (resistances R 1  and R 2 ) arranged in series with each other between the input terminal  7  and the low-potential side  2   b  of the power supply. The superposing circuit  11   b  comprises a resistor  21  (resistance RP), a capacitor  24  connected in parallel to the resistor  21 , and a DC current output circuit  25  for outputting a DC current depending on a detection result of the detection circuit  11   a  to a terminal of the resistor  21  on the internal circuit side.  
         [0031]    The detection circuit  11   a  outputs divided voltages divided by the resistors  22  and  23  to the DC current output circuit  25  of the superposing circuit lib as detection results. The DC current output circuit  25  outputs a DC current depending on a detection result of the detection circuit  11   a . The resistances of the resistors  21 ,  22 , and  23  are about several kΩ each. The capacitance of the capacitor  24  is about several hundred nF. The DC current output circuit  25  has a high input impedance of about several kΩ.  
         [0032]    [0032]FIG. 3 is a diagram showing the schematic configuration of the DC current output circuit  25  shown in FIG. 2. The DC current output circuit  25  comprises resistors  31  and  32  (resistances R 3  and R 4 ) one terminals of which are connected to the high-potential side  2   a  of the power supply, a PNP transistor  33  the emitter of which is connected to the other terminal of the resistor  31  and the collector of which is connected to the input terminal  10  of the internal circuit  9 , a PNP transistor  34  the emitter of which is connected to the other terminal of the resistor  32  and the base and collector of which are connected to the base of the PNP transistor  33 , and a resistor  30  (resistance R 5 ) arranged between the collector of the PNP transistor  34  and the detection circuit  11   a . The PNP transistors  33  and  34  have equal sizes and constitute a current mirror circuit.  
         [0033]    Operation of the circuit of the first embodiment will be described below. The detection circuit  11   a  detects the bias voltage of the input signal. More specifically, a divided voltage VC is generated by the resistors  22  and  23 , and the divided voltage VC is output to a current control terminal (one terminal of the resistor  30 ) of the DC current output circuit  25  as a detection result. The divided voltage VC is expressed by equation (11):  
           VC =(( VCC 2−( I 1× RS 1)/2)+ VGAP 1)×( R 2/( R 1 + R 2))  (11)  
         [0034]    The voltage VC increases in accordance with the increase of the potential difference VGAP 1 .  
         [0035]    An output current IP of the DC current output circuit  25  is controlled by the voltage VC of the current control terminal. Base-emitter voltages of the PNP transistors  33  and  34  are represented by VBE 1 , the current IP is expressed by equation (12):  
           IP =(VCC2− VC−VBE 1)/( R 4+ R 5)  (12)  
         [0036]    The current IP increases as the voltage VC decreases, and decreases as the voltage VC increases. The IP is set to be a value which is equal to or smaller than {fraction (1/10)} the signal from the output circuit  4  of the integrated circuit  1 . In this manner, a variation in signal voltage level at the input terminal  7  of the integrated circuit  2  can be neglected. In addition, the current IP is set to be a value which is  10  or more times a draw current of the internal circuit  9 . In this manner, a variation in signal voltage level at the input terminal  10  of the internal circuit  9  can be neglected.  
         [0037]    The current IP output from the DC current output circuit  25  flows in the resistor  21 . In this manner, a DC voltage VP expressed by equation ( 13 ) is superposed on a signal voltage generated at the input terminal  7 :  
           VP=RP×IP   (13)  
         [0038]    The DC current output circuit  25  changes the current IP with the change of the voltage VC to change the DC voltage VP. When the DC current output circuit  25  is set such that VP=(−VGAP 1 ) is satisfied, so that a bias voltage of the input signal can be corrected. The internal circuit  9  the bias of which is designed for a signal voltage obtained when the voltage VGAP 1  is 0 volt can be appropriately operated.  
         [0039]    When the resistor  21  having a high resistance is inserted in the signal line, a pass band of a signal frequency component is deteriorated. For this reason, in order to improve the pass band, the capacitance of the capacitor  24  is set to have a low impedance for a high frequency component.  
         [0040]    In this manner, a low impedance is realized for a high-frequency signal component, and only the DC voltage component can be superposed on the input signal through the resistor  21  without deteriorating the high-frequency signal component.  
         [0041]    As described above, according to the first embodiment, by using the detection circuit  11   a  having a high input impedance and the superposing circuit  11   b  having a high input impedance for a low-frequency component, the bias voltage of the input signal at the input terminal  7  of the integrated circuit  2  can be prevented from varying, and a simple terminal configuration can be realized. In addition, the detection circuit  11   a  detects the bias voltage of the input signal, and the superposing circuit  11   b  superposes the voltage of (−VGAP 1 ) volt which is equal to the opposite of the potential difference VGAP 1  on the input signal on the basis of a detection result of the detection circuit  11   a . For this reason, a defective operation of the internal circuit  9  and the deterioration of a signal amplitude caused by the potential difference VGAP 1  can be prevented. Furthermore, since a capacitor having a large capacity need not be inserted in the signal line, the peripheral circuit can be prevented from being increased, and, in the integrated circuit, for a signal frequency component in a wide band extending from a high frequency to a low frequency, a bias voltage of an input signal can be corrected without deteriorating the signal amplitude.  
         [0042]    In the first embodiment described above, one terminal of the terminal resistance  8  is connected to the high-potential side  2   a  of the power supply. However, one terminal of the terminal resistance  8  may be connected to the low-potential side  2   b  of the power supply or an arbitrary bias voltage terminal in accordance with the terminal conditions of the integrated circuit  2 . In this case, the same effect can be obtained. Furthermore, in the above example, the PNP transistors are used, one terminals of the resistors  31  and  32  of the current mirror current supply are connected to the high-potential side  2   a  of the power supply, and one terminal of the resistor  23  is connected to the low-potential side  2   b  of the power supply. However, depending on the internal circuit configuration of the integrated circuit  2 , NPN transistors may be used in place of the PNP transistors, one terminals of the resistors  31  and  32  of the current mirror current supply may be connected to the low-potential side  2   b  of the power supply, and one terminal of the resistors  23  may be connected to the high-potential side  2   a  of the power supply. In this case, the same effect as described above can be obtained.  
         [0043]    [0043]FIG. 4 is a diagram showing the schematic configuration of an integrated circuit according to a second embodiment of the present invention. This integrated circuit  42  comprises a positive-phase input terminal  47   a  which receives a positive-phase signal from a differential output circuit  44  of another integrated circuit  41  treating a differential signal through a positive-phase signal transmission line  46   a , a negative-phase input terminal  47   b  which receives a negative-phase signal of the differential output circuit  44  through a negative-phase signal transmission line  46   b , terminal resistors  48   a  and  48   b  (resistances RSP and RSN) arranged in series with each other between the positive-phase input terminal  47   a  and the negative-phase input terminal  47   b , a differential internal circuit  49 , and a superposing circuit  51   b , arranged between the positive-phase input terminal  47   a  and the negative-phase input terminal  47   b  of the integrated circuit  42  and a positive-phase input terminal  50   a  and a negative-phase input terminal  50   b  of the differential internal circuit  49 , for superposing a correction voltage for correcting a bias voltage to a predetermined value on a positive-phase input signal and a negative-phase input signal.  
         [0044]    A potential difference VGAP 40  is generated between a low-potential side  41   b  of the power supply of the integrated circuit  41  and a low-potential side  42   b  of the power supply of the integrated circuit  42 . The differential output circuit  44  of the integrated circuit  41  treats a differential signal, outputs a positive-phase signal to the positive-phase signal transmission line  46   a , and outputs a negative-phase signal to the negative-phase signal transmission line  46   b . Terminal resistors  48   a  and  48   b  constitute a detection circuit  51   a  for detecting a bias voltage of an input signal. The detection circuit  51   a  and the superposing circuit  51   b  constitute a self-bias adjustment circuit  51 .  
         [0045]    The power supply voltage of the integrated circuit  41  and the power supply voltage of the integrated circuit  42  are equal to each other. More specifically, equation ( 14 ) is satisfied:  
         ( VCC 41− VEE 41)=( VCC 42− VEE 42)  (14)  
         [0046]    In this equation, reference symbol VCC 41  denotes a voltage of a high-potential side  41   a  of the power supply of the integrated circuit  41 , reference symbol VEE 41  denotes a voltage of the low-potential side  41   b  of the power supply of the integrated circuit  41 , reference symbol VCC 42  denotes a voltage of a high-potential side  42   a  of the power supply of the integrated circuit  42 , and reference symbol VEE 42  denotes a voltage of the low-potential side  42   b  of the power supply of the integrated circuit  42 .  
         [0047]    The superposing circuit  51   b  comprises a resistor  61   a  (resistance RPP) arranged between the positive-phase input terminal  47   a  of the integrated circuit  42  and the positive-phase input terminal  50   a  of the differential internal circuit  49 , a capacitor  64   a  connected in parallel to the resistor  61   a , a DC current output circuit  65   a  for outputting a DC current IPP depending a detection result of the detection circuit  51   a  to the terminal of the resistor  61   a  on the internal circuit side, a resistor  61   b  (resistance RPN) arranged between the negative-phase input terminal  47   b  of the integrated circuit  42  and the negative-phase input terminal  50   b  of the differential internal circuit  49 , a capacitor  64   b  connected in parallel to the resistor  61   b , and a DC current output circuit  65   b  for outputting a DC current IPN depending on a detection result of the detection circuit  51   a . On the basis of the detection result of the detection circuit  51   a , a correction voltage for correcting a bias voltage to a predetermined value on a positive-phase input signal and a negative-phase input signal.  
         [0048]    The resistance of the terminal resistor  48   a  is equal to an impedance value of the positive-phase signal transmission line  46   a . The resistance of the terminal resistor  48   b  is equal to an impedance value of the negative-phasesignaltransmissionline 46   b . The resistors  61   a  and  61   b  have a resistance of about several kΩ each. The capacitors  64   a  and  64   b  have a capacitance of about several hundred nF each. The DC current output circuits  65   a  and  65   b  have a high input impedance of about several kΩ each. The internal circuit  9  has a high input impedance. In this manner, input impedances of the positive-phase input terminal  47   a  and the negative-phase input terminal  47   b  of the integrated circuit  42  are determined by the terminal resistors  48   a  and  48   b , respectively, and impedance matching for the positive-phase signal transmission line  46   a  and the negative-phase signal transmission line  46   b  is established.  
         [0049]    If a signal has a high-frequency component, low-reflective characteristics are obtained at the positive-phase input terminal  47   a  and the negative-phase input terminal  47   b , and high-frequency signal components are not deteriorated by adding the resistors  61   a  and  61   b  and the capacitors  64   a  and  64   b . A state in which a signal current ID from the integrated circuit  41  flows into the negative-phase input terminal  47   b  through the terminal resistors  48   a  and  48   b  and a state in which the signal current ID is drawn from the negative-phase input terminal  47   b  are made, and a differential signal voltage VD expressed by equation (15):  
           VD=ID ×( RSP+RSN )  (15)  
         [0050]    The differential signal voltage VD is not deteriorated by adding the resistors  61   a  and  61   b  and the capacitors  64   a  and  64   b.    
         [0051]    [0051]FIG. 5 is a diagram showing the schematic configuration of the DC current output circuits  65   a  and  65   b  shown in FIG. 4. The DC current output circuits  65   a  and  65   b  are integrally arranged, and comprises resistors  72 ,  73 , and  74  (resistances R 11 , R 12 , and R 13 ) one terminals of which are connected to the high-potential side  42   a  of the power supply, a PNP transistor  75  the emitter of which is connected to the other terminal of the resistor  72  and the collector of which is connected to the positive-phase input terminal  50   a  of the differential internal circuit  49 , a PNP transistor  77  the emitter of which is connected to the other terminal of the resistor  74  and the collector of which is connected to the negative-phase input terminal  50   b  of the differential internal circuit  49 , a PNP transistor  76  the emitter of which is connected to the other terminal of the resistor  73  and the base and collector of which are connected to the bases of the PNP transistors  75  and  77 , and a resistor  71  (resistance R 10 ) arranged between the collector of the PNP transistor  76  and a detection circuit  48 .  
         [0052]    The PNP transistors  75 ,  76 , and  77  have the same sizes, and constitute a current mirror circuit. All the resistances R 11 , R 12 , and R 13  of the resistors  72 ,  73 , and  74  are equal to each other, and R 11 =R 12 =and R 13  is satisfied.  
         [0053]    Operation of the circuit of the second embodiment will be described below. The detection circuit  51   a  detects a bias voltage of an input signal. More specifically, by divided resistors  48   a  and  48   b , a common mode voltage VCM serving as an offset voltage between the positive-phase input terminal  47   a  and the negative-phase input terminal  47   b  of the integrated circuit  42  is generated, and the common mode voltage VCM is output as a detection result to the current control terminals (one terminal of the resistor  71 ) of the DC current output circuits  65   a  and  65   b.    
         [0054]    The output current IPP of the DC current output circuit  65   a  and the output current IPN of the DC current output circuit  65   b  are controlled by the common mode voltage VCM. When base-emitter voltages of the PNP transistor  75  to  77  are represented by VBE 2 , the current IPP and the current IPN are expressed by equation (16):  
           IPP=IPN =( VCC 2− VCM−VBE 2)/( R 10+ R 12)  (16)  
         [0055]    The currents IPP and IPN increase as the common mode voltage VCM decreases, and decreases as the common mode voltage VCM increases. The currents IPP and IPN are set to be equal to or smaller than {fraction (1/10)} a signal current ID from the differential output circuit  44  of the integrated circuit  41 . In this manner, variations in signal voltage level at the input terminals  47   a  and  47   b  of the integrated circuit  42  can be neglected. In addition, the currents IPP and IPN are set to be equal to or larger than 10 times the draw current of the differential internal circuit  49 . In this manner, variations in signal voltage level at the input terminals  50   a  and  50   b  of the differential internal circuit  49  can be neglected.  
         [0056]    The currents IPP and IPN respectively output from the DC current output circuits  65   a  and  65   b  flow in the resistors  61   a  and  61   b . In this manner, DC voltage VPP and VPN expressed by equation (17) and equation (18) are superposed on signal voltages generated by the input terminals  47   a  and  47   b , respectively:  
           VPP=RPP×IPP   (17)  
           VPN=RPN×IPN   (18)  
         [0057]    When the potential difference VGAP 40  is generated, a voltage of VGAP 40  volt is added to the common mode voltage VCM, and the common mode voltage VCM increases as the potential difference VGAP 40  increases. The DC current output circuits  65   a  and  65   b  respectively change the currents IPP and IPN in accordance with the change of the common mode voltage VCM to respectively change the DC voltages VPP and VPN. When the DC current output circuits  65   a  and  65   b  are set such that VPP−VPN=(−VGAP 40 ) is satisfied, a bias voltage of an input signal can be corrected, and the differential internal circuit  49  the bias of which is designed in accordance with a signal voltage obtained when the VGAP 40  is 0 volt can be appropriately operated.  
         [0058]    When the resistors  61   a  and  61   b  each having a high resistance are inserted in the signal line, the pas band of the signal frequency component is deteriorated. For this reason, in order to improve the pass band, the capacitances of the capacitors  64   a  and  64   b  are set such that a low impedance is achieved for a high-frequency component. In this manner, a low impedance can be realized for a high-frequency signal component, and only a DC voltage component can be superposed on an input signal through the resistors  61   a  and  61   b  without deteriorating the high-frequency signal component.  
         [0059]    As described above, according to the second embodiment, since the resistors  61   a  and  61   b  each having a high resistance are arranged on the signal line, the input impedance of the integrated circuit  42  is determined by the terminals  48   a  and  48   b , and a simple terminal configuration can be realized. The common mode voltage VCM between the positive-phase input terminal  47   a  and the negative-phase input terminal  47   b  in the integrated circuit  42  is detected, and the output currents IPP and IPN from the DC current output circuits  65   a  and  65   b  are controlled by using the common mode voltage VCM such that the DC voltages VPP and VPN are (−VGAP) volt each, and the DC voltages VPP and VPN are superposed on an input signal of the integrated circuit  42 .  
         [0060]    In this manner, a defection operation of the differential internal circuit  49  and the deterioration of a signal amplitude caused by the potential difference VGAP 40  can be prevented. In addition, since a large-capacity capacitor need not be inserted in the signal line, a peripheral circuit can be suppressed being increased in size. In the integrated circuit, for a signal frequency component in a wide band extending from a high frequency to a low frequency, a bias voltage of an input signal can be corrected without deteriorating a signal amplitude.  
         [0061]    The second embodiment explained the case in which PNP transistors are used, and one terminals of the resistors  72 ,  73 , and  74  of the current mirror current source are connected to the high-potential side  42   a  of the power supply. However, depending on the internal circuit configuration of the integrated circuit  42  NPN transistor may be used in place of a PNP transistor, and one terminals of the resistors  72 ,  73 , and  74  of the current mirror current source may be connected to the low-potential side  42   b  of the power supply. In this case, the same effect as described above can be obtained. The first and second embodiments explained the case in which a self-bias adjustment circuit is applied to an integrated circuit. However, the self-bias adjustment circuit may be applied to not only an integrated circuit but also a discrete circuit. In this case, the same effect as described above can be obtained.  
         [0062]    As described above, according to this invention, influence of a potential difference on the low-potential side of the power supply can be suppressed without using a large-capacity capacitor. Therefore, the internal circuit is appropriately operated while suppressing an increase in size of the device and an increase in cost to make it possible to reduce a deterioration of a signal amplitude is achieved. Furthermore, the detection unit has a simple circuit configuration. Therefore, cost reduction becomes possible. Furthermore, DC current depending on a detection result can be output.  
         [0063]    Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.