Abstract:
An interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populate with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 11/835,235 entitled DUAL LAMINATE PACKAGE STRUCTURE WITH EMBEDDED ELEMENTS filed Aug. 7, 2007 now U.S. Pat. No. 7,687,899. 
    
    
     STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT 
     Not Applicable 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to integrated circuit chip package technology and, more particularly, to a semiconductor package which includes a prefabricated embedded interposer configured to allow two complimentary laminate substrate elements (i.e., a bottom element and a top element) to be joined to each other subsequent to one or both of the substrate elements being populated with various electronic components. 
     2. Description of the Related Art 
     Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body. 
     The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die attach pad or die pad of the leadframe also remains exposed within the package body. In other semiconductor packages, the metal leadframe is substituted with a laminate substrate to which the semiconductor die is mounted and which includes pads or terminals for mimicking the functionality of the leads and establishing electrical communication with another device. 
     Once the semiconductor dies have been produced and encapsulated in the semiconductor packages described above, they may be used in a wide variety of electronic devices. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically includes a printed circuit board on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor dies highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density. 
     Even though semiconductor packages have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a need to find a semiconductor package design to maximize the number of semiconductor packages that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor packages. One method to minimize space needed to accommodate the semiconductor packages is to stack the semiconductor packages on top of each other, or to stack individual semiconductor devices or other devices within the package body of the semiconductor package. However, existing solutions for package stacking such as straddle mount laminate BGA or stacked die TSOP often do not meet form factor requirements. Therefore, a new solution is needed. The present invention is an extension of the stacking solution for space efficiency in that it is directed to, among other things, a semiconductor package which includes a prefabricated embedded interposer configured to allow two complimentary laminate substrate elements (i.e., a bottom element and a top element) to be joined to each subsequent to one or both of the substrate elements being populated with various electronic components. In this regard, the present invention provides a two-sided package architecture which allows topside routing (also known as a “lands-over-top” feature) while also enabling the embedding of multiple components, including but not limited to active, passive and prepackaged components. These, as well as other features and attributes of the present invention will be discussed in more detail below. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with the invention, there is provided an interconnect structure (i.e., an interposer) which is mounted and electrically connected to a bottom semiconductor package substrate either prior or subsequent to such bottom substrate being populated with one or more electronic components. Subsequently, a top semiconductor package substrate which may also be populated with one or more electronic components is mounted to the interposer, such that all of the electronic components are disposed between the top and bottom interposers. The mounting of the interposer to the bottom and top substrates may be accomplished by way of a standard ball grid array (BGA) interconnect or other type of interconnect. Thereafter, a suitable mold compound is injected between the top and bottom substrates, the mold compound flowing about the electronic components, between the BGA joints, and at least partially about the interposer, thus helping to lock the interposer in place in the completed semiconductor package. The interposer may be mounted to a bottom substrate strip with an array of units so that a single interposer strip or frame is attached to adjacent units. During singulation (i.e., the separation of the completed units or semiconductor packages from each other), the interposer is separated so that the interposer is exposed on at least one side of the semiconductor package. 
     The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These, as well as other features of the present invention, will become more apparent upon reference to the drawings wherein: 
         FIG. 1  is a cross-sectional view of the semiconductor package constructed in accordance with a first embodiment of the present invention; 
         FIG. 2  is a cross-sectional view of a semiconductor package constructed in accordance with a second embodiment of the present invention; 
         FIG. 3  is a cross-sectional view of a semiconductor package constructed in accordance with a third embodiment of the present invention; and 
         FIGS. 4A-4D  illustrate an exemplary sequence of steps which may be used to fabricate the semiconductor package of the second embodiment shown in  FIG. 2 . 
     
    
    
     Common reference numerals are used throughout the drawings and detailed description to indicate like elements. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring now to the drawings wherein the showings are for purposes of illustrating various embodiments of the present invention only, and not for purposes of limiting the same,  FIG. 1  depicts a semiconductor package  10  constructed in accordance with a first embodiment of the present invention. The semiconductor package  10  comprises a laminate bottom substrate  12  which has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the bottom substrate  12  defines a generally planar top surface  14  and an opposed, generally planar bottom surface  16 . Disposed on the top surface  14  is a plurality of top contacts  18  of the bottom substrate  12 . In the bottom substrate  12 , the top contacts  18  are segregated into two sets, with the top contacts  18  of each set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the bottom substrate  12 . Formed on the bottom surface  16  of the bottom substrate  12  is a plurality of bottom contacts  20 . Though not shown in  FIG. 1 , the top and bottom contacts  18 ,  20  are electrically connected to each other in a prescribed pattern or arrangement by conductive vias which extend through the bottom substrate  12 . 
     Attached to a central area of the top surface  14  of the bottom substrate  12  is at least one electronic component of the semiconductor package  10 , and more particularly a die stack  22 . The die stack  22  comprises a plurality of individual semiconductor dies  24  which are arranged in a stacked configuration. In this regard, the uppermost semiconductor die  24  in the die stack  22  is secured to the semiconductor die  24  below it by a layer of suitable adhesive. Similarly, the attachment of the lowermost semiconductor die  24  in the die stack  22  to the top surface  14  of the bottom substrate  12  is facilitated by an adhesive layer  26 . As shown in  FIG. 1 , two (2) semiconductor dies  24  are depicted as being included in the die stack  22 . However, those of ordinary skill in the art will recognize that the die stack  22  may be assembled to include greater than the two semiconductor dies  24  depicted in  FIG. 1 , or may be substituted with a single semiconductor die  24 . In the semiconductor package  10 , the pads or terminals of each of the semiconductor dies  24  of the die stack  22  are electrically connected to at least some of the top contacts  18  through the use of conductive wires  28 . More particularly, in the semiconductor package  10 , it is contemplated that the conductive wires  28  may extend from the semiconductor dies  24  to conductive traces or the like which are disposed on the top surface  14  and in turn electrically connected to the top contacts  18  in a prescribed pattern or arrangement. The conductive wires  28  may be fabricated from aluminum, copper, gold, silver or a functional equivalent. Though not shown in  FIG. 1 , conductive wires may also be used to electrically connect the semiconductor dies  24  of the die stack  22  to each other. Though also not shown in  FIG. 1 , it is contemplated that the lowermost semiconductor die  24  in the die stack  22  may be electrically connected to such conductive traces on the top surface  14  of the underlying bottom substrate  12  through the use of a flip-chip connection as an alternative to the use of the wires  28 . 
     The semiconductor package  10  further comprises an interposer  30  which is mounted and electrically connected to the top contacts  18  of the bottom substrate  12 . It is contemplated that the interposer  30  may comprise a first segment  30   a  which is electrically connected to each of the top contacts  18  of one of the sets thereof, and a separate second segment  30   b  which is electrically connected to each of the top contacts  18  of the remaining set thereof. The first and second segments  30   a ,  30   b  of the interposer  30  are identically configured to each other and, in the completed semiconductor package  10 , extend in spaced, generally parallel relation to each other. 
     Each of the interposer segments  30   a ,  30   b  of the interposer  30  comprises an interposer body  32  having a top surface  34 , a bottom surface  36 , an opposed pair of longitudinal side surfaces  37 , and an opposed pair of lateral side surfaces. Disposed on the top surface  34  of the interposer body  32  of each of the first and second segments  30   a ,  30   b  is a plurality of top pads  38 . Similarly, disposed on the bottom surface  36  of each of the first and second segments  30   a ,  30   b  is a plurality of bottom pads  40 . The top and bottom pads  38 ,  40  disposed on the interposer body  32  of each of the first and second segments  30   a ,  30   b  are segregated into multiple pairs, with the top pad  38  of each pair being disposed in spaced, substantial vertical alignment with the bottom pad  40  of the same pair. The top and bottom pads  38 ,  40  of each pair within each of the first and second segments  30   a ,  30   b  are electrically connected to each other by one or more conductive vias  42  which extend through the interposer body  32  substantially perpendicularly between the top and bottom pads  38 ,  40  of the corresponding pair. The top and bottom pads  38 ,  40  of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is the conductive via(s)  42  extending therebetween. Those of ordinary skill in the art will recognize that the top and bottom pads  38 ,  40  of each pair need not necessarily be in exact vertical alignment, and that some degree of juxtaposition therebetween is contemplated to fall within the scope of the present invention. 
     In the semiconductor package  10 , each bottom pad  40  in each of the first and second segments  30   a ,  30   b  is electrically connected to a respective one of the top contacts  18  of a corresponding set thereof by a solder ball  44 . However, those of ordinary skill in the art will recognize that solder paste, conductive adhesive, or other suitable materials may be employed as an alternative to the use of the solder balls  44 . As seen in  FIG. 1 , such attachment is preferably facilitated such that one of the longitudinal side surfaces  37  of each of the first and second segments  30   a ,  30   b  extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the bottom substrate  12 . Formed on each of the bottom contacts  20  of the bottom substrate  12  is a solder bump or solder ball  46 . 
     The semiconductor package  10  of the first embodiment further comprises a laminate top substrate  48  which is mechanically and electrically connected to the interposer  30  in a manner which will be described in more detail below. The top substrate  48  also has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the top substrate  48  defines a generally planar top surface  50  and an opposed, generally planar bottom surface  52 . Disposed in the approximate center of the top surface  50  of the top substrate  48  is a plurality of top contacts  54  of the top substrate  48 . Additionally, formed on the bottom surface  52  of the top substrate  48  is a plurality of bottom contacts  56  thereof. In the top substrate  48 , the bottom contacts  56  are segregated into two sets, with the bottom contacts  56  of each set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the top substrate  48 . Though not shown, the top and bottom contacts  54 ,  56  are electrically connected to each other by conductive vias which extend through the top substrate  48 . Those of ordinary skill in the art will recognize that each top contact  54  may be electrically connected to one or more bottom contacts  56  in any pattern or arrangement through the use of such conductive vias. The top and bottom contacts  54 ,  56  are also each preferably identically configured to each other, and fabricated from a suitable conductive material, as is any conductive via extending there between. 
     In the semiconductor package  10 , each top pad  38  of each of the first and second segments  30   a ,  30   b  of the interposer  30  is electrically connected to a respective one of the bottom contacts  56  of a corresponding set thereof by a solder ball  58 . However, those of ordinary skill in the art will recognize that solder paste, conductive adhesive, or other suitable materials may be employed as an alternative to the use of the solder balls  58 . As is also seen in  FIG. 1 , such attachment is preferably facilitated such that one of the longitudinal side surfaces  37  of each of the first and second segments  30   a ,  30   b  extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the top substrate  48 . Thus, in addition to extending in generally co-planar relation to respective longitudinal side surfaces  37  of the first and second segments  30   a ,  30   b , the peripheral edge segments defined by the top substrate  48  also extend in generally co-planar relation to respective ones of the peripheral edge segments defined by the bottom substrate  12 . When the top substrate  48  is electrically and mechanically connected to the interposer  30  in the above-described manner, the die stack  22  as well as the conductive wires  28  are effectively positioned between the bottom and top substrates  12 ,  48 , and more particularly the top surface  14  of the bottom substrate  12  and the bottom surface  52  of the top substrate  48 . 
     In the semiconductor package  10 , the die stack  22 , wires  28  and portions of the first and second segments  30   a ,  30   b  of the interposer  30  are encapsulated or covered by an encapsulant material which is injected between the bottom and top substrates  12 ,  48 . Such encapsulant material, upon hardening, forms a package body  60  of the semiconductor package  10 . Also fully covered by the package body  60  are the solder balls  44 ,  58  used to effectuate the electrical connection between the first and second segments  30   a ,  30   b  of the interposer  30  and the bottom and top substrates  12 ,  48 . The fully formed package body  60  directly contacts the top surface  14  of the bottom substrate  12  as well as the bottom surface  52  of the top substrate  48 , and extends to a substantially flush relationship to the peripheral edge segments thereof. In addition, the package body  60  defines multiple side surfaces  62 , and is formed such that one of the longitudinal side surfaces  37  of the interposer body  32  of each of the first and second segments  30   a ,  30   b  is exposed in and substantially flush with a respective one of such side surfaces  62 . Further, though not shown, it is contemplated that each of the lateral side surfaces of the interposer body  32  of each of the first and second segments  30   a ,  30   b  will be exposed in and substantially flush with a respective one of the side surfaces  62 . 
     As indicated above, in the semiconductor package  10 , two sets of the top contacts  18  are provided on the bottom substrate  12 , with the top contacts  18  of each set extending along a respective one of an opposed pair of side surfaces  62  defined by the package body  60 . Similarly, two sets of the bottom contacts  56  are provided on the top substrate  48 , with the bottom contacts  56  of each set extending along a respective one of an opposed pair of side surfaces  62  defined by the package body  60 . However, it is contemplated that the top contacts  18  and bottom contacts  56  may each be segregated into greater or fewer than two sets, and may be arranged so as to extend along one or more of the side surfaces  62  defined by the package body  60  in any combination. As will be recognized, if the top contacts  18  and bottom contacts  56  are each arranged as a single set extending along only a single, common side surface  62  of the package body  60 , such semiconductor package may include an interposer  30  having only one of the above-described first and second segments  30   a ,  30   b . Alternatively, if multiple sets of the top contacts  18  and bottom contacts  56  are provided so as to extend along respective ones of each of the side surfaces  62  of the package body  60 , the interposer  30  may be formed to have a continuous ring-like or frame-like configuration. The top contacts  54  of the top substrate  48  provide top side routing also known as a “lands-over-top” feature in the completed semiconductor package  10 . 
     Referring now to  FIG. 2 , there is depicted a semiconductor package  100  constructed in accordance with a second embodiment of the present invention. The semiconductor package  100  comprises a laminate bottom substrate  112  which has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the bottom substrate  112  defines a generally planar top surface  114  and an opposed, generally planar bottom surface  116 . Disposed on the top surface  114  is a plurality of top contacts  118  of the bottom substrate  112 . In the bottom substrate  112 , the top contacts  118  are segregated into two sets, with the top contacts  118  of each set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the bottom substrate  112 . Formed on the bottom surface  116  of the bottom substrate  112  is a plurality of bottom contacts  120 . Though not shown in  FIG. 2 , the top and bottom contacts  118 ,  120  are electrically connected to each other in a prescribed pattern or arrangement by conductive vias which extend through the bottom substrate  112 . Further, the top and bottom contacts  118 ,  120  are preferably identically configured to each other, and fabricated from a suitable conductive material, as is any conductive via extending therebetween. 
     Attached to a central area of the top surface  114  of the bottom substrate  112  is at least one electronic component  122  of the semiconductor package  100 , which is preferably a semiconductor die. The attachment of the electronic component  122  to the top surface  114  of the bottom substrate  112  is facilitated by an adhesive layer  126 . Those of ordinary skill in the art will recognize that the electronic component  122  may alternatively comprise the die stack  22  described above in relation to the semiconductor package  10 . In the semiconductor package  100 , the pads or terminals of the electronic component  122  are electrically connected to at least some of the top contacts  118  through the use of conductive wires  128 . More particularly, in the semiconductor package  100 , it is contemplated that the conductive wires  128  may extend from the electronic component  122  to conductive traces or the like which are disposed on the top surface  114  and in turn electrically connected to the top contacts  118  in a prescribed pattern or arrangement. The conductive wires  128  may be fabricated from aluminum, copper, gold, silver or a functional equivalent. Though not shown in  FIG. 2 , it is contemplated that the electronic component  122  may be electrically connected to such conductive traces on the top surface  114  of the underlying bottom substrate  112  through the use of a flip-chip connection as an alternative to the use of the wires  128 . 
     The semiconductor package  100  further comprises an interposer  130  which is mounted and electrically connected to the top contacts  118  of the bottom substrate  112 . It is contemplated that the interposer  130  may comprise a first segment  130   a  which is electrically connected to each of the top contacts  118  of one of the sets thereof, and a separate second segment  130   b  which is electrically connected to each of the top contacts  118  of the remaining set thereof. The first and second segments  130   a ,  130   b  of the interposer  130  are identically configured to each other and, in the completed semiconductor package  100 , extend in spaced, generally parallel relation to each other. 
     Each of the interposer segments  130   a ,  130   b  of the interposer  130  comprises an interposer body  132  having a top surface  134 , a bottom surface  136 , an opposed pair of longitudinal side surfaces  137 , and an opposed pair of lateral side surfaces. Disposed on the top surface  134  of the interposer body  132  of each of the first and second segments  130   a ,  130   b  is a plurality of top pads  138 . Similarly, disposed on the bottom surface  136  of each of the first and second segments  130   a ,  130   b  is a plurality of bottom pads  140 . The top and bottom pads  138 ,  140  disposed on the interposer body  132  of each of the first and second segments  130   a ,  130   b  are segregated into multiple pairs, with the top pad  138  of each pair being disposed in spaced, substantial vertical alignment with the bottom pad  140  of the same pair. The top and bottom pads  138 ,  140  of each pair within each of the first and second segments  130   a ,  130   b  are electrically connected to each other by one or more conductive vias  142  which extend through the interposer body  132  substantially perpendicularly between the top and bottom pads  138 ,  140  of the corresponding pair. The top and bottom pads  138 ,  140  of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is the conductive via(s)  142  extending therebetween. Those of ordinary skill in the art will recognize that the top and bottom pads  138 ,  140  of each pair need not necessarily be in exact vertical alignment, and that some degree of juxtaposition therebetween is contemplated to fall within the scope of the present invention. 
     In the semiconductor package  100 , each bottom pad  140  in each of the first and second segments  130   a ,  130   b  is electrically connected to a respective one of the top contacts  118  of a corresponding set thereof by a solder ball  144 . However, those of ordinary skill in the art will recognize that solder paste, conductive adhesive, or other suitable materials may be employed as an alternative to the use of the solder balls  144 . As seen in  FIG. 2 , such attachment is preferably facilitated such that one of the longitudinal side surfaces  137  of each of the first and second segments  130   a ,  130   b  extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the bottom substrate  112 . Formed on each of the bottom contacts  120  of the bottom substrate  112  is a solder bump or solder ball  146 . 
     The semiconductor package  100  of the first embodiment further comprises a laminate top substrate  148  which is mechanically and electrically connected to the interposer  130  in a manner which will be described in more detail below. The top substrate  148  also has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the top substrate  148  defines a generally planar top surface  150  and an opposed, generally planar bottom surface  152 . Disposed in the approximate center of the top surface  150  of the top substrate  148  is a plurality of top contacts  154  of the top substrate  148 . Additionally, formed on the bottom surface  152  of the top substrate  148  is a plurality of bottom contacts  156  thereof. In the top substrate  148 , some of the bottom contacts  156  are segregated into two sets, with the bottom contacts  156  of each such set extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the top substrate  148 . Though not shown, the top and bottom contacts  154 ,  156  are electrically connected to each other by conductive vias which extend through the top substrate  148 . Those of ordinary skill in the art will recognize that each top contact  154  may be electrically connected to one or more bottom contacts  156  in any pattern or arrangement through the use of such conductive vias. The top and bottom contacts  154 ,  156  are also each preferably identically configured to each other, and fabricated from a suitable conductive material, as is any conductive via extending there between. 
     Attached to a central area of the bottom surface  152  of the top substrate  148  is at least one, and preferably multiple electronic components  124 . Such electronic component(s)  124  may comprise semiconductor dies, passive devices or the like provided in any combination. The attachment of one or more of the electronic components  124  to the bottom surface  152  of the top substrate  148  may be facilitated by an adhesive layer. In the semiconductor package  100 , the pads or terminals of the electronic components  124  are electrically connected to respective ones of the centrally located bottom contacts  156  through the use of a flip-chip connection. Though not shown in  FIG. 2 , it is contemplated that the electronic components  124  may be electrically connected to such bottom contacts  156  through the use of conductive wires as an alternative to the use of a flip-chip connection. 
     In the semiconductor package  100 , each top pad  138  of each of the first and second segments  130   a ,  130   b  of the interposer  130  is electrically connected to a respective one of the bottom contacts  156  of a corresponding set thereof by a solder ball  158 . However, those of ordinary skill in the art will recognize that solder paste, conductive adhesive, or other suitable materials may be employed as an alternative to the use of the solder balls  158 . As is also seen in  FIG. 2 , such attachment is preferably facilitated such that one of the longitudinal side surfaces  137  of each of the first and second segments  130   a ,  130   b  extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the top substrate  148 . Thus, in addition to extending in generally co-planar relation to respective longitudinal side surfaces  137  of the first and second segments  130   a ,  130   b , the peripheral edge segments defined by the top substrate  148  also extend in generally co-planar relation to respective ones of the peripheral edge segments defined by the bottom substrate  112 . When the top substrate  148  is electrically and mechanically connected to the interposer  130  in the above-described manner, the electronic components  122 ,  124  as well as the conductive wires  128  are effectively positioned between the bottom and top substrates  112 ,  148 , and more particularly the top surface  114  of the bottom substrate  112  and the bottom surface  152  of the top substrate  148 . 
     In the semiconductor package  100 , the electronic components  122 ,  124 , wires  128  and portions of the first and second segments  130   a ,  130   b  of the interposer  130  are encapsulated or covered by an encapsulant material which is injected between the bottom and top substrates  112 ,  148 . Such encapsulant material, upon hardening, forms a package body  160  of the semiconductor package  100 . Also fully covered by the package body  160  are the solder balls  144 ,  158  used to effectuate the electrical connection between the first and second segments  130   a ,  130   b  of the interposer  130  and the bottom and top substrates  112 ,  148 . The fully formed package body  160  directly contacts the top surface  114  of the bottom substrate  112  as well as the bottom surface  152  of the top substrate  148 , and extends to a substantially flush relationship to the peripheral edge segments thereof. In addition, the package body  160  defines multiple side surfaces  162 , and is formed such that one of the longitudinal side surfaces  137  of the interposer body  132  of each of the first and second segments  130   a ,  130   b  is exposed in and substantially flush with a respective one of such side surfaces  162 . Further, though not shown, it is contemplated that each of the lateral side surfaces of the interposer body  132  of each of the first and second segments  130   a ,  130   b  will be exposed in and substantially flush with a respective one of the side surfaces  162 . 
     As indicated above, in the semiconductor package  100 , two sets of the top contacts  118  are provided on the bottom substrate  112 , with the top contacts  118  of each set extending along a respective one of an opposed pair of side surfaces  162  defined by the package body  160 . Similarly, two sets of the bottom contacts  156  are provided on the top substrate  148 , with the bottom contacts  156  of each set extending along a respective one of an opposed pair of side surfaces  162  defined by the package body  160 . However, it is contemplated that the top contacts  118  and bottom contacts  156  (other than those to which the electronic components  124  are connected) may each be segregated into greater or fewer than two sets, and may be arranged so as to extend along one or more of the side surfaces  162  defined by the package body  160  in any combination. As will be recognized, if such top contacts  118  and bottom contacts  156  are each arranged as a single set extending along only a single, common side surface  162  of the package body  160 , such semiconductor package may include an interposer  130  having only one of the above-described first and second segments  130   a ,  130   b . Alternatively, if multiple sets of such top contacts  118  and bottom contacts  156  are provided so as to extend along respective ones of each of the side surfaces  162  of the package body  160 , the interposer  130  may be formed to have a continuous ring-like or frame-like configuration. The top contacts  154  of the top substrate  148  provide top side routing also known as a “lands-over-top” feature in the completed semiconductor package  100 . 
     Referring now to  FIG. 3 , there is depicted a semiconductor package  200  constructed in accordance with a third embodiment of the present invention. The semiconductor package  200  comprises a laminate bottom substrate  212  which has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the bottom substrate  212  defines a generally planar top surface  214  and an opposed, generally planar bottom surface  216 . Disposed on the top surface  214  is a plurality of top contacts  218  of the bottom substrate  212 . In the bottom substrate  212 , the top contacts  218  are segregated into at least three sets, with the top contacts  218  of two of these sets extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the bottom substrate  212 . The top contacts  218  of the third set extend between and in generally parallel relation to the top contacts  218  of the other two sets thereof. Formed on the bottom surface  216  of the bottom substrate  212  is a plurality of bottom contacts  220 . Though not shown in  FIG. 3 , the top and bottom contacts  218 ,  220  are electrically connected to each other in a prescribed pattern or arrangement by conductive vias which extend through the bottom substrate  212 . 
     Attached to a central area of the top surface  214  of the bottom substrate  212  is at least one electronic component  222  of the semiconductor package  200 , which is preferably a semiconductor die. The attachment of the electronic component  222  to the top surface  214  of the bottom substrate  212  is facilitated by an adhesive layer  226 . Those of ordinary skill in the art will recognize that the electronic component  222  may alternatively comprise the die stack  22  described above in relation to the semiconductor package  10 . In the semiconductor package  200 , the pads or terminals of the electronic component  222  are electrically connected to at least some of the top contacts  218  through the use of conductive wires  228 . More particularly, in the semiconductor package  200 , it is contemplated that the conductive wires  228  may extend from the electronic component  222  to conductive traces or the like which are disposed on the top surface  214  and in turn electrically connected to the top contacts  218  in a prescribed pattern or arrangement. The conductive wires  228  may be fabricated from aluminum, copper, gold, silver or a functional equivalent. Though not shown in  FIG. 3 , it is contemplated that the electronic component  222  may be electrically connected to such conductive traces on the top surface  214  of the underlying bottom substrate  212  through the use of a flip-chip connection as an alternative to the use of the wires  228 . 
     The semiconductor package  200  further comprises an interposer  230  which is mounted and electrically connected to the top contacts  218  of the bottom substrate  212 . It is contemplated that the interposer  230  may comprise separate first, second and third segments  230   a ,  230   b ,  230   c  which are electrically connected to each of the top contacts  218  of respective ones of the three sets thereof. The first, second and third segments  230   a ,  230   b ,  230   c  of the interposer  230  are identically configured to each other and, in the completed semiconductor package  200 , extend in spaced, generally parallel relation to each other. 
     Each of the interposer segments  230   a ,  230   b ,  230   c  of the interposer  230  comprises an interposer body  232  having a top surface  234 , a bottom surface  236 , an opposed pair of longitudinal side surfaces  237 , and an opposed pair of lateral side surfaces. Disposed on the top surface  234  of the interposer body  232  of each of the first, second and third segments  230   a ,  230   b ,  230   c  is a plurality of top pads  238 . Similarly, disposed on the bottom surface  236  of each of the first, second and third segments  230   a ,  230   b ,  230   c  is a plurality of bottom pads  240 . The top and bottom pads  238 ,  240  disposed on the interposer body  232  of each of the first, second and third segments  230   a ,  230   b ,  230   c  are segregated into multiple pairs, with the top pad  238  of each pair being disposed in spaced, substantial vertical alignment with the bottom pad  240  of the same pair. The top and bottom pads  238 ,  240  of each pair within each of the first and second segments  230   a ,  230   b  are electrically connected to each other by one or more conductive vias  242  which extend through the interposer body  232  substantially perpendicularly between the top and bottom pads  238 ,  240  of the corresponding pair. The top and bottom pads  238 ,  240  of each pair are preferably identically configured to each other, and fabricated from a suitable conductive material, as is the conductive via(s)  242  extending therebetween. Those of ordinary skill in the art will recognize that the top and bottom pads  238 ,  240  of each pair need not necessarily be in exact vertical alignment, and that some degree of juxtaposition therebetween is contemplated to fall within the scope of the present invention. 
     In the semiconductor package  200 , each bottom pad  240  in each of the first, second and third segments  230   a ,  230   b ,  230   c  is electrically connected to a respective one of the top contacts  218  of a corresponding set thereof by a solder ball  244 . However, those of ordinary skill in the art will recognize that solder paste, conductive adhesive, or other suitable materials may be employed as an alternative to the use of the solder balls  244 . As seen in  FIG. 3 , such attachment is preferably facilitated such that one of the longitudinal side surfaces  237  of each of the first and second segments  230   a ,  230   b  extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the bottom substrate  212 . Formed on each of the bottom contacts  220  of the bottom substrate  212  is a solder bump or solder ball  246 . 
     The semiconductor package  200  of the third embodiment further comprises a laminate top substrate  248  which is mechanically and electrically connected to the interposer  230  in a manner which will be described in more detail below. The top substrate  248  also has a generally quadrangular configuration defining four (4) peripheral edge segments. In addition, the top substrate  248  defines a generally planar top surface  250  and an opposed, generally planar bottom surface  252 . Disposed on the top surface  250  of the top substrate  248  is a plurality of top contacts  254  of the top substrate  248 . Additionally, formed on the bottom surface  252  of the top substrate  248  is a plurality of bottom contacts  256  thereof. In the top substrate  248 , some of the bottom contacts  256  are segregated into three sets, with the bottom contacts  256  of two of these three sets extending along and in spaced relation to a respective one of an opposed pair of the peripheral edge segments defined by the top substrate  248 . The bottom contacts  256  of the third set extend between and in generally parallel relation to the bottom contacts  256  of the other two sets thereof. Though not shown, the top and bottom contacts  254 ,  256  are electrically connected to each other by conductive vias which extend through the top substrate  248 . Those of ordinary skill in the art will recognize that each top contact  254  may be electrically connected to one or more bottom contacts  256  in any pattern or arrangement through the use of such conductive vias. The top and bottom contacts  254 ,  256  are also each preferably identically configured to each other, and fabricated from a suitable conductive material, as is any conductive via extending there between. 
     Attached to the bottom surface  252  of the top substrate  248  is at least one, and preferably multiple electronic components  224 . Such electronic component(s)  224  may comprise semiconductor dies, passive devices or the like provided in any combination. The attachment of one or more of the electronic components  224  to the bottom surface  252  of the top substrate  248  may be facilitated by an adhesive layer. In the semiconductor package  200 , the pads or terminals of the electronic components  224  are electrically connected to certain ones of the bottom contacts  256  through the use of a flip-chip connection. Though not shown in  FIG. 3 , it is contemplated that the electronic components  224  may be electrically connected to such bottom contacts  256  through the use of conductive wires as an alternative to the use of a flip-chip connection. 
     In the semiconductor package  200 , each top pad  238  of each of the first, second and third segments  230   a ,  230   b ,  230   c  of the interposer  230  is electrically connected to a respective one of the bottom contacts  256  of a corresponding set thereof by a solder ball  258 . However, those of ordinary skill in the art will recognize that solder paste, conductive adhesive, or other suitable materials may be employed as an alternative to the use of the solder balls  258 . As is also seen in  FIG. 3 , such attachment is preferably facilitated such that one of the longitudinal side surfaces  237  of each of the first and second segments  230   a ,  230   b  extends in generally co-planar relation to a respective one of the sides or peripheral edge segments defined by the top substrate  248 . Thus, in addition to extending in generally co-planar relation to respective longitudinal side surfaces  237  of the first and second segments  230   a ,  230   b , the peripheral edge segments defined by the top substrate  248  also extend in generally co-planar relation to respective ones of the peripheral edge segments defined by the bottom substrate  212 . When the top substrate  248  is electrically and mechanically connected to the interposer  230  in the above-described manner, the electronic components  222 ,  224  as well as the conductive wires  228  are effectively positioned between the bottom and top substrates  212 ,  248 , and more particularly the top surface  214  of the bottom substrate  212  and the bottom surface  252  of the top substrate  248 . Further, the third segment  230   c  of the interposer  230  creates an effective barrier between the electronic component  222  and one of the electronic components  224 , the advantages of which will be discussed in more detail below. 
     In the semiconductor package  200 , the electronic components  222 ,  224 , wires  228 , portions of the first and second segments  230   a ,  230   b  of the interposer  230 , and the entirety of the third segment  230   c  of the interposer  230  are encapsulated or covered by an encapsulant material which is injected between the bottom and top substrates  212 ,  248 . Such encapsulant material, upon hardening, forms a package body  260  of the semiconductor package  200 . Also fully covered by the package body  260  are the solder balls  244 ,  258  used to effectuate the electrical connection between the first, second and third segments  230   a ,  230   b ,  230   c  of the interposer  230  and the bottom and top substrates  212 ,  248 . The fully formed package body  260  directly contacts the top surface  214  of the bottom substrate  212  as well as the bottom surface  252  of the top substrate  248 , and extends to a substantially flush relationship to the peripheral edge segments thereof. In addition, the package body  260  defines multiple side surfaces  262 , and is formed such that one of the longitudinal side surfaces  237  of the interposer body  232  of each of the first and second segments  230   a ,  230   b  is exposed in and substantially flush with a respective one of such side surfaces  262 . Further, though not shown, it is contemplated that each of the lateral side surfaces of the interposer body  232  of each of the first, second and third segments  230   a ,  230   b ,  230   c  will be exposed in and substantially flush with a respective one of the side surfaces  262 . The orientation of the third segment  230   c  of the interposer  230  n the semiconductor package  200  allows one or more of the electronic components  222 ,  224  to be “compartmentalized” for purposes of shielding the same from the remaining electronic component(s)  222 ,  224 . 
     As indicated above, in the semiconductor package  200 , three sets of the top contacts  218  are provided on the bottom substrate  212 , with the top contacts  218  of two of these sets extending along respective ones of an opposed pair of side surfaces  262  defined by the package body  260 . Similarly, three sets of the bottom contacts  256  are provided on the top substrate  248 , with the bottom contacts  256  of two of these sets extending along respective ones of an opposed pair of side surfaces  262  defined by the package body  260 . However, it is contemplated that the top contacts  218  and bottom contacts  256  (other than those to which the third segment  230   c  and electronic components  124  are connected) may each be segregated into greater or fewer than two sets, and may be arranged so as to extend along one or more of the side surfaces  262  defined by the package body  260  in any combination. As will be recognized, if such top contacts  218  and bottom contacts  256  are each arranged as a single set extending along only a single, common side surface  262  of the package body  260 , such semiconductor package may include an interposer  230  having the third segment  230   c  and only one of the above-described first and second segments  230   a ,  230   b . Alternatively, if multiple sets of such top contacts  218  and bottom contacts  256  are provided so as to extend along respective ones of each of the side surfaces  262  of the package body  260 , the interposer  230  may be formed to have a continuous ring-like or frame-like configuration, with the third segment  230   c  bisecting such frame. The top contacts  254  of the top substrate  248  provide top side routing also known as a “lands-over-top” feature in the completed semiconductor package  200 . 
     Referring now to  FIGS. 4A-4D , there is depicted an exemplary sequence of steps which may be used to facilitate the simultaneous fabrication of multiple semiconductor packages  100  constructed in accordance with the second embodiment of the present invention. As seen in  FIG. 4A , in the initial step of the fabrication process, a plurality of the top substrates  148  are provided, with the electronic component(s)  124  being electrically connected to certain ones of the bottom contacts  156  of each of the top substrates  148  in the same manner described above in relation to the semiconductor package  100  shown in  FIG. 2 . As is further shown in  FIG. 4A , for each top substrate  148 , solder balls  158  are formed on those bottom contacts  156  which are arranged as the two sets extending along respective ones of an opposed pair of the peripheral edge segments defined by such top substrate  148 . 
     In the next step of the fabrication process, a bottom substrate strip  312  is provided, such bottom substrate strip  312  including multiple bottom substrates  112  which are integrally connected to each other. In this respect, disposed on the top surface of the bottom substrate strip  312  is a plurality of the top contacts  118  which are oriented such that each of the bottom substrates  112  included in the bottom substrate strip  312  is provided with an assortment of the top contacts  118  arranged in the same pattern described above in relation to the bottom substrate  112  of the semiconductor package  100  shown in  FIG. 2 . As shown in  FIG. 4B , electrically connected to the top contacts  118  of the bottom substrate strip  312  is an interposer strip  330  which comprises a plurality of interposers  130  integrally connected to each other. The interposer strip  330  is oriented relative to the bottom substrate strip  312  such that each of the interposers  130  within the interposer strip  330  is aligned with and electrically connected to the top contacts  118  of a corresponding one of the bottom substrates  112  in the bottom substrate strip  312  in the same manner described above in relation to the electrical connection of the interposer  130  to the bottom substrate  112  in the semiconductor package  100  shown in  FIG. 2 . The electrical connection of the interposer strip  330  to the top contacts  118  of the bottom substrate strip  312  is preferably accomplished by initially forming solder balls  144  upon respective ones of the top contacts  118 , and completing a reflow process subsequent to the abutment of the bottom pads  140  of each of the interposers  130  within the interposer strip  330  against respective ones of the solder balls  144 . 
     As further shown in  FIG. 4B , in addition to the interposer strip  330  being electrically connected to the bottom substrate strip  312  in the aforementioned manner, one or more electronic components  122  is/are attached to a prescribed location of the top surface of the bottom substrate strip  312 . The electronic component(s)  122  is/are electrically connected to certain ones of the top contacts  118  of a corresponding one of the bottom substrates  112  within the bottom substrate strip  312  in the same manner described above in relation to the electrical connection of the electronic component  122  to certain ones of the top contacts  118  of the bottom substrate  112  in the semiconductor package  100  shown in  FIG. 2 . Additionally, the electronic component(s)  122  is/are oriented in respective voids or openings  331  of the interposer strip  330 , each such opening  331  extending between the first and second segments  130   a ,  130   b  of a respective one of the interposers  130  within the interposer strip  330 . 
     In the next step of the fabrication process shown in  FIG. 4C , each of the top substrates  148  shown in  FIG. 4A  is mated and electrically connected to a respective one of the interposers  130  within the interposer strip  330 . The mounting and electrical connection of each top substrate  148  to a respective interposer  130  is accomplished in the same manner described above in relation to the electrical connection of the top substrate  148  to the interposer  130  in the semiconductor package  100  shown in  FIG. 2 . In this regard, each of the solder balls  158  formed on respective ones of the bottom contacts  156  on each of the top substrates  148  is brought into direct contact with a respective one of the top pads  138  included in each of the interposers  130  of the interposer strip  330 . Thereafter, a reflow process is completed as effectively electrically connects each of the top substrates  148  to a corresponding one of the interposers  130  within the interposer strip  330 . 
     Subsequent to the mounting and electrical connection of each of the top substrates  148  to respective ones of the interposers  130  within the interposer strip  330 , a suitable encapsulant material or mold compound is injected between the top surface of the bottom substrate strip  312  and the bottom surface  152  of each of the top substrates  148  mounted and electrically connected to the interposer strip  330 . Thus, the encapsulant material effectively fills each of the openings  331  defined by the interposer strip  330 . As shown in  FIG. 4D , upon the hardening of the encapsulant material, a singulation process is completed to effectively separate the bottom substrate strip  312  into the individual bottom substrates  112 , and to further separate the interposer strip  330  into the individual interposers  130 . As further shown in  FIG. 4D , the singulation process is also completed such that portions of the bottom substrate strip  312  and hardened encapsulant material are removed as needed to cause one of the longitudinal side surfaces  137  of each of the first and second interposer segments  130   a ,  130   b  of each interposer  130  to extend in substantially flush relation to a respective side surface  162  of the package body  160  in each resultant semiconductor package  100 , and as also described above in relation to the semiconductor package shown in  FIG. 2 . It is contemplated that the singulation process described above will completed through sawing, though alternative singulation methods may also be employed without departing from the spirit and scope of the present invention. 
     This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.