Abstract:
A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the field of integrated circuit chips; more specifically, it relates to through-silicon-vias and methods of fabricating through-silicon-vias of integrated circuit chips. 
     BACKGROUND 
     Through-silicon-vias are electrically conductive structures that extend from the back surface to the front surface of the silicon substrate of integrated circuits. A dielectric liner between the electrically conductive core and the silicon substrate prevents the electrically conductive core from shorting to the silicon substrate. During fabrication, it is necessary to stress test these vias during the fabrication process. After stress testing, the integrated circuit chips are discarded regardless of whether the chips pass the stress test or not because of reliability concerns. This is expensive and wasteful. Accordingly, there exists a need in the art to eliminate the deficiencies and limitations described hereinabove. 
     SUMMARY 
     A first aspect of the present invention is a structure, comprising: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region. 
     A second aspect of the present invention is a method, comprising: forming a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; forming a dielectric liner on all sidewalls of the trench; and filling all remaining space in the trench with an electrical conductor, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region. 
     A third aspect of the present invention is a method, comprising: providing a structure comprising: a trench extending from a top surface of a semiconductor substrate into but not through the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls and a bottom of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region; and testing the dielectric liner by applying a direct current voltage between the electrical conductor and the core region of the semiconductor substrate and measuring a current flow from the electrical conductor and the core region of the semiconductor substrate. 
     A fourth aspect of the present invention is a method, comprising: providing a structure comprising: a trench extending from a top surface of a semiconductor substrate to a bottom surface the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls and a bottom of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region; and testing the dielectric liner by applying a direct current voltage between the electrical conductor and the core region of the semiconductor substrate and measuring a current flow from the electrical conductor and the core region of the semiconductor substrate. 
     These and other aspects of the invention are described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein: 
         FIGS. 1 to 8  illustrate fabricating and testing of a through-silicon-via according to an embodiment of the present invention; and 
         FIGS. 9 ,  9 A and  9 B illustrate an alternative through-silicon-via according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Because of the high aspect ratio (i.e., width to depth) of through-silicon-vias (TSVs) the integrity (e.g., local thickness and composition and local dielectric constant) of the dielectric liner of the TSV must be stress tested at high voltage (i.e., an accelerated wear out or life test) to ensure the reliability of shipped parts. However, the high voltage stress testing itself can degrade the dielectric liner and shorten the expected lifetime of the integrated circuit chip. The TSVs according to embodiments of the present invention provide an electrically conductive core between an inner and sacrificial region of the dielectric liner and an outer region of the dielectric liner. The inner region of the dielectric liner is not relied upon for insulating the electrically conductive core of the TSV from the silicon substrate of the integrated chip in use in the field and thus may be stress tested at high voltage with no concern for field failures due to the stress test itself. Thus, the expected life-time of the TSV has not been degraded by stress testing yet the reliability of integrated circuit chips that pass the stress test can be shipped. The sacrificial inner region of the dielectric liner is “sacrificial” in the sense that the integrity of sacrificial inner region dielectric liner has been sacrificed. It should also be understood that the abbreviation TSV can also stand for through-substrate-via when the substrate is not silicon. 
       FIGS. 1 to 8  illustrate fabricating and testing of a TSV according to an embodiment of the present invention.  FIGS. 9 ,  9 A and  9 B illustrate an alternative through-silicon-via according to an embodiment of the present invention. 
       FIG. 1  is a cross-section view of a region of an integrated chip where a TSV will be formed. In  FIG. 1 , a substrate (e.g., a single-crystal silicon substrate) has a top surface  102  and a bottom surface  103 . An exemplary field effect transistor  105  includes source/drains  110  formed in substrate  100  proximate to top surface  102 , and a gate dielectric layer  115  and a gate electrode  120 . Hereinafter, all wires and contacts are defined as being electrically conductive. A first interlevel dielectric layer  125  is formed on top surface  102  of substrate  100 . First interlevel dielectric layer  125  includes a damascene contact  130  to FET  105  and a damascene contact  130 A to substrate  100 . Formed on the top surface of first interlevel dielectric layer  125  is a second interlevel dielectric layer  135 . Formed in second interlevel dielectric layer  135  is a damascene wire  140  contacting damascene contact  130  and a damascene wire  140 A contacting damascene contact  130 A. Formed on the top surface of second interlevel dielectric layer  135  are a third interlevel dielectric layer  145 A and an interlevel fourth dielectric layer  145 B. Formed in third and fourth interlevel dielectric layers  145 A and  145 B is a dual-damascene wire  150  contacting damascene wire  140  and a dual damascene wire  150 A contacting damascene wire  140 A. Formed on the top surface of fourth interlevel dielectric layer  145 B are a fifth interlevel dielectric layer  155 A and a sixth interlevel dielectric layer  155 B. Formed in fifth and sixth interlevel dielectric layers  155 A and  155 B are a dual-damascene wire  160  contacting dual-damascene wire  150  and a dual damascene wire  160 A contacting dual-damascene wire  150 A. Formed on the top surface of sixth interlevel dielectric layer  155 B are a seventh interlevel dielectric layer  165 A and an eighth interlevel dielectric layer  165 B. Thereby there is an electrical path from dual-damascene wire  160  to FET  105  and an electrical path from dual-damascene wire  160 A to substrate  100 . Damascene contact  130 , damascene wire  140  and dual damascene wires  150  and  160  comprise a wire stack  170 A which provides electrical contact to FET  105 . Damascene contact  130 A, damascene wire  140 A and dual damascene wires  150 A and  160 A comprise a wire stack  170 B which provides electrical contact to substrate  100 . In one example, dielectric interlevel layers  145 A,  155 A and  165 A comprise a material that is a diffusion barrier to copper. In one example, interlevel dielectric layers  145 A,  155 A and  165 A comprise silicon nitride. In one example, interlevel dielectric layers  125 ,  135 ,  145 B,  155 B and  165 B comprise silicon oxide. In one example, interlevel dielectric layer  165 B comprises tetraethylorthosilicate (TEOS). In one example, contacts  130  and  130 A comprise tungsten and wires  140 ,  140 A,  150 ,  150 A,  160  and  160 A comprise copper. 
     A damascene wire or contact is a wire or contact formed by processes in which wire trenches or via openings are formed in an interlevel dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited in the trenches and on a top surface of the interlevel dielectric layer. A chemical-mechanical-polish (CMP) process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the interlevel dielectric layer to form damascene wires (or damascene vias). A dual-damascene wire or contact is a wire or contact formed in either a via first dual-damascene process or a trench first dual-damascene process. In a via first dual-damascene process, via openings are formed through the entire thickness of an interlevel dielectric layer followed by formation of trenches part of the way through the interlevel dielectric layer in any given cross-sectional view. In a trench first dual-damascene process is one in which trenches are formed part way through the thickness of an interlevel dielectric layer followed by formation of vias inside the trenches the rest of the way through the interlevel dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface the interlevel dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias. Wiring levels are comprised of the interlevel dielectric layer and the corresponding damascene and/or dual damascene wires formed in the interlevel dielectric layer. 
     In  FIG. 2 , a patterned photoresist layer  175  is formed on the top surface of dielectric layer  165 B over wire stack  170 A and wire stack  170 B. In  FIGS. 3 and 3A , an annular trench  180  (see  FIG. 3A ) having sidewalls  185  and a bottom  187  is etched (in one example, by one or more reactive ion etch (RIE) processes) through dielectric layers  125 ,  135 ,  145 A,  145 B,  155 A,  155 B,  165 A and  165 B and into substrate  100  a depth D.  FIG. 3  is a sectional view through line  3 - 3  of  FIG. 3A . Trench  180  surrounds a core  100 A of substrate  100 . Core  100 A has a width W 1  and trench  180  has a width W 2 . In one example, D is between about 1 micron and about 100 microns. In one example, W 1  is between about 0.1 micron and about 10 microns. In one example, W 2  is between about 1 microns and about 20 microns. Photoresist layer  175  (see  FIG. 2 ) is removed after trench  180  is etched. There are no devices (e.g., FETs, diodes, capacitors) formed in core  100 A. 
     In  FIG. 4 , a dielectric liner  190  is formed on sidewalls  185  and bottom  187  of trench  180  as well as on the top surface of dielectric layer  165 B. Dielectric liner  190  has a thickness T 1  on sidewalls  185  of trench  180 . In one example, T 1  is between about 0.1 microns and about 3 microns. In one example, dielectric layer comprises plasma enhanced chemical vapor deposition (PECVD) silicon oxide. 
     In  FIG. 5 , an electrical conductor  195  is formed in trench  180  and on the top surface of dielectric liner  190 . Conductor  195  completely fills the remaining space in trench  180 . Turning to  FIG. 5A , in one example, conductor  195  comprises a tantalum nitride (TaN) layer  195 A deposited on the exposed surface of dielectric liner  190 , a tantalum (Ta) layer  195 B deposited on the exposed surface of TaN layer  195 A, copper-manganese (Cu—Mn) layer  195 C deposited on the exposed surface of Ta layer  195 B, and an electroplated copper core  195 D. 
     In  FIGS. 6 and 6A , a chemical-mechanical polish (CMP) process is performed to remove conductor from the top surface of dielectric liner  190 , so top surface  197  of dielectric liner  190  is coplanar with top surface  198  of conductor  195 . A damascene stack contact  200  is formed through dielectric liner  190  and dielectric layers  165 A and  165 B to wire stack  170 B. Wire stack  170 B is isolated from electrical conductor  195  by dielectric layers  125 ,  135 ,  145 A,  145 B,  155 A,  155 B,  165 A and  165 B as well as by dielectric layer  195 .  FIG. 6  is a sectional view through line  6 - 6  of  FIG. 6A . At this point, a high voltage stress test may be performed to test the integrity (resistance to current flow and dielectric breakdown) of dielectric liner  190 . The high voltage stress includes applying a direct current (DC) voltage between the top surface  198  of conductor  195  and a damascene stack contact  200  and measuring the current flow. The current flow (if any) will be between the inner region of dielectric liner  190  between core  100 A and conductor  195  leaving the outer region of dielectric liner  195  between the rest of substrate  100  and conductor  195  unstressed. For a P-type substrate, the positive bias is applied to stack contact  200 . For an N-type substrate, the positive bias is applied to conductor  195 . In one example, the voltage level is selected to apply an electrical field of between about 0.5 MV/cm and about 20 MV/cm to dielectric liner  195 . An exemplary electrical field strength would be about 3 MV/cm or greater and is applied for a typical duration of about one second. During testing, trench  180  does not extend all the way through substrate  100 . 
     While in  FIG. 6 , the stress test has been illustrated as being performed after four wiring levels (not counting stack contact  200 ) have been completed, the stress test may be performed after formation of any wiring level by adjustments to the process flow described. However, it is preferred that conductor  195  not be wired to any other wires of the integrated circuit until after the high voltage stress test. 
     In  FIG. 7 , a dielectric layer  210  is formed on dielectric liner  190  and conductor  195 . A dual damascene wire  215 A is formed to wire stack  170 A and a damascene wire  205 B is formed to conductor  195 . As illustrated, wire  215 B does not contact wire stack  170 B. In one example, dielectric layer  210  comprises multiple dielectric layers. In one example, dielectric layer  210  comprises a layer of silicon nitride on dielectric liner  190  and conductor  195 , a layer of TEOS on the silicon nitride layer, and a layer of fluoro-TEOS (FTEOS) on the TEOS layer. 
     In  FIG. 8 , a backside grind followed by a substrate etch of substrate  100  has been performed to expose conductor  195 , followed by a deposition of a dielectric layer  220  (e.g., silicon nitride), followed by a CMP to expose a bottom surface  217  of conductor  195 . An electrically conductive layer  225  is optionally formed to contact bottom surface  217  of conductor  195 . Thus, a TSV  230  comprising dielectric liner  190 , conductor  190 , core  100 A and wire stack  170 B has been formed. Because core  100 A is isolated from substrate  100 , it does not matter if the integrity (defined supra) of the inner region  232  of dielectric liner  195  contacting core  100 A has been compromised by the stress test, because the outer region  233  of dielectric liner gas not been stressed and provides the isolation of TSV  230  from substrate  100 . Alternatively, wire  215 A and  215 B could be integrally formed to provide a direct electrical connection between TSV  230  and FET  105   
       FIGS. 9 ,  9 A and  9 B illustrate an alternative through-silicon-via according to an embodiment of the present invention. In  FIGS. 9 ,  9 A and  9 B the structure illustrated is fabricated and the stress testing is performed from the backside of the substrate after thinning the substrate as described supra. In  FIG. 9 , dielectric layer  235  is formed on the backside of substrate  100  and damascene wire  240 A and  240 B formed in dielectric layer  235 . Wire  240 A contacts conductor  195  and wire  240 B contacts core  100 A. The high voltage stress includes applying a direct current (DC) voltage between wire  240 A and wire  240 B and measuring the current flow. The current flow (if any) will be between the inner region of dielectric liner  190  between core  100 A and conductor  195  leaving the region of dielectric liner  195  between the rest of substrate  100  and conductor  195  unstressed. For a P-type substrate, the positive bias is applied to wire  240 B. For an N-type substrate, the positive bias is applied to wire  240 A. In one example, the voltage level is selected to apply an electrical field of between about 0.5 MV/cm and about 20 MV/cm to dielectric liner  195 . An exemplary electrical field strength would be about 3 MV/cm or greater and the field is applied for a duration of about one second. Thus a TSV  245  comprising dielectric liner  190  and electrical conductor  195  has been formed. Because core  100 A is isolated from substrate  100 , it does not matter if the integrity (defined supra) of the inner region  232  of dielectric liner  195  contacting core  100 A has been compromised by the stress test, because the outer region  233  of dielectric liner gas not been stressed and provides the isolation of TSV  245  from substrate  100 . 
       FIG. 9  is a sectional view through line  9 - 9  of  FIG. 9A  or alternatively through line  9 - 9  of  FIG. 9B . The difference between  FIGS. 9A and 9B  is a gap  250  is provided in wire  240 A for a wire  255  connecting wire  240 B to a pad  260 . In  FIG. 9B , wire  240 B, wire  255  and pad  260  are integrally formed. 
     In  FIG. 9 , the stress test has been illustrated as being performed on the grinded side (i.e., backside) of the substrate after four wiring levels have been completed on the non-grinded side (i.e., frontside) of the substrate. However, the stress test may be performed after formation of any wiring level by adjustments to the process flow described. It is preferred that conductor  195  not be wired to any other wires of the integrated circuit until after the high voltage stress test. It is also preferred that the stress test be performed after forming all wiring levels on the non-grinded surface and prior to forming terminal pads on the wires on the non-grinded surface of substrate  100 . 
     TSVs according the embodiments of the present invention may be used, after high-voltage stress testing, in functional circuits of integrated circuit chips that are shipped to customers. Alternatively, TSVs according the embodiments of the present invention may be used as dummy, stress test only structures, of integrated circuit chips that are shipped to customers. 
     While, TSVs according to embodiments of the present invention have been illustrated in  FIGS. 3A ,  6 A,  9 A and  9 B as having a circular perimeter when viewed from the top surface of the substrate, TSVs according to embodiments of the present invention may have oval, square, rectangular, polygon or irregular perimeters when viewed from the top surface of the substrate. 
     Thus, the embodiments of the present invention provide an integrated circuit chip TSV with a sacrificial dielectric liner that may be stress tested at high voltage and if the TSV passes the stress test, the integrated circuit chip may be shipped without wear out concerns. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. For example, silicon substrates may be replaced with other semiconductor substrates (e.g., SiGe) and TSV may then stand for “through-substrate-via). The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.