Abstract:
A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is related to co-pending U.S. patent application Ser. No. 09/758,792 entitled “Circuit Protection Implemented Using a Double Polysilicon Layer CMOS Process” filed on Jan. 11, 2001 by J. P. Baukus, Lap Wai Chow and W. C. Clark. 
         [0002]    This application is also related to U.S. patent application Ser. No. 10/637,848 entitled “Use of Silicon Block Process Step to Camouflage a False Transistor” filed on Aug. 7, 2003 by Lap Wai Chow, W. C. Clark, J. P. Baukus and G. Harbison (Now U.S. Pat. No. 6,979,606 issued Dec. 27, 2005), the disclosure of which is hereby incorporated herein by reference. 
     
     TECHNICAL FIELD 
       [0003]    The present invention relates to integrated circuits (ICs) and semiconductor devices in general and their methods of manufacture wherein the integrated circuits and semiconductor devices employ camouflaging techniques which make it difficult for the reverse engineer to discern how the semiconductor device functions. 
       RELATED ART 
       [0004]    The present invention is related to the following US patents by some of the same inventors as the present inventors: 
         [0000]    (1) U.S. Pat. Nos. 5,866,933; 5,783,375 and 6,294,816 teach connecting transistors in a CMOS circuit by implanted (and therefore hidden and buried) lines between the transistors. The implanted lines are formed by modifying the p+ and n+ source/drain masks. These implanted interconnections are used to make 3-input AND or OR circuits look substantially identical to the reverse engineer. Also, buried interconnects force the reverse engineer to examine the IC in greater depth to try to figure out the connectivity between transistors and hence their function.
 
(2) U.S. Pat. Nos. 5,783,846; 5,930,663 and 6,064,110 teach modifying the source/drain implant masks to provide a gap in the implanted connecting lines between transistors. The length of the gap being approximately the minimum feature size of the CMOS technology being used. If this gap is “filled” with one kind of implant, the line conducts; but if it is “filled” with another kind of implant, the line does not conduct. The intentional gaps are called “channel blocks.” The reverse engineer is forced to determine connectivity on the basis of resolving the implant type at the minimum feature size of the CMOS process being used.
 
(3) U.S. Pat. No. 6,117,762 teaches a method and an apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas are formed on a substrate and a silicide layer is formed over at least one active area of the semiconductor active areas and over a selected substrate area. The silicide layer connecting the at least one active area with another active area.
 
       BACKGROUND OF THE INVENTION 
       [0005]    The creation of complex integrated circuits and semiconductor devices can be an expensive undertaking because of the large number of hours of sophisticated engineering talent involved in designing such devices. Additionally, integrated circuits can include read only memories and/or EEPROMs into which software, in the form of firmware, is encoded. Further, integrated circuits are often used in applications involving the encryption of information. In order to keep the encrypted information confidential, devices should be protected from being reverse engineered. Thus, there can be a variety of reasons for protecting integrated circuits and other semiconductor devices from being reversed engineered. 
         [0006]    In order to keep the reverse engineer at bay, different techniques are known in the art to make integrated circuits more difficult to reverse engineer. One technique is to make the connections between transistors difficult to determine forcing the reverse engineer to perform a careful analysis of each transistor (in particular, each CMOS transistor pair for CMOS devices), and thwarting attempts to use automatic circuit and pattern recognition techniques in order to reverse engineer an integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to analyze each transistor carefully in a device can effectively frustrate the reverse engineer&#39;s ability to reverse engineer the device successfully. 
         [0007]    A conductive layer, such as silicide, is often used during the manufacture of semiconductor devices. In modern CMOS processing, especially with a minimum feature size below 0.5 μm, a silicide layer is utilized to improve the conductivity of gate, source and drain contacts. In accordance with typical design rules, any active region resulting in a source/drain region is often silicided. 
         [0008]    One reverse engineering technique involves de-layering the completed IC by means of chemical mechanical polishing (CMP) or other etching processes. The etching processes may, under some conditions, reveal the regions between where the silicide was formed on the substrate, and where it was not, i.e. the regions defined by the silicide block mask step and by regions where structures, such as a polysilicon gate, prevent the silicide layer from being deposited on the substrate. These regions may be revealed because, under some kinds of etches, there is an observable difference in topology due to different etching rates for silicided versus non-silicided silicon. The reverse engineer, by noting the silicided areas versus non-silicided areas, may make assumptions as to the function of the device. This information can then be stored into a database for automatic classification of other similar devices. 
         [0009]    Some methods of protecting against reverse engineering may be susceptible to discovery under some reverse engineering techniques, such as chemical-mechanical polishing (CMP) or other etching techniques. For example,  FIG. 1   a  depicts a possible top-down view of a false transistor FT made in accordance with U.S. patent application Ser. No. 09/758,792 after etching. During the manufacturing of the false transistor, and in accordance with normal design rules, the silicide block mask allows for a silicide layer  15 , see  FIG. 1   b , to be placed completely over the active regions  12 ,  16  in substrate  22 , and optionally over gate layer  14 . Gate layer  14  may be a polysilicon layer. During the CMP reverse engineering process, the gate layer  14  would be removed, thereby resulting in the top-down view as shown in  FIG. 1   a . As shown, the silicide layer edge  18  aligns with the gate edge  11 ,  13 , thus the reverse engineer only sees one line along the gate edge  11 ,  13 . 
         [0010]    The top-down view of the false transistor is different from a top-down view of a true transistor and as such, the difference may be a signature that the transistor is not a true transistor. 
         [0011]    For functional or true transistors, as shown in  FIGS. 2   a  and  2   b , the silicide layer edge  18 ′ is offset from the polysilicon gate layer  14  due to the presence of sidewall spacers  19  that are formed adjacent to gate layer  14 . A lightly doped density (LDD) implant  10  is typically formed after the formation of the gate layer  14  and before the formation of the sidewall spacers. After sidewall spacers  19  are formed, active areas  12 ,  16  are typically formed in the substrate. The formation of active areas  12 ,  16  saturate most of the LDD implant, so that only the portion of the LDD implant  10  that is under the sidewall spacers  19  effectively remains. A conductive layer, such as silicide  15 , is typically placed over the active areas  12 ,  16  and over the gate layer  14 . The sidewall spacers  19  prevent the silicide from being deposited upon the exposed substrate in those areas. Thus, the artifact edge  18 ′ is spaced from and lies mostly parallel with the edges  11 ,  13  of the gate layer  14  for a true transistor TT. Thus, from the examination of the top-down views of  FIGS. 1   a  and  2   a  the reverse engineer may be able to determine that a structure originally placed in the area was in fact a (i) false transistor FT meant to confuse the reverse engineer due to the absence of artifact edges  18 ′ lying spaced from and mostly parallel with edges  11 ,  13  of the polysilicon gate  14  or (ii) a true transistor TT. A reverse engineer could then program computer software to recognize the absence of artifact edges  18 ′ of the silicide layers lying separate from and being mostly parallel with the edges  11 ,  13  of the gate layer  14  as indications of false transistors FT among a plurality of true transistors TT formed on a single integrated circuit device or chip. 
         [0012]    It should be understood that although  FIG. 1   b  depicts active regions  12 ,  16  adjacent to the gate layer  14  and  FIG. 2   b  depicts LDD implants  10  adjacent to the gate layer  14 , it is extremely difficult, if not impossible, for the reverse engineer to determine a difference in both doping levels and doping types (n or p) between the LDD implant  10  and the active regions  12 ,  16 . 
         [0013]    Our U.S. patent application Ser. No. 10/637,848 teaches a semiconductor device and a method of manufacturing semiconductor devices that uses artifact edges to confuse the reverse engineer. Providing artifact edges that are not indicative of the actual device formed will further confuse the reverse engineer and result in incorrect conclusions as to the actual composition, and thus function, of the device. 
         [0014]    We have further developed the teachings about in order to allow LDD implants and, preferably in combination with judicious patterning of silicide layers, to interconnect (or not interconnect) active regions of different transistors in a way which is very apt to confuse the reverse engineer. This new technique can be used with the techniques disclosed in the related application to further confuse the reverse engineer. 
       SUMMARY OF THE INVENTION 
       [0015]    A technique is described by which connections between transistors (and more specifically between implanted active areas from which transistors are formed) in a CMOS logic circuit are produced in such a way that they are difficult to observe by a reverse engineer. In fact, the structure by which the connection is affected is a lightly doped density (LDD) implanted region between the active areas and the difficulty for the reverse engineer comes from two aspects of this invention and the structure described below. First, connections or disconnections can be made by the same structure by choosing either the “right” LDD implant or the “wrong” LDD implant depending upon the dopant type (n or p) used for the active areas. Because the dopant density of the LDD is so small, the reverse engineer cannot use typical reverse engineering techniques to determine when implants are in the substrate and what their polarity is. Second, the connections are not made via metal wiring above the substrate that is clearly visible to the reverse engineer, as a result etching to the surface is required. Because of the relatively small density of the LDD implant compared to the implant used in a normal source or drain active region, the connections made are more resistive than would be a by conductive metal wiring or by a heavier implant. As a result, the technique would preferentially be used to connect transistors that do not carry signal power, but rather are necessary for the logical performance of the circuit. There are many such connections in a typical IC and hence, using this invention, all or some of these “connections” can be made that they appear functionally ambiguous to the reverse engineer. 
         [0016]    In another aspect the present invention provide methods for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]      FIG. 1   a  depicts artifact edges of a silicide layer that the reverse engineer could see after all the metal and oxide layers have been removed from a false transistor; 
           [0018]      FIG. 1   b  depicts a cross-section view of the false transistor of  FIG. 1   a;    
           [0019]      FIG. 2   a  depicts prior art artifact edges of a silicide layer that the reverse engineer could see after all the metal and oxide layers have been removed from a true transistor; 
           [0020]      FIG. 2   b  depicts a cross-section view of the prior art true transistor of  FIG. 2   a;    
           [0021]      FIG. 3  depicts a structure to provide programmable connection or isolation between two spaced apart active areas, denoted by the active regions on this figure; and 
           [0022]      FIG. 4  is a plan view of a portion of a semiconductor chip diagrammatically showing a plurality of transistors formed thereon with programmable connection or isolation between the active regions thereof; 
           [0023]      FIG. 5   a  depicts a structure to provide connection or isolation between an implanted active area of a transistor (the N+active region in this figure) and V ss ; 
           [0024]      FIG. 5   b  is similar to the embodiment of  FIG. 4   a , but this embodiment depicts a structure to provide connection or isolation between an implanted active area of a transistor (the P+ active region in this figure) and V dd . 
       
    
    
     DETAILED DESCRIPTION 
       [0025]    The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which a two embodiments of the invention are shown. This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. 
         [0026]    Many methods of manufacturing semiconductor devices are well known in the art. The following discussion focuses on modifying a conductive layer block mask used during the manufacture of semiconductor devices in order to confuse the reverse engineer. The discussion is not intended to provide all of the semiconductor manufacturing details, which are well known in the art. Moreover, the following detailed description discusses the formation of implanted regions in a semiconductor substrate. Those skilled in the art will appreciate that regions in a semiconductor substrate formed by adding dopants into the substrate can be formed by a number of techniques, including implantation and diffusion. In terms of the present disclosure, implantation is the preferred technique, but those skilled in the art should realize that other regions forming techniques may alternatively be used if desired. 
         [0027]    In order to confuse the reverse engineer, the placement of an artifact edge of a silicide layer that would be seen when a reverse engineer examines devices manufactured with other reverse-engineering-detection-prevention techniques can be changed, as described in the patent application referred to above. In reverse-engineering-detection-prevention techniques, false, or non-operational, transistors may be used along with true, or operational, transistors. Some false transistors are manufactured without sidewall spacers, see  FIG. 1   b , while corresponding true transistors may well have sidewall spacers  19 , as shown in  FIG. 2   b . Depending of the conductivity type of device&#39;s implanted source and drain, a well  20  may be formed as is well known in the art. The doped regions  10  under the side wall spacers  19  are referred to as Lightly Doped Density (LDD) regions since the level of doping is considerable lighter compared to the level of doping in source and drain regions  12 ,  16 . From a top-down view, and when most reverse engineering techniques are used, these false transistors look the same as operational transistors. However, using some reverse engineering techniques, such as chemical mechanical polishing (CMP) or other etching processes, the artifact edges of the silicide layer may be exposed and thereby give away the reverse-engineering-detection-prevention technique being utilized (that this, the reverse engineer discovers how to detect the presence of false transistors). As shown in  FIG. 1   a , for some false transistors, the artifact edges  18  of a silicide layer  15  coincide with the edges  11 ,  13  of the gate layer  14 . However, with operational transistors as shown in  FIG. 2   a , the artifact edges  18 ′ of a silicide layer  15  are offset from the edges  11 ,  13  of the gate layer  14  by the width of sidewall spacers  19 . 
         [0028]    Techniques for locating the artifact edges on non-operational transistors such that they appear to a reverse engineer as operational transistors are discussed in our co-pending pending U.S. patent application Ser. No. 10/637,848 discussed above. 
         [0029]    The presently disclosed technique also allows for connections between transistors (and more specifically between implanted active areas from which transistors are formed) in a CMOS logic circuit to be formed in such a way that they are difficult to observe by a reverse engineer. In  FIGS. 3 ,  5   a  and  5   b , two active regions  12 ′ and  16  are depicted. Each active region  12 ′,  16  is associated with a different transistor device. It is assumed here that active region  16  corresponds to either an active region of a functional or a non-functional transistor device, such as, for example, the transistors shown in  FIGS. 1   b  and  2   b .  FIG. 3  corresponds to a section view taken along line A-A in  FIG. 1   b  or  2   b . The other active region  12 ′ is an active region of a second transistor device, either operational (and hence a true transistor) or non-operational (and hence a false transistor). Each transistor has its own gate region, shown in  FIG. 1   b  (if a false transistor is utilized) or  FIG. 2   b  (if a true transistor is utilized). The gate regions can be oriented above and/or below the major surface of the substrate shown in the section view of  FIG. 3  or the gate regions could be arranged outboard of the active regions which the location where field oxide (FO) is presently shown, if desired. Persons skilled in the art should be able to appropriately position gate regions next to the depicted active regions  12 ,  16 , either as shown or as described. 
         [0030]    The structure by which the connection is effected between the two active regions is a lightly doped density (LDD) region or channel  21  disposed between the active regions  12 ′,  16 . Channel  21  is preferably formed using semiconductor implantation techniques, but other well-known semiconductor fabrication techniques, known to those skilled in the art may, be used instead to form regions or channel  21  and indeed to form active regions  12 ′,  16  as well. 
         [0031]    The lightly doped density (LDD) region or channel  21  is preferably formed at the same time and with the same dopant concentration and depth as LDD region  10 , which is also preferably formed by the same fabrication technique used to form region or channel  21 , such as implantation, but its polarity will depend on whether it is formed at the same time as the LDD regions  10  of a (i) n-type or (ii) p-type transistor. As such, no additional processing should be needed to be added to conventional CMOS processing in order to implement this technology since the LDD regions  10  of both (i) n-type and (ii) p-type transistors are formed when making CMOS devices. Therefore the polarity of the region or channel  21  can be programmed as desired by selecting whether region or channel  21  has n-type or p-type doping. 
         [0032]    The difficulty for the reverse engineer comes from two aspects of this invention and this structure. First, connections or disconnections can be made by the same structure  21  by choosing either the “right” LDD implant conductivity type or the “wrong” LDD implant conductivity type depending upon the dopant type (n or p) used for the connected active areas. For example, if active regions  12 ′ and  16  are n-type, then a n-type LDD channel  21  interconnecting them will form an electrical conduction path between regions  12 ′ and  16 , whereas if active regions  12 ′ and  16  are again n-type but region  21  is formed using a dopant creating p-type conductivity, then no electrical conduction channel is then formed between regions  12 ′ and  16 . The dopant density of the LDD is sufficiently small compared to the doses normally used in the source and/or drain active regions, that the reverse engineer cannot easily use his or her conventional reverse engineering techniques to determine both (i) where LDD regions and/or channels  21  occur in the substrate and (ii) what their conductivity type is. Since channel  21  is formed when other LDD regions  10  are formed, it has the same relatively low dopant density and the reverse engineer will have some difficulty in determining whether channel  21  even exists and even more difficulty in determining whether it is conducting or non-conducting. Second, the connections between regions  12 ′ and  16  are not made via a conventional metal layer above the substrate (that is clearly visible to the reverse engineer), and therefore etching of the surface is required by the reverse engineer to “see” connections formed by channels  21 . Since the channels  21  preferably have LDD doping levels they are hard to even see using etching techniques. And since the channels  21  preferably have LDD doping levels their polarity (n-type or p-type) is even more difficult to determined. And if the reverse engineer has to find thousands of channels  21  on a given chip and then try to determine their polarities, then he or she was a major, time-consuming problem to solve. 
         [0033]    Because of the preferred relatively small concentration of the LDD impurity dosage (used to make the LDD region n-type or p-type) compared to the impurity dosage used in a typical source or drain active region, the connections  21  made (when they are of the same conductivity type as the active regions they are joining) are more resistive than would be by conductive metal wiring or by a heavier dopant concentration. As a result, this technique is preferably be used to connect active areas of transistors that do not carry signal power (like a RF power transistor, for example), but rather are preferably used to interconnect low power transistors used, for example, in the logical operation of an intended circuit. There are many such low power connections in a typical IC and hence, using this invention, all or some of these “connections” can be made that they appear functionally ambiguous to the reverse engineer. 
         [0034]    The designer who utilizes region or channel  21  has the following options: 
         [0035]    (i) to make a connection between two N+ regions  12 ′,  16 , the implant  21  would be a n-type LDD implant; 
         [0036]    (ii) to instead isolate the two N+ regions  12 ′,  16 , the one could provide no channel  21  and instead rely on the p-well  20  or provide a p-type LDD dose to channel  21 , depending on the details of the process and the implant levels available. 
         [0037]    The design constraints for L 1  and L 2  are as follows: 
         [0038]    (i) L 1 , the distance between the active regions of neighboring transistors (see  FIG. 3 ), should preferably be to be as small as reasonably possible (in order to reduce the resistance of the channel  21 ), the value of L 1  typically being specified by the design rules for the CMOS fabrication process being used. 
         [0039]    (ii) L 2  is the minimum silicide block overlap S/D implant (i.e. the implants  12 ′,  16  in this figure) to ensure there is no short from the silicide  15  to either the channel  21 , the substrate  22  or the well  20 , as the case may be, due to mask alignment errors. 
         [0040]    If the channel  21  is intended as being a false, non-conducting channel, then allowing silicide overlay it (at the points where it meets the active regions  12 ′,  16 ) would bring channel  21  into conduction when it is desired that it be non-conducting. If the channel  21  is supposed to be conducting, then allowing the silicide to overlay does not adversely affect its conductivity, but since the desire is to confuse the reverse engineer, the silicide is preferably spaced from the channels  21  (for both conducting and non-conducting channels) at least one end of the channel so that both conducting and non-conducting channels  21  would be conducting or non-conducting as a function of the conductivity type of the channel  21  as opposed to the configuration of the overlying silicide layer (since the configuration of the overlying silicide layer is more easily detected by the reverse engineer than is the existence and conductivity type—polarity—of the channels  21 . 
         [0041]    The distance L 2  is usually larger than a typical sidewall spacing thickness. 
         [0042]    The discussion above regarding  FIG. 3  is with reference to a n-type structure with a p-type well  20 . A p-type structure would use dopings of the opposite conductivity type (n-type for the source and drain and their associate LDD regions, if used), but otherwise the same structural arrangements would apply. The use of well  20  in substrate  22  may be optional as is well known in the art. Also, while the active regions  12 ′,  16  and the well region  20  are preferably formed using implantation techniques, it is be understood that the present invention does not necessarily require the use of implantation techniques to form those regions or any of the regions and channels depicted as other techniques may be used to add dopant to semiconductor materials. Typically the substrate may be silicon, but the techniques disclosed herein are not limited to silicon based semiconductor material technology. 
         [0043]      FIG. 4  depicts who this technology can be used in designing and/or making a semiconductor chip which is resistance to reverse engineering.  FIG. 4  depicts a plurality of true transistors TT formed in or on substrate  22 . The true transistors may form CMOS devices, that is, they may comprises both N-type true transistors and P-type true transistors. Optionally, false transistors FT may be formed on or in substrate  22  in order to try to confuse the reverse engineer as taught by U.S. patent application Ser. No. 09/758,792 mentioned above. The transistors (TT and also FT, if utilized) are interconnected to form an operational circuit. The interconnections are preferably formed by utilizing the afore-described channels  21  to connect nearby or adjacent active regions of the true transistors (and also with active regions of false transistors should they be used). The previously described, the channels  21  can be conducting or non-conducting. Conducting channels  21 C and true transistors TT are used to help form the aforementioned operational circuit. Non-conducting channels  21 NC (and false transistors FT, if utilized) are used to confuse the reverse engineer by making it appear to the reverse engineer that there exist additional functional conducting channels  21  (and possibly additional functional transistors) when those additional channels (and additional transistors, if used) are in fact non-conducting and thus do not adversely influence the proper operation of the circuit. Of course, if the reverse engineer cannot easily distinguish between a conducting channel  21 C and a non-conducting channel  21 NC, then the reverse engineer is presented with a daunting problem in figuring out how the circuit works, particularly if the chip has thousands or even millions of true transistors TT with many, many conducting channel connections  21 . Then, you add some optional false transistors FT to the mix, and the result is a very confused reverse engineer. 
         [0044]    In  FIG. 4  only ten transistors are shown on a chip substrate  22  and they are shown connected in a purely arbitrary fashion with channels  21 . The conducting channels  21 C are depicted in solid lines and would preferably form an operational circuit. The non conducting channels  21 NC are shown in dashed lines and would be present only to confuse the reverse engineer. 
         [0045]    In order to make a circuit truly operational, chances are that many transistor interconnects will need to be provided and, due to topology limitations, some of the interconnects will be provided by conventional imaged metal layers. But the use of conventional imaged metal layers for transistor interconnects should preferably be minimized since it is a fairly easy task for the reverse engineer to work out such metal interconnects on a semiconductor chip. Let the reverse engineer toil away instead trying to figure out which channels  21  are conducting (and therefore real) and which channels  21  are non-conducting (and therefore fake), since they all look the same to the reverse engineer who sees the chip in a top down view. 
         [0046]    The above-discussed embodiment demonstrates one technique for providing ambiguity in interconnects between active regions of spaced apart transistors. This technology can be used in other connection embodiments, such as a connection of an active region to either V ss  or V dd . 
         [0047]    The channels  21 , as noted provide desirable ambiguity, and similar structures can be fabricated with ambiguity of connection or isolation to either V ss  or V dd , for example. See  FIGS. 5   a  and  5   b . The these figures the LDD doped region or charmel  21 : 
         [0048]    (i) can be a N-type LDD (NLDD) doped channel to connect an active region  12 ,  16  to V ss  in a n-type structure as shown in  FIG. 5   a , or 
         [0049]    (ii) the opposite, i.e. a P-type LDD (PLDD) doped channel to isolate an active region  12 ,  16  from V DD  as shown in  FIG. 5   b.    
         [0050]    The design rules for the fabrication process determine the dimensions noted below, i.e. 
         [0051]    (i) L 3 =the minimum silicide block opening which consists of one part within the active region that prevents leakage plus another part outside the active region where the distance is the possible mask alignment error for the process utilized; 
         [0052]    (ii) L 4 =the minimum N+ to P+ separation within the same region of active area—i.e. a breakdown consideration; 
         [0053]    (iii) L 2 =specifies the mask alignment error to insure that active region (which could be N+ type) is not shorted to the well (which would then be p-type). 
         [0054]    As noted above, a reverse engineer uses an etch process to try to differentiate the polarity of doped areas, but, more accurately, the etch process helps determine an edge between two different doped regions. This difference may be either in concentration or polarity (e.g., a N+active region compared to a P-type well or other LDD regions). The difference will be seen due to the difference in the etch rate between the differently doped regions. Since the LDD implant is relatively low in density compared to the active region implant, the edge between these two regions will show up in the etch. That is, the structure in  FIG. 3  will have a similar after-etch image independent of whether the structure forms is a true connection or a false connection (with channel  21  is doped with either n-type or p-type LDD dopant in the case of a n-type structure). Hence, using the structure of  FIG. 3  in a circuit can make it difficult for the reverse engineer to determine the real connectivity of channel  21 , particularly if a mixture of conducting and non-conducting LDD channels  21  are formed on a device having many instances of the structure shown in  FIG. 3 , some with the “correct” conductivity type in order to form a conducting channel and some with the “wrong” conductivity type in order to form a pseudo, non-conducting channel, which looks like a real conducting channel to the reverse engineer, but it is not conducting. 
         [0055]    Using the LDD doping levels in the channel  21  provides the connection ambiguity discussed above. In contrast, using a full density doping in channel  21  would not provide the highly desirable ambiguity that fends off the reverse engineer because an LDD region is more ambiguous after etching where a stain may be used by the reverse engineer to try to determine the conductivity type of the regions and a lower density dosage gives a weaker response to stain and thus it is more difficult to distinguish n-type LLD regions from p-type LLD regions compared to distinguishing full density N+ and P+ regions. Also, full density regions butted together provide poor isolation as the diode junction is worse (it has a lower breakdown voltage) compared to the full density to LDD junction which occurs in the embodiment of  FIG. 3  between the active regions and a non-conducting LDD channel  21 . So the use of full density channels would be undesirable not only because their function (or lack of function) can be more easily discovered by a reverse engineer, but also because they can cause possible breakdown problems. 
         [0056]    Having described the invention in connection with certain preferred embodiments thereof, modification will now certainly suggest itself to those skilled in the art. As such, the invention is not to be limited to the disclosed embodiments, except as is specifically required by the appended claims.