Abstract:
An integrator circuit with multiple time window functions for carrying out a plurality of integration operations in parallel, each integration operation being carried out in a coherent manner over a sequence of time windows including at least one such window. The circuit includes a plurality of integration paths each corresponding to an integration operation. The integration paths share a same voltage/current converter and a same first switching mechanism for switching a signal to be integrated at an input of the converter, each integration path further including at least one integration capacitor mounted in counter-reaction to a functional amplifier and receiving a resulting current via a second switching mechanism for selecting the path.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates to the field of integrator circuits with multiple time window functions. It is in particular applicable in UWB telecommunications systems of the impulse type and pulsed wave radar systems. 
       BACKGROUND OF THE INVENTION 
       [0002]    Ultra wide band (UWB) telecommunications systems of the impulse type are well known from the prior art. In such a system, a symbol emitted by or intended for a given user is sent using a sequence of ultra-short waves, in the vicinity of a nanosecond or a hundredth of a picosecond. 
         [0003]      FIG. 1  diagrammatically illustrates a user&#39;s signal corresponding to a given information symbol. This signal is made up of a temporal sequence of N f  frames, each frame itself being divided into N c  elementary intervals also called chip time. 
         [0004]    The base signal relative to a user k, called TH-UWB (Time Hopped UWB) signal, can be expressed generally by: 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       s 
                       k 
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     
                       ∑ 
                       
                         n 
                         = 
                         0 
                       
                       
                         
                           N 
                           f 
                         
                         - 
                         1 
                       
                     
                      
                     
                       p 
                        
                       
                         ( 
                         
                           t 
                           - 
                           
                             nT 
                             f 
                           
                           - 
                           
                             
                               
                                 c 
                                 k 
                               
                                
                               
                                 ( 
                                 n 
                                 ) 
                               
                             
                              
                             
                               T 
                               c 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0005]    where p(t) is the shape of the elementary pulse, T c  is a chip time, T f  is the length of a frame with N f =N c T c  where N c  is the number of chips in an interval, the time sequence having total length T s =N f T f  where N f  is the number of frames in the sequence. The length τ of the elementary pulse is chosen to be smaller than the chip time. The sequence c k (n) for n=0, . . . , N s −1 defines the time hop code for the user k. The sequences of time hops are chosen so as to minimize the number of collisions between impulses belonging to time hop sequences relative to different users. 
         [0006]    On the transmitter side, the user&#39;s base signal is modulated by the information symbol, for example using pulse position modulation (PPM): 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       s 
                       k 
                     
                      
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     
                       ∑ 
                       
                         n 
                         = 
                         0 
                       
                       
                         
                           N 
                           f 
                         
                         - 
                         1 
                       
                     
                      
                     
                       p 
                        
                       
                         ( 
                         
                           t 
                           - 
                           
                             nT 
                             f 
                           
                           - 
                           
                             
                               
                                 c 
                                 k 
                               
                                
                               
                                 ( 
                                 n 
                                 ) 
                               
                             
                              
                             
                               T 
                               c 
                             
                           
                           - 
                           
                             m 
                              
                             
                                 
                             
                              
                             ɛ 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0007]    where ε is a modulation delay substantially shorter than the chip time T c  and m=0, . . . , M−1 is position M-PPM area. 
         [0008]    On the receiver side, the received signal is the subject of multiple time window integration. The positions of the time windows depend on the user one wishes to receive.  FIG. 1B  shows the multiple time window signal associated with the user k. The time windows here are calibrated on the positions of the time hops c k (n). 
         [0009]    In general, for a given user k, if the propagation delay is subtracted, the receiver performs an integration in some time windows of the received signal r k (t), or in time windows: 
         [0000]    w(t−nT f −c k (n)T c ), n=0, . . . , N f −1 for the first modulation position, or I 0   k =∫r k (t)w(t−nT f −c k (n)T c )dt,
 
w(t−nT f −c k (n)T c −mε), n=0, . . . , N f −1 for the (m+1) th  modulation position, or I m   k =∫r k (t)w(t−nT f −c k (n)T c −mε)dt,
 
w(t−nT f −c k (n)T c −(M−1)ε), n=0, . . . , N f −1 for the last modulation position, or:
 
         [0000]        I   M-1   k   =∫r   k ( t ) w ( t−nT   f   −c   k ( n ) T   c −( M− 1)ε) dt,  
 
         [0000]    where w(t) is a bounded support function with a width slightly larger than the duration τ of the pulse p(t). 
         [0010]    The receiver estimates the modulation position and therefore the information symbol sent, by comparing the integrated values I m   k  or: 
         [0000]    
       
         
           
             
               
                 
                   
                     m 
                     ^ 
                   
                   = 
                   
                     
                       argmax 
                       m 
                     
                      
                     
                       ( 
                       
                         I 
                         m 
                         k 
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0011]    Multiple time window integration of a signal r(t) generally refers to a coherent integration operation over a plurality N of disjointed time windows: 
         [0000]    
       
         
           
             
               
                 
                   
                     I 
                     s 
                   
                   = 
                   
                     ∫ 
                     
                       
                         r 
                          
                         
                           ( 
                           t 
                           ) 
                         
                       
                        
                       
                         
                           ∑ 
                           
                             n 
                             = 
                             0 
                           
                           
                             N 
                             - 
                             1 
                           
                         
                          
                         
                           
                             
                               w 
                               n 
                             
                              
                             
                               ( 
                               t 
                               ) 
                             
                           
                            
                           
                              
                             t 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0000]    where w n (t), n=0, . . . , N−1, are bounded and disjointed support functions. It will be noted that in the aforementioned example, each of the values m=0, . . . , M−1 is obtained through a multiple time window integration on N f  windows. 
         [0012]    Multiple time window integration is also used in pulsed wave radar receivers. Indeed, to determine whether a target is present in a given range bin, the receiver integrates the received signal, after having demodulated it if applicable, in a time window. In order to improve the signal to noise ratio, it is known to integrate the received radar signal coherently in a plurality of time windows spaced out over the recurrence period of the radar 1/PRF, where PRF (Pulse Recurrence Frequency) is the recurrence frequency of the radar. 
         [0013]    A first known example of a multiple time window integrator circuit is shown in  FIG. 2A . 
         [0014]    The circuit  200  comprises a plurality of window switches  211 ,  212 ,  213 ,  214 , a voltage/current conversion module  220 , also called transconductance block, converting the differential input voltage into a proportional current, a functional amplifier  230 , two integration capacitors  241  and  242 , mounted in counter-reaction between the differential outputs and inputs of the op-amp. The integrated signal appears in differential form between the outputs V out   +  and V out   −  of the integrator circuit. Two switches  251  and  252 , respectively mounted in parallel on the two integration capacitors  241  and  242 , ensure that the integrator is reset. 
         [0015]    The voltage signal to be integrated is applied differentially between the inputs V in   +  and V in   −  of the integrator circuit. This signal is switched by the switches  211  and  213 , by a multiple window logic signal 
         [0000]    
       
         
           
             
               w 
                
               
                 ( 
                 t 
                 ) 
               
             
             = 
             
               
                 ∑ 
                 
                   n 
                   = 
                   0 
                 
                 
                   N 
                   - 
                   1 
                 
               
                
               
                 
                   w 
                   n 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
             
           
         
       
     
         [0000]    towards the differential inputs of the transconductance module  220 . 
         [0016]    One example of a multiple window logic signal w(t) has already been shown in  FIG. 1B . Each time window w n (t) has a bounded support A n , for example w n =1 if tεA n  and w n (t)=0 otherwise. The time supports A n  are disjointed and distributed over time uniformly (example of the aforementioned radar receiver) or non-uniformly (example of the aforementioned TH-UWB receiver). 
         [0017]    The complementary logic signal  w (t) switches the inputs of the transconductance module over a same reference voltage V ref . Thus, outside the windows w n (t) one ensures that a null differential voltage is applied to the input of the module  220 . The capacitors  241  and  242  integrate the output currents of the module  220 . The output voltages V out   +  and V out   −  are such that at the end of the multiple window function, V out   + −V out   −  represents a coherent integration of the input signal on the windows w n (t), or: V out   + −V out   − =∫α(V in   + −V in   − )w(t)dt where α is a constant that depends on the circuit. 
         [0018]    The integrated value is reset by short circuiting the capacitors  241  and  242 . 
         [0019]    The integrator circuit illustrated in  FIG. 2A  has a high output impedance and good performance in terms of bandwidth and gain control. 
         [0020]    A second example of an integrator circuit with multiple time window functions is shown in  FIG. 2B . Identical elements bear the same references as in  FIG. 2A . Unlike the circuit from  FIG. 2A , the integrator circuit of  FIG. 2B  has a single-pole output configuration. This configuration makes it possible to eliminate a counter-reaction control loop with a shared mode and therefore to reduce the consumption of the circuit while increasing its bandwidth. To preserve the symmetry of the assembly, in particular to balance drains during switching, the capacitor  241  is, however, kept as well as its associated reset switch  251 . 
         [0021]    The integrator circuits of  FIGS. 2A and 2B  do not make it possible to perform, in parallel, a plurality of multiple window integration operations. For example, such an integrator circuit does not make it possible to obtain, in parallel, the values I m   k  corresponding to the different positions PPM, m=0, . . . , M−1 of a TH-UWB system or to perform a coherent integration for different range bins in a pulsed wave radar system. 
         [0022]    A first solution to perform parallel integration operations consists of providing as many integrator circuits as integration operations. For example, in the case of the TH-UWB telecommunication system described above, M integrator circuits could provide, in parallel, the values I m   k  for the M modulation positions, m=0, . . . , M−1. Similarly, K parallel integrator circuits can provide integration results for K distinct users. 
         [0023]    This solution is not, however, fully satisfactory inasmuch as the integrators can have a dispersion of their characteristics, for example the transconductance gain of the module  220  or the capacitor values of  241  and  242 , which can lead to different integration constants α and therefore erroneous estimates (e.g. an erroneous estimate {circumflex over (m)}). Furthermore, the multiplication of the integrators causes a greater power consumption. 
         [0024]    The problem at the root of the invention is therefore to propose an integrator circuit with a multiple time window function, capable of carrying out a plurality of parallel integration operations, while guaranteeing good precision and low consumption. 
       BRIEF DESCRIPTION OF THE INVENTION 
       [0025]    The present invention is defined by an integrator circuit with multiple time window functions for carrying out a plurality of integration operations in parallel, each integration operation being carried out in a coherent manner over a sequence of time windows including at least one such window, said circuit comprising a plurality of integration paths each corresponding to an integration operation. Said integration paths share a same voltage/current converter and same first switching means for switching the signal to be integrated at the input of said converter, each integration path further including at least one integration capacitor mounted in counter-reaction to a functional amplifier and receiving the resulting current via second switching means for selecting said path. 
         [0026]    Advantageously, the integrator circuit also comprises three switching means adapted to transferring the integrated charge in each integration capacitor towards a corresponding storage capacitor, when said plurality of integration operations is finished. 
         [0027]    The integrator circuit can also comprise a fourth switching means to switch the voltages at the terminals of said storage capacitors towards the output of the integrator circuit, after the transfer of charges from the integration capacitors to the corresponding storage capacitors has been done. 
         [0028]    Preferably, the first switching means are controlled by a first control signal obtained using an OR logic of the path signals, each path signal having a high logic level during the time windows of that path and a low logic level outside these windows. 
         [0029]    According to a first alternative, said converter has a differential input and the first switching means applies the signal to be integrated between the input terminals of said converter when the first control signal is at a high logic level and a reference voltage at each of these terminals when it is at a low logic level. 
         [0030]    According to a second alternative, said converter has a single-pole input and the first switching means applies the signal to be integrated to the input terminal of said converter, when the first control signal is at a high logic level, and a reference voltage at said terminal when it is at a low logic level. 
         [0031]    According to a first embodiment, said integration paths share the same functional amplifier, the inputs of said amplifier respectively being connected to the outputs of said converter, and each path comprises a reference capacitor disposed between a reference voltage and a first input of the functional amplifier as well as an integration capacitor mounted in counter-reaction between the output of the functional amplifier and its second input. 
         [0032]    The second switching means is then advantageously controlled by a path selection signal, 
         [0033]    and connects, when this selection signal is at a high logic level:
       a first terminal of the reference capacitor to the reference voltage and the second terminal of said capacitor to the first input of the functional amplifier;   a first terminal of the integration capacitor to the output of the functional amplifier and the second terminal of this capacitor to the second input of the functional amplifier;       
 
         [0036]    and, when the selection signal is at a low logic level:
       disconnects the first terminal of the reference capacitor from the reference voltage and connects the second terminal of this capacitor to the reference voltage;   disconnects the first terminal of the integration capacitor from the output of the functional amplifier and connects the second terminal of this capacitor to the reference voltage.       
 
         [0039]    The integrator circuit advantageously comprises reset means adapted to applying said reference voltage simultaneously to the first and second terminals of the reference capacitor and to the first and second terminals of the integration capacitor when a reset is done. 
         [0040]    The storage capacitors are typically mounted in parallel at the output of the functional amplifier, each storage capacitor having a first terminal connected to said output via the third switching means and a second terminal connected to said reference voltage. Preferably, said first terminals of the storage capacitors are also connected to the output of the integrator circuit via the fourth switching means. 
         [0041]    According to one alternative of the first embodiment, said integration paths share the same functional amplifier, the inputs of said amplifier respectively being connected to the outputs of said converter, and each path comprises a first integration capacitor disposed in counter-reaction between a first output and a first input of the functional amplifier as well as a second integration capacitor disposed in counter-reaction between a second output and a second input of the functional amplifier. 
         [0042]    The second switching means is advantageously controlled by a path selection signal, and 
         [0043]    connects, when this selection signal is at a high logic level:
       a first terminal of the first integration capacitor to the first output of the functional amplifier and the second terminal of this capacitor to the first input of the functional amplifier;   a first terminal of the second integration capacitor to the second output of the functional amplifier and the second terminal of this capacitor to the second input of the functional amplifier; and       
 
         [0046]    when the selection signal is at a low logic level:
       disconnects the first terminal of the first integration capacitor from the first output of the functional amplifier and connects the second terminal of this capacitor to the reference voltage;   disconnects the first terminal of the second integration capacitor from the second output of the functional amplifier and connects the second terminal of this capacitor to the reference voltage.       
 
         [0049]    The integrator circuit can also comprise reset means adapted to apply said reference voltage simultaneously to the first and second terminals of the first integration capacitor and the first and second terminals of the second integration capacitor when a reset is done. 
         [0050]    Typically, the storage capacitors are mounted in parallel between the first and second outputs of the functional amplifier, each storage capacitor having a first terminal and a second terminal respectively connected to the first and second outputs of the functional amplifier via the third switching means. Preferably, said first terminals of the storage capacitors are connected to a first output of the integrator circuit and said second terminals of the storage capacitors are connected to a second output of the integrator circuit, via the fourth switching means. 
         [0051]    According to a second embodiment, each integration path comprises a functional amplifier, the inputs of said amplifier respectively being connected to the outputs of said converter via the second switching means, a reference capacitor disposed between a reference voltage and a first input of the functional amplifier as well as an integration capacitor disposed in counter-reaction between the output of the functional amplifier and its second input. 
         [0052]    The second switching means is then advantageously controlled by a path selection signal and, for each path, it connects and disconnects, when this selection signal is at a high logic level and a low logic level, respectively, the outputs of the converter to the inputs of the functional amplifier. 
         [0053]    The integrator circuit can also comprise reset means, adapted to apply said reference voltage simultaneously to the first and second terminals of the reference capacitor and to the first and second terminals of the integration capacitor, when a reset is done. 
         [0054]    Typically, the integrator circuit comprises, for each path, a storage capacitor having a first terminal connected to the output of the functional amplifier, via the third switching means, and a second terminal connected to said reference voltage. Preferably, said first terminal of the storage capacitor is also connected to the output of the integrator circuit via the fourth switching means. 
         [0055]    According to one alternative of the second embodiment, each integration path comprises a functional amplifier, the inputs of said amplifier being respectively connected to the outputs of said converter via the second switching means, a first integration capacitor mounted in counter-reaction between a first output and a first input of the functional amplifier as well as a second integration capacitor mounted in counter-reaction between a second output of the functional amplifier and its second input. 
         [0056]    The second switching means is advantageously controlled by a path selection signal and, for each path, it connects and disconnects when this selection signal is at a high logic level and at a low level, respectively, the outputs of the converter to the inputs of the functional amplifier. 
         [0057]    The integrator circuit can also comprise, for each path, reset means, adapted to apply said reference voltage simultaneously to the first and second terminals of the first integration capacitor as well as the first and second terminals of the second integration capacitor, when a reset is done. 
         [0058]    Typically, the integrator circuit comprises, for each path, a storage capacitor having a first terminal connected to the first output of the functional amplifier and a second terminal connected to its second output, via the third switching means. Preferably, said first and second terminals of the storage capacitor are also connected via the fourth switching means, respectively to a first output and to a second output of the integrator circuit. 
         [0059]    According to a third embodiment, said integration paths are distributed in a plurality of subassemblies and the second switching means comprises a first rank second means for selecting a subassembly of paths among said plurality of subassemblies, and second rank second means for selecting a path within a subassembly, and 
         [0060]    each subassembly of paths comprises a functional amplifier, the inputs of said amplifier respectively being connected to the outputs of said converter via the first rank second switching means; 
         [0061]    the paths of a subassembly sharing the functional amplifier relative to this subassembly, each path of said subassembly comprising a reference capacitor disposed between a reference voltage and a first input of said amplifier as well as an integration capacitor mounted in counter-reaction between the output of said amplifier and its second input. 
         [0062]    According to one alternative of the third embodiment, said integration paths are distributed in a plurality of subassemblies and the second switching means comprises a first rank second means for selecting a subassembly of paths among said plurality of subassemblies and a second rank second means for selecting a path within a subassembly, and 
         [0063]    each subassembly of paths comprises a functional amplifier, the inputs of said amplifier being respectively connected to the outputs of said converter via the first rank second switching means, 
         [0064]    the paths of a subassembly share the functional amplifier relative to that subassembly, each path of said subassembly comprising a first integration capacitor mounted in counter-reaction between a first output and a first input of this amplifier as well as a second integration capacitor mounted in counter-reaction between a second output and its second input. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0065]    Other features and advantages of the invention will appear upon reading one preferred embodiment of the invention done in reference to the appended figures in which: 
           [0066]      FIG. 1A  shows an example of a user signal in a UWB telecommunications system; 
           [0067]      FIG. 1B  shows an example of a multiple time window function for receiving the user signal of  FIG. 1A ; 
           [0068]      FIGS. 2A and 2B  show two examples of an integrator circuit with time window functions known from the state of the art; 
           [0069]      FIG. 3  diagrammatically illustrates an integrator circuit with multiple time window functions according to a first embodiment of the invention; 
           [0070]      FIG. 3A  shows the structure of a battery of integration capacitors used in the circuit of  FIG. 3 ; 
           [0071]      FIG. 3B  provides an example of an operating chronogram of the integrator circuit of  FIG. 3 ; 
           [0072]      FIGS. 4 to 6  respectively show first, second, and third alternative embodiments of the integrator circuit of  FIG. 3 ; 
           [0073]      FIG. 7  diagrammatically illustrates an integrator circuit with multiple time window functions according to a second embodiment of the invention; 
           [0074]      FIG. 7A  shows the structure of a module used in the circuit of  FIG. 7 ; 
           [0075]      FIG. 7B  shows an operating chronogram of the integrator circuit of  FIG. 7 ; 
           [0076]      FIG. 8  shows a first alternative embodiment of the integrator circuit of  FIG. 7 ; 
           [0077]      FIG. 8A  shows the structure of a module used in the circuit of  FIG. 8 ; 
           [0078]      FIGS. 9 and 10  respectively show second and third embodiments of the integrator circuit of  FIG. 7 ; 
           [0079]      FIG. 11  diagrammatically illustrates an integrator circuit with multiple time window functions according to a third embodiment of the invention; 
           [0080]      FIG. 11A  shows the structure of a module used in the circuit of  FIG. 11 ; 
           [0081]      FIG. 12  diagrammatically illustrates a first alternative embodiment of the integrator circuit of  FIG. 11 ; 
           [0082]      FIG. 12A  shows the structure of a module used in the circuit of  FIG. 12 ; 
           [0083]      FIG. 13  diagrammatically illustrates an integrator circuit according to  FIG. 8  also including means to compensate an offset effect; 
           [0084]      FIG. 13A  shows the structure of a module used in the circuit of  FIG. 13 ; 
           [0085]      FIG. 13B  shows an operating chronogram of the integrator circuit of  FIG. 13 ; and 
           [0086]      FIG. 14  diagrammatically illustrates the structure of a functional amplifier with a single-pole output including a means to compensate an offset effect according to the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0087]    The idea at the base of the invention is to multiplex all or some of the integration operations with multiple time window functions within at least one part of the integrator circuit. 
         [0088]    A first embodiment of the invention is illustrated in  FIG. 3 . The integrator circuit  300 , like the integrator circuit  200 , comprises a plurality of switches  311  to  314 , a voltage/current conversion module  320 , and a functional amplifier  330 . The switches  311  and  313  are controlled by a same logic signal W. As shown later, the signal W is a composite window function signal. When the signal W is active, the switches  311  and  313  respectively apply the voltages and V in   +  and V in   − , forming the differential voltage, to the conversion module  320 . The switches  312  and  314  are controlled by the complementary logic signal  W . When the signal  W  is active, the reference voltage V ref  is applied by the switches  312  and  314  to the inputs of the conversion module  320 , which corresponds to a null differential input voltage. 
         [0089]    The differential current output of the conversion module  320  is connected to the differential input of the op-amp  330 . 
         [0090]    Unlike the circuit  200 , the integrator circuit  300  comprises a first battery  341  of P integration capacitors, situated between the terminal  351  and a first input (virtual mass)  331  of the op-amp  330 . The reference voltage V ref  is continuously applied on the output terminal  351 . Similarly, the circuit comprises a second battery  342  of P integration capacitors, mounted in negative counter-reaction between the output  334  of the op-amp and its second input  332 . The batteries  341  and  342  of integration capacitors have the same structure  340 , described below. 
         [0091]    The shared structure of the batteries of integration capacitors was shown in  FIG. 3A . The battery  340  comprises a plurality P of identical modules noted  340   1 , . . . ,  340   P , connected to a shared input terminal  340   In  and a shared output terminal  340   Out . 
         [0092]    Each module  340   p  comprises a capacitor  344   p , having a capacitor value C, a pair of selection switches  345   p  and  347   p  controlled by the logic signal sel p  and an idle switch  346   p  controlled by the complementary signal  sel   p . When the signal sel p  is active, the terminal  344   p - 1  is connected via the switch  345   p  to the input terminal  340   In . Likewise, the terminal  344   p - 2  is connected via the switch  347   p  to the output terminal  340   Out . The capacitor  344   p  is thus selected in the counter-reaction loop of the op-amp and the current generated by the conversion module  320  charges the capacitor in question. As shown later, the various signals sel p  make it possible to select different windows within the composite signal W. 
         [0093]    Conversely, when the signal  sel   p  is active, the terminal  344   p - 1  remains subject to the reference voltage V ref  via the switch  346   p  and the terminal  344   p - 2  is disconnected from the output  340   Out  by the switch  347   p . No current circulates through the capacitor  344   p  and the application of the voltage V ref  prevents any discharge of the capacitor  344   p  during the switch. 
         [0094]    Each module  340   p  also comprises a switch  341   p , mounted in parallel with the switches  345   p  and  346   p  between the terminals  340   In  and  341   p - 1 , as well as a switch  343   p  mounted in parallel with the capacitor  344   p . The switches  341   p  and  343   p  are both controlled by the reset logic signal Reset. When the Reset signal is active, the capacitor is discharged by a short circuit between its terminals and its terminals are brought to the reference potential V ref . 
         [0095]    Returning to  FIG. 3 , the output terminal  352  of the second battery  342  of integration capacitors is connected to a battery  360  of storage capacitors. It comprises a plurality P of storage capacitors  364   p , p=1, . . . , P. A same plurality P of switches  361   p  respectively switches the input terminal  352  on the terminals  364   p - 1  of the capacitors  364   p , p=1, . . . , P. More precisely, when the control signal Memo p  is active, the switch  361   p  connects the input  352  to the terminal  364   p - 1  of the storage capacitor  364   p . The terminals  364   p - 1  are also connected to the output  370  via output switches  365   p , respectively controlled by logic signals Out p , p=1, . . . , P. The other terminals  364   p - 2  of the capacitors  364   p  are kept at the reference voltage V ref . 
         [0096]      FIG. 3B  illustrates the operating chronogram of the integrator circuit of  FIG. 3 . 
         [0097]    As an illustration it has been assumed that P=2. For example, the integrator circuit will be able to analyze two users in a system, or two modulation positions of a user in a TH-UWB system, or two distinct range bins in a radar system. 
         [0098]    In  390 - 1  and  390 - 2  we have shown, respectively, first (w 1 ) and second (w 2 ) multiple window function signals. Each multiple window function signal generally includes a plurality N of time windows, i.e.: 
         [0000]    
       
         
           
             
               
                 w 
                 p 
               
                
               
                 ( 
                 t 
                 ) 
               
             
             = 
             
               
                 ∑ 
                 
                   n 
                   = 
                   1 
                 
                 N 
               
                
               
                 
                   w 
                   n 
                   p 
                 
                  
                 
                   ( 
                   t 
                   ) 
                 
               
             
           
         
       
     
         [0099]    The time windows w n   p (t), p=1, . . . , P, n=1, . . . , N do not overlap. 
         [0100]    In the illustrated case, N=2. 
         [0101]    The composite window function signal W was shown in  390 - 3 . It is obtained by using an OR logic of the multiple window function signals w p , i.e.: 
         [0000]    
       
         
           
             
               
                 
                   W 
                   = 
                   
                     
                       ⋁ 
                       
                         
                           p 
                           = 
                           1 
                         
                         , 
                         
                             
                         
                          
                         … 
                          
                         
                             
                         
                         , 
                         P 
                       
                     
                      
                     
                       w 
                       p 
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0102]    The selection signals sel p , p=1, 2 are given in  390 - 4  and  390 - 5 , respectively. The signal sel p  has rising pulse edges synchronous with those of the multiple window function signal w p . Alternatively, the rising pulse edges of Sel p  can slightly precede those of w p . In any case, the descending pulse edges of sel p  are delayed by a time τ relative to the descending pulse edges of w p . The time τ is determined to take into account the travel time of the conversion module  320  and the reestablishment time at the end of integration into a time window. Thus, on the n th  descending pulse edge of sel p , it is certain that the input signal has been taken into account and integrated in the entire duration of the time window w n   p  by the integration capacitor  344   p . It will be noted that the signal sel p  makes it possible to select the multiple window function signal w p , i.e. the time windows w n   p , within the composite signal W, or w p =Ŵsel p . 
         [0103]    The reset signal Reset is given in  390 - 6 . A reset occurs before the beginning of an integration cycle, i.e. before the beginning of the P parallel integration operations. It polarizes the different elements of the circuit at the reference voltage, which guarantees a stable and reproducible initialization of the circuit upon each integration cycle Int. 
         [0104]    The integration cycle Int is followed by a transfer cycle Trf in which the P integration results are sequentially transferred to the storage capacitors  364   p  owing to the controls Memo p , p=1, 2 shown in  390 - 7  and  390 - 8 . When the signals sel p  and Memo p  are simultaneously active, the charge contained in the integration capacitor  344   p  is transferred to the associated storage capacitor  364   p  via the switches  347   p  and  361   p . Once all of the integration results have been transferred into the storage capacitors, a reset Reset can take place. This reset does not affect the charges stored in the battery of storage capacitors  360 . 
         [0105]    The results thus stored can be read during the following integration cycle using reading signals Out p , p=1, 2, shown in  390 - 9  and  390 - 10 . When the signal Out p  is active, the voltage present at the terminal  364   p - 1  can be read on the output terminal  370  of the circuit. Thus, the reading of the integration results of the preceding cycle can take place in parallel with the integration operations of the current cycle. 
         [0106]    The fact that the integration operations use the same conversion module and the same functional amplifier makes it possible to reduce the dispersion and therefore substantially improve the precision and reliability of the integration results. 
         [0107]      FIG. 4  shows a first alternative embodiment of the integrator of  FIG. 3 . Elements identical to those of  FIG. 3  are designated using the same reference numbers increased by 100. This alternative differs from the preceding circuit in that the output is not single-pole, but differential. The two batteries of integration capacitors  441  and  442  are mounted in respective negative counter-reaction between the differential outputs and inputs of the functional amplifier. They have the same structure as shown in  FIG. 3A . 
         [0108]    The outputs of the two batteries  441  and  442  are connected to the terminals  433  and  434  between which a plurality P of storage capacitors  464   p  is mounted in parallel. The terminals  464   p - 1 , p=1, . . . , P, are connected to the terminal  433  through the switches  461   p  and to the output terminal  471  through the switches  465   p , respectively. Similarly, the terminals  464   p - 2 , p=1, . . . , P, are connected to the terminal  434  through the switches  462   p  and to the output terminal  472  through the switches  466   p , respectively. The switches  461   p  and  462   p , p=1, . . . , P, are respectively controlled by the controls Memo p , p=1, . . . , P: they make it possible to transfer the charges stored in the integration capacitors, selected by the commands sel p  within  441  and  442  towards the storage capacitors. The switches  465   p  and  466   p , p=1, . . . , P, are respectively controlled by the controls Out p , p=1, . . . , P. When the signal Out p  is active, the voltage present between the terminals of the capacitor  464   p  can be read between the output terminals  471  and  472  of the circuit. 
         [0109]      FIG. 5  illustrates a second alternative embodiment of the circuit of  FIG. 3 . It differs therefrom in that the input of the voltage/current conversion module is single-pole, i.e. the current generated by this module is proportional to the voltage applied either to the voltage V in  of the signal to be integrated by the switch  511 , or the reference voltage V ref  by the switch  512 . The switch  511  is controlled by the composite window function signal W and the switch  512  by its complement  W . 
         [0110]    The rest of the circuit is identical to that of  FIG. 3 , the same elements bearing the same reference numbers increased by 200. 
         [0111]      FIG. 6  shows a third alternative embodiment of the integrator according to  FIG. 3 . This alternative embodiment has a differential output like the first alternative, but a single-pole input like the second alternative. It will therefore not be described in more detail. Elements identical to those of  FIG. 4  and  FIG. 5  are increased by 200 and 100, respectively. 
         [0112]      FIG. 7  shows a second embodiment of the integrator circuit according to the invention. 
         [0113]    According to this embodiment, the input switches and the voltage/current conversion module are shared by the different integration operations with multiple window functions as in the first embodiment. More specifically, elements  711 - 714 ,  720  are identical to elements  311 - 314 ,  320 , respectively. 
         [0114]    However, the P integration, storage, and reading operations are performed within distinct modules  740   1 , . . . ,  740   P , mounted in parallel on the outputs of the conversion module  720 . The different modules  740   p  are connected at their output to the output terminal of the circuit  770 . The different modules  740   p , p=1, . . . , P all have the same structure illustrated in  FIG. 7A . 
         [0115]      FIG. 7A  shows the structure of a module  740   p . This module is organized around a functional amplifier  730   p  whereof the inputs  731   p  and  732   p  are respectively connected to the output terminals of the conversion module  720  through two switches  735   p  and  735 ′ p  controlled by the same command sel p . 
         [0116]    A first capacitor  744   p , called reference capacitor, with value C, is disposed between the reference voltage V ref  and a first input  731   p  of the op-amp. A second integration capacitor  744 ′ p  of the same value is mounted in negative counter-reaction between the output of the op-amp and its second input  732   p  (the values of the capacitors  744   p  and  744 ′ p , p=1, . . . , P are all equal to C). A switch  743   p  (resp.  743 ′ p ) controlled by the reset signal Reset is mounted in parallel between the terminals of the capacitor  744   p  (resp.  744 ′ p ). Furthermore, a switch  741   p  (resp.  741 ′ p ) also controlled by the signal Reset, connects the terminal  744   p - 1  (resp.  741 ′ p - 1 ) of the capacitor  744   p  (resp.  744 ′ p ) to the voltage V ref . Thus, when the signal Reset is active, the capacitors  744   p  and  744 ′ p  are short circuited and their terminals polarized at the voltage V ref . 
         [0117]    The terminal  764   p - 1  of the storage capacitor  764   p  is connected, on one hand, to the terminal  744 ′ p - 2  of the integration capacitor, via the transfer switch  761   p  and, on the other hand, to the output of the integrator circuit  770 , via the reading switch  765   p . The transfer switch  761   p , controlled by the signal Memo p  makes it possible to transfer the charge integrated into  744 ′ p  to the corresponding storage capacitor  764   p . The reading switch  765   p , controlled by the reader signal Out p , makes it possible to show, on the output  770 , the voltage corresponding to the stored charge. 
         [0118]      FIG. 7B  shows an operating chronogram of the integrator according to the second embodiment, for example with p=2 and N=2. 
         [0119]    The multiple window function signals w 1 , w 2  and the composite signal W shown in  790 - 1 ,  790 - 2  and  790 - 3  are identical to those of  FIG. 3B . However, it will be noted that the selection signals sel p , p=1, 2, in  790 - 4  and  790 - 5  are slightly different from the preceding ones. Indeed, due to the physical separation of the various modules  740   p  in the second embodiment, it is not necessary to multiplex the transfer of the charges from the integration capacitors towards the storage capacitors. Thus, the signals sel p  do not need to be active during the transfer cycle Trf. Likewise, the storage signals Memo p  are advantageously all identical, the transfer of the charges then being done simultaneously and in parallel during the transfer cycle. The reading of the stored values can be done, as in  FIG. 3A , during the following integration cycle, by sequentially activating the commands Out p ), as indicated in  790 - 9  and  790 - 10 . 
         [0120]    The second embodiment has, relative to the first, the advantage of allowing very rapid switching from one time window to the other. If the multiple window signals w 1  and w 2  are very close, for example if the windows w 1   1  and w 1   2  follow each other at short intervals, the independence of the modules  740   1  and  740   2  ensures the independence of the integration operations. In particular, the selection switches relative to the first window do not create a current disruption in the counter-reaction loop relative to the second window. 
         [0121]    The second embodiment also makes it possible to obtain a high level of precision owing to the sharing of the voltage/current conversion module by the P parallel integration operations. 
         [0122]    It also makes it possible to accelerate the charge transfer phase between the integration capacitors and the storage capacitors since this transfer can be done in parallel. 
         [0123]    Despite a plurality of functional amplifiers, the integrator circuit according to the second embodiment has a relatively modest consumption due to the use of a shared voltage/current conversion module. 
         [0124]      FIG. 8  shows a first alternative of the integrator circuit of  FIG. 7 , in which the input and the output of the circuit are both differential. A plurality of modules  840   p , p=1, . . . , P are mounted in parallel between the differential output terminals of the conversion module  820  and the differential output terminals  871  and  872  of the circuit. 
         [0125]      FIG. 8A  illustrates the structure of a module  840   p  of  FIG. 8 . Unlike the structure of  FIG. 7A , the output of this module is differential instead of being single-pole. It will be noted that the two integration paths on either side of the op-amp  830   p  are symmetrical here. 
         [0126]      FIG. 9  shows a second alternative of the integrator circuit of  FIG. 7 . It differs, however, in that it has a single-pole input instead of a differential input. In other words, the input and the output of the circuit are both single-pole here. 
         [0127]      FIG. 10  shows a third alternative of the integrator circuit of  FIG. 7 . It differs from the first alternative in that the input is single-pole, and from the second alternative in that the output is differential. 
         [0128]    In  FIGS. 9 and 10 , elements identical to those of  FIG. 7 ,  8  are increased by 200, respectively. They will therefore not be described again. 
         [0129]      FIG. 11  shows a third embodiment of the integrator circuit according to the invention. This embodiment is a hybrid form of the first and second embodiments. 
         [0130]    The switches  1111  to  1114  as well as the voltage/current conversion module  1120  are identical to those of the preceding embodiments. 
         [0131]    A plurality of modules  1140   q , q=1, . . . , Q, are mounted in parallel on the outputs of the voltage/current conversion module  1120 . 
         [0132]    The structure of a module  1140   q  is illustrated in  FIG. 11A . It comprises a functional amplifier  1130   q  as well as first and second batteries, respectively designated by  1141   q  and  1142   q , each including P integration capacitors. The structure of the batteries  1141   q  and  1142   q  is identical to that given in  FIG. 3A . The battery of integration capacitors  1141   q  is disposed between the reference voltage V ref  and the virtual mass  1131   q  of the op-amp. However, the battery of integration capacitors  1142   q  is disposed in a counter-reaction loop between the output of the op-amp and its virtual mass  1132   q . The output of the battery  1142   q  is connected to a battery  1160   q  of P storage capacitors  1164   q   p , via the respective switches  1161   q   p , p=1, . . . , P. The charge of the capacitor  1161   q   p  can be read on the output  1170  by activating the associated switch  1165   q   p . 
         [0133]    It will be understood that the circuit of  FIG. 11  supplies QP multiple time window integration paths. These paths are grouped together in subassemblies of P integration paths, the paths of a same subassembly sharing the same voltage/current conversion module, the same op-amp and the same counter-reaction loop. The integration operations of these different paths are multiplexed over time. However, the paths of separate subassemblies only share the voltage/current conversion module. The integration operations of these paths can be done in parallel. 
         [0134]    Generally, an integration path is selected here by activating the subassembly selection switches, called first rank,  1135   q  and  1135 ′ q , as well as path selection switches within this subassembly, called second rank. 
         [0135]    These second rank switches correspond to the switches  345   1 / 346   1  (cf.  FIG. 3A ) in the batteries  1141   q  and  1142   4 . 
         [0136]    One skilled in the art will understand that, like the first and second embodiments, the third embodiment can be broken down into a first alternative with differential input and differential output, a second alternative with single-pole input and single-pole output, and lastly a third alternative with single-pole input and differential output. 
         [0137]      FIG. 12  illustrates, as an example, the first alternative of the third embodiment. As in  FIG. 11 , the integrator circuit shown provides a set of QP integration paths with multiple time window functions, these paths being grouped together in subassemblies of P integration paths. Unlike  FIG. 11 , the modules  1240   q , q=1, . . . , Q, each have a differential output connected on the output terminals  1271  and  1272  of the integrator circuit. 
         [0138]    The structure of a module  1240   q  is illustrated in  FIG. 12A . It comprises a functional amplifier  1230   q  as well as first and second batteries of integration capacitors, respectively designated by  1241   q  and  1242   q , each including P capacitors. The structure of the batteries  1241   q  and  1242   q  is identical to that given in  FIG. 3A . The first battery of integration capacitors  1241   q  is mounted in counter-reaction between the first output  1233   q  of the op-amp and its first input  1231   q . The second battery of integration capacitors  1242   q  is mounted in counter-reaction between the second output  1234   q  of the op-amp and its second input  1233   q . The respective outputs of the batteries of integration capacitors,  1241   q  and  1242   q , are connected to a battery of storage capacitors  1260   q . More specifically, this battery  1260   q  comprises a plurality P of storage capacitors  1264   q   p , p=1, . . . , P, connected in parallel to the outputs  1233   q  and  1234   q  of the op-amp, via the respective switches  1261   q   p . The voltage at the terminals of the capacitor  1264   q P can be read between the outputs  1271  and  1272  by activating the reading switches  1165   q   p  and  1165 ′ q   p . 
         [0139]    The selection of a given integration path is done as before by activating the selection switches of a subassembly, i.e. first rank and, within that subassembly, by activating the path selection switches, i.e. second rank. 
         [0140]    In general, an integrator circuit with multiple time window functions can include an offset due primarily to the mismatching of the MOS transistors making up the inputs of the voltage/current converter and the functional amplifier. This offset can be compensated by post-processing by readjusting the value obtained after integration, by a known and constant factor. 
         [0141]    However, when the number of coherent integrations increases, the accumulation of the offset can end up producing a saturation at the output of the functional amplifier(s). This modifies the precision on the integrated value because the integration is no longer done in the linear operating zone. In that case, a post-processing compensation is no longer possible. 
         [0142]    Thus, to be able to maintain good precision on the results of the integration, it is necessary to limit the number of coherent integrations to a determined number of about ten integrations. 
         [0143]    In order to resolve this problem, and to improve the detectability of the receiver by increasing the number of coherent integrations, the integrator circuit can advantageously be configured to eliminate the accumulation effect of the offset by continuously compensating for it during the integration process. 
         [0144]    More particularly, the integrator circuit according to the present invention can be configured to periodically reverse the effect of the offset on the results of the integration. This can be done by adding pairs of switches with alternating switching along the integration path. Thus, for an even number of coherent integrations, the offset is compensated by the fact that it is applied in one direction, then the other on the results of the integration. 
         [0145]    Advantageously, in the event the output of the functional amplifier is differential, two pairs of switches with alternating switching can be mounted at the input as well as the output of the functional amplifier. 
         [0146]    Likewise, in the event the input of the voltage/current converter is differential, two pairs of switches with alternating switching can be mounted at the input as well as the output of the voltage/current converter. 
         [0147]    Thus, the integrator circuit including a voltage/current converter with a differential input (i.e. according to the embodiments of  FIGS. 3 ,  4 ,  7 ,  8 ,  11  and  12 ) can comprise first and second pairs of switches with alternating switching according to first and second phases mounted upstream of the voltage/current converter and third and fourth pairs of switches with alternating switching according to the first and second phases mounted downstream of the voltage/current converter. Each pair of switches can be controlled by first and second clock signals according to the first and second phases. 
         [0148]    Likewise, the integrator circuit including a functional amplifier with differential output (i.e. according to the embodiments of  FIGS. 4 ,  6 ,  8 A and  12 A) can comprise fifth and sixth pairs of switches with alternating switching according to the first and second phases mounted upstream of the functional amplifier and seventh and eighth pairs of switches with alternating switching according to the first and second phases mounted downstream of the functional amplifier. 
         [0149]      FIGS. 13 and 13A  illustrate, as an example, the mounting of pairs of switches in the integrator circuit shown in  FIGS. 8 and 8A . 
         [0150]    The structure of the integrator circuit of  FIG. 13  differs from  FIG. 8  in that it includes first ( 1321   c   1  and  1321   c   2 ) and second ( 1322   c   1  and  1322   c   2 ) pairs of switches with alternating switching upstream of the conversion module  1320  and third ( 1323   c   1  and  1323   c   2 ) and fourth ( 1324   c   1  and  1324   c   2 ) pairs of switches with alternating switching downstream of the conversion module  1320 . 
         [0151]    More particularly, the first ( 1321   c   1  and  1321   c   2 ) and second ( 1322   c   1  and  1322   c   2 ) pairs of switches with alternating switching are inserted between the differential input terminals of the conversion module  1320  on the one hand and the input switches  1311  to  1314  on the other hand. 
         [0152]    The third ( 1323   c   1  and  1323   c   2 ) and fourth ( 1324   c   1  and  1324   c   2 ) pairs of switches with alternating switching are inserted between the differential output terminals of the conversion module  1320  on the one hand and the modules  1340   1 , . . . ,  1340   p  on the other hand. 
         [0153]    Furthermore, the structure of the conversion module  1340   p  of  FIG. 13A  differs from  FIG. 8A  in that it includes fifth ( 1325   c   1  and  1325   c   2 ) and sixth ( 1326   c   1  and  1326   c   2 ) pairs of switches with alternating switching upstream of the functional amplifier  1330   p  and seventh ( 1327   c   1  and  1327   c   2 ) and eighth ( 1328   c   1  and  1328   c   2 ) pairs of switches with alternating switching downstream of a functional amplifier  1330   p . 
         [0154]    More particularly, the fifth ( 1325   c   1  and  1325   c   2 ) and sixth ( 1326   c   1  and  1326   c   2 ) pairs of switches with alternating switching are inserted between the differential input terminals of the functional amplifier  1330   p  on one hand, and the two switches ( 1335   p  and  1335   p ) controlled by the command sel p  on the other hand. 
         [0155]    The seventh ( 1327   c   1  and  1327   c   2 ) and eighth ( 1328   c   1  and  1328   c   2 ) pairs of switches with alternating switching are inserted between the differential output terminals of the functional amplifier  1330   p  on the one hand, and the terminals ( 1364   p - 1  and  1364   p - 2 ) of the storage capacitor  1364   p  via the transfer switches ( 1361   p  and  1361 ′ p ) on the other hand. 
         [0156]      FIG. 13B  shows an operating chronogram of the integrator according to the embodiment of  FIGS. 13 and 13A , for one example with p=2 and N=2. 
         [0157]    The signals shown in  1390 - 1 , . . . ,  1390 - 10  are identical to those of  FIG. 7B . However, it will be noted that there are two integration cycles Int 1  and Int 2  before the transfer cycle Trf. 
         [0158]    Indeed, for each of the first (w 1 ) and second (w 2 ) multiple window signals, the integration is done twice according to a clock signal clkoffset shown in  1390 - 0 . A first integration Int 1  is done in a first phase (or positive phase) corresponding to a clock signal clkoffset=1 and a second integration Int 2  in a second phase (or negative phase) corresponding to a clock signal corresponding to clkoffset=0 (i.e.  clckoffset =1). Thus, the offset applies in a first direction during the first integration and in a second direction opposite the first during the second integration. As a result, the offset produced on the results of the first integration is compensated by that created on the result of the second integration. 
         [0159]    Then, as in  FIG. 7B , the transfer of the charges is done simultaneously and in parallel during the storage signals Memo p  in  1390 - 7  and  1390 - 8  of the transfer cycle. Once all of the integration results have been transferred into the storage capacitors, the reset signal Reset is given in  1390 - 6 . The reading of the stored values can be done, as in  FIG. 7B , during the following integration cycle, by sequentially activating the read commands Out p , as indicated in  1390 - 9  and  1390 - 10 . 
         [0160]    It will be noted that in the event the input of the voltage/current converter is single-pole (i.e. according to the embodiments of  FIGS. 5 ,  6 ,  9 , and  10 ), the offset effect is negligible by design and in that case, it is not useful to add pairs of switches with alternating switching. 
         [0161]    Moreover, in the event the output of the functional amplifier is single-pole (i.e. according to the embodiments of  FIGS. 3 ,  5 ,  7 A, and  11 A), fifth and sixth pairs of switches with alternating switching according to the first and second phases can be mounted upstream of the functional amplifier in the same way as in the example of  FIG. 13B . However, the seventh and eighth pairs of switches with alternating switching according to the first and second phases are, in this case, mounted in the very structure of the functional amplifier so as to reverse the polarity of the single-pole output relative to the input terminals of the functional amplifier. 
         [0162]      FIG. 14  illustrates, as an example, the mounting of the seventh and eighth pairs of switches with alternating switching in the structure of a functional amplifier with a single-pole output. 
         [0163]    This figure diagrammatically shows a functional amplifier  1430   p  including a first differential pair of input transistors Q 1  and Q 2  whereof the drains are respectively connected to the drains of a second pair of transistors Q 3  and Q 4  of a current mirror and whereof the sources are connected to a current source G 14 . 
         [0164]    A seventh pair ( 1427   c   1  and  1427   c   2 ) of switches with alternating switching according to the first and second phases is inserted between the drains of the input transistors Q 1  and Q 2  on the one hand, and the gates of the transistors Q 3  and Q 4  of the current mirror on the other hand. 
         [0165]    Moreover, an eighth pair ( 1428   c   1  and  1428   c   2 ) of switches with alternating switching according to the first and second phases is inserted between the drains of the input transistors Q 1  and Q 2  on the one hand, and the single-pole output S terminal  1434   p  of the functional amplifier  1430   p  on the other hand. 
         [0166]    Thus, during the first phase corresponding to the clock signal clkoffset=1, the gates of the transistors Q 3  and Q 4  of the current mirror are connected to the drain of the transistor Q 1  of the reversing input  1432   p , while the single-pole output terminal  1434   p  is connected to the drain of the transistor Q 2  of the non-reversing input  1431   p . 
         [0167]    However, during the second phase corresponding to the clock signal  clkoffset =1, the gates of the transistors Q 3  and Q 4  of the current mirror are connected to the drain of the transistors Q 2  of the non-reversing input  1431   p , while the single-pole output is connected to the drain of the transistor Q 1  of the reversing input  1432   p . 
         [0168]    As a result, the offset applies in a first direction during the first integration (first phase) and in the opposite direction during the second integration (second phase). 
         [0169]    One skilled in the art will understand that, as illustrated as an example in the embodiments of  FIGS. 13 ,  13 A,  13 B, and  14 , pairs of switches with alternating switching can also be inserted into the other embodiments of the present invention.