Abstract:
A dual resolution circuit for supporting normal resolution display mode and half resolution display mode is disclosed. In the dual resolution circuit, cascaded shift registers are controlled by a group of clock signals to generate intermediate scan signals in response to a start pulse. A normal/reverse scan switch, controlling a normal scan mode and a reverse scan mode, feeds back the intermediate scan signal from one shift register to another shift register. A dual resolution switch switches signal paths of the intermediate scan signals to logic gates. The logic gates perform logic operation on an enablement signal and the intermediate scan signals to generate final scan signals used in dual resolution display modes.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority benefits of U.S. provisional application Ser. No. 60/671,965, filed on Apr. 15, 2005. All disclosure of this application is incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of Invention  
         [0003]     The present invention relates to a circuit structure for dual resolution in a display apparatus.  
         [0004]     2. Description of Related Art  
         [0005]     LCD is one kind of popular flat panel display devices. There are two resolution modes in LCD, normal resolution mode and half resolution mode. In general, LCD is displayed under the normal resolution mode. In some cases, for example, for power-saving or low resolution requirement, LCD will be displayed under the half resolution mode.  
         [0006]      FIGS. 1   a  and  1   b  show the definition of unit pixel in the normal resolution mode and the half resolution mode, respectively. Referring to  FIG. 1   a , in the normal resolution mode, one unit pixel includes one individual pixel, with R, G and B three sub-pixels. Referring to  FIG. 1   b , in the half resolution mode, one unit pixel includes four individual pixels. In  FIGS. 1   a  and  1   b , symbols “R”, “G” and “B” refer to R/G/B sub-pixels and “R 1 ”, “R 2 ”, and “R 3 ” refer to first, second and third pixel rows. As known, one individual pixel includes three sub-pixels, or said R/G/B sub-pixels. By defining different unit pixel in  FIGS. 1   a  and  1   b , dual resolution function is made.  
         [0007]     Two kinds of vertical scan signals are used to define different unit pixel under different resolution modes.  FIG. 2   a  and  FIG. 2   b  show two kinds of vertical scan signals, respectively. In  FIG. 2   a , to define the unit pixel under the normal resolution, the vertical scan signal scan one pixel row in one pulse. In  FIG. 2   b , to define the unit pixel under the half resolution, the vertical scan signal scan two pixel rows in one scan pulse.  
         [0008]     Taking an LCD panel with 640 pixel rows * 480 channels for example. In this LCD panel, 640 vertical scan signals are required to scan pixel rows. In normal resolution mode, a resolution of 640*480 is displayed. In half resolution mode, a resolution of 320*240 is displayed.  
         [0009]     A cost effective and well performance circuit configuration for dual resolution modes in the LCD apparatus is needed.  
       SUMMARY OF THE INVENTION  
       [0010]     One aspect of the invention is to provide a circuit configuration for dual resolution modes in a display apparatus, which is low cost, small area and well performance.  
         [0011]     To achieve the above aspect, in one embodiment, a dual resolution circuit for supporting dual resolution display modes in a display apparatus is provided. The dual resolution circuit includes a shift register stage, a dual resolution switch and a logic circuit stage. The shift register stage receives a start pulse and four clock signals to generate intermediate scan signals. The dual resolution switch is controlled by a resolution mode signal to switch signal paths of the intermediate scan signals. The logic circuit stage receives the intermediate scan signals from the shift register stage and the switched intermediate scan signals from the dual resolution switch to generate output scan signals for performing dual resolution modes.  
         [0012]     Another embodiment of the invention provides a display apparatus having a dual resolution circuit for supporting dual resolution display modes. The dual resolution circuit includes: a clock generator, generating first, second, third and fourth clock signals; a shift register stage, receiving a start pulse and the first, second, third and fourth clock signals for generating a plurality of intermediate scan signals; a normal/reverse scan switch, receiving a normal scan signal, a reverse scan signal and the start pulse, for controlling a normal scan or a reverse scan of the display apparatus; a dual resolution switch, being controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals; and a logic circuit stage, receiving the plurality of intermediate scan signals from the shift register stage and the switched plurality of intermediate scan signals from the dual resolution switch to generate a plurality of output scan signals for performing dual resolution display modes in the display apparatus.  
         [0013]     Still another embodiment of the invention provides a display panel having a dual resolution circuit for supporting dual resolution display modes. The dual resolution circuit includes: a clock generator, generating first, second, third and fourth clock signals; a shift register stage, receiving a start pulse and the first, second, third and fourth clock signals for generating a plurality of intermediate scan signals; a normal/reverse scan switch, receiving a normal scan signal, a reverse scan signal and the start pulse, for controlling a normal scan or a reverse scan of the display panel; a dual resolution switch, being controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals; and a logic circuit stage, receiving the plurality of intermediate scan signals from the shift register stage and the switched plurality of intermediate scan signals from the dual resolution switch to generate a plurality of output scan signals for performing dual resolution display modes in the display panel.  
         [0014]     Yet another embodiment of the invention provides an electronic device having a display panel. The display panel includes a dual resolution circuit. The dual resolution circuit is used for supporting dual resolution display modes in the display panel. The dual resolution circuit includes: a clock generator, generating first, second, third and fourth clock signals; a shift register stage, receiving a start pulse and the first, second, third and fourth clock signals for generating a plurality of intermediate scan signals; a normal/reverse scan switch, receiving a normal scan signal, a reverse scan signal and the start pulse, for controlling a normal scan or a reverse scan of the display panel; a dual resolution switch, being controlled by a resolution mode control signal to switch signal paths of the plurality of intermediate scan signals; and a logic circuit stage, receiving the plurality of intermediate scan signals from the shift register stage and the switched plurality of intermediate scan signals from the dual resolution switch to generate a plurality of output scan signals for performing dual resolution display modes in the display panel.  
         [0015]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0016]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0017]      FIGS. 1   a  and  1   b  show the definition of unit pixel under the normal resolution mode and half resolution mode, respectively.  
         [0018]      FIGS. 2   a  and  2   b  show two kinds of horizontal scan signals used in the normal resolution mode and half resolution mode, respectively.  
         [0019]      FIG. 3  shows a block diagram of a dual resolution circuit according to one preferred embodiment of the present invention.  
         [0020]      FIG. 4   a  shows a block diagram of a clock generator in the dual resolution circuit of  FIG. 3  and  FIG. 4   b  shows waveforms of the clock signals from the clock generator of  FIG. 4   a.    
         [0021]      FIG. 5  shows a block diagram of a shift register stage in the dual resolution circuit of  FIG. 3  and waveforms thereof.  
         [0022]      FIG. 6  shows a waveform of output scan signals under the normal resolution mode.  
         [0023]      FIG. 7  shows a waveform of output scan signals under the half resolution mode.  
         [0024]      FIGS. 8   a ˜ 8   d  show signal paths under normal/reverse scan and normal/half resolution modes of  FIG. 3 .  
         [0025]      FIG. 9  shows an electronic device according to another embodiment of the invention.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]     Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0027]      FIG. 3  shows a block diagram of dual resolution circuit according to one embodiment of the present invention. The dual resolution circuit generates output signals GATE 1 ˜GATE 4  which function as the scan signals of  FIG. 2   a  or  FIG. 2   b  under different resolution display modes. Referring to  FIG. 3 , the dual resolution circuit  300  at least includes a clock generator  310 , a shift register state  330 , a normal/reverse scan switch  350 , a dual resolution switch  370  and a logic circuit stage  390 .  
         [0028]     The clock generator  310  generates four clock signals CKV 1 , CKV 2 , CKV 3  and CKV 4  based on a control signal CTL, two original clock signals CKV 1 , CKV 2  and two resolution mode control signals NORMAL and HALF. Wherein, CKV 2  is an inverted signal of CKV 1 . The operation of the clock generator  310  and waveforms of the signals thereof are shown in  FIGS. 4   a  and  4   b , which will be described more detailed later.  
         [0029]     The shift register stage  330  receives the clock signals CKV 1 , CKV 2 , CKV 3  and CKV 4  from the clock generator  310  and further a start pulse. The shift register stage  330  includes at least four cascaded shift registers SR 311 , SR 313 , SR 315  and SR 317 . The clock signals CKV 1  and CKV 2  are input into the shift register SR 311 ; the clock signals CKV 3  and CKV 4  are input into the shift register SR 313 ; the clock signals CKV 3  and CKV 4  are input into the shift register SR 315 ; and the clock signals CKV 1  and CKV 2  are input into the shift register SR 317 . The shift register stage  330  generates intermediate scan signals SR_OUT_ 1 , SR_OUT_ 2 , SR_OUT_ 3  and SR_OUT_ 4 , which is processed by the logic circuit stage  390  via the normal/reverse scan switch  350  and the dual resolution switch  370  to generate the scan signals GATE 1 ˜GATE 4 . The start pulse received by the shift register stage  330  is either the signal STVUI if under a normal scan mode or the signal STVBI if under a reverse scan mode.  
         [0030]     The operation of the shift register stage  330  and waveforms of the signals thereof are shown in  FIG. 5 , which will be described more detailed later.  
         [0031]     The normal/reverse scan switch  350  controls a normal or reverse scan based on normal/reverse scan control signals CSV and XCSV. The switch  350  at least includes eight transmission gates TM 351 ˜TM 358 . In the normal scan mode, the pixel rows are scanned in a direction, for example, from top to bottom. In the reverse scan mode, the pixel rows are scanned in a reverse direction, for example, from bottom to top. Signal XCSV is an inverted signal of signal CSV. When a normal scan operation is required, the signal CSV is logic H, or said the signal XCSV is logic L. On the other hand, when a reverse scan operation is required, the signal XCSV is logic H, or said the signal CSV is logic L. The detail operation of the switch  350  is described later by referring  FIGS. 8   a ˜ 8   d.    
         [0032]     The dual resolution switch  370  controls a normal resolution mode or a half resolution mode based on normal/half resolution control signals NORMAL and HALF. The dual resolution switch  370  at least includes four transmission gates TM 371 ˜TM 377 . The dual resolution switch  370  conduct appropriate signals SR_OUT_ 1 ˜SR_OUT_ 4  to the logic circuit stage  390  for generating output scan signals GATE 1 ˜GATE 4  under the normal resolution mode and the half resolution mode. The detail operation of the switch  370  is described later by referring  FIGS. 6, 7  and  8   a ˜ 8   d . If a normal resolution mode is required, the signal NORMAL is logic H and the signal HALF is logic L. If a half resolution mode is required, the signal NORMAL is logic L and the signal HALF is logic H.  
         [0033]     The logic circuit stage  390  includes at least four NAND gates NAND 1 ˜NAND 4 . The stage  390  performs logic operation on the output signals from the shift register stage  330  and an enablement signal ENBV to produce output scan signals GATE 1 ˜GATE 4 . In this embodiment, under normal resolution mode, overlapping between output scan signals GATE 1 ˜GATE 4  is prevented by NAND logic operation.  
         [0034]      FIG. 4   a  shows a block diagram of the clock generator  310  in the dual resolution circuit of  FIG. 3  and  FIG. 4   b  shows waveforms of the clock signals from the clock generator of  FIG. 4   a . As shown in  FIG. 4   a , the clock generator  310  includes four transmission gates TM 401 , TM 403 , TM 405  and TM 407 . On/off states of the transmission gates are controlled by signals NORMAL and HALF. When NORMAL is logic H and HALF is logic L, i.e. under normal resolution mode, TM 403  and TM  407  are on; and TM 401  and TM  405  are off. So, under normal resolution mode, CKV 3 =CKV 1  and CKV 4 =CKV 2 . Similarly, when NORMAL is logic L and HALF is logic H, i.e. under half resolution mode, TM 403  and TM  407  are off; and TM 401  and TM  405  are on. So, under normal resolution mode, CKV 4 =CKV 1  and CKV 3 =CKV 2 . Waveforms of CKV 1 ˜CKV 4  under different resolution modes are shown is  FIG. 4   b . The clock signals CKV 1 ˜CKV 4  are used to control operation states of the shift registers in the next stage  330 .  
         [0035]      FIG. 5  shows a block diagram of the shift register stage  330  in the dual resolution circuit of  FIG. 3  and waveforms thereof. The shift register stage  330  includes at least four cascaded shift registers SR 311 , SR 313 , SR 315  and SR 317 . For simplicity, only four shift registers are shown in  FIGS. 3 and 5 , but the present invention are not limited thereby. Each shift register includes two clock inverters and one inverter. The shift register SR 311  includes two clock inverters  311   a  and  311   c  and one inverter  311   b . The shift register SR 313  includes two clock inverters  313   a  and  313   c  and one inverter  313   b . The shift register SR 315  includes two clock inverters  315   a  and  315   c  and one inverter  315   b . The shift register SR 317  includes two clock inverters  317   a  and  317   c  and one inverter  317   b . The clock inverter has two operation states, latch state and transmission state. In latch state, the output signal of the shift register is latched. In the transmission state, the input signal is transmitted as the output signal. The configuration of the shift registers and the clock inverters are not specially limited.  
         [0036]     As shown in  FIGS. 3 and 5 , the clock signals CKV 1 ˜CKV 4  are used to control states of the shift register SR 311 ˜SR 317 . For example, clock signals CKV 1  and CKV 2  are used to control the shift register SR 311 . A start pulse received by the shift register stage  330  is either the signal STVUI if under a normal scan mode or the signal STVBI if under a reverse scan mode. Besides, the start pulse is input to the first or last shift register, depending on the normal/reverse scan mode.  FIG. 5  only shows under normal scan mode, a start pulse STV (STVUI) is fed into the first shift register SR 311  as an input signal, and output signals from a previous shift register are fed into a next shift register as an input. For example, under normal scan mode, the signal SR_OUT_ 1  from the shift register SR 311  are input into the shift register SR 313  as an input. On the other hand, under reverse scan mode, a start pulse STVBI is fed into the last shift register SR 317  as an input signal, and output signals from a next shift register are fed into a previous shift register as an input, although this case is not shown in  FIG. 5  for clarity. For example, under reverse scan mode, the signal SR_OUT_ 4  from the shift register SR 317  are input into the shift register SR 315  as an input signal. The normal/reverse scan switch  350  is used to conduct appropriate start pulse and signal into the shift registers. The detailed conducting operation is described later by referring  FIGS. 8   a ˜ 8   d.    
         [0037]      FIG. 6  shows a waveform of output scan signals GATE 1 ˜GATE 4  under the normal resolution mode. Under normal resolution mode, to generate output scan signals GATE 1 ˜GATE 4  as waveforms in  FIG. 2   a , GATE 1 ˜GATE 4  are expressed by:  
         [0038]     GATE 1 =NAND (SR_OUT_ 1 , SR_OUT_ 2 , ENBV);  
         [0039]     GATE 2 =NAND (SR_OUT_ 2 , SR_OUT_ 3 , ENBV);  
         [0040]     GATE 3 =NAND (SR_OUT_ 3 , SR_OUT_ 4 , ENBV);  
         [0041]     GATE 4 =NAND (SR_OUT_ 4 , SR_OUT_ 5 , ENBV).  
         [0042]     Signal SR_OUT_ 5 , not shown in attached figures, refer to an output signal from fifth shift register (not shown) in the stage  330 . Although only four shift registers in the stage  330  and four scan control signals GATE 1 ˜GATE 4  are shown in  FIG. 3 , the embodiment is not limited thereby. For example, if there are 640 pixel rows in an LCD panel, then 640 scan signals GATE  1 ˜GATE 640  and 640 shift registers in the stage  330  are required.  
         [0043]      FIG. 7  shows a waveform of output signals under the half resolution mode. Under half resolution mode, to generate output scan signals GATE 1 ˜GATE 4  as waveforms in  FIG. 2   b , GATE 1 ˜GATE 4  are expressed by:  
         [0044]     GATE 1 =NAND (SR_OUT_ 1 , SR_OUT_ 3 , ENBV);  
         [0045]     GATE 2 =NAND (SR_OUT_ 2 , SR_OUT_ 3 , ENBV);  
         [0046]     GATE 3 =NAND (SR_OUT_ 3 , SR_OUT  5 , ENBV);  
         [0047]     GATE 4 =NAND (SR_OUT_ 4 , SR_OUT_ 5 , ENBV).  
         [0048]     As shown in  FIG. 3 , the output signals SR_OUT_ 1 ˜SR_OUT_ 4  from the shift register stage  330  is passed by the switch  350  into the switch  370 , so the switch  350  is not shown in  FIGS. 6 and 7 .  
         [0049]      FIGS. 8   a ˜ 8   d  show signal paths under normal/reverse scan and normal/half resolution modes of  FIG. 3 .  
         [0050]      FIG. 8   a  shows the signal paths under normal scan and normal resolution modes. Under this case, the transmission gates TM 352 , TM 353 , TM 356  and TM 357  in the switch  350  are conducted and the transmission gates TM 371  and TM 375  in the switch  370  are conducted. The pulse STVUI is fed into the shift register SR 311  and the pulse STVBO is generated from the shift register SR 317 . The pulse STVBI is fed into the NAND 4  as an input.  
         [0051]      FIG. 8   b  shows the signal paths under normal scan and half resolution modes. Under this case, the transmission gates TM 352 , TM 353 , TM 356  and TM 357  in the switch  350  are conducted and the transmission gates TM 373  and TM 377  in the switch  370  are conducted. The pulse STVUI is fed into the shift register SR 311  and the pulse STVBO is generated from the shift register SR 317 . The pulse STVBI is fed into the NAND 4  as an input.  
         [0052]      FIG. 8   c  shows the signal paths under reverse scan and normal resolution modes. Under this case, the transmission gates TM 351 , TM 354 , TM 355  and TM 358  in the switch  350  are conducted and the transmission gates TM 371  and TM 375  in the switch  370  are conducted. The pulse STVBI is fed into the shift register SR 317  and the pulse STVUO is generated from the shift register SR 311 .  
         [0053]      FIG. 8   d  shows the signal paths under reverse scan and half resolution modes. Under this case, the transmission gates TM 351 , TM 354 , TM 355  and TM 358  in the switch  350  are conducted and the transmission gates TM 373  and TM 377  in the switch  370  are conducted. The pulse STVBI is fed into the shift register SR 317  and the pulse STVUO is generated from the shift register SR 311 .  
         [0054]     By the embodiment, a dual resolution circuit configuration for supporting the normal resolution mode and the half resolution mode is achieved. The dual resolution circuit configuration is cost-effective and good performance.  
         [0055]      FIG. 9  shows an electronic device according to another embodiment of the invention. In  FIG. 9 , the electronic device  900  at least includes a display panel  920  and the display panel  920  at least includes a dual resolution circuit  940  for supporting dual resolution display modes in the display panel  920 . The dual resolution circuit  940  are for example, the same or similar to the dual resolution circuit  300  in  FIG. 3 . The electronic device may be, for example but not limited to, a PDA (personal digital assistance), a mobile phone etc. The signals STVUO (start pulse up out) and STVBO (start pulse bottom out) are used for circuit functional test.  
         [0056]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.