Abstract:
A integrated circuit device made using LCD-COG (liquid crystal display-chip on glass) technique is disclosed. The integrated circuit device comprises a substrate, a plurality of dies having surfaces with a plurality of compliant bumps thereon. The compliant bumps are rearranged in any area of the dies for electrically connecting the dies and the substrate. The joint area of the bumps after rearrangement is smaller than the joint area of the bumps on the center. An adhesive is daubed on the joint area of the substrate and the dies for the purpose of jointing the substrate and the dies. By changing the position of the compliant bumps so that they are centrally corresponded on the dies without changing the electrical characteristics and the wiring arrangement of the dies, costs are lowered, reliability is increased and the glass substrate is less easily bent.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This Application is a Continuation-in-Part of application Ser. No. 11/094,198, filed on 31 Mar. 2005, and entitled FLIP CHIP DEVICE. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the invention  
         [0003]     The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device using a LCD-COG (liquid crystal display-chip on glass) technique.  
         [0004]     2. Description of the Prior Art  
         [0005]     In flip chip technology the jointed surface of the chip and the substrate form a pad or bump replacing the lead frame used in wire bonding technology. By directly stressing the bump or pad of the jointed surface of the chip and the substrate, electric conduction of the circuit is achieved. Recently, due to advances in the related technology, electronic products are becoming increasingly smaller and lightweight, so the applications of flip chip technology are increasing day by day.  
         [0006]     The flip chip device of the prior art is the surface of the chip and the bumps formed by the substrate; the surface of the substrate is daubed with an adhesive and then the chip and the substrate are stressed to complete the flip chip device. Because the thermal expansion coefficient of the chip is different from that of the glass substrate, it may result in a certain degree of warp causing a disproportionate gap in the center and on the edge of the IC chip.  
         [0007]     In order to improve upon the above stated disadvantages, U.S. Pat. No. 5,508,228 discloses “compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same”. As shown in  FIG. 1 , a compliant bump includes an IC chip  10 , a compliant bump  14  covering a metal layer  16  thereon is formed on a bond pad  12  and connected to a glass base  18 .  
         [0008]      FIG. 2  shows U.S. Pat. No. 6,084,301 that discloses “Bump structure and method of manufacture”. A compliant bump includes an IC chip  20  with a plurality of conductive joints  22  and a protective film  26  covering the joints  22 . A polymer bump  21  is formed on the joints  22  and a conductive metal layer  24  is formed on the polymer bump  21 . Next, a metal layer  25  is formed on the conductive metal layer  24 .  
         [0009]     However, due to the limits of the initial arrangement of the IC, regardless of whether gold bumps or compliant bumps are used, these bumps will always have a ringed-type arrangement.  FIG. 3  shows a plurality of bumps  31  ringed around an IC chip  30 . This arrangement may however, have a negative effect when applied to the COG junction. As shown in  FIG. 4 , which is a schematic view of a warped COG of the flip chip device due to the thermal applied force of the prior art. The IC chip  34  and the substrate  35  are jointed via the bumps  36  and the conductive adhesive  37  (anisotropic conductive film). Because the thermal expansion coefficient of the IC chip  34  is different from that of the glass substrate  35 , it causes a certain degree of warp creating a disproportionate gap in the center and on the edge of the IC chip thereby reducing the reliability of the products.  
         [0010]     The inventor of the present invention recognizes the above shortage should be corrected and special effort has been paid to research this field. The present invention is presented with reasonable design and good effect to resolve the above problems.  
       SUMMARY OF THE INVENTION  
       [0011]     The prime object of the present invention is to provide an integrated circuit device that arranges the bumps in a central area of the die or on any area of the die. The joint area of the bumps after they have been rearranged is smaller than the joint area of the bumps in the center. The present invention reduces costs, increases their reliability and reduces bending.  
         [0012]     For achieving the objects stated above, an integrated circuit device comprises a substrate, a plurality of dies having surfaces, and a plurality of compliant bumps thereon. The compliant bumps are rearranged on any area of the dies for electrically connecting the dies and the substrate. The joint area of the bumps after rearrangement is smaller than the joint area of the bumps on the center, and an adhesive is daubed on a joint area of the substrate and the dies for jointing the substrate and the dies. The compliant bumps are formed with a first metal layer, a bump and a second metal layer. By extending the first metal layer to change the position of the compliant bumps, the compliant bumps are disposed on the dies without changing the electrical characteristics or the wiring arrangement of the dies.  
         [0013]     The integrated circuit device further comprises a plurality of non-connecting electrically compliant bumps disposed in a corner of the die or opposite to a side for maintaining the parallel of the joint.  
         [0014]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. Other advantages and features of the invention will be apparent from the following description, drawings and claims. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  is a schematic view showing the structure of the conductive compliant bump of the prior art;  
         [0016]      FIG. 2  is another schematic view showing a conductive compliant bump structure of the prior art;  
         [0017]      FIG. 3  is a schematic view showing the arrangement of the compliant bumps of the prior art;  
         [0018]      FIG. 4  is a schematic view showing the warped COG of the integrated circuit device due to the thermal applied force of the prior art;  
         [0019]      FIG. 5  is a schematic view showing the structure of the integrated circuit device of the present invention;  
         [0020]      FIG. 6A  is a top view showing the structures of the compliant bumps of the present invention;  
         [0021]      FIG. 6B  is schematic views showing the structures of the compliant bumps of the present invention;  
         [0022]      FIG. 6C  is an extended structure schematic view showing the first embodiment of the compliant bumps of the present invention;  
         [0023]      FIG. 6D  is an extended structure schematic view showing the second embodiment of the compliant bumps of the present invention;  
         [0024]      FIG. 6E  is an extended structure schematic view showing the second embodiment of the compliant bumps of the present invention;  
         [0025]      FIG. 7  is a schematic view showing the second embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0026]      FIG. 8A  is a schematic view showing the third embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0027]      FIG. 8B  is a schematic view showing the fourth embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0028]      FIG. 9A  is a schematic view showing the fifth embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0029]      FIG. 9B  is a schematic view showing the sixth embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0030]      FIG. 10A  is a schematic view showing the seventh embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0031]      FIG. 10B  is a schematic view showing the eighth embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0032]      FIG. 11A  is a schematic view showing the ninth embodiment of the compliant bumps disposed on the chip of the present invention;  
         [0033]      FIG. 11B  is a schematic view showing the tenth embodiment of the compliant bumps disposed on the chip of the present invention; and  
         [0034]      FIG. 11C  is a schematic view showing the eleventh embodiment of the compliant bumps disposed on the die of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0035]     Reference is made to  FIG. 5 , which is  3   a  schematic view showing the structure of the integrated circuit device of the present invention. Included are a substrate  54 , a die  50  which has a surface and a plurality of compliant bumps  52  thereon, the compliant bumps  52  are rearranged on any area of the die  50  for electrically connecting to the die  50  and the substrate  54 . A joint area of the bumps after rearrangement is smaller than a joint area of the bumps on the center, and an adhesive  53  daubed on a joint area of the substrate  54  and the die  50  for jointing the substrate  54  and the die  50 . The rearrangement of the compliant bumps  52  makes a surrounding (or distribution) area smaller than an electrode of the original die  50 . Therein, the adhesive  53  is comprised of an anisotropic conductive film, UV glue, or a non-conductive glue; the substrate is an organic substrate, a ceramic substrate, a glass substrate, a silicon substrate, or a GaAs substrate. The integrated circuit device further comprises a non-conductive adhesive  55  daubed on a non-conductive joint area of the substrate  54  and the die  50  so as to reduce the amount of conductive adhesive required, thereby reducing costs.  
         [0036]     Reference is made to  FIG. 6A  which is a top view showing the structures of the compliant bumps of the present invention. A bump  60  of the compliant bumps  52  is not covered by a second metal layer  62 . The other two opposite side surfaces that don cover the second metal layer  62  block the lateral electrical connection of the adjacent compliant bumps  52  so that the compliant bumps  52  centrally disposed on the center of the die  50  will not short. This is a first embodiment of the present invention. When it is implemented to the compliant bumps  52 , the second metal layer  62  covers one side, two sides, three sides or all of the sides of the bump  60 . Therein, the adhesive  53  is comprised of an anisotropic conductive film.  
         [0037]     Reference is made to  FIG. 6B  which is a schematic view showing the structure of the compliant bumps of the present invention. The compliant bumps are formed with a first metal layer  58 , the bump  60 , and the second metal layer  62 . The second metal layer  62  covers two opposite side surfaces of the bump  60  to connect with the first metal layer  58  for electrically connecting the substrate  54  and the electrodes  56  of the die  50 . Therein, the first metal layer  58  is a Ti—W metal layer, the bump  60  is formed with a polymer, and the second metal layer  62  is an Au metal layer.  
         [0038]     Reference is made to  FIG. 6C  which is an extended structure schematic view showing the first embodiment of the compliant bumps of the present invention. By extending the first metal layer  58  to change the position of the compliant bumps  52 , the compliant bumps  52  are centrally disposed on the die  50  without changing the electrical characteristics and the wiring arrangement of the die  50 . The manufacture of the bump  60  can also use the process of producing the compliant bumps, without changing the number of masks or the number of processes needed, as long as the first metal layer  58  is extended to move the compliant bumps  52  to the center of the die  50 .  
         [0039]     Reference is made to  FIG. 6D  which is an extended structure schematic view showing the second embodiment of the compliant bumps of the present invention. By extending the first metal layer  58  and the second metal layer  62  to change the position of the compliant bumps  52  simultaneous, the compliant bumps  52  are centrally disposed on the die  50  without changing the electrical characteristics and the wiring arrangement of the die  50 . The manufacture of the bump  60  can also use the process of producing the compliant bumps, without changing the number of masks or the number of processes needed, as long as the first metal layer  58  and the second metal layer  62  are extended to move the compliant bumps  52  to the center of the die  50 .  
         [0040]     Reference is made to  FIG. 6E  which is an extended structure schematic view showing the second embodiment of the compliant bumps of the present invention. By extending the second metal layer  62  to change the position of the compliant bumps  52 , the compliant bumps  52  are centrally disposed on the die  50  without changing the electrical characteristics and the wiring arrangement of the die  50 . The manufacture of the bump  60  can also use the process of producing the compliant bumps, without changing the number of masks or the number of processes needed, as long as the second metal layer  62  is extended to move the compliant bumps  52  to the center of the die  50 .  
         [0041]     Reference is made to  FIG. 7 , which is a schematic view showing the second embodiment of the compliant bumps disposed on the die of the present invention. Included are a die  72  which has a surface and a plurality of compliant bumps  74  thereon, the compliant bumps  74  are centrally corresponded on the die  72 , and a plurality of non-connecting electrically compliant bumps  76  are disposed in a corner of the die  72  or opposite to a side of the compliant bumps for maintaining the parallel of the joint.  
         [0042]     Reference is made to  FIG. 8A , which is a schematic view showing the third embodiment of the compliant bumps disposed on the die of the present invention. Included are a die  80  and a plurality of compliant bumps  82  disposed on reduced distance from the second sides of the die  80 . Therein, the reduced distance is smaller than the die  80  areas.  
         [0043]     Reference is made to  FIG. 8B , which is a schematic view showing the fourth embodiment of the compliant bumps disposed on the die of the present invention. Included are a die  80  and a plurality of compliant bumps  82  disposed on reduced distance from the second side of the die  80 , and a plurality of non-connecting electrically compliant bumps  84  that are disposed in a corner of the die  80  or opposite to a side of the compliant bumps for maintaining the parallel of the joint. Therein, the reduced distance is smaller than the die  80  areas.  
         [0044]     Reference is made to  FIG. 9A , which is a schematic view showing the fifth embodiment of the compliant bumps disposed on the die of the present invention. Included are a die  80  and a plurality of compliant bumps  92  centrally disposed on reduced distance from the other sides of the die  80 . Therein, the reduced distance is smaller than the die  80  areas.  
         [0045]     Reference is made to  FIG. 9B , which is a schematic view showing the sixth embodiment of the compliant bumps disposed on the die of the present invention. Included is a die  80  and a plurality of compliant bumps  92  centrally disposed on reduced distance from the other sides of the die  80 , and a plurality of non-connecting electrically compliant bumps  94  disposed in a corner of the die  80  or opposite to a side of the compliant bumps for maintaining the parallel of the joint.  
         [0046]     Reference is made to  FIG. 10A , which is a schematic view showing the seventh embodiment of the compliant bumps disposed on the die of the present invention. Included is a die  80  and a plurality of compliant bumps  98  centrally disposed on reduced distance whose diagonal lines are half of the length of the die  80 . Therein, the reduced distance is smaller than the die  80  areas.  
         [0047]     Reference is made to  FIG. 10B , which is a schematic view showing the eighth embodiment of the compliant bumps disposed on the die of the present invention. Included is a die  80  and a plurality of compliant bumps  98  centrally disposed on reduced distance whose diagonal lines are half of the length of the die  80 , and a plurality of non-connecting electrically compliant bumps  99  that are disposed in a corner of the die  80  or opposite to a side of the compliant bumps for maintaining the parallel of the joint. Therein, the reduced distance is smaller than the die  80  areas.  
         [0048]     Reference is made to  FIG. 11A , which is a schematic view showing the ninth embodiment of the compliant bumps disposed on the die of the present invention. Included is a die  80  and a plurality of compliant bumps  100  centrally disposed on one side of the die  80 .  
         [0049]     Reference is made to  FIG. 11B , which is a schematic view showing the tenth embodiment of the compliant bumps disposed on the die of the present invention. Included is a die  80  and a plurality of compliant bumps  100  centrally disposed on one side of the die  80 , and a plurality of non-connecting electrically compliant bumps  102  that are disposed in a corner of the die  80  or opposite to a side of the compliant bumps for maintaining the parallel of the joint.  
         [0050]     Reference is made to  FIG. 11C , which is a schematic view showing the eleventh embodiment of the compliant bumps disposed on the die of the present invention. Included is a die  80  and a plurality of compliant bumps  100  centrally disposed on an electrode outside of the die  80 , and a plurality of non-connecting electrically compliant bumps  102 A and  102 B that are disposed in a corner of the die  80  or opposite to a side of the compliant bumps  102 B for maintaining the parallel of the joint.  
         [0051]     The characteristics and efficiencies of the present invention are described below:  
         [0052]     1. The bumps inwardly disposed on the center of the die avoid the delamination of the adhesives because of thermal stress, thereby maintaining the quality of the inner joints.  
         [0053]     2. The joints of the bumps inwardly assembled on the center of the die maintain the same resistance value of the joints.  
         [0054]     3. The position of the bumps move inwardly to extend the distance between the joints thereby prolonging their user life.  
         [0055]     4. A non-conductive adhesive is used on a non-conductive joint area to reduce costs added in the prior art due to the need for a conductive adhesive.  
         [0056]     5. The present invention avoids the bending of the glass substrate due to adhesive bleeding of the prior art.  
         [0057]     Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.