Abstract:
A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This is a continuation application of and claims priority from U.S. application Ser. No. 13/628,726, filed on Sep. 27, 2012, the entire contents of which are incorporated herein by reference. 
     
    
     FIELD OF INVENTION 
       [0002]    The present invention relates generally to field effect transistors, and more specifically, to nanowire field effect transistors. 
       DESCRIPTION OF RELATED ART 
       [0003]    Nanowire field effect transistor (FET) devices include a nanowire arranged on a substrate. A gate stack is arranged conformally on a channel region of the nanowire. Source and drain regions of the nanowire extend outwardly from the channel region. 
         [0004]    As the size of semiconductor devices decreases, it has become desirable to increase the density of the arrangement of FET devices on a substrate. 
       BRIEF SUMMARY 
       [0005]    According to an embodiment of the present invention, nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate. 
         [0006]    According to another embodiment of the present invention, a nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate, a first gate stack disposed about the first nanowire, and a second gate stack disposed about the second nanowire. 
         [0007]    According to yet another embodiment of the present invention, a nanowire field effect transistor device includes a first elliptically shaped nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second elliptically shaped nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a first plane, the plane arranged substantially orthogonal to a second plane defined by a planar surface of the substrate. 
         [0008]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0009]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0010]      FIG. 1  illustrates a side view of a semiconductor-on-insulator (SOI) substrate. 
           [0011]      FIG. 2  illustrates a top view of  FIG. 1 . 
           [0012]      FIG. 3  illustrates a side view the patterning of the SOI substrate. 
           [0013]      FIG. 4  illustrates a top view of  FIG. 3 . 
           [0014]      FIG. 5  illustrates a side view of the formation of a dummy gate stack. 
           [0015]      FIG. 6  illustrates a top view of  FIG. 5 . 
           [0016]      FIG. 7  illustrates a side view of the formation of source and drain regions  7 . 
           [0017]      FIG. 8  illustrates a top view of  FIG. 7 . 
           [0018]      FIG. 9  illustrates a side view of the e formation of a capping layer. 
           [0019]      FIG. 10  illustrates a top view of  FIG. 9 . 
           [0020]      FIG. 11  illustrates a side view of the removal of the dummy gate stack. 
           [0021]      FIG. 12  illustrates a top view of  FIG. 11 . 
           [0022]      FIG. 13  illustrates a side view of the formation of an optional cavity. 
           [0023]      FIG. 14  illustrates a top view of  FIG. 13 . 
           [0024]      FIG. 15  illustrates a side view following the removal of exposed portions of the sacrificial layers. 
           [0025]      FIG. 16  illustrates a top view of  FIG. 15 . 
           [0026]      FIG. 17  illustrates a perspective view of  FIG. 15 . 
           [0027]      FIG. 18  illustrates a perspective view following an optional removal of portions of the nanowires. 
           [0028]      FIG. 19  illustrates a side view of the formation of a dielectric layer. 
           [0029]      FIG. 20  illustrates a top view of  FIG. 19 . 
           [0030]      FIG. 21  illustrates a side view a capping layer formed in the cavity. 
           [0031]      FIG. 22  illustrates a top view of  FIG. 21 . 
           [0032]      FIG. 23  illustrates a cut away view along the line  23  of  FIG. 22 . 
           [0033]      FIG. 24  illustrates a cut away view along the line  24  of  FIG. 22 . 
       
    
    
     DETAILED DESCRIPTION 
       [0034]    As the size of semiconductor devices decreases, it has become desirable to increase the number or density of FET devices arranged on the substrates of the semiconductor devices. In this regard, the methods and resultant devices described below provide for an arrangement of stacked nanowire FET devices. The stacking of the nanowire FET devices allows a number of FET devices to occupy a space on the substrate. 
         [0035]      FIG. 1  illustrates a side view and  FIG. 2  illustrates a top view of a semiconductor-on-insulator (SOI) substrate having an insulator layer  102  and a sacrificial layer  104  including for example, a first semiconductor material such as, for example, SiGe, Ge, Si:C, and GaAs disposed on the insulator layer  102 . A semiconductor layer  106  including a second semiconductor material such as, for example, Si is arranged on the sacrificial layer  104 , a second sacrificial layer  104  is arranged on the semiconductor layer  106 , and a second semiconductor layer  106  is arranged on the second sacrificial layer  104 . A hardmask layer  108  that includes, for example, an oxide material is arranged on the second semiconductor layer  106 . Though the illustrated embodiment includes two pairs  101  of sacrificial layers  104  and semiconductor layers  106 , alternate embodiments may include any number of pairs  101 . The first semiconductor material and the second semiconductor material include dissimilar materials. (The semiconductor material chosen for the semiconductor layer  106  will become the material used in the channel region of the nanowire FET device described below.) 
         [0036]      FIG. 3  illustrates a side view and  FIG. 4  illustrates a top view of the resultant structure following the patterning of the hardmask layer  108  and the pairs  101  of layers  104  and  106 . The patterning may include, for example a photolithographic patterning and etching process such as, for example reactive ion etching (RIE) that removes exposed portions of the layers  104  and  106  and exposes portions the insulator layer  102 . 
         [0037]      FIG. 5  illustrates a side view and  FIG. 6  illustrates a top view of the formation of a dummy gate stack  502  and spacers  504 . The dummy gate stack  502  is formed by depositing a layer dummy gate stack material such as, for example, polysilicon conformally over the exposed portions of the insulator layer  102 , the hardmask layer  108  and the layers  104  and  106 . A photolithographic patterning and etching process is performed to remove exposed portions of the dummy gate stack material and pattern the dummy gate stack  502 . The spacers  504  may be formed by, for example, depositing a conformal layer of spacer material such as a nitride or oxide material over the exposed portions of the insulator layer  102 , the hardmask layer  108  and the layers  104  and  106  and the dummy gate stack  502 . An etching process is performed to remove portions of the spacer material layer and define the spacers  504 . 
         [0038]      FIG. 7  illustrates a side view and  FIG. 8  illustrates a top view of the formation of source and drain regions  702  and  704  respectively. The source and drain regions  702  and  704  may be formed by, for example, removing the exposed portions of the hard mask layer  108  and performing an epitaxial growth process of an epitaxial semiconductor material such as, for example, epi-silicon or epi-germanium. The source and drain regions  702  and  704  may be doped with dopants, by for example, an ion implantation process, or during the epitaxial growth process. 
         [0039]      FIG. 9  illustrates a side view and  FIG. 10  illustrates a top view of the resultant structure following the formation of a capping layer  902  over the source and drain regions  702  and  704 . The capping layer  902  may be formed by, for example, the deposition of a layer of insulator material such as an oxide or nitride material followed by a planarization process such as chemical mechanical polishing (CMP). 
         [0040]      FIG. 11  illustrates a side view and  FIG. 12  illustrates a top view of the resultant structure following the removal of the dummy gate stack  502  (of  FIG. 10 ). The dummy gate stack  502  may be removed by, for example, a selective etching process that removes the dummy gate stack  502 . The removal of the dummy gate stack  502  forms a cavity  1102  that exposes portions of the hardmask  108 , the insulator layer  102 , and the pairs  101  of layers  104  and  106 . 
         [0041]      FIG. 13  illustrates a side view and  FIG. 14  illustrates a top view of the resultant structure following the formation of an optional cavity  1302  formed below the layers  104  and  106 . In this regard, exposed portions of the insulator layer  102  may be removed using an anisotropic etching process. An isotropic etching process may be performed to remove regions of the insulator layer  102  below the first sacrificial layer  104   a.  Exposed portions of the hardmask layer  108  (of  FIG. 11 ) may also be removed. 
         [0042]      FIG. 15  illustrates a side view,  FIG. 16  illustrates a top view, and  FIG. 17  illustrates a perspective view of the resultant structure following the removal of exposed portions of the sacrificial layers  104 . The exposed portions of the sacrificial layers  104  may be removed with, for example, a selective isotropic etching process that removes the exposed portions of the sacrificial layers  104  (e.g., SiGe material) without appreciably removing exposed portions of the semiconductor layers  106  (e.g., Si material). The resultant structure defines nanowires  1502  arranged in the cavity  1102  that are suspended above the insulator layer  102 . 
         [0043]      FIG. 18  illustrates a perspective view of the resultant structure following an optional removal of portions of the nanowires  1502  to round the edges and reduce the size of the nanowires  1502  such that the nanowires  1502  have an elliptical cross-sectional shape. The nanowires  1502  may be rounded by, for example, performing a hydrogen annealing process.  FIG. 18  includes lines  1801  and  1803  that illustrate the longitudinal axes of the nanowires  1502   a  and  1502   b  respectively. The longitudinal axes of the nanowires  1502   a  and  1502   b  define a plane that is substantially orthogonal to the plane defined by the lines  1805  and  1807  defined by the planar surface of the insulator layer  102  that is in contact with the source and drain regions  702  and  704 . 
         [0044]      FIG. 19  illustrates a side view and  FIG. 20  illustrates a top view of the formation of a dielectric layer  1902  in the cavity  1102 . The dielectric layer  1902  may include, for example, a high-K dielectric material that is formed conformally about the nanowires  1502 . The dielectric layer  1902  may be formed along the sidewalls of the spacers  504  and over the exposed portions of the insulator layer  102 . Following the formation of the dielectric layer  1902 , a gate metal layer  1904  may be formed around the dielectric layer  1902  on the nanowires  1502 . The dielectric layer  1902  and the metal gate layer  1904  formed about the nanowires  1502  define a gate stack  1906  arranged around a channel region of the nanowires  1502 . The dielectric layer  1902  and the gate metal layer  1904  may each include a single layer of material or multiple layers of materials. 
         [0045]      FIG. 21  illustrates a side view and  FIG. 22  illustrates a top view following the formation of a capping layer  2102  that is formed in the cavity  1102 . The capping layer  2102  may include, for example, a polysilicon material that may be deposited in the cavity  1102  and about the nanowires  1502  (of  FIG. 19 ).  FIG. 23  illustrates a cut away view along the line  23  (of  FIG. 22 ).  FIG. 24  illustrates a cut away view along the line  24  (of  FIG. 22 ). 
         [0046]    Following the formation of the capping layer  2102 , conductive vias (not shown) may be formed in the capping layer  902  to provide electrical contacts to the source and drain regions  702  and  704 . 
         [0047]    Though the illustrated embodiments include an arrangement of a single pair of vertically stacked FET devices, alternate embodiments may include any number of FET devices in a vertical stack. In such embodiments additional pairs  101  of layers  104  and  106  may be disposed on each other to provide for vertical stacks of nanowire FET devices having any number of nanowire FET devices in a vertical stack. 
         [0048]    The illustrated exemplary embodiments provide for a method and resultant structure that includes nanowire FET devices disposed in a vertically stacked arrangement over an insulator substrate. Such an arrangement increases the density of the FET devices arranged on the substrate. 
         [0049]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0050]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 
         [0051]    The diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0052]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.