Abstract:
A netlist generating apparatus including a memory configured to store logic design data and a processor configured to execute an operation. The operation including selecting paths with which names of instances after logic synthesis match names of modules before being uniquified during the logic synthesis by referring to violation data for paths of the instances and a correspondence table in which the modules are associated with paths of the instances, extracting a path with worst violation data from selected paths by comparing violation data of the selected paths, and adjusting a timing of the extracted path with the worst violation data and generating a netlist.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2010-196195, filed on Sep. 1, 2010, the entire contents of which are incorporated herein by reference. 
       FIELD 
       [0002]    The embodiments discussed herein are related to a netlist generating apparatus and method. 
       BACKGROUND 
       [0003]    There have been logic synthesis tools that automate logic synthesis for generating a netlist (a gate circuit) from a description, such as a register-transfer-level (RTL), of an integrated circuit. The logic synthesis tool generates a netlist from an input RTL so that a circuit is formed of logic gates that are optimum from viewpoints such as timing, area, and power consumption. 
         [0004]    With the logic synthesis tool, in cases where a module defined by a user is present in an input RTL, and the module is used as an instance a plurality of times, it is typical that replacement processing of a module name is automatically performed so that the module that each instance refers to is unique. In this case, mapping to a logic gate, timing analysis, and adjustment for improvement in timing are performed after the replacement processing. 
         [0005]    The term “module” as used herein means a definition for a logic circuit, and the term “instance” means an entity of a logic circuit itself generated from a definition. The word “unique” represents a state in which there is only one entity for one definition, and the word “nonunique” represents a state in which there are a plurality of entities for one definition. 
         [0006]    There is known a technique in which, at the time of timing adjustment during logic synthesis, pins of a module are left as net information, so that layering of the module can be performed again after the logic synthesis, and replacing function blocks organized in a hierarchical manner makes it possible to readily modify logic after the logic synthesis. There are also known a netlist generating method for facilitating analysis with physical information taken into consideration during timing verification, and a technique for performing automatic arrangement with physical information taken into consideration. 
         [0007]    Related art is disclosed in Japanese Laid-open Patent Publication No. 2005-122577 and Japanese Laid-open Patent Publication No. 2006-164132. 
         [0008]    Unfortunately, conventional techniques in which, during logic synthesis, a module is made unique and a netlist is generated have the following problems. 
         [0009]    First, making a module unique results in generation of a plurality of new modules in a netlist, and therefore the need for physical design for each module arises. In the case of a design method mainly using an automatic tool such as an application specific integrated circuit (ASIC), making a module unique hardly affects the man-hours taken for physical design. However, in the case of a design method that mainly involves operation performed by a user, such as in the case of a processor, if a module is made unique, each module generated as a result of this gives rise to the need for an operation used in physical design. This greatly affects the man-hours taken for physical design. 
         [0010]    The timings of modules differ from one another depending on what peripheral logics are connected to the modules with which instantiation is performed in a higher layer, and depending on the timing constraints of modules for input and output interfaces. The timing violation values differ between modules with which instantiation is performed. 
         [0011]    For example, if a “module_A” having a path  1  and a path  2  is made unique, and, as a result, a “module_A 1 ” and a “module_A 2 ” are obtained, there is a case where the path  1  of the “module_A 1 ” is a target of timing adjustment, and the path  2  is not a target, whereas the path  1  of the “module_A 2 ” is not a target of timing adjustment, and the path  2  is a target. 
         [0012]    In this case, the “module_A” with which timing adjustment of the path  1  and timing adjustment of the path  2  are simultaneously performed does not exist. Thus, in the case of putting an optimum module as an IP macro into a library, the optimum module is not selected from modules that have been made unique. 
       SUMMARY 
       [0013]    A netlist generating apparatus including a memory configured to store logic design data and a processor configured to execute an operation. The operation including selecting paths with which names of instances after logic synthesis match names of modules before being uniquified during the logic synthesis by referring to violation data for paths of the instances and a correspondence table in which the modules are associated with paths of the instances, extracting a path with worst violation data from selected paths by comparing violation data of the selected paths, and adjusting a timing of the extracted path with the worst violation data and generating a netlist. 
         [0014]    The object and advantages of the invention will be realized and attained at least by the elements, features, and combinations particularly pointed out in the claims. 
         [0015]    It is to be understood that both the foregoing general description and the following detailed description are example and explanatory and are not restrictive of the invention, as claimed. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0016]      FIG. 1  is a schematic diagram of a netlist generating apparatus according to this embodiment. 
           [0017]      FIG. 2  is a data association diagram in the case where modules are made so that each module is unique, and a netlist is generated, in a comparative example. 
           [0018]      FIG. 3  is a flowchart in the case where modules are made so that each module is unique, and the netlist is generated, in the comparative example. 
           [0019]      FIG. 4  is a data association diagram of the technique of this disclosure. 
           [0020]      FIG. 5  is a flowchart illustrating a processing operation of a logic synthesis program in  FIG. 4 . 
           [0021]      FIG. 6  is a flowchart illustrating a processing operation of a netlist generating program in  FIG. 4 . 
           [0022]      FIG. 7  is a specific example of a gate-level database. 
           [0023]      FIG. 8  is a specific example of a violation database. 
           [0024]      FIG. 9  is a specific example of a correspondence table. 
           [0025]      FIG. 10  is a specific example of an updated violation database. 
           [0026]      FIG. 11  is a specific example of a netlist after timing adjustment by a method of the embodiment. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0027]      FIG. 1  is a schematic diagram of a netlist generating apparatus according to this embodiment. A netlist generating apparatus  10  illustrated in  FIG. 1  has a CPU (central processing unit), storage devices, such as a memory, and a hard disk drive (HDD). Processes to be described below that the netlist generating apparatus  10  performs are executed by the CPU. The CPU is configured to perform processes as a path selection unit  11 , a violation comparison unit  12 , and a timing adjustment unit  13 . Data that the CPU reads and data that the CPU outputs are stored in storage devices such as a memory and an HDD. 
         [0028]    The path selection unit  11  refers to a violation database D 11  and a correspondence table D 12 , and selects paths with which the names of instances match the names of modules. The correspondence table D 12  is a database in which, for logic design data of an integrated circuit obtained by logic synthesis, modules before being made unique during logic synthesis are associated with paths of instances after the logic synthesis. The violation database D 11  is a database that holds, as violation data, timing violation values for paths of instances. 
         [0029]    The violation comparison unit  12  compares violation data of paths selected by the path selection unit  11 , and leaves the path with the worst violation data and deletes other paths. 
         [0030]    The timing adjustment unit  13  refers to a gate-level database D 13  in which gate-level netlists are registered, and adjusts the timings of the module maintained as a result of processing of the violation comparison unit  12 , and generates a netlist D 14 . 
         [0031]      FIG. 2  is a data association diagram in the case where modules are made so that each module is unique, and a netlist is generated, as a comparative example. In the case where modules are made so that each module is unique, and a netlist is generated, a logic synthesis program  20  generates a netlist D 24  using an RTL_D 21 , a library D 22 , and timing constraints D 23 . 
         [0032]      FIG. 3  illustrates a flowchart of the case where modules are made so that each module is unique, and a netlist is generated, as the comparative example. In the flow illustrated in  FIG. 3 , the logic synthesis program  20  selects one user-defined module from the RTL_D 21 , and determines whether the selected user-defined module is used as an instance a plurality of times (S 101 ). If the selected module is used a plurality of times (S 101 , Yes), then the module is replaced so that the module is unique (S 102 ). 
         [0033]    If the selected module is not used a plurality of times (S 101 , No), or after the module has been made unique in S 102 , the logic synthesis program  20  determines whether all modules in the RTL_D 21  have been inspected (S 103 ), and returns to S 101  if there remains a module that has not yet been inspected (S 103 , No). 
         [0034]    After all modules in the RTL_D 21  have been inspected (S 103 , Yes), the logic synthesis program  20  performs logic gate mapping referring to the library D 22  (S 104 ), so that a gate-level netlist D 13  is generated. 
         [0035]    The logic synthesis program  20  analyzes timings referring to the generated gate-level netlist D 13 , the library D 22 , and the timing constraints D 23  (S 105 ), so that a timing report is generated. 
         [0036]    Then, referring to the gate-level netlist D 13 , the library D 22 , and a timing report, the logic synthesis program  20  adjusts timings (S 106 ), and outputs the netlist D 24 . 
         [0037]      FIG. 4  is a data association diagram of the technique of this disclosure. In the technique of this disclosure, the logic synthesis program  20  generates the violation database D 11 , the correspondence table D 12 , and the gate-level database D 13  from the RTL_D 21 , the library D 22 , and the timing constraints D 23 . A netlist generating program  10   a,  which causes a computer to operate as the netlist generating apparatus  10 , generates the netlist D 14  from the library D 22 , the violation database D 11 , the correspondence table D 12 , and the gate-level database D 13 . 
         [0038]      FIG. 5  is a flowchart illustrating a processing operation of the logic synthesis program  20  in  FIG. 4 . In the flow illustrated in  FIG. 5 , the logic synthesis program  20  selects one user-defined module from the RTL_D 21 , and determines whether the selected user-defined module is used as an instance a plurality of times (S 201 ). If the selected module is used a plurality of times (S 201 , Yes), then the module is replaced so that the module is unique (S 202 ). 
         [0039]    If the selected module is not used a plurality of times (S 201 , No), or after the module has been made unique in S 202 , the logic synthesis program  20  determines whether all modules in the RTL_D 21  have been inspected (S 203 ), and returns to S 201  if there remains a module that has not yet been inspected (S 203 , No). 
         [0040]    After all the modules in the RTL_D 21  have been inspected (S 203 , Yes), the logic synthesis program  20  selects one module and determines whether the selected module is a module that has been made unique (S 204 ). If the selected module is a module that has been made unique (S 204 , Yes), then the module is restored to its nonunique state and is integrated (S 205 ). 
         [0041]    If the selected module has not been made unique (S 204 , No), or after the module has been made nonunique in S 205 , the logic synthesis program  20  determines whether all modules in the RTL_D 21  have been inspected as to whether they have been made nonunique (S 206 ), and returns to S 204  if there remains a module that has not yet been inspected (S 206 , No). 
         [0042]    As such, in the logic synthesis program  20 , processing until a module used as an instance a plurality of times in the RTL is replaced so that each module is unique is automated prior to mapping to the logic gate. The technique of this disclosure therefore causes the logic synthesis program  20  to execute processing of restoring a module that has become unique to its original, nonunique state. 
         [0043]    After all modules in the RTL_D 21  have been inspected as to whether they have been made nonunique (S 206 , Yes), the logic synthesis program  20  performs logic gate mapping referring to the library D 22  (S 207 ), so that the gate-level database D 13  is generated. 
         [0044]    The logic synthesis program  20  analyzes timings referring to the generated gate-level database D 13 , the library D 22 , and the timing constraints D 23  (S 209 ), so that a timing report is generated. 
         [0045]    Then, the logic synthesis program  20  generates the violation database D 11  from the timing report (S 210 ), and generates the correspondence table D 12  from the gate-level database D 13  (S 208 ). 
         [0046]    As such, in a state where nonunique modules are made, the technique of this disclosure performs processing of mapping to a logic gate (S 207 ) and generates the gate-level database D 13 , which is a database of gate-level netlists. It is to be noted that operations S 201  to S 207  of  FIG. 5  are examples for generating the gate-level database D 13 , and may be appropriately reordered. For example, the gate-level database D 13  can be generated in the order in which operations S 204  to S 206  are performed after operation S 207  has been performed. 
         [0047]    Timings are analyzed using a gate-level netlist, and, based on the obtained timing report, paths where violations are detected are stored in a database. This database is the violation database D 11 . 
         [0048]    The correspondence table D 12  is a table indicating correspondence between instance names with hierarchical paths and module names for all latches and flip-flops that are present in a circuit. For example, in the case where a path is AAA/BBB/CCC/DDD, the hierarchy instance name is AAA/BBB/CCC, the in-module instance name is DDD, the instance name with a hierarchical path is AAA/BBB/CCC/DDD, and the module name is the name of a module from which DDD is instantiated. 
         [0049]      FIG. 6  is a flowchart illustrating a processing operation of the netlist generating program  10   a  in  FIG. 4 . In the flow illustrated in  FIG. 6 , if paths with the same module and the same instance name are present in the violation database D 11  (S 301 , Yes), then the netlist generating program  10   a  maintains the path with the worst violation data, among the paths with the same module and the same instance name, and discards other paths from the database (S 302 ). In this way, the path with the worst violation data is extracted. 
         [0050]    After S 302 , or if a path with the same module and the same instance name is absent (S 301 , No), the netlist generating program  10   a  determines whether the inspections of S 301  have been finished for all paths of the violation database D 11 . 
         [0051]    If there remains a path on which the inspection of S 301  has not yet been finished (S 303 , No), then the netlist generating program  10   a  returns to S 301 . If the inspections of S 301  have been finished on all paths of the violation database D 11  (S 303 , Yes), then the netlist generating program  10   a  performs timing adjustment targeted to paths remaining in the post-change violation database D 11  referring to the gate-level database D 13  (S 304 ). As a result of this timing adjustment, the netlist D 14  is generated. 
         [0052]    As such, with inputs from the gate-level database D 13 , the violation database D 11 , and the correspondence table D 12  obtained by the processing in  FIG. 5 , the technique of this disclosure adjusts timings of a netlist in which nonunique modules exist. Therefore, timing adjustment for the netlist in which nonunique modules exist can be realized. 
         [0053]    Among paths present in the violation database, all paths having the same in-module instance name and the same module name are detected. A comparison on a violation value is made among the detected paths. A path with a violation value representing the worst violation is selectively maintained in the violation database D 11 , and timing adjustment processing is performed. In this way, timings are adjusted with reference to the violation value representing the worst violation. Therefore, all violations of timing paths can be eliminated even if the violations are not the worst. 
         [0054]      FIG. 7  is a specific example of the gate-level database D 13 . A circuit block BLK 1  is generated from a module A and has an instance INST 1 . A circuit block BLK 2  is generated from the module A and has the instance INST 1 . A circuit block BLK 3  is generated from a module B and has the instance INST 1  and an instance INST 2 . A circuit block BLK 4  is generated from the module A and has the instance INST 1 . A circuit block BLK 5  is generated from the module B and has the instance INST 1  and the instance INST 2 . 
         [0055]      FIG. 8  is a specific example of the violation database D 11 . Timings are analyzed by the logic synthesis program  20  with the gate-level database D 13  of  FIG. 6 . From a timing report generated here, a violation database as illustrated in  FIG. 8  is generated. 
         [0056]    Specifically, in  FIG. 8 , for the path  1 , “Endpoint: BLK 1 /INST 1  violation: −1.0 ns” is given; for the path  2 , “Endpoint: BLK 2 /INST 1  violation: −2.0 ns” is given; for a path  3 , “Endpoint: BLK 3 /INST 1  violation: −1.5 ns” is given; for a path  4 , “Endpoint: BLK 4 /INST 1  violation: −3.0 ns” is given; and for a path  5 , “Endpoint: BLK 5 /INST 2  violation: −1.0 ns” is given. 
         [0057]    The logic synthesis program  20  generates a correspondence table detailing the correspondence between instance names with hierarchical paths and module names as illustrated in  FIG. 9 . In  FIG. 9 , “BLK 1 /INST 1 ” corresponds to “module_A”, “BLK 2 /INST 1 ” corresponds to “module_A”, “BLK 3 /INST 1 ” corresponds to “module_B”, “BLK 4 /INST 1 ” corresponds to “module_A”, and “BLK 5 /INST 2 ” corresponds to “module_B”. 
         [0058]    The gate-level database D 13 , violation database D 11 , and correspondence table D 12  are input to the netlist generating program  10   a.  As processing before timing adjustment of modules in their nonunique states, paths with which module names match instance names are selected, and the path with the worst violation data is maintained. 
         [0059]    Specifically, among paths related to “module_A” that are present in the violation database illustrated in  FIG. 8 , the path with the worst violation data is searched for. In the correspondence table of  FIG. 9 , an instance name “BLK 1 /INST 1 ” with a hierarchical path “path  1 ” and an instance name “BLK 2 /INST 1 ” with a hierarchical path “path  2 ” have the same in-module instance name “INST 1 ” and the same module name “module_A”. Therefore, values of violations are compared between “path  1 ” and “path  2 ”, and “path  2 ” regarded as the worst is maintained in the violation database. 
         [0060]    Likewise, “path  2 ” and “path  4 ” corresponding to “module_A” are compared, and “path  4 ” is maintained in the database because the violation of “BLK 4 /INST 1 ” has the worst value. For “module_B”, processing is performed similarly. It is to be noted that “path  3 ” and “path  5 ” are different in an in-module instance name, and therefore both the paths are maintained in the database. This results in a violation database illustrated in  FIG. 10 . 
         [0061]    For paths that are present in the violation database illustrated in  FIG. 10 , timing adjustment is performed to generate a netlist. This result is illustrated in  FIG. 11 . In  FIG. 11 , the circuit blocks BLK 1 , BLK 2 , and BLK 4  generated from the module A have the same internal configuration. Likewise, the circuit blocks BLK 3  and BLK 5  generated from the module B have the same internal configuration. 
         [0062]    As described above, with a program, an apparatus and a method according to this embodiment, for logic design data of an integrated circuit obtained by logic synthesis, a violation database and a correspondence table are referred to, and paths with which names of instances match names of modules are selected. Violation data is compared among the selected paths, and the path with the worst violation data is maintained and other paths are discarded. For the module remaining as a result of this, timings are adjusted, so that a netlist is generated. Therefore, regarding a module used as an instance a plurality of times in an RTL, a netlist is generated with the module in its nonunique state. Thus, timing adjustment covering all cases can be performed so as to reduce or prevent the number of objects which a nonunique module is in charge of from becoming insufficient. Such a technique is particularly effective for physical design mainly using manual arrangement. 
         [0063]    All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Although the embodiment(s) of the present invention has(have) been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.