Abstract:
A negative differential resistance (NDR) device is designed and a possible compact device implementation is presented. The NDR device includes a voltage blocker and a current blocker and exhibits high peak-to-valley current ratio (PVCR) as well as high switching speed. The corresponding process and design are completely compatible with contemporary Si CMOS technology and area efficient. A single-NDR element SRAM cell prototype with a compact size and high speed is also proposed as its application suitable for embedded memory.

Description:
CROSS REFERENCE APPLICATIONS 
       [0001]    This application claims priority from U.S. Provisional Patent Application No. 61/056,415, filed on May 27, 2008. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a negative differential resistance (NDR) device and memory using the same. 
         [0004]    2. Description of Prior Art 
         [0005]    A negative differential resistance (NDR) device has the characteristic of negative differential resistance on its current-versus-voltage curve. Namely, the current is decreasing while the voltage is increasing. For example, resonant tunneling diode, tunneling diode, Gunn diode, resonant tunneling transistor and so on are the most common negative differential resistance devices. 
         [0006]    NDR device has great potential in design and application of RF circuits because NDR device has the advantages of fast switching and operating in RF area (the working frequency is up to 1 GHz). Moreover, frequency multiplier, oscillator, multiple-state memory, analog/digital converter, current-and-voltage-level reference, multiple-value counter, multiple-value multiplexer, logic circuit, pulse generator have promising applications based on the NDR device. 
         [0007]    However, previous NDR devices have three primary features hindering their application. First, the processes involved are usually not easy to control or even too complicated to be compatible with Si technology. Second, the peak-to-valley current ratio (PVCR) is usually too small, not high enough for memory applications considering both the switching speed and power consumption. Third, the value of current of those devices might depend on some sensitive factors (tunneling current, trapping effect, etc., for examples), which makes the uniformity of the fabrication becomes very critical and hard to control. 
         [0008]    Random Access Memory (RAM) is a kind of volatile memory, which includes both Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM requires periodical refresh to preserve the data while SRAM preserves data due to self-latching effect. Due to its self-latching feature, the switching speed of SRAM is fast among other semiconductor memory and is used widely nowadays. Typical SRAM is consisted of six transistors and can hold the data even after the write/read operation since the cross coupled inverters formed a negative feedback to latch the data. Although SRAM is faster than DRAM, the price is higher since it needs more area than a typical one-transistor DRAM. 
         [0009]    Since NDR device has bi-stable feature, it can be also applied to design memory. For example, SRAM can be implemented by NDR device in prior art reference. However, the PVCR thereof is not high enough (higher standby power or slower speed), the manufacturing process is complicated and the result-in SRAM might still occupy considerable area. 
       SUMMARY OF THE INVENTION 
       [0010]    Here, we proposed an NDR structure with both high PVCR and fast switching speed, with the additional features of CMOS compatibility and area efficiency. 
         [0011]    In order to achieve the object mentioned above, the NDR device includes a first transistor including a first gate, a first input terminal and a first output terminal; and a second transistor with opposite polarity of the first transistor, and the second transistor including a second gate, a second input terminal and a second output terminal. The first input terminal and the second gate are electrically connected and are applied with substantially the same voltage. The first output terminal is electrically connected to the second input terminal. Therefore, the NDR device provides negative differential resistance between the first input terminal and the second output terminal. 
         [0012]    According to one aspect of the invention, the voltage blocker can be an N-type MOSFET for example, which includes a first drain, a first gate and a first source. The current blocker with the opposite polarity (N/P type) of the voltage blocker can be a P-type MOSFET which includes a second drain, a second gate and a second source. Due to the complementary feature of MOSFET, the voltage blocker can also be a P-type MOSFET as long as the current blocker is an N-type MOSFET. In the former situation, the second source is electrically connected to the first source of the voltage blocker via direct contact (ex: P/N junction) or the current bridge (ex: a metal shunt). A predetermined gate voltage can also be supplied to the first gate of the voltage blocker. The first drain is electrically connected to the second gate. This proposed NDR device can provide negative differential resistance between the first drain and second drain. 
         [0013]    Moreover, according to another aspect of the present invention, by slightly modifying the proposed NDR structure, it can become a memory device. We can do this by including an access transistor, for example, another MOSFET, whose gate connects to a word line in a typical memory design and a bit line electrically connected to one of the other two terminals, for example, drain of the access transistor. The proposed NDR device is electrically connected to, in this example, source of the access transistor. By doing similar operations as the previous SRAM or DRAM, for example, changing the voltage of bit line or word line, the read/write/hold operation can be performed. The data in this exemplary embodiment is stored as the form of voltage difference between the first drain and second drain of the NDR device. 
     
    
     
       BRIEF DESCRIPTION OF DRAWING 
         [0014]    The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which: 
           [0015]      FIG. 1  is a structure diagram of NDR device according to one embodiment of present invention. 
           [0016]      FIG. 2  is an I-V curve for NDR device according to the present invention, where solid line indicates current in log scale and dashed line indicates current in linear scale. 
           [0017]      FIG. 3  is an I-V curve illustrating the operation of the present NDR device invention. 
           [0018]      FIG. 4A  is a circuit diagram of NDR device shown in  FIG. 1 . 
           [0019]      FIG. 4B  is a circuit diagram of NDR device according to another embodiment of present invention. 
           [0020]      FIG. 5  is a structure diagram of NDR memory according to one embodiment of the present invention. 
           [0021]      FIG. 6A  is a circuit diagram of NDR memory according to another embodiment of the present invention. 
           [0022]      FIG. 6B  is a circuit diagram of NDR memory according to still another embodiment of the present invention. 
           [0023]      FIG. 7  is a circuit diagram of the NDR device shown in  FIG. 5 . 
           [0024]      FIG. 8  is an I-V curve for NDR memory according to  FIG. 5 . 
           [0025]      FIG. 9  is the Voltage-time plot showing the memory behavior according to  FIG. 6B . 
           [0026]      FIGS. 10A to 10D  are device structure corresponding to curves I 1 -I 4  in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0027]    Please refer to  FIG. 1 , which is a structure diagram of NDR device according to one embodiment of present invention. The NDR device of present invention includes a voltage blocker  10  and a current blocker  20  electrically connected to the voltage blocker  10 . With reference also to  FIG. 4A , in the embodiment, the voltage blocker  10  is, for example, an enhancement mode N-channel MOSFET; and the current blocker  20  is, for example, a depletion mode P-channel MOSFET. Since there is no external contact on the source region of each transistor, we can reduce the area by directly coupling the two sources as shown in  FIG. 1 . This source-coupled region acts as a bridge for current conduction between the two series connected transistors. In  FIG. 1 , a current bridge  30  is also included in the NDR device of present invention. The current bridge  30  is electrically connected to the first source  16  of the voltage blocker  10  and the second source  26  of the current blocker  20  to provide a current shunt path. Materials like silicide or metal can be used on top of this source-coupled region to provide better current conducting capability between the voltage blocker  10  and the current blocker  20  other than the band-to-band tunneling (BTBT) current intrinsically between first source  16  and second source  26 . Moreover, since there is no lithography involved for this local silicide interconnect, this compact structure as shown in  FIG. 1  not only simplifies the process but also has the area reduction of two contacts and isolation. 
         [0028]    In  FIG. 1 , the channel doping under the gate of the voltage blocker  10  is P type. However, NMOS can also be provided by using N-type channel with gate electrode of suitable work function to switch between enhancement mode and depletion mode. Therefore, specific channel doping is not limitation for the present invention. Moreover, although the exemplary NDR device uses insulation substrate, other kinds of substrates can also be used. 
         [0029]    The voltage blocker  10  includes a first drain  12  (first input terminal), a first gate  14  and a first source (first output terminal)  16 . The current blocker  20  includes a second drain (second output terminal)  22 , a second gate  24  and a second source (second input terminal)  26 . The first source  16  of the voltage blocker  10  is electrically connected to the second source  26  of the current blocker  20 . It should be noted above description for input and output terminal is only for exemplification and the first source  16  can also be defined as the first input terminal because the source-drain symmetric property of MOSFET. Therefore, the scope of the present invention is defined by attached claim and not by the specific exemplary example. 
         [0030]    A predetermined voltage Vd is supplied to the first drain  12  of the voltage blocker  10  and the second gate  24  of the current blocker  20 . Moreover, even in  FIG. 1 , the same voltage Vd is applied to the first drain  12  of the voltage blocker  10  and the second gate  24  of the current blocker  20 , the NDR device according to the present invention still works when substantially the same voltage is applied to the first drain  12  of the voltage blocker  10  and the second gate  24  of the current blocker  20 . Namely, the voltages applied to the first drain  12  of the voltage blocker  10  and the second gate  24  of the current blocker  20  can have slight difference. A gate voltage Vg is supplied to the first gate  14  of the voltage blocker  10 . The second drain  22  of the current blocker  20  is electrically connected to ground. Here, the exact voltage of Vg can be tuned depends on the usage of the NDR device as well as the channel doping of the voltage blocker. 
         [0031]    The operation of the NDR device of present invention will be described in more detail with reference to the I-V curve shown in  FIG. 2  and  FIG. 3 . Please first refer to  FIG. 2 , which shows I-V curve for the NDR device of present invention. Please also refer to  FIG. 1 , at first, the gate voltage Vg is supplied to provide driving voltage for the voltage blocker  10 . The DC voltage Vd is supplied to provide driving voltage for the second gate of the current blocker  20  and the first drain  12  of the voltage blocker  10 . When the DC voltage Vd increases from zero, the I-V curve rises in rapid and proportional fashion, because both of the voltage blocker  10  and the current blocker  20  are turned on. 
         [0032]    Afterwards, the DC voltage Vd increases and two situations occur. First, the voltage blocker  10  will be in saturation region. That means, even if the voltage Vd increases, the conducting current is almost the same (so the voltage blocker  10  has voltage blocking function). Second, the voltage Vd increment will cause the channel of the current blocker  20  to be narrower and eventually turned off so that the conducting current decreases (so the current blocker  20  has current blocking function). The NDR device of present invention will manifest the characteristic of negative differential resistance. Namely, the corresponding current is decreasing while the voltage is increasing. 
         [0033]    In  FIG. 1 , essentially, this NDR device could also be viewed as a gate-modulated “reverse-biased” PNPN structure (or PN structure when the NMOS is turned on) and hence is immune to the usual latch-up issues associated with “forward-biased” PNPN structures as some previous device. Moreover, even though the NDR device is exemplified with MOSFET in  FIG. 1 , those skilled in the art can replace MOSFET with other transistors such as JFET and BJT as long as the transistor are biased to provide voltage blocker function and current block function. The JFET has the same node notation as MOSFET and the modification is straightforward. For BJT, the NMOS  10  and PMOS  20  can be replaced by BJT transistors of different polarities, respectively. 
         [0034]    Please now refer to  FIG. 3  and also to  FIGS. 10A-10D , which show corresponding device structures. Conceptually, the operation principle of this NDR structure can be viewed as two transistors with their own switching behaviors but triggered in a unique sequence by single input. By cross-coupling the drain voltage of the NMOS  10  in  FIG. 1  with the gate voltage of the PMOS  20  in  FIG. 1 , a competition between the “I d -V d  turn on” behavior of the NMOS and the “I d -V g  turn off” behavior of the PMOS is produced. In addition, the source-coupled region “decouples” the voltage change from the sweeping voltage (V d ) to the source side of PMOS  20  but still allows current to flow. To illustrate the origin of the NDR characteristic, the I-V curve of each isolated component is shown in  FIG. 3  with the reduced device structure for each curve in the  FIGS. 10A-10D . First, without the turn-off mechanism from the PMOS (current blocker  20 ), the I-V curve simply becomes “I d -V d ” plot as shown in  FIG. 3  “I 1 ” with the device structure in  FIG. 10A . Second, without the “voltage blocker”, the structure essentially becomes an n +  region connected directly to the source and also cross-coupled to the gate of the PMOS. The increasing V d  cannot be screened by the source-coupled region and this results in a direct current injection. Although the PMOS gate bias is increasing, this transistor cannot be turned off since its source voltage is also increasing, which makes the “V gs ” of the PMOS still larger than its threshold voltage (V t   Dep ). In other words, the field-modulated turn-off mechanism by the depletion mode transistor becomes inefficient at turning off the current since the direct current injection wins over the indirect gate modulation through an oxide. As a result, the current saturates as shown in  FIG. 3  “I 2 ” with the device structure in  FIG. 10B . Next, “I 3 ” with the device structure in  FIG. 10C  shows the I d -V d  curve without the silicide or metal shunt. Namely the current is conducting only through the reverse-biased P-N junction. Unlike the previous two cases, here the NDR behavior is still preserved but with a smaller peak current limited by the BTBT current. As a result, the voltage blocker  10  and current blocker  20  are essential for the proper NDR operation while the addition of current bridge improves the performance. Finally, the “I d -V g ” plot for the depletion mode PMOS is shown in  FIG. 3  “I 4 ” with the device structure in  FIG. 10D  to demonstrate the turn-off behavior once the source is pinned around 0.6V in this example. Conceptually, the resulting NDR behavior in  FIG. 2  can be viewed as the combination of these individual components although we can not directly superimpose them. However,  FIG. 3  confirms that the functions for individual components, such as voltage blocker, current bridge and current blocker, of the proposed NDR structure. 
         [0035]    Furthermore, since V g  is dc-biased to turn on the NMOS, the NDR behavior hence depends on the V g  and this can be used to distinguish the “state of the device”. First, when this structure is at the state with low V d , a further increase in V g  does not change the current since the current is limited by the applied V d . However, if the structure is conducting the valley current at the high V d  biasing state, an increase in V g  turns on the NMOS by reforming the channel, and the pinned potential of the source-coupled region is released. As a result, the current starts to flow and this case is similar in “I 2 ” of  FIG. 3 . In this way, pulsing up the gate voltage of the NMOS can provide the information on which state the NDR structure is in. On the other hand, we can also decrease V g  to turn off the NMOS while it&#39;s not being operated to further reduce the steady state leakage current of this NDR element. 
         [0036]    While  FIG. 4A  shows the equivalent circuit of  FIG. 1 ,  FIG. 4B  is the circuit diagram of NDR device according to another embodiment of present invention. The NDR device includes a voltage blocker  10 ′ and a current blocker  20 ′. In this embodiment, the voltage blocker  10 ′ is an enhancement mode PMOS. The current blocker  20 ′ is a depletion mode NMOS. A DC voltage −Vd is supplied to the drain of the voltage blocker  10 ′ and the gate of the current blocker  20 ′, respectively. The source of the voltage blocker  10 ′ is electrically connected to the source of the current blocker  20 ′. The drain of the current blocker  20 ′ is electrically connected to ground. 
         [0037]    Please refer to  FIG. 5 , which is a structure diagram of an NDR memory according to one embodiment of the present invention. 
         [0038]    Please refer to  FIG. 7 , which is a circuit diagram of the NDR device for the embodiment shown in  FIG. 5 . In this embodiment, the NDR memory is mainly composed of two NDR devices. The NDR memory of present invention includes an access transistor  300 , a word line  400 , a bit line  500 , a first NDR device  100  and a second NDR device  200 . 
         [0039]    The first NDR device  100  includes a first voltage blocker  110  realized by an enhancement mode NMOS and a first current blocker  120  realized by a depletion mode PMOS. The second NDR device  200  includes a second voltage blocker  210  realized by an enhancement mode PMOS and a second current blocker  220  realized by a depletion mode NMOS. The channel doping under the gate of the voltage blocker  110  is, for example, P type. 
         [0040]    The first voltage blocker  110  includes a fifth drain  112 , a fifth gate  114  and a fifth source  116 . The first current blocker  120  includes a sixth drain  126 , a sixth gate  124  and a sixth source  122 . The second voltage blocker  210  includes a third drain  212 , a third gate  214  and a third source  216 . The second current blocker  220  includes a fourth drain  226 , a fourth gate  224  and a fourth source  222 . 
         [0041]    The access transistor  300  is electrically connected to the word line  400  and the bit line  500 . The access transistor  300  is electrically connected to the fifth drain  112 , the sixth gate  124 , the third drain  212 , and the fourth gate  224  through a first point P 1 . A first gate voltage Vg 1  is supplied to the fifth gate  114 . A second gate voltage Vg 2  is supplied to the third gate  214 . The fifth source  116  is electrically connected to the sixth source  122 . A first current bridge  130  is electrically connected to the fifth source  116  and the sixth source  122  to provide a current shunt path. The third source  216  is electrically connected to the fourth source  222 . A second current bridge  230  is electrically connected to the third source  216  and the fourth source  222  to provide current shunt path. 
         [0042]    The first current bridge  130  and the second current bridge  230  are composed of metal silicide or metal. The sixth drain  126  is electrically connected to a second point P 2 , where the potential of the second point P 2  is smaller than the potential of the first point P 1 . The fourth drain  226  is electrically connected to a third point P 3 , where the potential of the third point P 3  is larger than the potential of the first point P 1 . 
         [0043]    This NDR pair (the first NDR device  100  and the second NDR device  200  shown in  FIG. 5 ) looks and functions like a pair of cross-coupled inverters, however, there are two main differences. First, as stated before, the area is less than the cross-coupled inverters since there is no contact between them and only a self-aligned silicide (Salicide) process or metal shunt is needed. Second, this structure is “single-ended” instead of the “double-ended” nature of the cross-coupled inverters structure. That is, the storage node is at the symmetric point P 1  of the structure and there is no “dummy cell” needed when performing the data retrieve. 
         [0044]    Please refer to  FIG. 8 , which shows I-V curve for the NDR memory of present invention. More particularly, N-type curve is for the first NDR device  100  while P-type curve is for the second NDR device  200 . The stable operation point of the NDR memory is the points which the two NDR devices  100  and  200  have the same absolute-value current. Therefore, after the data is written, the logic 0 data or the logic 1 data is stored in the NDR memory (indicated by the dashed-line circle shown in  FIG. 8 ). Moreover, as shown in  FIG. 8 , the voltage value for the point with equal current value for the two characteristic curves can be used for bias point when data is to be read from the NDR memory of present invention. 
         [0045]    With reference to the circuit connection shown in  FIG. 7  and the characteristic curves shown in  FIG. 8 , the NDR memory of the present invention will manifest memory characteristic. The NDR memory of the present invention has Si CMOS compatible manufacturing process, high PVCR and reduced area. 
         [0046]    Please refer to  FIGS. 6A and 6B , which show the circuit diagrams of an NDR memory according to another embodiments of the present invention, where only one NDR device (first NDR device  100  or the second NDR device  200 ) is used to implement the memory function. More particularly, the embodiment shown in  FIG. 6A  is exemplified with the first NDR device  100  and the embodiment shown in  FIG. 6B  is exemplified with the second NDR device  200 . In this case, the first logic data can be sustained by the NDR structure while the second logic data can be sustain by the leakage current of access transistor  300 . 
         [0047]    To further illustrate the operation of this proposed single-NDR memory in  FIGS. 6A and 6B , here we choose the second NDR device  200  from  FIG. 6B  as the example, assuming the holding mode bit line voltage is at ground. In the holding mode, the current flowing from P 3  through the second NDR device  200  to P 1  is used to maintain the “high” state while the leakage current flowing from P 1  through the access transistor  300  to bit line  500  is used to maintain the “low” state. When P 1  deviates from the “high” state, usually Vdd, the data is restored by a large charging current from P 3  to P 1  through the second NDR device  200 , while at P 1 ˜0V (“low” state, usually ground), the requirement that the leakage current of the access transistor  300  is greater than the valley current of the second NDR device  200  must be met to maintain the static low state. Although other high PVCR material based NDR structures could also be used in this architecture, the low state leakage requirement is hard to meet since the process for fabricating and controlling the features of the memory element is different from that of the logic device and the current components are more sensitive to process and environment change. We can then design the access transistor  300  with a leakage current larger than the leakage current of the second NDR device  200  to maintain the stable “low” state. To demonstrate its data retention feature, please refer to  FIG. 9 , where Vs means the voltage of P 1 . As expected, when the stored voltage is deviated from the two stable points less than Vdd/2, the “high” state restoration can be done very fast but the “low” state restoration is much slower due to the small leakage current available from the access transistor  300 . However, both states are static and need no refresh. 
         [0048]    Additionally, this structure can also be used in another scheme: choosing the access transistor  300  with a smaller leakage current but applying a “universal refresh”. The universal refresh can be conducted by peripheral circuit for the memory device shown in  FIG. 6B  through following two approaches, respectively. First, the peripheral circuit refreshes storage data by changing a predetermined voltage of the node of the transistor  300 , which is electrically connected to the bit line  500 , for a predetermined period. Second, the peripheral circuit refreshes storage data by changing a predetermined voltage of the gate voltage of the transistor  300  for a predetermined period. Namely, the universal refresh is performed by either slightly activating the word line  400  or pulling down the holding voltage of the bit line  500  in the previous example. By doing this, the access transistor  300  is partially turned-on and the leakage current increases to restore the “low” state cells while those cells in the “high” state attached to the same bit line  500  are still maintained by the high peak current of the attached NDR element. This “universal refresh” is very different from the conventional DRAM cell operation whose refresh operation is done by reading each cell individually since it is essentially a “read and write-back” operation. Here this “universal refresh” is applied for whole blocks at one time and only those cells storing the “low” state will react and be restored. 
         [0049]    Moreover, the power consumption of the single-NDR memory in  FIGS. 6A  and  6 B can be reduced by changing a predetermined voltage of the gate voltage (Vg 1  or Vg 2 ) for a predetermined period with peripheral circuit when the NDR device is not activated. 
         [0050]    To demonstrate the key features and advantages by using a circuit based approach, we proposed a single-NDR based SRAM prototype that combines both features of the existing DRAM and SRAM. Essentially, by adding the NDR element as the active charging component, the DRAM cell becomes a SRAM cell. This SRAM cell operates like a DRAM cell but there are three main differences. First of all, it is static and needs no individual refresh since the data retention issue is solved by the NDR element. Besides, the access transistor needs no special design for high threshold voltage (low-leakage) purpose which also partially limits the available current and speed of the conventional DRAM. In other words, the data storage and data access are partially decoupled in this proposed memory cell. The NDR element is mainly used for data storage while the data access is mostly through the peripheral circuit which can provide larger current drive and higher speed. As a result, this memory prototype can be operated at high speed with approximately half the area of the conventional six-transistor SRAM. 
         [0051]    Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and others will occur to those of ordinary skill in the art. For example, the MOSFET in those embodiments can be any other transistor including JFET which performs the same logic function. The choice of substrate, choice of doping type and the choice of enhancement or depletion mode can also be applied to those of ordinary skill in this art.