Abstract:
An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.

Description:
PRIORITY CLAIM 
       [0001]    This application claims priority from Chinese Application for Patent No. 201510337146.X filed Jun. 17, 2015, the disclosure of which is incorporated by reference. 
       TECHNICAL FIELD 
       [0002]    This application is directed to the field of electronics, and, more particularly, to a circuit to shift the phase of a clock signal. 
       BACKGROUND 
       [0003]    Electronics devices such as computers, laptops, smartphones, tablets, televisions, and the like may have a need to shift the phase of a clock signal. Current circuits to shift the phase of the clock signal typically employ a D-type flip flop that has a D input, a Q output, and a trigger input. The D-type flip flop receives the clock signal at its D input, and a signal at its trigger input that corresponds to an inverted form of the clock signal with its frequency doubled. This circuit produces a version of the clock signal that is phase shifted by 90 degrees. 
         [0004]    While this described phase shifting circuit may be useful in some situations, it suffers from the drawback that the phase shift is determined by the signal at its trigger input. Generation of the necessary signal at the trigger input to provide a desired phase shift may involve the use of a phase locked loop, and the associated complexity (as well as on-chip space) that is associated therewith. 
         [0005]    Therefore, new circuits that shift the phase of the clock in other ways are desirable. 
       SUMMARY 
       [0006]    An electronic device includes a first circuit being configured to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is configured to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is configured to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal. 
         [0007]    A conversion circuit may be configured to receive an input signal and to generate the input current, with the input current being proportional to a frequency of the input signal and to a conversion capacitor. A time for the first voltage to exceed the threshold voltage is based upon a first ratio, with the first ratio being a ratio of a capacitance of the first capacitor to a capacitance of the conversion capacitor. The signal output differs in phase from the input signal based upon the first ratio. 
         [0008]    The first and second capacitors may have a same capacitance. 
         [0009]    A time for the second voltage to exceed the threshold voltage is based upon a second ratio, with the second ratio being a ratio of a capacitance of the second capacitor to the capacitance of the conversion capacitor. The signal output differs in duty cycle from the input signal based upon the second ratio. 
         [0010]    An enable circuit may be configured to enable the first circuit when the input signal has the first logic level and disable the first circuit when the input signal has the second logic level, and to enable the second circuit when the input signal has the second logic level and disable the second circuit when the input signal has the first logic level. The enable circuit may include a first inverter coupled to receive the input signal and to output an inverted version thereof to the first circuit, and a second inverter coupled to the first inverter to receive the inverted version of the input signal and to output an inverted version thereof to the second circuit. 
         [0011]    The first circuit may include a first transistor in a current mirror relationship with an output transistor of the conversion circuit such that the input current may flow therethrough, and a first node. A second transistor may be configured to selectively allow the flow of the input current through the first transistor to flow through the second transistor and into the first node when the input signal has the first logic level. The first capacitor is configured to be charged by the input current flowing through the first node. A comparator is configured to compare a voltage at the first node to the threshold voltage and to generate the output control signal when the voltage at the first node exceeds the threshold voltage. The voltage at the first node is the first voltage across the first capacitor. 
         [0012]    A first current sink circuit may be configured to sink current from the first node based upon the input signal having the second logic level. The first current sink circuit may include a third transistor comprising a first NMOS transistor having a source coupled to ground, a drain coupled to the first node, and a gate coupled to receive an inverse of the input signal. The first current sink circuit may also include a fourth transistor comprising a second NMOS transistor having a source coupled to ground, a drain coupled to the first node, and a gate coupled to the signal output. 
         [0013]    The first transistor may be a first PMOS transistor having a source coupled to a power supply, a drain, and a gate coupled to a gate of the output transistor. The second transistor may be a second PMOS transistor having a source coupled to the drain of the first PMOS transistor, a drain coupled to the first capacitor, and a gate coupled to an inverse of the input signal. 
         [0014]    The second circuit may include a fifth transistor in a current mirror relationship with an output transistor of the conversion circuit such that the input current may flow therethrough, and a second node. A sixth transistor may be configured to selectively allow the flow of the input current through the fifth transistor to flow through the sixth transistor and into the second node when the input signal has the second logic level. A comparator may be configured to compare a voltage at the second node to the threshold voltage and to generate the output reset signal when the voltage at the second node exceeds the threshold voltage. The voltage at the second node may be the second voltage across the second capacitor. 
         [0015]    A second current sink circuit may be configured to sink current from the second node based upon the input signal having the first logic level. The second current sink may include a seventh transistor comprising a third NMOS transistor having a drain coupled to the second node, a source coupled to ground, and a gate coupled to the input signal. 
         [0016]    The fifth transistor may be a third PMOS transistor having a source coupled to the power supply, a drain, and a gate coupled to the gate of the output transistor. The sixth transistor may be a fourth PMOS transistor having a source coupled to the drain of the fifth transistor, a drain coupled to the second node, and a gate coupled to the clock signal. 
         [0017]    A method aspect may include generating a clock current based upon a clock signal. On a rising edge of the clock signal, the method may include generating an output control signal when a first voltage across a first capacitor receiving the clock current exceeds a threshold voltage, wherein a time for the first voltage to exceed the threshold voltage is based upon the clock current and the first capacitor. On a falling edge of the clock signal, the method may include generating an output reset signal when a second voltage across a second capacitor receiving the clock current exceeds the threshold voltage. A clock output may be generated as logic high in response to the output control signal. The clock output may be reset to low based upon the output reset signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a schematic block diagram of a phase shifting circuit in accordance with this disclosure. 
           [0019]      FIG. 2  is a circuit schematic diagram of a phase shifting circuit in accordance with this disclosure. 
           [0020]      FIG. 3  is a timing diagram of the phase shifting circuit of  FIG. 1  in operation. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    One or more embodiments of communication systems in accordance with the principles of the present invention will be described below. These described embodiments are only examples of techniques to implement the invention, as defined solely by the attached claims. Additionally, in an effort to provide a focused description of the invention and the principles of the invention, irrelevant features of an actual implementation may not be described in the specification. 
         [0022]    With reference to  FIG. 1 , a phase shifting circuit  100  for an input signal, such as a clock signal, is now described. Operation of the phase shifting circuit  100  will now be described in general, and thereafter more specific operation details will be given. 
         [0023]    The phase shifting circuit  100  includes a flip flop  170  for generating a signal output CLKOUT. The flip flop  170  receives a voltage representing a logic high at its D input, and provides the signal output CLKOUT at its Q output. The flip flop  170  is clocked by a first circuit  130 , and is reset by a second circuit  150 . The first and second circuits  130 ,  150  receive a clock signal CLKIN as input. 
         [0024]    When the clock signal CLKIN transitions to logic high, the first circuit  130  generates an output control signal whose rising edge clocks the flip flop  170 . The rising edge of the output control signal is delayed with respect to the rising edge of the clock signal CLKIN, and therefore serves to generate a rising edge of the signal output CLKOUT that has its phase shifted with respect to the clock signal CLKIN by a value of X°. 
         [0025]    When the clock signal CLKIN transitions to logic low, the second circuit  150  generates an output reset signal having a falling edge to reset the flip flop  170 . The falling edge of the output reset signal is delayed with respect to the falling edge of the clock signal CLKIN, and therefore serves to generate a falling edge of the signal output CLKOUT that has its phase shifted with respect to the input signal by a value of Y°. 
         [0026]    The delay of the output control signal set by the first circuit  130  therefore shifts the phase of the signal output CLKOUT with respect to the clock signal CLKIN by X°. Similarly, the delay of the output reset signal set by the second circuit  150  alters the duty cycle of the signal output CLKOUT with respect to the clock signal CLKIN. If X°=Y°, then the duty cycle is not changed. 
         [0027]    Further details of the phase shifting circuit  100  are now given with reference to  FIG. 2 . A conversion circuit  110  comprises a conversion capacitor Cc and a switch S 2 (φ 2 ) coupled in parallel between a node  111  and ground. A NMOS compensation transistor T 4  has a gate coupled to the node  111 , and a source and drain both coupled to ground GND. The NMOS transistor T 4  serves to compensate capacitors C 1  and C 2 . A switch S 1 (φ 1 ) is coupled between the node  111  and a second node  112 . An additional conversion capacitor Cc 2  is coupled between the node  112  and ground GND. An operational amplifier  115  has an inverting terminal coupled to through a switch S 3 (φ 2 ) to node  112 , and a non-inverting terminal coupled to a reference voltage Vref. A feedback capacitor Cc 3  is coupled between the inverting input and output of the operational amplifier  115 . 
         [0028]    A NMOS transistor T 3  has a gate coupled to the output of the operational amplifier  115 , a source coupled to ground GND via a resistor R, and a drain coupled to a node  116 . A PMOS transistor T 1  has a source coupled to a power supply voltage Vdd, a drain coupled to the node  116 , and a gate also coupled to node  116 . A PMOS transistor T 2  has a source coupled to the power supply voltage Vdd, a drain coupled to node  111 , and a gate coupled to the node  116 . 
         [0029]    During operation of the conversion circuit  110 , the switches S 1 (φ 1 ), S 2 (φ 2 ), and S 3 (φ 2 ), are triggered according to the clock CLKIN. The φ on each switch denotes when that switch transitions. φ 1  represents one logic state of the clock, and φ 2  represents the other logic state of the clock. φ 1  and φ 2  are non-overlapping clock control signals derived from input signal CLKIN. During φ 2 , the switches S 2 (φ 2 ) and S 3 (φ 2 ) close while the switch S 1 (φ 1 ) is open, and the capacitor Cc discharges to ground. At the same time, the voltage across Cc 2  is forced to ground by Vref. During φ 1 , the switch S 1 (φ 1 ) closes, while the switches S 2 (φ 2 ) and S 3 (φ 2 ) are opened. Thus, the operational amplifier  115  provides a constant voltage to the gate of the transistor T 3 , which pulls a constant current through transistor T 1  and into the node  116 . This constant current is mirrored to T 2 , and flows through capacitors Cc and Cc 2 . Thus, the constant current is provided to the capacitors Cc and Cc 2  by the current mirror arrangement formed by the transistors T 1  and T 2 , thereby charging the capacitors Cc and Cc 2 . 
         [0030]    When the transition to φ 2  occurs, the switch S 1 (φ 1 ) opens, while the switches S 2 (φ 2 ) and S 3 (φ 2 ) close. The capacitor Cc 2  is then discharged into the feedback capacitor Cc 3  at the same time as Cc is discharged to ground. If the voltage across Cc 2  is greater than Vref, the voltage output by the operational amplifier  115  will decrease when Cc is discharged to ground, causing a reduction in the constant current. If the voltage across Cc 2  is less than Vref, the voltage output by the operational amplifier  115  will increase, causing an increase in the constant current. This increase or decrease in the steady state current affects how quickly the capacitors Cc and Cc 2  charge up. Ultimately, once the conversion circuit  110  reaches a steady state, the voltage across Cc 2  will be equal to Vref, and the constant current can be described mathematically as: 
         [0000]        I= 2 V   REF Cc F   CLKIN    
         [0000]    This steady state current is proportional to both the frequency of the input signal and the capacitance of the capacitor Cc, and is referred to herein as the clock current or input current. 
         [0031]    The first circuit  130  includes a first PMOS transistor P 1  that has its source coupled to the power supply Vdd, and its gate coupled to the node  116 . A second PMOS transistor P 2  has its source coupled to the drain of the first PMOS transistor P 1 , its gate coupled to node  127 , and its drain coupled to node  161 . A comparator  132  has its non-inverting terminal coupled to node  161 , and its inverting terminal coupled to the reference voltage Vref. A first capacitor C 1  is coupled between the node  161  and ground. 
         [0032]    A first current sink circuit  160  includes a first NMOS transistor N 1  having its drain coupled to the node  161 , its source coupled to ground, and its gate coupled to node  127 . A second NMOS transistor N 2  has its drain coupled to node  161 , its source coupled to ground GND, and its gate coupled to receive the signal output CLKOUT. 
         [0033]    A second circuit  150  includes a third PMOS transistor P 3 , which has its source coupled to the power supply Vdd, and its gate coupled to node  116 . A fourth PMOS transistor P 4  has its source coupled to the drain of the third PMOS transistor P 3 , its gate coupled to inverter  135  at node  153 , and its drain coupled to the node  151 . A comparator  152  has its non-inverting terminal coupled to the node  151 , and its inverting terminal coupled to the reference voltage Vref. A second capacitor C 2  is coupled between the node  151  and ground GND. A second current sink circuit  140  includes a third NMOS transistor N 3  having its drain coupled to the node  151 , its source coupled to ground GND, and its gate coupled to node  153 . 
         [0034]    As will be explained, the input current is utilized by the first circuit  130  and second circuit  150 . However, the conversion circuit  110  should be in a steady state before the current is so utilized. Therefore, an enable circuit  120  is used to, in part, delay usage of the input current by the first circuit  130  and second circuit  150 . 
         [0035]    The enable circuit  120  is includes an AND gate  124 , which receives at its inputs the input signal CLKIN, and a delayed version of an enable signal EN. An inverter  126  is coupled to the output of the AND gate  124  via node  127 . When the input signal CLK is high and enable signal is asserted, and after the delay of the enable signal imposed by the delay block  122 , the AND gate  124  outputs a logic high, which is then inverted by inverter  126 . The output of the inverter  126  is passed to another inverter  135  via node  153 . 
         [0036]    In operation, the first PMOS transistor P 1  mirrors the input current through the transistor T 1  of the conversion circuit. When the input signal is high, the enable circuit  120  outputs a logic low to node  127 , which serves to turn on the second PMOS transistor P 2 , and turn off the first NMOS transistor N 1 . The input current thus flows from the first PMOS transistor P 1 , through the second PMOS transistor P 2 , into the first capacitor C 1  at node  161 , and charges up the first capacitor C 1 . When the voltage across the first capacitor C 1  is greater than the reference voltage Vref, the comparator  132  outputs a logic high to the clock input CP of the flip flop  132  at node  133 , which then latches a logic high value from the input D of the flip flop  132  to the output Q of the flop flop  132 . This output is then inverted twice by the inverters  172  and  174 , and is output as the phase shifted clock output CLKOUT. 
         [0037]    The time for the voltage across the capacitor C 1  to exceed the reference voltage Vref is a function of the value of the input current and the capacitor C 1 , and thus dependent upon a ratio of the capacitance of the capacitor C 1  to the capacitor Cc. This time can be calculated as: 
         [0000]    
       
         
           
             
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         [0000]    Thus, the amount of phase shift X° as a result of the time delay is easily adjustable by selecting the value of the capacitors C 1  and Cc. 
         [0038]    When the input signal transitions low, the logic high at node  127  turns on the first NMOS transistor N 1  and turns off P 2 . This serves to discharge the capacitor C 2  to ground. Since the comparator  132  will then see ground at its non-inverting terminal and the reference voltage Vref at its inverting terminal, it will output a logic low to the clock input CP of the flip flop  170 . In addition, when the signal output CLKOUT is high, the second NMOS transistor N 2  turns on, further helping to discharge the first capacitor C 1  to ground. 
         [0039]    In addition, when the input signal goes low, the enable circuit  120  outputs a logic high to node  127 , which is then inverted by the inverter  135 , which serves to turn on the fourth PMOS transistor P 4  and turn off the third NMOS transistor N 3 . This allows the input current, mirrored from transistor T 1  to the third PMOS transistor P 3 , to flow through the fourth PMOS transistor P 4 . The input current thus flows through the capacitor C 2 , charging C 2 . When the voltage across C 2  exceeds the reference voltage Vref, the comparator  152  outputs a logic high, which is then inverted by the inverter  154 , and fed to the reset input CN of the flip flop  170  at node  156 . This resets the flip flop  170 , pulling the output low, and thus the signal output CLKOUT low. 
         [0040]    The time for the voltage across the capacitor C 2  to exceed the reference voltage Vref is a function of the value of the input current and the capacitor C 2 , and thus is based upon a ratio of the capacitance of the capacitor C 2  to the capacitor Cc. This time can be calculated as: 
         [0000]    
       
         
           
             
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         [0000]    Thus, the amount of phase shift Y° which causes adjustment in duty cycle is easily alterable by selecting the value of the capacitors C 2  and Cc. 
         [0041]    A timing diagram showing the various signals of the phase shifting circuit  100  in operation is depicted by  FIG. 3 . In particular,  FIG. 3  shows CLKIN, the voltage at nodes  127 ,  161 ,  133 ,  153 ,  151 , and  156 , and CLKOUT. 
         [0042]    While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims.