Abstract:
A memory controller is disclosed. The memory controller includes a mechanism to perform a first command to transition an interface coupled between the memory controller and to facilitate a memory write and to perform a second command to immediately write data to the memory device a predetermined period after performing the command to transition the interface.

Description:
COPYRIGHT NOTICE  
       [0001]     Contained herein is material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any person as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights to the copyright whatsoever.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to computer systems; more particularly, the present invention relates to controlling memory devices.  
       BACKGROUND  
       [0003]     A bidirectional interface is a pin-efficient mechanism implemented for connecting to memory devices, such as DRAMs. However, bandwidth efficiency suffers from the loss of bandwidth during the idle periods required to turn the interconnect around. Such turnarounds occur between writes and reads and between reads and writes, as the interconnect transmitter and receiver exchange roles.  
         [0004]     Moreover, as the data rate on bidirectional interconnects scales to achieve performance requirements of future memory systems, the turnaround time will only slowly change, being more a function of the propagation latency of the channel than of the speed of the logic on either end of the interconnect. Thus these turnarounds will cause a larger and larger proportion of lost bandwidth as the data rate scales.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]     The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:  
         [0006]      FIG. 1  is a block diagram of one embodiment of a computer system;  
         [0007]      FIG. 2  illustrates one embodiment of a timing diagram for an opportunistic write;  
         [0008]      FIG. 3  illustrates one embodiment of a flow diagram for the implementation of turnaround and immediate write commands;  
         [0009]      FIG. 4  illustrates one embodiment of a timing diagram for turnaround and immediate write commands; and  
         [0010]      FIG. 5  illustrates another embodiment of a timing diagram for turnaround and immediate write commands.  
     
    
     DETAILED DESCRIPTION  
       [0011]     According to one embodiment, a method to mitigate performance turnaround in a bidirectional interconnect is described. In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.  
         [0012]     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.  
         [0013]      FIG. 1  is a block diagram of one embodiment of a computer system  100 . Computer system  100  includes a central processing unit (CPU)  102  coupled to bus  105 . In one embodiment, CPU  102  is a processor in the Pentium® family of processors including the Pentium® II processor family, Pentium® III processors, and Pentium® IV processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used.  
         [0014]     A chipset  107  is also coupled to bus  105 . Chipset  107  includes a memory control hub (MCH)  110 . MCH  110  may include a memory controller  112  that is coupled to a main system memory  115 . Main system memory  115  stores data and sequences of instructions that are executed by CPU  102  or any other device included in system  100 . In one embodiment, main system memory  115  includes dynamic random access memory (DRAM); however, main system memory  115  may be implemented using other memory types. Additional devices may also be coupled to bus  105 , such as multiple CPUs and/or multiple system memories.  
         [0015]     Chipset  107  also includes an input/output control hub (ICH)  140  coupled to MCH  110  to via a hub interface. ICH  140  provides an interface to input/output (I/O) devices within computer system  100 . For instance, ICH  140  may be coupled to a Peripheral Component Interconnect bus adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oreg.  
         [0016]     As discussed above, memory controller  112  interfaces with main system memory  115 . In one embodiment, memory controller  112  is coupled to memory  115  via a bidirectional interface. As previously mentioned, idle periods are incurred while turning the interconnect around. As a result, write flushes are often executed by queuing a multitude of write commands at memory controller  112  and transmitting the writes to memory  115  the writes as a batch.  
         [0017]     In some instances, however, it would be inefficient to queue write commands if the interface is not being used. Therefore, memory controllers typically feature an opportunistic write command that performs a single write command if the interface is not being used. However, a problem may occur during the implementation of a write command where a read command is received immediately after initiating the opportunistic write command.  
         [0018]     The problem is that the read command cannot be serviced until after the write command has been completed. Before the command can be completed, however, the interface is first turned around to permit the write command, and subsequently the write command is performed. This leads to a relatively long delay prior being able to issue the read command.  
         [0019]      FIG. 2  illustrates one embodiment of a timing diagram for an opportunistic write.  FIG. 2  shows intervals to the right and left that indicate periods for which no delay is incurred upon receiving a read command. However, the middle interval indicates a delay incurred for a read received at a certain time after the opportunistic write has been initiated.  
         [0020]     According to one embodiment, memory controller  112  performs two new commands to implement a write. The first command is a turnaround command (TRW) that begins a read-write turnaround in preparation for a write. In one embodiment, the TRW command specifies a target rank and bank set. The second command is an immediate write command (IW).  
         [0021]     According to one embodiment, the IW command is similar to a write column address signal (Wr CAS) with short write latency (tWL) (e.g., includes CAS address). In a further embodiment, data is posted into memory  115  and transferred to a memory  115  array in one column access. Thus the IW command is not sensitive to tWL.  
         [0022]      FIG. 3  illustrates one embodiment of a flow diagram for the implementation of turnaround and immediate write commands. At processing block  305 , a command to access memory  115  is received at memory controller  112 . At decision block  310 , it is determined whether the command is a read command. If the command is a read command, the read is performed and data is read from memory  115  via the interface, processing block  315 .  
         [0023]     However, if the command is a write command it is determined whether a read command has recently been received, decision block  320 . If a read command has been received control is returned to processing block  315  where the read is performed. If, however, no read command has been received, memory controller  112  performs the TWL command, and the interface is turned around so that a write command may be performed, processing block  325 .  
         [0024]     At decision block  330 , it is determined whether a read command has been received within a predetermined period since the TWL command has been performed. If a read command has been received, the interface is turned back around so that the read may be performed, processing block  335 . Subsequently, control is returned to processing block  315  where the read is performed. If no read command has been received, memory controller  112  performs the IW command, and an immediate write is performed, processing block  340 .  
         [0025]     The TRW and IW commands permit an opportunistic write to be separated into two decision points (e.g., turnaround and data transfer). As a result, each decision point may now be delayed until as late as possible. Thus if a read arrives after the turnaround decision but before data the transfer decision, the data transfer can be aborted, reducing the delay to the read. The opportunistic write data transfer can be re-scheduled for a subsequent time.  
         [0026]      FIGS. 4 and 5  illustrate how separating the write commands into two new commands permits the turnaround penalty to be minimized.  FIG. 4  illustrates one embodiment of a timing diagram where a read is received after the IW command. In this instance, the delay period is reduced to the amount of time to perform the IW command, since no read command would have been received after the TRW command and before the issuance of the IW command.  
         [0027]      FIG. 4  illustrates one embodiment of a timing diagram where a read is received after the TRW command, but before the IW command. As shown in  FIG. 5 , only a small delay period is incurred because only the interface is turned around prior to beginning the write.  
         [0028]     The above described method enables the turnaround penalty to be significantly reduced since either no read traffic to be penalized for read-write turnaround, or a write can be aborted to minimize latency for a newly arriving read. Thus, there is a latency savings approximately equal to the write data transfer time plus time to turn the interface around at the memory.  
         [0029]     Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which in themselves recite only those features regarded as essential to the invention.