Abstract:
A multi-core processor system has a first core executing an OS and multiple applications, and a second core to which a first thread of the applications is assigned. The multi-core processor system includes a processor configured to receive from the first core, an interrupt signal specifying an event that has occurred with an application among the applications, determine whether the event specified by the received interrupt signal is any one among a start event for exclusion and a start event for synchronization for the first thread currently under execution by the second core, save from the second core, the first thread currently under execution, upon determining the specified event to be a start event, and assign a second thread different from the saved first thread and among a group of execution-awaiting threads of the applications, as a thread to be executed by the second core.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation application of International Application PCT/JP2010/052733, filed on Feb. 23, 2010 and designating the U.S., the entire contents of which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The embodiment discussed herein is related to a multi-core processor system, an interrupt program, and an interrupt method that control thread interrupts. 
       BACKGROUND 
       [0003]    Conventionally, multi-core processor systems have been disclosed. For example, in response to a start request from a master CPU, a multi-core processor starts a slave library as a thread at a slave central processing unit (CPU), without invoking the kernel of the operating system (OS) (see, for example, Japanese Laid-Open Patent Publication Nos. 2005-25726, H6-243102, H6-149752, and 2006-185348). In this case, overhead consequent to the OS kernel is minimized by having only minimally required thread execution preparation and a function of interrupt control from the master CPU, at the slave CPU, without invoking the kernel. 
         [0004]    For example, when a library thread executed by the master CPU has a slave library thread call for the slave CPU, parallel execution can be realized by the master CPU and the slave CPU. 
         [0005]    nonetheless, with the conventional technologies above, although the slave CPU executes a thread when the slave CPU is called by the master CPU, when the slave CPU is not called, the slave CPU continues to remain in a quiescent mode. Cases in which the master CPU and the slave CPU continuously operate in parallel are rare and generally, the slave CPU is in a quiescent mode until called upon by the master CPU. 
         [0006]    Thus, although the utilization efficiency of the system is determined by the ratio of software to be run that can be executed in parallel (Amdahl&#39;s law), problems arise in that accompanying increases in the number of processors, or accompanying decreases in the ratio of software that can be executed in parallel, utilization efficiency becomes extremely poor and performance deteriorates. 
         [0007]    On the other hand, if each CPU of a multi-processor is run, although applications are executed at each CPU, exclusion control for simultaneously executed applications becomes necessary. Thus, although fine control by the OS kernel becomes possible, a problem arises in that overhead arises consequent to the management structure. In particular, in integrated systems such as mobile terminals, the overhead consequent management mechanisms becomes a load that cannot be disregarded. 
       SUMMARY 
       [0008]    According to an aspect of an embodiment, a multi-core processor system has a first core executing an OS and multiple applications, and a second core to which a first thread of the applications is assigned. The multi-core processor system includes a processor configured to receive from the first core, an interrupt signal specifying an event that has occurred with an application among the applications, determine whether the event specified by the received interrupt signal is any one among a start event for exclusion and a start event for synchronization for the first thread currently under execution by the second core, save from the second core, the first thread currently under execution, upon determining the specified event to be a start event, and assign a second thread different from the saved first thread and among a group of execution-awaiting threads of the applications, as a thread to be executed by the second core. 
         [0009]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0010]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0011]      FIG. 1  is a block diagram of a hardware configuration of a multi-core processor system according to the present embodiment; 
           [0012]      FIG. 2  is a flowchart depicting a procedure of processing executed at the multi-core processor system according to the present embodiment; 
           [0013]      FIG. 3  is a sequence diagram depicting a first example of interrupt control; 
           [0014]      FIG. 4  is a sequence diagram depicting a second example of interrupt control; 
           [0015]      FIG. 5  is a sequence diagram depicting a third example of interrupt control; and 
           [0016]      FIG. 6  is a sequence diagram depicting a fourth example of interrupt control. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0017]    Preferred embodiments of a multi-core processor system, an interrupt program, and an interrupt method will be explained with reference to the accompanying drawings. In the multi-core processor system of the present embodiment, a multi-core processor is a processor equipped with multiple cores. Provided multiple cores are equipped, a multi-core processor may be a single processor equipped with multiple cores, or a group of parallel single-core processors. In the present embodiment, for the sake of simplicity, description will be given using a group of parallel single-core processors as an example. 
         [0018]      FIG. 1  is a block diagram of a hardware configuration of the multi-core processor system according to the present embodiment. In  FIG. 1 , a multi-core processor system  100  includes a master CPU  101 , 1 or more slave CPUs  102  (1 in the example depicted in  FIG. 1 ), and memory  103 , respectively connected through a bus  104 . Cache memory is integrated in the master CPU  101  and the slave CPU  102 . 
         [0019]    An OS  110  that controls management of the memory and the slave CPU  102  runs on the master CPU  101 . The OS  110  runs only on the master CPU  101 . On the master CPU  101 , applications corresponding to the OS  110  run during time slices, according to the OS  110  scheduling. Application A includes thread B, which is invoked while application A is running. Application X includes thread Y, which is invoke while application X is running. 
         [0020]    The slave CPU  102  executes an interrupt program  120 . A thread of an application executed by the master CPU  101  is also executed. Since the OS  110  does not run on the slave CPU  102 , the slave CPU  102  operates independently. 
         [0021]    The memory  103  stores the OS  110 , applications as well as other types of information, and is used as a work area of the master CPU  101  and the slave CPU  102 . The memory  103 , for example, is a storage device such as Read Only Memory (ROM), Random Access Memory (RAM), flash memory, and a hard disk drive. 
         [0022]    In  FIG. 1 , at the master CPU  101 , applications A and X are running on the OS  110  according to time slices. At the slave CPU  102 , thread B of application A is running independently. Thread Y of application X is waiting in a thread queue of the CPU  101 . 
         [0023]    In the present embodiment, if an exclusive event or a synchronized event occur, the slave CPU  102  operates efficiently. Here, an example of synchronization will be described. For example, application A is assumed to have a function of reading in and expanding a file on the memory  103 ; and thread B, which is simultaneously executed, is assumed to use the data of the file expanded on the memory  103 . In this case, thread B waits until completion of the file reading and expansion on the memory by application A. In other words, when the file is read, the memory area where the data is expanded is simultaneously under exclusive monitoring by application A and thread B is temporarily released from the slave CPU  102 . Subsequently, after expansion on the memory, the data is shared (simultaneously) with thread B. 
         [0024]    An example of exclusion will be described. For example, application A is assumed to be a browser and thread B is assumed to be a program for playing moving images. Application X is assumed to be a mailer and thread Y is assumed to be an inquiry program of the mailer. 
         [0025]    At the master CPU  101 , application A (browser) and application X (mailer) are assumed to run by time sharing. If the time at which thread Y (inquiry program of mailer) is to start arrives while thread B (program for playing moving images) is playing a moving image from a video delivery server, since the OS  110  causes thread Y (inquiry program of mailer) to be executed by the slave CPU  102 , the OS  110  performs exception handling with respect to thread B (program for playing moving images). Consequently, thread B (program for playing moving images) is released from the slave CPU  102  and thread Y (inquiry program of mailer) is executed at the slave CPU  102 . 
         [0026]      FIG. 2  is a flowchart depicting a procedure of processing executed at the multi-core processor system  100  according to the present embodiment. In  FIG. 2 , the processing procedure of the master CPU  101  represents management processing of the OS  110  and the processing procedure of the slave CPU  102  represents thread interrupt control processing from the master CPU  101 . 
         [0027]    The management processing of the OS  110  at the master CPU  101  will be described. The OS  110  invokes master processes in parallel (step S 201 ). For example, applications A and X, which are master processes, are run according to time slices. 
         [0028]    When an invoked master process is run, the master CPU  101 , via the OS  110 , places a thread of the master process in a thread queue  200 , according to the execution state of the master process (step S 202 ). For example, threads B and Y are placed in the thread queue  200 . Status of the thread queue  200 , for example, is written to the memory  103  and can be referred to by the slave CPU  102 . 
         [0029]    The master CPU  101 , via the OS  110 , detects the occurrence of an event (step S 203 ). Here, an event is, for example, thread invocation, suspension, exclusion, synchronization, signal/message, etc. An event occurs consequent to an application executed on the OS  110  or a thread executed by the slave CPU  102 . 
         [0030]    Upon detecting the occurrence of an event, the OS  110  determines the type of the event (step S 204 ). If the event is an event related to exclusion or synchronization (step S 204 : exclusion/synchronization), the master CPU  101 , via the OS  110 , applies to the upper bits of an interrupt signal, an identifier indicative of exclusion or synchronization (step S 205 ), and transitions to step S 206 . 
         [0031]    At step S 204 , if the event is an event of a type other than exclusion/synchronization (step S 204 : other), the master CPU  101  transitions to step S 206 . At step S 206 , the master CPU  101 , via the OS  110 , transmits to the slave CPU  102 , an interrupt signal corresponding to the event for which the type was determined at step S 204  (step S 206 ). Thus, the master CPU  101 , via the OS  110 , transmits to the slave CPU  102 , an interrupt signal when an event occurs in a master process and inserts necessary threads into the thread queue  200  to await execution. 
         [0032]    The slave CPU  102  awaits the start of a thread by the interrupt program  120  (step S 210 ). Upon start of the thread, the slave CPU  102  executes the thread via the interrupt program  120  (step S 211 ). Thread operations are performed until an interrupt signal is received. If the thread finishes before an interrupt signal is received, the flow transitions to step S 216 . 
         [0033]    Upon receiving the interrupt signal from the master CPU  101 , the slave CPU  102 , via the interrupt program  120 , executes interrupt receipt processing (step S 212 ). The slave CPU  102 , via the interrupt program  120 , determines the event type indicated by the interrupt signal (step S 213 ). If the event is an event of a type other than exclusion or synchronization (step S 213 : other), the slave CPU  102 , via the interrupt program  120 , executes event processing according to the event (step S 214 ), and returns to step S 211 . 
         [0034]    Meanwhile, if the event type is a start event for exclusion or synchronization (step S 213 : exclusion start/synchronization start), the slave CPU  102 , via the interrupt program  120 , saves the state of the thread currently under execution (step S 215 ). For example, the data on the cache memory of the slave CPU  102 , used by the thread currently under execution, is flushed to the memory  103  and the position of the program counter that has been in operation up to now is saved, without releasing the context area on the memory  103 . Consequently, the slave CPU  102  is released from the executed thread. 
         [0035]    Upon saving the thread state, the slave CPU  102 , via the interrupt program  120  checks the status of the thread queue  200  of the OS  110  (step S 216 ). If the thread queue  200  is not an empty set (step S 216 : queue≠Φ), the slave CPU  102 , via the interrupt program  120 , sets the thread (not the saved thread) at the head of the thread queue  200  as the thread to be executed, and executes the thread (step S 217 ). The flow returns to step S 211 . 
         [0036]    Meanwhile, if the thread queue  200  is an empty set (step S 216 : queue=Φ), the slave CPU  102 , via the interrupt program  120 , is set to a low power mode (step S 218 ), and transitions to the thread-start standby mode at step S 210 . 
         [0037]    At step S 213 , if the event type is exclusion release (end) or synchronization end (step S 213 : exclusion release/synchronization end), the slave CPU  102 , via the interrupt program  120 , restores the saved thread state (step S 219 ). For example, although the slave CPU  102  has been released from the saved thread, the memory area used by the saved thread is preserved since the context area on the memory  103  has not been released. 
         [0038]    Simply, by restoration alone of the program counter of the saved thread stored to a register (or the memory  103 ) of the slave CPU  102 , the save thread can be resumed (restored). Subsequently, the flow returns to step S 211 . Thus, the slave CPU  102 , which conventionally is in a quiescent state to await exclusion or synchronization, can be operated more efficiently by the operations above. 
         [0039]    With reference to  FIGS. 3 to 6 , an example of interrupt control will be described. 
         [0040]      FIG. 3  is a sequence diagram depicting a first example of interrupt control. In  FIG. 3 , at the master CPU  101 , applications A and X are assumed to run on the OS  110  according to time slices (in actuality, the OS  110 , applications A and X run according to time slices). At the slave CPU  102 , thread B is assumed to be executed. In the thread queue  200  of the OS  110 , thread Y is assumed to be waiting as an execution-awaiting thread. 
         [0041]    In application A, when an exclusion start event is detected, an interrupt signal (exclusion start) is transmitted to thread B from application A. At the slave CPU  102 , when notification of the exclusion start event is received, thread B is saved, whereby slave CPU  102  is released. Since thread Y is present in the thread queue  200 , thread Y is assigned to the slave CPU  102 . Consequently, thread Y is executed at the slave CPU  102 . Subsequently, when thread Y ends, since the thread queue  200  is empty, the slave CPU  102  transitions to a low power mode. 
         [0042]    Thereafter, in application A, when an exclusion end event is detected, an interrupt signal (exclusion end) is transmitted to the slave CPU  102  from application A. At the slave CPU  102 , when notification of the exclusion end event is received, thread B is restored by the slave CPU  102 , whereby execution of thread B can be resumed from the saved position. 
         [0043]    Similarly, in the case of synchronization, in application A, when a synchronization start event is detected, application A instructs thread B to execute coherent processing and gives notification to the slave CPU  102 . Here, at slave CPU  102 , although thread B is temporarily saved, thread B is soon restored. When the time at which synchronization is to start arrives, application A and thread B are simultaneously executed. 
         [0044]      FIG. 4  is a sequence diagram depicting a second example of interrupt control. In  FIG. 4 , at the master CPU  101 , applications A and X are assumed to run on the OS  110  according to time slices. At the slave CPU  102 , thread B is assumed to be executed. Thread B is assumed to be subject to exclusion by application X, which is not a master process (parent) of thread B. 
         [0045]    When thread B detects an exclusion start event for application X, thread B gives notification to the OS  110 , trigging detection of a suspend event for application X at the OS  110 . Thereafter, the OS  110  and application A run according to time slices. Subsequently, when thread B detects an exclusion end event for application X, thread B gives notification to the OS  110 . Thereafter, at the master CPU  101 , application X is restored, and the OS  110  and applications A and X are run according to time slices. Thus, even when an exclusion event is detected by the slave CPU  102 , the multi-core processor system  100  operates trouble-free. 
         [0046]      FIG. 5  is a sequence diagram depicting a third example of interrupt control. In  FIG. 5 , at the master CPU  101 , applications A and X are assumed to run on the OS  110  according to time slices. At the slave CPU  102 , thread B is assumed to be executed. Thread B is assumed to be subject to exclusion by application A, which is a master process (parent) of thread B. 
         [0047]    When thread B detects an exclusion start event for application A, thread B gives notification to the OS  110 , triggering detection of a suspend event for application A at the OS  110 . Thereafter, the OS  110  and application X run according to time slices. Subsequently, when thread B detects an exclusion end event for application A, thread B gives notification to the OS  110 . Thereafter, at the master CPU  101 , application A is restored, and the OS  110 , and applications A and X are run according to time slices. Thus, even when an exclusion event is detected by the slave CPU  102 , the multi-core processor system  100  operates trouble-free. 
         [0048]      FIG. 6  is a sequence diagram depicting a fourth example of interrupt control.  FIG. 6  depicts an example where in the example depicted in  FIG. 5 , thread Y is placed in the thread queue  200  of the OS  110 . When thread B detects an exclusion start event for application A, thread B gives notification to the OS  110 , triggering a suspend event of application A to be detected at the OS  110 , whereby application A is suspended. 
         [0049]    In the example in  FIG. 6 , although the OS  110  and application X run according to time slices thereafter, if thread Y is to be invoked in application X, since thread B is under execution at the slave CPU  102 , thread Y cannot be executed. Consequently, the execution of application X is also suspended, whereby the OS  110  alone is executed at the master CPU  101 . 
         [0050]    Thereafter, when an exclusion end event is detected by the slave CPU  102 , the OS  110  is given notification from thread B. Consequently, thread B ends and at the master CPU  101 , the OS  110  and applications X and A run according to time slices. 
         [0051]    Thus, in the multi-core processor system  100  according to the present embodiment, irrespective of which CPU among the master CPU  101  and the slave CPU  102  an exclusion or synchronization event occurs, efficient operation can be facilitated. 
         [0052]    As described, the multi-core processor system  100 , the interrupt program  120 , and the interrupt method according to the present embodiment enables the OS  110  alone to be run at the master CPU  101  and since the interrupt program  120  is merely executed by the slave CPU  102 , operation that imposes low load can be facilitated. 
         [0053]    Further, by subjecting a thread of the slave CPU  102  to exclusion or synchronization by the master CPU  101 , a thread under execution can be saved and with the slave CPU  102  in an available state thereafter, an execution-awaiting thread is assigned and executed. Thus, at the slave CPU  102 , quiescent mode interval can be significantly reduced, enabling efficient operation to be facilitated. When no execution-awaiting thread is present, the slave CPU  102  transitions to a low power mode, enabling low power consumption to be facilitated. 
         [0054]    The present multi-core processor system, interrupt program, and interrupt method effect improved the efficiency of processor utilization and operation that imposes low load. 
         [0055]    All examples and conditional language provided herein are intended for pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.