Abstract:
The present invention provides a SRAM that is capable of performing a writing and reading operations simultaneously without collision while reducing size of cell, by providing a dual port SRAM cell. For this, the dual port SRAM cell, including: a writing section having a first transistor for inputting a data input signal from a bit line in response to a control signal from a word line; a data storage section having three transistors for storing the data input signal from the outside through the writing section; and a reading section having two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to a unit cell circuit of SRAM (static random access memory) in a semiconductor memory device; and, more particularly, to a dual port SRAM cell with 6 transistors.  
         [0002]     Description of Related Art  
         [0003]     In general, SRAM has an advantage that there is not required additional refresh because it employs latch type of cell unlike DRAM (dynamic random access memory). Conventionally, a single port SRAM that is composed of 6 transistors (TRs) is used as cell circuit.  
         [0004]     Meanwhile, a RAM embedded TFT LCD driver generally carries out the following two operations: one is a writing operation to write data to be displayed in the RAM and the other is a reading operation to read the data written in the RAM. The data written in the RAM is read and outputted through a output driver periodically for its scanning on LCD panel.  
         [0005]     In such RAM embedded TFT LCD driver, in case that the single port SDRAM cell with 6 TRs is employed, reading data stored for scanning tends to collide with the writing operation. To solve the problem, a dual port SRAM cell is traditionally used.  
         [0006]      FIG. 1  is a circuit diagram of the single port SRAM cell with 6 TRs, and  FIG. 2  is a circuit diagram of the dual port SRAM cell with 8 TRs.  
         [0007]     Referring to  FIG. 1 , a memory cell  100  comprises two access transistors NO 2 A and NO 2 B for connecting storage nodes cellA and cellB to bit lines BL and BLX according to a switching that depends on a signal via a word line WL, and four transistors P 00 , P 01 , N 00 , N 01  for configuring inverting latch between the storage nodes cellA and cellB. One pair of bit lines BL and BLX are input and output paths of data, whereas the word line WL is a path carrying a signal to control its input and output.  
         [0008]     There exists complementary relationship between signal levels on a positive bit line BL and a negative bit line BLX. That is, if one of them is logic H state, then the other generally becomes logic L state. However, in order to increase operation speed of SRAM, it makes in such a manner that levels of the two signals are all set to logic H or L state, or to specific values such as VDD/2 before data is written in the SRAM or read therefrom.  
         [0009]     Before or after data is written in the SRAM memory cell or read therefrom, in case that it is designed that both the positive bit line BL and the negative bit line BLX have VDD/2, operation procedure of the SRAM cell is as follow.  
         [0010]     When writing data value of logic H in the SRAM memory cell, after the positive bit line BL and the negative bit line BLX are set to have VDD/2, it makes value to be written in the SRAM placed on the bit line by applying logic H onto the positive bit line BL and logic L onto the negative bit line BLX. After that, if a word line WL is enabled to have logic H, then values on the positive bit line BL and the negative bit line BLX are applied to the cell storage nodes cellA and cellB, respectively.  
         [0011]     Since the transistors P 00 , N 00  and P 01 , N 01  are composed of pairs of inverters, they function to invert and output values at input nodes.  
         [0012]     Thus, if data is inputted from the positive bit line BL and then H level signal is applied to the cell storage node cellA through the access transistor NO 2 A, the input signal is inverted by way of the inverters P 00  and N 00  and becomes L level state at the cell storage node cellB.  
         [0013]     Similarly, if data is inputted from the negative bit line BLX and then L level signal is applied to the cell storage node cellB through the access transistor NO 2 B, the input signal is inverted by passing through the inverters P 01  and N 01  and becomes H level state at the cell storage node cellA.  
         [0014]     Accordingly, H and L states are stably maintained at the nodes cellA and cellB, respectively.  
         [0015]     In such a state, if it makes state of the word line WL changed to L, then signal levels at the nodes cellA and cellB are stably maintained as data values stored although new signal level is not applied from the positive bit line BL and the negative bit line BLX.  
         [0016]     When reading data stored in the SRAM, the word line WL is first activated and set to have H state. This is contrary to the writing operation.  
         [0017]     In the state that the positive bit line BL and the negative bit line BLX are designed to have VDD/2, if H level is applied onto the word line WL, H level and L level signals stored in the nodes cellA and cellB are outputted and provided to the positive bit line BL and the negative bit line BLX through the access transistors N 02 A and NO 2 B, respectively. At that time, signal levels on the bit lines BL and BLX are read as H and L, respectively.  
         [0018]     A 8 TR dual port SRAM cell  110  shown in  FIG. 2  comprises four NMOS transistors Nl 2 A, N 10 , N 11 , Nl 2 B, and four PNMOS transistors P 10 , P 11 , P 12 , P 13 .  
         [0019]     A basic configuration further comprises two PMOS transistors P 12  and P 13 , in addition to 6 TR single port SRAM shown in  FIG. 1 . The added two transistors are provided to resolve the problem that the single port SRAM can&#39;t perform writing and reading operations simultaneously.  
         [0020]     In other words, 8 TR dual port SRAM cell  110  allows data to be displayed to be stored in the cell storage node through a pair of bit lines BL and BLX during the writing operation, and also allows the stored data to be outputted through the data line D during the reading operation. Thus, in the 8 TR dual port SRAM cell  110  as shown in  FIG. 1 , because a path for writing operation is separated from a path for reading operation, the writing and reading operations can be carried out independently, without collision.  
         [0021]     More specifically, operation of the dual port SRAM cell with 8 TRs depends on the basic principle of operation of the single port SRAM shown in  FIG. 1 .  
         [0022]     But, the dual port SRAM cell with 8 TRs further includes PMOS transistors P 12  and P 13  and outputs date in a cell storage node onto a data line D by a control signal on a common line C. In default state, the data line D provides logic L by a pull-down transistor N 14  that consists of NMOS transistor.  
         [0023]     In writing operation for the SRAM memory cell  110 , it first allows H and L level data to be carried on the positive bit line BL and the negative bit line BLX, respectively, and then allows data level on a word line WL to be transited to H state, making the NMOS transistors N 12 A and N 12 B turned-on. At that time, there are stored H and L signals in the nodes cel 1 A and cellB, respectively.  
         [0024]     By applying L level signal onto the common line C, data stored in the SRAM memory cell  110  can be outputted through the data line D.  
         [0025]     But, before the signal is applied onto the common line C, there are carried out the following operations: the full-down transistor N 14  is first turned-on, making the data line D be L level; and, then, the pull-down transistor N 14  is turned-off.  
         [0026]     If L level signal is inputted to the common line C, then the transistor P 13  for the common line&#39;s selection becomes turned-on, thereby outputting signal in a node cellC to the data line D.  
         [0027]     Data in the node cellc is decided by a signal in the node cellB and, if signal stored in the node cellB is L, the pull-up transistor P 12  becomes ON, allowing value in the node cellc to be H. In this case, by turning-on the transistor P 13  for the common line&#39;s selection, H signal is outputted onto the data line D.  
         [0028]     If it makes data “0” written on the SRAM memory cell by inputting L and H signals onto the positive bit line BL and the negative line BLX, respectively, L and H signals are stored in the nodes cellA and cellB, respectively.  
         [0029]     Thus, to read value in the node cellB through the common line C and the transistors P 12  and P 13 , the transistor P 12  is OFF and the transistor P 13  is ON; and thus L level made by the pull-down transistor N 14  is maintained on the data line D that is output node, enabling output of L signal.  
         [0030]     On the other hand, the SRAM having the configuration as shown in  FIG. 2  has an advantage that it is possible to read and write simultaneously, compared to the single port SRAM shown in  FIG. 1 , but has a disadvantage that size per cell is relatively large because it is composed of 8 transistors. As a result, since there are arrays of a number of cells in the SRAM, making RAM embedded TFT LCD driver chip incorporating therein SRAM increased in size.  
       SUMMARY OF THE INVENTION  
       [0031]     It is, therefore, an object of the present invention to provide a SRAM that is capable of performing a writing and reading operations simultaneously without collision while reducing size of cell, by providing a dual port SRAM with 6 transistors.  
         [0032]     In accordance with the present invention, there is provided a dual port SRAM cell with 6 transistors, including: a writing section having a transistor for inputting a data input signal from a bit line in response to a control signal from a word line; a data storage section composed of three transistors for storing the data input signal from the outside through the writing section; and a reading section composed of two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.  
         [0033]     Preferably, the writing section is composed of one transistor whose gate is coupled to a word line, one port is connected to a single bit line and another port is coupled to a transistor that is coupled to the data storage section. And, the data storage section comprises: a second transistor whose gate is coupled to a first node on said another port of the first transistor, and drain and source are connected to a first supply voltage and a second node, respectively; a third transistor whose gate is connected to the second node, and drain and source are coupled to the first node and a second supply voltage, respectively; and a fourth transistor whose gate is connected to the first node, and drain and source are coupled to the first node and the second supply voltage, respectively. Further, the reading section comprises: a fifth transistor whose gate is coupled to the second node, and drain and source are connected to the third node and the second supply voltage, respectively; and a sixth transistor whose gate is connected to a common line C, and drain and source are coupled to a data line D carrying data to be read, and the third node, respectively. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0034]     The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:  
         [0035]      FIG. 1  is a circuit diagram of a single port SRAM memory with 6 transistors according to a prior art;  
         [0036]      FIG. 2  is a circuit diagram of a dual port SRAM memory with 8 transistors according to another prior art;  
         [0037]      FIG. 3  is a circuit diagram of a dual port SRAM memory with 6 transistors in accordance with the present invention; and  
         [0038]      FIG. 4  is a timing diagram showing signal state for each element of the memory circuit shown in  FIG. 3  in accordance with the invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0039]     Hereinafter, configuration and operation of a dual port SPAM cell circuit with 6 transistors of the invention will be described in detail with reference to the accompanying drawings.  
         [0040]      FIG. 3  is a circuit diagram of a dual port SRAM cell with 6 transistors in accordance with the present invention.  
         [0041]     As shown in  FIG. 3 , the dual port SRAM cell  120  having 6 transistors in accordance with the present invention comprises NMOS transistors N 20 A, N 20 , N 21 , N 22 , N 23 , and one PMOS transistor P 21 .  
         [0042]     Unlike the prior arts shown in  FIGS. 1 and 2 , the present invention is provided with only a single bit line BL, wherein there is omitted a negative bit line BLX carrying an inverted one of a signal on the bit line.  
         [0043]     A selection of the memory cell is made through a word line WL and data is stored in the cell via the bit line BL. The data stored is outputted onto the data line DL by a control signal applied through a common line C.  
         [0044]     More specifically, the 6 TR dual port SRAM cell  120  of the invention includes a writing section  122  which has one transistor and receives data signal from the single bit line BL under the control of a signal from the word line WL, a data storage section  124  which is constituted with three transistors and stores the data signal from the writing section  122 , and a reading section  128  which is comprised of two transistors and reads the data signal stored in the data storage section  124  under the control of a signal via the common line C.  
         [0045]     The writing section  122  includes a NMOS transistor N 02 A whose gate is coupled to the word line WL, one side terminal is connected to the bit line BL, and the other side terminal is coupled to the data storage section  124 .  
         [0046]     The NMOS transistor N 20 A is called an access transistor that inputs the signal on the bit line BL by its on or off depending on the signal on the word line WL. In switch ON state, the signal on the bit line BL is delivered to the inside of the memory cell; and, in switch OFF state, it is disconnected from the bit line. This access transistor is largely different from the NMOS transistors N 02 A and N 12 A shown in  FIGS. 1 and 2  in that the cell consists of a single transistor although it performs a same function.  
         [0047]     The data storage section  124  functions to store and maintain the inputted data. To implement this function, it comprises a PMOS transistor P 21  whose gate is coupled to a cell storage node cell 2 A which is connected to the NMOS transistor N 20 A, and drain and source are coupled to a supply voltage VCC and a cell storage node cell 2 B, respectively, a NMOS transistor N 20  whose gate is connected to the cell storage node cell 2 B, and drain and source are coupled to the cell storage node cell 2 A and the ground voltage VSS, respectively, and a NMOS transistor N 21  whose gate is connected to the cell storage node cell 2 A, and drain and source are coupled to the cell storage node cell 2 B and the ground voltage VSS, respectively.  
         [0048]     The reading section  128  includes a NMOS transistor N 22  whose gate is coupled to the cell storage node cell 2 B, and drain and source are connected to the node cell 2 C and the ground voltage, respectively, and a NMOS transistor N 23  whose gate is coupled to a common line C, and drain and source are connected to a data line D carrying read data and the node cell 2 C, respectively.  
         [0049]     The PMOS transistor P 24  for pull-up driving the data line D is added to the outside of the SRAM cell  120 . Although there is not shown, the data line D is commonly coupled to each reading section of a plurality of arrayed memory cells; and, one of them is arranged per each block if memory cell array is blocked and distinguished.  
         [0050]     Hereinafter, operation of the SRAM cell of the present invention shown in  FIG. 3  will be described in detail.  
         [0051]     (1) In WRITE mode:  
         [0052]     User can store 1-bit data of H or L state in one SRAM cell  120 .  
         [0053]     When the user wants to write H signal in the SRAM cell  120  through an input pin of the bit line BL, H signal is first applied through the input pin of the bit line BL. If H signal is inputted onto the word line WL after the H signal is stably set-up in the bit line BL, then the NMOS transistor N 20 A becomes ON and the signal on the bit line BL is outputted onto the node cell 2 A. As a result, the node cell 2 A becomes H state.  
         [0054]     When the node cell 2 A is H state, the PMOS transistor P 21  becomes OFF and then the NMOS transistor N 21  becomes ON state. From this, the node cell 2 B becomes L state and NMOS transistor N 20  also becomes OFF state. As a result, the node cell 2 A becomes H and the node cell 2 B maintains the writing state of L.  
         [0055]     In case of writing L signal in the SRAM memory cell  120 , there is performed in the same manner. First, if L signal is applied onto the bit line BL and H signal is inputted onto the word line WL, then the transistor N 02 A becomes ON, allowing the signal on the bit line BL to be outputted. As a result, the node cell 2 A becomes logic L state.  
         [0056]     When the node cell 2 A is L state, the PMOS transistor P 21  is ON and the NMOS transistor N 21  is OFF. Then, the node cell 2 B becomes H state, NMOS transistor N 20  also becomes ON. Consequently, although the transistor N 02 A is OFF by the word line WL, but the nodes cell 2 A and cell 2 B are maintained as the writing state of logic H.  
         [0057]     (2) In READ mode:  
         [0058]     The data written in the nodes cell 2 A and cell 2 B of the SRAM memory cell  120  can be outputted onto the data line D through two NMOS transistors N 22  and N 23 .  
         [0059]     The data line D becomes logic H state by the PMOS transistor P 24 . The data line D provides L signal only if the two transistors N 22  and N 23  are all ON and outputs H signal if at least one is OFF, among the NMOS transistors N 22  and N 23 .  
         [0060]     The common line C serves to input an output signal for outputting the data written in the memory cell  120 . When the signal on the common line C is H, a same signal level as the data on the node cell 2 A of the memory cell is outputted onto the data line D.  
         [0061]     More specifically, if signal level of the bit line BL is H and thus the node cell 2 A is H state, then the node cell 2 B is L state. Thus, the NMOS transistor N 22  is OFF and H signal is inputted onto the common line C, outputting H signal onto the data line D when the NMOS transistor N 23  is ON.  
         [0062]     Similarly, if signal level of the bit line BL is L and thus the node cell 2 A is L state, then the node cell 2 B is H state. Thus, the NMOS transistor N 22  is ON and H signal is inputted onto the common line C, outputting L signal onto the data line D when the NMOS transistor  23  is ON.  
         [0063]      FIG. 4  provides signal waveforms showing a simulation result of each part of the SRAM memory cell circuit in accordance with the present invention shown in  FIG. 3 .  
         [0064]     In  FIG. 4 , signals, BL, WL, C, and pull-up, are control signals of the bit line BL, the word line WL and the common line C, and also control signal of the PMOS pull-up transistor P 24 , respectively.  
         [0065]     Signals, Cell 2 A, Cell 2 B and Cell 2 C, are signal values at the node cell 2 A, the node cell 2 B and the node cell 2 C that are placed in the inside of the SRAM  120  shown in  FIG. 3 , respectively.  
         [0066]     Further, a signal D is data signal that is outputted onto the data line D from the SRAM memory cell.  
         [0067]     Now, process of applying data onto the nodes cell 2 A and cell 2 B of the SRAM memory cell through the bit line BL will be explained in detail.  
         [0068]     As shown in  FIG. 4 , level of Cell 2 A signal is transited to a same level as the BL signal whenever the WL signal is transited to H state. This means that the signal of the bit line BL is outputted onto the node cell 2 A as it is, depending on the control signal on the word line WL.  
         [0069]     On the other hand, the Cell 2 B signal always has a waveform that is of an inverse state to the Cell 2 A signal. This is to confirm that they have level inversion relationship between the Cell 2 B signal and the Cell 2 A signal.  
         [0070]     In addition, even if the WL signal is transmitted from H to L, values of Cell 2 A and Cell 2 B signals are unchanged. This is to confirm that electrical potentials at the nodes cell 2 A and cell 2 B maintain without change although the NMOS transistor N 20 A that is access transistor is OFF by changing signal value on the word line WL from H to L in the memory cell circuit of  FIG. 3 . From the above, it can be seen that the memory cell of  FIG. 3  can perform functions as memory well.  
         [0071]     When reading the data written in the SRAM cell, it is possible to do so by making the control signal C inputted onto the common line C.  
         [0072]     Meanwhile, before the data is read through the common signal C, it makes output data signal D on the data line D pulled-up in H state by using an input signal, pull-up, that is inputted to the PMOS transistor P 24 . In  FIG. 3 , the pull-up transistor P 24  is operated when input thereto is L; and thus the output data signal D on the data line D has H state when the pull-up signal, pull-up, is L.  
         [0073]     When the pull-up signal, pull-up, of L is outputted and then the output data signal D is pulled-up in H state, data written in the memory cell may be outputted onto the data line D if a control signal C that is read signal READ is inputted to the SRAM memory cell.  
         [0074]     In  FIG. 4 , in the state that it is maintained that Cell 2 A is H and Cell 2 B is L, if instruction to read data is inputted by transiting the control signal C to H, H signal is outputted onto the data line D. Further, in the state that it is maintained that Cell 2 A is L and Cell 2 B is H, if instruction to read data is inputted by transiting the control signal C to H, L signal is outputted onto the data line D.  
         [0075]     With the method as mentioned above, in response to BL, WL, C, that are signal values on the bit line BL, the word line WL, and the common line C, signal levels of Cell 2 A and Cell 2 B, that are data stored in the nodes cell 2 A and cell 2 B that are inside nodes of the SRAM memory cell, can be outputted onto the data line D as output data signal D.  
         [0076]     By using the configurative features as mentioned above, the present invention can provide the dual port SRAM cell that utilizes 6 MOS transistors having advantages that it can improve degree of integration of the single port SRAM that is designed by 6 MOS transistors in the prior art (see  FIG. 1 ) and the prior art dual port SRAM that is designed by 8 MOS transistors can perform writing and reading operations simultaneously (see  FIG. 2 ).  
         [0077]     The present application contains subject matter related to Korean patent application No. 2004-22194, filed in the Korean Patent Office on Mar. 31, 2004, the entire contents of which being incorporated herein by reference.  
         [0078]     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.