Abstract:
A semiconductor memory device analyzes tRCD inferiority by simultaneously interlock-controlling an enable time of column address and an access time of cell data. The semiconductor memory device includes a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address, and an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals in a read/write operation mode, and controlling a column address enable signal to activate the bank column address to have the same enable delay time as the bank control signal.

Description:
FIELD OF THE INVENTION 
   The present invention relates to semiconductor design technologies, and more particularly, to a technique capable of analyzing tRCD inferiority by simultaneously controlling both an enable time of a column address and an access time of cell data. 
   BACKGROUND 
   In general, a semiconductor memory device such as Dynamic Random Access Memory (DRAM) is driven by a row address and a column address externally provided.  FIG. 1  is a block diagram of a conventional semiconductor memory device. 
   The conventional semiconductor memory device includes a global column address controller  10 , a clock controller  20 , a bank column address controller  30 , a command controller  40 , a column address enable controller  50  and a Column Address (CA) latch unit  60 . 
   The global column address controller  10  is provided with an address (ADD) pad  11 , an ADD buffer  12 , an ADD latch  13 , an ADD selector  14 , an Additive Latency (AL) shift register  15 , a CA selector  16 , and a CL shift (CL+1(+3) shift register  17 . 
   The clock controller  20  is provided with a clock (CK/CKB) pad  21  and a clock (CLK/CLKB) buffer  22 . 
   The bank column address controller  30  is equipped with a Bank Address (BA) pad  31 , an ADD buffer  32 , an ADD latch  33 , an ADD selector  34 , an AL shift register  35 , a CL shift (CL+1(+3) shift register  36 , a CA selector  37 , and a BA decoder  38 . 
   The command controller  40  is composed of a command (CMD) pad  41 , a CMD buffer  42 , a CMD latch  43 , a CMD decoder  44 , AL shift registers  45  and  46 , and a CL shift register  47 . The column address enable controller  50  is provided with a column address enable (YAE) signal generator  51 , a YAE signal delay unit  52 , and a YAE signal decoder  53 . The CA latch unit  60  is provided with a CA latch  61 . 
     FIG. 2  is a detailed circuit diagram of the BA decoder  38  shown in  FIG. 1 . 
   The BA decoder  38  is composed of a plurality of inverters IV 1  to IV 6  and a plurality of NAND gates ND 1  to ND 4  to logically multiply signals input thereto. As illustrated, the BA decoder  38  is applied to a semiconductor memory device having a 4-bank structure. 
   More specifically, the NAND gate ND 1  NAND-operates a bank address BA 0  inverted by the inverter IV 1  and a bank address BA 1  inverted by the inverter IV 2 . The NAND gate ND 2  NAND-operates the bank address BA 0  and the bank address BA 1  inverted by the inverter IV 2 . The NAND gate ND 3  NAND-operates the bank address BA 0  inverted by the inverter IV 1  and the bank address BA 1 . The NAND gate ND 4  NAND-operates the bank addresses BA 0  and BA 1 . 
   The inverter IV 3  inverts an output of the NAND gate ND 1  to provide a bank column address CBA&lt;0&gt; . The inverter IV 4  inverts an output of the NAND gate ND 2  to output a bank column address CBA&lt;1&gt; . The inverter IV 5  inverts an output of the NAND gate ND 3  to provide a bank column address CBA&lt;2&gt; . The inverter IV 6  inverts an output of the NAND gate ND 4  to provide a bank column address CBA&lt;3&gt;. 
   The following is an operation description of the conventional semiconductor memory device having the configuration as mentioned above, which is made with reference to an operation timing diagram shown in  FIG. 3 . In the operation timing diagram of  FIG. 3 , it is assumed that in Double Data Rate Two Synchronous DRAM (DDR 2  SDRAM) AL is “2,” CL is “6” and Burst Length (BL) is “4.” 
   The column address is controlled by the global column address controller  10  and the bank column address controller  30 . The global column address controller  10  serves to control a global column address for each bank to access (read or write) data of a sense amplifier. The bank column address controller  30  is to control a bank column address having information of a bank to be selected. Here, the bank column address implies a column address enable signal to latch the bank selected according to the global column address. 
   Each column address is generated in an identical sequence under the control of the clock controller  20  and the command controller  40 . The clock buffer  22  buffers clocks (CLK and CLKB) provided from the clock pad  21  to provide the same as an overall synchronizing signal within a chip. 
   An address applied to the ADD pad  11  is fed to the ADD latch  13  via the ADD buffer  12 . A bank address at the BA pad  31  is delivered to the ADD latch  33  via the ADD buffer  32 . At this time, the ADD latches  13  and  33 , as shown in A(A′) of  FIG. 3 , outputs the addresses to the ADD selectors  14  and  34  in synchronism with a falling edge of a clock CLK provided from the clock buffer  22 , respectively. 
   Thereafter, when a write command WT or read command RD is applied to the CMD pad  41 , it is delivered to the ADD selectors  14  and  34 , in which the column addresses are queued, in synchronism with the falling edge of the clock CLK, as in the address. 
   Further, as depicted in B(B′) of  FIG. 3 , a signal is output to the AL shift registers  15  and  35  to perform the AL and CL functions depending on Mode Register Set (MRS) that is set by latching the column address. 
   At this time, Read Latency (RL) becomes AL+CL and Write Latency (WL) becomes RL- 1  in DDR2 spec, which leads to AL+CL−1. In the read mode, the column address is shifted by the clock number of AL value, as in D(D′) of  FIG. 3 , and the clock corresponding to CL value is shifted by the CL clock number in a block that outputs data to a DQ pad. 
   When the read command is input, a read command signal RDP is output through the CMD decoder  44  followed by the same AL shift register  45  as in the column address. The column addresses through the AL shift registers  15  and  35  are applied to the CA selectors  16  and  37 , which take the read command signal RDP and provide read column addresses, as in E(E′) of  FIG. 3 . 
   On the other hand, in the write mode, the column address is shifted by WL and further shifted by BL/2. The DDR 2  is characterized by 4-bit pre-fetch. Here, in order to perform the 4-bit pre-fetch, 2-clock is required where BL=4 and 4-clock where BL=8, by conducting the fetch at the rising edge and falling edge of every clock. 
   In the write mode, data is input after WL, and therefore, more time is needed to fetch the data in order to make the data internally aligned. By further shifting the data by that time, the write column address can be synchronized with the data on the Global Input/Output (GIO) bus at the same timing. Accordingly, the write column address, as in D(D′) of  FIG. 3 , is shifted by AL+CL+1 where BL=4 (2-clock) and AL+CL+3 where BL=8 (4-clock). 
   The write command is shifted by the same clock number via the CMD decoder  44  to output the write command signal WTP. The write command signal WTP of the CMD decoder  44  is then applied to the CA selectors  16  and  37  to provide write column addresses, as in E(E′) of  FIG. 3 . 
   Among the output addresses, the column address as in E of  FIG. 3  is globally delivered to all banks; and the bank column address as in E&#39; of  FIG. 3  is decoded by the BA decoder  38  and a signal as in CBA of  FIG. 3  is then output to only a selected bank. The output signal CBA of the BA decoder  38  is latched by the CA latch  60  and then delivered to the selected bank. 
   Meanwhile, the YAE signal generator  51  combines the read command signal RDP, the write command signal WTP and the CAS signal ICASP (where BL=8). And the YAE signal delay unit  52  delays an output signal of the YAE signal generator  51  for a certain time. The YAE signal decoder  53  decodes a bank information signal BBY&lt;0:3&gt; and an output signal of the YAE signal delay unit  52  to provide a column address enable signal YAE&lt;0:3&gt; to the selected bank. 
   At this time, during the write operation in the selected bank, the data transferred from the GIO bus is stored in a corresponding cell according to an enable of a write driver (WTDRV). During the read operation in the selected bank, a developed signal of data transferred through local input/output buses SIO and LIO is amplified in a bit line sense amp depending on an enable of an Input/Output Sense Amp (IOSA) and then fed to the GIO bus. Thus, it is required to maintain a constant interval with the column address in order to secure a margin during the write and read operations. For this, the YAE signal delay unit  52  delays the column address enable signal YAE for a certain time. 
   The column address is delivered after the row address is provided to the bank together with an active command. This elapsed time is defined as tRCD [Row Address Strobe (RAS) to CAS Delay], which may be 15 ns as 6-clock where CL=6. This means time that the data of the sense amp can be accessed by the column address after the word line is enabled by the row address and thus the sense amp is sufficiently operated. Such tRCD time is used as an index to determine the performance, wherein the performance is judged to be excellent as it is shorter. 
   Therefore, there is no problem if tRCD margin is sufficient, but there is problem in delaying the externally applied column address if it is deficient. 
   In addition, there is a recent trend to require low latency products with tRCD decreased by 1 clock in comparison with the spec. Accordingly, although there is tRCD margin in the spec, lack of margin may happen due to operation under such tRCD state decreased by 1 clock. 
   SUMMARY OF THE INVENTION 
   It is, therefore, an object of the present invention to provide a semiconductor memory device capable of analyzing tRCD inferiority by simultaneously controlling both an enable time of column address and an access time of cell data. 
   In accordance with one aspect of the present invention, there is provided a semiconductor memory device including: a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address; and an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals in a read/write operation mode, and controlling a column address enable signal to activate the bank column address to have the same enable delay time as the bank control signal. 
   In accordance with another aspect of the present invention, there is provided a semiconductor memory device including: a bank column address controller for decoding an bank address and a bank control signal to provide a bank column address; an enable controller for outputting a plurality of control signals with different states in response to a test mode signal, outputting the bank control signal of which enable delay time is controlled by a selective activation state of the plurality of control signals, and controlling the access enable time of cell data to have the same delay time as the bank control signal; and a bank for controlling an access operation of the cell data depending on the bank column address in a read/write operation mode. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the instant invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram of a conventional semiconductor memory device; 
       FIG. 2  is a detailed circuit diagram of the BA decoder shown in  FIG. 1 ; 
       FIG. 3  is an operation timing diagram of the conventional semiconductor memory device; 
       FIG. 4  is a block diagram of a configuration of a semiconductor memory device in accordance with a preferred embodiment of the present invention; 
       FIG. 5  is a detailed circuit diagram of the BA decoder shown in  FIG. 4 ; 
       FIG. 6  is a detailed circuit diagram of the pulse generator and the mode delay unit shown in  FIG. 4 ; 
       FIG. 7  is a detailed circuit diagram of the mode controller shown in  FIG. 4 ; 
       FIG. 8  is a detailed circuit diagram of the mode delay unit and the mode selector shown in  FIG. 4 ; and 
       FIG. 9  is an operation timing diagram of the semiconductor memory device in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Hereinafter, preferred embodiments of the present invention will be set forth in detail with reference to the accompanying drawings. 
     FIG. 4  is a block diagram of a semiconductor memory device in accordance with a preferred embodiment of the present invention. 
   The semiconductor memory device of the present invention includes a global column address controller  10 , a clock controller  20 , a bank column address controller  30 , a command controller  40 , a column address latch  60 , a column address enable controller  100 , a mode controller  200 , and a control signal generator  300 . In the following embodiments, like reference numerals identify like elements and a construction and operation description of like elements will be omitted. 
   The column address enable controller  100  is provided with a YAE signal generator  110 , a YAE signal delay unit  120 , a mode delay unit  130 , a mode selector  140 , and a YAE signal decoder  150 . 
   The mode controller  200  is provided with a mode generator  210 , a mode selector  220  and a mode decoder  230 . And the control signal generator  300  is provided with a pulse generator  310  and a mode delay unit  320 . 
     FIG. 5  is a detailed circuit diagram of the BA decoder  38 - 1  shown in  FIG. 4 . 
   As shown therein, the BA decoder  38 - 1  is composed of a plurality of inverters IV 7  to IV 16  and a plurality of NAND gates ND 5  to ND 12 . Here, it is illustrated that the BA decoder  38 - 1  is applied to a semiconductor memory device having a 4-bank structure. 
   More specifically, the NAND gate ND 5  NAND-operates a bank address BA 0  inverted by the inverter IV 7  and a bank address BA 1  inverted by the inverter IV 8 . The NAND gate ND 6  NAND-operates the bank address BA 0  and the bank address BA 1  inverted by the inverter IV 8 . The NAND gate ND 7  NAND-operates the bank address BA 0  inverted by the inverter IV 7  and the bank address BA 1 . The NAND gate ND 8  NAND-operates the bank addresses BA 0  and BA 1 . 
   In succession, the NAND gate ND 9  NAND-operates an output of the inverter IV 9  following the NAND gate ND 5  and a control signal CBA_CTRL. The NAND gate ND 10  NAND-operates an output of the inverter IV 10  following the NAND gate ND 6  and the control signal CBA_CTRL. The NAND gate ND 11  NAND-operates an output of the inverter IV 11  following the NAND gate ND 7  and the control signal CBA_CTRL. The NAND gate ND 12  NAND-operates an output of the inverter IV 12  following the NAND gate ND 8  and the control signal CBA_CTRL. 
   The inverter IV 13  inverts an output of the NAND gate ND 9  to provide a bank column address CBA&lt; 0 &gt;. The inverter IV 14  inverts an output of the NAND gate ND 10  to output a bank column address CBA&lt; 1 &gt; . The inverter IV 15  inverts an output of the NAND gate ND 11  to provide a bank column address CBA&lt; 2 &gt;. The inverter IV 16  inverts an output of the NAND gate ND 12  to provide a bank column address CBA&lt; 3 &gt;. 
     FIG. 6  is a detailed circuit diagram of the pulse generator  310  and the mode delay unit  320  shown in  FIG. 4 . 
   The pulse generator  310  is provided with inverters IV 17  to IV 19  and an NAND gate ND 13 . Here, the NAND gate ND 13  NAND-operates a read command signal RDP inverted by the inverter IV 17 , a write command signal WTP inverted by the inverter IV 18  and a CAS signal ICASP inverted by the inverter IV 19 . 
   The mode delay circuit  320  is provided with an inverter IV 20 , a plurality of NAND gates ND 14  to ND 26  connected in series and a plurality of NAND gates ND 27  to ND 33  connected in parallel. Here, the inverter IV 20  inverts a control signal C 7 . 
   The plurality of NAND gates ND 27  to ND 33  connected in parallel NAND-operates control signals C 6  to C 1  and an output of the NAND gate ND 13  to provide their outputs to odd NAND gates out of the NAND gates ND 14  to ND 26 , respectively. The plurality of NAND gates ND 14  to ND 26  connected in series NAND-operates outputs of their respective previous NAND gates and a power supply voltage VDD or outputs of the NAND gates ND 27  to ND 33  to provide a control signal CBA_CTRL. 
     FIG. 7  is a detailed circuit diagram of the mode controller  200  shown in  FIG. 4 . 
   The mode generator  210  is provided with PMOS transistors P 1  to P 3 , NMOS transistors N 1  to N 9 , fuses F 1  to F 3 , inverters IV 21  to IV 26 , and NOR gates NOR 1  to NOR 4 . 
   The PMOS transistor P 1  and the NMOS transistors N 1  and N 2  are connected in series between a power supply voltage end VDD and a ground voltage end. The PMOS transistor P 1  receives a test mode setting signal TMSET via its gate terminal, the NMOS transistor N 1  receives a reset signal RSTP via its gate terminal, and the NMOS transistor N 2  receives the power supply voltage via its gate terminal. 
   The fuse F 1  and the NMOS transistor N 3  are connected in series between the power supply voltage end and the ground voltage end and the NMOS transistor N 3  receives an output of the inverter IV 21  via its gate terminal. The NOR gate NOR 1  NOR-operates the output of inverter IV 21  and a test signal TM&lt; 0 &gt; and the inverter IV 22  inverts an output of the NOR gate NOR 1 . 
   Similarly, the PMOS transistor P 2  and the NMOS transistors N 4  and N 5  are connected in series between the power supply voltage end and the ground voltage end. The PMOS transistor P 2  receives the reset signal RSTP via its gate terminal, the NMOS transistor N 4  receives the test mode setting signal TMSET via its gate terminal, and the NMOS transistor N 5  receives the power supply voltage via its gate terminal. 
   The fuse F 2  and the NMOS transistor N 6  are connected in series between the power supply voltage end and the ground voltage end and the NMOS transistor N 6  receives an output of the inverter IV 23  via its gate terminal. The NOR gate NOR 2  NOR-operates the output of inverter IV 23  and a test signal TM&lt; 1 &gt; and the inverter IV 24  inverts an output of the NOR gate NOR 2 . 
   Likewise, the PMOS transistor P 3  and the NMOS transistors N 7  and N 8  are connected in series between the power supply voltage end and the ground voltage end. The PMOS transistor P 3  receives the reset signal RSTP via its gate terminal, the NMOS transistor N 7  receives the test mode setting signal TMSET via its gate terminal, and the NMOS transistor N 8  accepts the power supply voltage via its gate terminal. 
   The fuse F 3  and the NMOS transistor N 9  are connected in series between the power supply voltage end and the ground voltage end and the NMOS transistor N 9  receives an output of the inverter IV 25  via its gate terminal. The NOR gate NOR 3  NOR-operates the output of inverter IV 25  and a test signal TM&lt;2&gt; and the inverter IV 26  inverts an output of the NOR gate NOR 3 . And the NOR gate NOR 4  NOR-operates the outputs of inverters IV 22 , IV 24  and IV 26  and the test mode setting signal TMSET. 
   The mode selector  220  is provided with inverts IV 27  to IV 29 , NAND gates ND 34  to ND 42 , and switches SW 1  to SW 3  of which switching operations are controlled depending on a metal option M 0 . 
   The NAND gate ND 34  NAND-operates an output of the inverter IV 27  following the NOR gate NOR 4  and an output of the inverter IV 22 . The NAND gate ND 35  NAND-operates an output of the switch SW 1  and the output of the NOR gate NOR 4 . The NAND gate ND 36  NAND-operates outputs of the NAND gates ND 34  and ND 35 . 
   Similarly, the NAND gate ND 37  NAND-operates an output of the inverter IV 24  and an output of the inverter IV 28  following the NOR gate NOR 4 . The NAND gate ND 38  NAND-operates an output of the switch SW 2  and the output of the NOR gate NOR 4 . The NAND gate ND 39  NAND-operates outputs of the NAND gates ND 37  and ND 38 . 
   In the same manner, the NAND gate ND 40  NAND-operates an output of the inverter IV 26  and an output of the inverter IV 29  following the NOR gate NOR 4 . The NAND gate ND 4 l NAND-operates the output of the switch SW 3  and an output of the NOR gate NOR 4 . The NAND gate ND 42  NAND-operates outputs of the NAND gates ND 40  and ND 41 . 
   In succession, the mode decoder  230  is provided with a plurality of inverters IV 30  to IV 40  and a plurality of NAND gates ND 43  to ND 50 . The NAND gate ND 43  NAND-operates outputs of the inverters IV 30  to IV 32 . The NAND gate ND 44  NAND-operates an output of the NAND gate ND 36  and outputs of the inverters IV 31  and IV 32 . The NAND gate ND 45  NAND-operates outputs of the inverters IV 30  and IV 32  and an output of the NAND gate ND 39 . The NAND gate ND 46  NAND-operates outputs of the NAND gates ND 36  and ND 39  and an output of the inverter IV 32 . 
   The NAND gate ND 47  NAND-operates outputs of the inverters IV 30  to IV 31  and an output of the NAND gate ND 42 . The NAND gate ND 48  NAND-operates outputs of the NAND gates ND 36  and ND 42  and an output of the inverter IV 31 . The NAND gate ND 49  NAND-operates an output of the inverter IV 30  and outputs of the NAND gates ND 39  and ND 42 . The NAND gate ND 50  NAND-operates outputs of the NAND gates ND 36 , ND 39  and ND 42 . 
   The inverter IV 33  inverts an output of the NAND gate ND 43  to output a control signal C&lt; 0 &gt; , the inverter IV 34  inverts an output of the NAND gate ND 44  to output a control signal C&lt; 1 &gt;, the inverter IV 35  inverts an output of the NAND gate ND 45  to output a control signal C&lt; 2 &gt; , the inverter IV 36  inverts an output of the NAND gate ND 46  to output a control signal C&lt; 3 &gt;, and the inverter IV 37  inverts an output of the NAND gate ND 47  to output a control signal C&lt; 4 &gt; . The inverter IV 38  inverts an output of the NAND gate ND 48  to output a control signal C&lt; 5 &gt;, the inverter IV 39  inverts an output of the NAND gate ND 49  to output a control signal C&lt; 6 &gt; , and the inverter IV 40  inverts an output of the NAND gate ND 50  to output a control signal C&lt; 7 &gt;. 
     FIG. 8  illustrates a detailed circuit diagram of the mode delay unit  130  and the mode selector  140  shown in  FIG. 4 . 
   As shown therein, the mode delay unit  130  is provided with an inverter IV 41 , a plurality of NAND gates ND 51  to ND 63  connected in series and a plurality of NAND gates ND 64  to ND 70  connected in parallel. The inverter IV 41  inverts the control signal C 7 . 
   The plurality of NAND gates ND 64  to ND 70  connected in parallel NAND-operates control signals C 6  to C 1  and an output IN of the YAE signal delay unit  120  to provide their outputs to odd NAND gates out of the NAND gates ND 51  to ND 63 , respectively. The plurality of NAND gates ND 51  to ND 63  connected in series NAND-operates outputs of their respective previous NAND gates and the power supply voltage or outputs of the NAND gates ND 64  to ND 70 . 
   Subsequently, the mode selector  140  is provided with an inverter IV 42  and NAND gates ND 71  to ND 73 . Here, the NAND gate ND 71  NAND-operates an output of the NAND gate ND 63  and a control signal C 7  inverted by the inverter IV 42 . The NAND gate ND 72  NAND-operates the control signal C 7  and the output IN of the YAE signal delay unit  120 . The NAND gate ND 73  NAND-operates outputs of the NAND gates ND 71  and ND 72  to provide a mode selection signal MS to the next YAE signal decoder  150 . The YAE signal decoder  150  decodes the MS and a bank information sianal BBY&lt; 0 : 3 &gt; to provide a colunm address enable signal YAE&lt; 0 : 3 &gt; to the selected bank. 
   A detailed operation procedure of the present invention having the configuration as above will be described with reference to an operation timing diagram shown in  FIG. 9 . 
   First, the pulse controller  310  NAND-operates the read command signal RDP, the write command signal WTP and the internal CAS signal ICASP to provide an output signal to the mode delay unit  320 . The mode controller  200  makes a mode selection depending on a metal option, a fuse option or a test mode option. 
   Then, the mode generator  210  provides a low level signal by connecting the fuse F 1  to the power supply voltage end under the normal state that the fuse F 1  is not cut. In contrast, a final output of the mode generator  210  becomes a high level by making a connection node of the fuse F 1  maintained at a low level by a latch composed of the inverter IV 21  and the NMOS transistor N 3  when the fuse F 1  is cut. 
   There may be a floating state wherein the PMOS transistor P 1  and the NMOS transistor N 1  connected at the same node are all disabled. Thus, at the moment of the power-up operation, the reset signal RSTP for initialization is applied as a pulse signal to the gate terminal of the NMOS transistor N 1 . In response thereto, the node to which the fuse F 1  is connected is controlled to be a low level during the initialization operation, thereby rendering the output of the latch composed of the inverter IV 21  and the NMOS transistor N 3  maintained at a high level. 
   That is, if the fuse F 1  is not cut, the output of the inverter IV 21  becomes logic low, and if the fuse F 1  is cut, the output of the inverter IV 21  becomes logic high. At this time, if the test mode setting signal TMSET is activated, the PMOS transistor P 1  becomes turned on. Based on this, upon initialization, the fuse F 1  becomes cut and thus the output of the inverter IV 21  is maintained to be a low level even when the output of the latch (composed of the inverter IV 21  and the NMOS transistor N 3 ) is kept to be a high level. 
   Therefore, if the test mode setting signal TMSET is input, the fuse F 1  is under the state that is not cut although it is actually cut. Further, if the test signal TM&lt; 0 : 2 &gt; that is another test mode signal is input, the output value is decided based on it. 
   Thereafter, the mode selector  220  selects one of the output of the switch SW 1  by the metal option and the output of the mode generator  210 . 
   Under the normal state that the fuse F 1  is not cut and the test mode setting signal TMSET is inactivated, the output of the mode generator  210  becomes logic low. In this case, the output of the switch SW 1  decided by the metal option becomes the power supply voltage or ground voltage level and then provided to the mode decoder  230 . At this time, the metal option can be set by proceeding with revision. 
   In contrast, if the fuse F 1  is cut or the test signal TM&lt; 0 : 2 &gt; is input depending on the test mode setting signal TMSET, the value by the metal option is neglected and the value by the fuse F 1  or test signal TM&lt; 0 : 2 &gt; is output to the mode decoder  230 . At this time, in case of selecting the metal option, fuse and test mode, it is preferable to decide them in the order of test mode, fuse and metal option. 
   In succession, the mode decoder  230  decodes the output of the mode selector  220  to output the control signal C&lt; 0 : 7 &gt; to each of the mode delay unit  320  to control the bank column address and the mode delay unit  130  to decide the activation time of the column address enable signal. 
   Next, the mode delay unit  320  allows the rising time and falling time of a signal delayed by the delay block composed of NAND to NAND gate to have same characteristics. Thus, the number of NAND gates enabled in the mode delay unit  320  is varied depending on the control signal C&lt; 0 : 7 &gt; decoded by the mode decoder  230 . Based on this, the delay value is varied. 
   The amount of delay is varied with the delay width to length ratio of the NAND gate. With regard to the delay variation rate, the NAND gate delay passes 4-stage if the control signal C 0  that is the default value is enabled, and is decreased step by step if the control signals are enabled in the order of C 3 , C 2  and C 1 . On the contrary, if the control signals are enabled in the order of C 4 , C 5  and C 6 , the delay is increased step by step. 
   The delay variation amount of the column address and the column address enable signal YAE according to the output of the mode decoder  230  is shown in Table 1 below. 
   
     
       
             
             
             
             
             
           
         
             
               TABLE 1 
             
             
                 
             
             
                 
               TM1, 
               TM0, 
               Control 
               Delay variation 
             
             
               TM2, F3, SW3 
               F2, SW2 
               F1, SW1 
               signal C 
               rate 
             
             
                 
             
           
           
             
               0 
               0 
               0 
               C0 
               Default 
             
             
               0 
               0 
               1 
               C1 
               Decreased by 3-step 
             
             
               0 
               1 
               0 
               C2 
               Decreased by 2-step 
             
             
               0 
               1 
               1 
               C3 
               Decreased by 1-step 
             
             
               1 
               0 
               0 
               C4 
               Increased by 1-step 
             
             
               1 
               0 
               1 
               C5 
               Increased by 2-step 
             
             
               1 
               1 
               0 
               C6 
               Increased by 3-step 
             
             
               1 
               1 
               1 
               C7 
               0 
             
             
                 
             
           
        
       
     
   
   Thereafter, the bank control signal CBA_CTRL with the variation rate of enable time is provided to the BA decoder  38 - 1 . The BA decoder  38 - 1  decodes the bank addresses BA 0  and BAl and again decodes the decoded signal and the bank control signal CBA_CTRL to output the bank column address CBA&lt;3&gt; and Column Address Control Pulse (CACP) to the column address latch  60 . Then, the column address latch  60  latches the bank column address CBA&lt; 3 &gt; and outputs it in the shape of pulse, as in F of  FIG. 9 . 
   If the control signal C 7  is enabled, the bank control signal CBA_CTRL that is the output of the mode decoder  320  is fixed to be logic high so that the decoder following the BA decoder  38 - 1  becomes the stand-by state. Accordingly, the primary decoding result of the bank column address can be output to the bank as it is. 
   The mode delay unit  130  is also operated in the same manner as the mode delay unit  320 . If the control signal C 7  is enabled, the output of the mode delay unit  130  becomes logic low. Then, the logic low is applied to the mode selector  140 , and thus, the output of the NAND gate ND 71  becomes logic high. Based on the output of the NAND gate ND 71 , its output is decided. 
   At this time, since the input signal of the NAND gate ND 72  is just the output IN of the YAE signal delay unit  120 , the mode selection signal MS that is the output of the NAND gate ND 73  has the same shape as the bank column address. Accordingly, the bank column address and the column address enable signal YAE can be controlled simultaneously by increasing or decreasing their enable time. 
   The bank column address and the column address enable signal YAE according to the present invention can be controlled in the same way depending on the metal option, fuse cutting or test mode. Further, it is possible to again change tRCD time by cutting fuse even when tRCD margin is bad due to effects such as environments upon the test, under the state that the timing of the bank column address and the column address enable signal is increased or decreased by proceeding with revision according to a change of tRCD on the basis of characteristics of chip. 
   Furthermore, if packaging of the chip is in progress, it is also possible to analyze tRCD inferiority by changing the enable timing of the bank column address and the column address enable signal YAE using the test mode. 
   As set forth above, the present invention can enable inferiority analysis and also improve yield by setting the enable signal of the column address as an optimal value by its change if the timing margin of tRCD is sufficient or deficient within the chip, in forming DRAM or semiconductor device. 
   The present application contains subject matter related to Korean patent application Nos. 2005-91551 and 2006-29649, filed with the Korean Intellectual Property Office on Sep. 29, 2005 and Mar. 31, 2006, the entire contents of which are incorporated herein by reference. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.