Abstract:
A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

Description:
RELATED APPLICATIONS 
     The present application is related to, and incorporates by reference, U.S. Provisional Patent Application Ser. No. 60/591,499 filed by Mario Au, Jason Z. Mo, Xiaoping Fang, Hui Su, Cheng-Han Wu, Ta-Chung Ma and Lan Lin on Jul. 26, 2004. The present application is also related to, and incorporates by reference, U.S. Provisional Patent Application Ser. No. 60/600,347 filed by Mario Au, Jason Z. Mo, Xiaoping Fang, Hui Su, Cheng-Han Wu, Ta-Chung Ma and Lan Lin on Aug. 9, 2004. 
     The present application is also related to, and incorporates by reference, the following commonly owned, co-filed U.S. patent applications. 
     U.S. Patent Application Ser. No. 11/040,895, now U.S. Pat. No. 7,099,231 “Interleaving Memory Blocks to Relieve Timing Bottleneck in a Multi-Queue First-In First-Out Memory System” by Mario Au, Jason Z. Mo, Ta-Chung Ma and Lan Lin. 
     U.S. patent application Ser. No. 11/040,637 “Mark/Re-Read and Mark/Re-Write Operations in a Multi-Queue First-In First-Out Memory System” by Mario Au and Jason Z. Mo. 
     U.S. patent application Ser. No. 11/040,896 “Partial Packet Read/Write and Data Filtering in a Multi-Queue First-In First-Out Memory System” by Mario Au, Jason Z. Mo and Hui Su. 
     U.S. patent application Ser. No. 11/040,804, now U.S. Pat. No. 7,257,687 “Synchronization of Active Flag and Status Bus Flags in a Multi-Queue First-In First-Out Memory System” by Mario Au, Jason Z. Mo and Cheng-Han Wu. 
     U.S. patent application Ser. No. 11/040,893 “Status Bus Accessing Only Available Quadrants During Loop Mode Operation in a Multi-Queue First-In First-Out Memory System” by Mario Au, Jason Z. Mo and Cheng-Han Wu. 
     U.S. patent application Ser. No. 11/040,926 “Multi-Queue Address Generator for Start and End Addresses in a Multi-Queue First-In First-Out Memory System” by Mario Au, Jason Z. Mo and Xiaoping Fang. 
     U.S. patent application Ser. No. 11/040,927, now U.S. Pat. No. 7,154,327 “Self-Timed Multiple Blanking For Noise Suppressiong During Flag Generation in a Multi-Queue First-In First-Out Memory System” by Mario Au and Jason Z. Mo. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a multi-queue first in, first out (FIFO) memory. 
     PRIOR ART 
     In a conventional multi-queue FIFO memory, a queue switch may be performed, wherein during a read (or write) operation, processing switches from one queue (a present queue) to another queue (a new queue). 
       FIG. 1  is a waveform diagram illustrating a typical queue switch performed during a read operation. Read operations in the conventional multi-queue FIFO memory are performed to provide output data (DOUT) in response to a read clock signal (RCLK), a read enable signal (REN#), a read address enable signal (RADEN), a read counter value (RCNT), a write counter value (WCNT), a programmable almost empty flag (PAE#) and an empty flag (EF). 
     In  FIG. 1 , the read enable signal REN# is activated low, thereby indicating that read operations should be performed. The read clock signal RCLK exhibits queue switch cycles QS- 1 , QS 0 , QS 1 , QS 2  and QS 3 , which are labeled with respect to the time that the read address enable signal RADEN is activated. The read address enable signal RADEN is activated prior to the beginning of cycle QS- 1 , thereby indicating that a queue switch should be performed. That is, data should no longer be read from a present queue (PQ), but rather from a new queue (NQ) identified by a new read address (not shown). In the described example, there is a four-cycle latency during a queue switch, such that data (NQ 1 , NQ 2 ) is not read from the new queue until cycle QS 3 . 
     After the read address enable signal RADEN is activated, data values PQ 1 , PQ 2 , PQ 3  and PQ 4  are read from the present queue during the next four cycles QS- 1 , QS 0 , QS 1 , and QS 2 , respectively. During the cycles QS- 1 , QS 0  and QS 1 , the read counter value (RCNT P ) and write counter value (WCNT P ) associated with the present queue are compared to generate the present programmable almost empty flag (PAE# P ) and the present empty flag (EF P ). 
     Also during cycles QS- 1 , QS 0  and QS 1 , the read counter value (RCNT N ) and the write counter value (WCNT N ) associated with the new queue are retrieved from memory. The new read counter value RCNT N  and the new write counter value WCNT N  become active during cycle QS 2 . The new read counter value RCNT N  and the new write counter value WCNT N  are compared to generate a new programmable almost empty flag value (PAE# N ) and a new empty flag value (EF N ), which also become active during cycle QS 2 . Thus, during cycle QS 2 , the programmable almost empty flag PAE# and the empty flag EF represent the status of the new queue, even though the data value PQ 4  is read from the present queue during cycle QS 2 . 
     A problem will exist if the present queue is not empty during cycle QS 2 , and the data value PQ 4  is provided as an output value. An internal counter needs to keep track of this read operation for the present queue, and at the same time provide count values for new queue flag calculation. This problem has been solved by using a pipeline scheme at the output terminals of the write counter and the read counter, and by specifying a forced-word-fall-through (FWFT) restriction on the data output during a queue switch. Thus, if the present queue is not empty, the last data before queue switch will be output in cycle QS 2  even though there is no active external read signal. This enables the read counter to predict what happens during cycle QS 2 , instead of relying on what actually occurs during cycle QS 2 . However, this scheme undesirably requires the user to process data during cycle QS 2 . 
     It would therefore be desirable to have a multi-queue FIFO memory system that is capable of determining exactly how many read operations have been performed on the present queue, without any prediction or forced data out. 
     SUMMARY 
     Accordingly, the present invention provides a multi-queue memory device that includes a read queue register file that stores read count pointers associated with each queue of the multi-queue device. For example, a device having  128  queues will have  128  corresponding read count pointers. To read data from one of the queues (i.e., a present queue), the read count pointer associated with that queue (i.e., the present queue read point counter) is retrieved from the read queue register file. Read operations are performed from the present queue, beginning at the location identified by the present queue read count pointer. 
     Each time that a read operation is performed from the present queue, the present queue read count pointer is incremented by a first read counter. The present queue read count pointer is routed from the first read counter to read flag logic. In response, the read flag logic generates an empty flag which identifies the “empty” status of the present queue. 
     A queue switch from the present queue to a new queue can be indicated by activating a read address enable signal and providing an address associated with the new queue. When a queue switch is indicated, the read count pointer associated with the new queue (i.e., the new queue read count pointer) is retrieved from the read queue register file. A selector circuit routes both the present queue read count pointer and the new queue read count pointer to the read flag logic. 
     The read flag logic continues to generate an empty flag that identifies the empty status of the present queue for a predetermined number of cycles after the queue switch is indicated. Data can be read from the present queue during these “transition” cycles. During these transition cycles, the read flag logic also determines the empty status of the new queue in response to the new queue read count pointer. At the end of the transition cycles, the read flag logic provides an empty flag that identifies the empty status of the new queue. At this time, read operations are performed from the new queue (as long as the new queue is not empty), beginning at the location identified by the new queue read count pointer. Also, at the end of the transition cycles, the present queue read count pointer is written back to the read queue file register. 
     The new queue read count pointer is subsequently loaded into a second read counter. Each time that a read operation is performed from the new queue, the new queue read count pointer is incremented by the second read counter. The new queue read count pointer is routed from the second read counter to the read flag logic, such that the read flag logic can continue generating an empty flag that identifies the empty status of the new queue. 
     Because each read operation to the present queue and new queue is accurately counted by the first read counter and the second read counter, the present queue read count pointer and new queue read count pointer are accurate, without requiring a pipeline scheme or a forced-word-fall-through (FWFT) restriction on the data output during a queue switch. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a waveform diagram illustrating a typical queue switch performed during a read operation. 
         FIG. 2  is a block diagram of a multi-queue flow-control device in accordance with one embodiment of the present invention. 
         FIG. 3  is a block diagram of a read flag counter register (FCR) file having multiple read counters in accordance with one embodiment of the present invention. 
         FIGS. 4 ,  5 ,  6 ,  7  are waveform diagrams illustrating the operation of the read FCR file of  FIG. 3  in accordance with various embodiments of the present invention. 
         FIG. 8  is a block diagram of a write flag counter register (FCR) file in accordance with one embodiment of the present invention. 
         FIGS. 9 ,  10 ,  11 ,  12  are waveform diagrams illustrating the operation of the write FCR file of  FIG. 8  in accordance with various embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention includes a multi-queue flow-control device, which is implemented on a single chip. The multi-queue device can be configured to implement between 1 and 128 discrete FIFO queues. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 128. The user can also independently select the individual queue depths. 
     All queues within the device have a common data input bus (write port), and a common data output bus (read port). Data written to the write port is directed to a respective queue via an internal de-multiplexer, which is addressed by a user. Data read from the read port is accessed from a respective queue via an internal multiplexer, addressed by the user. Data writes and reads can be performed at high speeds (up to 200 MHz, with access times of 3.6 ns in accordance with one embodiment of the present invention). Data write and read operations are totally independent of each other. Thus, a queue may be selected on the write port, and a different queue may be selected on the read port. Alternately, read and write operations may be selected on the same queue simultaneously. 
     The device provides a Full Flag (FF#) and an Empty Flag (EF#) that identify the status of the queues selected for write and read operations, respectively. The device also provides a Programmable Almost Full Flag (PAF#) and a Programmable Almost Empty Flag (PAE#) that identify the status of the queues selected for write and read operations, respectively. The positions of the PAF# and PAE# flags are programmable by the user. The flags for queue N are specified by the flag name, followed by N (e.g., PAF#_N). 
       FIG. 2  is a block diagram of a multi-queue flow-control device  100  in accordance with one embodiment of the present invention. Device  100  includes dual-port memory  101 , write port (de-multiplexer)  110 , write control logic  111 , active write queue flag circuit  114 , output multiplexer  120 , read control logic  121 , active read queue flag circuit  124 , output register  130  and output buffer  131 . In the described embodiment, dual-port memory is a 4.7 Mbit memory, which can be logically divided into up to 128 FIFO queues, each having a minimum capacity of 9 k bits. 
     In general, write control logic  111  controls write accesses to the various queues in dual-port memory  101 . More specifically, write control logic  111  provides the required control/address signals to input de-multiplexer  110  and dual-port memory  101  in response to a write chip select signal WCS#, a write enable signal WEN#, a write clock signal WCLK, a write address signal WRADD[7:0] and a write address enable signal WADEN. As described in more detail below, write control logic  111  also provides control signals to active write queue flag circuit  114 , active read queue flag circuit  124  and read control logic  121 . 
     Similarly, read control logic  121  controls read accesses from the various queues in dual-port memory  101 . More specifically, read control logic  121  provides the required control/address signals to output multiplexer  120  and dual-port memory  101  in response to a read chip select signal RCS#, a read enable signal REN#, a read clock signal RCLK, a read address signal RDADD[7:0] and a read address enable signal RADEN. As described in more detail below, read control logic  121  also provides control signals to active write queue flag circuit  114 , active read queue flag circuit  124  and write control logic  111 . 
     As described in more detail below, active write queue flag circuit  114  generates a full flag FF# (input ready flag IR#) and programmable almost full flag PAF# in response to the write address WRADD[7:0] and the control signals received by write control logic  111  and read control logic  121 . Also, as described in more detail below, active read queue flag circuit  124  generates an empty flag EF# (output ready flag OR#) and programmable almost empty flag PAE# in response to the read address RDADD[7:0] and the control signals received by write control logic  111  and read control logic  121 . 
     Read operations to multi-queue device  100  will now be described. In general, when a queue within dual-port memory  101  is selected for a read operation, the next word in the selected queue automatically falls through output multiplexer  120  to the output register  130 . All subsequent words from the selected queue require an enabled read cycle in order to be routed to the output register  130 . Data cannot be read from the selected queue if the queue is empty. The active read queue flag circuit  124  provides an active-low empty flag/output ready signal (EF#/OR#) indicating when the data read from the selected queue is valid. If the user switches to a queue that is empty, the last word read from the previous queue will remain in the output register  130 . As described in more detail below, dual-port memory  101  exhibits a four-cycle latency when switching from one queue to another queue (i.e., during a queue switch). 
       FIG. 3  is a block diagram of a read flag counter register (FCR) system  200 , which is located in read control logic block  121  and active read queue flag circuit  124 , in accordance with one embodiment of the present invention. Read FCR system  200  includes read FCR file  201 , register  202 , multiplexers  211 - 214 , adder circuits  220 - 221 , read counters  250 - 251  and read flag logic  260 . 
     Read FCR file  201  includes  128  entries, one for each possible queue in multi-queue device  100 . Each entry stores a read count pointer for a corresponding queue. Each entry of read FCR file  201  is coupled to register  202  via a selection circuit (not shown). As described in more detail below, register  202  latches a read count pointer retrieved from read FCR file  201  at the start of a queue switch (during cycle QS- 1 ). The read count pointer stored in register  202  is applied to the “1” input terminal of multiplexer  211  and the “0” input terminal of multiplexer  212 . 
     The output terminal of multiplexer  211  is coupled to the “0” input terminals of multiplexers  213  and  214  and to adder  220 . Similarly, the output terminal of multiplexer  212  is coupled to the “1” input terminals of multiplexers  213  and  214  and to adder  221 . Adders  220  and  221  each add one to the read count values provided by multiplexers  211  and  212 , respectively. Adders  220  and  221  apply the incremented read count values to read counters  250  and  251 , respectively. Read counters  250  and  251  latch the incremented read count values on rising edges of the RCLKy and RCLKx read clock signals, respectively. Read counters  250  and  251  apply output read count values RCNTy and RCNTx, respectively, to the “0” and “1” input terminals of multiplexers  211  and  212 , respectively. In the described embodiment, multiplexers  211  and  212  are controlled by the same control signal RMUX 0 , although this is not necessary. Multiplexers  213  and  214  are controlled by RMUX 1  and RMUX 2  signals, respectively. Multiplexer  213  provides an output signal RCNT 1 , and multiplexer  214  provides an output signal RCNT 2 , which are used to derive the empty flag, EF# and the programmable almost empty flag, PAE#, respectively. The RCNT 2  signal is also routed back to read FCR file  201 , such that the read FCR file is updated to store changes in the RCNT 2  signal during each read cycle. 
       FIG. 4  is a waveform diagram illustrating the operation of read FCR system  200  in accordance with one embodiment of the present invention. 
     The read clock signal RCLK, read enable signal REN#, read address enable signal RADEN and read address signal RDADD[7:0] are applied to read control logic  121  ( FIG. 2 ). Relevant cycles of the RCLK signal are labeled QS- 1 , QS 0 , QS 1 , QS 2  and QS 3 . Prior to read cycle QS- 1 , data is being read from a first queue, which is hereinafter referred to as the present queue (PQ). At this time, read FCR system  200  is configured as follows. The read clock signal RCLK is routed as the read clock signal RCLKy to read counter  250 . Read counter  250  maintains a read count value (RCNTy) associated with the present queue PQ. The RMUX 0  signal has a logic “0” value, such that multiplexer  211  routes the RCNTy value provided by read counter  250  to multiplexers  213  and  214 . The RMUX 1  and RMUX 2  signals both have a logic “0” value, such that multiplexers  213  and  214  route the RCNTy value as the RCNT 1  and RCNT 2  signals, respectively, to read flag logic  260 . At this time, read flag logic  260  generates the empty flag EF# and programmable almost empty flag PAE# in response to the read count value RCNTy associated with the present queue PQ. More specifically, read flag logic  260  generates the empty flag EF# in response to the RCNT 1  signal and a write pointer value WCNT_EF provided by a write FCR system  300  ( FIG. 8 ). Similarly, read flag logic  260  generates the programmable almost empty flag PAE# in response to the RCNT 2  signal and another write pointer value WCNT_PAE provided by the write FCR file. In general, WCNT_EF is the write count pointer of the same queue represented by the RCNT 1  read count pointer, and WCNT_PAE is the write count pointer of the same queue represented by the RCNT 2  read count pointer. The operation of multiplexers  315  and  316  is described in more detail in “Method to Optimize Interfaces Between Driver and Receiver Circuits in Datapaths” by Prashant Shamarao, Jason Z. Mo and Jianghui Su, U.S. Provisional Patent Application Ser. No. 60/555,716, filed Mar. 23, 2004, which is hereby incorporated by reference. 
     Each time that a read operation is performed from the present queue PQ, the read clock signal RCLKy is asserted, thereby causing read counter  250  to latch the incremented read count value (i.e., RCNTy plus 1) provided by adder circuit  220 . Read flag logic  260  then uses the incremented RCNTy signal to generate the EF# and PAE# flags associated with the present queue PQ. In the present example, the EF# and PAE# flags associated with the present queue PQ remain de-activated high, thereby indicating that the present queue is neither empty nor almost empty. 
     Prior to the start of read cycle QS- 1 , the read address enable signal RADEN transitions to a logic “1” state, thereby indicating that a queue switch (QS) will be performed. That is, the read operations from the present queue PQ will be stopped, and read operations will be performed from a new queue (NQ) in dual port memory  101 . The address of the new queue NQ is identified by the read address signal RDADD[7:0]. The RADEN and RDADD[7:0] signals are detected at the beginning of read cycle QS- 1  (at the rising edge of the RCLK signal). 
     In response to the detected RADEN signal, read FCR file  201  retrieves the read count pointer from the register corresponding to the queue identified by the RDADD[7:0] signal. For example, if the read address signal RDADD[7:0] identifies queue  2 , then read FCR file  201  provides the read count pointer of queue  2  to register  202 . The write FCR system  300  ( FIG. 8 ) also retrieves the write count pointer associated with the addressed queue (e.g., queue  2 ) on port “d” at this time. Data is read from the present queue and the read count value RCNTy is incremented during read cycle QS- 1 . 
     By the start of the next read cycle QS 0 , the read count pointer retrieved from read FCR file  201  has been loaded into register  202 . At this time, multiplexer  212  routes the read count pointer stored in register  202  to the logic “1” input terminals of multiplexers  213  and  214 , and to the input terminal of adder circuit  221 . Also at the start of read cycle QS 0 , the RMUX 1  signal transitions to a logic “1” value, thereby causing multiplexer  213  to route the newly retrieved read point counter associated with the new queue NQ as the RCNT 1  signal. Also, at the start of read cycle QS 0 , the write FCR system  300  provides the newly retrieved write point counter associated with the new queue NQ as the WCNT_EF signal. In response, read flag logic  260  starts to generate a new empty flag EF# in response to the retrieved read and write count pointers associated with the new queue NQ. Data (DOUT) is still read from the present queue (and the read count value RCNTy is incremented) during read cycle QS 0 . Note that the RCNTy value associated with the present queue PQ signal (and provided as the RCNT 2  signal) and a write count pointer associated with the present queue (WCNT_PAE) are still used to generate the programmable almost empty PAE# flag during the read cycle QS 0 . 
     During cycles QS 1  and QS 2 , the read enable signal REN# remains activated low, thereby enabling data values to be read from the present queue PQ during cycles QS 1  and QS 2 , and enabling read clock counter  250  to increment the RCNTy value at the rising edges of read cycles QS 1  and QS 2 . As described in more detail below, the read enable signal REN# can be de-activated high prior to the beginning of a read cycle, thereby preventing data values from being read from the queue during the read cycle. In this case, the high REN# signal prevents the read clock signal RCLKy from clocking read counter  250 , such that the read count value RCNTy is not incremented during the read cycle. 
     The last data value to be read from the present queue PQ is provided during read cycle QS 2 . The read count value RCNTy is routed through multiplexers  211  and  214  to read FCR file  201  as the RCNT 2  signal. During read cycle QS 2 , the read count value RCNTy is stored as the read count pointer associated with the present queue PQ in read FCR file  201 . 
     At the end of read cycle QS 2 , the read count value RCNTy provided by read counter  250  is representative of the exact number of read operations that have been performed to the present queue PQ, without any prediction, pipelining or forced data out. Consequently, the next time the present queue is accessed, the read count pointer retrieved from read FCR file  201  accurately represents the read address of this queue. 
     At the start of read cycle QS 2 , read flag logic  260  provides an empty flag EF# representative of the status of the new queue NQ. As described above, this empty flag EF# is provided in response to the read count pointer previously stored in register  202  during read cycle QS 0  and provided as the RCNT 1  signal. 
     Note that during cycle QS 1 , read flag logic  260  decodes the address of the new queue NQ, and retrieves a previously stored programmable almost empty flag PAE#, which identifies the almost empty status of the new queue NQ. During cycle QS 2 , read flag logic  260  provides the PAE# flag associated with the new queue as the active PAE# flag. The active PAE# flag associated with the new queue is then updated during cycle QS 3  (and during subsequent cycles). This process provides an accurate result, because the earliest that a read operation can be performed to the new queue is during cycle QS 3 . The logic used to generate the programmable almost empty flag is described in more detail in U.S. patent application Ser. No. 11/040,804, now U.S. Pat. No. 7,257,687, “Synchronization of Active Flag and Status Bus Flags in a Multi-Queue First-In First-Out Memory System”, by Mario Au, Jason Z. Mo and Cheng-Han Wu, which is hereby incorporated by reference. 
     Also during read cycle QS 2 , a write count pointer associated with the new queue is retrieved on port “f” of the write FCR system  300 . 
     During read cycle QS 3 , data is read from the new queue NQ. More specifically, data is read from the address of the new queue NQ identified by the read count pointer stored in register  202 . At the start of read cycle QS 3 , the read clock signal RCLK is routed to read counter  251  as the read clock signal RCLKx. At the rising edge of read cycle QS 3 , read counter  251  latches an incremented read count value (RCNTx plus 1) provided by adder circuit  221 . During read cycle QS 3 , the RMUX 0  signal is controlled to have a logic “1” state, thereby causing multiplexer  212  to route the incremented read count value RCNTx from read counter  251  to multiplexers  213  and  214 . The multiplexer control signal RMUX 2  is also controlled to have a logic “1” value, thereby causing multiplexer  214  to route the incremented read count value RCNTx associated with the new queue to read flag logic  260 . The write count pointer associated with the new queue is retrieved on port “f” of the write FCR system  300  and provided to read flag logic  260  as the write count pointer WCNT_PAE during cycle QS 3 . Read flag logic  260  then begins to generate the programmable almost empty flag PAE# in response to the new read count pointer RCNT 2  and the new write count pointer WCNT_PAE. 
       FIG. 5  is a waveform diagram illustrating the operation of read FCR system  200  in accordance with another embodiment of the present invention. The embodiment of  FIG. 5  is similar to the embodiment of  FIG. 4 , with differences noted below. In the embodiment of  FIG. 5 , the last data value in the present queue PQ is read during read cycle QS 0 . Because the present queue becomes empty during read cycle QS 0 , the empty flag EF# is activated low during this read cycle. Note that the programmable almost empty flag PAE# was activated low in previous read cycles. The logic low empty flag EF# prevents additional data values from being read from the present queue, and prevents the read count value RCNTy from being incremented. This is accomplished by basic FIFO read logic, which feeds back the status of the empty flag EF# to prevent read operations from occurring (i.e., an internal read is only activated if the empty flag EF# is high and the read enable signal REN# is low). 
     The new queue NQ is neither empty nor almost empty in the example of  FIG. 5 . Consequently, the empty flag EF# and programmable almost empty flag PAE# are activated high during read cycle QS 2 , thereby indicating the non-empty status of the new queue NQ. A data value is read from the new queue NQ during read cycle QS 3  in the manner described above in connection with  FIG. 4 . 
       FIG. 6  is a waveform diagram illustrating the operation of read FCR system  200  in accordance with another embodiment of the present invention. The embodiment of  FIG. 6  is similar to the embodiment of  FIG. 4 , with differences noted below. In the embodiment of  FIG. 6 , data values are read from the present queue PQ through read cycle QS 2  in the manner described above in connection with  FIG. 4 . However, in the example of  FIG. 6 , the new queue is empty during cycle QS 3 . Because the new queue is empty, the empty flag EF# and the programmable almost empty flag PAE# are activated low during read cycle QS 2 . The logic low empty flag EF# prevents data values from being read from the new queue, and prevents the read count value RCNTx from being incremented. 
       FIG. 7  is a waveform diagram illustrating the operation of read FCR system  200  in accordance with another embodiment of the present invention. The embodiment of  FIG. 7  is similar to the embodiment of  FIG. 4 , with differences noted below. In the embodiment of  FIG. 7 , the read enable signal REN# is de-activated high prior to the rising edge of read cycle QS 1 . The logic high read enable signal REN# prevents a new data value from being read from the present queue during read cycle QS 1 , and prevents the read count value RCNTy from being incremented during read cycle QS 1 . 
     In the foregoing manner, a read queue switch can be implemented in a seamless and flexible manner, without requiring forced data fall through or pipelining the output data. 
       FIG. 8  is a block diagram of a write flag counter register (FCR) system  300 , which is located in write control logic block  111  and active queue flag circuit  114 , in accordance with one embodiment of the present invention. Write FCR system  300  includes write FCR file  301 , register  302 , multiplexers  311 - 314 , adder circuits  320 - 321 , write counters  350 - 351 , and write flag logic  360 . Write FCR system  300  is configured in the same manner as read FCR system  200  ( FIG. 3 ). 
     Write FCR file  301  includes  128  entries, one for each possible queue in device  100 . Each entry stores a write count pointer for a corresponding queue. Each entry of write FCR file  301  is coupled to register  302  via a selection circuit (not shown). As described in more detail below, register  302  latches a new write count pointer retrieved from write FCR file  301  at the start of a queue switch (during cycle QS- 1 ). The write count pointer stored in register  302  is applied to the “1” input terminal of multiplexer  311  and the “0” input terminal of multiplexer  312 . 
     The output terminals of multiplexers  311  and  312  are coupled to the “0” input terminals of multiplexers  313  and  314 , respectively, and to adders  320  and  321 , respectively. Adders  320  and  321  each add one to the write count values provided by multiplexers  311  and  312 , respectively. Adders  320  and  321  apply the incremented write count values to write counters  350  and  351 , respectively. Write counters  350  and  351  latch the incremented write count values on rising edges of the WCLKy and WCLKx write clock signals, respectively. Write counters  350  and  351  apply output write count values WCNTy and WCNTx, respectively, to the “0” and “1” input terminals of multiplexers  311  and  312 , respectively. In the described embodiment, multiplexers  311  and  312  are controlled by the same control signal WMUX 0 , although this is not necessary. Multiplexers  313  and  314  are controlled by WMUX 1  and WMUX 2  signals, respectively. Multiplexer  313  provides an output signal WCNT 1 , and multiplexer  314  provides an output signal WCNT 2 , which are used to derive the full flag FF# and the programmable almost full flag PAF#, respectively. The WCNT 2  signal is also routed back to write FCR file  301  as a write count signal, such that the write FCR file  301  is updated to store changes in the WCNT 2  signal during each write cycle. 
       FIG. 9  is a waveform diagram illustrating the operation of write FCR system  300  in accordance with one embodiment of the present invention. 
     The write clock signal WCLK, write enable signal WEN#, write address enable signal WADEN and write address signal WRADD[7:0] are applied to write control logic  111  ( FIG. 2 ). Relevant cycles of the WCLK signal are labeled QS- 1 , QS 0 , QS 1 , QS 2  and QS 3 . Prior to write cycle QS- 1 , data is being written to a first queue in dual-port memory  101 , which is hereinafter referred to as the present queue (PQ). At this time, write FCR system  300  is configured as follows. The write clock signal WCLK is routed as the write clock signal WCLKy to write counter  350 . Write counter  350  maintains a write count value (WCNTy) associated with the present queue PQ. The WMUX 0  signal has a logic “0” state, such that multiplexer  311  routes the WCNTy value provided by write counter  350  to multiplexers  313  and  314 . The WMUX 1  and WMUX 2  signals both have a logic “0” value, thereby routing the WCNTy value as the WCNT 1  and WCNT 2  signals. Write flag logic  360  generates the full flag FF# and programmable almost full flag PAF# in response to the write count value WCNTy associated with the present queue PQ. 
     Each time that a write operation is performed to the present queue PQ, the write clock signal WCLKy is asserted, thereby causing write counter  350  to latch the incremented write count value (i.e., WCNTy plus 1) provided by adder circuit  320 . The incremented WCNTy signal is then used to generate the FF# and PAF# flags associated with the present queue PQ. In the present example, the FF# and PAF# flags associated with the present queue PQ remain de-activated high, thereby indicating that the present queue is neither full nor almost full. 
     Prior to the start of write cycle QS- 1 , the write address enable signal WADEN transitions to a logic “1” state, thereby indicating that a queue switch (QS) will be performed. That is, the write operations to the present queue PQ will be stopped, and write operations will be performed to a new queue (NQ) in dual port memory  101 . The address of the new queue NQ is identified by the write address signal WRADD[7:0]. The WADEN and WRADD[7:0] signals are detected at the beginning of write cycle QS- 1  (at the rising edge of the WCLK signal). 
     In response to the detected WADEN signal, write FCR file  301  retrieves the write count value from the register corresponding to the queue identified by the WRADD[7:0] signal. For example, if the write address signal WRADD[7:0] identifies queue  127 , then write FCR file  301  provides the write count value of queue  127 . The read FCR system  200  ( FIG. 3 ) also retrieves the read count pointer associated with the addressed queue (e.g., queue  127 ) on port “a” at this time. Data is written to the present queue and the write count value WCNTy is incremented during write cycle QS- 1 . 
     By the start of the next write cycle QS 0 , the write count pointer retrieved from write FCR file  301  has been loaded into register  302 . In response to the logic “0” WMUX 0  signal, multiplexer  312  routes the write count pointer stored in register  302  to the logic “1” input terminals of multiplexers  313  and  314 , and to the input terminal of adder circuit  321 . Also at the start of the next write cycle QS 0 , the WMUX 1  signal transitions to a logic “1” value, thereby routing the newly retrieved write count pointer (WCNTx) associated with the new queue NQ as the WCNT 1  signal. Also, at the start of read cycle QS 0 , the read FCR system  200  provides the newly retrieved read point counter associated with the new queue NQ as the RCNT_FF signal. In response, write flag logic  360  starts to generate a new full flag FF# in response to the retrieved read and write count pointers associated with the new queue NQ. Data (DIN) is written to the present queue (and the write count value WCNTy is incremented) during the QS 0  write cycle. Note that the WCNTy value associated with the present queue PQ signal (and provided as the WCNT 2  signal) and a write count pointer associated with the present queue (RCNT_PAF) are still used to generate the programmable almost full PAF# flag during the read cycle QS 0 . 
     During cycles QS 1  and QS 2 , the write enable signal WEN# remains activated low, thereby enabling data values to be written to the present queue PQ during cycles QS 1  and QS 2 , and enabling write clock counter  350  to increment the WCNTy value at the rising edges of write cycles QS 1  and QS 2 . As described in more detail below, the write enable signal WEN# can be de-activated high prior to the beginning of a write cycle, thereby preventing data values from being written to the queue during the write cycle. In this case, the high WEN# signal prevents the write clock signal WCLKy from clocking write counter  350 , such that the write count value WCNTy is not incremented during the write cycle. 
     The last data value to be written to the present queue PQ is written during write cycle QS 2 . The write count value WCNTy is routed through multiplexers  311  and  314  as the write count value WCNT 2  to write FCR file  301 . During write cycle QS 2 , the write count value WCNTy is stored as the write count pointer associated with the present queue PQ in write FCR file  301 . 
     At the end of write cycle QS 2 , the write count value WCNTy provided by write counter  350  is representative of the exact number of write operations that have been performed to the present queue PQ, without any prediction or pipelining. Consequently, the next time the present queue is written, the write count pointer retrieved from write FCR file  301  accurately represents the last write address for this queue. 
     At the start of write cycle QS 2 , write flag logic  360  provides a full flag FF# representative of the status of the new queue NQ. As described above, this full flag FF# is provided in response to the write count pointer previously stored in register  302  during read cycle QS 0  and provided as the WCNT 1  signal. 
     Note that during cycle QS 1 , write flag logic  360  decodes the address of the new queue NQ, and retrieves a previously stored programmable almost full flag PAF#, which identifies the almost full status of the new queue NQ. During cycle QS 2 , write flag logic  360  provides the PAF# flag associated with the new queue as the active PAF# flag. The active PAF# flag associated with the new queue is then updated during cycle QS 3  (and during subsequent cycles). This process provides an accurate result, because the earliest that a write operation can be performed to the new queue is during cycle QS 3 . The logic used to generate the programmable almost full flag is described in more detail in U.S. patent application Ser. No. 11/040,804, now U.S. Pat. No. 7,257,687, “Synchronization of Active Flag and Status Bus Flags in a Multi-Queue First-In First-Out Memory System”, by Mario Au, Jason Z. Mo and Cheng-Han Wu, which is hereby incorporated by reference. 
     Also during write cycle QS 2 , a read count pointer associated with the new queue is retrieved on port “c” of the read FCR system  200 . 
     During write cycle QS 3 , data is written to the new queue NQ. More specifically, data is written to the address of the new queue NQ identified by the write count pointer stored in register  302 . At the start of write cycle QS 3 , the write clock signal WCLK is routed to write counter  351  as the write clock signal WCLKx. At the rising edge of write cycle QS 3 , write counter  351  latches an incremented write count value (WCNTx plus 1) provided by adder circuit  321 . During write cycle QS 3 , the WMUX 0  signal is controlled to have a logic “1” value, thereby causing multiplexer  312  to route the incremented write count value WCNTx from write counter  351  to multiplexers  313  and  314 . The multiplexer control signal WMUX 2  is controlled to have a logic “1” value, thereby routing the incremented write count value WCNTx to write flag logic  360 . The read count pointer associated with the new queue is retrieved on port “c” of the read FCR system  200  and provided to write flag logic  360  as the read count pointer RCNT_PAF during cycle QS 3 . Write flag logic  360  then begins to generate the programmable almost full flag PAF# in response to the new write count pointer RCNT 2  and the new read count pointer RCNT_PAF. 
       FIG. 10  is a waveform diagram illustrating the operation of write FCR system  300  in accordance with another embodiment of the present invention. The embodiment of  FIG. 10  is similar to the embodiment of  FIG. 9 , with differences noted below. In the embodiment of  FIG. 10 , the last data value written to the present queue PQ is written during write cycle QS 0 . Because the present queue is full during write cycle QS 0 , the full flag FF# is activated low during this write cycle. Note that the programmable almost full flag PAF# was activated low in previous write cycles. The logic low full flag FF# prevents additional data values from being written to the present queue, and prevents the write count value WCNTy from being incremented. This is accomplished by basic FIFO read logic, which feeds back the status of the full flag FF# to prevent write operations from occurring (i.e., an internal write is only activated if the full flag FF# is high and the write enable signal WEN# is low). 
     The new queue NQ is neither full nor almost full in the example of  FIG. 10 . Consequently, the full flag FF# and programmable almost full flag PAF# are de-activated high during write cycle QS 2 , thereby indicating the non-full status of the new queue NQ. A data value is written to the new queue NQ during write cycle QS 3  in the manner described above in connection with  FIG. 9 . 
       FIG. 11  is a waveform diagram illustrating the operation of write FCR system  300  in accordance with another embodiment of the present invention. The embodiment of  FIG. 11  is similar to the embodiment of  FIG. 9 , with differences noted below. In the embodiment of  FIG. 11 , data values are written to the present queue PQ through write cycle QS 2  in the manner described above in connection with  FIG. 9 . However, in the example of  FIG. 11 , the new queue is full during cycle QS 3 . Because the new queue is full, the full flag FF# and the programmable almost full flag PAF# are activated low during write cycle QS 2 . The logic low full flag FF# prevents data values from being written to the new queue, and prevents the write count value WCNTx from being incremented. 
       FIG. 12  is a waveform diagram illustrating the operation of write FCR system  300  in accordance with another embodiment of the present invention. The embodiment of  FIG. 12  is similar to the embodiment of  FIG. 9 , with differences noted below. In the embodiment of  FIG. 12 , the write enable signal WEN# is de-activated high prior to the rising edge of write cycle QS 1 . The logic low write enable signal WEN# prevents a new data value from being written to the present queue during write cycle QS 1 , and prevents the write count value WCNTy from being incremented during write cycle QS 1 . 
     In the foregoing manner, a write queue switch can be implemented in a seamless and flexible manner, without requiring forced data fall through or-pipelining the output data. 
     Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. Thus, the present invention is only intended to be limited by the following claims.