Abstract:
A slicer can receive a communication signal having a level or amplitude that is between two discrete levels of a multilevel digital communication scheme. The slicer can compare the communication signal to a plurality of references such that multiple comparisons proceed essentially in parallel. A summation node can add the results of the comparisons to provide an output signal set to one of the discrete levels. The slicer can process the communication signal and provide the output signal on a symbol-by-symbol basis. A decision feedback equalizer (“DFE”) can comprise the slicer. A feedback circuit of the DFE can delay and scale the output signal and apply the delayed and scaled signal to the communication signal to reduce intersymbol interference (“ISI”).

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority to U.S. Provisional Patent Application Ser. No. 60/531,901, entitled “Slicer Apparatus for High-Speed Multilevel Decision Feedback Equalization,” and filed Dec. 22, 2003. The contents of U.S. Provisional Patent Application Ser. No. 60/531,901 are hereby incorporated by reference. 
     This application is related to U.S. Pat. No. 6,816,101, assigned Nonprovisional patent application Ser. No. 10/383,703, entitled “High-Speed Analog-To-Digital Converter Using a Unique Gray Code,” and filed on Mar. 7, 2003. The contents of U.S. Pat. No. 6,816,101 are hereby incorporated by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to the field of data communications, and more specifically to processing a multilevel communication signal to reduce bit errors by suppressing interference, such as intersymbol interference, that occurs during signal propagation over a physical medium. 
     BACKGROUND 
     Digital communications involves conveying digital data by generating, sending, receiving, and processing analog waveforms. A transmitter accepts a sequence of digitally formatted data and converts the sequence into an analog waveform. Each time interval of this waveform carries or is encoded with an element of digital information referred to as a symbol. A one-to-one correspondence typically exists between each discrete waveform state and each symbol. That is, for the set of symbols that a communication system can convey, each symbol matches a specific signal level from two or more signal level possibilities. The transmitter outputs the waveform onto a medium or channel. The waveform transmits or propagates over the medium or channel to a receiver, which decodes or extracts the original data from the received waveform. 
     The transmitter generating the waveform sets the signal amplitude, phase, and/or frequency of the output waveform to one of N discrete values, levels, or states during the time interval to represent digital information. Binary signaling uses N=2 levels, with the levels corresponding to or representing “0” and “1”. Multilevel signaling schemes can use more than two levels, i.e. N≧2, with the levels being “0”, 1, . . . , “N−1”. The transmitter transmits a signal level or symbol during a predetermined time period or interval called the symbol period and denoted as T 0 . Thus, the transmitter conveys digital data to the receiver as a sequence of symbols, transmitting one symbol per symbol period. 
     On the opposite end of the communication link from the transmitter, the receiver decodes the digital information from the communicated analog waveform. That is, for each symbol, the transmitter determines or detects which of the levels was transmitted from the N possibilities. Thus, the receiver processes the incoming waveform to assign a symbol to each symbol period. If the symbol that the receiver assigns to the waveform is the same symbol that the transmitter used as the basis for modulating or generating the waveform, then the communication of that symbol succeeded, and that data element transmitted without error. 
     However, the transmission of data in a physical medium or communication channel is not always error free. The communicated signal can degrade during propagation resulting in data errors. In particular, the transmission channel or transmission medium can distort the waveforms via dispersion or other phenomena resulting in what is known as intersymbol interference (“ISI”). Noise or interference from external sources can also corrupt the signal during transmission, for example exacerbating ISI. 
     The term “intersymbol interference” or “ISI,” as used herein, refers to signal interference stemming from the transfer of signal or waveform energy from one symbol period to another symbol period. ISI can appear as slight movements of a transmission signal in time or phase, also known as jitter or timing distortion, that may cause synchronization problems. ISI can result from temporal spreading and consequent overlapping of the pulses or waveform segments that occupy each symbol period. The severity of ISI can compromise the integrity of the received signal to the extent that the receiver does not reliably distinguish between the symbols in two adjacent symbol periods or otherwise misidentifies a symbol. 
     Signal distortion, as well as noise related to ISI and other interference sources, can lead to decoding errors. In some limited circumstances, conventional equalization techniques are available to reduce the incidence of data errors that ISI causes. The term “equalization,” as used herein, refers to manipulating a communication signal in a manner that counteracts or otherwise compensates for signal changes that occur during transmission on a communication channel or medium. 
     Equalization can be viewed as an intentional “distortion,” applied at either the receiving or the transmitting end of communication link, that counteracts detrimental distortion introduced by the channel. Unfortunately, many conventional equalization techniques (linear equalizers in particular) tend to exacerbate the effect of the noise. Thus, conventional equalizers are often limited in the magnitude of equalization that they can apply. Beyond a certain level of applied equalization, such equalizers can induce or amplify noise, thereby degrading communication integrity. An appropriately-set equalizer based on conventional technology is usually balanced to yield a favorable tradeoff between the amount of ISI removed and the amount of noise amplified. 
     Decision feedback equalization is a known equalization method that can be applied at the receive-end of a communications system. A decision feedback equalizer (“DFE”) is a nonlinear equalizer intended to remove ISI without exacerbating the noise, thereby permitting a higher level of ISI cancellation and an improved equalized signal. The term “decision feedback equalizer” or “DFE,” as used herein, refers to a device that suppresses ISI in a first time interval of a communication signal by generating a correction signal based on processing a second time interval of the communication signal and applying the correction signal to the first time interval of the communication signal. 
       FIG. 1  illustrates a functional block diagram of an exemplary conventional DFE  110 . The DFE  110  takes as input the communicated signal v rx    120  and applies a corrective signal v fb    130  to suppress or remove ISI. The DFE  110  generates this corrective signal  130  via an internal feedback mechanism based on an arrangement of delay stages  170  and attenuators or amplifiers  180 . 
     The compensated signal v comp    140  (i.e. received signal  120  plus the applied corrective signal  130 ) is quantized by the slicer  150  to one of the candidate N signal levels. Specifically, the slicer  150  takes as input a (potentially distorted) multilevel signal  140  and outputs a reconstructed or regenerated multilevel signal  160 . The term “slicer,” as used herein, refers to a device that processes an incoming analog signal and outputs a signal having a discrete characteristic that corresponds to at least one element of digital data. For example, a slicer  150  can slice, clip, or set the amplitude of a pulse to provide a resulting signal that has a specified amplitude. 
     For each symbol period, the slicer  150  sets or forces the signal level of its output  160  to the discrete level or state of the nearest valid symbol of the multilevel signal, thereby removing minor signal degradation. In other words, for each symbol period, the slicer  150  evaluates the incoming signal  140  and manipulates it to provide a discrete signal state that corresponds to one of the symbol possibilities. If the signal degradation is within a range of severities that the conventional DFE  110  can accommodate, the resulting symbol value output by the slicer  150  is the same as the symbol that was transmitted. In other words, within a limited level of signal degradation, the conventional DFE  110  removes noise or signal ambiguity to accurately reconstruct the signal output by the transmitter, thereby providing data transmission without error. 
     Since the slicer output v out    160  should nominally have the same level as the transmitted signal, the slicer output  160  can be delayed and scaled to model (and subsequently remove) the ISI that this symbol imposes on symbols yet to be received in the communicated waveform. That is, the conventional DFE  110  processes the waveform element in each symbol period based in part on the processing of earlier-received waveform elements. 
     Referring now to  FIGS. 1 and 2 , the illustrated conventional DFE  110  provides a plurality of feedback loops  210 , each providing a delay δ i  (small letter “delta”) and an amplification gain a i . Referring specifically to the feedback loop  210  identified in  FIG. 2 , the delay element  170   a  delays the quantized signal  160  by an amount of time δ 1  such that the cumulative delay through (i) the slicer  150 , (ii) the delay element  170   a , (iii) the adjustable amplifier  180   a , and (iv) the summation nodes  190   a  and  190   b  is equal to the symbol period T 0 . The delay along this path  210  will be referred to as the primary loop delay Δ (capital letter “delta”). Through appropriate setting of the gain a 1  on the adjustable amplifier  180   a , the ISI from the immediately preceding symbol can be removed when Δ=T 0 . Referring now to  FIGS. 1 and 2 , in a similar fashion, setting the delay δ k  and gain a k  on subsequent stages or feedback paths of the DFE  110  can remove ISI from the symbols of other symbol periods. 
     Thus, the feed back loop  210  through amplifier  180   a  addresses ISI on a current symbol period resulting from a symbol transmitted in the immediately preceding symbol period. The feedback loop through amplifier  180   b  addresses ISI on the current symbol period resulting from a symbol transmitted during the time frame that is two symbol periods earlier. Likewise, the K th  feedback loop through amplifier  180   c  addresses ISI on the current symbol period due to a symbol transmitted during the K th  previous symbol period. 
     One problem with the conventional DFE  110  lies in implementation feasibility for high-speed multilevel systems with N&gt;2. In these systems, it is often a challenge to build a slicer  150  with a propagation delay sufficiently small to meet the primary loop delay criterion Δ=T 0 . In certain conventional applications involving relatively slow data rates, conventional DFEs  110  may perform adequately. That is, the slicer propagation delay limitation that most conventional DFEs exhibit may not prevent adequate performance at slow or modest data rates. In particular, at low symbol rates (e.g. thousands or a few millions of symbols per second), the functionality illustrated in  FIG. 1  could be realized by sampling the signal with an analog-to-digital converter (“ADC”) and carrying out the DFE operations in a digital signal processor (“DSP”). 
     However, conventional DFEs  110  are often inadequate for high-speed communication systems, (e.g. systems with symbol rates above 100 million bits per second or on the order of billions of symbols per seconds). It is often impractical to implement a conventional DFE  110  with an ADC and a DSP commensurate with the high symbol rate (i.e. small T 0  and hence stringent primary loop delay criterion). 
     For high-speed systems, conventional DFEs  110  have been built for binary (N=2 levels) systems based on fast integrated circuit (“IC”) processes. With good IC design, the propagation delay criterion can be achieved because the slicer  150  (which is usually the most significant contributor to the first loop propagation delay Δ) corresponds to a simple thresholding device that can be implemented with a small amount of circuitry. In particular, a single comparator or limiting amplifier can perform the slicing function for binary communication as known to those skilled in the art. 
     Problems can arise when attempting to use conventional technology to implementing a DFE  110  for a high-speed communication system that uses more than two communication signal levels (N&gt;2) to convey data. One approach is to quantize the slicer input  120  by (i) applying an ADC to decode the signal value, followed by (ii) applying a digital-to-analog converter (“DAC”) to regenerate the multilevel signal. This regeneration, however, is problematic because the propagation delay through the combination of the ADC and DAC usually exceeds the aforementioned time criteria for the primary loop  210 . 
     Conventional attempts have been made to increase DFE performance by reducing propagation delay through aspects of the DFE  100  other than the slicer  150 . That is, conventional technologies may quicken the computing of the amount of ISI compensation (i.e. v fb    130 ) based on the slicer output v out    160 . However, conventional technologies generally fail to adequately shorten the total propagation delay of the primary feedback loop for high-speed multilevel communication. Thus, for many applications, the net delay of the conventional primary loop path  210 , which includes the slicer delay, extends beyond the symbol period and thus is too lengthy. In other words, slow slicing often limits conventional DFEs  110  to addressing ISI on communication signals that convey data with two signal levels or with relatively slow data rates. 
     U.S. Pat. No. 5,594,756, entitled “Decision Feedback Equalization Circuit” proposes a DFE for high-speed communications systems. The disclosed technology attempts to address the difficulty of quickly estimating the feedback correction component from the slicer output. A disclosed feedback mechanism pre-computes correction components for each of the potential cases of transmitted symbols and uses a switch to select a specific one of these correction components for application. One shortcoming of the technology is that the slicer propagation delay, termed “DET” in that patent&#39;s disclosure, generally limits the slicer propagation delay to an unacceptably long time. Thus, for many high-speed applications, the technology of the &#39;756 patent may be inadequate. 
     U.S. Pat. No. 6,047,026, entitled “Method and Apparatus for Automatic Equalization of Very High Frequency Multilevel and Baseband Codes Using a High Speed Analog Decision Feedback Equalizer,” discloses another DFE approach. The &#39;026 patent proposes a DFE structure utilizing positive and negative portions of slicer output pulses that feed into finite impulse response (“FIR”) filters. The use of both positive and negative components purportedly allows operation at high frequencies in certain circumstances. This patent emphasizes achieving faster generation of the ISI corrective component but fails to disclose adequate slicer technology that provides sufficient speed for many applications. Despite improving the speed of the feedback loop in a DFE, the technology of the &#39;026 patent supports symbol rates generally limited by the propagation delay of the slicer. 
     U.S. Pat. No. 6,198,420, entitled “Multiple Level Quantizer,” proposes an ADC with automatic dark-level detection for optical communications contexts. The &#39;420 patent discloses using a flash converter in a manner that can be inadequate for many high speed applications. The technology disclosed in the &#39;420 patent is generally limited in its capability to adequately address propagation delay of an ADC. Further, that technology has limitations related to combining the functionality of a DAC and an ADC in a DFE. The disclosed latching mechanisms following each comparator can add significant propagation delay that may encumber the primary feedback loop with excessive aggregate delay. Latching mechanisms have been known to exhibit propagation delays that can exceed one half of the symbol period, for example. As discussed above, a DFE should regenerate multilevel signals (i.e. the function performed by the combination of the ADC and the DAC) in less time that the time span of a symbol period T 0 . Thus, the technology of the &#39;420 patent may not adequately support many high-speed applications involving multi-level communications. 
     To address these representative deficiencies in the art, what is needed is a capability to deal with ISI in high-speed multi-level communication systems. A further need exists for a DFE that operates in a communication system that conveys data using more than two signal levels. Yet another need exists for a slicer that quantizes multilevel signals to the candidate symbol values with a propagation delay that is small enough to support setting the primary loop delay Δ in the DFE to the symbol period T 0  of the communication system. Such capabilities would reduce ISI effects and facilitate higher bandwidth in numerous communication applications. 
     SUMMARY OF THE INVENTION 
     The present invention supports compensating for signal interference, such as ISI, occurring as a result of transmitting a communication signal through a communication channel or over a communication medium to convey digital data. Compensating for interference can improve signal quality and enhance bandwidth or information carrying capability. 
     A communication system can convey data by transmitting data elements or symbols in a sequential manner, wherein each symbol transmits during a timeframe or symbol period. Each transmitted symbol can be one symbol selected from a finite number of possibilities, for example chosen from a set of binary numbers or other numbers. The waveform of the communication signal during the symbol period can specify the symbol communicated during that symbol period. The waveform can have a specific level or voltage state, selected from a finite number of possibilities, corresponding to the communication symbol. Thus, the level of the waveform during a specific symbol period can identify a specific symbol transmitted on that time interval. Transmitting the data over a physical medium, such as in a wire or through the air, can cause the level of the waveform to vary or deviate from the specified level. ISI or signal energy from one symbol period bleeding into another symbol period can cause such deviation. At the receiving end of a communication link, the deviation can impair identifying the symbol that was transmitted. In other words, a transmitter can output a communication signal with a discrete amplitude corresponding to a specific symbol, and a receiver can receive a distorted version of that signal with an amplitude that is between that discrete level and another discrete level corresponding to a different symbol. 
     In one aspect of the present invention, a signal processing system can process the received communication signal to identify and recover or regenerate the signal level output by the transmitter. That is, a circuit can receive a communication signal that has deviated, drifted, or varied from the amplitude set at the transmitter, process the signal to determine the original amplitude setting, and output a signal having the original amplitude setting. A series, bank, or set of electrical devices, such as comparators, can each compare the received communication signal to a respective reference, such as an electrical voltage or current. Each of these electrical devices or comparators can output a two-state comparison signal. The comparison signal can have a high-voltage (or current) state when the communication signal is above the respective reference and a low-voltage (or current) state when the communication signal is below the reference. A signal adding device, such as a summation node or junction, can provide an output signal comprising a summation of the comparison signals. The output signal can have a level or amplitude set to the discrete value that the transmitter specified at the sending end of the communication link. The signal processing system can process multilevel communication signals, including communication signals that convey digital data via three or more signal levels. The signal processing system can process the communication signal and generate the output signal with a signal delay that is shorter than the symbol period. Thus, the signal processing system can output a result for each symbol in a sequence of symbols. The signal processing system can be a slicer that outputs a sliced signal on a symbol-by-symbol basis. 
     In another aspect of the present invention, a feedback circuit can process the sliced signal, generate a corrective signal, and apply the corrective signal to the communication signal during subsequent timeframes or symbol periods. So applied, the corrective signal can suppress or eliminate interference imposed on later-arriving symbols. That is, the feedback circuit can estimate the interference that a current symbol imposes on subsequent symbols and apply a delayed correction that coincides with the reception of those subsequent symbols. The feedback circuit can comprise one or more feedback paths, each having a delay device and a scaling device such as an amplifier or attenuator. Each of the feedback paths can generate and store a correction signal to correct interference for a subsequent symbol period. The delay device of each feedback path can delay the sliced signal to provide timing that matches one of the subsequent symbol periods. The scaling device of each feedback path can attenuate the sliced signal to approximate the interference that the current symbol imposes on that subsequent symbol period. The feedback circuit can apply to each incoming symbol period an aggregate correction that comprises each correction signal from each of the feedback paths. The applied correction can suppress interference on each incoming symbol period. 
     The discussion of processing communication signals and canceling or correcting interference presented in this summary is for illustrative purposes only. Various aspects of the present invention may be more clearly understood and appreciated from a review of the following detailed description of the disclosed embodiments and by reference to the drawings and claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of a conventional DFE. 
         FIG. 2  is an illustration of a feedback loop of the conventional DFE illustrated in  FIG. 1 . 
         FIG. 3  is a functional block diagram of a conventional flash converter receiving a compensated communication signal. 
         FIG. 4  is a functional block diagram of an exemplary slicer in accordance with an embodiment of the present invention. 
         FIG. 5  is a functional block diagram of an exemplary DFE in accordance with an embodiment of the present invention. 
         FIG. 6  is a flow chart illustrating an exemplary process for slicing a communication signal in accordance with an embodiment of the present invention. 
         FIG. 7  is a flow chart illustrating an exemplary process for equalizing a communication signal in accordance with an embodiment of the present invention. 
     
    
    
     Many aspects of the invention can be better understood with reference to above-described drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of exemplary embodiments of the present invention. Moreover, in the drawings, reference numerals designate corresponding parts throughout the several views. 
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     The present invention supports processing a communication signal to address ISI. In an exemplary system and method, a DFE can address ISI by equalizing a multi-level communication signal using a high-speed slicer that operates with a small propagation delay. While an exemplary slicer will be described in the context of a DFE operating environment, the invention can be used in other applications. A variety of applications can benefit from a multilevel slicer that exhibits small or minimal propagation delay. 
     This invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those having ordinary skill in the art. Furthermore, all “examples” given herein are intended to be non-limiting, and among others supported by exemplary embodiments of the present invention. 
     A multilevel slicer in accordance with an exemplary embodiment of the present invention can comprise an integration of certain elements or functions of a conventional ADC with certain elements or functions of a conventional DAC. In a back-to-back configuration, the ADC elements receive the communication signal and feed the DAC elements, which output a sliced signal. 
     An ADC can receive an analog communication signal having ISI and output a corresponding digital signal representation of that analog signal. Whereas the input analog signal may have any amplitude within an amplitude range, the digital signal representation has a discrete value selected from a finite number of possibilities. A DAC can receive the digital signal representation and output a corresponding analog signal. That is, the DAC sets the amplitude of its analog signal output to a specific level defined by the digital data. Whereas the amplitude of the analog signal input into the ADC may have essentially any value within an amplitude range, the analog signal output by the DAC has a value selected from a limited number of possibilities. Thus, an ADC-DAC pair can process an analog communication signal of variable amplitude and output an analog signal having a fixed amplitude corresponding to a digital state. 
     A slicer in accordance with an exemplary embodiment of the present invention can be made by combining the ADC with the DAC and eliminating extraneous, unnecessary, or redundant circuitry of the ADC and the DAC. That is, integrating the ADC and the DAC can include removing select portions of both the ADC and the DAC associated with converting a signal to and from a plurality of binary signals conveying a binary representation of the multilevel signal. A single or monolithic IC chip can result from or embody this integration, for example. 
     To better understand creating a slicer by integrating an ADC and a DAC, it will be useful to review the operation of a conventional flash converter, which is a type of ADC. Specifically, certain aspects of a conventional flash converter can serve as an architecture platform for a slicer in accordance with an exemplary embodiment of the present invention.  FIG. 3  illustrates a functional block diagram of an exemplary flash converter  310  used to receive a compensated communication signal  140 . 
     The flash converter ADC  310  takes as input the compensated multilevel signal V comp    140 . This signal  140  is split and fed to a set of N−1 comparators  320 . The term “comparator” as used herein refers to a device that compares an input signal to a reference and outputs a signal  330  based on the comparison. Each comparator  320  has its own distinct threshold level v n  or reference that serves as the decision threshold between signal levels n−1 and n. The set of N−1 comparator outputs  330  thus conveys the signal level, albeit in an over-complete representation, using N−1 bits for each symbol. The outputs  330  of the comparators  320  feed to a decoding logic block  340  that translates the information into a maximally concise binary representation using log 2  N bits. As will be appreciated by those skilled in the art, more information on flash converters can be found in the conventional art. 
     One specific embodiment of a flash converter is described in U.S. Pat. No. 6,816,101 by Hietala and Kim, entitled “High-Speed Analog-To-Digital Converter Using a Unique Gray Code,” and granted on Nov. 9, 2004. The contents of U.S. Pat. No. 6,816,101 are hereby incorporated by reference. 
     The decision on the level of the input signal  140  is available from the comparator outputs  330  of the flash converter ADC  310  in  FIG. 3 . The logic block  340  provides the signal level information in a specific binary representation. While the comparator array  320  provides a function useful for a slicer, the decoding logic can be superfluous for the slicer. Thus, as will be discussed in additional detail below, a slicer can comprise the comparator array  320  or front-end of the conventional flash converter ADC  310 . And, the superfluous decoding logic  340  can be eliminated. Since the comparators  320  are arranged in a parallel configuration, the propagation delay through the comparator set  320  is essentially the same as the delay of a single comparator  320   a.    
     The conventional flash converter ADC  310  can be adapted to create a slicer by replacing the decoding logic  340  with a summation node. That is, adding together each of the comparator outputs  330  and bypassing or eliminating the decoding logic block  340  provides a slicing function. As will be discussed in more detail below,  FIG. 4  illustrates an exemplary slicer  400  having this configuration. 
     Referring now to  FIG. 3 , a discussion follows of the principles of operation of the flash converter  310 , its comparators  320 , and the relationships among comparator outputs  330  in the context of creating the slicer  400  that  FIG. 4  illustrates. 
     The parallel comparator set  320  provides information on parallel lines  330  that describes the level of the input signal  140 . That is, the set of individual comparator outputs  330   a ,  330   b  . . .  330   c  specifies the magnitude of v comp    140  within a level of precision. Whereas the comparator array  320  of the flash converter  310  provides a plurality of N−1 binary signals  330 , an exemplary slicer  400  should output a single regenerated multilevel signal. 
     Thus, the slicer  400  should have circuitry to convert the N−1 bits into a single N-level signal in place of the flash converter&#39;s DAC, which conventionally converts a series of log 2 N bits into a single N-level symbol. The over-completeness of the N−1 bit representation can be advantageous for multilevel signal regeneration. In particular, because the N−1 bit representation is over-complete, there are well-defined dependencies among the N−1 bits, i.e. not all permutations of N−1 bit combinations are valid. The slicer  400  can use this property as an architectural basis. 
     The thresholds (v N−1 , v N−2  . . . v 1 ) on the comparator set  320  in  FIG. 3  can be arranged in a monotonic sequence without loss of generality. That is, one can assume that v 1 &lt;v 2 &lt; . . . &lt;v N−1  or could permute the ordering of these reference thresholds to provide an increasing sequence and adjust the decoding logic block  340  accordingly. 
     Because the same signal v comp    140  feeds all N−1 comparators  320 , it follows that if the output of comparator n is “true” (i.e. if v comp &gt;v n ), then the output of comparator m is also “true” (i.e. v comp &gt;v m ) for all m&lt;n since v m &lt;v n . A consequence of this property is that if the signal v comp  lies between v n  and v n+1 , i.e. v n &lt;v comp &lt;v n+1 , then the outputs of comparators 1 through n are “true” and the outputs of comparators n+1 through N−1 are “false.” In other words, in this situation, exactly n of the comparator outputs are “true.” 
     Recognizing that v comp  falling between v n  and v n+1  can be interpreted as declaring the symbol as level n, it follows that counting the number of “true” comparator outputs  330  obtains the desired regenerated multilevel symbol. In other words, the identity of the multilevel symbol for the input signal  140  corresponds to the number of comparator outputs  330  that are in an “on” or high-voltage state. Thus, the multilevel symbol can be regenerated by summing all the comparator outputs  330 . Those skilled in the art will recognize that signal summation can be implemented in a manner that takes negligible time, thereby achieving a desirably small propagation delay. 
       FIG. 4  illustrates an exemplary slicer  400  configured to sum the comparator outputs  330  in accordance with an exemplary embodiment of the present invention. The comparator output lines  330  feed into a summation node  410  that outputs the sliced signal  160 . It may be useful to scale the comparator outputs  330  in order to prevent signal saturation in the summation node  410 . Each of the comparator outputs  330   a ,  330   b  . . .  330   c  may be attenuated by a common scaling factor, for example. Such attenuation does not detract from the performance of the slicer  400  as the effect is that the multilevel slicer output  160  is also attenuated by the same factor. Furthermore, this scaling can be implemented with simple passive elements that introduce negligible propagation delay. 
     Thus, in accordance with an exemplary embodiment of the present invention, the multilevel slicer  400  that  FIG. 4  illustrates can comprise the front end of a conventional flash converter, specifically a set of N−1 comparators  320 . One of the inputs of each comparator  320  couples to the slicer input  140 , while the other input of each comparator  320  is tied to a reference or threshold v n . The threshold for the n th  comparator  320   n  is taken as the desired decision threshold between level n−1 and level n of the multilevel signal. The summation node  410  adds the outputs of the N−1 comparators  320  to regenerate the multilevel signal  160 . As discussed above, optional attenuation components (not shown) between the output of each comparator  320  and the summation node  410  can prevent signal saturation at the summation node  410 . 
     The delay through the comparator set  320  as a whole is essentially the same as the delay through a single comparator  320   a , since the slicer architecture provides a parallel comparator arrangement. Furthermore, the delay through the summation node  410  and any attenuation components can be negligibly small. Thus, the multilevel slicer  400  operates with minimal propagation delay and thereby supports multilevel DFEs with high symbol rates. 
     It will be appreciated by those skilled in the art that the division of the system  400  into functional blocks, modules, or respective sub-modules as illustrated in  FIG. 4  (and similarly the systems illustrated in the other figures discussed herein) is conceptual and does not necessarily indicate hard boundaries of functionality or physical groupings of components. Rather, representation of the exemplary embodiments as illustrations based on functional block diagrams facilitates describing an exemplary embodiment of the present invention. In practice, these modules may be combined, divided, and otherwise repartitioned into other modules without deviating from the scope and spirit of the present invention. 
     Turning now to  FIG. 5 , this figure illustrates a functional block diagram of an exemplary DFE  500  in accordance with an embodiment of the present invention. The DFE  500  comprises the slicer  400  that is illustrated in  FIG. 4  and discussed above. A feedback circuit  510  processes the slicer output  160  to generate ISI compensation  130  in the form of feedback  130  that the summation node  190   a  applies to the incoming communication signal  120 . The feedback circuit  510  adjusts the waveform in each symbol period to compensate for or remove ISI on that portion of the waveform that is due to previously-received symbol periods. 
     The propagation delay of the slicer  400  is less than or equal to the symbol period. That is, the amount of time between a signal entering and exiting the slicer  400  is less than or equal to the amount of time that each data element of the communication signal  120  occupies. In exemplary embodiments, the communication signal  120  can convey data at a rate exceeding one megabit per second, one gigabit per second, ten gigabits per second, or 100 gigabits per second, or in a range thereof. 
     The DFE  500  can comprise a conventional DFE  110 , as illustrated in  FIG. 1  and discussed above, with the slicer  400  replacing the conventional slicer  150 . That is, in one exemplary embodiment of the present invention, a conventional DFE  110  or DFE design can be upgraded by removing the conventional slicer  150  and inserting the slicer  400 . In addition to the conventional DFE  110  illustrated in  FIG. 1  and discussed above, the slicer  400  can be applied to a wide variety of DFE systems, designs, or architectures know to those skilled in the art. Furthermore, a slicer  400  in accordance with an exemplary embodiment of the present invention can enhance performance of other equalizers, equalizing devices, and communication systems. 
     Turning now to  FIG. 6 , this figure illustrates a flowchart of an exemplary process  600 , entitled Slice Signal, for slicing a communication signal  140  according to an embodiment of the present invention. The steps of Process  600  will be discussed with exemplary reference to the slicing system  400  of  FIG. 4 , which is discussed above. 
     Certain steps in this process or the other exemplary processes described herein must naturally precede other steps for the present invention to function as described. However, the present invention is not limited to the order of the steps described if such order or sequence does not alter the functionality of the present invention. That is, it is recognized that some steps may be performed before or after other steps or in parallel with other steps without departing from the scope and spirit of the present invention. 
     At Step  610 , the first step in Process  600 , a communication signal  140  conveys digital information or data in a sequence or series of symbols. Designated timeslots or symbol periods each carry one of the symbols. For each symbol period, a specific signal level, selected from two or more discrete signal level possibilities, identifies or corresponds to the symbol in that symbol period. 
     At Step  615 , the sequence of symbols propagates in a physical medium or communication channel. Energy transfers between or among two or more symbol periods, thus causing ISI that distorts each signal level in each symbol period. 
     At Step  620 , for a current symbol period, the communication signal  140  has an amplitude or level that is between two adjacent levels in the multilevel communication scheme. That is, in response to the ISI or energy transfer, the signal level for the symbol period that arrives at a receiver at a current time has shifted, varied, or deviated from its pre-transmission setting. 
     At Step  625 , circuit traces in the slicer  400  feed the communication signal  140  for the current symbol period to a set, bank, or plurality of comparators  320 . The comparators  320  are disposed in a parallel configuration so that each of the comparators  320  processes the communication signal  140  during an overlapping or essentially concurrent timeframe. 
     At Step  630 , each of the comparators  320  compares the communication signal  140  to a respective reference or threshold (v N−1 , v N−2  . . . v 1 ). Responsive to the comparisons, each comparator  320  outputs a comparison signal  330  that has one of two states. The comparison signal  330   a  has a high state or voltage level if the comparator  320   a  determines that the communication signal  140  is higher than the reference v N−1 . On the other hand, the comparison signal  330   a  assumes a low state or voltage level if the comparator  320   b  determines that the communication signal  140  is lower than the reference v N−1 . 
     At Step  635 , a summation node  410  or other summing device generates the sliced signal  160  for the current symbol period by summing each of the comparison signals  330 . The sliced signal  160  has a level set to one of the two adjacent signal levels. Specifically, the chosen level is the best matching or closest level. Thus, the sliced signal  160  can comprise a regenerated or reconstructed version of a degraded communication signal  140 . 
     Following Step  635 , Process  600  iterates Steps  610 - 635 . Thus, Process  600  iteratively processes the communication signal  140  for each incoming symbol period in the symbol series. 
     Turning now to  FIG. 7 , this figure illustrates a flowchart of an exemplary process  700 , entitled Equalize Signal, for equalizing a communication signal  120  according to an embodiment of the present invention. The steps of Process  700  will be discussed with exemplary reference to the DFE system  500  of  FIG. 5 , which is discussed above. 
     The first step in Process  700  is Slice Signal  600 , which  FIG. 6  illustrates as discussed above. Process  600  outputs a sliced signal  160  having a discrete signal level for a current symbol period. 
     At Step  715 , the first delay element  170   a  of a feedback circuit  510  delays the sliced signal  160  of the current symbol period. The amount of applied delay results in a timing match between the delayed signal and the next incoming symbol period of the communication signal  120 . 
     At Step  720 , the first attenuator or amplifier  180   a  attenuates or scales the delayed sliced signal. The amount of applied attenuation yields a corrective signal that approximates the ISI imposed on the next incoming symbol period by the signal energy of the current symbol period. 
     At Step  725 , the summation node  190   a  of the feedback circuit  510  applies the attenuated and delayed sliced signal to the next incoming or first subsequent symbol period of the communication signal  120 . This compensation or correction  130  reduces the ISI on that symbol period due to the current symbol period. That is, the applied corrective signal  130  comprises a corrective component produced via the first delay  170   a  and the first amplifier  180   a.    
     At Step  730 , the second delay element  170   b  of the feedback circuit  510  further delays the sliced signal of the current symbol period. The applied delay provides a timing match between the delayed signal and the second subsequent symbol period. 
     At Step  735 , the second amplifier  180   b  attenuates the signal output by the second delay element  170   b . The applied attenuation yields an amplitude or level that matches or approximates the ISI that the energy in the current symbol period imposes on the second subsequent symbol period. 
     At Step  740 , the summation node  190   a  applies to the communication signal  120  a corrective component  130  that the second delay element  170   b  and the second amplifier  180   b  produce. Specifically, that component of the corrective signal  130  addresses ISI on the second subsequent symbol period due to the energy transfer from the current symbol period. Following Step  740 , Process  700  iterates, thus applying ISI correction  130  to the communication signal  120  for each symbol period, on a symbol-by-symbol basis. 
     Although a system in accordance with the present invention can comprise a circuit that addresses ISI of a communication signal, those skilled in the art will appreciate that the present invention is not limited to this application and that the embodiments described herein are illustrative and not restrictive. Furthermore, it should be understood that various other alternatives to the embodiments of the invention described here may be employed in practicing the invention. The scope of the invention is intended to be limited only by the claims below.