Abstract:
A pipeline analog-to-digital converter includes a conversion unit receiving an analog input signal and outputting a plurality of digital signals corresponding to quantization values obtained by quantizing the input signal, the conversion unit including a plurality of stages that output the plurality of digital signals, the plurality of stages being connected in a cascade manner, each of the stages receiving a residue analog signal from a previous stage, and a first stage receiving an analog input signal and a digital correction logic receiving the plurality of digital signals, correcting an error, and outputting a digital output signal corresponding to the input signal, wherein a first reference voltage is applied to the plurality of stages, a second reference voltage, which is different from the first reference voltage, is applied to at least one of the plurality of stages, at least one of the plurality of stages includes a plurality of unit capacitors that sample the residue analog signal, and at least one of the plurality of unit capacitors is coupled to the second reference voltage.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims priority from Korean Patent Application No. 10-2007-0098146 filed on Sep. 28, 2007 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to a pipeline analog-to-digital converter and a method of driving the same. 
         [0004]    2. Discussion of Related Art 
         [0005]    In recent years, with the development of digital technologies, an analog-to-digital converter (ADC) has been widely used in high definition TVs, mobile multimedia devices, and wireless communication devices. Various analog-to-digital converters, such as flash analog-to-digital converters and pipeline analog-to-digital converters, have been used. In particular, the pipeline analog-to-digital converter, which includes a plurality of stages connected in series to each other, has been mainly used because high data throughput, reduction in chip area, and low power consumption are realized. 
         [0006]    As the design rule is reduced, however, a high-gain amplifier is needed, which makes it difficult to design a high-resolution pipeline analog-to-digital converter. 
       SUMMARY OF THE INVENTION 
       [0007]    An exemplary embodiment of the present invention provides a pipeline analog-to-digital converter that can realize a low power consumption and a high resolution. 
         [0008]    An exemplary embodiment of the present invention provides a method of driving a pipeline analog-to-digital converter that can realize a low power consumption and a high resolution. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the attached drawings, in which: 
           [0010]      FIG. 1  is a block diagram showing a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0011]      FIG. 2  is an exemplary circuit diagram showing a first Multiplying Digital-to-Analog Converter (MDAC) in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0012]      FIG. 3  is a diagram showing an exemplary unit capacitor array of a first MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0013]      FIG. 4  is a diagram showing input/output transmission characteristics of a first MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0014]      FIG. 5  is an exemplary circuit diagram showing a second MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0015]      FIG. 6  is a diagram showing an exemplary unit capacitor array of a second MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0016]      FIG. 7  is a diagram illustrating a coding method in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; 
           [0017]      FIG. 8  is a block diagram showing a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention; and 
           [0018]      FIG. 9  is a diagram illustrating a coding method in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention. 
       
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0019]    A pipeline analog-to-digital converter according to exemplary embodiments of the present invention will be described with reference to  FIGS. 1 to 7 . 
         [0020]      FIG. 1  is a block diagram showing a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention. In the exemplary embodiment, for explanatory convenience, a pipeline analog-to-digital converter includes five stages, each of which outputs a 12-bit digital output signal in response to an analog input signal, however, the present invention is not limited thereto. 
         [0021]    Referring to  FIG. 1 , the pipeline analog-to-digital converter outputs a digital output signal Dout in response to an analog input signal Ain. The pipeline analog-to-digital converter includes a conversion unit  100  and a digital correction logic  200 . 
         [0022]    The conversion unit  100  transmits a plurality of digital signals D 1  to D 5  to the digital correction logic  200  in response to the input signal Ain. In this exemplary embodiment, the conversion unit  100  includes first to fifth stages, and to each of which is applied the same first reference voltage (not shown). 
         [0023]    Excluding the fifth stage, each of the stages includes an MDAC (Multiplying Digital-to-Analog Converter) and a sub analog-to-digital converter. 
         [0024]    The first stage, 1st STAGE, receives the input signal Ain and outputs an m-bit first digital signal D 1  and a first residue analog signal A 1 . The first stage, 1st STAGE, includes a first sub analog-to-digital converter SUB ADC 1  and a first MDAC, MDAC 1 . 
         [0025]    The first sub analog-to-digital converter SUB ADC 1  can apply the m-bit first digital signal D 1  corresponding to a quantization value to the first MDAC, MDAC 1 , and to the digital correction logic  200  in response to the input signal Ain. The first sub analog-to-digital converter SUB ADC 1  may be, for example, a flash analog-to-digital converter (flash ADC) that includes 2 m −1 comparators. 
         [0026]    The first MDAC, MDAC 1 , compares an analog signal, which is obtained by converting the first digital signal D 1  from the SUB ADC 1 , with the input signal Ain, amplifies the difference between the converted analog signal and the input signal Ain, and transmits the amplified difference to the second stage, 2nd STAGE, as the first residue analog signal A 1 . 
         [0027]    A first MDAC according to an exemplary embodiment of the present invention will be described below in detail with reference to  FIGS. 2 to 4 . 
         [0028]      FIG. 2  is an exemplary circuit diagram showing a first MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention.  FIG. 3  is a diagram showing an exemplary unit capacitor array of a first MDAC in a pipeline analog-to-digital converter, according to an exemplary embodiment of the present invention. In this exemplary embodiment, for explanatory convenience, the first MDAC receives a 3-bit digital signal, however, the present invention is not limited thereto. 
         [0029]    Referring to  FIG. 2 , the first MDAC, MDAC 1 , includes a first switch array  11 , a second switch array  13 , a plurality of unit capacitors C 1  to C 9 , an amplifier AMP, and a control logic  15 . The first MDAC, MDAC 1 , shown in  FIG. 2  receives a first clock signal CLK 1  at a high level and samples the input signal Ain with the first switch array  11 . In addition, the first MDAC, MDAC 1 , receives a second clock signal CLK 2  at a high level, compares the analog signal, which is obtained by converting the first digital signal D 1 , with the input signal Ain in the control logic  15 , amplifies the difference between the analog signal and the input signal Ain in the amplifier AMP, and outputs the amplified difference as the first residue analog signal A 1 . In this exemplary embodiment, the first clock signal CLK 1  and the second clock signal CLK 2  may not overlap each other. 
         [0030]    The first MDAC, MDAC 1 , receives the first clock signal CLK 1  at the high level and samples the input signal Ain. Specifically, if the first clock signal CLK 1  at the high level is received, the first switch array  11  is enabled, and the eight unit capacitors C 1  to C 8  sample the input signal Ain. In this exemplary embodiment, when the input signal Ain is sampled, a switch Q 1  is enabled and the capacitors C 1  to C 8  are grounded. 
         [0031]    The first MDAC, MDAC 1 , receives the second clock signal CLK 2  at a high level, compares the analog signal, which is obtained by converting the first digital signal D 1 , with the input signal Ain in the control logic, amplifies the difference between the analog signal and the input signal Ain in the amplifier AMP, and outputs the amplified difference as the first residue analog signal A 1 . In this exemplary embodiment, when the first residue analog signal A 1  is output, the switch Q 1  is disabled in response to the second clock signal CLK 2 . 
         [0032]    Specifically, the control logic  15  of the first MDAC, MDAC 1 , selectively enables the second switch array  13  in response to the first digital signal D 1 , and couples the plurality of unit capacitors C 1 -C 8  to a first reference voltage Vref, a ground GND, or a feedback F/B. 
         [0033]    Referring to  FIG. 3 , the unit capacitor C 9  is always coupled to the feedback F/B as a fixed feedback unit capacitor, as shown in  FIG. 2 . The other unit capacitors C 1  to C 8  may be selectively coupled to the first reference voltage Vref, the ground GND or the feedback F/B. In this exemplary embodiment, one of the unit capacitors C 1  to C 8  is used as a variable feedback unit capacitor to improve the linearity of the pipeline analog-to-digital converter. 
         [0034]    The first MDAC, MDAC 1 , compares the analog signal, which is obtained by converting the first digital signal D 1 , with the input signal Ain, causes the amplifier AMP to amplify the difference between the analog signal and the input signal Ain 2 k  times (for example, 2 2  times), and outputs the amplified difference as the first residue analog signal A 1 . In this case, k is smaller than m, which is the number of bits of the first digital signal D 1 . 
         [0035]    The DC gain, which is provided by the amplifier AMP, is generally represented by Equation 1. 
         [0000]    
       
         
           
             
               
                 
                   
                     
                       2 
                       k 
                     
                     
                       1 
                       + 
                       
                         
                           ( 
                           
                             1 
                             + 
                             
                               2 
                               k 
                             
                             + 
                             
                               α 
                               p 
                             
                           
                           ) 
                         
                         / 
                         
                           A 
                           0 
                         
                       
                     
                   
                   ≥ 
                   
                     
                       2 
                       k 
                     
                      
                     
                       ( 
                       
                         1 
                         - 
                         
                           2 
                           
                             - 
                             
                               ( 
                               
                                 N 
                                 - 
                                 m 
                               
                               ) 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
         [0036]    In this case, 2 k  denotes an inter-stage gain, A 0  denotes a DC gain of the amplifier AMP, α p  denotes a ratio of summing node parasitic capacitance to feedback capacitance, 2 N  denotes accuracy of input, and m denotes stage resolution. In addition, m, which denotes the stage resolution, is the number of bits of the digital signal that is output from a corresponding stage. N, which denotes the accuracy of the input, is the number of bits of the digital output signal that is output from the pipeline analog-to-digital converter. 
         [0037]    In addition, because the parasitic capacitance is much smaller than the feedback capacitance, if Equation 1 is summarized for the DC gain A 0  while ignoring α p , Equation 2 is obtained. 
         [0000]        Ao≧ 2 (N+k−m)   (2) 
         [0038]    When the pipeline analog-to-digital converter outputs a 12-bit digital output signal Dout in response to the input signal Ain, the minimum DC gain, which is provided by the amplifier AMP, is 6(12+k−m) dB. That is, in the pipeline analog-to-digital converter, the minimum DC gain that is provided by the amplifier AMP is 6(m−k) dB, which is smaller than the minimum DC gain when m and k are the same. For example, the minimum DC gain, which is provided by the amplifier AMP of the first MDAC, MDAC 1 , may be 6 dB, which is smaller than the minimum DC gain when m and k are the same. 
         [0039]      FIG. 4  is a diagram showing input/output transmission characteristics of a first MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention, in which the x-axis represents an input signal, and the y-axis represents an output signal. 
         [0040]    Referring to  FIG. 4 , it can be understood that, from the input/output transmission characteristics of the first MDAC, MDAC 1 , the swing range of the first residue analog signal A 1 , which is output from the first MDAC, MDAC 1 , is lower than the swing range of the input signal Ain, which is output from the first MDAC, MDAC 1 . That is, the swing level of the input signal Ain can be expanded while the swing level of the first residue analog signal A 1  can be adjusted to a stable output range of the amplifier AMP without loss. 
         [0041]    As shown in  FIG. 1 , the second stage 2nd STAGE receives the first residue analog signal A 1  from the first stage 1st STAGE, and outputs a second digital signal D 2  and a second residue analog signal A 2 . The second stage 2nd STAGE includes a second sub analog-to-digital converter SUB ADC 2  and a second MDAC, MDAC 2 . 
         [0042]    The second sub analog-to-digital converter SUB ADC 2  outputs the second digital signal D 2  corresponding to a quantization value to the second MDAC, MDAC 2 , and the digital correction logic  200  in response to the first residue analog signal A 1 . The second digital signal D 2  may have (k+1) bits and (2 k +2) levels. For example, the second digital signal D 2  may have 3 bits and 6 levels. In this case, each level of the digital signal corresponds to each code (for example,  111 ,  110 , . . . ) of the digital signal, as shown in  FIG. 3 . 
         [0043]    In this exemplary embodiment, among the (2 k +2) levels of the second digital signal D 2 , 2 k  levels are actually used as a signal that corresponds to the quantization value, and 2 levels are used as an error-correction signal. In this case, the 2 k  levels, which are used as the signal corresponding to the quantization value, may fall within a nominal range shown in  FIG. 7 . The 2 levels that are used as the error-correction signal may fall within correction ranges ADD 1  and SUB 1  shown in  FIG. 7 . For example, 2 2  levels of the second digital signal D 2  may fall within the nominal range, and the 2 levels thereof may be used as the error-correction signal. 
         [0044]    The second sub analog-to-digital converter SUB ADC 2  may be, for example, a flash analog-to-digital converter that includes 2 k +1 comparators. 
         [0045]    The second MDAC, MDAC 2 , compares the analog signal, which is obtained by converting the second digital signal D 2 , with the first residue analog signal A 1 , amplifies the difference between the analog signal and the first residue analog signal A 1 , and outputs the amplified difference to the third stage 3rd STAGE as the second residue analog signal A 2 . 
         [0046]    A second MDAC according to an exemplary embodiment of the present invention will be described below in detail with reference to  FIGS. 5 and 6 . 
         [0047]      FIG. 5  is a circuit diagram showing a second MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention.  FIG. 6  is a diagram showing a unit capacitor array of a second MDAC in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention. 
         [0048]    Referring to  FIG. 5 , the second MDAC, MDAC 2 , includes a first switch array  21 , a second switch array  23 , a plurality of unit capacitors C 1  to C 8 , an amplifier AMP, and a control logic  25 . The second MDAC, MDAC 2 , receives a third clock signal CLK 3  at a high level and samples the first residue analog signal A 1 . In addition, the second MDAC, MDAC 2 , receives a fourth clock signal CLK 4  at a high level, compares the analog signal, which is obtained by converting the second digital signal D 2 , with the first residue analog signal A 1 , amplifies the difference between the analog signal and the first residue analog signal A 1 , and outputs the amplified difference as the second residue analog signal A 2 . In this exemplary embodiment, the third clock signal CLK 3  may the same as the above-described second clock signal CLK 2 . 
         [0049]    The second MDAC, MDAC 2 , receives the third clock signal CLK 3  at the high level and samples the first residue analog signal A 1 . Specifically, if the third clock signal CLK 3  at the high level is received, the first switch array  21  is enabled, and the eight unit capacitors C 1  to C 8  sample the first residue analog signal A 1 . 
         [0050]    The second MDAC, MDAC 2 , receives the fourth clock signal CLK 4  at the high level, compares the analog signal, which is obtained by converting the second digital signal D 2 , with the first residue analog signal A 1 , amplifies the difference between the analog signal and the second residue analog signal A 1 , and outputs the amplified difference as the second residue analog signal A 2 . 
         [0051]    Specifically, the control logic  25  of the second MDAC, MDAC 2 , selectively enables the second switch array  23  in response to the second digital signal D 2  and selectively couples the plurality of unit capacitors C 1  to C 8  to the first reference voltage Vref, the ground GND, or the feedback F/B. 
         [0052]    Referring to  FIG. 6 , among the plurality of unit capacitors C 1  to C 8 , the six unit capacitors C 2  to C 7  are selectively coupled to the first reference voltage Vref, the ground GND, or the feedback F/B. The unit capacitor C 8  is only coupled to the feedback F/B as a fixed feedback unit capacitor. The first unit capacitor C 1  is coupled only to a second reference voltage Vref/2, thereby correcting the offset of an error correction bit. In this exemplary embodiment, the second reference voltage Vref/2 may be half the first reference voltage Vref. 
         [0053]    The second MDAC, MDAC 2 , compares the analog signal, which is obtained by converting the second digital signal D 2 , with the sampled first residue signal A 1 , causes the amplifier AMP to amplify the difference between the analog signal and the sampled first residue signal A 1  2 k  times (for example, 2 2  times), and outputs the amplified difference as the second residue analog signal A 2 . 
         [0054]    Accordingly, the magnitude of the quantized analog signal in the second stage 2nd STAGE may be the same as the magnitude of the quantized analog signal in the first stage 1st STAGE. For example, in the first stage 1st STAGE and the second stage 2nd STAGE, the magnitudes of the quantized analog signals may be equal to each other, for example, Vref/8. In this exemplary embodiment, the magnitude of the quantized analog signal may be the magnitude of the difference between the levels in the digital signal. 
         [0055]    Similarly, a third sub analog-to-digital converter SUB ADC 3  of the third stage 3rd STAGE outputs a third digital signal D 3  corresponding to the quantization value to a third MDAC, MDAC 3 , and the digital correction logic  200  in response to the second residue analog signal A 2 . The third MDAC, MDAC 3 , compares the analog signal, which is obtained by converting the third digital signal D 3 , with the second residue analog signal A 2 , amplifies the difference between the analog signal and the second residue analog signal A 2 , and outputs the amplified difference to the fourth stage 4th STAGE as the third residue analog signal A 3 . 
         [0056]    A fourth sub analog-to-digital converter SUB ADC 4  of the fourth stage 4th STAGE outputs a fourth digital signal D 4  corresponding to the quantization value to a fourth MDAC, MDAC 4 , and the digital correction logic  200  in response to the third residue analog signal A 3 . The fourth MDAC, MDAC 4 , compares the analog signal, which is obtained by converting the fourth digital signal D 4 , with the third residue analog signal A 3 , amplifies the difference between the analog signal and the third residue analog signal A 3 , and outputs the amplified difference to the fifth stage 5th STAGE as the fourth residue analog signal A 4 . 
         [0057]    In this exemplary embodiment, the magnitudes of the quantized analog signals in the first to fourth stages may be the same. 
         [0058]    The fifth stage 5th STAGE outputs a fifth digital signal D 5  corresponding to the quantization value to the digital correction logic  200  in response to the fourth residue analog signal A 4 . The fifth stage 5th STAGE only includes a fifth sub analog-to-digital converter SUB ADC 5 , unlike the first to fourth stages 1st STAGE to 4th STAGE. The fifth sub analog-to-digital converter SUB ADC 5  outputs the fifth digital signal D 5  that has four bits and ten levels. Here, eight levels of the fifth digital signal D 5  are actually used as a signal corresponding to the quantization value, and two levels of the fifth digital signal D 5  are used as an error-correction signal. In addition, the fifth sub analog-to-digital converter SUB ADC 5  may be, for example, a flash analog-to-digital converter that includes nine comparators. 
         [0059]    The digital correction logic  200  receives the plurality of digital signals D 1  to D 5  from the plurality of stages 1st STAGE to 5th STAGE. When an offset error occurs in a previous stage, for example, the 1st STAGE, the digital correction logic  200  corrects the offset error, and outputs the digital output signal Dout that corresponds to the analog input signal Ain. 
         [0060]    The operation of the pipeline analog-to-digital converter according to an exemplary embodiment of the present invention will be described with reference to  FIGS. 1 to 7 . 
         [0061]      FIG. 7  is a diagram illustrating a coding method in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention. In this exemplary embodiment, a comparator  3  may be provided in the sub analog-to-digital converter of each stage. 
         [0062]    Referring to  FIGS. 1 to 7 , the first stage 1st STAGE outputs the 3-bit first digital signal D 1  corresponding to the quantization value in response to the input signal Ain shown in  FIG. 1 . In addition, the first stage 1st STAGE compares the analog signal, which is obtained by converting the first digital signal D 1 , with the input signal Ain, amplifies the difference between the analog signal and the input signal Ain 2 2  times, and outputs the amplified difference to the second stage 2nd STAGE as the first residue analog signal A 1  shown in  FIG. 1 . 
         [0063]    The second stage 2nd STAGE outputs the second digital signal D 2  that has six levels and three bits. Four levels in the nominal range are actually used as a signal corresponding to the quantization value, and two levels in the correction ranges ADD 1  and SUB 1  are used as an error-correction signal. In this exemplary embodiment, the nominal range may be a range where the result of the previous stage is used as it is, because the offset error does not exist in the previous stage (for example, the 1st STAGE). In addition, each of the correction ranges ADD 1  and SUB 1  may be a range where, when the offset error exists in the previous stage, the offset error is detected in the next stage (for example, the 2nd STAGE), and the offset error is corrected. For example, the offset error may be corrected by interpolating the MSB (Most Significant Bits) of the second stage 2nd STAGE and the LSB (Least Significant Bits) of the first stage 1st STAGE. 
         [0064]    The second stage 2nd STAGE compares the analog signal, which is obtained by converting the second digital signal D 2 , with the first residue analog signal A 1 , amplifies the difference between the analog signal and the first residue analog signal A 1  2 2  times, and outputs the amplified difference to the third stage 3rd STAGE as the second residue analog signal A 2 . In this exemplary embodiment, the magnitudes of the quantized analog signals in the first stage 1st STAGE and the second stage 2nd STAGE may be the same. 
         [0065]    Similarly, the third stage 3rd STAGE outputs the third digital signal D 3  that has six levels and three bits. The third stage 3rd STAGE compares the analog signal, which is obtained by converting the third digital signal D 3 , with the second residue analog signal A 2 , amplifies the difference between the analog signal and the second residue analog signal A 2  2 2  times, and outputs the amplified difference to the fourth stage 4th STAGE as the third residue analog signal A 3 . 
         [0066]    The fourth stage 4th STAGE outputs the fourth digital signal D 4  that has six levels and three bits. The fourth stage 4th STAGE compares the analog signal, which is obtained by converting the fourth digital signal D 4 , with the third residue analog signal A 3 , amplifies the difference between the analog signal and the third residue analog signal A 3  2 2  times, and outputs the amplified difference to the fifth stage 5th STAGE as the fourth residue analog signal A 4 . 
         [0067]    The fifth stage 5th STAGE outputs the fifth digital signal D 5  that has ten levels and four bits. 
         [0068]    The digital correction logic  200  receives the first to fifth digital signals D 1  to D 5  from the first to fifth stages 1st STAGE to 5th STAGE, and outputs the 12-bit digital output signal Dout. 
         [0069]    A pipeline analog-to-digital converter according to an exemplary embodiment of the present invention is described below with reference to  FIGS. 8 and 9 . 
         [0070]      FIG. 8  is a block diagram showing a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention.  FIG. 9  is a diagram illustrating a coding method in a pipeline analog-to-digital converter according to an exemplary embodiment of the present invention. The same parts, which perform the same functions as those shown in  FIGS. 1 to 7 , are represented by the same reference numerals, and the detailed descriptions thereof will be omitted. In this exemplary embodiment, for explanatory convenience, a pipeline analog-to-digital converter includes four stages, each of which outputs a 12-bit digital output signal in response to an analog input signal, however, the present invention is not limited thereto. 
         [0071]    Referring to  FIGS. 8 and 9 , the pipeline analog-to-digital converter according to an exemplary embodiment of the present invention is different from the previously described pipeline analog-to-digital converter in that, in the first stage 1st STAGE and the second stage 2nd STAGE, from 2 k  of Equation 2 that indicates the inter-stage gain, k is smaller than m that indicates the stage resolution. 
         [0072]    The first stage 1st STAGE outputs the 4-bit first digital signal D 1  corresponding to the quantization value in response to the input signal Ain. The first MDAC, MDAC 1 , of the first stage 1st STAGE compares the analog signal, which is obtained by converting the first digital signal D 1 , with the input signal Ain, amplifies the difference between the analog signal and the input signal Ain 2 3  times, and outputs the amplified difference to the second stage 2nd STAGE as the first residue analog signal A 1 . In this exemplary embodiment, the first analog-to-digital converter SUB ADC 1  may be, for example, a flash analog-to-digital converter that includes fifteen comparators, shown typically at 3 in  FIG. 9 . 
         [0073]    The second stage 2nd STAGE outputs the second digital signal D 2  (ten levels and four bits) corresponding to the quantization value in response to the first residue analog signal A 1 . In this exemplary embodiment, the eight levels in the nominal range are actually used as a signal corresponding to the quantization value, and the two levels in the correction ranges ADD 1  and SUB 1  are used as an error-correction signal. The second sub analog-to-digital converter SUB ADC 2  may be, for example, a flash analog-to-digital converter that includes nine comparators. 
         [0074]    The second MDAC, MDAC 2 , of the second stage 2nd STAGE compares the analog signal, which is obtained by converting the second digital signal D 2 , with the first residue analog signal A 1 , amplifies the difference between the analog signal and the first residue analog signal A 1  2 2  times, and outputs the amplified difference to the third stage 3rd STAGE as the second residue analog signal A 2 . 
         [0075]    Similarly, the third stage 3rd STAGE outputs the third digital signal D 3  (six levels and three bits) corresponding to the quantization value in response to the second residue analog signal A 2 . In this exemplary embodiment, four levels in the nominal range are actually used as a signal corresponding to the quantization value, and two levels in the correction ranges ADD 1  and SUB 1  are used as an error-correction signal. The third sub analog-to-digital converter SUB ADC 3  may be, for example, a flash analog-to-digital converter that includes five comparators. 
         [0076]    The third MDAC, MDAC 3 , of the third stage 3rd STAGE compares the analog signal, which is obtained by converting the third digital signal D 3 , with the second residue analog signal A 2 , amplifies the difference between the analog signal and the second residue analog signal A 2  2 2  times, and outputs the amplified difference to the fourth stage 4th STAGE as the third residue analog signal A 3 . 
         [0077]    In this exemplary embodiment, the magnitudes of the quantized analog signals in the first to third stages, 1st STAGE to 3rd STAGE, may be the same. 
         [0078]    The fourth stage 4th STAGE outputs the fourth digital signal D 4  (ten levels and four bits) corresponding to the quantization value in response to the third residue analog signal A 3 . In this exemplary embodiment, eight levels in the nominal range are actually used as a signal corresponding to the quantization value, and two levels in the correction ranges ADD 1  and SUB 1  are used as an error-correction signal. The fourth sub analog-to-digital converter SUB ADC 4  may be, for example, a flash analog-to-digital converter that includes nine comparators. 
         [0079]    The digital correction logic  200  shown in  FIG. 8  receives the first to fourth digital signals, D 1  to D 4 , from the first to fourth stages, 1st STAGE to 4th STAGE, corrects an error, and outputs the digital output signal Dout.