Abstract:
Disclosed are control circuits capable of auto-configuring two LED arrays either in parallel when the two LED arrays are operating off of 100±20% V AC voltage sources or in series when the two LED arrays are operating off of 200±20% V AC voltage sources according to the detection of the AC input voltage magnitude. The disclosed control circuits, ruling over the parallel or series configuration of the two LED arrays, could be implemented in discrete forms or as integrated circuits (IC).

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefits of TW102145706, filed Dec. 11, 2013, and TW103131204, filed Sep. 10, 2014, the disclosures of which are fully incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to control circuits able to auto-configure two extrinsic LED arrays either in parallel or in series in accordance with the detection result of the AC input voltage range. The LED illuminating apparatuses auto-configured with the aid of disclosed control circuits could support dual-range (both 100±20% V and 200±20% V) operation, enabling a wider range of acceptable AC input. 
     2. Description of the Prior Art 
     As compared with the traditional lighting devices, the LED has a higher luminous efficacy. The LEDs can give off more than 100 lumens per watt because less electric energy is converted into waste heat. In sharp contrast, a traditional bulb only gives off about 15 lumens per watt because more electric energy is converted into waste heat. Moreover, LED-based lighting devices are gradually becoming preferred the lighting equipment because of having a relatively longer lifetime to reduce maintenance cost, being less susceptible to exterior interference, and being less likely to get damaged. 
     Technically, LEDs need to be DC-driven. So, an AC sinusoidal voltage source would normally be rectified by a full-wave or half-wave rectifier into a rectified sinusoidal voltage source before coming into use. Besides, the traditional AC-to-DC LED drivers usually require buck or boost converters to step down or up a rectified sinusoidal voltage source to a proper DC voltage level for normal operation, ending up with tons of shortcomings such as bulky and heavy design, conducted and radiated EMI, short lifetime, high cost, and so forth. 
     Traditional AC-direct LED light engines are only for single-range (either 100±20% V or 200±20% V) operation, narrowing the acceptable range of the AC input. To widen the acceptable range of the AC input, the inventors came up with the control circuits for series or parallel auto-configuration. With the aid of the disclosed control circuits for series or parallel auto-configuration, traditional AC-direct LED light engines could be easily upgraded from single-range (either 100±20% V or 200±20% V) operation to dual-range (both 100±20% V and 200±20% V) operation so as to enable a wider acceptable range of the AC input for worldwide applications. 
     In a nutshell, the main purpose of the present invention is to create control circuits so as to upgrade single-range (either 100±20% V or 200±20% V) operation to dual-range (both 100±20% V and 200±20% V) operation. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a control circuit able to auto-configure two extrinsic LED arrays either in parallel or in series according to the AC input voltage range, so that an illuminating apparatus having the control circuit is adaptable to a wider range of acceptable AC input. 
     In one aspect, the present invention provides a control circuit, comprising a first switch, a second switch, a freewheeling switch, and a switch controller, for auto-configuring two extrinsic LED arrays either in parallel or in series according to the AC input voltage range. The first switch is coupled between ground and the cathode of a first extrinsic LED array. The second switch is coupled between an extrinsic voltage source and the anode of a second extrinsic LED array. The freewheeling switch has a channel lying between the cathode of the first extrinsic LED array and the anode of the second extrinsic LED array. The switch controller is coupled to the output terminal of a voltage divider for sampling the peak voltage of the extrinsic voltage source and comparing the sampled peak voltage with an intrinsic reference or threshold voltage. When the extrinsic voltage source comes within a low range, the switch controller turns on the first and the second switch at the same time and the freewheeling switch is off so that the first and the second extrinsic LED array are lit up in parallel. When the extrinsic voltage source comes within a high range, the switch controller turns off the first and the second switch at the same time and the freewheeling switch is on so that the first and the second extrinsic LED array are lit up in series. 
     In another aspect, the present invention provides an integrated circuit having a substrate on which the aforementioned control circuit is integrated. 
     In still another aspect, the present invention provides an illuminating apparatus, comprising the aforementioned control circuit, at least one rectifier coupled to the extrinsic voltage source, as well as a first and a second extrinsic LED array under the control of the control circuit, wherein the first and the second extrinsic LED array each comprises a plurality of LED sub-arrays. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing conceptions and their accompanying advantages of the present invention will get more readily appreciated after being better understood by referring to the following detailed description, in conjunction with the accompanying drawings, wherein: 
         FIG. 1A  illustrates a block diagram of an illuminating apparatus having the control circuit according to an embodiment of the present invention; 
         FIG. 1B  illustrates a diagram showing an integrated circuit having the control circuit according to an embodiment of the present invention; 
         FIG. 1C  illustrates a block diagram of another illuminating apparatus having the control circuit according to another embodiment of the present invention; 
         FIG. 2  illustrates a schematic diagram of an illuminating apparatus having the control circuit according to an embodiment of the present invention; 
         FIG. 3  illustrates a schematic diagram of an illuminating apparatus having the control circuit according to another embodiment of the present invention; 
         FIG. 4  illustrates a schematic diagram of an illuminating apparatus having the control circuit according to another embodiment of the present invention; 
         FIGS. 5(   a ),  5 ( b ), and  5 ( c ) illustrate schematic diagrams showing the applicable types of the comparators according to the embodiments of the present invention; 
         FIG. 6  illustrates a schematic diagram of an illuminating apparatus having the control circuit according to another embodiment of the present invention; 
         FIG. 7  illustrates a schematic diagram of an illuminating apparatus having the control circuit according to another embodiment of the present invention; and 
         FIG. 8  illustrates a schematic diagram of an illuminating apparatus having the control circuit according to still another embodiment of the present invention. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The detailed explanation of the present invention is described as follows. The described preferred embodiments are presented for purposes of illustrations and description, and not intended to limit the scope of the present invention. 
       FIG. 1A  illustrates a block diagram of an illuminating apparatus powered by a single AC voltage source and having a control circuit according to the embodiment of the present invention. The illuminating apparatus  1  comprises a single AC voltage source, a rectifier  100 , a first extrinsic LED array G 1  (comprising sub-arrays L 1 , L 2 , and L 3 ), a second extrinsic LED array G 2  (comprising LED sub-arrays L 4 , L 5 , and L 6 ), and a control circuit  10  used for auto-configuring the two extrinsic LED arrays. The control circuit  10  comprises a voltage divider (resistors R 1  and R 2 ), a first switch S 1 , a second switch S 2 , a freewheeling switch D 0 , and a switch controller  120 . The first extrinsic LED array G 1  and the second extrinsic LED array G 2  each comprise an LED array in any form. Besides, each of the two extrinsic LED arrays has at least one proper intrinsic current-limiting resistor, or is coupled to a current regulator to protect them from being damaged by excessive current flow. On top of that, the first switch S 1  and the second switch S 2  can be implemented with the adoption of Bipolar Junction Transistor (BJT), Junction Field Effect Transistor (JFET), or Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The freewheeling switch D 0  can be a diode or a transistor. If a diode is chosen as the freewheeling switch D 0 , the on or off state of the diode is determined by the forward or reverse bias across the diode. If a transistor is chosen as the freewheeling switch D 0 , the on or off state of the transistor is determined by the control signal from the switch controller  120 . It is necessary that the on or off state of the first switch S 1  be in sync with that of the second switch S 2  but out of sync with that of the freewheeling switch D 0 . In other words, when the first switch S 1  and the second switch S 2  are both on, the freewheeling switch D 0  must be off, and vice versa. 
     The first switch S 1  is coupled between the cathode of the first extrinsic LED array G 1  and ground. The second switch S 2  is coupled between the anode of the second extrinsic LED array G 2  and the high-side DC output terminal of the rectifier  100 . The rectifier  100  provides a rectified sinusoidal voltage source. The freewheeling switch D 0 , which could be a diode or a transistor, has a channel lying between the cathode of the first extrinsic LED array G 1  and the anode of the second extrinsic LED array G 2 . The switch controller  120  has its input terminal coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its first output terminal represented in the form of a solid arrow and coupled to the control terminal of the first switch S 1 , its second output terminal represented in the form of another solid arrow and coupled to the control terminal of the second switch S 2 , and its third optional output terminal represented in the form of a dashed arrow and coupled to the control terminal of the freewheeling switch D 0  implemented with the selection of a transistor. 
     When the AC voltage source comes within a low range, such as 100±20% V, the first switch S 1  and the second switch S 2  are turned on by the switch controller  120  simultaneously. Thus, both the first extrinsic LED array G 1  and the second extrinsic LED array G 2  connect between rectified sinusoidal voltage source and ground. Besides, the freewheeling switch D 0  is off. So, the first extrinsic LED array G 1  and the second extrinsic LED array G 2  are lit up in parallel. 
     When the AC voltage source comes within a high range, such as 200±20% V, the first switch S 1  and the second switch S 2  are turned off by the switch controller  120  simultaneously. Besides, the freewheeling switch D 0  is on. Thus, the first extrinsic LED array G 1  and the second extrinsic LED array G 2  are lit up in series. The amplitude and range of the high range (200±20% V) are twice as high and wide as those of the low range (100±20% V). 
       FIG. 1B  illustrates an integrated circuit having a control circuit according to an embodiment of the present invention. The integrated circuit  20  has four pins A, B, C, and D as well as a substrate  200  on which the control circuit  10 , as shown in  FIG. 1A , is placed. The integrated circuit  20  has its pin A coupled to the low-side terminal of the resistor R 2  and the low-side terminal of the first switch S 1 , its pin B coupled to the low-side terminal of the freewheeling switch D 0  and the low-side terminal of the second switch S 2 , its pin C coupled to the high-side terminal of the first switch S 1  and the high-side terminal of the freewheeling switch D 0 , and its pin D coupled to the high-side terminal of the resistor R 1  and the high-side terminal of the second switch S 2 . 
     In  FIG. 1B , resistors R 1  and R 2  are both placed on the substrate  200 . In other embodiments, resistor R 1  or R 2  can also be placed outside the integrated circuit  20  to make the low and the high range programmable to circuit designers. Pins D and C respectively connect to the anode and the cathode of the first extrinsic LED array G 1 . Pins B and A respectively connect to the anode and the cathode of the second extrinsic LED array G 2 . 
       FIG. 1C  illustrates a block diagram of an illuminating apparatus powered by a dual AC voltage source and having a control circuit according to another embodiment of the present invention. In the present embodiment, the first voltage source AC′, coupled to the rectifier  100 ′ through the switch S 15 , provides a low-range AC voltage such as 100±20% V while the second voltage source AC, coupled to the rectifier  100  through the switch S 25 , provides a high-range AC voltage such as 200±20% V. 
     When the switches S 15  and S 25  are both off, the control circuit  10  is out of operation without the voltage source. The first extrinsic LED array G 1  and the second extrinsic LED array G 2  are both off. When the switch S 15  is on and S 25  is off, the voltage source comes within the low range, the first switch S 1  and the second switch S 2  are both turned on under the control of the switch controller  120 . The freewheeling switch D 0  is off, so the first extrinsic LED array G 1  (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array G 2  (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel. When the switch S 15  is off and S 25  is on, the voltage source comes within the high range, the first switch S 1  and the second switch S 2  are both turned off under the control of the switch controller  120 . The freewheeling switch D 0  is on, so the first extrinsic LED array G 1  and the second extrinsic LED array G 2  are lit up in series. 
     When the switches S 15  and S 25  are both on, the rectifier  100 ′ coupled to the low-range voltage source AC′ through the closed switch S 15  is relatively reverse biased to disallow conduction while the rectifier  100  coupled to the high-range voltage source AC through the closed switch S 25  is relatively forward biased to allow conduction, so the voltage source turns out to be within the high range. The first switch S 1  and the second switch S 2  are both turned off under the control of the switch controller  120 . The freewheeling switch D 0  is on, so the first extrinsic LED array G 1  and the second extrinsic LED array G 2  are lit up in series. 
       FIGS. 2˜4  and  FIGS. 6˜8  illustrate a variety of preferred embodiments of the illuminating apparatus according to the present invention. The main difference between these preferred embodiments lies in the implementation pattern of the control circuit  10 , as shown in  FIG. 1A . That is to say, those skilled in the art might mix and match the various implementation patterns of the first switch S 1 , the second switch S 2 , the freewheeling switch D 0 , and the switch controller  120  within the spirit and scope of the present invention. More specifically, each of the first switch S 1 , the second switch S 2 , the freewheeling switch D 0 , and the switch controller  120  could be picked up and pieced together at random from any one of their preferred embodiments, shown in  FIGS. 2˜4  and  FIG. 6  as examples rather than limitations. 
     Please refer to  FIG. 2 , where the first switch B 1  is an npn BJT, the second switch P 1  is a pnp BJT, and the freewheeling switch D 1  is a diode. The first switch B 1  has its base coupled to the first output terminal of the switch controller  120 , its emitter coupled to ground, and its collector coupled to the cathode of the first extrinsic LED array and the anode of the freewheeling switch D 1 . The second switch P 1  has its base coupled to the low-side terminal of the resistor Rp 1  and the high-side terminal of the resistor Rp 2  (i.e., the second output terminal of the switch controller  120 ), its emitter coupled to the anode of the first extrinsic LED array, the high-side terminal of the resistor Rp 1 , and the high-side DC output terminal of the rectifier  100 , and its collector coupled to the anode of the second extrinsic LED array and the cathode of the freewheeling switch D 1 . 
     The switch controller  120  comprises a peak rectifier PR (comprising a diode D 3  and a capacitor C 2 ), an interlock circuit LC (comprising an interlocking BJT P 3 , a resistor Rp 3 , a resistor Rp 4 , a resistor Rp 5 , a resistor Rc 1 , and an interlocking NMOS M 2 ), a current-limiting resistor Rd 1 , a resistor Rb 1 , a resistor Rp 2 , a diode D 2 , a capacitor C 1 , an npn BJT B 2 , an NMOS M 1 , and a Zener diode Zc. 
     The switch controller  120  has its first input terminal (the anode of the diode D 3 ) coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its second input terminal (the anode of the diode D 2 ) coupled to the anode of the LED sub-array L 6 , its first output terminal (the base of the BJT B 2 , the drain of the NMOS M 1 , and the low-side terminal of the resistor Rb 1 ) coupled to the base of the first switch B 1 , and its second output terminal (the high-side terminal of the resistor Rp 2 ) coupled to the base of the second switch P 1  and the low-side terminal of the resistor Rp 1 . 
     In the present embodiment, the diode D 2  has its anode coupled to the anode of the LED sub-array L 6  and its cathode coupled to the high-side terminal of the current-limiting resistor Rd 1 . Swapping the diode D 2  and the current-limiting resistor Rd 1  is also feasible. The capacitor C 1 , connected in parallel with the Zener diode Zc, is coupled between the current-limiting resistor Rd 1  and ground. As a matter of fact, the LED sub-array L 6  made up of one or more LEDs with an adequate forward voltage drop could serve as a DC voltage source so that the capacitor C 1  could get charged up to the breakdown voltage V Z  of the Zener diode Zc through the diode D 2  and the current-limiting resistor Rd 1  whenever the LED sub-array L 6  is lit up to show its forward voltage drop. 
     The voltage divider (resistors R 1  and R 2 ) is used for sampling the rectified sinusoidal voltage source and the peak rectifier PR is used for holding a sampled peak voltage serving as a signal input to the interlock circuit LC. The interlock circuit LC comprises the interlocking BJT P 3  and the interlocking NMOS M 2 . The interlocking BJT P 3  has its base coupled to the low-side terminal of the resistor Rp 4  and the high-side terminal of the resistor Rp 5 , its emitter coupled to the high-side terminal of the capacitor C 1 , the cathode of the Zener diode Zc, the low-side terminal of the resistor Rd 1 , the high-side terminal of the resistor Rp 4 , and the high-side terminal of the resistor Rb 1 , and its collector coupled to the high-side terminal of the resistor Rp 3 . The interlocking NMOS M 2  has its gate coupled to the high-side terminal of the resistor Rc 1 , the high-side terminal of the capacitor C 2 , the low-side terminal of the resistor Rp 3 , and the cathode of the diode D 3 , its source coupled to the low-side terminal of the resistor Rc 1  and the low-side terminal of the capacitor C 2 , and its drain coupled to the low-side terminal of the resistor Rp 5 . The interlock circuit LC in conjunction with the peak rectifier PR controls the on or off state of the first switch B 1 , the second switch P 1 , and the freewheeling switch D 1 . 
     The sampled peak voltage held across the capacitor C 2  in the peak rectifier PR is compared with the threshold voltage V th,M2  of the interlocking NMOS M 2  for determining the operation mode of the interlock circuit LC. If the sampled peak voltage is lower than the threshold voltage V th,M2 , the interlocking NMOS M 2  wouldn&#39;t get turned on to forward bias the emitter-base junction of the interlocking BJT P 3  through the resistor Rp 5 , so the interlocking BJT P 3  gets turned off. The turn-off of the interlocking BJT P 3  wouldn&#39;t inject a boost voltage 
                 V   C     ×       Rc   ⁢           ⁢   1         Rp   ⁢           ⁢   3     +     Rc   ⁢           ⁢   1           ,         
higher than the threshold voltage V th,M2  by design, into the high-side terminal of the capacitor C 2  and thus the interlocking NMOS M 2  remains off. Such a latch-in-parallel mode takes place when the voltage source comes within the low range.
 
     Conversely, if the sampled peak voltage is higher than the threshold voltage V th,M2,  the interlocking NMOS M 2  would get turned on to forward bias the emitter-base junction of the interlocking BJT P 3  through the resistor Rp 5 , so the interlocking BJT P 3  gets turned on. The turn-on of the interlocking BJT P 3  would inject a boost voltage 
                 V   C     ×       Rc   ⁢           ⁢   1         Rp   ⁢           ⁢   3     +     Rc   ⁢           ⁢   1           ,         
higher than the threshold voltage V th,M2  by design, into the high-side terminal of the capacitor C 2  and thus the interlocking NMOS M 2  remains on. Such a latch-in-series mode takes place when the voltage source comes within the high range.
 
     More specifically, when the voltage source comes within the low range, such as 100±20% V, even the upper limit of the sampled peak voltage, 
               120   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept below the threshold voltage V th,M2  of the interlocking NMOS M 2  by design, leading to the aforementioned latch-in-parallel mode within the low range. In this latch-in-parallel mode, the first switch B 1  and the npn BJT B 2  are both turned on. The turn-on of the BJT B 2  would, in turn, turn on the second switch P 1  by forward biasing the emitter-base junction of the second switch P 1 . With the turn-on of the first switch B 1  and the second switch P 1  at the same time, the freewheeling switch D 1  is reverse biased to turn off. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel within the low range.
 
     Conversely, when the voltage source comes within the high range, such as 200±20% V, even the lower limit of the sampled peak voltage, 
               160   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept above the threshold voltage V th,M2  of the interlocking NMOS M 2  by design, leading to the aforementioned latch-in-series mode within the high range. In this latch-in-series mode, the first switch B 1  and the npn BJT B 2  are both turned off. The turn-off of the BJT B 2  would, in turn, turn off the second switch P 1  by not forward biasing the emitter-base junction of the second switch P 1 . With the turn-off of the first switch B 1  and the second switch P 1  at the same time, the freewheeling switch D 1  is forward biased to turn on. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in series within the high range.
 
     Please refer to  FIG. 3 , where the first switch M 3  is an enhancement mode NMOS, the second switch P 1  is a pnp type BJT, and the freewheeling switch D 1  is a diode. The first switch M 3  has its gate coupled to the first output terminal of the switch controller  120 , its source coupled to ground, and its drain coupled to the cathode of the first extrinsic LED array and the anode of the freewheeling switch D 1 . The second switch P 1  has its emitter coupled to the high-side DC output terminal of the rectifier  100 , the high-side terminal of the resistor R 1 , the anode of the first extrinsic LED array, and the high-side terminal of the resistor Rp 1 , its base coupled to the low-side terminal of the resistor Rp 1  and the second output terminal of the switch controller  120 , and its collector coupled to the cathode of the freewheeling switch D 1  and the anode of the second extrinsic LED array. 
     The switch controller  120  comprises a peak rectifier PR (comprising a diode D 3  and a capacitor C 2 ), an interlock circuit LC 1  (comprising an interlocking BJT P 3 , a resistor Rd 4 , a resistor Rd 5 , a resistor Rc 1 , and a comparator CA 1 ), a resistor Rp 2 , a current-limiting resistor Rd 1 , a voltage divider (resistors Rd 2  and Rd 3 ), a MOSFET M 4 , a diode D 2 , a capacitor C 1 , and a shunt regulator X 1 . The switch controller  120  has its first input terminal (the anode of the diode D 3 ) coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its second input terminal (the anode of the diode D 2 ) coupled to the anode of the LED sub-array L 6 , its first output terminal (the output terminal of the comparator CA 1 , the base of the BJT P 3 , and the low-side terminal of the resistor Rd 5 ) coupled to the gate of the first switch M 3  and the gate of the NMOS M 4 , and its second output terminal (the high-side terminal of the resistor Rp 2 ) coupled to the low-side terminal of the resistor Rp 1  and the base of the second switch P 1 . 
     In the present embodiment, the diode D 2  has its anode coupled to the anode of the LED sub-array L 6  and its cathode coupled to the high-side terminal of the current-limiting resistor Rd 1 . Swapping the diode D 2  and the current-limiting resistor Rd 1  is also feasible. The capacitor C 1 , connected in parallel with the shunt regulator X 1 , is coupled between the current-limiting resistor Rd 1  and ground. As a matter of fact, the LED sub-array L 6  made up of one or more LEDs with an adequate forward voltage drop could serve as a DC voltage source so that the capacitor C 1  could get charged up to a preset voltage level 
               (     1   +       Rd   ⁢           ⁢   2       Rd   ⁢           ⁢   3         )     ×   Vref         
regulated by the shunt regulator X 1  through the diode D 2  and the current-limiting resistor Rd 1  whenever the LED sub-array L 6  is lit up to show its forward voltage drop.
 
     The voltage divider (resistors R 1  and R 2 ) is used for sampling the rectified sinusoidal voltage source and the peak rectifier PR is used for holding a sampled peak voltage serving as a signal input to the interlock circuit LC 1 . The interlock circuit LC 1  comprises the comparator CA 1  and the interlocking BJT P 3 . The comparator CA 1  has its non-inverting input terminal coupled to the reference terminal of the shunt regulator X 1  and fed with a reference voltage (for example, 2.5V) for comparison, its inverting input terminal coupled to the high-side terminal of the capacitor C 2  and fed with the sampled peak voltage for comparison, and its output terminal coupled to the base of the interlocking BJT P 3 , the gate of the first switch M 3 , and the base of the second switch P 1  through the NMOS M 4  and the resistor Rp 2  to control the on or off state of the first and the second switch. 
     The sampled peak voltage received by the inverting input terminal of the comparator CA 1  is compared with the reference voltage received by the non-inverting input terminal of the comparator CA 1 . If the sampled peak voltage is lower than the reference voltage, the output terminal potential of the comparator CA 1  would go up to the terminal voltage Vc of the capacitor C 1  to turn off the interlocking BJT P 3  by not forward biasing its emitter-base junction. The turn-off of the interlocking BJT P 3  wouldn&#39;t inject a boost voltage 
                 V   C     ×       Rc   ⁢           ⁢   1         Rd   ⁢           ⁢   4     +     Rc   ⁢           ⁢   1           ,         
higher than the reference voltage by design, into the high-side terminal of the capacitor C 2  and thus the interlocking BJT P 3  remains off. Such a latch-in-parallel mode takes place when the voltage source comes within the low range.
 
     Conversely, if the sampled peak voltage is higher than the reference voltage, the output terminal potential of the comparator CA 1  would go down to ground level to turn on the interlocking BJT P 3  by forward biasing its emitter-base junction. The turn-on of the interlocking BJT P 3  would inject a boost voltage 
                 V   C     ×       Rc   ⁢           ⁢   1         Rd   ⁢           ⁢   4     +     Rc   ⁢           ⁢   1           ,         
higher than the reference voltage by design, into the high-side terminal of the capacitor C 2  and thus the interlocking BJT P 3  remains on. Such a latch-in-series mode takes place when the voltage source comes within the high range.
 
     More specifically, when the voltage source comes within the low range, such as 100±20% V, even the upper limit of the sampled peak voltage, 
               120   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept below the reference voltage of the shunt regulator X 1  by design, leading to the aforementioned latch-in-parallel mode within the low range. In this latch-in-parallel mode, the first switch M 3  and the NMOS M 4  are both turned on. The turn-on of the NMOS M 4  would, in turn, turn on the second switch P 1  by forward biasing its emitter-base junction through the resistor Rp 2 . With the turn-on of the first switch M 3  and the second switch P 1  at the same time, the freewheeling switch D 1  is reverse biased to turn off. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel within the low range.
 
     Conversely, when the voltage source comes within the high range, such as 200±20% V, even the lower limit of the sampled peak voltage, 
               160   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept above the reference voltage of the shunt regulator X 1  by design, leading to the aforementioned latch-in-series mode within the high range. In this latch-in-series mode, the first switch M 3  and the NMOS M 4  are both turned off. The turn-off of the NMOS M 4  would, in turn, turn off the second switch P 1  by not forward biasing its emitter-base junction through the resistor Rp 2 . With the turn-off of the first switch M 3  and the second switch P 1  at the same time, the freewheeling switch D 1  is forward biased to turn on. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in series within the high range.
 
     Please refer to  FIG. 4 , where the first switch M 3  is an enhancement mode NMOS, the second switch M 5  is a depletion mode NMOS, and the freewheeling switch D 1  is a diode. The first switch M 3  has its gate coupled to the first output terminal of the switch controller  120 , its source coupled to ground, and its drain coupled to the cathode of the first extrinsic LED array and the anode of the freewheeling switch D 1 . The second switch M 5  has its gate coupled to the low-side terminal of the resistor Rm 1 , the anode of the Zener diode Z 1 , and the second output terminal of the switch controller  120 , its source coupled to the high-side terminal of the resistor Rm 1 , the cathode of the Zener diode Z 1 , the cathode of the freewheeling switch D 1 , and the anode of the second extrinsic LED array, and its drain coupled to the high-side DC output terminal of the rectifier  100 , the high-side terminal of the resistor R 1 , and the anode of the first extrinsic LED array. 
     The switch controller  120  comprises a peak rectifier PR (comprising a diode D 3  and a capacitor C 2 ), an interlock circuit LC 2  (comprising an interlocking BJT P 3 , a resistor Rd 4 , a resistor Rd 5 , and a comparator CA 3 ), a current-limiting resistor Rd 1 , a voltage divider (resistors Rd 2  and Rd 3 ), a comparator CA 2 , a diode D 2 , a capacitor C 1 , and a shunt regulator X. The switch controller  120  has its first input terminal (the anode of the diode D 3 ) coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its second input terminal (the anode of the diode D 2 ) coupled to the anode of the LED sub-array L 6 , its first output terminal (the output terminal of the comparator CA 3 , the base of the interlocking BJT P 3 , the low-side terminal of the resistor Rd 5 , and the inverting input terminal of the comparator CA 2 ) coupled to the gate of the first switch M 3 , and its second output terminal (the high-side terminal of the resistor Rm 2 ) coupled to the anode of the Zener diode Z 1 , the low-side terminal of the resistor Rm 1 , and the gate of the second switch M 5 . 
     In the present embodiment, the diode D 2  has its anode coupled to the anode of the LED sub-array L 6  and its cathode coupled to the high-side terminal of the current-limiting resistor Rd 1 . Swapping the diode D 2  and the current-limiting resistor Rd 1  is also feasible. The capacitor C 1 , connected in parallel with the shunt regulator X, is coupled between the current-limiting resistor Rd 1  and ground. The structure of the LED sub-array L 6  and the charging of the capacitor C 1  can be identical or similar to those shown in  FIG. 3 . 
     The voltage divider (resistors R 1  and R 2 ) is used for sampling the rectified sinusoidal voltage source and the peak rectifier PR is used for holding a sampled peak voltage serving as a signal input to the interlock circuit LC 2 . The interlock circuit LC 2  comprises the comparator CA 3  and the interlocking BJT P 3 . The comparator CA 3  has its non-inverting input terminal coupled to the reference terminal of the shunt regulator X and the non-inverting input terminal of the comparator CA 2  as well as fed with a reference voltage (for example, 2.5V) for comparison, its inverting input terminal coupled to the high-side terminal of the capacitor C 2  and fed with the sampled peak voltage for comparison, and its output terminal coupled to the base of the interlocking BJT P 3 , the gate of the first switch M 3 , the low-side terminal of the resistor Rd 5 , and the inverting input terminal of the comparator CA 2  to control the on or off state of the first and the second switch. 
     The sampled peak voltage received by the inverting input terminal of the comparator CA 3  is compared with the reference voltage received by the non-inverting input terminal of the comparator CA 3 . If the sampled peak voltage is lower than the reference voltage, the output terminal potential of the comparator CA 3  would go up to the terminal voltage Vc to turn off the interlocking BJT P 3  by not forward biasing its emitter-base junction. The turn-off of the interlocking BJT P 3  wouldn&#39;t inject a boost voltage 
                 V   C     ×       Rc   ⁢           ⁢   1         Rd   ⁢           ⁢   4     +     Rc   ⁢           ⁢   1           ,         
higher than the reference voltage by design, into the high-side terminal of the capacitor C 2  and thus the interlocking BJT P 3  remains off. Such a latch-in-parallel mode takes place when the voltage source comes within the low range.
 
     Conversely, if the sampled peak voltage is higher than the reference voltage, the output terminal potential of the comparator CA 3  would go down to ground level to turn on the interlocking BJT P 3  by forward biasing its emitter-base junction. The turn-on of the interlocking BJT P 3  would inject a boost voltage 
                 V   C     ×       Rc   ⁢           ⁢   1         Rd   ⁢           ⁢   4     +     Rc   ⁢           ⁢   1           ,         
higher than the reference voltage by design, into the high-side terminal of the capacitor C 2  and thus the interlocking BJT P 3  remains on. Such a latch-in-series mode takes place when the voltage source comes within the high range.
 
     More specifically, when the voltage source comes within the low range, such as 100±20% V, even the upper limit of the sampled peak voltage, 
               120   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept below the reference voltage of the shunt regulator X by design, leading to the aforementioned latch-in-parallel mode within the low range. In this latch-in-parallel mode, the first switch M 3  is turned on and the NMOS M 4  is turned off. The turn-off of the NMOS M 4  would, in turn, turn on the second switch M 5  by providing its gate and source with a zero voltage difference. With the turn-on of the first switch M 3  and the second switch M 5  at the same time, the freewheeling switch D 1  is reverse biased to turn off. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel within the low range.
 
     Conversely, when the voltage source comes within the high range, such as 200±20% V, even the lower limit of the sampled peak voltage, 
               160   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept above the reference voltage of the shunt regulator X by design, leading to the aforementioned latch-in-series mode within the high range. In this latch-in-series mode, the first switch M 3  is turned off and the NMOS M 4  is turned on. The turn-on of the NMOS M 4  would, in turn, turn off the second switch M 5  by providing its gate and source with an adequate negative voltage difference. With the turn-off of the first switch M 3  and the second switch M 5  at the same time, the freewheeling switch D 1  is forward biased to turn on. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in series within the high range.
 
       FIGS. 5(   a ),  5 ( b ), and  5 ( c ) illustrate various types of comparators applicable to  FIGS. 3 and 4 . All of the comparators have a total of five terminals in common: a non-inverting input terminal V I1 , an inverting input terminal V I2 , an output terminal V O , a supply terminal V CC , and a ground terminal. The difference between them lies in the presence or absence of an internal pull-up switch SW+ or an external pull-up resistor R+ between the supply terminal V CC  and the output terminal V O  as well as an internal pull-down switch SW− or an external pull-down resistor R− between the output terminal V O  and the ground terminal. Each switch SW+ or SW− could be but wouldn&#39;t be limited to a MOSFET or a BJT. 
       FIG. 5(   a ) illustrates a first type comparator having a switch SW+ between its supply terminal V CC  and its output terminal Vo as well as a switch SW− between its output terminal Vo and its ground terminal. Whenever the potential of the non-inverting input terminal V I1  is higher than that of the inverting input terminal V I2 , the switch SW+ is closed and the switch SW− is open, so the potential of the comparator output terminal is pulled high through the switch SW+. Whenever the potential of the non-inverting input terminal V I1  is lower than that of the inverting input potential V I2 , the switch SW+ is open and the switch SW− is closed, so the potential of the comparator output terminal is pulled low through the switch SW−. 
       FIG. 5(   b ) illustrates a second type comparator having a resistor R+ between its supply terminal V CC  and its output terminal Vo as well as a switch SW− between its output terminal Vo and its ground terminal. Whenever the potential of the non-inverting input terminal V I1  is higher than that of the inverting input potential V I2 , the switch SW− is open, so the potential of the comparator output terminal is pulled high through the resistor R+. Whenever the potential of the non-inverting input terminal V I1  is lower than that of the inverting input potential V I2 , the switch SW− is closed, so the potential of the comparator output terminal is pulled low through the switch SW−. 
       FIG. 5(   c ) illustrates a third type comparator having a SW+ between its supply terminal V CC  and its output terminal Vo as well as an R− between its output terminal Vo and its ground terminal. Whenever the potential of the non-inverting input terminal V I1  is higher than that of the inverting input potential V I2 , the switch SW+ is closed, so the potential of the comparator output terminal is pulled high through the SW+. Whenever the potential of the non-inverting input terminal V I1  is lower than that of the inverting input potential V I2 , the switch SW+ is open, so the potential of the comparator output terminal is pulled low through the R−. 
     Please refer to  FIG. 6 , where the first switch X 6  is an enhancement mode NMOS, the second switch X 3  is an enhancement mode NMOS, and the freewheeling switch X 11  is an enhancement mode NMOS. The first switch X 6  has its gate coupled to the first output terminal of the switch controller  120 , its source coupled to ground, and its drain coupled to the cathode of the first extrinsic LED array, the source of the freewheeling switch X 11 , the anode of the Zener diode Z 2 , and the low-side terminal of the resistor Rx 8 . The second switch X 3  has its gate coupled to the low-side terminal of the resistor Rk 4 , the high-side terminal of the resistor Rk 9 , the cathode of the Zener diode D 6 , and the emitter of the BJT Q 11  (i.e., the second output terminal of the switch controller  120 ), its source coupled to the drain of the freewheeling switch X 11 , the anode of the second extrinsic LED array, the collector of the BJT Q 11 , and the anode of the Zener diode D 6 , and its drain coupled to the cathode of the LED sub-array L 0  and the anode of the first extrinsic LED array. 
     The switch controller  120  comprises a peak rectifier PR (comprising a diode D 3  and a capacitor C 2 ), an interlock circuit LC 3  (comprising an interlocking BJT Q 8 , a resistor Rd 2 , a resistor Rd 3 , a resistor Rx 3 , a resistor Rx 4 , a resistor Rx 5 , and an interlocking BJT Q 5 ), a current-limiting resistor Rd 1 , a resistor Rx 1 , a resistor Rx 2 , a resistor Rx 6 , a resistor Rx 7 , a resistor Rx 8 , a resistor Rk 1 , a resistor Rk 2 , a resistor Rk 3 , a resistor Rk 4 , a resistor Rk 5 , a resistor Rk 9 , a diode D 2 , a diode D 5 , a diode D 10 , a diode D 16 , a capacitor C 1 , a NMOS X 7 , a NMOS X 12 , a NMOS X 13 , a pnp BJT Q 3 , a pnp BJT Q 11 , a Zener diode D 6 , a Zener diode D 7 , a Zener diode D 8 , a Zener diode Z 2 , a Zener diode Z 3 , a Zener diode Z 4 , and a Zener diode Zc. 
     The switch controller  120  has its first input terminal (the anode of the diode D 3 ) coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its second input terminal (the anode of the diode D 2 ) coupled to the anode of the LED sub-array L 6 , its first output terminal (the cathode of the Zener diode D 7 , the anode of the diode D 5 , and the low-side terminal of the resistor Rx 1 ) coupled to the gate of the first switch X 6 , its second output terminal (the low-side terminal of the resistor Rk 4 , the cathode of the Zener diode D 6 , the emitter of the pnp BJT Q 11 , and the high-side terminal of the resistor Rk 9 ) coupled to the gate of the second switch X 3 , and its third output terminal (the low-side terminal of the resistor Rx 7 , the cathode of the Zener diode Z 2 , and the high-side terminal of the resistor Rx 8 ) coupled to the gate of the freewheeling switch X 11 . 
     In the present embodiment, the diode D 2  has its anode coupled to the anode of the LED sub-array L 6  and its cathode coupled to the high-side terminal of the current-limiting resistor Rd 1 . Swapping the diode D 2  and the current-limiting resistor Rd 1  is also feasible. The capacitor C 1 , connected in parallel with the Zener diode Zc, is coupled between the current-limiting resistor Rd 1  and ground. As a matter of fact, the LED sub-array L 6  made up of one or more LEDs with an adequate forward voltage drop could serve as a DC voltage source so that the capacitor C 1  could get charged up to the breakdown voltage V Z  of the Zener diode Zc through the diode D 2  and the current-limiting resistor Rd 1  whenever the LED sub-array L 6  is lit up to show its forward voltage drop. 
     The voltage divider (resistors R 1  and R 2 ) is used for sampling the rectified sinusoidal voltage source and the peak rectifier PR is used for holding a sampled peak voltage serving as a signal input to the interlock circuit LC 3 . The interlock circuit LC 3  comprises the interlocking BJT Q 8  and the interlocking BJT Q 5 . The interlocking BJT Q 8  has its base coupled to the low-side terminal of the resistor Rd 2 , its emitter coupled to ground, and its collector coupled to the low-side terminal of the resistor Rx 5  as well as the cathodes of the diode D 5  and the diode D 10 . The interlocking BJT Q 5  has its emitter coupled to the high-side terminal of the capacitor C 1 , the cathode of the Zener diode Zc, the low-side terminal of the resistor Rd 1 , and the high-side terminal of the resistor Rx 4 , its base coupled to the low-side terminal of the resistor Rx 4  and the high-side terminal of the resistor Rx 5 , and its collector coupled to the high-side terminal of the resistor Rx 3 . The resistor Rd 2  is used as an anti-clamping resistor. The interlock circuit LC 3  in conjunction with the peak rectifier PR controls the on or off state of the first switch X 6 , the second switch X 3 , and the freewheeling switch X 11 . 
     The sampled peak voltage held across the capacitor C 2  in the peak rectifier PR is compared with the cut-in voltage of the interlocking BJT Q 8  for determining the operation mode of the interlock circuit LC 3 . If the sampled peak voltage is lower than the cut-in voltage, the interlocking BJT Q 8  wouldn&#39;t get turned on to forward bias the emitter-base junction of the interlocking BJT Q 5  through the resistor Rx 5 , so the interlocking BJT Q 5  gets turned off. The turn-off of the interlocking BJT Q 5  wouldn&#39;t inject a boost voltage 
                 V   C     ×       Rd   ⁢           ⁢   3         Rx   ⁢           ⁢   3     +     Rd   ⁢           ⁢   3           ,         
higher than the cut-in voltage by design, into the high-side terminal of the capacitor C 2  and thus the interlocking BJT Q 5  remains off. Such a latch-in-parallel mode takes place when the voltage source comes within the low range.
 
     Conversely, if the sampled peak voltage is higher than the cut-in voltage, the interlocking BJT Q 8  would get turned on to forward bias the emitter-base junction of the interlocking BJT Q 5  through the resistor Rx 5 , so the interlocking BJT Q 5  gets turned on. The turn-on of the interlocking BJT Q 5  would inject a boost voltage 
                 V   C     ×       Rd   ⁢           ⁢   3         Rx   ⁢           ⁢   3     +     Rd   ⁢           ⁢   3           ,         
higher than the cut-in voltage by design, into the high-side terminal of the capacitor C 2  and thus the interlocking BJT Q 5  remains on. Such a latch-in-series mode takes place when the voltage source comes within the high range.
 
     More specifically, when the voltage source comes within the low range, such as 100±20% V, even the upper limit of the sampled peak voltage, 
               120   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept below the cut-in voltage of the interlocking BJT Q 8  by design, leading to the aforementioned latch-in-parallel mode within the low range. In this latch-in-parallel mode, the first switch X 6  and the NMOS X 12  are both turned on. The turn-on of the NMOS X 12  would, in turn, turn on the second switch X 3  by pulling low the gate potential of the NMOS X 7  and not forward biasing the emitter-base junction of the BJT Q 11 . With the turn-on of the first switch X 6  and the second switch X 3  at the same time, the freewheeling switch X 11  gets turned off due to the turn-off of the BJT Q 3  to discharge its intrinsic gate-source capacitor. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel within the low range.
 
     Conversely, when the voltage source comes within the high range, such as 200±20% V, even the lower limit of the sampled peak voltage, 
               160   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept above the cut-in voltage of the interlocking BJT Q 8  by design, leading to the aforementioned latch-in-series mode within the high range. In this latch-in-series mode, the first switch X 6  and the NMOS X 12  are both turned off. The turn-off of the NMOS X 12  would, in turn, turn off the second switch X 3  by not pulling low the gate potential of the NMOS X 7  and forward biasing the emitter-base junction of the BJT Q 11 . With the turn-off of the first switch X 6  and the second switch X 3  at the same time, the freewheeling switch X 11  gets turned on due to the turn-on of the BJT Q 3  to charge its intrinsic gate-source capacitor. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in series within the high range.
 
     Please refer to  FIG. 7 , where the illuminating apparatus further comprises a current regulator R and a current regulator R′. The current regulator R comprises a NMOS Ma, a resistor Rd, a resistor Ra, and a BJT Ba. The NMOS Ma has its gate coupled to the collector of the BJT Ba and the low-side terminal of the resistor Ra, its source coupled to the base of the BJT Ba and the high-side terminal of the resistor Rd, and its drain coupled to the high-side DC output terminal of the rectifier  100  and the high-side terminal of the resistor Ra. The BJT Ba has its base coupled to the source of the NMOS Ma and the high-side terminal of the resistor Rd, its emitter coupled to the low-side terminal of the resistor Rd and the anode of the first extrinsic LED array, and its collector coupled to the gate of the NMOS Ma and the low-side terminal of the resistor Ra. The current regulator R′ comprises a NMOS Ma′, a resistor Rd′, a resistor Ra′, and a BJT Ba′. The structure of the current regulator R′ is similar to that of the current regulator R, and the similarity is not repeated herein. 
     When the first and the second extrinsic LED array are lit up in parallel, the current flowing through the first extrinsic LED array would be regulated by the current regulator R at a preset current level of 
                 V     be   ,   Ba       Rd     ,         
wherein V be,Ba  represents the cut-in voltage of the BJT Ba and Rd represents the resistance of the current-sensing resistor Rd. Similarly, the current flowing through the second extrinsic LED array would be regulated by the current regulator R′ at a preset current level of
 
                 V     be   ,     Ba   ′           Rd   ′       ,         
wherein V be,Ba′  represents the cut-in voltage of the BJT Ba′ and Rd′ represents the resistance of the current-sensing resistor Rd′. On the contrary, when the first and the second extrinsic LED array are lit up in series, the current flowing through the first and second extrinsic LED array would be regulated by the current regulator R at a preset current level of
 
     
       
         
           
             
               
                 V 
                 
                   be 
                   , 
                   Ba 
                 
               
               Rd 
             
             . 
           
         
       
     
     In this embodiment, the first switch M 7  is an enhancement mode NMOS, the second switch P 1  is a pnp type BJT, and the freewheeling switch D 1  is a diode. The first switch M 7  has its gate coupled to the first output terminal of the switch controller  120 , its source coupled to ground, and its drain coupled to the cathode of the first extrinsic LED array and the anode of the freewheeling switch D 1 . The second switch P 1  has its base coupled to the low-side terminal of the resistor r 7  and the high-side terminal of the resistor r 8 , its emitter coupled to the high-side DC output terminal of the rectifier  100 , the high-side terminal of the current regulator R, and the high-side terminal of the resistor r 7 , and its collector coupled to the high-side terminal of the current regulator R′. 
     The switch controller  120  comprises a peak rectifier PR (comprising a diode D 3  and a capacitor C 2 ), an interlock circuit LC 4  (comprising an interlocking BJT B 4 , a resistor r 3 , a resistor r 9 , a resistor r 10 , a resistor r 11 , and an interlocking shunt regulator X), a current-limiting resistor Rb, a resistor r 5 , a resistor r 6 , a resistor r 7 , a resistor r 8 , a diode D 2 , a capacitor C 1 , a diode D 5 , a diode D 10 , a Zener diode D 7 , a Zener diode D 8 , and a Zener diode Zb. The switch controller  120  has its first input terminal (the anode of the diode D 3 ) coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its second input terminal (the high-side terminal of the resistor Rb) coupled to the anode of the LED sub-array L 6 , its first output terminal (the cathode of the Zener diode D 7  and the low-side terminal of the resistor r 6 ) coupled to the gate of the first switch M 7 , and its second output terminal (the low-side terminal of the resistor r 7  and the high-side terminal of the resistor r 8 ) coupled to the base of the second switch P 1 . 
     The diode D 2  has its anode coupled to the low-side terminal of the resistor Rb and its cathode coupled to the high-side terminal of the capacitor C 1 , the cathode of the Zener diode Zb, and the emitter of the BJT B 4 . Swapping the diode D 2  and the current-limiting resistor Rb is also feasible. The capacitor C 1 , connected in parallel with the Zener diode Zb, is coupled between the cathode of the diode D 2  and ground. As a matter of fact, the LED sub-array L 6  made up of one or more LEDs with an adequate forward voltage drop could serve as a DC voltage source so that the capacitor C 1  could get charged up to the breakdown voltage of the Zener diode Zb through the diode D 2  and the current-limiting resistor Rb whenever the LED sub-array L 6  is lit up to show its forward voltage drop. 
     The voltage divider (resistors R 1  and R 2 ) is used for sampling the rectified sinusoidal voltage source and the peak rectifier PR is used for holding a sampled peak voltage serving as a signal input to the interlock circuit LC 4 . The interlocking BJT B 4  has its base coupled to the low-side terminal of the resistor r 10  and the high-side terminal of the resistor r 11 , its emitter coupled to the high-side terminal of the capacitor C 1 , the cathode of the Zener diode Zb, the cathode of the diode D 2 , and the high-side terminal of the resistor r 10 , and its collector coupled to the high-side terminal of the resistor r 9 . The interlocking shunt regulator X has its reference terminal coupled to the low-side terminal of the resistor r 9 , the high-side terminal of the resistor r 3 , the high-side terminal of the capacitor C 2 , and the cathode of the diode D 3 , its cathode coupled to the low-side terminal of the resistor r 11 , the cathode of the diode D 10 , and the cathode of the diode D 5 , and its anode coupled to the low-side terminal of the resistor r 3  and the low-side terminal of the capacitor C 2 . The interlock circuit LC 4  in conjunction with the peak rectifier PR controls the on or off state of the first switch M 7  and the second switch P 1  as well as the reverse or forward bias across the freewheeling switch D 1 . 
     The sampled peak voltage held across the capacitor C 2  in the peak rectifier PR is compared with the reference voltage of the interlocking shunt regulator X (V ref,X ) for determining the operation mode of the interlock circuit LC 4 . If the sampled peak voltage is lower than the reference voltage V ref,X , the interlocking shunt regulator X wouldn&#39;t get turned on to forward bias the emitter-base junction of the interlocking BJT B 4  through the resistor r 11 , so the interlocking BJT B 4  gets turned off. The turn-off of the interlocking BJT B 4  wouldn&#39;t inject a boost voltage 
                 V   C     ×       r   ⁢           ⁢   3         r   ⁢           ⁢   3     +     r   ⁢           ⁢   9           ,         
higher than the reference voltage V ref,X  by design, into the high-side terminal of the capacitor C 2  and thus the interlocking shunt regulator X remains off. Such a latch-in-parallel mode takes place when the voltage source comes within the low range.
 
     Conversely, if the sampled peak voltage is higher than the reference voltage V ref,X , the interlocking shunt regulator X would get turned on to forward bias the emitter-base junction of the interlocking BJT B 4  through the resistor r 11 , so the interlocking BJT B 4  gets turned on. The turn-on of the interlocking BJT B 4  would inject a boost voltage 
                 V   C     ×       r   ⁢           ⁢   3         r   ⁢           ⁢   3     +     r   ⁢           ⁢   9           ,         
higher than the reference voltage V ref,X  by design, into the high-side terminal of the capacitor C 2  and thus the interlocking shunt regulator X remains on. Such a latch-in-series mode takes place when the voltage source comes within the high range.
 
     More specifically, when the voltage source comes within the low range, such as 100±20% V, even the upper limit of the sampled peak voltage, 
               120   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept below the reference voltage of the interlocking shunt regulator X (V ref,X ) by design, leading to the aforementioned latch-in-parallel mode within the low range. In this latch-in-parallel mode, the first switch M 7  and the NMOS M 6  are both turned on. The turn-on of the NMOS M 6  would, in turn, turn on the second switch P 1  by forward biasing its emitter-base junction through the resistor r 8 . With the turn-on of the first switch M 7  and the second switch P 1  at the same time, the freewheeling switch D 1  is reverse biased to turn off. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel within the low range and driven with a regulated current
 
                 (       V     be   ,   Ba       Rd     )     ⁢           ⁢   and   ⁢           ⁢     (       V     be   ,     Ba   ′           Rd   ′       )       ,         
respectively.
 
     Conversely, when the voltage source comes within the high range, such as 200±20% V, even the lower limit of the sampled peak voltage, 
               160   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept above the reference voltage of the interlocking shunt regulator X (V ref,X ) by design, leading to the aforementioned latch-in-series mode within the high range. In this latch-in-series mode, the first switch M 7  and the NMOS M 6  are both turned off. The turn-off of the NMOS M 6  would, in turn, turn off the second switch P 1  by not forward biasing its emitter-base junction through the resistor r 8 . With the turn-off of the first switch M 7  and the second switch P 1  at the same time, the freewheeling switch D 1  is forward biased to turn on. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in series within the high range and driven with a regulated current
 
               (       V     be   ,   Ba       Rd     )     ,         
commonly.
 
     Please refer to  FIG. 8 , where the illuminating apparatus further comprises a current regulator R and a current regulator R′. The structure of the current regulator R and the current regulator R′ in  FIG. 8  is similar to that in  FIG. 7 , and the similarity is not repeated herein. The current regulator R′ also functions as a second switch S 2 . 
     When the first and the second extrinsic LED array are lit up in parallel, the current flowing through the first extrinsic LED array would be regulated by the current regulator R at a preset current level of 
                 V     be   ,   Ba       Rd     ,         
wherein V be,Ba  represents the cut-in voltage of the BJT Ba and Rd represents the resistance of the current-sensing resistor Rd. Similarly, the current flowing through the second extrinsic LED array would be regulated by the current regulator R′ at a preset current level of
 
                 V     be   ,     Ba   ′           Rd   ′       ,         
wherein V be,Ba′  represents the cut-in voltage of the BJT Ba′ and Rd′ represents the resistance of the current-sensing resistor Rd′. On the contrary, when the first and the second extrinsic LED array are lit up in series, the current flowing through the first and second extrinsic LED array would be regulated by the current regulator R at a preset current level of
 
     
       
         
           
             
               
                 V 
                 
                   be 
                   , 
                   Ba 
                 
               
               Rd 
             
             . 
           
         
       
     
     In this embodiment, the first switch M 7  is an enhancement mode NMOS, the second switch S 2  is the current regulator R′, and the freewheeling switch D 1  is a diode. The first switch M 7  has its gate coupled to the first output terminal of the switch controller  120 , its source coupled to ground, and its drain coupled to the cathode of the first extrinsic LED array, and the anode of the freewheeling switch D 1 . The second switch S 2  (the current regulator R′) has its control terminal coupled to the second output terminal of the switch controller  120  (the emitter of the BJT B 3  and the high-side terminal of the resistor r 7 ), its first channel terminal coupled to the high-side DC output terminal of the rectifier  100 , and its second channel terminal coupled to the anode of the second extrinsic LED array and the cathode of the freewheeling switch D 1 . 
     The switch controller  120  comprises a peak rectifier PR (comprising a diode D 3  and a capacitor C 2 ), an interlock circuit LC 5  (comprising an interlocking BJT B 4 , a resistor r 3 , a resistor r 9 , a resistor r 10 , a resistor r 11 , and an interlocking shunt regulator X), a current-limiting resistor Rb, a resistor r 6 , a resistor r 7 , a resistor r 8 , a diode D 2 , a diode D 5 , a capacitor C 1 , a Zener diode D 7 , and a Zener diode Zb. The switch controller  120  has its first input terminal (the anode of the diode D 3 ) coupled to the output terminal of the voltage divider (resistors R 1  and R 2 ), its second input terminal (the high-side terminal of the resistor Rb) coupled to the anode of the LED sub-array L 6 , its first output terminal (the cathode of the Zener diode D 7  and the low-side terminal of the resistor r 6 ) coupled to the gate of the first switch M 7 , and its second output terminal (the high-side terminal of the resistor r 7  and the emitter of the BJT B 3 ) coupled to the low-side terminal of the resistor Ra′, the collector of BJT Ba′, and the gate of the NMOS Ma′ in the second switch S 2 . 
     In the present embodiment, the diode D 2  has its anode coupled to the low-side terminal of the current-limiting resistor Rb and its cathode coupled to the high-side terminal of the capacitor C 1 . Swapping the diode D 2  and the current-limiting resistor Rb is also feasible. The capacitor C 1 , connected in parallel with the Zener diode Zb, is coupled between the cathode of the diode D 2  and ground. As a matter of fact, the LED sub-array L 6  made up of one or more LEDs with an adequate forward voltage drop could serve as a DC voltage source so that the capacitor C 1  could get charged up to the breakdown voltage of the Zener diode Zb through the diode D 2  and the current-limiting resistor Rb whenever the LED sub-array L 6  is lit up to show its forward voltage drop. 
     The voltage divider (resistors R 1  and R 2 ) is used for sampling the rectified sinusoidal voltage source and the peak rectifier PR is used for holding a sampled peak voltage serving as a signal input to the interlock circuit LC 5 . The interlocking BJT B 4  has its base coupled to the low-side terminal of the resistor r 10  and the high-side terminal of the resistor r 11 , its emitter coupled to the high-side terminal of the capacitor C 1 , the cathode of the Zener diode Zb, the cathode of the diode D 2 , and the high-side terminal of the resistor r 10 , and its collector coupled to the high-side terminal of the resistor r 9 . The interlocking shunt regulator X has its reference terminal coupled to the low-side terminal of the resistor r 9 , the high-side terminal of the resistor r 3 , the high-side terminal of the capacitor C 2 , and the cathode of the diode D 3 , its cathode coupled to the low-side terminal of the resistor r 11  and the cathode of the diode D 5 , and its anode coupled to the low-side terminal of the resistor r 3  and the low-side terminal of the capacitor C 2 . The interlock circuit LC 5  in conjunction with the peak rectifier PR controls the on or off state of the first switch M 7  and the second switch S 2  (the current regulator R′) as well as the reverse or forward bias across the freewheeling switch D 1 . 
     The sampled peak voltage held across the capacitor C 2  in the peak rectifier PR is compared with the reference voltage of the interlocking shunt regulator X (V ref,X ) for determining the operation mode of the interlock circuit LC 5 . If the sampled peak voltage is lower than the reference voltage V ref,X , the interlocking shunt regulator X wouldn&#39;t get turned on to forward bias the emitter-base junction of the interlocking BJT B 4  through the resistor r 11 , so the interlocking BJT B 4  gets turned off. The turn-off of the interlocking BJT B 4  wouldn&#39;t inject a boost voltage 
                 V   C     ×       r   ⁢           ⁢   3         r   ⁢           ⁢   3     +     r   ⁢           ⁢   9           ,         
higher than the reference voltage V ref,X , by design, into the high-side terminal of the capacitor C 2  and thus the interlocking shunt regulator X remains off. Such a latch-in-parallel mode takes place when the voltage source comes within the low range.
 
     Conversely, if the sampled peak voltage is higher than the reference voltage V ref,X , the interlocking shunt regulator X would get turned on to forward bias the emitter-base junction of the interlocking BJT B 4  through the resistor r 11 , so the interlocking BJT B 4  gets turned on. The turn-on of the interlocking BJT B 4  would inject a boost voltage 
                 V   C     ×       r   ⁢           ⁢   3         r   ⁢           ⁢   3     +     r   ⁢           ⁢   9           ,         
higher than the reference voltage V ref,X , by design, into the high-side terminal of the capacitor C 2  and thus the interlocking shunt regulator X remains on. Such a latch-in-series mode takes place when the voltage source comes within the high range.
 
     More specifically, when the voltage source comes within the low range, such as 100±20% V, even the upper limit of the sampled peak voltage, 
               120   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept below the reference voltage of the interlocking shunt regulator X (V ref,X ) by design, leading to the aforementioned latch-in-parallel mode within the low range. In this latch-in-parallel mode, the first switch M 7  is turned on and the BJT B 3  is turned off. The gate and the source of the NMOS Ma′ are not shorted out by the turn-off of the BJT B 3 , so the second switch S 2  gets turned on. With the turn-on of the first switch M 7  and the second switch S 2  at the same time, the freewheeling switch D 1  is reverse biased to turn off. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in parallel within the low range and driven with a regulated current
 
                 (       V     be   ,   Ba       Rd     )     ⁢           ⁢   and   ⁢           ⁢     (       V     be   ,     Ba   ′           Rd   ′       )       ,         
respectively.
 
     Conversely, when the voltage source comes within the high range, such as 200±20% V, even the lower limit of the sampled peak voltage, 
               160   ⁢     2     ⁢       R   ⁢           ⁢   1         R   ⁢           ⁢   1     +     R   ⁢           ⁢   2           ,         
is kept above the reference voltage of the interlocking shunt regulator X (V ref,X ) by design, leading to the aforementioned latch-in-series mode within the high range. In this latch-in-series mode, the first switch M 7  is turned off and the BJT B 3  is turned on. The turn-on of the BJT B 3  would, in turn, turn off the second switch S 2  by shorting out the gate and the source of the NMOS Ma′. With the turn-off of the first switch M 7  and the second switch S 2  at the same time, the freewheeling switch D 1  is forward biased to turn on. The first extrinsic LED array (comprising LED sub-arrays L 1 , L 2 , and L 3 ) and the second extrinsic LED array (comprising LED sub-arrays L 4 , L 5 , and L 6 ) are lit up in series within the high range and driven with a regulated current
 
               (       V     be   ,   Ba       Rd     )     ,         
commonly.
 
     To sum up, the aforementioned preferred embodiments according to the present invention provide the LED illuminating apparatuses adaptable to dual-range (both 100±20% V and 200±20% V) operation to meet worldwide needs while being able to achieve tons of advantages: high driver efficiency, high power factor (PF), high product manufacturability, high product reliability, low bill of materials (BOM) cost, low maintenance cost, low parts count, low total harmonic distortion (THD), no conducted and radiated electromagnetic interference (EMI), no through-hole components, no electrolytic capacitors, no magnetic components, and tight line regulation especially when used in collocation with traditional AC-direct LED light engines. 
     While the present invention is susceptible to various modifications and alternative forms, specific examples thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the present invention should not be limited to the disclosed particular forms, but to the contrary, should cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims.