Abstract:
A charge pump CMOS circuit comprises a differential input stage with two parallel circuit branches. Each of the parallel circuit branches has a diode-connected MOS transistor connected in series with a complementary input MOS transistor. There is a common tail current source for both circuit branches. The diode-connected MOS transistors each have their gate/drain node connected to corresponding current sources. The charge pump CMOS circuit is suitable for use in an oscillator.

Description:
TECHNICAL FIELD OF THE INVENTION 
       [0001]    The technical field of this invention is generally CMOS charge pump circuits. More particularly, but not exclusively, the present invention relates to a pre-bias mechanism for charge pumps in clock control applications. 
       BACKGROUND OF THE INVENTION 
       [0002]    Clock control applications generally require a charge pump controlled by a digital clock signal, for example in regulation of the duty cycle of a crystal oscillator in an ultra-low power microcontroller circuit. When a charge pump is controlled by a clock signal, the charge pump switches between a positive and a negative current controlled by the clock signal. Switching of the full output current causes a larger than required voltage change in diode connected MOS transistors used in current mirror operational amplifiers in the charge pump circuit. This increases the delay of the charge pump. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention is a charge pump CMOS circuit, including a differential input stage with two parallel circuit branches. Each of the parallel circuit branches has a diode connected MOS transistor connected in series with a complementary input MOS transistor. The parallel circuit branches have a common tail current source. The diode-connected MOS transistors each have their gate/drain node connected to a current source. This provides a pre-bias scheme, which avoids complete discharge of the diode-connected MOS transistors during switching, therefore reducing the delay in charging up the voltage nodes in the driver. 
         [0004]    Preferably, each of the parallel circuit branches has an associated current mirror stage. One of the current mirror stages can be a single-ended output stage. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    These and other aspects of this invention are illustrated in the drawings, in which: 
           [0006]      FIG. 1  illustrates a charge pump CMOS circuit according to the invention; and 
           [0007]      FIG. 2  illustrates the clock signals applied to the inputs of the charge pump CMOS circuit according to the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0008]      FIG. 1  shows a charge pump CMOS circuit, which is basically a current mirror OTA. The circuit includes an N-channel MOS transistor MN 0  having a source terminal connected to a source terminal of another N-channel MOS transistor MN 1 . Gate terminals of transistors MN 0  and MN 1  receive respective differential input signals so that the transistors MN 0  and MN 1  are differential input stages. The drain terminal of the transistor MN 0  is connected to the drain terminal of a P-channel MOS transistor MP 3 . The drain terminal of the transistor MN 1  is connected to the drain terminal of a P-channel MOS transistor MP 4 . The transistor pairs MN 0  and MP 3 , and MN 1  and MP 4  form parallel circuit branches. Transistors MP 3  and MP 4  are diode connected and have interconnected source terminals. The connection of the gate and drain terminals of the transistor MP 3  forms a voltage node Vb. The connection of the gate and drain terminals of the transistor MP 4  forms a voltage node Va. 
         [0009]    The source terminal of the transistor MP 3  is also connected to the source terminal of another P-channel MOS transistor MP 2 . The source terminal of the transistor MP 4  is connected to the source terminal of a P-channel MOS transistor MP 5 . Thus the source terminals of all the transistors MP 2 -MP 5  are interconnected. The transistor pairs MP 2  and MP 6 , and MP 5  and MP 7  form current mirror stages associated with each of the two parallel branches formed by the transistors MN 0  and MN 3 ; and MP 4  and MN 1 , respectively. Each current mirror stage is amplifies the signal output from each of the branches by a factor depending on the actual physical size of the transistors MP 2  and MP 6 , and MP 5  and MP 7 . 
         [0010]    The drain terminal of the transistor MP 2  is interconnected with the drain terminal of an N-channel MOS transistor MN 6 . The drain terminal of the transistor MP 5  is connected to the drain terminal of another N-channel MOS transistor MN 7 . The transistor pairs MP 2  and MP 3 , MP 4  and MP 5 , and MN 6  and MN 7 , respectively have interconnected gate terminals. There is also an interconnection between the gate terminal and the drain terminal of the transistor MN 6 . The gate terminals of the transistors MN 0  and MN 1  receive respective input voltage signals Inm and Inp. 
         [0011]    A current source Ib is connected between a node interconnecting the source terminals of the transistors MN 0  and MN 1  and a node interconnecting the source terminals of the transistors MN 6  and MN 7  so that the two parallel circuit branches have a common tail current source. A current source I 1  is connected to the node Vb interconnecting the gate and drain terminals of the transistor MP 3 , the drain terminal of the transistor MN 0  and the gate terminal of the transistor MP 2 . The current source I 1  is also connected to the node interconnecting the source terminals of the transistors MN 6  and MN 7 . A current source  12  is connected to the node Va interconnecting the source terminals of the transistors MN 6  and MN 7  and a node interconnecting the gate and drain terminals of the transistor MP 4 , the drain terminal of the transistor MN 1  and the gate terminal of the transistor MP 5 . The current sources I 1  and I 2  provide respective bias currents to the nodes Vb and Va. The output node Out of the driver is provided at a node interconnecting the drain terminals of the transistors MP 5  and MN 7 . Thus the current mirror stage comprising the transistors MP 5  and MN 7  is a single-ended output stage. An interconnection of the gate and drain terminals of the transistor MN 6  forms a voltage node Vc. 
         [0012]    In operation, differential input signals Inp and Inm are applied to the respective gates of the transistors MN 0  and MN 1 . These input signals are illustrated in  FIG. 2 . The voltage node Vb is biased by the current source I 1  and the voltage node Va is biased by the current source  12 . The bias currents I 1  and I 2  cancel each other at the output so that they introduce no error to the output signal. The averaged output current from the driver then depends on the duty cycle of the input signals Inm and Inp. 
         [0013]    The voltage nodes Va, Vb and Vc do not discharge fully when the input signals Inm and Inp to the corresponding transistors MN 0  and MN 1  are switched from high to low due to the current sources I 1  and I 2 . Therefore the charge pump driver has a reduced switching delay. For example, if the input signal Inm applied to the gate of the transistor MN 0  is at its maximum value and then switches to zero for the next cycle, this causes a large change in voltage of the voltage node Vb because the transistor MP 3  discharges completely. This introduces a large delay because the voltage node Vb must be fully charged again when the input signal Inm switches back to high. However, because the node Vb is permanently charged via current source I 1 , the time required to charge the node Vb to its maximum voltage is reduced. 
         [0014]    Furthermore, the presence of the current sources I 1  and I 2  means that the current generated by the current source Ib can be lower, while still keeping the switching time of the driver constant. 
         [0015]    Although the present invention has been described with reference to a specific embodiment, it is not limited to this embodiment and no doubt further alternatives will occur to the skilled person that lie within the scope of the invention as claimed.