Abstract:
A method and apparatus for charge addressing a non-volatile MNOS memory cell in a LSI array of memory cells, is disclosed. Each MNOS cell of the array is made up of a substrate; adjacent diffusion areas in the substrate; a memory window intermediate the adjacent diffusion areas, controlled by a memory gate; and an enable gate adjacent the memory window and overlapping one of the diffusion areas. The memory gate and the enable gate are each separated from the substrate and each other by silicon dioxide/silicon nitride layers to provide a capacitive dielectric. Addressing of an individual cell in the array is achieved by selective activation of a corresponding enable gate and a corresponding memory gate, which are formed in an orthogonal grid array. The cell is accessed by a single stage of a shift register for both read and write operations through a transfer gating means.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an improved method and apparatus for selectively charge addressing individual MNOS memory cells of an MNOS transistor array. 
     2. State of the Prior Art 
     In the prior art, conventional single gate MNOS memory cells are employed and individually read by use of a current-sense flip-flop circuit, as is typically shown in FIG. 1. The flip-flop circuit 10 is conventional and, for illustration purposes, comprises transistors 1, 3, 5 and 7. The flip-flop circuit 10 is initially set so that both sides are at substrate voltage V s  by an initiate signal I s  applied to transistors 3 and 5, turning them on. When the MNOS cell 2 is to be read, the transistors 3 and 5 are turned off by the initiate signal I s  and the flip-flop circuit 10 enters a &#34;race&#34; condition to determine which side of the flip-flop circuit 10 will first provide the current sufficiently large to set the opposite side in a &#34;1&#34; state. A reference transistor 4, having its gate connected to a reference voltage V D , is connected to one side of the flip-flop circuit. The other side of the flip-flop circuit is connected to the MNOS memory cell while a read voltage V M  is applied thereto. Thus, the memory cell current competes with the reference transistor current. A transfer signal applied to a transfer gate 6 provides access to a stage of a parallel-in shift register 15. The sensing of the MNOS cell 2 against the reference transistor 4 is performed in the source-follower mode, which is characterized by a relatively slow decision speed. The operation of the prior art circuit shown in FIG. 1 is critically dependent upon the adjustment of the &#34;current window&#34; which may be controlled by an adjustment of the reference signal voltage V D . Unfortunately, the required reference signal voltage may be different for each memory cell and a single reference supply is often not sufficient to similarly adjust the &#34;current window&#34; across a large array of memory cells. 
     In addition to the problems recited above, a more serious problem is encountered when high density arrays are required. In general, as the memory array size and cell density increases, the dimensions of the memory cell decreases and the drive current capacity of the memory cell becomes smaller, thereby increasing the time required to charge the capacitance C of the columns. Therefore, the prior art technique shown in FIG. 1, for reading a memory cell, has an access time to first bit which increases as the memory array size increases or the memory cell size decreases. It is seen as a near impossibility to implement the prior art memory array and read out system on a LSI chip of 16K bit or greater, since the flip-flop circuits must be placed on the pitch of the memory array. 
     SUMMARY OF THE INVENTION 
     In attempting to overcome the problems of the prior art readout techniques for LSI MNOS memory arrays, wherein high density (&gt;16K bits) require memory cell sites &lt;0.5mil 2  /bit, and preferably &lt;0.25mil 2  /bit, the present invention was discovered. The present invention employs a high density array of MNOS transistor cells which are each characterized by a single diffusion region and a plurality of control gates. Each memory cell is also characterized as being in a high threshold state or a low threshold state. The memory cells are selectively addressed for either read or write operations directly from a parallel-in shift register which may be a conventional Dynamic Ratioless type. A plurality of clockpulse phases are employed to shift data in the parallel-in shift register and also to provide for multiple shift register access to the memory array. 
     It is an object of the present invention to provide a novel MNOS memory array which provides for high density packing. 
     It is another object of the present invention to eliminate the conventional flip-flop detection circuitry used to sense current flow in a MNOS memory cell. 
     It is still another object of the present invention to provide a novel method of addressing an MNOS memory cell in a high density array. 
     It is a further object of the present invention to provide a novel method of reading the threshold level of addressed memory cells in a high density LSI array. 
     It is a still further object of the present invention to reduce the number of geometric entities employed to produce a high density array of memory cells. 
     It is a still further object of the present invention to provide an array of MNOS memory cells, each of which utilize diffusion regions common to other memory cells. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a prior art method of addressing a single gate MNOS memory cell by use of a current-sensing flip-flop circuit. 
     FIG. 2 is a circuit diagram indicating a method of charge addressing a MNOS memory transistor of the present invention. 
     FIG. 3A is a cross-sectional view of a single MNOS memory cell of the memory cell array employed in the present invention. 
     FIG. 3B is a top view of the single MNOS memory cell shown in FIG. 3A. 
     FIG. 4 is a detailed circuit diagram illustrating the charge addressing techniques employed in the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     A method of charge addressing a MNOS memory cell of the present invention is illustrated in the circuit diagram of FIG. 2. In this method, the multigated MNOS memory cell 12 is &#34;read&#34; after the column capacitance C is charged to a specific reference voltage V R . Then, after the column capacitance C is preset, &#34;read&#34; signals are applied to the address gates of the memory cell 12. The memory cell 12, which has been addressed with &#34;read&#34; signals will cause the charge stored in the capacitor C to discharge, from the drain to the source, if the memory cell is in a low threshold state. Alternatively, if the addressed memory cell 12 is in a high threshold state, the charge V C  stored in the capacitor C will be maintained since no discharge will occur from the drain to the source. Subsequently, the transfer switch 16 is addressed and the remaining charge stored in the capacitor C is sensed in the shift register 15, to thereby read the threshold state of the memory cell 12. It has been found in the read mode, that the discharge of the capacitor C through the memory cell 12 occurs more rapidly when the memory cell is in the drain follower configuration, as is shown in FIG. 2, than in the source follower configuration. 
     The above method of addressing a MNOS memory cell transistor is a significant improvement over the prior art, since it eliminates the flip-flop circuitry employed by the prior art and increases the achievable density due to the array layout of the MNOS cells, discussed below. 
     FIGS. 3A and 3B illustrate a single MNOS transistor memory cell of an array of such cells, similar to those in commonly assigned copending U.S. Pat. application Ser. No. 653,849, filed on Jan. 30, 1976, entitled ADDRESSABLE MNOS CELL FOR NON-VOLATILE MEMORIES. 
     The principle features of a unit cell are given by example as a single channel of 4μm wide P+ diffusion region per memory column, a 6μm wide polysilicon enable gate, and a 10μm wide memory gate controlling a 4μm wide memory window offset from the P+ diffusion. 
     The array of MNOS transistors are formed on a substrate 32, which is of a material having a given conductivity type of, for example, N-type Si. Columns of diffusion regions of the opposite conductivity type, for example, P+ are formed on the substrate 32 and indicated as 44, 54, . . . , etc. Polysilicon enable gates 45, 55, . . . , etc., parallel and corresponding to each diffusion area are formed above the substrate 32 separated by a dielectric material. Each enable gate overlaps the corresponding diffusion area and an adjoining portion of the surface of the substrate 32. Aluminum memory gates 33, 43, . . . , etc. extend orthogonally to the diffusion areas and the polysilicon gates, controlling memory windows mW defined between each diffusion area, wherein the intersections of said aluminum memory gates and said memory windows define a non-volatile discrete charge storage site at each occurrance. 
     A single transistor cell, as shown in FIG. 3A, of the array shown in FIG. 3B is defined by two adjacent diffusion areas 44 and 54, which are each common to other cells, in the same and adjoining columns; a memory window mW, controlled by a specific memory gate 43, which is common to other cells along that column; and a polysilicon enable gate 45, corresponding to the selected diffusion region 44 and overlapping in the direction of the selected memory window. The enable gate 45 is also common to other cells in the same column. In the example shown in FIG. 3A, diffusion region 54 is designated as the drain and diffusion region 44 is designated as the source, while the intersecting memory gate 43 controls a memory window mW between the respective drain and source. It should be understood that the roles of the diffusion areas may be interchanged as operations require. 
     The MNOS memory cell shown in FIGS. 2, 3A and 3B is capable of either high or low threshold states, and may enter the high threshold state during the &#34;write&#34; operation. In the illustrated example, during the &#34;write&#34; operation, the diffusion 44 is disabled by the polysilicon enable gate 45 at substrate voltage and a &#34;write&#34; voltage of -25 volts is applied to memory gate 43 creating a depletion region beneath the memory window mW. Data from the shift register is transferred to the diffusion 54 upon the command of a transfer signal. If the data is high (substrate voltage), minority charge is injected into the depletion region created in the substrate at the memory window. The depletion region therefore collapses to substrate voltage and the entire &#34;write&#34; voltage is dissipated across the dielectric at the memory window and charge tunneling occurs. The resulting charge storage in the dielectric leaves the cell in a high threshold state where V T  ≃ -10 volts. 
     Alternatively, if the write data from the shift register is low in a range of approximately -15V to -25V, there is no charge injection and the &#34;write&#34; voltage is dissipated over the depletion region. Therefore, when the data is low, no tunneling occurs and the cell remains in a low threshold state where V T  ≃ -2 volts. 
     FIG. 4 shows a schematic diagram of a single stage of respective parallel shift registers 15 and 15&#39;, which are used to read and write data with respect to the correspondingly addressed MNOS memory cells. Since each of the shift registers 15 and 15&#39; are identical, only the operation of the register 15 stage will be explained in detail. 
     Clock pulses φ1 and φ2 are used to shift data in the shift register 15, (clock pulses φ3 and φ4 are used in shift register 15&#39;) which comprises a transfer gate and an inverter corresponding to φ1 and a transfer gate and inverter corresponding to φ2, for each shift stage. During the time data is being shifted into the shift register 15, transfer gates TA and TB are disabled, thereby preventing unwanted communication between the shift register and the memory array. In this embodiment, when the φ1 clock pulse goes from a zero level first state to a negative level second state, data at the input mode D IN  is transferred to a node &#34;a&#34; through a transfer device T1. A varactor V is provided in the shift register 15, since it acts to enhance negative data at the input node D IN  and counter-balances the charge sharing that occurs between the input node D IN  and the node &#34;a&#34;. Simultaneously, a node &#34;b&#34; is charged to said negative state under the influence of the negative clock pulse φ1. The node &#34;b&#34; takes on the state of the clock pulse φ1, since φ1 turns on the transfer device T3. Clock pulse φ1 then goes to the zero level state, turning off transfer device T1 and thereby isolating node &#34;a&#34; from the input node D IN . If the node &#34;a&#34; is negative, the transfer device T2 is on and causes the node &#34;b&#34; to discharge after clock pulse φ1 goes to the zero state. However, if node &#34;a&#34; is positive, transfer device T2 is off and node &#34;b&#34; remains negatively charged. Therefore, it can be seen that a single φ1 clock pulse causes the data to be transferred and inverted from the input node D IN  to node &#34;b&#34;. A second clock pulse φ2 causes the data stored at node &#34;b&#34; to be transferred to a subsequent node in identical fashion to that recited above. Data is then continually shifted along the shift register 15 for a predetermined number of clock pulses as is desired for a particular operation. 
     The capacitance associated with node a is comprised of diffusion capacitance of the transistor T1, the gate capacitance of interconnection capacitance for the aluminum connection between T1 and T2. No additional capacitance is needed for operation since node a is a high impedance node when T1 transistor is not conducting. The only mechanism for losing charge (and thereby signal voltage) from node a is the reverse biased leakage current of the T1 diffusion. With proper processing, node a will hold sufficient charge for operation for several seconds at 25° C. Node b operates in similar fashion, having the capacitance of 5 transistor diffusions, the varactor gate, and necessary interconnections. Other nodes in the circuit, for example, the p+ diffusions 54, 44, 34, and 24 are also operated in a manner which uses their inherent capacitance as a means of storing a signal voltage. 
     During a &#34;write&#34; operation, data enters the shift register 15 and is shifted to a desired position in the shift register by a predetermined number of clock pulses. On the negative transistion of the final φ1 clock pulse, a selected transfer gate, for example, TA is switched on by a transfer command signal. The effect of the clock pulse φ1 in the negative state, causes the correspondingly selected P+ diffusion region 54 to be charged negatively along with node &#34;b&#34;. When final φ1 clock pulse returns positive, the data polarity at node &#34;a&#34; determines whether the P+ diffusion region 54 remains negatively charged or whether it will be returned positive along with node &#34;b&#34;. After the clock pulse φ1 returns positive, a selected memory gate such as 43, is addressed with a &#34;write&#34; voltage of approximately -25 volts with all read/enable gates turned off. If the data applied to the P+ diffusion 54 from node &#34;b&#34; is at zero volts (positive with respect to said write voltage), the depletion region under the memory gate 43, corresponding to the memory window mW, is injected with minority carriers, thereby collapsing the surface potential at the memory window to 0V. The negative voltage applied to the memory gate as the &#34;write&#34; signal, causes charge tunneling to occur across the dielectric, thereby leaving the selected cell in a high threshold state. 
     If the diffusion region 54 is negative, corresponding to the node &#34;b&#34;, minority carriers are not injected and the memory gate voltage is dissipated across the depletion region, thereby inhibiting tunneling and leaving said memory cell in a low threshold state. 
     It should be evident from the above, that for the &#34;write&#34; operation, the memory cell is not employed as a conventional MNOS transistor, since only a single diffusion area is used. 
     A &#34;read&#34; operation is performed on the selectively addressed memory cells by, for example, negatively precharging the capacitive node &#34;b&#34; and the selected P+ diffusion 54 through actuated transfer gate TA. The lower shift register 15&#39; simultaneously sets the adjacent P+ diffusion 44 to 0 volts (substrate voltage) through transfer gate TA&#39;. A &#34;read&#34; voltage is applied to the selected memory gate 43. The &#34;read&#34; voltage has a value intermediate of the high and low threshold values of the memory. Generally, a high threshold has a value of approximately -10V and a low threshold has a value of apprximately -2V, while the read voltage is selected to have a value of approximately -6V. An appropriate enable gate is similarly activated (in this case, polygate 45) with a voltage more negative than the low threshold voltage and the charge at node &#34;b&#34; is either maintained at its initial level or is discharged to 0V (substrate voltage), depending upon the threshold state of the selected memory cell. 
     If a given memory cell is in its low threshold state, during the above &#34;read&#34; operation the memory transistor is ON and the data node &#34;b&#34; is discharged to 0 volts. Correspondingly, if the memory threshold is in its high state, the data node &#34;b&#34; remains charged negative. The threshold state of selectively addressed memory cells in a memory array are therefore rapidly and precisely read into the shift register without disturbing the threshold state of the address cell. 
     It will be apparent that many modifications and variations of the above favored embodiment may be effected without departing from the scope of the novel concept of this invention. Therefore, it is intended by the appended claims to cover all such modifications and variations which fall within the true spirit and scope of the invention.