Abstract:
A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.

Description:
FIELD OF THE INVENTION 
     The present invention relates to the addition of multiple ports to a hierarchical multi-bank structure to multiply the available cyclic random bandwidth. 
     RELATED ART 
     Prior art has introduced the concept of multiple ports in static random access memory (SRAM) technology to increase the available random bandwidth of a memory system. Multiple ports increase the available transaction generation frequency by the number of ports. However, there is enormous area overhead due to the required use of a multi-port SRAM bit cell. 
       FIG. 1  is a block diagram of a conventional multi-port SRAM  100 , which includes memory cell array  101  and three separate access ports  111 - 113 . Memory cell array  101  is made of a plurality of 3-port SRAM cells. The multi-port nature of the SRAM cells in array  101  allows simultaneous accesses to be performed on each of the three access ports  111 - 113 . For example, a first read access can be performed on access port  111 , a second read access can be simultaneously performed on access port  112 , and a write access can be simultaneously performed on access port  113 . The 3-port SRAM cells of array  101  are much larger than a conventional single port SRAM cell. The large size of the 3-port SRAM cells restricts the usage of multi-port SRAM  100  to small memory instances (typically embedded memory). It would therefore be desirable to have an improved multi-port memory system. 
     SUMMARY 
     The present invention introduces a memory system that includes a plurality of memory banks, each having multiple ports. Each of the memory banks includes a corresponding memory array, which is single port in nature. That is, the individual memory arrays are made of single-port memory cells. These single-port memory cells can be, for example, dynamic random access memory (DRAM) cells, embedded DRAM (EDRAM) cells, or flash memory cells. 
     Simultaneous accesses may be performed on all of the multiple ports at the top (chip) level. However, none of these simultaneous accesses may address the same individual memory bank. Each of the individual memory banks may be accessed from any one of the multiple ports. However, each of the individual memory banks is only accessed from (at most) one of the multiple ports during any given access cycle. In one embodiment, a multiplexer structure within each memory bank couples the corresponding memory array to each of the multiple ports. 
     In one embodiment, the multi-bank multi-port memory system can be expanded to include an additional level of hierarchy (i.e., partitions), which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. All ports at the partition level may be simultaneously accessed. In this embodiment, the number of concurrent accesses per cycle equals the number of partitions times the number of ports. For example, in a memory system having three ports and four partitions, the cyclic random bandwidth is multiplied by 12, while the area overhead is increased by less than five percent, compared to a single port memory structure. 
     The present invention will be more fully understood in view of the following description and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a conventional three-port memory system, which includes an array of three-port memory cells. 
         FIG. 2  is a block diagram of a multi-port multi-bank memory system in accordance with one embodiment of the present invention. 
         FIG. 3  is a block diagram illustrating a memory bank of the multi-port multi-bank memory system of  FIG. 2 , in accordance with one embodiment of the present invention. 
         FIG. 4  is a block diagram of a memory system that includes four memory partitions, in accordance with another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a block diagram of a multi-port multi-bank memory system  200  in accordance with one embodiment of the present invention. Memory system  200  includes four memory banks B 00 -B 03  and three access ports P 1 -P 3 . Although memory system  200  includes four memory banks and three access ports, it is understood that memory system  200  can include other numbers of memory banks and other numbers of ports, as long as the number of memory banks is greater than or equal to the number of ports. 
     In the embodiment illustrated by  FIG. 2 , ports P 1  and P 2  are read ports, and port P 3  is a write port. The first read port P 1  includes a first read address bus RA_ 01  and a first read data bus RD_ 01 . The second read port P 2  includes a second read address bus RA_ 02  and a second read data bus RD_ 02 . The write port P 3  includes a write address bus WA_ 0  and a write data bus WD_ 0 . 
     Each of the memory banks B 00 -B 03  is coupled to each of the three ports P 1 -P 3 . More specifically, each memory bank B XX  includes a first read port P 1   XX  (which is coupled to port P 1 ), a second read port P 2   XX  (which is coupled to port P 2 ) and a write port P 3   XX  (which is coupled to port P 3 ), wherein XX=00, 01, 02 and 03. 
     The first read address bus RA_ 01  provides read addresses to the first read ports P 1   00 , P 1   01 , P 1   02  and P 1   03 , through bus connections labeled A 1 . The first read data bus RD_ 01  receives read data values from the first read ports P 1   00 , P 1   01 , P 1   02  and P 1   03 , through bus connections labeled R 1 . 
     The second read address bus RA_ 02  provides read addresses to the second read ports P 2   00 , P 2   01 , P 2   02  and P 2   03 , through bus connections labeled A 2 . The second read data bus RD_ 01  receives read data values from the second read ports P 2   00 , P 2   01 , P 2   02  and P 2   03 , through bus connections labeled R 2 . 
     The write address bus WA_ 0  provides write addresses to the write ports P 3   00 , P 3   01 , P 3   02  and P 3   03 , through bus connections labeled WA. The write data bus WD_ 0  provides write data values to write ports P 3   00 , P 3   01 , P 3   02  and P 3   03 , through bus connections labeled WD. 
     An external device (or devices) may initiate accesses to memory system  200  in the following manner. Accesses may be simultaneously initiated on ports P 1 , P 2  and/or P 3 , as long as none of these simultaneous accesses specify the same memory bank. For example, a read access on port P 1  may access memory bank B 00  at the same time that a read access on port P 2  accesses memory bank B 02 , and a write access on port P 3  accesses memory bank B 03 . Because each of the memory banks B 00 -B 03  is accessed by, at most, one of the ports P 1 -P 3  at any given time, the memory banks B 00 -B 03  can be implemented using single-port memory cells. The internal structure of memory banks B 00 -B 03  is described in more detail below. 
       FIG. 3  is a block diagram illustrating memory bank B 00  in more detail, in accordance with one embodiment of the present invention. Memory banks B 01 , B 02  and B 03  are identical to memory bank B 00  in the described embodiments. Memory bank B 00  includes multiplexer  201 , de-multiplexer  202 , access control logic  205 , and memory array M 00 . Memory array M 00  includes an array of single-port memory cells. These single-port memory cells can be, for example, dynamic random access memory (DRAM) cells, static random access memory (SRAM) cells, embedded DRAM (EDRAM) cells, or flash memory cells. Multiplexer  201  and access control logic  205  are coupled to receive the read address on the first read address bus RA_ 01  (via bus connections A 1 ), the read address on the second read address bus RA_ 02  (via bus connections A 2 ), and the write address on the write address bus WA_ 0  (via bus connections WA). Each of these received addresses includes a bank address (which specifies one of the memory banks B 00 -B 03 ) and a local address (which specifies a row/column location within the memory array of the memory bank). Access control logic  205  determines whether one of the received read addresses or the received write address includes a bank address that specifies the memory bank B 00 . In one embodiment, memory bank B 00  is assigned a unique address, and access control logic  205  compares the bank addresses received on buses RA_ 01 , RA_ 02  and WA_ 0  with this unique address to determine whether memory bank B 00  is specified for an access. During any given access cycle, only one (or none) of the buses RA_ 01 , RA_ 02  and WA_ 0  will carry a bank address that specifies memory bank B 00 . 
     If access control logic  205  determines that one of the buses RA_ 01 , RA_ 02  and WA_ 0  carries a bank address that specifies memory bank B 00 , then access control logic  205  will cause multiplexer  201  to route the associated local (row/column) address to memory array M 00 , as the array address signal ADR 00 . For example, if access control logic  205  detects that the bank address on read address bus RA_ 01  specifies memory bank B 00 , then access control logic  205  will cause multiplexer  201  to route the local (row/column) address from read address bus RA_ 01  to single-port memory array M 00 . 
     Access control logic  205  also generates a read/write access control signal (R/W) in response to the received addresses. If access control logic  205  determines that a matching bank address is received on one of the read address buses RA_ 01  or RA_ 02 , then access control logic  205  generates a R/W access control signal that specifies a read operation. If access control logic  205  determines that a matching bank address was received on the write address bus WA_ 0 , then access control logic  205  generates a R/W access control signal that specifies a write operation. If access control logic  205  determines that no matching bank address was received on address buses RA_ 01 , RA_ 02  or WA_ 0 , then access control logic  205  generates a R/W access control signal that specifies an idle cycle (no operation). 
     If the R/W control signal indicates that a matching bank address was received on one of the read address buses RA_ 01  or RA_ 02 , then memory array M 00  performs a read operation to the address location specified by the array address ADR 00 . The resulting read data value DOUT 00  is provided from memory array M 00  to de-multiplexer  202 . Access control logic  205  causes de-multiplexer  202  to route the read data value DOUT 00  to the read data bus associated with the read access. For example, if the matching bank address was received on the first read address bus RA_ 01  (i.e., port P 1 ), then de-multiplexer  202  routes the read data value DOUT 00  to the first read data bus RD_ 01  (i.e., port P 1 ). Conversely, if the matching bank address was received on the second read address bus RA_ 02  (i.e., port P 2 ), then de-multiplexer  202  routes the read data value DOUT 00  to the second read data bus RD_ 02  (i.e., port P 2 ). 
     If the R/W control signal indicates that a matching bank address was received on the write address bus WA_ 0 , then memory array M 00  performs a write operation, whereby the write data value on write data bus WD_ 0  (i.e., DIN 00 ) is written to the address location specified by the array address ADR 00 . 
     Assuming that each of the memory banks B 00 -B 03  operates at a frequency F, then memory system  200  may operate at a maximum frequency of 3×F. That is, two read operations may be simultaneously performed at frequency F on ports P 1  and P 2 , while one write operation is simultaneously performed at frequency F on port P 3 . 
       FIG. 4  is a block diagram of a memory system  400  that includes four memory partitions MP 0 -MP 3 , in accordance with another embodiment of the present invention. In the described embodiment, memory partition MP 0  is identical to memory system  200  ( FIGS. 2-3 ). Thus, memory partition MP 0  includes memory banks B 00 -B 03  and ports P 1 -P 3 , as described above. Memory partitions MP 1 -MP 3  are identical to memory partition MP o . Memory partitions MP 1 , MP 2  and MP 3  include memory banks B 10 -B 13 , B 20 -B 23  and B 30 -B 33 , respectively, and ports P 4 -P 6 , P 7 -P 9  and P 10 -P 12 , respectively. Memory banks B 10 -B 13 , B 20 -B 23  and B 30 -B 33  are identical to memory banks B 00 -B 03 . Ports P 4 -P 5 , P 7 -P 8  and P 10 -P 11  are read ports, similar to read ports P 1 -P 2 . Ports P 6 , P 9  and P 12  are write ports, similar to write port P 3 . 
     Up to eight read operations and four write operations may be performed simultaneously within memory system  400 . More specifically, eight read operations may be initiated by providing read addresses on the read address buses RA_ 01 , RA_ 02 , RA_ 11 , RA_ 12 , RA_ 21 , RA_ 22 , RA_ 31  and RA_ 32  of ports P 1 , P 2 , P 4 , P 5 , P 7 , P 8 , P 10  and P 11 , respectively. Each of these read operations must specify different memory banks within the corresponding memory partitions. In response, eight read data values are provided on read data buses RD_ 01 , RD_ 02 , RD_ 11 , RD_ 12 , RD_ 21 , RD_ 22 , RD_ 31  and RD_ 32  of ports P 1 , P 2 , P 4 , P 5 , P 7 , P 8 , P 10  and P 11 , respectively. 
     Similarly, four write operations may be initiated by providing write addresses on the write address buses WA_ 0 , WA_ 1 , WA_ 2  and WA_ 3  of ports P 3 , P 6 , P 9  and P 12 , respectively, and providing write data values on the write data buses WD_ 0 , WD_ 1 , WD_ 2  and WD_ 3  of ports P 3 , P 6 , P 9  and P 12 , respectively. 
     The use of memory partitions MP 0 -MP 3  in memory system  400  adds an additional level of hierarchy to the structure of memory system  200 , thereby allowing for multiplication of the number of simultaneously accessible ports, with minimal area overhead. The additional area overhead associated with memory system  400  is less than 5 percent, when compared with a conventional single-ported memory structure having the same capacity. 
     The maximum operating frequency of memory system  400  is equal to the operating frequency of the memory banks times the number of ports per memory partition, times the number of memory partitions. Assuming that each of the memory banks of memory system  400  operates at a frequency F, then memory system  400  may operate at a maximum frequency of 3×4×F. That is, eight read operations may be simultaneously performed at frequency F on ports P 1 , P 2 , P 4 , P 5 , P 7 , P 8 , P 10  and P 11 , while four write operations are simultaneously performed at frequency F on ports P 3 , P 6 , P 9  and P 12 . 
     Although memory system  400  includes four memory partitions, with three ports per memory partition, it is understood that memory system  400  can include other numbers of memory partitions, having other numbers of ports per memory partition, in other embodiments. 
     Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Accordingly, the present invention is limited only by the following claims.