Abstract:
A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to memory systems, and more particularly, to systems and methods for coupling command, address and data signals between a memory controller and one or more memory devices.  
       BACKGROUND OF THE INVENTION  
       [0002]     Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These DRAM devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The system memory is typically arranged in memory modules each having multiple memory devices, and the memory modules are coupled through a memory bus to the memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read or to which data or instructions are to be written. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory through the memory bus. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.  
         [0003]     A high data bandwidth is a desirable capability of memory systems. Generally, bandwidth limitations are not related to the memory controllers since the memory controllers sequence data to and from the system memory as fast as the memory devices allow. One approach to increasing bandwidth is to increase the speed of the memory data bus coupling the memory controller to the memory devices. However, memory devices have not been able to keep up with increases in the data bandwidth of memory controllers and memory data buses. In particular, the memory controller must schedule all memory commands to the memory devices in a manner that allows the memory devices to respond to the commands. Although these hardware limitations can be reduced to some degree through the design of the memory device, a compromise must be made because reducing the hardware limitations typically adds cost, power, and/or size to the memory devices, all of which are undesirable alternatives. While memory devices can rapidly handle “well-behaved” accesses at ever increasing rates, for example, sequel traffic to the same page of a memory device, it is much more difficult for the memory devices to resolve “badly-behaved traffic,” such as accesses to different pages or banks of the memory device. As a result, the increase in memory data bus bandwidth does not result in a corresponding increase in the bandwidth of the memory system.  
         [0004]     In addition to the limited bandwidth of memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data cannot be output from the SDRAM device until a delay of several clock periods has occurred. Although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices. These latency issues generally cannot by alleviated to any significant extent by simply increasing the memory data bus bandwidth.  
         [0005]     The memory latency problem is greatly exacerbated by read accesses alternating with write accesses, a situation known as “read/write turnarounds.” When a memory controller issues a read command to a memory device, the memory device must couple read data from a memory array to external data bus terminals of the memory device. The read data must then be coupled through a data bus portion of the memory bus from the memory device to the memory controller. It is only then that the memory controller can couple write data to the memory device through the data bus to initiate a write memory access.  
         [0006]     Latency problems also exist for sequentially read command directed to different pages of memory cells in memory devices. If a second read is directed to a different page, the page to which the read is directed will not be an “open” page, i.e., a row of memory cells from which data was read during the previous memory access. If the row to which the read access is directed is not already open, data cannot be coupled from a memory array to the data bus terminals of the memory device until the page has been opened. Opening the page requires the coupling of memory command and a row address and a column address from the memory controller to the memory device. In response to the read address, the memory device must equilibrate the corresponding row, turn on access transistors for that row, and allow a sense amplifier for each column to sense the voltage that a respective memory cells couples to the sense amplifier. All of this can take a considerable period of time. For this reason, a read operations from a closed page and read/write turnarounds can prevent memory devices from even coming close to achieving the data bandwidths that are possible with high speed memory controllers and memory buses.  
         [0007]     There is therefore a need for a memory device and memory system that allows a higher data bandwidth to be achieved particularly in the presence of alternating read and write accesses.  
       SUMMARY OF THE INVENTION  
       [0008]     A memory system is able to achieve a high bandwidth and low latency through the use of two separate data buses coupling a memory controller to one or more memory device. A downstream bus couples write data from the memory controller to each memory device, and an upstream bus couples read data from each memory device to the memory controller. As a result, read data can be coupled from each memory device to the memory controller at the same time that write data can be coupled from the memory controller to each memory device. A single downstream memory bus may be used to couple memory commands and memory addresses to each memory device along with write data. Each memory device can include a write buffer that allows memory commands and addresses and write data for several write access to be accumulated while read requests are processed. After a number of write accesses have been accumulated, they can be processed in a burst manner without any intervening read accesses. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  is a block diagram of a memory system according to one embodiment of the invention.  
         [0010]      FIG. 2  is a block diagram of a dynamic random access memory devices used in the memory system of  FIG. 1 .  
         [0011]      FIG. 3  is a block diagram of a computer system using the memory system of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION  
       [0012]     A memory system  10  according to one embodiment of the invention is illustrated in  FIG. 1 . The memory system  10  includes a memory controller  14  coupled to the four dynamic random access memory (“DRAM”) devices  20 ,  22 ,  24 ,  26 . The memory controller  14  is coupled to each of the DRAM devices  20 - 26  by an 8-bit write data bus  30  and an 8-bit read data bus  32 . The memory controller  14  couples memory commands and memory addresses “downstream” to the DRAM devices  20 - 26  through either the write data bus  30 , a separate command/address bus (not shown) or separate command and address buses (not shown). If the memory commands and memory addresses are coupled through the downstream bus, the commands and addresses may be in the form of a packet, which, for write commands, may also include write data.  
         [0013]     In operation, the memory controller  14  couples write data “downstream” to the DRAM devices  20 - 26  through the write data bus  30 , and the DRAM devices  20 - 26  couple read data “upstream” to the memory controller  14  through the read data bus  32 . The bandwidth of the write data bus  30  may be the same as the bandwidth of the read data bus  32 . Alternatively, the write data bus  30  and the read data bus  32  may have different bandwidths to accommodate different data rates though the buses  30 ,  32 . In the event the DRAM devices  20 - 26  are synchronous DRAM (“SDRAM”) devices, the memory controller  14  also couples a clock signal to each of the DRAM devices  20 - 26 . By using separate write and read data buses  30 ,  32 , respectively, the memory controller  14  can couple write data to the DRAM devices  20 - 26  at the same time that the memory devices  20 - 26  are coupling read to the memory controller  14 .  
         [0014]     The DRAM devices  20 - 26  are shown in greater detail in  FIG. 2 . Each of the DRAM devices  20 - 26  includes eight memory banks  40   a - h  each of which are coupled to a common write data bus  42  and a common read data bus  44 . The write data bus  42  receives write data from a write buffer  46 , and the read data bus  44  couples read data to a read latch  50 . Write data is coupled to the write buffer  46  through a write data bus  52  and is latched into the buffer  46  by a clock signal coupled through line  54 . Memory commands and addresses are also coupled through the write data bus  52 , and they are stored in a command/address register  58 .  
         [0015]     The read latch  50  outputs read data on an 8-bit read data bus  60  in synchronism with a clock signal that is also coupled from the read latch  50  on line  62 . The memory devices  20 - 26  include a large number of other conventional memory device components, but these have been omitted from  FIG. 2  in the interest of brevity and clarity.  
         [0016]     In operation, memory commands, such as write commands and read commands, as well as memory addresses are coupled through the write data bus  52 . The memory commands and addresses are stored in the command/address register  58 . The write data also coupled through the write data bus  52  and stored in the write buffer  46 . In response to a read command coupled to the command/address register  58 , the memory devices  20 - 26  output read data, which are coupled to the read latch  50 . The read latch  50  stores the read data until the read data bus  60  and memory controller  14  ( FIG. 1 ) are able to receive the read data. The read data are then clocked out of the read latch  50  through the read data bus  60 . The read memory accesses are preferably given priority over write memory accesses so that a number of write commands and associated addresses are stored in the command/address register  58  while the write data are accumulated in the write buffer  46 . When a sufficient number of write accesses have been accumulated, they are processed sequentially without any intervening read accesses. As a result, the latency penalties inherent in read/write turnarounds are avoided. Although it is not possible for write data to be coupled to one of the banks  40   a - h  at the same time read data is being coupled from the same bank, it is possible for write data to be coupled to one of the banks  40   a - h  at the same time read data is being coupled from another of the banks  40   a - h  . Thus, by using separate write and read data buses  30 ,  32 , respectively, the memory controller  14  can couple write data to each of the DRAM devices  20 - 26  at the same time that the respective memory device  20 - 26  is coupling read data to the memory controller  14 . By allowing a read command to be coupled through the write data bus  52  and stored in the command/address register  58 , read commands can be coupled to the memory devices  20 - 26  during write or read operation. As a result, the latency for read operations is minimized. Otherwise, it would be necessary to wait for a write operation to be completed before a read command could be sent.  
         [0017]     In one embodiment of the invention, the memory controller  14  ( FIG. 1 ) simply issues read and write memory commands and addresses to the memory devices  20 - 26 . The memory commands are stored in the command/address register  58  until the memory devices  20 - 26  are able to process them. The commands are then processed by each of the memory devices  20 - 26 , and this processing includes coupling a read response or a write response to the controller through the read data bus  60 . The read responses and write responses indicate to the memory controller  14  that processing of a corresponding memory request has been completed. The responses uniquely identify the memory request corresponding to the response so that it is not necessary for the memory controller  14  to keep track of the memory requests, and the memory requests may be processed out-of-order. In the case of a read response, the read response may also include the read data resulting from the corresponding read request.  
         [0018]     A computer system  100  using the memory system  10  of  FIG. 1  is shown in  FIG. 3 . The computer system  100  includes a processor  102  for performing various computing functions, such as executing specific software for performing specific calculations or tasks. The processor  102  includes a processor bus  104  that normally includes an address bus, a control bus, and a data bus. The processor buss is coupled to an expansion bus  108 , such as a peripheral component interconnect (“PCI”) bus, through a system controller  110 . The computer system  100  includes one or more input devices  114 , such as a keyboard or a mouse, coupled to the processor  102  through the expansion bus  108 , system controller  110  and processor bus  104  to allow an operator to interface with the computer system  100 . Typically, the computer system  100  also includes one or more output devices  116  coupled to the expansion bus  108 , such output devices typically being a printer or a video terminal. One or more mass data storage devices  118  are also typically coupled to the expansion bus  108  to store data or retrieve data from external storage media (not shown). Examples of typical mass data storage devices  118  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  102  is also typically coupled to a cache memory  126 , which is usually static random access memory (“SRAM”). As mentioned above, the computer system  100  also includes the memory system  10  of  FIG. 1 . Specifically, the system controller  110  includes the memory controller  14 , which, as explained above with reference to  FIG. 1 , is coupled to several DRAM devices  20 - 26 . The memory controller  14  is coupled to each of the DRAM devices  20 - 26  through the write data bus  30  and the read data bus  32  as well as a command bus  130  and an address bus  134 .  
         [0019]     Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Such modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.