Abstract:
A disk drive system including a write circuit for controlling current through a magnetic write head includes an H-switch circuit and a charge-pumping circuit. The H-switch circuit controls direction of current through the magnetic write head. The charge-pumping circuit is connected to the H-switch circuit for storing energy during a first state of the H-switch circuit, and delivering energy upon switching from the first state to a second state of the H-switch circuit to accelerate a change in direction of current through the write head.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to a magnetizing current control circuit which operates with a magnetic recording head in a magnetic data storage and retrieval system. In particular, the present invention relates to a magnetizing current control circuit having a higher switching rate and reduced power dissipation.  
           [0002]    In magnetic data storage and retrieval systems, a magnetic recording head records two-logic-state data in a magnetic data storage medium such as a magnetic tape or magnetic disc. The magnetic recording head has an inductive coil with currents provided therethrough in alternate directions representing the data, to impart a series of alternate magnetic field patterns over time to the magnetic medium moving by it. Producing alternate magnetic field patterns over time entails switching the electric current through the inductive coil between forward and reverse directions therethrough to correspond to the data. Current in the inductive coil generates a magnetic field oriented in a direction corresponding to the direction of flow through the coil; thus, reversing the direction of current reverses the orientation of the magnetic field. The magnetic fields generated by the inductive coil currents intersect the magnetic medium to polarize adjacent magnetic medium regions which in effect serve as data symbol storage positions on the medium, and so form magnetic patterns along a corresponding one of more or less concentric tracks in the medium from which an information signal can be retrieved.  
           [0003]    Controlling the directions and magnitudes of currents through the inductive coil is the purpose of a magnetizing current control circuit. A typical magnetizing current control circuit includes a switching network and a signal coupler. The switching network is connected to the ends of the inductive coil in the magnetic recording head at first and second head nodes, and includes four switching transistors arranged as pairs with each pair member connected to a corresponding one of these head nodes. One pair is switched on directing current flow in one direction through the inductive coil with the other pair switched off and, alternatively, this latter pair is switched on to direct current flow through the inductive coil in the opposite direction with the first pair being switched off. More specifically, the switching transistors are connected to the inductive coil such that a first switching transistor is connected between a first voltage source node and the first head node, a second switching transistor is connected between the first voltage source node and the second head node, a third switching transistor is connected between the first head node and a second voltage source node, and a fourth switching transistor is connected between the second head node and the second voltage source node.  
           [0004]    One principal concern in the performance of magnetizing current control circuits is the duration of time needed to complete a switching of current direction through the inductive coil which directly affects the switching rate. Switching rate, a measure of how often the magnetizing current control circuit can reverse current direction through the inductive coil per unit of time, determines the maximum linear spatial density of data along a track in the magnetic medium. Ultimately, a higher switching rate yields denser data storage and thus greater total data capacity for a magnetic medium.  
           [0005]    A key determinant of the current reversal switching time duration is the head swing voltage, i.e. the voltage difference between the head nodes of the magnetizing current control circuit. The larger the voltage drop applied in the opposite direction across the inductive coil after a switching to reverse the current therethrough, the quicker the change in direction of current through the inductive coil. This is because the voltage-current characteristic of an inductive coil is determined by V=Ldi/dt+R L I, where V is the voltage across the inductive coil, di/dt is the rate of change of current over time through the inductive coil, L is the inductance of the inductive coil, R L  is the resistance of the inductive coil, and I is the current through the inductive coil. Because the inductance of the inductive coil is constant and the resistance of the inductive coil is relatively small, there is a direct relationship between the voltage impressed across the inductive coil after switching and the rate of change of current over time through the inductive coil.  
           [0006]    In typical magnetizing current control circuits using MOS switching transistors, the head swing voltage is equal to the voltage difference between the drains of the first and second switching transistors. In order to create a large voltage difference between the drains of the first and second switching transistors after a switching to reverse the current through the inductive coil, a larger voltage difference must be provided between the voltage source nodes. This, however, typically requires the magnetizing current control circuit to be operated by a continuous high supply voltage, which in turn causes the circuit to have high power consumption.  
           [0007]    Accordingly, there is a need for a magnetizing current control circuit that maximizes the head swing voltage while minimizing the power consumption of the circuit.  
         BRIEF SUMMARY OF THE INVENTION  
         [0008]    The present invention is a disk drive system including a write circuit for controlling current through a magnetic write head. An H-switch circuit controls direction of current through the magnetic write head. A charge-pumping circuit is connected to the H-switch circuit for storing energy during a first state of the H-switch circuit, and delivering energy upon switching from the first state to a second state of the H-switch circuit to accelerate a change in direction of current through the write head. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    [0009]FIG. 1 shows a circuit schematic diagram of a prior art magnetic write circuit.  
         [0010]    [0010]FIG. 2 shows a circuit schematic diagram of a magnetic write circuit embodying the present invention.  
         [0011]    [0011]FIG. 3 shows a timing diagram of a magnetic write circuit embodying the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0012]    [0012]FIG. 1 shows a circuit schematic diagram of a prior art magnetic write circuit  10 . Prior art magnetic write circuit  10  is part of a disk drive system and controls the magnitude and direction of current through a magnetic write head  11  represented in the diagram as an inductive coil L H . Prior art magnetic write circuit  10  includes switching transistors M 1 -M 4 , current generators I 1  and I 2 , input signal circuit nodes WDX and WDY, circuit head nodes H 1  and H 2 , and voltage source nodes V 1  and GND.  
         [0013]    Switching transistors M 1  and M 2  are PMOS transistors each having a gate, a source, and a drain. Switching transistors M 3  and M 4  are NMOS transistors each having a gate, a drain, and a source. Current generators I 1  and I 2  are each portions of a current mirror circuit used to generate a reference current Iw. Input signal circuit node WDX is connected to the gates of switching transistors M 1  and M 3 , and input signal circuit node WDY is connected to the gates of switching transistors M 2  and M 4 . The sources of switching transistors M 1  and M 2  are each connected to voltage source node V 1 , and the drains of switching transistors M 1  and M 2  are connected respectively to circuit head nodes H 1  and H 2 . Current generator I 1  is connected between circuit head node H 1  and the drain of switching transistor M 3 , and current generator I 2  is connected between circuit head node H 2  and the drain of switching transistor M 4 . The sources of switching transistors M 3  and M 4  are each connected to voltage source node GND.  
         [0014]    In an initial input signal situation chosen for purposes of description, input signal node WDX has a high voltage (V 1 ) and input signal node WDY has a low voltage (GND), for example. In the steady state in this situation, switching transistors M 2  and M 3  are turned on and switching transistors M 1  and M 4  are turned off. The voltages at circuit head nodes H 1  and H 2  are approximately V 1 −VSD, as the resistance of inductive coil L H  is low (where VSD is the voltage drop across the source-drain junction of transistor M 2 ). Current Iw is drawn from voltage source node V 1 , through the source and drain of switching transistor M 2 , through magnetic write head  11  from head node H 2  to H 1 , through current generator I 1 , through the drain and source of switching transistor M 3 , and into voltage source node GND.  
         [0015]    When the input signal on nodes WDX and WDY is subsequently changed to then have a high voltage (V 1 ) at input signal node WDY and a low voltage (GND) at input signal node WDX, switching transistors M 1  and M 4  are turned on and switching transistors M 2  and M 3  are turned off. This causes the voltage at the drain of switching transistor M 1  to initially rise to approximately V 1 −VSD, and the voltage at the drain of switching transistor M 2  to initially drop to approximately VDS+VI 2  (where VDS is the voltage drop across the drain-source junction of transistor M 4 , and VI 2  is the voltage drop across current generator I 2 ).  
         [0016]    Because the voltage at head node H 1  (which is equal to the voltage at the drain of switching transistor M 1 ) is approximately V 1 −VSD and the voltage at head node H 2  (which is equal to the voltage at the drain of switching transistor M 2 ) is approximately VDS+VI 2 , a voltage drop of approximately V 1 −VSD−VDS−VI 2  volts is initially created across inductive coil L H  from head node H 1  to H 2 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 2  to H 1 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 1  to H 2 .  
         [0017]    After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 1  to H 2 , the voltage at head node H 2  will begin to rise to nearly the voltage at head node H 1 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 1  is held approximately constant because the voltage drop VSD across the source-drain junction of switching transistor M 1  (which is turned on) is approximately constant.  
         [0018]    Therefore, because switching transistors M 1  and M 4  are turned on and switching transistors M 2  and M 3  are turned off with a high voltage at node WDY and a low voltage at node WDX, a current approximately equal to Iw is drawn from voltage source node V 1 , through the source and drain of switching transistor M 1 , through magnetic write head I 1  from head node H 1  to H 2 , through the drain and source of switching transistor M 4 , and into voltage source node GND. As described above, a maximum voltage drop of approximately V 1 −VSD−VDS−VI 2  volts is created across inductive coil L H  from head node H 1  to H 2  at the beginning of the input situation to reverse the direction of current through inductive coil L H .  
         [0019]    When the input signal on nodes WDX and WDY is subsequently changed to again have a high voltage (V 1 ) at input signal node WDX and a low voltage (GND) at input signal node WDY as in the initial input signal steady state situation described above, switching transistors M 2  and M 3  are turned on and switching transistors M 1  and M 4  are turned off. This causes the voltage at the drain of switching transistor M 2  to initially rise to approximately V 1 −VSD, and the voltage at the drain of switching transistor M 1  to initially drop to approximately VDS+VI 1  (where VDS is the voltage drop across the drain-source junction of transistor M 3 , and VI 1  is the voltage drop across current generator I 1 ).  
         [0020]    Because the voltage at head node H 2  (which is equal to the voltage at the drain of switching transistor M 2 ) is approximately V 1 −VSD and the voltage at head node H 1  (which is equal to the voltage at the drain of switching transistor M 1 ) is approximately VDS+VI 1 , a voltage drop of approximately V 1 −VSD−VDS−VI 1  volts is initially created across inductive coil L H  from head node H 2  to H 1 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 1  to H 2 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 2  to H 1 .  
         [0021]    After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 2  to H 1 , the voltage at head node H 1  will begin to rise to nearly the voltage at head node H 2 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 2  is held approximately constant because the voltage drop VSD across the source-drain junction of switching transistor M 2  (which is turned on) is approximately constant.  
         [0022]    Therefore, because switching transistors M 2  and M 3  are turned on and switching transistors M 1  and M 4  are turned off with a high voltage at node WDY and a low voltage at node WDX, a current approximately equal to Iw is drawn from voltage source node V 1 , through the source and drain of switching transistor M 2 , through magnetic write head I 1  from head node H 2  to H 1 , through the drain and source of switching transistor M 3 , and into voltage source node GND. As described above, a maximum voltage drop of approximately V 1 −VSD−VDS−VI 1  volts is created across inductive coil L H  from head node H 2  to H 1  at the beginning of the input situation to reverse the direction of current through inductive coil L H .  
         [0023]    [0023]FIG. 2 shows a circuit schematic diagram of a magnetic write circuit  20  embodying the present invention. Magnetic write circuit  20  is part of a disk drive system and controls the magnitude and direction of current through a magnetic write head  21  represented in the diagram as an inductive coil L H . Magnetic write head  21 , which is coupled into the remainder of the circuit between circuit head nodes H 1  and H 2 , includes inductive coil L H  along with magnetic material positioned in magnetic fields generated by current therethrough. Magnetic write circuit  20  includes writer circuit  22 , charge pumping circuit  24 , input signal circuit nodes WDX and WDY, the circuit head nodes H 1  and H 2  previously mentioned, and voltage source nodes V 1  and GND. Magnetic write circuit  20  is preferably fabricated in an integrated circuit.  
         [0024]    Writer circuit  22  includes switching transistors M 1 -M 4 , and current generators I 1  and I 2 . Switching transistors M 1  and M 2  are PMOS transistors each having a gate, a source, and a drain. Switching transistors M 3  and M 4  are NMOS transistors each having a gate, a drain, and a source. Current generators I 1  and I 2  are each portions of a current mirror circuit used to generate a reference current Iw. Input signal circuit node WDX is connected to the gates of switching transistors M 1  and M 3 , and input signal circuit node WDY is connected to the gates of switching transistors M 2  and M 4 . The drains of switching transistors M 1  and M 2  are connected respectively to circuit head nodes H 1  and H 2 . Current generator I 1  is connected between circuit head node H 1  and the drain of switching transistor M 3 , and current generator I 2  is connected between circuit head node H 2  and the drain of switching transistor M 4 . The sources of switching transistors M 3  and M 4  are each connected to voltage source node GND.  
         [0025]    Charge pumping circuit  24  includes capacitors C 1  and C 2 , and diodes D 1  and D 2 . Diodes D 1  and D 2  each have an anode and a cathode. Capacitor C 1  is connected between input signal circuit node WDY and the source of switching transistor M 1 , and capacitor C 2  is connected between input signal circuit node WDX and the source of switching transistor M 2 . Diode D 1  has its anode connected to voltage source node V 1  and its cathode connected to the source of switching transistor M 1 , and diode D 2  has its anode connected to voltage source node V 1  and its cathode connected to the source of switching transistor M 2 .  
         [0026]    In an initial input signal situation chosen for purposes of description, input signal node WDX has a high voltage (V 1 ) and input signal node WDY has a low voltage (GND), for example. In the steady state in this situation, switching transistors M 1  and M 4  in writer circuit  22  are turned off, switching transistors M 2  and M 3  in writer circuit  22  are turned on, and diodes D 1  and D 2  in charge pumping circuit  24  are turned on. The voltages at circuit head nodes H 1  and H 2  are approximately V 1 −VD−VSD, as the resistance of inductive coil L H  is low (where VD is the voltage drop across diode D 2  when turned on, and VSD is the voltage drop across the source-drain junction of switching transistor M 2 ). Current Iw is drawn from voltage source node V 1 , through diode D 2 , through the source and drain of switching transistor M 2 , through magnetic recording head  21  from head node H 2  to H 1 , through current generator  11 , through the drain and source of switching transistor M 3 , and into voltage source node GND. In addition, the voltage across capacitor C 1  is approximately V 1 −VD, and the voltage across capacitor C 2  is approximately −VD.  
         [0027]    When the input signal on nodes WDX and WDY is subsequently changed to then have a high voltage (V 1 ) at input signal node WDY and a low voltage (GND) at input signal node WDX, switching transistors M 1  and M 4  are turned on, and switching transistors M 2  and M 3  are turned off. Because the voltage at input signal node WDY is now V 1 , the voltage at the source of switching transistor MI momentarily becomes approximately 2V 1 −VD. This is because the voltage-current characteristic of a capacitor is determined by I=Cdv/dt, where I is the current through the capacitor, C is the capacitance of the capacitor, and dv/dt is the rate of change of the voltage across the capacitor. As a result, the voltage across capacitor C 1  (which remains V 1 −VD from the prior input signal situation) cannot instantaneously change (which would produce infinite current) and causes the voltage at the source of switching transistor M 1  to momentarily rise to approximately 2VI−VD, and turn diode D 1  off. This causes the voltage at the drain of switching transistor M 1  to initially rise to approximately 2V 1 −VD−VSD, and the voltage at the drain of switching transistor M 2  to initially drop to approximately VDS+VI 2  (where VDS is the voltage drop across the drain-source junction of transistor M 4 , and VI 2  is the voltage drop across current generator I 2 ).  
         [0028]    Because the voltage at head node H 1  (which is equal to the voltage at the drain of switching transistor M 1 ) is approximately 2V 1 −VD−VSD and the voltage at head node H 2  is approximately VDS+VI 2 , a voltage drop of approximately 2V 1 −VD−VSD−VDS−VI 2  volts is initially created across inductive coil L H  from head node H 1  to H 2 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 2  to H 1 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 1  to H 2 .  
         [0029]    After switching transistor M 1  is turned on and diode D 1  is turned off, switching transistor M 1  draws current from capacitor C 1  and causes capacitor C 1  to discharge. As the voltage across capacitor C 1  decreases, the voltage at the source of switching transistor M 1  will eventually drop to V 1 −VD. At this point, diode D 1  turns on (because the voltage at its cathode is now a VD lower than the voltage at its anode) and switching transistor M 1  draws current from voltage source node V 1  instead of capacitor C 1 . In addition, after switching transistor M 2  is turned off, capacitor C 2  charges up through diode D 2  until the voltage across capacitor C 2  becomes V 1 −VD.  
         [0030]    After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 1  to H 2 , the voltage at head node H 2  will begin to rise to nearly the voltage at head node H 1 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 1  is held approximately constant because the voltage drop VSD across the source-drain junction of switching transistor M 1  (which is turned on) is approximately constant.  
         [0031]    Therefore, because switching transistors M 1  and M 4  are turned on and switching transistors M 2  and M 3  are turned off with a high voltage at node WDY and a low voltage at node WDX, a current approximately equal to Iw is drawn from voltage source node V 1 , through diode D 1 , through the source and drain of switching transistor M 1 , through magnetic write head  21  from head node H 1  to H 2 , through the drain and source of switching transistor M 4 , and into voltage source node GND. In addition, the voltage across capacitor C 1  is approximately −VD, and the voltage across capacitor C 2  is approximately V 1 −VD. As described above, a maximum voltage drop of approximately 2V 1 −VD−VSD−VDS−VI 2  volts is initially created across inductive coil L H  from head node H 1  to H 2  at the beginning of the input situation to reverse the direction of current through inductive coils.  
         [0032]    When the input signal on nodes WDX and WDY is subsequently changed to again have a high voltage (V 1 ) at input signal node WDX and a low voltage (GND) at input signal node WDY as in the initial input signal steady state situation described above, switching transistors M 2  and M 3  are turned on, and switching transistors M 1  and M 4  are turned off. Because the voltage at input signal node WDX is now V 1  and the voltage across capacitor C 2  remains V 1 −VD from the prior input signal situation, the voltage at the source of switching transistor M 2  momentarily becomes approximately 2V 1 −VD, and turns diode D 2  off. This causes the voltage at the drain of switching transistor M 2  to initially rise to approximately 2V 1 −VD−VSD, and the voltage at the drain of switching transistor M 1  to initially drop to approximately VDS+VI 1  (where VDS is the voltage drop across the drain-source junction of transistor M 3 , and VI 1  is the voltage drop across current generator I 1 ).  
         [0033]    Because the voltage at head node H 2  (which is equal to the voltage at the drain of switching transistor M 2 ) is approximately 2V 1 −VD−VSD and the voltage at head node H 1  is approximately VDS+VI 1 , a voltage drop of approximately 2V 1 −VD−VSD−VDS−VI 1  volts is initially created across inductive coil L H  from head node H 2  to H 1 . As a result, the current through inductive coil L H  (which, prior to the change at input signal nodes WDX and WDY, was flowing through inductive coil L H  from head node H 1  to H 2 ) will follow the change in polarity across inductive coil L H  and ultimately change direction and flow through inductive coil L H  from head node H 2  to H 1 .  
         [0034]    After switching transistor M 2  is turned on and diode D 2  is turned off, switching transistor M 2  draws current from capacitor C 2  and causes capacitor C 2  to discharge. As the voltage across capacitor C 2  decreases, the voltage at the source of switching transistor M 2  will eventually drop to V 1 −VD. At this point, diode D 2  turns on (because the voltage at its cathode is now a VD lower than the voltage at its anode) and switching transistor M 2  draws current from voltage source node V 1  instead of capacitor C 2 . In addition, after switching transistor M 1  is turned off, capacitor C 1  charges up through diode D 1  until the voltage across capacitor C 1  becomes V 1 −VD.  
         [0035]    After the change in direction of current through inductive coil L H  so that a current approximately equal to Iw now flows from head node H 2  to H 1 , the voltage at head node H 1  will begin to rise to nearly the voltage at head node H 2 . This is because once the direction of the current through inductive coil L H  is established, the rate of change of the current will decrease to nearly zero because the resistance of inductive coil L H  is relatively small. Also, the voltage at head node H 2  is held approximately constant because the voltage drop VSD across the source-drain junction of switching transistor M 2  (which is turned on) is approximately constant.  
         [0036]    Therefore, because switching transistors M 2  and M 3  are turned on and switching transistors M 1  and M 4  are turned off with a high voltage at node WDX and a low voltage at node WDY, a current approximately equal to Iw is drawn from voltage source node V 1 , through diode D 2 , through the source and drain of switching transistor M 2 , through magnetic write head  21  from head node H 2  to H 1 , through the drain and source of switching transistor M 3 , and into voltage source node GND. In addition, the voltage across capacitor C 1  is approximately V 1 −VD, and the voltage across capacitor C 2  is approximately −VD. As described above, a maximum voltage drop of approximately 2V 1 −VD−VSD−VDS−VI 1  volts is initially created across inductive coil L H  from head node H 2  to H 1  at the beginning of the input situation to reverse the direction of current through inductive coil L H .  
         [0037]    [0037]FIG. 3 shows a timing diagram of a magnetic write circuit  20  embodying the present invention. Waveform  30  illustrates the voltage at input signal circuit node WDX. Waveform  32  illustrates the voltage at input signal circuit node WDY. Waveform  34  illustrates the voltage at the source of switching transistor M 1 . Waveform  36  illustrates the voltage at the source of switching transistor M 2 .  
         [0038]    Waveform  34  shows that when the voltage at input signal node WDX becomes low and the voltage at input signal node WDY becomes high, the voltage at the source of switching transistor M 1  initially rises to a maximum level well above V 1  and then drops to a steady state level slightly below V 1 . In addition, waveform  34  shows that when the voltage at input signal node WDX becomes high and the voltage at input signal node WDY becomes low, the voltage at the source of switching transistor M 1  initially drops to a minimum level and then rises to a steady state level slightly below V 1 .  
         [0039]    Waveform  36  shows that when the voltage at input signal node WDX becomes high and the voltage at input signal node WDY becomes low, the voltage at the source of switching transistor M 2  initially rises to a maximum level well above V 1  and then drops to a steady state level slightly below V 1 . In addition, waveform  36  shows that when the voltage at input signal node WDX becomes low and the voltage at input signal node WDY becomes high, the voltage at the source of switching transistor M 2  initially drops to a minimum level and then rises to a steady state level slightly below V 1 .  
         [0040]    In summary, the present invention introduces a magnetic write circuit that maximizes the head swing voltage while minimizing the power consumption of the circuit. By utilizing a charge-pumping circuit, the magnetic write circuit stores energy during a given input situation and delivers energy upon switching to the next input situation to maximize the head swing voltage without increasing the supply voltage to the circuit.  
         [0041]    Although the preferred embodiment of the present invention is shown using FET technology, the present invention may also be practiced using bipolar junction transistor technology, the topology being readily derived from the small-signal models associated with the FET embodiment. Workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.