Abstract:
A method of operation of a processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues coupled by a dispatch routing network provides flexible and efficient use of internal resources. The dispatch routing network is controlled to dynamically vary the relationship between the slices and instruction streams according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis. Instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices configured to act in concert for the particular instructions. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

Description:
The present application is a Continuation of U.S. patent application Ser. No. 14/274,927, filed on May 12, 2014 and claims priority thereto under 35 U.S.C. 120. The disclosure of the above-referenced parent U.S. patent application is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to processing systems and processors, and more specifically to a pipelined processor core with dynamic instruction stream mapping. 
     2. Description of Related Art 
     In present-day processor cores, pipelines are used to execute multiple hardware threads corresponding to multiple instruction streams, so that more efficient use of processor resources can be provided through resource sharing and by allowing execution to proceed even while one or more hardware threads are waiting on an event. 
     In existing systems, specific resources and pipelines are typically allocated for execution of the different instruction streams and multiple pipelines allow program execution to continue even during conditions when a pipeline is busy. However, resources are still tied up for pipelines that are busy, and when all the pipeline(s) assigned to an instruction stream are busy, the instruction stream is stalled, reducing the potential throughput of the processor core. 
     It would therefore be desirable to provide a method for processing program instructions that provides improved flexibility and throughput. 
     BRIEF SUMMARY OF THE INVENTION 
     The invention is embodied in a method of operation of a processor core. 
     The processor core includes multiple parallel instruction execution slices for executing multiple instruction streams in parallel and multiple dispatch queues coupled by a dispatch routing network to the execution slices. The method controls the dispatch routing network such that the relationship between the dispatch queues and the instruction execution slices is dynamically varied according to execution requirements for the instruction streams and the availability of resources in the instruction execution slices. In some embodiments, the instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution and ordinary instruction execution on a per-instruction basis, permitting the mixture of those instruction types. In other embodiments, instructions having an operand width greater than the width of a single instruction execution slice may be processed by multiple instruction execution slices dynamically configured to act in concert for the particular instructions requiring greater operand width. In other embodiments, when an instruction execution slice is busy processing one or more previously accepted instructions for one of the streams, another instruction execution slice can be selected to perform execution of a next instruction for the stream, permitting an instruction stream to proceed with execution even while one of the instruction execution slices is stalled. 
     The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
       The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of the invention when read in conjunction with the accompanying Figures, wherein like reference numerals indicate like components, and: 
         FIG. 1  is a block diagram illustrating a processing system in which techniques according to an embodiment of the present invention are practiced. 
         FIG. 2  is a block diagram illustrating details of a processor core  20  that can be used to implement processor cores  20 A- 20 B of  FIG. 1 . 
         FIG. 3  is a pictorial diagram illustrating a dispatch of instructions by processor core  20 . 
         FIG. 4  is a pictorial diagram illustrating another dispatch of instructions by processor core  20 . 
         FIG. 5  is a block diagram illustrating details of processor core  20 . 
         FIG. 6  is a block diagram illustrating details of segmented execution and I/O slices  30  of  FIG. 5 . 
         FIG. 7  is a block diagram illustrating details of an instruction execution slice  42  that can be used to implement instruction execution slices  42 A- 42 D of  FIG. 6 . 
         FIG. 8  is a block diagram illustrating details of an alternative instruction execution slice  42 AA that can be used to implement instruction execution slices  42 A- 42 D of  FIG. 6 . 
         FIG. 9  is a block diagram illustrating details of an instruction execution slice  44  that can be used to implement load-store slices  44 A- 44 D of  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention relates to methods of operation in processors and processing systems in which conventional pipelines are replaced with execution slices that can be assigned arbitrarily to execute instructions, in particular when a slice executing a current instruction for a stream is busy, and in which slices can be combined on-the-fly to execute either wider instructions or single-instruction-multiple-data (SIMD) instructions requiring multiple slices to handle the multiple data. Multiple dispatch queues are provided to receive multiple instruction streams and the dispatch queues are coupled to the instruction execution slices via a dispatch routing network so that the dispatch routing network can be controlled to perform the above dynamic reconfiguration of the relationship between the instruction execution slices and the dispatch queues according to the availability of the instruction execution slices and/or the requirements for instruction processing. A plurality of cache slices are coupled to the instruction execution slices via a result routing network so that the cache slices can also be varied in relationship with the instruction execution slices according to availability or according to other criteria. The result routing network provides communication of results and operands needed for further processing by instruction execution slices and/or cache slices. 
     Referring now to  FIG. 1 , a processing system in accordance with an embodiment of the present invention is shown. The depicted processing system includes a number of processors  10 A- 10 D, each in conformity with an embodiment of the present invention. The depicted multi-processing system is illustrative, and a processing system in accordance with other embodiments of the present invention include uni-processor systems having multi-threaded cores. Processors  10 A- 10 D are identical in structure and include cores  20 A- 20 B and local storage  12 , which may be a cache level, or a level of internal system memory. Processors  10 A- 10 B are coupled to a main system memory  14 , a storage subsystem  16 , which includes non-removable drives and optical drives, for reading media such as a CD-ROM  17  forming a computer program product and containing program instructions implementing generally, at least one operating system, associated applications programs, and optionally a hypervisor for controlling multiple operating systems&#39; partitions for execution by processors  10 A- 10 D. The illustrated processing system also includes input/output (I/O) interfaces and devices  18  such as mice and keyboards for receiving user input and graphical displays for displaying information. While the system of  FIG. 1  is used to provide an illustration of a system in which the processor architecture of the present invention is implemented, it is understood that the depicted architecture is not limiting and is intended to provide an example of a suitable computer system in which the techniques of the present invention are applied. 
     Referring now to  FIG. 2 , details of an exemplary processor core  20  that can be used to implement processor cores  20 A- 20 B of  FIG. 1  are illustrated. Processor core  20  includes an instruction cache ICache that stores multiple instruction streams fetched from higher-order cache or system memory and presents the instruction stream(s) to a plurality of dispatch queues Disp 0 -Disp 3 . Control logic within processor core  20  controls the dispatch of instructions from dispatch queues Disp 0 -Disp 3  to a plurality of instruction execution slices ES 0 -ES 7  via a dispatch routing network  22  that permits instructions from any of dispatch queues Disp 0 -Disp 3  to any of instruction execution slices ES 0 -ES 7 , although complete cross-point routing, i.e., routing from any dispatch queue to any slice is not a requirement of the invention. Instruction execution slices ES 0 -ES 7  perform sequencing and execution of logical, mathematical and other operations as needed to perform the execution cycle portion of instruction cycles for instructions in the instructions streams, and may be identical general-purpose instruction execution slices ES 0 -ES 7 , or processor core  20  may include special-purpose execution slices ES 0 -ES 7 . Instruction execution slices ES 0 -ES 7  may include multiple internal pipelines for executing multiple instructions and/or portions of instructions, so that the indication of “busy” as described herein may also include a condition in which a particular one of instruction execution slices ES 0 -ES 7  is busy processing multiple instructions for a given instruction stream. Instruction execution slices ES 0 -ES 7  are coupled by an execution slice communication network  29  through which values can be exchanged between instruction execution slices ES 0 -ES 7 , for example when further processing is performed by one slice on values generated by another execution slice. A fully-routed (or cross-point) network may be used to implement execution slice communication network  29 . Alternatively, the connections between instruction execution slices ES 0 -ES 7  may be made only between particular groups of instruction execution slices, e.g., only neighboring slices might be connected in some implementations. Execution slice communication network  29  is also used for tandem execution of SIMD or large-operand instructions that require concurrent/coordinated execution, although execution of such instructions can be performed in a de-coupled manner, as well. 
     The load-store portion of the instruction execution cycle, (i.e., the operations performed to maintain cache consistency as opposed to internal register reads/writes), is performed by a plurality of cache slices LS 0 -LS 7 , which are coupled to instruction execution slices ES 0 -ES 7  by a write-back (result) routing network  24 . In the depicted embodiment, any of cache slices LS 0 -LS 7  can be used to perform load-store operation portion of an instruction for any of instruction execution slices ES 0 -ES 7 , but that is not a requirement of the invention. Instruction execution slices ES 0 -ES 7  may issue internal instructions concurrently to multiple pipelines, e.g., an instruction execution slice may simultaneously perform an execution operation and a load/store operation and/or may execute multiple arithmetic or logical operations using multiple internal pipelines. The internal pipelines may be identical, or may be of discrete types, such as floating-point, scalar, load/store, etc. Further, a given execution slice may have more than one port connection to write-back routing network  24 , for example, a port connection may be dedicated to load-store connections to cache slices LS 0 -LS 7 , while another port may be used to communicate values to and from other slices, such as special-purposes slices, or other instruction execution slices. Write-back results are scheduled from the various internal pipelines of instruction execution slices ES 0 -ES 7  to write-back port(s) that connect instruction execution slices ES 0 -ES 7  to write-back routing network  24 . A load-store routing network  28  couples cache slices LS 0 -LS 7  to provide conversion transfers for execution of SIMD instructions, processing of instructions with data width greater than a width of cache slices LS 0 -LS 7  and other operations requiring translation or re-alignment of data between cache slices LS 0 -LS 7 . An I/O routing network  26  couples cache slices LS 0 -LS 7  to a pair of translation slices XS 0 , XS 1  that provide access to a next higher-order level of cache or system memory that may be integrated within, or external to, processor core  20 . While the illustrated example shows a matching number of cache slices LS 0 -LS 7  and execution slices ES 0 -ES 7 , in practice, a different number of each type of slice can be provided according to resource needs for a particular implementation. As mentioned above, dispatch routing network  22  is a unidirectional network, but can also take the form of a cross-point network as shown, as may load-store routing network  28  and I/O routing network  26 . 
     Referring now to  FIG. 3 , examples of instruction routing to instruction execution slices ES 0 , ES 1  and ES 2  within processor core  20  are shown. In the examples given in this disclosure, it is understood that the instructions dispatched to instruction execution slices may be full external instructions or portions of external instructions, i.e., decoded “internal instructions.” Further, in a given cycle, the number of internal instructions dispatched to any of instruction execution slices ES 0 , ES 1  and ES 2  may be greater than one and not every one of instruction execution slices ES 0 , ES 1  and ES 2  will necessarily receive an internal instruction in a given cycle.  FIG. 3  depicts three columns showing sequences of instructions that are sent to instruction execution slices ES 0 , ES 1  and ES 2 , respectively. Rows correspond to an instruction dispatch sequence of the instructions, and while the rows are aligned for simplicity of illustration, it is understood that in practice that the dispatches will generally not occur simultaneously and there is no constraint between the columns on when an execution slice may complete or receive a particular instruction. In rows 1-2, independent instructions are dispatched to each of instruction execution slices ES 0 , ES 1  and ES 2 . At row 3, an instruction requiring a wider execution unit is dispatched for execution by dynamically combining instruction execution slices ES 1  and ES 2 , while instruction execution slice ES 0  is sent another instruction having a width matching the width of instruction execution slices ES 0 , ES 1  and ES 2 . At rows 4-5, independent instructions are again dispatched to each of instruction execution slices ES 0 , ES 1  and ES 2 . In rows 6-7, SIMD instructions having three data values are executed by linking instruction execution slices ES 0 , ES 1  and ES 2  to perform the parallel operation, and at rows 8-9, SIMD instructions having two data values are executed by linking instruction execution slices ES 0 , ES 1  while instruction execution slice ES 2  is sent other independent instructions. At row 10, instruction execution slices ES 0 , ES 1  and ES 2  again commence independent execution of instructions. The examples provided in  FIG. 3  are only illustrative and are provided to show the flexibility of dynamic reconfiguration provided in processor core  20 . As can be seen, the configurability provides the potential for maintaining all of instruction execution slices ES 0 -ES 7  in an active execution state while performing various types of operations, such as executing SIMD or variable width instruction streams. 
     Referring now to  FIG. 4 , another example of instruction processing within processor core  20  is shown, and which is illustrated separately in  FIG. 4 , but that may be combined with any or all of the instruction execution slice reconfigurations provided in the examples of  FIG. 3 .  FIG. 4  depicts three columns showing sequences of instructions that are sent to instruction execution slices ES 0 , ES 1  and ES 2 , respectively. As in  FIG. 3 , rows correspond to an instruction sequence and the number shown in each block is the number of an instruction stream numbered from 0 to 2, to which the instructions being executed belong. In rows 1-2, instructions are dispatched to each of instruction execution slices ES 0 , ES 1  and ES 2  for each of corresponding instruction streams 0-2. At row 3, instruction execution slice ES 1  becomes busy, as instruction execution slice ES 1  is still processing the current instruction in instruction stream 1. In row 4, instruction execution slice ES 2  is dispatched an instruction for instruction stream 1, either due to a prioritization, round-robin, or other scheme that permits instructions for instruction streams to be routed to instruction execution slices other than a default instruction execution slice for the instruction stream. In Row 5, instruction execution slice ES 0  becomes busy after accepting an instruction from row 4, instruction execution slice ES 1  is available to accept further instructions, so instruction execution slice ES 1  receives dispatch of a next instruction for instruction stream 1. Instruction execution slice ES 2  is also executing an instruction for instruction stream 1. In row 6, instruction execution slice ES 0  is still busy and instruction execution slices ES 1  and ES 2  resume execution of instructions for instruction streams 1 and 2, respectively. At row 7, instruction execution slice ES 1  is co-opted to execute a next instruction for instruction stream 0, while instruction slice ES 0  is still busy executing a current instruction and instruction execution slice ES 2  executes another instruction for instruction stream 2. In row 8, instruction execution slice ES 1  executes an instruction for instruction stream 1, while instruction execution slice ES 2  executes another instruction for instruction stream 2. The examples provided in  FIG. 4  are only illustrative and are provided to show the flexibility of mapping of instruction stream dispatches provided in processor core  20 . As can be seen, the routable dispatch provides the potential for maintaining all of instruction streams in an active execution state, even while a busy condition is encountered for some execution slices. 
     Referring now to  FIG. 5 , further details of processor core  20  are illustrated. Processor core  20  includes a branch execution unit  32  an instruction fetch unit (IFetch)  33  and an instruction sequencer unit (ISU)  34  that control the fetching and sequencing of instructions. A self-learning instruction buffer (IB)  35  groups instructions in order to perform re-configurations such as those shown in  FIG. 3 , i.e., arranging instructions in the dispatch queues to setup execution of SIMD and variable-width operations. An instruction buffer (IBUF)  36  is partitioned to maintain dispatch queues (Disp 0 -Disp 3  of  FIG. 2 ) for each of the instruction streams and dispatch routing network  22  couples IBUF  36  to the segmented execution and cache slices  30 . An instruction flow and network control block  37  performs control of segmented execution and cache slices  30  and dispatch routing network  22  to perform dynamic control of the slices as illustrated in  FIG. 3  and  FIG. 4 , as well as other operations as described in further detail below. An instruction completion unit  38  is also provided to track completion of instructions sequenced by ISU  34  and to control write-back operations by cache slices within segmented execution and cache slices  30 . A power management unit  39  provides for energy conservation by reducing or increasing a number of active slices within segmented execution and cache slices  30 . 
     Referring now to  FIG. 6 , further details of segmented execution and cache slices  30  within processor core  20  are illustrated. Instruction execution slices  42 A- 42 D are representative of, for example, instruction execution slices ES 0 , ES 2 , ES 4  and ES 6  in  FIG. 2 , and cache slices  44 A- 44 D are representative of cache slices LS 0 , LS 2 , LS 4  and LS 6  in  FIG. 2 . Write-back routing network  24  takes the form of a cross-pointed set of eight busses that permits simultaneous bidirectional communication between each of instruction execution slices ES 0 , ES 2 , ES 4  and ES 6  and a selected corresponding one of cache slices LS 0 , LS 2 , LS 4  and LS 6 . With respect to the bidirectional communication, a cache slice used for write back of results for an instruction execution slice may be different from the cache slice used for loading of data, since, as illustrated in  FIGS. 3-4 , the sequence of instructions may alternate between instruction streams and under such conditions it will generally be desirable to connect a cache slice to a different instruction execution slice when changing the execution slice used for executing the next instruction in a sequence for an instruction stream. Further, the relationship between cache slices and instruction execution slices may be arbitrarily varied, e.g., for instructions referencing large amounts of data, multiple cache slices may be assigned for loads, while for instructions modifying large numbers of values, multiple cache slices may be assigned for result write-back operations. By providing write-back routing network  24  that supports arbitrary connections between cache slices and instruction execution slices, segmented execution is efficiently supported by enabling transfer of values from one or more generating slices to one or more receiving slices, which may be the same type of slice as the generating slice, or may be another slice type, e.g., special purpose slice(s). A cluster fence  46  provides for coupling write-back routing network to other write-back routing networks of other groups (clusters) of instruction execution slices and cache slices, e.g., instruction execution slices ES 1 , ES 3 , ES 5  and ES 7  and cache slices LS 1 , LS 3 , LS 5  and LS 7 . 
     Referring now to  FIG. 7 , an example of an execution slice (ES)  42  that can be used to implement instruction execution slices  42 A- 42 D in  FIG. 6  is shown. Inputs from the dispatch queues are received via dispatch routing network  22  by a register array  50  so that operands and the instructions can be queued in the execution reservation stations (ER)  53 . Register array  50  is architected to have independent register sets for independent instruction streams or SIMD instructions, while dependent register sets that are clones across multiple instruction execution slices are architected for instances where multiple instruction execution slices are executing non-SIMD instructions or the same segment of an SIMD instruction for the same instruction stream(s). An alias mapper 51 maps the values in register array to any external references, such as write-back values exchanged with other slices over write-back routing network  24 . A history buffer HB  52  provides restore capability for register targets of instructions executed by ES  42 . Result values selected from write-back routing network  24  and operand values from register array  50  are selected by an arithmetic logic unit (ALU) input multiplexer  54  and operated on by an ALU  55 . A result buffer  56  receives results from ALU  55  and a multiplexer  57  makes the value of result buffer  56  available to one or more channels of write-back routing network  24  that can be used by a next ES processing a next instruction for the instruction stream or a cache slice to store the result, depending on the target of the operation. Multiplexer  57  also provides connection to other instruction execution slices via execution slice communication network  29 . Write-back routing network  24  is also coupled to ER  53 , history buffer  52  and ALU input multiplexer  54  by a write-back buffer  58 , so that write-back of resource values, retirement of completed instructions and further computation on results are supported, respectively. 
     Referring now to  FIG. 8 , another example of details within an execution slice (ES)  42 AA that can be used to implement instruction execution slices  42 A- 42 D in  FIG. 6  is shown. Execution slice  42 AA is similar to execution slice  42  of  FIG. 7 , so only differences between them will be described in detail below. Execution slice  42 AA is illustrated alongside another execution slice  42 BB to illustrate an execution interlock control that may be provided between pairs of execution slices within execution slices ES 0 -ES 7  of  FIG. 2 , or between other groupings of execution slices, The execution interlock control provides for coordination between execution slices supporting execution of a single instruction stream, since otherwise execution slices ES 0 -ES 7  independently manage execution of their corresponding instruction streams. Execution slice  42 AA includes multiple internal execution pipelines  70 A- 70 C and  72  that support out-of-order and simultaneous execution of instructions for the instruction stream corresponding to execution slice  42 AA. The instructions executed by execution pipelines  70 A- 70 C and  72  may be internal instructions implementing portions of instructions received over dispatch routing network  22 , or may be instructions received directly over dispatch routing network  22 , i.e., the pipelining of the instructions may be supported by the instruction stream itself, or the decoding of instructions may be performed upstream of execution slice  42 AA. Execution slice  72  is illustrated separately multiplexed to show that single-pipeline, multiple-pipeline or both types of execution units may be provided within execution slice  42 AA. The pipelines may differ in design and function, or some or all pipelines may be identical, depending on the types of instructions that will be executed by execution slice  42 AA. For example, specific pipelines may be provided for address computation, scalar or vector operations, floating-point operations, etc. Multiplexers  57 A- 57 C provide for routing of execution results to/from result buffer  56 A and routing of write-back results to write-back routing network  24 , I/O routing network  26  and other routing network(s)  28  that may be provided for routing specific data for sharing between slices or write-back operations sent to one or more of cache slices LS 0 -LS 7 . 
     Referring now to  FIG. 9 , an example of a cache slice (LS Slice)  44  that can be used to implement cache slices  44 A- 44 D in  FIG. 6  is shown. A load/store access queue (LSAQ)  60  is coupled to write-back routing network  24 , and the direct connection to write-back routing network  24  and LSAQ  60  is selected by a multiplexer  61  that provides an input to a cache directory  63  of a data cache  62  from either LSAQ  60  or from write-back routing network  24 . Connections to other cache slices are provided by load-store routing network  28 , which is coupled to receive from data cache  62  and to provide data to a data unalignment block  64  of a another slice. A data formatting unit  65  couples cache slice  44  to write-back routing network via a buffer  66 , so that write-back results can be written through from one execution slice to the resources of another execution slice. Data cache  62  is also coupled to I/O routing network  26  for loading values from higher-order cache/system memory and for flushing or casting-out values from data cache  62 . 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention.