Abstract:
A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an amplifier. When the first and second capacitors are disconnected from the amplifier, they are charged by respective first and second input signals. The apparatus includes a plurality of sampling capacitors, each configured to sample a respective one of a plurality of signals during a sampling phase, an amplifier, and a plurality of decoupling switches configured to isolate the sampling capacitors from the amplifier during the sampling phase and to connect the plurality of sampling capacitors to the amplifier during the amplifying phase.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    In general, the present invention relates to CMOS circuitry and, more particularly, to switched capacitor amplifiers. 
         [0002]    Analog integrated circuits (ICs) are integrated circuits that process analog signals. Examples of such circuits may include, for example, amplifiers, reference current sources, and reference voltage sources. Digital integrated circuits are ICs which process digital signals. Examples of digital integrated circuits may include, for example, logical circuit and state machines, such as processors. 
         [0003]    Some integrated circuits, however, may process both analog and digital signals. Such circuits are known as mixed signal integrated circuits. Mixed signal ICs may require the use of a DC bias current supply. A common example of a mixed signal circuit is an analog-to-digital converter (ADC). ADCs, such as pipelined ADCs, may accept an input analog signal and produce an output digital signal having a value corresponding to the magnitude of the input analog signal. ADCs may be found in numerous products, such as CMOS based imaging products. CMOS imaging products may include ICs that include a plurality of ADCs, so that a plurality of analog signals may be simultaneously converted to corresponding digital signals. 
         [0004]    Most CMOS imagers have a maximum power consumption value, which they may not exceed. The ADCs&#39; constant consumption of current from the DC bias current supply forms a significant part of the maximum power consumption value for most imagers. Accordingly, it is desirable to reduce imager power consumption attributable to sources other than consumption of the DC bias current. 
         [0005]    One such source of power consumption by the ADCs themselves is the switched capacitor amplifiers that make up the various stages of pipelined ADCs. Switched capacitor amplifiers may include a number of switches. Charge injection from turning on or off at least some of the switches contributes to a relatively long settling time of the switched capacitor amplifier, which increases ADC power consumption. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    Included in the drawing are the following figures: 
           [0007]      FIG. 1  is a timing diagram for operating a switched capacitor amplifier according to an embodiment of the present invention. 
           [0008]      FIG. 2(   a ) is a circuit diagram of a switched capacitor amplifier at a first time during the sampling phase according to an embodiment of the present invention. 
           [0009]      FIG. 2(   b ) is a circuit diagram of the switched capacitor amplifier of  FIG. 2(   a ) at a second time during the sampling phase. 
           [0010]      FIG. 2(   c ) is a circuit diagram of the switched capacitor amplifier of  FIGS. 2(   a ) and ( b ) during a third time during the sampling phase. 
           [0011]      FIG. 2(   d ) is a circuit diagram of the switched capacitor amplifier of  FIGS. 2(   a )-( c ) during the amplifying phase. 
           [0012]      FIG. 3(   a ) is a graph showing a differential output of a differential amplifier of the switched capacitor amplifier during the phase shown in  FIG. 2(   a ). 
           [0013]      FIG. 3(   b ) is a graph showing a differential output of the differential amplifier of the switched capacitor amplifier during the phase shown in  FIG. 2(   b ). 
           [0014]      FIG. 3(   c ) is a graph showing a comparison between the differential output of the differential amplifier of the switched capacitor amplifier during the phase shown in  FIG. 2(   c ) and the differential output of a conventional switched capacitor amplifier. 
           [0015]      FIG. 3(   d ) is a graph showing a comparison between the differential output of the differential amplifier of the switched capacitor amplifier during the phase shown in  FIG. 2(   d ) and the differential output of a conventional switched capacitor amplifier. 
           [0016]      FIG. 4  is a diagram and graph showing a computer simulation and the differential amplifier output results of the computer simulation of the switched capacitor amplifier of  FIGS. 2(   a )-( d ). 
           [0017]      FIG. 5  is a diagram of a 1.5 bit per stage pipelined ADC which may be used with the switched capacitor amplifier of  FIGS. 2(   a )-( d ). 
           [0018]      FIG. 6  is a circuit diagram of a switched capacitor amplifier according to an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    An example 1.5 bit per stage pipelined ADC for converting an analog signal into digital words is shown in  FIG. 5 . As shown, the example ADC may include 7 cascade connected stages. Each of the first six stages may convert a portion of the analog signal using two lines to encode three values (i.e. 1.5 bits). Stage seven may convert the remaining portion of the analog signal into three digital bits, resulting in a total conversion of the analog signal into a twelve bit digital word. 
         [0020]    Each stage may include at least one switched capacitor amplifier. Stage 1 may receive a differential input signal v_dif in and timing and reference signals (not shown). Stages 2-7 may receive the timing and reference signals and receive an output signal from the preceding stage. The output signal from each stage may equal the input signal to the stage, less the value of the portion of the signal already converted, amplified by a predetermined gain factor. For stage 1, the predetermined gain factor may be, for example, 1 and for stages 2-7, the predetermined gain factor may be, for example, 2. 
         [0021]    Each stage may provide signals to the digital block (encoder), as shown. The digital block may output a 12 bit word. 
         [0022]    Switched capacitor amplifier  100  according to an example embodiment of the present invention is shown in  FIG. 6 . As shown, switched capacitor amplifier  100  may include first and second input nodes  34  and  40  for receiving first and second input signals vinp and vinn of a differential input signal, respectively, and may include first and second reference voltage input nodes  36  and  38  for receiving first and second reference voltages vref+ and vref−, of a differential reference voltage, respectively. Switched capacitor amplifier  100  may also include amplifier  46 , which may include first and second amplifier input nodes  26  and  28 , for receiving and amplifying the sampled first and second signals, and first and second output nodes  30  and  32  for providing a differential output signal. Amplifier  46  may be any suitable differential amplifier, such as, for example, a differential operational amplifier. Switched capacitor amplifier  100  may also include sampling capacitors  4  and  6  and sampling/feedback capacitors  2  and  8 ; sampling switches  10 ,  12 ,  14  and  16  coupled to top plates of respective sampling capacitors  2 ,  4 ,  6  and  8 ; first and second crowbar switches  52  and  54 ; feedback switches  42  and  44  in respective feedback lines; decoupling switches  18  and  20  coupled between respective bottom plates of sampling capacitors  2 / 4  and  6 / 8  and input nodes  26  and  28 ; reference voltage line vcm for providing a reference voltage which may be a common mode voltage for the circuit; bottom plate switches  48  and  50  coupled between respective bottom plates of sampling capacitors  2 / 4  and  6 / 8 ; and vcm and reset switches  22  and  24  coupled between the input nodes  26  and  28  and vcm. The example switched capacitor amplifier  100  may be included in the example 1.5 bit per stage pipelined ADC shown in  FIG. 5 . 
         [0023]    While in the above example the sampling capacitors are described as having specific top and bottom plates, this is not intended to limit the scope of the embodiment. Instead, either of the plates of each capacitor may be top plates, bottom plates, first ends or second ends. 
         [0024]    Sampling switches  10 ,  12 ,  14  and  16 , crowbar switches  52  and  54 , feedback switches  42  and  44 , decoupling switches  18  and  20  and bottom plate switches  48  and  50  may be any suitable switches, such as, for example, MOS transistors or CMOS transfer gates. After current passes through such a switch in a conducting state and the switch is subsequently switched from conducting to not conducting, some amount of charge remaining in the transfer gate when it is turned off may be injected to surrounding components. The amount of charge injected when the switch is switched from conducting to not conducting is proportional to the amount of current passing through the switch immediately before it is switched. 
         [0025]    Switched capacitor amplifier  100  may operate in two different phases, which may perform two different functions. The first phase may be a sampling phase. In the sampling phase, the differential input signal may be sampled onto sampling capacitors  2 ,  4 ,  6  and  8 . The second phase may be an amplifying phase. In the amplifying phase, the capacitors  2  and  8  may be switched by the feedback switches  42  and  44  to become feedback capacitors and the sampled differential input signal may be amplified to a desired gain. If example switched capacitor amplifier  100  were operated in, for example, a 1.5 bit per stage pipelined ADC, the gain for the first stage may be 1 and the gain for the remaining stages may be two and the amplified differential output signal may be output to the next sequential stage in the pipeline. To achieve a gain of two, the capacitance of the sampling capacitors  4  and  6  and the sampling/feedback capacitors  2  and  8  may be substantially equal. 
         [0026]      FIG. 1  is a timing diagram showing overlapping clock signal phases φ 1   p  and φ 1  and φ 2   p  and φ 2 , which define the sampling and amplifying phases. Here, at the leading edge of φ 1  and φ 1   p , the sampling phase may begin. Similarly, at the leading edge of φ 2  and φ 2   p , the amplifying phase may begin. This may not, however, always be true. For example, if switched capacitor amplifier  100  were operated in, for example, a 1.5 bit per stage pipelined ADC, only odd stages, for example, may operate as described above. In this example, even stages may operate such that at the leading edge of φ 1  and φ 1   p , the amplifying phase may begin, and at the leading edge of φ 2  and φ 2   p , the sampling phase may begin. Alternatively, the opposite may be true, such that even stages may operate such that at the leading edge of φ 1  and φ 1   p , the sampling phase may begin and at the leading edge of φ 2  and φ 2   p , the amplifying phase may begin. In this alternative construction, odd stages may operate such that at the leading edge of φ 1  and φ 1   p , the amplifying phase may begin and at the leading edge of φ 2  and φ 2   p , the sampling phase may begin. In this way, each stage in the example 1.5 bit per stage pipelined ADC may generate successive bits concurrently, resulting in faster analog to digital conversion of a bit string. During the non-overlap period between the trailing edge of φ 1  and the leading edge of φ 2  and φ 2   p , amplifier  46  may be in an open loop configuration. 
         [0027]    Operation of example switched capacitor amplifier  100  will now be described with reference to  FIGS. 2(   a )-( d ),  3 ( a )-( d ) and  5 . 
         [0028]    During a first portion of the sampling phase occurring at the leading edge of φ 1  and φ 1   p , sampling switches  10 ,  12 ,  14  and  16  and bottom plate switches  48  and  50  may be closed. Closing the bottom plate switches may apply the common mode voltage, vcm, to the bottom plates of sampling capacitors  2 ,  4 ,  6  and  8  and closing the sampling switches at the same time may sample first input signal vinp onto sampling capacitors  2  and  4  and second input signal vinn onto sampling capacitors  6  and  8 . At the same time, decoupling switches  18  and  20  may be opened and reset switches  22  and  24  may be closed. This arrangement is illustrated in  FIG. 2(   a ). 
         [0029]    Opening decoupling switches  18  and  20  may electrically disconnect amplifier input nodes  26  and  28  from the bottom plates of sampling capacitors  2 ,  4 ,  6  and  8 . Further, closing reset switches  22  and  24  may apply vcm to amplifier inputs  26  and  28  to reset amplifier input nodes  26  and  28 . 
         [0030]    The differential output from amplifier  46  may be zero volts between the leading edge of φ 1  and φ 1   p  and the trailing edge of φ 1   p  because no charge may flow to amplifier  46  during this period. This result is shown in  FIG. 3(   a ). 
         [0031]    During a second portion of the sampling phase occurring at the trailing edge of φ 1   p , bottom plate switches  48  and  50  may be opened first to electrically disconnect vcm from bottom plate nodes  60  and  62 . This step may be referred to as bottom plate sampling. This arrangement is shown in  FIG. 2(   b ). Under ideal conditions, when bottom plate switches  48  and  50  are opened, charge injection from bottom plate switches  48  and  50  may be stored in parasitic capacitances at respective bottom plate nodes  60  and  62  and respective amplifier input nodes  26  and  28 . The charge injection may, however, be equal at amplifier input nodes  26  and  28  because the input (vcm) to bottom plate nodes  60  and  62  was the same. Further, under ideal conditions, when sampling switches  10 ,  12 ,  14  and  16  are subsequently opened, as described below, charge injection from sampling switches  10 ,  12 ,  14  and  16  may not be stored in respective sampling capacitors  2  and  4  and  6  and  8  because bottom plate nodes  60  and  62  may be floating. 
         [0032]    In reality, however, charge injection from sampling switches  10 ,  12 ,  14  and  16  may be stored in sampling capacitors  2 ,  4 ,  6  and  8  because there may be a relatively large parasitic capacitance at bottom plate nodes  60  and  62  and, accordingly, those nodes may not be floating. By way of example, assume bottom plate switch  48  is connected to ground. If a parasitic capacitance connected to one of the bottom plate nodes is considered, when sampling switch  10  is turned off, sampling capacitor  2  may store an injected charge according to the following equation (1): 
         [0000]        Q _injected= V in( C sample× Cp )/( C sample+ Cp ),  (1) 
         [0000]    where Q_injected may be the charge injected from the associated sampling switches, Vin may be an input voltage, Csample may be the capacitance on the associated sampling capacitor and Cp may be the parasitic capacitance connected to the bottom plate node. If the node is floating (Cp=0), then Q_inject will also equal zero. If, however, the node is connected to ground such that Cp is large, Q_injected=Csample×Vin. 
         [0033]    In normal operation of a switched capacitor amplifier, without use of decoupling switches  18  and  20 , Cp seen by sampling capacitors  2 ,  4 ,  6  and  8  may be relatively large. Without decoupling switches  18  and  20 , then, sampling capacitors  2 ,  4 ,  6  and  8  may store at least some charge injected from opening sampling switches  10 ,  12 ,  14  and  16 . 
         [0034]    Using the embodiment of  FIGS. 2(   a ) through  2 ( d ), any charge injected from bottom plate switches  48  and  50  to amplifier  46  may cancel out due to the completely differential architecture of the example switched capacitor amplifier  100 . That is, when the bottom plate switches are opened, each one may inject the same amount of charge so that the differential output due to charge injection from the bottom plate switches may be zero. Thus, the differential output of amplifier  46  may be zero volts during the period between the trailing edges of φ 1   p  and φ 1 , as shown in  FIG. 3(   b ). 
         [0035]    Then, during a third portion of the sampling phase occurring at the trailing edge of φ 1 , sampling switches  10 ,  12 ,  14  and  16  and reset switches  22  and  24  may be opened. Opening the sampling switches may electrically disconnect the top plates of the sampling capacitors from the circuit input nodes. Opening the reset switches may electrically disconnect the amplifier input nodes from vcm. Decoupling switches  18  and  20  may remain open at this time, electrically disconnecting the amplifier from the bottom plates of the sampling capacitors. This arrangement is shown in  FIG. 2(   c ). 
         [0036]    Because the amplifier may be electrically disconnected from the bottom plates of the sampling capacitors, Cp seen by sampling capacitors  2 ,  4 ,  6  and  8  at bottom plate nodes  60  and  62  may be reduced. Accordingly, bottom plate sampling may operate according to or close to the ideal situation described above. In this way, decoupling switches  18  and  20  may prevent or substantially decrease injected charge, from sampling switches  10 ,  12 ,  14  and  16 , from being stored in sampling capacitors  2 ,  4 ,  6  and  8  and ultimately transferred to amplifier input nodes  26  and  28 . 
         [0037]    Preventing or substantially reducing charge injection from sampling switches  10 ,  12 ,  14  and  16  may be desirable because this charge injection may not be equal, as may be the case for charge injection from bottom plate switches  48  and  50 . This is because vinp and vinn, which were applied to sampling switches  10 ,  12 ,  14  and  16 , may be different, whereas vcm applied to bottom plate switches  18  and  20  was the same. 
         [0038]    As with the bottom plate switches, charge injected by turning off the reset switches  22  and  24  may cancel out due to the completely differential architecture of the example switched capacitor amplifier  100 . That is, when the reset switches are opened, each one may inject the same amount of charge so that differential input due to charge injection from the bottom plate switches may be zero. As with the bottom plate switches, this may be because a single potential, vcm, is applied to reset switches  22  and  24 . 
         [0039]    As shown by the solid line in  FIG. 3(   c ), the differential output of amplifier  46  may remain at zero volts between the trailing edge of φ 1  and the leading edge of φ 2 . This is because decoupling switches  18  and  20  may be open when sampling switches  10 ,  12 ,  14  and  16  are opened and, accordingly, charge injection to amplifier input nodes  26  and  28  may be differential zero. 
         [0040]    The dashed line in  FIG. 3(   c ) represents a differential output of amplifier  46  in the hypothetical situation where decoupling switches  18  and  20  are not included in switched capacitor amplifier  100 . Here, the differential output of amplifier  46 , voutp−voutn, may become negative quickly. This is because amplifier  46  may be in an open loop configuration during the non-overlap period when the injected charge is applied to the input terminals of the amplifier. 
         [0041]    As shown in  FIG. 2(   d ), during the amplifying phase beginning at the leading edge of φ 2  and φ 2   p  in  FIG. 1 , crowbar switches  52  and  54  and feed back switches  42  and  44  may be closed to achieve, for example, an amplifier gain of 2vin/vref. Such gain of 2 may be desirable, for example, in second through seventh stages of the example 1.5 bit per stage pipelined ADC of  FIG. 6 . 
         [0042]    As shown by the solid line in  FIG. 3(   d ), the starting point for settling of amplifier  46  is differential zero. As shown by the dashed line in  FIG. 3(   d ), the starting point for settling of amplifier  46  in the hypothetical situation in which decoupling switches  18  and  20  are not included in the switched capacitor amplifier is not differential zero. Instead, it is differential negative, due to the unequal charge injection from sampling switches  10 ,  12 ,  14  and  16  described above. As shown, use of decoupling switches  18  and  20  as described above may result in shorter settling time for amplifier  46 , resulting in reduced power consumption for switched capacitor amplifier  100 . 
         [0043]      FIG. 4  shows the results of computer simulations of example switched capacitor amplifier  100 . As shown, without decoupling and reset switches, the settling time for the amplifier is 9.5 ns. With decoupling and reset switches, however, the settling time for the amplifier is 6.1 ns. 
         [0044]    Accordingly, the example switched capacitor amplifier of the present invention may reduce settling time for the amplifier, thus reducing power consumption by the switched capacitor amplifier. If the example switched capacitor amplifier is used in, for example, a pipelined ADC, the power savings may be multiplied for each example switched capacitor amplifier located at each stage. Accordingly, the power savings due to the faster settling time may be substantial. 
         [0045]    While example embodiments of the invention have been shown and described herein, it will be understood that such embodiments are provided by way of example only. Numerous variations, changes and substitutions will occur to those skilled in the art without departing from the invention.