Abstract:
There is described a method of generating a power supply tracking a reference signal, comprising the steps of: filtering the reference signal; generating a first voltage in dependence on the filtered reference signal; generating a second voltage in dependence on the reference signal; and combining the first and second voltages to provide a power supply voltage.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to supply stages for generating power supply voltages, and particularly to supply voltage stages which track the envelope of a reference signal. 
       BACKGROUND OF THE INVENTION 
       [0002]    It is known in the art to provide efficient power supply generation circuitry for, in particular, power amplifier applications. Power amplifiers, for example radio frequency (RF) power amplifiers, typically have high peak-to-average (PAR) ratios. If a power supply voltage is provided which is sufficient to deal with the voltage peaks, then for a large portion of the operation of the amplifier the power supply voltages are unnecessarily high, and the operation of the power amplifier is highly inefficient. 
         [0003]    For this reason, efficient power supply generation means have been developed. Typical techniques fall into the broad categories of envelope elimination and restoration (EER) and envelope tracking (ET). 
         [0004]    An efficient envelope tracking voltages supply scheme is described in UK Patent No. 2398648 in the name of Nujira Limited. 
         [0005]    Prior art efficient envelope tracking power supplies operate efficiently for narrowband signals. However for wideband signals, inefficiencies arise. This is due to excessive switching losses and distortion as a result of having to adapt the power supply to handle a wide range of frequencies. 
         [0006]    It is an aim of the invention to provide an improved technique for efficiently providing a power supply voltage, preferably over an increased bandwidth. 
       SUMMARY OF THE INVENTION 
       [0007]    In one aspect the invention provides a method of generating a power supply tracking a reference signal, comprising the steps of: filtering the reference signal; generating a first voltage in dependence on the filtered reference signal; generating a second voltage in dependence on the reference signal; and combining the first and second voltages to provide a power supply voltage. 
         [0008]    The step of generating the first voltage may include tracking the filtered reference signal and the step of generating the second voltage comprises tracking the reference signal. 
         [0009]    The step of generating the second voltage may comprise subtracting the power supply voltage from the reference signal. 
         [0010]    The step of generating the second voltage may further comprise amplifying the subtracted signal. 
         [0011]    The step of generating the second voltage may include delaying the reference signal, the second voltage being generated in dependence on the delayed reference signal. 
         [0012]    The step of subtracting the power supply voltage from the reference signal may generate an error signal, and the step of amplifying the subtracted signal may amplify the error signal to generate a correction signal, wherein the correction signal forms the second voltage. 
         [0013]    The steps of filtering the reference signal may comprise: filtering the reference signal with a first filter bandwidth to provide a first filtered reference signal; and filtering the reference signal with a second filter bandwidth to provide a second filtered reference signal; the step of generating the first voltage being in dependence on the first filtered reference signal; and the step of generating the second voltage being in dependence on the second filtered reference signal. 
         [0014]    The second filter bandwidth may be broader than the first filter bandwidth. 
         [0015]    The step of filtering the reference signal may comprise: filtering the reference signal with n−2 further filter bandwidths to provide n−2 further filtered reference signals, wherein the total number of filtered reference signals is n; generating n−2 further voltages in dependence on the n−2 further filtered reference signals, wherein the total number of generated voltages is n; and combining the n−2 further voltages with the combined first and second voltages by: combining each of the further voltages in cascaded stages, wherein for the i th  stage, where i=3 ton, the i th  generated voltage is combined with the combined voltage of the i−1 th  stage to provide a modified power supply voltage, the output of the n th  stage forming the actual power supply voltage. 
         [0016]    The method may further comprise providing the first voltage as a feedback input to the step of generating the first voltage. 
         [0017]    The step of generating the second voltage may be further in dependence on the combined first and second voltages provided as a feedback signal. 
         [0018]    The step of generating the i th  generated voltage may be further in dependence on the combined voltage of the i stage provided as a feedback signal. 
         [0019]    The method may further comprise generating a further voltage in dependence on the unfiltered reference signal, and combining the further voltage with the combined first and second voltages to provide the power supply voltage. 
         [0020]    The method may further comprise generating a further voltage in dependence on the unfiltered reference signal, and combining the further voltage with the combined voltage of the n th  stage. 
         [0021]    In accordance with the invention there is also provided a method of generating a power supply tracking a reference signal, comprising the steps of: filtering, in a plurality n of filtering steps, the envelope signal, the filtering applied in each filtering step being different; generating, in a respective plurality n of voltage generation steps, a respective plurality of intermediate voltages in dependence on the respective filtered reference signals; receiving, in each of a plurality of n−1 voltage summation steps respectively associated with the 2 nd  to n th  voltage generation steps, the intermediate voltage generated in the respective generating step; receiving, in each of the plurality of n−1 voltage summation steps the output of the preceding summation step; generating, as an output of each summation step the sum of the two inputs; and providing the output of the n−1 th  summation step as the supply voltage. 
         [0022]    In successive filtering steps the filtering bandwidth may be successively broadened. 
         [0023]    The method may further comprise the steps of feeding-back the output of at least one summation step to the respective generating step, wherein the generating step generates the intermediate voltage in dependence on the feed-back output. 
         [0024]    The method may further comprise the step of feeding back the intermediate voltage generated in each of the generating steps to the input of generating step of the preceding generating step to thereby reduce a dc offset. 
         [0025]    In another aspect the invention provides a method of generating a power supply tracking a reference signal, comprising the steps of: filtering the reference signal; generating an intermediate power supply signal in dependence on the filtered reference signal; summing the intermediate power supply signal with a correction signal to provide an output power supply signal; subtracting the output power supply signal from the reference signal to generate an error signal; and generating the correction signal in dependence on the error signal. 
         [0026]    The method may further comprise the step of delaying the reference signal prior to performing the subtracting step. 
         [0027]    The delay may correspond to the delay of the filtering, generating and summing steps. 
         [0028]    The step of generating the intermediate power supply may be further adapted to remove a dc offset between the correction signal and the filtered signal. 
         [0029]    The step of generating the correction signal may comprise linearly amplifying the error signal. 
         [0030]    In accordance with a further aspect the invention provides an apparatus of generating a power supply tracking a reference signal, comprising the steps of: filtering the reference signal; generating a first voltage in dependence on the filtered reference signal; generating a second voltage in dependence on the reference signal; and combining the first and second voltages to provide a power supply voltage. 
         [0031]    The step of generating the first voltage may include tracking the filtered reference signal and the step of generating the second voltage comprises tracking the reference signal. 
         [0032]    The step of generating the second voltage may comprise subtracting the power supply voltage from the reference signal. 
         [0033]    The step of generating the second voltage may further comprise amplifying the subtracted signal. 
         [0034]    The step of generating the second voltage may include delaying the reference signal, the second voltage being generated in dependence on the delayed reference signal. 
         [0035]    The step of subtracting the power supply voltage from the reference signal may generates an error signal, and the step of amplifying the subtracted signal may amplifies the error signal to generate a correction signal, wherein the correction signal forms the second voltage. 
         [0036]    The steps of filtering the reference signal comprise: filtering the reference signal with a first filter bandwidth to provide a first filtered reference signal; and filtering the reference signal with a second filter bandwidth to provide a second filtered reference signal; the step of generating the first voltage being in dependence on the first filtered reference signal; and the step of generating the second voltage being in dependence on the second filtered reference signal. 
         [0037]    The second filter bandwidth may be broader than the first filter bandwidth. 
         [0038]    The step of filtering the reference signal may comprise: filtering the reference signal with n−2 further filter bandwidths to provide n−2 further filtered reference signals, wherein the total number of filtered reference signals is n; generating n−2 further voltages in dependence on the n−2 further filtered reference signals, wherein the total number of generated voltages is n; and combining the n−2 further voltages with the combined first and second voltages by: combining each of the further voltages in cascaded stages, wherein for the i th  stage, where i=3 to n, the i th  generated voltage is combined with the combined voltage of the i−1 th  stage to provide a modified power supply voltage, the output of the n th  stage forming the actual power supply voltage. 
         [0039]    The apparatus may further comprise providing the first voltage as a feedback input to the step of generating the first voltage. 
         [0040]    The apparatus may be adapted to generate the second voltage further in dependence on the combined first and second voltages provided as a feedback signal. 
         [0041]    The apparatus may be adapted to generate the i th  generated voltage further in dependence on the combined voltage of the i stage provided as a feedback signal. 
         [0042]    The apparatus may be adapted to generate a further voltage in dependence on the unfiltered reference signal, and combining the further voltage with the combined first and second voltages to provide the power supply voltage. 
         [0043]    The apparatus may be adapted to generate a further voltage in dependence on the unfiltered reference signal, and combining the further voltage with the combined voltage of the n th  stage. 
         [0044]    In an aspect the invention provides an arrangement for generating a power supply tracking a reference signal, comprising: a plurality n of voltage generation stages, each comprising: a filter for filtering the reference signal, wherein the bandwidth of each filter is different; and a voltage generation stage for generating an intermediate supply voltage in dependence on the filtered reference signal; a plurality n−1 of voltage summation stages, associated with the 2 nd  to n th  voltage generation stages respectively, each adapted to: receive as a first input the intermediate supply voltage generated by the respective voltage supply generation stage; receive as a second input the output of the preceding summation stage; and generate as an output the sum of the first and second inputs, wherein the output of the n−1 th  summation stage is the output supply voltage. 
         [0045]    In an aspect the invention provides an apparatus for generating a power supply tracking a reference signal, comprising of: means for filtering, in a plurality n of filtering steps, the envelope signal, the filtering applied in each filtering step being different; means for generating, in a respective plurality n of voltage generation steps, a respective plurality of intermediate voltages in dependence on the respective filtered reference signals; means for receiving, in each of a plurality of n−1 voltage summation steps respectively associated with the 2 nd  to n th  voltage generation steps, the intermediate voltage generated in the respective generating step; means for receiving, in each of the plurality of n−1 voltage summation steps the output of the preceding summation step; means for generating, as an output of each summation step the sum of the two inputs; and means for providing the output of the n−1 th  summation step as the supply voltage. 
         [0046]    In successive filtering steps the filtering bandwidth may be successively broadened. 
         [0047]    The apparatus may be adapted to feed-back the output of at least one summation step to the respective means for generating, wherein the means for generating generates the intermediate voltage in dependence on the feed-back output. 
         [0048]    The apparatus may further be adapted to feed back the intermediate voltage generated in each of the generating steps to the input of generating step of the preceding generating step to thereby reduce a dc offset. 
         [0049]    In another aspect the invention provides an arrangement for generating a power supply tracking a reference signal, comprising: a filter for filtering the reference signal; an intermediate power supply stage for generating an intermediate power supply signal in dependence on the filtered reference signal; a summer for summing the intermediate power supply signal with a correction signal to provide an output power supply signal; a subtractor for subtracting the output power supply signal from the reference signal to generate an error signal; and an amplifier for generating the correction signal in dependence on the error signal. 
         [0050]    The arrangement may further comprise a delay stage at the input to the subtractor for delaying the reference signal. 
         [0051]    The delay stage may be adapted to delay the reference signal by an amount corresponding to the delay of the filtering, generating and summing steps. 
         [0052]    The amplifier may comprise a linear amplification stage. 
         [0053]    The intermediate power supply stage may be an envelope tracking power supply stage for generating the intermediate power supply in dependence on the envelope of the reference signal. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0054]    The invention is now described by way of example with reference to the accompanying figures, in which: 
           [0055]      FIG. 1  illustrates an improved envelope tracking voltage supply stage in accordance with an embodiment of the invention; 
           [0056]      FIG. 2  illustrates an implementation of a power supply stage of the arrangement of  FIG. 1  in an embodiment; 
           [0057]      FIG. 3  illustrates a modification to the power supply stage of  FIG. 3  in a further embodiment; 
           [0058]      FIG. 4  illustrates an implementation of a linear amplification stage of  FIG. 1  in a further embodiment; 
           [0059]      FIG. 5  illustrates a voltage supply stage in accordance with an embodiment of the invention; 
           [0060]      FIG. 6  illustrates a modification to the voltage supply stage of  FIG. 5  in accordance with a further embodiment; 
           [0061]      FIG. 7  illustrates a modification to the voltage supply of  FIG. 6  in accordance with a still further modification; and 
           [0062]      FIG. 8  illustrates an exemplary implementation of a part of the voltage supply stage of the embodiments of any one of  FIGS. 5 to 7 . 
       
    
    
     DETAILED DESCRIPTION 
       [0063]    The invention is now described by way of example with reference to a number of exemplary embodiments. One skilled in the art will appreciate that the invention is not limited to the details of any embodiment described. In particular the invention is not limited to any specific technique for the implementation of an efficient power supply stage. Whilst a particularly efficient power supply stage is described in UK Patent No. 2398648, and is advantageously incorporated in embodiments of the invention, the invention is not limited to the use of such a specific efficient power supply stage. In general, the invention may preferably be implemented, in embodiments, utilising any efficient envelope tracking power supply stage. 
         [0064]      FIG. 1  illustrates the broad principles of an exemplary arrangement in accordance with one aspect of the present invention. 
         [0065]    With reference to  FIG. 1 , there is generally illustrated by reference numeral  118  an efficient power supply generation stage. As illustrated in  FIG. 1 , the efficient power supply generation stage  118  includes a filter  102  and an intermediate power supply stage  104 . The filter  102  is connected to receive at its input a reference signal on line  114 , and generate an output. The reference signal on line  114  is derived from, or represents, the envelope of a signal to be amplified. This signal may be derived from an envelope detection circuit. The output of the filter  102  forms an input to the intermediate power supply stage  104 . The intermediate power supply stage  104  is preferably an efficient power supply stage, which generates at its output a supply voltage for delivery to an amplifier stage. However, in accordance with the principles of this invention, the supply voltage generated by the intermediate power supply voltage stage  104  at its output is considered to be an intermediate supply voltage, and is further modified as is discussed further hereinbelow. 
         [0066]    It should be understood that the implementation of the intermediate power supply stage  104  may vary, but that a particularly preferred implementation is set forward in UK Patent No. 2398648. The implementation of the efficient supply stage  118  may also vary. In  FIG. 1  there is shown a single intermediate power supply stage  104 , with an associated filter  102  at its input. In other embodiments the efficient supply stage  118  may include multiple parallel or cascaded intermediate power supply stages  104 . However in accordance with the principles of the invention, where multiple intermediate power supply stages  104  are provided in parallel in the efficient power supply stage  118 , each of such stages will take its input through an associated filter, corresponding to input filter  102  associated with intermediate power supply stage  104 . 
         [0067]    Turning further to  FIG. 1 , it can be seen that the intermediate supply voltage generated at the output of the intermediate power supply stage  104  forms a first input to an adder or combiner stage  112 , and generates an output forming an input to a subtractor  108 . The subtractor  108  receives a further input from the output of a delay stage  106 . The output of the subtractor  108  forms an input to a linear amplifier  110 . The output of the linear amplifier  110  forms a further input to the adder  112 . The subtractor  108  is arranged to subtract the signal at the output of the adder  112  from the signal at the output of the delay stage  106 . The adder  112  is adapted to add the intermediate supply voltage signal at the output of the intermediate power supply stage  104  to the signal at the output of the linear amplifier  110 . The output of the adder  112  on a line  116  also forms a supply voltage, preferably for an amplifier stage, and is preferably connected to the drain/collector terminal of an RF amplifier transistor. 
         [0068]    The delay stage  106 , subtractor  108 , linear amplifier  110 , and adder  112  are thus combined and connected in combination with the efficient supply stage  118  to form a clean-up loop for the supply voltage stage, as will be discussed in further detail hereinbelow. Not all of these elements are essential in order to achieve the benefits of the invention, the essential elements being apparent from the following discussion. 
         [0069]    It should be noted that the generation of a supply voltage in accordance with the principles of this invention is not limited to the generation of a supply voltage for an RF amplifier arrangement, although it is particularly advantageous when used in such an arrangement. 
         [0070]    The intermediate power supply stage  104  represents an existing power supply stage that gives very good efficiency over a narrow bandwidth, but does not have either enough bandwidth or linearity for a desired application. As such, an additional loop based on the linear amplifier  110  is added. This additional loop adds a signal to the output of the existing power supply stage so as to produce a full bandwidth signal that is closer to the final desired output signal than the existing power supply stage is capable of producing. 
         [0071]    The signal to the intermediate power supply stage  104  is band limited by the filter  102  to ensure that the signal it processes is within the specified limits for the efficient operation of the power supply stage  104 . The voltage supply generated by the power supply stage  104  is then provided as an input to the combiner  112 , which additionally receives the output of the linear amplifier  110 . These two signals are added together to provide a supply voltage on line  116  for delivery to the power supply terminal of an amplifier stage. 
         [0072]    The modified output of the power supply stage provided on line  116  is additionally compared, in the subtractor  108 , with the reference signal on line  114  which represents the required final envelope signal. The subtractor  108  generates an error signal at its output, which forms an input to the linear amplifier, and the amplified version thereof provided to the summer  112  forms a correction signal for correcting the output of the power supply stage  104 . 
         [0073]    As such, the discrepancy between the required output signal to be delivered on line  116  and the voltage supply output provided by the power supply stage  104  is reduced. 
         [0074]    The filter stage  102  could be a low pass filter or a high pass filter. The purpose of the filter is to limit the bandwidth of the signal delivered to the intermediate power supply stage  104 , the specific frequencies which are filtered not being important. The bandwidth of the filter will be implementation-dependent, dependent upon the bandwidth which the intermediate power supply stage  104  is designed to efficiently process. The purpose of the filter  102  is to band-limit the signal delivered to the intermediate power supply  104 , so that such signal is efficiently processed. 
         [0075]    The delay stage  106  is provided in order to compensate for delays caused by the efficient supply stage  118 . This ensures that the signals provided to the subtractor  108  are time-aligned. In the event of an arrangement in which no time-misalignment occurs due to processing in other stages, or where some different compensation for time-misalignment is provided, the delay stage  106  may not be required. In addition the delay stage  106  is required to optimise performance, satisfactory performance being obtained without the delay stage  106  in certain implementations. 
         [0076]    With reference to  FIG. 2  there is illustrated an exemplary implementation of the intermediate power supply stage  104  of  FIG. 1 . This shows that the intermediate power supply stage  104  may comprise a switched supply  202  and a correction stage  204 . This structure is consistent with that described in UK Patent No. 2398648. One of a plurality of available supplies is selected by the switched supply  202  in dependence upon the filtered reference signal, and the correction stage  204  operates to reduce an error in the selected supply voltage. 
         [0077]    With reference to  FIG. 3  there is illustrated a further adaptation to the arrangement of  FIG. 1 . There is provided a feedback path from the output of the linear amplifier  110  to the input of the intermediate power supply  104 . The output of the linear amplifier  110  is fed to a control block  340 , which provides an output to a combiner  302 . The combiner  302  substracts the output of the control block  340  from the filtered reference signal at the output of the filter  102 , and the resulting combined signal then provides the input to the intermediate power supply stage  104 . This feedback into the efficient power supply stage removes any dc offset that would otherwise exist between the input and the output of the intermediate power supply stage  104 . This dc offset, when present, is caused due to a dc offset between the input to the intermediate power supply stage  104  and the output of the delay stage  106 . The control stage  340  provides the necessary dc offset compensation in dependence on the signal at the output of the linear amplifier  110 . 
         [0078]    Thus a measured signal is derived from the linear amplifier output that is fed into a further input of the efficient power supply stage, that ensures the efficient power stage does not have any dc or low frequency offset with respect to the linear amplifier. 
         [0079]    The additional features of  FIG. 3 , for the removal of dc offset, are only required when dc offset is present and its removal is required. If no dc offset is present, then the additional features of  FIG. 3  are not required. 
         [0080]    With reference to  FIG. 4  there is shown an exemplary implementation of the linear amplifier  110  of  FIGS. 1 to 3 . As illustrated in  FIG. 4 , the linear amplifier  110  is preferably implemented as an arrangement comprising an amplifier stage  402 , a loop filter  406 , and a combiner  404 . The output of the subtractor  108  forms a first input to the combiner  404 , and provides an output which forms the input to the amplifier  402 . The output of the amplifier  402  forms the input to the adder stage  112 , and additionally forms an input to the loop filter  406 . The output of the loop filter forms the second input to the combiner  404 . The combiner  404  operates to subtract the output of the loop filter from the output of the subtractor stage  108 . 
         [0081]    The linear amplifier  110  is preferably implemented as a class-AB amplifier  402 . The class-AB amplifier  402  is preferably a high bandwidth linear amplifier. 
         [0082]    Feedback is preferably provided around the class-AB amplifier by the loop filter  406 . In order to minimise power dissipation in the class-AB amplifier  402 , it is essential to minimise its output. Therefore in the preferred arrangement, to minimise the amplifier output, the loop filter  406  is used. 
         [0083]    The arrangements described with reference to  FIGS. 1 to 4  thus provide improvements over prior art techniques in allowing the efficient generation of a wideband power supply signal. The majority of the power is still handled by the efficient power supply stage  118 , and therefore efficiency is maintained at a reasonable level. Even if the filter  102  is a narrowband filter, efficiencies are still obtained. 
         [0084]    The additional loop based around the linear amplifier  110 , which may be referred to as a clean-up loop, has additional advantages. It allows the linearity of the power supply generation stage to be increased to thereby reduce distortion. Just reducing the distortion on its own would be a benefit, independent of whether wideband signal. Therefore the arrangement described has two advantageous benefits, and may be used to: (i) allow the efficient generation of a power supply signal with increased bandwidth; (ii) to facilitate the reduction of distortion; or (iii) to achieve both (i) and (ii). 
         [0085]    It should be noted, with reference to the embodiment of  FIG. 1 , that the output of the subtractor  108  is dominated by high frequencies because the intermediate supply stage  104  outputs the low frequency part of the output signal such that the extra loop based around the linear amplifier  110  provides for high frequency correction (on the assumption that the filter  102  filters the high frequency signal). 
         [0086]    The general principles of another aspect of the invention in accordance with a set of preferred embodiments are illustrated with respect to  FIG. 5 . It should be noted that, throughout the description, where elements in one Figure correspond to those in another Figure like reference numerals are used. 
         [0087]    In  FIG. 5  it can be seen that the efficient power supply stage  118 , previously shown in  FIGS. 1 to 3 , is implemented as a plurality n of efficient power supply stages denoted by reference numerals  118   1  to  118   n . Each includes a respective “intermediate” power supply stage, identified by reference numerals  104   1  to  104   n  respectively. 
         [0088]    Each efficient power supply stage  118   1  to  118   n  is associated with a respective filter  102   1  to  102   n . In general each filter  102  and power supply stage  104  combination can be considered a voltage generation stage, denoted by reference numerals  118   1  to  118   n . 
         [0089]    Each of the filters  102   1  to  102   n  receives the reference signal on line  114 . The filters are arranged such that they have different bandwidths. Thus the signal delivered to each of the intermediate power supply stages  104   1  to  104   n  is different in dependence upon the characteristics of the associated filters  102   1  to  102   n . 
         [0090]    In one arrangement, each filter may be arranged such that it filters a different set of frequencies. In another arrangement each filter may be arranged such that they are of successfully broader (or narrower) bandwidths. Thus the filter  102   1  may be a narrowband filter, the filter  102   2  being a wider bandwidth filter encompassing the bands of the filter  102   1 , and the filter  102   n  being a wideband filter but encompassing the bands of all previous filters. 
         [0091]    The more efficient a tracking power supply is, the higher the amount of distortion generated. If such a power supply handles a wide bandwidth, not only will the efficiency be compromised, but the distortion will be manifested over a much broader range of frequencies. Conversely, a linear stage will be able to handle a wide bandwidth stage with minimal distortion, but the efficiency will be poor. On account of this, the most efficient power supply stage will have a filter that restricts the signal input to the best signal bandwidth efficiency compromise, and since such a supply generates the most distortion, it is preferably placed at the top of the cascade so that subsequent supplies will suppress any distortion. As the cascade progresses towards the output, a progression of supplies that handle wider bandwidths with lower distortion and progressively lower efficiency is preferably used. The more linear power supplies towards the output of the cascade will remove some of the distortion created by the more efficient supplies further back, such that the final stage of the arrangement of  FIG. 4 , denoted by reference numeral  118   n , has less distortion to correct. 
         [0092]    In general the power supply stage  118  preferably includes n stages as illustrated in  FIG. 5 , where n is 2 or greater. 
         [0093]    As can be seen in  FIG. 5 , each filter  102   1  to  102   n  receives the reference signal on line  114 . The output of the respective filters forms the input to the respective intermediate power supply stages  104   1  to  104   n . The output of each supply stage  118   1  to  118   n , provided by the output of the intermediate power supply stages  104   1  to  104   n  respectively, is combined with the combined output of all previous stages in the cascade. For this purpose, each of the stages  118   2  to  118   n  is associated with a respective combiner or adder denoted by reference numerals  120   1  to  120   n-1 . Thus, as can be seen in  FIG. 5 , a first combiner  120   1  is associated with the supply stage  118   2 , and combines the output of the intermediate power supply stage  104   2  with the output of the intermediate power supply  104   1 . This combined output then provides a first input to a combiner  120   2  (not shown) which will combine this with the output of the intermediate power supply stage  104   3  (not shown). As shown in  FIG. 5 , the final combiner  120   n-1  combines the output of the intermediate power supply stage  104   n  with an output provided by a combiner  120   n-2  (not shown) which represents the cumulative supply voltage for all previous stages in the cascade. The combiner  102   n-1  provides the final output voltage on line  116  for the efficient power supply stage  118 . 
         [0094]    It should be noted that the arrangement of  FIG. 5  sets out an exemplary arrangement of the efficient supply stage  118  of  FIG. 1 . The arrangement of  FIG. 1  is not limited to the implementation of  FIG. 5 . Similarly, the arrangement of  FIG. 5  is not limited to the implementation if  FIG. 1 . The supply voltage of  FIG. 5  on line  116  may be provided directly to a power amplifier supply mode, or may form an input to the “clean-up” loop based around the linear amplifier  110  as shown in  FIG. 1 . 
         [0095]    Preferably, in the arrangement of  FIG. 5  one or more of the filters  102  incorporates a delay such that the outputs of respective voltage generation stages can be time-aligned, similar to the delay stage  106  of  FIG. 1 . 
         [0096]    With reference to  FIG. 6  there is illustrated a modification to the arrangement of  FIG. 5 , wherein each voltage generation stage  118   1  to  118   n  receives a feedback signal from the combined output of its associated combiner, to remove an error component from the input to the intermediate power supply stage. This removes a frequency portion of the signal to be handled by the intermediate power supply stage, such that each intermediate power supply stage can be implemented more efficiently. 
         [0097]    Thus, as can be seen in  FIG. 6 , each of the stages  118   1  to  118   n  is provided with an additional combiner  202   1  to  202   n , positioned between the respective filter  102  output and the output to the respective intermediate power supply stage  104 . Thus one input to each of the combiners  202   1  to  202   n  is taken from the output of the respective filter, and the output of the combiners  202   1  to  202   n  forms an input to the respective supply stages. A second input to the combiners  202   1  to  202   n  is derived from the cumulative supply determined at the output of the respective stage. For the first stage  118   1 , this is simply the output of the stage itself on line  130   1 , and this is fed back into the combiner  202   1 . For subsequent stages, this is the output of the associated combiner  120   1  to  120   n-1 . Thus, for example, for the voltage in supply stage  118   2 , the combiner  202   2  receives its second input from the output of the adder  120   1 , on line  132   1 . 
         [0098]    In  FIG. 6 , for the voltage generation stage  118 , there is also shown a feedforward path  204  from the output of the filter  102 , to the intermediate power supply stage  104   1 . This is an optional correction which may provide certain efficiencies: the feedforward path may reduce the signal processing burden on the intermediate power supply stage  104   1 . Although shown in the voltage generation stage  118  of  FIG. 6 , this is purely illustrative, and such a feedforward path may be provided in none, some, or all of the voltage generation stages  118   1  to  118   n . 
         [0099]    It can be seen that, in an arrangement in which n=2, and the filter  102   2  is an all-pass filter, the arrangement of  FIG. 7  is transformed to the arrangement of  FIG. 1 . 
         [0100]    With reference to  FIG. 7  there is illustrated a further modification to the arrangement of  FIGS. 5 and 6 , to allow for dc offset compensation. In this arrangement the outputs of the 2 nd  to n th  intermediate power supply stages  118   2  to  118   n  are fed back to the inputs respectively of the first to (n−1) th  intermediate power supply stages  118   1  to  118   n-1 , via control blocks  304 . Control blocks  304  are adapted to operate on the outputs of the intermediate power supply stages  104   2  to  104   n  to correct for a dc offset between the signals at the input to the intermediate power supply stages and the signals at the output thereof. 
         [0101]    Thus, as can be seen in  FIG. 7 , an additional combiner  302   1  to  302   2  is added to each of the stages  118   1  to  118   n-1 . These combiners take as a first input the intended input to the intermediate power supply stages, and as a second input the fed back output of the immediately succeeding intermediate power supply stage delivered through the control circuit  304   1  to  304   n  respectively. The output of the combiners  302   1  to  302   n  is then provided as the input to the intermediate power supply stage, with dc offset removed. 
         [0102]    The principle of dc offset correction in  FIG. 7  is the same as the principle of dc offset correction in  FIG. 3 . 
         [0103]    With reference to  FIG. 8  there is illustrated an exemplary implementation of a switched mode power supply circuit which may be implemented as the intermediate power supply stage  104   1 . Preferably the intermediate power supply stages  104   2  to  104   n  are implemented as fast, highly accurate power supply stages, either in combination with a switched supply stage such as that shown in  FIG. 8  or simply as correction stages. 
         [0104]    As can be seen in  FIG. 8 , the power supply stage  104   1  may include a subsidiary supply bank  802 , a switch array  804 , an inductor  806  having inductance value L, a capacitor  808  having capacitive value C, and one or more batteries  810 . The switch  804  is controlled to connect one of a plurality of supplies from the subsidiary supply bank  802  to the input of the inductor, and the inductor-capacitor combination  806 ,  808  operate to filter such signal and provide it at the output  412 . The filtering operation averages the signal selected by the switch supply. 
         [0105]    With reference to  FIG. 8 , the switched mode supply shown operates at a reduced bandwidth. The switched output of the stage will therefore be reduced in comparison with the final envelope of the output voltage supply generated by the overall stage. Thus it may be possible to connect the switched output supply stage directly to the battery rather than just to the outputs of a switched mode supply. The arrangement of  FIG. 8  is designed to be adaptive so that as much power as possible is drawn direct from the battery. This means that one stage of power conversion losses is reduced. 
         [0106]    The combiners  120  of  FIGS. 5 to 7  may be implemented, in a preferred embodiment, by suitable combinations of inductors or transformers. 
         [0107]    The invention has been described with reference to particular embodiments in order to convey an understanding thereof. One skilled in the art will appreciate that the invention is not limited to the details of any specific embodiment described. In addition the features of any embodiments may be utilised in isolation or combination.