Abstract:
In a method and system in accordance with the present invention, solder balls are added on top of vertically integrated MEMS with CMOS by using wafer scale fabrication compatible with existing chip scale packaging capabilities. In the present invention, both the MEMS and the CMOS dies are fabricated in equal dimensions. On the MEMS level, silicon islands are defined by DRIE etching to be bonded on top of CMOS pads. These conducting silicon islands later provide electrical connections between the CMOS pads and the conducting traces that lead to solder balls on top.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to sensors and more particularly to MEMS sensors utilized with electronics. 
     BACKGROUND OF THE INVENTION 
     Packaging for microelectronics and MEMS are one of the most important production steps before bringing the product into the market. Various packaging technologies have been developed for integrated circuits and MEMS. Initial MEMS devices used the technologies developed by IC industry. On the other hand, advances in the MEMS technologies offer a tremendous contribution to microelectronic integration and packaging. Historically, all the newly introduced packaging technologies enabled lower footprint and lower cost. Chip scale packaging (CSP) is the latest development where the final footprint of the device is fundamentally determined by the active die itself. 
     CSP for ICS 
     The term chip scale package was first introduced in 1994. It is defined as a package that has an area which is no more than 1.2 times the area of the active die. CSPs offer many advantages such as smaller size, lesser weight, relatively easier assembly process, lower cost, improved electrical performance due to lower parasitics. Chip scale packaging combines the strengths of various packaging technologies. For example, it offers the size and performance advantage of bare die attachment and the reliability of encapsulated devices. The significant size and weight reduction makes the CSP ideal for use in portable devices like cell phones, laptops, pocket computers, and digital cameras. 
     Various CSP technologies have been developed by different companies. These can be grouped under four major categories according to CSP structure: 
     1. Rigid interposer type. The die is flip-chip attached to a rigid printed circuit board (PCB) fabricated using advanced technologies that can accommodate the pitch and clearance requirements of the die. The interposer translates the die pad pitch into a rather large interconnect pitch. Mini BGA (IBM), Small Form (LSI logic), Flip chip BGA (Sony) are some of the package names used by different companies. 
     2. Flexible interposer type. This type is very similar to the first type except the material used for the interposer. Common materials for the interposer are liquid-crystal polymer and polyimide. Some of the package names are chip on flex (GE), fine pitch BGA (Nec), F. GBA (Sharp). 
     3. Custom lead frame type. In this type, frame leads are directly attached to the die pads. Small outline non-lead (Fujitsu), Lead on chip (Hitachi), Bottom lead package (LG) are some of the package names introduced by various companies. 
     4. Wafer-level assembly type (Wafer Level Chip Scale Package) (WLCSP). This type of package is substantially or completely constructed before the wafers are sawed into dies. Obviously, packaging the ICs at the same IC manufacturing site has many economic advantages. It eliminates wafer probing tests since these can now be achieved at the part level. It reduces or eliminates the costs associated with individual packaging of the parts like shipping the wafer overseas for packaging. And finally, it provides manufacturers the complete control over IC production. The next section will discuss the WLCSP in more detail below. 
     Wafer Level Chip Scale Packaging for ICs 
     Wafer level Chip Scale Packaging is the latest packaging technology. This technology comes in a variety of types. There are basically four different Wafer Level Chip Scale Packaging technology classifications. 
     1. Redistribution layer and bump technology. This is the most widely used technology. In this technology, first the IC surface is repassivated by one or more layers of a photo patternable polymer such as BCB (benzocyclobutene). This later provides protection for the die from external environment. It also allows multiple metal traces for routing between the solder bumps and the IC pads. Next, the redistribution layer is defined through sputtered and evaporated metals followed by a lift-off process. This layer can also be defined by electroplating. Finally, solder bumps are formed using electroplating on a UBM stack on the redistribution layer. 
     2. Encapsulated copper post technology. This is very similar to the redistribution and bump technology except that the redistribution layer routes the connections from IC pads to copper posts defined by sputtering/etching or electroplating techniques. After defining the copper posts, the IC surface is encapsulated in low stress epoxy by transfer molding. The epoxy coating leaves the top portions of the copper posts exposed. Later, standard solder bumping process is applied to solder balls on top of these posts. 
     3. Encapsulated wire bond. Similar to the two previous techniques, a redistribution layer is used to increase the IO pitch to the desired level. Then, S-shaped gold wires are placed on the redistribution pads using a modified wire bonder. These wires are later soldered to the PCB during the assembly. 
     4. Encapsulated beam technology. The packaging process starts by attaching a glass plate to the IC by means of an adhesive layer such that the active surface of the CMOS faces the glass plate. The CMOS is diced into dies by using either chemical etching or mechanical cutting while the die is attached to the glass plate. Then, the second glass plate is attached on top by another adhesive layer, preferably epoxy, filling the dice channels. Wafer sawing the second plate and CMOS reveals the edges of the IC pads. The routes between these conducting edges and the solder balls that will be placed on the second plate are defined by metal sputtering, patterning and etching. In this approach, the solder balls are placed on the back side of the CMOS. This packaging method provides a clear view for the active CMOS surface where an image sensor or a light detector can be placed. With slight variations in the packaging process, solder balls can be placed on the top side of the CMOS. 
     Packaging for MEMS 
     Packing requirements for MEMS are much more complex than IC packaging requirements. For example, optical sensors require transparent packaging such that the package does not attenuate the optical signals. On the other hand, an acoustic sensor needs to be accessible from outside through a finely engineered opening that allows maximum transmission of sound waves while blocking dust and wind. MEMS inertial sensors require hermetic sealing. Therefore, packaging of MEMS devices reveals itself in many novel designs and techniques. 
     The simplest approach to package a MEMS device is to place the sensor in a housing and provide electrical connections through wire bonding between the leads of the housing and the MEMS die. The housing should protect the moving parts from environmental effect such as humidity and dust. Hermetical or non-hermetical packages can be used for these purposes. Typical housing materials are metal, plastic or ceramics. However, this approach results in relatively large footprints and these packages are not suitable for the consumer applications where reduction in size is very desirable. Moreover, for MEMS devices that require low pressure this approach is not practical. 
     Wafer Level packaging for MEMS 
     Above problems can be partially or completely solved by achieving some part of the packaging at the wafer level. Various techniques have been proposed for wafer level packaging of MEMS devices. For example, a silicon cap bonded at the wafer level has been used to provide triple-level polysilicon surface micromachined accelerometer. Low temperature glass frits have been used to achieve the bonding. The cap provides mechanical protection for the accelerometer such that the sensor can be later packaged in a conventional injection molded plastic package. VTI technologies from Finland use triple-stack anodic bonding for their commercial accelerometers. Three wafers are bonded together to form a hermetically sealed cavity at the center. The seismic mass is defined in the center wafer. Upper and lower wafers have a thin glass layer on their surfaces. The glass layers provide the anodic bonding. There are also other similar wafer level packaging technologies developed to companies such as ST, Bosch and ADI. But none of these achieves both packaging of MEMS and integration with CMOS electronics at the same time. The connections between the MEMS and CMOS are enabled through wire bonding. This results in increased cost. The most successful packaging and integration method for MEMS has been introduced by Nasiri et al. in U.S. Pat. Nos. 6,939,473 and 7,104,129 (hereinafter, the Nasiri-fabrication process). The Nasiri-fabrication process includes a special SOI wafer where recesses formed in the handle layer. The MEMS device is defined in the device layer using DRIE. Then, the SOI wafer with the device definition is bonded directly to the aluminum layer on the CMOS wafer, without addition of any other material layers on top of the aluminum. The bonding is performed at low temperature using eutectic metals. In one bonding step, the Nasiri-Fabrication provides for a wafer-scale integration, by making electrical interconnects between the MEMS and CMOS, and wafer-scale packaging by providing a fully hermetic sealing of the sensitive MEMS structures at the same time. The finished wafer then goes through yet another patented and proprietary pad opening step that uses a standard saving technique to remove unneeded MEMS silicon that covers electrical pads. Finished wafer are then tested on standard automated wafer probers. The subsequent packaging can readily be completed cost effectively in plastic packages at any industry standard contract assembly house, avoiding the need for more costly and customized ceramic and/or multichip packaging alternatives. 
     Although the Nasiri fabrication platform successfully addresses the most of the packaging needs of the consumer products, emerging applications and portable products are demanding further miniaturization of MEMS sensors. Portable electronic devices are getting smaller and more feature rich. This requires further size reductions for MEMS sensor ICs in height. The key requirement for portable electronics, especially for handsets, is a maximum of 1 mm device height which is difficult to achieve using plastic or ceramic packages for MEMS. In today&#39;s mobile handset market the trend is to provide high performance, low cost components with integration of functionality and small form factor. Wafer scale chip scale packaging provides smaller and very cost effective devices for these applications. Therefore, it is the technology of choice for handset market. 
     Wafer Level Chip Scale Packaging for MEMS 
     Wafer Level Chip Scale Packaging technologies can also be applied to the MEMS devices. For this purpose, various techniques have been developed. Shiv et al, in “Wafer Level Chip Scale Packaging for MEMS,” developed a cap wafer with micro vias and Au/Sn seal ring that will provide eutectic bond to the MEMS/CMOS wafer. The process starts with an SOI wafer. The cavity and the vias are defined in the device layer. Later the device layer is covered by a passivation layer (oxide). The seal ring and micro vias are coated by electroplated Au/Sn solder. The cap wafer is then soldered to the MEMS/CMOS wafer. The cap wafer is etched from the handle side to provide access to the micro vias. This opens the ends of the vias. The solder balls that are placed on the back side of the cap are connected to the open ends of the vias. This approach has some draw backs. The cavity in the cap wafer can not be too deep. This limits the use of this method mostly to the surface micromachined devices. Also the cap height can not be made too high since the solder balls need to be placed on this side. In addition, this technique does not address the stress issues due to the different thermal expansion coefficients of PCB and silicon. 
     At Philips, there has been development effort for Wafer Level Chip Scale Packaging for their RF-MEMS components. In this approach, the MEMS devices are capped by another thin silicon piece which has solder on it. However, the capping is not done at wafer level, rather chip-to-chip solder bonding is used. Later solder balls are placed on the MEMS wafer. Although, the solder bumping is done at the wafer level, this approach is not true wafer level chip scale packaging. Therefore, it results in increased manufacturing cost. Moreover, the cap and the solder balls are on the same side of the wafer. This imposes limits on the solder size and cap size. 
     Fraunhofer IZM has also developed a Wafer Level Chip Scale Packaging technology. First, the cavities are defined on the cap wafer. Then seal rings are defined by depositing solder on the wafer. The cap wafer and the MEMS/CMOS wafer are aligned together under an IR aligner. The sandwiched wafer is brought into a reflow oven for soldering. After the soldering, back side grinding is performed to reduce total package height. The pads on the MEMS/CMOS wafer are exposed either by a pre-structured cap wafer or controlled dicing of the cap wafer without damaging the MEMS/CMOS wafer. The connections between the device pads and the solder balls are achieved by wire bonding from the pads to the top of the cap. Later, the wire bonds are covered with a liquid encapsulant and the dies are singulated using a wafer saw. Although this technology uses mature techniques, it has some drawbacks. For example, wire bonding limits the minimum distance between the dies resulting in increased footprint. Moreover, it is suitable only in surface micromachined devices. 
     Shellcase uses WLCSP for ICs as well as optic components. Their packaging technology is also suitable for MEMS devices. In this approach, first cavities are defined in SU8 layer deposited on a packaging substrate. The channels between the SU8 cavities are filled with epoxy. These epoxy filled channels are aligned over the MEMS/CMOS pads and the two substrates are brought together under pressure. After the epoxy is cured, the MEMS/CMOS wafer is etched from the back side, until the device pads are exposed. At the end of this step, the MEMS/CMOS dies are also singulated. A second packaging substrate is glued on the back side of the CMOS. The second substrate and the MEMS/CMOS die are then sawed by a wafer saw such that the edges of the pads are exposed close to the bottom of the cavities. Later, metal deposition makes contacts between these edges and the solder balls on the top of the second substrate. The major drawback of this approach is that it cannot provide a true hermetic seal for MEMS. Moreover, it is only applicable for surface micromachined devices. 
     None of the above technologies can address the wafer level chip size packaging need for bulk micromachined integrated MEMS with electronics while keeping the size small at reduced cost. The present invention addresses such as need. 
     SUMMARY OF THE INVENTION 
     In a method and system in accordance with the present invention, solder balls are added on top of vertically integrated MEMS with CMOS by using wafer scale fabrication compatible with existing chip scale packaging capabilities. In the present invention, both the MEMS and the CMOS dies are fabricated in equal dimensions. On the MEMS level, silicon islands are defined by DRIE etching to be bonded on top of CMOS pads. These conducting silicon islands later provide electrical connections between the CMOS pads and the conducting traces that lead to solder balls on top. Getting the electrical connections to the MEMS level from CMOS level eliminates the need for tab removal which is required for exposing pads. The key ideas differentiating this patent from the previous Wafer Level Chip Scale Packaging methods are summarized below: 
     1. Using conducting silicon islands over CMOS pads to provide electrical connections on the MEMS level. This simplifies the fabrication process. 
     2. The epoxy filling around the silicon islands over the CMOS pads. This enables further ruggedness to the fabricated devices. 
     3. Achieving true hermetic sealing during the wafer level packaging for MEMS. 
     4. The final device size is truly determined by the CMOS size. 
     5. Completely compatible with existing fabrication techniques and make use of minimum allowable dicing street dimensions. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1A  shows the cross section of vertically integrated MEMS with CMOS fabricated according to the Nasiri fabrication process. 
         FIG. 1B  shows the chip scale fabrication process starting with wafer thinning. 
         FIG. 1C  shows an optional aluminum deposition step. 
         FIG. 1D  shows a detailed picture of the silicon pads and the seal ring. 
         FIG. 1E  shows the top view of the structure. 
         FIG. 1F  depicts the DRIE etching step. 
         FIG. 1G  depicts the first aluminum deposition. 
         FIG. 1H  shows the aluminum layer being patterned typically by conventional photolithographic techniques to remove it from the silicon pads. 
         FIG. 1I  shows the oxide etching step. 
         FIG. 1J  shows the top view after oxide etching. 
         FIG. 1K  shows the epoxy deposition. 
         FIG. 1L  shows glass layer bonding. 
         FIG. 1M  shows a polymer layer being deposited and patterned leaving polymer posts on the glass plate. 
         FIG. 1N  shows wafer sawing that exposes the conducting silicon pads. 
         FIG. 1O  shows the second aluminum deposition making the ground connection. 
         FIG. 1P  shows aluminum patterning. 
         FIG. 1Q  shows electroless nickel/gold deposition. 
         FIG. 1R  shows solder mask deposition. 
         FIG. 1S  shows the solder mask patterning. 
         FIG. 1T  shows the solder ball forming. 
         FIG. 1U  shows the wafer sawing to singulate the devices. 
         FIG. 2  shows an alternative geometry for  FIG. 1E  where silicon walls are placed between the silicon pads. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The present invention relates generally to sensors and more particularly to MEMS sensors utilized with electronics. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein. 
     The following describes the fabrication process for Wafer Level Chip Scale Packaging for Nasiri fabrication platform. 
       FIG. 1A  shows the cross section of vertically integrated MEMS with CMOS structures  100  fabricated in accordance with the method described by Nasiri et al. The structure  100  includes three layers, a MEMS cover  102 , an actuator (MEMS) layer  104  and a CMOS substrate  106 . The actuator layer  104  is bonded to the cover  102  by fusion bonding and it is bonded to the CMOS substrate  106  by eutectic Al/Ge bond  112 . The structure  100  includes silicon islands  108  bonded on CMOS pads  110  by Al/Germanium alloy  112  for the electrical connection between the CMOS pads  110  and solder balls (not shown). To describe the chip scale fabrication techniques, refer now to the following description in conjunction with the accompanying Figures. 
     Step 1. Wafer thinning. The chip scale fabrication process starts with wafer thinning as shown in  FIG. 1B . The MEMS cover  102  is thinned down to preferably 150 microns. CMOS substrate  106  thinning is optional depending on the final height requirement. 
     Step 2. Aluminum deposition (optional).  FIG. 1C  shows an aluminum deposition step. This step can also be performed after DRIE etching of MEMS cover  102 . Depending on when the deposition is done, the area of the ground shield changes. For the rest of the fabrication steps, the aluminum deposition  202  is assumed to be done after the DRIE step. 
       FIG. 1D  shows a detailed picture of the CMOS pads  110  and the seal ring  115 . Initially, the silicon on pads  108  are shared between the neighboring parts forming a bridge over the dice channels  150 . As the rest of the actuator layer  104 , the pads  108  are fusion bonded to the MEMS cover  102  and eventually bonded to the CMOS pads  110 . A passivation layer  119  covers the CMOS area except on the pad openings and dice street  150 . 
     The top view of the structure is depicted in  FIG. 1E . The silicon on pads  108  are electrically isolated from the rest of the actuator layer  104  by removing the silicon during the actuator layer definition and by forming isolation channels  123  as shown in the figure. Actuator layer definition is described, for example, in the Nasiri fabrication process. 
     Step 3. DRIE etching.  FIG. 1F  depicts the DRIE etching step. First, the MEMS cover  102  is covered by photoresist which is later patterned photo lithographically to expose the area that is going to be etched. After DRIE, grooves  155  are formed over the silicon on pads  108 . The DRIE stops on the oxide layer  121 . At the end of the etch cycle, the oxide layer  121  is exposed on the bottom of the grooves  155 . The oxide layer  121  forms membranes when there is no actuator layer underneath. The membrane geometry is defined by the cross sectional area of the isolation channels  123  in the actuator layer  104  and the bottom surface of the grooves  155 . 
     Step 4. Aluminum deposition.  FIG. 1G  depicts the first aluminum deposition  302 . As mentioned earlier, this step can be performed before DRIE. The deposited aluminum  302  covers everywhere. The membranes of the oxide layer  121  prevent aluminum from getting into the isolation trenches. 
     Step 5. Aluminum patterning. Following the deposition, the aluminum layer  302  is patterned typically by conventional photolithographic techniques to remove it from the silicon on pads  108  ( FIG. 1H ). Since the wafer surface has topography, electroplated photoresist can be used to cover the aluminum surface. This photoresist can be patterned using a shadow mask in the grooves. On the ground pad  306  a small portion of the aluminum can be left. After wafer sawing, the edge of the aluminum is exposed and makes contact with a second aluminum layer which is short circuited to the ground pad  306 . 
     Step 6. Oxide etching.  FIG. 1I  shows the oxide etching step. The photoresist mask that was used to pattern aluminum can also be used as the oxide mask layer. Oxide on the silicon on pads  108  can be etched in an HF or a BOE solution. 
       FIG. 1J  shows a top view after oxide etching. After oxide etching, the isolation channels  123  become accessible. The first aluminum deposition  302  covers most of the area including top and slanted surfaces. This layer  302  will be used for shielding. As shown in the Figure, a small portion of the aluminum  302  extends over the silicon on pad  108 . The aluminum edge on the silicon on pad  108  will be connected to the ground pad  306  via a second aluminum deposition. 
     Step 7. Epoxy deposition. The next step in the fabrication is the epoxy deposition  402  ( FIG. 1K ). The epoxy  402  can be spray coated, curtain coated, or spin coated. The epoxy  402  will fill the grooves  155  and isolation trenches within the actuator layer  104 . 
     Step 8. Glass layer bonding. After pre-curing, a layer of glass plate  406 , preferably 100 microns thick, is bonded over epoxy  402  leaving 10 to 20 micron thick epoxy  402  between the MEMS cover  102  and the glass plate  406  ( FIG. 1L ). Applying pressure over the glass plate  406  also helps to fill in the isolation trenches. 
     Step 9. Polymer deposition and patterning. In the next step, as shown in  FIG. 1M , a polymer layer is deposited and patterned leaving polymer posts  408  on the glass plate  406 . Later solder balls will be placed on these polymer posts  408  whose function is to relieve a portion of the stress due to the PCB mounting. 
     Step 10. Wafer sawing to form a notch.  FIG. 1N  shows wafer sawing that exposes the conducting silicon on pads  108 . At this step, the edge of the first aluminum  302  also becomes accessible on the ground pad  306 . The notch angle with normal is approximately 30 degrees. 
     Step 11. Aluminum deposition. The second aluminum deposition  410  ( FIG. 1O ), makes the ground connection. 
     Step 12. Aluminum patterning. For non-ground pads, the patterned aluminum enables the connections between the solder balls and silicon on pads  108  ( FIG. 1P ). The aluminum layer  410  is patterned by a suitable photolithographic method, preferably by deposition of electroplated photoresist followed by shadow masking. 
     Step 13.  FIG. 1Q  shows electroless Nickel/Gold deposition  412 . Electroless deposition of Nickel/Gold covers the aluminum traces. 
     Step  14 .  FIG. 1R  shows a solder mask deposition. Solder mask  414  can be deposited by any suitable method such as spraying, screen printing or spin coating. 
     Step  15 . Solder mask patterning. Solder mask  414  is later patterned ( FIG. 1S ) to expose the pad openings. 
     Step  16 .  FIG. 1T  shows a solder ball  416  forming. Solder is deposited over the wafer. Solder flow forms the balls  416  over the pad openings. 
     Step  17 . Wafer sawing to singulate the devices.  FIG. 1U  shows the top view of one of the devices. 
       FIG. 2  shows another variation, in which one may place silicon pieces (or plates) extended between the silicon on pads  108 . 
     DESCRIPTION OF VARIATIONS AND ALTERNATE EMBODIMENTS 
     There are variations of the structure and the fabrication process described above. 
     1. One variation is that the first aluminum can be deposited before the DRIE step. In this case, only the top surface of the MEMS cover will be shielded. The ground connection to this shield can be picked up along the short edge of the die. A shallow wafer sawing of epoxy reveals the edge of the aluminum shield. In this case, this wafer sawing should be performed before the second aluminum deposition. The second aluminum deposition makes a connection to the shield along the edge and routes the ground connection to the solder ball reserved for ground. Alternatively, the oxide on the ground pad can be removed by using an additional oxide mask. This allows depositing the first aluminum directly on the ground pad. 
     2. In another variation, one may place silicon pieces (or plates) extended between the silicon on pads  108  as shown in  FIG. 2 . These additional silicon pieces increase the electrical isolation between  108  the pads. The silicon island and plates are all defined during the MEMS definition using DRIE. 
     Features 
     The MEMS package has several features that may be included therein. They are listed below. The third substrate may be silicon, glass or quartz. The bond between the second substrate and the CMOS substrate may be a eutectic Al/Ge bond between Ge and on the stand offs and Al on the CMOS. 
     The bond between the second substrate and the CMOS substrate may be a soldering between Au/Sn on stand offs and CMOS where the pads are coated Cu, Ti/Cu, Au, TI/Au, Cr/Au, Ni, or Cr/Ni. 
     The third substrate may have an aluminum shield on top and on side edges to prevent EMI coupling and to reduce parasitic coupling. The third substrate may have an aluminum shield only on top to prevent EMI coupling and to reduce parasitics. The fourth substrate may have an aluminum shield on top under the solder balls and on the edge surfaces to prevent EMI coupling. There may be grounded silicon isolation between interconnects. The edge surfaces may be designed in an angle to facilitate easy fabrication and deposition of the interconnects and lithography. 
     The MEMS package may include aluminum, copper, doped poly silicon, or any other conducting material. The MEMS package may include an isolation layer between the fourth substrate and the third substrate made of epoxy, BCB, polyimide, or solder mask. The MEMS package may include an isolation layer between the fourth substrate and the top conducting layer made of epoxy, BCB, polyimide, or solder mask. The MEMS package may be compatible with creating hermetically seal for the MEMS. The MEMS package may be compatible with wafer scale packaging. 
     The third substrate may be thinned down to 150 micro-meters. The fourth substrate may be nominally 100 micro-meters. The MEMS package may have a cover thinned down to 150 micrometers. The first substrate may be thinned down to 250 micro-meters. The MEMS package may include conducting traces between the solder balls and the conducting bond material on the silicon interconnect standoffs. 
     Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.