Abstract:
A reference voltage circuit for a differential analog-to-digital converter wherein a first reference voltage source is connected to a midpoint of a resistive ladder for the analog-to-digital converter. A master module may regulate the voltage over an auxiliary resistor connected to the first reference voltage source and to a second reference voltage source. The regulated current in the auxiliary resistor may be scaled and copied into a current which is sourced into the top of the resistive ladder and also scaled and copied into a second equal current which is sinked from the bottom of the resistive ladder. Decoupling capacitors may be placed so as to improve the power supply ripple rejection to the resistive ladder.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority from U.S. Provisional Application entitled “REFERENCE VOLTAGE CIRCUIT FOR DIFFERENTIAL ANALOG-TO-DIGITAL CONVERTER (ADC)”, filed Nov. 8, 2000, application Ser. No. 60/247,401, which is hereby incorporated by reference. 
    
    
     BACKGROUND 
     The present application describes systems and techniques relating to reference voltage circuits for differential analog-to-digital converters (ADCs), for example, flash ADCs used in image sensors. An ADC is an electronic circuit that measures an analog signal, which typically represents some real-world phenomenon (e.g., temperature, pressure, incident light, acceleration, speed), and converts it to a digital signal by comparing the analog signal to a known reference voltage. 
     FIG. 1 is a functional block diagram illustrating a prior art design  100  for providing a differential reference voltage for an ADC. The design  100  uses a resistive ladder  102  with a differential analog input reference that may be provided by voltage controlled current sources  104 . The design includes circuits with either non-regulated or regulated high and low voltages V ADC     —     HIGH , V ADC     —     LOW  set up around a common-mode voltage. The input references may be regulated by voltage regulators  106 ,  108 , according to reference input voltages V REF     —     HIGH , V REF     —     LOW    
     FIG. 2 is a schematic illustrating an example circuit  200  implementing the prior art design  100  shown in FIG.  1 . In FIG. 2, an amplifier AMP, regulates the voltage V ADC     —     HIGH  according to a reference input V REF     —     HIGH . An amplifier AMP 2  regulates the voltage V ADC     —     LOW  according to a reference input V REF     —     LOW . Resistors R 1 , R 2 , R 3 , R 4  constitute a resistive ladder  202  for the ADC. A capacitor C 3  is a differentially connected decoupling capacitor for the ladder,  202 . Capacitors C 1  and C 2  are phase compensating capacitors for regulators  206 ,  208 , respectively. 
     SUMMARY 
     In one aspect, a reference voltage circuit for an analog-to-digital converter includes a resistive ladder having an even number of resistors and a midpoint between the resistors and a reference voltage source coupled to the midpoint. The resistive ladder may include four, eight, or more resistors. The reference voltage source may be a regulated voltage source that will accept both input and output currents. The reference voltage source may differ from a common-mode voltage of the analog input signal to the analog-to-digital converter by a small amount, such as by less than one half a least significant bit (½ LSB) of the analog-to-digital converter. 
     The reference voltage circuit may also include a reference resistor coupled with the reference voltage source, a voltage-controlled current source coupled with the reference resistor, a voltage regulator coupled with the first voltage-controlled current source, and a low voltage source coupled to the voltage regulator. The voltage regulator may be an amplifier coupled in a feedback loop with the voltage controlled current source. The reference voltage circuit may also include a current mirror coupled with a power supply, the voltage regulator, and the resistive ladder, wherein the current mirror scales current in the resistive ladder by a factor of eight. Resistance matching may be provided between the reference resistor and a total combined series resistance of the resistive ladder. 
     In another aspect, an analog-to-digital converter may be manufactured, such as on a semiconductor substrate, to include a reference voltage circuit having a resistive ladder and a reference voltage source connected with a midpoint of the resistive ladder. The analog-to-digital converter may also include a plurality of comparators coupled with the resistive ladder, and a digital output encoder. 
     In another aspect, a method includes forming on a substrate, a resistive ladder having an even number of resistors and a midpoint between the resistors, and connecting a reference voltage source to the midpoint. The method may further include forming a reference resistor on the substrate, forming a first voltage-controlled current source on the substrate, forming a voltage regulator on the substrate, connecting the reference resistor with the reference voltage source, connecting the first voltage-controlled current source with the reference resistor, and connecting the voltage regulator with the first voltage-controlled current source and with a low voltage source. The method may also include connecting an amplifier in a feedback loop with the first voltage-controlled current source, where the amplifier is the voltage regulator. 
     In another aspect, a method includes applying a reference voltage to a midpoint of a resistive ladder in a circuit to create a plurality of reference voltages for an analog-td-digital converter. The method may further include providing a power source for the circuit, and providing a ground for the circuit. The method may also include providing an analog input to a plurality of comparators coupled with the resistive ladder to generate a digital output. 
    
    
     DRAWING DESCRIPTIONS 
     FIG. 1 is a functional block diagram illustrating a prior art design for providing a differential reference voltage for an ADC. 
     FIG. 2 is a schematic illustrating an example circuit implementing the prior art design shown in FIG.  1 . 
     FIG. 3 is a functional block diagram illustrating a design for providing a differential reference voltage for an ADC. 
     FIG. 4 is a schematic illustrating an example reference voltage circuit implementing the design shown in FIG.  3 . 
     FIG. 5 is a schematic illustrating an example ADC circuit using the reference voltage circuit of FIG.  4 . 
     FIG. 6 is a schematic illustrating an example circuit implementing the design shown in FIG.  3 . 
     FIG. 7 is an illustration showing a graphical output display for a simulation of transient response time of the regulator in the example circuit of FIG.  6 . 
     FIG. 8 is an illustration showing a graphical output display for a simulation of transient responses from a pulse on a power supply node in the example circuit of FIG.  6 . 
    
    
     Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features and advantages may be apparent from the description and drawings, and from the claims. 
     DETAILED DESCRIPTION 
     The systems and techniques described here relate to reference voltage circuits for differential ADCs. The description that follows discusses reference voltage circuits in the context of two-bit ADCs, but may apply equally in other contexts. For example, the reference voltage circuits described here may be implemented with larger resistive ladders and/or may be used with multiple ADCs, such as with a photo sensor built on a single chip substrate. 
     As discussed in the background section of this application, FIGS. 1 and 2 illustrate a prior art design  100  and an example circuit  200  for providing a differential reference voltage for an ADC. One of the disadvantages of the design of FIGS. 1 and 2 is poor power supply ripple rejection (PSRR). For example, referring to FIG. 2, an increase in a transient voltage on VDD may cause an increase in the current I 1  through the resistive ladder and a displacement current in the decoupling capacitor C 3 . This, in turn, may cause an upper regulator  206  to decrease the current through transistor MP. 
     However, a lower regulator  208  also observes an upward-going voltage on the node V ADC     —     LOW . Therefore, the lower regulator  208  may try to increase the current through transistor MN and the resistive ladder  202 . Hence the two regulators  206 ,  208  take opposite actions. Depending on the bandwidth of the two regulators, their inherent power supply ripple rejection and the frequency spectrum of the power supply noise, this regulator system may tend to amplify the power supply ripple. An ADC ladder biasing method and circuit as disclosed in this application, may have a better power supply ripple rejection. 
     The ladder resistors in FIG. 2 should be low-impedance so that there is a relatively low resistive path from the two quarter positions QP 1 , QP 2  of the ladder, to the differential decoupling capacitor C 3 . The path should also be low resistive between the two quarter positions QP 1 , QP 2 . The quarter positions QP 1 , QP 2  represent the worst-case high impedance points that need to be decoupled properly. Therefore, there may be significant power dissipation in such a biased resistive ladder. 
     FIG. 3 is a functional block diagram illustrating a design  300  for providing a differential reference voltage for an ADC. The design  300  sets up the voltage over a resistive ladder  302  by connecting the ladder&#39;s midpoint  304  to a voltage source  306  (V REF ). The voltage source  306  would typically be very close to the common-mode voltage of the differential ADC and the signal amplifier(s) prior to the ADC. This voltage source  306  is preferably regulated and will accept both input and output currents. 
     The design  300  may include a reference resistor R REF , a voltage regulator  308 , and multiple voltage controlled current sources  310 ,  312 . Those voltage controlled current sources  312  that are on either side of the resistive ladder  302  may be scaled by a factor of eight over the other voltage controlled current sources  310 , as discussed further below. Equal currents are sourced into the top of the ladder  302  (at V ADC     —     HIGH ) and sinked out of its bottom (at V ADC     —     LOW ), to create a ladder current of I 1 . Any small mismatch currents are absorbed by the midpoint voltage source  306 . 
     FIG. 4 is a schematic illustrating an example reference voltage circuit implementing the design shown in FIG.  3 . The reference voltage circuit shown in FIG. 4 generally includes a master module  402  and a slave module  404 . An amplifier AMP 1  is configured in a feedback loop. The amplifier sets the voltage over resistor R REF  close to one half of the effective differential ADC reference voltage: 
     
       
           V   REG   ≈V   REF   −V   REF     —     LOW   (1) 
       
     
     In this configuration, the current I 1  is scaled by a factor of eight over the current sourced by the voltage V REG . Thus, the current in the ADC ladder is: 
     
       
           I   1 =8*( V   REF   −V   REF     —     LOW )/(4 *R   LADDER )  (2) 
       
     
     where R LADDER  is the total combined series resistance of the ladder resistors R 1 , R 2 , R 3 , R 4 . 
     The actual differential ADC ladder voltage is: 
     
       
           V   LADDER =2*( V   REF   −V   REP     —     LOW )  (3) 
       
     
     Hence, 
     
       
           V   ADC     —     HIGH   =V   REF +½ *V   LADDER   (4) 
       
     
     
       
           V   ADC     —     LOW   =V   REF −½ *V   LADDER   (5) 
       
     
     Preferably the circuit  400  provides resistance matching between R REF  and R LADDRR . The slave voltage will be independent of global (lot-dependent) sheet resistance variations. 
     The circuit  400  has a lower ladder quarter-point resistance than the prior art design of FIGS. 1 and 2. Since the midpoint VREF is regulated, it has close to zero ohm resistance.. The quarter-point resistance becomes (¾)×R QP . Even assuming ideal decoupling with the capacitor C 3  in FIG. 2, the quarter-point resistance of the circuit  200  in FIG. 2 is R QP . 
     In the circuit  400  of FIG. 4, the capacitor C 2  is used to phase compensate the regulator. Capacitor C 1  is used to ensure that the power supply ripple couples to the gates of the upper current mirror. Thus, the new design  300  and circuit  400  substantially improve the PSRR. 
     FIG. 5 is a schematic illustrating an example ADC circuit  500  using the reference voltage circuit of FIG. 4. A fully differential and symmetric around the reference voltage V REF , analog input signal between nodes “analog pos.” and “analog neg.” is provided, along with the reference voltages along the resistive ladder, to comparators  502 . For each bit these comparators  502  are pair wise arranged, and their output currents are pair wise wire-OR&#39;d together by resistors  504  connected to the positive power supply VDD. The output from the comparators  502  and the resistors  504  is input for a digital output encoder  506 , which provides a two-bit binary output  508  corresponding to the differential analog input. 
     FIG. 6 is a schematic illustrating an example circuit  600  implementing the design shown in FIG.  3 . The circuit  600  includes dummy transistor structures for matching. An important design issue is the transient response time of the regulator to any changes in the input reference voltage (e.g., V REF  from FIG.  4 ). Internally in an integrated circuit, such a reference voltage is typically not an ideal stiff voltage source. Thus, analog-to-digital conversion can generally only take place after a certain settling time of the voltage source regulator. 
     FIG. 7 is an illustration showing a graphical output display  700  for a simulation of transient response time of the regulator in the example circuit of FIG. 6. A typical positive triangular change in the input reference voltage V ref  is shown as the middle waveform  705 . The settling time of the regulator in the example circuit is represented by a V adc     —     high  waveform  710  and a V adc     —     low  waveform  715 . As can be seen in FIG. 7, the settling time of this example circuit is 2.24 μs. 
     FIG. 8 is an illustration showing a graphical output display  800  for a simulation of transient responses from a pulse on a power supply node in the example circuit of FIG. 6. A pulse waveform  805  on the power supply node results in a high-side waveform  810  for the resistive reference ladder and a low-side waveform  815  for the resistive reference ladder. The peak power supply ripple rejection in the time domain is from 100 mV to 7 mV (23.1 dB). Thus, the new design  300  and circuit  400 , from FIGS. 3 and 4 respectively, substantially improve the PSRR. 
     Various implementations of the systems and techniques described here may be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits) or in computer hardware, firmware, software, or combinations thereof. 
     Other embodiments may be within the scope of the following claims.