Abstract:
An output buffer translates digital input signals which toggle between ground and V DDL  to signals which toggle between ground and V DDH . The technology dielectric breakdown voltage limit is less than the magnitude of V DDH , such that use of a traditional output stage would subject transistors&#39; dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors&#39; (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V DDL  =V DDH , and its performance is V DDL  independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths. Desired performance and temperature compensation are accomplished without subjecting any dielectrics to voltages which exceed the technology dielectric breakdown limit.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is related to the following copending applications: 
     1. U.S. patent application Ser. No. 08/757,978 entitled &#34;Circuitry and Method for Translating Voltages&#34; filed by International Business Machines Corporation on Nov. 27, 1996, now U.S. Pat. No. 5,777,490, issued Jul. 7, 1998; and 
     2. U.S. patent application Ser. No. 08/851,261, entitled &#34;A Static Pulsed Cross-Coupled Level Shifter and Method Therefor&#34;, filed on May 5, 1997, invented by Joshua Siegel, Hector Sanchez, and Chai-Chin Chao and assigned to the assignee hereof. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to electrical circuits, and more particularly, to digital output buffer circuits. 
     BACKGROUND OF THE INVENTION 
     Semiconductor technologies continuously evolve such that leading edge semiconductors have decreased geometries of transistor sizes and decreased voltages for voltage supplies. The smaller transistors are now manufactured with very thin gate oxide material. As a result, the dielectric breakdown voltage for such transistors in the leading edge semiconductor products has decreased. Thus, a decreased voltage supply is both desirable in order to reduce power consumption and necessary in order to avoid damaging the very thin gate oxide material. Meanwhile, other semiconductor products coupled to the leading edge semiconductor products still have much higher breakdown voltage devices, and utilize higher supply voltages. 
     For many years, semiconductor designers have dealt with the problem of translating between various levels of supply voltages. For example, when technology transferred between TTL (Transistor to Transistor Logic) to MOS (Metal Oxide Silicon) technology there was a need for voltage level shifting to be performed between the TTL and MOS technologies. Additionally, as supply voltages gradually decreased from 15 volts to 5 volts to 3 volts, designers created interface circuits which could operate between different voltage systems. However, most of those designs were focused on the issue of being able to just interface between one system operating at one voltage and a second system operating at a different voltage. Such systems typically did not have the problem of coping with breakdown voltages of transistors being threatened by the higher voltage system. 
     There are many chips and integrated circuits such as memories, memory controllers, and other peripherals that work with leading edge microprocessors. However, such peripherals and memories have not changed their supply voltages or reduced their voltage levels nearly as quickly as microprocessors have. In being able to interface between a peripheral circuit that has a much higher voltage than a leading edge integrated circuit, such as a microprocessor, designers often use a well biasing technique to try to minimize the impact in an integrated circuit of receiving a voltage signal much higher than the supply voltage intended for that integrated circuit. The well bias technique which is used eliminates a charge drain from the output node to an output stage power supply within the circuit. Prior circuits typically dealt with receiving higher voltage levels and using those voltage levels in a system operating at a lower voltage level. However, such systems did not typically worry about or have to compensate for transistor damage due to thin gate oxides. As technologies have evolved, the maximum voltage permitted across a transistor has decreased much faster than the decrease of supply voltages for the output bus. As a result, a need exists for a circuit and method which is able to guarantee the integrity of transistors and transistor gate oxides when interfacing with very high supply voltages at the output bus. 
     A known circuit for dealing with protecting gate oxides when coupling to an output bus having a higher supply voltage than the circuit supply voltage is illustrated in FIG. 1. An output buffer 10 has an input portion 11, an intermediate portion 12, and an output portion 13. In input portion 11, a P-channel transistor 15 has a source connected to a first (higher voltage) supply voltage V DDH , a gate connected to a node 24, and a drain connected to a node 17. A P-channel transistor 18 has a source connected to the supply voltage V DDH , and a gate connected a drain thereof at node 17. An N-channel transistor 20 has a drain connected to node 17, a gate connected to a second (lower voltage) supply voltage V DDL , and a source connected to a drain of an N-channel transistor 21. The gate of transistor 21 is connected to the DATA INPUT terminal, and a source of transistor 21 is connected to a ground terminal. Intermediate portion 12 includes an inverter 23 and an inverter 26 connected via a node 24 which is also connected to the gate of P-channel transistor 15. Inverters 23 and 26 are connected between the first supply voltage V DDH  and the second supply voltage V DDL . The output portion 13 comprises P-channel transistors 28 and 29 and N-channel transistors 31 and 32. P-channel transistor 28 has a source connected to the first supply voltage V DDH , a gate connected to the output of inverter 26, and a drain connected to a source of transistor 29. P-channel transistor 29 has a gate connected to supply voltage V DDL , and a drain connected to a chip output terminal. N-channel transistor 31 has a drain connected to the chip output terminal, a gate connected to supply voltage V DDL , and a source connected to a drain of N-channel transistor 32. N-channel transistor 32 has a gate connected to the complement of the &#34;DATA INPUT&#34; signal, and has a source connected to the ground terminal. 
     In operation, circuit 10 is an output buffer with an input portion 11 which consumes DC power. Input portion 11 functions as a level shift stage. When the input data has a logic high level, node 17 is driven low by the input portion 11. However, node 17 does not assume a ground level potential, but rather node 17 is at a level which is driven below V DDL . Once node 17 is driven below V DDL , the first inverter 23 drives node 24 to the V DDH  supply level. As a result, inverter 26 transitions the gate of transistor 28 to V DDL  so that transistor 28 is made conductive. As a result, the chip output terminal is driven to the V DDH  value. In the illustrated form, V DDL  is a lower voltage magnitude than V DDH , and V DDH  exceeds the maximum permitted voltage of the gate-to-source voltage, V GS , of each of the transistors of buffer 10. However, the difference between the V DDH  voltage level and the V DDL  voltage level is less than the maximum gate-to-source/drain voltage allowed in the technology in which buffer 10 is implemented. 
     When the DATA INPUT signal is at a logic low level, N-channel transistor 21 isolates node 17 from the ground terminal, and node 17 transitions to the V DDH  potential. As a result, inverter 23 transitions node 24 to supply voltage V DDL  and inverter 26 transitions the gate of transistor 28 to V DDH  which makes transistor 28 non-conductive. Furthermore, transistor 32 is conductive and thus the chip output signal transitions to the ground terminal potential. Note in summary that output buffer 10 operates to consume power in the input portion 11 when the DATA INPUT signal is at logic high state. When the DATA INPUT signal is at a logic low state, power is not consumed. Although the power consumption of output buffer 10 is a potential problem for many applications, output buffer 10 functions to allow the circuit to interface with a system having a higher supply voltage. Additionally, output buffer 10 does not permit a voltage between the gate to source electrodes of each transistor which would destroy the gate oxide of that transistor. 
     Additionally output buffer 10 suffers from various limitations. If the two voltages are equal: V DDH  =V DDL , output buffer 10 is not functional. The reason is that level shifted inverters do not work. It is common practice for a manufacturer of an Integrated Circuit to set voltage V DDH  to V DDL  during the debug phase of a design as well as for simplicity of test equipment during stress testing, such as is done in &#34;bum-in&#34; testing. Furthermore, the propagation delays of output buffer 10 do not track well as process technology, temperature, and voltage change, since transistors 28 and 32 are decoupled and are not driven from the same source. Part of this problem arises because the high and low output propagation paths differ significantly in circuit topology. Also note that output stage 13 tends to consume more active power than desired due to increased &#34;crowbar&#34; or short-circuit current due to different switching times through the two propagation paths since transistors 28 and 32 are decoupled. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying Figures. where like numerals refer to like and corresponding parts and in which: 
     FIG. 1 illustrates in schematic form a known output buffer for interfacing between two supply voltages of differing magnitude. 
     FIG. 2 illustrates in partial schematic and partial block diagram form an output buffer in accordance with one embodiment of the present invention. 
     FIG. 3 illustrates in partial schematic and partial block diagram form an output buffer in accordance with a second embodiment of the present invention. 
     FIG. 4 illustrates in schematic form one embodiment of the voltage dropping elements of FIGS. 2 and 3. 
     FIG. 5 illustrates in schematic form a second embodiment of the voltage dropping elements of FIGS. 2 and 3. 
     FIG. 6 illustrates in schematic form one embodiment of a bias circuit for use with the output buffers of FIGS. 2 and 3. 
     FIG. 7 illustrates in schematic form a second embodiment of a bias circuit for use with the output buffers of FIGS. 2 and 3. 
    
    
     DETAILED DESCRIPTION 
     The output buffers presented herein operate correctly even if voltages V DDH  =V DDL . Propagation delays high to low and low to high track over process technology, temperature, and voltage changes since the output stage is driven from a common signal. Crowbar or short-circuit current is minimized as well since both high and low propagation paths switch together. Also importantly, transistors are biased as closely as possible to a given technology&#39;s maximum gate to source voltage to provide higher performance and smaller resulting circuit. The propagation delays of the output buffers disclosed herein are strictly a function of the V DDH  level, and are not dependent upon the difference in voltage between V DDH  and V DDL  as in output buffer 10 in FIG. 1. 
     FIG. 2 is a block diagram that illustrates one version of a digital output buffer for multiple voltage system 36. Three stages or parts are shown: a first dual output voltage limiting inverter 40, a second dual output voltage limiting inverter 50, and an output stage 60. Both the first dual output voltage limiting inverter 40 and the second dual output voltage limiting inverter 50 have nearly identical structure and functionality. 
     The first dual output voltage limiting inverter 40 contains a first bias circuit 46 coupled in series between a first terminal 47 of a voltage drop circuit 44 and ground. Also coupled to the first terminal 47 of the voltage drop circuit 44 is a switch 48 to ground controlled by the DATA INPUT signal 64. The first terminal of the voltage drop circuit 44 provides a first output. Coupled between a second terminal 45 of the voltage drop circuit 44 and a output voltage V DDH  is a second bias circuit 42. Also coupled to the second terminal 45 of the voltage drop circuit 44 is a switch 43 to V DDH . The second terminal of the voltage drop circuit 44 provides a second output. 
     The second dual output voltage limiting inverter 50 contains a first bias circuit 56 coupled in series between a first terminal 57 of a voltage drop circuit 54 and ground. Also coupled to the first terminal 57 of the voltage drop circuit 54 is a switch 58 to ground controlled by an inverted 62 DATA INPUT 64 signal. The first terminal 57 of the voltage drop circuit 54 provides a first output signal 68. Coupled between a second terminal 55 of the voltage drop circuit 54 and the output voltage V DDH  is a second bias circuit 52. Also coupled to the second terminal 55 of the voltage drop circuit 54 is a switch 53 to V DDH . The second terminal 55 of the voltage drop circuit 54 provides a second output signal 66. The second switch 43 of the first dual output voltage limiting inverter 40 is controlled by the second terminal 55 of the dual output voltage limiting inverter 50, and the second switch 53 of the second dual output voltage limiting inverter 50 is controlled by the second terminal 45 from the first dual output voltage limiting inverter 40. 
     BIAS1 and BIAS2 are chosen such that the potential across voltage drop 44, 54 allows the voltages across the dielectrics of switches 43, 48, 53, 58 to reach but not exceed the maximum dielectric voltage permitted in the technology. The voltage drop circuits 44, 54 provide a constant voltage drop. Though a resistor is one possible implementation, it is far from optimum. Two preferred embodiments are further disclosed hereinbelow in FIGS. 4 and 5. 
     The output stage 70 consists of four transistors in series between V DDH  and ground. A first P-channel transistor 72 controlled by the second output signal 66 from the second dual output voltage limiting inverter 50 has its source coupled to V DDH  and its drain coupled to the source of a second P-channel transistor 74. The first N-channel transistor 78 controlled by the first output signal 68 from the second dual output voltage limiting inverter 50 has its source coupled to ground and its drain coupled to a source of a second N-channel transistor 76. The drains of the second P-channel transistor 74 and the second N-channel transistor 76 are coupled together to provide a CHIP OUTPUT signal 79 and are both controlled by BIASP and BIASN, respectively. 
     FIG. 3 is a block diagram that illustrates one version of a digital output buffer for multiple voltage system. Three stages or parts are shown: a first dual output voltage limiting inverter 80, a second dual output voltage limiting inverter 90, and an output stage 60. Both the first dual output voltage limiting inverter 80 and the second dual output voltage limiting inverter 90 have nearly identical structure and functionality. 
     The first dual output voltage limiting inverter 80 contains a first bias circuit 86 coupled in series between a first terminal 87 of a voltage drop circuit 84 and ground. Also coupled to the first terminal 87 of the voltage drop circuit 84 is a switch 88 to ground controlled by output 106 from a pulse generator. The pulse generator receives its input from the DATA INPUT signal 100 and comprises an odd number of inverters 102 in series as one input to an AND gate 104. The second input to the AND gate 104 is the DATA INPUT signal 100. The width of the pulse is the time it takes for a pulse to transit the number of inverters 102 in the pulse generator. The output 106 of the AND gate 104 is the output of the pulse generator that controls the switch 88 to ground. The first terminal of the voltage drop circuit 84 provides a first output. Coupled between a second terminal 85 of the voltage drop circuit 84 and a output voltage V DDH  is a second bias circuit 82. The second terminal of the voltage drop circuit 84 provides a second output. 
     The second dual output voltage limiting inverter 90 contains a first bias circuit 96 coupled in series between a first terminal 97 of a voltage drop circuit 94 and ground. Also coupled to the first terminal 97 of the voltage drop circuit 94 is a switch 98 to ground controlled by an inverted 108 DATA INPUT 100 signal. The first terminal 97 of the voltage drop circuit 94 provides a first output signal 68. Coupled between a second terminal 95 of the voltage drop circuit 94 and the output voltage V DDH  is a second bias circuit 92. Also coupled to the second terminal 95 of the voltage drop circuit 94 is a switch 93 to V DDH . The second terminal 95 of the voltage drop circuit 54 provides a second output signal 66. The second switch 93 of the second dual output voltage limiting inverter 90 is controlled by the second terminal 85 from the first dual output voltage limiting inverter 80. 
     The output stage 70 consists of four transistors in series between V DDH  and ground. A first P-channel transistor 72 controlled by the second output signal 66 from the second dual output voltage limiting inverter 90 has its source coupled to the first supply voltage V DDH  and its drain coupled to the source of a second P-channel transistor 74. The gate of a first N-channel transistor 78 is controlled by the first output signal 68 from the second dual output voltage limiting inverter 90, and its source is coupled to ground and its drain is coupled to a source of a second N-channel transistor 76. The drains of the second P-channel transistor 74 and the second N-channel transistor 74 are coupled together to provide a CHIP OUTPUT signal 79 and are both controlled by bias voltages BIASP and BIASN. 
     Note that the pulse generator output 106 essentially replaces the need for the first switch 43 to V DDH  in FIG. 2. This embodiment allows a much larger second bias circuit 82 to be used, since the time in which it is enabled is substantially shortened due to the pulse generated by the ANDing of the output of the inverters 102 with the DATA INPUT signal 100. Furthermore, this embodiment allows a substantially faster propagation through the output buffer. 
     A blownup schematic of the inverters 62, 102, 108 illustrated in FIGS. 2 and 3 is also shown. It is a standard inverter comprised of one N-channel transistor and one P-channel transistor. Note though that the drain of the P-channel transistor as well as its well bias are both tied to the second supply voltage (V DDL ). This second supply voltage (V DDL ) is usually the reference voltage of the interior of the integrated circuit, whereas the first reference voltage (V DDH ) is used on the exterior of the integrated circuit. The AND gate 104 is similarly constructed to contain transistors connected to V DDL . 
     FIG. 4 illustrates in schematic form one embodiment of the voltage dropping elements of FIGS. 2 and 3. Voltage dropping element 110 includes a first PNP transistor 112 and a second PNP transistor 114. Transistor 112 has an emitter providing the first terminal of voltage dropping element 110, a base, and a collector connected to ground. Transistor 114 has an emitter connected to the base of transistor 112, a base forming the second terminal of voltage dropping element 110 and a collector connected to ground. 
     In operation, voltage dropping element 110 provides a voltage drop which is equal to two (2) diode voltage drops formed by the emitter-base junction of collector 112 in series with the emitter-base junction of transistor 114. In processes where vertical PNP transistors such as transistors 112 and 114 are available, voltage dropping element 110 provides an exponential current voltage characteristic. This is desirable because the current through the PNP transistor increases exponentially as its voltage increases, which is faster than a linear or quadratic increase. Thus, voltage dropping element 110 is preferable to other types of voltage dropping elements such as resistors, diode connected MOS transistors and the like. In particular, voltage dropping element 110 may be advantageously implemented using a conventional CMOS process. In such a case, the emitter of transistors 112 and 114 are formed by a P+ diffusion in an N-well, the base being formed by the N-well and the collector by the P-substrate and thus transistors 112 and 114 represent the parasitic bipolar transistors formed in P-substrate N-well CMOS integrated circuits. 
     FIG. 5 illustrates in schematic form a second embodiment 120 of the voltage dropping elements of FIGS. 2 and 3. Voltage dropping element 120 represents a voltage dropping element formed in a CMOS process and further including disabling circuitry to reduce steady state or DC current consumption. Voltage dropping element 120 includes N-channel transistors 122 and 124, a CMOS transmission gate 128, a P-channel transistor 130, an N-channel transistor 132, and a P-channel transistor 126. Transistor 122 has a drain forming the first terminal of voltage dropping element 120, a gate for receiving a signal label &#34;SHIFT OE&#34; and a source. Transistor 124 has a drain connected to the source of transistor 122, a gate connected to the drain thereof, and a source. Transistor 126 has a source connected to the source of transistor 124, a gate and a drain, and a bulk electrode connected to the source thereof and a drain electrode forming the second terminal of voltage dropping element 120. Transmission gate 128 has a first terminal connected to the gate of transistor 126 and a second terminal connected to the drain of transistor 126. Transmission gate 128 is a conventional CMOS transmission gate formed of a P-channel transistor and an N-channel transistor connected in parallel. Thus, for controlling the conductivity of transmission gate 128, the N-channel transistor receives a signal labeled &#34;OE&#34; on its gate and the P-channel transistor receives a compliment of signal OE labeled &#34;OE&#34; on its gate. 
     Transistor 130 has a source connected to the first supply voltage V DDL , a gate for receiving signal OE and a drain and a bulk connected to the source thereof. Transistor 132 has a drain connected to the drain of transistor 130, a gate for receiving a signal labeled &#34;SHIFT OE&#34; and a source connected to the gate of transistor 126. In operation, voltage dropping element 120 includes a series combination of two diode connected transistors 124 and 126 in conjunction with enabling circuitry. The enabling circuitry includes transistor 122 which prevents current from flowing through transistors 124 and 126 when signal OE is at a logic low state and transmission gate 128 which selectively couples the gate of transistor 126 to the drain thereof thereby forming the diode connection and the series combination of transistors 130 and 132 which act to pull the gate of transistor 126 to the logic high level of signal SHIFT OE minus the threshold voltage of transistor 132. While voltage dropping element 120 provides a less ideal voltage dropping characteristic due to the quadratic current voltage characteristic of MOS transistors it is useful, however, for lower power applications because it can be easily disabled. 
     FIG. 6 illustrates in schematic form one embodiment 140 of a bias circuit for use with the output buffers of FIGS. 2 and 3. The bias circuit illustrated in FIG. 6 uses voltage dropping element 110 of FIG. 4 and is used to provide the bias voltages for P-channel transistors 74 and 76 as previously illustrated in FIGS. 2 and 3. Bias circuit 140 includes a P-channel transistor 141, bipolar transistors 112 and 114, an N-channel transistor 144, all of which are used in conjunction with output stage 70. Transistor 141 has a source connected to V DDH , a gate, a drain connected to the gate thereof for providing a signal labeled &#34;BIAS2&#34; and a bulk connected to the source thereof. Transistor 112 has an emitter connected to the drain of transistor 141, a base, and a collector connected to ground. Transistor 114 has an emitter connected to the base of transistor 112, a base and a collector connected to ground. Transistor 144 has a drain connected to the base of transistor 114, a gate connected to the drain thereof, and a source connected to ground. The drain of transistor 144 provides a signal labeled &#34;BIAS1&#34;. Driver stage 70 is connected as previously shown in FIGS. 2 and 3 except that transistor 74 receives signal BIAS1 on the gate thereof and transistor 76 receives signal BIAS2 on the gate thereof. Note that bias circuit 140 provides voltages on the gates of transistors 74 and 76 which are intermediate to power supplies V DDH  and ground and thereby prevent the dielectrics of transistors 74 and 76 from exposure to voltage potentials greater than the dielectric breakdown voltage for the technology. 
     It is important to note that by connecting BIAS2 to the gate of transistor 76 and using a signal NDRIVE generated from BIAS1, the series combination of transistors 76 and 78 provide a roughly constant current drive as temperature varies. As temperature increases, transistor 78 increases in current drive, while transistor 76 proportionately decreases in current drive, thus limiting the current drive of the series combination. As temperature decreases, the current drive of transistor 78 decreases, while the current drive of transistor 76 increases proportionately, thus maintaining approximately the same current drive for the series combination of transistors 76 and 78. So, this technique allows the current drive characteristics of the series combination of transistors 76 and 78 to remain fairly constant across temperature changes. Furthermore, connecting the gate of transistor 74 to BIAS1 and using the signal PDRIVE generated from BIAS2, the same temperature compensation is achieved for the P-channel series combination. 
     FIG. 7 illustrates in schematic form a second embodiment 150 of a bias circuit for use with the output buffers of FIGS. 2 and 3 and output stage 70. Bias circuit 150 includes P-channel transistors 151, 152 and 154, an N-channel transistor 155, a P-channel transistor 156, and N-channel transistors 160 and 162 used in conjunction with voltage dropping element 120. Transistor 151 has a source connected to V DDH , a gate for receiving an input signal which is opposite in polarity to the signal on the gate of transistor 160, a drain, and a bulk connected to the source thereof. Transistor 152 has a source connected to V DDH , a drain connected to the drain of transistor 151 and a bulk connected to the source thereof. Voltage dropping element 120 has a first terminal connected to the drains of transistors 151 and 152 and a second terminal. Transistors 152 and 162 operate as BIAS2 and BIAS1, respectively. Transistor 154 has a source connected to V DDL , a gate for receiving signal OE and a drain. Transistor 155 has a drain connected to the drain of transistor 154, a gate for receiving signal OE, and a source connected to transistor 74. Transistor 156 has a source connected to the drain of transistor 154, a gate for receiving signal OE, and a drain connected to the gate of transistor 74. Transistor 160 has a drain connected to the second terminal of voltage dropping element 120, a gate for receiving an input signal which is opposite in polarity to the signal on the gate of transistor 151, and a source connected to ground. Transistor 162 has a drain connected to the second terminal voltage dropping element 120, a gate connected to the drain thereof and a source connected to ground. The gate of transistor 76 is also connected to the source of transistor 155, the drain of transistor 156, the gate of transistor 74, and the drain of transistor 124. Note that the drain of transistor 124 in voltage dropping element 120 is used as a further output terminal to bias transistors 74 and 76. When output enable signal is inactive, transistors the gates of transistors 74 and 76 are biased to V DDL . 
     Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims. 
     Claim elements and steps herein have been numbered and/or lettered solely as an aid in readability and understanding. As such, the numbering and/or lettering in itself is not intended to and should not be taken to indicate the ordering of elements and/or steps in the claims.