Abstract:
A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Description:
BACKGROUND  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a delay circuit incorporating a capacitive element and, in particular, it relates to a delay circuit suitable for ring oscillators and to oscillators incorporating the delay circuit.  
         [0003]     2. Description of Related Art  
         [0004]     A delay circuit produces an output signal that is delayed with respect to the input signal. Many delay devices typically use Resistor-Capacitor (“RC”) circuits, where the delay is adjusted by varying a resistive and/or a capacitive load. In an integrated circuit using field effect transistors, such as MOS (Metal Oxide Semiconductor) transistors, the resistive and capacitive loads may be provided by transistors. Delay circuits are used in ring oscillators, which are important components of Phase-Locked Loop (“PLL”) circuits that have wide applications in the electronics world.  
         [0005]     A ring oscillator is a circuit composed of a plurality of delay circuits that are coupled to form a ring. The ring oscillator achieves oscillation by inverting its input signal upon ring-traversal and delaying its output in response to the input. The amount of time required for an input signal to traverse the ring is determined by the sum of the individual delays of the delay circuits that form the ring. Thus, the period of oscillation of the ring oscillator can be controlled by varying the delays of its individual constituent delay circuits.  
         [0006]     Ring oscillators are often used in phase-locked loop (“PLL”) circuits. In a phase-locked loop, an oscillator whose frequency and/or phase can be varied is synchronized in phase and/or frequency with a reference source. Therefore, the oscillator operates over a range of frequencies so that its frequency may be altered to match that of the reference source. The use of delay circuits in oscillators for PLLs is well known. See, for example, Ian A. Young “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, IEEE Journal Of Solid-State Circuits, Vol. 27, No. 11, November 1992; pp. 1599-1607 (“Young”); or Tsung-Hsien Lin, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop”, IEEE Journal Solid-State Circuits, Vol. 36, No.  3 , March 2001, pp. 424-431 (“Lin”), each of which is herein incorporated by reference in their entirety.  
         [0007]     For conventional delay circuits, delay length is typically varied by changing the bias voltage of a MOS transistor in the circuit. Changing the bias voltage causes a variation in the current through the transistor, or the resistance of the transistor. However, the range of variation of the current through the transistor, or of the resistance of the transistor, is limited because of restrictions on the range of bias voltages. Therefore, in order to expand the range by which delay lengths can be varied, the capacitance value of capacitors in delay circuits is also varied.  
         [0008]     Variation in the capacitance values is generally accomplished through the use of switching elements. This has the unfortunate consequence of introducing the parasitic capacitance of the switching elements into the delay circuit leading to an increase in the minimum value of delay length. As a result, the upper limit of the oscillation frequency of a ring oscillator incorporating such a delay circuit is reduced.  
         [0009]     There is thus a need for delay circuits in which the delay length may be varied over a wide range without effects introduced by the parasitic capacitances of switching elements. The successful incorporation of such delay circuits into ring oscillators would also allow ring oscillators to operate over a greater range of frequencies.  
       SUMMARY  
       [0010]     Embodiments of a delay circuit capable of operating over a wide range of frequencies are presented. In some embodiments, the delay circuit includes a capacitor bank including a first capacitor, and one or more additional capacitors capable of being coupled in parallel with the first capacitor; a first switching configuration to selectively enable one of two or more transistors coupled in series; and a second switching configuration to charge or discharge the first capacitor and/or one of the other capacitors using one of the two transistors in accordance with an input signal. In some embodiments according to the present invention, the first capacitor is used when the first switching configuration enables one of the transistors, while the first capacitor and at least one of the other capacitors coupled in parallel are used when the first switching configuration selects one of the other transistors. In some embodiments according to the present invention, the means used to selectively enable one of the transistors does not load the output and permits a wide operational frequency range for the delay circuit. In some embodiments, the transistors may serve as resistors or current sources.  
         [0011]     In some embodiments the delay circuit may be fabricated as an integrated circuit. In some embodiments, the delay circuit may be a functional element of a larger component that is fabricated as an integrated circuit.  
         [0012]     Embodiment of a ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form an oscillator, wherein the output of each delay circuit is fed to the next delay circuit in sequence and the output of the last delay circuit in the sequence is fed back to the first delay circuit in the sequence.  
         [0013]     In some embodiments the oscillator may be fabricated as an integrated circuit. In some embodiments, the oscillator may be a functional element of a larger component that is fabricated as an integrated circuit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  shows a circuit diagram showing an arrangement of a conventional delay circuit.  
         [0015]      FIG. 2  shows a diagram showing an arrangement of a ring oscillator incorporating the conventional circuit of  FIG. 1 .  
         [0016]      FIG. 3  illustrates the operation of the ring oscillator of  FIG. 2 .  
         [0017]      FIG. 4  shows a circuit diagram showing an arrangement of another conventional delay circuit.  
         [0018]      FIG. 5  shows a diagram showing an arrangement of a ring oscillator incorporating the conventional circuit of  FIG. 4 .  
         [0019]      FIG. 6  graphically illustrates the operation of the ring oscillator of  FIG. 5 .  
         [0020]      FIG. 7  shows a circuit diagram showing an arrangement of an exemplary delay circuit, according to embodiments of the present invention.  
         [0021]     FIGS.  8 (A) and  8 (B) illustrate the operation of the exemplary delay circuit shown in  FIG. 7 , according to embodiments of the present invention.  
         [0022]      FIG. 9  shows a circuit diagram of another arrangement of an exemplary delay circuit, according to the embodiments of the present invention.  
         [0023]     FIGS.  10 (A) and  10 (B) illustrate the operation of the exemplary delay circuit shown in  FIG. 9 . 
     
    
     DETAILED DESCRIPTION  
       [0024]     A conventional delay circuit incorporates elements such as a current source, a resistor, and a capacitor with the delay being controlled by varying the values of one or more of the current, resistance, and capacitance. The capacitance value may be varied by using a plurality of switches and capacitors, with the switches serving to add or remove capacitors from the circuit.  
         [0025]     The delay circuit shown in  FIG. 1  illustrates a conventional differential delay circuit and includes MOS transistors MN 3  and MN 4 , which form a differential pair, a current source  11 , and a pair of delay setting sections  12  and  13  for setting the length of the delay. MOS transistors MN 3  and MN 4  are supplied with inputs IN and IP at their respective gates, and provide outputs OP and ON at their respective drains. Delay setting section  12  includes P-type MOS transistor MP 2 , capacitors C 3 -C 5 , and switches SW 5  and SW 6 . Delay setting section  13  can be arranged in the same manner as delay setting section  12 , although the various individual elements have not been shown in  FIG. 1 .  
         [0026]     In  FIG. 1 , the resistance of MOS transistor MP 2  is controlled by bias voltage “Bias” applied to the gate. If input voltage IN at the gate of MOS transistor MN 3  is greater than input IP to MOS transistor MN 4 , an electrical current flows from MP 2  to MN 3 . Consequently, the output voltage OP of MN 3  decreases, and the output voltage ON of MN 4  increases. On the other hand, if input voltage IP is greater than input voltage IN, current flow to MN 3  is stopped. Consequently, output voltage OP increases, and output voltage ON decreases.  
         [0027]      FIG. 3A  shows output voltage variations of outputs OP and ON of MOS transistors MN 3  and MN 4 . Note that, outputs OP and ON correspond to “P 0 P” and “P 0 N”, respectively, in  FIG. 3A . The mathematical relationship of the output voltages P 0 P and P 0 N with circuit elements may be expressed by the equations (1) and (2) respectively. 
   P 0 P=VDD−I*R *exp{− t /( R*C )}  (1)    P 0 N=VDD−I*R *(1−exp{− t /( R*C )})  (2)  
         [0028]     In equations 1 and 2, “VDD” denotes the voltage of the power supply, “R” denotes the resistance of MOS transistor MP 2 , “C” denotes the capacitance added to drain terminals of MOS transistors MN 3  and MN 4 , and “t” denotes the elapsed time. Capacitance value C described above refers to the capacitance value of the capacitor C 3  if the switches SW 5  and SW 6  are both off. If switch SW 5  is on and switch SW 6  is off, then C refers to the sum of the capacitances of C 3  and C 4 . If switches SW 5  and SW 6  are both on, then C is the sum of the capacitances C 3 , C 4 , and C 5 .  
         [0029]     Note that potentials P 0 P and P 0 N of the delay circuit shown in  FIG. 1  behave as shown in  FIG. 3 (A). Output voltage P 0 P increases from voltage (VDD−I·R), whereas the output voltage P 0 N decreases from the power supply voltage VDD, with P 0 P=P 0 N at the point of intersection of the lines denoting P 0 P and P 0 N.  
         [0030]      FIG. 2  shows a ring oscillator that includes four delay circuits of the type shown in  FIG. 1  coupled in a ring. Specifically, the ring oscillator includes four cascaded delay circuits  211 - 214  with the output signals of the back-end delay circuit  214  P 0 P and P 0 N being fed back as input signals to the front-end delay circuit  211 . Likewise, the output signals P 1 P and P 1 N of delay circuit  211  are fed as input signals to delay circuit  212 ; output signals P 2 P and P 2 N of circuit  212  are fed as input signals to delay circuit  213 ; and output signals P 3 P and P 3 N of delay circuit  213  are fed as input signals to delay circuit  214 . The relative variations of the output signals of delay circuits  211 - 214  with respect to each other are shown in FIGS.  3 (A)- 3 (D) respectively.  
         [0031]     As shown in  FIG. 3 (A), input voltage P 0 P of delay circuits  211  increases from a voltage of (VDD−I·R), while input voltage P 0 N decreases from the power supply voltage VDD. At the point in time where the graphs denoting P 0 P and P 0 N intersect, P 0 P=P 0 N and voltages P 0 P and P 0 N are equal.  
         [0032]     As shown in  FIG. 3 (B), from the point in time at which its input voltages P 0 P and P 0 N are equal (i.e. when P 0 P=P 0 N), output voltage P 1 P of delay circuit  211  starts to increase from (VDD−I·R), while output voltage P 1 N of the delay circuit  211  starts to decrease from voltage VDD. As before, output voltage P 1 P=P 1 N when lines denoting voltages P 1 P and P 1 N intersect.  
         [0033]     Similarly,  FIG. 3 (C) shows output voltage P 2 P of the delay circuit  212  increasing from voltage (VDD−I·R), while output voltage P 2 N starts decreasing from VDD, starting from the time at which input voltages P 1 P and P 1 N are equal. Again, intersection of the lines denoting P 2 P and P 2 N indicate that the output voltages of delay circuit  212  are equal, i.e. P 2 P=P 2 N.  
         [0034]      FIG. 3 (D) shows output voltage P 3 P of delay circuit  213  increasing from voltage (VDD−I·R), whereas output voltage P 3 N decreases from voltage VDD, from the time when input voltages P 2 P and P 2 N of delay circuit  213  are equal. Voltage P 3 P=P 3 N when lines representing voltages P 3 P and P 3 N intersect.  
         [0035]     Note that when the input voltages P 3 P and P 3 N are equal, output voltages P 0 P and P 0 N of delay circuit  214  (representing the input voltages to circuit  211 ) are at voltage VDD and the voltage (VDD−I·R) respectively. Thereafter, output voltage P 0 P decreases toward voltage (VDD−I·R), while output voltage P 0 N increases toward voltage VDD, and the lines intersect when P 0 P=P 0 N.  
         [0036]     If the input voltages for a given circuit are equal at time t=0, then the time T D  at which the output voltages become equal is given by equating output voltages expressed by equations (1) and (2). Therefore, 
 
 VDD−I*R *exp{− T   D /( R*C )}= VDD−I*R (1−exp{− T   D   /RC }),  (3) 
 
 which yields, 
 
exp{− T   D /( R*C )}=(1/2),  (4) 
 
 implying that 
 
 T   D =−( R/C )log e (1/2).  (5) 
 
         [0037]     In general, the time period TD of the ring oscillator is determined by the propagation time of a single transition through the complete chain, or T=2*T D *N, where N is the number of cascaded delays circuits in the ring. For the ring oscillator shown in  FIG. 3 , the number of delay cascaded delay circuits is  4 , i.e. N=4. The factor  2  results from the observation that a full cycle requires both a low-to-high and a high-to-low transition. Thus, the ring oscillator shown in  FIG. 2 , has a period given by 8*T D  and oscillates with a period of 8*T D .  
         [0038]     Time T D  is proportional to R and to C as indicated by equation (5). Thus, the oscillation period of the ring oscillator shown in  FIG. 2  can be varied by varying the resistance value of the MOS transistor MP 2 , or by varying the sum of capacitance values of the capacitors C 3 -C 5 .  
         [0039]      FIG. 4  shows another example of a single-ended conventional delay circuit comprising of a MOS transistor MN  6  and a delay setting section  14  for setting the length of delay. MOS transistor MN 6  is supplied with an input IN at its gate and provides an output OUT at its drain. Delay setting section  14  includes a P-type MOS transistor MP 5 , capacitors C 9 , CA and CB, and switches SWC and SWD.  
         [0040]     As shown in  FIG. 4 , MOS transistor MP 5  controls the current value through a bias voltage “Bias” applied to its gate. If input voltage IN at the gate of MOS transistor MN 6  exceeds its threshold voltage V TH , then MOS transistor MN 6  is turned on, and output voltage OUT decreases. On the other hand, if input voltage IN is lower than threshold voltage V TH , then MOS transistor MN 6  is turned off, and output voltage OUT increases. Variations in output voltage OUT depend on the current through MOS transistor MP 5 , and the capacitance of capacitor C 9  and are shown in  FIG. 6 (A). The output potential V can be expressed by the following equation: 
 
 V =( I/C )· t.   (6) 
 
         [0041]     In the formula above, “I” denotes the value of the current through the MOS transistor MP 5 , “C” denotes the value of the capacitance added to the output line, and “t” denotes the elapsed time.  
         [0042]      FIG. 5  shows a ring oscillator comprising three delay circuits of the type shown in  FIG. 4  coupled in a ring. Specifically, the ring oscillator includes three cascaded delay circuits  511 - 513  with the output signal of back-end delay circuit  513  being fed back to be the input signal of front-end delay circuit  511 .  
         [0043]     As shown in  FIG. 6 (A), the output voltage O 0  of delay circuit  511  increases from 0 and reaches threshold voltage V TH . At this point in time, the output voltage O 1  of the delay circuit  512  drops to 0, as shown in  FIG. 6 (B), while output voltage O 2  of delay circuit  513  starts increasing from 0, as shown in  FIG. 6 (C).  
         [0044]     Next, when output voltage O 2  of the delay circuit  513  reaches threshold voltage V TH , as shown in  FIG. 6 (C), the output potential O 0  of the delay circuit  511  drops to 0, as shown in  FIG. 6 (A), while the output potential  1  of the delay circuit  512  starts increasing from 0, as shown in  FIG. 6 (B).  
         [0045]     Finally, when output voltage O 1  of delay circuit  512  reaches threshold voltage V TH  as shown in  FIG. 6 (B), output potential O 2  of delay circuit  513  drops to 0, as shown in  FIG. 6 (C), while output potential O 0  of delay circuit  511  starts increasing from 0, as shown in  FIG. 6 (A).  
         [0046]     This sequence of increasing and decreasing output voltages continues for each delay circuit in the ring oscillator. Here, the time T D  representing the time taken from the point in time when the input potential of each delay circuit drops to 0 (i.e. the point in time at which the output of its predecessor drops to 0) to the point in time when its output potential reaches the threshold voltage V TH  can be expressed by the equation: 
 
 V   TH =( I/C )* T   D ,  (7) 
 
 which yields the following equation for T D . 
 
 T   D   =V   TH *( C/I ).  (8) 
 
         [0047]     The ring oscillator shown in  FIG. 5  has a time period of 3*T D . In other words, it takes 3*T D , from a point in time when output voltage O 0  of the delay circuit  511  is V TH  to the next point in time when output voltage O 0  reaches threshold voltage V TH  again. Note that time T D  is proportional to C and inversely proportional to I, as indicated by equation (8). Thus, the oscillation period of the ring oscillator shown in  FIG. 5  can be varied by varying the sum of the capacitances of capacitors C 9 , CA and CB, and/or the value of current I through MOS transistor MP 2 .  
         [0048]     The use of switching elements to vary the capacitance results in the introduction of the parasitic capacitance of the switching elements into the delay circuit, leading to an increase in the minimum value of delay length. As a result, the upper limit of the oscillation frequency of a ring oscillator incorporating such a delay circuit is reduced.  
         [0049]     In some embodiments of the present invention, a delay circuit with a minimal load capacitance is presented leading to a lower minimum delay value. Thus, a higher range of operating frequencies is possible for a ring oscillator incorporating a delay circuit according to embodiments of the present invention.  
         [0050]      FIG. 7  shows a circuit diagram showing a delay circuit according to some embodiments of the present invention. In some embodiments, as shown in  FIG. 7 , a differential delay circuit may be used comprising of a differential pair of N-type MOS transistors MN 1  and MN 2 , a current source  1 , and a pair of delay setting sections  2  and  3  for setting delay length. Delay setting sections  2  and  3  are disposed symmetrically and can have the same circuit arrangement. Accordingly, the internal arrangement of the delay setting section  3  has not been shown and follows from the description of delay section  2 . MOS transistors MN 1  and MN 2 , in delay section  2 , are supplied with inputs IN and IP respectively at their gates. The sources of MN 1  and MN 2  are coupled to each other and the connection grounded via current source  1 . MOS transistors MN 1  and MN 2  provide outputs OP and ON respectively at their drains.  
         [0051]     As shown in  FIG. 7 , delay setting section  2  also includes capacitor set  21  with capacitors C 0 , C 1  and C 2 , two P-type transistors MP 0  and MP 1  which also serve as resistors when charging or discharging capacitor set  21 , and switches SW 0 -SW 4 . Switches SW 0 -SW 2  selectively enable MOS transistors MP 0  or MP 1 . Switches SW 3  and SW 4  are coupled in series to capacitors C 1  and C 2  respectively, and allow capacitors C 1  and C 2  to be selectively coupled in parallel with capacitor C 0 . Capacitor C 0  is coupled to the drains of MOS transistors MN 1  and MP 0  at one end and grounded at the other end. Capacitor C 1  is coupled to the junction of MOS transistors MP 0  and MP 1  through switch SW 3  at one end and grounded at the other end. Capacitor C 2  is coupled to the junction of MOS transistors MP 0  and MP 1  through switch SW 4  at one end and grounded at the other end.  
         [0052]     In  FIG. 7 , MOS transistors MP 0  and MP 1  are coupled in series (the drain of MP 1  is coupled to the source of MP 0 ) and coupled to a power supply VDD at one end, and to capacitor C 0  and the drain of MOS transistor MN 1  at the other end. Additionally, the gate of MOS transistor MP 0  can be grounded via switch SW 2 , Bias voltage “Bias” is applied to the gate of MP 1  and can be applied to the gate of MP 0  using switch SW 1 . Note that both the drain and source of MOS transistor MP 1  are coupled to switch SW 0 , effectively short-circuiting MP 1  when the switch is turned on (closed). The resistance of MOS transistors MP 0  and MP 1  is a function of input bias voltage, Bias.  
         [0053]     A delay circuit according to some embodiments of the present invention, as shown in  FIG. 7 , can operate in two modes as shown in  FIG. 8 (A) and  FIG. 8 (B), respectively.  FIG. 8 (A) and  FIG. 8 (B) are simplified circuit diagrams of the delay circuit section  2  that result from certain configurations of the switches in  FIG. 7 .  
         [0054]     In a first operation mode, switches SW 0  and SW 1  are turned on, and the switch SW 2  is turned off, as shown in  FIG. 8 (A). With SW 0  turned on, the source and drain of MOS transistor MP 1  are short-circuited, so that the source of MOS transistor MP 0  can be considered as coupled to power supply VDD. In this mode, delay length of the circuit is determined by the resistance of MOS transistor MP 0  and load capacitance of capacitor C 0 . Note that since switches SW 3  and SW 4  are not coupled to the drain of MOS transistor MN 1 , they are not loads on MN 1 .  
         [0055]     In a second operation mode, switches SW 0  and SW 1  are turned off, and the switch SW 2  is turned on, as shown in  FIG. 8 (B). When switch SW 2  is turned on, the gate of MOS transistor MP 0  is grounded, so that the drain and source of MP 0  can be considered to be short-circuited. Therefore, in this mode, the delay length of the delay circuit is determined by the resistance of the MOS transistor MP 1  and a load capacitance, which is a sum of the capacitance of capacitor C 0  and a controllable capacitance determined by the capacitances of capacitors C 1  and C 2  based on the on/off state of switches SW 3  and SW 4 . In this mode, the delay circuit may have the capacitors C 1  and C 2  as loads thereon, as shown in  FIG. 8 (B).  
         [0056]     Note that according to embodiments of the present invention as shown in  FIG. 8 (A), in the first operational mode, switches SW 3  and SW 4 , which select capacitors C 1  and C 2  respectively, are not coupled to the output terminal of the delay circuit. Thus, any additional parasitic capacitance that would otherwise result from the use of switches SW 3  and SW 4  is not added to the delay circuit. Therefore, the minimum load capacitance of the exemplary delay circuit configuration shown in  FIG. 7  and  FIG. 8 (A) can be lower than that of conventional delay circuits, such as the circuit shown in  FIG. 1 . A delay circuit according to embodiments of the present invention can have a minimum delay amount smaller than that of a conventional circuit.  
         [0057]     In some embodiments, the delay circuit may be arranged so that MOS transistor MP 1  is short-circuited. In some embodiments, MOS transistor MP 0 , may be short-circuited by using a switch provided in parallel with the MOS transistor MP 0 , instead of switch SW 2 . In some embodiments, a capacitance, such as C 0 , can be provided in the form of a wiring capacitance, or the parasitic capacitance of a transistor. In some embodiments, an additional capacitor with a series-coupled switch may be provided in parallel with capacitor C 1  and series-coupled switch SW 3 . In some embodiments, an additional capacitor with a series-coupled switch may be provided in parallel with capacitor C 2  and the series-coupled switch SW 4 . In some embodiments, a fixed capacitor that is not controlled by a switch may be loaded in parallel with C 1  or C 2 . In some embodiments, the positions of the capacitor and its series-coupled switch may be interchanged, so that the switch, rather than the capacitor, is grounded.  
         [0058]     In some embodiments, the exemplary delay circuit of  FIG. 7  may be used in the ring oscillator of  FIG. 2 . Four delay circuits  211 - 214  of the type shown in  FIG. 7  may be cascaded to form a ring oscillator with the output signal of the back-end delay circuit being fed back to be the input signal of the front-end delay circuit, according to embodiments of the present invention.  
         [0059]      FIG. 9  shows a circuit diagram of a single-ended delay circuit according to some embodiments of the present invention. As shown in  FIG. 9 , the delay circuit includes N-type MOS transistor MN 5  and delay setting section  4 . In some embodiments, delay setting section  4 , in turn, includes capacitor set  41  with capacitors C 6 , C 7 , and C 8 ; P-type transistors MP 3  and MP 4  serving as resistors for charging or discharging capacitor set  41 ; and switches SW 7 -SW 9 , SWA, and SWB. Switches SW 7 -SW 9  are arranged to selectively enable one of MOS transistors MP 3  or MP 4 . Switches SWA and SWB are coupled in series to the capacitors C 7  and C 8 , respectively, and may be used to selectively couple capacitors C 7  and C 8  respectively in parallel with capacitor C 6 .  
         [0060]     As shown in the exemplary circuit in  FIG. 9 , capacitor C 6  is also coupled to the drains of MOS transistors MN 5  and MP 4  at one end and grounded at the other end. Capacitors C 7  and C 8  are coupled (through switches SWA and SWB respectively) to the junction of MOS transistors MP 3  and MP 4  at one end and grounded at the other end. Series-coupled MOS transistors MP 3  and MP 4  are coupled to power supply VDD at one end, and to capacitor C 6  and the drain of MOS transistor MN 5  at the other end. Bias voltage “Bias” is applied to the gate of MOS transistor MP 3 , and to the gate of MP 4  using switch SW 8 . Current in the exemplary circuit shown in  FIG. 9 , is controlled by MOS transistors MP 3  and MP 4  based on the value of bias voltage Bias, applied to the gates of MOS transistors MP 3  and MP 4 . Note that both the drain and source of MOS transistor MP 3  are coupled to switch SW 7 , effectively short-circuiting MP 3  when the switch is turned on (closed). Note also that switch SW 9  may be used to ground the gate of MP 4 .  
         [0061]     A delay circuit according to some embodiments of the present invention, as shown in  FIG. 9 , can operate in two modes as shown in  FIG. 10 (A) and  FIG. 10 (B), respectively.  FIG. 10 (A) and  FIG. 10 (B) are simplified diagrams of the circuit of  FIG. 9  resulting from certain configurations of the switches in  FIG. 9 .  
         [0062]     In a first operation mode, switches SW 7  and SW 8  are turned on, and switch SW 9  is turned off. The resulting circuit is shown in  FIG. 10 (A). In this mode, with switch SW 7  turned on, MOS transistor MP 3  is short-circuited. Thus, the source of MOS transistor MP 4  is coupled to power supply VDD. Accordingly, delay length is determined by the current passing through MOS transistor MP 4  and load capacitance of capacitor C 6 . Note that switches SWA and SWB are not coupled to the drain of MOS transistor MN 5 , which is an output terminal of the delay circuit. Thus, switches SWA and SWB are not loads on MOS transistor MN 5 .  
         [0063]     In a second operation mode, the switches SW 7  and SW 8  shown in  FIG. 9  are turned off, and the switch SW 9  is turned on. The resulting circuit is shown in  FIG. 10 (B). In this mode, switch SW 9  grounds the gate of the MOS transistor MP 4 , so that the drain and source of the MOS transistor MP 4  can be considered to be short-circuited. Accordingly, delay length is determined by the current passing through MOS transistor MP 3  and the load capacitance. The load capacitance is the sum of the capacitance of capacitor C 6  and a controllable capacitance determined by the capacitances of the capacitors C 7  and C 8  based on the on/off state of switches SWA and SWB.  
         [0064]     Note that according to embodiments of the present invention as shown in  FIG. 10 (A), in the first operational mode, switches SWA and SWB, which select capacitors C 7  and C 8  respectively, are not coupled to the output terminal of the delay circuit. Thus, any additional parasitic capacitance that would otherwise result from the use of switches SWA and SWB is not added to the delay circuit. Therefore, the minimum load capacitance of the exemplary delay circuit configuration shown in  FIG. 9  and  FIG. 10 (A) can be lower than that of conventional delay circuits, such as the circuit shown in  FIG. 4 . A delay circuit according to embodiments of the present invention can have a minimum delay amount smaller than that of a conventional circuit.  
         [0065]     In some embodiments, the delay circuit may be arranged so that MOS transistor MP 3  is short-circuited, in a manner similar to MP 4 . In some embodiments, MOS transistor MP 4  may be short-circuited by using a switch provided in parallel with transistor MP 4 , instead of switch SW 9 . In some embodiments, a capacitance, such as C 6 , can be provided in the form of a wiring capacitance, or the parasitic capacitance of a transistor. In some embodiments, an additional capacitor with a series-coupled switch may be provided in parallel with capacitor C 7  and series-coupled switch SWA. In some embodiments, an additional capacitor with a series-coupled switch may be provided in parallel with capacitor C 8  and the series-coupled switch SWB. In some embodiments, a fixed capacitor that is not controlled by a switch may be loaded in parallel with C 7  or C 8 . In some embodiments, the positions of the capacitor and its series-coupled switch may be interchanged, so that the switch, rather than the capacitor, is grounded.  
         [0066]     In some embodiments, the exemplary delay circuit of  FIG. 9  may be used in the ring oscillator of  FIG. 5 . Three delay circuits  511 - 513  of the type shown in  FIG. 9  may be cascaded to form a ring oscillator with the output signal of back-end delay circuit  513  being fed back to be the input of front-end delay circuit  511 , according to some embodiments of the present invention.  
         [0067]     Other embodiments of the present invention may make use of many types of delay circuits and methods to carry out the delay circuit or oscillator functions. In some embodiments, the embodiments described could be incorporated into an integrated circuit. The embodiments described above are exemplary only and are not intended to be limiting. The operations, stages, and procedures described above and illustrated in the accompanying drawings are sufficiently disclosed to permit one of ordinary skill in the art to practice the invention. One skilled in the art may recognize various possible modifications that are intended to be within the spirit and scope of this disclosure. As such, the invention is limited only by the following claims.