Abstract:
An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.

Description:
CROSS REFERENCE TO RELATED APPLICATON 
     This application is a divisional of application Ser. No. 08/870,614, filed Jun. 6, 1997, pending. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates in general to chip-on-board applications for integrated circuit dice, and in particular to devices and methods for electrically and thermally coupling to the backsides of dice in such applications. 
     2. State of the Art 
     Integrated circuit (IC) dice or “chips” are small, generally rectangular IC devices cut from semiconductor wafers, such as silicon wafers, on which multiple IC&#39;s have been fabricated. Most dice are packaged by attaching them to lead frames supported in plastic or ceramic packages, and the lead frames and packages are typically designed to conduct heat away from the dice in order to protect them from heat damage. Such packages are also typically designed to protect the dice from corrosion. 
     Some dice, however, are packaged in what are known as “chip-on-board” (COB) applications, in which the dice are directly attached to printed circuit boards (PCB&#39;s) or other known substrates using well-known die-attach techniques. In these applications, bond pads on one or more dice are connected to signal traces on the surfaces of PCB&#39;s or other substrates using wire, or tape-automated, bonding, and a liquid or gel encapsulant, commonly referred to as a “glob top,” is applied over the dice to protect them from corrosion. One such COB application is described in U.S. Pat. No. 5,497,027. 
     Dice in COB applications typically generate more heat than their associated PCB&#39;s alone can satisfactorily conduct away. Consequently, certain techniques have been devised to assist in conducting heat away from dice in COB applications. In one such technique shown in FIG. 1, circuit traces  10  that widen near a die  12  and are directly attached to the surface  14  of a PCB  16  assist the PCB  16  in conducting significant amounts of heat away from the die  12 . Unfortunately, circuit traces that widen sufficiently near dice to satisfactorily conduct heat away from the dice typically use an inordinately large amount of surface space on their associated PCB&#39;s. As a result, widened circuit traces can be difficult or impossible to implement in today&#39;s densely packed COB applications. Widened circuit traces can also lead to an undesirable increase in capacitive and inductive parasitics, which are highly undesirable for high-speed applications. 
     Another technique for conducting heat away from dice in COB applications involves using thermally conductive PCB&#39;s in place of the more commonly used glass-epoxy PCB&#39;s. Thermally conductive PCB&#39;s are made with materials such as insulated aluminum, porcelainized steel, and ceramics that are superior in heat transfer characteristics to glass-epoxy. Because this technique is not applicable to the glass-epoxy PCB&#39;s used in the majority of COB applications, it is of limited utility. 
     Therefore, there is a need in the art for a device and method for satisfactorily conducting heat away from dice that are directly attached to a variety of PCB&#39;s, including conventional, widely-utilized glass-epoxy PCB&#39;s, without degrading the electrical characteristics of the interconnecting circuitry in COB applications. 
     BRIEF SUMMARY OF THE INVENTION 
     An inventive device for chip-on-board applications comprises a base, such as a printed circuit board (PCB) or a multi-chip module, that includes a conductive layer, such as a copper or other metallic plane, positioned on a surface of a supporting insulative substrate. An insulating layer overlies the surface of the conductive layer and defines at least one aperture in substantial registry with a localized region on the conductive layer on which a bare integrated circuit die is to be placed. The backside surface of the die is directly attached to the conductive plane in the localized region using a conductive die-attach material, such as a silver-filled epoxy, interposed between the conductive layer and the die. The inventive device thus can advantageously conduct heat away from the die by directly coupling the backside of the die to the conductive layer through the conductive die-attach material. The device can also conduct a substrate bias voltage to the backside of the die through the conductive layer and the die-attach material. 
     In a modified version of the base described above, the base includes multiple vertically-separated conductive layers, each layer having a localized region for conductive attachment to one of multiple bare integrated circuit dice. As a result, each of the dice may receive a different substrate bias voltage through its respective conductive layer. 
     In another embodiment of the present invention, an electronic device includes the base described above and an integrated circuit die, such as a Dynamic Random Access Memory (DRAM) die. In still another embodiment, an electronic system includes input, output, memory, and processor devices, and one or more of these devices includes the base described above. 
     In a further embodiment, a system for conducting heat away from a die includes a thermally conductive interior PCB layer having a surface with an externally accessible die-attach region. A thermally conductive die-attach material directly attaches a backside surface of the die to the die-attach region to establish thermal conduction between the die and the thermally conductive layer. 
     In a still further embodiment of the present invention, a system for supplying a substrate bias voltage to a die includes a substrate bias voltage generator and an electrically conductive layer inside a PCB for conducting the substrate bias voltage to an externally accessible die-attach region on the surface of the conductive layer. An electrically conductive die-attach material directly attaches a backside surface of the die to the die-attach region to conduct the substrate bias voltage to the backside surface of the die. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
     FIG. 1 is an isometric view of a portion of a prior art printed circuit board that uses widened circuit traces near a directly attached (i.e., “on-board”) integrated circuit die to conduct heat away from the die; 
     FIG. 2 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to a conductive layer of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between the conductive layer and the dice in accordance with the present invention; 
     FIG. 3 is an isometric sectional view of the multi-chip module portion of FIG. 2 with an alternative substrate biasing arrangement; 
     FIG. 4 is an isometric view of a portion of a multi-chip module including integrated circuit dice directly attached at their backsides to multiple conductive layers of a base, such as a printed circuit board, in order to effect direct electrical and thermal conduction between each die and one of the conductive layers in accordance with the present invention; and 
     FIG. 5 is a block diagram of an electronic system including the multi-chip module of FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     As shown in FIG. 2, the present invention comprises a multi-chip module  20  that includes a plurality of integrated circuit dice  22 , each recessed in an aperture  23  in an insulating layer  24  of an insulative base  26 . The base  26  may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB, the term PCB as employed herein including conductor-carrying substrates of silicon, ceramic, polymers and other materials known in the art. Although the present invention will be described with respect to multi-chip module embodiments, it will be understood by those having skill in the field of this invention that the present invention is also applicable to single-die applications employing PCB&#39;s or other conductor-carrying bases. It will also be understood that the present invention is applicable to memory dice, such as Dynamic Random Access Memory (DRAM) dice, packaged in Single In-line Memory Modules (SIMM&#39;s), Dual In-line Memory Modules (DIMM&#39;s), and memory cards, as well as to processors and other dice commonly employed singly and in multi-chip assemblies on a variety of conductor-carrying substrates. 
     Backsides (not shown) of the dice  22  are directly attached in a chip-on-board (COB) application to a conductive layer  28  of the base  26  using a conductive die-attach material  30 , such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive. Also, the conductive layer  28  is positioned on a substrate  32  that may comprise one or more PCB layers. It will be understood that the conductive die-attach material and the conductive layer may be thermally conductive, electrically conductive, or preferably both, and that the conductive layer may comprise a wide variety of conductive materials, including copper, gold, and platinum. It should also be understood that there may be more than one vertically-superimposed conductive layer in a base and, consequently, that different dice may be attached to different conductive layers in the same base through apertures  23  extending to different depths of base  26 . 
     Bond pads  34  on front- or active-side surfaces of the dice  22  are wire-bonded to signal traces  36  carried on a surface of the insulating layer  24 . Of course, the bond pads  34  may also be bonded to the signal traces  36  using tape-automated bonding (TAB) techniques, wherein the conductors are carried on a flexible dielectric film. Also, the signal traces  36  may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. Further, it should be understood that, while the multi-chip module  20  of FIG. 2 is shown as having a single insulating layer  24  between the conductive layer  28  and the signal traces  36 , the present invention is equally applicable to COB applications in which there are multiple superimposed layers, such as insulating, conductive, or signal layers, between a conductive layer to which the backside of a die is directly attached and the signal layer to which the front-side of each die is bonded. 
     Because the present invention directly attaches the backsides of dice to a conductive layer, heat from the dice is advantageously conducted away from the dice through the conductive layer. Also, as shown in FIG. 2, a substrate bias voltage generator  38  can supply a substrate bias voltage V bb  to the backsides (not shown) of the dice  22  through the conductive layer  28 . As a result, there is no need for on-board substrate bias voltage generators (not shown) in the dice  22 , and there is no need to supply the substrate bias voltage V bb  to the dice  22  through bond pads  34  on their front-side surfaces. Of course, a supply voltage (commonly designated V cc ), ground potential (commonly designated V ss ), or electronic signal may be supplied to the dice  22  through the conductive layer  28  in place of the substrate bias voltage V bb . Also, although the generator  38  is shown in FIG. 2 as applying a negative substrate bias voltage V bb  to the conductive layer  28 , it should be understood that the generator  38  may instead provide a positive substrate bias voltage V bb  to the layer  28 . 
     The present invention also provides marginally greater physical protection for dice by positioning them within a protective aperture in the thin upper insulating layer  24 . Further, the present invention advantageously allows incrementally shorter bond wires to be used during die-bond because the front-side surfaces of the dice are slightly closer to the level of the signal traces to which they are bonded. While such advantages are relatively small, they are nonetheless significant. 
     As shown in a sectional view in FIG. 3, an alternative version of the multi-chip module  20  of FIG. 2 includes the substrate bias voltage generator  38  directly applying a bias between the conductive layer  28  and a conductive reference layer  41 . Of course, while the reference layer  41  is shown in FIG. 3 as being grounded, it may be coupled to any voltage, particularly other reference voltages. 
     As shown in FIG. 4, the present invention also comprises a multi-chip module  40  that includes a plurality of integrated circuit dice  42 , each recessed in an aperture  43  in insulating layers  44  and  46  and a first conductive layer  48  of an insulative base  50 . The base  50  may comprise an FR-4 glass-epoxy printed circuit board (PCB) or other PCB. 
     Backsides (not shown) of the dice  42  are directly respectively attached in a chip-on-board (COB) application to the first conductive layer  48  and a second conductive layer  52  of the base  50  using a conductive die-attach material (not shown), such as a eutectic solder (e.g., a gold/silver eutectic), a metal-filled epoxy (e.g., a silver-filled epoxy), or a conductive polyamide adhesive. Also, the second conductive layer  52  is positioned on a substrate  54  that may comprise one or more PCB layers. It will be understood that the conductive die-attach material and the conductive layers may be thermally conductive, electrically conductive, or preferably both, and that the conductive layers may comprise a wide variety of conductive materials, including copper, gold, and platinum. 
     Bond pads  56  on front- or active-side surfaces of the dice  42  are Tape-Automated Bonded (TAB) to signal traces  58  carried on a surface of the insulating layer  44 . Of course, the signal traces may comprise a wide variety of conductors, including, without limitation, copper, gold, and platinum. The flexible film (usually polyimide) of the TAB tape has been deleted for clarity. 
     Because the present invention directly attaches the backsides of dice to conductive layers, heat from the dice is advantageously conducted away from the dice through the conductive layers. Also, substrate bias voltage generators (not shown) can supply a first substrate bias voltage V bb1  to the backside (not shown) of one of the dice  42  through the first conductive layer  48  and a second substrate bias voltage V bb2  to the backside (not shown) of the other of the dice  42  through the second conductive layer  52 . As a result, there is no need for on-board substrate bias voltage generators in the dice  42 , and there is no need to supply the substrate bias voltages V bb , and V bb2  to the dice  42  through bond pads  56  on their front-side surfaces. Of course, a supply voltage V cc , ground potential V ss , or electronic signal may be supplied to the dice  42  through the conductive layers  48  and  52  in place of the substrate bias voltages V bb1  and V bb2 . Also, the substrate bias voltages V bb1  and V bb2  can be different voltages. 
     As shown in FIG. 5, the multi-chip module  40  of FIG. 4 can be incorporated into a memory device  60  of an electronic system  62 , such as a computer system, that includes an input device  64  and an output device  66  coupled to a processor device  68 . Of course, the multi-chip module  40  can alternatively be incorporated into the input device  64 , the output device  66 , or the processor device  68 . Alternatively, the multi-chip module (not shown) of FIG. 2 may be incorporated into the input device  64 , output device  66 , processor device  68 , or memory device  60 . Also, the memory device  60  of FIG. 5 may comprise a DIMM, SIMM, memory card or any other memory die-carrying substrate. 
     Although the present invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described.