Abstract:
A voltage converter comprises an input terminal receiving a DC input voltage, an output terminal outputting an output voltage, a first switch coupled between a first node and the input terminal, a second switch coupled between the input terminal and a second node, a first capacitor coupled between the first node and the second node, a third switch coupled between the second node and ground, a fourth switch coupled between a third node and ground, a first electrical device coupled between the third node and the input terminal, a load capacitor coupled between ground and the output terminal, a second electrical device coupled between the first node and the output terminal, a second capacitor coupled between the third node and a fourth node, a fifth switch coupled between the first node and the fourth node, and a sixth switch coupled between the second node and the fourth node.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to a voltage converter. In particular, the invention relates to a multiphase, multistage voltage converter. 
   2. Description of the Related Art 
     FIG. 1  shows conventional three stage two-Phase voltage doubler (TPVD)  100  comprising capacitors C 101 , C 102 , C 103 , C 104  and C 105 , loading capacitor C load  and switches  101 ˜ 112 . Input terminal  110  receives a direct current (DC) input voltage Vin. Output terminal  120  outputs an output voltage Vout. Switch  101  is coupled between node  131  and input terminal  110 . Switch  102  is coupled between nodes  131  and  133 . Switch  103  is coupled between input terminal  110  and node  132 . Switch  104  is coupled between node  132  and ground GND. Capacitor C 101  is coupled between nodes  131  and  132 . Capacitor C 102  is coupled between node  133  and ground GND. Switch  105  is coupled between nodes  133  and  134 . Switch  106  is coupled between nodes  134  and  136 . Switch  107  is coupled between nodes  133  and  135 . Switch  108  is coupled between node  135  and ground GND. Capacitor C 103  is coupled between nodes  134  and  135 . Capacitor C 104  is coupled between node  136  and ground GND. Switch  109  is coupled between nodes  136  and  137 . Switch  110  is coupled between node  137  and output terminal  120 . Switch  111  is coupled between nodes  136  and  138 . Switch  112  is coupled between node  138  and ground GND. Capacitor C 105  is coupled between nodes  137  and  138 . Capacitor C load  is coupled between output terminal  120  and ground GND. 
   Switches  101 ,  104 ,  105 ,  108 ,  109  and  112  are turned on and switches  102 ,  103 ,  106 ,  107 ,  110  and  111  are turned off in first phase φ 1 . Switches  102 ,  103 ,  106 ,  107 ,  110  and  111  are turned on and switches  101 ,  104 ,  105 ,  108 ,  109  and  112  are turned off in second phase φ 2 . The voltage level of node  131  is charged to input voltage Vin during first phase φ 1 , and to double input voltage 2 Vin during second phase φ 2 . The voltage level of node  132  is zero during first phase φ 1  and Vin during second phase φ 2 . Therefore, the voltage level of node  133  is charged to double input voltage 2 Vin. Similarly, the voltage level of node  136  is charged to four times input voltage 4 Vin and the voltage level of loading capacitor C load  is charged to eight times input voltage 8 Vin. The voltage transfer gain of three stages TPVD  100  is eight. In high current application, capacitors must have high capacitance. However, such capacitors can&#39;t be implemented in the voltage converter chip, thus external capacitors are required with corresponding pin increase and increased size, resulting in high cost and more space requirements. 
   BRIEF SUMMARY OF THE INVENTION 
   In order to solve the above-mentioned problem, the invention provides a voltage converter. The voltage converter comprises an input terminal receiving a DC input voltage, an output terminal outputting an output voltage, a first switch coupled between a first node and the input terminal, a second switch coupled between the input terminal and a second node, a first capacitor coupled between the first node and the second node, a third switch coupled between the second node and ground, a fourth switch coupled between a third node and ground, a first electrical device coupled between the third node and the input terminal, a load capacitor coupled between ground and the output terminal, a second electrical device coupled between the first node and the output terminal, a second capacitor coupled between the third node and a fourth node, a fifth switch coupled between the first node and the fourth node, and a sixth switch coupled between the second node and the fourth node. 
   In addition, the invention provides a charge pump circuit comprising an input terminal receiving a DC input voltage, an output terminal outputting an output voltage, a first switch coupled between a first node and the input terminal, a second switch coupled between the input terminal and a second node, a first capacitor coupled between the first node and the second node, a third switch coupled between the second node and ground, a fourth switch coupled between a third node and ground, a first switch device coupled between the third node and the input terminal, a load capacitor coupled between ground and the output terminal, a second switch device coupled between the first node and the output terminal, a second capacitor coupled between the third node and a fourth node, a fifth switch coupled between the first node and the fourth node, and a sixth switch coupled between the second node and the fourth node. 
   In addition, the invention provides a voltage lifter converter comprising an input terminal receiving a DC input voltage, an output terminal outputting an output voltage, a first switch coupled between a first node and the input-terminal, a second switch coupled between the input terminal and a second node, a first capacitor coupled between the first node and the second node, a third switch coupled-between the second node and ground, a fourth switch coupled between a third node and ground, an inductor coupled between the third node and the input terminal, a load capacitor coupled between ground and the output terminal, a load resistor coupled between ground and the output terminal, a diode coupled between the first node and the output terminal, a second capacitor coupled between the third node and a fourth node, a fifth switch coupled between the first node and the fourth node, and a sixth switch coupled between the second node and the fourth node. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
       FIG. 1  shows a three stage two-Phase voltage doubler (TPVD); 
       FIG. 2  shows a multiphase multistage voltage lifter converter according to an embodiment of the invention; 
       FIG. 3  is a timing diagram illustrating control signals (φ 1 , φ 2 , φ 3  . . . φ(N), φ(N+1),  φ (N+1)) of MMVLC of  FIG. 2 ; 
       FIG. 4  shows a MMVLC according to another embodiment of the invention; 
       FIG. 5  shows two stage multiphase voltage lifter converter  500  based on MMVLC of  FIG. 2 ; 
       FIG. 6  is a timing diagram illustrating control signals (φ 1 , φ 2 , φ 3 ,  φ ( 3 )) of two stage, multiphase voltage lifter converter of  FIG. 5 ; 
       FIG. 7  shows two stage multiphase voltage lifter converter of  FIG. 5  when control signal φ 1  is at high voltage level; 
       FIG. 8  shows two stage multiphase voltage lifter converter of  FIG. 5  when control signal φ 2  is at high voltage level; 
       FIG. 9  shows two stage multiphase voltage lifter converter of  FIG. 5  when control signal φ 3  is at high voltage level; 
       FIG. 10  shows multiphase multistage single frequency charge pump (MMSFCP) according to another embodiment of the invention; 
       FIG. 11  is a timing diagram illustrating control signals (φ 1 , φ 2 , φ 3  . . . φ(N), φ(N+1)) of MMSFCP of  FIG. 10 ; 
       FIG. 12  shows a two stage multiphase charge pump circuit based on MMSFCP of  FIG. 10 ; 
       FIG. 13  is a timing diagram illustrating control signal (φ 1 , φ 2 , φ 3 ) of MMSFCP of  FIG. 12 ; 
       FIG. 14  shows a two stage multiphase charge pump circuit of  FIG. 12  when control signal φ 1  is at high voltage level; 
       FIG. 15  shows two stage multiphase charge pump circuit of  FIG. 12  when control signal φ 2  is at high voltage level; and 
       FIG. 16  shows two stage multiphase charge pump circuit of  FIG. 12  when control signal φ 3  is at high voltage level. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  shows a multiphase multistage voltage lifter converter (MMVLC)  200  according to an embodiment of the invention. MMVLC  200  comprises N capacitors (C 1 , C 2 , C 3  . . . C(N)), loading capacitor C load , (4N−2) switches, diode  231  and inductor  232 . The voltage transfer gain Av of MMVLC  200  is: 
           Av   =       Vo   Vin     =         N   ⁡     (     N   +   1     )       2     +       1     1   -   k       ⁢   in   ⁢           ⁢     (     N   +   1     )     ⁢           ⁢   phases               
where k is the duty cycle of the converter governed by
 
           k   =         t   ⁢           ⁢   1     +     t   ⁢           ⁢   2     +     t   ⁢           ⁢   3     +     …   ⁢           ⁢     t   ⁡     (   n   )               t   ⁢           ⁢   1     +     t   ⁢           ⁢   2     +     t   ⁢           ⁢   3     +     …   ⁢           ⁢     t   ⁡     (   n   )         +     t   ⁡     (     n   +   1     )                 
and the minimum numerical value of N is two. Parameters (t 1 , t 2 , t 3  . . . t(n), t(n+1)) are discussed in detail as follows.
 
     FIG. 3  is a timing diagram illustrating control signals (φ 1 , φ 2 , φ 3  . . . φ(N), φ(N+1),  φ (N+1)) of MMVLC  200 . The switches controlled by control signal φ 1  are turned on when control signal φ 1  is at high voltage level, as are other switches, turned on when their respective control signals are at high voltage level. In addition, diode  231  is conductive when control signal φ(N+1) is at high voltage level. Control signal (φ 1 , φ 2 , φ 3  . . . , or φ(N)) may be at high voltage level (phase  1 , phase  2  . . . , or phase (N)) as long as one duration (t 1 , t 2 , t 3  . . . , or t(n)) or may be shorter than one duration (t 1 , t 2 , t 3  . . . , or t(n)). As shown in  FIG. 3 , durations (t 1 , t 2 , t 3  . . . t(n)) are all equal, while duration t(n+1) may be equal, shorter or larger than any of the durations (t 1 , t 2 , t 3  . . . t(n)). 
     FIG. 4  is MMVLC  400  according to another embodiment of the invention. Unlike MMVLC  200 , here, diode  231  is replaced by switch  431 . Switch  431 , controlled by control signal φ(N+1) is turned on when control signal φ(N+1) is at high voltage level. Other operations of MMVLC  400  are similar to those of MMVLC  200 . 
     FIG. 5  shows a two stage multiphase voltage lifter converter  500  of  FIG. 2 . Two stage multiphase voltage lifter converter  500  comprises input terminal  510  receiving a DC input voltage Vin, output terminal  520  outputting an output voltage Vout, switch  501  coupled between node  531  and input terminal  510 , switch  502  coupled between input terminal  510  and node  532 , C 501  coupled between node  531  and node  532 , switch  503  coupled between node  532  and ground GND, switch  504  coupled between node  533  and ground GND, inductor L 507  coupled between node  533  and input terminal  510 , load resistor R load  coupled between ground GND and output terminal  520 , load capacitor C load  coupled between ground GND and output terminal  520 , diode  508  coupled between node  531  and output terminal  520 , capacitor C 502  coupled between node  533  and node  534 , switch  505  coupled between node  531  and node  534 , and switch  506  coupled between node  532  and node  534 . 
   Switch  501  and switch  503  are turned on when control signal φ 1  is at high voltage level, switch  502  and switch  505  are turned on when control signal φ 2  is at high voltage level, switch  506  is turned on and diode  508  is conductive when control signal φ 3  is at high voltage level, and switch  504  is turned off when control signal φ 3  is at low voltage level. 
     FIG. 6  is a timing diagram illustrating control signals φ 1 , φ 2 , φ 3 ,  φ ( 3 )) of two stage multiphase voltage lifter converter  500 . Switches having a control signal φ 1  are turned on when control signal φ 1  is at high voltage level. As are other switches turned on when their respective control signals are at high voltage level. Control signal (φ 1  or φ 2 ) may be at high voltage level (phase  1  or phase  2 ) as long as one duration (t 1  or t 2 ) or shorter than one duration (t 1  or t 2 ). As shown in  FIG. 6 , durations (t 1  and t 2 ) are equal, while duration t( 3 ) may be equal, shorter or longer than durations (t 1  and t 2 ). Switch-on period KT is equal to t 1 +t 2 . Switch-off period (1−K)T is equal to t 3 . Period T is equal to t 1 +t 2 +t 3 . 
     FIG. 7  shows two stage multiphase voltage lifter converter  500  when control signal φ 1  is at high voltage level (phase  1 ). Because switches ( 501  and  503 ), controlled by control signal φ 1 , are turned on, capacitor C 501  is charged to reach a voltage level equal to input voltage Vin at phase  1  (phase  1  may be shorter than duration t 1 ). Due to switches ( 505  and  506 ) being turned off and switch  504  turned on, the top plate of capacitor C 502  is floated and the bottom plate of capacitor C 502  is connected to ground GND. Because the voltage across diode  508  is not high enough, diode  508  is non-conductive. Current I L1  through inductor L 507  increases with time. 
     FIG. 8  shows two stage multiphase voltage lifter converter  500  when control signal φ 2  is at high voltage level (phase  2 ). Switches ( 502  and  505 ) controlled by control signal φ 2  are turned on, connecting the bottom plate of capacitor C 501  to input terminal while the top plate of capacitor C 501  is connected to the top plate of capacitor C 502 . The bottom plate of C 502  is connected to ground GND charging capacitor C 502  until reaching a voltage equal to twice input voltage 2 Vin. Current I L1  is still increasing with time. Because voltage across diode  508  is not high enough, diode  508  is still non-conductive. 
     FIG. 9  shows two stage multiphase voltage lifter converter  500  when control signal φ 3  is at high voltage level (phase  3 ). Switch  504 , controlled by control signal  φ ( 3 ), is turned off. Switch  506 , controlled by control signal φ 3 , is turned on connecting the bottom plate of capacitor C 502  to inductor L 507  while the top plate of capacitor C 502  is connected to the bottom plate of capacitor C 501 . The top plate of C 501  is connected to output terminal. Current I L1  flowing through inductor L 507  increases with voltage Vin during switch-on period KT and decreases with voltage−(Vout−4 Vin) during switch-off period (1−k)T. The ripple of current I L1  is 
             Δ   ⁢           ⁢     i     L   ⁢           ⁢   1         =         Vin     L   ⁢           ⁢   507       ⁢   kT     =         Vout   -     4   ⁢   Vin         L   ⁢           ⁢   507       ⁢     (     1   -   k     )     ⁢     T   .               
The voltage transfer gain is
 
             A   v     =       Vout   Vin     =         4   -     3   ⁢   k         1   -   k       .             
If K=0.5, the voltage transfer gain A v , is 5.
 
     FIG. 10  shows multiphase multistage single frequency charge pump (MMSFCP)  600  according to another embodiment of the invention. MMSFCP  600  comprises N capacitors (C 1 , C 2 , C 3  . . . C(N)), loading capacitor C load , and 4N switches. The voltage transfer gain Av of MMSFCP  600  is 
           Av   =         N   ⁡     (     N   +   1     )       2     +     1   ⁢           ⁢   in   ⁢           ⁢     (     N   +   1     )     ⁢           ⁢   phases             
where the minimum N is two.
 
     FIG. 11  is a timing diagram illustrating control signals φ 1 , φ 2 , φ 3  . . . φ(N), φ(N+1)) of MMSFCP  600 . The switches controlled by control signal φ 1  are turned on when control signal φ 1  is at high voltage level, as are other switches, turned on when their respective control signals are at high voltage level. Control signal φ 1 , φ 2 , φ 3  . . . φ(N), or φ(N+1)) may be at high voltage level (phase  1 , phase  2  . . . , or phase (N+1)) as long as one duration (t 1 , t 2 , t 3  . . . , or t(n)) or may be shorter than one duration (t 1 , t 2 , t 3  . . . , or t(n)). As shown in  FIG. 11 , durations (t 1 , t 2 , t 3  . . . t(n), t(n+1)), are all equal and periods T (T=1/f) of all control signals (φ 1 , φ 2 , φ 3  . . . φ(N), φ(N+1)) are all equal makeing MMSFCP  600  a single frequency charge pump. 
     FIG. 12  shows two stage multiphase charge pump circuit  700  based on MMSFCP  600 . Two stage multiphase charge pump circuit  700  comprises input terminal  710  receiving a DC input voltage Vin, output terminal  720  outputting an output voltage Vout, switch  701  coupled between node  731  and input terminal  710 , switch  702  coupled between input terminal  710  and node  732 , capacitor C 701  coupled between node  731  and node  732 , switch  703  coupled between node  732  and ground GND, switch  704  coupled between node  733  and ground GND, switch  707  coupled between node  733  and input terminal  710 , load capacitor C load  coupled between ground GND and output terminal  720 , switch  708  coupled between node  731  and output terminal  720 , capacitor C 702  coupled between node  733  and node  734 , switch  705  coupled between node  731  and node  734 , and switch  706  coupled between node  732  and node  734 . 
   Switch  701  and switch  703  are turned on when control signal φ 1  is at high voltage level, switch  702  and switch  705  are turned on when control signal φ 2  is at high voltage level, switch  706 , switch  707  and switch  708  are turned on when control signal is at high voltage level, and switch  704  is turned on during durations t 1  and t 2 . 
     FIG. 13  is a timing diagram illustrating control signal φ 1 , φ 2 , φ 3 ) of MMSFCP  700 . Switches having control signal φ 1  are turned on when control signal φ 1  is at high voltage level. As are other switches turned on when their respective control signals are at high voltage level. Control signal (φ 1  or φor φ 2 ) may be at high voltage level (phase  1  or phase  2 ) as long as one duration (t 1  or t 2 ) or shorter than one duration (t 1  or t 2 ). As shown in  FIG. 6 , durations (t 1 , t 2  and t 3 ): are all equal and periods T (T=1/f) of all control signals (φ 1 , φ 2  and φ 3 ) are all equal. 
     FIG. 14  shows two stage multiphase charge pump circuit  700  when control signal φ 1  is at high voltage level (phase  1 ). Because switches ( 701  and  703 ) controlled by control signal φ 1  are turned on, the top plate of capacitor C 701  is connected to input terminal  710  and the bottom plate of capacitor C 701  is connected to ground GND. Capacitor C 701  is charged to reach a voltage level equal to input voltage Vin at phase  1  (phase  1  may be shorter than duration t 1 ). Due to switches ( 705  and  706 ) being turned off and switch  704  being turned on, the top plate of capacitor C 702  is floated and the bottom plate of capacitor C 502  is connected to ground GND. Switch  708  controlled by control signal φ 3  is turned off. 
     FIG. 15  shows two stage multiphase charge pump circuit  700  when control signal φ 2  is at high voltage level (phase  2 ). Due to switches ( 702  and  705 ) being turned on, the bottom plate of capacitor C 701  is connected to input terminal while the top plate of capacitor C 701  is connected to the top plate of capacitor C 702 . Due to switch  704  being turned on, the bottom plate of capacitor C 702  is connected to ground GND. Capacitor C 702  is charged to reach a voltage level equal to two times input voltage 2 Vin. 
     FIG. 16  shows two stage multiphase charge pump circuit  700  when control signal φ 3  is at high voltage level (phase  3 ). Switches ( 707  and  708 ), controlled by control signal φ 3 , are turned on. The bottom plate of capacitor C 702  is connected to input terminal  710  while the top plate of capacitor C 702  is connected to the bottom plate of capacitor C 701 . The top plate of capacitor C 701  is connected to the load capacitor C load . Load capacitor C load  is charged to reach a voltage level equal to four times input voltage 4 Vin. If input voltage Vin is 1V, output voltage Vout is 4V. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.