Abstract:
A display device includes a column driver having an initialization sequence in the vertical blanking interval. The signal used to render the column driver TFT conductive is determined in the vertical blanking interval and maintained on a capacitor in the column driver for the duration of the vertical field. The column driver also includes an autozero comparator which is subject to the autozero operation during the vertical blanking interval.

Description:
This application claims the benefit of U.S. Provisional Application No. 60/096,797 filed Aug. 17, 1998. This application is a divisional application of U.S. patent application Ser. No. 09/201,033 filed Nov. 30, 1998. 
    
    
     FIELD OF THE INVENTION 
     The present invention is directed to self scanned integrated displays and in particular to displays having a column driver which exhibits reduced voltage stress. 
     BACKGROUND OF THE INVENTION 
     Active matrix liquid crystal displays generate images by altering the polarization of individual picture elements using a liquid crystal material. The picture elements (pixels) are arranged in rows and columns. Image data is loaded into the liquid crystal display one row at a time. The rows of pixels are sequentially scanned in order to form image frames. 
     Each pixel in an active matrix display includes a thin film transistor (TFT). The thin film transistor receives video data from a column driver on the display when the display row containing the pixel is selected. The TFT stores the received video data onto the capacitance of the pixel. 
     One material which may be used to form active matrix LCD displays is amorphous silicon. This material has the advantage that it may be fabricated at relatively low temperatures. 
     Because the TFTs of the pixels are fabricated from amorphous silicon. It is desirable to implement the peripheral circuitry, for example, the line scanners and column drivers using TFTs. It is difficult to design circuitry with TFTs, however, because they exhibit threshold drift. Threshold drift is a phenomenon where the gate to source voltage needed to turn on the transistor changes over time. In amorphous silicon TFTs, threshold drift occurs when a TFT is driven at a high duty cycle. 
     U.S. Pat. No. 5,670,979 to Huq et al. entitled “Dataline Drivers with Common Reference Ramp Display” discloses a column driver implemented with amorphous silicon technology. The column driver disclosed in this patent includes circuitry which adjusts the drive voltage of certain ones of the transistors to accommodate for threshold drift in these transistors. The disclosed circuit, however, drives transistors at a relatively high duty cycle, and thus undesirably reduces the expected lifetime of these transistors. 
     SUMMARY OF THE INVENTION 
     The present invention is embodied in a display device which includes a column driver having an initialization sequence in the vertical blanking interval. 
     According to one aspect of the invention, the display device is an active matrix display including a thin-film transistor (TFT) which is connected to drive the column of the display device. The signal used to render the column driver TFT conductive is determined in the vertical blanking interval and maintained on a capacitor in the column driver for the length of the vertical field internal. 
     According to another aspect of the invention, the autozero operation on the comparator of the column driver is performed during the vertical blanking interval. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a conventional column driver. 
     FIG. 2 is a schematic diagram of a column driver circuit according to the present invention. 
     FIG. 3 is a timing diagram which is useful for describing the operation of the column driver shown in FIG.  1 . 
     FIG. 4 is a timing diagram which is useful for describing the operation of the column driver circuit shown in FIG.  2 . 
    
    
     DETAILED DESCRIPTION 
     An XGA display includes 1,024 column drivers, each of which drives 768 pixels. Because the entire XGA display is updated every 16.7 MS, the total line time is approximately 16 microseconds. In this time, potential values stored in the capacitance of each LCD cell of the line are dissipated and new potentials are established. Due to the relatively short amount of time to perform these operations, it is advantageous for the data ramp signal to be active for the longest amount of time possible during the 16 microseconds. According to one aspect of the present invention, the initialization of the column driver circuitry (not shown) of the display device (not shown) is modified so that it occurs during the vertical blanking interval rather than during the horizontal line interval. 
     FIG. 1 is a schematic diagram of a prior art column driver circuit similar to that described in the above referenced patent to Huq et al. The column drivers shown in FIGS. 1 and 2 include features which are not illustrated in the drawing figures. In particular, data signals are loaded into the column drivers in a two step pipeline. During the time at which the column driver is transferring a pixel of line N to the display device for display, the corresponding pixel data for line N+1 is being loaded into the column driver and particularly on to capacitor C 4 . After line N has been loaded into the pixels of the LCD display, the data for line N+1 in each of the column drivers is transferred from capacitor C 4  to capacitor C 3  responsive to the signal DTX. The description of the column driver set forth below does not address the transfer of data from column storage elements into the column drivers via the transistor N 10  and data write pulse, DW. Instead this description begins at the start of the horizontal line period in which the data to be loaded into the array has previously been stored onto the capacitor C 4 . 
     The column drivers shown in FIGS. 1 and 2 also include a feature by which gate voltages applied to certain of the TFT&#39;s are adjusted to compensate for threshold drift. The compensating signal is indicated in FIGS. 1 and 2 as VFB. This signal may be developed, for example, by subjecting a dummy TFT (not shown) to the current and driving potentials of, for example, the transistor N 1 . The response of the dummy transistor may be monitored by feedback circuitry (not shown) to determine the driving voltage needed by the dummy transistor to produce the desired output current. The feedback circuit adjusts the driving voltage by an amount, VFB, to compensate for drift in the threshold voltage of the TFT. This adjustment potential is then applied to other TFT&#39;s in the display device which may be subject to threshold drift. 
     FIG. 1 is described with reference to the timing diagram shown in FIG.  3 . The column driver shown in FIG. 1 is inactive between time T 0  and time T 1 , the row deselect interval. At time T 1 , signal AZ 1  becomes logic high, turning on transistor N 4  and applying a voltage VP 5  (e.g. +5 volts)+VFB to the gate electrode of transistor N 1 . This pulse of the signal AZ 1  establishes a potential of VP 5 +VFB across capacitor CN 1  which represents the gate to source capacitance of the transistor N 1 . Next, at time T 2 , the signal AZ 1  becomes logic low and the signal AZ 2  becomes logic high. Signal AZ 2  turns on transistor N 6  which connects the drain electrode of transistor N 5  to its gate electrode. Due to the potential stored on capacitor CN 1 , this pulse of the signal AZ 2  turns on transistor N 5  allowing the potential stored on capacitor CN 1  to drain to the supply voltage level VM 5  (e.g. −5 volts)+VFB. When the charge across capacitor CN 1  dissipates to just below the potential needed to turn on transistor N 5 , transistor N 5  is rendered non-conductive. 
     This operation of pulse AZ 2  autozeros the comparator, represented by transistor N 5 , by establishing a potential across capacitor CN 5  (the gate to source capacitance of transistor N 5 ) which is substantially equal to the gate to source threshold potential of transistor N 5 . This operation removes this threshold potential from the comparison operation performed by the transistor N 5  when data values are written into the pixels of the display device. 
     Also between times T 2  and T 3 , the signal PC 2  becomes logic high connecting capacitor C 3  to the potential VP 5  through transistor N 7 . This pulse initializes capacitor C 3  at the largest possible pixel potential. This operation conditions the capacitor C 3  to accept the data value stored on capacitor C 4 . Signals AZ 2  and PC 2  are activated at the same time in order to remove any charge from capacitor C 2 , the coupling capacitor between capacitor C 3  and the gate electrode of transistor N 5 , while capacitor C 3  is charged to the VP 5  potential. At time T 3 , both the signals AZ 1  and DTX become logic high. The signal DTX connects capacitor C 4  to capacitor C 3 , causing the potential stored on capacitor C 3  to be reduced in proportion by the pixel data potential stored on capacitor C 4 . Thus, at time T 4 , when signal DTX becomes logic low, the difference between the potential VP 5  and the potential stored on capacitor C 3  is proportional to the data value which had previously been stored on capacitor C 4 . 
     At time T 3 , when signal AZ 1  again becomes logic high, the gate electrode of transistor N 1  is charged to the VP 5 +VFB potential, which turns on the transistor N 1 . At time T 3 , the value of the data ramp signal is at a reference potential (e.g. ground) and any charge which had been stored on the capacitance of the selected pixel is dissipated through transistor N 1 . 
     At time T 5 , the charge on the pixel capacitance has been dissipated and signal AZ 1  becomes logic low. Next, at time T 6 , both of the signals RAMP and DATA RAMP begin to increase. Due to the potential stored across capacitor CN 1  between times T 3  and T 5  responsive to the signal AZ 1 , transistor N 1  remains conductive as the data ramp signal is applied to the pixel capacitance. The signal RAMP is added to the potential stored on capacitor C 3  and the sum of these potentials is applied to the coupling capacitor C 2 . 
     The sum of the signal RAMP, the potential across capacitor C 3  and the potential across capacitor C 2  represents a potential which is applied to the gate electrode of transistor N 5 . As this potential rises above the threshold potential of transistor N 5 , the transistor is turned on, dissipating the charge stored at the gate electrode of transistor N 1 . As this charge dissipates, transistor N 1  is turned off. The potential stored on the pixel capacitance is held at the value of the signal DATA RAMP when transistor N 1  is turned off. 
     The prior art column driver initializes the potential across capacitors CN 1  and CN 5  during each line interval. Thus, transistors N 4  and N 6  are subject to a duty cycle which includes one pulse per line of the image. 
     To improve the expected life times of transistors N 4  and N 6  it is desirable to reduce their duty cycle. In addition, it would be advantageous for the operation of the column driver, especially for a high resolution display device, if the portion of the line time used to store image data into the pixel cells  122  could be increased. 
     FIG. 2 is a schematic diagram of a column driver according to the present invention which achieves these goals. FIG. 2 is described with reference to the timing diagram shown in FIG.  4 . 
     The circuitry shown in FIG. 2 has been modified relative to the circuitry shown in FIG. 1 to activate transistor N 4  only during the vertical blanking interval. In addition, transistors N 2  and N 3  and capacitor C 1  have been added to apply the potential which turns on transistor N 1  prior to the start of the comparison operation. The gate voltage applied to transistor N 2  has been compensated via the feedback voltage VFB to track any threshold drift of transistor N 2 . 
     With reference to FIG. 3, the circuitry shown in FIG. 2 operates as follows. During the vertical blanking interval, at time T 8 , signal RS 1  becomes logic high and RS 2  transitions from a logic-low voltage, V 0 , to a voltage V 1  which is less than the logic-high voltage, V 2 . Signal RS 1  gates the potential VK 1  (e.g. 18 volts)+VFB onto the capacitor C 1  while signal RS 2  holds the lower plate of the capacitor at V 1  potential. The potential VK 1 +VFB is sufficient to turn on transistor N 2 . Applying the potential VK 1 +VFB onto the gate electrode of transistor N 1 . 
     At time T 9 , both of the signals RS 1  and RS 2  become logic low. After time T 9 , capacitor C 1  holds a bias potential substantially equal to the potential VK 1 +VFB minus V 1 , the potential of the signal RS 2  between times T 8  and T 9 . This potential is insufficient to turn on transistor N 2 . During operation of the display device, transistor N 2  may be turned on by applying a logic-high signal RS 2  as described below. 
     Next, at time T 10 , the signals AZ 1 , AZ 2  and PC 2  become logic high. The signal PC 2  turns on transistor N 7 , erasing any residual charge stored on capacitor C 3  as described above. At the same time, signal AZ 1  turns on transistor N 4  applying the potential VP 5  plus VFB to the gate electrode of transistor N 1  and to the junction of the source electrode of transistor N 6  and the drain electrode of transistor N 5 . The logic high signal AZ 2  applied to transistor N 6  turns this transistor on causing it to apply the signal VP 5 +VFB to the gate electrode of transistor N 5 , thus turning on transistor N 5 . 
     At time T 11 , the signal AZ 1  becomes logic low while the signals AZ 2  and PC 2  remain logic high. When the signal AZ 1  becomes logic low, transistor N 4  turns off and the potential applied to the gate electrode of transistor N 1  is dissipated through transistor N 5 , until this potential, as applied to the gate electrode of transistor N 5 , reaches a level just below the gate to source threshold potential of transistor N 5 . Because the signals PC 2  and AZ 2  are logic high at the same time, any charge stored across capacitor C 2  is also dissipated during this interval, while capacitor C 3  is charged to the VP 5  potential. 
     This operation of the signals AZ 1 , RS 2  and AZ 2 , establishes the reference potential across Transistor N 5  which autozeros the comparator of the column driver shown in FIG.  2 . In the exemplary embodiment of the invention, the capacitance CN 5  is sufficient to maintain this autozero potential through the entire frame time. Thus, the autozero operation may be performed on a frame basis only and does not need to be performed each line time, as in the conventional line driver shown in FIG.  1 . 
     The line operations of the column driver shown in FIG. 2 begin at time T 1 , during the row deselect. At time T 1 , the signal PC 2  becomes logic high applying the signal VP 5  to capacitor C 3 , while the signal RAMP is at the reference potential. As described above, this operation erases any stored charge that may exist on capacitor C 3  from the prior storage operation. At time T 2 , the signal RS 2  becomes logic high. When RS 2  becomes logic-high the potential, V 2 , applied to the capacitor C 1  plus the potential stored on the capacitor C 1  causes the potential at the gate electrode of transistor N 2  to turn the transistor on thereby applying the potential VK 1 +VFB to the gate electrode of transistor N 1 . During the time T 2  through T 5 , the signal RS 2  is held logic high, turning on transistor N 1  and allowing any charge on the pixel capacitance to dissipate to the signal DATA RAMP which, during this interval, is at the reference potential. 
     At time T 3 , the signal PC 2  becomes logic low and the signal DTX becomes logic high allowing the charge stored on capacitor C 4  to be transferred onto capacitor C 3  as described above. At time T 4 , the signal DTX becomes logic low turning off transistor N 9  and breaking the connection between capacitors C 3  and C 4 . Thus, after time T 4 , the difference between the potential VP 5  and the potential across capacitor C 3  is proportional to the potential across capacitor C 4 . 
     Once the data on capacitor C 4  has been transferred to capacitor C 3 , the signal PC 1  becomes logic high applying the potential VP 5  to capacitor C 4  and thus erasing any data charge that previously had been stored on the capacitor. This step is done prior to storing new input data onto capacitor C 4  as described above. 
     At time T 5 , the signal RS 2  becomes logic low. At this time, any charge stored on the pixel capacitance has been dissipated and the potential VK 1 +VFB has been stored on the capacitance CN 1 , allowing transistor N 1  to remain turned on after signal RS 2  becomes logic low. At time T 6 , the signals RAMP and DATA RAMP begin increasing in value. As the signal RAMP increases, the combined potential represented by the signal RAMP, the pixel data value stored on capacitor C 3 , and any potential stored across capacitor C 2  is applied to the gate electrode of transistor N 5 . As this potential increases above its gate to source threshold potential, transistor N 5  is turned on, dissipating the charge stored across capacitor CN 1  and turning off transistor N 1 . As described above, the time at which transistor N 1  is turned off determines the potential stored on the pixel capacitance. 
     It is noted that at time T 5  in both FIG.  3  and FIG. 4, the initialization operations that are performed in the line time are complete and the comparison operation may begin. Time T 5  in FIG. 4, however, is considerably earlier in the line time than T 5  in FIG.  3 . This allows a longer portion of the line time for the comparison operation to occur. This is especially important when the circuitry shown in FIG. 2 is used with a high-resolution display such as the XGA type display device of the exemplary embodiment of the invention, because this device has a relatively short line time (e.g. 16 microseconds). In addition, it is noted that the duty cycle of transistor N 4  has been greatly reduced in the embodiment of the invention shown in FIG. 2 as signal AZ 1  is active only during the vertical blanking interval. Furthermore, it is noted that transistor N 2  has been compensated for threshold drift by application of the signal VK 1 +VFB via transistor N 3 , which is also active only during the vertical blanking interval. Thus the column driver circuitry shown in FIG. 2, in addition to being more suitable for use in a high resolution display device also exhibits less voltage stress and, so, a longer lifetime than the prior art circuitry shown in FIG.  1 . 
     While the invention has been described in terms of an exemplary embodiment, it is contemplated that it may be practiced as outlined above within the scope of the appended claims.