Abstract:
An embedded memory system ( 10 ) uses an MRAM core ( 12 ) and error correction code (ECC) corrector circuitry ( 20 ). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or a write cycle and not necessarily when the memory is in a special test mode. As errors are corrected, the error corrections are counted by an error counter ( 24 ) to create a count value. The count value is stored in the MRAM core itself and can later be retrieved and read during a test mode for an indication of how many bit corrections are required for the MRAM core over a period of time. The count value is stored by using an unused portion of a write memory cycle during a read operation.

Description:
FIELD OF THE INVENTION  
       [0001]     This invention relates to Magnetoresistive Random Access Memories (MRAMs), and more particularly to reliability of operation of MRAMs.  
       BACKGROUND OF THE INVENTION  
       [0002]     Non-volatile memory devices, such as FLASH memories, are extremely important components in electronic systems. FLASH is a major non-volatile memory device in use today. Disadvantages of FLASH memory include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 10 4 -10 6  cycles before memory failure. In addition, to maintain reasonable data retention, the scaling of the gate oxide is restricted by the tunneling barrier seen by the electrons. Hence, FLASH memory is limited in the dimensions to which it can be scaled.  
         [0003]     To overcome these shortcomings, magnetic memory devices are being evaluated. One such device is magnetoresistive random access memory (hereinafter referred to as “MRAM”). To be commercially practical, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds.  
         [0004]     For an MRAM device, the stability of the nonvolatile memory state, the repeatability of the read/write cycles, and the memory element-to-element switching field uniformity are three of the most important aspects of its design characteristics. A memory state in MRAM is not maintained by power, but rather by the direction of the magnetic moment vector. Storing data is accomplished by applying magnetic fields and causing magnetic material in a MRAM device to be magnetized into either of two possible memory states. Recalling data is accomplished by sensing the resistive differences in the MRAM device between the two states. The magnetic fields for writing are created by passing currents through strip lines external to the magnetic structure or through the magnetic structures themselves.  
         [0005]     As the lateral dimension of an MRAM device decreases, several problems occur. First, the switching field increases for a given shape and film thickness, requiring a larger magnetic field to switch. Second, the total switching volume is reduced so that the energy barrier for reversal decreases. The energy barrier refers to the amount of energy needed to switch the magnetic moment vector from one state to the other. The energy barrier determines the data retention and error rate of the MRAM device and unintended reversals can occur due to thermofluctuations (superparamagnetism) if the barrier is too small. A major problem with having a small energy barrier is that it becomes extremely difficult to selectively switch one MRAM device in an array. Selectablility allows switching without inadvertently switching other MRAM devices. It is important to control the current flowing during a write operation in the array to avoid undesired current surges or spikes during transistor switching.  
         [0006]     Finally, because the switching field is produced by shape, the switching field becomes more sensitive to shape variations as the MRAM device decreases in size. With photolithography scaling becoming more difficult at smaller dimensions, MRAM devices will have difficulty maintaining tight switching distributions.  
         [0007]     Since MRAMs are subject to reliability issues when the memory is written or programmed due to these issues, a need exists for an improved nonvolatile memory that is more reliable. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0008]     The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings:  
         [0009]      FIG. 1  is a block diagram of an MRAM with an embedded control circuit; and  
         [0010]      FIG. 2  is a cycle timing diagram illustrating timing coordination of error processing between read and write memory cycles. 
     
    
     DETAILED DESCRIPTION  
       [0011]      FIG. 1  illustrates an embedded memory system  10  having error correction circuitry with a counter for counting detected errors during normal read and write cycle operation. An MRAM core  12  is generally illustrated. It should be understood that the MRAM core  12  contains column and row decoders, read sense amplifiers and write drivers that are not specifically illustrated. The MRAM is accessed by an address bus that receives an address value labeled “Address”. The MRAM core  12  also has an error, read and write counts field  14  that is a special memory location for storing error counts, read cycle counts and write cycle counts.  
         [0012]     An input buffer  16  has an input coupled to a bus for receiving input data labeled “Data In”. An output of the input buffer  16  is connected via a bus to an input of an Error Correction Code (ECC) coder  18 . An output of the ECC coder  18  is connected to a data input of the MRAM core  12  via a bus. A data output of the MRAM core  12  is connected via a bus to an input terminal of an ECC corrector  20 . A first output of the ECC corrector  20  is connected to an input of an output buffer  22 . An output of the output buffer  22  provides output data labeled “Data Out”. An error counter  24  has an input connected to a second output of the ECC corrector  20  via a bus. An output of the error counter  24  is connected to a second input of the ECC coder  18  via a bus. The second output of the ECC corrector  20  is also connected to an input of a write cycle counter  26 . An output of the write cycle counter  26  is connected to the second input of the ECC coder  18  via the bus that the output of error counter  24  is connected to. The second output of the ECC corrector  20  is also connected to an input of a read cycle counter  28 . The output of the read cycle counter  28  is connected to the second input of the ECC coder  18  via the bus that the output of error counter  24  is connected to. A control circuit  30  has a first input for receiving a Read control signal and a second input for receiving a Write control signal. A first output of control circuit  30  is connected to a control terminal of the MRAM core  12 . A second output of the MRAM core  12  is connected to a control input of the ECC coder  18 . A third output of the control circuit  30  is connected to a control input of the ECC corrector  20 . A fourth output of the control circuit  30  is connected to a control input of the output buffer  22 . A fifth output of the control circuit  30  is connected to a control input of the error counter  24 . A sixth output of the control circuit  30  is connected to a control input of the write cycle counter  26 . A seventh output of the control circuit  30  is connected to a control input of the read cycle counter  28 . An eighth output of the control circuit  30  is connected to a second input of the read cycle counter  28  for providing a Read Pulse signal. A ninth output of the control circuit  30  is connected to a second input of the write cycle counter  26  for providing a Write Pulse signal. A tenth output of the control circuit  30  is connected to a second input of the input buffer  16  for controlling storage timing of input buffer  16 . A third output of the ECC corrector  20  is connected to a third input of the error counter  24  and to a third input of the control circuit  30 .  
         [0013]     In operation during a Write memory cycle, assume that data is received and stored by input buffer  16  under control of the control signal provided by control circuit  30  when the Write signal is active. The input data is connected to the ECC coder  18  in response to ECC coder  18  receiving an active control signal from control circuit  30 . The ECC coder  18  adds redundancy code to the data before being stored in the MRAM core  12 . The redundancy code is one of several error correction codes known in the art, such as, for example, a Hamming code. The write cycle counter  26  is incremented on each write cycle by control circuit  30 .  
         [0014]     During a Read memory cycle under the control of control circuit  30  after the assertion of the Read signal, data with its redundancy code is transferred to the ECC corrector  20  from the MRAM core  12 . ECC corrector  20  checks the data and redundancy code correcting error(s), if any, and transfers the data to the output buffer  22  under control of control circuit  30 . If an error is detected, error counter  24  is incremented by a signal from ECC corrector  20 . The signal from the ECC corrector  20  also is provided to the control circuit  30 . The read cycle counter  28  is incremented on each read cycle by control circuit  30 .  
         [0015]     After the ECC corrector  20  signals the control circuit  30  that an error has occurred, the control circuit  30  generates control signals to store the values in the error counter  24 , write cycle counter  26  and read cycle counter  28  in error, read and write counts field  14  of MRAM core  12 . To do this storage operation, the control circuit  30  causes the error counter  24  to transfer its current value to ECC coder  18  which adds redundancy code to the current value and stores the information in error, read and write counts field  14  of MRAM core  12 . Likewise, the control circuit  30  causes the write cycle counter  26  to transfer its current value to ECC coder  18  which adds redundancy code to the current value and stores the information in error, read and write counts field  14  of MRAM core  12 .  
         [0016]     The control circuit  30  causes the read cycle counter  28  to transfer its current value to ECC coder  18  which adds redundancy code to the current value and stores the information in error, read and write counts field  14  of MRAM core  12 .  
         [0017]     In another form, the control circuit  30  may be implemented to force error counter  24 , write cycle counter  26  and read cycle counter  28  to transfer their respective count values to the MRAM core  12  for storage in error, read and write counts field  14 . The forced transfer may be implemented either periodically or selectively based upon any of predetermined criteria.  
         [0018]     When the MRAM core  12  is initialized or powered up, the control circuit  30  restores the error count, write cycle count and read cycle count, respectively, to the error counter  24 , write cycle counter  26  and read cycle counter  28  from their values stored in MRAM core  12  at error, read and write counts field  14 . The various control signals provided by control circuit  30  and illustrated in  FIG. 1  implement this initialization of the counters.  
         [0019]     Illustrated in  FIG. 2  is a timing diagram that illustrates an exemplary timing of MRAM core  12 . For purposes of illustration only, five successive cycles are provided out of a series of continuous memory cycles. Additionally, in this example, the MRAM core  12  is assumed to a magnetoresistive random access memory that is a toggle memory, such as described in U.S. Pat. No. 6,545,906 entitled “Method of Writing To Scalable Magnetoresistance Random Access Memory Element”. Each of the memory cycles, whether it is a read cycle or a write cycle, contains an address decode portion and a sense portion. In addition, the read cycles each contain a portion to output data. Separately, the write cycles each contain a portion for comparing a stored bit with a new data bit and then, if necessary, toggling the bit to reverse the stored value. In this illustrated form, cycles 0, 2 and 3 are read cycles and cycles 1 and 4 are write cycles.  
         [0020]     Each cycle is substantially the same time length in the illustrated form but do not necessarily need to be. Illustrated in cycle 2, an error is detected by ECC corrector  20  during a read operation. The controller  30  can then store the error count, write cycle count and read cycle count by using the otherwise unused ECC coder  18  and compare/toggle circuitry in MRAM core  12  (not shown) during any subsequent read cycle(s) and the address portion of the following cycle(s). It should be noted that the compare and toggle operation of a write cycle could complete during cycle 1 and cycle 4 depending upon the time length of cycles 1 and 4, respectively. Such completion makes use of the address decode portion of a following cycle unnecessary. While the cycles in  FIG. 2  are illustrated as having the same length (i.e. synchronous), the operation described herein also is applicable when the cycle lengths vary and asynchronous operation occurs. Whether one or multiple subsequent read cycles are required to update the counter information in MRAM core  12  depends upon the selected bit widths of the count values and memories. For example, in  FIG. 2  the updating in MRAM core  12  of the error count value resulting from the error in cycle 2 is performed in at the end of cycle 3 because cycle 3 happened to be a read cycle. If cycle 3 had been a write cycle then updating of the count value would have to be deferred at least until the next read cycle because otherwise the ECC coder  18  and compare/toggle circuitry is used during write cycles. While the error is illustrated in  FIG. 2  as occurring during a read cycle, it should be understood that the counting applies equally in an analogous manner for detected errors during a write cycle.  
         [0021]     By now it should be apparent that there has been provided an MRAM having ECC circuitry for detecting and correcting soft errors (i.e. random, seldom repeated errors that are not caused from hardware flaws). The MRAM has embedded circuitry (i.e. circuitry contained in a same integrated circuit) that keeps a count value of the number of errors detected, a total number of read cycles executed and the total number of write cycles executed from the time of initial operation of the MRAM.  
         [0022]     The count value is stored in the MRAM during normal operation of the memory and not only during a test of the MRAM or when the MRAM is placed in some other special mode of operation. In other words, detected errors may also be counted during a test mode. However, the control circuit  30  may be configured by a user or programmed to omit the counting of errors during predetermined operational modes, including test. Therefore, the MRAM circuitry described herein permits continuous monitoring of an MRAM memory in use. Because MRAM memories are non-volatile, the error count value stored in the MRAM remains cumulative regardless of whether the MRAM is powered or not. However, it should be understood that control circuit  30  may reinitialize the error count if desired as well as reinitializing either or both of the read cycle count and the write cycle count. The memory operation described herein functions for any type of magnetoresistive random access memory regardless of its principle of operation. Additionally, the memory used herein may be any type of nonvolatile random access memory (NVRAM) in addition to MRAM, such as ovonic memories.  
         [0023]     In one form there is herein provided a memory circuit having a magnetoresistive random access memory (MRAM) core for storing data received by the memory circuit and outputting stored data and a having a reserved portion. An error correction code (ECC) coder adds a redundancy code to the data for storing in the MRAM core. An ECC corrector is coupled to the memory core for performing an analysis of the stored data and the redundancy code to detect and correct errors in the stored data output by the MRAM core and provides an error signal when an error is detected during the performing of the analysis. An error counter is coupled to the ECC corrector and the MRAM core for providing a count of occurrences of the error signal for storage in the reserved portion of the MRAM core. In one form the error counter is coupled to the MRAM core by the ECC coder. In another form the memory circuit further comprises a write cycle counter for providing a count of occurrences of writing data in the MRAM core for storage in the reserved portion of the MRAM core. In yet another form the memory circuit further has a read cycle counter for providing a count of occurrences of reading data from the MRAM core for storage in the reserved portion of the MRAM core. In one form the read cycle counter and the write cycle counter are coupled to the MRAM core by the ECC coder. In another form the memory circuit further includes control circuitry for initiating writing the count of the error counter during an end portion of a read cycle and completing writing the count of the error counter before or during a beginning portion of a cycle immediately following the read cycle. In a further form the control circuitry causes performance of a read operation, a compare operation, and a write operation to perform a write cycle. In another form a memory circuit has a non-volatile random access memory (NVRAM) core for storing data received by the memory circuit and outputting stored data. An ECC corrector is coupled to the NVRAM core, for performing an analysis of stored data fetched from the NVRAM core during a read cycle of the NVRAM core to detect and correct errors in the stored data output by the NVRAM core and providing an error signal when an error is detected from the performing of the analysis. An error counter is coupled to the ECC corrector and the NVRAM core for providing a count of occurrences of the error signal for storage in the NVRAM core. The memory circuit further includes an ECC coder, coupled to the NVRAM core, for adding a redundancy code to the data for storing in the NVRAM core. The ECC corrector performs an analysis of the redundancy code to detect and correct errors. The NVRAM core has a reserved portion and the count of the error counter is stored in the reserved portion. In one form the error counter is coupled to the NVRAM core by the ECC coder. In another form the memory circuit further includes a write cycle counter for providing a count of occurrences of writing data in the NVRAM core for storage in the NVRAM core. In another form the memory circuit further includes a read cycle counter for providing a count of occurrences of reading data from the NVRAM core for storage in the NVRAM core. In one embodiment the read cycle counter and the write cycle counter are coupled to the NVRAM core by the ECC coder. In one form the NVRAM core is a magnetoresistive random access memory core and further includes control circuitry for initiating writing the count of the error counter before or during an end portion of a read cycle and completing writing the count of the error counter during a beginning portion of a cycle immediately following the read cycle. In another form the control circuitry causes performance of a read operation, a compare operation, and a toggle operation to perform a write cycle. There is also provided a method of operating a memory circuit having a non-volatile random access memory (NVRAM) core. Data received by the memory circuit is stored in the NVRAM core. The data stored in the NVRAM core is output. An analysis of the data output from the NVRAM core is performed to detect and correct errors therein. A count of detected errors is obtained. The count in the NVRAM is stored. In one form a redundancy code is stored with the data in the NVRAM core. In another form the analysis includes analyzing the redundancy code. In one form storing the count includes initiating the storing of the count during an end portion of a next read cycle of the memory circuit after an error has been detected and completing the storing of the count before or during an initial portion of a cycle immediately following the next read cycle. In one form the NVRAM core is a magnetoresistive random access memory core and the cycle immediately following the next read cycle is a write cycle. The write cycle in one form has a read operation, a compare operation, and toggle operation. In another form the non-volatile random access memory (NVRAM) core is implemented with bit cells having storage values that are changed by toggling their state. In one form a count of read cycles is made. The count of read cycles is stored in the NVRAM core. A count of write cycles is obtained. The count of write cycles is stored in the NVRAM core. In another form the count of detected errors is compared to the count of write cycles. In yet another form the count of detected errors is compared to the count of read cycles. In a further form the count of detected errors is compared to a sum of the count of read cycles and the count of write cycles.  
         [0024]     Various changes and modifications to the embodiments herein chosen for purposes of illustration will readily occur to those skilled in the art. For example, although a toggle programming MRAM is discussed for some applications, it should be apparent that other types of memory cells may utilize the features disclosed herein. The circuitry may be implemented with transistors of various types and having any type of conductivity. Various types of counters may be used to implement the counting functions discussed herein. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.  
         [0025]     Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms a or an, as used herein, are defined as one or more than one. The term plurality, as used herein, is defined as two or more than two. The term another, as used herein, is defined as at least a second or more. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). The term coupled, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically.