Abstract:
A system and method for controlling an internal combustion engine and electrical inverter system for powering a load, including controlling the operation of a spark-ignited internal combustion engine prime mover used in generation of electrical power by way of a generator. A microprocessor (e.g., DSP) controlled circuit taking engine speed input from an engine speed signal is used to control the operation of the internal combustion engine prime mover so that it is preferably operated substantially at wide open throttle.

Description:
TECHNICAL FIELD 
       [0001]    The present application relates to controllers and control circuits for controlling an internal combustion engine, including a gas fired internal combustion prime mover used for driving a generator for generating electrical power. 
       BACKGROUND 
       [0002]    Modern internal combustion engines are commonly controlled by a control circuit, which typically includes a microprocessor and programmed instructions to control the speed and other parameters of the running of the engine. In motor vehicles (e.g., cars and trucks) the internal combustion engines are operated according to an engine management system of hardware and software programmed by the manufacturer of the vehicle. After market modifications of the engine management circuits and software are sometimes carried out to achieve desired performance results or variations on the operation of the basic engine characteristics. 
         [0003]    Similarly, engines (prime movers) used in electrical power generation systems are controlled and monitored by electronic circuits and programmed instructions running in the circuits. Inputs such as engine revolutions per minute (RPM), operational temperatures, pressures, fuel and air intake rates and concentrations of certain exhaust gases can all be used in addition to the operator&#39;s inputs to control and drive an engines. 
         [0004]    Existing engine controllers and control circuits (collectively “engine controllers”) come in a variety of configurations. Many engine controllers are prone to environmental effects due to the adverse physical conditions in which the engine controllers are disposed. For example, engine controllers can be subjected to temperature extremes and other conditions such as high humidity, contamination and vibration. Modern circuitry in engine controllers can be susceptible to damage from such environmental effects and the reliability or life of an engine controller can suffer as a result. The end result of a failed engine controller can vary from non-optimal engine operation to catastrophic damage to the engine and associated equipment or even personal injury to engine operators. In some applications space is at a premium and an engine controller must occupy as little space as possible, which factors into the design of the controller in some applications. Additionally, economics are a factor that needs to be taken into consideration in the design of engine controllers so that the overall commercial engine and control system is built to conserve design, materials and manufacturing costs thereof. 
         [0005]    Accordingly, a number of motives for improving engine controllers inform the present disclosure of an engine controller, especially an engine controller for a prime mover of an electrical generator or an engine used for co-generation of power and heat in a multifunctional system design. 
       SUMMARY 
       [0006]    This disclosure is directed to controllers and control circuits for controlling an internal combustion engine, including a gas fired internal combustion prime mover used for driving a generator for generating electrical power. This design can be used for engine controllers for internal combustion engines used to drive electrical generators (feeding an electrical load, e.g., grid, AC or DC bus and associated loads). 
         [0007]    Aspects of the invention include a controller for controlling engine speed of a prime mover engine in an electrical generation system, including a housing for containing a plurality of electrical parts of said controller; an engine speed processor that senses a movement of said prime mover engine and generates a first engine speed signal; an input speed processor that receives said first engine speed signal and generates a second engine speed signal corresponding at least in part to said first engine speed signal; an engine metering circuit that receives said second engine speed signal and relates said second engine speed signal to a clock signal and stores engine revolutions (RPM) and other data relating to the speed of said engine in at least one memory storage unit; a digital signal processor (DSP) controller coupled to said engine metering circuit by at least one multi-pin connection so as to permit said DSP to access said at least one memory storage unit on said engine metering circuit; and a host communication interface receiving signals from said DSP over a communication bus and further providing an output control signal for controlling the speed of said engine. 
     
    
     
       IN THE DRAWINGS 
         [0008]    For a fuller understanding of the nature and advantages of the present invention, reference is made to the following detailed description of preferred embodiments and in connection with the accompanying drawings, in which: 
           [0009]      FIG. 1  illustrates an exemplary architecture for generation, transformation and delivery of electrical power to a load; 
           [0010]      FIG. 2  illustrates a representation of an engine controller; 
           [0011]      FIG. 3  illustrates an exemplary engine metering circuit and components; 
           [0012]      FIG. 4  illustrates an engine speed processor; 
           [0013]      FIG. 5  illustrates an input speed processor; 
           [0014]      FIG. 6  illustrates a host communication interface; and 
           [0015]      FIG. 7  illustrates a representation of an engine controller. 
       
    
    
     DETAILED DESCRIPTION 
       [0016]    As stated earlier, improvements in engine controller design can offer better durability, life span, efficiency and economy of an engine and/or engine-generator system. Such systems are employed for example in motor-generator pairs or in electric and heat co-generation systems. A particular but non-limiting use of the present engine controller is for engines operated at or substantially at wide-open throttle, a method of operation found by the present applicants to offer effective use of internal combustion engines in the above applications. 
         [0017]      FIG. 1  illustrates a motor-generator and other (e.g., solar, battery) power generation system  10 . The motor-generator  100  outputs alternating current (AC) electrical power, which is converted to direct current (DC) electrical power in AC-to-DC Converter (ACDC)  102 . Solar collector generation system  110  generates DC electrical power output, which may be transformed or conditioned as needed in DC-to-DC Converter (DCDC)  112 . The DC outputs from ADC  102  and DDC  112  are delivered to a common DC bus  120 . A DC-to-AC Converter (DCAC)  130  transforms the DC power from the common bus  120  to AC electrical power provided to a load  140 . The load  140  may be an electrical grid, customer facility, industrial or residential infrastructure, or an islanding load. 
         [0018]      FIG. 2  illustrates an architecture for an internal combustion engine controller  20  according to one or more embodiments of the invention. Some components of controller  20  will be discussed in further detail below. 
         [0019]    An engine speed processor or circuit  30  is employed to generate an engine speed signal  32  corresponding to the rotational (e.g., revolutions per minute or equivalent) speed of the internal combustion prime mover (engine). The engine speed signal  32  is provided from engine speed processor or circuit  30  to an input speed processor or circuit  40 , which in turn outputs an engine speed input signal  42  for use in other portions of the controller  20 . Engine metering circuit  50  receives numerous signals at its input bus or input pin interface including the engine speed input signal  42 . A shared data bus  52  and a shared address (ADDR) bus  54  are disposed between the engine metering circuit  50  and a digital signal processor (DSP) controller or circuit  60 . DSP controller  60  processes the inputs relating to engine performance and speed from the other components and sensors of the system and outputs a CAN bus signal(s)  62  sent through a host communication interface circuit  70  to a host controller as host controller signal  72 . 
         [0020]      FIG. 3  illustrates a detail of engine metering circuit  50 , which receives an input ESS 2   42  representing engine speed as mentioned herein. Engine metering circuit  50  can be generally viewed as a collection of interconnected components, including a clock generator  51 , a speed signal pulse (+n) component  55 , both of which provide a signal to counter  53 , which in turn provides an output signal to frequency (RPM) converter  57 . FPGA engine metering circuit  50  is then coupled to DSP controller  60  as mentioned above. 
         [0021]      FIG. 4  illustrates an exemplary arrangement of engine speed processor or circuit  30  according to one or more embodiments of the present invention. Those skilled in the art will appreciate that equivalent and similar embodiments aside from the illustrative embodiments of the current examples can be implemented without loss of generality. Various implementations may depend on the specific applications at hand, design constraints, and other factors. Such other configurations and examples are meant to be reasonably comprehended by the scope of the present claims. 
         [0022]      FIG. 4  illustrates a circuit configuration for an engine speed signal generator  30 , which is part of the controller system  20 . A two-pin input sensor or interface connector P 1  is directly or indirectly coupled to an engine speed sensor. Power to circuit  30  is supplied at V 1  and V 2 , which may be received in the form of a  15  Volt supply from a power supply bus or similar voltage reference source. A pair of balanced input resistors R 1 , R 2  are disposed as shown between P 1  and op amp A 1 . A first RC loop comprising resistor R 4  and capacitor C 1  is coupled to a first input (−) of op amp A 1 . A second RC loop comprising resistor R 3  and capacitor C 2  (grounded through G 1 ) is coupled to a second input (+) of op amp A 1 . Capacitors C 3  and C 5  are disposed between voltage input points V 1  and V 2  and ground points G 2  and G 3 , respectively. The output of op amp A 1  representing a first engine speed signal (ESS 1 ,  32 ) is delivered through capacitor C 4  to input speed processor circuit  40 . 
         [0023]      FIG. 5  illustrates an engine input speed processing circuit  40 , which is part of the controller system  20 . The circuit  40  takes first engine speed signal ESS 1 ,  32 , which is referenced in the previous figures, through an input resistance R 5 . An output of R 5  is fed into a first (+) input of op amp A 2 . The second input (−) of op amp A 2  is coupled to ground G 4  through resistance R 6 . A 2  is further fed from source voltages V 3  and V 4 , which are coupled to capacitors C 6  and C 7 . An output of op amp A 2  is delivered to a first diode D 1  through resistor R 8 . A second diode D 2  is coupled to ground at G 5 . The outputs of diodes D 1  and D 2  are connected and coupled back to ground G 5  through resistor R 9  as well as being coupled to the input of Schmitt trigger inverter A 3  through resistor R 10 . Inverter A 3  provides improved signal conditioning between the analog and digital portions of the controller circuit. Inverter A 3  delivers an output ESS 2 ,  42  of circuit  40 , which is a second signal indicative of a speed of the engine. This second engine speed signal (ESS 2 ) is usable as a speed input (SPEED_IN) signal for use in the FPGA circuit  50  below. 
         [0024]    The FPGA processing circuit  50  is an integrated circuit (IC) having a multi-pin input/output circuit interface with the other components of controller  20 . One input received by FPGA is the second engine speed signal ESS 2 ,  42 , described earlier and indicative of a rotational speed of the prime mover engine that is the subject of the present disclosure. Other electronic signals, clocking inputs and so on are also provided to engine metering circuit  50 . 
         [0025]    In an aspect, one mechanical rotation of a prime mover engine causes the speed sensor to generate a number “Q” of output electrical pulses, which can be over 100 such pulses. The number (Q) can then be divided by four (4) so as to ascertain the number of output pulses in a quarter-turn of the prime mover engine. This quarter-turn periodicity can then be correlated with clock counts, and, in an aspect to calculate the revolutions per minute (RPM) of the engine. Those skilled in the art will appreciate that other techniques for revolution counting and clocking and speed processing are possible, which are comprehended by this invention, and that this is but one exemplary technique for doing so. 
         [0026]    The engine metering circuit  50 , is coupled by one or more electronic busses to digital signal processor (DSP) controller circuit  60 , which allow DSP  60  to access memory storage units or addresses on circuit  50 . Engine metering circuit  50  may comprise a field programmable gate array (FPGA) circuit in one embodiment. In another embodiment, engine metering circuit  50  may comprise a reduced instruction set circuit (RISC). 
         [0027]    In an example, provided here for the sake of illustration, two busses connect engine metering circuit  50  and DSP controller circuit  60 . The first is a Data Bus  52  and the second is an address bus  54 . The engine metering circuit  50  is configured to measure the engine speed and store that speed in a register (e.g., memory unit). The DSP controller circuit  60  can read the contents of this register through Data Bus  52  and Address Bus  54 . Other information in the circuit  50  storage registers includes digital I/O status, AC line frequency, and circuit  50  program RPM data. In one configuration, the DSP controller circuit  60  comprises a TMS320 family DSP controller chip from Texas Instruments, or similar DSP chip. The DSP controller circuit  60  can be programmable with machine executable instructions such as a reduced instruction set allowing signal processing functions thereon. In an aspect, the DSP circuit  60  is coupled to the FPGA engine metering circuit  50  by way of the aforementioned buses  52  and  54 . DSP controller  60  delivers CAN bus signal(s)  62 , which include in some embodiments signals over a controller area network (CAN) bus. In an example, the CAN bus is compliant with ISO1050 described at, e.g., www.ti.com/lit/ds/symlink/iso1050.pdf. 
         [0028]      FIG. 6  illustrates an exemplary host communication interface circuit  70 , which is part of controller system  20 . This portion of the controller receives CAN bus inputs (CAN Rx and CAN Tx) that receive and transmit signals from and to DSP controller  60  according to the suitable CAN signaling protocol (e.g., ISO1050). The CAN bus inputs are provided to respective pin connections on ISO1050 circuit (chip) P 2 . Other inputs to circuit P 2  are voltage inputs V 5  and V 6 , which are isolated from grounds G 6  and G 7  by capacitors C 8  and C 9 , respectively. Circuit P 2  is further grounded at ground connections G 8  and G 9  as shown. Circuit P 2  provides CAN outputs to a pair of two-pin Headers P 4  and P 5 , which in an embodiment provides a CAN Low (CANL) signal to Header P 4  and inductor I 2 , and a CAN High (CANH) signal to Header P 5  and inductor I 1  as shown. Headers P 4  and P 5  are grounded through resistors R 11  and R 12 , respectively, which are both in turn coupled to ground G 10  through capacitor C 11 . Here, a header acts as a connector, and typically is a male connector. I 1  and I 2  can comprise one part in some embodiments, which is a common mode choke. 
         [0029]    A four-pin Header P 3  taps into the outputs of inductors I 1 , I 2 , and is further coupled to a voltage V 7 , across capacitor C 10 . The I 1  and I 2  output taps connected to four-pin Header P 3  are further connected to respective pins of a multi-pin CAN input/output (I/O) communication connector  74 . CAN I/O  74  is furthermore connected to ground G 11 . Finally, CAN I/O connector  74  provides an output communication signal (OCS)  72  which is used to control the speed of the prime mover engine-generator pair. Ground connection G 11  on the figure indicates that the physical connector body is grounded. 
         [0030]      FIG. 7  illustrates an internal engine controller system  80  and circuitry according to an embodiment of the invention. The system  80  is used to control the operation, speed and other functional parameters of an engine-generator pair (e.g.,  820 ,  830 ) used to generate electrical power to a load  860 . Those skilled in the art would appreciate that equivalent implementations are possible by rearranging certain parts of the illustrated embodiment, which are comprehended by the attached claims. Also, the illustrated engine controller represents a simplification of detail that would be understood by those skilled in the art. For example, digital signal processing (DSP) and other controllers, amplifiers and processing units themselves include sub-components and circuits and logic blocks that are not illustrated in the present drawing but are understood to be a part thereof. These details can be modified and specifically called out parts could be substituted with similar or equivalent parts as necessary for a given application without loss of generality. 
         [0031]    As described earlier, an engine or generator or shaft RPM sensor (generally, a speed sensor)  825  senses the rotational speed of an engine  820  and/or generator  830 . The speed sensor  825  provides a signal corresponding to engine speed to speed sensing amplifier  860 , which in turn provides an amplified engine speed signal to a signal conditioner  870 . The output of signal conditioner  870  is provided to an engine speed measurement circuit  820 , which may be implemented as a field programmable gate array (FPGA) architecture, but may also be implemented in other (e.g., RISC) configurations. The output of speed measurement FPGA  820  comprises a speed feedback signal  821 . 
         [0032]    Engine controller  80  includes a host microcontroller unit (MCU)  810  having a processor, and a digital signal processing (DSP) controller  800  and other engine speed measuring and signal handling components that receive an output power command or signal  814  and generate an engine speed command  812 . It is noted that those of skill in the art can substitute the exemplary DSP in this embodiment with other architectures, e.g., general processor, graphics processor, etc. 
         [0033]    The engine speed command and speed feedback signal  821  are provided to comparator  808  of DSP controller  800 . The output of comparator  808  is delivered to a PID  804  which amplifies a speed error signal and generates an output current command  806  for use by an inverter grid connection controller  802 . 
         [0034]    Electrical generator  830  provides AC electrical power through AC/DC converter (ADC)  840  and controllable DC/AC inverter  850  to load  860 . 
         [0035]    Therefore, the engine speed is used, among other factors, to control an inverter by way of the above control circuit  80  so as to optimize the running of engine  820  and generator  830  and inverter  850 , especially when engine  820  is operated in a full throttle mode or wide open throttle (WOT) mode of operation. 
         [0036]    The present invention should not be considered limited to the particular embodiments described above, but rather should be understood to cover all aspects of the invention as fairly set out in the present claims. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable, will be readily apparent to those skilled in the art to which the present invention is directed upon review of the present disclosure. The claims are intended to cover such modifications.