Abstract:
Traditionally, buck-boost switching regulators with bridge topologies have been avoided due to their inability to seamlessly transition between buck mode and boost mode. Here, however, a buck-boost switching regulator with a bridge topology has been provided, which has an improved controller. Namely, a processor (such as a digital signals processor or DSP) provides digital control for the bridge to enable it so substantially seamlessly transition between buck mode and boost mode.

Description:
TECHNICAL FIELD 
       [0001]    The invention relates generally to power converters and, more particularly, to power converters using a bridge topology. 
       BACKGROUND 
       [0002]    There are a number of applications that may need a switching regulator or switched mode power supply to operate in non-inverting buck or boost modes, transitioning relatively seamlessly between the two. Turning to  FIG. 1 , an example of a bridge  100 , which can operate in boost and buck modes can be seen. This bridge  100  is generally an H-bridge, using switches S 1  to S 4 , and an inductor L, which is coupled between the switching nodes of the H-bridge. In buck mode, switches S 4  and S 3  are closed and open, respectively, while pulse width modulation (PWM) signals are provided to switches S 1  and S 2 . Alternatively, in boost mode, switches S 1  and S 2  are closed and open, respectively, while PWM signals are provided to switches S 3  and S 4 . 
         [0003]    A problem with bridge  100 , however, is that there are some practical constraints that limit the ability to seamlessly transition between the buck and boost modes, namely, on-time and dead-time. Looking to buck mode, for example, switch S 1  (or S 2 ) cannot seamlessly reach 100% duty cycle. As can be seen in  FIG. 2 , switch S 2 , for example, has a minimum on-time T ON  (which is generally dictated by the physics of switch S 2 ), and there is a dead-time T DEAD  between a rising/falling edge of the PWM signal for switch S 1  and the falling/rising edge of the PWM signal for switch S 2 . If the total on-time for switch S 1  (for example) for a fixed frequency of 1/T (duty cycle in buck mode D BU  times the period T) is greater than the period T minus this predetermined constraint period (D BU *T&gt;T−2T DEAD −T ON ), then the gain (V OUT /V IN ) of the regulator can deviate from an expected value. 
         [0004]    Thus, there is a need for an improved switching regulator. 
         [0005]    Some other conventional circuits are: U.S. Pat. No. 6,166,527; U.S. Pat. No. 6,037,755; and U.S. Patent Pre-Grant Publ. No. 2009/0039852. 
       SUMMARY 
       [0006]    A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises a buck-boost switching regulator having an input terminal, an output terminal, a predetermined buck gain, a predetermined boost gain, a predetermined dead-time, and a predetermined on-time; and control circuitry that is coupled to at least one of the output terminal and the input terminal and that controls the buck-boost switching regulator, wherein the control circuitry employs a compensation function to determine pulse width modulation (PWM) duty cycles for the buck-boost switching regulator, wherein the control circuitry includes a processor and a storage medium with a computer program product embodied thereon, and wherein the computer program product includes: computer code for operating the buck-boost switching regulator in a buck mode when an output of the compensation function is less than the predetermined buck gain; computer code for operating the buck-boost switching regulator in the bridge mode when the output of the compensation function is between the predetermined buck gain and the predetermined boost gain; and computer code for operating the buck-boost switching regulator in a boost mode when the output of the compensation function is greater than the predetermined boost gain. 
         [0007]    In accordance with a preferred embodiment of the present invention, the computer code for operating the buck-boost switching regulator in the bridge mode when the output of the compensation function is between the predetermined buck gain and the predetermined boost gain further comprises: computer code for operating the buck-boost switching regulator in a first bridge mode when the output of the compensation function is between the predetermined buck gain and an intermediate value; and computer code for operating the buck-boost switching regulator in a second bridge mode when the output of the compensation function is between the intermediate value and the predetermined boost gain. 
         [0008]    In accordance with a preferred embodiment of the present invention, the buck-boost switching regulator further comprises: a first switch that is coupled between the input terminal and a first switching node; a second switching that is coupled between the first switching node and ground; an inductor that is coupled between the first switching node and a second switching node; a third switch that is coupled between the second switching node and ground; and a fourth switching that is coupled between the second switching node and the output terminal. 
         [0009]    In accordance with a preferred embodiment of the present invention, the computer code for operating the buck-boost switching regulator in the first bridge mode when the output of the compensation function is between the predetermined buck gain and the intermediate value further comprises: computer code for operating the first switch at a first duty cycle having a value that is the difference between the output of the compensation function and a first constant value; and computer code for operating the third switch at a second duty cycle that is a second constant value, wherein a gain of buck-boost switching regulator, in the first bridge mode, is the product of a third constant and the value of the first duty cycle. 
         [0010]    In accordance with a preferred embodiment of the present invention, the computer code for operating the buck-boost switching regulator in the second bridge mode when the output of the compensation function is between the intermediate value and the predetermined boost gain further comprises: computer code for operating the first switch at a third duty cycle having a fourth constant value; and computer code for operating the third switch at a fourth duty cycle having a value that is the difference between the output of the compensation function and a fifth constant value, wherein a gain of the buck-boost switching regulator, in the second bridge mode, is the product of the fourth constant value and a difference between a sixth constant value and the output of the compensation function. 
         [0011]    In accordance with a preferred embodiment of the present invention, the control circuitry further comprises: a voltage divider that is coupled to the output terminal; and an error amplifier that receives a reference voltage and that is coupled to the voltage divider and the processor. 
         [0012]    In accordance with a preferred embodiment of the present invention, the processor is a digital signals processor (DSP). 
         [0013]    In accordance with a preferred embodiment of the present invention, a method is provided. The method comprises detecting at least one of an input voltage, an output voltage, an input current, and an output current of a buck-boost switching regulator, wherein buck-boost switching regulator includes a predetermined buck gain, a predetermined boost gain, a predetermined dead-time, and a predetermined on-time, and wherein the buck-boost switching regulator includes: a first switch that is coupled between the input terminal and a first switching node; a second switching that is coupled between the first switching node and ground; an inductor that is coupled between the first switching node and a second switching node; a third switch that is coupled between the second switching node and ground; and a fourth switching that is coupled between the second switching node and the output terminal; operating the buck-boost switching regulator in a buck mode when an output of the compensation function is less than the predetermined buck gain; operating the buck-boost switching regulator in a first bridge mode when the output of the compensation function is between the predetermined buck gain and an intermediate value; operating the buck-boost switching regulator in a second bridge mode when the output of the compensation function is between the intermediate value and the predetermined boost gain; and operating the buck-boost switching regulator in a boost mode when the output of the compensation function is greater than the predetermined boost gain. 
         [0014]    In accordance with a preferred embodiment of the present invention, the step of operating the buck-boost switching regulator in the first bridge mode when the output of the compensation function is between the predetermined buck gain and the intermediate value further comprises: operating the first switch at a first duty cycle having a value that is the difference between the output of the compensation function and a first constant value; and operating the third switch at a second duty cycle that is a second constant value, wherein a gain of buck-boost switching regulator, in the first bridge mode, is the product of a third constant value and the value of the first duty cycle. 
         [0015]    In accordance with a preferred embodiment of the present invention, the step of operating the buck-boost switching regulator in the second bridge mode when the output of the compensation function is between the intermediate value and the predetermined boost gain further comprises: operating the first switch at a third duty cycle having a fourth constant value; and operating the third switch at a fourth duty cycle having a value that is the difference between the output of the compensation function and a fifth constant value, wherein a gain of the buck-boost switching regulator, in the second bridge mode, is the product of the fourth constant value and a difference between a sixth constant value and the output of the compensation function. 
         [0016]    In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a solar cell; a buck-boost switching regulator having an input terminal, an output terminal, a predetermined buck gain, a predetermined boost gain, a predetermined dead-time, and a predetermined on-time, wherein the input terminal is coupled to the solar cell; and control circuitry that is coupled to the output terminal and that controls the buck-boost switching regulator, wherein the control circuitry employs a compensation function to determine PWM duty cycles for the buck-boost switching regulator, wherein the control circuitry includes a processor and a storage medium with a computer program product embodied thereon, and wherein the computer program product includes: computer code for operating the buck-boost switching regulator in a buck mode when an output of the compensation function is less than the predetermined buck gain; computer code for operating the buck-boost switching regulator in a first bridge mode when the output of the compensation function is between the predetermined buck gain and an intermediate value; computer code for operating the buck-boost switching regulator in a second bridge mode when the output of the compensation function is between the intermediate value and the predetermined boost gain; and computer code for operating the buck-boost switching regulator in a boost mode when the output of the compensation function is greater than the predetermined boost gain. 
         [0017]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0019]      FIG. 1  is a circuit diagram of a conventional bridge; 
           [0020]      FIG. 2  is a timing diagram illustrating constraints of operation of the bridge of  FIG. 1 ; and 
           [0021]      FIG. 3  is an example of a system in accordance with a preferred embodiment of the present invention; 
       
    
    
     DETAILED DESCRIPTION 
       [0022]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0023]    Turning to  FIG. 3  of the drawings, an example of a system  300  in accordance with a preferred embodiment of the present invention can be seen. System  100  generally comprises a bridge  100 , solar cell  302 , capacitor C 1 , voltage divider (resistors R 1  and R 2 ), error amplifier  308 , processor  304 , and storage medium  306 . Collectively, the voltage divider, error amplifier  308 , processor  304 , and storage medium  306  generally operate as a control circuitry, while bridge  100  and capacitor C 1  generally operate as a buck-boost switching regulator. In operation, an input voltage V IN  and input current I IN  are provide to the input terminal of the switching regulator from, for example, a solar cell  302  (which may include multiple solar cells coupled in series or parallel to the input terminal) so as to generate an output voltage V OUT  and an output current I OUT  at the output terminal. The control circuitry measures the output voltage V OUT  and the input voltage V IN  and generates the appropriate PWM signals for switches S 1  through S 4 . The error amplifier  308  compares an output from the voltage divider to a reference voltage REF so that the processor  304  can perform correction of the PWM signals. In an alternative arrangement, the error amplifier  308  and voltage divider can be removed, with the functionality being provided by the processor  304 . In other alternative arrangements, input current I IN , output current I OUT , or input voltage V IN  may be used instead of the output voltage V OUT  for correction of the PWM signals. Additionally, the processor  304  may be a digital signals processor or DSP. 
         [0024]    For conventional bridge switching or buck-boost operation, pairs of switches S 1 /S 3  or S 2 /S 4  are switched on and off at about the same time, and the duty cycle D BR  is the fraction of the cycle that that switches S 1 /S 3  are on. This switching mode operates generally smoothly through a gain G (ratio of the output voltage V OUT  to the input voltage V IN ) of 1, but it also dissipates more power than either the buck mode or boost mode. The excessive power dissipation is generally due to there being four active switches (instead of two) and generally due to there being a higher average inductor current I L  than in either the buck mode (I L =I OUT ) or boost mode (I L =I IN ); namely, the average inductor current I L  is the sum of the input current I IN  and output current I OUT  (I L =I IN +I OUT ). 
         [0025]    A reduction in this average inductor current I L  is possible, however. Assuming that the duty cycles of the buck (for switches S 1  and S 2 ) and boost (for switches S 3  and S 4 ) sides are independent and assuming that the buck duty cycle D BU  (or boost duty cycle D BO ) represents a fraction of the switching period T that switch S 1  (or S 3 ) is on, the gain G and inductor current IL can be represented as follows: 
         [0000]    
       
         
           
             
               
                 
                   G 
                   = 
                   
                     
                       
                         V 
                         OUT 
                       
                       
                         V 
                         IN 
                       
                     
                     = 
                     
                       
                         D 
                         BU 
                       
                       
                         1 
                         - 
                         
                           D 
                           BO 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
             
               
                 
                   
                     I 
                     L 
                   
                   = 
                   
                     
                       
                         I 
                         IN 
                       
                       + 
                       
                         I 
                         OUT 
                       
                     
                     
                       1 
                       + 
                       
                         D 
                         BU 
                       
                       - 
                       
                         D 
                         BO 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    As shown, the gain G shows that there is a continuum of buck duty cycle D BU  and boost duty cycle D BO  combinations that will produce a gain G, so long as the relationship between buck duty cycle D BU  and boost duty cycle D BO  is obeyed (i.e., D BU =G(1−D BO )). Additionally, it can be seen that a large buck duty cycle D BU  and a small boost duty cycle D BO  create a substantial reduction in inductor current I L . Generally, control of the these duty cycles D BU  and D BO  is performed or executed by processor  304  through the use of software or a computer program product that is embodied on the storage medium  306  (i.e., flash memory). 
         [0026]    Each bridge (i.e.,  100 ) generally has predetermined characteristics, such as a predetermined dead-time, a predetermined on-time, a predetermined maximum buck gain, and a predetermined minimum boost gain. Each of these characteristics generally contribute to the bridge operational modes; typically, two bridge modes are employed. When an output of a compensation function D (which is generated by processor  304  and used to determine PWM duty cycles) is less then the predetermined maximum buck gain, the switching regulator operates in buck mode, and when the output of the compensation function D is greater than the predetermined minimum boost gain, the switching regulator operates in boost mode. However, when the output of the compensation function D is between the predetermined maximum buck gain and a constant value, the switching regulator operates in an initial bridge mode, where: 
         [0000]        D   BU   =D−C   1 ; and  (3)
 
         [0000]        D   BO   =C   2 ,  (4)
 
         [0000]    where C 1  and C 2  are constant values. Now, applying equations (1) and (2) to equations (3) and (4), the gain G and ratio of the inductor current I L  to the input current I IN  for the initial bridge mode are: 
         [0000]    
       
         
           
             
               
                 
                   G 
                   = 
                   
                     
                       D 
                       - 
                       
                         C 
                         1 
                       
                     
                     
                       1 
                       - 
                       
                         C 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       I 
                       L 
                     
                     
                       I 
                       IN 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             I 
                             OUT 
                           
                           
                             I 
                             IN 
                           
                         
                       
                       ) 
                     
                      
                     
                       1 
                       
                         1 
                         + 
                         D 
                         - 
                         
                           C 
                           1 
                         
                         - 
                         
                           C 
                           2 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0000]    Additionally, when the output of the compensation function D is between a constant value and the predetermined minimum boost gain, the switching regulator operates in an final bridge mode, where: 
         [0000]        D   BU   =C   3 ; and  (7)
 
         [0000]        D   BO   =D−C   4 ,  (8)
 
         [0000]    where C 3  and C 4  are constant values. Now, applying equations (1) and (2) to equations (7) and (8), the gain G and ratio of the inductor current I L  to the input current I IN  for the final bridge mode are: 
         [0000]    
       
         
           
             
               
                 
                   G 
                   = 
                   
                     
                       C 
                       3 
                     
                     
                       1 
                       - 
                       D 
                       + 
                       
                         C 
                         4 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
             
               
                 
                   
                     
                       I 
                       L 
                     
                     
                       I 
                       IN 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             I 
                             OUT 
                           
                           
                             I 
                             IN 
                           
                         
                       
                       ) 
                     
                      
                     
                       1 
                       
                         1 
                         + 
                         
                           C 
                           3 
                         
                         - 
                         D 
                         + 
                         
                           C 
                           4 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
           
         
       
     
         [0000]    In order to further illustrate the operation of bridge modes for system  300 , it can be assumed for the sake of illustration for Table 1 that the switching period T, maximum buck gain, minimum boost gain, dead-time, and on-time are 4000 ns, 0.9, 1.0292, 150 ns, and 133 ns, respectively. 
         [0000]    
       
         
               
               
               
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Mode 
                 D 
                 D BU   
                 D BO   
                 G 
                 I L /I IN   
               
               
                   
               
             
             
               
                 Buck 
                 D ≦ 0.9 
                 D 
                 0 
                 D BU   
                 1/D BU   
               
               
                 Initial 
                 0.9 &lt; D &lt; 0.9292 
                 D − 0.0292 
                 0.03333 
                 1.0345(D − 0.0292) 
                 1/(D − 0.0292) 
               
               
                 Bridge 
               
               
                 Final 
                 0.9292 &lt; D &lt; 1.0333 
                 0.9 
                 D − 0.8958 
                 0.9/(1.8958 − D) 
                 1.111 
               
               
                 Bridge 
               
               
                 Boost 
                 D &gt; 1.0333 
                 1 
                 D − 1 
                 1/D 
                 1 
               
               
                   
               
             
          
         
       
     
         [0027]    In order to realize these bridge modes in processor  304  and storage medium  306 , an algorithm is provided that adjusts the boost duty cycle D BO  and buck duty cycle D BU  in terms of a controller clock cycles (i.e., 1/60 MHz=16.67 ns). In Table 2 below, the gain G and ratio of the inductor current I L  to the input current I IN , buck duty cycle D BU , and boost duty cycle D BO  can be seen for an example of this algorithm. 
         [0000]    
       
         
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Mode 
                 D 
                 D BU   
                 D BO   
                 G 
                 I L /I IN   
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 Buck 
                 210 
                 210 
                 0 
                 0.875 
                 1.143 
               
               
                   
                 Buck 
                 211 
                 211 
                 0 
                 0.879 
                 1.137 
               
               
                   
                 Buck 
                 212 
                 212 
                 0 
                 0.883 
                 1.132 
               
               
                   
                 Buck 
                 213 
                 213 
                 0 
                 0.888 
                 1.127 
               
               
                   
                 Buck 
                 214 
                 214 
                 0 
                 0.892 
                 1.121 
               
               
                   
                 Buck 
                 215 
                 215 
                 0 
                 0.896 
                 1.116 
               
               
                   
                 Buck 
                 216 
                 216 
                 0 
                 0.900 
                 1.111 
               
               
                   
                 Initial Bridge 
                 217 
                 210 
                 8 
                 0.905 
                 1.143 
               
               
                   
                 Initial Bridge 
                 218 
                 211 
                 8 
                 0.909 
                 1.137 
               
               
                   
                 Initial Bridge 
                 219 
                 212 
                 8 
                 0.914 
                 1.132 
               
               
                   
                 Initial Bridge 
                 220 
                 213 
                 8 
                 0.918 
                 1.127 
               
               
                   
                 Initial Bridge 
                 221 
                 214 
                 8 
                 0.922 
                 1.121 
               
               
                   
                 Initial Bridge 
                 222 
                 215 
                 8 
                 0.927 
                 1.116 
               
               
                   
                 Initial Bridge 
                 223 
                 216 
                 8 
                 0.931 
                 1.111 
               
               
                   
                 Final Bridge 
                 224 
                 216 
                 9 
                 0.935 
                 1.111 
               
               
                   
                 Final Bridge 
                 225 
                 216 
                 10 
                 0.939 
                 1.111 
               
               
                   
                 Final Bridge 
                 226 
                 216 
                 11 
                 0.943 
                 1.111 
               
               
                   
                 Final Bridge 
                 227 
                 216 
                 12 
                 0.947 
                 1.111 
               
               
                   
                 Final Bridge 
                 228 
                 216 
                 13 
                 0.952 
                 1.111 
               
               
                   
                 Final Bridge 
                 229 
                 216 
                 14 
                 0.956 
                 1.111 
               
               
                   
                 Final Bridge 
                 230 
                 216 
                 15 
                 0.960 
                 1.111 
               
               
                   
                 Final Bridge 
                 231 
                 216 
                 16 
                 0.964 
                 1.111 
               
               
                   
                 Final Bridge 
                 232 
                 216 
                 17 
                 0.969 
                 1.111 
               
               
                   
                 Final Bridge 
                 233 
                 216 
                 18 
                 0.973 
                 1.111 
               
               
                   
                 Final Bridge 
                 234 
                 216 
                 19 
                 0.977 
                 1.111 
               
               
                   
                 Final Bridge 
                 235 
                 216 
                 20 
                 0.982 
                 1.111 
               
               
                   
                 Final Bridge 
                 236 
                 216 
                 21 
                 0.986 
                 1.111 
               
               
                   
                 Final Bridge 
                 237 
                 216 
                 21 
                 0.986 
                 1.111 
               
               
                   
                 Final Bridge 
                 238 
                 216 
                 22 
                 0.991 
                 1.111 
               
               
                   
                 Final Bridge 
                 239 
                 216 
                 23 
                 0.995 
                 1.111 
               
               
                   
                 Final Bridge 
                 240 
                 216 
                 24 
                 1.000 
                 1.111 
               
               
                   
                 Final Bridge 
                 241 
                 216 
                 25 
                 1.005 
                 1.111 
               
               
                   
                 Final Bridge 
                 242 
                 216 
                 26 
                 1.009 
                 1.111 
               
               
                   
                 Final Bridge 
                 243 
                 216 
                 27 
                 1.014 
                 1.111 
               
               
                   
                 Final Bridge 
                 244 
                 216 
                 28 
                 1.019 
                 1.111 
               
               
                   
                 Final Bridge 
                 245 
                 216 
                 29 
                 1.024 
                 1.111 
               
               
                   
                 Final Bridge 
                 246 
                 216 
                 30 
                 1.029 
                 1.111 
               
               
                   
                 Final Bridge 
                 247 
                 216 
                 31 
                 1.033 
                 1.111 
               
               
                   
                 Boost 
                 248 
                 240 
                 8 
                 1.034 
                 1.000 
               
               
                   
                 Boost 
                 249 
                 240 
                 9 
                 1.034 
                 1.000 
               
               
                   
                   
               
             
          
         
       
     
         [0028]    As a result of this configuration, several advantages can be realized. First, there is a relatively seamless transition between buck mode and boost mode, which can be useful for solar applications, where input voltage and input current are generally inflexible. Additionally, the average inductor current I L  can be reduced, which reduces power losses within the switching regulator. 
         [0029]    Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.