Abstract:
A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

Description:
BACKGROUND 
   Semiconductor device performance is related to carrier mobility. For example, in metal-oxide semiconductor (MOS) devices, the higher the carrier mobility in the channel of the device, the faster the current can flow in the channel and the faster the device can perform. 
   Carrier mobility is determined by properties of the semiconductor material such as its lattice constant. Stress in the semiconductor substrate can change the lattice constant and thus the carrier mobility. One way to add stress to the substrate is to add a contact etch stop layer. Further, the thickness of the spacers on the sidewalls of the gate electrode also affect the effect of stress on the substrate. Thick spacers reduce the desirable impact of the strained contact etch stop. However, thick spacers are desirable during the manufacture of semiconductor devices to control short channel effects. Therefore, there is an inherent conflict on the spacer thickness to achieve a well-performing semiconductor device. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1   a  through  1   g  are simplified sectional views of a semiconductor device at selected stages of manufacture; 
       FIG. 2  is a diagram of low pressure chemical vapor deposition (LPCVD) hexachlorodisilane (HCD) silicon nitride (SiN) spacer with high hydrofluoric acid (HF) etch rate at various temperatures; and 
       FIG. 3  is a diagram of low pressure chemical vapor deposition (LPCVD) (TEOS) (tetraethyl orthosilicate) oxide with high hydrofluoric acid (HF) etch rate at various temperatures. 
   

   SUMMARY OF THE INVENTION 
   In one embodiment, a method of forming a semiconductor device comprises forming a gate on a semiconductor substrate, forming a first spacer layer, forming shallow lightly-doped regions on both sides of the gate in the substrate and being offset from the gate by the first spacer layer, forming a second spacer layer over the first spacer layer, etching the first and second spacer layers to form a thick spacer, forming source and drain regions on both sides of the gate in the substrate and being offset from the gate by the thick spacer, and etching the thick spacer to form a thin spacer. 
   In another embodiment, a semiconductor device comprises a substrate, a gate disposed on the substrate, a source and drain formed in the substrate on both sides of the gate, and a thin spacer having a liner layer and a nitrogen-containing layer formed on the sidewalls of the gate, wherein the liner layer and the nitrogen-containing layer have comparable hydrofluoric acid etch rates. 
   In yet another embodiment, a semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant. 
   DETAILED DESCRIPTION 
     FIGS. 1   a  through  1   g  are simplified sectional views of a semiconductor device  10  at selected states of manufacture to illustrate an embodiment of a method of making the device. In  FIG. 1   a , a gate structure  14  is formed over a semiconductor substrate  12 . Semiconductor substrate  12  may be silicon, strained silicon, silicon germanium (SiGe), silicon on insulator (SOI), or another suitable material. Gate structure  14  may be a stack structure comprising a dielectric layer with a polysilicon layer disposed thereon. Other materials such as doped polysilicon, silicon germanium, metal, silicide, etc. may also be used to form the gate electrode. The gate dielectric may be formed with oxide, nitrided oxide, nitride, a high dielectric constant (k) material, silicate, multiple film stacks, or another suitable material or composition. The gate dielectric may be formed using a technique such as chemical vapor deposition (CVD), for example. Lithography techniques may be used to pattern and form gate structure  14 . The gate structure may be a single gate structure, a multiple gate structure, a FinFET gate structure, or a T-gate structure, for example. 
   In  FIG. 1   b , a spacer liner layer  16  is formed or deposited over gate structure  14  and substrate  12 . Spacer liner layer  16  may be an oxide, a nitrided oxide, a nitride, a high k material, or a low k material, for example. The thickness of spacer liner  16  may range from about 1 to 50 nanometers (nm), for example. Preferably, the thickness of spacer liner  16  ranges between about 2 to 10 nm. The precursor material or gaseous reactants may include TEOS (tetraethyl orthosilicate, Si(OC 2 H 5 ) 4 ), TRIES (triethoxysilane), BTBAS (bis tertbutylamino silane), HCD 0 , O 2 , N 2 O, NO, or other materials. The deposition method used to form the spacer liner may be LPCVD (low pressure CVD), PECVD (plasma enhanced CVD), HDP-CVD (high density plasma CVD), APCVD (atmospheric pressure CVD), radical enhanced CVD, ATD (atomic layer deposition), ATCVD (atomic layer CVD), or other methods now known or later developed. 
   In  FIG. 1   c , ions of an appropriate material is implanted into substrate  12  to form lightly doped drain (LDD)  18  or a pocket structure through liner oxide layer  16  on both sides of gate stack  14 . Spacer liner  16  serves as an offset for lightly doped drain implantation. In  FIG. 1   d , a silicon nitride (SiN) spacer layer  20  is deposited over spacer liner layer  16 . Silicon nitride layer  20  may be deposited by a chemical vapor deposition technique such as LPCVD or a method enumerated above. The precursor reactant may include HCD (hexachlorodisilane), BTBAS, DCS (dichlorosilane, SiH 2 Cl 2 ), DS (?), SiH 4 , NH 3 , C 3 H 4 , N 2 , or another suitable material. The process parameters of the chemical vapor deposition step may be tuned so that the hydrofluoric acid (HF) etch rate of silicon nitride layer  20  is high and compatible with the hydrofluoric acid etch rate of the spacer liner. For example, the deposition temperature, pressure, gas flow rate, precursor, and dopant concentration may be set so that the resultant hydrofluoric acid etch rate of silicon nitride layer  20  ranges from about 30 to about 1000 Å per minute at about 100:1 hydrofluoric acid concentration at room temperature. Low deposition temperatures such as less than 630° C. may be used. A chamber pressure of about 0.1 torr to about 10 torr may be used. The nitrogen concentration of spacer layer  20  may range from 1 to 70% in atomic percentage. Spacer layer  20  may further comprise dopants such as carbon, oxygen, fluorine, chlorine, boron, arsenic, etc. The resultant etch rate of silicon nitride layer  20  is preferably the same as the oxide spacer liner  16 . Thereafter, spacer layer  20  and spacer liner  16  are both etched back to form a thick spacer structure  21  as shown in  FIG. 1   e . The spacer thickness may range from about 1 nm to about 200 nm, for example. A suitable dry etch technique may be used to form thick spacer  21 . 
   In  FIG. 1   e , source and drain regions  22  and  24  are formed by implanting an appropriate impurity. Alternatively, semiconductor device  10  may comprise raised SiGe drain and source regions or another suitable structure. In  FIG. 1   f , thick spacer  21  is further etched back to form a thin spacer  25  and then source and drain regions  22  and  24  are annealed. Alternatively, the annealing step may be performed prior to the spacer etch back step. The anneal step may comprise a rapid thermal anneal, a laser anneal, or a furnace anneal, for example. The anneal step also shrinks and densifies the spacer layer without the use of phosphoric acid (H 3 PO 4 ) etching. The shrink rate of the spacer layer may be controlled by the deposition parameters when the spacer layer was formed. Because the etch rate of phosphoric acid is difficult to control and unstable, phosphoric acid etching is undesirable. Therefore, hydrofluoric acid etching to form the spacer is desired. As an example, the etch rate using hydrofluoric acid may range from about 30 to about 1000 Å per minute at about 49% HF to H 2 O in the ratio of about 1:100 at room temperature. After annealing, the spacer etch rate may range from about 10 to about 500 Å per minute at about 49% solution of HF to H 2 O in the ratio of about 1:100 at room temperature. 
   In  FIG. 1   g , a silicide layer  26  is formed on the source, drain and gate electrode. Silicide layer  26  may be, for example, cobalt silicide (CoSi 2 ), nickel silicide (NiSi 2 ), titanium silicide (TiSi 2 ), molibdenum silicide, (MoSi 2 ), platinum silicide (PtSi), tungsten silicide (WSi 2 ), tantalum silicide (TaSi 2 ), etc. Silicide layer  26  may range in thickness from about 3 nm to about 100 nm. Thereafter, a contact etch stop (CES) layer  28  is formed over the source, drain and gate of device  10 . Contact etch stop layer  28  may be constructed of silicon nitride formed using a deposition technique. Contact etch stop  28  may be formed from a highly strained silicon nitride film having stress ranging from about −2 giga-pascal (Gpa) to about 2 Gpa and a thickness of about 100 to about 1000 Å. Contact etch stop layer  28  may be an oxide, a nitride, an oxynitride, a doped nitride, or a multiple film stack structure, for example. Thereafter, a metallization process to form source, drain and gate contacts is performed. 
     FIG. 2  is a diagram of low pressure chemical vapor deposition HCD SiN with high hydrofluoric acid etch rate at various temperatures. Spacer layer  20  preferably has a high etch rate that is compatible with the etch rate of spacer liner  16  so that both may be etched back using the same etch process. The etch rate may be fine-tuned by modifying the deposition parameters such as temperature, pressure, gas flow rate, and doping. The etch rates of the spacer liner and spacer layer should enable the hydrofluoric acid wet etch process to achieve the desired thin spacer profile. As shown in  FIG. 2 , the etch rates of silicon nitride with and without carbon doping at various temperatures can be compared with the etch rates of TEOS oxide at various temperatures shown in  FIG. 3 . 
   Therefore, advantages associated with having a thick spacer during source and drain ion implantation such as the ability to control short channel effect are still realized. After source and drain implantation, the thick spacer is etched back. The thin spacer structure is achieved by shrinkage during annealing of the source and drain formation and primarily by the hydrofluoric acid wet etch process. The spacer liner and the spacer layer are formed with process parameters that contribute to an etch rate that is compatible so that both are etched back in the same etch process. This process thus produces a slim spacer profile without the use of phosphoric acid etching, which is unreliable and difficult to control. The thin spacer structure of the resultant semiconductor device enables the stress induced by a strained channel etch stop to have full impact on carrier mobility and desirable device performance.