Abstract:
A semiconductor device and a method for making the semiconductor device having a barrier layer in a via hole region and a barrier layer in a via line region. The barrier layer in the via line region is initially thicker than the barrier layer in the via hole region, prior to being etched during an etching process due to varying selectivity of etching rates between the via hole region and the via line region.

Description:
BACKGROUND 
   Via hole structures are common and are used to vertically connect metal or metalized layers in semiconductor devices. Via line structures are also used to connect metal layers. In some instances, via line structures are used inside the active area of a chip; in other instances, they are used outside of the active area. 
     FIG. 1  shows via hole structures  101 - 107  used with via line structures  108 - 109  on the same chip.  FIGS. 2A and 2B  show a conventional process for creating both via hole and via line structures on the same chip. Referring to  FIG. 2A , a substrate  201  includes metal lines (or metalized lines)  202  and  203  for contact using a via line and via hole, respectively. It is appreciated that substrate  201  is used for illustrative purposes only and the structure of  201  may occur on top of other layers, not necessarily as part of a substrate, per se. Accordingly, lines  202  and  203  are described as being a first structure  201 . 
   A barrier layer  204  is commonly deposited on top of structure  201 . The barrier layer  204  is used to prevent oxidation or corrosion or migration of the material in metal lines  202 - 203 . Metal lines  202 - 203  may include copper, aluminum, titanium, tantalum and tungsten, and other metals as known in the art. The barrier layer  204  may include SiCN, although other etch stopping compounds can be used. A thick SiCN layer is sometimes helpful as it seals a metal or metalized surface from moisture, corrosion, and metal migration without significantly increasing an interconnect capacitance between a covered metal or metalized layer and the conductive material filling the via hole or via line, so as to make the interconnect unusable. 
   On top of barrier layer  204  is another layer, for instance, a SiOCH layer  205  (also referred to as a SiOCH layer). Topping layer  205  is an oxide layer (for instance, silicon oxide, SiOx)  206 . On top of the oxide layer  206  is a patterned resist layer  207 , having patterned aperture  208  for a via line and  209  for a via hole. 
     FIG. 2B  shows the structure of  FIG. 2A  after etching. Here, an anisotropic etch (for instance, reactive ion etching) may be used to create openings for the via line  210  and via hole  211 . Ashing may or may not be then used to remove the resist layer  207 . 
   One of the issues associated with various etching techniques, including but not limited to RIE, is the variance in selectivity during the etching process. For instance, the rate of etching may to some degree be related to a minimum cross sectional dimension. This means that layer  204  may etch faster over a via line (with a minimum dimension commonly around 100 nanometers) than over a via hole (with a minimum dimension commonly around 10 nanometers in diameter). 
     FIG. 2B  shows a result of the differing etch rates. Here, while layer  204  was properly removed over line  202 , at least a part of it (portion  213 ) remains over hole  203 , thereby preventing complete contact with the metal contact  203 . 
   A process is needed that accounts for the differing etch rates for via lines compared to via holes in semiconductor devices. 
   SUMMARY 
   Aspects of the invention address one or more of the issues described above, thereby providing an improved process for forming via lines and via holes in semiconductor devices. A barrier layer or barrier layers over a contact for a via line region may be thicker (or more numerous) than a corresponding barrier layer or layers over a contact for a via hole region. This difference compensates for varying etching rates or selectivity based on respective sizes of the via hole and via line regions. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The following provides descriptions of the various drawings. 
       FIG. 1  shows a conventional via holes and via lines in a plan view. 
       FIGS. 2A and 2B  show a conventional technique for forming via holes and via lines. 
       FIGS. 3A and 3B  show views of a structure in accordance with aspects of the present invention for forming via holes and via lines. 
       FIGS. 4A-5C  show a first process for making via hole and via lines in accordance with aspects of the present invention. 
       FIGS. 6A and 6B  show a second process for making via holes and via lines in accordance with aspects of the present invention. 
   

   DETAILED DESCRIPTION 
   Aspects of the present invention relates to processes and structures for forming via lines and via holes in semiconductor devices. 
   It is noted that various connections are set forth between elements in the following description. It is noted that these connections in general and, unless specified otherwise, may be direct or indirect and that this specification is not intended to be limiting in this respect. 
     FIG. 3A  shows an illustrative example of a structure for forming via holes and via lines. Via holes  301 - 307  and via lines  308 - 309  are shown.  FIG. 3A  may optionally include an additional layer  308  of a buffer formed on top of metal lines reached by the via lines. 
     FIG. 3B  shows a completed via line and via hole structure.  FIG. 3B  show a structure  311  with metal or metalized lines  312  and  313 . Next is barrier layer  314  for both via holes and via lines. Over the via line sections is an additional barrier layer  310 . Covering the barrier layer (or layers, not shown) is layer or layers  315 . Layer or layers  315  may or may not include a SiOCH layer. Via holes  306  and via lines  308  are filled with a plug material  317  (for instance, tungsten or any other plug material) and capped by metal or metalized contacts  318 . 
   In one example, layer  310  may be at least 50% more than the thickness of layer  314 . This thickness difference may be adjusted up or down based on the resulting etch rate selectivity differences between the etching in the via line region compared against that in the via hole region. 
   The thickness of layer  314  (for instance, a SiCN layer) may be greater than 100 angstroms to be effective in stopping corrosion of metal or metalized lines  312  and  313 . This value may be adjusted to account for via line and via hole sizes. For instance, smaller holes and smaller lines may work well with thinner SiCN layers. As an example, layer  314  may be 350 angstroms in thickness. Layer  310  may be 150 angstroms thick, resulting in a total layer thickness of 500 angstroms in the via line region and 350 angstroms in the via hole region. Here, the percentage difference between 150 angstroms and 350 angstroms is 42.8%. 
   The distances of overlap between the width of the via hole and via line and the metal or metalized lines  312  and  313  may vary. Also, layer  310  may extend beyond the width of the via line dimension by some amount. The amount may be 0 angstroms in some situations. The amount may always be greater than 10 angstroms in others. Here, the amount of overlap may be dependent on the etch rate selectivity and to the degree that etching on the sides of the via line regions may occur, where the overlap of region  310  is to stop the etching into the metal or metalized line  312  around the sides of layer  310 . It is appreciated that the degree of overlap may vary based on the size of the minimum dimension of the via line region: larger minimum dimensions may include the use of a higher overlap (more than 15 angstroms) and smaller minimum dimensions may include the use of less to no overlap (less than 5 angstroms). 
   The following figures describe the formation of the various layers of one or more aspects of the present invention. 
     FIGS. 4A and 4B  and  4 C show a first process and structure for providing a trench for a via line and hole for a via hole. Referring to  FIG. 4A , structure  401  includes metal or metalized lines  403  and  404 . Structure  401  is covered by barrier layer  402  (for example, SiCN) and by another barrier layer  410  (also for example, SiCN). A resist layer is deposited and patterned  407 . 
     FIG. 4B  shows layer  410  having been etched back and patterned resist layer  407  removed. 
     FIG. 4C  shows additional layers added to the structure of  FIG. 4B . In particular, layer  405  (which may be a SiOCH layer) may be deposited. The next layer may include an oxide layer  406  (for example, a silicon oxide layer), upon which is formed a resist layer  407  with apertures  411  and  412 . The layers may be deposited and/or grown through standard techniques. 
     FIG. 5A  shows the structure of  FIG. 4C  having been etched (for example, by RIE) to remove the material of layer  405  (possibly a SiOCH layer), resulting in trenches  411  and  412  for the via line and via hole, respectively. Here, the two barrier layers  402  and  410  prevented the etching process from penetrating through to metal or metalized line  404  and  403 . It is noted that via line  411  includes a double layer of barrier layer ( 402  and  410 ). 
   The following describes two situations where the etching of layer  405  of  FIG. 4A  may vary: etching differences between via hole and via line regions for a specific chip and etching differences across a wafer. 
   1. Etching Differences Between Via Hole and Via Line Regions
         With respect to etching between via hole and via line regions, in some situations, the RIE etch to remove relevant sections of layer  405  may also etch into barrier layer or layers  402  and  410 . The RIE etch for layer  405  may, in some situations, be more active in via line regions than in via hole regions.  FIG. 5A  shows an example where the RIE etch for layer  405  removed all of layer  405  in via hole region  412 . However, because of the varying etch rates for via hole and via line regions, the RIE etch for layer  405  continued to etch into layer  410  of via line region  411 . The result is at least a partial removal of barrier layer  410  as shown by the new surface  502  of barrier layer  410 . Depending on the degree of etching, the RIE etch for removal of layer  405  may etch a partial amount of barrier layer  410  or all the way through layer  410  to the surface of layer  402  (and possibly into barrier layer  402 ). Additionally, there may or may not be some etching of layer  402  in the via hole region as well from the RIE etch to remove layer  405 .       

   2. Etching Across Wafer
         With respect to etching across chips on a wafer, variations may occur across a wafer including but not limited to varying etch rates and layer thicknesses across the wafer. In some situations, additional etching may be required to ensure that the RIE etch to remove layer  405  has, for all chips, completely removed layer  405  in the via hole and via line regions. In an additional example, the RIE etch for removing layer  405  may be continued to allow for the etch to remove layer  410  to the surface of layer  402  in the via line region for all chips. For example, to ensure the RIE etch of layer  405  has etched through layer  410  to the surface of layer  402  in all via line regions, etching time may be increased by 20%. The 20% increase in etch time to ensure complete etching across a wafer is typical. It is appreciated that the etch time increase may be varied (increased or decreased) according to operational conditions, structure complexity, and/or other conditions known in the art.       

   Continuing with  FIG. 5A , the structure of  FIG. 5A  may be ashed to remove the photoresist layer  407 . The structure may be subjected to an RIE SiCN etch to etch through the SiCN layers  402  and  410 . Because of the faster etching in the via line region  411  matched with the additional layer of SiCN  410 , the etching time required to etch through the SiCN in the via line region  411  can be made to approximately match the etching time needed to etch through the SiCN in the via hole region  412 . This has the effect of the SiCN etching through the SiCN to the surface of the metal or metalized lines  403  and  404 , without significantly etching into them. The resulting structure is shown in  FIG. 5B . 
   The following charts explain the distinctions of the results of etching between the etching of conventional layers in  FIG. 2B  and etching of the layers of  FIG. 5B . 
   
     
       
             
             
             
             
           
         
             
                 
             
           
           
             
                 
                 
               RIE Etching 
                 
             
             
                 
                 
               Rates 
             
             
                 
                 
               (pre-barrier 
             
             
                 
                 
               layer etch 
             
             
               Type of 
               Barrier Layer of 
               and barrier 
               Effect of RIE 
             
             
               Region 
               FIGS. 2A-2B 
               layer etch) 
               Etches 
             
             
                 
             
             
               Via Line 
               Same thickness 
               Faster than 
               Combined faster 
             
             
               Region 
               barrier layer 
               via hole 
               etch rates etch 
             
             
                 
               in via hole and 
               etch rate 
               through via 
             
             
                 
               via line regions 
                 
               line region 
             
             
                 
                 
                 
               barrier layer 
             
             
                 
                 
                 
               before via 
             
             
                 
                 
                 
               hole region 
             
             
                 
                 
                 
               barrier layer 
             
             
               Via Hole 
               Same thickness 
               Slower than 
               Some of 
             
             
               Region 
               barrier layer 
               via line 
               barrier layer 
             
             
                 
               in via hole and 
               etch rate 
               in via hole 
             
             
                 
               via line regions 
                 
               region remains 
             
             
                 
             
             
                 
                 
               RIE Etching 
                 
             
             
                 
                 
               Rates 
             
             
                 
                 
               (pre-barrier 
             
             
                 
                 
               layer etch 
             
             
               Type of 
               Barrier Layer of 
               and barrier 
               Effect of 
             
             
               Region 
               FIGS. 5A-5B 
               layer etch) 
               RIE Etches 
             
             
                 
             
             
               Via Line 
               Thicker barrier 
               Faster than 
               Combined faster 
             
             
               Region 
               layer/additional 
               via hole 
               etch rates 
             
             
                 
               barrier layer in 
               etch rate 
               etch through 
             
             
                 
               via line regions 
                 
               thicker/ 
             
             
                 
                 
                 
               additional 
             
             
                 
                 
                 
               barrier layers 
             
             
                 
                 
                 
               in same time 
             
             
                 
                 
                 
               as etching 
             
             
                 
                 
                 
               through 
             
             
                 
                 
                 
               thinner/fewer 
             
             
                 
                 
                 
               barrier layers 
             
             
                 
                 
                 
               in via hole 
             
             
                 
                 
                 
               regions 
             
             
               Via Hole 
               Thinner/fewer 
               Slower than 
               Barrier layers 
             
             
               Region 
               barrier layers 
               via line 
               removed in both 
             
             
                 
               in via hole 
               etch rate 
               via hole and 
             
             
                 
               regions 
                 
               via line regions 
             
             
                 
             
           
        
       
     
   
   Next, the structure of  FIG. 5B  may be further processed. The via line and via hole regions maybe filled and capped with conventional materials  317  and  318  (including but not limited to tungsten), thereby providing via holes and via lines. The resulting structure is shown in  FIG. 5C . 
     FIGS. 6A and 6B  show another process for adjusting the thickness of SiCN layers to account for varying etch rates in the via hole and via line regions. Similar to the structure of  FIGS. 4A-4C ,  FIG. 6A  includes an extra SiCN layer  601 . This layer can be used in situations where the via holes are larger (or the via lines are narrower), thereby providing effective etching times that are closer where using only a single barrier layer for via hole regions and double barrier layers for via line regions.  FIG. 6B  shows the result of ashing of resist layer  407 , etching through layer  405  (which may or may not include SiOCH), and a SiCN etch through layers  402 ,  410 , and  601  to metal or metalized lines  403  and  404 . 
     FIGS. 6A and 6A  represent that any number of barrier layers can be used. Additional layers or fewer layers for via line  411  compared to the via hole  412  allow for fine tuning the SiCN etching process so that consistent and reliable etching of the SiCN layer (or layers) occurs. 
   It is appreciated that the different number of barrier layers between the via line and via hole regions may be replaced or augmented with thicker or thinner barrier layers between the various regions. 
   It is appreciated that the figures described above show the layers as continuous between the via hole and via line regions. This has been done for simplicity of illustrations. In most situations, the layers may be disconnected or deposited at different times. For instance, the layers may be separated by other structures or distances as shown by broken line A in  FIGS. 3B ,  4 A,  4 B,  4 C,  5 A,  5 B,  6 A, and  6 B.