Abstract:
In an offset cancelling circuit of a Hall element, a voltage is applied from four directions and from outside such that a current flowing in the Hall element is switched by 90°, to set a first state through a fourth state, and output voltages of the Hall element in the first state through the fourth state are averaged.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The entire disclosure of Japanese Patent Application No. 2009-136907 filed on Jun. 8, 2009, including specification, claims, drawings, and abstract, is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Technical Field 
     The present invention relates to an offset cancelling circuit which is used for adjustment of an output or the like of a Hall element. 
     2. Related Art 
     In recent years, image capturing devices such as a digital still camera and a digital video camera realize higher image quality by increasing the number of pixels of an image capturing element of the image capturing device. On the other hand, as another method for realizing higher image quality of the image capturing device, it is desired to equip the image capturing device with a vibration absorption control circuit having a shake correction function in order to prevent shaking of imaging target caused by shaking of the hand holding the image capturing device. 
     A vibration absorption control circuit for shake correction receives a signal from a gyro sensor which detects an angular velocity component generated by vibration of the image capturing device, and drives optical components such as a lens and an image capturing element according to the received signal, to prevent shaking of the imaging target. With such a configuration, even if the image capturing device vibrates, the component of the vibration is not reflected in the obtained image signal, and a high-quality image signal having no image shaking can be obtained. 
     In this process, a Hall element is used for detecting a position of the optical component such as the lens which is driven. As shown in  FIG. 8 , an equivalent circuit of the Hall element  10  can be represented as a bridge circuit of resistors R 1 ˜R 4 . Because of this, an output signal of the Hall element  10  includes an offset component due to influences of variations in the resistors, according to a combination of a terminal on which a power supply voltage Vcc is applied and a terminal from which the output signal is extracted. 
     In consideration of this, an offset cancelling circuit is used which applies a voltage such that currents flowing in the Hall element  10  differ by 90°, and adds and calculates an average of the output voltages. When the current flowing in the Hall element  10  is changed by 90°, the offset of the output voltage of the Hall element  10  occurs in an opposite direction, and thus the offset value of the output voltage of the Hall element  10  is cancelled. 
     The offset cancelling circuit of the related art assumes that no change occurs in the resistors R 1 ˜R 4  of the equivalent circuit of the Hall element in a first state and a second state. 
     However, in a normal Hall element, there is a voltage dependency of the resistors R 1 ˜R 4 . As shown in  FIG. 9 , the resistors R 1 ˜R 4  are represented as an N-type semiconductor element in which a P-type substrate is grounded. When the terminal A is grounded, Vcc is applied to the terminal B, and Vcc/2 is applied to the terminal D as shown in  FIG. 9 , there is a difference in a depth in a depletion layer (channel) X formed in the element, and thus the resistors R 1 ˜R 4  have a voltage dependency. In other words, the values of resistors R 1 ˜R 4  would vary depending on the combination of the voltages applied to the terminals A˜D. 
     In such a case, the offset value of the output voltage of the Hall element cannot be accurately cancelled with the offset cancelling circuit of the related art. 
     SUMMARY 
     According to one aspect of the present invention, there is provided an offset cancelling circuit for a Hall element, wherein voltages are applied from four directions and from outside such that a current flowing in the Hall element is switched by 90° to achieve a first state through a fourth state, and output voltages of the Hall element in the first state through the fourth state are averaged. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A preferred embodiment of the present invention will be described in further detail based on the following drawings, wherein: 
         FIG. 1  is a diagram showing a structure of an offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIG. 2  is a diagram showing a first state of the offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIG. 3  is a diagram showing a second state of the offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIG. 4  is a diagram showing a third state of the offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIG. 5  is a diagram showing a fourth state of the offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIG. 6  is a diagram showing an output state of the offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIGS. 7A˜7D  are diagrams showing an action of the offset cancelling circuit according to a preferred embodiment of the present invention; 
         FIG. 8  is a diagram showing a structure of an offset cancelling circuit in related art; and 
         FIG. 9  is a diagram for explaining a voltage dependency of an offset value of an output voltage of a Hall element. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows a basic structure of an offset cancelling circuit (OC circuit)  100  of a Hall element. The offset cancelling circuit  100  comprises a Hall element  10 , an amplifier circuit  12 , and an averaging circuit  14 . 
     The Hall element  10  can be represented as a bridge circuit of resistors R 1 ˜R 4 . Switching elements S 1 ˜S 12  which switch connection points A˜D of the resistors R 1 ˜R 4  to a power supply voltage Vcc, ground, or output are connected to the resistors R 1 ˜R 4 . 
     The amplifier circuit  12  comprises operational amplifiers  12   a  and  12   b . The operational amplifier  12   a  amplifies a voltage which is input to a non-inverting input terminal (+) and outputs the amplified voltage. The operational amplifier  12   b  amplifies a voltage which is input to a non-inverting input terminal (+) and outputs the amplified voltage. 
     The averaging circuit  14  comprises switching elements S 13 ˜S 30 , capacitors C 1 ˜C 4 , and an operational amplifier  14   a  (which may be of a Schmitt buffer type). As shown in  FIG. 1 , the switching elements S 13 ˜S 30  connect any of output terminals of the operational amplifiers  12   a  and  12   b , terminals of the capacitors C 1 ˜C 4 , and an input terminal of the operational amplifier  14   a  with each other. 
     An operation of the offset cancelling circuit  100  will now be described. The offset cancelling circuit  100  cancels the offset value of the output voltage of the Hall element  10  and outputs the resulting voltage by switching among a first state through a fourth state and an output state which will be described below. 
     First, as shown in  FIG. 2 , the switching elements S 1 ˜S 30  are controlled to be switched ON and OFF, to set the offset cancelling circuit  100  to a first state. The switching element S 1  is switched ON and the switching elements S 2  and S 3  are switched OFF to apply a power supply voltage Vcc to the connection point A of the resistors R 1  and R 3 , the switching element S 5  is switched ON and the switching elements S 4  and S 6  are switched OFF to connect the connection point B of the resistors R 2  and R 4  to the ground, the switching element S 9  is switched ON and the switching elements S 7  and S 8  are switched OFF to connect the connection point C of the resistors R 1  and R 2  to the non-inverting input terminal (+) of the operational amplifier  12   b , and the switching element S 12  is switched ON and the switching elements S 10  and S 11  are switched OFF to connect the connection point D of the resistors R 3  and R 4  to the non-inverting input terminal (+) of the operational amplifier  12   a . In addition, of the switching elements S 13 ˜S 30 , the switching elements S 14  and S 16  are switched ON and the other switching elements are switched OFF to connect the output of the operational amplifier  12   a  to a positive terminal of the capacitor C 1  and the output of the operational amplifier  12   b  to a negative terminal of the capacitor C 1 , so as to achieve a state where the capacitor C 1  is charged by the output voltages of the operational amplifiers  12   a  and  12   b . This state is referred to as the first state. 
     Next, as shown in  FIG. 3 , the switching elements S 1 ˜S 30  are controlled to be switched ON and OFF, to set the offset cancelling circuit  100  to a second state. The switching element S 3  is switched ON and the switching elements S 1  and S 2  are switched OFF to connect the connection point A of the resistors R 1  and R 3  to the non-inverting input terminal (+) of the operational amplifier  12   a , the switching element S 6  is switched ON and the switching elements S 4  and S 5  are switched OFF to connect the connection point B of the resistors R 2  and R 4  to the non-inverting input terminal (+) of the operational amplifier  12   b , the switching element S 8  is switched ON and the switching elements S 7  and S 9  are switched OFF to connect the connection point C of the resistors R 1  and R 2  to ground, and the switching element S 10  is switched ON and the switching elements S 11  and S 12  are switched OFF to apply the power supply voltage Vcc to the connection point D of the resistors R 3  and R 4 . In addition, of the switching elements S 13 ˜S 20 , the switching elements S 13  and S 15  are switched ON and the other switching elements are switched OFF, to connect the output of the operational amplifier  12   a  to a negative terminal of the capacitor C 2  and the output of the operational amplifier  12   b  to a positive terminal of the capacitor C 2 , so as to achieve a state where the capacitor C 2  is charged by the output voltages of the operational amplifiers  12   a  and  12   b . This state is referred to as the second state. 
     Next, as shown in  FIG. 4 , the switching elements S 1 ˜S 30  are controlled to be switched ON and OFF, to set the offset cancelling circuit  100  to a third state. The switching element S 2  is switched ON and the switching elements S 1  and S 3  are switched OFF to connect the connection point A of the resistors R 1  and R 3  to ground, the switching element S 4  is switched ON and the switching elements S 5  and S 6  are switched OFF to apply the power supply voltage Vcc to the connection point B of the resistors R 2  and R 4 , the switching element S 9  is switched ON and the switching elements S 7  and S 8  are switched OFF to connect the connection point C of the resistors R 1  and R 2  to the non-inverting input terminal (+) of the operational amplifier  12   b , and the switching element S 12  is switched ON and the switching elements S 10  and S 11  are switched OFF to connect the connection point D of the resistors R 3  and R 4  to the non-inverting input terminal (+) of the operational amplifier  12   a . In addition, of the switching elements S 13 ˜S 20 , the switching elements S 17  and S 19  are switched ON and the other switching elements are switched OFF, to connect the output of the operational amplifier  12   a  to a negative terminal of the capacitor C 3  and the output of the operational amplifier  12   b  to a positive terminal of the capacitor C 3 , so as to achieve a state where the capacitor C 3  is charged by the output voltages of the operational amplifiers  12   a  and  12   b . This state is referred to as the third state. 
     Next, as shown in  FIG. 5 , the switching elements S 1 ˜S 30  are controlled to be switched ON and OFF, to set the offset cancelling circuit  100  to a fourth state. The switching element S 3  is switched ON and the switching elements S 1  and S 2  are switched OFF to connect the connection point A of the resistors R 1  and R 3  to the non-inverting input terminal (+) of the operational amplifier  12   a , the switching element S 6  is switched ON and the switching elements S 4  and S 5  are switched OFF to connect the connection point B of the resistors R 2  and R 4  to the non-inverting input terminal (+) of the operational amplifier  12   b , the switching element S 7  is switched ON and the switching elements S 8  and S 9  are switched OFF to apply the power supply voltage Vcc to the connection point C of the resistors R 1  and R 2 , and the switching element S 11  is switched ON and the switching elements S 10  and S 12  are switched OFF to connect the connection point D of the resistors R 3  and R 4  to ground. In addition, of the switching elements S 13 ˜S 20 , the switching elements S 18  and S 20  are switched ON and the other switching elements are switched OFF, to connect the output of the operational amplifier  12   a  to a positive terminal of the capacitor C 4  and the output of the operational amplifier  12   b  to a negative terminal of the capacitor C 4 , so as to achieve a state where the capacitor C 4  is charged by the output voltages of the operational amplifiers  12   a  and  12   b . This state is referred to as the fourth state. 
     In this manner, the first through the fourth states are switched for the Hall element  10 , to charge the capacitors C 1 ˜C 4  with the Hall voltages V 1 ˜V 4 , respectively, of four directions)(360°), 90° each, for the four terminals of the Hall element  10 . The offset cancelling circuit  100  is then set in an output state to average the charged voltages V 1 ˜V 4  of the capacitors C 1 ˜C 4 , to cancel the offset value of the output voltage of the Hall element  10 , and output the resulting voltage. 
     In the output state, as shown in  FIG. 6 , the switching elements S 13 ˜S 20  are switched OFF, to disconnect the operational amplifiers  12   a  and  12   b  and the capacitors C 1 ˜C 4 . In addition, the switching elements S 21 ˜S 30  are switched ON to commonly connect the negative terminals of the capacitors C 1 ˜C 4  to one of the input terminals of the operational amplifier  14   a , and commonly connect the positive terminals of the capacitors C 1 ˜C 4  to the other one of the input terminals of the operational amplifier  14   a . In this manner, the charged voltages V 1 ˜V 4  of the capacitors C 1 ˜C 4  are averaged and output from the output terminal of the operational amplifier  14   a . When the operational amplifier  14   a  is of a Schmitt buffer type, a high-level output and a low-level output are switched and output according to the size relationship between the two input terminals. 
     An operation to cancel the offset value of the output voltage of the Hall element  10  by the offset cancelling circuit  100  will now be described with reference to  FIGS. 7A˜7D . 
       FIG. 7A  shows an equivalent circuit of the Hall element  10  when the offset cancelling circuit  100  is switched to the first state. In the first state, the resistors R 1  and R 3  are at the high-voltage side (power supply voltage Vcc side) and the resistors R 2  and R 3  are at the low-voltage side (ground side). In this configuration, because of the voltage dependency of the resistors, the resistors R 1  and R 3  have values R 1 =r 1 +α and R 3 =r 3 +α, respectively, and similarly, the resistors R 2  and R 4  have values R 2 =r 2 −α and R 4 =R 4 −α, respectively. Therefore, the voltage V 1  stored in the capacitor C 1  is represented by the following equation (1). In the equation, an offset value which does not have a voltage dependency is represented as Voff. 
     
       
         
           
             
               
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                     ] 
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             
                               
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                                 ⁢ 
                                 
                                     
                                 
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                                 4 
                               
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                                 ⁢ 
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                               + 
                               
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                                 4 
                               
                             
                           
                           - 
                           
                             
                               
                                 r 
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                                 2 
                               
                               - 
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                                 r 
                                 ⁢ 
                                 
                                     
                                 
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                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                         
                         ) 
                       
                       ⁢ 
                       Vcc 
                     
                     + 
                     Voff 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
       FIG. 7B  shows an equivalent circuit of the Hall element  10  when the offset cancelling circuit  100  is switched to the second state. In the second state, the resistors R 3  and R 4  are at the high-voltage side (power supply voltage Vcc side) and the resistors R 1  and R 2  are at the low-voltage side (ground side). In this configuration, because of the voltage dependency of the resistors, the resistors R 3  and R 4  have values R 3 =r 3 +α and R 4 =r 4 +α, respectively, and similarly, the resistors R 1  and R 2  have values R 1 =r 1 −α and R 2 =r 2 −α, respectively. Therefore, the voltage V 2  stored in the capacitor C 2  is represented by the following equation (2). In this equation, the offset value which does not have the voltage dependency is represented as Voff, and the polarities are reversed from the first state because the second state is 90° rotated from the first state. 
     
       
         
           
             
               
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                     ] 
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
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                         ( 
                         
                           
                             
                               
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                       ⁢ 
                       Vcc 
                     
                     + 
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                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
       FIG. 7C  shows an equivalent circuit of the Hall element  10  when the offset cancelling circuit  100  is switched to the third state. In the third state, the resistors R 2  and R 4  are at the high-voltage side (power supply voltage Vcc side) and the resistors R 1  and R 3  are at the low-voltage side (ground side). In this configuration, because of the voltage dependency of the resistors, the resistors R 2  and R 4  have values R 2 =R 2 +α and R 4 =r 4 +α, respectively, and similarly, the resistors R 1  and R 3  have values R 1 =r 1 −α and R 3 =r 3 −α, respectively. Therefore, the voltage V 3  stored in the capacitor C 3  is represented by the following equation (3). In this equation, the offset value which does not have the voltage dependency is represented as Voff. 
     
       
         
           
             
               
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                     ] 
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     V 
                     ⁢ 
                     
                         
                     
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                   = 
                   
                     
                       
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                                 ⁢ 
                                 
                                     
                                 
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                                 ⁢ 
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                               + 
                               
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                                 2 
                               
                             
                           
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                               - 
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                       ⁢ 
                       Vcc 
                     
                     + 
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                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
       FIG. 7D  shows an equivalent circuit of the Hall element  10  when the offset cancelling circuit  100  is switched to the fourth state. In the fourth state, the resistors R 1  and R 2  are at the high-voltage side (power supply voltage Vcc side) and the resistors R 3  and R 4  are at the low-voltage side (ground side). In this configuration, because of the voltage dependency of the resistors, the resistors R 1  and R 2  have values R 1 =r 1 +α and R 2 =r 2 +α, respectively, and similarly, the resistors R 3  and R 4  have values R 3 =r 3 −α and R 4 =r 4 −α, respectively. Therefore, the voltage V 4  stored in the capacitor C 4  is represented by the following equation (4). In this equation, the offset value which does not have voltage dependency is represented by Voff, and the polarities are reversed because the state is a state rotated from the third state by 90°. 
     
       
         
           
             
               
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       4 
                     
                     ] 
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   
                     V 
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                     ⁢ 
                     4 
                   
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                       ⁢ 
                       Vcc 
                     
                     - 
                     Voff 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Thus, a voltage Vout resulting from adding and averaging the voltages V 1 ˜V 4  is represented by the following equation (5). In the voltage Vout, the variable a representing the voltage dependency of the offset value of the output voltage of the Hall element  10  and the voltage Voff are cancelled. 
     
       
         
           
             
               
                 
                   
                     [ 
                     
                       Equation 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       5 
                     
                     ] 
                   
                   ⁢ 
                   
                       
                   
                 
               
               
                 
                     
                 
               
             
             
               
                 
                   Vout 
                   = 
                   
                     
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                             + 
                             
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                               4 
                             
                           
                         
                         - 
                         
                           
                             
                               r 
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                               ⁢ 
                               3 
                             
                             - 
                             
                               r 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                           
                             
                               r 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             + 
                             
                               r 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                           
                         
                       
                       ) 
                     
                     ⁢ 
                     Vcc 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     As described, according to the offset cancelling circuit  100  of the present embodiment, the offset value in the output voltage of the Hall element  10  can be suitably cancelled. In other words, the offset value which has the voltage dependency and the offset value which does not have the voltage dependency can both be cancelled.