Abstract:
A semiconductor memory device includes in its chip a decoder circuit which receives external selection signals for selecting a memory chip. The decoder circuit performs the selection of the memory chip in accordance with a logic corresponding to the combination of the external selection signals. The selection logic can be changed by the user of the semiconductor device.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which provides chip selection means. The semiconductor memory device of the present invention is in the form of a ROM, an EPROM, a PROM, an EAROM or a RAM. 
     In the system which uses a plurality of memory chips, it is necessary to select the desired memory chip by means of address signal supplied to the system. 
     In the prior art systems illustrated in FIGS. 1A and 1B, each of the chips CH-1, CH-2, CH-3 and CH-4 provides a chip selection terminal CS or chip selection terminals CS 1  (CS 1 ) and CS 2  (CS 2 ). The chips of FIG. 1B are of the Mask ROM type. The chip selection logic is determined in the wafer processing stage. The chip selection signal SEL which occupies the higher bit portions of the address signal ADR is supplied to the external decoder circuit in FIG. 1A and the chip selection terminals CS 1  (CS 1 ) and CS 2  (CS 2 ) in FIG. 1B. 
     The disadvantage of the prior art system of FIG. 1A is that an external decoder circuit DEC is required to generate from signal SEL the signals to select the desired chip. 
     The disadvantage of the prior art system of FIG. 1B is that it is impossible to change the select condition of the signals applied to the chip selection terminals CS 1  (CS 1 ) and CS 2  (CS 2 ), once they are selected at wafer processing. 
     The present invention eliminates the disadvantages in the prior art semiconductor memory systems described above. 
     SUMMARY OF THE INVENTION 
     The present invention presents a semiconductor memory device in which a memory chip is selected out in accordance with the logic of external selection signals. The semiconductor memory device is characterized by a decoder circuit on the memory chip for receving the external selection signals for selecting a memory chip. The decoder circuit selects a memory chip in accordance with a logic corresponding to the combination of external selection signals. The selected combination can be changed by the user of the semiconductor memory device. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1A and 1B illustrate prior art semiconductor memory device chip selection systems, 
     FIG. 2 illustrates a semiconductor memory device embodying the present invention, 
     FIGS. 3A and 3B illustrate the control circuits used in the device of FIG. 2, and, 
     FIG. 4 is a table indicating a manner of cell selection in the device of FIG. 2. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A semiconductor memory device embodying the present invention is illustrated in FIG. 2. The semiconductor memory device of FIG. 2 is an EPROM type. The control circuits 7 and 8 for producing the chip selection signals S 1 , S 1 , S 2  and S 2  are illustrated in FIGS. 3A and 3B. These signals are applied to the gates of the double gate FAMOS FETs 312, 313, 314 and 315 in the device of FIG. 2. 
     Control circuit 7 of FIG. 3A comprises depletion type load FETs 101, 103 and 105 connected to a voltage source V cc  (e.g., 5 volts), and enhancement type driver FETs 102, 104 and 106, a depletion type FET 107, an enhancement type FET 108, a depletion type FET 109, an enhancement type FET 110 connected to a voltage source V pp  (e.g. 25 volt). 
     The structure of control circuit 8 of FIG. 3B is identical to that of the control circuit 7 of FIG. 3A. 
     In the writing-in mode, the potential of the signal PRG is HIGH (e.g. 25 volts) and the potential of the signal PRG is LOW (0 volt). Accordingly, the potentials of the signals S 1  and S 1  are HIGH or LOW in accordance with the potential of the signal SEL 1 . The HIGH potential of the signals S 1  and S 1  is equal to the HIGH potential of the signal PRG (e.g. 25 volts), minus the threshold voltage of the FET 108 or FET 110. The LOW potential of the signals S 1  and S 1  is zero volt. In the chip-selection mode, the potential of the signal PRG is LOW (0 volt) and the potential of the signal PRG is HIGH (e.g. 5 volts). Accordingly, the potentials of the signals S 1  and S 1  are HIGH (e.g. 5 volts) or low (0 volt) in accordance with the potential of the signal SEL 1 . 
     The semiconductor memory device of FIG. 2 comprises a NOR gate circuit portion 6, an inverter circuit portion 5, an output buffer portion 4, a sense circuit 3, a column gate 2 and memory Cells No. 1. The NOR gate circuit portion 6 comprises double gate FAMOS type FEts 312, 313, 314 and 315, an FET 311, an FET 323 and an FET 316. 
     The inverter circuit portion 5 comprises FETs 317 and 318. The output buffer portion 4 comprises FETs 319, 320, 321 and 322. The output signal S l  of the inverter circuit portion 5 is applied to an input terminal of the output buffer portion 4. 
     In the NOR gate circuit portion 6, the drains of the FETs 312, 313, 314 and 315 are series connected to the voltage sources V cc  through FETs 323 and 311, and to voltage source V pp  through FET 316. In the writing-in mode, the potential of the signal PRG is HIGH (e.g. 25 volts) and the potential of the signal PRG is LOW (0 volt). In the chip selection mode, the potential of the signal PRG is LOW (0 volt) and the potential of the signal PRG is HIGH (e.g. 5 volts). The writing-in of the chip selection logic is usually carried out simultaneously with the writing-in of the information to the memory. The potentials of the signals SEL 1  and SEL 2  are set so that when in the chip selection mode, the memory cell in question is selected when the signals SEL 1  and SEL 2  assume potentials. The potentials applied during the writing-in mode of the signals SEL 1  and SEL 2  must be filed constant while the writing-in of the information into the memory is carried out. 
     A HIGH potential of a signal SEL 1  and the LOW potential of the signal SEL 2  are used to realize the chip selection logic in which the memory chip 1 is selected by the high potential of SEL 1  signal and the LOW potential of SEL 2  signal. When this condition occurs in the writing-in mode, the potential of the signals PRG becomes HIGH (e.g. 25 volts) and the potential of the signal PRG becomes LOW (0 volt). Accordingly, the potentials of the signals S 1  and S 2  become HIGH, that is 25 volts minus the threshold voltage of the FET 110 or FET 208. Also, the potentials of the signals S 1  and S 2  become LOW (0 volt). Electrons are injected into the floating gates of the FETs 312 and 315, in accordance with the well-known operative characteristics of the floating gate type EPROM, due to the application of a HIGH (approximately 20 volts) voltage to the drains of the FETs whose gate potentials are HIGH. As a result, the threshold voltages of FETs 312 and 315 are caused to shift to a positive value of, for example, 8 volts. No electrons are injected into the floating gates of the FETs 313 and 314 whose gate potentials are LOW. Therefore, the threshold voltages of the FETs 313 and 314 are unchanged and are remain at the original value of, for example, 2 volts. 
     After a chip selection logic is written into the NOR gate circuit portion 6 with the aid of control circuits 7 and 8 of FIGS. 3A and 3B, the data stored in the Cells No. 1 is read out as the output signal S out  at the output terminal of the output buffer circuit 4 only when the predetermined levels of SEL 1  and SEL 2  are applied to the gates of FETs 102 and 202. When the potential of the signal SEL 1  is HIGH and the potential of the signal SEL 2  is LOW, the potentials of the signals S 1  and S 2  are HIGH (e.g. 5 volts) and the potentials of the signals S 1  and S 2  are LOW (0 volt), and all of the FETs 312, 313, 314 and 315 are brought to the cut-off state, because the thread voltages of the FETs 312 and 315 are higher than the HIGH applied gate potential (e.g. 5 volts). Thus, the potential of the signal S l  is LOW (0 volt), and both FET 319 and FET 320 are brought to the cut-off state. Accordingly, the output signal S out  which corresponds to the information stored in the memory cells 1 is obtained. 
     When the potential condition of the signals SEL 1  and SEL 2  is other than the above assumed condition, at least one of the potentials of the signals S 1  and S 2  is HIGH (e.g. 5 volts), and at least one of the FETs 313 314 is in the ON state. Thus, the potential of the signal S l  is HIGH (e.g. 5 volts), and FETs 319 and 320 are in the ON state and the FETs 321 and 322 are in the cut-off state. Accordingly, no output signal S out  is obtained. 
     Similarly, the chip selection logic will be written into the chips so that the Cells No. 2 are selected under the condition that both the selection signals SEL 1  and SEL 2  are in HIGH state, the Cells No. 3 are selected under the condition that both the selection signals SEL 1  and SEL 2  are in LOW state, and the Cells No. 4 are selected under the condition that the selection signal SEL 1  is in LOW state and the selection signal SEL 2  is in HIGH state. The manner of cell selection described above is tabulated in FIG. 4. 
     Thus, if the chip selection logic has been stored in the device of FIG. 2, the data in the memory cells in question can be read out by applying the signals SEL 1  and SEL 2  which correspond to the higher bit portions of the address signal, without providing external decoder circuits. 
     The erasure of the chip selection logic stored in the device of FIG. 2 is carried out by means of, for example, the irradiation of the ultra-violet ray, simultaneously with the erasure of the data stored in the memory cells. In this case, electrons stored in the floating gates in the FAMOS type FETs 312 through 315 are eliminated by the ultra-violet irradiation. Therefore, it is possible to set a new logic state of the FETs of the NOR gate circuit portion 6 when data is next written into the Cells Nos. 1 through 4. Thus, changing the active logic state of the FETs of the NOR gate circuit portion 6 is possible. 
     If it is desired that one of the Cells Nos. 1 through 4 is always selected, as in the case of the so-called &#34;DON&#39;T CARE&#34; selection, such selection can be achieved by bringing all of the FETs 312, 313, 314 and 315 to the inoperative state by effecting the writing-in twice with a HIGH and a LOW level signal applied at the SEL 1  and SEL 2  terminals.