Abstract:
A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and outputs a signal at a node. The second inverter receives a second input signal and outputs an inverted second input signal at the same node. The current source provides current to the node via a first switch, the first switch receiving an input at a first input where the voltage output swing at the node is larger than a power supply voltage applied to the current source.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of and claims the priority of U.S. Non-Provisional Application No. 13/408,196, which was filed on Feb. 29, 2012 and which is incorporated herein in its entirety. 
     
    
     TECHNICAL FIELD  
       [0002]    Aspects of the present disclosure relate in general to electronic circuitry. In particular, aspects of the disclosure include a Voltage Mode Driver with Current Booster (VMDCB) able to achieve a larger voltage output swing than its supply voltage. 
       BACKGROUND 
       [0003]    The output swing of a conventional Voltage Mode Driver (VMD) structure is limited by the power supply of the circuit. For example, a circuit with a one volt (1 V) power supply can produce a one volt differential peak-to-peak (1 V DIFFPP ) swing. 
         [0004]    However, as semiconductor fabrication processes shrink device sizes smaller and smaller, the supply voltage is typically decreased as well. Consequently, it is difficult to achieve 1 V DIFFPP  when supply voltage is less than 1V. 
         [0005]    There are several approaches used in the prior art to address this issue. 
         [0006]    One approach is to raise the supply voltage. However, raising the supply voltage to overdrive a device often results in a device reliability issue. 
         [0007]    Another approach is to adjust the termination to produce a large divided voltage on the receiver side. However, such a change would cause an impedance mismatch, and result in poor signal integrity. 
         [0008]    A conventional (PRIOR ART) voltage mode driver (VMD) system  1000  is shown in  FIG. 1 . Voltage Mode Driver  1100  comprises a pair of p-type transistors  1102 ,  1106  coupled to n-type transistors  1104 ,  1108 , driving positive output node TXP and negative output node TXN via a supply voltage AVTTR, respectively. The receiver nodes (positive reception node RXP and negative reception node RXN) are modeled as capacitors  1202 ,  1206  serially connected to resistors  1204 ,  1208 . Assuming the termination is 50 ohms, the receiver&#39;s signal amplitude will be AVTTR/ 4 . For example, 1V of AVTTR can produce 0.25V amplitude-which is 1V of V DIFFPP  swing. 
         [0009]    However, as semiconductor processes shrink, supply voltage sizes are also shrunk. In current state of the art processes, the supply voltage is often below 1V. Consequently, it is difficult to achieve 1V V DIFFPP . 
         [0010]    When the supply voltages are raised to obtain a higher V DIFFPP  output swing, the device reliability is a concern, as the transistors are overstressed. 
       SUMMARY 
       [0011]    A voltage mode driver circuit is able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and output a signal at a node. The second inverter receives a second input, and outputs at the same output node. The current source is serially coupled to the output node via a first switch, the first switch receiving an input at the first input. 
         [0012]    In another embodiment, a voltage mode driver circuit includes a first p-type transistor, a first n-type transistor, a first current source, and a second current source. The first p-type transistor has a first p-type gate, a first p-type source and a first p-type drain. The first p-type gate is connected to receive a first input; the first p-type source is connected to a power supply; the first p-type drain is serially coupled with an output node TXP via a first resistance. The first n-type transistor has a first n-type gate, a first n-type source and a first n-type drain. The first n-type gate is connected to receive the first input. The first n-type source is connected to ground. The first n-type drain is serially coupled with the output node TXP via a second resistance. The first current source is serially coupled between the power supply and the node TXP via a first switch. The second current source is serially coupled between ground and to the node TXP via a second switch. 
     
    
     
       DESCRIPTION OF THE DRAWINGS 
         [0013]      FIG. 1  depicts a conventional Voltage Mode Driver (VMD) structure of the PRIOR ART. 
           [0014]      FIG. 2  describes a model of Voltage Mode Driver with Current Booster (VMDCB) circuit. 
           [0015]      FIG. 3  is the embodiment of a Voltage Mode Driver with Current Booster (VMDCB). 
           [0016]      FIGS. 4A and 4B  are example use scenarios of a Voltage Mode Driver with Current Booster embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    One aspect of the present disclosure includes a voltage mode driver with a current source to boost output swing. Impedance matching with output receivers may be accomplished through the use of high-resistance current sources. 
         [0018]    In another aspect, the control is synchronized between the voltage mode driver and current source, ignoring any resulting skew. 
         [0019]    Embodiments overcome a lower output voltage swing, and overcome the lower output swing due to headroom decrease in advanced semiconductor processes. This results in lower power consumption and a smaller die-size area. 
         [0020]    In embodiments of the current disclosure, the output voltage swing is somewhat independent of the supply voltage, and instead may be adjusted by the current ratio of parallel current sources. 
         [0021]    Embodiments are compatible with any semiconductor process and lower supply voltages. Embodiments with proper impedance matching may result in good output signal integrity, and are more reliable than the prior art. 
         [0022]    The following embodiments are described in a plurality of sections. Further, circuit elements making up each of functional blocks of the following embodiments are formed on a semiconductor substrate made of a single crystal silicon by use of the known integrated circuit (IC) technology for Complementary Metal Oxide Semiconductors (CMOS) transistors. With the present embodiments, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated to MOS transistor) is used as an example of a Metal Insulator Semiconductor Field Effect Transistor (MISFET). However, a non-oxide film is not precluded as a gate insulating film. In the drawings, a symbol O is affixed to a p-channel MOS transistor (PMOS transistor or “p-type” transistor) to be thereby differentiated from an n-channel MOS transistor (NMOS transistor or “p-type” transistor). Further, in the drawings, connection of a substrate potential of a MOS transistor is not specifically shown, however, there is no particular limitation to a connection method thereof if the MOS transistor is present in a normally operable range. 
         [0023]    Embodiments of the invention will be described hereinafter with reference to the drawings. In all the drawings for use describing the embodiments, identical members are in principle denoted by like reference numerals, thereby omitting detailed description thereof. 
         [0024]    Let us now turn to an embodiment of a voltage mode divider circuit  2000 , shown in  FIG. 2 .  FIG. 2  illustrates an embodiment of a Voltage Mode Driver with current booster  2100 , constructed and operative in accordance with an embodiment of the current disclosure. As shown in  FIG. 2 , Voltage Mode Driver  2100  drives positive output node TXP and negative output node TXN via a supply voltage AVTTR. The receiver nodes (positive reception node RXP and negative reception node RXN) are modeled as capacitors  2202 ,  2206  serially connected to resistors  2204 ,  2208 . 
         [0025]    Voltage Mode Driver  2100  comprises two paths for generating the positive and negative output nodes. We shall refer to these nodes as positive output node TXP and negative output node TXN. 
         [0026]    The voltage of positive output node TXP is governed by an inverter with p-type transistor  2102  coupled through resistors to n-type transistor  2104 . In parallel to this pair of transistors are current sources  2110   a - b  linked with switches  2112   a - b . Node TXP may driven by a power source (labeled AVTTR) serially connected with current source I P    2110   a  and switch  2112   a,  current source I P    2110   a  and switch  2112   a  connected to ground, and power source AVTTR serially connected with current source I N    2114   a  and switch  2116   a.    
         [0027]    Similarly, the voltage of negative output node TXN is governed by an inverter with p-type transistor  2106  coupled to n-type transistor  2108 ; this transistor pair is further driven by a voltage source linked current source I N    2114   b  and switch  2116   b  connected to ground. It is understood by those known in the art that transistors  2106  and  2108  receive an opposite signal from transistors  2102  and  2104 . 
         [0028]    In this embodiment, current sources I P    2110   a - b  and I N    2114   a - b  are controllable and may adjust to power supply AVTTR voltage changes. Control of switches  2112   a - b ,  2216   a - b  is synchronous with Voltage Mode Divider&#39;s  2100  input signal. It is understood by those practicing the art that switches  2112   a - b ,  2216   a - b  may be metal-oxide-semiconductor (MOS) switches or any other switches known in the art. 
         [0029]    Resisters may be used for impedance matching. In  FIG. 2 , 50 ohm terminations are shown for each output terminal. 
         [0030]    Moving to  FIG. 3 , an alternate embodiment of a Voltage Mode Driver with Current Booster is depicted, constructed and operative in accordance with an embodiment of the current disclosure. In this second embodiment, Voltage Mode Driver  3000  has a single positive output node TXP, and receives opposite inputs SMAINB and SPOSIB; Voltage Mode Driver  3000  is further powered by voltage supply AVDD. The inputs SMAIN and SMAINB are received from a previous buffer chain. Voltage Mode Driver  3000  comprises a pair of impedance matched inverters  3100   a - b , in parallel with switched current sources IMAIN  3200  and IPOS  3100 . 
         [0031]    Inverter  3100   a  receives input SMAINB, while inverter  3100   b  receives input SPOSIB. Each inverter  3100  comprises a p-type transistor  3102  coupled to n-type transistor  3104  powered by voltage source AVDD. The gates of each transistor  3102  are connected with the appropriate input, as shown in  FIG. 3 . The inverter output TXP is impedance matched (using a resistance R) with an expected receiver. 
         [0032]    In addition to the two parallel inverters, TXP is driven with a pair of switched current sources IMAIN  3200  and IPOS  3300 . Current sources IMAIN  3200  and IPOS  3100  are used to either “pull-up” or “pull-down” the output voltage. 
         [0033]    IMAIN  3200  comprises two current sources Imain  3202   a - b  controlled by switches  3204   3206 . Switches  3204   3206  receives input from signal SMAINB. Switch  3204  may be a p-type transistor, while switch  3206  may be an n-type transistor. 
         [0034]    Similarly, IPOS  3300  comprises two current sources Ipos  3302   a - b  controlled by switches  3304   3306 . Switches  3304   3306  receives input from signal SPOSIB. Switch  3304  may be a p-type transistor, while switch  3306  may be an n-type transistor. 
         [0035]    Operation of a Voltage Mode Driver with Current Booster  3000  is better understood thorough  FIGS. 4A and 4B , constructed and operative in accordance with an embodiment of the current disclosure.  FIGS. 4A and 4B  are use scenarios of a Voltage Mode Driver with Current Booster  3000  embodiment. It is understood by those familiar with the art that the voltage supply, resistance, current supply and other values may be adjusted or changed to fit any particular application. The values of these circuit elements are used for illustrative purposes only to explain a functional operation of such an embodiment. 
         [0036]    Turning to  FIG. 4A ,  FIG. 4A  is an example of achieving a 1 V DIFFPP  when the supply voltage is less than 1V, constructed and operative in accordance with an embodiment of the current disclosure. In this example, power supply AVDD is 0.9V, and the receiver is modeled as a capacitor in series with a 50 ohm resistance. 
         [0037]    To achieve a 1V peak-to-peak voltage swing, the receiver pad should produce a voltage swing of half of the voltage supply +/− 0.25V. Thus, for a power supply AVDD of 0.9V, the TXP voltage would be 0.7V (0.9V/2+0.25V=0.7V). 
         [0038]    The current from inverts  3100   a  and  3100   b  can be adjusted through setting the appropriate resistance of resistors R 1  and R 2 . In this example, resistor R 1  is 60 ohms, while R 2  is 300 ohms, respectively. Current from inverter  3100   a  can therefore be calculated as 3.33 mA (0.9V−0.7V/60 ohms), while current from inverter  3100   b  is 0.66 mA (0.9V−0.7V/300 ohms). 
         [0039]    Current sources IMAIN  3200  and IPOS  3300  are sized such that their total current output is 1 mA. In this embodiment, IMAIN  3200  is 0.85 mA, while IPOS  3300  is 0.15 mA. 
         [0040]    The total driving current from the two inverters and power supplies is therefore 5 mA. The total driving current of 5 mA results in a 1V peak-to-peak voltage swing, even though the voltage supply is 0.9V. 
         [0041]    In another embodiment,  FIG. 4B  is an example of achieving a −3.5 dB voltage level swing when the supply voltage is less than 1V, constructed and operative in accordance with an embodiment of the current disclosure. In this example, power supply AVDD is 0.9V, and the receiver is modeled as a capacitor in series with a 50 ohm resistance. 
         [0042]    To achieve a −3.5 dB voltage level swing, the receiver pad should produce a voltage swing of half of the voltage supply +/−0.167V. Thus, for a power supply AVDD of 0.9V, the TXP voltage would be 0.617V (0.9V/2+0.167V=0.617V). 
         [0043]    The current from inverts  3100   a  and  3100   b  can be adjusted through setting the appropriate resistance of resistors R 1  and R 2 . Like the previous example, resistor R 1  is 60 ohms, while R 2  is 300 ohms, respectively. Current from inverter  3100   a  can therefore be calculated as 4.716 mA (0.9V−0.617V/60 ohms), while current from inverter  3100   b  is 2.056 mA (0.9V−0.617V/300 ohms). 
         [0044]    Again, current sources IMAIN  3200  and IPOS  3300  are sized such that their total current output is 1 mA. In this embodiment, IMAIN  3200  is 0.85 mA, while IPOS  3300  is 0.15 mA. 
         [0045]    The total driving current from the two inverters and power supplies is therefore 3.36 mA. The total driving current of 3.36 mA results in a −3.5 dB voltage level swing, even though the voltage supply is 0.9V. 
         [0046]    The previous description of the embodiments is provided to enable any person skilled in the art to practice the invention. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Thus, the current disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.