Abstract:
In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain; and addressing circuits to address the MRAM cells.

Description:
[0001]    This application claims the benefit of priority to U.S. Provisional Patent Application No. 61/419,403 filed Dec. 03, 2010, the entire specification of which is incorporated herein by reference. 
     
    
     FIELD 
       [0002]    Embodiments of the invention relate to MRAM (Magnetic Random Access Memory) semiconductor devices. 
       BACKGROUND 
       [0003]    A FIMS (Field Induced Magnetic Switching) MRAM cell comprises a MTJ (Magnetic Tunnel Junction) in the form of a stacked memory element, a bit line (BL) metal running on the MTJ in a first direction, a write word line (WWL) running under the MTJ in a second direction crossing the first direction, a read word line (RWL) as a select gate running in the second direction and a read metal wire connecting the MTJ to a selected device. The MTJ is connected to the BL. An insulation layer is disposed between the MTJ and the WWL to prevent current flow through the MTJ during a write operation. 
         [0004]    The MTJ is a stack comprising a pinned layer with fixed magnetism, a tunnel layer and a free layer. Two orthogonal currents carried by the write word line and the bit line manipulate magnetic fields in the free layer. When the direction of the free layer field coincides with that of the pinned layer, tunnel resistance of the MTJ becomes low. When the direction is opposite, the resistance becomes high. A memory high or low state is defined as high or low resistance of the MTJ element. A read word line (RWL) selects a column to be read. 
         [0005]    There are two word lines, RWL and WWL, in a unit cell. The RWL or WWL play no role during “write” or “read” operations. Thus, having a RWL and a WWL is not only inefficient but also limits the miniaturization of a memory cell. WWL is patterned in the second or upper metals. A metal stud to connect the read metal is also formed at the WWL metal level. There are two sets of metal and space along bit line direction, and one set along the word line direction. Since the MTJ should be within widths of BL and WWL, overlay margin is added to widths of BL and WWL. Minimum feature size of 2 nd  or upper metal width is 1.5 to 2 times larger than gate width. The unit cell area becomes 30 to 40 F 2 , where F is minimum feature size of its technology. 
         [0006]    Another serious issue with the conventional MRAM cell is that the write current to switch a vector of free layer is not scaled down with miniaturization. Thus, the problem of electro migration arises from high current density, 
       SUMMARY 
       [0007]    According to a first aspect of the invention, there is provided a magnetic random access (MRAM) cell, comprising: a magnetic bit; and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain. 
         [0008]    According to a second aspect of the invention, there is provided a magnetic random access (MRAM) device, comprising: a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and write conductors defined by conductors patterned in a second metal layer above the magnetic bit; and a gate formed below the magnetic bit between a source and a drain; and addressing circuits to address the MRAM cells. 
         [0009]    According to a third aspect of the invention, there is provided a method for operating a magnetic random access (MRAM) device, the method comprising: selecting a MRAM cell for writing to; and writing to the selected MRAM cell by passing a write current through a gate between a source and a drain below the MRAM cell. 
         [0010]    Other aspects of the invention will become apparent from the written description below. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a cross-sectional representation of base line structure, depicting an MRAM cell in accordance with the prior art. 
           [0012]      FIGS. 1.1  to  1 . 7  illustrate various process steps in the manufacturing of the base line structure of  FIG. 1 . 
           [0013]      FIG. 2  is a cross-sectional representation of metal gate MRAM in accordance with one embodiment of the invention. 
           [0014]      FIGS. 2.1  to  2 . 3  illustrate various process steps in the manufacturing of the metal gate MRAM of  FIG. 2 . 
           [0015]      FIG. 3  is a cross-sectional representation of an MRAM array architecture with a thin local metal structure, in accordance with one embodiment of the invention. 
           [0016]      FIG. 3.1  is an electrical diagram for the MRAM array architecture of  FIG. 3 . 
           [0017]      FIGS. 3.2  to  3 . 9  illustrate various process steps in manufacturing the MRAM array architecture of  FIG. 3 . 
           [0018]      FIG. 4  is a cross-sectional representation of an MRAM array with a PIN diode structure, in accordance with one embodiment of the invention. 
           [0019]      FIG. 4.1  is an electrical diagram for the MRAM array with a PIN diode structure shown in  FIG. 4 . 
           [0020]      FIGS. 4.2  to  4 . 7  illustrates various process steps to fabricate the MRAM array with a PIN diode structure shown in  FIG. 4 . 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. 
         [0022]    Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments. 
         [0023]    Broadly, embodiments of the present invention disclose a MRAM device in which the write conductors used for write operations are defined by metal conductors in a second metal layer (M 2 ) and metal gates of each memory cell. This obviates the need for defining write conductors using second and third metal layers and results in a more compact MRAM array. 
         [0024]      FIG. 1  shows a cross-section through a base line structure that is defined by a conventional MRAM cell architecture.  FIGS. 1.1  to  1 . 7  illustrate various process steps in the manufacturing of the base line structure of  FIG. 1 . 
         [0025]    As shown in  FIG. 1.1 , STI (shallow trench isolation)  101  is formed in silicon substrate  100  with a conventional process. An active area array bounded by STI runs straightly along a first direction to define a cell area. The edges are also isolated by STI. Conventional MOS gate consisting of gate oxide  102  and gate electrode  103  is placed along a second direction across the active area array as shown in  FIG. 1.2 . Source and drain species are implanted to form source and drain regions  104  shown in  FIG. 1.3  with conventional CMOS process followed by activation anneal and silicidation process. Dielectric is deposited and planerized by CMP (chemical mechanical polish). Contact studs  105  are placed on the source and drain regions as shown in  FIG. 1.3  by using conventional lithography, etch, tungsten deposition and CMP process. At first metal step as shown in  FIG. 1.4 , source contact studs are connected to first metal line  107  to make them a common source line. Metal pillars  106  are stacked on each bit (drain) contact to extend to a MTJ memory unit (yet to be formed). 
         [0026]    A pillar  108  of via 1 and second metal is also stacked on the bit stack as shown in  FIG. 1.5 . A WWL(write word line)  109  is patterned at a second metal level. The pillar  108  and WWL  109  are patterned by conventional damascene process and planerized, followed by a dielectric film deposition. The dielectric film may be thinner than 100 nm. Read metal  110  and MTJ film stack are deposited subsequently. The MTJ and read metal stack film is patterned with a two mask step. The first mask corresponds to the rectangular pattern  110  of the read metal. The MTJ and read metal stack is etched with the first mask. A second mask is applied along a second direction across the rectangular shape array. The etching with second mask is stopped at the read metal surface to make each MTJ cell  111 . Dielectric film is deposited and each via is opened over each MTJ cell  111 . BL metal is deposited and BL  112  is patterned along a first direction as shown in  FIG. 112 . A pad metal process is then performed to complete the wafer process. 
         [0027]      FIG. 2  is a cross-sectional representation of metal gate MRAM in accordance with one embodiment of the invention.  FIGS. 2.1  to  2 . 3  illustrate various process steps in the manufacturing of the metal gate MRAM of  FIG. 2 . 
         [0028]    With the metal gate MRAM shown in  FIG. 2 , the read gate electrode works also as a write word line. The MTJ memory cell is placed right over the read gate electrode. The structure over the MTJ is same as that of base line structure describe above. Since a large current is required for the write word line, the resistance should be low. Thus, a metal gate is preferred. 
         [0029]    Up to the gate process, the fabrication method is same as with the base line structure. The gate electrode  203  in  FIG. 2.1  comprise a metal, in one embodiment. The common source  205  in  FIG. 2.2  is formed by using a local wire process. The read lead metal  210  and MTJ  211  is patterned right over the gate as shown in  FIG. 2.3 . 
         [0030]      FIG. 3  is a cross-sectional representation of an MRAM array architecture with a thin local metal structure, in accordance with one embodiment of the invention.  FIG. 3.1  is an electrical diagram for the MRAM array architecture of  FIG. 3 . 
         [0031]    The thin local metal is used for the write word line to increase current density. A Global Write Word Line (GWWL) runs along a first direction, parallel to the Bit Line. A Local Write Word Line (LWWL) is split into two ways from the GWWR in a second direction. The LWWR runs under 8 or 16 cells per side. The LWWR is connected a write transistor. 
         [0032]    The STI  301  and active area  300  in  FIG. 3.2  has the same structure as with base line structure of  FIG. 1 . Two memory cells can fit between the STI along the first direction. A write gate  304  is added between two read gates  303  as shown in  FIG. 3.3 , followed by conventional source and drain process, silicidation process, and contact process. Contact stud  305  is placed on every bit as in  FIG. 3.4 . The contact stud on drain side of read gate is extended by Metal  1  pillar  307  to connect read metal. Contact stud on both sides of the word gate is connected by first metal  306  as shown in  FIG. 3.5 . The first metal line  306  is connected LWWL  308  in  FIG. 3.6 . Read bit stack is extended by pillar  309 . The read metal  310  and MTJ  311  in  FIG. 3.7  are patterned in the same way as base line structure. BL metal  312  connects the MTJ along 1st direction as shown in  FIG. 3.8 . GWWL  313  stitches every other LWWL along the first direction as shown in  FIG. 3.9 . 
         [0033]      FIG. 4  is a cross-sectional representation of an MRAM array with a PIN diode structure, in accordance with one embodiment of the invention.  FIG. 4.1  is an electrical diagram for the MRAM array with a PIN diode structure shown in  FIG. 4 .  FIGS. 4.2  to  4 . 7  illustrates various process steps to fabricate the MRAM array with a PIN diode structure shown in  FIG. 4 . In the embodiment of  FIG. 4 , there is a “PIN” diode under the MTJ as can be seen. A read transistor attached to eache MTJ cell is not necessary any more. The structure can miniaturize the unit cell area drastically. LWWL is split into two ways from GWWL. Pillar PIN diode is patterned on the LWWL and MTJ is patterned on PIN. LWWL is connected to bit diffusion at the end. 
         [0034]    As shown in  FIG. 4.2 , write transistor lines  401  are patterned to select write cell and flow write current. The contact stud  403  as shown in  FIG. 4.3  is formed to connect to LWWL. LWWL  404  is patterned as corm as in  FIG. 4.4 . PIN layers  405  and MTJ stack are  406  are deposited and patterned on the LWWL  404  as pillar as shown in  FIG. 4.5 . Bit line metal  407  connects MTJ along the first direction as in  FIG. 4.6 . LWWL is stitched by GWWL  408  as shown in  FIG. 4.7 . 
         [0035]    Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader spirit of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense.