Abstract:
A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.

Description:
TECHNICAL FIELD OF THE INVENTION 
     The present invention relates generally to memory devices and in a particular embodiment the present invention relates to non-volatile memory devices. 
     BACKGROUND OF THE INVENTION 
     Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. 
     A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation. 
     Each memory cell can be programmed as a single bit per cell (i.e., single level cell—SLC) or multiple bits per cell (i.e., multilevel cell—MLC). Each cell&#39;s threshold voltage (V t ) determines the data that is stored in the cell. For example, in a single bit per cell, a V t  of 0.5V can indicate a programmed cell while a V t  of −0.5V might indicate an erased cell. The multilevel cell may have multiple V t  ranges that each indicates a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage distribution for the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell. 
       FIG. 1  illustrates a typical prior art V t  distribution where the vertical axis is the quantity of cells and the horizontal axis is the threshold voltage V t . L0  101  is typically referred to as the erased state and has a negative voltage. The remaining positive states are labeled L1  102 , L2  103 , and L3  104  and are programmed from the erased state  101 . 
     As illustrated in  FIG. 2 , conventional MLC programming uses incrementally increasing (e.g., ΔV) programming pulses  201  that are applied to the access lines (e.g., word lines) of the memory cell array to achieve discrete levels of V t  for the cells in the array. Between each program pulse, a verify  203  is performed to determine if the cell&#39;s target V t  has been achieved. Memory cells that have reached their target V t  are inhibited from further programming during subsequent pulses by biasing of the data line (e.g., bit line). 
     The variations in each V t  distribution width  110  is an important parameter to control. The tightest possible distribution is desired, as shown in  FIG. 1 , in order to produce greater spacing  115  between each of the states. This enables easier discrimination between states since the possibility of a higher voltage of one distribution overlapping a lower V t  of the next distribution is reduced. A smaller programming voltage step (ΔV) produces a tighter distribution. However, the smaller programming voltage steps require a longer programming time. Thus, there is a trade-off between tighter distributions and programming speed. 
     Floating gate-to-floating gate capacitive coupling also affects distribution width. This coupling effect results from increasing density of a memory device by decreasing the distance between memory cells on the memory die. The decreased distance between cells increases the ability of each cell to affect the V t  distribution of adjacent cells. 
     Program disturb is yet another phenomenon that can affect the V t  distribution size. As mentioned earlier, memory cells that have achieved their target V t  are inhibited from further programming. However, additional programming pulses having high programming voltages necessary for further programming of higher states can still increase the threshold voltages of already programmed memory cells. The increased threshold voltages result in wider threshold distributions. 
     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce V t  distribution width and program disturb without impacting the programming throughput of the memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows typical prior art threshold voltage distribution diagram. 
         FIG. 2  shows a series of prior art program and verify pulses. 
         FIG. 3  shows schematic diagram of one embodiment of a non-volatile memory array. 
         FIG. 4  shows one embodiment of a threshold distribution in accordance with a first pass programming step. 
         FIG. 5  shows one embodiment of a threshold distribution in accordance with a second pass programming step. 
         FIG. 6  shows a comparison between first pass programming pulse incremented voltages and second pass programming pulse incremented voltages. 
         FIG. 7  shows a flowchart of one embodiment of a multi-pass programming method. 
         FIG. 8  shows a simplified block diagram of one embodiment of a memory system of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. 
       FIG. 3  illustrates a schematic diagram of a portion of a NAND architecture memory array comprising series strings of non-volatile memory cells on which the embodiments of the subsequently discussed data collection and compression/decompression can operate. While the subsequent discussions refer to a NAND memory device, the present embodiments are not limited to such an architecture but can be used in other memory device architectures as well. For example, alternate embodiment arrays could be organized in NOR or AND architectures. 
     The memory array is comprised of an array of non-volatile memory cells  301  (e.g., floating gate) arranged in columns such as series strings  304 ,  305 . Each of the cells  301  is coupled drain to source in each series string  304 ,  305 . A word line WL 0 -WL 31  that spans across multiple series strings  304 ,  305  is connected to the control gates of each memory cell in a row in order to bias the control gates of the memory cells in the row. The bit lines BL 1 , BL 2  are eventually connected to sense amplifiers (not shown) that detect the state of each cell by sensing current on a particular bit line. 
     Each series string  304 ,  305  of memory cells is coupled to a source line  306  by a source select gate transistor  316 ,  317  and to an individual bit line BL 1 , BL 2  by a drain select gate transistor  312 ,  313 . The source select gate transistors  316 ,  317  are controlled by a source select gate control line SG(S)  318  coupled to their control gates. The drain select gate transistors  312 ,  313  are controlled by a drain select gate control line SG(D)  314 . 
     Each memory cell can be programmed as a single level cell (SLC) or multilevel cell (MLC). Each cell&#39;s threshold voltage (V t ) is indicative of the data that is stored in the cell. For example, in an SLC, a V t  of 0.5V might indicate a programmed cell while a V t  of −0.5V might indicate an erased cell. The MLC has multiple V t  ranges that each indicate a different state. Multilevel cells can take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell. 
     The memory array can be organized as memory blocks. The quantity of memory blocks is typically determined by the size of the memory device (i.e., 512 MB, 1 GB). In one embodiment, each memory block programmed in an SLC manner is comprised of 64 pages. In another embodiment, a memory block programmed in a MLC manner is comprised of 128 pages. Each page is typically comprised of 2048 bytes of data. 
       FIG. 4  illustrates a threshold voltage distribution for three possible programmed states in a memory cell. These states are labeled L1, L2, and L3. L0 is considered the erased state and typically has a negative threshold voltage. The three states shown in  FIG. 4  are for illustration purposes only as alternate embodiments can have more or less than three programmed states. 
     The three programmed states L1-L3 are representative of digital data programmed into a memory cell. For example, L1 might represent a “01” pattern, L2 a “10” pattern, and L3 a “00” pattern. Alternate embodiments can use other digital patterns. Thus, to program a “01” to a memory cell, that particular cell&#39;s threshold voltage is moved from the erased state (e.g., “11”) having a negative threshold voltage to the threshold voltage at L1. This is accomplished using the programming embodiments described subsequently. 
     During the programming operation, the selected word line for the memory cell to be programmed is biased with a series of incrementing voltage programming pulses. The series of pulses start at an initial voltage that is greater than a predetermined programming voltage (e.g., 16V). After each programming pulse, a verification operation is performed to determine if the cell&#39;s threshold voltage V t  has increased to the target programmed level (e.g., 0.5V). In one embodiment, the verification operation uses a word line voltage of 0V on the selected word line. 
     During the programming operation, the unselected word lines for the remaining memory cells of the memory block being programmed are typically biased at a voltage (e.g., 10V) that is less than the programming voltage. In one embodiment, the unselected word line voltage can be any voltage above ground potential. Each of the memory cells is programmed in a substantially similar manner. 
     The bit line, during the programming operation, is biased at a low voltage such as ground. The higher the bit line voltage, the slower the programming of the memory cell. A voltage of V CC  on the bit line will inhibit programming of the memory cells coupled to that particular bit line. 
       FIG. 4  illustrates the first pass of a programming operation. The memory cells start at the L0 level (i.e., erased state of “11”). During the first pass, the memory cells are programmed to a pre-L1 or pre-L2 level. The first pass also programs the top-most level L3 to its target V t  without using a pre-L3 level. The first pass uses large ΔV increments between programming pulses. This concept is illustrated in  FIG. 6 . 
       FIG. 6  shows that during the first programming pass, the ΔV increment to the next programming pulse is greater than the ΔV used during the second programming pass. Thus, ΔV 1st pass &gt;ΔV 2nd pass . 
     The top-most level L3 does not require a pre-L3 programming level since it can tolerate a wider distribution than the lower levels. This is due to the fact that the top-most level does not have any remaining levels with which it can interfere. Thus, the L3 level can use only the larger ΔV and be programmed more quickly than the remaining cells. 
     In one embodiment, ΔV 1st pass  is optimized for programming L3. In other words, ΔV st pass is a voltage that programs L3 the most efficiently. This can be accomplished using empirical testing of different voltages during the manufacturing and testing process. This voltage is then used during the first pass for also programming the pre-L1 and pre-L2 levels. 
     In one embodiment, the starting voltage  601  of the programming operation, as illustrated in  FIG. 6 , is set conservatively. This reduces the chances of the memory cells being programmed to the L1 level from overshooting their target V t . 
     Programming speed is a function of the number of program/erase cycles that a memory cell has experienced. If the memory cells are uncycled, the first few programming pulses may not cause a V t  shift and are thus wasted. In the present programming method, the voltage at which the first pre-L1 cell passes the program verify operation is recorded. This voltage, or some offset of this voltage, can then be used as the starting voltage during the second programming pass. 
     During the first programming pass, once the pre-L1 level has been programmed, ΔV 1st pass  can be altered or increased to suit the needs of programming the pre-L2 level. Similarly, once the pre-L2 level has been programmed, ΔV 1st pass  can be altered or increased to suit the needs of programming the L2 level. 
     During the second programming pass, once the L1 level has been programmed, ΔV 2nd pass  can be altered or increased to suit the needs of programming L2. Altering the program step voltage after the pre-levels or programmed levels have been reached can be done with alternate embodiments having more than four levels of threshold voltages. 
       FIG. 5  illustrates the second pass of the programming operation. In the second programming pass, the starting voltage  602  as shown in  FIG. 6 , has been determined during the first programming pass as described previously. Also during the second programming pass, the ΔV is less in order to fine tune the movement of the pre-L1 or pre-L2 levels to the target L1 or target L2 levels. 
     The shift in the threshold voltages from the pre-L1 and pre-L2 levels is relatively small compared to the initial programming from the erased level to the pre-levels. Thus the floating gate-to-floating gate coupling aggression will also be relatively small. Also, the program disturb induced  501  on L3 while finishing the programming of either the L1 or the L2 levels is relatively small. 
     Reference is made to the programming pulses of  FIG. 6  while describing the programming method illustrated in the flowchart of  FIG. 7 . The method begins with an erase operation performed on the memory cell block comprising the target memory cells to be programmed  701 . In one embodiment, the erase operation is comprised of biasing the word lines to be erased with a large negative voltage pulse. An erase verify operation  703  is then performed. If the memory cell block is not erased, the erase pulses continue until the erase verify operation passes. 
     The first programming pass begins at the conservative programming voltage  601  and increases by ΔV 1st pass  for every subsequent programming pulse. Thus, the first pass programming pulse is generated  705  at the start voltage  601 . A program verify operation is then performed  707  to determine if the memory cell is programmed to the pre-level (e.g., pre-L1 or pre-L2) or the highest target level. If the program verify  707  fails, the memory cell has not yet reached the threshold voltage for either pre-level or the highest target level. The programming voltage is then increased by ΔV 1st pass    706 . This first pass programming operation  705 ,  706 ,  707  is performed until the memory cell reaches its pre-level threshold voltage or the highest target level. 
     If the program verify  707  passes, the second pass programming pulses are generated. The voltage for the first programming pulse  602  for the second pass is determined from the first programming pass as described previously. This programming pulse is then generated  709  only for the memory cells programmed to their pre-level since the target memory cell programmed to the highest target level is done programming. A program verify operation is performed to determine if the memory cell has reached its target program level  711 . If the memory cell has not reached the threshold voltage for this level, the programming pulse is increased by ΔV 2nd pass    710  and the second pass programming operation  709 ,  710 ,  711  is repeated until the memory cell being programmed reaches the target level. At this point, the programming operation has been completed  713 . 
       FIG. 8  illustrates a functional block diagram of a memory system  820  that includes a memory device  800 . The memory device  800  has been simplified to focus on features of the memory that are helpful in understanding the present embodiments for memory programming. The memory device  800  is coupled to an external system controller  810 . The controller  810  may be a microprocessor or some other type of control circuitry. 
     The memory device  800  includes an array  830  of non-volatile memory cells, such as the one illustrated in  FIG. 3  and discussed previously. The memory array  830  is arranged in banks of word line rows and bit line columns. In one embodiment, the columns of the memory array  830  are comprised of series strings of memory cells. As is well known in the art, the connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture. 
     Address buffer circuitry  840  is provided to latch address signals provided through the I/O circuitry  860 . Address signals are received and decoded by a row decoder  844  and a column decoder  846  to access the memory array  830 . It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array  830 . That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts. 
     The memory device  800  reads data in the memory array  830  by sensing voltage or current changes in the memory array columns using sense amplifier circuitry  850 . The sense amplifier circuitry  850 , in one embodiment, is coupled to read and latch a row of data from the memory array  830 . I/O circuitry  860  is included for bidirectional data communication as well as address communication over a plurality of data connections  862  with the controller  810 . Write circuitry  855  is provided to program data to the memory array  830 . 
     Memory control circuitry  870  decodes signals provided on control connections  872  from the controller  810 . These signals are used to control the operations on the memory array  830 , including data read, data write (program), and erase operations. The memory control circuitry  870  may be a state machine, a sequencer, or some other type of controller to generate the memory control signals. In one embodiment, the memory control circuitry  870  is configured to transfer data to the memory array  830  for execution of the programming embodiments discussed previously. The memory control circuitry  870  is further configured to read data from the memory array  830 . 
     The memory device illustrated in  FIG. 8  has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of flash memories are known to those skilled in the art. 
     CONCLUSION 
     In summary, one or more embodiments of the present invention provide a method for programming multilevel cell solid state memory devices in order to produce narrow V t  distributions and mitigate floating gate-to-floating gate coupling without impacting programming speed. This can be accomplished by programming, during a first programming pass, memory cells having lower target levels to a pre-level and memory cells having an upper level to its target level. A second programming pass programs the lower levels to their associated target levels. The first programming pass programs the memory cell at a faster program rate than the second programming pass due to the greater ΔV between the programming pulses in the first programming pass. 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.