Abstract:
An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.

Description:
FIELD OF THE INVENTION 
   The present invention relates to circuitry for reading the program state of eFuse circuits. 
   BACKGROUND 
     FIG. 1  illustrates the components of a typical eFuse cell. The “eFuse” or fuse  2  in the cell does not act as a typical fuse does by breaking the circuit if it carries too much current. Instead, the eFuse is made with poly-silicon or a similar type of material where the resistance of the fuse can change by allowing a certain amount of current to flow. A high current on the Vfs (“fuse voltage”) pad  16  will increase the resistance of the eFuse  2  from a low of about 300 Ohms to a high of about 1 Mega Ohm. 
   In addition to the eFuse  2 , the eFuse cell of  FIG. 1  includes thick oxide transistors  4 ,  6  and  8 , capable of having high voltages across their terminals. The thick oxide is illustrated by the “x” pattern drawn on the gate. Further, a PMOS transistor  10  and inverters  12  and  14  are formed with thin oxide devices, which operate at a lower, typical “core” or system voltage (e.g., 1.0v). The PMOS transistor  10  is illustrated by a gate circle, while NMOS devices  4 ,  6  and  8  have no gate circle. The Vfs pad  16  is a voltage supply pad shared by all fuses within an array of eFuse cells. The “fs” of “Vfs” stands for fuse to source voltage. 
   When programming the eFuse cell of  FIG. 1 , “Read” is held to a logic low or 0, and “Program,” is a logic high or 1. A high programming voltage, for example either 3.3 volts or 2.5 volts, is further applied to “Vfs.” Because “Read” is low and “Pgm” is high, transistors  4  and  8  are then turned off and transistor  6  is on. Current from “Vfs” flows through the node n 2 , “fuse,” node n 1 , and transistor  6  to ground. The current created, for example about 10 milliamps, changes the resistance of the fuse  2  from a low of about 300 Ohms to a high of about 1 Mega Ohm. (The main purpose of transistor  8  is to isolate, and therefore protect thin oxide devices from any high voltages on the programming path.) 
   During reading, “Read” is a logic 1 and “Pgm” is a logic 0. No voltage is supplied on the Vfs pad  16 . Thus, transistor  6  is turned off, and transistors  4  and  8  are on. Because the gate of transistor  10  is low, shown as ground, transistor  10  is also on. Thus, transistors  10 ,  8  and  4  and the fuse  2  in effect form a voltage divider whose output is node n 3 . Typically, transistors  4  and  8  are designed to be sufficiently strong and have a low impedance so that they do not have an effect on the voltage at node n 3 , leaving the eFuse device to control the voltage on node n 3 . 
   Thus, the voltage on node n 3  is a function of transistor  10  and the resistance of eFuse  2  only. For  FIG. 1 , when the “fuse” is un-programmed, having a low resistance of about 300 ohms, node n 3  is at a relatively low voltage, referenced as n 3 _min. When the eFuse  2  is programmed, having a high resistance, node n 3  is at a relatively high voltage, referenced as n 3 _max. Voltages n 3 _max and n 3 _min are between Vdd and ground. Inverter  12  is designed to have a trip point somewhere between n 3 _min and n 3 _max so that it, along with inverter  14 , can resolve the node n 3  voltage to logic 0 or 1 on the output, Data. For example, Data will be a logic 0 if the node n 3  voltage is at n 3 _min for an unprogrammed eFuse because n 3 _min is less than the inverter  12  trip point. 
   The 12 inverter trip point varies with process, voltage, and temperature (PVT). The n 3 _min to n 3 _max range also varies with PVT, as well as the difference between the un-programmed and programmed resistances of eFuse  2 . A disadvantage with having inverter  12  sense the n 3  node voltage is that its trip point varies independently of the n 3 _min to n 3 _max variation. For example, under some PVT condition it is possible for the n 3  min to n 3 _max range to shift up while the trip point of inverter  12  shifts down. If the trip point shifts below the n 3  voltage range, the Data output will always have a logic 1, regardless of the resistance of eFuse  2 . It would be desirable to accurately sense the state of the eFuse by having the sensing trip point track the n 3  node voltage variations across process, voltage and temperature. 
   SUMMARY 
   Embodiments of the present invention provide a circuit and process for sensing the state of the fuse in a reliable fashion irrespective of variations in process, voltage and temperature (PVT). 
   The eFuse sensing circuit according to embodiment of the present invention replaces the inverters of the conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the reference circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the reference circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations. 
   Circuitry is further provided in one embodiment for the comparator of the eFuse sensing circuit to provide for more accurate sensing. The comparator circuit includes cross coupled inverters with power supplied to the cross coupled inverters through transistors receiving an enable signal. The enable signal is applied to power the comparator when a reading of the eFuse state is desired, and the comparator output is latched before the sense enabling signal is removed to power it down. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further details of the present invention are explained with the help of the attached drawings in which: 
       FIG. 1  shows components of a conventional eFuse cell; 
       FIG. 2  shows components of an eFuse cell with sensing components according to embodiments of the present invention for reading the eFuse cell; 
       FIG. 3  shows waveforms for a read operation using the circuitry of  FIG. 2 ; and 
       FIG. 4  illustrates an embodiment of circuit components usable in the comparator of  FIG. 2 . 
   

   DETAILED DESCRIPTION 
     FIG. 2  shows a block diagram of an eFuse cell with a sensing circuit according to embodiments of the present invention. The comparator  20 , which replaces the inverters  12  and  14  of prior circuits, is represented having three inputs and one output. The ‘in’ input comes from node n 3  of the eFuse cell  42 , while the reference or ‘ref’ input comes from a reference voltage Vref generated by reference generator circuit  40 , and an enable input ‘Enable Sense_b’ input when asserted compares the former two inputs. The ‘out’ output produces the state of the eFuse after the comparison. If the voltage on node n 3  is less than the Vref voltage during the comparison, the comparator  20  produces a logic low on the output. Similarly, if the n 3  voltage is greater than the Vref voltage during the comparison, a logic high is produced by comparator  20 . PMOS transistor  10  in one embodiment is a low Vt device. For convenience, components carried over from  FIG. 1  to  FIG. 2 , as well as components carried over in subsequent drawings, are similarly labeled. 
   This reference generator circuit  40  mimics the read path of the eFuse cell (transistor  10 =transistor  30 , transistor  8 =transistor  38 , and transistor  4 =transistor  24 ) and produces the Vref reference voltage as an output. With transistors in the reference generator  40  and eFuse circuit  42  the same size and made by the same process, the reference resistor  22  in the reference generator circuit  40  determines the output Vref voltage, in the same way the eFuse resistance determines the n 3  output voltage. The difference in the resistance of eFuse  2  and resistance Rref of resistor  22  produces a delta voltage ΔV to the comparator  20 . Thus the trip point of the comparator  20  can be expressed as a function of the resistance Rref of resistor  22 . If eFuse resistance is less than Rref the sensing circuit will produce a logic 0 because Vn 3 &lt;Vref, and if the resistance of eFuse  2  is greater than Rref, a logic 1 is produced. 
   Note that Vref also connects to the gate of transistor  30 , so that both transistor  30  and transistor  10  have the same gate voltage. In one embodiment, both transistor  10  and  30  are set to operate in the saturation region of MOS operation. The transistors  10  and  30  are then both low Vt versions of PMOS devices to allow for low Vdd operation, although regular Vt versions are possible. This ensures that the main difference between the reference generator  40  and eFuse cell  42  are the resistances of resistor  22  and eFuse  2 , as far as reading the eFuse state is concerned. 
   Because corresponding transistors of the reference generator circuit  40  and the eFuse cell  42  match, both Vref and the voltage at node n 3  vary substantially identically with PVT variations, so that the trip point is solely determined by the resistance Rref. The resistor  22  in one embodiment can be implemented with salicide blocked poly. In another embodiment it can also be diffusion, or a discrete, off-chip resistor. The reference voltage generator  40  in one embodiment is shared between an array of eFuse cells, helping to reduce area requirements. 
   During read operations, when Read=1, static current is consumed from the Vdd supply because there is a low impedance path between Vdd and ground through either transistors  10 ,  8  and  4 , or transistors  30 ,  38  and  24 . If the data is required to be available for long periods of time, this static current drain would not be desirable. Instead, the data from eFuse cell  2  can be read for a short period of time, and the flip-flop  36  can be used to latch and store the data. Once the eFuse cell is read, the power supply can be disabled to components of the eFuse cell  42  and reference generator circuit  40  to prevent a power drain. The signal Enable Sense_b signal applied to the comparator  20  provides a power supply disabling signal between reads of the eFuse cell. The signal Read_b applied to the flip-flop  36  similarly allows for reading of he eFuse cell state only when the eFuse cell is powered up. 
     FIG. 3  shows waveforms illustrating a read operation using the circuitry of  FIG. 2  and the Enable Sense_b signal. Initially a read signal is applied to enable reading in a high state. The voltage difference between Vref and the voltage on node n 3 , ΔV, is shown changing states both during the read signal and after the read signal goes back low. The Enable Sense_b is enabled in a low state, as indicated by the “_b”, for a period of time. When Read first goes high, ΔV changes as shown by arrow  51 , but neither the Data Available, nor the Data Stored change because Enable Sense_b remains disabled. Once Enable Sense_b is enabled, then the Data Available will transition because the comparator  20  can change states as shown by arrow  52 . Data Stored, however, remains unchanged with arrow  52 . With arrow  53 , the Read signal returns to low, and the latch is triggered with read_b to latch the state of the Data Available as Data Stored. Arrows  53  and  54  show that even though ΔV and Data Available may change with the comparator  20  disabled with Enable Sense_b, the Data Stored will not change states without Read being toggled to trigger flip-flop  36 . 
     FIG. 4  shows a circuit implementation of the comparator  20  in accordance with one embodiment of the invention. The circuit initially includes cross coupled inverters  70  and  71 . Inverter  70  is made up of PMOS transistor  60  and NMOS transistor  61 . Inverter  71  is made up of transistors  63  and  64 . Input signal controlled supply switches are formed using PMOS transistors  76  and  78 . The PMOS transistors  76  and  78  control power supplied to the respective inverters  70  and  71 . Gates of the PMOS transistors  76  and  78  receive the inputs “in” and “ref” of the comparator  20 . Inverter  86  connected to the output of inverter  71  provides the output of the comparator  20 . An inverter  88  connects to the output of inverter  70 , the inverter  88  matching inverter  86  to balance the load between the cross coupled inverters  70  and  71 . 
   The comparator  20  further includes enabling components to initialize the comparator  20  to enable accurate reading of the eFuse state. The PMOS transistor  74  acts as a Vdd supply switch for the entire comparator circuit  20 . When not sensing (Enable Sense_b=1), PMOS transistor  74  is off to disconnect Vdd and NMOS transistors  80 - 83  are on to pull nodes n 6  and n 7 , as well as the outputs of cross coupled inverters  70  and  71  to ground to initialize the inverters  70  and  71 . This keeps the two symmetrical halves in an identical state in preparation for sensing the delta voltage across the “ref” and “in” inputs. When Enable Sense_b goes from 1 to 0, PMOS transistor  74  turns on to supply power to node n 5 . 
   Depending on the relative voltages on “ref” and “in”, either transistor  76  or  78  will be turned on faster than the other, and transistor  74  will supply the voltage Vdd to raise the power supply at the nodes n 6  and n 7  to Vdd at a different speed, so as to steer the cross coupled inverters  70  and  71  into a certain state. If the voltage on “in” is higher than “ref”, node n 6  will rise faster. With the gate of transistor  60  initially low, current passes through transistor  60  to turn on transistor  64  and turn off transistor  63 . This in turn drives the output of inverter  71  low, maintaining the gate of transistor  60  low and keeping transistor  61  off so that the output of inverter  70  stays high. With the output of inverter  71  low, the inverter  86  will provide a high output. In a similar way, if the voltage on “in” is lower than “ref”, the cross-coupled inverter  70  and  71  will produce a low data output through inverter  86 . 
   As previously mentioned, the purpose of NMOS transistors  80 - 83  is to keep the two symmetrical halves of the comparator circuit  20  in the same state prior to sensing. To do so helps increase the sensitivity of the comparator  20 , meaning the circuit will be able to resolve smaller delta voltages across “ref” and “in” into logic 1s and 0s. 
   Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims.