Abstract:
A semiconductor integrated circuit device includes a first block, a second block, and a control section. The first block includes a first fuse, a first switching configured to write data to the first fuse, a first holding portion capable of holding a first instruction, and a first instruction portion configured to turn on the first switching when a second instruction is given thereto with the first instruction. The second block includes a second fuse, a second switching configured to write data to the second fuse, a second holding portion capable of holding the first instruction, and a second instruction portion configured to turn on the second switching when the second instruction is given thereto with the first instruction. The control section issues the second instruction at a point in time when the first instruction is held in the first and second holding portions.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-322518, filed Dec. 18, 2008, the entire contents of which are incorporated herein by reference. 
       BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to a semiconductor integrated circuit device, in which data is written to one-time programmable (OTP) memory elements welded by electric current, and a control method therefore. 
         [0004]    2. Description of the Related Art 
         [0005]    The number of electrical fuse elements used in a system LSI mounted with memory elements is assumed to be several hundred to 1,000. If data is programmed in a plurality of fuses in one write processing cycle, a required current value increases. Thus, a circuit is needed to supply current for programming. Even if programs are simultaneously executed for a plurality of electrical fuse elements, moreover, there are inevitable differences in programming time between the fuse elements. 
         [0006]    Thus, the values of currents that flow individually through the electrical fuse elements must be controlled, and this control is laborious. As described in Japanese Patent No. 2007-48394, to overcome this, there is a method in which electrical fuse elements mounted in an LSI are programmed one after another. 
       BRIEF SUMMARY OF THE INVENTION 
       [0007]    A semiconductor integrated circuit device according to aspect of the present invention includes, 
         [0008]    a first functional block including a first fuse element, a first switching circuit configured to write data to the first fuse element when turned on, a first holding portion capable of holding a first write instruction transferred synchronously with a clock, and a first instruction portion configured to turn on the first switching circuit when a second write instruction is given thereto with the first write instruction held in the first holding portion; 
         [0009]    a second functional block including a second fuse element, a second switching circuit configured to write data to the second fuse element when turned on, a second holding portion capable of holding the first write instruction transferred from the first holding portion in synchronism with a clock, and a second instruction portion configured to turn on the second switching circuit when the second write instruction is given thereto with the first write instruction held in the second holding portion; and 
         [0010]    a control section which issues the second write instruction at a point in time when the first write instruction is held in the first and second holding portions as the data are written to the first and second fuse elements. 
         [0011]    The method of control a semiconductor integrated circuit device, the device including functional blocks for individually controlling fuse elements, the functional blocks individually including holding circuits capable of holding a first write instruction, the holding circuits being connected in series, the method according to aspect of the present invention, 
         [0012]    causing each of the functional blocks to sequentially transfer the first write instruction in synchronism with a clock signal; 
         [0013]    causing a control section to output a second write instruction to the functional block corresponding to any of the fuse elements to be an object of writing at a point in time when the first write instruction is transferred to the holding circuit of the corresponding functional block; and 
         [0014]    causing the functional block given both the first and second write instructions to write data to the corresponding fuse element. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0015]      FIG. 1  is a block diagram of a program control circuit according to a first embodiment of the invention; 
           [0016]      FIG. 2  is a flowchart showing the operation of the program control circuit according to the first embodiment; 
           [0017]      FIG. 3  is a time chart showing various signals in the program control circuit according to the first embodiment; 
           [0018]      FIG. 4  is a block diagram of a program control circuit according to a second embodiment of the invention; 
           [0019]      FIG. 5  is a flowchart showing the operation of the program control circuit according to the second embodiment; 
           [0020]      FIG. 6  is a time chart showing various signals in the program control circuit according to the second embodiment; 
           [0021]      FIG. 7  is a block diagram of a memory system provided with the program control circuit according to the first and second embodiment; and 
           [0022]      FIG. 8  is a block diagram of the program control circuit according to the first and second embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0023]    Embodiments of this invention will now be described with reference to the accompanying drawings. In the description to follow, like reference numbers designate common portions throughout the several views. 
       First Embodiment 
       [0024]    The following is a description of a semiconductor integrated circuit device according to a first embodiment of the invention and a memory system provided with the same. The present embodiment, as described below, is based on a configuration (hereinafter referred to as the program control circuit) for controlling programs for electrical fuse elements that function as OTP elements. 
         [0025]    &lt;Configuration of Program Control Circuit&gt; 
         [0026]    The program control circuit according to the present embodiment will be described with reference to  FIG. 1 . The circuit shown in  FIG. 1  is provided with electrical fuse elements that relieve memory cells for three bits when a memory is flawed, for example. As shown in  FIG. 1 , a program control circuit  1  is provided with a control section  10 , flip-flop  20 , and three functional blocks  30 - 0  to  30 - 2 . 
         [0027]    The control section  10  outputs a write signal PE and signal SI to the flip-flop  20  and functional block  30 - 2 , respectively, based on a clock signal CLK, in order to execute programs for respective electrical fuse elements of the functional blocks  30 - 0  to  30 - 2 . 
         [0028]    The flip-flop  20  latches the write signal PE in synchronism with the clock signal CLK and outputs it as a write signal PEp to the functional blocks  30 - 0  to  30 - 2 . 
         [0029]    The functional block  30 - 2  is provided with an electrical fuse element  31 - 2 , MOS transistor  32 - 2 , AND gate  33 - 2 , and flip-flop  34 - 2 . The electrical fuse element  31 - 2  is enabled to hold data and is energized when the data is programmed. One end (source) of the MOS transistor  32 - 2  is grounded to a current path, and the other end (drain) is connected to one end of the electrical fuse element  31 - 2 . The fuse element  31 - 2  is programmed when the MOS transistor  32 - 2  is turned on. The flip-flop  34 - 2  latches signal SI from the control section  10  in synchronism with the clock signal CLK and transfers it as signal SI&lt; 2 &gt; to the AND gate  33 - 2  and functional block  30 - 1 . The AND gate  33 - 2  performs an AND operation for the write signal PEp, signal SI&lt; 2 &gt;, and clock signal CLK. The result of the AND operation is output as signal PRG&lt; 2 &gt; to the gate of the MOS transistor  32 - 2 . When signal PRG&lt; 2 &gt; goes high, therefore, the MOS transistor  32 - 2  is turned on, whereupon the electrical fuse element  31 - 2  is programmed. 
         [0030]    The functional block  30 - 1  is provided with an electrical fuse element  31 - 1 , MOS transistor  32 - 1 , AND gate  33 - 1 , and flip-flop  34 - 1 . The electrical fuse element  31 - 1  is enabled to hold data and is energized when the data is programmed. One end (source) of the MOS transistor  32 - 1  is grounded to the current path, and the other end (drain) is connected to one end of the electrical fuse element  31 - 1 . The fuse element  31 - 1  is programmed when the MOS transistor  32 - 1  is turned on. The flip-flop  34 - 1  latches signal SI&lt; 2 &gt; from the flip-flop  34 - 2  in synchronism with the clock signal CLK and transfers it as signal SI&lt; 1 &gt; to the AND gate  33 - 1  and functional block  30 - 0 . The AND gate  33 - 1  performs an AND operation for the write signal PEp, signal SI&lt; 1 &gt;, and clock signal CLK. The result of the AND operation is output as signal PRG&lt; 1 &gt; to the gate of the MOS transistor  32 - 1 . When signal PRG&lt; 1 &gt; goes high, therefore, the MOS transistor  32 - 1  is turned on, whereupon the electrical fuse element  31 - 1  is programmed. 
         [0031]    The functional block  30 - 0  is provided with an electrical fuse element  31 - 0 , MOS transistor  32 - 0 , AND gate  33 - 0 , and flip-flop  34 - 0 . The electrical fuse element  31 - 0  is enabled to hold data and is energized when the data is programmed. One end (source) of the MOS transistor  32 - 0  is grounded to the current path, and the other end is connected to one end of the electrical fuse element  31 - 0 . The fuse element  31 - 0  is programmed when the MOS transistor  32 - 0  is turned on. The flip-flop  34 - 0  latches signal SI&lt; 1 &gt; from the flip-flop  34 - 1  in synchronism with the clock signal CLK and transfers it as signal SI&lt; 0 &gt; to the AND gate  33 - 0  and functional block  30 - 0 . The AND gate  33 - 0  performs an AND operation for the write signal PEp, signal SI&lt; 0 &gt;, and clock signal CLK. The result of the AND operation is output as signal PRG&lt; 0 &gt; to the gate of the MOS transistor  32 - 0 . When signal PRG&lt; 0 &gt; goes high, therefore, the MOS transistor  32 - 0  is turned on, so that the electrical fuse element  31 - 0  is programmed. 
         [0032]    If the functional blocks  30 - 0  to  30 - 2  are not distinguished from one another, in the configuration described above, they will be collectively referred to as functional blocks  30 . Likewise, if the electrical fuse elements  31 - 0  to  31 - 2 , MOS transistors  32 - 0  to  32 - 2 , AND gates  33 - 0  to  33 - 2 , and flip-flops  34 - 0  to  34 - 2  are not discriminated from one another, they will be simply referred to as electrical fuse elements  31 , MOS transistors  32 , AND gates  33 , and flip-flops  34 , respectively. 
         [0033]    &lt;Operation of Program Control Circuit&gt; 
         [0034]    A data write operation of the program control circuit according to the abovementioned present embodiment will now be described with reference to  FIG. 2 .  FIG. 2  is a flowchart showing the operation of the program control circuit according to the present embodiment. 
         [0035]    First, the control section  10  determines an electrical fuse element  31 - i  (i=0, 1 or 2) as an object of writing (Step S 0 ) and issues signal SI to the flip-flop  34 - 2  (S 1 ). When signal SI is issued, signal SI&lt;j&gt; goes high in synchronism with the clock signal CLK (S 2 ). However, the initial value of j immediately after the issue of signal SI is 2. 
         [0036]    If j=i, that is, if signal SI&lt;j&gt; input to a functional block to be programmed is high level (YES in S 3 ), in this case, the control section  10  issues the write signal PE to the flip-flop  20  with a timing such that the write signal PEp goes high during a period in which a flip-flop  34 - i  holds signal SI&lt;j&gt; (S 4 ). 
         [0037]    Thereupon, an AND gate  33 - i  makes signal PRG&lt;j&gt; high level (S 5 ). Thus, a MOS transistor  32 - j  is turned on (S 6 ), so that a current flows through the electrical fuse element  31 - i , and programming is performed (S 7 ). 
         [0038]    Then, the control section  10  checks the value of j. If j=0 (YES in S 8 ), writing to the electrical fuse elements is terminated. 
         [0039]    If the value of j is not 0 (NO in S 8 ), 1 is subtracted from j (S 9 ), and the aforementioned processing of Step S 2  and the subsequent steps is repeated so that j=0 is obtained. 
         [0040]    If it is concluded in Step S 3  that j≠i, that is, if signal SI&lt;j&gt; input to a functional block not to be programmed is high level (NO in S 3 ), the control section  10  does not issue the write signal PE (S 10 ), that is, PE is low level. Thereupon, an AND gate  33 - j  makes signal PRG&lt;j&gt; low level (S 11 ). Thus, the MOS transistor  32 - j  is turned off (S 12 ), so that the electrical fuse element  31 - j  is not programmed. Thereafter, the process of Step S 8  is executed by the control section  10  (S 8 ). 
         [0041]    A specific example of this processing will be described with reference to  FIG. 3 .  FIG. 3  is a time chart showing the clock signal CLK and signals SI, SI&lt; 0 &gt; to SI&lt; 2 &gt;, PE, PEp, and PRG&lt; 0 &gt; to PRG&lt; 2 &gt;. 
         [0042]    In the following example, programming is performed for the electrical fuse elements  31 - 0  to  31 - 2 . The electrical fuse element  31 - 0  is first programmed, the electrical fuse element  31 - 1  is then subjected to non-programmable processing, and the electrical fuse element  31 - 2  is finally programmed. 
         [0043]    &lt;Processing for Electrical Fuse Element  31 - 2 &gt; 
         [0044]    First, the electrical fuse element  31 - 2  is programmed (S 0 ). At time t 0  when the clock signal CLK is low level, signal SI and write signal PE are individually high level (S 1  and S 4 ). When the clock signal CLK goes high at time t 1 , the high level signals SI and PE are latched by the flip-flops  34 - 2  and  20 , respectively. 
         [0045]    Thus, signals PEp and SI&lt; 2 &gt; go high at times t 2  and t 3 , respectively (S 2 ). The control section  10  issues signals SI and PE while the clock signal CLK is low level, in order to secure setup periods for the flip-flops  34 - 2  and  20 . Consequently, signal PRG&lt; 2 &gt; goes high at time t 4  (S 5 ). 
         [0046]    Thus, the MOS transistor  32 - 2  is turned on (S 6 ), so that a current flows through the electrical fuse element  31 - 2 , and programming for the fuse element  31 - 2  is performed (S 7 ). 
         [0047]    Then, the control section  10  makes signals SI and PE low-level at time t 5 . At time t 6 , thereafter, the clock signal CLK goes low. When the clock signal CLK goes high at time t 7 , signals PRG&lt; 2 &gt; and PEp go low at times t 8  and t 9 , respectively. 
         [0048]    &lt;Processing for Electrical Fuse Element  31 - 1 &gt; 
         [0049]    Then, the electrical fuse element  31 - 1  is subjected to non-programmable processing. When the clock signal CLK goes high at time t 7 , the high-level signal SI&lt; 2 &gt; is latched by the flip-flop  34 - 1 . Consequently, signal SI&lt; 1 &gt; goes high at time t 10 . 
         [0050]    Since the electrical fuse element  31 - 1  is not programmed, the control section  10  keeps signal PE low level (S 10 ). Consequently, signal PRG&lt; 1 &gt; is low while signal SI&lt; 1 &gt; is low level (S 11 ). Thereupon, the MOS transistor  32 - 1  remains off (S 12 ). Thus, no current flows through the fuse element  31 - 1 , so that no program is executed. 
         [0051]    &lt;Processing for Electrical Fuse Element  31 - 0 &gt; 
         [0052]    Then, the electrical fuse element  31 - 0  is programmed. Subsequently, at time t 13  when the clock signal CLK is low level, the control section  10  makes the write signal PE high level (S 4 ). When the clock signal CLK then goes high at time t 14 , the high-level signal SI&lt; 1 &gt; is latched by the flip-flop  34 - 0 . Consequently, signal SI&lt; 0 &gt; goes high at time t 16  (S 2 ). When the clock signal CLK goes high at time t 14 , moreover, the high-level signal PE is latched by the flip-flop  20 . 
         [0053]    Thus, signal PEp goes high at time t 15 . Consequently, signal PRG&lt; 0 &gt; goes high at time t 17  (S 5 ). 
         [0054]    Thus, the MOS transistor  32 - 0  is turned on (S 6 ), so that a current flows through the electrical fuse element  31 - 0 , and programming for the fuse element  31 - 0  is completed (S 7 ). 
         [0055]    &lt;Effect According to Present Embodiment&gt; 
         [0056]    With the program control circuit according to the present embodiment, the circuit scale can be reduced. The following is a description of an effect according to the present embodiment. 
         [0057]    In the program control circuit  1 , the flip-flops  34  are connected in a serial chain such that signal SI from the control section  10  can be sequentially transferred to the functional blocks  30 - 0  to  30 - 2 . The write signal PEp is made high level when any of signals SI&lt; 0 &gt; to SI&lt; 2 &gt; output from the flip-flop  34  corresponding to the electrical fuse element to be programmed is high level. In other words, the control section  10  issues the write signal PEp so that it is high level at this time. 
         [0058]    Thus, each of the functional blocks  30 - 0  to  30 - 2  does not need to have information on whether or not it is an object of writing. Further, each functional block is not expected to hold information on the timing for the programming of its electrical fuse element  31  either. Thus, the circuit scale can be reduced. 
       Second Embodiment 
       [0059]    The following is a description of a semiconductor integrated circuit device according to a second embodiment of the invention. In the present embodiment, the non-programmable processing according to the first embodiment for electrical fuse elements that are not to be programmed is omitted. 
         [0060]    &lt;Configuration of Program Control Circuit&gt; 
         [0061]      FIG. 4  is a block diagram of a program control circuit according to the present embodiment. As shown in  FIG. 4 , a program control circuit  1  of the present embodiment is further provided with a data decoder  40  added to the configuration of  FIG. 1  described in connection with the first embodiment. 
         [0062]    The data decoder  40  receives an address signal DI of a memory cell to be relieved from, for example, a controller (not shown). The decoder  40  decodes signal DI and supplies the result of this decoding as signal Dp&lt;i&gt; to functional blocks  30 - 0  to  30 - 2 . More specifically, signal Dp&lt;i&gt; is supplied (or asserted) to a flip-flop  34 - i  corresponding to an electrical fuse element  31 - i  to be programmed. If a plurality of electrical fuse elements  31 - i  are to be programmed, in this case, signals Dp&lt;i&gt; are supplied individually to flip-flops  34 - i  with staggered timing. Thus, in each period of a clock signal CLK, only one of signals Dp&lt; 0 &gt; to Dp&lt; 2 &gt; goes high. 
         [0063]    Further, a control section  10  does not issue signal SI. Flip-flops  34 - 0  to  34 - 2  receive signals Dp&lt; 0 &gt; to Dp&lt; 2 &gt; and output them to AND gates  33 - 0  to  33 - 2 , respectively. 
         [0064]    The AND gates  33 - 0  to  33 - 2  individually perform AND operations for signal PEp, signals Dp&lt; 0 &gt; to Dp&lt; 2 &gt;, and clock signal CLK. The results of the AND operations are output as signals PRG&lt; 0 &gt; to PRG&lt; 2 &gt;. Other configurations are the same as those of the first embodiment. 
         [0065]    &lt;Operation of Program Control Circuit&gt; 
         [0066]    A data write operation of the program control circuit according to the abovementioned present embodiment will now be described with reference to  FIG. 5 .  FIG. 5  is a flowchart showing the operation of the program control circuit according to the present embodiment. 
         [0067]    First, the control section  10  determines (Step S 0 ) the electrical fuse element  31 - i  (i=0, 1 or 2) as an object of writing (Step S 0 ) and issues a write signal PE to the flip-flop  20  (S 21 ). Then, the data decoder  40  decodes an externally received address signal DI (S 22 ). Further, the data decoder  40  executes write processing for the electrical fuse elements  31 - 2  to  31 - 0  in the order named, so that the control section  10  concludes that j=2 (S 23 ). Thus, if there are a plurality of objects for which signals Dp&lt;i&gt; are issued, signals Dp&lt;i&gt; are sequentially issued starting from the side of the electrical fuse element  31 - 2 . Thereupon, the data decoder  40  sequentially notices the functional blocks  30 , starting with the one nearest to the control section  10 . The functional block  30  that is noticed by the data decoder  40  will be referred to as the functional block  30 - j . Thus, the initial value of j is 2. 
         [0068]    If j=i, that is, if the functional block  30 - j  is a functional block to be programmed (YES in S 24 ), in this case, the data decoder  40  issues signal Dp&lt;j&gt;. Specifically, signal Dp&lt;j&gt; is assumed to be high level. 
         [0069]    Thereupon, an AND gate  33 - i  makes signal PRG&lt;j&gt; high level (S 5 ). Thus, a MOS transistor  32 - j  is turned on (S 6 ), so that a current flows through the electrical fuse element  31 - i , and programming is performed (S 7 ). 
         [0070]    Then, the control section  10  checks the value of j. If j=0 (YES in S 8 ), writing to the electrical fuse elements is terminated. 
         [0071]    If the value of j is not 0 (NO in S 8 ), 1 is subtracted from j (S 9 ), and the aforementioned processing of Step S 24  and the subsequent steps is repeated so that j=0 is obtained. 
         [0072]    If it is concluded in Step S 24  that j≠i (NO in S 24 ), that is, if the functional block is not one to be programmed, the data decoder  40  does not issue signal Dp&lt;j&gt;, that is, signal Dp&lt;j&gt; is low level (S 26 ). Thereupon, an AND gate  33 - j  makes signal PRG&lt;j&gt; low level (S 11 ). Thus, the MOS transistor  32 - j  is turned off (S 12 ), so that an electrical fuse element  31 - j  is not programmed. Thereafter, the process of Step S 8  is executed by the control section  10  (S 8 ). 
         [0073]    A specific example of this processing will be described with reference to  FIG. 6 .  FIG. 6  is a time chart showing the clock signal CLK and signals Dp&lt; 0 &gt; to Dp&lt; 2 &gt;, PE, PEp, and PRG&lt; 0 &gt; to PRG&lt; 2 &gt;. In  FIG. 6 , signals Dp&lt; 0 &gt; to Dp&lt; 2 &gt; are signals that are output from the flip-flops  34 - 0  to  34 - 2  to AND gates  33 - 0  to  33 - 2 . 
         [0074]    In the following example, programming is performed for the electrical fuse elements  31 - 0  and  31 - 2 . Programming is first performed for the electrical fuse element  31 - 0  and then for the electrical fuse element  31 - 2 . 
         [0075]    &lt;Processing for Electrical Fuse Element  31 - 2 &gt; 
         [0076]    First, the electrical fuse element  31 - 2  is programmed (S 0 ). At time t 0  when the clock signal CLK is low level, the control section  10  first makes the write signal PE high level (S 21 ). When the clock signal CLK goes high at time t 1 , the write signal PE is latched by the flip-flop  20 , and signal PEp goes high at time t 2 . 
         [0077]    At time t 3  in a period during which the clock signal CLK is high-level, thereafter, the flip-flop  34 - 2  issues signal Dp&lt; 2 &gt; from the data decoder  40  to the AND gate  33 - 2 , regarding signal as being high level (S 25 ). 
         [0078]    Consequently, signal PRG&lt; 2 &gt; goes high at time t 4  (S 5 ). Thus, a MOS transistor  32 - 2  is turned on (S 6 ), so that a current flows through the electrical fuse element  31 - 2 , and programming for the fuse element  31 - 2  is performed (S 7 ). 
         [0079]    At time t 5 , moreover, the control section  10  makes write signal PE low level. When the clock signal CLK goes low at time t 6 , thereafter, signal PRG&lt; 2 &gt; goes low at time t 7 . At time t 8 , the data decoder  40  makes signal Dp&lt; 2 &gt; low level. Then, at time t 9  in a period during which the clock signal CLK is low level, the control section  10  makes the write signal PE high level (S 21 ). When the clock signal CLK goes high at time t 10 , the write signal PE is latched by the flip-flop  20 . Thus, the write signal PEp continually maintains high level from time t 0  onward. 
         [0080]    &lt;Processing for Electrical Fuse Element  31 - 0 &gt; 
         [0081]    Then, the electrical fuse element  31 - 0  is programmed. At time t 11  in a period during which the clock signal CLK is high level, the flip-flop  34 - 0  makes signal Dp&lt; 0 &gt; to be issued to the AND gate  33 - 0  high level (S 25 ). 
         [0082]    Consequently, signal PRG&lt; 0 &gt; goes high at time t 12  (S 5 ). Thereupon, the AND gate  33 - 0  makes signal PRG&lt; 0 &gt; high level and outputs it to the gate of the MOS transistor  32 - 0 . Thus, the MOS transistor  32 - 2  is turned on (S 6 ), so that a current flows through the electrical fuse element  31 - 2 , and programming for the fuse element  31 - 2  is performed (S 7 ). 
         [0083]    Since signal Dp&lt; 1 &gt; is low level during the period from time to t 0  time t 16 , signal PRG&lt; 1 &gt; is always low level. Thus, programming for the electrical fuse element  31 - 1  is not performed. 
         [0084]    &lt;Effect According to Present Embodiment&gt; 
         [0085]    In addition to the effect according to the first embodiment, with the program control circuit according to the present embodiment, there is an effect that programming time can be cut down. The following is a description of this effect. 
         [0086]    In the present embodiment, the data decoder  40  issues signal Dp to only the flip-flop corresponding to the electrical fuse element to be programmed. In other words, signal Dp is not issued to any of the electrical fuse elements that are not be programmed. Thus, signal Dp is always low level. 
         [0087]    In a programmable or non-programmable mode, therefore, the functional blocks  30  that require processing synchronous with the clock signal CLK should only be those which include the electrical fuse elements  31  to be programmed. In other words, the functional blocks that include no electrical fuse elements to be programmed do not require special processing. This is because programming is always inhibited with the low level signal Dp. Thus, the programming time can be cut down in proportion to the number of electrical fuse elements that are not to be programmed. 
         [0088]    The program control circuits according to the first and second embodiments can be used to relieve a cache in the memory system. This memory system will be described with reference to  FIG. 7 .  FIG. 7  is a block diagram of the memory system. 
         [0089]    As shown in  FIG. 7 , a memory system  50  is, for example, a computer that is provided with a CPU  51 , main memory  52 , cache memory  54 , I/O terminal  53 , program control circuit  55 , and data bus  56 . 
         [0090]    The main memory  52  is a semiconductor memory, such as an SRAM or DRAM, which holds programs and data used in the CPU. 
         [0091]    The cache memory  54  is also a semiconductor memory, such as an SRAM or DRAM, which temporarily holds programs and data stored in the main memory  52 . 
         [0092]    The CPU  51  performs computation based on the programs and data in the main memory  52  or cache memory  54 . 
         [0093]    The I/O terminal  53  accepts an external data input and outputs data and the result of the computation to the outside. 
         [0094]    The data bus  56  connects the CPU  51 , main memory  52 , I/O terminal  53 , and cache memory  54  so that data can be transferred between them. 
         [0095]    The program control circuit  55  is identical with the program control circuit  1  described in connection with each of the first and second embodiments. In the program control circuit  55 , the electrical fuse elements  31  are loaded with the addresses of defective cells in the cache memory  54 . 
         [0096]    In the configuration of  FIG. 7 , moreover, the function of the control section  10  (and data decoder  40 ) in the program control circuit  1  may be assigned to the CPU and cache memory. This aspect will be described with reference to  FIG. 8 .  FIG. 8  is a block diagram of the control section  10  described in connection with each of the first and second embodiments. 
         [0097]    As shown in  FIG. 8 , the control section  10  is provided with a cache memory  61 , CPU  60 , and data bus  63 . Further, the cache memory  61  is provided with a program  62 , which determines the issue timings of the signals described in connection with each of the first and second embodiments. 
         [0098]    According to the first embodiment, for example, the cache memory  61  temporarily holds the program  62  that determines the respective issue timings of the clock signal CLK, signal SI, and write signal PE. This program includes information on defective memory cells, that is, on the electrical fuse elements  31  to be programmed. By performing the computation after reading this program from the cache memory  61 , the CPU  60  issues the clock signal CLK, signal SI, and write signal PE with the timings shown in  FIG. 3 . 
         [0099]    According to the second embodiment, on the other hand, the cache memory  61  holds the program that determines the respective issue timings of the clock signal CLK, signal Dp, and write signal PE. This program also includes information on defective memory cells. By performing the computation after reading this program from the cache memory  61 , the CPU  60  issues the clock signal CLK, signal Dp, and write signal PE with the timings shown in  FIG. 6 . 
         [0100]    In the program control circuit according to the first embodiment, in particular, the programs are successively executed in synchronism with the clock signal CLK for all the functional blocks  30 - 0  to  30 - 2 . In consideration of this point, the program control circuit is effective for the case where the size of a memory to be relieved is as small as, for example, 128 bits (or 16 bytes). 
         [0101]    Although the program control circuits according to the first and second embodiments have been described as being configured to relieve defective memory cells for three bits, moreover, it may alternatively be configured to relieve defectives for four or more bits. In other words, the number of functional blocks may be increased depending on the number of bits that should be relieved. 
         [0102]    Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.