Abstract:
A system error analysis device which includes a top unit and a storage unit coupled to the top module is mentioned. The storage unit is configured to store each of the input data, each of the output data and each of the bus data transmitted by the top unit. When receiving an interrupting signal, the system error analysis device outputs the input data, the output data and the bus data stored as soon as the interrupting signal is received and the input data, the output data and the bus data stored before the receiving of the interrupting signal. Accordingly, by comparing and analyzing the data output by system error analysis device, the system employing the system error analysis device is able to obtain the reason of the generation of the interrupting signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No(s). 100147789 filed in Taiwan, R.O.C. on Dec. 21, 2011, the entire contents of which are hereby incorporated by reference. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present disclosure relates to an analyzing method and the device using the same, more particularly to a system error analyzing method and the device using the same. 
         [0004]    2. Related Art 
         [0005]    Generally, a server system takes a programmable logic device as a controlling device which is used for controlling signals in the baseboard. The programmable logic device has a top unit and a plurality of function unit, wherein the function units are connected to the top unit. Here, by the top unit, the programmable logic device can receive input data from an external input device and transmit them to the function units. Then the programmable logic device outputs the output data received from the function unit and transmits them to the corresponding external input device, and transmits bus data from an external bidirectional bus device to the function units. Thus, the programmable logic device can control and process the signals outputted and received by the input device, the output device, and the bidirectional bus device in the server system. 
         [0006]    Furthermore, the programmable logic device also has a memory space for storing the signals on the baseboard. In addition, the programmable logic device outputs the data stored in the memory space to inform the user or the administrator the state of the baseboard. However, because the memory space mentioned above merely could store the signals in the baseboard, once an error occurs during the operation of the server system or the power of the server system is interrupted, it is difficult for the server system to analyze the causation of the failure or the power interruption. 
       SUMMARY 
       [0007]    In one aspect, some embodiments provide a system error analyzing method. The system error analysis method is used in a system error analysis device. The system error analysis device is capable of receiving an interrupting signal and includes a top unit. Thus, the system error analysis method comprises the following steps: N input data, M output data, and P bus data transmitted by the top unit are stored, wherein N, M and P are positive integers. Whether the N, M or P is larger than or equal to 2 is determined when the interrupting signal is received. The Nth input data and the (N−1)th input data are output, if N is larger than or equal to 2, wherein the Nth input data is stored when the interrupting signal is received. The Mth output data and the (M−1)th output data are output, if M is larger than or equal to 2, wherein the Mth output data is stored when the interrupting signal is received.; The Pth bus data and the (P−1)th bus data are output, if P is larger than or equal to 2, wherein the Pth bus data is stored when the interrupting signal is received. 
         [0008]    In another aspect, some embodiments provide a system error analysis device. The system error analysis device is electrically coupled to at least one input device, at least one output device and at least one bidirectional bus device. The system error analysis device is capable of receiving an interrupting signal. The system error analysis device includes a top unit and a storage unit. The top unit is configured to receive N input data output from the at least one input device, output M output data to the at least one output device and transmit P bus data from at least one bidirectional bus device to the system error analysis device. Wherein N, M and P are positive integers. The storage unit is coupled to the top unit and is configured to store the N input data, the M output data and the P bus data. When the system error analysis device receives the interrupting signal, the system error analysis device respectively determines whether the N, M and P is larger than or equal to 2. If N is larger than or equal to 2, the storage unit outputs a Nth input data and a (N−1)th input data, wherein the Nth input data is stored when the interrupting signal is received. If M is larger than or equal to 2, the storage unit outputs a Mth output data and a (M−1)th output data, wherein the Mth output data is stored when the interrupting signal is received. If P is larger than or equal to 2, the storage unit outputs a Pth bus data and a (P−1)th bus data, wherein the Pth bus data is stored when the interrupting signal is received. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The present disclosure will become more fully understood from the detailed description given herein below for illustration only, and thus are not limitative of the present disclosure, and wherein: 
           [0010]      FIG. 1A  is a block diagram of a structure of a system error analysis device  100  without interrupt signal received, according to one embodiment of the disclosure; 
           [0011]      FIG. 1B  is block diagram of a structure of a system error analysis device  100  with the interrupt signals received, according to the embodiment of the disclosure; 
           [0012]      FIG. 2  is a flow chart of the system error analysis method implemented by the system error analysis device as shown in  FIG. 1B  according to the embodiment of the disclosure; and 
           [0013]      FIG. 3  is a schematic structural view of the input device, the output device, the bidirectional bus device, the top unit and the storage unit shown in  FIG. 1A , according to an embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    In the following embodiments, a system error analysis device  100  can be implemented by a complex programmable logic device (CPLD) used in a server system  200 , but the disclosure is limited by the embodiments. 
         [0015]      FIG. 1A  is a block diagram of the system error analysis device  100  of an embodiment, wherein no interrupt signal is received.  FIG. 1B  is block diagram of the system error analysis device  100 , wherein the interrupt signals are received. In this embodiment, the system error analysis device  100  is employed by a server system  200  and is suitable for connecting with four input devices  20 , two output devices  30  and one bidirectional bus device  40 . The four input devices  20  are, for example, GPI (General Purpose Input) devices, the two output devices  30  are, for example, GPOs (General Purpose Outputs) devices, and the bidirectional bus device  40  is, for example, LPC (Low Pin Count) device. Here, the numbers of the input device, the output device and the bidirectional bus device which are coupled with the actual system error analysis device  100  can be adjusted according to the actual demand. 
         [0016]    Here, the system error analysis device  100  comprises four function units  50 , a top unit  60  and a storage unit  70 . Each of the function units and the storage unit  70  are coupled to the top unit  60 , and the top unit  60  is coupled to the four input devices  20 , the two input devices  300  and the bidirectional bus device  40 . In this embodiment, four function units  50  are provided in the system error analysis device  100 , but the disclosure is limited by the embodiment. 
         [0017]    The top unit  60  is used to transmit N input data  21  output from the input devices  20  to the corresponding function unit  50 , to output M output data  31  from the output device  30  to the corresponding function unit  50 , and to transmit the P BUS data  41  from the bidirectional bus device  40  to the function unit  50 , wherein N, M and P are positive integers. The storage unit  70  is used to store the N input data  21 , the M output data  31  and the P BUS data  41 , that is, the storage unit  70  is used to store all of the input data  21 , the output data  31  and the BUS data  41  received or outputted by the system error analysis device  100 . 
         [0018]    Referring  FIGS. 1A ,  1 B and  FIG. 2 ,  FIG. 2  is a flow chart of the system error analysis method implemented by the system error analysis device as shown in  FIG. 1B . The system error analysis method includes following steps. In the step S 202 , the N input data, the M output data and the P bus data transmitted by the top unit are stored, wherein all of N, M and P are positive integers. In the step S 204 , determining whether the N, M or P is larger than or equal to 2when an interrupting signal is received. In the step S 206 , the Nth input data and the (N−1)th input data are output, if N is larger than or equal to 2. The Nth input data is stored when the interrupting signal is received. In the step S 208 , the Mth output data and the (M−1)th output data are output, if M is larger than or equal to 2. The Mth output data is t stored when the interrupting signal is received. In the step S 210 , the Pth bus data and the (P−1)th bus data is output, if the P is larger than or equal to 2. The Pth bus data is stored when the interrupting signal is received. 
         [0019]    When the system error analysis device  100  does not receive an interrupting signal  80 , the system error analysis device  100  receives each of the input data  21 , outputs each of the output data  31 , and transmits each of the bus data  41 . The interrupting signal  80  can be the error signal or the power failure signal, which is transmitted by a central processing unit (not shown) in the server system  200 . When the top unit  60  inputs each of the N input data  21 , outputs each of the M output data  31  and transmits each of the P bus data  41 , the storage unit  70  reads and stores each of the input data  21  received by the top unit  60 , each of the output data  31  output by the top unit  60  and each of the bus data  41  transmitted by the top unit  60  (i.e., S 202 ). 
         [0020]    The top unit  60  comprises a first register unit  61 , a second register unit  62  and a third register unit  63 . The first register unit  61  is used to temporarily store the input data  21  from each of the input devices  20 , the second register unit  62  is used to temporarily store the output data  31  from each of the output devices  30 , and the third register unit  63  is used to temporarily store the bus data  41  transmitted from the bidirectional bus device  40  to each of the function units  50 . The data size of each of the input data  21  can be a one bit, the data size of the output data  31  can be a one bit, and the size of the bus data  41  can be, but is not limited to, 28 bits. When every bit in all of the bus data  41  is input to the third register unit  63  (that is, when the third register unit  63  has stored all of the bus data  41 ), the top unit  60  transmits each of the bus data  41  stored in the third register unit  63  to the bidirectional bus device  40  or the corresponding function unit  50 . In another word, the bus data stored in the storage unit  70  is completed. For example, data size of each of the bus data received by the storage unit is also 28 bits. 
         [0021]    Additionally, the top unit  60  further comprises a switching unit  64 . The switching unit  64  is coupled to the bidirectional bus device  40  and the third register unit  63 , when the system error analysis device  100  does not receive the interrupt signal  80 . Thus, each of the bus data  41  can be transmitted from the bidirectional bus device  40  to the third register unit  63 . 
         [0022]      FIG. 3  is a schematic structural view of the input device, the output device, the bidirectional bus device, the top unit and the storage unit according to an embodiment as shown in  FIG. 1A . In this embodiment, the storage unit  70  includes a first storage area  71 , a second storage area  72 , and a third storage area  73 . The first storage area  71  is used to store each of the input data  21 , the second storage area  72  is used to store each of the output data  31 , and the third storage area  73  is used to store each of the bus data  41 . The first storage area  71 , the second storage area  72  and the third storage area  73  are serial-in storage areas. 
         [0023]    More specifically, the first storage area  71  includes, but is not limited to, two first storage units  71   a  (i.e., each block in the first storage units  71   a , as shown in  FIG. 3 ) used to store the input data  21 . The input data  21  stored in the first one of the first storage units  71   a  (i.e., the leftmost first storage unit  71   a  in  FIG. 3 ) is the latest input data  21  stored in the first storage area  71 , while the input data  21  stored in the last one of the first storage unit  71   a  (i.e., the rightmost first storage unit  71   a  in  FIG. 3 ) is the earliest input data  21  stored in the first storage area  71 . When the number of the input data received by the first storage area  71  is more than 2, the input data  21  stored in the first one of the first storage units  71   a  is deleted, and then the input data  21  stored in the another first storage unit  71   a  is shifted into the first one of the first storage areas  71   a . In this embodiment, the number of the first storage units  71   a  can be two, the data size of each of the input data  21  transmitted by each of the input devices  20  can be, but is not limited to, one bit, and the data size of each data stored in each of the first storage unit  71   a  can be four bits. However, the embodiment is not intended to limit the disclosure. 
         [0024]    The second storage area  72  includes, but is not limited to, two second storage units  72   a  (i.e., each block in the second storage units  72   a , as shown in  FIG. 3 ) used to store the output data  31  output to the output device  30 . The output data  31  stored in the second one of second storage units  72   a  (i.e., the leftmost second storage unit  72   a  in  FIG. 3 ) is the latest output data  31  stored in second storage area  72 , while the output data  31  stored in the first one of the second storage units  72   a  (i.e., the rightmost second storage unit  72   a  in  FIG. 3 ) is the earliest output data  31  stored in the second storage area  72 . When the number of the output data received by the second storage area  72  is more than 2, the output data  31  stored in the first one of the second storage units  72   a  is deleted, and then the output data  31  stored in the second one of the second storage unit  72   a  is shifted into the first one of the second storage units  72   a . In this embodiment, the number of the second storage units  72   a  can be two, each of the output data  31  transmitted by each of the input devices  20  can be but not limited to one bit, and the amount of data stored in each of the second storage unit  72   a  can be two bits. However, the embodiment does not be used to limit the disclosure. 
         [0025]    At the same time, the third storage area  73  includes, but is not limited to, two third storage units  73   a  used to store the bus data  41 . The bus data  41  stored in the second one of third storage unit  73   a  (i.e., the leftmost third storage unit  73   a  in  FIG. 3 ) is the latest bus data  41  stored in the third storage area  73 , while the bus data  41  stored in the first one of the third storage units  73   a  (i.e., the rightmost third storage unit  73   a  in  FIG. 3 ) is the earliest bus data  41  stored in the third storage area  73 . When the number of the bus data received by the third storage area  73  is larger than 2, the bus data  41  stored in the first one of the third storage units  73   a  is deleted, and then the bus data  41  stored in the second one of the third storage units  73   a  is shifted into the first one of the third storage units  73   a . In this embodiment, the number of the third storage units  73   a  can be two, the data size of each of the bus data  41  transmitted by the bus device  40  or the function unit  50  can be, but is not limited to, 28 bits, and the data size of each data stored in each of the third storage unit  73   a  can be 28 bits. However, the embodiment is not intended to limit the disclosure. 
         [0026]    Refer to  FIGS. 1B and 2 , when the system error analysis device  100  receives the interrupting signal  80 , the bidirectional bus device  40  is coupled to the storage unit  70  by the switching unit  64 . The system error analysis device  100  determines whether the N, M or P is larger than or equal to 2 when the interrupting signal is received (S 204 ). If the system error analysis device  100  determines that N is larger than or equal to 2, then the Nth input data  21  and the (N−1)th input data  21  are outputted, wherein the Nth input data  21  is stored in the system error analysis device  100  as soon as the interrupting signal  80  is received (S 206 ). If the system error analysis device  100  determines that M is larger than or equal to 2, then the system error analysis device  100  outputs the Mth output data  31  and the (M−1)th output data  31 , wherein the Mth output data  31  is stored in the system error analysis device  100  as soon as the interrupting signal is received (S 208 ). If the system error analysis device  100  determines that P is larger than or equal to 2, the Pth bus data  41  stored in the system error analysis device  100  as soon as the interrupting signal is received (S 210 ). 
         [0027]    And then, the server system  200  receives and analyzes the data (i.e., the two input data  21 , the two output data  31 , and the two bus data  41 ) outputted by the system error analysis device  100  as the interrupting signal  80  is received for obtaining the reason of the interrupting signal  80 . Here, the steps S 206  to S 210  mentioned above can be implemented respectively or synchronously, and the actual execution sequence of the steps S 206  to S 210  can be adjusted according to the actual demanded. 
         [0028]    Additionally, the system error analysis method further comprises a step S 212  of outputting a special signal, when the interrupting signal is received and every one of N, M and P is less than 2. For example, in a case where the interrupting signal  80  is received as soon as the server system  200  starts the system error analysis device  100 , every one of the N, M and P is less than 2. In such case, the system error analysis device  100  transmits a special signal  90  to a baseboard management controller  92  for informing the server system  200  that the storage unit  70  can not provide the complete data for correcting the fault, wherein, the special signal  90  has a special flag. For example, when the system error analysis device  100  sets the flag in the special signal  90  to 1, it indicates that the storage unit  70  can not provide the complete data for correcting the fault. However, the value of the flag is not intended to limit the disclosure. In some embodiments, the system error analysis device  100  also could set the flag in the special signal  90  to 0 to indicate that the storage unit  70  can not provide the complete data for correcting the fault. 
         [0029]    According to the system error analysis method and the device thereof provided in the disclosure, since the storage unit stores each of the input data, each of the output data and each of bus data transmitted by the top unit, the system error analysis device can output two input data, two output data or two bus data (that is, the input data, the output data or the bus data received by the system error analysis device as soon as the interrupting signal is received, and the input data, the output data or the bus data stored in the system error analysis device before the interrupting signal is received), when an interrupting signal is received. By this way, the system provided with the system error analysis device could compare and analyze the data output from the system error analysis device, to obtain the reason of the interrupting signal. When the number of the input data, the number of the output data or the number of the bus data is less than two (for example, when the system just has been started) as soon as the system error analysis device received an interrupting signal, the system error analysis device outputs a special signal to inform that there is not enough for the correcting analyze.