Abstract:
An object of the present invention is to prevent formation of a badly situated via metal in a Damascene wiring portion in multiple layers having an air-gap structure. In the present invention, a via is completely separated from an air-gap  45  by forming an interlayer insulating film  44  having the air-gap  45  between adjacent Damascene wiring portions after forming a sacrifice film pillar  42  from a selectively removable insulating film in a formation region of a connection hole. The present invention can provide multiple-layered buried wiring in which a high reliable via connection and a reduced parasitic capacitance due to the air-gap are achieved.

Description:
INCORPORATION BY REFERENCE  
       [0001]     The present application claims priority from Japanese application JP2005-331020 filed on Nov. 16, 2005, the content of which is hereby incorporated by reference into this application.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a method for producing a semiconductor integrated circuit device, especially to a method for producing a semiconductor integrated circuit device having multi-layered buried wiring.  
         [0004]     2. Description of Related Art  
         [0005]     A structure of buried wiring is formed in a manner that wiring material is buried in an aperture for wiring such as a wiring groove or connection hole formed in an insulating film by wiring formation technologies as called Damascene Technologies (Single-Damascene Technology and Dual-Damascene Technology).  
         [0006]     Recently, an increase in integration of the semiconductor integrated circuit device has reduced a clearance between such buried wiring lines. This increases such parasitic capacitance to cause a signal delay. Therefore, it may be desired to reduce the parasitic capacitance between wirings.  
         [0007]     In U.S. Pat. No. 6,159,845 (hereinafter, referred to as “Patent”), a technique to form an air-gap between buried wiring lines is disclosed.  FIGS. 1A  to  1 E in this Patent illustrate a method for producing one layer having buried wiring in the order of process steps. The technique shown may be characterized by reduced parasitic capacitance between adjacent buried wiring lines, because an insulating film intervening between adjacent buried wiring lines includes an air-gap.  
         [0008]     In the Patent, a method for fabricating multi-layered buried wiring having an air-gap structure is not explicitly stated. From considerations conducted by the present inventors, it has been found that when the multi-layered buried wiring is formed using the technique described in the Patent, there may be problems of an increase in resistance of a via portion due to a defectively buried metal in the via portion, or parasitic capacitance that cannot be reduced between adjacent buried wiring lines because of metal films formed in the air-gap. This is because, as shown in  FIG. 2 , misalignment during a typical photolithographic process between underlying buried wiring portions  65  (single Damascene wiring) and the via portions  66  in the overlying buried wiring portions  68  (dual Damascene wiring) brings the via portions  66  into contact with an air-gap  67  formed between the underlying buried wiring portions  65 : this causes a metal intrusion  69  in the air-gap  67  or a defectively buried metal  70  in the via portion when metal film is formed in the overlying buried wiring portion  68  including the via portion  66 .  
       BRIEF SUMMARY OF THE INVENTION  
       [0009]     According to the present invention herein disclosed, representative embodiments will be summarized as follows.  
         [0010]     A process for producing a semiconductor integrated circuit device according to the present invention includes the following steps of:  
         [0011]     (a) providing a first insulating film over a semiconductor substrate;  
         [0012]     (b) providing a plurality of wiring grooves in the first insulating film;  
         [0013]     (c) forming a first conductive film on the first insulating film including respective insides of the plurality of the wiring grooves;  
         [0014]     (d) removing the first conductive film lying outside the plurality of the wiring grooves to form a wiring line composed of the first conductive film in respective insides of the plurality of the wiring grooves;  
         [0015]     (e) forming a second insulating film from material different than that of the first insulating film on the first insulating film and the wiring line;  
         [0016]     (f) etching the second insulating film by using a mask covering a formation region of a connection hole to be formed in a later step for exposing the upper surface of the wiring line, to form a sacrifice film pillar composed of the second insulating film in the formation region of the connection hole;  
         [0017]     (g) selectively removing the first insulating film in a region not covered with the sacrifice film pillar to leave behind the first insulating film under the sacrifice film pillar;  
         [0018]     (h) forming a third insulating film from material different than that of the second insulating film on the wiring line and sacrifice film pillar, while leaving behind an air-gap in a space region between the wiring line portions on which the first insulating film was removed;  
         [0019]     (i) removing the third insulating film on the sacrifice film pillar to expose the upper surface of the sacrifice film pillar;  
         [0020]     (j) removing the sacrifice film pillar to form the connection hole for exposing the upper surface of the wiring line; and  
         [0021]     (k) forming a second conductive film inside the connection hole.  
         [0022]     A process for producing a semiconductor integrated circuit device according to the present invention includes the following steps of:  
         [0023]     (a) providing a first insulating film over a semiconductor substrate;  
         [0024]     (b) removing a part of the first insulating film to form a plurality of first wiring grooves for a first Damascene wiring portion to be formed in a later step;  
         [0025]     (c) forming a first conductive film on the first insulating film including respective insides of the plurality of the first wiring grooves;  
         [0026]     (d) removing the first conductive film lying outside the plurality of the first wiring grooves to form the first Damascene wiring portion composed of the first conductive film in respective insides of the plurality of the first wiring grooves;  
         [0027]     (e) forming a second insulating film from material different than that of the first insulating film on the first insulating film and the first Damascene wiring portion;  
         [0028]     (f) etching the second insulating film using a mask covering a formation region of a plurality of connection holes to be formed in a later step for a via portion of a second Damascene wiring portion to form a plurality of sacrifice film pillars composed of the second insulating film in the formation region of the plurality of the connection holes;  
         [0029]     (g) selectively removing the first insulating film in a region not covered with the sacrifice film pillars to leave behind the first insulating film under the sacrifice film pillars;  
         [0030]     (h) forming a third insulating film from material different than that of the second insulating film on the wiring portion and the sacrifice film pillars, while leaving behind an air-gap in a space region between the wiring portions on which the first insulating film was removed;  
         [0031]     (i) removing the third insulating film on the sacrifice film pillars to expose the upper surface of the plurality of the sacrifice film pillars;  
         [0032]     (j) removing a part of the third insulating film and the top of the plurality of the sacrifice film pillars to form a plurality of second wiring grooves for wiring of the second Damascene wiring portion to be formed in a later step;  
         [0033]     (k) removing the bottom of the plurality of the sacrifice film pillars to form the plurality of the connection holes;  
         [0034]     (l) forming a second conductive film on the third insulating film including respective insides of the plurality of the second wiring grooves and the plurality of the connection holes; and  
         [0035]     (m) removing the second conductive film lying outside the plurality of the second wiring grooves and the plurality of the connection holes to form the second Damascene wiring portion composed of the second conductive film in respective insides of the plurality of the first wiring grooves and the plurality of the connection holes.  
         [0036]     According to the present invention herein disclosed, advantages achieved by the representative embodiments will be summarized as follows.  
         [0037]     The present invention can provide a buried wiring portion in multiple layers having high reliable via connection and reduced parasitic capacitance due to an air-gap.  
         [0038]     Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING  
       [0039]      FIG. 1  is a longitudinal sectional view of a substantial portion of a semiconductor device of an example  1  of the present invention;  
         [0040]      FIG. 2  is a longitudinal sectional view illustrating issues of a buried wiring portion in multiple layers having a conventional air-gap structure;  
         [0041]      FIG. 3  is a longitudinal sectional view illustrating formation of a wiring layer in the semiconductor device of the example 1 according to the present invention for each of steps;  
         [0042]      FIG. 4  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0043]      FIG. 5  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0044]      FIG. 6  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0045]      FIG. 7  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0046]      FIG. 8  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0047]      FIG. 9  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0048]      FIG. 10  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0049]      FIG. 11  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 1 according to the present invention for each of the steps;  
         [0050]      FIG. 12 (A) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0051]      FIG. 12 (B) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0052]      FIG. 13 (A) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0053]      FIG. 13 (B) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0054]      FIG. 13 (C) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0055]      FIG. 14 (A) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0056]      FIG. 14 (B) is a longitudinal sectional view of the substantial portion of the semiconductor device of the example 1 of the present invention;  
         [0057]      FIG. 15  is a longitudinal sectional view of a substantial portion of a semiconductor device of an example 2 of the present invention;  
         [0058]      FIG. 16  is a longitudinal sectional view illustrating formation of a wiring layer in the semiconductor device of the example 2 according to the present invention for each of steps;  
         [0059]      FIG. 17  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 2 according to the present invention for each of the steps;  
         [0060]      FIG. 18  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 2 according to the present invention for each of the steps;  
         [0061]      FIG. 19  is a longitudinal sectional view of a substantial portion of the semiconductor device of the example 2 of the present invention;  
         [0062]      FIG. 20  is a longitudinal sectional view of a substantial portion of a semiconductor device of an example 3 of the present invention;  
         [0063]      FIG. 21  is a longitudinal sectional view illustrating formation of a wiring layer in the semiconductor device of the example 3 according to the present invention for each of processes;  
         [0064]      FIG. 22  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 3 according to the present invention for each of the steps; and  
         [0065]      FIG. 23  is a longitudinal sectional view illustrating the formation of the wiring layer in the semiconductor device of the example 3 according to the present invention for each of the steps. 
     
    
     DESCRIPTION OF REFERENCE NUMERALS  
       [0000]    
       
           1  . . . Semiconductor substrate  
           2  . . . Field insulating film  
           3  . . . Diffusion layer, Source region and drain region  
           4  . . . Gate electrode  
           5  . . . Side wall insulating film  
           6  . . . Interlayer insulating film  
           7  . . . Plug  
           8  . . . SiCN/SiC film  
           9  . . . FSG film, Insulating film  
           10  . . . Laminated single Damascene wiring portion, Single Damascene wiring portion  
           11  . . . SiLK film  
           12  . . . P-TEOS film  
           13  . . . Convex resist, Resist  
           14  . . . Sacrifice film pillar  
           15  . . . Partial film, FSG film  
           16  . . . Interlayer insulating film, FSG film  
           17  . . . Air-gap  
           18  . . . Interlayer insulating film  
           20  . . . Resist pattern, Resist  
           21  . . . Groove  
           22  . . . Connection hole  
           23  . . . Dual Damascene wiring portion  
           24  . . . Partial film of the interlayer insulating film  16   
           25  . . . Air-gap  
           26  . . . Interlayer insulating film  
           27  . . . Dual Damascene wiring portion  
           28  . . . Air-gap  
           29  . . . Interlayer insulating film  
           30  . . . Dual Damascene wiring portion  
           31  . . . Partial film of the interlayer insulating film  26   
           32  . . . CoWB alloyed film  
           33  . . . CoWB alloyed film  
           34  . . . Under part of the sacrifice film pillar  
           35  . . . Groove  
           36  . . . Connection hole  
           37  . . . P—SiN film  
           38  . . . SiN hard mask  
           39  . . . SiLK film  
           40  . . . P-TEOS film  
           41  . . . Convex resist, Resist  
           42  . . . Sacrifice film pillar  
           43  . . . Partial film of the insulating film, FSG film  
           44  . . . Interlayer insulating film  
           45  . . . Air-gap  
           46  . . . Via  
           47  . . . SiCN/SiC film  
           48  . . . FSG film  
           49  . . . Single Damascene wiring portion  
           50  . . . Interlayer insulating film  
           51  . . . CoWB alloyed film  
           52  . . . CoWB alloyed film  
           53  . . . Insulating film  
           54  . . . Interlayer insulating film  
           55  . . . Air-gap  
           56  . . . Via  
           57  . . . SiCN/SiC film  
           58  . . . FSG film  
           59  . . . Single Damascene wiring portion  
           60  . . . Sacrifice film pillar  
           61  . . . SiC film  
           62  . . . Porous SiOC film  
           63  . . . Air-gap  
           64  . . . Via  
           65  . . . Underlying buried wiring portion (single Damascene wiring portion)  
           66  . . . Via portion  
           67  . . . Air-gap  
       
     
       DETAILED DESCRIPTION OF THE INVENTION  
       [0132]     Now, the present invention will be explained in relation to examples according to the present invention with reference to the drawings. However, throughout the drawings for illustrating the examples, like components having like function will be denoted by like symbols, and the redundant explanation of them will be omitted. Also, in the examples described below, redundant explanation of the same or similar portions will not be in principle repeated other than particularly required.  
       EXAMPLE 1  
       [0133]      FIG. 1  is a cross sectional view of a substantial portion of a semiconductor device of an example 1 of the present invention.  
         [0134]     The main surface of a semiconductor substrate  1  is divided into each of element regions by a field insulating film  2 , and a diffusion layer  3  including a source region, drain region and the like is formed in each of the element regions. A gate electrode  4  composed of polycrystalline silicon is formed through a gate insulating film (not shown) between the regions of the source region and drain region  3  on the main surface of the semiconductor substrate  1 , and lateral sides of the gate electrode  4  are covered with a side wall insulating film  5 .  
         [0135]     The diffusion layer  3  or the gate electrode  4  formed on the main surface of the semiconductor substrate  1  is connected to one end of a plug  7  through an interlayer insulating film  6 , and the other end of the plug  7  is connected to a laminated single Damascene wiring portion  10  through the interlayer insulating film  6 . The interlayer insulating film  6  is formed by depositing a P—SiN film (50 nm), HDP—SiO film (400 nm) and P—SiO film (400 nm) in sequence, and subsequently by polishing by about 500 nm (an amount of polishing the large area of the wiring portion) using CMP technology to planarize a step between elements created by the gate electrode  4  and the like.  
         [0136]     The plug  7  is formed by depositing a titanium film (10 nm) and titanium nitride film (50 nm) by spattering and a tungsten film by CVD in sequence and processing by CMP.  
         [0137]     A single Damascene wiring portion  10  is formed by depositing a tantalum nitride film (15 nm), tantalum film (15 nm) and copper film (80 nm) by spattering and a copper film (500 nm) by plating in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and processing by CMP technology.  
         [0138]     A dual Damascene wiring portion  23  is connected to the single Damascene wiring portion  10  through an interlayer insulating film  16  having an air-gap  17  in a small space between adjacent single Damascene wiring portions  10 . At this time, a partial film  15  of the insulating film used at the time of forming the single Damascene wiring portion  10  remains under a via portion of the dual Damascene wiring portion  23  offset from the single Damascene wiring portion  10 .  
         [0139]     The dual Damascene wiring portions  23 ,  27  and  30 , similarly to the single Damascene wiring portion  10 , is formed by depositing a tantalum nitride film (15 nm), tantalum film (15 nm) and copper film (80 nm) by spattering and a copper film (500 nm) by plating in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and processing by CMP technology.  
         [0140]     The dual Damascene wiring portion  27  is connected to the dual Damascene wiring portion  23  through an interlayer insulating film  26  having an air-gap  25  in a small space between adjacent dual Damascene wiring portions  23 . At this time, a partial film  24  of the interlayer insulating film  16  remains under a via portion of the dual Damascene wiring portion  27  offset from the dual Damascene wiring portion  23 .  
         [0141]     The dual Damascene wiring portion  30  is connected to the dual Damascene wiring portion  27  through an interlayer insulating film  29  having an air-gap  28  in a small space between adjacent dual Damascene wiring portions  27 . At this time, a partial film  31  of the interlayer insulating film  26  remains under a via portion of the dual Damascene wiring portion  30  offset from the dual Damascene wiring portion  27 .  
         [0142]     In this example, issues of an increase in resistance due to a defectively buried metal in the via portion and an increase in parasitic capacitance due to an intrusion of metal into the air-gap can be avoided, because there is no contact between the via portion and the air-gap.  
         [0143]     Now, a method for producing a semiconductor device according to the example 1 will be explained for each of steps with reference to FIGS.  3  to  11 .  
         [0144]     First, after the main surface of a semiconductor substrate  1  is divided into each of element regions by a field insulating film  2 , a diffusion layer  3  including a source region, drain region and the like in each of the element regions, and a gate electrode  4  composed of polycrystalline silicon is formed through a gate insulating film (not shown) between the regions of the source region and drain region  3  on the main surface of the semiconductor substrate  1 , subsequently, lateral sides of the gate electrode  4  are covered with a side wall insulating film  5 .  
         [0145]     An interlayer insulating film  6  is formed by depositing a P—SiN film (50 nm), HDP—SiO film (400 nm) and P—SiO film (400 nm) in sequence, and subsequently by polishing by about 500 nm (an amount of polishing a large area gate) using CMP technology to planarize a step between elements created by the gate electrode  4  and the like.  
         [0146]     Next, after a connection hole is made by a normal photographic and drying technology, a naturally oxidized film on the bottom of the connection hole is removed by Ar plasma, subsequently a plug  7  is formed by depositing a Ti/TiN film  7   a  (10/50 nm) and a CVDW film  7   b  (300 nm) by spattering in sequence, and then, by removing the Ti/TiN film and the CVDW film except for those in the connection hole by CMP technology.  
         [0147]     Next, after depositing a SiCN/SiC film  8  (25/25 nm) and a FSG film  9  (a first insulating film) which is an inorganic insulating film (300 nm), a groove for forming a wiring portion  10  is formed by a normal photographic and drying technology.  
         [0148]     Next, after a naturally oxidized film on the surface of the plug  7  exposed on the bottom of the groove is removed by Ar plasma, a single Damascene wiring portion  10  is formed by depositing a tantalum nitride/tantalum film  10   a  (15/15 nm) by spattering which is a barrier metal film, and a copper film by spattering and a copper film by plating (a first conductive film)  10   b  (80/500 nm) which is a main conductive film in sequence, and then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and removing the tantalum nitride/tantalum/copper film except for those in the groove by CMP.  FIG. 3  shows these situations.  
         [0149]     Next, after depositing a SiLK film  11  (a second insulating film) (700 nm) which is an organic insulating film and a P-TEOS film  12  (100 nm), a convex resist  13  is formed. The resist  13 , which is columnar, is formed to cover a formation region of the connection hole for exposing the upper surface of the single Damascene wiring portion  10  to be formed in a later step.  FIG. 4  shows these situations.  
         [0150]     Next, a sacrifice film pillar  14  composed of the SiLK film is formed by etching the P-TEOS film  12  using the resist  13  as a mask, in succession, etching the SiLK film  11  using the resist  13  and P-TEOS film  12  as a mask. At this step, the P-TEOS film  12  on the surface of the SiLK film remains.  
         [0151]     Next, the FSG film  9  in a region not covered with the sacrifice film pillar is removed by etching the FSG film  9  in an anisotropic way between the single Damascene wiring portions  10 . At this time, a part of the FSG film  9  lying under the sacrifice film pillar  14  remains to form a FSG film  15 .  FIG. 5  shows these situations.  
         [0152]     Next, a FSG film  16  (a third insulating film) (1200 nm), which is an inorganic insulating film, is formed. At this time, the FSG film  16  is formed by depositing using the CVD method under a low coverage formation condition so that an air-gap  17  is formed in a small space between adjacent the single Damascene wiring portions  10 . Alternately, the FSG film  16  may be formed by depositing using CVD method in such a manner that during an initial formation step, a low coverage formation condition is used to form the air-gap  17  and after the air-gap  17  is formed, a high coverage condition is used to bury a space between the sacrifice film pillars  14 . Further, it is necessary to deposit to such a film thickness that the surface of the FSG film  16  is higher than the upper surface of the sacrifice film pillar  14 .  FIG. 6  shows these situations.  
         [0153]     Next, the surface of the FSG film  16  is planarized by CMP to expose the surface of the sacrifice film pillar  14 , and to form an interlayer insulating film  18  for forming a dual Damascene wiring portion composed of the FSG film. At this step, the P-TEOS film  12  is not left behind on the surface of the sacrifice film pillar  14 .  FIG. 7  shows these situations.  
         [0154]     Next, a resist pattern  20  for forming the dual Damascene wiring portion is formed.  FIG. 8  shows these situations.  
         [0155]     Next, a groove  21  for wiring of the dual Damascene wiring portion is formed by etching the sacrifice film pillar  14  and interlayer insulating film  18  at an approximately similar etching rate for both of them using the resist pattern  20  as a mask.  FIG. 9  shows these situations.  
         [0156]     Next, a connection hole  22  for a via portion of the dual Damascene wiring portion is formed by selectively removing the sacrifice film pillar  14  using NH3 plasma.  FIG. 10  shows these situations.  
         [0157]     Next, after removing and cleaning etching polymer, similarly to the formation of the single Damascene wiring portion  10 , a naturally oxidized film on the surface of the single Damascene wiring portion  10  exposed on the bottom of the connection hole  22  is removed by Ar plasma, subsequently a dual Damascene wiring portion  23  is formed by depositing a tantalum nitride/tantalum film  23   a  (15/15 nm) by spattering which is a barrier metal film, and a copper film by spattering and a copper film by plating (a second conductive film)  23   b  (80/500 nm) which is a main conductive film in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and by removing the tantalum nitride/tantalum/copper film except for those in the connection hole  22  and the groove  21  by CMP technology.  FIG. 11  shows these situations.  
         [0158]     The situations shown in  FIG. 1  illustrates the dual Damascene wiring portion in multiple layers in which air-gaps  25 ,  28  are formed between adjacent dual Damascene wiring portions  23  and also in a small space between dual Damascene wiring portions  27  by repeating the above steps.  
         [0159]     In the example described above, the example using Cu for the main conductive film for the single Damascene wiring portion  10  or the dual Damascene wiring portion  23  has been shown, but not to be limited to this, at least any one of metals including Al, W, Ag and Au may be used as the main conductive film.  
         [0160]     In this example, a stable connection of the via to the underlying Damascene wiring portion having the air-gap structure can be achieved, because the air-gap to be disposed between adjacent Damascene wiring portions can be formed apart from the via portion due to the formation of the sacrifice film pillar, and so contact between the air-gap and the via portion dose not occur even if misalignment is caused.  
         [0161]     In the example described above, improvement in reliability of the Damascene wiring portions  10 ,  23  and the like can be achieved, after forming the Damascene wiring portions  10 ,  23 , by selectively forming a CoWB alloyed films  32 ,  33  as a metal cap film on the surface of the Damascene wiring portions. However, not to be limited to the CoWB alloyed film, at least any one of metals and metallic compounds including Co, W, Ni, Cr and Au may be used as the metal cap film. FIGS.  12 (A), (B) show these situations.  
         [0162]     Also, in the example described above, as shown in  FIG. 9 , the groove  21  for wiring of the dual Damascene wiring portion  23  is formed by etching the sacrifice film pillar  14  and the interlayer insulating film  18  at an approximately like etching rate, but, as shown in FIGS.  13 (A) to (C), also, after only an upper part of the sacrifice film pillar  14  is etched back to near a depth of the groove, a groove  35  may be formed in the interlayer insulating film  18 . Next, a connection hole  36  is formed by selectively removing an under part  34  of the sacrifice film pillar. This method is useful for a case where it is difficult to etch the sacrifice film pillar  14  and the interlayer insulating film  18  at the approximately like etching rate.  
         [0163]     Moreover, in the groove processing shown in  FIG. 9  or  FIG. 13 (B), there may be an insufficient resist  20 , then, as shown in  FIG. 14 , a SiN hard mask  38  is formed from an additional P—SiN film  37 , and the groove may be also processed by using this mask as a mask.  
       EXAMPLE 2  
       [0164]      FIG. 15  is a cross sectional view of a substantial portion of a semiconductor device of an example 2 of the present invention.  
         [0165]     The main surface of a semiconductor substrate  1  is divided into each of element regions by a field insulating film  2 , and a diffusion layer  3  including a source region, drain region and the like is formed in each of the element regions. A gate electrode  4  composed of polycrystalline silicon is formed through a gate insulating film (not shown) between the regions of the source region and drain region  3  on the main surface of the semiconductor substrate  1 , and lateral sides of the gate electrode  4  are covered with a side wall insulating film  5 .  
         [0166]     The diffusion layer  3  or the gate electrode  4  formed on the main surface of the semiconductor substrate  1  is connected to one end of a plug  7  through an interlayer insulating film  6 , and the other end of the plug  7  is connected to a laminated single Damascene wiring portion  10  through the interlayer insulating film  6 . The interlayer insulating film  6  is formed by depositing a P—SiN film (50 nm), HDP—SiO film (400 nm) and P—SiO film (400 nm) in sequence, and subsequently by polishing by about 500 nm (an amount of polishing the large area of the wiring portion) using CMP technology to planarize a step between elements created by the gate electrode  4  and the like.  
         [0167]     The plug  7  is formed by depositing a titanium film (10 nm) and titanium nitride film (50 nm) by spattering, and a tungsten film by CVD in sequence and working using CMP.  
         [0168]     The single Damascene wiring portion  10  is formed by depositing a tantalum nitride film (15 nm), tantalum film (15 nm) and copper film (80 nm) by spattering and a copper film (500 nm) by plating in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and working using CMP technology.  
         [0169]     A single Damascene wiring portion  49  is connected to the single Damascene wiring portion  10  through a via  46  passing through a interlayer insulating film  50  having an air-gap  45  in a small space between adjacent single Damascene wiring portions  10 . At this time, a partial film  43  of the insulating film used at the time of forming the single Damascene wiring portion  10  remains under a via  46  offset from the single Damascene wiring portion  10 .  
         [0170]     In this example, issues of an increase in resistance due to a defectively buried metal in the via and an increase in parasitic capacitance due to an intrusion of metal into the air-gap can be avoided, because there is no contact between the via and the air-gap.  
         [0171]     Now, a method for producing a semiconductor device according to the example 2 will be explained for each of steps with reference to FIGS.  16  to  18 .  
         [0172]     First, after the steps of the example 1 shown in  FIG. 3 , and after depositing a SiLK film (a second insulating film)  39  (400 nm) which is an organic insulating film and a P-TEOS film  40  (100 nm), a convex resist  41  is formed. The resist  41 , which is columnar, is formed to cover a formation region of a connection hole for exposing the upper surface of the single Damascene wiring portion  10  to be formed in a later step.  FIG. 16  shows these situations.  
         [0173]     Next, a sacrifice film pillar  42  composed of the SiLK film is formed by etching the P-TEOS film  40  using the resist  41  as a mask, and in succession, by etching the SiLK film  39  using the resist  41  and P-TEOS film  40  as a mask. At this step, The P-TEOS film  40  on the surface of the SiLK film remains.  
         [0174]     Next, a FSG film  9  in a region not covered with the sacrifice film pillar is removed by etching the FSG film  9  in an anisotropic way between the single Damascene wiring portions  10 . At this time, a part of the FSG film  9  under the sacrifice film pillar  42  remains to form a FSG film  43 .  
         [0175]     Next, a FSG film (a third insulating film) (800 nm), which is an inorganic insulating film, is formed. At this time, the FSG film is formed by depositing using CVD method under a low coverage formation condition so that an air-gap  45  is formed in a small space between adjacent the single Damascene wiring portions  10 . Alternately, the FSG film may be formed by depositing using CVD method in such a manner that during an initial formation step, a low coverage formation condition is used to form the air-gap  45  and after the air-gap  45  is formed, a high coverage formation condition is used to bury a space between the sacrifice film pillars  42 . Further, it is necessary to deposit to such a film thickness that the surface of the FSG film is higher than the upper surface of the sacrifice film pillar  42 .  
         [0176]     Next, the surface of the FSG film is planarized by CMP to expose the surface of the sacrifice film pillar  42 , and to form an interlayer insulating film  44  for forming a via composed of the FSG film.  FIG. 17  shows these situations.  
         [0177]     Next, a connection hole which reaches the single Damascene wiring portion  10  is made by selectively removing the sacrifice film pillar  42  using NH3 plasma.  
         [0178]     Next, after removing and cleaning etching polymer, a naturally oxidized film on the surface of the single Damascene wiring portion  10  exposed on the bottom of the connection hole is removed by Ar plasma, subsequently a via  46  is formed by depositing a tantalum nitride/tantalum film (15/15 nm) by spattering which is a barrier metal film, and a copper film by spattering and a copper film by plating (a second conductive film) (80/500 nm) which is a main conductive film in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and by removing the tantalum nitride/tantalum/copper film except for those in the connection hole by CMP technology.  FIG. 18  shows these situations.  
         [0179]     Now,  FIG. 15  referred to above shows that by using the same method for forming the single Damascene wiring portion  10 , a groove is formed after depositing a SiCN/SiC film  47  and a FSG film  48  which is an inorganic insulating film, then in this groove, a single Damascene wiring portion  49  is formed.  
         [0180]     However, not shown, a Damascene wiring portion having three or more layers may be also formed by repeating the steps described above.  
         [0181]     In the embodiment described above, the example using Cu for the main conductive film for the single Damascene wiring portions  10 ,  49  or the via  46  has been shown, but not to be limited to this, at least any one of metals including Al, W, Ag and Au may be used as the main conductive film.  
         [0182]     In this example, a stable connection of the via to the underlying Damascene wiring portion having the air-gap structure can be achieved, because the air-gap formed between adjacent Damascene wiring portions can be formed apart from the via due to the formation of the sacrifice film pillar, and so contact between the air-gap and the via dose not occur even if misalignment or the like is caused.  
         [0183]     Further, in the example described above, after forming the Damascene wiring portions  10 ,  49  and the like, improvement in reliability of the Damascene wiring portions  10 ,  49  and the like can be achieved by selectively forming CoWB alloyed films  51 ,  52  as a metal cap film on the surface of the Damascene wiring portions. However, not to be limited to the CoWB alloyed film described above, at least any one of metals and metallic compounds including Co, W, Ni, Cr and Au may be used as the metal cap film.  FIG. 19  shows these situations.  
         [0184]     However, not shown, a CoWB alloyed film may be also formed on the surface of the via  46 .  
         [0185]     Moreover, as shown in  FIG. 14 , a hard mask processing using a P—SiN film may be also applicable.  
       EXAMPLE 3  
       [0186]      FIG. 20  is a cross sectional view of a substantial portion of a semiconductor device of an example 3 of the present invention.  
         [0187]     The main surface of a semiconductor substrate  1  is divided into each of element regions by a field insulating film  2 , and a diffusion layer  3  including a source region, drain region and the like is formed in each of the element regions. A gate electrode  4  composed of polycrystalline silicon is formed through a gate insulating film (not shown) between the regions of the source region and drain region  3  on the main surface of the semiconductor substrate  1 , and lateral sides of the gate electrode  4  are covered with a side wall insulating film  5 .  
         [0188]     The diffusion layer  3  or the gate electrode  4  formed on the main surface of the semiconductor substrate  1  is connected to one end of a plug  7  through an interlayer insulating film  6 , and the other end of the plug  7  is connected to a laminated single Damascene wiring portion  10  through the interlayer insulating film  6 . The interlayer insulating film  6  is formed by depositing a P—SiN film (50 nm), HDP—SiO film (400 nm) and P—SiO film (400 nm) in sequence, and subsequently by polishing by about 500 nm (an amount of polishing the large area of the wiring portion) using CMP technology to planarize a step between elements created by the gate electrode  4  and the like.  
         [0189]     The plug  7  is formed by depositing a titanium film (10 nm) and titanium nitride film (50 nm) by spattering and a tungsten film by CVD in sequence, and subsequently by processing by CMP.  
         [0190]     The single Damascene wiring portion  10  is formed by depositing a tantalum nitride film (15 nm), tantalum film (15 nm) and copper film (80 nm) by spattering, and a copper film (500 nm) by plating in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and working by CMP technology.  
         [0191]     A single Damascene wiring portion  59  is connected to the single Damascene wiring portion  10  through a via  56  passing through a interlayer insulating film  54  having an air-gap  55  in a small space between adjacent single Damascene wiring portions  10 . At this time, a partial film  43  of the insulating film  9  used at the time of forming the single Damascene wiring portion  10  remains under the via  56  offset from the single Damascene wiring portion  10 .  
         [0192]     Also, an insulating film  53  intervenes between the interlayer insulating film  54 , and the single Damascene wiring portion  10  and the via  56 .  
         [0193]     In this example, issues of an increase in resistance due to a defectively buried metal in the via and an increase in parasitic capacitance due to an intrusion of metal into the air-gap can be avoided, because there is no contact between the via and the air-gap.  
         [0194]     Now, a method for producing a semiconductor device according to the example 3 will be explained for each of steps with reference to FIGS.  21  to  23 .  
         [0195]     After the steps of the example 2 shown in  FIG. 16 , a sacrifice film pillar  60  composed of the SiLK film is formed by etching the P-TEOS film  40  using the resist  41  as a mask and etching the SiLK film  39  using the resist  41  and P-TEOS film  40  as a mask. At this step, the P-TEOS film  40  on the surface of the SiLK film remains.  
         [0196]     Next, the FSG film  9  in a region not covered with the sacrifice film pillar is removed by etching the FSG film  9  in an anisotropic way between the single Damascene wiring portions  10 . At this time, a part of the FSG film  9  under the sacrifice film pillar  60  remains to form a FSG film  43 .  
         [0197]     Next, a SiC film  61  (10 nm) and porous SiOC film (a third insulating film)  62  (800 nm) are deposited.  FIG. 21  shows these situations. At this time, during an initial formation of the porous SiOC film  62 , deposition is performed under a low coverage formation condition so that an air-gap  63  is formed in a small space between adjacent single Damascene wiring portions  10 . Further, it is necessary to deposit to such a film thickness that the surface of the porous SiOC film  62  is higher than the upper surface of the sacrifice film pillar  60 .  
         [0198]     Next, the porous SiOC film  62  and SiC film  61  are planarized by CMP to expose the surface of the sacrifice film pillar  60 .  FIG. 22  shows these situations. The SiC film  61  on the surface of the sacrifice film pillar  60  may be removed by CMP or selectively etching.  
         [0199]     Next, a connection hole which reaches the single Damascene wiring portion  10  is formed by selectively removing the sacrifice film pillar  60  using NH3 plasma.  
         [0200]     Next, after cleaning etching polymer, a naturally oxidized film on the surface of the single Damascene wiring portion  10  exposed on the bottom of the connection hole is removed by Ar plasma, subsequently a via  64  is formed by depositing a tantalum nitride/tantalum film (15/15 nm) by spattering which is a barrier metal film, and a copper film by spattering and a copper film by plating (a second conductive film) (80/500 nm) which is a main conductive film in sequence, then by heat-treating for 2 min at 400° C. in a hydrogen atmosphere and removing the tantalum nitride/tantalum/copper film except for those in the connection hole by CMP technology.  FIG. 23  shows these situations.  
         [0201]     Next,  FIG. 20  referred to above shows situations that by using the same method for forming the single Damascene wiring portion  10 , after depositing a SiCN/SiC film  57  and a FSG film  58  which is an inorganic insulating film, a groove is formed, then in this groove, a single Damascene wiring portion  59  is formed.  
         [0202]     However, not shown, a Damascene wiring portion having three or more layers may be also formed by repeating the steps described above.  
         [0203]     In this example, a stable connection of the via to the underlying Damascene wiring portion having the air-gap structure can be achieved, because the air-gap to be disposed between adjacent Damascene wiring portions can be formed apart from the via due to the formation of the sacrifice film pillar, and so contact between the air-gap and the via portion dose not occur even if misalignment or the like is caused.  
         [0204]     Moreover, because of a structure in which the via  64  will not contact directly with the porous SiOC film  62 , a defect of via poisoning due to gas seeping from the porous SiOC film  62  can be prevented.  
         [0205]     Further, a formation of the cap metal film on the surface of the Damascene wiring portion, a hard mask processing and the like will not be described, but it is certain that these may be also applicable, similarly to the examples 1 and 2.  
         [0206]     Although the present invention made by the present inventors has been specifically explained in relation to the examples above, the present invention is not intended to be limited to the examples above and it is certain that various modifications may be made without departing from the spirit and scope of the present invention.  
         [0207]     For example, the gate electrode is not to be limited to polysilicon, and the present invention can be implemented by using a silicide gate electrode employing Ti or Co.  
         [0208]     It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.