Abstract:
A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a divisional of U.S. patent application Ser. No. 12/625,827, filed Nov. 25, 2009, the disclosure of which is incorporated by reference herein in its entirety. 
     
    
     BACKGROUND 
       [0002]    The present invention relates to semiconductor structures, and more specifically, to the formation of a planar metal oxide semiconductor field-effect transistor (MOSFET) structure with high electron mobility using channel engineering. 
         [0003]    To enhance the performance of MOS devices, stress may be introduced in the channel region of the MOSFET to improve carrier mobility. It is desirable to induce a tensile stress in the channel region of an n-type metal oxide semiconductor (NMOS) device in a source-to-drain direction, and a compressive stress in the channel region of a p-type metal-oxide-semiconductor (PMOS) device in a source-to-drain direction. 
         [0004]    Current n-FET High-k/Metal-Gate (HKMG) technology utilizes a silicon nitride stress liner on top of silicon surfaces to achieve higher electron mobility. Aggressive PC pitch and height scaling in advanced complementary metal oxide semiconductor (CMOS) technologies result in lower benefits from the use of stress liners. Therefore, embedded stress elements are being used in place of the stress liners. 
         [0005]    Embedded silicon germanium (SiGe) is used to improve performance of the PMOS device. Embedded silicon carbon can be used to improve performance of the NMOS device. By introducing embedded stress elements, the channel stress can be further enhanced thereby resulting in even higher drive currents.  FIG. 1  is a diagram of an NMOS device. As shown in  FIG. 1 , the MOS device  10  includes a gate stack  13  on a silicon substrate  12 . The gate stack  13  includes a gate electrode  14  disposed on a gate dielectric  16 . A polysilicon layer  17  and a silicide layer  18  are formed over the gate electrode  14 . The MOS device  10  further includes spacers  19   a  and  19   b  and  20   a  and  20   b  on sidewalls of the gate stack  13 , and source and drain regions  21  and  22 . One conventional method includes epitaxially growing silicon carbon (SiC) stressors  23  and  24  in the source and drain regions  21  and  22 , therefore tensile stress is applied to a channel region  25  between the source SiC stressor  23  and the drain SiC stressor  24 . Improvement in performance of the NMOS device is more difficult to achieve due to challenging process integration when using silicon carbon (SiC) and the improvement is limited due to the fact that the source SiC stressor  23  and the drain SiC stressor  24  are away from the inversion layer directly under gate dielectric  16 ; therefore the use of an embedded stressor near the inversion layer within NMOS devices would be more desirable to gain performance improvement. 
       SUMMARY 
       [0006]    In one embodiment, a semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape. 
         [0007]    According to another embodiment, a semiconductor structure includes a semiconductor substrate; and a metal oxide semiconductor (MOS) device including a gate stack on the semiconductor substrate, a plurality of spacers disposed on laterally opposing sides of the gate stack, source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions, and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape. 
         [0008]    Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0009]    The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0010]      FIG. 1  is a diagram illustrating a conventional NMOS device having source and drain silicon carbon (SiC) stressors. 
           [0011]      FIG. 2A through 2C  are diagrams illustrating fabrication operations for forming an embedded stressor that can be implemented within embodiments of the present invention. 
           [0012]      FIGS. 3A through 3C  are diagrams illustrating fabrication operations for forming a semiconductor layer over the embedded stressor shown in  FIGS. 2B and 2C  that can be implemented within embodiments of the present invention. 
           [0013]      FIG. 4  is a diagram illustrating a semiconductor structure having an embedded stressor that can be implemented within embodiments of the present invention. 
           [0014]      FIGS. 5A through 5F  are graphs illustrating stress effect of the embedded stressor shown in  FIG. 4  that can be implemented within embodiments of the present invention compared to that of the conventional art. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    The present invention provides an embedded triangular-shaped stressor within a semiconductor substrate which is used to enhance channel mobility within NMOS devices of a semiconductor structure. 
         [0016]    A fabrication method of an embedded stressor within a semiconductor structure will now be described with reference  FIGS. 2A through 2C .  FIG. 2A  is a diagram illustrating an initial fabrication operation of the embedded stressor according to an embodiment of the present invention. As shown in  FIG. 2A , a substrate  50  of stressor material is provided. The substrate  50  includes sidewall portions  50   a  and  50   b . According to an embodiment of the present invention, the stressor material is silicon germanium (SiGe). According to one embodiment of the present invention, the Ge concentration in the SiGe may be about 25%. However, the stressor material may vary as necessary. For example, the stressor material may be SiGe or SiGeC. 
         [0017]    A dummy gate stack  52  is formed over the substrate  50 . The dummy gate stack  52  may include an insulating layer  54  formed of silicon oxynitride (SiON), for example, and a gate electrode  55 . The dummy gate stack  52  is used to first form an embedded stressor (as depicted in  FIG. 2B ) and is then replaced by a functional gate stack during a replacement gate process after the subsequent processing operations have been completed. 
         [0018]      FIG. 2B  is a diagram illustrating an etching operation of the stressor material that can be implemented within embodiments of the present invention. As shown in  FIG. 2B , according to one embodiment, the sidewall portions  50   a  and  50   b  of the substrate  50  subjacent to the dummy gate stack  52  are anistropically etched to form an embedded stressor  60 . Any conventional etching process may be performed. According to an embodiment of the present invention, anistropically etching of the sidewall portions  52   a  and  52   b  forms a triangular-shaped embedded stressor  60 . The anistropic etching process is carried out using the dummy gate stack  52  as a mask to pattern the substrate  50 . According to one embodiment of the present invention, the anisotropic etching of the substrate  50  is carried out by using one or more dry-etching processes, such as reactive ion etching (RIE). The dry etching is directional and therefore etches the stressor material in approximately equal rates along each sidewall portion  50   a  and  50   b.  The pyramidal shape is formed by wet etching which preferentially etches &lt;111&gt; crystallographic plane relative to the &lt;100&gt; plane. The stressor  60  contains SiGe, and therefore, tensile stress is created in the channel region (as depicted in  FIG. 4 ). Therefore, the semiconductor structure is suitable for forming an n-channel in an NMOS device and enhances electron mobility. 
         [0019]    After etching, the embedded stressor  60  includes angled sidewall portions  62   a  and  62   b  each formed of a predetermined fixed angle a. According to an embodiment of the present invention, the predetermined fixed angle a ranges from approximately 50 degrees to approximately 57 degrees. Further, a top portion  62   c  of the embedded stressor is a predetermined distance from a gate stack of the MOS device (as depicted in  FIG. 4 ). The predetermined distance ranges from about 5 nanometers (nm) to about 20 nanometers (nm). According to one embodiment of the present invention, the predetermined distance is about 8 nanometers (nm). Further, according to an embodiment of the present invention, the embedded stressor 60 may be formed of a height h ranging from about 60 nanometers (nm) to about 100 nanometers (nm). 
         [0020]      FIG. 2C  is a diagram illustrating a cross-sectional view taken along I-I of  FIG. 2B . As shown in  FIG. 2C , according to an embodiment of the present invention, at least one shallow trench isolation (STI) region  64  adjoins the embedded stressor  60 . 
         [0021]    After forming the embedded stressor  60 , additional fabrication processes are performed as shown in  FIGS. 3A through 3C  discussed below. 
         [0022]      FIG. 3A  is a diagram illustrating a deposition operation of a semiconductor layer that can be implemented within embodiments of the present invention.  FIG. 3B  is a cross-section view taken along II-II of  FIG. 3A . As shown in  FIGS. 3A and 3B , a conductive material  66  is epitaxially grown on the angled sidewall portions  62   a  and  62   b  and the top portion  62   c  of the embedded stressor  60 . Alternatively, the conductive material  66  may be deposited via other conventional deposition techniques. According to one embodiment of the present invention, the conductive material  66  is formed of silicon (Si). However, the present invention is not limited to silicon (Si) and may vary as necessary. Alternatively, the conductive material  66  may be semiconductor material with smaller lattice size than that of the embedded stressor  60 . For example, it may be SiGe with lower Ge concentration. 
         [0023]      FIG. 3C  is a diagram illustrating a planarizing operation of the conductive material that can be implemented within embodiments of the present invention. As shown in  FIG. 3C , after deposition of the conductive material  66 , the dummy gate stack  52  is removed. Further, the conductive material  66  is planarized by a planarization technique such as chemical mechanical polishing (CMP) however other conventional planarization techniques may be performed. Therefore, a semiconductor layer  67  formed of conductive material  66  overlies the embedded stressor  60 . Additional CMOS processing operations, such as source/drain extension implantation, source/drain implantation, can be further carried out to form a complete semiconductor device (as depicted in  FIG. 4 ), which contains a channel region with the desired stress. 
         [0024]      FIG. 4  is a diagram illustrating a semiconductor structure including an embedded stressor that can be implemented within embodiments of the present invention. As shown in  FIG. 4 , a semiconductor structure  100  is provided. The semiconductor structure  100  includes a gate stack  80  including a gate dielectric  82  and a gate electrode  84  formed over the gate dielectric  82 . A polysilicon layer  86  is formed over the gate electrode  84  and a silicide layer  88  is formed over the polysilicon layer  86 . Spacers  90   a  and  90   b  are formed along sidewalls of the gate electrode  84  to protect the gate electrode  84 . The spacers  90   a  and  90   b  may be formed of silicon oxide or silicon nitride, for example. Further, spacers  92   a  and  92   b  are provided to be electrically conductive. As shown in  FIG. 4 , the spacers  90   a,    90   b,    92   a  and  92   b  are formed on laterally opposite sides of the gate electrode  84 . Using the spacers  92   a  and  92   b  and the silicide layer  88  as a mask, recesses are formed by implant to create source and drain regions  94  and  96  in the semiconductor layer  67 . The implant may be a conventional source/drain extension implant using arsenic for N channel transistor. The semiconductor structure  100 , further includes the embedded stressor  60  formed over a semiconductor substrate  110  that provides physical support for the semiconductor structure  100  and an insulating layer  112 . The semiconductor substrate  110 , the insulating layer  112  and the semiconductor layer  67  together may formed a semiconductor-on-insulator (SOI) substrate. A bulk substrate may be used instead. 
         [0025]    The gate dielectric  82  may be formed of commonly used dielectric materials such as oxides, nitrides, oxynitrides, oxycarbides, carbonitrides, combinations thereof, and multi-layers thereof. The gate electrode  84  may be formed of commonly used conductive materials, such as doped polysilicon, metals, metal silicides, metal nitrides, and the like. According to another embodiment of the present invention, the gate dielectric  82  may be a high-k dielectric formed by depositing high-k material and etching the material to form the high-k dielectric. Further, the gate electrode  84  may be a metal gate electrode. 
         [0026]      FIGS. 5A through 5F  are graphs illustrating stress effect of the embedded stressor shown in  FIG. 4  that can be implemented within embodiments of the present invention compared to that of the conventional art. According to one embodiment of the present invention, the effective stress may be calculated by using equation (1): 
         [0000]        Seff=Sxx− 1.6* Syy+ 0.7* Szz    
         [0027]    Wherein Sxx represents stress level in the x-direction (i.e., source-to-drain direction; Syy represents stress level in the y-direction (i.e., a direction vertical to the surface of the semiconductor layer  67 ); and Szz represents stress level in the z-direction (i.e., a width direction).  FIGS. 5A ,  5 C and  5 E are  2 -D stress profiles for each stress component.  FIG. 5A  is for stress in the Sxx orientation,  FIG. 5C  is for stress in the Syy orientation, and  FIG. 5E  is for stress in the Szz orientation. While  FIGS. 5B ,  5 D, and  5 F are taken at 2 nm below surface to get a numeric idea. Further shown in the graphs of  FIG. 5B ,  5 D and  5 F, the line indicated by reference numeral  200  represents the stress level of the present invention and the line indicated by reference numeral  300  represents the stress level of the conventional art. 
         [0028]      FIGS. 5A and 5B  are a diagram and graph respectively illustrating the stress level in the x-direction (Sxx). As shown in  FIG. 5B , the line  200  shows a significant increase in the stress level at approximately 2 nanometers (nm) below a surface of the semiconductor layer 67 in the present invention compared to that of the conventional art. For example, as shown, the stress level in the center of the channel region is approximately 3.1 GPa for the present invention compared to approximately 0.28 GPa for the conventional art. 
         [0029]      FIGS. 5C and 5D  are a diagram and graph respectively illustrating the stress level in the y-direction (Syy) at approximately 2 nanometers (nm) below a surface of the semiconductor layer  67 . As shown in  FIG. 5D , the stress level at 0.065 micros is approximately −200 MPa for the present invention compared to approximately −250 MPa for the conventional art. 
         [0030]      FIGS. 5E and 5F  are a diagram and graph respectively illustrating the stress level in the z-direction (Szz) level at approximately  2  nanometers (nm) below a surface of the semiconductor layer  67 . As shown in  FIG. 5F , the stress level in the center channel region at 0.065 microns is 5 GPa for the present invention compared to 0 GPa for the conventional art. 
         [0031]    According to the current embodiment of the present invention,  FIGS. 5A through 5F  are the stress level from TCAD simulation to illustrate the present invention. These simulations are generated based on embedded SiGe with 25% Ge. 
         [0032]    Embodiments of the present invention include an embedded SiGe stressor which provides higher drive currents over the current HKMG technology and enhances electron mobility. 
         [0033]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one ore more other features, integers, steps, operations, element components, and/or groups thereof. 
         [0034]    The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated 
         [0035]    The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
         [0036]    While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.