Abstract:
An orthogonal frequency division multiplexing (OFDM)-based synchronization detection apparatus including a 2 n  level quantizing unit quantizing received data samples into levels of 2 n , where n is an integer greater than or equal to zero (0), and a delaying unit delaying the data samples quantized through the 2 n  level quantizing unit by a predetermined number of clocks and outputting data indicative thereof. A shifting unit shifts the output data samples of the 2 n  level quantizing unit by an amount corresponding to an exponent of the output data of the delaying unit and a peak detecting unit detects a peak value from sums of outputs from the shifting unit.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
         [0001]    This application claims the priority of Korean Patent Application No. 2002-68761, filed on Nov. 7, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
         BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a method and apparatus for detecting synchronization at a receiving stage of an orthogonal frequency division multiplexing (OFDM) transmission system, and more particularly, to a method and apparatus of detecting a synchronization using samples quantized in 2 n  levels.  
           [0004]    2. Description of the Related Art  
           [0005]    An orthogonal frequency division multiplexing (OFDM) system used in European digital video broadcasting for television (DVB-T), digital audio broadcasting (DAB), and high-speed wireless local area network (WLAN) systems synchronize a timing by detecting an offset in the timing of a received frame using a correlation between a received frame signal and a cyclic prefix signal for a frame.  
           [0006]    [0006]FIG. 1 shows a transmission data format used in the European DVB-T system. Transmission data  100  includes a first cycle prefix  110 , data  120 , a second cycle prefix  140 , and data  150 . The first cycle prefix  110  is a copy of a portion  130  (i.e., duplication data) of the data  120 , and the second cycle prefix  140  is a copy of a portion  160  of the data  150 . The term “cycle prefix” is a duplicate portion of the transmission data  100  used for a purpose of detecting synchronization. When the cycle prefix is included in a data frame at a transmitting stage, a starting point of the data can be detected at a receiving stage using the cycle prefix.  
           [0007]    [0007]FIG. 2 is a block diagram of a conventional correlation system for detecting a synchronization of the timing. Referring to FIG. 2, the correlation system  200  includes a delaying unit  210  delaying received input data samples by N clocks, a complex conjugate extracting unit  220  extracting complex conjugates of outputs of the delaying unit  210 , a multiplying unit  230  multiplying outputs of the complex conjugate extracting unit  220  by the received input data samples, an integer extracting unit  240  extracting only integer parts from outputs of the multiplying unit  230 , a moving sum calculating unit  250  summing up consecutive L outputs of the integer extracting unit  240  at every clock, and a peak detecting unit  260  detecting a maximum value among outputs of the moving sum calculating unit  250  and determining the synchronization of timing.  
           [0008]    The moving sum calculating unit  250  calculates correlation values according to the following equation:  
               Λ        (   n   )       =       ∑     k   =   1       n   +   L              r        (   k   )              r   *          (     k   -   N     )                   (   1   )                               
 
           [0009]    where r(k) is a received signal sampled with a baseband frequency, N is a size of input data for Digital Fourier Transform (DFT) used in the OFDM system, and r*(k-N) is complex conjugate data of r(k) delayed by N clocks. Among the calculated correlation values Λ(n), a maximum correlation value Λ max (n) represents a correlation peak, and based upon whether and where the correlation peak is detected, the timing is synchronized.  
           [0010]    That is, in the transmission data shown in FIG. 1, there is a time delay of N clocks between the first cycle prefix data  110  and the duplication data  130  thereof. Therefore, if the correlation system  200  shown in FIG. 2 delays the received input data samples by N clocks, the data interval between every other cycle prefix can be spaced, and if the received input data sample refers to the cycle prefix, the moving sum calculating unit  250  outputs a maximum value because the cycle prefix and the duplication data  130  thereof are the same data. In this way, the correlation system shown in FIG. 2 can detect the synchronization of timing.  
           [0011]    [0011]FIG. 3 is a block diagram of another conventional correlation system to detect the synchronization of the timing. Referring to FIG. 3, the correlation system  300  includes a sign bit quantizing unit  310  for quantizing input data using only sign bits of the input data, i.e., quantizing input signals as +1 if the input signals are greater than zero, or otherwise, as −1, a delaying unit  320  for delaying outputs of the sign bit quantizing unit  310  by N clocks, a complex conjugate extracting unit  330  for extracting complex conjugates of outputs of the delaying unit  320 , and a multiplying unit  340  for multiplying outputs of the complex conjugate extracting unit  330  by the outputs of the sign bit quantizing unit  310 . The correlation system  300  also includes an integer extracting unit  350  for extracting only integer parts from outputs of the multiplying unit  340 , a moving sum calculating unit  360  for summing up consecutive L outputs of the integer extracting unit  350  at every clock, and a peak detecting unit  370  for detecting a maximum value among outputs of the moving sum calculating unit  360  and determining the synchronization of timing.  
           [0012]    The conventional correlation systems described above require multiplying units for obtaining correlation values. However, because the circuit configurations for the multiplying units are very complex, the conventional correlation systems have disadvantageously complex hardware structures.  
         SUMMARY OF THE INVENTION  
         [0013]    The present invention provides an orthogonal frequency division multiplexing (OFDM)-based synchronization detection apparatus and method with a simplified hardware structure and undiminished synchronization detection performance.  
           [0014]    According to an aspect of the present invention, there is provided an OFDM-based synchronization detection apparatus, which includes a 2 n  level quantizing unit quantizing received data samples into levels of 2 n , where n is an integer greater than or equal to zero (0); a delaying unit delaying the data samples quantized through the 2 n  level quantizing unit by a predetermined number of clocks and outputting data indicative thereof; a shifting unit shifting the output data samples of the 2 n  level quantizing unit by an amount corresponding to an exponent of the output data of the delaying unit; and a peak detecting unit detecting a peak value from sums of outputs from the shifting unit.  
           [0015]    In the OFDM-based synchronization detection apparatus, according to an aspect of the present invention, the 2 n  level quantizing unit proportionally magnifies the received data samples by values of 2 n , and converges the proportionally magnified data samples to levels of 2 m , where m=0, 1, 2, . . . n. The proportional magnification may include scaling of the samples r(k) in accordance with the following equation:  
       x   =         2   n                     r        (   k   )           max                   r        (   k   )                                 
 
           [0016]    Further, the convergence may include converging the normalized value x in accordance with the following equation:  
           Q   L          (   x   )       ≅     {             2     [       log   2        x     ]       ,           x   &gt;   0               0   ,           x   =   0                                   
 
           [0017]    where [log 2  x] is an integer mostly approximate to log 2  x.  
           [0018]    According to another aspect of the present invention, there is provided an OFDM based synchronization detection method, which includes quantizing received data samples into levels of 2 n ; delaying the quantized data samples by a predetermined numbers of clocks; shifting the quantized data samples by an amount corresponding to an exponent of the delayed data and outputting shifting results indicative thereof; and detecting synchronization using the shifted results.  
           [0019]    According to an aspect of the present invention, there is provided an orthogonal frequency division multiplexing (OFDM)-based synchronization detection apparatus, including: a 2 n  level quantizing unit quantizing received data samples into levels of 2 n ; a delaying unit delaying the quantized data samples by a predetermined number of clocks; a complex conjugate extracting unit extracting complex conjugates of the delayed quantized data samples; an n-bit shifting unit shifting quantized outputs q(k) from the 2 n  level quantizing unit by an amount corresponding to a value of extracted complex conjugates; an integer extracting unit extracting integer parts from the shifted quantized outputs q(k) and outputting L outputs indicative thereof; a moving sum calculating unit summing up consecutively the L outputs at every clock; and a peak detecting unit detecting a maximum value among the summing up of the consecutive L outputs to determine a synchronization of timing.  
           [0020]    Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0021]    These and/or other aspects and/or advantages of the invention will become apparent and more readily appreciated from the following description of the aspects of the present invention, taken in conjunction with the accompanying drawings of which:  
         [0022]    [0022]FIG. 1 shows a transmission data format according to a DVB-T standard;  
         [0023]    [0023]FIG. 2 is a block diagram of a conventional correlation system detecting synchronization of timing;  
         [0024]    [0024]FIG. 3 is a block diagram of another conventional correlation system detecting the synchronization of the timing;  
         [0025]    [0025]FIG. 4 a block diagram of a correlation system detecting the synchronization of the timing, according to an aspect of the present invention; and  
         [0026]    [0026]FIG. 5 is a graph illustrating a 2 n  level quantization method used in the correlation system shown in FIG. 4. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]    Reference will now be made in detail to the aspects of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The aspects are described below in order to explain the present invention by referring to the figures.  
         [0028]    As described above with reference to FIG. 1, a cycle prefix used for detecting a synchronization of a timing at a receiving stage of a DVB-T system is a periodic copy of a portion of transmission data. While the cycle prefix has been detected by delaying received data by N clocks and using a complex multiplier for multiplying the delayed data directly with the received data, the detection of the cycle prefix, according to an aspect of the present invention, is performed by quantizing the received data in 2 n  levels and using a shifter instead of the complex multiplier.  
         [0029]    [0029]FIG. 4 shows a correlation system for detecting the synchronization of the timing, according to an aspect of the present invention. Referring to FIG. 4, the correlation system  400 , according to an aspect of the present invention, includes a 2 n  level quantizing unit  410  quantizing received data samples into levels of 2 n , a delaying unit  420  delaying the quantized data samples through the 2 n  level quantizing unit  410  by a predetermined number of clocks, a complex conjugate extracting unit  430  extracting complex conjugates of delayed quantized data samples from the delaying unit  420 , and an n-bit shifting unit  440  shifting quantized outputs q(k) from the 2 n  level quantizing unit  410  by an amount corresponding to a value of n extracted from the complex conjugate extracting unit  430 . The correlation system  400  also includes an integer extracting unit  450  extracting only integer parts from outputs from the n-bit shifting unit  440 , a moving sum calculating unit  460  summing up consecutive L outputs from the integer extracting unit  450  at every clock, and a peak detecting unit  470  detecting a maximum value among outputs from the moving sum calculating unit  460  and determining the synchronization of timing.  
         [0030]    The 2 n  level quantizing unit  410  quantizes the received data samples into a maximum of 2 n  levels as follows. The 2 n  level quantizing is defined as quantizing data levels of exponents of 2. For example, a 2 1  level quantizing includes levels of 0, 2 0 , and 2 1 . In a 2 1  level quantizing, a data sample between 0 and 1 is quantized into either 0 or 1 based on which one is closer, and a sample between 1 and 2 is quantized into either 1 or 2 based on which one is closer. Likewise, in a 2 2  level quantizing, samples are quantized as any one level among 0, 2 0 , 2 1 , and 2 2  levels, and in a 2 3  level quantizing; the quantizing levels are 0, 2 0 , 2 1 , 2 2 , and 2 3 .  
         [0031]    [0031]FIG. 5 shows samples quantized into levels of 2 n . For example, sample 1 having a value between 2 0  and 2 1  is quantized into 2 0  because the value is closer to 2 0 , and sample 4 having a value between 2 1  and 2 2  is quantized into 2 1  because the value is closer to 2 1 . By quantizing the samples in this way, every sample has a value that is an exponent of 2, and by using the quantized samples, the complex multiplication in the conventional systems can be replaced with simple shifting.  
         [0032]    The 2 n  level quantizing method will be described in more detail below. If the samples r(k) in the above-described Equation (1) are substituted with 2 n  level quantized samples q(k), the following equation is obtained:  
               Λ        (   n   )       =       ∑     k   =   1       n   +   L              q        (   k   )              q   *          (     k   -   N     )                   (   2   )                               
 
         [0033]    If a sample max r(k) having a largest value among the samples r(k) is 2 n , and the other samples r(k) are proportionally magnified or scaled, the 2 n  level quantized samples q(k) can be represented by a quantization function Q L  as follows:  
               q        (   k   )       =       Q   L          [         2   n                     r        (   k   )           max                   r        (   k   )           ]               (   3   )                               
 
         [0034]    The term Q L [x] in Equation (3) represents a complex quantization to quantize the scaled sample values into levels of 2 i  in accordance with the following equation:  
         Q L [x]≅Q[Re{x}]+jQ[Im{x}]  (4)  
         [0035]    The term Q L [x] can also be represented as follows:  
                 Q   L          (   x   )       ≅     {             2     [       log   2        x     ]       ,           x   &gt;   0               0   ,           x   =   0                     (   5   )                               
 
         [0036]    In Equation (5), [log 2  x] is an integer mostly approximate to log 2  x. Through the quantizing processes described above, the 2 n  level quantized samples q(k) can have 2 m  level quantized values, and the conventional complex multiplier can be replaced with a simple m-bit shifter. The quantizing processes described above are performed through the 2 n  level quantizing unit  410 , the quantized values q(k) are transmitted to the delaying unit  420  and the n-bit shifting unit  440 .  
         [0037]    If the shifter is used instead of the multiplier, Equation (1) can be represented as follows:  
               Λ        (   n   )       =       ∑     k   =   1       n   +   L            {       q        (   k   )            l        (     k   -   N     )         }               (   6   )                               
  l ( k - N )=log 2    q *( k - N )   (7)  
         [0038]    The term q(k)&lt;&lt;l(k-N) in Equation (6) represents a shift of the quantized value q(k) to the left bit location by l(k-N) bits. Meanwhile, Equation (7) represents a transformation of the 2 n  level quantized samples q*(k-N) into the values of l(k-N), which are values of exponents extracted from the 2 n  level quantized samples. Although an element for performing the transformation of q*(k-N) into l(k-N), i.e., an element for extracting the values of the exponents from the 2 n  level quantized samples is not shown in FIG. 4, but it will be understood by those of ordinary skill in the art that such an element can be interposed between the complex conjugate extracting unit  430  and the n-bit shifting unit  440 . Further, it will be understood by those of ordinary skill in the art that the shifting of a bit by the value of an exponent extracted as described above performs the same function as a multiplication.  
         [0039]    As described above, according to an aspect of the present invention, because correlation coefficients quantized in 2 n  levels are used in a correlation apparatus for detecting synchronization at receiving stages of an OFDM system, and a shifter can be used instead of a conventional complex multiplier, a complexity of a hardware structure can be reduced without diminishing a system performance.  
         [0040]    Although a few aspects of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this aspect without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.