Abstract:
A power converter is disclosed that includes an active valley fill (AVF) capacitor that is actively switched to provide current to a load during a portion of an alternating current (AC) input cycle. The current supplied to the load includes some current supplied by the AC input and some current supplied by the AVF capacitor. Circuitry is configured to regulate the amount of current flowing through the load, including controlling the amount of current supplied by the AVF capacitor. The duty cycle on the AVF capacitor can be adjusted to shape the AC input current waveform.

Description:
TECHNICAL FIELD 
       [0001]    This disclosure relates generally to alternating current (AC) powered systems that drive direct current (DC) loads or require a DC supply. 
       BACKGROUND 
       [0002]      FIG. 1  is a schematic diagram of a voltage halving passive valley fill (PVF) circuit  100 . PVF circuit  100  includes a full wave rectifier (FWR)  102  (e.g., diodes DBR 1 -DBR 4 ), diodes D 1 -D 3 , fill capacitors C 2 , C 4 , C 5  and resistor R 1 . In AC powered systems that drive DC loads or require DC supply, PVF circuit  100  can provide power to a load when the rectified AC input voltage approaches zero. PVF capacitors C 2 , C 4 , C 5  are charged in series and discharged in parallel due to diodes D 1 -D 3 . During discharge, the fill capacitors provide half of the peak AC input voltage to the load. 
         [0003]      FIG. 2  is a plot illustrating the rectified AC input voltage, which is output from FWR  102 . Each cycle of the rectified AC input voltage is twice the frequency of the AC input voltage. Each cycle of the rectified AC input voltage arbitrarily starts at the beginning of time period A and ends at the end of time period A′. For discussion purposes, a cycle of the rectified AC input voltage is assumed to start at the beginning of time period B and end at the end of the next time period A. 
         [0004]      FIG. 3  is a plot of output voltage of PVF circuit  100 . PVF capacitors C 2 , C 4 , C 5  charge to the peak input voltage. Because of diodes DBR 1 -DBR 4  in FWR  102 , when the rectified AC input voltage falls below one half of the peak voltage, the combined voltage on PVF capacitors C 2 , C 4 , C 5 , is larger than the AC input voltage and PVF capacitors C 2 , C 4 , C 5  supply current to the load. The combined voltage of PVF capacitors C 2 , C 4 , C 5  falls as the load draws current. Thus, the rectified AC input voltage surpasses the combined voltage on PVF capacitors C 2 , C 4 , C 5  before the end of time period A. 
         [0005]      FIG. 4  is a plot of PVF capacitor current. The current in PVF capacitors C 2 , C 4 , C 5  is shown in  FIG. 4 . Line  402  illustrates the resistor limiting the inrush current into PVF capacitors C 2 , C 4 , C 5  and line  400  illustrates a low resistor value R. During time period A, and most of time period A′, PVF capacitors C 2 , C 4 , C 5  supply current to the load. During the end of time periods A, B and B′, the AC input supplies current to the load and current to charge PVF capacitors C 2 , C 4 , C 5 . Because PVF capacitors C 2 , C 4 , C 5  are coupled in series when charging the recharge of PVF capacitors C 2 , C 5 , C 5  occurs when the rectified AC input voltage is near, but prior to, the peak AC input voltage. Because PVF capacitors C 2 , C 4 , C 5  are coupled in parallel during discharge, PVF capacitors C 2 , C 4 , C 5  supply current to the load when the rectified AC input voltage falls below half of peak AC input voltage. 
         [0006]    The current from the AC input is the sum of the current supplied to the load during time periods B and B′ plus the current to charge PVF capacitors C 2 , C 4 , C 5 . For approximately one third of the cycle of the AC input voltage (A and most of A′), the AC input sees no load and the load at the output is supplied by PVF capacitors C 2 , C 4 , C 5 . 
         [0007]      FIG. 5  is a plot of actual AC current (I_ac) versus ideal AC current. For the DC current load (I_load), the actual AC current is a rather rough approximation of the ideal AC current, where “ideal” means having a higher power factor near 1.0. This is for a constant current load, meaning the output power is not constant. For a constant load power, the I_load becomes much worse (worse PF) because the current must increase near the valley to compensate for the decreasing supply voltage, as shown in  FIG. 6 . 
         [0008]      FIGS. 7A and 7B  are plots illustrating an input voltage waveform of PVF circuit  100  with a resistive load and resistor current limiting. One can observe from  FIGS. 7A and 7B , that PVF circuit  100  is limited in its ability to provide a good power factor. The current from the AC input is zero when PVF capacitors C 2 , C 4 , C 5  are conducting. Although the shape of the PVF voltage and current waveforms look better with a resistive load, there is no current drawn from the resistive load for roughly one third of the cycle and there is a current spike near the middle of the cycle to charge the PVF capacitors. 
         [0009]      FIG. 8  is a schematic diagram of a two-stage power factor correction (PFC) converter  200 . Two-stage converter  800  is a conventional solution to the power factor problem described above. First stage  802  of converter  800  includes inductor L 1 , diode D 1 , capacitor C 1 , resistors Ra, Rb, transistor N 2  and integrated circuit IC 1 . Second stage  804  includes the remaining components in  FIG. 8  in conjunction with IC 1 . The power factor correction provided by two-stage converter  800  is good but the extra inductor L 1  and the associated losses and costs are not desired. 
       SUMMARY 
       [0010]    A power converter is disclosed that includes an active valley fill (AVF) capacitor that is actively switched to provide current to a load during a portion of an AC input cycle. The current supplied to the load includes some current supplied by the AC input and some current supplied by the AVF capacitor. Circuitry is configured to regulate the amount of current flowing through the load, including controlling the amount of current supplied by the AVF capacitor. The duty cycle on the AVF capacitor can be adjusted to shape the AC input current waveform. The AVF capacitor can be combined with a floating buck converter for powering the load. The AVF can be used in non-isolated and isolated PFC converter topologies. The isolated topologies can use a winding of an isolation transformer to transfer voltage from the AVF capacitor to the load. The isolated topologies can include an open or closed loop to the secondary side of the transformer. Circuitry can be included on the secondary side of the transformer to rectify the AVF capacitor voltage due to reverse polarity of the winding used to transfer the AVF capacitor voltage to the load. 
         [0011]    In some implementations, a power converter includes a rectifier configured for coupling to an AC input. An AVF capacitor is coupled to an output of the rectifier through a first switch. The first switch is configurable to enable flow of current from the AVF capacitor. An energy storage circuit is coupled to the AVF capacitor and to the output of the rectifier through a second switch. The second switch is configurable to regulate current in the energy storage circuit. A control circuit is coupled to the first switch and the second switch. The control circuit is configurable to control duty cycles of the first and second switches concurrently during a portion of a cycle of the AC input to supply current from the AVF capacitor and AC input to the energy storage circuit. 
         [0012]    In some implementations, a method performed by a power converter comprises: receiving an AC input; rectifying the AC input; configuring a first switch coupled to an AVF capacitor to enable a flow of current from the AVF capacitor; configuring a second switch to regulate current flow in an energy storage circuit; and configuring a control circuit coupled to the first switch and the second switch to control duty cycles of the first and second switches concurrently during a portion of a cycle of the AC input voltage to supply current from the AVF capacitor and AC input to the energy storage circuit. 
         [0013]    Particular implementations disclosed herein provide one or more of the following advantages: 1) input capacitors are maintained on the input side of a power converter, where they can be smaller in high voltage systems, and to which a fast DC-DC converter without bandwidth limitations of conventional active PFC converters can be coupled; 2) improved current shaping that satisfies regulatory harmonic current requirements; 3) significantly lowered part count and system cost of implementing solutions; 4) improved efficiency; and 5) decreased physical area requirements for implementing solutions. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a schematic diagram of a voltage halving PVF 
           [0015]      FIG. 2  is a plot illustrating an FWR AC input waveform. 
           [0016]      FIG. 3  is a plot of PVF voltage. 
           [0017]      FIG. 4  is a plot of PVF capacitor current. 
           [0018]      FIG. 5  is a plot of actual AC current versus ideal AC current. 
           [0019]      FIG. 6  is a plot of supply current for a constant power load. 
           [0020]      FIGS. 7A and 7B  are plots illustrating a resistive load on a PVF circuit with resistor current limiting. 
           [0021]      FIG. 8  is a schematic diagram of a two-stage PFC converter. 
           [0022]      FIGS. 9A and 9B  are schematic diagrams of an exemplary primary side active AVF circuit. 
           [0023]      FIGS. 10A through 10C  are plots illustrating AVF voltage waveforms. 
           [0024]      FIGS. 11A through 11C  are plots of PVF versus AVF currents. 
           [0025]      FIG. 12  is a schematic diagram of an exemplary AVF circuit with center tap transformer. 
           [0026]      FIG. 13  is a schematic diagram of an exemplary AVF circuit with secondary FWR. 
           [0027]      FIG. 14  is a schematic diagram of an exemplary simplified AVF circuit. 
           [0028]      FIG. 15  is a schematic diagram of an exemplary charge and discharge AVF circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]      FIG. 9A  is a schematic diagram of an exemplary primary side AVF circuit  900  for a primary side Light Emitting Diode (LED) application. While the circuit configuration shown is for an LED application, circuit  900  may be used with other types of applications. 
         [0030]    In the example shown, circuit  900  is a floating buck converter that includes FWR, resistors R 1 , R 2 , diode D 4 , capacitors C 1 , C 2  transistors P 1 , N 1 , integrated circuit IC 1 , load S 1  and an energy storage circuit including diode D 1  and inductor L 1 . When switch N 1  (e.g., NMOS transistor) is driven closed, the current in circuit  900  begins to increase and L 1  drops a voltage. The voltage drop across L 1  counteracts the input voltage and reduces the net voltage across load S 1 , which in this example is an LED string. Over time, L 1  allows the current in circuit  900  to increase slowly by decreasing the voltage it drops and therefore increasing the net voltage seen by S 1 . During this time, L 1  is storing energy in the form of a magnetic field. If N 1  is driven open before L 1  has fully charged, then there will always be a voltage drop across L 1 , such that the net voltage seen by S 1  will always be less than the input voltage source. When N 1  is driven open again, the load from the string S 1  will not flow through the input voltage Vac, the current will begin to drop, causing L 1  to reverse the direction of its voltage and to act like a voltage source. If N 1  is driven closed again before L 1  fully discharges, S 1  will always see a non-zero voltage. 
         [0031]    AVF capacitor C 1  placed in parallel with S 1  helps to smooth out the voltage waveform as L 1  charges and discharges in each cycle. R 2  is an optional resistor to limit inrush current when C 1  is being charged. D 4  is also optional and allows R 2  to be bypassed when the charge from C 1  is being delivered to the load. The gate G 1  of N 1  is driven by IC 1  based on the current through S 1 . 
         [0032]      FIG. 9B  is a schematic diagram illustrating the operation of circuit  900 . Switch P 1  (e.g., PMOS transistor) controls the discharge of AVF capacitor C 1 . Because of the parasitic diode (source to drain) inherent in P 1 , C 1  will charge independent of the voltage on the gate G 3  of P 1 . In the discharge phase (when C 1  supplies current to the load) the drain of P 1  will fall below ground and will remain off until G 3  is driven (at least a threshold voltage) below ground. This is the purpose of C 2  and the switches sw 1 , sw 2  and sw 3 . When P 1  is desired off, sw 2  and sw 1  are driven closed and sw 3  is driven open. This switch configuration drives G 3  to zero volts, turning off P 1 , and charges C 2  to the supply voltage (e.g., 12 volts). When P 1  is desired to be on, sw 1  and sw 2  are driven open and sw 3  is driven closed. This switch configuration drives G 3  to approximately a negative supply voltage (e.g., −12V), turning P 1  on. 
         [0033]    When P 1  is off, the FWR voltage is seen at Vfwr. When P 1  is on, the voltage on C 1  is seen at Vfwr. In this manner, circuit  900  can switch between the full-rectified voltage and the voltage on C 1  at any desired time. Circuit  900  is not limited to half the peak voltage as in PVF circuit  100 . In fact, AVF circuit  900  allows for switching back and forth between the FWR voltage and the voltage on C 1  at any time. 
         [0034]      FIG. 10A  illustrates a full wave rectified waveform. To aid the comparison of AVF with PVF, the A′ and A part of the cycle will be examined. With AVF, the AVF capacitor C 1  may be engaged at any time. For example, P 1  may be turned on before A′ starts or well after A′ starts. Thus, the time for which the AC input current is drawn can be shortened or lengthened. In  FIG. 10B , capacitor C 1  is switched in for the entire A′ and A interval. 
         [0035]      FIG. 10C  illustrates the full wave rectified waveform with switching between the voltage on AVF capacitor C 1  and the rectified AC input voltage. The time duration is not representative of the actual time or duty cycle but is shown for illustrative purposes. The advantage of AVF circuit  900  is that current is drawn from the AC input during time A′ and A when both capacitor C 1  and the AC input are supplying current to the load concurrently. If the switching is fast enough, the AC input sees the average current drawn during A′ and A. The circuit can switch back to the AC input for a short amount of time such that the average current follows the AC input waveform. The current drawn by the load can be decreased to zero as the AC input voltage decreases and increased as the AC input voltage increases. 
         [0036]    Referring to  FIG. 10C  and  FIG. 9A , the capacitor C 1  provides current to the load (Vout) during time period A and A′, and the input voltage provides power to the load during time periods B, B′, A and A′. Table 1 below illustrates how the AC input voltage and AVF capacitor provide current to the load during the time periods B, B′, A and A′. 
         [0000]    
       
         
               
             
               
               
               
             
           
               
                 TABLE I 
               
             
             
               
                   
               
               
                 Load Current Contributions During AC Input Cycle 
               
             
          
           
               
                 Time Period 
                 AC Input 
                 Capacitor C1 
               
               
                   
               
               
                 B 
                 Sole supplier of current 
                 No current supplied 
               
               
                   
                 to the load 
                 to load (C1 charging) 
               
               
                 B′ 
                 Sole supplier of current 
                 Idle 
               
               
                   
                 to the load 
               
               
                 A′ 
                 Supplies some current 
                 Supplies some current 
               
               
                   
                 to the load 
                 to the load 
               
               
                 A 
                 Supplies some current 
                 Supplies some current 
               
               
                   
                 to the load 
                 to the load 
               
               
                   
               
             
          
         
       
     
         [0037]    During time period B, the input voltage supplies power to the load and charges up C 1 . During time B′, C 1  is charged and is idle. The input voltage supplies power to the load. During time A and A′, both the input and C 1  provide power to the load. When input voltage is high (near the start of time period A′), most of the current in the load is supplied by the input and a small amount of current is supplied by C 1 . Consequently, the duty cycle (on time) of switch P 1  is small. When the voltage is low (near the end of time period A′ and the beginning of time period A), most of the current is supplied by C 1  and a small amount of current is supplied by the input. Consequently, the duty cycle on P 1  is high. Effectively, the duty cycle on C 1  increases as the voltage from the input falls and is thus inversely proportional to the FWR voltage. A blowup of time period A′ in  FIG. 10C  illustrates the duty cycle on C 1  starting low and getting higher (on time is increasing) as the FWR voltage decreases. 
         [0038]    Referring to  FIG. 9A , D 1 , L 1  and S 1  are the primary components of the floating buck converter. N 1 , R 1  and IC 1  regulate the current in the floating buck converter. The effect is to create a controlled current in L 1  such that the current in the load S 1  is controlled. The floating buck converter requires a minimum voltage that is greater than the output voltage (Vout) to maintain Vout. Even so, current can still be drawn from the AC input when the AC input falls below this minimum voltage. In this case, instead of adding current to L 1 , the rate at which L 1  current falls is decreased and current is drawn from the AC input as desired to create good PFC. 
         [0039]    In operation, the L 1  current in the floating buck converter increases when N 1  is on and the supply voltage is greater than the Vout. The inductor current decreases when N 1  is off. When the FWR voltage is below Vout, if the AC input voltage is switched from the voltage across C 1  to the FWR voltage there is no change of behavior when N 1  is off (the current decreases). However, when N 1  is on, the L 1  current will still decrease but at a slower rate because the voltage V across L 1  is less and the change in current over time is less (V=L di/dt). As long as C 1  is switched back (by IC  1  through switch P 1 ) to maintain the desired L 1  current, the FWR voltage can be switched into the load by IC 1  through switch N 1  to draw current. 
       Setting Duty Cycle on Switch P 1   
       [0040]    The circuit configuration that is shown in  FIG. 9A  uses a floating buck topology to regulate the output voltage (Vout). The duty cycle of switch N 1  increases as the FWR voltage drops and will reach 100% when the FWR voltage is approximately equivalent to Vout. This is the point where AVF capacitor C 1  is used to deliver some of the current to the load. Once the 100% duty cycle is achieved, switch N 1  stays on. Resistor R 1  is used to monitor the current through the floating buck. The circuit configuration is effectively a floating buck converter that switches between two voltages: the voltage on C 1  and the FWR voltage. The switching can be controlled by the duty cycle of switch P 1 . For example, the gate G 3  of transistor P 1  can be driven negative by IC 1  to turn P 1  on. 
         [0041]    In some implementations, it may be desirable to slow or smooth the transition from a floating buck to a conventional buck. This could have the benefit of wave shaping for better power factor correction. For example, the circuit can start switching C 1  at a low duty cycle half way through the time period B′. During the transition phase (before N 1  duty cycle reaches 100%), the circuit can start switching C 1 . The FWR current waveform can be shaped based on when and how the current from C 1  is supplied to the load. 
         [0042]    In some implementations, a comparator (not shown) can be added to the circuit in  FIG. 9A  that takes as inputs the FWR voltage and Vout. When the input voltage is less than Vout, the comparator outputs a voltage that can be used as a signal to reconfigure the floating buck converter to a conventional buck converter. 
         [0043]      FIGS. 11A through 11C  are plots of PVF versus AVF currents. Comparing the current in PVF (for a resistive load) and AVF, the power factor of AVF is significantly improved. AVF provides better power delivery (smaller capacitor C 1 , higher voltage on C 1 ) and better power factor. Compared to a two-stage converter Shown in  FIG. 8 , AVF gets nearly as good a power factor (AVF still has the capacitor charging current) and nearly as good a power delivery (two-stage converter places a slightly higher voltage on the capacitor). Finally, AVF eliminates the inductive losses (e.g., magnetic losses and resistive losses) due to the inductor used in the two-stage converter. 
       Example AVF Circuit Topologies with Isolated Loads 
       [0044]    AVF can be used in isolated or non-isolated designs as shown in  FIGS. 12-15 . These example topologies each include a forward FWR; however, other known isolated designs are applicable. Additionally, each circuit includes an open loop to the secondary side. In some implementations, however, feedback may also be used. For example, an opto-isolator or other means can be used to provide feedback on the secondary side of the transformer. 
         [0045]      FIG. 12  is a schematic diagram of an exemplary AVF circuit with a center tap transformer T 1  having four windings T 1 A-T 1 D. AVF is accomplished using winding T 1 D to transfer the voltage from AVF capacitor C 1  to the load. Diode D 1  allows capacitor C 1  to charge to the peak voltage of the FWR input. An optional inrush current limiting resistor (not shown) can be placed in series with D 1 . This configuration acts as a forward converter that transfers energy to the secondary from either the AVF voltage on C 1  or the FWR input. The FWR input energy is transferred in a forward converter manner, by turning on switch N 1 . This forward biases diode D 2  and allows energy to pass to inductor L 1  and capacitor C 2 . When switch N 2  is turned on, energy is transferred through diode D 3 . Since switches N 2 , N 1  are not on at the same time, the sense resistor R 1  can be shared by switches N 2 , N 1 . Diodes D 2  and D 3  rectify the input. 
         [0046]      FIG. 13  is a schematic diagram of an exemplary AVF circuit including a secondary FWR. The AVF circuit is equivalent in function to the AVF circuit in  FIG. 12  but includes a secondary FWR comprising diodes D 3 , D 5  on each side of the secondary winding T 1 B to rectify the FWR input. In this topology, the transformer T 1  does not require a center tap. In  FIGS. 12 and 13 , the polarity of coil T 1 D of the transformer T 1  is reversed. This guarantees that the voltage on the drain of switch N 2  is positive. As a consequence, the voltage from the AVF capacitor C 1  is inverted, which accounts for the need to rectify in the AVF circuits of  FIGS. 12 and 13 . 
         [0047]      FIG. 14  is a schematic diagram of an exemplary simplified AVF circuit. The circuit in  FIG. 14  is simplified further from the circuits shown in  FIGS. 12 and 13  by including only a single diode D 2  on the secondary side of transformer T 1 . D 2  can be used if the turn ratio of coils T 1 A and T 1 D is at or near one. It is important to keep the parasitic diode in N 2  from turning on. Other than when C 1  is charging, the voltage on C 1  is always greater than the voltage on Vfwr. If the turn ratio is one or less then turning on transistor N 1  will maintain a positive voltage on the drain of N 2  and the parasitic diode of N 2  will remain off. The circuits in  FIGS. 12 and 13  do not have the turn ratio requirement because of the polarity of the T 1 D winding. 
         [0048]      FIG. 15  is a schematic diagram of an exemplary charge and discharge AVF circuit. This topology uses coil T 1 D to charge the AVF capacitor C 1 . Diode D 1  is eliminated and the current that is sensed at s 1  (the voltage across R 1 ) represents the total load on the AC input. 
         [0049]    The isolated AVF circuits shown in  FIGS. 12-15  have the advantage of using only NMOS transistors N 1 , N 2  for switches and requiring only a positive voltage to turn on the NMOS transistors N 1  and N 2 . Additionally, each of these circuits assumes a positive FWR. In some implementations, a negative FWR could be used by reversing the diodes in the FWR and replacing the NMOS transistors with PMOS transistors and vice-versa. 
         [0050]    While this document contains many specific implementation details, these should not be construed as limitations on the scope what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination may be directed to a sub combination or variation of a sub combination.