Abstract:
Current mode charge pumps having improved power consumption characteristics and reduced peak current requirements. The current mode charge pumps utilize a differential transistor pair with a current source providing the tail current for the differential pair. The differential pair alternately steers the current of the current source through first and second fly capacitors, with additional circuitry coupling the opposite fly capacitor, previously charged, to the output of the charge pump. Selection of the tail current provides for matching of circuit performance with the required charge pump output voltage, the load current to be provided thereby and the start time requirements.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to the field of charge pumps. 
     2. Prior Art 
     Charge pumps are well known in the prior art for operating from a power supply of a first voltage for such purposes as providing a source of power at a second voltage higher than the first voltage (voltage multiplication), and/or providing a balanced (plus and minus) power supply from a single power supply (voltage inversion). Such charge pumps are often realized in integrated circuit form and the output thereof used for various purposes on that integrated circuit. By way of a specific example, the preferred embodiment of the present invention is intended for use in CMOS integrated circuits to provide an augmented dual supply to achieve rail-to-rail input and rail-to-rail output voltages for on chip integrated circuits. 
     A typical circuit for a prior art voltage mode charge pump may be seen in FIG.  1 . As shown in that Figure, fly capacitors C 1  and C 2  are driven by a clock signal CLK through inverters INV 1 , INV 2  and INV 3 . The inverters are shown schematically, in that the output of the inverters INV 1  and INV 2  are non-overlapping signals representing the inverted clock signal CLK and the non-inverted clock signal, respectively. When the output of inverter INV 1  is high and the output of inverter INV 2  is low, the charge on capacitor C 1  will drive the voltage on node  1  higher than the supply voltage V DD . This turns off n-channel transistor M 1 , and turns on n-channel transistor M 2  to charge capacitor C 2  to the power supply voltage V DD  (the output of inverter INV 2  being low, typically at ground potential). At the same time node  1 , being driven higher than the power supply V DD , will hold p-channel device M 4  off. The low voltage on node  2 , however, will turn on p-channel device M 3  to couple the higher voltage at node  1  to the output V OUT , delivering charge to the reserve capacitor C OUT  in an amount dependent upon the value of the output voltage V OUT , the current being drawn by the load connected to the output V OUT  and the various other parameters of the charge pump. 
     When the output of the inverter INV 1  goes low and the output of inverter INV 2  goes high, the voltage on node  2  will now go higher than the supply voltage V DD  because of the charge on capacitor C 2 , turning on n-channel transistor M 1  to recharge capacitor C 1  to the voltage V DD . The voltage on node  1  will turn on p-channel device M 4  to couple the higher voltage on node  2  to the output V OUT , delivering charge from fly capacitor C 2  to the reserve capacitor C OUT . Note that even if the voltage on node  1  is equal to V DD , as it would be when capacitor C 1  is fully charged, the voltage on node  2  when the output of inverter INV 2  is high, and the output voltage V OUT , will both be higher than the voltage V DD , SO that both the source and drain of p-channel device M 4  will be at higher voltages than the gate of the device. With no significant load on the output of the charge pump, the output voltage V OUT  will stabilize at approximately 2 V DD . 
     In the foregoing circuit, the power consumption is not well controlled due to switching losses, namely the feed through current in inverters INV 1 , INV 2  and INV 3 . Also the excess current required to charge and discharge the capacitors due to the switching times. 
     BRIEF SUMMARY OF THE INVENTION 
     Current mode charge pumps having improved power consumption characteristics and reduced peak current requirements. The current mode charge pumps utilize a differential transistor pair with a current source providing the tail current for the differential pair. The differential pair alternately steers the current of the current source through first and second fly capacitors, with additional circuitry coupling the opposite fly capacitor, previously charged, to the output of the charge pump. Selection of the tail current provides for matching of circuit performance with the required charge pump output voltage, the load current to be provided thereby and the start time requirements. Various embodiments are disclosed. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a prior art voltage mode charge pump. 
     FIG. 2 is a circuit diagram for an exemplary current mode charge pump in accordance with the present invention as used for a voltage multiplier. 
     FIG. 3 is a block diagram illustrating the regulation of tail current for a charge pump of the type illustrated in the circuit of FIG. 2 to minimize power requirements while providing a short startup time. 
     FIG. 4 is a circuit diagram for an exemplary current mode charge pump in accordance with the present invention as used for voltage inversion. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Now referring to FIG. 2, a preferred embodiment of the present invention may be seen. In this Figure, the fly capacitors C 1  and C 2 , as well as the reserve capacitor C OUT , are labeled as in FIG. 1, as their primary functions are the same as in the prior art circuit. Also in FIG. 2, while the main power supply lines are labeled V DD  for the positive supply voltage, and GRD for ground (which alternatively could be any first and second voltages), two additional inputs other than the clocking signals are provided to the circuit, namely voltages VN 1  and VP 1 . These voltages are gate voltages typically mirrored from another MOS device having a predetermined current there through, so that the devices having their gates referenced to these voltages will have the same or proportionate current there through when biased into conduction. Thus, n-channel devices MN 2 , MN 2 X, MN 2 Y and MN 2 Z act as current sources, as generally do p-channel MOS devices MP 6  and MP 7  when biased into forward conduction. 
     In the circuit shown in FIG. 2, n-channel devices MN 4  and MN 5  are coupled as a differential pair having a tail current determined by the n-channel devices MN 2 , MN 2 X, MN 2 Y and MN 2 Z. These last three n-channel devices (MN 2 X, MN 2 Y and MN 2 Z) are trim devices, in that all three may be used to contribute a component to the total tail current of the differential pair, or alternatively any one, two or all three of such devices may be taken out of circuit by opening one, two or all three links LK 1 , LK 2  and LK 3  at the time of wafer sort to trim the tail current to the desired level, irrespective of process variations and/or for different applications. In the preferred embodiment, all four transistors MN 2 , MN 2 X, MN 2 Y and MN 2 Z are the same size, though different sizes and/or different numbers of transistors may be used, such as by way of example, a binary progression of transistor widths might be used, if desired, for greater trimming adjustment accuracy. 
     In the circuit of FIG. 2, n-channel devices MN 6  and MN 7  are high voltage, high threshold devices. Also p-channel devices MP 6  and MP 7  provide a current to charge capacitors C 3  and C 4 , which couple the voltage changes on the non-overlapping clock inputs CLKA and CLKB, respectively, to the gates of p-channel transistors MP 4  and MP 5 , respectively, to turn the same off when the respective clock signal is high and to turn the same on when the respective clock signal is low. 
     In operation, when clock signal CLKA is high and the opposite clock signal CLKB is low, devices MN 4  and MP 5  will be turned on and devices MN 5  and MP 4  will be turned off. This connects node  1  to the source of tail current (devices MN 2 , etc.) through device MN 4 , with device MP 5  pulling node  2  to the power supply voltage V DD . At this time, node  4  will be pushed above voltage V DD  by the voltage on capacitor C 2 , turning device MN 6  on so that capacitor C 1  will charge at a rate set by the tail current for the differential pair MN 4 , MN 5 . Because device MN 6  is on, node  3  will be at voltage V DD , holding device MN 7  off to allow node  4  to go above V DD  as previously described. With node  4  approaching V OUT , device MP 1  will be off, and the low voltage on node  3  (device MN 4  being on) will turn on device MP 2  to couple the fly capacitor C 2  to the output V OUT . Thus devices MP 5  and MP 2  will be on, and capacitor C 2  will be coupled in parallel with the reserve capacitor C OUT . 
     When CLKA goes low and CLKB goes high, devices MN 5 , MP 4 , MN 7  and MP 1  turn on, and devices MN 4 , MP 5 , MN 6  and MP 2  turn off to couple now charged fly capacitor C 1  between V DD  and the output V OUT  in parallel with C OUT  and to couple fly capacitor C 2  between V DD  and ground through the current source for recharging for the next charge pump cycle. 
     In the charge pump circuit of FIG. 2, the output voltage V OUT  will be approximately 2 V DD , dependent on the clock frequency, tail current and ratio between C 1 , C 2  and C OUT . The tail current supplied to the differential pair MN 4 , MN 5  may be selected to just provide the necessary load current at the desired output voltage, thereby minimizing the output ripple, though unless the tail current is significantly higher than this, at least during startup, the startup time could be excessive for some applications. Also, it can be shown that increasing the tail current tends to increase power consumption, and tends to increase the ripple in the output voltage V OUT . As an alternative, the tail current could be made variable, such as one value for startup and one for steady state operation, or alternatively, could be controlled by feedback to provide fast startup and to regulate the charge pump output during steady state operation. Such a system is shown in block diagram form in FIG.  3 . 
     In the exemplary embodiment disclosed and described herein, the charge pump is shown operating between the two power supply voltages V DD  and ground, though these two voltages are intended to merely be representative of first and second voltages generally. Similarly, the output of the charge pump V OUT  is a voltage above V DD , though other output voltages such as voltages lower than the first and higher than the second voltages may also be obtained if desired (dual supply). By way of one specific example, as shown in FIG. 4, if all transistors are changed to the opposite conductivity type, the V DD  connection is coupled to ground and the ground connection is coupled to V DD , the output voltage V OUT  will be a voltage lower than either the first or second voltages (lower than ground and V DD , or a negative voltage in this example). Also, the charge pumps, plus or negative or both, may be cascaded to provide charge pumps capable of delivering voltages exceeding the output voltage limits for a single stage charge pump, for those application requiring still higher output voltages. Also, while the exemplary embodiments disclosed are disclosed in the form of CMOS circuits, other transistor forms may also be used, such as junction transistors if desired. Also alternatively, transistors MP 4  and MP 5  could have their respective gates separately driven, or driven through other circuitry if desired. Thus, various preferred and alternate embodiments of the present invention have been disclosed and described herein in detail as exemplary only and not for purposes of limitation, as various changes in form and detail will be obvious to those skilled in the art, and may readily be applied to the present invention without departing from the spirit and scope of the invention.