Abstract:
A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for forming a single diffusion break between finFET devices and the resulting devices. 
         [0003]    2. Description of the Related Art 
         [0004]    In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices. 
         [0005]    A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. In a planar FET device, the gate structure is formed above a substantially planar upper surface of the substrate. In some cases, one or more epitaxial growth processes are performed to form epitaxial (epi) semiconductor material in recesses formed in the source/drain regions of the planar FET device. In some cases, the epi material may be formed in the source/drain regions without forming any recesses in the substrate for a planar FET device, or the recesses may be overfilled, thus forming raised source/drain regions. The gate structures for such planar FET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques. 
         [0006]    To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded. 
         [0007]    In contrast to a FET, which has a planar structure, a so-called finFET device has a three-dimensional (3D) structure.  FIG. 1A  is a side view of an illustrative prior art finFET semiconductor device  100  that is formed above a semiconductor substrate  105 . In this example, the finFET device  100  includes three illustrative fins  110 , a gate structure  115 , sidewall spacers  120 , and a gate cap  125 . The gate structure  115  is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device  100 . The fins  110  have a three-dimensional configuration. The portions of the fins  110  covered by the gate structure  115  is the channel region of the finFET device  100 . An isolation structure  130  is formed between the fins  110 . In a conventional process flow, the portions of the fins  110  that are positioned outside of the spacers  120 , i.e., in the source/drain regions of the device  100 , may be increased in size or even merged together by performing one or more epitaxial growth processes. The process of increasing the size of the fins  110  in the source/drain regions of the device  100  is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions. 
         [0008]    A particular fin  110  may be used to fabricate multiple devices.  FIG. 1B  illustrates a cross-sectional view of the finFET device  100  along the length of one fin  110  prior to the formation of any gate structures  115 . One or more diffusion breaks  135 ,  140  are formed along the axial length of the fin  110  to define separate fin portions by removing a portion of the fin  110  and replacing it with a dielectric material. The strength of the isolation provided by the diffusion break  135 ,  140  depends on its size. A diffusion break having a lateral width (in the current transport direction, or gate length (GL) direction of the completed devices) corresponding to the lateral width of two adjacent gate structures  115  (later formed) is referred to as a double diffusion break  135 , and a diffusion break having a lateral width corresponding to the lateral width of one gate structure  115  is referred to as a single diffusion break  140 . The process for forming the single diffusion break gouges the fin  110  and defines recesses  145 . 
         [0009]      FIG. 1C  illustrates the device  100  after a plurality of processes were performed to define a plurality of gate structures  115 , with cap layers  125 , and sidewall spacers  120  above the fin  110 .  FIG. 1D  illustrates the device  100  after a self-aligned etch process was performed to recess the fin  110  using the gate structures  115  and spacers  120  as an etch mask to define recesses  150 ,  155  in the fin  110 . Because of the fin gouging, the recesses  150  adjacent the single diffusion break  140  are deeper than the other recesses  155 . 
         [0010]      FIG. 1E  illustrates the device  100  after an epitaxial growth process was performed to define epitaxial regions  160 ,  165  in the recesses  150 ,  155 . Due to the difference in the depth of the recesses  150 ,  155 , the post-fill height of the epitaxial region  160  is less than that of the epitaxial region  165 . This epitaxial material underfill changes the electrical characteristics of the device  100  in the region adjacent to the single diffusion break  140  as compared to the regions without underfill. 
         [0011]    The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above. 
       SUMMARY OF THE INVENTION 
       [0012]    The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. 
         [0013]    Generally, the present disclosure is directed to various methods of forming semiconductor devices. One illustrative method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. 
         [0014]    One illustrative device disclosed herein includes, among other things, a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: 
           [0016]      FIGS. 1A-1E  schematically depict an illustrative prior art finFET device; 
           [0017]      FIGS. 2A-2L  depict various methods disclosed herein of forming single diffusion breaks in a finFET device; and 
           [0018]      FIGS. 3A-3H  depict an alternative method disclosed herein of forming single diffusion breaks in a finFET device. 
       
    
    
       [0019]    While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
       DETAILED DESCRIPTION 
       [0020]    Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. 
         [0021]    The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. 
         [0022]    The present disclosure generally relates to various methods of forming finFET devices with a single diffusion break without causing significant underfill of epitaxial semiconductor regions formed in the fin and the resulting semiconductor devices. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. 
         [0023]      FIGS. 2A-2J  illustrate various methods for forming a single diffusion break between finFETs in a device  200 .  FIGS. 2A-2J  show a cross-sectional view of the device  200  along the axial length of an illustrative fin  210  defined in a substrate  205  with a double diffusion break  215  (e.g., silicon dioxide) defined in the fin  210 . The substrate  205  may have a variety of configurations, such as the depicted bulk silicon configuration. The substrate  205  may also have a silicon-on-insulator (SOI) configuration that includes a bulk silicon layer, a buried insulation layer and an active layer, wherein semiconductor devices are formed in and above the active layer. The substrate  205  may be formed of silicon or silicon germanium or it may be made of materials other than silicon, such as germanium. Thus, the terms “substrate” or “semiconductor substrate” should be understood to cover all semiconducting materials and all forms of such materials. The substrate  205  may have different layers. For example, the fin  210  may be formed in a process layer formed above the base layer of the substrate  205 . 
         [0024]      FIG. 2B  illustrates the device after several processes were performed to define placeholder gate structures  220  (e.g., polysilicon) above the fin  210 . A cap layer  230  (e.g., silicon nitride) is formed above the placeholder gate structure  220 , and sidewall spacers  225  (e.g., silicon nitride) are formed on the placeholder gate structure  220 . Techniques for forming the gate structures  220  are known to those of ordinary skill in the art. In the illustrative embodiment, a replacement gate technique is used to form the finFET device  200 , and the placeholder gate electrode structure  220  is illustrated prior to the formation of the replacement gate structure. The placeholder gate structure  220  includes a sacrificial gate electrode material (not separately shown), such as polysilicon, and a sacrificial gate insulation layer (not separately shown), such as silicon dioxide. 
         [0025]      FIG. 2C  illustrates the device  200  after a self-aligned etch process was performed using the placeholder gate structures  220  and sidewall spacers  225  as an etch mask to define recesses  235  in the fin  210 . 
         [0026]      FIG. 2D  illustrates the device  200  after an epitaxial growth process was performed to form epitaxial material  240  in the recesses  235 . The epitaxial semiconductor material  240  will become part of subsequently defined source/drain regions of the device  200 . The epitaxial material  240  may be comprised of different materials and it may be a strain-inducing material, such as silicon germanium or silicon carbon, formed on a silicon fin  210  or silicon formed on a silicon germanium or silicon carbon fin  210 . The epitaxial material  240  may be doped in situ or an implantation process may be performed to dope the epitaxial material  240  in the source/drain regions of the device  200 . The gate cap layer  230  and the spacers  225  shield a portion of the fin  210  in a channel region of the device  200  during the epitaxial material growth process. In one embodiment, the fin  210  may not have been doped prior to the epitaxial growth process. An implantation process may be performed after the epitaxial material growth process to dope both the fin  210  and the epitaxial material  240 . If a lightly doped source/drain region is desired, an implant process may be performed on the fin  210  after forming the placeholder gate electrode structure  220 , but prior to forming the spacers  225 . 
         [0027]      FIG. 2E  illustrates the device  200  after a first conformal deposition process was performed to deposit an etch stop layer  245  (e.g., silicon nitride) above the epitaxial material  240  and a second blanket deposition process was performed to deposit an interlayer dielectric (ILD) layer  250  above the device  200 . An exemplary material for the ILD layer  250  is silicon dioxide or a low-k dielectric material (k value less than about 3.5). The etch stop layer  245  may be a stress-inducing etch stop layer. 
         [0028]      FIG. 2F  illustrates the device  200  after a planarization process (e.g., an etching and/or CMP process) was performed to remove portions of the ILD layer  250 , the etch stop layer  245 , and the cap layer  230  and thereby expose a top surface of the placeholder gate structures  220 . 
         [0029]      FIG. 2G  illustrates the device  200  after a patterned etch mask layer  255  was formed above the ILD layer  250  to expose a selected placeholder gate structure  220 A. 
         [0030]      FIG. 2H  illustrates the device  200  after a first etch process was performed to remove the selected placeholder gate structure  220 A and a second etch process was performed to define a recess  260  in the fin  210 . 
         [0031]      FIG. 2I  illustrates the device  200  after a stripping process was performed to remove the patterned etch mask layer  255  and a deposition process was performed to deposit a dielectric layer  265  (e.g., silicon dioxide) to over-fill the recess  260  and the space created by the removal of the selected placeholder gate structure  220 A. In some embodiments, the dielectric layer  265  may be formed using the same material as the double diffusion break  215 . 
         [0032]      FIG. 2J  illustrates the device  200  after a planarization process was performed to remove portions of the dielectric layer  265  and expose the remaining placeholder gate structures  220 . The remaining portion of the dielectric layer  265  defines a single diffusion break  270 . Because the single diffusion break is formed after the placeholder gate structures  220  were formed (for a replacement technique), the epitaxial material  240  adjacent the single diffusion break  270  has substantially the same profile as the epitaxial material  240  in other recesses  235  formed in the fin. This uniformity improves the performance of the device  100  and reduces the likelihood of defects in the epitaxial material  240  adjacent the single diffusion break  270 . 
         [0033]      FIG. 2K  illustrates the device after a plurality of processes were performed to form replacement gate structures  275  in place of the placeholder gate structures  220 . First an etch process was performed to remove the exposed placeholder gate structures  220 . The replacement gate structure  275  includes a gate insulation layer (not separately shown) and a conductive gate electrode (not separately shown). The gate insulation layer may include a variety of different deposited or thermally grown materials, such as, for example, silicon dioxide, a so-called high-k (k greater than 10) insulation material, such as hafnium oxide, etc. The conductive gate electrode may include one or more layers, such as one or more layers of exemplary materials, TiN, TiAlN, TiC, TaN, TaC, TaCN or W. After the materials are formed in the replacement gate cavities created by removal of the placeholder gate structures  220 , a planarization process may be performed to remove portions of the gate materials positioned outside of the replacement gate cavities. 
         [0034]      FIG. 2L  illustrates the device  200  after several processes were performed to recess the replacement gate structure  275  and form a gate cap  280 . The replacement gate structure  275  in combination with the gate cap  280  defines a gate  285  having a height. The gate  285  has a height substantially equal to the height of the single diffusion break  270 . The term “substantially equal” refers to the heights of the gate  285  with or without a gate cap layer  280 . 
         [0035]    The process illustrated in  FIGS. 2A-2L  includes two planarization processes to expose the placeholder gate structures  220 , one for the replacement process of the placeholder gate structures  220 A to form the single diffusion break  270  ( FIG. 2F ), and one for the replacement process to form the replacement gate structures  275  ( FIG. 2J ). Due to the multiple planarizations, the gate height of the replacement gate structures  275  is reduced. 
         [0036]      FIGS. 3A-3H  illustrate another embodiment of a method for forming a single diffusion break in a finFET device  200 .  FIG. 3A  illustrates the device  200  after the first planarization process shown in  FIG. 2F  was performed, and after a plurality of deposition processes were performed to deposit a cap layer  300  (e.g., silicon dioxide) and hard mask layer  305  (e.g., silicon nitride) above the ILD layer  250 . 
         [0037]      FIG. 3B  illustrates the device  200  after a patterned etch mask layer  310  was formed above the hard mask layer  305  to expose a region above the selected placeholder gate structure  220 A. 
         [0038]      FIG. 3C  illustrates the device  200  after one or more anisotropic etch processes were performed to define openings in the hard mask layer  310  and the cap layer  305 , to remove the selected placeholder gate structure  220 A, and to define a recess  315  in the fin  210 . 
         [0039]      FIG. 3D  illustrates the device  200  after a stripping process was performed to remove the mask layer  310  and a deposition process was performed to deposit a dielectric layer  320  (e.g., silicon dioxide) to over-fill the recess  315  and the space created by the removal of the selected placeholder gate structure  220 A. 
         [0040]      FIG. 3E  illustrates the device  200  after a planarization process was performed to remove portions of the dielectric layer  320  using the hard mask layer  305  as a stop layer. 
         [0041]      FIG. 3F  illustrates the device  200  after a timed, wet etch process was performed to recess the dielectric layer  320  to a height approximately equal to that of the cap layer  300 . 
         [0042]      FIG. 3G  illustrates the device  200  after an etch process was performed to remove the hard mask layer  305 . 
         [0043]      FIG. 3H  illustrates the device  200  after a timed etch process (e.g., a SiConi™ etch) was performed to remove the cap layer  300  and expose the remaining placeholder gate structures  220 . The remaining portion of the dielectric layer  320  defines a single diffusion break  325 . Subsequent processing may continue as described in  FIGS. 2K-2L  to form replacement gate structures. Because the second planarization process is avoided, the height of the replacement gate structures is not reduced as compared to the embodiment illustrated in  FIG. 2J . 
         [0044]    The methods described herein, including forming increased height fins  210  and recessing the fins in channel regions, reduces the likelihood of source/drain epi overfill, thereby providing uniform raised source/drain height throughout densely-spaced regions and isolated regions. 
         [0045]    The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.