Abstract:
A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.

Description:
FIELD OF THE INVENTION 
     This invention relates to a method and apparatus for generating a local clock signal, and more particularly to an improved programmable local clock generator. 
     BACKGROUND OF THE INVENTION 
     High performance arrays in an integrated circuit system, such as an SRAM in a processor system, typically use a local clock generator circuit to control the internal circuit timing of the array. Such array local clock generators (also referred to as a Local Clock Buffer or LCB) are used to control critical circuit functions of the array, such as word decode/bit decode and read/write functions. In order to provide flexibility in tuning the timing of the array circuit function and an ability to change the array circuit timing as part of a hardware debugging process, a state of the art LCB will often have a programmable control circuit that can alter the delay of the local clock relative to the system clock and can alter the local clock pulse width. In the prior art, a programmable control input to an explicit decoder typically selects the number of elements in an inverter delay chain. Discreet decoders and separate discreet delay chains used in the prior art result in a Local Clock Buffer that is complex, requires a substantial area of the chip to implement, and requires substantial power to operate. 
     SUMMARY OF THE INVENTION 
     An object of this invention is the provision of an array local clock generator circuit topology that is simple to implement and requires only a small amount of power to operate. 
     Another object of the invention is the provision of a delay chain topology that is simpler to implement as compared to the typical prior art inverter delay chain. 
     Briefly, this invention contemplates a programmable Local Clock Buffer with a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a partially schematic and partially block diagram of a programmable clock generator for an array in which the programmable clock generator of  FIG. 2  can be used. 
         FIG. 2  is a schematic diagram of one embodiment of a programmable array clock generator in accordance with the teaching of this invention. 
     
    
    
     The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring briefly to  FIG. 1 , it discloses a state of the art array Local Clock Buffer system in which the programmable clock delay circuit of  FIG. 2  can be used advantageously. The system of  FIG. 1  is comprised of several blocks to provide various clock control functions. These functional blocks include a BASE block for LCB input control; a LCK block for providing programmable clock delay control, which will be explained in detail in connection with  FIG. 2 ; a CHOP_B block for clock chopper control; a pwvar block for programmable clock pulse width control; and an LCK_driver block for driving the output of the LCB. 
     Referring now to  FIG. 2 , a system clock input clk is coupled as an input to a first inverter PN transistor pair P 0 , N 0  connected in series between Vd and gd by N transistor N 1 . The delayed clock output terminal lck_b is coupled to the output of the first inverter P 0 , N 0 . The system clock input clk also is coupled as an input to a second inverter PN transistor pair P 4 , N 4 . The output dly_clk_b of this second inverter coupled as an input to P transistor P 5  and N transistor N 5  and also as an input to a third inverter PN transistor pair P 10 , N 10 . The output of the third inverter is coupled as an input to a fourth inverter PN transistor pair P 11 , N 11 . Transistors P 5  and N 5  are part of a first transistor stack between Vd and gd. This first transistor stack also includes P transistor P 6  and N transistor N 6 . A second transistor stack similar to the first includes P transistors P 7  and P 8  and N transistors N 7  and N 8 . The output of the fourth inverter is coupled as an input to the gate of transistor P 6  and as an input to the gate of transistor N 7 . The clock delay select input dly 1  is coupled as an input to the gate of transistor N 6  and to the gate of transistor P 7 . The delay select input dly 0  is coupled as an input to the gate of transistor N 8  and to the gate of transistor P 8 . The node d 2  between P 7  and N 7  is coupled to the gate of transistor N 1  and the gate of transistor P 1  so that the dc state of this node d 2  modulates conduction of the system clock signal through the first inverter, P 0 , N 0 . 
     In operation of this exemplary embodiment of the invention, the programmable clock delay circuit uses two mode bits dly 0  and dly 1  to provide three delay settings, fast (that is minimal delay), normal or nominal delay, and slow (that is maximum delay). The two-to-three decode function is combined with the delay chains and the delay chains are configured with a modulated PFET/NFET inverter structure instead of the simple inverter chains of the prior art. In simple inverter delay chains, the delay elements are consist of series of PFET/NFET stacks. Switching of these various delay elements are controlled or enabled by simple input gating logic. The new modulated PFET/NFET inverter structure described here (P 5 -N 5  to P 8 -N 8  circuit topology) instead have the control/enable function merged with the multi-stack PFET/NFET devices. Switching of these PFET/NFET delay elements are therefore modulated by the delay input settings. The input clock clk is active high and the output clock lclk_b is active low. 
     With dly 0  and dly 1  both low (logical 0) P 7  and P 8  are both DC on, pulling node d 2  up to Vd. Transistor N 1  turns on and transistor P 1  turns OFF. The input clock switches through the first inverter P 0 , N 0  introducing only one inverter delay between the input clock clk and the output clock lclk_b, which provides the “fast” setting, that is, the minimum delay. 
     With dly 0  low and dly 1  high, the inverter stack P 7 -P 8 /N 7 -N 8  is held off, as the input clock clk transitions from its low inactive state to high active state, as a result of the high input to P 7  and low input to N 8 . Node d 2  is low so the clock output lck_b remains initially high with conduction through inverter P 0 , N 0  blocked and P 1  connecting the output terminal lck_b to Vd. The clock signal clk switches through inverter P 4 , N 4  and then through the P 5 , P 6  stack pulling node d 2  up to Vd, enabling inverter P 0 , N 0  and turning off P 1 . The delay is three inverter stages long in total, and two stages longer than the so-called “fast” setting of the previous paragraph. This three-inverter delay is the “nominal” setting. 
     With dly 0  high (logical 1) the state of dly 1  is immaterial, and the dly 0  high state selects the so-called “slow” setting. With dly 0  high P 8  is turned off, and the N 7 -N 8  stack is enabled and node d 2  is low initially. The input clock clk switches through inverter P 4 -N 4 , next through inverter P 10 -N 10 , and then through inverter P 11 -N 11 . The inverted clock signal output dly_clk_b of the P 4 -N 4  inverter first turns on P 5  after a one-inverter delay, then waits for the switching of P 6  to come through after two-inverters delay. Inverted clock signal output of inverter P 11 -N 11  turns on P 6  and turns off N 7  after a three-inverter delay. With P 5  and P 6  both on, they pull node d 2  up to Vd, enabling the inverter P 0 -N 0 , and providing a five inverter delay. P 5 -P 6  and N 7 -N 8  are part of the five-inverter delay path between the clock input clk and the clock output lclk_b, which is two inverter delay stages longer than the nominal setting. 
     The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof. 
     As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately. 
     Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided. 
     The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention. 
     While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.