Abstract:
A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit, and the second pump capacitor, the second transfer circuit and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval.

Description:
This application is a continuation-in-part (CIP) application of the co-pending application Ser. No. 11/938,314, filed on Nov. 12, 2007. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates in general to a multiple-stage charge pump, and more particularly to a multiple-stage charge pump with a charge recycle circuit. 
     2. Description of the Related Art 
     With the increasing development of technology, multiple-stage charge pump has been widely used in the circumstances for providing voltage exceeding the voltage of the circuit power supply, for example, to write and erase operation in EEPROM. 
     Referring to  FIG. 1 , a circuit diagram of a conventional multiple-stage charge pump is shown. The conventional multiple-stage charge pump  100  includes four stages  120  and each of the stages  120  includes a diode D and a pump capacitor C. Clock signals CK 1  and CK 2  are 180 degree out of phase with each other for respectively turning on the diodes of the odd stages and the diodes of the even stages in different time intervals, which are non-overlapped. When the diode D is turned on, the pump capacitor C connected to the N end of the diode D is charged by the voltage at the P end of the diode D. Then the voltage at the N end is elevated by the corresponding clock signal. After the four stages  120 , an output voltage Vo is substantially 5 times a high voltage Vdd is obtained. 
     However, the conventional multiple-stage charge pump circuit has the disadvantages of high power consumption because the capacitor C is repeatedly charged and discharged. Therefore, how to provide a multiple-stage charge pump with lower power consumption and higher power efficiency is one of the efforts the industries are making. 
     SUMMARY OF THE INVENTION 
     The invention is directed to a multiple-stage charge pump circuit with lower power consumption and higher power efficiency in comparison to the conventional multiple-stage charge pump circuit. 
     According to an aspect of the present invention, a multiple-stage charge pump circuit is provided. The multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first transfer circuit provides a high voltage to the first end of the first pump capacitor in a first time interval of a time period. The second transfer circuit provides the voltage at the first end of the first pump capacitor to the first end of the second pump capacitor in the second time interval of the time period. The first driving circuit pulls down the voltage at the second end of the first pump capacitor in the second time interval and pulls up the voltage thereat in the first time interval. The second driving circuit pulls down the voltage at the second end of the second pump capacitor in the first time interval and pulls up the voltage thereat in the second time interval. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in the third and the fourth time interval. The first to the fourth time intervals are non-overlapped and the third and the fourth time intervals come after the second and the first time intervals, respectively. 
     The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a circuit diagram of a conventional multiple-stage charge pump. 
         FIG. 2  shows a circuit diagram of the multiple-stage charge pump circuit of the embodiment. 
         FIG. 3  shows a waveform diagram of the signals in  FIG. 2 . 
         FIG. 4  shows another circuit diagram of the multiple-stage charge pump of the embodiment. 
         FIG. 5  shows another circuit diagram of the multiple-stage charge pump of the embodiment. 
         FIG. 6  shows another circuit diagram of the multiple-stage charge pump of the embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention provides a multiple-stage charge pump circuit which uses a charge recycle circuit for transferring charge stored in a charge pump stage circuit to another charge pump stage circuit through a short circuit path formed by the charge recycle circuit, so as to reuse the charge. 
     Referring to  FIG. 2  and  FIG. 3 , a circuit diagram of the multiple-stage charge pump circuit of the embodiment and a waveform diagram of the signals in  FIG. 2  are respectively shown. The multiple-stage charge pump circuit  10  comprises stage circuits  12 ,  14 , and a charge recycle circuit  16 . The first stage circuit  12  includes a transfer circuit  12   a , a pump capacitor CP 1 , and a voltage driving circuit  120 . The transfer circuit  12   a  includes a transfer capacitor CT 1  and transistors T 1 , T 2 . 
     The pump capacitor CP 1  has first end E 11  and second end E 12 . The transfer capacitor CT 1  has first end E 21  and second end E 22 . The first and the second transistors T 1  and T 2  are, for example, N-type metal oxide semiconductor (MOS) transistors. The drains of the first and the second transistors T 1  and T 2  receive a high voltage VCC, the gates of them are respectively coupled to the second end E 22  and the first end E 21 , and the sources of them are respectively coupled to the first end E 11  and the second end E 22 . The second end E 12  is coupled to the voltage driving circuit  120  and the first end E 21  receives a clock signal P 4 . 
     In a time interval TP 1 , the voltage driving circuit  120  provides a high voltage VCC to the second end E 12  so as to pull the voltage at the first end E 11  high. The transistor T 2  is turned on based on the high voltage at the first end E 11 . When the transistor T 2  is turned on in the time interval TP 1 , the high voltage VCC is provided to the second end E 22  via the transistor T 2 . The clock signal P 4  is equal to a low voltage VSS in the time interval TP 1 . 
     In a time interval TP 2 , the clock signal P 4  rises from the low voltage VSS to the high voltage VCC. Because the voltage difference between the first and the second ends E 21  and E 22  remains unchanged, the voltage at the second end E 22  raises from the high voltage VCC to a voltage substantially two times the voltage of the high voltage VCC. The transistor T 1  is turned on and provides the high voltage VCC to the first end E 11  because the voltage at the second end E 22  (=2VCC) is higher than the voltage at the first end E 11  (VCC). The voltage driving circuit  120  provides the low voltage VSS to the second end E 12  in the time interval TP 2  so as to pull down the voltage at the second end E 12  to the low voltage VSS. As a result, the voltage difference between the first and the second ends E 11  and E 12  is equal to the voltage (VCC−VSS). The low voltage VSS, for example, equals to the ground level and the voltage difference between the first and the second ends E 11  and E 12  is equal to the high voltage VCC. 
     As the voltage at the second end E 12  is elevated to the high voltage VCC in the next time interval TP 1 , the voltage at the first end E 11  is elevated by the high voltage VCC and is equal to a voltage two times the voltage of the high voltage VCC. 
     The second stage circuit  14  includes a transfer circuit  14   a , a pump capacitor CP 2 , and a voltage driving circuit  140 . The transfer circuit  14   a  includes a transfer capacitor CT 2  and transistors T 3 , T 4 . The transistors T 3  and T 4  are N-type MOS transistors. The pump capacitor CP 2  has first end E 31  and second end E 32 . The transfer capacitor CT 2  has first end E 41  and second end E 42 . The operation of the second stage circuit  14  is similar to the operation of the first stage  12 . The second stage circuit  14  provides the voltage at the first end E 11  two times the voltage of the high voltage VCC to the first end E 31 , elevates the voltage at the first end E 31  by the high voltage VCC, and generates a voltage three times the voltage of the high voltage VCC. 
     In the multiple-stage charge pump circuit  10  of the embodiment, the first and the second stage circuits  12  and  14  operate based on clock signals P 4  and P 1 . The voltage of the second end E 12  is pulled up to the high voltage VCC in the time interval TP 1  and is pulled low to the low voltage VSS in the time interval TP 2 . The voltage of the second end E 32  is pulled down to the low voltage VSS in the time interval TP 1  and is pulled up to the high voltage VCC in the time interval TP 2 . 
     In this embodiment, the charge recycle circuit  16  is applied to recycle the charge from one of the second ends E 12  and E 32  with the high voltage VCC to the other with the low voltage VSS. The charge recycle circuit  16  of the embodiment is for connecting the second ends E 12  and E 32  in a time interval TP 3  and a time interval TP 4  of the period. The time intervals TP 3  and TP 4  respectively come after the time intervals TP 1  and TP 2 . 
     In the time interval TP 3 , the voltages at the second ends E 12  and E 32  are respectively close to the high voltage VCC and the low voltage VSS and the first and the second voltage driving circuits  120  and  140  are both disabled. Thus, the path from the second end E 12  to second end E 32  through the charge recycle circuit is formed. Therefore, in the time interval TP 3 , the charge at the second end E 12  with the high voltage VCC is recycled and transferred to the second end E 32  with the low voltage VSS, rather than directly discharged to the ground. 
     In the time interval TP 4 , the voltages at the second end E 32  and E 12  are respectively close to the high voltage VCC and the low voltage VSS and the first and the second voltage driving circuits  120  and  140  are both disabled. Thus, the path from the second end E 32  to second end E 12  through the charge recycle circuit is formed. Therefore, in the time interval TP 4 , the charge at the second end E 32  with the high voltage VCC is recycled and transferred to the second end E 12  with the low voltage VSS, rather than directly discharged to the ground. 
     In the embodiment, the charge recycle circuit  16  comprises switch circuits  162  and  164 . The switch circuits  162  and  164  include first ends and second ends. The first ends of the switch circuit  162  and  164  are respectively coupled to the second end E 12  and E 32 , and the second ends of the switch circuits  162  and  164  are coupled to each other. The switch circuits  162  and  164  are turned on in the time intervals TP 3  and TP 4  for coupling the second ends E 12  and E 32 . 
     The switch circuits  162  and  164  respectively include transistors T 5  and T 6 . The transistor T 5  and T 6  are, for example, N-type MOS transistors. The drains of the transistors T 5  and T 6  are the first end of the switch circuits  162  and  164  coupled to the second end E 12  and E 32 , respectively. The source of the transistors T 5  and T 6  are the second ends of the switch circuits  162  and  164  for coupled to each other. The gate of the transistors T 5  and T 6  receives a control signal SC 1 . The control signal SC 1  is equal to the high voltage VCC in the time intervals TP 3  and TP 4 . The transistors T 5  and T 6  are turned on based on the high control signal SC 1  in the time intervals TP 3  and TP 4 . 
     The voltage driving circuit  120  includes transistors T 7  and T 8 . The transistors T 7  and T 8  are, for example, a P-type MOS transistor and an N-type MOS transistor, respectively. The drains of the transistors T 7  and T 8  are respectively connected to the second end E 12  and E 32 . The sources of the transistors T 7  and T 8  respectively receive the high voltage VCC and the low voltage VSS. The transistors T 7  and T 8  are for providing paths for pulling up and pulling down the voltage at the second end E 12  based on the low level of a clock signal P 1 B and the high level of the clock signal P 4 , respectively, wherein the clock signal P 1 B is the inverse clock signal of the clock signal P 1 . 
     The voltage driving circuit  140  has a similar circuit structure as the voltage driving circuit  120 . The voltage driving circuit  120  includes transistors T 9  and T 10 . The transistors T 9  and T 10  are, for example, respectively a P-type MOS transistor and an N-type MOS transistor. The transistors T 9  and T 10  is for pulling up and pulling down the voltage at the second end E 32  based on the low level of a clock signal P 4 B and the high level of the clock signal P 1 , respectively. The clock signal P 4 B is an inverse signal of the clock signal P 4 . 
     The multiple-stage charge pump circuit  10  further includes an output stage circuit  18  for receiving and outputting the voltage at the first end E 31  as an output voltage VO. The output stage circuit  18  includes transistors T 11 , T 12  and a transfer capacitor CT 3 , which have substantially the same circuit connection as the transistors T 1 , T 2  and the transfer capacitor CT 1 . Therefore, the output stage  18  can effectively output the output voltage VO without voltage drop of the threshold voltage of the transistor T 11 . The output stage  18  can operate as a diode for preventing the output voltage VO from generating current flowing backward to the first end E 31  as the voltage thereat is lower than three times of the high voltage VCC. 
     The effect of charge sharing operation performed in the time intervals TP 3  and TP 4  is explained in the following. In the time interval TP 1  before the time interval TP 3 , the voltage at the second end E 12  and end E 32  are the high voltage VCC and the low voltage VSS, respectively. Since the voltage at the second end E 12  and E 32  will be respectively pulled down and pulled high in the time interval TP 2  after the time interval TP 3 , recycling the charge stored at the end E 12  to the end E 32  can effectively lower the power consumption needed to directly pull down and pull up the voltage at the second end E 12  and E 32 . The operation in the time interval TP 2  before the time interval TP 4  is similar to the operation in the time interval TP 1 , which can effectively lower the power consumption needed to directly pull down and pull up the voltage at the second end E 32  and E 12 . Therefore, the multiple-stage charge pump circuit has the advantages of lower power consumption and higher power efficiency in comparison to the conventional multiple-stage charge pump circuit. 
     Although the multiple-stage charge pump circuit  10  is exemplified to have the first and the second stage circuits  12  and  14 , the multiple-stage charge pump circuit  10  is not limited to have two stage circuits and can further include four or more than four stage circuits. For example, referring to  FIG. 4 , another circuit diagram of the multiple-stage charge pump of the embodiment is shown. The multiple-stage charge pump circuit  10 ′ differs from the multiple-stage charge pump circuit  10  in that the multiple-stage charge pump circuit  10 ′ further includes third and fourth stage circuits  12 ′ and  14 ′, the charge recycle circuit  16 ′ includes four transistors M 1 ˜M 4  correspondingly coupled to the stage circuits  12 ,  14 ,  12 ′ and  14 ′, and the transistors M 1 ˜M 4  are respectively controlled by different control signals SC 1 ˜SC 4 . 
     The circuit connection and the operation of the first and the third stage circuits  12  and  12 ′ are substantially the same. The circuit connection and the operation of the second and the fourth stage circuits  14  and  14 ′ are substantially the same. Therefore, the multiple-stage charge pump  10 ′ can effectively provide output voltage VO′ five times of the high voltage VCC. The charge recycle circuit  16 ′ is for connecting all the second ends of the pump capacitors CP 1  to CP 4  in the time intervals TP 3  and TP 4  for transferring the charge. In the charge recycle interval TP 3  or TP 4 , the transistors M 1 ˜M 4  can be respectively turned on by the control signals SC 1 ˜SC 4  at the same time for charge sharing just like in the case of the above-mentioned multi-stage charge pump  10 , or only a portion of the transistors M 1 ˜M 4  are turned on and the other portion of the transistors M 1 ˜M 4  are turned off for charge sharing among the pump capacitors CP 1 ˜CP 4  coupled to the turned-on transistors M 1 ˜M 4 . 
     For example, in the time interval TP 3  when the pump capacitors CP 1  and CP 3  have the VDD level, and the pump capacitors CP 2  and CP 4  have the ground level, the transistors M 1 ˜M 4  are all turned on by the control signals SC 1 ˜SC 4  (e.g. at the VDD level), the two VDD levels of the pump capacitors CP 1  and CP 3  are equally distributed and shared among the four stage circuits  12 ,  14 ,  12 ′ and  14 ′ via the turned-on transistors M 1 ˜M 4 . As a result of the charge sharing, the level of each capacitor CP 1 ˜CP 4  is 2*VDD/4=VDD/2 and the transfer ratio is 1/2. 
     In the time interval TP 3 , if only the three transistors M 1 , M 3  and M 4  are turned on by the control signals SC 1 , SC 3  and SC 4  and the transistor M 2  is turned off by the control signal SC 2  (e.g. at the ground level), the two VDD levels of the pump capacitors CP 1  and CP 3  can be equally distributed and shared among the three stages  12 ,  12 ′ and  14 ′ via the turned-on transistors M 1 , M 3  and M 4 . As a result, the level of each capacitor CP 1 , CP 3  or CP 4  is 2*VDD/3 and the transfer ratio is 2/3. Similarly, if the transistor M 4  is turned off and the transistor M 1 ˜M 3  are turned on in the time interval TP 3 , after the charge sharing, the level of each capacitor CP 1 ˜CP 3  is 2*VDD/3 and the transfer ratio is also 2/3. 
     If the multiple-stage charge pump circuit has N(=2n) stage circuits (n is a positive integer not smaller than 2), the charge recycle circuit has N switch elements (e.g. transistors) correspondingly coupled to the N stage circuits and controlled by different control signals. In the charge recycle interval, the pump capacitors of n stage circuits have the high voltage (VDD) level and the pump capacitors of the other n stage circuits have the ground level. By turning on b switch elements coupled to the pump capacitors having the VDD level, turning off (n-b) switch elements coupled to the other pump capacitors having the VDD level, turning on c switch elements coupled to the pump capacitors having the ground level and turning off the (n−c) switch elements coupled to the other pump capacitors having the ground level, after the charge sharing, the level of each pump capacitor coupled to the (b+c) turned-on switch elements is b*VDD/(b+c), and the transfer ratio is equal to b/(b+c), wherein b, c, (n−b), (n−c) are all positive integers. Therefore, by using different control signals to control the switch elements of the charge recycle circuit so that only a portion of the switch elements are turned on and the other portion of the switch elements are turned off, different charge transfer ratio can be obtained in the charge recycle interval to achieve different charge sharing effects. 
     Although the charge recycle circuit  16  is exemplified to include N-type MOS transistors T 5  and T 6  and connect the second ends E 12  and E 32  through them, the charge recycle circuit  16  is not limited thereto and can use other kind of transistors to connect the second ends E 12  and E 32 . For example, as shown in  FIG. 5 , the charge recycle circuit  16 ″ can include and use P-type MOS transistors to connect the second ends E 12  and E 32 , wherein the control signal SC 1 B is the inverse signal of the control signal SC 1 . Or, as shown in  FIG. 6 , the charge recycle circuit  16 ″ can even include and use complimentary MOS transistors circuit to connect the second ends E 12  and E 32 . 
     The multiple-stage charge pump circuit includes a charge recycle circuit for connecting the second end of the pump capacitors of the first and the second stage circuits to each other, so as to elevate the voltage at one of the second end of the pump capacitors based on the charge transferred from the other one. Therefore, the multiple-stage charge pump circuit has the advantages of lower power consumption and higher power efficiency in comparison to the conventional multiple-stage charge pump circuit. 
     While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.