Abstract:
A system for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the system comprises a processor-to-PCI bridge connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the system comprises two or more processor-to-PCI bridges connected to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding resistance to single point failures.

Description:
RELATED APPLICATIONS 
     The subject matter of U.S. patent application entitled METHOD OF EXPANDING PCI BUS LOADING CAPACITY, filed on Oct. 1, 1997, application Ser. No. 08/942,223, and is related to this application. 
    
    
     PRIORITY CLAIM 
     The benefit under 35 U.S.C. § 119(e) of the following U.S. provisional application(s) is hereby claimed: 
     
       
         
               
               
               
             
           
               
                   
               
               
                   
                 Application 
                   
               
               
                 Title 
                 No. 
                 Filing Date 
               
               
                   
               
             
             
               
                 “Hardware and Software Architecture for 
                 60/047,016 
                 May 13, 1997 
               
               
                 for Inter-Connecting an Environmental 
               
               
                 Management System with a Remote 
               
               
                 Interface” 
               
               
                 “Self Management Protocol for a Fly-By- 
                 60/046,416 
                 May 13, 1997 
               
               
                 Wire Service Processor” 
               
               
                 “Isolated Interrupt Structure for Input/ 
                 60/047,003 
                 May 13, 1997 
               
               
                 Output Architecture” 
               
               
                 “Three Bus Server Architecture with a 
                 60/046,490 
                 May 13, 1997 
               
               
                 Legacy PCI Bus and Mirrored I/O PCI 
               
               
                 Buses” 
               
               
                 “Computer System Hardware Infra- 
                 60/046,398 
                 May 13, 1997 
               
               
                 structure for Hot Plugging Single and 
               
               
                 Multi-Function PC Cards Without 
               
               
                 Embedded Bridges” 
               
               
                 “Computer System Hardware Infrastruc- 
                 60/046,312 
                 May 13, 1997 
               
               
                 ture for Hot Plugging Multi-Function PCI 
               
               
                 Cards With Embedded Bridges” 
               
               
                   
               
             
          
         
       
     
     APPENDICES 
     Appendix A, which forms a part of this disclosure, is a list of commonly owned copending U.S. patent applications. Each one of the applications listed in Appendix A is hereby incorporated herein in its entirety by reference thereto. 
     Appendix B, which forms part of this disclosure, is a copy of the U.S. provisional patent application filed May 13, 1997, entitled “ISOLATED INTERRUPT STRUCTURE FOR INPUT/OUTPUT ARCHITECTURE” and assigned Application Ser. No. 60/047,003. Page 1, line 17 of the provisional application has been changed from the original to positively recite that the entire provisional application, including the attached documents, forms part of this disclosure. 
     Appendix C, which forms part of this disclosure, is a copy of the U.S. provisional patent application filed May 13, 1997, entitled “THREE BUS SERVER ARCHITECTURE WITH A LEGACY PCI BUS AND MIRRORED I/O PCI BUSES” and assigned application Ser. No. 60/046,490. Page 1, line 15 of the provisional application has been changed from the original to positively recite that the entire provisional application, including the attached documents, forms part of this disclosure. 
     COPYRIGHT RIGHTS 
     A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates generally to information processing systems, such as computer servers and personal computers (PCs). More particularly, this invention relates to the transfer of control and data signals within an information processing system having multiple bus architecture. 
     2. Description of the Related Art 
     Information processing systems, such as personal computers (PCs), have virtually become an inseparable part of everyone&#39;s daily activities. These systems process an enormous amount of information in a relatively short time. To perform these sophisticated tasks, the computer system typically includes a microprocessor, memory modules, various system and bus control units, and a wide variety of data input/output (I/O) and storage devices. These computer components communicate information using various data rates and protocols over multiple system buses. The demand for faster processing speeds, and the revolutionary fast-track development of computer systems, have necessitated the use of interconnecting devices. These devices act as bridges among various data transfer protocols within the computer system. One example of such interconnecting devices is the peripheral component interconnect (PCI) bridge. 
     The  PCI Local Bus Specification, Revision  2.1 (“PCI Specification”) defines a PCI Local Bus with the primary goal of establishing an industry standard. The PCI Local Bus is a 32-bit or 64-bit bus with multiplexed address and data lines. The bus is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The PCI Specification includes the protocol, electrical, mechanical, and configuration specification for PCI Local Bus components and expansion boards. The electrical definition provides for 5.0V (e.g., desktop PCs) and 3.3V (e.g., mobile PCs) signaling environments. 
     Typical PCI Local Bus implementations support up to four add-in boards. An add-in board is a circuit board that plugs into a motherboard and provides added functionality. The motherboard is the main circuit board which contains the basic function (e.g., a central processing unit or CPU, I/O, and expansion connectors) of a computer system. FIG. 1 shows a typical PCI Local Bus system architecture. As shown in FIG. 1, a processor  102 , a cache  104 , and a dynamic random access memory (DRAM)  106  are connected to a PCI Local Bus  112  through a PCI Bridge  108 . The PCI Bridge  108  provides the logic that connects one bus to another to allow an agent (i.e., an entity that operates on a computer bus) on one bus to access an agent on the other. The PCI Bridge  108  provides a low latency path through which the processor  102 , the cache  104 , and DRAM  106  may directly access PCI devices mapped anywhere in the memory or I/O address spaces. Typical PCI devices include an audio card  116 , a motion video card  120 , a local area network (LAN) interface  124 , a small computer system interface (SCSI)  128 , an expansion bus interface  132 , and a graphics card  136 . The expansion bus interface  132  typically connects industry standard architecture (ISA) and extended ISA (EISA) devices (not shown in this figure) to the PCI local bus  112  via an ISA, EISA, or MicroChannel  140 . The expansion bus interface  132  is often referred to as the ISA/EISA bridge. 
     PCI bus drivers spend a relatively large portion of time in transient switching. PCI bus drivers are specified in terms of their AC switching characteristics. Specifically, the voltage to current relationship (V/I curve) of the driver through its active switching range is the primary means of specification. The PCI Specification defines that PCI bus drivers achieve acceptable AC switching behavior in typical configurations of six loads on the motherboard and two expansion connectors (each is considered as two loads). The PCI bus drivers can also achieve acceptable switching behavior in configurations of two loads on the mother board and four expansion connectors. Hence, the loading capacity on the PCI Local Bus  112  is limited to ten loads. In practice, however, a standard PCI configuration uses a Processor-to-PCI bridge to generate the PCI bus with up to four card slots thereon. Violation of expansion board trace length or loading limits may compromise system signal integrity. 
     The foregoing loading limits have imposed serious restrictions on system designers, and prevented the addition of new functions to computer systems. Several attempts have been made to increase the loading capacity of a PCI bus. One approach involves implementing a Processor-to-PCI bridge by coupling it to a local processor bus (i.e., the bus to which the CPU is connected). The Processor-to-PCI bridge provides a connection between the local processor bus and a PCI bus. As noted above, the loading capacity of such a PCI Chipset bridge, however, is limited to four card slots. With the increasing performance demands on personal computers, such load capacity remains insufficient. Accordingly, there is a need in the technology to expand the loading capacity of a PCI bus. Such expansion of loading capacity ensures the demands of adding powerful features to already overburdened information processing systems can be met. 
     SUMMARY OF THE INVENTION 
     To overcome the limitations of the related art, the invention provides a system for expanding the loading capacity of a PCI bus beyond its maximum loading capacity. The invention fully complies with the PCI Specification and does not compromise the system signal integrity. 
     According to one embodiment of the invention, a PCI bridge system for expanding the loading capacity of a PCI bus is provided. The PCI bridge system allows the expansion of the loading capacity of a PCI bus up to sixteen add-in board connectors (“card slots”). In this embodiment, a first-to-second bridge (e.g., the “processor-to-PCI bridge”) connects a local processor bus to four second-to-third bridges (e.g., the “PCI-to-PCI bridges”). Each PCI-to-PCI bridge supports up to four PCI card slots via its unique PCI bus. Hence, the PCI bridge system results in expanding the PCI bus to sixteen card slots without violating the loading capacity or signal integrity of the system. 
     In another embodiment of the invention, two or more processor-to-PCI bridges are integrated with the local processor bus. Each processor-to-PCI bridge connects the local processor bus to four PCI-to-PCI bridges via its unique PCI bus. Each PCI-to-PCI bridge supports up to four PCI card slots via its unique PCI bus. A third processor-to-PCI bridge is connected to the local processor bus to function as a compatibility bridge. The implementation of two processor-to-PCI bridges in a symmetric architecture adds redundancy and fault tolerance characteristics to the system. Additionally, any system breakdowns due to single-point failures is minimized. 
    
    
     BRIEF DESCRIPTION OF THE INVENTION 
     The above and other aspects, features and advantages of the invention will be better understood by referring to the following detailed description, which should be read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a conventional PCI local bus architecture in a computer system. 
     FIG. 2 is a block diagram of a local processor bus architecture implemented according to one embodiment of the invention. 
     FIG. 3 is a block diagram of a local processor bus architecture implemented according to another embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention provides a system for expanding the loading capacity of a PCI bus in an information processing system (the “computer system”). In a first embodiment, the invention provides a system for expanding the loading capacity of a PCI bus up to sixteen card slots. FIG. 2 shows a block diagram of a local processor bus architecture implemented in this first embodiment. As shown in FIG. 2, a Local Processor Bus  200  is provided to support the transfer of control and data signals among various devices within a computer system. In this embodiment, one or more processor  202  is connected to the Local Processor Bus  200  to communicate with the other devices installed within the computer system. A Cache  204  is coupled to a Cache Controller  203  which is connected to the Local Processor Bus  200 . Dynamic random access memory (DRAM)  206  is coupled to a Memory Controller  205  which is connected to the Local Processor Bus  200 . 
     A Chipset PCI Bridge  240  is connected to the Local Processor Bus  200  to provide access by a variety of PCI devices on a First PCI Bus  252  to the Local Processor Bus  200 . The Chipset PCI Bridge  240  generates the First PCI Bus  252  when connected to the Local Processor Bus  200 . Another Chipset PCI Bridge  260  is coupled to the Local Processor Bus  200  as a “compatibility bridge.” The Chipset PCI Bridge  260  generates a Second PCI Bus  262  when connected to the Local Processor Bus  200 . The Chipset PCI Bridge  260  is a compatibility bridge because compatibility devices of a personal computer (PC) are located on its Second PCI Bus  262 . With this configuration, the Chipset PCI Bridge  240  “knows” that it is a non-compatibility bridge and initializes itself with different power-on default values compared to the Chipset PCI Bridge  260 . The two Chipset PCI Bridges  240  and  260  are considered peers at the host level. A chipset PCI bridge may be based on the 82450/82454 family of PCI Chipsets manufactured by Intel Corporation. 
     Four PCI-to-PCI Bridges  242 ,  244 ,  246 , and  248 , are connected to the First PCI Bus  252  to provide access to the Local Processor Bus  200  via the Chipset PCI Bridge  240 . Each PCI-to-PCI Bridge ( 242 ,  244 ,  246 , and  248 ) fully complies with the PCI Specification, and has full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. Each PCI-to-PCI Bridge ( 242 ,  244 ,  246 , and  248 ) provides a connection between two independent PCI buses. The first independent bus is the First PCI Bus  252  which is common to all the PCI-to-PCI bridges. The First PCI Bus  252  is often referred to as the primary PCI bus in view of its close proximity to the processor  202 . Each PCI-to-PCI bridge has its unique secondary PCI bus. The unique four PCI buses are the Secondary PCI Buses  254 ,  255 ,  256 , and  257 . These PCI buses are secondary PCI buses because they are farthest from the Local Processor Bus  200 . 
     Each PCI-to-PCI Bridge ( 242 ,  244 ,  246 , and  248 ) supports buffering of simultaneous multiple posted write and delayed transactions in both directions. Each PCI-to-PCI Bridge ( 242 ,  244 ,  246 , and  248 ) allows the Local Processor Bus  200  and each of its respective Secondary PCI Buses ( 254 ,  255 ,  256 , and  257 ) to operate concurrently. A master and target on the same PCI bus may communicate while the other PCI bus is busy. The term “target” refers to a device on the PCI bus which responds with a positive acknowledgement to a bus transaction initiated by a master. 
     If its internal arbiter is used, each of the PCI-to-PCI Bridges ( 242 ,  244 ,  246 , and  248 ) supports up to four PCI bus master devices on its respective Secondary PCI Bus ( 254 ,  255 ,  256 , and  257 ). Four add-in board connectors  250  (the “PCI Card Slots”) are connected to each of the Secondary PCI Buses  254 ,  255 ,  256 , and  257 , to provide access of PCI devices to the Local Processor Bus  200 . The connector that supports each PCI Card Slot  250  is derived from a Micro Channel (MC)-style connector. MC systems are based on an architecture expansion bus defined by IBM for its PS/2 line of personal computers. The same PCI expansion board can be used in an ISA-, EISA-, and MC-based systems, provided that the motherboard supports PCI card slots in combination with ISA, EISA, and MC card slots. PCI expansion cards use an edge connector and motherboards that allow a female connector be mounted parallel to the system bus connectors. To provide a quick and easy transition from 5.0V to 3.3V component technology, there are two types of add-in board connectors: one for the 5.0V signaling environment and one for the 3.3V signaling environment. 
     Arbitration is provided to coordinate data transfers among PCI devices installed in the PCI Card Slots  250 . On the primary bus, the Chipset PCI Bridge  240 , or an independent arbiter (not shown in this figure), arbitrates the use of the First PCI Bus  252  when forwarding upstream transactions. On a secondary bus, each PCI-to-PCI bridge, or an independent arbiter (not shown in this figure), arbitrates for use of its respective secondary PCI bus for the downstream transactions. The arbiter for the primary bus may reside on the motherboard (not shown in this figure) which is external to the PCI Chipset Bridge  240 . For each secondary PCI bus, each PCI-to-PCI bridge implements an internal arbiter (not shown in this figure). If desired, this arbiter may be disabled, and an external arbiter may be used instead. The PCI-to-PCI bridge may be based on the chips 21050/21152 PCI-to-PCI Bridges manufactured by Digital Equipment Corporation. 
     As noted above, the Chipset PCI Bridge  260  operates as a compatibility bridge. It generates a Second PCI Bus  262  when connected to the Local Processor Bus  200 . As a compatibility bridge, typical PC devices may be connected to its Second PCI Bus  262  to access devices which are resident on the Local Processor Bus  200 . Typical personal computer PCI devices may include a graphics interface  264 , a SCSI  266 , a LAN interface  268 , an audio interface  270 , and an ISA/EISA bridge  272 . The ISA/EISA bridge connects industry standard architecture (ISA) extended ISA (EISA) devices (not shown in this figure) to the Local Processor Bus  200 . These ISA devices may include a floppy drive, a key board, a mouse, a serial port, a parallel port, a read only memory (ROM) unit, a real-time clock (RTC), and an audio interface. 
     Referring now to FIG. 3, a block diagram of a PCI bus architecture implemented as a second embodiment of the invention is shown. As shown in FIG. 3, a Local Processor Bus  300  is provided to support the transfer of control and data signals among various devices within a computer system. In this embodiment, one or more processor  302  is connected to the Local Processor Bus  300  to communicate with the other devices installed within the computer system. A Cache  304  is coupled to a Cache Controller  303  which is connected to the Local Processor Bus  300 . A dynamic random access memory (DRAM)  306  is coupled to a Memory Controller  305  which is connected to the Local Processor Bus  300 . 
     A Chipset PCI Bridge  340  is connected to the Local Processor Bus  200  to provide access by a variety of PCI devices on a First PCI Bus  352  to the Local Processor Bus  300 . Similarly, another Chipset PCI Bridge  360  is connected to the Local Processor Bus  200  to provide access by a variety of PCI devices on a Second PCI Bus  381  to the Local Processor Bus  300 . A third Chipset PCI Bridge  360  is coupled to the Local Processor Bus  300  as a “compatibility bridge.” 0  The Chipset PCI Bridge  360  generates a Third PCI Bus  362  when connected to the Local Processor Bus  300 . The Chipset PCI Bridge  360  is a compatibility bridge because compatibility devices of a personal computer (PC) are located on its Third PCI Bus  362 . The Chipset PCI Bridge  360  interconnects PCI devices and an ISA/EISA bridge in the same manner described in FIG.  2 . 
     Four PCI-to-PCI Bridges  342 ,  344 ,  346 , and  348 , are connected to the First PCI Bus  352 , and another four PCI-to-PCI Bridges  382 ,  384 ,  386 , and  388 , are connected to the Second PCI Bus  381 . The Chipset PCI Bridge  340  provides the PCI-to-PCI Bridges  342 ,  344 ,  346 , and  348 , with access to the Local Processor Bus  300 . Similarly, the Chipset PCI Bridge  380  provides the PCI-to-PCI Bridges  382 ,  384 ,  386 , and  388 , with access to the Local Processor Bus  300 . The specifications of each PCI-to-PCI Bridge ( 342 ,  344 ,  346 ,  348 ,  382 ,  384 ,  386 , and  388 ) are similar to the specifications of the PCI-to-PCI Bridges  242 ,  244 ,  246 , and  248  described in FIG.  2 . Each of the PCI-to-PCI Bridges ( 342 ,  344 ,  346 , and  348 ) provides a connection between two independent PCI buses. The first independent bus is the First PCI Bus  352  which is common to all these PCI-to-PCI bridges. The First PCI Bridge  352  is often referred to as the primary PCI bus in view of its close proximity to the processor  302 . Similarly, each of the PCI-to-PCI Bridges ( 382 ,  384 ,  386 , and  388 ) provides a connection between two independent PCI buses. The first independent bus is common to all these PCI-to-PCI bridges: Second PCI Bus  381  which is referred to as the primary PCI bus in view of its close proximity to the Local Processor Bus  300 . Each PCI-to-PCI bridge has its unique secondary PCI bus. A first set of unique PCI buses is the Secondary PCI Buses  354 ,  355 ,  356 , and  357 . These PCI buses are secondary PCI buses because they are farthest from the Local Processor Bus  300 . A second set of unique PCI buses is the Secondary PCI Buses  394 ,  395 ,  396 , and  397 . These PCI buses are secondary PCI buses because they are farthest from the Local Processor Bus  300 . 
     Each of the PCI-to-PCI Bridges ( 342 ,  344 ,  346 ,  348 ,  382 ,  384 ,  386 , and  388 ) supports up to four PCI bus master devices on its respective Secondary PCI Bus ( 354 ,  355 ,  356 ,  357 ,  394 ,  395 ,  396 , and  397 ). Each of the Secondary PCI Buses  354 ,  355 ,  356 , and  357 , supports four add-in board connectors  350  (the “PCI Card Slots”) to provide access for PCI devices to the Local Processor Bus  300 . Similarly, each of the Secondary PCI Buses  394 ,  395 ,  396 , and  397  supports four add-in board connectors  390  (the “PCI Card Slots”) to provide access for PCI devices to the Local Processor Bus  300 . The specifications of each PCI Card Slot  350  and  390  are preferably similar to the specifications of the PCI Card Slots  250  described in FIG.  2 . Arbitration is provided to coordinate data transfers among PCI devices in the same manner described in FIG.  2 . 
     The PCI architecture of each of the Chipset PCI Bridge  340  and  380  may optionally be identical to or different from the other. More particularly, if the PCI Card Slots  350  and  390  are supporting substantially identical PCI devices, a substantially symmetric PCI bridge architecture is achieved. A key advantage of such a symmetric architecture includes the redundant or fault-tolerant characteristic of a PCI signal path. For instance, if the Chipset PCI Bridge  340  fails, or any or all of its PCI-to-PCI bridges fail, the availability of the Chipset PCI Bridge  380  ensures access between the PCI Card Slots  390  and the Local Processor Bus  300 . Similarly, if the Chipset PCI Bridge  380  fails, or any or all of its PCI-to-PCI bridges fail, the availability of the Chipset PCI Bridge  340  ensures access between the PCI Card Slots  350  and the Local Processor Bus  300 . Moreover, in view of the availability of an alternative signal path between PCI devices and the Local Processor Bus  300 , the possibility of a single-point failure is minimized. A single-point failure is defined as a failure occurring at a single point in the system wherebecause the entire system fails. 
     From the standpoint of the Local Processor Bus  300 , the loading of each of the Chipset PCI Bridges  340 ,  360 , and  380  with all its supported PCI devices are considered one load. Using this PCI bridge architecture, the loading capacity of the Local Processor Bus  312  is not violated. More importantly, the sharing of the PCI signals among the newly created thirty-two PCI Card Slots  350  and  390  does not compromise the system signal integrity. 
     In view of the foregoing, it will be appreciated that the invention overcomes the longstanding need for expanding the loading capacity of a PCI bus without the disadvantages of compromising system signal integrity. The invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive and the scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.