Abstract:
A monolithic semiconductor device is constructed by a plurality of repetitive cells each including one circuit section and one current source for supplying a current to said circuit section, and a plurality of first impedance circuits, each connected between the current sources of two of the repetitive cells, for reducing the effect of cell mismatches among the repetitive cells.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a monolithic semiconductor device (chip) including repetitive cells.  
           [0003]    2. Description of the Related Art  
           [0004]    For example, a flash or parallel-type analog/digital (A/D) converter is constructed by a large number of repetitive cells. That is, such an A/D converter is constructed by comparators for comparing an analog input voltage with reference voltages, latch circuits for latching the output signals of the comparators, and a binary encoder for encoding the output signals of the latch circuits. In this case, the comparators form repetitive cells in a monolithic semiconductor device. Each of the comparators is constructed by one differential pair and one current source for supplying a current thereto. This will be explained later in detail.  
           [0005]    In the above-mentioned A/D converter, when mismatches resulting from deviations from nominal occur between the repetitive cells, the differential and integral linearity would deteriorate.  
           [0006]    In order to suppress the above-mentioned mismatches between the repetitive cells, an impedance network such as a resistor is connected between outputs of differential pairs (see: U.S. Pat. No. 5,175,550). This also will be explained later in detail.  
           [0007]    In the above-described prior art, however, although the mismatches resulting from deviations from nominal occurring between the differential pairs of the comparators can be suppressed, the mismatches resulting from deviations from nominal occurring between the current sources of the comparators cannot be suppressed, which still would deteriorate the differential and integral linearity of the above-mentioned A/D converter.  
         SUMMARY OF THE INVENTION  
         [0008]    It is an object of the present invention to provide a monolithic semiconductor device capable of suppressing mismatches between repetitive cells, particularly, between their current sources.  
           [0009]    According to the present invention, a monolithic semiconductor device is constructed by a plurality of repetitive cells. Each of the repetitive cells includes one circuit section and one current source for supplying a current to the circuit section. Also, a plurality of impedance circuits are connected between the current sources of two of the repetitive cells, to reduce the effect of cell mismatches among the repetitive cells. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein:  
         [0011]    [0011]FIG. 1 is a circuit diagram illustrating a 3-bit flash or parallel-type A/D converter to which a first prior art monolithic semiconductor device is applied;  
         [0012]    [0012]FIG. 2 is a detailed block circuit diagram of the monolithic semiconductor device of FIG. 1;  
         [0013]    [0013]FIG. 3 is an equivalent circuit diagram for explaining the operation of the monolithic semiconductor device of FIG. 2;  
         [0014]    [0014]FIG. 4 is a circuit diagram illustrating a 3-bit flash or parallel A/D converter to which a second prior art monolithic semiconductor device is applied;  
         [0015]    [0015]FIG. 5 is a detailed block circuit diagram of the monolithic semiconductor device of FIG. 4;  
         [0016]    [0016]FIGS. 6A and 6B are equivalent circuit diagrams for explaining the operation of the monolithic semiconductor device of FIG. 5;  
         [0017]    [0017]FIG. 7 is a circuit diagram illustrating a 3-bit flash or parallel A/D converter to which a first embodiment of the monolithic semiconductor device according to the present invention is applied;  
         [0018]    [0018]FIG. 8 is a detailed block circuit diagram of the monolithic semiconductor device of FIG. 7;  
         [0019]    [0019]FIGS. 9, 10 and  11  are equivalent circuit diagrams for explaining the operation of the monolithic semiconductor device of FIG. 8;  
         [0020]    [0020]FIG. 12 is a circuit diagram illustrating a 3-bit flash or parallel A/D converter to which a second embodiment of the monolithic semiconductor device according to the present invention is applied; and  
         [0021]    [0021]FIG. 13 is a detailed block circuit diagram of the monolithic semiconductor device of FIG. 12. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0022]    Before the description of the preferred embodiments, prior art monolithic semiconductor devices will be explained with reference to FIGS. 1, 2,  3 ,  4 ,  5 ,  6 A and  6 B.  
         [0023]    In FIG. 1, which illustrates a 3-bit flash or parallel-type A/D converter to which a first prior art monolithic semiconductor device is applied, reference numerals  1 - 0 ,  1 - 1 , . . . ,  1 - 7  designate comparators for comparing an analog input voltage V in  with reference voltages V REF0 , V REF1 , . . . V REF7 , respectively, which are generated from a resistor string circuit  2  powered by two voltages VRT and VRB. Also, latch circuits  3 - 0 ,  3 - 1 , . . . ,  3 - 7  are connected to the comparators  1 - 0 ,  1 - 1 , . . . ,  1 - 7 , respectively, to latch the output signals of the comparators  1 - 0 ,  1 - 1 , . . . ,  1 - 7  and generate binary output signals B 0 , B 1 , . . . , B 7  which are supplied to a binary encoder  4 . Note that the comparators  1 - 0 ,  1 - 1 , . . . ,  1 - 7  form repetitive cells integrated in a monolithic semiconductor device.  
         [0024]    In FIG. 2, which is a detailed block circuit of the monolithic semiconductor device of FIG. 1, each of the comparators  1 - 1 ,  1 - 2 , . . . ,  1 - 7  is constructed by one differential pair  10   i  (i=0, 1, . . . , 7) formed by N-channel MOS transistors Q 1  and Q 2  having a common source, and resistors R 1  connected to drains of the transistors Q 1 and Q   2 , respectively, and one current source  20   i  (i=0, 1, . . . , 7).  
         [0025]    The operation of the monolithic semiconductor device of FIG. 2 is explained next with reference to FIG. 3 where there are a large number of comparators (cells) that are indefinite in extent.  
         [0026]    In FIG. 3, assume that a current flowing through the differential pair or current source of a specified comparator  1 - i  is deviated from nominal and can be defined as I+ΔI or I+δI where ΔI or δI is an error current. Here, the current flowing through the differential pair is defined as the sum of currents flowing through the transistors Q 1 and Q   2 . In this case, since the error current ΔI or δI is never dispersed into the other comparators (cells), ΔI=δI. Therefore, mismatches resulting from deviations from nominal occurring between the cells remain. For example, differences in output common voltage or output dynamic response between the cells would remain because the current of each cell changes independently. This would deteriorate the differential and integral linearity of the A/D converter of FIG. 1.  
         [0027]    In FIG. 4, which illustrates a 3-bit flash or parallel-type A/D converter to which a second prior art monolithic semiconductor device is applied, resistors R 2  as impedance circuits are connected between the outputs of the comparators  1 - 0 ,  1 - 1 , . . . ,  1 - 7  of FIG. 1 (see: U.S. Pat. No. 5,175,550). That is, as illustrated in FIG. 5, which is a detailed block circuit diagram of the monolithic semiconductor device of FIG. 4, the output OUTP of one differential pair  10   i  is connected via the resistor R 2  to the output OUTP of its adjacent differential pair  10   i - 1  or  10   i+ 1. Also, the output OUTN of one differential pair of  10   i  is connected via the resistor R 2  to the output OUTN of its adjacent differential pair  10   i - 1  and  10   i+ 1.  
         [0028]    The operation of the monolithic semiconductor device of FIG. 5 is explained next with reference to FIG. 6 where there are a large number of comparators (cells) as indefinite in extent. FIG. 6A is a half circuit of FIG. 5 where only one branch of each differential pair (Q 1 ) is shown. On the other hand, FIG. 6B is a full circuit of FIG. 5 where both branches of each pair (Q 1  and Q 2 ) is shown.  
         [0029]    In FIG. 6A, assume that a current flowing through the transistor Q 1  of the differential pair of a specified comparator  1 - i  is deviated from nominal and can be defined as I/2+δI where δI is an error current. In this case, since the error current δI is dispersed via the resistors R 2  into the other comparators (cells), mismatches resulting from deviations from nominal occurring between the cells can be suppressed, which would improve the differential and integral linearity of the A/D converter of FIG. 4.  
         [0030]    In FIG. 6B, another equivalent circuit of FIG. 5 is shown. In FIG. 6B, assume that a current flowing through the differential pair or current source of a specified comparator  1 - i  is deviated from nominal and can be defined as I+ΔI or I+δI where ΔI or δI is an error current. Here, the current flowing through the differential pair is defined as the sum of the current flowing through Q 1  and Q 2 . In this case, since the error current ΔI or δI is never dispersed into the other comparators (cells), ΔI=δI. Therefore, mismatches resulting from deviations from nominal occurring between the cells remain. For example, differences in output common voltages or output dynamic responses between the cells would remain because the current of each cell changes independently. This would deteriorate the differential and integral linearity of the A/D converter of FIG. 4. In FIG. 4, although the mismatches resulting from deviations from nominal occurring between the differential pairs  100 ,  101 , . . . ,  107  of the cells can be suppressed, mismatches resulting deviations from nominal occurred between the current sources  200 ,  201 , . . . ,  207  cannot be suppressed.  
         [0031]    In FIG. 7, which illustrates a 3-bit flash or parallel-type A/D converter to which a first embodiment of the monolithic semiconductor device according to the present invention is applied, resistors R 3  as impedance circuits are connected between the comparators  1 - 0 ,  1 - 1 , . . . ,  1 - 7  of FIG. 1. In this case, it is preferable that the resistors R 3  have the same value. In more detail, as shown in FIG. 8, the resistors R 3  are connected between nodes N 0 , N 1 , . . . , N 7  of the differential pairs  100 ,  101 , . . . ,  107  and the constant current sources  200 ,  201 , . . . ,  207 .  
         [0032]    The operation of the monolithic semiconductor device of FIG. 8 is explained next with reference to FIGS. 9, 10 and  11  where there are a large number of comparators (cells) that are indefinite in extent.  
         [0033]    In FIG. 9, assume that a current flowing through the constant current source of a specified comparator (i=0) is deviated from nominal and can be defined as I+δI where δI is an error current. V(−4), V(−3), V(−2), V(−1), V(0), V(1), V(2), V(3), V(4), . . . are defined as respective voltages at the common nodes of the differential pairs, and W(−4), W(−3), W(−2), W(−1), W(0), W(1), W(2), W(3), W(4), . . . are defined as respective voltages of the output common voltages of the differential pairs.  
         [0034]    The analysis of only the error current δI can be carried out by the principle of superposition. That is, in FIG. 10, ΔI(−4), ΔI(−3), ΔI(−2), ΔI(−1), ΔI(0), ΔI(1), ΔI(2), ΔI(3), ΔI(4), . . . are defined as error currents flowing through the respective differential pairs of the comparators  1 - i  (i=−4, −3, −2, −1, 0, 1, 2, 3, 4, . . . ), and dV(−4), dV(−3), dV(−2), dV(−1), dV(0), dV(1), dV(2), dV(3), dV(4), . . . are defined as respective voltage changes at the common nodes of the differential pairs of the comparators  1 - i  (i=−4, −3, −2, −1, 0, 1, 2, 3, 4, . . . ) caused by δI. In FIG. 10, the differential pairs (Q 1 , Q 2 ) and the load resistors R 1  are replaced as an equivalent circuit comprising bias voltage source BIAS(−4), BIAS(−3), BIAS(−2), BIAS(−1), BIAS(0), BIAS(1), BIAS(2), BIAS(3), BIAS(4) and output resistors R 4 .  
         [0035]    As shown in FIG. 11, it is reasonable that the impedance R X  from every node is the same. As a result,  
           R   X   =R   3 +( R   4   //R   X )  
         ∵ R   X   ={R   3 +(R 3   2 +4 ·R   3   ·R   4 ) 1/2 }/2  
         [0036]    At the comparator (i=0), an error current ΔI(0) of the differential pair caused by the error current δI can be represented by  
         Δ I (0)={( R   4   //R   X   //R   X )/ R   4   }·δI    
         [0037]    Therefore, the deviation δW(0) of the output common voltage of the differential pair can be represented by  
         δ W (0)=( R   4   //R   X   //R   X )·δ½ 
         [0038]    At the comparators (i=1 or −1),  
         Δ I (1)=Δ I (−1)= r·ΔI (0)  
         δ W (1)=δ W (−1)= r·δW (0)  
         [0039]    where r=(R 4 //R X )/R X    
         [0040]    Similarly, at the comparators (i=2 or −2),  
         Δ I (2)=Δ I (−2)= r   2   ·ΔI (0)  
         δ W (2)=δ W (−2)= r   2   ·δW (0)  
         [0041]    Generally, at the comparators (i=n or −n),  
         Δ I ( n )=Δ I (− n )= r   n   ·ΔI (0)  
         δ W ( n )=δ W (− n )= r   n   ·δW (0)  
         [0042]    Thus, as the error current δI caused by the current source of the comparator  1 - i  (i=0) is dispersed via the resistors R 3  into its adjacent comparators (cells), and the current flowing through each differential pair becomes nearly the same value. Therefore, differences in output voltage or output dynamic response between the cells are suppressed and mismatches resulting from deviation from nominal occurring between the cells can be suppressed, which would improve the differential and integral linearity of the A/D converter of FIG. 7.  
         [0043]    In FIG. 12, which illustrates a 3-bit flash or parallel-type A/D converter to which a second embodiment of the monolithic semiconductor device according to the present invention is applied, the resistors R 2  of FIG. 4 as impedance circuits are added to the elements of FIG. 7. In more detail, as shown in FIG. 13, the resistors R 2  are connected between the outputs OUTP of the differential pairs  100 ,  101 , . . . ,  107  and between the outputs OUTN of the differential pairs  100 ,  101 , . . . ,  107 .  
         [0044]    In FIGS. 12 and 13, differences in output voltage or output dynamic response between the cells are suppressed by the resistors R 3 , and also, the mismatches resulting from deviation from nominal occurring between the cells are suppressed by the resistors R 2 . Thus, the differential and integral linearity of the A/D converter would be further improved.  
         [0045]    In the above-described embodiments, the differential pairs can be formed by bipolar transistors. Also, the present invention can be applied to other repetitive cells than the comparators of a flash or parallel-type A/D converter, such as a memory cell, a gate array, a logic gate or a register having differential pairs and constant current sources.  
         [0046]    As explained hereinabove, according to the present invention, mismatches between repetitive cells can be suppressed.