Abstract:
An echo signal processing apparatus is disclosed. The echo signal processing apparatus is utilized for generating a cancellation signal by using group phenomenon of a frequency response of an echo signal to remove the echo signal. The echo signal processing apparatus has lower cost and is able to remove the echo efficiently.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a communication system, and more particularly, to a communication system having an echo cancellation apparatus. 
         [0003]    2. Description of the Prior Art 
         [0004]    In communication systems, part of a transmission signal transmitted by a transmitter will be coupled to a receiving signal received by a receiver, which is the so-called signal echo phenomenon. The signal echo phenomenon will affect the receiving performance of the receiver. In addition, the energy magnitude and shape of an echo signal depend on the transmission channel; that is, each transmission channel has a corresponding echo response. Generally speaking, the prior art design implements an echo canceller (EC) in the receiver. Ideally, the echo canceller will generate an echo cancellation signal, which is an inverse version of the echo signal and has a magnitude identical to that of the echo signal. Therefore, both signals will achieve echo cancellation, allowing the receiver to receive a cleaner receiving signal. 
         [0005]    In general, the prior art design utilizes a digital filter to realize the echo canceller, where a digital filter with more taps can remove the echo signal more effectively. However, each tap includes a delay cell, a multiplier and an adder, wherein the multiplier requires a larger circuit area. In other words, the digital filter with more taps means a higher hardware cost. Therefore, how to design an echo canceller with lower hardware cost and/or remove the echo signal more effectively is an urgent issue for designers/manufacturers. 
       SUMMARY OF THE INVENTION 
       [0006]    Therefore, one of the objectives of the present invention is to provide an echo processing apparatus for removing an echo signal, and a related method. 
         [0007]    According to an embodiment of the present invention, an echo processing apparatus is disclosed. The echo processing apparatus is used for generating an echo cancellation signal to remove an echo signal, wherein the echo signal includes a first response and a second response. The echo processing apparatus includes: a first signal processing circuit, for generating a first echo cancellation signal substantially corresponding to the first response; a second signal processing circuit, for generating a second echo cancellation signal substantially corresponding to the second response, wherein the first response and the second response are at different times; and a summing circuit, for summing up the first echo cancellation signal and the second echo cancellation signal to generate the echo cancellation signal. 
         [0008]    According to an embodiment of the present invention, a method for generating an echo cancellation signal is disclosed. The echo cancellation signal is used for cancelling an echo signal, which includes a first response and a second response. The method includes: generating a first echo cancellation signal substantially corresponding to the first response; generating a second echo cancellation signal substantially corresponding to the second response, wherein the first response and the second response are at different times; and summing up the first echo cancellation signal and the second echo cancellation signal to generate the echo cancellation signal. 
         [0009]    As the present invention utilizes the group phenomenon of the impulse response of the echo signal to design the echo signal processing apparatus, the echo signal processing apparatus of the present invention therefore can use less taps to achieve the objective of removing the echo signal. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating a frequency response of an echo signal. 
           [0012]      FIG. 2  is a diagram illustrating an echo cancellation circuit according to an embodiment of the present invention. 
           [0013]      FIG. 3  is a diagram illustrating an embodiment of a signal processing circuit shown in  FIG. 2  according to the present invention. 
           [0014]      FIG. 4  is a diagram illustrating an embodiment of a delay circuit in the echo cancellation circuit shown in  FIG. 2  according to the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    The inventors of the present invention observe that the impulse response of the echo signal should have the characteristic shown in  FIG. 1 . If a prior art echo canceller is employed to remove such a long echo response shown in  FIG. 1 , a large number of taps is required. As shown in  FIG. 1 , the echo response will have group phenomenon, such as a plurality of responses  100   a - 100   g  included therein, where the responses (i.e. amplitude) between the groups are very small. Thus, the present invention purposely ignores the responses between groups. The group phenomenon of the echo response is mainly induced by the impedance mismatch. Taking a twist-pair for example, the impedance mismatch commonly occurs at the twist-pair sections (i.e., between the connections of the wires). However, the length and the number of the twist-pair sections are well-defined in the system, and the number and size of the groups can be controlled. 
         [0016]      FIG. 2  is a diagram illustrating an echo cancellation circuit  200  according to an embodiment of the present invention.  FIG. 2  further shows a transmitter  202 , a receiver  204 , and a transmission channel  206 . The transmitter  202  transmits a transmission signal X[n] to the transmission channel  206 . The echo signal will reflect to receiver  204  via the transmission channel  206 . The echo cancellation circuit  200  generates an echo estimation signal Y[n] according to the transmission signal X[n]. The receiver  204  is used for receiving a received signal E[n] from the transmission channel  206  and the echo estimation signal Y[n] from the echo cancellation circuit  200  to generate a processed signal R[n]. The echo cancellation circuit  200  includes a plurality of signal processing circuits  200   a - 200   g , a plurality of delay circuits  300   a - 300   f , a delay control circuit  400  and a summing circuit  500 . The signal processing circuit  200   a  is used for generating a first echo estimation signal Y 1 [n] according to the transmission signal X[n], and delaying the transmission signal X[n] to generate a first delay signal X 1 [n]. The delay circuit  300   a  is used for delaying the first delay signal X 1 [n] by a specific delay time T 1  to generate a second delay signal X 2 [n]. The signal processing circuit  200   b  is used for generating a second echo estimation signal Y 2 [n] according to the second delay signal X 2 [n]. As other signals are processed according to the above-mentioned rules, the following signal processing circuits and the operations of the delay circuits are omitted here for brevity. The summing circuit  500  is coupled to the plurality of signal processing circuits  200   a - 200   g , for generating the echo estimation signal Y[n] according to a plurality of echo estimation signals Y 1 [n]-Y g [n]. The summing circuit  500  is implemented using a plurality of adders. The delay control circuit  400  is used for controlling a plurality of specific delay times T 1 -T f  of a plurality of delay circuits  300   a - 300   f , respectively. 
         [0017]    The delay control circuit  400  includes a delay setting block  400   a.  The delay setting block  400   a  is used for controlling a plurality of delay circuits  300   a - 300   f  having a plurality of candidate delay times Tx 1 -Tx f , respectively. Then, the delay setting block  400   a  dynamically adjusts the candidate delay time of each delay circuit. The delay control circuit  400  further includes a calculating block  400   b,  coupled to a plurality of signal processing circuits  200   a - 200   g  which are employed for calculating a plurality of calculation results respectively corresponding to the candidate delay times Tx 1 -Tx f  according to parameter settings to which the signal processing circuits  200   a - 200   g  correspond when the delay circuits  300   a - 300   f  dynamically utilize the candidate delay times Tx 1 -Tx f , respectively. Finally, the delay setting block  400   a  further determines a plurality of specific delay times T 1 -T f  corresponding to the candidate delay times Tx 1 -Tx f  according to the calculation results. 
         [0018]      FIG. 3  is a diagram illustrating an embodiment of the signal processing circuit  200   a  shown in  FIG. 2  according to the present invention. For brevity, the signal processing circuit is for illustrative purposes only, and the signal processing circuit  200   a  of this embodiment is implemented by a digital filter (e.g., a finite impulse response (FIR) filter), and operations of other signal processing circuits  200   b - 200   g  are similar to that of the signal processing circuit  200   a.  The signal processing circuit  200   a  includes a plurality of delay cells D — 0-D_N−2, a plurality of multipliers C — 0-C_N−1 and a plurality of adders A — 0-A_N−2, wherein the value of N indicates the tap number of the digital filter. The calculating block  400   b  will set a plurality of parameters C a,0 -C a,n−1 , and provide them to a plurality of multipliers C — 0-C_N−1, respectively. 
         [0019]    According to an embodiment of the present invention, the signal processing circuits  200   a - 200   g  are used for processing a plurality of corresponding responses  100   a - 100   g  respectively (to generate a plurality of corresponding echo estimation signals Y 1 [n]-Y g [n]), as shown in  FIG. 1  and  FIG. 2 . In other words, the echo estimation signals Y 1 [n]-Y g [n] are used for removing the corresponding responses  100   a - 100   g,  respectively. To more precisely remove the responses  100   a - 100   g  from the signal, the specific delay times T 1 -T f  respectively corresponding to the delay circuits  300   a - 300   f  need to be calculated precisely. 
         [0020]    First, the calculating block  400   b  performs a training mechanism on each of the signal processing circuits  200   a - 200   g  to calculate parameter(s) of each signal processing circuit. Taking the signal processing circuit  200   a  for example, the calculating block  400   b  will perform the training mechanism on the signal processing circuit  200   a  to determine the parameters C a,0 -C a,n−1 , and then the signal processing circuit  200   a  can utilize the parameters C a,0 -C a,n−1  to generate the cancellation amount corresponding to the response  100   a.  By analogy, the parameters of each signal processing circuit can be determined when the delay circuits  300   a - 300   f  have candidate delay times Tx 1 -Tx f , respectively. Then, the delay setting block  400   a  dynamically adjusts the delay time of each delay circuit between the signal processing circuits  200   a - 200   g , e.g. the delay setting block  400   a  dynamically adjusts the candidate delay time Tx 1  of the delay circuit  300   a , for maximizing the total cancellation amount of the signal processing circuits  200   a - 200   g.  Finally, the calculating block  400   b  will find the maximum total cancellation amount of the signal processing circuits  200   a - 200   g  when the delay times of the delay circuits  300   a - 300   f  are specific delay times (i.e., T 1 -T f ), respectively. Therefore, compared to the prior art echo canceller design, the echo cancellation circuit  200  of the present invention can implement fewer taps to achieve the same echo cancellation effect; or when the echo cancellation circuit  200  of the present invention has the same number of taps as the prior art echo canceller, the echo cancellation circuit  200  can remove a longer echo response. 
         [0021]    In addition, how the delay setting block  400   a  adjusts the delay time of each delay circuit between the signal processing circuits  200   a - 200   g  is not limited in the present invention. The calculating block  400   b  will calculate the cancellation amount of each signal processing circuit that is applied to the echo signal E[n]block when the delay setting block  400   a  sets different delay times. Then, the calculating block  400   b  can calculate the total cancellation amount of the signal processing circuits  200   a - 200   g  that is applied to the echo signal E[n]. Therefore, the echo cancellation circuit  200  can remove the maximum portion of the echo signal E[n] when the delay times of the delay circuits  300   a - 300   f  are predetermined delay times T 1 -T f , respectively. 
         [0022]    According to an embodiment, each time respectively setting delay times of the delay circuits  300   a - 300   f , the calculating block  400   b  will sum up the absolute values of all parameters determined by the training mechanism, i.e., 
         [0000]    
       
         
           
             
               ∑ 
               
                 k 
                 = 
                 0 
               
               
                 M 
                 - 
                 1 
               
             
              
             
               
                 ∑ 
                 
                   i 
                   = 
                   0 
                 
                 
                   N 
                   - 
                   1 
                 
               
                
               
                 
                    
                   
                     C 
                     
                       k 
                       . 
                       i 
                     
                   
                    
                 
                 . 
               
             
           
         
       
     
         [0000]    According to another embodiment, the total cancellation amount of the signal processing circuits  200   a - 200   g  that is applied to the echo signal E[n] is determined by a calculation result, which is a sum of square values of all parameters of the signal processing circuits  200   a - 200   g , i.e. 
         [0000]    
       
         
           
             
               
                 ∑ 
                 
                   k 
                   = 
                   0 
                 
                 
                   M 
                   - 
                   1 
                 
               
                
               
                 
                   ∑ 
                   
                     i 
                     = 
                     0 
                   
                   
                     N 
                     - 
                     1 
                   
                 
                  
                 
                   
                      
                     
                       C 
                       
                         k 
                         . 
                         i 
                       
                     
                      
                   
                   2 
                 
               
             
             , 
           
         
       
     
         [0000]    where M is the number of the signal processing circuits  200   a - 200   g , n is the number of taps of each signal processing circuit, k=0˜M−1, i=0˜N−1, and C a,0  is the coefficient of the k th  tap in the i th  signal processing circuit. Therefore, the calculating block  400   b  can get a set of parameters corresponding to a maximum accumulation result via dynamically and iteratively adjusting the delay times of the delay circuits  300   a - 300   f  and performing the training mechanism on the signal processing circuits  200   a - 200   g.    
         [0023]    In addition, adjusting the delay times of the delay circuits  300   a - 300   f  can be accomplished by other means, such as utilizing the microprocessor, firmware, software, or a combination thereof. 
         [0024]      FIG. 4  is a diagram illustrating an embodiment of a delay circuit of the echo cancellation circuit  200  shown in  FIG. 2 . The delay circuit  300   a  is illustrated for illustrative purposes. In this embodiment, the delay circuit is implemented by a pure delay line. After reading the description of the delay circuit  300   a,  the corresponding operations of the other delay circuits  300   b - 300   f  should be readily appreciated by those skilled in the art. The delay circuit  300   a  is implemented by a pure delay line (which comprises a plurality of cascaded pure delay cells  3002 - 3008 ) and a multiplexer  3010 , wherein the delay setting block  400   a  generates a delay control signal Sda to the delay circuit  300   a  according to the specific delay time T 1 . To put it simply, the specific delay time T 1  determines the delay control signal Sda to thereby select the required delay signal transmission X 2 [n] from the output signals X 1d [n], X 2d [n], X 3d [n] of the delay cells. 
         [0025]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.