Abstract:
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation of U.S. patent application Ser. No. 13/407,085, filed Feb. 28, 2012, which is a continuation of U.S. patent application Ser. No. 11/603,935, filed Nov. 22, 2006, all of which are hereby incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present invention relates to packaged semiconductor chips and to methods of manufacture thereof. 
       BACKGROUND OF THE INVENTION 
       [0003]    The following published patent documents are believed to represent the current state of the art: 
         [0004]    U.S. Pat. Nos. 6,737,300; 6,828,175; 6,608,377; 6,103,552; 6,277,669; 6,492,201; 6,498,387; 6,727,576; 6,743,660 and 6,867,123; and 
         [0005]    US Patent Application Publication Numbers: 2005/0260794, which issued as U.S. Pat. No. 7,329,563; 2006/0017161; 2005/0046002, which issued as U.S. Pat. No. 7,276,799; 2005/0012225; 2002/0109236, which issued as U.S. Pat. No. 6,448,661; 2005/0056903, which issued as U.S. Pat. No. 7,180,149; 2004/0222508; 2006/0115932 and 2006/0079019, which issued as U.S. Pat. No. 7,264,995. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention seeks to provide improved packaged semiconductor chips and methods of manufacture thereof. 
         [0007]    There is thus provided in accordance with a preferred embodiment of the present invention, a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device. 
         [0008]    In accordance with a preferred embodiment of the present invention, the semiconductor wafer contains at least one of silicon and Gallium Arsenide. Preferably, the packaging layer is adhered to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. Additionally or alternatively, the packaging layer includes silicon. 
         [0009]    In accordance with another preferred embodiment of the present invention, the chip-sized wafer level packaged device also includes at least one compliant layer formed over the packaging layer and underlying the ball grid array. Preferably, the chip-sized wafer level packaged device also includes metal connections formed over the compliant layer and underlying the ball grid array, the metal connections providing electrical contact between the ball grid array and the device. 
         [0010]    In accordance with yet another preferred embodiment of the present invention the device includes a memory device. Preferably, alpha-particle shielding is provided between the ball grid array and the device. More preferably, the alpha-particle shielding is provided by at least one compliant layer formed over the packaging layer and underlying the ball grid array. Additionally or alternatively, the chip-sized wafer level packaged device also includes metal connections formed over the packaging layer and underlying the ball grid array, the metal connections providing electrical contact between the ball grid array and the device. 
         [0011]    There is also provided in accordance with another preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a semiconductor wafer including a multiplicity of devices, forming a packaging layer over the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer, forming ball grid arrays over a surface of the packaging layer, the ball grid arrays being electrically connected to ones of the multiplicity of devices and dicing the semiconductor wafer and the packaging layer. 
         [0012]    In accordance with a preferred embodiment of the present invention the providing a semiconductor wafer includes providing a semiconductor wafer containing at least one of silicon and Gallium Arsenide. Preferably, the method also includes adhering the packaging layer to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. Additionally or alternatively, the forming a packaging layer includes forming a silicon packaging layer. 
         [0013]    In accordance with another preferred embodiment of the present invention the method also includes forming at least one compliant layer over the packaging layer prior to forming the ball grid arrays. Preferably, the forming at least one compliant layer includes forming at least one electrophoretic layer. Additionally or alternatively, the forming at least one compliant layer includes providing alpha-particle shielding between the ball grid array and the surface. 
         [0014]    In accordance with still another preferred embodiment of the present invention the multiplicity of devices include a memory device. Preferably, the method also includes providing alpha-particle shielding between the ball grid array and the surface. Additionally or alternatively, the method also includes forming metal connections over the packaging layer and underlying the ball grid array, the metal connections providing electrical contact between the ball grid array and the device. 
         [0015]    There is additionally provided in accordance with yet another preferred embodiment of the present invention a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, a compliant layer formed over the packaging layer at at least some locations thereon and a ball grid array formed over a surface of the packaging layer and over the compliant layer and being electrically connected to the device. 
         [0016]    In accordance with a preferred embodiment of the present invention the packaging layer includes a material having thermal expansion characteristics similar to those of the semiconductor wafer. Preferably, the compliant layer is provided at locations underlying individual balls of the ball grid array. Additionally or alternatively, the compliant layer may include silicone. 
         [0017]    In accordance with another preferred embodiment of the present invention the device is a DRAM device. Preferably, the compliant layer includes platforms formed of compliant material, each of the platforms having formed thereon a ball of the ball grid array. Additionally or alternatively, the chip-sized wafer level packaged device also includes metal connections formed over the compliant layer and underlying the ball grid array, the metal connections providing electrical contact between the ball grid array and the device. Preferably, alpha-particle shielding is provided between the ball grid array and the device. 
         [0018]    There is further provided in accordance with a further preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged integrated circuit devices including providing a semiconductor wafer including a multiplicity of integrated circuit devices, forming a packaging layer over the semiconductor wafer, forming recesses in a replication silicon wafer in a planar arrangement corresponding to that of a desired ball grid array, placing compliant material in the recesses thereby to define an array of regions of the compliant material, planarizing the array of regions of the compliant material, attaching the silicon wafer over the packaging layer, such that planarized surfaces of the array of regions of the compliant material lie over and facing the packaging layer, removing the replication silicon wafer such that the array of regions of the compliant material remain, forming ball grid arrays over the array of regions of the compliant material, the ball grid arrays being electrically connected to the ones of the multiplicity of integrated circuit devices and dicing the semiconductor wafer and the packaging layer. 
         [0019]    In accordance with a preferred embodiment of the present invention the forming a packaging layer includes a forming a packaging layer of a material having thermal expansion characteristics similar to those of the semiconductor wafer. Preferably, the forming a packaging layer includes forming a packaging layer of silicon. Additionally or alternatively, the placing compliant material includes placing silicone. 
         [0020]    In accordance with another preferred embodiment of the present invention the multiplicity of integrated circuit devices includes at least one DRAM device. Preferably, the method also includes forming metal connections the compliant material prior to the forming ball grid arrays, the metal connections providing electrical contact between the ball grid arrays and ones of the multiplicity of integrated circuit devices. 
         [0021]    In accordance with yet another preferred embodiment of the present invention the method also includes forming a compliant electrophoretic coating layer over the packaging layer prior to the attaching the replication silicon wafer. Preferably, the forming a compliant electrophoretic coating layer includes providing alpha-particle shielding between the ball grid arrays and the integrated circuit devices. 
         [0022]    There is yet further provided in accordance with a yet further preferred embodiment of the present invention a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a passivation layer formed over the portion of the semiconductor wafer, a compliant layer formed over the passivation layer at at least some locations thereon and a ball grid array formed over a surface of the passivation layer and over the compliant layer and being electrically connected to the device. 
         [0023]    In accordance with a preferred embodiment of the present invention the compliant layer includes silicone. Additionally or alternatively, the passivation layer includes a polymer. Preferably, the passivation layer includes a polyimide. 
         [0024]    In accordance with another preferred embodiment of the present invention the passivation layer provides alpha-particle shielding between the ball grid array and the device. Preferably, the device is a DRAM device. Additionally or alternatively, the chip-sized wafer level packaged device also includes metal connections formed over the compliant layer and underlying the ball grid array, the metal connections providing electrical contact between the ball grid array and the device. 
         [0025]    There is still further provided in accordance with a still further preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a semiconductor wafer including a multiplicity of devices, forming a passivation layer over the semiconductor wafer, forming a compliant layer over the passivation layer, forming ball grid arrays over a surface of the compliant layer, the ball grid arrays being electrically connected to ones of the multiplicity of devices and dicing the semiconductor wafer and the packaging layer. 
         [0026]    In accordance with a preferred embodiment of the present invention the forming a passivation layer includes forming the passivation layer from a polymer. Preferably, the forming a passivation layer includes forming the passivation layer from a polyimide. Additionally or alternatively, the forming a compliant layer includes forming the compliant layer from silicone. 
         [0027]    In accordance with another preferred embodiment of the present invention the forming a passivation layer includes providing alpha-particle shielding between the ball grid arrays and the device. Preferably, the multiplicity of devices includes at least one DRAM device. Additionally or alternatively, the method also includes forming metal connections over the compliant layer and underlying the ball grid array, the metal connections providing electrical contact between the ball grid array and the device. 
         [0028]    There is additionally provided in accordance with an additional preferred embodiment of the present invention a chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically coupled to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. 
         [0029]    In accordance with a preferred embodiment of the present invention the at least one packaging layer includes a plurality of packaging layers. Preferably, the plurality of packaging layers are disposed on the same side of the portion of the semiconductor wafer. Additionally or alternatively, the device is a DRAM device. 
         [0030]    In accordance with another preferred embodiment of the present invention the chip-sized wafer level packaged device also includes at least one compliant layer, formed over the packaging layer and underlying at least one of the first and second ball grid arrays. Preferably, the chip-sized wafer level packaged device also includes metal connections formed over the at least one compliant layer and underlying at least one of the first and second ball grid arrays, the metal connections providing electrical contact between at least one of the first and second ball grid arrays and the device. Additionally or alternatively, the at least one compliant layer includes at least one of silicone and a polymeric dielectric material. Preferably, the polymeric material is a polyimide. 
         [0031]    In accordance with yet another preferred embodiment of the present invention alpha-particle shielding is provided between at least one of the first and second ball grid arrays and the device. 
         [0032]    There is also provided in accordance with another preferred embodiment of the present invention a chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, a least one packaging layer formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device, a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device and a compliant electrophoretic coating layer underlying at least one of the first and second ball grid arrays. 
         [0033]    In accordance with a preferred embodiment of the present invention the at least one packaging layer contains silicon. Preferably, the compliant electrophoretic coating layer provides alpha-particle shielding between at least one of the first and second ball grid arrays and the device. Additionally or alternatively, the device is a DRAM device. 
         [0034]    In accordance with another preferred embodiment of the present invention the at least one packaging layer includes a plurality of packaging layers. Preferably, the plurality of packaging layers are disposed on the same side of the portion of the semiconductor wafer. Additionally or alternatively, the chip-sized wafer level packaged device also includes metal connections formed over the compliant electrophoretic coating layer and underlying at least one of the first and second ball grid arrays, the metal connections providing electrical contact between at least one of the first and second ball grid arrays and the device. 
         [0035]    In accordance with yet another preferred embodiment of the present invention the compliant electrophoretic coating layer comprises a sufficiently conductive inorganic packaging layer which is electrophoretically coated by an organic layer employing appropriate modulus which provides under-ball compliancy. 
         [0036]    There is additionally provided in accordance with yet another preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a semiconductor wafer including a multiplicity of devices, forming at least one packaging layer including a silicon packaging layer over the semiconductor wafer, forming a first ball grid array over a surface of the at least one packaging layer and being electrically connected to ones of the multiplicity of devices, forming a second ball grid array over a surface of the portion of the semiconductor wafer and being electrically connected to ones of the multiplicity of devices and dicing the semiconductor wafer and the at least one packaging layer. 
         [0037]    In accordance with a preferred embodiment of the present invention the forming at least one packaging layer includes forming a plurality of packaging layers. Preferably, the forming a plurality of packaging layers includes disposing the plurality of packaging layers on the same side of the semiconductor wafer. Additionally or alternatively the multiplicity of devices includes at least one DRAM device. 
         [0038]    In accordance with another preferred embodiment of the present invention the method also includes forming at least one compliant layer over the packaging layer and underlying at least one of the first and second ball grid arrays. Preferably, the method also includes forming metal connections over the at least one compliant layer and underlying at least one of the first and second ball grid arrays, the metal connections providing electrical contact between at least one of the first and second ball grid arrays and the device. Additionally or alternatively, the method also includes providing alpha-particle shielding between at least one of the first and second ball grid arrays and the device. 
         [0039]    There is also provided in accordance with yet another preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a semiconductor wafer including a multiplicity of devices, forming at least one packaging layer over the semiconductor wafer, forming a first ball grid array over a surface of the at least one packaging layer and being electrically connected to ones of the multiplicity of devices, forming a second ball grid array over a surface of the portion of the semiconductor wafer and being electrically connected to ones of the multiplicity of devices, forming a compliant electrophoretic coating layer underlying at least one of the first and second ball grid arrays and dicing the semiconductor wafer and the at least one packaging layer. 
         [0040]    In accordance with a preferred embodiment of the present invention the forming at least one packaging layer includes forming at least one packaging layer which contains silicon. Preferably, the forming a compliant electrophoretic coating layer includes providing alpha-particle shielding between the ball grid arrays and the device. Additionally or alternatively, the multiplicity of devices includes at least one DRAM device. 
         [0041]    In accordance with another preferred embodiment of the present invention the forming at least one packaging layer includes forming a plurality of packaging layers. Preferably, the forming a plurality of packaging layers includes disposing the plurality of packaging layers on the same side of the semiconductor wafer. Additionally or alternatively, the method also includes forming metal connections over the compliant electrophoretic coating layer and underlying at least one of the first and second ball grid arrays, the metal connections providing electrical contact between at least one of the first and second ball grid arrays and ones of the multiplicity of devices. 
         [0042]    There is additionally provided in accordance with still another preferred embodiment of the present invention a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, a ball grid array formed over a surface of the packaging layer and being electrically connected to the device and metal connections interconnecting the ball grid array with the device, the metal connections including first metal connections, each extending from a bond pad of the device at a first location over the portion of the semiconductor wafer to a second location over the portion of the semiconductor wafer, transversely displaced from the first location and second metal connections, each extending from one of the first metal connections at the second location to a ball forming part of the ball grid array. 
         [0043]    In accordance with a preferred embodiment of the present invention the packaging layer includes silicon. Preferably, the chip-sized wafer level packaged device also includes a compliant layer formed over the packaging layer and underlying the ball grid array. Additionally or alternatively, the device includes a memory device. 
         [0044]    In accordance with another preferred embodiment of the present invention alpha-particle shielding is provided between the ball grid array and the device. Preferably, the compliant layer provides alpha-particle shielding between the ball grid array and the device. Additionally or alternatively, the chip-sized wafer level packaged device also includes an encapsulant layer formed between the portion of the semiconductor wafer and the packaging layer. 
         [0045]    There is further provided in accordance with a further preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a semiconductor wafer including a multiplicity of devices, providing a packaging layer over the semiconductor wafer, forming a ball grid array over a surface of the packaging layer and electrically connecting it to ones of the multiplicity of devices by metal connections including forming first metal connections, each extending from a bond pad of the device at a first location over the portion of the semiconductor wafer to a second location over the portion of the semiconductor wafer, transversely displaced from the first location and forming second metal connections, each extending from one of the first metal connections at the second location to a ball forming part of the ball grid array and dicing the semiconductor wafer and the packaging layer. 
         [0046]    In accordance with a preferred embodiment of the present invention the providing a packaging layer includes providing a packaging layer formed of silicon. Preferably, the method also includes forming a compliant layer over the packaging layer and underlying the ball grid array. Additionally or alternatively, the multiplicity of devices includes a memory device. 
         [0047]    In accordance with another preferred embodiment of the present invention the method also includes providing alpha-particle shielding between the ball grid array and the device. Preferably, the forming a compliant layer includes providing alpha-particle shielding between the ball grid array and the device. Additionally or alternatively, the method also includes forming an encapsulant layer between the portion of the semiconductor wafer and the packaging layer. 
         [0048]    There is yet further provided in accordance with yet a further preferred embodiment of the present invention a chip-sized wafer level packaged device including a first portion of a first semiconductor wafer including a first active surface, a second portion of a second semiconductor wafer including a second active surface, the second portion of the second semiconductor wafer being arranged with respect to the first portion of the first semiconductor wafer such that the first and second active surfaces are in a mutually facing spatial relationship, at least one ball grid array formed over a non-active surface of at least one of the first and second portions and metal connections interconnecting the at least one ball grid array with the first and second active surfaces, the metal connections including first metal connections, each extending from a bond pad on one of the first and second active surfaces at a first location over a corresponding one of the first and second portions to a second location over the corresponding one of the first and second portions, transversely displaced from the first location and second metal connections, each extending from one of the first metal connections at the second location to a ball forming part of the at least one ball grid array. 
         [0049]    In accordance with a preferred embodiment of the present invention the chip-sized wafer level packaged device also includes a compliant layer underlying the at least one ball grid array. Preferably, the packaged device includes a memory device. 
         [0050]    In accordance with another preferred embodiment of the present invention alpha-particle shielding is provided between the at least one ball grid array and the first and second active surfaces. Preferably, the compliant layer provides alpha-particle shielding between the at least one ball grid array and the first and second active surfaces. Additionally or alternatively, the packaging layer includes silicon. 
         [0051]    There is still further provided in accordance with a still further preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a first portion of a first semiconductor wafer including a first active surface, providing a second portion of a second semiconductor wafer including a second active surface, arranging the second portion of the second semiconductor wafer with respect to the first portion of the first semiconductor wafer such that the first and second active surfaces are in a mutually facing spatial relationship, forming at least one ball grid array over a non-active surface of at least one of the first and second portions and forming metal connections interconnecting the at least one ball grid array with the first and second active surfaces, including forming first metal connections, each extending from a bond pad on one of the first and second active surfaces at a first location over a corresponding one of the first and second portions to a second location over the corresponding one of the first and second portions, transversely displaced from the first location and forming second metal connections, each extending from one of the first metal connections at the second location to a ball forming part of the at least one ball grid array and dicing the first and second semiconductor wafers. 
         [0052]    In accordance with a preferred embodiment of the present invention the method also includes forming a compliant layer prior to forming the at least one ball grid array. Preferably, the method also includes providing alpha-particle shielding between the at least one ball grid array and the first and second active surfaces. More preferably, the forming a compliant layer includes providing alpha-particle shielding between the at least one ball grid array and the first and second active surfaces. 
         [0053]    There is additionally provided in accordance with an additional preferred embodiment of the present invention stacked chip-sized, wafer level packaged devices including at least first and second chip-sized wafer level packaged devices each including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device, the first ball grid array of the first device being electrically connected to the second ball grid array of the second device. 
         [0054]    In accordance with a preferred embodiment of the present invention the at least one packaging layer includes a plurality of packaging layers. Preferably, the plurality of packaging layers are disposed on the same side of the portion of the semiconductor wafer. Additionally or alternatively, the device is a DRAM device. 
         [0055]    There is also provided in accordance with another preferred embodiment of the present invention stacked chip-sized, wafer level packaged devices including at least first and second chip-sized wafer level packaged devices each including a portion of a semiconductor wafer including a device, at least one packaging layer formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device, a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device and a compliant electrophoretic coating layer underlying at least one of the first and second ball grid arrays, the first ball grid array of the first device being electrically connected to the second ball grid array of the second device. 
         [0056]    In accordance with a preferred embodiment of the present invention the at least one packaging layer contains silicon. Preferably, the compliant electrophoretic coating layer provides alpha-particle shielding between the first and second ball grid arrays and the device. Additionally or alternatively, the device is a DRAM device. 
         [0057]    There is additionally provided in accordance with yet another preferred embodiment of the present invention a method of manufacture of stacked chip-sized wafer level packaged devices including providing at least first and second chip-sized wafer level packaged devices including, for each of the first and second chip-sized wafer level packaged devices providing a semiconductor wafer including a multiplicity of devices, forming at least one packaging layer including a silicon packaging layer over the semiconductor wafer, forming a first ball grid array over a surface of the at least one packaging layer and being electrically connected to ones of the multiplicity of devices, forming a second ball grid array over a surface of the semiconductor wafer and being electrically connected to ones of the multiplicity of devices and dicing the semiconductor wafer and the at least one packaging layer and soldering the first ball grid array of the first device to the second ball grid array of the second device. 
         [0058]    In accordance with a preferred embodiment of the present invention the forming at least one packaging layer includes forming a plurality of packaging layers. Preferably, the forming a plurality of packaging layers includes disposing the plurality of packaging layers on the same side of the portion of the semiconductor wafer. Additionally or alternatively, the multiplicity of devices includes at least one DRAM device. 
         [0059]    There is also provided in accordance with still another preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing at least first and second chip-sized wafer level packaged devices including, for each of the first and second chip-sized wafer level packaged devices, providing a semiconductor wafer including an active surface defining a multiplicity of devices, forming at least one packaging layer over the semiconductor wafer, forming a first ball grid array over a surface of the at least one packaging layer and being electrically connected to ones of the multiplicity of devices, forming a second ball grid array over a surface of the semiconductor wafer and being electrically connected to ones of the multiplicity of devices, forming a compliant electrophoretic coating layer underlying at least one of the first and second ball grid arrays and dicing the semiconductor wafer and the at least one packaging layer and soldering the first ball grid array of the first device to the second ball grid array of the second device. 
         [0060]    In accordance with a preferred embodiment of the present invention the forming at least one packaging layer includes forming a plurality of packaging layers. Preferably, the forming a plurality of packaging layers includes disposing the plurality of packaging layers on the same side of the portion of the semiconductor wafer. Additionally or alternatively, the multiplicity of devices includes at least one DRAM device. 
         [0061]    There is further provided in accordance with a further preferred embodiment of the present invention a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a plurality of interconnects formed over a surface of the packaging layer and being electrically connected to the device. 
         [0062]    In accordance with a preferred embodiment of the present invention the plurality of interconnects includes Anisotropic Conductive Film (ACF) attachable interconnects. Preferably, the ACF attachable interconnects are formed of copper. Additionally or alternatively, the chip-sized wafer level packaged device also includes a printed circuit board including interconnects and a conductive film bonding the interconnects of the printed circuit board to the interconnects of the packaging layer. 
         [0063]    In accordance with another preferred embodiment of the present invention the conductive film includes an Anisotropic Conductive Film (ACF). Preferably, the semiconductor wafer contains at least one of silicon and Gallium Arsenide. Additionally or alternatively, the packaging layer is adhered to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. 
         [0064]    In accordance with yet another preferred embodiment of the present invention the packaging layer includes silicon. Preferably, the device includes a memory device. 
         [0065]    There is yet further provided in accordance with yet a further preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a semiconductor wafer including a multiplicity of devices, forming a packaging layer over the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer, forming a plurality of interconnects over a surface of the packaging layer which are electrically connected to ones of the multiplicity of devices and dicing the semiconductor wafer and the packaging layer. 
         [0066]    In accordance with a preferred embodiment of the present invention the forming a plurality of interconnects includes forming ACF attachable interconnects. Preferably, the forming ACF attachable interconnects of copper. Additionally or alternatively, the method also includes providing a printed circuit board including interconnects and bonding the interconnects of the printed circuit board to the attachable interconnects of the packaging layer by a conductive film. 
         [0067]    In accordance with another preferred embodiment of the present invention the bonding includes bonding by an anisotropic conductive film. Preferably, the providing a semiconductor wafer includes providing a semiconductor wafer containing at least one of silicon and Gallium Arsenide. Additionally or alternatively, the method also includes adhering the packaging layer to the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. 
         [0068]    There is still further provided in accordance with still a further preferred embodiment of the present invention a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over an active surface of the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer, metal connections formed onto the packaging layer, the metal connections being electrically connected to the device and including portions which are gold plated and a printed circuit board including metal pins, the metal pins being coated with an Indium layer, the pins being mounted onto the portions of the metal connections which are gold plated by eutectic Au/In intermetallic bonding. 
         [0069]    In accordance with a preferred embodiment of the present invention the semiconductor wafer contains at least one of silicon and Gallium Arsenide. Preferably, the packaging layer is adhered to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. Additionally or alternatively, the packaging layer includes silicon. 
         [0070]    In accordance with another preferred embodiment of the present invention the chip-sized wafer level packaged device also includes at least one compliant layer formed over the packaging layer and underlying the metal connections. Preferably, the device includes a memory device. 
         [0071]    There is also provided in accordance with another preferred embodiment of the present invention a chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over an active surface of the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer, metal connections formed onto the packaging layer, the metal connections being electrically connected to the device and including portions which are gold plated and a wafer level die including a portion of a semiconductor wafer including a device, a packaging layer formed over an active surface of the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and metal pins coated with an Indium layer, the pins being mounted onto the portions of the metal connections which are gold plated by eutectic Au/In intermetallic bonding. 
         [0072]    In accordance with a preferred embodiment of the present invention at least one of the semiconductor wafers contains at least one of silicon and Gallium Arsenide. Preferably, the packaging layer is adhered to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. Additionally or alternatively, the packaging layer includes silicon. 
         [0073]    In accordance with another preferred embodiment of the present invention the chip-sized wafer level packaged device also includes at least one compliant layer formed over the packaging layer and underlying the metal connections. Preferably, the device includes a memory device. 
         [0074]    There is additionally provided in accordance with an additional preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a portion of a semiconductor wafer including a multiplicity of devices, forming a packaging layer over an active surface of the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer, forming metal connections mounted onto the packaging layer, the metal connections being electrically connected to the device and including portions which are gold plated, providing a printed circuit board including metal pins which are coated with an Indium layer and employing eutectic Au/In intermetallic bonding to bond the metal pins to the portions of the metal connections which are gold plated, thereby mounting the printed circuit board to the packaging layer. 
         [0075]    In accordance with a preferred embodiment of the present invention the method also includes adhering the packaging layer to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. Preferably, the method also includes forming at least one compliant layer over the packaging layer and underlying the metal connections. 
         [0076]    There is further provided in accordance with a further preferred embodiment of the present invention a method of manufacture of chip-sized wafer level packaged devices including providing a portion of a semiconductor wafer including a multiplicity of devices, forming a packaging layer over an active surface of the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer, forming metal connections mounted onto the packaging layer, the metal connections being electrically connected to the device and including portions which are gold plated, providing a wafer level die including a portion of a semiconductor wafer including a device, a packaging layer formed over an active surface of the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and metal pins coated with an Indium layer and employing eutectic Au/In intermetallic bonding to bond the metal pins to the portions of the metal connections which are gold plated, thereby mounting the wafer level die onto the packaging layer. 
         [0077]    In accordance with a preferred embodiment of the present invention the method also includes adhering the packaging layer to the portion of the semiconductor wafer by an adhesive, the adhesive having thermal expansion characteristics similar to those of the packaging layer. Preferably the method also includes forming at least one compliant layer over the packaging layer and underlying the metal connections. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0078]    The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which: 
           [0079]      FIGS. 1A ,  1 B,  1 C,  1 D,  1 E,  1 F,  1 G,  1 H,  1 I,  1 J,  1 K and  1 L are simplified sectional illustrations of a method for manufacturing packaged semiconductor chips in accordance with a preferred embodiment of the present invention; 
           [0080]      FIG. 1M  is a simplified, partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 1A-1L ; 
           [0081]      FIGS. 2A ,  2 B,  2 C,  2 D,  2 E,  2 F,  2 G,  2 H, and  2 I are simplified illustrations of a method for manufacturing packaged semiconductor chips in accordance with another preferred embodiment of the present invention; 
           [0082]      FIG. 2J  is a simplified partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 1A-1G  and  2 A- 2 I; 
           [0083]      FIGS. 3A ,  3 B,  3 C,  3 D,  3 E,  3 F,  3 G,  3 H and  3 I are simplified sectional illustrations of a method for manufacturing packaged semiconductor chips in accordance with yet another preferred embodiment of the present invention; 
           [0084]      FIG. 3J  is a simplified partially pictorial, partially sectional illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 3A-3I ; 
           [0085]      FIGS. 4A ,  4 B,  4 C,  4 D,  4 E,  4 F,  4 G,  4 H,  4 I,  4 J,  4 K,  4 L,  4 M and  4 N are simplified sectional illustrations of a method for manufacturing packaged semiconductor chips in accordance with still another preferred embodiment of the present invention; 
           [0086]      FIG. 4O  is a simplified partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 4A-4N ; 
           [0087]      FIGS. 5A ,  5 B,  5 C,  5 D,  5 E,  5 F,  5 G,  5 H,  5 I,  5 J,  5 K,  5 L,  5 M and  5 N are simplified sectional illustrations of a further method for manufacturing packaged semiconductor chips in accordance with a further preferred embodiment of the present invention; 
           [0088]      FIG. 5O  is a simplified partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 5A-5N ; 
           [0089]      FIGS. 6A ,  6 B,  6 C,  6 D,  6 E,  6 F,  6 G,  6 H,  6 I,  6 J,  6 K,  6 L,  6 M,  6 N,  6 O, and  6 P are simplified sectional illustrations of yet a further method for manufacturing packaged semiconductor chips in accordance with yet a further preferred embodiment of the present invention; 
           [0090]      FIG. 6Q  is a simplified partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 6A-6P ; 
           [0091]      FIGS. 7A ,  7 B,  7 C,  7 D,  7 E,  7 F,  7 G,  7 H,  7 I,  7 J,  7 K and  7 L are simplified sectional illustrations of still a further method for manufacturing packaged semiconductor chips in accordance with still a further preferred embodiment of the present invention; 
           [0092]      FIG. 7M  is a simplified partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 7A-7L ; 
           [0093]      FIGS. 8A ,  8 B,  8 C,  8 D,  8 E,  8 F,  8 G,  8 H,  8 I,  8 J,  8 K,  8 L,  8 M,  8 N,  8 O and  8 P are simplified sectional illustrations of another method for manufacturing packaged semiconductor chips in accordance with another preferred embodiment of the present invention; 
           [0094]      FIG. 8Q  is a simplified, partially cut away part-pictorial and part-sectional illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 8A-8P ; 
           [0095]      FIGS. 9A ,  9 B,  9 C,  9 D,  9 E,  9 F,  9 G,  9 H,  9 I,  9 J,  9 K,  9 L,  9 M,  9 N,  9 O,  9 P and  9 Q are simplified sectional illustrations of yet another method for manufacturing packaged semiconductor chips in accordance with another preferred embodiment of the present invention; 
           [0096]      FIG. 9R  is a simplified partially cut away part-pictorial and part-sectional illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 9A-9Q ; 
           [0097]      FIGS. 10A ,  10 B,  10 C,  10 D,  10 E,  10 F,  10 G,  10 H,  10 I,  10 J,  10 K,  10 L,  10 M and  10 N are simplified sectional illustrations of still another method for manufacturing packaged semiconductor chips in accordance with another preferred embodiment of the present invention; 
           [0098]      FIG. 10O  is a simplified pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 10A-10N ; 
           [0099]      FIGS. 11A ,  11 B,  11 C,  11 D,  11 E,  11 F,  11 G,  11 H,  11 I and  11 J are simplified sectional illustrations of a method for manufacturing packaged stacked semiconductor chips in accordance with a further preferred embodiment of the present invention; 
           [0100]      FIG. 11K  is a simplified pictorial illustration of part of a packaged stacked semiconductor chip manufactured in accordance with the method of  FIGS. 11A-11J ; 
           [0101]      FIG. 12  is a simplified pictorial illustration of a packaged stacked semiconductor chip including semiconductor chips manufactured in accordance with the method of  FIGS. 8A-8P ; 
           [0102]      FIG. 13  is a simplified pictorial illustration of a packaged stacked semiconductor chip including semiconductor chips manufactured in accordance with the method of  FIGS. 9A-9Q ; 
           [0103]      FIG. 14  is a simplified partially sectional illustration of a packaged semiconductor chip constructed and operative in accordance with an additional preferred embodiment of the present invention; 
           [0104]      FIGS. 15A ,  15 B,  15 C and  15 D are simplified sectional illustrations of an additional method for manufacturing and mounting packaged semiconductor chips in accordance with a further preferred embodiment of the present invention; 
           [0105]      FIGS. 16A and 16B  are simplified sectional illustrations of a further method for manufacturing and mounting packaged semiconductor chips in accordance with yet a further preferred embodiment of the present invention; 
           [0106]      FIGS. 17A and 17B  are simplified illustrations of a method for manufacturing and mounting stacked packaged semiconductor chips in accordance with still another preferred embodiment of the present invention; 
           [0107]      FIGS. 18A ,  18 B,  18 C,  18 D,  18 E,  18 F,  18 G,  18 H,  18 I,  18 J,  18 K and  18 L are simplified sectional illustrations of yet a further method for manufacturing packaged semiconductor chips in accordance with yet a further preferred embodiment of the present invention; and 
           [0108]      FIG. 18M  is a simplified partially cut away pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 18A-18L . 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0109]    Reference is now made to  FIGS. 1A-1L , which are simplified sectional illustrations of a method for manufacturing packaged semiconductor chips in accordance with a preferred embodiment of the present invention. 
         [0110]    Turning to  FIG. 1A , there is seen part of a semiconductor wafer  100  including dies  102 , each typically having an active surface  104  including electrical circuitry  106  having bond pads  108 . The wafer  100  is typically silicon of thickness 730 microns. The electrical circuitry  106  may be provided by any suitable conventional technique. Alternatively, the wafer  100  may be any other suitable material, such as, for example, Gallium Arsenide and may be of any suitable thickness. 
         [0111]      FIG. 1B  shows a wafer-scale packaging layer  110  attached to wafer  100  by an adhesive  112 , such as epoxy. As seen in  FIG. 1B , the adhesive  112  covers the active surfaces  104  of dies  102 . Preferably, the adhesive is homogeneously applied to the packaging layer by spin bonding, as described in U.S. Pat. Nos. 5,980,663 and 6,646,289, the contents of which is hereby incorporated by reference. Alternatively, any other suitable technique may be employed. 
         [0112]    It is a particular feature of the present invention that the thermal expansion characteristics of the packaging layer  110  are closely matched to those of the semiconductor wafer  100 . For example, if the semiconductor wafer  100  is made of silicon, which has a coefficient of thermal expansion of 2.6 μm·m-1·K-1 at 25° C., the coefficient of thermal expansion of the packaging layer  110  should be similar. Furthermore, the adhesive  112  preferably has a coefficient of thermal expansion which is closely matched to the coefficients of thermal expansion of the semiconductor wafer  100  and of the packaging layer  110 . Preferably, when the semiconductor wafer  100  comprises silicon, the protective layer  110  also comprises silicon having sufficient conductivity to permit electrophoretic coating thereof. 
         [0113]    Turning to  FIG. 1C , it is seen that the semiconductor wafer  100  is thinned as by machining its non-active surface  114 . Preferably, the thickness of the semiconductor wafer  100  at this stage, following thinning thereof, is 300 microns. 
         [0114]      FIG. 1D  shows notches  120 , preferably formed by photolithography employing plasma etching or wet etching techniques, at locations which overlie bond pads  108 . The notches  120  preferably do not extend through adhesive  112 . 
         [0115]    Turning to  FIG. 1E , it is seen that the adhesive  112  overlying bond pads  108  and underlying notches  120  is removed, preferably by dry etching. 
         [0116]      FIG. 1F  shows the formation of an electrophoretic, electrically insulative compliant layer  122  over the packaging layer  110 . Examples of suitable compliant layers include Powercron 645 and Powercron 648, both commercially available from PPG of Pittsburgh, Pa., USA; Cathoguard 325, commercially available from BASF of Southfield, Mass., USA; Electrolac, commercially available from Macdermid of Waterbury, Conn., USA and Lectraseal DV494 and Lectrobase 101, both commercially available from LVH Coatings of Birmingham, UK. Once cured, compliant layer  122  encapsulates all exposed surfaces of the packaging layer  110 . Compliant layer  122  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0117]      FIG. 1G  illustrates the formation of a metal layer  130 , by sputtering chrome, aluminum or copper. Metal layer  130  extends from the bond pads  108 , over the compliant layer  122  and along the inclined surfaces of the packaging layer  110 , defined by notches  120 , onto outer, generally planar surfaces of the compliant layer  122  at dies  102 . 
         [0118]    As shown in  FIG. 1H , metal connections  132  are preferably formed by patterning the metal layer  130 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  132  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0119]      FIG. 1I  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  134  over the metal connections  132  and over the compliant layer  122 . Preferably, encapsulant passivation layer  134  comprises solder mask.  FIG. 1J  shows patterning of the encapsulant passivation layer  134 , preferably by photolithography, to define solder bump locations  135 . 
         [0120]      FIG. 1K  illustrates the formation of solder bumps  140  at locations  135  on the metal connections  132 , at which the encapsulant passivation layer  134  is not present. 
         [0121]      FIG. 1L  shows dicing of the wafer  100  and packaging layer  110  of  FIG. 1K  along scribe lines  142  to produce a multiplicity of individually packaged dies  144 . 
         [0122]    Reference is now made to  FIG. 1M , which is a simplified, partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 1A-1L . As seen in  FIG. 1M , a notch  150 , corresponding to notch  120  ( FIGS. 1D-1L ), is formed in a packaging layer  152 , corresponding to packaging layer  110  (FIGS.  1 B- 1 L), which forms part of a die  153 , corresponding to die  144  ( FIG. 1L ). 
         [0123]    The notch  150  exposes a row of bond pads  154 , corresponding to bond pads  108  ( FIGS. 1A-1L ). A layer  156  of adhesive, corresponding to layer  112  ( FIGS. 1B-1L ), covers a silicon layer  158 , corresponding to semiconductor wafer  100 , of the silicon wafer die  153  other than at notch  150 , and packaging layer  152  covers the adhesive  156 . An electrophoretic, electrically insulative compliant layer  160 , corresponding to electrophoretic, electrically insulative compliant layer  122  ( FIGS. 1E-1L ), covers the packaging layer  152  and extends along inclined surfaces of notch  150 , but does not cover the bond pads  154 . 
         [0124]    Patterned metal connections  162 , corresponding to metal connections  132  ( FIGS. 1H-1L ), extend from bond pads  154  along the inclined surfaces of notch  150  and over generally planar surfaces of compliant layer  160  to solder bump locations  164 , corresponding to solder bump locations  135  ( FIGS. 1J-1L ). An encapsulant passivation layer  166 , corresponding to encapsulant passivation layer  134  ( FIGS. 1I-1L ), is formed over compliant layer  160  and metal connections  162  other than at locations  164 . Solder bumps  168 , corresponding to solder bumps  140  ( FIGS. 1K and 1L ), are formed onto metal connections  162  at locations  164 . 
         [0125]    Reference is now made to  FIGS. 2A-2I , which illustrate an alternative methodology, useful for some of the bond pads  108 . For such bond pads, the methodology of  FIGS. 2A-2I  takes place following the steps of  FIGS. 1A-1G , and replaces steps  1 H,  1 I,  1 J,  1 K and  1 L. The methodology of FIGS.  1 A- 1 G and  2 A- 2 I is particularly useful for devices having a high density of bond pads  108 , such as DRAMs. 
         [0126]      FIG. 2A  illustrates patterning of metal layer  130  ( FIG. 1G ) to define metal connections  252 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  252  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0127]      FIG. 2B  shows the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  254  over the metal connections  252  and over the compliant layer  122 . Preferably, the encapsulant passivation layer  254  comprises solder mask.  FIG. 2C  shows patterning of the encapsulant passivation layer  254 , preferably by photolithography. 
         [0128]      FIG. 2D  illustrates the formation of a second metal layer  260  by sputtering chrome, aluminum or copper. Metal layer  260  extends from the metal connections  252  over the encapsulant passivation layer  254 . 
         [0129]    As shown in  FIG. 2E , metal connections  262  are preferably formed by patterning metal layer  260 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  262  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0130]      FIG. 2F  shows the application, preferably by spray coating, of a third, electrically insulative, encapsulant passivation layer  264  over the metal connections  262  and over the encapsulant passivation layer  254  and the compliant layer  122 . Preferably, the encapsulant passivation layer  264  comprises solder mask.  FIG. 2G  shows patterning of the encapsulant passivation layer  264 , preferably by photolithography, to define solder bump locations  266 . 
         [0131]      FIG. 2H  illustrates the formation of solder bumps  270  at solder bump locations  266 , at which the encapsulant passivation layer  264  is not present. 
         [0132]      FIG. 2I  shows dicing of the wafer  100  and packaging layer  110  of  FIG. 2H  along scribe lines  272  to produce a multiplicity of individually packaged dies  274 . 
         [0133]    Reference is now made to  FIG. 2J , which is a simplified partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 1A-1G  and  2 A- 2 I. As seen in  FIG. 2J , a notch  276 , corresponding to notch  120  ( FIGS. 2A-2I ), is formed in packaging layer  277 , corresponding to packaging layer  110  ( FIGS. 2A-2H ), which forms part of a silicon wafer die  278 , corresponding to die  274  ( FIG. 2I ). 
         [0134]    The notch  276  exposes a row of bond pads  279 , corresponding to bond pads  108  ( FIGS. 2A-2I ). A layer  280  of adhesive, corresponding to layer  112  ( FIGS. 2A-2I ), covers a silicon layer  282 , corresponding to semiconductor wafer  100 , of silicon wafer die  278  other than at notch  276  and packaging layer  277  covers the adhesive  280 . An electrophoretic, electrically insulative compliant layer  284 , corresponding to electrophoretic, electrically insulative compliant layer  122  ( FIGS. 2A-2I ), covers the packaging layer  277  and extends along inclined surfaces of notch  276 , but does not cover the bond pads  279 . 
         [0135]    Patterned metal connections  286 , corresponding to metal connections  132  ( FIGS. 1H-1L ), extend from some of bond pads  279  along the inclined surfaces of notch  276  and over generally planar surfaces of compliant layer  284  to solder bump locations  288 , corresponding to some of solder bump locations  135  ( FIGS. 1J-1L ). Other patterned metal connections  286 , corresponding to metal connections  252  ( FIGS. 2A-2I ), extend from other bond pads  279  along the inclined surfaces of notch  276  to additional locations  290 . 
         [0136]    An encapsulant passivation layer  292 , corresponding to encapsulant passivation layer  254  ( FIGS. 2B-2I ), is formed over compliant layer  284  and metal connections  286  other than at solder bump locations  288  and additional locations  290 . 
         [0137]    Additional metal connections  294 , corresponding to metal connections  262  ( FIGS. 2E-2I ), extend from additional locations  290  over generally planar surfaces of compliant layer  284  to solder bump locations  296 , corresponding to solder bump locations  266  ( FIGS. 2G-2I ). Solder bumps  298 , corresponding to solder bumps  270  ( FIGS. 2H and 2I ) are formed onto metal connections  294  at locations  296 . 
         [0138]    An encapsulant passivation layer  299 , corresponding to encapsulant passivation layer  264  ( FIGS. 2G-2I ), is formed over encapsulant passivation layer  292  and metal connections  294  other than at solder bump locations  296 . 
         [0139]    Reference is now made to  FIGS. 3A-3I , which are simplified sectional illustrations of a method for manufacturing packaged semiconductor chips in accordance with yet another preferred embodiment of the present invention wherein the packaging layer  110  is electrically conductive. The method of  FIGS. 3A-3I  employs the steps described hereinabove with reference to  FIGS. 1A-1C , which are followed by the steps shown in  FIGS. 3A-3I . 
         [0140]      FIG. 3A  shows notches  300  and  302  formed in the structure of  FIG. 1C , described hereinabove. Notches  300  and  302  are preferably formed by photolithography, employing plasma etching or wet etching techniques, and preferably do not extend through adhesive  112 . Notches  300  are formed at locations which overlie bond pads  108  and are similar to notches  120  of  FIGS. 1D-1L  and  2 A- 2 I. 
         [0141]    Preferably, notches  302  are wider than notches  300  and are symmetrically formed on both sides of scribe lines  304 . Notches  302  are of varying width and depth, such that at corners of dies at which adjacent dies meet, there is provided electrically conductive continuity of the packaging layer  110  across adjacent dies  102  prior to dicing. This is achieved by decreasing the depth and corresponding width of the notches  302  at junctions of adjacent dies  102 . 
         [0142]    Turning to  FIG. 3B , it is seen that the adhesive  112  overlying bond pads  108  and underlying notches  300  is removed, preferably by dry etching. 
         [0143]      FIG. 3C  shows the formation of an electrophoretic, electrically insulative compliant layer  322  over the packaging layer  110 . Examples of suitable materials for compliant layer  322  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  322  encapsulates all exposed surfaces of the packaging layer  110 . Compliant layer  322  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0144]      FIG. 3D  illustrates the formation of a metal layer  330 , by sputtering chrome, aluminum or copper. Metal layer  330  extends from the bond pads  108 , over the compliant layer  322  and along the inclined surfaces of the packaging layer  110 , defined by notches  300  and  302 , onto outer, generally planar surfaces of the compliant layer  322  at dies  102 . 
         [0145]    As shown in  FIG. 3E , metal connections  332  are preferably formed by patterning the metal layer  330 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  332  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0146]      FIG. 3F  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  334  over the metal connections  332  and over the compliant layer  322 . Preferably, the encapsulant passivation layer  334  comprises solder mask.  FIG. 3G  shows patterning of the encapsulant passivation layer  334 , preferably by photolithography, to define solder bump locations  336 . 
         [0147]      FIG. 3H  illustrates the formation of solder bumps  340  at locations  336  on the metal connections  332 , at which the encapsulant passivation layer  334  is not present. 
         [0148]      FIG. 3I  shows dicing of the wafer  100  and packaging layer  110  of  FIG. 3H  along scribe lines  304  to produce a multiplicity of individually packaged dies  344  having inclined surfaces  346  adjacent the scribe lines  304 . 
         [0149]    Reference is now made to  FIG. 3J , which is a simplified partially pictorial, partially sectional illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 3A-3I . As seen in  FIG. 3J , the edge structure of each individually package die  344  includes a straight-edged base portion  350  including an edge defined by a silicon layer  352 , corresponding to a portion of semiconductor wafer  100  ( FIGS. 3A-3I ) overlaid with a layer  354  of adhesive, corresponding to adhesive layer  112  ( FIGS. 3A-3I ). 
         [0150]    Disposed over straight-edged base portion  350  and set back slightly therefrom, other than at the corners of the packaged semiconductor DRAM chip, thereby defining a shoulder  356 , is an inclined edge portion  358  corresponding to inclined surface  346  ( FIG. 3I ). Since the depth and corresponding width of the notches  302  are decreased at junctions of adjacent dies  102 , shoulders  356  do not extend to the corners. 
         [0151]    The inclined edge portion  358  is defined by an encapsulant passivation layer  360 , corresponding to encapsulant passivation layer  334  ( FIGS. 3F-3I ) which overlies an electrophoretic, electrically insulative compliant layer  362 , corresponding to electrophoretic, electrically insulative compliant layer  322  ( FIG. 3B-3I ), which in turn overlies a packaging layer  364 , corresponding to packaging layer  110  ( FIGS. 3A-3I ). 
         [0152]    As also seen in  FIG. 3J , the corner structure of each individually package die  344  includes a straight-edged corner portion  370  including a corner defined by silicon layer  352 , overlaid with layer  354  of adhesive, above which is a portion of packaging layer  364 , electrophoretic, electrically insulative compliant layer  362  and encapsulant passivation layer  360 . 
         [0153]    Reference is now made to  FIGS. 4A-4N , which are simplified sectional illustrations of a method for manufacturing packaged semiconductor chips in accordance with still another preferred embodiment of the present invention. Turning to FIG.  4 A, there is seen part of a semiconductor wafer  500 . The wafer  500  is typically formed of silicon and has a thickness of 730 microns. Alternatively, the wafer  500  may be formed of any other suitable material and may be of any suitable thickness. 
         [0154]      FIG. 4B  shows the formation of a plurality of recesses  502  in a surface  504  of wafer  500  as by a conventional etching technique.  FIG. 4C  shows filling of the recesses  502  with a compliant material  506 , preferably a silicone-based material such as Dow WL-5150, commercially available from Dow Corning, Inc., typically by use of a squeegee. The compliant material  506  is then cured in a conventional manner. 
         [0155]      FIG. 4D  shows removal of excess compliant material  506  and planarization of surface  504 , as by grinding, thereby leaving platforms  507  of compliant material  506  in recesses  502 .  FIG. 4E  shows the application of an adhesive  508  onto surface  504 , overlying recesses  502  filled with compliant material  506  defining platforms  507 , as by spin coating. Adhesive  508  is preferably a suitable epoxy. 
         [0156]    Reference is now made to  FIG. 4F , which shows the wafer  500  of  FIG. 4E , turned upside down and bonded onto the structure of  FIG. 1F , described hereinabove, and here designated by reference numeral  510 , with a surface  512 , opposite surface  504  being exposed. 
         [0157]      FIG. 4G  shows thinning of wafer  500 , preferably by grinding surface  512 , down to a thickness equal to the depth of recesses  502 , typically 100 microns. 
         [0158]      FIG. 4H  shows removal of the remainder of wafer  500 , and those portions of adhesive  508  not underlying platforms  507  of compliant material  506 , as by silicon etching and ultrasonic cleaning. 
         [0159]      FIG. 4I  illustrates the formation of a metal layer  514 , by sputtering chrome, aluminum or copper. Metal layer  514  extends from the bond pads  108 , over the compliant layer  122  and along the inclined surfaces of the packaging layer  110 , defined by notches  120 , onto outer, generally planar surfaces of the compliant layer  122  and over platforms  507  at dies  102 . 
         [0160]    As shown in  FIG. 4J , metal connections  516  are preferably formed by patterning the metal layer  514 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  516  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0161]      FIG. 4K  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  518  over the metal connections  516 , over the compliant layer  122  and over platforms  507 . Preferably, the encapsulant passivation layer  518  comprises solder mask.  FIG. 4L  shows patterning of the encapsulant passivation layer  518 , preferably by photolithography, to define solder bump locations  519 . 
         [0162]      FIG. 4M  illustrates the formation of solder bumps  520  onto platforms  507  at locations on the metal connections  516  at which the encapsulant passivation layer  518  is not present. 
         [0163]      FIG. 4N  shows dicing of the wafer  100  and packaging layer  110  of  FIG. 4M  along scribe lines  522  to produce a multiplicity of individually packaged dies  524 . 
         [0164]    Reference is now made to  FIG. 4O , which is a simplified partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 4A-4N . As seen in  FIG. 4O , a notch  550 , corresponding to notch  120  ( FIGS. 4F-4N ), is formed in a packaging layer  551  of a silicon wafer die  552 , corresponding to die  524  ( FIG. 4N ). 
         [0165]    The notch  550  exposes a row of bond pads  554 , corresponding to bond pads  108  ( FIGS. 4F-4N ). A layer  556  of adhesive, corresponding to layer  112  ( FIGS. 4F-4N ), covers a silicon layer  558 , corresponding to semiconductor wafer  100 , the silicon wafer die  552  other than at notch  550  and packaging layer  551  covers the adhesive  556 . An electrophoretic, electrically insulative compliant layer  560 , corresponding to electrophoretic, electrically insulative compliant layer  122  ( FIGS. 4F-4N ), covers the packaging layer  551  and extends along inclined surfaces of notch  550 , but does not cover the bond pads  554 . Platforms  562 , corresponding to platforms  507  ( FIGS. 4D-4N ) are formed over compliant layer  560  at solder bump locations  564 , corresponding to solder bump locations  519  ( FIGS. 4L-4N ). 
         [0166]    Patterned metal connections  566 , corresponding to metal connections  516  ( FIGS. 4J-4N ), extend from bond pads  554  along the inclined surfaces of notch  550  and over generally planar surfaces of compliant layer  560  and terminate over platforms  562 . An encapsulant passivation layer  568 , corresponding to encapsulant passivation layer  518  ( FIGS. 4K-4N ), is formed over compliant layer  560  and metal connections  562  other than at locations  564 . Solder bumps  570 , corresponding to solder bumps  520  ( FIGS. 4M and 4N ), are formed onto metal connections  566  at locations  564 . 
         [0167]    Reference is now made to  FIGS. 5A-5N , which are simplified sectional illustrations of a further method for manufacturing packaged semiconductor chips in accordance with a further preferred embodiment of the present invention. 
         [0168]    The method of  FIGS. 5A-5N  employs the steps described hereinabove with reference to  FIGS. 4A-4E , which are followed by the steps shown in  FIGS. 5A-5N . 
         [0169]    Reference is now made to  FIG. 5A , which shows the wafer  500  of  FIG. 4E , turned upside down and bonded onto a wafer scale packaging layer  900 , preferably a silicon wafer, with a surface  902  of packaging layer  900  being exposed. 
         [0170]      FIG. 5B  shows the structure of  FIG. 5A  bonded at surface  902  to the structure of  FIG. 1A  at surface  104  thereof, preferably by means of an adhesive  904 , such as epoxy. 
         [0171]      FIG. 5C  shows thinning of wafer  100 , preferably by machining its non-active surface  114 . Preferably the thickness of the semiconductor wafer  100  at this stage, following thinning thereof, is 300 microns. 
         [0172]      FIG. 5D  shows thinning of wafer  500 , preferably by grinding surface  512 , down to a thickness equal to the depth of recesses  502 , typically 100 microns. 
         [0173]      FIG. 5E  shows removal of the remainder of wafer  500 , and those portions of adhesive  508  not underlying platforms  507  of compliant material  506 , as by silicon etching and ultrasonic cleaning. 
         [0174]      FIG. 5F  shows notches  920 , preferably formed by photolithography employing plasma etching or wet etching techniques, at locations which overlie bond pads  108 . The notches preferably do not extend through adhesive  904 . 
         [0175]    Turning to  FIG. 5G , it is seen that the adhesive  904  overlying bond pads  108  and underlying notches  920  is removed, preferably by dry etching. 
         [0176]      FIG. 5H  shows the formation of an electrophoretic, electrically insulative compliant layer  922  over those portions of packaging layer  900  not underlying platforms  507 . Examples of suitable materials for compliant layer  922  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  922  encapsulates all exposed surfaces of the packaging layer  900 . Compliant layer  922  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0177]      FIG. 5I  illustrates the formation of a metal layer  924 , by sputtering chrome, aluminum or copper. Metal layer  924  extends from the bond pads  108 , over the compliant layer  922  and along the inclined surfaces of the packaging layer  900 , defined by notches  920 , onto outer, generally planar surfaces of the compliant layer  922  and over platforms  507  at dies  102 . 
         [0178]    As shown in  FIG. 5J , metal connections  926  are preferably formed by patterning the metal layer  924 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  926  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0179]      FIG. 5K  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  930  over the metal connections  926 , over the compliant layer  922  and over platforms  507 . Preferably, the encapsulant passivation layer  930  comprises solder mask.  FIG. 5L  shows patterning of the encapsulant passivation layer  930 , preferably by photolithography, to define solder bump locations  931 . 
         [0180]      FIG. 5M  illustrates the formation of solder bumps  932  onto platforms  507  at locations  931  on the metal connections  926 , at which the encapsulant passivation layer  930  is not present. 
         [0181]      FIG. 5N  shows dicing of the wafer  100  and packaging layer  110  of  FIG. 5M  along scribe lines  942  to produce a multiplicity of individually packaged dies  944 . 
         [0182]    Reference is now made to  FIG. 5O , which is a simplified partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 5A-5N . As seen in  FIG. 5O , a notch  950 , corresponding to notch  920  ( FIGS. 5F-5N ), is formed in a packaging layer  951 , corresponding to packaging layer  900  ( FIGS. 5A-5N ), of silicon wafer die  952 , corresponding to die  944  ( FIG. 5N ). 
         [0183]    The notch  950  exposes a row of bond pads  954 , corresponding to bond pads  108  ( FIGS. 5B-5N ). A layer  956  of adhesive, corresponding to layer  904  ( FIGS. 5B-5N ), covers a silicon layer  958 , corresponding to semiconductor wafer  100 , of the silicon wafer die  952  other than at notch  950  and packaging layer  951  covers the adhesive  956 . Platforms  960 , corresponding to platforms  507  ( FIGS. 5A-5N ) are formed over packaging layer  951  at solder bump locations  961 , corresponding to solder bump locations  931  ( FIGS. 5L-5N ). An electrophoretic, electrically insulative compliant layer  962 , corresponding to electrophoretic, electrically insulative compliant layer  922  ( FIGS. 5G-5N ), covers the packaging layer  951 , surrounds platforms  960  and extends along inclined surfaces of notch  950 , but does not cover the bond pads  954 . 
         [0184]    Patterned metal connections  966 , corresponding to metal connections  926  ( FIGS. 5J-5N ), extend from bond pads  954  along the inclined surfaces of notch  950  and over generally planar surfaces of compliant layer  962  and terminate over platforms  960 . An encapsulant passivation layer  968 , corresponding to encapsulant passivation layer  930  ( FIGS. 5K-5N ), is formed over compliant layer  962  and metal connections  966  other than at locations  961 . Solder bumps  970 , corresponding to solder bumps  932  ( FIGS. 5M and 5N ), are formed onto metal connections  966  at locations  961 . 
         [0185]    Reference is now made to  FIGS. 6A-6P , which are simplified sectional illustrations of yet a further method for manufacturing packaged semiconductor chips in accordance with yet a further preferred embodiment of the present invention. 
         [0186]    The method of  FIGS. 6A-6P  employs the steps described hereinabove with reference to  FIGS. 1A-1C , which are followed by the steps shown in  FIGS. 6A-6P . 
         [0187]    Reference is now made to  FIG. 6A , which shows a structure similar to the structure of  FIG. 1C , but having a packaging layer  1300  which is thicker than packaging layer  110  ( FIG. 1C ). On a top surface  1302  of packaging layer  1300  there are formed a plurality of recesses  1304 , preferably by a conventional etching technique employing spin-coated photoresist. 
         [0188]    As seen in  FIG. 6B , surface  1302  undergoes electrophoretic deposition of a layer of photoresist  1306 , followed by lithography, which leaves portions  1308  of the bottom surfaces  1310  of recesses  1304  exposed to etching, as seen in  FIG. 6C . Subsequent silicon etching produces an undercut recess  1312  at each recess  1304 , as seen in  FIG. 6D . 
         [0189]      FIG. 6E  shows filling of the recesses  1312  and  1304  with a compliant material  1314 , preferably a silicone-based material such as Dow WL-5150, commercially available from Dow Corning, Inc., typically by use of a squeegee. The compliant material  1314  is then cured in a conventional manner. 
         [0190]      FIG. 6F  shows removal of excess compliant material  1314  and planarization of surface  1302 , as by grinding, thereby leaving platforms  1316  of compliant material  1314  in recesses  1312  and  1304 . 
         [0191]      FIG. 6G  shows removal of the portions of packaging layer  1300  surrounding but not underlying platforms  1316  of compliant material  1314 , as by silicon etching and ultrasonic cleaning. 
         [0192]      FIG. 6H  shows notches  1320 , preferably formed by photolithography employing plasma etching or wet etching techniques, at locations which overlie bond pads  108 . The notches preferably do not extend through adhesive  112 . 
         [0193]    Turning to  FIG. 6I , it is seen that the adhesive  112  overlying bond pads  108  and underlying notches  1320  is removed, preferably by dry etching. 
         [0194]      FIG. 6J  shows the formation of an electrophoretic, electrically insulative compliant layer  1322  over those portions of packaging layer  1300  not underlying platforms  1316 . Examples of suitable materials for compliant layer  1322  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  1322  encapsulates all exposed surfaces of the packaging layer  1300 . Compliant layer  1322  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0195]      FIG. 6K  illustrates the formation of a metal layer  1324 , by sputtering chrome, aluminum or copper. Metal layer  1324  extends from the bond pads  108 , over the compliant layer  1322  and along the inclined surfaces of the packaging layer  1300 , defined by notches  1320 , onto outer, generally planar surfaces of the compliant layer  1322  and over platforms  1316  at dies  102 . 
         [0196]    As shown in  FIG. 6L , metal connections  1326  are preferably formed by patterning the metal layer  1324 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  1326  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0197]      FIG. 6M  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  1330  over the metal connections  1326 , over the compliant layer  1322  and over platforms  1316 . Preferably, the encapsulant passivation layer  1330  comprises solder mask.  FIG. 6N  shows patterning of the encapsulant passivation layer  1330 , preferably by photolithography, to define solder bump locations  1331 . 
         [0198]      FIG. 6O  illustrates the formation of solder bumps  1332  onto platforms  1316  at locations  1331  on the metal connections  1326  at which the encapsulant passivation layer  1330  is not present. 
         [0199]      FIG. 6P  shows dicing of the wafer  100  and packaging layer  1300  of  FIG. 6O  along scribe lines  1342  to produce a multiplicity of individually packaged dies  1344 . 
         [0200]    Reference is now made to  FIG. 6Q , which is a simplified partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 6A-6P . As seen in  FIG. 6Q , a notch  1350 , corresponding to notch  1320  ( FIGS. 6H-6P ), is formed in a packaging layer  1351 , corresponding to packaging layer  1300  ( FIGS. 6A-6P ), of a silicon wafer die  1352 , corresponding to die  1344  ( FIG. 6P ). 
         [0201]    The notch  1350  exposes a row of bond pads  1354 , corresponding to bond pads  108  ( FIGS. 6A-6P ). A layer  1356  of adhesive, corresponding to layer  112  ( FIGS. 6A-6P ), covers a silicon layer  1358 , corresponding to semiconductor wafer  100  ( FIGS. 6A-6P ), of the silicon wafer die  1352  other than at notch  1350  and packaging layer  1351  covers the adhesive  1356 . Platforms  1360 , corresponding to platforms  1316  ( FIGS. 6F-6P ) are formed over packaging layer  1351  at solder bump locations  1361 , corresponding to solder bump locations  1331  ( FIGS. 6N-6P ). It is a particular feature of the embodiment of  FIGS. 6A-6Q  that platforms  1360  are formed directly onto the packaging layer  1351  and not, as in the embodiment of  FIGS. 5A-5O , formed over a layer of adhesive. 
         [0202]    An electrophoretic, electrically insulative compliant layer  1362 , corresponding to electrophoretic, electrically insulative compliant layer  1322  ( FIGS. 6I-6P ), covers the packaging layer  1351 , surrounds platforms  1360  and extends along inclined surfaces of notch  1350 , but does not cover the bond pads  1354 . 
         [0203]    Patterned metal connections  1366 , corresponding to metal connections  1326  ( FIGS. 6L-6P ), extend from bond pads  1354  along the inclined surfaces of notch  1350  and over generally planar surfaces of compliant layer  1362  and terminate over platforms  1360 . An encapsulant passivation layer  1368 , corresponding to encapsulant passivation layer  1330  ( FIGS. 6M-6P ), is formed over compliant layer  1362  and metal connections  1366  other than at locations  1361 . Solder bumps  1370 , corresponding to solder bumps  1332  ( FIGS. 6O and 6P ), are formed onto metal connections  1366  at locations  1361 . 
         [0204]    Reference is now made to  FIGS. 7A-7L , which are simplified sectional illustrations of still a further method for manufacturing packaged semiconductor chips in accordance with still a further preferred embodiment of the present invention. 
         [0205]    The method of  FIGS. 7A-7L  employs the steps described hereinabove with reference to  FIGS. 4A-4E , which are preceded by the steps shown in  FIGS. 7A-7C  and followed by the steps shown in  FIGS. 7D-7L . 
         [0206]    Reference is now made to  FIG. 7A , which shows the structure of  FIG. 1A  having formed thereover an encapsulant passivation layer  1700 , typically comprising a suitable polymer, such as, for example a polyimide, which provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0207]      FIG. 7B  shows thinning of wafer  100 , preferably by machining its non-active surface  114 . Preferably the thickness of the semiconductor wafer  100  at this stage, following thinning thereof, is 300 microns.  FIG. 7C  shows the structure of  FIG. 7B  following patterning of the encapsulant passivation layer  1700 , by conventional etching methodology, to expose bond pads  108  on the active surface  104  of semiconductor wafer  100 . 
         [0208]      FIG. 7D  shows the wafer  500  of  FIG. 4E , turned upside down and bonded onto the structure of  FIG. 7C , with a surface  512 , opposite surface  504  being exposed. 
         [0209]      FIG. 7E  shows thinning of wafer  500 , preferably by grinding surface  512 , down to a thickness equal to the depth of recesses  502 , typically 100 microns. 
         [0210]      FIG. 7F  shows removal of the remainder of wafer  500  and those portions of adhesive  508  not underlying platforms  507  of compliant material  506 , as by silicon etching and ultrasonic cleaning. 
         [0211]      FIG. 7G  illustrates the formation of a metal layer  1714 , by sputtering chrome, aluminum or copper. Metal layer  1714  extends from the bond pads  108 , along the inclined surfaces of encapsulant passivation layer  1700 , onto outer, generally planar surfaces of the encapsulant passivation layer  1700  and over platforms  507  at dies  102 . 
         [0212]    As shown in  FIG. 7H , metal connections  1716  are preferably formed by patterning the metal layer  1714 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  1716  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0213]      FIG. 7I  illustrates the application, preferably by spray coating, of an electrically insulative, encapsulant passivation layer  1718  over the metal connections  1716 , over the encapsulant passivation layer  1700  and over platforms  507 . Preferably, the encapsulant passivation layer  1718  comprises solder mask.  FIG. 7J  shows patterning of the encapsulant passivation layer  1718 , preferably by photolithography, to define solder bump locations  1719 . 
         [0214]      FIG. 7K  illustrates the formation of solder bumps  1720  onto platforms  507  at locations  1719  on the metal connections  1716  at which the encapsulant passivation layer  1718  is not present. 
         [0215]      FIG. 7L  shows dicing of the wafer  100  and packaging layer of  FIG. 7K  along scribe lines  1722  to produce a multiplicity of individually packaged dies  1724 . 
         [0216]    Reference is now made to  FIG. 7M , which is a simplified partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 7A-7L . As seen in  FIG. 7M , a notch  1740 , produced by patterning of an encapsulant passivation layer  1742 , corresponding to encapsulant passivation layer  1700  ( FIG. 7C ), of a silicon wafer die  1743 , corresponding to silicon wafer die  1724  ( FIG. 7L ), exposes a row of bond pads  1754 , corresponding to bond pads  108  ( FIGS. 7A-7L ). Platforms  1762 , corresponding to platforms  507  ( FIGS. 7F-7L ) are formed over encapsulant passivation layer  1742  at solder bump locations  1764 , corresponding to solder bump locations  1719  ( FIGS. 7J-7L ). 
         [0217]    Patterned metal connections  1766 , corresponding to metal connections  1716  ( FIGS. 7H-7L ), extend from bond pads  1754  along the inclined surfaces of notch  1740  and over generally planar surfaces of encapsulant passivation layer  1742  and terminate over platforms  1762 . An encapsulant passivation layer  1768 , corresponding to encapsulant passivation layer  1718  ( FIGS. 7I-7L ), is formed over encapsulant passivation layer  1742  and metal connections  1766  other than at locations  1764 . 
         [0218]    Solder bumps  1770 , corresponding to solder bumps  1720  ( FIGS. 7K and 7L ), are formed onto metal connections  1766  at locations  1764 . 
         [0219]    Reference is now made to  FIGS. 8A-8P , which are simplified sectional illustrations of another method for manufacturing packaged semiconductor chips in accordance with another preferred embodiment of the present invention. The method of  FIGS. 8A-8P  employs the steps described hereinabove with reference to  FIGS. 1A-1C , which are followed by the steps shown in  FIGS. 8A-8P . 
         [0220]    Reference is now made to  FIG. 8A , which shows the structure of  FIG. 1C  turned upside-down. Notches  2120 , preferably formed by photolithography employing plasma etching or wet etching techniques, are formed in semiconductor wafer  100  at locations which overlie, in the sense of  FIG. 8A , some of bond pads  108 , here designated by reference numeral  2121 . 
         [0221]      FIG. 8B  shows the formation of an electrophoretic, electrically insulative compliant layer  2122  over the semiconductor wafer  100 . Examples of suitable materials for compliant layer  2122  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  2122  encapsulates all exposed surfaces of the semiconductor wafer  100 . Compliant layer  2122  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0222]      FIG. 8C  illustrates the formation of a metal layer  2130 , by sputtering chrome, aluminum or copper. Metal layer  2130  extends from the bond pads  2121 , over the compliant layer  2122  and along the inclined surfaces of the semiconductor wafer  100 , defined by notches  2120  onto outer, generally planar surfaces of the compliant layer  2122 . 
         [0223]    As shown in  FIG. 8D , metal connections  2132  are preferably formed by patterning the metal layer  2130 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  2132  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0224]      FIG. 8E  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  2134  over the metal connections  2132  and over the compliant layer  2122 . Preferably, the encapsulant passivation layer  2134  comprises solder mask.  FIG. 8F  shows patterning of the encapsulant passivation layer  2134 , preferably by photolithography, to define solder bump locations  2136 . 
         [0225]      FIG. 8G  illustrates the formation of solder bumps  2140  at locations  2136  on the metal connections  2132 , at which the encapsulant passivation layer  2134  is not present. 
         [0226]    Reference is now made to  FIG. 8H , which shows the structure of  FIG. 8G  turned upside-down. Notches  2150 , preferably formed by photolithography employing plasma etching or wet etching techniques, are formed at locations which overlie bond pads  2151 , which are some of bond pads  108 . The notches preferably do not extend through adhesive  112 . 
         [0227]    Turning to  FIG. 8I , it is seen that the adhesive  112  overlying bond pads  2151  and underlying notches  2150  is removed, preferably by dry etching. 
         [0228]      FIG. 8J  shows the formation of an electrophoretic, electrically insulative compliant layer  2152  over the packaging layer  110 , which is typically formed of a sufficiently conductive inorganic substrate. Compliant layer  2152  preferably provides protection to the device from alpha particles emitted by BGA solder balls. Examples of suitable materials for compliant layer  2152  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  2152  encapsulates all exposed surfaces of the packaging layer  110 . 
         [0229]      FIG. 8K  illustrates the formation of a metal layer  2160 , by sputtering chrome, aluminum or copper. Metal layer  2160  extends from the bond pads  2151 , over the compliant layer  2152  and along the inclined surfaces of the packaging layer  110 , defined by notches  2150  onto outer, generally planar surfaces of the compliant layer  2152 . 
         [0230]    As shown in  FIG. 8L , metal connections  2162  are preferably formed by patterning the metal layer  2160 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  2162  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0231]      FIG. 8M  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  2164  over the metal connections  2162  and over the compliant layer  2152 . Preferably, the encapsulant passivation layer  2164  comprises solder mask.  FIG. 8N  shows patterning of the encapsulant passivation layer  2164 , preferably by photolithography, to define solder bump locations  2166 . 
         [0232]      FIG. 8O  illustrates the formation of solder bumps  2170  at locations  2166  on the metal connections  2162  at which the encapsulant passivation layer  2164  is not present. 
         [0233]      FIG. 8P  shows dicing of the wafer  100  and packaging layer  110  of  FIG. 8O  along scribe lines  2172  to produce a multiplicity of individually packaged stackable dies  2174 . 
         [0234]    Reference is now made to  FIG. 8Q , which is a simplified, partially cut away part-pictorial and part-sectional illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 8A-8P . As seen in  FIG. 8Q , a notch  2175 , corresponding to notch  2150  ( FIGS. 8H-8P ), is formed in a packaging layer  2176 , corresponding to packaging layer  110  ( FIG. 8A-8P ) over a first surface of a silicon wafer die  2177 , corresponding to die  2174  ( FIG. 8P ). 
         [0235]    The notch  2175  exposes a row of bond pads  2178 , corresponding to bond pads  108  ( FIGS. 8A-8P ). A layer  2179  of adhesive, corresponding to layer  112  ( FIGS. 8A-8P ), covers a silicon layer  2180 , corresponding to semiconductor wafer  100  of the silicon wafer die  2177 , other than at notch  2175  and packaging layer  2176  covers the adhesive  2179 . An electrophoretic, electrically insulative compliant layer  2181 , corresponding to electrophoretic, electrically insulative compliant layer  2152  ( FIGS. 8I-8P ), covers the packaging layer  2176  and extends along inclined surfaces of notch  2175 , but does not cover the bond pads  2178 . 
         [0236]    Patterned metal connections  2182 , corresponding to metal connections  2162  ( FIGS. 8L-8P ) extend from bond pads  2178  along the inclined surfaces of notch  2175  and over generally planar surfaces of compliant layer  2181  to solder bump locations  2183 , corresponding to solder bump locations  2166  ( FIGS. 8N-8P ). An encapsulant passivation layer  2184 , corresponding to encapsulant passivation layer  2164  ( FIGS. 8M-8P ), is formed over compliant layer  2181  and metal connections  2182  other than at locations  2183 . Solder bumps  2185 , corresponding to solder bumps  2170  ( FIGS. 8O and 8P ), are formed onto metal connections  2182  at locations  2183 . 
         [0237]    At a second surface of silicon wafer die  2177  facing oppositely from the first surface, a plurality of bond pad specific notches  2186 , corresponding to notches  2120  ( FIGS. 8A-8P ), are shown, formed in silicon layer  2180 . 
         [0238]    The notches  2186  each expose one of bond pads  2178 . An electrophoretic, electrically insulative compliant layer  2187 , corresponding to electrophoretic, electrically insulative compliant layer  2122  ( FIGS. 8B-8P ), covers the second surface and extends along inclined surfaces of notches  2186 , but does not cover the bond pads  2178  which are exposed by notches  2186 . 
         [0239]    Patterned metal connections  2188 , corresponding to metal connections  2132  ( FIGS. 8D-8P ) extend from bond pads  2178  along the inclined surfaces of notches  2186  and over generally planar surfaces of compliant layer  2187  to solder bump locations  2189 , corresponding to solder bump locations  2136  ( FIGS. 8F-8P ). An encapsulant passivation layer  2190 , corresponding to encapsulant passivation layer  2134  ( FIGS. 8E-8P ), is formed over compliant layer  2187  and metal connections  2188  other than at locations  2189 . Solder bumps  2192 , corresponding to solder bumps  2140  ( FIGS. 8G-8P ), are formed onto metal connections  2188  at locations  2189 . 
         [0240]    Reference is now made to  FIGS. 9A-9Q , which are simplified sectional illustrations of another method for manufacturing packaged semiconductor chips in accordance with another preferred embodiment of the present invention. 
         [0241]    The method of  FIGS. 9A-9Q  employs the steps described hereinabove with reference to  FIGS. 1A-1C , which are followed by the steps shown in  FIGS. 9A-9Q . 
         [0242]    Reference is now made to  FIG. 9A , which shows the structure of  FIG. 1C  having bonded to surface  114  thereof an additional packaging layer  2500 , typically by means of a suitable adhesive  2502 , such as epoxy. 
         [0243]      FIG. 9B  shows the structure of  FIG. 9A  turned upside-down. Notches  2520 , preferably formed by photolithography employing plasma etching or wet etching techniques, are formed so as to extend through additional packaging layer  2500 , adhesive  2502  and semiconductor wafer  100  at locations which overlie, in the sense of  FIG. 9B , some of bond pads  108 , here designated by reference numeral  2521 . 
         [0244]      FIG. 9C  shows the formation of an electrophoretic, electrically insulative compliant layer  2522  over the additional packaging layer  2500 . Examples of suitable materials for compliant layer  2522  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  2522  encapsulates all exposed surfaces of the packaging layer  2500  and semiconductor wafer  100  other than bond pads  2521 . Compliant layer  2522  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0245]      FIG. 9D  illustrates the formation of a metal layer  2530 , by sputtering chrome, aluminum or copper. Metal layer  2530  extends from the bond pads  2521 , over the compliant layer  2522  and along the inclined surfaces of the additional packaging layer  2500 , adhesive  2502  and semiconductor wafer  100 , defined by notches  2520  onto outer, generally planar surfaces of the compliant layer  2522 . 
         [0246]    As shown in  FIG. 9E , metal connections  2532  are preferably formed by patterning the metal layer  2530 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  2532  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0247]      FIG. 9F  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  2534  over the metal connections  2532  and over the compliant layer  2522 . Preferably, the encapsulant forming the encapsulant passivation layer  2534  comprises solder mask.  FIG. 9G  shows patterning of the encapsulant passivation layer  2534 , preferably by photolithography, to define solder bump locations  2536 . 
         [0248]      FIG. 9H  illustrates the formation of solder bumps  2540  at locations  2536  on the metal connections  2532 , at which the encapsulant passivation layer  2534  is not present. 
         [0249]    Reference is now made to  FIG. 9I , which shows the structure of  FIG. 9H  turned upside-down. Notches  2550 , preferably formed by photolithography employing plasma etching or wet etching techniques, are formed at locations which overlie bond pads  2551 , which are bond pads  108  other than bond pads  2521 . The notches preferably do not extend through adhesive  112 . 
         [0250]    Turning to  FIG. 9J , it is seen that the adhesive  112  overlying bond pads  2551  and underlying notches  2550  is removed, preferably by dry etching. 
         [0251]      FIG. 9K  shows the formation of an electrophoretic, electrically insulative compliant layer  2552  over the packaging layer  110 , which is typically formed of silicon, glass or a suitable polymeric material such as, for example a polyimide. Compliant layer  2552  preferably provides protection to the device from alpha particles emitted by BGA solder balls. Examples of suitable materials for compliant layer  2552  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  2552  encapsulates all exposed surfaces of the packaging layer  110 . 
         [0252]      FIG. 9L  illustrates the formation of a metal layer  2560 , by sputtering chrome, aluminum or copper. Metal layer  2560  extends from the bond pads  2551 , over the compliant layer  2552  and along the inclined surfaces of the packaging layer  110 , defined by notches  2550  onto outer, generally planar surfaces of the compliant layer  2552 . 
         [0253]    As shown in  FIG. 9M , metal connections  2562  are preferably formed by patterning the metal layer  2560 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  2562  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0254]      FIG. 9N  illustrates the application, preferably by spray coating, of a second, electrically insulative, encapsulant passivation layer  2564  over the metal connections  2562  and over the compliant layer  2552 . Preferably, the encapsulant passivation layer  2564  comprises solder mask.  FIG. 9O  shows patterning of the encapsulant passivation layer  2564 , preferably by photolithography, to define solder bump locations  2566 . 
         [0255]      FIG. 9P  illustrates the formation of solder bumps  2570  at locations  2566  on the metal connections  2562  at which the encapsulant passivation layer  2564  is not present. 
         [0256]      FIG. 9Q  shows dicing of the wafer  100 , packaging layer  110  and packaging layer  2500  of  FIG. 9P  along scribe lines  2572  to produce a multiplicity of individually packaged stackable dies  2574 . 
         [0257]    Reference is now made to  FIG. 9R , which is a simplified partially cut away part-pictorial and part-sectional illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 9A-9Q . As seen in  FIG. 9Q , a notch  2575 , corresponding to notches  2550  ( FIGS. 9I-9Q ), is formed in a packaging layer  2576 , corresponding to packaging layer  110  ( FIG. 9A-9Q ) over a first surface of a silicon layer  2577 , corresponding to semiconductor wafer  100 , of silicon wafer die  2578 , corresponding to die  2574  ( FIG. 9Q ). 
         [0258]    The notch  2575  exposes a row of bond pads  2579 , corresponding to bond pads  108  ( FIGS. 9A-9Q ). A layer  2580  of adhesive, corresponding to layer  112  ( FIGS. 9A-9Q ), covers the first surface of the silicon layer  2577  other than at notch  2575  and packaging layer  2576  covers the adhesive  2580 . An electrophoretic, electrically insulative compliant layer  2582 , corresponding to electrophoretic, electrically insulative compliant layer  2552  ( FIGS. 9J-9Q ), covers the packaging layer  2576  and extends along inclined surfaces of notch  2575 , but does not cover the bond pads  2579 . 
         [0259]    Patterned metal connections  2583 , corresponding to metal connections  2562  ( FIGS. 9L-9Q ) extend from bond pads  2579  along the inclined surfaces of notch  2575  and over generally planar surfaces of compliant layer  2582  to solder bump locations  2584 , corresponding to solder bump locations  2566  ( FIGS. 9O-9Q ). An encapsulant passivation layer  2585 , corresponding to encapsulant passivation layer  2564  ( FIGS. 9N-9Q ), is formed over compliant layer  2582  and metal connections  2583  other than at locations  2584 . Solder bumps  2586 , corresponding to solder bumps  2570  ( FIGS. 9P and 9Q ), are formed onto metal connections  2583  at locations  2584 . 
         [0260]    At a second surface of silicon layer  2577 , facing oppositely from the first surface, a packaging layer  2586 , corresponding to packaging layer  2500  ( FIGS. 9A-9Q ) is bonded by an adhesive layer  2590 , corresponding to adhesive  2502  ( FIGS. 9A-9Q ). 
         [0261]    A plurality of bond pad specific notches  2591 , corresponding to notches  2520  ( FIGS. 9B-9Q ), are shown, extending through packaging layer  2586 , adhesive layer  2590  and silicon layer  2577 . 
         [0262]    The notches  2591  each expose one of bond pads  2579 . An electrophoretic, electrically insulative compliant layer  2592 , corresponding to electrophoretic, electrically insulative compliant layer  2522  ( FIGS. 9C-9Q ), covers the packaging layer  2586  and extends along inclined surfaces of notches  2591 , but does not cover the bond pads  2579  which are exposed by notches  2591 . 
         [0263]    Patterned metal connections  2593 , corresponding to metal connections  2532  ( FIGS. 9D-9Q ) extend from bond pads  2579  along the inclined surfaces of notches  2591  and over generally planar surfaces of compliant layer  2592  to solder bump locations  2594 , corresponding to solder bump locations  2536  ( FIGS. 9G-9Q ). An encapsulant passivation layer  2595 , corresponding to encapsulant passivation layer  2534  ( FIGS. 9F-9Q ), is formed over compliant layer  2592  and metal connections  2593  other than at locations  2594 . Solder bumps  2596 , corresponding to solder bumps  2540  ( FIGS. 9H-9Q ), are formed onto metal connections  2593  at locations  2594 . 
         [0264]    Reference is now made to  FIGS. 10A-10I  which illustrate additional alternative methodologies which may be used for some or all of the bond pads  108  ( FIG. 1A ). These methodologies are particularly useful for devices, such as DRAMs, having a high density of bond pads  108 . 
         [0265]      FIG. 10A  shows the formation of an encapsulant passivation layer  3000  over surface  104  of the structure of  FIG. 1A . 
         [0266]      FIG. 10B  shows patterning of the encapsulant passivation layer  3000 , preferably by photolithography, to expose bond pads  108 .  FIG. 10C  illustrates the formation of a metal layer  3030 , by sputtering chrome, aluminum or copper over the encapsulant passivation layer  3000 . 
         [0267]    As shown in  FIG. 10D , metal connections  3032  are preferably formed by patterning the metal layer  3030 , to extend from some of the bond pads  108  and over generally planar encapsulant passivation layer  3000 . Metal connections  3032  preferably are formed by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  3032  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0268]      FIG. 10E  shows a wafer-scale packaging layer  3034  attached to encapsulant passivation layer  3000  by an adhesive  3036  such as epoxy. 
         [0269]      FIG. 10F  shows notches  3038 , preferably formed by photolithography employing plasma etching or wet etching techniques, at locations which overlie some of bond pads  108 , here designated by reference numeral  3040 .  FIG. 10F  also shows notches  3048 , preferably formed by photolithography employing plasma etching or wet etching techniques, at locations which overlie corresponding portions of metal connections  3032  at locations designated by reference numeral  3050 . The notches  3038  and  3048  preferably do not extend through adhesive  3036 . 
         [0270]    Turning to  FIG. 10G , it is seen that the adhesive  3036 , overlying bond pads  3040  and locations  3050  of metal connections  3032 , is removed, preferably by dry etching. 
         [0271]      FIG. 10H  shows the formation of an electrophoretic, electrically insulative compliant layer  3060  over the packaging layer  3034 . Examples of suitable materials for compliant layer  3060  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  3060  encapsulates all exposed surfaces of the packaging layer  3034 . Compliant layer  3060  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0272]      FIG. 10I  illustrates the formation of a second metal layer  3070  by sputtering chrome, aluminum or copper. Metal layer  3070  extends from the metal connections  3032  and the bond pads  3040  over the compliant layer  3060 . 
         [0273]    As shown in  FIG. 10J , metal connections  3071  and  3072  are preferably formed by patterning metal layer  3070 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  3071  and  3072  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. It is noted that metal connections  3071  extend from bond pads  3040  and metal connections  3072  extend from metal connections  3032  at locations  3050 . 
         [0274]      FIG. 10K  shows the application, preferably by spray coating, of an additional, electrically insulative, encapsulant passivation layer  3073  over the metal connections  3071  and  3072  and over the compliant layer  3060 . Preferably, the encapsulant passivation layer  3073  comprises solder mask.  FIG. 10L  shows patterning of the encapsulant passivation layer  3073 , preferably by photolithography, to define solder bump locations  3074  and  3075  on metal connections  3071  and  3072 , respectively. 
         [0275]    As seen in  FIG. 10L , the semiconductor wafer  100  is thinned, as by machining its non-active surface  114 . Preferably, the thickness of the semiconductor wafer  100  at this stage, following thinning thereof, is 300 microns. It is appreciated that the semiconductor wafer  100  may be thinned at any stage prior to the formation of solder bumps on dies  102 . 
         [0276]      FIG. 10M  illustrates the formation of solder bumps  3076  at respective locations  3074  and  3075  on the metal connections  3071  and  3072 , at which the encapsulant passivation layer  3073  is not present. 
         [0277]      FIG. 10N  shows dicing of the wafer and packaging layer of  FIG. 10M  along scribe lines  3077  to produce a multiplicity of individually packaged dies  3078 . 
         [0278]    Reference is now made to  FIG. 10O , which is a simplified pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 10A-10N . As seen in  FIG. 10O , notches  3079  and  3080 , respectively corresponding to notches  3038  and  3048  ( FIGS. 10F-10N ), are formed in a packaging layer  3081 , corresponding to packaging layer  3034  ( FIGS. 10E-10N ), of silicon wafer die  3082 , corresponding to die  3078  ( FIG. 10N ). 
         [0279]    A silicon layer  3083 , corresponding to semiconductor wafer  100  ( FIGS. 10A-10N ) is covered by an encapsulant passivation layer  3084 , corresponding to encapsulant passivation layer  3000  ( FIGS. 10A-10N ), other than over some of bond pads  3085 , which correspond to bond pads  3040  ( FIGS. 10A-10N ). Patterned metal connections  3086 , corresponding to metal connections  3032  ( FIGS. 10D-10N ), extend from some of bond pads  3085  over generally planar surfaces of encapsulant passivation layer  3084 . 
         [0280]    Packaging layer  3081  is bonded over encapsulant passivation layer  3084  and metal connections  3086  by an adhesive layer  3087 , corresponding to adhesive  3036  ( FIGS. 10E-10N ). 
         [0281]    Notch  3080  extends through packaging layer  3081  and adhesive layer  3087  to corresponding portions of metal connections  3086  at locations designated by reference numeral  3088 , which correspond to locations  3050  ( FIGS. 10F-10N ). 
         [0282]    Notch  3079  extends through packaging layer  3081 , adhesive layer  3087  and encapsulant passivation layer  3084  to those of bond pads  3085  which are not connected to metal connections  3086 . 
         [0283]    An electrophoretic, electrically insulative compliant layer  3089 , corresponding to electrophoretic, electrically insulative compliant layer  3060  ( FIGS. 10G-10N ), covers the packaging layer  3081  and extends along inclined surfaces of notches  3079  and  3080 , but does not cover the bond pads  3085 . 
         [0284]    Patterned metal connections  3090 , corresponding to metal connections  3071  ( FIGS. 10J-10N ), extend from bond pads  3085  which are not connected to metal connections  3086 , along the inclined surfaces of notch  3079  and over generally planar surfaces of compliant layer  3089  to solder bump locations  3091 , corresponding to solder bump locations  3074  ( FIGS. 10L-10N ). 
         [0285]    Patterned metal connections  3092 , corresponding to metal connections  3072  ( FIGS. 10J-10N ), extend from portions of metal connections  3085  at locations  3088 , along the inclined surfaces of notch  3080  and over generally planar surfaces of compliant layer  3089  to solder bump locations  3093 , corresponding to solder bump locations  3075  ( FIGS. 10L-10N ). 
         [0286]    An encapsulant passivation layer  3094 , corresponding to encapsulant passivation layer  3073  ( FIGS. 10K-10N ), is formed over compliant layer  3089  and metal connections  3090  and  3092  other than at locations  3091  and  3093 . Solder bumps  3095 , corresponding to solder bumps  3076  ( FIGS. 10M and 10N ), are formed onto respective metal connections  3090  and  3092  at respective locations  3091  and  3093 . 
         [0287]    Reference is now made to  FIGS. 11A-11J , which are simplified sectional illustrations of a method for manufacturing packaged stacked semiconductor chips in accordance with a further preferred embodiment of the present invention. 
         [0288]    The method of  FIGS. 11A-11J  employs the steps described hereinabove with reference to  FIGS. 10A-10D , which are followed by the steps shown in  FIGS. 11A-11J . 
         [0289]    Reference is now made to  FIG. 11A , which shows face-to-face bonding of the structure of  FIG. 1A , turned upside-down, here designated by reference numeral  3400 , to the structure of  FIG. 10D , here designated by reference numeral  3402 , preferably by means of an adhesive  3406  such as epoxy. It is appreciated that the pitch of bond pads on structures  3400  and  3402  is typically different, as shown, and that the bond pads of structures  3400  and  3402  are typically not in registration. 
         [0290]      FIG. 11B  shows the formation of notches  3408  and  3409 , preferably by photolithography employing plasma etching or wet etching techniques, at locations which overlie respective bond pads  3410  and  3411 .  FIG. 11B  also shows notches  3412 , preferably formed by photolithography employing plasma etching or wet etching techniques, at locations which overlie corresponding portions of metal connections  3032  at locations designated by reference numeral  3414 . The notches  3412  preferably do not extend through adhesive  3406 . 
         [0291]    Turning to  FIG. 11C , it is seen that the adhesive  3406 , overlying metal connections  3032  at locations  3414 , is removed, preferably by dry etching. 
         [0292]      FIG. 11D  shows the formation of an electrophoretic, electrically insulative compliant layer  3420  over exposed silicon surfaces of semiconductor wafer  100  of structure  3400 . Examples of suitable materials for compliant layer  3420  are those described hereinabove with reference to  FIG. 1F . Once cured, compliant layer  3420  encapsulates all exposed surfaces of the semiconductor wafer  100  of structure  3400 . Compliant layer  3420  preferably provides protection to the device from alpha particles emitted by BGA solder balls. 
         [0293]      FIG. 11E  illustrates the formation of a metal layer  3430  by sputtering chrome, aluminum or copper. Metal layer  3430  extends from the metal connections  3032  at locations  3414  and from bond pads  3410  and  3411  over the compliant layer  3420 . 
         [0294]    As shown in  FIG. 11F , metal connections  3432  and  3434  are preferably formed by patterning metal layer  3430 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  3432  and  3434  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. It is noted that metal connections  3432  extend from bond pads  3410  and metal connections  3434  interconnect metal connections  3032  at locations  3414  with bond pads  3411 . 
         [0295]      FIG. 11G  shows the application, preferably by spray coating, of an electrically insulative, encapsulant passivation layer  3440  over the metal connections  3432  and  3434  and over the compliant layer  3420 . Preferably, the encapsulant forming the encapsulant passivation layer  3440  comprises solder mask.  FIG. 11H  shows patterning of the encapsulant passivation layer  3440 , preferably by photolithography, to define solder bump locations  3441  and  3442 . 
         [0296]    As seen in  FIG. 11H , the semiconductor wafer  100  of structure  3402  is thinned, as by machining its non-active surface  114 . Preferably, the thickness of the semiconductor wafer  100  at this stage, following thinning thereof, is 300 microns. It is appreciated that the semiconductor wafer  100  of structure  3402  may be thinned at any stage prior to the formation of solder bumps on structure  3400 . 
         [0297]      FIG. 11I  illustrates the formation of solder bumps  3444  at respective locations  3441  and  3442  on the metal connections  3432  and  3434 , at which the encapsulant passivation layer  3440  is not present. 
         [0298]      FIG. 11J  shows dicing of the wafer and packaging layer of  FIG. 11I  along scribe lines  3448  to produce a multiplicity of individually packaged dies  3450 . 
         [0299]    Reference is now made to  FIG. 11K , which is a simplified pictorial illustration of part of a packaged semiconductor chip manufactured in accordance with the method of  FIGS. 11A-11J . As seen in  FIG. 11K , notches  3451 ,  3452  and  3453 , respectively corresponding to notches  3408 ,  3409  and  3412  ( FIGS. 11B-11J ), are formed in a portion of a semiconductor wafer  3454 , corresponding to a portion of semiconductor wafer  100  ( FIGS. 11A-11J ), which forms part of structure  3455 , corresponding to structure  3400  ( FIGS. 11A-11J ). 
         [0300]    An adhesive layer  3456 , corresponding to adhesive  3406  ( FIGS. 11A-11J ) joins an active surface of structure  3455  to a passivation layer  3458 , corresponding to layer  3000  ( FIGS. 10A-10D ). Passivation layer  3458  covers an active surface of a portion of a semiconductor wafer  3459 , corresponding to a portion of a semiconductor wafer which forms part of structure  3402  ( FIGS. 11A-11J ) other than over bond pads  3460 , which correspond to bond pads  3033  ( FIG. 10D ). Patterned metal connections  3462 , corresponding to metal connections  3032  ( FIGS. 10D-10N ), extend from bond pads  3460  over generally planar surfaces of passivation layer  3458  and underlying adhesive layer  3456 . 
         [0301]    Notch  3453  extends through the portion of semiconductor wafer  3454  and adhesive layer  3456  to portions of metal connections  3462  at locations designated by reference numeral  3464 , which correspond to locations  3414  ( FIGS. 11B-11J ). 
         [0302]    Notch  3451  extends through the portion of semiconductor wafer  3454  to bond pad  3466 , corresponding to bond pad  3410  ( FIGS. 11A-11J ). 
         [0303]    Notch  3452  extends through the portion of semiconductor wafer  3454  to bond pad  3468 , corresponding to bond pad  3411  ( FIGS. 11A-11J ). 
         [0304]    An electrophoretic, electrically insulative compliant layer  3470 , corresponding to electrophoretic, electrically insulative compliant layer  3420  ( FIGS. 11C-11J ), covers the exposed surfaces of the portion of semiconductor wafer  3454 . 
         [0305]    Metal connections  3472 , corresponding to metal connections  3432  ( FIGS. 11F-11J ), extend from bond pads  3466  over generally planar surfaces of coating  3470  to solder bump locations  3476 , corresponding to solder bump locations  3441  ( FIGS. 11I and 11J ). 
         [0306]    Metal connections  3478  interconnect metal connections  3462  at locations  3464  with bond pads  3468  and extend over generally planar surfaces of coating  3470  to solder bump locations  3480 , corresponding to solder bump locations  3442  ( FIGS. 11I and 11J ). 
         [0307]    A passivation layer  3482 , corresponding to encapsulant layer  3440  ( FIGS. 11G-11J ) is formed over coating  3470  and metal connections  3472  and  3478  other than at locations  3476  and  3480 . Solder bumps  3484 , corresponding to solder bumps  3444  ( FIGS. 11I and 11J ), are formed onto respective metal connections  3472  and  3478  at respective locations  3476  and  3480 . 
         [0308]    Reference is now made to  FIG. 12 , which illustrates a stacked structure formed of two devices of the type shown in  FIG. 8Q , which correspond to individually packaged stackable dies  2174 , preferably manufactured in accordance with the description hereinabove referencing  FIGS. 8A-8P . It is seen that the solder bumps  2184  ( FIG. 8Q ) of an upper one of the devices are soldered together to corresponding solder bumps  2190  ( FIG. 8Q ) of a lower one of the devices. 
         [0309]    Reference is now made to  FIG. 13 , which illustrates a stacked structure formed of two devices of the type shown in  FIG. 9R , which correspond to individually packaged stackable dies  2574 , preferably manufactured in accordance with the description hereinabove referencing  FIGS. 9A-9Q . It is seen that the solder bumps  2584  ( FIG. 9R ) of an upper one of the devices are soldered together to corresponding solder bumps  2592  ( FIG. 9R ) of a lower one of the devices. 
         [0310]    Reference is now made to  FIG. 14 , which shows a packaged semiconductor DRAM chip  4000 , which is similar in all relevant respects to the DRAM of  FIG. 1M , but wherein solder bumps  168  are replaced by thickened ACF attachable interconnects  4068 , typically having a thickness of 10 microns and being formed of copper. In this embodiment an encapsulant layer  4070  preferably fills the notches  150  ( FIG. 1M ). 
         [0311]    As seen in  FIG. 14 , a PCB  4072  is formed on an underside thereof with thickened ACF attachable interconnects  4074 , typically having a thickness of 10 microns and being formed of copper. An anisotropic conductive film  4076  bonds the PCB  4072  to the DRAM chip  4000 , in accordance with conventional ACF attachment techniques. 
         [0312]    Reference is now made to  FIGS. 15A-15D , which are simplified sectional illustrations of an additional method for manufacturing and mounting packaged semiconductor chips, preferably DRAM chips, in accordance with a further preferred embodiment of the present invention. 
         [0313]    The method of  FIGS. 15A-15D  employs the steps described hereinabove with reference to  FIGS. 1A-1I , which are followed by the steps shown in  FIGS. 15A-15D . 
         [0314]    Reference is now made to  FIG. 15A , which shows patterning of encapsulant layer  134  of the structure of  FIG. 1I , preferably by photolithograpy, defining a die  4100 . 
         [0315]      FIG. 15B  shows gold plating of portions of metal connections  132  at locations at notches  120  where the metal connections  132  are not covered by the encapsulant layer  134 . The gold plating layer is designated by reference numeral  4102 . 
         [0316]      FIG. 15C  shows a PCB  4104  having metal pins  4106  coated with an Indium layer  4108  in registration with gold plated surfaces of notches  120 . 
         [0317]      FIG. 15D  shows the structure of  FIG. 15B  mounted onto pins  4106  of PCB  4104  by eutectic Au/In intermetallic bonding. As seen in  FIG. 15D , the method of  FIGS. 15A-15D  can be employed for producing and mounting a DRAM chip  4110 , such as onto PCB  4104 . 
         [0318]    Reference is now made to  FIGS. 16A and 16B , which are simplified sectional illustrations of a further method for manufacturing and mounting packaged semiconductor chips in accordance with a further preferred embodiment of the present invention. 
         [0319]    The method of  FIGS. 16A and 16B  employs the steps described hereinabove with reference to  FIGS. 15A and 15B , which are followed by the steps shown in  FIGS. 16A and 16B . 
         [0320]    Reference is now made to  FIG. 16A , which shows a die  4200 , similar in all relevant respects to die  144  of  FIG. 1L , but having metal pins  4204  coated with an Indium layer  4206 . In this embodiment the encapsulant layer  134  preferably fills the notches  120 . 
         [0321]    Die  4200  is shown turned upside-down and having pins  4204  in registration with gold plated surfaces of notches  120  of die  4100  ( FIG. 15B ). 
         [0322]      FIG. 16B  shows die  4100  mounted onto pins  4204  of die  4200  by eutectic Au/In intermetallic bonding. As seen in  FIG. 16B , the method of  FIGS. 16A and 16B  can be employed for producing and mounting a DRAM chip  4210  onto another device, such as another DRAM chip  4212 . 
         [0323]    Reference is now made to  FIGS. 17A and 17B , which are simplified illustrations of a method for manufacturing and mounting stacked packaged semiconductor chips in accordance with a preferred embodiment of the present invention. 
         [0324]    The method of  FIGS. 17A and 17B  may employ any of the semiconductor devices described hereinabove. In the illustrated embodiment, a device comprising stacked, packaged semiconductor chips, here designated by reference numeral  4300 , such as a DRAM device, is formed with side contacts  4302  and is configured to be mounted on a PCB  4304  having similarly configured contracts  4306 .  FIG. 17B  shows the DRAM device  4300  mounted onto PCB  4304 . 
         [0325]    Reference is now made to  FIGS. 18A-18L , which are simplified sectional illustrations of yet a further method for manufacturing packaged semiconductor chips in accordance with yet a further preferred embodiment of the present invention. 
         [0326]    The method of  FIGS. 18A-18L  employs the steps described hereinabove with reference to  FIGS. 4A-4D , which are preceded by the steps shown in  FIGS. 18A-18C  and followed by the steps shown in  FIGS. 18D-18L . 
         [0327]    Reference is now made to  FIG. 18A , which shows the structure of  FIG. 1A  having placed thereon a punched adhesive film  4400 , preferably formed of suitable polymers, such as, for example MC-550 or MC-795 commercially available from Mitsui Chemicals Inc. of Tokyo, Japan, which include epoxy, polyimide and inorganic filler. The adhesive film  4400  preferably has relatively high density and a thickness of 50 microns or less, thereby protecting the device from alpha particles emitted by BGA solder balls. As seen clearly in the enlarged portion of  FIG. 18A , the adhesive film  4400  has channels  4402  punched therein, which are aligned with bond pads  108  and allow access thereto when the adhesive film  4400  is attached to wafer  100 . The adhesive film  4400  preferably is cured following placement thereof on the wafer  100 . 
         [0328]      FIG. 18B  shows thinning of wafer  100 , having adhesive film  4400  attached thereto, preferably by machining its non-active surface  114 . Preferably the thickness of the semiconductor wafer  100  at this stage, following thinning thereof, is 300 microns.  FIG. 18C  shows the structure of  FIG. 18B  following patterning of the adhesive film  4400 , preferably by dicing the adhesive film  4400  with an angled blade following curing of the adhesive. 
         [0329]      FIG. 18D  shows the wafer similar to wafer  500  of  FIG. 4D  but having deeper recesses, turned upside down and bonded onto the adhesive film  4400  of  FIG. 18C , with a surface  512 , opposite surface  504  being exposed. 
         [0330]      FIG. 18E  shows thinning of wafer  500 , preferably by grinding surface  512 , down to a thickness equal to the depth of recesses  502 , typically 100 microns. 
         [0331]      FIG. 18F  shows removal of the remainder of wafer  500  surrounding platforms  507  of compliant material  506 , as by silicon etching and ultrasonic cleaning. 
         [0332]      FIG. 18G  illustrates the formation of a metal layer  4404 , by sputtering chrome, aluminum or copper. Metal layer  4404  extends from the bond pads  108 , along the inclined surfaces of adhesive film  4400 , onto outer, generally planar surfaces of the adhesive film  4400  and over platforms  507  at dies  102 . 
         [0333]    As shown in  FIG. 18H , metal connections  4406  are preferably formed by patterning the metal layer  4404 , preferably by 3D photolithography employing a suitable photoresist, preferably Eagle 2100, commercially available from Rohm and Haas Shipley Division of Marlborough, Mass., U.S.A. Optionally, the metal connections  4406  may be plated with nickel, as by electroless techniques, in order to provide enhanced corrosion resistance. 
         [0334]      FIG. 18I  illustrates the application, preferably by spray coating, of an electrically insulative, encapsulant passivation layer  4408  over the metal connections  4406 , over the adhesive film  4400  and over platforms  507 . Preferably, the encapsulant passivation layer  4408  comprises solder mask.  FIG. 18J  shows patterning of the encapsulant passivation layer  4408 , preferably by photolithography, to define solder bump locations  4409 . 
         [0335]      FIG. 18K  illustrates the formation of solder bumps  4410  onto platforms  507  at locations  4409  on the metal connections  4406  at which the encapsulant passivation layer  4408  is not present. 
         [0336]      FIG. 18L  shows dicing of the wafer  100  and adhesive film  4400  of  FIG. 18K  along scribe lines  4412  to produce a multiplicity of individually packaged dies  4414 . 
         [0337]    Reference is now made to  FIG. 18M , which is a simplified partially cut away pictorial illustration of part of a packaged semiconductor DRAM chip manufactured in accordance with the method of  FIGS. 18A-18L . As seen in  FIG. 18M , a channel  4440 , produced by punching and dicing of an adhesive film  4442 , corresponding to adhesive film  4400  ( FIG. 18A ), of a silicon wafer die  4443 , corresponding to silicon wafer die  4414  ( FIG. 18L ). The channel  4440  exposes a row of bond pads  4454 , corresponding to bond pads  108  ( FIGS. 18A-18L ), which are formed on a substrate  4456 , corresponding to substrate  100  ( FIGS. 18A-18L ). Platforms  4462 , corresponding to platforms  507  ( FIGS. 18F-18L ) are formed over adhesive film  4442  at solder bump locations  4464 , corresponding to solder bump locations  4409  ( FIGS. 18J-18L ). 
         [0338]    Patterned metal connections  4466 , corresponding to metal connections  4406  ( FIGS. 18H-18L ), extend from bond pads  4454  along the inclined surfaces of channel  4440  and over generally planar surfaces of adhesive film  4442  and terminate over platforms  4462 . An encapsulant passivation layer  4468 , corresponding to encapsulant passivation layer  4408  ( FIGS. 18I-18L ), is formed over adhesive film  4442  and metal connections  4466  other than at locations  4464 . Solder bumps  4470 , corresponding to solder bumps  4410  ( FIGS. 18K and 18L ), are formed onto metal connections  4466  at locations  4464 . 
         [0339]    It will be appreciated by persons skilled in the art that the present invention is not limited by what has been specifically claimed herein. Rather the scope of the present invention includes both combinations and sub-combinations of various features described hereinabove as well as modifications thereof which may occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.