Abstract:
The invention proposes a system and method for extending the maximum duty cycle of a step-down switching converter to nearly 100% while maintaining a constant switching frequency. The system includes a voltage mode or current mode step-down converter driven by a leading edge blanking (LEB) signal, which operates at the desired switching frequency. More particularly, the LEB signal is connected to a slope generator and/or a current sense network. In each switching cycle, the LEB signal forces the slope signal and/or current sense signal to reset, thereby achieving a constant switching frequency. Corresponding methods for how to extend the maximum duty cycle of a step-down switching converter while maintaining a constant frequency are also disclosed.

Description:
FIELD OF INVENTION 
       [0001]    This invention generally relates to power from power supply or regulation systems. More specifically, the present invention relates to the system and method for maximizing duty and maintaining constant switching frequency without the use of maximum duty control circuitry. 
       BACKGROUND 
       [0002]    A switching converter regulates power supplied to a load by modulating the duty ratio of a power switch that connects the power from a source to the load. The circuit diagram of a prior art step-down switching converter circuit without maximum duty control is depicted in  FIG. 1 . The prior art converter shown in  FIG. 1  comprises a pair of switches Q 1  and Q 2  connected in series between an input voltage V IN  and a ground node GND. A phase node  107  of switches Q 1  and Q 2  is simultaneously connected to a first end of an inductor L and to a current sense network  101 , which generates a current signal I SNS  indicative of the current through inductor L when the high-side switch Q 1  is turned on. The current signal I SNS  is then connected to a summation network  108  wherein I SNS  is combined with a slope signal I SLOPE  generated from a slope signal generator  110  to produce a combined current signal I SLOPE+SNS . A second end of inductor L is connected to an output node  111  having an output voltage V OUT . The output node is further connected to a load network  102  and a voltage divider formed by resistors R 1  and R 2 . The voltage divider produces a feedback voltage V FB  indicative of V OUT . V FB  and a reference voltage V REF  are connected respectively to the inverting input and the noninverting input of an error amplifier  104 . The error amplifier  104  compares V FB  to V REF  and amplifies their difference. A compensation network  103 , such as a Type II network formed by passive elements R 3 , C 1 , and C 2 , is connected to the output of the error amplifier  104 , thereby generating an error signal V COMP . V COMP  and a voltage signal V SUM  indicative of I SLOPE+SNS  are respectively connected to the inverting input and the noninverting input of a pulse width modulation (“PWM”) comparator  105 , which compares V COMP  to V SUM  and generates an output signal RESET. RESET and a clock signal CLK are respectively connected to the R input and the S input of a reset-dominant latch  106 , which outputs a DUTY signal that is provided to a gate driver GD  109 . The gate driver GD  109  generates HS and LS signals to control the switching frequency of switches Q 1  and Q 2 , thereby achieving the regulation of power supplied to the load network  102 . 
         [0003]      FIG. 2  is a waveform diagram for the prior art converter shown in  FIG. 1  wherein the voltage of V IN , V OUT , V COMP , and V SUM  are plotted versus time. In each switching cycle, the control signal V SUM  starts at a base voltage V SUM0  at the base of the slope and increases at an approximately constant slew rate. As V SUM  rises to the same voltage as V COMP , which serves as a ceiling, V SUM  resets to its initial voltage V SUM0  and repeat the slope cycle. During a typical switching cycle, the relationship between the switching frequency, the slew rate of V SUM , and V COMP  is expressed in EQ. (1), wherein F S  is the switching frequency, T S  is the switching period, m is the slew rate, and V SUM0  is the base voltage of V SUM . 
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         [0004]      FIG. 2  is partitioned into three temporal phases to elucidate the problem encountered by the prior art converter when the input-output voltage differential (i.e., the difference between V IN  and V OUT ) temporarily falls below the dropout voltage V THRESHOLD . In Phase I, V IN , V OUT , and V COMP  are in their respective steady state conditions when the input-output voltage differential is greater than the dropout voltage V THRESHOLD . The switching frequency of the converter in Phase I can be characterized by EQ. (2), wherein F S1 , T S1 , and V COMP1  are, respectively, the switching frequency, the switching period, and V COMP  in Phase I. The voltage of slope signal V SUM  starts from the base voltage V SUM0 , increases to V COMP1 , then resets back to V SUM0 . Operation in this manner repeats every T S1  second and maintains a switching frequency of F S1  until V COMP  changes. 
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         [0005]    In Phase II, over the period from t 1  to t 3 , V IN  falls from the initial steady state voltage to below the target voltage for V OUT . At time t 2 , V OUT  begins to decrease as the input-output voltage differential falls below the dropout voltage V THRESHOLD . The drop in V OUT  triggers a compensation response in which V COMP  rises to increase V OUT  to its initial target voltage. However, since V OUT  cannot exceed V IN , V OUT  is prevented from attaining the target voltage when V IN  is lower than the target voltage. While V OUT  is lower than the target voltage, V COMP  continues to increase until it saturates, at which point V COMP  levels out. As previously mentioned, V COMP  provides the upper threshold for triggering V SUM  to reset; increasing V COMP  causes V SUM  to slope up unrestricted until it also saturates. 
         [0006]    From time t 4  to t 6 , V IN  is gradually restored to its initial steady-state value. As V IN  increases, the input-output voltage differential and V OUT  also begin to increase. At t S , the input-out voltage differential exceeds V THRESHOLD , at which point V OUT  is restored to its target voltage. In response to the increase in V OUT , V COMP  gradually decreases until a new steady-state value is achieved at time t 7 . When V COMP  decreases to the same voltage as V SUM , the slope signal V SUM  resets and resumes the aforementioned slope and reset cycle. 
         [0007]    In Phase III, both V IN  and V OUT  are restored to their original steady-state voltage. V COMP  levels out to a new steady-state voltage V COMP3 , which may be different from the initial steady-state voltage V COMP1 . The switching frequency of the converter in Phase III can be characterized by EQ. (3), wherein F S3 , T S3 , and V COMP3  are, respectively, the switching frequency, the switching period, and V COMP  in Phase III. 
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         [0008]    Since the slew rate of V SUM  is approximately constant and V COMP  provides the upper threshold for triggering V SUM  to reset the slope cycle, the duration of each slope cycle depends on the difference between V COMP  and V SUM0 . The greater the difference between V COMP  and V SUM0 , the longer V SUM  would take to reach the V COMP  threshold. It was previously introduced in EQ. (1) that the switching period T S  is the inverse of the switching frequency F S . When a change in Wow causes the switching period T S  to change, the switching frequency F S  also changes. By way of example, assume that V SUM0  is 0 and that V COMP3 =2V COMP1 ; then the relationship between the switching frequencies F S1  and F S3 , can be derived by algebraic manipulation of EQs. (2) through (5). Substituting EQs. (2) and (4) into EQ. (6), it is determined that the switching frequency is reduced by half when V COMP  is doubled. 
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         [0009]    The above example demonstrates that the switching frequency of the prior art converter is dependent on V COMP . The tendency for the switching frequency to drift after the circuit experiences a temporary anomalous decrease in the input voltage renders this prior art converter unsuitable for applications where the maintenance of a constant switching frequency is desirable or even essential. 
       BRIEF SUMMARY OF THE INVENTION 
       [0010]    In view of the above, the present invention provides a system and method for extending the maximum duty cycle of a step-down switching converter to nearly 100% while maintaining a constant switching frequency. The system includes a voltage mode or current mode step-down converter driven by a leading edge blanking (LEB) signal, which operates at the desired switching frequency. More specifically, the LEB signal is connected to a slope generator and/or a current sense network. In each switching cycle, the LEB signal forces the slope signal and/or current sense signal to reset, thereby achieving a constant switching. Corresponding methods for how the system operates is also described. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings: 
           [0012]      FIG. 1  is a block diagram of a prior art step-down switching converter; 
           [0013]      FIG. 2  is a waveform diagram of V IN , V OUT , V COMP , and V SUM  from the prior art step-down switching converter plotted versus time; 
           [0014]      FIG. 3A  is a simplified block diagram of a first embodiment of the present invention; 
           [0015]      FIG. 3B  is a detailed circuit diagram of a circuit according to the first embodiment of the present invention; 
           [0016]      FIG. 4A  is a simplified block diagram of a second embodiment of the present invention; 
           [0017]      FIG. 4B  is a detailed circuit diagram of a circuit according to the second embodiment of the present invention; 
           [0018]      FIG. 5A  is a simplified block diagram of a third embodiment of the present invention; 
           [0019]      FIG. 5B  is a detailed circuit diagram of a circuit according to the third embodiment of the present invention; 
           [0020]      FIG. 6  illustrates a number of waveforms associated with the operation of the step-down switching converter of the present invention; 
       
    
    
       [0021]    Like reference numbers and designations in the various drawings indicate like elements. 
       DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0022]    Various features of the embodiments of the present invention are herein described in detail with reference to the drawings, where like reference numbers represent like elements throughout the several views. The drawings are not necessarily drawn to scale, and in some cases have been exaggerated and/or simplified for illustrative purposes only. Reference to a particular embodiment does not limit the scope of the present invention. One of ordinary skill in the art will appreciate the many possible applications and variations based on the general principles defined herein and that may be applied to other embodiments. The present invention is to be accorded the widest scope consistent with the principles and novel features herein disclosed. 
         [0023]    Referring to  FIG. 3A , a block diagram of a first embodiment of the present invention is disclosed. The first embodiment comprises a timing element-driven LEB network  309  connected to a voltage-mode step-down switching converter. According to this embodiment, an input voltage V IN  is connected to a switch network  301 , which is further connected to a ground node GND. A phase node  308  in the switch network  301  is connected to a load network  302  via inductor L. An output voltage V OUT  measured across the load network  302  is provided to a feedback network  303 , which generates a feedback signal V FB  indicative of the output voltage. The feedback signal V FB  and a reference signal V REF  indicative of a target voltage of V OUT  are provided to an error amplifier  304 . The error amplifier  304  produces an output signal V COMP , which is connected to and stabilized by a compensation network  305 . A timing element CLK 1  provides a constant frequency clock signal to the LEB network  309  representing the desired switching frequency. The LEB network  309  then produces an LEB signal and an RSTB signal based on the LEB signal. The RSTB signal is active low and is the inverse of the LEB signal. A slope signal generator  310 , which produces a slope signal I SLOPE , receives and uses the RSTB signal to reset the slope signal I SLOPE  at the frequency of CLK 1 . V COMP , I SLOPE , and a timing signal CLK 2  are provided to a PWM network  306 , which generates a DUTY signal. A gate driver GD  307  then receives the DUTY signal and generates one or more control signals to control the on/off duration of switches within the switch network  301 , through which the power delivered to the load network  302  is modulated. 
         [0024]    The circuit diagram in  FIG. 3B  is a circuit using the configuration described in the first embodiment of the present invention. A clock signal CLK 1  from a timing element is provided to the LEB network  309 . The LEB network  309  comprises a first inverter  309   a , a delay network DLY  309   b , a NOR gate  309   c , and a second inverter  309   d . The CLK 1  signal representing the desired switching frequency is provided to both the first inverter  309   a  and DLY  309   b . The output of the first inverter  309   a  and the output of DLY  309   b  are respectively connected to the first and the second input of the NOR gate  309   c , which produces an LEB signal. In a given cycle, the LEB signal starts in the high-state, then switches to the low-state, then rises back to the high-state at the end of the cycle. The duration that the LEB signal remains in the high-state depends on the design parameters of the delay network DLY. The LEB signal is then provided to the second inverter  309   d , which inverts the LEB signal to produce the RSTB signal. In a given cycle, the RSTB signal begins in the low-state, rises to the high-state, and then returns to the low-state. The duration of the signal in the low-state at the beginning of each cycle is the blanking duration. The slope signal generator  310  receives the RSTB signal and is further connected to a PWM comparator  306   a . Using the blanking duration, the RSTB signal resets the slope signal generator  310  at the beginning of each cycle. The slope signal generator  310  provides a slope signal I SLOPE  to the PWM network  305 . 
         [0025]    In the step-down converter, V IN  is connected to a switch network  301  comprising a pair of serially-connected switches Q 1  and Q 2 , which are further connected to the ground node GND. The phase node  308  between switches Q 1  and Q 2  is connected to the load network  302  via the inductor L. V OUT  measured across the load network  302  is provided to a feedback network  303 , which is connected between V OUT  and GND. The feedback network  303 , comprising a pair of serially-connected voltage dividing resistors R 1  and R 2 , is connected between V OUT  and GND. A feedback signal V FB  indicative of V OUT , taken from the node between resistors R 1  and R 2 , is provided to an error amplifier  304 . V FB  and a reference signal V REF  indicative of a target voltage of V OUT  are connected to the inverting input and the noninverting input of the error amplifier  304 , respectively. The error amplifier  304  produces an output signal V COMP , which is connected to and stabilized by a compensation network  305 . In this example, a Type II network formed by passive elements R 3 , C 1 , and C 2 , is used. The slope signal I SLOPE  generated by the slope signal generator  310 , V COMP , and a timing signal CLK 2 , are provided to a PWM network  306  to generate a DUTY signal. In this circuit, the PWM network  306  comprises a PWM comparator  306   a  and a reset-dominant latch  306   b . A voltage signal V SUM  corresponding to the slope signal I SLOPE  is provided. V COMP  and V SUM  are respectively provided to the inverting input and the noninverting input of a PWM comparator  306   a , whereby a RESET signal is produced. RESET signal and CLK 2  are respectively provided to the R and S inputs of the reset-dominant latch  306   b , whereby a DUTY signal is produced. DUTY is provided to a gate driver GD  307 , which produces an HS signal and an LS signals to control switches Q 1  and Q 2 , respectively, thereby modulating the power delivered to the load network  302 . 
         [0026]    The block diagram in  FIG. 4A  discloses a second embodiment of the present invention. This embodiment comprises a timing element-driven LEB network  309  connected to a current-mode step-down switching converter. According to this embodiment of the invention, a current sense network  401  detects the current through inductor L when the high-side switch Q 1  is turned “on”, and then feedbacks a current sense signal I SNS  to the PWM network to adjust the power modulation accordingly. Referring to  FIG. 4A , an input voltage V I N  is connected to a switch network  301 , which is further connected to a ground node GND. A phase node  308  in the switch network  301  is connected to a load network  302  via inductor L. The current sense network  401  connects to the V IN  node and the phase node  308  to generate the current sense signal I SNS . An output voltage V OUT  measured across the load network  302  is provided to a feedback network  303 , which generates a feedback signal V FB  indicative of the output voltage. The feedback signal V FB  and a reference signal V REF  indicative of a target voltage of V OUT  are provided to an error amplifier  304 . The error amplifier  304  produces an output signal V COMP , which is connected to and stabilized by a compensation network  305 . A timing element CLK 1  provides a constant frequency clock signal to the LEB network representing the desired switching frequency. The LEB network  309  provides to the current sense network an RSTB signal, which is used to reset the current sense signal I SNS  according to the frequency of CLK 1 . V COMP , I SNS , and a timing signal CLK 2  are provided to a PWM network  306 , which generates a DUTY signal. A gate driver GD  307  receives DUTY and generates one or more control signals to control the on/off duration of the switch network  301 , whereby the power delivered to the load network  302  is modulated. 
         [0027]    The circuit diagram in  FIG. 4B  shows a circuit according to the second embodiment of the present invention. The current mode converter is similar to the voltage mode converter described in  FIG. 3B  except for several key distinctions. First, the slope signal generator is replaced with a current sense network  401 . The current sense network  401  comprises a resistor R P , a comparator  401   a , and a switch Q 3 . V IN  is connected to a first end of R P , while the second end of R P  is connected to both the source terminal of switch Q 3  and to the inverting input of comparator  401   a . The output of the comparator  401   a  is provided to the gate terminal of switch Q 3 . The drain terminal generates and provides to the PWM comparator  306   a  a current sense signal I SNS  indicative of the inductor current. Second, the RSTB reset signal is provided to a node connected to the inverting input of the comparator  401   a  and the source of switch Q 3 . The RSTB signal resets I SNS  at a frequency determined by CLK 1 . 
         [0028]      FIG. 5A  discloses a third embodiment of the present invention, in which the LEB network is connected to a hybrid current mode step-down switching converter, which comprises both a current sense network  401  and a slope signal generator  310 . The slope signal I SLOPE  and the current sense signal I SNS  are provided to an adder  501  wherein both signals are summed to produce a sum signal I SLOPE+SNS . A voltage signal V SUM , which corresponds to I SLOPE+SNS , is provided to the inverting input of the PWM comparator  306   a  for comparison with V COMP . 
         [0029]    The circuit diagram in  FIG. 5B  shows a circuit according to the third embodiment of the present invention. This circuit combines elements from both the first and the second embodiments. 
         [0030]    First, the timing element CLK 1 , the LEB network, and the slope signal generator  310  are provided according to the configuration of  FIG. 3B  with the exception of the connection of between the slope signal generator  310  and the PWM comparator  306   a . The current signal I SLOPE  is provided to an adder  501 . 
         [0031]    Second, a current sense network is provided according to the configuration of  FIG. 4B . The input voltage V IN  is connected to the first end of R P , while the second end of R P  is connected to both the source terminal of switch Q 3  and to the inverting input of comparator  401   a . The output of the comparator  401   a  is provided to the gate terminal of switch Q 3 . The drain terminal generates and provides to the adder  501  a current sense signal I SNS  indicative of the inductor current. 
         [0032]    Third, the adder  501  combines the slope signal I SLOPE  with the current sense signal I SNS  to produce a sum signal I SLOPE+SNS , which is further converted into a corresponding voltage signal V SUM . The signal V SUM  is provided to the noninverting input of the PWM comparator  306   a , wherein V SUM  is compared with V COMP . The PWM comparator  306   a  provides a RESET signal to the R input of the reset-dominant latch  306   b  while a timing element provides a timing signal CLK 2  to the S input. The latch  306   b  generates and provides to the gate driver  307  a DUTY signal. The rest of the elements, including the switch network  301 , the load network  302 , the feedback network  303 , the error amplifier  304 , the compensation network  305 , and the gate driver GD  307  are configured in the same way as the circuits shown in  FIGS. 3B and 4B   
         [0033]    The above-described embodiments are only examples of the present invention, which is in essence to use an LEB network to reset the slope signal and/or the current sense signal at a preset frequency so that the switching frequency of the converter is maintained constant. Other embodiments of the present invention will be readily apparent to a person having ordinary skill in the art upon reading the above description. A non-exhaustive list of some other variations is described below. 
         [0034]    Each embodiment of the present invention may be modified to use a different configuration for the gate driver GD  307  and the switch network  301 . For instance, the low-side switch Q 2  may be replaced with a passive rectifier, such as a Schottky diode. Gate driver GD  307  would then provide only an HS signal to control the high-side switch Q 1 . Each embodiment may be further modified to use a set-dominant latch instead of a reset-dominant latch. Yet another variation of the embodiments is to synchronize CLK 1  and CLK 2  or replaces both timing elements with a single timing element so that the LEB network and the PWM network are synchronized and have the same frequency. 
         [0035]      FIG. 6  illustrates a number of waveforms associated with the operation of the step-down converters disclosed in the above paragraphs. The waveforms are merely intended to conceptually represent the type of response that can be expected from a system built according to the descriptions of the present invention; however, actual performance may vary. The waveforms shown are the signals for V IN , V OUT , V COMP , V SUM , RSTB, LEB, and CLK 1 . For better comparison with the prior art waveform shown in  FIG. 2 , the waveforms for V IN , V OUT , and V COMP  are kept the same. As shown, CLK 1  is preset to operate at a desired switching frequency F S1 . The LEB network  309 , the slope signal generator  310 , and/or the current sense network  401  are directly or indirectly driven by CLK 1  to operate at the same frequency (i.e., the desired switching frequency). Since V SUM  is the voltage corresponding to the signal I SLOPE , I SNS , Or I SLOPE+SNS , the periodic reset of the slope signal generator  310  also causes V SUM  to reset at the desired switching frequency F S1 . In Phase II of  FIG. 6 , the input-output differential falls below the threshold voltage at time t 2 , thereby causing V OUT  to drop below the target voltage. In response, V COMP  rises to compensate for the decrease. In contrast to the prior art scenario shown in  FIG. 2 , V SUM  in the present invention no longer relies on V COMP  for providing the ceiling signal to reset V SUM . Instead, V SUM  independently and continuously resets at the target switching frequency F S1  notwithstanding the input-output voltage differential temporarily falling below the threshold voltage. 
         [0036]    The present invention also describes methods for extending the maximum duty cycle of a step-down switching converter while maintaining a constant frequency using the above described embodiments. Corresponding to the voltage mode switching converter described in the first embodiment, the first method entails the following steps:
       STEP  1  providing an RSTB signal operating at a desired switching frequency;   STEP  2 A providing a slope signal I SLOPE ;   STEP  3 A periodically resetting the slope signal I SLOPE  at the desired switching frequency using the RSTB signal;   STEP  4  providing a switch network  301  configured to connect an input node having an input voltage V IN  to inductor L, which is further connected to an output node having an output voltage V OUT , the switch network  301  comprises (1) a high-side switch Q 1  connected between the input node and a phase node  308  having a phase node voltage, and (2) a low-side element connected between the phase node  308  and ground;   STEP  5  generating an error voltage V COMP  based on comparison of a feedback voltage V FB  signal indicative of the output voltage V OUT  with a reference voltage V REF ;   STEP  6 A generating a DUTY signal based on the error voltage V COMP , a sum signal V SUM  indicative of the slope signal I SLOPE , and a second clock signal CLK 2 ;   STEP  7  generating one or more control signals for controlling the switch network  301  based on the DUTY signal; and   STEP  8  modulating the power delivered from the input node to the output node by controlling the switch network  301  with the one or more control signals.       
 
         [0045]    According to the second embodiment of present invention, which described a current mode switching converter (see  FIG. 4A ), a current sense network  401  produces a signal indicative of the current through inductor L when the high-side switch Q 1  is turned on. The second embodiment uses the same method as the first embodiment with the exception of STEPs  2 A,  3 A, and  6 A, which are replaced with STEPs  2 B,  3 B, and  6 B, respectively:
       STEP  2 B providing a current sense signal I SNS  indicative of the current through inductor L when the high-side switch Q 1  is turned on;   STEP  3 B periodically resetting the current sense signal I SNS  at the desired switching frequency using the RSTB signal; and   STEP  6 B generating a DUTY signal based on V COMP , I SNS , and CLK 2 .       
 
         [0049]    The third embodiment of the present invention described a system wherein the switching converter includes both the slope generator  310  and the current network  401 . The method for the third embodiment uses the same steps as the method for the first embodiment, except for that STEP  2 A is replaced with  2 C-a and  2 C-b, and STEP  6 A is replaced with  6 C.
       STEP  2 C-a providing an I SNS  signal indicative of the current through inductor L when the high-side switch Q 1  is turned on;   STEP  2 C-b generating a signal V SUM  indicative of the sum of I SNS  and I SLOPE , directly or indirectly, by summing I SNS , and I SLOPE ; and   STEP  6 C generating a DUTY signal based on V COMP , V SUM , and CLK 2 .       
 
         [0053]    With respect to STEP  1 , the following steps describe one method for producing the RSTB signal.
       STEP  1 - a  providing a first clock signal CLK 1  having a desired switching frequency;   STEP  1 - b  inverting the first clock signal CLK 1  to generate an inverted first clock signal;   STEP  1 - c  delaying the first clock signal CLK 1  to generate a delayed first clock signal;   STEP  1 - d  inputting the inverted first clock signal and the delayed first clock signal into a NOR gate to generate an LEB signal; and   STEP  1 - e  inverting the LEB signal to generate the RSTB signal operating at the desired switching frequency.       
 
         [0059]    Various embodiments and variations of the present invention have been described. While the above descriptions of the various embodiments and variations of the present invention contain many details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of embodiments specific to particular embodiments of the invention. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments. In addition, the methods described herein do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain cases, the steps may also be performed simultaneously.