Abstract:
A smart capacitor includes a main capacitor having at least one intelligence mechanism selected from a prognostics mechanism and a high speed protection mechanism integrated within the main capacitor. The at least one intelligence mechanism and the main capacitor are together configured to generate at least one type of output signal selected from long term induced failure mechanism signals and sudden capacitor failure condition signals in response to desired input signals.

Description:
BACKGROUND 
     The invention relates generally to smart capacitors and more particularly to high energy density capacitors and a method for integrating one or both of prognostics and protection mechanisms into high energy density capacitors to implement smart capacitors without significantly impacting the energy density or performance. 
     Capacitors are traditionally the least reliable component in power electronic systems. Microscopic changes in the capacitor&#39;s dielectric material and conductor over its working life, induced by high voltage(s), high current transients (di/dt&#39;s), temperature, temperature cycling and humidity can lead to reduced performance and accelerate the time to failure and/or system failure to which the capacitor(s) is/are attached. High performance applications, such as military applications, can accelerate this process. Maintaining maximum operational capability of the system for most applications is highly desirable. 
     Providing prognostics and/or protection within a capacitor can reduce system failures and increase operational capabilities of the system(s) to which the capacitor is attached. Prognostics can be used to detect long term induced failure mechanisms and high speed protection can be used to protect the system in the event of a sudden capacitor failure caused by conditions that can lead to capacitor failure. 
     In view of the foregoing, it would be advantageous to provide a high energy density capacitor structure having prognostics and/or high speed protection mechanisms integrated therein, and a method for integrating one or both prognostics and high speed protection into high energy density capacitors without significantly impacting the energy density or performance. 
     BRIEF DESCRIPTION 
     Briefly, in accordance with one embodiment, a smart capacitor comprises: 
     a main capacitor; and 
     at least one intelligence mechanism selected from a reference capacitor prognostics mechanism and a high speed protection mechanism integrated within the high energy density capacitor, wherein the at least one intelligence mechanism and the main capacitor are together configured to generate at least one type of output signal selected from long term induced failure mechanism signals and sudden capacitor failure condition signals in response to desired input signals. 
    
    
     
       DRAWINGS 
       These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein: 
         FIG. 1  is a two-dimensional diagram illustrating an unrolled view of a capacitor structure according to one embodiment of the invention; 
         FIG. 2  is a three-dimensional view illustrating the unrolled capacitor structure depicted in  FIG. 1  when fully assembled; 
         FIG. 3  is a circuit diagram depicting an equivalent circuit corresponding to the fully assembled capacitor shown in  FIG. 2 ; 
         FIG. 4  is a circuit diagram illustrating a main capacitor and a corresponding sense capacitor combined with processing circuits to determine electrically induced aging effects of the main capacitor using the sense capacitor as a reference, according to one embodiment of the invention; and 
         FIG. 5  is a system block diagram illustrating main and back-up capacitor banks using a plurality of smart capacitors in a matrix interconnect system configuration, according to one embodiment of the invention. 
     
    
    
     While the above-identified drawing figures set forth alternative embodiments, other embodiments of the present invention are also contemplated, as noted in the discussion. In all cases, this disclosure presents illustrated embodiments of the present invention by way of representation and not limitation. Numerous other modifications and embodiments can be devised by those skilled in the art which fall within the scope and spirit of the principles of this invention. 
     DETAILED DESCRIPTION 
     Realizing that capacitor life and internal and external faults can be predicted and detected through measurements of capacitance degradation and loss factor, the present inventors recognized this function can be implemented according to one aspect by integrating a sense capacitor of the same type into a main capacitor and configuring the resultant capacitor such that the integrated sense capacitor is not subjected to any of the electrical stresses seen by the main capacitor. 
     It is noted that temperature and thermal cycling induced failure modes that are common to both the sense capacitor and the main capacitor can be detected by integrating a negative temperature coefficient (NTC) resistor or thermal couple into the main capacitor. It is also noted the sense capacitor can be designed with a capacitance value several orders of magnitude lower than the main capacitor and to share a common terminal with the main capacitor. 
     Looking now at  FIG. 1 , a two-dimensional diagram illustrates an unrolled layout view of a capacitor structure  10  according to one embodiment of the invention. The capacitor structure  10  includes a common terminal  12 , a main terminal  14 , and a sense terminal  16  comprising a solder pad  18 . The capacitor structure  10  further includes a first isolation zone  20  and a second isolation zone  22 . 
       FIG. 2  is a three-dimensional view illustrating a fully assembled capacitor  24  that employs the unrolled structure  10  depicted in  FIG. 1  to implement a main capacitor and a sense capacitor integrated therein. Capacitor  24  can be seen to include the common terminal  12 , main terminal  14 , and sense terminal  16  for providing external connection points for the corresponding main capacitor and sense capacitor. 
       FIG. 3  is a circuit diagram depicting an equivalent circuit corresponding to the fully assembled capacitor  24  shown in  FIG. 2 . The equivalent circuit shows that fully assembled capacitor  24  comprises both a main capacitor  30  connected to both the common terminal  12  and the main terminal  14 , and a sense capacitor  40  connected to both the common terminal  12  and the sense terminal  16 . According to some embodiments, the sense capacitor  40  can be integrated into the same layers comprising the main capacitor  30 , or alternatively can be disposed between the main capacitor layers and made porous with respect to the main capacitor  30 . 
     According to one aspect, low magnitude, high frequency signals can be injected into both the main capacitor  30  and the sense capacitor  40 . Any differences between measured feedback signals via integrated prognostic electronics will reflect the degradation, if any, of the main capacitor  30 . Such integrated prognostic electronics can derive its power by, for example, scavenging power from the main capacitor, or for example, by the corresponding system that employs the capacitor  24  through a signal cable such as depicted in  FIG. 5 , described in detail below. Further, external faults may be detected using the same circuits simply by detecting abnormal current transients (di/dt&#39;s) that do not coincide with trigger signals to the system. 
     The present inventors recognized that a sense capacitor of the same type can be integrated into the main capacitor that is not subjected to any electrical stresses of the main capacitor and employed in combination with prognostics and/or high speed protection mechanisms integrated therein to predict and detect capacitor life and internal and external capacitor faults through measurements of degradation of the corresponding capacitance and loss factor. 
       FIG. 4  illustrates a smart capacitor assembly  50  including a main capacitor  30  and a corresponding sense capacitor  40  combined with processing circuits  42 ,  44  to determine electrically induced aging effects of the main capacitor  30  using the sense capacitor  40  as a reference, according to one embodiment of the invention. According to one aspect, the sense capacitor  40  has a capacitance value several orders of magnitude (at least three) lower than the main capacitor  30  and shares a common terminal  12  with the main capacitor  30 . 
     According to one aspect, low magnitude, high frequency signals are injected into the sense capacitor  40  via terminals  12 ,  16  and into the main capacitor  30  via terminals  12 ,  14 . Feedback signals are measured at corresponding processing circuit output terminals  46 ,  48 . The difference between the respective feedback signals generated via corresponding processing circuits  42 ,  44  reflects the degradation of the main capacitor  30 . The processing (prognostic) electronics  42 ,  44  can derive the requisite power by any suitable means, including without limitation, by either scavenging from the main capacitor  30 , or provided by the corresponding system through respective signal cables, as stated above. It is noted that external faults can be detected using the same processing circuits  42 ,  44  by detecting abnormal di/dt&#39;s that do not coincide with trigger signals to the corresponding system that employs the smart capacitor  50 . 
     The prognostics mechanism signal processing circuits  42 ,  44  are configured according to one embodiment to provide capacitor information selected from capacitance value, loss tangent, and changes in capacitor characteristics with respect to time. Embodied processing circuits  42 ,  44  can be seen to include corresponding DC blocking capacitors  32 ,  34 . These DC blocking capacitors  32 ,  34  are each connected in series with a corresponding detuning inductor  36 ,  38  that is configured to detune the voltage blocking capacitor effects at a desired sense frequency and enhance measurement accuracy. 
       FIG. 5  is a protection system  100  block diagram illustrating main and back-up capacitor banks using a plurality of main capacitors  30  and back-up capacitors  60  in a matrix interconnect system configuration, according to one embodiment of the invention. The protection system  100  can disconnect the defective capacitor(s)  30  and connect a back up capacitor(s)  60  in place of the defective capacitor(s)  30 . 
     The protection system  100  circuits can be integrated into the main capacitor(s)  30  and the back-up capacitor(s)  60  using high temperature active power switches such as, but not limited to, normally-off type SiC MOSFETs  64  connected to the back-up capacitor(s)  60  and normally-on type SiC JFETs  62  connected to the main capacitor(s)  30 . Upon detection of end of life and/or internal and external faults, the faulty capacitor(s)  30  can be disconnected by turning off its corresponding SiC JFET  62  and by connecting a back-up capacitor  60  by turning on its corresponding SiC MOSFET  64 . 
     The SiC switches  62 ,  64  can be integrated with the main and back-up capacitors  30 ,  60 , as stated above. This integrated structure maximizes modularity, adaptability and recoverability of capacitors for different applications by allowing the main and back-up capacitors  30 ,  60  to operate in a reconfigurable matrix format. 
     According to one embodiment, the integrated fault isolation active power electronics can be implemented as a planar disk with the contact area being identical to the main capacitor  30  terminal  14  as seen in  FIG. 2 . The resultant planarity and low profile of the fault isolation power electronics will also aid thermal management of both the capacitor(s)  30 ,  60  and the corresponding integrated circuits. Power for the control electronics can be provided, without limitation, by scavenging from energy stored in the corresponding capacitor(s)  30 ,  60 , or provided by the system that employs the protection system  100  through an error signal. It is noted that the choice of a JFET will enable the protection system  100  to function with reduced capability in the event of loss of supply power. 
     In summary explanation, embodiments of smart capacitors and systems that employ smart capacitors have been described herein. These smart capacitors can employ one or both prognostics and protection circuits integrated therein to measure and detect aging effects of the capacitors during operation and to provide system protection against sudden capacitor failures. According to one aspect, the protection circuits are integrated into a main capacitor terminal. A sense capacitor integrated inside the main capacitor operates in combination with the prognostic circuits to provide capacitance and loss factor information. 
     While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.