Abstract:
Metalization structures are modeled by employing automatic substrate grounding and shielding generation in conjunction with a design and simulation process for modeling the charge distributions and the interactions of these charge distributions on metalization structures arising from voltages and currents flowing in metalization structures. By generating and, then, employing a grounding structure that is optimized to strongly screen the metalization structure being designed and simulated, the requirement is eliminated for the accurate incorporation of the strongly dependent long range metalization sub unit to sub unit charge distribution coupling from the charge distribution determination process. In one embodiment of the invention, representative metalization sub units are selected, such as straight sections of infinitesimal length, right angle bends and intersections. Charge distributions are determined in those representative sub units based on the assumption that the integrated circuit substrate strongly suppresses any long range circuit interactions or frequency dependent effects. Then, based on the above assumption, self and mutual interactions are determined of the metalization sub units. Further, based on determined characteristics of those sub units, substrate grounding structures are determined and constructed that ensure the validity of the simulation assumption that the substrate grounding is adequate to strongly suppress any long range circuit interactions and/or frequency dependent effects. The determined self and mutual interactions can then be used as initial solutions to describe all interactions between similar metalization sub units in the overall physical metalization structure to be fabricated.

Description:
RELATED APPLICATIONS 
     U.S. patent applications Ser. Nos. 09/283,392, 09/283,393 and 09/283,394 were filed concurrently herewith. 
    
    
     TECHNICAL FIELD 
     This invention is related to the design of optimized metalization structures and, more particularly, to modeling of electromagnetic interactions in electrical circuit metalizations to simulate the electrical properties of metalization structures in integrated circuits from their physical characteristics and using those electrical properties to obtain improved metalization performance. 
     BACKGROUND OF THE INVENTION 
     It is desirable to be able to model quickly and accurately the electrical characteristics of metalization structures, such as inductors, interconnects and the like. It is also desirable to generate metalization structures that minimize the flow of unwanted signals between circuit nodes. Determination of these electrical characteristics requires a detailed solution of the charge density everywhere in the metalization structure combined with an understanding of the extent to which time dependent variations in the charge density will generate unwanted variations in the charge density elsewhere. Because of very rapid three (3) dimensional variation in charge density with position in known metalization structures and because these variations strongly affect the electrical characteristics of the metalizations and because the variations can arise from variations in distant metalization structures, an accurate and fast method for determining those charge distributions and the interactions between those charge distributions is required in order to properly determine the electrical properties of, for example, inductors or other systems of metals. One family of techniques that has been used for this purpose, employs a uniform or variable three (3) dimensional mesh of the entire metalization structure and assumes that the charge distribution will be strongly determined by interactions with adjacent metalization structures at all distances. However, these so-called long range solvers are very inefficient, i.e., slow, when employed in an attempt to model metalization structures that are largely planar as in integrated circuit metalization structures and that are strongly shielded from distant structures. Another family of techniques employs so-called short range solvers that are faster than the long range solvers, but do not account for long range interactions that may be important and, therefore, these short range solvers yield inaccurate results. 
     SUMMARY OF THE INVENTION 
     These and other problems and limitations of prior known modeling arrangements and methods are overcome by employing automatic substrate grounding and shielding generation in conjunction with a design and simulation process for modeling the charge distributions and the interactions of these charge distributions on metalization structures arising from voltages and currents flowing in metalization structures. By generating and, then, employing a grounding structure that is optimized to strongly screen the metalization structure being designed and simulated, the requirement is eliminated for the accurate incorporation of the strongly dependent long range metalization sub unit to sub unit charge distribution coupling from the charge distribution determination process. 
     In one embodiment of the invention, representative metalization sub units are selected, such as straight sections of infinitesimal length, right angle bends and intersections. Charge distributions are determined in those representative sub units based on the assumption that the integrated circuit substrate strongly suppresses any long range circuit interactions or frequency dependent effects. Then, based on the above assumption, self and mutual interactions are determined of the metalization sub units. Further, based on determined characteristics of those sub units, substrate grounding structures are determined and constructed that ensure the validity of the simulation assumption that the substrate grounding is adequate to strongly suppress any long range circuit interactions and/or frequency dependent effects. The determined self and mutual interactions can then be used as initial solutions to describe all interactions between similar metalization sub units in the overall physical metalization structure to be fabricated. 
     Technical advantages arising from use of applicant&#39;s unique shielding arrangement are a significant reduction in the time required to obtain simulation results for modeling the metalization structures, while still maintaining a very acceptable accuracy of results, and the ability to perform the simulation process concurrently with the process of modeling the grounding structure that provides the substrate shielding. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     FIG. 1A shows, in simplified form, a cross section of a circuit metals structure fabricated on a substrate without grounding structures and the lines of coupling to adjacent circuit elements; 
     FIG. 1B shows, in simplified form, a cross section of a circuit metals structure fabricated on a substrate with grounding structures and the absence of lines of coupling to adjacent circuit elements; 
     FIGS. 2A through 2C show, in simplified form, an inductor to be fabricated from circuit metalizations, as well as, the cross section of the metalization paths in the inductor; 
     FIG. 3 is a graphical representation illustrating test elements relative to lines of charge/current in a section of the inductor of FIG. 2; 
     FIG. 4 shows, in simplified form, simulation apparatus including an embodiment of the invention; 
     FIG. 5 shows, in simplified block diagram form, details of the apparatus of FIG. 4; and 
     FIG. 6 is a flowchart illustrating steps in one embodiment of a simulation process including an embodiment of the invention. 
    
    
     DETAILED DESCRIPTION 
     FIG. 1A shows, in simplified form, a cross section of a prior art circuit metals structure fabricated on a substrate without grounding structures and the lines of coupling to adjacent circuit elements. Shown is the so-called standard approach that does not use substrate shielding to shunt the currents to ground potential. Specifically, shown are substrate  101  without shielding, its parasitic capacitances  102  and currents  103  generated by the unshielded fields arising from the metalization structure finding ground potential through substrate  101 . Note that in addition to currents  103  flowing downward through substrate  101  there are similar currents (not shown) flowing upward from substrate  101 . Use of this prior so-called standard approach requires a significantly longer time to solve for a desired metalization structure to be fabricated, than by using applicant&#39;s unique invention, because of the currents and fields flowing to ground potential through substrate  101  interact strongly with adjacent metalization sub units. 
     FIG. 1B shows, in simplified form, a cross section of a circuit metals structure fabricated on a substrate with grounding structures and the absence of lines of coupling to adjacent circuit elements. Shown is the so-called shielding approach of applicant&#39;s unique invention that does use substrate shielding to shunt the currents to ground potential, and which establishes a so-called counter charge under the metalization structure. This counter charge is identical to but opposite in sign to the metalization structure&#39;s voltage induced charge. Consequently, the counter charge cancels the strong interaction with distant metalization sub units caused by the voltage induced charge. Specifically, shown are substrate  101  with substrate shield  104 , its parasitic capacitances  102  and currents  105  finding ground potential through shielding  104 . Use of applicant&#39;s unique shielding approach yielding a quicker and more accurate approach to simulating a physical metalization structure to be fabricated. 
     FIGS. 2A through 2C show, in simplified form, an inductor  200  to be fabricated from circuit metalizations, as well as, the cross section of the metalization paths in the inductor. FIG. 2A shows three (3) sub units  1 ,  2  and  3  of an integrated circuit inductor as shown in FIGS. 2B and 2C. The uppermost metal  201  in each of the sub units is 3 um thick, while the lower metals  202  and  203  are each 0.5 um thick. The sub units  1 ,  2  and  3  form a portion of the overall integrated circuit inductor  200 , which is fabricated on substrate  204 . FIGS. 2B and 2C graphically illustrate overall inductor  200  including the representative sub units  1 ,  2  and  3 . Note the high-lighted portions illustrating sub units  1 ,  2  and  3  in FIGS. 2B and 2C, and that the sub units have been partitioned into smaller sub elements as indicated, for example, by the cross hatching in sub unit  3 . 
     FIG. 3 is a graphical representation illustrating test elements relative to lines of charge/current in a section of the inductor of FIG.  2 . Shown are test elements  301 , which are in parallel alignment relative the lines of current/charge  302  on a sub unit of inductor  100 . Specifically, test elements  301  are in solid outline and delineated at each end solid by a dot, and the lines of charge/current  302  are in dotted outline. In FIG. 3, the test elements  301  and lines of charge/current  302  are shown relative to the groups of sub units  1 ,  2  and  3  of inductor  100 . 
     FIG. 4 shows, in simplified form, simulation apparatus including an embodiment of the invention. Thus, shown is computer system  400  which may be, for example, a workstation of a type well known in the art, including a central processor, system memory, hard disk and the like (not shown) but housed in cabinet  401 . Also included are monitor  402 , display unit  403 , keyboard  404  and pointing device, i.e., mouse  405 . Cabinet  401  also houses a CD-ROM drive  406 . The hard disk and system memory are employed in well known fashion to store and retrieve software programs incorporating code for effecting an embodiment of the invention. Additionally, cabinet  401  may also house a floppy disk drive (not shown). 
     FIG. 5 shows, in simplified block diagram form, details of the apparatus of FIG.  4 . Thus, shown is computer system  400  including monitor  402  including display unit  403 , display adapter  414 , keyboard  404 , mouse  405 , central processor  407 , system memory  408 , removable disk drive  409 , hard disk drive  410 , I/O controller  411  and speaker  412  all interconnected via bus  413 . Indeed, FIG. 5 illustrates but one arrangement for implementing an embodiment of the invention and other similar arrangements may be employed to equally practice one or more embodiments of the invention. 
     FIG. 6 is a flowchart illustrating steps in one embodiment of a simulation process including an embodiment of the invention. In this embodiment, the flowchart of FIG. 6 when employed in the simulation apparatus of FIGS. 4 and 5 effects a process and apparatus for modeling metalization structures on substrates by employing substrate grounding and shielding in conjunction with the simulation of charge distributions and interactions on metalization structures. 
     At this time it is believed that a discussion of the theory of applicant&#39;s unique modeling and simulation process is in order. In what follows, test elements are used which are smaller than the charge carrying elements; however, this is not generally required. The field or potential on each of the test elements arising from the charge on the longer elements is determined by the sum of two components. The first component, the self induced potential of a sub unit element of radius ρ whose endpoints are offset by the distances x a,b =x i,a −x j,b  in the direction parallel to their lengths is determined by:                      Φ                   s     i   ,   j         =                  1     2                 π                 ɛ              ∑     a   =     -   1       1            ∑     b   =     -   1       1              (     -   1     )       1   +   b       ·                                      [             (       ρ   2     +     x     i   ,   j         )       3   /   2       +            x     i   ,   j            3         3                   ρ   2         +              x     i   ,   j            2     ·     log        (       2   ·     x     i   ,   j         ρ     )           ]     ,                   (   1   )                                
     where the origin of the coordinate system has been chosen such that            ∑     a   ,     b   =     ±   1                x     a   ,   b         =   0.                          
     The second component, arising from the coupling of test elements to adjacent lines of charge or the charge images that are separated from the test element can be determined by:                  φ     i   ,   j       =       1     4                 π                 ɛ              ∫   0   i            ∫   0   j            [       1              r   _     i     -       r   _     j              -     1              r   _     i     -       r   _     j     -     2      z                   z   ⋒                  ]                 _            l   _     i       ·          _            l   _     j                   ,           (   2   )                                
     where {overscore (r)} is the location of the observation point, {overscore (r)} j  is the location of the source and z is the height of the source. In Equation 2, the second term in the brackets enforces the condition of infinite substrate conductivity. Although Equation 2 is useful, in our simulation a closed form expression is used for the interactions between straight elements. 
     In order to determine the complex admittance matrix for the metalization structure, the potentials are described in the form:                φ   j     =         (       φ                   s     i   ,   j         +     φ                   sb     i   ,   j           )          q   j       +       ∑     i   ≠   j                q   i          (       φ                   ρ     i   ,   j         +     φ                 n                   ρ     i   ,   j         +     φ                   sb     i   ,   j           )       .                 (   3   )                                
     If all sub units in a prescribed group of sub units are solved simultaneously, Equation 3 will run over all charge elements in the three sub units. If the sub units are solved independently Equation 3 need not include terms from more than one sub unit as it is being solved. 
     The φ j  are generally the same for all parallel test elements. It is often necessary to find the physical characteristics of the sub units in the external electric potential arising from the charges in other sub units. These external potentials are of the form:                  Φ        (     x   0     )       +           ∂   Φ       ∂   x       ·   2                       (     x   -     x   0       )     ws       +           ∂   2        Φ       ∂     x   2         ·     (       6                       (     x   -     x   0       )     2       ws   2         -     1   2       )       +   …                ,           (   4   )                                
     where x is taken to be along the line which intersects the end of each of the parallel test elements, x 0  is at the center of the sub unit, ws is the width of a particular sub unit and adjustments are made to the magnitudes of the potential Φ and its derivatives. It should be noted that there can be significant variation in magnitude of the charge along the length of the metalization sub unit, consequently, additional terms can be added to Equation 4 to account for these variations. Note, however, that these variations tend to be limited by the screening effects of the substrate. 
     In structures such as the inductor shown in FIGS. 2B and 2C, the sub unit in each turn can be excited with a voltage independently, the three sub units can be solved for each excitation, and the sub unit charge distribution and electrical properties can then be determined as a function of their self and adjacent turn voltages. 
     For structures lacking the symmetry of the structure in FIGS. 2B and 2C, it is often desirable to solve Equations 3 and 4 independently for each significant term in the electric potential expansion (Equation 3) so that the dependence of the sub unit charge distribution and, therefore, its electrical properties on the potential or its derivatives can be quantified. Then, in the determination of the overall metalization structure, the effects of the field dependence of a sub unit charge distribution will be accurately represented as it responds to the potential variations generated by the charge distributions in other system sub units. 
     Because the sub units are small compared to the wavelength of the electrical signal, voltages of the elements in and connected to the sub units is roughly constant so that the whole structure can be assigned a constant voltage during its determination. This constraint is implemented for sub units being excited through requiring that: 
     
       
         φ i =1.  (5) 
       
     
     For sub units that are not being excited, the constraint is: 
     
       
         φ i =0.  (6) 
       
     
     As described above, the simultaneous solution of Equations 1 through 6 allows the field dependent charge distribution of the sub unit to be obtained. 
     In order to determine the characteristics of the sub unit, the charge distribution on the sub unit is used, as well as, the difference between the sub unit voltage φ i  on the left of Equation 3 and that of adjacent structures. The complex in field sub unit admittance is determined by the total sub unit charge divided by the sub unit voltage, namely:                  Y                   ρ     i   ,   j         =       qtot   i       φ   j         ,           (   7   )                                
     where qtot i  is the sum of the charge on the region of the charge carrying elements spanned by the test elements. 
     The mutual interactions between two sub units, for example, A and B, can be determined through:                  C     A   ,   B       =       ∑   i            ∑   j            (       φ                   ρ     i   ,   j         +     φ                 n                   ρ     i   ,   j         +     φ                   sb     i   ,   j           )            q     A   ,   i       ·     q     B   ,   j                 ,           (   8   )                                
     where the q A,i  and the q B,j  are the charges on the A th  and B th  sub units, respectively. 
     A more efficient manner for the determining and expressing the mutual interactions between sub units is through multipole decomposition. In this process, the charge distributions on the sub units are decomposed into mathematically orthogonal distribution functions that efficiently capture the differing properties of the components of the charge distributions. These charge distribution functions generate potentials whose spatial dependence is stored in a look up table, and these spatial dependent potentials can then be used to determine the couplings of the adjacent sub units. Following this procedure, the most convenient charge distribution functions are            f   n     =   1     ,   x   ,         3        x   2       2     -     1   /   2       ,   …                          
     The magnitude of the component a′ n  of each of the ƒ n  in a sub unit charge distribution is:                  a   n   ′     =           2      n     +   1     N            ∑     i   =   0       N   -   1                f   n          (         2      i     -   N   +   1       N   -   1       )       ·     q   i             ,           (   9   )                                
     where a′ n  then represents the component of the function ƒ n  in the sub unit charge distribution. The potential generated by a′ n  is given by:                  Φ        (       ρ   /   w     ,   θ     )       =       N     4                 π                 ɛ                 w       ·       ∫     -   1     1                         a   n   ′          f   n             x           (       ρ   2     +     2                 ρ                 x                 cos                 θ     +     x   2       )       1   /   2               ,           (   10   )                                
     where w is the width of the sub units, ρ is the distance to the center of the distribution being represented and θ is the angle between the charge flow and line between the point current source and observation points. Because these potentials also determine the mutual admittances between sub units, these solutions permit the full determination of the parallel admittances of the overall metalization structure. 
     A method for determining the variation of the sub unit self and mutual electrical properties that arise from variations in sub unit length is to decompose a sub unit of perturbed length into the sum of the original sub unit plus a short physical extension to the sub unit. The self and mutual electrical characteristics of the sub unit extension can be determined through substitution of the previously determined sub unit charge distribution (found through Equation 3) into Equations 5 to 7 that describe the self and mutual interactions between charge elements that represent the sub unit extension. 
     The parallel metalization self and mutual admittances of the overall metalization structure are determined through the suitable combination of the representative sub units to form the larger structure and the tabulation of their characteristics and interactions when assembled into the larger structure in the following form:                  I     j   -   1       -     I   j       =         V   j        Y                   ρ   j       +     2                 π                 if          ∑     i   ≠   j              (       V   j     -     V   i       )            C     i   ,   j       .                     (   11   )                                
     In Equation 11, I j−1 −I j  represents currents that are derived from the series paths through parallel impedances. In Equation 11, the Yρ j , describing the capacitive and resistive admittances to a grounded substrate are much more important than the C i,j , that describe inter sub unit capacitances that describe the inter sub unit capacitances          C     i   ,   j       =       ∑   n              Φ   n          (       ρ   /   w     ,   θ     )       .                              
     The parallel admittances of Equation 11 are then solved for the two (2) port frequency dependent network admittances. 
     By way of an example, the parasitic admittances and the substrate grounding structures are determined, as described below. In general, impedance Z is given by: 
     
       
           Z=R−i′X   C   (12) 
       
     
     and 
     
       
         | Z|={square root over (R 2   +X   C   2 +L )},   (13) 
       
     
     where          X   C     =     1     2                 π                 fC                              
     and for complete screening X C &gt;&gt;R, 1/Z is the complex admittance and          1     Y                 ρ       =       X   C     .                            
     Consequently,                   Z        ⇒       X   C            1   +       R   2       2        X   C   2                           and             (   14   )                                
     the screening level (SL) is              SL   =           i   ′          X   C             i   ′          X   C       +   R       ⇒     1   +           i   ′        R       X   C       .                 (   15   )                                
     Then, the resistance is set to a maximum value to determine the necessary simulation accuracy, for example, for 90% screening. Consequently,          R     X   C       =   0.1                          
     and             Z        ≈       X   C          (     1   +       R   2       2        X   C   2           )                              
     and, therefore, in this example, a ΔZ value to be added is            R   2       2        X   C   2         =     0.5        %   .                              
     In turn, this yields            Δ                 C     ≈     -       R   2       2        X   C   2             =       -   0.5          %   .                              
     Thereafter, a resistance of        R   =       X   C     10                            
     is added to the sub unit to substrate admittance found above and capacitance is reduced by 0.5% on the sub unit to substrate admittance. Then, the substrate contact area or poly-silicon area is generated by:                R   =         X   C     10     =       (       R   substrate       π                   ln   i         )            log   e          (       π                 Δ                 x       2        a   f         )             ,           (   16   )                                
     where Δx is the separation from the center of a sub unit to the center of a ground structure, R substrate  is the substrate resistivity, and a ƒ  is the average area of the sub unit and the substrate area. Then, a ƒ  is determined as follows:                a   f     =         πΔ                 x     2                            (         -     X   C          π                   ln   i         10                   R   substrate         )       .               (   17   )                                
     Note that in one example, a ƒ  is set for the worst case but the results are typically better than the worst case. 
     Indeed, then a new value for the parasitic admittance is determined by Yρ j  of Equation 11. It should be noted that C i,j  of Equation 11 is corrected in similar fashion as Yρ. 
     Alternatively, a grounded poly silicon shield may be fabricated under the metalization structure to provide a very high conductivity layer. In one example, the poly silicon shield is in the shape of a “snow flake” that assures the desired high conductivity. 
     It should be noted that for each sub unit admittance there typically would be a corresponding substrate admittance and also a corresponding complex admittance. Consequently, one or more sub unit admittances and one or more corresponding substrate admittances may be employed in determining one or more complex admittances. Therefore, at least one (complex) admittance could be one or more (complex) admittances, i.e., just one (complex) admittance or a plurality of (complex) admittances. 
     Returning to the flow chart of FIG. 6, the process is started in step  601 , where the physical description is inputted of the metal structure that is to be fabricated on the conductive substrate. Step  602  causes the inputted metal structure to be decomposed into metalization structure sub units. In step  603  the sub units are decomposed into sets of much smaller sized sub unit elements. Step  604  assumes that the substrate has infinite, i.e., complete, conductivity. In step  605 , the static charge distributions of selected sets of elements, i.e., sub elements, is determined. This is realized by employing Equations 1 and 3 through 6. Thereafter, step  606  determines the overall metalization structure charge distribution. This is realized by employing Equations 3 through 6. Step  607  statically determines the sub unit admittances by employing Equations 7, 8 and 10. Then, in step  608  the substrate admittance is determined, as described via the example given above. Step  609  causes the sub unit and substrate admittances to be combined, also as described in the example given above. The parasitic admittance information is supplied as an output via step  610 . Step  611  causes the substrate grounding, i.e., screening, structures to be generated. This is also described in the above example and, specifically, by Equations 16 and 17. Then step  612  generates the substrate structure, which is supplied as an output via step  613 . 
     The above-described methods and apparatus are, of course, merely illustrative of the principles of the invention. Indeed, numerous other methods or apparatus may be devised by those skilled in the art without departing from the spirit and scope of the invention.