Abstract:
An address conversion circuit is disclosed for converting a logical address to a physical address and outputting the physical address to a memory, the memory including a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory. The address conversion circuit includes: an address conversion section for converting the logical address to a first physical address in the normal memory array and outputting the first physical address; a defective address storing section for storing the defective address corresponding to the defective memory cell in the memory; and a redundancy decision circuit for, in response to a decision that the first physical address matches the defective address, replacing the first physical address with a second physical address corresponding to the redundant address and sending the second physical address to the memory.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an address conversion circuit and an address conversion system. More particularly, the present invention relates to an address conversion circuit and an address conversion system for use with a memory which is provided with a redundant memory array for relieving defective memory cells so as to facilitate ensuring memory capacity. 
     2. Description of the Related Art 
     FIG. 6 illustrates a conventional address conversion system. The address conversion system includes a CPU  3 , a memory control circuit  110  connected to the CPU  3 , and a plurality of memories  102  connected to the memory control circuit  110 . 
     Memory is sold typically with a particular capacity (eg. 40 MB). This capacity is ensured, meaning that even if some memory cells are defective, the memory will still provide the designated capacity. 
     Each memory  102  includes a normal memory array (not shown) having a capacity corresponding to the total capacity of the memory  102 . 
     The memory  102  of the conventional address conversion system includes, in addition to the normal memory array, a redundant memory array (not shown) and a redundancy decision circuit  103  for ensuring the total capacity of the memory  102  even when the normal memory array includes a defective memory cell (not shown). When the defective memory cell is to be accessed, the redundancy decision circuit  103  replaces a physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in the redundant memory array. 
     FIG. 7 illustrates the memory  102  and the memory control circuit  110  of the conventional address conversion system in greater detail. For sake of simplicity, only one memory  102  is shown in FIG.  7 . The memory control circuit  110  includes an address conversion section  101 . The redundancy decision circuit  103  in the memory  102  includes a comparison circuit  102 A and a defective address storing section  102 B. 
     The address conversion circuit  101  converts a logical address received from the CPU  3  to a physical address corresponding to a memory cell in the memory  102 . The comparison circuit  102 A compares the physical address received from the address conversion circuit  101  with a defective address stored in the defective address storing section  102 B. 
     When the physical address received from the address conversion circuit  101  matches the defective address, the memory cell to be accessed is a defective memory cell. In such a case, the redundancy decision circuit  103  replaces the physical address received from the address conversion circuit  101  by a redundant address corresponding to a memory cell in the redundant memory array and accesses the memory cell in the redundant memory array instead of the defective memory cell. 
     When the physical address received from the address conversion circuit  101  does not match the defective address, the memory cell to be accessed is a normal memory cell. In such a case, the redundancy decision circuit  103  accesses the memory cell in the normal memory array corresponding to the physical address received from the address conversion circuit  101 . 
     As described above, the conventional address conversion system includes the redundancy decision circuit  103  in each memory  102  so that the redundancy decision is made within the memory  102  for ensuring the total capacity of the memories  102  even when a defective memory cell exists. In such an address conversion system, however, the access speed to the memory decreases for the reason described below. 
     FIG. 8A illustrates a first processing method used in a memory access operation by the conventional address conversion system. FIG. 8B illustrates a second processing method used in a memory access operation by the conventional address conversion system. 
     Referring to FIG. 8A, in the first processing method, the redundancy decision circuit  103  first performs a process P 1  (over a time period T 1 ) for determining whether a physical address received from the address conversion circuit  101  matches a defective address stored in the defective address storing section  102 B and, if there is a match, replacing the physical address with a redundant address. Subsequent to the process P 1 , a process P 2  (over a time period T 2 ) is performed for accessing a memory cell corresponding to either the physical address from the address conversion circuit  101  (a normal address) or the redundant address by which the physical address from the address conversion circuit  101  is replaced. 
     Referring to FIG. 8B, in the second processing method, the process P 1  is performed as described above while performing, in parallel with the process P 1 , a process P 3  (over a time period T 3 ) for making an access to a certain point in an access path to the memory cell corresponding to the normal address. 
     Subsequent to the process P 1 , if the redundancy decision circuit  103  in the memory  102  determines that the physical address received from the address conversion circuit  101  matches the defective address, a process P 4  (over the time period T 2 ) is performed to access the memory cell corresponding to the redundant address with which the physical address from the address conversion circuit  101  is replaced. 
     If the redundancy decision circuit  103  determines that the physical address received from the address conversion circuit  101  does not match the defective address, the redundancy decision circuit  103  does not have to perform the address replacement process. In such a case, after a wait time T 5  (=T 1 −T 3 ), a process P 6  (over a time period T 6 =T 2 −T 3 ) is performed to complete access to the normal address part of which has been made during the process P 3 . 
     In either the first processing method or the second processing method, the accessing time (a time period from the time when the memory  102  receives a physical address to the time when the addressed data is accessed and output) necessarily includes the time period T 1  (for the redundancy decision circuit  103  to determine whether the physical address received from the address conversion circuit  101  matches a defective address and, if there is a match, replace the physical address by a redundant address). 
     Conventionally, in order to meet the demand to design a memory such that the memory independently ensures the total capacity thereof, the redundancy decision circuit  103  has been provided in the memory  102 . As a result, the time period T 1  (for determining whether the physical address received from the address conversion circuit  101  matches a defective address and, if there is a match, replacing the physical address by a redundant address) has been consumed by the memory  102 . This is disadvantageous, however, in terms of reducing the time required by the address conversion system to access the memory  102 . 
     SUMMARY OF THE INVENTION 
     According to one aspect of this invention, an address conversion circuit is provided for converting a logical address to a physical address and outputting the physical address to a memory, the memory including a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory. The address conversion circuit includes: an address conversion section for converting the logical address to a first physical address in the normal memory array and outputting the first physical address; a defective address storing section for storing the defective address corresponding to the defective memory cell in the memory; and a redundancy decision circuit for, in response to a decision that the first physical address matches the defective address, replacing the first physical address with a second physical address corresponding to the redundant address and sending the second physical address to the memory. 
     In one embodiment of the invention, the redundancy decision circuit includes: a comparison section for comparing the first physical address output from the address conversion section with a defective address stored in the defective address storing section and outputting a comparison result; a replacement section for replacing the first physical address in the normal memory array by the second physical address corresponding to the redundant address; and a selector for selectively outputting to the memory one of the first and second physical addresses based on the comparison result. 
     In one embodiment of the invention, the redundancy decision circuit includes a mode signal output section for outputting a mode signal to the memory based on the comparison result. 
     According to another aspect of this invention, an address conversion system includes: a CPU for outputting a logical address; an address conversion circuit for receiving the logical address, converting the logical address to a physical address and outputting the physical address; and a memory for receiving the physical address and accessing a memory cell corresponding to the physical address. The memory includes a normal memory array and a redundant memory array wherein a defective address corresponding to a defective memory cell in the normal memory array is replaced by a redundant address in the redundant memory array so as to ensure total memory capacity of the memory. The address conversion circuit includes: an address conversion section for converting the logical address to a first physical address in the normal memory array and outputting the first physical address; a defective address storing section for storing the defective address corresponding to the defective memory cell in the memory; and a redundancy decision circuit for, in response to a decision that the first physical address matches the defective address, replacing the first physical address by a second physical address corresponding to the redundant address and sending the second physical address to the memory. 
     In one embodiment of the invention, the redundancy decision circuit includes: a comparison section for comparing the first physical address output from the address conversion section with a defective address stored in the defective address storing section and outputting a comparison result; a replacement section for replacing the first physical address in the normal memory array by the second physical address corresponding to the redundant address; and a selector for selectively outputting to the memory one of the first and second physical addresses based on the comparison result. 
     In one embodiment of the invention, the address conversion circuit further includes a mode signal output section for outputting a mode signal to the memory based on the comparison result. 
     In one embodiment of the invention, the memory includes a plurality of memory chips. 
     When a defective memory cell is to be accessed, the address conversion circuit of the present invention replaces the physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in a redundant memory array, and outputs the redundant address to the memory. 
     Thus, when using the address conversion circuit of the present invention, the time period consumed for determining whether a received physical address matches a defective address and, if there is a match, replacing the physical address by a redundant address is not included in the accessing time (a time period from the time when the memory receives a physical address to the time when the addressed data is accessed and output). 
     As a result, it is possible to reduce the time required to access the memory while ensuring total capacity of the memory even when a defective memory cell exists in the memory. 
     Thus, the invention described herein makes possible the advantages of (1) providing an address conversion circuit which can reduce the time required to access a memory while ensuring total memory capacity even when a defective memory cell exists in the memory; and (2) providing an address conversion system incorporating such an address conversion circuit. 
    
    
     These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 illustrates an address conversion system according to an example of the present invention; 
     FIG. 2 illustrates a memory control circuit and a memory of the address conversion system of FIG. 1; 
     FIG. 3 shows an exemplary address conversion algorithm for use with the address conversion system of FIG. 1; 
     FIG. 4 is a timing diagram illustrating a memory access operation performed by the address conversion system of FIG. 1; 
     FIG. 5 illustrates a memory control circuit and a memory of an address conversion system according to a variation of the present invention; 
     FIG. 6 illustrates a conventional address conversion system; 
     FIG. 7 illustrates a memory and a memory control circuit of the conventional address conversion system; 
     FIG. 8A illustrates a first processing method used by the conventional address conversion system for performing a memory access operation; and 
     FIG. 8B illustrates a second processing method used by the conventional address conversion system for performing a memory access operation. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An address conversion system according to an example of the present invention will now be described. 
     FIG. 1 illustrates the address conversion system according to the example of the present invention. The address conversion system includes the CPU  3 , a memory control circuit  10  connected to the CPU  3 , and a plurality of memories  2  connected to the memory control circuit  10 . The memory control circuit  10  includes a redundancy decision circuit  1 . When a defective memory cell (not shown) is to be accessed, the redundancy decision circuit  1  replaces the physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in a redundant memory array (not shown). 
     FIG. 2 illustrates the memory control circuit  10  and the memory  2  of the address conversion system in greater detail. FIG. 3 shows an exemplary address conversion algorithm for use with the address conversion system of the present invention. 
     Referring to FIG. 2, the memory control circuit  10  includes the redundancy decision circuit  1 , an address conversion circuit  101 ′, a defective address storing circuit  4  and a control circuit  12 . The redundancy decision circuit  1  includes a comparison circuit  1 B, a replacement circuit  1 C and a selector  1 D. The memory  2  includes a normal memory array  2 A, a redundant memory array  2 B and a defective address storing section  2 C. The CPU  3 , the memory control circuit  10  and the memory  2  are connected to a clock signal line CLK. 
     The normal memory array  2 A includes normal memory cells having a capacity corresponding to the total capacity specification of the memory  2 . The redundant memory array  2 B includes redundant memory cells for replacing defective memory cells which may exist in the normal memory array  2 A, in order to ensure total memory capacity. 
     When the address conversion circuit  101 ′ receives a logic address from the CPU  3 , the address conversion circuit  101 ′ converts the logic address to a physical address in the normal memory array  2 A and outputs the physical address. This address conversion process is performed based on the address conversion algorithm shown in FIG.  3 . 
     The comparison circuit  1 B compares the physical address output by the address conversion circuit  101 ′ with a defective address stored in the defective address storing circuit  4 , and outputs the comparison result. The replacement circuit  1 C replaces the physical address output by the address conversion circuit  101 ′ by another physical address representing a redundant address corresponding to a memory cell in the redundant memory array  2 B. 
     When the comparison result output by the comparison circuit  1 B indicates that there is a match, the selector  1 D selects and outputs the physical address representing the redundant address output by the replacement circuit  1 C to the memory  2 . When the comparison result output by the comparison circuit  1 B indicates that there is no match, the Selector  1 D selects and outputs the physical address in the normal memory array  2 A output by the address conversion circuit  101 ′ to the memory  2 . 
     Based on the physical address from the selector  1 D, the memory  2  accesses either the normal memory array  2 A or the redundant memory array  2 B. 
     FIG. 4 is a timing diagram illustrating an operation of the address conversion system of the present invention. 
     The CPU  3  and the memory control circuit  10  operate in synchronization with a clock signal provided through the clock signal line CLK. Recently, in some systems, the access operation by the memory  2  is also in synchronization with the clock signal provided through the clock signal line CLK. A significant factor in such a clock synchronization type address conversion system is “setup time”. The term “setup time” as used herein and illustrated in FIG. 4 refers to a length of time allowed before a rising edge of the next clock signal pulse after accessed data is obtained. While respective processes performed by the CPU  3 , the memory control circuit  10  and the memory  2  each have a certain setup time, the process by the memory  2  has the least setup time. Therefore, it is desirable to increase the setup time in the process by the memory  2 . 
     As shown in “Conventional Example 1” in FIG. 4, in the conventional address conversion system, the process P 1  (consuming time period T 1 ) is performed as part of the process by the memory  2 . 
     The process P 2  consumes time period T 2  in making an access based on either a normal address or a redundant address (e.g., receiving an address sent from the address conversion circuit  101 ′; pre-decoding the received address; and selecting a word line and a column line). 
     When the memory  2  is assigned with the process P 1  in addition to the process P 2 , the resulting setup time TSU 2  is very short as shown in FIG.  3 . Thus, there is not sufficient time for the accessing process performed by the memory  2 . 
     In order to provide a sufficient setup time TSU 3  as shown in “Conventional Example 2” in FIG. 4, the end of the accessing process is necessarily delayed by one clock. As a result, a latency of 5 clocks is required for the process which is supposed to require a latency of only 4 clocks. Thus, the access speed of the memory  2  decreases when the process P 1  is assigned to the memory  2 , and the memory  2  is responsible for ensuring the total memory capacity. 
     Looking over the entire address conversion system, however, a sufficient time for the accessing process can be found in the process by the memory control circuit  10 . A 1-clock time period TAD is assigned to the process by the memory control circuit  10 . The time period TAD is sufficient to additionally accommodate the process P 1  (for comparing a received physical address with a defective address and, if there is a match, replacing the physical address by a redundant address). 
     Thus, in the address conversion system of the present invention, the process P 1  is assigned as part of the time period TAD. In other words, the time period T 1  as defined in the first and second conventional process methods (FIGS. 8A and 8B) is assigned as part of the time period TAD. As a result, the memory is afforded sufficient time for the accessing process, and the total access time is reduced as compared to the conventional systems. 
     FIG. 5 illustrates a memory control circuit  10 A and the memory  2  of another address conversion system according to a variation of the present example of the invention. In FIG. 5, elements which have been already presented in FIG. 2 are provided with the same reference numerals, and those elements will not be further described below. 
     A difference from the address conversion system illustrated in FIG. 2 is that a mode signal output circuit  1 E is provided in a redundancy decision circuit  11 . The memory control circuit  10 A includes the redundancy decision circuit  11 , the address conversion circuit  101 ′, the defective address storing circuit  4  and the control circuit  12 . The redundancy decision circuit  11  includes the comparison circuit  1 B, the replacement circuit  1 C, the selector  1 D and the mode signal output circuit  1 E. 
     When the comparison result output by the comparison circuit  1 B indicates that there is a match, the mode signal output circuit  1 E sends a mode signal to the memory  2  indicating access to the redundant memory array  2 B. When the comparison result output by the comparison circuit  1 B indicates that there is no match, the mode signal output circuit  1 E sends a different mode signal to the memory  2  indicating access to the normal memory array  2 A. 
     Since the normal memory array  2 A and the redundant memory array  2 B are structurally different from each other, different addressing methods should preferably be used for the respective memory arrays. The redundant memory array  2 B typically has small capacity. If the redundant memory array  2 B has 16 redundant memory cells, for example, an address bit length of 4 is used for addressing the redundant memory array  2 B. Generally, the address bit length used for addressing the redundant memory array  2 B is less than that used for addressing the normal memory array  2 A. Thus, different addressing methods are used for the normal memory array  2 A and the redundant memory array  2 B, respectively. 
     When the memory  2  receives a mode signal indicating access to the redundant memory array  2 B, the memory  2  accesses the redundant memory array  2 B based on an addressing method suitable for the redundant memory array  2 B. Similarly, when the memory  2  receives a mode signal indicating access to the normal memory array  2 A, the memory  2  accesses the normal memory array  2 A based on another addressing method suitable for the normal memory array  2 A. Thus, based on the mode signal, the memory  2  can determine whether a physical address received from the selector  1 D is an address in the normal memory array  2 A or is an address in the redundant memory array  2 B. 
     A method for storing a defective address in the defective address storing circuit  4  will now be described. A defective address in the memory  2  is first stored in the defective address storing section  2 C which is a non-volatile memory device provided in the memory  2 . Thereafter, the defective address is read out from the defective address storing section  2 C and then stored in the defective address storing circuit  4 , as indicated by an arrow AR (FIG.  2 ). For example, a defective address can be stored in the defective address storing section  2 C before the shipping of the memory  2 , and the defective address can be transferred from the defective address storing section  2 C to the defective address storing circuit  4  after mounting the memory  2  in the address conversion system. 
     Defects causing defective addresses include a point bit defect as well as continuous defects such as a word line defect and a bit line defect where the resulting defective addresses are continuous. It is possible to store the continuous defective addresses caused by a continuous defect one by one in the defective address storing circuit  4  or the defective address storing section  2 C. Alternatively, each set of continuous addresses having some common upper bits for each row or column can collectively be stored as defective addresses. 
     Moreover, the redundancy decision circuit  1  can further include a test circuit for determining whether an address in the memory  2  is a defective address and, if it is, storing the defective address in the defective address storing circuit  4 . In such a case, it is possible to relieve not only the defective addresses which have been stored before the shipping of the memory  2 , but also other defective addresses newly found after the memory  2  is mounted in the address conversion system. 
     As described above, the address conversion system of the present invention reduces time required to access a memory while ensuring total capacity of the memory even when a defective memory cell exists in the memory. 
     In the address conversion system according to the illustrated example of the present invention, only one redundancy decision circuit is provided in the memory control circuit. Therefore, it is possible to reduce the area and cost of the memory  2  from those in the conventional address conversion system where the redundancy decision circuit is provided for each of the plurality of memories. 
     In the address conversion system according to the illustrated example of the present invention, before an access request is sent to the memory  2 , the redundancy decision circuit determines whether the requested physical address is a normal address or a redundant address. Therefore, the memory  2  does not have to operate respective circuits for accessing the normal address and for accessing the redundant address. When the requested physical address is a normal address, the memory  2  can operate only one circuit for accessing the normal address. When the requested physical address is a redundant address, the memory  2  can also operate only one circuit for accessing the redundant address. As a result, the power consumption of the address conversion system can be reduced from that of the conventional address conversion system which is required to operate both of such circuits. 
     In the above-described example, the memory  2  is a synchronous type memory which operates in synchronization with a clock signal, but the present invention is not limited thereto For example, the memory  2  may alternatively be a non-synchronous type memory. 
     Moreover, in the above-described example, the redundancy decision circuit is provided in the memory control circuit, but the present invention is not limited thereto. For example, the redundancy decision circuit may alternatively be a circuit separate from the memory control circuit. 
     As described above, when a defective memory cell is to be accessed, the address conversion circuit of the present invention replaces the physical address corresponding to the defective memory cell by another physical address corresponding to a memory cell in the redundant memory array, and outputs the redundant address. 
     Thus, the memory does not require the time period for determining whether the received physical address matches a defective address and, if there is a match, replacing the received physical address by a redundant address. 
     As a result, it is possible to reduce the time required to access a memory while ensuring total capacity of the memory even when a defective memory cell exists in the memory. 
     Various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be broadly construed.