Abstract:
In some embodiments, same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning (SAP) is presented. In this regard, a method is introduced including patterning a first density region of a laminated substrate surface using LPP, patterning a second density region of the laminated substrate surface using SAP, and plating the first and second density regions of the laminated substrate surface, wherein features spanning the first and second density regions are directly coupled. Other embodiments are also disclosed and claimed.

Description:
FIELD OF THE INVENTION 
       [0001]    Embodiments of the present invention generally relate to the field of integrated circuit package substrates, and, more particularly to same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning (SAP). 
       BACKGROUND OF THE INVENTION 
       [0002]    Reductions in the size and pitch of integrated circuit devices require advancements in the manufacture of IC package substrates. The use of lasers is becoming more common for patterning substrates. Disadvantageously, the use of laser projection patterning to pattern a substrate layer tends to cost much more than semi-additive patterning. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0003]    The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which: 
           [0004]      FIG. 1  is a graphical illustration of an overhead view of a package substrate surface, in accordance with one example embodiment of the invention; 
           [0005]      FIGS. 2A-2J  are graphical illustrations of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention; and 
           [0006]      FIGS. 3A-3K  are graphical illustrations of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0007]    In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention. 
         [0008]    Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. 
         [0009]      FIG. 1  is a graphical illustration of an overhead view of a package substrate surface, in accordance with one example embodiment of the invention. In accordance with the illustrated example embodiment, package substrate  100  includes one or more of necking region  102 , main routing region  104 , die shadow  106 , and signal trace  108 . 
         [0010]    Necking region  102  represents a region on the surface of substrate  100  where signals, such as signal trace  108  routed to escape from an integrated circuit die, which would occupy die shadow  106 . In one embodiment, signal traces  108  are input/output (I/O) signals that are routed from outer bumps of the integrated circuit die. Necking region  102  generally has a higher density than main routing region  104 . In one embodiment, necking region  102  contains line widths of about 9 micrometers and spaces of about 12 micrometers. In one embodiment, main routing region  104  contains line widths of greater than about 14 micrometers and spaces of greater than about 14 micrometers. In one embodiment, signal traces  108  have a length within necking region  102  of a few millimeters. As shown, necking region  102  is slightly larger than die shadow  106 . 
         [0011]    As described in embodiments hereafter, same layer microelectronic circuit patterning may use laser projection patterning (LPP) in necking region  102  and semi-additive patterning (SAP) in main routing region  104 . Signal traces  108  are seamlessly spanned (for example, continuous copper traces) across both regions. 
         [0012]      FIGS. 2A-2J  are graphical illustrations of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention.  FIG. 2A  depicts substrate  200  after build-up dielectric  202  is laminated on a core or existing build-up layers, including pads  204 , followed with pre-cure of the dielectric. The dielectric materials are generally polymer based and filled with dispersed silica fillers, such as commercially available fillers and a variety of other materials. 
         [0013]      FIG. 2B  depicts substrate  200  after laser via  206  drilling over the whole pattern and desmear. The desmear process comprises of swelling the walls of via  206  using alkali solution such as sodium hydroxide, and them etching with highly reductive chemical such as permanganate based aqueous solution. 
         [0014]      FIG. 2C  depicts substrate  200  after LPP ablation to form a blank pattern  208  in dielectric  202  at the necking region, such as necking region  102 . The necking region is normally a little larger than the die shadow, containing fine lines and spaces for I/O signal routing and fan-out. 
         [0015]      FIG. 2D  depicts substrate  200  after electroless copper seed layer plating followed with electrolytic copper plating  210  to specific thickness, for example, 5-20 um. The necking area is covered with over-plated copper  212  on the dielectric top surface. 
         [0016]      FIG. 2E  depicts substrate  200  after removal of over-plated copper  212  using a selection of methods such as CMP, mechanical polishing, chemical etching or the combination of the above. After this step the necking region of the pattern is completed. 
         [0017]      FIG. 2F  depicts substrate  200  after electroless copper  214  plating and dry film resist (DFR)  216  lamination. 
         [0018]      FIG. 2G  depicts substrate  200  after DFR  216  is patterned with conventional litho process (exposure and development). The necking region patterned is covered with DFR  216 , except for outer portions  217  of the necking region. 
         [0019]      FIG. 2H  depicts substrate  200  after electrolytic copper  218  plating to specific thickness, for example, 5-20 um. In this way, the main routing region is plated on top of the outer portions  217  of the necking routing region. 
         [0020]      FIG. 2I  depicts substrate  200  after DFR  216  is stripped using alkali solutions such as aqueous sodium carbonate solution. Organic type of solution can also be used. 
         [0021]      FIG. 2J  depicts substrate  200  after chemical etching to remove the electroless copper seed layer  214  to form the whole pattern. 
         [0022]    In one embodiment, package substrate  200  is coupled on surface  220  with an integrated circuit die such as a flip chip silicon die. In another embodiment, surface  220  is laminated with another dielectric layer as part of a continued build-up process. 
         [0023]      FIGS. 3A-3K  are graphical illustrations of a cross-sectional view of a partially formed IC package substrate, in accordance with one example embodiment of the invention.  FIG. 3A  depicts substrate  300  after build-up dielectric is laminated on core or existing layer, including pads  304 , followed with pre-cure of the dielectric. The dielectric materials are generally polymer based and filled with dispersed silica fillers, such as commercially available fillers and a variety of other materials. 
         [0024]      FIG. 3B  depicts substrate  300  after a dielectric protrusion  306  is made on dielectric surface  307  at the necking region. This can be made by selectively laminating an added layer of dielectric, or by imprinting the dielectric layer laminated in step  1  with a pocket that corresponds to the protrusion to be formed. 
         [0025]      FIG. 3C  depicts substrate  300  after laser via  308  drilling over the whole pattern and desmear. The desmear process comprises of swelling the walls of via  308  using alkali solution such as sodium hydroxide, and them etching with highly reductive chemical such as permanganate based aqueous solution. 
         [0026]      FIG. 3D  depicts substrate  300  after LPP ablation to form a blank pattern  310  within protrusion  306  at the necking region. The neck region is normally a little larger than the die shadow, containing fine lines and spaces for I/O signal routing and fan-out. 
         [0027]      FIG. 3E  depicts substrate  300  after electroless copper seed layer  312  plating over the whole pattern. 
         [0028]      FIG. 3F  depicts substrate  300  after DFR  314  lamination over the whole pattern. 
         [0029]      FIG. 3G  depicts substrate  300  after DFR  314  is patterned with conventional litho process (exposure and development). The necking region pattern  310  is exposed after litho. Main region pattern  316  outside the necking region is defined. 
         [0030]      FIG. 3H  depicts substrate  300  after electrolytic plating  318  of the whole pattern to specific thickness, for example, 5-20 um. The necking area is covered with over-plated copper  320  on the top surface of the dielectric layer. 
         [0031]      FIG. 31  depicts substrate  300  after removal of over-plated copper  320  using a selection of methods such as chemical mechanical polishing (CMP), mechanical polishing, chemical etching or the combination of the above. After this step the necking region of the pattern is completed. 
         [0032]      FIG. 3J  depicts substrate  300  after DFR  314  is stripped using alkali solutions such as aqueous sodium carbonate solution. Organic type of solution can also be used. 
         [0033]      FIG. 3K  depicts substrate  300  after chemical etching to remove the electroless copper seed layer  312  to form the whole pattern. 
         [0034]    In one embodiment, package substrate  300  is coupled on surface  322  with an integrated circuit die such as a flip chip silicon die. In another embodiment, surface  322  is laminated with another dielectric layer as part of a continued build-up process. 
         [0035]    In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form. 
         [0036]    Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims.