Abstract:
A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a comparator structure for use in high accuracy applications such as analog to digital converters (ADC). 
         [0003]    2. Related Art 
         [0004]    Comparators are often used in high accuracy applications, such as analog-to-digital conversion. In these applications, quiet high and low voltage supplies are required to achieve low supply noise. However, many known comparators have large current spikes on one or both voltage supplies during output transitions. These current spikes can interfere with chip operation. For example, an image sensor chip may include many column-parallel comparators, each having an output that switches when an input ramp signal reaches a reference level. If the outputs of many comparators transition at the same time, large current spikes may exist on the V DD  or ground rails, thereby creating significant noise that may adversely impact comparators having outputs that have not yet transitioned. 
         [0005]      FIG. 1  is a circuit diagram of a conventional differential comparator  100 , exhibits a large current spike when the output of the comparator changes state. Differential comparator  100  includes PMOS transistors  101 - 102 , NMOS transistors  103 - 104 , output capacitor  105  and current source  110 . PMOS transistors  101  and  102  form a simple differential input pair, which is connected to the active a load formed by NMOS transistors  103  and  104  and capacitor  105 . The gate of PMOS transistor  101  is configured to receive a ramp voltage V+, and the gate of PMOS transistor  102  is configured to receive a reference voltage V−. As the ramp voltage V+ rises from ground level to the V DD  supply voltage, the supply current (I) provided by current source  110  changes in the manner described below. 
         [0006]    When the ramp voltage V+ is less than the reference voltage V−, current flows through PMOS transistor  101 , and current source  110  provides a maximum current. When the ramp voltage V+ reaches or exceeds the reference voltage V−, no current flows through PMOS transistor  101 . At this time, current will flow through PMOS transistor  102  until the output voltage V OUT  of the comparator increases to V DD . At this time, PMOS transistor  102  and current source  110  stop charging capacitor  105  and current flow through PMOS transistor  102  stops. Thus, the current drawn by comparator  100  transitions from a maximum current (when V+ is less than V−) to zero current (when V+ exceeds V−). Some comparators attempt to limit this current transition by connecting the gate of NMOS transistor  104  to a constant bias voltage. However, even in these comparators, the supply current transitions from a maximum current to a current equal to one half of the maximum current. 
         [0007]    U.S. Pat. No. 5,070,259, issued to Rempfer et al., describes an amplifier stage for use in a comparator, wherein the amplifier stage draws a substantially continuous supply current for different values of input voltage. However, this amplifier stage undesirably exhibits a relatively low gain, requiring a large number of amplifier stages to be connected in series in order to provide an adequate gain. In addition, an input capacitor and an output capacitor must be connected in the signal path of the series-connected amplifier stages. 
         [0008]    It would therefore be desirable to have a comparator that does not experience current spikes on either the V DD  or ground supplies during output transitions of the comparator. It would further be desirable if such a comparator does not require an overly complicated structure, a large number of circuit elements, or capacitors connected in the signal path. It would further be desirable for such a comparator to have an input offset cancellation option. 
       SUMMARY 
       [0009]    Accordingly, the present invention provides a comparator that includes a differential comparator and a current control circuit connected in parallel with the differential comparator. In one embodiment, the current control circuit comprises a pair of transistors connected in series between a V DD  supply terminal and a ground supply terminal. The current control circuit draws a current in parallel with the differential comparator, such that the total current drawn by the differential comparator and the current control circuit remains relatively constant across transitions in the output of the comparator. 
         [0010]    The present invention will be more fully understood in view of following description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram of a conventional comparator. 
           [0012]      FIG. 2  is a circuit diagram of a comparator in accordance with one embodiment of the present invention. 
           [0013]      FIGS. 3A and 3B  are circuit diagrams of the comparator of  FIG. 2  during different operating phases in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]      FIG. 2  is a circuit diagram of a comparator  200  in accordance with one embodiment of the present invention. Comparator  200  includes PMOS transistors  201 - 203 , NMOS transistors  204 - 206 , current source  210 , sample capacitor  215 , output capacitor  220  and switches S 1 -S 3 . Comparator  200  is supplied by a V DD  voltage supply  250  and a ground voltage supply  251 . These voltage supplies  250 - 251  effectively form a current source  210 , which provides a source current (I S ) to node N 1 . 
         [0015]    As described in more detail below, PMOS transistors  201 - 202  and NMOS transistors  204 - 205  form a differential comparator circuit, which provides an output voltage (V OUTPUT ) in response to the voltages (V+, V−) applied to the gates of PMOS transistors  201  and  202 . PMOS transistor  203  and NMOS transistor  206  form a current control circuit, which is coupled in parallel with the current paths of the differential comparator circuit, and ensures that a substantially constant current is drawn from current source  210  during all operating phases of comparator  200 . 
         [0016]    The sources of PMOS transistors  201 - 203  are commonly connected to node N 1 , such that these transistors receive the source current I S  provided by current source  210 . The drains of PMOS transistors  201 - 203  are coupled to the drains of NMOS transistors  204 - 206 , respectively. The sources of NMOS transistors  204 - 206  are commonly coupled to the ground supply  251 . The drain of NMOS transistor  204  is also coupled to the gates of NMOS transistors  204  and  205 . Similarly, the drain of NMOS transistor  206  is connected to the gate of NMOS transistor  206 . 
         [0017]    The gate of PMOS transistor  201  is coupled to switches S 1  and S 3 . Switch S 1  is further coupled to receive a reference voltage V REF , and switch S 3  is further coupled to receive a ramp voltage V RAMP . The gates of PMOS transistors  202 - 203  are commonly coupled to a first terminal of sample capacitor  215 . The second terminal of sample capacitor  215  is coupled to the ground supply  251 . The drains of PMOS transistor  202  and NMOS transistor  205  are commonly coupled to the first terminal of output capacitor  220  (i.e., the comparator output terminal). The second terminal of output capacitor  220  is coupled to ground supply  251 . Switch S 2  is coupled between the first terminals of sample capacitor  215  and output capacitor  220 . 
         [0018]    PMOS transistor  203  and NMOS transistor  206  provide a current path from V DD  to ground, enabling the source current I S  provided by current source  210  to remain constant during transitions in the output voltage V OUTPUT . 
         [0019]    PMOS transistor  203  acts as a voltage clamp to maintain the voltage on node N 1  at a level lower than the sum of the input voltage V− and the threshold voltage (V TP ) of PMOS transistor  202 . NMOS transistor  206  maintains a symmetrical source current flow when the input voltage V+ reaches (or exceeds) the input voltage V−. This configuration allows comparator  200  to be connected in a unity feedback configuration to cancel any input offsets. 
         [0020]    The operation of comparator  200  will now be described in more detail.  FIGS. 3A and 3B  are circuit diagrams illustrating the two operating phases of comparator  200  in accordance with one embodiment of the present invention. 
         [0021]      FIG. 3A  illustrates a first operating phase of comparator  200 , wherein switches S 1  and S 2  are closed (conductive) and switch S 3  is open (non-conductive). Under these conditions, a reference voltage V REF  is applied to the gate of PMOS transistor  201 . In response, sample capacitor  215  charges until the voltage applied to the gate of PMOS transistor  202  is equal to the reference voltage V REF  (i.e., the input voltage V− is equal to the reference voltage V REF ). Stated another way, the reference voltage V REF  is sampled on the first terminal of sample capacitor  215  (as well as the first terminal of output capacitor  220 ). In one embodiment, the reference voltage V REF  may be a predetermined voltage. In another embodiment, the reference voltage V REF  may be representative of a pixel value. 
         [0022]    During the first operating phase illustrated by  FIG. 3A , the source current I S  flows through PMOS transistors  201 - 203 . If PMOS transistors  201 - 203  are all the same size, and NMOS transistors  204 - 206  are all the same size, then the same current (i.e., I S /3) will flow through PMOS transistors  201 ,  202  and  203  during the first operating phase. 
         [0023]      FIG. 3B  illustrates a second operating phase of comparator  200 , wherein switches S 1  and S 2  are open (non-conductive) and switch S 3  is closed (conductive). Under these conditions, an increasing single-slope ramp voltage V RAMP  is applied to the gate of PMOS transistor  201 . In one embodiment, the ramp voltage V RAMP  starts at ground (0 Volts) and linearly increases to a voltage equal to the V DD  supply voltage. In another embodiment, the ramp voltage V RAMP  starts from a voltage representative of a pixel value. When switch S 2  is opened, sample capacitor  215  continues to apply the sampled reference voltage V REF  to the gates of PMOS transistors  202  and  203 . Because the ramp voltage signal V RAMP  is initially less than the sampled reference voltage V REF , the output voltage V OUTPUT  is pulled down to ground via NMOS transistor  205 , and no current flows through PMOS transistor  202 . 
         [0024]    While the ramp voltage V RAMP  is less than the reference voltage V REF , the source current I S  flows only through PMOS transistor  201 . When the ramp voltage V RAMP  reaches the reference voltage V REF , the source current I S  flows through all of PMOS transistors  201 - 203  equally. 
         [0025]    When the ramp voltage V RAMP  exceeds the reference voltage V REF , the source current I S  initially flows through PMOS transistors  202  and  203  equally. The current flowing through PMOS transistor  202  charges output transistor  220 , thereby increasing the output voltage V OUTPUT . As the output voltage V OUTPUT  rises, the current flow through PMOS transistor  202  decreases, thereby increasing the current flow through PMOS transistor  203 . When the output voltage V OUTPUT  reaches a voltage equal to the reference voltage V REF  plus the threshold voltage of PMOS transistor  202 , current no longer flows through PMOS transistor  202 , and the entire source current I S  flows through PMOS transistor  203 . 
         [0026]    Advantageously, the unity feedback configuration of  FIG. 3A  (wherein the reference voltage V REF  applied to the gate of PMOS transistor  201  is fed back to the gates of PMOS transistors  202 - 203 ) in combination with the application of the ramp voltage V RAMP  of  FIG. 3B  (wherein the ramp voltage V RAMP  is applied to the gate of PMOS transistor  201 ) effectively cancels any input offset exhibited by comparator  200 . 
         [0027]    Current spikes associated with comparator  200  are reduced approximately 100 times, when compared with a conventional comparator structure. Comparator  200  advantageously reduces current spikes from the V DD  voltage supply  250  and the ground supply  251  by adding only two transistors  203  and  206  to a conventional comparator structure. Thus, the improvements are achieved at a relatively low cost in terms of increased layout area. 
         [0028]    Comparator  200  can advantageously be replicated many times in an analog to digital converter, such as a column parallel global ramp ADC in an image sensor, while maintaining quiet power supplies. In addition, comparator  200  advantageously does not require capacitors in the signal path. 
         [0029]    Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Thus, the invention is limited only by the following claims.