Abstract:
A power supply circuit arranged in a circuit board to supply a determined voltage to an element is disclosed. The power supply circuit includes two voltage receiving terminals to receive voltage signals, a window comparator, and an electrical switch. The comparator drives the electrical switch to be turned on, therefore a terminal of the electrical switch stably output the determined voltage to the element.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to power supply circuits and, particularly, to a power supply circuit to supply a voltage to an element of a circuit board. 
     2. Description of Related Art 
     Most motherboards include south bridge chips. Power supply circuits provide voltages to the south bridge chips. These power supply circuits may include some voltage converting chips. However, these voltage converting chips are very expensive and complicated. A low-cost power supply circuit is therefore desirable. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       The drawing is a circuit diagram of an exemplary embodiment of a power supply circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to the drawing, an exemplary embodiment of a power supply circuit  10  is arranged in a motherboard  100  to supply a 1.5V voltage to a south bridge chip  20 . The power supply circuit  10  includes a 3.3V voltage receiving terminal 3.3V_SB, a 12V voltage receiving terminal 12V_SYS, a 1.8V voltage receiving terminal 1.8V_STR, a window comparator U, an electrical switch such as a field-effect transistor (FET) Q, a divider circuit including two resistors R 1  and R 2 , a resistor R 3 , and five capacitors C 1 -C 5 . The 3.3V voltage receiving terminal 3.3V_SB is used to receive a 3.3V voltage signal from the motherboard  100 . The 12V voltage receiving terminal 12V_SYS is used to receive a 12V voltage signal from the motherboard  100 . The 1.8V voltage receiving terminal 1.8V_STR is used to receive a 1.8V voltage signal from the motherboard  100 . In one embodiment, the 3.3V, 12V, and 1.8V voltage signals are respectively a 3.3V standby voltage signal, a 12V system voltage signal, and a 1.8V memory voltage signal of the motherboard  100 . 
     The 3.3V voltage receiving terminal 3.3V_SB is grounded via the capacitor C 1 , and connected to a first terminal of the resistor R 1 . A second terminal of the resistor R 1  is grounded via the resistor R 2  and the capacitor C 2 , which are connected in parallel. A node between the resistor R 1  and the resistor R 2  is connected to a non-inverting terminal of the comparator U. A power terminal of the comparator U is connected to the 12V voltage receiving terminal 12V_SYS, and grounded via the capacitor C 3 . A ground terminal of the comparator U is grounded. An inverting terminal of the comparator U is connected to a 1.5V voltage pin 1.5V_ICH of the south bridge chip  20 . An output terminal of the comparator U is connected to a gate of the FET Q, and connected to the 1.5V voltage pin 1.5V_ICH of the south bridge chip  20  via the resistor R 3 . A source of the FET Q is connected to the 1.5V voltage pin 1.5V_ICH of the south bridge chip  20 . A drain of the FET Q is connected to the 1.8V voltage receiving terminal 1.8V_STR, and grounded via the capacitor C 4 . The capacitor C 5  is connected between the 1.5V voltage pin 1.5V_ICH of the south bridge chip  20  and ground. A voltage drop between the source and drain of the FET Q is 0.3V when the FET Q is turned on. Resistances of the resistors R 1  and R 2  satisfy the voltage of the non-inverting terminal of the comparator U, which is approximately 1.5V. 
     When the motherboard  100  is powered on, the 3.3V, 12V, and 1.8V voltage receiving terminals 3.3V_SB, 12V_SYS, and 1.8V_STR respectively receive the 3.3V, 12V, and 1.8V voltage signals from the motherboard  100 . The comparator U outputs a high voltage signal, such as 3V, to the gate of the FET Q to turn on the FET Q. Because the voltage drop between the source and drain of the FET Q is 0.3V when the FET Q is turned on, the voltage of the source of the FET Q is equal to 1.8V−0.3V=1.5V. The 1.5V voltage pin 1.5V_ICH of the south bridge chip  20  receives the 1.5V voltage signal of the source of FET Q. Because the inverting terminal of the comparator U receives a 1.5V feedback signal from the 1.5V voltage pin 1.5V_ICH of the south bridge chip  20 , the non-inverting terminal of the comparator U is approximately 1.5V, and because the comparator U is a window comparator, thereby the 1.5V voltage signal of the source of FET Q is stable. Furthermore, output currents from the comparator U and the FET Q are very large, thereby the power supply circuit  10  can drive a great load. In other embodiments the capacitors C 1 -C 5  can be omitted to save costs. 
     It is to be understood, however, that even though numerous characteristics and advantages of the embodiments have been set forth in the foregoing description, together with details of the structure and function of the embodiments, the disclosure is illustrative only, and changes may be made in details, especially in matters of shape, size, and arrangement of parts within the principles of the embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.