Abstract:
Pipeline analog-to-digital converters (ADCs) are used in many applications, but because of the configuration, components may be idled, which wastes power. Here, an ADC is provided that enables one or more stages to be switched off during a power conservation mode. By using switch networks, the ADC can produce accurate results with reduced power consumption, as desired.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is claims priority from Japanese Patent Application No. 2009-132360, filed Jun. 1, 2009, which is hereby incorporated by reference for all purposes. 
       TECHNICAL FIELD 
       [0002]    The invention generally relates to a pipeline analog-to-digital converter (ADC). 
       BACKGROUND 
       [0003]    Pipeline ADCs are employed is in wide variety of applications, such as for signal processing in the field of video and communication. An example of a conventional circuit is Japanese Patent Application No. JP10-163,875. In many of these applications, in order to decrease power consumption by the signal processor, the frequency of the clock signal is switched. For example, when pictures are taken and recorded to a memory in a digital camera, in order to increase the resolution of the pictures, the frequency of the clock signal is increased, and the clock signal is decreased to lower the resolution of the image only in the period when the image of the object is displayed on the screen. That way, switching the frequency of the clock signal to correspond to the user&#39;s application mode or the like, it is possible to efficiently decrease the current consumption, particularly of the logic circuit. However, a pipeline ADC is a circuit with combined analog and digital portions, and the current steadily consumed by the analog portion is larger than that consumed in the digital portion. The method for switching the frequency of the clock signal is effective in decreasing the current flowing any time the logic value of the output of the digital portion varies. However, this method has no effect at all in decreasing the current steadily consumed in the analog portion. 
       SUMMARY 
       [0004]    In accordance with a preferred embodiment of the invention, an apparatus is provided. The apparatus comprises a clock generator that generates a plurality of clock signals; a sample-and-hold (S/H) circuit that is coupled to the clock generator and that receives an input signal; a plurality conversion stages coupled in series with one another in a sequence, wherein each conversion stage is coupled to the clock generator; a switch network that is coupled to at least one of the conversion stage so as to turn it off and bypass it in a power conservation mode; a plurality of delay circuits, wherein each delay circuit is coupled to at least one of the conversion stages, and wherein each delay circuit includes at least one latch that is coupled to the clock generator; a plurality of correction circuit, wherein each correction circuit is coupled to at least one of the delay circuits; and a register that is coupled to each of the correction circuits. 
         [0005]    In accordance with a preferred embodiment of the invention, the apparatus further comprises a clock switch that is coupled between the clock generator and each of the delay circuits. 
         [0006]    In accordance with a preferred embodiment of the invention, the clock switch that is coupled between the clock generator and each of the conversion stages. 
         [0007]    In accordance with a preferred embodiment of the invention, wherein the switch network further comprises: a first switch that is coupled between the S/H circuit and the first conversion stage of the sequence, wherein the first switch is closed in a normal mode, and wherein the first switch is open in the power conservation mode; a second switch that is coupled between the S/H circuit and the second conversion stage of the sequence, wherein the second switch is open in the normal mode, and wherein the second switch is closed in the power conservation mode; a third switch that is coupled between a power supply and the first conversion stage of the sequence, wherein the third switch is closed in the normal mode, and wherein the third switch is open in the power conservation mode; and a fourth switch that is coupled between the first conversion stage of the sequence and its delay circuit, wherein fourth switch couples the first conversion stage of the sequence to it delay circuit in the normal mode. 
         [0008]    In accordance with a preferred embodiment of the invention, the apparatus further comprises a crossbar that is coupled between at least one of the conversion stages and its delay circuit. 
         [0009]    In accordance with a preferred embodiment of the invention, the switch network further comprises: a first switch that is coupled between the third-to-last conversion stage of the sequence and the second-to-last conversion stage of the sequence, wherein the first switch is closed in a normal mode, and wherein the first switch is open in the power conservation mode; a second switch that is coupled between the third-to-last conversion stage of the sequence and the last conversion stage of the sequence, wherein the second switch is open in the normal mode, and wherein the second switch is closed in the power conservation mode; a third switch that is coupled between a power supply and the second-to-last conversion stage of the sequence, wherein the third switch is closed in the normal mode, and wherein the third switch is open in the power conservation mode; and a fourth switch that is coupled between the second-to-last conversion stage of the sequence and the clock generator, wherein fourth switch couples the first conversion stage of the sequence to it delay circuit in the normal mode. 
         [0010]    In accordance with a preferred embodiment of the invention, the switch network further comprises a first switch network, and wherein the apparatus further comprises a second switch network that is coupled between the clock switch and the delay circuit associated with the first conversion stage of the sequence. 
         [0011]    In accordance with a preferred embodiment of the invention, the switch network further comprises: a first switch that is coupled between the third-to-last conversion stage of the sequence and the second-to-last conversion stage of the sequence, wherein the first switch is closed in a normal mode, and wherein the first switch is open in the power conservation mode; a second switch that is coupled between the third-to-last conversion stage of the sequence and the last conversion stage of the sequence, wherein the second switch is open in the normal mode, and wherein the second switch is closed in the power conservation mode; a third switch that is coupled between a power supply and the second-to-last conversion stage of the sequence, wherein the third switch is closed in the normal mode, and wherein the third switch is open in the power conservation mode; and a fourth switch that is coupled between the second-to-last conversion stage of the sequence and the clock generator, wherein fourth switch couples the first conversion stage of the sequence to it delay circuit in the normal mode. 
         [0012]    In accordance with a preferred embodiment of the invention, the switch network further comprises a first switch network, and wherein the apparatus further comprises a second switch network that is coupled between the clock generator and the delay circuit associated with the second-to-last conversion stage of the sequence. 
         [0013]    In accordance with a preferred embodiment of the invention, the apparatus further comprises a crossbar that is couple between each of the correction circuits and the register. 
         [0014]    In accordance with a preferred embodiment of the invention, an apparatus is provided. The apparatus comprises a clock generator that generates a plurality of clock signals; a sample-and-hold (S/H) circuit that is coupled to the clock generator and that receives an input signal; a plurality conversion stages coupled in series with one another in a sequence, wherein each conversion stage is coupled to the clock generator, and wherein each conversion stage includes: an analog-to-digital converter (ADC); a digital-to-analog converter (DAC) that is coupled to the DAC; a S/H circuit; an adder that is coupled to the S/H circuit and the DAC so as to generate a difference between output of the S/H circuit and the DAC; and an amplifier that is coupled to the adder; a switch network that is coupled to at least one of the conversion stage so as to turn it off and bypass it in a power conservation mode; a plurality of delay circuits, wherein each delay circuit is coupled to at least one of the conversion stages, and wherein each delay circuit includes at least one latch that is coupled to the clock generator; a plurality of correction circuit, wherein each correction circuit is coupled to at least one of the delay circuits; and a register that is coupled to each of the correction circuits. 
         [0015]    The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0017]      FIG. 1  is a block diagram of an example of an ADC in accordance with a preferred embodiment of the present invention; 
           [0018]      FIG. 2  is a block diagram of an example of a conversion stage of  FIG. 1 ; 
           [0019]      FIG. 3  is a timing diagram for the clock signals of  FIG. 1 ; and 
           [0020]      FIGS. 4 and 5  are block diagrams of examples of ADCs in accordance with a preferred embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. 
         [0022]    Turning to  FIG. 1 , an ADC  100 - 1  in accordance with a preferred embodiment of the present invention can be seen. ADC  100 - 1  generally comprises a sample-and-hold (S/H) circuit  10 , conversion stages  20 - 1  to  20 - 7 , delay circuit  30  (which includes delay circuits  31 - 37 ), correction circuit  40  (which includes correction circuits  41 - 46 ), register  50 , clock generator  60 , clock switch  70 , and switches SW 11 , SW 12 , SW 3 , SW 4 . In operation, clock generator  60  generates two clock signals CK 1 , CK 2  in different phases and changes their frequencies in response to control signal SMOD that indicates the operation mode. S/H circuit  10  carries out sampling and holding of the input analog signal SIN in synchronization with clock signal CK 1 . 
         [0023]    Conversion stages  20 - 1  to  20 - 7  sequentially convert analog signal SIN held in S/H circuit  10  to digital signals Do 1 -Do 7  from the most-significant bit to the least-significant bit. Conversion stage  20 - 1  converts analog signal SIN held in S/H circuit  10  to 3-bit digital signal Do 1 , and the difference between the analog signal corresponding to the digital signal Do 1  and the input analog signal SIN is amplified and is output to the next stage (conversion stage ( 20 - 2 )). Just as conversion stage  20 - 1 , conversion stages  20 - 2  to  20 - 6  each convert its input signal from the preceding stage to a 3-bit digital signal Do 2 -Do 6 , amplify the difference between the analog signal, and output the amplified difference. Additionally, as an example, conversion stage  20 - 7  can be a flash type ADC, and the input signal from the preceding section (conversion stage  20 - 6 ) is converted to 4-bit digital signal Do 7 . 
         [0024]    Turning now to  FIG. 2  is a diagram illustrating an example of conversion stages  20 - 1  to  20 - 6  of  FIG. 1  (hereinafter referred to as  20 ) can be seen. Conversion stage  20  generally comprises an ADC  21 , a digital-to-analog converter (DAC)  22 , an S/H circuit  24 , an adder  25 , and an amplifier. In operation the ADC generate digital signal Do from signal Vin, while DAC  22  converts signal Do back to an analog signal that is provided to the adder  25 . S/H circuit  24  samples signal VIN based on clock signal, which is provided to the adder  25 . Adder  25  determines the difference between the sample of signal VIN and the analog signal from DAC  22 , and amplifier  26  amplifies the difference. 
         [0025]    In  FIG. 3 , a timing diagram for clock signals CK 1  and CK 2  can be seen. As shown, clock signals CK 1  and CK 2  are phase shifted from each other by 180°. This phase shift enables S/H circuit  10  (of  FIG. 1 ) to sample and hold input signal SIN based on clock signal CK 1 . 
         [0026]    Now, turning back to  FIG. 1 , the switch network of ADC  100 - 1  can control the conversion stage pipeline so as to operate in one of two modes: power conservation mode and normal mode. In power conservation mode, switches SW 3  and SW 11  are open, while switches SW 12  is close, and while switch SW 4  coupled the delay circuit  31  to ground. Thus, in power conservation mode, the power to stage  20 - 1  and delay circuit is cut off, and stage  20 - 1  is skipped or bypassed. In normal mode, switches SW 3  and SW 11  are closed, while switch SW 12  is open and while switch SW 4  couples stage  20 - 1  to delay circuit  31 . Thus, the full pipeline can be used in the normal mode. 
         [0027]    Looking to circuit  30 , it includes delay circuits  31 - 37  that delay digital signals Do 1 -Do 7  generated in conversion stages  20 - 1  to  20 - 7 , respectively. Delay circuit  31 - 37  respectively comprise a 7-stage latch circuit (L 11  to L 17 ), a 6-stage latch circuits (L 21  to L 26 ), a 5-stage latch circuits (L 31  to L 35 ), a 4-stage latch circuits (L 41  to L 44 ), a 3-stage latch circuits (L 51  to L 53 ), a 2-stage latch circuits (L 61  to L 62 ), and a of 1-stage latch circuit (L 71 ). Different clock signals (clock signal CKA or CKB which are output from clock switch  70 ) are input to the odd-numbered stages and even-numbered stages connected in tandem in delay circuits  31 - 36 . That is, one clock signal is commonly input to the odd-numbered stages, while the other clock signal is commonly input to the even-numbered stages. Each latch circuit holds the input signal in synchronization with the rising edge of the clock signal. Typically, clock signal CK 1  is fed to the last-stage latch circuits (L 17 , L 26 , L 35 , L 44 , L 53 , L 62 , L 71 ) of delay circuits  31 - 37 . However, just as with other latch circuits in the delay circuit, one may also adopt a method in which carry signal CKA or CKB is selectively fed corresponding to the operation mode. 
         [0028]    Because clock signal CKA and clock signal CKB have phases shifted from each other by half-period (see, e.g.,  FIG. 3 ), the tandem latch circuit shifts the digital signal every half-period of the clock signal. That is, a delay of a half-period is generated due to one stage of the latch circuit. The delay of a half-period corresponds to the delay of one stage when digital signals Do 1 -Do 7  are sequentially generated in conversion stages  20 - 1  to  20 - 7 . The first-stage latch circuits (L 11 , L 21 , L 31 , L 41 , L 51 , L 61 , L 71 ) of delay circuits  31 - 37  latch the digital signal when the state is changed from hold state to sampling state for the conversion stage preceding the conversion stage of the output origin of the latched digital signals Do 1 -Do 7  that should be latched (or held by S/H circuit  10 ). For example, latch circuit L 31  for input of digital signal Do 3  of the 3rd conversion stage  20 - 3  latches digital signal Do 3  when conversion stage  20 - 2  as the stage, preceding the conversion stage  20 - 3 , transitions from hold state to sampling state. In normal mode, clock signal CK 1  (or CKA) is input to conversion stage  20 - 2 , and latch circuit L 31  latches digital signal Do 3  in synchronization with the rising edge of clock signal CK 1  (or CKA). 
         [0029]    Additionally, depending on to mode of operation, clock switch  70  can switch clock signals CK 1  and CK 2  fed to conversion stage  20  and delay circuit  30 . That is, in normal mode, clock switch  70  outputs clock signal CK 1  as clock signal CKA, and outputs clock signal CK 2  as clock signal CKB. On the other hand, in power conservation mode, clock switch  70  outputs clock signal CK 1  as clock signal CKB, and clock signal CK 2  as clock signal CKA. More specifically, in normal mode, clock signal CK 2  is input to the latch circuits of the odd-numbered stages of delay circuits  32 ,  34 , and  36  and the latch circuits of the even-numbered stages of delay circuits  31 ,  33 , and  35 , and clock signal CK 1  is input to the latch circuits of the even-numbered stages of delay circuits  32  and  34  and the latch circuits of the odd-numbered stages of delay circuits  31 ,  33 , and  35 . In power conservation mode, clock signal CK 1  is input to the latch circuits of the odd-numbered stages of delay circuits  32 ,  34 , and  36  and the latch circuits of the even-numbered stages of delay circuits  31 ,  33 , and  35 , and clock signal CK 2  is input to the latch circuits of the even-numbered stages of delay circuits  32  and  34  and the latch circuits of odd-numbered stages of delay circuits  31 ,  33 , and  35 . In this power conservation mode, just as in normal mode, clock signal CK 1  is fed to the last-stage latch circuits (i.e., L 17 , L 26 , L 35 , L 44 , L 53 , L 62 , L 71 ) of various delay circuits  31 - 37 . 
         [0030]    As clock switch  70  switches clock signals CK 1  and CK 2  in power conservation mode, the timing of sampling of the input signal in conversion stages  20 - 2  to  20 - 6  downstream of the conversion stage  20 - 1  in the off state and timing in holding and sampling are inverted. Also, corresponding to inversion of timing in conversion stages  20 - 2  to  20 - 6 , the timing of signal holding is also changed in delay circuits  32 - 36  that hold digital signals Do 2 -Do 6  of conversion stages  20 - 2  to  20 - 6  downstream of conversion stage  20 - 1  in the off state. Additionally, because the number of the bypassed conversion stages is an odd number, clock switch  70  switches clock signal CK 1  and clock signal CK 2 . On the other hand, when the number of the bypassed conversion stages is an even number, there is no need to switch between clock signal CK 1  and clock signal CK 2 . 
         [0031]    Looking now to the correction circuit  40 , in includes correction circuits  41 - 46  that correct digital signals Do 1 -Do 6  generated in conversion stages  20 - 1  to  20 - 6 . The most-significant bit in 4-bit digital signal Do 1  outputs from delay circuit  37  inputs as a carry signal is input to the correction circuit  46 . The correction circuit  46  corrects digital signal Do 6  based on the input carry signal, and as the correction result, it generates a 3-bit digital signal. In the correction, for example, the input carry signal and digital signal Do 6  of the connection object are added to generate a 3-bit digital signal. The correction circuit  46  outputs the most-significant bits in the generated 3-bit digital signal as the carry signal to correction circuit  45 , and, at the same time, it outputs the least-significant two bits as the place-4 and place-5 bit signals B 3 , B 4  of digital signal DOUT to register  50 . Correction circuits  41 - 45  generate digital signals Do 1 -Do 5  as the correction object and the carry signal in company with correction of the digital signal generated in the conversion stage downstream of the conversion stage of the generating origin of the digital signal input to it. For example, for correction circuit  45 , its generating origin of digital signal Do 5  as the correction object is conversion stage  20 - 5 , and its downstream stage is conversion stage  20 - 6 . Digital signal Do 6  generated in conversion stage  20 - 6  is corrected by correction circuit  46 , and correction circuit  45  receives the carry signal from correction circuit  46 . Here, correction circuits  41 - 45  correct the digital signals as the correction object based on the input carry signal, and they generate the 3-bit digital signals as the correction results. In this correction, for example, the carry signal input from the downstream conversion stage and the digital signals Do 1 -Do 5  as the correction object are added to generate the 3-bit digital signal. 
         [0032]    Additionally, correction circuits  41 - 45  output the carry signal generated corresponding to the correction result for correcting the digital signal generated by the upstream conversion stage with respect to the conversion stage of the generating origin of digital signals Do 1 -Do 5  as the correction object. For example, for correction circuit  45 , the upstream stage with respect to conversion stage ( 20 - 5 ) as the generating origin of digital signal Do 5  is conversion stage ( 20 - 4 ). Digital signal Do 4  generated by conversion stage ( 20 - 4 ) is corrected by correction circuit  44 , so that correction circuit  45  outputs the carry signal to correction circuit  44 . In this case, correction circuits  41 - 45  output the most-significant bit among the generated 3-bit digital signal as the carry signal to the upstream conversion stage, while they output the remaining two bits as a portion of digital signal Dout to register  50 . For example, correction circuit  45  outputs the most-significant bit of the generated 3-bit digital signal as the carry signal to correction circuit  44 , and it outputs the remaining two bits as bit signals B 5 , B 6  (the  6 th and  7 th places) of digital signal Dout to register  50 . In addition, the top correction circuit  41  outputs the carry signal generated in company with correction of digital signal Do 1  as bit signal B 15  (16th place) of digital signal Dout to register  50 . While register  50  outputs the least-significant 3 bits of 4-bit digital signal Do 1  from delay circuit  37  input as bit signals B 0 -B 2  (1st place to 3rd place) of digital signal Dout, the 13-bit signal output from correction circuit  40  is input as bit signals B 3 -B 15  (4th place to 16th place) of digital signal Dout. The register  50  holds input bit signals B 0 -B 15  in synchronization with clock signal CK 1  or CK 2 . 
         [0033]    As explained above, in power conservation mode, conversion stage  20 - 1  is turned off, and the input signal to conversion stage  20 - 1  is input to conversion stage  20 - 2  as the downstream stage. As a result, it is possible to efficiently decrease power consumption by performing analog/digital conversion while the number of conversion stages is smaller than that in normal mode. 
         [0034]    Also, in power conservation mode, the top conversion stage is turned off. For the upstream conversion stage, signals should be processed at a higher precision than in the downstream conversion stage. Consequently, the upstream conversion stage consumes a larger current than the downstream conversion stage. Consequently, it is possible to efficiently decrease the power consumption by turning off the top conversion stage  20 - 1  that consumes the largest current. Also, for the ADC in the present embodiment, the frequency of the clock signals CK 1 , CK 2  in power conservation mode is much lower than that of the normal mode. 
         [0035]    When the frequency of the clock signal decreases, the operational speed required on the conversion stage is lower, and it is possible to meet the necessary precision corresponding to a smaller current consumption. That is, in normal mode at a high operation frequency, the least-significant conversion stage that cannot meet the precision needed for the most-significant stage can meet the precision of the most-significant stage in power conservation mode at a lower operation frequency. 
         [0036]    Consequently, for ADC  100 - 1 , the upstream conversion stage in normal mode is turned off in power conservation mode, and the downstream conversion stage is shifted for use as the upstream conversion stage. Even in this case, the current consumption of the downstream conversion stage is kept the same as that in normal mode, and the necessary precision can be met. As a result, there is no need to change and adjust the current consumption of the downstream conversion stage corresponding to the operation mode. Consequently, it is possible to simplify the circuit. Also, there is no need to have an excessive current for consumption flow in the downstream conversion stage, so that there is no degradation in the effect of decrease in the current consumption. Also, the circuit may also have a constitution in which supply of clock signals CK 1  and CK 2  to conversion stage  20 - 1  is turned off in the off state and delay circuit  31  of digital signal Do 1 . As a result, it is possible to further decrease power consumption. Also, when conversion stage  20 - 1  is turned off due to transition to power conservation mode, by means of clock switch  70 , the timing of sampling of the input signal and the timing of holding of the sampled results in conversion stages  20 - 2  to  20 - 6  downstream from conversion stage  20 - 1 , which has been turned off, are inverted. 
         [0037]    Consequently, with the ADC  100 - 1 , even when the number of conversion stages is changed due to transition to power conservation mode, it is still possible to set the sampling/holding timing in each conversion stage appropriately. Also, corresponding to inversion of the timing of conversion stage  20 , the timing of latching in delay circuit  30  is inverted by clock switch  70 . As a result, by changing the timing of sampling and holding to change the timing of output of the digital signal from each conversion stage, delay circuit  30  still can latch the digital signal at an appropriate timing. Additionally, when the second conversion stage  20 - 2  becomes substantially the first stage in power conservation mode, the carry signal generated by correction circuit  42 , which carries out correction of digital signal Do 2 , is output as the most-significant bit (B 13 ) of the analog/digital conversion result Dout from correction circuit  41  to register  50 . 
         [0038]    Turning now to  FIG. 4 , ADC  100 - 2  can be seen. ADC  100 - 2  is similar in structure to ADC  100 - 1 . However, switches SW 11 , SW 12 , SW 3 , and SW 4  have been replaced by switches SW 11 A, SW 12 A, SW 3 A, SW 41 , SW 42 , SW 26 A and SW 5 , and crossbar  80  has been included. As with ADC  100 - 1 , ADC  100 - 2  operates in two modes: power conservation mode and normal mode. 
         [0039]    In power conservation mode, switches SW 11 A, SW 12 A, SW 3 A, SW 5 , and SW 26 A are controlled to skip or bypass stage  20 - 6 . Switch SW 3 A cuts off the power supply to conversion stage  20 - 6 , while switch SW 26 A turns off supply of the clock signal with respect to conversion stage  20 - 6 . Additionally, switch SW 11 A and switch SW 12 A controls the output signal of conversion stage  20 - 5  to bypass conversion stage  20 - 6  and be input to conversion stage  20 - 7 . Switch SW 11 A is provided in the path that connects the output of conversion stage  20 - 5  and the input of conversion stage  20 - 6 . Switch SW 12 A is provided in the path that connects the output of conversion stage  20 - 5  and the input of conversion stage  20 - 7 . Also, switch SW 5  decouples correction circuit  41  from input B 13  in power conservation mode. 
         [0040]    In contrast, switches SW 11 A, SW 12 A, SW 13 A, SW 41 , SW 42 , SW 26 A and SW 5  are controlled to include stage  20 - 6  in normal mode. In particular, switch SW 12 A is open, and switches SW 3 A and SW 11 A are closed. Additionally, switch SW 26 A couples stage  20 - 6  to receive the clock signal. 
         [0041]    Look to crossbar  80 , it switches couplings between upstream conversion stages  20 - 1  to  20 - 5  and delay circuits  31 - 36  so that the timing of output of digital signal Do 7  of conversion stage  20 - 7  downstream from conversion stage  20 - 6  in the off state from delay circuit  30  and the timing of output of digital signals Do 1 -Do 5  of upstream conversion stages  20 - 1  to  20 - 5  from conversion stage  20 - 6  in the off state from delay circuit  30  are in agreement with each other. That is, in normal mode, crossbar  80  couples conversion stages  20 - 1  to  20 - 6  to delay circuits  31 - 36 , respectively, and in power conservation mode, crossbar  80  coupled conversion stages  20 - 1  to  20 - 5  to delay circuits  32 - 36 , respectively. In power conservation mode, conversion stages  20 - 1  to  20 - 5  are shifted downstream by one stage, and the delay of digital signals Do 1 -Do 5  is shortened by a half-period of the clock signal. 
         [0042]    Corresponding to switching of conversion stages ( 20 - 1  to  20 - 5 ) and delay circuits  31 - 36  by crossbar  80 , clock switch  70  switches clock signals CK 1  and CK 2  input to the various latch circuits of the delay circuit so that the digital signals output from the various conversion stages are held in the latch circuits of the delay circuit at an appropriate timing. In normal mode, clock signal CK 1  is fed to the odd number latch circuits of delay circuits  32 ,  34 , and  36  and the even number latch circuits of delay circuits  31 ,  33 , and  35 , and clock signal CK 2  is fed to the even number latch circuits of delay circuits  32 ,  34 ,  36  and the odd number latch circuits of delay circuits  31 ,  33 ,  35 . On the other hand, in power conservation mode, the supply destinations of clock signals CK 1  and CK 2  are reversed, and, at the same time, by means of switch SW 41  and switch SW 42 , feed of clock signals CK 1 , CK 2  to delay circuit  31  is turned off. Also, clock switch  70  feeds clock signal CK 1  to conversion stage  20 - 7  in normal mode and feeds clock signal CK 2  to conversion stage  20 - 7  in power conservation mode. 
         [0043]    Turning now to  FIG. 5 , ADC  100 - 3  can be seen. ADC  100 - 3  is similar in construction to ADC  100 - 2 , but switches SW 41  and SW 42 , clock switch  70 , and crossbar  80  have been omitted. Additionally, switches SW 71 , SW 72 , SW 81 , SW 82 , SW 91  and crossbar  90  are provided, and delay circuit  37  is has been by delay circuit  37 A. Similar to both ADCs  100 - 1  and  100 - 2 , ADC  100 - 3  has two modes of operation: power conservation mode and normal mode. As a results, switches SW 12 A, SW 11 A, SW 3 , and SW 26 A of ADC  100 - 3  have the same configurations as with ADC  100 - 2 . 
         [0044]    When conversion stage  20 - 6  is in off state in power conservation mode, delay circuit  37 A increases the number of stages of the latch circuits in delay circuit ( 37 A) by one stage so that digital signals Do 1 -Do 5  generated sequentially in conversion stages  20 - 1  to  20 - 5  upstream of conversion stage  20 - 6  and digital signal Do 7  generated after digital signal Do 6  in conversion stage  20 - 7  downstream of conversion stage  20 - 6  are output at the common timing from delay circuit  30 . For example, as shown in  FIG. 7 , delay circuit  37 A has latch circuit L 71 , latch circuit L 71 A, and switch SW 9 . The latch circuit L 71 A latches digital signal Do 7  in synchronization with the rising edge of clock signal CK 1 . The switch SW 9  selects digital signal Do 7  (output signal of conversion stage ( 20 - 7 )) in normal mode, and it selects the output signal of latch circuit L 71 A in power conservation mode. The latch circuit L 71  latches the signal selected by switch SW 9  in synchronization with the rising edge of clock signal CK 2 . The switch SW 81  and switch SW 82  turn off supply of clock signals CK 1  and CK 2  to latch circuits L 61  and L 62  of delay circuit  36  in power conservation mode. Switch SW 81  inputs clock signal CK 1  to latch circuit L 61  in normal mode, and it inputs a low-level signal instead of clock signal CK 1  in power conservation mode. The switch SW 82  inputs clock signal CK 2  to latch circuit L 62  in normal mode, and it inputs a low-level signal instead of clock signal CK 2  in power conservation mode. 
         [0045]    Switches SW 71  and SW 72  also operate to varying coupling depending on the mode of operation. In power conservation mode, correction circuit  46  stops generating digital signal Do 6 , and the carry signal from the least-significant place is input to correction circuit  45 . That is, switches SW 71  and SW 72  select the carry signal from correction circuit  46  or the most-significant bit of latch circuit L 71  and input it as the carry signal to correction circuit  45 . Switch SW 71  is provided in the path that connects the input of the carry signal of correction circuit  46  and the input of the carry signal of correction circuit  45 , and it is turned off in normal mode and turned on in power conservation mode. Switch SW 72  is provided in the path between output of the carry signal of correction circuit  46  and input of the carry signal of correction circuit  45 , and it is turned on in normal mode and off in power conservation mode. 
         [0046]    Crossbar  90  also operates to varying coupling depending on the mode of operation. Crossbar  90  switches couplings between the output of correction circuit  40  and the input of register  50  corresponding to the operation mode. That is, crossbar  80  inputs the 1 3 -bit output signal of correction circuit  40  as bit signals B 3 -B 15  to register  50  in normal mode, and it inputs the most-significant 11-bit output signal of correction circuit  40  as bit signals B 3 -B 13  to register  50 . In this case, crossbar  90  outputs a low level (value 0) signal to bit signals B 15  and B 14  of register  50 . 
         [0047]    Having thus described the invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.