Abstract:
A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is continuation of U.S. patent application Ser. No. 12/323,283, filed Nov. 25, 2008, now U.S. Pat. No. 7,706,170, which is a continuation of U.S. patent application Ser. No. 11/860,898, filed Sep. 25, 2007, now U.S. Pat. No. 7,457,148, issued Nov. 25, 2008, which is a continuation of U.S. patent application Ser. No. 11/092,288, filed Mar. 29, 2005, now U.S. Pat. No. 7,274,588, issued Sep. 25, 2007, which is a continuation of U.S. patent application Ser. No. 10/657,848, filed Sep. 9, 2003, entitled “Compact and Highly Efficient DRAM Cell, ” now U.S. Pat. No. 6,906,946, issued Jun. 14, 2005, which is a continuation of U.S. patent application Ser. No. 10/128,328, filed Apr. 23, 2003, entitled “Compact and Highly Efficient DRAM Cell, ” now U.S. Pat. No. 6,650,563, issued Nov. 18, 2003, the complete subject matter of all of which is hereby incorporated herein by reference in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     Certain embodiments of the present invention afford an efficient approach for using a compact DRAM cell to reduce the leakage current when storing a data bit in the DRAM cell. In particular, certain embodiments provide a compact DRAM cell having a storage node formed by electrically connecting the drain nodes of two transistors in the DRAM cell. 
     Dynamic RAM is a type of memory that keeps its contents only if supplied with regular clock pulses and a chance to periodically refresh the stored data internally. DRAM is much less expensive than static RAM (which needs no refreshing) and is the type found in most personal computers and other digital applications. 
     DRAM storage cells may be formed from two elements, usually a transistor and a capacitor. A major reduction in storage cell area is achieved with such a configuration. As a result, DRAM is an attractive option for custom and semi-custom chips. 
     Highly integrated System-on-Chip (SOC) implementations require high density and efficient embedded memory. Embedded DRAM memory has the potential to offer high density, low power, and high speed required for state-of-the-art chip designs. Costs associated with integrating embedded DRAM remain a significant factor that slows the integration and adoption of DRAM memory for a wide range of applications including next-generation handsets and high-speed networking. 
     A DRAM cell configuration having high storage capacity and low leakage current that uses generic fabrication processes, requiring no additional masks, is desired. Reducing leakage current maximizes retention time which means reducing the number of times per second a data bit needs to be refreshed in a storage node so the data bit is not lost. The more often the data bits must be refreshed, the higher the required power and the less the dependability of the data bits. 
     Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments of the present invention as set forth in the remainder of the present application with reference to the drawings. 
     BRIEF SUMMARY OF THE INVENTION 
     An embodiment of the present invention provides a compact and highly efficient DRAM cell configuration embedded on an ASIC chip. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip, The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node. 
     A method of the present invention provides the highly efficient use of a compact DRAM cell configuration by reducing leakage current when storing a data bit in the DRAM cell. The method includes writing a data bit to the DRAM cell during a first time segment and storing the data bit during a second time segment. During the second time segment, a transistor disabling reference ground potential is applied to a first gate node of a first transistor of the DRAM cell. A first reference voltage is also applied to a first source node of the first transistor during the second time segment. A second reference voltage is applied to a second gate node of a second transistor during at least a portion of the second time segment. The second reference voltage is more positive than the first reference voltage. The second source node is electrically floating to increase the effective storage capacitance of the storage node of the DRAM cell. 
     Certain embodiments of the present invention afford an efficient approach for using a compact DRAM cell to reduce the leakage current when storing a data bit in the DRAM cell. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram of a DRAM cell configuration in accordance with an embodiment of the present invention. 
         FIG. 1A  illustrates a two-cell layout of the DRAM cell configuration of  FIG. 1  in accordance with an embodiment of the present invention. 
         FIG. 2  is an exemplary timing diagram illustrating a write time segment followed by a store time segment in accordance with an embodiment of the present invention. 
         FIG. 3  is a schematic block diagram illustrating an undesirable read/write state and resultant high leakage storage state of the DRAM cell configuration of  FIG. 1 . 
         FIG. 4  is a schematic block diagram illustrating a first method of writing to the DRAM cell configuration of  FIG. 1  and storing a data bit in accordance with an embodiment of the present invention. 
         FIG. 5  is a schematic block diagram illustrating a second method of writing to the DRAM cell configuration of  FIG. 1  and storing a data bit in accordance with an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is a schematic block diagram of a DRAM cell configuration  5  in accordance with an embodiment of the present invention. The DRAM cell  5  includes a pass transistor  10  and a storage transistor  20 . The pass transistor  10  acts as a pass gate to enable reading and writing of a data bit. A data bit line  14  connects to the source node  11  of the pass transistor  10 . A read/write enable line connects to the gate node  12  of the pass transistor  10 . 
     A storage node  100  is formed by the connection of the drain node  13  of the pass transistor  10  and the drain node  21  of the storage transistor  20 . A bias voltage is applied to the gate node  22  of the storage transistor  20 . The source node  23  of the storage transistor  20  is left floating. The capacitance associated with the storage transistor  20  allows the storage transistor  20  to act as a storage device for a data bit. 
     By sharing the drain nodes between the pass transistor  10  and the storage transistor  20 , the space available for the storage node may be increased when the DRAM cell is implemented on a chip using embedded CMOS technology. As a result, the effective storage capacitance is increased.  FIG. 1A  illustrates a two-cell layout of the DRAM cell configuration of  FIG. 1  in accordance with an embodiment of the present invention. 
     The pass transistor  10  and the storage transistor  20  are field-effect-transistors (FETs). The capacitance provided by the storage FET  20  is due to a junction capacitance of the storage FET  20  and an oxide layer of the floating source node of the storage FET  20 . The two capacitances create an effective storage node capacitance that is used to store a data bit. The sharing of the diffusion of the drain nodes of the two FETs on a CMOS chip allows the effective storage capacitance to be increased. 
       FIG. 2  is an exemplary timing diagram illustrating a write time segment  30  followed by a store time segment  40  in accordance with an embodiment of the present invention. During the write time segment  30 , a data bit is written to the storage node  100  of the DRAM cell. Writing of the data bit is accomplished by applying a data bit voltage to the source node  14  of the pass FET  10 . A read/write-enabling voltage is applied to the gate node  12  of the pass FET  10 , A bias voltage of the same level as the read/write voltage is applied to the gate node  22  of the storage FET  20 . 
     During the store time segment  40 , the gate node  12  is brought to an electrical ground potential to turn off the pass gate  10  after the write time segment when the storage node is charged up. The data bit line  14  is put at a voltage reference level of V DD . A bias voltage is applied to gate node  22  of the storage FET  20  during the store time segment. 
     During the store time segment  40 , a leakage current develops within the cell  5  due to the flow of current from the V DD  potential of the data bit line  14  to the potential of the storage node  100 . When the data bit stored at storage node  100  is a logic “1”, the voltage stored at node  100  is at or very near the V DD  potential. As a result, the potential difference between data bit line  14  and the storage node  100  is small and the leakage current is small and does not significantly affect the stored potential at storage node  100 . 
     However, when the data bit stored is a logic “0”, the leakage current is significantly higher and may charge up the storage node toward a logic “1” potential much more quickly after the logic “0” is written to the cell. For example, when the bias voltage applied to gate node  22  is V DD  during the store time segment  40  and a logic “0” (zero volts) is being stored at storage node  100 , then the leakage current between the data bit line  14  and the storage node  100  may cause the logic “0” potential to charge up to a logic “1” potential in about 1 microsecond. As a result, the logic “0” would have to be written again to the cell, or refreshed, within the 1 microsecond time interval. 
       FIG. 3  illustrates the case where V DD    60  is applied to gate node  22  during both the write time segment  30  and the store time segment  40 . During the write time segment (read/write state of the cell) a voltage level of V DD    60  is applied to gate node  12  to enable pass FET  10 . The logic “0” potential of zero volts  70  on data bit line  14  is written to storage node  100 . Once the logic “0” is written to the cell, the logic “0” potential is stored by disabling the pass FET  10  by applying a ground reference potential V SS    50  of zero volts to the gate node  12 . A reference potential of V DD    60  is applied to data bit line  14 . The potential difference between the data bit line  14  and the storage node  100  is then V DD    60  and the potential difference between the gate node  12  and the storage node  100  is zero. Since the gate node  22  is still at V DD    60 , the storage node  100  tends to charge up quickly, in about 1 microsecond, to a logic “1”, V DD , due to the leakage current through the cell. 
       FIG. 4  illustrates a method, according to an embodiment of the present invention, to increase the time it takes to charge up the storage node by a factor of about  100 , thus reducing the frequency of updating or refreshing the storage node when storing a logic “0”. During the write time segment  30  (read/write state), a read/write enabling voltage V PP    80 , which is more positive than V DD    60 , is applied to the gate node  12  of pass FET  10 . The gate node  22  is also at V PP    80  during the write time segment  30  and is kept at V PP  during the store time segment  40 . The data bit line  14  is again at V DD  during the store time segment  40 . As a result, the voltage stored at the storage node  100  is (V PP −V DD ) and is greater than zero since V PP  is greater than V DD . Therefore, the potential difference between the data bit line  14  and the storage node  100  is (V DD −(V PP −V DD )) which is less than it was in the previous case. 
     The leakage current is reduced as a result of the higher potential of the storage node  100 . Instead of the storage node  100  charging up to a logic “1” in about 1 microsecond, it may now take about 100 microseconds when (V PP −V DD ) is 200 millivolts. Again, the gate node  12  is at a reference ground potential V SS    50  of zero volts during store time segment  40 . The voltage between the gate node  12  and the storage node  100  is −(V PP −V DD )  90 . 
     As one possible alternative, instead of keeping the gate node  22  at V PP    80 , the gate node  22  may be at V DD    60  during the write time segment  30  and pulsed to V PP  during the store time segment  40  as illustrated in  FIG. 5 . A voltage driver  25  is used to provide the voltage pulse from V DD  to V PP  on gate node  22  during the store time segment  40 . During the write time segment  30 , the pass FET  10  is turned on by a read/write voltage which is at a voltage potential of V DD    60 . After the data bit voltage  70  is written to the storage node  100 , the voltage driver  25  pulses the node gate  22  from V DD  to V PP  to create a storage node potential of (V PP −V DD ). As a result, the leakage current is reduced similarly to the case shown in  FIG. 4  and the charge time is again extended to about 100 microseconds from 1 microsecond when (V PP −V DD ) is 200 millivolts. 
     Applying a constant potential of V PP    80  during the write time segment and store time segment is easier to implement and does not require a voltage driver  25 . However, using the voltage driver  25  and pulsing the gate node  22  allows finer control of the leakage current and, therefore, the frequency of storage node updates required. 
     The various elements of the DRAM cell  5  may be combined or separated according to various embodiments of the present invention. For example, the storage FET  20  and the voltage driver  25  may be integrated as a single embedded device or may be implemented as two separate embedded devices that are electrically connected through an embedded trace. 
     In summary, certain embodiments of the present invention afford an approach to obtain system on chip (SOC) integration of high density and efficient embedded memories. Embedded DRAM memories offer high density, low power and high speed required for state-of-the-art chip designs. Leakage currents of embedded DRAM cells are also reduced, increasing memory storage efficiency. 
     While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.