Abstract:
A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional application of a pending US patent application entitled “SEMICONDUCTOR PACKAGE OF SMALL FOOTPRINT WITH A STACK OF LEAD FRAME DIE PADDLE SANDWICHED BETWEEN HIGH-SIDE AND LOW-SIDE MOSFETS AND MANUFACTURING METHOD” by YuPing Gong et al with application Ser. No. 13/302,077, and filing date of Nov. 22, 2011 whose content is hereby incorporated by reference for all purposes. 
     PRIORITY CLAIM 
     This application claims the priority benefit of Chinese patent application number 201110310147.7 filed Sep. 28, 2011, the entire disclosures of which are incorporated herein by reference. 
     FIELD OF THE INVENTION 
     This invention relates to a semiconductor package and its manufacturing method, in particular, of a semiconductor package including high-side (HS) and low-side (LS) semiconductor chips. 
     BACKGROUND OF THE INVENTION 
     In applications of power transistors, for example metal-oxide-semiconductor field effect transistors (MOSFETs), the heat dissipation and package size are two important parameters of the devices. Device&#39;s heat dissipation is improved by exposing the source and/or drain of the transistor, but the implementation process is very complicated. 
     In some switching circuits, such as synchronous buck converter, half-bridge converter and inverter, two power MOSFETs are needed for switching in a complementary manner. The switching circuit as shown in  FIG. 1  includes two MOSFETs, which is HS MOSFET 1 and LS MOSFET 2, connected in series to a voltage source 3, in which, the source of HS MOSFET 1 is connected to the drain of LS MOSFET 2 through a plurality of parasitic inductances such as LDHS, LSHS, LDLS and LSLS. 
     For these devices, when the HS chip and LS chip are co-packaged and two chips are connected by lead wire, the lead inductance is reduced. However, the HS chip and LS chip are arranged side by side on one side of a lead frame, thus the whole device has a large size. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a synchronous buck converter of conventional technology with the source of HS MOSFET electrically connected to drain of LS MOSFET; 
         FIG. 2  is a perspective view of a lead frame of the semiconductor device with co-packaged HS and LS semiconductor chips in this invention; 
         FIG. 3  is a perspective view illustrating the connection between the LS chip and the lead frame of the semiconductor device in this invention; 
         FIG. 4  is a perspective view of the HS chip of the semiconductor device in this invention; 
         FIG. 5  is a perspective view illustrating connection between the HS chip and the lead frame in the semiconductor device in this invention; 
         FIG. 6  is a cross-sectional view of a semiconductor device including LS and HS chips connecting respectively to the lead frame&#39;s upper and bottom surfaces in this invention; 
         FIG. 7  is a perspective view from the front side of the semiconductor device package in this invention; 
         FIG. 8  is a perspective view from back side of the semiconductor device package in this invention; 
         FIG. 9  is a perspective view from the front side of the semiconductor device package with bending pins; 
         FIG. 10  is a perspective view from back side of the semiconductor device package with bending pins; 
         FIG. 11  is a cross-sectional view of the semiconductor device package in this invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Specific embodiments of this invention will be described as follows with illustration drawings. 
     As shown in  FIG. 2  to  FIG. 11 , this invention relates to a semiconductor package including co-packaged HS and LS semiconductor chips and its manufacturing method. 
       FIG. 11  is a cross-sectional schematic diagram of a semiconductor package of a preferred embodiment of the present invention. As shown in  FIG. 11 , the semiconductor package includes a lead frame  100 , a LS chip  200  connected to top side of the lead frame and a HS chip  300  connected to a bottom side of the lead frame  100 . The LS and HS chips  200  and  300  are vertical MOSFET having gate and source located at the top of the chip, while drain located at the bottom of the chip. 
     As shown in  FIG. 2 , the lead frame  100  includes a die paddle  110  and a plurality of pins set around the die paddle  110  and are in the same plane with the die paddle  110  including the first pin  121 , the second pin  122  and the third pin  123  functioning as LS source pin  121 , LS gate pin  122  and HS gate pin  123  respectively and being separated and not electrically connected with the die paddle  110  and the fourth pin  124  being a part of the die paddle  110 , or is an extension of die paddle  110 , functioning as HS drain and LS source pin. 
     As shown in  FIG. 3 ,  FIG. 6  and  FIG. 11 , the backside of the LS chip  200  is attached onto the die paddle  110  of the lead frame  100  to electrically connect its bottom drain onto the top surface of the die paddle  110 . A metal clip  230  (e.g. copper clip) is used for connection between the top source  211  of the LS chip  200  and the first pin  121  of the lead frame  100 . A metal clip  232  is used for connection between the top gate  212  of the LS chip  200  and the second pin  122  of the lead frame  100 . The metal clips  230  and  232  can be replaced with conductive belts, conductive leads or other conductive connectors. In an alternatively embodiment, the top source  211  of the LS chip  200  is electrically connected to the first pin  121  on lead frame  100  via a metal clip, while the top gate  212  of LS chip  200  is electrically connected to the second pin  121  of lead frame  100  via a bonding wire. The metal clips  230  and  232  are connected to the LS chip  200  and pins  121  and  122  by a high temperature alloy  220 . 
     As shown in  FIG. 4 ,  FIG. 5 ,  FIG. 6 , and  FIG. 11 , a plurality of solder balls  311  and  312  are formed correspondingly at gate and source on top of the HS chip  300 . The solder balls can be made from low temperature alloys. A metal layer  320  is formed on backside of the LS chip  300  via evaporation or sputtering of metal composition such as Ti/Ni/Ag (titanium/nickel/silver). Alternatively, a conductive layer  320 ′ is deposited on the backside of the HS chip  300 . The HS chip  300  is attached onto the backside of the lead frame  100 , so that the source balls  311  are electrically connected to the backside of the die paddle  110 , and the gate balls  312  are electrically connected to the third pin  123 . As described above, source of HS chip  300  and drain of LS chip  200  are separately connected to the backside and front side of the die paddle  110  respectively, which are connected with the external devices through the fourth pin  124 . 
     As shown in  FIG. 6  to  FIG. 11 , the LS chip  200 , die paddle  110  of lead frame  100 , and HS chip  300  are co-packaged with a molding compound to form a semiconductor package  400 . The vertical stacked structure of the HS and LS chips and the die paddle reduces the size of the package  400 . At this point, the end part of each of the pins  121 ,  122 ,  123 ,  124  exposed out of the package  400  is bent to the same plane with the backside of device ( FIGS. 9 ,  10  and  11 ). In addition, the metal layer  320  or  320 ′ on back of the HS chip  300  provides the protection for its bottom drain and is exposed out from backside of the device ( FIGS. 8 and 10 ) for electrical connection between the bottom drain of the HS chip  300  and the external devices and for heat dissipation. In a preferred embodiment, metal clip  230 , which connects top source  211  of LS chip  200  and the first pin  121  of lead frame  100 , has a top surface exposed out from the package  400  (not shown) to further improve the heat dissipation of the device. 
     The present invention also proposes a manufacturing method of the semiconductor package  400 . A lead frame  100  made of conductive materials is firstly provided, as shown in  FIG. 2 , which includes a die paddle  110 , first, second, and third pins  121 ,  122 ,  123  separated from the die paddle  110 , and the fourth pin  124  connected to the die paddle  110 . A plurality of LS semiconductor chips  200  are formed on a first semiconductor wafer (not shown), with the gates and sources of all LS chips  200  formed on the front side of the wafer, and drains of all LS chips formed on backside of the semiconductor wafer. Individual LS chips  200  are then singulated from the semiconductor wafer. 
     Similarly, a plurality of HS semiconductor chips  300  are formed on a second semiconductor wafer (not shown) with gates and sources of all HS chips  300  formed on the front side of the wafer and drains of all HS chips formed on backside of the wafer. A plurality of conductive solder balls  311  and  312  are formed correspondingly on source and gate at front side of the HS chip  300 . A metal layer  320  are formed on backside of the HS chip  300 , or the backside of the semiconductor wafer, by evaporation or sputtering of Ti/Ni/Ag (titanium/nickel/silver) or by attaching a conductive metal layer  320 ′ on backside of the HS chip  300 . Individual HS chips are then singulated from the semiconductor wafer. 
     The backside of the LS chip  200  is attached on the front side of the lead frame  100 , as shown in  FIG. 3 , with its bottom drain electrically connected on top surface of the die paddle  110 , for example by an high temperature alloy  220 , while its source and gate electrically connected to the first pin  121  and the second pin  122  of the lead frame respectively via metal clips  230 ,  232  and the high temperature alloy  220 . 
     The HS chip  300  with the solder balls  311 ,  312  is attached on backside of the lead frame  100 , as shown in  FIG. 5 , so that its top source is electrically connected to the bottom surface of the die paddle  110  via the source balls  311  and the its top gate is electrically connected to the third pin  123  of lead frame  100  via the gate balls  312 . 
     The LS chip  200 , die paddle  110  of lead frame  100 , and HS chip  300  are co-packaged with a molding compound to form a semiconductor package  400 , as shown in  FIG. 7  and  FIG. 8 , so that the metal layer  320  or  320 ′ on backside of the HS chip  300  is exposed out of the package  400  for electrical connection between the bottom drain of the HS chip and the external devices and for heat dissipation. In a preferred embodiment, a top surface of the metal clip  230 , which connects top source  211  of LS chip  200  and the first pin  121  of lead frame  100 , is exposed out from the package  400  (not shown) to further improve the heat dissipation of the device. Individual packages  400  are singulated to expose the pins  121 ,  122 ,  123  and  124  out from the package  400 . The end of exposed pins  121 ,  122 ,  123  and  124  are then bent so that the end of exposed pins  121 ,  122 ,  123  and  124  are on the same plane with the backside of the package  400  as shown in  FIGS. 9-11 . 
     The steps of the above method can be implemented in different orders. For example, the HS chip is attached to the backside of the lead frame before the LS chip is attached on the front side of the lead frame. In the semiconductor device in this invention the LS chip and HS chip are vertically stacked at top and bottom sides of the lead frame forming a three-dimensional stacked structure, thus reduces the package&#39;s size compared to the package with side by side arrangement of LS and HS chips on one side of a lead frame in existing technology. In addition, the exposed backside of the HS chip at the back surface of the package improves the heat dissipation. Furthermore, the exposed surface of the metal clip that connects the top source of the LS chip and the lead frame at the package&#39;s top surface further improves the heat dissipation of the device. 
     Although the contents of this invention have been described in detail in the above preferred embodiments, it should be recognized that the above description shall not be considered as a limitation to this invention. After reading the above description by technical personnel in this field, a number of modifications and replacements for this invention will be obvious. Therefore, the scope of protection for this invention shall be subject to the attached claims.