Abstract:
A pipelined oversampling analog-to-digital converter having a first conversion block including inputs for receiving an analog input signal and an analog reference signal, and a plurality of conversion blocks following the first conversion block. Each conversion block includes means for receiving the analog input signal and the analog reference signal, and at least one analog integrator input and at least one digital decimator input from a previous conversion block; a D/A converter having at least one distinct analog output level and an analog input of the analog reference signal; at least one integrator; a quantizer that computes at least one bit as an output; means for combining the output of the quantizer with the at least one digital decimator input; and means for providing an analog output signal output, at least one analog integrator output, and at least one digital decimator output to a following conversion block. A result is generated from the at least one digital decimator output at the last of the conversion blocks.

Description:
PRIORITY INFORMATION 
     This application claims priority from provisional application Ser. No. 60/073,040 filed Jan. 29, 1998. 
    
    
     This invention was made with government support under Contract Number F19628-90-C-0002 awarded by the Air Force. The government has certain rights in the invention. 
    
    
     BACKGROUND OF THE INVENTION 
     The invention relates to the field of A/D converters, and in particular to a pipelined oversampling A/D converter. 
     Oversampled ΔΣ modulation is a technique that is commonly used for implementing high precision analog-to-digital (A/D) converters. It involves converting an analog input into a coarse digital code at a frequency much higher than the Nyquist rate, and then digitally decimating this code to produce a higher resolution, lower data rate result. 
     Single-loop systems, such as that illustrated in FIG. 1, are the simplest example of ΔΣ converters. FIG. 1 is a schematic block diagram of a first order ΔΣA/D converter  100  that includes an analog modulator  102  and a digital decimator  104 . The modulator  102  consists of a discrete-time integrator  106 , a coarse analog-to-digital converter (ADC)  108 , and a coarse digital-to-analog converter (DAC)  110 , connected in a feedback configuration. The ADC and DAC are often 1-bit elements. The modulator&#39;s front end performs analog operations, while its output is digital. The decimator  104  is strictly digital and consists of a lowpass filter  112  followed by a downsampler  114 . 
     The modulator can be analyzed by modeling ideal quantization noise and other sources of non-ideal noise, introduced by the feedforward ADC, as an additive error, e r . The modulator&#39;s output is then described by the difference equation 
     
       
         w r   [n ]=s i   [n −1]+e r   [n ]−e r   [n −1].  (1) 
       
     
     Node w r  contains signal information, unchanged except for a delay, and the 1st-order difference of feedforward ADC quantization noise. 
     FIG. 2 shows the time-domain characteristics of the modulator&#39;s output w r . The duty cycle represents the converter&#39;s average analog input. An input greater than half of the full-scale value results in a stream of digital bits with more 1s than 0s. Although large error is introduced into each value of w r  by the 1-bit quantization shown here, feedback ensures that the average, or duty cycle, of w r  tracks that of the analog input, s i . Similarly, a signal less than half of the full-scale value results in more 0s than 1s. 
     Differentiation of the quantization noise, e r , is one form of noise shaping. A frequency domain representation of this process is illustrated in FIG.  3 . FIG. 3 is a graph of frequency-domain characteristics of ΔΣ modulation. Shaping reduces noise within the signal bandwidth. In this simple model, it is assumed that e r  is uniformly distributed in frequency before it experiences noise shaping. At the modulator&#39;s output, w r  has a z-transform of 
     
       
         W r =S i   ·z   −1 +E r ·(1 −z   −1 ).  (2) 
       
     
     The spectral distribution of e r  is shaped as indicated in FIG.  3 . Quantization noise energy is reduced at low frequencies but is increased at high frequencies. The response of a simple sinc 2  decimation filter is shown in the figure. Input signals are restricted to frequencies within the decimator&#39;s passband, typically a small fraction of the modulator&#39;s total bandwidth. The ratio between modulator sampling frequency and input Nyquist rate is referred to as the oversampling ratio. 
     The modulator&#39;s output, w r , contains input signal components as well as modulation and circuit noise. The decimation filter attenuates its energy outside of the signal bandwidth so that when w r  is resampled at a lower rate, aliasing does not corrupt the signal. Only noise within the signal bandwidth influences the converter&#39;s result. In the final stages of decimation, downsampling converts the filter&#39;s output from a series of low resolution, high frequency words to a series of higher-resolution words at the Nyquist rate. Resolution in the converter&#39;s output words is increased by 9 dB, or 1.5 bits, for every doubling of the oversampling ratio. 
     The 1st-order architecture described above is the simplest example of an oversampling ΔΣ modulator. It contains only a single feedback loop. However, single-loop modulators require large oversampling ratios to achieve high resolution. The need for a large oversampling ratio is alleviated by use of 2nd-order ΔΣ modulation. 
     FIG. 4 is a schematic block diagram of a second order ΔΣ system  400  which includes a modulator  402  and a decimator  404 . The system contains two nested feedback loops within its modulator. The inner loop is similar to that of a 1st-order modulator, with an integrator  406 , a coarse ADC  408 , and a coarse DAC  410 . The outer loop adds a second analog integrator  412 , cascaded with the first integrator, and an outer feedback path. The decimator  404  is also modified to include first  414 , second  416  and third  418  stages of digital accumulation with a downsampler  420 . 
     In this architecture, the modulator&#39;s output has a z-transform of 
     
       
         W r =S i   ·z   −2 +E r ·(1 −z   −1 ) 2 ,  (3) 
       
     
     which contains delayed signal information plus the 2nd-order difference of quantization and other errors in the feedforward path. In comparison to first order, this modulator is capable of greater resolution for the same oversampling ratio because its higher-order noise shaping leaves less noise energy within the signal band. Resolution in the converter&#39;s output word is improved by 15 dB, or 2.5 bits, for every doubling of the oversampling ratio. 
     ΔΣ techniques offer a number of advantages that make them well suited for high-resolution A/D conversion. First, high resolution is achieved despite inaccuracies of internal circuit components such as the ADC. In contrast, component imperfections generally limit non-oversampling architectures to about 12-bit resolution. Second, high resolution is achieved from an ADC with only a few levels and these levels do not require great precision. The ADC in a 1-bit system is particularly simple to implement because it consists of a single comparator. A third advantage is that high resolution is possible from a DAC with only a few levels. Although full resolution is required from the placement of these levels, 1-bit systems are capable of excellent linearity because they contain only two DAC levels and variation in the placement of these does not introduce nonlinearity. A final advantage is that antialias filtering at the converter&#39;s input is simplified because the decimator serves as a digital antialias filter. 
     The advantages of ΔΣ techniques arise through a series of tradeoffs. First, higher accuracy is achieved at the expense of a drastic increase in the number of operations required. The number of operations performed by non-oversampling architectures, such as successive approximation, increases linearly with converter bits, whereas for A) converters it increases exponentially. In a second tradeoff, ΔΣ converters achieve simplicity in their analog circuitry by moving processing complexity into the digital domain. Decimation filters with a flat passband response and a sharp cutoff transition often constitute a majority of the complexity, chip area, and power dissipation of such a device. In a third tradeoff, resolution is improved by a longer decimator impulse response at the expense of increased converter settling time. 
     Finally, ΔΣ techniques include an inherent tradeoff between speed and resolution, whereby these characteristics are not independently adjustable. An increase in the oversampling ratio improves resolution, but reduces the data rate. Similarly, a decrease in the oversampling ratio improves the data rate at the expense of resolution. Data rates are limited because the modulator must operate over many clock cycles to produce a single result. This speed-resolution tradeoff has been the subject of much attention. Data rates are improved by higher-order modulators, but those of greater than second order are susceptible to instability and have increased circuit complexity. Data rates are improved by use of multi-bit quantizers, but their success has been limited by the accuracy required from multi-bit feedback elements. More recently, multi-bit quantizers with single-bit feedback have been used to reduce oversampling ratios, but these devices continue to be limited by a fixed speed-resolution product. 
     SUMMARY OF THE INVENTION 
     Accordingly, the invention provides an analog-to-digital converter having a first conversion block including inputs for receiving an analog input signal and an analog reference signal, and a plurality of conversion blocks following the first conversion block. Each conversion block includes means for receiving the analog input signal and the analog reference signal, and at least one analog integrator input and at least one digital decimator input from a previous conversion block; a D/A converter having at least one distinct analog output level and an analog input of the analog reference signal; at least one integrator; a quantizer that computes at least one bit as an output; means for combining the output of the quantizer with the at least one digital decimator input; and means for providing an analog output signal output, at least one analog integrator output, and at least one digital decimator output to a following conversion block. A result is generated from the at least one digital decimator output at the last of the conversion blocks. 
     In accordance with another embodiment of the invention there is provided an analog-to-digital converter having a first conversion block including an input for receiving an analog input signal and a plurality of conversion blocks following the first conversion block. Each conversion block includes means for receiving the analog input signal, at least one analog integrator input, and at least one digital decimator input from a previous conversion block; at least one digital integrator having an input coupled to the at least one digital decimator input; a multiplying first D/A converter having at least one distinct analog output level and an analog reference input coupled to the analog input signal; a second D/A converter having at least one distinct analog output level and a digital input coupled to the at least one digital decimator input; at least one analog integrator, the first of which has inputs coupled to the output of the first D/A converter and the output of the second D/A converter; a quantizer that computes at least one bit as an output and having an input coupled to the output of the last of the at least one integrator; means for combining the output of the quantizer with the at least one digital decimator input; and means for providing an analog output signal, at least one analog integrator output, and at least one digital decimator output to a following conversion block. A result is generated from the at least one digital decimator output at the last of the conversion blocks. 
     In accordance with yet another embodiment of the invention there is provided an analog-to-digital converter having a first conversion block including an input for receiving an analog input signal and a plurality of conversion blocks following the first conversion block. Each conversion block includes means for receiving the analog input signal, at least one analog integrator input, and at least one digital decimator input from a previous conversion block; at least one digital integrator having an input coupled to the at least one digital decimator input; a multiplying first D/A converter having at least one distinct analog output level and an analog reference input coupled to the analog input signal; a second D/A converter having at least one distinct analog output level and a digital input coupled to the at least one digital decimator input; a quantizer that computes at least one bit as an output and having an input coupled to the output of the first D/A converter and the output of the second D/A converter; means for combining the output of the quantizer with the at least one digital decimator input; and means for providing an analog output signal and at least one digital decimator output to a following conversion block. A result is generated from the at least one digital decimator output at the last of the conversion blocks. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic block diagram of a first order ΔΣ A/D converter; 
     FIG. 2 is a time graph showing the time-domain characteristics of the modulator of FIG. 1 output w r ; 
     FIG. 3 is a graph of frequency-domain characteristics of ΔΣ modulation; 
     FIG. 4 is a schematic block diagram of a second order ΔΣ system; 
     FIG. 5A is a schematic block diagram of a converter having a single modulator and a decimator operating over many clock cycles to produce a train of digital outputs; FIG. 5B is a schematic block diagram of a converter having a pipelined modulator and a pipelined decimator; 
     FIGS. 6A and 6B are graphs comparing signals in time-oversampling and pipelined devices, respectively; 
     FIGS. 7A and 7B are graphs showing sampling of clocked waveforms; 
     FIG. 8 is a schematic block diagram of a time-oversampling converter; 
     FIG. 9 is a schematic block diagram of a POSC utilizing a first order algorithm in cyclic form; 
     FIGS. 10A and 10B are schematic block diagrams of a first order POSC that is a pipelined implementation of the converter of FIG. 9, and an nth block, respectively 
     FIG. 11 is a schematic block diagram of a second order POSC; 
     FIGS. 12A and 12B are schematic block diagrams of a pipelined second order POSC which contains P identical conversion blocks and a nth conversion block, respectively; 
     FIGS. 13A-13C illustrate the transition from a second order analog-integration architecture, such as that in FIG. 11, to a second order architecture with a combination of analog and digital integration; 
     FIG. 14 is a schematic block diagram of a POSC with a configuration which includes two stages of digital integration and no analog integration; and 
     FIGS. 15A and 15B are schematic block diagrams of a second order digital-integration POSC that has a pipeline containing P identical conversion blocks and a n th  stage, respectively. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Pipelining can be applied to oversampling converters to circumvent their speed-resolution tradeoff and its associated limitations. Conventional and pipelined architectures are compared in FIGS. 5A and 5B. FIG. 5A is a schematic block diagram of a converter  500  having a single modulator  502  and a decimator  504  operating over many clock cycles to produce a train of digital outputs. Many of these bits are combined within the decimator to generate a single higher-resolution digital result. Each result in a converter with an oversampling ratio of R requires an additional R clock cycles of operation. This type of operation is referred to hereinafter as time oversampling. 
     The operations performed in FIG. 5A can also be implemented in a pipelined fashion. Such a configuration is shown in FIG.  5 B. 
     FIG. 5B is a schematic block diagram of a converter  506  having a pipelined modulator  508  and a pipelined decimator  510 . The analog input is initially sampled by the first pipeline stage. The modulator&#39;s feedback loop is unraveled into a chain of many stages that operate sequentially on this input sample. The decimator, which is pipelined as well, accepts the modulator&#39;s outputs at each stage. Signals from all pipeline stages are combined in the decimator to produce a result at the end of the pipeline. 
     Since oversampling in a pipelined structure occurs sequentially in space rather than sequentially in time, resolution is determined by the pipeline length. The converter&#39;s data rate is equal to the clock rate at which the pipeline is operated. Since these two parameters are independently adjustable, there is no longer a speed-resolution tradeoff. 
     FIGS. 6A and 6B compare signals in time-oversampling and pipelined devices, respectively. The analog input to a time-oversampling converter is shown in FIG. 6A as a slowly varying sinewave that is sampled at a frequency much greater than its Nyquist rate. Many input samples are collected during the period for one result. A lowpass filter is applied to samples from a longer time interval, equal to the decimator&#39;s impulse response length. The input may vary during each of these intervals, although it can not change rapidly. 
     Lowpass filtering in the decimator for such a device has a number of consequences. First, the decimator serves as a digital antialias filter because noise outside of its passband is suppressed. This noise might already be present on the incoming signal or might arise as a result of sampling at the converter&#39;s input. However, both desirable and undesirable high-frequency components of the input signal are suppressed. FIGS. 7A and 7B are graphs showing sampling of clocked waveforms. FIG. 7A shows that time oversampling is limited by a long settling time, while FIG. 7B shows that pipelined oversampling performs Nyquist sampling. 
     FIG. 7A is an example where lowpass filtering is undesirable. The converter&#39;s presampled input is shown by the upper waveform. Samples of it, indicated by dots, occur during both plateau and transition regions. Since the filter&#39;s impulse response length covers multiple plateau regions, there is a mixing between consecutive outputs. The converter&#39;s output, shown by the lower curve in FIG. 7A, has a long settling time in response to each step transition. When downsampling is performed, the result does not accurately represent the original input. 
     Data flow for a pipelined device is shown in FIG.  6 B. The analog input is shown as a sinewave that is rapidly varying along the time axis. A sequence of samples of this waveform are captured by the first pipeline stage. An additional dimension of space is used to represent position along the pipeline. After each sample is captured, it is passed unchanged along the pipeline and is used by each stage toward computation of a final output. Therefore, from the perspective of the ΔΣ computation, the input is constant. 
     Computationally a pipelined oversampling converter (POSC) is similar to a time-oversampling converter configured as shown in FIG.  8 . FIG. 8 is a schematic block diagram of a time-oversampling converter  800  having a sample-and-hold  802 , a modulator  804  and a decimator  806 . A low frequency clock is used to reset integrators in the modulator, reset memory in the decimator, and perform sampling of an analog input. The sampled input is held constant while the modulator and decimator operate on it over many cycles using a higher frequency clock. The converter&#39;s result is transferred to its output on the next slow clock edge, at the same time that the next phase of resetting and sampling occurs. 
     Each output word from a POSC is generated from a single sample of the incoming analog waveform and is processed independently from its neighbors. As a result, a pipelined device performs Nyquist sampling. FIG. 7B illustrates the operation with presampled signals. The converter&#39;s input, shown by the upper waveform is sampled at the times denoted by dots. One sample is captured during each plateau and each of these is used to compute an output word. There is no mixing between adjacent computations and the converter&#39;s output, shown by the lower waveform, accurately reproduces its input. The benefits of Nyquist sampling in a POSC do, however, come at a price. As with any Nyquist-sampling converter, an analog antialias filter must precede a pipelined converter to prevent high frequency noise from aliasing into the signal passband. 
     A POSC has a number of unique attributes that differentiate its ΔΣ algorithm from that of a time-oversampling device. These include integrator resetting in the modulator, accumulator resetting in the decimator, an input signal that is effectively constant, an input signal whose form is precisely known, and a constrained filter impulse response length. These aspects are described in more detail hereinafter. 
     The POSC architectures in accordance with the invention are based on the 1st-order devices described heretofore with modifications. FIG. 9 is a schematic block diagram of a POSC  900  utilizing a first order algorithm in cyclic form. The converter  900  includes a modulator  902  and a decimator  904 . Initially, the integrator i 1  is replaced with first  906  and second  908  integrators, u 1  and v 1 . The modulator also includes a coarse ADC  910  and a coarse DAC  912  in a feedback loop. 
     Each accumulator loop in the decimator  904  is modified to include a delay  914  in its feedforward path, in addition to first  916  and second  918  accumulators and a downsampler  920 . This configuration is more appropriate for a pipelined implementation where each operation occupies one pipeline stage. 
     An incoming analog signal is sampled at the converter&#39;s input, where n=0. S g  is a constant equal to the value of this sample and the modulator&#39;s input sequence, s i , is equal to 
     
       
         s i   [n ]=S g ·u[ n],   (4) 
       
     
     where u[n] is a unit step function. Integrator  906  (u 1 ) integrates signal information, via s i , and integrator  908  (v 1 ) integrates feedback information, via feedback f b . The difference between their values is similar to the integrated quantity i 1  of FIG.  1 . However, as shown, this configuration is single-ended, not differential, and u 1  and v 1  are not a differential pair. 
     All integrators are preset to zero at time n=0, and their values at cycle n are given by                        u   1          [   n   ]       =     {         0           for                 n     ≤   0                   u   1          [     n   -   1     ]       +       s   i          [     n   -   1     ]                 for                 n     ≥   1                             v   1          [   n   ]       =     {         0           for                 n     ≤   0                   v   1          [     n   -   1     ]       +       f   b          [     n   -   1     ]                 for                 n     ≥   1                           (   5   )                                
     The value of integrator  906  (u 1 ) increases linearly with time because S g  is unconditionally added to it each cycle. Feedback ensures that u 1  and v 1  coarsely track each other, so v 1  increases with the same slope. 
     The coarse ADC  910  with a full-scale value of reference R f  (same for all stages) generates an r-bit digital representation                  w   r          [   n   ]       =         1     R   f            (         u   1          [   n   ]       -       v   1          [   n   ]         )       +       e   r          [   n   ]                 (   6   )                                
     of the difference between u 1  and v 1 . The expression for w r  contains an error term, e r , that is due to r-bit quantization as well as circuit inaccuracies in the coarse ADC. As defined in equation (6), e r  is normalized to the full scale. 
     The k most significant bits of w r  are used to form the modulator&#39;s first output and its feedback value                  w   k          [   n   ]       =         1     R   f            (         u   1          [   n   ]       -       v   1          [   n   ]         )       +       e   r          [   n   ]       -         t   k          [   n   ]       .               (   7   )                                
     This signal contains an additional error term, t k , that is due to truncating an r-bit word to k bits. In contrast to error e r , error t k  is a known quantity and can be compensated for in downstream digital processing. It is provided as an input to the decimator for this purpose. Errors e r  and t k  are both zero for n&lt;1 since no comparisons occur during this time. 
     Node w k , is supplied to the feedback DAC  912  with a full-scale value of R f  that generates a corresponding analog quantity 
     
       
         f b   [n ]=u 1   [n ]−v 1   [n ]+R f ·(e r   [n ]−t v   [n ]).  (8) 
       
     
     Node w r  represents the difference u 1 −v 1  quantized with 5-bit resolution. Node f b  is a 2-bit representation of w r  and is always smaller than it as a result of truncation. Since the average of f b  approximates the value of S g , the average of w r  is always greater than or equal to S g . 
     Solving equations (5), (7), and (8) recursively yields a time-domain and frequency-domain modulator output of                        w   k          [   n   ]       =           S   g       R   f       ·     u        [     n   -   1     ]         +     (         e   r          [   n   ]       -       e   r          [     n   -   1     ]         )     -     (         t   k          [   n   ]       -       t   k          [     n   -   1     ]         )                       W   k          (   z   )       =           S   g       R   f       ·       z     -   1         (     1   -     z     -   1         )         +       (       E   r     -     T   k       )     ·     (     1   -     z     -   1         )                       (   9   )                                
     Signal w k  contains a delayed version of the input sample plus the 1st-order difference of errors e r  and t k . 
     The decimator&#39;s purpose is to amplify signal information and attenuate quantization noise in the modulator&#39;s digital output. One example of such a decimator is shown in FIG.  9 . The decimator&#39;s  904  first stage accumulates w k  according to                  d   1          [   n   ]       =     {           0           for                 n     ≤   1                   d   1          [     n   -   1     ]       +       w   k          [     n   -   1     ]                 for                 n     ≥   2           .               (   10   )                                
     Solving equations (9) and (10) yields the response                  d   1     =           S   g       R   f       ·     (     n   -   1     )     ·     u        [     n   -   1     ]         +     (         e   r          [     n   -   1     ]       -       t   k          [     n   -   1     ]         )         ,           (   11   )                                
     containing signal information that increases linearly with n at a rate of S g /R f , and unamplified error that has a constant mean-square value. 
     Truncation error is digitally corrected after the first accumulator  916  by adding t k  to d 1 . 
     The result,                    d   k          [   n   ]       =           S   g       R   f       ·     (     n   -   1     )     ·     u        [     n   -   1     ]         +       e   r          [     n   -   1     ]           ,           (   12   )                                
     represents the number of times R f  was added to the first integrator  906  (v 1 ) over the previous n−1 cycles. Equation (12) could be used directly to reconstruct the input sample, S g . However, better resolution is achieved from a second stage of accumulation. The accumulated result                  d   2          [   n   ]       =     {         0           for                 n     ≤   2                   d   2          [     n   -   1     ]       +       d   k          [     n   -   1     ]                 for                 n     ≥   3                     (   13   )                                
     has a value at time n of                  d   2          [   n   ]       =           S   g       2   ·     R   f              (     n   -   2     )            (     n   -   1     )     ·     u        [     n   -   2     ]           +       ∑     i   =   1       n   -   2                         e   r          [   i   ]                   (14a)                                
     and a corresponding z transform of                D   2     =           S   g       R   f       ·       z     -   3           (     1   -     z     -   1         )     3         +       (       E   r     -     T   k       )              z     -   2         (     1   -     z     -   1         )       .                 (14b)                                
     Signal information in d 2  is amplified as n 2  while the quantization noise term increases more slowly as {square root over (n)}. The value of d 2  is independent of both truncation error t k  and of the number of feedback bits k. It does, however, depend on the number of ADC bits, r, because this determines the mean-square value of e r . This configuration is referred to hereafter as an error-averaging decimator because the final term in equation (14a) contains an average of e r . 
     The input sample is easily reconstructed from d 2 . Since the sequence s i  is constant, equations (14a) and (14b) can be solved directly for S g  in terms of d 2  and n. The quantization noise term is assumed to be negligible. For a P-stage pipeline, the final value of d 2  is completed at time n=P+2 and reconstruction is given by                S   g     ≈         d   2          [     P   +   2     ]       ·       (       2        R   f           P   2     +   P       )     .               (   15   )                                
     Equation (15) has a particularly simple implementation if the pipeline length P is chosen so that the term P 2 +P is a power of two. In this case, the result is identically equal to d 2  with a change in significance of its bits. Alternatively, the term P 2 +P, which only impacts converter gain, could be treated as part of the full-scale value. 
     The term “pipeline stage” is used heretofore to describe both the hardware comprising one feedback operation and the hardware exercised during one clock period. This terminology must be modified here because the pipelined structures used to implement a POSC often utilize multiple clock cycles to perform one feedback operation. To differentiate between these, the former is referred to as a “conversion block” and the latter is referred to as a “stage”. Using this convention, a conversion block might contain multiple stages. 
     FIGS. 10A and 10B are schematic block diagrams of a first order POSC  1000  that is a pipelined implementation of the converter  900  of FIG. 9, and an nth block  1002 , respectively. The pipeline in FIG. 10A contains P conversion blocks  1004 (1)- 1004 (P). Two analog channels, a signal channel  1006  (s i ) and an integrator channel  1008  (i 1 ), flow through the pipeline and include respective delays  1010  and  1012 . The integrator channel  1008  also includes an integrator  1013  Two digital channels, a first decimator channel  1014  (d 1 ) and a second decimator channel  1016  (d 2 ), carry decimator signals. The decimator channels include respective delays  1018  and  1020 . 
     Before the first conversion block, the states of i 1 , d 1 , and d 2  are all set to zero. The converter&#39;s analog input is sampled by the first block and is passed unchanged along the pipeline. The converter&#39;s final result is generated by normalizing d 2  from the last block using equation (3-15). Multiple input samples are processed in parallel along the pipeline so that a new digital word is completed at each clock cycle. 
     The contents of a single conversion block are shown schematically in FIG.  10 B. Subscripts of n are used to denote outputs from the nth block. Each element labeled D performs delay and latching operations. An ADC  1022  is a coarse r-bit A/D converter, with a full-scale reference of R f , that is implemented using a non-oversampling architecture such as one-bit-per-stage successive approximation. The ADC  1022  operates as a quantizer as implemented. A DAC  1024  represents a coarse k-bit D/A converter, with a full-scale reference R f , which is also implemented using a non-oversampling architecture. 
     Each block accepts a feedback signal w k  from its predecessor and generates a corresponding analog quantity that is subtracted from the delayed input sample, s i . The result, after subtraction, is added to integrator  1013 . An r-bit quantized representation of this integrator&#39;s value is divided into upper and lower bits. The k upper bits form the feedback signal w k . These are added to the first decimator channel  1014  and are passed forward to the next block via delay  1026 . The only digital signal from block n that is needed by block n+1 is w k . Signals d 1  and d 2  are not needed until the pipeline&#39;s end, and their computations can, therefore, be reordered or spread across multiple conversion blocks. An example of this is shown in FIG.  10 B. The delay shown in FIG. 9 for t k  is eliminated and t k  is added directly to d 2 . At the completion of these operations all results are passed forward to a subsequent conversion block. 
     The configuration in FIG. 10B is not well suited for high-speed operation because each conversion block contains only one delay. All of its operations, including D/A conversion, addition, subtraction, and A/D conversion, must be completed within a single clock period. Speed is improved if each conversion block is divided into multiple pipeline stages, with fewer operations per stage, so that a higher frequency clock can be used. Each feedback operation is then allowed multiple clock cycles to complete. Latency is increased but throughput remains one result per cycle. 
     The first order POSC architecture can be modified as shown in FIG. 11 to accommodate second order modulation. FIG. 11 is a schematic block diagram of a second order POSC  1100 . The POSC  1100  includes a modulator  1102  and a decimator  1104 . The configuration shown here differs from the time-oversampling configuration of FIG. 4 in three ways. First, integrators i 1  and i 2  are replaced with pairs of integrators, u 1 /v 1  and u 2 /v 2 . Integrators  1106  and  1108  are in the analog signal channel and integrators  1110  and  1112  are in a feedback loop. Second, all integrators and accumulators are modified to include a delay in their feedforward paths. This configuration is more appropriate for a pipelined implementation where each operation occupies one stage. Third, a gain of two unit  1114  is added into the inner loop&#39;s feedback path to compensate for the additional delay from f b  to v 1 . Algorithms are illustrated using a cyclic configuration. 
     The analysis parallels that for first order modulation. The converter&#39;s input samples an incoming analog signal. S g  is a constant equal to the value of this sample. The input to the ΔΣ algorithm, s i , equals 
     
       
         s i   [n ]=S g ·u[ n],   (16) 
       
     
     where u[n] is a unit step function. Integrators  1106  (u 1 ) and  1108  (u 2 ) accumulate signal information via s i , and integrators  1110  (v 1 ) and  1112  (v 2 ) accumulate feedback information via f b . The difference between their values is similar to integrated quantities i 1  and i 2  of FIG.  4 . 
     The modulator&#39;s first and second integrators are preset to zero at time n=0 and their values at cycle n are given by                  u   1          [   n   ]       =     {             0           for                 n     ≤   0                   u   i          [     n   -   1     ]       +       s   i          [     n   -   1     ]                 for                 n     ≥   1                             v   1          [   n   ]         =     {         0           for                 n     ≤   0                   v   1          [     n   -   1     ]       +       f   b          [     n   -   1     ]                 for                 n     ≥   1                         (   17   )             and                                     u   2          [   n   ]       =     {         0           for                 n     ≤   1                   u   2          [     n   -   1     ]       +       u   1          [     n   -   1     ]                 for                 n     ≥   2                                        v   2          [   n   ]       =     {         0           for                 n     ≤   1                   v   2          [     n   -   1     ]       +       v   1          [     n   -   1     ]       +     2          f   b          [     n   -   1     ]                   for                 n     ≥   2                     .           (   18   )                                
     The values of u 1  and u 2  increase linearly and quadratically with time. Feedback ensures that v 1  tracks u 1  and v 2  tracks u 2 . 
     A coarse ADC  1116  with a full-scale value of R f  generates an r-bit digital representation                  w   r          [   n   ]       =       1   Rf          (         u   2          [   n   ]       -       v   2          [   n   ]       +       e   r          [   n   ]         )               (   19   )                                
     of the difference between u 2  and v 2 . The error term, e r , in this signal is due to r-bit quantization noise as well as circuit inaccuracies in the coarse ADC. 
     The modulator&#39;s first output and its feedback value,                    w   k          [   n   ]       =         1     R   f            (         u   2          [   n   ]       -       v   2          [   n   ]         )       +       e   r          [   n   ]       -       t   k          [   n   ]           ,           (   20   )                                
     consists of the k most significant bits of w r . The additional term, t k , results from truncating an r-bit word to k bits and can be digitally corrected for downstream in the decimator. Errors e r  and t k  are zero for n&lt;1 since no comparisons occur during this time. 
     Node w k , is supplied to a feedback DAC  1118  with a full-scale value of R f  that generates a corresponding analog quantity 
     
       
         f b   [n ]=u 2   [n ]−v 2   [n ]+(e r   [n ]−t k   [n ])·R f .  (21) 
       
     
     An iterative solution of equations (17), (18), (20) and (21) yields a time-domain modulator output of                  w   k          [   n   ]       =           S   g       R   f       ·     u        [     n   -   2     ]         +     (         e   r          [   n   ]       -     2          e   r          [     n   -   1     ]         +       e   r          [     n   -   2     ]         )     +     (         t   k          [   n   ]       -     2          t   k          [     n   -   1     ]         +       t   k          [     n   -   2     ]         )               (22a)                                
     and a z transform of                  W   k          (   z   )       =           S   g       R   f       ·       (       z     -   2       -     z       -   P     -   2         )       1   -     z     -   1             +       (       E   r     -     T   k       )              (     1   -     z     -   1         )     2     .                 (22b)                                
     This signal contains a delayed version of the input sample, plus the second order difference of errors e r  and t k . 
     The decimator  1104  includes a feedforward path having delays  1120  and  1122 . The signal path includes first  1124 , second  1126  and third  1128  accumulators, and a downsampler  1130 . The decimator  1104  processes the modulator&#39;s output, w k , to amplify signal information and attenuate quantization noise. The first and second accumulators are given by                                d   1          [   n   ]       =     {         0           for                 n     ≤   2                   d   1          [     n   -   1     ]       +       w   k          [     n   -   1     ]                 for                 n     ≥   3                             d   2          [   n   ]       =     {         0           for                 n     ≤   3                   d   2          [     n   -   1     ]       +       d   1          [     n   -   1     ]                 for                 n     ≥   4                           .           (   23   )                                
     Solving equations (20) and (23) yields responses of                  d   1          [   n   ]       =           S   g       R   f              (     n   -   2     )     ·     u        [     n   -   2     ]           +     (         e   r          [     n   -   1     ]       -       e   r          [     n   -   2     ]         )     -     (         t   k          [     n   -   1     ]       -       t   k          [     n   -   2     ]         )               (   24   )                                
     and                  d   2          [   n   ]       =           S   g       2        R   f              (     n   -   3     )            (     n   -   2     )     ·     u        [     n   -   3     ]           +       e   r          [     n   -   2     ]       -         t   k          [     n   -   2     ]       .               (   25   )                                
     Signals d 1  and d 2  track u 1  and u 2 . They increase linearly and quadratically with n at a rate of S g /R f . Error terms e r  and t k , which were differentiated at the decimator&#39;s input, are restored to their original form, with a constant mean-square value, by point d 2 . 
     Truncation error is digitally removed from the second accumulator&#39;s  1126  output,                  d   k          [   n   ]       =           S   g       2        R   f              (     n   -   3     )            (     n   -   2     )     ·     u        [     n   -   3     ]           +         e   r          [     n   -   2     ]       .               (   26   )                                
     The final accumulator has a value at time n of                  d   3          [   n   ]       =     {         0           for                 n     ≤   4                   d   3          [     n   -   1     ]       +       d   k          [     n   -   1     ]                 for                 n     ≥   5                     (   27   )                                
     and a resulting time and frequency response of                        d   3          [   n   ]       =           S   g       6        R   f              (     n   -   4     )          (     n   -   3     )            (     n   -   2     )     ·     u        [     n   -   4     ]           +       ∑     i   =   2       n   -   3                         e   r          [   i   ]                           D   3          (   z   )       =           S   g       R   f       ·       (       z     -   5       -     z       -   P     -   5         )         (     1   -     z     -   1         )     4         +       E   r     ·         z     -   3         (     1   -     z     -   1         )       .                       (   28   )                                
     The value of d 3  is independent of both truncation error, t k , and the number of feedback bits, k. However, it does depend on the number of ADC bits, r, since this determines the mean-square value of e r . Like the decimator  904  of FIG. 9, this configuration is referred to as an error-averaging decimator because the last term in equation (28) contains an average of e r . This is a general aspect of configurations in which the decimator order is one greater than that of the modulator. 
     The converter&#39;s input sample can be easily reconstructed from d 3  because the sequence S i  is known to be constant along the pipeline. Equation (28), evaluated at n=P+4, can be solved directly for S g  in terms of d 3  and P, under the assumption that its quantization noise term is negligible. Reconstruction is given by                S   g     ≈         d   3          [     P   +   4     ]       ·       (       6        R   f           P   3     +     3        P   2       +     2      P         )     .               (   29   )                                
     Equation (29) has a particularly simple implementation if the factor multiplying d 3  is chosen as a power of two. In this case the result is identically equal to d 3  with a change in significance of its bits. Alternatively, this factor, which only impacts overall converter gain, could be treated as part of the full-scale reference. 
     A pipelined implementation of the POSC  1100  of FIG. 11 is shown in FIGS. 12A and 12B. FIG. 12A is a schematic block diagram of a pipelined second order POSC  1200  which contains P identical conversion blocks  1202 (1)- 1202 (P). FIG. 12B is a schematic block diagram of the nth conversion block  1204 . Each conversion block includes three analog channels,  1206  (s i ),  1208  (i 1 ), and  1210  (i 2 ) that flow through the pipeline. Three digital channels,  1212  (d 1 ),  1214  (d 2 ), and  1216  (d 3 ) that carry decimator signals. Inputs to all integrators and accumulators are zero. The converter&#39;s analog input is sampled before the first pipeline stage. The result is passed along the pipeline and used in each stage as part of ΔΣ computations, but it is never altered. The converter&#39;s output word is generated by the last stage. Multiple input samples are processed in parallel along the pipeline so that one digital word is completed each clock cycle. 
     The integrated quantity i 1 , from the previous stage, is added to integrator  1218 . The digital feedback signal w k . is used by a DAC  1220 , with a full-scale value of R f , to generate an analog quantity, f b . This value is subtracted twice from i 2  with integrator  1222  and once from i 1  by integrator  1224 . At the same time, the delayed input sample, s i  is added to i 1  by integrator  1224 . An r-bit ADC  1226  with a full-scale value of R f  quantizes the newly modified value of i 2 . The k upper bits of the ADC&#39;s result form w k , the output from this stage. Decimator signals are updated as shown in the figure. The only digital signal from block n that is needed by block n+1 is w k . The computations for d 1 , d 2 , and d 3  can be spread across multiple stages since these signals are not needed until the pipeline&#39;s end. As shown, t k  is added directly to d 3 , without delays being present. The final result is not impacted by these delays. Finally, all signals are passed on to the following stage and the process is repeated. The converter&#39;s result is generated by normalizing d 3  from the last stage using equation (29). 
     The second order architecture described heretofore includes two stages of cascaded analog integration. Alternatively, one or both of these integration operations may be performed digitally. FIGS. 13A-13C illustrate the transition from a second order analog-integration architecture, such as that in FIG. 11, to a second order architecture with a combination of analog and digital integration. FIG. 13A is a schematic block diagram of a POSC  1300  having a modulator  1302  and a decimator  1304  that differs from the POSC  1100  of FIG. 11 in that the DAC  1306  is repositioned. It was originally located before v 1 , but now is positioned between v 1  and v 2 . To balance signal and reference paths, a second DAC  1308  is also placed within the upper path, between u 1  and u 2 . In this configuration, u 1  and v 1  are digital values. Analog quantities S g  and R f  enter the converter through the DAC full-scale references. 
     The transition from POSC  1300  to POSC  1310  of FIG. 13B is based on the fact that integrators for u 1  and v 1  are redundant. They can be removed to reduce hardware and power, without altering the ΔΣ algorithm. Node v 1  may be replaced by d 1  since the values of these two signals are identical. Node u 1  may be replaced with the fixed expression (n)u[n], since this signal is a function of pipeline stage, but is independent of the converter&#39;s input sample. The schematic block diagram of POSC  1312  of FIG. 13C differs from that in FIG. 13B in that u 2  and v 2  are combined into a single integrator i 2 . 
     The configuration in FIG. 13C is referred to as a digital-integration architecture. Other varieties of digital-integration architectures are possible as well. For example, FIG. 14 is a schematic block diagram of a POSC  1400  with a modulator  1402  and a decimator  1404 . The POSC  1400  has a configuration which includes two stages of digital integration and no analog integration. The only analog operations in this converter are sampling, subtraction, D/A conversion, and coarse A/D conversion. 
     Digital-integration and analog-integration architectures are algorithmically equivalent. The differences between these approaches lie in their implementations. The upper DAC  1406  has a digital input that is a function of pipeline stage and an analog input equal to the converter&#39;s input sample. It generates a signal                  i   2          [   n   ]       =     {         0                 i   2          [     n   -   1     ]       +       u   1          [     n   -   1     ]       -       v   1          [     n   -   1     ]                         (   30   )                                
     equal to the product of these inputs. The result is similar to u 1  in FIG.  11 . The lower DAC  1408  has a digital input that is signal dependent and an analog input that is constant. It generates a signal 
     
       
         v 1 [ n ]=R·(d 1   [n ]+2w k   [n ]),  (31) 
       
     
     whose value is similar to v 1  in FIG.  11 . It represents the modulator&#39;s prediction of the value of u 1 . 
     The difference between u 1  and v 1  is combined in the analog integrator according to                  i   2          [   n   ]       =     {           0           for                 n     ≤   1                   i   2          [     n   -   1     ]       +       u   1          [     n   -   1     ]       -       v   1          [     n   -   1     ]                 for                 n     ≥   2           .               (   32   )                                
     The modulator&#39;s feedback operates to keep the value in this integrator small so that it may be quantized using only a few bits. An r-bit ADC  1410  with a full-scale value of R f  generates a digital representation of i 2 . The result,                    w   r          [   n   ]       =         1     R   f       ·       i   2          [   n   ]         +       e   r          [   n   ]           ,           (   33   )                                
     contains quantization noise, e r . The k most significant bits of this signal form the feedback quantity                  w   k          [   n   ]       =         1     R   f       ·       i   2          [   n   ]         +       e   r          [   n   ]       -         t   k          [   n   ]       .               (   34   )                                
     An expression for the modulator&#39;s output is arrived at by iteratively solving equations (30), (31), (32) and (34). The resulting expression,                    w   k          [   n   ]       =           S   g       R   f       ·     u        [     n   -   2     ]         +     (         e   r          [   n   ]       -     2          e   r          [     n   -   1     ]         +       e   r          [     n   -   2     ]         )     +     (         t   k          [   n   ]       -     2          t   k          [     n   -   1     ]         +       t   k          [     n   -   2     ]         )         ,           (   35   )                                
     is identical to that previously derived for an analog integration architecture in equation (22). Decimator operation is identical to that described for analog integration and is not repeated here. 
     A pipelined implementation of the digital-integration architecture in FIG. 13C is shown in FIGS. 15A and 15B. FIG. 15A is a schematic block diagram of a second order digital-integration POSC  1500  that has a pipeline containing P identical conversion blocks  1502 (1)- 1502 (P). The pipeline in FIG.  15 A( a ) differs from that of analog integration in that it has only two analog channels,  1506  (s i ) and  1508  (i 2 ) that flow through the pipeline, and first  1518 , second  1520  and third  1522  decimator channels. 
     FIG. 15B is a schematic block diagram of the n th  stage  1504 . An incoming digital feedback signal, f b , is used by a DAC  1510  with a full-scale value of R f  to generate an analog quantity that is subtracted from i 2  by integrator. At the same time, the delayed input sample, s i , is provided as a full-scale reference to a DAC  1514  with a digital input of n, and the result is added to i 2 . An r-bit ADC  1516  with a full-scale value of R f  quantizes the newly modified value of i 2 . The k upper bits of the ADC&#39;s result are combined with the first decimator value d 1  to generate the feedback output from this stage. Decimator signals are updated in the same way as those for an analog-integration architecture. Finally, all signals are passed on to the following stage and the process is repeated. The converter&#39;s result is generated by normalizing d 3  from the last stage using equation (3-52). 
     Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.