Abstract:
A current-mode analog-to-digital (IADC) has subnA sensitivity. An IADC cell receives an input current signal and provides an output to a comparator for comparison with an adjustable input reference signal. A digital output signal is generated and an analog output is provided to the next cell.

Description:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH 
   This invention was made with government support under Grant No. F49620-02-C-0041, awarded by the United States Air Force Office of Scientific Research and under Grant No. 5-R01-HL072849-04, awarded by the National Institutes of Health. The government has certain rights in this invention. 

   CROSS REFERENCE TO RELATED APPLICATIONS 
   Not applicable. 
   BACKGROUND 
   As is known in the art, analog-to-digital converters (ADCs) convert a signal in analog format to a signal in digital format. Conventional ADC circuits can have a variety of circuit architectures each of which has certain concomitant disadvantages. Known ADC architectures include pipeline, sigma-delta, cyclic, flash, successive approximation, and dual-slope. Each ADC architecture is generally applicable to a limited operating range. That is, each of these architectures has strengths and weaknesses that make them more amenable to working in certain frequency and resolution ranges. 
   Some ADC architectures do not operate outside certain ranges or consume prohibitively high power in certain ranges as compared to other architectures. Even within preferred operating ranges, a given architecture can have a performance level that is dictated by certain circuit parameters that are fixed for a given design. 
   High-performance analog-to-digital converters (ADCs) are generally optimized for conversion speed and resolution with a given size and power budget. In CMOS-based mobile biochemical sensor application, however, speed and resolution are immaterial because of the slow reaction rates (&gt;seconds) and inherent experimental errors (˜10%) typical of most biochemical reactions. Instead, ADC sensitivity, power consumption and size may be of greater interest. 
   In one known attempt to apply ADCs to biochemical reactions, to convert sub-nA level photo currents into voltage, the input signal is amplified using large-gain (10 6 ) current mirrors, increasing power and area requirements and the current mirror&#39;s susceptibility to mismatch errors for a given chip area, as disclosed in U. Lu, Hu, B. C-P., Shih, Y-C., Wu, C-Y, and Yang, Y-S, “The design of a novel complementary metal oxide semiconductor detection system for biochemical luminescence,”  Biosensors and Bioelectronics , vol. 19, pp. 1185-1191, 2004, which is incorporated herein by reference. 
   In M. Simpson, Sayler, G, Patterson, G, Nivens, E, Bolton, E., Rochells, J., Arnott, J, Applegate, B., Ripp, S., and Guillom, M., “An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit,”  Sensors and Actuators B , vol. 72, pp. 134-140, 2002, which is incorporated herein by reference, increased ADC sensitivity was achieved by successive capacitive integration and voltage-to-frequency conversion at the expense of increased power consumption and long conversion time (˜ seconds). 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The exemplary embodiments contained herein will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a circuit diagram of an exemplary ADC unit cell in accordance with the present invention; 
       FIG. 2  is a block diagram of an ADC having cells coupled together; 
       FIG. 3  is a circuit diagram of a further exemplary ADC unit cell in accordance with the present invention; 
       FIG. 4  is a block diagram of a further ADC having cells coupled together; 
       FIG. 5  is a circuit diagram of an ADC unit cell having scaling of a reference signal; 
       FIG. 5A  is a block diagram of another ADC having cells coupled together; 
       FIG. 6  is a graphical depiction of simulation results for a 4-cell ADC in accordance with the present invention; and 
       FIGS. 7A and 7B  are graphical depictions of simulated and fabricated responses respectively, for an ADC in accordance with the present invention. 
   

   DETAILED DESCRIPTION 
   In general, the inventive current-mode analog-to-digital converter has a structure that provides sub-nA sensitivity. Due to low-voltage low-power and small-size capabilities, the inventive ADC (Analog-to-Digital Converter) is well-suited for portable chemical or biosensor applications, for example. As will be readily understood by one skilled in the art, CMOS (Complementary Metal-Oxide Semiconductor)-based integrated biochemical sensors generate photo currents at sub-nanoampere (nA) levels, which present a challenge for digital data acquisition. 
   The inventive current-mode ADC (IADC) is capable of digitizing photo currents, for example, at a speed and resolution commensurate with such applications. In one embodiment, the IADC operates at a supply voltage (V DD ) as low as about 1.2V, contains no capacitors or clocks, and can be directly integrated alongside the CMOS photodiode in well known fabrication processes. 
     FIG. 1  shows an exemplary IADC cell  100  in accordance with the present invention. Cells n=1, 2, . . . N are cascaded with the analog output of one cell connected to the analog input of the following cell, as shown and described in  FIG. 2 . The analog input I IN (n) into cell n is scaled using a 1:k n  scaling circuit  102 . In an exemplary embodiment, the scaling circuit  102  includes a current mirror having transistor Q 1 . A comparator  104  includes switches Q 5 -Q 8  coupled as shown providing a digital output signal D O (n). The output signal D O (n) is a logical HI if k n ·I IN (n) is greater than a user-defined reference current I REF . Otherwise the cell output signal Do(n) is a logical LO. 
   To ensure operation in the sub-nanoAmpere range, transmission switches gated by D O (n) included in some prior art configurations, are eliminated in order to avoid large switching current artifacts that may disrupt the signal conversion process. D. G. Naim, and Salama, A., “Current-mode algorithmic analog to digital converter,” IEEE Journal of Solid State Circuits, vol. 25, pp. 997-1004, 1991, which is incorporated herein by reference, is an example of a prior art ADC having a transmission switch gated by a digital output signal. 
   Due to the switch elimination in the inventive ADC cell, the input current (I IN (n+1)=k n ·I IN (n)−I REF ) into the next cell via a subtraction circuit  106 , which includes current subtraction transistors Q 2 , Q 3 , is no longer dependent on the comparator  104  output signal D O (n). That is, the analog current signal A O (n) passed to the next cell (n+1) is independent from the digital output. This flash-type architecture increases the conversion speed for given operating conditions 
   As is known in the art, traditional flash architecture generates a thermometer code according to a voltage divider sequence. In contrast, in the inventive IADC the 1:k n  scaling of input current I IN  in each cell  100  provides an equivalent current divider sequence [1−(k 1 ·k 2  . . . k n ) −1 ], n=1, 2 . . . N, for the range I REF /k 1 ≦I IN (1) ≦I REF , where I IN (1) is the current input to the IADC, and k 1  is the mirror ratio of n=1. When k n ·I IN (n)&lt;I REF  for cell n, the inputs to all subsequent cells are zero so that D O (n:N) is a logical LO. Thus the analog input is quantized by the largest value of n such that D O (n) is a logical HI. 
   Where conventional IADC designs allow high-speed conversion down to the μA range by biasing the transistors in the strong-inversion (above-threshold) regime, sub-nA sensitivity is achieved in exemplary embodiments of the inventive ADC. In addition, a relatively low supply voltage V DD , e.g., about 1.2V can be used. 
     FIG. 2  shows an exemplary IADC  200  having a series of cascaded cells  202   a - d , which can be provided as the cell  100  of  FIG. 1 . An input current signal I IN (1) along with a reference current I REF  is provided to the first cell  202   a , which produces a first digital output signal D O (n1). An analog output signal A O (n1), i.e., ((I IN (2)=k 1 ·I IN (1)−I REF ), is provided by the first cell  202   a  to the analog input of the second cell  202   b , which generates a second digital output signal D O (n2), and so on. 
   As noted above, when k n ·I IN (n)&lt;I REF  for cell n, the inputs to all subsequent cells are zero so that D O (n:N) is a logical LO. The cell digital output signal D O (n) is a logical HI if k n ·I IN (n) is greater than the user-defined reference current I REF . 
   In some conventional designs, such as D. G. Naim et al. cited above, a drawback of the cell design is that in the region k n ·I IN (n)≈I REF  where the currents in the subtraction transistors Q 2 , Q 3  of cell n are almost balanced, the drain current of transistor Q 1  in the next cell n+1 may cause a significant error. 
   As shown in the exemplary inventive embodiment  200  of  FIG. 3 , where like reference numbers in  FIG. 1  indicate like elements, this drawback is overcome by redefining the input-output relationship of each cell as follows: A set of cells m=1, 2, . . . M are cascaded but with I IN (m+1)=k m I IN (m) via transistor Q 4  coupled to the current mirror  102 . This results in a current divider sequence (k 1 ·k 2 . . . k m ) −1  for the range 0≦I IN (1) ≦I REF /k M , such that when I IN (m)&gt;I REF /k m , D O (m:M) is HI. In this case, the analog input I IN (m) is quantized by the smallest m such that D O (m) is LO. 
     FIG. 4  shows an exemplary IADC  300  having a series of cascaded m-type cells  302  each providing a digital output signal D O (m) and an output analog signal A O (m), which can be provided as the I IN  to next cell. 
   Both the n-cell ( FIGS. 1 and 2 ) and m-cell ( FIGS. 3 and 4 ) type IADCs have a variable dynamic range that is set by I REF . I REF  values in or below the nA range bias the transistors in the subthreshold regime, allowing the conversion of sub-nA currents. 
   It is understood that the input signal and/or the reference signal can be scaled to meet the needs of a particular application.  FIG. 5  shows an exemplary implementation  300  in which the reference signal I REF (n) is scaled by a scaling circuit  302 , such as a current mirror. It is understood that the illustrated cell  300  includes n-type and m-type circuitry. In this arrangement, m and n type cells receive a copy of I IN (1), which is referred to as I IN  and is the same for all cells in the exemplary embodiment shown. The cell digital output signal D O (n) is a logical HI if k n ·I REF (n) is greater than I IN . When k n ·I REF (n)&lt;I IN  for cell n, the inputs to subsequent cells are zero so that D O (n:N) is a logical LO. Thus the analog input is quantized by the largest value of n such that D O (n) is a logical HI. In the m-cell case, the analog input I IN  is quantized by the smallest m such that D O (m) is LO. As shown in  FIG. 5A , an analog output signal A O (m1), i.e., ((I REF (2)=k1·I REF (1)−I IN (1)), is provided by the first cell  350   a  to the analog input of the second cell  350   b , which generates a second digital output signal D O (m2), and so on. 
   EXAMPLE 
   The IADC designs shown in  FIGS. 1 and 3  were simulated on T-Spice and a prototype chip was fabricated using an AMI 1.5 μm process. For convenience the results for 4 m-cells and 4 n-cells with k n =k m =2 are presented. It is understood, however, that the illustrated designs can be readily extended to any number of cells with arbitrary current divider ratios. 
   In general, the simulations showed that the m-cells of  FIG. 3  generally had higher sensitivity and accuracy than the n-cells of  FIG. 1 . Measurements of the fabricated IDAC with a Keithley 6485 picoammeter showed that the m-cells had an input current sensitivity of &lt;100 picoampere (pA). 
   The IADC response bandwidth is determined by the conversion delay, which is given by the maximum rise or fall time (whichever is longer) of cell responses when switching on or off, respectively. For each cell, this value is determined primarily by the corresponding comparator&#39;s switching time, τ ∝(C L ·V DD )/(I IN −I REF ), where C L  is the load capacitance. 
   Looking to  FIG. 6 , the simulations showed that for V DD =1.2V and a square-wave current input with amplitude Î IN (1)=0.1 nA and I REF =1.6 nA, the conversion delay was &lt;500 μs. At Î IN (1)=1 nA and I REF =16 nA, the conversion delay was &lt;15 μs. 
   In  FIG. 7A , the fabricated IADC chip responded to a triangular-wave input with peak current Î IN (1)=30 nA at a frequency of 1 Hz. Similar results were obtained for Î IN (1) down to 1 nA. At even lower input currents or higher frequencies, measurements were limited by the response of the testbed, which was not designed to operate at such low current levels. Simulations showed that the IADC converted the signal with Î IN (1)=50 pA at a frequency of 1 Hz ( FIG. 6B ). In practice, the IADC can interface directly to the CMOS photodiode on chip, preserving the IADC response as predicted by simulations. 
   Because of inevitable current-mirror mismatch, the resulting current divider ratios may differ from the designed value of two. In  FIG. 7A , a simple calibration procedure yielded the actual ratios of 2.44, 2.36, and 2.6 for m4/m3, m3/m2, and m2/m1, respectively. Once calibrated, proper IADC operation was achieved. In practice, mismatch errors may be further minimized by increasing transistor sizes or decreasing process dimensions for a given size. 
   The present invention provides an IADC having high input sensitivity, low supply voltage V DD  and a programmable dynamic range. The illustrated embodiments can have a design that is simple, small, and power efficient. A conversion cell with I REF =1 nA uses &lt;10 nW of static power. 
   The resultant IADC conversion speed is generally adequate for biosensor applications. For example, the sub-nA level currents from an HRP-luminal-H 2 O 2  system in can be digitized in &lt;1 second, allowing ample temporal resolution for the measurement of initial reaction rates that are important to enzyme kinetics. 
   The inventive IADC can be readily integrated with portable CMOS sensors at reduced overall power, size, and cost. Its input sensitivity, speed and resolution can be further enhanced by employing sub-pA circuits and low-voltage wide-input comparator design techniques and with increased number of conversion cells. 
   Having described preferred embodiments of the invention, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. These embodiments should not be limited to disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety. 
   Other embodiments are within the scope of the following claims.