Abstract:
An apparatus and method for controlling the AGC in a receiver is described. Samples of the input signal are compared to the upper and lower threshold values which are defined by the dynamic range of the A-to-D converter. These samples are recorded and used in determining whether to count-up or count-down in counters prior to the time the signal is detected. These counts provide, in effect, a history of what has occurred prior to signal detection and are used in computing an AGC gain. The gain can be computed more quickly since there is zero latency in starting the calculation for correcting the AGC.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    2. Prior Art  
           [0003]    Typically, most high speed digital receivers used in networking consist of an analog front end (AFE) and a digital base-band processor (DBP). Once such processor will be discussed subsequently in conjunction with FIG. 1. The AFE amplifies the incoming analog signal at a gain setting which is generally variable. Ideally, the gain is set so that the entire dynamic range of an analog-to-digital converter is used since this enables the best signal detection. After signal or carrier detection, a predetermined number of samples are needed to adjust the gain. It is desirable to have this adjustment done as soon as possible during the preamble of a data packet because this provides for a more stable receiver.  
           [0004]    As will be seen, the present invention reduces the time required for gain control to occur and in effect, provides zero latency for the initiation of the computation used for gain control.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    [0005]FIG. 1 is a block diagram illustrating a prior art digital receiver such as used in networks.  
         [0006]    [0006]FIG. 2 is a circuit diagram of an embodiment of the present invention.  
         [0007]    [0007]FIG. 3 is a timing diagram used in conjunction with FIG. 1.  
         [0008]    [0008]FIG. 4 is a timing diagram used in conjunction with FIG. 2.  
         [0009]    [0009]FIG. 5 illustrates steps used in the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0010]    A zero latency circuit for starting a gain control calculations for a digital signal processor (DSP) is described. In the following description, specific details such as specific components are described in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these details. In other instances, well-known circuits have not been described in detail in order not to unnecessarily obscure the present invention.  
         [0011]    Referring first to FIG. 1, a typical prior digital receiver such as used for digital signal processing is illustrated. The receiver includes an analog front end (AFE)  10  having an analog amplifier with automatic gain control (AGC), the gain of which is controllable by a signal on line  18 , and an analog-to-digital converter which receives the amplified signal. Samples S(n) of the input analog signal obtained within the AFE  10  and coupled to the digital base-band processor (DBP)  11 . Generally, for all linear modulations such as quadrature amplitude modulation (QAM), the signal gain level is determined in the DBP and if a gain adjustment is necessary a new gain value is sent to the AFE on line  18 .  
         [0012]    The AGC plays an important role in both wired and wireless digital transceiver networks. The use of the AGC significantly increases the receiver&#39;s dynamic range and therefore the performance of the receiver. The longer a receiver can train on a preamble (the header portion of the data frame which is used for channel chaining, frequency or time synchronization) at the correct gain setting, the better the performance of the receiver.  
         [0013]    To verify that a signal is at the correct gain setting, the amplitude of a signal is measured after the signal is detected in the DBP  11 . Before this can occur, however, the signal is processed with for instance, in the radio frequency interference suppressor (RFI)  12  and signal demodulator (Dmod)  13 . Then the absolute value and truncation of the signal occurs within the ABS  14 . Filtering typically now is used, such as with low pass filtering through the filter (FIL)  15 . The signal detector (SD)  16  determines when a signal is above a signal detect threshold, thereby verifying that a signal is present. Once a signal has been detected (SIG_FIND) goes high, and then the automatic gain control (AGC) logic  17  compares the signal amplitude to a predetermined threshold for a chosen constant number of cycles to determine if the gain is correct. If a gain is not correct, the AGC logic  17  sets a new gain on line  18  in the AFE  10 .  
         [0014]    The initial start to determine if the AGC level is correct is delayed from the time a signal is received until the signal is processed by the AFE  10  and through the SD  16  of the DBP  11 . Then additional time is required for the AGC computation. Ideally, the AGC calculation should start with zero latency to maximize the useful training period during the preamble, as will be described for the present invention.  
         [0015]    As shown in FIG. 3, the timing diagram for the circuit of FIG. 1 begins with an AFE latency. This is the period between when the first analog digital signal is received and converted to a digital sample. Then after the DSP logic latency period  20 , the signal is detected and (SIG_FIND) occurs. Once SIG_FIND occurs, the AGC computation begins. A relatively large number of sample periods is required for the calculation before AGC_NUM occurs. Now, at time  25  the AGC can be corrected, if necessary. The sooner that the AGC can be brought to, or determined to be at a correct level, the better the system performance becomes. As can be seen from FIG. 3, there is a substantial latency before the AGC calculation begins, specifically the AFE latency and the period  20 .  
         [0016]    Turning now to FIG. 2, the circuit provides gain control signals which control gain such as the signal on line  18 . The circuit represented by FIG. 2 receives the complement of the SIG_FIND signal and samples S(n) from the analog-to-digital converter of the AFE. Additionally, the circuit receives a clocking signal which corresponds to the sample clock used within the AFE. The input signal samples which are taken at the output of the analog-to-digital converter and thus have been amplified by the gain control amplifier, are coupled to the circuit of FIG. 2 on line  30 . These samples are coupled to a first comparator  31  and a second comparator  40 . Within comparator  31 , each sample is compared to a voltage threshold level which represents a minimum signal level of the dynamic range of the analog-to-digital converter. If the signal is greater than this lower voltage threshold, then the condition of the comparator  31  is met and a signal is coupled to both the shift register  32  and the logic circuit  33 . Similarly, the comparator  40  compares the signal on line  30  with an upper digital threshold limit, this limit corresponding to the upper digital voltage range of the analog-to-digital converter. If the signal is greater than the upper threshold, then a signal is applied to the shift register  41  and to the logic circuit  42 .  
         [0017]    As will be seen the shift registers  32  and  41  record a history of whether the incoming signals are greater than the lower and upper thresholds. In effect, they provide a history in a trailing window of the past relative signal amplitudes. These, as will be seen, enable zero latency in starting the calculation of a AGC signal. For the embodiment of FIG. 2, this history is stored as one bit data signals in the shift registers  32  and  41 . Other memory means such as a random-access memory (RAM) can be used to store this information.  
         [0018]    On each sample clock pulse, the shift registers  32  and  41  are incremented such that the data from the comparators is shifted from stage-to-stage within the shift registers. A “1” or a “0” from the comparators  31  or  40  is consequently shifted to the most significant bit position in the shift registers. Both shift registers receive the complement of the SIG_FIND signal on line  50 . As long as the complement of SIG_FIND is high, the shift registers shift. Once an input signal is detected, SIG_FIND will go high and shifting ceases and the most significant bit from the register is no longer used within the circuit of FIG. 2 for the AGC calculation as indicated by the “X” in the Truth Table below.  
                                                     TRUTH TABLE                For Both   Shift Reg   En cnt up   En cnt down       SIG_FIND   Comparators   Msb   Output   Output               0   0   0   0   0       0   0   1   0   1       0   1   0   1   0       0   1   1   0   0       1   0   X   0   0       1   1   X   0   0       1   1   X   1   0       1   1   X   1   0                  
 
         [0019]    The logic circuit  33  receives the output of the comparator  31 , the most significant bit from the register  32  and the SIG_FIND signal. Similarly, the logic circuit  42  receives the most significant bit from the register  41 , the output of the comparator  40  and the SIG_FIND signal. The above table shows whether the output of the logic circuit enables a count-up signal, a count-down signal or no count. The first column in the table is the state of the SIG_FIND signal, the second column is the output of the comparator  31  (COMP 1 ) or the comparator  40  (COMP 2 ), the third column indicates the state of the most significant bit in the shift registers  32  and  41 . The output of the logic circuits are shown in the last two columns as either a count-up signal, a count-down signal or no signal.  
         [0020]    A first counter (low counter  34 ) receives the count-up and count-down signals from the logic circuit  33  as well as a clock signal. Similarly, a high counter  43  receives count-up and count-down signals from the logic circuit  42  as well as the clocking signal.  
         [0021]    The count within the counter  34  is compared to a count stored within the third comparator  35 . In a similar manner, the count within a counter  43  is compared to a predetermined count stored within the comparator  44 . If the count within the counter  34  is less than or equal to the count stored within the counter  35  (MIN_LOW) the conditions of the comparator  35  are met and a signal is applied to the gain control circuit  36 . If the count within the counter  43  is greater than the count stored in the counter  44  (MAX_HIGH) the conditions of the fourth comparator  44  are met and a signal is sent to the gain control  45 . The gain control  36  and the gain control  35  are integral parts of the gain control circuit. Block  36  is used to illustrate a doubling of the gain, whereas block  45  illustrates a halving of the gain. These blocks are shown separately in FIG. 2 but are typically an integral part of the AGC circuit.  
         [0022]    Initially for the circuit of FIG. 2, the shift registers contain all zero&#39;s and the counters  34  and  43  are set to zero. The number of stages in the shift registers  32  and  41  are sufficient to hold data representative of the relative amplitude of the samples that occur between the receipt of a first digital data signal and SIG_FIND that is, when the signal is first detected. This is shown in FIG. 3 for instance, as the DBP logic latency. The counters  34  and  43  may have 3 or 4 bits each in a typical application.  
         [0023]    In operation, the comparator  31  determines when a sample is larger than the stored threshold value, and when this occurs a signal (binary 1) is sent to the shift register  32  and to the logic circuit  33 . As can be seen from the Truth Table above, since the conditions of the comparator are met and the most significant bit from the register is still a zero, counter  31  will count up by one count. On the other hand, if the conditions of comparator  31  are not met, a zero is sent to the shift register  32 . The same operation is done by the comparator  40  if the sample is greater than the upper voltage threshold value.  
         [0024]    As mentioned, the shift register will have all zero&#39;s initially. After the receiver is enabled, and after the number of clocks issued equals the total latency of the AFE and the DBF (to SIG_FIND), the shift registers will be full and hold a record of when the threshold counters were enabled to count up. If SIG_FIND has not been asserted at this point, the process continues comparing the most significant bit of the shift registers, the comparator outputs and the SIG_FIND signal to control the threshold counters as shown in the Truth Table above. If the most significant bit of the shift register  31  is 1, and the output of the comparator  31  is 0, the counter  31  will have a count-down signal. This, in effect, means that the data for that clock position in the shift register was not data from an actual signal because SIG_FIND did not become valid while that bit was in the most significant position in the shift register. This process continues until SIG_FIND goes active. Similarly, this process continues for the counter  43  when the sample is greater than the upper threshold of that comparator.  
         [0025]    Once the control signal SIG_FIND is asserted, the shift registers and the most significant bit from the shift registers has no affect on the output of the logic circuits  33  and  42 . Only the output of the comparators are used by the logic circuits  33  and  44  to enable the count up in the counters. When SIG_FIND goes active, the counters have the count representing the number of times that the samples were above the lower and upper voltage thresholds for the number of data samples that is equal to the total number of cycles of DBP logic latency as discussed above. Note that if a number of clock cycles for DBP logic latency, is equal to the total number of cycles needed to do the AGC calculation (AGC_NUM), then the first AGC gain adjustment may be done at the same cycle time as the signal is detected (SIG_FIND).  
         [0026]    As shown in FIG. 4, again receipt of the first analog data is shown along with the AFE latency and the DBP latency all occurring before SIG_FIND. As can be seen, the number of cycles to do the AGC calculation includes the AFE and DBP latency periods since the counters have been operating as described above during this latency period. Thus, the first sample that occurs after SIG_FIND is used along with the current count in the counters to enable the AGC calculation to be continued. As shown in FIG. 4, the first AGC adjustment occurs at time  55  which is substantially sooner than the time  25  of FIG. 3,  
         [0027]    To finish the AGC adjustment once SIG_FIND occurs, the process is continued until AGC_NUM number of cycles have been used to calculate the signal amplitude (gain). If the count value in the counter  34  is smaller or equal to the stored constant MIN_LOW in the comparator  35 , then the AGC sends out a signal (AGC_ADJ) to the AFE to increase the gain by a set number of dBs, for instance 3 dB. The same operation applies to the counter  43  except the gain is reduced by a set number of dBs when the conditions are met.  
         [0028]    The MIN_LOW value stored within register  35  can be empirically determined based on overall receiver performance. The same is true for MAX_HIGH in the comparator  44 . These values initially may be set midway between the maximum counts of the counters  34  and  43 .  
         [0029]    The steps used by the circuit of FIG. 2 are shown from the standpoint of overall circuit operation in FIG. 5. As shown within step  60  the data is recorded representing the relative amplitude of the input samples. This is done as discussed by placing binary 1&#39;s or 0&#39;s into the shift registers  32  and  41 .  
         [0030]    As shown by step  61 , a counter is controlled based on the current relative amplitude of the input sample and the recorded data. The recorded data is only used up until the time that SIG_FIND occurs. The counting up and counting down logic for the counters is shown in the Truth Table set forth above.  
         [0031]    Finally, as shown by step  62  the gain is adjusted based on the contents of the counter when the AGC calculation is completed.  
         [0032]    Thus, a circuit has been described which has zero latency for the start of an initial AGC calculation in a digital signal processor.  
       APPENDIX A  
       [0033]    William E. Alford, Reg. No. 37,764; Farzad E. Amini, Reg. No. 42,261; William Thomas Babbitt, Reg. No. 39,591; Carol F. Barry, Reg. No. 41,600; Jordan Michael Becker, Reg. No. 39,602; Lisa N. Benado, Reg. No. 39,995; Bradley J. Bereznak, Reg. No. 33,474; Michael A. Bernadicou, Reg. No. 35,934; Roger W. Blakely, Jr., Reg. No. 25,831; R. Alan Burnett, Reg. No. 46,149; Gregory D. Caldwell, Reg. No. 39,926; Andrew C. Chen, Reg. No. 43,544; Thomas M. Coester, Reg. No. 39,637; Donna Jo Coningsby, Reg. No. 41,684; Florin Corie, Reg. No. 46,244; Dennis M. deGuzman, Reg. No. 41,702; Stephen M. De Klerk, Reg. No. 46,503; Michael Anthony DeSanctis, Reg. No. 39,957; Daniel M. De Vos, Reg. No. 37,813; Sanjeet Dutta, Reg. No. 46,145; Matthew C. Fagan, Reg. No. 37,542; Tarek N. Fahmi, Reg. No. 41,402; George Fountain, Reg. No. 37,374; James Y. Go, Reg. No. 40,621; James A. Henry, Reg. No. 41,064; Libby N. Ho, Reg. No. 46,774; Willmore F. Holbrow III, Reg. No. 41,845; Sheryl Sue Holloway, Reg. No. 37,850; George W Hoover II, Reg. No. 32,992; Eric S. Hyman, Reg. No. 30,139; William W. Kidd, Reg. No. 31,772; Sang Hui Kim, Reg. No. 40,450; Walter T. Kim, Reg. No. 42,731; Eric T. King, Reg. No. 44,188; George Brian Leavell, Reg. No. 45,436; Kurt P. Leyendecker, Reg. No. 42,799; Gordon R. Lindeen III, Reg. No. 33,192; Jan Carol Little, Reg. No. 41,181; Robert G. Litts, Reg. No. 46,876; Joseph Lutz, Reg. No. 43,765; Michael J. Mallie, Reg. No. 36,591; Andre L. Marais, under 37 C.F.R. § 10.9(b); Paul A. Mendonsa, Reg. No. 42,879; Clive D. Menezes, Reg. No. 45,493; Chun M. Ng, Reg. No. 36,878; Thien T. Nguyen, Reg. No. 43,835; Thinh V. Nguyen, Reg. No. 42,034; Dennis A. Nicholls, Reg. No. 42,036; Robert B. O&#39;Rourke, Reg. No. 46,972; Daniel E. Ovanezian, Reg. No. 41,236; Kenneth B. Paley, Reg. No. 38,989; Gregg A. Peacock, Reg. No. 45,001; Marina Portnova, Reg. No. 45,750; William F. Ryann, Reg. 44,313; James H. Salter, Reg. No. 35,668; William W. Schaal, Reg. No. 39,018; James C. Scheller, Reg. No. 31,195; Jeffrey Sam Smith, Reg. No. 39,377; Maria McCormack Sobrino, Reg. No. 31,639; Stanley W. Sokoloff, Reg. No. 25,128; Judith A. Szepesi, Reg. No. 39,393; Vincent P. Tassinari, Reg. No. 42,179; Edwin H. Taylor, Reg. No. 25,129; John F. Travis, Reg. No. 43,203; Joseph A. Twarowski, Reg. No. 42,191; Tom Van Zandt, Reg. No. 43,219; Lester J. Vincent, Reg. No. 31,460; Glenn E. Von Tersch, Reg. No. 41,364; John Patrick Ward, Reg. No. 40,216; Mark L. Watson, Reg. No. 46,322; Thomas C. Webster, Reg. No. 46,154; and Norman Zafman, Reg. No. 26,250; my patent attorneys, and Firasat Ali, Reg. No. 45,715; Justin M. Dillon, Reg. No. 42,486; Thomas S. Ferrill, Reg. No. 42,532; and Raul Martinez, Reg. No. 46,904, my patent agents, of BLAKELY, SOKOLOFF, TAYLOR &amp; ZAFMAN LLP, with offices located at 12400 Wilshire Boulevard, 7th Floor, Los Angeles, Calif. 90025, telephone (310) 207-3800, and Alan K. Aldous, Reg. No. 31,905; Edward R. Brake, Reg. No. 37,784; Ben Burge, Reg. No. 42,372; Jeffrey S. Draeger, Reg. No. 41,000; Cynthia Thomas Faatz, Reg No. 39,973; John N. Greaves, Reg. No. 40,362; Seth Z. Kalson, Reg. No. 40,670; David J. Kaplan, Reg. No. 41,105; Peter Lam, Reg. No. 44,855; Charles A. Mirho, Reg. No. 41,199; Leo V. Novakoski, Reg. No. 37,198; Thomas C. Reynolds, Reg. No. 32,488; Kenneth M. Seddon, Reg. No. 43,105; Mark Seeley, Reg. No. 32,299; Steven P. Skabrat, Reg. No. 36,279; Howard A. Skaist, Reg. No. 36,008; Gene I. Su, Reg. No. 45,140; Calvin E. Wells, Reg. No. P43,256, Raymond J. Werner, Reg. No. 34,752; Robert G. Winkle, Reg. No. 37,474; Steven D. Yates, Reg. No. 42,242; and Charles K. Young, Reg. No. 39,435; my patent attorneys, of INTEL CORPORATION; and James R. Thein, Reg. No. 31,710, my patent attorney with full power of substitution and revocation, to prosecute this application and to transact all business in the Patent and Trademark Office connected herewith.  
       APPENDIX B  
     Title 37, Code of Federal Regulations, Section 1.56 Duty to Disclose Information Material to Patentability  
       [0034]    (a) A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section. The duty to disclosure information exists with respect to each pending claim until the claim is cancelled or withdrawn from consideration, or the application becomes abandoned. Information material to the patentability of a claim that is cancelled or withdrawn from consideration need not be submitted if the information is not material to the patentability of any claim remaining under consideration in the application. There is no duty to submit information which is not material to the patentability of any existing claim. The duty to disclosure all information known to be material to patentability is deemed to be satisfied if all information known to be material to patentability of any claim issued in a patent was cited by the Office or submitted to the Office in the manner prescribed by §§1.97(b)-(d) and 1.98. However, no patent will be granted on an application in connection with which fraud on the Office was practiced or attempted or the duty of disclosure was violated through bad faith or intentional misconduct. The Office encourages applicants to carefully examine:  
         [0035]    (1) Prior art cited in search reports of a foreign patent office in a counterpart application, and  
         [0036]    (2) The closest information over which individuals associated with the filing or prosecution of a patent application believe any pending claim patentably defines, to make sure that any material information contained therein is disclosed to the Office.  
         [0037]    (b) Under this section, information is material to patentability when it is not cumulative to information already of record or being made or record in the application, and  
         [0038]    (1) It establishes, by itself or in combination with other information, a prima facie case of unpatentability of a claim; or  
         [0039]    (2) It refutes, or is inconsistent with, a position the applicant takes in:  
         [0040]    (i) Opposing an argument of unpatentability relied on by the Office, or  
         [0041]    (ii) Asserting an argument of patentability.  
         [0042]    A prima facie case of unpatentability is established when the information compels a conclusion that a claim is unpatentable under the preponderance of evidence, burden-of-proof standard, giving each term in the claim its broadest reasonable construction consistent with the specification, and before any consideration is given to evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.  
         [0043]    (c) Individuals associated with the filing or prosecution of a patent application within the meaning of this section are:  
         [0044]    (1) Each inventor named in the application;  
         [0045]    (2) Each attorney or agent who prepares or prosecutes the application; and  
         [0046]    (3) Every other person who is substantively involved in the preparation or prosecution of the application and who is associated with the inventor, with the assignee or with anyone to whom there is an obligation to assign the application.  
         [0047]    (d) Individuals other than the attorney, agent or inventor may comply with this section by disclosing information to the attorney, agent, or inventor.