Abstract:
A pulse generator system includes a plurality of buffers at least two transmission gates. The inverters successively and input insert delays into an signal having a series of pulses, each pulse having first and second edges. The transmission gates are operatively coupled to the inverters. The first transmission gate selectively passes the input signal. The second transmission gape selectively passes inverted signal of the input signal.

Description:
BACKGROUND 
     This invention relates to a dual edge-triggered circuit, and more particularly to an explicit pulse generator circuit. 
     Dual edge-triggered circuits latch data on both the rising and falling edges of the clock. This may halve the clock frequency for the same data throughput. Since the power dissipation may be proportional to the frequency of operation, the total used power may be reduced. Further, since a significant portion of the total power of the circuit may be consumed in the clock distribution network, it may be advantageous to employ chips that operate on both edges of the clock. Thus, replacing conventional single edge-triggered circuits with dual edge-triggered circuit may result in up to 50% power savings in the clock distribution. However, the circuits must be designed in an energy-efficient manner to provide meaningful reduction in the total power consumption. 
     Prior art designs on creating dual edge-triggered flip-flops have been provided by replicating the latch elements of a single edge-triggered flip-flop and multiplexing the outputs. For example, M. Afghahi and J. Yuan, in “Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits”, IEEE Journal of Solid-State Circuits, pages 1168-1170, Vol. 26, No. 8, August 1991, suggest reducing the power dissipation of a clock distribution circuit by using flip-flops triggered on both edges of the clock pulses instead of on only one edge. The dual edge-triggered flip-flop is created from two true single-phase clock elements and a NAND gate. A. Gago et. al., in “Reduced implementation of D-type DET Flip-Flops”, IEEE Journal of Solid-State Circuits, pages 400-402, Vol. 28, No. 3, March 1993, present a dual edge-triggered static master-slave flip-flop. The design duplicates a single edge-triggered flip-flop but shares the clock transistors that are common to both latches. These implementations suffer from a larger clock load at the same level of performance as a single edge-triggered flip-flop. Therefore, this may offset gain from the reduced clock frequency. 
     SUMMARY 
     In an embodiment, flip-flop device may include a transmission gate to receive data and, in response to control signals, to pass the data, a buffer coupled to an output of the first transmission gate to save and output the data, and a dual edge triggered pulse generator. The dual edge triggered pulse generator may receive a input clock signal having a frequency and a pulse width and generate the control signals as a function of the input clock signal. The control signals may have a frequency equal to twice the input clock signal frequency. The control signals may enable the first transmission gate to pass the data for a time duration less than one-half of the input clock signal pulse width so that a slave latch for latching the data is not required. 
     The dual edge triggered pulse generator may include two or more inverters connected in series, each inverter to successively insert a delay into the input clock signal and to generate a delay signal, and additional transmission gates, responsive to the delay signal and coupled to said at least two inverters, where the outputs of the additional transmission gates may be coupled together. One of the transmission gates may be coupled to receive and selectively pass the input clock signal as a second output signal having a delay time less than the input clock signal pulse width. Another of the transmission gates may be coupled to receive and selectively pass inverted signal of the input clock signal as a third output signal having a delay time less than the input clock signal pulse width. The second output signal and the third output signal may combine at the transmission gate outputs to form an output clock signal having two pulses within one cycle of the input clock signal. 
    
    
     DESCRIPTION OF DRAWINGS 
     These and other features and advantages of the invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings. 
     FIG. 1 shows an explicit-pulsed static flip-flop element according to an embodiment of the present disclosure. 
     FIG. 2 shows a timing diagram of the explicit pulse generator shown in FIG.  1 . 
     FIG. 3 illustrates one embodiment of a dual edge-triggered explicit-pulsed static flip-flop element. 
     FIG. 4 shows a timing diagram of the explicit pulse generator shown in FIG.  3 . 
     FIG. 5 shows a method for generating explicit pulse signals. 
    
    
     DETAILED DESCRIPTION 
     In recognition of the above-described difficulties with conventional dual edge-triggered circuits, the present disclosure describes an explicit pulse generator that provides a dual edge-triggered signal. The explicit pulse dual edge-triggered circuit provides advantages over a conventional dual edge-triggered circuit by allowing larger energy savings from fewer device count and reduced clock load. 
     An explicit-pulsed static flip-flop element  100  according to an embodiment is shown in FIG.  1 . The flip-flop element  100  includes an explicit pulse generator  102  and a flip-flop portion  120 . This element  100  is a single edge-triggered flip-flop. 
     In the illustrated embodiment, the rising edge on the “Clk” input  104  produces a falling clock pulse on the PMOS transistor  108  of the transmission gate  106 . The “Clk” input  104  also produces a rising clock pulse on the NMOS transistor  110  of the transmission gate  106 . The width of the clock pulse, produced at the output of the explicit pulse generator  102 , may be set by the number and sizes of inverters  112 . Thus, the clock pulse may be set to achieve a reasonable balance between the amount of time borrowing desired and the maximum hold time that may be tolerated. Although no pulse is generated on the falling edge of the incoming clock, power is dissipated in the pulse generator  102  as the inverters  112  switch. 
     FIG. 2 shows a timing diagram of the explicit pulse generator  102  shown in FIG.  1 . The timing diagram shows that the rising edge  200  on the Clk input produces a falling clock pulse  202  on the PMOS transistor  108  (node P) and a rising clock pulse  204  on the NMOS transistor  110  (node N). The pulses  202 ,  204  are generated when the input node B of the NAND gate  114  is delayed with respect to the input node A by the inverters  112 . The NAND gate  114  outputs a falling edge pulse at node P, in response to the rising edge of the Clk input, when the input nodes A and B are both logic high. Therefore, the pulse width  206  is set by the delay generated by the inverters  112 . Accordingly, the rising edge clock pulse  204  at the NMOS transistor  110  and the falling edge clock pulse  202  at the PMOS transistor  108  of the transmission gate  106  clocks data input D  116  to output Q  118  of the flip-flop. 
     One embodiment of a dual edge-triggered explicit-pulsed static flip-flop element  300  is illustrated in FIG.  3 . The dual edge-triggered element  300  includes an explicit pulse generator system  302 . The element  300  also includes a flip-flop portion  304  having the same design as the flip-flop portion  120  of the single edge-triggered element  100  shown in FIG.  1 . 
     The explicit pulse generator system  302  includes a transmission-gate XOR circuit involving two transmission gates  306 ,  308 . The transmission-gate XOR circuit provides a clock pulse generated on both edges of the incoming clock  310 . 
     Since the flip-flop portion  304  has not been modified, there is no performance penalty for the dual edge-triggered design as compared to the single edge-triggered version. Further, since no replication is necessary, the total area of the dual edge-triggered element  300  may be smaller than the conventional dual edge-triggered design. 
     In the illustrated embodiment of the explicit pulse generator system  302  shown in FIG. 3, there are three inverters  312  and two transmission gates  306 ,  308 . Each of the transmission gates  306 ,  308  includes a PMOS transistor and an NMOS transistor connected in parallel. The transistors in the transmission gate are controlled by a pair of complementary signals driving the gates of the transistors. For example, the transmission gate  306  is controlled by delayed signals, at nodes C and D, feeding the gate terminals of the NMOS and PMOS transistors, respectively. The transmission gate  308  is controlled by delayed signals, at nodes D and C, feeding the gate terminals of the NMOS and PMOS transistors, respectively. Input signals to the transmission gates  306 ,  308  are supplied by the input signal at node A and the delayed signal at node B, respectively. The outputs of the transmission gates  306 ,  308  are tied together to form a wired-OR configuration at node  314 . 
     FIG. 4 shows a timing diagram of the explicit pulse generator system  302  shown in FIG.  3 . The delayed clock pulses at nodes A through D are shown below the input clock pulse (“Clk”). The transmission gate  306  passes the input clock to the output node P 1 , when the pulse at node C is at logic high and the pulse at node D is at logic low. The transmission gate  308  passes the delayed pulse at node B to the output node P 2 , when the pulse at node D is at logic high and the pulse at node C is at logic low. Therefore at node P 1 , a falling clock pulse (indicated by solid line) is generated at the falling edge of the input clock  310 . At node P 2 , a falling clock pulse (indicated by solid line) is generated at the falling edge of the signal at node B. This signal may be a delayed rising edge of the input clock  310 . 
     Accordingly, falling clock pulses are generated at both edges of the input clock at node P, as shown in FIG.  4 . Rising clock pulses are generated at both edges of the input clock at node N. 
     FIG. 5 shows a method for generating explicit pulse signals. The method includes successively inserting a delay into an input signal, at  500 . The input signal and delayed signals of the input signal are then coupled, at  502 . At  504 , the input signal is selectively passed at first and second edges of the input signal by using delayed signals. 
     The advantages of using an explicit pulse generator similar to the generator system  302  shown in FIG. 3 have been measured. For a target D-to-Q delay of 100 pico-seconds, the explicit-pulsed dual edge-triggered flip-flop element was measured to consume less energy than the single edge-triggered version. Additional energy savings may be realized in the clock distribution network. 
     While specific embodiments of the invention have been illustrated and described, other embodiments and variations are possible. For example, although the illustrated embodiments show the pulse generator being used in a flip-flop circuit, other circuits are envisioned that utilize the explicit pulse generator. Furthermore, the clock signal generated by the explicit pulse generator may be used for purposes other than for clocking. Thus, the pulse generator may be used in transition encoders for low-power busses, or in frequency doubler circuits. 
     All these are intended to be encompassed by the following claims.