Abstract:
An input/output buffer circuit is capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to a halt. The input/output buffer circuit has an input/output terminal ( 10 ) for performing the input/output of data. When a write enable signal WR is in an active state, the input/output buffer circuit outputs a signal to the input/output terminal ( 10 ). When a read enable signal RD is in an active state, the input/output buffer circuit receives data from the input/output terminal ( 10 ). When the write enable signal RD and the read enable signal WR are both in a non-active state, the input/output buffer circuit outputs a signal based on any of signals supplied thereto.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    The present invention relates to an input/output buffer circuit suitable for use in a microcomputer or the like, which controls an external bus connected to an input/output terminal.  
           [0002]    A microcomputer or the like is provided with an input/output buffer circuit for controlling an external bus. The input/output buffer circuit is connected to a data bus connected to an input/output terminal and mainly controlled by a read enable signal RD and a write enable signal WR. Since the data bus is a bidirectional bus, it needs to be placed under input/output control.  
           [0003]    In general, a read enable signal RD or a timing signal similar thereto is used as an input-permitting control signal. Further, a write enable signal WR or a timing signal similar thereto is used as an output-permitting control signal. There might be a case in which a write enable signal WR or a timing signal similar thereto is used only as a control signal for always allowing the input and output without using a control signal for allowing the input.  
           [0004]    Since, however, the write enable signal WR or timing signal similar thereto used as the output-permitting control signal is not active in the input/output buffer circuit having the above configuration during its access-to-outside free time, the output of the data bus results in high impedance Hiz. Since the read enable signal RD becomes negative when the write enable signal WR is active, the data bus is brought to the high impedance Hiz when no output is transferred even from an external part connected to the input/output terminal.  
           [0005]    General externally connected parts might include one in which a through current flows in an input gate thereof when a data bus connected to an input/output terminal on the microcomputer side is brought to the high impedance Hiz. Therefore, a problem arises in that a system including the microcomputer and the externally connected parts increases in current consumption. This becomes a big problem in a low power consumption mode for bringing a clock to a halt in particular. As a measure against it, a measure might be taken for pulling up or down the data bus or externally providing a bus hold circuit so as to prevent the data bus from being brought to the high impedance Hiz. However, the measure involves a problem in that current consumption at the operation of the data bus increases in reverse.  
         SUMMARY OF THE INVENTION  
         [0006]    The present invention may provide an input/output buffer circuit capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to halt.  
           [0007]    The input/output buffer circuit according to the invention of the present application has an input/output terminal for performing the input/output of data, and outputs a signal to the input/output terminal when a write enable signal is in an active state and receives data from the input/output terminal when a read enable signal is in an active state.  
           [0008]    The input/output buffer circuit according to the invention of the present application outputs a signal based on any of signals supplied thereto when the write enable signal and the read enable signal are both in a non-active state. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]    While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:  
         [0010]    [0010]FIG. 1 is a circuit diagram showing an input/output buffer circuit according to a first embodiment of the present invention;  
         [0011]    [0011]FIG. 2 is a diagram illustrating an example of a buffer circuit with an enable terminal;  
         [0012]    [0012]FIG. 3 is a circuit diagram depicting an input/output buffer circuit according to a second embodiment of the present invention; and  
         [0013]    [0013]FIG. 4 is a circuit diagram showing an input/output buffer circuit according to a third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0014]    Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.  
         [0015]    [0015]FIG. 1 is a circuit diagram showing a first embodiment of the present invention. An input/output buffer circuit showing the first embodiment, which is connected to an input/output terminal  10 , comprises a buffer circuit  12  with an enable terminal, an inverter  14 , a first AND circuit  16 , and a second AND circuit  18 . The input/output terminal  10  is electrically connected to a first input of the first AND circuit  16 , and a read enable signal RD is supplied to a second input thereof. An output of the first AND circuit  16  is transferred to the inside of the circuit as input data.  
         [0016]    A first input of the second AND circuit  18  is supplied with output data from inside the circuit, and a second input thereof is supplied with a write enable signal WD. The output of the second AND circuit  18  outputs output data therefrom only when the write enable signal WD is of an H level (active level).  
         [0017]    The buffer circuit  12  is a circuit which outputs a signal received at its input therefrom only when a signal having an active level is inputted to the enable terminal thereof, and which brings an output into high impedance Hiz regardless of the level of the signal received at its input when a signal having a disable level is received at the enable terminal.  
         [0018]    The input of the buffer circuit  12  with the enable terminal is electrically connected to the output of the second AND circuit  18 , and the output thereof is electrically connected to the input/output terminal  10 . The enable terminal of the buffer circuit  12  is supplied with a signal obtained by inverting the read enable signal RD by means of the inverter  14 .  
         [0019]    As a specific circuit of the buffer circuit  12  with the enable terminal, may be illustrated such a circuit as shown in FIG. 2 by way of example. The buffer circuit shown in FIG. 2 comprises a PMOS transistor  22 , an NMOS transistor  24 , a NAND circuit  26 , a NOR circuit  28 , and an inverter  30 . The PMOS transistor  22  and NMOS transistor  24  are electrically connected in series between a power source VDD and the ground, and the input/output terminal  10  is electrically connected to their connecting point.  
         [0020]    A first input of the NAND circuit  26  is supplied with output data sent from inside the circuit, whereas a second input thereof is supplied with a signal obtained by inverting a signal (represented as an enable signal Enable in the present circuit) supplied to an enable terminal of the inverter  30  by means of the inverter  30 . A first input of the NOR circuit  28  is supplied with the output data sent from inside the circuit, whereas a second input thereof is supplied with the enable signal Enable. The output of the NAND circuit  26  is electrically connected to its corresponding gate of the PMOS transistor  22 , and the output of the NOR circuit  28  is electrically connected to its corresponding gate of the NMOS transistor  24 .  
         [0021]    The buffer circuit  12  shown in FIG. 2 outputs output data to the input/output terminal  10  when the enable signal Enable is of an H level (active level). When, however, the enable signal Enable is of an L level, the output of the buffer circuit  12  is brought to high impedance.  
         [0022]    Incidentally, various circuits have been considered as the buffer circuit  12  even except for the buffer circuit  12  as shown in FIG. 2. In the present invention, even circuits other than one shown in FIG. 2 can be utilized if they are circuits each switched to either a high impedance state or a normal output state in response to the enable signal Enable.  
         [0023]    The operation of the input/output buffer circuit shown in FIG. 1 will next be described.  
         [0024]    Since the read enable signal RD is brought to an H level (active level) when the input/output buffer circuit is in an input state, a signal supplied to the input/output terminal  10  from an externally connected circuit is transferred to the inside thereof via the first AND circuit  16 . On the other hand, since the buffer circuit  12  is supplied with a signal (corresponding to a signal of an L level) obtained by inverting a read enable signal RD by means of the inverter  14 , the buffer circuit  12  is brought into a high impedance state regardless of a signal inputted thereto. Thus, the signal supplied to the input/output terminal  10  does not undergo interference of the buffer circuit  12 .  
         [0025]    When the input/output buffer circuit is in an output state, the read enable signal RD is brought to an L level (non-active level). Thus, since the buffer circuit  12  is supplied with a signal (corresponding to a signal of an H level) obtained by inverting the read enable signal RD by means of the inverter  14 , the buffer circuit  12  outputs the signal inputted thereto. On the other hand, since a write enable signal WR reaches an H level (active level), output data supplied to the second AND circuit  18  is transferred to the buffer circuit  12 . Accordingly, the output data is transferred to the input/output terminal  10 .  
         [0026]    During a period in which the input/output buffer circuit is held neither in the output state nor in the input state, the read enable signal RD and the write enable signal WR reach the L level (non-active level). Thus, since the buffer circuit  12  is supplied with a signal (corresponding to a signal of an H level) obtained by inverting the read enable signal RD by means of the inverter  14 , the buffer circuit  12  outputs the signal inputted thereto. However, since the write enable signal WR is brought to the L level (non-active level), the output of the second AND circuit  18  is fixed to the L level. Accordingly, the buffer circuit  12  outputs the signal of the L level therefrom.  
         [0027]    Since, as described above, the input/output buffer circuit according to the first embodiment of the present invention outputs the L level signal even during the period in which it is held neither in the output state nor in the input state, the L level signal is supplied even to an input buffer for the external device connected to the input/output terminal  10 . It is thus possible to prevent the occurrence of a through current due to the input buffer of the external device connected to the input/output terminal  10  being responsive to the input having high impedance.  
         [0028]    [0028]FIG. 3 is a circuit diagram showing an input/output buffer circuit according to a second embodiment of the present invention. In FIG. 3, the same elements of structure are identified by the same reference numerals and the description thereof will therefore be omitted. The input/output buffer circuit according to the second embodiment is different from the input/output buffer circuit according to the first embodiment in that a buffer circuit  36  is provided as an alternative to the first AND circuit  16 . Since the buffer circuit  36  is not placed under the control of a read enable signal RD, it always transfers a signal at an input/output terminal  10  to the inside thereof. Thus, when the input/output buffer circuit is held in an input state, it operates in a manner similar to the first embodiment. When the input/output buffer circuit is held in an output state, it transfers a signal outputted from a buffer circuit  12  with an enable terminal to an internal circuit as it is. While the input/output buffer circuit transfers the output signal of the buffer circuit  12  to the internal circuit as it is even during a period in which the input/output buffer circuit is held neither in the output state nor in the input state, the input/output buffer circuit results in an operation similar to the first embodiment because the output signal of the buffer circuit  12  is L in level.  
         [0029]    The input/output buffer circuit according to the second embodiment operates in a manner similar to that according to the first embodiment except when output data is inputted to the inside of the input/output buffer circuit as input data as it is when it is held in the output state. Thus, the input/output buffer circuit according to the second embodiment has the advantage that the output data can be brought to the inside thereof in the output state, in addition to the advantage of the input/output buffer circuit according to the first embodiment.  
         [0030]    [0030]FIG. 4 is a circuit diagram showing an input/output buffer circuit according to a third embodiment of the present invention. The input/output buffer circuit according to the third embodiment is different from the input/output buffer circuit according to the first embodiment in that an enable terminal of a buffer circuit  42  provided with it s supplied with a signal obtained by taking the logic of a read enable signal RD, a write enable signal WR and a primary function signal, and the input of the buffer circuit  42  is supplied with a signal obtained by taking the logic of output data, primary data and the write enable signal WR.  
         [0031]    Described specifically, the input of a first AND circuit  50  is supplied with the output data and the write enable signal WR, and the output thereof is electrically connected to one input of a first OR circuit  48 . The inputs of a second AND circuit  52  are respectively supplied with the primary data and a signal obtained by inverting the write enable signal WR by means of a first inverter, and the output thereof is electrically connected to the other input of the first OR circuit  48 . The output of the first OR circuit  48  is electrically connected to the input of the buffer circuit  42 .  
         [0032]    A third AND circuit  58  has three inputs. The first input thereof is supplied with the primary function signal, the second input thereof is supplied with a signal obtained by inverting the read enable signal RD by means of a second inverter  62 , and the third input thereof is supplied with a signal obtained by inverting the write enable signal WR by means of a third inverter  60 , respectively. The output of the third AND circuit  58  is connected to one input of a second OR circuit  56 . The other input of the second OR circuit  56  is supplied with the write enable signal WR, and the output of the second OR circuit  56  is electrically connected to the enable input of the buffer circuit  42  provided with the enable terminal.  
         [0033]    Since the inverted signal of the write enable signal RD is inputted to the enable input of the buffer circuit  42  with the enable terminal regardless of other signals when the input/output buffer circuit according to the third embodiment is held in an input state, the input/output buffer circuit results in the same operation as that according to the first embodiment.  
         [0034]    Since the write enable signal WR is of an H level when the input/output buffer circuit is held in an output state, the first AND circuit  50  outputs output data therefrom, and the second AND circuit  52  outputs an L level signal regardless of the primary data. Accordingly, the first OR circuit  48  outputs the output data therefrom. On the other hand, the second OR circuit  56  outputs an H level of the write enable signal WR regardless of one input (output of the third AND circuit  58 ). Thus, the input/output buffer circuit still results in an operation similar to that according to the first embodiment.  
         [0035]    During a period in which the input/output buffer circuit is held neither in the output state nor in the input state, the read enable signal RD and the write enable signal WR are respectively brought to an L level (non-active level). Accordingly, the first AND circuit  50  outputs an L level signal regardless of the output data, and the second And circuit  52  outputs the primary data therefrom. Thus, the first OR circuit  48  outputs the primary data therefrom.  
         [0036]    On the other hand, since the third AND circuit  58  outputs the primary function signal therefrom, and the second OR circuit  56  also allows the primary function signal to pass therethrough, the buffer circuit  42  with the enable terminal outputs the primary data when the primary function signal is of an H level, whereas when the primary function signal is of an L level, the buffer circuit  42  is brought into a high impedance state. Thus, whether the buffer circuit  42  is brought to the high impedance state or outputs the primary data, is controlled based on the primary function signal during the period in which it is held neither in the output state or in the input state.  
         [0037]    According to the invention of the present application as described above in detail, since an L level signal is outputted from an input/output terminal even during a period in which neither of an output state and an input state is taken, it is possible to prevent the occurrence of a through current in an input buffer of an external device connected to the input/output terminal.  
         [0038]    While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.