Abstract:
A digital signal receiver for a high-bitrate digital signal has a serial signal input ( 20, 20 ′) and a number of N parallel digital signal outputs ( 26 ) with N&gt;1. The receiver contains at least N+1 digital sampling channels ( 31 - 35 ), a Q-monitor ( 37, 38 ) for comparing the output signal of at least two of said sampling channels ( 31 - 35 ), and a switch fabric ( 36 ) for controllably connecting N of said sampling channels ( 31 - 35 ) to said output leads ( 36 ) and at least two of said sampling channels ( 31 - 35 ) to said Q-monitor ( 37, 38 ). This allows to use N of the sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention is based on a priority application EP 06300895.7 which is hereby incorporated by reference. 
         [0002]    The present invention relates to the field of telecommunications and more particularly to a digital signal receiver with Q-monitor, which can be used in optical transport networks operating at a very high bitrate. 
       BACKGROUND OF THE INVENTION 
       [0003]    The ITU recommendation ITU-T O.201, which is incorporated by reference herein, describes Q-factor measurement equipment, commonly also referred to as a Q-monitor. A Q-monitor is a powerful circuit for performance monitoring of high speed optical signals as well as a sensor for adaptive adjustment of decision threshold, decision phase and other parameters like amplifier gain or equalizer setting in an EDC (Electronic Dispersion Compensation) based receiver. 
         [0004]    The basic Q-monitor circuit shown in  FIG. 1 , which is taken from ITU-T O.201, uses two decision channels, where one channel is operated in the optimum sampling point (regenerated input signal), whereas the other scans the input signal in the amplitude/phase dimensions. The outputs of the two decision channels are compared (EXOR) and integrated (error counter) for different monitor thresholds and phases. This results in a one or two dimensional eye contour. If an algorithm is used to derive from this measurement the optimum decision threshold and phase, the receiver is operated in its optimum sampling point and additionally computes a Q-factor for performance monitoring purposes. 
         [0005]    Q-factor measurement is an established method for characterization of optical channels. Particularly at low bit error rates the method has the advantage of taking less time than a traditional BER measurement, which requires to count bit errors over a statistically significant time period. The Q-factor is defined as the (electrical) signal-to-noise ratio at the decision circuit of a digital signal receiver. 
         [0006]    A Q-monitor is also described in EP 0 923 204 A2, which is incorporated by reference herein. EP 1 445 879 A1, which is likewise incorporated by reference herein, modifies the basic Q-monitor concept in such a way that the two decision channels can be alternatively operated in monitor and data sampling mode. A crossover switch following the two decision channels selects the appropriate decision channel for the data and the monitor paths. This way, all phase and amplitude offsets in the circuit can be compensated effectively. 
         [0007]    Existing Q-monitors are, however, not well suited for highest bitrate applications at well above 10 Gbit/s. Moreover, for further processing of highest bitrate signals (i.e., overhead processing, FEC etc), such signals are typically converted to a parallel format. 
         [0008]    It is therefore an object of the present invention to provide a digital signal receiver with Q-monitor, which is suited for highest bitrate applications, preferably at 40 GBit/s and above. 
       SUMMARY OF THE INVENTION 
       [0009]    These and other objects that appear below, are achieved by a digital signal receiver for a high-bitrate digital signal which has a serial signal input and a number of N parallel digital signal outputs with N&gt;1. The receiver contains at least N+1 digital sampling channels, a Q-monitor for comparing the output signal of at least two of said sampling channels, and a switch fabric for controllably connecting N of said sampling channels to said output leads and at least two of said sampling channels to said Q-monitor. 
         [0010]    With such design, it is possible to use N sampling channels to provide the N output signals while at the same time, the at least one remaining sampling channel can be used by the Q-monitor to scan an eye diagram. By using in different measurement runs different of the sampling channels to generate the output signals and to scan an eye diagram, all sampling channels can be scanned one after another and operational parameters such as decision phase and/or threshold value optimized. Switch fabric, sampling channels, and Q-monitor can be controlled by a microcontroller, which can be internal or external to the receiver. 
         [0011]    Compared to existing implementations, the invention is better suited for 40 Gbps and other high rate applications, as less additional hardware needed for the same level of performance, which increases sensitivity, lowers power consumption and real estate needed on silicon. 
         [0012]    A zig-zag or round-robin scheduling reduces the complexity/size of the switch matrix following the decision channels, as only a limited number of cross-points need to be populated. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    Preferred embodiments of the present invention will now be described with reference to the accompanying drawings in which 
           [0014]      FIG. 1  shows the prior art decision circuit with Q-monitor; 
           [0015]      FIG. 2  shows a processor-controlled receiver with Q-monitor; 
           [0016]      FIG. 3   a  shows a receiver with Q-monitor according to the invention; 
           [0017]      FIG. 3   b  shows the receiver of  FIG. 3   a  with an alternate clock generator; 
           [0018]      FIG. 4  shows an eye diagram with optimized decision point; and 
           [0019]      FIG. 5  shows zig-zag scheduling rules used in the preferred embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0020]      FIG. 1  shows a known decision circuit as described above. A received O/E converted analog input signal  10  is fed to two decision circuits  11  and  12 , which are both clocked by a recovered clock signal  16 . The output of the two decision circuits  11 ,  12  is compared by an EXOR gate  13  the output of which is fed to an error counter  14 . The count value represents pseudo errors and is used by a software-driven control unit  15  to adjust the threshold of the decision gate  12 . 
         [0021]    This approach is suitable at moderate bitrates of up to 10 Gbit/s. Higher bitrates typically require parallel processing. 
         [0022]      FIG. 2  shows a receiver with a variable gain amplifier (VGA)  21 , an equalizer (EQ)  22 , a clock recovery circuit  23 , a combined Q-Monitor and demultiplexing circuit  24  and a microcontroller  25 . It should be noted that microcontroller  25  also be external to the receiver and can for instance control a larger number of receivers in a network node. 
         [0023]    A received O/E converted data signal  20  is first amplified by amplifier  21  and fed to equalizer  22 , which compensates for distortions in the signal due to dispersion effects in the optical domain. Equalizer  22  can for instance be implemented as a linear equalizer, a decision-feedback equalizer, or a transversal filter. The equalized signal is branched to clock recovery circuit  23  and Q-monitor and demultiplexing circuit  24 . Clock recovery  23  delivers a recovered clock signal to Q-monitor and demultiplexing circuit  24 , which outputs a recovered signal  26  in parallel format and a pseudo error signal  27  that is read by microcontroller  25 . Responsive to the pseudo error signal  27 , microcontroller determines adjustment parameters  28  for phase and/or threshold of the Q-monitor and demultiplexing circuit  24 . In addition, microcontroller is preferably also capable to generate adjustment parameters  28 ′,  28 ″ for equalizer  22  and amplifier  21 . 
         [0024]    The demultiplexing and Q-monitor circuit  24  and the clock recovery  23  from  FIG. 2  are shown in more detail in  FIG. 3   a . The received signal  20 ′ coming from the optional equalizer  22  in  FIG. 2  is branched to demultiplexing and Q-monitor circuit  24  and to clock recovery  23 . Circuit  24  contains five sampling channels (SC 0  to SC 4 )  31  to  35  receiving in parallel the signal input  20 ′, a switch matrix  36 , an EXOR circuit  37 , an error counter  38 , optional D-flip-flops  40  at the signal output  26  and an optional 1:16 divider for additional clock output. 
         [0025]    The five sampling channels  31 - 35  labeled with SC 0  to SC 4  are decision gates with adjustable phase and threshold values. Each sampling channel contains a sampler, threshold/offset compensation and a phase shifter. The phase shifter has a high accuracy of lower than 0.5 ps per step and allows full 4 UI phase shift with respect to 43 Gbit/s clock. Each sampling channel allows a threshold range covering the entire range of the analog input signal. A practically useful value is ±250 mV. 
         [0026]    In a preferred embodiment, the phase shifters of the sampling channels  31 - 35  are implemented using a simple vector adding approach: Clock signals have a sine wave form. Four copies of the clock signal, mutually shifted by 90°, respectively, are combined in a weighted sum. The result of this weighted sum is again a clock signal but with a phase shift depending on the weighting factors used. By simply adjusting the weighting factors in the phase shifters, any desired phase shifted clock can be created. 
         [0027]    It should be noted that instead of four mutually shifted copies of the input clock, two copies at 0° and 90° would also work, if the weighting factors are allowed to be negative. 
         [0028]    Via the switch matrix  36 , each sampling channel can be alternately connected to the EXOR gate  37  and to one of four parallel output leads  26 . The switch matrix  36  is controlled by microcontroller  25  in such a way that the sampling channels  31 - 35  are connected in alternating order according to a predetermined schedule to the four output leads  26  and the EXOR gate  37 . 
         [0029]    Depending on the schedule used, it is not necessary that all cross points of the switch matrix  36  are populated with switch elements. In the preferred embodiment, a zig-zag schedule as shown in  FIG. 5  is used. The switch matrix is hence populated as shown in  FIG. 3   a . In particular, the switch matrix has the following switch elements:
       three switch elements to switch sampling channels  31 ,  33 , or  35  to a first input of EXOR gate  37 ,   two switch elements to switch sampling channels  32  or  34  to a second input of EXOR gate  37 ,   two switch elements to switch sampling channel  31  or  32  to a first output lead,   two switch elements to switch, sampling channel  32  or  33  to a second output lead,   two switch elements to switch, sampling channel  33  or  34  to a third output lead, and   two switch elements to switch, sampling channel  34  or  35  to a fourth output lead.       
 
         [0036]    A basic switch element, which can be used to advantage in the switching matrix is described in EP 1445863, which is incorporated by reference herein. 
         [0037]    Each decision gate receives the same signal input  20 ′. It should be clear however, that the five decision gates do not operate all simultaneously but shifted in time by an amount corresponding to one bit of the input signal, respectively. To accomplish this, the sampling channels are clocked by an actuating clock of ¼ of the data rate of signal  20 ′ and operate at different phase values of the actuating clock. The clock shift is preferably achieved by setting appropriate phase values in each decision gate. For example four sampling channels that are at a time connected to the output leads via switch matrix  36  can have phase values of 0°, 90°, 180°, and 270°, respectively. In the general case with N output leads, the value by which the phases of the individual sampling channels are mutually shifted will be 2π/N. 
         [0038]    Alternatively, the sampling channels  31 - 35  can operate with different clock signals shifted in time with respect to each other. They can also operate on a clock signal corresponding to the bitrate of the input signal. In the latter case, clock dividers, implemented for example by counters, can be connected before the clock input of the sampling channels, respectively. 
         [0039]    According to a principle of the invention, the fifth sampling channel is at the same time used to scan the eye diagram of another one of the sampling channels. This will be explained in more detail below with reference to  FIG. 5 . 
         [0040]    The data rate is in the preferred embodiment the rate defined for OTU-3, i.e., 43 Gbit/s. The actuating clock is hence 10.75 GHz. 
         [0041]    As an optional improvement of the invention, D (“delay”) flip-flops (DFFS)  40  can be provided at the output leads  26 . A DFF conveys its input to the output when the clock is strobed. The data output is hence posted at the output one clock cycle after it arrives at the input. The DFFs  40  are clocked by the actuating clock signal  26 ′, so that all four parallel output leads  26  convey their respective output signals at the same clock phase. 
         [0042]    Clock signal  26 ′ is further supplied at a clock output lead. In addition, a lower rate clock signal of 1/16 of the actuating clock is derived by clock divider  39  and supplied at a respective low speed clock output to support additional functions (not shown) in the receiver, which are beyond the scope of this invention. 
         [0043]    The output of EXOR gate  37  is fed to error counter  38  and counted as pseudo errors. Microcontroller  25  can read out and reset error counter  38  at predetermined intervals, and uses the error count to adjust phase and/or threshold parameters of the sampling channels  31 - 35  according to an adjustment algorithm. 
         [0044]    Various algorithms to determine from an error rate adjustment parameters are known as such and can be implemented by a skilled reader without undue experimentation. The common principle is to adjust the respective parameters such as decision phase and threshold, equalizer parameters, or amplification in such a way as to minimize the error rate. An algorithm which allows to set initial phase and threshold values is described for example in the unpublished European patent application 05292228 entitled “Method and Apparatus for Controlling the Decision Point of a Receiver for Digital Communication Signals” by C. Haslach, which is incorporated by reference herein. 
         [0045]    The importance of an accurate control of the decision point in a receiver is illustrated by  FIG. 4 , which shows an eye diagram of a received signal after passing a dispersive fiber link. Due to dispersion, adjacent bit values overlap and hence cause wrong decision if the decision point is not accurately set. In particular, eyes  1  and  3  are “wrong” eyes but the optimum decision point defined by decision phase DPH and decision threshold DTH lies in the middle of the “right” eye  2 . 
         [0046]    Coming back to  FIG. 3   a , the function of the clock recovery  23  is to generate and supply a recovered clock for demultiplex and Q-monitor circuit  24 . It basically contains a phase-locked loop consisting of a phase detector  43 , a low pass filter  44  and a voltage controlled oscillator (VCO)  42 . 
         [0047]    VCO  42  delivers a clock signal of 21.5 GHz. Phase detector  43  detects phase offset between a received data pulse and the clock signal from VCO  42  and provides a corresponding adjustment voltage, which after low pass filtering is applied to the control lead of VCO  42 . A divider  46  divides the output clock signal of VCO  42  by  2  and supplies four 10.75 GHz clock signals at 0°, 90°, 180°, and 270°, respectively, as actuating clocks to circuit  24 . 
         [0048]    As already explained, the phase shifters in the sampling channels  31 - 35  create from these mutually shifted clocks a properly phase shifted clock signal through a simple vector addition. The phase shift can be adjusted by adjusting the weighting factors used. 
         [0049]    Alternatively, VCO  42  and phase detector  43  can operate at the full rate of 43 GHz followed by a 1:4 clock divider to generate the 0°, 90°, 180°, and 270° clocks. 
         [0050]    An alternate embodiment of the clock recovery  23  is shown in  FIG. 3   b . In this embodiment, the clock recovery is based on a quarterrate (e.g. 10.75 GHz) quadrature VCO QVCO)  45 , which generates the four clocks with 0°, 90°, 180°, and 270° phase relationship. An EXOR gate  41  is used to generate from the 0° and 90° clock outputs of QVCO  45  a 21.5 GHz clock for phase detector  43 , which is operated in halfrate mode as in  FIG. 3   a.    
         [0051]    An alternative for the clock recovery based on the quarterrate QVCO  25  is to operate the phase detector  43  with a quarterrate clock (e.g. 10.75 GHz). 
         [0052]    An example of the alternating operation of the five sampling channels  31 - 35  is shown in the table of  FIG. 5 . Each line of the table corresponds to measurement run of the Q-monitor. The eye diagram measurement as such is carried out as with a conventional Q-monitor, i.e., by varying phase and/or threshold value of the fifth sampling channel during the measurement run and counting pseudo errors for each phase/threshold configuration. 
         [0053]    A reasonable time for one measurement is between 1 μs and 100 μs, depending on the accuracy for the Q-factor measurement needed by the controlling algorithm. The measurement times may need to be adapted to the noise distribution of the input signal. 
         [0054]    The first four columns indicate which sampling channel is connected through the switch matrix  36  to which one of the four parallel output leads  26 . The five sampling channels are identified as SC 0 , SC 1 , SC 2 , SC 3 , and SC 4  and the parallel output leads are identified as DS 0 , DS 1 , DS 2 , and DS 3 . The fifth column shows, which sampling channels are fed via EXOR gate  37  to error counter  38  during that measurement run. The last column shows, which one of the five sampling channels  31 - 35  is optimized during the measurement run. This is always the sampling channel, which is not connected to one of the output leads and which phase and threshold values are varied during the measurement run to scan its eye diagram. 
         [0055]    So, for instance, in line  1 , SC 0  is connected to DS 0 , SC 1  to DS 2 , SC 2  to DS 3 , and SC 4  to DS 3 . EXOR  37  receives at the same time the output of sampling channels SC 1  and SC 2 , which is not used as an active output is scanned and optimized by microcontroller  25 . 
         [0056]    As can be observed from  FIG. 5 , assignment of only one output signal is changed from one measurement run to the next. This one is shown grey shaded. For instance from line  1  to line  2 , only the sampling channel assigned to output lead DS 2  changes from SC 1  to SC 2 , while now SC 1  is optimized during the next measurement run. 
         [0057]    In  FIG. 5 , this results in a zig-zag pattern, so that this mode of operation is termed zig-zag schedule. It should be clear that other schedules such as round robin or the like can equally be used, depending on how the switching matrix  36  is designed. 
         [0058]    A particular advantage of the described receiver is that it can be used without any modification in the HF-path also for 10 Gbit/s operation by using only one of the sampling channels at a time for data output. 
         [0059]    It should be clear that the invention is not limited to a four bit wide parallel data output, but that any other suitable parallel format could equally be implemented in a similar way. For example, while the shown four bit wide output provides nibbles (half-bytes), a two bit parallel output would supply “crumps” (2 bits) and a eight bit wide output would deliver full bytes per clock cycle. 
         [0060]    It should also be clear that for an N-bit wide output signal, more than N+1 sampling channels could be provided. In this case, several eye diagrams can be measured in parallel. So, for instance for an 8 bit wide output signal, 10 sampling channels could be provided such that 8 operate to generate the parallel output signals while two are used for Q-monitor measurement.