Abstract:
A station arrester employing metal oxide varistors has varistors whose capacitances increase in a direction measured from the ground side of the arrester. An approximately uniform voltage distribution can be produced across the varistors when appropriately graded according to their positions in the varistor stack. In this configuration, the varistor disks located near the top or line end of the stack are not subjected to increased thermal stresses.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to station arresters and more particularly to station arresters including a stack of metal oxide varistors in which the capacitance of the varistors is graded so as to produce a more uniform distribution of voltage throughout the stack. 
     A station arrester is an electrical protective device which acts to protect transmission lines, transformers, and other equipment from excess voltage pulses arising from natural conditions such as lightning or from power system sources such as transient surges. Present station arresters typically comprise a stack of metal oxide varistors disposed in a cylindrical porcelain housing having external fin-like protrusions thereon for increasing the arc path length. The varistors are disposed in a stack; the top most varistor in the stack being connected to a line terminal of the arrester and the bottom varistor being connected to a ground terminal of the arrester. These terminals serve to electrically connect the arrester into the power system it is to protect. Metal oxide varistors are nonlinear resistive devices which under normal conditions exhibit a high resistance value; but which, when subjected to voltages in excess of their breakdown voltages, exhibit a very low resistance thereby acting as a protective device since destructive currents are shunted through the varistor stack. These varistors typically have high energy absorption capabilities and are well suited to act as protective devices. Nonetheless, in the station arrester application, the varistors are subject to the continual presence of the line power voltage. However, this line voltage is typically well below the varistor breakdown voltage. In this normal ambient state, the varistors exhibit a high resistance, but nonetheless some current does flow predominantly but not only by capacitive action. 
     Each varistor in the stack can be approximately modeled by a variable resistor in parallel with a capacitance, C v . Additionally, each varistor in the stack has associated with it a coupling capacitance to ground, C g . This group capacitance is approximately the same for each varistor in the stack. The capacitance C v  associated with each individual varistor is an intrinsic property of metal oxide varistors produced from a sintered mixture of zinc oxide and various metal oxide additives. As a result of the capacitance effect, particularly the ground capacitance, a larger current flows through the top (i.e., line) varistors in the stack since the upper varistors also pass the capacitive ground currents which flow through the lower varistors. A larger current in these upper varistors subjects them to a greater level of power dissipation which results in a higher operating temperature and inferior stability for these varistor disks thereby acting to decrease the actual useful life of the arrester because of premature failures of the upper or line side varistor disks. 
     The conventional solutions to the nonuniform distribution of voltage and watts loss in the varistor stack require the tailoring of the capacitances of varistors by placing them in parallel with low dissipation capacitors. This method is expensive and cumbersome because it involves added costs associated with high voltage capacitors, connectors, and leads and, additionally, because of the requirement for additional space in the arrester housing, which space is expensive to provide because of the high cost of the housing itself. Nonetheless, the net capacitances are graded so that the varistor nearest the line terminal is connected in parallel with a capacitor having a greater capacitance than is the capacitance connected in parallel with a varistor closer to the ground terminal of the stack. 
     SUMMARY OF THE INVENTION 
     In accordance with a preferred embodiment of the present invention, an arrester comprises a housing in which there is disposed a stack of metal oxide varistors, the top of the stack being connected to the line terminal and the bottom of the stack being connected to the ground terminal. The varistors in the stack are graded so that the varistors exhibit increased capacitance with increased proximity to the line terminal. In particular, if the capacitance C vi  of the i th  varistor in the stack is selected to be approximately C O  +C g  (N-i) 2  /2, where N+1 is the number of varistors in the stack, C O  is the capacitance of the varistor connected to the ground terminal, i is an integer indicating the position of the varistor in the stack, and C g  is the ground capacitance for each varistor, then it is found that the voltage distribution across the varistors is approximately uniform. 
     Accordingly, it is the object of the present invention to provide an arrester for surge protection of power transmission lines exhibiting long life and uniform distribution of energy loss in each varistor without the cumbersome necessity for separate grading capacitances. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a partial cross-sectional elevation view illustrating the construction of a typical arrester employing metal oxide varistor disks. 
     FIG. 2 is an electrical circuit diagram illustrating an equivalent circuit for the arrester stack of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 illustrates a conventional station arrester employing a varistor stack. Arrester housing 10 typically comprises a procelain cylindrical structure having finned shaped projections 16 on the exterior thereof to increase the discharge arc path along the exterior of the arrester housing 10. A stack of serially connected metal oxide varistors 11 are disposed along the hollow portion of the housing so that the top varistor is in electrical contact with the line terminal 13 of the arrester and the bottom varistor of the stack is in electrical contact with the ground terminal 14 of the arrester. Also, spacers 15, typically configured as partial annular sections, are conventionally employed internal to the housing. Such spacing material affects the varistor-to-ground capacitance discussed immediately below. The varistors 11 are somewhat spaced apart and electrically connected through the conducting plates 12 typically comprising a soft metal such as lead. 
     As described above, the varistors nearer to the line side of the arrester are subject to greater currents and concomitantly greater voltage drops and watts losses therein predominately because of capacitive currents arising through the varistor-to-ground capacitance, C g , associated with each varistor. A greater appreciation of this phenomenon can be had by examining the equivalent circuit shown in FIG. 2 where the varistor stack and arrester of FIG. 1 are shown. Each varistor in the stack is modeled by variable resistor R vi , i=0, 1, 2, . . . , N, wherein R vO  is that varistor nearest the line end of the stack and R vN  is the varistor nearest the ground end of the stack, there being N+1 varistors in the stack. For the i th  varistor in the stack as counted from the line end, there is associated with each R vi  an intrinsic capacitance C vi , as shown. Additionally, there is associated with each varistor in the stack a varistor to ground capacitance C g  effectively connected between the upper electrode contact of each varistor and the ground plane. The ground capacitance C g  is closely associated with the presence of the housing and is approximately equal for each varistor in the stack as shown. As can be appreciated from FIG. 2, the varistors proximal to the high voltage or line side of the arrester are subject to the capacitive currents which flow not only through the varistor stack directly but also to those currents injected into the varistor stack because of the presence of the ground capacitance. In this manner, the varistors in the upper portions of the stack are subjected to larger currents, greater voltage drops across the varistor and concomitant greater watts losses which accordingly have a more deleterious effect upon stability for those varistors near the line side of the arrester. 
     The problem of variable varistor stability in the stack is significantly reduced by insuring a uniform voltage drop across each varistor in the stack. It is known that by choosing C vi  to be equal to C O  +C g  (N-i) 2  /2 that a uniform voltage drop results. However, as described above, this is conventionally accomplished through the use of separate, lumped capacitive devices connected in parallel with one or more varistors in the stack. However, as indicated, this is a costly cumbersome, and excessively complicated method for insuring uniformity. 
     In accordance with the present invention, the capacitance of the varistors themselves are selected in a graded fashion so that varistors near the line end of the varistor stack exhibit a greater capacitance. There are several methods for achieving this variation in capacitance. First, the thickness of the varistor disk could be changed. Second, the disk breakdown field could be varied while keeping the varistor thickness fixed. Third, the capacitance of a varistor could be chosen for a fixed varistor thickness and breakdown field. The first method mentioned is not desirable since changing the varistor disk thickness changes the capacitive coupling to ground and the thermal coupling to the exterior environment in a fashion which reduces the effectiveness of the method. The second method changes the varistor disk capacitance since it is inversely proportional to the breakdown field at a fixed thickness. However, increasing the breakdown field also increases the watts loss per unit volume since the watts loss per varistor grain boundary is approximately constant. Accordingly, this second method is also not preferred. 
     However, the third method as outlined above is preferred and is readily accomplished through varying the antimony trioxide content of varistor manufacture. 
     In general, the capacitance of a varistor is given by C var  =εF 1  (ε o  A/V 1 ) where F 1  is the breakdown field of the variator, A is the area of the varistor, ε o  is the permitivity of free space, V 1  is the breakdown voltage of the varistor, and ε is the dielectric constant of the varistor material. Thus, it is seen from the aforementioned formula that the capacitance of a varistor may be controlled by varying quantity εF 1  by holding area and the breakdown voltage of the varistor constant. The quantity εF 1  is controllable by varying the antimony trioxide content as shown in the following table. 
     
                       TABLE 1______________________________________Sb.sub.2 O.sub.3 Content            εF.sub.1 × 10.sup.-6(Mole Percent)   (volts/cm)______________________________________1.0              2.152.0              1.145.0              0.566.0              0.378.0              0.2610.0             no varistor action______________________________________ 
    
     The above-mentioned variation in antimony content is produced in a varistor composition having approximately the following constituents: 0.2 mole percent H 3  BO 3 , 0.1 mole percent BaCO 3 , 0.5 mole percent Cr 2  O 3 , 1.0 mole percent NiO, 0.5 mole percent MnO 2 , 0.5 mole percent Co 2  O 3 , 0.5 mole percent Bi 2  O 3 , the remainder being zinc oxide, ZnO. 
     By way of example and not limitation, the following approximate description of the parameters of an arrester are provided. Typical values for the total ground capacitance of a large arrester is approximately 100 picofarads. Hence, in a 30 varistor disk stack, C g  is approximately 3 picofarads (≈100/30). Additionally, the capacitance of a standard production three inch diameter and one inch thick arrester disk is approximately 2,000 picofarads. Assuming that such a conventional varistor disk is the top disk in the stack, the above formula for C vi  is employed to find the capacitance C O  for the bottom varistor in the stack. Applying this formula produces a C O  of 650 picofarads. Thus, such an arrester construction results in a varistor stack with a top disk having a capacitance of approximately 2,000 picofarads and a bottom varistor disk having a capacitance of approximately 650 picofarads, while the other varistor capacitances (in picofarads) are given by C vi  =1.5 (30-i) 2  +650. Other varistor stack designs may also be developed using the foregoing analysis and formulas. 
     It is known that conventional varistor material comprises zinc oxide grains separated by layers of intergranular material. The increased Sb 2  O 3  content promotes the formation of extra insulating material, Zn-Sb spinel, for example in the regions surrounded by zinc oxide grains. The insulating material acts to reduce the εF 1  product. Likewise, additional insulating material may be provided amidst zinc oxide grains by using silicon dioxide (SiO 2 ) or magnesium oxide (MgO) or other refractory materials in the varistor formulation. Suitable amounts of these other refractory materials may be added, these amounts ranging from approximately 1 to approximately 15 mole percent. For example, MgO promotes the formation of Mg-Zn spinel. In this way, varistors exhibiting εF 1  products below approximately 1.5×10 6  volts/cm are easily fabricated. 
     From the above, it may be appreciated that the varistor of the present invention exhibits a uniform voltage distribution across each varistor in the stack thereby resulting in a long-lived varistor stack in which no particular stack varistors are subjected to above normal thermal stresses resulting in loss of stability and device failure. The varistors of the present invention accordingly exhibit a controlled capacitance depending upon the amount of antimony additive present in the varistor mix. 
     While this invention has been described with reference to particular embodiments and examples, other modifications and variations will occur to those skilled in the art in view of the above teachings. Accordingly, it should be understood that within the scope of the appended claims the invention may be practiced otherwise than is specifically described.