Abstract:
A capacitor includes a semiconductor substrate, a bottom conductive pattern, first to third insulating layers, first to third metal plates and a connecting pattern. The bottom conductive pattern is formed on the semiconductor substrate. The first to third insulating layers are formed on the bottom conductive pattern, the first and second metal plates, respectively. The first metal plate is formed on the first insulating layer within a first area. The first metal plate is electrically connected to the bottom conductive pattern. The second metal plate is formed on the second insulating layer within the first area. The second metal plate has an opening in the center thereof. The third metal plate is formed on the third insulating layer. The connecting pattern is formed through the second and third insulating layers and the opening of the second metal plate. The connecting pattern electrically connects the first and the third metal plate.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     A claim of priority is made to U.S. provisional application Ser. No. 60/421,779, filed Oct. 29, 2002, the entire contents of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to the field of integrated circuits that include capacitor arrays, particularly for use in switched-capacitor amplifiers, digital-to-analog converters and analog-to-digital converters. 
     Arrays of precision capacitors are used in various switched capacitor circuits. One example is illustrated in  FIG. 1 , where a switched-capacitor DAC using (n+1) capacitors (C, 2C, . . . , 2 n−1 C, 2 n C) with a common top plate and separate bottom plates is shown. The use of a similar capacitor array of capacitors (C 1 =C, C 2 =2C, . . . , C K+1 =2 K−1 C) in an ADC is presented in  FIG. 2 . In both cases, the values of the capacitances are powers of 2 of a unit capacitance. For matching reasons, the capacitor arrays are built from unit capacitors, interconnected as to provide the appropriate values, and distributed in the array as to compensate for the gradients of the dielectric thickness. In the particular cases shown in  FIGS. 1 and 2 , the top plates of the capacitors of the arrays are common. 
     The conventional arrays of precision capacitors are usually built using polysilicon-polysilicon structures. The ratio of the capacitances is usually of great importance, and in order to compensate for the thickness gradients in the dielectric layer(s), the capacitors are built using unit cells arranged in a common centroid array. This strategy is illustrated in  FIG. 3   b , for a 3-bit ADC built using the schematic of  FIG. 3   a . The capacitors marked  2 ,  4 ,  8  are, respectively, belonging to the capacitors C 2 =2*C, C 4 =4*C, C 8 =8*C. The capacitors with a similar marking are connected in parallel. Because in this array structure the top plate is common, only the bottom plates of the similarly marked capacitors are connected together through dedicated lines. One can also see capacitors marked D (dummy), which have no active role in the array. Their presence enhances the matching of the capacitors in the array, by providing similar surroundings to each unit capacitor. 
     In a digital process, usually there is only one layer of polysilicon available and the precision capacitors are implemented as a sandwiched structure of three metal layers, as shown in  FIG. 4 . The internal layer  14  is the top plate, while the external layers  16  and  18  are connected together and form the bottom plate of the capacitor. Usually, the connection  17  between the layers forming the bottom plate is made at the periphery of each capacitor. 
     When the capacitors are arranged in an array with a common top plate, there is a need to connect the various bottom plates in order to form the required capacitor configurations. In a polysilicon-polysilicon capacitor array, the connection between the bottom plates is usually made in one or more of the metal layers, on top of the capacitor structures. For a metal-metal capacitor, the connection is usually made in an extra layer of metal. 
     When using a metal-metal sandwich structure, the specific capacitance is small and the capacitors occupy a large area of the integrated circuit. Besides the greater level of noise induced into the substrate or collected from the substrate by a big capacitor array, a large percentage of the area is occupied by the connection between the various existing bottom plate layers, thus reducing the useful area allocated to the capacitors and making the layout more difficult. 
     SUMMARY OF THE INVENTION 
     In order to increase the useful area occupied by a metal-metal capacitor sandwich, the present invention discloses a preferably symmetrical three metal layers capacitor structure with a connection between the bottom plate layers made in the center of the structure, through an opening in the central layer. 
     Also provided by the present invention is a method of connecting the capacitors in an array structure, by using uniformly distributed diffusion and/or polysilicon and/or metal lines placed under the capacitor array. 
     A method of building the capacitor array periphery in such a way as to cancel all systematic unit capacitor mismatch is also described. 
     The method of building the capacitor structure and the array of capacitors is most useful in single polysilicon CMOS integrated circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a switched-capacitor digital-to-analog converter. 
         FIG. 2  shows a schematic diagram of a switched-capacitor analog-to-digital converter. 
         FIG. 3   a  is the schematic diagram of the capacitor array of a switched-capacitor 3-bit DAC. 
         FIG. 3   b  illustrates a possible common-centroid layout configuration of the DAC presented in  FIG. 3   a , with the allocation of unit capacitors to the various capacitors. 
         FIG. 4  shows a simplified cross-section of a conventional metal-metal sandwich capacitor structure. 
         FIG. 5  shows a capacitor fabricated in accordance to the present invention. 
         FIG. 6   a  shows a simplified cross-section of a Metal 1 -Metal 2 -Metal 3  sandwich capacitor structure with polysilicon bottom interconnection, built in accordance to the present invention. 
         FIG. 6   b  shows a simplified cross-section of a Metal 1 -Metal 2 -Metal 3  sandwich capacitor structure with diffused bottom interconnection, built in accordance to the present invention. 
         FIG. 6   c  shows a simplified cross-section of a Metal 2 -Metal 3 -Metal 4  sandwich capacitor structure with polysilicon bottom interconnection, built in accordance to the present invention. 
         FIG. 6   d  shows a simplified cross-section of a Metal 2 -Metal 3 -Metal 4  sandwich capacitor structure with Metal 1  and polysilicon bottom interconnections, built in accordance to the present invention. 
         FIG. 7  shows a capacitor array with interconnections for a 3-bit DAC, built according to the present invention. 
         FIG. 8  shows the internal portion of an array of capacitors fabricated in accordance to the present invention and a cross section of this structure. 
         FIG. 9  shows the traditional way of connecting dummy capacitors at the periphery of a capacitor array and a cross section of the structure. The unit capacitors are built in accordance to the present invention. 
         FIG. 10  presents the preferred embodiment of the periphery dummy capacitors and a cross section of the structure. 
         FIG. 11  is an array of 16 matched unit capacitors with 1 common terminal; the array includes the dummy capacitor border built according to this invention. 
         FIG. 12  shows two arrays of matched unit capacitors each array with a common terminal; the array includes the dummy capacitor border built according to this invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The basic capacitor according to this disclosure is shown in  FIG. 5 . The capacitor is built out of a sandwich of three metal plates, in three different metal layers on an oxide layer  520  formed in substrate  510 . Let&#39;s assume, for instance, that the metal layers used are Metal 1  (M 1 ), Metal 2  (M 2 ) and Metal 3  (M 3 ). 
     The capacitor consists of:
         a top plate  570  made of Metal 2  and having an opening  573  in the center and conductive branch members  572 ;   a first bottom plate  550  made of Metal 1 ;   a second bottom plate  590  made of Metal 3 ;   a stack of via  560 , Metal 2  plate  511  and via  561  connecting the first and the second bottom plates through the  573  opening;   a contact structure  540  connecting the first bottom plate  550  to a bottom connection  530  placed between the first metal plate and the substrate.       

     The bottom connection can be made of polysilicon, metal or a diffused layer into the substrate. 
     The capacitor plates, made of metal, can be implemented in any three layers of metal. For the sake of the highest specific capacitance, these three layers have to be consecutive, for instance Metal 1 , Metal 2 , Metal 3 , or Metal 2 , Metal 3 , Metal 4 , but the capacitor can be easily implemented in other metal layers, like Metal 2 , Metal 4  and Metal 5 . 
     In case the capacitor is implemented in Metal 1 , Metal 2  and Metal 3 , the bottom interconnection can be made of polysilicon or of a diffused layer. If the capacitor is implemented in higher layers of metal, then the bottom connection can be made of polysilicon, diffused layer or metal. 
     A regular way of implementing a metal sandwich capacitor uses metal shields around the top layer, thus increasing the overall capacitor area for a given capacitance. Per direction, the extra area is associated with two stacks of vias and metal and the associated clearing spaces in the top plate layer. The capacitor of  FIG. 5  allows a better use of the silicon area, by using only one stack of vias and metal per direction. 
     Usually, several lines of bottom interconnection can be placed under the capacitor structure, allowing the allocation of various unit capacitors to a main capacitor. As an example, this is shown in  FIG. 5  as five 530 lines. Several combinations of metal layers and bottom interconnection layers are shown in a simplified manner in  FIGS. 6   a, b, c , and d.  FIG. 6   a  shows a capacitor built in M 1 , M 2 , M 3 , with bottom interconnection made of polysilicon. In  FIG. 6   b  there is a M 1 -M 2 -M 3  capacitor with bottom interconnections made of an n+ diffusion into a p-substrate.  FIG. 6   c  shows a M 2 -M 3 -M 4  capacitor with polysilicon bottom interconnection.  FIG. 6   d  shows a M 2 -M 3 -M 4  capacitor with M 1  bottom interconnection and an extra interconnection layer in polysilicon, thus allowing more complex bidimensional connections between the bottom plates of the capacitors. 
       FIG. 7  shows an example of using the capacitors of  FIG. 5  in an array built according to this invention, with bottom interconnections and common top plate. The array of capacitors includes the capacitors  711 ,  712 ,  713 ,  721 ,  722 ,  723 ,  731 ,  732 ,  733 ,  741 ,  742 ,  743 ,  751 ,  752 ,  753 ,  761 ,  762 ,  763  of identical structure and size. As an example, the capacitors can be built with Metal 1 , Metal 2  and Metal 3  plates, with bottom interconnections made of polysilicon. The capacitors are arranged in a 6 rows by 3 columns matrix. There are 1+1+2+4+8=16 active capacitors and two dummy capacitors ( 712  and  762 ). Each column of capacitors has four bottom interconnection lines:  7101 ,  7102 ,  7103 ,  7104  for the  711 ,  721 , . . . ,  761  capacitors;  7201 ,  7202 ,  7203 ,  7204  for the  712 ,  722 , . . . ,  762  capacitors;  7301 ,  7302 ,  7303 ,  7304  for the  713 ,  723 , . . . , 763  capacitors. The unit capacitors allocation is as following:
         to the C 8  capacitor:  711 ,  721 ,  751 ,  761 ,  713 ,  723 ,  753 ,  763 ;   to the C 4  capacitor:  731 ,  741 ,  733 ,  743 ;   to the C 2  capacitor:  722 ,  752 ;   to the C 1   a  capacitor:  732 ;   to the C 1   b  capacitor:  742 .       
     The multiple-unit capacitors C 2 , C 4 , C 8  are built in a common-centroid manner. 
     The bottom plates of the capacitors  711 ,  721 ,  751  and  761  belonging to the C 8  capacitor are connected through the bottom connection  7103 , accessible both from the top and from the bottom of the capacitor array. 
     The bottom plates of the capacitors  711 ,  721 ,  751  and  761  belonging to the C 8  capacitor are connected through the bottom connection  7102 , accessible both from the top and from the bottom of the capacitor array. 
     The bottom plates of the capacitors  731 ,  741  belonging to the C 4  capacitor are connected through the bottom connection  7103 , accessible from the top of the capacitor array. The bottom line  7103  is broken between the capacitors  741  and  751 , allowing the use of the bottom portion for other connections. 
     The bottom plates of the capacitors  733 ,  743  belonging to the C 4  capacitor are connected through the bottom connection  7303 , accessible from the top of the capacitor array. The bottom line  7303  is broken between the capacitors  743  and  753 , allowing the use of the bottom portion for other connections. 
     The bottom plates of the capacitors  722 ,  752  belonging to the C 2  capacitor are connected through the bottom connection  7203 , accessible from both the top and the bottom of the capacitor array. 
     The bottom plate of the capacitor  732  being the only component of the C 1   a  capacitor is connected through the bottom connection  7202 , accessible from the top of the capacitor array. The bottom line  7202  is broken under the capacitor  742 , allowing the use of the bottom portion for other connections. 
     The bottom plate of the capacitor  742  being the only component of the C 1   b  capacitor is connected through the bottom connection  7201 , accessible from both the top and the bottom of the capacitor array. 
     The bottom lines corresponding to unit capacitors belonging to the same capacitor can be connected outside the main capacitor array. The common top plate can also be connected outside the main capacitor array. 
     For certain configurations, it is possible to have capacitors in the array with different top plate connections. 
     The capacitors  712  and  762  do not belong to the 3-bit DAC, but their presence does improve the matching of the active capacitors. In order for the active capacitors to see the same surroundings, dummy capacitors can be added to the array, following well established layout techniques. 
       FIG. 8  shows the internal portion of an array of capacitors fabricated in accordance to the present invention and a cross section of this structure. The middle layer terminal of each capacitor (top capacitor plate) is separated and is denoted in gray. The black center square of each unit capacitor represents the contact between the top and the bottom conductive layers that form the bottom capacitor plate. The whole array is equivalent to a multi-terminal capacitor due to the fact that the unit capacitors are close to each other and the electrical field of one can influence the charges on the neighboring capacitors. The cross section from  FIG. 8  shows the different terminals of this multi-terminal capacitor. If one grounds all terminals except T 4 , the total capacitance of T 4  will be the sum of the different mutual capacitances. If we take into consideration a bi-dimensional case and neglect the capacitances related to other terminals except the ones presented in the cross section then:
   C   3   =C   30   +C   31   +C   32   +C   34   +C   35   +C   36   
     Where: 
     C 30  is the parasitic capacitance of terminal T 4  to ground, C mn  is the capacitance between terminal TM and TN where M=1,6 and N=1,6. 
     Due to the symmetry of the capacitor C 31 =C 35  and C 32 =C 36 , C 34  is the useful capacitance, C 30  is the main bottom plate capacitance and all other capacitances are related to the neighboring unit capacitors. Let&#39;s define C u =C 34 , C b =C 30 , C nbt =C 31  and C ntt =C 32 . 
     The usual way to build a well-balanced and matched array of capacitors is to place at the periphery a border of dummy devices that will compensate for non-uniform etching and other neighboring-related non-idealities.  FIG. 9  shows the traditional way of connecting dummy capacitors at the periphery of a capacitor array. The unit capacitors are built in accordance to the present invention. The whole dummy capacitor border is connected to a terminal denoted G in  FIG. 9 . This is usually ground but can be used by the designer as an extra terminal of the capacitor array. All non-dummy unit capacitors have a common top terminal (denoted M in  FIG. 9 ). If we use the cross section from  FIG. 9  and use a bi-dimensional approximation, we can calculate the capacitance between A and M and between B and M:
 
 C   AM   =C   u   +C   nbt  and  C   BM   =C   u +2 ×C   nbt 
 
     Where C u  and C nbt  were defined above. 
     This shows that the two capacitances C AM  and C BM  are not well matched due to the dummy capacitor tied to G. 
       FIG. 10  shows a possible solution to match the two array capacitances. The new dummy edge capacitor denoted E in  FIG. 10  has three conductive regions defined in the middle layer (the one used for the top unit capacitor terminal). The right-most region denoted M is tied to the common terminal of the capacitor array denoted also M. The middle region is tied to terminal G (usually ground). The left-most region (denoted F) can be left floating or tied to other terminal or even to ground. This part plays no electrical role. In the case in which matching due to non-uniform etching or other neighboring-related effects is good enough, this left part of the dummy edge capacitor can be even omitted. 
     In this case, by analyzing the cross section we obtain:
 
 C   AM   =C   u +2 ×C   nbt  and  C   BM   =C   u +2 ×C   nbt 
 
     Where C u  and C nbt  were defined above. 
     This shows that C AM =C BM  and the whole array of unit capacitors is well matched. 
       FIG. 11  shows an array of 16 matched unit capacitors (e.g. one unit capacitor is denoted I) with 1 common top terminal. The edge dummy cells (E) are present at the periphery of the array as described before. This array uses only half size dummy capacitors as described before. The corner dummy capacitors (C) can be built on the same principle as the edge dummy capacitors (i.e. with the middle layer connected to the common terminal of the array. Due to the fact that the capacitance between two neighboring corners is much smaller that the one between two neighboring edges, the good enough solution, as shown in  FIG. 11  is to use all three layers of the dummy capacitor tied to G. 
       FIG. 11  shows also how to extract the top terminal of the capacitor array using the edge cell denoted M. This half of the unit capacitor adds about C u /2 to the parasitic capacitance between the array&#39;s top plate and ground. 
       FIG. 12  shows two arrays (A 1  and A 2 ) of matched unit capacitors (e.g. I) each array with a common terminal. The external edge (E 1 ) and corner (C) dummy capacitors are fully drawn (not half as in  FIG. 11 ). The internal border dummy capacitors (e.g. E 1 ) are used to separate the two top plates of the arrays A 1  and A 2 . The M 1  and M 2  edge capacitors are used to route the top plate of each array. 
     The principles presented above f or ensuring a top terminal layer of the edge and corner cells connected to the array&#39;s top terminal can be used to build also non-rectangular arrays or groups of arrays.