Abstract:
A data sorting device and a method thereof are disclosed, wherein the data sorting device includes plural storage modules and an enabling controller. Moreover, each storage module has a falling edge-triggered register and a rising edge-triggered register, and each storage module receives a serial data in response to the rising edge of clock and the falling edge of clock. Furthermore, the enabling controller is connected with each storage module for enabling each storage module by sequence turns in response to the trigger of the rising edge of clock.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention is related to a data sorting device and a method thereof, and more particularly to a device and a method for maintaining the correct sorting of serial data under DDR (Double Data Rate) transmission. 
         [0003]    2. Description of the Related Art 
         [0004]    Please refer to  FIG. 1 , which is a schematic view showing the conventional shift register. The shift register  1  is constituted by a first register  10 , a second register  12 , a third register  14  and a fourth register  16 , and is a 4-bit shift register. The shift register  1  is triggered by clock clk 1  or clk 2  for receiving serial data serial_data, and then, the received serial_data is submitted to output terminals Q 0 ˜Q 3 . However, since the serial data serial_data submitted to the output terminals Q 0 ˜Q 3  is triggered by the flip flop in the shift register in response to different phase clocks clk, this might cause the serial data to be outputted in an altered data sort. 
         [0005]    Please refer to  FIG. 2 , which shows the clocks. When the first data S 1  of the serial data serial_data is transmitted, owing to different trigger phases, the clock is divided into clock clk 1  and clock clk 2 . When the first data S 1  of the serial data serial_data is triggered by the falling edge of clock clk 1  at time t 0 , the first data S 1  will be transmitted to the second register  12 , and when the second data S 2  of the serial data serial_data is triggered by the rising edge of clock clk 1  at time t 1 , the second data will be transmitted to the first register  10 . Then, when the third data S 3  of the serial data serial_data is triggered by the falling edge of clock clk 1  at time t 2 , the third data will be transmitted to the second register  12 , and the first data S 1  in the second register  12  will be transmitted to the fourth register  16 . Continuously, when the fourth data S 4  of the serial data serial_data is triggered by the rising edge of clock clk 1  at time t 3 , the fourth data will be transmitted to the first register  10 , and the second data S 2  in the first register  10  will be transmitted to the third register  14 . Therefore, at time t 3 , the serial data serial_data collected by the shift register  1  and submitted to the output terminals Q 0 ˜Q 3  of the registers  10 ˜ 16  may have a sequence of S 4 , S 3 , S 2 , S 1 . 
         [0006]    Moreover, when the first data S 1  of the serial data serial_data is triggered by the rising edge of clock clk 2 , the first data S 1  will be transmitted to the first register  10  at time t 0 , and when the second data S 2  of the serial data serial_data is triggered by the falling edge of clock clk 2 , the second data S 2  will be transmitted to the second register  12  at time t 1 . Then, when the third data S 3  of the serial data serial_data is triggered by the rising edge of clock clk 2 , the third data S 3  will be transmitted to the first register  10  at time t 2 , and the first data S 1  in the first register  10  will be transmitted to the third register  14 . Continuously, when the fourth data S 4  of the serial data serial_data is triggered by the falling edge of clock clk 2 , the fourth data S 4  will be transmitted to the second register  12  at time t 3 , and the second data S 2  in the second register  12  will be transmitted to the fourth register  16 . Therefore, at time t 3 , the serial data serial_data collected by the shift register  1  and submitted to the output terminals Q 0 ˜Q 3  of the registers  10 ˜ 16  may have a sequence of S 3 , S 4 , S 1 , S 2 . 
         [0007]    Consequently, when utilizing the shift register  1  to collect serial data serial_data, the sequence of the serial data collected by the shift register  1  might be changed since the first data S 1  might be triggered by the rising edge or the falling edge of clock. For solving this problem, an additional phase detector is used for detecting the clock phase. However, the cost is also increased. 
         [0008]    Thus, under SMIA (Standard Mobile Imaging Architecture) standard, for avoiding from using the phase detector, it defines that under DDR transmission, the first data S 1  of the serial data serial_data has to be triggered by the falling edge of clock. 
         [0009]    However, only if the first data S 1  is not triggered by the falling edge of clock owing to any accident of transmitter, substrate, board or system, the sort of the serial data serial_data will be disordered, so that a success decryption for producing synchronization code from the serial data serial_data can not be achieved, thereby causing the whole system disordered and uncovered. 
       SUMMARY OF THE INVENTION 
       [0010]    The object of the present invention is to provide a data sorting device and a method thereof for maintaining the correct sort of serial data under DDR (Double Data Rate) transmission, so as to solve the problem that the sort of the serial data might be altered since the first data S 1  of the serial data might be triggered by the falling edge or the rising edge of clock. 
         [0011]    The present invention provides a data sorting device including plural storage modules and an enabling controller, wherein each storage module has a falling edge-triggered register and a rising edge-triggered register, and each storage module is triggered by a rising edge of a clock and a falling edge of the clock to receive a serial data, and the enabling controller is connected with each storage module for enabling each storage module in turn in response to the trigger of the rising edge of the clock. 
         [0012]    In the data sorting device described above, the enabling controller is utilized to enable the first storage module in response to the trigger of the falling edge of the clock. If the first data of the serial data obeys the SMIA standard, the first data will be transmitted through the trigger of the falling edge of clock, the second data will be transmitted through the trigger of the rising edge of clock, the third data will be transmitted through the trigger of the falling edge of clock, and so forth, wherein after the even-th data of the serial data serial_data is transmitted, the enabling controller will enable the next storage module (the second storage module), so that the serial data serial_data can have a sequence identical to the inputted serial data serial_data. 
         [0013]    In another aspect, if the first data of the serial data serial_data does not obey the SMIA standard, the first data will be transmitted through the trigger of the rising edge of clock, the second data will be transmitted through the trigger of the falling edge of clock, the third data will be transmitted through the trigger of the rising edge of clock, and so forth, wherein after the odd-th data of the serial data serial_data is transmitted, the enabling controller will enable the next storage module (the second storage module), so that the serial data serial_data can still have a sequence identical to the inputted serial data serial_data. 
         [0014]    Consequently, according to the present invention, the method of utilizing the rising edge of the clock to trigger the enabling controller to enable each storage module can maintain the correct sort of serial data without the extra phase detector even when the transmission does not obey the SMIA standard. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The foregoing aspects and many of the attendant advantages of this application will be more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: 
           [0016]      FIG. 1  is a schematic view showing the architecture of conventional shift register; 
           [0017]      FIG. 2  shows the clock phases; 
           [0018]      FIG. 3  is a schematic view showing the architecture of data sorting device according to the present invention; 
           [0019]      FIG. 4  shows the clock phases; 
           [0020]      FIG. 5  is a flow chart showing the method for sorting serial data according to the present invention; and 
           [0021]      FIG. 6  is another flow chart showing the method for sorting serial data according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0022]    Please refer to  FIG. 3 , which is a schematic view showing a data sorting device according to the present invention. In this embodiment, it takes the  4  bit output as example. The data sorting device  2  includes a first storage module  20 , a second storage module  22  and an enabling controller  24 . However, it should be noted that for increasing the number of output bit, the number of storage module also should be increased. 
         [0023]    Please refer to  FIG. 3 . The first storage module  20  include a first falling edge-triggered register  200  and a first rising edge-triggered register  202 , wherein the registers  200 ,  202  are both D-typed flip flop. The first falling edge-triggered register  200  is triggered by the falling edge of a clock clk, so as to receive a serial data serial_data, and the first rising edge-triggered register  202  is triggered by the rising edge of the clock clk, so as to receive the serial data serial_data. 
         [0024]    Furthermore, the second storage module  22  include a second falling edge-triggered register  220  and a second rising edge-triggered register  222 , wherein the registers  220 ,  222  are both D-typed flip flop. The second falling edge-triggered register  220  is triggered by the falling edge of the clock clk, so as to receive the serial data serial_data, and the second rising edge-triggered register  222  is triggered by the rising edge of the clock clk, so as to receive the serial data serial_data. Besides, the enabling controller  24  is connected to the first storage module  20  and the second storage module  22 , and can enable the first storage module  20  and the second storage module  22  in turn in response to the rising edge of the clock clk. 
         [0025]    Please refer to  FIG. 4 , which shows the clock phase, wherein owing to different trigger phases, when the first data S 1  of the serial data serial_data is transmitted, the clock is divided into clock clk 1  and clock clk 2 . The first data S 1  of the serial data serial_data is transmitted under SMIA standard and triggered by the falling edge of the clock clk 1 , and the first storage module  20  is enabled, so that at time t 0 , the first data S 1  is transmitted to the first falling edge-triggered register  200 . Then, the second data S 2  of the serial data serial_data is triggered by the rising edge of clock clk 1  at time t 1  and is transmitted to the first rising edge-triggered register  202 . In addition, in response to the trigger of the rising edge of the clock clk 1 , the enabling controller  24  enables the second storage module  22 . 
         [0026]    Moreover, the third data S 3  of the serial data serial_data is triggered by the falling edge of clock clk 1  at time t 2 , and is transmitted to the second falling edge-triggered register  220 . Then, at time t 3 , the fourth data S 4  of the serial data serial_data is triggered by the rising edge of clock clk 1 , and is transmitted to the second rising edge-triggered register  222 . Therefore, at time t 3 , the serial data serial_data collected by the data sorting device  2  and submitted the output terminals Q 0 ˜Q 3  of the first storage module  20  and the second storage module  22  can have a sequence of S 1 , S 2 , S 3 , S 4 . 
         [0027]    In another aspect, when the first data S 1  of the serial data serial_data is not transmitted under SMIA standard and is triggered by the falling edge of the clock clk 2 , the first data S 1  will be transmitted to the first rising edge-triggered register  202  at time t 0 , and in response to the trigger of the rising edge of the clock clk 2 , the enabling controller  24  enables the second storage module  22 . Then, the second data S 2  of the serial data serial_data is triggered by the falling edge of clock clk 2  at time t 1  and is transmitted to the second falling edge-triggered register  220 . Then, the third data S 3  of the serial data serial_data is triggered by the rising edge of clock clk 2  at time t 2  and is transmitted to the second rising edge-triggered register  222 , and again, in response to the trigger of the rising edge of clock clk 2 , the enabling controller  24  enables the second storage module  22 . Then, at time t 3 , the fourth data S 4  of the serial data serial_data is triggered by the falling edge of clock clk 2 , and is transmitted to the first falling edge-triggered register  200 . Therefore, at time t 3 , the serial data serial_data collected by the data sorting device  2  and submitted to the output terminals Q 0 ˜Q 3  of the first storage module  20  and the second storage module  22  can have a sequence of S 4 , S 1 , S 2 , S 3 . 
         [0028]    Accordingly, if the first data S 1  of serial data serial_data obeys the SMIA standard, the first data S 1  will be transmitted through the trigger of the falling edge of clock clk 1 , the second data S 2  will be transmitted through the trigger of the rising edge of clock clk 1 , the third data S 3  will be transmitted through the trigger of the falling edge of clock clk 1 , and so forth, wherein after the even-th data of the serial data serial_data is transmitted, the enabling controller  24  will enable the second storage module  22 , so that the serial data serial_data outputted at the output terminals Q 0 ˜Q 3  of the first storage module  20  and the second storage module  22  can have a sequence identical to the inputted serial data serial_data. 
         [0029]    In another aspect, if the first data S 1  of the serial data serial_data does not obey She MIA standard, the first data S 1  will be transmitted through the trigger of the rising edge of clock clk 2 , the second data S 2  will be transmitted through the trigger of the falling edge of clock clk 2 , the third data S 3  will be transmitted through the trigger of the rising edge of clock clk 2 , and so forth, wherein after the odd-th data of the serial data serial_data is transmitted, the enabling controller  24  will enable the first storage module  20 , so that the serial data serial_data outputted at the output terminals Q 0 ˜Q 3  of the first storage module  20  and the second storage module  22  can still have a sequence identical to the inputted serial data serial_data. 
         [0030]    Please refer to  FIG. 5 , which is a flow chart showing the method for sorting the serial data according to the present invention. In this method, first, under SMIA standard, the first data S 1  is transmitted to the first storage module by the trigger of the falling edge of clock (S 100 ). Then, in response to the trigger of the rising edge of clock, the second data S 2  is transmitted to the first storage module, and at the same time, the rising edge of clock enables the second storage module (S 102 ). Then, in response to the trigger of the next falling edge of clock, the third data S 3  is transmitted to the enabled second storage module (S 104 ). Finally, in response to the trigger of the next rising edge of clock, the fourth data S 4  is transmitted to the second storage module, and the third storage module is also enabled (S 106 ). In accordance with this method, under SMIA standard, if the serial data including S 1 ˜SN data is transmitted, the sequence in transmission will be S 1 , S 2 , S 3 , S 4  . . . SN. 
         [0031]    Please refer to  FIG. 6 , which is another flow chart showing the method for sorting serial data according to the present invention. First, without obeying SMIA standard, the first data S 1  is transmitted to the first storage module by the trigger of the rising edge of clock, and at the same time, the rising edge of clock enables the second storage module (S 200 ). Then, in response to the trigger of the falling edge of clock, the second data S 2  is transmitted to the second storage module (S 202 ). Then, in response to the trigger of the next rising edge of clock, the third data S 3  is transmitted to the enabled second storage module, and at the same time, the rising edge of clock enables the third storage module (S 204 ). Finally, in response to the trigger of the next falling edge of clock, the fourth data S 4  is transmitted to the third storage module (S 206 ). In accordance with this method, without obeying SMIA standard, if the serial data including S 1 ˜SN data is transmitted, the sequence in transmission still will be S 1 , S 2 , S 3 , S 4  . . . SN. 
         [0032]    In the aforesaid, the present invention provides a data sorting device and a method thereof which utilizes the architecture and operation procedure of robust for sorting the serial signal produced by SubLVDS sequence, so that even the first data of the serial signal does not obey the SMIA standard due to accident (triggered by falling edge of clock), the whole serial data still can maintain the original sequence without phase detector. 
         [0033]    Consequently, the data sorting device and the method thereof provided by the present invention can maintain a correct sort of serial data under DDR transmission, so as to solve the problem that the sequence sort of the first data may change due to the transmission thereof is triggered by the rising edge or by the falling edge of clock, and at the same time, to omit the phase detector. 
         [0034]    It is to be understood, however, that even though numerous characteristics and advantages of the present application have been set forth in the foregoing description, together with details of the structure and function of the application, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the application to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.