Abstract:
In an internal combustion engine, the magnitude of the engine load is compared with a reference level which is variable as a function of engine speed to detect when the engine load under low speed operation is small in proportion to the engine speed. Under these circumstances, fuel supply to a portion of the cylinders is blocked to allow the engine to run on a lesser number of cylinders so that fuel economy is achieved.

Description:
FIELD OF THE INVENTION 
     The present invention relates to method and apparatus for operating an internal combustion engine on cylinders of reduced number under light load condition to provide fuel economy, while operating it on full cylinders under heavy load condition to provide power. 
     BACKGROUND OF THE INVENTION 
     Internal combustion engines are conventionally operated on full cylinders regardless of the magnitude of the engine load and it is the mixture ratio of air to fuel supplied to the engine that determines the power necessary for the vehicle. However, from the fuel economy standpoint it is unsatisfactory to operate an engine on full cylinders under light load or cruising drive. 
     Since electronic fuel injection is capable of providing accurate proportioning of air-fuel mixture for each cylinder in response to engine operating parameters, it is advantageous to utilize the capability of the electronic fuel injection to switch the operating mode of the engine cylinders in response to the varying engine loads. 
     Copending U.S. Pat. application No. 724,082 filed on Sept. 16, 1976 now patent No. 4,064,844 discloses a system which permits the engine to run on full cylinder operation until the vehicle speed rises above approximately 30 kilometers per hour. Although the full cylinder operation during low speed drive avoids undesirable engine vibration which could become appreciable if the engine should run on three cylinders at lower speed level, the fuel cut-off range is only limited to highway drive. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to achieve fuel economy for internal combustion engines during low speed operation by cutting off fuel supply to part of the cylinders when engine load is relatively small in relation with vehicle speed. 
     Another object of the invention is to provide method and apparatus in which engine load is compared with a reference threshold to determine when the engine load is relatively small in comparison with the engine speed. The reference threshold is variable as a function of the engine speed so that the threshold is low at low engine speed and increases therewith until it reaches a medium speed level. When the engine load is below the variable threshold with the engine running at low speed, fuel supply is cut off to part of the cylinders so that the engine runs on the rest of the cylinders. 
     In accordance with the invention, an internal combustion engine is provided with a load sensor and an engine speed sensor. Function generators are connected to the speed sensor to provide an output from each of the generators. The output from one of the function generators has a nonlinear characteristic as a function of the engine speed and the output from the other function generator has a similar nonlinear characteristic with the amplitude lower than the amplitude of the output from the first-mentioned function generator. Specifically, each output increases as the engine speed increases until it reaches medium speed. The outputs from these function generators are applied to first and second comparators, respectively, as high and low threshold levels for comparison with the sensed engine load. When the engine load is below the lower threshold level, an output is delivered from the respective comparator to a logic control circuit which disables a predetermined number of cylinders, and when the engine load lies between the high and low threshold level the working cylinders are maintained in the same condition as in the previous operational mode. When the engine load rises above the higher threshold level, the logic circuit switches the operational mode so that active cylinders are increased to give more power. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other objects, features and advantages of the present invention will be understood from the following description when read in conjunction with the accompanying drawings, in which: 
     FIG. 1 is an embodiment of the present invention; 
     FIG. 2 is a graphic representation of the nonlinear output characteristic of function generators used in the embodiment of FIG. 1; 
     FIGS. 3 and 3A are timing diagrams useful for describing the operation of the embodiment of FIG. 1; 
     FIG. 4 is a modification of the embodiment of FIG. 1; and 
     FIG. 5 is a modification of the embodiment of FIG. 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIG. 1, an electronic fuel injection system embodying the invention is illustrated. A load sensor 1 is provided to detect the pressure depression in the intake manifold, or air-flow volume per unit revolution of the engine, to provide a signal which represents the magnitude of the detected engine load to an inverting input of comparators 5 and 6. The engine RPM is detected by a sensor 2 and the signal representing the engine RPM is applied to function generators 3 and 4. The function generator 3 is designed to provide an output whose amplitude has a characteristic change as a function of the input signal. As indicated by the curve F 1  of FIG. 2, the output from the function generator 3 increases linearly as the engine RPM increases and levels off when the engine reaches approximately 2000 RPM. The output from the function generator 3 corresponds to the intake vacuum (mm Hg) so that it represents a variable reference level with which the input variable sensed by the load sensor 1 is compared. Therefore, the engine load is compared with a lower reference level until 2000 RPM is reached than when the engine RPM exceeds that speed level. The function generator 4 is designed to provide an output characteristic curve as indicated by curve F 2 , which is similar to the curve F 1  except that the level of the output is lower than the curve F 1 , so that the voltage delivered from the function generator 3 when the engine RPM is 3000 corresponds to an intake vacuum pressure of -100 mm Hg whereas the voltage delivered from the function generator 4 corresponds to an intake vacuum pressure of -200 mm Hg. Therefore, the difference in output voltage between function generators 3 and 4 corresponds to a difference in vacuum pressure of 100 mm Hg. 
     The outputs from the function generators 3 and 4 are connected to the noninverting of the comparators 5 and 6, respectively, for comparison with the sensed engine load. Comparator 5 provides a high voltage level output when the engine load is lower than the reference setting level determined by the function generator 3 and a low voltage level output when the situation is reversed. Similarly, comparator 6 provides a high voltage level output when the engine load is lower than the reference setting level determined by the function generator 4 and a low voltage level output when the situation is reversed. 
     The outputs from the comparators 5 and 6 are both at the high voltage level or &#34;1&#34; logic state when the engine load as represented by intake vacuum is lower than the setting level determined by the curve F 2  of function generator 4 and both at the lower voltage level or &#34;0&#34; logic state when the engine load is higher than the setting level determined by the curve F 1  of function generator 3. 
     When the engine load lies between the levels set by function generators 3 and 4, comparator 5 output is &#34;1&#34; while comparator 6 output is &#34;0&#34; so that AND gate 8 is activated. 
     The engine is assumed to have been started at time t 0  (see FIG. 3) and the engine load is higher than the reference level F 1  until time t 1 . During this time interval, comparators 5 and 6 provide &#34;0&#34; output so that AND gates 7 and 8 remain in the low or &#34;0&#34; output state (FIGS. 3d to 3g). 
     The outputs from the AND gates 7 and 8 are connected to the J and K input terminals of flip-flops 9 and 10, respectively. Flip-flops 9 and 10 are both synchronized with a clock signal supplied to their clock terminals CL from an electronic fuel injection control unit 11. This clock signal is also used as a fuel injection signal for the fuel injectors No. 4, No. 5 and No. 6 so that they are ignited at the same timed intervals, while the injectors No. 1, No. 2, and No. 3 are activated simultaneously with different timing from the injectors No. 4 to No. 6. The injection pulses supplied to the No. 1 to No. 3 injectors are termed injection signal A and those supplied to the No. 4 to No. 6 injectors are termed injection signal B and both signals are supplied from the control unit 11 (FIGS. 3b, 3c). 
     During the time interval t 0  to t 1 , flip-flops 9 and 10 remain in the same logic state and provide high voltage level Q outputs (FIGS. 3h and 3i). The Q outputs of flip-flops 9 and 10 are connected to AND gates 15 and 13, respectively. AND gate 13, when enabled by the Q output from the flip-flop 10, passes the clock signal to AND gates 14 and 15, and thence to the up- and down-count terminals of an up-down or forward-backward counter 18, respectively. The output of the counter 18 is coupled to the AND gate 15 and the inverted output of the counter 18 by means of an inverter 19 is coupled to the AND gate 14 and also over lead 20 to an AND gate 21 to which is also applied the clock or injection signal B. The output from the AND gate 21 is connected to the No. 4 injector. 
     With the Q output of flip-flop 10 being at the &#34;1&#34; logic state, AND gate 13 is enabled to pass the clock pulses to AND gates 14 and 15. During this initial time period t 0  to t 1 , the output from the forward-backward counter 18 is still in the &#34;0&#34; logic level and thus AND gates 14 and 15 are in the &#34;0&#34; logic state and AND gate 21 is enabled so that all the injectors are supplied with injection control signals. Therefore, it should be understood that when the engine load is above the higher setting level F 1  during the initial starting period, i.e. when the engine is operating under heavy load condition with its crankshaft revolution relatively low, all the cylinders of the engine are brought into full operation to give maximum output power. 
     When the engine load falls below the setting level F 1 , but lies above the lower setting level F 2  at time t 1 , comparator 5 is switched to the high output state while comparator 6 remains in its low output state, resulting in the AND gate 8 providing a &#34;1&#34; output. With AND gate 8 being switched to &#34;1&#34;, clock pulse B1 that occurs immediately after time t 1  causes flip-flop 10 to change the binary state of its Q output to &#34;0&#34;, disabling AND gate 13. 
     At time t 2  the engine load falls below the lower setting level F 2  and consequently comparator 6 is switched to the high output state. The output of AND gate 7 goes high and that of AND gate 8 goes low. Clock pulse B2 that occurs immediately after time t 2  changes the binary state of flip-flops 9 and 10. AND gates 13 and 14 are thus enabled and clock pulse B3 which occurs subsequent to pulse B2 is applied to the up-count input of counter 18 with the result that the output thereof goes high at time t 3 . With the counter output being at the &#34;1&#34; logic state, AND gate 14 is disabled to prevent the application of subsequent clock pulses to the up-count input, and the AND gate 21 is disabled. Therefore, during the time interval t 1  to t 3  the 6-cylinder ignition mode is maintained. 
     From time t 2  onward the engine runs under light load condition with its crankshaft revolution relatively high, No. 4 injector is disabled and the vehicle runs on five cylinders. 
     It is assumed that the vehicle speed has decelerated after time t 3  and accelerated again at time t 4  so that the vehicle speed or RPM is relatively low in comparison with the engine load. With the engine load exceeding the lower setting level F 2  at time t 4 , the comparator 6 output goes low and AND gate 8 provides &#34;1&#34; output. Clock pulse B4 occurring after time t 4  switches the flip-flop 10 so that its Q output goes low. As a result AND gate 13 is disabled. 
     At time t 5  the engine load exceeds the higher setting level F 1  to enable the comparator 5 to be switched to the low output state and AND gates 7 and 8 are also switched to the &#34;0&#34; logic state. Clock pulse B5 subsequent to time t 5  switches the flip-flops 9 and 10 so that their Q outputs assume a high voltage level, causing AND gate 13 to be enabled. Since the output state of the counter 18 is in the &#34;1&#34; logic state, AND gate 15 is also enabled and a subsequent clock pulse B6 is applied to the down-count input of the counter 18, so that the output of the counter 18 changes to the &#34;0&#34; state at time t 6 . This enables AND gate 21 so that the engine&#39;s operational mode is again switched to the 6-cylinder mode at time t 6  &#39; in response to the subsequent injection pulse B7. 
     During time interval t 6  to t 7 , engine load is above the higher setting level F 1  and during interval t 7  to t 8  it lies between the high and low setting levels as during the interval t 1  to t 2 . The engine runs on six cylinders until time t 9 . As the engine runs at low city traffic speeds the outputs from the function generators 3 and 4 gradually decrease as illustrated in FIG. 3A-a, and if the engine load is assumed to decrease below the decreasing lower threshold lever F 2  as illustrated, the No. 4 cylinder injector is disabled at time t 9  and the engine runs on five cylinders from then on. 
     Flip-flops 9 and 10 are designed to change their binary state in response to the trailing edge of the injection pulse. This guarantees against the generation of injection pulses having different pulse duration from that determined by the electronic fuel injection control unit 11. 
     A modification of the previous embodiment is shown in FIG. 4 in which the maximum number of disabled cylinders is three instead of one and disabling is effected on a one-cylinder-at-a-time basis in step with successive injection pulses. In the modification of FIG. 4 identical parts to those shown in FIG. 1 are omitted for the sake of simplicity, only the modified parts being illustrated. The Q and Q outputs of the flip-flop 9 are connected to AND gates 30 and 31, respectively, to which is also connected the output from AND gate 13 for application of clock or injection signal B to forward-backward counter 32. The output of the counter 32 is connected to a decoder 33 having C 0 , C 1 , C 2  and C 3  output leads. The output lead C 0  is connected to AND gate 31, and C 3  to AND gate 30 and to AND gates 37 and 39. The output lead C 1  is in turn connected to an AND gate 36, the lead C 2  being connected to the J and K inputs of a flip-flop 34 and to an AND gate 38. 
     When the engine is started and its load is above the higher setting level F 1 , the decoder 33 provides a low level output on lead C 0  and a high level output on leads C 1  to C 3 , causing AND gates 30 and 31 to be disabled. Under these circumstances, flip-flop 34 is switched to provide a high Q output to AND gate 35, and AND gates 36 to 39 are all enabled so that all the cylinders are activated. 
     This condition continues until the time when the flip-flops 9 and 10 change their stable states as at time t 2  when the engine load falls below the setting level F 2  (FIG. 3). AND gate 30 is enabled by the &#34;1&#34; logic state of Q output of flip-flop 9 to pass clock pulses to the up-count input of the counter 32. In response to each of the applied clock pulses, the counter 32 is up-counted, and its binary output is decoded so that the output state of the leads C 1 , C 2  and C 3  changes respectively in sequence &#34;011&#34;, &#34;101&#34; and &#34;110&#34;. Therefore, in response to the first clock or injection pulse subsequent to time t 2 , the output states of the leads C 1 , C 2  and C 3  assumes &#34;0&#34;, &#34;1&#34; and &#34;1&#34;, respectively. This combination of output states on leads C 1  to C 3  produces a low voltage level output or disabling signal at the output of AND gate 36 and the No. 4 cylinder is disabled while the remainder cylinders are enabled. in response to the second injection pulse, the output condition of the decoder 33 changes so that leads C 1  to C 3  asumme &#34;1&#34;, &#34;0&#34; and &#34;1&#34; logic state respectively. This combination of output states produces disabling signals from the output of AND gates 35 and 39, disabling No. 1 and No. 6 cylinders. In response to the third injection pulse, leads C 1  to C 3  takes binary states &#34;1&#34;, &#34;1&#34; and &#34;0&#34;, respectively, to generate disabling signals from the AND gates 36, 37 and 39. Thus, No. 4, No. 5 and No. 6 cylinders are disabled. 
     Therefore, within the time interval t 2  to t 4  the number of active cylinders is successively decreased one at a time in step with subsequent injection pulses to a minimum number of three. It will be understood therefore that at time t 5 , the number of active cylinders will increase successively on a one-at-a-time basis in response to each injection pulse at the same rate as when the number of cylinders is decreased successively as at time t 2 . 
     During acceleration it is advantageous to increase the number of active cylinders at a higher rate than the rate at which it is decreased successively during deceleration, since the higher rate increase serves to prevent deficient delivery of power for acceleration. FIG. 5 illustrates a circuit necessary for effecting such higher rate enabling control. The output from the AND gate 13 is coupled to counters 40 and 41. The counter 40 is designed to provide its output at each count of N 1  input pulses, while the counter 41 provides its output at each count of N 2  input pulses, where N 2  is smaller than N 1 . The outputs from the counters 40 and 41 are connected to the AND gates 30 and 31 whose respective outputs are connected to the up- and down-count input terminals of the forward-backward counter 32 as previously described. AND gate 31 is thus arranged to receive input pulses which occur at shorter intervals than the pulses applied to the AND gate 30 so that the forward-backward counter 32 is down counted at a higher rate than it is up counted.