Abstract:
A slave device for exchanging data with a master device over a serial interface sends data to the master device upon receipt of a command from the master device. A controller responsive to a command byte in a receive register commences transmission of data in the transmit register under the control of a clock signal prior to reception of a complete command.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application claims the benefit under 35 USC 119(e) of U.S. provisional application No. 62/144,440, filed Apr. 8, 2015, the contents of which are herein incorporated by reference. 
     
    
     FIELD OF THE INVENTION 
       [0002]    This invention relates to synchronous serial interfaces, for example, and more particularly to a method of improving the performance of such interfaces. 
       BACKGROUND OF THE INVENTION 
       [0003]    Low speed synchronous serial interfaces, such as the System Peripheral Interface (SPI) and its numerous variants, are widely used for interfacing microprocessors with peripheral devices, including flash memories, sensors, data conversion devices, timing and synchronization devices, communication devices, audio codecs, and liquid crystal displays. 
         [0004]    For some of these applications, it is desired to maximize the bandwidth of data transfers by increasing the clock rate. In a 4-wire SPI interface, this is relatively easy to achieve for master-to-slave transfers, which transmit clock and data in a source synchronous manner. Slave-to-master transfers however transmit clock and data in opposite directions, and thus suffer from the effects of round trip time delay, severely limiting performance. 
         [0005]    A known technique to increase clock rate on SPI and similar interfaces involves modification to the master side of the interface, supporting an adjustable data sampling point. While this technique may be effective, it has some disadvantages: It has a high degree of design complexity. System integrators simply adding a new slave device to an existing SPI bus may be resistant to any master side modifications that may risk affecting communications with other devices. The required modifications may not be possible, e.g. when the master is integrated into an existing microprocessor design that does not support these features. Delaying the sampling point at the master requires the host processor to accept the data at a later point in time, which may require further, potentially infeasible system level changes or may impact system performance. 
       SUMMARY OF THE INVENTION 
       [0006]    Embodiments of the invention make a modification to the hardware design of the slave side of the SPI interface and higher-level protocol between the master and slave to advance the launch point for data after receipt of a command from the master. As a result, the interface clock speed can be increased, improving bandwidth beyond what was initially limited by round trip time 
         [0007]    According to the present invention there is provided a slave device for exchanging data with a master device over a synchronous serial interface, wherein the slave device sends data to the master device upon receipt of a command from the master device, the slave device comprising: a receive shift register for storing incoming commands; a transmit shift register for storing outgoing data; and a controller responsive to a command in the receive register to transmit data in the transmit register under the control of a clock signal, said controller being configured to commence transmission of said data in response to said command prior to complete reception of said command. 
         [0008]    Typically, the shift registers will be have a length capable of storing a complete byte, i.e. 8 bits, but one skilled in the art will appreciate that other bit-lengths could be employed, for example, 12 bits or 16 bits. 
         [0009]    Embodiments of the invention may offer the several advantages over previously known methods. The hardware changes are confined to the slave side only. The hardware implementation uses efficient standard digital logic and does not require modification to input and output buffers. The device may be implemented in both direct-clocked and sample-clocked designs and maintain backward compatibility with existing SPI masters, at supported clock rates. The device can also co-exist with peer slave devices not supporting the enhancement. 
         [0010]    In another aspect the invention provides a master device for receiving data from a slave device over a synchronous serial interface, wherein the slave device sends data to the master device upon receipt of a command from the master device, the master device being configured to send out a command to the slave device wherein a last transmitted bit of the command is a dummy bit containing no useful data. 
         [0011]    In yet another aspect the invention provides a method for sending data to a master device from a slave device over a synchronous serial interface, the method comprising: the slave device receiving a command from the master device; and the slave device in response to partial reception of said command transmitting data to the master device prior to complete reception of the command. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    This invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which: 
           [0013]      FIG. 1  illustrates a prior art serial Peripheral Interface (SPI); 
           [0014]      FIGS. 2 a  and 2 b    are timing diagrams showing standard launch and early launch respectively in accordance with an embodiment of the invention; and 
           [0015]      FIG. 3  is a schematic diagram of a modified SPI slave interface with support for standard and early launch in accordance with an embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0016]      FIG. 1  shows a high level view of a prior art 4-wire Serial Peripheral Interface (SPI). A master device  101  communicates with a slave device  102  using four signals: a clock signal SCLK  103 ; master output to slave input data signal MOSI  104 ; master input to slave output data signal MISO ( 105 ); and a slave chip select signal /SS  106 . In the case of multiple slave devices, a separate /SS line is typically used for each slave, although target addressing schemes also exist. Many variants of SPI and other similar synchronous serial interfaces exist. 
         [0017]      FIGS. 2 a  and 2 b    show a timing diagram of the interface, with standard launch and with early launch in accordance with an embodiment of the invention. In this example, a one byte command C 7 -C 0  is transferred from master device  101  to the slave device  102  on the MOSI line requesting data from the slave. After receiving the hill command, the slave immediately responds with one byte of data D 7 -D 0 . The higher layer protocol could extend this to an arbitrary number of bytes. We assume an operating mode with an initially low clock (clock polarity CPOL=0) and capture on the leading clock edge (clock phase CPHA=0). However, all other CPOL, CPHA combinations are equally valid for the invention. 
         [0018]    The round trip delay, which includes the propagation of SCLK from master device  101  to slave device  102  plus the propagation of MISO from slave back to the master reduces the setup time for sampling the MISO signal at the master device. The setup time is the time a signal is stable before it is sampled. Flip flop D pins at the circuit level and clocked input data pins at the device level specify a minimum required setup time in their datasheets. With increasing clock rate, the setup time is eventually reduced to the point where timing failure occurs. With the early launch scheme in accordance with embodiments of the invention, the data is driven from the slave device  102  earlier, one half clock cycle earlier in this example, providing additional setup margin, allowing for higher clock rates, and thus increased interface bandwidth. 
         [0019]    With the early launch feature in accordance with the invention, there is insufficient time for the slave to decode the last transmitted bit of the command byte. To overcome this problem, the higher layer protocol is modified to change the last hit into a dummy zero bit, which is ignored by the slave device, The host system software need only shift the command left by one bit, with no changes required to the typical master hardware design. If the remaining 6 bits of command is insufficient, multiple command bytes could be used for some or all commands. 
         [0020]      FIG. 3  shows a schematic diagram for the modified SPI slave device  200  supporting both standard launch and early launch in accordance with the invention. The slave device  200  comprises shift registers receive register  201 , transmit register  202 , flip-flop  204 , multiplexer  205 , MISO input  205   a,  MISO output driver  205   b,  //SS input  207 , and SCLK input  208 . 
         [0021]    Receive data and commands are clocked on the rising edge from MOSI into the receive shift register  201 . The transmit data and commands are clocked on the falling edge from the transmit shift register  202  out to MISO output  205   b.  A controller  203  processes commands and coordinates shift register operation. 
         [0022]    Rising edge flip-flop  204  and multiplexer  205  allow selection of the launch edge, with the launch cycle being determined by logic in the controller  203 . 
         [0023]    In the illustrated example the contents of the shift registers  201 ,  202  correspond to point indicated by * in  FIG. 2 b   , just before the rising edge of the clock in the last bit of the command byte. At this point, command bits C 6 - 0  have been shifted in and decoded. The receive shift register has deepest bit location  208  containing an unknown value X left over from a previous transaction and thus ignored. Data bit D 7  is about to be loaded into flip-flop  204  at the same time as the output driver  205   b  is enabled. 
         [0024]    The launch point can be made configurable. Also, the embodiment wherein the slave device clocks directly from SCLK as in  FIG. 3  could launch data on any preceding clock edge, while slave devices using a high speed internal sampling clock could have finer grain control over the launch point. When selecting a launch point, care must be taken not to violate hold time. For a half cycle early launch, hold time is easily guaranteed by the minimum round trip delay. 
         [0025]    It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. For example, a processor may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included. The functional blocks or modules illustrated herein may in practice be implemented in hardware or software running on a suitable processor.