Abstract:
A method for transferring data in a memory system including at least first and second memories, includes activating the first memory to conduct a read operation, activating the second memory during the read operation of the first memory, and transferring data which is obtained from the read operation, directly to the second memory from the first memory.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 2006-123966 filed on Dec. 7, 2006, the entire contents of which are hereby incorporated by reference. 
       BACKGROUND 
       [0002]    1. Field of the Invention 
         [0003]    The present invention disclosed herein relates to memory systems and more particularly, to a memory system and method for transferring data between pluralities of memories. 
         [0004]    2. Description of Related Art 
         [0005]      FIG. 1  is a block diagram of a memory system  100 . Referring to  FIG. 1 , the memory system  100  includes a controller  120 , and memories  140  and  160 . The memories  140  and  160  are NAND flash memories. The memories  140  and  160  are connected to the controller  120  by way of a common bus. Chip-enable pins CEb and ready/busy pin RBb of the memories  140  and  160  are independently connected to the controller  120 . 
         [0006]      FIG. 2  is a schematic illustrating a pattern of data transmission between memories  140  and  160  in the memory system  100 . In the memory system  100 , a procedure for transferring data from a source page  144  of the first memory  140  to a destination page  164  of the second memory  160  is as follows. Referring to  FIG. 2 , first, data of the source page  144  of the first memory  140  is transferred to a page buffer  146  ({circle around (1)}). Then, the data transferred to the page buffer  146  is transferred to a buffer  122  of the controller  120  ({circle around (2)}). Next, the data transferred to the buffer  122  of the controller  110  is transferred to a page buffer  166  of the second memory  160  ({circle around (3)}). Subsequently, the data transferred to the page buffer  166  is transferred to the destination page  164  of the second memory  160  ({circle around (4)}). 
         [0007]      FIG. 3  is a timing diagram according to the data transmission pattern shown in  FIG. 2 . Referring to  FIG. 3 , the memory system  100  is operable with data transmission by reading page data from the first memory  140  and writing the read page data into the second memory  160 . The controller  120  selects the memories  120  and  140 , and transfers a read or write command for a selected one of the memories. Each of the memories  140  and  160  generates the ready/busy signal RBb 0  or RBb 1 , for interrupting access from the controller  120 , while conducting the read or write operation. 
         [0008]    While a page size of the NAND flash memory is large, the memory system  100  needs to conduct a write operation after a read operation to accomplish data transmission between NAND flash memories. Therefore, a data transmission time becomes longer with the page size. 
       SUMMARY OF THE INVENTION 
       [0009]    According to an embodiment of the present invention, a method for transferring data in a memory system including at least first and second memories, includes activating the first memory to conduct a read operation, activating the second memory during the read operation of the first memory, and transferring data, which is obtained from the read operation, directly to the second memory from the first memory. 
         [0010]    According to an embodiment of the present invention, the memory system further includes a controller operating to control the first and second memories. The data read through the read operation is directly transferred to the second memory without passing through the controller. 
         [0011]    According to an embodiment, the first and second memories share a data bus for receiving a command, an address, and the data from the controller. 
         [0012]    According to an embodiment, the first and second memories are NAND flash memories. 
         [0013]    According to an embodiment, the activating of the first memory to conduct the read operation includes loading the data of a source page into a first page buffer of the first memory in response to a read command, and outputting the data, which is loaded into the first page buffer, to the data bus. 
         [0014]    According to an embodiment, the activating of the second memory during the read operation includes transferring the data, which is output to the data bus by the activating of the first memory to conduct the read operation, to a second page buffer of the second memory, and storing the data into a destination page of the second page buffer. 
         [0015]    According to an embodiment, the first and second memories receive chip-enable signals (CEb), read-enable signals (REb), write-enable signals (WEb), and ready/busy signals (RBb) each through respective lines from the controller. 
         [0016]    According to an embodiment, in the activating of the first memory to conduct the read operation, the second memory is inactive while the read command and an address of the source page are being transferred to the first memory. 
         [0017]    According to an embodiment, in the activating of the second memory during the read operation, the first memory is being inactive while the write command and an address of the destination page are being transferred to the second memory. 
         [0018]    According to an embodiment, after transferring the address of the second memory, the first memory is activated. 
         [0019]    According to an embodiment, after the data is transferred to the second page buffer of the second memory from the first page buffer of the first memory, the first memory maintains an inactive state. 
         [0020]    According to an embodiment, while the data is transferred to the second memory from the first memory, the read-enable signal (REb) and the write-enable signal (WEb) are simultaneously transferred to the first memory and the second memory, respectively. 
         [0021]    According to an embodiment of the present invention a system includes a first memory, a second memory, and a controller operating to control the first and second memories. The controller operates the first memory for a read operation and controls the first and second memories to transfer data, which is obtained by the read operation, directly to the second memory from the first memory. 
         [0022]    According to an embodiment, the first and second memories are NAND flash memories. 
         [0023]    According to an embodiment, the first and second memories receive chip-enable signals (CEb), read-enable signals (REb), write-enable signals (WEb), and ready/busy signals (RBb) each through respective lines from the controller so as to transfer the data directly into the second memory from the first memory without passing through the controller. 
         [0024]    According to an embodiment, the second memory maintains an inactive state while transferring the data into the second memory from the first memory and while transferring a read command and an address of a source page to the first memory. 
         [0025]    According to an embodiment, the first memory maintains an inactive state while transferring the data into the second memory from the first memory and while transferring a write command and an address of a destination page to the second memory. 
         [0026]    According to an embodiment, after transferring the address of the second memory, the first memory is activated. 
         [0027]    According to an embodiment, the first memory and the second memory comprise a first page buffer and a second page buffer, respectively, and after the data is transferred to the second page buffer of the second memory from the first page buffer of the first memory, the first memory maintains an inactive state. 
         [0028]    According to an embodiment, while the data is transferred to the second memory from the first memory, the read-enable signal (REb) and the write-enable signal (WEb) are simultaneously transferred to the first memory and the second memory, respectively. 
         [0029]    According to an embodiment, the memory system is a memory card. 
     
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         [0030]    Non-limiting and non-exhaustive embodiments of the present invention will be described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various figures unless otherwise specified. In the figures: 
           [0031]      FIG. 1  is a block diagram of a memory system; 
           [0032]      FIG. 2  is a schematic illustrating a pattern of data transmission between memories in the memory system; 
           [0033]      FIG. 3  is a timing diagram according to the data transmission pattern shown in  FIG. 2 ; 
           [0034]      FIG. 4  is a block diagram of a memory system in accordance with an embodiment of the present invention; 
           [0035]      FIG. 5  is a schematic illustrating a pattern of data transmission between memories in the memory system according to an embodiment of the present invention; 
           [0036]      FIG. 6  is a timing diagram according to the data transmission pattern shown in  FIG. 5 ; and 
           [0037]      FIG. 7  comparatively illustrates data transmission times of the memory systems by the present invention and the art. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0038]    Preferred embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be constructed as limited to embodiments set forth herein. Rather, embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout the accompanying figures. 
         [0039]      FIG. 4  is a block diagram of a memory system  200  in accordance with an embodiment of the present invention. Referring to  FIG. 4 , the memory system  200  includes a controller  200  and memories  240  and  260 . The memory system  200  according to an embodiment of the present invention stores data directly into the second memory  260  from the first memory  240  without passing through the controller  200 , improving the efficiency of data transmission between the memories  240  and  260 . 
         [0040]    In  FIG. 4 , the memories  240  and  260  are implemented in NAND flash memories for convenience of description. As illustrated in  FIG. 4 , each of the NAND flash memories includes input/output pins I/O[7:0], a command latch-enable pin CLE, an address latch-enable pin ALE, a chip-enable pin CEb, a read-enable pin REb, a write-enable pin WEb, a write-protection pin WPb, and a ready/busy pin RBb. 
         [0041]    The input/output pins I/O[7:0] are used for receiving a command, address signals, and data from the controller  220 , and outputting data during a read operation. The input/output pins I/O[7:0] are conditioned in a floating state when the memory is deselected or there is no output therefrom. 
         [0042]    The command latch-enable pin CLE receives a command signal from the controller  220 . For example, when a signal input to the command latch-enable pin CLE at a rising edge of the write-enable signal WEb has a logically high level, the NAND flash memory identifies a signal, which is input through an input/output bus, as a command and latches the corresponding command in a register (not shown). 
         [0043]    The address latch-enable ALE receives an address signal from the controller  220 . For example, the NAND flash memory latches an address signal at a rising edge of the write-enable signal WEb when the address latch-enable signal ALE has a logically high level. 
         [0044]    The chip-enable pin CEb receives a signal, which activates the NAND flash memory, from the controller  220 . 
         [0045]    The read-enable pin REb receives a signal, which outputs serial data of the NAND flash memory, from the controller  220 . 
         [0046]    The write-enable pin WEb receives a signal, which controls a write operation of the NAND flash memory, from the controller  220 . For example, the NAND flash memory latches a command, an address signal, and data at a rising edge of the write-enable signal WEb. 
         [0047]    The write-protection pin WPb receives a signal, which protects the NAND flash memory from being inadvertently read or written when there is a power variation, from the controller  220 . For instance, when the write-protection signal WPb has a logically low level, an internal high voltage generator (not shown) of the NAND flash memory is reset. 
         [0048]    The ready/busy pin RBb outputs a signal informing the controller  220  of a current state of the NAND flash memory. For example, while the NAND flash memory is conditioned in a write, erase, or read operation, the ready/busy signal RBb is output to the controller  220  having logically low level. 
         [0049]    The memories  240  and  260  are NAND flash memories as aforementioned. Pin connection between the controller  220  and the memories  240  and  260  store data from the first memory  240  directly into the second memory  260  without passing through the controller  220 . The chip-enable pins CEb, the read-enable pins REb, the write-enable pins WEb, and the ready/busy pins RBb, of the memories  240  and  260 , are individually connected by the controller  220 , except the write-protection pins WPb. 
         [0050]      FIG. 5  is a schematic illustrating a pattern of data transmission between the memories in the memory system  200  according to an embodiment of the present invention. Referring to  FIG. 5 , the memory system  200  includes the controller  220 , the first memory  240 , and the second memory  260 . The first memory  240  includes a memory cell array  242  and a page buffer  246 . The memory cell array  242  of the first memory  240  includes a source page  244  storing data to be transferred. The second memory  260  includes a page buffer  266  and a memory cell array  262  having a destination page  264  that stores data transferred from the first memory  240 . 
         [0051]    A NAND flash memory is operable with a read or write operation in the unit of a page. 
         [0052]    The memory system  200  according to an embodiment of the present invention transfers data to the destination page  264  of the second memory  250 , not to the controller  220 , from the source page  244  of the first memory  240 . Data of the source page  244  of the first memory  240  is transferred to the destination page  264  of the second memory  260  through the following course. 
         [0053]    Referring to  FIG. 5 , the controller  220  transfers a read command READ to the first memory  240  and a write command WRITE to the second memory  260  at the same time. The first memory  240  loads data into the page buffer  246  from the source page  244  in response to the read comment READ provided from the controller  220 . The second memory  260  is ready to conduct a write operation in response to the write command WRITE provided from the controller  220 . The data loaded into the page buffer  246  moves to the page buffer  266  of the second memory  260 , and the data transferred to the page buffer  266  is stored in the destination page  264 . 
         [0054]    While transferring data between the memories in the memory system  200 , data does not pass through the controller  220 . Thus, the memory system  200  is operable in a faster speed of data transmission. 
         [0055]      FIG. 6  is a timing diagram according to the data transmission pattern shown in  FIG. 5 . Referring to  FIG. 6 , data is directly stored into the second memory  260  from the first memory  240  without passing through the controller  200 , which will be detailed hereinafter. 
         [0056]    To conduct a read operation of the first memory  240  in the memory system  200 , the controller  220  transfers a first chip-enable signal CEb 0  to the first memory  240 . The first memory  240  is activated in response to a logical low level of the first chip-enable signal CEb 0 . The first memory  240  activated receives a read command  00 h through a data bus in response to the command latch-enable signal CLE and receives an address through the data bus in response to the address latch-enable signal ALE. The first memory  240  loads data into the page buffer  246  from the source page  244 . Simultaneously, the first memory  240  generates a ready/busy signal RBb 0  to inhibit access to itself while loading the data. 
         [0057]    During the read operation of the first memory  240 , the controller  220  outputs a second chip-enable signal CEb 1  to activate the second memory  260  and outputs the first chip-enable signal CEb 0  to deactivate the first memory  240 . The second memory  260  is activated in response to the second chip-enable signal CEb 1  having a logically low level. The second memory  260  receives a write command  80 h through the data bus in response to the command latch-enable signal CLE and receives an address corresponding thereto through the data bus in response to the address latch-enable signal ALE. After transferring the address to the second memory  260 , the controller  220  outputs the first chip-enable signal CEb 0  to reactivate the first memory  240  while the second memory  260  is being active. 
         [0058]    The controller  220  applies a read-enable signal REb 0  to the first memory  240  that is active. The first memory  240  outputs data to the data bus from the page buffer  246  in response to the read-enable signal REb 0 . At the same time, the controller  220  applies a write-enable signal WEb 1  to the second memory  260  that is active. The second memory  260  loads the data, which is output from the page buffer  246  of the first memory  240 , into the page buffer  266  of the second memory  260  in response to the write-enable signal WEb 1 . After completing data transmission from the page buffer  246  of the first memory  240  into the page buffer  266  of the second memory  260 , the controller  220  applies a write command  10 h to the second memory  260 . When the write command  10 h is input thereto, the second memory  260  starts to program the destination page  264  with the data transferred to the page buffer  266 . Simultaneously, the second memory  260  outputs the ready/busy signal RBb 1  having a logically low level to inhibit access to the second memory  260 . The controller  220  outputs the chip-enable signals CEb 0  and CEb 1  to deactivate the first and second memories  240  and  260 . 
         [0059]    As such, the memory system  200  according to an embodiment of the present invention performs direct data transmission between the memories  240  and  260  without passing through the controller  220 , which makes a data transmission time shorter. 
         [0060]      FIG. 7  comparatively illustrates data transmission times of the memory systems  200  according to an embodiment of the present invention and the memory system  100  shown in  FIG. 1 . 
         [0061]    The memory system  100  conducts a write operation after a read operation. Referring to  FIGS. 1 and 7 , the whole time for data transmission between the memories  140  and  160  is 360 us summing up a time for transferring a read command to the first memory  240  from the controller  120  (500 ns), a time for loading data into the page buffer  146  from the source page  144  (25 us), a time for transferring the data from the page buffer  146  to the buffer  122  of the controller  120  (80 us), a time for transferring a write command to the second memory  160  from the controller  120  (500 ns), a time for transferring the data to the page buffer  166  of the second memory  160  from the buffer  122  of the controller  120 , and a time for writing the data into the destination page  164  from the page buffer  166 . 
         [0062]    The memory system  200  according to an embodiment of the present invention stores data directly into the second memory  260  from the first memory  240  without passing through the controller  200 . Referring to  FIGS. 4 and 7 , the whole time for data transmission is summed up just by a time for reading data from the source page  244  of the first memory  240  and a time for writing the data into the destination page  264  of the second memory  260 . Thus, the whole data transmission time of the memory system  200  by the present invention becomes 305.5 us. 
         [0063]    As a result, data transmission in the memory system  200  is improved up to 21% as compared to the memory system  100 . 
         [0064]    The memory system  200  according to an embodiment of the present invention is helpful to further reduce a data transmission time as a page size becomes larger. 
         [0065]    The memory system  200  may be a memory card, e.g., a subscriber identity module (SIM) card. 
         [0066]    As described above, the memory system according to an embodiment of the present invention is effective in shortening a time for transferring data between the memories by storing data into the second memory from the first memory without through the controller. 
         [0067]    The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.