Abstract:
A method and apparatus for locking a memory device to prevent unauthorized data from being written to the memory device is disclosed. In a preferred embodiment an address of a memory device is selected such that when that address is selected, a &#34;1&#34; is written to an auxiliary memory device. This event causes the write-enable of the main memory to be disabled thereby locking the main memory device and preventing subsequent write operations thereto.

Description:
This application is a continuation, of application Ser. No. 07/471,643, filed Jan. 29, 1990, now abandoned. 
    
    
     FIELD OF THE INVENTION 
     The present invention is directed to a method and apparatus for selectively &#34;locking&#34; a memory circuit to prevent unauthorized data from being written to the memory circuit after the occurrence of a predetermined event. 
     BACKGROUND OF THE INVENTION 
     Memory circuits to which data may be written and stored and from which the stored data may read are widely used in a number of applications. One such application is in the field of electronic voting machines or other types of preference expression devices. Electronic voting machines may comprise at least a voting station where a voter casts votes for various candidates, referenda, etc. These votes may be recorded by storing data representative of the voter&#39;s selections in a removable tally module associated with the voting station or remote therefrom. This tally module comprises a memory device. It is very important that the data stored in this memory device be secure to preserve the integrity of the election process. In a multi-district election, e.g., the tally module from each district may be removed after the polls are closed and delivered to election authorities so that the data stored in the tally modules may be read. 
     Various safeguards may be implemented to protect against election fraud during the voting process. However, it is also very important to safeguard the data after the polls close so that between the time the polls close and the time the memory device is presented to the central election authorities, no unauthorized alteration of the stored data may occur. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, there is provided a novel method and apparatus for preventing the unauthorized writing of data to a memory device after the occurrence of a predetermined event. In one embodiment, this event may be the closing of the polls. According to one aspect of the invention, there is provided circuitry to cause a main memory device (which may be located in a tally module) to be &#34;locked&#34; such that once locked, no additional data can be written to the main memory device until it is erased by external means. This locking may occur by writing data to a specified address of an auxiliary memory device which is connected to the main memory device in such a manner to render the main memory device incapable of having any additional data written to it. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of the locking memory device. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     AS shown in FIG. 1, there is provided a main memory device 1, an auxiliary memory device 2, and address comparator 3, NAND gate 5, bus transceiver 4, address bus 6, write-enable line 7, chip select line 8, inverters 9 and 13, data bus 10, and data lines 11 and 12. 
     Main Memory device 1 may be any type of memory device capable of having data written thereto and read therefrom. Moreover, the main memory may be of any size or storage capacity. For purposes of this description, a 32K×8 EEPROM is shown. The auxiliary memory device 2 is shown as a 512×8 EEPROM, however other sizes, storage capacities and types of memories may be used. Both main memory 1 and auxiliary memory 2 have at least a chip-enable pin, a write-enable pin, an output enable pin, address pins and data pins. 
     On main memory 1, the chip-enable pin is connected to chip select line 8. The write-enable pin is connected to write-enable line 7 through NAND gate 5. The output-enable pin is connected to write-enable line 7. The address pins are connected to the address bus 6 and the data pins are connected to the data bus 10. 
     On auxiliary memory device 2, the chip-enable pin is connected to the chip select line 7. The write enable pin is connected to the output of address comparator 3. The output-enable pin is connected to the output of address comparator 3 through inverter 9. The address pins are connected to ground, effectively making the selection of address 0 permanent. Only one data pin is connected and that is connected to a data pin on the &#34;B&#34; side of bus transceiver 4; such connection constituting data line 11. 
     On address comparator 3, the function-select pin is connected to the write-enable line 7, through inverter 13; effectively allowing a signal (either low or high) to be generated on the output pin only when the write-enable is pulled high. The address lines are connected to the address bus 6. The count pins are connected to a source of a high signal, effectively making the address to be compared all ones. This compared address (all ones in the preferred embodiment) constitutes the &#34;write-lock address&#34;. The output pin is connected to the function-select pins of the bus transceiver 4, and to the write-enable and output-enable pins of the auxiliary memory device 2 (the latter through the inverter 9). 
     On bus transceiver 4, the function-select pins are both connected to the output of the address comparator 3, effectively assuring that either one function or the other of the bus transceiver is selected. Only one data pin on the &#34;B&#34; side is connected, and that connection is to a data pin on the auxiliary memory device 2; such connection constitutes data line 11. Only one data pin on the &#34;A&#34; side is connected and that pin corresponds to the data pin connected on the &#34;B&#34; side; the connection is made from that data pin to a source of a high signal (through a high-resistance, on the order of 20,000 ohms) and to an input pin of NAND gate 5. 
     In operation, according to a preferred embodiment, address comparator 3 has been wired as previously described to detect the presence of the &#34;write-lock&#34; address on the address bus 6 by comparing the address on address bus 6 with the address &#34;stored&#34; in the address comparators. The initial state of each memory device (1 and 2) is &#34;cleared&#34; (all zeroes). Since, auxiliary memory device 2 is permanently addressed at zero in the preferred embodiment, all reading from or writing to that device will be to that single address therein. When either reading from or writing to main memory device 1, the chip select signal is brought high, and the address of the target memory location is applied to the address bus 6. When reading is desired, the write-enable line 7 is pulled low and the data may be found on data bus 10; when writing is desired, the write-enable line 7 is brought high and the data to be written is presented on data bus 10. 
     The direction of data transfer through the bus transceiver 4 is dependent on the output of the address comparator 3, because of the nature of the connections of that output to the GAB and GBA pins of the transceiver 4. If the output of address comparator 3 is low, data is transferred from the B side to the A side; if the output of address comparator 3 is high, data is transferred from the A side to the B side. Therefore, transceiver 4 operates as a directional controller for data line 12 (connected between NAND gate 5 and a source of a high signal) and data line 11 (connected between auxiliary memory device 2 and the B side of the bus transceiver). While in the preferred embodiment this device is shown as a bus transceiver, various other types of devices or circuits to accomplish the same function will be readily apparent to one of ordinary skill in the art. 
     When writing to memory device 1 is desired, and the write-enable line 7 is pulled low, the address of the desired memory location is applied to the address bus 6 of both the main memory device 1 and the address comparator 3. Because of NAND gate 5, the actual write-enable signal to the main memory device 1 is dependent upon the signal on data line 12. If the signal on data line 12 is low (&#34;0&#34;), the main memory device 1 will be enabled for writing and the signals on the data bus 10 will be stored in the appropriate memory location of memory device 1. If the signal on data line 12 is high (&#34;1&#34;), the main memory device 1 will not be enabled for writing and no action is taken within the main memory device 1. 
     The signal on data line 12 is dependent upon the direction of transceiver 4 and the signal on data line 11. If the transceiver 4 is selected to function from A to B, then data line 12 will go high as a &#34;1&#34; is simultaneously transferred across the bus transceiver 4. If transceiver 4 is selected to function from B to A, then data line 12 will have whatever signal is on data line 11. As noted before, transceiver 4 is selected to function from A to B when the output of comparator 3 is high and functions from B to A whenever the output of comparator 3 is low. Thus, main memory device 1 is only write-enabled when the output from the address comparator 3 and the signal on data line 11 are both low, (after an appropriate settling time) 
     As described above, the output of the address comparator a has a low signal only when the address on address bus 6 is NOT the same as the write-lock address (all ones in the preferred embodiment) simultaneously when the write-enable line is high, i.e., when an attempt is made to write to the write-lock address. In the circuit of the present invention, that same low signal causes activation of an output-enable function on the auxiliary memory device 2 thereby causing the contents of address 0 of the auxiliary memory device 2 to be presented on data line 11. While the auxiliary memory device 2 remains in its initial cleared state (all zeros), these contents are necessarily 0 and the main memory device 1 is write-enabled as just explained. Therefore, as long as the contents of auxiliary memory device 2 remain in its initial cleared state (all zeros), any address of the main memory device 1 can be written to other than the write-lock address. 
     However, if the address on address bus 6 is ever the same as the write-lock address, then a high signal on the output of address comparator 3 causes the bus transceiver to transfer a high signal (1) to data line 11 (i.e., A to B). The high signal on the output of address comparator 3 also causes the write-enable pen, the auxiliary memory device 2 to be high, causing the 1 on line 11 to be written to that memory. As a result, the auxiliary memory device 2 is no longer in its initial cleared state, but instead has a 1 stored therein (&#34;set state&#34;). It should be noted that the only way of write-enabling the auxiliary memory device 2 is by the occurrence of the above events, so there is no way of writing a 0 to the auxiliary memory device 2 and thus no way of returning it to a cleared state, save by physically erasing the memory by external means (not shown). Placing auxiliary memory device 2 in its set state constitutes activation of the locking circuit. 
     Since there is no way to return the auxiliary memory device to the cleared state (absent erasure), once the auxiliary memory device 2 is in the set state, the signal on line 11 is always high (1). As a result, the main memory device 1 cannot be write-enabled, as previously explained. Thus, by activation of the locking circuit the memory is permanently &#34;locked&#34; from all subsequent attempts to write to it until the auxiliary memory is erased by external means. 
     External means of erasure of the memory devices 1 and 2 are not shown, but could be accomplished either by physical removal of the devices and replacement, or by the addition of a circuit which causes writing zeroes to all memory locations in both the devices upon an appropriate externally supplied signal. 
     As specifically applied to an electronic voting system, the entirety of the circuit could be part of a module used to store votes cast by voters. The module could contain a housing which would allow physical access to the memory devices only in a secure manner, for example, by use of a key. During voting hours, the voting control system avoids any attempt to write to the write-lock address. When it is finally desired to lock the memory after the voting hours have passed (at the close of the polls), the controlling system deliberately would attempt to write to the write-lock address. As a result of that action, any subsequent attempt to write to the main memory would fail because of the activation of the locking circuit as described above. Any such attempts would fail regardless if made by the original controlling system or, more importantly, if made by another system. The locked state would remain in effect until physical access is made to the memory devices to erase them. Thus, after activation of the locking circuit, it is possible to erase the votes completely (in a secure manner), but it is not possible to selectively tamper with them thereby preserving the integrity of the voting process. 
     While the foregoing describes a preferred embodiment of the invention, it is to be understood thai the invention is not limited thereto. Various alternative embodiments will be readily apparent to one of ordinary skill in the art. For example, the use of programmable logic arrays (PLAs) or logic cell arrays (LCAs) or both may be used instead of the discrete logic described herein. Moreover, the use of PLAs or LCAs permits additional functions to be performed such as error detection and correction, controlled erasure of a memory device and control by command as opposed to control by logic (e.g., writing to a memory location). Moreover, the invention is not limited to the field of electronic voting machines. The invention is only limited by the claims appended hereto.