Abstract:
There is disclosed a semiconductor integrated circuit device capable of eliminating an influence of a power voltage drop generated in a circuit disposed in the semiconductor integrated circuit device to inhibit an operation defect or an operation speed decrease of the circuit. In a semiconductor integrated circuit device  10  including a power wiring  18  connected to a power supply (Vdd) via a power terminal  12,  a ground wiring  20  connected to a ground (0 V) via a ground terminal 14, and a plurality of circuits  301  to  30   f  connected in parallel with one another between the power wiring  18  and the ground wiring  20,  a negative power terminal  16  connected to a negative power supply (−Vdd) is disposed, and a current source  22  is disposed as a current generating section between the negative power terminal  16  and a node Gf on a ground wiring  20  side of the f-th circuit  30   f  disposed in a region most distant from the ground.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to semiconductor integrated circuit devices such as LSI, particularly to a semiconductor integrated circuit device which inhibits a capability of a circuit from being degraded by a power voltage drop generated in the circuit disposed in the semiconductor integrated circuit device.  
         [0003]     This application is counterpart of Japanese patent application, Serial Number 382455/2003, filed Nov. 12, 2003, the subject matter of which is incorporated herein by reference.  
         [0004]     2. Description of the Related Art  
         [0005]     In recent years, semiconductor integrated circuit devices such as LSI have been requested to have an enlarged scale or multiple functions, and there has been a tendency to complication of a constitution of the semiconductor integrated circuit device and to an increase of a circuit area. This has involved an increase in a resistance by drawing around a power wiring and a ground wiring disposed in the semiconductor integrated circuit device, or in a decrease in a power voltage for the purpose of saving a power consumption and increasing a speed of the circuit. This has caused a voltage drop of a supply voltage in the circuit disposed in a position distant from a power supply, and has caused problems such as a defective operation and an operation speed decrease of the circuit.  
         [0006]     To solve the problems, a method has been used in which supply portions of the power voltage are increased or the supply portions are devised to decrease circuits to be disposed in positions distant from the supply portions or a meshed or thick power wiring is disposed to reduce an effective wiring resistance.  
         [0007]     Moreover, as a device which inhibits the voltage drop of the supply voltage in a general circuit disposed in the position distant from the power supply, a semiconductor integrated circuit device has been known which detects an internal power voltage level and an internal ground voltage level of the general circuit disposed in a semiconductor integrated circuit. In the device, the general circuit is controlled so as to compensate for a change of the voltage level of the general circuit by obtained internal power voltage detection signal and internal ground voltage detection signal (e.g., see Japanese Patent Application Laid-Open No. 05-315544).  
         [0008]     However, in the method of increasing the power supply portions, input pads need to be increased in order to secure the power supply portions. In the method of devising the shape of the power wiring or thickening the power wiring, there is a problem that a layout area of a power wiring portion increases. In this method, the effective resistance of the power wiring decreases but is not completely eliminated. Therefore, this method cannot sufficiently cope with the reduced voltage or the enlarged scale, and cannot be said to be an actually useful method.  
         [0009]     Moreover, the conventional semiconductor integrated circuit device for inhibiting the voltage drop of the supply voltage in the general circuit disposed in the position distant from the power supply has a problem that a circuit for detecting the internal power voltage level and internal ground voltage level is required for each general circuit. Another problem is that the wiring on the semiconductor integrated circuit device is complicated.  
       SUMMARY OF THE INVENTION  
       [0010]     The present invention has been developed to solve the above-described problem, and an object thereof is to provide a semiconductor integrated circuit device capable of eliminating an influence of a power voltage drop generated in a circuit disposed in the semiconductor integrated circuit device to inhibit an operation defect or an operation speed decrease of the circuit.  
         [0011]     To achieve the above-described object, according to the present invention, there is provided a first semiconductor integrated circuit device comprising: a power wiring whose one end is connected to a power supply; a ground wiring whose one end is connected to a ground; and a plurality of circuits connected in parallel between the power wiring and the ground wiring. The other end of the ground wiring is connected to a current generating section for generating a predetermined current in a state in which the section is connected to a negative power supply.  
         [0012]     That is, the ground wiring of the first semiconductor integrated circuit device is connected to the current generating section. The current generating section generates the predetermined current in the state in which the section is connected to the negative power supply.  
         [0013]     Accordingly, a direction of the current flowing through the ground wiring corresponds to that extending to a ground from the negative power supply (current generating section). Potentials in nodes which are points connecting a plurality of circuits to the ground wiring become higher, when the nodes are closer to the ground. On the other hand, the potential in the node closer to the power supply becomes higher even on a power wiring side. Therefore, a potential difference between the power supply and the ground can be secured to hold a sufficient voltage level in each circuit, and the operation defect or the operation speed decrease of the circuit can be inhibited.  
         [0014]     According to the present invention, there is provided a second semiconductor integrated circuit device comprising: a power wiring whose one end is connected to a power supply; a ground wiring whose one end is connected to a ground; a plurality of circuits connected in parallel between the power wiring and the ground wiring; and a current generating section whose one end is connected to the other end of the ground wiring to generate a predetermined current in a state in which the other end of the section is connected to a negative power supply.  
         [0015]     That is, in the second semiconductor integrated circuit device, the current generating section is disposed in the semiconductor integrated circuit device.  
         [0016]     According to the present invention, there is provided a third semiconductor integrated circuit device comprising: a power wiring whose one end is connected to a power supply; a ground wiring whose one end is connected to a ground; a plurality of circuits connected in parallel between the power wiring and the ground wiring; a negative power supply; and a current generating section whose one end is connected to the ground wiring and whose other end is connected to the negative power supply to generate a predetermined current.  
         [0017]     That is, in the third semiconductor integrated circuit device, the negative power source and current generating section are disposed in the semiconductor integrated circuit device.  
         [0018]     Since the second and third semiconductor integrated circuit devices function in the same manner as in the first semiconductor integrated circuit device of the present invention, the potential difference between the power supply and the ground is secured, the sufficient voltage level can be held in each circuit, and the operation defect or the operation speed decrease of the circuit can be inhibited.  
         [0019]     In the first to third semiconductor integrated circuit devices, the current generating section is preferably disposed in a wiring portion most distant from a portion in which a ground potential of the ground wiring is supplied.  
         [0020]     It is to be noted that in the first to third semiconductor integrated circuit devices, the current generating section may be either one of a current source and an,operating circuit which consumes a predetermined current to operate. That is, the current generating section may be the current source or the operating circuit which consumes the predetermined current to operate.  
         [0021]     For example, the operating circuit which consumes the predetermined current to operate may be a clock generator which outputs a clock signal. Since the clock generator consumes much current, a sufficient voltage level can be held in the plurality of circuits connected in parallel between the power wiring and the ground wiring. The clock generator is preferably connected to a level shifter for converting a level of the outputted clock signal to supply the clock signal to the plurality of circuits.  
         [0022]     As described above, according to the present invention, since the ground wiring of the semiconductor integrated circuit device is connected to the current generating section and negative power supply, an effect is produced that an influence of a power voltage drop generated in the circuit disposed in the semiconductor integrated circuit device is eliminated and an operation defect or operation speed decrease of the circuit can be inhibited. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIG. 1  is a circuit constitution diagram of a semiconductor integrated circuit device according to a first embodiment; and  
         [0024]      FIG. 2  is a circuit constitution diagram of the semiconductor integrated circuit device according to a second embodiment. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0025]     Preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings.  
       First Embodiment  
       [0026]      FIG. 1  is a circuit constitution diagram of a semiconductor integrated circuit device according to a first embodiment.  
         [0027]     As shown, a power terminal  12 , a ground terminal (ground pad)  14 , and a negative power terminal  16  are disposed in a semiconductor integrated circuit device  10 . The power terminal  12  is connected to an external power supply, and a power voltage (Vdd) is supplied to the power terminal. The ground terminal  14  is connected to a ground (0 V). An external negative power supply is connected to the negative power terminal  16 , and a negative power voltage (−Vdd) is supplied to the terminal. In this case, in the present embodiment, the negative power supply is disposed so that a voltage having the same magnitude as that of the voltage between the power supply and the ground is generated between the negative power supply and the ground.  
         [0028]     Moreover, the power terminal  12  is connected to a power wiring  18 , and the ground terminal  14  is connected to a ground wiring  20 . A plurality of circuits including a first circuit  301  to an f-th circuit  30   f  are connected in parallel in order from the circuit closest to the power supply and ground between the power wiring  18  and the ground wiring  20 .  
         [0029]     Furthermore, a current source  22  which is a current generating section is disposed between a node Gf and the negative power terminal  16  on the side of the ground wiring  20  in the f-th circuit  30   f  disposed in a region most distant from the ground among the plurality of circuits. That is, the current source  22  is disposed in a wiring portion most distant from the ground terminal (ground pad)  14  for supplying a ground potential (0 V) to the ground wiring  20 , and generates a current so that a direction of the current flowing through the ground wiring  20  extends toward the negative power supply (current source  22 ) from the ground.  
         [0030]     An operation of the semiconductor integrated circuit device  10  will hereinafter be described.  
         [0031]     When a current is supplied from the power wiring  18 , the current flows into the ground wiring  20  through the respective circuits  301  to  30   f.  At this time, when the current flows through each resistance (hereinafter referred to as the power wiring resistance) disposed in the power wiring  18 , a voltage drop is generated. Concretely, assuming that the current flowing through a power wiring resistance Rv 1  is Iv 1 , the voltage drop to a node V 1  of the first circuit  301  on the power wiring  18  from the power supply is Rv 1 ×Iv 1 . Assuming that the current flowing through a power wiring resistance Rv 2  is Iv 2 , the voltage drop to a node V 2  of the second circuit  302  from the node V 1  is Rv 2 ×Iv 2 . Therefore, the voltage drop to the node V 2  from the power supply is Rv 1 ×Iv 1 +Rv 2 ×Iv 2  which is obtained by integrating the respective voltage drops. Similarly, the voltage drop to the node Vf on the power wiring  18  side of the f-th circuit  30 f from the power supply indicates a value obtained by integrating all the voltage drops in the respective power wiring resistances.  
         [0032]     Therefore, as the respective nodes V 1 , V 2 , . . . Vf on the power wiring  18  are distant from the power supply, the potentials in the nodes drop.  
         [0033]     On the other hand, when the current source  22  connected to the negative power supply is not disposed in the ground wiring  20 , the direction of the current flowing through each resistance (hereinafter referred to as the ground wiring resistance) disposed in the ground wiring  20  extends toward the ground from the node Vf of the f-th circuit  30   f  on the ground wiring  20 . However, since the current source  22  connected to the negative power supply is connected to the ground wiring  20  here, the direction of the current flowing through each ground wiring resistance extends to the current source  22  from the ground.  
         [0034]     Accordingly, the voltage drop is also generated on the ground wiring  20  side. Concretely, assuming that the current flowing through a ground wiring resistance Rg 1  is Ig 1 , and the current flowing through a ground wiring resistance Rg 2  is Ig 2 , the voltage drop of a node G 1  of the first circuit on the ground wiring  20  from the ground is Rg 1 ×Ig 1 , and the voltage drop to a node G 2  of the second circuit from the node G 1  is Rg 2 ×Ig 2 . Therefore, the voltage drop to the node G 2  from the ground is Rg 1 ×Ig 1 +Rg 2 ×Ig 2  which is obtained by integrating the respective voltage drops. Similarly, the voltage drop to the node Gf from the ground indicates a value obtained by integrating all the voltage drops in the respective ground wiring resistances.  
         [0035]     Therefore, all the potentials of the respective nodes G 1 , G 2 , . . . Gf on the ground wiring  20  are lower than a ground potential of 0 V, and drop, as the nodes are distant from the ground.  
         [0036]     As described above, when the current source  22  connected to the negative power supply is not disposed, the direction of the current flowing through the ground wiring  20  extends to the ground from the node Gf. Therefore, as the node on the ground wiring  20  is distant from the ground (in order of G 1 , G 2 , . . . Gf), the potential of the node increases, and becomes highest in the node Gf. As the node on the ground wiring  18  is distant from the power supply (in order of V 1 , V 2 , . . . Vf), the potential of the node decreases. As the disposed position of the circuit is distant from the power supply (ground), the potential difference between the node on the power supply side and the node on the ground side in the respective circuits  301  to  30   f  decreases. Especially, the voltage level in the f-th circuit  30   f  disposed farthest from the power supply largely drops as compared with the first circuit  301  disposed in the vicinity of the power supply (ground).  
         [0037]     On the other hand, in the present embodiment, since the current source  22  connected to the negative power supply is disposed, the direction of the current flowing through the ground wiring  20  extends to the node Gf from the ground. As the node on the ground wiring  20  is distant from the ground (in order of G 1 , G 2 , . . . Gf), the potential of the node lowers, and becomes lowest in the node Gf. As the node on the ground wiring  18  is distant from the ground (in order of V 1 , V 2 , . . . Vf), the potential of the node lowers. Therefore, a sufficient potential difference can be secured between the node on the power supply side and the node on the ground side in the respective circuits  301  to  30   f,  and the voltage level does not drop even in the circuit disposed in a position distant from the power supply (ground). The circuit is stabilized to such an extent that the circuit is not influenced by the power voltage drop or the ground voltage rise.  
         [0038]     It is to be noted that an example in which the negative power supply is disposed outside the semiconductor integrated circuit device has been described in the present embodiment, but the negative power supply may also be built in the semiconductor integrated circuit device.  
         [0039]     Moreover, in the present embodiment, the semiconductor integrated circuit device in which the current source is built has been described as an example, but the current source may also be disposed outside the semiconductor integrated circuit device.  
       Second Embodiment  
       [0040]     In the first embodiment, the example in which the current source  22  is disposed as the current generating section in the semiconductor integrated circuit device  10  has been described. In a second embodiment, an example in which an operating circuit actually consuming the current to operate is disposed instead of the current source  22  will be described. It is to be noted that a constitution similar to that of the first embodiment is denoted with the same reference numerals, and the description thereof is omitted.  
         [0041]      FIG. 2  is a circuit constitution diagram of a semiconductor integrated circuit device  10   a  according to the present embodiment.  
         [0042]     As shown, an operating circuit is disposed as the current generating section between the node Gf on the ground wiring  20  side and the negative power terminal  16  of the f-th circuit  30   f  disposed in the region most distant from the ground among a plurality of circuits. It is to be noted that the operating circuit disposed as the current generating section is preferably constituted of a circuit which consumes much current, and a clock generator  24  is used here. After a signal level of an output signal generated by the clock generator  24  is adjusted by a level shifter  26 , the signal is outputted to the respective circuits  301  to  30   f  disposed between the power supply and the ground, and is used as a synchronous signal or the like in the circuits  301  to  30   f.    
         [0043]     In the present embodiment, since the clock generator  24  connected to the negative power supply is connected to the ground wiring  20 , the direction of the current flowing through each ground wiring resistance extends toward the clock generator  24  from the ground. Therefore, in the same manner as in the first embodiment, as the node on the ground wiring  20  is distant from the ground (in order of G 1 , G 2 , . . . Gf), the potential of the node lowers. As the node on the ground wiring  18  is distant from the power source (in order of V 1 , V 2 , . . . Vf), the potential of the node lowers. Therefore, the sufficient potential difference can be secured between the node on the power supply side and the node on the ground side in the respective circuits  301  to  30   f,  and the voltage level does not drop even in the circuit disposed in the position distant from the power supply (ground). The circuit is stabilized to such an extent that the circuit is not influenced by the power voltage drop or the ground voltage rise.  
         [0044]     Moreover, in the present embodiment, since the current flowing toward the negative power supply from the ground is also used for the circuit operation of the clock generator  24 , a current supply amount in the whole circuit may be reduced. Furthermore, since the clock generator  24  is disposed as the current generating section, a layout area can be reduced as compared with a case where the current source  22  is disposed.  
         [0045]     It is to be noted that an example in which the negative power supply is disposed outside the semiconductor integrated circuit device has been described in the present embodiment, but the negative power supply may also be built in the semiconductor integrated circuit device.  
         [0046]     Moreover, in the present embodiment, the semiconductor integrated circuit device in which the operating circuit (clock generator) is built has been described as the example, but the operating circuit may also be disposed outside the semiconductor integrated circuit device.  
         [0047]     It is to be noted that the present invention is not limited to the semiconductor integrated circuit device described as the example in the first and second embodiments, and can be applied to various semiconductor integrated circuit devices.