Abstract:
A circuit for interfacing to a limit switch configured to be closed when a wire connected to the limit switch is relatively hot and configured to be opened when the wire is relatively cold includes an input, an output, and a control portion. The input is configured to receive a pulse width modulated (PWM) signal having a duty cycle with a high pulse and a low pulse. The output is configured to apply the PWM signal to an external transistor associated with the wire, and a control portion. The high pulse actuates heating of the wire when the high pulse is applied to the external transistor. The control portion is configured to cause voltage across the limit switch to be substantially zero, whereby arcing of the limit switch is relatively minimal, when the limit switch closes while the high pulse is being applied to the external transistor.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 61/551,479, filed Oct. 26, 2011; the disclosure of which is incorporated in its entirety by reference herein. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates to an interface circuit for a limit switch. 
       BACKGROUND 
       [0003]    Certain vehicle seat modules control the air pressure inside multiple bladders. One or more of the bladders is located under the surface of a vehicle seat. The contour of the seat is modified with changing pressure. Certain modules may employ air valve technology which internally uses a shape memory alloy (SMA) wire to actuate the valve. When heated, the SMA property causes the wire to shrink and thereby open the valve. 
         [0004]    The valve technology includes a limit switch. The limit switch is used to sense when the valve is in its full opened position. The valve is in its full opened position while the wire is adequately heated such that the wire is shrunk enough to thereby open the valve to its full opened position. The limit switch is closed when the valve is in its full opened position. As such, by detecting that the limit switch is closed it can be detected that the valve is in its full opened position. The valve is not in its full opened position while the wire is not adequately heated. The limit switch is not closed (e.g., the limit switch is opened) when the valve is not in its full opened position. As such, by detecting that the limit switch is opened it can be detected that the valve is not in its full opened position. 
         [0005]    Using the limit switch to sense the position of the valve permits control circuits to maintain the valve in its full opened position while applying further minimal heat to the wire. This level of control provides predictable behavior of the valve over varying temperature and air flow conditions and also minimizes the heat and mechanical stress on the wire. 
         [0006]    Pulse Width Modulation (PWM) may be used for heating the wire. Current pulses are passed through the wire with resistivity losses of the wire causing self-heating of the wire. The PWM current pulses can be generated by a microcontroller for application to the wire. 
       SUMMARY 
       [0007]    Embodiments of the present invention are directed to an electronic circuit for interfacing to a limit switch. The switch is used in an application for heating a wire such as a shape memory alloy (SMA) wire. An electronic circuit (i.e., a “limit switch interface circuit” or “switch interface circuit”) in accordance with embodiments of the present invention is intended to reduce operating current and minimize commutation thereby extending life of the switch. Previous designs commutate the switch circuit load current through the switch for each open-close event as part of the normal operation. A concern is that the low-voltage micro-arching may prematurely wear out the sensitive contacts of the switch. An electronic circuit in accordance with embodiments of the present invention uses transistors to commutate the switch current and may thereby nearly eliminate the low-voltage micro-arching. In this manner, the switch state (i.e., opened or closed) pursuant to the use of an electronic circuit in accordance with embodiments of the present invention is better described as being sampled rather than driving the response load circuit as per the previous designs. 
         [0008]    In an embodiment, a circuit for interfacing to a limit switch is provided. The limit switch is configured to be closed when a wire connected to the limit switch is relatively hot and configured to be opened when the wire is relatively cold. The circuit includes an input, an output, and a control portion. The input is configured to receive a pulse width modulated (PWM) signal having a duty cycle with a high pulse and a low pulse. The output is configured to apply the PWM signal to an external transistor associated with the wire, and a control portion. The high pulse actuates heating of the wire when the high pulse is applied to the external transistor. The control portion is configured to cause voltage across the limit switch to be substantially zero, whereby arcing of the limit switch is relatively minimal, when the limit switch closes while the high pulse is being applied to the external transistor. 
         [0009]    In an embodiment, an assembly having a wire, a limit switch, and a circuit is provided. The wire is configured to move a valve to a fully opened position when the wire is relatively hot, the wire being associated with an external transistor. The limit switch is movable to and from a closed position, wherein the limit switch is configured to be in the closed position when the valve is in the fully opened position. The circuit interfaces to the limit switch and includes an input, an output, and a control portion. The input is configured to receive a pulse width modulated (PWM) signal having a duty cycle with a high pulse and a low pulse. The output is configured to apply the PWM signal to an external transistor associated with the wire. The high pulse actuates heating of the wire when the high pulse is applied to the external transistor. The control portion is configured to cause voltage across the limit switch to be substantially zero, whereby arcing of the limit switch is relatively minimal, when the limit switch closes while the high pulse is being applied to the external transistor. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1  illustrates a schematic diagram of an assembly having a limit switch interface circuit in accordance with a first embodiment of the present invention; 
           [0011]      FIG. 2  illustrates a schematic diagram of an assembly having a limit switch interface circuit in accordance with a second embodiment of the present invention; 
           [0012]      FIG. 3  illustrates a schematic diagram of the assembly shown in  FIG. 1  with a generalized functional description diagram of the limit switch interface circuit; and 
           [0013]      FIG. 4  illustrates a schematic diagram of an assembly having a simple limit switch interface circuit. 
       
    
    
     DETAILED DESCRIPTION 
       [0014]    Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the present invention that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. 
         [0015]    Referring now to  FIG. 1 , an assembly  10  having a limit switch interface circuit  12  in accordance with a first embodiment of the present invention is shown. Assembly  10  further includes a sub-assembly  14  having a limit switch  16  and a shape memory alloy (SMA) wire  18 . Assembly  10  further includes a wire heating model sub-assembly  17  for providing feedback to operate limit switch  16 . Wire heating model sub-assembly  17  is used for simulation purpose. 
         [0016]    Limit switch and SMA wire sub-assembly  14  represents limit switch  16  and SMA valve wire  18 . Wire  18  is denoted by the sum of the resistances R1-Wire and R2-Wire. Switch  16  senses voltage at a mid-point of wire  18 . The mid-point is due to the mechanical construction of the valve for this particular application. Switch  16  is a normally opened-type switch. Switch  16  is closed when the valve is fully opened. The valve is fully opened while wire  18  is adequately heated such that wire  18  shrinks enough thereby causing the valve to open into its fully opened position. The valve is in a position other than its fully opened position when wire  18  is not adequately heated to shrink enough in order to open the valve to its fully opened position. Switch  16  closes upon the valve being fully opened and remains closed while the valve is fully opened. Switch  16  opens upon the valve moving from its fully opened position to another position and remains opened while the valve is in a position other than its fully opened position. In this example, switch  16  presents one-half of the voltage across wire  18  when switch  16  is closed as a result of the valve being in its fully opened position. 
         [0017]    As described in greater detail below, a purpose of switch  16  is to interrupt Pulse Width Modulated (PWM) generated wire heating when the valve is fully opened. That is, the PWM wire heating is to be interrupted most of the time while switch  16  is closed. The PWM wire heating is interrupted by preventing the PWM signal from being presented to the gate of a MOSFET  19  (or for example, a bipolar junction transistor (BJT)) connected to the wire. 
         [0018]    Conversely, the PWM wire heating is to be enabled when the valve is in a position other than its fully opened position (i.e., when switch  16  is not closed). That is, the PWM wire heating is enabled when switch  16  is opened. The PWM wire heating is enabled by allowing the PWM signal to be presented to the gate of MOSFET. 
         [0019]    Limit switch interface circuit  12  includes a first transistor Q 1 , a second transistor Q 2 , and a third transistor Q 3 . Transistors Q 1 , Q 2 , and Q 3  along with associated resistive components including resistors R 1 , R 2 , R 3 , R 4 , R 5 , and R 6  are arranged in the configurations shown in  FIG. 1 . The PMW signal is input to transistor Q 1  and transistor Q 3  componentry as shown in  FIG. 1 . Transistor Q 2  componentry is electrically connected to switch  16  as shown in  FIG. 1 . Transistor Q 3  componentry is electrically connected to the gate of MOSFET  19  as shown in  FIG. 1 . 
         [0020]    A function of limit switch interface circuit  12  is to allow the state of switch  16  to be communicated to the PWM signal stream for control of heating or cooling of wire  18 . Another function of interface circuit  12  is to minimize the commutation of current passing through switch  16  thereby extending the life of switch  16 . Commutation of current occurs when switch  16  actively initiates or terminates current flowing through switch  16 . This causes micro-arcing at the switch contacts at the instant of closing or opening resulting in wear. 
         [0021]    In a typical application, the PWM duty cycle may be 10%. A fundamental principle of reducing the current commutation of switch  16  is to recognize that information about the state (e.g., closed or opened) of switch  16  is only required when the PWM pulse is logic high. Heating of wire  18  occurs when the PWM high pulse is applied to the gate of MOSFET  19 . As such, wire  18  is not heated during the PWM high pulse if the PWM high pulse is not applied to the gate of MOSFET  19 . Wire  18  is not heated when the PWM pulse is logic low regardless of whether the PWM low pulse is applied to the gate of MOSFET  19 . As such, in the typical application where the PWM duty cycle is 10% the information about the state of switch  16  is only required 10% of the time. That is, when the PWM pulse is high, which occurs 10% of the time in this example, the information about the switch state is needed as heating of the wire can occur with the PWM high pulse. Conversely, when the PWM pulse is low (i.e., logic zero), which occurs 90% of the time in this example, the information about the switch state is not needed as no heating will occur with the PWM low pulse. 
         [0022]    One operation of limit switch interface circuit  12  in reducing the commutation is to keep the switch electrical load disconnected during the time the PWM pulse is at logic low, 90% of the time in this example. Additional operations are implemented by interface circuit  12  to reduce switch commutation while the PWM pulse is logic high, 10% of the time in this example. 
         [0023]    The Limit Switch Commutation Current Is Minimized: Cases #1-Cases #5. 
         [0024]    Case #1: The PWM signal is at logic low causing transistor Q 1  of limit switch interface circuit  12  to be off. At any moment whenever switch  16  opens from its closed position due to the cooling down of wire  18  from the adequately heated position, no switch current flows and no switch commutation or micro-arcing occurs. This is because the base-emitter of transistor Q 2  has zero bias voltage or has negative bias depending on the state of the output of MOSFET  19 . 
         [0025]    Case #2: Wire  18  is adequately heated and does not require additional heat (and the valve is fully opened with switch  16  being closed). While switch  16  is closed, at the moment the PWM signal transitions to logic high current flows through switch  16  but will not be commutated. There is no micro-arcing within switch  16  as switch  16  is already closed. In this case, the base-emitter of transistor Q 2  becomes forward biased causing conduction to the base of transistor Q 3 . The speed of this transaction is fast compared to the turn-on time of MOSFET  19  due to the gate capacitance and limiting resistors R 5  and R 6 . This causes transistor Q 3  to clamp the node between resistors R 5  and R 6  to ground thereby preventing the PWM signal from being applied to the gate of MOSFET  19 . As the PWM signal is prevented from enabling MOSFET  19 , further heating of wire  18 , which is already adequately heated, is blocked. 
         [0026]    Case #3: Wire  18  requires heating as the valve is not fully opened (and the switch  16  is opened). Wire heating is initiated at the start of a PWM high pulse as switch  16  is opened. In this case, transistor Q 2  and wire  18  are on. The resistor divider R1-R2 is active causing both sides of switch  16  to have the same voltage, namely, the midpoint voltage across wire  18 . (The voltage divider R1 and R2 are chosen to approximate the voltage divider R1-Wire and R2-Wire.) Upon wire  18  being adequately heated such that switch  16  closes during the PWM high pulse, no current flows and no commutation occurs according to the case #2 above. 
         [0027]    Case #4: Wire  18  is adequately heated at the start of a PWM high pulse, but cools off enough during the PWM high pulse such that wire  18  needs to be heated further. In this case, switch  16  is closed at the start of the PWM high pulse, but opens during the PWM high pulse thereby calling for heating of wire  18 . This is the same as case #2 until switch  16  opens. This situation causes switch commutation, but is relatively rare. This situation is rare due to the typically small 10% duty cycles. Commutation does occur, but has been minimized. Further, some of those skilled in the art may consider that limited commutation is necessary to clean films or other minor contamination from switch  16 . 
         [0028]    Case #5: Switch  16  opens or closes right on the edge of a PWM pulse. This situation is neglected as the PWM transition times occupy a relatively extremely small part of the PWM period thereby making this situation rare. 
         [0029]    As described by the cases, features of switch interface circuit  12  is to prevent the arcing across switch  16 . To this end, interface circuit  12  is configured such that: (i) when switch  16  closes to terminate heating while wire heating is on, the voltage across switch  16  is small and arcing is minimal; (ii) when switch  16  opens to call for heating while the wire heating is off, the voltage across switch  16  is small and minimal arcing occurs; and (iii) if limit switch  16  were to close, due to delayed response of the heated wire, while wire heating is off, still the voltage across switch  16  is minimal. 
         [0030]    As described, limit switch interface circuit  12  allows switch  16  to effectively be “sampled” in hardware by the PWM signal for wire heating control while minimizing current commutation at the switch contacts to thereby extend the life of switch  16 . 
         [0031]    Referring now to  FIG. 2 , with continual reference to  FIG. 1 , an assembly  20  having a limit switch interface circuit  22  in accordance with a second embodiment of the present invention is shown. Assembly  20  includes limit switch and SMA wire sub-assembly  14  and wire heating model sub-assembly  17 . Limit switch and SMA wire sub-assembly  14  includes limit switch  16  and SMA wire  18 . 
         [0032]    Limit switch interface circuit  22  is an alternate embodiment if “high-side” drive of wire  18  is desired. Interface circuit  22  includes a transistor Q-level_shift, a first transistor Q 1 , a second transistor Q 2 , and a third transistor Q 3 . Transistors Q-level_shift, Q 1 , Q 2 , and Q 3  along with associated resistive components including resistors R 1 , R 2 , R 3 , R 4 , R 5 , and R 6  are arranged in the configurations shown in  FIG. 2 . The PMW signal is input to transistor Q-level_shift as shown in  FIG. 2 . Transistor Q 2  componentry is electrically connected to switch  16  as shown in  FIG. 2 . Transistor Q 3  componentry is electrically connected to the gate of MOSFET  19  as shown in  FIG. 2 . 
         [0033]    Limit switch interface circuits in accordance with other embodiments may include replacing MOSFET  19  with a suitable bi-polar device and appropriate bias circuits. 
         [0034]    Referring now to  FIG. 3 , with continual reference to  FIG. 1 , a schematic diagram of assembly  10  shown in  FIG. 1  with a generalized functional description diagram of limit switch interface circuit  12  is shown. As shown in  FIG. 3 , the electrical componentry of interface circuit  12  form a two-state reference block  32 , a compare function block  34 , and a gating function block  36 . 
         [0035]    Transistor Q 1  and resistors R 1  and R 2  form two-state reference block  32 . Two-state reference block  32  provides a PWM switchable two-state reference voltage with a first voltage representing the wire heat-off state of the mid-value voltage of wire  18  and a second voltage representing the wire heat-on state of the mid-value voltage of wire  18 . 
         [0036]    Transistor Q 2  and resistors R 3  and R 4  form compare function block  34 . Compare function block  34  provides a comparator function for comparing the switchable reference voltage of two-state reference block  32  to the mid-value voltage of wire  18  based on the state (i.e., closed or opened) of switch  16 . 
         [0037]    Transistor Q 3  and resistors R 5  and R 6  form gating function block  36 . Gating function block  36  provides a gating function to enable or disable the operation of MOSFET  19  based on the comparator output function of compare function block  34  and the PWM stream. 
         [0038]    Referring now to  FIG. 4 , a schematic diagram of an assembly  40  having a simple limit switch interface circuit  42  is shown. Interface circuit  42  includes only the PWM gating function (enable/disable operation) of MOSFET  19 . In this case, switch  16  commutates the current for all switch state transitions for all conditions. While simple, limit switch interface circuit  42  causes accelerated wear-out over limit switch interface circuits  12  and  22  described above. 
         [0039]    While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms of the present invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the present invention. Additionally, the features of various implementing embodiments may be combined to form further embodiments of the present invention.