Abstract:
Carry lookahead adders reduce the number of logic levels required to sum two numbers. A pure carry lookahead adder, however, requires circuits with large fan-outs and fan-ins making it impractical to build for a large number of bits. Carry lookahead tree adders use a plurality of small carry lookahead adders to build a complete adder. A binary carry lookahead adder is a typical implementation of a carry lookahead tree adder. Each stage of the binary carry lookahead adder generates a propagate output and generate output from propagate and generate inputs and calculates a carry output from a carry input. A modified generate circuit is introduced which reduces the propagation delay of the generate circuit. A modified propagate circuit is introduced that ensures the inputs to the modified propagate circuit do not create a short circuit. Additionally, a combination propagate and generate circuit is introduced which reduces the number of transistors required to implement the propagate and generate circuits. Still further, a quadrature carry lookahead tree adder is discussed and a combination propagate and generate circuit for the quadrature tree adder is presented.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to adders and more particularly to a combination propagate and generate gate for carry lookahead adders. 
     2. Description of the Relevant Art 
     Microprocessors determine the speed and power of personal computers and a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input output unit (I/O unit), the control unit, and the arithmetic-logic unit (ALU). The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of a signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the program is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the microprocessor. 
     An essential component of any ALU is the adder circuit. The adder circuit performs addition operations on two or more input operands. Because the addition operation is one of the most commonly invoked operations during the execution of a computer program, the speed with which the adder circuit can compute the sum (or difference) of two input operands is extremely important in determining the speed of the overall system. 
     Several common adder circuits are well known in the field of digital logic. A ripple-carry adder, for example, adds two (or possibly more) operands in much the same manner as a person would add two numbers. The least significant bit of the first operand is added to the least significant bit of the second operand (and possibly a carry-in bit) to produce a least significant result bit and a least significant carry bit. The least significant carry bit is then added to the next most significant bit of the first operand and the next most significant bit of the second operand to produce a next most significant result bit and a next most significant carry bit. This sequence continues until, eventually, the most significant bits of the operands have been added together with the carry bit from the preceding stage to produce the most significant result bit and a carry-out bit. The carry-out bit of the ripple carry adder can be used as a carry-in bit to a subsequent adder circuit such that multiple ripple carry adders can be connected together in series. 
     Referring now to FIG. 1A, a 4-bit ripple carry adder 10 is shown. A first operand comprising first operand bits a 0 , a 1 , a 2 , and a 3  is added to a second operand comprising second operand bits b 0 , b 1 , b 2 , and b 3 , to produce a result comprising result bits s 0 , s 1 , s 2 , and s 3 . During a first cycle, stage 20A adds carry-in bit c in  to least significant bit a 0  of the first operand and least significant bit b 0  of the second operand to produce a least significant bit s 0  of the result and a first carry bit c 1 . During the next cycle, first carry bit c 1 , next most significant bit a 1 , and next most significant bit b 1  are added by stage 20B to produce next most significant result bit s 1  and second carry bit c 2 . This procedure is repeated until carry bit c 3  is added to most significant bit a 3  and most significant bit b 3  4 to produce most significant bit s 3  and carry-out bit c out . The inventor skilled in the art of digital circuit design will appreciate that least significant bit s 0  of the result is generated prior to intermediate significant result bit s 1  which is generated prior to most significant result bit s 3 . Therefore, there is a time delay (t d ) between the generation of least significant result bit s 0  and most significant result bit s 3 . If multiple adder circuits similar to the circuit depicted in FIG. 1A are connected in series such that the carry-out bit of a preceding stage forms the carry-in bit for a subsequent stage, a larger adder will result. To form a 32-bit adder, for example, eight 4-bit adders, such as the one shown in FIG. 1A, can be connected in series. With each additional stage, the time delay, t d , between generation of the least significant result bit and the most significant result bit increases more or less linearly, negatively impacting the overall performance of the ALU, the microprocessor, and ultimately, the computing system as a whole. Generally speaking, the ripple carry adder requires 2N levels of logic to implement, where N is the number of bits in each operand. 
     A carry lookahead adder reduces the time delay to compute a sum. Each stage of the carry lookahead adder calculates c i  from the known values of a i  and b i  rather than waiting for c i  to be calculated by a previous stage. Two intermediate values are defined: a generate (g i ) signal and a propagate (p i ) signal. The following equations define g i  and p i  : 
     
         g.sub.i =a.sub.i b.sub.i, p.sub.i =a.sub.i +b.sub.i. 
    
     The generate signal indicates that a carry is generated by that stage. If both the a input and b input to a stage are true, that stage will generate a carry and the generate signal for that stage is asserted. The propagate signal indicates that a stage will propagate a carry signal if a carry input signal is true. If the a or b input to a stage is true, the stage will propagate a carry input received. Therefore, the propagate input is defined as either a or b being true. A stage will generate a carry output if either the generate signal is true or the propagate signal is true and a carry input signal is true. Accordingly, the following equation defines the carry output of a stage: 
     
         c.sub.i+1 =g.sub.i +p.sub.i c.sub.i. 
    
     Carry-out is identified as c i+1  because the carry-out signal of one stage is typically the carry input signal for the subsequent stage. Using the above equation c i  is defined as g i-1  +p i-1  c i-1 . In a recursive manner c i-1  may be defined in terms of g i-2 , p i-2  and c i-2 . Ultimately, c i+1  may be defined by the following equation: 
     
         c.sub.i+1 =g.sub.i +p.sub.i g.sub.i-1 +p.sub.i p.sub.i-1 g.sub.i-2 + . . . +p.sub.i p.sub.i-1 . . . p.sub.1 g.sub.0 +p.sub.i p.sub.i-1 . . . p.sub.1 p.sub.0 c.sub.0 
    
     where c 0  is a carry-in signal to the adder. If there is no carry-in signal, the last product term of the equation above may be eliminated. The carry-in signal for each stage of an adder can be computed concurrently using the above equation. A carry lookahead adder requires one logic level for calculating p and g for each stage and two logic levels to calculate the carry signal for each stage. Additionally, each stage requires two levels of logic to compute the sum for that counter stage. Thus, a carry lookahead adder requires five logic levels to compute a sum regardless of the number of bits in each operand. This is a significant improvement over the ripple carry adder which requires 2N logic levels to compute a sum, where N is the number of bits in each operand. 
     Although a carry lookahead adder requires a minimal number of logic levels, the gates of the carry lookahead adder may have a large number of inputs, or a large fan-in. For example, the computation of c i+1  requires an OR gate with N+1 inputs. Additionally, the p i  signal is an input to each AND gate required to implement the c i+1  equation described above. Thus, the OR gate that computes p i  must drive N logic gates, i.e. has a fan-out of N. 
     A compromise between the speed of a carry lookahead adder and the simplicity of a ripple adder is a hierarchical carry lookahead tree adder. The carry lookahead tree adder uses a plurality of small carry lookahead adders. Referring now to FIG. 1B, a hierarchical carry lookahead tree adder is shown. Tree stages 102A-102H computes p&#39;s and g&#39;s for each stage of the adder. Additionally, when c i  is available, tree stages 102A-102H computes s i  from a i , b i  and c i . 
     The generate and propagate signals can be calculated for a group of bits. For example, G 01  indicates whether the group of bits consisting of bits 0 and 1 generates a carry-out signal. Likewise, P 01  indicates whether the group of bits 0 and 1 will propagate a carry-in signal. G 01  and P 01  are defined by the following equations: 
     
         G.sub.01 =g.sub.1 +p.sub.1 g.sub.0 
    
     
         P.sub.01 =p.sub.1 p.sub.0 
    
     c 2  is defined in terms of G and P as: 
     
         c.sub.2 =G.sub.01 +P.sub.01 c.sub.0. 
    
     Further, G and P of larger groups of bits may be defined in terms of G and P of smaller groups of bits. For example, G 03  =G 23  +P 23  G 01  and P 03  =P 01  P 23 . In general terms, the following equations may be used for any j where i&lt;j, j+1&lt;k: 
     
         c.sub.j+1 =G.sub.ij +P.sub.ij c.sub.i 
    
     
         G.sub.ik =G.sub.j+1k +P.sub.j+1k G.sub.ij 
    
     
         P.sub.ik =P.sub.ij P.sub.j+1k 
    
     In FIG. 1B, tree stages 104A-104G compute G and P of larger groups of bits from G and P of small groups of bits. For example, stage 104D generates G 67  and P 67  from g 7 , P 7 , g 6  and P 6 . Similarly, stage 104F generates G 47  and P 47  from G 67 , P 67 , G 45  and P 45 . Eventually, stage 104G calculates G 07  and P 07  from G 47 , P 47 , G 03  and P 03 . 
     Stages 104A-104G additionally generate carry signals. Stage 104G receives c 0  and generates C 4 . Stage 104F generates c 6  from c 4 , and stage 104D generates c 7  from c 6 . As can be seen in FIG. 1B, the generate and propagate signals are generated as the signals propagate down the tree structure and the carry signals are generated as the carry signals propagate up the tree structure. Stages 102A-102H receive the carry signals and calculate the sum from the carry signals and the operand inputs (a and b). For a more detailed discussion of adders, refer to Computer Architecture A Quantative Approach by Hennessy and Patterson, Morgan Kaufmann Publishers, Inc., 1990, pp. A31-A39. This reference is herein incorporated by reference. 
     Turning now to FIG. 2, conventional circuits for generating G and P are shown. FIG. 2A illustrates a circuit that implements the equation G ik  =G j+1k+P   j+1k  G ij . FIG. 2B illustrates a circuit that implements the propagate equation P ik  =P ij  P j+1k . The generate and propagate circuits are designed for both positive and negative logic. Accordingly, the circuits can be cascaded without inverting signals between stages. 
     What is desired is a faster and smaller circuit for implementing the propagate and generate signals of a carry lookahead adder. 
     SUMMARY OF THE INVENTION 
     The present invention modifies the generate circuit shown in FIG. 2A such that the drain of T5 is coupled to voltage source Vdd rather than to the source of T1. This modification allows the size of transistor T5 to be reduced. Because Vdd is separated from the output by only one transistor, the size of transistor T5 can be reduced while maintaining the same voltage drop from Vdd to the output as a conventional circuit. Reducing the size of transistor T5 reduces the input capacitance to input P j+1k , thereby increasing the operation speed of the propagate circuit. To prevent a drive fight, or short between two transistors of the modified propagate circuit, P j+1k  cannot be low at the same time that G j-1k  is high. To prevent the occurrence of this condition, the propagate circuit is modified. The modified propagate circuit is symmetrical with the generate circuit except the G ij  input of the generate circuit is replaced with P ij . 
     The present invention takes advantage of the symmetry of the generate and propagate circuit to combine the propagate and generate circuits into one circuit. The combination circuit reduces the number of transistors required to implement the generate and propagate circuits and increases the speed of the circuits. 
     Broadly speaking, the present invention contemplates a combined generate and propagate circuit in a carry lookahead adder, including a generate output node, a propagate output node, and ten switches. A first pair of switches comprises a first switch coupled between a first potential and the propagate output node and a second switch coupled between the first potential and the generate output node. A second pair of switches comprises a third switch coupled between a second potential and the propagate output node, and a fourth switch coupled between the second potential and the generate output node. A third pair of switches comprises a fifth switch coupled between a third node and the propagate output node, and a sixth switch coupled between the third node and the generate output node. A fourth pair of switches comprises a seventh switch coupled between a fourth node and the propagate output node, and an eighth switch coupled between the fourth node and the generate output node. A ninth is switch operably coupled between the first potential and the third node. A tenth switch is operably coupled between the second potential and the fourth node. 
     The present invention further contemplates a combined generate and propagate circuit in a carry lookahead adder including a generate output node, a propagate output node and twenty-two switches. A first switch is coupled between a third node and the propagate output node. A second switch is coupled between a fourth node and the propagate output node. A third switch is coupled between the third node and the generate output node. A fourth switch is coupled between the fourth node and the generate output node. A fifth switch is coupled between a fifth node and the propagate output node. A sixth switch is coupled between a sixth node and the propagate output node. A seventh switch is coupled between the fifth node and the generate output node. A eight switch is coupled between the sixth node and the generate output node. A ninth switch is coupled between a seventh node and the propagate output node. A tenth switch is coupled between a eighth node and the propagate output node. A eleventh switch is coupled between the seventh node and the generate output node. A twelfth switch is coupled between the eighth node and the generate output node. A thirteenth switch is coupled between a first potential and the propagate output node. A fourteenth switch is coupled between a second potential and the propagate output node. A fifteenth switch is coupled between the first potential and the generate output node. A sixteenth switch is coupled between the second potential and the generate output node. A seventeenth switch operably is coupled between the third node and the fifth node. A eighteenth switch operably is coupled between the fourth node and the sixth node. A nineteenth switch operably is coupled between the fifth node and the seventh node. A twentieth switch operably is coupled between the sixth node and the eighth node. A twenty-first switch operably is coupled between the seventh node and the first potential. A twenty-second switch operably is coupled between the eighth node and the second potential. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: 
     FIG. 1A is a block diagram of one embodiment of a ripple carry adder. 
     FIG. 1B is a block diagram of one embodiment of a carry lookahead tree adder. 
     FIGS. 2A and 2B are circuit diagrams illustrating conventional implementations for generate and propagate circuits. 
     FIG. 3A is a circuit diagram of an improved generate circuit. 
     FIG. 3B is a circuit diagram of an improved propagate circuit. 
     FIG. 3C is a circuit diagram of an improved carry circuit. 
     FIG. 4 is a circuit diagram of an improved combination generate and propagate circuit. 
     FIG. 5 is a block diagram of one embodiment of a quadrature carry lookahead tree adder. 
     FIG. 6 is a circuit diagram of a combination propagate and generate circuit for the adder of FIG. 5. 
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Turning now to FIG. 3A, a circuit diagram of an improved generate circuit is shown. The generate circuit includes p-channel transistors T1, T2 and T5, and n-channel transistors T3, T4 and T6. A drain of transistor T1 is coupled to Vdd, a gate of T1 is coupled to input G j+1k , and a source of T1 is coupled to a drain of T2. A source of T2 is coupled to a source of T3, a source of T5, a source of T6, and a generate output (G ik ). The gate of T2 is coupled to input G ij . The drain of T3 is coupled to the source of T4. The gate of T3 is coupled to the G ij  input. The gate of T4 is coupled to input P j+1k . The drain of T4 is coupled to ground. The drain of T5 is coupled to power source Vdd. The gate of T5 is coupled to P j+1k . The source of T5 is coupled to the source of T6, the source of T2, the source of T3, and the generate output. The gate of T6 is coupled to the G j+1k  input. The source of T6 is coupled to ground. 
     One improvement of the generate circuit shown in FIG. 3A over the generate circuit shown in FIG. 2A is that the drain of T5 is coupled to the Vdd rather than to the source of T1. Connecting the drain of T5 to Vdd has several advantages. When the generate output is pulled high, only one transistor is coupled between Vdd and the generate output. Accordingly, the series resistance between Vdd and the generate output is reduced from a conventional implementation. This allows the size of transistor T5 to be reduced while maintaining the series resistance between Vdd and the generate output of a conventional implementation. The size of a transistor is inversely proportional to the series resistance of the transistor. Therefore, reducing the size of a transistor increases the series resistance between drain and source. Because the improved circuit illustrated in FIG. 3A has one transistor between Vdd and the generate output rather than two transistors in a conventional generate circuit, transistor T5 of the improved circuit can be approximately half the size of transistor T5 in FIG. 2A without increasing the series resistance between Vdd and the generate output. 
     Reducing the size of a transistor also decreases the input capacitance of a transistor, which decreases the switching time of the previous stage. If T5 of the improved generator circuit is smaller than T5 of conventional generate circuits, the input capacitance of T5 is smaller. The smaller input capacitance reduces the time delay from the transition of the gate signal to the transistor turning on, or entering a low impedance mode. In the generate circuit illustrated in FIG. 3A, reducing the size of transistor T5 decreases the time delay from the transition of signal P j+1k  from high to low or low to high. 
     One limitation of the generate circuit illustrated in FIG. 3A is that a short circuit condition arises when G j+1k  is high while P j+1k  is low. When P j+1k  is low, transistor T5 is turned on and the generate output is coupled to Vdd through the low on-resistance of T5. When input G j+1k  is high, T6 enters a low impedance mode and couples the generate output to ground through the low on-resistance of T6. The combination of transistors T5 and T6 being in a low impedance mode concurrently creates a low impedance path, or short, between Vdd and ground. This obviously undesirable condition can be avoided by preventing G j+1k  from being high at the same time that P j+1k  is low. In one embodiment, this is accomplished by modifying the propagate circuit. 
     As discussed above, a conventional propagate circuit implements the equation P ik  =P ij  P j+1k . Using this equation, it is possible for P ik  to be low at the same time as G ik  is high, and therefore possible for P j+k  to be low at the same time as G j+1k  is high. To prevent this condition the propagate equation is modified. In one embodiment, the equation for P ik  is modified to: 
     
         P.sub.ik =G.sub.j+1k +P.sub.j+1k P.sub.ij =P.sub.j+1k (G.sub.j+1k +P.sub.ij) 
    
     Using the modified equation, P ik  is never low when G ik  is high. G ik  (G ik  =G j+k  +P j+1k  +G ij ) is high under two conditions either G j+1k  is high, or both P j+1k  and G ij  are high. If G j+1k  is high, then P ik  will also be high. If P j+1k  is high, then P ik  will be high if P ij  is high. Accordingly, G j+1k  is not high while P j+1k  is low unless G ij  is high while P ij  is low. This relationship can be extended to indicate that G j+1k  is not high while P j+1k  is low unless g i  is high while p i  is low. Using the equations for g i  (g i  =a i  b i ) and p i  (p i  =a i  +b i ) is it apparent that g i  cannot be high while p i  is low. Thus, the condition that causes a short circuit in the generate circuit is not encountered using the modified propagate equation. 
     Put in other terms, from the equations g i  =a i  b i  and p i  =a i  +b i  it can be seen that ˜pigi=0. Further using the modified equations for P i  and G i , it can be shown that ˜P 01  G 01  =0; and further extrapolated to show that ˜P i  G i  =0. As discussed above, G 01  =g 1  +p 1  g 0  and P 01  =g 1  +p 1  p 0 . The only way for P 01  to be low, when G 01  is high is for p 0  to be low while g 0  is high. Accordingly, because ˜p 0  g 0  =0, ˜P 01  G 01  =0. This same relationship holds for Pi and Gi. 
     The propagate equation now mirrors the generate equation and the circuit of FIG. 3A may be used to calculate the propagate signal. FIG. 3B illustrates the circuit for generating a propagate signal according to one embodiment of the present invention. The circuit is the same as the generate circuit except G ij  is replaced with P ij . 
     Turning now to FIG. 3C, a circuit for generating a carry-out signal is shown. The equation for the carry-out signal mirrors the equation for the generate signal and propagate signal. The carry-out signal is calculated using the following equation: 
     
         c.sub.j+1 =G.sub.ij +P.sub.ij c.sub.i. 
    
     The same circuit used for the propagate and generate signals shown in FIGS. 3A and 3B may be used to calculate the carry-out signal. Like the propagate and generate circuits, G ij  cannot be high while P ij  is low for the carry circuit to operate correctly. As discussed above, the modified propagate circuit of FIG. 3B ensures that this condition does not occur. 
     Turning now to FIG. 4, a combination generate and propagate circuit according to one embodiment of the present invention is shown. When the propagate and generate circuits of FIGS. 3A and 3B are combined, several transistors are redundant. For example, T1 and T7 are both coupled to Vdd and G j+1k . Similarly, transistors T4 and T10 are both coupled to ground and P j+1k . Combining the generate and propagate circuit allows the redundant transistors to be eliminated, thereby reducing the number of transistors to implement the generate and propagate circuit. In the illustrated embodiment, the number of transistors to implement the generate and propagate circuits is reduced from 12 to 10. Transistor T7 is eliminated and the source of transistor T1 is coupled to both transistor T2 and T8. Likewise, transistor T4 is eliminated and the source of transistor T10 is coupled to both of T3 and of T9. 
     In some combinations of inputs, transistors T1 and T10 may have to drive both the propagate and generate output. For example, if G j+1k , P ij  and G ij  are all low, transistor T1 must drive the generate output through transistor T2 and the propagate output through transistor T8. In one embodiment, transistor T1 is designed to be twice the size of transistor T1 of FIG. 2A. The current drive of a transistor is proportional to the size of the transistor. Increasing the size of T1 provides sufficient current to drive both the generate and propagate outputs when the condition arises. In this embodiment, eliminating transistor T7 does not provide a significant reduction in the silicon area required to implement the combination of propagate and generate circuit. This embodiment, however, does increase the speed of the propagate generate circuit under certain conditions. For example, if inputs G j+1k  and G ik  are low and input P ij  is high, transistor T1 drives the generate output through transistor T2. In this situation, transistor T1 is only driving one output, therefore, the additional current of the larger transistor leads to less propagation delay in the assertion of the generate output. Likewise, when G j+1k  and P ij  are low and G ij  is high, T1 drives the propagate output through transistor T8. Because T1 is only driving one output, the propagation delay in asserting the propagate output is reduced. 
     Similarly, T10 replaces transistors T4 and T10 of FIGS. 3A and 3B. T10 in FIG. 4 may be designed to be twice as large as T10 in FIG. 3B. In a manner similar to that discussed above with reference to T1, when T10 drives only one output, T10 is able to sink twice as much current, thereby reducing the propagation delay in deasserting the propagate output or, the generate output. 
     Turning now to FIG. 5, a block diagram of a quadrature (or radix-4) carry lookahead tree adder is shown. Carry lookahead tree adders may be implemented with different levels of integration than the binary tree structure shown in FIG. 1B. FIG. 5 illustrates a quadrature tree structure. Tree stages 502A and 502B each receive propagate and generate inputs from four tree stages. The quadrature tree structure requires more complicated gates to implement each stage, but reduces the number of stages, thereby reducing the propagation delay of the adder. For example, tree stage 502A calculates G03 and P03 from the outputs of tree stages 102A-102D. Comparing FIG. 5 to FIG. 1B, tree stage 502A replaces tree stages 104A, 104B and 104E. Although FIG. 5 illustrates an 8-bit adder, the quadrature tree structure is better suited for 16-bit adders. In a 16-bit adder, the last stage, stage 104G, would be replaced with a quadrature tree stage and the tree stage would receive propagate and generate inputs from stages 502A, 502B and two other quadrature tree stages. In this manner, a 16-bit adder is implemented with three levels of circuitry. In contrast, the binary tree structure illustrated in FIG. 1B would require five levels of circuitry to implement a 16-bit adder. 
     Turning now to FIG. 6, a circuit diagram of a combination propagate and generate circuit for a quadrature tree structure is shown. The quadrature tree stage receives four propagate inputs (p i  through p i+3 ) and four generate inputs (g i  through g i+3 ). The quadrature tree stage includes 22 switches (T1 through T22). The quadrature tree structure advantageously reduces the number of transistor required to implement the propagate and generate circuit. Comparing the binary tree stage of FIG. 4 to the quadrature tree stage of FIG. 6, the quadrature tree stage replaces three binary tree stages. The quadrature tree stage requires 22 transistors while the three binary tree stages that the quadrature tree stage replaces require a total of 30 transistors. 
     T1 is operably coupled between a propagate output, a first propagate input and a third node. T2 is operably coupled between the propagate output, the first propagate input and a fourth node. T3 is operably coupled between a generate output, a first generate input and the third node. T4 is operably coupled between the generate output, the first generate input and the fourth node. T5 is operably coupled between the propagate output, a second propagate input and a fifth node. T6 is operably coupled between the propagate output, the second generate input and a fifth node. T7 is operably coupled between the generate output, a second propagate input and the fifth node. T8 is operably coupled between the generate output, the second generate input and the sixth node. T9 is operably coupled between the propagate output, a third propagate input and a seventh node. T10 is operably coupled between the propagate output, a third generate input and a eighth node. T11 is operably coupled between the generate output, the third propagate input and the seventh node. T12 is operably coupled between the generate output, the third generate input and the eighth node. T13 is operably coupled between the propagate output, a fourth propagate input and Vdd. T14 is operably coupled between the propagate output, a fourth generate input and ground. T15 is operably coupled between the generate output, the fourth propagate input and Vdd. T16 is operably coupled between the generate output, the fourth generate input and ground. T17 is operably coupled between the third node, the second generate input and the fifth node. T18 is operably coupled between the fourth node, the second propagate input and the sixth node. T19 is operably coupled between the fifth node, the third generate input and the seventh node. T20 is operably coupled between the sixth node, the third propagate input and the eighth node. T21 is operably coupled between the seventh node, the fourth generate input and Vdd. T22 is operably coupled between the eighth node, the fourth propagate input and ground. 
     Although only radix-2 (FIG. 3C) and radix-4 (FIG. 6) generate and propagate circuits have been shown, the present invention contemplates combination generate and propagate circuits of any radix. 
     Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.