Abstract:
New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    The present application claims the benefit of U.S. provisional application serial No. 60/071,879, titled “1.25 GBaud CMOS Driver and On-Chip Termination for Gigabit Ethernet PHY Chip,” invented by Gijung Ahn, Deog-Kyoon Jeong, and Gyudong Kim, and filed on Jan. 20, 1998. The present application is also a continuation-in-part of U.S. patent application Ser. No. 09/146,818, titled “System and Method for High-Speed, Synchronized Data Communication,” invented by Deog-Kyoon Jeong and Gijung Ahn, and filed on Sep. 4, 1998. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Technical Field  
           [0003]    This invention relates to data communication systems. More particularly, this invention relates high-speed communications systems including high-speed transmitters and receivers.  
           [0004]    2. Description of Related Art  
           [0005]    As electronic and computer technology continues to evolve, communication of information among different devices, either situated near by or at a distance becomes increasingly important. For example, it is now more desirable than ever to provide for high speed communications among different chips on a circuit board, different circuit boards in a system, and different systems with each other. It is also increasingly desirable to provide such communications at very high speeds, especially in view of the large amount of data required for data communications in intensive data consuming systems using graphical or video information, multiple input-output channels, local area networks, and the like.  
           [0006]    It is particularly desirable to enable individual personal computers, workstations, or other computing devices, within which data is normally internally transferred using parallel data buses, to communicate with each other over relatively simple transmission lines. Such transmission lines typically include only one or two conductors, in contrast with the 64-bit and wider data paths within computing systems now commonly available.  
           [0007]    A communication system that includes oversampling is often utilized to recover transmitted data. Such a system includes a receiver which samples the incoming serial data stream at a rate greater than the rate at which symbols (bits) are being transmitted. For example, in a three-times (3×) oversampling receiver, the incoming data stream is sampled at a rate approximately three times the symbol rate. However, there are various problems to overcome in order to effectively implement such a receiver when the rate of data transmission is very high. For example, parasitic capacitance and inductance typically introduce substantial distortion into the received signal.  
           [0008]    The physical layer of the Gigabit Ethernet standard (IEEE 802.3z) requires a so-called PHY chip which operates at gigabaud speeds. Traditionally, either GaAs or bipolar techniques have been used to implement such PHY chips. However, GaAs and bipolar circuits cannot be easily integrated with other CMOS (complementary metal-oxide-semiconductor) circuits and are typically more costly to manufacture than CMOS circuits.  
         SUMMARY OF THE INVENTION  
         [0009]    The above described needs are met and problems are solved by the present invention. New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]    [0010]FIG. 1 shows a block diagram of a communication system utilizing a gigabaud CMOS driver in accordance with a preferred embodiment of the present invention.  
         [0011]    [0011]FIG. 2 shows a circuit diagram of a high-speed serializer in accordance with a preferred embodiment of the present invention.  
         [0012]    [0012]FIG. 3 shows a circuit diagram of a differential voltage driver in accordance with a preferred embodiment of the present invention.  
         [0013]    [0013]FIG. 4 shows typical circuit configurations of (a) a current mode driver and (b) a voltage mode driver in accordance with a preferred embodiment of the present invention.  
         [0014]    [0014]FIG. 5 shows simulated waveforms under the configurations shown in FIG. 4 in accordance with a preferred embodiment of the present invention.  
         [0015]    [0015]FIG. 6 shows a circuit diagram of an on-chip termination circuit in accordance with a preferred embodiment of the present invention.  
         [0016]    [0016]FIG. 7 shows the characteristics of the on-chip termination circuit shown in FIG. 6 for a 75 ohm transmission line in accordance with a preferred embodiment of the present invention.  
         [0017]    [0017]FIG. 8 contrasts (a) a conventional receiver configuration using external termination outside the conventional receiver with (b) the receiver configuration which utilizes on-chip termination within the receiver in accordance with a preferred embodiment of the present invention.  
         [0018]    [0018]FIG. 9 contrasts (a) a simulated waveform in a receiver using external termination in accordance with FIG. 8( a ) with (b) a simulated waveform in a receiver utilizing on-chip termination in accordance with FIG. 8( b ).  
         [0019]    [0019]FIG. 10 shows a block diagram of (a) a phase tracker and (b) a frame aligner in accordance with a preferred embodiment of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]    [0020]FIG. 1 shows a block diagram of a communication system  100  utilizing a gigabaud CMOS driver  108  in accordance with a preferred embodiment of the present invention. The system  100  includes a transmitter (TX)  102 , a receiver (RX)  104 , and a phase-locked loop (PLL)  106 .  
         [0021]    As shown in FIG. 1, the transmitter  102  outputs a 1.25 gigabit per second (Gbps) signal to a transmission medium. Of course, the particular speed of the signal may vary within the scope of the present invention. The transmitter  102  includes a differential voltage driver (the gigabaud CMOS driver)  108 , a serializer  110 , and a data retimer  112 .  
         [0022]    In accordance with a preferred embodiment, the data retimer  112  receives a 125 MHz external clock and a DC-balanced and limited run-length 10-bit parallel data stream from an encoder. The data retimer  112  utilizes the external clock to adjust the timing of the data stream.  
         [0023]    The serializer  110  receives the adjusted 10-bit parallel data stream from the data retimer  112 . The serializer  110  also receives  10  phase clocks from the PLL  106 . The serializer  110  utilizes the 10 phase clocks to transform the 10-bit parallel data stream into a serial bit stream.  
         [0024]    The differential voltage driver  108  receives the serial bit stream from the serializer  110 . The differential voltage driver  108  drives the serial bit stream onto the medium at 1.25 Gbps, 10 times the 125 MHz speed of the external clock.  
         [0025]    The transmission medium which carries the 1.25 Gbps signal is not terminated with a conventional external resistor. Instead, the transmission medium is terminated by an on-chip termination circuit  114  within the receiver  104 . Use of the on-chip termination circuit  114  reduces signal distortion in comparison with external termination. The receiver  104  includes, in addition to the on-chip termination  114 , a 3-times (3×) oversampler  116 , a phase tracker  118 , a RX clock selector  120 , and a frame aligner  122 .  
         [0026]    The oversampler  116  receives the data signal from the on-chip termination  114 . The oversampler  116  utilizes  30  phase clocks supplied by the PLL  106  to oversample the data signal and generate  30  sampled bits in parallel. The 3× oversampler  116  provides the 30 sampled bits in parallel to the phase tracker  118 . The phase tracker  118  and the RX clock selector  120  operate to recover the clock and the data from the oversampled data and provides the recovered data stream to the frame aligner  122 . In a preferred embodiment, the frame aligner  122  searches for a comma character in the recovered data stream and makes a near instant alignment of the boundary between words when such a comma character is found.  
         [0027]    In accordance with a preferred embodiment of the system  100 , a clock frequency difference between the TX  102  and the RX  104  of less than 0.1% is to be tolerated. The PLL  106  operates to keep the clock frequency difference within that tolerance.  
         [0028]    [0028]FIG. 2 shows a circuit diagram of a high-speed serializer  110  in accordance with a preferred embodiment of the present invention. The serializer  110  comprises NMOS (n-type metal-oxide-semiconductor) transistors used as switching elements, and PMOS (p-type metal-oxide-semiconductor) transistors (M 1 , M 2 , M 3 ) used as loads. These transistors are used to form differential pseudo-NMOS logic.  
         [0029]    Regarding the PMOS transistors, M 1  has its source coupled to a supply voltage, its gate coupled to an electrical ground, and its drain coupled to the sources of M 2  and M 3 . Operationally, Ml pulls down the common mode voltage so that the output voltage moves around one-half the supply voltage (Vdd/2) with a small swing. M 2  has its gate coupled to an electrical ground, and its drain coupled to a first NMOS transistor network  202 . M 3  has its gate coupled to an electrical ground, and its drain coupled to a second NMOS transistor network  204 .  
         [0030]    The first network  202  includes a first node  206  coupled to the drain of M 2 . The first node  206  is also coupled to the negative input terminal of the differential voltage driver  108 . In addition, the first node  206  is coupled to ten columns ( 210 ,  211 , . . . ,  219 ) of NMOS transistors. Each column  210 - 219  includes three NMOS transistors in series between the first node  206  and electrical ground. For example, the first column  210  includes a first NMOS transistor  210   a  whose source is coupled to the first node  206 , a second NMOS transistor  210   b  whose source is coupled to the drain of the first NMOS transistor  210   a , and a third NMOS transistor  210   c  whose source is coupled to the drain of the second NMOS transistor  210   b  and whose drain is coupled to an electrical ground. The gate of the first NMOS transistor  210   a  is coupled to receive a fifth phase clock signal (ck 4 ) from the PLL  106 . The gate of the second NMOS transistor  210   b  is coupled to receive a first phase clock signal (ck 0 ) from the PLL  106 . Finally, the gate of the third NMOS transistor  210   c  is coupled to receive a first data signal (d 0 ) from the data retimer  112 .  
         [0031]    Similarly, the second column  211  includes three NMOS transistors ( 211   a - 211   c ) coupled in series between the first node  206  and an electrical ground. The gate of the first NMOS transistor  211   a  is coupled to receive a sixth phase clock signal (ck 5 ) from the PLL  106 . The gate of the second NMOS transistor  211   b  is coupled to receive a second phase clock signal (ck 1 ) from the PLL  106 . Finally, the gate of the third NMOS transistor  211   c  is coupled to receive a second data signal (d 1 ) from the data retimer  112 .  
         [0032]    And so on for the other columns  212 - 219 , incrementing the signals on the gates appropriately. For example, regarding the tenth column  219 , the gate of the first NMOS transistor  219   a  is coupled to receive a fourth phase clock signal (ck 3 ) from the PLL  106 . The gate of the second NMOS transistor  219   b  is coupled to receive a tenth phase clock signal (ck 9 ) from the PLL  106 . Finally, the gate of the third NMOS transistor  219   c  is coupled to receive a tenth data signal (d 9 ) from the data retimer  112 .  
         [0033]    The second network  204  includes a second node  208  coupled to the drain of M 3 . The second node  208  is also coupled to the positive input terminal of the differential voltage driver  108 . In addition, the second node  208  is coupled to ten columns ( 220 ,  221 , . . . ,  229 ) of NMOS transistors. Each column  220 - 229  includes three NMOS transistors in series between the second node  208  and electrical ground. For example, the first column  220  includes a first NMOS transistor  220   a  whose source is coupled to the second node  208 , a second NMOS transistor  220   b  whose source is coupled to the drain of the first NMOS transistor  220   a , and a third NMOS transistor  220   c  whose source is coupled to the drain of the second NMOS transistor  220   b  and whose drain is coupled to an electrical ground. The gate of the first NMOS transistor  220   a  is coupled to receive a fifth phase clock signal (ck 4 ) from the PLL  106 . The gate of the second NMOS transistor  220   b  is coupled to receive the first phase clock signal (ck 0 ) from the PLL  106 . Finally, the gate of the third NMOS transistor  220   c  is coupled to receive an inverted version of the first data signal (inverted d 0 ) from the data retimer  112 .  
         [0034]    Similarly, the second column  221  includes three NMOS transistors ( 221   a - 221   c ) coupled in series between the second node  208  and an electrical ground. The gate of the first NMOS transistor  221   a  is coupled to receive a sixth phase clock signal (ck 5 ) from the PLL  106 . The gate of the second NMOS transistor  221   b  is coupled to receive a second phase clock signal (ck 1 ) from the PLL  106 . Finally, the gate of the third NMOS transistor  221   c  is coupled to receive an inverted version of the second data signal (inverted d 1 ) from the data retimer  112 .  
         [0035]    And so on for the other columns  222 - 229 , incrementing the signals on the gates appropriately. For example, regarding the tenth column  229 , the gate of the first NMOS transistor  229   a  is coupled to receive a fourth phase clock signal (ck 3 ) from the PLL  106 . The gate of the second NMOS transistor  229   b  is coupled to receive a tenth phase clock signal (ck 9 ) from the PLL  106 . Finally, the gate of the third NMOS transistor  229   c  is coupled to receive an inverted version of the tenth data signal (d 9 ) from the data retimer  112 .  
         [0036]    [0036]FIG. 3 shows a circuit diagram of a differential voltage driver  108  in accordance with a preferred embodiment of the present invention. The communication system  100  uses such a differential voltage driver  108  instead of a current mode driver, because a current mode driver is not appropriate to drive a high speed signal onto a transmission line in the presence of large parasitic capacitance and inductance due to bonding wires and pads. The differential voltage driver  108  comprises a first inverter circuit  302   a  and a second inverter circuit  302   b.    
         [0037]    The first inverter circuit  302   a  comprises a NMOS transistor M 1 , a PMOS transistor M 2 , and an inverter  304   a . The NMOS transistor M 1  has its gate coupled to a supply voltage, its drain coupled to a first node  306   a , and its source coupled to a second node  308   a . The PMOS transistor M 2  has its gate coupled to an electrical ground, its drain coupled to the first node  306   a , and its source coupled to the second node  308   a . The inverter  304   a  has its input coupled to the first node  306   a  and its output coupled to the second node  308   a . The first node  306   a  is also coupled to receive the negative polarity (−) output from the serializer  110 . The second node  308   a  is also coupled to output a positive polarity (+) output to the transmission medium (for example, a cable). Thus, the circuitry of the first inverter circuit  302   a  operates to receive the negative polarity data signal from the serializer  110 , invert the signal, and output a positive polarity data signal to the transmission medium. M 1  and M 2  are used as feedback resistors which reduce the voltage swing of the inverter  304   a  as well as reducing the output impedance.  
         [0038]    The second inverter circuit  302   b  comprises a NMOS transistor M 1 , a PMOS transistor M 2 , and an inverter  304   b . The NMOS transistor M 1  has its gate coupled to a supply voltage, its drain coupled to a first node  306   b , and its source coupled to a second node  308   b . The PMOS transistor M 2  has its gate coupled to an electrical ground, its drain coupled to the first node  306   b , and its source coupled to the second node  308   b . The inverter  304   b  has its input coupled to the first node  306   b  and its output coupled to the second node  308   b . The first node  306   b  is also coupled to receive the positive polarity (+) output from the serializer  110 . The second node  308   b  is also coupled to output a negative polarity (−) output to the transmission medium (for example, a cable). Thus, the circuitry of the second inverter circuit  302   b  operates to receive the positive polarity data signal from the serializer  110 , invert the signal, and output a negative polarity data signal to the transmission medium. M 1  and M 2  are used as feedback resistors which reduce the voltage swing of the inverter  304   b  as well as reducing the output impedance.  
         [0039]    [0039]FIG. 4 shows typical circuit configurations of (a) a current mode driver  408  and (b) a voltage mode driver  108 . The voltage mode driver  108  would be in accordance with a preferred embodiment of the present invention.  
         [0040]    In both cases, the driver ( 408  or  108 ) is coupled to a transmission medium via a connection typically including bonding and wire pads. The transmission medium and connection thereto are modeled by two capacitors C 1  and C 2  and an inductor L for each of two lines. C 2  represents the capacitance of each transmission line, and each of the capacitors C 2  is coupled between a transmission line and an electrical ground. Each LC circuit (comprising inductor L and capacitor C 1 ) represents the parasitic inductance and capacitance due to the bonding wires and pads. The other end of the transmission medium is coupled to a receiver via an appropriate connection (including termination). The appropriate connection varies depending upon whether the driver is a current mode driver  408  or a voltage mode driver  108 .  
         [0041]    [0041]FIG. 5 shows simulated waveforms under the configurations shown in FIG. 4 in accordance with a preferred embodiment of the present invention. For purposes of the simulation, in order to model parasitic effects of the transmission medium and the connection thereto, the inductance L was set to be 4nH, and the two capacitors C 1  and C 2  were set to be 2 pF and 4 pF, respectively.  
         [0042]    As shown in FIG. 5( a ), significant inter-symbol interference occurs in the current mode driver  408  configuration. This inter-symbol interference may be attributed to slow, passive pull-up and constant current pull-down. In contrast, as shown in FIG. 5( b ), only an insignificant amount of distortion occurs in the voltage mode driver  108  configuration. This is because the voltage mode driver  108  drives the signal actively in both directions (up and down).  
         [0043]    [0043]FIG. 6 shows a circuit diagram of an on-chip termination circuit  114  in accordance with a preferred embodiment of the present invention. As shown in FIG. 6, the on-chip termination circuit is based on a common gate CMOS configuration. In particular, the on-chip termination circuit  114  includes an internal voltage divider  602 , an impedance matching bias circuit  604 , an external resistor  606 , and a configuration of common gate MOS transistors  608 .  
         [0044]    In accordance with a preferred embodiment, the internal voltage divider  602  includes four resistors ( 610 ,  612 ,  614 ,  616 ) and three nodes (V h , V m , and V l ). The four resistors are coupled in series between a supply voltage and an electrical ground. The three nodes exist between the four resistors. The first resistor  610  couples the supply voltage to the first node V h . The second resistor  612  couples the first node V h  to the second node V m . The third resistor  614  couples the second node V m  to the third node V l . The fourth resistor  616  couples the third node V l  to an electrical ground. The voltage at V h  is relatively high, the voltage at V l  is relatively low, and the voltage at V m  is in between. Finally, each of the three nodes is coupled to the bias circuit  604 . Thus, the internal voltage divider  602  generates three reference voltages.  
         [0045]    In a preferred embodiment, the bias circuit  604  includes three operational amplifiers (opamps)  618 ,  620 , and  622  and 7 transistors (M 0 -M 6 ). The first opamp  618  has its negative terminal coupled to V m  of the voltage divider  602 , its positive terminal coupled to a first node  624 , and its output terminal coupled to a second node  626 . The second opamp  620  has its positive terminal coupled to of the voltage divider  602 , its negative terminal coupled to a third node  628 , and its output terminal coupled to a fourth node  630 . The fourth node  630  is also labeled as voltage V p . The third opamp  622  has its positive terminal coupled to V l , its negative terminal coupled to a fifth node  632 , and its output terminal coupled to a sixth node  634 . The sixth node  634  is also labeled as voltage V N .  
         [0046]    The first transistor MO comprises a PMOS transistor having its source coupled to a supply voltage, its drain coupled to the first node  624 , and its gate coupled to the second node  626 . The second transistor M 1  comprises a PMOS transistor having its source coupled to a supply voltage, its drain coupled to a seventh node  636 , and its gate coupled to the second node  626 . The third transistor M 2  comprises a PMOS transistor having its source coupled to a supply voltage, its drain coupled to the third node  628 , and its gate coupled to the second node  626 . Thus, each of the first three transistors M 0 -M 2  comprise PMOS transistor having their gates controlled by the output of the first opamp  618 .  
         [0047]    The fourth transistor M 3  comprises a NMOS transistor having its source coupled to a supply voltage, its drain coupled to the fifth node  632 , and its gate coupled to the sixth node  634  (V N ). The fifth transistor M 4  comprises a PMOS transistor having its source coupled to the third node  628 , its drain coupled to an electrical ground, and its gate coupled to the fourth node  630  (V P ). The sixth transistor M 5  comprises a NMOS transistor having its source and its gate both coupled to the seventh node  636 , and its drain coupled to an electrical ground. Finally, the seventh transistor M 6  comprises a NMOS transistor having its source coupled to the fifth node  632 , its drain coupled to an electrical ground, and its gate coupled to the seventh node  636 .  
         [0048]    The external resistor  606  includes a resistor, denoted as having a resistance value of Re, coupled between the first node  624  of the bias circuit  604  and an electrical ground. The external resistor  606  is used as a reference impedance.  
         [0049]    The common gate MOS transistors  608  include two NMOS transistors M 7  and M 9 , and two PMOS transistors M 8  and M 0 . The first NMOS transistor M 7  has its source coupled to a supply voltage, its drain coupled to a first output node  638 , and its gate coupled to the sixth node  634  of the bias circuit  604 . The first PMOS transistor M 8  has its source coupled to the first output node  638 , its drain coupled to an electrical ground, and its gate coupled to the fourth node  630  of the bias circuit  604 . The first output node  638  is coupled to the positive polarity line from the transmission medium for termination purposes. The second NMOS transistor M 9  has its source coupled to a supply voltage, its drain coupled to a second output node  640 , and its gate coupled to the sixth node  634  of the bias circuit  604 . The second PMOS transistor M 10  has its source coupled to the second output node  640 , its drain coupled to an electrical ground, and its gate coupled to the fourth node  630  of the bias circuit  604 . The second output node  640  is coupled to the negative polarity line of the transmission medium for termination purposes.  
         [0050]    Operationally, the bias circuit  604  controls the termination voltage and impedance by providing bias voltages V P  and V N  to the gates of the common gate MOS transistors  608 . Within the bias circuit  604 , transistors M 0 , M 1 , M 2 , M 5  and M 6  are connected as current mirrors. All currents in the current mirrors are set as V m /Re. Transistors M 7  and M 9  are replicas of M 3 . Transistors M 8  and M 10  are replicas of M 4 . M 3  generates current Io at V l . M 4  generates current Io at V h .  
         [0051]    [0051]FIG. 7 shows the characteristics of the on-chip termination circuit  114  shown in FIG. 6 for a 75 ohm transmission line in accordance with a preferred embodiment of the present invention. Both voltage  702  and current  704  characteristics are shown. In addition, a voltage versus current graph  706  is also shown.  
         [0052]    The voltage vs. current graph  706  shows net current  706   a , PMOS transistor current  706   b , and NMOS transistor current  706   c . The graph  706  shows that although the impedance of either the PMOS transistor or the NMOS transistor is not linear, the combined effect of the PMOS and NMOS transistors is almost linear when the voltage is around Vdd/2. In particular, when the resistor values in the voltage divider are such that (V h −V m )=(V m −V l ), then the relation between termination resistance R T  and external resistance Re is as follows:  
           R   T =( V   h   −V   m )/ Io=Re ·( V   h   −V   m )/ V   m    
         [0053]    The above equation shows that impedance is independent of supply voltage because both (V h −V m ) and V m  are proportional to Vdd. There is a trade-off between power consumption and termination resistance range.  
         [0054]    [0054]FIG. 8 contrasts (a) a conventional receiver configuration  801  using external termination  806  outside the conventional receiver  804  with (b) the receiver configuration  802  which utilizes on-chip termination  114  within the receiver  104  in accordance with a preferred embodiment of the present invention. As shown in FIG. 8, the conventional receiver configuration  801  has the external termination  806  placed in between the capacitance C 2  of the transmission medium and the LC circuit (L and C 1 ) on the conventional receiver  804 . In contrast, the receiver configuration  802  has the on-chip termination  114  between the LC circuit (L and C 1 ) on the conventional receiver  804  and the rest of the conventional receiver  804 .  
         [0055]    [0055]FIG. 9 contrasts (a) a first simulated waveform  901  in a receiver using external termination in accordance with FIG. 8( a ) with (b) a second simulated waveform  902  in a receiver utilizing on-chip termination in accordance with FIG. 8( b ). The simulations were run assuming the following values: L=4 nH, C 1 =2 pF, and C 2 =4 pF. The simulations also assumed an ideal rectangular pulse train driven through a 75 ohm medium. As shown in FIG. 9, significantly reduced distortion can be seen in the second simulated waveform  902  in comparison to the first simulated waveform  901 . Thus, using the on-chip termination  114  reduces distortion of the received signal.  
         [0056]    [0056]FIG. 10 shows a block diagram of (a) a phase tracker  118  and (b) a frame aligner  122  in accordance with a preferred embodiment of the present invention. In the preferred embodiment shown in FIG. 10( a ), the phase tracker  118  includes a sample rotator  1002 , a first D-type flip flop (DFF) array  1004 , a second D-type flip flop (DFF) array  1006 , a most frequent transition-edge finder  1008 , a phase decision circuit  1010 , and a phase counter  1012 .  
         [0057]    In a preferred embodiment, the rotator  1002  receives thirty samples in parallel from the sampler  116 . The rotator  1002  applies a signal from the phase counter  1012  to shuffle the samples and to the timing of the samples into a RX clock domain. The rotated samples are provided by the rotator  1002  to the DFF arrays  1004  and  1006 . Both the two DFF arrays  1004  and  1006  also receives the RX clock signal from the RX clock selector  120  for control purposes. In particular, the first  15  samples are provided to the first DFF array  1004 , and the second  15  samples are provided to a second half of the second DFF array  1006 . The first DFF array  1004  provides its contents to a first half of the second DFF array  1006 . The second DFF array  1006  outputs 10 bits of data in parallel to the frame aligner  122 , and also outputs its contents to the finder  1008 .  
         [0058]    In a preferred embodiment, the finder  1008  determines the most frequent transition-edge in the contents provided by the second DFF  1006 . The most frequent edge information is passed from the finder to the phase decision circuit  1010 . By continuously monitoring the most frequent transition-edge in the oversampled data, the phase of the RX clock keeps track of the sender&#39;s clock. In a preferred embodiment, the phase decision circuit  1010  uses the most frequent transition-edge information to determine whether an up signal or a down signal should be sent to the phase counter  1012 . The phase counter  1012  applies any up or down signal received from the phase decision circuit  1010  and provides a 10-bit phase pointer to the rotator  1002  and to the clock selector  120 . The phase pointer indicates which clock among the 30 PLL clocks is closest to the clock of the transmitter  102 .  
         [0059]    In the preferred embodiment shown in FIG. 10( b ), the frame aligner  122  includes a D-type flip flop (DFF) array  1016 , a comma detector  1018 , a comma pointer  1020 , and a data selector  1022 . The DFF array  1016  stores the previous 9 bits of word-unaligned data from the phase tracker  118  and provides them to a comma detector  1018 . The comma detector  1018  also receives the current 10 bits of word-unaligned data from the phase tracker  118 . The comma detector  1018  searches across the 19 bit data sequence to detect any comma which would comprise the sequence of bits 0011111010. The detected position of a comma is stored using a comma pointer  1020 . The comma pointer  1020  is used by the data selector  1022  to extract the word aligned 10 bits of data until a new comma is detected.