Abstract:
A thin film transistor (TFT) structure is provided. The TFT comprises a gate, a first electrode, a second electrode, a dielectric layer, and a channel layer. By overlapping the area between the first electrode and the gate, the TFT structure acquires a parasitic capacitor that is unaffected by manufacture deviations. Therefore, the TFT needs no compensation capacitor, thereby, increasing the aperture ratio of the TFT.

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
       [0001]    This is a divisional application of patent application Ser. No. 11/849,593 filed on Sep. 4, 2007, now allowed. The prior application Ser. No. 11/849,593 claims the benefit of Taiwan Patent Application No. 095146465 filed on Dec. 12, 2006, the disclosures of which are incorporated herein by reference in their entirety. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
       [0002]    Not applicable. 
       BACKGROUND OF THE INVENTION 
       [0003]    1. Field of the Invention 
         [0004]    The present invention relates to a TFT structure; specifically, it relates to a TFT structure for use in a TFT liquid crystal display. 
         [0005]    2. Descriptions of the Related Art 
         [0006]    In recent years, flat panel displays have gradually replaced conventional cathode ray tube displays. Current flat panel displays include: organic light-emitting diodes displays (OLEDs), plasma display panels (PDPs), liquid crystal displays (LCDs), field emission displays (FEDs), etc. An essential component of these flat panel displays is the thin-film transistor (TFT), which controls the on and off state of each pixel. 
         [0007]    Stability is important to maintain during the panel manufacturing process to ensure good product quality and enhance manufacturing yield rates. However, during the manufacturing process, varying circumstantial conditions can cause the manufacturing parameters to deviate, resulting in electrical characteristic deviation in each TFT on the panel. For example, a parasitic capacitance of each TFT presents different distributions depending on the different areas of the panel. Because parasitic capacitances can occur all over the panel, non-uniform distributions of the parasitic capacitances will cause non-uniform distributions of the voltage jumps, resulting in the flickering of the screen. 
         [0008]    To generally suppress the screen flickering, a compensating capacitor connected with the TFT has been designed to neighbor the original TFT for eliminating the effect of the TFT parasitic capacitance caused by the manufacturing process deviation. However, adding the compensating capacitor on the panel takes up space needed for lighting, and decreases the aperture ratio (i.e. the ratio between the pixel lighting area and total pixel area) accordingly. Moreover, a large compensating capacitor should not be used because it may result in an over range of the voltage jump. 
         [0009]    In view of the above-mentioned issue, it is essential for the industry to provide a transistor structure for effectively reducing the area occupied by the compensating capacitors in circuit layouts. 
       SUMMARY OF THE INVENTION 
       [0010]    One objective of this invention is to provide a TFT structure for use in a LCD. The TFT comprises a gate electrode, a first electrode, a second electrode, a dielectric layer and a channel layer. The gate electrode connects to the LCD scanning line and overlaps with the working area of the TFT structure. The first electrode is disposed on two sides of the working area. The second electrode is disposed in the center of the working area. The dielectric layer is disposed between the gate electrode and the working area. The channel layer is disposed under the first and the second electrodes and is electrically connected to the first and the second electrodes. The first electrode is parallel to the second electrode in the working area, which overlaps with the gate electrode. One of the first electrodes and second electrodes are connected to the pixel electrode of the LCD, while the other electrodes are connected to the data line of the LCD. 
         [0011]    Another objective of this invention is to provide a TFT structure for use in a LCD. The TFT comprises a gate electrode, a first electrode, a second electrode, a dielectric layer and a channel layer. The gate electrode connects to the LCD scanning line and overlaps with the working area of the TFT structure. The first electrode includes two branches disposed on the center area of the working area. The second electrode includes three branches respectively disposed in the center, as well as two sides of the working area. The dielectric layer is disposed between the gate electrode and the working area. The channel layer is disposed under the first and the second electrodes and is electrically connected to the first and the second electrodes. The branches of the second electrode are disposed on two sides of the branches of the first electrode respectively. The first electrode is parallel to the second electrode in the working area, which overlaps with the gate electrode. One of the first electrode and the second electrode is connected to the pixel electrode of the LCD, while the others thereof are connected to the data line of the LCD. 
         [0012]    The invention provides stability to the TFT, thereby preventing deviation and parasitic capacitance in the manufacturing process. Meanwhile, since no extra compensating capacitor is required, the parasitic capacitance will not increase significantly when the TFT structure area is increased to obtain a higher conduction current. 
         [0013]    The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0014]      FIG. 1  is a schematic diagram illustrating the top view of a first embodiment of the invention; 
           [0015]      FIG. 2  is a schematic diagram of a partial sectional view of the first embodiment; and 
           [0016]      FIG. 3  is a schematic diagram illustrating the top view of a second embodiment of the invention. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
       [0017]      FIG. 1  is a schematic diagram illustrating the top view of a TFT structure  1  of a first embodiment of the invention is shown. The TFT structure  1  comprises a primary TFT  11  and an auxiliary TFT  12 . The primary TFT  11  and the auxiliary TFT  12  are electrically connected to each other in parallel and share a gate electrode  115 . The primary TFT  11  comprises a first electrode  111  and a second electrode  112 , and both electrodes connect to a drain and the source of the primary TFT  11 , respectively, wherein the second electrode  112  comprises a horizontal size, i.e. a width. The auxiliary TFT  12  comprises a third electrode  113  and a fourth electrode  114 , both connect to the drain and the source of the auxiliary TFT  12  respectively. The second electrode  112  electrically connects to the fourth electrode  114 , while the first electrode  111  and the third electrode  113  connect to different pixel electrodes (not shown). Meanwhile, the second electrode  112  connects to a data line (not shown). In this embodiment and the following embodiment, the only difference between the source and the drain is their names for representing providing and receiving terminals of holes or electrons without any substantial manufacturing process difference. 
         [0018]    In this embodiment, within the area overlapping the gate electrode  115 , a working area is formed between the channel, which is located between the drain and the source, and the gate electrode  115 . The first electrode  111  is parallel to the second electrode  112  for maintaining uniformity of the TFT channel lengths. The first electrode  111  overlaps with the gate electrode  115  in a direction parallel to the channel and extends outside the working area. That is, the first electrode  111  overlaps with the working area and extends outside the working area. In this embodiment, the overlapping area of the first electrode  111  and the gate electrode  115  comprises a horizontal size, i.e. a width, of about 1˜10 μm, preferably 4˜7 μm. Meanwhile, the second electrode  112  also comprises a horizontal size, i.e. a width, of about 1˜10 μm, preferably 4˜7 μm. When the manufacturing process parameters deviate, such as the case resulting from the misalignment of the manufacturing process for the first electrode  111 , the left side portion of the first electrode  111  that extends outside the working area may deviate to the right. Meanwhile, the right side of the first electrode  111  that extends outside the working area may deviate to the right synchronously. Consequently, the total overlap area of the first electrode  111  remains the same. Similarly, the total overlap area of the first electrode  111  and the gate electrode  115  remains the same as well. The capacitance value of the flat type capacitors is decided by the overlapping area between the upper and lower electrode of the capacitor and the dielectric layer therebetween. Thus, the total overlap between the first electrode  111  and the gate electrode  115  remains constant, and as a result, the parasitic capacitance between the gate and the drain of the primary TFT  11  is stable and not affected from the deviation generated from the manufacturing process. 
         [0019]    Moreover, in this embodiment, the auxiliary TFT  12  also relies on the structure to maintain stable parasitic capacitance when deviation occurs during the manufacturing process. The fourth electrode  114  and the second electrode  112  of the auxiliary TFT  12  are connected directly. In the horizontal extension direction overlapping the working area and the third electrode  113  of the auxiliary TFT  12 , the gate electrode  115  comprises an indented shape so that the center area does not overlap with the gate electrode  115 . Only the two sides of the third electrode  113  and the gate electrode  115  form two overlaps when the third electrode  113  extends outside the working area. Herein, when manufacturing parameter deviation occurs, such as the deviation which results from the manufacturing misalignment of the third electrode  113 , the whole third electrode  113  will be synchronously deviated. Consequently, the total overlap area of the first electrode  113  and the gate electrode  115  does not change and the parasitic capacitance between the gate and the drain of the auxiliary TFT  12  stay stable without being affected by the deviation generated during the manufacturing process. 
         [0020]    In this embodiment, the primary objective of the first electrode  111  and the third electrode  113  is to maintain that the overlapping area overlapped by the electrodes  111 ,  113  and the gate electrode  115  will not be affected by the manufacturing process deviation. Consequently, the first electrode  111  and the third electrode  113  have to be designed to partially overlap with the gate electrode  115  and extend outside the gate electrode  115 . In this embodiment, the first electrode  111  and the third electrode  113  extend out in a direction parallel to the channel. For different layouts, the first electrode  111  and the third electrode  113  can extend out in the direction normal to the channel as well. 
         [0021]    Meanwhile, since no extra compensating capacitor is required, the parasitic capacitance will not increase significantly when the TFT structure area is enlarged to obtain a higher conduction current. 
         [0022]      FIG. 2  is a cross-sectional view of the primary TFT  11  sectioned along an AA′ line in  FIG. 1 , wherein a silicon nitride layer  116  is located between the gate electrode  115  and the working area  118 . The silicon nitride layer  116  acts as a dielectric layer, while the channel layer is found beneath the first electrode  111  and the second electrode  112 . In this embodiment, the channel layer can be an amorphous silicon layer  117  electrically connected to the first electrode  111  and the second electrode  112  to provide a channel for carriers flow. The auxiliary TFT  12  is similar to the primary TFT  11  in cross-sectional structure. 
         [0023]      FIG. 3  is a schematic diagram illustrating the top view of the TFT structure  3  of the second embodiment of the invention. The TFT structure  3  comprises a primary TFT  31  and an auxiliary TFT  32 . The primary TFT  31  and the auxiliary TFT  32  are also electrically connected to each other in parallel and share a gate electrode  315 , wherein the primary TFT  31  comprises a first electrode  311  and a second electrode  312 , which connect to the drain and source of the primary TFT  31  respectively. Similarly, the auxiliary TFT  32  comprises a third electrode  313  and a fourth electrode  314  which connect to the drain and source of the auxiliary TFT  32 , respectively. The second electrode  312  electrically connects to the fourth electrode  314 , while the first electrode  311  and the third electrode  313  connects to different pixel electrodes (not shown). Meanwhile, the second electrode  312  connects to a data line (not shown). 
         [0024]    In this embodiment, within an area overlapping the gate electrode  315 , a working area is formed between the channel, which is located between the drain and source, and the gate electrode  315 . The first electrode  311  comprises two branches disposed in the center of the working area, while the second electrode  312  comprises three branches which are respectively disposed in the center area and two sides of the working area. The branches of the first electrode  311  and the second electrode  312  are arranged in an interleave fashion, i.e. branches of the second electrode  312  are respectively disposed on two sides of the branches of the first electrode  311  and are parallel to each other for maintaining uniform TFT channel lengths. The first electrode  311  overlaps with the gate electrode  315  in a direction normal to the channel and extends outside the working area. That is, the first electrode  311  overlaps with the working area and extends outside the working area. In this embodiment, each branch of the first electrode  311  has a horizontal size, i.e. a width, of about 1˜10 μm, preferably 4˜7 μm. The center branch of the second electrode  312  comprises a horizontal size, i.e. a width, of about 1˜10 μm, preferably 4˜7 μm. The two overlapping regions of the second electrode  312  and the gate electrode  315 , i.e. the two overlapping areas between the two side branches and the gate electrode  315 , respectively, have a horizontal size, i.e. a width, of about 1˜10 μm, preferably 4˜7 μm. When manufacturing process parameters deviate, such as the deviation resulting from the misalignment of the first electrode  311  during the manufacturing process, the left side of the first electrode  311  that extends outside the working area may deviate to the right. Meanwhile, the right side of the first electrode  311  that extends outside the working area deviates to the right synchronously. Consequently, the total overlapping area between the working area and the first electrode  311  remains the same. Similarly, the total overlapping area between the first electrode  311  and the gate electrode  315  also remain the same. Like the first embodiment, the total overlap area of the first electrode  311  and the gate electrode  315  does not change and the parasitic capacitance between the gate and the drain of the primary TFT  31  remain stable without being affected by the deviation generated during the manufacturing process. 
         [0025]    Furthermore, in this embodiment, the auxiliary TFT  32  also relies on the structure to maintain a stable parasitic capacitance when deviation occurs during the manufacturing process. The fourth electrode  314  of the auxiliary TFT  32  and the second electrode  312  are directly connected. The gate electrode  315  of the auxiliary TFT  32  comprises an indented shape so that the center area portion does not overlap with the gate electrode  315  and only two sides and the gate electrode  315  form two overlaps when the third electrode  313  extends outside the working area. Herein, when manufacturing parameter deviation occurs, such as the deviation resulting from the misalignment of the third electrode  313  during the manufacturing process, the whole third electrode  313  synchronously deviates. Consequently, the total overlap area of the first electrode  313  and the gate electrode  315  does not change and the parasitic capacitance between the gate and the drain of the auxiliary TFT  32  maintain stability without being affected by the deviation generated during the manufacturing process. Meanwhile, since no extra compensating capacitor is required, the parasitic capacitance will not increase significantly when the TFT structure area is enlarged to obtain a higher conduction current. 
         [0026]    In this embodiment, the design rules of the first electrode  311  and the third electrode  313  are the same as those of the first embodiment; thus, the details are omitted here. Alternatively, the first electrode  311  and the third electrode  313  can also extend out in the direction parallel to the channel as well. 
         [0027]    The above disclosure is related to the detailed technical contents and inventive features thereof. People skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.