Abstract:
The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     Generally, the present disclosure relates to highly sophisticated semiconductor structures, and, in particular, to a protection layer for avoiding vertical voltage breakdown in highly advanced semiconductor technologies. 
     2. Description of the Related Art 
     The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. This includes several connection lines between different components, such as transistors and diodes. The connection lines are organized on multiple vertical levels, also known as metal levels. On each metal level, a plurality of connection lines may be realized. 
     The proximity, both horizontal and vertical, of connection lines results in several issues. The signal in a given line may be influenced by neighboring lines due to the parasitic capacitance present between the lines. Even more dangerously, there is a risk of a voltage breakdown between neighboring lines. 
     The possibility of a voltage breakdown depends on the materials used, the voltages present and the dimensions and placement of the lines. In view of further device scaling, it is expected that the distance between neighboring metal lines will get smaller and smaller at each technology node, both in the vertical and horizontal direction. This increases the risk of a breakdown through the insulator between the metal lines. 
     Although this is at least partially compensated for by the reduction in operating voltages, there are applications in which voltages cannot be reduced enough to compensate for the reduced distance, for instance, automotive or high voltage applications such as those needed for the operation of fuses or similar devices. 
     Moreover, while the horizontal distance between metal lines can be varied for each metal line with respect to its neighboring lines, the same cannot be done in the vertical direction. So, for instance, if, on a metal level, only one metal line has a high voltage applied to it, horizontally neighboring metal lines can be spaced further apart to avoid any issues. However, the same cannot be done in the vertical direction since the increase in the vertical spacing would negatively reflect on all of the metal lines of the metal plane, which do not need the increased vertical spacing, and not only on the one carrying the high voltage. 
     In view of the situation described above, the present disclosure relates to semiconductor structures and manufacturing techniques thereof allowing the realization of at least one high voltage metal line on a metallization level of an integrated chip which avoids the risk of voltage breakdown. 
     SUMMARY OF THE INVENTION 
     The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later. 
     Generally, the present disclosure solves the above-mentioned problems by using a dielectric prevention layer, at least in the vertical direction, increasing the dielectric separation in the vertical direction between neighboring metal lines. 
     One illustrative embodiment disclosed herein may relate to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line. In some embodiments, the breakdown prevention layer may comprise any of SiN, SiCN, TEOS or any other dielectric film. In some embodiments, the breakdown prevention layer may have a thickness up to a few tens of nm. In some embodiments, the part of the vertical space separating the first connecting line from the second connecting line not occupied by the breakdown prevention layer comprises a silicon-based insulator, preferably SiCOH or SiO2. In some embodiments, the first connecting line and/or the second connecting line may be made of copper and/or copper alloys, preferably CuMn and/or CuAl, and/or aluminum. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which: 
         FIG. 1 a    schematically illustrates a cross-sectional view along section A-A′ of  FIG. 1 b    of a semiconductor structure according to the state of the art; 
         FIG. 1 b    schematically illustrates a top view of  FIG. 1 a   , according to the state of the art; 
         FIG. 2 a    schematically illustrates a cross-sectional view along section A-A′ of  FIG. 2 b    of a semiconductor structure according to an embodiment of the invention; and 
         FIG. 2 b    schematically illustrates a top view of  FIG. 2 a   , according to an embodiment of the invention. 
     
    
    
     While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. 
     DETAILED DESCRIPTION 
     Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers&#39; specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. 
     The following embodiments are described in sufficient detail to enable those skilled in the art to make use of the invention. It is to be understood that other embodiments would be evident, based on the present disclosure, and that system, structure, process or mechanical changes may be made without departing from the scope of the present disclosure. In the following description, numeral-specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the embodiments of the disclosure may be practiced without the specific details. In order to avoid obscuring the present disclosure, some well-known circuits, system configurations, structure configurations and process steps are not disclosed in detail. 
     The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase. 
       FIG. 1 a    schematically illustrates a cross-sectional view of a semiconductor structure  1  in accordance with the state of the art.  FIG. 1 b    schematically illustrates a top view of the same semiconductor structure. The cross-sectional view of  FIG. 1 a    is taken along line A-A′ of  FIG. 1   b.    
     In  FIG. 1 a   , two metal levels M 1  and M 2  are illustrated. This is for convenience only, and several metal levels could be present instead. Also, for convenience, only one metal line  300  is shown on metal level M 1  and only two metal lines  100  and  200  are shown on metal level M 2 . Also in this case, several metal lines could be realized instead. 
     As can be seen, the vertical distance between two metal lines  100  and  300  is D 2 , which may have a value in the range of tens to hundreds of nanometers. The horizontal distance between two metal lines  100  and  200  is D 1 , which may have a value larger than 40 nm. As previously mentioned, the horizontal distance D 1  may be changed for each couple of metal lines on the same metal level. In this way, if one metal line has a higher voltage to carry, the neighboring metal lines may be spaced further away. To the contrary, the distance D 2  must be the same for all metal lines in level M 1  and M 2 . Increasing distance D 2  only to avoid voltage breakdown on a single metal line  100 , where several other thousand metal lines  200  on the same level do not need such an increased distance, would not be effective as it would increase the thickness of the chip, thus increasing costs, slowing down signal propagation and worsening heat dissipation. 
       FIG. 2 a    schematically illustrates a cross-sectional view of a semiconductor structure  2  in accordance with an embodiment of the present invention.  FIG. 2 b    schematically illustrates a top view of the same semiconductor structure. The cross-sectional view of  FIG. 2 a    is taken along line A-A′ of  FIG. 2 b   . It should be noted that, for ease of visual representation, in  FIG. 2 b   , the layer  410  above metal lines  101 ,  201  and  301  is not illustrated. 
     In semiconductor structure  2 , the dielectric insulation in the vertical direction between metal lines  101 - 301  and between metal lines  201 - 301  is increased by means of a dielectric breakdown prevention layer  430 . The dielectric breakdown protection layer  430  could be any of SiN, SiCN, TEOS, or other silicon-based dielectrics. It could be put in place prior to the realization of metal lines  101  and  201  by means of physical vapor deposition (PVD), chemical vapor deposition (CVD) or spin-on processes. The metal lines could be made of Cu and/or Cu alloys, such as CuMn or CuAl, or Al, or, in general, any metallic material. The dielectric between the metal lines could be silicon-based, such as SiCOH or SiO2. Each of layers  410 ,  420 ,  430  could have a thickness in the range of 5-30 nm, which may become smaller in future technologies. 
     Thanks to the presence of dielectric breakdown prevention layer  430 , the dielectric insulation between the metal lines is increased, at least in the vertical direction. In fact, the dielectric breakdown prevention layer  430  may have a dielectric constant larger than four, which is higher than the dielectric constant of the dielectric usually present in the space between the metal lines  101 ,  201  and  301 , such as, for instance, silicon oxide, or SiCOH with a dielectric constant, for instance, smaller than three. Moreover, in some embodiments, the layer  430  could be used as an etch damage protection layer of the dielectric during trench etch. 
     The addition of the dielectric breakdown prevention layer  430  does not negatively impact the signal propagation. In particular, due to the presence of the breakdown prevention layer  430 , the thickness in the Y direction of metal line  101  and  201  is reduced and this increases the resistance of the lines. However, the increased resistance could be brought back to its original value (i.e., without the breakdown prevention layer  430 ) by increasing the thickness of the metal line  101 ,  201 . Alternatively, the increased resistance could be tolerated since, usually, high voltage metal lines do not carry signals with a critical impact on the timing of the ASIC. 
     Moreover, although both lines  101  and  201  are illustrated as being provided with the breakdown prevention layer  430 , the invention is not limited thereto. The application of the breakdown prevention layer  430  could be limited to those lines carrying a voltage higher than a certain threshold, for instance 1.8V in a 28 nm node. That is, assuming, for instance, that metal line  101  has a low voltage and metal line  201  has a high voltage signal, only metal line  201  could be provided with the breakdown prevention layer  430 . 
     Furthermore, it will be clear to those skilled in the art that, although described and illustrated, layers  410  and  420  are not necessary to carry out the present invention and they have been included for providing additional details on one specific implementing embodiment of the present invention. In particular, layer  410  may be a SiCN based dielectric cap with any of the following functions: (a) adhesion layer between Cu and SiCOH (dielectric), and/or (b) etch stop layer for via etch, and/or (c) prevent Cu diffusion into the dielectric, while layer  420  may be a Ta-based barrier (bi-) layer to prevent Cu diffusion into the dielectric. Alternatively, or in addition, the breakdown prevention layer  430  could be in direct contact with the metal line  101  and/or  201  and/or  301 . 
     Moreover, although the breakdown prevention layer  430  has been illustrated as being placed underneath metal lines  101  and  201 , the present invention is not limited thereto. Alternatively, or in addition, it will be clear to those skilled in the art that the same result could be achieved by placing it above metal line  301 , and/or anywhere in the space vertically separating lines  101  and  301  or lines  201  and  301 . 
     Additionally, although connecting lines  100 - 300  and  101 - 301  have been described as metal lines, the present invention is not limited to the use of fully metallic connecting lines. Alternatively, or in addition, lines containing doped semiconducting material, or a mixture of the latter and metal, such as, for instance, silicide lines, could be used. 
     The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.