Abstract:
Methods and apparatus for reducing the common mode voltage generated by eliminating zero-voltage vectors in a rectifier/inverter variable frequency drive (VFD) system includes comparing three phase voltages to each other to determine a maximum voltage in one phase, a minimum voltage in another phase and a middle voltage in still another phase, inverting phase voltages for one phase having the maximum voltage and another phase having the minimum voltage, comparing the phase voltages to a carrier wave to determine gating signals for three respective phases of the inverter, and inverting gating signals for the one phase having the maximum voltage and for another phase having the minimum voltage to reduce the common mode voltage in the motor. In one embodiment, the zero-voltage vectors are removed by relating a first plurality of gating signals and a plurality of sector logic signals in a logic table to a second plurality of gating signals that are applied to phases of the inverter

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     NOT APPLICABLE  
       STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH  
       [0002]     NOT APPLICABLE  
       TECHNICAL FIELD  
       [0003]     The field of the invention is control systems for controlling the operation of AC motors.  
       BACKGROUND ART  
       [0004]     A well known type of AC drive includes an AC-to-DC converter including a boost rectifier for converting three-phase AC source voltages to DC voltages on a DC bus. The DC bus interfaces the AC-to-DC converter to a DC-to-AC inverter, which is typically a three-phase bridge network of solid state switches, which are switched at high frequency to generate pulse width modulation (PWM) or other types of modulated low frequency power signals which are supplied to an AC motor. These systems generate a common mode voltage, for example, a voltage measured between a neutral in the motor and an electrical ground. These also generate common mode currents in part the result of parasitic capacitances between mechanical parts in the motor and ground, and between mechanical parts in the motor and the stator windings. It is desirable to attenuate or eliminate these voltages to prevent interference that might trip fault protection devices and to reduce currents in motor bearings that might reduce their service life. Passive circuits including filters and transformers have been employed to correct this problem, but with increased production costs and increased installation costs. A number of prior art publications have suggested modifications to inverter modulation methods to control the inverter common mode voltages. This approach has cost and manufacturing advantages over passive circuits.  
         [0005]     The inverter switching states can be modeled with the aid of a space vector PWM (SVPWM) theory and diagram more fully described below. Two of the vectors in this theory are zero-voltage switching vectors (V 0  and V 7 ). Some prior art methods skip these vectors by using two active vectors that are 180 degrees out of phase. However, these modified modulation schemes require that dwell time (on time for the inverter switches) be calculated in real time.  
         [0006]     Some modified modulators shift the active voltage vectors of the inverter to align with those of the boost rectifier. With this strategy, it is possible to eliminate one common-mode voltage pulse in every switching period by shifting the active voltage vectors of the inverter to align with those of the boost rectifier. Compared with the conventional three-phase SVPWM methods, this proposed method can reduce the total number of common-mode voltage pulses to two-thirds. However, this SVPWM strategy cannot be applied to diode front-end variable frequency drive (VFD) systems that are more common in AC motor drives. For those modified modulators for active front-end VFD systems, dwell times are calculated in real time to shift the active voltage vectors, and those shifts are performed in each switching period.  
         [0007]     It would be advantageous to provide common-mode voltage reduction methods for a PWM carrier-based modulator by eliminating zero-voltage vectors.  
       SUMMARY OF THE INVENTION  
       [0008]     The present invention relates generally to methods for reducing the common mode voltage generated by removing zero-voltage vectors in a converter/inverter variable frequency drive system. This invention is more particularly applied for common mode voltage reduction in a preferred embodiment in which modulation techniques are based on carrier-based pulse width modulation (PWM). The proposed common mode voltage reduction methods can be applied to a carrier-based PWM modulator.  
         [0009]     In a method of the invention, the three phase voltages are compared to each other to determine a maximum voltage in one phase, a minimum voltage in another phase and a middle voltage in still another phase. The phase voltages are also compared to a carrier wave to produce gating signals for turning on switches in a three-phase inverter. For the one phase having the maximum voltage and for another phase having the minimum voltage the phases are inverted prior to their comparison with the carrier wave to produce the gating signals. The gating signals for the one phase having the maximum voltage and for another phase having the minimum voltage are then inverted. This method produces gating signals that will reduce the peak-to-peak common mode voltage in the motor.  
         [0010]     The determination of maximum, minimum and middle voltages in each time period and the inverting of the modulated phase signals can be carried out by a microelectronic CPU executing a stored control program of instructions, or these acts can be carried out with non-CPU logic circuitry. The inverting of the gating signals can be also performed by a microelectronic CPU or by non-CPU logic circuitry.  
         [0011]     In still another variation of the invention, certain zero-voltage vectors are removed in a non-CPU logic circuit in which a first plurality of gating signals and a plurality of sector logic signals are related in a logic table to a second set of gating signals that are applied that eliminate the zero-vectors in the space vector diagram model (“SVPWM”).  
         [0012]     The invention will enable one to reduce the peak-to-peak common mode voltage using a lower cost solution than the prior art.  
         [0013]     These and other objects and advantages of the invention will be apparent from the description that follows and from the drawings which illustrate embodiments of the invention, and which are incorporated herein by reference.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a block diagram of a motor drive for practicing the methods of the present invention;  
         [0015]      FIG. 2  is a space vector diagram illustrating the direct digital SVPWM principles;  
         [0016]      FIG. 3  is a graph of the three-phase common mode voltage (CMV) as a function of time in the system of  FIG. 1  without practicing reduction methods for these voltages;  
         [0017]      FIG. 4  is a graph of a voltage (V no ) between a neutral (n) and a dc link midpoint (o) seen in the system of  FIG. 1  without practicing reduction methods for these voltages;  
         [0018]      FIG. 5  is a graph of the three-phase common mode voltage (CMV) as a function of time in the system of  FIG. 1  with an active controlled converter;  
         [0019]      FIG. 6  is a flow chart of a program routine for modifying the switching signals in the inverter to reduce the three-phase common mode voltage;  
         [0020]      FIG. 7  is a logic diagram for further illustrating the method of  FIG. 6 ;  
         [0021]      FIG. 8  is graph of the inverter switch gating signals as a function of time using the method of  FIGS. 6 and 7 ;  
         [0022]      FIG. 9  is a flow chart of a second program routine for modifying the switching signals in the inverter to reduce the three-phase common mode voltage;  
         [0023]      FIGS. 10-15  are diagrams of the gating signals G 1 , G 3 , G 5  for the inverter switches as a function of time before modification and the gating signals G 1 ′, G 3 ′, G 5 ′ for the inverter switches as a function of time after modification according to the present invention;  
         [0024]      FIG. 16  shows a circuit diagram with a state table logic circuit for controlling the gating signals to the inverter switches; and  
         [0025]      FIGS. 17-19  are state table logic diagrams for gate pulses, G 1 ′, G 3 ′ and G 5 ′, respectively.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0026]      FIG. 1  illustrates a block diagram of an AC drive controller  10  for controlling an AC-to-DC converter  11  including a converter, for example, a boost rectifier, for converting three-phase AC source voltages, V a , V b  and V c , from an AC voltage supply  12  to DC voltages, V dc , on a DC bus  13 . The DC bus  13  interfaces the AC-to-DC converter  11  to a DC-to-AC inverter  14 , which is typically a three-phase bridge network of solid state switches SW 1 -SW 6 , which are switched at high frequency to generate pulse width modulation (PWM) or other types of modulated low frequency power signals V u , V v , V w , which are applied to an AC motor  15 .  
         [0027]     The controller  10  includes a microelectronic CPU  16  operating according to instructions in a control program  17  stored in memory. The program  17  includes instructions for performing regulation of a DC bus voltage and regulation of current supplied to the motor  15 . The controller provides gating signals  19  to control the switching of the switches SW 1 -SW 6  in the inverter  14 . These switches SW 1 -SW 6  are preferably IGBT&#39;s of a type well known in the art.  
         [0028]     The common mode voltage (CMV) is defined in expression 1) below as the voltage difference between the neutral point “n” in the motor  15  and the ground “g” for the AC voltage supply  12 . It is the sum of the voltage V no  between the midpoint “o” of the DC bus and the neutral point “n” in the motor  15  and the voltage V og  between the midpoint “o” of the DC bus  13  and ground “g” for the AC voltage supply  12 . The voltages V no  and V og  are three-phase voltages summed from the individual phase voltages of the motor  18  and the AC voltage supply  12  as shown in expressions 2) and 3) below.
 
 CMV=V   ng   =V   no   +V   og   1)
 
 V   no =( V   uo   +V   vo   +V   wo )/3  2)
 
 V   og =−( V   ao   +V   bo   +V   co )/3  3)
 
         [0029]     The frequency and amplitude of V no  is determined by the AC supply mains, which produce a positive 180 Hz (or 150 Hz) ripple waveform and negative 180 Hz (or 150 Hz) ripple waveform in the common mode voltage. Another part of CMV, V no , is related to the inverter modulation, and its amplitude is shown in Table 1 below.  
                                         TABLE 1                           Common mode voltages for diode front-end variable       frequency drive system.            Vector   State (G1, G3, G5)   V uo     V vo     V wo     V no                 V 0     0, 0, 0   −V dc /2   −V dc /2   −V dc /2   −V dc /2       V 1     1, 0, 0   V dc /2   −V dc /2   −V dc /2   −V dc /6       V 2     1, 1, 0   V dc /2   V dc /2   −V dc /2   V dc /6       V 3     0, 1, 0   −V dc /2   V dc /2   −V dc /2   −V dc /6       V 4     0, 1, 1   −V dc /2   V dc /2   V dc /2   V dc /6       V 5     0, 0, 1   −V dc /2   −V dc /2   V dc /2   −V dc /6       V 6     1, 0, 1     dc /2   −V dc /2   V dc /2   V dc /6       V 7     1, 1, 1   V dc /2   V dc /2   V dc /2   V dc /2                  
 
         [0030]     An example of the waveform of both CMV and V no  for diode front-end VFD system is shown in  FIGS. 3 and 4 , respectively. According to the switching states configuration summarized in Table 1 above, instantaneous values of V no  of the diode front-end VFD system can be determined from equation 4).  
               V   no     =     {             ±       V   dc     2       ⁢           ⁢   for   ⁢           ⁢     V   0     ⁢           ⁢   and   ⁢           ⁢     V   7                   ±       V   dc     6       ⁢           ⁢   for   ⁢           ⁢   other   ⁢           ⁢   states                     4   )             
 
         [0031]     According to the space vector PWM model, there are eight available output voltage vectors (V 0 -V 7 ) for both the converter and inverter as shown in  FIG. 2 . There are two zero-voltage vectors V 0 , V 7  and six non-zero voltage vectors (V 1 -V 6 ). The transition from each non-zero voltage vector to the next non-zero voltage vector defines one of six sectors S 1 -S 6  in the circle diagram in  FIG. 2 . The possible CMV states for the various output voltage vectors (V 0 -V 7 ) of the converter/inverter system are summarized in Table 2 as follows as a function of dc voltage, V dc .  
                                                   TABLE 2                           Common mode voltages as a function of active converter and       inverter output voltage vectors.                Inverter Output Voltage Vector                    V 1 , V 3 ,    V 2 , V 4 ,                       V 5     V 6     V 0     V 7                 Converter   V 1 , V 3 , V 5     0   V dc /3   −V dc /3   2 V dc /3       Output Voltage   V 2 , V 4 , V 6     −V dc /3   0   −2 V dc /3   V dc /3       Vector   V 0     V dc /3   2 V dc /3   0   V dc             V 7     −2 V dc /3   −V dc /3   −V dc     0                  
 
         [0032]     In the case of an asynchronous switching sequence or a different switching frequency between the boost rectifier and inverter, a common mode voltage (CMV) with peak-to-peak amplitude of 2V dc  can occur, as illustrated in  FIG. 5 . The V no  waveform is equal to V dc  as seen in  FIG. 4 . The waveform for CMV is equal to 2V dc  for active front-end VFD system as shown in  FIG. 5 .  
         [0033]     It is known in the art that the peak-to-peak amplitude of the common mode voltage generated by active front-end variable frequency drive system can be limited to no more than 1.33V dc , as seen in  FIG. 3 , by synchronizing the switching sequence. This is not easy to accomplish when the switching frequency of the boost rectifier and inverter are different.  
         [0034]     The proposed common mode voltage reduction methods in this disclosure are operational without calculating direct digital SVPWM dwell times of the inverter sectors SW 1 -SW 6 . The invention can be applied to the active converter and inverter modulators, to reduce the common mode voltage (CMV) produced by a diode front-end variable frequency drive system or active front-end system.  
         [0035]      FIG. 6  shows a routine in the program  17  stored in a memory in the controller  10  for modifying the three-phase reference voltages applied to the motor and then modifying the gating signals G 1 , G 3 , G 5  that control the turning on of the inverter switches SW 1 -SW 6  in the three legs of the inverter  14 . When speaking about turning on switches SW 1 , SW 3 , SW 5 , it is understood, that if one switch SW 1  in one leg of the inverter  14  is conducting, then the other switch SW 2  in that leg of the inverter  14  is normally not conducting.  
         [0036]     In the routine in  FIG. 6 , the blocks represent groups of program instructions. As represented by the initialization block  60  in  FIG. 6 , G is set to a “1” if Tri&lt;the V u,v,w     —     ref  and to a “0” if Tri&gt;the V u,v,w     —     ref . Next, the maximum and minimum reference phase voltages are determined by comparing the phase voltages to each other as represented by process block  61 . Next, two of the phase reference voltages corresponding to the maximum and minimum voltage are inverted as represented by process block  62 . Then, the phase voltages are modulated by the carrier wave as represented by process block  63 . Next, the gating signals corresponding to the maximum and minimum phase reference voltages are set to be modified (inverted) as represented by process block  64 . The routine then loops back to process block  61  to repeatedly determine the maximum, minimum and middle phase voltages for six cycles of the triangular carrier wave corresponding to the six sectors, S 1 -S 6  of the SVPWM diagram.  
         [0037]      FIG. 7  shows a preferred embodiment of control program routine  17  operating with logic circuitry  20   a  for implementing the common mode voltage reduction. Referring in more detail to  FIG. 7 , which is a PWM modulating logic circuit  20   a , a reference phase voltage V u     —     ref  is an input at terminal  21  and is fed to one input on a selector circuit  28 . This reference phase voltage V u     —     ref  is inverted preferably in program routine  17  ( FIG. 1 ) or by an inverter  24  in logic circuit  20   a , and it becomes a second input to a selector circuit  28 . The selector circuit  28  is controlled at the middle input by a logic signal representing a determination that this phase represents a maximum phase voltage or a minimum phase voltage, or is a middle phase voltage from among the three phase voltages. This logic signal is output of the control program  17  and is received at input  30 .  
         [0038]     The phase voltage, V u     —     ref , either inverted or non-inverted, is fed to a comparator  25  to be compared with a triangular wave carrier, Tri, received from the input  24  by the comparator  25 . The resulting modulated phase output voltage is then used at selector circuit  26  to select between a logic high gating signal =1 for the upper switch SW 1  or a logic low gating signal =0 for the upper switch SW 1 . The selector circuit  26  produces a gating signal at its output that is inverted by a “NOT” operator  29  and is also fed as a non-inverted signal to a final selector circuit  27  to produce a gating signal G 1  for controlling V u     —     ref ′. The selector circuit  27  is controlled by the logic signal from input  30  representing a determination that this phase represents a maximum phase voltage, a minimum phase voltage or a middle phase voltage from among the three phase voltages. A circuit similar to  FIG. 7  is present to process each one of the three phase voltages, V u     —     ref , V v     —     ref , V w     —     ref .  
         [0039]      FIG. 8  illustrates the results of the carrying out the process in  FIG. 7 , in which at least one of the gate pulses from phases U, V, W, is always an opposite state from the other two gate signals. Thus the first logic low phase U pulse is opposite a high pulse for the phase V gate signal and a high pulse for the phase W gate signal.  
         [0040]      FIG. 9  illustrates a second program routine in which the blocks  90 - 93  represent one or more program instructions executed by the CPU  16  in the controller  10 . In this routine, an Event Manager sets up flag values in registers of the CPU to control the gating signals depending on the relative magnitudes of the reference voltages in relation to the carrier wave. As represented by the initialization block  90  in  FIG. 9 , G is set to a “1” if Tri&gt;the V u,v,w     —     ref  and to a “0” if Tri&lt;the V u,v,w     —     ref . Next, the maximum and minimum reference phase voltages are determined as represented by process block  91 . Next, the maximum and minimum reference signals are exchanged for one another and inverted as indicated by example in block  92 . Then, the gating signal for maximum phase voltage and the gating signal for the minimum phase voltage are inverted as indicated in process block  93 . The routine then loops back to process block  91  to repeatedly sense the phase voltages for six cycles of the triangular carrier wave corresponding to the six sectors, S 1 -S 6  of the SVPWM diagram.  
         [0041]      FIGS. 10-15  show in detail a switching pattern controlled by the invention through the six sectors S 1 -S 6  of the space vector diagram in  FIG. 2 .  
         [0042]     In  FIGS. 10-15 , the high or “1” state represents a gate “on” command signal, while the low or “0” state represents a gate “off” command signal. The actual “on” or “off” times are not timed. In these diagrams, the identity of which of the three phase reference voltages V u     —     ref ,V v     —     ref ,V w     —     ref  is the minimum, maximum and mid-value of the three reference voltages determines switching pattern, which in turn determines which sectors in the space vector diagram are entered. The methodology changes the “1” state representing a gate “on” command signal to the low or “0” state or gate “off” command signal for the maximum and minimum reference voltage phases. The gating signal for the mid-level phase voltage is retained at the logic high or “1” state. This prevents switches SW 1 , SW 3  and SW 5  from being switched high or “on” at the same time. By using this method, the peak-to-peak amplitude of the common mode voltage can be reduced.  
         [0043]     In the first switching sequence shown in  FIG. 10 , the triangular carrier wave, Tri, is shown as it intersects the three reference voltages on the first three axes, for which it is assumed that V u     —     ref &gt;V v     —     ref &gt;V w     —     ref . These signals may be sinusoidal signals varying 120 degrees in phase, but at the frequency of the carrier wave (typically 2 Khz-16 Khz) it is assumed that their relative magnitudes can be represented as shown. When their relative magnitudes (maximum, mid-level, minimum) change, the system enters the next switching sequence in one of  FIGS. 10-15 . The next three axes in  FIG. 9  show the conventional gating signals, G 1 , G 3 , G 5  for switches SW 1 , SW 3 , SW 5 . Gating signal G 1  has the longest “on time” because V u     —     ref  exceeds Tri for the greatest interval. Gating signal G 5  has the shortest “on time” because V w     —     ref  exceeds Tri for the shortest interval. The bottom three axes in  FIG. 10  show that the gating signals can be changed so that G 1 ′=1 if V w     —     ref &lt;Tri; G 3 ′=G 3  and G 5 ′=1 if V u     —     ref &lt;Tri. G 1 ′ becomes the inverse of G 5  and G 5 ′ becomes the inverse of G 1 , while G 3 ′ remains the same as G 3 . The bottom axis shows the vector states traversed during the switching sequence in  FIG. 7 . For signals G 1 , G 3 , G 5 , the vectors produced would be V 0 , V 1 , V 2 , V 7 , V 2 , V 1  and V 0 . By performing the change to gating signals G 1 ′, G 3 ′ G 5 ′, the vectors produced are V 6 , V 1 , V 2 , V 3 , V 2 , V 1  and V 6 . It should be noticed that the operation is basically in Sector S 1  going from vector V 1  to vector V 2  and back, but substituting the V 6  and V 3  vectors for the zero-voltage vectors, V 0  and V 7 . This reduces the common mode voltage.  
         [0044]     In the second sector, S 2 , the triangular carrier wave, Tri, is shown in  FIG. 11  as it intersects the three reference voltages on the first three axes, for which it is assumed that V v     —     ref &gt;V u     —     ref &gt;V w     —     ref . The next three axes in  FIG. 11  show the conventional gating signals, G 1 , G 3 , G 5  for switches SW 1 , SW 3 , SW 5 . Gating signal G 3  has the longest “on time” because V v     —     ref  exceeds Tri for the greatest interval. Gating signal G 5  has the shortest “on time” because V w     —     ref  exceeds Tri for the shortest interval. The bottom three axes in  FIG. 11  show that the gating signals can be changed so that G 1 ′=1 if V u     —     ref &gt;Tri; G 3 ′=0, when V w     —     ref &gt;Tri and and G 5 ′=0 if V v     —     ref &gt;Tri. G 3 ′ becomes the inverse of G 5  and G 5 ′ becomes the inverse of G 3 , while G 1 ′ remains the same as G 1 . For signals G 1 , G 3 , G 5 , the vectors produced would be V 0 , V 3 , V 2 , V 7 , V 2 , V 3  and V 0 . By performing the change to gating signals G 1 ′, G 3 ′ G 5 ′, the vectors produced are V 4 , V 3 , V 2 , V 1 , V 2 , V 3  and V 4 . It should be noticed that the operation is in Sector S 2  going from vector V 3  to V 2  and back, but substituting the V 4  and V 1  vectors for the zero-state vectors, V 0  and V 7 . This reduces the common mode voltage.  
         [0045]     For the third sector of the space vector diagram, S 3  in  FIG. 2 , the triangular carrier wave, Tri, is shown in  FIG. 12 , as it intersects the three reference voltages on the first three axes, for which it is assumed that V v     —     ref &gt;V w     —     ref &gt;V u     —     ref . The next three axes in  FIG. 11  show the conventional gating signals, G 1 , G 3 , G 5  for switches SW 1 , SW 3 , SW 5 . Gating signal G 3  has the longest “on time” because V v     —     ref  exceeds Tri for the greatest interval. Gating signal G 1  has the shortest “on time” because V u     —     ref  exceeds Tri for the shortest interval. The bottom three axes in  FIG. 12  show that the gating signals can be changed so that G 1 ′=1 if V v     —     ref &lt;Tri; G 3 ′=0 if V u     —     ref &gt;Tri and G 5 ′=G 5 . G 1 ′ becomes the inverse of G 3  and G 3 ′ becomes the inverse of G 1 , while G 5 ′ remains the same as G 5 .  
         [0046]      FIGS. 13-15  show the fourth through sixth sectors, S 4 -S 6  of the space vector diagram seen in  FIG. 2 . In each of these sectors, one of the two gating signals G 1 ′, G 3 ′, G 5 ′ remains the same as its counterpart G 1 , G 3 , G 5 , while the other two are inverted.  
         [0047]     Referring next to  FIG. 16 , the CPU  16  in the controller  10  can more particularly be a digital signal processor  16   a , which generates gating trigger pulse signals G 1 , G 3 , G 5  and sector logic signals S 0 , S 1 , S 2  (three logical bits) to a pre-programmed read-only logic device  20   b . The zero switching states can be avoided by changing the original trigger pulses G 1 , G 3  and G 5  to the modified trigger pulses G 1 ′, G 3 ′ and G 5 ′ by using the following logic equations 5), 6) and 7), where S 2 , S 1  and S 0  indicates three bits designating the identity of the sector S 1 -S 6 . The programmed logic device operates according to the following logic equations in mapping original trigger pulses G 1 , G 3  and G 5  and sector signals S 2 , S 1  and S 0  to modified trigger pulses G 1 ′, G 3 ′ and G 5 .  
                     G   1   ′     =       ⁢         G   1     ⁢       G   3     _       +       G   1     ⁢     G   3     ⁢       G   5     _       +         G   1     _     ⁢       G   3     _     ⁢       G   5     _                         ⁢       (           S   2     _     ⁢       S   1     _     ⁢     S   0       +         S   2     _     ⁢     S   1     ⁢     S   0       +       S   2     ⁢       S   1     _     ⁢       S   0     _       +       S   2     ⁢     S   1     ⁢       S   0     _         )     +                     ⁢       G   1     ⁢     G   3     ⁢       G   5     ⁡     (           S   2     _     ⁢     S   1     ⁢       S   0     _       +       S   2     ⁢       S   1     _     ⁢     S   0         )                       5   )                       G   3   ′     =       ⁢           G   1     _     ⁢     G   3       +       G   1     ⁢     G   3     ⁢       G   5     _       +         G   1     _     ⁢       G   3     _     ⁢       G   5     _                         ⁢       (           S   2     _     ⁢     S   1       +       S   2     ⁢       S   1     _     ⁢     S   0       +       S   2     ⁢     S   1     ⁢       S   0     _         )     +                     ⁢       G   1     ⁢     G   3     ⁢       G   5     ⁡     (           S   2     _     ⁢       S   1     _     ⁢     S   0       +       S   2     ⁢       S   1     _     ⁢       S   0     _         )                       6   )                       G   5   ′     =       ⁢           G   1     _     ⁢       G   3     _     ⁢     G   5       +         G   1     _     ⁢     G   3     ⁢     G   5       +       G   1     ⁢       G   3     _     ⁢     G   5       +         G   1     _     ⁢       G   3     _     ⁢       G   5     _                         ⁢       (           S   2     _     ⁢       S   1     _     ⁢     S   0       +         S   2     _     ⁢     S   1     ⁢       S   0     _       +       S   2     ⁢       S   1     _         )     +                     ⁢       G   1     ⁢     G   3     ⁢       G   5     ⁡     (           S   2     _     ⁢     S   1     ⁢     S   0       +       S   2     ⁢     S   1     ⁢       S   0     _         )                       7   )             
 
         [0048]      FIGS. 16-18  are logic tables for generating the modified trigger pulses G 1 ′, G 3 ′ and G 5 ′, respectively, as a function of the six sectors, S 1 -S 6  of the SVPWM diagram in  FIG. 2 . By using this method, zero-voltage vectors V 0  and V 7  can be avoided and the peak-to-peak amplitude of the common mode voltage can be reduced. This logic produces the same sets of signals seen in  FIGS. 10-15  for the six sectors S 1 -S 6  of the SVPWM diagram of  FIG. 2 .  
         [0049]     This has been a description of several preferred embodiments of the invention. It will be apparent that various modifications and details can be varied without departing from the scope and spirit of the invention, and these are intended to come within the scope of the following claims.