Abstract:
Driving methods for display panels are provided, in which a K th  row of pixels in a pixel array is driven during a first period, and a K+1 th  row of pixels in the pixel array is driven during a second period. A control clock applied for a charge pump is toggled at least N times during a third period between the first and second periods, and the control clock is maintained at a fixed logic level during the first and second periods, in which N≧2.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a display system, and in particular to a display system capable of preventing banks (non-uniform color), water waves and high frequency noise. 
     2. Description of the Related Art 
     Liquid crystal displays (LCDs) are used in a variety of applications, including calculators, watches, color televisions, computer monitors, and many other electronic devices. Active-matrix LCDs are a well known type of LCD. In a conventional active matrix LCD, each picture element (or pixel) is addressed using a matrix of thin film transistors (TFTs) and one or more capacitors. The pixels are arranged and wired in an array having a plurality of rows and columns. 
     To address a particular pixel, the switching TFTs of a specific row are switched “on” (i.e., charged with a voltage), and data voltage is sent to the corresponding column. Since other intersecting rows are turned off, only the capacitor at the specific pixel receives the data voltage charge. In response to the applied voltage, the liquid crystal cell of the pixel changes its polarization, and thus, the amount of light reflected from or passing through the pixel changes. In liquid crystal cells of a pixel, the magnitude of the applied voltage determines the amount of light reflected from or passing through the pixel. 
     Generally, boosting devices are required for LCDs in order to provide a higher voltage to drive display panels therein. Most commonly, a charge pump is used and voltages generated thereby control the magnitude of the respective gate line signal applied to each of gate line, the magnitude of the Vcom signal applied to the common electrode (COM), and the Gammar circuit to generate different gray values. Thus, a charge pump providing stable high voltage is important for high display quality. 
     BRIEF SUMMARY OF THE INVENTION 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     Embodiments of a driving method for display panels are provided, in which a K th  row of pixels in a pixel array is driven during a first period, and a K+1 th  row of pixels in the pixel array is driven during a second period. A control clock applied for a charge pump is toggled at least N times during a third period between the first and second periods, and the control clock is maintained at a fixed logic level during the first and second periods, in which N≧2. 
     The invention provides an embodiment of a driving method for display panels, in which a plurality rows of pixels in a pixel array is driven in sequence, a control clock applied for a charge pump is maintained to a fixed logic level when any of the rows of pixels is driven, and the control clock is toggled at least N times during every blank period when none of the rows of pixels is driven, in which N≧2. 
     The invention also provides an embodiment of a display system for a panel displaying images. In the display panel, a pixel array comprises a plurality of pixels in a matrix, a plurality of scan lines and a plurality of data lines, a data driver coupled to the data lines, a scan driver coupled to the scan lines, and wherein the data driver and the scan driver drive rows of pixels in the pixel array in sequence. A voltage controller comprises at least one charge pump to generate at least one DC voltage applied to the data driver and the scan driver. A clock generator generates a control clock applied to the charge pump to generate the DC voltage accordingly and maintains the control clock at a fixed logic level when any of the rows of pixels is driven, and toggles the control clock at least N times during every blank period when none of the rows of pixels is driven, in which N≧2. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  shows an embodiment of a display panel; 
         FIG. 2A  shows a timing chart of a display panel; 
         FIG. 2B  shows another timing chart of a display panel; 
         FIG. 2C  shows another timing chart of a display panel; 
         FIG. 2D  shows another timing chart of a display panel; 
         FIG. 2E  shows another timing chart of a display panel; 
         FIG. 3  shows another embodiment of a display panel; 
         FIG. 4  shows an embodiment of a charge pump; and 
         FIG. 5  shows an embodiment of a display system. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
       FIG. 1  shows an embodiment of a display panel. As shown, display panel  100  comprises a pixel array  102 , a timing controller  108 , a clock generator  110 , a voltage controller  112 , a data driver  114 , a scan driver  116  and a common voltage (Vcom) generator  118 . 
     The pixel array  102  comprises a plurality of pixels arranged in a matrix (not shown), a plurality of scan lines G 1 ˜Gn, and a plurality of data lines D 1 ˜Dm, wherein the pixels are driven by the data driver  114  and the scan driver  116 . 
     The timing controller  108  generates synchronized image data S_DATA to the data driver  114  according to image data VIDEO_DATA, a system control clock DOTCLK and a synchronization signal (H_SYNC and V_SYNC) from a graphic processor or a data processor, controlling timing of data signals generated by the data driver  114  and applied to data lines D 1 ˜Dm of the pixel array  102 . 
     Similarly, the timing controller  108  generates scan signals SG to the scan driver  116  according to the system control clock DOTCLK and the synchronization signal (H_SYNC and V_SYNC) from the graphic processor or the data processor, controlling timing of scan signals generated by the scan driver  116  and applied to scan lines G 1 ˜Gn of the pixel array  102 . Further, the timing controller  108  generates an initial common voltage SCOM to the Vcom generator  118  according to the system control clock DOTCLK from the graphic processor, controlling timing of a common voltage (Vcom) signal generated from the Vcom generator  118  and applied to a common electrode (not shown) of the pixel array  102 . 
     The voltage controller  112  comprises at least one charge pump  104  to generate at least one direct current (DC) voltage. A typical charge pump used in a display panel generates a DC voltage, such as DCV 1 , DCV 2  or DCV 3 ) a multiple of a reference voltage (Vref) when pumped by a control clock signal (DCCLK). Examples of such charge pumps are disclosed in U.S. Patent Applicant Publication No. U.S. 2002/0044118 and U.S. Patent Applicant Publication No. U.S. 2003/0011586. 
     For example, the DC voltage DC 1  can be generated by the voltage controller  112  for the data driver  114  to control the magnitude of the respective data line signal applied to each of the data lines D 1 ˜Dm. Similarly, the DC voltage DC 2  is generated by the voltage controller  112  for the scan driver  116  to control the magnitude of the respective scan line signal applied to each of the scan lines G 1 ˜Gn. Further, the DC voltage DC 3  is generated by the voltage controller  112  for the Vcom generator  118  to control the magnitude of the common voltage Vcom applied to the common electrode of the pixel array  102 . 
     The clock generator  110  generates at least one control clock DCCLK to control at least one charge pump  104  (shown in  FIG. 4 ) in the voltage controller  112 , such that the DC voltage DCV 1 , DCV 2  and DCV 3  are generated. 
       FIG. 2A  shows a timing chart of the display panel, presenting the relationship between the display wave PAW and the control clock DCCLK applied to the charge pump in the voltage controller  112 . As shown, display periods DP_N, DP_N+1, DP_N+2 and DP_N+3 and blank periods BK 1 , BK 2 , BK 3  and BK 4  appear alternately. In the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3, the data driver  114  and the scan driver  116  drive N th  to N+4 th  rows of pixels in the pixel array  102  in sequence. 
     To generate required DC voltage, such as DC 1 , DC 2  or DC 3 , by the charge pump in the voltage controller  112 , the control clock DCCLK toggles several times, i.e., the voltage level of the clock DCCLK goes low from high or vice versa. However, because the control clock DCCLK is toggled during the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3, non-uniform color (banks) or water waves can occur in the images. This is because the output voltage on the data lines of the data driver  114  is unstable during the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3 but the control clock DCCLK is toggled at these time intervals. 
       FIG. 2B  shows another timing chart of the display panel. In this embodiment, because the control clock DCCLK is not toggled in the display periods DP_N, DP_N+1, DP_N+2 or DP_N+3 but in the blank periods BK 1 , BK 2 , BK 3  and BK 4 , non-uniform color (banks) or water waves are prevented. However, because frequency of the control clock DCCLK is too low, the DC conversion efficiency of the current in the charge pump of the voltage controller  112  is poor and noticeable noise is generated. 
     In view of this, the invention further provides another display driving method.  FIG. 2C  shows another timing chart of the display panel, presenting the relationship between the display wave PAW and the control clock DCCLK applied to the charge pump in the voltage controller  112 . As shown, display periods DP_N, DP_N+1, DP_N+2 and DP_N+3 and blank periods BK 1 , BK 2 , BK 3  and BK 4  appear alternately. 
     In the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3, the data driver  114  and the scan driver  116  drive N th  to N+4 th  rows of pixels in the pixel array  102  in sequence. For example, during the display period DP_N, the scan driver  116  scan the N th  scan line, such as G 2 , according to the scan control signal SG from the timing controller  108  and the data driver  114  provide corresponding data on the data lines D 1 ˜Dm of the pixel array  102  according to the synchronized image data S_DATA from the timing controller  108 . Namely, the N th  row of pixels in the pixel array  102  are driven. Similarly, the N+1 th  to N+3 th  rows of pixels in the pixel array  102  are driven in sequence during the display periods DP_N+1, DP_N+2 and DP_N+3, and operations of those are similar to that of the N th  row of pixels and thus, are omitted for simplification. During the blank periods BK 1 ˜BK 4 , all scan lines G 1 ˜Gn are not activated (scanned), i.e., the image data of the pixels are not updated in these time intervals. 
     In this embodiment, the clock generator  110  quickly toggles the control clock DCCLK only during the blank periods BK 1 , BK 2 , BK 3  and BK 4  and maintains the control clock DCCLK at a logic high without being toggled during the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3. Thus, not only are non-uniform color (banks) or water waves prevented but also poor DC conversion efficiency and noticeable noise. 
       FIG. 2D  shows another timing chart of the display panel. Similarly, the clock generator  110  quickly toggles the control clock DCCLK only during the blank periods BK 1 , BK 2 , BK 3  and BK 4  and does not toggle during the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3. In this embodiment, during the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3, the control clock DCCLK is maintained at a low logic level rather than a high logic level as shown in  FIG. 2C . 
       FIG. 2E  shows another timing chart of the display panel. Similarly, the clock generator  110  does not toggle the control clock DCCLK during the display periods DP_N, DP_N+1, DP_N+2 and DP_N+3. The clock generator  110  toggles the control clock DCCLK twice during the blank periods BK 1 , BK 2 , BK 3  and BK 4  and maintains the control clock DCCLK at a high logic level. It should be noted that frequency of the control clock preferably exceeds 20 KHz, such that noticeable noise can be prevented. 
       FIG. 3  shows another embodiment of display panel in a display system. As shown, the display panel  100 ″ is similar to the panel  100  in  FIG. 1 , differing only in that the control clock DCCLK for the charge pump in the voltage controller  112  is generated by the timing controller  108  directly rather an additional clock generator (as shown in  FIG. 1 ). 
       FIG. 4  shows an embodiment of charge pump. As shown, the charge pump  104  comprises a plurality of MOS transistors M 1 ˜MN connected in series and capacitors C 1 ˜CN−1. For example, the transistor M 1  can comprise a first terminal coupled to the reference voltage Vref from the timing controller  108 , a second terminal coupled to a capacitor C 1  and a control terminal coupled to the first terminal thereof. The transistor M 2  comprises a first terminal coupled to the second terminal of the transistor M 1 , a second terminal coupled to a capacitor C 2  and a control terminal coupled to the first terminal thereof, and so on. However, the transistor MN comprises a first terminal coupled to the second terminal of the previous transistor, a second terminal serving as an output terminal and a control terminal coupled to the first terminal thereof. Further, the odd-numbered capacitors, such as C 1 , C 3 , . . . , are coupled to the control clock DCCLK from the clock generator  110  or the timing controller  108  and the even-numbered capacitors, such as C 2 , C 4 , . . . , are coupled to an inversion signal of the control clock DCCLK. By toggling the control clock DCCLK, the charge pump  104  can boost the reference voltage Vref to a desired DC voltage, such as DCV 1 , DCV 2  or DCV 3 , for output to the data driver  114 , the scan driver  116  and the Vcom generator  118 . The charge pump  104  shown in  FIG. 4  is an example and the disclosure is not limited thereto, with examples of such charge pumps disclosed in U.S. Patent Applicant Publication No. U.S. 2002/0044118 and U.S. Patent Applicant Publication No. U.S. 2003/0011586. 
       FIG. 5  shows an embodiment of a display system implemented in an electronic device. As shown, the electronic device  500  comprises a display panel, such as the display panel  100  or  100 ″ and an input unit  510  coupled to the display panel  100 / 100 ″ for providing input signals such that to the display panel  100 / 100 ″ displays images. For example, the display panel  100 / 100 ″ can be a liquid crystal display panel, an original light emitting display panel, field emission display panel or a plasma display panel, but is not limited thereto. The electronic device can be a digital camera, a portable DVD, a television, a car display, a PDA, a display monitor, a notebook computer, a tablet computer, or a cellular phone. 
     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.