Abstract:
A MOSFET gate electrode is interrupted from extending across a common conduction region, thereby reducing gate capacitance. The reduced gate capacitance provides very low gate-to-drain charge, Q GD , and very low gate-to-source charge, Q GS . The gate electrode is supported by and is in effect or is actually interrupted by an oxide block over a common conduction area. The MOSFET can be formed by methods including: patterning oxide blocks on a substrate; providing gate electrode material in and over appropriate gaps between the oxide blocks; removing excess gate material; and forming oxide layers around the gate electrode material. Oxide blocks can alternately be patterned to permit gate electrodes to be formed directly between the oxide blocks. The reduced gate capacitance reduces switching delays while permitting minimum R DSON  values.

Description:
RELATED CASES 
     This application is based upon and claims benefit of Provisional Application No. 60/279,800 filed Mar. 28, 2001, to which a claim of priority is hereby made. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to semiconductor devices and more specifically relates to a MOSFET having an ultra low gate to drain and gate to source capacitance and thus ultra low charges Q GD  and Q GS . 
     BACKGROUND OF THE INVENTION 
     Very high speed power MOSFETs preferably have a minimized product of Q G  and R DSON . To accomplish this minimal value, the value of the gate to drain capacitance should be minimized. Further, it is desired to have good immunity against dv/dt conditions and, for this purpose, a small ratio of Q GD /Q GS  is desired, to produce good Cdv/dt immunity. It is also desired to provide a minimum R DSON  and a low gate poly resistance, and in the manufacturing process, a minimum number of mask steps. 
     BRIEF DESCRIPTION OF THE INVENTION 
     In accordance with the invention, a greatly thickened oxide is disposed above the common conduction region or accumulation region between spaced bases of a vertical conduction planar power MOSFET having a cellular or striped base configuration. By increasing the spacing between the polysilicon gate and the drain surfaces over a substantial portion of their facing areas, the capacitance between the gate to the drain is substantially reduced. The ratio of Q GD /Q GS  is also substantially reduced, producing excellent Cdv/dt immunity. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a cross-sectional view of a small portion of a planar vertical conduction power MOSFET of the prior art. 
     FIG. 2 shows a first embodiment of the present invention in which a thickened oxide is provided over the accumulation region of the structure of FIG.  1  and is an ultra low Q GD  self-aligned SAC (Self Aligned Contact) MOSFET. 
     FIG. 3 is a cross-section of a low Q GD  SAC MOSFET like that of FIG.  2 . 
     FIG. 4 is a cross-section of a further embodiment of this invention employing a dual spacer design of a polysilicon spacer and an insulation SAC spacer. 
     FIGS. 5 to  14  show the process steps for the manufacture of a dual spacer SAC MOSFET. 
     FIGS. 15A to  15 C show a still further process flow in accordance with the invention. 
     FIGS. 16A to  16 D show a still further process flow, employing gap fill for a dual poly spacer MOSFET. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring first to FIG. 1, there is shown a cross-section of a few cells (or stripes) of a conventional vertical conduction power MOSFET (that is, a MOSFET in which the current flows vertically across at least a portion of a chip or die, usually to a bottom drain electrode). The numerals used in the following are duplicated in the drawings to identify similar parts. 
     The well-known device usually employs a silicon substrate  30  having a junction-receiving epitaxially deposited layer  31 . Layers  30  and  31  are of the N +  and N −  concentration types, for an N channel device. All concentration types can be reversed for a P channel device. The typical device will usually have a plurality of spaced P bases (or channel regions)  32  which each receive an N +  shallow source region  33  to define invertible P channel regions between the end boundaries of the N +  source and P base. The spaced P channel regions  32  may be connected at the portions of their extent, such as at the ends of P type base stripes. 
     A thin gate oxide  34  overlies the invertible P channels and the top of the N −  accumulation regions (or “common conduction” regions)  35 . A conductive polyox layer  36  overlies the gate oxide layers  34  and is insulated by a polysilicon layer  37  and by oxide SAC spacers  38  from a top (source) metal contact  39  which may be aluminum or some other suitable top metal. Usually, the edge of the polysilicon elements (or lattice, if a cellular geometry is used) define the diffusion windows for bases  32  and sources  33 . Spacers  38  define a self-aligned window for the etching of shallow trenches  40  through sources  33  and into bases  32 . Trenches  40  are filled with conductive metal during the formation of top contact  39 , which makes contact with both sources  33  and bases  32 . 
     The gate to drain capacitance of the device of FIG. 1 is related to the area of poly gate segments  36  over the drain and to the thickness of thin oxide  34 , which may be in the range of about 500 Å to 1000 Å. This capacitance defines the gate charge Q GD  which, for MOSFETs in certain applications, should be as small as possible. 
     The present invention provides a novel structure for drastically reducing the charge Q GD . Thus, as shown in FIG. 2, a greatly thickened oxide mass or block  50  is formed over a substantial portion of the width of common conduction region  35 . For example, oxide block  50  can have a height of about 0.5 micron, which is drastically larger than the thickness of gate oxide  34  (less than 1000 Å). The width of spacer oxide block  50  covers at least more than one-half of the width of regions  35 , and preferably as great as possible a portion of their width without interference with the processing tolerance of the wafer processing equipment. 
     It can be seen in FIG. 2 that the oxide blocks  50  elevate the conductive polysilicon layers  36  away from the surface of the silicon, and also reduce the area of the polysilicon which overlies the surface of regions  35 . The conductive polysilicon layers  36  form gate electrodes that interact with opposing invertible channels with which the electrodes are paired. The gate electrodes do not interact with the common conduction areas between the base regions because of the separation caused by the oxide blocks  50 . Thus, the gate to drain capacitance is greatly reduced, thereby reducing Q GD . 
     A number of novel process sequences may be used to form the thickened oxide spacers  50 , as will be described. Further, polysilicon spacers  51  can be employed on the sides of oxide blocks  50  as shown in FIG. 3, and a dual block structure using both the oxide block  50  and a SAC oxide block  38  can be employed as shown in FIG.  4 . 
     The device shown in FIG. 4 has a number of benefits over the prior art structure of FIG.  1 . Thus, the device has: 
     A near zero Q GD . 
     A lower Q GS  (gate to source charge). 
     The ratio of Q GD /Q GS  is very small, producing excellent Cdv/dt immunity. 
     Ultra low R DSON  through the use of shallow channel junctions (for example, 0.5 to 0.6 μm compared to the presently used 0.9 μm) and a smaller cell pitch. 
     A low R G  (gate resistance) if an optional silicide on the polysilicon is employed. 
     No added mask steps are needed. 
     FIGS. 5 to  14  show the main process steps used to manufacture the dual spacer structure of FIG.  4 . The initial step, shown in FIG. 5, is the growth or deposition of a thick oxide block  50  on the upper surface of epitaxially deposited layer  31 . Oxide  50  may be 0.5 micron thick, as an example. The oxide layer  50  is then patterned and etched, leaving spaced oxide blocks  50 , shown in FIG. 5, and a thin gate oxide layer  34  is grown on the silicon surface exposed between spaced oxide blocks  50 . 
     Thereafter, and as shown in FIG. 6, a layer  36  of polysilicon is deposited atop the surface of FIG. 5 and a POCl deposition and diffusion is carried out to make the polysilicon N type, and conductive. The top surface is then deglassed and, as shown in FIG. 7, the polysilicon is patterned and etched to define separated spacers  51  on the sides of oxide blocks  50 . The gate pad and gate bus poly (not shown) is protected during this etch, which may be a wet or a dry etch. 
     It should be noted that the polysilicon  36  may be processed using a CMP process (chemical mechanical polishing) to define spacers  51  in FIG.  7 . 
     Suitable implants and diffusions are then carried out to define a conventional double diffused shallow base or channel regions  32  and self-aligned source regions  33 . A thin oxide layer  60  (source oxide) grows over polysilicon spacers  51  at this time. 
     As next shown in FIG. 8, a thin oxidation blocking layer  70 , which may be a nitride, is deposited atop the die surface and over oxide layer  60 . The gap above the central portion of sources  33  is then filled with an etch protectant, such as a photoresist  75  (FIG. 9) and the upper surface receives a short etch to remove excess photoresist. 
     Thereafter, and as shown in FIG. 10, the exposed upper layer of nitride  70  is etched and photoresist  75  is stripped off. A polyoxide  37  is then grown atop poly spacers  51 . The remaining nitride film  70  (or the like) is then stripped off as shown in FIG.  11 . 
     As an option, and if the resistance R G  of the gate is to be further reduced, polysilicide layers  80  may be formed on poly spacers  51  as shown in FIG.  12 . In this process, the gap between adjacent spacers  51  is partially filled with an etch protectant, for example, a photoresist, to cover the horizontal oxide surface, but having most of the vertical side walls of spacers  51  unprotected. A short oxide etch is then carried out to remove oxide  60  layer on the side walls of poly spacers  51  and the photoresist is stripped. Polysilicide layer  80 , for example, of WSi or the like, is then formed on the bare side walls of spacers  51 . 
     Thereafter, and as shown in FIG. 13, the self-aligned contact process is carried out, in which a conformal oxide layer is deposited atop the die surface and is patterned and etched by a planar oxide etch-back step to leave oxide spacers  38  in place. A silicon trench etch is then carried out to form trenches  40 . 
     As next shown in FIG. 14, the device top surface is patterned and etched to form a polygate contact and the photoresist is again removed. A short oxide etch is then carried out and a metal contact  39  such as aluminum is then deposited atop the wafer. Contact  39  is then appropriately patterned as desired. 
     The completed device of FIG. 14 will have an extraordinary low Q GD  due to the presence of oxide block  50  and the reduced width of polysilicon over the accumulation region  35 . 
     FIGS. 15A to  15 C show a modified process flow in which poly spacers  51  are formed by protecting the poly “valleys” with an oxidation blocking film such as SiN 3 , and then etching the poly and oxidizing and thereby consuming the etched poly. Thus, FIG. 15A shows the silicon in the stage of manufacture of FIG. 6. A layer of silicon nitride  90 , or the like (FIG. 15B) is formed over the upper surface. The gaps are filled with a protectant such as a photoresist and the nitride which is exposed is etched and the resist is stripped as shown in FIG.  15 B. The exposed polysilicon mesas are then etched to the level of oxide block  50  and polyoxide layers  37  are grown atop the etched surface of the polysilicon  36 / 51 . Nitride  90  is then stripped and the polysilicon is etched and the process is completed as shown in FIGS. 8 to  14 . 
     FIGS. 16A to  16 D show a still further modified process flow in which the starting thick oxide layer is originally patterned as shown in FIG. 16A to define dual poly gates and cells. A gate oxide  34  is then grown and polysilicon layer  36  is formed to fill the gaps between oxide blocks  50  as shown in FIG. 16B. A planar etch back or CMP step is then carried out to planarize the upper surface as shown in FIG.  16 C. 
     A non-critical alignment step is then carried out to protect oxide block  50  over the accumulation regions and etch the wider oxide block  50  as shown in FIG.  16 D. The processing then continues as shown in FIGS. 8 through 14. 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.