Abstract:
A two-term vector multiplier for calculating Ax+BY and useful in FFT and digital filter circuits is disclosed. The variables A and B are converted into standard type-minimal representation codes which are then operated upon to generate selection signals and an addition-subtraction control signal. The selection signals select one of four values, X, Y, Y/2 and O, to be sent to an accumulator where the selected value is either added to or subtracted from one half the value presently in the accumulator to provide a new accumulator value. The final accumulation value is Z=AX+BY.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a two-term vector multiplier for the efficient calculation of AX+BY. 
     A two-term vector multiplication (referred to as two-term multiplication hereunder) is a basic operation for the realization of spectrum analyzers using FFT (Fast Fourier Transform) for digital signal processing as well as for the realization of communication systems using digital filters. 
     For, instance, the FFT involves complex operations including complex multiplications shown below, and the real part and the imaginary part of such complex multiplication are calculated by the two-term multiplication: ##EQU1## where S R , S I  and T r , T I  represent the real and imaginary parts of S and T, respectively. 
     In the digital filter, the following operation including the two-term multiplication is always accomplished. Stated in detail, in view of the stability of coefficients for giving the characteristics to the digital filter, such filter is generally composed of a combination of second-order filters whose operations are represented by the following pair of equations: ##EQU2## where X i  is the input data, y i  ; the output data; and w i , the internal state of a second-order filter all at the sampling time i; and α, β, γ and δ are coefficients of the second-order filter. The parenthesized parts in Equation (2) are two-term multiplications. 
     The two-term multiplications are thus basic operations in the field of the digital signal processing, and their efficient calculation greatly contributes to improving the performance of digital signal processors. 
     For details of an FFT and Digital filters, reference is made to &#34;Theory and Application of digital Signal Processing&#34;, by Lawrence R. Robiner et al, published by PRENTICE-HALL, Inc., 1975, pp. 356-437 and pp. 75-295, respectively. 
     To perform two-term multiplications using an FFT and/or digital filters on a real time basis, an arithmetic circuit with smaller power consumption and a high processing capability is needed. For this approach, a basic serial-parallel type-multiplier (referred to as basic multiplier) has been proposed in &#34;Digital Computer Design Fundamentals&#34;, by Yaohan Chu published by McGraw-Hill Book Company, Inc., 1962, pp. 24-35. The operation principle of the basic multiplier is summarized as follows: Variables X and A are computed to give a product Z in the following manner: ##EQU3## with symbol &#34;α&#34; indicating that a i  is an element of set {0,1}. Equation (3) can also be solved by computing the following recursive formula, where n is the total bit number of variable A and suffix i represents the i-th recursive operation and the i-th bit position of variable A: ##EQU4## 
     A more improved example of the basic serial-parallel multiplier is the pipeline multiplier described in U.S. Pat. No. 3,885,141. This multiplier is intended to reduce the computing time per multiplication basic on the fact that the part corresponding to the number of bits of the multiplier on the LSB (least significant bit) side in the multiplication result is not used. As a result, the multiplication speed is doubled as compared with the basic multiplier by starting the next multiplication, upon completion of the LSB side operation of a first multiplication, while the MSB (most significant bit) side operation of the first multiplication is not finished. This multiplier, however, requires not only a complicated control but also a complicated structure in which six flip-flops are needed per adder for processing of each bit as is evident from FIG. 5. 
     Another upgraded serial-parallel multiplier is illustrated in FIG. 7 of U.S. Pat. No. 3,777,130. This multiplier uses an ROM (read only memory) and a circuit having approximately the same function as the basic multiplier to compute A 1  x 1  +A 2  x 2 . . . A M  x M  in time equal to what the basic multiplier will take to accomplish a multiplication. This is due to the fact that the sum resulting from different combinations of coefficients A 1 , A 2 , . . . , A M  are calculated and stored in the ROM in advance. Accordingly, this multiplier using the ROM is useful only when the coefficients A 1 , A 2 , . . . , A M  are fixed, but not applicable to realize digital filters of different characteristics by the multiplex use of this multiplier on a time-sharing basis. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is therefore to provide a serial-parallel type-two-term vector multiplier free of the above-mentioned disadvantages and simplified to achieve the high speed multiplication of AX+BY. 
     The present multiplier for calculating AX+BY, comprises first and second minimal-representation generating circuits for separately converting first and second variables A and B, respectively, into standard type-minimal representation codes; a control circuit responsive to the minimal representation codes of said first and second variables for generating a selection signal and an addition-subtraction control signal; a selection circuit responsive to third and fourth variables X and Y, and said selection signal generated by said selection circuit for selecting one out of said third variable, said fourth variable, 1/2 of the value of said fourth variable and zero; and an acumulator connected to said selection circuit for executing in response to said addition-subtraction control signal given from said control circuit, addition and subtraction between 1/2 of the accumulated value and the output of said selection circuit to produce a new accumulated value. 
     The present invention enables the manufacture of a multiplier with the hardware scale similar to the conventional basic multiplier, with the processing capability comparable to the above-mentioned pipeline multiplier, and with the great flexibility compared with said ROM-use multiplier. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of one embodiment of this invention; 
     FIG. 2 illustrates the detail a part of the embodiment; 
     FIG. 3 illustrates in detail another part of the embodiment; 
     FIG. 4 illustrates in detail still another part of the embodiment; and 
     FIG. 5 illustrates in detail yet another part of the embodiment. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     A theoretical feature of this invention lies in that time-serial and time-parallel (referred to as serial and parallel, respectively hereunder) input variables are represented by A, B and X and Y, and tuples (f i ), (k i ) and (c i ) for developing the two-term multiplication are obtained as follows; ##EQU5## where n is the total bit number of each of variables A and B, i indicates the bit position, and bar &#34;-&#34; marked on symbols denotes their negation. Moreover, tuples (f i ), (k i ) and (c i ) have the following relationship: 
     
         .sub.i, f.sub.i, k.sub.i ε{0, 1} 
    
     
         .sub.1, c.sub.i ε{0, ±1}                       (6) 
    
     where   i  represents that i can have any value with the range of 0≦i≦n+1. 
     Though the method for determining the tuples (f i ), (k i ) and (c i ) will be explained later, the principle of this invention, is stated next, assuming that the development of Equation (5) has been achieved. Equation (5) can be computed by the following set of recursive formulas: ##EQU6## 
     R, can be further developed as follows according to the combinations of elements f i , k i  and c i  or tuples (f i ), (k i  9 and (c i ): ##EQU7## 
     The comparisons of Equations (8) and (4) clearly shows that the number of calculations needed for obtaining the value Z is almost the same, and that the only difference in that Equation (8) has a greater choice for the second term than Equation (4). 
     Next, the procedure for determining tuples F=(f i ), K=(K i ) and C=(c i ) will be described. In this procedure 
     (1) variables A and B are converted into standard type-minimal representation codes (a&#39; i ) and (b&#39; i ), respectively. 
     Such standard type-minimal representation (abbreviated to s-representation) is discussed in detail in the article entitled &#34;Arithmetic Norms and Bounds of the Arithmetic An Codes&#34; by Albert C. L. CHIANG published in &#34;IEEE Transactions on Information Theory&#34;, Vol. IT-16, No. 4, July 1970, pp. 470-476. 
     A brief explanation of the minimal representation (m-representation) will be made next. An m-representation is a sort of numerical expression in radix 2 system, each of whose digits is permitted to have one of three values, 0, +1 and -1, and which has the smallest possible number of non-zero digits. By this method, a given value can be represented by a number of different m-representation codes. For instance, decimal number 11 has an m-representation code (1011) because it can be represented as 1×2 3  +0×2 2  +1×2 1  +1×2 0 , and another code (1101) because it can also be represented as 1×2 3  +1×2 2  +0×2 1  +(-1)×2 0 , where 1 denotes -1. in either expression, the number of non-zero digits is three, which is the smallest among all the m-representation codes of decimal number 11. In this case, such m-representation codes may have the longer digit length by one digit than that of the ordinary binary expression code of the same value. 
     Among the number of possible m-representation codes of a given value, there is always one in which the product of every adjoining pair of digits is 0. For any value, there is only one m-representation code, which is called the s-representation code of a given value. To take decimal number 11, its s-representation code is (10101) because 11 can be represented as 1×2 4  +0×2 3  +(-1)×2 2  +0×2 1  +(-1)×2 0  and because the product of every adjoining pair of digits in (10101) is 0. 
     In this case, because of the nature of the s-representation (a&#39; i ) and (b&#39; i ) consist of n+1 tuples each, and the following equation is made. ##EQU8## 
     (2) A set of digits which makes neither (a&#39; i ) nor (b&#39; i ) zero is formed; i.e., the following equation is established: 
     
         H={i||a&#39;.sub.i |=|b&#39;.sub.i |=1}(10) 
    
     (3) Tuple P is formed on the basis of the following equation; 
     
         P=(p.sub.i |p.sub.i =b&#39;.sub.i -S.sub.H (i)b&#39;.sub.i) (11) 
    
     where S H  (i) is a characteristic function. ##EQU9## where symbol ε denotes not being an element of H. 
     In other words, tuple P is obtained from the replacement of elements in (b&#39; i ) having suffix i EH by 0. 
     (4) Tuple O is formed depending on the following equation: 
     
         Q=(q.sub.i |q.sub.i p.sub.i +S.sub.H (i-1) (b&#39;.sub.i-1) (13) 
    
     Thus, Q results from the replacement of elements in (b&#39; i+1 ) having suffix i E H by (b&#39; i ). 
     (5) Tuples C, F, and K are determined depending on the following equation: ##EQU10## 
     It will be demonstrated hereunder that tuples C, F, and K can be determined and the two-term vector product of Equation (5) can be computed by the procedure described above. 
     Two-term vector product Z can be represented by the following equation using s-representation codes (a&#39; i ) and (b&#39; i ), where s-representation codes (a&#39; 1 ) and (b&#39; i ) have the longer digit length by one digit than that of the ordinary binary expression codes (a i ) and (b i ) of variables A and B, respectively: ##EQU11## 
     If both element a&#39; i  (a&#39; i ) and element b&#39; i  of (b&#39; i ) for a given suffix i do not take non-zero at a time, that is, 
     
         H=φ (φ denotes null set)                           (16) 
    
     either X or Y but not both in Equation (15) will undergo addition so that this equation like Equation (5) can be computed with a single accumulator. However, since the condition of Equation (16) is not always established , (b&#39; i ) is replaced with tuple P of Equation (11). Consequently, variable B is made smaller by the amount indicated by the following equation: ##EQU12## To compensate for this decrement, tuple O of Equation (13) is used, and the following equation is derived from Equation (13): ##EQU13## by using relationship of Equation (9) which leads to: 
     
         p.sub.i =0(i-1εH)                                  (19) 
    
     It has to be noted that tuple Q has the longer digit length by one digit than that of tuple P because the former has a term of S H  (i-1)×b&#39; i-1  absent in the latter. 
     Further, since the following expression is obtained: 
     
         b&#39;.sub.i-1 2.sup.i-1 =b&#39;.sub.i-1 2.sup.i -b&#39;.sub.i-1 2.sup.i-1 (20) 
    
     where value B can be expressed in terms of tuples Q and K by using Equations (18) and (20) as follows: ##EQU14## To substitute Equation (21) for B in Equation (15), the following equation is obtained: ##EQU15## where a&#39; n+1  is supposed to be equal to 0. 
     Also, as can be readily understood from the construction of tuple Q and from Equation (9), since both elements a&#39; i  and q i  can never be non-zero for any given suffix i at a time, Equation (22) is paraphrased as follows by using tuple F of Equation (14); ##EQU16## 
     On the other hand, since the relations a&#39; i  ε{0, .sup.± 1} and q i  ε{0, .sup.± 1} are maintained, elements a&#39; i  and q i  take 0, +1 or -1 so that the operations in Equation (23) including addition and subtraction may be performed. Therefore, Equation (23) can be transformed to derive Equation (5) by using tuple C into: ##EQU17## 
     In the following description, English letters and symbols such as A, B, X, Y, (f i ), (c i ) and (k 1 ), etc., correspond to those of the above-mentioned description. 
     As illustrated in FIG. 1, one embodiment of this invention includes input terminals 101, 102, 103 and 104, a two-term vector product output terminal 105, intermediate terminals 106, 108, 109 and 110, s-representation generating circuits 200, a control circuit 300, a selection circuit 400 and an accumulator 500. Details of the circuits 200, 300, 400 and 500 are respectively described later referring to FIGS. 2, 3, 4 and 5. 
     In FIG. 1, thick arrows marked on paths 103, 104, 110 and 105 represent the parallel supply of input variables X and Y, any one of (X, Y, Y/2 and 0) selected by the selection circuit 400 and output Z, and thin arrows on paths 101, 102, 1060, 1061, 1070, 1071, 1080 through 1083 and 109 represent the serial supply of input variables A and B, the absolute value code and the polarity code of the s-representation code of variable A, the absolute value code and the polarity code of the s-representation code of variable B, four control signals to the circuit 400 and a control signal to the circuit 500. Variables A and B are respectively fed to the terminals 101 and 102, and converted sequentially from the LSB side into their respective s-representation codes (a&#39; i ) and (b&#39; i ). The absolute value code and the polarity code of (a&#39; i ) are then fed through the paths 1060 and 1061 to the control circuit 300, respectively. Similarly, the absolute value code and the polarity code of (b&#39; i ) are given through the paths 1070 and 1071 to the control circuit 300, respectively. The circuit 300 produce control variables (f i ), (c i ) and (k i ) in Equation (14) based on said s-representation codes (a&#39; i ) and (b&#39; i ), sequentially from the LSB side, and generates control signals for the selection of the second term of Equation (8), i.e., the selection of one out of X, Y, Y/2 and 0 depending on appropriate combinations of elements f i , c i  and k i . The control signals given from the circuit 300 are sequentially conveyed to the circuit 400 through the paths 1080, 1081, 1082 and 1083, and at the same time, the circuit 300 produces addition-subtraction control signals to the accumulator 500 through the terminal 109 immediately when element c i  becomes 1. Said variable X and Y are given from the terminals 103 and 104, respectively, to the circuit 400 so that one out of X, Y, Y/2 and 0 may be produced to the input terminal of the accumulator 500 in response to the control signals 1801 to 1803 from the control circuit 300. An accumulator register 504 (see FIG. 5) of the accumulator 500 temporarily stores p i  of Equation (7), and performs Equation (8) sequentially according to the one selected by the circuit 400 out of X, Y, Y/2 and 0 and to the addition-subtraction control signal given from the control circuit 300 through the path 109. As a result, at the (n+2)-th time point, the result Z of the two-term vector product computation represented by Equation (7) is given to the terminal 105. 
     For example, the calculation of 11×21+5×38 is considered below. To the terminals 103 and 104 are respectively fed decimal number 21 as variable X and decimal number 38 as variable Y in parallel six-bit codes, and to the terminals 101 and 102 are supplied four-bit codes representing decimal numbers 11 and 5 as variables A and B from the LSB side on a time serial basis. In other words, (1011) is supplied to the terminal 101, and (0101) to the terminal 102 on a time serial basis. These serial data are converted by the circuit 200 into s-representation codes. As a result, to the intermediate terminals 1060 and 1061 are respectively supplied the absolute value code sequence (10101) and the polarity code sequence (00101) of the s-representation code (10101) of decimal value 11, and to the terminals 1070 and 1071 are respectively fed the absolute value code sequence (00101) and the polarity code sequence (00000) of the s-representation code (00101) of decimal value 5. Now, 0  and 1 are supposed to be positive and negative polarity codes, respectively. The control circuit 300 generates tuples C, F and K based on these two s-representation codes depending on Equations (14). In this instance, the tuples are represented as follows: 
     
         C=(011111) 
    
     
         F=(010101) 
    
     
         K=(001010) 
    
     Consequently, the following selection sequence can be made in appropriate combinations of tuples C, F and K at the terminals 1080 to 1083 by activating the corresponding terminals in the selection order of: 
     
         (X, Y/2, X, Y/2, X, and 0). 
    
     Meanwhile, successively control signals indicative of subtraction, addition, subtraction, addition, addition and subtraction appear at the terminal 109 depending on tuple C. 
     The selection circuit 400 gives binary numbers corresponding to decimal numbers 21, 38/2, 21, 38/2, 21 and 0 to the terminal 110 in response to the signals supplied from the terminals 1080 through 1083. 
     The accumulator 500 accomplishes the accumulation in response to the control signals appearing at the terminal 109 and the outputs at the circuit 400, resulting in supplying to the out-terminal 105 the following correct solution: ##EQU18## 
     Referring to FIG. 2, the circuit 200 comprises input terminal 101, an s-representation-absolute value output terminal 1060, an s-representation-sign bit output terminal 1061, flip-flops 204, 205, 206, a full adder 207 an Exclusive-OR gate 208, an AND gate 209, and a polarity-code expanding circuit 210. The conversion of a binary number into its s-representation code is performed as follows: Namely, if a given binary number is represented by W, the arithmetic sum W and 2W is subtracted by W on a bit-by-bit basis, and the result is multiplied by 1/2. The bit-by-bit subtraction gives the s-representation code of three values (0,  35  1). For details of the above-mentioned conversion technique, reference is made to &#34;Error Correcting Codes, Second Edition, pp. 450-453&#34; by Peterson &amp; Weldon, published in 1972 by the MIT Press. 
     For example, how to obtain the s-representation of the earlier cited decimal value 11 will be described below. Decimal number 11 can be represented as (1011) by binary notion. This value and its two fold multiple are arithmetically added: ##EQU19## 
     Subtraction of decimal number 11 from the final result (100001) on a bit-by-bit basis, followed by the elimination of the LSB or, in other words, the multiplication of the result by 1/2, gives said s-representation: ##EQU20## 
     It is supposed that, in FIG. 2, each of five bits of variable A is given sequentially from its LSB into the terminal 101. Since the flip-flop 204 delays variable A by one bit, its output is 2A. The full adder 207 adds the output 2A of the flip-flop 204 and variable A whose polarity code is expanded by one bit through the polarity-code expanding circuit 210. In this addition, the flip-flop 205 is used to maintain carry. The resultant output of the full adder 207 is 3A. The flip-flop 206 for delaying the output 3A by one bit produces an output A. To enable the 3A and A to undergo the arithmetic operation, the output of the flip-flop 204 is given the same bit length as that of 3A produced on the flip-flop 206 through the circuit 210, and the bit-by-bit subtractions are accomplished by the gates 208 and 209 with the result that the s-representation code is obtained from the output terminal 1060 and the terminal 1061. The circuit 210 is a flip-flop to expand the MSB of a given data by one bit. The carry-maintaining flip-flop 205 has to be reset in advance of the adding operation. 
     Referring to FIG. 3, the control circuit 300 has absolute-value code input terminals 1060 and 1070, polarity code input terminals 1061 and 1071, intermediate terminals 305, 306, 307 and 308, selection-signal output terminals 1080, 1081, 1082 and 1083, an addition-subtraction control signal 109, AND gates 314, 322, 323, 325 and 326, OR gates 320 and 321, and inverter gate 324, flip-flops 315, 316 and 317, and 2-1 selection circuits 318 and 319. A first s-representation code (a&#39; i ) is given from the terminals 1060 and 1061, and a second s-representation code (b&#39; i ) is similarly fed from the terminals 1070 and 1071. Supposing that the absolute value codes of said s-representation codes (a&#39; i ) and (b&#39; i ) are sequentially given to the terminals 1060 and 1070, respectively, the AND gate 314 detects bit positions where both are non-zero. Since the flip-flop 316 delays the output of the gate 314 by one bit, the terminal 307 is fed with tuple (k i ) represented by tuple k of recursive Equation (14). The absolute value code of said code (a&#39; 1 ) is tuple (f i ) of Equation (14), and (f i ) is sequentially supplied to the terminal 305. Said code (b&#39; i ) supplied from the terminals 1070 and 1071 undergoes the control by the 2-1 selection circuits 318 and 319 in response to the output of the flip-flop 316, i.e., a signal corresponding to tuple (k i ) of Equation (14), and is supplied as output either as it is or delayed by one bit by the flip-flops 315 and 317. This means that (q i ) of Equation (18) has been produced. Consequently, the absolute value code of (q i ) of said Equation (18) is generated as output of the 2-1 selection circuit 318, and also the polarity code of Equation (18) is supplied as output of the 2-1 selection circuit 319. Since the OR gates 320 and 321 function to add the absolute value code and the polarity code of the s-representation code (a&#39; i ) respectively given to the terminals 1060 and 1061 to those corresponding to (q i ) of Equation (18) supplied from the circuits 318 and 319, the absolute value code and the polarity code of tuple (c i ) of Equation (14) are obtained at the terminals 306 and 308, respectively. The output of the OR gate 321 appearing at the terminal 308 is conveyed directly as the addition-subtraction control signal to the output terminal 109 to control the accumulator 500 of FIG. 1. The AND gate 322 provides the conditions corresponding to the first and second lines of Equation (8) based on the absolute value codes corresponding to (f i ) and (c i ) of Equation (14) respectively emerging at the terminals 305 and 306, and transmits to the terminal 1080 a signal which requests the selection circuit 400 of FIG. 1 to select variable X given to the terminal 103. The AND gates 323 and 325 make the conditions corresponding to the third and fourth lines of Equation (8) given from the signals appearing at the terminals 305, 306 and 307, respectively, corresponding to the absolute value codes of (f i ) and (c i ) and (k i ) of Equation (14). Consequently, a signal which requests the selection circuit 400 to select said variable Y given to the terminal 104 is supplied to the terminal 1082 through the AND gate 325. The AND gates 323 and 326 give the conditions corresponding to the fifth and sixth lines of Equation (8) from the signals produced at the terminals 305, 306 and 307 respectively corresponding to the absolute value codes of tuples (f i ) and (c i ) and to (k i ) of Equations (14). As a result, a signal which requests the circuit 400 to select 1/2 of said variable Y, i.e., Y/2 is given to the terminal 1083 through the gate 326. The gate 324 gives the condition corresponding to the seventh line of Equation (8) by inversing the absolute value code of (c i ) of Equation (14) given at the terminal 306, and transmits to the terminal 1081 a signal which requests the circuit 400 to select 0. 
     Referring to FIG. 4, the selection circuit 400 is composed of input terminals 1080 through 1083, a zero input terminal 105, a third parallel variable (X) input terminal 103, a fourth parallel variable (Y) input terminal 104 selection gates 410, 411, 412 and 413, and an output terminal 110. Since the variable (Y) input terminal 104 is connected to the gate 413 in the form shifted down by one bit, the output of the gate 413 is Y/2. The selection signal generated from the control circuit 300 is applied to the terminals 1082, 1083, 1080 and 1081 and activates any one of the gates 410, 411, 412 and 413. The activated gate conveys one of four values 0, X, Y and Y/2 to the terminal 110. 
     Referring to FIG. 5, the accumulator 500 consists of a control-signal input terminal 109, an accumulation input terminal 110, an accumulator output terminal 105, an accumulator register 504 and an addition-subtraction circuit 505. Herein, the output of the accumulator 504 is connected to the input of the circuit 505 in the shift-down form so that said output may be multiplied by 1/2. The accumulator 504 temporarily stores the partial product p i  of Equation (7). Thus, Equation (7) is executed to give the output of the circuit 505 in response to a signal given from the circuit 300 through the terminal 109 and the data (X, Y, 0 or Y/2) selected by the circuit 400, and as a result, new partial product p i  is transferred to the register 504. By repeating this procedure n+2 times, Z in Equation (7) is obtained to give the two-term vector product of Equation (5). 
     In this way, this invention achieves the two-term vector multiplication with the simple circuits.