Abstract:
A LCD panel is proposed, which meets analog display mode and memory display mode. The LCD panel includes a capacitive element, first to third switch elements, and a circuit. The first switch element turns ON during a first operation for writing pixel potential from signal line to the capacitive element, and turns OFF during a second operation. The second and third switch elements turn OFF during the first operation. The second switch element turns ON during a readout period in the second operation, to read out the pixel potential from the capacitive element. The third switch element turns ON during a write period in the second operation, to rewrite the pixel potential into the capacitive element. The circuit restores a logic level of the pixel potential read out from the capacitive element, and rewrites inversion of the restored logic level to the capacitive element.

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
       [0001]    The subject matter of application Ser. No. 12/634,462, is incorporated herein by reference. The present application is a Continuation of U.S. Ser. No. 12/634,462, filed Dec. 9, 2009, which claims priority to Japanese Patent Application JP 2008-321652 filed in the Japanese Patent Office on Dec. 17, 2008, the entire contents of which is hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The invention relates to a liquid crystal display panel having a pixel structure meeting both an analog display mode and a memory display mode. The invention further relates to an electronic device mounted with the liquid crystal display panel. 
         [0004]    2. Description of the Related Art 
         [0005]    Recently, some liquid crystal display panel may meet both of display in an analog display mode and display in a memory display mode (for example, see Japanese Patent Application Unexamined Publication No. H09-243995). The analog display mode means a display mode in which a pixel gray-scale may be analogously expressed with multiple gray-scales in a minimum display unit (called “sub pixel” in the specification). The memory display mode means a display mode in which a pixel gray-scale may be expressed with two gray-scales of white and black based on binary information (H level or L level) stored in a memory. 
         [0006]    In the memory display mode, operation of writing gray-scale potential need not be performed with a frame period. Therefore, power consumption can be reduced in the memory display mode compared with in the analog display mode. 
       SUMMARY OF THE INVENTION 
       [0007]      FIGS. 1 and 2  show pixel circuit examples of a liquid crystal display panel meeting both the analog display mode and the memory display mode, respectively. The pixel circuits of  FIGS. 1 and 2  show a case where SRAM is used for a memory within a sub pixel respectively.  FIG. 1  shows a pixel circuit example when one SRAM is disposed for one sub pixel.  FIG. 2  shows a pixel circuit example when one SRAM is disposed for three sub pixels. 
         [0008]    In  FIG. 1 , LC shows a liquid crystal corresponding to the sub pixel. However, in  FIG. 2 , LC is omitted to be shown for convenience of drawing. 
         [0009]    In  FIG. 1 , Cs is a holding capacitance holding gray-scale potential. In  FIG. 2 , three holding capacitances are shown as Cs(B), Cs(G) and Cs(R). B in the parenthesis shows a holding capacitance used for a sub pixel corresponding to blue. G in the parenthesis shows a holding capacitance used for a sub pixel corresponding to green. R in the parenthesis shows a holding capacitance used for a sub pixel corresponding to red. 
         [0010]    Each of thin film transistors N 1 , N 1 (B), N 1 (G) and N 1 (R) is an active element that is controlled to be ON during a period of writing gray-scale potential to a corresponding holding capacitance Cs, and controlled to be OFF during other periods. Control lines CTL 1 , CTL 1 (B), CTL 1 (G) and CTL 1 (R) are used for the thin film transistors N 1 , N 1 (B), N 1 (G) and N 1 (R) respectively. In  FIG. 2 , ON periods of the thin film transistors N 1 , N 1 (B), N 1 (G) and N 1 (R) are time-sequentially arranged. 
         [0011]    In  FIG. 1 , the thin film transistor N 2  is an active element that is controlled to be ON during a period of writing gray-scale potential to corresponding, one sub pixel. In  FIG. 2 , the thin film transistor N 2  is an active element that is controlled to be ON during a period of writing gray-scale potential to one of corresponding, three sub pixels. In  FIG. 2 , gray-scale potential is finally written to the sub pixel corresponding to blue. 
         [0012]    The thin film transistor N 3  is an active element that is controlled to be ON when gray-scale potential is written in the analog display mode, or when electric potential VXCS different from that of a counter electrode is written in the memory display mode. Holding potential of SRAM (P 1 , P 2 , N 6  and N 7 ) is used for such control. In the case of the circuit example, when the transistor N 3  is ON, the transistor N 4  is OFF, and when the transistor N 3  is OFF, the transistor N 4  is ON. 
         [0013]    The thin film transistor N 4  is an active element that is controlled to be ON when the same potential as that of the counter electrode is written to the holding capacitance in the memory display mode. 
         [0014]    The thin film transistor N 5  is an active element that is controlled to be ON when control potential is written to the SRAM (P 1 , P 2 , N 6  and N 7 ). A control line CTL 2  is used for controlling the thin film transistor N 5 . The thin film transistor N 5  is controlled to be ON or OFF such that the thin film transistor N 3  may be controlled to be ON when gray-scale potential is written in the analog display mode, or when electric potential VXCS different from that of the counter electrode is written in the memory display mode. 
         [0015]    Some difficulties still exist in the pixel circuits of  FIGS. 1 and 2 . One of the difficulties is a fact that large area is required for forming the SRAM. It is particularly pointed out that when one SRAM is arranged for one sub pixel, transmissive aperture ratio is reduced. 
         [0016]    In addition, when high display resolution is required for a liquid crystal display panel, it is technically difficult to dispose one SRAM within one sub pixel. This leads to a difficulty that the resolution is limited when the circuit configuration of  FIG. 1  or  2  is employed. 
         [0017]    It is desirable to provide a liquid crystal display panel having a memory display mode and an electronic device, capable of avoiding reduction in transmissive aperture ratio and achieving high resolution. 
         [0018]    A liquid crystal display panel according to an embodiment of the invention includes: a capacitive element holding pixel potential representing a gray-scale level and provided in each of pixels; a first switch element having a first terminal connected to one electrode of the capacitive element and to a drive electrode in a liquid crystal element, and having a second terminal connected to a signal line, the first switch element being controlled to be ON during a first operation period where pixel potential is written from the signal line to the capacitive element, and controlled to be OFF during a second operation period where readout of the pixel potential from the capacitive element, inversion and amplification of the read out pixel potential, and rewriting of the inverted-amplified pixel potential to the capacitive element are sequentially performed; a second switch element having a first terminal connected to a first terminal of the first switch element, the second switch element being controlled to be OFF during the first operation period, and controlled to be ON during a readout period where pixel potential stored in the capacitive element is read out, the readout period being one part of the second operation period; a third switch element having a first terminal connected to the first terminal of the first switch element, the third switch element being controlled to be OFF during the first operation period, and controlled to be ON during a write period where the pixel potential is written into the capacitive element, the write period being another part of the second operation period; and a circuit restoring a logic level of pixel potential read out from the capacitive element through the second switch element during the readout period, and then writing logically-inverted output having the restored logic level to the capacitive element through the third switch element during the write period. 
         [0019]    An electronic device according to an embodiment of the invention includes the liquid crystal display panel described above. 
         [0020]    In the liquid crystal display panel and the electronic device according to the embodiments of the invention, the second switch element and the third switch element are controlled to be OFF during the first operation period, and the pixel potential of the signal line is written to the capacitive element at the timing when the first switch element is controlled to be ON. On the other hand, the first switch element is controlled to be OFF, and in this state, the second switch element is controlled to be ON and the third switch element is controlled to be OFF during the second operation period. Thereby, the pixel potential held by the capacitive element is read by the circuit, and a logic level of the read pixel potential is restored. That is, a self-refresh function is performed. Then, the second switch element is controlled to be OFF, and the third switch element is controlled to be ON. Thereby, the logically-inverted output of the restored logic level is written by the circuit to the capacitive element through the third switch element. That is, a self-inverting function is performed. 
         [0021]    According to the liquid crystal display panel and the electronic device of the embodiments of the invention, the capacitive element in each pixel is used as DRAM and refresh operation is completed within the circuit. Therefore, it is possible to avoid reduction in transmissive aperture ratio and to achieve high resolution. Also, the signal line having a large load capacity need not be charged or discharged during the refresh operation. Therefore, it is possible to reduce power consumption associated with the refresh operation. 
         [0022]    Other and further objects, features and advantages of the invention will appear more fully from the following description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a diagram showing a pixel structure example of a liquid crystal display panel. 
           [0024]      FIG. 2  is a diagram showing a pixel structure example of a liquid crystal display panel. 
           [0025]      FIG. 3  is a diagram showing a pixel structure example of a liquid crystal display panel according to an embodiment of the invention. 
           [0026]      FIG. 4  is a diagram showing an example of outside appearance of a liquid crystal display panel. 
           [0027]      FIG. 5  is a diagram showing a sectional structure example of the liquid crystal display panel. 
           [0028]      FIG. 6  is a diagram showing a system configuration example of the liquid crystal display panel. 
           [0029]      FIG. 7  is a diagram showing an arrangement example of sub pixels. 
           [0030]      FIG. 8  is a diagram showing a configuration example of a pixel circuit according to a first embodiment. 
           [0031]      FIG. 9  is a diagram showing a drive operation example in an analog display mode. 
           [0032]      FIG. 10  is a diagram showing a connection condition within a pixel circuit in the analog display mode. 
           [0033]      FIG. 11  is a diagram showing a general drive operation example in a memory display mode. 
           [0034]      FIG. 12  is a diagram showing a detailed drive operation example in the memory display mode. 
           [0035]      FIG. 13  is a diagram showing a connection condition within a pixel circuit when gray-scale potential is read from a holding capacitance. 
           [0036]      FIG. 14  is a diagram showing a connection condition within a pixel circuit during latch operation. 
           [0037]      FIG. 15  is a diagram showing a connection condition within a pixel circuit in a transient period. 
           [0038]      FIG. 16  is a diagram showing a connection condition within a pixel circuit when gray-scale potential inverted in logic is written to the holding capacitance. 
           [0039]      FIG. 17  is a diagram showing a configuration example of a pixel circuit according to a second embodiment. 
           [0040]      FIG. 18  is a diagram showing a drive operation example in an analog display mode. 
           [0041]      FIG. 19  is a diagram showing a general drive operation example in a memory display mode. 
           [0042]      FIG. 20  is a diagram showing a detailed drive operation example in the memory display mode. 
           [0043]      FIG. 21  is a diagram showing a configuration example of a pixel circuit according to a third embodiment. 
           [0044]      FIG. 22  is a diagram showing a drive operation example in an analog display mode. 
           [0045]      FIG. 23  is a diagram showing a general drive operation example in a memory display mode. 
           [0046]      FIG. 24  is a diagram showing another configuration example of a pixel circuit. 
           [0047]      FIG. 25  is a diagram showing a detailed drive operation example in a memory display mode. 
           [0048]      FIG. 26  is a diagram showing a functional configuration example of an electronic device. 
           [0049]      FIG. 27  is a diagram showing a product example of an electronic device. 
           [0050]      FIGS. 28A and 28B  are diagrams showing a product example of the electronic device. 
           [0051]      FIG. 29  is a diagram showing a product example of the electronic device. 
           [0052]      FIGS. 30A and 30B  are diagrams showing a product example of the electronic device. 
           [0053]      FIG. 31  is a diagram showing a product example of the electronic device. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0054]    Hereinafter, embodiments of the invention will be described with reference to accompanied drawings. 
         [0055]    A liquid crystal display panel according to one embodiment of the invention employs a pixel circuit utilizing a capacitive element holding gray-scale potential as DRAM, and includes the following elements (1) to (5) illustrated in  FIG. 3 . 
         [0056]    (1) A capacitive element Cs holding pixel potential representing a gray-scale level and provided in each of pixels. 
         [0057]    (2) A first switch SW 1  having a first terminal connected to one electrode of the capacitive element and to a drive electrode in a liquid crystal element, and having a second terminal connected to a signal line. The first switch is controlled to be ON during a first operation period where pixel potential is written from the signal line to the capacitive element, and controlled to be OFF during a second operation period where readout of the pixel potential from the capacitive element, inversion and amplification of the read out pixel potential, and rewriting of the inverted-amplified pixel potential to the capacitive element are sequentially performed. 
         [0058]    (3) A second switch SW 2  having a first terminal connected to a first terminal of the first switch. The second switch is controlled to be OFF during the first operation period, and controlled to be ON during a readout period where pixel potential stored in the capacitive element is read out. The readout period is one part of the second operation period. 
         [0059]    (4) A third switch SW 3  having a first terminal connected to the first terminal of the first switch element. The third switch is controlled to be OFF during the first operation period, and controlled to be ON during a write period where the pixel potential is written into the capacitive element. The write period is another part of the second operation period. 
         [0060]    (5) A circuit  1  restoring a logic level of pixel potential read out from the capacitive element through the second switch during the readout period, and then writing logically-inverted output having the restored logic level to the capacitive element through the third switch during the write period. 
         [0061]    In the following, embodiments of the invention will be described with reference to  FIG. 4  to  FIG. 31 . The description will be given in the following order. 
       (A) Basic Structure of Liquid Crystal Display Panel 
     (B) First Embodiment: One Circuit  1  Per Sub Pixel 
       [0062]    (B-1) System Configuration Example 
         [0063]    (B-2) Configuration of Pixel Circuit 
         [0064]    (B-3) Drive Operation Example 
         [0065]    (B-4) Conclusion 
       (C) Second Embodiment: One Circuit  1  Per Three Sub Pixels 
       [0066]    (C-1) Configuration of Pixel Circuit 
         [0067]    (C-2) Drive Operation Example 
         [0068]    (C-3) Conclusion 
       (D) Third Embodiment: One Circuit  1  Per Six Sub Pixels 
       [0069]    (D-1) Configuration of Pixel Circuit 
         [0070]    (D-2) Drive Operation Example 
         [0071]    (D-3) Conclusion 
       (E) Other Embodiments 
       [0072]    It will be appreciated that the invention is not limited to embodiments. 
       (A) BASIC STRUCTURE OF LIQUID CRYSTAL DISPLAY PANEL 
     (A-1) Outside Structure 
       [0073]    First, an example of outside appearance of a liquid crystal display panel is described. As used herein, the term “liquid crystal display panel” refers not only to a panel module where a pixel array section and a drive circuit are formed using the same process, but also to a panel module where a drive circuit configured as an integrated circuit is mounted on a panel provided with a pixel array section. The integrated circuit here corresponds to “semiconductor device”. 
         [0074]      FIG. 4  shows the example of outside appearance of the liquid crystal display panel. The liquid crystal display panel  11  has a structure where a support substrate  13  is attached with a counter substrate  15 . 
         [0075]    The support substrate  13  includes glass, plastic or another transmissive material. The counter substrate  15  also includes glass, plastic or another transmissive material. The counter substrate  15  is a member sealing a surface of the support substrate  13  with a seal material in between. 
         [0076]    In addition, FPC (Flexible Printed Circuit)  7  is disposed on the liquid crystal display panel  11  for inputting an external signal or drive power as necessary. 
       (A-2) Sectional Structure 
       [0077]      FIG. 5  shows a sectional structure example of the liquid crystal display panel. The liquid crystal display panel  11  of  FIG. 5  includes two glass substrates  13  and  15 , and a liquid crystal layer  19  enclosed in a manner of being sandwiched by the substrates. A polarizing plate  21  is disposed on an outer surface of each substrate, and an alignment film  23  is disposed on an inner surface thereof. The alignment film  23  is used for arranging liquid crystal molecules of the liquid crystal layer  19  in a certain direction. A polyimide film is typically used for the film  23 . 
         [0078]    Pixel electrodes  25  and counter electrodes  27  are formed on the glass substrate  15 , the electrodes  25  and  27  being formed of a transparent conductive film respectively. In  FIG. 5 , pixel electrodes  25  have a structure where five electrode branches  25 A formed into a comb shape are connected at either ends via connections. 
         [0079]    In contrast, the counter electrodes  27  are formed on a lower layer side (glass substrate  15  side) with respect to the electrode branches  25 A in a manner of covering the whole pixel area. This electrode structure induces a parabolic electric field between the electrode branches  25 A and the counter electrodes  27 . That is, even regions on tops of the electrode branches  25 A may be affected by the electric field. Therefore, a liquid crystal in the whole pixel area may be directed to a desired orientation direction. 
       (B) FIRST EMBODIMENT 
     (B-1) System Configuration Example 
       [0080]    First, description is made on a system configuration of a liquid crystal display panel  31  having a pixel structure according to the present embodiment. 
         [0081]      FIG. 6  shows a system configuration example of the liquid crystal display panel module  31 . The module  31  has a configuration where a pixel array section  33 , a signal line drive section  35 , a control line drive section  37 , and a drive timing generation section  39  are arranged on a lower glass substrate (corresponding to the glass substrate  15  in  FIG. 5 ). In the embodiment, a drive circuit of the pixel array section  33  is formed as one or plural semiconductor integrated circuit/circuits, and mounted on the glass substrate. 
         [0082]    The pixel array section  33  has a matrix structure where white units, each unit configuring one pixel of display, are arranged in M rows and N columns. As used herein, the term “row” refers to a pixel line configured of 3*N sub pixels  41  arranged in an X axis direction in the figure. The term “column” refers to a pixel line configured of M sub pixels  41  arranged in a Y axis direction in the figure. Note that a value of M and a value of N are determined according to display resolution in a vertical direction and display resolution in a horizontal direction respectively. 
         [0083]      FIG. 7  shows an arrangement example of the sub pixels  41  configuring white units. The example of  FIG. 7  is an arrangement example when a white unit is configured of sub pixels  41  corresponding to three primary colors. Note that a configuration of a white unit is not limited to this. 
         [0084]    The signal line drive section  35  is a circuit driving signal lines DTL. In the present embodiment, the signal lines DTL are wired extending in the Y axis direction in the figure. For example, in the analog display mode, the signal line drive section  35  operates so that optional gray-scale potential (analog potential Vsig) in accordance with pixel gray-scale is applied to a corresponding signal line DTL. For example, even in the memory display mode, when a logic level of gray-scale potential to be stored in a sub pixel  41  is changed, the section  35  operates so that necessary pixel gray-scale is applied to a corresponding signal line DTL. 
         [0085]    The control line drive section  37  is a circuit driving control lines CTL  21  to  25 . In the present embodiment, the control lines CTL  21  to  25  are wired extending in the X axis direction in the figure. For example, in the analog display mode, the section  37  controls operation of writing gray-scale potential applied to a signal line DTL to a sub pixel  41 . For example, in the memory display mode, the section  37  controls refresh operation of gray-scale potential stored in a sub pixel  41 , and rewriting operation. 
         [0086]    The drive timing generation section  39  is a circuit device supplying a drive pulse to the signal line drive section  35  and to the control line drive section  37 . 
       (B-2) Configuration of Pixel Circuit 
       [0087]      FIG. 8  shows a configuration example of a pixel circuit corresponding to the sub pixel  41  according to the present embodiment.  FIG. 8  shows a circuit configuration as a circuit configuration example when the circuit  1  ( FIG. 3 ) having a self-refresh function and a self-inverting function is disposed in one-to-one correspondence to the sub pixel  41 . 
         [0088]    Hereinafter, each of elements configuring the pixel circuit is described. 
         [0089]    In  FIG. 8 , LC shows a liquid crystal corresponding to the sub pixel  41 . 
         [0090]    In  FIG. 8 , “Cs” shows a holding capacitance holding gray-scale potential. In the present embodiment, the holding capacitance Cs is used as DRAM in the memory display mode. 
         [0091]    A thin film transistor N 11  is an active element that is controlled to be ON during writing gray-scale potential to the holding capacitance Cs, and controlled to be OFF during other periods. A control line CTL 21  is used for controlling the thin film transistor N 11 . One main electrode of the transistor N 11  is connected to wiring connected to a pixel electrode, and the other main electrode is connected to one main electrode of a thin film transistor N 12  through wiring. 
         [0092]    The thin film transistor N 12  is an active element that is controlled to be ON when gray-scale potential is written from the signal line DTL. A control line CTL 22  is used for controlling the thin film transistor N 12 . The thin film transistor N 12  corresponds to the first switch SW 1  in  FIG. 3 . One main electrode of the transistor N 12  is connected to the signal line DTL, and the other main electrode thereof is connected to the one main electrode of the thin film transistor N 11  through wiring. 
         [0093]    A thin film transistor N 13  is an active element that is controlled to be OFF when pixel potential is written from the signal line to the holding capacitance. The transistor N 13  is controlled to be ON only for a certain period immediately before end of each frame during performing internal refresh operation of the memory display mode. Gray-scale potential held by the holding capacitance Cs acting as DRAM is read by the circuit  1  ( FIG. 3 ) during a period where the thin film transistor N 13  is controlled to be ON. A control line CTL 23  is used for controlling the thin film transistor N 13 . The thin film transistor N 13  corresponds to the second switch SW 2  in  FIG. 3 . 
         [0094]    A thin film transistor N 14  is also an active element that is controlled to be OFF when pixel potential is written from the signal line to the holding capacitance. The transistor N 14  is controlled to be ON only for a certain period immediately after start of each frame during performing internal refresh operation of the memory display mode. Gray-scale potential, which has been inverted in logic within the circuit  1  ( FIG. 3 ), is written to the holding capacitance Cs during a period where the thin film transistor N 14  is controlled to be ON. A control line CTL 24  is used for controlling the thin film transistor N 14 . The thin film transistor N 14  corresponds to the third switch SW 3  in  FIG. 3 . 
         [0095]    Thin film transistors P 11 , P 12 , N 15 , N 16  and N 17  configure the circuit  1  in  FIG. 3 . 
         [0096]    The thin film transistors P 11  and N 15  configure an inverter circuit (amplifier circuit). In addition, the thin film transistors P 12  and N 16  configure an inverter circuit (amplifier circuit). Drive power of the inverter circuits includes high-level power of VDD and low-level power of VSS. 
         [0097]    An input side of the inverter circuit including the thin film transistors P 11  and N 15  is connected to one main electrode of the thin film transistor N 13 . The inverter circuit may input gray-scale potential of the holding capacitance Cs when the transistor N 13  is ON. 
         [0098]    An input side of the inverter circuit including the thin film transistors P 12  and N 16  is connected to one main electrode of the thin film transistor N 14 . The inverter circuit may write gray-scale potential inverted in logic to the holding capacitance Cs when the transistor N 14  is ON. 
         [0099]    An output side of the inverter circuit including the thin film transistors P 11  and N 15  is connected to an input side of the inverter circuit including the thin film transistors P 12  and N 16 . An output side of the inverter circuit including the thin film transistors P 12  and N 16  is connected to the input side of the inverter circuit including the thin film transistors P 11  and N 15  through a thin film transistor N 17 . The thin film transistor N 17  controls operation of the circuit  1  ( FIG. 3 ). A control line CTL 25  is used for controlling the thin film transistor N 17 . 
         [0100]    For example, when the thin film transistor N 17  is ON, the two inverter circuits operate as a latch circuit. When the inverter circuits operate as the latch circuit, a self-refresh function is enabled. That is, operation of restoring a logic level is performed so as to have logic amplitude of VDD to VSS. Logically-inverted output of gray-scale potential read from the holding capacitance Cs is provided on the output side of the inverter circuit including the thin film transistors P 11  and N 15 . 
         [0101]    In addition, for example, when the thin film transistor N 17  is OFF, the two inverter circuits operate as independent amplifier circuits. 
       (B-3) Drive Operation Example 
       [0102]    Hereinafter, drive operation examples of the pixel circuit configuring the sub pixel  41  are described for each display mode. 
       (1) Analog Display Mode 
       [0103]      FIG. 9  shows specific control operation of the control line drive section  37  for a certain scan line in the analog display mode. In  FIG. 9 , (A) shows a waveform of gray-scale potential applied to the signal line DTL. In the present embodiment, polarity of voltage applied between a pixel electrode and a counter electrode is inverted on a horizontal-period cycle (1H cycle). That is, line inversion drive is performed. Therefore, in (A), the waveform of gray-scale potential applied to the signal line DTL is drawn such that a potential level is inverted on a 1H cycle. High-level potential of the gray-scale potential applied to the signal line DTL is VDD 1 , and low-level potential thereof is VSS. While (A) shows an example of a case of the largest amplitude, a potential level between VDD 1  and VSS is actually used depending on pixel gray-scale. 
         [0104]    In  FIG. 9 , (B) shows a drive waveform of each of the control lines CTL 21  and CTL 22 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . As shown in the figure, drive potential is controlled to the high-level potential VDD 2  only at the timing of writing gray-scale potential from the signal line DTL. 
         [0105]    (C) shows a drive waveform of each of the control lines CTL 23  and CTL 24 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . However, the control lines CTL 23  and CTL 24  are continuously controlled at the low-level potential VSS 2  in the analog display mode. 
         [0106]    (D) shows a drive waveform of the control line CTL 25 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . However, the control line CTL 25  is continuously controlled at the high-level potential VDD 2  in the analog display mode. 
         [0107]      FIG. 10  shows a connection condition within a pixel circuit when gray-scale potential is written from the signal line DTL in the analog display mode. A writing path of the gray-scale potential is shown by an arrow. 
         [0108]    In this case, only the thin film transistor N 12  corresponding to the first switch SW 1  is controlled to be ON as shown in  FIG. 10 . In contrast, both of the thin film transistor N 13  corresponding to the second switch SW 2  and the thin film transistor N 14  corresponding to the third switch SW 3  are controlled to be OFF over the whole period. That is, a portion of the pixel circuit including the holding capacitance Cs and a pixel electrode is electrically perfectly isolated from the circuit  1  ( FIG. 3 ). 
         [0109]    The thin film transistor N 17  in the circuit  1  is continuously controlled to be ON, and thus continuously operates as a latch circuit. 
       (2) Memory Display Mode 
       [0110]    The memory display mode includes operation of writing gray-scale potential from the signal line DTL to the holding capacitance Cs, and operation of refreshing gray-scale potential stored in the holding capacitance Cs within a sub pixel. The operation of writing gray-scale potential from the signal line DTL to the holding capacitance Cs is performed, for example, when display contents are changed. When gray-scale potential is written from the signal line DTL to the holding capacitance Cs, operation of the pixel circuit is the same as operation in the analog display mode. Therefore, description of the operation is omitted. 
         [0111]      FIG. 11  shows a content of control operation of the control line drive section  37  in the case of refreshing gray-scale potential stored in the holding capacitance Cs within a sub pixel.  FIG. 11  shows a relationship in drive operation in frames. 
         [0112]    In  FIG. 11 , (A) shows a drive waveform of the control line CTL 21 . (B) shows a drive waveform of each of the control lines CTL 23  and CTL 24 . The two control lines are applied with high-level potential in a pulsed manner on a one-frame cycle. (C) shows a drive waveform of the control line CTL 25 . The control line CTL 25  is applied with low-level potential in a pulsed manner on a one-frame cycle. 
         [0113]    In  FIG. 11 , (D) shows a drive waveform of counter electrode potential VCS. As shown in the figure, high-level potential and low-level potential are alternately outputted on a one-frame cycle. 
         [0114]    (E) shows a waveform of showing change in gray-scale potential (PIX) to be written to the holding capacitance Cs. As shown in the figure, the gray-scale potential (PIX) is alternately changed in order to keep a light emitting state of the sub pixel  41  in the memory display mode. 
         [0115]    In the memory display mode, the control line CTL 22  is continuously controlled at low-level potential. 
         [0116]    Next, drive operation within one frame is described in detail. 
         [0117]      FIG. 12  shows a content of control operation of the control line drive section  37  for a certain scan line in the memory display mode.  FIG. 12  shows a boundary portion between frames of  FIG. 11  in an expanded manner. In  FIG. 12 , a preceding frame is shown as frame N, and a following frame is shown as frame N+1. 
         [0118]    In  FIG. 12 , (A) shows a drive waveform of the control line CTL 21 . As shown in the figure, the control line CTL 21  is controlled at the high-level potential VDD 2  for a certain period from a point immediately before end of the frame N to a point immediately after start of the frame N+1. 
         [0119]    (B) shows a drive waveform of the control line CTL 23 . As shown in the figure, the control line CTL 23  is controlled at the high-level potential VDD 2  only for a certain period immediately before end of each frame. 
         [0120]    (C) shows a drive waveform of the control line CTL 24 . As shown in the figure, the control line CTL 24  is controlled at the high-level potential VDD 2  only for a certain period immediately after start of each frame. 
         [0121]    (D) shows a drive waveform of the control line CTL 25 . As shown in the figure, the control line CTL 25  is basically controlled at the high-level potential VDD 2 , but controlled at the low-level potential VSS 2  immediately before starting read of gray-scale potential from the holding capacitance Cs to the circuit  1  ( FIG. 3 ). 
         [0122]    Then, when certain time has passed, the control line CTL 25  is controlled at the high-level potential VDD 2  again. Such application of the high-level potential VDD 2  is performed for a certain period before the frame N is finished. A latch function of the circuit  1  ( FIG. 3 ) is enabled during applying the high-level potential VDD 2 , and gray-scale potential (PIX) read from the holding capacitance is returned to original potential. That is, self-refresh operation is performed. In this way, self-refresh operation is performed without charging or discharging the signal line DTL. 
         [0123]    When the self-refresh operation is finished, the control line CTL 25  is controlled at the low-level potential VSS 2  again, and such a potential state is kept until a certain period has passed from start of a following frame. Then, after a certain time has passed from start of ON control of the thin film transistor N 14  acting as the third switch SW 3 , the control line CTL 25  is controlled to be ON again, and such a potential state is kept. 
         [0124]    In  FIG. 12 , (E) shows a waveform showing change in counter electrode potential VCS. As shown in the figure, a potential level is inverted with a frame period. 
         [0125]      FIG. 13  shows a state within the pixel circuit when gray-scale potential (PIX) is read from the holding capacitance Cs in the memory display mode. 
         [0126]    At that time, the thin film transistor N 11  and the thin film transistor N 13  (second switch SW 2 ) are controlled to be ON. Thus, gray-scale potential held by the holding capacitance Cs acting as DRAM is read by the inverter circuit including the thin film transistor P 11  and the thin film transistor N 15  through an input end of the inverter circuit. 
         [0127]    When the thin film transistor N 17  is controlled to be ON in this state, the circuit  1  ( FIG. 3 ) operates as a latch circuit as shown in  FIG. 14 , and logic amplitude of the gray-scale potential read from the holding capacitance Cs is restored. 
         [0128]    Then, the thin film transistor N 17  is controlled to be OFF, and then the thin film transistor N 13  is also controlled to be OFF. This state is a connection state as shown in  FIG. 15 . Thus, gray-scale potential inverted in logic is provided on an input side of each of the thin film transistors P 12  and N 16  while restoring logic amplitude of gray-scale potential read from the holding capacitance Cs during a period of the frame N. 
         [0129]    Then, the thin film transistor N 14  is first controlled to be ON, and then the thin film transistor N 17  is controlled to be ON. This state is a connection state as shown in  FIG. 16 . Thus, gray-scale potential is newly written to the holding capacitance Cs, the gray-scale potential being inverted in logic after gray-scale potential of the frame N is refreshed. 
         [0130]    The above operation is repeated during a period of the memory display mode. 
       (B-4) Conclusion 
       [0131]    The pixel structure according to the present embodiment is used, so that a liquid crystal display panel may be achieved, which may meet both the analog display mode and the memory display mode. 
         [0132]    In addition, since the holding capacitance Cs is used as DRAM in the memory display mode, capacitance area can be small, and thus an aperture ratio may be designed to be high. 
         [0133]    Moreover, in the case of the pixel structure according to the present embodiment, the sub pixel  41  is basically unnecessary to be connected to the signal line DTL in the memory display mode. That is, even if the signal line DTL is not charged or discharged, gray-scale potential of the holding capacitance Cs, which is allowed to act as DRAM, may be refreshed. This enables further reduction in power consumption in the memory display mode. 
       (C) SECOND EMBODIMENT 
       [0134]    Next, a second embodiment is described. In the present embodiment, description is made on a case where one circuit  1  ( FIG. 3 ) is disposed for three sub pixels  41  configuring a white unit. 
       (C-1) Configuration of Pixel Circuit 
       [0135]      FIG. 17  shows a configuration example of a pixel circuit corresponding to sub pixels  41  according to the second embodiment. In  FIG. 17 , portions corresponding to those in  FIG. 8  are marked with the same reference numerals or signs. Even in  FIG. 17 , LC is omitted to be shown for convenience of drawing as in  FIG. 2 . 
         [0136]      FIG. 17  is different from  FIG. 8  in that thin film transistors N 11  are prepared to the number of three sub pixels  41  configuring a white unit. That is, three thin film transistors N 11 (B), N 11 (G) and N 11 (R) are prepared. “B” in the parenthesis shows a thin film transistor used for a sub pixel corresponding to blue. “G” in the parenthesis shows a thin film transistor used for a sub pixel corresponding to green. “R” in the parenthesis shows a thin film transistor used for a sub pixel corresponding to red. 
         [0137]    Therefore, a holding capacitance Cs(B) shows a holding capacitance Cs of the sub pixel  41  corresponding to blue display. Similarly, a holding capacitance Cs(G) shows a holding capacitance Cs of the sub pixel  41  corresponding to green display. Similarly, a holding capacitance Cs(R) shows a holding capacitance Cs of the sub pixel  41  corresponding to red display. 
         [0138]    A control line CTL 21 (B) is used for controlling the thin film transistor N 11 (B). A control line CTL 21 (G) is used for controlling the thin film transistor N 11 (G). A control line CTL 21 (R) is used for controlling the thin film transistor N 11 (R). 
       (C-2) Drive Operation Example 
       [0139]    Hereinafter, drive operation examples of the pixel circuit according to the present embodiment are described for each display mode. 
       (1) Analog Display Mode 
       [0140]      FIG. 18  shows a content of control operation of the control line drive section  37  for a certain scan line in the analog display mode. In  FIG. 18 , (A) shows a waveform of gray-scale potential applied to the signal line DTL. In the present embodiment, polarity of voltage applied between a pixel electrode and a counter electrode is inverted on a horizontal-period cycle (1H cycle). That is, line inversion drive is performed. Therefore, in (A), the waveform of gray-scale potential applied to the signal line DTL is drawn such that a potential level is inverted on a 1H cycle. High-level potential of the gray-scale potential applied to the signal line DTL is VDD 1 , and low-level potential thereof is VSS. While (A) shows an example of a case of the largest amplitude, a potential level between VDD 1  and VSS is actually used depending on pixel gray-scale. 
         [0141]    In  FIG. 18 , (B) shows a drive waveform of the control line CTL 22 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . As shown in the figure, drive potential is controlled to the high-level potential VDD 2  only at the timing of writing gray-scale potential from the signal line DTL. 
         [0142]    (C 1 ) to (C 3 ) show drive waveforms of the control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B) respectively. As shown in the figure, the control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B) are sequentially controlled at high-level potential VDD 2  in order of R, G and B. Periods where the respective control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B) are at the high-level potential VDD 2  are set to be not overlapped with one another. During the period where each of the control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B) is at the high-level potential VDD 2 , corresponding signal potential Vsig is applied to the signal line DTL. High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . 
         [0143]    In  FIG. 18 , (D) shows a drive waveform of each of the control lines CTL 23  and CTL 24 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . However, the control lines CTL 23  and CTL 24  are continuously controlled at the low-level potential VSS 2  in the case of the analog display mode. 
         [0144]    (E) shows a drive waveform of the control line CTL 25 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . However, the control line CTL 25  is continuously controlled at the high-level potential VDD 2  in the analog display mode. 
       (2) Memory Display Mode 
       [0145]    The memory display mode includes operation of writing gray-scale potential from the signal line DTL to the holding capacitance Cs, and operation of refreshing gray-scale potential stored in the holding capacitance Cs within a sub pixel. The operation of writing gray-scale potential from the signal line DTL to the holding capacitance Cs is performed, for example, when display contents are changed. When gray-scale potential is written from the signal line DTL to the holding capacitance Cs, the pixel circuit performs the same operation as operation in the analog display mode. Therefore, description of the operation is omitted. 
         [0146]      FIG. 19  shows a content of control operation of the control line drive section  37  in the case of refreshing gray-scale potential stored in the holding capacitance Cs within a sub pixel.  FIG. 19  shows a relationship in drive operation in frames. 
         [0147]    In  FIG. 19 , (A 1 ) to (A 3 ) show drive waveforms of the control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B) respectively. In the present embodiment, the control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B) are applied with high-level potential in a pulsed manner on a three-frame cycle. 
         [0148]    In  FIG. 19 , (B) shows a drive waveform of each of the control lines CTL 23  and CTL 24 . The two control lines are applied with high-level potential in a pulsed manner on a one-frame cycle. (C) shows a drive waveform of the control line CTL 25 . The control line CTL 25  is applied with low-level potential in a pulsed manner on a one-frame cycle. 
         [0149]    In  FIG. 19 , (D) shows a drive waveform of counter electrode potential VCS. As shown in the figure, high-level potential and low-level potential are alternately outputted on a one-frame cycle. 
         [0150]    (E 1 ) to (E 3 ) show waveforms showing change in gray-scale potential (PIXR, PIXG and PIXB) to be written to the holding capacitance Cs respectively. In the figure, a waveform shown by a broken line is a drive waveform of counter electrode potential VCS. A waveform shown by a solid line is a waveform of gray-scale potential stored in each sub pixel  41 . 
         [0151]    As shown in the figure, gray-scale potential is changed with change in counter electrode potential, and a potential relationship between the counter electrode potential VCS and the gray-scale potential (PIXR, PIXG and PIXB) held by the holding capacitance Cs is changed on a three-frame cycle. That is, self-refresh/self-inverting operation for each color is performed on a three-frame cycle. Note that a potential relationship within the sub pixel  41  is kept from preceding self-refresh/self-inverting operation to following self-refresh/self-inverting operation. Therefore, in the present embodiment, the holding capacitance Cs has sufficient capacitance to keep certain gray-scale potential even if a refresh rate is a three-frame cycle. In the memory display mode, the control line CTL 22  is continuously controlled at low-level potential. 
         [0152]    Next, drive operation within one frame is described in detail. 
         [0153]      FIG. 20  shows a content of control operation of the control line drive section  37  for a certain scan line in the memory display mode.  FIG. 20  shows a boundary portion between frames of  FIG. 19  in an expanded manner. In  FIG. 20 , a preceding frame is shown as frame N, and a following frame is shown as frame N+1. 
         [0154]    In  FIG. 20 , (A) shows a drive waveform of each of the control lines CTL 21 (R), CTL 21 (G) and CTL 21 (B). That is, (A) shows operation at a time point of each pulse output in (A 1 ) to (A 3 ) of  FIG. 19 . Hereinafter, description is made on the control line CTL 21 (R). 
         [0155]    As shown in the figure, the control line CTL 21 (R) is controlled at the high-level potential VDD 2  for a certain period from a point immediately before end of the frame N to a point immediately after start of the frame N+1. 
         [0156]    (B) shows a drive waveform of the control line CTL 23 . As shown in the figure, the control line CTL 23  is controlled at the high-level potential VDD 2  only for a certain period immediately before end of each frame. 
         [0157]    (C) shows a drive waveform of the control line CTL 24 . As shown in the figure, the control line CTL 24  is controlled at the high-level potential VDD 2  only for a certain period immediately after start of each frame. 
         [0158]    (D) shows a drive waveform of the control line CTL 25 . As shown in the figure, the control line CTL 25  is basically controlled at the high-level potential VDD 2 , but controlled at the low-level potential VSS 2  immediately before starting read of gray-scale potential from the holding capacitance Cs to the circuit  1  ( FIG. 3 ). 
         [0159]    Then, when certain time has passed, the control line CTL 25  is controlled at the high-level potential VDD 2  again. Such application of the high-level potential VDD 2  is performed for a certain period before the frame N is finished. A latch function of the circuit  1  ( FIG. 3 ) is enabled during applying the high-level potential VDD 2 , and gray-scale potential (PIX) read from the holding capacitance is returned to original potential. That is, self-refresh operation is performed. In this way, self-refresh operation is performed without charging or discharging the signal line DTL. 
         [0160]    When the self-refresh operation is finished, the control line CTL 25  is controlled at the low-level potential VSS 2  again, and such a potential state is kept until a certain period has passed from start of a following frame. Then, after a certain time has passed from start of ON control of the thin film transistor N 14  acting as the third switch SW 3 , the control line CTL 25  is controlled to be ON again, and such a potential state is kept. 
         [0161]    In  FIG. 20 , (E) shows a waveform showing change in counter electrode potential VCS. As shown in the figure, a potential level is inverted with a frame period. 
         [0162]    The above operation is sequentially performed in frames for the sub pixel  41  corresponding to red display, the sub pixel  41  corresponding to green display, and the sub pixel  41  corresponding to blue display. 
       (C-3) Conclusion 
       [0163]    Even in the present embodiment, the liquid crystal display panel, which may meet both the analog display mode and the memory display mode, may be achieved. 
         [0164]    In addition, in the present embodiment, a single circuit  1  ( FIG. 3 ) may be sequentially used for three sub pixels  41 . That is, the number of circuits  1  ( FIG. 3 ) formed within one white unit may be decreased from three to one. As a result, the number of elements configuring a white unit within a pixel area may be reduced. Also, when the number of elements configuring a liquid crystal display panel is reduced, a yield may be correspondingly improved. 
       (D) THIRD EMBODIMENT 
       [0165]    Next, a third embodiment is described. In the present embodiment, description is made on a case where one circuit  1  ( FIG. 3 ) is disposed for six sub pixels  41  configuring two white units. 
       (D-1) Configuration of Pixel Circuit 
       [0166]      FIG. 21  shows a configuration example of a pixel circuit corresponding to the sub pixels  41  according to the third embodiment. In  FIG. 21 , portions corresponding to those in  FIG. 17  are marked with the same reference numerals or signs. Even in  FIG. 21 , LC is omitted to be shown for convenience of drawing as in the case of  FIG. 2  or  17 . 
         [0167]      FIG. 21  is different from  FIGS. 2 and 17  in that thin film transistors N 11  are prepared to the number of six sub pixels  41  configuring two white units. That is, six thin film transistors N 11 (B 1 ), N 11 (G 1 ), N 11 (R 1 ), N 11 (B 2 ), N 11 (G 2 ) and N 11 (R 2 ) are prepared. 
         [0168]    Even in  FIG. 21 , “B” in the parenthesis shows a thin film transistor used for a sub pixel corresponding to blue. “G” in the parenthesis shows a thin film transistor used for a sub pixel corresponding to green. “R” in the parenthesis shows a thin film transistor used for a sub pixel corresponding to red. 
         [0169]    “1” in the parenthesis shows a thin film transistor used for a sub pixel configuring a first white unit, and “2” in the parenthesis shows a thin film transistor used for a sub pixel configuring a second white unit. 
         [0170]    Therefore, a holding capacitance Cs(B 1 ) shows a holding capacitance Cs of the sub pixel  41  corresponding to blue display configuring the first white unit. Similarly, a holding capacitance Cs(G 1 ) shows a holding capacitance Cs of the sub pixel  41  corresponding to green display configuring the first white unit. Similarly, a holding capacitance Cs(R 1 ) shows a holding capacitance Cs of the sub pixel  41  corresponding to red display configuring the first white unit. 
         [0171]    A holding capacitance Cs(B 2 ) shows a holding capacitance Cs of the sub pixel  41  corresponding to blue display configuring the second white unit. Similarly, a holding capacitance Cs(G 2 ) shows a holding capacitance Cs of the sub pixel  41  corresponding to green display configuring the second white unit. Similarly, a holding capacitance Cs(R 2 ) shows a holding capacitance Cs of the sub pixel  41  corresponding to red display configuring the second white unit. 
         [0172]    A control line CTL 21 (B 1 ) is used for controlling the thin film transistor N 11 (B 1 ). A control line CTL 21 (G 1 ) is used for controlling the thin film transistor N 11 (G 1 ). A control line CTL 21 (R 1 ) is used for controlling the thin film transistor N 11 (R 1 ). 
         [0173]    A control line CTL 21 (B 2 ) is used for controlling the thin film transistor N 11 (B 2 ). A control line CTL 21 (G 2 ) is used for controlling the thin film transistor N 11 (G 2 ). A control line CTL 21 (R 2 ) is used for controlling the thin film transistor N 11 (R 2 ). 
       (D-2) Drive Operation Example 
       [0174]    Hereinafter, drive operation examples of the pixel circuit according to the present embodiment are described for each display mode. 
       (1) Analog Display Mode 
       [0175]      FIG. 22  shows a content of control operation of the control line drive section  37  for a certain scan line in the analog display mode. In  FIG. 22 , (A) shows a waveform of gray-scale potential applied to the signal line DTL. Even in the present embodiment, polarity of voltage applied between a pixel electrode and a counter electrode is inverted on one horizontal-period cycle (1H cycle). That is, line inversion drive is performed. Therefore, in (A), the waveform of gray-scale potential applied to the signal line DTL is drawn such that a potential level is inverted on a 1H cycle. High-level potential of the gray-scale potential applied to the signal line DTL is VDD 1 , and low-level potential thereof is VSS. While (A) shows an example of a case of the largest amplitude, a potential level between VDD 1  and VSS is actually used depending on pixel gray-scale. 
         [0176]    In  FIG. 22 , (B) shows a drive waveform of the control line CTL 22 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . As shown in the figure, drive potential is controlled to the high-level potential VDD 2  only at the timing of writing gray-scale potential from the signal line DTL. 
         [0177]    (C 1 ) to (C 6 ) show drive waveforms of the control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B 1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ) respectively. The control lines CTL 21 (B 1 ), CTL 21 (R 2 ) and CTL 21 (G 2 ) are omitted to be shown. 
         [0178]    As shown in the figure, the control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B 1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ) are sequentially controlled at high-level potential VDD 2  in order of R 1 , G 1 , B 1 , R 2 , G 2  and B 2 . Periods where the respective control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B 1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ) are at the high-level potential VDD 2  are set to be not overlapped with one another. During the period where each of the control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B 1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ) is at the high-level potential VDD 2 , corresponding signal potential Vsig is applied to the signal line DTL. High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . 
         [0179]    In  FIG. 22 , (D) shows a drive waveform of each of the control lines CTL 23  and CTL 24 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . However, the control lines CTL 23  and CTL 24  are continuously controlled at the low-level potential VSS 2  in the analog display mode. 
         [0180]    (E) shows a drive waveform of the control line CTL 25 . High-level potential of drive amplitude is VDD 2 , and low-level potential thereof is VSS 2 . However, the control line CTL 25  is continuously controlled at the high-level potential VDD 2  in the analog display mode. 
       (2) Memory Display Mode 
       [0181]    The memory display mode includes operation of writing gray-scale potential from the signal line DTL to the holding capacitance Cs, and operation of refreshing gray-scale potential stored in the holding capacitance Cs within a sub pixel. The operation of writing gray-scale potential from the signal line DTL to the holding capacitance Cs is performed, for example, when display contents are changed. When gray-scale potential is written from the signal line DTL to the holding capacitance Cs, the pixel circuit performs the same operation as operation in the analog display mode. Therefore, description of the operation is omitted. 
         [0182]      FIG. 23  shows a content of control operation of the control line drive section  37  in the case of refreshing gray-scale potential stored in the holding capacitance Cs within a sub pixel.  FIG. 23  shows a relationship in drive operation in frames. 
         [0183]    In  FIG. 23 , (A 1 ) to (A 6 ) show drive waveforms of the control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B  1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ) respectively. In the present embodiment, the control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B 1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ) are applied with high-level potential in a pulsed manner on a six-frame cycle. 
         [0184]    In  FIG. 23 , (B) shows a drive waveform of each of the control lines CTL 23  and CTL 24 . The two control lines are applied with high-level potential in a pulsed manner on a one-frame cycle. (C) shows a drive waveform of the control line CTL 25 . The control line CTL 25  is applied with low-level potential in a pulsed manner on a one-frame cycle. 
         [0185]    In  FIG. 23 , (D) shows a drive waveform of counter electrode potential VCS. As shown in the figure, high-level potential and low-level potential are alternately outputted on a one-frame cycle. 
         [0186]    (E 1 ) to (E 6 ) show waveforms showing change in gray-scale potential (PIXR 1 , PIXG 1 , PIXB 1 , PIXR 2 , PIXG 2  and PIXB 2 ) to be written to the holding capacitance Cs respectively. In the figure, a waveform shown by a broken line is a drive waveform of counter electrode potential VCS. A waveform shown by a solid line is a waveform of gray-scale potential stored in each sub pixel  41 . 
         [0187]    As shown in the figure, gray-scale potential is changed with change in counter electrode potential, and a potential relationship between the counter electrode potential VCS and the gray-scale potential (PIXR 1 , PIXG 1 , PIXB 1 , PIXR 2 , PIXG 2  and PIXB 2 ) held by the holding capacitance Cs is changed on a six-frame cycle. That is, self-refresh/self-inverting operation for each color is performed on a six-frame cycle. Note that a potential relationship within the sub pixel  41  is kept from preceding self-refresh/self-inverting operation to following self-refresh/self-inverting operation. Therefore, in the present embodiment, the holding capacitance Cs has sufficient capacitance to keep certain gray-scale potential even if a refresh rate is a six-frame cycle. In the memory display mode, the control line CTL 22  is continuously controlled at low-level potential. 
         [0188]    Even in this case, detailed drive operation within one frame is the same as that in each of the described, two embodiments. Specifically, drive operation similar to drive operation of  FIG. 20  is performed. The drive operation is different from that of  FIG. 20  only in that drive waveforms similar to those of A of  FIG. 20  correspond to the control lines CTL 21 (R 1 ), CTL 21 (G 1 ), CTL 21 (B 1 ), CTL 21 (R 2 ), CTL 21 (G 2 ) and CTL 21 (B 2 ). 
       (D-3) Conclusion 
       [0189]    Even in the present embodiment, the liquid crystal display panel, which may meet both the analog display mode and the memory display mode, may be achieved. 
         [0190]    In addition, in the present embodiment, a single circuit  1  ( FIG. 3 ) may be sequentially used for six sub pixels  41 . That is, the number of circuits  1  ( FIG. 3 ) formed within two white units may be decreased from six to one. As a result, the number of elements configuring two white units within a pixel area may be further reduced. Also, when the number of elements configuring a liquid crystal display panel is reduced, a yield may be correspondingly improved. 
       (E) OTHER EMBODIMENTS 
     (E-1) Another Pixel Configuration Example 
       [0191]    In the embodiments described above, description has been made on a case where the pixel structure as shown in  FIG. 8  is used as a basic configuration. That is, description is made on a case where a thin film transistor N 17  was disposed on one of paths connecting input/output ends of two inverter circuits to one another, and latch operation of the circuit  1  was controlled through ON/OFF control of the thin film transistor N 17 . 
         [0192]    However, the drive operation may be achieved even by a pixel circuit shown in  FIG. 24 . 
         [0193]    In  FIG. 24 , LC shows a liquid crystal corresponding to a sub pixel  41 . 
         [0194]    In  FIG. 24 , Cs shows a holding capacitance holding gray-scale potential. In the present embodiment, the holding capacitance Cs is used as DRAM in the memory display mode. 
         [0195]    A thin film transistor N 11  is an active element that is controlled to be ON during writing gray-scale potential to the holding capacitance Cs, and controlled to be OFF during other periods. A control line CTL 21  is used for controlling the thin film transistor N 11 . One main electrode of the transistor N 11  is connected to wiring connected to a pixel electrode, and the other main electrode is connected to one main electrode of a thin film transistor N 12  through wiring. 
         [0196]    The thin film transistor N 12  is an active element that is controlled to be ON when gray-scale potential is written from a signal line DTL. A control line CTL 22  is used for controlling the thin film transistor N 12 . The thin film transistor N 12  corresponds to the first switch SW 1  in  FIG. 3 . One main electrode of the transistor N 12  is connected to the signal line DTL, and the other main electrode thereof is connected to the one main electrode of the thin film transistor N 11  through wiring. 
         [0197]    A thin film transistor N 13  is an active element that is controlled to be OFF when pixel potential is written from the signal line to the holding capacitance. The transistor N 13  is controlled to be ON only for a certain period immediately before end of each frame during performing internal refresh operation of the memory display mode. Gray-scale potential held by the holding capacitance Cs acting as DRAM is read by the circuit  1  ( FIG. 3 ) during a period where the thin film transistor N 13  is controlled to be ON. A control line CTL 23  is used for controlling the thin film transistor N 13 . The thin film transistor N 13  corresponds to the second switch SW 2  in  FIG. 3 . 
         [0198]    A thin film transistor N 14  is also an active element that is controlled to be OFF when pixel potential is written from the signal line to the holding capacitance. The transistor N 14  is controlled to be ON only for a certain period immediately after start of each frame during performing internal refresh operation of the memory display mode. Gray-scale potential, which has been inverted in logic within the circuit  1  ( FIG. 3 ), is written to the holding capacitance Cs during a period where the thin film transistor N 14  is controlled to be ON. A control line CTL 24  is used for controlling the thin film transistor N 14 . The thin film transistor N 14  corresponds to the third switch SW 3  in  FIG. 3 . 
         [0199]    Thin film transistors P 11  and N 15 , and a capacitance C configure the circuit  1  in  FIG. 3 . 
         [0200]    The thin film transistors P 11  and N 15  configure an inverter circuit (amplifier circuit). An input side of the inverter circuit including the thin film transistors P 11  and N 15  is connected to one main electrode of the thin film transistor N 13 . The inverter circuit may input gray-scale potential of the holding capacitance Cs when the transistor N 13  is ON. Gray-scale potential of the holding capacitance Cs is stored in the capacitance C. While the capacitance C is explicitly disposed in  FIG. 24 , wiring capacitance may be used. 
         [0201]    An output side of the inverter circuit including the thin film transistors P 11  and N 15  is connected to one main electrode of the thin film transistor N 14 . 
         [0202]    In this circuit configuration, a single inverter circuit is used to achieve a refresh function and a logic inverting function. In this circuit configuration, the three thin-film transistors P 12 , N 16  and N 17  being used in  FIG. 8  may be eliminated. Circuit area may be correspondingly reduced. 
         [0203]    Even in the pixel structure shown in  FIG. 24 , when pixel potential is written from the signal line to the capacitive element, the thin film transistors N 13  and N 14  can be controlled to be OFF. 
         [0204]    When internal refresh operation of the memory display mode is performed, drive control can be performed as shown in  FIG. 25 . 
         [0205]      FIG. 25  shows a content of control operation of the control line drive section  37  for a certain scan line when internal refresh operation of the memory display mode is performed. 
         [0206]    In  FIG. 25 , a preceding frame is shown as frame N, and a following frame is shown as frame N+1. 
         [0207]    In  FIG. 25 , (A) shows a drive waveform of the control line CTL 21 . As shown in the figure, the control line CTL 21  is controlled at high-level potential VDD 2  for a certain period from a point immediately before end of the frame N to a point immediately after start of the frame N+1. 
         [0208]    (B) shows a drive waveform of the control line CTL 23 . As shown in the figure, the control line CTL 23  is controlled at the high-level potential VDD 2  only for a certain period immediately before end of each frame. Gray-scale potential (PIX) read from the holding capacitance Cs is stored into the capacitance C within the circuit  1  ( FIG. 3 ) during applying the high-level potential VDD 2 . 
         [0209]    Inverted output of the gray-scale potential (PIX) is provided at an output end of the inverter circuit, and the gray-scale potential is inverted in logic at that time. Moreover, output amplitude of the gray-scale potential is changed into high-level potential VDD or low-level potential VSS. That is, self-refresh operation and self-inverting operation are performed. Again, the self-refresh operation is performed without charging or discharging the signal line DTL. 
         [0210]    In  FIG. 25 , (C) shows a drive waveform of the control line CTL 24 . As shown in the figure, the control line CTL 24  is controlled at the high-level potential VDD 2  only for a certain period immediately after start of each frame. An output end of the inverter circuit is electrically connected to the holding capacitance Cs during applying the high-level potential VDD 2 , so that the gray-scale potential (PIX) inverted in logic is written to the holding capacitance. 
         [0211]    (D) shows a waveform showing change in counter electrode potential VCS. As shown in the figure, a potential level is inverted in frames. 
       (E-2) Product Example (Electronic Device) 
       [0212]    The described technique of applying drive voltage is distributed not only in a form of a liquid crystal panel, but also in a form of a product in which the liquid crystal panel is mounted on each of electronic devices. Hereinafter, an example where the liquid crystal panel is mounted on an electronic device is shown. 
         [0213]      FIG. 26  shows a conceptual configuration example of an electronic device  51 . The electronic device  51  includes a liquid crystal panel  53  using the technique of applying drive voltage, a system control section  55 , and an operation input section  57 . A content of processing executed in the system control section  55  is different depending on a product form of the electronic device  51 . The operation input section  57  is a device receiving operation input to the system control section  55 . For example, a switch, a button or another mechanical interface, or a graphic interface is used for the operation input section  57 . 
         [0214]    The electronic device  51  is not limited to a device in a particular field as long as the device has a function of displaying a picture or a video image being generated within the device or being externally inputted. 
         [0215]      FIG. 27  shows an example of outside appearance when another electronic device is a television receiver. A display screen  67  including a front panel  63 , a filter glass  65  and the like is disposed in front of a housing of a television receiver  61 . 
         [0216]    This type of electronic device  51 , for example, may be a digital camera.  FIGS. 28A and 28B  show an example of outside appearance of a digital camera  71  respectively.  FIG. 28A  shows an outside example of the camera  71  on a front side (object side), and  FIG. 28B  shows an outside example of the camera  71  on a back side (photographer side). The digital camera  71  includes a protective cover  73 , an imaging lens section  75 , a display screen  77 , a control switch  79 , and a shutter button  81 . 
         [0217]    Moreover, this type of electronic device  51 , for example, may be a video camera.  FIG. 29  shows an example of outside appearance of a video camera  91 . 
         [0218]    The video camera  91  includes an imaging lens  95  forming an image of an object in front of a body  93 , a photographing start/stop switch  97 , and a display screen  99 . 
         [0219]    Moreover, this type of electronic device  51 , for example, may be a mobile terminal device.  FIGS. 30A and 30B  show an example of outside appearance of a mobile phone  101  as the mobile terminal device. The mobile phone  101  shown in  FIGS. 30A and 30B  is of folding type.  FIG. 30A  shows an outside example of the mobile phone where a housing is opened, and  FIG. 30B  shows an outside example of the mobile phone where a housing is closed. 
         [0220]    The mobile phone  101  includes an upper housing  103 , a lower housing  105 , a connection (hinge in this example)  107 , a display screen  109 , an auxiliary display screen  111 , a picture light  113 , and an imaging lens  115 . 
         [0221]    Moreover, this type of electronic device  51 , for example, may be a computer.  FIG. 31  shows an example of outside appearance of a notebook computer  121 . 
         [0222]    The notebook computer  121  includes a lower housing  123 , an upper housing  125 , a keyboard  127 , and a display screen  129 . 
         [0223]    In addition, this type of electronic device  51  may also be an audio player, a game machine, an electronic book, an electronic dictionary and the like. 
       (E-3) Others 
       [0224]    Various modifications or alterations of the embodiments described above may be considered within a scope of the gist of the invention. Moreover, various modifications and applications of the embodiments are considered to be created based on the description of the specification, or various combinations of them may be considered. 
         [0225]    Therefore, it should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof. 
         [0226]    The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2008-321652 filed in the Japan Patent Office on Dec. 17, 2008, the entire content of which is hereby incorporated by reference.