Abstract:
An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a precise resistor value. At least two semiconductor resistor device structures may be connected in series or in parallel configuration through the intermediary of one or more fuse devices that may be blown to achieve a desired total resistance value.

Description:
BACKGROUND OF INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates generally to electronic devices and specifically, is directed to the manufacture of compact, precision semiconductor on-chip resistors and precision resistor array devices having improved properties.  
         [0003]     2. Description of the Prior Art  
         [0004]     Conventional on-chip resistors made of TaN or polysilicon are either placed within the multi-level Back End of Line (BEOL) interconnect layers or placed on the surface of a Si substrate. For TaN precision on-chip resistors which are placed within the metal levels, heat dissipation, thermally induced electromigration (EM) of neighboring interconnect wires, and the space occupancy are all of some concern. For polysilicon resistors which are placed on the surface of the Si substrate, precision control of resistance (control of doping level), doping uniformity, resistance variation due to temperature, and space occupancy are also of serious concerns. Therefore, there is a need to develop a compact precision resistor configuration with good thermal dissipation and less EM impacts on BEOL interconnects.  
         [0005]     It would be highly desirable to provide a new on-chip, ultra-compact, and programmable resistor configuration and a method of forming such on-chip, ultra-compact, and programmable resistors, e.g., in CMOS technology.  
       SUMMARY OF INVENTION  
       [0006]     According to the invention, there is provided an on-chip, ultra-compact, and programmable resistor device structure and a method of fabricating such programmable resistor structure.  
         [0007]     In a first embodiment of the invention there is provided a semiconductor resistor device structure and method of manufacture. According to this first embodiment, a semiconductor resistor device element comprises a single trench buried in a semiconductor substrate, the trench filled with a conductive material, e.g., TaN or PolySilicon material, and lined with an insulator material.  
         [0008]     Further to the first embodiment, there is provided a semiconductor resistor device and method of manufacture, wherein a conductive material, e.g., TaN or PolySilicon material, is buried inside each trench of a series of trenches that are connected in a unique way to form a resistor sub-array on a substrate, the array having a precise resistor value. A thin dielectric material is formed between the TaN or PolySilicon material and the substrate to serve as an insulation layer. Resistor sub-arrays may be connected through a fuse either in series or in parallel to form a programmable precision resistor array.  
         [0009]     According to a second embodiment, a semiconductor resistor device element comprises a single trench buried in a semiconductor substrate, the trench including a dielectric material lining each side and bottom of the trench, and including a conductive material layer formed within the trench having a bottom and two side portions of the trench, the trench further filled with a dielectric material.  
         [0010]     Further to the second embodiment of the invention, there is provided a semiconductor resistor device structure and method of manufacture, wherein a conductive film of TaN or PolySilicon material, for example, is formed buried inside each trench of a series of trenches that are connected to form a resistor sub-array on a substrate having a precise resistor value. A thin dielectric material is formed between the TaN or PolySilicon conductive film and the substrate to serve as an insulation layer.  
         [0011]     Resistor sub-arrays according to the first and second embodiments may be connected through a fuse either in series or in parallel to form a programmable precision resistor array.  
         [0012]     In each of the first and second embodiments, each column and row of the resistor array is separated by isolation (such as trench isolation or STI) or local oxidation of silicon (LOCOS) to minimize noise. The whole substrate serves as a good heat sink for thermal dissipation. The whole resistor structure is ultra-compact, taking up a small surface area of space. Further, utilizing the trench array concept of the invention, blocks of arrays may be connected through fuses that may be blown to form a resultant resistor structure of a very precise resistance value.  
         [0013]     Advantageously, the process methods implemented in the production of the precision resistors and resistor arrays of the invention are fully compatible with current CMOS processes and only very limited extra steps are required to fabricate such resistors. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0014]     The objects, features and advantages of the present invention will become apparent to one skilled in the art, in view of the following detailed description taken in combination with the attached drawings in which:  
         [0015]      FIG. 1  illustrates a cross-sectional view of a trench type buried resistor according to a first embodiment of the invention;  
         [0016]      FIG. 2  illustrates a top view of a trench type buried resistor array having resistive elements formed in accordance with the embodiment depicted in  FIG. 1 ;  
         [0017]      FIG. 3  illustrates a cross-sectional view of a trench type buried resistor according to a second embodiment of the invention;  
         [0018]      FIG. 4  illustrates a top view of a trench type buried resistor array having resistive elements formed in accordance with the embodiment depicted in  FIG. 3 ;  
         [0019]     FIGS.  5 ( a )- 5 ( d ) illustrate various process steps implemented in the formation of the deep trench buried resistor of  FIG. 3 ; and,  
         [0020]      FIG. 6  illustrates a programmable trench resistor comprising sub-banks of buried trench type resistors according to the invention. 
     
    
     DETAILED DESCRIPTION  
       [0021]      FIG. 1  illustrates a cross-sectional view of a trench type buried resistor  10  according to a first embodiment of the invention. As shown in  FIG. 1 , the trench buried type resistor includes a series of trenches  12   a ,  12   b , . . . ,  12   n  formed in a substrate  15 , aligned, for example, in a row, with each trench separated by a dielectric region  16 , e.g., an oxide. Each trench  12   a ,  12   b , . . . ,  12   n  is filled with a conductor material  13  such as Tantalum Nitride (TaN) or Polysilicon, and each trench includes a buried plate bottom connective portion  20   a ,  20   b , . . . ,  20   n . As shown in  FIG. 1 , between alternating adjacent first trenches, e.g., trenches  12   a ,  12   b  and  12   c ,  12   d , etc., there are formed ion implantation bands  25  comprising ion implanted doped substrate material that connect these adjacent trenches in alternating fashion. Likewise, between alternating adjacent second trenches  12   b ,  12   c  and  12   d ,  12   e  etc., there are formed top surface resistive connective portions  30  that connect these adjacent trenches in alternating fashion as shown in  FIG. 1 . The resultant structure of device  10  shown in  FIG. 1  is a series of connected individual buried trench type resistor elements that form a buried trench type resistor chain having a resistor value. As will be described, each individual connected resistor portion has a resistive value (in ohms) that varies according to the dimensions of the trench and the type of conductive material used to fill the trench. It is understood that the formed chain comprising the plurality of connected trench resistor portions may be tailored to form a resistor device structure  10  according to a desired resistive value. More particularly, as shown in  FIG. 1 , each trench  12   a ,  12   b , . . . ,  12   n  includes a bottom portion comprising a buried plate contact  20  formed of a conductive material, and includes sidewalls in an upper portion lined with a dielectric material, e.g., an oxide, nitride or oxynitride to form a collar  14 . Examples of dielectric materials forming a trench collar include SiN, SiO 2  or like dielectric material. As will be explained in greater detail herein, after forming the trenches with each bottom plate connector  20 , and after forming the alternative top surface connection portions, the doped ion implantation bands  25  that connect alternating adjacent first trenches, e.g., trenches  12   a ,  12   b  and  12   c ,  12   d , etc., are formed by ion implantation techniques that connect every other trench implementing a self-aligned method. For a particular resistor design, n+ dopants may be ion implanted.  
         [0022]     A method for forming the trench type buried resistor  10  according to the first embodiment of the invention includes the following process steps: First, a reactive ion etch (RIE) technique is implemented for forming a series of trenches  12   a ,  12   b , . . . ,  12   n  in a substrate such as Silicon, SiGe, GaAs, etc. Each trench may range in depth between about 1.0 μm to 7.0 μm below the substrate surface, for example, and may be of a width and a length ranging between 0.1 μm and 10 μm commensurate with current CMOS fabrication techniques. The shape of the top trench surface could be oval, rectangular, circular, square, etc. The distance between adjacent trenches may further range between 0.1 μm and 10 μm. Each trench in the series is separated by an isolation  16  (such as a shallow trench isolation or STI) or local oxidation of silicon (LOCOS) to minimize noise as shown in  FIG. 1 . After the formation of the trenches and isolation regions, an Arsenic silicon glass (ASG) or gas phase doping (GPD) process is implemented to form trench bottom buried plate contacts  20   a , . . . ,  20   n  in accordance with well-known processes. In one embodiment, the buried plate contact is 800 Å thick arsenic doped Silicon glass. Then, a dielectric collar  14  is formed at sidewalls of a portion of each trench above the buried plate contact and comprises an oxide, SiN, SiO 2 , or other low-k or high-k dielectric material. A conventional process may be used to form the dielectric collar to line the inner sidewalls of the upper portions of each trench. After lining each trench sidewall with a dielectric collar, a deposition, e.g., chemical vapor deposition (CVD) or like deposition technique, e.g., PVD, MBE, thermal evaporation, e-beam, etc., may be used to fill the trench with conductive materials including, TaN, Polysilicon material, or other conductive material such as Ta, W, Ti, Cu, Al, TiN, TaN/TiN bilayer, Pt, alloys of pure metals, etc. The TaN or Polysilicon trench fill material is then subject to a chemical-mechanical polish (CMP) technique for planarizing the top trench surface portions. Then, implementing a mask and conventional deposition techniques, TaN, Polysilicon, or like conductive material used to form the resistor is deposited at the surface locations to form the top surface connections  30  between alternating second adjacent trenches such as shown in  FIG. 1 . Finally, the self-aligned trench bottom buried plate ion implantation band connections  25  that connect alternating adjacent first trenches such as shown in  FIG. 1 , are formed by known ion implantation techniques. Known ion implantation techniques may be utilized that are tailored according to the type of dopant utilized which may comprise n+ dopant material such as arsenic, phosphorus or, p+ dopant material such as boron. In one embodiment, the connective ion implantation band is about 0.25 μm above the trench bottom. As known, the depth of connective ion implantation band determines the ion implantation energies. As an example, for 1.75 μm deep phosphorus doped connective band with doping concentration equal to 1.0e18 cm −3 , the ion implantation parameters are: 1000 keV energy and 4.0e13 cm −2  dose.  
         [0023]     According to the first embodiment of the buried trench resistor, when either TaN or polySi is used to fill all the trench, the approximate resistance value per trench, R (Trench) , is calculated according to equation 1) as: 
 
 R   (Trench) =ρ (TaN or polySi)   *h/A   1) 
 
         [0024]     For both TaN and polySi fill cases, the rho (ρ) could be varied. For example, assuming a typical ρ (TaN) =3.0 ohm-μm and a trench dimension h=2.0 μm, D (diameter)=0.5, and A=pi*D 2 /4 for a cylinder type trench (top trench surface is a circle), the R (TaN)  is approximately 30.56 ohm (Ω). A typical ρ (polySi) =9.0 ohm-μm to 15.0 ohm-μm.  
         [0025]      FIG. 2  illustrates a top view of an example trench type buried resistor array  100  including resistors formed according to the embodiment depicted in  FIG. 1 . In the array  100  of  FIG. 2 , multiple rows, e.g., four (4) rows  101   a , . . . , 101   d , each comprise a chain of trench type resistor elements, e.g., seven (7) trenches  12   a - 12   g  in row  101   a , are formed according to the method herein described. Bottom plate elements (not shown) of resistive trenches  12   g  and  12   h , for instance, may be connected to form a series connection, so that the whole array  100  comprises a chain connection of resistive elements. Other configurations are possible with chains of buried trench resistor elements of the array connected in parallel. As will be described in greater detail herein, by connecting fuse devices at specific locations in the trench type buried resistor array of  FIG. 2 , or between connected trench type buried resistor arrays, and judiciously destroying one or more fuses, a resistor having a precise value may be programmed.  
         [0026]      FIG. 3  illustrates a cross-sectional view of a trench type buried resistor  50  according to a second embodiment of the invention. As shown in  FIG. 3 , the trench buried type resistor includes a series of trenches  52   a ,  52   b , . . . ,  52   n  formed in a substrate  55 , aligned, for example, in a row, with each trench separated by a dielectric region  56 , e.g., an oxide. Each trench  52   a ,  52   b , . . . ,  52   n  includes a buried thin layer  53  of conductive material such as TaN or Polysilicon, shaped in conformance with the shape of the trench and having side  53   a,b  and bottom  53   c  portions. This thin conductive material layer may range between 50 Å and 500 Å in thickness depending upon the desired resistance, e.g., as dictated by circuit requirements. Between each trench  52   a ,  52   b , . . . ,  52   n  there is formed a top surface resistive connector portion  60  that connects each buried thin layer  53  (conductive layer sidewalls  53   a,b ) of a trench with the buried thin conductive layer  53  of an adjacent trench, thus forming a series connection of individual connected resistor portions that form a resistor chain. The resultant structure of device  50  shown in  FIG. 3  is a series connection of individual connected buried trench type resistors that form a buried trench type resistor chain having a resistor value. As will be described, each individual connected resistor portion has a resistive value (in ohms) that varies according to the dimensions of the trench and the thickness and type of conductive buried thin layer  53  within the trench. Each individual connected resistor portion has a determined resistive value and a formed chain of a plurality of connected trench resistor portions may be tailored to form a resistor device structure  50  according to a desired resistive value. More particularly, each trench  52   a ,  52   b , . . . ,  52   n  includes a dielectric material  54  formed at the bottom and on the sidewalls to surround the bottom and side portions of the thin conductive material layer  53 , the rest of the trench including a dielectric material filler such as an oxide, nitride or oxynitride. Example dielectric materials include SiN, SiO 2  or like dielectric material.  
         [0027]     A method for forming the trench type buried resistor  50  according to the second embodiment of the invention includes the following process steps: First, a reactive ion etch (RIE) technique is implemented for forming a series of trenches  52   a ,  52   b , . . . ,  52   n  in a substrate  55  such as Silicon, SiGe, GaAs, etc. Use of a substrate etch process that purposely tapers the trench sidewall can be useful both for removing the TaN by RIE, and to allow some kinds of PVD processes to deposit the TaN or other conductive films. Each trench may range in depth from 1.0 μm to 7.0 μm below the substrate surface, and may be of a width and a length between 0.1 μm and 10 μm commensurate with current CMOS fabrication techniques. The distance between adjacent trenches ranges between 0.1 μm and 10 μm. After the formation of the trenches, the dielectric collar  54  comprising, for instance, an oxide, SiN, SiO 2 , or other low-k or high-k dielectric material is formed at sidewalls and bottom portion of each trench. A conventional process, e.g., thermal oxidation, may be used to form the dielectric collar  54  that lines the inner sidewalls of the upper portions of each trench. After lining each trench sidewall and trench bottom with the dielectric, a deposition, e.g., chemical vapor deposition (CVD) or like deposition technique is used to form the buried thin layer  53  of conductive material such as TaN, Polysilicon material, or other conductive material inside the trench that conforms to the structure of the formed collar at the bottom, front, back and sidewalls. However, as will be described in greater detail, the front and back portions of the buried thin layer  53  are removed in a later process step. Next, a further step is performed to fill the trench with a dielectric material  57  such as an oxide, SiN, SiO 2 , or other low-k or high-k dielectric material.  
         [0028]     As mentioned, after the step of depositing a conductive material layer inside the trench that conforms to the structure of the formed collar at the bottom, front, back and sidewalls, it is necessary to remove the front and back portions. This is accomplished by an additional selective etch step now described in connection with FIGS.  5 ( a )- 5 ( d ). As shown in  FIG. 5 ( a ), there is depicted a top view of a trench  52   a  having a dielectric collar  54  (e.g., an oxide), a conforming buried thin conductive material layer  53  inside the trench that conforms to the structure of the trench having front, back and sidewall portion and a filled dielectric material  57 .  FIG. 5 ( a ) additionally illustrates the placement of a wing mask  75  that is used in the selective etch process step to remove the front and back conductive material layer portions  53   d ,  53   e . After placement of the wing mask  75 , which is smaller enough than the trench width “w” so that the oxide filling the trench is exposed, RIE etch the oxide away so that the TaN is exposed all the way to the bottom of the trench. Then either a wet etch or a RIE etch could be used to remove the TaN from the exposed trench wall, leaving the TaN protected by the masked area. For the wet etch, an etchant selective to TaN (or PolySilicon) is applied to remove the front and back buried thin conductive layer portions  53   d ,  53   e  with the resulting structure showing the remaining gap  58  as shown in  FIG. 5 ( b ) and a cross-sectional view provided in  FIG. 5 ( c ). As known to skilled artisans a wet etch may be performed at this step using etchants such as H 2 :O:HF:HNO 3 =4:1:5. For the reactive ion etching (RIE), reactive gases such as Cl 2 , CF 4 , and BCl 3  with inductively coupled plasma could be used to remove TaN. A top view of the resultant trench structure  52   a  is illustrated in  FIG. 5 ( d ) showing the gap  58  left in a trench after the TaN (or PolySilicon) material wet etch and illustrating a potential TaN (or PolySilicon) film under cut region  59  due to the wet etch process step. In a final step, the remaining unfilled portion is filled with a dielectric material (e.g., oxide, nitride or oxynitride) and a CMP may be performed in a final step.  
         [0029]     According to the second embodiment of the buried trench resistor  50 , when either TaN or polySi thin film is buried in the trench (after implementing the wing mask/etch step), the approximate resistance value per trench, R (Trench) , is calculated according to equation 2) as: 
 
 R   (Trench) =ρ(TaN or polySi)*(2 h+w )/( tL )   2) 
 
         [0030]     where “h” is the trench height, “w” is the trench width, “t” is the conductive film thickness, and “L” is the wing mask width. The rho (ρ) for TaN and polySi may be varied (e.g., for polySi, ρ may range between 3.0 ohm-μm 70 ohm-μm). Assuming a TaN ρ=3.0 ohm-μm and a trench height h=2.0 μm, trench width w=2.0 μm, TaN film thickness t=500 Å, and wing mask width L=1.0 μm, R(TaN) is approximately 600 ohm (Ω). As shown in equation 2, the value of single resistor can be varied to suit the technology by varying ρ, L, w, h, and t.  
         [0031]      FIG. 4  illustrates a top view of an example trench type buried resistor array  500  including resistors formed according to the embodiment depicted in  FIG. 3 . In the resistor array  500  of  FIG. 4 , multiple rows, e.g., four (4) rows  501   a , . . . ,  501   d , each comprise a chain of resistor elements, e.g., six (6) trenches  52   a - 52   g , are formed according to the method herein described. Selected top surface connections  60  may be connected to form the series connection of trench resistor elements so that the whole array comprises a chain connection of trench type resistive elements. Other configurations are possible with chains of buried trench resistor elements of the array connected in parallel. As will be described in greater detail herein, by connecting fuse devices at specific locations in the trench type buried resistor array of  FIG. 4 , or between connected trench type buried resistor arrays, and judiciously destroying one or more fuses, a resistor having a precise value may be programmed.  
         [0032]     According to a further embodiment of the invention, both of the buried trench resistor arrays of  FIGS. 2 and 4  may be connected in the form of a “trench resistor bank” to further improve the flexibility and precision of a semiconductor device.  FIG. 6  illustrates a programmable trench resistor comprising sub-banks of buried trench type resistors according to the invention. As shown in  FIG. 6 , precision buried trench type resistors as shown in  FIG. 1  or  3 , or trench type precision resistor array such as shown in  FIG. 2  or  4  form resistor sub-banks  80 ,  82  and  84  that may be connected in series through respective fuse devices  180 ,  182  and  184 . Similarly, precision buried trench type resistors as shown in  FIG. 1  or  3 , or trench type precision resistor array such as shown in  FIG. 2  or  4  form precision resistor sub-banks  90 ,  92  and  94  that may be connected in parallel. The parallel connection of precision resistor sub-banks  90 ,  92  and  94  are connected through respective fuse devices  190   a,b  and  192   a,b  as shown in  FIG. 6 . According to the invention, a total resistance of a formed resistor device may be programmed by implementing well-known techniques for blowing one or more fuse devices to add or subtract resistance, for example, by deleting serial connection of a trench resistor sub-bank (e.g.,  80 ,  82 ,  84 ) or parallel connection of a trench resistor sub-bank (e.g.,  92 ,  94 ).  
         [0033]     Advantageously, utilizing a buried trench approach of the invention, the formed resistor device is ultra-compact and does not need a large amount of surface area. For example, a planar resistor with 1F*1F area has about 10× larger surface area than the trench resistor with surface area of 0.3F*0.3F and 1.5F depth. By placing TaN material inside of the substrate, heat dissipation is significantly improved and no direct thermal impact of EM performance of top BEOL wires exists.  
         [0034]     While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.