Abstract:
A method and apparatus are provided for conveying low level signals from a first circuit card to a second circuit card. The low level signals are encoded using a simple integer value N, and the low level signals are then communicated to the second circuit card as a sequence of N alternating values. A binary counter is used to generate the sequence of alternating values using the output of a single pin of the counter, although a second pin may be used to generate a clock signal. The invention allows all low level signals to be communicated in a robust yet simple way, minimizing the chance of spurious signals being generated upon hot insertion or extraction without complicated ad hoc solutions.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to card-to-card signaling, and more particularly low level signaling during hot insertion and removal of circuit cards. 
       BACKGROUND OF THE INVENTION 
       [0002]    Systems designed for hot insertion or removal of hardware must deal with a number of issues in order to prevent disruptions or errors from occurring due to freshly inserted or removed hardware. Fundamental electrical problems arise during hot insertion or removal, such as instantaneous load changes on the system power supply or instantaneous load changes on interconnected signals between circuit cards. Interconnected signals may also be disrupted by mechanical chattering when a circuit card&#39;s mating connector makes or breaks contact with the system. Signal disruption may also arise from the indeterministic behaviour of the electrical device driving or receiving the interconnected signal when its power supply is ramping-up during card insertion or when its power supply subsides during card removal. In addition, hot insertion or removal of cards may give rise to spurious behaviour on signals leading to their misinterpretation. 
         [0003]    Such unpredictable signal behaviour is undesirable and can lead to system fault conditions, especially for low level signals. Low level signals are regular digital signals that are not encoded or protected in any way, and are used for basic functions such as card resets, circuit enables, and arbitration. Many solutions attempt to deal with each of the individual possible causes of signal disruption. For example, one or more recessed connector pins can be used to indicate that a card is fully inserted by detecting latent mating ground connections. The resultant signal acts as a qualifier for other signals or electrical circuits, essentially indicating that the card is fully inserted. This solution deals with mechanical connection problems. Another solution is to carefully select particular electrical circuits for driving or receiving interconnected signals. 
         [0004]    While some of these solutions appear to be successful at addressing all the issues, problems often arise given the number of variables and the unpredictable behaviour of signals during transient states. Other solutions only address some of the issues, leaving other issues to chance. 
         [0005]    A method which added integrity and robustness to the behaviour of low level signals in general, without being limited to particular signals or problems, would reduce spurious signals and allow more predictable behaviour of systems. Given the common nature of low level signals, such a method should also be simple and inexpensive. 
       SUMMARY OF THE INVENTION 
       [0006]    In accordance with one aspect of the invention, a method of transmitting low-level signals from a first circuit card to a second circuit card is provided. An integer N is determined which corresponds to a low-level signal or combination of low-level signals to be transmitted, the integer N uniquely identifying the low-level signal or combination of low-level signals. A data sequence is transmitted from the first circuit card to the second circuit card, the data sequence being a series of N alternating values. A termination sequence is transmitted from the first circuit card to the second circuit card. The data sequence may be values of a bit from a binary counter. 
         [0007]    In accordance with another aspect of the invention, a circuit card is provided. The circuit card includes a controlling entity for determining that a low-level signal or a combination of low-level signals is to be sent to a second circuit card. The circuit card also includes an encoder for transmitting a digital data signal to the second circuit card, the data signal including a data sequence and a termination sequence. The data sequence is a series of N alternating values where N is an integer uniquely identifying the low-level signal or combination of low-level signals. 
         [0008]    In according with yet another aspect of the invention, a circuit card is provided which includes a receiving entity for receiving a low-level signal or combination of low-level signals from a second circuit card. The circuit card also includes a decoder for detecting and receiving a data signal from the second circuit card, the data signal including a data sequence and a termination sequence. The data sequence is a series of N alternating values, N being an integer which uniquely identifies the low-level signal or combination of low-level signals. The decoder identifies the low-level signal or combination of low-level signals to the receiving entity based on the value of N. 
         [0009]    The methods of the invention may be stored as processing instructions on computer-readable media. 
         [0010]    The methods and apparatus of the present invention provide a simple solution for avoiding spurious signals upon hot insertion and removal of circuit cards, and provide robustness in that any low level signals which are legitimately transmitted between cards are correctly delivered. By using an encoding technique for low level signals, it is highly improbable for a given signaling condition to be inadvertently replicated during the various error conditions and noise which can occur during transient states. The use of encoding also allows a combination of signals to be communicated over a 2-wire interface as a single coded sequence and the total number of signals required is reduced, which reduces the overall susceptibility to spurious signal problems. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    The features and advantages of the invention will become more apparent from the following detailed description of the preferred embodiment(s) with reference to the attached figures, wherein: 
           [0012]      FIG. 1  is a diagram of communication components of two circuit cards exchanging low level signals according to one embodiment of the invention; 
           [0013]      FIG. 2  is a flowchart of a method carried out by the transmit encoder of  FIG. 1  to send low level signals to the second circuit card according to one embodiment of the invention; and 
           [0014]      FIG. 3  is a diagram of two signals sent by the first circuit card of  FIG. 1  according to one embodiment of the invention. 
       
    
    
       [0015]    It will be noted that in the attached figures, like features bear similar labels. 
       DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0016]    Referring to  FIG. 1 , communication components of two circuit cards which exchange low level signals is shown according to one embodiment of the invention. A first circuit card  10  sends low level signals to a second circuit card  12 . The first circuit card  10  includes a controlling entity  14  and a transmit encoder  16 . The second circuit card  12  includes a receiving entity  18  and a receive decoder  20 . The receive decoder  20  acts as a receiver for low level signals conveyed from the transmit encoder. The transmit encoder  16  includes a first binary counter  22  and the receive decoder  20  includes a second binary counter  24 . 
         [0017]    Referring to  FIG. 2 , a flowchart of a method carried out by the transmit encoder  16  to send low level signals to the second circuit card  12  is shown according to one embodiment of the invention. At step  30  the encoder  16  receives a command from the controlling entity  14 . The command is generally instructions to transmit a single low level signal or a combination of low level signals. At step  32  the encoder  16  attempts to determine a value N corresponding to the command received at step  30  is a valid command. The value of N is a parameter that will be used in encoding the command when it is sent to the second circuit card. The encoder  16  may determine the value N corresponding to the command in any way, such as hardware encoding relating a numerical identifier of the command with the value N. Each different type of command which can be received from the controlling entity has a unique corresponding value of N. Or, more accurately since some commands may not be recognizable by the encoder  16 , each different value of N which can be determined by the encoder  16  uniquely identifies a corresponding command. In this way each command can be encoded using a simple integer value N. 
         [0018]    If the encoder  16  is unable to determine a value of N for the command at step  32 , then the encoder takes no further action and ends treatment of the command at step  34 . In one alternative the encoder  16  may signal at step  34  to the controlling entity  14  that the command was not recognized. If the encoder  16  is able to determine a value of N at step  32 , then the encoder  16  can encode the command. At step  38  the encoder  16  transmits an introduction sequence to the second circuit card  12 . At step  40  the encoder  16  transmits a data sequence to the second circuit card  12 , the data sequence consisting of N consecutive bits of alternating value. At step  42  the encoder  16  transmits a termination sequence to the second circuit card  12 . The introduction sequence, data sequence, and termination sequence are transmitted sequentially as a serial data signal. 
         [0019]    Once the encoder  16  has transmitted the data signal, the encoder  16  may acknowledge to the controlling entity  14  at step  44  that the encoded command was transmitted to the second circuit card. The encoder  16  may accomplish this, for example, by automatically clearing the register bit that was used to communicate the command. 
         [0020]    Returning to  FIG. 1 , the method described above with reference to  FIG. 2  will be illustrated with reference to communication components of the two circuit cards  10  and  12 . A particular implementation of transmission of the data signal will also be illustrated. 
         [0021]    The controlling entity  14  sends a command signal cmd_ 1  to the transmit encoder  16 . The command signal cmd_ 1  may be in any form, such as a hardware indication or a change to a software configurable register (step  30  of  FIG. 2 ). The transmit encoder  16  determines a number of cycles N corresponding to the command signal (step  32  of  FIG. 2 ). 
         [0022]    The transmit encoder  16  communicates the command to the receive decoder  20  using two serial signals over two pins of the first binary counter  22 , for example the pins Q 0  and Q 1 . The binary counter  22  counts to an arbitrary number having a value of at least 2 N+8−1. The lowest bit is transmitted to the receive decoder  20  over the first pin Q 0  and is used as a clock signal. The binary counter  22  counts at a frequency determined by an arbitrary clock, such as the system clock of the first circuit card. For example, the binary counter  22  could toggle its count at half the frequency of the system clock. The clock signal generated by the lowest bit of the binary counter  22  is transmitted to a clock input of the second binary counter  24  on the second circuit card  12 . 
         [0023]    The second lowest bit of the binary counter  22  is transmitted to the receive decoder  20  using the second pin Q 1  and is used as a data signal. The transmit encoder  16  masks the output of the second pin Q 1  in order to generate an introduction sequence of “0”s for the duration of four or more consecutive bit counts (step  38  of  FIG. 2 ). The transmit encoder  16  then halts masking the output of the second pin Q 1  and allows transmission of the alternating data pattern over the second pin Q 1  for a duration of 2 N bit counts (step  40  of FIG.  2 ). The transmit encoder  16  then masks the output of the second pin Q 1  in order to generate a terminating sequence of “0”s for the duration of four or more consecutive bit counts (step  42  of  FIG. 2 ). The transmit encoder  16  may then send a confirmation signal cmd_done back to the controlling entity, confirming that the command has been transmitted to the second circuit card  12  (step  44  of  FIG. 2 ). In the current embodiment, this is achieved by automatically clearing the register bit that was used to communicate the command. 
         [0024]    The effect of this is shown in  FIG. 3 . The output of the lowest bit of the binary counter  22  is an alternating series of “1”s and “0”s and can be used as a clock signal  50 . The output of the second lowest bit of the binary counter  22  is used as a data signal  52 , and consists of an introduction sequence  54 , a data sequence  56 , and a termination sequence  58 . If viewed in terms of the frequency of the clock signal  50  rather than in terms of the bit counting, the introduction sequence  54  consists of two consecutive “0”s, the data sequence  56  consists of N alternative “1”s and “0”s, and the terminating sequence  58  consists of two consecutive “0”s. 
         [0025]    The receive decoder  20  monitors the data signal  52  and the clock signal  50  received over its corresponding data and clock inputs. The reception of two or more consecutive “0”s on the data signal  52  with respect to the sampling edge on the clock signal  50  places the receiver in an initialized state with its binary counter  24  set to zero. Upon detection of an alternating pattern on the data signal  52 , the receiver begins to increment the second binary counter  24 . The second binary counter  24  counts and continues to increment for every alternating bit on the data signal  52  for which a sampling edge is provided on the clock signal  50 . When an alternating pattern is detected as no longer present on the data signal  52 , that is two or more consecutive “0”s or two or more consecutive “1”s are detected, the receiver determines the number N to which the second binary counter  24  counted. The receive decoder  20  determines the command corresponding to the number of cycles N, the command corresponding to the command sent from the controlling entity  14  to the transmit encoder  16 . The receive decoder  20  then transmits this command to the receiving entity  18  as sig_ 1 . If however the receive decoder  20  can not associate a command with the number of cycles N, then the receive decoder takes no action. In an alternate embodiment, the receive decoder  20  provides feedback to the controlling entity  14  if no association with a command and the number of cycles N can be made. 
         [0026]    If the controlling entity  14  has a different or an additional low level signal to send to the receiving entity  18 , a different command signal cmd_ 2  is sent to the transmit encoder  16 . The transmit encoder  16  determines the value of N 2  corresponding to the command signal cmd_ 2 , which will be different from the value N for the command signal cmd_ 1 , and sends an introduction sequence, a data sequence of length 2 N 2  bits (or of length N 2  in the reference frequency of the clock signal), and a termination sequence to the receive decoder  20 . The receive decoder detects the sequence of N 2  alternating “1”s and “0”s, determines the command corresponding to the number N 2 , and transmits this command sig_ 2  to the receiving entity  18 . 
         [0027]    The invention has been described using the lowest bit of the first binary counter  22  as the clock signal  50 . Alternatively, a separate clock signal shared by the transmit encoder  16  and the receive decoder  20  could be used. In such an embodiment, the output of the lowest bit of the first binary counter  22  is used as the data signal  52  as long as the sequence of outputs is synchronized with the clock signal. Since it is the lowest bit that is being used as the data signal, and hence to indicate N, the transmit encoder  16  need only transmit the output of the lowest pin of the binary counter  22  for a count of at least (N+4−1): two bits for the introduction sequence, N bits for the data sequence, and two bits for the termination sequence. However this may not be advantageous enough to warrant synchronization with an independent clock signal. 
         [0028]    The invention has been described using an introduction code of two bits (with reference to the frequency of the clock signal) and a termination code of two bits (with reference to the frequency of the clock signal). Different introduction and termination sequences could be used, such as a different number of consecutive “0”s, or using consecutive “1”s instead of “0”s. In general, the invention finds advantage in transmitting a low level signal as a digital sequence consisting of an introduction sequence, a data sequence of N alternating values where N indicates the type of the low level signal or combination of low level signals, and a termination sequence which indicates that the data sequence is over. The introduction sequence and termination sequence can also be collapsed into a single sequence if deemed advantageous to do so for performance or other reasons, in that the termination sequence can initialize the receive decoder to begin monitoring for a new alternating sequence. 
         [0029]    The invention has been described with the controlling entity  14  indicating to the transmit encoder  16  the type of low level signal or signals, and the transmit encoder  16  determining the number N of alternating bits which corresponds to the type of low level signal or signals. Alternatively the controlling entity  14  could contain the logic for determining the number N which corresponds to the type of low level signal or combination of signals. In such an embodiment, the command signals cmd_ 1  etc. simply convey a value of N to the transmit encoder  16 . The transmit encoder  16  then simply transmits the introduction sequence, the data sequence of N alternating bits, and the termination sequence, without having to determine the value of N for a given low level signal. Similarly, the receive decoder  20  simply determines the value of N and passes this value to the receiving entity  18  as sig_ 1 , and the receiving entity  18  then determines which low level signal or combination of signals is signified by this value N. This embodiment allows more general use of the invention, particularly as new low level signals or combinations of low level signals may be programmed into the logic of the controlling entity  14  and the receiving entity  18  without having to change hardware of the transmit encoder  16  and receive decoder  20 . Further alternatives may be used, such as intermediate components which translate a low level signal received from the controlling entity  14  to a value of N sent to the transmit encoder  16 . The method described above with reference to  FIG. 2  may be carried out by any component on the first circuit card  10 , or by any combination of components on the first circuit card  10 . In general, the invention envisions any conveyance of a command, the command being a low level signal or combination of low level signals, from a first circuit card to a second circuit card using a digital sequence of N alternating bits which uniquely define the command, thereby encoding the command into a serial data signal. 
         [0030]    The invention has been described as a controlling entity on a first circuit card conveying low level signals to a single receiving entity on a single second circuit card. Alternatively, the transmit encoder on the first circuit card could transmit the low level signals of the controlling entity to more than one receiving entity, located on one or more circuit cards. Each receiving entity could be sensitive to common commands, as well as commands specific to the receiving entity or specific to the card on which the receiving entity is located. 
         [0031]    The invention is preferably implemented as hardware on the transmit encoder and the receive decoder. The invention may alternatively be implemented as software or hardware on some or all of the devices within  FIG. 1 , or as a combination of software and hardware. If in the form of software, the logical instructions may be stored on a computer-readable medium. 
         [0032]    The embodiments presented are exemplary only and persons skilled in the art would appreciate that variations to the embodiments described above, such as methods logically equivalent to that described with reference to  FIG. 2 , may be made without departing from the spirit of the invention.