Abstract:
The disclosure relates to a method for detecting a current comprising: generating a bias current, transmitting the bias current to a feedback stage and a measurement stage connected to the measurement node receiving a current to be measured, slaving a voltage to the measurement node at a constant value by the measurement and feedback stages, transmitting to an output stage, a current circulating in the measurement stage, which depends on the bias current and the current to be measured, and converting a current circulating in the output stage into a voltage.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to integrated circuits and in particular the detection and measurement of a current in such a circuit. The present disclosure applies in particular to current detection circuits or current sense amplifiers present in non-volatile memories to read the state of memory cells. The present disclosure more generally applies to any circuit in which a current must be detected or measured. 
     2. Description of the Related Art 
     Various battery-powered devices comprise a non-volatile memory such as an EEPROM or Flash memory. Such memories are also present in contactless integrated circuit cards, which are powered from electric signals picked up by their antennas. It is therefore desirable that volatile memories may operate in a wide supply voltage range and in particular at low supply voltages, and that their electrical consumption may be as low as possible. These objectives of supply voltage and electrical consumption are hard to reach when memory reading and writing operations are subjected to heavy constraints in terms of execution speed. 
     The reading speed of a memory is significantly affected by the speed performances of the memory sense amplifiers, which tend to decrease with the supply voltage. Reading a memory cell of a non-volatile memory generally involves converting a current coming from the memory cell into a voltage and comparing the voltage obtained to a reference voltage. The conversion of cell current into voltage is performed by a current detection circuit. An example of such a circuit is shown in  FIG. 1 . 
     In  FIG. 1 , the circuit comprises a reference branch, a measurement branch and a comparator CP 1 . The reference branch comprises a P-channel MOS transistor referred to as P 11 , an N-channel MOS transistor referred to as N 11 , an inverter I 1  and a current source CS 1  supplying a reference current Irf 1 . Transistor P 11  comprises a source terminal receiving a supply voltage Vdd of the circuit, and gate and drain terminals connected to the drain of transistor N 11 . Transistor N 11  comprises a source terminal connected to the ground through current source CS 1  and connected to a gate terminal of transistor N 11  through inverter I 1 . The measurement branch comprises a P-channel MOS transistor referred to as P 12 , an N-channel MOS transistor referred to as N 12 , an inverter  12  and a current source CS 2  symbolizing the current to be detected or measured. Transistor P 12  comprises a source terminal receiving a supply voltage Vdd of the circuit, and a gate terminal connected to the gate of transistor P 11 . Transistor P 12  comprises a drain terminal connected to the drain terminal of transistor N 12 . Transistor N 12  comprises a source terminal connected to the ground through current source CS 2  and connected to a gate terminal of transistor N 12  through inverter  12 . The comparator CP 1  compares the voltage present on the drain terminals of transistors P 12  and N 12  with the voltage present on the drain terminals of transistors P 11  and N 11  (or on the gate terminals of transistors P 11  and P 12 ), and supplies an output voltage Vout representative of the comparison result. Transistors P 11 , P 12  form a current mirror having a transmission rate equal to one, to transmit all the current Irf 1  circulating in the reference branch to the measurement branch. Transistors in cascode configuration with an inverter and a source follower stage with a unitary feedback loop are used to obtain a short precharge duration of the circuit in which the current must be measured, independent of the circuit capacitive load. The circuit of  FIG. 1  allows a rapid precharge to be obtained independently of the capacitive load of the circuit whose current is to be measured, up to a supply voltage of 1.6 V. Below this value, the circuit in which the current is to be measured is not insufficiently biased, and the reading speed deteriorates. 
     There is therefore a need for a current detection or measurement circuit keeping good performances in terms of detection speed and electrical consumption, up to supply voltages lower than 1 V. There is also a need for a circuit which is simple and having low electrical energy consumption. 
     BRIEF SUMMARY 
     Embodiments relates to a method for detecting a current comprising: generating a bias current, transmitting the bias current to a feedback stage and a measurement stage connected to a measurement node receiving a current to be measured, slaving a voltage to the measurement node at a constant value by the measurement and feedback stages, transmitting to an output stage, a current circulating in the measurement stage, which depends on the bias current and the current to be measured, and converting a current circulating in the output stage into a voltage. 
     According to an embodiment, the method comprises transmitting a fraction of the bias current to the output stage. 
     According to an embodiment, the fraction of the bias current transmitted to the output stage is equal to the half 
     According to an embodiment, the method comprises applying the steps of transmitting the bias current to the measurement, feedback and output stages, and slaving and measurement steps, to a reference current and the current to be measured, and a step of comparing the measures obtained. 
     According to an embodiment, the bias current is a reference current independent of a power supply voltage of the measurement, feedback and output stages. 
     Embodiments also relate to a current measurement circuit configured to implement the above-defined method. 
     According to an embodiment, the circuit comprises a bias stage transmitting a bias current, a measurement stage, a feedback stage and an output stage, the bias stage forming with each measurement and feedback stages a current mirror to transmit the bias current to the measurement stage and the feedback stage, the feedback stage and the measurement stage being connected and forming a slaving loop to maintain a voltage constant in a measurement node of the measurement stage. 
     According to an embodiment, the measurement stage forms with the output stage a current mirror to transmit to the output stage a difference between the bias current and a current to be measured taken from the measurement node. 
     According to an embodiment, the bias stage forms with the output stage a current mirror to transmit a fraction of the bias current to the output stage. 
     According to an embodiment, the bias stage forms with the output stage a current mirror to transmit a fraction of the bias current to the output stage, and the measurement stage forms with the output stage a current mirror to transmit to the output stage a current difference between the bias current and a current to be measured taken from the measurement node, the output stage supplying a voltage representative of a difference between the current difference and a fraction of the bias current. 
     According to an embodiment, the bias current comes from a reference current source insensitive to variations of a power supply voltage of the circuit. 
     According to an embodiment, the measurement stage comprises a P-channel MOS transistor through which a current passes, corresponding to a difference between the current to be measured and the bias current, the feedback stage comprising an N-channel MOS transistor through which the bias current passes, and controlled by a voltage present on the measurement node, the P-channel MOS transistor being controlled by a voltage present on a drain terminal of the N-channel MOS transistor. 
     According to an embodiment, the circuit comprises two identical measurement circuits, one receiving a reference current and the other a current to be measured, and a comparator to compare a reference current measure provided by one of the two measurement circuits, to a measure of the current to be measured provided by a second of the two measurement circuits. 
     Embodiments also relate to an integrated circuit comprising a measurement circuit as above-defined. 
     Embodiments also relate to a memory comprising current sense amplifiers complying with the measurement circuit as above-defined. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Embodiments of the disclosure will be described hereinafter, in relation with, but not limited to the appended figures wherein: 
         FIG. 1  previously described shows a current detection circuit, according to prior art; 
         FIG. 2  shows a current detection circuit, according to one embodiment; 
         FIG. 3  schematically shows a current detection circuit, according to another embodiment; 
         FIG. 4  shows a circuit of the detection circuit of  FIG. 3 . 
         FIG. 5  is a schematic diagram of a memory according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  shows a current detection circuit DTC, according to one embodiment. The circuit DTC comprises a reference stage RFS, a feedback stage FBS, a measurement stage MSS, and an output stage OST. The reference stage RFS comprises a P-channel MOS transistor, referred to as P 1 , and a bias current source CSR. Transistor P 1  comprises a source terminal receiving a supply voltage Vdd of the circuit, and gate and drain terminals connected to the ground through current source CSR. The current source CSR is configured to generate a substantially constant bias current Ib independent of possible variations of the supply voltage Vdd. However, the current Ib may vary as a function of the circuit operating temperature and the circuit manufacture conditions. 
     The feedback stage FBS comprises a P-channel MOS transistor, referred to as P 2 , and an N-channel MOS transistor, referred to as N 1 , these two transistors forming an amplifier. Transistor P 2  comprises a source terminal receiving the supply voltage Vdd, a gate terminal at a voltage V 1 , connected to the gate and drain terminals of transistor P 1  and a drain terminal connected to a drain terminal of transistor N 1 . Transistor N 1  comprises a source terminal connected to the ground. 
     The measurement stage MSS comprises two P-channel MOS transistors, referred to as P 3 , P 5 , and an N-channel MOS transistor, referred to as N 2 . Transistor P 3  comprises a source terminal receiving the supply voltage Vdd, and a gate terminal connected to the gate terminals of transistors P 1 , P 2 . Transistor P 3  also comprises a drain terminal at a voltage V 2 , connected to the gate terminal of transistor N 1 , to a source terminal of transistor P 5  and a measurement node MN receiving a current to be measured Ic symbolized in the figure by a current source CSM. Transistor P 5  comprises a gate terminal at a voltage V 3 , connected to the drain terminals of transistors P 2  and N 1 , and a drain terminal at a voltage V 4 , connected to drain and gate terminals of transistor N 2 . Transistor N 2  comprises a source terminal connected to the ground. 
     The output stage OST comprises a P-channel MOS transistor, referred to as P 4 , and an N-channel MOS transistor, referred to as N 3 , these two transistors forming an amplifier. The stage OST may also comprise a buffer circuit BF. Transistor P 4  comprises a source terminal receiving the supply voltage Vdd, a gate terminal connected to the gate terminals of transistors P 1 , P 2 , P 3 , and a drain terminal at a voltage V 5 , connected to a drain terminal of transistor N 3  and to the input of the buffer circuit BF. Transistor N 3  comprises a gate terminal connected to the gate and drain terminals of transistors N 2 , and a source terminal connected to the ground. The circuit BF supplies an output voltage Vout depending on the voltage V 5 , which depends on the current to be measured Ic. 
     Transistors P 2 , P 3 , P 4  form current mirrors with transistor P 1 . The width/length ratios of the channels of transistors P 1 , P 2 , P 3  are chosen equal so that copies of the current Ib present on the drain terminal of transistor P 1  are integrally transmitted to the drain terminals of transistors P 2 , P 3 . The current on the drain terminal of transistor P 5  is therefore equal to Ib−Ic. If transistor P 5  is conductive, it integrally transmits the current Ib−Ic to transistor N 2 . Transistors N 2 , N 3  also form a current mirror. The width/length ratios of the channels of transistors N 2 , N 3 , are chosen equal so that a copy of the current Ib−Ic present on the drain terminal of transistor N 2  is integrally transmitted to the drain terminal of transistor N 3 . The width/length ratio of the channel of transistor P 4  is chosen equal to a 1/n fraction of the width/length ratio of the channel of transistor P 1 , so that the current transmitted by the drain terminal of transistor P 4  is equal to a same fraction of the current Ib present on the drain of transistor P 1 , i.e., Ib/n. The result is that the current Ib-Ic transmitted by the current mirror formed by transistors N 4  and N 3  is compared to the current equal to Ib/n transmitted by the current mirror formed by transistors P 1  and P 4 . In the example of  FIG. 2 , the width/length ratio of the channel of transistor P 4  is chosen equal to half that of the channel of transistor P 1 , so that the current transmitted by the current mirror formed by transistors P 1  and P 4  is equal to half the current Ib. This current comparison makes a threshold current appear, equal to Ic=Ib−Ib/n (=Ib/2 if n=2). When the current Ic is lower than this threshold current, the current at the drain terminals of transistors P 4  and N 3  establishes at Ib/n, and voltage V 5  establishes at the voltage between the drain and the source of transistor N 3  (V 5 =VdsN 3 ), this last voltage may be around one hundred millivolts. On the contrary, when the current Ic is higher than this threshold current, the current at the drain terminals of transistors P 4  and N 3  establishes at Ib−Ic, and the voltage V 5  establishes at the supply voltage Vdd minus the voltage between the source and drain terminals of transistor P 4  (V 5 =Vdd−VdsP 4 ). Consequently, the output stage performs a current-voltage conversion. 
     In particular, the function of the circuit BF is to add gain to the current-voltage conversion. Circuit BF may be formed by two inverters in series. Circuit BF is configured to supply an output voltage Vout equal to zero when voltage V 5  is lower than a threshold voltage of circuit BF which may be equal to Vdd/2, and a voltage Vout equal to voltage Vdd when voltage V 5  is higher than Vdd/2. 
     If voltage V 2  of the current measurement node MN decreases due to an increase of the current to be measured Ic, transistor N 1  tends to become less conductive. The result is that voltage V 3  on the drain terminal of transistor N 1  increases with a significant gain as a function of the gain of the stage FBS. The increase of voltage V 3  causes a decrease of the current going through transistor P 5 . Consequently, voltage V 2  tends to increase. Similarly, a decrease of the current Ic and therefore of voltage V 2  of the measurement node MN is compensated by an increase of voltage V 3  on the gate of transistor P 5 . The result is that voltage V 2  of the measurement node MN is maintained fixed by the slaving loop formed between transistors N 1 , P 2  and P 5 , even if the current Ic varies. The measurement node MN therefore has very low impedance and voltage V 2  corresponds to the voltage between the gate and source terminals of transistor N 1 . In addition, it is to be noted that voltage V 2  is not sensitive to the variations of the supply voltage Vdd thanks to the current mirror formed by transistors P 1  and P 3 . 
     During operation of the detection circuit DTC, a current circulates in the various branches of the circuit and in particular in the measurement stage MSS which comprises more transistors than the other stages RFS, FBS, OST. To that end, in one embodiment, the supply voltage Vdd is higher than a minimum voltage of 0.9 V corresponding to the sum of a minimum gate-source voltage of transistor N 2  (around 0.5 V), a minimum drain-source voltage of transistor P 5  (around 0.2 V) and a minimum saturation voltage of transistor P 3  (around 0.2 V). The circuit DTC may also operate with a relatively high supply voltage Vdd, only limited by the breakdown voltage of transistors P 1  to P 4 . 
     The rejection ratio of the supply voltage of circuit DTC is only linked to the corresponding ratio of current source CSR. Current source CSR may be of the type Proportional To the Absolute Temperature PTAT, Complementary To the Absolute Temperature CTAT, or Zero-dependence To the Absolute Temperature ZTAT. 
     The output circuit of the measurement circuit DTC may be modified in several ways. Thus, according to one embodiment, the gate terminal of transistor P 4  may simply be grounded instead of being connected to the gate terminal of transistor P 1 . In this case, a voltage different from zero appears at the output Vout of circuit BF when the current Ic is higher than the current Ib. According to another embodiment, the current Ib−Ic on the drain terminal of transistor N 3  or P 5  may be used by another circuit configured to supply a voltage whose value depends on the value of the current Ib−Ic. 
       FIG. 3  shows a current detection circuit DTCD, according to another embodiment. The circuit DTCD comprises two identical current detection circuits DTC 1 , DTC 2 . Each circuit DTC 1 , DTC 2  comprises a bias node BN connected to a common bias current source CSB, supplying the bias current Ib. Each circuit DTC 1 , DTC 2  comprises a measurement node MN. The node MN of circuit DTC 2  is connected to a reference current source CSR supplying a measurement reference current Icr. In the case of a memory, the current Icr may be that obtained with a reference memory cell in a known programmed or erased state. The node MN of circuit DTC 2  is connected to the current source CSM supplying the current to be detected or measured Ic. Each circuit DTC 1 , DTC 2  supplies an output voltage Vo representative of the current Ic, Icr received on their measurement node MN. The circuit DTCD comprises a comparator CP receiving in input the output voltages Vo of circuits DTC 1 , DTC 2  and supplying an output voltage Vout representative of the difference between the output voltages of circuits DTC 1 , DTC 2 , and therefore the difference between the currents Ic and Icr. 
     According to one embodiment, circuits DTC 1 , DTC 2  are identical to the circuit DTC shown in  FIG. 2 . The current source Ib is not necessarily fixed or stable or independent of the supply voltage Vdd of circuits DTC 1 , DTC 2 . Indeed, the comparator 
     CP compares the voltages representative of the currents Ib−Icr and Ib−Ic, i.e., supplies a signal representative of the current (Ib−Icr)−(Ib−Ic) which is equal to Ic−Icr, this value being independent of the current Ib. 
     According to another embodiment, circuits DTC 1 , DTC 2  are identical to the circuit DTC 3  shown in  FIG. 4 . Circuit DTC 3  differs from the circuit DTC shown in  FIG. 2  in that it does not comprise the output stage OST comprising transistors P 4  and N 3 . Thus, the output voltage Vo of circuit DTC 3  corresponds to the voltage V 4  taken from the gate and drain of transistor N 2 . 
     A schematic diagram of a memory  10  according to one embodiment of the present disclosure is shown in  FIG. 5 . The memory  10  includes a memory array  12  and a current detector  14  that acts as a sense amplifier to determine memory states of memory cells of the memory array. The current detector  14  may be implemented using any of the current detectors DTC, DTCD, DTC 3  discussed above and shown in  FIGS. 2-4 . In particular, the current IC to be detected using the current detectors DTC, DTCD, DTC 3  may be the current through an accessed memory cell of the memory array  12  and the current Icr may be a reference current that is compared to the memory cell current Ic in order to determine the value stored in the memory cell. Of course, the depiction in  FIG. 5  is highly schematic, and the memory  10  may include numerous other parts that are not shown, such as column and row decoders, bias circuits, etc. and may include multiple current detectors  14  acting as sense amplifiers. 
     The memory  10  may be a non-volatile memory, such as an EEPROM or Flash memory, or any other type of memory that can be read using a current detector such as the current detector  14 . The memory  10  can be included in numerous different devices, such as various battery-powered devices or in contactless integrated circuit cards, which are powered from electric signals picked up by their antennas. 
     It will be clear to those skilled in the art that the present disclosure is susceptible of various embodiments and applications. In particular, the disclosure is not limited to the circuits previously described. Indeed, these circuits may be easily modified by those skilled in the art. 
     In addition, the disclosure does not necessarily apply to current sense amplifiers present in EEPROM and Flash memories, but may apply to any circuit in which a current is to be detected or measured. Thus, the disclosure may for example apply to circuits comprising a sensor such as a photodetector, supplying a current as a function of an electromagnetic radiation received by the photodetector. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.