Abstract:
A circuit and method for sensing the inductor current flowing to a load from a switching power supply without using a sense resistor in the path of the inductor current. In a synchronous buck converter topology, the inductor current is derived by sensing the voltage drop across the synchronous MOSFET of the half-bridge and reconstructing the current using a sample and hold technique. A ripple current synthesizer is employed to reconstruct inductor current outside the sample and hold window. The sampled product I Load ×R DSon  is used to update the ripple current estimator with dc information every switching cycle. The resulting voltage waveform is directly proportional to the inductor current. The inductor current synthesizer of the present invention can also be used in boost converter, flyback converter and forward converter topologies.

Description:
This application claims the benefit of U.S. Provisional Application Serial No. 60/190,926, filed Mar. 21, 2000, and U.S. Provisional Application Serial No. 60/209,478, filed Jun. 5, 2000. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to current mode control of switching power supplies, particularly low voltage power supplies. 
     2. Description of Related Art 
     Current mode power supplies, such as the synchronous buck converter shown in FIG. 1, typically use a resistive element to sense current. This method has the drawback of causing additional circuit losses, and the sense resistor occupies space. Accordingly, it would be desirable to provide a current mode power supply which does not require a resistive element for sensing inductor current. 
     SUMMARY OF THE INVENTION 
     The present invention, in lieu of directly sensing the inductor current with a resistor, derives the inductor current by sensing the voltage drop across the synchronous MOSFET of the half-bridge and reconstructs the current using a sample and hold technique. A ripple current synthesizer is employed to reconstruct inductor current outside the sample and hold window. The sampled product I Load ×R DSon  is used to update the ripple current synthesizer with dc information every switching cycle. The resulting voltage waveform is directly proportional to the inductor current. 
     The power converter may operate at constant switching frequency if desired. The synchronous MOSFET may be turned off after a brief sample period if desired. The inductor current synthesizer of the present invention can be used not only in a synchronous buck converter power supply, but also with boost converter, flyback converter and forward converter topologies. 
     Other features and advantages of the present invention will become apparent from the following description of the invention, which refers to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 shows a circuit schematic of the inductor current synthesizer circuit of the present invention. 
     FIG. 2 shows a set of timing and control waveforms that illustrate the operation of the circuit the schematic of which is provided in FIG.  1 . 
     FIG. 3 shows a digital embodiment of the inductor current synthesizer of the present invention. 
     FIGS. 4 a ,  4   b  and  4   c  show common power circuit topologies in which the inductor current synthesizer of the present invention can employed. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to FIG. 1, the inductor current synthesizer circuit of the present invention is identified generally by reference numeral  2  and comprises two major circuit blocks, namely a switching power supply dc load information converter  4 , and an inductor ripple current estimator  6 . 
     Switching power supply dc load information converter  4  comprises inverting amplifier  10  and sample and hold switches  12  and  14 . Inductor ripple current estimator  6  comprises transconductance amplifier  16 , current slope synthesizer C slope , and control switch  18 . 
     The synchronous buck power stage in FIG. 1, which consists of power MOSFETs Q 1  and Q 2 , MOSFET driver  24 , inductor L 1 , output capacitor C 1  and R load , is used to illustrate the operation of the current synthesizer circuit of the present invention. As shown in FIGS. 4 a - 4   c , the current synthesizer circuit of the present invention can also be used in boost converter, flyback converter and forward converter topologies. 
     In a conventional buck converter as shown in FIG. 1, a high drive pulse at UG (upper gate driver) turns MOSFET Q 1  on and a high drive pulse at LG (lower gate driver) turns MOSFET Q 2  on. Drive pulses UG and LG are complementary as shown in FIG. 2, waveforms  2  and  3 . 
     Referring to FIG. 2, the operation of the inductor current synthesizer of the present invention is as follows: 
     PERIOD  1 : Sample Period  1  (SH 1 ) 
     Sample Period  1  (SH 1 ), which is the settling time period for inverting amplifier  10 , allows the transfer of switch node negative voltage V sw  information expressed in equation (1) to inverting amplifier  10 . 
     
       
         V sw =−(I Load )×(R dsonQ2 )  (1) 
       
     
     Sample period SH 1  is adequate to allow inverting amplifier output  10  to settle before Sample Period  2 . Inverting amplifier  10  amplifies the sampled portion of V sw  by a factor required by current mode control system loop, and is denoted by Idc shown as waveform  6  in FIG.  2 . The output Idc of inverting amplifier  10  is described by equation (2), where −K 10  is the gain of inverting amplifier  10 . 
     
       
         I dc =−K 10 ×V sw   (2) 
       
     
     PERIOD  2 : Sample Period  2  (SH 2 ) 
     After an appropriate delay from the application of SH 1 , Sample Period  2  is initiated through closure of switch  14  by the dc update signal SH 2  as shown in waveform  5  of FIG.  2 . The closure of switch  14  provides cycle-by-cycle update of dc information to C slope . 
     ILsynth, shown in waveform  7  of FIG. 2, experiences a slight correction of ramp voltage, which is indicative of the ILsynth signal being calibrated to Idc level through closure of switch  14 . In practice, the correction to ILsynth may be either positive, negative, or rarely, zero. The DC update signal SH 2  is held high throughout the Q 2  on time period. 
     Waveform  8  of FIG. 2 shows the inductor voltage V L1  which can be calculated according to equation (3): 
     
       
         V L1Q2 =V out +I L1 ×R dson   (3) 
       
     
     PERIOD  3 : Ripple Charge Period 
     As UG goes high, Q 2  is turned off and Q 1  is turned on and V sw approaches the input voltage and the inductor voltage becomes V L1Q1  as expressed in equation (4) and as shown in waveform  8  of FIG.  2 . The output of transconductance amplifier  16  provides a charging current to charge Cslope which can be derived from equations (4) through (9): 
     
       
         V L1Q1 =V in −V out   (4) 
       
     
     The inductor current ripple di L1  is represented by equation (5)                     i   Li       =         V   L1Q1     ×          t   on         L1             (   5   )                                
     The i Cslope  capacitor charging current is related to the inductor voltage V L1Q1  by the transconductance G m16  of amplifier  16 , and is represented by equation (6): 
     
       
         i Cslope =G m16 ×V L1Q1   (6) 
       
     
     The capacitor charge current i Cslope  also develops a changing voltage dv which is represented by equation (7):                i   Cslope     =       C   slope     ×            v   slope              t   on                   (   7   )                                
     The change of inductor current di L1  is related to change in capacitor voltage dv Cslope  by scaling factor K and is represented in equation (8): 
     
       
         di L1 =K×dv Cslope   (8) 
       
     
     By proper substitution, a relationship between K factor and transconductance G m16  is established and is represented by equation (9)                      V   L1Q1     ×          t   on           L   1       ×   K     =           V   L1Q1     ×          t   on           C   slope       ×     G   m16               (   9   )                                
     PERIOD  4 : Switch Node settling period 
     The switch node settling period is the period when turn-off and recovery of Q 1  take place and Q 2  is in the turn-on process. It provides adequate switch node settling time before Period  1  is initiated. 
     The inductor current synthesizer represented in FIG. 3 is the digital embodiment of the inductor current synthesizer circuit of the present invention. 
     Similar to the analog counterpart shown in FIG. 1, the digital embodiment consists of two major building blocks. 
     1. The switching power supply dc load and accumulated error information converter  30 , which comprises n-bit analog to digital converter  32 , two to one line selector  34 , and current accumulator  36 ; and 
     2. Inductor ripple current estimator  38 , which comprises n-bit analog to digital converters  40  and  42 , two to one line selector  44 , adder  46 , and scaling stage  48 . 
     Inputs from both stages are added at adder  50 , and scaled in scaler  52 , the output of which is the digitally synthesized inductor current. 
     The power stage is similar to the one described with respect to the first embodiment of the invention. It consists of Q 1  and Q 2  power MOSFETs, inductor L 1 , output capacitor C 1  and load R load . 
     As in a conventional buck converter, a high output UG turns Q 1  on and a high output LG turns Q 2  on. UG and LG are complementary drive pulses. 
     The states of the inductor current digital synthesizer are described in the following table: 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                   
                   
               
               
                   
                 Sample 
                 Sample 
                 Ripple Discharge 
                 Ripple Charge 
               
               
                   
                 Period SH1 
                 Period SH2 
                 Period 
                 Period 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                 UG 
                 Low 
                 Low 
                 Low 
                 High 
               
               
                 LG 
                 High 
                 High 
                 High 
                 Low 
               
               
                 SH1 
                 High 
                 High 
                 Low 
                 Low 
               
               
                 SH2 
                 High, delayed 
                 High 
                 Low 
                 Low 
               
               
                   
                 wrt to SH1 
               
               
                   
               
             
          
         
       
     
     The operation of the inductor current digital synthesizer is described in the following paragraphs: 
     In the following paragraphs, the notations used in the formulae are defined as: 
     Vout: Output voltage of the synchronous regulator, in volts 
     Vin: Input voltage of the synchronous regulator, in volts 
     Vsw: Switching node voltage of the synchronous regulator, in volts 
     ΔCount dis : Incremental count during discharge period, unitless 
     ΔCount ch : Incremental count during charge period, unitless 
     HF: Frequency of the high frequency clock in MHz 
     FS: Full scale voltage range, in volts 
     L 1 : inductance of L 1  inductor, in henries 
     K 1 : scaling factor, unitless 
     K 2 : scaling factor, unitless 
     n: number of Analog to Digital converter bits 
     Sample Period SH 1   
     Sample period SH 1  is the period when the output of A/D converter  32  is allowed to settle. This includes the period of quantization of the analog information and the binary coding of the quantized input. 
     During this period the time varying input switch node voltage Vsw(t) is digitized into n-bits by analog to digital converter  32 .          Vsw     (   t   )            -&gt;   nbits            Vsw     (   0   )                     …                   Vsw     (   n   )                                
     Sample Period SH 2   
     During this period, the output of analog to digital converter  32  is used to recalibrate the synthesized inductor current information at current accumulator  36 . 
     SH 2  is a timed signal that enables the output of A/D converter  32  to be transferred to the output of selector  34  during the on time of Q 2 . Thus, the digitized current information is supplied to current accumulator  36  via selector  34  selector during SH 2 . 
     Ripple Discharge period 
     When Q 2  is turned on, Logic Low inputs of selector  44  are selected. Therefore, the output of adder  46  is the complemented value of the output voltage. 
     The output of A/D converter  42 , converted into n-bits, is:          Vout     (   t   )            -&gt;   nbits            Vout     (   0   )                     …                   Vout     (   n   )                                
     and is complemented at inverter  45  because during this period the inductor voltage is −Vout. 
     The output of selector  44  steers the logic low inputs to adder  46 . 
     During discharge, the incremental count ΔCount dis  at each clock cycle is calculated according to:                  Δ                   Count   dis       =         -   Vout       L   1       ×     1   HF              
          Also   ,             (   10   )                 Δ                   Count   dis       =         -   Vout       K   1       ×         2   ″     -   1     FS               (   11   )                                
     where K 1  is the scaling factor which is calculated from equations (10) and (11):              K1   =           2   ″     -   1     FS     ×     L   1     ×   HF             (   12   )                                
     The expression for K 1  in equation (12) indicates that it is independent of the input and the output voltages and is modified due to errors caused by variations in inductance of the inductor, the high frequency clock, and number of A/D converter bits. 
     During this period, the selected data at the output of selector  34  is loaded to the current accumulator  36  at each occurrence of the high frequency clock HF. The accumulated data is fed to adder  50 . 
     Ripple Charge Period 
     When Q 1  is turned on, the quantized input voltage Vin at the output of n-bit A/D converter  40  is selected by two to one line selector  44 . The output of selector  44  is provided to one of the inputs of adder  46 . The data at the output of adder  46  is the digital representation of Vin−Vout. 
     The output of A/D converter  40  is Vin converted to n-bits:          V                 i                   n     (   t   )              →   nbits          V                 i                   n     (   0   )                     …                 V                 i                   n     (   n   )                                
     The output of selector  44  steers the digitized Vin inputs to adder  46 . During this period, the inductor voltage will be V in −V out . 
     During charge the incremental count at each clock cycle will be:          Δ                   Count   ch       =         (       V                 i                 n     -     V                 out       )       L   1       ×     1     H                 F                                
     Through a similar exercise, one can demonstrate that the expression obtained for K 1  in ripple charge period is identical to the one obtained in the ripple discharge period, which is independent of Vin and Vout. 
     The inductor current up-slope and down-slope information is fed to adder  50  after being scaled by scaler  48 . 
     During this period, the selected data at the output of selector  34  is loaded to the current accumulator  36  at each occurrence of the high frequency clock HF. The accumulated data is fed to adder  50 . 
     Scaling factor K 2  at scaler  52  provides correction for changes for synchronous MOSFET Q 2  Rdson process variations and Rdson temperature variations. 
     EXAMPLE 
     Assume A/D converter  32  is 10 bits. A/D converters  40  and  42  are 8 bits. 
     Switching frequency f s : 300 KHz, 
     Switching period T s : 3.33 microseconds. 
     Inductor L 1 : 800 nH 
     HF Clock: 10 MHz, 
     Q 2  on resistance R dson : 6 millions 
     Input voltage V in : 20 Volts 
     Output voltage V out : 1.3 Volts 
     I L1 =20 A 
     Inductor ripple current: 5 A 
     n: 10 bits for A/D converter  32  and 8 bits for A/D converters  40  and  42  Input of A/D converter  32  when Q 2  is conducting is: 
     
       
         V sw =R dson ×I L1   (1) 
       
     
     V sw =0.006*20 A=120 mV 
     Voltage to Current scaling is 100 mV/A 
     A/D converter  32  will output  120  counts at 1.024v Full Scale.          Count   /   Amp     =         120                 count       20      A       =     6                   counts   /   Amp                                
     At the ripple generator, 25.5 volts Full Scale for an 8 bit A/D. 
     Number of counts to maintain 5 A peak to peak ripple: 
     
       
         C ripple =5A×6 count/A=30 counts  (2) 
       
     
     Each clock cycle will provide C clk  counts                Count   ch     =           (       V     i                 n       -     V   out       )       L   1       ×     1     H                 F         =     2.34        A   /   clk                 (   3   )                                
     Number of counts required to generate 5 A ripple 
     C clk =Count/A×Count ch    
     C clk =6×2.34=14.04 counts 
     K factor is calculated:              K1   =       (       V     i                 n       -     V   out       )     ×     255   FS     ×     1     C   clk                 (   4   )                               K 1 =13.32 
     Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.