Abstract:
The present invention refers to a fully differential operational amplifier of the folded cascode type.  
     In one embodiment the fully differential operational amplifier comprises: a differential input stage able to drive a differential output stage; said differential output stage includes a first branch having at least a first and a second transistor, and a second branch having at least a third and a fourth transistor; said first and second branch are coupled to a first and a second voltage source; a feedback circuit of said first, second, third and fourth transistors that is constituted by a single amplifier having four inputs and four outputs, said four inputs taking the voltages present on a terminal of said first, second, third and fourth transistors, and providing voltages to the control elements of said first, second, third and fourth transistors, which voltages depend on the input voltages of said four inputs.

Description:
TECHNICAL FIELD  
         [0001]    The present invention refers to a fully differential operational amplifier of the folded cascode type.  
         BACKGROUND OF THE INVENTION  
         [0002]    In applications where it is necessary to have high direct current (“DC”) gain without bandwidth restrictions, single stage amplifiers are used with the output transistors cascode connected, and with a feedback loop for each output transistor, to increase the output impedance. These feedback loops are commonly called gain amplifier circuits (gain boosting circuits) because of their function.  
           [0003]    A fully differential operational amplifier with a single stage includes four output transistors (two for each output). Therefore, four feedback loops are needed, which normally are realized by means of four unbalanced operational amplifiers.  
           [0004]    As disclosed in the U.S. Pat. No. 5,748,040, a further realization of the feedback loops is effected by replacing the four individual output operational amplifiers with two differential operational amplifiers. The principal advantages of this realization are a reduced current consumption and the use of a smaller silicon area.  
         SUMMARY OF THE INVENTION  
         [0005]    According to the present invention, a reduced current consumption, the use of less silicon area, and other objectives are achieved by means of a fully differential operational amplifier of the folded cascode type comprising: a differential output stage; a differential input stage able to drive said output stage; said differential output stage including a first branch having at least a first and a second transistor and a second branch having at least a third and a fourth transistor; said first and second branches coupled to a first and to a second voltage source; and a feedback circuit of said first, second, third and fourth transistors wherein said feedback circuit is constituted by a single amplifier having four inputs and four outputs, said four inputs taking the voltages present on terminals of said first, second, third and fourth transistors, and said four outputs each providing a voltage to the control elements of said first, second, third and fourth transistors, which said voltage depends on the value of the input voltage of said four inputs.  
           [0006]    Such objectives are also achieved by means of an amplifier, having four inputs and four outputs, able to provide an output voltage that depends on the value of the input voltages of said four inputs wherein: said amplifier includes a first differential pair composed of a first and a second transistor having their drains respectively connected to two output terminals and coupled to the first voltage source through two current generators; the gates of said first and second transistors coupled to two input terminals; a second differential pair composed of a third and a fourth transistor having their drains connected respectively to two output terminals and coupled to the second voltage source through two current generators; the gates of said third and fourth transistors coupled to two input terminals; the sources of said first, second, third and fourth transistors connected together; and a voltage generator applied between the first voltage source and said transistor sources. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]    The features and the advantages of the present invention will be made more evident by the following detailed description of a particular embodiment, illustrated as a non-limiting example in the attached drawings, wherein:  
         [0008]    [0008]FIG. 1 illustrates a schematic circuit of a fully differential operational amplifier of the folded cascode type according to the known art;  
         [0009]    [0009]FIG. 2 illustrates a schematic circuit of a fully differential operational amplifier of the folded cascode type according to the present invention;  
         [0010]    [0010]FIG. 3 illustrates a schematic circuit of an amplifier having four inputs and four outputs according to the present invention; and  
         [0011]    [0011]FIG. 4 illustrates a schematic circuit of a second embodiment of an amplifier having four inputs and four outputs according to the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0012]    Referring to FIG. 1, it is illustrated a schematic circuit of a fully differential operational amplifier of the folded cascode type according to the known art. A differential pair of transistors  11  and  12  are connected in a common source configuration with the sources connected to a terminal of a current generator  10 , whose other terminal is connected to a first voltage source VDD. The drain of the transistor  11  is connected to a node  14 , and the drain of the transistor  12  is connected to a node  13 . The gate of the transistor  11  is connected to a positive input IN+, and the gate of the transistor  12  is connected to a negative input IN−.  
         [0013]    To the node  13  is connected the drain of a transistor  18 , and a source of transistor  18  is connected to a second voltage source GND. To the node  14  is connected the drain of a transistor  22 , whose source is connected to the second voltage source GND.  
         [0014]    To the first voltage source VDD is connected the source of a transistor  15 , whose drain is connected to a node  23 ; to the first voltage source VDD is also connected the source of a transistor  19 , whose drain is connected to a node  24 . The gates  30 ,  31 ,  32  and  33  respectively belonging to the transistors  15 ,  19 ,  18  and  22  in FIG. 1 are left open for simplicity of representation, but they are to be connected to their relative bias voltages not shown, and they serve the function of current mirrors.  
         [0015]    To the node  13  is also connected the source of a transistor  17 , whose drain is connected to a negative output terminal OUT−. To this terminal OUT− is connected the drain of a transistor  16 , whose source is connected to the node  23 .  
         [0016]    In an analogous configuration, on the other symmetrical branch, to the node  14  is connected the source of a transistor  21 , whose drain is connected to a positive output terminal OUT+. To this terminal OUT+ is connected the drain of a transistor  20 , whose source is connected to the node  24 .  
         [0017]    An operational amplifier  24  having differential output has an input IN 1  connected to the node  13 , an input IN 2  connected to the node  14 , an output OUT 1  connected to the gate of the transistor  17 , and an output OUT 2  connected to the gate of the transistor  21 . An operational amplifier  23  having differential output has an input IN 3  connected to the node  23 , an input IN 4  connected to the node  24 , an output OUT 3  connected to the gate of the transistor  16 , and an output OUT 4  connected to the gate of the transistor  20 .  
         [0018]    The transistors  11 ,  12 ,  15 ,  16 ,  19  and  20  are, for instance, p-channel transistors, and the transistors  17 ,  18 ,  21  and  22  are, for instance, n-channel transistors.  
         [0019]    [0019]FIG. 1 represents an example of a fully differential operational amplifier of the folded cascode type. However, other circuit configurations are possible which could be regarded as functionally equivalent.  
         [0020]    [0020]FIG. 2 shows a schematic circuit of a fully differential operational amplifier of the folded cascode type according to the present invention. It is of the type shown in FIG. 1, and, therefore, the corresponding elements have the same numerical references.  
         [0021]    With respect to the schematic of FIG. 1, where are shown two operational amplifiers  23  and  24  having differential outputs which form the feedback loops (gain boosting circuits), the two operational amplifiers have been replaced, in FIG. 2, by a single amplifier  40  having four inputs IN 1 , IN 2 , IN 3  and IN 4  and four outputs OUT 1 , OUT 2 , OUT 3  and OUT 4 .  
         [0022]    [0022]FIG. 3 shows a schematic circuit of the amplifier  40  having four inputs and four outputs according to the present invention.  
         [0023]    The amplifier  40  is comprised of two symmetrical branches, the first branch having a current generator  41  connected on a side to the first voltage source VDD and connected on the other side to both the output OUT 3  and the drain of a transistor M 3 , whose gate is connected to the input IN 3  and whose source is connected to a node  46 . To the node  46  is also connected the source of a transistor M 1 , whose gate is connected to the input IN 1  and whose drain is connected to both the output OUT 1  and a side of a current generator  42 , whose other side is connected to the second voltage source GND. The second branch comprises a current generator  43  connected on a side to the first voltage source VDD and on the other side to both the output OUT 4  and the drain of a transistor M 4 , whose gate is connected to the input IN 4  and whose source is connected to the node  46 . To the node  46  is also connected the source of a transistor M 2 , whose gate is connected to the input IN 2  and whose drain is connected to both the output OUT 2  and a side of a current generator  44 , whose other side is connected to the second voltage source GND.  
         [0024]    A resistor  45  is connected between the first voltage source VDD and a transistor M 5  connected like a diode, having the gate and the drain connected to the resistor  45  and the source connected to the node  46 .  
         [0025]    The transistors M 1  and M 2  are, for instance, p-channel transistors, and the transistors M 3 , M 4  and M 5  are, for instance, n-channel transistors.  
         [0026]    [0026]FIG. 4 illustrates a schematic circuit of a second embodiment of the amplifier  40  having four inputs and four outputs according to the present invention. The elements corresponding to those shown in FIG. 3 have the same numerical references.  
         [0027]    In addition to the elements of FIG. 3, in FIG. 4 there is a transistor M 6  having the drain connected to the first voltage source VDD and having the source connected to a current generator  48  in turn connected to the second voltage source GND. The gate of the transistor M 6  is connected to the drain of the transistor M 3 , and the output OUT 3  is this time taken from the source of the transistor M 6 . A transistor M 7  has a drain connected to the second voltage source GND and has a source connected to a current generator  47 , which is in turn connected to the first voltage source VDD. The gate of the transistor M 7  is connected to the drain of the transistor M 1 , and the output OUT 1  is this time taken from the source of the transistor M 7 .  
         [0028]    In an analogous configuration for the other symmetrical branch, we find a transistor M 8  having a drain connected to the first voltage source VDD and having a source connected to a current generator  49 , which is in turn connected to the second voltage source GND. The gate of the transistor M 8  is connected to the drain of the transistor M 4 , and the output OUT 4  is this time taken from the source of the transistor M 8 . A transistor M 9  has a drain connected to the second voltage source GND and has a source connected to a current generator  50 , which is in turn connected to the first voltage source VDD. The gate of the transistor M 9  is connected to the drain of the transistor M 2 , and the positive output OUT 2  is this time taken from the source of the transistor M 9 .  
         [0029]    The transistors M 7  and M 9  are, for instance, p-channel transistors, and the transistors M 6  and M 8  are, for instance, n-channel transistors.  
         [0030]    As shown in FIG. 4, it is preferable to add the transistors and the current generators on the outputs of the amplifier  40  in order stabilize the output signal. The additional transistors work like voltage followers, and they can be designed so that they consume low current and occupy a small space.  
         [0031]    Returning to the amplifier having four inputs and four outputs shown in FIG. 3, it is to be noted that the simple structure allows for a low current consumption and a wide bandwidth. A notable reduction of used silicon area has also been achieved in comparison with the prior circuits. It must be considered that our new circuit has only a small reduction in the DC open loop gain when compared to the known circuits in the art. If we assume the transconductance (gm) of the transistors M 1 , M 2 , M 3  and M 4  to be equal we have:  
           Vout ( n )=0.25  gm rDS ( n ) with  n= 1, . . . , 4  (1)  
         [0032]    where rDS is the impedance of the output transistor in consideration. On the other hand, in the conventional circuits we had:  
           Vout ( n )=0.5  gm rDS ( n ) with  n= 1, . . . , 4  (2)  
         [0033]    Also, for the circuit of FIG. 3, we have:  
           Vout 1 −Vout 2 =K 1( VIN 1 −VIN 2)+ K 2( VIN 3− VIN 4)  (3)  
         [0034]    where Vout 1  and Vout 2  are the output voltages respectively of the output OUT 1  and OUT 2 ; VIN 1 , VIN 2 , VIN 3  and VIN 4  are the input voltages of the four inputs, respectively IN 1 , IN 2 , IN 3 , IN 4 ; K 1  is a first amplification factor and K 2  is a second amplification factor, with K 1  greater than K 2 . K 1  is about 26 dB and K 2  is about 1 dB.  
         [0035]    A similar relationship is valid also for the other two outputs:  
           Vout 3− Vout 4 =K 1( VIN 3− VIN 4)+ K 2( VIN 1− VIN 2)  (4)  
         [0036]    where Vout 3  and Vout 4  are the output voltages respectively of the output OUT 3  and OUT 4 ; VIN 1 , VIN 2 , VIN 3  and VIN 4  are the input voltages of the four inputs, respectively IN 1 , IN 2 , IN 3 , IN 4 ; K 1  is a first amplification factor and K 2  is a second amplification factor, with K 1  greater than K 2 . K 1  is about 26 dB and K 2  is about 1 dB.  
         [0037]    The resistor  45  and the transistor M 5  are used for the biasing of the node  46 .  
         [0038]    From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.