Abstract:
A method and apparatus for greatly increasing the output voltage or current transformation ratio in an impedance transformation amplifier are disclosed. Broadly, the method takes advantage of multiple, phase-synchronized impedance transformation stages, each of which preferably contributes an equal portion of the eventual output voltage or current.

Description:
REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority from U.S. Provisional Patent Application Ser. No. 60/380,436, filed May 13, 2002, the entire content of which is incorporated herein by reference. 
     
    
     FIELD OF THE INVENTION  
       [0002]     This invention relates generally to impedance transformation amplifiers, and in particular, to techniques for increasing the output voltage or current transformation ratio in an amplifier of this kind.  
       BACKGROUND OF THE INVENTION  
       [0003]     Impedance transformation amplifiers, as described in U.S. Pat. No. 5,610,553, entitled “Switching Amplifier with Impedance Transformation Output Stage” and incorporated herein by reference, provide output voltage or current exceeding that of the input without the use of a transformer. The maximum voltage or current amplification ratio is limited at low load impedances, however, if high efficiency is to be obtained. Typical voltage ratios with loads under eight ohms are typically limited to 4:1 or less. In some limited voltage applications, the maximum obtainable ratio does not provide adequate power. There exists a need to increase the output amplification ratio in impedance transformation amplifiers, so as to extend their use in higher-power applications.  
       SUMMARY OF THE INVENTION  
       [0004]     This invention resides in a method and apparatus for greatly increasing the output voltage or current transformation ratio in an impedance transformation amplifier. Broadly, the method takes advantage of multiple, phase-synchronized impedance transformation stages, each of which preferably contributes an equal portion of the eventual output voltage or current. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]      FIG. 1  shows a preferred embodiment of the present invention; and  
         [0006]      FIG. 2  shows voltage waveforms of control and output signals with respect to the circuitry of  FIG. 1 . 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0007]     Referring now to  FIG. 1 , voltage source  101  supplies power for all subsequently noted actions. Switching device  104  charges inductor  102  under the control of signal  119  from PWM Modulator  109 , which provides control signals in response to the receipt of incoming data stream  118 . Standard pulse-width modulation techniques are preferably used.  
         [0008]     At the termination of signal  119 , inductor  102  releases its stored charge through diode  106  into capacitor  108 . Following this cycle of events, switching device  105  charges inductor  103  under the control of signal  120  from PWM Modulator  109 . At the termination of signal  120 , inductor  103  releases its stored charge through diode  107  into capacitor  108 . Alternately, it can be seen that energy representative of incoming data  118  is stored at the voltage of source  101  in either inductor  102  or  103 , and released into capacitor  108  at another voltage.  
         [0009]     Control signals on lines  121  and  122  are controlled by PWM Modulator  109  to reflect the sign of incoming data  118 . Such operation may occur statically or dynamically, according to various practices in the art. Control signals  121  and  122  serve to activate switching devices  110  and  112 , respectively, while deactivating switching devices  111  and  113 , respectively, through the operation of inverters  123  and  124 .  
         [0010]     The net effect of the above is that charge stored in capacitor  108  is made available to one terminal of load  117  through either switching device  110  and inductor  114 , or switching device  112  and inductor  115 , thereby controlling direction of current flow through load  117 . Inductors  114  and  115 , in conjunction with capacitor  116  serve to filter out alias products inherent in the sampling process. Current return for load  117  is effected through either switching device  111  or  113  to voltage source  101 . This connection method allows output available at load  117  to approach zero.  
         [0011]     Referring now to  FIG. 2 , trace  201  and  202  show activity of control signals  119  and  120 , respectively, of  FIG. 1 . Traces  203  and  204  show activity of the cathodes of diodes  106  and  107 , respectively, hence voltage potential of inductors  102  and  103 , respectively, of  FIG. 1 . Trace  205  shows activity at the common connection of diodes  106  and  107 , capacitor  108 , and switching devices  110  and  112 , all of  FIG. 1 ; hence the instantaneous voltage produced by the actions described herein.  
         [0012]     At time  206 , control signal  119  is asserted in trace  201 , the result of which can be seen at diode  106  in trace  203 . At time  207 , release of control signal  119 , seen in trace  201 , produces a flyback voltage from inductor  102 , seen in trace  203 . This flyback voltage, conducted through diode  106 , results in a potential increase across capacitor  108 , seen in trace  205 . Subsequent assertion and deassertion of control signal  120 , seen at times  208  and  209 , respectively, result in a similar flyback voltage from inductor  103 , seen in trace  204  at time  209 , and a potential increase across capacitor  118 , as seen in trace  205  at this time.  
         [0013]     Note that use of two alternate inductor flyback periods results in possible charge periods twice that of the output period (the period that would be available to an inductor of a single stage) for each inductor. This period multiplication holds true for subsequent flyback stage additions, i.e., use of three inductors allows inductor charge periods three times that of the output period, etc. In that doubling the inductor charge period available doubles its maximum current, the resultant maximum flyback voltage therefore doubles for any given load resistance. Resultant output power of an impedance transformation amplifier of this topology then becomes that of the voltage transformation ratio in use multiplied by the square of the number of stages used.