Abstract:
A method and system for transmitting N-bit serial data (where N is a positive number) in the form of a bit serial, including a data sending circuit, a data receiving circuit and data transmission lines. The system includes a first data transmission line; a second transmission line; a transfer circuit, provided in the receiving means, for sending back to the data sending circuit through the second data transmission line, the bit content of received N-bit data each time one bit of the N-bit data is received through the first data transmission line; a comparison circuit, provided in the data sending circuit, for comparing the transmitted bit content and the bit content sent back on the second data transmission line; and a detection circuit provided in the data receiving circuit. The data sending circuit is adapted to transmit as a start bit a signal of a prescribed logical value before the N-bit serial data is sent, and, as an alarm bit, the results of the comparison after the N-bit serial data has been sent. The detection circuit detects whether the logical values of the start bit and the alarm bit are prescribed logical values, so that a transmission error or a break in a transmission line can be detected.

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to a method and system for the transmission of serial data, and more particularly to a method and system for the transmission of serial data that enable transmission errors and the breakage or disconnection of transmission lines to be detected in a reliable manner. 
     Data transmission systems which are widely known in the art have two data transmission paths, namely a sending line and a receiving line, over which serial data can be sent and received between two units in both directions in the form of a bit serial. If one unit is denoted the master and the other the slave, the master sends serial data to the slave over the sending line, and the slave transfers serial data to the master over the receiving line. Data transmission systems of this type frequently experience breakage or disconnection of transmission lines and transmission errors due to noise or the like, and such occurrences must be detected rapidly to preclude erroneous equipment operation. 
     Various systems have been put into practice to check for transmission errors. One such system adds a parity bit to the data. However, this does not permit a transmission error to be detected if the even-numbered bit in the received serial data has undergone a change in sign, nor does it permit detection of a break or disconnection in the transmission lines. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a method and system for the transmission of serial data, enabling a transmission error to be detected in a reliable manner if at least one of the bits in N-bit serial data experiences a transmission error. 
     It is another object of the present invention to provide a method and system for the transmission of serial data, which detect a break or disconnection in transmission lines, specifically sending, receiving and strobe lines, in a reliable manner. 
     It is still another object of the present invention to provide a method and system for the transmission of serial data, which both reduce the wasteful use of data transmission time and detect transmission errors and breakage of transmission lines in a reliable manner. 
     It is a further object of the present invention to provide a method and system for the transmission of serial data, which prevent erroneous system operation due to transmission errors or line breakage. 
     Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit block diagram showing an embodiment of the electrical system of a serial data transmission system in accordance with the present invention; and 
     FIGS. 2A and 2B are waveform diagrams of various signals carried over the sending, receiving and strobe lines, 
     FIG. 2A showing waveforms of signals when serial data is sent from a master to a slave, and FIG. 2B showing waveforms of signals when serial data is sent from the slave to the master. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIGS. 1 and 2, serial data is exchanged between a master unit MAS and a slave unit SLV. A sending line SL transmits the serial data from the master MAS to the slave SLV, and a receiving line RL transmits the serial data from the slave SLV to the master MAS. As the serial data is being sent and received, strobe pulses STB consisting of 18 pulses S 1  through S 18 , generated by a transmission control circuit TRFM which is located in the master MAS, and which will be described in more detail later, are sent to the slave SLV through a strobe line STL, the pulses being delivered in synchronism with the serial data. A shift register SFRm is supplied with 16-bit parallel data, to be sent to the slave SLV, which is transmitted over a bus line BUSM from a memory (not shown). The 16-bit parallel data is set in the register SFRm and is converted thereby into serial data SDO (FIG. 2A) one bit at a time in synchronism with shift pulses (the strobe pulses). The serial data is delivered to the slave SLV. In addition, serial data SDI&#39; (FIG. 2B) sent from the slave SLV is stored in the shift register SFRm from the most significant digit MSD while being shifted one bit at a time in synchronism with shift pulses, the shift register sending the data out on the bus line BUSM as parallel information upon receipt of 16 bits. 
     The transmission control circuit TRFM generates signals MS, SM which indicate the direction in which serial data is to be transmitted, as well as strobe pulses STB, shown in FIG. 2, consisting of 18 pulses S 1  through S 18 , these strobe pulses being generated as the master MAS sends N-bit serial data to the slave SLV, namely when signal MS is at logical &#34;1,&#34; and as the N-bit serial data is received from the slave SLV, namely when signal SM is at logical &#34;1.&#34; The transmission control circuit TRFM sends these strobe pulses STB to the slave SLV. The shift register SFRm located in the master MAS operates in synchronism with the positive-going transitions of the strobe pulses S 2  through S 17 , whereas a shift register which is located in the slave SLV, and which will be described later, operates in synchronism with the negative going transitions of the strobe pulses STB. 
     A comparator COIM compares sequentially the content of each bit in the N-bit serial data SDO sent from the master MAS to the slave SLV, and the content of each bit in the serial data SDI sent back to the master MAS each time the slave SLV receives one bit. The comparator COIM, after N bits have been sent from the master to the slave, delivers a signal comprising a logical &#34;1&#34; if all N bits in the sent and returned serial data were in agreement, but produces an alarm signal comprising a logical &#34;0&#34; if there was a discrepancy of even one bit in the sent and returned N-bit data. 
     GM 1  and GM 2  denote gate circuits. When serial data SDO is transmitted from the master to the slave, i.e., when signal MS is logical &#34;1,&#34; the gate circuit GM 1  supplies the sending line SL with (N+2)-bit serial data SDO (FIG. 2A) comprising a 1-bit start bit, N-bit serial data, and the 1-bit alarm bit, whereas when serial data SDI&#39; is being received from the slave, i.e., when signal SM is logical &#34;1,&#34; the gate circuit GM 1  supplies the sending line SL with the content of the most significant digit MSD of the shift register SFRm each time the bit is received. The bit content of the start bit is logical &#34;0.&#34; Thus, when signal MS is a &#34;1,&#34; the gate circuit GM 1  transmits a &#34;0&#34; in synchronism with the first pulse S 1  of the strobe pulses STB, transmits the N-bit parallel data, stored in shift register SFRm, bit-by-bit as serial data in synchronism with the second through 17th pulses S 2  through S 17 , and transmits the output of the comparator COIM as an alarm bit in synchronism with the pulse S 18 . On the other hand, when signal SM is a &#34;1,&#34; the gate circuit GM 1  transmits the content of the most significant digit MSD of the shift register SFR m , each time one bit of data is received from the slave, in synchronism with the pulses S 2  through S 17 . The gate circuit GM 2  has two functions as described below. When serial data SDO is being transmitted from the master MAS to the slave SLV (i.e., when signal MS is logical &#34;1&#34;) the slave SLV sequentially sends back to the master MAS, in synchronism with the negative-going transitions of the strobe pulses STB, the bit content which it has received from the master bit-by-bit. This bit content is sent back to the master as the serial data SDI shown in FIG. 2A. The gate circuit GM 2  delivers this returning serial data SDI to the comparator COIM over line l 2 . On the other hand, when serial data SDI&#39; is being sent from the slave SLV to the master MAS (i.e., when signal SM is logical &#34;1&#34;) the gate circuit GM 2  applies the serial data SDI&#39; to the shift register SFRm as the most significant digit MSD. 
     A detection circuit, designated DTCM, is adapted to detect transmission errors, as well as a break in the sending line SL, receiving line RL and strobe line STL, when serial data is being sent from the slave to the master, that is, when SM is a &#34;1.&#34; More specifically, the arrangement is such that the slave will send the 1-bit start bit at logical &#34;0&#34; before it sends the N-bit serial data, and the 1-bit alarm bit, which will be logical &#34;1&#34; in the absence of a transmission error, after it has sent the N-bit serial data. In the event of a transmission error or line breakage, however, the master MAS will receive the start bit, which will be logical &#34;1,&#34; or the alarm bit, which will be logical &#34;0,&#34; this being detected by the detection circuit DTCM as a transmission error or line breakage in a manner which will be described below. DVM, DVM&#39; denote drivers, and RVM denotes a receiver. 
     Shift registers in the slave SLV are denoted at SFRs and SFRs&#39;. The 16-bit parallel information which is to be transmitted from the slave SLV to the master MAS is set in shift register SFRs. Once this has been accomplished the information is converted into the serial data SDI&#39; bit-by-bit in synchronism with the shift pulses S 2  through S 17 , namely the strobe pulses STB, and is delivered to the master MAS. These signals are shown in FIG. 2B. The shift register SFRs&#39;, while shifting bit-by-bit in synchronism with the shift pulses S 2  through S 17  the serial data SDO which arrives from the master MAS, stores the data from the most significant digit MSD and delivers it as parallel information after the 16 bits have been received. A comparator COIS compares sequentially the content of each bit in the N-bit serial data SDI&#39; which the slave sends to the master, and the content of each bit in the serial data SDO&#39; which the master sends back to the slave each time the master receives one bit. After N bits have been sent from the slave to the master, the output of comparator COIS will be logical &#34;1&#34; if all N bits in the sent and returned serial data were in agreement, and logical &#34;0,&#34; namely an alarm bit, if there was a discrepancy of even one bit in the sent and returned N-bit data. 
     GS 1  and GS 2  denote gate circuits. When serial data SDI&#39; is transmitted from the slave SLV to the master MAS (i.e., when signal SM is logical &#34;1&#34;) the gate circuit GS 1  supplies the receiving line RL with (N+2)-bit serial data comprising a 1-bit start bit, N-bit serial data, and the 1-bit alarm bit, whereas when serial data SDO is being received from the master MAS (i.e., when signal MS is logical &#34;1&#34;) the gate circuit GS 1  supplies the receiving line RL with the content of the most significant digit MSD of the shift register SFRs&#39; each time the bit is received. The bit content of the start bit is logical &#34;0.&#34; Thus, when the signal SM is a &#34;1,&#34; the gate circuit GS 1  transmits a &#34;0&#34; in synchronism with the first pulse of the strobe pulses STB, transmits the N-bit parallel data, stored in shift register SFRs, bit-by-bit as serial data in synchronism with the second through 17th pulses S 2  through S 17 , and transmits the output of the comparator COIS as an alarm bit in synchronism with the 18th pulse S 18 . On the other hand, when signal MS is a &#34;1,&#34; the gate circuit GS 1  transmits the content of the most significant digit MSD of shift register SFRs&#39;, each time one bit of data is received from the master, in synchronism with the pulses S 2  through S 17 . The gate circuit GS 2 , on the other hand, functions as follows. When serial data SDI&#39; is being transmitted from the slave SLV to the master MAS (i.e., when SM is logical &#34;1&#34;) the master MAS sends back to the slave SLV, sequentially in synchronism with the positive-going transitions of the strobe pulses STB, the bit content which it has received from the slave bit-by-bit, this content being sent back as the serial data SDO&#39;. The gate circuit GS 2  delivers this returning serial data SDO&#39; to the comparator COIS over the line l 2  &#39;. On the other hand, when serial data is being transmitted from the master MAS to the slave SLV (i.e., when signal MS is logical &#34;1&#34;) the gate circuit GS 2  delivers the serial data SDO to the shift register SFRs&#39;. 
     A detection circuit, designated DTCS, is adapted to detect transmission errors, as well as a break in the sending line SL, receiving line RL and strobe line STL, when serial data SDO is being transmitted from the master to the slave, that is, when MS is a &#34;1.&#34; In particular, the master will send the 1-bit start bit at logical &#34;0&#34; before it sends the N-bit serial data, and the 1-bit alarm bit (which will be logical &#34;1&#34; in the absence of a transmission error) after it has sent the N-bit serial data. In the event of a transmission error or line breakage, however, the slave SLV will receive the start bit, which will be logical &#34;1,&#34; or the alarm bit, which will be logical &#34;0,&#34; this being detected by the detection circuit DTCS as a transmission error or as line breakage in a manner which is described below. DVS denotes a driver, and RVS, RVS&#39; denote receivers. TRFS denotes a transmission control circuit which receives strobe pulses STB from the transmission control circuit TRFM in the master MAS, and which responds by generating strobe signals STB, as well as signals MS, SM. 
     The operation of the present invention will now be described in connection with the transmission of N-bit serial data from the master MAS to the slave SLV. 
     In a case where the master MAS sends N-bit data to the slave SLV, N-bit parallel data (N=16), arriving over bus line BUSM from a memory (not shown), is set in the shift register SFRm. The transmission control circuit TRFM generates the signals MS, SM, at logical &#34;1&#34; and logical &#34;0, &#34; respectively, as well as the 18successive strobe pulses STB, consisting of the pulses S 1  through S 18 . The gate circuit GM 1  responds by delivering the start bit at logical &#34;0&#34; during the generation of the first pulse S 1 . The start bit is applied to the detection circuit DTCS through the driver DVM, sending line SL, receiver RVS, gate circuit GS 2 , and line l 1  &#39;. Gate circuit GS 2  is so controlled that, when MS is a &#34;1,&#34; an output will appear on line l 1  &#39; only and not on line l 2  &#39;. 
     Meanwhile, the transmission control circuit TRFS on the slave side receives the strobe pulses STB over the strobe line STL, and successively generates the strobe pulses STB (S 1  through S 18 ), as well as the signals MS, SM at logical &#34;1&#34; and logical &#34;0,&#34; respectively. These signals are applied to the various circuits in the slave. 
     The outputs of the AND gates AG 1  &#39;, AG 2  &#39; in the detection circuit DTCS are logical &#34;0&#34; if the slave SLV correctly receives the start bit of &#34;0&#34; logic, so that the output ALM, namely an alarm signal, of the OR gate OR&#39; is logical &#34;0.&#34; Hence, no alarm is issued. If there is an error in transmission, however, the bit content of the start bit goes to logical &#34;1,&#34; in a manner which will be described later, with the result that the output of AND gate AG 1  &#39; goes to logical &#34;1.&#34; This causes the output ALM of the OR gate OR&#39; to become logical &#34;1,&#34; so that an alarm indication of the transmission error is given. 
     When the second pulse S 2  of the strobe pulses STB is generated, the content of the shift register SFRm is shifted one bit to the right, so that the content of the first bit in the N-bit data, which bit was the least significant digit LSD in the shift register SFRm (the content of the bit being represented by the shaded portion of the signal SDO in FIG. 2A), is set in the shift register SFRs&#39; as the most significant digit MDS. The signal is transmitted via the gate circuit GM 1  &#39;, driver DVM, sending line SL, receiver RVS, gate circuit GS 2 , and line l 1  &#39;. The arrangement is such that gate circuit GM 1  delivers only the signal on line L 1  when signal MS is a logical &#34;1.&#34; 
     When the slave SLV receives the first bit of the N-bit data, the slave immediately sends the received bit content (represented by the shaded portion of the signal SDI in FIG. 2A) back to the master MAS through the line L 1  &#39;, gate circuit GS 1 , driver DVS, and receiving line RL. The arrangement is such that the gate circuit GS 1  delivers only the signal which appears on line L 1  &#39; when the signal MS is a logical &#34;1.&#34; The gate circuit GM 2  on the master side, upon receiving the 1-bit information which returns from the slave SLV, delivers this information over line l 2  to the comparator COIM which is being fed the serial data SDO. The gate circuit GM 2  is controlled so as to deliver the received signal to line l 2  only when the signal MS is a logical &#34;1.&#34; Since the signal (the shaded portion of signal SDO in FIG. 2A) being sent on line L 1  and the signal (the shaded portion of signal SDI in FIG. 2A) returning on line l 2  overlap for one-half the period of the strobe pulses, the comparator COIM, upon comparing the two signals, later delivers a signal at logical &#34;1&#34; to line L 3 . If there is no coincidence, the output of the comparator COIM is &#34;0&#34; and this will be sent out on the line L 3  subsequently. 
     As the content of the shift register SFRm is being shifted bit-by-bit as each of the strobe pulses S 3  through S 17  is generated, the content is delivered as serial data SDO. The shift register SFRs&#39; in the slave, on the other hand, stores the serial data SDO while the content of the register is shifted bit-by-bit. The slave SLV sends the received bit content back to the master MAS as serial data SDI through the line L 1  &#39;, gate circuit GS 1 , and driver DVS each time one bit of the data is received from the master. The master MAS, on the other hand, compares the sent signals SDO and the returned signals SDI sequentially bit-by-bit through the comparator COIM. 
     When the 18th strobe pulse S 18  is generated, the gate circuit GM 1  of the master sends the output of the comparator COIM out on the sending line SL as the alarm bit. The alarm bit is applied to the detection circuit DTCS through the driver DVM, sending line SL, receiver RVS, gate circuit GS 2 , and line l 1  &#39;. The alarm bit is logical &#34;1&#34; if there has been no error during the transmission of the N-bit serial data, and logical &#34;0&#34; if a transmission error has occurred. Accordingly, no alarm signal is issued in the absence of a transmission error, i.e., the alarm signal ALM is logical &#34;0.&#34; If a transmission error does take place, however, the output of the AND gate AG 2  &#39; in the detection circuit DTCS goes to logical &#34;1,&#34; so that the circuit issues an alarm signal, i.e., ALM is logical &#34;1.&#34; If ALM is logical &#34;0,&#34; the content of shift register SFRs&#39; is delivered as parallel data, but there is no output from the shift register SFRs&#39; if ALM is logical &#34;1.&#34; Thus, erroneous operation is prevented. 
     The foregoing operation relates to the transmission of serial data SDO from the master MAS to the slave SLV. It should be noted, however, that the operation is entirely the same for transmission of the serial data SDI&#39; from the slave SLV to the master MAS. The data to be transmitted from the slave SLV to the master MAS is stored in the shift register SFRs of the slave and transmitted bit-by-bit to the shift register SFRm of the master through the receiving line RL. 
     Detection of a break in the strobe line STL, sending line SL or receiving line RL is performed in the following manner. 
     A. Break in strobe line STL: 
     (a) If a break develops in the strobe line STL during the transmission of the serial data SDO from the master MAS to the slave SLV, the response from the slave will be clamped at either logical &#34;0&#34; or logical &#34;1&#34; from the time of the break onward. In other words, a break in the strobe line STL will not permit the strobe pulses STB to be generated on the slave side, thereby preventing the updating of the content of shift register SFRs&#39;. The response of the slave following the occurrence of the break is to send back to the master the content, either logical &#34;1&#34; or logical &#34;0,&#34; which was stored in the most significant digit MSD of the shift register SFRs&#39; immediately before the break. The result is a lack of agreement between the serial data SDO which was sent to the slave and the data SDI which was returned by the slave, so that the alarm bit goes to logical &#34;0.&#34; The detection circuit DTCs, therefore, issues an alarm as set forth above. Though an alarm cannot be issued if the serial data to be transmitted is all &#34;0&#34;s or all &#34;1&#34;s, such data is transmitted only rarely if at all; hence, in most cases, the alarm signal will be generated upon the completion of transmission. Furthermore, even if the alarm fails to be issued upon the completion of one transmission, the alarm signal will be delivered assuredly following the completion of the next transmission of the serial data SDO. 
     (b) If a break develops in the strobe line STL during the transmission of the serial data SDI&#39; from the slave SLV to the master MAS, the data to be received by the master is clamped, after the occurrence of the break, in the shift register SFRs as the last significant digit (either logical &#34;0&#34; or logical &#34;1&#34;). If the data is clamped at logical &#34;0,&#34; the alarm bit will go to logical &#34;0,&#34; and the detection circuit DTCM will issue the alarm when the final strobe pulse S 18  is generated. If the data is clamped at logical &#34;1,&#34; the start bit will go to logical &#34;1,&#34; and the detection circuit DTCM will issue the alarm upon the transmission of the subsequent 16-bit serial data SDI&#39;. 
     B. Break in receiving line RL: 
     (a) If a break develops in the receiving line RL during the transmission of the serial data SDO from the master to the slave, the data which the master receives from the slave will be clamped at either &#34;1&#34; or &#34;0,&#34; so that the detection circuit DTSC issues an alarm in the manner described above in connection with A(a). 
     (b) If a break develops in the receiving line RL during the transmission of serial data SDI&#39; from the slave to the master, the data which the master receives from the slave will be clamped at either &#34;1&#34; or &#34;0,&#34; so that the detection circuit DTCM issues an alarm in the manner described above in connection with A(b). 
     C. Break in sending line SL: 
     (a) If a break develops in the sending line SL during the transmission of seral data SDO from the master to the slave, the data which the slave receives from the master will be clamped at either &#34;0&#34; or &#34;1.&#34; If the data is clamped at &#34;0,&#34; the alarm bit will go to &#34;0&#34; and the detection circuit DTCS will issue the alarm when the strobe pulse S 18  is generated. If the data is clamped at &#34;1,&#34; the start bit will go to &#34;1&#34; and the detection circuit DTCS will issue the alarm upon the transmission of the subsequent serial data SDO. 
     (b) If a break develops in the sending line SL during the transmission of serial data SDI&#39; from the slave to the master, the data which the slave receives from the master will be clamped at either &#34;0&#34; or &#34;1.&#34; The result is a lack of agreement between the serial data which was sent from the slave to the master, and the data (all &#34;1&#34;s or all &#34;0&#34;s) which was returned by the master. Hence, the alarm bit goes to &#34;0&#34; so that the detection circuit DTCM issues the alarm. 
     It should be noted that while the start and alarm bits are described above are logical &#34;0&#34; and logical &#34;1,&#34; respectively, during the normal transmission of serial data, &#34;1&#34; and &#34;0&#34; may be employed as the respective bit logic during normal transmission. It is only necessary that the start and alarm bit logic not be identical. 
     In accordance with the present invention as described and illustrated above, received data is sent back to the sending side and both the sent and received data are compared, thereby allowing the detection of a transmission error if even one bit in the sent and returned 16-bit serial data is different. Furthermore, a break in the strobe, sending and receiving lines can be detected reliably by transmitting the start bit (either a &#34;0&#34; or a &#34;1&#34;) before the transmission of the N-bit data, and by transmitting the alarm bit (either a &#34;1&#34; or a &#34;0&#34;) after the transmission of the N-bit data. 
     It should also be noted that waste of serial data transfer time is reduced, despite the transmission error and line breakage detection capability, because only two bits are added to the N-bit serial data. 
     As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to beunderstood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.