Abstract:
An integrated circuit comprises a control input providing a connection to a capacitor. A delay circuit generates a delayed enable signal responsive to a provided enable signal. A second circuit performs a control function. A switching circuit responsive to the delayed enable signal connects the control input to the delay circuit in a first mode of operation and connects the control input to the second circuit in a second mode of operation.

Description:
PRIORITY CLAIM  
     This application claims benefit of U.S. Provisional Patent Application Ser. No. 61/075,389 filed Jun. 25, 2008 and entitled DUAL USE OF DELAY CAPACITOR, the specification of which is incorporated herein by reference in its entirety. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding, reference is now made to the following description taken in conjunction with the accompanying Drawings in which: 
       FIG. 1  is an illustration of a delay circuit; 
       FIG. 2  is an illustration of a compensation circuit, 
       FIG. 3  is an illustration of an output pin and associated capacitor capable of use for multiple functionalities within an integrated circuit; and 
       FIG. 4  is a flow diagram describing the operation of the circuit of  FIG. 3 . 
    
    
     DETAILED DESCRIPTION 
     Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout, the various views and embodiments of a dual use delay capacitor are illustrated and described, and other possible embodiments are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations based on the following examples of possible embodiments. 
     Within power management integrated circuits a sufficient number of output pins are required for the functionalities provided within the integrated circuit. Within the circuit there are pins dedicated to delay functionalities and pins dedicated to analog circuit function such as amplifier compensation. Customers may require an integrated circuit manufacturer to provide a large number of functionalities within a particular package/pin count in order to save on manufacturing costs. This may cause a situation where there are insufficient pins available to enable all of the desired functionalities within the integrated circuit. If a feature cannot be achieved, and this feature is necessary for the operation of an integrated circuit, a circuit designer has the option of implementing the feature on-chip, which would require considerable additional chip area and the associated costs, or alternatively, the designer can relax the specification of the chip so that the features can be eliminated. 
       FIGS. 1 and 2  illustrate the use of an external pin and capacitor for two different examples of chip implemented functionalities.  FIG. 1  illustrates the use of an output pin  102  and associated capacitor  104  with a delay circuit of an integrated circuit  106 . The delay circuit of  FIG. 1  is connected to the output pin  102  at node  108 . A current source  110  sources a current into node  108  to charge the capacitor  104  connected to pin  102 . The current source  110  is enabled via an enable signal provided at an enable pin  112 . The enable signal causes a switch S 1   114  to close connecting the current source  110  to system power VDD. Node  108  is also connected with the non-inverting input of a comparator  116 . The comparator  116  is connected at its inverting input a reference voltage VREF 1 . The comparator  116  compares the voltage across capacitor  104  at node  108  with the reference voltage VREF 1  to determine when the voltage across capacitor  104  exceeds the voltage VREF 1 . When this occurs, the output DELAY_EN signal goes to a logical “high” level. From the time that the enable signal applied at input pin  112  goes high, there is a time delay of T DEL  that occurs before the DELAY_EN signal at the output of comparator  116  goes high. The delay time T DEL  may be determined according to the equation (C 1 ×V REF1 )/I 1 . 
     The circuit illustrated in  FIG. 1  is one of many functions that are used within an integrated circuit  106  using an external output pin  102  and associated external components such as a capacitor C 1   104 . The delay circuit is typically used in a power sequence. Quite often the external pin  102  is dedicated to a delay function that is used only at the start of a power-on sequence when the chip is first enabled, and the pin  102  is no longer used by the integrated circuit  104  after completion of the power-on process. The value of the external capacitor  104  can be changed in order to change the delay time provided by the delay circuit. Typically, an external capacitor  104  is connected to a delay pin  102  and an internal current source  110  is used to ramp the voltage up to the external capacitor. When this voltage reaches a certain threshold level established by the value of V REF1 , the state of the output of the comparator  116  changes. This output is used to enable some function upon the integrated circuit  106 , and the pin  102  becomes dormant until the next time the chip is disabled/enabled and a new power-on sequence begins. 
     Referring now to  FIG. 2 , there is illustrated the use of the external pin  202  and a capacitor C 2   204  as a compensation network. The capacitor  204  is connected in series with a resistor R 1   206  between the external pin  202  and ground. The capacitor  204  and resistor  206  are used as part of a compensation network for amplifiers  207  and  208 . The capacitor  204  and resistor  206  are connected at node  210  which is at the output of GM amplifier  207  and at one of the inputs of amplifier  208 . The inverting input of amplifier  207  is connected to the FB pin  212 . The non-inverting input of amplifier  207  is connected to receive a reference voltage V REF2 . The capacitor  204  and resistor  206  are used to shape the frequency response of a closed loop system so that there is sufficient phase margin for stable operations of the amplifiers  207  and  208  to be maintained. These external compensation components are selected to optimize the compensation of the circuit. Thus in  FIG. 2 , pin  202  is being used for compensation, with the capacitor  204  and resistor  206  being part of a compensation network for the amplifiers. 
     Referring now to  FIG. 3 , there is illustrated a schematic diagram wherein an external control pin  302  and an external capacitor C 2   304  in series with a resistor R 2   306  are used for dual functions as both a delay circuit and a compensation circuit with respect to an integrated circuit device  308 . The capacitor  304  and resistor  306  are connected in series between the control pin  302  and ground. The pin  302  is connected to a pair of switches S 2   310  and S 3   312 . The switches  310  and  312  are controlled by a switch control signal T DEL  provided from the output of a latch circuit  314 . Switch  310  connects the capacitor  304  and control pin  302  to a delay circuit  316 . The switch  312  connects the control pin  302  and capacitor  304  to a compensation circuit  318 . 
     The delay circuit  316  comprises a comparator  320  having its non-inverting input connected to node  322  which is connected with switch  310 . The inverting input of comparator  320  is connected to a reference voltage source V REF1    324 . A current source  326  is connected between a switch  328  and node  322 . Switch  328  is responsive to an ENABLE signal provided at control pin  330  and connects the current source  326  to system power V DD  responsive to a logical “high” level on control pin  330 . The current source  326  provides a charging current to capacitor  304  when switch  310  is closed connecting pin  302  with node  322 . The ENABLE signal additionally enables the reference voltage source V REF1    324 . The ENABLE signal is applied through an inverter  325  to the reset input of latch circuit  314 . The output of the comparator  320  provides a delay enable signal (DEL_EN) to a latch circuit  314 . The output of the latch circuit  314  provides the delay signal T DEL  that controls the operation of switches  310  and  312 . 
     In a power-on or enable sequence, switch  310  is closed and switch  312  is open to connect pin  302  to the delay circuit  316 . Once the ENABLE signal actuates the delay circuit by closing the switch  328 , the current source  326  begins charging capacitor  304  through the control pin  302 . Once the capacitor  304  has been charged to a sufficient level such that the voltage at node  322  is greater than or equal to the voltage V REF1 , the output of the comparator  320  will drive the DEL_EN signal to a logical “high” level and apply this signal to the S input of latch circuit  314 . The output Q of the latch circuit  314  will also be driven to a logical “high” level which is applied to the switches  310  and  312  connected with control pin  302 . Once the T DEL  signal goes to a logical “high” level, switch  310  is opened and switch  312  is closed to connect the control pin  302  to the compensation circuit  318 . 
     Switch  312  connects control pin  302  to the compensation circuit at node  340 . An amplifier  342  has its output connected to node  340 . The inverting input of amplifier  342  is connected to the FB pin  344 . The non-inverting input of amplifier  342  is connected to a reference voltage source V REF2    346 . The reference voltage source  346  for V REF2  is enabled by the ENABLE signal. Node  340  also provides one input to an amplifier circuit  348 . The output of the amplifier  348  provides some type of control function output. 
     Thus, once the external pin  302  has finished being used for the delay function with delay circuit  316  as indicated by the T DEL  signal going to a logical “high” level, switch  310  is opened and switch  312  is closed to connect the external pin  302  to the compensation circuit  318 . The external pin  302  and compensation network consisting of capacitor  304  and resistor  306  are now connected to the compensation network  318  at node  340 . The value of the resistor  306  is chosen to have a negligible effect upon the delay circuit  316 . External control pins such as pin  302  that provide a one off delay function (i.e., are used for a short period of time when the chip is first enabled and then remain in the dormant state until the next power/enable cycle) are suitable candidates for being used for an additional purpose once the pins normal functions have been completed. Thus, once the control pin&#39;s  302  normal function has been completed, (e.g., the delay function), the internal switches  310  and  312  disconnect the external capacitor from the delay circuit and connect the pin to the amplifier to be compensated. The dual use of the external capacitor  304  requires that the capacitor be set to a suitable value to operate within both operations. This can normally be accommodated in a delay block by scaling the applied ramp current I 1  to a suitable level to drive the compensation capacitor to achieve the desired delay. 
     Referring now to  FIG. 4 , there is a flow diagram describing the operation of the circuit of  FIG. 3 . The process is initiated at step  404  by a power-on or enable process being initiated. Inquiry step  406  determines whether the ENABLE signal is active. If not, inquiry step  406  continues to monitor for an active ENABLE signal. Once an active ENABLE signal is detected, latch  316  is reset causing its Q output to a logical low level. The ENABLE signal also causes a current source I 1    110  and the V REF1  reference voltage to be turned on, as well as enabling comparator  320  at step  408 . Voltage source V REF1  is directly actuated by the ENABLE signal while current source  326  is actuated by the closing of switch  328  to connect the current source with system power V DD . Next, inquiry step  410  determines whether the capacitance voltage of capacitor  304  measured at node  322  is greater than or equal to the reference voltage V REF1 . If not, the process remains at inquiry step  410 . Once the capacitance voltage at node  322  is greater than or equal to the reference voltage V REF1 , the output of the comparator  320  is driven to a logical “high” level at step  412 . This output is latched at the logical “high” level at step  414  by the latch circuit  314 . This causes the T DEL  signal to disconnect the delay circuit  316  from control pin  302  and connect the compensation circuit  318  to the control pin  302  at step  416 . This is accomplished by opening switch  310  and closing switch  312 . The process is completed at step  418  until a next power-on or enable process is initiated at step  404 . 
     While the above description has described using the control pin  302  and associated capacitor  304  with respect to a compensation circuit once the delay functionality of the delay circuit  316  has been completed, it will be appreciated that other uses of the capacitor  304  and control pin  302  may be utilized by an associated integrated circuit  308  once the use of the control pin  302  and capacitor  304  for a delay functionality has been completed. This will provide the opportunity for control pins  302  and associated external circuitry to be used for a variety of functions that will increase the capabilities of an associated integrated circuit without requiring additional on-chip area to be devoted to a newly provided functionality or to require additional output or control pins to implement the additional functionalities. 
     It will be appreciated by those skilled in the art having the benefit of this disclosure that this disclosure provides a dual use delay capacitor. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to be limiting to the particular forms and examples disclosed. On the contrary, included are any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope hereof, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments.