Abstract:
An electronic sound generating circuit for an electronic device having standard signal generator including a first audio frequency signal generating circuit generating a first audio frequency signal, a second audio frequency signal generating circuit generating a second audio frequency signal having a frequency which differs from said first audio frequency signal, a mixing circuit mixing said first audio frequency signal and said second audio frequency signal to provide a mixed signal, and a tone generating circuit generating an audible tone in response to said mixed signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to improvements in an electronic tone used for the chime of a timepiece or the like. More particularly, the invention relates to an electronic sound generating circuit providing a sound which is closer to that of an actual mechanical tolling bell. 
     2. Prior Art 
     Various improvements have been made in the electronic tone used in the chime or melody of timepieces in order to make the electronic tone resembling a tone of an actual mechanical bell toll. For example, one improvement is an envelope effect, wherein the volume of an electronic tone is gradually attenuated with the passage of time. 
     However, even with these conventional improvements, the generated electronic tone lacks quality and depth of an actual mechanical bell toll. 
     There are two reasons for this. One is that the conventional artificial electronic tone includes only a single frequency component, whereas an actual mechanical bell toll includes a mixture of several frequency components. The other is that the volume of an actual mechanical bell toll does not merely attenuate with time but the volume undergoes slight changes while attenuating. 
     A sound produced by mixing several frequencies and by varying volume in small increments cannot be obtained with the frequency or volume varying method conceived of heretofore in the prior art. There is need of a novel method for producing such a sound. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is the primary object of this invention to provide an electronic sound generating circuit producing a sound having a peculiar quality and depth, such as a mechanical bell toll. 
     In keeping with the principles of the present invention, the object is accomplished by an electronic sound generating circuit for an electronic device having a standard signal generating means, comprising a first audio frequency signal generating circuit generating a first audio frequency signal, a second audio frequency signal generating circuit generating a second audio frequency signal having a frequency which differs from said first audio frequency signal by from 1 to 10 Hz, a mixing circuit mixing said first audio frequency signal and said second audio frequency signal to provide a mixed signal, and a tone generating circuit generating an audible tone in response to said mixed signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-mentioned features and objects of the present invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings in which: 
     FIGS. 1A, 1B are a block circuit diagram illustrated an embodiment of the present invention; 
     FIG. 2 is a structure of the hour contact and more detailed circuits of the chime control circuit and chime timing counter shown in FIG. 1; 
     FIGS. 3 and 4 are time charts of various signals used in the circuits of FIG. 2; 
     FIG. 5 is a more detailed circuit of the chime number control circuit shown in FIG. 1; 
     FIG. 6 is a time chart of various signals used in the circuit of FIG. 5; 
     FIG. 7 is more detailed circuits of the first and second audio frequency signal generating circuits, etc. shown in FIG. 1; 
     FIG. 8 and 9 are time charts of various signals used in the circuits of FIG. 7; 
     FIG. 10 is a modification of the first and second audio frequency signal generating circuits of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a block circuit diagram illustrated an embodiment of the present invention. In the illustrated embodiment, the invention is utilized to produce the chime of a timepiece. 
     In FIG. 1, reference numeral 2 denotes a standard signal generator, 4 a frequency divider circuit, 6 a wave shaping circuit, 8 a driver circuit, 10 a motor, 12 a wheel train, 13 a time indicating hands. These constitute an arrangement similar to that of the conventional analog display timepiece. 
     Reference numeral 14 denotes an hour contact which is incorporated within the wheel train 12. The hour contact 14 is closed exactly on the hour and then produces an ON signal 14a. In response to the signal 14a, a chime control circuit 16 produces a chime start signal 16a. The chime start signal 16a is applied to a chime timing counter 18. In response to the chime start signal 16a, the chime timing counter 18 counts the number of chimes and applies an envelope start signal 18a to an envelope generating circuit 20 and, at the same time, produces a reset release signal 18b for releasing first and second audio frequency signal generating circuit 26, 28 from the reset state. Further, a count signal 18c is applied to a chime number control circuit 22 which detects whether the count signal attains a value set for the count. If the set value is attained, the chime number control circuit 22 supplies a chime stop signal 22a to the chime timing counter 18. The number of chimes is set in the chime count control circuit 22 by operating a number setting switch 24. 
     In this embodiment, the first audio frequency signal generating cirucit 26 produces a first audio frequency signal 26a in response to the signal 18b from the chime timing counter 18. The second audio frequency signal generating circuit 28 produces a second audio frequency signal 28a in response to the signal 18b from the chime timing counter 18. The second audio frequency signal 28a has a frequency differing from the first audio frequency signal by from 1 to 10 Hz. 
     The first and second audio frequency signals 26a, 28a are applied to analog switches 30, 32, respectively. The analog switches 30, 32 also receive an envelope signal 20a from the envelope generating circuit 20 and convert the signals 26a, 28a into signals 30a, 32a having a gradually attenuated amplitude in accordance with the envelope signal 20a. The attenuated signals 30a, 32a from the analog switches 30, 32 are applied to a mixing circuit 34 and are mixed by the mixing circuit 34. A mixed signal 34a is applied to a tone generating circuit 36, whereby the tone generating circuit 36 generates a sound having a peculiar quality and depth, such as a mechanical bell toll. 
     The sound generated by the tone generating circuit 36 in the present invention comprises the first and second frequency which are attenuated. Therefore, the sound in the present invention resembles a real bell toll. 
     FIG. 2 shows a structure of the hour contact 14 and more detailed circuits of the chime control circuit 16 and chime timing counter 18 shown in FIG. 1. FIGS. 3 and 4 are time charts of various singals used in the circuits of FIG. 2. The hour contact 14 comprises a cam 41 fixed to a minute wheel 39 which rotates once in every hour, a lever 45 rotatably supported by a pin 49 and urged in the counterclockwise direction by a spring 51, a magnet 53 provided at one end of the lever 45 and a switch 55 disposed adjacent the magnet 53. The lever 45 is normally positioned as shown by the dotted line with the magnet 53 away from the switch 55. In this state, the switch 55 is in an off condition. At the right hour, a cam follower portion 45a provided at the upper end of the lever 45 engages the notch of the cam 41, whereby the lever 45 rotates to the position shown by the solid line. As a result, the magnet 53 comes adjacent the switch 55, therefore, the switch 55 becomes the on condition and produces the signal 14a. In FIG. 2, the chime control circuit 16 is shown as comprising a resistance 38, a condenser 40 and a flip-flop 42 having a terminal D connected to the hour contact 14 through the resistance 38 and condenser 40 and a terminal φ receiving 64 Hz signal from the frequency divider circuit 4. 
     The chime timing counter 18 comprises a reset circuit 43 composed of a flip-flop 44 and an inverter 46, a counter circuit 47 composed of flip-flops 48, 50, 52, 54 reset by a signal 18e from the flip-flop 44 and gates 58, 60, 62 and a timing signal generating circuit 63 composed of a counter 56 reset by the signal 18e, NOR gate 66 providing an envelope start signal 18a and NOR gate 64 providing a reset signal 18b. 
     As shown in FIG. 3, the flip-flop 42 of the chime control circuit 16 is responsive to the signal 14a provided from the hour contact 14 exactly on the hour to change the singal 16a from the low potential level (referred to hereinafter as the L level) to the high potential level (referred to hereinafter as the H level). The H level signal 16a is applied to the reset circuit 43 of the chime timing counter 18 through the inverter 46. The output Q of the flip-flop 44 attains to the L level in synchronism with the falling portion of the signal 18d. When the signal 18e goes to L level, the flip-flops 48, 50, 52, 54 of the counter circuit 47 and the counter 56 of the timing signal generating circuit 63 are released from the reset state, whereby the counter circuit 47 and the timing singal generating circuit 63 begin to operate. When the counter 56 operates, signals as shown in FIG. 4 are provided from the outputs Q 1  -Q 8  of the counter 56. These signals are applied to the NOR gate 64 and NOR gate 66, respectively, whereby pulses appear on the outputs of the NOR gate 64 and NOR gate 66, respectively. The envelope start signal 18a is applied to the envelope generating circuit 20. The envelope generating circuit 20 generates the envelope signal in response to the H level pulses which appear in the envelope start signal 18a. 
     On the other hand, the pulsed reset signal 18b is applied to the first and second audio frequency signal generating circuits 26, 28. The first and second audio frequency signal generating circuits 26, 28 are released from the reset state in response to the L level portion of the signal 18b and are reset in response to every H level portions of the signal 18b. The signal 18b from the NOR gate 64 is also applied to the clock terminal φ of the flip-flop 48 through an inverter 65. The output Q of the flip-flop 48 is changed to the H or L level in synchronism with every falling portions of the signal 18b. Therefore, the outputs Q of the flip-flops 50, 52, 54 are also changed in response to their respective output signals, i.e. the counter circuit 47 counts the number of the pulses appearing in the signal 18b. 
     The output signals 18f, 18g, 18h, 18i of the counter circuit 47 are applied to the chime number control circuit 22 and are compared with the chime number which is set by user. When the chime number counted by the chime timing counter 18 is corresponding to the chime number set by user in the chime number control circuit 22, the reset signal 22a is provided to the flip-flop 44 of the chime timing counter 18 from the chime number control circuit 22. Then, the flip-flop 44 is reset by the reset signal 22a, whereby the signal 18e is changed from the L level to the H level. Thus, the flip-flops 48, 50, 52, 54 and the frequency divider circuit 56 are reset again. 
     FIG. 5 shows a more detailed circuit of the chime number control circuit 22 shown in FIG. 1. FIG. 6 is a time chart of various singals used in the circuit of FIG. 5. When the number setting switch 24 is actuated for setting the chime number, a switching singal providing circuit 68 comprising flip-flops 70, 72 and AND gate 74 provides a switching singal. The switching singal is applied to counter circuit 76 comprising flip-flops 78,80, 82, 84 and gates 86, 88, 90, 92. Output signals 22b, 22c, 22d, 22e of the flip-flops 78, 80, 82, 84 are applied to a coincidence detection circuit 94 comprising exclusive OR gates 96, 98, 100, 102 and NOR gate 104 together with the signals 18f, 18g, 18h, 18i. A coincidence signal provided from the NOR gate 104 is applied to a reset signal generating circuit 106 comprising flip-flops 108, 110 and AND gate 112. The chime timing counter 18 is reset by the output signal 22a of the AND gate 112, as the above mention. 
     For example, as shown in FIG. 6, the counter circuit 76 is set to chime number &#34;3&#34; by actuating the switch 24, and then the output singals 22b, 22c, 22d, 22e of the flip-flops 78, 80, 82, 84 are set to H level, H level, L level and L level, respectively. In this state, when the signals 18f, 18g, 18h, 18i of the chime timing counter 18 become H, H, L and L level, respectively, by being counted the number of the pulses which appear in the signal 18a by the counter circuit 47 of the chime timing counter 18, the state of the signals 18f, 18g, 18h, 18i coincides with the state of the signals 22b, 22c, 22d, 22e. Therefore, all of the output signals 22f, 22g, 22h, 22i become L level, and then the output of the NOR gate 104 is changed to H level. Next, the single pulse appears in the output singal 22a of the reset signal generating circuit 106 in response to the H level signal 22j. By means of this pulse of the signal 22a, the chime timing counter 18 is reset, and the counter circuit 76 of the chime number control circuit 22 is advanced from its count value &#34;3&#34; to &#34;4&#34; for providing &#34;4&#34; chimes exactly on the next hour. 
     FIG. 7 shows more detailed circuits of the first and second audio frequency signal generating circuits 26, 28, envelope generating circuit 20, etc. The first audio frequency signal generating circuit 26 comprises a frequency divider circuit 114 for frequency-dividing a signal from the frequency divider circuit 4 of the timepiece down to a frequency of 65.536 KHz(=2 16  Hz), and a programmable frequency divider 116 for frequency-dividing an output signal 26b from the frequency divider circuit 114. The programmable frequency divider 116 is an eight-stage binary programmable frequency divider the frequency dividing ratio of which is set to 1/125. Accordingly, the output singal 26b (65.536 KHz=2 16  Hz) from the frequency divider circuit 114 is divided down to the singal 26a having a frequency ratio of 524 Hz. 
     The second audio frequency singal generating circuit 28 is constituted by a programmable frequency divider 118 for frequency-dividing the output singal 26b of the frequency divider circuit 114 in the first audio frequency signal generating circuit 26. The programmable frequency divider 118 is an eight-stage binary programmable frequency divider whose frequency dividing ratio is set to 1/124. Thus, the signal 26b (65.536 KHz=2 16  Hz) from the frequency divider circuit 114 is divided down to 529 Hz. 
     The programmable frequency divider 116, 118 of the first and second audio frequency signal generating circuit 26, 28 receive the reset singal 18b to their reset terminals. 
     The envelope generating circuit 20 comprises N-channel trnasistor 120 having a gate terminal receiving the envelope start signal 18a, and a condenser 122 and resistance 124 connected to each other in parallel. The N-channel transistor 120 goes to the conductive state by receiving the H level singal 18a, whereby the condenser 122 is charged. Then, the N-channel transistor 120 goes to the non-conductive state in response to the fall of the signal 18a, and the condenser 122 gradually discharges. 
     The analog switches 30, 32 comprise transmission gates 126, 128, inverter 130, 132 and P-channel transistor 134, 136, respectively. The transmission gate 126 receives the envelope signal 20a and the first audio frequency signal 26a and transmits the envelope signal 20a in accordance with the timing of the frequency of the signal 26a. The transmission gate 128 receives the envelope signal 20a and the second audio frequency signal 28a and transmits the envelope signal 20a in accordance with the timing of the frequency of the signal 28a. 
     The output signals 30a, 32a of the analog switches 30, 32 are applied to the mixing circuit 34 and are mixed in the mixing circuit 34. 
     The tone generating circuit 36 comprising an amplifier circuit 138 and a speaker 140 generates a sound in response to the mixed singal 34a from the mixing circuit 34. 
     The operation of this circuitry will now be described using the time charts of FIGS. 8 and 9. 
     The chime start signal 16a from the chime control circuit 16 shown in FIG. 2 goes from the L level to H level exactly on the hour, in response to which the reset signal 18b from the chime timing counter 18 goes from H level to L level to release the programmable frequency dividers 116, 118 from the reset state, whereby the 65.536 KHz (2 16  Hz) signal 26b from the frequency divider circuit 114 starts being frequency divided. Simultaneously, a single positive pulse appears in the envelope start signal 18a, whereby the envelope generating circuit 20 generates the envelope signal 20a shown in FIG. 8. The envelope signal 20a and the 524 Hz and 529 Hz signals 26a, 28a are applied to the analog switches 30, 32. Accordingly, the output signal 30a of the analog switch 30 is an attenuated signal having a frequency of 524 Hz with the envelope attenuation, and the output signal 32a of the analog switch 32 is an attenuated signal having a frequency of 529 Hz with the envelope attenuation. The output signals 30a, 32a are mixed by the mixing circuit 34. The result is a signal whose power and pulse width vary periodically in accordance with the balance of the frequencies of the first and second audio frequency signals 26a, 28a as shown in FIG. 9. This mixed signal 34a is applied to the tone generating circuit 36, in response to which the tone generating circuit 36 produces a sound whose power and frequency component vary in small increase and decrease. When the envelope waveform from the envelope generating circuit 20 vanishes, the reset signal 18b from the chime timing counter 18 goes from the L level to H level to reset the programmable frequency dividers 116, 118. Thereafter, the chime number control circuit 22 determines whether the prescribed number of chimes have been issued. If the prescribed number has not been attained, the reset signal 18b again goes from the H level to L level, a single positive pulse arrears in the envelope start signal 18a, and the operation for producing the chime tone is repeated as described above. 
     According to the present invention, in addition to employing the envelope effect in which volume is diminished gradually with the passage of time, volume and the contained frequency components are varied periodically in accordance with the balance of the frequencies of the first and second audio frequency signals 26a, 28a in small increase and decrease while the volume is being diminished. This produces quality and depth in the manner of an actual mechanical bell toll. 
     In the illustrated embodiment, the frequency difference between the first audio frequency signal and second audio frequency signal is 5 Hz, though it may be changed to any value between 1 and 10 Hz. In addition, while the first audio frequency signal generating circuit 26 utilizes the signal from the timepiece frequency divider circuit 4, an independent oscillator may be provided. Although the first audio frequency signal generating circuit 26 and the second audio frequency generating circuit 28 both use a programmable frequency divider, first and second oscillators 142, 144 having different oscillation frequencies may be provided as shown in FIG. 10. Further, in the illustrated embodiment, the present invention is applied to the generation of a chime in a timepiece. However, it is obvious that the invention may be applied to an electronic musical instrument or the like.