Abstract:
Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to and the benefit of Korean Patent Application No. 10-2008-0087332, filed Sep. 4, 2008, the disclosure of which is incorporated herein by reference in its entirety. 
     BACKGROUND 
     1. Field of the Invention 
     The present invention relates to a lock detection circuit and a lock detecting method, and more particularly, to a lock detection circuit capable of detecting a lock state of a phase locked loop (PLL) circuit and a lock detecting method. 
     2. Discussion of Related Art 
     In transmitting and receiving a digital signal using a digital clock, in order to clearly identify whether a received signal is 0 or 1, it is necessary to accurately discern a location where each clock starts and stops. However, transmitting a signal in a wired or wireless configuration causes the signal to be delayed according to a signal path, and its phase to be changed as well. Therefore, it may be unclear for a receiving part to know which parts correspond to a start point and a stop point to determine 0 and 1. 
     Under these circumstances, a circuit that synchronizes a start point of a clock with its stop point is required, and a phase locked loop (PLL) circuit functions to synchronize a start (0 degree) with a stop (360 degrees) of a period. 
     The PLL circuit compares a phase of a reference signal with that of a feedback signal from a voltage controlled oscillator (VCO) to synchronize the phase. It is used in various applications such as a communication system, etc. Thanks to recent developments in semiconductor technology, the PLL circuit can be implemented as semiconductor integrated circuit. 
       FIG. 1  is a block diagram of a general PLL circuit. 
     Referring to  FIG. 1 , a PLL circuit  100  includes a first frequency divider  110  dividing a frequency of a reference signal FREF, a second frequency divider  120  dividing a frequency of a feedback signal FVCO, a phase frequency detector  130  comparing a phase of a frequency-divided reference signal FREF′ with that of a frequency-divided feedback signal FVCO′ to output an up signal UP or a down signal DN depending on a phase difference, a lock detection circuit  140  detecting a lock state according to the up signal UP or the down signal DN output from the phase frequency detector  130  to output a low or high lock detection signal LKD, a charge pump  150  pumping charge according to the up signal UP or the down signal DN output from the phase frequency detector  130 , a loop filter  160  filtering a high frequency component from the signal output from the charge pump  150 , and a VCO  170  varying a frequency of the output signal FVCO according to a control voltage output from the loop filter  160 . 
     When a phase of the frequency-divided reference signal FREF′ is faster than that of the frequency-divided feedback signal FVCO′, the PLL circuit  100  raises an oscillation frequency so that a phase of the feedback signal FVCO becomes faster. Also, when a phase of the frequency-divided reference signal FREF′ is slower than that of the frequency-divided feedback signal FVCO′, the PLL circuit  100  lowers an oscillation frequency so that the phase of the feedback signal FVCO becomes delayed. 
     When the phase of the frequency-divided reference signal FREF′ and that of the frequency-divided feedback signal FVCO′ are locked by the synchronization, i.e., a high lock detection signal LKD is output from the lock detection circuit  140 , an output of the VCO  170  may be used for various application circuits. 
     Therefore, the lock detection circuit  140  is able to accurately detect the lock state of the PLL circuit, and for this purpose, it is necessary for the up signal UP and the down signal DN, which are output from the phase frequency detector  130 , to have an accurate state value. 
     The state value of the up signal UP and the down signal DN, which are output from the phase frequency detector  130 , will be described below in detail. 
       FIG. 2A  is a circuit diagram of a three-state phase frequency detector that is generally used in a PLL circuit,  FIG. 2B  illustrates a state machine of the phase frequency detector illustrated in  FIG. 2A , and  FIG. 2C  is a timing diagram of the phase frequency detector illustrated in  FIG. 2A . 
     Referring to  FIG. 2A , the three-state phase frequency detector includes two D flip-flops and one AND gate, and in the detector, a phase difference between a frequency-divided reference signal FREF′ and a frequency-divided feedback signal FVCO′ is detected at rising edges of the two signals to output an up signal UP and a down signal DN. Here, as illustrated in  FIG. 2B , when a phase of the frequency-divided reference signal FREF′ is faster than that of the frequency-divided feedback signal FVCO′, the state value moves to “state 0” or “state 1” depending on a former state. Further, when a phase of the frequency-divided reference signal FREF′ is more delayed than that of the frequency-divided feedback signal FVCO′, the state value moves to “state 0” or “state 2” depending on a former state. Moreover, when the frequency-divided reference signal FREF′ and the frequency-divided feedback signal FVCO′ are locked, “state 0” is maintained. 
     However, as illustrated in  FIG. 2C , delayed time of each logic circuit device of the phase frequency detector may periodically cause an abnormal interval (Trst interval) in which both the up signal UP and the down signal DN become 1. Also, despite the unlock state, the lock detection circuit may detect a lock state. 
     Therefore, research into a lock detection circuit capable of taking the delayed time of a logic circuit device to accurately detect a lock state has been progressively carried out, and as a result, a lock detection circuit as illustrated in  FIG. 3  has been disclosed. 
       FIG. 3  schematically illustrates a conventional lock detection circuit. 
     Referring to  FIG. 3 , the conventional lock detection circuit includes a delay circuit, seven NAND gates, two T-flip-flops, and four inverters, and only when a time difference between an up signal UP and a down signal DN is smaller than a predetermined reference signal FREF, a high lock detection signal LKD is output. 
     However, in order to implement the lock detection circuit, many logic circuit devices should be connected to each other, resulting in the complicated hardware implementation, its large size, and increased power consumption. 
     SUMMARY OF THE INVENTION 
     The present application is directed to a lock detection circuit capable of accurately detecting a lock state with a simple structure. 
     The present application is also directed to a lock detecting method capable of accurately detecting a lock state within a short time period. 
     One aspect of the present invention provides a lock detection circuit, including: a front-end lock detector receiving an up signal or a down signal based on a phase difference between a reference signal and a feedback signal, and outputting a preliminary lock detection signal indicating lock states of the reference signal and the feedback signal according to the up signal and the down signal. Here, the front-end lock detector includes: first and second delay devices respectively delaying the up and down signals for a predetermined time period and outputting them; a first D flip-flop receiving the delayed up signal and outputting the received signal in response to the down signal; a second D flip-flop receiving the delayed down signal and outputting the received signal in response to the up signal; and a NOR gate outputting a high or low preliminary lock detection signal depending on output signals of the first and second D flip-flops. 
     The lock detection circuit may further include a back-end lock detector receiving the preliminary lock detection signal from the front-end lock detector to output a preliminary lock detection signal that maintains a high state for a predetermined time period as a final lock detection signal. 
     The back-end lock detector may include: a third D flip-flop receiving the preliminary lock detection signal, delaying it as long as a time interval of the reference signal and outputting it; a fourth D flip-flop receiving the output signal of the third D flip-flop, delaying it as long as the time interval of the reference signal and outputting it; and an AND gate outputting a preliminary lock detection signal that maintains a high state for a predetermined time period according to the output signals of the third and fourth D flip-flops as a final lock detection signal. 
     Another aspect of the present invention provides a lock detecting method, including: delaying the up signal and the down signal for a predetermined time period when an up signal and a down signal are input according to a phase difference between a reference signal and a feedback signal; generating a first output signal when the delayed up signal is faster than the down signal, and generating a second output signal when the delayed down signal is faster than the up signal; and generating and outputting a preliminary lock detection signal indicating lock states of the reference signal and the feedback signal according to the first and second output signals. 
     In generating the first and second output signals, when the delayed up signal is faster than the down signal, the first output signal may be in a high state, and when the delayed down signal is faster than the up signal, the second output signal may be in a high state. In generating and outputting the preliminary lock detection signal, when the first and second output signals are in low states, the preliminary lock detection signal may be in a high state. 
     The lock detecting method may further include extracting a preliminary lock detection signal that maintains a high state for a predetermined time period from the preliminary lock detection signal generated in the process of generating and outputting the preliminary lock detection signal as a final lock detection signal. 
     The extracting of the preliminary lock detection signal may include: delaying the preliminary lock detection signal as long as a time interval of the reference signal; delaying the delayed preliminary lock detection signal as long as the time interval of the reference signal; and performing an AND operation on the first delayed preliminary lock detection signal and the second delayed preliminary lock detection signal to extract a preliminary lock detection signal maintaining a high state for a predetermined time period. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
         FIG. 1  is a block diagram of a general PLL circuit; 
         FIG. 2A  is a circuit diagram of a three-state phase frequency detector that is generally used in a PLL circuit; 
         FIG. 2B  illustrates a state machine of the phase frequency detector illustrated in  FIG. 2A ; 
         FIG. 2C  is a timing diagram illustrating operations of the phase frequency detector illustrated in  FIG. 2A ; 
         FIG. 3  schematically illustrates a conventional lock detection circuit; 
         FIG. 4  illustrates a lock detection circuit according to an exemplary embodiment of the present invention; and 
         FIGS. 5A and 5B  are timing diagrams illustrating operations of the lock detection circuit illustrated in  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Hereinafter, exemplary embodiments of the present invention will be described in detail. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms. Therefore, the following embodiments are described in order for this disclosure to be complete and enabling to those of ordinary skill in the art. 
       FIG. 4  illustrates a lock detection circuit according to an exemplary embodiment of the present invention, and  FIGS. 5A and 5B  are timing diagrams illustrating operation of the lock detection circuit illustrated in  FIG. 4 . 
     Referring to  FIG. 4 , a lock detection circuit  400  of to an exemplary embodiment of the present invention includes a front-end lock detector  400 A and a back-end lock detector  400 B. The front-end lock detector  400 A includes first and second delay devices D 1  and D 2 , first and second D flip-flops FF 1  and FF 2 , and a NOR gate NORG. The back-end lock detector  400 B includes third and fourth D flip-flops FF 3  and FF 4  and an AND gate ANDG. 
     The lock detection circuit  400  may be integrated with a PLL circuit or may be separated from a PLL circuit and it can be applied to electronic devices such as communication systems, an FM receiver or a multimedia system, which require lock determination of a PLL circuit. 
     Operations of the front-end lock detector  400 A will be described below. 
     The first and second delay devices D 1  and D 2  respectively receive an up signal UP and a down signal DN from a phase frequency detector (not shown) and delay them for a predetermined time period to respectively output the delayed up signal τ UP  and the delayed down signal τ DN . 
     Here, the delayed up signal τ UP  and the delayed down signal τ DN  are respectively input into each data input D of the first and second D flip-flops FF 1  and FF 2 , and the down signal DN and the up signal UP are respectively input into each clock input CK of the first and second D flip-flops FF 1  and FF 2 . 
     The first D flip-flop FF 1  outputs the delayed up signal τ UP  at a rising edge of the down signal DN, and the second D flip-flop FF 2  outputs the delayed down signal τ DN  at a rising edge of the up signal. 
     As illustrated in the timing diagram  FIG. 5A , when the delayed up signal τ UP  is faster than the down signal DN, an output signal Q DN  of the first D flip-flop FF 1  becomes high, and when the delayed down signal τ DN  is faster than the up signal UP, an output signal Q UP  of the second D flip-flop FF 2  becomes high. 
     Next, the NOR gate NORG outputs a preliminary lock detection signal LS in a high state, when both the output signal Q DN  of the first D flip-flop FF 1  and the output signal Q UP  of the second D flip-flop FF 2  are in low states. 
     Here, state transition delay of the up signal Up or the down signal DN may make the preliminary lock detection signal LS output from the NOR gate NORG to be in a high sate, as represented in a dotted line of  FIG. 5A , although it is not in a lock state. 
     Therefore, in the exemplary embodiment of the present invention, in order to prevent such a problem, only a preliminary lock detection signal LS maintaining a high state for a predetermined time period is output as a final lock detection signal LKD using the back-end lock detector  400 B, which will be described below in more detail. 
     First, the preliminary lock detection signal LS output from the front-end lock detector  400 A is input into D input of the third D flip-flop FF 3 , and an output y0 of the third D flip-flop FF 3  is input into D input of the fourth D flip-flop FF 4 . Here, a reference signal is input into each CK of the third and fourth D flip-flops FF 3  and FF 4 . 
     That is, the third D flip-flop FF 3  delays the preliminary lock detection signal LS as long as a time interval of a reference signal FREF, and the fourth D flip-flop FF 4  delays the preliminary lock detection signal that is delayed through the third D flip-flop FF 3  again as long as the time interval of the reference signal FREF. 
     Outputs y0 and y1 of the third and fourth D flip-flops FF 3  and FF 4  are input into the AND gate ANDG, and the AND gate ANDG outputs a final lock detection signal LKD when the outputs y0 and y1 of the third and fourth D flip-flops FF 3  and FF 4  are high. 
     Therefore, when the back-end lock detector  400 B receives the preliminary lock detection signal LS from the front-end lock detector  400 A, it outputs only a preliminary lock detection signal LS maintaining a high state for a predetermined time period as a final lock detection signal LKD. 
     As described above, the lock detection circuit  400  of the present invention can accurately detect a lock state using a simple structure, and as a result, the lock detection circuit may be compact in size and consume less electric power. Further, when a lock state is detected using the lock detection circuit  400  of the present invention, lock state detection procedures may be simpler, and the lock state may be detected within a shorter time period. 
     In the lock detection circuit  400  according to the exemplary embodiment of the present invention, the back-end lock detector  400 B may be modified. Also, in case that the front-end lock detector  400 A accurately detects a preliminary lock detection signal in an actual lock state, the back-end lock detector  400 B may be omitted. 
     According to the present invention, a lock detection circuit capable of detecting a lock state can be implemented in a simple structure, resulting in compact size and less consumption of electric power. 
     Also, according to the present invention, lock detection process may become simpler, and a lock state can be detected within a shorter time period. 
     While the invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.