Abstract:
The present invention relates to a semiconductor device; and, more particularly, to a delay adjusting circuit which is required to adjust a delay time of an internal circuit in a test mode and required to verify a characteristic and a margin of the semiconductor device. The delay adjusting apparatus according to the present invention comprises: a normal delayer for delaying an input signal from an external circuit; a delay time storage for maintaining a predetermined delay time produced by a control signal and delaying the input signal based on the predetermined delay time; and a selector for selectively outputting one of output signals from the normal delayer and the delay time storage in response to a test mode signal.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor device; and, more particularly, to a delay adjusting apparatus which is required to adjust a delay time of an internal circuit in a test mode and required to verify a characteristic and a margin of the semiconductor device.  
         BACKGROUND OF THE INVENTION  
         [0002]    [0002]FIG. 1 is a block diagram illustrating a conventional delay adjusting circuit. Referring to FIG. 1, the conventional delay adjusting circuit includes first to third delay parts  110  to  130  and first to fourth NAND gates  141  to  144 . The first delay part (delay 1 )  110  has six inverters to delay an input signal signal_in from an external circuit. These six inverters are in series connected to each other and work in a normal mode. The second delay part (delay 2 )  120  has two inverters to delay the input signal signal_in. These two inverters are also connected in series and work in a test mode. The delay time of the second delay part  120  is different from that of the first delay part  110  because the member of inverters in the first delay part  110  is different from that in the second delay part  120 . The third delay part (delay 3 )  130  has four inverters to delay the input signal signal_in. These four inverters are in series connected to each other and work in a test mode. The delay time of the third delay part  130  is different from that of the first and second delay parts  110  and  120  because the member of inverters in the third delay part  130  is different from that in the first and second delay parts  110  and  120 , respectively. The first NAND gate  141  receives an inverted signal of a test mode signal test_mode and an output signal of the first delay part  110 , thereby NANDing the inverted test mode signal and the output signal of the first delay part  110 . The second NAND gate  142  receives the inverted test mode signal, an output signal of the second delay part  120  and a test selection signal test_sel, thereby NANDing the received signals. The third NAND gate  143  receives the inverted test mode signal, an inverted signal of the test selection signal test_sel and an output signal of the third delay part  130 , thereby NANDing the received signals. The fourth NAND gate  144  receives output signals of the first to third NAND gates  141  to  143  to perform a NAND operation.  
           [0003]    In a normal mode, since the test mode signal test_mode is not activated and is in a low voltage level, the NAND gate  141  receiving the inverted test mode signal produces an output signal in response to the input signal signal_in. In this normal mode, the second and third NAND gates  142  and  143  are always in a high voltage level, irrespective of the input signal signal_in. The NAND gate  144  receives high voltage level signals from the second and third NAND gates  142  and  143  and an output signal (logic low level) from the first NAND gate  141 , thereby producing a delay signal which is determined by a delay time of the first delay part  110 . At this time, since the normal mode is not a test mode, the test selection signal test_sel is not activated and is in a low voltage level. Further, in the test mode, the first NAND gate  141  receiving an inverted signal of the test mode signal test_mode outputs a high voltage level signal irrespective of the input signal signal_in because the test mode signal is activated and is in a high voltage level.  
           [0004]    When a delayed signal from the second delay part  120  is required during the test mode operation, the test selection signal test_sel is activated and is in a high voltage level. In this case, the third NAND gate  143  receiving the inverted signal of the test selection signal always outputs a high voltage level signal, irrespective of the input signal signal_in. Therefore, only second NAND gate  142  produces an output signal responsive to the input signal signal_in. The fourth NAND gate  144  receives an output signal of the second NAND gate  142 , which is produced by the delay signal from the second delay part  120 , to receive the input signal signal_in.  
           [0005]    On the other hand, when a delayed signal from the third delay part  130  is required during the test operation, the test selection signal test_sel is activated and is in a high voltage level. In this case, the second NAND gate  142  receiving the inverted signal of the test selection signal always outputs a high voltage level signal, irrespective of the input signal signal_in. Therefore, only third NAND gate  143  outputs an output signal responsive to the input signal signal_in. The fourth NAND gate  144  receives an output signal of the third NAND gate  143 , which is produced by the delay signal from the third delay part  130 , to receive the input signal signal_in.  
           [0006]    However, since the above-mentioned delay adjusting device is limited to a few numbers of delay parts, only predetermined delay time can be achieved. As a result, the conventional delay adjusting device can not obtain different kinds of testing modes. Even if a member of delay parts and a decoding circuit can be considered in a modification circuit, each bit of the test address to select a delay part must be allocated to corresponding pins and lots of pins must be provided. Further, it is difficult to provide many numbers of pins which are sufficient to provide various delay time.  
         SUMMARY OF THE INVENTION  
         [0007]    It is, therefore, an object of the present invention to provide a delay adjusting device capable of providing different delay signals in semiconductor memory devices.  
           [0008]    It is another object of the present invention to provide a delay adjusting device which can receive different delay input signals and can provide different delay signals by storing the inputted delay signals.  
           [0009]    In accordance with an aspect of the present invention, there is provided a delay adjusting apparatus in a semiconductor device comprising: a normal delay means for delaying an input signal from an external circuit; a delay time storage means for maintaining a predetermined delay time produced by a control signal and delaying the input signal based on the predetermined delay time; and a selection means for selectively outputting one of output signals from the normal delay means and the delay time storage means in response to a test mode signal.  
           [0010]    In accordance with another aspect of the present invention, there is provided a delay adjusting apparatus in a semiconductor device comprising: a control signal divider for producing a plurality delay control signals using an input control signal in a test mode; and a plurality of unit delayers which are in series coupled to each other, wherein each unit delayer selectively outputs a delayed input data signal in response to each of the delay control signals. The control signal divider includes: a plurality of delayers, which are in series coupled to each other, for delaying the input control signal and outputting a plurality of delayed control signals; and a pulse adjusting means for adjusting and trimming a plurality of delayed control signals in response to a test mode signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:  
         [0012]    [0012]FIG. 1 is a block diagram illustrating a conventional delay adjusting circuit;  
         [0013]    [0013]FIG. 2 is a block diagram illustrating a delay adjusting circuit according to an embodiment of the present invention;  
         [0014]    [0014]FIG. 3 is a block diagram illustrating a delay time storage device, which has a delay register unit, in the delay adjusting circuit of FIG. 2;  
         [0015]    [0015]FIG. 4 is a timing chart illustrating the delay adjusting circuit of FIG. 2;  
         [0016]    [0016]FIG. 5 is a block diagram illustrating a unit delayer according to another embodiment of the present invention;  
         [0017]    [0017]FIG. 6 is a block diagram illustrating a delay register unit according to further another embodiment of the present invention; and  
         [0018]    [0018]FIG. 7 is a block diagram illustrating a clock signal adjusting unit according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]    Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be explained in detail.  
         [0020]    First, referring to FIG. 2, a delay adjusting device according to the present invention includes a normal delay part  210 , a delay time storage device  220  and a selection unit  230 . The normal delay part  210  delays an input signal signal_in inputted from an external circuit and outputs a delayed input signal to the selection unit  230 . The delay time storage device  220  stores a delay time, which is set up by a control signal, and outputs a delayed input signal to the selection unit  230  after delaying the input signal signal_in based on the delay time.  
         [0021]    The selection unit  230  receives a test mode signal test_mode. In case that the test mode signal test_mode is in a low voltage level, the selection unit  230  outputs a delay signal from the normal delay part  210  as an output signal and, in case that the test mode signal test_mode is in a high voltage level, the selection unit  230  outputs a delay signal from the delay time storage device  220  as an output signal.  
         [0022]    A first inverter  231  in the selection unit  230  inverts the received test mode signal test_mode and outputs the inverted test mode signal to a first NAND gate  232 . The first NAND gate  232  receives output signals of the first inverter  231  and the normal delay part  210  in order to perform the NAND operation and outputs the result of the NAND operation. A second NAND gate  233  in the selection unit  230  receives the test mode signal test_mode and an output signal of the delay time storage device  220  in order to perform the NAND operation and outputs the result of the NAND operation. Output signals of the first and second NAND gates  232  and  233  are inputted into a third NAND gage  234  and the third NAND gage  234  outputs a NAND operation signal as a delay signal delay_out.  
         [0023]    [0023]FIG. 3 is a block diagram illustrating the delay time storage device  220  in the delay adjusting circuit of FIG. 2. Referring to FIG. 3, the delay time storage device  220  includes a delay time determining unit  310  and a delay register unit  320 . The delay time determining unit  310  receives the test mode signal test_mode and a control signal ctrl. While the test mode signal test_mode is in a high voltage level, one of first to third delay control signals p 1  to p 3  is activated in a high voltage level and other two delay control signals are in a low voltage level.  
         [0024]    The delay time determining unit  310  includes a delay chain  311 , a pulse width adjusting unit  312  and a pulse width constraining unit  313 .  
         [0025]    The delay chain  311  includes a plurality of unit delay elements each of which receives the control signal ctrl. In this embodiment, the plurality of unit delay elements are made up of first to fifth unit delay elements  311   a  to  311   e.    
         [0026]    A first unit delay signal d 1  produced by the first unit delay element  311   a  goes from a low voltage level to a high voltage level after one unit delay time (T) from a rising edge of the control signal ctrl and goes from a high voltage level to a low voltage level with a falling edge of the control signal ctrl.  
         [0027]    A fourth NAND gate  311   a - 1  in the first unit delay element  311 a has two input terminals each of which receives the control signal ctrl and performs a NAND operation of the received signals, thereby outputting a result of the NAND operation to a second inverter  311   a - 2 . The second inverter  311   a - 2  inverts an output signal of the fourth NAND gate  311   a - 1  and outputs an inverted signal as the first unit delay signal d 1 .  
         [0028]    A second unit delay signal d 2  produced by the second unit delay element  311   b  goes from a low voltage level to a high voltage level after two unit delay times (2T) from a rising edge of the control signal ctrl and goes from a high voltage level to a low voltage level with a falling edge of the control signal ctrl.  
         [0029]    A fifth NAND gate  311   b - 1  in the second unit delay element  311   b  has two input terminals, each of which receives the control signal ctrl and the first unit delay signal d 1 , and performs a NAND operation of the received signals and outputs a result of the NAND operation to a third inverter  311   b - 2 . The third inverter  311   b - 2  inverts an output signal of the fifth NAND gate  311   b - 1  and outputs an inverted signal as the second unit delay signal d 2 .  
         [0030]    The third unit delay signal d 3  in the third unit delay element  311   c  goes from a low voltage level to a high voltage level after three unit delay times (3T) from a rising edge of the control signal ctrl and goes from a high voltage level to a low voltage level with a falling edge of the control signal ctrl, thereby producing a third unit delay signal d 3 ; however, the third unit delay signal d 3  is kept in a low voltage level because the control signal falls down after three unit delay times (3T) falls down. In the third unit delay element  311   c,  a sixth NAND gate  311   c - 1  in the third unit delay element  311   c  has two input terminals, each of which receives the control signal ctrl and the second unit delay signal d 2 , and performs a NAND operation of the received signals and outputs a result of the NAND operation to a fourth inverter  311   c - 2 . The fourth inverter  311   c - 2  inverts an output signal of the sixth NAND gate  311   c - 1  and outputs an inverted signal as the third unit delay signal d 3 .  
         [0031]    The fourth unit delay signal d 4  in the fourth unit delay element  311   d  goes from a low voltage level to a high voltage level after four unit delay times (4T) from a rising edge of the control signal ctrl and goes from a high voltage level to a low voltage level with a falling edge of the control signal ctrl, thereby producing a fourth unit delay signal d 4 ; however, the fourth unit delay signal d 4  is also kept in a low voltage level because the control signal falls down after three unit delay times (3T) falls down. In the fourth unit delay element  311   d,  a seventh NAND gate  311   d - 1  in the fourth unit delay element  311   d  has two input terminals, each of which receives the control signal ctrl and the third unit delay signal d 3 , and performs a NAND operation of the received signals and outputs a result of the NAND operation to a fifth inverter  311   d - 2 . The fifth inverter  311   d - 2  inverts an output signal of the seventh NAND gate  311   d - 1  and outputs an inverted signal as the fourth unit delay signal d 4 .  
         [0032]    Furthermore, the fifth unit delay signal d 5  in the fifth unit delay element  311   e  goes from a low voltage level to a high voltage level after five unit delay times (5T) from a rising edge of the control signal ctrl and goes from a high voltage level to a low voltage level with a falling edge of the control signal ctrl, thereby producing a fifth unit delay signal d 5 ; however, the fifth unit delay signal d 5  is also kept in a low voltage level because the control signal falls down after three unit delay times (3T) falls down. In the fifth unit delay element  311   e,  an eighth NAND gate  311   e - 1  in the fifth unit delay element  311   e  has two input terminals, each of which receives the control signal ctrl and the fourth unit delay signal d 4 , and performs a NAND operation of the received signals and outputs a result of the NAND operation to a sixth inverter  311   e - 2 . The sixth inverter  311   e - 2  inverts an output signal of the eighth NAND gate  311   e - 1  and outputs an inverted signal as the fifth unit delay signal d 5 .  
         [0033]    In the unit delay elements  311   a  to  311   e,  the unit delay signal is kept in a low voltage level if the control signal ctrl is falling down before a low voltage level goes to a high voltage level. That is, a high voltage level of the unit delay signal is limited in a high voltage level duration of the control signal ctrl.  
         [0034]    The pulse width adjusting unit  312  in the delay time determining unit  310  includes first to fourth unit control signal generators  312   a  to  312   d  which are in parallel connected to each other. Each of the unit control signal generators  312   a  to  312   d  receives two unit delay signals from the delay chain  311 .  
         [0035]    The first unit control signal generator  312   a  receives the first unit delay signal d 1  and the second unit delay signal d 2  and outputs a first set signal set 1 . In case that the first unit delay signal d 1  is in a high voltage level and the second unit delay signal d 2  is in a low voltage level, the first set signal set 1  is outputted in a low voltage level. Also, the first unit control signal generator  312   a  includes a seventh inverter  312   a - 1  and a ninth NAND gate  312   a - 2 . The seventh inverter  312   a - 1  receives and inverts the second unit delay signal d 2  and the ninth NAND gate  312   a - 2  receives the inverted unit delay signal from the seventh inverter  312   a - 1  and the first unit delay signal d 1  in order to perform the NAND operation.  
         [0036]    The second unit control signal generator  312   b  receives the second unit delay signal d 2  and the third unit delay signal d 3  and outputs a second set signal set 2 . In case that the second unit delay signal d 2  is in a high voltage level and the third unit delay signal d 3  is in a low voltage level, the second set signal set 2  is outputted in a low voltage level. Also, the second unit control signal generator  312   b  includes an eighth inverter  312   b - 1  and a tenth NAND gate  312   b - 2 . The eighth inverter  312   b - 1  receives and inverts the third unit delay signal d 3  and the tenth NAND gate  312   b - 2  receives the inverted unit delay signal from the eighth inverter  312   b - 1  and the second unit delay signal d 2  in order to perform the NAND operation.  
         [0037]    The third unit control signal generator  312   c  receives the third unit delay signal d 3  and the fourth unit delay signal d 4  and outputs a third set signal set 3 . In case that the third unit delay signal d 3  is in a high voltage level and the fourth unit delay signal d 4  is in a low voltage level, the third set signal set 3  is outputted in a low voltage level. Also, the third unit control signal generator  312   c  includes a ninth inverter  312   c - 1  and an eleventh NAND gate  312   c - 2 . The ninth inverter  312   c - 1  receives and inverts the fourth unit delay signal d 4  and the eleventh NAND gate  312   c - 2  receives the inverted unit delay signal from the ninth inverter  312   c - 1  and the third unit delay signal d 3  in order to perform the NAND operation.  
         [0038]    The fourth unit control signal generator  312   d  receives the fourth unit delay signal d 4  and the fifth unit delay signal d 5  and outputs a fourth set signal set 4 . In case that the fourth unit delay signal d 4  is in a high voltage level and the fifth unit delay signal d 5  is in a low voltage level, the fourth set signal set 4  is outputted in a low voltage level. Also, the fourth unit control signal generator  312   d  includes a tenth inverter  312   d - 1  and a twelfth NAND gate  312   d - 2 . The ninth inverter  312   a - 1  receives and inverts the fourth unit delay signal d 4  and the twelfth NAND gate  312   d - 2  receives the inverted unit delay signal from the tenth inverter  312   d - 1  and the fourth unit delay signal d 4  in order to perform the NAND operation.  
         [0039]    The pulse width constraining unit  313  includes first to third flip-flops  313   a  to  313   c.  The pulse width constraining unit  313  receives the first to fourth set signals set 1  to set 4  from the control signal generating unit  312 , while the test mode signal test_mode is in a high voltage level, and outputs one of the delay control signals p 1  to p 3  in a high voltage level in response to the first to fourth set signals set 1  to set 4 . At this time, only one of the first to third delay control signals p 1  to p 3  is activated in a high voltage level and other delay control signals are kept in a low voltage level.  
         [0040]    The first flip-flop  313   a  receives the test mode signal test_mode and the first and second set signals set 1  and set 2  and outputs the first delay control signal p 1 . When the first set signal set 1  goes to a low voltage level, the first flip-flop  313   a  makes the first delay control signal p 1  go to a high voltage level and, when the second set signal set 2  goes to a high voltage level, the flip-flop  313   a  makes the first delay control signal p 1  go to a low voltage level.  
         [0041]    The second flip-flop  313   b  receives the test mode signal test_mode and the second and third set signals set 2  and set 3  and outputs the second delay control signal p 2 . When the second set signal set 2  goes to a low voltage level, the second flip-flop  313   b  makes the second delay control signal p 2  to go a high voltage level and, when the third set signal set 3  goes to a high voltage level, the flip-flop  313   b  makes the second delay control signal p 2  to go a low voltage level.  
         [0042]    The third flip-flop  313   c  receives the test mode signal test_mode and the third and fourth set signals set 3  and set 4  and outputs the third delay control signal p 3 . When the third set signal set 3  goes to a low voltage level, the third flip-flop  313   c  makes the third delay control signal p 3  be in a high voltage level; however, the third delay control signal p 3  in this embodiment is kept in a low voltage level because the third set signal set 3  is kept in a high voltage level.  
         [0043]    On the other hand, the delay register unit  320  includes first to third unit delayers  321 ,  323  and  325  and first to third switches  322 ,  324  and  326 . The first to third unit delayers  321 ,  323  and  325  are in series couple to each other and the first to third switches  322 ,  324  and  326  respectively transfer output signals of the first to third unit delayers  321 ,  323  and  325  to an output terminal of the delay time storage device  220 .  
         [0044]    The first unit delayer  321  includes two inverters which are in series coupled to each other and receives the input signal signal_in, thereby outputting a delayed input signal. The first switch  322  transfers the delayed input signal to the output terminal of the delay time storage device  220  in response to a high voltage level of the first delay control signal p 1  from the first flip-flop group  313   a.    
         [0045]    The second unit delayer  323  also includes two inverters which are in series coupled to each other and receives the delayed input signal from the first unit delayer  321 , thereby outputting a delayed input signal. The second switch  324  transfers the delayed input signal, which is caused by the second unit delayer  323 , to the output terminal of the delay time storage device  220  in response to a high voltage level of the second delay control signal p 2  from the first flip-flop group  313   b.    
         [0046]    Also, the third unit delayer  325  includes two inverters which are in series coupled to each other and receives the delayed input signal from the second unit delayer  323 , thereby outputting a delayed input signal. The second switch  326  transfers the delayed input signal, which is caused by the third unit delayer  325 , to the output terminal of the delay time storage device  220  in response to the third delay control signal p 3  from the first flip-flop group  313   c.    
         [0047]    [0047]FIG. 5 is a block diagram illustrating a unit delayer according to another embodiment of the present invention. Referring to FIG. 5, a unit delayer  321 ′ according to another embodiment of the present invention includes two NAND gates  501  and  503  and two inverters  502  and  504 . The NAND gates  501  and  503  and the inverters  502  and  504  are alternatively coupled in series and each of the NAND gates  501  and  503  has two input terminals which receive the same input signal.  
         [0048]    [0048]FIG. 6 is a block diagram illustrating a delay register unit  320 ′ according to another embodiment of the present invention. The delay register unit  320 ′ includes a plurality of delay counters  610  to  630  which are enabled by an enable signal. The delay counter  610  receives the enable signal EN and the input signal signal_in and produces a delay input signal.  
         [0049]    In the delay counter  610 , an eleventh inverter  611  receives and inverts the input signal signal_in. A thirteen NAND gate  612  receives the enable signal EN and an output signal of the eleventh inverter  611  in order to perform a NAND operation.  
         [0050]    A twelfth inverter  613  inverts an output signal of the thirteenth NAND gate  612 , a thirteenth inverter  614  inverts an output signal of the twelfth inverter  613 , and a fourteenth inverter  615  coupled to an input terminal of the eleventh inverter  611  inverts an output signal of the thirteenth inverter  614 . Also, a fifteenth inverter  616  inverts the output signal of the thirteenth NAND gate  612 . A switch  641  transfers the output signal of the delay counter  610 ,  
         [0051]    Each of the delay counters  620  and  630  receives the enable signal EN and has a delay time twice as long as an amount of the delay in the delay counter  610 . A first transistor  621  in the delay counter  620  has a gate to which the output signal of the delay counter  610  is applied. A sixteenth inverter  622  is coupled to the first transistor  621  and inverts an output signal of the first transistor  621 . A seventeenth inverter  623  receives and inverts an output signal of the sixteenth inverter  622 , thereby forming a latch circuit together with the sixteenth inverter  622 . A second transistor  624  has a gate to which the output signal of the delay counter  610  is applied and is coupled to the sixteenth inverter  622 . An eighteenth inverter  625  is coupled to the second transistor  624  and inverts an output signal of the second transistor  624 . A fourteenth NAND gate  626  receives the enable signal EN and an inverted signal from the eighteenth inverter  625  and outputs the result of the NAND operation to the eighteenth inverter  625 . A nineteenth inverter  627  inverts an output signal of the eighteenth inverter  625  and outputs the inverted signal to the first transistor  621 . A switch  642  in the delay register unit  320 ′ transfers the output signal of the delay counter  620   
         [0052]    On the other a switch  643  in the delay register unit  320 ′ transfers the output signal of the delay counter  630 . The control signals p 1 , p 2  and p 3  are applied to the gate of the switches  641 ,  642  and  643 , respectively. In case that control signals p 1 , p 2  and p 3  are in a high voltage level, the switches  641 ,  642  and  643  respectively transfer an input voltage to the output terminal of the delay register unit  320 ′.  
         [0053]    [0053]FIG. 7 is a block diagram illustrating a clock signal adjusting unit according to the present invention. Referring to FIG. 7, an external clock buffer  710  temporally stores an external clock signal CLK and thereafter outputs the stored clock signal to a clock signal adjusting unit  700 . In FIG. 7, the delay register unit in FIG. 6 is denoted as the same reference numeral  320 .  
         [0054]    The clock signal adjusting unit  700  receives the enable signal EN, an output signal of the external clock buffer  710 , an output signal of the delay register unit  320  and the test mode signal test_mode. In case that the enable signal EN is in a high voltage level and the test mode signal test_mode is in a high voltage level, an internal clock generator outputs the output signal of the delay register unit  320  as an internal clock signal. In case that the test mode signal test_mode is in a low voltage level, the internal clock generator outputs the output signal of the external clock buffer  710  as the internal clock signal. Accordingly, the clock signal adjusting unit  700  produces internal clock signal using the delayed input signal in the test mode and the clock signal adjusting unit  700  produces internal clock signal using the external delayed input signal in a normal mode.  
         [0055]    In the clock signal adjusting unit  700 , a fifteenth NAND gate  721  is coupled to the delay register unit  320  for NANDing the output signal of the delay register unit  320  and the enable signal EN.  
         [0056]    As mentioned above, the clock signal adjusting unit  700  selectively transfers the output signal of the delay register unit  320  or the output signal of the clock buffer  710 . A twentieth inverter  722  inverts the test mode signal test_mode and the inverted test mode signal is inputted into the first and second pass gates  724  and  725 . Also, a twenty-first inverter  723  inverts the inverted test mode signal again and the re-inverted test mode signal is inputted into the second pass gates  724  and  725 . The output signal of the fifteenth NAND gate  721  is transferred to the internal clock generator in response to the inverted test mode signal and the re-inverted test mode signal and the clock signal from the clock buffer  710  is also transferred to the internal clock generator in response to the inverted test mode signal and the re-inverted test mode signal.  
         [0057]    Referring again to FIG. 4, the normal delay part  210  outputs a delayed signal to the selection unit  230  after delaying the input signal signal_in from an external circuit. Since the selection unit  230  receives the test mode signal test_mode in a low voltage level at the initial time, the selection unit  230  outputs the output signal of the normal delay part  210  as a delayed signal. That is, the first inverter  231  inverts the test mode signal test_mode and outputs the inverted test mode signal in a high voltage level to the first NAND gate  232 . Since the first NAND gate  232  performs the NAND operation of the test mode signal test_mode and the output signal of the normal delay part  210  and outputs the result of the NAND operation to the third NAND gate  234 , the output signal of the normal delay part  210  is reflected on the output signal of the delay adjusting circuit in FIG. 2. The second NAND gate  233  performs the NAND operation of the test mode signal test_mode of a low voltage level and the output signal of the delay time storage device  220  and outputs the result of the NAND operation to the third NAND gate  234 . Accordingly, the output signal of the delay time storage device  220  is reflected on the output signal of the delay adjusting circuit in FIG. 2.  
         [0058]    In the test mode, the delay time storage device  220  outputs the delayed input signal signal_in to the selection unit  230  based on the delay control signals p 1  to p 3  which are created by the control signal ctrl. The control unit  310  receives the test mode signal test_mode of a high voltage level during the test mode operation. The first unit delay element  311   a  in the delay chain  311  receives the control signal ctrl and delays the rising edge of the control signal ctrl by the delay time T. Further, since the second to fifth unit delay elements  311   b  to  311   e  are in series connected to each other and each of them receives an output signal of the previous unit delay element, the second to fifth unit delay elements  311   b  to  311   e  delay the rising edge of the control signal ctrl by the delay time 2T, 3T, 4T and 5T, respectively. However, it should be noted that the output signals of the first to fifth unit delay elements  311   a  to  311   e  are limited within the high voltage level so that a high voltage level is not shown on the third unit delay signal d 3 . The amount of the delay time T is determined by the NAND gate and the inverter in each of the first to fifth unit delay elements  311   a  to  311   e.  The first to fourth unit control signal generators  312   a  to  312   d  in the pulse width adjusting unit  312  respectively have one inverter and one NAND gate which receives the adjacent two unit delay signals so that they controls the pulse width of the unit delay signals and outputs the first to third set signals set 1  to set 3 . The first to third flip-flops  313   a  to  313   c  in the pulse width constraining unit  313  respectively produces the first to third delay control signals p 1  to p 3 . As shown in FIG. 4, the first set signal set 1  is in a high voltage level at the first time. When the first set signal set 1  goes from the high voltage level to a low voltage level, the first delay control signal p 1  goes to a high voltage level and, when the second set signal set 2  goes from a high voltage level to a low voltage level, the first delay control signal p 1  goes to a low voltage level. Since the set signal set 3  is in a high voltage level, the second delay control signal p 2  is in a high voltage level for 3T within the test mode. Accordingly, high voltage levels of the first to third delay control signal p 1  to p 3  are not overlapped.  
         [0059]    As illustrated above, in accordance with the present invention, different delay times can be provide in the different test modes. Further, since the present invention use a control signal to provide the different delay time, the structure of the delay adjusting circuit can be simplified.  
         [0060]    Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.