Abstract:
Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC&#39;s current demands.

Description:
FIELD 
     Aspects of the present invention generally relate to voltage regulation and, more particularly, to a parallel combination of a low dropout voltage regulator with a switching-mode power supply to regulate voltage. 
     BACKGROUND 
     Many functions of an advanced electronic device, such as a mobile phone, are implemented in a system-on-a-chip (SoC) integrated circuit. The SoC consumes current that changes with the number and kind of operations it performs. Descriptions of an element in terms of current or power are interchangeable after scaling by a respective voltage. The operations performed can change rapidly, for example, a few nanoseconds. The change in current consumption can be large, for example, a few amps. This results in a large current time derivative (dI/dt) that can interfere with operation of the SoC. 
     A power distribution network supplies power, for example, as a voltage supply, to the SoC. The SoC may be packaged in an integrated-circuit package that may be mounted on an interconnection substrate, such as a printed circuit board, for connection with other components including, for example, a power supply and battery. The power distribution network includes connections through the printed circuit board and integrated-circuit package. The connections of the power distribution network can have substantial parasitic inductance. This inductance combined with the large current time derivatives can cause large spike-like dips in the supply voltage, also referred to as droop, in the voltage supplied to the SoC. The droop can be so large as to interfere with proper operation of the device. 
     The voltage level supplied to the SoC is generally increased (which may be referred to as guardbanding) by the amount of voltage droop so the “drooped” voltage is sufficient for proper operation of the SoC. Guardbanding the voltage level increases power consumption and is undesirable, for example, due to increased temperature and decreased battery duration. Some prior systems have attempted to reduce the voltage droop, for example, by reducing inductance in the power distribution network or adding decoupling capacitors on or close to the SoC. For example, external landside capacitors (LSCs) and embedded-passive-substrate (EPS) capacitors may be added during routing of the PDN. Added decoupling capacitors may only slightly reduce the voltage droop. Additionally, they can be size and cost prohibitive. 
     SUMMARY 
     In one aspect, a hybrid parallel power supply is provided that includes: a first power supply connected to a power rail and configured to supply current to a load device via the power rail, the first power supply being further configured to regulate the power rail to a first target voltage level; and a voltage regulator connected to the power rail and configured to supply current to the load device via the power rail, the voltage regulator being further configured to regulate the power rail to a second target voltage level. 
     In one aspect, a method is provided for of supplying power to a load device. The method includes: supplying current from a power supply to the load device via a power rail at a first target voltage level; and supplying current from a voltage regulator to the load device via the power rail at a second target voltage level. 
     In one aspect, a hybrid parallel power supply is provided that includes: a first means for supplying power connected to a power rail and configured to supply current at a first target voltage level to a load device via the power rail; and a means for regulating voltage connected to the power rail and configured to supply current at a second target voltage level to the load device via the power rail. 
     Other features and advantages of the present invention should be apparent from the following description which illustrates, by way of example, aspects of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The details of the present invention, both as to its structure and operation, may be gleaned in part by study of the accompanying drawings, in which like reference numerals refer to like parts, and in which: 
         FIG. 1  is a schematic diagram of a model of a power distribution network; 
         FIG. 2  is a graph of a droop characteristic of a power distribution network in the time domain; 
         FIG. 3  is a graph of impedance of a power distribution network in the frequency domain; 
         FIG. 4  is a graph of frequency responses of a switching-mode power supply and a low dropout voltage regulator; 
         FIG. 5  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment; 
         FIG. 6  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment; 
         FIG. 7  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment; 
         FIG. 8  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment; 
         FIG. 9  is a time-domain graph of a droop characteristic of a hybrid parallel power supply according to a presently disclosed embodiment; and 
         FIG. 10  is a flowchart of a process for supplying power to an electronic device according to a presently disclose embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description set forth below, in connection with the accompanying drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in simplified form in order to avoid obscuring such concepts. 
       FIG. 1  is a schematic diagram of a model of a power distribution network (PDN). The PDN may be segregated into interconnect domains corresponding to a die domain  105 , a package domain  110 , a power-supply domain  112 , and a circuit-board domain  115 . Each of the PDN interconnect domains includes respective combinations of resistances, capacitances, and inductances that form a characteristic impedance for that domain. The resistances, capacitances, and inductances may be referred to as parasitic elements. These parasitic elements may be aggregated into equivalent component values of resistance, capacitance, and inductance that are present between components mounted within the PDN interconnect domains. For example, the circuit-board domain  115  may contribute series inductance due to the traces conducting current from a battery  165  to a power supply  170  in the power-supply domain  112 . The components within the PDN interconnect domains may have equivalent values of resistance, capacitance, and inductance that interact electrically with the parasitic elements of the PDN interconnect domains. 
     In the PDN model of  FIG. 1 , the circuit-board domain  115  includes a circuit-board-inter-planar capacitance  125  that may aggregates per unit length of interconnect traces across the interconnect substrate. The interconnect traces also contribute a circuit-board-equivalent-series resistance  120  and a circuit-board-equivalent-series inductance (L-pcb)  130  that aggregate per unit length of the trace. 
     The battery-equivalent impedance includes an equivalent-battery-output resistance  175  in series between the battery  165  and the parasitic elements of the circuit-board domain  115 . The power supply  170  in the power-supply domain  112  receives power from the battery  165  through the equivalent-battery-output resistance  175 , the circuit-board-equivalent-series resistance  120 , and the circuit-board-equivalent-series inductance  130 . The power supply  170  includes an equivalent-power-supply-output resistance  180 . Other impedances of the power supply may be lumped into an equivalent-power-supply output impedance  185  including series inductance, resistance, and capacitance. A power-supply-domain inductance  190  models the inductance encountered in routing traces between the power supply  170  and the package domain  110 . 
     In a fashion similar to that of the circuit-board domain  115 , the package domain  110  includes a package-inter-planar capacitance  135 , a package-equivalent-series inductance  140 , and a package-equivalent-series resistance  145 . Each of these parasitic elements aggregates per unit length that the PDN runs through the package domain  110 . The die domain  105  is modeled with an equivalent-load impedance  150  and a switched-equivalent-load impedance  155 . The equivalent-load impedance  150  represents portions of the SoC (which from a power distribution network viewpoint may be referred to as the load) that are not switching and/or portions of SoC circuitry that are in a continuous or standby operation. The switched-equivalent-load impedance  155  represents portions of SoC circuitry that are activated or deactivated according to particular operations of the SoC. A switch  160  symbolically represents the switched activity of the switched-equivalent-load impedance  155 . 
       FIG. 2  is a graph of the droop characteristic of a power distribution network in the time domain. The droop characteristic will be described with reference to the PDN of  FIG. 1  but similar effects occur in other systems. The graph shows a supply voltage  215  at the SoC in the die domain  105 . The y-axis of the graph is voltage and the x-axis of the graph is time. Initially, the SoC draws a low level of current from the battery  165  via the power supply  170 . At time  250 , the SoC switches to drawing a high level of current. The low level of current is modeled by the switch  160  in the load model being open and the high level of current is modeled by the switch  160  being closed. Initially, the supply voltage  215  (at the load) is at a nominal voltage level. At time  250 , the current drawn by the load increases rapidly. This increase in current is satisfied by additional current from the battery  165  flowing through the circuit-board domain  115 , the package domain  110 , power-supply domain  112 , and the die domain  105 . The inductances in this path result in a spike-like dip  205  in the supply voltage  215 . The spike-like dip  205  may result in the supply voltage  215  dropping below a minimum level for proper operation of the SoC. For example, in some systems, a droop characteristic  210  may be as much as an 18-30% drop in the supply voltage  215  for a 2.3 amp load-current transient occurring in a 4 ns timeframe. 
       FIG. 3  is a graph of impedance of a power distribution network in the frequency domain. The graph will be described with reference to the power distribution network of  FIG. 1 ; however, other networks result in similar impedances. The graph shows several impedance peaks that correspond to the respective impedances formed from parasitic elements in the respective PDN interconnect domains. A first impedance peak  305  corresponds to the current limiting impedances in the die domain  105 . The first impedance peak  305  may be primarily associated with the frequency dependent impedances seen by the portion of the PDN path on-die. The first impedance peak  305  may have a center frequency of about 100 MHz and may be the largest impedance peak. A second impedance peak  310  corresponds to the current limiting impedances created by the parasitic elements formed as the PDN is routed through the package domain  110 . The second impedance peak  310  may have a center frequency of about 2 MHz. A third impedance peak  315  corresponds to the current limiting impedances caused by the parasitic elements in the circuit-board domain  115 . The third impedance peak  315  may have a center frequency of about 100-200 kHz. When variations in SoC currents occur at or near the frequencies of the impedance peaks, the effect of voltage droop is increased. 
     The system of  FIG. 1  includes the power supply  170  between the battery  165  and the load device to provide voltage regulation and avoid droop characteristics. The power supply  170  may be a switching-mode power supply (SMPS) and provide power to the load device with the degree of supply voltage regulation that is available according to the regulating abilities of the SMPS. The SMPS may be implemented within the circuit-board domain  115  on a separate die from the load device and provide power through the circuit board interconnection layers to the SoC die (load device in the die domain  105 ). The SMPS receives power from the battery  165 . The battery  165  connects to the SMPS through the circuit board. The SMPS is coupled to the die through the parasitic elements introduced by the interconnection path through the circuit-board domain  115  and the package domain  110 . These interconnection path parasitic elements correspond to the package-inter-planar capacitance  135 , the package-equivalent-series inductance  140 , the package-equivalent-series resistance  145 , and the power-supply-domain inductance  190  described above. 
       FIG. 4  is a graph of frequency responses of a switching-mode power supply (SMPS) and a low dropout voltage regulator (LDO). The graph includes a SMPS frequency response  405  and an LDO frequency response  425  plotted versus frequency. The SMPS frequency response  405  and the LDO frequency response  425  are plotted in terms of output power in  FIG. 4 . Other measures, for example, current, may also be used. The frequency responses are generally flat at low frequencies and then decline at higher frequencies. The SMPS frequency response  405  may be described as having a SMPS corner frequency  410  where the power is attenuated by 3 dB (or a factor of two) and a corresponding SMPS bandwidth  415 . Similarly, the LDO frequency response  425  may be described as having a LDO corner frequency  430  and a corresponding LDO bandwidth  435 . 
     An exemplary SMPS may have a bandwidth of about 2 MHz. Generally, the SMPS bandwidth  415  may occur at about one-fifth of the SMPS clock frequency. This bandwidth is not sufficient for the SMPS to supply rapidly changing power requirements that can occur in an SoC. The SMPS is, however, suited for supplying relatively large amounts of current with a high efficiency. For example, the SMPS may be able to supply 3.0 A with an efficiency of about 85%. 
     An exemplary LDO may have a bandwidth of about 600 MHz. This bandwidth is much better suited than the SMPS bandwidth for supplying rapidly changing power requirements that can occur in an SoC. The LDO is, however, less efficient than the SMPS. For example, an LDO that receives a 1.2 V input supply voltage and produces a 0.9 V output will have an efficiency less than 75%. 
       FIG. 5  is a functional block diagram of an electronic system including a hybrid parallel power supply according to a presently disclosed embodiment. The system uses a hybrid parallel power supply to provide power to a load device  560 . The hybrid parallel power supply connects a power supply (e.g., a switching-mode power supply) in parallel with a voltage regulator (e.g., a low dropout voltage regulator). The hybrid parallel power supply combines advantageous features of both switching-mode power supplies and low dropout voltage regulators. The hybrid parallel power supply is power efficient and can supply a stable voltage to load device, such as a smartphone SoC, whose current demand rapidly changes. 
     The hybrid parallel power supply includes a first power supply (“SMPS1”)  505  connected in parallel with a voltage regulator (“LDO”)  510 . The first power supply  505  supplies power to a power rail  520 . The first power supply  505  works to regulate the power rail  520  to a first target voltage level, for example, 0.9 V. The first target voltage level may be configurable, for example, using a control register. The first power supply  505  receives power from a first supply terminal  545  (e.g., connected to the battery  165  in the system of  FIG. 1  via connections on a circuit board  515 ). The first power supply  505  is able to supply power to the power rail  520  with high efficiency. The first power supply  505  may be a switching-mode power supply (SMPS). 
     The voltage regulator  510  also supplies power to the power rail  520 . The voltage regulator  510  works to regulate the power rail  520  to a second target voltage level. The second target voltage level may be configurable, for example, using a control register. The voltage regulator  510  has an input connected to a second supply terminal  540  from which the voltage regulator  510  receives power. The voltage regulator  510  is able to provide current with a high-frequency-response characteristic to the power rail  520 . The voltage regulator  510  may be a low dropout voltage regulator (LDO). An LDO can operate with low headroom (difference between the input voltage and output voltage), for example, regulating a 1.2 V input to produce a 0.9 V output. 
     The voltage regulator  510 , in an embodiment, operates with a Class-B current mode output. Such circuits can have high bandwidths, for example, 600 MHz. The Class-B current mode output of the voltage regulator  510 , in contrast with a push-pull output, sources current to the power rail  520  (e.g., to the load device  560 ) when the voltage on the power rail  520  is below the second target voltage level but does not sink current from the power rail  520  when the voltage on the power rail  520  is above the second target voltage level. This facilitates connecting the voltage regulator  510  and the first power supply  505  in parallel to the power rail  520 . 
     The first power supply  505  and the voltage regulator  510  operate to regulate the voltage level of the power rail  520 . This voltage regulation may be understood as the monitoring of the voltage level of the power rail  520  and when the voltage level differs from the respective target voltage level, changing operation of circuits driving the power rail  520  so that the voltage level moves toward the target voltage level. The voltage level of the power rail  520  may vary due, for example, to inexact target voltage levels in the first power supply  505  and the voltage regulator  510 , output impedances of the first power supply  505  and the voltage regulator  510 , and response times of the first power supply  505  and the voltage regulator  510  to changes in current demand of the load device  560 . 
     The second target voltage level, to which the voltage regulator  510  regulates the power rail  520 , may be different from the first target voltage level, to which the first power supply  505  regulates the power rail  520 . The second target voltage level may be, for example, an offset voltage less than the first target voltage level. For example, in a hybrid parallel power supply where the first target voltage level is 0.9 V, the second target voltage level may be 088 V. In this arrangement, the first power supply  505  may supply most of the current dissipated by the load device  560  with the voltage regulator  510  rapidly supplying current in response to any dips in the voltage on the power rail  520 . 
     The hybrid parallel power supply of  FIG. 5  includes a second power supply (“SMPS2”)  530  to supply power to the voltage regulator  510  via second supply terminal  540 . The second power supply  530  works to drive the first supply terminal  545  to a third target voltage level. The third target voltage level may be chosen, for example, to allow efficient operation of the voltage regulator  510 . The third target voltage level may also be a level used by other components in the system. The third target voltage level may be, for example, 1.2 V when the nominal level on the power rail  520  is 0.9 V. The second power supply  530  is able to supply power to the voltage regulator  510  with high efficiency. The second power supply  530  receives power from the first supply terminal  545 . The second power supply  530  may be a switching-mode power supply. 
     The voltage regulator  510  and the load device  560  may be fabricated on a first die (“DIE 1”)  525 . Since the voltage regulator  510  and the load device  560  are located together, parasitic impedances between the voltage regulator  510  and the load device  560  are small. Portions of the power rail  520  may also be fabricated on the first die  525 . Board and package parasitic impedances do not impair the connection between the voltage regulator  510  and the load device  560 . 
     In the embodiment of  FIG. 5 , the first die  525  includes an on-die capacitor  550  connected to the second supply terminal  540 , which supplies power to the voltage regulator  510 . The on-die capacitor  550  can supply current to the voltage regulator  510  with a high-frequency-response characteristic. The on-die capacitor  550  supports the voltage regulator  510  supplying current to the load device  560  with a high-frequency-response characteristic and aids in reducing a droop characteristic that would otherwise occur on the power rail  520  when the current demand of the load device  560  rapidly changes. The on-die capacitor  550  stores more charge than a capacitor on the power rail  520  due to the higher voltage of second supply terminal  540  compared to the power rail  520 . As a result, the parallel combination of the voltage regulator  510  and the first power supply  505  may operate without (or with little) further capacitance, such as a bulk capacitor, an external capacitor, a landside capacitor, or an embedded-passive-substrate (EPS) capacitor. According to certain exemplary embodiments, the on-die capacitor  550  may be about 220 nF. 
     The on-die capacitor  550  may alternatively be fabricated external to the first die  525 , for example, on a circuit board or integrated circuit package, or a combination of on-die and external capacitors. Provisioning of capacitance on die, on package, or on circuit board may be determined according to the relative costs and performance of the respective implementations. These costs may include the costs of capacitors, interconnection, and package pins. Performance of the power distribution network generally improves with capacitance closer to the load device. 
     The first power supply  505  and the second power supply  530  may be fabricated on a second die (“DIE 2”)  535 . Combining the voltage regulator  510  and the load device  560  on the first die  525  and combining the first power supply  505  and the second power supply  530  on the second die may allow the various components to be manufactured using fabrication processes that are selected for the particular requirements of the components. For example, the voltage regulator  510  and the load device  560  may be manufactured using a high-density complementary metal-oxide-semiconductor (CMOS) process that allows many functions to be provided by the load device  560  and the first power supply  505  and the second power supply  530  may be manufactured using a high-power process that allows high efficiency power supplies. The first die  525  and the second die  535  may be mounted (directly or using integrated circuit packages) on an interconnection substrate, such as the circuit board  515 . In an embodiment, the second die  535  may be a power-management integrated circuit (PMIC). 
     A system using a hybrid parallel power supply may be more power efficient than systems using an SMPS, an LDO, or a series SMPS-LDO combination. The efficiency of the hybrid parallel power supply for an example implementation is about 76%. The hybrid parallel power supply can also lower system power by allowing a smaller voltage guardband. This is particularly valuable in systems (such as a CMOS SoC) where the power is proportional to the voltage squared. An SoC with the voltage regulator  510  and the load device  560  may also have a reduced number of pins due, for example, to direct connection of the first power supply  505  and the voltage regulator  510  to the load device  560  and reduced use of decoupling capacitors on the power rail  520 . 
     The parallel combination of the LDO and SMPS combines the characteristics of the individual circuits to efficiently supply power while reducing voltage droop caused by rapid load current changes. The SMPS can be viewed as generally involved in supplying the steady-state current needs of the load device. In this way, the relatively large current demand of the load device is provided with the high efficiency of the SMPS. The LDO can be viewed as generally involved in supplying current to the load device in response in changes in the load current that could otherwise cause large voltage droops. That is, the LDO rapidly reacts to drops in the supply voltage and supplies current to the load device until the SMPS can react. The high bandwidth of the LDO enables the hybrid parallel power supply to provide sufficient current in a timely manner such that the droop characteristics are greatly reduced. Additionally, a parallel combination of the LDO and SMPS may allow use of a simplified SMPS, for example, an SMPS with fewer phases. 
       FIG. 6  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment. The hybrid parallel power supply of  FIG. 6  generally corresponds to the hybrid parallel power supply in the system of  FIG. 5 . According, the description of the system of  FIG. 6  may omit details common to the system of  FIG. 5 . The system of  FIG. 6  includes the first power supply  505  and the voltage regulator  510  (receiving power from the second power supply  530 ) supplying power to the load device  560  via power rail  520 . The load device  560  (which may be an SoC including a processor and other circuits) is modeled with an equivalent load impedance  675   a  and a switched equivalent load impedance  675   b.    
     The voltage regulator  510  includes an operational amplifier  610 , a current mirror  615 , a reference converter (“DAC”)  620 , and a bandgap source  625 . The reference converter  620  and the bandgap source  625  combine to produce a reference voltage that sets the second target voltage level at which the voltage regulator  510  supplies power to the power rail  520 . The bandgap source  625  produces a reference output voltage that is nearly constant (e.g., less than 1% variation with process, supply voltage, and temperature). The bandgap source  625 , in an embodiment, produces the reference output voltage at a sub-bandgap level (e.g., 0.64 V). The reference converter  620  scales the reference output voltage from the bandgap source  625  to produce the reference voltage. For example, the reference converter  620  may scale a 0.64 V reference output voltage from the bandgap source  625  by 11/8 to produce a 0.88 V reference voltage. The reference converter  620  may be a digital-to-analog converter (DAC). The reference converter  620  may receive a digital input to configure the reference voltage. The digital input may be used to adjust the second target voltage level. 
     The operational amplifier  610  and the current mirror  615  operate as an LDO. The current mirror  615  is coupled to the output of the operational amplifier  610  and can provide current from the second power supply  530  to the power rail  520 . The current mirror  615  includes a sense device  630  and a drive device  635 . In the embodiment of  FIG. 6 , the sense device  630  and the drive device  635  are p-channel transistors. The source of the sense device  630  and the source of the drive device  635  connect to the output of the second power supply  530 . The gate and the drain of the sense device  630  and the gate of the drive device  635  connect to the output of the operational amplifier. The drain of the drive device  635  connects to the power rail  520 . The sense device  630  sources a current to the operational amplifier  610  and produces a corresponding gate voltage for the drive device  635 . The current mirror  615  allows for scaling of currents between the drive device  635  and the sense device  630 . The drive device  635  sources current to the power rail  520  that is scaled (e.g., by scaling of device sizes between the drive device  635  and the sense device  630 ) from the current sunk by the operational amplifier  610 . For example, the size (e.g., transistor width) of the drive device  635  may be 200-800 times the size of the sense device  630 . The drive device  635  may be, for example, fabricated from multiple devices arranged in parallel to produce the scaled drive strength. 
     The operational amplifier  610  has its non-inverting input (“+”) connected to the reference voltage from the reference converter  620  and its inverting input (“−”) connected to the power rail  520 . The operational amplifier  610  may be a Class-B (push-pull) operational transconductance amplifier (OTA). The output of the operational transconductance amplifier sources or sinks current based on the voltage difference between the inverting and non-inverting inputs. The feedback loop from the output of the operational amplifier  610  through the current mirror  615  to the power rail  520  back to the inverting input of the operational amplifier  610  causes the voltage regulator  510  to regulate its output to the level (second target voltage level) of the reference voltage. 
     The voltage regulator  510  may be considered to operate as a comparator that turns on to source current to the power rail  520  when the voltage on the non-inverting input is greater than the voltage on the inverting input and turns off when the voltage on the non-inverting input is less than the voltage on the inverting input. Viewed thusly, the operational amplifier  610  compares the level of the reference voltage to the level of the power rail  520  with the level of the reference voltage serving as triggering level to turn the current mirror  615  on. An operational transconductance amplifier can have high bandwidth so that the voltage regulator  510  can provide current to the power rail  520  with a high-frequency-response characteristic. Additionally, a Class-B OTA may be fabricated using standard logic transistors and without special devices or device fabrication techniques. The voltage regulator  510  may also have low quiescent current and thus contribute to overall power reduction for the system. The LDO may also be implemented within a small amount of die area 
     The system of  FIG. 6  includes the on-die capacitor  550  and a second capacitor  650  located in a package  605  housing the SoC and connected to the input of the voltage regulator  510 . The values of the second capacitor  650  and the on-die capacitor  550  may be selected based on, for example, cost, performance, and size. In an example embodiment, the capacitance of the second capacitor  650  may be about 200 times greater than the capacitance of the on-die capacitor  550 . For example, the capacitance of the second capacitor  650  may be 200 nF and the capacitance of the on-die capacitor  550  may be 1 nF. In some embodiments, a further capacitor may be located on the circuit board  515  and connected to the input of the voltage regulator  510 . 
     In some embodiments, a rail capacitor  680  located in the first die  525  is connected to the power rail  520 . The rail capacitor  680  may work in combination with the on-die capacitor  550  to provide current to the load device  560  during a droop event. Other combinations of capacitors on the circuit board  515 , the package  605 , the first die  525 , or other locations may also be used. 
       FIG. 6  also shows interconnection-parasitic elements  665   a,b  that represent the reactive elements encountered in making various electrical connections between the first power supply  505  and the power rail  520  and the second power supply  530  and the voltage regulator  510 . The interconnection-parasitic elements  665   a,b  are shown in the domain of the circuit board  515  between the first die  525  and the second die  535 . The interconnection-parasitic elements  665   a,b  may be combinations of resistors, capacitors, and inductors that represent an equivalent impedance encountered by electrical connections spanning between the first die  525  and the second die  535 . 
       FIG. 7  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment. The hybrid parallel power supply of  FIG. 7  is similar to the hybrid parallel power supply in the system of  FIG. 6 . Accordingly, the description of the system of  FIG. 7  omits details common to the system of  FIG. 6 . 
     The hybrid parallel power supply of  FIG. 7  includes a PMIC control module  705  to supply a control signal to the first power supply  505 . The PMIC control module  705  may be implemented in various ways. When the first power supply  505  is arranged to receive a digital control signal, the PMIC control module  705  supplies the control signal in digital form. For example, the PMIC control module  705  may signal the first target voltage level to the first power supply  505  using a serial protocol. The PMIC control module  705  may signal the first target voltage level open loop. Alternatively, the PMIC control module  705  may signal the first target voltage level closed loop by, for example, comparing the relative levels of the power rail  520  and the reference output voltage from the bandgap source  625 . 
     Alternatively, when the first power supply  505  is arranged to receive an analog control signal, the PMIC control module  705  supplies the control signal in analog form. The PMIC control module  705  may signal the first target voltage level to the first power supply  505  open loop by supplying the control signal at the first target voltage level or a scaled version of the first target voltage level. Alternatively, the PMIC control module  705  may signal the first target voltage level closed loop by, for example, comparing the relative levels of the power rail  520  and reference output voltage from the bandgap source  625 . The first power supply  505  can utilize the closed-loop control signal to produce a corresponding change in the voltage generated by the first power supply  505  on the power rail  520 . The PMIC control module  705 , in an example closed-loop analog embodiment, includes a second operational amplifier having an output that provides the control signal to the first power supply  505 . The non-inverting input (“+”) of the second operational amplifier connects to a supply reference voltage. The inverting input (“−”) of the second operational amplifier connects to the power rail  520 . The supply reference voltage sets the first target voltage level at which the first power supply  505  supplies power to the power rail  520 . The supply reference voltage is produced by a second reference converter that scales the reference output voltage from the bandgap source  625  to produce the supply reference voltage. For example, the second reference converter may scale a 0.64 V reference output voltage from the bandgap source  625  by 45/32 to produce a 0.9 V supply reference voltage. The second reference converter may be a direct current (DC) converter, also known as a DC-to-DC converter. The second reference converter may receive a digital input to adjust the level of the supply reference voltage. 
     The second operational amplifier may be considered to operate as a comparator in a fashion similar to that described above in relation to the operational amplifier  610 . The second operational amplifier compares the voltage on the power rail  520  (applied to the inverting input) to the voltage level of the supply reference voltage (applied to the non-inverting input). The result of the comparison is signaled on the feedback signal to the first power supply  505 . A feedback loop from the second operational amplifier to the first power supply  505  back to the second operational amplifier via the power rail  520  works to drive the power rail  520  to the supply reference voltage (first target voltage level). 
     The voltage regulator  510 , in the embodiment of  FIG. 7 , includes a stabilization capacitor  750  in the current mirror  615 . The stabilization capacitor  750  is coupled between drain and gate of the driver device  634 . The stabilization capacitor  750  may be configured to provide an impedance to stabilize the voltage regulator  510 . According to certain exemplary embodiments, the stabilization capacitor  750  may be about one-tenth the gate capacitance of the drive device  635 . Other compensation techniques may also be used. 
       FIG. 8  is a functional block diagram of an electronic system with a hybrid parallel power supply according to a presently disclosed embodiment. The hybrid parallel power supply of  FIG. 8  is similar to the hybrid parallel power supply in the system of  FIG. 6 . Accordingly, the description of the system of  FIG. 8  omits details common to the system of  FIG. 6 . 
     The voltage regulator  510 , in the hybrid parallel power supply of  FIG. 8 , includes a reference level module  825  that produces a reference voltage that sets the second target voltage level at which the voltage regulator  510  supplies power to the power rail  520 . The reference level module  825  supplies the reference voltage by scaling and low-pass filtering the power rail  520 . Setting the second target voltage level at a scaled level relative to the average level on power rail  520  allows the first power supply  505  supply most of the current to the load device  560 . The voltage regulator  510  then supplies current to the load device  560  when the power rail  520  drops below the reference voltage. The reference level module  825  may, for example, use a scale factor (of the second target voltage level relative to the level of the power rail  520 ) of 15/16. The amount of filtering may be chosen, for example, based on the bandwidth of the first power supply  505 . 
     The reference level module  825 , in the embodiment illustrated in  FIG. 8 , includes a first resistor  826  coupled in series with a second resistor  827  between the power rail  520  and the ground reference. The midpoint of the first resistor  826  and the second resistor  827  connects to a filter capacitor  828 . The relative values of the first resistor  826  and the second resistor  827  control the amount of scaling of the supply level and the capacitance of the filter capacitor  828  in combination with the values of the first resistor  826  and the second resistor  827  control the amount of filtering. One or both of the first resistor  826  and the second resistor  827  may be variable so that the amount of scaling can be controlled. Additionally, a resistor-DAC may be used in the reference level module  825 . 
       FIG. 9  is a time-domain graph of a droop characteristic in a system using a hybrid parallel power supply according to a presently disclosed embodiment. The graph illustrates operation of the hybrid parallel power supplies of  FIGS. 5-8 . Similar to the graph of  FIG. 2 , the graph of  FIG. 9  illustrates an example of a rapid change in current at time  950 . The graph of  FIG. 9  plots load current  905  for the load device  560  and supply voltage  910  for the power rail  520 . Prior to time  950 , the load current  905  is 1.25 A. At time  950 , the load current  905  rapidly increases to 3.55 A. 
     In addition to the step in current demand of the load device at time  950 , small variations in the load current  905  occur, for example, as different calculations are performed in a processor in the load device  560 . These small variations in the load current  905  cause ripples (small variations, e.g., 4 mV) in the supply voltage  910 . The ripples in the supply voltage may be at frequencies that are higher than the bandwidth of the first power supply  505 . The first power supply  505  will then supply current the power rail  520  based on a low-pass filtered average of the supply voltage. The ripples in the supply voltage may, however, be at frequencies that are within the bandwidth of the voltage regulator  510 . The voltage regulator  510  will then supply current the power rail  520  that reduces the magnitude of the ripples. 
     Prior to time  950 , the supply voltage  910  is at a nominal voltage level, for example, 0.9 V. At time  950 , the rapid increase in load current causes a droop characteristic  925  in the supply voltage  910 . The high frequency response of the voltage regulator  510  allows it to quickly increase current supplied to the load device  560  to reduce the magnitude of the droop characteristic  925 . An example system has a resultant droop characteristic of &lt;7% for a 2.3 A/5 ns step change in load current. The apparatus and systems described above relate to a droop characteristic defined in terms of a spike-like lowering of the supply voltage at a load device on a die. A similar effect, but with a positive-going spike, may be realized in certain circuit situations where the current demand of a load device rapidly decreases. Techniques and circuits similar to those described above may be applied, although in a complementary sense, to overcome the fluctuations in the power supply level experienced on a power rail during switching related to load devices. 
       FIG. 10  is a flowchart of a process for supplying power to an electronic device according to a presently disclose embodiment. The process will be described with reference to the system of  FIG. 5 ; however, various embodiments of the process may be applied to any suitable apparatus. 
     In block  1005 , the process supplies current from a power supply to a load device via a power rail at a first target voltage level. In block  1005 , an efficient power supply, such as a switching mode power supply, is used. For example, the first power supply  505  can regulate the power rail  520  to a first target voltage level to supply current to the load device  560 . 
     In block  1015 , the process supplies current from a voltage regulator to the load device via the power rail at a second target voltage level. In block  1015 , a voltage regulator, such as a low dropout voltage regulator, with high-frequency-response characteristic is used. For example, the voltage regulator  510  can regulate the power rail  520  to a second supply voltage level to supply current to the load device  560 . The first target voltage level and the second target voltage level may be different and may be configurable. The process may generate the first target voltage level and the second target voltage level by generating a reference output voltage based on a bandgap source and then generating the second target voltage level based on a first digital input and the reference output voltage and generating the first target voltage level based on a second digital input and the reference output voltage. 
     The process of  FIG. 10  may be modified, for example, by adding or altering blocks. Additionally, blocks may be performed concurrently. 
     Although features the invention are described above for particular embodiments, many variations are possible. For example, hybrid parallel power supplies may be formed using other fabrication processes including processes different types of transistors. Additionally, hybrid parallel power supplies may use different types of voltage regulators and different types of power supplies. Further, hybrid parallel power supplies may have different numbers of power supplies and voltage regulators. In another variation, the voltage regulator  510  can be shut off and removed from providing voltage regulation. In yet another variation, a low-power retention voltage regulator is included on the SoC for use during standby modes. Additionally, features of the various embodiments may be combined in combinations that differ from those described above. 
     Those of skill in the art will appreciate that the various illustrative blocks and modules described in connection with the embodiments disclosed herein can be implemented in various forms. Some blocks and modules have been described above generally in terms of their functionality. How such functionality is implemented depends upon the design constraints imposed on an overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the invention. In addition, the grouping of functions within a module, block, or step is for ease of description. Specific functions or steps can be moved from one module or block or distributed across to modules or blocks without departing from the invention. 
     The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein can be applied to other embodiments without departing from the spirit or scope of the invention. Thus, it is to be understood that the description and drawings presented herein represent a presently preferred embodiment of the invention and are therefore representative of the subject matter which is broadly contemplated by the present invention. It is further understood that the scope of the present invention fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present invention is accordingly limited by nothing other than the appended claims.