Abstract:
The present invention relates to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency. The plurality of array units in the memory array include a plurality of normal memory cells and a plurality of redundancy memory cells. The normal data stored in the plurality of normal memory cells and the redundancy data stored in the plurality of redundancy memory cells are outputted through a local normal input/output line and a local redundancy input/output line, respectively. The column redundancy unit outputs a redundancy enable signal according to a column address, a row address, and a state of a fuse. The normal data stored in the plurality of normal memory cells or the redundancy data stored in the plurality of redundancy memory cells is selected according to a logical state of the redundancy enable signal, and outputted to a main amplifier via a global input/output line.

Description:
This application claims the benefit of Korean patent application No. 30393/1999, filed Jul. 26, 1999, which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a column redundancy circuit for semiconductor memory, and in particular to a column redundancy circuit for a semiconductor memory which can facilitate a high integration semiconductor circuit whose memory array is divided into a plurality of array units to be properly operated at a high frequency, by selecting and outputting one of a normal data or a redundancy data which are outputted from the memory array, according to a row address and a column address. 
     2. Discussion of the Background Art 
     FIG. 1 is a block diagram illustrating the conventional column redundancy circuit using the column address. 
     A clock buffer  1  buffers an external clock signal EX_CLK and outputs it to a pulse width control unit  5 . An address buffer  2  buffers an external address EX_ADD and outputs it to a column redundancy unit  4  and a column predecoder  6 . In a burst mode, an address counter  3  counts the buffered external address EX_ADD, and outputs an internal address IN_ADD to the column redundancy unit  4  and the column predecoder  6 . The column redundancy unit  4  determines whether to repair each memory array unit according to the external address EX_ADD and the internal address IN_ADD to be inputted to the column redundancy unit  4 , and outputs corresponding redundancy information RE_INF. The pulse width control unit  5  serves to output the internal clock signal EX_CLK to the column predecoder  6  for determining a pulse width of a column selecting signal according to the buffered external clock signal EX_CLK, and to output a redundancy clock signal CLK_RE_INF having the redundancy information RE_INF to a column decoder  7 . 
     The column predecoder  6  enables a normal address path in a non-redundancy mode where a repair operation is not performed. To the contrary, the column predecoder  6  disables the normal address path in a redundancy mode where the repair operation is carried out, predecodes a column address Y_ADD from the address buffer  2 , and outputs it to the column decoder  7 . A pulse width of the predecoded column address Y_ADD is determined by the external clock signal EX_CLK. 
     The column decoder  7  determines whether to repair according to the redundancy clock signal CLK_RE_INF, and outputs a normal column selecting signal NYS or a redundancy column selecting signal RYS to a memory array  8 . That is, the column decoder  7  outputs the normal column selecting signal NYS in the non-redundancy mode, and outputs the redundancy column selecting signal RYS in the redundancy mode. Here, the normal column selecting signal NYS and the redundancy column selecting signal RYS are signals for selecting a sense amplifier (not shown) in the memory array  8 . 
     The memory array  8  consists of a plurality of normal memory cells and a plurality of redundancy memory cells. When the column decoder  7  outputs the normal column selecting signal NYS, the data stored in the normal memory cells of the memory array are read. In case the column decoder  7  outputs the redundancy column selecting signal RYS, the data stored in the redundancy memory cells of the memory array  8  are read. The data which have been read are-inputted to a main amplifier  9  via an input/output line LIOT/B, amplified and outputted to an output buffer (not shown). 
     FIGS. 2A and 2B are timing diagrams for the circuit in FIG.  1 . FIG. 2A is a timing diagram in the non-redundancy mode, and FIG. 2B is a timing diagram in the redundancy mode. As shown in the Figures, if a column address strobe signal CAS is inputted in a state where the external clock signal EX_CLK is inputted, the external address EX_ADD and the internal address IN_ADD are transited. When a first predetermined time t1 lapses after the internal address IN_ADD is transited, the redundancy information RE_INF is at a high level, and the redundancy clock signal EX_CLK is also at a high level. As shown in FIG. 2A, the redundancy clock signal EX_CLK being at a high level implies that the column redundancy circuit is operated in the non-redundancy mode. In FIG. 2B, the redundancy clock signal EX_CLK being at a high level means that the column redundancy circuit is operated in the redundancy mode. 
     When a second predetermined time t2 lapses after the first predetermined time t1, the normal column selecting signal NYS is enabled in the normal mode, as shown in FIG. 2A, and the redundancy column selecting signal RYS is enabled in the redundancy mode, as depicted in FIG.  2 B. 
     The second predetermined time t2 is a time taken to determine whether the column predecoder  6  and the column decoder  7  operate the column redundancy circuit in the normal mode or the redundancy mode according to whether to repair, and is identical in the normal mode and the redundancy mode. 
     The second predetermined time t2 is clearly longer when the normal column selecting signal NYS is outputted without determining whether to repair. As the second predetermined time t2 becomes longer, a total processing speed of the column redundancy circuit is reduced. 
     In order to overcome such a disadvantage, FIG. 3 illustrates a block diagram of another conventional redundancy circuit. As shown in Figures, the clock buffer  1 , the address buffer  2  and the address counter  3  are identical in constitution and operation to those in FIG. 1. A pulse width control unit  31  outputs an internal clock signal IN_CLK to a column predecoder  32  for determining a pulse width of a column selecting signal according to a buffered external clock signal EX_CLK. A column address Y_ADD is inputted to a column decoder  33  via the address buffer  2  and the column predecoder  32 . The column decoder  33  outputs a column selecting signal YS to the memory array  34 . Here, the column address Y_ADD and the column selecting signal YS are not related to a repair operation. The memory array  34  includes normal memory cells and redundancy memory cells. Each array is not divided into a plurality of array units, differently from the memory array  8  as illustrated in FIG.  1 . The data stored in the normal array cells are inputted to a main amplifier  35  through a normal input/output line NLIOT/B, and the data stored in the redundancy memory cells are inputted to the main amplifier  35  via a redundancy input/output line RLIOT/B. 
     The column redundancy unit  36  determines whether to repair the normal input/output line NLIOT/B and the redundancy input/output line RLIOT/B, and outputs redundancy information RE_INF to the main amplifier  35 . According to the redundancy information RE_INF, the main amplifier  35  amplifies and outputs one of the data inputted through the normal input/output line NLIOT/B or the redundancy input/output line RLIOT/B. 
     As described above, in the circuit as shown in FIG. 3, when the column selecting signal YS (identical to the normal column selecting signal NYS as shown in FIG. 1) is outputted to the memory array  34 , whether to repair or not is determined, differently from the circuit as shown in FIG.  1 . Accordingly, an extra amount of time to determine whether to repair is not necessary. As a result, the circuit in FIG. 3 is faster in operation than the circuit in FIG.  1 . However, the memory array is not divided, and thus redundancy efficiency is reduced. In addition, as the memory array is divided into a plurality of array units, and thus the number of the array units is increased, a load of the redundancy input/output line RLIOT/B is also increased. Accordingly, in order to employ such a circuit, the number of the array units must be limited. Thus, it is not suitable for a high integration circuit where the memory array is divided into many array units. 
     SUMMARY OF THE INVENTION 
     Accordingly, a primary object of the present invention to provide a column redundancy circuit for a semiconductor memory which can improve an operational speed of a high integration semiconductor circuit whose memory array is divided into a plurality of memory array units. 
     It is another object of the present invention to provide a column redundancy circuit for a semiconductor memory wherein a memory array uses an identical global input/output line both in a normal mode and a redundancy mode, thereby reducing a layout of the memory array. 
     In order to achieve the above-described objects of the present invention, there is provided a column redundancy circuit for a semiconductor memory comprising a column decoder for receiving a predecoded column address and an internal clock signal and for outputting a normal column selecting signal and a redundancy column selecting signal, a column redundancy unit for outputting a redundancy enable signal in accordance with a column address, a row address, and a state of fuse, and a memory array including a plurality of array units having a plurality of normal memory cells and a plurality of redundancy memory cells, and a switch unit selecting and outputting one of a normal data stored in the normal memory cell according to the normal column selecting signal or a redundancy data stored in the redundancy memory cell according to the redundancy column selecting signal, wherein the data selected by the switch unit is outputted to a main amplifier via a global input/output line in accordance with the redundancy enable signal. 
     In order to achieve the above-described objects of the present invention, there is provided a column redundancy circuit for a semiconductor memory including a column redundancy unit outputting a redundancy enable signal in accordance with a column address, a row address, and a state of fuse, a memory array consisting of a plurality of array units, respectively having a plurality of normal memory cells and a plurality of redundancy memory cells, and a switch unit selecting and outputting one of a normal data stored in the normal memory cell or a redundancy data stored in the redundancy memory cell in accordance with the redundancy enable signal, wherein the data selected and outputted by the switch unit is outputted to a main amplifier via a global input/output line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein: 
     FIG. 1 is a block diagram illustrating a conventional column redundancy circuit employing a column address of a semiconductor memory; 
     FIGS. 2A and 2B are timing diagrams for the circuit in FIG. 1 in a non-redundancy mode and in a redundancy mode, respectively; 
     FIG. 3 is a block diagram illustrating a conventional redundancy circuit of the semiconductor memory; 
     FIG. 4 is a block diagram illustrating a column redundancy circuit employing a column address of a semiconductor memory in accordance with a preferred embodiment of the present invention; 
     FIG. 5 is a detailed structure view illustrating a column redundancy unit in the configuration of FIG. 4; 
     FIG. 6 is a detailed circuit view illustrating a memory array in the configuration of FIG. 4; and 
     FIGS. 7A and 7B are timing diagrams for the circuit in FIG. 4 in a non-redundancy mode and in a redundancy mode, respectively. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     A column redundancy circuit for a semiconductor memory in accordance with the present invention will now be described with reference to the accompanying drawings. 
     FIG. 4 is a block diagram illustrating the column redundancy circuit using a column address of the semiconductor memory in accordance with a preferred embodiment of the present invention. A clock buffer  1 , an address buffer  2 , and an address counter  3  as shown in FIG. 4 are identical in constitution and operation to those as shown in FIG. 1, and thus explanation thereof is omitted. 
     A pulse width control unit  41  outputs an internal clock signal IN_CLK to a column predecoder  42  and a column decoder  43  according to an external clock signal EX_CLK buffered in the clock buffer  1  for controlling a pulse width of a column selecting signal. A column decoder  43  receives a predecoded column address and the internal clock signal IN_CLK, and outputs a normal column selecting signal NYS and a redundancy column selecting signal RYS to a memory array  45 , regardless of whether to repair. 
     A column redundancy unit  44  receives an external address EX_ADD from the address buffer  2  and an internal address IN_ADD from the address counter  3 , determines whether to repair, and outputs a redundancy enable signal EN_RE to the memory array  45 . In more detail, referring to FIG. 5, the column redundancy unit  44  consists of a plurality of enable units  440 - 447  outputting a column address true signal Y_ADDnT or a column address bar signal Y_ADDnB in accordance with row addresses X_ADD 0  and X_ADD 1  and state of fuses F 0  and F 1 ; and a combination unit  448  combining the signals outputted from the plurality of enable units  440 - 447  and outputting a redundancy enable signal EN_RE to the memory array  45 . 
     The number of the plurality of enable units  440 - 447  is identical to that of the column addresses. A first enable unit  440  includes: a NAND gate N 51  receiving a read/write enable signal R/W at its one-side input terminal; a plurality of fuses F 0  and F 1 ; a plurality of switching transistors N 1  and N 2  having their gates connected to receive the row addresses X_ADD 0  and X_ADD 1  and being connected to the other input terminal of the NAND gate N 51  through the fuses F 0  and F 1 ; and two transmission gates T 1  and T 2 . In FIG. 5, only two fuses F 0  and F 1  and two switching transistors N 1  and N 2  are illustrated for convenience. However, the entire number thereof is identical to the number of the row addresses. 
     The two transmission gates T 1  and T 2  are turned on/off according to a level of an output signal from the NAND gate N 51  and a level of the other side input terminal of the NAND gate N 51 . A first column address true signal Y_ADD 0 T is passed through the first transmission gate T 1  and a first column address bar signal Y_ADD 0 B is passed through the second transmission gate T 2 . The first transmission gate T 1  and the second transmission gate T 2  have a complementary relationship. That is, when the first column address true signal Y_ADD 0 T is passed, the first column address bar signal Y_ADD 0 B is interrupted. Also, when the first column address bar signal Y_ADD 0 B is passed, the first column address true signal Y_ADD 0 T is interrupted. The other enable units  441 - 447  are identical in constitution to the first enable unit  440 . However, each enable unit  441 - 447  outputs different address signals. For instance, the second enable unit  441  selectively outputs a second column address true signal Y_ADD 1 T or a second column address bar signal Y_ADD 1 B. 
     When the column address true signals Y_ADD 0 T through Y_ADD 7 T or the column address bar signals Y_ADD 0 B through Y_ADD 7 B outputted from the plurality of enable units  440 - 447  are all at a high level, the combination unit  448  outputs the redundancy enable signal EN_RE having a high level to the memory array  45 . The combination unit  448  includes: NAND gates N 52 , N 53 , and N 54  NANDing a predetermined number of output signals among the output signals from the enable units  440 - 447 , respectively; a NOR gate NOR 5  NORing output signals from the NAND, gates N 52 , N 53 , and N 54 ; and two inverters I 51  and I 52  buffering a level of the output signal from the NOR gate NOR 5  and outputting the redundancy enable signal EN_RE. 
     The operation of the first enable unit  440  will now be explained. It is presumed that the read/write enable signal R/W is enabled, that is the input terminal at the one side of the first NAND gate N 51  is at a high level. 
     The plurality of row addresses X_ADD 0  and X_ADD 1  which are inputted from the address buffer  2  are sequentially coded. After a first row address X_ADD 0  is coded, a second row address X_ADD 1  is coded. When the first row address X_ADD 0  is coded, the first switching transistor N 1  is turned on. In this state, if the first fuse F 0  is disconnected, the terminal at the other side of the first NAND gate N 51  is at a high level. To the contrary, if the first fuse F 0  is connected, the terminal at the other side of the first NAND gate N 51  is at a low level. 
     In the case, when the first fuse F 0  is disconnected, namely when it is presumed that the terminal at the other side of the NAND gate N 51  is at a high level, the NAND gate N 51  outputs a low-level signal. As a result, the first transmission gate T 1  is turned on and thus the column address true signal Y_ADD 0 T is passed through. To the contrary, when the first fuse F 0  is not disconnected, namely when the terminal at the other side of the NAND gate NAND 51  is at a low level, the first transmission gate T 1  is turned off and the second transmission gate T 2  is turned on. Thus the column address bar signal Y_ADD 0 B is passed through. 
     As described above, the first enable unit  440  outputs the first column address true signal Y_ADD 0 T or the first column address bar signal Y_ADD 0 B according to whether the fuse is connected or disconnected. In addition, the second enable unit  441  outputs the second column address true signal Y_ADD 1 T or the second column address bar signal Y_ADD 1 B according to whether a fuse (not shown) is connected or disconnected. 
     Each of the eight enable units  440 - 447  selectively outputs one of first to eighth column address true signals, Y_ADD 0 T through Y_ADD 7 T, or one of first to eighth column address bar signals, Y_ADD 0 B through Y_ADD 7 B, respectively, according to the row address signals X_ADD 0  and X_ADD 1 . The signals outputted from the first to third enable units  440 - 442  are NANDed in the second NAND gate N 52 , the signals outputted from the fourth to sixth enable units  443 - 445  are NANDed in the third NAND gate N 53 , and the signals outputted from the seventh and eight enable units  446  and  447  are NANDed in the fourth NAND gate N 54 . According to the present invention, the address signals respectively outputted from the eight enable units  440 - 447  are NANDed in the three NAND gates N 52 -N 54 . However, the number of the NAND gates may be changed, if necessary. 
     The signals outputted from the second to fourth NAND gates N 52 -N 54  are combined in the NOR gate NOR 5 , and the levels thereof are converted in the two inverters I 51  and I 52 . Accordingly, the signals are outputted to the memory array  45  as the redundancy enable signal EN_RE. As described above, the combination unit  448  outputs the redundancy enable signal EN_RE at a high level when the eight address signals are all at a high level and outputs the redundancy enable signal EN_RE at a low level when any of the eight address signals is at a low level. 
     The memory array  45  outputs a normal data or a redundancy data to a main amplifier  46  according to the redundancy enable signal EN_RE. FIG. 6 is a detailed structure view illustrating the memory array in accordance with the preferred embodiment of the present invention. As shown in Figures, the memory array  45  includes: a plurality of array units  451 - 454  consisting of a plurality of normal memory cells and a plurality of redundancy memory cells; a local normal input/output line LIO_N connected to each array unit  451 - 454 , and transmitting the normal data stored in the normal memory cell; a local redundancy input/output line LIO_R connected to each array unit  451 - 454 , and transmitting the redundancy data stored in the redundancy memory cell; and a global input/output line GIO commonly connected to the local normal input/output line LIO_N and the local redundancy input/output line LIO_R. 
     In addition, the memory array  45  further includes a switch unit which receives the redundancy enable signal EN_RE from the combination unit  448  and transmits/interrupts the redundancy data or the normal data to/from the global input/output line GIO. The switch unit includes: a buffer unit  456  buffering the redundancy enable signal EN_RE and outputting a redundancy switching signal ENR and a normal switching signal ENN; a plurality of redundancy&#39;switches SWR 1 -SWR 4  switched according to the redundancy switching signal ENR and connecting the local redundancy input/output line LIO_R to the global input/output line GIO; and a plurality of normal switches SWN 1 -SWN 4  switched according to the normal switching signal ENN, and connecting the local normal input/output line LIO_N to the global input/output line GIO. 
     The buffer unit  456  buffers the redundancy enable signal EN_RE, thereby outputting the redundancy switching signal ENR and the normal switching signal ENN having an opposite logic state to the redundancy switching signal ENR. For this, the buffer unit  456  includes: a NAND gate N 6  NANDing the read/write enable signal R/W and the redundancy enable signal EN_RE and outputting the redundancy switching signal ENR; and an inverter I 6  inverting the redundancy switching signal ENR and outputting the normal switching signal ENN. 
     When the read/write enable signal R/W is at a high level and the high-level redundancy enable signal EN_RE is inputted, the NAND gate N 6  outputs an output signal at a low level. The output signal is supplied to the plurality of redundancy switches SWR 1 -SWR 4  as the redundancy switching signal ENR. The inverter  16  inverting the output from the NAND gate N 6  outputs the normal switching signal ENN at a high level, and the normal switching signal ENN is applied to the plurality of normal switches. As the normal switching signal ENN becomes at a high level, the normal switches SWN 1 -SWN 4  are electrically connected. Accordingly, the normal data stored in the normal memory cell are applied to the global line GIO via each local normal input/output line LIO_N, and transmitted to the sense amplifier  46 . Here, the redundancy switches SWR 1 -SWR 4  are not enabled because of the low-level redundancy switching signal ENR. To the contrary, when the redundancy enable signal EN_RE is at a low level, the redundancy switching signal ENR becomes a high level, and thus the plurality of redundancy switches SWR 1 -SWR 4  are enabled. Accordingly, the normal switching signal ENN becomes a low level, and thus the plurality of normal switches SWN 1 -SWN 4  are disabled. As a result, the redundancy data stored in the redundancy memory cell are applied to the global line GIO through each local redundancy input/output line LIO_R, and transmitted to the sense amplifier  46 . 
     FIGS. 7A and 7B are timing diagrams for the circuit in FIG.  4 . FIG. 7A is a timing diagram in a non-redundancy mode and FIG. 7B is a timing diagram in a redundancy mode. Referring to FIGS. 7A and 7B, the points that the external address EX_ADD and the internal address IN_ADD are transited are identical as shown in FIGS. 2A and 2B. However, referring to FIGS. 2A and 2B, the redundancy clock signal EX_CLK becomes a high level when a first predetermined time t1 lapses after the internal address IN_ADD is transited. According to the preferred embodiment of the present invention, as depicted in FIGS. 7A and 7B, the redundancy clock signal EX_CLK becomes a high level as soon as the internal address IN_ADD is transited. In the conventional art, the normal column selecting signal NYS and the redundancy column selecting signal RYS are outputted when the first predetermined time t1 and the second predetermined time t2 lapse after the internal address IN_ADD is transited. However, in accordance with the preferred embodiment of the present invention, the normal column selecting signal NYS and the redundancy column selecting signal RYS are outputted when the second predetermined time t2 lapses after the internal address IN_ADD is transited. Accordingly, the present invention reduces the operating time of the column redundancy circuit of the conventional art by the amount of the time from an internal address transition point to an output point of the redundancy clock signal having the redundancy information (the first predetermined time t1). 
     As discussed earlier, the column redundancy circuit in accordance with the present invention can improve speed by switching the data outputted from the memory array according to the redundancy information. In addition, in the normal mode, the normal data outputted from the memory array is amplified in the main amplifier, and in the redundancy mode, the redundancy data outputted from the memory array is amplified in the main amplifier. As a result, the present invention can be applied even when a load of the input/output line is high. In addition, since the redundancy data or the normal data is selectively outputted to the sense amplifier via the global input/output line, only one global input/output line is used for outputting the redundancy data and the normal data, thereby reducing the layout of the memory array. The aforementioned effects and benefits are increased in accordance with high integration of a semiconductor memory circuit. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the column redundancy circuit for semiconductor memory of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.