Abstract:
A semiconductor memory device comprises planes each configured to comprise flag cells storing data about program methods of memory cells of the plane, page buffer units configured to sense the data of the flag cells, a flag cell data detection circuit configured to make a determination of program methods of the planes on the basis of a result, obtained by comparing the sensed data of the flag cells of the planes, and the sensed data of the flag cells, and a microcontroller configured to control the page buffer units, wherein the page buffer units read least significant bit (LSB) data of the planes or both the least significant bit (LSB) data and most significant bit (MSB) data on the basis of the determination of the flag cell data detection circuit.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    Priority to Korean patent application number 10-2010-0075248 filed on Aug. 4, 2010, the entire disclosure of which is incorporated by reference herein, is claimed. 
       BACKGROUND 
       [0002]    Exemplary embodiments relate to a semiconductor memory device and a method of reading data from the same and, more particularly, to a semiconductor memory device including a plurality of planes programmed by using different program methods and a method of reading the semiconductor memory device. 
         [0003]      FIG. 1  is a diagram showing the distributions of threshold voltages of planes programmed by using different program methods. 
         [0004]    Referring to  FIG. 1 , a plane programmed using only a single bit program method (that is, the least significant bit (LSB) program method) has two threshold voltage distributions; a threshold voltage distribution corresponding to data ‘1’ and a threshold voltage distribution corresponding to data ‘0’. Here, data ‘11’, indicating that the single bit program operation has been performed, is programmed into the flag cell of the plane. 
         [0005]    On the other hand, a plane programmed using a multi-bit program method (that is, the least significant bit (LSB) program and the most significant bit (MSB) program) has three or more threshold voltage distributions. For example, in case where data of 2 bits is programmed into one memory cell, a plane has threshold voltage distributions A, B, C, and D, as shown in the drawing. Here, data ‘10’, indicating that the multi-bit program operation has been performed, is programmed into the flag cell of the plane. 
         [0006]      FIG. 2A  is a flowchart illustrating a data read method for the least significant bit (LSB) page of a semiconductor memory device. 
         [0007]    The read method of the semiconductor memory device including first and second planes is described below with reference to  FIGS. 1 and 2A . 
         [0008]    Data of the memory cells and the flag cells of the first and second planes is sensed by performing a first read operation using a read voltage RD 2  at step L 11 . It is determined whether the least significant bit (LSB) data of the sensed flag cells is ‘1’ at step L 12 . Here, if the flag cells of the first and second planes have different data, the data of a flag cell of the second plane is first selected, and a subsequent operation is performed on the second plane. If, as a result of the determination, the least significant bit (LSB) data of the sensed flag cells is determined not to be ‘1’ (that is, determined to be ‘0’), the first and second planes are determined to have been programmed using a multi-bit program method. Next, data of the memory cells of the first and second planes, read by the first read operation, is outputted at step L 13 . 
         [0009]    Meanwhile, if, as a result of the determination at step L 12 , the least significant bit (LSB) data of the sensed flag cells is determined to be ‘1’, the first and second planes are determined to have been programmed using a single bit program method. Thus, the least significant bit (LSB) data of the memory cells of the first and second planes is sensed by performing a second read operation using a read voltage RD 1  at step L 14 . Next, data of the memory cells of the first and second planes, read by the second read operation, is outputted at step L 13 . 
         [0010]      FIG. 2B  is a flowchart illustrating a data read method for the most significant bit (MSB) page of a semiconductor memory device. 
         [0011]    The read method of the semiconductor memory device including first and second planes is described below with reference to  FIGS. 1 and 2B . 
         [0012]    Data of the memory cells and the flag cells of the first and second planes is sensed by performing a first read operation using a read voltage RD 2  at step M 11 . It is determined whether the least significant bit (LSB) data of the sensed flag cells is ‘1’ at step M 12 . Here, if the flag cells of the first and second planes have different data, the data of a flag cell of the second plane is first selected, and a subsequent operation is performed on the second plane. If, as a result of the determination, the least significant bit (LSB) data of the sensed flag cells is determined not to be ‘1’ (that is, ‘0’), the first and second planes are determined to have been programmed using a multi-bit program method. Accordingly, the data of the memory cells of the first and second planes is read by performing a second read operation using a read voltage RD 1  at step M 13 . Next, data of the memory cells of the first and second planes is read by performing a third read operation using a read voltage RD 3  at step M 14 . The data of the first to third read operations is combined, and multi-bit data of the memory cells of the first and second planes is outputted at step M 15 . 
         [0013]    Meanwhile, if, as a result of the determination at step M 12 , the least significant bit (LSB) data of the sensed flag cells is determined to be ‘1’, the first and second planes are determined to have been programmed using a single bit program method. Both the data of memory cells of the first and second planes, read by the first read operation, is changed to ‘1’ at step M 16 . Next, step M 15  is performed. 
         [0014]    In the above-described known read method of the semiconductor memory device, in case where  t he first and second planes have been programmed by using different program methods, a read algorithm is determined according to the data of a flag cell of the second plane. Here, the data of a plane programmed using a single bit program method is read by using a multi-bit read algorithm or the data of a plane programmed using a multi-bit program method is read by using a single bit read algorithm. 
       BRIEF SUMMARY 
       [0015]    Exemplary embodiments relate to a semiconductor memory device and a method of reading the same, wherein when a read operation is performed on the semiconductor memory device including first and second planes, the first and second planes are determined to have been programmed using the same method by comparing the data of flag cells of the first and second planes, and a read method corresponding to the program method of each of the first and second planes is used. 
         [0016]    A semiconductor memory device according to an aspect of the present disclosure comprises planes each configured to comprise flag cells storing data about program methods of memory cells of the plane, page buffer units configured to sense the data of the flag cells, a flag cell data detection circuit configured to make a determination of program methods of the planes on the basis of a result, obtained by comparing the sensed data of the flag cells of the planes, and the sensed data of the flag cells, and a microcontroller configured to control the page buffer units, wherein the page buffer units read least significant bit (LSB) data of the planes or both the least significant bit (LSB) data and most significant bit (MSB) data on the basis of the determination of the flag cell data detection circuit. 
         [0017]    A read method of a semiconductor memory device according to another aspect of the present disclosure comprises receiving a least significant bit (LSB) page address; sensing data of memory cells and data of flag cells that indicates program methods of first and second planes, by performing a first read operation and storing the sensed data in first and second page buffer units; making a determination of whether the first and second planes have been programmed using an identical program method by comparing the data of the flag cells of the first and second planes; in response to determining that the first and second planes have been programmed using the identical program method, reading least significant bit (LSB) data of the first and second planes by performing an identical read operation on the first and second planes; and in response to determining that the first and second planes have been programmed using different program methods, reading the least significant bit (LSB) data of the first and second planes by performing different read operations on the first and second planes. 
         [0018]    A read method of a semiconductor memory device according to another aspect of the present disclosure comprises receiving a most significant bit (MSB) page address; sensing data of memory cells and data of flag cells of first and second planes by performing a first read operation and storing the sensed data in first and second page buffer units; making a determination of whether the first and second planes have been programmed using an identical program method by comparing the data of the flag cells of the first and second planes; in response to determining that the first and second planes have been programmed using the identical program method, reading most significant bit (MSB) data of the first and second planes by performing an identical read operation on the first and second planes; and in response to determining that the first and second planes have been programmed using different program methods, reading the most significant bit (MSB) data of the first and second planes by performing different read operations on the first and second planes, respectively. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0019]      FIG. 1  is a diagram showing the distributions of threshold voltages of planes programmed by using different program methods; 
           [0020]      FIGS. 2A and 2B  are flowcharts illustrating a method of reading a semiconductor memory device; 
           [0021]      FIG. 3  is a block diagram of a semiconductor memory device according to an exemplary embodiment of this disclosure; 
           [0022]      FIG. 4  is a flowchart illustrating a read method for the least significant bit (LSB) pages of the semiconductor memory device according to an exemplary embodiment of this disclosure; and 
           [0023]      FIG. 5  is a flowchart illustrating a read method for the most significant bit (MSB) pages of the semiconductor memory device according to an exemplary embodiment of this disclosure. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0024]    Hereinafter, some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of the disclosure. 
         [0025]      FIG. 3  is a block diagram of a semiconductor memory device according to an exemplary embodiment of this disclosure. 
         [0026]    Referring to  FIG. 3 , the semiconductor memory device includes a memory unit  100 , a voltage supply circuit  200 , a flag cell data detection circuit  300 , and a microcontroller  400 . 
         [0027]    The memory unit  100  includes a plurality of planes and a plurality of page buffer units corresponding to respective ones of the plurality of planes. According to an example, the memory unit  100  includes a first plane  110  and a second plane  120 . Each of the first plane  110  and the second plane  120  includes a plurality of memory cells and flag cells. 
         [0028]    A first page buffer unit  130  and a second page buffer unit  140  correspond to the first plane  110  and the second plane  120 , respectively. The first page buffer unit  130  senses data of the memory cells and data of the flag cells, of the first plane  110 , and temporarily stores the sensed data in a plurality of latches. The second page buffer unit  140  senses data of the memory cells and data of the flag cells, of the second plane  120 , and temporarily stores the sensed data in a plurality of latches. 
         [0029]    The voltage supply circuit  200  includes a pump unit  210 , a switch unit  220 , and first and second row decoders  230 ,  240 . The pump unit  210  generates a read voltage and a pass voltage which are used in a read operation. The switch unit  220  sends the read voltage and the pass voltage to the first and second row decoders  230 ,  240 . The first and second row decoders  230 ,  240  supply the read voltage and the pass voltage to a plurality of word lines WL&lt;n:0&gt; of the first and second planes  110 ,  120 . 
         [0030]    The flag cell data detection circuit  300  determines the program methods of the first and second planes  110 ,  120  (that is, whether they have been programmed using a single level cell method or a multi-level cell method) by comparing the data of the flag cells and the data of the flag cells, sensed by the first page buffer unit  130  and the second page buffer unit  140 . 
         [0031]    The flag cell data detection circuit  300  includes a flag cell data detection unit  310 , first and second registers  320 ,  330 , and a comparison unit  340 . The flag cell data detection unit  310  receives the data of the flag cells corresponding to the first and second page buffer units  130 ,  140  and sends the received data to the first and second registers  320 ,  330 . The first and second registers  320 ,  330  stores the received data of the flag cells and outputs them as first and second flag cell data signals Flag-1 and Flag-2. The comparison unit  340  determines whether the first and second flag cell data signals Flag-1 and Flag-2 are the same logic signal by comparing the first and second flag cell data signals Flag-1 and Flag-2 and outputs a comparison signal camp. 
         [0032]    The microcontroller  400  outputs a first control signal CS 1  and a second control signal CS 2  controlling the first page buffer unit  130  and the second page buffer unit  140 , respectively, in response to the first and second flag cell data signals Flag-1 and Flag-2 and the comparison signal camp. 
         [0033]      FIG. 4  is a flowchart illustrating a read method for the least significant bit (LSB) pages of the semiconductor memory device according to an exemplary embodiment of this disclosure. 
         [0034]    The read method of the least significant bit (LSB) pages according to the exemplary embodiment of this disclosure is described below with reference to  FIGS. 1 ,  3 , and  4 . 
         [0035]    (1) First Read Operation—L 410   
         [0036]    When a least significant bit (LSB) page address is inputted to the semiconductor memory device, a read operation is performed on the least significant bit (LSB) pages of the first and second planes  110 ,  120 . 
         [0037]    First, data of the memory cells and the flag cells of the first and second planes  110 ,  120  is sensed by performing a first read operation using a first read voltage RD 1 . Here, the pages of the first and second planes  110 ,  120 , having the same page address, are selected and the data of the memory cells and the flag cells of the selected pages is sensed. The sensed data of the memory cells and the flag cells is temporarily stored in the respective main latches of the first and second page buffer units  130 ,  140 . 
         [0038]    (2) Store Data of Flag Cells—L 420   
         [0039]    The data of the flag cells stored in the main latches of the first and second page buffer units  130 ,  140  is sent to the flag cell data detection unit  310 . The flag cell data detection unit  310  sends the received data of the flag cells to the first register  320  and the second register  330 , respectively. That is, the data of the flag cells of the first plane  110  is stored in the first register  320 , and the data of the flag cells of the second plane  120  is stored in the second register  330 . 
         [0040]    (3) Compare Data of Flag Cells of First Plane and Data of Flag Cells of Second Plane—L 430   
         [0041]    The comparison unit  340  determines whether the flag cell data signal Flag-1, indicating the data of the flag cells of the first plane  110  stored in the first register  320 , and the flag cell data signal Flag-2, indicating the data of the flag cells of the second plane  120  stored in the second register  330 , have the same value and output the comparison signal camp. For example, if, as a result of the determination, the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have the same value, the comparison unit  340  outputs the comparison signal camp of a high level. However, if, as a result of the determination, the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have different values, the comparison unit  340  outputs the comparison signal camp of a low level. 
         [0042]    (4) Determine Data of Flag Cells of Second Plane—L 440   
         [0043]    If, as a result of the determination at step L 430 , the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have different values, it is determined whether the sensed data of the flag cells of the second plane  120  is ‘1’. 
         [0044]    (5) Store Data of First Plane in Temporary Latch of First Page Buffer Unit—L 450   
         [0045]    If, as a result of the determination at step L 440 , the sensed data of the flag cells of the second plane  120  is determined not to be ‘1’ (that is, ‘0’), it means that the first plane  110  has been programmed by using a least significant bit (LSB) program method, and the second plane  120  has been programmed by sequentially using a least significant bit (LSB) program method and a most significant bit (MSB) program method. 
         [0046]    In this case, the data of the memory cells stored in the main latch of the first page buffer unit  130  is stored in the temporary latch. 
         [0047]    (6) Perform Second Read Operation—L 460   
         [0048]    A second read operation using a second read voltage RD 2 . More specifically, data of the memory cells of the first and second planes  110 ,  120  is sensed and stored in the respective main latches of the first and second page buffer units  130 ,  140 . The second read operation using the second read voltage RD 2  is performed to read the least significant bit (LSB) data of a memory cell on which a least significant bit (LSB) program and a most significant bit (MSB) program have been sequentially performed. 
         [0049]    (7) Send Data of Temporary Latch of First Plane to Main Latch—L 470   
         [0050]    After the second read operation L 460 , the data stored in the temporary latch of the first page buffer unit  130  is stored in the main latch. Accordingly, the data sensed by the first read operation is stored in the main latch of the first page buffer unit  130 . 
         [0051]    (8) Store Data of Second Plane in Temporary Latch of Second Page Buffer Unit—L 480   
         [0052]    Meanwhile, if, as a result of the determination at step L 440 , the sensed data of the flag cells of the second plane  120  is determined to be ‘1’, it means that the first plane  110  has been programmed by sequentially using a least significant bit (LSB) program method and a most significant bit (MSB) program method, and the second plane  120  has been programmed by using a least significant bit (LSB) program method. 
         [0053]    In this case, the data of the memory cells of the second plane, stored in the main latch of the second page buffer unit  140 , is stored in the temporary latch of the second page buffer unit  140 . 
         [0054]    (9) Perform Third Read Operation—L 490   
         [0055]    A third read operation using a second read voltage RD 2  is performed. More specifically, data of the memory cells of the first and second planes  110 ,  120  is sensed and stored in the respective main latches of the first and second page buffer units  130 ,  140 . The third read operation using the second read voltage RD 2  is performed to read the least significant bit (LSB) data of a memory cell on which a least significant bit (LSB) program and a most significant bit (MSB) program have been sequentially performed. 
         [0056]    (10) Store Data of Second Plane in Main Latch of Second Page Buffer Unit—L 500   
         [0057]    After the third read operation L 490 , the data stored in the temporary latch of the second page buffer unit  140  is stored in the main latch of the second page buffer unit  140 . The data sensed by the first read operation L 410  is stored in the main latch of the second page buffer unit  140 . 
         [0058]    (11) Store Data of Main Latches of First and Second Page Buffer Units in Cache Latches—L 510   
         [0059]    After the steps L 470  and L 500 , the data of the first plane  110  and the second plane  120 , stored in the main latches of the first and second page buffer units  130 ,  140 , are stored in the cache latches of the first and second page buffer units  130 ,  140 . 
         [0060]    (12) Determine Data of Second Plane—L 520   
         [0061]    Meanwhile, if, as a result of the determination at step L 430 , the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have the same value, it is determined whether the data stored in the flag cells of the second plane  120  is ‘1’. If, as a result of the determination, the data stored in the flag cells of the second plane  120  is determined to be ‘1’, it means that the first and second planes  110  and  120  have been programmed by using a least significant bit (LSB) program method. In this case, the step L 510  is performed. That is, the data sensed by the first read operation L 410  is stored in the respective main latches of the first and second page buffer units  130 ,  140  and then stored in the cache latches of the first and second page buffer units  130 ,  140 . 
         [0062]    (13) Fourth Read Operation—L 530   
         [0063]    If, as a result of the determination at step L 520 , the data stored in the flag cells of the second plane  120  is determined not to be ‘1’ (that is, determined to be ‘0’), it means that the first and second planes  110  and  120  have been programmed by sequentially using a least significant bit (LSB) program method and a most significant bit (MSB) program method. In this case, a fourth read operation using a second read voltage RD 2  is performed. That is, the data of the memory cells stored in the first and second planes  110 ,  120  is sensed by performing the fourth read operation and respectively stored in the first and second page buffer units  130 ,  140 . The fourth read operation using the second read voltage RD 2  is performed to read least significant bit (LSB) data of a memory cell on which a least significant bit (LSB) program and a most significant bit (MSB) program have been sequentially performed. Next, the process returns to step L 510 . 
         [0064]    (14) Output Data—L 540   
         [0065]    After step L 510 , the data of the first plane  110  and the second plane  120 , stored in the cache latches of the first and second page buffer units  130 ,  140 , is outputted. 
         [0066]      FIG. 5  is a flowchart illustrating a read method for the most significant bit (MSB) pages of the semiconductor memory device according to an exemplary embodiment of this disclosure. 
         [0067]    The read method for the most significant bit (MSB) page according to the exemplary embodiment of this disclosure is described below with reference to  FIGS. 1 ,  3 , and  5 . 
         [0068]    (1) First Read Operation—M 410   
         [0069]    When a most significant bit (MSB) page address is inputted to the semiconductor memory device, a read operation is performed on the most significant bit (MSB) pages of the first and second planes  110 ,  120 . 
         [0070]    First, data of the memory cells and the flag cells of the first and second planes  110 ,  120  is sensed by performing a first read operation using a first read voltage RD 1 . Here, the pages of the first and second planes  110 ,  120 , having the same page address, are selected and the data of the memory cells and the flag cells of the selected pages is sensed. The sensed data of the memory cells and the flag cells is temporarily stored in the first and second page buffer units  130 ,  140 , respectively. 
         [0071]    (2) Store Data of Flag Cells M 420   
         [0072]    The data of the flag cells stored in the first and second page buffer units  130 ,  140  is sent to the flag cell data detection unit  310 . The flag cell data detection unit  310  sends the received data of the flag cells to the first register  320  and the second register  330 , respectively. That is, the data of the flag cells of the first plane  110  is stored in the first register  320 , and the data of the flag cells of the second plane  120  is stored in the second register  330 . 
         [0073]    (3) Compare Data of Flag Cells of First Plane and Data of Flag Cells of Second Plane—M 430   
         [0074]    The comparison unit  340  determines whether the flag cell data signal Flag-1, indicating the data of the flag cells of the first plane  110  stored in the first register  320 , and the flag cell data signal Flag-2, indicating the data of the flag cells of the second plane  120  stored in the second register  330 , have the same value and outputs the comparison signal camp. For example, if, as a result of the determination, the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have the same value, the comparison unit  340  outputs the comparison signal camp of a high level. However, if, as a result of the determination, the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have different values, the comparison unit  340  outputs the comparison signal camp of a low level. 
         [0075]    (4) Determine Data of Flag Cells of Second Plane—M 440   
         [0076]    If, as a result of the determination at step M 430 , the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have different values, it is determined whether the sensed data of the flag cells of the second plane  120  is ‘1’. 
         [0077]    (5) Second Read Operation—M 450   
         [0078]    If, as a result of the determination at step M 440 , the data of the flag cells of the second plane  120  is determined not to be ‘1’ (that is, determined to be ‘0’), it means that the first plane  110  has been programmed by using a least significant bit (LSB) program method, and the second plane  120  has been programmed by sequentially using a least significant bit (LSB) program method and a most significant bit (MSB) program method. 
         [0079]    Thus, a second read operation using a second read voltage RD 2  is performed. That is, the data of the memory cells of the first and second planes  110 ,  120  is sensed using the second read voltage RD 2  and stored in the respective main latches of the first and second page buffer units  130 ,  140 . Subsequently, the data stored in the main latches is sent to the cache latches of the first and second page buffer units  130 ,  140  and then outputted. 
         [0080]    (6) Third Read Operation M 460   
         [0081]    A third read operation using a third read voltage RD 3  is performed. That is, the data of the memory cells of the first and second planes  110 ,  120  is sensed using the third read voltage RD 3  and stored in the respective main latches of the first and second page buffer units  130 ,  140 . Subsequently, the data stored in the main latches is sent to the cache latches of the first and second page buffer units  130 ,  140  and then outputted. 
         [0082]    (7) Change Data of First Plane to ‘1’—M 470   
         [0083]    The data of the first plane  110  read by the second and third read operations is changed to ‘1’. That is, since the first plane  110  has been programmed by using only the least significant bit (LSB) program method, the most significant bit (MSB) data of the first plane  110  is changed to ‘1’ and outputted, when a most significant bit (MSB) read operation is performed. 
         [0084]    (8) Fourth Read Operation—M 480   
         [0085]    If, as a result of the determination at step M 440 , the data of the flag cells of the second plane  120  is determined to be ‘1’, it means that the first plane  110  has been programmed by sequentially using a least significant bit (LSB) program method and a most significant bit (MSB) program method, and the second plane  120  has been programmed by using a least significant bit (LSB) program method. 
         [0086]    Thus, a fourth read operation using a second read voltage RD 2  is performed. That is, the data of the memory cells of the first and second planes  110 ,  120  is sensed using the second read voltage RD 2  and stored in the respective main latches of the first and second page buffer units  130 ,  140 . Subsequently, the data stored in the main latches of the first and second page buffer units  130 ,  140  is sent to the cache latches thereof and then outputted. 
         [0087]    (9) Fifth Read Operation M 490   
         [0088]    A fifth read operation using a third read voltage RD 3  is performed. That is, the data of the memory cells of the first and second planes  110 ,  120  is sensed using the third read voltage and stored in the respective main latches of the first and second page buffer units  130 ,  140 . Subsequently, the data stored in the main latches of the first and second page buffer units  130 ,  140  is sent to the cache latches thereof and then outputted. 
         [0089]    (10) Change Second Plane Data ‘1’—M 500   
         [0090]    The data of the second plane  120  read by the fourth and fifth read operations M 480 ,  490  is changed to ‘1’. That is, since the second plane  120  has been programmed by using only the least significant bit (LSB) program method, the most significant bit (MSB) data of the first plane  110  is changed to ‘1’ and outputted, when a most significant bit (MSB) read operation is performed. 
         [0091]    (11) Determine Data of Second Plane—M 510   
         [0092]    Meanwhile, if, as a result of the determination at step M 430 , the flag cell data signal Flag-1 and the flag cell data signal Flag-2 are determined to have the same value, it is determined whether the data of the flag cells of the second plane  120  is ‘1’. 
         [0093]    (12) Change Data to ‘1’—M 520   
         [0094]    If, as a result of the determination at step M 510 , the data of the flag cells of the second plane  120  is determined to be ‘1’, it means that both the first and second planes  110 ,  120  have been programmed by using a least significant bit (LSB) program method. In this case, both the data of the first and second planes  110 ,  120 , read by the first read operation at step M 410 , is changed to ‘1’. That is, both the most significant bit (MSB) data is changed to ‘1’. 
         [0095]    (13) Sixth Read Operation—M 530   
         [0096]    However, if, as a result of the determination at step M 510 , the data of the flag cells of the second plane  120  is determined not to be ‘1’ (that is, determined to be ‘0’), it means that both the first and second planes  110 ,  120  have been programmed by using a multi-level cell program method. In this case, the data of the memory cells of the first and second planes  110 ,  120  is read by performing a sixth read operation using a second read voltage RD 2  and then outputted. 
         [0097]    (14) Seventh Read Operation—M 540   
         [0098]    Next, the data of the memory cells of the first and second planes  110 ,  120  is read by performing a seventh read operation using a third read voltage RD 2  and then outputted. 
         [0099]    (15) Output Data M 550   
         [0100]    After steps M 470 , M 500 , M 520 , and M 540  are performed, the data outputted by the read operations is combined and outputted as most significant bit (MSB) data. 
         [0101]    As described above, according to the exemplary embodiments of this disclosure, in case where a first plane and a second plane are programmed by using different program methods in read operations for a least significant bit (LSB) page and a most significant bit (MSB) page, it is first determined as to which one of program methods that the planes have been programmed, and data of the planes is then read on the basis of results of the determination. Accordingly, error in detecting data can be prevented/reduced when data is outputted. 
         [0102]    More specifically, in a read operation of a semiconductor memory device including first and second planes, it is first determined whether the first and second planes have been programmed by the same method by comparing data of the flag cells of the first and second planes. Next, a read method corresponding to the program method of each plane is used. Accordingly, error in detecting data can be prevented/reduced in the read operation.