Abstract:
A DC-DC converter control circuit disclosed herein comprises a first switching element having a first terminal to which a first voltage is supplied and a second terminal which is connected to an output node; a second switching element having a first terminal which is connected to the output node and a second terminal to which a second voltage lower than the first voltage is supplied; and a control circuit which outputs a first control signal to a control terminal of the first switching element and outputs a second control signal to a control terminal of the second switching element so as to control on/off states of the first switching element and the second switching element, wherein the control circuit switches the second switching element from the off state to the on state after detecting that the first switching element is in the off state when switching the second switching element from the off state to the on state.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]    This application claims benefit of priority under 35 U.S.C.§119 to Japanese Patent Application No. 2003-115861, filed on Apr. 21, 2003, the entire contents of which are incorporated by reference herein. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    1. Field of the Invention  
           [0003]    The present invention relates to a DC-DC converter control circuit and a DC-DC converter, and particularly relates to a DC-DC converter control circuit and a DC-DC converter in which simultaneous on states of its high side and low side are avoided.  
           [0004]    2. Description of the Related Art  
           [0005]    [0005]FIG. 1 is a diagram showing the circuit configuration of a related DC-DC converter control circuit. As shown in FIG. 1, the DC-DC converter control circuit includes a control circuit  10  and transistors Q 1  and Q 2 .  
           [0006]    This DC-DC converter operates as follows. First, (1) when an input control signal IN is low, an output of a NAND circuit ND 1  is high. This output of the NAND circuit ND 1  is inputted to a high-side level shift circuit  30 . The high-side level sift circuit  30  is a circuit which raises a signal using a ground voltage as a reference to a signal using a voltage VLX of a node LX as a reference. Therefore, when an input to the level sift circuit  30  is high, the level sift circuit  30  outputs a signal which is at a high level relative to the voltage VLX as the reference.  
           [0007]    Accordingly, when the input control signal IN is low, the level shift circuit  30  outputs a high, whereby the transistor Q 11  is switched on and the transistor Q 12  is switched on. Hence, a node HO is low, and the transistor Q 1  which is a main switching element is in an off state.  
           [0008]    A mask time setting circuit  40  is a circuit which delays the input control signal IN for a predetermined period of time and then outputs it to the NAND circuit ND 1  and a NOR circuit NR 1 . Therefore, when the input control signal IN is in a low-level stable state, the mask time setting circuit  40  outputs a low-level signal. As a result, the NOR circuit NR 1  outputs a high-level output to an inverter circuit INV 1 . Hence, an input to a level shift circuit  32  is low.  
           [0009]    The level shift circuit  32  is a circuit which is provided to be matched with the high-side level sift circuit  30  and outputs an inputted signal without change. Therefore, an output of the level shift circuit  32  is low, whereby a transistor Q 21  is switched on, and a transistor Q 22  is switched off. As a result, a node LO goes high, and the transistor Q 2  which is a switching element for synchronous rectification is switched on. Thereby, an output node is connected to a ground via the transistor Q 2 , and an output voltage OUT 1  drops. With the drop in the output voltage OUT  1 , an output voltage OUT 2  between an inductance L 1 , and a capacitor C 1  and a load R also drops.  
           [0010]    (2) When the input control signal IN changes from low to high, the output of the NOR circuit NR 1  goes low, and an output of the inverter signal INV 1  goes high. Therefore, the output of the low-side level shift circuit  32  goes high, whereby the transistor Q 21  is switched off, and the transistor Q 22  is switched on. Hence, a node LO goes low, and the transistor Q 2  is switched off.  
           [0011]    On the other hand, the NAND circuit ND 1  outputs a high as heretofore until the output of the mask time setting circuit  40  goes high. Accordingly, the transistor Q 1  remains off. After the predetermined period of time, the output of the mask time setting circuit  40  changes from low to high.  
           [0012]    As a result, the output of the NAND circuit ND 1  goes low, and the output of the level shift circuit  30  also goes low. Hence, the transistor Q 11  is switched on, and the transistor Q 12  is switched off. Consequently, the node HO goes high, and the transistor Q 1  is switched on. Accordingly, an input voltage VIN is supplied to the output node via the transistor Q 1 , whereby the output voltages OUT 1  and OUT 2  rise.  
           [0013]    (3) when the input control signal IN changes from high to low, the output of the NAND circuit ND 1  goes high. Therefore, the output of the high-side level shift circuit  30  goes high, whereby the transistor Q 11  is switched off and the transistor Q 12  is switched on. Hence, the node HO goes low, and the transistor Q 1  is switched off.  
           [0014]    On the other hand, the NOR circuit NR 1  outputs a high as heretofore until the output of the mask time setting circuit  40  goes low. Accordingly, the transistor Q 2  remains off. After the predetermined period of time, the output of the mask time setting circuit  40  changes from high to low.  
           [0015]    As a result, the output of the NOR circuit NR 1  goes high, and the output of the inverter circuit INV 1  goes low. The output of the level shift circuit  32  also goes low, whereby the transistor Q 21  is switched on, and the transistor Q 22  is switched off. Consequently, the node LO goes high, and the transistor Q 2  is switched on. Accordingly, the output node is connected to the ground via the transistor Q 2 , and the output voltage OUT 1  drops.  
           [0016]    [0016]FIG. 2 is a diagram showing an example of operation waveforms of the DC-DC converter control circuit shown in FIG. 1. FIG. 2 shows level changes of the node LO and the node HO when the input control signal IN changes from high to low and thereafter changes from low to high.  
           [0017]    When the input control signal IN changes from high to low, the transistor Q 1  switches from the on state to the off state, and the transistor Q 2  switches from the off state to the on state. In this case, in order to avoid simultaneous on states of the transistor Q 1  and the transistor Q 2 , it is necessary that the transistor Q 2  is switched on after the transistor Q 1  is switched off. Therefore, the node HO changes from high to low, after being delayed for a delay time toff which is required for the operation of each element after the input control signal IN changes from high to low, whereas the node LO changes from low to high, after being delayed for a delay time ton of the mask time setting circuit  40  after the input control signal IN changes from high to low.  
           [0018]    This applies to a case where the input control signal IN changes from low to high, and hence the transistor Q 2  is switched off after being delayed for the delay time toff, and the transistor Q 1  is switched on after being delayed for the delay time ton.  
           [0019]    Such a DC-DC converter control circuit is disclosed, for example, in Japanese Patent Laid-open NO. Hei 9-117131, Japanese Patent Laid-open No. Hei 11-32477, and Japanese Patent Laid-open No. Hei 11-187651.  
           [0020]    In the circuit shown in FIG. 1, however, the delay time of the mask time setting circuit  40  needs to have a sufficient margin in consideration of variations in elements. Namely, the delay time of the mask time setting circuit  40  needs to be set long so as to prevent simultaneous on states of the transistor Q 1  and the transistor Q 2 .  
           [0021]    Hence, there arises a problem that the time required from when the high level/low level of the input control signal IN is changed until the transistor Q 1  or the transistor Q 2  is switched to the on state becomes longer and thereby the response of the circuit is deteriorated. However, unless the delay time of the mask time setting circuit  40  is set sufficiently long, the transistor Q 1  and the transistor Q 2  are simultaneously switched on, which causes an increase in power consumption, and at the worst, causes the possibility of destroying elements.  
         SUMMARY OF THE INVENTION  
         [0022]    In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a DC-DC converter control circuit, comprises:  
           [0023]    a first switching element having a first terminal to which a first voltage is supplied and a second terminal which is connected to an output node;  
           [0024]    a second switching element having a first terminal which is connected to the output node and a second terminal to which a second voltage lower than the first voltage is supplied; and  
           [0025]    a control circuit which outputs a first control signal to a control terminal of the first switching element and outputs a second control signal to a control terminal of the second switching element so as to control on/off states of the first switching element and the second switching element, wherein the control circuit switches the second switching element from the off state to the on state after detecting that the first switching element is in the off state when switching the second switching element from the off state to the on state.  
           [0026]    According to another aspect of the present invention, a DC-DC converter, comprises:  
           [0027]    a first switching element having a first terminal to which a first voltage is supplied and a second terminal which is connected to an output node;  
           [0028]    a second switching element having a first terminal which is connected to the output node and a second terminal to which a second voltage lower than the first voltage is supplied;  
           [0029]    a feedback circuit which compares a voltage of the output node with a reference voltage so as to generate a first control signal, wherein the feedback circuit outputs the first control signal; and  
           [0030]    a control circuit to which the first control signal is inputted and which controls a second control signal to be outputted to a control terminal of the first switching element and a third control signal to be outputted to a control terminal of the second switching element based on the first control signal so as to control on/off states of the first switching element and the second switching element, wherein the control circuit switches the second switching element from the off state to the on state after detecting that the first switching element is in the off state when switching the second switching element from the off state to the on state. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0031]    [0031]FIG. 1 is a diagram showing the circuit configuration of a related DC-DC converter control circuit;  
         [0032]    [0032]FIG. 2 is a diagram showing an example of operation waveforms of the DC-DC converter control circuit in FIG. 1;  
         [0033]    [0033]FIG. 3 is a diagram showing the schematic configuration of a DC-DC converter according to an embodiment;  
         [0034]    [0034]FIG. 4 is a diagram showing an example of a waveform of an output voltage of the DC-DC converter in FIG. 3;  
         [0035]    [0035]FIG. 5 is a diagram showing the circuit configuration of a DC-DC converter control circuit according to the embodiment; and  
         [0036]    [0036]FIG. 6 is a diagram showing an example of operation waveforms of the DC-DC converter control circuit in FIG. 5. 
     
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS  
       [0037]    In this embodiment, in a DC-DC converter control circuit including a low-side transistor and a high-side transistor, the on/off state of the high-side transistor is detected, and when the low-side transistor is switched from an off state to an on state, the low-side transistor is switched to the on state after the switching of the high-side transistor from the on state to the off state is detected. Further details will be given below.  
         [0038]    [0038]FIG. 3 is a diagram showing the schematic configuration of a DC-DC converter  50  according to this embodiment. As shown in FIG. 3, the DC-DC converter  50  according to this embodiment includes transistors Q 1  and Q 2 , a control circuit  100 ,a feedback circuit  110 , an inductance L 1 , and a capacitor C 1 . A load R is connected between the inductance L 1  and the capacitor C 1 . In this embodiment, the control circuit  100  and the transistors Q 1  and Q 2  are formed as one IC 60 , and this IC 60  corresponds to a DC-DC converter control circuit in this embodiment.  
         [0039]    An input voltage VIN of this DC-DC converter  50  is inputted to the transistor Q 1 , and an output voltage OUT 2  is outputted therefrom. The level to be shifted of the input voltage VIN, which is outputted as the output voltage OUT 2 , is determined by the on/off ratio between the transistor Q 1  and the transistor Q 2 . Namely, it is controlled depending on the ratio in which the control circuit  100  turns on the transistor Q 1  and the transistor Q 2 .  
         [0040]    More specifically, as shown in FIG. 4, the output voltage OUT 2  rises when the transistor Q 1  is on and the transistor Q 2  is off, whereas it drops when the transistor Q 1  is off and the transistor Q 2  is on. The feedback circuit  110  acquires the voltage of the output voltage OUT 2  and compares it with a reference voltage. The feedback circuit  110  outputs an input control signal IN of low level to the control circuit  100  when the output voltage OUT 2  is higher than the reference voltage, and outputs the input control signal IN of high level to the control circuit  100  when the output voltage OUT 2  is lower than the reference voltage. The control circuit  100  controls the on/off of the transistor Q 1  and the transistor Q 2  based on the level of the input control signal IN.  
         [0041]    In other words, when the output voltage OUT 2  is higher than the reference voltage, the control circuit  100  switches the transistor Q 1  off and the transistor Q 2  on. Contrary to this, when the output voltage OUT 2  is lower than the reference voltage, the control circuit  100  switches the transistor Q 2  off and the transistor Q 1  on. By repeating the aforementioned operation, the voltage of the output voltage OUT 2  is controlled to be equal to the reference voltage.  
         [0042]    [0042]FIG. 5 is a diagram showing the circuit configuration of the control circuit  100 . As shown in FIG. 5, the control circuit  100  according to this embodiment includes inverter circuits INV 2 , INV 3 , and INV 4 , NOR circuits NR 2  and NR 3 , a level shift circuit  120 , a first detection circuit  130 , a second detection circuit  140 , and transistors Q 11 , Q 12 , Q 21 , and Q 22 .  
         [0043]    In this embodiment, the transistor Q 11  is a P-type MISFET, the transistor Q 12  is an N-type MISFET, the transistor Q 21  is a P-type MISFET, and the transistor Q 22  is an N-type MISFET.  
         [0044]    A voltage BST is supplied to a source terminal of the transistor Q 11 , and a drain terminal of the transistor Q 11  is connected to a drain terminal of the transistor Q 12 . A source terminal of the transistor Q 12  is connected to a node LX. The drain terminal of the transistor Q 12  is also connected to a node HO. An output signal from the level shift circuit  120  is inputted to gate terminals of the transistor Q 11  and the transistor Q 12 .  
         [0045]    On the other hand, a voltage Vdd is supplied to a source terminal of the transistor Q 21 , and a drain terminal of the transistor Q 21  is connected to a drain terminal of the transistor Q 22 . A source terminal of the transistor Q 22  is connected to a ground. The drain terminal of the transistor Q 22  is also connected to a node LO. An output signal from the inverter circuit INV 4  is inputted to gate terminals of the transistor Q 21  and the transistor Q 22 .  
         [0046]    The level shift circuit  120  raises a signal using a ground voltage as a reference to a signal using a voltage VLX of a node LX as a reference. Therefore, when an input to the level sift circuit  120  is high, the level sift circuit  120  outputs a signal which is at a high level relative to the voltage VLX as the reference.  
         [0047]    The first detection circuit  130  is a circuit to detect the switching of the transistor Q 1  to the off state by monitoring the voltage of the node LX. In this embodiment, the first detection circuit  130  includes resistances R 1 , R 2 , and R 3 , and a transistor Q 30  which is an N-type MISFET.  
         [0048]    More specifically, one end of the resistance R 1  is connected to the node LX, and the other end of the resistance R 1  is connected to a drain terminal of the transistor Q 30 . A source terminal of the transistor Q 30  is connected to one end of the resistance R 2 , and the other end of the resistance R 2  is connected to a ground. One end of the resistance R 3  is connected to a gate terminal of the transistor Q 30 , and the voltage VDD is supplied to the other end of the resistance R 3 . A signal outputted from a node between the transistor Q 30  and the resistance R 2  is inputted to the NOR circuit NR 3 .  
         [0049]    The second detection circuit  140  is a circuit to detect the switching of the transistor Q 2  to the off state by monitoring the voltage of the node LO. In this embodiment, the second detection circuit  140  is configured by connecting inverter circuits INV 10  and INV 11  in series. Namely, the second detection circuit  140  buffers and outputs the voltage of the node LO.  
         [0050]    The transistor Q 1  and the transistor Q 2  each of which is an N-type MISFET are connected in series between the input voltage IN and a ground. Namely, the input voltage VIN is supplied to a drain terminal of the transistor Q 1 . A source terminal of the transistor Q 1  is connected to a drain terminal of the transistor Q 2  as well as to an output node. A source terminal of the transistor Q 2  is connected to the ground.  
         [0051]    A gate terminal of the transistor Q 1  is connected to the node HO, and hence the on/off state of the transistor Q 1  is controlled by the on/off states of the transistor Q 11  and the transistor Q 12 . A gate terminal of the transistor Q 2  is connected to the node LO, and hence the on/off state of the transistor Q 2  is controlled by the on/off states of the transistor Q 21  and the transistor Q 22 .  
         [0052]    One end of the inductance L 1  is connected to the output node. The other end of the inductance L 1  is connected to one end of the capacitor C 1  which is a smoothing capacitor. The other end of the capacitor Cl is connected to a ground. The load R is connected to a node between the inductance L 1  and the capacitor C 1 , and the output voltage OUT 2  is outputted therefrom.  
         [0053]    The DC-DC converter operates as follows. First, it is assumed that the node LX is high. In this case, the transistor Q 1  is on, and the transistor Q 2  is off.  
         [0054]    (1) It is assumed that the input control signal IN changes from high to low in this state. On the high side, an output of the inverter circuit INV 2  goes high. Accordingly, an output of the NOR circuit NR 2  is low, an output of the inverter circuit INV 3  is high, and hence the level shift circuit  120  outputs a high.  
         [0055]    Since the output of the level shift circuit  120  is high, the transistor Q 11  is switched off, and the transistor Q 12  is switched on, whereby the node HO goes low. Accordingly, the transistor Q 1  switches from the on state to the off state.  
         [0056]    On the other hand, on the low side, the low-level input control signal IN is inputted to the NOR circuit NR 3 . Since an output from the first detection circuit  130  is inputted to this NOR circuit NR 3 , an output of the NOR circuit NR 3  does not go high unless the output from the first detection circuit  130  goes low.  
         [0057]    Namely, when the node LX is high, the output of the first detection circuit  130  to the NOR circuit NR 3  is voltage Vdd−Vgs(Q 30 )=R 2 ×Ids(Q 30 ). Here, Vgs(Q 30 ) is the gate-source voltage of the transistor Q 30 , and Ids(Q 30 ) is the drain-source current of the transistor Q 30 .  
         [0058]    In this case, if R 2  is increased, Ids(Q 30 ) can be limited to a small current. Correspondingly, Vgs(Q 30 ) also decreases, and the output to the NOR circuit NR 3  goes high.  
         [0059]    Adequate time is required from when the input control signal IN changes from high to low until the high-side transistor Q 1  switches from the on state to the off state. Accordingly, at a point in time when the input control signal IN changes from high to low, the transistor Q 1  is not yet switched off, and hence the node LX remains high. Therefore, the output of the first detection circuit  130  remains high, and the output of the NOR circuit NR 3  remains low. As a result, the transistor Q 2  is maintained in the off state.  
         [0060]    When the transistor Q 1  switches from the on state to the off state after the adequate time, the voltage of the node LX drops. With the drop in the voltage of the node LX, Vds (Q 30 ) drops, and the transistor Q 30  switches from the on state to the off state. Here, Vds( 30 ) is the drain-source voltage of the transistor Q 30 . When the transistor Q 30  switches to the off state, the output voltage to the NOR circuit NR 3  becomes voltage VLS×R 2 /(R 1 +R 2 ). When the value of this voltage is lower than a threshold voltage of the NOR circuit NR 3 , the output of the NOR circuit NR 3  changes from low to high.  
         [0061]    When the output of the NOR circuit NR 3  goes high, the output of the inverter circuit INV 4  goes low, whereby the transistor Q 21  is switched on, and the transistor Q 22  is switched off. Thus, the node LO goes high, and the transistor Q 2  switches from the off state to the on state. As can be seen from the above, in this embodiment, after the first detection circuit  130  detects the switching of the transistor Q 1  from the on state to the off state, the transistor Q 2  switches from the off state to the on state. For this purpose, a high-side signal which is operating with a floating reference is converted to a signal with a ground reference and inputted to the NOR circuit NR 3  by the first detection circuit  130 .  
         [0062]    (2) Next, it is assumed that from the above state, the input control signal IN changes from low to high. On the low side, the high-level input control signal IN is inputted to the NOR circuit NR 3 , and the output of the NOR circuit NR 3  goes low. As a result, the output of the inverter circuit INV 4  goes high, whereby the transistor Q 21  is switched off, the transistor Q 22  is switched on, and the node LO goes low. Hence, the transistor switches from the on state to the off state.  
         [0063]    On the other hand, on the high side, the output of the inverter circuit INV 2  goes low, and a low-level signal is inputted to the NOR circuit NR 2 . Since an output from the second detection circuit  140  is inputted to this NOR circuit NR 2 , an output of the NOR circuit NR 2  does not go high unless the output from the second detection circuit  140  goes low.  
         [0064]    Namely, only after the voltage of the node LO changes from high to low and the transistor Q 2  switches from the on state to the off state, the output of the NOR circuit NR 2  goes high. When the node LO changes to low, the output of the NOR circuit NR 2  goes high, whereby the output of the inverter circuit INV 3  goes low and the output of the level shift circuit  120  also goes low. Hence, the transistor Q 11  is switched on, and the transistor Q 12  is switched off, whereby the node HO goes high. Consequently, the transistor Q 1  switches from the off state to the on state.  
         [0065]    As can be seen from the above, in this embodiment, after the second detection circuit  140  detects the switching of the transistor Q 2  from the on state to the off state, the transistor Q 1  switches from the off state to the on state. Namely, the second detection circuit  140  detects the switching of the transistor Q 2  to the off state by monitoring the voltage of the node LO.  
         [0066]    [0066]FIG. 6 is a diagram showing an example of operation waveforms of the DC-DC converter control circuit shown in FIG. 5. FIG. 6 shows level changes of the node LO and the node HO when the input control signal IN changes from high to low and thereafter changes from low to high.  
         [0067]    As can be seen from a comparison with FIG. 2, a delay time ton when the transistor Q 1  and the transistor Q 2  each switch from the off state to the on state is shorter than that in the related art. Namely, when the input control signal IN changes from high to low, the node HO changes from high to low after being delayed for a delay time toff, whereas the node LO changes from low to high after being delayed for the delay time ton. According to the DC-DC converter control circuit according to this embodiment, the delay time ton is shorter than that of the related DC-DC converter control circuit.  
         [0068]    This applies to a case where the input control signal IN changes from low to high, and the delay time ton of the high-side transistor Q 1  is shorter than that in the related art. Hence, according to the DC-DC converter control circuit and the DC-DC converter according to this embodiment, fast responsiveness can be achieved.  
         [0069]    Moreover, since the gate voltage of the transistor Q 30  is used as a low-voltage power source, the DC-DC converter control circuit according to this embodiment can be realized by using a MISFET fabricated by a fine process, and the operating range for the input voltage VIN can be increased.  
         [0070]    It should be mentioned that the present invention is not limited to the aforementioned embodiment, and various changes may be made therein. For example, although the MISFET is used as an example of the switching element in the aforementioned embodiment, the switching element can be realized by some other element. Moreover, the circuit configuration of the first detection circuit  130  is not limited to the configuration in the aforementioned embodiment, and an equivalent function may be realized by some other circuit configuration.