Abstract:
A circuit and method of demodulating an FSK signal uses digital circuitry to convert the received signal into count values. For each reception an adaptive reference count value is determined by averaging the duration of received pulses during the preamble of the transmission. The adaptive reference count corresponds to a demodulated logic &#34;1&#34; or logic level &#34;0&#34;. The counts from the coded portion of the transmission are compared to the adaptive reference count. If the count is within predetermined windows from the reference count, the count value is converted to the corresponding digital signal.

Description:
BACKGROUND OF THE INVENTION 
     The present invention is directed to frequency-shift keyed (FSK) demodulating circuits and more specifically to an adaptive digital demodulating circuit. 
     Frequency-shift keyed signals are found in a variety of applications involving data transmission such as RF transmissions and telephone data transmission. FSK signals use two distinct frequencies to represent logic level &#34;1&#34; signal and the logic level &#34;0&#34; signals. A demodulating circuit converts the frequency data to a digital format for use in associated circuitry. 
     Several techniques are known for demodulating FSK signals. One method described in U.S. Pat. No. 4,574,247 requires the derivation of a reference signal from a full data signal train that requires both the &#34;1&#34; and &#34;0&#34; frequencies to be present. The two frequencies must be present for a relatively large amount of time to set a reference before data reception. The reference value obtained represents a frequency between the logic 0 value and the logic 1 value. One disadvantage of the circuit is that noise contained in the input signal causes the reference to be set incorrectly. 
     Other methods of demodulating an FSK signal use a phase lock loop to provide feedback. One drawback to such circuits is the high cost due to the high number of components. Another disadvantage is that during the manufacturing process the phase lock loop requires calibration. Such circuits are not easily manufacturable on a single integrated circuit. 
     It would be desirable to provide a low cost, low part count circuit that can be fabricated on one integrated circuit to reliably demodulate an FSK signal. 
     SUMMARY OF THE INVENTION 
     One object of the present invention is to provide an FSK demodulation circuit fabricated on a single integrated circuit. 
     One advantage of the present invention is that an adaptive reference count is determined in each transmission from a relatively small number of samples of either the logic 1 frequency or the logic 0 frequency. 
     The present invention is a circuit for demodulating an FSK signal having a first frequency with a corresponding first period and a second frequency with a corresponding second period. The FSK signal has a preamble with a period corresponding to a selected one of the first period or the second period and a coded signal portion which alternates between the first and second periods. The circuit includes a receiving means receiving an FSK signal and a clock means for generating a clock signal having a third frequency corresponding to a third period substantially shorter than the first period and the second period. The counter means is connected to the clock means and the receiving means for generating a count corresponding to a number of third periods of the clock signal during a period of the FSK signal. An averaging means is coupled to the counter means for calculating an adaptive reference count by averaging a predetermined number of counts during the preamble. The reference count represents either the high or low logic level. A comparing means compares the count occurring during the coded signal portion with the adaptive reference count. An output means provides a digital level output signal based whether the count is within a predetermined range from the adaptive reference count, the predetermined range corresponds to either a valid low logic or a valid high logic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a passive anti-theft system including the demodulating circuit according to the present invention. 
     FIG. 2 is the analog signal received from the transponder. 
     FIG. 3 is a processed version of FIG. 2. 
     FIG. 4 is a digital message signal corresponding to the signals of FIGS. 1 and 2. 
     FIG. 5 is a graph of signals at predetermined points in FIG. 1. 
     FIG. 6 is a detailed block diagram of the DSP filter of FIG. 1. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1, a passive anti-theft system for a motor vehicle includes a key 10 having a shank portion 12 cut for insertion and mechanical activation of a lock cylinder (not shown). Key 10 also has an encoded transponder 14 that generates a coded FSK signal. A function, such as allowing an engine of an automobile to start, is enabled if both the code of the FSK signal and the cut key match the particular vehicle. 
     An antenna 16 receives the FSK signal transmitted from transponder 14 as a sinusoidal waveform, signal A in FIG. 2. The coded signal contains two frequencies, 123 KHz and 134 KHz that are eventually converted to a &#34;logic 1&#34; and a &#34;logic 0&#34; respectively. Each FSK signal generated by transponder 14 has a preamble or initial period 2 ms long of either the logic 1 or the logic 0 frequency to allow calculation of an adaptive reference as described further below. The coded portion of the signal follows the initial 2 ms. 
     The frequencies generated correspond to the specifications of transponder 14. The same antenna circuitry in the transponder transmits both the logic 1 and logic 0 frequencies. The circuitry in the transponder in this example is calibrated around the logic 0 frequency. Consequently, the frequency tolerance around the logic 0 frequency is much narrower than the logic 1 frequency. Logic 0 has a center frequency at 135.25±3.75 Hz and the logic 1 has a center frequency of 124±4 Hz. Because the same antenna and associated circuitry generate both the logic 0 and logic 1 frequencies, any drifts of the frequencies occurring due to temperature or other variations are essentially the same for both logic 1 and logic 0. As a result, only one frequency needs to be used in the preamble of the transmission for the purpose of obtaining a frequency reference in the receiver. 
     An amplifier and limiter block 18 processes the received analog signal and converts it into a square wave, signal B of FIG. 3. Block 18 uses a comparator to compare the amplitude of the analog signal to a reference voltage. The output signal of the comparator changes state when the input signal crosses the reference voltage threshold. 
     The output of amplifier and limiter block 18 is input to a digital counter 20 having an 8 bit output. It should be understood that the number of output bits may vary according to the range of counts required. Digital counter 20 is connected to a clock 22 that is a high precision clock source such as a crystal oscillator having a frequency substantially higher than the period of the signal transmitted by transponder 14. Clock 22 is preferably 16,104 MHz which is over 100 times faster than the FSK signal frequencies. Digital counter 20 counts the number of clock periods per period of the square wave from the amplifier and limiter block 18 (hereinafter referred to as counts). The time corresponding to one period (i.e., one count) is about 62 ns. The count value is a direct measurement of the period of the digital signal and has an inverse relationship to the frequency of the FSK signal from transponder 14. FIG. 5 shows a sample output of the digital count as signal C. The detection of where to start and stop counting may be performed by an edge detector. 
     A sequencer state machine 23 controls the flow of the signal throughout the circuit. Sequencer state machine 23 may be a microprocessor. 
     A DSP filter 24 processes the signals from digital counter 20 to improve the accuracy of the signal when noise commonly found in automotive environments is present. Although not required, DSP filter 24 can be used to improve the reliability of the system. Filter 24 may be implemented with a digital-to-analog converter in series with an RC low pass filter followed by an analog to digital converters a D-to-A converter in series with a switched capacitor type filter followed by an A-to-D converter or by using a straight feedback gain type DSP filter (an example of which is further described in reference to FIG. 6). Signal D of FIG. 5 is the output of DSP filter 24. 
     The counts from DSP filter 24 taken during the preamble of each transmission are input to an averager 26. Averager 26 averages the counts for a predetermined number of periods within the preamble. In the present invention the counts of ten cycles of the logic 0 frequency transmitted within the first 2 ms of each transmission are averaged. Adaptive reference block 28 stores the average of the ten cycles as the adaptive reference count for the transmission. Adaptive reference count is the basis for each of the subsequent logic level determinations of the following transmission. Adaptive reference count is signal E of FIG. 5. 
     Magnitude comparator 30 compares the adaptive reference count to the count of the processed FSK signal. Because the tolerances of the transponder, windows are set with respect to the adaptive reference count. The width of the windows is set according to tolerances of the transponder. In the present invention, logic 0 ranges from -4 to +3 counts from the adaptive reference count. Logic 1  is from +4 to +17 counts from the adaptive reference count. Invalid frequencies are those less than -4 counts and above 17 counts from the adaptive reference count. Magnitude comparator also provides an indication whether there has been a carrier time out which is a result of the counter overflowing. The output of magnitude comparator 30 shown as signal F of FIG. 5. is a 2 bit number shown according to the following chart: 
     
         ______________________________________COMPARATOR OUTPUT    MEANING______________________________________00                   Invalid frequency01                   Valid 010                   Valid 111                   Carrier time out______________________________________ 
    
     A decision block 32 converts the two bit output of magnitude comparator 30 into a serial logic 0 or logic 1 level signal. Decision block 32 may directly translate the two bit output into a digital level signal or, in addition, decision block 32 acts as a form of digital filter. Decision block 32 in the present invention waits for a predetermined number of two bit outputs to be the same before changing its output signal as a further form of digital processing. For example, if the output of decision block 32 is a logic 1, then three consecutive logic 0s must be present before the output level changes. Also if four consecutive carrier timeouts occur, decision block 32 generates a loss of carrier signal indicating whether an incoherent signal is present. Signal G of FIG. 5 is the output of decision block. 
     Counter 20, sequencer state machine 23, DSP filter 24, averager 26, adaptive reference block 28, magnitude comparator 30, and decision block 32 may all be fabricated on one integrated circuit 33. Integrated circuit 33 receives the input signal and provides a digital level output signal. 
     Referring now to FIG. 5, a graph of the above mentioned signals is shown. In the beginning of the time period shown, a logic 1 is being transmitted. Sinal C is somewhat erratic due to noise. The smoothing effect of the digital filter on signal D is shown in comparison to signal C. Also, the output signal does not change from a logic 0 until three consecutive logic level 0s are received. 
     Referring now to FIG. 6, a preferred example of DSP filter 24 is shown. The input to the filter is a count from counter 20. The count is multiplied by an input constant in block 34. A summer 36 adds the output of the filter multiplied by a feedback constant 42 to get a signal called NEXT. The formula in algebraic terms is: ##EQU1## 
     An input constant for the above equation of 48 and a feedback constant of 208 have been satisfactorily employed. 
     A multiplexor 38 has two inputs: the NEXT signal and the OUTPUT signal, one of which is passed to a register 40. Multiplexor 38 switches inputs when the counter has stopped counting (i.e., on the edge of a subsequent input period). Register 40 stores the value from multiplexor 38. Multiplexor will only store a new count value in register 40 if the NEXT signal is within a predetermined range. For example, from the configurations described above, the predetermined range is between 90 to 160. If the NEXT signal is not within a predetermined range, the value in register 40 remains the same. 
     Various modifications will be apparent to those skilled in the art. For example, the FSK frequencies generated, the clock frequency, and the number and range of the counts are all modifications which are within the true spirit of the scope of the appended claims.