Abstract:
A time-to-digital converter includes at least one chain of delay elements, a status of which represents a digital signal relating to a time interval to be converted. The converter includes a provider for providing trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in the chain of delay elements, a capturer for capturing the status of the chain of delay elements in response to the calibration trigger signals, the status depending on delay times of the delay elements, a determiner for determining an actual contribution of at least some of the delay elements to an overall delay of the chain of delay elements on the basis of occurrences of pulse positions in response to the calibration trigger signals. The converter is configured to take into account the actual contribution of at least some of the delay elements when converting the time interval into said digital signal.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present invention relates to a time-to-digital converter and a method for time-to-digital conversion. 
       SUMMARY 
       [0002]    According to an embodiment, a time-to-digital converter may have: at least one chain of delay elements, wherein a status of said chain of delay elements represents a digital signal relating to a time interval to be converted, a provider for providing calibration trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in said chain of delay elements, capturer for capturing said status of said chain of delay elements in response to said calibration trigger signals, wherein said status depends on delay times of said delay elements, a determiner for determining an actual contribution of at least some of said delay elements to an overall delay of said chain of delay elements on the basis of occurrences of pulse positions in response to said calibration trigger signals, wherein the converter is configured to take into account said actual contribution of at least some of said delay elements when converting said time interval into said digital signal. 
         [0003]    According to another embodiment, a method for time-to-digital conversion using a time-to-digital converter having at least one chain of delay elements, wherein a status of said chain of delay elements represents a digital signal relating to a time interval to be converted, may have the steps of: providing calibration trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in said chain of delay elements; capturing said status of said chain of delay elements in response to said calibration trigger signals, wherein said status depends on delay times of said delay elements; determining an actual contribution of at least some of said delay elements to an overall delay of said chain of delay elements on the basis of occurrences of pulse positions in response to said calibration trigger signals; and taking into account said actual contribution of at least some of said delay elements when converting said time interval into said digital signal. 
         [0004]    Another embodiment may have a software program or product, stored on a data carrier, for controlling or executing the method for time-to-digital conversion using a time-to-digital converter having at least one chain of delay elements, wherein a status of said chain of delay elements represents a digital signal relating to a time interval to be converted, said method including: providing calibration trigger signals having statistically equally distributed variable positions relative to a pulse forwarded in said chain of delay elements; capturing said status of said chain of delay elements in response to said calibration trigger signals, wherein said status depends on delay times of said delay elements; determining an actual contribution of at least some of said delay elements to an overall delay of said chain of delay elements on the basis of occurrences of pulse positions in response to said calibration trigger signals; and taking into account said actual contribution of at least some of said delay elements when converting said time interval into said digital signal, when run on a data processing system such as a computer. 
         [0005]    According to embodiments of the present invention, a time-to-digital converter is realized which comprises at least one chain of delay elements. In an embodiment the delay elements are arranged in series having a first and a last delay element. In an alternative embodiment the chain of delay elements is built-up in a closed loop, thus establishing a closed ring that can be excited for oscillation forming a ring oscillator. 
         [0006]    Embodiments can realize e.g. time-to-digital conversion for time stamping applications or time interval measurements. Alternative embodiments can be applied for jitter measurements in digital systems, dynamic phase-locked-loop (PLL) measurements, demodulation of phase modulated or frequency modulated carrier with high linearity and/or analog-to-digital conversion with high linearity. High resolution time-to-digital converter have application in a number of measurement systems, e. g. time-of-flight particle detectors, laser range-finders and logic analyzers. Modern time-of-flight spectrometry systems, used in particle physics experiments as well as in industrial methods of material surface analysis necessitate a time-to-digital converter to have a resolution well below 1 ns, low dead-time, and a large dynamic range. 
         [0007]    In an embodiment the means for providing trigger signals is chosen such that all pulse positions in time have equal probability. In an embodiment any stable clock of the existing system can be used that is not too close to a multiple or to a sub-multiple of the frequency of the ring oscillator formed by the delay elements. The trigger rate will not be correlated, because the frequency of the ring oscillator is independent from the trigger source. 
         [0008]    In an embodiment the means for capturing said status of said chain of delay elements in response to said calibration trigger signals is realized by a register being clocked by the trigger signal. The register reads-out the status of the chain of delay elements. A Pulse position logic unit determines the position of the pulse within the chain of delay elements at the point in time when the trigger signal has a rising and/or when the trigger signal has a falling edge. The pulse position is a measure in digital form for the time to be converted. 
         [0009]    During a calibration phase all possible pulse positions occur with the same probability and thus with equidistribution. For ideal delay elements having all the same delay time, the resulting pulse positions would also be equidistributed. Due to variation of the individual delay time of the plurality of delay elements, may those variations arise from manufacturing, change of physical environment conditions like temperature, pressure, humidity, and/or due to aging effects, the resulting pulse positions are not equidistributed. 
         [0010]    According to an embodiment, the non-equidistribution is not physically compensated but detected and quantified. The actual contribution of at least some, advantageously of all of said delay elements, to an overall delay of said chain of delay elements is determined and subsequently taken into account during the conversion phase when converting said time interval into said digital signal. In an embodiment the number of inputs of the register capturing the status of the delay elements is equal or greater to the number of delay elements. Each input can be assigned to a particular corresponding delay element. 
         [0011]    In an embodiment the converter comprises a coarse time converter unit and a fine time converter unit, the results of which are combined. The coarse time converter unit can count the number of clock edges of a system or converter clock. The chain of delay elements can either be part of the coarse time counter unit and/or of a fine time counter unit. In an embodiment the chain of delay elements is arranged as a ring oscillator being part of the coarse as well as of the fine time converter unit. A single coarse time counter can count the number of periods of the oscillations of the ring oscillator, said number of periods representing the coarse time part of the time to be converted. Such an embodiment is advantageous over the known art, even without the above described calibration. 
         [0012]    In an embodiment the coarse time converter unit comprises at least two coarse time counters being connected to delay elements being far apart from each other within the chain of delay elements, e.g. a first coarse time counter in a middle position of the chain and a second coarse time counter at the end of the chain. The output of that coarse time counter is chosen to contribute to the conversion which is further away from the position of the pulse within the chain to avoid any transient effects of the delay elements and/or the coarse time counter to the result of the conversion. 
         [0013]    In an embodiment the delay elements are arranged in a single delay chain using the calibration as described above. In an alternative embodiment the converter comprises at least two chains of delay elements, e.g. the converter comprises a Vernier delay line comprising two open (no closed loop) chains of delay elements. The delay time of the delay elements of the first chain is longer than the delay time of the delay elements of the second chain. A first pulse is injected in the first chain and after a time interval, said time interval is to be converted in a digital signal, a second pulse is injected in the second chain. If the delay line is long enough, the second pulse catches-up the first pulse due to shorter delay time of the delay elements of the second chain. The position at which the second pulse catches-up the first pulse is a measure in digital form for the time interval between the first and second pulse. 
         [0014]    In an embodiment a relation between the time interval to be converted and the position at which the second pulse catches-up the first pulse is established. Due to variations in the delay time of individual delay elements it is possible that—against the general rule—a particular delay element in the first chain has a shorter delay time than the corresponding delay element in the second chain. This can result in non-monotonicity of the relation between time interval and catch-up position. In an embodiment the particular delay element is detected at which the pulse in the second chain catches-up the pulse in the first chain for the first time and/or for the last time and said relation is established accordingly. This results in a definite, monotonous relation. In an embodiment the calibration described above can be applied to such monotonous Vernier delay line resulting in excellent precision and linearity of time-to-digital conversion. 
         [0015]    The invention also relates to a corresponding method for time-to-digital conversion. In an embodiment a histogram is created from the status of the chain of delay elements in response to said calibration trigger signals. The histogram represents the frequencies of occurrences of the pulse individually at each delay element in response to the equidistributed calibration trigger signal. The histogram can be inverted, i.e. from the histogram the exact delay time can be derived for each individual delay element. In an embodiment those “measured” individual delay times can be stored, e.g. in a look-up table, and taken into account when converting said time into said digital signal. 
         [0016]    Embodiments of the invention can be partly or entirely embodied or supported by one or more suitable software programs, which can be stored on or otherwise provided by any kind of data carrier, and which might be executed in or by any suitable data processing unit. Software programs or routines can be applied during calibration phase and/or during conversion phase, in particular during the step of relating the pulse position to a digital time value, during correction of the related digital time value according to a correction table, for the decision which coarse counter is to be chosen and/or during combination of the outputs of coarse and fine time counter units. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS  
         [0017]    Other objects and many of the attendant advantages of embodiments of the present invention will be readily appreciated and become better understood by reference to the following more detailed description of embodiments in connection with the accompanied drawing(s). Features that are substantially or functionally equal or similar will be referred to by the same reference sign(s). 
           [0018]    Embodiments of the present invention will be detailed subsequently referring to the appended drawings, in which: 
           [0019]      FIG. 1  is a time-to-digital converter comprising a ring oscillator, 
           [0020]      FIG. 2  is a pulse diagram corresponding to the time-to-digital converter of  FIG. 1 , 
           [0021]      FIG. 3  is an embodiment of the present invention, 
           [0022]      FIG. 4  is the calculation of correction values to be stored in the correction table, 
           [0023]      FIG. 5  is the calibration of the total ring delay, 
           [0024]      FIG. 6  is a further embodiment of a time-to-digital converter, 
           [0025]      FIG. 7  is one possible embodiment of the Vernier delay line unit shown in  FIG. 6 , 
           [0026]      FIG. 8  is a timing diagram for an embodiment of the converter of  FIG. 6 , and 
           [0027]      FIG. 9  is an embodiment for the correction unit of the converter shown in  FIG. 6 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]      FIG. 1  shows a time-to-digital converter  10  comprising a ring oscillator  24 . The time-to-digital conversion is a combination of coarse time conversion and fine time conversion. A coarse time is determined by a coarse time converter unit  12  having a first input  14  connected to a stable reference clock  16  and a second input  18  connected to the output of a D flip-flop  20 . The second input  18  represents the COUNT ENABLE (CE) of the coarse counter  12 . A count value C is output at the output  22  representing the coarse time to be converted. 
         [0029]    A pulse is circulated in the ring oscillator  24  comprising a plurality of delay elements  26  and an odd number of inverters  28 . The output of each delay element  26  and of said inverter  28  is connected to a first fine time register  30  as well as to a second fine time register  32 . The state of the ring oscillator  24  is captured in the first fine time register  30  in response to a rising edge of a trigger signal  34  which is connected to the input  36  of the first fine time register  30  as well as to the input of D flip-flop  20 . A first pulse position logic unit  38  determines the pulse position within the ring oscillator  24  at the time of the rising edge of trigger signal  34 . 
         [0030]    With the following rising edge of clock  16  the state of the ring oscillator  24  is captured in the second fine time register  32 . A second pulse position logic  40  is connected with the second fine time register  32  and determines the pulse position within the ring oscillator  24  at the time of the following rising edge of clock signal  16 . The outputs of first and second pulse position logic units  38 ,  40  are connected with a delta time calculation unit  42 , the output  44  of which represents the fine time. 
         [0031]      FIG. 2  shows a pulse diagram corresponding to the time-to-digital converter  10  of  FIG. 1 . The upper line shows the rising edge of the trigger signal  34 . Correspondingly the first register  30  changes its state into “state  1 ”. The third line shows the clock  16  being a stable reference signal. The COUNT ENABLE (CE) signal at the second input  18  of coarse time converter unit  12  is shown in the fourth line, derived from the clock  16  and provided by the output of the D flip-flop  20 . If CE=0, then the coarse time converter unit  12  stops counting and keeps the last state C at its output  22 . The last line represents “state  2 ” of the second register  32 . 
         [0032]    In practice, mismatches of the many individual buffer delay elements  26  cause a non-linearity of the fine time measurement. The combination of fine time and coarse time conversion can even result in non-monotonicity, in particular at boundaries of the coarse counts, because coarse and fine conversion are based on different frequencies, i.e. the coarse time conversion is based on the clock frequency and the fine time conversion is based on the frequency of the ring oscillator  24 . In addition, within the fine time conversion different paths are used for capturing the state of the ring oscillator  24  in response to the trigger signal  34  and the clock signal  16 . Using different paths can introduce different mismatches. Furthermore, the large pulse position logic units  38 ,  40  are needed twice. 
         [0033]    Another time-to-digital conversion comprises injection of a trigger signal into a buffer delay chain for fine time measurement. The pulse position is captured with the next clock edge. The clock is also counted as a measure of the coarse time. Mismatches of the individual buffer delay elements cause a non-linearity of the fine time measurement. Furthermore the non-continuos operation of the delay chain causes thermal changes and corresponding delay drift. 
         [0034]    Another time-to-digital conversion comprises starting of an analog ramp by a trigger. The next clock edge stops the ramp and the reached ramp level is used as a measure for the fine time. The clock is also counted as a measure for the coarse time, wherein the trigger captures the state of the corresponding coarse time counter. The linearity of the analog ramp signal limits the linearity of the fine time conversion. 
         [0035]      FIG. 3  shows an embodiment of the present invention. The time-to-digital converter  110  comprises a ring oscillator  124  having an inverter  128  and n delay elements  126 . 1 ,  126 . 2 , . . . ,  126 .x, . . .  126 .N each of which having an individual delay time τ 1 , τ 2 , . . . τ N . The input of the middle delay element  126 .X is connected to the input of a first coarse time counter  112 . 1 , and the output of the last delay element  126 .N is connected to the input of a second coarse time counter  112 . 2 . The outputs of all delay elements  126 . 1 ,  126 . 2 , . . . ,  126 .x, . . .  126 .N are individually connected to corresponding inputs of a register  130 . The outputs of the first and second coarse time counter  112 . 1 ,  112 . 2  are connected to corresponding inputs of the register  130 . 
         [0036]    The input  136  of the register  130  is connected to the output of a first switch or selection unit  150  for selecting or switching between a conversion mode and a calibration mode of the converter  110  according to a selection signal on input  152 . The input  136  may be a clock entry of the register  130 . In the calibration mode trigger signals  154  having statistically equally distributed variable positions relative to the pulse forwarded in ring oscillator  124  are switched to the input  136  of the register  130 . The trigger signals  154  are provided by a trigger signal source  156  on the basis of a trigger source clock  158 . In the conversion mode the time signal  160  comprising the edge defining the time to be converted is switched to the input  136  of the register  130 . 
         [0037]    Coarse time is measured by counting the ring oscillator cycles or periods. Contrary to the converter  10  in  FIG. 1  no reference clock is counted for coarse time measurement. A rising and/or falling edge in the time signal  160  triggers the register  130  to capture the complete status of the ring oscillator  124  as well as the status of first and second coarse time counter  112 . 1 ,  112 . 2 . The captured pulse position within the ring oscillator  124  is a measure for the fine time measurement of the position of the corresponding edge in the time signal  160 . 
         [0038]    The register  130  provides output signals corresponding to the status of the delay elements  126 . 1 ,  126 . 2 ,  126 .N to a pulse position logic  138 . Furthermore the register  130  provides output signals corresponding to the status of the first and second coarse time counter  112 . 1 ,  112 . 2  to a second switch  162 , which is controlled by the pulse position logic unit  138 . If the pulse position logic unit  138  detects that the pulse is close to the end of the ring oscillator, e.g. near or at the position of the last delay element  126 .N, then the captured status of first coarse counter  112 . 1  is used for coarse time measurement, otherwise the captured status of second coarse counter  112 . 2  is used for coarse time measurement. This avoids inconsistent transitioning coarse counter status. The fine time is measured using the captured status of the ring oscillator  124  and fine and coarse time measurements are combined. Using the ring oscillator  124  for fine as well as for coarse time measurement overcomes the need to count a clock and ensures monotonicity. The pulse position logic unit  138  and the following logic can be realized in hardware or software, or in a combination of hard- and software. 
         [0039]    The embodiment in  FIG. 3  further comprises a method and the structure for calibration of the ring oscillator  124 . The basic idea is to randomly capture the status of the ring oscillator  124 , e.g. the status of all delay elements  126 . 1 ,  126 . 2 ,  126 .N of the ring oscillator  124 . The occurring pulse positions are dependent on the individual delay of the delay elements  126 . 1 ,  126 . 2 ,  126 .N, e.g. it is possible to determine the individual delay of each delay elements  126 . 1 ,  126 . 2 ,  126 .N on the basis of the pattern, e.g. of a histogram, of the distribution of pulse positions. 
         [0040]    In the calibration mode the first switch unit  152  switches trigger signals  154  to the input  136  of register  130 . The pulse positions are determined for each of a large number of e.g. M trigger signals  154 . A histogram is created and corrections values for each pulse position is calculated and stored in a fine time correction table  164 . 
         [0041]    In the conversion mode the time signal  160  comprising the edge defining the time to be converted is switched to the input  136  of the register  130 . The pulse position within the ring oscillator  124  is captured and forwarded to the pulse position logic unit  138  which look-up in the fine time correction table  164  for fine time correction resulting in exact fine time measurement. Fine time value F and coarse time value C are combined by combination unit  166  at the output of which the converted time as a digital signal  168  is provided. This method allows for non-invasive calibration, i.e. the ring oscillator  124  is neither interrupted for calibration nor anything else is changed in the structure of the converter  110 . No relevant hardware overhead is needed for the calibration, in particular no time reference. The trigger signal  154  can be random or deterministic or even periodic, e.g. a stable clock. 
         [0042]      FIG. 4  shows the calculation of correction values to be stored in the correction table  164 , wherein N is the number of stages in the ring oscillator  124 , M is the number of trigger signals  154  during calibration, wherein M&gt;&gt;N, p m  is the pulse position for each of M triggers, h n  represents the histogram, e.g. the occurrences of pulse position p m  is equal to n, and F k  represents the content of the correction table  164 , e.g. corrected fine time values for pulse position k, normalized to complete ring delay being equal to 1. 
         [0043]      FIG. 5  shows the calibration of the total ring delay. The first switch unit  152  selects trigger signal  154  as input for the register  130 . Two trigger events are generated at times T 1  and T 2 , separated by exactly L periods of a stable and known clock  158 . The values C 1  and C 2  of the first and second coarse time converter units  112 . 1 ,  112 . 2  are recorded as well as pulse positions p 1  and p 2 . As a variation the first and last trigger of calibration can be used. Fine delay calibration can be ignored, F(p)=p/N, using L being large enough. Fine time measurement can be ignored, t=t R ×C, using L being large enough. 
         [0044]    The conversion is monotonous at ring cycle boundaries and only one single path to capture the status of the ring oscillator  124  simplifies calibration. The frequency drift can be reduced due to the free-running ring oscillator  124 . The remaining frequency drift of the ring oscillator  124  can easily be corrected. The calibration is accurate because the operation of the ring oscillator  124  is not changed between calibration mode and conversion mode. 
         [0045]    The embodiment described above provide perfect boundary between coarse and fine delay and the monotonicity given e.g. by the ring oscillator or a single delay chain enables histogram calibration resulting in a very linear conversion. If in an embodiment the ring oscillator is free running, its frequency is not fixed and thus the absolute time cannot be measured directly. In a further embodiment at least one open (no closed loop) chain of delay elements is used at least for fine time conversion. 
         [0046]      FIG. 6  shows a further embodiment of a time-to-digital converter  210 . A control unit  270  starts the conversion in response to an arming ARM signal  272 . The control unit  270  outputs a reference or register RCLK clock  274  to a coarse counter  212  operated for example with a frequency of 2 GHz. Due to a register load RL signal  276  outputted by the control unit  270  to a coarse register  278  the status of the coarse counter  212  is captured by the coarse register  278 . The reference RCLK clock  274  corresponds to the clock CLK signal  216  provided to the control unit  270 . Until a rising edge of a trigger TRG signal  260  representing the time signal to be converted the coarse counter  212  counts by one at every rising edge of the reference clock RCLK signal  274 . 
         [0047]    The control unit  270  forwards the clock CLK signal  216  as delay line DCLK clock  280  injecting each pulse of the delay line DCLK clock  280  in a second chain of delay elements of Vernier delay line unit  282 . The delay elements of that second chain having in general a larger delay time than the delay elements of a first chain of the Vernier delay line unit  282 , i.e. T 1 &gt;τ 1  (see  FIG. 7 ). A pulse DD signal  281  is injected in the first chain comprising a measuring edge in response to the trigger signal  260  forwarded by the control unit  270 . Following said measuring edge the DD signal  281  comprises at least one further edge, advantageously at least two further edges, defining a calibration pulse of defined length. In an embodiment the calibration pulse follows said measuring edge as soon as possible to have the same thermal and other conditions for the measuring edge and for the calibration pulse. In an embodiment the time between the measuring edge and the calibration pulse is between one and two clocks. In an embodiment the Vernier delay line unit  282  comprises about 700 stages or groups of delay elements with a difference of 1 ps. 
         [0048]    For each stage or group of delay elements of the first and second delay line the Vernier delay line unit  282  comprises a shift register comprising two D flip-flops, e.g. a first and second D flip-flop. All outputs of the first D flip-flops of all stages of the Vernier delay line unit  282  representing a second B output  286  of the Vernier delay line unit  282 . Correspondingly all outputs of all second D flip-flops forming a first A output  284  of the Vernier delay line unit  282 . 
         [0049]    The first output  284  is connected to a pulse position unit  288  and the second output  286  is connected to a period stages unit  290 . The outputs of the pulse position unit  288  and the period stages unit  290  are connected to a correction unit  292  taking into account any deviation between a first status of the chain of delay elements being expected in response to a calibration pulse and an actual status of said chain of delay elements in response to said calibration pulse when determining the fine time. The output  294  of the correction unit  292  representing fine time TF measurement as well as the output  296  of a coarse register  278  representing coarse time TC are connected to a combination unit  266 . The output  268  of the combination unit  266  provides the time T to be converted as a digital signal. 
         [0050]    As an alternative or in addition to the absolute time or period calibration described above for the embodiment with the Vernier delay line unit  282  a histogram calibration can be applied similar or identical as described above for the embodiment with the ring oscillator  124  (see  FIG. 3 ). A calibration trigger unit  267  provides trigger TC signals  269  to the control unit  270  such that the pulse positions in time have equal probability. 
         [0051]      FIG. 7  shows one possible embodiment of the Vernier delay line unit  282  shown in  FIG. 6 . A first delay line comprising N- 1  delay elements  226 . 1 ,  226 . 2 , . . .  226 .N- 1  having a smaller delay time τ 1 , τ □ , . . . . τ N-1  than a second delay line comprising N delay elements  227 . 0 ,  227 . 1 ,  227 . 2 , . . .  227 .N- 1  having delay time □ 1 , □ □ , . . . □ N-1 . The delay line clock DCLK signal  280  is connected to a leading delay element  227 . 0  of the second delay line which—in the shown embodiment only—has no counterpart in the first delay line. Each subsequent delay element  227 . 1 ,  227 . 2 , . . .  227 .N- 1  of the second delay line has a counterpart in the first delay line thus forming N- 1  groups of delay elements  226 . 1 ,  227 . 1 - 226 . 2 ,  227 . 2 — . . . — 226 .N- 1 ,  227 .N- 1 . To each group of delay elements a shift register is related comprising a first D flip-flop  271  and a second D flip-flop  273 . Since all groups or stages of the Vernier delay line unit  282  are identical, in the following only the first group or stage formed by delay elements  226 . 1 ,  227 . 1  is described. 
         [0052]    The pulse DD signal  281  for the first delay line is connected to the first delay element  226 . 1  as well as to the D input of first D flip-flop  271 . The delay line DCLK clock  280  is connected to the leading delay element  227 . 0 , the output of which is connected to the first delay element  227 . 1  of the second delay line as well as to the clock input of first and second D flip-flops  271 ,  273 . The output of the first D flip-flop  271  is provided as a first bit B[ 0 ] of the second output  286  of Vernier delay line unit  282  as well as connected to the D input of second D flip-flop  273 . The output of the second D flip-flop  273  is provided as the first bit A[ 0 ] of the first output  284  of Vernier delay line unit  282 . In an embodiment the number of groups of pairs of delay elements  226 . 1 ,  227 . 1  and shift registers  271 ,  273  is 700 resulting in 700 bits A[ 0 ], . . . , A[ 699 ] of the first output  284  and 700 bits B[ 0 ], . . . , B[ 699 ] of the second output  286 . 
         [0053]      FIG. 8  shows a timing diagram for an embodiment of the converter  210  of  FIG. 6 . In the upper line the clock CLK signal  216  is shown which can be a stable reference clock. The arming ARM signal  272  enables the conversion. The delay line DCLK clock  280  may simply correspond to the clock signal  216 . The coarse counter  212  counts every rising edge of the reference RCLK clock  274  until a rising edge of the trigger TRG signal  260  occurs. The counted number, e.g. “2”, is loaded as RD signal from the coarse counter  212  into the register  278  and can be provided to the combination unit  266  as coarse time signal  296 . 
         [0054]    In an embodiment the time to be converted into a digital signal is the time difference t 1  between the rising edge of the trigger TRG signal  260  and a preceding rising edge of the delay line clock DCLK signal  280 . The time to be converted can also be a time interval defined by t 1  or comprising t 1 . The corresponding information is first available at a second B output  286  of Vernier delay line unit  282 . The rising edge of the trigger TRG signal  260  is adopted by pulse DD signal  281 . Following the rising edge of pulse DD signal  281  injected into the first delay line of Vernier delay line unit  282  after a predetermined time a calibration pulse of known position and/or known duration t 3 -t 2  in time is injected in said chain of delay elements. A particular status of the chain of delay elements is expected in response to said calibration pulse. The actual status of said chain of delay elements in response to said calibration pulse is captured due to a pulse of delay clock  280  and provided at the second B output  286  of the Vernier delay line unit  282  and simultaneously the previous value of the second B output  286  corresponding to the time t 1  to be converted is shifted into the first A output  284  of the Vernier delay line unit  282 . 
         [0055]    Due to variations in the individual delay time τ 1 , τ 2 , . . . and T 1 , T 2 , . . . of the delay elements in the first and second delay chain, i.e. deviations of the actual delay times and the nominal delay times of the according individual delay elements, differences between the delays of the first and second delay lines can change sign and thus accumulated delay may be non-monotonous. Since histogram calibration necessitates monotonicity, the output of the Vernier delay line unit  282  has to be processed to ensure monotonicity. 
         [0056]    The pulse position unit  288  provides monotonicity by applying a rule, e.g. to indicate the position of first “1” or of last “0” in the first A output  284  of the Vernier delay line unit  282 . For example the Vernier delay line unit  282  provides 700 bits for the first A output  284 , i.e. as thermometer coded “000 . . . 01011111”. The rule implemented in the pulse position unit  288  is, for example, to indicate the position of the last “0”. In the above given example, the last “0” is on the 6 th  position counted from behind. For the 700&lt;2 10  bits of the first A output  284  the number N 1  at the output of the pulse position unit  288  is of 10 bit width. Accordingly the 6 th  position of the last “0” is indicated as “0000000110” in binary code at the output of pulse position unit  288 . Applying such a rule makes the output N 1  of pulse position unit  288  monotonous. 
         [0057]      FIG. 9  shows an embodiment for the correction unit  292  of the converter  210  shown in  FIG. 6 . The period stages unit  290  provides a signal N 32  representing the actual measurement of the calibration pulse, e.g. a measurement for the time t 3 -t 2  (see  FIG. 8 ), derived from the second B output  286  of the Vernier delay line unit  282 . A switch and/or difference forming unit  281  forwards the signal N 32  or a difference of the signal N 32  and a calibration signal Ncal to a period correction table  283 . In an embodiment the switch and/or difference forming unit  281  calculates the deviation or difference of a first status of said chain of delay elements being expected in response to said calibration pulse and an actual status of said chain of delay elements in response to said calibration pulse. The result may be forwarded as a 4 bit word to the period correction table  283 . 
         [0058]    In an embodiment the period correction table  283  assigns a correction value depending on the deviation or difference of expected and actual status in response to the calibration pulse. The correction value may be dependent on the expected and/or actual length of the calibration pulse. The correction value may be forwarded as a 6 bit word to a weighting unit  285 . 
         [0059]    The output N 1  of the pulse position unit  288 , being for example a 10 bit word, is connected to a stage correction table  287 , determining a rough correction value, being for example a 10 bit word, depending on the output N 1  of the pulse position unit  288 . The rough correction value represents a first correction value and is connected to the weighing unit  285  as well as to a adder unit  289 . The weighting unit  285  outputs a second correction value to the adder unit  289 , e.g. by weighting the first correction value depending on the correction value assigned by the period correction table  283 , e.g. by calculating a second correction value as the result of a multiplication of the first correction value with the correction value assigned by the period correction table  283 . At the output of the adder unit  289  the corrected fine time TF is provided for the combination unit  266 . In an embodiment look-up tables are stored in period correction table  283  and/or stage correction table  287 . The period correction table  283  may represent the correction resulting from absolute period calibration using the calibration pulse of length t 3 -t 2  as described above. The stage correction table  287  may represent the correction resulting from histogram calibration. Thus the content of the stage correction table  287  can be calculated correspondingly as described for  FIG. 4 . For randomly capturing the state of the Vernier delay line unit  282  a suitable calibration trigger signal source  267  is used, e.g. a ring oscillator being statistically uncorrelated to the coarse frequency, i.e. to the pulse position. Other clock sources might be used as well. In an embodiment a high accuracy low-jitter clock is not needed, instead the clock may comprises jitter since any jitter improves randomness. The pulse position p m  for each of M trigger signals is determined and a histogram is created and a fine time correction table is calculated due to the fact, that the pulse position occurrence is proportional to stage delay. During conversion, the pulse position p is determined and a correction value is selected from the look-up table. This provides non-invasive calibration, without interrupting the normal operation, and only few or no additional hardware is necessitated and/or no time reference, but only a stable frequency. 
         [0060]    While this invention has been described in terms of several embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations and equivalents as fall within the true spirit and scope of the present invention.