Abstract:
In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

Description:
[0001]    This application claims the benefit of the filing date of U.S. Provisional Application No. 61/791,328 filed on Mar. 15, 2013, the teachings of which are incorporated herein by reference in their entirety. 
     
    
     BACKGROUND 
       [0002]    1. Field 
         [0003]    The current disclosure relates to digital power amplifiers, and more specifically, but not exclusively, to digital power amplifiers for radio-frequency transmission systems. 
         [0004]    2. Description of the Related Art 
         [0005]    Radio-frequency (RF) transmitters communicate with RF receivers using radio-frequency electromagnetic signals. A typical RF transmitter includes a processing module and an antenna. A digital processing module uses relatively low-power digital signals. The signals transmitted by the antenna, however, need to be relatively high-powered and analog in order to be picked up by antennas in the RF receivers. Consequently, a power amplifier is typically used by RF transmitters on outgoing signals between the processing module and the antenna. 
         [0006]    Conventional power amplifiers that use analog components provide relatively low power efficiencies. Digital power amplifiers, such as so-called class-D and class-S amplifiers, can be significantly more efficient than analog power amplifiers. Increasing the power-use efficiency may reduce initial costs, operating costs, and maintenance costs of an RF transmitter. The design and operation of various analog and digital power amplifiers are described in Stephen Ralph&#39;s “Class-S Power Amplifier For Use In Mobile Phone Basestations,” National University of Ireland Maynooth, 2007, incorporated herein by reference in its entirety. 
         [0007]      FIG. 1  shows a simplified block diagram of conventional power amplification system  100  of an RF transmitter with a digital processing module. System  100  comprises digital signal source  101  which provides multi-bit, relatively low-frequency, digital baseband (BB) signal  101   a  to bit-stream generator  102 . Bit-stream generator  102  may be, for example, a pulse-width modulator or a sigma-delta modulator. Bit-stream generator  102  generates a digital, low resolution (e.g., 1-bit), radio-frequency switching signal, or bit stream,  102   a , which is derived from digital signal  101   a  based on a transfer function implemented by bit-stream generator  102 . 
         [0008]    Switching signal  102   a  is at a higher frequency but a lower resolution than digital signal  101   a , because the transformation of signal  101   a  into signal  102   a  introduces quantization noise into signal  102   a . The transfer function of bit-stream generator  102  may be used for spectral shaping and may be set so that the location, on a frequency scale, of the quantization noise is moved away from a frequency band of interest to an outlying frequency band. Bit-stream generator  102  performs frequency up-conversion from a baseband frequency to a radio frequency and transforms high-resolution digital signal  101   a  into low-resolution digital signal  102   a  while maintaining a high signal-to-noise ratio (SNR) in the frequency band of interest. 
         [0009]    Switching power amplifier  103  acts as a high-fidelity RF digital-to-analog converter that outputs amplified RF signal  103   a  based on signal  102   a . Signal  103   a  is then provided to bandpass filter  104 , which substantially passes through the frequency band of interest while substantially blocking other frequencies, thereby substantially filtering out the quantization error introduced by bit-stream generator  102 . Bandpass filter  104  outputs analog signal  104   a , which is provided to antenna  105  for transmission. Note that system  100  uses oversampling, where the sampling frequency of bit-stream signal  102   a  is several times higher than the desired bandwidth of the analog RF output signal  104   a.    
         [0010]      FIG. 2  shows a circuit diagram of one conventional implementation of switching power amplifier  103  of  FIG. 1 , which functions to provide output signal  103   a , an amplified analog version of its digital input signal  102   a . Amplifier  103  comprises n-channel field-effect transistor (FET)  201  and p-channel FET  202 , both of whose gates are controlled by input signal  102   a . FETs  201  and  202  may be power transistors using, for example, GaN, LDMOS, or GaAs technologies. The drain terminal of FET  201  is connected to voltage source  203 . The drain terminal of FET  202  is connected to common (i.e., ground) voltage  204 . The source terminals of FETs  201  and  202  are connected together to generate output signal  103   a . Protection diode  205  is connected between the drain and source of FET  201 , while protection diode  206  is connected between the drain and source of FET  202 . Output signal  103   a  may go through a broad-band RF band-pass filter (not shown) before being output by amplifier  103 . A broad-band RF band-pass filter may be implemented as an RF tank circuit, also known as an LC circuit. 
         [0011]      FIG. 3  shows a simplified block diagram of one implementation of bit-stream generator  102  of  FIG. 1 . Bit-stream generator  102  of  FIG. 3  is implemented as a sigma-delta modulator and comprises upsampler  301 , loop filter  302 , and quantizer  303 . A sigma-delta modulator, as its name suggests, performs a summation of differences. Upsampler  301  receives input digital signal  101   a  at sampling frequency Fs, increases the sampling frequency by a factor P, and outputs digital signal  301   a  at sampling frequency P*Fs. Signal  301   a  is one of the inputs to loop filter  302  with the other being signal  102   a , the 1-bit output of bit-stream generator  102 . Loop filter  302  comprises a comparator and an integrator (not shown) and performs a summing of differences between input  301   a  and input  102   a  and outputs the result as signal  302   a  to quantizer  303 . Quantizer  303  outputs a high or low value—corresponding to a positive or negative value, respectively—depending on whether  302   a  is above or below a set threshold. 1-bit output signal  102   a  has a sampling frequency of P*Fs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    Other aspects, features, and advantages of the disclosure will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
           [0013]      FIG. 1  shows a simplified block diagram of a power amplification segment of a conventional transmitter. 
           [0014]      FIG. 2  shows a circuit diagram of one implementation of the switching power amplifier of  FIG. 1 . 
           [0015]      FIG. 3  shows a simplified block diagram of one implementation of the bit-stream generator of  FIG. 1 . 
           [0016]      FIG. 4  shows a simplified block diagram of a power amplification segment of a transmitter in accordance with one embodiment of the disclosure. 
           [0017]      FIG. 5  shows a simplified block diagram of an exemplary implementation of the interleaved-bit-stream generator of  FIG. 4 . 
           [0018]      FIG. 6  shows a block diagram of an exemplary implementation of a Farrow structure. 
           [0019]      FIG. 7  shows exemplary source code for simulating the generation of a band-pass bit-stream signal. 
           [0020]      FIGS. 8(A)-8(G)  are a series of frequency graphs illustrating the exemplary generation by the serializer block of  FIG. 5  of a band-pass bit-stream output signal of a single tone. 
           [0021]      FIG. 9  shows an alternative implementation of the interleaved-bit-stream generator of  FIG. 4 . 
           [0022]      FIGS. 10(A)-10(B)  help illustrate how the FD filter pairs and corresponding adders of  FIG. 9  generate their corresponding outputs. 
           [0023]      FIGS. 11(A)-11(G)  are a series of related frequency graphs illustrating the processing of signals using substantially the same arrangement as used in  FIGS. 8(A)-8(G) , but for narrowband (and band-limited) signals. 
           [0024]      FIGS. 12(A)-12(D)  show four variations for the spectral components for the signal of  FIG. 11(G) . 
           [0025]      FIGS. 13(A)-13(C)  show time and corresponding spectral plots of simulations using single tones in generating low-pass, high-pass, and band-pass signals. 
           [0026]      FIGS. 14(A)-14(B)  show time and corresponding spectral plots for exemplary scenarios of  FIGS. 11(A)-11(G)  using dual tones in generating low-pass and high-pass signals. 
           [0027]      FIGS. 15(A)-15(D)  show time and corresponding spectral plots for exemplary LSB/USB scenarios using dual tones in generating band-pass signals. 
           [0028]      FIGS. 16(A)-16(D)  show spectral plots for exemplary scenarios of  FIGS. 8(A)-8(G) , incorporating bit-stream generators, and using dual-tone bit-streams in generating various signals. 
       
    
    
     DETAILED DESCRIPTION 
       [0029]    Cellular telecommunication systems include base stations that include subsystems similar to power amplification system  100  of  FIG. 1 . Cellular telecommunication systems typically communicate at radio frequencies of approximately 2 GHz. In order for a transmitter using a bit-stream generator to output a radio signal at 2 GHz with satisfactory noise characteristics, the frequency of the bit-stream provided to the switching power amplifier should be at least 8 GHz. Conventional bit-stream generators are not able to operate and provide outputs at such a high frequency. 
         [0030]      FIG. 4  shows a simplified block diagram of power amplification system  400  of a transmitter in accordance with one embodiment of the disclosure. System  400  is similar to system  100  of  FIG. 1 , but with interleaved-bit-stream generator  402  replacing bit-stream generator  102  of  FIG. 1 . Note that digital signal source  401 , switching power amplifier  403 , bandpass filter  404 , and antenna  405  may be substantially similar to the corresponding elements of power amplification system  100  of  FIG. 1 . Interleaved-bit-stream generator  402  generates digital RF switching signal  402   a , which is used as the input to switching power amplifier  403 . Interleaved-bit-stream generator  402  uses a plurality of fractional-delay filters operating at a relatively low frequency and connected to an interleaving serializer to generate a relatively high-frequency output. Switching power amplifier  403  outputs amplified RF signal  403   a  to bandpass filter  404 , which, in turn, outputs analog RF output signal  404   a  to antenna  405 . 
         [0031]      FIG. 5  shows a simplified block diagram of an example implementation of interleaved-bit-stream generator  402  of  FIG. 4 . Interleaved-bit-stream generator  402  of  FIG. 5  is an 8-path bit-stream generator. First, n-bit digital signal  401   a , where n is an integer greater than 1, is applied to an array of eight parallel fractional delay (FD) filters  501 ( 1 )- 501 ( 8 ). In any particular processing cycle, each of FD filters  501 ( 1 )- 501 ( 8 ) receives the same sample. Note that digital signal  401   a  is also referred to herein as u. 
         [0032]    FD filters  501 ( 1 )- 501 ( 8 ) are substantially identical to each other in structure, but each one introduces an independent fractional delay to the signal. Namely, FD filter  501 ( i ) introduces into its corresponding signal a fractional delay represented by Φ i . The fractional delay of each FD filter  501 ( i ) should be set so as to account for the total number of signals being interleaved, account for the desired signal manipulation, and compensate for any delays introduced by serializer block  503 , which interleaves the signals. The delays for the FD filters  501  of one embodiment of interleaved-bit-stream generator  402  are discussed in detail below. Note that varying the fractional delay values of any of FD filters  501  will vary the signals output by FD filters  501  and, consequently, the resulting interleaved output of interleaved-bit-stream generator  402 , which is digital RF switching signal  402   a.    
         [0033]    Each FD filter  501  may be implemented using a Farrow structure, which is a tunable fractional delay filter used to estimate the values of an input signal between existing discrete-time samples. In other words, FD filter  501  is an interpolation filter that can be used to compute new sample values at arbitrary points. A Farrow structure may be implemented as a polynomial-based digital filter. Note that each FD filter  501  may operate at the base-band rate of digital signal source  401  of  FIG. 4 , which may be, for example, 128 MHz, rather than at a radio-frequency rate such as, for example, 1 GHz. Operating each FD filter  501  at the lower rate would reduce power consumption of interleaved-bit-stream generator  402 . Note that reducing power consumption would be particularly useful for power amplification systems that are powered by batteries and/or solar panels, since those power sources are generally not as robust as connections to the electric grid. 
         [0034]      FIG. 6  shows a block diagram of module  600 , which is an example implementation of a Farrow structure. Module  600  comprises L FIR (finite impulse response) subfilters  601 , where L is a positive integer and each subfilter  601 ( q ) has a transfer function H q (z), where q is an integer between 0 and L−1, inclusive. All L FIR subfilters  601  have the same input. The output of subfilter  601 (L−1), whose transfer function is H L-1 (z), is scaled by a factor α—an adjustable gain parameter—and the result added to the output of subfilter  601 (L−2), whose transfer function is H L-2 (z). That sum is then scaled by the factor α and the result added to the output of subfilter  601 (L−3) (not shown), whose transfer function is H L-3 (z). This pattern repeats until the summation of the a-scaled penultimate sum with the output of subfilter  601 ( 0 ), whose transfer function is H 0 (z). As would be appreciated by a person of skill in the art, there are known systems and methods for generating a Farrow structure having a particular desired fractional delay. 
         [0035]    Referring again to  FIG. 5 , the output u i  of each FD filter  501 ( i ) is provided to a corresponding bit-stream generator  502 ( i ). Bit-stream generators  502 ( 1 )- 502 ( 8 ) form an array of bit-stream generators corresponding to FD filter array  501 ( 1 )- 501 ( 8 ). Bit-stream generators  502 ( 1 )- 502 ( 8 ) are substantially identical to each other in structure and each may be implemented similarly to bit-stream generator  102  of  FIG. 3 . Note that other implementations of a bit-stream generator may be used instead. Each bit-stream generator  502 ( i ) performs the up-sampling and quantizing functions described above and outputs a corresponding, relatively high-frequency, bit-stream x i , which is provided to 8-to-1 serializer block  503 . The bit-streams x 1 -x 8  are at a first frequency such as, for example, 1 GHz. 
         [0036]    Serializer block  503  comprises a funneling cascade of serializer modules  504 ( 1 )-( 7 ), wherein each serializer module  504  is a 2-to-1 serializer that may be implemented as a switch. Each serializer module  504  takes two bit-stream inputs x A  and x B , where A and B represent signal identifiers, each of which has a first sampling frequency. Serializer module  504  then outputs a combined bit-stream signal x AB , whose sampling frequency is double the first sampling frequency. The interleaving is performed on a bit-by-bit basis, wherein serializer  504  goes back and forth between outputting a bit from the first input bit-stream and a bit from the second input bit-stream. 
         [0037]    The funneling cascade of serializer block  503  may be viewed as comprising three stages. In the first stage of the cascade, (a) bit-streams x 1  and x 2  are combined to generate bit-stream x 12 , (b) bit-streams x 3  and x 4  are combined to generate bit-stream x 34 , (c) bit-streams x 5  and x 6  are combined to generate bit-stream x 56 , and (d) bit-streams x 7  and x 8  are combined to generate bit-stream x 78 —by four respective serializer modules  504 ( 1 )-( 4 ) operating at a second frequency such as, for example, 2 GHz, that is twice the first exemplary frequency of 1 GHz. 
         [0038]    In the second stage of the cascade, (a) bit-streams x 12  and x 34  are combined to generate bit-stream x 1234 , and (b) bit-streams x 56  and x 78  are combined to generate bit-stream x 5678 —by two respective serializer modules  504 ( 5 ) and  504 ( 6 ) operating at a third frequency such as, for example, 4 GHz, that is twice the second exemplary frequency. 
         [0039]    In the third stage of the cascade, bit-streams x 1234  and x 5678  are combined to generate bit-stream x 12345678 —by one serializer module  504 ( 7 ) operating at a fourth frequency such as, for example, 8 GHz, that is twice the third exemplary frequency. Bit-stream x 12345678  is used as output signal  402   a  of interleaved-bit-stream generator  402 . The serializer modules  504  of the various cascade levels (1) may be structurally identical to the serial modules  504  of the other cascade levels, but operating at different frequencies or (2) may be structurally different from serializer modules  504  of other cascade levels to allow for optimization of performance at particular operational frequencies. 
         [0040]    Note that alternative implementations of an 8-to-1 serializer may be used for serializer block  503 . Serializer block  503  outputs digital RF switching signal  402   a , which, as noted above, has a frequency eight times the frequency of the bit-streams output by bit-stream generators  502 . 
         [0041]      FIG. 7  shows exemplary MATLAB source code  700  for simulating the generation of band-pass bit-stream signals as shown in and described below in reference to, for example,  FIGS. 8(A)-8(G) . MATLAB is a registered trademark of MathWorks, Inc., of Natick, Mass. The source code shows particular coefficient values that may be used for corresponding modules of, for example, interleaved-bit-stream generator  402  of  FIG. 5 . The bit-stream generators are bypassed in this source code (in other words, x i =u i  for i=1 to 8), but the fractional delays are implemented. In other words, the u i  signals are obtained using the array of fractional delay filters shown in  FIG. 5 . Also implemented are the series of interleaving operations, resulting in the final output of signal x 12345678 . The time-domain signals are converted into frequency domain information using the fast Fourier transform (FFT) and plotted to create  FIGS. 13-16 , described further below. These simulations illustrate how the signals are up-converted via the interleaving process implemented by a series of serializer modules. 
         [0042]    Source code  700  simulates a two-tone signal—in other words, a signal having two distinct frequency components. If multiplier a2 is set to 0, then source code  700  would be a single-tone signal as represented in  FIGS. 8(A)-8(G) . Source code  700  presents the fractional delays of FD filter  501  as sums of constants. For example, Φ 1 , the delay of signal x 1 , applied by FD filter  501 ( 1 ), is ph1 — 1+ph12 — 1+ph1234 — 1, which equals 0+0+0, or 0. The delays applied by the other FD filter  501  are shown below, where f is the digital frequency and N is the number of samples in a sampling period of signal  401   a:    
         [0043]      501 ( 2 ): Φ 2 =4/4*π*f/N, 
         [0044]      501 ( 3 ): Φ 3 = 2/4*π*f/N+π, 
         [0045]      501 ( 4 ): Φ 4 =6/4*π*f/N+π, 
         [0046]      501 ( 5 ): Φ 5 =¼*π*f/N−π/2, 
         [0047]      501 ( 6 ): Φ 6 =5/4*π*f/N−π/2, 
         [0048]      501 ( 7 ): Φ 7 =3/4*π*f/N+π/2, and 
         [0049]      501 ( 8 ): Φ 8 =7/4*π*f/N+π/2. 
         [0000]    Note that source code  700  uses the terms N1, N2 (which equals 2*N1), and N4 (which equals 4*N1). For greater simplification, N has been used above instead of N1 and substituted into the formulas using N2 and N4. Note that alternative implementations may use different delays. In particular, alternative implantations may add or subtract different fractions of it in order to generate high-pass, low-pass, or band-pass interleaved signals within serializer block  503 . 
         [0050]    For example, as noted in source code  700 , one of the phase shift elements for signals x 5 -x 8 , indicated by the constant ph5678 — 1, may be either π*f/(4*N)+π/2—for high-side sampling—or π*f/(4*N)−π/2—for low-side sampling. The above-listed delays are intended for low-side sampling. In accordance with source code  700  and the above-described simplification, the applied delays for FD filters  501  for high-side sampling would be: 
         [0051]      501 ( 1 ): Φ 1 =0 
         [0052]      501 ( 2 ): Φ 2 =4/4*π*f/N, 
         [0053]      501 ( 3 ): Φ 3 = 2/4*π*f/N+π, 
         [0054]      501 ( 4 ): Φ 4 =6/4*π*f/N+π, 
         [0055]      501 ( 5 ): Φ 5 =¼*π*f/N+π/2, 
         [0056]      501 ( 6 ): Φ 6 =5/4*π*f/N+π/2, 
         [0057]      501 ( 7 ): Φ 7 =¾*π*f/N+3π/2, and 
         [0058]      501 ( 8 ): Φ 8 =7/4*π*f/N+3π/2 
         [0000]    As noted above, for greater simplification, N has been used above instead of N1 and substituted into the formulas using N2 and N4. 
         [0059]    Below is an analysis of simulated exemplary operation of interleaved-bit-stream generator  402 . Note that since the bit-stream generators  502 ( 1 )- 502 ( 8 ) act as high-fidelity radio-frequency digital modulators at the frequency band of interest, converting a higher-resolution multi-bit (e.g., 8-bit) signal into a lower-resolution fewer-bit (e.g., 1-bit) signal, the information in the frequency band of interest represented in each input signal u i  is very close in detail to the information in the frequency band of interest represented in its corresponding output signal x i , even though their respective sampling frequencies may be far apart. Consequently, the symbols u i  and x i  may be used interchangeably in the below analysis of interleaving of signals in the frequency band of interest. 
         [0060]      FIG. 8(A)  shows the frequency spectrum for exemplary bit-stream signal x 1 , having a nominal frequency f and sampled at frequency Fs1, showing frequency components at close to zero frequency, or DC (i.e., direct current, which has a frequency of zero), and close to the exemplary signal&#39;s sampling frequency of Fs1. Note that single-tone signal x 1  shows two frequency components because of the aliasing caused by sampling, as would be appreciated by a person of ordinary skill in the art. Also note that frequency components are sometimes referred to as spectral components. 
         [0061]      FIGS. 8(A)-8(G)  are a series of simplified simulated frequency graphs illustrating the exemplary generation by serializer block  503  of  FIG. 5  of a band-pass bit-stream output signal x 12345678  that represents a single tone near a desired output frequency of Fs8/4. Note that the sampling frequencies of the signals illustrated in  FIGS. 8(A)-8(G)  are Fs1, Fs2, Fs4, and Fs8, where Fs2 is twice Fs1, Fs4 is four times Fs1, and Fs8 is eight times Fs1. Output bit-stream signal x 12345678  is generated by interleaving eight input single-tone bit-stream signals, namely, x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , and x 8 , each sampled at sampling frequency Fs1 of, for example, 1 GHz. 
         [0062]    Note that in actual operation, the truncation of least-significant bits in various arithmetic operations performed will result in some truncation error, which is similar to quantization error. As would be appreciated by a person of ordinary skill in the art, the location along the frequency spectrum of the truncation error may be shaped using mathematical operations so as to have the truncation error located at frequencies away from the frequency band of interest so that the truncation errors may be filtered out by an appropriate pass filter (e.g., a low-pass, high-pass, or band-pass filter). Note that any shaped truncation error components of the bit-stream signals in  FIGS. 8(A)-8(G)  are not shown. 
         [0063]    Bit-stream signal x 1  of  FIG. 8(A)  is an exemplary output of bit-stream generator  502 ( 1 ) of  FIG. 5 , whose input is signal u 1 . As noted above, the frequency spectrum for signal x 1  includes spectral components at close to 0 Hz (or DC) and aliased components close to the signal&#39;s sampling frequency of Fs1. Bit-stream signal x 2  of  FIG. 8(B)  is an exemplary output of bit-stream generator  502 ( 2 ), whose input is signal u 2 . Exemplary signal x 2  also shows spectral components at close to DC and alias components close to the signal&#39;s sampling frequency of Fs1. Note that the input signals u 1  and u 2  of  FIG. 5  were generated from the input signal  401   a  by passing input signal  401   a  through fractional delay filters  501 ( 1 ) and  501 ( 2 ), respectively, with corresponding fractional delays Φ 1  and Φ 2 , respectively. 
         [0064]      FIG. 8(C)  shows the frequency spectrum of bit-stream signal x 12 , sampled at sampling frequency Fs2 (e.g., 2 GHz) and which was obtained by interleaving x 1  and x 2 , each sampled at sampling frequency Fs1 (e.g., 1 GHz). As can be seen, the interleaved signal x 12  has four frequency-spectrum components, one of which, at the lowest frequency, is considered the actual signal and the other three are considered aliases in the 0—Fs2 frequency range. The spectral component close to 0 Hz (or DC) is referred to as the low-pass component. The alias of the low-pass component resulting from sampling appears close to Fs2. The spectral component just below Fs2/2 is called a high-pass component, and its alias due to sampling is just above Fs2/2. In the particular case of  FIG. 8(A)  and  FIG. 8(B) , x 1  and x 2  are low-pass bit-streams. Also, the respective fractional delays, Φ 1  and Φ 2 , for x 1  and x 2  are selected so that x 12  becomes a low-pass bit-stream where the high-pass component and its image in x 12  cancel out because they are generated to have opposite phases. This is done by setting the appropriate parameters for the corresponding fractional delay filters, as described elsewhere herein. Note that the canceled-out segments are shown as grayed out in  FIG. 8(C)  and subsequent figures. Note that Φ 1  and Φ 2  can, instead, be selected so that signal x 12  would, instead, become a high-pass bit stream where the low-pass component and its image in signal x 12  would cancel out. 
         [0065]      FIG. 8(C)  illustrates the use of the method described elsewhere herein for constructing signal x 12  as a low-pass bit-stream from the two low-pass bit-streams x 1  and x 2 . 
         [0066]      FIG. 8(D)  shows, similarly to  FIG. 8(C) , the result of the use of the method described elsewhere herein to construct signal x 34  as a low-pass bit-stream from bit-streams x 3  and x 4 . 
         [0067]      FIG. 8(E)  shows the subsequent generation of signal x 1234 , which is constructed to be a high-pass bit-stream generated from the two low-pass bit-streams x 12  and x 34 . The grayed out spectral components represent the canceled aliasing components. Note that the sampling frequency used for signal x 1234  is Fs4 (e.g., 4 GHz). 
         [0068]      FIG. 8(F)  shows, similarly to  FIG. 8(E) , the result of the use of the elsewhere-described method to construct signal x 5678  as a high-pass bit-stream generated from bit-streams x 56  and x 78 . Signal x 56  (not shown) was generated from single-tone signals x 5  and x 6  (not shown) in a manner similar to the generation of signal x 12 , as described above. Similarly, signal x 78  (not shown) was generated from single-tone signals x 7  and x 8  (not shown) in a manner similar to the generation of signal x 12 , as described above. 
         [0069]      FIG. 8(G)  shows the result of the use of the elsewhere-described method to construct signal x 12345678  as a lower side band (LSB) band-pass sine wave, having a spectral component by Fs8/4 (e.g., 2 GHz), as desired. Note that the sampling frequency used for signal x 12345678  is Fs8 (e.g., 8 GHz). 
         [0070]    The following is an explanation of the setting of the fractional delays implemented by FD filters  501  in  FIG. 5  and enumerated above. These fractional delays are applied to input signal  401   a  in order to obtain the spectral plots shown in  FIG. 8 . 
         [0071]    An analog sine-wave x can be described as 
         [0000]        x=A *sin(2 π*f*t +Φ)
 
         [0000]    where A is constant coefficient, f is the frequency, t is the time, and Φ is a phase shift or delay. A digital sine-wave x can be described as 
         [0000]        x=A *sin(2*π*f/Fs*[1 :N ]+Φ)
 
         [0000]    where N is the number of samples and Fs is the sampling frequency (using standard Matlab syntax). Therefore, f/Fs is the normalized digital frequency and [1:N], which represents the set [1, 2, 3, . . . , N], represents the normalized digital time samples occurring during each sampling period Ts, which equals 1/Fs. 
         [0072]    If x 1  and x 2  are low-pass sine waves of frequency f sampled at Fs1, then x 12 , which is obtained by interleaving x 1  and x 2 , will be: (1) a low-pass sine wave (with high-pass components cancelled) if Φ 1 =0 and Φ 2 =f*π/Fs1 or (2) a high-pass sine wave (with low-pass components cancelled) if Φ 1 =0 and Φ 2 =f*π/Fs1+π. (Note that it is the relative phase difference between (Di and Φ 2  that matters, not the absolute phase values of Φ 1  and Φ 2 . 
         [0073]    Similarly, if x 3  and x 4  are low-pass sine waves of frequency f sampled at Fs1, then x 34 , which is obtained by interleaving x 3  and x 4 , will be: (1) a low-pass sine wave (with high-pass components cancelled) if Φ 3 =0 and Φ 4 =f*π/Fs1 or (2) a high-pass sine wave (with low-pass components cancelled) if Φ 1 =0 and Φ 2 =f*π/Fs1+π. 
         [0074]    If x 1  and x 2  are high-pass sine waves of frequency f sampled at Fs1, then x 12 , which is obtained by interleaving x 1  and x 2 , will be: (1) a lower side band (LSB) band-pass sine wave (with upper side band (USB) components cancelled) if Φ 1 =0 and Φ 2 =f*π/Fs1+π/2 or (2) or an upper side band (USB) band-pass sine wave (with LSB components cancelled) if Φ 1 =0 and Φ 2 =f*π/Fs1−π/2. As noted above, the fractional delays implemented by particular fractional delay filters may be modified in accordance with the above descriptions to obtain different desired outputs as signal x 12345678 . 
         [0075]      FIG. 9  shows interleaved-bit-stream generator  900 , which outputs digital RF switching signal  900   a  and is an alternative implementation of interleaved-bit-stream generator  402  of  FIG. 4 . Bit-stream generator  900  splits input signal  401   a  into sixteen signals provided to sixteen corresponding FD filters  901 ( 1 )-( 16 ). Fractional delay filters  901  are substantially similar to FD filters  501  of  FIG. 5 . The outputs of corresponding pairs of FD filters  901 (2i−1) and  901 (2i), where i=1 to 8—such as  901 ( 1 ) and  901 ( 2 )—are provided to corresponding adders  902 ( i ). The output of each adder  902 ( i ) is provided to corresponding bit-stream generator  502 ( i ), which, together with serializer block  503 , operates substantially the same as the corresponding elements of interleaved-bit-stream generator  402  of  FIG. 5 . Using the additional FD filters and adders allows for increased signal bandwidth, as explained below. 
         [0076]      FIGS. 10(A)-10(B)  help illustrate how the FD filter  901  pairs and corresponding adders  902  of FIG.  9 —such as FD filters  901 ( 1 ) and  901 ( 2 ) and adder  902 ( 1 )—generate their corresponding outputs—such as signal x 1 . Note that signals x 2 -x 8  are similarly generated. In interleaved-bit-stream generator  900 , signal  401   a , or u i  is input to, among others, fractional delay filters  901 ( 1 ) and  901 ( 2 ). The fractional delay implemented by fractional delay filter  901 ( 1 ) (e.g., Φ 1a ) is different from the fractional delay implemented by fractional delay filter  901 ( 2 ) (e.g., Φ 1b ). The outputs of FD filters  901 ( 1 ) and  901 ( 2 )—u 1LSB  and u 1USB , respectively—are added by adder  902 ( 1 ) to generate signal u 1  which is then provided to bit-stream generator  502 ( 1 ) to generate signal x 1 . 
         [0077]      FIG. 10(A)  is a frequency graph that shows—as upside-down U&#39;s—the spectral components—primary and aliased—of exemplary signal u 1LSB , which was generated to be a lower-side-band component signal.  FIG. 10(B)  shows—as upside-down V&#39;s—the spectral components of exemplary signal u 1USB , which was generated to be an upper-side-band component signal. After the interleaving of signal x 1  and similarly generated signals x 2 -x 8  by serializer block  503 , the resulting interleaved bandpass signal x 12345678  contains useful signal information on both sides of the target frequency, thereby effectively providing double the bandwidth of signals x 1 -x 8  of  FIGS. 8(A)-8(G) . This is further described below. 
         [0078]      FIGS. 11(A)-11(G)  are a series of related frequency graphs illustrating the processing of signals in interleaved-bit-stream generator  900  of  FIG. 9 . The signals in  FIGS. 11(A)-11(G)  are similar to the signals in  FIGS. 8(A)-8(G) , but are narrowband (and band-limited) signals, where the resultant signal x 12345678  is a band-pass signal constructed by interleaving signals x 1 , x 2 , x 3 , x 4 , x 5 , x 6 , x 7 , and x 8 . Note, however, that as described above in reference to signal x 1 , each signal x, is generated using two fractional delay filters  901 . Accordingly, the spectral components of each of signal x 1  in  FIG. 11(A)  and signal x 2  in  FIG. 11(B)  are represented by both an upside-down U—corresponding to the lower-side-band (LSB) component—and an upside-down V—corresponding to the upper-side-band component (USB). Note that the LSB and USB signal components in x 1  (and x 2 ) overlap in frequency but are discriminated by phases.  FIGS. 11(A)-11(G)  illustrate use of the above-described methods of selecting fractional delays and interleaving the signals x, to cancel aliases.  FIG. 11(G)  shows that the resultant signal x 12345678  has double the signal bandwidth of the individual input signals by placing the LSB and USB components side by side. 
         [0079]      FIGS. 12(A)-12(D)  show four variations for the spectral components around Fs8/4 for signal x 12345678  of  FIG. 11(G)  resulting from alternative implementations. The particular resultant variation depends on x 1LSB  and x 1USB , which depend on the particular delay settings of the corresponding fractional delay filters that output the signal.  FIG. 12(D)  shows the variation shown in  FIG. 11(G)  and described above.  FIG. 12(A)  shows another variation that provides double bandwidth by the frequency (Fs8)/4.  FIG. 12(B)  and  FIG. 12(C)  show variations where only the regular bandwidth is available and USB and LSB overlap in frequency, which may not be desirable. 
         [0080]      FIGS. 13(A)-13(C)  show time (on the left) and corresponding spectral plots (on the right) of simulations using input single tones x A  and x 13  in generating low-pass (FIG.  13 (A)), high-pass (FIG.  13 (B)), and band-pass ( FIG. 13(C) ) signals x AB , respectively, where A and B are signal identifiers. Note that (1) low-pass signals refers to signals whose frequencies are predominantly close to zero, (2) high-pass signals refers to signals whose frequencies are predominantly close to Fs/2, where Fs is the sampling frequency, and (3) band-pass signals refers to signals whose frequencies fall between low-pass and high-pass (e.g., close to Fs/4). 
         [0081]    Input tone x A  is illustrated in the top two graphs and input tone x 13  is illustrated in the middle two graphs of  FIGS. 13(A)-13(C) . The resultant signal x AB  is illustrated in the bottom two graphs of  FIGS. 13(A)-13(C) . Specifically,  FIG. 13(A)  illustrates the interleaving of input signals x 1  and x 2  to generate low-pass signal x 12 . Low-pass signal x 34  would be similarly generated.  FIG. 13(B)  illustrates the interleaving of input signals x 12  and x 34  to generate high-pass output signal x 1234 . High-pass signal x 5678  would be similarly generated.  FIG. 13(C)  illustrates the interleaving of input signals x 1234  and x 5678  to generate band-pass output signal x 123456678 . 
         [0082]      FIGS. 14(A)-14(B)  show time and corresponding spectral plots for exemplary scenarios of using dual tones in generating low-pass and high-pass signals, respectively. The dual tones may be generated as described above in reference to  FIG. 9  and  FIGS. 10(A)-10(B) .  FIG. 14(A)  and  FIG. 14(B)  show simulations illustrating scenarios similar to those shown in  FIGS. 11(A)-11(F) . 
         [0083]      FIGS. 15(A)-15(D)  show time and corresponding spectral plots for exemplary lower-sideband and upper-side-band scenarios using dual tones in generating band-pass signals.  FIGS. 15(A)-15(D)  show simulations illustrating scenarios similar to the variations shown in  FIGS. 12(A)-12(D) . 
         [0084]      FIGS. 16(A)-16(D)  show spectral plots for exemplary scenarios of  FIGS. 8(A)-8(G) , incorporating bit-stream generators, and using dual-tone bit-streams in generating various signals.  FIG. 16(A)  shows a sample spectral plot for low-pass dual-tone bit-stream x 1 .  FIG. 16(B)  shows a sample spectral plot for low-pass dual-tone interleaved bit-stream x 12 .  FIG. 16(C)  shows a sample spectral plot for high-pass dual-tone bit-stream x 1234 .  FIG. 16(D)  shows a sample spectral plot for band-pass dual-tone bit-stream x 12345678 . 
         [0085]    Exemplary embodiments have been described where n=8, in other words, using arrays of eight FD filters and bit-stream generators. Alternative multi-path embodiments use different values of n, with corresponding numbers of FD filters, bit-stream generators, and serializer inputs. In some alternative embodiments, the fractional delays of the FD filters are spaced 1/n of a sample period apart. For example, in one four-path embodiment, the fractional delays are ¼, ½, ¾, and 1 of a sample period. In another four-path embodiment, the fractional delays are 0, ¼, ½, and ¾ of a sample period. 
         [0086]    An exemplary embodiment has been described where all of the FD filters of interleaved-bit-stream generator  402  of  FIG. 5 , and of interleaved-bit-stream generator  900  of  FIG. 9 , respectively, are identical to each other in structure. In alternative embodiments, interleaved-bit-stream generator  402 , or interleaved-bit-stream generator  900 , includes two or more FD filters having different structures. 
         [0087]    An exemplary embodiment has been described where all of the bit-stream generators of an interleaved-bit-stream generator, such as interleaved-bit-stream generator  402  of  FIG. 5  or interleaved-bit-stream generator  900  of  FIG. 9 , are identical to each other in structure. In alternative embodiments, interleaved-bit-stream generator  402 , or interleaved-bit-stream generator  900 , includes two or more bit-stream generators having different structures. 
         [0088]    An exemplary embodiment has been described where all of the serializer modules of serializer block  503  of  FIG. 5  and  FIG. 9  are identical to each other in structure. In alternative embodiments, serializer block  503  includes two or more serializer modules having different structures. 
         [0089]    As used herein in reference to data transfers between entities in the same device, and unless otherwise specified, the terms “receive” and its variants can refer to receipt of the actual data, or the receipt of one or more pointers to the actual data, wherein the receiving entity can access the actual data using the one or more pointers. 
         [0090]    Exemplary embodiments have been described wherein particular entities (a.k.a. modules) perform particular functions. However, the particular functions may be performed by any suitable entity and are not restricted to being performed by the particular entities named in the exemplary embodiments. 
         [0091]    Exemplary embodiments have been described with data flows between entities in particular directions. Such data flows do not preclude data flows in the reverse direction on the same path or on alternative paths that have not been shown or described. Paths that have been drawn as bidirectional do not have to be used to pass data in both directions. 
         [0092]    Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here. 
         [0093]    References herein to the verb “to generate” and its variants in reference to information or data do not necessarily require the creation and/or storage of new instances of that information. The generation of information could be accomplished by identifying an accessible location of that information. The generation of information could also be accomplished by having an algorithm for obtaining that information from accessible other information. 
         [0094]    The present invention may be implemented as circuit-based systems, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing steps in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, or general-purpose computer. 
         [0095]    The present invention can be embodied in the form of methods and apparatuses for practicing those methods. The present invention can also be embodied in the form of program code embodied in tangible media, such as magnetic recording media, optical recording media, solid state memory, floppy diskettes, CD-ROMs, hard drives, or any other non-transitory machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. The present invention can also be embodied in the form of program code, for example, stored in a non-transitory machine-readable storage medium including being loaded into and/or executed by a machine, wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code segments combine with the processor to provide a unique device that operates analogously to specific logic circuits. 
         [0096]    The present invention can also be embodied in the form of a bitstream or other sequence of signal values stored in a non-transitory recording medium generated using a method and/or an apparatus of the present invention. 
         [0097]    It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
         [0098]    Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
         [0099]    Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. As used in this application, unless otherwise explicitly indicated, the term “connected” is intended to cover both direct and indirect connections between elements. 
         [0100]    For purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. The terms “directly coupled,” “directly connected,” etc., imply that the connected elements are either contiguous or connected via a conductor for the transferred energy. 
         [0101]    The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as limiting the scope of those claims to the embodiments shown in the corresponding figures. 
         [0102]    The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to non-statutory subject matter are explicitly disclaimed even if they fall within the scope of the claims. 
         [0103]    Although the steps in the following method claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.