Abstract:
A driving device includes a first driving circuit, coupled to a first voltage source and a second voltage source having a voltage level lower than the first voltage source, for driving a positive output voltage to a first output end according to a first display voltage and charging the first output end with the second voltage source according to a control signal indicating whether the driving device performs a polarity inversion; and a second driving circuit, coupled to the second voltage source and a third voltage source having a voltage level lower than the second voltage source, for driving a negative output voltage to a second output end according to a second display voltage and discharging the second output end with the second voltage source according to the control signal.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation application of U.S. patent application Ser. No. 14/494,572, filed on Sep. 23, 2014, and all benefits of such earlier application are hereby claimed for this new continuation application. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a driving device, and more particularly, to a driving device capable of reducing voltage differences of charging and discharging operations in the driving device. 
     2. Description of the Prior Art 
     A liquid crystal display (LCD) is a flat panel display which has the advantages of low radiation, light weight and low power consumption and is widely used in various information technology (IT) products, such as notebook computers, personal digital assistants (PDA), and mobile phones. An active matrix thin film transistor (TFT) LCD is the most commonly used transistor type in LCD families, especially in the large-size LCD family. A driving system installed in the LCD, includes a timing controller, source drivers and gate drivers. The source and gate drivers respectively control data lines and scan lines, which intersect to form a cell matrix. Each intersection is a cell including crystal display molecules and a TFT. 
     In the driving system (e.g. a driving integrated circuit (IC)), the gate drivers are responsible for transmitting scan signals to gates of TFTs to turn on the TFTs on the panel. The source drivers are responsible for converting digital image data, sent by the timing controller, into analog voltage signals and outputting the voltage signals to sources of the TFTs. When the TFT receives the voltage signals, a corresponding liquid crystal molecule has a terminal whose voltage changes to equalize the drain voltage of the TFT, and thereby changes its own twist angle. The rate that light penetrates the liquid crystal molecule is changed accordingly, and thus different colors can be displayed on the panel. 
     Due to the heavy loadings of the TFTs and the liquid crystal molecules in the panel, the driving system consumes significant power when repeating charging and discharging the TFTs and the liquid crystal molecules, resulting in the violent temperature increase of the driving system and the reliability decrease of the driving system. Thus, how to reduce the power consuming on driving the panel becomes a topic to be discussed. 
     SUMMARY OF THE INVENTION 
     In order to solve the above problem, the present invention provides a driving device capable of reducing voltage differences of charging and discharging operations in the driving device for reducing the power consumption. 
     In an aspect, the present invention discloses a driving device. The driving device comprises a first driving circuit, coupled to a first voltage source and a second voltage source having a voltage level lower than the first voltage source, for driving a positive output voltage to a first output end according to a first display voltage and charging the first output end with the second voltage source according to a control signal indicating whether the driving device performs a polarity inversion; and a second driving circuit, coupled to the second voltage source and a third voltage source having a voltage level lower than the second voltage source, for driving a negative output voltage to a second output end according to a second display voltage and discharging the second output end with the second voltage source according to the control signal. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a driving module according to an embodiment of the present invention. 
         FIGS. 2A and 2B  are timing diagrams of related signals when the driving module shown in  FIG. 1  performs the polarity inversion. 
         FIG. 3  is an exemplary embodiment of the control unit  100  shown in  FIG. 1 . 
         FIG. 4  is a schematic diagram of a driving module according to another embodiment of the present invention. 
         FIG. 5  is a schematic diagram of a driving module according to still another embodiment of the present invention. 
         FIG. 6  is a timing diagram of related signals when the driving module shown in  FIG. 5  performs the polarity inversion. 
         FIG. 7  is a schematic diagram of a driving module according to an embodiment of the present invention 
         FIGS. 8A and 8B  are timing diagrams of the related signals when the driving module  70  shown in  FIG. 7  operates. 
     
    
    
     DETAILED DESCRIPTION 
     In the following embodiments of the present invention, driving modules for a driving device of a display system are disclosed. The power consumption of the driving modules are significantly decreased via reducing the voltage differences of charging and discharging operations in the driving modules when performing the polarity inversion, such that the temperature of the driving device would not increase violently and the reliability of the driving device can be improved. The present invention is particularly shown and described with respect to at least one exemplary embodiment accompanied by drawings. Words utilized for describing connections between two components such as ‘couple’ and ‘connect’ should not be taken as limiting a connection between the two components to be directly coupling or indirectly coupling. 
     Please refer to  FIG. 1 , which is a schematic diagram of a driving module  10  according to an embodiment of the present invention. The driving module  10  is utilized in a driving device (e.g. a driver integrated circuit (IC)) of a display system (e.g. a liquid-crystal display (LCD)) for generating output voltages VOUTP and VOUTN used for driving display components, such as liquid crystal molecules, of the display system. For example, the driving module  10  may be a source driver and the driving device may comprise a plurality of driving modules  10  for generating signals for driving a plurality of data lines of the display system. As shown in  FIG. 1 , the driving module  10  comprises a control unit  100  and driving units  102  and  104 . The control unit  100  is utilized for generating a control signal CON according to a polarity signal POL, wherein the polarity signal POL indicates whether the driving device performs a polarity inversion. The driving unit  102  is coupled to the control unit  100  and voltage sources VDD and VMID for generating the output voltage VOUTP at an output end VOUTP according to a display voltage VD 1  and charging the output end VOUTP via the voltage source VMID according to the control signal CON. Similarly, the driving unit  104  is coupled to the control unit  100  and the voltage source VMID and a ground GND for generating the output voltage VOUTN at an output end VOUTN according to a display voltage VD 2  and discharging the output end VOUTN via the voltage source VMID according to the control signal CON. Via charging the output end OUTP and discharging the output end OUTN when the polarity signal POL indicates that the display system performs the polarity inversion, the voltage differences of the transistors in the driving units  102  and  104  while performing the polarity inversion can be reduced, such that the power consumption of the driving module  10  is decreased. 
     In details, the voltage sources VDD and VMID may be provided by voltage regulators, such as buck converters, boost converters or low-voltage drop regulators, and is not limited herein. The voltage of the voltage source VDD is greater than that of the voltage source VMID and the voltage of the voltage source VMID is greater than that of the ground GND (i.e. VDD&gt;MID&gt;GND). For example, the voltage of the voltage source VMID may be the average of the voltages of the voltage source VDD and ground GND 
               (       i   .   e   .           ⁢   VMID     =       VDD   +   GND     2       )     .         
The driving unit  102  comprises an amplifier AMP 1 , switches SW 1 -SW 4 , and transistors MP 1  and MN 1 . The amplifier AMP 1  comprises a positive input end INP 1  for receiving the display voltage VD 1 , a negative input end INN 1  coupled to the output end OUTP, and output ends OP 1  and ON 1 . The switch SW 1  is coupled between the output end OP 1  and the gate of the transistor OP 1 , the switch SW 2  is coupled between the output end ON 1  and the gate of the transistor MN 1 , the switch SW 3  is coupled between the output end OP 1  and a voltage source VA, and the switch SW 4  is coupled between the output end ON 1  and the voltage source VA. The source and the drain of the transistor MP 1  are coupled to the voltage source VDD and the output end OUTP, respectively, and the source and the drain of the transistor MN 1  are coupled to the voltage source VMID and the output end OUTP, respectively. Note that, the voltage difference between the voltage sources VDD and VA is capable of making the transistor MP 1  to turn into cut-off state and the voltage difference between the voltage source VA and ground GND is capable of conducting the transistor MN 1 . For example, the voltage of the voltage source VA may be that of the voltage source VDD.
 
     Similarly, the driving unit  104  comprises an amplifier AMP 2 , switches SW 5 -SW 8 , and transistors MP 2  and MN 2 . The amplifier AMP 2  comprises a positive input end INP 2  for receiving the display voltage VD 2 , a negative input end INN 2  coupled to the output end OUTN, and output ends OP 2  and ON 2 . The switch SW 5  is coupled between the output end OP 2  and the gate of the transistor OP 2 , the switch SW 6  is coupled between the output end ON 2  and the gate of the transistor MN 2 , the switch SW 7  is coupled between the output end OP 2  and a voltage source VB, and the switch SW 8  is coupled between the output end ON 2  and the voltage source VB. The source and the drain of the transistor MP 2  are coupled to the voltage source VMID and the output end OUTN, respectively, and the source and the drain of the transistor MN 2  are coupled to the ground GND and the output end OUTN, respectively. Note that, the voltage difference between the voltage sources VMID and VB is capable of conducting the transistor MP 1  and the voltage difference between the voltage source VB and ground GND is capable of making the transistor MN 1  to turning into cut-off state. For example, the voltage of the voltage source VB may be that of ground GND. 
     When the polarity signal POL indicates that the driving module  10  performs normal operations, the control unit  100  generates the control signal CON to conduct the switches SW 1 , SW 2 , SW 5  and SW 6  and to disconnect the switches SW 3 , SW 4 , SW 7  and SW 8 . The amplifier AMP 1  therefore outputs appropriate signals UP 1  and DN 1  at the output ends OP 1  and ON 1 , respectively, to control the output stage consisted of the transistors MP 1  and MN 1  to charge the output end OUTP via a current I P1  from the voltage source VDD or to discharge the output end OUTP via a current I N1  to the voltage source VMID, so as to generate the output voltage VOUTP according to the display voltage VD 1 . In such a condition, an instant power consumption P +  and an average power consumption P AVG+  within a period T of the output stage consisted of the transistors MP 1  and MN 1  can be expressed as the following equations:
 
 P   +   =V   DSP1   ×I   P1   +V   DSN1   ×I   N1   (1)
 
     
       
         
           
             
               
                 
                   
                     P 
                     
                       AVG 
                       + 
                     
                   
                   = 
                   
                     
                       1 
                       T 
                     
                     ⁢ 
                     
                       
                         ∫ 
                         T 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             
                               
                                 V 
                                 
                                   DSP 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               × 
                               
                                 I 
                                 
                                   P 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                             
                             + 
                             
                               
                                 V 
                                 
                                   DSN 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                               × 
                               
                                 I 
                                 
                                   N 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   1 
                                 
                               
                             
                           
                           ) 
                         
                         ⁢ 
                         dt 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     wherein the voltage V DSP1  is the voltage across the drain and the source of the transistor MP 1  when charging the output end OUTP and the voltage V DSN1  is the voltage across the drain and the source of the transistor MN 1  when discharging the output end OUTP. 
     Similarly, the amplifier AMP 2  outputs appropriate signals UP 2  and DN 2  at the output ends OP 2  and ON 2 , respectively, to control the output stage consisted of the transistors MP 2  and MN 2  to charge the output end OUTN via a current I P2  from the voltage source VMID or to discharge the output end OUTN via a current I N2  to the ground GND, so as to generate the output voltage VOUTN according to the display voltage VD 2 . An instant power consumption P −  and an average power consumption P AVG−  within the period T of the output stage consisted of the transistors MP 2  and MN 2  can be expressed as the following equations:
 
 P   −   =V   DSP2   ×I   P2   +V   DSN2   ×I   N2   (3)
 
     
       
         
           
             
               
                 
                   
                     P 
                     
                       AVG 
                       - 
                     
                   
                   = 
                   
                     
                       1 
                       T 
                     
                     ⁢ 
                     
                       
                         ∫ 
                         T 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             
                               
                                 V 
                                 
                                   DSP 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                               × 
                               
                                 I 
                                 
                                   P 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                             + 
                             
                               
                                 V 
                                 
                                   DSN 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                               × 
                               
                                 I 
                                 
                                   N 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                             
                           
                           ) 
                         
                         ⁢ 
                         dt 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     wherein the voltage V DSP2  is the voltage across the drain and the source of the transistor MP 2  when charging the output end OUTN and the voltage V DSN2  is the voltage across the drain and the source of the transistor MN 2  when discharging the output end OUTN. As can be seen from the equations (1)-(4), the average power consumption of the driving module  10  can be reduced if the voltages V DSP1 , V DSN1 , V DSP2 , and V DSN2  become smaller. 
     When the polarity signal POL indicates that the display system is going to perform the polarity inversion, the output voltage VOUTP may need to be adjusted from ground voltage to a voltage greater than the voltage of the voltage source VMID and the output voltage VOUTN may need to be adjusted from the voltage of the voltage source VDD to a voltage smaller than the voltage of the source VMID. Generally, the output end OUTP is charged via the transistor MP 1  and the output end OUTN is discharged via the transistor MN 2 . In such a condition, an average power consumption P AVG  of the output stages consisted of the transistors MP 1 , MN 1  and MP 2 , MN 2  can be expressed as: 
     
       
         
           
             
               
                 
                   
                     P 
                     AVG 
                   
                   = 
                   
                     
                       
                         P 
                         
                           AVG 
                           + 
                         
                       
                       + 
                       
                         P 
                         
                           AVG 
                           - 
                         
                       
                     
                     = 
                     
                       
                         
                           1 
                           T 
                         
                         ⁢ 
                         
                           
                             ∫ 
                             T 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   P 
                                   + 
                                 
                                 + 
                                 
                                   P 
                                   - 
                                 
                               
                               ) 
                             
                             ⁢ 
                             dt 
                           
                         
                       
                       = 
                       
                         
                           
                             1 
                             T 
                           
                           ⁢ 
                           
                             
                               ∫ 
                               T 
                             
                             ⁢ 
                             
                               
                                 ( 
                                 
                                   
                                     
                                       V 
                                       
                                         DSP 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                     × 
                                     
                                       I 
                                       
                                         P 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         1 
                                       
                                     
                                   
                                   + 
                                   
                                     
                                       V 
                                       
                                         DSN 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         2 
                                       
                                     
                                     × 
                                     
                                       I 
                                       
                                         N 
                                         ⁢ 
                                         
                                             
                                         
                                         ⁢ 
                                         2 
                                       
                                     
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               d 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               t 
                             
                           
                         
                         = 
                         
                           
                             1 
                             T 
                           
                           ⁢ 
                           
                             
                               ∫ 
                               T 
                             
                             ⁢ 
                             
                               
                                 [ 
                                 
                                   VDD 
                                   ⁡ 
                                   
                                     ( 
                                     
                                       
                                         I 
                                         
                                           P 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           1 
                                         
                                       
                                       + 
                                       
                                         I 
                                         
                                           N 
                                           ⁢ 
                                           
                                               
                                           
                                           ⁢ 
                                           2 
                                         
                                       
                                     
                                     ) 
                                   
                                 
                                 ] 
                               
                               ⁢ 
                               dt 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     In order to reduce the power consumption of the driving module  10 , the control unit  100  generates the control signal CON for disconnecting the switches SW 1 , SW 2 , SW 5  and SW 6  and conducting the switches SW 3 , SW 4 , SW 7  and SW 8  for a certain period when the polarity signal POL indicates that the display system performs the polarity inversion in this embodiment. Within the certain period, the output end OUTP is charged via a current I N1′  from the voltage source VMID and the output end OUTN is discharged via a current I P2′  from the voltage source VMID. After the certain period, the output voltages VOUTP and VOUTN become the voltage of the voltage source VMID and the switches SW 1 , SW 2 , SW 5  and SW 6  are conducted and the switches SW 3 , SW 4 , SW 7  and SW 8  are disconnected according to the control signal CON. The output end OUTP changes to be charged via a current I P1′  from the voltage source VDD and the output end OUTN changes to be discharged by a current I N2  from ground GND. An average power consumption P AVG′  of the output stages consisted of the transistors MP 1 , MN 1  and MP 2 , MN 2  in this embodiment can be expressed as: 
     
       
         
           
             
               
                 
                   
                     P 
                     AVG 
                     ′ 
                   
                   = 
                   
                     
                       
                         P 
                         
                           AVG 
                           + 
                         
                         ′ 
                       
                       + 
                       
                         P 
                         
                           AVG 
                           - 
                         
                         ′ 
                       
                     
                     = 
                     
                       
                         
                           1 
                           T 
                         
                         ⁢ 
                         
                           
                             ∫ 
                             T 
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 
                                   P 
                                   + 
                                 
                                 + 
                                 
                                   P 
                                   - 
                                 
                               
                               ) 
                             
                             ⁢ 
                             dt 
                           
                         
                       
                       = 
                       
                         
                           
                             1 
                             T 
                           
                           ⁢ 
                           
                             
                               ∫ 
                               T 
                             
                             ⁢ 
                             
                               
                                 ( 
                                 
                                   
                                     P 
                                     + 
                                   
                                   + 
                                   
                                     P 
                                     - 
                                   
                                 
                                 ) 
                               
                               ⁢ 
                               dt 
                             
                           
                         
                         = 
                         
                           
                             
                               1 
                               T 
                             
                             ⁢ 
                             
                               
                                 ∫ 
                                 T 
                               
                               ⁢ 
                               
                                 
                                   [ 
                                   
                                     
                                       ( 
                                       
                                         
                                           
                                             V 
                                             
                                               DSN 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               1 
                                             
                                           
                                           × 
                                           
                                             I 
                                             
                                               N 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               1 
                                             
                                             ′ 
                                           
                                         
                                         + 
                                         
                                           
                                             V 
                                             
                                               DSP 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               1 
                                             
                                           
                                           × 
                                           
                                             I 
                                             
                                               P 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               1 
                                             
                                             ′ 
                                           
                                         
                                       
                                       ) 
                                     
                                     + 
                                     
                                       ( 
                                       
                                         
                                           
                                             V 
                                             
                                               DSP 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               2 
                                             
                                           
                                           × 
                                           
                                             I 
                                             
                                               P 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               2 
                                             
                                             ′ 
                                           
                                         
                                         + 
                                         
                                           
                                             V 
                                             
                                               DSN 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               2 
                                             
                                           
                                           × 
                                           
                                             I 
                                             
                                               N 
                                               ⁢ 
                                               
                                                   
                                               
                                               ⁢ 
                                               2 
                                             
                                             ′ 
                                           
                                         
                                       
                                       ) 
                                     
                                   
                                   ] 
                                 
                                 ⁢ 
                                 dt 
                               
                             
                           
                           = 
                           
                             
                               1 
                               T 
                             
                             ⁢ 
                             
                               
                                 ∫ 
                                 T 
                               
                               ⁢ 
                               
                                 
                                   [ 
                                   
                                     VMID 
                                     ⁡ 
                                     
                                       ( 
                                       
                                         
                                           I 
                                           
                                             P 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             1 
                                           
                                           ′ 
                                         
                                         + 
                                         
                                           I 
                                           
                                             N 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             1 
                                           
                                           ′ 
                                         
                                         + 
                                         
                                           I 
                                           
                                             P 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             2 
                                           
                                           ′ 
                                         
                                         + 
                                         
                                           I 
                                           
                                             N 
                                             ⁢ 
                                             
                                                 
                                             
                                             ⁢ 
                                             2 
                                           
                                           ′ 
                                         
                                       
                                       ) 
                                     
                                   
                                   ] 
                                 
                                 ⁢ 
                                 dt 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Assuming the times of charging and discharging the output ends OUTP and OUTN are constant and the charges in the driving module  10  obey the law of charges conservation, the current IP 1  is equal to the sum of the currents I P1′  and I N1′  (i.e. I P1 =I P1′ +I N1′ ) and the current IN 2  is equal to the sum of the current I P2′  and I N2′  (i.e. I N2 =I P2′ +I N2′ . According to the equations (5) and (6), the average power consumption P AVG′  is smaller than the average power consumption P AVG  since the voltage of the voltage source VMID is smaller than that of the voltage source VDD. In other words, the voltage differences of charging the output end OUTP and discharging the output end OUTN is reduced (e.g. reduced from the voltage of the voltage source VDD to that of the voltage source VMID) in this embodiment, so as to decrease the average power consumption of the driving module  10 . 
     Please refer to  FIGS. 2A and 2B , which are timing diagrams of related signals when the driving module  10  performs the polarity inversion. In  FIG. 2A , the switches SW 1 , SW 2 , SW 5  and SW 6  are constantly conducted and the switches SW 3 , SW 4 , SW 7  and SW 8  are constantly disconnected when the display system performs the polarity inversion and the operations of the driving module  10  are similar to those of the source driver in the conventional art. When the polarity inversion is performed, the output voltage VOUTP is desired to be increased from the voltage of ground GND to a target voltage VTAR 1 , which is greater than the voltage of the voltage source VMID, and the output voltage VOUTN is desired to be decreased from the voltage of the voltage source VDD to a target voltage VTAR 2 , which is smaller than the voltage of the voltage source VMID, in the period T. In such a condition, the amplifier AMP 1  would conduct the transistor MP 1  and disconnect the transistor MN 1  via the signals UP 1  and DN 1 , to charge the output end OUTP via the current IP 1  from the voltage source VDD and to increase the output voltage VOUTP to the target voltage VTAR 1 . Similarly, the amplifier AMP 2  would disconnect the transistor MP 2  and conduct the transistor MN 2  via the signals UP 2  and DN 2 , to discharge the output end OUTN via the current IN 2  from ground GND and to decrease the output voltage VOUTN to the target voltage VTAR 2 . The voltage difference of charging the output end OUTP is the voltage difference between the voltage of the voltage source VDD and the output voltage VOUTP, and the voltage difference of discharging the output end OUTN is the voltage difference between the voltage of the ground GND and the output voltage VOUTN in the beginning. 
     In comparison, please refer to  FIG. 2B , the switches SW 1 , SW 2 , SW 5  and SW 6  are disconnected and the switches SW 3 , SW 4 , SW 7  and SW 8  are conducted for the certain period when the display system performs the polarity inversion. As shown in  FIG. 2B , since the output end OUTP is charged by the voltage source VMID within a period TA and is charged by the voltage source VDD within a period TB, the voltage difference of charging the output end OUTP within the period TA is reduced to be the voltage difference between the voltage of the voltage source VMID and the output voltage OUTP, and the voltage difference of charging the output end OUTP within the period TB is the voltage difference between the voltage of the voltage source VDD and the output voltage OUTP. Similarly, since the output end OUTN is discharged by the voltage source VMID within the period TA and is discharged by ground GND within the period TB, the voltage difference of discharging the output end OUTN within the period TA is the voltage difference between the voltage of the voltage source VMID and the output voltage VOUTN, and the voltage difference of discharging the output end OUTN within the period TB is the voltage difference between the voltage of ground GND and the output voltage VOUTN. Via disconnecting the switches SW 1 , SW 2 , SW 5  and SW 6  and conducting the switches SW 3 , SW 4 , SW 7  and SW 8  for the certain period (i.e. the period TA) when the display system performs the polarity inversion, the voltage difference of charging the output end OUTP and discharging the output end OUTN is reduced, so as to decrease the average power consumption of the driving module  10 . 
     According to different applications and design concepts, the control unit  100 , the driving units  102  and  104  may be realized in different ways. Please refer to  FIG. 3 , which is a schematic diagram of an exemplary embodiment of the control unit  100  shown in  FIG. 1 . As shown in  FIG. 3 , the control unit  100  comprises inverters INV 1 , INV 2 , an exclusive-or logic gate XOR and a controller  300 . An input end of the inverter INV 1  is coupled to the polarity signal POL and an output end of the inverter INV 1  is coupled to the inverter INV 2 . An input end of the exclusive-or logic gate XOR is coupled to an output end of the inverter INV 2 , another input end of the exclusive-or logic gate XOR is coupled to the polarity signal POL and an output end of the exclusive-or logic gate XOR is coupled to the controller  300 . When the polarity signal POL switches from a high-voltage level to a low-voltage level (i.e. from ‘1’ to ‘0’) or from the low-voltage level to the high-voltage level (i.e. from ‘0’ to ‘1’), the display system performs the polarity inversion. Via the inverters INV 1 , INV 2  and the exclusive-or logic gate XOR, the controller  300  receives pulses when the polarity signal POL is switched, so as to generate the corresponded control signal CON according to the pulses for disconnecting the switches SW 1 , SW 2 , SW 5  and SW 6  and conducting the switches SW 3 , SW 4 , SW 7  and SW 8  for the certain period when the display system performs the polarity inversion. 
     Please refer to  FIG. 4 , which is a schematic diagram of a driving module  40  according to an embodiment of the present invention. The driving module  40  is similar to the driving module  10  shown in  FIG. 1 ; thus, the components and the signals with the similar functions use the same symbols. The driving module  40  is utilized in a driving device of a display system for generating the output voltages VOUTP and VOUTN used for driving display components, such as liquid crystal molecules, of the display system. For example, the driving module  40  may be a source driver and the driving device may comprise a plurality of driving modules  40  for generating signals for driving a plurality of data lines of the display system. Different from the driving module  10 , the switch SW 3  changes to be disposed between the output end OP 1  and the voltage source VDD, the switch SW 4  changes to be disposed between the output end ON 1  and the voltage source VMID, the switch SW 7  changes to be disposed between the output end OP 2  and the voltage source VMID, and the switch SW 8  changes to be disposed between the output end ON 2  and ground GND in the driving module  40 . The driving module  40  further adds switches SW 9 , SW 10 , diodes DIO 1  and D 102  in the driving units  102  and  104 , respectively. The switch SW 9  is coupled between the cathode of the diode DIO 1  and the output end OUTP, the anode of the diode DIO 1  is coupled to the voltage source VMID, the switch SW 10  is coupled between the anode of the diode D 102  and the output end OUTN, and the cathode of the diode D 102  is coupled to the voltage source VMID. 
     When the polarity signal POL indicates that the display system performs the polarity inversion, the control unit  100  generates the control signal for disconnecting the switches SW 1 , SW 2 , SW 5  and SW 6  and conducting the switches SW 3 , SW 4 , SW 7 -SW 10  for the certain period. Within the certain period, the transistors MP 1 , MN 1 , MP 2  and MN 2  are all in the cut-off state, the output end OUTP is charged by the voltage source VMID via the diode DIO 1  and the output end OUTN is discharged by the voltage source VMID via the diode VMID. As a result, the amount of charges of the voltage source VDD charging the output end OUTP and ground GND discharging the output end OUTN is reduced, so as to decrease the average power consumption of the driving module  40 . 
     Please refer to  FIG. 5 , which is a schematic diagram of a driving module  50  according to an embodiment of the present invention. The driving module  50  is similar to the driving module  10  shown in  FIG. 1 ; thus, the components and the signals with the similar functions use the same symbols. The driving module  50  is utilized in a driving device of a display system for generating the output voltages VOUTP and VOUTN used for driving display components, such as liquid crystal molecules, of the display system. For example, the driving module  50  may be a source driver and the driving device may comprise a plurality of driving modules  50  for generating signals for driving a plurality of data lines of the display system. In comparison with the driving module  10 , the switches SW 1 -SW 8  are removed and the output ends OP 1 , ON 1 , OP 2 , and ON 2  are coupled to the gates of the transistors MP 1 , MN 1 , MP 2  and MN 2 , respectively. The transistor MP 1  can be regarded as the switch coupled between the voltage source VDD and the output end OUTP and controlled by the control signal UP 1 . The transistor MN 1  can be regarded as the switch coupled between the voltage source VMID and the output end OUTP and controlled by the control signal DN 1 . The transistor MP 2  can be regarded as the switch coupled between the voltage source VMID and the output end OUTN and controlled by the control signal UP 2 . The transistor MN 2  can be regarded as the switch coupled between the ground and the output end OUTN and controlled by the control signal DN 2 . The control unit  100  may receive a charging-discharging signal CDS (e.g. the polarity signal POL), which indicates that the timings of the voltage source VDD charging the output end OUTP via the transistor MP 1 , the voltage source VMID discharging the output end OUTP via the transistor MN 1 , the voltage source VMID charging the output end OUTN via the transistor MP 2  and the ground GND discharging the output end OUTN via the transistor MN 2  according to the polarity signal POL. According to the charging-discharging signal CDS, the control unit  100  adjusts the voltages of the voltage sources VDD, VMID and ground GND. The voltage differences of charging/discharging the output end OUTP and charging/discharging the output end OUTN is therefore reduced 
     Please refer to  FIG. 6 , which is a timing diagram of related signals when the driving module  60  performs the polarity inversion. As shown in  FIG. 6 , when the polarity inversion is performed, the output voltage VOUTP is desired to be increased to a target voltage VTAR 3 , which is greater than the voltage of the voltage source VMID, and the output voltage VOUTN is desired to be decreased to a target voltage VTAR 4 , which is smaller than the voltage of the voltage source VMID, in the period T. Within the period T, the voltage of the voltage source VDD is decreased to a voltage VDD′, which is greater than the target voltage VTAR 3 . The voltage difference of charging the output end OUTP (i.e. the voltage difference across the drain and the source of the transistor MP 1 ) is therefore reduced, so as to decrease the power consumption of the driving module  50 . Similarly, the voltage of ground GND is increased to a voltage GND′, which is smaller than the target voltage VTAR 4 . The voltage difference of discharging the output end OUTN (i.e. the voltage difference across the drain and the source of the transistor MN 2 ) is therefore reduced, so as to decrease the power consumption of the driving module  50 . 
     Please refer to  FIG. 7 , which is a schematic diagram of a driving module  70  according to an embodiment of the present invention. The driving module  70  is similar to the driving module  10  shown in  FIG. 1 ; thus, the components and the signals with the similar functions use the same symbols. The driving module  70  is utilized in a driving device of a display system for generating the output voltages VOUTP and VOUTN used for driving display components, such as liquid crystal molecules, of the display system. For example, the driving module  70  may be a source driver and the driving device may comprise a plurality of driving modules  70  for generating signals for driving a plurality of data lines of the display system. In this embodiment, the control signal CON is not only used for switching the switches SW 1 -SW 8 , but also used for adjusting the voltages of the voltage sources VDD, VMID and ground GND. Similar to the driving module  10 , the switches SW 1 , SW 2 , SW 5  and SW 6  are conducted and the switches SW 3 , SW 4 , SW 7  and SW 8  are disconnected by the control signal CON when the polarity signal POL indicates that the driving module  10  performs normal operations. When the polarity signal POL indicates that the display system is going to perform the polarity inversion, the switches SW 1 , SW 2 , SW 5  and SW 6  are disconnected and the switches SW 3 , SW 4 , SW 7  and SW 8  for are conducted for certain period by the control signal CON. In this embodiment, the control signal CON further adjusts the voltages of the voltages of the voltage sources VDD, VMID and ground GND in the certain period, to decrease the drain-source voltages of charging and discharging the output ends OUTP and OUTN, so as to reduce the power consumption of the driving module  70 . 
     Please refer to  FIGS. 8A and 8B , which are timing diagrams of the related signals when the driving module  70  shown in  FIG. 7  operates. In  FIGS. 8A and 8B , the output end OUTP is charged by the voltage source VMID within the period TA and is charged by the voltage source VDD within the period TB. As shown in  FIG. 8A , the voltage source VMID keeps the same in the period TA and the charges consuming for charging the output end OUTP from the voltage source VMID is equal to the hatched area shown in  FIG. 8A . In comparison, the voltage source VMID is decreased at the beginning of the period TA and is gradually increased in the period TA. In such a condition, the charges consuming for charging the output end OUTP from the voltage source VMID is equal to the hatched area shown in  FIG. 8B . As can be seen from  FIGS. 8A and 8B , the charges of charging the output end OUTP from the voltage source VMID can be decreased if the voltage of the voltage source VMID is appropriately adjusted. According to different design concepts, the voltage of the voltage source VMID also can be increased when the control signal CON instructs discharging the output end OUTP to the voltage source VMID, to decrease the power consumption of discharging the output end OUTP. Via transiently adjusting the voltages of the voltage sources VDD, VMID and the ground GND, the power consumption of the driving module  70  can be reduced. 
     To sum up, the driving modules in the above embodiments reduce the power consumption via decreasing the voltage differences of charging and discharging operations when performing the polarity inversion. Therefore, the temperature of the driving device and the display system is prevented from being increased and the reliability of the driving device is improved. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.