Abstract:
A circuit for reducing leakage current in an ESD overvoltage protection circuit is described. Specifically, the circuit uses a semiconductor controlled rectifier or a semiconductor controlled switch to minimize the leakage.

Description:
FIELD OF THE INVENTION 
     The present invention pertains to the field of integrated circuit design. More particularly, the present invention relates to a circuit to place a device in a forward conducting state during transient power supply overvoltage events and to turn the device off during normal operation. 
     BACKGROUND OF THE INVENTION 
     On an integrated circuit chip, power rails are typically used to supply power to the chip. The power rails may comprise a positive power source Vcc and a ground Vss. Ideally, the power rails provide constant, steady voltages to the chip. Noise on the power rails, however, may cause voltage spikes or overvoltage on the Vcc network. Transient voltage on the Vcc network is a typical electrostatic discharge (ESD) event. ESD is potentially dangerous to transistors on an integrated circuit. Thus, overvoltage protection circuits are used to help discharge ESD events. 
     One example of an ESD overvoltage protection circuit is depicted in FIG.  1 . The circuit includes power rails Vcc  100  and Vss  105 , a timer circuit comprising resistor  110  and capacitor  120 , a first inverter comprising transistors  130  and  140  coupled to the timer circuit, a second inverter comprising transistors  150  and  160  coupled to the first inverter, a capacitor  170  coupled to the second inverter, and a transistor  180  coupled to capacitor  170 . The transistor  180  is typically a large PMOS device. 
     In normal operation, node  125  is held high by the timer circuit. The first inverter inverts the signal of node  125  and outputs an active low signal at node  155 . The second inverter then inverts the active low signal of node  155  and outputs an active high signal at node  175 . Because the node  175  is active high in normal operation, the transistor  180  is turned off. 
     During a voltage transient on Vcc  100 , the first inverter is toggled and outputs an active high signal at node  155 . The second inverter is also toggled and outputs an active low signal at node  175 , turning on transistor  180 . The transistor  180 , being a large PMOS transistor, is capable of shunting a large amount of current between power rails Vcc  100  and Vss  105 , which helps to discharge the ESD event. As the overvoltage is reduced, the inverters revert back to their normal logic levels and turn the transistor  180  off. 
     The transistor  180 , however, may be an appreciable source of leakage current between power rails Vcc  100  and Vss  105  during normal operation. The current trend in integrated circuit deign in CMOS technologies is toward ultra thin gate oxides, which tends to create higher levels of gate and subthreshold leakage. A typical product may have dozens of power supply clamps placed throughout the die. This can be problematic for power constrained or low-power applications. Therefore, a power clamping circuit that reduces standby leakage is desired. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The embodiments of the present invention are illustrated by way of example and not in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
     FIG. 1 is a prior art ESD protection circuit; 
     FIG. 2A is an embodiment of an ESD protection circuit that minimizes steady state leakage current; 
     FIG. 2B is another embodiment of an ESD protection circuit that minimizes steady state leakage current; 
     FIG. 3 is an embodiment of a semiconductor controlled switch; and 
     FIG. 4 is an embodiment of an optimized ESD protection circuit that minimizes steady state leakage current. 
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention. 
     FIG. 2A depicts one embodiment of the invention. The power supply clamping circuit of FIG. 2A comprises power rails Vcc  200  and Vss  205  and a timer circuit. For this embodiment of the invention, the timer circuit comprises resistor  210  and capacitor  220 . A first inverter comprising transistors  230  and  240  is coupled to the timer circuit. A second inventor comprising transistors  250  and  260  and a first capacitor  290  are coupled to the output of the first inverter. A semiconductor controlled switch (SCS)  280  and a second capacitor  270  is coupled to the output of the second inverter. The SCS  280  is a four terminal PNPN device that provides a discharge path between Vcc  200  and Vss  205  during transient overvoltage events. 
     An embodiment of the four terminal SCS  280  is depicted in FIG.  3 . The SCS  280  comprises a first p-doped region  310 , a first n-doped region  320 , a second p-doped region  330 , and a second n-doped region  340 . The first p-doped region  310  is coupled to Vcc  200  and the second n-doped region  340  is coupled to Vss  205 . The second p-doped region  330  is coupled to node  255  and the first n-doped region  320  is coupled to node  275 . 
     During normal operation, the SCS  280  is maintained in a forward blocking state to reduce leakage. Because node  255  is active low during normal operation and node  275  is active high during normal operation, the internal PN junction of the SCS  280  formed by n-doped region  320  and p-doped region  330  is kept in reverse bias which helps to prevent the SCS  280  from conducting current. The circuit of FIG. 2A helps to reduce the gate or transistor subthreshold leakage of power clamping circuits such as the large transistor structure of FIG.  1 . 
     During an ESD event, the high Vcc  200  to Vss  205  bias applied to the p-doped region  310  and the n-doped region  340  of SCS  280  will work to trigger the SCS  280  into a forward conducting state. In addition, the combination of node  255  being pulled active high and node  275  being pulled active low will help facilitate the transition of the SCS  280  to a forward conducting state. When the ESD event occurs, capacitor  220  charges to the new Vcc  200  value. If the node  225  attains a high enough value to trip transistor  230 , node  255  becomes an active high state. The second inverter then outputs an active low signal at node  275 . 
     The capacitors  290  and  270  help to modulate the effects of ESD events. The capacitors  290  and  270 , however, should be weak enough so that the first and second inverters can toggle the nodes  255  and  275  during an ESD event. Thus, capacitors  290  and  270  may be sized to be values less than the internal capacitances of SCS  280 . 
     To turn off the SCS  280  after the voltage transient is reduced, nodes  255  and  275  transition back to their steady state operating points which halts bipolar action of the SCS  280  and returns the device back to the forward blocking state to reduce leakage. Thus, node  225  returns to an active high state, the first inverter outputs an active low signal at node  255 , and the second inverter outputs an active high signal at node  275 . The size of SCS  280  may be adjusted to optimize the turn-on and the turn-off characteristics of the bipolar transition in addition to maintaining clamp stability. 
     Because the values of nodes  255  and  275  depend upon node  225 , the time for the SCS  280  to return to a forward blocking stage is also controlled in part by the speed in which the timer circuit takes to charge capacitor  220  back to an active high state. This voltage charging speed is defined by an RC time constant, which depends on the values of resistor  210  and capacitor  220 . The values of resistor  210  and capacitor  220  may be chosen such that the RC time constant is approximately one microsecond. The value of resistor  210  may be approximately one Mega-ohm. 
     For another embodiment of the invention, the SCS  280  may be substituted with a semiconductor controlled rectifier (SCR). A SCR is a three terminal PNPN transistor. Because a SCR has only three terminals, the SCR offers less control in placing the internal junction of the transistor in reverse or forward bias, but should otherwise provide the same functionality as the SCS  280 . 
     FIG. 2B depicts yet another embodiment of the invention. The power supply clamping circuit of FIG. 2B comprises power rails Vcc  201  and Vss  206 , and a RC timer circuit. For this embodiment of the invention, the timer circuit comprises transistor  211 , resistor  212 , and capacitor  221 . The transistor  211  functions as the resistance in the RC timer circuit. The transistor  211  may have a resistance in the Mega-ohm range. 
     A first inverter comprising transistors  231  and  241  is coupled to resistor  211  and capacitor  221 . A second inventor comprising transistors  251  and  261  and a first capacitor  291  are coupled to the output of the first inverter. A semiconductor controlled switch (SCS)  281  and a second capacitor  271  is coupled to the output of the second inverter. The SCS  281  is a four terminal PNPN device that provides a discharge path between Vcc  201  and Vss  201  during transient overvoltage events. 
     FIG. 4 depicts yet another embodiment of the invention. The circuit comprises power rails  400  and  405  and timer circuit  420 . A first inverter comprising transistors  410  and  415  is coupled to the timer circuit  420 . A second inverter comprising transistors  430  and  440  and is coupled to the output of the first inverter. A third inverter comprising transistors  450  and  460  and a first capacitor  490  are coupled to the output of the second inverter. A second capacitor  470  and an SCS  480  are coupled to the output of the third inverter. The circuit of FIG. 4 optimizes the circuits of FIG.  2 A and FIG. 2B by preventing the first inverter from having to drive both the second inverter and the SCS device. Instead, the output load of the first inverter is broken up in order to provide cleaner signals to the triggers of the SCS  480 . The trade-off of the optimized circuit of FIG. 4 is that is takes up more die area than the previously described circuits. 
     In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modification and changes may be made thereto without departure from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.