Abstract:
In the verification method of the present invention, a defect that is to cause a problem in fabrication is extracted from a mask pattern. The mask pattern is one obtained by deforming a mask pattern of a photomask used in a photolithography process so as to provide a transferred image close to a desired design pattern. The verification method includes the steps of: determining the exposure dose in the photolithography process; simulating the photolithography process on a computer based on the determined exposure dose; checking whether or not the desired design pattern has been obtained; and locating a fault point and outputting the result.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority under 35 U.S.C. §119 on Patent Application No. 2004-69585 filed in Japan on Mar. 11, 2004, the entire contents of which are hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to a method for forming a mask pattern used for fabrication of semiconductor integrated circuits with high accuracy relative to a layout pattern as design values for the semiconductor integrated circuits.  
         [0003]     In conventional mask pattern correction methods, corrected are a defocus occurring in an exposure process due to a difference in the height of an underlying layer and a dimension error occurring due to the proximity effect of a corrected pattern (Japanese Laid-Open Patent Publication No. 2002-333701 (page 3, paragraph 0016,  FIG. 1 ), for example).  
         [0004]     In other methods, correction using optical simulation results of layout design pattern data is adopted (Japanese Laid-Open Patent Publication No. 2002-174890 (page 2, paragraph 0008,  FIG. 1 ), for example).  
         [0005]     In the prior art technologies, with the aim of replicating a layout pattern as faithfully as possible, attention is focused on correction technology for correcting a mask pattern. The correction technology is known to include an error due to its theoretical limit. However, no verification has yet been established for circuit operation associated with deformation of a layout pattern due to this error. For example, when the absolute value of a fabrication variation is ±5 nm, the error is ±1.43% in the case of a minimum feature size of 350 mm, but it is ±5% in the case of a minimum feature size of 100 nm. In the latter case, therefore, the relative variation increases. No verification has conventionally been allowed for whether or not this potential variation error is permissible in the circuit design.  
         [0006]     A problem that will occur in the future with achievement of a finer fabrication process and a potential problem that may occur in the present situation cannot be verified even based on layout data as long as simulation is made within the normal fabrication variation range. For example, although no problem occurs in fabrication in the case of a minimum feature size of 350 nm, a problem may occur in the case of a minimum feature size of 250 nm. To find out this problem under the fabrication technology for the minimum feature size of 350 mm, layout data for the minimum feature size of 350 nm may be scaled down to 71%, and fabrication may be made under the fabrication technology for the minimum feature size 350 nm. A problem that may possibly occur in the case of a minimum feature size of 250 nm can then be detected. The problem detected in the above manner is found to be a potential point of problem (point having the possibility of becoming a problem and coming to the surface in the future) because this indicates that the fabrication technology has no allowance at this point of problem even in the case of a minimum feature size of 350 nm.  
         [0007]     In prediction of the yield in fabrication of semiconductor integrated circuits, the predicted value obtained based on layout data is different from the actual yield value because no consideration is given to the finished shape of a circuit pattern on a silicon wafer. The predicted value therefore includes an error. For example, a layout pattern formed on a silicon wafer is susceptible to the exposure dose within the range of a fabrication variation, defocus and steps computed from the layout pattern. The resultant layout pattern includes portions locally heavy or thin sporadically compared with the original layout pattern. Therefore, the sensitivity to an open circuit (cutting of the pattern) and a short circuit (contacting of adjacent lines of the pattern) tends to be low in the prediction of the yield of the semiconductor integrated circuits.  
       SUMMARY OF THE INVENTION  
       [0008]     The method of the present invention includes the steps of: simulating deformation of a layout pattern to be formed on a silicon wafer; extracting a circuit configuration formed on the silicon wafer from the deformed layout pattern; and simulating operation of the extracted circuit, whereby the degree of deformation of the layout pattern is computed based on the exposure dose within the range of a fabrication variation, defocus and steps computed from the layout pattern, a circuit configuration is extracted from the deformed layout pattern, and the resultant circuit is simulated, to thereby verify an effect of the deformation of the layout pattern on the circuit operation.  
         [0009]     Alternatively, the method of the present invention includes the steps of: shrinking a layout pattern at a given rate; and simulating deformation of the shrunk layout pattern to be formed on a silicon wafer, whereby the degree of deformation of the layout pattern is computed based on the exposure dose within the range of a fabrication variation, defocus and steps computed from the layout pattern, to thereby verify an effect of the deformation of the shrunk layout pattern on the circuit operation.  
         [0010]     Alternatively, the method of the present invention includes the steps of: simulating deformation of a layout pattern to be formed on a silicon wafer; and simulating an irregular problem occurring in a fabrication process, whereby the degree of deformation of the layout pattern is computed based on the exposure dose within the range of a fabrication variation, defocus and steps computed from the layout pattern, and degradation in yield due to an irregular problem in a fabrication process is detected, to thereby verify an effect of the deformation of the layout pattern on the circuit operation.  
         [0011]     According to the present invention, a problem in circuit operation due to deformation of a layout pattern to be formed on a wafer can be detected. Thus, not the entire mask pattern, but only a portion of the mask pattern that is to cause a problem in circuit operation can be properly corrected. If such correction is not allowed, it is possible to return to circuit design and change the circuit configuration to enable normal operation.  
         [0012]     Also, by shrinking a layout pattern at a given rate, prior examination can be made on a problem that will occur in design of next-generation semiconductor integrated circuits. In addition, a currently potential defective portion can be verified.  
         [0013]     Moreover, by computing the yield based on deformation of a layout pattern to be formed on a wafer, the actual yield can be computed accurately, and thus proper correction can be made for a portion of a mask pattern that is to cause a problem. If such correction is not allowed, it is possible to return to layout design and change the layout pattern to enable normal operation.  
         [0014]     The layout data verification method, the mask pattern correction method and the circuit operation verification method of the present invention include a photolithography simulation step, a silicon wafer step simulation step, a circuit information extraction step and a yield calculation step. These methods are useful for verification of a mask pattern and other uses. Using the verification results, also, these methods are applicable to prediction of the yield in fabrication of semiconductor integrated circuits and other uses. They are also applicable to detection of a potential problem factor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0015]      FIG. 1  is a flowchart showing a procedure of a mask pattern verification method of Embodiment 1 of the present invention.  
         [0016]      FIG. 2  is a flowchart showing a procedure of processing performed in a silicon wafer surface step simulation step shown in  FIG. 1 .  
         [0017]      FIG. 3  is a view showing an example of a pattern having a high possibility of a short circuit.  
         [0018]      FIG. 4  is a view showing an example of a pattern having a high possibility of a break.  
         [0019]      FIG. 5  is a flowchart showing a procedure of a circuit information extraction method of Embodiment 2 of the present invention.  
         [0020]      FIG. 6  is a flowchart showing a procedure of processing performed in an exposure dose determination step shown in  FIG. 5 .  
         [0021]      FIG. 7  is a flowchart showing a procedure of processing performed in a photolithography simulation step shown in  FIG. 5 .  
         [0022]      FIG. 8  is a flowchart showing a procedure of processing performed in a circuit information extraction step shown in  FIG. 5 .  
         [0023]      FIGS. 9A, 9B  and  9 C are diagrammatic views demonstrating simplification of a layout pattern in the circuit information extraction step.  
         [0024]      FIG. 10  is a flowchart showing a procedure of a mask pattern verification method of Embodiment 3 of the present invention.  
         [0025]      FIGS. 11A and 11B  are views for demonstrating a critical area.  
         [0026]      FIG. 12  is a flowchart showing a procedure of a circuit design verification method of Embodiment 4 of the present invention.  
         [0027]      FIG. 13  is a flowchart showing a procedure of processing performed in a layout pattern uniform shrink step shown in  FIG. 12 .  
         [0028]      FIG. 14  is a graph showing the number of chips obtainable on a silicon wafer, the predicted yield of chips and the number of conforming chips obtainable on a silicon wafer, with respect to the layout pattern uniform shrink rate.  
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.  
       Embodiment 1  
       [0030]      FIG. 1  is a flowchart showing a procedure of a mask pattern verification method of Embodiment 1 of the present invention. This verification method includes a silicon wafer surface step simulation step ST 100 , an exposure dose determination step ST 110 , a photolithography simulation step ST 120 , a wafer image verification step ST 130 , and a fault point detection step ST 140 . Hereinafter, these steps will be described specifically.  
         [0031]     &lt;Silicon Wafer Surface Step Simulation Step ST 100 &gt; 
         [0032]      FIG. 2  shows a flow of processing performed in the silicon wafer surface step simulation step ST 100 .  
         [0033]     First, the entire mask pattern is divided into regions in a grid shape (ST 101 ). In this region division, each of the divided mask pattern regions is arranged to overlap its adjacent mask pattern regions by a given amount so that in photolithography simulation to follow for each layer of each of the mask pattern regions, a layout pattern is obtained as a result of simulation performed correctly even to the boundaries of each region.  
         [0034]     The area factor of each layer is then calculated for each layout pattern region (ST 102 ). The area factor of each layer is multiplied by a coefficient related to the height of the layer, to obtain the height of each layer of each layout pattern region, and then the height of a silicon wafer in each photolithography process can be obtained as the sum of the heights of all layers.  
         [0035]     The difference (defocus) of the resultant height from the focus setting in the photolithography simulation is then determined as the silicon wafer surface step (ST 103 ).  
         [0036]     &lt;Exposure Dose Determination Step ST 110 &gt; 
         [0037]     In the exposure dose determination step ST 110 , the step width is determined according to the required analysis accuracy within the range of a variation in exposure dose arising in the fabrication process in fabrication of semiconductor integrated circuits, and the exposure dose is determined to be changed so that the range of the variation from its lower to upper limits is scanned with the step width.  
         [0038]     &lt;Photolithography Simulation Step ST 120 &gt; 
         [0039]     In the photolithography simulation step ST 120 , simulation is performed to replicate the photolithography process in fabrication of semiconductor integrated circuits on a computer based on the defocus value determined in the silicon wafer surface step simulation step ST 100  and the exposure dose for each step width determined in the exposure dose determination step ST 110 . As a result of the simulation, a layout pattern shape (wafer image) formed on a silicon wafer is obtained.  
         [0040]     &lt;Wafer Image Verification Step ST 130 &gt; 
         [0041]     In the wafer image verification step ST 130 , pattern comparison is made between the layout pattern obtained as a result of the photolithography simulation and the design layout pattern.  
         [0042]     &lt;Fault Point Detection Step ST 140 &gt; 
         [0043]     In the final fault point detection step ST 140 , when a short circuit or a break is found in the wafer image verification step ST 130 , such a point is naturally detected as a fault point. In addition, an allowance is set so that a point having a high possibility of causing a short circuit or a break although not yet causing such a trouble (for example, solid-line patterns (b) in  FIGS. 3 and 4 ) can also be detected as a fault point, and any point exceeding the allowance is regarded as an error as a fault point.  FIG. 3  shows an example of pattern having a high possibility of a short circuit, and  FIG. 4  shows an example of pattern having a high possibility of a break. In  FIGS. 3 and 4 , the reference code (a) denotes a design layout pattern, and (b) denotes a layout pattern obtained as a result of the photolithography simulation.  
       Embodiment 2  
       [0044]      FIG. 5  is a flowchart showing a procedure of a circuit information extraction method of Embodiment 2 of the present invention. This verification method includes an exposure dose determination step ST 200 , a photolithography simulation step ST 210 , a circuit information extraction step ST 220 , and a fault point detection step ST 230 . Hereinafter, these steps will be described specifically.  
         [0045]     &lt;Exposure Dose Determination Step ST 200 &gt; 
         [0046]      FIG. 6  shows a flow of processing performed in the exposure dose determination step ST 200 . In the exposure dose determination step ST 200 , the step width is determined according to the required analysis accuracy within the range of a variation in exposure dose arising in the fabrication process in fabrication of semiconductor integrated circuits (ST 201 ), and the exposure dose is determined to be changed so that the range of the variation from its lower to upper limits is scanned with the step width (ST 202 ).  
         [0047]     &lt;Photolithography Simulation Step ST 210 &gt; 
         [0048]      FIG. 7  shows a flow of processing performed in the photolithography simulation step ST 210 . In the photolithography simulation step ST 210 , simulation is performed to replicate the photolithography process in fabrication of semiconductor integrated circuits on a computer based on the exposure dose for each step width determined in the exposure dose determination step ST 200  (ST 211  to ST 213 ). As a result of the simulation, a layout pattern shape formed on a silicon wafer is obtained (ST 214 ).  
         [0049]     &lt;Circuit Information Extraction Step ST 220 &gt; 
         [0050]      FIG. 8  shows a flow of processing performed in the circuit information extraction step ST 220 . In the circuit information extraction step ST 220 , the layout pattern shape formed on a silicon wafer is entered, and the layout pattern is simplified to facilitate extraction of circuit information (ST 221  to ST 222 ).  FIGS. 9A  to  9 C show an example of the simplification.  FIG. 9A  shows original layout data (hatched region), and  FIG. 9B  shows a layout pattern shape (hatched region) formed on a silicon wafer. Specifically,  FIG. 9B  shows a layout pattern shape (hatched region) formed on a silicon wafer, represented by a curve or a polygon having a considerably large number of vertexes, which is to be simplified to a shape having roughly the same number of vertexes as the original layout data as preprocessing for extraction of information on a semiconductor integrated circuit.  
         [0051]     In this simplification, the layout pattern shape formed on a silicon wafer is made to approximate the original layout data as shown in  FIG. 9C  (hatched region) by shifting sides of the layout pattern shape with reference to the sides of the polygon representing the original layout data.  
         [0052]     Information on the semiconductor integrated circuit is then extracted from the simplified layout pattern (ST 223 ). Examples of information extracted in this step include the gate length and gate width of transistor elements and the width of interconnections for connection between semiconductor elements. Based on such information, information on the semiconductor integrated circuit is reconstructed.  
         [0053]     &lt;Fault Point Detection Step ST 230   
         [0054]     In the fault point detection step ST 230 , circuit operation is simulated based on the information on the semiconductor integrated circuit, to locate a defective circuit.  
       Embodiment 3  
       [0055]      FIG. 10  is a flowchart showing a procedure of a mask pattern verification method of Embodiment 3 of the present invention. This method will be described with reference to  FIG. 10 .  
         [0056]     Approximate data  1001  to the layout pattern shape formed on a silicon wafer, extracted in a circuit information extraction step ST 301  (processing in this step is the same as that described in Embodiment 2) is given to a critical area computation step ST 302 .  
         [0057]     In the critical area computation step ST 302 , the layout data  1001  is divided into line regions and space regions by graphic logical operation. The line regions are then classified into several types according to the line width by resizing and graphic logical operation, and the sum of critical areas for each type is determined. Likewise, the space regions are classified into several types according to the space shape, and the sum of critical areas for each type is determined. In this way, a critical area  1002  of an image formed on a silicon wafer is computed.  
         [0058]     In a yield prediction step ST 303 , the yield of the image formed on a silicon wafer can be predicted from expression 1 to be described later, permitting random defect prediction for both open circuit and short circuit.  
         [0059]     An example of prediction of the yield in fabrication will be described. Some methods have been proposed for yield prediction, including a method using a defect distribution curve and the critical area in which a defect actually causes a failure for the yield prediction (ISSM 1997, 0.25 um Integrated Circuit Yield Model Design and Validation).  
         [0060]     The overall yield of a process is generally represented by the product of the systematic yield (YS) determined according to the system and the yield (YR) determined with a random defect.  
         [0061]     The yield YR determined with a random defect is represented by the expression 1 below according to a Poisson distribution model, for example. 
 
 YR =exp(− DD*Ac )  Expression 1 
 
 where DD is the number of defects per unit critical area and Ac is a critical area. 
 
         [0062]     The critical area as used herein refers to the total sum of areas in a chip that may actually be impaired due to existence of defects.  
         [0063]     The idea of the critical area will be described in relation to a short circuit between interconnections with reference to  FIGS. 11A and 11B . Assuming that interconnections  30  having a line width  31  run in parallel with each other with a space  32  therebetween, when a defect  33  is smaller than the space  32  as shown in  FIG. 11A , the critical area is determined zero. When the defect  33  is greater than the space  32  as shown in  FIG. 11B , the defect  33  may possibly cause a critical area. Therefore, by parameterizing the relationship among the line width  31 , the space  32  and the defect  33 , the critical area can be computed by extracting the layout data for each line width.  
         [0064]     The critical area can also be computed in relation to open interconnections in a similar manner.  
         [0065]     Thus, the yield prediction for the pattern formed on a silicon wafer can be performed by computing the critical area based on the data obtained after the extraction of the circuit information from the simulation result and adopting the model of the expression 1.  
       Embodiment 4  
       [0066]      FIG. 12  is a flowchart showing a procedure of a circuit design verification method of Embodiment 4 of the present invention. This verification method is a circuit design verification method based on potential variation error performed using a layout pattern uniform shrink scheme. Hereinafter, steps of this method will be described specifically.  
         [0067]      FIG. 13  shows a flow of processing performed in a layout pattern uniform shrink step ST 400 .  
         [0068]     Referring to  FIG. 13 , in the layout pattern uniform shrink step ST 400 , the chip size after shrink is computed based on an entered shrink rate (ST 401  to ST 402 ), and the number of chips obtainable on a silicon wafer is computed from the chip size (ST 403 ). Separately from this step, the layout pattern is uniformly shrunk (ST 404 ), and the predicted yield for the shrunk data is computed (ST 405 ). The number of conforming chips obtainable on a silicon wafer is then computed from the computation result of the number of chips obtainable on a silicon wafer and the computation result of the predicted yield (ST 406 ). This computation of the number of conforming chips is made in the descending order of the shrink rate from 100%. As shown in  FIG. 14 , as the shrink rate decreases, the yield decreases, but the number of chips obtainable on a silicon wafer increases. By multiplying the yield by the number of chips obtainable on a silicon wafer, the number of conforming chips on a silicon wafer for each shrink rate can be computed, and from  FIG. 14 , the shrink rate at which the number of conforming chips is maximum can be determined.  
         [0069]     In an exposure dose determination step ST 410 , the step width is determined according to the required analysis accuracy within the range of a variation in exposure dose arising in the fabrication process in fabrication of semiconductor integrated circuits, and the exposure dose is determined to be changed so that the range of the variation from its lower to upper limits is scanned with the step width.  
         [0070]     In a photolithography simulation step ST 420 , simulation is performed to replicate the photolithography process in fabrication of semiconductor integrated circuits on a computer based on the exposure dose for each step width determined in the exposure dose determination step ST 410 . As a result of the simulation, a layout pattern shape formed on a silicon wafer is obtained.  
         [0071]     In a fault point detection step ST 430 , circuit operation is simulated based on the information on the semiconductor integrated circuit, to locate a defective circuit.  
         [0072]     While the present invention has been described in preferred embodiments, it will be apparent to those skilled in the art that the disclosed invention may be modified in numerous ways and may assume many embodiments other than that specifically set out and described above. Accordingly, it is intended by the appended claims to cover all modifications of the invention which fall within the true spirit and scope of the invention.