Abstract:
A synchronous DRAM (SDRAM) or a fast cycle RAM (FCRAM) includes capacitors connected by switches to a signal wire. The switches are controlled to connect and disconnect the capacitors to the signal wire. In a test mode, various combinations of the capacitors are connected to the signal wire and the signal timing is then measured. The signal timing of the memory device can be controlled by selecting which and how many of the capacitors are connected to the signal wire.

Description:
[0001]    The present invention relates to semiconductor memory devices and methods for testing semiconductor memory devices. More particularly, the present invention relates to a method for testing semiconductor memory devices, which are operated by acquiring external commands and external addresses synchronously with high frequency clock signals.  
           [0002]    In recent synchronous dynamic random access memories (SDRAM), the cycle time (RAS cycle time) for acquiring external commands has been reduced to 60 nanoseconds. Such SDRAMs acquire external command signals in synchronism with clock signals and are operated at high speeds. More specifically, the conventional SDRAM acquires a row address simultaneously with an active command during a read/write operation. The SDRAM then acquires a column address simultaneously with an active command.  
           [0003]    Since the recent SDRAMs use control signals (i.e., bit wire short signals, word wire latch signals, and sense amplifier latch signals) having shortened cycles, the transmission timing of the control signals must be accurate. Thus, the timing of the control signals is adjusted by employing an electron-beam (EB) tester to perform a focused ion beam (FIB) process.  
           [0004]    The SDRAM undergoes various testing. For example, an internal refresh counter test is carried out on the SDRAM in accordance with the following procedures. First, when entering a counter test cycle in response to a test command, the row address indicated by the count value of the internal counter is accessed. This increments the value of the internal refresh counter. Test data is then written at a predetermined column address in response to a write command. The SDRAM then exits the counter test cycle. Afterward, the counter test cycle is entered again in response to a test command. After the value of the internal refresh counter is incremented, predetermined data is written on the incremented column address by another write command.  
           [0005]    The write process is performed repeatedly thereafter. When the count value of the internal refresh counter reaches a final value, the executed command is changed from the write command to a read command and a data check is carried out. The command is shifted when re-entering the test mode after exiting the test mode.  
           [0006]    Generally, when the SDRAM is in the test mode, a so-called write-read process, in which test data is immediately read after the test data is written, is also performed to test every cell.  
           [0007]    A RAM which acquires commands in short cycles of 20 nanoseconds has also been proposed. The FCRAM is adapted to cope with high speeds by acquiring external commands (read/write command) and external addresses (row address and column address) in synchronism with clock signals. Such a RAM is referred to as a fast cycle (FC) RAM. The control signals of the FCRAM have cycles that are shorter than those of the SDRAM described above. Furthermore, the FCRAM differs from the conventional SDRAMs in that active commands are not used. The FCRAM is provided with an auto precharge function which automatically executes precharge after the read process or the write process to increase the speed.  
           [0008]    The FCRAM operates at a higher speed than the SDRAM. Thus, when the technology applied to the SDRAM is applied to the DRAM, the following shortcomings occur.  
           [0009]    (1) Due to the FCRAM&#39;s control signal cycle, which is shorter than the SDRAM&#39;s control signal cycle, the FCRAM cannot adjust the timing as accurately as the SDRAM if the timing is adjusted in the same manner as the SDRAM. More particularly, the FIB process carried out on the SDRAM is performed before a protective film, such as polyimide, is applied to the circuits of the device since the timing cannot be adjusted unless the wires are uncovered. However, the protective film greatly affects the wire capacitance and changes the delay times of the control signals. Thus, the formation of the protective film varies the timing even if the timing is adjusted through the FIB process. Accordingly, the timing cannot be adjusted with high accuracy regardless of whether the timing adjustment is carried out before the formation of the protective film. That is, the timing cannot be adjusted if the protective film is applied as in the actual state of usage.  
           [0010]    (2) The FCRAM acquires the row addresses and column addresses simultaneously and activates the RAS and CAS circuits simultaneously. Therefore, when the FCRAM carries out the same counter test as the SDRAM, the refresh counter value is incremented whenever entering the test cycle in accordance with the test command. Furthermore, since the FCRAM acquires the row address and the column address simultaneously, the value of the refresh counter is incremented each time the write command is acquired. This writes test data on every other cell. Thus, every cell cannot be tested if the read/write operation is performed in the same manner as the SDRAM.  
           [0011]    (3) The performance of a burn-in test on the FCRAM to effectively eliminate initial malfunctions also leads to a shortcoming. The burn-in test is carried out to detect initial malfunctions by actuating the device under conditions that are higher than the rated ambient temperature and the rated power supply voltage.  
           [0012]    During the burn-in test, the device may be operated with an extremely long cycle of several hundreds of microseconds. In such case, the FCRAM automatically performs precharge after a read process or a write process regardless of the clock cycle. Thus, the FCRAM is in a precharge state during most of the test time. Accordingly, the FCRAM cannot be tested effectively.  
           [0013]    Furthermore, the auto precharge is performed each time the refresh counter is operated when performing the counter test. Accordingly, the precharge operation is not necessary when testing only the refresh counter.  
           [0014]    Accordingly, it is an objective of the present invention to provide a semiconductor memory device which performs tests efficiently and with high accuracy.  
         SUMMARY OF THE INVENTION  
         [0015]    To achieve the above objective, the present invention provides a method for testing a semiconductor memory device that acquires an external command and an external address in synchronism with a clock signal. The device includes a signal wire through which a control signal is provided and a plurality of capacitors connected in parallel to the signal wire via a plurality of switch circuits. The method includes the steps of connecting a predetermined number of the capacitors to the signal wire by making a predetermined number of the switch circuits conductive, providing the control signal to the signal wire, measuring the transmission time of the control signal, and varying the capacitance of the signal wire by altering the number of the conductive switch circuits.  
           [0016]    In a second aspect of the present invention, a semiconductor memory device that acquires an external command and an external address simultaneously in synchronism with a clock signal is provided. The device includes a signal wire through which a control signal is provided, a plurality of capacitors connected in parallel to the signal wire via a plurality of switch circuits, a test mode setting circuit for generating a mode signal provided to the signal wire in accordance with the external command, and a selecting circuit connected to the test mode setting circuit and each of the switch circuits for generating a selection signal, which selects the switch circuit that is made conductive, and provides the selection signal to the selected switch circuit when receiving the mode signal from the test mode setting circuit.  
           [0017]    In a third aspect of the present invention, a method for testing a semiconductor memory device that acquires an external command and an external address in synchronism with a clock signal is provided. The device includes a refresh counter for generating an internal address, and an address latch circuit for latching either the external address or the internal address. The method includes the steps of providing a mode signal which instructs the device to execute operations and providing a pulse signal derived from the external command. The operations include a counter testing operation and a refresh operation. The method also includes the steps of incrementing the value of the internal address in accordance with the pulse signal when the mode signal instructs execution of the counter testing operation or the refresh operation, and latching the internal address in the address latch circuit.  
           [0018]    In a fourth aspect of the present invention, a semiconductor memory device that acquires an external command, which includes a write command and a read command, and an external address in synchronism with a clock signal is provided. The device includes a mode setting circuit for receiving a pulse signal and generating control pulse signals. The pulse signal is generated in accordance with the write command and the read command. The mode setting circuit generates a first control pulse signal in accordance with a first mode signal which instructs execution of a counter testing operation and a refresh operation based on the external command. The mode setting circuit further generates a second control pulse signal in accordance with a second mode signal which instructs execution of an operation other than the counter testing operation and the refresh operation. A refresh counter is connected to the mode setting circuit. The refresh counter receives the first control pulse signal from the mode setting circuit and performs a counting operation in accordance with the first control pulse signal. An address latch circuit is connected to the mode setting circuit and the refresh counter. The address latch circuit outputs either the first control pulse signal or the second control pulse signal as a row address. The address latch circuit latches the count value of the refresh counter in accordance with the first control pulse signal and outputs the latched value as the row address. The address latch circuit also latches the external address acquired together with the write command or the read command in accordance with the second control pulse signal and outputs the latched value as the row address.  
           [0019]    In a fifth aspect of the present invention, a method for testing a semiconductor memory device that acquires an external command, which includes a write command and a read command, and an external address in synchronism with a clock signal and automatically performs precharge after the read operation or the write operation is provided. The method includes the steps of setting a test mode, and stopping the precharge when either the read operation or the write operation is performed.  
           [0020]    In a sixth aspect of the present invention, a semiconductor memory device that acquires an external command, which includes a write command and a read command, and an external address simultaneously in synchronism with a clock signal and automatically performs precharge after the read operation or the write operation is provided. The device includes a read/write control circuit for generating an auto precharge signal for a predetermined time after the read operation and write operation are performed. A precharge control circuit receives the auto precharge signal and outputs a precharge signal. A test mode setting circuit provides a mode signal, which invalidates the auto precharge signal to the precharge control signal.  
           [0021]    Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0022]    The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:  
         [0023]    [0023]FIG. 1 is a schematic diagram showing a timing adjustment circuit of a synchronous DRAM according to a first embodiment of the present invention;  
         [0024]    [0024]FIG. 2 is a circuit diagram showing a switch circuit of the timing adjustment circuit of FIG. 1;  
         [0025]    [0025]FIG. 3 is a schematic diagram showing a capacitor selecting circuit of the timing adjustment circuit of FIG. 1;  
         [0026]    [0026]FIG. 4 is a schematic diagram showing a counter tester circuit of a refresh counter according to a second embodiment of the present invention;  
         [0027]    [0027]FIG. 5 is a circuit diagram showing a counter portion of the counter test circuit of FIG. 4;  
         [0028]    [0028]FIG. 6 is a circuit diagram showing a latch circuit portion of the counter test circuit of FIG. 4;  
         [0029]    [0029]FIG. 7 is a schematic diagram showing an auto precharge stopping circuit according to a third embodiment of the present invention;  
         [0030]    [0030]FIG. 8 is a schematic diagram showing a test mode setting circuit of the auto precharge stopping circuit of FIG. 7; and  
         [0031]    [0031]FIG. 9 is a schematic diagram showing a precharge control circuit of the auto precharge stopping circuit of FIG. 7. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0032]    (First Embodiment)  
         [0033]    An FCRAM according to a first embodiment of the present invention will now be described with reference to FIGS.  1  to  3 .  
         [0034]    As shown in FIG. 1, the FCRAM includes a timing adjustment circuit  10  connected to a signal wire LI . The timing adjustment circuit  10  may also be connected to a signal wire through which control signals, such as a bit wire control signal, a word line latch signal, and a sense amplifier signal, are transmitted. First and second inverters INV 1 , INV 2 , a resistor R, and a capacitor C are connected to the signal wire LI. The timing adjustment circuit  10  is connected to the signal wire LI between the first and second inverters INV 1 , INV 2 . The first inverter INV 1  receives a control signal SX from an internal circuit (not shown) and provides the inverted control signal SX to the second inverter INV 2  through the signal wire LI . The second inverter INV 2  inverts the inverted control signal SX and then provides the control signal SX to the next internal circuit (not shown). The resistor R and the capacitor C form a delay circuit.  
         [0035]    The timing adjustment circuit  10  includes a delay time adjustment circuit  11 , a selection circuit  12 , and a test mode setting circuit  13 .  
         [0036]    The delay time adjustment circuit  11  includes first, second, third, and fourth delay circuits  15 ,  16 ,  17 ,  18 . The delay circuits  15 - 18  include switch circuits SW 1 , SW 2 , SW 3 , SW 4  and capacitors C 1 , C 2 , C 3 , C 4 , respectively.  
         [0037]    As shown in FIG. 2, each of the switch circuits SW 1 -SW 4  includes a p-channel MOS transistor T 1 , an n-channel MOS transistor T 2 , and an inverter INV 3 . The transistors T 1 , T 2  form a transfer gate circuit.  
         [0038]    The PMOS transistor T 1  has a gate which receives an associated first, second, third, or fourth gate signal SG 1 , SG 2 , SG 3 , SG 4 . The NMOS transistor T 2  has a gate which receives the same gate signal SG 1 , SG 2 , SG 3 , SG 4  via the inverter INV 3 .  
         [0039]    When the first to fourth gate signals SG 1 -SG 4  are low, the associated switch circuits SW 1 -SW 4  are activated. This connects the associated switch circuit SW 1 -SW 4  to the signal wire LI. If the first to fourth gate signals SG 1 -SG 4  are high, the associated switch circuit SW 1 -SW 4  is de-activated. This electrically disconnects the associated switch circuit SW 1 -SW 4  from the signal wire LI.  
         [0040]    Accordingly, the number of capacitors C 1 -C 4  connected to the signal wire LI is controlled by controlling the level of the first to fourth gate signals SG 1 -SG 4 . This adjusts the wire capacitance of the signal wire LI and the transmission timing of the control signal SX. The transmission delay increases as the number of the capacitors C 1 -C 4  connected to the signal wire LI increases. Of course, as will be understood by those of ordinary skill in the art, the transmission delay can also be effected by various size capacitors.  
         [0041]    As shown in FIG. 1, the selection circuit  12  includes a first input buffer  21 , a second input buffer  22 , a capacitor selecting circuit  23 , a first gate circuit  35 , a second gate circuit  36 , a third gate circuit  37 , and a fourth gate circuit  38 . The first and second input buffers  21 ,  22  receive first and second designation signals A 1 , A 2 , respectively, and provide the designation signals A 1 , A 2  to the capacitor selecting circuit  23 . The first designation signal A 1  from the first input buffer  21  is provided directly to the capacitor selecting circuit  23 . The designation signal A 1  is also provided to the capacitor selecting circuit  23  via an inverter  24  as a third designation signal /A 1 . The first and third designation signals A 1 , /A 1  are complementary signals. The second designation signal A 2  from the second input buffer  22  is provided directly to the capacitor selecting circuit  23 . The designation signal A 2  is also provided to the capacitor selecting circuit  23  via an inverter  125  as a fourth designation signal /A 2 . The second and fourth designation signals A 2 , /A 2  are complementary signals. The first to fourth designation signals A 1 , A 2 , /A 1 , /A 2  are used to select the capacitors C 1 -C 4  to be connected to the signal line LI .  
         [0042]    As shown in FIG. 3, the capacitor selecting circuit  23  has first to seventh NAND circuits  25 - 31  and an inverter  32 .  
         [0043]    The first NAND circuit  25  has two input terminals which receive the third and fourth designation signals /A 1 , /A 2  and an output terminal connected to the input terminal of the fifth NAND circuit  29 . The second NAND circuit  26  has two input terminals which receive the first and fourth designation signals A 1 , /A 2  and an output terminal connected to the input terminals of the fifth and sixth NAND circuits  29 ,  30 . The third NAND circuit  27  has two input terminals which receive the third and second designation signals /A 1 , A 2  and an output terminal connected to the input terminals of the fifth to seventh NAND circuits  29 - 31 . The fourth NAND circuit  28  has two input terminals which receive the first and second designation signals A 1 , A 2  and an output terminal connected to the input terminals of the fifth to seventh NAND circuits  29 - 31  and to the inverter  32 .  
         [0044]    The fifth NAND circuit  29  receives the signals from the first to fourth NAND circuits  25 - 28  and provides a first selection signal SEL 1  to the first gate circuit  35 . The sixth NAND circuit  30  receives the signals from the second to fourth NAND circuits  26 - 28  and provides a second selection signal SEL 2  to the second gate circuit  36 . The seventh NAND circuit  31  receives the signals from the third and fourth NAND circuits  27 ,  28  and provides a third selection signal SEL 3  to the third gate circuit  37 . The inverter  32  receives the signal from the fourth NAND circuit  28  and provides a fourth selection signal SEL 4  to the fourth gate circuit  38 .  
         [0045]    The level of each of the first to fourth selection signals SEL 1 -SEL 4  is set in accordance with the levels of the first and second designation signals A 1 , A 2 . If the first and second designation signals A 1 , A 2  are both low, the first selection signal SEL 1  is high and the second to fourth selection signals SEL 2 -SEL 4  are all low. If the first designation signal A 1  is high and the second designation signal A 2  is low, the first and second selection signals SEL 1 , SEL 2  are high and the third and fourth selection signals SEL 3 , SEL 4  are low. If the first designation signal A 1  is low and the second designation signal A 2  is high, the first to third selection signals SEL 1 -SEL 3  are high and the fourth selection signal SEL 4  is low. If the first and second designation signals A 1 , A 2  are both high, the first to fourth selection signals SEL 1 -SEL 4  are all high.  
         [0046]    As shown in FIG. 1, the first to fourth gate circuits  35 - 38  receive the associated first to fourth selection signals SEL 1 -SEL 4  from the capacitor selecting circuit  23  and a mode signal MS 1  from the test mode setting circuit  13 . The first to fourth gate circuits  35 - 38  provide the associated delay circuits  15 - 18  with the corresponding first to fourth gate signals SG 1 -SG 4 .  
         [0047]    Therefore, when the mode signal MS 1  is high, the first to fourth gate circuits  35 - 38  provide the first to fourth gate signals SG 1 -SG 4  to the associated switch circuits SW 1 -SW 4 .  
         [0048]    If the first and second designation signals A 1 , A 2  are both low, the first gate signal SG 1  falls, which activates the switch circuit SW 1 . This connects the capacitor C 1  to the signal wire LI. If the first designation signal A 1  is high but the second designation signal A 2  is low, the first and second signals SG 1 , SG 2  fall, which activates the switch circuits SW 1 , SW 2 . This connects the capacitors C 1 , C 2  to the signal wire LI. If the first designation signal A 1  is low but the second designation signal A 2  is high, the first to third gate signals SG 1 -SG 3  fall, which activates the switch circuits SW 1 -SW 3 . This connects the capacitors C 1 -C 3  to the signal wire LI. If the first and second designation signals A 1 , A 2  are both high, the first to fourth gate signals SG 1 -SG 4  fall, which activates the switch circuits SW 1 -SW 4 . This connects the capacitors C 1 -C 4  to the signal wire LI.  
         [0049]    The test mode setting circuit  13  receives a test signal TS generated in accordance with a test command, which is sent from a testing apparatus (not shown), and provides the mode signal MS 1  to the first to fourth gate circuits  35 - 38 . When the level of the test signal TS indicates execution of the test mode (e.g., when the signal TS is high), the test mode setting circuit  13  provides a high mode signal MS 1  to the first to fourth gate circuits  35 - 38 . In this state, the capacitor C 1 -C 4  connected to the signal wire LI is selected in accordance with the combination of the levels of the first and second designation signals A 1 , A 2 . If the level of the test signal TS indicates that the test mode is not being executed (e.g., when the signal TS is low), the test mode setting circuit  13  provides a low mode signal MS 1  to the first to fourth gate circuits  35 - 38 . In this state, the first to fourth gate signals SG 1 -SG 4  all rise, which causes all of the capacitors C 1 -C 4  to be electrically disconnected from the signal wire LI regardless of the level of the first and second designation signals A 1 , A 2 .  
         [0050]    The operation of the timing adjustment circuit  10  will now be described.  
         [0051]    The test mode setting circuit  13  is provided with a high test signal TS in order to test the transmission timing of the control signal SX, which is transmitted between the first and second inverters INV 1 , INV 2 , with the testing apparatus. A high mode signal MS 1  is then provided to the first to fourth gate circuits  35 - 38 .  
         [0052]    If the first and second designation signals A 1 , A 2  both fall in response to the command from the testing apparatus, the capacitor C 1  is connected to the signal wire LI. This provides a testing control signal SX to the signal wire LI. In this state, the transmission time (i.e., transmission timing) required for the control signal SX to reach the second inverter INV 2  from the first inverter INV 1  is measured.  
         [0053]    After the time measurement, a high first designation signal A 1  and a low second designation signal A 2  connect the capacitors C 1 , C 2  to the signal wire LI . In this state, the transmission time required for the control signal SX to reach the second inverter INV 2  from the first inverter INV 1  is measured.  
         [0054]    A low first designation signal A 1  and a high second designation signal A 2  then connect the capacitors C 1 -C 3  to the signal wire LI. In this state, the transmission time required for the control signal SX to reach the second inverter INV 2  from the first inverter INV 1  is measured.  
         [0055]    Finally, high first and second designation signals A 1 , A 2  are provided to connect the capacitors C 1 -C 4  to the signal wire LI. In this state, the transmission time required for the control signal SX to reach the second inverter INV 2  from the first inverter INV 1  is measured. This completes the testing of the transmission time.  
         [0056]    As described above, the number of capacitors C 1 -C 4  connected to the signal wire LI is altered in accordance with the combination of the level of the first and second designation signals A 1 , A 2 . This facilitates transmission time measurement, which is necessary to obtain the optimal timing of the control signal SX.  
         [0057]    The testing method of the first embodiment differs from the prior art testing method, which uses an EB tester, in that the testing may be executed after the FIB process has been carried out on the circuits of the device. Accordingly, the testing method of the first embodiment is performed efficiently and with high accuracy since the test is carried out with the protective film (e.g., polyimide) already applied to the circuit wires, which is the actual state of usage.  
         [0058]    The test is carried out by activating the switch circuits SW 1 -SW 4  when the first to fourth delay circuits  15 - 18  (capacitors C 1 -C 4 ) are disconnected from the signal wire LI. However, the test may also be carried out by activating the switch circuits SW 1 -SW 4  when the first to fourth delay circuits  15 - 18  (capacitors C 1 -C 4 ) are connected to the signal wire LI.  
         [0059]    (Second Embodiment)  
         [0060]    An FCRAM according to a second embodiment of the present invention will now be described with reference to FIGS.  4  to  6 .  
         [0061]    As shown in FIG. 4, the FCRAM includes a counter test circuit  90 . The counter test circuit  90  is provided with a refresh counter  40 , an address latch circuit  44 , and a mode setting circuit  48 .  
         [0062]    The refresh counter  40  is an n base counter including a plural number (n) of counter portions  40   a , which are connected to one another in series. The counter portions  40   a  output signals AD 1 -ADn, which are used to form an address value. Thus, the address value increases by one each time the first (initial stage) counter portion  40   a  receives a pulse signal.  
         [0063]    The first and second counter portions  40   a  are shown in FIG. 5. Each of the counter portions  40   a  directly receives a first control pulse signal SP 1  and a second control pulse signal SP 2 , which is obtained by inverting the first control pulse signal SP 1  with an inverter INV 4 . The first and second control pulse signals SP 1 , SP 2  are complementary signals.  
         [0064]    The first counter portions  40   a  each include first, second, and third CMOS inverter circuits  41 ,  42 ,  43 . The first CMOS inverter  41  has a PMOS transistor  41   a  and an NMOS transistor  41   b . A PMOS transistor T 3  and an NMOS transistor T 4  are connected between the PMOS and NMOS transistors  41   a ,  41   b . The PMOS transistor T 3  is activated and deactivated with the second control pulse signal SP 2 . The NMOS transistor T 4  is activated and deactivated with the first control pulse signal SP 1 . The first CMOS inverter circuit  41  is activated when the first control pulse signal SP 1  is high and deactivated when the first control pulse signal SP 1  is low. Further, the first CMOS inverter circuit  41  has an input terminal connected to the mode setting circuit  48  and an output terminal connected to the output terminal of the second CMOS inverter  42  and the input terminal of the third CMOS inverter circuit  43 .  
         [0065]    The second CMOS inverter  42  has an input terminal connected to the output terminal of the third CMOS inverter  43 . Thus, the second and third CMOS inverters  42 ,  43  form a latch circuit. The third CMOS inverter circuit  43  outputs a signal AD 1 .  
         [0066]    The second CMOS inverter  42  has a PMOS transistor  42   a  and an NMOS transistor  42   b . A PMOS transistor T 5 , activated and deactivated with the first control pulse signal SP 1 , is connected to the PMOS transistor  42   a . An NMOS transistor T 6 , activated and deactivated with the second control pulse signal SP 2 , is connected to the NMOS transistor  42   b . The second CMOS inverter circuit  42  is activated when the first control pulse signal SP 1  is low and deactivated when the first control pulse signal SP 1  is high.  
         [0067]    Therefore, when the first CMOS inverter circuit  41  is activated, the second CMOS inverter circuit  42  is deactivated, and when the first CMOS inverter circuit  41  is deactivated, the second CMOS inverter circuit  42  is activated.  
         [0068]    The second counter portion  40   a  has the same structure as the first counter portion  40   a , but differs in that the first control pulse signal SP 1  is provided to the PMOS and NMOS transistors T 3 , T 6  and the second control pulse signal SP 2  is provided to the PMOS and NMOS transistors T 4 , T 5 . Further, the second counter portion  40   a  receives the signal AD 1  from the first counter portion  40   a  and outputs a signal AD 2 . Odd order counter portions  40   a  have substantially the same structure as the first counter portion  40   a  and even order counter portions  40   a  have substantially the same structure as the second counter portion  40   a.    
         [0069]    Accordingly, the first and second counter portions  40   a  have a relationship as described below.  
         [0070]    When the first CMOS inverter circuit  41  of the first counter  40   a  is activated and the signal from the mode setting circuit  48  is being acquired, the first CMOS inverter circuit  41  of the second counter portion  40   a  is deactivated. Thus, the counter portion  40   a  of the second counter portion  40   a  does not acquire the signal acquired by the first counter portion  40   a . In this state, the second counter  40   a  provides the signal previously latched by the second and third CMOS inverter circuits  42 ,  43  to the third counter portion  40   a  (not shown).  
         [0071]    The first CMOS inverter circuit  41  of the first counter portion  40   a  is then deactivated and the first CMOS inverter circuit  41  of the second counter portion  40   a  is activated. This causes the second counter portion  40   a  to acquire the signal latched by the first counter portion  40   a . In this state, the signal latched by the second counter portion  40   a  is not acquired by the third counter portion  40   a  since the first CMOS inverter circuit  41  of the third counter portion (not shown) is deactivated.  
         [0072]    In this manner, the refresh counter  40  increases the address value, formed by the signals AD 1 -ADn, by one each time the refresh counter  40  receives the first control pulse signal SP 1 .  
         [0073]    With reference to FIG. 4, the address latch circuit  44  receives the signals AD 1 -ADn from the counter portions  40   a . The address latch circuit  44  further receives external address signals BD 1 -BDn and selects either the signals AD 1 -ADn or the external address signal BD 1 -BDn to output row address signals CA 1 -CAn.  
         [0074]    The address latch circuit  44  includes latch circuit portions  44   a , the number of which is the same as the number of the counter portions  40   a  of the refresh counter  40 . As shown in FIG. 6, each of the latch circuit portions  44   a  includes a first latch portion  45  which latches the external address signal BD 1 -BDn, a second latch portion  46  which latches the signals AD 1 -ADn, and a third latch portion  47  which latches the signal from the first and second latch portions  45 ,  46  and outputs the latched signal as the corresponding row address signal CA 1 -CAn.  
         [0075]    The first latch portion  45  includes two transfer gate circuits  45   a ,  45   b  and four inverters  45   c ,  45   d ,  45   e ,  45   f . The inverters  45   c ,  45   d  form a latch circuit. The input terminal of the latch circuit is connected to the transfer gate circuit  45   a . The output terminal of the latch circuit is connected to the transfer gate circuit  45   b.    
         [0076]    The transfer gate circuit  45   a  includes a PMOS transistor T 7  and an NMOS transistor T 8 . The PMOS transistor T 7  has a gate which receives a control pulse signal via the inverters  45   e ,  45   f . Since the phase of the control pulse signal is the same as that of a third control pulse signal SP 3 , the control pulse signal will be referred to as the third control pulse signal SP 3 . The NMOS transistor T 8  has a gate which receives a fourth control pulse signal SP 4  via the inverter  45   e . The third and fourth control pulse signals SP 3 , SP 4  are complementary signals.  
         [0077]    The transfer gate circuit  45   b  includes a PMOS transistor T 9  and an NMOS transistor T 10 . The PMOS transistor T 9  has a gate which receives the fourth control pulse signal SP 4  via the inverter  45   e . The NMOS transistor T 10  has a gate which receives the third control pulse signal SP 3  via the inverters  45   e ,  45   f.    
         [0078]    When the third control pulse signal SP 3  is low, the transfer gate circuit  45   a  is activated and the transfer gate circuit  45   b  is deactivated. If the third control pulse signal SP 3  is high, the transfer gate circuit  45   a  is deactivated and the transfer gate circuit  45   b  is activated.  
         [0079]    If the third control pulse signal SP 3  falls, the latch portion  45  of each latch circuit portion  44   a  receives the corresponding external address signal BD 1 -BDn and latches the external address signal BD 1 -BDn with the latch circuit formed by the inverters  45   c ,  45   d . When the third control pulse signal SP 3  rises, each latch portion  45  provides the latched corresponding external address signal BD 1 -BDn to the third latch portion  47 .  
         [0080]    The structure and operation of the second latch circuit  46  is substantially the same as the first latch circuit  45 . The second latch circuit  46  includes elements  46   a - 46   f which correspond to the elements  45   a - 45   f  of the first latch portion  45 , respectively. The inverter  46   e receives the first control pulse signal SP 1  and provides the second control pulse signal SP 2  to the transfer gate circuits  46   a ,  46   b.    
         [0081]    When the first control pulse signal SP 1  falls, the latch portion  46  of each latch circuit portion  44   a  receives the corresponding output signal AD 1 -ADn and latches the output signal AD 1 -ADn with the latch circuit formed by the inverters  46   c ,  46   d . When the first control pulse signal SP 1  rises, the latched signal AD 1 -ADn is provided to the third latch portion  47 .  
         [0082]    The third latch portion  47  includes two inverters  47   a ,  47   b  which form a latch circuit. If the third latch portion  47  receives the corresponding external address signal BD 1 -BDn from the first latch portion  45 , the third latch portion  47  outputs the external address signal BD 1 -BDn as the corresponding row address signal CA 1 -CAn. Further, if the third latch portion  45  receives the signal AD 1 -ADn from the second latch portion  46 , the third latch portion  47  outputs the signal AD 1 -ADn as the corresponding row address signal CA 1 -CAn.  
         [0083]    The mode setting circuit  48 , which controls the selection operation of the address latch circuit  44 , will now be described with reference to FIG. 4. The mode setting circuit  48  includes a first NAND circuit  49  and a second NAND circuit  51 . The signal from the first NAND circuit  49  is provided to the refresh counter  40  and the address latch circuit  44  via an inverter  50  as the first control pulse signal SP 1 .  
         [0084]    The first NAND circuit  49  has two input terminals, an address control input terminal and a counter test control input terminal. The address control input terminal is provided with a pulse signal PS, which is generated when the DRAM receives a write command or a read command. The counter test control input terminal is provided with a mode signal MS. The mode signal MS is low in a normal operation mode and high when the counter test operation or refresh operation is being performed.  
         [0085]    If the mode signal MS is low (normal operation), the first control pulse signal SP 1  remains low regardless of the level of the pulse signal PS. If the mode signal MS is high (counter test operation or refresh operation), the first control pulse signal SP 1  having the same phase as the pulse signal PS is generated each time the pulse signal PS is provided.  
         [0086]    The second NAND circuit  51  has an input terminal which receives the pulse signal PS and another input terminal which receives the mode signal MS via an inverter  53 . The signal output by the second NAND circuit  51  is provided to the address latch circuit  44  as the third control pulse signal SP 3  via an inverter  52 .  
         [0087]    If the mode signal MS is low (normal operation), the third control pulse signal SP 3  having the same phase as the pulse signal PS is generated each time the pulse signal PS is provided. If the mode signal MS is high (counter test operation or refresh operation), the third control pulse signal SP 3  remains low regardless of the level of the pulse signal PS.  
         [0088]    The operation of the counter test circuit  90  will now be described.  
         [0089]    When performing the counter test of the refresh counter  40  using a testing apparatus, a high mode signal MS is provided to the mode setting circuit  48  by the testing apparatus.  
         [0090]    The mode setting circuit  48  receives a pulse signal PS at the counter test control input terminal in response to a write command from the testing apparatus. This causes the inverter  50  to provide the first control pulse signal SP 1 , which phase is the same as the pulse signal PS, to the refresh counter  40 . The third control pulse signal SP 3  output by the inverter  52  remains low regardless of the level of the pulse signal PS.  
         [0091]    The counter portions  40   a  of the refresh counter  40  increase the signals AD 1 -ADn, or the address value, by one in response to the first control pulse signal SP 1 . Since the third control pulse signal SP 3  remains low and the transfer gate circuit  45   b  is deactivated, the first latch portions  45  of the address latch circuit  44  do not provide the third latch portions  47  with the corresponding external address signals BD 1 -BDn even when receiving the external address signals BD 1 -BDn.  
         [0092]    The second latch portions  46  of the address latch circuit  44  latches the counted signals AD 1 -ADn (i.e., address value) in response to the first control pulse signal SP 1 . Further, the second latch portions  46  provide the associated third latch portions  47  with the corresponding latched signal AD 1 -ADn and do not acquire the signals AD 1 -ADn until the next first control signal SP 1  is generated.  
         [0093]    Subsequently, if the mode setting circuit  48  receives the pulse signal PS at the counter test input terminal in response to a new write command, the counter portions  40   a  increase the corresponding signals AD 1 -ADn (i.e., address value) by one in response to the first control pulse signal SP 1 . Further, the second latch portions  46  latch the counted signals AD 1 -ADn in response to the first control pulse signal SP 1  and provide the signals AD 1 -ADn to the associated third latch portions  47 .  
         [0094]    In the same manner, the counter portions  40   a  continues to increase the signals AD 1 -ADn (address value) by one in response to new write commands and output the signals AD 1 -ADn via the associated second and third latch portions  46 ,  47  as the row addresses CA 1 -CAn.  
         [0095]    When the signals AD 1 -ADn (address value) from the refresh counter  40  reach the final value (i.e., when test data is written on the cells corresponding to all of the addresses), a read command is provided to the FCRAM from the testing apparatus. In other words, the test data written on every cell in accordance with the preceding write commands is inspected.  
         [0096]    If the mode setting circuit  48  is provided with a pulse signal PS at the counter test control input terminal in response to the read command, the inverter  50  provides the first control pulse signal SP 1  to the refresh counter  40 . In this state, the control portions  40   a  return to the initial address value (signals AD 1 -ADn), or the value when the count operation began in response to the first write command. The initial signals AD 1 -ADn are latched by the second latch portions  46  of the address latch circuit  44  and provided to the third latch portions  47 . In other words, the row address of the cell on which data was written by the first write command is designated and the data of that cell is read.  
         [0097]    In the same manner, the counter portions  40   a  continue to increase the signals AD 1 -ADn (address value) one at a time in response to new read commands and output the signals AD 1 -ADn as the row address signals CA 1 -CAn via the second and third latch portions  46 ,  47 .  
         [0098]    When the signals AD 1 -ADn from the refresh counter  40  reach the final value (i.e., when the test data written on the cells corresponding to all of the addresses is read), the testing apparatus completes the counter test.  
         [0099]    The FCRAM, which acquires the row address and the column address simultaneously with the read/write command, performs the counter test in the same manner as the conventional SDRAM.  
         [0100]    The address value is counted accurately by the write command which writes the test data and the read command which reads the test data. Thus, the counter test performed on the FCRAM is efficient and accurate.  
         [0101]    In addition, when the writing of the test data on every cell is completed (i.e., when the refresh counter  40  completes one cycle), a read command immediately starts the read process. Consequently, the counter test is performed more efficiently than in the prior art.  
         [0102]    The refresh operation is performed in the same manner as the read operation and the write operation except that the high mode signal MS and the pulse signal PS are not generated by the testing apparatus.  
         [0103]    Normal operation of the FCRAM will now be described. A normal external command from an FCRAM controller, which serves as an external device, causes a low mode signal MS to be provided to the first and second NAND circuits  49 ,  51  of the mode setting circuit  48 .  
         [0104]    A write command from the FCRAM controller causes the pulse signal PS to be provided to the mode setting circuit  48  at the counter test control input terminal. This results in the output of the third control pulse signal SP 3 , which phase is the same as the pulse signal PS, by the inverter  52 . The first control pulse signal SP 1  from the inverter  50  remains low regardless of the level of the pulse signal PS.  
         [0105]    Since the first control pulse signal SP 1  remains low, the counter portions  40   a  do not perform the count operation. Furthermore, since the first control pulse signal SP 1  remains low, the second latch portions  46  of the address latch circuit  44  do not latch the signals AD 1 -ADn (address value) from the counter portions  40   a  of the refresh counter  40  and provide the signals AD 1 -ADn to the third latch portions  47 .  
         [0106]    The first latch portions  45  of the address latch circuit  44  latch the external address signals BD 1 -BDn based on the address data acquired together with the write command in response to the third control pulse signal SP 3 . The first latch portions  45  provide the latched external address signals BD 1 -BDn to the third latch portions  47 . The third latch portions  47  output the external address signals BD 1 -BDn as the row address signals CA 1 -CAn.  
         [0107]    (Third Embodiment)  
         [0108]    An FCRAM  200  according to a third embodiment of the present invention will now be described with reference to FIG. 7. The FCRAM of the third embodiment is provided with an auto precharge function.  
         [0109]    As shown in FIG. 7, the FCRAM  200  includes an auto precharge stopping circuit  100 , an internal circuit  72 , and a sense amplifier  73  connected between a bit line BL and a bit line /BL. The FCRAM  200  is connected to a burn-in testing apparatus  71 .  
         [0110]    The internal circuit  72  is provided with a read/write control circuit  61  which controls the sense amplifier  73 . The internal circuit  72  receives a test command from the testing apparatus  71  and provides internal test command signals and a sense amplifier control signal SAC to the auto precharge stopping circuit  100 . The internal circuit  72  generates an internal test command signal when receiving a test command for stopping unnecessary auto precharge.  
         [0111]    The auto precharge stopping circuit  100  includes a read/write control circuit  61  arranged in the internal circuit  72 , a test mode setting circuit  62 , a NOR circuit  63  connected to the test mode setting circuit  62  and the read/write control circuit  61 , an inverter  64  connected to the NOR circuit  63 , and a precharge control circuit  65 .  
         [0112]    The read/write control circuit  61  generates a high sense amplifier control signal SAC when operating the sense amplifier  73  and a low sense amplifier signal SAC when terminating the operation of the sense amplifier  73 . The read/write control circuit  61  provides the low sense amplifier control signal SAC to the NOR circuit  63  for a predetermined time. More specifically, the read/write control circuit  61  generates a low sense amplifier control signal SAC for a predetermined period after the operation of the sense amplifier  73  is completed during a read or write operation. The read/write control circuit  61  receives a signal indicating that the sense amplifier has completed amplification (e.g., a column selection signal) and generates a low sense amplifier control signal SAC.  
         [0113]    The test mode setting circuit  62  provides a mode signal MS 3  to the NOR circuit  63 . More specifically, the test mode setting circuit  62  receives the internal test command signal generated by the internal circuit  72  in accordance with the command provided from the testing apparatus  71  when the DRAM is being tested. Upon receipt of the internal test command signal, the test mode setting circuit  62  generates a high mode signal MS 3 . If the testing is not being performed with the testing apparatus  100 , the test mode setting circuit  62  generates a low mode signal MS 3 , since the internal test command signal is not received.  
         [0114]    The NOR circuit  63  receives the signal SAC from the read/write control circuit  61  and the signal MS 3  from the test mode setting circuit  62  and provides a precharge control signal CPR to the precharge control circuit  65  via the inverter  64 .  
         [0115]    When the mode signal MS 3  is low (i.e., when in a mode other than the test mode), the phase of the precharge control signal CPR is the same as that of the sense amplifier control signal SAC. Thus, if a low sense amplifier control signal SAC is provided to the NOR circuit  63  for a predetermined time, the precharge control signal CPR is also low for the predetermined time. If the mode signal MS 3  is high (i.e., when in the test mode), the precharge control signal CPR remains high regardless of the level of the sense amplifier control signal SAC.  
         [0116]    The precharge control circuit  65  provides a precharge signal PR to the internal circuit  72  in response to the precharge control signal CPR. The precharge control signal CPR is inverted to obtain the precharge signal PR. When the precharge signal PR is high (i.e., when the sense amplifier control signal SAC is low), the internal circuit  72  activates a precharge circuit (not shown) to precharge the bit lines BL, /BL.  
         [0117]    With reference to FIG. 8, the test mode setting circuit  62  includes a NOR circuit  75  and an inverter  76  which are connected in series to each other. The NOR circuit  75  has a plurality of input terminals which receive a plurality of internal command signals. When the NOR circuit  75  receives an internal command for stopping unnecessary precharge, the NOR circuit  75  provides a low signal to the inverter  76 . The inverter  76  inverts the signal from the NOR circuit  75  and provides the inverted signal as the mode signal MS 3  to the NOR circuit  63 .  
         [0118]    As shown in FIG. 9, the precharge control circuit  65  includes a delay circuit  77 , a high pulse generating circuit  82 , and an inverter  87  which are connected to one another in series.  
         [0119]    The delay circuit  77  includes four inverters  78 ,  79 ,  80 ,  81  which are connected to one another in series. The high pulse signal generating circuit  82  includes a NAND circuit  86  and three inverters  83 ,  84 ,  85 . The NAND circuit  86  has an input terminal which receives a signal from the inverter  81  and a further input terminal which receives a signal from the inverter  81  via inverters  83 - 85 . The NAND circuit  86  output is connected to the inverter  87 , which then outputs the precharge signal PR.  
         [0120]    The operation of the auto precharge stopping circuit will now be described.  
         [0121]    The burn-in test performed on the FCRAM  200  will first be described. In order to initiate the burn-in test, the test mode setting circuit  62  provides a high mode signal MS 3  to the NOR circuit  63  in accordance with an external command from the testing apparatus  71 .  
         [0122]    During the burn-in test, the FCRAM  200  performs the write operation and the read operation with a clock cycle of several hundred microseconds, which is longer than the normal clock cycle. The read/write control circuit  61  provides a low sense amplifier control signal SAC to the NOR circuit  63  over a predetermined time whenever the sense amplifier  73  is deactivated.  
         [0123]    In this state, the NOR circuit  63  keeps the precharge control signal CPR high regardless of the low sense amplifier control signal SAC due to the high mode signal MS 3  received from the test mode setting circuit  62 . In other words, the test mode setting circuit  62  provides the high mode signal MS 3  to the NOR circuit  63  to invalidate the sense amplifier control signal SAC.  
         [0124]    Accordingly, in contrast to prior art FCRAMs, the FCRAM  200  is prevented from being maintained in a precharge state during most of the testing period, even though the clock cycle is extremely long. As a result, the burn-in test is performed efficiently and with high accuracy.  
         [0125]    During a normal usage state (when not in the test mode), the test mode setting circuit  62  provides a low mode signal MS 3  to the NOR circuit  63 . The read/write control circuit  61  provides a low sense amplifier control signal SAC to the NOR circuit  63  for a predetermined time whenever operation of the sense amplifier  73  is completed. Thus, the precharge control circuit  65  provides a high precharge signal PR to the internal circuit  72  in response to the precharge control signal CPR, which phase is substantially the same as the sense amplifier control signal SAC. In other words, precharge is performed automatically whenever the read operation or the write operation is performed.  
         [0126]    The precharge operation may be prohibited not only during the burn-in test but also when testing the refresh counter during the counter test. Furthermore, the auto precharge may be prohibited when tests that do not require auto precharge are performed.  
         [0127]    The timing adjustment circuit  10  of the first embodiment, the counter test circuit  90  of the second embodiment, and the auto precharge stopping circuit  100  of the third embodiment may be combined in various ways in the FCRAM, as will be understood by those of skill in the art.  
         [0128]    The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.