Abstract:
A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

Description:
RELATED APPLICATIONS/PATENT 
     This application is a divisional of U.S. patent application Ser. No. 10/057,162, filed Jan. 24, 2002, now U.S. Pat. No. 6,623,987 entitled PASSIVATED MAGNETO-RESISTIVE BIT STRUCTURE AND PASSIVATION METHOD THEREFOR, which is a divisional of U.S. patent application Ser. No. 09/638,419, filed Aug. 14, 2000, entitled “PASSIVATED-MAGNETO-RESISTIVE BIT STRUCTURE AND PASSIVATION METHOD THEREFOR,” now U.S. Pat. No. 6,392,922, the entireties of which are hereby incorporated by reference. This application is also related to U.S. application entitled “PASSIVATED MAGNETO-RESISTIVE BIT STRUCTURE,” with Ser. No. 10/078,234, filed on Feb. 14, 2002, now U.S. Pat. No. 6,806,546, the entirety of which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates to magneto-resistive memories, and more particularly, to the passivation of magneto-resistive bit structures. 
     Typical magneto-resistive memories such as giant magneto-resistive random access memory cells (GMR MRAM&#39;s) use variations in the magnetization direction of a thin film of ferromagnetic material in a GMR stack can be referred to as a magneto-resistive bit. During a write operation, the magnetization direction of a selected bit is set by passing an appropriate current near the bit, often using a word line, digital line, or sense line. The current produces a magnetic field that sets the magnetization direction of at least one of the layers in the ferromagnetic film in a desired direction. The magnetization direction dictates the magneto-resistance of the film. During a subsequent read operation, the magneto-resistance of the film can be read by passing a sense current through the bit structure via a sense line or the like. 
     Some prior art magneto-resistive bit structures are shown and described in U.S. Pat. No. 4,731,757 to Daughton et al. and U.S. Pat. No. 4,780,848 to Daughton et al., both of which are assigned to the assignee of the present invention and both of which are incorporated herein by reference. Illustrative processes for forming such magnetic bit structures are shown and described in U.S. Pat. No. 5,496,759 to Yue et al., and U.S. Pat. No. 5,569,617 to Yeh et al., both of which are assigned to the assignee of the present invention and both of which are incorporated herein by reference. 
     Such magneto-resistive memories are often conveniently provided on the surface of a monolithic integrated circuit to provide easy electrical interconnection between the bit structures and the memory operating circuitry on the monolithic integrated circuit. To provide a sense current through the bit structure, for example, the ends of the bit structure are typically connected to adjacent bit structures through a metal interconnect layer. The string of bit structures then forms a sense line, which is often controlled by operating circuitry located elsewhere on the monolithic integrated circuit. 
     A problem which arises as a result of the use of magneto-resistive memories is that conventional integrated circuit processes often cannot be used to form the contact holes or vias that are used to provide connections to the bit structure. For example, in a conventional integrated circuit process, vias are often formed by means of an etching process. First, a patterned photoresist layer, which defines the location and size of the vias, is provided over the integrated circuit. With the photoresist layer in place, vias are etched down to the bit structure. Once the vias are etched, a photoresist removal step typically is used to remove the photoresist layer. 
     In a typical integrated circuit back-end process the GMR bit ends are susceptible to damage by the corrosive chemicals used in the etching process. Furthermore, GMR bit ends may be exposed to a plasma environment with oxygen during removal of the photoresist in the oxygen asher process and are left unpassivated thereafter. Oxidation of the side walls of the bit ends can lead to significant degradation and adversely affect performance of the GMR MRAM&#39;s. In order to avoid potential disastrous consequences, oxygen plasma photoresist removal is not generally utilized as the post Permalloy via etch or subsequent M3 etch stages. Instead, various solvent photoresist strip process are utilized to remove the photoresist layers. Where a solvent or “wet” photoresist strip is used, it is necessary to choose the solvent with extreme care and to limit solvent use to mild solvents. In general, wet photoresist strips, although reducing the risk of oxidation, are prone to other defects and are not very production-worthy. 
     What would be desirable, therefore, is a magneto-resistive bit structure which is not subject to oxidation or corrosion by processing steps when forming vias. More specifically, it would be desirable to form a magneto-resistive bit structure without directly exposing the side walls of the bit ends to the potentially adverse effects of processes involved in via formation. This may allow more efficient and reliable back-end processing, which, in turn may reduce the defect density and increase the overall performance of devices incorporating magneto-resistive memories. 
     SUMMARY OF THE INVENTION 
     The present invention overcomes many of the disadvantages of the prior art by providing a magneto-resistive bit structure wherein the bits are protected from the potentially adverse effects of process steps that could damage the unprotected bit structure. 
     In one embodiment of the invention, magneto-resistive bits are encapsulated by means of an etch stop barrier material, such as CrSi, which is deposited as a barrier to cover both the top surface and side walls of a GMR stack. Encapsulation of GMR cells is highly desirable in the switching characteristics of the cells. The etch stop barrier material, preferably CrSi, provides a good barrier to oxygen and corrosive chemicals and thereby improves the robustness of GMR cells. It is selected to have a bulk resistivity which is low enough to allow sense line contact and high enough so that shunting will be negligible. 
     In another embodiment of the present invention, an etch stop barrier layer, for example, a layer of CrSi protects the top of the GMR stack while the side walls are protected by means of a dielectric extending along the edges of the GMR stack. For example, a SiN spacer can be formed by means of a controlled Permalloy via etch. 
     Metals deposited upon the passivated bit structure contact the bit ends only from the top through the etch stop layer, while the side walls of the bit ends are insulated from the metal by the dielectric spacer. 
     Passivation of magneto-resistive bit structures by the methods of this invention significantly improves the repeatability of GMR cells and makes the GMR back-end process more production-worthy. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects of the present invention and many of the attendant advantages thereof will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designated like parts throughout the figures thereof and wherein: 
         FIG. 1  is a plan view, partly in phantom, of one illustrative embodiment of the passivated magneto-resistive bit structures of the present invention; 
         FIG. 2  is a plan view showing sense line metal contacts on top of the passivated magneto-resistive bit structure shown in  FIG. 1 ; 
         FIGS. 3 to 10  are cross-sectional views showing certain of the steps of a process for forming a passivated magneto-resistive bit structure according to one embodiment of the present invention; and 
         FIGS. 11 to 15  are cross-sectional views showing certain of the steps of a process for forming the passivated magneto-resistive bit structure according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
       FIG. 1  is a plan view of an illustrative embodiment of the present invention. An array of passivated magneto-resistive bit structures are shown generally at  2 . A passivating material  4  is deposited on top of magneto-resistive bit  6 , shown in phantom.  FIG. 2  is similar to  FIG. 1  with sense line metal contacts  8  deposited on top of passivating material  4 , which is at least partially conductive. 
     A process for forming a passivated magneto-resistive bit structure according to a preferred embodiment of the present invention will now be illustrated by reference to  FIGS. 3 to 10 . 
     Referring to  FIG. 3 , a GMR stack  32  is shown deposited upon a SiN substrate  30 , which may be a 500 Å SiN layer. Alternatively, substrate  30  may be a monolithic integrated circuit or an integrated circuit separated from GMR stack layer  32  by a dielectric layer. A SiN layer  34  is deposited upon GMR stack  32 . SiN layer  34  may be an 800 Å SiN layer. 
     In the next step of the process, an ion mill mask is built upon GMR stack  32  using the SiN layer  34 .  FIG. 4  shows ion mill mask  34   a  formed from SiN layer  34 . Part of SiN layer  34  is etched away by reactive ion etching. 
     In the next step of the process, ion milling is used to pattern GMR stack  32 .  FIG. 5  shows a patterned GMR stack  32   a  resulting from this step, in which ion mill mask  34   a  is removed as well as part of GMR stack layer  32 . 
     The next step in the overall process is the deposition of a barrier layer, which, after patterning, serves as the encapsulant in this embodiment of the present invention. As a barrier layer any etch stop material can be used which has a bulk resistivity low enough to allow sense line contact and high enough so that shunting will be negligible. CrSi is preferred. If desired, a thin Ta or TaN diffusion barrier can be deposited between the above-described barrier layer and the GMR stack to prevent intermixing.  FIG. 6  shows a barrier layer  36 , made up of a 300 Å CrSi layer on a 100 Å Ta layer, deposited upon patterned GMR stack  32   a  and SiN substrate  30 . 
     Following the Ta/CrSi barrier layer deposition a dielectric layer is deposited upon barrier layer  36 . Any dielectric can be used. SiO 2  or SiN is preferred.  FIG. 7  shows a 1000 Å SiO 2  layer  38  deposited upon Ta/CrSi barrier layer  36 . 
     Following deposition of SiO 2  layer  38 , in the next step, shown in  FIG. 8 , a part of dielectric layer  38  is removed by reactive ion etch to expose the unwanted portions of Ta/CrSi barrier layer  36 , resulting in patterned dielectric layer  38   a.    
     With the unwanted portions of the Ta/CrSi barrier layer  36  exposed, ion milling is utilized to remove the unwanted portions of the Ta/CrSi barrier layer  36 .  FIG. 9  shows pattern Ta/CrSi barrier layer  36   a  resulting from this step as well as a residual SiO 2  layer  38   b . Patterned SiO 2  layer  38   a  in  FIG. 8  has been reduced in thickness as a result of the ion milling step to result in residual SiO 2  layer  38   b  having a thickness of 400 Å. 
     Finally, as shown in  FIG. 10  residual SiO 2  layer  38   b  from  FIG. 9  is removed by reactive ion etch, resulting in GMR stack  32   a  being fully encapsulated by Ta/CrSi barrier  36   a . Thus, a passivated magneto-resistive bit structure is provided by encapsulation of the GMR stack by means of a Ta/CrSi barrier. Both the tops and the side walls of the GMR bits are protected by passivation in the manner described above. The side walls of the GMR bits are not exposed either during Permalloy via etch or thereafter. Therefore, oxygen asher photoresist removal and conventional wet chemical strips can be used without damage to the passivated GMR bits. 
     An alternative embodiment of the present invention will now be illustrated in reference to  FIGS. 11 to 15 . Referring to  FIG. 11 , an underlayer  40 , which may be a monolithic integrated circuit, serves as a substrate for a GMR stack  42 . Underlayer  40  preferably includes a dielectric layer separating the GMR stack from an integrated circuit. The dielectric layer may be, for example, a 500 Å seed SiN layer, not shown. A CrSi barrier layer  44  is deposited on top of GMR stack  42 . A SiN ion mill mask  46  is fabricated in a known manner on top of CrSi layer  44 . For example, a relatively thick SiN layer can be deposited upon CrSi layer  44  and patterned using a photoresist and reactive ion etch. Layer  44  may, for example, be an 800 Å thick CrSi layer. CrSi is preferred because, in addition to being a good oxygen barrier and etch stop, CrSi has a bulk resistivity low enough to allow sense line contact and high enough to minimize shunting. Ion mill mask  46  may be a 2000 Å SiN layer. Other suitable dielectric materials such as SiO 2  can be used, if desired. SiN is preferred because, in addition to being an excellent dielectric, it provides an efficient barrier against oxidation and protects GMR bits from other damaging materials as well. 
     The next steps in the process is illustrated in  FIG. 12 , wherein the results of ion milling are shown. It can be seen that portions of CrSi layer  44  and portions of GMR stack  42  have been removed, resulting in patterned GMR stack  42   a  and patterned CrSi barrier layer  44   a . The ion mill mask is then separately removed. As shown, CrSi layer  44   a  has been reduced from a thickness of 800 Å to a remaining thickness of 700 Å. 
     The next step in the process is deposition of a layer of a dielectric material, such as a 2000 Å layer of SiN or SiO 2 , followed by planarization, such as by using high angle ion milling or chemical mechanical polishing (CMP).  FIG. 13  shows a planarized layer of SiN  48  deposited upon the structure of  FIG. 12 . 
     The next process step is a controlled Permalloy via etch, the results of which are illustrated in  FIG. 14 . In this step most of the SiN layer  48  is removed, leaving naturally created SiN passivation spacers  48   a  along the side walls  42   b  of patterned GMR stack  42   a  and providing a passivated magneto-resistive bit structure. Spacers  48   a  are shown abutting the side walls  42   b  of patterned GMR stack  42   a  and the side walls  44   b  of patterned CrSi layer  44   a . Spacers  48   a  are shown having side walls  48   b , which are spaced out laterally from the side walls  42   b  of GMR stack  42   a  and side walls  44   b  of patterned CrSi layer  44   a.    
     In  FIG. 15  a contact metal  50  is deposited over the passivated magneto-resistive bit structure of  FIG. 14 . Contact metal  50  does not contact GMR stack  42   a  directly at any point, since the side walls  42   b  of GMR stack  42   a  are protected by spacers  48   a  and the top of GMR stack  42   a  is protected by CrSi layer  44   a . Indirect contact between GMR stack  42   a  and contact meal  50  is possible only at the top of GMR stack  42   a  through CrSi layer  44   a , which conducts electric current between contact metal  50  and GMR stack  42   a . The SiN spacers provide an excellent barrier against oxidation and contact by corrosive chemicals. 
     Having thus described the preferred embodiments of the present invention, those of skill in the art will readily appreciate that yet other embodiments may be made and used within the scope of the claims hereto attached. Numerous advantageous of the invention covered by this document have been set forth in the foregoing description. It will be understood, however, that this disclosure is, in many respects, only illustrative. Changes may be made in details, particularly in matters of shape, size, and arrangement of parts without exceeding the scope of the invention.