Abstract:
A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state.

Description:
BACKGROUND 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to random access memory (RAM). More particularly, the present invention relates to RAM blocks suitable for use in field programmable gate array (FPGA) architectures. 
         [0003]    2. The Prior Art 
         [0004]    Modern FPGAs generally contain blocks of RAM. Each RAM block has address and data inputs, data outputs, a write enable input and often also a read enable input. When read enable is deasserted, the outputs of the RAM block are held in the previous state. This avoids adding any delay to the read path, or consuming dynamic power to disable it. Deasserting read enable may also be used to power down some circuitry, such as sense amplifiers. 
         [0005]    Since the RAM blocks in an FPGA of necessity have a fixed capacity, customers who need higher RAM capacity must gang multiple RAM blocks together. For instance, an FPGA may provide RAM blocks capable of storing 8 Kbits in either a 4K-word×2-bit or 1K-word×8-bit format. In a design to be programmed into the FPGA that requires a RAM that is arranged as 4K words×8 bits, it is required that four RAM blocks be combined. 
         [0006]    One way to combine RAM blocks to achieve the desired capacity is to configure the four blocks in 4K-word×2 bit format, with each block producing 2 of the 8 output bits. This provides the minimal delay as no extra logic is required in the speed path. However since all RAM blocks must be enabled for every read operation, the dynamic power will be that of four RAM blocks. 
         [0007]    An alternative way to combine RAM blocks to achieve the desired capacity is shown in  FIG. 1 , which is generally preferred in low power applications. Composite RAM block  10  is configured from RAM blocks  12 ,  14 ,  16 , and  18 , each block arranged in 1K-word×8-bit format. RAM blocks  12 ,  14 ,  16 , and  18  share address bits A0-A9. Additional address bits A10 and A11 are then used as the select inputs of an 8-bit wide 4-input multiplexer  28  which selects the output of one of the RAM blocks  12 ,  14 ,  16 , and  18  to be used. To save power, each block can be enabled only when the corresponding values of A10 and A11 are present. This is achieved by means of AND gates  20 ,  22 ,  24  and  26 . AND gates  20 ,  22 ,  24 , and  26  are “soft gates” created by programming the programmable logic resources in the FPGA as is known in the art. Table 1 shows the combinations of address inputs A10 and A11 that enable the individual ones of RAM blocks  12 ,  14 ,  16 , and  18 . 
         [0000]    
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 A10 
                 A11 
                 RAM Block Enabled 
               
               
                   
               
             
             
               
                 0 
                 0 
                 RAM Block 12 
               
               
                 0 
                 1 
                 RAM Block 14 
               
               
                 1 
                 0 
                 RAM Block 16 
               
               
                 1 
                 0 
                 RAM Block 18 
               
               
                   
               
             
          
         
       
     
         [0008]    The total dynamic power in the configuration shown in  FIG. 1  is thus the same as the power consumed if only one of the blocks was present in the design, but some additional delay in the speed path is incurred due to the insertion of one of AND gates  20 ,  22 ,  24 , and  26  to decode A10 and A11 to produce the enable signal for each of RAM blocks  12 ,  14 ,  16 , and  18 . Another delay is incurred by the 4-input multiplexer  28  positioned to pass only the output of the enabled one of RAM blocks  12 ,  14 ,  16 , and  18 . Another disadvantage is that the additional logic (AND gates  20 ,  22 ,  24 ,  26  and multiplexer  28 ) must be provided by programming soft gates in the FPGA. 
         [0009]    The prior art circuit of  FIG. 1  is similar to one shown in Tessier, Betz, Neto, Gopalsamy,  Power - aware RAM Mapping for FPGA Embedded Memory Blocks , Int&#39;l Symp. FPGAs, 2006, pp. 189-198. 
         [0010]    U.S. Pat. No. 6,049,487 discloses and claims RAM arrays having multiple read enables, but only in combination with tristate outputs and an output enable scheme. Tri-state signals are disadvantageous in state-of-the-art FPGAs due to their greater complexity and the possibility of conflicting drivers. 
       BRIEF DESCRIPTION 
       [0011]    A random-access memory block for a field programmable gate array includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are provided. Hardwired decoding logic inside the RAM block is coupled to the at least two programmably invertible enable inputs to selectively enable the random-access memory array. A gate is coupled to the output of the random-access memory array and is configured to pass the output of the random-access memory array only if the random-access memory is enabled for a read operation, and otherwise generate a preselected logic state. 
         [0012]    According to one aspect of the present invention, a random-access memory block includes a random-access memory array having address inputs, a data input, a data output and including a plurality of storage locations. At least two programmably invertible enable inputs are each coupled to a different memory address line. Hardwired decoding logic inside the RAM block is coupled to the programmably invertible enable inputs. A block-enable register is coupled to the output of the decoding logic. A data-input register is coupled to the data input of the random-access memory array. A memory address register has inputs coupled to an address bus and outputs coupled to the address inputs of the random-access memory array. A gate is coupled to the output of the block-enable register, the output of a write-enable register (if desired) and the output of the random-access memory array. 
         [0013]    According to another aspect of the present invention, a method for operating a random access memory in a field programmable gate array includes enabling the random access memory block only when it is uniquely selected and a read operation is requested, and generating output data at an output of the random access memory block only when it is uniquely selected and a read operation is requested, otherwise generating a preselected logic state at the output of the random access memory block. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0014]      FIG. 1  is a diagram illustrating a typical prior-art ganged RAM block arrangement. 
           [0015]      FIG. 2  is a diagram showing an illustrative ganged RAM block arrangement in accordance with one aspect of the present invention. 
           [0016]      FIG. 3  is a logic diagram showing one illustrative way of selectively inverting the logic value present on either of two address inputs to the RAM block. 
           [0017]      FIG. 4  is a logic diagram showing one illustrative way of forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. 
           [0018]      FIG. 5  is a logic diagram showing another illustrative way of forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. 
           [0019]      FIG. 6  is a logic diagram showing another illustrative way of forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. 
           [0020]      FIG. 7  is a logic diagram showing an illustrative way of choosing between holding outputs of a RAM block at the previous values and forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0021]    Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
         [0022]    Modern FPGAs generally contain RAM blocks. Since the RAM blocks each have a fixed capacity, customers who need higher-capacity RAMs must gang multiple RAM blocks together. The object of this invention is to allow this to be done in a manner that is power efficient yet with minimal delay through the RAM with any required soft gates implemented in the surrounding programmable logic. 
         [0023]    Referring now to  FIG. 2 , a diagram shows an illustrative embodiment of the present invention. Composite RAM block  30  is configured from RAM blocks  32 ,  34 ,  36 , and  38 , each block arranged in 1K-word×8-bit format. RAM blocks  32 ,  34 ,  36 , and  38  share address bits A0-A9. Additional address bits A10 and A11 are used as select inputs to choose one of the RAM blocks  32 ,  34 ,  36 , and  38  to be used by driving its enable input. To save power, each block is enabled only when the corresponding values of A10 and A11 are present. 
         [0024]    The present invention as shown in  FIG. 2  has a combination of features. Multiple enable inputs, e.g., N=2 in  FIG. 2 , are provided on each RAM block  32 ,  34 ,  36 , and  38 . The enable inputs are logically combined (e.g., ANDed together as shown in  FIG. 1 ) with dedicated hardwired logic within the block instead of using decoding logic formed from programmed soft gates. There is a programmable inversion on each enable input, indicated by bubbles at en0 and en1 of RAM block  32 , en1 of RAM block  34 , and en0 of RAM block  36  of  FIG. 2 . This way, up to 2N blocks can be ganged together without requiring relatively slow soft gates to decode the N high-order address bits to provide a block enable signal. 
         [0025]    According to another aspect of the present invention, instead of holding the previous output values when a block is disabled, or tristating them, as in prior-art FPGA RAM block designs, the output values are forced to a known logic state, for example all zero. By doing this, the 2N-input multiplexer of the RAM block of  FIG. 1  can be replaced with a 2N-input OR gate  40 . An OR gate is generally realizable in fewer soft logic elements and with less delay than a multiplexer having the same number of inputs. For example, two 4-input lookup tables (LUTs) are required to implement a 4-input multiplexer, while only one 4-input LUT is required to implement the 4-input OR gate shown as an example in  FIG. 2 . The number of levels of LUT in the speed path is also reduced from two to one in this example, since an OR gate only exhibits a single LUT level whereas a multiplexer exhibits a two level LUT. 
         [0026]    These two features of the RAM block of the present invention may slightly increase the delay of a single RAM block used in isolation as compared to a stand-alone RAM block. But, as will be appreciated by persons of ordinary skill in the art, employing these features will eliminate at least an entire level of soft logic when RAMs are ganged together as contemplated by the present invention. 
         [0027]    Referring now to  FIG. 3 , a logic diagram shows one illustrative circuit  50  that may be used to selectively invert the logic value present on either of two address inputs to the RAM block. In the illustrative example shown in  FIG. 3 , address inputs A10 and A11 are provided to the en0 and en1 inputs of circuit  50  located in RAM bock  52  (as indicated by the dashed line). Persons of ordinary skill in the art will appreciate that the circuit of  FIG. 3  is illustrative and not limiting, and that other known circuitry may be used to selectively invert the address bits appearing at enable inputs en0 and en1. 
         [0028]    A first hardwired XOR gate  54  has one of its inputs coupled to address line A10 at input en0 of RAM block  52  and the other one of its inputs coupled to a configuration signal invert0. A second hardwired XOR gate  56  has one of its inputs coupled to address line A11 at input en1 of RAM block  52  and the other one of its inputs coupled to a configuration signal invert1. Depending on which RAM block the RAM block  52  is designated as in a ganged RAM block arrangement according to the present invention, neither, either or both of inputs invert0 and invert1 may be set to invert the logic level at neither, one, or both address inputs A10 and A11 as shown in Table 1. If the input invert0 (or input invert1) is set to logic zero, the input at the respective enable input en0 or en1 passes uninverted through XOR gate  54  (or  56 ). If, on the other hand, the input invert0 (or input invert1) is set to logic one, the input at the respective enable input en0 or en1 becomes inverted through XOR gate  54  (or  56 ). The states of the invert0 and invert1 inputs to XOR gates  54  and  56  are set by programmable switches in the FPGA during FPGA programming. 
         [0029]    As previously disclosed herein, the states of the outputs of the individual RAM blocks in a ganged RAM block arrangement according to the present invention are forced to a known state when the RAM block is not outputting data. In a synchronous RAM, the block-enable must be registered at the input, just like data and address and write- and/or read-enable. The output of the block-enable input register combined with write- and/or read-enable can simply gate data-outputs by AND gates. This is one illustrative example of circuitry that can be used to implement this function, but there are many other implementations possible to force output data to zero deeper inside the read logic. The output should stay zero until the next valid read-access. 
         [0030]    Referring now to  FIG. 4 , a logic diagram shows one illustrative circuit  60  for forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. Circuit  60  includes memory array block  62  and a portion of its circuitry including block-enable register  64  and write-enable register  66 . The input to block-enable register  64  may be coupled to output signal en of circuit  50  of  FIG. 3 . The output of memory array block  62  is ANDed in AND gate  68  with the output of block-enable register  64  and with the output of write-enable register  66  inverted by inverter  70 . In the event that the output of block enable register  64  is deasserted, d out  will be deasserted, i.e. set to a known state, irrespective of the value of the data within memory array  62 . Similarly, during a write operation to memory array  62 , the output d out  will be deasserted, i.e. set to a known state, irrespective of the value of the data within memory array  62 . 
         [0031]    Referring now to  FIG. 5 , a logic diagram shows another illustrative circuit  80  for forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. Circuit  80  includes memory array block  82  and a portion of its circuitry including block-enable register  84 , and separate write-enable and read-enable registers  86  and  88 , respectively. The input to block-enable register  84  may be coupled to output signal en of circuit  50  of  FIG. 3 . The output of the memory array block  82  is ANDed in AND gate  90  with the output of block-enable register  64  and the output of read-enable register  88 . 
         [0032]    In circuits  60  and  80  of  FIGS. 4 and 5 , respectively, which represent implementations of portions of a RAM block, the output of AND gate  68 ,  90 , respectively, is only equal to d out  of memory array block  62 ,  82 , respectively, when the other inputs to AND gate  68 ,  90 , respectively, indicate a valid read access. If only a write-enable is provided, as in the illustration shown in  FIG. 4 , it usually means a read access is indicated by a deasserted write-enable signal. If the RAM block uses block-enable and write-enable, then: 
         [0000]        d   out   =d   out (internal)&amp; block-enable&amp;!write enable.
 
         [0000]    If the RAM block was designed with a separate read-enable, then: 
         [0000]        d   out   =d   out (internal)&amp; block-enable&amp;read-enable
 
         [0000]    In all other cases, d out =0. 
         [0033]    Referring now to  FIG. 6 , a logic diagram shows another illustrative circuit  100  for forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. Circuit  100  includes memory array block  102  and a portion of its circuitry including block-enable register  104 . The input to block-enable register  104  may be coupled to output signal en of circuit  50  of  FIG. 3 , and may optionally be arranged to pass signal en, with or without buffering. The output of the memory array block  102  is ANDed in AND gate  106  with the output of block-enable register  104 . Circuits such as the one in  FIG. 6  would be preferred if the memory is providing useful data at the read outputs even during a write operation (e.g. a read-then-write operation, or a flow-through write operation). Persons of ordinary skill in the art will appreciate that but there are many other possible implementations for forcing output data to zero deeper inside the read logic of the RAM block. Whichever implementation is chosen, the output should stay at logic zero until the next valid read-access. 
         [0034]    The embodiment shown in  FIG. 6  is similar to the embodiments shown in  FIGS. 4 and 5 , except that d out  is only forced to zero when the RAM block containing circuit  100  is disabled, not also during write operations as with the embodiments of  FIGS. 5 and 6 . 
         [0035]    One advantage of the implementations using AND gates just before the data outputs is that this minimizes the dynamic power necessary to force the outputs to zero since the capacitances internal to the RAM of the memory array need not be discharged. 
         [0036]    Where feasible, it may be advantageous to support either of two modes when the RAM is disabled. In a first mode, the outputs are held at the previous values as in the prior art. In a second mode, the outputs are forced to a known state as described and shown with reference to  FIGS. 4 and 5 . The first mode is best suited to the case where the RAM is used individually and the second mode to the case where the RAMs are ganged as described herein. The choice of mode can be made when the FPGA is configured. 
         [0037]    Referring now to  FIG. 7 , a logic diagram shows an illustrative circuit  110  which permits choosing between holding outputs of a RAM block at the previous values and forcing the output of a RAM block to a known state in accordance with one aspect of the present invention. Circuit  110  includes memory array block  112  and a portion of its circuitry including block-enable register  114 . The input to block-enable register  114  may be coupled to output signal en of circuit  50  of  FIG. 3 . The output of the memory array block  102  is ANDed in AND gate  116  with the output of block-enable register  114 . Another input  118  may be provided to AND gate  116  to provide an input term from the output of a write- or read-enable register, such as write enable register  66  or read-enable register  88  of  FIGS. 4 and 5 , respectively, so that the output dout will be deasserted, i.e., set to a known state during a write operation to memory array  112 , irrespective of the value of the data within memory array  112 . 
         [0038]    The output of AND gate  116  drives the “0” data input of multiplexer  120 . The output of memory array  112  drives the “1” data input of multiplexer  120 . The select input of multiplexer  120  is driven by a configuration or mode signal at line  122 . This signal can be set to a fixed value during device programming or can be driven by a mode control signal generated by other logic in the integrated circuit. Thus, in the event that the select input of multiplexer  120  is set to pass the “1” data input, the output of memory array block  112  is maintained at the output. In the event that the select input of multiplexer  120  is set to pass the “0” input, the output of the RAM block is set to a known state responsive to AND gate  116 . 
         [0039]    While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.