Abstract:
A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.

Description:
FIELD OF THE INVENTION 
   The present invention is related to multi-port registers and more particularly improving multi-port register file performance. 
   BACKGROUND DESCRIPTION 
   Register files or, simply, registers are well known small, fast local storage arrays. A typical n by m register file includes storage latches in n rows and is m wide, e.g., a single byte, word or multi-word. Register files include, for example, first in first out (FIFO) or serial shift registers and first in last out (FILO) or push/pop registers. A FIFO may be a circulating shift register, for example, or a multi-port register with at least one input port and at least one output port. Additionally, typical such multi-port registers may be used for improving processor performance, e.g., in processor data queues or as pipeline registers. 
   In a state of the art pipeline structure, synchronous logic is segmented with a pipeline between segments or stages. So, in a pipeline processor, for example, a processor clock clocks pipeline registers distributed at strategic locations throughout the processor logic. Ideally, data latched in one pipeline stage propagates to, and arrives at, the next stage just as it is clocked into that next stage. So, pipeline registers act as boundaries between data units traversing the pipeline stages. Thus, for an N segment pipeline, N data units may be traversing the pipeline with one data unit in each segment. Also ideally, the logic delay through the N stages is N clock periods, i.e., the time each data unit spends in the pipeline is no more than necessary to propagate through the logic. So, ideal registers do not add path delay that detracts from overall performance. 
   In practice however, registers add to path delay, regardless of the register type (FIFO or FILO) or its use, e.g., whether as local storage or as a pipeline boundary. Consequently, for a pipeline circuit for example, the clock period limits the depth of the logic between pipeline registers to less than the clock cycle for any given clock frequency. Instead, the propagation delay between registers is offset or reduced by the register delay, where the register delay is the time through the registers, i.e., the time in and out of a register. So, the register delays reduce the time available for logic for each stage. 
   Further, the register delay is additive because it is encountered at each stage. For a pipeline circuit with 10 pipeline stages, for example, the 10 additional register delays may add one or more clock cycles to the time each data unit requires to traverse the pipeline, which is also known as the latency. Typically designers reduce the logic between stages with a corresponding increase in the overall number of stages to accommodate for these register delays. Each additional stage increases the circuit complexity without adding to the chip function; while it consumes valuable circuit area or real estate and so, reduces logic density. Further, each additional stage increases chip power, again without adding to the function and so, reduces chip efficiency. Of course, these problems dissipate as the register delays are reduced relative to other path logic. 
   Thus, there is a need for improved register performance. 
   SUMMARY OF THE INVENTION 
   It is a purpose of the invention to improve register performance; 
   It is another purpose of the invention to reduce register delays; 
   It is yet another purpose of the invention to reduce pipeline path latency. 
   The present invention relates to a multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses, e.g., with a high K dielectric bootstrap capacitor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: 
       FIG. 1A  shows an example of a preferred two port storage register latch with a bootstrapped supply, such a may be included in a high performance N by M register file according to a preferred embodiment of the present invention; 
       FIG. 1B  shows comparison of boosting cell supply voltage from three base supply voltages, 0.7V, 0.9V and 1.1V verses performance improvement for a typical register file cell; 
       FIG. 2  shows an example of a cross section of a preferred embodiment high performance N by M register file of preferred embodiment cells. 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
   Turning now to the drawings and, more particularly,  FIG. 1  shows an example of a preferred multi-port register cell  100  with a bootstrapped supply such as may be included in a high performance N by M multi-port register file according to a preferred embodiment of the present invention. The multi-port register cell  100  is a two port storage register latch in this example that, preferably, is in the insulated gate technology known as CMOS. The register cell  100  includes a pair of cross-coupled inverters  102 ,  104 . A pair of write pass gate field effect transistors (FETs)  106 ,  108  are connected to the cross-coupled inverters  102 ,  104 . A word-select line  110  is connected to the gates of write pass gate FETs  106 ,  108 , which are connected between the cross-coupled inverters  102 ,  104  and a pair of complementary write lines, a write true (WRT)  112  and a write complement (WRC)  114 . The cross-coupled inverters  102 ,  104 , each include a p-type FET (PFET)  102   p ,  104   p  and an n-type FET (NFET)  102   n ,  104   n  and are connected between a word supply  116  and a supply return or register ground. Output  118  from one of the cross-coupled inverters ( 104  in the example) is connected to the gate of one of a pair of series connected NFETs  120 ,  122 . The series connected NFETs  120 ,  122  are connected between ground (which need not be register ground) and a read data output line  124 . A read-select line  126  is connected to the gate of the other of the series connected NFETs  120 ,  122 . Thus, the cell contents  118  and the read-select line  126  are NANDed at read-data output line  124 . A capacitor  128 , preferably interline coupling capacitance, couples the read-select line  126  to the word supply  116 . For additional or enhanced bootstrap capacitance, optionally, capacitor  128  may be a high K dielectric capacitor, e.g., with a high K dielectric material passivating the read-select line  126  to the word supply  116  wiring layer. Also, capacitor  128  may include an individually formed capacitor (e.g., an FET capacitor or conductive plates or alternating wiring layers) between each read-select line  126  and word supply  116 . 
   Writing the register cell  100  begins with placing the intended data value on the pair of complementary bit write lines  112 ,  114 , driving one high and the other low. Then, the word-select line  110  is driven high, which turns on the pass gate FETs  106 ,  108 . Turning on the pass gate FETs  106 ,  108  couples the pair of complementary bit write lines  112 ,  114  to the cross-coupled inverters  102 ,  104 . A single bit of data is transferred to the cross-coupled inverters  102 ,  104 . Then, the word-select line  110  is returned low, which turns off the pass gate FETs  106 ,  108 , latching the data in the cross-coupled inverters  102 ,  104 . 
   Prior to reading data, however, the read-select line  126  is low and word supply  116  is at normal supply voltage, i.e., at V dd . So, the full array supply voltage is applied to bootstrap capacitor  128 , i.e., it is fully charged to V dd . The read-data output line  124  is pre-charged high and may then be allowed to float. The stored data may be read out by driving the read-select line  126  high, which is NANDed with the contents of the cell, i.e., at the output  118  of inverter  104 . So, with the read-select line  126  high, if output  118  is high, the read-data output line  124  is pulled low; or, otherwise, remains high. In addition however, the bootstrap capacitor  128  bootstraps the word supply  116  above V dd , i.e., to V dd +δ. The difference voltage is primarily a function of the ratio of bootstrap capacitance at bootstrap capacitor  128  and the apparent capacitance of the supply line  116 , which includes direct and indirect (e.g., through on cross-coupled inverter PFETs  102 P or  104 P) cell capacitances. As noted hereinabove, in addition to line to line coupling capacitance, bootstrap capacitor  128  may include a space capacitor (e.g., an area capacitor of two plates on adjacent wiring layer or an FET capacitor) specifically added to enhance bootstrap capacitance. If cell contents internal node  118  is high, bootstrapping the supply voltage  116  facilitates switching the read-data output line  124 , because V dd +δ is passed to the gate of NFET  120 , increasing the drive to switch the read-data output line  124 . 
     FIG. 1B  shows a comparison of boosting cell supply voltage from three base supply voltages, 0.7V, 0.9V and 1.1V at each of  130 ,  132  and  134  respectively, verses performance improvement for a typical register file cell, e.g.,  100  in  FIG. 1A . Thus, performance improvement may be realized by boosting cell supply in each of the examples  130 ,  132 ,  134  until an upper limit is reached, when the read performance improvement essentially plateaus, e.g., the added output transition time offsets the additional drive to a single FET ( 120 ) of the two NANDed devices  120 ,  122 . 
     FIG. 2  shows an example of a cross section of a preferred embodiment high performance N by M register file  140  of preferred embodiment cells, e.g., two port storage register latches  100  of  FIG. 1A . In this example, 3 read word lines  126 - 0 ,  126 - 1 ,  126 - 2 , of N words or rows are shown, with a single two port storage register latch  100  being shown in a single bit of one word,  126 - 1 . A typical row driver  142 - 0 ,  142 - 1 ,  142 - 2  drives a corresponding read word line  126 - 0 ,  126 - 1 ,  126 - 2 . Each of the N read word lines  126 - 0 ,  126 - 1 ,  126 - 2  are capacitively coupled to adjacent shared row supply lines  144 ,  146 ,  148 ,  150 , which are shared in this example by cells connected to adjacent read word lines  126 - 0 ,  126 - 1 ,  126 - 2 . Preferably, this capacitive coupling is from physical placement of the read word lines  126 - 0 ,  126 - 1 ,  126 - 2  interleaved with the shared row supply lines  144 ,  146 ,  148 ,  150 , analogous to what is shown graphically in this  FIG. 2 . Thus, for example, the read word lines  126 - 0 ,  126 - 1 ,  126 - 2  and shared row supply lines  144 ,  146 ,  148 ,  150  may be physically located on a common chip layer at minimum pitch and organized substantially as shown. Each row supply line  144 ,  146 ,  148 ,  150  includes at least one switch  144 - 0 ,  146 - 0 ,  146 - 1 ,  148 - 1 ,  148 - 2 ,  150 - 2 ,  150 - 3  and etc., connected between the respective row supply line  144 ,  146 ,  148 ,  150  and an ungated supply line  152 , e.g., register array or chip supply V dd . In this example, except at boundary cells connected to boundary supply lines, e.g.,  126 - 1 , switches  144 - 0 ,  146 - 0 ,  146 - 1 ,  148 - 1 ,  148 - 2 ,  150 - 2 ,  150 - 3  are pairs of series connected PFETs in each end of the respective row supply line  144 ,  146 ,  148 ,  150 . Each read word line  126 - 0 ,  126 - 1 ,  126 - 2  also gates off and on (opens and closes) the PFET switches  144 - 0 ,  146 - 0 ,  146 - 1 ,  148 - 1 ,  148 - 2 ,  150 - 2 ,  150 - 3  and etc. So, when a read word line, e.g.,  126 - 1 , is high, the corresponding row supply lines  146 ,  148  are decoupled from the array supply  152  because one of each respective pair is open, e.g., PFETs  146 - 1 ,  148 - 1  are off. 
   Data is written by placing the intended contents on complementary bit write pairs  112 ,  114  in  FIG. 1A  (i.e., driving one high and the other low) and driving a word select-line  110  high. Once data is written into the selected register location, the word-select line  1110  is dropped. A read is selected by driving low one input to the corresponding row driver, e.g., to  142 - 1 . In response to the low on the input, the selected row driver  142 - 1  drives the corresponding read word line  126 - 1  high, which opens the row supply switches, i.e., turns off the connected pair PFETs  146 - 1 ,  148 - 1 . With the switches  146 - 1 ,  148 - 1  open, the row supply lines  146 ,  148  are decoupled from the ungated supply  154 . Simultaneously, charge across the bootstrap capacitance  128  couples the signal from the read word line  126 - 1  to the row supply lines  146 ,  148 , bootstrapping them above V dd . The higher cell contents  118  are NANDed with read word line  126 - 1 . However, the higher bootstrap voltage is passed to  118 , which causes read bit line  124  to switch faster than it would normally switch, i.e., unbootstrapped. Thereafter, the input to the row driver  142 - 1  is raised which drops the corresponding read word line  126 - 1 , closing the switches  146 - 1 ,  148 - 1  in the row supply lines  146 ,  148  and reconnecting the row supply lines  146 ,  148  to the ungated supply  154 . Thus, read performance is improved for each selected word, improving array performance. 
   Advantageously, bootstrapping the rows supply lines in the register, increases the read biases for improved storage register read time. Therefore, fewer pipeline stages are required for the same logic in a preferred embodiment pipeline. Thus, circuit and chip efficiency is improved and chip latency is reduced. 
   While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims. It is intended that all such variations and modifications fall within the scope of the appended claims. Examples and drawings are, accordingly, to be regarded as illustrative rather than restrictive.