Abstract:
The circuits and methods of the present invention provide rail-to-rail output stages that cancel the non-linear components of the transconductances of transistors used in the output stages, that allow the idling current in the output stages to be controlled by external current sources and device size ratios, and that enable the idling current in the output stages to be maintained independently of manufacturing processes, temperature, and power supply voltages. The output stages generally comprise a complementary subcircuit, a current mirror and an output driver. The output stages receive an input signal and a bias voltage from an external source and responsively produce a push current that feeds current into a load and a pull current that pulls current from the load. When the push current matches the pull current, the output stages are said to be “idling.” The bias voltage controls the idling current. By mimicking the voltages and currents produced in the output stages using similar components, a bias voltage generation circuit provides a bias voltage that enables the idling point to be maintained in the output stages independently of manufacturing processes, temperature, and power supply voltages.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a division of application Ser. No. 09/113,618, filed Jul. 10, 1998 entitled CIRCUITS AND METHODS FOR PROVIDING RAIL-TO-RAIL OUTPUT STAGES. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to circuits and methods for providing rail-to-rail output stages. More particularly, this invention relates to circuits and methods for rail-to-rail output stages that provide high linearity without the use of feedback, that provide high linearity in their transconductance, that allow for designer-controllable idling currents, and that provide those designer-controllable idling currents independently of manufacturing processes, temperatures, and power supply voltages. 
     Rail-to-rail output stages are widely known in the prior art. The typical rail-to-rail output stage incorporates two common-source (or common-emitter) transistors of complementary polarities whose drains (or collectors) are connected together to form an output node that is connected to a load, whose sources (or emitters) are connected to a positive and a negative power supply voltage, and whose gates (or bases) are connected to two drive signals derived in turn from an external input signal. These output stages are very useful in that they maximize the output signal voltage swing capability of a circuit to nearly the limits of the power supply and, consequently, provide a maximal signal-to-noise ratio for a given noise level. 
     Many known circuits and methods for providing rail-to-rail output stages, however, exhibit very non-linear input to output transfer characteristics. These non-linear input to output characteristics often lead to signal distortion, especially at high frequencies where limited loop gain is available for correcting the output stage non-linearity by negative feedback. It is, therefore, desirable to provide high linearity in these output stages without the use of feedback. 
     In rail-to-rail output stages, it is often also desirable to maintain a known idling current flowing in each of the transistors of the output stage. This idling current is the current that flows in the transistors when the output stage is neither driving current into, nor sinking current from, a load that is connected to the output node. By maintaining an idling current in the transistors of the output stage, cross-over distortion in the output stage is kept to a minimum. However, this idling current can be difficult to control because of variations in manufacturing processes, temperatures, and power supply voltages of the components used to implement the output stage. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, it is an object of this invention to provide rail-to-rail output stages that achieve high linearity. 
     It is a further object of this invention to provide rail-to-rail output stages that achieve high linearity in their transconductance. 
     It is a still further object of this invention to provide rail-to-rail output stages that allow for designer-controllable idling currents. 
     It is also an object of this invention to provide rail-to-rail output stages that achieve high linearity without the use of feedback. 
     It is a yet further object of this invention to provide rail-to-rail output stages that allow idling currents to be independent of manufacturing processes, temperatures, and power supply voltages. 
     In accordance with the present invention, circuits and methods for rail-to-rail output stages that achieve these and other objects are provided. More particularly, the circuits and methods of the present invention provide rail-to-rail output stages that cancel the non-linearities inherent in transconductances of transistors in the output stages, that allow the idling current in the output stages to be controlled by current sources and device-size ratios, and that enable the idling current in the output stages to be maintained independently of manufacturing processes, temperatures, and power supply voltages. 
     Generally speaking, at a functional level, output stages constructed in accordance with the present invention comprise a two-transistor complementary subcircuit, a current mirror circuit, and an output driver circuit. These circuits are arranged so that an input signal is provided to the two-transistor complementary subcircuit and the output driver circuit. A bias voltage is also connected to the two-transistor complementary subcircuit. The two-transistor complementary subcircuit and the output driver circuit may also be connected to a supply voltage. The two-transistor complementary subcircuit drives the current mirror circuit. The current mirror circuit is also connected to another supply voltage. The current mirror circuit and the output driver circuit share a common terminal which is connected to a load. The load is also connected to a ground typically having a potential between the voltage supplied by the two supply voltages. 
     In operation, preferred output stages constructed in accordance with the present invention receive an input signal from an external source and a bias voltage from a bias generator, such as that described below. Responsive to this input signal, an output driver may produce a push current that feeds current into a load. Responsive to a voltage difference created by the input signal and the bias voltage, a two-transistor complementary subcircuit may feed a subcircuit current into a current mirror. In proportion to this subcircuit current, the current mirror then pulls a pull current from the load. When the push current that is being fed into the load by the output driver matches the pull current that is being pulled into the current mirror from the load, the output stage is said to be “idling” because the net current flowing in the load is zero. The response of the load current to input-signal voltage is, as usual, termed transconductance. 
     While the output driver is providing at least some push current and the current mirror is pulling in at least some pull current, the output stages of the present invention provide a substantially linear transconductance. This linear transconductance is achieved by the output stages matching the non-linear component of the push-path transconductance with a canceling, non-linear component of the pull-path transconductance. When a sufficiently strong voltage is provided as an input signal, one of the push or pull currents stops flowing. Once one of these currents stops flowing, the output stage stops canceling the non-linear components of the output signal and, instead, enters class AB operation wherein power efficiency is improved. 
     The output stages of the present invention may also incorporate bias voltage generation circuits to produce voltages that can be used as bias voltages for the output stages. These bias voltage generation circuits produce the desired bias voltages by mimicking the transistor voltages and currents produced in the output stages when operating at their idling points. Consequently, the idling currents in the output stages can be set ratiometrically with device-size ratios and reference current sources. The bias voltage generation circuits produce bias voltages for the rail-to-rail output stages so that the desired idling currents will be produced in the output stages independently of integrated circuit manufacturing processes, temperatures, and power supply voltages. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and advantages of the present invention will be apparent upon consideration of the following detailed description, taken in conjunction with accompanying drawings, in which like reference characters refer to like parts throughout, and in which: 
     FIG. 1 is a schematic diagram of a known configuration of a pair of output transistors in a rail-to-rail output stage; 
     FIG. 2 is a schematic diagram of an illustrative embodiment of a rail-to-rail output stage in accordance with the present invention; 
     FIG. 3 is a graph illustrating the voltage-to-current relationship between the input signal (V IN ) and the push current (I P ), the pull current (I N ), and the output current (I OUT ) of the circuit of FIG. 2; 
     FIG. 4 is a schematic diagram of a second illustrative embodiment of a rail-to-rail output stage that is arranged with its input signal driving an NMOS field effect transistor (FET) in accordance with the present invention; 
     FIG. 5 is a schematic diagram of a third illustrative embodiment of a rail-to-rail output stage that incorporates bipolar junction transistors (BJTs) in accordance with the present invention; and 
     FIG. 6 is a schematic diagram of an illustrative embodiment of a biasing circuit for providing a desired bias voltage (V BIAS ) in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In accordance with the present invention, circuits and methods for providing rail-to-rail output stages are disclosed. The rail-to-rail output stages of the present invention achieve high linearity without the use of feedback by matching and canceling non-linearities inherent in large-signal transconductance behavior of transistors in the output stages. Designer control of idling currents in these rail-to-rail output stages is facilitated by developing the idling currents from device-size ratios and reference currents. 
     For notational convenience, saturated-FET current-voltage equations are formulated herein in a threshold-voltage convention in which the threshold-voltage parameter (“V T ”) is positive for enhancement-mode FETs of both n-channel and p-channel polarities. Also, voltages not indicated as being measured between a pair of terminals are with reference to a ground terminal not necessarily shown. 
     FIG. 1 illustrates a known configuration  20  of a pair of output transistors in a rail-to-rail output stage. As shown, configuration  20  comprises PMOS FET  22  and NMOS FET  24  arranged with their drains  26  and  28 , respectively, connected together and tied to a load  30 , their sources  32  and  34  connected to V DD  and V SS  (the positive and negative rails), respectively, and their gates  40  and  42  connected to p-drive input  44  and n-drive input  46 , respectively. Load  30  is also connected to ground  31  whose potential is typically between that of V DD  and that of V SS . To drive the transistors of configuration  20  so that a current is created in load  30 , drive voltages must be applied to inputs  44  and  46 . When a drive voltage is applied at input  44  so that the source to gate voltage (V SG ) at FET  22  exceeds its PMOS threshold voltage (V TP ), a current flows out of drain  26 . This current is controlled by the source to gate voltage of FET  22 . When a drive voltage is applied at input  46  such that the gate to source voltage (V GS ) at FET  24  exceeds its NMOS threshold voltage (V TN ), a current flows into drain  28 . This current is controlled by the gate to source voltage of FET  24 . 
     The total current created in load  30  by FETs  22  and  24  is the difference between the current flowing out of drain  26  and the current flowing into drain  28 . Thus, when the current flowing out of drain  26  exceeds the current flowing into drain  28 , a current flows through load  30  toward ground  31 . When the current flowing out of drain  26  is less than the current flowing into drain  28 , a current flows through load  30  away from ground  31 . Finally, when the current flowing out of drain  26  equals the current flowing into drain  28 , the output stage is said to be at its idling point and no current flows through load  30 . At this idling point, the current flowing out of drain  26  and into drain  28  is referred to as the idling current (“I Q ”) of FETs  22  and  24 . 
     A circuit that provides high linearity and designer-controllable idling current in accordance with the present invention is illustrated in FIG.  2 . As shown, output stage  60  includes a PMOS FET  62  and an NMOS FET  64  that have their drains connected together and tied to a load  66 , and their sources connected to V DD  and V SS , respectively. Load  66  is also tied to a ground  67  whose potential is typically between that of V DD  and that of V SS . Also included in output stage  60  are an NMOS FET  72 , which together with NMOS FET  64  forms a current mirror  74 , and an NMOS FET  76  and a PMOS FET  78 , which together form a two-transistor complementary subcircuit  80 . As illustrated, the gate of FET  64  is connected to the gate and drain of FET  72  and the drain of FET  78 . The source of FET  72  is tied to V SS . The source and body terminal (to eliminate body effect) of FET  78  are connected to the source of FET  76 . The drain of FET  76  is tied to V DD . The gates of PMOS FET  62  and NMOS FET  76  are driven by V IN , and the gate of PMOS FET  78  is connected to V BIAS . 
     Current mirror  74  is intended to return a current I N  that is close to M times its input current I 1 , and to this end, NMOS FET  64  is preferably constructed from M identical parallel copies of NMOS FET  72 , placed in close proximity to FET  72  to minimize thermal differences. 
     For purposes of illustration, FIG. 2 as well as later FIGS. 4,  5  and  6  show examples of integrated circuits manufactured in an N-well CMOS fabrication process. Therefore in these figures, the P-type substrates of the illustrated integrated circuits are implicitly connected to V SS , and in PMOS transistors whose well (“body”) connection is not shown explicitly, the body is tied to V DD , following typical practice in the art. In FIG. 2, the connection of the body terminal of FET  78  to its source terminal removes the effect of body-to-source voltage on threshold voltage (the “body effect”) in FET  78 . All of the circuits described here can also be implemented in P-well or other CMOS processes, or in N-well processes with PMOS body connections different from those in the figures, in accordance with the invention. 
     Although circuit  60  is illustrated using PMOS and NMOS FETs  62 ,  64 ,  72 ,  76  and  78 , persons skilled in the art will appreciate that some or all of these devices could be replaced with different polarity FETs, with the same or different polarity BJTs, etc. Also, although not illustrated, the drain current of FET  76  could be recovered and incorporated into I OUT  by, for example, inserting a resistor between V DD  and the junction of the source of FET  62  and the drain of FET  76 . 
     Output stage  60  generally operates as follows. A current I OUT  is produced in load  66  under the control of inputs provided by V IN  and V BIAS . I OUT  is the difference between push current I P  (provided by the drain of FET  62 ) and pull current I N  (provided by the drain of FET  64 ). Like the current flowing out of the drain of FET  22  of FIG. 1, current I P  is controlled directly by V IN , and is a function of the difference between the voltages at V DD  and V IN . 
     Unlike the current flowing into the drain of FET  24  of FIG. 1, current IN flowing into the drain of FET  64  is not controlled directly by a single, dedicated input. Rather, current I N  is a function of the combination of the signals at V IN  and V BIAS . Based upon the voltages at V IN  and V BIAS , a current I 1  flows through subcircuit  80 . As explained in detail below, subcircuit  80  acts analogously to an NMOS FET whose threshold voltage is controllable by V BIAS  and whose transconductance factor is a combination of those of FETs  76  and  78 . Current I 1  also flows through FET  72  of current mirror  74 . Based upon the current ratio of current mirror  74 , current I N  flows into the drain of FET  64  at a rate that is M times current I 1  flowing through FET  72 . 
     Turning to FIG. 3, the high linearity and designer-controllable idling current properties of the present invention are illustrated graphically. FIG. 3 shows the currents I P , I N  and I OUT  that are produced as a function of the input signal at V IN  (FIG. 2) . As can be seen from FIG. 3, I P  and I N  behave non-linearly over the input voltage range illustrated. Because each of the FETs in FIG. 2 typically operate in saturation when turned on, currents I P  and I N  follow a square-law relationship. For an NMOS FET such as FET  64  of FIG. 2, this square-law relationship can be approximated mathematically as follows: 
     
       
           I   N   ≅K   N ( V   GSN   −V   TN ) 2 ,   (1) 
       
     
     where I N  is the drain current as defined in FIG. 2, K N  is the transconductance factor, V GSN  is the gate to source voltage, and V TN  is the threshold voltage, of the NMOS FET. For a PMOS FET such as FET  62  of FIG. 2, using the threshold-voltage convention described earlier, this square-law relationship can be approximated mathematically as follows: 
     
       
           I   P   ≅K   P ( V   SGP   −V   TP ) 2 ,   (2) 
       
     
     where I P  is the drain current as defined in FIG. 2, K P  is the transconductance factor, V SGP  is the source to gate voltage, and V TP  is the threshold voltage, of the PMOS FET. 
     To the accuracy of equations (1) and (2), referring to FIG. 2, it is clear that for PMOS FET  62 , I P  can also be represented by the following equation: 
     
       
           P   =K   P (V DD   −V   IN   −V   TP ) 2 .  (3) 
       
     
     Alternatively, equation (3) can be stated as follows: 
     
       
           I   P   =K   P   V   DD   2 −2 K   P   V   DD   V   IN −2 K   P   V   DD   V   TP   +K   P   V   IN   2 +2 K   P   V   IN   V   TP   +K   P   V   TP   2 .   (4) 
       
     
     To similarly represent current I N  in terms of V IN , it is necessary to take into consideration the topology of output stage  60  and the characteristics of subcircuit  80  and current mirror  74 . First, observing the topology of output stage  60 , it is apparent that the gate to source voltage V GS76  of FET  76  plus the source to gate voltage V SG78  of FET  78  is equal to the input signal voltage V IN  minus the bias voltage V BIAS . This relationship can be represented by the following equation: 
     
       
           V   GS76   +V   SG78   =V   IN   −V   BIAS .  (5) 
       
     
     Also, because the current I D76  flowing into the drain of FET  76  is the same as the current I D78  flowing out of the drain of FET  78 , I 1  can be represented by the following relationship: 
     
       
         I 1 =I D76 =I D78 .   (6) 
       
     
     Under the square-law relationship, the current in the drain of FET  76  can be approximated by the following equation: 
     
       
           I   D76   =K   76 ( V   GS76   −V   T76 ) 2 .   (7) 
       
     
     where K 76  is the transconductance factor, V GS76  is the gate to source voltage, and V T76  is the threshold voltage, of FET  76 . Equation (7) can be stated alternatively as: 
     
       
           V   GS76   =V   T76 +( I   D76   /K   76 ) ½ .   (8) 
       
     
     Similarly, under the square-law relationship, the current in the drain of FET  78  can be approximated by the following equation: 
     
       
           I   D78   =K   78 ( V   SG78   −V   T78 ) 2 ,  (9) 
       
     
     where K 78  is the transconductance factor, V SG78  is the source to gate voltage, and V T78  is the threshold voltage, of FET  78 . Equation (9) can be stated alternatively as: 
     
       
           V   SG78   =V   T78 +( I   D78   /K   78 ) ½ .   (10) 
       
     
     Combining equations (5), (6), (8), and (10) and solving for I 1 , it is apparent that I 1  can be represented by the following equation: 
     
       
           I   1   =K   C ( V   IN   −V   BIAS   −V   T76   −V   T78 ) 2 ,   (11) 
       
     
     where K C  is defined by the following equation and represents the transconductance factor of subcircuit  80 : 
     
       
           K   C =1/(1 /K   76   ½ +1 /K   78   ½ ) 2 .   (12) 
       
     
     Because I N  is proportional by a factor M to the current in FET  72  in accordance with the current ratio of current mirror  74 , and because the current in FET  72  is equal to current I 1  in subcircuit  80 , current I N  can be represented by the following equation: 
     
       
           I   N   =MI   1   =MK   C ( V   IN   −V   BIAS   −V   T76   −V   T78 ) 2 ,  (13) 
       
     
     or alternatively as: 
     
       
           I   N =MK C   V   IN   2 −2 MK   C   V   IN   V   BIAS −2 MK   C   V   IN   V   T76 −2 MK   C   V   IN   V   T78   
       
     
     
       
         +MK C   V   BIAS   2 +2 MK   C   V   BIAS   V   T76 +2 MK   C   V   BIAS   V   T78   +MK   C   V   T76   2  +2 MK   C   V   T76   V   T78   +MK   C   V   T78   2 .  (14) 
       
     
     Referring to equation (4) above, it is apparent that K P V IN   2  is the only component of I P  that is non-linear in V IN , because V DD  and V TP  are independent of V IN . Similarly, referring to equation (14) above, it is apparent that MK C V IN   2  is the only component of I N  that is non-linear in V IN , because V BIAS , V T76 , and V T78  are independent of V IN . 
     In order to achieve linearity from V IN  to I OUT , it is necessary to eliminate the non-linear components of I P  and I N . As stated above, I OUT  is simply the difference between I P  and I N , as expressed by the following equation: 
     
       
           I   OUT   =I   P   −I   N .   (15) 
       
     
     Accordingly, eliminating the non-linear components of I P  and I N  can be accomplished by matching and canceling the two non-linear components of I P  and I N . In order to do so, the following equation must be satisfied: 
     
       
         K P V IN   2 =MK C V IN   2 ,   (16) 
       
     
     or as alternatively stated: 
     
       
         K P =MK C .   (17) 
       
     
     Thus, by selecting a combination of FET  62  with a transconductance K P , FETs  76  and  78  with transconductances K 76  and K 78 , respectively, and, therefore, a combined transconductance K C , and FETs  64  and  72  so that current mirror  74  has a current ratio M, such that equation (17) is satisfied, output current I OUT  will be a linear function of V IN . 
     Although the principal non-linearity in the V IN -to-I OUT  relation has been canceled in output stage  60  by the constraint in equation (17), it is important also to provide for designability of the idling current I Q  (the current that flows in devices  62  and  64  when I OUT  is zero). 
     In FIG. 2, two separate paths link V IN  to I OUT : an upper (I P ) path through PMOS device  62  and a lower (I N ) path through the other devices. Separate, non-linear, large-signal V IN -to-I curves govern these two paths, as illustrated in FIG. 3, even though the nonlinear parts of these curves cancel in I OUT . The two curves intersect at point  94 , where I P  equals I N , at a current value I Q , which is the idling current. Intersection of the I P  and I N  curves occurs at a particular value of V IN , which is referred to herein as “V INQ .” 
     The V BIAS  voltage in FIG. 2 can be used to set the idling current value I Q . This is because, as may be evident from the circuit of FIG.  2  and is also explicit in equation (13), V BIAS  directly offsets the effect of V IN  on I N . That is, as V BIAS  becomes more positive or negative, the value of V IN  required to obtain a given value of I N  changes, respectively positive or negative, by the same amount. The effect of this in the plot of FIG. 3 is to shift the I N  curve to the right or left, respectively. V BIAS  shifts the I N  curve but not the I P  curve, mathematically equation (3). Consequently, changing V BIAS  changes the intersection current I Q  and the corresponding voltage V INQ . 
     Analyzing for the input-output relationship (V IN  to I OUT ) in output stage  60  shows explicitly the form of dependance of V INQ  and I Q  on V BIAS , the value of V BIAS  necessary to bring about a desired value of I Q , the corresponding value of V INQ , and a simple relationship between I OUT  and V IN . From equations (3) and (13) and using the shorthand V TC =V T76 +V T78 , I OUT  can be represented by the following equation: 
     
       
           I   OUT   =I   P   −I   N   =K   P ( V   DD   −V   IN   −V   TP ) 2   −MK   C ( V   IN   −V   BIAS   −V   TC ) 2 .  (18) 
       
     
     Using the earlier linearizing condition of equation (17) to eliminate the factor MK C  and rearranging yields the general expression: 
     
       
           I   OUT   =K   P [( V   DD   −V   TP ) 2 −( V   BIAS   +V   TC ) 2 −2 V   IN ( V   DD   −V   TP   −V   BIAS   −V   TC )].   (19) 
       
     
     This I OUT  is zero at a particular value of V IN , called V INQ . Solving for the condition I OUT =O and rearranging gives: 
     
       
           V   INQ =( V   DD   −V   TP   +V   BIAS   +V   TC )/2,   (20) 
       
     
     and the idling current I Q , which is the value of I P  (or I N ) when V IN =V INQ , can be shown to be: 
     
       
           I   Q   =[K   P ( V   DD   −V   TP   −V   BIAS   −V   TC ) 2 ]/4.   (21) 
       
     
     The last expression can be rearranged for the required value of V BIAS  to obtain a given idling current I Q : 
     
       
         V BIAS   =V   DD   −V   TP   −V   TC −2( I   Q   /K   P ) ½   (22) 
       
     
     Such a voltage can be derived in a V BIAS  generator circuit using similar transistors, as shown below, and the output of this V BIAS  generator circuit can simultaneously drive many output stages  60 . 
     With this value of V BIAS  applied, the input idling voltage V INQ  becomes: 
     
       
           V   INQ   =V   DD   +V   TP −( I   Q   /K   P ) ½ .   (23) 
       
     
     When this proper V BIAS  of equation (22) is applied to an output stage  60  also satisfying the linearity condition of equation (17), the input-output relation of equation (19) simplifies (using the foregoing results) to: 
     
       
           I   OUT =−4( K   P   I   Q ) ½ ( V   IN   −V   INQ ).   (24) 
       
     
     Equation (24) is valid as long as the FETs in output stage  60  are in normal strong-inversion saturated operation, and in particular, conducting current. Within that constraint, equation (24) is a general, or large-signal, result, not the far more common situation of a linearized model predicated on signal excursions being negligible. This is a major benefit of the invention. The linearizing condition K P =MK C  of equation (17) is easily satisfied because four different factors enter into it: the size of FET  76  (which contributes to K 76  and hence K C  as shown in equation (12)); the size of the FET  78  (which contributes to K 78  and hence K C  as shown in equation (12)); the size ratio of FETs  72  and  64  via current mirror ratio M; and the size of FET  62  via the factor K P . These four factors can be combined in many different ways to satisfy equation (17). 
     In order for output stage  60  to cancel the non-linear components of currents I P  and I N  as described above, both FETs  62  and  64  must be conducting current, and, thus, output stage  60  must be in the class A operating mode. Once one of FETs  62  or  64  has shut off, the non-linear cancellation feature of output stage  60  no longer functions, and, accordingly, output stage  60  leaves the class A operating mode and enters the class AB operating mode, wherein power efficiency is improved. 
     An alternate embodiment of output stage  60  is illustrated by output stage  100  in FIG.  4 . In output stage  100 , V IN  drives an NMOS FET  102  rather than driving a PMOS FET as is done in output stage  60  of FIG.  2 . 
     Like output stage  60 , output stage  100  includes NMOS FET  102  and PMOS FET  104  whose drains are connected together and tied to load  106 , and whose sources are connected to V SS  and V DD , respectively. Load  106  is also connected to ground  107  whose potential is typically between that of V DD  and that of V SS . I OUT  flowing in load  106  is the difference between I P  flowing out of the drain of FET  104  and I N  flowing into the drain of FET  102 . Also included in output stage  100  are PMOS FET  112 , which together with PMOS FET  104  forms 1:M current mirror  114 , and PMOS FET  116  and NMOS FET  118 , which together form two-transistor complementary subcircuit  120 . As illustrated, the gate of FET  104  is connected to the gate and drain of FET  112  and the drain of FET  118 . The source of FET  112  is tied to V DD . The source of FET  118  is connected to the source of FET  116 , which is also connected to the body terminal of FET  116  (to eliminate body effect). The drain of FET  116  is connected to V SS . The gates of NMOS FET  102  and PMOS FET  116  are driven by V IN , and the gate of NMOS FET  118  is connected to V BIAS . 
     Although circuit  100  is illustrated with PMOS and NMOS FETs  102 ,  104 ,  112 ,  116 , and  118 , persons skilled in the art will appreciate that some or all of these devices could be replaced with different polarity FETs, with the same or different polarity BJTs, etc. Also, although not illustrated, the drain current of FET  116  could be recovered and incorporated into I OUT  by, for example, inserting a resistor between V SS  and the junction of the source of FET  102  and the drain of FET  116 . 
     Output stage  100  is an N-to-P complement, or “upside-down,” variation of output stage  60  of FIG.  2 . The operation of the two circuits  60  and  100  is exactly analogous, with the substitution of NMOS devices for PMOS and vice versa. Analysis of the operation of output stage  100  proceeds as for output stage  60 , with the following basic results. For notational convenience, as with FIG. 2, saturated-FET current-voltage equations are formulated here so that the threshold-voltage parameters (“V T ”) for both NMOS and PMOS polarities of FETs are positive with enhancement-mode devices. Parameters K N  and V TN  characterize output-driver NMOS FET  102 . Two-transistor complementary subcircuit  120 , like analogous subcircuit  80  of FIG. 2, can be characterized with composite parameters V TC  and K C , defined by: 
     
       
           V   TC   =V   T118   +V   T116 ,   (25) 
       
     
     and 
     
       
           K   C =1/(1 /K   118   ½ +1 /K   116   ½ ) 2 .   (26) 
       
     
     The components in currents I P  and I N  that are nonlinear functions of V IN  cancel out in I OUT  when the following condition is satisfied: 
     
       
         K N =MK C .   (27) 
       
     
     With this condition met, the required value of V BIAS  to achieve a desired idling current I Q  in both I P  and I N  is: 
     
       
           V   BIAS   =V   SS   +V   TN   +V   TC +2( I   Q   /K   N ) ½ .   (28) 
       
     
     With this value of V BIAS  applied, the corresponding idling value of V IN  is V INQ , where: 
     
       
           V   INQ   =V   SS   +V   TN +( I   Q   /K   N ) ½ ,   (29) 
       
     
     and the overall input-output expression is: 
     
       
           I   OUT =−4( K   N   I   Q ) ½ ( V   IN   −V   INQ ).   (30) 
       
     
     FIG. 5 illustrates an output stage  150  incorporating Bipolar Junction Transistors (BJTs) in accordance with the present invention. Functionally, output stage  150  operates analogously to output stage  100  of FIG.  4 . Although output stage  150  is illustrated with BJTs  166 ,  170 ,  176  and  186 , and FETs  190 ,  192  and  194 , output stage  150  could alternatively be implemented with some or all of the BJTs being replaced by the same or different polarity FETs and/or some or all of the FETs being replaced by the same or different polarity BJTs. Moreover, even though an output stage incorporating BJTs that operates analogously to output stage  100  is illustrated in FIG. 5, other output stages incorporating BJTs, such as an output stage incorporating BJTs that operates analogously to output stage  60 , could be implemented in accordance with the present invention. 
     As shown in FIG. 5, output stage  150  includes a two-transistor complementary subcircuit  182 , a current mirror  158 , an output driver circuit  156  and a PNP BJT  176  that is used for anti-saturation clamping. Subcircuit  182  incorporates a PMOS FET  190 , a resistor  188  and an NPN BJT  186 . The gate of FET  190  is connected to V IN  and the drain of FET  190  is connected to V SS . One side of resistor  188  is connected to the source of FET  190 , which is also connected to the body terminal of FET  190  (to eliminate body effect), and the other side of resistor  188  is connected to the emitter of NPN BJT  186 . Connected to the base of BJT  186  is V BIAS . Current mirror  158  includes PMOS FET  192  and PMOS FET  194 . The gate and drain of FET  192  and the gate of FET  194  are connected to the collector of BJT  186 . The sources of FETs  192  and  194  are connected to V DD . The drain of FET  194  is connected to one side of load  154 . The other side of load  154  is connected to ground  153  whose potential is typically between that of V DD  and that of V SS . 
     Output driver circuit  156  incorporates NPN BJT  170 , resistor  172 , NPN BJT  166  and current source  168 , which current source may be replaced by a resistor or omitted entirely. The collector of BJT  170  is connected to one side of load  154  and to the drain of FET  194 , and the emitter of BJT  170  is connected to one side of resistor  172 . The other side of resistor  172  is connected to V SS . The base of BJT  170  is connected to the emitter of BJT  166  and current source  168 . Current source  168  is also connected to V SS . The collector of BJT  166  is connected to V DD  and the base of BJT  166  is connected to V IN  and the emitter of PNP BJT  176 . The base of PNP BJT  176  is connected to the collector of BJT  170  and the collector of PNP BJT  176  is connected to V SS . 
     Although circuit  150  of FIG. 5 is illustrated with resistors  172  and  188 , either or both of these resistors may be omitted entirely and replaced by a connection between the circuit nodes at their terminals. 
     As in output stages  60  and  100  of FIGS. 2 and 4, respectively, output stage  150  produces push current I P  and pull current I N  that control the current in load  154 . I P  is produced in response to a bias voltage provided at V BIAS  and an input signal provided at V I   N . More particularly, when NPN transistor  186  and PMOS FET  190  are driven by V BIAS  and V IN , respectively, I C  flows through BJT  186 , resistor  188 , and FET  190  of subcircuit  182 . As with subcircuit  80  of FIG.  2  and subcircuit  120  of FIG. 4, the equivalent threshold voltage of subcircuit  182  is variable and is controlled by the bias voltage presented at V BIAS . Responsive to I C , current mirror  158  causes I P  to flow out of the drain of PMOS FET  194  in proportion to I C , by a factor M, into load  154  and/or output driver circuit  156 . 
     I N  is produced by output driver circuit  156  in response to the input signal provided at V IN . Circuit  156  is preferably a degenerated common-collector, common-emitter pair as is well known in the art. To prevent saturation of transistor  170 , PNP BJT  176  is provided in output stage  150  to decrease the current flowing into the base of transistor  166  when the voltage at the collector of transistor  170  falls below a threshold value. 
     A circuit  200  for producing a desired bias voltage for a V BIAS  of one or more output stages  60  (FIG. 2) is illustrated in FIG.  6 . Circuit  200  produces the desired bias voltage by mimicking the voltages and currents produced by output stage  60  while output stage  60  is operating at idling point  94 . More particularly, the voltages produced in many of the components of circuit  200  are identical to voltages produced in the corresponding components of output stage  60 . For example, the gate-to-source, and in most cases also the drain-to-source, voltages produced in FETs  218 ,  210 ,  208 ,  216  and  214  are identical to the voltages produced in FETs  62 ,  64 ,  72 ,  76  and  78 , respectively, of output stage  60 . 
     The currents produced in these components of circuit  200  may be either identical to or proportional to the currents in the corresponding components of output stage  60 . For example, in order to conserve power, the currents in circuit  200  may be scaled down proportionally to the currents in output stage  60 . The transistor sizes, and hence transconductance (“K”) parameters, of the transistors in circuit  200  must be scaled according to their currents, in order to achieve the same operating terminal voltages. By mimicking the voltages and currents produced in output stage  60  under similar operating conditions, a V BIAS  voltage is produced by circuit  200  so that an idling current is produced in output stage  60  that is independent of variations in integrated circuit manufacturing processes, temperature, and power supply voltages and is dependent only upon current sources in circuit  200  and device size ratios. By mimicking circuit  60  in this way, the process, temperature, and supply voltage dependencies of the devices in circuit  200  tend to cancel those in circuit  60 . 
     The generation of the desired V BIAS  voltage in circuit  200  is controlled by current sources  202  and  204 . Current sources  202  and  204  may be implemented using any known circuits or methods. The currents produced by current sources  202  and  204  may be either identical to, or proportional to, the idle current I Q  desired in output stage  60 . Each of the currents produced by current sources  202  and  204  drive one of two overlapping negative feedback loops. These feedback loops operate to establish the voltages at the gates of FETs  214 ,  216 , and  218  that cause the full currents provided by current sources  202  and  204  to flow through FETs  210 ,  212 , and  218 . 
     One negative feedback loop can be traced from node  240 , to the gate of FET  216 , through two-transistor complementary subcircuit  232 , current mirror  206 , cascode FET  212  and back to node  240 . This feedback loop maintains current I 2  at the exact value of current source  202  by adjusting the voltages and currents in the loop to correct deviations in  12  away from the exact value of current source  202 . More particularly, if FETs  210  and  212  did not conduct the exact value of current source  202 , then the DC current flow into node  240  would not equal the DC current flow out of node  240 , and, as is known from Kirchhoff&#39;s Current Law, the voltage at node  240  would begin to increase or decrease as the transistor capacitances at node  240  charged up or down. This increase or decrease in voltage at node  240  would result in a restoring effect tending to direct the current in FETs  210  and  212  toward the full value of current source  202 . 
     For example, if the drain current in FETs  210  and  212  were to decrease to below the exact value of current source  202 , then the voltage at node  240  would tend to become more positive in voltage. This increase in voltage would cause the gate voltages of FETs  216  and  218  to increase, and the gate voltage of FET  214  to decrease as a result of the inverting action of FET  218 . Because of the increase in the voltage across the gates of FETs  214  and  216 , I 3  in subcircuit  232  would increase similarly to I 1  in subcircuit  80  of FIG.  2 . This increase in current in subcircuit  232  would then cause the current in FET  210  of current mirror  206  and in FET  212  to increase, thereby restoring I 2  to the exact value of current source  202 . 
     Another negative feedback loop can be traced from the gate of FET  214 , through subcircuit  232 , current mirror  206 , and cascode FET  212 , to the gate of FET  218 , through FET  218 , and back to V BIAS . Analogously to the first feedback loop, this feedback loop operates to maintain the current I 4  flowing through FET  218  at the exact value of current source  204 . If FET  218  did not conduct the exact value of current source  204 , then the DC current flow into node  242  would not equal the DC current flow out of node  242 , and, as is known from Kirchhoff&#39;s Current Law, the voltage at node  242  would begin to increase or decrease as the transistor capacitances charged up or down. This increase or decrease in voltage at node  242  would result in a restoring effect tending to direct the current in FET  218  toward the exact value of current source  204 . 
     For example, if I 4  flowing through FET  218  were to fall below the exact value of current source  204 , then the voltage at node  242  would tend to become less positive. This decrease in voltage at node  242 , and, consequently, the gate of FET  214  of subcircuit  232 , would cause an increase in I 3  flowing in subcircuit  232 . Responsive to this increase in I 3 , current mirror  206  would cause a proportional increase in I 2 . As stated above, such an increase in current would cause a decrease in voltage at node  240  and the gate of FET  218 . This decrease in gate voltage at FET  218  would result in a restoring effect that increases I 4  in FET  218  to the exact value of current source  204 . 
     As stated above, because FETs  218 ,  216 ,  214 ,  208  and  210  are selected to exhibit substantially identical voltages and substantially identical or proportional currents to those produced in FETs  62 ,  76 ,  78 ,  72  and  64  of output stage  60 , respectively, the voltages produced by these feedback loops are those that will be produced in output stage  60  when operating at idling point  94 . More particularly, since I 4  flowing through FET  218  matches, or is proportional to, I Q  in FET  62 , it is apparent that the gate voltage of FET  218  is equal to V IN &#39;s idling value V INQ  of output stage  60 . Also, since I 2  flowing through FET  210  matches, or is proportional to, I Q  in FET  64 , it is apparent that I 3  flowing through subcircuit  232  matches, or is proportional to, I Q  flowing through FETs  76 ,  78  and  72  of output stage  60 . Because subcircuit  232  behaves like subcircuit  80 , and because the gate of FET  216  has a voltage equal to the idling input voltage V INQ  of output stage  60 , and because I 3  flowing through subcircuit  232  matches I 1  in subcircuit  80  when operating at idling point  94 , it follows that the voltage at the gate of FET  214 , and consequently V BIAS , matches the required V BIAS  for output stage  60  to operate at the idling point. 
     As illustrated in FIG. 6, cascode FET  212  and capacitor  220  are provided in circuit  200 . Under the control of a reference voltage  226  connected to its gate, cascode FET  212  allows the drain-to-source voltage of FET  210  to be fixed so that the V DS  of FET  210  matches the V DS  of FET  64  (FIG. 2) at idle. Capacitor  220  stabilizes the feedback loops in the V BIAS  generator by preventing oscillations. Capacitor  220  is connected between V BIAS  and ground  230 . It is desirable, although not mandatory, to place capacitor  220  at V BIAS  because it is desirable to place the dominant pole of a regulator at the output. Capacitor  220  then not only stabilizes the feedback loops against oscillations, but also guarantees low output impedance at most frequencies and absorbs transient currents on V BIAS . 
     V BIAS  GENERATOR  200  in FIG. 6 is designed for use with, and contains transistors whose operating conditions mimic those of transistors in, output stage  60  of FIG.  2 . Each of the other output stage circuits that are variants of circuit  60 , such as those in FIGS. 4 and 5 as well as other variants not illustrated, needs a corresponding V BIAS  generator. In each case, a V BIAS  generator analogous to circuit  200  can be constructed following the principles described above for circuit  200  and its relationship to output stage  60 . 
     Persons skilled in the art will thus appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.