Abstract:
A power array includes a plurality of FET power assemblies and each FET power assembly has at least one field effect transistor mounted to a ciruit board. The circuit boards are arranged atop each other. A power supply pin extends through the circuit boards and is connected to a power input of each field effect transistor. A power output of each FET power assembly is connected to a power output pin which extends through each of the circuit boards. A heat sink is mounted to the power array beneath the lowest FET power assembly and is thermally connected to the field effect transistors of each FET power assembly. A method of assembling a power array including a plurality of FET power assemblies with at least one field effect transistor.

Description:
TECHNICAL FIELD 
   This invention relates generally to FET arrays for providing power to electronic devices, and more particularly, to multi-layer FET arrays, to methods for fabricating such arrays, and to power supplies including such arrays. 
   BACKGROUND 
   Many systems employ electrical devices. It is often desirable to densely pack these devices so as to reduce the size of the system. Indeed, the ability to do so can be essential to meeting the demand for systems having smaller packages and ever increasing power densities. 
   In these densely packed systems, power must be provided to operate the electrical devices. It is also desirable that the power supplies be arranged and configured to take up as little space as possible. Often, such power supplies might include a Field Effect Transistor (FET). To provide power to a plurality of electrical devices within the system, often these power supplies would include multiple FETs in order to supply the power required by the other electrical components. Such FETs may be mounted to printed circuit boards (PCBs) alongside the other components. Alternatively, FETs may be mounted to smaller component PCBs and the component PCBs mounted to the main PCB with the other components. 
   However, the space required for each of the FETs reduces the amount of space within the system for the inclusion of other electrical components, assuming that a given system volume is fixed and the system has a finite amount of PCB area for mounted electrical components within a given space. If the system requires a certain type and array of components, then the system would be configured to fit into a larger volume. 
   It is desirable to improve the density of power supply that may be provided within an electrical system without requiring additional PCB area. 
   SUMMARY 
   The present invention relates to a power away including a plurality of FET power assemblies, each FET power assembly with at least one field effect transistor mounted to a circuit board. The circuit boards are arranged atop each other. A power supply pin extends through the circuit boards and is connected to a power input of each field effect transistor. A power output of each FET power assembly is connected to a power output pin which extends through each of the circuit boards. A heat sink is mounted to the power away beneath the lowest FET power assembly and is thermally connected to the field effect transistors of each FET power assembly. 
   The present invention further relates to a method of assembling a power array including a plurality of FET power assemblies. The FET power assemblies are positioned within a plurality of pins of a base of a power array assembly fixture. Power input pins are inserted through first opening in the FET power assemblies and a power output pin is inserted within a second opening in each of the FET power assemblies. The FET power assemblies and the pins are bonded together into a power array which is removed from the power array assembly fixture. The power array is mounted to a heat sink and each FET assembly is thermally connected to the heatsink. 
   Other advantages of the multi-layer laminate and method of the present invention will become apparent in view of the following detailed description of preferred embodiments, claims, and accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and constitute a part of the description, illustrate several aspects of the invention and together with the detailed description, serve to explain the principles of the invention. A brief description of the drawings is as follows: 
       FIG. 1  is a side view of an FET power array mounted to a heat sink. 
       FIG. 2  is a side view of the FET power array of  FIG. 1 , removed from the heat sink. 
       FIG. 3  is a side exploded view of the FET power array of  FIG. 2 . 
       FIG. 4  is a bottom view of one of the FET assemblies of the FET power array of  FIG. 2 . 
       FIG. 5  is a side exploded view of a fixture for assembling the FET power array of  FIG. 2 . 
       FIG. 6  is a side view of the fixture of  FIG. 5 , with the components of the FET power array positioned within the fixture. 
       FIG. 7  is a top view of the fixture of  FIG. 5 , with the top of the fixture removed. 
       FIG. 8  is a schematic diagram of an FET power array according to the present invention. 
   

   DETAILED DESCRIPTION 
   Reference will now be made in detail to exemplary aspects of the present invention which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
     FIG. 1  shows a power assembly  10  for providing power to other electrical devices. Power assembly  10  includes a FET array  12  mounted to a heat sink  14 . FET assembly  12  includes a plurality of FET assemblies  16 , a power output pin  18 , a pair of switch or gate control pins  20  and a plurality of power input pins  22 . Power or current input pins  22  and power output pin  18  may also serve other functions, such as structurally supporting array  12 , in addition to conveying electrical current from and to FETs  26 . Gate control pins  20  may also provide structural support to array  12 . 
   Arranging FET assemblies  16  in the manner shown in  FIG. 1  permits each FET assembly  16  to be connected in parallel with other FET assemblies  16 , as opposed to being connected in series. Each FET  26  on a FET assembly  16  presents a certain amount of resistance to current flow from power input pins  22  to power output pin  18 . Multiple FETs  26  connected in parallel, as shown in  FIG. 1 , will result in less total resistance than the same number of FETs  26  connected in series. Thus, FET array  12  of power assembly  10  with FETs  26  connected in parallel is able to provide power to downstream devices at a higher current than a device with a similar number of FETs arranged in series. 
   As shown in  FIGS. 2 and 3 , array  12  includes four FET assemblies  16 , stacked one on top of each other, with pins  18 ,  20  and  22  extending generally perpendicular to assemblies  16 . Between each pair of FET assemblies  16  are electrically insulative pads  24  which provide electrical insulation and prevent physical contact of FETs  26  with adjacent FET assemblies  16 . Another pad  24  is positioned beneath the lowest FET assembly  16  to provide electrical insulation between the lowest FET assembly and heat sink  14 . 
   Referring now to  FIG. 4 , FET assembly  16  includes a pair of FET banks  26  mounted to a circuit board  28 . Circuit board  28  includes traces which provide electrical connectivity between pins  18 ,  20  and  22 , the FET banks  26 , and other electrical components of FET assembly  16 . Circuit board  28  includes a plurality of pin openings  29  for pins  20  and  22  and a pin opening  30  for power output pin  18 . 
   As shown in the FIGS., pin  18  includes a larger diameter lower section  52  which engages opening  30  of each FET assembly  16  and a smaller diameter upper section  54 . Alternatively, pin  18  may be a consistent diameter over its entire length and sized to fit within opening  30 . Pin  18  extends above the top-most FET assembly  16  to provide a stand-off to prevent FET array  12  or power assembly  10  from being mounted too closely to other objects within an enclosure. This will help prevent interference with the function of power assembly  10  and aid in cooling airflow about FET assemblies  16 . Pin  18  may be sized to extent no further above the top-most FET assembly than is necessary to aid assembly of FET array  12  and connection of pin  18  to items requiring power from FET array  12 . Current input pins  22  as shown only extend far enough above top-most FET assembly  16  to provide convenient connection to current sources, such as a power circuit, that are needed to supply FET banks  26  to create suitable power to be output by pin  18 . Heat sink  14  may also include a printed circuit board which includes the power circuit, allowing pins  22  to receive current from below the bottom-most FET assembly  16 . Gate control pins  20  only extend far enough above top-most FET assembly  16  to aid in connection with a control circuit mounted elsewhere in the electronic device to which FET assembly  10  is supplying power. Pins  20  may also extend further above the top-most FET assembly  16 . Alternatively, heat sink  14  may include a printed circuit board which includes the control circuit, allowing gate control pins  20  to receive gate switching instructions from below the bottom-most FET array  16 . 
   Pins  20  and  22  are shown the same length. Pins  22  are seated against heat sink  14  in power assembly  10  to provide a heat path from the heat generating FET banks  26  to heat sink  14 . Pins  20  are mounted offset from heat sink  14  so that there is no electrical connectivity between pins  20  and heat sink  14 . As noted above, if heat sink  14  includes a printed circuit board with a power input circuit or a gate control circuit, pins  22  and  20 , respectively, may be electrically connected with heat sink  14 . Similarly, pin  18  may be mounted similarly vertically offset from heat sink  14 . A spacer or electrically insulative pad  56  may also be mounted between pin  18  and heat sink  14  to ensure that no output power is directed into heat sink  14  rather being directed to another electrical element requiring power to operate. By offsetting the power and current handling pins  18  and  20  from heat sink  14 , heat sink  14  may be made from a metallic material, such as aluminum or other common heat sink materials, without concern regarding the dielectric properties of the material. 
   As shown, pins  20  are not involved in the transfer of power or electrical current to or from FET banks  26 . Rather, pins  22  are used primarily to control transfer heat generated by FET banks  26  to heat sink  14 . Additional heat transfer to heat sink  14  may come through insulative pads  24  and  56 , although pads  24  and  56  may provide some degree of thermal as well as electrical insulation. Alternatively, pins  18 ,  20  and  22  may be electrically connected to an electrical circuit member positioned atop heat sink  14  but electrically insulated from heat sink  14 . Such a circuit member may be thermally bonded to heat sink  14  and permit pins  18  and  20  to be used as additional conduits to permit heat flow from FET assemblies  16  to heat sink  14 . In such an alternative arrangement, current input pins  22  may be thermally isolated from heat sink  14 , if the additional thermal transfer capacity is not required. 
   As shown in  FIG. 4 , FET assembly  16  has FET banks  26  mounted to a bottom surface  40  of circuit board  28 . Alternatively, FET banks  26  could be mounted to a top surface  42  (shown in  FIG. 7 ). 
     FIG. 8  is a schematic diagram of an FET assembly  116 , which may be used with FET array  12  and power assembly  10 . FET assembly  116  may be similar in layout and function to FET assembly  16 , described above. FET assembly  116  includes a pair of FET banks  26 , labeled A and B, a pair of gate control pins  20 , labeled A and B, a pair of switches  118 , labeled A and B, a plurality of current input pins  22 , and a power output pin  18 . Switches  118  are mounted to circuit board  28 . Pins  22  are electrically connected to a current source. Pin  18  is electrically connected to a device or circuit requiring power. Pins  22  are electrically connected to each of the FET banks  26  A and B. Switches  118  A and B are connected to the corresponding gate control pin  20  A and B, respectively. Flow of power from either of FET banks  26  A and B is determined by the state of switches  118  A and B. The state of switches  118  A and B is controlled by commands set through gate control pins  20  A and B, respectively, by the control circuit. Switches  118  A and B may operate in a complimentary fashion, so that pin  18  receives power from one of the FET banks  26  but is prevented from being left without power or from receiving power from both FET banks simultaneously. 
   To control power flow to pin  18 , the control circuit provides commands through pins  20  to switches  118  to move to a high state (closed) or to a low state (open). When switch  118 A is moved to high, switch  118 B is moved to low, and current flows from pins  22  into FET bank  26 A and to pin  18 . When switch  118 A is moved to low, switch  118 B is moved to high and current flows from pins  22  into FET bank  26 B and to pin  18 . 
   Referring now to  FIGS. 5 to 7 , a method of assembling FET array  12  is illustrated. An assembly jig or fixture  32  includes a plurality of posts  34  for orienting and positioning FET assemblies  16  one atop the other. As shown in  FIG. 8 , posts  34  are arranged to cooperate with features of circuit board  28 , such as a recess  44  (shown in  FIG. 4 ) and an end  46  (shown in  FIG. 4 ) opposite from a tab  48  where opening  30  is located. A further post  34  engages a side  50  (shown in  FIG. 4 ). Posts  34  cooperate with recess  44 , end  46  and side  50  to align FETs assemblies  16  so that openings  29  and  30  of the assemblies are coaxially aligned. This alignment allows pins  18 , 20  and  22  to be positioned within these openings. 
   To assemble FET array  12 , a first pad  24  is placed on a base  36  of assembly fixture  32 . A first FET assembly  16  is placed between posts  34  atop of the pad  24  on fixture base  36 . A second pad  24  is placed on the first FET assembly  16  and a second FET assembly  16  is placed on the second pad  24 . This process continues until the desired number of FET assemblies  16  have been positioned between posts  34  atop base  36 . Pins  20  and  22  may be inserted after all FET assemblies  16  have been positioned on base  36  or may be inserted earlier in the assembly process. Pin  18  may also be inserted after all FET assemblies  16  have been positioned or earlier in the assembly process. Pad  56  is positioned between pin  18  and base  34 . 
   Once all FET assemblies  16  and pins  18 ,  20  and  22  have been positioned atop base  36 , a top  38  of assembly fixture  32  is placed on posts  34 . Top  38  includes a lower extension  58  which extends from a lower surface  60  of top  38  the distance that pins  20  are desired to extend above the top-most FET assembly  16 . Top  38  also includes an opening  62  into which upper portion  54  of pin  18  may extend. Top further includes a plurality of openings  64  into which posts  34  may extend. As shown, top  38  includes two openings  64  for receiving two of the three posts  34  and a recess  66  permitting the third post  34  to pass alongside top  38 . Base  34  includes a pair of raised seats  68  which are positioned beneath openings  29  for receiving pins  20 . Seats  68  provide the desired offset of pins  20  above heat sink  14  when FET array  12  is included within power assembly  10 . 
   Extension  58 , opening  62  and openings  64  cooperate to permit top  38  to positioned on base  36  of fixture  32  with extension  58  atop the top-most FET assembly  16 . Extension  58  compresses the FET assemblies  16  and pads  24  together, and lower surface  60  engages pins  20  and compresses pins  20  against seats  68 . While these components are so held within fixture  32 , they may be soldered together to form FET array  12 . Solder applied to pins  18  and  20  will aid the electrical connection of the pins with FET banks  26  and traces of circuit board  28  while solder applied to pins  22  will aid the mechanical and thermal connection of pins  22  to circuit board  28 . Alternatively, pins  22  may be sized to be require only a press or friction fit, and not require solder. As a further alternative, other mechanical or chemical bonding agents may be used to connect pins  22  within FET array  12 . 
   Once FET assemblies  16  have been positioned with respect to pins  18 ,  20  and  22 , and fixed in place, either by bonding, soldering, friction, or other mechanical linkage, top  38  is removed from about pins  34  of base  36  and the FET array  12  may be removed from base  36 . At this stage, heat sink  14  may be bonded or attached to FET array  12  to form a power assembly  10 . Alternatively, heat sink  14  could be pre-positioned within a device where a power supply is desired and power array  12  positioned atop heat sink  14 . 
   While configurations of FET assemblies  16  are shown with two FET banks  26 , more or fewer FET banks  26  may be included on each FET assembly  16 . Similarly, four FET assemblies  16  are shown in FET array  12 , and more or fewer FET arrays  12  may be used. The number of FETs  26  and/or the number of FET assemblies  16  included in each FET array  12  will typically be determined based on the power requirements of the device or devices that FET array  12  will be supplying. 
   Note that, except where otherwise stated, phrases such as, for example, “connected to” mean “connected directly to” or “connected indirectly to”. 
   Also note that, except where otherwise stated, terms such as, for example, “comprises”, “has”, “includes”, and all forms thereof, are considered open-ended, so as not to preclude additional elements and/or features. 
   While there have been shown and described various embodiments, it will be understood by those skilled in the art that the present invention is not limited to such embodiments, which have been presented by way of example only, and that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is limited only by the appended claims and equivalents thereto.