Abstract:
A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2015-0054558, filed on Apr. 17, 2015, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus. 
         [0004]    2. Related Art 
         [0005]    In general, semiconductor apparatuses are mass-produced after a large number of tests. 
         [0006]    A semiconductor apparatus is tested in a wafer state and a package state. When the semiconductor apparatus in the wafer state is tested, a probing pad included in the semiconductor apparatus is coupled to a test device. 
         [0007]    The test device includes a limited number of lines for coupling the semiconductor apparatus. Thus, when the number of lines coupled to one semiconductor apparatus is reduced, a larger number of semiconductor apparatuses can be tested at a time. 
       SUMMARY 
       [0008]    In an embodiment of the present disclosure, a semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas. 
         [0009]    In an embodiment of the present disclosure, a semiconductor apparatus may include: a data storage group including a first data storage area activated when both of a first channel select signal and a first clock enable signal are enabled, a second data storage area activated when both of a second channel select signal and a second clock enable signal are enabled, a third data storage area activated when both of the first channel select signal and the second clock enable signal are enabled, and a fourth data storage area activated when both of the second channel select signal and the first clock enable signal are enabled; first and second channel select pads configured to transmit the first channel select signal to the first and third data storage areas, respectively; third and fourth channel select pads configured to transmit the second channel select signal to the second and fourth data storage areas, respectively; first and second clock enable pads configured to transmit the first clock enable signal to the first and fourth data storage areas, respectively; and third and fourth clock enable pads configured to transmit the second clock enable signal to the second and third data storage areas, respectively. 
         [0010]    In an embodiment of the present disclosure, a semiconductor apparatus may include: a data storage group including first to eighth data storage areas; a first channel select pad configured to transmit a channel select signal to the first and third data storage areas; a first inverting unit configured to invert the channel select signal inputted from the first channel select pad and transmit the inverted channel select signal to the second and fourth data storage areas; a first clock enable pad configured to transmit a clock enable signal to the first and third data storage areas; a second inverting unit configured to invert the clock enable signal inputted from the first clock enable pad and transmit the inverted clock enable signal to the second and fourth data storage areas; a second channel select pad configured to transmit the channel select signal to the sixth and eighth data storage areas; a third inverting unit configured to invert the channel select signal inputted from the second channel select pad and transmit the inverted channel select signal to the fifth and seventh data storage areas; a second clock enable pad configured to transmit the clock enable signal to the fifth and seventh data storage areas; and a fourth inverting unit configured to invert the clock enable signal inputted from the second clock enable pad and transmit the inverted clock enable signal to the sixth and eighth data storage areas. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0012]      FIG. 1  is a configuration diagram of a semiconductor apparatus according to an embodiment of the present disclosure; 
           [0013]      FIG. 2  is a configuration diagram of a semiconductor apparatus according to an embodiment of the present disclosure; and 
           [0014]      FIGS. 3 and 4  are configuration diagrams illustrating connection between a test device and the semiconductor apparatus according to the embodiment of the present disclosure. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Hereinafter, a semiconductor apparatus according to the present disclosure will be described below with reference to the accompanying drawings through exemplary embodiments. 
         [0016]    As illustrated in  FIG. 1 , a semiconductor apparatus  100  according to an embodiment of the present disclosure may include a data storage group  110 , first to fourth channel select pads PT_cs 1  to PT_cs 4 , and first to fourth clock enable pads PT_cke 1  to PT_cke 4 . 
         [0017]    The data storage group  110  may include first to eighth data storage areas  101  to  108 . 
         [0018]    The first channel select pad PT_cs 1  may be coupled to the first data storage area  101  and the third data storage area  103 . 
         [0019]    The second channel select pad PT_cs 2  may be coupled to the second data storage area  102  and the fourth data storage area  104 . 
         [0020]    The third channel select pad PT_cs 3  may be coupled to the sixth data storage area  106  and the eighth data storage area  108 . 
         [0021]    The fourth channel select pad PT_cs 4  may be coupled to the fifth data storage area  105  and the seventh data storage area  107 . 
         [0022]    The first clock enable pad PT_cke 1  may be coupled to the first data storage area  101  and the third data storage area  103 . 
         [0023]    The second clock enable pad PT_cke 2  may be coupled to the second data storage area  102  and the fourth data storage area  104 . 
         [0024]    The third clock enable pad PT_cke 3  may be coupled to the fifth data storage area  105  and the seventh data storage area  107 . 
         [0025]    The fourth clock enable pad PT_cke 4  may be coupled to the sixth data storage area  106  and the eighth data storage area  108 . 
         [0026]    At this time, the first and third channel select pads PT_cs 1  and PT_cs 3  may receive the same channel select signal C_s 1  (refer to  FIG. 3 ), or receive different channel select signals C_s 1  and C_s 3  (refer to  FIG. 4 ). The second and fourth channel select pads PT_cs 2  and PT_cs 4  may receive the same channel select signal C_s 2  (refer to  FIG. 3 ), or receive different channel select signals C_s 2  and C_s 4  (refer to  FIG. 4 ). The first and third clock enable pads PT_cke 1  and PT_cke 3  may receive the same clock enable signal CKE_s 1  (refer to  FIG. 3 ), or receive different clock enable signals CKE_s 1  and CKE_s 3  (refer to  FIG. 4 ). The second and fourth clock enable pads PT_cke 2  and PT_cke 4  may receive the same clock enable signal CKE_s 2  (refer to  FIG. 3 ), or receive different clock enable signals CKE_s 2  and CKE_s 4  (refer to  FIG. 4 ). 
         [0027]    Each of the first to fourth channel select pads PT_cs 1  to PT_cs 4  and the first to fourth clock enable pads PT_cke 1  to PT_cke 4  may transmit a signal inputted thereto to the data storage area coupled thereto. 
         [0028]    Each of the first to eighth data storage areas  101  to  108  may be activated when both of the channel select signal and the clock enable signal inputted thereto are enabled. 
         [0029]    The operation of the semiconductor apparatus having the above-described configuration according to the embodiment of the present disclosure will be described with reference to  FIGS. 1, 3, and 4 . 
         [0030]    As illustrated in  FIG. 3 , the first and third channel select pads PT_cs 1  and PT_cs 3  of the semiconductor apparatus  100  according to the embodiment of the present disclosure may receive the same signal, that is, the first channel signal C_s 1  in common, and the second and fourth channel select pads PT_cs 2  and PT_cs 4  may receive the same signal, that is, the second channel select signal C_s 2  in common. Furthermore, the first and third clock enable pads PT_che 1  and PT_cke 3  may receive the same signal, that is, the first clock enable signal CKE_s 1 , and the second and fourth clock enable pads PT_che 2  and PT_che 4  may receive the same signal, that is, the second clock enable signal CKE_s 2 . At this time, the first and second channel select signals C_s 1  and C_s 2  and the first and second clock enable signals CKE_s 1  and CKE_s 2  may be outputted from a test device  200  outside the semiconductor apparatus  100 . 
         [0031]    The first to fourth channel select pads PT_cs 1  to PT_cs 4  and the first to fourth clock enable pads PT_cke 1  to PT_cke 4  may transmit signals C_s 1 , C_s 2 , CKE_s 1 , and CKE_s 2  received from the test device  200  to the data storage group  110 . 
         [0032]    As illustrated in  FIG. 1 , the data storage group  110  may include first to eighth data storage areas  101  to  108 . 
         [0033]    The first channel select signal C_s 1  inputted from the first channel select pad PT_cs 1  may be inputted to the first data storage area  101  and the third data storage area  103 . 
         [0034]    The first channel select signal C_s 1  inputted from the third channel select pad PT_cs 3  may be inputted to the sixth data storage area  106  and the eighth data storage area  108 . 
         [0035]    The second channel select signal C_s 2  inputted from the second channel select pad PT_cs 2  may be inputted to the second data storage area  102  and the fourth data storage area  104 . 
         [0036]    The second channel select signal C_s 2  inputted from the fourth channel select pad PT_cs 4  may be inputted to the fifth data storage area  105  and the seventh data storage area  107 . 
         [0037]    The first clock enable signal CKE_s 1  inputted from the first clock enable pad PT_cke 1  may be inputted to the first data storage area  101  and the third data storage area  103 . 
         [0038]    The first clock enable signal CKE_s 1  inputted from the third clock enable pad PT_cke 3  may be inputted to the fifth data storage area  105  and the seventh data storage area  107 . 
         [0039]    The second clock enable signal CKE_s 2  inputted from the second clock enable pad PT_cke 2  may be inputted to the second data storage area  102  and the fourth data storage area  104 . 
         [0040]    The second clock enable signal CKE_s 2  inputted from the fourth clock enable pad PT_cke 4  may be inputted to the sixth data storage area  106  and the eighth data storage area  108 . 
         [0041]    At this time, only one of the first and second channel select signals C_s 1  and C_s 2  may be enabled, and the other one may be disabled. Furthermore, only one of the first and second clock enable signals CKE_s 1  and CKE_s 2  may be enabled, and the other one may be disabled. 
         [0042]    Each of the first to eighth data storage areas  101  to  108  may be activated when both of the channel select signal and the clock enable signal inputted thereto are enabled. 
         [0043]    For example, when both of the first channel select signal C_s 1  and the first clock enable signal CKE_s 1  are enabled, the first and third data storage areas  101  and  103  may be activated. When both of the first channel select signal C_s 1  and the second clock enable signal CKE_s 2  are enabled, the sixth and eighth data storage areas  106  and  108  may be activated. When both of the second channel select signal C_s 2  and the first clock enable signal CKE_s 1  are enabled, the fifth and seventh data storage areas  105  and  107  may be activated. When both of the second channel select signal C_s 2  and the second clock enable signal CKE_s 2  are enabled, the second and fourth data storage areas  102  and  104  may be activated. 
         [0044]    The semiconductor apparatus according to the embodiment of the present disclosure may input the same signal to a pair of pads among the plurality of pads, in order to selectively activate a plurality of data storage areas. 
         [0045]    As illustrated in  FIG. 4 , the semiconductor apparatus  100  according to the embodiment of the present disclosure may input the first to fourth channel select signals C_s 1  to C_s 4  to the first to fourth channel select pads PT_cs 1  to PT_cs 4 , respectively. Furthermore, the semiconductor apparatus  100  may input the first to fourth clock enable signals CKE_s 1  to CKE_s 4  to the first to fourth clock enable pads PT_cke 1  to PT_cke 4 , respectively. At this time, the first to fourth channel select signals C_s 1  to C_s 4  and the first to fourth clock enable signals CKE_s 1  to CKE_s 4  may be outputted from the test device  200  outside the semiconductor apparatus  100 . 
         [0046]    The first to fourth channel select pads PT_cs 1  to PT_cs 4  and the first to fourth clock enable pads PT_cke 1  to PT_cke 4  may transmit signals C_s 1 , C_s 2 , CKE_s 1 , and CKE_s 2  received from the test device  200  to the data storage group  110 . 
         [0047]    As illustrated in  FIG. 1 , the data storage group  110  may include the first to eighth data storage areas  101  to  108 . 
         [0048]    The first channel select signal C_s 1  inputted from the first channel select pad PT_cs 1  may be inputted to the first data storage area  101  and the third data storage area  103 . 
         [0049]    The second channel select signal C_s 2  inputted from the second channel select pad PT_cs 2  may be inputted to the second data storage area  102  and the fourth data storage area  104 . 
         [0050]    The third channel select signal C_s 3  inputted from the third channel select pad PT_cs 3  may be inputted to the sixth data storage area  106  and the eighth data storage area  108 . 
         [0051]    The fourth channel select signal C_s 4  inputted from the fourth channel select pad PT_cs 4  may be inputted to the fifth data storage area  105  and the seventh data storage area  107 . 
         [0052]    The first clock enable signal CKE_s 1  inputted from the first clock enable pad PT_cke 1  may be inputted to the first data storage area  101  and the third data storage area  103 . 
         [0053]    The second clock enable signal CKE_s 2  inputted from the second clock enable pad PT_cke 2  may be inputted to the second data storage area  102  and the fourth data storage area  104 . 
         [0054]    The third clock enable signal CKE_s 3  inputted from the third clock enable pad PT_cke 3  may be inputted to the fifth data storage area  105  and the seventh data storage area  107 . 
         [0055]    The fourth clock enable signal CKE_s 4  inputted from the fourth clock enable pad PT_cke 4  may be inputted to the sixth data storage area  106  and the eighth data storage area  108 . 
         [0056]    At this time, only one of the first to fourth channel select signals C_s 1  to C_s 4  may be enabled, and the others may be disabled. Furthermore, only one of the first to fourth clock enable signals CKE_s 1  to CKE_s 4  may be enabled, and the others may be disabled. 
         [0057]    Each of the first to eighth data storage areas  101  to  108  may be activated when both of the channel select signal and the clock enable signal inputted thereto are enabled. 
         [0058]    For example, when both of the first channel select signal C_s 1  and the first clock enable signal CKE_s 1  are enabled, the first and third data storage areas  101  and  103  may be activated. When both of the second channel select signal C_s 2  and the second clock enable signal CKE_s 2  are enabled, the second and fourth data storage areas  102  and  104  may be activated. When both of the third channel select signal C_s 3  and the fourth clock enable signal CKE_s 4  are enabled, the sixth and eighth data storage areas  106  and  108  may be activated. When both of the fourth channel select signal C_s 4  and the third clock enable signal CKE_s 3  are enabled, the fifth and seventh data storage areas  105  and  107  may be activated. 
         [0059]    As such, the semiconductor apparatus  100  according to the embodiment of the present disclosure may selectively activate the data storage areas even though different signals are inputted to the respective pads from the test device  200 , and selectively activate the data storage areas even though the same signal is inputted to a pair of pads in common. 
         [0060]    As illustrated in  FIG. 2 , a semiconductor apparatus  100 - 1  according to an embodiment of the present disclosure may include first and second channel select pads PT_csA and PT_csB, first and second clock enable pads PT_ckeA and PT_ckeB, and a data storage group  110 - 1 . 
         [0061]    The data storage group  110 - 1  may include first to eighth data storage areas  101 - 1  to  108 - 1  and first to fourth inverting units IV 1  to IV 4 . 
         [0062]    The first channel select pad PT_csA may be coupled to the first data storage area  101 - 1  and the third data storage area  103 - 1 . 
         [0063]    The first inverting unit IV 1  may be coupled to the first channel select pad PT_csA, the second data storage area  102 - 1 , and the fourth data storage area  104 - 1 . At this time, the first inverting unit IV 1  may include an inverter which inverts the signal inputted from the first channel select pad PT_csA and transmits the inverted signal to the second and fourth data storage areas  102 - 1  and  104 - 1 . 
         [0064]    The second channel select pad PT_csB may be coupled to the sixth data storage area  106 - 1  and the eighth data storage area  108 - 1 . 
         [0065]    The third inverting unit IV 3  may be coupled to the second channel select pad PT_csB, the fifth data storage area  105 - 1 , and the seventh data storage area  107 - 1 . At this time, the third inverting unit IV 3  may include an inverter which inverts the signal inputted from the second channel select pad PT_csB and transmits the inverted signal to the fifth and seventh data storage areas  105 - 1  and  107 - 1 . 
         [0066]    The first clock enable pad PT_ckeA may be coupled to the first data storage area  101 - 1  and the third data storage area  103 - 1 . 
         [0067]    The second inverting unit IV 2  may be coupled to the first clock enable pad PT_ckeA, the second data storage area  102 - 1 , and the fourth data storage area  104 - 1 . At this time, the second inverting unit IV 2  may invert a signal inputted from the first clock enable pad PT_ckeA and transmit the inverted signal to the second and fourth data storage areas  102 - 1  and  104 - 1 . 
         [0068]    The second clock enable pad PT_ckeB may be coupled to the fifth data storage area  105 - 1  and the seventh data storage area  107 - 1 . 
         [0069]    The fourth inverting unit IV 4  may be coupled to the second clock enable pad PT_ckeB, the sixth data storage area  106 - 1 , and the eighth data storage area  108 - 1 . At this time, the fourth inverting unit IV 4  may include an inverter which inverts the signal inputted from the second channel select pad PT_csB and transmits the inverted signal to the sixth and eighth data storage areas  106 - 1  and  108 - 1 . 
         [0070]    At this time, the first and second channel select pads PT_csA and PT_csB may receive a channel select signal (not illustrated) in common. The first and second clock enable pads PT_ckeA and PT_ckeB may receive a clock enable signal (not illustrated) in common. 
         [0071]    Each of the first to eighth data storage areas  101  to  108  may be activated when both of two signals inputted thereto are at a high level. 
         [0072]    The operation of the semiconductor apparatus having the above-described configuration according to the embodiment of the present disclosure will be described as follows. 
         [0073]    When signals (for example, channel select signals) inputted from the first and second channel select pads PT_csA and PT_csB are at a high level and signals (for example, clock enable signals) inputted from the first and second clock enable pads PT_ckeA and PT_ckeB are at a high level, the first and third data storage areas  101 - 1  and  103 - 1  may be activated. 
         [0074]    When the signals (for example, channel select signals) inputted from the first and second channel select pads PT_csA and PT_csB are at a high level and the signals (for example, clock enable signals) inputted from the first and second clock enable pads PT_ckeA and PT_ckeB are at a low level, the first sixth and eighth data storage areas  106 - 1  and  108 - 1  may be activated. 
         [0075]    When the signals (for example, channel select signals) inputted from the first and second channel select pads PT_csA and PT_csB are at a low level and the signals (for example, clock enable signals) inputted from the first and second clock enable pads PT_ckeA and PT_ckeB are at a high level, the fifth and seventh data storage areas  105 - 1  and  107 - 1  may be activated. 
         [0076]    When the signals (for example, channel select signals) inputted from the first and second channel select pads PT_csA and PT_csB are at a low level and the signals (for example, clock enable signals) inputted from the first and second clock enable pads PT_ckeA and PT_ckeB are at a low level, the second and fourth data storage areas  102 - 1  and  104 - 1  may be activated. 
         [0077]    The semiconductor apparatus  100 - 1  according to the embodiment of the present disclosure can selectively activate the data storage areas like the semiconductor apparatus  100 , even though the number of pads is reduced to the half of the number of pads included in the semiconductor apparatus  100  illustrated in FIG. 
         [0078]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor apparatus described herein should not be limited based on the described embodiments. Rather, the semiconductor apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.