Abstract:
An electrostatic discharge (ESD) protection circuit is disclosed, which comprises an ESD detection circuit and protection switches. If an ESD event occurs, the ESD detection circuit turns off the protection switches so as to protect an application circuit provided in integrated circuits (IC) from being damaged by the electrostatic discharge, and if not, the ESD detection circuit turns on the protection switches so as to make the application circuit provided in integrated circuits (IC) function normally.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of Invention 
         [0002]    The present invention relates to an electrostatic discharge protection circuit, and in particular, to an electrostatic discharge protection circuit provided in integrated circuits (IC) for electrostatic discharge protection. 
         [0003]    2. Description of Related Art 
         [0004]    In integrated circuits (IC), a plurality of devices are formed of metal oxide semiconductor (being referred to as MOS, hereinafter). However, gate oxides of such MOS devices are likely to be punched through by an abrupt high voltage caused by electrostatic discharge (being referred to as ESD, hereinafter), and a failure may be caused due to such punch-through. Therefore, it is necessary to set up in the IC an ESD protection circuit for protecting the whole IC from being damaged by external ESD. 
         [0005]    In general, the ESD circuit eliminates electrostatic electricity by driving electrostatic electricity out of the IC in order to protect the IC from being damaged by electrostatic electricity. In other words, if an ESD event occurs, the ESD protection circuit can protect the IC from damage caused by the ESD event by means of discharging the electrostatic electricity through a path of a supply voltage VDD or VSS. However, as the microminiaturization of semiconductor process is improved, the thickness of the gate oxide of the MOS transistor is further reduced. Also, the prior art ESD protection circuits cannot protect the metal oxides of MOS transistors having reduced thickness from a high voltage environment. In such circumstances, lifetimes of MOS transistor are adversely reduced. 
       SUMMARY OF THE INVENTION 
       [0006]    In view of the above, an object of the present invention is to provide an ESD protection circuit, which can protect an application circuit from an instantaneous high voltage during an ESD event but does not affect a normal operation of the application circuit if the application circuit operates in a normal state. 
         [0007]    Also, the object of the present invention is to provide an ESD protection circuit for increasing lifetime of an application circuit. 
         [0008]    The present invention provides an ESD protection circuit provided in integrated circuits having an input pad and an application circuit, comprising: an ESD detection circuit for detecting whether there is an ESD event occurred at the input pad, and outputting a detection signal based on the detection; and a protection switch being coupled between the input pad and the application circuit, and being turned on/off based on the detection signal, wherein the protection switch is turned off by the detection signal so as to disconnect the input pad from the application circuit when the ESD event occurs, and the protection switch is turned on by the detection signal so as to form a short circuit between the input pad and the application circuit when no ESD event occurs. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    These and other features, aspects, and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention, with reference to accompanying drawings, in which 
           [0010]      FIG. 1  illustrates a schematic circuit diagram of an ESD protection circuit according to an embodiment of the present invention and an application in which it is provided in integrated circuits. 
       
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0011]    The embodiment according to the present invention will be described, with reference to  FIG. 1 .  FIG. 1  illustrates a schematic circuit diagram of an ESD protection circuit according to the embodiment of the present invention. As shown in  FIG. 1 , integrated circuits  100  include an application circuit  102 , a plurality of input pads  1031  to  103   n  (only two pads are shown in the figure), an electrostatic discharge (ESD) detection circuit  104 , and a plurality of protection switches  1071  to  107   n  (only two switches are shown in the figure). The ESD detection circuit  104  and the plurality of protection switches  1071  to  107   n  form the ESD protection circuit. For purpose of clarity, only two input pads  1031  and  1032  and only two protection switches  1071  and  1072  are given as examples for explanations. 
         [0012]    In general, each of the input pads  1031  to  1032  is coupled to the ESD detection circuit  104  via a discharging circuit formed by a diode and a transistor. Normally, the detection circuit  104  includes a discharge circuit and a detection circuit. Here, the discharge circuit corresponds to an NMOS transistor M 4  and a diode D 3 , and the detection circuit is mainly formed by a PMOS transistor M 3 , a resistor R 1  coupled to the transistor M 3 , and a capacitor P 1  coupled to a node N 1 , as shown in  FIG. 1 . According to the embodiment of this invention, for example, the capacitor P 1  may be implemented with a transistor. It should be noted that coupling relations among all of the elements of the detection circuit  104  are clearly illustrated in  FIG. 1  and their associated descriptions will be omitted here. In addition, the ESD detection circuit  104  may be implemented in various forms, and this invention is not limited to the detection circuit  104  illustrated in  FIG. 1 . 
         [0013]    As illustrated in  FIG. 1 , the protection switches  1071  and  1072  are implemented with MOS transistors. If NMOS transistors are used as the protection switch  1071  and  1072 , a drain of the NMOS transistor  1071  is coupled to the input pad  1031  and a source of the NMOS transistor  1071  is coupled to a gate of an MOS transistor  1021  in the application circuit  102 , a drain of the NMOS transistor  1072  is coupled to the input pad  1032  and a source of the NMOS transistor  1072  is coupled to a gate of an MOS transistor  1022  in the application circuit  102 , and gates of the NMOS transistors  1071  and  1072  receive a detection signal a from the ESD detection circuit  104 . 
         [0014]    When the detection signal is equal to 0 (low level), the protection switches  1071  and  1072  are in a high resistance state or form an open circuit, and accordingly isolate the application  102  from signals input from input pads. When the detection signal a is equal to 1 (high level), the protection switches  1071  and  1072  are in a conductive state or form a short circuit, and accordingly couple the application circuit  102  to the input pads. Here, since the NMOS transistors are used as the protection switches  1071  and  1072 , the MOS transistors in the open circuit state can function as resistors having resistance about 100 M Ω or higher. 
         [0015]    Next, an operation relation between the detection signal a generated by the ESD detection circuit  104  and the protection switches  1071  to  107   n  during an ESD event is further explained. 
         [0016]    During the ESD event, if the electrostatic voltage V ESD  applied to the input pad  1031  is a positive voltage, the diode D 1  coupled to the input pad can be conducted and therefore static charges can flow to the ground voltage VSS through the transistor M 4  in the detection circuit  104 . Such electrostatic discharging route is indicated by a dash line with an arrow I ESD  in  FIG. 1 . 
         [0017]    According to this invention, since the detection signal a output from the node N 1  is logic 0 when the ESD event is occurred, the gate of the transistor M 4  receives a signal (logic 1) inverted to the detection signal a and thus is conducted to make the ESD operation executed. At the same time, the protection switches  1071  and  1072  receive the detection signal a (logic 0) so as to be kept in the open circuit state, and accordingly function as resistors having high resistance between the input pad  1031  and the application circuit  102 . Thus, the application circuit  102  can be protected from being affected by the static electricity. After the static electricity is discharged through the transistor M 4 , the transistor M 3  is conducted, the node N 1  becomes to be in logic 1, and the protection switches are conducted so as to be in a short circuit state. Therefore, the application circuit  102  can normally receive the input signals from the input pads  1031  and  1032 . 
         [0018]    Although one MOS transistor is used as the protection switch, this invention is not limited to this. For example, the protection switch may be formed by a plurality of transistors, which may be connected in series or in parallel. In addition, the application circuit  102  may be an analog circuit or a digital circuit, and this invention is not limited to the circuit shown in  FIG. 1 . 
         [0019]    According to the present invention, the protection switches can be turned on/off based on the detection signal from the ESD detection circuit, thereby to significantly reduce the instantaneous electrostatic voltage applied to circuits under protection, and to increase the lifetime of the application circuit. Also, if the integrated circuits operate normally, the protection switches remain conducted without affecting the normal operation of the integrated circuits. 
         [0020]    While the present invention has been described with reference to exemplary embodiments, this invention is not limited to the specific details disclosed in the above. Therefore, various changes, modifications, alternatives, etc. may be made by those skilled in this art without departing the spirits of the present invention and the scope defined by the appended claims and their equivalents.