Abstract:
One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.

Description:
BACKGROUND  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to the process of simulating digital circuits. More specifically, the present invention relates to a method and an apparatus for calibrating parameters of a model to be used in a simulation of a digital circuit.  
           [0003]    2. Related Art  
           [0004]    As integrated circuits continue to increase in density and operating speed, they are becoming more sensitive to noise caused by inductive and capacitive coupling between signal lines. This noise can interfere with the operation of an integrated circuit and hence must be considered during the process of routing of signal lines within the digital circuit.  
           [0005]    Circuit designers typically use a computer-based model of a digital circuit to determine the effects of various circuit parameters, including inductive and capacitive noise, on performance of the digital circuit. The results of these circuit simulations can be used to verify that the digital circuit meets performance targets, and to iteratively adjust the design of the digital circuit.  
           [0006]    Unfortunately, there presently exists no accurate way to determine the magnitude of the noise coupling parameters to be used in such a computer-based model. This leads circuit designers to make rough estimates of such noise coupling parameters or to ignore such parameters in developing a model. Hence, when the results determined from the model do not match the results measured from the physical circuit, there is no clear way to determine how to adjust the parameters to more accurately model the digital circuit.  
           [0007]    What is needed is a method and an apparatus for accurately calibrating parameters to be used in a simulation of a digital circuit.  
         SUMMARY  
         [0008]    One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The system operates by first fabricating a digital circuit for calibration purposes. Next, an input signal is applied to an aggressor net within the digital circuit. The system then measures how noise from the input signal affects the amplitude of a signal on a victim net within the digital circuit. Finally, the system adjusts parameters of the circuit model using the measured results.  
           [0009]    In a variation on this embodiment, measuring how noise affects the amplitude of the signal on the victim net involves using multiple level detectors to quantize the signal on the victim net. The system then digitizes the output of these level detectors.  
           [0010]    In a further variation, a given level detector includes a complementary metal oxide semiconductor inverter circuit.  
           [0011]    In a further variation, the detection level of a given level detector is established by adjusting the beta of the complementary metal oxide semiconductor inverter circuit.  
           [0012]    In a further variation, the system adjusts the beta by adjusting the ratio of ω p  to ω n .  
           [0013]    In a further variation, each level detector has a different beta.  
           [0014]    In a further variation, a given level detector is followed by a series of inverters, which amplify and shape an output pulse.  
           [0015]    In a further variation, digitizing the output of a given level detector involves latching the state of the last inverter of the series of inverters so that the state can be read to determine the output of the given level detector. 
       
    
    
     BRIEF DESCRIPTION OF THE FIGURES  
       [0016]    [0016]FIG. 1 illustrates a noise detecting circuit in accordance with an embodiment of the present invention.  
         [0017]    [0017]FIG. 2 illustrates the output of a noise detecting circuit in accordance with an embodiment of the present invention.  
         [0018]    [0018]FIG. 3 illustrates inverter transfer curves in accordance with an embodiment of the present invention.  
         [0019]    [0019]FIG. 4 illustrates an inverter circuit in accordance with an embodiment of the present invention.  
         [0020]    [0020]FIG. 5 is a flowchart illustrating the process of calibrating a circuit model in accordance with an embodiment of the present invention.  
         [0021]    [0021]FIG. 6 illustrates signals at various points within noise amplifier  106  in accordance with an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION  
       [0022]    The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.  
         [0023]    Noise Detecting Circuit  
         [0024]    [0024]FIG. 1 illustrates a noise detecting circuit in accordance with an embodiment of the present invention. The noise detecting circuit includes aggressor net  102 , victim net  104 , noise amplifier  106 , noise digitizer  108 , diodes  156  and  158 . Note that there exists inductive and capacitive coupling from aggressor net  102  into victim net  104 . Also note that diodes  156  and  158  limit the voltage extremes of noise signals coupled into victim net  104  so that the input circuits of noise amplifier  106  are not damaged.  
         [0025]    Noise amplifier  106  includes inverters  110 - 132 . Inverters  110 - 132  function as level detecting and pulse shaping circuits for several different levels of signal amplitude. For example, inverters  110 - 116  detect noise levels above 400 mV, inverters  118 - 124  detect signal amplitudes; above 500 mV, while inverters  126 - 132  detect signal amplitudes above 700 mV. Note that additional inverter chains can be added, if necessary, to detect other signal amplitudes.  
         [0026]    The first inverter in each of the chains ( 110 ,  118 , and  126 ) controls the detection level for the chain. Note that each of these first inverters adds a different β to detect a different signal amplitude level. For example, in one embodiment of the present invention, β is 0.04 for inverter  110 , 0.5 for inverter  118 , and 4 for inverter  126 .  
         [0027]    The remaining inverters in each chain shape any incoming signals into rectangular pulses for noise digitizer  108 . For example, in the embodiment of the present invention illustrated in FIG. 1, inverters  112 ,  120 , and  128  each have a β of 17; inverters  114 ,  122 , and  130  each have a β of 0.5; and inverters  116 ,  124 , and  132  each have a β of 17. This combination provides acceptable pulses for noise digitizer  108  when noise is detected.  
         [0028]    The outputs of noise amplifier  106  are coupled to noise digitizer  108 . Specifically, the output of inverter  116  is coupled to transistor  134 , the output of inverter  124  is coupled to transistor  136 , and the output of inverter  132  is coupled to transistor  138 . Additional output inverters in noise amplifier  106  are similarly coupled to transistors in noise digitizer  108 .  
         [0029]    Noise digitizer  108  includes input transistors  134 ,  136 , and  138 ; latches  140 ,  142 , and  144 ; and output transistors  146 ,  148 , and  150 . The operation of noise digitizer  108  is controlled by write control signal  152  and read control signal  154 . Write control signal  152  turns on transistors  134 ,  136 , and  138  to sample the outputs of inverters  116 ,  124 , and  132 , respectively. When the input transistors are turned on, the state of inverters  116 ,  124 , and  132  is transferred to latches  140 ,  142 , and  144 , respectively.  
         [0030]    Latches  140 ,  142 , and  144  are formed using back-to-back inverters, which hold their input state even after write control signal  152  turns off the input transistors  134 ,  136 , and  138 . Read control signal  154  turns on output transistors  146 ,  148 , and  150  which makes the state of latches  140 ,  142 , and  144  available at outputs F 4 , F 5 , and F 7 , respectively.  
         [0031]    Noise Detecting Circuit Output  
         [0032]    [0032]FIG. 2 illustrates the output of a noise detecting circuit in accordance with an embodiment of the present invention. Outputs F 4 , F 5 , F 6 , and F 7  detect signal amplitudes of 400 mV, 500 mV, 600 mV, and 700 mV, respectively. Note that F 6  is not shown in FIG. 1 but would include similar circuitry to that used for generating F 4 , F 5 , and F 7 .  
         [0033]    As shown in FIG. 2, an input signal amplitudes of 300 mV results in signals F 4 , F 5 , F 6 , and F 7  all being zero. When the input signal amplitude is 400 mV, F 4  is one, while F 5 , F 6 , and F 7  are zero. Thus, an output of 1000 on F 4 , F 5 , F 6 , and F 7  indicates that the noise is at least 400 mV but is not 500 mV. Each increase of input noise level above the next threshold sets the next output to one. Thus, an output of 1110 on F 4 , F 5 , F 6 , and F 7  indicates that the signal amplitude is at least 600 mV but is not 700 mV, while an output of 1111 indicates that the signal amplitude is greater than 700 mV.  
         [0034]    Transfer Curves  
         [0035]    [0035]FIG. 3 illustrates inverter transfer curves in accordance with an embodiment of the present invention. FIG. 3 displays V OUT  VS V IN  for several values of β. V TN  indicates the threshold voltage for the N-type transistor while V TP  indicates the threshold voltage for the P-type transistor. V TN  indicates the lowest level of detectable noise, while V DD -V TP  indicates the highest level of detectable noise.  
         [0036]    The different levels of β control the detection level of the inverters. For example, when β is 0.1, a relatively small noise signal will cause the inverter to change state. When β is 10, however, a relatively large signal is needed to cause the inverter to change state. Controlling β, therefore, allows the inverters to be tailored to respond to specific levels of noise.  
         [0037]    Inverter Circuit  
         [0038]    [0038]FIG. 4 illustrates an inverter circuit in accordance with an embodiment of the present invention. As shown in FIG. 4, the inverter includes P-type transistor  402  and N type transistor  404 . The basic operation of the inverter is well known in the art and will not be discussed in detail herein. However, the method for establishing β for a given inverter is of interest. β is the ratio of the width parameter ω p  of the P-type transistor to the width parameter ω N  of the N-type transistor or ω P /ω N . Thus, controlling the detection levels in noise amplifier  106  involves simply adjusting the width parameters appropriately.  
         [0039]    Calibrating a Circuit  
         [0040]    [0040]FIG. 5 is a flowchart illustrating the process of calibrating a circuit model in accordance with an embodiment of the present invention. The system starts when a digital circuit is fabricated for calibration purposes (step  502 ). Next, an input signal is applied to an aggressor net within the digital circuit (step  504 ).  
         [0041]    Noise amplifier  106  then detects a signal that is coupled into a victim net within the digital circuit (step  506 ). After detecting the signal, the signal is quantized by noise amplifier  106  (step  508 ). Next, noise digitizer  108  digitizes the output of noise amplifier  106  (step  510 ). Finally, the digitized output from noise digitizer  108  is used to adjust the parameters of the circuit model (step  512 ). This can be accomplished by iteratively adjusting inductive and capacitive coupling parameters in the circuit model until the output of the model matches the measured output of the digital circuit.  
         [0042]    Signals  
         [0043]    [0043]FIG. 6 illustrates signals at various points within noise amplifier  106  in accordance with an embodiment of the present invention. Specifically, FIG. 6 illustrates signals with an amplitude of 500 mV on victim net  104 . The output of inverters  110 ,  118 , and  126  are shown. Note that these outputs depend on the β of the respective inverters. The dashed line on each chart illustrates the threshold voltage V T  of the following inverter. The output of inverters  112 ,  120 , and  128  are also shown. Note that the output of inverter  112  remains constant because the output of inverter  110  is below the V T  of inverter  112 . The outputs of inverters  120  and  128 , however, are rectangular pulses because the outputs of inverters  118  and  126 , respectively, are above V T .  
         [0044]    The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.