Abstract:
A short pulse rejection circuit is disclosed. The circuit comprises a signal transition detecting circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal transition detecting circuit is to output detecting pulses in response to any input pulse. The control signal generating circuit generates two control signals for capacitor charging and discharging in response to the detecting pulses. The capacitor resetting and charging circuit generates discharging and charging signals in response to two control signals. The charge pulse detecting circuit generates output enable pulse and outputting a short pulse rejected pulses in response to the charging signals and original input pulse.

Description:
FIELD OF INVENTION  
       [0001]     This invention relates to a circuit, more particularly, to a circuit having a signal detected and converted circuit, a control signal generating circuit, and a reset circuit in series connected, which provides a function of filtering those pulses having their pulse width narrower than a predetermined value but pass through the otherwise.  
       BACKGROUND OF INVENTION  
       [0002]     For integrated circuit is concerned, the role of the input/output (I/O) pad likely acts as a bridge which communicates the chip itself to another. An ideal I/O pad seems as a buffer without signal gain or degrade, as is shown in  FIG. 1   a  with an input terminal A and an output terminal Z. As a signal pulse imposes on the input terminal A, the signal fed into the buffer, usually even numbers of inverters, for time delay of about several neon-seconds, the output terminal Z should get the same pulse width as the original one.  
         [0003]     If a low pass filter is added to the I/O pad to make the I/O pad having function of filtering, it may result in malfunctioning. An example is shown in  FIG. 1    b  it shows a low pass filter I/O pad series connected with two inverters having a capacitor C in between, where “A” is an input terminal, “Z” being an output terminal, and V CP  is the terminals voltage of the capacitor C.  
         [0004]     Assuming forgoing low pass filter circuit is desired to filter those pulses having short pulse width, such as 20 ns and below, the filter may get a malfunction due to the situation described below. Supposing a first pulse H 1  having pulse width 15 ns is passed through the first inverter INV 1 , the signal charging the capacitor C to a voltage of V CP  is followed. Since the V CP  dose not reach the threshold voltage V TH  of the second inverter INV 2 , V Z =0 is resulted. Hence, the pulse H 1  had been filtered out successfully. Thereafter, V A  returns to its original level (e.g. 0) for a time duration L (e.g. 5 ns), and then the charges in the capacitor C, discharge through the first inverter INV 1 . However, if the capacitor C is not discharged completely within the time duration L, and a second pulse H 2  following H 1  is exerted on terminal A, the V CP  may still possibly attain to the threshold voltage of V TH  of the second inverter INV 2  even though the pulse width of the second pulse H 2  is small than 20 ns due to the residue charges in the capacitor C. In other words, the interval between pulses H 1  and H 2  becomes critical. Thus, take the time duration L=5 ns as an example, as shown in FIG  1   b , the pulse H 2  may make the V CP  to exceed V TH  while approaching the ending of the pulse H (it may be about 10 ns). As a result, an undesired pulse H 2  appears at the output terminal Z.  
         [0005]     An object of the present invention is thus to provide a circuit, which utilizes feed back signals associated with MOS (Metal-Oxide-Semiconductor) transistors, to reset the charging/discharging circuit. The high current drivability of the MOS makes the operation of fast charging/discharging possible, and prevents the malfunction due to residual charges.  
       SUMMARY OF THE INVENTION  
       [0006]     A short pulse rejection circuit is disclosed. The circuit comprises a signal detected and converted circuit, a control signal generating circuit, a capacitor resetting and charging circuit, and a charge pulse detecting circuit. The signal detected and converted circuit is to output detecting pulses in response to any input pulse transit. The control signal generating circuit generates two control signals for capacitor charging and discharging in response to the detecting pulses. The capacitor resetting and charging circuit generates discharging and charging signals in response to two control signals. The charge pulse detecting circuit generates output enable pulse and outputting a short pulse rejected pulses in response to the charging signals and original input pulse. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0007]     The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:  
         [0008]      FIG. 1   a  illustrates a traditional I/O pad the same as a buffer but can&#39;t serve as a signal filter.  
         [0009]      FIG. 1   b  illustrates a traditional I/O pad associated with a low pass filter to filter high frequency signal but it will fail to filter those signals providing with a very short time interval.  
         [0010]      FIG. 2  shows function block of circuit for short pulse rejection in accordance with the present invention.  
         [0011]      FIG. 3  shows short pulse rejection circuit in accordance with the present invention.  
         [0012]      FIG. 4  shows a pulses-timing diagram in response to the input signal in accordance with the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0013]     As forgoing descriptions in the prior art, an input/output pad associated with a simple RC (Resistor Capacitor) low pass circuit is not safe for filtering those high frequency noises, especially, as if an interval in between two high frequency noises is short. It is because that charges stored in the capacitor do not have enough time to discharge completely while the first noise is filtered and the second one followed within a short time. As a result, accumulated charges will make the second noise over a threshold condition, and thus resulted in malfunction. The present invention can overcome the problems.  
         [0014]     The functional blocks of the short pulse rejection circuit according to the present invention is shown in  FIG. 2 , the circuit includes a signal detected and converted circuit  100 , a control signal generating circuit  150 , a reset and charging circuit  200 , and a capacitor pulse detected and signal outputting circuit  250 , in series connected in order. The signal detected and converted circuit  100  has a signal receiving terminal IN and an output terminal  110 . The circuit  100  generates a detected pulse at the output terminal  110  while a pulse signal received by the signal-receiving terminal IN is in occurrence with a raising edge or falling edge. In response to the detected pulse, two control signals CP and CK 0  are generated by the control signal generating circuit  150 . The reset and charging circuit  200  providing a function of fast charging or discharging the capacitor  204 , as shown in  FIG. 4  according to signals CP and CK 0 . The capacitor pulse detected and signal outputting circuit  250  then respond the signal IN and the charges in the capacitor  204  to determine if the terminal voltage of the capacitor  204  over a predetermined threshold or not. If so, a resulted pulse OUT having a short pulse rejection is outputted in response to receiving signal IN.  
         [0015]     Referring to  FIG. 4 , a pulses-timing diagram is shown. The signal detected and converted circuit  100  generates a detected pulse signal X 01  to the control signal generating circuit  150  while the input signal IN has its edges either raising or falling. Otherwise, the X 01  keeps at voltage level  0 .  
         [0016]     Please refer to  FIG. 3 . The signal detected and converted circuit  100  includes a first CMOS  102  with an input terminal for receiving a signal IN, an output terminal connected with a first signal delay circuit  105  and input terminal of an Exclusion Or gate (XOR)  106 . The first signal delay circuit  105  may be composed of even numbers of inverters to generate a time delayed signal. The signal outputted from the CMOS  102  that is delayed about t 1  time unit by the first signal delay circuit  105  is fed to the second input terminal of XOR  106 . Hence, as is shown in  FIG. 4 , if the input pulse signal IN with an edge transit no matter what the situation is low to high or high to low, the XOR will output a pulse signal XO 1  of about t 1  in pulse width. Preferably, the delayed time t 1  done by first signal delay circuit  105  is limited within 2 ns. The fact of time delayed too long may cause the current pulse signal with the previous pulse signal proceeding XOR operation but not the signal INX 2  XOR the signal INX 1 .  
         [0017]     The control signal generating circuit  150  includes a first inverter  151 , a second delay circuit  152 , a second inverter  153 , a third inverter  154 , an edge-trigger-reset D flip-flop  155 , and a second CMOS  162 . The output signal R 1  of the first inverter  151  functions as an input signal of both D flip-flop  155  and the second delay circuit  152 . The second delay circuit  152  delays a time unit t 2  to avoid DC current path from MOS  201  to MOS  202  and meet the set up time constrain of the D flip-flop  155 .  
         [0018]     The second inverter  153  outputs the signal ck 0  for both the third inverter  154  and the reset and charging circuit  200 . The third inverter  154  then generates signal ck 1 , which functions as a clock signal ck of the D flip-flop  155 . Consequently, the clock signal ck of the D flip-flop  155  at least lags behind the signal R 1  by t 2 . The input terminal of the D flip-flop  155  is connected to a signal V dd , and the output terminal Q outputs a signal cp 0 , which is fed into the input terminal of the second CMOS  162 .  
         [0019]     The reset and charging circuit  200  having a pMOS  201 , cascodes over an nMOS  202  and a capacitor  204 . The nMOS  202  and the capacitor  204  are connected in parallel. The switch of the pMOS  201  is controlled by the signal CP and the switch of the nMOS  202  is controlled by the signal CK 0 .  
         [0020]     The pulse detected of capacitor and signal output circuit  250  is composed of a fourth inverter  251 , a fifth inverter  252  and an edge-trigger D flip-flop  255 . The fourth inverter  251 , in series connected with the fifth inverter  252  and then feeds into the clock terminal CK of the second D flip-flop  255 . The input terminal D of the D flip-flop  255  is to receive input signal IN, and the output terminal Q outputs the signal OUT, which is an aimed signal free from short pulse.  
         [0021]     The operations of the circuit according to the present invention are shown in  FIG. 4 , a timing diagram. As the input signal IN varies, for example at time t 0 , a pulse H 1  appeal, the first CMOS  102  outputs an signal INX 1  and a time lagged signal INX 2 , which make the XOR gate  106  outputs two pulses  401  and  402 , which correspond, respectively, the rising edge  301  and falling edge  302  of the pulse H 1 . As is shown in  FIG. 4 , the invert signals R 1  are inversed of the pulses  401  and  402 . The inverse of signals R 1  is delayed by the second delayed circuit  152  and further is inversed again by the second inverter  153 , two signals CK 0  are thus resulted. The two signals CK 0  are further inverted to generate signals CK 1  by the third inverter  154 . Since the D flip-flop  155  is an edge-trigger type, thus in response to the raising edges of the clock signals CK 1 , the signals CP 0  formed are resulted. See the left edges  501  and  502 .  
         [0022]     Signals CP  601  and  602  are resulted output signals of the second CMOS  162  while input signals  501 ,  502  are fed. Referring to the circuit shown in  FIG. 3 , that state of pMOS  201  is cut off and nMOS  202  is saturated while CP=1 and CK 0 =1. The charges of the capacitor  204  will conducted to ground though the nMOS  202 . On the other hand, CP=0 and CK 0 =0 will turn off the nMOS  202  but turn on the pMOS  201 . In the situation, the capacitor  204  is charged. In the other situation of CP=1 and CK 0 =0, both pMOS  201  and nMOS  202  will turned off. The charges in the capacitor are thus hold. Thereafter, the terminal voltage PU 0  of capacitor versus time varied  203  is shown as In  FIG. 4 . The capacitor  204  will be discharged  701  during the pulse  601  until the ending of  601 . Thereafter, the capacitor is charged again, as is indicated by numeral  702 . The appearance of the short pulse  602  will make the capacitor  204  discharged again. Thus, if the time interval between the pulse  601  and  602  is small, the signal PU 0  will not able to over the threshold voltage VTH of the fourth inverter  251 , as a result, the output of the pulse detected of capacitor and signal output circuit  250  will be hold as it was.  
         [0023]     When L 1  followed with input signal H 1  is not width enough, as is shown in  FIG. 4 , the signal X 01  will generate the pulse  402  and the corresponding signal CP 0  will generate pulse  502 . Though the capacitor  204  is charged as is indicated by  703  in  FIG. 4 , the signal is still not over the V TH .  
         [0024]     When the input signal H 2  followed with signal L 1  is width enough, then the capacitor  204  is charged at the end of pulse  603  till the pulse  604  presents. During the charging time, the voltage of the signal PU 0  will surpass the V TH  and then makes the pulse detected of capacitor and signal output circuit  250  generate pulse  804 . The pulse  804  is fed to the flip-flop  255  causes output terminal of the flip-flop outputs a signal that is the same as signal IN while the left edge of the pulse  804  raising.  
         [0025]     Worth to note, not only the high-pulse such as H 1  and H 2  will charge the capacitor  204 , please see the signals  702 , and  704 , the low-pulses such as L 1  and L 2  will charge the capacitor  204  too, please see the signals  703 , and  705 . Hence, the circuit proposed by the present invention not only provides to filter those short high-pulses, but also those short low-pulses. For instance, if the width of the low-pulse L 2  is not enough large, the charged signal  705  will be not able to generate a pulse at terminal PU. By contrast, the pulse  805  is generated while the width of the low-pulse L 2  is enough, as is shown in  FIG. 4 .  
         [0026]     The charge rate of the capacitor  204  is determined by a ratio of the channel width/channel length (W/L) of the pMOS  201  the larger ratio will provide large current and thus results in larger charge speed. A ratio of the (W/L of the nMOS  202  will determine the discharged speed. The size of capacitor  204  is also critical. It should make the voltage PU 0  over V TH  of the inverter  251 . The W/L ratio of the pMOS  201  together with the size of the capacitor  204  will be designed to determine the size of the pulse to be filtered. According, for capacitor  204  of 0.05 pF is concerned, filter the pulse, the W/L ratio of nMOS  202  at 4 μm/0.22 μm will case capacitor being discharged completely at 0.5 ns. Hence, it is satisfied most of the requirement 1 ns discharged time.  
         [0027]     While there have been described above the principles of the present invention in conjunction with specific devices, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention, Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.