Abstract:
A network switch including a physical layer device and a media access controller. The physical layer device includes an auto-negotiation circuit configured to negotiate a first data rate for transmission of data between the physical layer device and a network client external to the network switch, and a first serializer interface configured to receive the first data rate from the auto-negotiation circuit. The media access controller includes a second serializer interface. The first serializer interface of the physical layer device is configured to, based on the negotiated first data rate received from the auto-negotiation circuit, selectively replicate portions of data received from the network client, and transmit the data to the second serializer interface of the media access controller at a second data rate regardless of the first data rate negotiated between the auto-negotiation circuit and the network client. The first data rate and the second data rate are different.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present disclosure is continuation of U.S. patent application Ser. No. 13/230,769 (now U.S. Pat. No. 8,619,571), filed on Sep. 12, 2011, which is a continuation of U.S. patent application Ser. No. 12/723,915 (now U.S. Pat. No. 8,018,962), filed on Mar. 15, 2010, which is a continuation of U.S. patent application Ser. No. 11/516,359 (now U.S. Pat. No. 7,680,146), filed on Sep. 6, 2006, which is a continuation of U.S. patent application Ser. No. 10/892,356 (now U.S. Pat. No. 7,173,942), filed on Jul. 16, 2004, which is a continuation of U.S. patent application Ser. No. 09/501,556 (now U.S. Pat. No. 6,816,505), filed on Feb. 9, 2000. The entire disclosures of the applications referenced above are incorporated herein by reference. 
    
    
     The inventors incorporate IEEE Standard 802.3 in its entirety herein by reference. 
     FIELD 
     This invention relates generally to an interface and switch for a high speed network, and more particularly to an interface and network switch capable of communicating at a nominal rate of up to 1 gigabit per second 
     DESCRIPTION OF THE RELATED ART 
     Interconnections of and communications among computers, peripheral devices, Internet appliances (generally referred to as network clients hereinbelow) via computer networks are ubiquitous. Moreover as applications such as, multimedia, require higher data transfer rates there is a need for more robust and faster networks. 
     Network switches facilitate interconnections and communications among networks and network clients. Conventional networks may utilize twisted pair cable such as Category 5 and operate at a data rate of either 10 megabits per second which generally complies with IEEE Standard 802.3, section 14, commonly known as 10 BASE-T, and 100 megabits per second which generally complies with IEEE Standard 802.3, sections 24 and 25, commonly known as 100 BASE-TX, the contents of each of which are incorporated herein by reference. As the demand for increased data transfer rates is required, a newer networking standard has been proposed that utilizes twisted pair cable and operates at a nominal data transfer rate of 1 gigabit per second (1000 megabits per second). The 1 gigabit per second transfer rate complies with IEEE Standard 802.3, section 40, commonly known as 1000 BASE-T, the contents of which are incorporated herein by reference. 
       FIG. 1  is schematic diagram of a typical networking system. As shown therein, a computer  10  is connected to a first port of switch  20  via a communications channel, such as, twisted pair cable  30 . Switch  20  may comprise 24 ports, to allow computer  10  to communicate with other computers, peripherals, network appliances and other networks. 
     Computer  10  comprises a media access controller or MAC  12  and physical layer interface (PHY) or transceiver  16 , which are connected to each other by an interface defined by, for example, the Media Independent Interface (MII) for 10 BASE-T standard and for 100 BASE-TX standard or the Gigabit Media Independent Interface (GMII) for 1000 BASE-T standard. MII for 10 BASE-T standard and for 100 BASE-TX standard are discussed at IEEE standard 802.3 section 22, the contents of which are incorporated herein by reference. The Gigabit Media Independent Interface (GMII) is defined by IEEE 802.3 section 35, the contents of which are incorporated herein by reference. 
     Media access controller  12  controls media access of transmitting and receiving packets to and from computer  10 . Typically for gigabit level products, MAC  12  and PHY  16  are implemented as individual integrated circuits. 
     Switch  20  comprises MAC  22   n  and PHY  26   n , which are respectively connected to each other in accordance with an interface as defined above. MAC  22   n  and PHY  26   n  are functionally similar to MAC  12  and PHY  16  of computer  10 . 
     When the network is operated in accordance with 10 BASE-T or 100 BASE-TX the interface is defined in accordance with Media Independent Interface (MII). The MII passes data to and from the MAC  22   n  in 4 bit wide nibbles. The nibbles are converted to and from 10BASE-T or 100BASE-TX on the network side. When the network is operated at a higher transmission rate in accordance with 1000 BASE-T, the interface is defined by the GMII. In accordance with GMII, data is passed to and from the MAC  22   n  in 8 bit wide bytes. The bytes are converted to and from 1000BASE-T on the network side. Note that if fiber is used on the network side then the bytes are converted to and from 1000BASE-X on the network side. In other words, the MII/GMII provides a standard interface from a MAC to a transceiver regardless of the actual protocol used on the network side. 
     In a system that complies with 10 BASE-T, the MII requires 16 connection lines or pins connecting the integrated circuit embodying PHY  16  and PHY  26  to integrated circuit embodying MAC  12  and MAC  22 , respectively. Similarly, in a system that complies with 100 BASE-TX 16 connection lines or pins are required. In a system that complies with 1000 BASE-T  24  connection lines or pins are required. The number of pins required for MAC  12  is not a problem because there is only one MAC and one PHY. On the other hand since there are n ports in switch  20 , and since the n MAC  221 - 22   n  are typically fabricated as a single integrated circuit  22 , the number of pins are 24×n. For example if there are 24 ports then the n MAC  22  requires 24×24 or 576 pins. The higher number of pins result in a larger die, a larger package, a more complicated integrated circuit and higher costs, particularly at the higher data transfer rates. 
     Various attempts have been made to solve the above-mentioned problems. Two ad hoc standards, namely Reduced Media Independent Interface (RMII) and Serial Media Independent Interface (SMII) reduce the number of pins by serialization techniques for 10 BASE-T and 100 BASE-TX. The RMII technique requires 7 pins per port and the frequency doubles from 25 MHz to 50 MHz. Thus for a 24 port switch 7×24 or 168 pins are required. The SMII technique requires 2 pins per port plus 1 synchronizing pin and the frequency increases  5  fold from 25 MHz to 125 MHz. In this technique 2×24+1 or 49 pins are required for the SMII technique. As will be appreciated by one of ordinary skill in the art, these techniques operate at frequencies in which clock recovery between PHY  26  and MAC  22  is not required. 
     The GMII interface consists of 24 pins operating at 125 Megabits per second. However, design of such circuit is difficult as the length of the traces and impedances between the traces must match for good signal integrity at this higher frequency. This results in a more costly and complicated integrated circuit. 
     An additional requirement of a network circuit operating at 1 gigabit per second is to be backward compatible with 10 BASE-T and 100 BASE-TX networks. That is, the network circuit must detect the maximum data transmission rate capability and set the transmission rate to that rate. For example, if computer  10  is capable of a maximum transmission rate of 100 Mb per second, switch  20  having a capability of 1 gigabit per second, must detect the 100 Mb per second rate and set the transmission rate of the port of switch  20  connect to computer  10  to 100 Mb per second. This feature is commonly known as auto-negotiation. The auto-negotiation feature is typically implemented in PHY  16  and PHY  26   n . PHY  16  communicates the auto-negotiated data transmission rate to MAC  12  and PHY  26   n  communicates the auto-negotiated data transmission rate to MAC  22   n.    
     Traditional techniques either requires higher pin counts and complicated board routing. 
     OBJECTS OF THE INVENTION 
     Therefore, it is an object of the present invention to overcome the aforementioned problems. 
     It is another object of the present invention to provide an interface between physical layer devices having data rates up to 1 gigabit per second. 
     It is a further object of the present invention to provide an interface between which reduces the number of pins or connections. 
     It is an additional object of the present invention to provide a system to efficiently control the auto-negotiated data rate. 
     SUMMARY 
     According to one aspect of the present invention, a network device is provided which comprises a first integrated circuit having fabricated thereon a media access controller and a first serializer interface in communication with said media access controller. A second integrated circuit is provided comprising a physical layer interface in communication with an external device and a second serializer interface in communication with physical layer interface and said first serializer interface. The first and second serializer interfaces comprise a fiber channel physical layer device implemented in accordance with 1000 BASE-X. 
     According to a second aspect of the present invention, the first serializer interface comprises a first receiver/decoder and a first transmitter/encoder, the second serializer interface comprises a second receiver/decoder and a second transmitter/encoder, and the first transmitter/encoder being in communication with the second receiver/decoder and the second transmitter/encoder being in communication with the first receiver/decoder. 
     In accordance with a third aspect of the present invention, the physical layer interface communicates with the external device at a selected one of plural data transmissions rates in accordance with a negotiated data transmission rate negotiated with the external device. The first transmitter/encoder communicates with the second receiver/decoder at a predetermined data transmission rate regardless of the negotiated transmission rate, and the second transmitter/encoder communicates with the first receiver/decoder at the predetermined data transmission rate regardless of the negotiated transmission rate. 
     In accordance with a fourth aspect of the present invention, the second integrated circuit further comprises a transceiver to communicate with the external device and an auto-negotiation circuit in communication with the transceiver. The auto-negotiation circuit negotiates the negotiated data transmission rate with the external device and provides a first control signal indicative of the negotiated data transmission rate to the second receiver/decoder and the second transmitter/encoder. If first control signal indicates that the negotiated data transmission rate is less than a specified data transmission rate, the second transmitter/encoder replicates data transmitted to the first receiver/decoder. The first receiver/decoder determines if any data received from the second transmitter/encoder has been replicated and provides a second control signal indicative of a received data transmission rate to the first transmitter/decoder. If the second control signal indicates that the first received data transmission rate is less than the specified data transmission rate, the first transmitter/encoder replicates data transmitted to the second receiver/decoder. The second receiver/decoder determines if any data received from the first transmitter/encoder has been replicated to determine the received data transmission rate and compares the received transmission rate with the first control signal. If the received data transmission rate is not equal to the negotiated data transmission rate, the second receiver/decoder provides a third control signal to the transceiver. The transceiver transmits idle data to the external device upon receipt of the third control signal. 
     In accordance with a fifth aspect of the present invention, the predetermined data transmission rate is 1.25 gigabits per second. 
     In accordance with a sixth aspect of the present invention, the physical layer interface is capable of communicating with the external device at a nominal data transmission rate of 1 gigabit per second. 
     In accordance with a seventh aspect of the present invention, a network switch is provided and comprises a first integrated circuit having a plurality of media access controllers and a plurality of first serializer interfaces, each in communication with a respective one of the plurality of media access controllers. A plurality of second integrated circuits are provide, each comprising a physical layer interface in communication with an external device, and a second serializer interface in communication with the physical layer interface and a corresponding one the first serializer interfaces. 
     In accordance with a eighth aspect of the present invention the first and second serializer interfaces comprise a fiber channel physical layer device implemented in accordance with 1000 BASE-X. 
     In accordance with a ninth aspect of the present invention, an integrated circuit comprises a media access controller and a serializer interface in communication with the media access controller and an external device. The serializer interface comprises a fiber channel physical layer device implemented in accordance with 1000 BASE-X. 
     In accordance with a tenth aspect of the present invention, an integrated circuit comprises a physical layer interface in communication with a first external device and a serializer interface in communication with the physical layer interface and a second external device. The serializer interface comprises a fiber channel physical layer device implemented in accordance with 1000 BASE-X. 
     Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       In the drawings wherein like reference symbols refer to like parts: 
         FIG. 1  is a schematic diagram of a conventional networking system; 
         FIG. 2  is a schematic diagram of a networking system in accordance with a first embodiment of the present invention; 
         FIG. 3  is a more detailed schematic diagram of a media access controller (MAC) and PHY in accordance with the first embodiment of the present invention; 
         FIG. 4  is a more detailed schematic diagram of a media access controller (MAC) and PHY in accordance with a second embodiment of the present invention; and 
         FIG. 5  is a more detailed schematic diagram illustrating auto-negotiation in accordance with the first embodiment of the present invention. 
     
    
    
     DESCRIPTION 
     Referring to  FIG. 2 , shown therein is a preferred embodiment of the present invention. As shown therein, a computer  10  is connected to a first port of switch  20  via a communications channel, such as, twisted pair cable  30 . Switch  20 ′ may comprise 24 ports, to allow computer  10  to communicate with other computers, peripherals, network appliances and other networks. 
     Computer  10  comprises a media access controller or (MAC)  12  and physical layer interface (PHY) or transceiver  16 , which are connected to each other in accordance with an interface, such as, MII or GMII discussed above. Media access controller  12 , computer  10 , and PHY  16  are similar to those described above, therefore no further discussion is provided herein. As will be appreciated by one of ordinary skill in the art, communication channel  30  may be implemented using a variety of techniques, for example wired, wireless, radio frequency, optical and the like. 
     Switch  20 ′ comprises n ports. Each of the n ports comprises MAC  22 ′, and PHY  26 ′ n . PHY  26 ′ n  comprises serializer interface  27   n , and MAC  22 ′ n  comprises serializer interface  28   n , which are connected to each other to facilitate communication between MAC  22 ′ n  and PHY  26 ′ n . Serializer interfaces  28   1 - 28   n  and MAC&#39;s  22 ′ 1 - 22 ′ n  are fabricated on a single integrated circuit. PHY  26 ′ n  and serializer interface  27   n  are fabricated on another integrated circuit. Serializer interfaces  27   n  and  28   n  have high bandwidth that can connected to each other using only a small number of wires, connections or pins for each transmit and receive link. In the preferred embodiment, serializer interfaces  27   n  and  28   n  are implemented in accordance with the fiber channel physical layer device standard as described in IEEE 802.3, section 36, commonly known as 1000 BASE-X. The contents of IEEE 802.3, section 36 are incorporated herein by reference. 
     Referring now to  FIG. 3 , serializer interface  28   n  comprises receive port  41   n , transmit port  42   n  and interface  43   n . Port  41   n  of serializer interface  28   n  is connected to the transmit port  46   n  of serializer interface  27   n  by a pair of differential wires, and transmit port  42   n  of serializer interface  28   n  is connected to receive port  47   n  of serializer interface  27   n  by a pair of differential wires. Port  43   n  is connected to MAC  22   n , and port  48   n  is connected to PHY  26 ′ n . 
     In the preferred embodiment serializer interface  28   n  requires only 4 pins, 2 pairs of differential wires or interconnections are required for each port. For a 24 port switch only 96 pins are required instead of the 576 pins required using conventional techniques. 
       FIG. 4  is a schematic diagram of another embodiment of the present invention. The embodiment shown herein is similar to the embodiment shown in  FIG. 2 , however PHY  26 ″ n  comprises a GMII standard interface  23   n . In this configuration, PHY  26 ″ n  can be connected to any GMII compliant device, which can facilitate communication between that device and either serializer interface  27   n  or twisted pair cable  30 . 
     The auto-negotiation feature will now be described below with reference to  FIG. 5 . 
     In accordance with any of the embodiments above, while switch  20 ′ has the capability of communicating at nominally 1 gigabit per second, switch  20  must also be able to communicate at data rates of 10 Mbits per second and 100 Mbits per second, dependent on the network client connected thereto. 
       FIG. 5  is a schematic diagram of an embodiment capable communicating with a network client having a different data transmission rate. This embodiment generally comprises the same components as that of  FIG. 2 . More specifically, serializer interface  27   n  comprises transmitter/encoder  60   n  and receiver/decoder  61   n  and serializer interface  28   n  comprises transmitter/encoder  63   n  and receiver/decoder  62   n . Very generally, the principal of operation is as follows. Firstly, the data transmission rate between serializer interface  27   n  and serializer interface  28   n  is maintained at 1.25 gigabit per second, regardless of the data transmission rate between the network client and PHY  26 ′ n . In operation, auto-negotiation circuit  70   n  negotiates the data transmission rate with the network client using known techniques such as, standard IEEE 802.3, sections 28 and 40, the contents of which are incorporated by reference. The negotiated transmission rate is communicated to transmitter/encoder  60   n  via control signal  110 . If the data transmission rate is below the nominal 1 gigabit per second, transmitter/encoder  60   n  will replicate data transmitted to serializer interface  28   n , as explained in detail below, while the data transmission rate between from transmitter/encoder  60   n  to serializer interface  28   n  is maintained at 1.25 gigabit per second. In the serializer interface  28   n , receiver/decoder  62   n  monitors the data transmission and determines if data has been replicated. If no data has been replicated, the data transmission rate is 1.25 gigabit per second and no special processing is performed and all data is communicated with MAC  22 ′ n . If receiver/decoder  62   n  determines that data is being replicated, then the replicated data is ignored and not communicated to MAC  22 ′ n . This feature allows switch  20 ′ to communicate with network clients having a lower transmission rate without the need for costly and complicated circuits. 
     In a data communication system in accordance with 1000 BASE-X as described in IEEE 802.3, section 36, when there is no data to be transmitted, the transmitting component, for example PHY n , sends an idle ordered set of data which consists of two alternating 10 bit code groups which are denoted as /K28.5/016.21. This ordered set is abbreviated as /I/. It is noted that the ordered set /K28.5/D5.6/ is occasionally utilized to maintain correct disparity. Also in accordance with 1000 BASE-X, when a packet is transmitted, the packet is delimited by a start of packet and end of packet delimiters which are abbreviated /S/ and /T/R/, respectively. 
     Receiver/decoder  62   n  and receiver/decoder  61   n  perform alignment of the bits stream into code-groups by searching for a comma pattern, namely, is 1100000 or 0011111. The comma pattern cannot be found in any code-group or within a concatenation of any combination of code-groups except for the code-groups /K28.5/, /K28.1/, and /K28.7/. In the preferred embodiment the code groups /K28.1/ and /K28.7/ are not used. Hence alignment is performed during idles where the /K28.5/ code-group is present. 
     It is further noted that the /K28.5/ code-group is also used in other ordered sets to pass configuration information. For example /K28.5/D21.5/Dx.x/Dx.x/is a valid configuration ordered set. In the preferred embodiment, receiver/decoder  62   n  and  61   n  ignore most of the ordered sets containing configuration information. This simplifies the design of receiver/decoders  62   n  and  61   n . 
     As noted above, the ordered set /K28.5/D5.6/ is occasionally utilized to maintain correct disparity. In general, the purpose of disparity is twofold. First, disparity is used to ensure that there will be equal numbers of 0&#39;s and 1&#39;s are transmitted over a short period of time to maintain DC balance regardless of the actual data within the packet. Second, disparity allows the receiver to detect the presence of errors that occurs over the transmission medium. Typically, for each code group there is two possible 10 bit sequences. One is transmitted when the disparity is positive, and the other when negative. (For some code-groups the same 10-bit sequence is used to for both positive and negative disparities.) 
     In the following discussion it is assumed that the signal flow is serializer interface  27   n  to serializer interface  28   n . The reverse process is used from the serializer interface  28   n  to serializer interface  27   n . 
     More specifically, in transmitter/encoder  60   n  nibbles are replicated. Since the conversion into 1000BASE-X requires byte wide data while 10BASE-T/100BASE-TX passes data in nibble wide data, the upper four bits of the byte are padded with dummy bits by transmitter/encoder  60   n . In 100BASE-TX the data is replicated 5 times and five bytes are transmitted from the 1000BASE-X for each 100BASE-TX nibble. In 10BASE-T the data is replicated 50 times. 
     In accordance with an alternative implementation of transmitter/encoder  60   n , the upper bits are not padded but rather two nibbles are passed at a time. In this case the data is replicated 10 and 100 For 100 BASE-TX and 10 BASE-T times respectively. The advantage of this approach is that MAC  22 ′ n  passes data in bytes regardless of the speed of operation. 
     Note that the /S/ code group must be transmitted 10 or 100 times for 100 BASE-TX and 10 BASE-T, respectively. In principle the /T/R/ and /I/ code-groups must be transmitted 10 or 100 times for 100 BASE-TX and 10 BASE-T, respectively. However in accordance with the present embodiment, latency can be shortened by transmitting the code groups 5 or 50 times, for 100 BASE-TX and 10 BASE-T, respectively. 
     In the present embodiment data is simply replicated as many times as needed and disparity is calculated once every 5 or 50 code groups for 100 BASE-TX and 10 BASE-T, respectively. In an alternate embodiment, disparity can also be calculated once every code group. This will allow a better short-term DC balance, but may complicate serializer interface  28   n . 
     PHY  26 ′ n  determines the data transmission rate of the network based on auto-negotiation. However the MAC  22 ′ n  requires some time to receive the data from the PHY  26   n  before it can respond. More specifically, auto-negotiation circuit  70   n  negotiates the transmission data rate with the network client and sends a control signal  110  to transmitter/encoder  60   n . As noted above, transmitter/encoder  60   n  will either pass the data through or replicate bits in accordance with the detected data transmission rate. Receiver/decoder  62   n  of serializer interface  28   n  can sense the data transmission rate by counting the number of /K28.5/ it receives, as noted above. Receiver/decoder  62   n  sends a control signal  212  to transmitter/encoder  63   n . Receiver/decoder  61   n  of serializer interface  27   n  can sense the data transmission rate as noted above. Receiver/decoder  61   n  then compares the data transmission rate it senses to the auto-negotiated data transmission rate from control signal  110 . If the data transmission rates are different, then receiver/decoder  61   n  sends control signal  112  to transceiver  80  to transmit idle bits. When the data transmission rates become the same, the control  112  then permits transceiver  80  to transmit data. 
     While the invention has been described in conjunction with several specific embodiments, it is evident to those skilled in the art that many further alternatives, modifications and variations will be apparent in light of the foregoing description. Moreover, it is contemplated that the present invention is not limited to the nominal 1 gigabit per second data transmission rate and above-described protocols, and may be implemented with other appropriate data transmission rates and protocols. Thus, the invention described herein is intended to embrace all such alternatives, modifications, applications and variations as may fall within the spirit and scope of the appended claims.