Abstract:
A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention generally relates to the manufacturing of MOS transistors in a semiconductor substrate. More specifically, the present invention relates to the manufacturing of transistors having a gate of a length smaller than 100 nm.  
         [0003]     2. Discussion of the Related Art  
         [0004]     Certain MOS transistors comprise pockets of a same first conductivity type but more heavily doped than the substrate, at the surface of which are formed lightly-doped regions (LDD) of the second conductivity type and heavily-doped surface regions (HDD) of the second conductivity type.  
         [0005]     The present invention will be described hereafter in relation with the forming of an N-channel MOS transistor formed in a P-type doped silicon substrate.  FIG. 1  illustrates, in a partial simplified cross-section view, an N-channel MOS transistor at an intermediary step of its manufacturing according to a known method.  
         [0006]     The method starts with the definition of a gate G insulated from the surface of substrate  1  by a thin insulator  3 . The method continues with the forming by implantation, at the substrate surface, of N-type lightly-doped regions (LDD)  4  on either side of gate G. In this implantation, gate G is used as an implantation mask. Pockets  6  of the same conductivity type as substrate  1  are also formed by implantation. The pockets are more heavily doped than the substrate, but less heavily than regions  4 . Pockets  6  are formed between regions  4  and substrate  1 . The pockets are generally formed, as illustrated in  FIG. 1 , along the entire junction between the substrate and regions  4 , gate G being also used as an implantation mask.  
         [0007]     The two successive implantations of the dopants of regions  4  and of pockets  6  are performed in any order.  
         [0008]     The same diffusion anneal during which the dopants of regions  4  and of pockets  6  diffuse to provide the structure of  FIG. 1  is then performed. This anneal can be performed at the end of the transistor forming process, after the implantation (not shown) of N-type dopants at the surface of regions  4  to form heavily-doped drain and source regions (HDD).  
         [0009]      FIG. 2  schematically illustrates the doping profiles of the structure of  FIG. 1  after the diffusion anneal. The abscissa axis corresponds to horizontal direction X of  FIG. 1 . As described previously, channel region  8  underlying gate G exhibits a small P-type doping and is separated from LDD lightly-doped N-type regions  4  by superficial portions of pockets  6  more heavily P-type doped than substrate  1 , but less heavily doped than regions  4 . As an example, the doping of substrate  1  and of channel region  8  is on the order of from 10 15  to 10 18  at·cm −3 , the surface doping of regions  4  is on the order of from 10 18  to 10 20  at·cm −3 , and the doping of pockets  6  is from 10 16  to 10 19  at·cm −3 .  
         [0010]     Pockets  6  are often used in transistors with small gate lengths to limit uncontrolled untimely switching problems imputed to so-called short channel effects. Such short channel effects are due to the diffusion of the dopants of regions  4  under gate G. Indeed, in the anneal performed to obtain regions  4  of an appropriate depth d, on the order of 20 nm, the dopants also diffuse under gate G with a diffusion length W. In operation, in the absence of pockets  6 , in a biasing of regions  4 , space charge areas create between regions  4  and substrate  1 . Such space charge areas mostly extend into substrate  1 , more lightly doped than regions  4 . When gate G is narrow, the space charge areas extend until they cover each other. The control of the channel establishment by the gate is then lost.  
         [0011]     The presence of pockets  6  more heavily P-type doped than substrate  1  enables limiting the extent of the space charge areas to these pockets. This enables keeping, in substrate  1 , a channel area  8  controlled by the sole biasing of gate G.  
         [0012]      FIG. 3  schematically illustrates a type of known implantation device  30  with a magnetic deviation dopant species selection. A target is ionized in a cation source IS. The cation flow coming out of chamber IS is accelerated under a potential difference V. The obtained beam is collimated by a diaphragm D and sent into a magnetic deviation chamber MAGDEV where a cation mass discrimination is performed. Indeed, from a given target, a great number of cations is obtained. For example, for a P-type doping by means of boron, a source of boron trifluoride BF 3  which provides, on ionization, cations B + , BF + , BF 2   + , and BF 3   + , is used. Magnetic deviation circuit MAGDEV enables only selecting the cations B +  which are sent to wafer  31  to be implanted. Thus, fundamentally, this type of device only enables implanting a single species (ionized atom or molecule) and dopant type.  
         [0013]      FIG. 4  schematically illustrates another type of known plasma implantation device  40  generally used for extremely fine implantations. In device  40 , a plasma  43  is created in the vicinity of a wafer  41 . Plasma  43  comprises, in the form of cations that can be dispersed in an inert carrier gas such as argon or xenon, a species to be implanted. The wafer is biased to a negative reference voltage Vs. Then, the cations implant into wafer  41 . Device  40  enables performing implantations at reduced implantation powers with respect to device  30 . The penetration depths of the doping cations is then reduced.  
         [0014]     Whatever the used implantation device  30  or  40 , two successive N-type and P-type implantations are performed, in an indifferent order, to obtain the structure of  FIG. 1  and the diffusion profiles illustrated in  FIG. 2 .  
         [0015]     A disadvantage of such a MOS transistor forming method lies in the long times linked to the implantations and the costs of use of two separated implanters.  
       SUMMARY OF THE INVENTION  
       [0016]     The present invention accordingly aims at providing a MOS transistor forming method with reduced costs.  
         [0017]     More specifically, the present invention aims at providing such a method in which the number of implantation steps is reduced.  
         [0018]     To achieve these and other objects, the present invention provides a method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying said surface regions. The present invention provides the step of negatively biasing the substrate placed in the vicinity of a plasma comprising in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.  
         [0019]     According to an embodiment of the present invention, the dopant of the first conductivity type is boron and the dopant of the second conductivity type is phosphorus, arsenic, or antimony.  
         [0020]     According to an embodiment of the present invention, the dopant of the first conductivity type is phosphorus and the dopant of the second conductivity type is indium.  
         [0021]     According to an embodiment of the present invention, a negative biasing voltage of the substrate is set according to the implantation depths of the dopants of the first desired conductivity type and the partial pressures of the dopants of the first and of the second conductivity type in the plasma are set according to the desired doses/concentrations and to the depth of the limit between doped surface regions of the second conductivity type and doped deep regions of the first conductivity type.  
         [0022]     The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]      FIG. 1  is a partial simplified cross-section view of an N-channel MOS transistor at an intermediary step of its manufacturing;  
         [0024]      FIG. 2  is a diagram illustrating the dopant concentration profile at the surface of  FIG. 1 ;  
         [0025]      FIG. 3  schematically illustrates a device of implantation by magnetic deviation;  
         [0026]      FIG. 4  schematically illustrates a plasma implantation device; and  
         [0027]      FIG. 5  is a diagram schematically illustrating the profiles of doses implanted according to the present invention before a diffusion anneal. 
     
    
     DETAILED DESCRIPTION  
       [0028]     For clarity, the same elements have been designated with the same reference numerals in the different drawings and, further, the various drawings are not to scale.  
         [0029]     Conventionally, in an implantation by device  30  of  FIG. 3  or by device  40  of  FIG. 4 , a single electrically-active dopant is implanted. In the case of plasma device  40 , the ionized dopant may be diluted in an inert neutral gas, such as argon or xenon, that may be ionized and implanted but which is electrically neutral. Further, even if several cations, for example, B + , BF + , BF 2   + , and BF 3   + , are implanted, a single species, boron B, is electrically active. The other species, F, is electrically neutral.  
         [0030]     The present invention is based on the awareness by the inventors that, conversely to a general prejudice, a plasma-type implanter may be used to simultaneously implant dopants of different types. This enables reducing manufacturing costs by simultaneously forming the LDD regions and the MOS transistor pockets of reduced dimensions in a same implantation step performed in the same plasma implanter.  
         [0031]     The implantation is then performed for the two types of dopants under the same power set by the biasing of the implanted wafer. However, the speed at which the cations hit the wafer depends on their mass and heavy cations are less heavily implanted than light cations. Then, to form in a same implantation LDD regions  4  and pockets  6  of  FIG. 1 , the dopants are selected so that the cations intended to form region  4  are heavier than the cations intended to form region  6 .  
         [0032]     As for the concentrations, that is, the implanted doses, they are set by the relative proportions of the partial pressures of the dopants present in the plasma. Thus, to obtain LDD regions  4  more heavily doped than pockets  6 , the partial pressure of the dopant of the LDD regions is set to a value higher than that of the pocket dopant. For example, the gas supply rates of the plasma chamber are set so that the flow rate of the dopant intended to form LDD regions is approximately twenty times as high as that of the dopant intended to form pockets.  
         [0033]     As an example, to form an N-channel MOS transistor, a plasma based on arsenic pentafluoride AsF 5  and on boron trifluoride BF 3  is used. From the arsenic pentafluoride, mostly AsF 3   +  and AsF 4   +  cations, which have a respective molecular mass of  132  and  151 , are obtained. From the boron trifluoride, mostly cations B + , BF + , and BF 2   +  of respective molecular mass of  11 ,  30 , and  49 , are obtained. To obtain a concentration difference of a factor  100  at the junction, the gas flow rates will be adjusted so that the arsenic pentafluoride flow rate is approximately twenty times greater than that of boron trifluoride.  
         [0034]      FIG. 5  schematically illustrates the profile of the implanted doses of arsenic in full lines and of boron in dotted lines. The abscissa corresponds to vertical direction Y of  FIG. 1 , outside of the region underlying gate G. The arsenic, being heavier, concentrates at the surface of substrate  1  and its concentration substantially linearly decreases. The boron, which is lighter, penetrates into the structure. Depth Y for which the boron concentration becomes greater than that of arsenic depends on its initial concentration in the plasma. This depth corresponds to the limit between regions  4  and pockets  6  of  FIG. 1 . Thus, if the partial pressure of boron trifluoride P(BF 3 ) in the plasma decreases: P 1 (BF 3 )&gt;P 2 (BF 3 )&gt;P 3 (BF 3 ), then the depth of pockets  6  increases (Y 1 &lt;Y 2 &lt;Y 3 ).  
         [0035]     The present inventors advantageously exploit what used to be considered up to now as disadvantages of plasma implantation, that is, the non-selectivity of the implanted species, and the low implantation power. The non-selectivity enables a co-implantation. The low power enables limiting the implantation depth of LDD regions  4 . Despite the low power, pockets  6  can be sufficiently deeply implanted by using a light dopant.  
         [0036]     Further, the implantation duration is significantly decreased with respect to that of a conventional ion implantation. This reduces the costs linked to the utilization period of the materials. This adds to the advantage of the co-implantation which eliminates the cost linked to the use of two implantation devices, each being dedicated to the implantation of a type of dopants.  
         [0037]     Of course, the present invention is not limited to the forming of N-channel transistors by co-implantation of arsenic and boron. Other co-implantations may be used, provided that the mass of the N-type dopant implanted at the surface is greater than that of the P-type dopant implanted in the pockets. As an example, if the boron in the form of boron trifluoride is the P-type dopant, arsenic as well as phosphorus (P, atomic mass  31 ) in the form of PF 3 , PF 5 , PH 3 , as well as antimony (Sb, of atomic mass  122 ) in the form of SbH 3 , may be used as the N-type dopant. Preferably, antimony, which is the heaviest and accordingly which will be best separated from boron, will be used.  
         [0038]     Further, the dopant supply form, that is, the molecular combination of the ionized target and the corresponding cations, may be of any kind, provided that the dopants of the complementary conductivity type which are desired to be implanted are associated with an electrically neutral species such as fluoride. It being a silicon substrate, the dopants may also be brought in the form of chloride or hydride.  
         [0039]     It is also possible to form P-channel MOS transistors of small dimensions by using a single co-implantation according to the present invention to form P-type LDD regions and N-type pockets. For example, indium, of atomic mass  114 , is used as a P-type dopant, and phosphorus is used as an N-type dopant.  
         [0040]     Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, it will be readily understood by those skilled in the art that only those elements of a MOS transistor necessary to the understanding of the present invention have been described and shown. It will be within the abilities of those skilled in the art to complete the previously-described method to obtain the full structure of a MOS transistor. Thus, it will be within the abilities of those skilled in the art, for example, after the co-implantation according to the present invention, to form spacers on the lateral walls of gate G, to use these spacers and the gate as an implantation mask of heavily-doped source/drain regions (HDD), to silicide the surfaces of the HDD regions thus obtained, and to form contacts with each of the source/drain and gate regions.  
         [0041]     Further, those skilled in the art will understand that the present invention generally applies to the simultaneous forming in a semiconductor substrate of two complementary superposed regions of opposite conductivity types.  
         [0042]     It will be within the abilities of those skilled in the art to select a device  40  capable of implementing the method according to the present invention. It will be, for example, a plasma reactor comprising an enclosure provided with a bottom on which is placed a support or susceptor that may be isolated form the bottom and which is capable of receiving a wafer to be implanted. The plasma is created by any means, for example, by a radio-frequency field and may be confined by electromagnetic fields. Of course, the enclosure comprises means of gas introduction, circulation, and extraction and possibly means for setting a temperature, for example, of support cooling, as well as bias means. The plasma then extends in the entire enclosure and in any case to the vicinity of the wafer to be implanted, as shown in  FIG. 4 .  
         [0043]     Further, “substrate” is used to designated a uniformly-doped silicon wafer as well as epitaxial areas and/or these areas being specifically doped by implantation/diffusion formed on or in a massive substrate.  
         [0044]     Generally, although the present invention has been described in the context of a silicon manufacturing process, it applies to any integrated circuit manufacturing process.  
         [0045]     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.