Abstract:
Apparatus for storing and retrieving data such as in a computer network. A plurality of local data storage units each comprise a local control circuit and a housing which encloses a moveable data transducer adjacent a data storage medium. A shared resource module physically interconnects each of the local units, and includes shared circuitry that supplies a resource required by the local control circuits to transfer data to and from the data storage media. In some preferred embodiments, the resource comprises a programming instruction set that is utilized by a programmable processor in each of the local control circuits, such as servo code used to provide data transducer positional control. Alternatively, the resource comprises a shared buffer memory space utilized by read/write channels in each of the local control circuits. Preferably, data are stored across the data storage media using RAID techniques (redundant array of independent discs/devices).

Description:
FIELD OF THE INVENTION  
       [0001]     The claimed invention relates generally to the field of data storage systems and more particularly, but not by way of limitation, to an apparatus comprising a plurality of local data storage units coupled to a shared resource module to form a data storage subgroup that utilizes local and shared resources to store and retrieve user data.  
       BACKGROUND  
       [0002]     Computer-based systems enable a wide variety of data processing tasks to be accomplished in a fast and efficient manner. From hand-held consumer products to geographically distributed wide area networks with multi-device data storage arrays, such systems continue to increasingly pervade all areas of society and commerce.  
         [0003]     Larger capacity data storage networks sometimes employ multiple numbers of individual data storage devices, such as hard disc drives, which are operationally arrayed together to form a large memory space. RAID techniques (redundant arrays of independent devices/discs) are also sometimes used to enhance the reliability with which data can be stored across such array.  
         [0004]     While various approaches have been proposed in the art to enhance the construction and operation of such arrays, there remains a continual need for improvements in the art, and it is to these and other improvements that the claimed invention is generally directed.  
       SUMMARY OF THE INVENTION  
       [0005]     Preferred embodiments of the present invention are generally directed to an apparatus for storing and retrieving data such as in a computer network.  
         [0006]     In accordance with preferred embodiments, a plurality of local data storage units each comprise a local control circuit and a housing which encloses a moveable data transducer adjacent a data storage medium.  
         [0007]     A shared resource module physically interconnects each of the local units, and includes shared circuitry that supplies a resource required by the local control circuits to transfer data to and from the data storage media.  
         [0008]     In some preferred embodiments, the resource comprises a programming instruction set that is utilized by a programmable processor in each of the local control circuits, such as servo code used to provide data transducer positional control. Alternatively, the resource comprises a shared buffer memory space utilized by read/write channels in each of the local control circuits.  
         [0009]     Preferably, data are stored across the data storage media using RAID techniques (redundant array of independent discs/devices).  
         [0010]     These and various other features and advantages which characterize the claimed invention will become apparent upon reading the following detailed description and upon reviewing the associated drawings. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]      FIG. 1  is an exploded view of a particular construction for a local data storage unit in accordance with preferred embodiments of the present invention.  
         [0012]      FIG. 2  is a generalized elevational view of a data storage subgroup formed from a number of the local units of  FIG. 1 .  
         [0013]      FIG. 3  provides a functional block diagram of the subgroup of  FIG. 2 .  
         [0014]      FIG. 4  provides a functional block diagram of relevant portions of the local circuitry and the subgroup (shared) circuitry of  FIG. 3 .  
         [0015]      FIG. 5  generally illustrates a preferred manner in which servo control resources are divided between the local circuitry and the shared circuitry.  
         [0016]      FIG. 6  generally illustrates a preferred manner in which data communication channel resources are divided between the local circuitry and the shared circuitry.  
         [0017]      FIG. 7  is a block diagram representation of a particular subgroup configured with a RAID 5 architecture.  
         [0018]      FIG. 8  is a block diagram representation of a network system that utilizes a number of the subgroups set forth in  FIG. 7  to provide an array memory space. 
     
    
     DETAILED DESCRIPTION  
       [0019]      FIG. 1  provides an exploded view of a preferred construction for a local data storage unit  100  utilized in accordance with preferred embodiments of the present invention. The local unit  100  includes a rigid, environmentally controlled housing  102  formed from a base deck  104  and a top cover  106 . A spindle motor  108  is mounted within the housing  102  to rotate a number of magnetic data storage media  110  (in this case, two) at a relatively high speed.  
         [0020]     Data are stored on the media  110  in an array of concentric tracks (not shown), which are accessed by a corresponding array of data transducing heads  112  (transducers). The heads  112  are supported by an actuator  114  and moved across the media surfaces by application of current to a voice coil motor, VCM  116 .  
         [0021]     A flex circuit assembly  117  facilitates communication between the actuator  114  and local circuitry mounted on an externally mounted printed circuit board, PCB  118 . In an alternative embodiment, the local circuitry is mounted elsewhere, such as within the interior of the housing  102 , as desired.  
         [0022]     For purposes herein, a head/disc assembly (HDA)  119  is defined as all of the various components of the local unit  100  apart from the local circuitry; that is, the HDA  119  comprises everything in  FIG. 1  except the PCB  118 . With regard to the operational capabilities of the local circuitry, it will be noted that the local unit  100  is not a stand-alone unit. That is, the local circuitry by itself is insufficient to enable the local unit  100  to provide data access operations with the media  108  without the use of separate resources not located within the confines of the local unit  100 .  
         [0023]     Such resources are provided within the context of a data storage subgroup  120 , as shown in  FIG. 2 . The subgroup  120  is formed from a number of local units (in this case, four) nominally identical to the local unit  100  of  FIG. 1 . The local units  100  are respectively coupled to a shared resource module  122 .  
         [0024]     The local units  100  are electrically interconnected with the module  122  via connector assemblies  124 . Each such interconnection provides a plurality of individual paths for the transmission of data, clock signals, power, etc. The connector assemblies  124  can take any number of suitable forms such as, for example, external connectors affixed to the PCB  120  ( FIG. 1 ), or through the use of bulkhead connectors that are integrated with the housing  102  of each local unit  100 . Additional mechanical support of the local units  100  and the subgroup module  122  can be provided through the use of an enclosure (represented by broken line  126  in  FIG. 2 ) that houses the local units  100  and the module  122 .  
         [0025]     The module  122  supports what is referred to herein as subgroup, or shared circuitry  128 , described below. Connector  130  and ribbon cable assembly  132  interconnect the circuitry  128  to other components of a computer network.  
         [0026]      FIG. 3  shows a functional representation of the subgroup  100  of  FIG. 2 . Blocks  134  denote the local circuitry of each of the local units  100 . These local circuitry blocks  134  operationally interface with the subgroup circuitry  128  of the module  122 .  
         [0027]     In  FIG. 4 , the circuitry above dividing line  136  represents a preferred arrangement of the local circuitry  134  of each unit  100 , and the circuitry below line  136  represents a preferred arrangement of the shared circuitry  128  in the subgroup module  122 . The local circuitry  134  includes a local read/write (R/W) channel  138 , preamplifier/driver (preamp) circuit  140 , local processor  142  and local servo circuit  144 .  
         [0028]     The R/W channel  138  operates during a write operation to encode and serialize data to be written to the media  108 . Output signals from the R/W channel  138  are provided to the preamp  140 , which in turn applies appropriate write currents to the associated head  112  to selectively magnetize the medium  108 . During a subsequent read operation, the head  112  transduces a readback signal from the medium which is preamplified by the preamp  140 , and decoded by the R/W channel  138  to output the originally stored data.  
         [0029]     The local processor  142  preferably comprises a general purpose microprocessor or a digital signal processor (DSP). The local processor  142  interfaces with the local servo circuit  144  to carry out servo control operations for the heads  112 , such as seeking to a destination track or track-following on a destination track. The local servo circuit  144  includes demodulation circuitry to demodulate servo data transduced from the media surfaces, as well as power amplifier circuitry to apply current to the VCM  116  ( FIG. 1 ). As required, the local processor  142  further supplies appropriate tap weights or other parametric control values to the R/W channel  140  during the aforementioned read/write operations.  
         [0030]     The shared circuitry  128  preferably includes a subgroup processor  146 , a subgroup buffer  148 , a subgroup interface (I/F) circuit  150 , subgroup servo memory  152 , and various miscellaneous blocks including power regulation circuitry  154 , timing circuitry  156  and diagnostics and monitoring circuitry  158 . Other groupings of circuitry can readily be utilized as desired, depending upon the requirements of a given application. The shared circuitry  128  is preferably incorporated into one or more specially configured ASICs.  
         [0031]     The subgroup processor  146  preferably comprises a relatively powerful general purpose microprocessor which provides top level control for the subgroup  120 . The subgroup buffer  148  is preferably characterized as an SRAM or similar volatile memory space configured to temporarily store data being transferred to or from the media  108  of the local units  100 . The buffer  148  further preferably stores programming steps utilized by the subgroup processor  146 , although this memory can be provided in another location. The subgroup I/F circuit  150  preferably comprises input/output controller hardware that enables the subgroup  120  to communicate with a host device preferably via a standard interface protocol (e.g., SAS, SCSI, fibre channel, etc.).  
         [0032]     The subgroup servo memory  152  preferably comprises SRAM or flash memory to store servo code. The power regulation block  154  supplies power at appropriate voltage levels (+3.3V, ±5V, ±12V, etc.) to the local units  100 . The timing block  156  generates the appropriate clock and other timing signals to the local units  100 , and the diagnostic and monitoring circuit  158  supplies appropriate error recovery and parametric monitoring and analysis capabilities for the units  100 .  
         [0033]     The generalized architecture of  FIG. 4  allows common components to be incorporated onto the shared circuitry of the subgroup module  122 , eliminating the need to incorporate duplicate sets of such components in each local unit  100 . For example, as represented in  FIG. 5 , each local processor  142  utilizes a bus structure  160  to access a single, common instruction set of the servo code programming in the servo memory block  152 .  
         [0034]     Peer-to-peer bus arbitration techniques can be used to allow all of the processors  142  to jointly access the same instruction set without adversely affecting performance of any individual servo loop. It will be recognized that in a subgroup constituting n local units  100 , a savings of n−1 instruction stores for the servo code is achieved by the architecture of  FIGS. 4 and 5  over supplying each local unit with its own individual instruction store.  
         [0035]     Similarly, as shown in  FIG. 6 , each local R/W channel  138  utilizes the subgroup buffer  148  to temporarily store readback data for subsequent transmission to the host, or to receive writeback data to be written to the media  108 . As before, an arbitrated bus structure  162 , preferably under control of the subgroup processor  146 , is used to allow the transfer of data between the subgroup buffer  148  and the local R/W channels  138  without the need for an intermediate memory store therebetween (such as, e.g., a local buffer in each local unit  100 ).  
         [0036]     The size of the subgroup buffer  148  is preferably at least n times the size requirements for each individual local unit  100 . This advantageously allows the buffer memory to more closely follow the lowest cost per megabyte (MB) memory device trends, and eliminates the need to procure older technology, smaller components for each of the units  100 . Also, more expensive memory types, such as ECC protected memory, can be utilized since the cost is spread out over the n local units  100 .  
         [0037]     Another advantage to the shared buffer architecture of  FIG. 6  is that data transfers to the media in the local units  100  can be maintained in a common location under control of the subgroup processor  148 . This would appear to improve efficiencies particularly when readback data are recovered and reassembled from multiple local units  100 , as in a RAID environment. The programming utilized to control such transfers, including rotational optimization of command sequencing for each local unit  100 , is also stored once (e.g., in the buffer  148 ) rather than n times.  
         [0038]     From  FIG. 6  it can be seen that further efficiencies are gained through the use of a single host interface (I/F block  150 ) instead of the use of n separate I/F blocks. The interface structures between the subgroup module  122  and the local units  100  can be a non-standard, simplified interface best suited to the particular application.  
         [0039]      FIG. 7  provides an alternative construction for the subgroup  120 . In this embodiment, five local units  100 , numerically designated as LU  1  through LU  5 , are arranged to store data in a RAID 5 arrangement (i.e., user data and parity data are striped across all of the units). Two separate subgroup modules  122  are coupled to the units  100  for redundancy. A RAID I/F block  172  provides a dual port R/W switch between the respective modules  122 . Although not shown, a second, redundant set of five local units  100  could additionally be incorporated to provide mirroring (i.e., a RAID 5+1 configuration).  
         [0040]      FIG. 8  shows an array  174  formed from a number N of the subgroups  120  discussed above to provide an overall array memory space. This space is controlled by a top level controller  176 . Although not shown, a second array and/or a second controller could also be utilized for redundancy. The controller  176  services access requests to the array from host computers A and B (denoted at  178 ,  180 ) through a network fabric  182 . From a system standpoint, it is contemplated that the local units  100  would be observed to operate the same way as if the array  174  were formed from a plurality of stand-alone data storage devices (e.g., individual hard disc drives).  
         [0041]     From the foregoing discussion it will be clear that the preferred embodiments of the present invention present several advantages over the prior art. Because the individual logical units  100  are not utilized in a stand-alone fashion, but rather are incorporated into a larger storage space, certain efficiencies are gained such as component count reductions and integrations.  
         [0042]     Newer generation technologies, such as for the subgroup processor  146  and the SRAM used for the buffer  148 , can be used to take advantage of higher levels of functionality at lower cost. RAID techniques can now be readily incorporated at the subgroup level, allowing individual subgroups to in turn be used as single devices for higher level RAID structures (e.g., a “RAID within a RAID”).  
         [0043]     It is also envisioned that maintenance updates are also significantly easier to enact; for example, only one new version of servo code or interface controller code be uploaded or otherwise installed, rather than accessing each individual local unit.  
         [0044]     While the local unit  100  disclosed herein has utilized magnetic data storage, it will be appreciated that such is merely for purposes of illustration and is not limiting; rather, any number of other configurations, including optical and magneto-optical data storage, can be used as desired.  
         [0045]     It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this detailed description is illustrative only, and changes may be made in detail, especially in matters of structure and arrangements of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.