Abstract:
A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the substrate. The chip package structure includes first conductive bumps arranged between and in direct contact with the chip package and the substrate providing a clearance. The chip package structure includes a chip structure having a first face and an opposing second face arranged in the clearance between the chip package and the substrate and adjacent to the first conductive bumps. The chip structure contains at least one chip. The chip package structure includes a solder cap connecting the first face of the chip structure and the chip package. The chip package structure includes a second conductive bump connecting the second face of the chip structure and the substrate.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 62/329,833, filed on Apr. 29, 2016, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs. 
     In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. 
     However, since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  is a cross-sectional view of a chip package structure, in accordance with some embodiments. 
         FIG. 1B  is a cross-sectional view of a chip structure, solder caps, and conductive bumps of the chip package structure, in accordance with some embodiments. 
         FIG. 2  is a cross-sectional view of a chip package structure, in accordance with some embodiments. 
         FIG. 3  is a cross-sectional view of a chip package structure, in accordance with some embodiments. 
         FIG. 4  is a cross-sectional view of a chip package structure, in accordance with some embodiments. 
         FIG. 5  is a cross-sectional view of a chip package structure, in accordance with some embodiments. 
         FIG. 6  is a cross-sectional view of a chip package structure, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. 
       FIG. 1A  is a cross-sectional view of a chip package structure  100 , in accordance with some embodiments.  FIG. 1B  is a cross-sectional view of a chip structure, solder caps, and conductive bumps of the chip package structure  100 , in accordance with some embodiments. 
     As shown in  FIG. 1A , a chip package structure  100  is provided, in accordance with some embodiments. The chip package structure  100  includes a substrate  110 , a chip package  120 , conductive bumps (e.g., solder balls)  130 , a chip structure  140 , solder caps  150 , and conductive bumps (e.g., solder balls)  160 , in accordance with some embodiments. The substrate  110  includes a printed circuit board (PCB), a chip, or another suitable structure with wiring layers. 
     The substrate  110  includes a dielectric layer  112 , conductive pads  114   a  and  114   b , wiring layers  116 , and conductive vias  118 , in accordance with some embodiments. The conductive pads  114   a  and  114   b  are formed over the dielectric layer  112 , in accordance with some embodiments. 
     The wiring layers  116  and the conductive vias  118  are formed in the dielectric layer  112 , in accordance with some embodiments. The conductive vias  118 , the wiring layers  116 , and the conductive pads  114   a  and  114   b  are electrically connected to each other, in accordance with some embodiments. 
     The chip package  120  is disposed over the substrate  110 , in accordance with some embodiments. The chip package  120  includes a fan-out package, in accordance with some embodiments. The chip package  120  includes a chip structure  122 , a molding compound  124 , conductive via structures  126 , and a redistribution structure  128 , in accordance with some embodiments. 
     The chip structure  122  includes a chip  122   a , interconnection structures  122   b , and an insulating layer  122   c , in accordance with some embodiments. The interconnection structures  122   b  are formed under the chip  122   a  to be electrically connected to conductive pads P of the chip  122   a , in accordance with some embodiments. The interconnection structures  122   b  include conductive pillars or conductive bumps, in accordance with some embodiments. 
     The insulating layer  122   c  is formed under the chip  122   a  and surrounds the interconnection structures  122   b , in accordance with some embodiments. The insulating layer  122   c  includes a polymer material or another suitable insulating material. The insulating layer  122   c  and the interconnection structures  122   b  are in direct contact with the conductive pads P, in accordance with some embodiments. 
     The molding compound  124  continuously surrounds the chip structure  122  (or the chip  122   a ), in accordance with some embodiments. The molding compound  124  includes a polymer material or another suitable insulating material. The molding compound  124  is in direct contact with the insulating layer  122   c , the chip  122   a , and the redistribution structure  128 , in accordance with some embodiments. 
     The conductive via structures  126  pass through the molding compound  124 , in accordance with some embodiments. The conductive via structures  126  include conductive plugs, in accordance with some embodiments. The conductive via structures  126  include copper, tungsten, aluminum, or another suitable conductive material. 
     The redistribution structure  128  is formed under the chip structure  122 , the molding layer  124 , and the conductive via structures  126 , in accordance with some embodiments. The redistribution structure  128  is between the chip  122   a  and the conductive bumps  130  and between the molding compound  124  and the conductive bumps  130 , in accordance with some embodiments. 
     The redistribution structure  128  includes a dielectric layer  128   a , redistribution layers  128   b , conductive pads  128   c  and  128   d , and conductive vias  128   e , in accordance with some embodiments. The redistribution layers  128   b  and conductive vias  128   e  are in the dielectric layer  128   a , in accordance with some embodiments. 
     The conductive pads  128   c  and  128   d  are over the dielectric layer  128   a , in accordance with some embodiments. The conductive vias  128   e  are between the conductive pads  128   c  and  128   d , the redistribution layers  128   b , the conductive via structures  126 , and the interconnection structures  122   b , in accordance with some embodiments. 
     Therefore, the conductive pads  128   c  and  128   d , the redistribution layers  128   b , the conductive via structures  126 , and the interconnection structures  122   b  are able to be electrically connected to each other through the conductive vias  128   e  according to design requirements, in accordance with some embodiments. The redistribution layers  128   b  are electrically connected to the conductive via structures  126 , in accordance with some embodiments. 
     The conductive bumps  130  are disposed between the chip package  120  and the substrate  110 , in accordance with some embodiments. Each of the conductive bumps  130  is disposed between the conductive pad  128   c  thereover and the conductive pad  114   a  thereunder, in accordance with some embodiments. The conductive bumps  130  are in direct contact with and electrically connected to the chip package  120  and the substrate  110 , in accordance with some embodiments. 
     Each of the conductive bumps  130  is in direct contact with and electrically connected to the conductive pad  128   c  thereover and the conductive pad  114   a  thereunder, in accordance with some embodiments. In some embodiments, some of the conductive bumps  130  are not between the chip  122   a  of the chip package  120  and the substrate  110 . 
     As shown in  FIGS. 1A and 1B , the chip structure  140  is disposed between the chip package  120  and the substrate  110 , in accordance with some embodiments. The chip structure  140  has a first face F 1  and an opposing second face F 2 , in accordance with some embodiments. The first face F 1  faces the chip package  120 , in accordance with some embodiments. The second face F 2  faces the substrate  110 , in accordance with some embodiments. The chip structure  140  is arranged adjacent to the conductive bumps  130 , in accordance with some embodiments. The chip structure  140  is between the conductive bumps  130 , in accordance with some embodiments. The conductive bumps  130  are distributed surrounding the chip structure  140 , in accordance with some embodiments. 
     As shown in  FIGS. 1A and 1B , the chip structure  140  includes a chip  141 , an insulating layer  142 , a redistribution structure  143 , insulating layers  144  and  145 , conductive via structures  146 , an insulating layer  147 , conductive pads  148 , insulating layers  149   a  and  149   b , and conductive pillars L, in accordance with some embodiments. 
     The chip  141  has opposite surfaces  141   a  and  141   b , in accordance with some embodiments. The insulating layer  142  is formed over the surface  141   b , in accordance with some embodiments. The redistribution structure  143  is formed over the insulating layer  142 , in accordance with some embodiments. 
     The redistribution structure  143  includes a dielectric layer  143   a , redistribution layers  143   b , conductive pads  143   c , and conductive vias  143   d , in accordance with some embodiments. The redistribution layers  143   b  and conductive vias  143   d  are in the dielectric layer  143   a , in accordance with some embodiments. The conductive pads  143   c  are over the dielectric layer  143   a , in accordance with some embodiments. 
     The conductive vias  143   d  are between the conductive pads  143   c  and the redistribution layers  143   b , in accordance with some embodiments. Therefore, the conductive pads  143   c  and the redistribution layers  143   b  are able to be electrically connected to each other through the conductive vias  143   d  according to design requirements, in accordance with some embodiments. 
     As shown in  FIG. 1B , through holes TH passing through the chip  141  and the insulating layers  142  and  144  are formed, in accordance with some embodiments. The insulating layer  145  is formed over inner walls A of the through holes TH, in accordance with some embodiments. 
     The conductive via structures  146  are formed in the respective through holes TH, in accordance with some embodiments. The conductive via structures  146  pass through the chip  141 , in accordance with some embodiments. As shown in  FIG. 1B , a portion of the conductive via structure  146  extends outside of the corresponding through hole TH and extends onto the insulating layer  144 , in accordance with some embodiments. 
     The insulating layer  147  is formed over the insulating layer  144  and covers portions of the conductive via structures  146 , in accordance with some embodiments. The insulating layer  147  has openings  147   a , in accordance with some embodiments. The openings  147   a  expose the respective conductive via structures  146  thereunder, in accordance with some embodiments. 
     The conductive pads  148  are formed in the respective openings  147   a , in accordance with some embodiments. A portion of the conductive pad  148  extends outside of the opening  147   a  and extends onto the insulating layer  147 , in accordance with some embodiments. 
     The insulating layer  149   a  is formed over the insulating layer  147  and covers portions of the conductive pads  148 , in accordance with some embodiments. The insulating layer  149   a  has openings OP 1 , in accordance with some embodiments. The openings OP 1  expose the respective conductive pads  148  thereunder, in accordance with some embodiments. 
     The insulating layer  149   b  is formed over the insulating layer  149   a  and covers portions of the conductive pads  148 , in accordance with some embodiments. The insulating layer  149   b  has openings OP 2 , in accordance with some embodiments. The openings OP 2  expose the respective conductive pads  148  thereunder, in accordance with some embodiments. 
     The conductive pillars L are formed in the respective openings OP 2 , in accordance with some embodiments. A portion of the conductive pillar L extends outside of the corresponding opening OP 2 , in accordance with some embodiments. 
     The conductive structures of the chip structure  140  (e.g., the redistribution layers  143   b , the conductive pads  143   c , the conductive vias  143   d , the conductive via structures  146 , the conductive pads  148 , or the conductive pillars L) include copper, aluminum, tungsten, or another suitable conductive material. 
     As shown in  FIG. 1B , solder caps  150  are formed over the respective conductive pillars L, in accordance with some embodiments. The solder caps  150  include a solder material, such as tin, in accordance with some embodiments. As shown in  FIG. 1B , conductive bumps  160  are formed over the respective conductive pads  143   c , in accordance with some embodiments. The conductive bumps  130  and  160  include a solder material, such as tin, in accordance with some embodiments. 
     As shown in  FIGS. 1A and 1B , the solder caps  150  are positioned between the chip package  120  and the chip structure  140 , in accordance with some embodiments. The solder caps  150  are in direct contact with the chip package  120  and the chip structure  140 , in accordance with some embodiments. The solder caps  150  connect the first face F 1  of the chip structure  140  and the chip package  120 , in accordance with some embodiments. Each of the solder caps  150  is positioned between the conductive pillar L thereunder and the conductive pad  128   d  thereover, in accordance with some embodiments. 
     Each of the solder caps  150  is in direct contact with the conductive pillar L thereunder and the conductive pad  128   d  thereover, in accordance with some embodiments. Each of the solder caps  150  is electrically connected to the conductive pillar L thereunder and the conductive pad  128   d  thereover, in accordance with some embodiments. 
     As shown in  FIGS. 1A and 1B , the conductive bumps  160  are positioned between the chip structure  140  and the substrate  110 , in accordance with some embodiments. The conductive bumps  160  are in direct contact with the chip structure  140  and the substrate  110 , in accordance with some embodiments. The conductive bumps  160  connect the second face F 2  of the chip structure  140  and the substrate  110 , in accordance with some embodiments. Each of the conductive bumps  160  is positioned between the conductive pad  114   b  thereunder and the conductive pad  143   c  thereover, in accordance with some embodiments. 
     Each of the conductive bumps  160  is in direct contact with the conductive pad  114   b  thereunder and the conductive pad  143   c  thereover, in accordance with some embodiments. Each of the conductive bumps  160  is electrically connected to the conductive pad  114   b  thereunder and the conductive pad  143   c  thereover, in accordance with some embodiments. The conductive via structures  146  electrically connect the solder caps  150  to the conductive bumps  160 , in accordance with some embodiments. 
     In some embodiments, a maximum width W 1  of the conductive bump  130  is greater than a maximum width W 2  of the conductive bump  160 . In some embodiments, the maximum width W 2  of the conductive bump  160  is greater than a maximum width W 3  of the solder cap  150 . In some embodiments, a maximum width W 4  of the chip structure  140  is greater than the maximum width W 1  of the conductive bump  130 . 
     In some embodiments, a distance D 1  between two adjacent conductive bumps  130  is greater than a distance D 2  between two adjacent conductive bumps  160 . In some embodiments, the distance D 2  between two adjacent conductive bumps  160  is greater than a distance D 3  between two adjacent solder caps  150 . 
     In some embodiments, the solder cap  150 , the chip structure  140 , and the conductive bump  160  have maximum heights H 2 , H 3 , and H 4  respectively. In some embodiments, a maximum height H 1  of the conductive bump  130  is equal to or greater than a maximum total height (H 2 +H 3 +H 4 ) of the solder cap  150 , the chip structure  140 , and the conductive bump  160 . 
     As shown in  FIG. 1A , the chip package structure  100  further includes a filling layer  170 , in accordance with some embodiments. The filling layer  170  is filled between the chip package  120  and the substrate  110 , in accordance with some embodiments. 
     The filling layer  170  continuously surrounds the conductive bumps  130  and  160 , the chip structure  140 , and the solder caps  150 , in accordance with some embodiments. The filling layer  170  includes an insulating material (e.g., a polymer material), in accordance with some embodiments. 
     As shown in  FIG. 1A , the chip package structure  100  further includes a chip package  180 , in accordance with some embodiments. The chip package  180  is disposed over the chip package  120 , in accordance with some embodiments. The chip package  180  includes a redistribution structure  181 , chips  182  and  183 , conductive wires  184  and  185 , and a molding compound  186 , in accordance with some embodiments. 
     The redistribution structure  181  includes a dielectric layer  181   a , redistribution layers  181   b , conductive pads  181   c  and  181   d , and conductive vias  181   e , in accordance with some embodiments. The redistribution layers  181   b  and conductive vias  181   e  are in the dielectric layer  181   a , in accordance with some embodiments. The conductive pads  181   c  and  181   d  are over opposite sides of the dielectric layer  181   a , in accordance with some embodiments. 
     The conductive vias  181   e  are between the conductive pads  181   c  and  181   d  and the redistribution layers  181   b , in accordance with some embodiments. Therefore, the conductive pads  181   c  and  181   d  and the redistribution layers  181   b  are able to be electrically connected to each other through the conductive vias  181   e  according to design requirements, in accordance with some embodiments. 
     The chip  182  is disposed over the redistribution structure  181 , in accordance with some embodiments. The conductive wires  184  (electrically) connect respective conductive pads  182   a  of the chip  182  to the respective conductive pads  181   c , in accordance with some embodiments. 
     The chip  183  is disposed over the chip  182 , in accordance with some embodiments. The conductive wires  185  (electrically) connect respective conductive pads  183   a  of the chip  183  to the respective conductive pads  181   c , in accordance with some embodiments. 
     The molding compound  186  is formed over the redistribution structure  181  to cover the chips  182  and  183  and the conductive wires  184  and  185 , in accordance with some embodiments. The molding compound  186  includes an insulating material (e.g., a polymer material), in accordance with some embodiments. 
     As shown in  FIG. 1A , the chip package structure  100  further includes conductive bumps  190 , in accordance with some embodiments. The conductive bumps  190  are formed between the conductive pads  181   d  and the conductive via structures  126 , in accordance with some embodiments. The conductive bumps  190  electrically connect the conductive pads  181   d  to the conductive via structures  126 , in accordance with some embodiments. 
     As shown in  FIG. 1A , the chip package structure  100  further includes a filling layer  210 , in accordance with some embodiments. The filling layer  210  is filled between the chip packages  180  and  120 , in accordance with some embodiments. The filling layer  210  continuously surrounds the conductive bumps  190  and the chip package  180 , in accordance with some embodiments. 
     The filling layer  210  includes an insulating material (e.g., a polymer material), in accordance with some embodiments. The filling layer  210  further extends onto the sidewalls of the dielectric layer  181   a  and the molding compound  186 , in accordance with some embodiments. The filling layer  210  surrounds the dielectric layer  181   a  and the molding compound  186 , in accordance with some embodiments. 
     Since the chip structure  140  has the conductive via structures  146  to electrically connect the chip package  120  to the substrate  110 , the chip structure  140  has the function of the conductive bump(s)  130 , in accordance with some embodiments. 
     Therefore, the chip structure  140  maintains or increases the conductive paths between the chip package  120  and the substrate  110 , in accordance with some embodiments. As a result, the chip structure  140  improves the routability of the redistribution structure  128  and the wiring layers  116 , in accordance with some embodiments. 
     Furthermore, the chip structure  140  further has active devices and/or passive devices. Therefore, the chip package structure  100  with the chip structure  140  has devices more than the chip package structure without the chip structure  140  and with the same size as the chip package structure  100 , in accordance with some embodiments. 
     That is, the chip structure  140  increases the device density of the chip package structure  100 , in accordance with some embodiments. As a result, the performance of the chip package structure  100  is improved. 
       FIG. 2  is a cross-sectional view of a chip package structure  200 , in accordance with some embodiments. As shown in  FIG. 2 , the chip package structure  200  is similar to the chip package structure  100 , except that the substrate  110  of the chip package structure  200  further has a recess  111 , in accordance with some embodiments. The conductive pads  114   b  are formed in the recess  111  and over the dielectric layer  112 , in accordance with some embodiments. 
     The chip structure  140  is over the recess  111 , in accordance with some embodiments. The chip structure  140  includes active devices and/or passive devices, in accordance with some embodiments. The width W 5  of the recess  111  is greater than the width W 4  of the chip structure  140 , in accordance with some embodiments. The conductive bumps  160  are formed between the chip structure  140  and the conductive pads  114   b , in accordance with some embodiments. 
     All of the conductive bumps  160  are in the recess  111 , in accordance with some embodiments. The solder caps  150  are over the recess  111 , in accordance with some embodiments. The solder caps  150  are between the chip structure  140  and the conductive pads  128   d , in accordance with some embodiments. 
     Since the substrate  110  has the recess  111 , the maximum heights H 2 , H 3 , and H 4  (as shown in  FIG. 1B ) of the solder cap  150 , the chip structure  140 , and the conductive bump  160  are enlarged, in accordance with some embodiments. Therefore, devices and redistribution layers of the chip structure  140  may be increased. The structural strength of the chip structure  140  may be improved. 
     Since the maximum height H 4  of the conductive bump  160  is enlarged, the size of the conductive bump  160  is enlarged. Therefore, the connection of the conductive bump  160  to the conductive pad  143   c  thereover and the conductive pad  114   b  thereunder is improved, in accordance with some embodiments. 
       FIG. 3  is a cross-sectional view of a chip package structure  300 , in accordance with some embodiments. As shown in  FIG. 3 , the chip package structure  300  is similar to the chip package structure  100 , except that the chip structure  140 , the solder caps  150 , and the conductive bumps  160  are between the chip packages  120  and  180 , in accordance with some embodiments. 
     The redistribution structure  181  further includes conductive pads  181   f , in accordance with some embodiments. The conductive pads  181   f  is embedded in the dielectric layer  181   a , in accordance with some embodiments. The solder caps  150  are between the conductive pads  181   f  and the chip structure  140 , in accordance with some embodiments. The conductive pads  181   f  are electrically connected to the chip structure  140  through the solder caps  150 , in accordance with some embodiments. 
     The chip package  120  further includes dielectric layers  129   a  and  129   b  and a redistribution layer  129   c , in accordance with some embodiments. The dielectric layer  129   a  is formed over the chip  122   a , in accordance with some embodiments. 
     The dielectric layer  129   b  is formed over the molding compound  124 , the dielectric layer  129   a , and the conductive via structures  126 , in accordance with some embodiments. The dielectric layer  129   b  has recesses R, in accordance with some embodiments. The recesses R expose the conductive via structures  126  and a portion of the dielectric layer  129   a , in accordance with some embodiments. 
     The redistribution layer  129   c  is formed over the dielectric layer  129   b  and extends into the recesses R, in accordance with some embodiments. The redistribution layer  129   c  is electrically connected to the conductive via structures  126 , in accordance with some embodiments. The conductive bumps  190  are formed between the conductive pads  181   d  and the redistribution layer  129   c , in accordance with some embodiments. 
     The conductive bumps  190  electrically connect the conductive pads  181   d  to the redistribution layer  129   c , in accordance with some embodiments. The conductive bumps  190  are not formed between the chips  182 ,  183 , and  122   a , in accordance with some embodiments. 
     The conductive bumps  160  are between the conductive pads  143   c  of the chip structure  140  and the redistribution layer  129   c , in accordance with some embodiments. The conductive bumps  160  electrically connect the conductive pads  143   c  to the redistribution layer  129   c , in accordance with some embodiments. The conductive bumps  160  are positioned in the respective recesses R, in accordance with some embodiments. 
     Since the chip structure  140  has the conductive via structures  146  to electrically connect the chip package  120  to the chip package  180 , the chip structure  140  has the function of the conductive bump(s)  190 , in accordance with some embodiments. 
     Therefore, the chip structure  140  maintains or increases the conductive paths between the chip packages  120  and  180 , in accordance with some embodiments. As a result, the chip structure  140  improves the routability of the redistribution structure  181  and the redistribution layer  129   c , in accordance with some embodiments. 
     Furthermore, the chip structure  140  further has active devices and/or passive devices. Therefore, the chip package structure  300  with the chip structure  140  has devices more than the chip package structure without the chip structure  140  and with the same size as the chip package structure  300 , in accordance with some embodiments. That is, the chip structure  140  increases the device density of the chip package structure  300 , in accordance with some embodiments. As a result, the performance of the chip package structure  300  is improved. 
       FIG. 4  is a cross-sectional view of a chip package structure  400 , in accordance with some embodiments. As shown in  FIG. 4 , the chip package structure  400  is similar to the chip package structure  300 , except that the redistribution structure  181  of the chip package structure  180  further has a recess  181   g , in accordance with some embodiments. The solder caps  150  are formed in the recess  181   g  and between conductive pads  181   f  and the chip structure  140 , in accordance with some embodiments. 
     All of the solder caps  150  are in the recess  181   g , in accordance with some embodiments. The chip structure  140  is under the recess  181   g , in accordance with some embodiments. The conductive bumps  160  are under the recess  181   g , in accordance with some embodiments. The width W 6  of the recess  181   g  is greater than the width W 4  of the chip structure  140 , in accordance with some embodiments. 
     Since the redistribution structure  181  has the recess  181   g , the maximum heights H 2 , H 3 , and H 4  (as shown in  FIG. 1B ) of the solder cap  150 , the chip structure  140 , and the conductive bump  160  are enlarged, in accordance with some embodiments. Therefore, devices and redistribution layers of the chip structure  140  may be increased. The structural strength of the chip structure  140  may be improved. 
     Since the maximum height H 4  of the conductive bump  160  is enlarged, the size of the conductive bump  160  is enlarged. Therefore, the connection of the conductive bump  160  to the conductive pad  143   c  thereover and the redistribution layer  129   c  thereunder is improved, in accordance with some embodiments. 
       FIG. 5  is a cross-sectional view of a chip package structure  500 , in accordance with some embodiments. As shown in  FIG. 5 , the chip package structure  500  is similar to the chip package structure  300 , except that the size and the arrangement of the solder caps  150  of chip package structure  500  are different from that of the chip package structure  300 , in accordance with some embodiments. 
     In some embodiments, the maximum width W 2  of the conductive bump  160  is equal to the maximum width W 3  of the solder cap  150 . In some other embodiments, the maximum width W 2  of the conductive bump  160  is less than the maximum width W 3  of the solder cap  150 . 
     In some embodiments, the distance D 2  between two adjacent conductive bumps  160  is equal to the distance D 3  between two adjacent solder caps  150 . In some embodiments, the distance D 2  between two adjacent conductive bumps  160  is less than the distance D 3  between two adjacent solder caps  150 . 
       FIG. 6  is a cross-sectional view of a chip package structure  600 , in accordance with some embodiments. As shown in  FIG. 6 , the chip package structure  600  is similar to the chip package structure  300 , except that the arrangement of the conductive bumps  190  of chip package structure  600  are different from that of the chip package structure  300 , in accordance with some embodiments. 
     In some embodiments, the distance D 4  between two adjacent conductive bumps  190  is greater than the distance D 2  between two adjacent conductive bumps  160 . In some embodiments, the distance D 4  between two adjacent conductive bumps  190  is greater than the distance D 3  between two adjacent solder caps  150 . 
     In accordance with some embodiments, chip package structures are provided. The chip package structure has a chip structure between a chip package and a substrate (or another chip package). The chip structure has conductive via structures to electrically connect the chip package to the substrate, and therefore the chip structure has the function of the conductive bump(s). Therefore, the chip structure maintains or increases the conductive paths between the chip package and the substrate. As a result, the chip structure improves the routability of a redistribution structure of the chip package and wiring layers of the substrate. Furthermore, the chip structure further has active devices and/or passive devices. Therefore, the chip structure increases the device density of the chip package structure. As a result, the performance of the chip package structure is improved. 
     The substrate has recess under the chip structure. Therefore, the maximum height of the chip structure is enlarged. Therefore, devices and redistribution layers of the chip structure are increased. The structural strength of the chip structure is improved. 
     In accordance with some embodiments, a chip package structure is provided. The chip package structure includes a chip package. The chip package structure includes a substrate. The chip package structure includes first conductive bumps between and in direct contact with the chip package and the substrate. The chip package structure includes a chip structure between the chip package and the substrate and adjacent to the first conductive bumps. The chip package structure includes solder caps between the chip package and the chip structure. The chip package structure includes second conductive bumps between the chip structure and the substrate. The chip package structure includes conductive via structures passing through a chip of the chip structure. The conductive via structures electrically connect the solder caps to the second conductive bumps. 
     In accordance with some embodiments, a chip package structure is provided. The chip package structure includes a first chip package. The chip package structure includes a second chip package. The chip package structure includes first conductive bumps between and in direct contact with the first chip package and the second chip package. The chip package structure includes a chip structure between the first chip package and the second chip package and adjacent to the first conductive bumps. The chip package structure includes solder caps between the first chip package and the chip structure. The chip package structure includes second conductive bumps between the chip structure and the second chip package. 
     In accordance with some embodiments, a chip package structure is provided. The chip package structure includes a chip package. The chip package structure includes a substrate. The chip package structure includes first conductive bumps between the chip package and the substrate. The chip package structure includes a chip structure between the chip package and the substrate and adjacent to the first conductive bumps. The chip package structure includes solder caps between the chip package and the chip structure. The chip package structure includes second conductive bumps between the chip structure and the substrate. A maximum height of the first conductive bump is equal to or greater than a maximum total height of the second conductive bump, the chip structure, and the solder cap. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.