Abstract:
A switch drive circuit utilizes charge transfer within and/or between boost circuit and/or snubber circuits for boosted switch drives. A boost circuit may include a divider to limit a boosted signal for driving a switch. A snubber circuit may transfer charge to a boost circuit.

Description:
This application claims priority from U.S. Provisional Application Ser. No. 60/598,666 entitled Gate Drive and Snubber for Switching Power Supply, filed Aug. 2, 2004, which is incorporated by reference. 
    
    
     BACKGROUND 
       FIG. 1  illustrates a prior art gate drive circuit for a switching power supply. The circuit of  FIG. 1  includes two transistors Q 1  and Q 2  connected to a switch node SW and arranged to alternately switch an inductor between two different power supply terminals PS and GND. This type of switch arrangement is commonly used in switching power supplies such as a synchronous buck converter. Transistors Q 1  and Q 2  are controlled by input signals IN 1  and IN 2  which drive the gates of Q 1  and Q 2  through drive circuits  10  and  12 , respectively. 
     Drive circuit  12  can receive its power from the positive power supply terminal PS because the source of Q 2  is referenced to the power supply ground terminal GND. However, the source of Q 1  is referenced to the switch terminal SW which is at nearly the same voltage as PS when the gate of Q 1  must be driven with a significantly higher voltage than PS. Therefore, the circuit of  FIG. 1  includes a boost circuit  14  to generate a boosted power supply BST which is used to operate the drive circuit  10  for Q 1 . Boost circuit  14  includes a diode D B  and capacitor C B  connected in a charge pump arrangement. 
     The circuit of  FIG. 1  also includes an RC snubber circuit  16  which dampens voltage spikes at the switch terminal SW caused by parasitic inductances in the transistors, the PC board on which they may be mounted, as well as the main inductor for the switching power supply. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a prior art gate drive circuit for a switching power supply. 
         FIG. 2  illustrates an embodiment of a circuit according to some of the inventive principles of this patent disclosure. 
         FIG. 3  illustrates another embodiment of a circuit according to some of the inventive principles of this patent disclosure. 
         FIG. 4  illustrates an embodiment of a circuit showing some additional implementation details according to some of the inventive principles of this patent disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to the circuit of  FIG. 1 , as an operational example, the power supply PS is assumed to be at a positive voltage V PS , and the power supply terminal GND is assumed to be at ground potential. Capacitor C B  in the boost circuit is charged to V PS -V D  when the low-side transistor Q 2  is turned on, that is, when the switch node SW is grounded through Q 2  (except for any resistive drop through Q 2 ). This capacitor voltage is driven onto the gate of high-side transistor Q 1  through driver  10  when input IN 1  is activated. The capacitor voltage added to the voltage at the switch node SW when Q 1  is on creates the boost voltage V BST  at the boost terminal BST. This places almost the full supply voltage V PS  (minus diode drop) across the gate-source input of Q 1  and requires C B  to store enough charge to charge up the gate capacitance of Q 1  to almost the full supply voltage. This can cause high switching losses due to the large amount of charge involved. 
     One possible technique for reducing the switching losses is to provide a lower supply voltage to the boost circuit  14 , i.e., not connect it directly to PS. The reduced supply voltage would need to be high enough to generate a boost voltage V BST  that turns the high-side transistor Q 1  completely on so as to minimize conduction losses through Q 1 , but low enough to minimize switching losses. There would typically be an optimum reduced supply voltage that would result in an optimum boost voltage, but the reduced supply voltage would usually have to be generated by a special circuit that adds cost and complexity to the system. 
     Another potentially problematic aspect of the circuit of  FIG. 1  is the power loss in the snubber circuit  16 . In many situations, a snubber circuit may be essential to prevent voltage spikes from damaging transistors Q 1  and Q 2 . However, a substantial amount of charge is shunted to ground through the snubber, thereby wasting power and reducing efficiency. 
     Some of the inventive principles of this patent disclosure relate to transferring charge within and/or between boost circuits and/or snubber circuits.  FIG. 2  illustrates an embodiment of a circuit that transfers charge according to some of the inventive principles of this patent disclosure. The circuit of  FIG. 2  includes a first switch  18  arranged between a power supply terminal PS and a switch node SW and controlled by a drive signal at drive node DRV 1 . A second switch  20  is arranged between SW and a second power supply terminal GND and controlled by a second drive signal at a second drive node DRV 2 . The drive signals DRV 1  and DRV 2  are generated by drive circuits  22  and  24  in response to switch input signals IN 1  and IN 2 , respectively. 
     A boost circuit  26  generates a boosted signal V BST  at boost node BST to operate the drive circuit  22 . The boost circuit includes a divider circuit  28 , shown conceptually in this example as a capacitive divider that transfers charge between components to limit the boosted signal. 
       FIG. 3  illustrates another embodiment of a circuit that transfers charge according to some of the inventive principles of this patent disclosure. The circuit of  FIG. 3  includes switches  18  and  20  and drive circuits  22  and  24  arranged in the same manner as the circuit of  FIG. 2 . The circuit of  FIG. 3 , however includes a snubber circuit  30  arranged to transfer charge to a boost circuit  32  which generates a boosted signal V BST  for providing power to drive the switch  18 . 
       FIG. 4  illustrates an embodiment of a circuit showing some example implementation details according to some of the inventive principles of this patent disclosure. Switches  18  and  20  are implemented as metal oxide semiconductor field effect transistors (MOSFETs), but any other type of suitable switches may be used. Drive circuits  22  and  24  may be any suitable gate drivers. A boot-strap diode D 1  is connected between a power source node PS and a boost node BST. A capacitor C 1  is connected between the switch node SW and the boost node BST, preferably through a resistor R 1 . A second capacitor C 2  is connected between BST and power supply GND. Capacitors C 1  and C 2  form a capacitive voltage divider that reduces the boost voltage V BST  at boost node BST. The arrangement of components shown in  FIG. 4  also provides snubbing at switch node SW which may transfer charge from the switch node SW to the boost circuit. 
     Depending on the details of implementation, the circuit of  FIG. 4  may reduce switching losses because of the reduced voltage level of the boost signal V BST  due to the voltage dividing effect of C 1  and C 2 . It may also provide optimized slew-rate control when switch  18  is turned on because of the feedback from switch node SW to the boost node BST through R 1 /C 1  and C 2 . That is, the voltage at the gate of transistor  18  may ramp up quickly to turn the transistor on quickly, then final slew-rate control may reduce voltage spikes at the switch node SW. The snubbing of the SW node through the interaction of R 1  in series with the C 1 /C 2  combination may provide better snubbing response than prior art methods because the snubbing is in the feedback of the driver. The arrangement of  FIG. 4  may reduce stresses on some or all of the components, for example, the voltage stresses on the switches and the boot strap diode. The overall efficiencies that may be obtained from the circuit of  FIG. 4  may, in turn, enable the use of fewer and/or lower cost switches and other components to be used. Yet another potential benefit of the circuit of  FIG. 4  is that resistor R 1  may reduce stress by limiting current surges through the boot-strap diode. Because the boosting and snubbing functions are integrated into the same components, these potential benefits may be realized without additional components and their associated costs. A further potential benefit is that efficiency may be improved because charge that may have been wasted by shunting to ground may be preserved by transferring it to the boost node. 
     Although not necessary to an understanding of the inventive principles of this patent disclosure, some helpful equations relating to component values in  FIG. 4  are provided as follows. The value of the capacitors may be determined from: 
               C   1     =       10   ×       Q   GATE         V   CC     -     V   D         ⁢           ⁢   and   ⁢           ⁢     C   2       =       10   ×       Q   GATE       V   GATE         -     C   1               
where Q GATE  is the total charge required on the gate of switch  18  at the desired gate voltage V GATE , V CC  is the power supply voltage, and V D  is the voltage drop across D 1 . The peak surge current I F(PEAK)  rating for the boot-strap diode may be determined from:
 
     
       
         
           
             
               I 
               
                 F 
                 ⁡ 
                 
                   ( 
                   PEAK 
                   ) 
                 
               
             
             = 
             
               
                 
                   V 
                   CC 
                 
                 - 
                 
                   V 
                   D 
                 
               
               
                 R 
                 1 
               
             
           
         
       
     
     The inventive principles of this patent disclosure have been described above with reference to some specific example embodiments, but these embodiments can be modified in arrangement and detail without departing from the inventive concepts. For example, switches have been shown in some embodiments as MOSFETS, but any other suitable switches may be used in accordance with the inventive principles of this patent disclosure. As a further example, the power supply and boosted signals are not limited to any particular polarity, voltage or switching power supply topology. As yet another example, resistor R 1  may be rearranged or omitted from the circuit of  FIG. 4  while still maintaining beneficial results. And as yet another example, the arrangement of C 2  may be between BST and other nodes besides GND. Thus, such changes and modifications are considered to fall within the scope of the following claims.