Abstract:
Embodiments of the present invention include a semiconductor structure including two transistor structures separated by a dummy gate of a different material and methods for forming said structure. Embodiments including forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the third sacrificial gate with an insulating material. The insulating material replacing the third sacrificial gate may serve as a dummy gate to electrically isolate nearby source/drain regions. Embodiments further include forming sacrificial gates on a semiconductor substrate, forming spacers on the sacrificial gates, forming source/drain regions adjacent to two sacrificial gates separated by a third sacrificial gate, and replacing the two sacrificial gates with metal gates while leaving the third sacrificial gate in place to serve as a dummy gate.

Description:
BACKGROUND 
       [0001]    The present invention generally relates to integrated circuit devices, and particularly to structures for isolating adjacent devices without the use of shallow trench isolation (STI). 
         [0002]    Due to the nature of epitaxial growth and certain structural features of integrated circuit devices, epitaxially grown regions may exhibit undesirably formed shapes that impact device performance and reliability. For example, the formation of epitaxially grown raised source/drain regions at the edge of STI regions of semiconductor devices may cause the raised source/drain regions to have faceted shapes at the STI region edges. The faceted shape of these raised source/drain regions may reduce the surface area of the raised source/drain regions. This reduced surface area in turn may undesirably increase the resistance between the raised source/drain regions and any formed contacts that are operable to provide device connectivity. Thus, since within integrated circuits a vast number of connections are needed, any degradation in connection resistance may compromise device operation within the integrated circuits and, therefore, lead to a reduction in device performance and yield. 
         [0003]      FIG. 1  refer to a semiconductor structure  100  derived from a processes associated with growing epitaxial regions at the edges of STI regions formed on an SOI substrate, as is known in the art. In particular,  FIG. 1  illustrates grown source/drain regions  130  and  170  for nFET and pFET devices  101  and  103 , respectively. As depicted, the source/drain regions  130 ,  170  are grown at the edge of STI region  102 , which includes divots  140 ,  180 . 
         [0004]    Source/drain regions  130  and  170  are formed after creating STI region  102 . As depicted, the STI region  102  includes divots  140  and  180 , which are a bi-product of the STI formation process. Since the STI region  102  and its corresponding divots  140 ,  180  are formed prior to growth of the source/drain regions  130 ,  170 , during such epitaxial growth; faceting occurs at the respective interfaces  138 ,  141  between the grown source/drain regions  130 ,  170  and the STI region  102 . Accordingly, based on the created facets  176 ,  132  that result from the formed divots  180 ,  140  associated with STI region  102 , source/drain regions  130  and  170  include reduced contact surfaces S 1  and S 1 ′ for connecting to contacts  190   b  and  190   c,  respectively. The reduced surfaces may establish a poor electrical connection with the contacts  190   b,    190   c.  Poor electrical connections cause increased contact resistance and, therefore, a potential device operation failure. 
         [0005]    In contrast, source/drain regions  128  and  172 , which are not located adjacent the STI region  102 , are not effected by the STI region&#39;s  102  formed divots  180 ,  140  and, therefore, do not exhibit the faceting observed at source/drain regions  130  and  170 . Therefore, contact surfaces S 2  and S 2 ′ for connecting to contacts  190   a  and  190   d,  respectfully, provide optimal electrical connectivity relative to contact surfaces S 1  and S 1 ′. 
         [0006]    Source/drain regions which are bounded by STI regions are important to the layout of practical circuits. They isolate connections to unrelated transistors in a circuit, allowing flexibility in the placement and connectivity between transistors. One potential solution to the contact degradation requires the addition of an additional unused gate to allow the extension of adjacent source/drain regions make them similar to non-STI bounded ones. This results in the addition of one unused device space for every required device break, resulting in a significant loss in circuit density of upwards of  20 %. Therefore, a process which allows for the isolation of adjacent transistors without incurring the reduced quality source/drain regions while reducing the loss of circuit density is desirable. 
       BRIEF SUMMARY 
       [0007]    The present invention relates to a semiconductor device including two transistors separated by a dummy gate of a different material and methods of forming said semiconductor device. 
         [0008]    One embodiment of the present invention includes a semiconductor substrate; a first transistor including a first metal gate, spacers on the sidewalls of the first metal gate, source/drains on each side of the first metal gate; a second transistor including a second metal gate, spacers on the sidewalls of the second metal gate, and source drains on each side of the second metal gate; and a dummy gate located on the surface of the semiconductor substrate between the first transistor and the second transistor. In one embodiment, the dummy gate includes an insulating material that electrically isolates the source/drains of the first transistor from the source/drains of the second transistor. 
         [0009]    Another embodiment includes forming, on a semiconductor substrate, a first sacrificial gate, a second sacrificial gate, and a third sacrificial gate located between the first sacrificial gate and the second sacrificial gate; forming spacers on sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate; forming a first source/drain on the semiconductor substrate between the first gate and the third gate, and a second source/drain on the semiconductor substrate between the second gate and the third gate; removing the third sacrificial gate to form a dummy recess region; and filling the dummy recess region with insulating material to form a dummy gate. The dummy gate isolates the first source/drain from the second source drain. 
         [0010]    Another embodiment of the present invention includes forming, on a semiconductor substrate, a first sacrificial gate, a second sacrificial gate, and a third sacrificial gate located between the first sacrificial gate and the second sacrificial gate; forming spacers on sidewalls of the first sacrificial gate, the second sacrificial gate, and the third sacrificial gate; forming a first source/drain on the semiconductor substrate between the first gate and the third gate, and a second source/drain on the semiconductor substrate between the second gate and the third gate; removing the first and third sacrificial gates to form gate recess regions; and filling the gate recess regions with metal to form a metal gates. In some embodiments, the third sacrificial gate may comprise an insulating material. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0011]      FIG. 1  is a vertical cross-sectional view of a semiconductor structure that illustrates the formation of facetted epitaxial regions located at the edges of an STI region, as is known in the art; 
           [0012]      FIGS. 2A-2L  are vertical cross-sectional views that illustrate the formation of a semiconductor structure having two transistor devices having sacrificial gates separated by a third sacrificial gate of the same material; 
           [0013]      FIGS. 2M-2T  are vertical cross-sectional views that illustrate replacing sacrificial gates of the two transistor structures with metal gates and the third sacrificial gate of  FIGS. 2A-2L  with a dummy gate of a different material, according to one embodiment of the invention. 
           [0014]      FIGS. 3A-3H  are vertical cross-sectional views that illustrate replacing sacrificial gates of the two transistor structures with metal gates and the third sacrificial gate of  FIGS. 2A-2L  with a dummy gate of a different material, according to another embodiment of the invention. 
           [0015]      FIGS. 4A-4E  are vertical cross-sectional views that illustrate replacing sacrificial gates of the two transistor structures with metal gates while leaving the third sacrificial gate in place to isolate the two transistor structures, according to one embodiment of the invention. 
       
    
    
       [0016]    Elements of the figures are not necessarily to scale and are not intended to portray specific parameters of the invention. For clarity and ease of illustration, dimensions of elements may be exaggerated. The detailed description should be consulted for accurate dimensions. The drawings are intended to depict only typical embodiments of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements. 
       DETAILED DESCRIPTION 
       [0017]    Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments. 
         [0018]    While the present invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that changes in forms and details may be made without departing from the spirit and scope of the described embodiments. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims. 
         [0019]    The following embodiments describe methods for manufacturing two adjacent field effect transistors (FETs) isolated by the formation of a dummy gate of a different material between the adjacent FETs. The disclosed embodiments depict two adjacent FETs of the same type (i.e. both pFETs or both nFETs) for illustrative simplicity, but a person of ordinary skill in the art will understand how to manufacture embodiments where the adjacent FETs are of different types. 
         [0020]      FIGS. 2A-2L  depict a process of manufacturing two FET structures each having a sacrificial gate, and a third sacrificial gate of the same material separating the two FET structures. Referring to  FIG. 2A , a layer stack  300  is depicted including, semiconductor substrate  301 , dielectric layer  302 , sacrificial gate layer  303 , hard mask layer  304 , and photoresist layer  305 . Substrate  301  may be made of bulk silicon and may be 750-800 um thick. In other embodiments, substrate  301  may include a silicon-on-insulator (SOI) layer. Dielectric layer  302  may be made for example, silicon oxide, and may be 20-60 Å thick, preferably 25-45 Å. Sacrificial gate layer  303  may be made of silicon and may be 400-1000 Å thick, preferably 500-800 Å. Hard mask layer  304  may be made of nitride and be 300-1000 Å thick, preferably 400-700 Å. Layer stack  300  may be formed by any known methods in the art. 
         [0021]      FIG. 2B  depicts the removal of portions of photoresist layer  305  to form photoresist sections  305   a,    305   b,  and  305   c,  and exposing surfaces  304   a,    304   b,    304   c,  and  304   d  of hard mask layer  304 . The removed portions of photoresist layer  305  may be removed by any known methods in the art, including, but not limited to, developing photoresist layer  305  with a light source and wet etching the portions to be removed. 
         [0022]      FIG. 2C  depicts removing portions of hard mask layer  304  to form hard caps  311   a,    311   b,  and  311   c.  A reactive ion etching (RIE) process may be used to etch exposed surfaces  304   a,    304   b,    304   c,  and  304   d  of hard mask layer  340  ( FIG. 2B ), while hard caps  311   a,    311   b,  and  311   c  are protected by photoresist sections  305   a,    305   b,  and  305   c  ( FIG. 2B ). Once hard caps  311   a,    311   b,  and  311   c  are formed, photoresist sections  305   a,    305   b,  and  305   c  are removed. 
         [0023]      FIG. 2D-2E  depicts forming gates  310   a,    310   b,  and  310   c  by removing excess material from sacrificial gate layer  303  to form sacrificial gates  312   a - 312   c  (seen in  FIG. 2D ) and dielectric layer  302  to form dielectric layers  313   a - 313   c  ( FIG. 2E ). Material may be removed from sacrificial gate layer  303  and dielectric layer  302  using any method known in the art including, for example, a RIE process. As depicted in  FIG. 2E , gates  310   a - 310   c  include hard caps  311   a - 311   c,  sacrificial gates  312   a - 312   c,  and dielectric layers  313   a - 313   c,  respectively. 
         [0024]    Referring to  FIGS. 2F-2G , spacers  321   a - 321   c  ( FIG. 2G ) are formed on gates  310   a - 310   c.    FIG. 3F  depicts the deposition of a spacer material layer  320  on the surface of each gate  310   a - 310   c  and the exposed top surface of substrate  301 . Spacer material layer may be made of, for example, silicon nitride or silicon carbon nitride, and may be 50-400 Å thick, preferably 80-200 Å.  FIG. 2G  then depicts removing material from spacer material layer  320 , using any known method in the art including, for example, a RIE process, to form spacers  321   a - 321   c  on gates  310   a - 310   c,  respectively. For the sake of illustrative simplicity, only spacer on each gate is shown. However, some embodiments may include more than one set of spacers. 
         [0025]    Referring to  FIGS. 2H-2I , source/drain regions are formed between each gate  310   a - 310   c.  The depicted embodiment includes raised source/drain regions. However other embodiments may include other types of source/drain regions. As depicted in  FIG. 2H , source/drain recesses  330   a - 330   d  may be formed in substrate  301  by any known method in the art, including, for example, an etch process using HBr-containing plasma. As depicted in  FIG. 2I , source/drain regions  331   a - 331   d  may be formed by epitaxial growth of source/drain material in the respective source/drain recess  330   a - 330   d  ( FIG. 3H ). Possible source/drain materials include silicon, silicon carbide, and silicon-germanium. In some embodiments, source/drain regions  331   a - 331   d  may be doped. 
         [0026]    Referring to  FIG. 2J , a Middle of Line (MOL) liner  341  may be deposited over the structure of  FIG. 2I  to protect the surfaces of the epitaxially grown source/drain regions  331   a - 331   d.  MOL liner  341  may be made of, for example, silicon nitride, silicon carbide, silicon carbon nitride, and may be 40-150 Å thick, preferably 60-100 Å. Referring to  FIG. 2K , the surface of the structure of  FIG. 2J  may be covered by a MOL insulation layer  342 . Referring to  FIG. 2L , the structure of  FIG. 2K  may be planarized using chemical-mechanical planarization or any other known method in the art to expose sacrificial gates  312   a - 312   c.    
       First Embodiment 
       [0027]      FIGS. 2M-2T  refer to a process to replace sacrificial gate  312   b  of  FIG. 2L  with an insulating material, according to a first embodiment. As depicted in  FIG. 2M , nitride layer  350  and photoresist layer  360  are deposited on the surface of the structure of  FIG. 2J . Nitride layer  350  may be 30-200 Å thick, preferably 50 Å. As depicted in  FIG. 2N , a portion of nitride layer  350  is removed so that sacrificial gate  312   b  is exposed while sacrificial gates  312   a  and  312   c  are still covered by the remaining portions of nitride layer  350 . In the depicted embodiment, the portion of nitride layer  350  may be removed by patterning photoresist layer  360  and transferring the pattern into the nitride layer  350  through any known method in the art, including reactive ion etching, and then removing photoresist layer  360 . As depicted in  FIG. 2O , sacrificial gate  312   b  ( FIG. 2N ) is removed by any known method, including, for example, a RIE process or hydroxide-containing silicon-selective wet etch, to form opening region  370 . As depicted in FIG.  2 P, opening region  370  ( FIG. 20 ) may be filled with an insulating material  380  by any known deposition process. Insulating material  380  may overfill the region  370  so that the top surface of the structure of  FIG. 20  is covered. Insulating material  380  may be made of, for example, silicon oxide or silicon nitride. As depicted in  FIG. 2Q , the structure of  FIG. 2P  may be planarized using chemical-mechanical planarization or any other known method so that sacrificial gates  312   a  and  312   c  are exposed. The remaining insulator material  380  forms dummy gate  381 . 
         [0028]      FIGS. 2R-2T  refer to a process to replace sacrificial gates  312   a  and  312   c  with metal gates. As depicted in  FIG. 2R , sacrificial gates  312   a  and  312   c  ( FIG. 2Q ) are removed by any known method, including, for example, an RIE process or a hydroxide-containing silicon-selective wet etch to form regions  390   a  and  390   b.  As depicted in  FIG. 2S , various metals may then be deposited in regions  390   a  and  390   b.  In some embodiments, dielectric layers  313   a  and  313   c  are removed prior to metal deposition (not shown). The depicted embodiment includes a high-k dielectric layer (not shown), first work-function metal  392 , a second work-function metal  393  and a metal film  394 . High-k dielectric layer may be made of, for example, hafnium oxide or hafnium silicate. First work-function metal  392  may be made of, for example, a combination of titanium nitride and tantalum nitride. Second work-function metal  393  may be made of titanium-aluminum, titanium, or titanium nitride. Metal film  394  may be made of, for example, aluminum, titanium nitride, or tungsten. Other embodiments may include more or less metal layers depending on the application and types of device or devices being formed. The composition of each metal layer may also vary and the process of selecting the material for each metal layer is known in the art. As depicted in  FIG. 2T , the structure of  FIG. 2S  may then be planarized using chemical-mechanical planarization or any other known method to expose dummy gate  381 . The remaining portions of the high-k dielectric layer (not shown), first work-function metal  392 , a second work-function metal  393  and metal film  394  form metal gates  395   a  and  395   b.  The structure is then ready for contact formation and/or fill processes. 
       Second Embodiment 
       [0029]      FIGS. 3A-3H  refer to a process to replace sacrificial gate  312   b  of  FIG. 2L  with an insulating material, according to a first embodiment. As depicted in  FIG. 3A , a photoresist layer  401  is deposited on the top surface of the structure of  FIG. 2L . As depicted in  FIG. 3B , photoresist layer  401  may be patterned to expose sacrificial gate  312   b  while not exposing sacrificial gates  312   a  and  312   c.  As depicted in  FIG. 3C , sacrificial gate  312   b  ( FIG. 3B ) may be removed using an anisotropic etching process to form region  410 . As depicted in  FIG. 3D , photoresist layer  401  ( FIG. 3C ) is removed and region  410  ( FIG. 3C ) may be filled with an insulating material  420  by any known deposition process. Insulating material  420  may overfill the region  410  ( FIG. 3C ) so that the top surface of the structure of  FIG. 3C  is covered. Insulating material  420  may be made of, for example, silicon oxide or silicon nitride. As depicted in  FIG. 3E , the structure of  FIG. 3F  may be planarized using, for example, chemical-mechanical planarization or any other known method so that sacrificial gates  312   a  and  312   c  are exposed. The remaining insulator material  420  forms dummy gate  430 . 
         [0030]      FIGS. 3F-3H  refer to a process to replace sacrificial gates  312   a  and  312   c  with metal gates. As depicted in  FIG. 3F , sacrificial gates  312   a  and  312   c  ( FIG. 2Q ) may be removed by any known method, including, for example, an RIE process or a hydroxide-containing silicon-selective wet etch to form regions  490   a  and  490   b.  As depicted in  FIG. 3G , various metals may be then deposited in regions  490   a  and  490   b.  In some embodiments, dielectric layers  313   a  and  313   c  are removed prior to metal deposition (not shown). The depicted embodiment includes a high-k dielectric layer (not shown), first work-function metal  492 , a second work-function metal  493  and a metal film  494 . The high-k dielectric layer may be made of, for example, hafnium oxide or hafnium silicate. First work-function metal  492  may be made of, for example, a combination of titanium nitride and tantalum nitride. Second work-function metal  493  may be made of titanium-aluminum, titanium, or titanium nitride. Metal film  494  may be made of, for example, aluminum, titanium nitride, or tungsten. Other embodiments may include more or less metal layers depending on the application and types of device or devices being formed. The composition of each metal layer may also vary and the process of selecting the material for each metal layer is known in the art. As depicted in  FIG. 3H , the structure of  FIG. 3G  may be then planarized using, for example, chemical-mechanical planarization or any other known method to expose dummy gate  430 . The remaining portions of the high-k dielectric layer (not shown), first work-function metal  492 , a second work-function metal  493  and metal film  494  form metal gates  495   a  and  495   b.  The structure is then ready for contact formation and/or fill processes. 
       Third Embodiment 
       [0031]      FIGS. 4A-4E  refer to a process to replace sacrificial gates  312   a  and  312   c  of  FIG. 2L  with metal gates while leaving sacrificial gate  312   b  in place, according to a third embodiment of the present invention. As depicted in  FIG. 4A , hard mask layer  510  and photoresist layer  520  are deposited on the surface of the structure of  FIG. 2L . hard mask layer  510  may be made of nitride and be 30-200 Å thick, preferably 50 Å. As depicted in  FIG. 4B , a portion of hard mask layer  510  is removed so that sacrificial gates  312   a  and  312   c  are exposed while sacrificial gate  312   b  is still covered by the remaining portions of hard mask layer  510 . In the depicted embodiment, the portion of hard mask layer  510  may be removed by patterning the photoresist layer  520  and transferring the pattern into the hard mask layer  510  through any known method in the art, including reactive ion etching. 
         [0032]    As depicted in  FIG. 4C , photoresist layer  520  may be removed and sacrificial gates  312   a  and  312   c  (seen in  FIG. 4B ) are removed by any known method, including, for example, an RIE process or a wet etch selective to the material of the sacrificial gates, to form regions  530   a  and  530   b.  As depicted in  FIG. 4D , various metals may then be deposited in regions  530   a  and  530   b.  In some embodiments, dielectric layers  313   a  and  313   c  are removed prior to metal deposition (not shown). The depicted embodiment includes a high-k dielectric layer (not shown), first work-function metal  542 , a second work-function metal  543  and a metal film  544 . The high-k dielectric layer may be made of, for example, hafnium oxide or hafnium silicate. First work-function metal  542  may be made of, for example, a combination of titanium nitride and tantalum nitride. Second work-function metal  543  may be made of titanium-aluminum, titanium, or titanium nitride. Metal film  544  may be made of, for example, aluminum, titanium nitride, or tungsten. Other embodiments may include more or less metal layers depending on the application and types of device or devices being formed. The composition of each metal layer may also vary and the process of selecting the material for each metal layer is known in the art. As depicted in  FIG. 4E , the structure of  FIG. 4D  may then be planarized using chemical-mechanical planarization or any other known method to expose sacrificial gate  312   b,  which will operate as a dummy gate. The remaining portions of the high-k dielectric layer (not shown), first work-function metal  592 , a second work-function metal  593  and metal film  594  form metal gates  595   a  and  595   b.  In some embodiments, sacrificial gate layer  303  may be made of an insulating material so that sacrificial gate  312   b  can better insulate source/drain region  331   b  from source/drain region  331   c.  The structure is then ready for contact formation and/or fill processes.