Abstract:
Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation of U.S. patent application Ser. No. 14/633,080 filed on Feb. 26, 2015, which is a divisional of U.S. patent application Ser. No. 12/002,539, filed on Dec. 17, 2007, now U.S. Pat. No. 8,989,214, which issued on Mar. 24, 2015, each of which are hereby incorporated by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    This invention relates to integrated circuit devices, and more particularly to circuitry on an integrated circuit that can be used to receive a serial data signal at very high bit rates (e.g., in the range of about 10 gigabits per second (10 Gbps or 10G) and higher). 
         [0003]    Industry standards have been developed that call for transmission of serial data signals between relatively closely spaced integrated circuits (“chips”) in a system. One typical application is the so-called 10 Gigabit Small Form Factor Pluggable module. The whole module specification for this standard is known as XFP, and the interface specification for this standard is known as XFI. This module supports telecommunication applications such as SONET OC-192 and G.709 “OUT-2,” and data communication applications such as 10 Gb/s Ethernet and 10 Gb/s Fibre Channel. The serial link in this standard includes a connector and a pair of printed circuit board (“PCB”) traces of less than 200 mm. The channel attenuation is about 6 dB at 5.5 GHz. Providing enough equalization and, at the same time, supporting such high data rates (i.e., in the range of about 10 Gbps and higher) in the circuitry that receives such a signal is a very challenging technical task. 
         [0004]    Another challenging task is to provide good and efficient conversion of data from the serial form in which it is received from a channel of the type described above to a parallel form in which it can be more easily handled by circuitry downstream from the receiver. A related problem is the reverse process on the transmitter side (i.e., converting parallel data to serial form for extremely high-speed serial output). 
       SUMMARY OF THE INVENTION 
       [0005]    In accordance with one possible aspect of the invention, a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gbps or higher) is received by two-stage, continuous-time, linear equalizer circuitry having only two serially connected stages. Certain parameters of these stages (e.g., their DC gain, the location in terms of frequency of a frequency response zero, and/or the location in terms of frequency of a frequency response pole) may be variable (e.g., programmably selectable or controllable). 
         [0006]    In accordance with another possible aspect of the invention, the equalizer output signal may be processed by half-rate, bang-bang, phase detector circuitry. This phase detector circuitry partly deserializes or demultiplexes the incoming data by converting successive pairs of serial data bits to successive parallel-form bit pairs. Further multi-stage demultiplexer circuitry may be provided for demultiplexing successive groups of the parallel-form bit pairs to successive blocks of much larger numbers of parallel bits (e.g., 64 bits per block). 
         [0007]    Still another possible aspect of the invention relates to multi-stage multiplexer circuitry for going in the opposite direction, i.e., converting successive relatively large blocks of parallel data bits to a high-speed serial data bit stream. 
         [0008]    Further features of the invention, its nature, and various advantages will be more apparent from the accompanying drawings and the following detailed description. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]      FIG. 1  is a simplified schematic block diagram of illustrative circuitry in accordance with the invention. 
           [0010]      FIG. 2  is a simplified schematic block diagram of further illustrative circuitry in accordance with the invention. 
           [0011]      FIG. 3  is a simplified schematic block diagram of still further illustrative circuitry in accordance with the invention. 
           [0012]      FIG. 4  is a simplified diagram that illustrates the flow of some representative data through the  FIG. 3  circuitry. 
           [0013]      FIG. 5  is a simplified schematic block diagram of still more illustrative circuitry in accordance with the invention. 
           [0014]      FIG. 6  is a simplified schematic block diagram providing additional detail as to how certain aspects of the  FIG. 1  circuitry may be constructed. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    An illustrative embodiment of equalizer circuitry  20  for use in high-speed serial data signal receiver circuitry  10  in accordance with the invention is shown in  FIG. 1 . Again, the 10G receiver equalizer  20  targets chip-to-chip serial link applications such as XFP/XFI. The function of equalizer  20  is to reduce the demands on the phase detector in clock and data recovery (“CDR”) circuitry that is also part of receiver  10 . The phase detector circuitry (see  FIG. 2  for an illustrative embodiment in accordance with the invention) needs to convert the data into digital signal levels without error. 
         [0016]    In accordance with the present invention, equalizer  20  is a two-stage, continuous-time, linear (CTL) equalizer. This architecture is relatively simple (i.e., only two stages  30   a  and  30   b ), and it has relatively small area and low power consumption. Equalizer  20  has five poles and two zeros. A first pole is at the differential inputs inp and inn to first stage  30   a . (Inputs inp and inn are, of course, the high-speed serial data signal that has been received from a transmitting device (another chip, not shown) via a communication link (also not shown).) A second pole is at the differential inputs to second stage  30   b . A third pole is at the differential outputs outp and outn of second stage  30   b . A fourth pole (the location of which is preferably variable (e.g., programmably variable or selectable)) is Wp of first stage  30   a . A fifth pole (the location of which is again preferably variable (e.g., programmably variable or selectable)) is Wp of second stage  30   b . A first zero (the location of which is preferably variable (e.g., programmably variable or selectable)) is Wz of first stage  30   a . A second zero (the location of which is also preferably variable (e.g., programmably variable or selectable)) is Wz of second stage  30   b . (“Location” in the preceding sentences means position of Wp or Wz in terms of frequency along the frequency axes shown in  FIG. 1 ). 
         [0017]    In  FIG. 1  the symbol for each of stages  30   a  and  30   b  contains a diagram showing the (parameterized) frequency response of that stage. The depicted frequency response parameters are DC gain, AC gain, zero location Wz, pole location Wp, and upward slope of the start of the equalizing region (i.e., the region of AC gain between Wz and Wp). In addition to Wz and Wp for each stage  30  being preferably variable, the amount of DC gain of each stage  30  is also preferably variable (e.g., programmably variable or selectable). The slope and AC gain parameters of each stage  30  may not be independently variable, but may depend on other factors such as the position of the zero (Wz) of that stage. 
         [0018]    Equalizer  20  has only two stages  30   a  and  30   b  because it is intended for operation in a relatively narrow frequency band (e.g., to support narrow-band 10G operation). In the type of chip-to-chip (e.g., XFP/XFI) operation that equalizer  20  is designed to support there is less loss than in other types of applications such as those involving a backplane communication link between the transmitting device and the receiving device. In such backplane applications (which may operate, for example, at 6 Gbps) there can be much greater loss and therefore a need for more than two stages in the receiver equalizer. More than two receiver equalizer stages are undesirable in the type of relatively low-loss, chip-to-chip application of interest in connection with the present invention because more than two equalizer stages tend to amplify noise two much. Overall, equalizer  20  may typically provide up to 6 dB gain boost at 5.5 GHz to compensate for the signal across the channel from the transmitting device (not shown) to receiver  10 . Although the intended range of operation of equalizer  20  is (as noted above) relatively narrow around 10 Gbps, the circuitry can also support somewhat higher frequencies (e.g., up to about 11.3 Gbps). 
         [0019]    Downstream from equalizer  20  in receiver circuitry  10  is a phase detector, which can be constructed as shown at  40  in  FIG. 2  in accordance with further aspects of the invention. The differential input signals inp and inn to phase detector  40  in  FIG. 2  are the differential output signals outp and outn in  FIG. 1 . The phase detector is an important high-speed block in CDR circuitry that forms part of a high-speed serial data signal receiver. Phase detector  40  takes the output from equalizer  20  and coverts it to the binary output (Dodd and Deven). Phase detector  40  also compares the phase differences between (1) a recovered clock signal from a voltage-controlled oscillator (“VCO”) in the CDR circuitry and (2) the equalized input data. The detected phase differences (lead and lag) help the VCO to synchronize the embedded clock information in the input data signal. 
         [0020]    To accommodate the high data rate, 10G phase detector  40  uses a half-rate, bang-bang structure. This structure includes four, binary, high-speed comparators or samplers  42   a - d . Each of samplers  42  is driven by a respective one of four quadrature clocks from the above-mentioned VCO. In particular, sampler  42   a  is driven by the clock signal having relative phase 0°; sampler  42   b  is driven by the clock signal having relative phase 90°; sampler  42   c  is driven by the clock signal having relative phase 270°; and sampler  42   d  is driven by the clock signal having relative phase 180°. It will thus be seen that the quadrature clock signals have phases that are equally distributed or spaced across one complete clock cycle (360°). Each sampler  42  samples the differential data signals that it receives in synchronism with the rising edge in the clock signal applied to it. If when such a sample is taken by a sampler  42 , the plus input to that sampler has higher voltage than the minus input, then the sampler outputs a binary 1 signal. On the other hand, if when such a sample is taken by a sampler  42 , the plus input to that sampler has lower voltage than the minus input, then the sampler outputs a binary 0 signal. Note that the frequency of the clock signals is half the serial data rate (i.e., one complete cycle of the clock signals occupies the same amount of time as two successive unit intervals (data bit durations) of the high-speed serial data input signal). Sampler  42   a  should therefore be sampling near the middle of successive odd-numbered bits in the serial data input signal, while sampler  42   c  should be sampling near the middle of successive even-numbered bits in the serial data input signal. Sampler  42   a  should accordingly be able to produce the Dodd output signal (i.e., a binary data output signal indicative of the odd-numbered data bits in the serial data input signal), while sampler  43   c  should be able to produce the Deven output signal (i.e., a binary data output signal indicative of the even-numbered data bits in the serial data input signal). 
         [0021]    Logic block  44  receives the output signals of all four samplers  42   a - d  to generate signals (lead and lag) indicative of how close to the centers of the odd and even bits samplers  42   a  and  42   c  are in fact sampling. For example, if samplers  42   a  and  42   c  are sampling earlier than the centers of the odd and even bits, then the outputs of samplers  42   a  and  42   b  will always be the same (because both of these samplers are sampling in the same unit interval of the serial data input signal), and the outputs of samplers  42   c  and  42   d  will also always be the same. Logic block  44  can detect this condition and can output a pulse on its “lead” output lead to indicate that the VCO clock signals are leading the phase that they should have for optimal sampling of the serial data input signal. Such a “lead” output pulse can be used to cause the VCO to slow down slightly in terms of frequency to improve the phasing of the quadrature clock signals produced by the VCO. Conversely, if samplers  42   a  and  42   c  are sampling the serial data input signal later than the centers of data bits in that signal, then the outputs of samplers  42   a  and  42   b  will frequently be different from one another (because these two samplers are sampling in two successive unit intervals in the incoming serial data signal), but the outputs of samplers  42   b  and  42   c  will always be the same. Similar behavior will be found in comparisons of the outputs of samplers  42   c  and  42   d  (frequently different) and  42   d  and  42   a  (always the same). Logic block  44  can detect this condition and can output a pulse on its “lag” output lead to indicate that the VCO clock signals are lagging the phase that they should have for optimal sampling of the serial data signal. Such a “lag” output pulse can be used to cause the VCO to speed up slightly in terms of frequency to improve the phasing of the quadrature clock signals produced by the VCO. 
         [0022]    Like equalizer  20 , the intended range of operation of phase detector  40  is around 10 Gbps, but it can also support somewhat higher frequencies (e.g., up to about 11.3 Gbps). 
         [0023]    Each high-speed comparator  42  in phase detector  40  preferably has built-in offset cancellation circuitry. This offset cancellation circuitry may be set by means of a calibration operation that is performed prior to normal operation of the circuitry to process an actual serial data signal. This calibration operation preferably gives each comparator  42  a threshold of 0 volts. Thereafter, each comparator looks for a positive difference between the plus and minus inputs to that comparator, and produces a binary 1 output when that difference is positive (i.e., greater than the 0 volt threshold that has been established for that comparator). 
         [0024]    Recapitulating some of the benefits and advantages of the foregoing, programmable zeros Wz in the receiver equalizer  20  boost the receiver gain up to about 6 dB at 5.5 GHz. The CTL equalizer structure  20  has low power and small area. Both the equalizer  20  and the phase detector  40  support data rates up to about 11.3 Gbps. Offset cancellation within phase detector  40  increases the 10G receiver input sensitivity. 
         [0025]    We turn now to possible de-serializer (and converse serializer) aspects of the invention. 
         [0026]    As has been mentioned, 10 Gbps electrical high-speed serial (“HSS”) transceivers are desired in many applications such as OC192SONET/SDH, 10 Gbit Ethernet, Optical Transport Networks, and/or systems with forward error correction, etc. While the HSS link (e.g., as shown in  FIGS. 1 and 2  herein) provides very high throughputs at the chip pin point, other circuitry that needs to use (or supply) these signals (e.g., the remaining circuitry of a programmable microcontroller, a field-programmable gate array (“FPGA”), or core logic of some other type of integrated circuit device that includes the HSS circuitry) may still process data in parallel at lower clock rates for better signal integrity and time margin. Thus the HSS receiver like  10  herein (or a comparable HSS transmitter like that shown, for example, in Wong et al. U.S. patent application Ser. No. 12/002,540) filed Dec. 17, 2007 needs to convert the serial data to parallel data (or to do the opposite on the transmitter side). The present disclosure provides 1:64 deserializer circuitry and 64:1 serializer circuitry that can be used for these purposes. 
         [0027]    An illustrative embodiment of deserializer circuitry  100  in accordance with the invention is shown in  FIG. 3 . This circuitry has a first stage that includes two 1:4 demultiplexers  110   a  and  110   b , and a second stage that includes eight 1:8 demultiplexers  120   a - h . Demultiplexer  110   a  receives the Deven output signal of circuitry  40 . In parallel with this, demultiplexer  110   b  receives the Dodd output signal of circuitry  40 . Demultiplexers  110   a - b  also receive a half-rate clock signal having (1) the same frequency as any of the phase 0 to phase 270 signals in  FIG. 2 , and (2) phase that is appropriate for allowing demultiplexers  110   a - 110   b  to latch in successive pairs of valid Deven and Dodd signals as will be described in more detail below. The output side of this first stage of the deserializer is clocked by a clock signal having frequency divided by 4 (by frequency divider  112 ) from the half-rate frequency used to clock in the input side of this deserializer stage. 
         [0028]    Demultiplexers  110   a - b  produce eight parallel output signals, each of which is applied to a respective one of the eight demultiplexers  120   a - h . The input side of demultiplexers  120   a - h  is clocked by a signal having the same frequency as is used to clock the output side of demultiplexers  110   a - b . Demultiplexers  120   a - h  eventually accumulate 64 bits of valid data and output that data in parallel on the Dout leads. The output side of this second stage of the deserializer is clocked by a clock signal having frequency divided by 8 (by frequency divider  122 ) from the frequency used to clock the input side of this deserializer stage. This clock signal (CLK_DIVRX) can also be applied to downstream circuitry to allow that circuitry to latch in valid Dout signals. 
         [0029]      FIG. 4  illustrates how data may flow through demultiplexers  110   a - b  and  120   a - h . In a first period of a half-rate clock (i.e., half the incoming serial bit rate), the first two serial bits to arrive (arbitrarily referred to as bits  0  and  1 ) are stored in demultiplexers  110   a  and  110   b , respectively. In a second period of the above-mentioned half-rate clock, the next two serial bits to arrive (i.e., bits  2  and  3 ) are stored in demultiplexers  110   a  and  110   b , respectively. In a third period of the half-rate clock, the next two bits to arrive serially (i.e., bits  4  and  5 ) are added to what is stored in demultiplexers  110   a  and  110   b , respectively. In a fourth half-rate clock period, bits  6  and  7  are added to what is stored in demultiplexers  110   a  and  110   b , respectively. The contents of demultiplexers  110  are then transferred to demultiplexers  120   a - h . In particular, bit  0  is transferred from demultiplexer  110   a  to demultiplexer  120   a , where bit  0  is now stored; bit  1  goes from demultiplexer  110   b  to demultiplexer  120   b , where bit  1  is now stored; bit  2  goes from  110   a  to  120   c , where bit  2  is now stored; bit  3  goes from  110   b  to  120   d , where bit  3  is now stored; and so on. In successive periods of the half-rate clock, multiplexers  110   a  and  b  are again filled with data from circuitry  40 . Then this data is again transferred to demultiplexers  120   a - h  so that  120   a  stores bits  0  and  8 ,  120   b  stores bits  1  and  9 ,  120   c  stores bits  2  and  10 ,  120   d  stores bits  3  and  11 , and so on. 
         [0030]    The above-described process continues until demultiplexers  120   a - h  are full (e.g.,  120   a  contains bits  0 ,  8 ,  16 ,  24 ,  32 ,  40 ,  48 , and  56 ). All eight of demultiplexers  120   a - h  then output all of their data in parallel on leads Dout. This parallel data can go to downstream circuitry which can process it at much lower data rates than the serial data rate. For example, this downstream circuitry can process this parallel data using a parallel data clock (like CLK_DIVRX) that is one-sixty-fourth (1/64) the incoming serial bit rate. This greatly facilitates the design, construction, and operation of the downstream circuitry (sometimes referred to as utilization circuitry). 
         [0031]    It will be noted that even within demultiplexer  100 , the construction of that circuitry helps it operate at clock signal frequencies that are lower than the serial bit rate. For example, each of demultiplexers  110   a  and  110   b  only has to receive data at one-half the serial bit rate. This is so because upstream circuitry  40  already puts two serially received bits in parallel (effectively cutting the data rate to one-half the serial bit rate). Demultiplexers  110   a  and  110   b  collectively output eight bits in parallel. Therefore their output data rate (and the input data rate of demultiplexers  120   a - h ) is one-eighth the serial bit rate. And of course the output data rate of demultiplexers  120   a - h  is one-sixty-fourth the serial bit rate. 
         [0032]    Illustrative multiplexer circuitry  200  in accordance with another possible aspect of the invention is shown in  FIG. 5 . The circuitry upstream from this circuitry can be part of the circuitry that is downstream from the circuitry shown in  FIG. 3  herein. The circuitry downstream from the  FIG. 5  circuitry can be transmitter driver circuitry (e.g., like that shown in the above-mentioned Wong et al. reference). 
         [0033]    Multiplexer  210  can receive 64 bits of data in parallel via the DATA_IN[63:0] leads. Multiplexer  210  also receives a clock signal having frequency and phase that allows multiplexer  210  to latch each successive block of  64  valid data bits that it receives. 
         [0034]    Multiplexer  210  outputs the 64 data bits that it has received in eight blocks of eight parallel bits each. For example, if the bits that multiplexer  210  has received are arbitrarily numbered 0-63, then bits  0 - 7  are output first; then bits  8 - 15  are output; then bits  16 - 23  are output; and so on. These 8-bit blocks are output at eight times the frequency that the 64-bit blocks are applied to multiplexer  210 . 
         [0035]    The even-numbered bits in each 8-bit block output by multiplexer  210  are all applied in parallel to multiplexer  220   a . The odd-numbered bits in each such 8-bit block are all applied in parallel to multiplexer  220   b . Thus, for example, from the 8-bit block that includes bits  0 - 7 , bits  0 ,  2 ,  4 , and  6  are all applied to multiplexer  220   a , and bits  1 ,  3 ,  5 , and  7  are all applied to multiplexer  220   b.    
         [0036]    Each of multiplexers  220   a  and  220   b  outputs the four bits that it receives in parallel one after another in series. Note, however that the two series output by multiplexers  220   a  and  220   b  are synchronized with one another so that they collectively constitute two data streams that are in parallel with one another. These two data streams are applied in parallel to the input side of multiplexer  230 . Because the successive outputs of multiplexer  220   a  are all even bits, while the successive outputs of multiplexer  220   b  are all odd bits, multiplexer  230  receives one even bit and one odd bit in each cycle of operation of its input side. 
         [0037]    Multiplexer  230  outputs each pair of bits (which it has received in parallel) one after another in series. Accordingly, multiplexer  230  produces the final serial data output stream TX_DATA. 
         [0038]    Clocking of the output side of multiplexer  230  is typically at the serial bit rate (e.g., about 10 Gbps or higher). Clocking of the input side of multiplexer  230  (and the output side of multiplexers  220 ) can be at one-half the serial bit rate. Clocking of the input side of multiplexers  220  (and the output side of multiplexer  210 ) can be at one-eighth the serial bit rate. Clocking of the input side of multiplexer  210  can be at one-sixty-fourth the serial bit rate. Some or all of the necessary clock signals can be provided by appropriate multiplication of the frequency of the CLK input to multiplexer  200 . Alternatively or in addition, some or all of the necessary clock signals can be provided by appropriately dividing the frequency of a serial bit rate clock signal (e.g., supplied from a reference clock signal source  240 ). For completeness, an example in which all of the clock signals (except for the input side of mux  210 ) are provided from such a high-speed reference clock signal source  240  is shown in  FIG. 5 . In this example, source  240  clocks the output side of mux  230 . Frequency divider  242  divides the reference clock frequency by 2 to clock the input side of mux  230  and the output side of muxes  220 . Frequency divider  244  divides the element  242  output frequency by 4 to clock the input side of muxes  220  and the output side of mux  210 . 
         [0039]    Note that the multiplexer structure shown in  FIG. 5  allows the upstream circuitry to operate at relatively low clock rates (e.g., one-sixty-fourth the serial output bit rate). The  FIG. 5  circuitry can accept this data at such a relatively low clock rate, and can then convert it to serial data having a very high serial data rate. In addition, the  FIG. 5  circuitry has the advantage of not needing to work with the very high serial data rate until the final, relatively small 2:1 multiplexer  230  is reached. Only the output side of this relatively small multiplexer  230  has to operate at the very high serial bit rate. The input side of mux  230  operates at one-half the serial bit rate, and the upstream stages of multiplexer  200  operate at that reduced rate or even further reduced rates. Another advantage of the circuitry of  FIG. 5  is that two 4:1 muxes  220   a  and  220   b  are provided and operate in parallel. The input clocking and phasing of both of these components  220  can be the same. The output clocking and phasing of both of these components can also be the same. In addition, the output clocking of these relatively large (as compared to mux  230 ) multiplexers  220  can be at lower frequency than the final serial output data bit rate. 
         [0040]      FIG. 6  recapitulates, amplifies, and depicts the point made earlier that the values of variable parameters of equalizer stage  30   a  and/or  30   b  (e.g., the DC gain, the location in frequency of the variable zero Wz, and/or the location in frequency of the variable pole Wp of either or both of those stages) can be programmably controlled. Thus  FIG. 6  shows that any or all of these parameters can be controlled by programmable memory  300 , which can be part of the integrated circuit device that includes the other circuitry such as 10 that is shown and described herein. For example, this integrated circuit may be or may include programmable circuitry such as a programmable microcontroller, a programmable logic device (“PLD”), etc. In such cases, memory  300  may be part of the programmable configuration memory of the programmable integrated circuit device. 
         [0041]    It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.