Abstract:
An example inverter circuit assembly includes at least one first transistor device and at least one second transistor device. The second transistor device comprises a silicon carbide junction gate field-effect transistor. The at least one second transistor device is an inner transistor device relative to the at least one first transistor device.

Description:
BACKGROUND 
       [0001]    This disclosure relates generally to inverters and, more particularly, to inverters incorporating a normally-on transistor, such as a normally-on junction gate field-effect transistor (JFET). 
         [0002]    Inverters are used in a wide variety of applications to change direct current to alternating current. Some inverters provide variable frequency alternating current power to loads, such as alternating current motors on aircraft. 
         [0003]    There are various types of inverters, including two-level inverters, which typically synthesize only two voltage levels, and neutral point clamped inverters, which are able to synthesize three voltage levels. Neutral point clamped inverters produce less distorted voltage waveforms than two-level inverters, as is known. 
         [0004]    Neutral point clamped inverters commonly use normally-off devices for all transistors. These normally-off devices limit a current shoot-through upon loss of gate drive control power but in some instances have higher on-state losses than comparable normally-on devices. Normally-on devices do not limit current shoot-through. 
       SUMMARY 
       [0005]    An example inverter circuit assembly includes at least one first transistor device and at least one second transistor device. The second transistor device comprises a normally-on silicon carbide junction gate field-effect transistor. The at least one second transistor device is an inner transistor device relative to the at least one first transistor device. 
         [0006]    An example inverter system includes an inverter having at least one inner transistor device and at least one outer transistor device. The at least one inner transistor device comprises a normally-on transistor. 
         [0007]    An example method of converting DC power to AC power includes commutating the AC load current through combinations of normally-on and normally-off transistor devices of an inverter circuit. 
     
    
     
       DESCRIPTION OF THE FIGURES 
         [0008]    The various features and advantages of the disclosed examples will become apparent to those skilled in the art from the detailed description. The figures that accompany the detailed description can be briefly described as follows: 
           [0009]      FIG. 1  shows an example inverter circuit. 
           [0010]      FIG. 2  shows a high level schematic view of a system incorporating the inverter circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    Referring to  FIGS. 1 and 2 , an example inverter circuit  10  is a neutral point clamped inverter circuit. Direct current (DC) to alternating current (AC) inverters are commonly used to provide variable frequency and voltage AC power to many loads, particularly AC motors. The example inverter circuit  10  is one leg of a three-phase inverter. 
         [0012]    The example inverter circuit  10  forms a portion of an inverter system  22 . A DC source  20  sends power through the inverter system  22  to an AC motor  24 . The inverter circuit  10  provides AC power to loads on an aircraft in this example. 
         [0013]    The example inverter circuit  10  includes transistor devices Q 1  to Q 4 . The transistor devices Q 1  and Q 4  are in closer proximity to DC terminals +DC and −DC than the transistor devices Q 2  and Q 3 . The transistor devices Q 2  and Q 3  are in closer proximity to the AC terminal  0  than the transistor devices Q 1  and Q 4 . The transistor devices Q 1  and Q 4  are considered outer devices, and the transistor devices Q 2  and Q 3  are considered inner or middle devices. 
         [0014]    The middle two transistor devices Q 2  and Q 3  of the example inverter circuit  10  are normally-on and the outer two transistor devices are normally-off. Further, in this example, the middle two transistor devices are depletion mode Silicon Carbide junction gate field-effect transistors (JFETs), and the outer two transistor devices Q 1  and Q 4  are Silicon Carbide metal-oxide-semiconductor field-effect transistors (MOSFETs). In other examples, the outer transistor devices Q 1  and Q 4  are other types of MOSFETs, enhancement mode JFETs, or insulated gate bipolar transistors (IGBTs). 
         [0015]    The example inverter circuit  10  also includes diodes D 1  to D 6 . The diodes D 1  to D 6  of the example inverter circuit  10  are Silicon Carbide Schottky diodes. 
         [0016]    The example inverter circuit has relatively low conduction losses through Q 2  and Q 3  due to the low specific on-resistance of Silicon Carbide depletion mode JFETs, which is lower than the specific on-resistance of Silicon Carbide MOSFETs, and Silicon Carbide enhancement mode (normally-off) JFETs. 
         [0017]    The example inverter circuit  10  has an output phase terminal  0  that is configured to be clamped to a direct current link center point when gate drive control power is not applied (lost) to all the transistor devices Q 1  to Q 4 . Since normally-off devices are used for Q 1  and Q 4 , there is no inherent shoot-through condition upon loss of gate drive control power to all the transistor devices Q 1  to Q 4 . 
         [0018]    The inverter circuit  10  synthesizes three node voltages (“levels”) at the phase output. A two-level inverter, by contrast, is only able to synthesize two voltage levels. Consequently, the three-level neutral point clamped inverter is able to produce a less distorted waveform than the two-level inverter of the prior art. 
         [0019]    Features of the disclosed examples include using silicon carbide normally-on (depletion mode) JFETs for Q 2  and Q 3 , which reduces conduction losses for a given chip area while maintaining insusceptibility to shoot-through faults. Another feature of the disclosed examples includes the ability to clamp the output voltage to a DC link center point when no gate drive voltages are applied to all the transistor devices Q 1  to Q 4 . This zero output voltage property may be desirable for powering certain loads. 
         [0020]    The preceding description is exemplary rather than limiting in nature. Variations and modifications to the disclosed examples may become apparent to those skilled in the art that do not necessarily depart from the essence of this disclosure. Thus, the scope of legal protection given to this disclosure can only be determined by studying the following claims.