Abstract:
A relaxation current controlled oscillator (CCO) is provided by forming an integrator out of a transconductance amplifier and a capacitor. The output of the integrator is fed to comparators which in turn feed a bistable circuit. The outputs of the bistable circuit control either the polarity of the input signals to the transconductance amplifier or the polarity of the input signals to the comparators. Switches, controlled by the bistable circuit, in turn control the polarity of the input signals. The feedback path created by the transconductance amplifier, comparators, flip-flops, and switches produces continuous oscillations. A DC current input adjusts the g m  of the transconductance amplifier allowing the oscillation frequency of the CCO to be adjusted. Several embodiments of CCOs are described which are fully compatible with PLLs with automatic time-constant or bandwidth tuning of a gm-C filter.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to relaxation oscillators for use in PLL circuits and in particular to current controlled oscillators without start-up or amplitude control problems used in PLLs for automatic time-constant or bandwidth tuning of g m -C filters. 
     2. Description of the Related Art 
     The design of a two-integrator based sinusoidal quadrature oscillator, which is widely used in phase locked loop (PLL) bandwidth tuning of g m -C filters (where g m -C stands for transconductance-Capacitor), is associated with amplitude control/start-up problems. See Khen Sang Tan and Paul R. Gray, “Fully Integrated Analog Filters Using Bipolar-JFET Technology”, IEEE Journal of Solid-State Circuits, vol. SC-2, pp. 814-821, December 1978, and John M. Khoury, “Design of a 15 MHz CMOS Continuous-Time Filter with On-Chip Tuning”, IEEE Journal of Solid-State Circuits vol. SC-26, no. 12, pp. 1988-1997, December 1991. 
     The above-mentioned PLL-based bandwidth-tuning scheme is shown in FIG.  1  and the two-integrator based quadrature sinusoidal current controlled oscillator (CCO) based on the traditional concept is shown in FIG.  2 . The PLL-based bandwidth-tuning scheme  10  of FIG. 1 is comprised of phase detector (PD)  12 , a charge pump (CP)  14 , a loop filter (LF)  16 , a voltage to current converter (VIC) 18, and a current controlled oscillator (CCO)  20 . Block  12  receives as input the reference frequency f REF  and from block  20  the feedback input f 0 . Block  12  feeds block  14  which feeds block  16 . The output of block  16  is a voltage which get converted by block  18  to the current I tunc , Signal I tunc  feeds other blocks for tuning (not shown) and block  20 . FIG. 2 is a more detailed diagram of CCO  20  which shows transconductance amplifiers  22  and  24  coupled in series, each with a transconductance of g m . The output OUT  2  of  22  is coupled to the negative input IN 4  of  24 . The output OUT 4  of  24  feeds the positive input IN 2  of  22 . The negative input of  22  and the positive input of  24  are grounded. Blocks  22  and  24  receive equal signals I tune    28  and  29 , respectively. The outputs OUT 2  and OUT 4  are coupled via equal capacitors  26  and  27 , respectively, to ground. This type of sinusoidal oscillators suffers from amplitude control and startup problems 
     U.S. Patents which have some bearing on the present invention are: 
     U.S. Pat. No. 6,201,450 (Shakiba et al) describes a relaxation oscillator which provides a very wide linear range of frequency variation versus control voltage (or current). U.S. Pat. No. 6,111,467 (Luo) discloses a time constant tuning circuit which uses a frequency of a clock to tune the circuit time constant. U.S. Pat. No. 6,084,465 (Dasgupta) describes a time constant tuning circuit in which a reference clock frequency is used to adjust the g m  of a transconductor. U.S. Pat. No. 6,060,957 (Kodmja et al.) teaches a relaxation oscillator with low phase noise particularly applicable to PLLs. U.S. Pat. No. 6,020,792 (Nolan et al.) describes a precision relaxation oscillator with temperature compensation to produce a stable clock frequency. U.S. Pat. No. 5,497,127 presents a voltage controlled oscillator with a wide range of frequencies and which includes a relaxation oscillator. U.S. Pat. No. 5,489,878 (Gilbert) discloses an oscillator which includes two gm/C stages. U.S. Pat. No. 5,418,502 (Ma et al.) teaches the use of an R-C relaxation oscillator where two comparators control the charge/discharge of the capacitor via an SCR. U.S. Pat. No. 5,093,634 (Khoury) shows using a triple input, triple output linear transconductance amplifier as an oscillator by feeding back the output of the amplifier to the input. U.S. Pat. No. 5,070,311 (Nicolai) describes using current sources, selected by a register, to control the charge/discharge of a capacitor and thereby adjusting the frequency of an oscillator. U.S. Pat. No. 4,977,381 (Main) presents a relaxation oscillator where the direction of the current to the capacitor in the oscillator is alternated, based on the state of a bistable circuit. U.S. Pat. No. 4,963,840 (Thommen) is similar to U.S. Pat. No. 4,977,381 above but in addition reduces power consumption. U.S. Pat. No. 4,725,993 (Owen et al.) discloses a low duty cycle relaxation oscillator which periodically gates an ultrasonic frequency relaxation oscillator. U.S. Pat. No. 4,377,790 (Zobel et al.) teaches a relaxation oscillator where a capacitor is charged and discharged between an upper and lower voltage level based on a signal from a comparator. U.S. Pat. No. 4,535,305 (Matsuo et al.) describes a transmission gate relaxation oscillator using a comparator which compares the charge/discharge voltage with a reference voltage. The invention is different from all of the above cited U.S. Patents. 
     The invention below describes several equivalent relaxation CCOs that overcome startup/amplitude control problems of sinusoidal CCOs, are simple to design and totally compatible with modern PLL circuits. 
     SUMMARY OF THE INVENTION 
     It is an object of at least one embodiment of the present invention to provide a circuit and a method for a relaxation current controlled oscillator (CCO) for phase locked loop (PLL)-based time constant tuning of g m -C filters. 
     It is another object of the present invention to provide a CCO which does not have amplitude control problems. 
     It is yet another object of the present invention to provide a CCO which does not have start-up problems. 
     It is still another object of the present invention to provide a CCO which is simple to design and is totally compatible with modem PLL circuits. 
     It is a further object of the present invention is to provide a CCO where there is great flexibility in choosing the reference frequency f REF  or the oscillation frequency f 0 . 
     It is yet a further object of the present invention is to provide a CCO with a truly 50% duty cycle output waveform. 
     It is still a further object of the present invention is to provide a CCO with a non overlapping output waveform. 
     These and many other objects have been achieved by forming a test integrator out of a transconductance amplifier and a capacitor. The output of the integrator is fed to comparators which in turn feed a bistable circuit such as a SR flip flop. The output Q and its inverse QB of the bistable circuit controls either the polarity of the input signals to the transconductance amplifier or the polarity of the input signals to the comparators (when the transconductance amplifier has a differential output). Switches, controlled by the bistable circuit, in turn control the polarity of the input signals. The feedback path created by the transconductance amplifier, comparators, flip-flops, and switches causes continuous oscillation to take place. A DC current input adjusts the g m  of the transconductance amplifier allowing the oscillation frequency of the CCO to be adjusted by varying the DC current input. There is great flexibility in choosing the reference frequency f REF  or the oscillation frequency f 0  by the proper choice of a resistive divider. 
     These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a time-constant Tuning PLL for g m -C filters of the prior art. 
     FIG. 2 is a block diagram of a quadrature sinusoidal oscillator of the prior art. 
     FIG. 3 a  is a schematic of a first preferred embodiment of a CCO for a time-constant tuning PLL of the present invention. 
     FIG. 3 b  is a graph of the input and output waveforms of FIG. 3 a.    
     FIG. 4 a  is a schematic of a second preferred embodiment of a CCO for a time-constant tuning PLL of the present invention. 
     FIG. 4 b  is a graph of the input and output waveforms of FIG. 4 a.    
     FIG. 5 a  is a schematic of a third preferred embodiment of a CCO for a time-constant tuning PLL of the present invention. 
     FIG. 5 b  is a graph of the input and output waveforms of FIG. 5 a.    
     FIG. 6 a  is a schematic of a fourth preferred embodiment of a CCO for a time-constant tuning PLL of the present invention. 
     FIG. 6 b  is a graph of the input and output waveforms of FIG. 6 a.    
     FIG. 7 is a graph of the tuning characteristics of the typical CCO of the preferred embodiment of the present invention. 
     FIG. 8 is a block diagram of the preferred method of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 3 a  shows the schematic of the first preferred embodiment of the inventive relaxation CCO  30 . A test integrator is formed out of the test transconductarnce amplifier  32  (of transconductance g m ) and a capacitor  34  (of capacitance C). The output Veap of the integrator is fed to two comparators  36   a  and  36   b . The outputs of the comparators feed a SR latch  38  with outputs Q and QB. SR latch  38  is not further described here since it is a basic component of digital circuitry and well known. The latch controls the polarity of the input DC voltage (across R B ) to the transconductance amplifier. A switching network comprising switching means S 1 , S 2 , S 3 , and S 4  is coupled across resistor R B  of a resistor string and the plus and minus inputs of transconductance amplifier  32 . The resistor string itself is a series network of resistors with values R A , R C , R B , R C , and R A  coupled between voltage supply V DD  and its return side (typically ground GND). V H  and V L  are nodes along the resistor string which couple to the plus and minus inputs of comparators  36   a  and  36   b , respectively. The output Veap of transconductance amplifier  32  couples to the minus and plus input of comparators  36   a  and  36   h,  respectively, and to capacitor  34 . In addition, current I tune  is applied to transconductance amplifier  32  of FIG. 3 a  as well as all transconductance amplifiers  32  of FIGS. 4 a ,  5   a  (including transconductance amplifier  52 ), and  6   a.    
     If Q is high and QB low (latch set), switching means S 1  and S 4  are open and S 2  and S 3  are closed. If QB is high and Q low (latch reset), switching means S 1  and S 4  are closed with S 2  and S 3  open. The latter state (when the latch is reset) applies the small voltage across R B  at the input to the integrator and as a consequence, its output Vcap rises linearly with time. This continues till Vcap reaches V H  and the upper comparator trips setting the latch (Q is high and QB low). Now S 1 , S 4  opens and S 2 , S 3  closes. This also applies the small voltage across R B  to the input of the integrator, but in the opposite direction. As a result; Vcap now goes down linearly with time till it reaches V L . At this point, the lower comparator trips and resets the latch. Therefore the above two sequences will repeat again and again causing continuous oscillation to take place. FIG. 3 b  displays the waveshapes at nodes Vcap (Curve  31 ), Q, and QB (Curves  32  and  33 , respectively). Note that the graphs of FIGS. 3 b ,  4   b ,  5   b , and  6   b  represent voltages in the vertical axis. 
     Below is the calculation to find the oscillation frequency f 0 .            V   L     =         R   A       ∑   R            V   DD         ,       V   H     =           R   A     +     2        R   C       +     R   B         ∑   R            V   DD         ,                         where Σ R= 2 R   A   +R   C   +R   H   (1) 
     
       
         
           
             
               
                 
                   
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     From (4)            f   0     ≅       1     2      π              g   m     C         ,                          
     if                  R   C       R   B       =   1.07           (   5   )                                
     Also,            f   0     =       1   2            g   m     C         ,                         if  R   C =0  (6) 
     Equation (5) shows that the circuit can be adjusted to have a frequency very nearly equal to that of the traditional two-integrator sinusoidal oscillator. 
     I tune  is the DC current input to adjust the g m  of the transconductance amplifier. This means the oscillation frequency f 0  of the CCO can be adjusted by varying I tune . When this CCO in used in the PLL shown in FIG. 1, we have:                f   REF     =       f   0     =       1     2        (     1   +       2        R   C         R   B         )                g   m     C                 (   7   )                                
     from (7) we have:                  g   m     C     =     2        (     1   +       2        R   C         R   B         )          f   REF               (   8   )                                
     Since R C /R B  is a constant, the g m /C of the test integrator is determined directly by f REF . If all the integrators in a g m -C filter are made identical to the test integrator and if I tune  from the PLL is used to control each transconductor (using current mirroring), then the bandwidth of the filter (determined by g m /C) is also determined by f REF  and can be tuned by it. Equation (8) shows that there is a great flexibility in choosing f REF  or f 0  due to the ratio R C /R B . In the case of the traditional sinusoidal oscillator, the constant multiplier of f REF  in (8) would be fixed at 2π. 
     The transconductance amplifier and the integrator formed by it are referred to as ‘test’ integrators because they are identical to those used in the main filter for which time-constant or bandwidth tuning one wants to do. The problem is to find out the ‘g m ’ of the ones in the main filter. Since this cannot be done directly without affecting the filter performance, an additional integrator, identical to the one in the filter, is used as a ‘test’ element and its ‘g m ’ is found out instead and corrected with a PLL using the inventive circuit. 
     FIG. 4 a  shows a second preferred embodiment of a CCO in the form of CCO  40 . Here differential outputs A (+) and B(−) are used for the transconductor  32 . However, again only one timing capacitor  34  is used. This implementation uses output switching instead of input switching of FIG. 3 a . This helps in getting rid of any delay through the transconductor and, therefore, allows higher frequency of operation. It is to be noted that non-overlapping output waveforms are generated, as shown in FIG. 4 b  Curves  47  and  48 , to avoid discharging of the timing capacitor  34  during switching. Curves  47  and  48  are enlarged sections of Curves  45  and  46 , respectively, to more clearly demonstrate non-overlapping. FIG. 4 b  also shows the waveforms for outputs A and B (Curves  41  and  42 , respectively), the waveform at Vcap and node C (Curves  43  and  44 , respectively), and output waveforms for φ 2  and φ 1  (Curves  45  and  46 , respectively). The resistor string of FIG. 4 a  is the same as that for FIG. 3 a  including connections to transconductor  32 , comparators  36   a  and  36   b , V DD  and ground. A switching network comprising switching means S 1 - 4  is coupled between outputs A and B and nodes Vcap and C. Vcap in turn is coupled to the positive and negative inputs of comparators  36   a  and  36   b , respectively, and via timing capacitor  34  (of capacitance C) to ground. Node C is coupled via resistors R D  to both V DD  and ground. Note also that capacitors Cd are connected at the NOR gates of SR latch  38  to help generate the non-overlap. R D  for FIG. 4 a  is defined as: 
     
       
           R   D   =R   A   +R   C   +R   B /2 
       
     
     Note that the suffix for S 1  to S 4  indicates during which phase the switching means is active, such that: S 1 -φ 2  and S 3 -φ 2  are on when output φ 2  of SR latch  38  is high, and that S 2 -φ 1  and S 4 -φ 1  are on when output φ 1  is high. 
     FIG. 5 a  shows a third preferred embodiment of a CCO in the form of CCO  50 . This implementation uses two differential output transconductors  32  and  52 . This implementation also employs output switching. The resistor string of FIG. 5 a  is the same as that for FIG. 3 a  including connections to transconductor  32 , comparators  36   a  and  36   b , V DD  and ground. A switching network comprising switching means S 1  to S 4  is coupled between outputs A and B of transconductor  32  and node Vcap and outputs C and D of transconductor  52 . More specifically, A is coupled via S 4 -φ 1  to C and via S 1 -φ 2  to Vcap, B is coupled via S 3 -φ 2  to D and via S 2 -φ 1  to Vcap. As in FIG. 4, Vcap is coupled to the positive and negative inputs of comparators  36   a  and  36   b , respectively, and via timing capacitor  34  (of capacitance C) to ground. Outputs C and D are coupled to nodes V L ′ and V H ′, respectively. Nodes V L ′ and V H ′ are part of a second resistive network comprising two resistor strings in parallel having resistors of value R A  and R D  in series between V DD  and ground, respectively, and, similarly, resistors R I)  and R A  in series between V DD  and ground, respectively. R D  is defined as: R D =R A +R B +2R C . Note that the voltages at nodes V H  and V H ′ are identical, so are the voltages at nodes V L  and V L ′. 
     Current from one output of the transconductor ( 32 ) charges the timing capacitor  34  of capacitance C and the other transconductor  52  helps to maintain continuity of the current from the other output of transconductor  32 . The advantage of this implementation is that transconductor  32  outputs A and B do not see voltage jumps when the switching means connect them to the timing capacitor, unlike in the second embodiment of FIG.  4 . This enables higher frequency of operation. Here also, non-overlapping output waveforms are generated. As in FIG. 4 a , capacitances Cd are added to SR latch  38 , which help to generate the non-overlapping waveform. 
     Note that the suffix for S 1  to S 4  indicates during which phase the switching means is active, such that: S 1 -φ 2  and S 3 -φ 2  are on when output φ 2  of SR latch  38  is high, and that S 2 -φ 1  and S 4 -φ 1  are on when output φ 1  is high. 
     FIG. 5 b  shows the waveforms for Vcap (Curve  51 ), A (Curve  52 ), B (Curve  53 ), C (Curve  54 ), D (Curve  55 ), φ 2  (Curve  56 ), and φ 1  (Curve  57 ). Curves  58  and  59  are enlarged sections of Curves  56  and  57  to more clearly demonstrate non-overlapping. 
     FIG. 6 a  shows a fourth preferred embodiment of a CCO in the form of CCO  60 . This is a fully differential implementation employing both input and output switching and four timing capacitors  64   a-d  each of capacitance C. Each timing capacitor is charged to the appropriate reference voltage and applied to the output of transconductor  32  for integration. The integration of a pair of capacitors is conducted while charging of the other pair is carried out. In this case also a non-overlapping output waveform is generated. However, the output frequency is double of the previous embodiments. Being fully differential, this circuit provides a truly 50% duty cycle output waveform as errors due to minor mismatches in the differential transistors balance off. 
     Still referring to FIG. 6 a , the circuit is explained in more detail. Resistive strings R A −R E −R A  and R D −R B −R D  are both coupled between V DD  and a reference potential (typically ground as shown in FIG. 6 a ). The node between R A  and R E  is labelled V H , and the node between R E  and R A  is labelled V L . In the identical switching arrangement as that of FIG. 3 a  for switching means S 1  to S 4 , the high side of R B  couples via S 1 -φ 2  and S 2 -φ 1  to the positive and negative input of transconductor  32 , respectively. The low side of R B  couples via S 3 -φ 1  and S 4 -φ 2  to the positive and negative input of transconductor  32 , respectively. The plus and minus output of transconductor  32  couples to the plus and minus input of dual-output comparator  66 , respectively. The plus and minus outputs of comparator  66  feed SR latch  38 . Coupled between nodes V H  and V L  are in series switching means S 5 -φ 2 , S 6 -φ 1 , S 7 -φ 2 , S 8 -φ 1 . The junction between S 6 -φ 1  and S 7 -φ 2  is node Vcap. A capacitor  64   a  is coupled between ground and the junction of S 5 -φ 2  and S 6 -φ 1 , and capacitor  64   b  is coupled between ground and the junction of S 7 -φ 2  and S 8 -φ. Node Vcap connects to the plus output of transconductor  32 . Similarly, coupled between nodes V H  and V L  are in series switching means S 9 -φ 1 , S 10 -φ 2 , S 11 -φ 1 , S 12 -φ 2 . The junction between S 10 -φ 2  and S 11 -φ 1  is node Vcap′ and connects to the negative output of transconductor  32 . Capacitor  64   c  is coupled between ground and the junction of S 9 -φ 1  and S 10 -φ 2 , and capacitor  64   d  is coupled between ground and the junction of S 11 -φ 1  and S 10 -φ 2 . Node Vcap′ connects to the minus output of transconductor  32 . Resistor R D  is defined as: R D =R A +R C , and resistor R E  is defined as: R E =R B +2R C . 
     Note that the suffix for S 1  to S 12  indicates during which phase the switching means is active, e.g., S 1 -φ 2 , S 4 -φ 2  and S 5 -φ 2  are on when output φ 2  of SR latch  38  is high, and S 2 -φ 1  S 3 -φ 1 ,  6 -φ 1  are on when output φ 1  is high. 
     FIG. 6 b  shows the waveforms for Vcap (Curve  61 ), Vcap′(Curve  62 ), φ 2  (Curve  63 ), and φ 1  (Curve  64 ). ). Curves  65  and  66  are enlarged sections of Curves  63  and  64  to more clearly demonstrate non-overlapping, caused by capacitors Cd. 
     The following table shows the comparison of the four embodiments: 
     
       
         
               
               
               
               
             
           
               
                   
               
               
                   
                   
                   
                 Waveform 
               
               
                 Embodiment no. 
                 H.F. capability 
                 Circuit complexity 
                 symmetry 
               
               
                   
               
             
             
               
                 1 
                 Low 
                 Low 
                 Good 
               
               
                 2 
                 Medium 
                 Medium 
                 Average 
               
               
                 3 
                 High 
                 High 
                 Average 
               
               
                 4 
                 Low 
                 Medium 
                 Very good 
               
               
                   
               
             
          
         
       
     
     Simulation Results: 
     Simulation results show that the circuit functions as expected. The calculated (with formula) and simulation frequency are very close. The curve of FIG. 7 shows a typical tuning characteristic of the CCO relating the bias current (I tune ) to the CCO frequency (f 0 ), valid for any of the above described preferred embodiments. 
     The method of providing a relaxation current controlled oscillator is shown in FIG.  8  and comprises the following steps: 
     Block  1 : forming an integrator from a test transconductance amplifier and capacitive means; 
     Block  2 : coupling the output of the integrator to comparator means; 
     Block  3 : applying the output of the comparator means to a bistable circuit; 
     Block  4 : applying a DC tuning current to adjust the transconductance g m  of the transconductance amplifier; 
     Block  5 : controlling switching means via the bistable circuit to alternate the state of the bistable circuit thus producing continuous oscillations. 
     In summary the advantages of the present invention include: 
     (1) A relaxation oscillator which is compatible with PLL-based tuning of g m -C filters. 
     (2) No start-up/amplitude control problems have to be overcome. 
     (3) There is more flexibility in deciding f REF  or f 0 . 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.