Abstract:
A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of U.S. patent application Ser. No. 13/212,731, filed Aug. 18, 2011, which is scheduled to issue as U.S. Pat. No. 8,156,262 on Apr. 10, 2012, which is a continuation application of U.S. patent application Ser. No. 12/503,097, filed Jul. 15, 2009, which issued as U.S. Pat. No. 8,019,913 on Sep. 13, 2011, which is a continuation of U.S. application Ser. No. 11/296,359, filed Dec. 8, 2005, which issued as U.S. Pat. No. 7,603,493 on Oct. 13, 2009, which is a divisional of U.S. patent application Ser. No. 10/191,290 filed Jul. 10, 2002, which issued as U.S. Pat. No. 7,149,824 on Dec. 12, 2006, the disclosures of which are hereby incorporated herein by reference. 
    
    
     FIELD OF INVENTION 
     The present invention relates to a method and apparatus which permits modification of the burst length of data in a memory device. 
     BACKGROUND OF THE INVENTION 
     A burst mode is known to be used in some memory devices to increase the speed of reading and writing data from and to the memory. Burst mode operation allows reads or writes from or to consecutive memory core locations at high speeds. When a burst mode is not implemented, a memory storage device uses one clock cycle to activate a row, giving the row address, and another clock cycle for column addressing. The READ or WRITE command is given with the column address on separate command lines. 
     In the clock cycle(s) following the addressing/command cycles, data is transferred from or to a memory device. For example, 4 eight bit data bytes being read from or written to a DDR SDRAM requires one clock cycle to decode each of the four column addresses. The first column address is issued with the READ or WRITE command with the subsequent column address being decoded internally on the DRAM device freeing up the command bus for other uses. 
     In addition, by eliminating column decoding time, the command bus is free to reduce latency during back intervening. Accordingly, a burst mode operation provides relatively high data transfer rates and significantly reduces the latency involved in a memory transfer. 
     The burst mode is generally controlled by setting one or more bits in a mode register provided within a memory device. As shown in  FIG. 1 , which depicts one exemplary memory device mode register, data within the mode register  100  controls a variety of different chip functions. Bits  13  and  14  of mode register  100  are used to select between a base mode register and an extended mode register; bits  7  through  12  of mode register  100  determine the operating mode of the memory device; bits  4 - 6  of mode register  100  determine the column address strobe (“CAS”) latency; bit  3  of mode register  100  determines whether the burst type is sequential or interleaved; and, bits  0 - 2  of mode register  100  determine the burst length. 
     The burst length determines the maximum number of consecutive column locations that can be accessed for a given READ or WRITE command without the need to use clock cycles to transfer subsequent intervening column addresses. As shown in tables  110  and  120 , burst lengths of 2, 4 or 8 bytes can be selected for each of the sequential and interleaved burst types which is set by bit position  3 . 
     Mode register  100  is programmed by a CPU or memory controller using a MODE REGISTER SET command and retains the set information until it is programmed again, or the memory device loses power. The mode register must be programmed while all memory cores are idle and no data bursts are in progress, and the memory controller or CPU must wait a specified time before initiating a memory access operation subsequent to programming. 
     A memory device which allows dynamic programming of burst length would be desirable and would permit faster adjustment of the burst length. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention mitigates the problems associated with current DRAM devices and provides a unique method and system of allowing a user to dynamically define burst length. 
     In accordance with an exemplary embodiment of the present invention, control pins provided on a memory storage device are used to set burst length. In addition, a control pin on the memory storage device can be used to determine the burst type. Using control pins to set burst length and type allows the burst length to be set while the memory cores are in use and without waiting after changing the burst length and/or type before initiating a memory access operation. 
     In another exemplary embodiment of the present invention, the address pins that are not used during column addressing are used for setting the burst length and/or burst type. This embodiment also allows the burst length and/or burst type to be set while the memory cores are in use and without waiting after changing the burst length and/or type before initiating a memory access operation. The burst length does not necessarily have to be set on active commands, READs or WRITEs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings. 
         FIG. 1  is an illustration of a conventional memory device mode register and its contents; 
         FIG. 2  is an illustration of the layout of control pins in a preferred embodiment of the present invention; 
         FIG. 3  is an illustration of a block diagram of a 256 Mx16 DDR SDRAM implementing the present invention. 
         FIG. 4  is an illustration of a burst length latch in a preferred embodiment of the present invention; 
         FIG. 5  is an illustration of a burst type latch in a preferred embodiment of the present invention; 
         FIG. 6  is an illustration of a column address counter/latch in an exemplary embodiment of the present invention; and 
         FIG. 7  illustrates a processor system which includes electronic devices containing the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention, and it is to be understood that structural changes may be made and equivalent structures substituted for those shown without departing from the spirit and scope of the present invention. 
     In accordance with an exemplary embodiment of the present invention, external pins provided on a memory storage device are used to dynamically set the burst length or hard set the burst length. An exemplary memory device  200  which may employ the invention is shown in  FIG. 2 , and is a 256 Mb double data rate synchronous DRAM (DDR SDRAM). As can be seen, memory device  200  has a plurality of control pins (for example, pins  21 ,  22 ,  23 ,  24  are control pins). While the following description of a preferred embodiment of the present invention is described with reference to a 256 Mb DDR SDRAM, the present invention can be implemented with any memory storage device having external pins. 
     Memory storage device  200  can be configured to use a single external pin to toggle between two possible burst lengths or a plurality of external pins if a larger number of burst lengths is desired. In most memory chip designs, there are many external pins that are not connected (“NC”) and can be turned into control pins. As a result, the present invention can be easily incorporated into most chip designs. One or more of the NC pins can be used as burst length toggle pins. For example, if two possible burst lengths are desired, pin  17  of memory storage device  200 , which is labeled NC in  FIG. 2 , can be used. If the two possible burst lengths are 4 bytes and 8 bytes, then when pin  17  is high, the burst length is e.g. 4 bytes; when pin  17  is low, the burst length is e.g. 8 bytes, or vice versa. If a burst length of 2 bytes is also desirable, NC pin  25  can also be used as up to four burst lengths can be programmed with two control pins. Although the description discusses several different burst lengths, the number of dynamically defined burst lengths is determined based on the number of available external pins. 
       FIG. 3  is a block diagram of the  FIG. 2  256 Mx16 DDR SDRAM. Control logic  310 , as shown in  FIG. 3 , receives a data signal on the burst length input pin (e.g. external pin  17 ) as an input. One or more external pins can be used to input burst length data. A command decode circuit  312 , which is part of the memory device control logic  310 , determines what the burst length is based on the data signals applied to the external burst control pin(s). For example, if the external burst pin is a single pin  17  (i.e. for 2 possible burst lengths), the command decode determines if the voltage on pin  17  is set to V cc  indicating a first burst length or V, indicating a second burst length. The status of the one or more burst length pins sets appropriate internal burst codes ( FIG. 4 , decode circuits  75 ,  77 ) within the command and decode circuit  312 . 
     Implementation of the present invention requires very little internal change to existing memory devices. Thus, where the burst length would previously be output from mode register  100  ( FIG. 1 ) to other circuits within control logic  310  ( FIG. 2 ) to set burst length, in the present invention, it is output to the other circuits from one or more decode circuits or data latches  75 ,  77  ( FIG. 4 ) within command decode circuit  312  which now contains this data. In both the conventional memory device of  FIG. 2  and one in accordance with the present invention, the burst length data is used by the control logic  310  to set burst length. Accordingly, nothing outside of the control logic  310  needs to be changed to implement the present invention, and very little change within control logic  310  is required. 
     By using external control pins to control the burst length instead of the mode register  100 , the burst length can be controlled dynamically from the exterior of the memory device  100 . The burst length also can be changed simultaneously with a READ or WRITE command. 
     In addition to using the external control pins to determine the burst length, the burst type can also be set using external control pins. This allows the burst type to also be set dynamically. As with using the external control pins to adjust burst length, using the external control pins to determine the burst type can be easily incorporated into most existing memory storage device designs by using another one of the NC pins. For example, referring to  FIG. 2 , external pin  53  could be used to determine burst type of the memory device  200 . If burst type pin  53  is e.g. high, the burst type is interleaved; if burst type pin  53  is e.g. low, the burst type is sequential. 
     The same type of modifications necessary to change control of the burst length from mode register  100  to the external pin  17  are necessary to change control of the burst type from mode register  100  to external pin  53 . Thus, a decode circuit  79  ( FIG. 5 ) within the column decode and burst counter circuit  312  receives a data signal applied to external pin  53  and the output of this circuit  79  goes to the same circuitry within the control logic  312  which processes burst type data previously set in the mode register  100 . Thus, controlling burst type with an external control pin only requires a small internal change within control logic  310 . 
     Another exemplary embodiment of the present invention uses the address pins to set burst length and/or burst type. As shown in  FIG. 3 , thirteen external pins (e.g. A 0 -A 12 ) are input into address register  320  for addressing. Both row and column addresses use the same 13 pins. During column addressing, however, only 10 (A 0 , . . . , A 9 ) of the 13 pins are needed. The remaining three pins (A 10  . . . A 12 ) can be used to determine burst length and/or burst type. 
     In this embodiment burst length data is applied to one or more of address pins A 10  . . . A 12 .  FIG. 6  shows two such address lines (A 10 , A 11 ) being used for this purpose. A decode circuit  81  decodes this data and supplies the burst length information to the column address counter/latch  330  ( FIG. 3 ). If less than all of the unused address lines are required for setting burst length, any remaining lines, e.g. A 12  in  FIG. 6 , can be used to set burst type decode circuit  77  ( FIG. 5 ). 
     It should be noted that although  FIG. 6  shows a decoder  81  for the burst length signal(s) which is external to the column address counter/latch  330 , decoder  81  may also be incorporated within the column address counter/latch  330 . 
     The mode register for a memory device implementing embodiments of the present invention does not require the bit positions A 0 -A 2  illustrated in mode register  100  for setting burst length and/or bit position A 3  for setting burst type and can therefore be made shorter in length, or the unused bit positions may be used for other functions. 
     The invention may be used in many types of memory devices in addition to the DDR SDRAM memory device illustrated in  FIGS. 2 and 3 . 
       FIG. 7  shows a processor system, such as, for example, a computer system in which the invention may be used. The processor system generally comprises a central processing unit (CPU)  710 , for example, a microprocessor, that communicates with one or more input/output (I/O) devices  740 ,  750  over a bus  770 . The system  700  also includes random access memory (RAM)  760 , a read only memory (ROM)  780  and, in the case of a computer system may include a permanent data storage device  708  and peripheral devices such as a floppy disk drive  720  and a compact disk (CD) ROM drive  730  which also communicates with CPU  710  over the bus  770 . The random access memory (RAM)  760  may incorporate external pin control of burst length and/or burst type in accordance with the invention. In addition, one or more of memory devices  760 ,  780  may be fabricated as an integral part with CPU  710 . While  FIG. 7  represents one processor system architecture, many others are also possible. 
     While the invention has been described with reference to an exemplary embodiments various additions, deletions, substitutions, or other modifications may be made without departing from the spirit or scope of the invention. Accordingly, the invention is not to be considered as limited by the foregoing description, but is only limited by the scope of the appended claims. 
     Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.