Abstract:
A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests disclosed in the present invention provides the digital input interfaces, which are comprised of capacitors, analog switches and digital circuits, for the usage of testing the mixed-signal circuits. The present invention provides a low-priced testing platform to accomplish the testing of circuits and to solve the problems of high-cost mixed mode tester and of utmost restrictions against the surrounding condition. Therefore, the present invention improves the testability, reduces the test cost, shorten the processes of designation and efficiently seize on the time-to-market.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The invention is related to a reconfigurable switched-capacitor input circuit, and more particularly, to a reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for testing mixed-signal circuits. 
   2. Description of the Related Art 
   At all electronics and electrical manufacturers focus on the family amusement market of meanwhile, makes the audio chip market growing up significantly. Hence, the test for a mixed-signal component that is comprised of the switched-capacitor circuits, such as the Sigma-Delta modulators, becomes more and more important. The evolution of the integrated circuit manufacture technology allows integrating diverse components such as digital, analog, and memory circuits on the same chip. The testability and high testing cost of such products become a sever issue due to the diversity of the test characteristics of the embedded circuits. And this issue is much more critical for the mixed-signal circuits since their tests traditionally have to rely on high-priced mixed-signal circuit testers like Aglient 94000. Also, on account of most testers that do not support testing the analog circuit and digital circuit simultaneously, a longer testing time is required and makes disadvantageous fluctuation factors in both of the cost and time-to-market of the products. 
   U.S. Pat. No. 5,132,685 titled as “Built-in self test for analog to digital converters” indicates that a ramp generator with a large area is exerted additionally and provides a ramp voltage to the A/D input, while a state machine monitors the output. Nevertheless, the testing accuracy depends on how accurate the ramp generator&#39;s output is and the generated ramp signal is not suitable for testing the circuits of either the Sigma-Delta modulator or the filter. 
   As for what disclosed in U.S. Pat. No. 5,305,003, “Test device of analog/digital converter”it is a digital circuit for testing the analog/digital converter only and fails to test the analog circuit. 
   In U.S. Pat. No. 5,659,312, it titles as “Method and apparatus for testing digital to analog and analog to digital converters” and reveals that a highly accurate built-in digital-to-analog converter with a large area is used as the stimulus source. In this invention, the testing accuracy depends on the accuracy of the built-in digital-to-analog converters exerted; that is, the digital-to-analog converter has to be verified by some means first. Consequently, higher cost for hardware and testing has to be endured. 
   A built-in self-test for analog to digital converter is mentioned in U.S. Pat. No. 6,333,706, a built-in random-waveform generator with a large area is applied in this invention. Still, the accuracy of test results depends on the accuracy of the built-in random-waveform generators employed. In addition to the higher hardware cost, the built-in random-waveform generator would not carry out the at-speed tests. 
   SUMMARY OF THE INVENTION 
   The primary objective of the present invention is to provide a reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for testing mixed-signal circuits, which carries out the tests of mixed-signal circuits via digital stimulus signals, would reduce the test cost. 
   A further objective of the present invention is to share critical circuit elements during testing thus offers high testing accuracy, high fault-coverage and the capability of performing at-speed tests owning to the shared critical circuit elements having the same loads in both test and normal operation modes. 
   A still further objective of the present invention is to provide a particular-designed reconfigurable circuit, which would apply for all kinds of the mixed-signal circuit architectures, for accelerating the design process and shortening the time-to-market. 
   According to the present invention, these objectives are achieved by providing a reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for testing mixed-signal circuits. The reconfigurable switched-capacitor input circuit includes an analog-input signal, a plurality of direct current voltage sources, an operational amplifier, at least two switched-capacitor sets as well as a digital switching-signal generator. The analog-input signal contains a positive phase voltage signal and a negative phase voltage signal. Those direct current voltage sources contain a first direct current voltage source, a second direct current voltage source, a third direct current voltage source, and a fourth direct current voltage source. The operational amplifier has a positive input end, a negative input end, a positive amplifier output end, and a negative amplifier output end; the operational amplifier amplifies the voltage bias of the positive and the negative input ends and produces an amplified output voltage between the positive and the negative amplifier output ends. Each of the switched-capacitor set consists of a first capacitor, a second capacitor and a plurality of analog-signal switches and every capacitor mentioned above has a bottom end and a top end. Moreover, every switched-capacitor set has a corresponding digital stimulus, which is a Sigma-Delta modulated bit-stream and has two logic states: an increased state and a decreased state. As for the signals received by the digital switching-signal generator, the digital mode signal has two logic states including a normal mode state and a test mode state; the clock signal is used to generate at least two non-overlapped clock phases including a first clock phase and a second clock phase. The digital switching-signal generator receives at least a digital mode signal, a clock signal, a plurality of the digital stimuli and generating a plurality of switching signals to control the analog-signal switches of the switched-capacitor sets. When the digital mode signal is in the test mode state, each of the switched-capacitor set behaves as a one-bit digital-to-charge converter with its corresponding digital stimulus as the digital input. 
   Over and above, those objectives also can be achieved by providing a reconfigurable switched-capacitor input circuit with digital-stimulus acceptability, which suits for a digitally testable architecture with a switched-capacitor input circuit. The reconfigurable switched-capacitor input circuit includes an analog-input signal, a plurality of direct current voltage sources, an operational amplifier, at least one switched-capacitor set as well as a digital switching-signal generator. The analog-input signal contains a positive phase voltage signal and a negative phase voltage signal. Those direct current voltage sources contain a first direct current voltage source, a second direct current voltage source, and a third direct current voltage source. The operational amplifier has a positive input end, a negative input end, a positive amplifier output end, and a negative amplifier output end; the operational amplifier amplifies the voltage bias of the positive and the negative input ends and produces an amplified output voltage between the positive and the negative amplifier output ends. Each of the switched-capacitor set consists of a first capacitor, a second capacitor and a plurality of analog-signal switches and every capacitor mentioned above has a bottom end and a top end. Moreover, every switched-capacitor set has a corresponding digital stimulus, which is a Sigma-Delta modulated bit-stream and has two logic states: an increased state and a decreased state. The digital switching-signal generator receives at least a digital mode signal, a clock signal, and a plurality of the digital stimuli and generates a plurality of switching signals to control the analog-signal switches of the switched-capacitor sets. As for the signals received by the digital switching-signal generator, the digital mode signal has two logic states including a normal mode state and a test mode state; the clock signal is used to generate at least two non-overlapped clock phases including a first clock phase and a second clock phase. When the digital mode signal is in the test mode state, each of the switched-capacitor set behaves as a one-bit digital-to-charge converter with its corresponding digital stimulus as the digital input. 
   Finally, there is still another architecture disclosed in this invention to achieve the objectives. A reconfigurable switched-capacitor input circuit with digital-stimulus acceptability for analog tests, which suits for a digitally testable architecture with a switched-capacitor input circuit. The reconfigurable switched-capacitor input circuit includes an analog-input signal, a digital-data signal, multiple direct current voltage sources, an operational amplifier, at least one switched-capacitor set as well as a digital switching-signal generator. The analog-input signal contains a positive phase voltage signal and a negative phase voltage signal while the digital-data signal has a subtraction logic state and an addition logic state. Those direct current voltage sources contain a first direct current voltage source, a second direct current voltage source and a third direct current voltage source. The operational amplifier has a positive input end, a negative input end, a positive amplifier output end, and a negative amplifier output end. The operational amplifier amplifies the voltage bias/difference of the positive and the negative input ends and produces an amplified output voltage between the positive and the negative amplifier output ends. Each of the switched-capacitor set consists of a first capacitor, a second capacitor and a plurality of analog-signal switches and every capacitor mentioned above has a bottom end and a top end. Moreover, every switched-capacitor set has a corresponding digital stimulus, which is a Sigma-Delta modulated bit-stream and has two logic states: an increased state and a decreased state. The digital switching-signal generator receives at least a digital mode signal, a clock signal, the digital-data signal, and a plurality of the digital stimuli and generates a plurality of switching signals to control the analog-signal switches of the switched-capacitor sets. As for the signals received by the digital switching-signal generator, the digital mode signal has two logic states including a normal mode state and a test mode state; the clock signal is used to generate at least two non-overlapped clock phases including a first clock phase and a second clock phase. When the digital mode signal is in the test mode state, each of the switched-capacitor set behaves as a one-bit digital-to-charge converter with its corresponding digital stimulus as the digital input. At the same time, each of the switched-capacitor set also preserves the effects of the digital-data as in the normal mode operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which: 
       FIG. 1  depicts the operation of the reconfigurable switched-capacitor input circuit in the normal mode for the first and third embodiments of the present invention. 
       FIG. 2  depicts the operation of the reconfigurable switched-capacitor input circuit in the test mode for the first and the second embodiments of the present invention. 
       FIG. 3  depicts the operation of the reconfigurable switched-capacitor input circuit in the normal mode for the second and the fourth embodiments of the present invention. 
       FIG. 4  depicts the operation of the reconfigurable switched-capacitor input circuit in the test mode for the third and the fourth embodiments of the present invention. 
       FIG. 5  depicts the operation of the reconfigurable switched-capacitor input circuit in the normal mode of the fifth embodiment of the present invention. 
       FIG. 6  depicts the operation of the reconfigurable switched-capacitor input circuit in the test mode of the fifth embodiment of the present invention. 
       FIG. 7  depicts the operation of the reconfigurable switched-capacitor input circuit in the normal mode of the sixth and the eighth embodiments of the present invention. 
       FIG. 8  depicts the operation of the reconfigurable switched-capacitor input circuit in the test mode of the sixth and the seventh embodiments of the present invention. 
       FIG. 9  depicts the operation of the reconfigurable switched-capacitor input circuit in the normal mode of the seventh and the ninth embodiments of the present invention. 
       FIG. 10  depicts the operation of the reconfigurable switched-capacitor input circuit in the test mode of the eighth and the ninth embodiments of the present invention. 
       FIG. 11  depicts the operation of the reconfigurable switched-capacitor input circuit in the normal mode of the tenth embodiment of the present invention. 
       FIG. 12  depicts the operation of the reconfigurable switched-capacitor input circuit in the test mode of the tenth embodiment of the present invention. 
       FIG. 13  is a practical circuit implementation of the switched-capacitor set for the third embodiment of the present invention. 
       FIG. 14  is a practical circuit implementation exerting two switched-capacitor sets for the third embodiment of the present invention. 
       FIG. 15  is a practical circuit implementation exerting two switched-capacitor sets and the switched-capacitor sets sharing several analog switches for the third embodiment of the present invention. 
       FIG. 16  is a second-order Sigma-Delta modulator example that exerts the third embodiment of the present invention. 
       FIG. 17  is a third-order Sigma-Delta modulator example that exerts the third embodiment of the present invention. 
       FIG. 18  is a second-order switched-capacitor low pass filter exerting the third embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention, which exerts the switched-capacitor and switch circuits as a reconfigurable switched-capacitor input circuit to replace the original input network of the circuit under test for receiving the digital stimuli during the analog test process, reduces the test cost substantially. 
   The present invention is a brand-new digitally testable circuit, which is suitable for the applications with a switched-capacitor input circuit. Substituting the switched-capacitor input circuit of the circuit under test with this invention provides two operation modes through controlling the digital mode signal: the normal mode and test mode. In the normal mode, the additional design-for-testability circuits have no impact on the circuit under test; the circuit under test stays in the primordial operation. 
   To better understand the operation of the reconfigurable switched-capacitor input circuit, the circuit connections in the two non-overlapped clock phases are described.  FIG. 1  represents the operation of the reconfigurable switched-capacitor input circuit in the normal mode for the first embodiment of the present invention that exerts at least two switched-capacitor sets.  FIG. 1(A)  shows the circuit connections in the first clock phase. The digital switching-signal generator generates the switching signals to control the analog-signal switches of the switched-capacitor sets  11  and  12  so that the bottom ends of the first capacitors Cp 0  and Cp 1  of the switched-capacitor sets connect to the analog input positive phase voltage signal +Vin and the bottom ends of the second capacitors Cn 0  and Cn 1  of the switched-capacitor sets connect to the analog input negative phase voltage signal −Vin. And all the top ends of the capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  connect to the direct current voltage source VC 2 . The circuit connections in the second clock phase in the normal mode are shown in  FIG. 1(B) . All the bottom ends of the capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  of the switched-capacitor sets  11 ′ and  12 ′ connect to the direct current voltage source VC 1 ; meanwhile, the top ends of the first capacitors Cp 0  and Cp 1  connect to the negative input end of the operational amplifier (opamp) and the top ends of the second capacitors Cn 0  and Cn 1  connect to a positive input end of the operational amplifier. 
   Furthermore,  FIG. 2  represents the operation in the test mode of the first embodiment of the present invention, wherein  FIG. 2(A)  and  FIG. 2(B)  illustrate the circuit connections in the two non-overlapped clock phases respectively.  FIG. 2(A)  shows the connections of the circuits in the first clock phase in the test mode. The conceptual analog multiplexers  211  and  212  are made up of the analog-signal switches of the switched-capacitor set  21  and accompanied with the capacitors within the switched-capacitor set  21  as well as the conceptual analog multipiexers  213  and  214  are parts of the switched-capacitor set  22  and accompanied with the capacitors within the switched-capacitor set  22 . The top ends of the capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  of the switched-capacitor sets  21  and  22  connect to the direct current voltage source VC 2 . The digital switching-signal generator receives a digital stimulus Di 0  and depends on its logic state to generate the switching signals to control the conceptual analog multiplexers  211  and  212  as well as the analog-signal switches of the switched-capacitor set  21 ; the digital switching-signal generator also receives a digital stimulus Di 1  to control the conceptual analog multiplexers  213  and  214 . And then, the connection states of the accompanied switched-capacitor sets  21  and  22  are determined in an “increased state” or a “decrease state” depending on their corresponding digital stimuli. The “increased state” of a switched capacitor set is defined if the bottom end of the first capacitor Cp 0  or Cp 1  within the switched-capacitor set is switched to connect to the direct current voltage source VR 1  and the bottom end of the second capacitor Cn 0  or Cn 1  within the same switched-capacitor set connects to the direct current voltage source VR 2 . On the other hand, the switched-capacitor set is in its “decreased state” if the bottom end of the first capacitor within the switched-capacitor set connects to the direct current voltage source VR 2  as well as the bottom end of the second capacitor within the same switched-capacitor set connects to the direct current voltage source VR 1 . 
   The digital stimuli Di 1  and Di 0  are the Sigma-Delta modulated digital stimulus bit-streams. The difference between the digital stimulus Di 1  and the digital stimulus Di 0  is that the digital stimulus Di 1  is delayed by at least one period comparing to the digital stimulus Di 0 . 
   Referring to  FIG. 2(B) , the circuit connections in the second clock phase in the test mode are indicated. All the bottom ends of capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  inside the switched-capacitor sets  21 ′ and  22 ′ connect to the direct current voltage source VC 1  controlled by the switching signals generated from the digital switching-signal generator. Also, the top ends of the first capacitors Cp 0  and Cp 1  within the switched-capacitor sets  21 ′ and  22 ′ connect to the negative input end of the operational amplifier and the top ends of the second capacitors Cn 0  and Cn 1  within the switched-capacitor sets  21 ′ and  22 ′ connect to the positive input end of the operational amplifier. 
   Actually, the operation of the input circuit of the circuit under test in the normal mode is not limited by that revealed in  FIG. 1 . The second embodiment with regard to the reconfigurable switched-capacitor input circuit in the normal mode is introduced in  FIG. 3 , wherein  FIG. 3(A)  and  FIG. 3(B)  represent the circuit connections in the two non-overlapped clock phases respectively. The circuit connections of the input circuit in the first clock phase are provided in  FIG. 3(A) . The digital switching-signal generator generates the switching signals to connect the analog input positive phase voltage signal +Vin to the bottom ends of the first capacitors Cp 0  and Cp 1  of the switched-capacitor sets  31  and  32  and, in the meantime, to connect the analog input negative phase voltage signal −Vin to the bottom ends of the second capacitors Cn 0  and Cn 1  of the switched-capacitor sets  31  and  32 . The top ends of the first capacitors of the switched-capacitor sets are connected to the negative input end of the operational amplifier and the top ends of the second capacitors of the switched-capacitor sets are connected to the positive input end of the same operational amplifier. In  FIG. 3(B) , the circuit connections in the second clock phase are shown. All the bottom ends of the switched-capacitor sets  31 ′ and  32 ′ connect to the direct current voltage source VC 1  and all the top ends of the switched-capacitor sets  31 ′ and  32 ′ connect to the direct current voltage source VC 2 . 
   Besides, the test mode operation in the two non-overlapped clock phases of the second embodiment whose normal mode operation is disclosed in  FIG. 3  is the same as what mentioned in  FIG. 2 . 
   Additionally, the test mode operation of a third embodiment of this invention whose normal mode operation is described in  FIG. 1  is unfolded in  FIG. 4 . Similar to the disclosure in  FIG. 2 , the circuit connections in the two non-overlapped clock phases in the test mode are shown in  FIG. 4(A)  and  FIG. 4(B)  respectively. In the first clock phase, the digital switching-signal generator generates the switching signals to control the analog-signal switches of the switched-capacitor sets  41  and  42  to make the top ends of the capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  inside the switched-capacitor sets  41  and  42  connecting to the direct current voltage source VC 2  as illustrated in  FIG. 4(A) . At the same time, the bottom ends of the first capacitors Cp 0  and Cp 1  and the second capacitors Cn 0  and Cn 1  inside the switched-capacitor sets  41  and  42  are connected to the direct current voltage source VR 1  and the direct current voltage source VR 2  respectively. One part of what illustrated in  FIG. 4(B)  is that all the bottom ends of all the capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  inside the switched-capacitor sets  41 ′ and  42 ′ are switched to connect to the direct current voltage source VC 1  in the second clock phase via the control of the switching signals from the digital switching-signal generator. Meanwhile, the digital switching-signal generator receives the digital stimuli Di 0  and Di 1  to generate corresponding switching signals to control the corresponding conceptual analog multiplexers  411 ,  412 ,  413  and  414  which are parts of the switched-capacitor sets  41 ′ and  42 ′ and to individually switch the switched-capacitor sets  41 ′ and  42 ′ to their “increased state” or the “decreased state”. When the top end of the first capacitor inside the switched-capacitor set connects to the negative input end of the operational amplifier as well as the top end of the second capacitor inside the same switched-capacitor set connects to the positive input end of the operational amplifier, the switched-capacitor set is defined in its “increased state”. If the top end of the first capacitor inside the switched-capacitor set connects to the positive input end of the operational amplifier as well as the top end of the second capacitor inside the same switched-capacitor set connects to the negative input end of the operational amplifier, the switched-capacitor set is defined in its “decreased state”. The digital stimuli Di 1  and Di 0  are the Sigma-Delta modulated digital stimulus bit-streams and the sole difference between the digital stimulus Di 1  and the digital stimulus Di 0  is at least one period delayed for the former one comparing to the later one. 
   The operation of the input circuit in the normal mode of a fourth embodiment is disclosed in detail by  FIG. 3 . The test mode operation of the fourth embodiment is the same as mentioned in  FIG. 4 . 
   Among the four embodiments provided above, the relationship of the two non-overlapped clock phases of both the normal and test modes may be the combinations of the one-to-one correspondent, of the first clock phase in the normal mode corresponding to the second clock phase in the test mode and of the second clock phase in the normal mode corresponding to the first clock phase in the test mode. The switched-capacitor sets mentioned may share several analog-signal switches. The direct current voltage source VC 1  may be the direct current voltage source VR 1  or the direct current voltage source VR 2 ; the direct current voltage source VC 2  may be the direct current voltage source VC 1 , the direct current voltage source VR 1 , or the direct current voltage source VR 2 . The “increased state” of the digital stimulus Di 0  may be corresponding to the “decreased state” of the digital stimulus Di 1  while the “decreased state” of the digital stimulus Di 0  may be corresponding to the “increased state” of the digital stimulus Di 1 . 
   In  FIG. 5 , a fifth embodiment that includes at least two switched-capacitor sets is disclosed. Still, there are at least two non-overlapped clock phases under the normal mode operation as illustrated in  FIG. 5(A)  and  FIG. 5(B) . In the first clock phase, the circuit connections of the reconfigurable switched-capacitor input circuit in the normal mode, which are controlled by the digital switching-signals, are shown in  FIG. 5(A) . The bottom ends of the first capacitors Cp 0  and Cp 1  of the switched-capacitor sets  51  and  52  are switched to connect to the analog input positive phase voltage signal +Vin; the bottom ends of the second capacitors Cn 0  and Cn 1  of the switched-capacitor sets  51  and  52  are switched to connect to the analog input negative phase voltage signal −Vin. The top ends of all the capacitors Cp 0 , Cn 0 , Cp 1  and Cn 1  of the switched-capacitor sets  51  and  52  are connected to the direct current voltage source VC 2 . Referring to  FIG. 5(B) , the circuit connections in the second clock phase in the normal mode are the top ends of the first capacitors Cp 0  and Cp 1  of the switched-capacitor sets  51 ′ and  52 ′ connect to the negative input end of the operational amplifier; the top ends of the second capacitors Cn 0  and Cn 1  of the switched-capacitor sets  51 ′ and  52 ′ connect to the positive input end of the operational amplifier. According to the logic state of the digital-data signal Diy received, the digital switching-signal generator generates switching signals to control the switched-capacitor sets  51 ′ and  52 ′ being in a “subtraction state” or an “addition state”. The circuit connections of the “subtraction state” are those the bottom ends of the first capacitors of the switched-capacitor sets  51 ′ and  52 ′ connect to the direct current voltage source VR 1  while the bottom ends of the second capacitors of the switched-capacitor sets  51 ′ and  52 ′ connect to the direct current voltage source VR 2 . On the other hand, the circuit connections of the “addition state” are those the bottom ends of the first capacitors of the switched-capacitor sets  51 ′ and  52 ′ connect to the direct current voltage source VR 2  while the bottom ends of the second capacitors of the switched-capacitor sets  51 ′ and  52 ′ connect to the direct current voltage source VR 1 . 
   In the basis of the embodiment in  FIG. 5 , the reconfigurable switched-capacitor input circuit operates in the test mode through controlling the digital mode signal. The test mode operation in the two non-overlapped clock phases are illustrated by  FIG. 6(A)  and  FIG. 6(B)  respectively. In the first clock phase, the digital switching-signal generator generates the switching signals to control the conceptual analog multiplexers  611  and  612  those are parts of the switched-capacitor set  61  so that the switched-capacitor set is in an “increased state” or a “decreased state” depending on the digital stimulus Di 0 . Similarly, the digital switching-signal generator generates the switching signals to control the conceptual analog multiplexers  613  and  614  inside the switched-capacitor set  62  so that the switched-capacitor set  62  is in the “increased state” or the “decreased state” depending on the digital stimulus Di 1 . The circuit connections of the “increased state” are those the bottom end of the first capacitor of the switched-capacitor set connects to the direct current voltage source VR 1  while the bottom end of the second capacitor of the same switched-capacitor set  61  or  62  connects to the direct current voltage source VR 2 . Oppositely, the circuit connections of the “decreased state” are those the bottom end of the first capacitor of the switched-capacitor set connects to the direct current voltage source VR 2  while the bottom end of the second capacitor of the same switched-capacitor set connects to the direct current voltage source VR 1 . All top ends of the capacitors in the switched-capacitor sets are connected to the direct current voltage source VC 2  in the first clock phase in the test mode. 
   The circuit connections in the second clock phase in the test mode are illustrated in  FIG. 6(B) . The top ends of the first capacitors Cp 0  and Cp 1  of the switched-capacitor sets  61 ′ and  62 ′ are connected to the negative input end of the operational amplifier while the top ends of the second capacitors Cn 0  and Cn 1  of the switched-capacitor sets  61 ′ and  62 ′ are connected to the positive input end of the operational amplifier. Moreover, depending on the logic state of the digital-data signal Diy received, the digital switching-signal generator generates switching signals to control the analog-signal switches as well as the conceptual analog multiplexers  615  and  616  and in the switched-capacitor sets  61 ′ and  62 ′ so that the switched-capacitor sets  61 ′ and  62 ′ are in a “subtraction state” or an “addition state”. The circuit connections of the “subtraction state” are those the bottom ends of the first capacitors of the switched-capacitor sets  61 ′ and  62 ′ connect to the direct current voltage source VR 1  while the bottom ends of the second capacitors of the switched-capacitor sets  61 ′ and  62 ′ connect to the direct current voltage source VR 2 . The circuit connections of the “addition state” are those the bottom ends of the first capacitors of the switched-capacitor sets  61 ′ and  62 ′ connect to the direct current voltage source VR 2  while the bottom ends of the second capacitors of the switched-capacitor sets  61 ′ and  62 ′ connect to the direct current voltage source VR 1 . The digital stimuli Di 1  and Di 0  are the Sigma-Delta modulated digital stimulus bit-streams and the sole difference between the digital stimulus Di 1  and the digital stimulus Di 0  is at least one period delayed for the former one comparing to the later one. 
   Furthermore, in the fifth embodiment, the “subtraction state” in the normal mode may be corresponding to the “addition state” in the test mode and vice versa. Similarly, the above-mentioned “increased state” controlled by the digital stimulus Di 1  may correspond to the above-mentioned “decreased state” controlled by the digital stimulus Di 0  and vice versa. Also, at least one analog-signal switch may be shared by the switched-capacitor sets. VC 2  can be either VR 1  or VR 2 . 
   Referring to  FIG. 7 , the normal mode operation of a sixth embodiment of the present invention that contains at least one switched-capacitor set is disclosed. The circuit connections in the two non-overlapped clock phases are illustrated in  FIG. 7(A)  and  FIG. 7(B) . In  FIG. 7(A) , the circuit connections of the switched-capacitor set  71  in the first clock phase are revealed. The digital switching-signal generator generates switching signals to control at least a switched-Capacitor set. The bottom end of the first capacitor Cp of the switched-capacitor set  71  is switched to connect to an analog input positive phase voltage signal +Vin; at the same time, the bottom end of the second capacitor Cn of the same switched-capacitor set is switched to connect to an analog input negative phase voltage signal −Vin. And the top ends of both capacitors Cp and Cn are connected to the direct current voltage source VC 2 . In  FIG. 7(B) , the circuit connections of the switched-capacitor set  71 ′ in the second clock phase in the normal mode are provided. The digital switching-signal generator generates the switching signals to control the bottom ends of the capacitors Cp and Cn in the switched-capacitor set  71 ′ connecting to the direct current voltage source VC 1 . Meanwhile, the top ends of the capacitors Cp and Cn are connected to the negative input end and the positive input end of the operational amplifier respectively. 
   In  FIG. 8 , the test mode operation of the sixth embodiment of the present invention is provided. Still, at least two non-overlapped clock phases are included in the test mode and the circuit connections are illustrated in  FIG. 8(A)  and  FIG. 8(B) . The circuit connections of the switched-capacitor set  81  in the first clock phase in the test mode are shown in  FIG. 8(A) . The digital switching-signal generator generates switching signals to make the direct current voltage sources VR 1  and VC 1  respectively connecting to the bottom ends of the capacitors Cp and Cn of the switched-capacitor set  81 . At the same time, the top ends of the capacitors Cp and Cn are all connected to the direct current voltage source VC 2 . In  FIG. 8(B) , the circuit connections in the second clock phase in the test mode are provided. The digital switching-signal generator generates associated switching signals to control the analog-signal switches as well as the conceptual analog multiplexers  811  and  812  inside the switched-capacitor set  81 ′ so that the bottom end of the first capacitor Cp connects to the direct current voltage source VC 1  and the bottom end of the second capacitor Cn connect to the direct current voltage source VR 1 . Depending on the logic state of the digital stimulus Di 0  received by the digital switching-signal generator, the corresponding switched-capacitor set  81 ′ is in an “increased state” or a “decreased state”. The circuit connections of the “increased state” are those the top end of the first capacitor Cp connects to the negative input end of the operational amplifier and the top end of the second capacitor Cn connects to the positive input end of the operational amplifier; the circuit connections of the “decreased state” are those the top end of the first capacitor Cp connects to the positive input end of the operational amplifier and the top end of the second capacitor Cn connects to the negative input end of the operational amplifier. 
   Referring to  FIG. 9 , the normal mode operation of the seventh embodiment of the present invention is shown. In  FIG. 9(A) , the circuit connections in the first clock phase are illustrated. The digital switching-signal generator generates switching signals to control the switched-capacitor set  91  such that the bottom ends of the capacitors Cp and Cn of the switched-capacitor set  91  connect to the analog input positive and negative voltage signals +Vin and −Vin respectively. At the same time, the top ends of the capacitors Cp and Cn connect to the negative and the positive input ends of the operational amplifier respectively. In  FIG. 9(B) , the circuit connections in the second clock phase are provided. The digital switching signals control the analog-signal switches in the switched-capacitor set  91 ′ so that the bottom ends of the capacitors Cp and Cn are connect to the direct current voltage source VC 1  while the top ends of the capacitors Cp and Cn connect to the direct current voltage source VC 2 . 
   Moreover, the test mode operation of the seventh embodiment is illustrated in  FIG. 8 . 
   As for the eighth embodiment that contains at least a switched-capacitor set, its circuit connections in the two non-overlapped clock phases operating in the normal mode are the same as shown in  FIG. 7 . 
   The test mode operation of the eighth embodiment is shown in  FIG. 10 . In  FIG. 10(A) , the circuit connections in the first clock phase are shown. The top ends of the capacitors in the switched-capacitor set connect to the direct current voltage source VC 2 . The switching-signal generator receives the corresponding digital stimulus Di 0  of the switched-capacitor set and generates corresponding switching signals to control the analog-signal switches as well as the conceptual analog multiplexers  101  and  102  inside the switched-capacitor set  100  to decide the switched-capacitor set to be in an “increased state” or a “decreased state”. In the “increased state”the bottom end of the first capacitor Cp connects to the direct current voltage source VR 1  while the bottom end of the second capacitor Cn connects to the direct current voltage source VC 1 . In the “decreased state”the bottom end of the first capacitor connects to the direct current voltage source VC 1  while the bottom end of the second capacitor connects to the direct current voltage source VR 1 . In  FIG. 10(B) , the circuit connections in the second clock phase in the test mode are provided. The bottom ends of the capacitors Cp and Cn connect to the direct current voltage source VC 1  and the top ends of the capacitors Cp and Cn respectively connect to the negative input end and the positive input end of the operational amplifier. 
   The normal mode operation of the ninth embodiment of the present invention is illustrated in  FIG. 9 . The circuit connections in the two non-overlapped clock phases in the test mode of the ninth embodiment of the present invention are as illustrated in  FIG. 10 . 
   Among the sixth, seventh, eighth and ninth embodiments provided above, one of the relationships of the two non-overlapped clock phases in both normal and test modes can be one-to-one correspondent. Also, the relationships of the first clock phase in the normal mode corresponding to the second clock phase in the test mode and the second clock phase in the normal mode corresponding to the first clock phase in the test mode are both allowable. Besides, if there are more than one switched-capacitor sets, the switched-capacitor sets are able to share at least one analog-signal switch. The direct current voltage source VC 2  can be the same as either the direct current voltage source VR 1  or the direct current voltage source VC 1 . 
   In  FIG. 11 , the normal mode operation of the tenth embodiment is provided. The tenth embodiment contains at least a switched-capacitor set. The circuit connections in the first clock phase are shown in  FIG. 11(A) . In the first clock phase, the bottom ends of the capacitors Cp and Cn of the switched-capacitor set  110  connect respectively to the analog input positive voltage signal +Vin and the analog input negative voltage signal −Vin. At the same time, the top ends of the capacitors Cp and Cn connect to the direct current voltage source VC 2 . Referring to circuit connections in the second clock phase illustrated in  FIG. 11(B) , the top end of the first capacitor Cp connects to the negative input end of the operational amplifier; the top end of the second capacitor Cn connects to the positive input end of the operational amplifier. Depending on the logic state of the received digital-data signal Diy, the digital switching-signal generator generates switching signals to control the analog switches and the conceptual analog multiplexers  111  and  112  inside the switched-capacitor set  110 ′ to determine the switched-capacitor set being in a “subtraction state” or an “addition state”. The “subtraction state” of the switched-capacitor set is that the bottom end of its first capacitor connects to the direct current voltage source VR 1  and the bottom end of its second capacitor connects to the direct current voltage source VR 2 . On the other hand, the “addition state” is defined as that the bottom end of the first capacitor Cp connects to the direct current voltage source VR 2  and the bottom end of the second capacitor Cn connects to the direct current voltage source VR 1 . 
   Referring to  FIG. 12 , the test mode operation of the tenth embodiment is provided. In the first clock phase in the test mode illustrated in  FIG. 12(A) , The digital switching-signal generator receives a corresponding digital stimulus Di 0  and generates switching signals to control the analog-signal switches as well as the conceptual analog multiplexers  121  and  122  in the switched-capacitor set. The switched-capacitor set either in an “increased state” or in a “decreased state” is determined by the current logic state of the digital stimulus Di 0 . In both states, the top ends of the capacitors Cp and Cn connect to a direct current voltage source VC 2 . When the switched-capacitor set is in the “increased state”the bottom ends of the capacitors Cp and Cn connect to the direct current voltage sources VR 1  and VR 2  respectively. When the switched-capacitor set is in the “decreased state”the bottom ends of the capacitors Cp and Cn connect to the direct current voltage sources VR 2  and VR 1  respectively. 
   In the second clock phase shown in  FIG. 12(B) , the top ends of the first capacitor Cp and second capacitor Cn connect respectively to the negative and positive input ends of the operational amplifier. The digital switching-signal generator receives the digital-data signal Diy and generates switching signals to control the analog-signal switches as well as the conceptual analog multiplexers  121 ′ and  122 ′ inside the switched-capacitor set. A “subtraction state” or an “addition state” of the switched-capacitor set is varied by the above-mentioned results. The circuit connections of the “subtraction state” are those bottom end of the first capacitor connects to the direct current voltage source VR 1  and bottom end of the second capacitor connects to the direct current voltage source VR 2 ; the “addition state” is defined as that the bottom end of the first capacitor connects to the direct current voltage source VR 2  and the bottom end of the second capacitor connects to the direct current voltage source VR 1 . In both states, the top ends of the two capacitors Cp and Cn are connected to the negative input end and the positive input end of the operational amplifier respectively. 
   As for the tenth embodiment above, the “subtraction state” in the normal mode may match with the “addition state” in the test mode and vice versa. At least one analog-signal switch can be shared by the switched-capacitor sets. The direct current voltage source VC 2  may be replaced by the direct current voltage source VR 1  or VR 2 . 
   For the ten embodiments mentioned above, the operational amplifier may be a part of the circuit under test. 
   What illustrated in  FIG. 13  is a practical circuit implementation of the switched-capacitor set described in the third embodiment of the present invention. ph 1  and ph 2  are the signals used to define the two non-overlapped clock phases. −OPin and +OPin represents the negative input end and the positive input end of the operational amplifier respectively. Every analog-signal switch turns on if its control signal shown in  FIG. 13  is logic “1”. T is the digital mode signal and Tb is the logic inverse of T. Similarly, Di 0  is the digital stimulus and Di 0 b is the logic inverse of it. 
   In  FIG. 14 , the circuit implementation of using two switched-capacitor sets applied in the third embodiment of the present invention is provided. 
   Referring to  FIG. 15 , the circuit implementation of using two switched-capacitor sets that share several analog-signal switches in the third embodiment of this invention is shown. 
   Referring to  FIG. 16 , a circuit schematic of the second-order Sigma-Delta modulator exerting the third embodiment of the present invention is illustrated. The schematic uses two capacitor sets  57  and  58  and is provided with two operation modes including the normal mode and the test mode. When T=0, Tb=1, Di 0 =1, Di 0 b=0, Di 1 =1 and Di 1 b=0, the circuit is in the normal mode and receives an analog input signal ±Vin. The circuit under this condition is a conventional second-order Sigma-Delta modulator in normal operation. As T=1 and Tb=0, the circuit receives two single-bit digital input stimuli Di 0  and Di 1  generated by a single-bit software Sigma-Delta modulator. The digital stimuli Di 0 b and Di 1 b are the converse logic signals of the Di 0  and Di 1  respectively. So, the switches S 11  to S 1 C, the capacitors Cp 0  and Cn 0 , the switches S 21  to S 2 C, the capacitors Cp 1  and Cn 1 , and the operational amplifier conceptually comprise two one-bit digital-to-charge converters for producing the test stimuli for the second-order Sigma-Delta modulator. Let the digital stimuli Di 0  and Di 1  be the same bit-streams with proper delays, the whole circuit under test with the reconfigurable input switched-capacitor circuit is equivalent to having the test stimulus Di 0  passing through a finite impulse response low pass filter. According to the above-mentioned, a stimulus more similar to the traditional analog one can be gained for increasing the test accuracy. 
   Additionally, all the capacitors, operational amplifiers and most of the analog switches are shared in the two operation modes in the present invention, so high measurement accuracy can be achieved. Also, since all the elements are stimulated, high fault coverage can be reached. Moreover, the capacitive loadings of the operational amplifiers in the normal mode are exactly the same with those in the test mode so that this circuit has the capability of performing at-speed tests in the test mode. 
   The present invention can be put in use of various architectures and orders of the Sigma-Delta modulators. All the analog-signal-receiving input switched-capacitor circuits, which are built in either the single-loop or the cascaded architectures, can be replaced by the present invention. Practically, all the input circuits of any kind of the switched-capacitor circuit may be substituted by the present invention to attain the goal of the low-cost test with pure digital stimuli, which substitutes for the traditional high-priced analog stimuli. 
   The circuit connection of a third-order Sigma-Delta modulator is going to be introduced in  FIG. 17 . It has the same input circuit as the second-order one has. As a result, their operation methods are similar. The application of the present invention in a switched-capacitor low pass filter is illustrated in  FIG. 18 . Replacing the input circuit of this second-order low pass filter as the present invention to accomplish the target of low-cost test with pure digital stimuli substituting for the high-priced analog stimuli. Coming to the same things as mentioned above, for the operation modes of the switched-capacitor low pass filter, there is no difference from the second-order Sigma-Delta modulator. 
   In conclusion, the present invention takes the Sigma-Delta modulation as the basis and is suitable for any architecture with switched-capacitor input circuits to make it digitally testable. Via controlling the digital mode signal T, the switched-capacitor circuit under test is determined to operate either in a normal mode or in a test mode. In the normal mode, the circuit receives an analog signal; in the test mode, the input circuit of the switched-capacitor CUT is reconfigured as a digital-test-stimulus-received digital-to-charge converter or more than two ones in parallel so that the high-priced analog stimulus generator may be replaced to reduce the cost of testing. 
   While the embodiments of the present invention are illustrated and described, various modifications and improvements can be made by persons skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications, which maintain the spirit and realm of the present invention, are within the scope as defined in the appended claims.