Abstract:
A ring oscillator circuit having an odd plurality of inverter stages (i.e., 2N+1 stages). In accordance with one embodiment of the present invention, only one of the inverter stages is operated in response to a variable input voltage, while the remaining inverter stages are operated in response to a highly filtered constant input voltage. The inverter stages that operate in response to the constant input voltage oscillate at a base frequency. The inverter stage that operates in response to the variable input voltage causes the frequency of the output signal to deviate from the base frequency by an amount determined by the variable input voltage. In this manner, the variable voltage inverter stage implements frequency control for the ring oscillator. The gain of the ring oscillator circuit is reduced by a factor of (2N+1) with respect to the gain of a conventional ring oscillator.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a voltage controlled oscillator (VCO). More specifically, the present invention relates to a VCO that includes a ring oscillator that exhibits an improved (reduced) gain. 
         [0003]    2. Related Art 
         [0004]    Voltage controlled oscillator (VCO) circuits are typically used to create frequency modulated (FM) signals. That is, a VCO circuit provides an output signal having a frequency (f OUT ) that varies in response to changes in an input supply voltage (V IN ). VCO circuits are the main building block for frequency modulation (FM) circuits and phase locked loop (PLL) circuits. 
         [0005]    The gain (K VCO ) of a VCO circuit can be described mathematically as, K VCO =Δf OUT /ΔV IN , where Δf OUT  represents the change in the output frequency and ΔV IN  represents the change in the input voltage. To obtain a desired modulation index, the gain of a VCO circuit should be appropriately low. However, the gain of a conventional VCO is typically too high to allow a frequency modulation system to be built using only a VCO circuit. Instead, frequency modulation systems are typically constructed using a low-frequency VCO circuit and one or more multiplier circuits. The output signal provided by the low-frequency VCO circuit is multiplied to obtain the desired high frequency output signal. 
         [0006]    A ring oscillator is an inexpensive type of VCO circuit that typically has a large gain that is proportional to the frequency of operation. This causes two problems: (1) it is very difficult to achieve wide bandwidth frequency modulation with a reasonable input voltage, and (2) for a certain frequency modulation index, a small signal may be needed at the input, thereby reducing the signal-to-noise ratio, resulting in undesirable phase noise. 
         [0007]      FIG. 1  is a block diagram of a conventional ring oscillator circuit  100 . Ring oscillator  100  includes an odd number of identical inverting amplifier stages  10   1 - 10   2N+1 . In the described examples, the odd number of stages is represented by the value (2N+1), wherein N is an integer greater than or equal to 1. The frequency control input terminal of each amplifier stage is connected to receive a control voltage V IN  from a common point P. Capacitor  20 , which has a capacitance C f , implements noise filtering of the control voltage V IN . Ring oscillator  100  draws a total current I P , which is equal to the sum of the currents I N  through each of the 2N+1 inverting amplifier stages. 
         [0008]      FIG. 2  is a circuit diagram illustrating conventional inverting amplifier stages  10   1  and  10   2 , which are implemented by CMOS inverters that include PMOS transistors  201 - 202  and NMOS transistors  203 - 204 . The current consumption of each of the inverting amplifier stages  10   1 - 10   2N+1  can be represented by the following equation, 
         [0000]        I   N   =C*f*V   IN   (1) 
         [0000]    wherein ‘C’ represents the total node capacitance between two of the CMOS inverters (i.e., the sum of the PMOS and NMOS gate and drain capacitances), ‘f’ represents the frequency of the output signal provided by each of the inverting amplifier stages, and V IN  represents the voltage swing of the output signal provided by each of the inverting amplifier stages. 
         [0009]    Within each CMOS amplifying inverter stage, the PMOS transistor (e.g., PMOS transistor  201 ) is typically designed to have the same threshold voltage (V T ) and the same β value as the associated NMOS transistor (e.g., NMOS transistor  203 ). Note that the β value of a transistor is defined as μ*C OX *W/L, wherein μ is the mobility of the transistor, C OX  is the gate capacitance of the transistor, W is the width of the transistor, and L is the length of the transistor. In this case, the current consumption (I N ) of each CMOS amplifying inverter stage can also be represented by the following equation. 
         [0000]        I   N =β*(0.5 *V   IN   −V   T ) 2   (2) 
         [0010]    Note that Equation (2) assumes that transitions in each inverting amplifier stage occur while the associated PMOS and NMOS transistors operate in a saturation condition, such that Equation (2) represents an approximation of transistor drain current. Equation (2) further relies on the fact that each transition occurs around ½ the input voltage V IN . 
         [0011]    Because there are 2N+1 identical CMOS inverters operating in an identical manner, the total current (I P ) drawn by ring oscillator circuit  100  is equal to the sum of the currents of the inverting amplifier stages. This relationship can be represented by the following equation. 
         [0000]        I   P =(2 N+ 1)* I   N   (3) 
         [0012]    Combining Equations (1) and (3) results in the following equation. 
         [0000]        I   P =(2 N+ 1)*( C*f*V   IN )  (4) 
         [0013]    Similarly, combining Equations (2) and (3) results in the following equation. 
         [0000]        I   P =(2 N+ 1)*β*(0.5 *V   IN   −V   T ) 2   (5) 
         [0014]    Taking the partial derivative of Equation (4) with respect to the input voltage V IN  yields the following equations. 
         [0000]      ∂ I   P   /∂V   IN   =∂/∂V   IN ((2 N+ 1)* C*f*V   IN )  (6) 
         [0015]    Because only the frequency f and the input voltage V IN  vary with respect to changes in the input voltage V IN , Equation (6) can be simplified as follows. 
         [0000]      ∂ I   P   /∂V   IN =(2 N+ 1)* C*V   IN   *∂f/∂V   IN +(2 N+ 1)* C*f*∂V   IN   /∂V   IN   (7) 
         [0000]      ∂ I   P   /∂V   IN =(2 N+ 1)* C*V   IN   *∂f/∂V   IN +(2 N+ 1)* C*f   (8) 
         [0016]    Similarly, taking the partial derivative Equation (5) with respect to the input voltage V IN  yields the following equations. 
         [0000]      ∂ I   P   /∂V   IN   =∂/∂V   IN ((2 N+ 1)*β*(0.5 *V   IN   −V   T ) 2 )  (9) 
         [0000]      ∂ I   P   /∂V   IN =(2 N+ 1)*β*∂/∂ V   IN (0.25 *V   IN   2   −V   IN   *V   T   +V   T   2 )  (10) 
         [0000]      ∂ I   P   /∂V   IN =(2 N+ 1)*β*(0.5 *V   IN   −V   T +0)  (11) 
         [0000]      ∂ I   P   /∂V   IN =(2 N+ 1)*β*(0.5 *V   IN   −V   T )  (12) 
         [0017]    Combining Equations (8) and (12) results in the following equation. 
         [0000]      β*(0.5 *V   IN   −V   T )= C*V   IN   *∂f/∂V   IN   +C*f   (13) 
         [0018]    Solving Equation (13) for ∂f/∂V IN  results in the following equation, which represents the gain (K 100 ) of ring oscillator  100 . 
         [0000]      ∂ f/∂V   IN =[β*(0.5 *V   IN   −V   T )− C*f ]/( C*V   IN )= K   100   (14) 
         [0019]    The gain K 100  represented by Equation (14) is undesirably high for certain applications such as frequency modulation. This high gain results in the undesirable operating characteristics described above. It would therefore be desirable to have an improved ring oscillator circuit that exhibits a reduced gain with respect to ring oscillator  100 . It would further be desirable if such an improved ring oscillator does not require the use of excessive additional circuitry. 
       SUMMARY 
       [0020]    Accordingly, the present invention provides a ring oscillator circuit having an odd plurality of inverter stages (i.e., 2N+1 stages). In accordance with one embodiment of the present invention, only one of the inverter stages is operated in response to a variable input voltage (V IN ), while the remaining inverter stages are operated in response to a highly filtered constant input voltage (V C ). The inverter stages that operate in response to the constant input voltage oscillate at a base frequency. The inverter stage that operates in response to the variable input voltage causes the frequency of the output signal to deviate from the base frequency by an amount determined by the variable input voltage. In this manner, the variable voltage inverter stage implements frequency control for the ring oscillator. 
         [0021]    The gain of the ring oscillator circuit of the present invention is reduced by a factor of (2N+1) with respect to the gain K 100  of conventional ring oscillator  100 . The low gain of the ring oscillator circuit of the present invention enables direct wideband frequency modulation (without requiring separate multiplier circuits). The low gain of the ring oscillator circuit of the present invention also reduces phase noise and allows complex PLL bandwidth adjustments. 
         [0022]    The present invention will be more fully understood in view of the following description and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0023]      FIG. 1  is a block diagram of a conventional ring oscillator circuit. 
           [0024]      FIG. 2  is a circuit diagram illustrating conventional CMOS inverting amplifier stages present in the ring oscillator circuit of  FIG. 1 . 
           [0025]      FIG. 3  is a block diagram of a reduced-gain ring oscillator circuit in accordance with one embodiment of the present invention. 
           [0026]      FIG. 4  is a circuit diagram of a voltage control circuit used in the ring oscillator circuit of  FIG. 3  in accordance with one embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]      FIG. 3  is a block diagram of a ring oscillator circuit  300  in accordance with one embodiment of the present invention. Ring oscillator circuit  300  includes an odd number of identical inverting amplifier stages  30   1 - 30   2N+1 . In the described examples, the odd number of stages is represented by the value (2N+1), wherein N is an integer greater than or equal to 1. In the described embodiments, inverting amplifier stages  30   1 - 30   2N+1  are identical CMOS inverters, of the type illustrated in  FIG. 2  above. Thus, each of the CMOS inverting amplifier stages  30   1 - 30   2N+1  includes at least one PMOS transistor and at least one NMOS transistor. These PMOS and NMOS transistors are designed to have the same threshold voltage (V T ) and the same β value. Moreover, the total node capacitance (C) between each pair of connected CMOS inverting amplifier stages  30   1 - 30   2N+1  is the same. 
         [0028]    The frequency control input terminal of inverting amplifier stage  30   1  is connected to receive a variable input voltage V IN  from voltage control circuit  310 . Thus, the output signal provided by inverting amplifier stage  30   1  has a full voltage swing of V IN . The current drawn by inverting amplifier stage  30   1  is designated as current I IN . 
         [0029]    The current consumption of the inverting amplifier stage  30   1  can be represented by each of the following equations. 
         [0000]        I   IN   =C*f*V   IN   (15) 
         [0000]        I   IN =β*(0.5 *V   IN   −V   T ) 2   (16) 
         [0030]    Equation (16) assumes that transitions in inverting amplifier stage  30   1  occur while the associated PMOS and NMOS transistors operate in a saturation condition, and that each transition occurs around ½ the input voltage V IN . 
         [0031]    The frequency control input terminals of inverting amplifier stages  30   2 - 30   2N+1  are connected to receive a constant input voltage V C  from voltage control circuit  310 . Capacitor  35 , which has a capacitance C F , implements noise filtering of the constant input voltage V C . The output signals provided by inverting amplifier stages  30   2 - 30   2N+1  have a full voltage swing of V C . Each of the identical inverting amplifier stages  30   2 - 30   2N+1  draws an identical current, which is designated as current I N . The current I N  consumed by each of the inverting amplifier stages  30   2 - 30   2N+1  can be represented by each of the following equations. 
         [0000]        I   N   =C*f*V   C   (17) 
         [0000]        I   N =β*(0.5 *V   C   −V   T ) 2   (18) 
         [0032]    Note that frequency ‘f’, represents the same value in Equations (15) and (17). That is, each of the inverting amplifier stages  30   1 - 30   2N+1  provides an output signal having the same frequency. 
         [0033]    The total current (I C ) drawn by the 2N inverting amplifier stages  30   2 - 30   2N+1  is equal to 2N*I N . The total current (I P ) drawn by ring oscillator circuit  300  is equal to the sum of currents I IN  and I C . The total current I P  can therefore be represented by the following equation. 
         [0000]        I   P   =I   IN +(2 N )* I   N   (19) 
         [0034]    Combining Equations (15), (17) and (19) results in the following equation. 
         [0000]        I   P   =C*f*V   IN +(2 N )* C*f*V   C   (20) 
         [0035]    Similarly, combining Equations (16), (18) and (19) results in the following equation. 
         [0000]        I   P =β*(0.5 *V   IN   −V   T ) 2 +(2 N )*β*(0.5 *V   C   −V   T ) 2   (21) 
         [0036]    Taking the partial derivative of Equation (20) with respect to the input voltage V IN  yields the following equation. 
         [0000]      ∂ I   P   /∂V   IN   =∂/∂V   IN ( C*f*V   IN )+∂/∂ V   IN (2 N*C*f*V   C )  (22) 
         [0037]    Because only the frequency f and the input voltage V IN  vary with respect to changes in the input voltage V IN , Equation (22) can be simplified as follows. 
         [0000]      ∂ I   P   /∂V   IN   =C*V   IN   *∂f/∂V   IN   +C*f*∂V   IN   /∂V   IN +2 N*C*V   C   *∂f/∂V   IN   (23) 
         [0000]      ∂ I   P   /∂V   IN   =C*V   IN   *∂f/∂V   IN   +C*f+ 2 N*C*V   C   *∂f/∂V   IN   (24) 
         [0038]    Taking the partial derivative of Equation (21) with respect to the input voltage V IN  yields the following equations. 
         [0000]      ∂ I   P   /∂V   IN =β*(0.5 *V   IN   −V   T ) 2   ∂/∂V   IN +(2 N )*β*∂/∂ V   IN (0.5 *V   C   −V   T ) 2   (25) 
         [0000]      ∂ I   P   /∂V   IN   =β*∂/∂V   IN (0.25 *V   IN   2   −V   IN   *V   T   +V   T   2 )+(2 N )*β*∂/∂ V   IN (0.25 *V   C   2   −V   C   *V   T   +V   T   2 )  (26) 
         [0000]      ∂ I   P   /∂V   IN =β*(0.5 *V   IN   −V   T +0)+(2 N )*β*(0−0+0)  (27) 
         [0000]      ∂ I   P   /∂V   IN =β*(0.5 *V   IN   −V   T )  (28) 
         [0039]    Combining Equations (24) and (28) provides the following equation. 
         [0000]      β*(0.5 *V   IN   −V   T )= C*V   IN   *∂f/∂V   IN   +C*f+ 2 N*C*V   C   *∂f/∂V   IN   (29) 
         [0040]    Solving Equation (29) for ∂f/∂V IN  results in the following equation, which represents the gain (K 300 ) of ring oscillator circuit  300 . 
         [0000]      ∂ f/∂V   IN =[β*(0.5 *V   IN   −V   T )− C*f ]/( C*V   IN +2 N*C*V   C )= K   300   (30) 
         [0041]    The gain K 300  of ring oscillator circuit  300  therefore has the following relationship with respect to the gain K 100  of conventional ring oscillator circuit  100 . 
         [0000]        K   100   /K   300 =( C*V   IN +2 N*C*V   C )/( C*V   IN )  (31) 
         [0000]        K   100   /K   300 =1+(2 N*V   C   /V   IN )  (32) 
         [0042]    In accordance with one embodiment of the present invention, the constant input voltage V C  is selected to provide an output signal having a predetermined base frequency of oscillation f B  (assuming that the variable input voltage V IN  has a potential equal to V C ). The variable input voltage V IN  is then varied about the constant input voltage V C  to adjust the frequency of the output signal. That is, variations in the variable input voltage V IN  cause the frequency of the output signal to vary about the base frequency f B . In this embodiment, the variable input voltage V IN  can be approximated as being equal to the constant voltage V C . This approximation enables Equation (32) to be simplified as follows. 
         [0000]        K   100   /K   300 =(1+2 N )  (33) 
         [0043]    Thus, it is seen that the gain K 300  of ring oscillator circuit  300  is less than the gain K 100  of conventional ring oscillator circuit  100  by a factor of (1+2N). For example, if ring oscillator circuits  100  and  300  each include fifteen inverting amplifier stages (i.e., N=7), then the gain K 300  of ring oscillator circuit  300  is 15 times less than the gain K 100  of ring oscillator circuit  100 . 
         [0044]    Advantageously, this reduced gain allows ring oscillator circuit  300  to implement high-frequency modulation without requiring the use of frequency multiplier circuits. The reduced gain of ring oscillator circuit  300  also enables wide bandwidth frequency modulation with a reasonable input voltage. The reduced gain of ring oscillator circuit  300  enables frequency modulation to be implemented, without requiring the use of small input voltage signals. As a result, the signal-to-noise ratio of ring oscillator circuit  300  is maintained at a level that minimizes undesirable phase noise. 
         [0045]      FIG. 4  is a circuit diagram of voltage control circuit  310  in accordance with one embodiment of the present invention. Voltage control circuit  310  provides the variable input voltage V IN  and the constant input voltage V C . Voltage control circuit  310  includes NMOS transistors  401 - 402 , PMOS transistors  403 - 404 , resistors  405 - 406 , constant current sources  411 - 414  and variable current source  415 . 
         [0046]    NMOS transistor  401  and resistor  405  are coupled in series between the V DD  voltage supply terminal and control terminal T 1 . The gate of NMOS transistor  401  is coupled to receive a bias voltage V BIAS . Constant current source  411  and variable current source  415  are connected in parallel between control terminal T 1  and ground. Thus, NMOS transistor  401  is connected in a source-follower configuration between the V DD  voltage supply terminal and control terminal T 1 . Control terminal T 1  is also coupled to the gate of PMOS transistor  403 . PMOS transistor  403  is connected in a source-follower configuration between the ground supply terminal and constant current source  413 . The variable input voltage V IN  is provided at the source of PMOS transistor  403 . 
         [0047]    Similarly, NMOS transistor  402  and resistor  406  are coupled in series between the V DD  voltage supply terminal and control terminal T 2 . The gate of NMOS transistor  402  is coupled to receive a bias voltage V BIAS . Constant current source  412  is connected between control terminal T 2  and ground. Thus, NMOS transistor  402  is connected in a source-follower configuration between the V DD  voltage supply terminal and control terminal T 2 . Control terminal T 2  is also coupled to the gate of PMOS transistor  404 . PMOS transistor  404  is connected in a source-follower configuration between the ground supply terminal and constant current source  414 . The constant input voltage V C  is established at the source of PMOS transistor  404 . Due to the cascaded source-follower transistors  402  and  404 , the constant input voltage V C  will be approximately equal to the bias voltage V BIAS . 
         [0048]    The gates of NMOS transistors  401  and  402  are commonly coupled to receive a bias voltage V BIAS . NMOS transistors  401  and  402  are sized such that NMOS transistor  402  is 2*N times as large as NMOS transistor  401 . Resistors  405  and  406  are sized such that the resistance of resistor  406  is 1/(2N) times the resistance of resistor  405 . The constant current source  412  is sized to draw a current that is 2*N times the current drawn by constant current source  411 . PMOS transistors  403  and  404  are sized such that PMOS transistor  404  is 2*N times as large as PMOS transistor  403 . The constant current source  414  is sized to draw a current that is 2*N times the current drawn by constant current source  413 . 
         [0049]    Variable current source  415  is initially controlled to draw no current. The above-described scaling of the various circuit elements causes the variable input voltage V IN  to be equal to the constant input voltage V C  under these conditions. Adjusting the bias voltage V BIAS  will adjust both the variable input voltage V IN  and the constant input voltage V C , thereby adjusting the base frequency f B  of ring oscillator circuit  300 . The bias voltage V BIAS  is held at a constant value after the base frequency f B  has been selected. 
         [0050]    After the desired base frequency has been selected, the variable current source  415  may be adjusted to draw (or supply) current. Adjusting the current (I V ) of variable current source  415  will adjust the voltage on the gate of PMOS transistor  403 , thereby adjusting the variable voltage V IN  provided on the source of PMOS transistor  403 . When current is drawn by variable current source  415 , the adjusted voltage V IN  will perturb the oscillation of ring oscillator circuit  300  with a gain that is (1+2N) less than conventional ring oscillator circuit  100 . The voltage shift due to the gate-to-source voltage of PMOS transistor  404  is typically compensated by a phase locked loop (PLL), in which the ring oscillator circuit  300  is used. 
         [0051]    In other words, assuming the voltages at the sources of NMOS transistors  401  and  402  are same due to the fact that their gate voltages are same (V BIAS ) and the drain currents and the sizes of these NMOS transistors are scaled perfectly, then the current I of current source  411  and the current I*2N of current source  412  result in the same voltage drop across the resistance R of resistor  405  and the resistance R/(2N) of resistor  406 , respectively, if the variable current I V  is zero. Therefore, the voltages at the gates and the sources of PMOS transistors  403  and  404  expected to be the same because the sizes and drain currents of these PMOS transistors  403  and  404  are scaled perfectly. Any non-zero I V  current introduced by variable current source  415  will result in an additional voltage drop of I V *R across resistor  405 , which will establish a voltage deviation at the gate of PMOS transistor  403  with respect to the voltage at the gate of PMOS transistor  404 , and will be reflected to the variable input voltage V IN  directly. 
         [0052]    Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. For example, although the present invention has been described in connection with a ring oscillator having a single inverter stage configured to operate in response to a variable control voltage, and the remaining inverter stages configured to operate in response to a constant control voltage, it is understood that in other embodiments, more than one inverter stage may be configured to operate in response to the variable control voltage. However, it is understood that each additional inverter stage configured to operate in response to the variable control voltage will undesirably increase the gain of the ring oscillator circuit. Moreover, although the present invention has been described as a current controlled oscillator that changes the output frequency in response to a varying current input (I V ), it is understood that the variable current source  415  can be replaced with a voltage-to-current converter, thereby enabling the output frequency to be changed in response to a varying input voltage, thereby keeping the voltage controlled oscillator concept intact. Thus, the invention is limited only by the following claims.