Abstract:
According to the invention, a circuit that is capable of automated scan testing is disclosed. Included in the circuit are a cryptographic engine, a digital circuit, an input pin, and an output pin. The cryptographic engine capable of performing at least one of encryption and decryption of one or more digital signals. The digital circuit includes combinatorial logic and a number of memory cells. The memory cells have scan inputs connected serially in a scan chain. The input pin and output pin are coupled to the scan chain. At least one of the input pin and the output pin carries at least some cipher text data of the scan chain.

Description:
[0001]    This application claims the benefit of U.S. Provisional Application Serial No. 60/377,551 filed on May 3, 2002, which is incorporated by reference in its entirety. 
     
    
     
       BACKGROUND OF THE INVENTION  
         [0002]    This invention relates in general to electronic circuits and, more specifically, to automated testing of electronic circuits with scan chains.  
           [0003]    Scan circuitry is used to test digital integrated circuits and circuit cards. Internal scan allows serially shifting an input scan signal into a scan chain of F/Fs of a digital integrated circuit to load them with an initial state. Once loaded, the integrated circuit can be clocked in the normal operational mode. Once normal operation stops, an output scan signal can be read out of the scan chain for analysis to confirm proper operation of the integrated circuit. Similarly, circuit card wiring can be tested using boundary scan techniques that test an integrated circuit input/output pins.  
           [0004]    Testing of digital integrated circuits can be performed overseas and/or in test facilities with varying levels of security. Some organizations only allow the digital circuits they use to be tested domestically. Some feel the inputs and/or outputs to the internal or boundary scan chains could be used to gain information about the circuits that they test. Physical security measures are conventionally used to protect the test vectors from exploitation. For example, the test vectors and circuit testers that store them are available to a limited set of individuals. Physical security and screening is generally seen as being exploitable. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    The present invention is described in conjunction with the appended figures:  
         [0006]    [0006]FIG. 1 is a block diagram of an embodiment of a circuit test system;  
         [0007]    FIGS.  2 A-H are block diagrams that each show an embodiment of a portion of a device under test (DUT);  
         [0008]    FIGS.  3 A-C are block diagrams that each show an embodiment of an encryption circuit;  
         [0009]    [0009]FIG. 4 is a flow diagram of an embodiment of a process for testing the DUT; and  
         [0010]    [0010]FIG. 5 is a timing chart of an embodiment of a test scenario.  
     
    
       [0011]    In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0012]    The ensuing description provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the invention. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the invention. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the invention as set forth in the appended claims.  
         [0013]    Referring first to FIG. 1, a block diagram of an embodiment of a circuit test system  100  is shown. The test system  100  is used to confirm the device under test (DUT) is functioning properly. This testing could be for debug of the DUT, production testing, etc. Included in the circuit test system  100  are a design workstation  104 , a circuit tester  108 , the DUT  112 , input test vectors  116 , and output test vectors. The DUT  112  is typically inserted into a DUT carrier that is part of the circuit tester  108 . Automated systems may allow many DUT  112  to be loaded for serially testing each. The DUT  112  could be a bare die, a packaged integrated circuit (IC), a hybrid package of multiple ICs, a circuit card with one or more ICs, a module with one or more circuit cards, a system of modules, or any other configuration of circuits. The DUT  112  includes a cryptographic function capable of encryption, decryption and/or a hash function.  
         [0014]    The circuit tester  108  applies signals to the DUT  112  and reads out other signals. Configuration information and the input test vectors  116  command the circuit tester  108  on how to stimulate the DUT  112 . That stimulus causes the output signals of the DUT  112  to react. Those reactions are recorded by the circuit tester  108  and stored as output test vectors. The circuit tester  108  may also compare the output test vectors against a set of expected test vectors  124  such that a conclusion can be reached by the tester  108  on whether the DUT  112  is functioning properly.  
         [0015]    The design workstation  104  may have many functions and is used to create the input test vectors  116  and the expected test vectors  124 . In many cases, the design workstation  104  has a logical model of the DUT  112  that is used to produce test vectors. The logical model would be capable of encrypting the scan signal in the same way as the DUT such that an expected test vector could be generated in a deterministic way. Some embodiments, could encrypt the input test vectors  116  with the design workstation  104  using a public or private key. The DUT would decrypt those input test vectors  116  prior to loading them into the flip-flops (F/F) of the scan chain such that the input stimulus is deterministic.  
         [0016]    The input test vectors  116  could be used to load seeds, DUT serial number, keys, and other initialization into the DUT  112 . The input test vectors could be customized in part or wholly for each DUT  112  and could be in plain or cipher text form. For example, wholly or partially encrypted test vectors could be prepared for a particular DUT  112  which has a unique key stored in the DUT. A label on the DUT could be used that matches the DUT serial number loaded by the input test vectors  116 .  
         [0017]    With reference to FIGS.  2 A-H, block diagrams that each show an embodiment of a portion of a DUT  112  are depicted. The depicted portion may be all or a portion of the DUT. Referring first to FIG. 2A, a single internal scan chain DUT  112 - 1  is shown that can selectively-decrypt, selectively-encrypt and/or selectively-hash a scan signal. Included in the DUT  112 - 1  are a circuit block  204 , a number of switches  208 , an encryption circuit  212 , a bypass circuit  216 , a decryption circuit  220 , and a scan interface  224 . Some embodiments of the DUT  112  could include any number of separate scan chains even though this embodiment only includes a single scan chain.  
         [0018]    The circuit block  204  is typically a combination of F/Fs or registers (i.e., a combination of memory cells) and combinatorial logic. The F/Fs and registers of the circuit block  204  are serially connected in an internal scan chain. The scan interface  224  receives a scan signal specified in the input test vectors  116 . A first switch  208 - 1  is used to either couple the scan signal to the decryption circuit  220  or bypass  216  the decryption circuit. In this way, some of the scan signal may be decrypted and some may not. A bit in each input test vector can be used to selectively activate decryption with the first switch  208 - 1 . In this embodiment, the decryption circuit uses serial decryption and encryption.  
         [0019]    Once the scan signal is in completely plain text form, it is fed into the circuit block  204 . The registers and F/Fs of the circuit block  204  are loaded in serial fashion with these initial values. A CAPTURE signal is activated to clock the circuit block  204  in normal operation. Once normal operation ends and the CAPTURE signal is deactivated, the scan chain in the circuit block  204  is unloaded in a serial fashion. A second switch  208 - 2  is used to selectively encrypt or hash the output scan signal by alternatively using the encryption circuit  212  or the bypass  216 . The output scan signal, which may be partially or wholly encrypted/hashed, is passed out the scan interface  224  to register as part of an output test vector  120 . Using a hash output allows verifying the circuit block  204  is likely functioning properly even thought the one-way nature of a hash function does not allow retrieving the plain-text version of the output scan signal.  
         [0020]    With reference to FIG. 2B, another embodiment of the DUT  112 - 2  is shown. This embodiment includes a number of scan chains for a number of circuit blocks  204 . There are a number of input scan signals that are driven by the input test vectors  116  in parallel fashion. The first switch  208  can individually turn off or on decryption for each scan signal. The decryption circuit  220  could decrypt each signal with a serial algorithm or could decrypt a number of input scan signals with a block algorithm. For example, there could be sixty-four input scan signals which each provide a bit for the block decryption.  
         [0021]    The plain text input scan signals are loaded into their respective circuit blocks  204 . In this embodiment, there is one scan signal per circuit block  204 . After normal operation with an active CAPTURE signal, clocking of the circuit blocks  204  continues such that the multiple scan chains are shifted out in serial fashion. The second switch bank  208  can selectively manipulate the different output scan signals. For example, four output scan signals could be wholly or partially encrypted while the remainder stay in the clear. The encryption circuit  212  can use either a serial or block algorithm.  
         [0022]    The embodiment  112 - 3  of FIG. 2C is similar to that of FIG. 2B except none of the input scan signals are decrypted. In FIG. 2D, another embodiment  112 - 4  is shown that encrypts all output scan signals. FIG. 2E shows an embodiment  112 - 5  that encrypts some output scan signals while others remain in the clear. In other words, a single output scan signal cannot be selectively encrypted. In the embodiment  112 - 6  of FIG. 2F, some whole input scan signals are decrypted while others are not. Also, some whole output scan signals are encrypted or hashed while others are not. A particular chain may have any permutation of encryption, decryption and/or hashing.  
         [0023]    The embodiments  112 - 7 ,  112 - 8  of FIGS. 2G and 2H relate to embodiments that have multiple ICs. These ICs could be in the same package or in different packages on the same or a different circuit board. In FIG. 2G, three circuit blocks in different ICs  204  have their scan chains connected in a serial fashion. Decryption and encryption circuits  220 ,  212  could be in separate ICs, the same IC or integrated into the same IC as one of the circuit blocks  204 . This embodiment  112 - 7  has bypass  216  for whole scan signals, but other embodiments could have partial scan signal bypass options.  
         [0024]    Referring to FIG. 2H, this embodiment  112 - 8  tests both internal and boundary scan. The internal scan of the first circuit  204 - 1  is connected to the boundary scan chain  228  and the second circuit  204 - 2 . In this way, boundary scan chains could be encrypted also. Some embodiments could test the boundary scan interface with possible cryptography without also linking through internal scan chains. Further, boundary scan chains for multiple chip packages, circuit cards and modules could be daisy-chained together in any combination to test those circuit assemblies.  
         [0025]    Referring next to FIG. 3A, a block diagram of an embodiment of an encryption circuit  212 - 1  is shown. This embodiment of the encryption circuit  212 - 1  performs block encryption. A word expansion block  308  takes the output scan signals and replicates some to achieve a block that has the word size of a block crypto engine. For example, where sixty-four bit blocks are encrypted by the block crypto engine  304  and only thirty-two output scan signals are input to the word expansion block  308 , each output scan signal would be replicated to achieve sixty-four bit blocks for encryption.  
         [0026]    The bits of the output scan signals could be expanded in any fashion. For example, some bits could be replicated twice, some could not be replicated at all and some could be replicated four times to achieve input into each bit of the block. The bit positions that the replicated signals were assigned to could be manipulated. The expansion process could be programmable such that different test scenarios could be expanded in different ways. Each bit input to the word expansion block  308  could be assigned to one or more output bit positions in a customizable way. Input test vectors  116  could be used to configure the word expansion block.  
         [0027]    Some embodiments may have a set algorithm for expansion based upon the active input bits that does not require configuration. Arithmetic functions could be performed on the input bits also, for example, an expanded output bit is the exclusive-OR of one or more input bits. Some embodiments could determine when an output scan signal is bypassing the encryption circuit  212 - 1  and expand another bit in its place. Although this embodiment uses bit replication or algorithmic bit replication, other embodiments could simply use bit stuffing to achieve a block of the proper size.  
         [0028]    The block crypto engine  304  is resident in the DUT  112 . The crypto engine  304  could also be capable of decryption and could use word expansion during decryption. Various crypto algorithms could be used by the block crypto engine that are either private or public key, for example, RSA, DES, triple DES, AES, etc. This embodiment receives its seed key from the expanded output scan chains. Beyond the first encryption, the output cipher text is used to influence the key by use of the OR-gate  312  in a form of CBC chaining. Although this embodiment uses a block encryption circuit  212 - 1 , others could use a serial encryption circuit. When encrypting the output test signal, a hash function could be used instead.  
         [0029]    The block crypto engine  304  could use a one-way function or hash when processing the output scan signals. The actual values of the scan chain registers and F/Fs is often not necessary in production testing, but verifying a hash output would verify proper operation in most circumstances. Although the present embodiment produces a output scan signal for each test vector cycle, the CBC chaining requires only periodic checking of the output test vectors  120  as an error in one test would influence the encryption process for all future output as the cipher text output is fed back as the key input.  
         [0030]    With reference to FIG. 3B, a block diagram of another embodiment of an encryption circuit  212 - 2  is shown. This embodiment uses an exclusive OR or XOR gate  316  for the CBC chaining. Other embodiments could use any logic gate that combines components from the plain text input to and cipher text output of the block crypto engine  316 .  
         [0031]    Referring next to FIG. 3C, a block diagram of yet another embodiment of an encryption circuit  212 - 3  is shown. This embodiment does not use CBC chaining on the key input, but does use CBC chaining for the plain text input. An XOR gate  316  is used to combine elements from the cipher text output and plain text input for the encryption process. The key input to the block crypto engine  304  could be a preset key in this embodiment, a series of preset keys, a key loaded from the test vectors, or a key generated elsewhere in the DUT  112 . Some embodiments could use a predetermined key for the first cryptographic operation and then use some combination of plain/cipher text.  
         [0032]    With reference to FIG. 4, a flow diagram of an embodiment of a process  400  for testing the DUT  112  is shown. The depicted portion of the process  400  begins in step  404  where the design workstation  104  is used to produce the input test vectors  116  and expected test vectors  124 . An ATPG tool with a logical model of the DUT could be used for this purpose. The test vectors  116 ,  124  are provided to the circuit tester along with configuration information for the test protocol. In step  408 , the DUT  112  is loaded into the circuit tester  108 . Automated mechanisms could be used to quickly load and unload one or more DUTs  112 .  
         [0033]    The input test vectors  116  are read by the circuit tester  108  and applied to the input pins of the DUT  112  according to the test protocol. This loads the one or more input scan signals into their scan chains in step  412 . The first switch  208 - 1  is manipulated to achieve partial or whole decryption for each input scan signal. Once all the registers and F/F for a circuit block  204  are loaded. Normal operation of the circuit block  204  is activated in step  416  by activating the CAPTURE signal that stops the serial shifting and begins normal operation on the next clock pulse. After deactivating the CAPTURE signal, the scan chains are shifted out in step  420  with manipulation of the second switch  208 - 8  for partial or whole encryption of the output scan chains.  
         [0034]    In step  424 , the expected output vectors  124  are tested against the actual output vectors  120  to confirm proper operation of the DUT  112 . If errors are determined in step  428 , the error is noted in step  434  and the testing could be aborted as defined by the test protocol. Where there is no error in step  428 , a second determination is made by the tester  108 . If there are more input test vectors  116 , processing loops back to step  412 . Where there no more input test vectors  116 , this portion of the testing for the DUT  112  is complete.  
         [0035]    Referring next to FIG. 5, a timing chart  500  of an embodiment of a test scenario is shown. In this embodiment, the first and second switches  208  have a single input to encrypt all scan signals when activated. A SCAN_IN signal  508  loads the input scan signals and a SCAN_OUT signal  516  reads out the output scan signals as depicted with a series of words in the chart  500 . A CLOCK signal  512  is used to sample the SCAN_IN signal  508  and SCAN_OUT signal  516  as well as clock the DUT when operating in normal mode. The CAPTURE signal manipulates the CLOCK signal input to the memory registers to switch the DUT between serial scan chain shift mode and normal mode. More specifically, normal operation is enabled when the CAPTURE signal is active and scan shift operation is enabled when the CAPTURE signal is inactive. The DECRYPT signal  504  activates/deactivates decryption of all input scan signals. Similarly, the ENCRYPT signal  520  activates/deactivates encryption of all output scan signals.  
         [0036]    A number of variations and modifications of the invention can also be used. For example, some embodiments could use asynchronous or self-timed circuitry in the DUT. Asynchronous or self-timed circuits perform some or all operations without a clock to pipeline every stage in the process. Input and/or output test signals for the asynchronous circuits would exist wholly or in-part in a cipher text form outside the DUT. Any method that is used for testing, the test data outside the asynchronous DUT can be encrypted.  
         [0037]    While the principles of the invention have been described above in connection with specific apparatuses and methods, it is to be clearly understood that this description is made only by way of example and not as limitation on the scope of the invention.