Abstract:
Read only memory(ROM) integrated circuit devices include a ROM cell block. A plurality of virtual ground lines and bit lines are coupled to the ROM cell block. A precharge circuit, including a virtual ground line precharge controller, virtual ground line precharging unit, bit line precharge controller and bit line precharging unit, independently controls timing of precharging the virtual ground lines and the bit lines. The precharge circuit may be configured to deactivate precharging of the virtual ground lines before deactivating precharging of the bit lines. Precharging of the virtual ground lines may be deactivated substantially concurrently with activation of discharging of the virtual ground lines.

Description:
RELATED APPLICATION  
       [0001]     This application is a continuation in part of U.S. patent application Ser. No. 10/406,476, filed Apr. 3, 2003 entitled “READ ONLY MEMORY DEVICES WITH INDEPENDENTLY PRECHARGED VIRTUAL GROUND AND BIT LINES AND METHODS FOR OPERATING THE SAME,” the disclosure of which is incorporated herein by reference as if set forth in its entirety, and claims priority to Korean Patent Application 2002-41975 filed on Jul. 18, 2002, the contents of which are herein incorporated by reference in their entirety. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to integrated circuit memory devices, and in particular to read only memory (ROM) devices having virtual ground and bit lines.  
         [0003]     A ROM integrated circuit device includes a ROM storage cell block including storage cells. Bit lines from the storage cells are used to output data from the storage cells during a read operation. Such devices may also include virtual ground lines that may be positioned adjacent the bit lines on the integrated circuit device. As integration density of the device increases, the widths and lengths of lines formed in the integrated circuit device generally are reduced. As a result, electrical coupling may result between adjacent ones of the virtual ground and bit lines.  
         [0004]     A variety of approaches may be taken to reduce or prevent such an electrical coupling from adversely affecting the device. For example, when the virtual ground lines and the bit lines are in a precharged state, the supply of the precharge voltage to the bit lines may be stopped when the virtual ground lines are being discharged to ground. As a result, the voltage of the bit lines may be affected by the virtual ground lines and drop to a predetermined level lower than the precharge voltage. To compensate for this drop, the supply of the precharge voltage to the bit lines is not stopped until a predetermined period of time after the virtual ground lines are grounded. Thus, the affect of the virtual ground lines on the bit lines may be reduced or eliminated.  
         [0005]     However, because the virtual ground lines and the bit lines are conventionally precharged at the same time, as described above, the precharge voltage is still applied for a predetermined period of time after the virtual ground lines are grounded. Thus, a short-circuit current may flow through the virtual ground lines and, as a result, the virtual ground lines may not be at a ground voltage level. This state may continue until the supply of the precharge voltage to the virtual ground lines stops. If the virtual ground lines are not fully grounded, the operational speed of the ROM integrated circuit device may decrease and its power consumption may increase.  
         [0006]     Accordingly, some embodiments of the present invention may provide a ROM semiconductor device that allows virtual ground lines to be fully grounded by preventing short-circuit current from flowing through the virtual ground lines when the virtual ground lines are precharged, discharged and grounded.  
       SUMMARY OF THE INVENTION  
       [0007]     According to some embodiments of the present invention, a read only memory (ROM) integrated circuit device is provided including: a ROM cell block for storing data; a plurality of virtual ground lines connected to the ROM cell block; a plurality of virtual ground line precharge controllers, each receiving a virtual ground line precharge control signal and an address control signal and outputing a virtual ground line precharge signal; a plurality of virtual ground line precharging units for precharging the plurality of virtual ground lines in response to the virtual ground line precharge signals; a plurality of bit lines connected to the ROM cell block; a plurality of bit line precharging units that precharge the plurality of bit lines in response to bit line precharge signals; and a plurality of switches connected to the plurality of virtual ground lines and for grounding the virtual ground lines in response to discharge signals.  
         [0008]     In other embodiments, when the virtual ground line precharge control signal and the address control signal are at a logic “high” level, the virtual ground line precharge signal is at a logic “low” activated level, and when either the virtual ground line precharge control signal or the address control signal is at a logic “low” level, the virtual ground line precharge signal is at a logic “high” deactivated level.  
         [0009]     When the virtual ground line precharge signal is at a logic “low” activated level, the virtual ground line precharging unit may be activated to precharge the virtual ground line, and when the virtual ground line precharge signal is at a logic “high” deactivated level, the virtual ground line precharging unit may be deactivated.  
         [0010]     In further embodiments of the present invention, the ROM integrated circuit device further includes a bit line precharge controller that receives a bit line precharge control signal and outputs the bit line precharge signals.  
         [0011]     In other embodiments, when the bit line precharage control signal is at a logic “high” level, the bit line precharge signal is at a logic “low” activated level, and when the bit line precharge control signal is at a logic “low” level, the bit line precharge signal is at a logic “high” deactivated level.  
         [0012]     When the bit line precharge signal is at a logic “low” activated level, the plurality of bit line precharging units may be activated to precharage the bit lines, and when the bit line precharge signal is at a logic “high” deactivated level, the plurality of bit line precharging units may be deactivated.  
         [0013]     In further embodiments of the present invention, the ROM integrated circuit device further includes a plurality of discharge controllers that receive a discharge control signal and an address signal and output the discharge signal.  
         [0014]     When either the discharge control signal or the address signal is at a logic “low”, the plurality of discharge controllers may output the discharge control signal at a logic “high” activated level, and when the discharge control signal and the address signal are both at a logic “high” level, the plurality of discharge controllers may output the discharge signal at a logic “low” deactivated level.  
         [0015]     When the discharge signal is at a logic “high” activated level, the switches may be activated to couple a corresponding virtual ground line to ground, and when the discharge signal is at a logic “low” deactivated level, the switches may be deactivated.  
         [0016]     In further embodiments of the present invention, a ROM integrated circuit device is also provided including: a ROM cell block for storing data; a plurality of bit lines connected to the ROM cell block; a plurality of virtual ground lines connected to the ROM cell block; a plurality of virtual ground line precharge controllers, each receiving a virtual ground line precharge control signal and an address control signal and outputing a virtual ground line precharge signal; a plurality of virtual ground line precharging units for precharging the plurality of virtual ground lines in response to the virtual ground line precharge signals and outputting bit line precharge control signals; a plurality of bit line precharge controllers, each receiving bit line precharge control signals from adjacent two virtual ground line precharging units and outputting bit line precharge signals; a plurality of bit line precharging units that precharge the plurality of bit lines in response to the bit line precharge signals; and a plurality of switches connected to the plurality of virtual ground lines and for grounding the virtual ground lines in response to discharge signals.  
         [0017]     In some embodiments of the present invention, when the virtual ground line precharge control signal and the address control signal are at a logic “high” level, the virtual ground line precharge signal is at a logic “low” activated level, and when either the virtual ground line precharge control signal or the address control signal is at a logic “low” level, the virtual ground line precharge signal is at a logic “high” deactivated level.  
         [0018]     When the virtual ground line precharge signal is at a logic “low” activated level, the virtual ground line precharging unit may be activated to precharge the virtual ground line, and when the virtual ground line precharge signal is at a logic “high” deactivated level, the virtual ground line precharging unit may be deactivated.  
         [0019]     In other embodiments, when the virtual ground line precharge signal is at a logic “low” activated level, the bit line precharge control signal is at a logic “high” level, and when the virtual ground line precharge signal is at a logic “high” deactivated level, the bit line precharge control signal is at a logic “low” level.  
         [0020]     In further embodiments, when the bit line precharage control signals input to each bit line precharge controller are both at a logic “high” level, the bit line precharge signal output from each bit line precharge controller is at a logic “low” activated level, and when either of the bit line precharge control signals input to each bit line precharge controller is logic “low” level, the bit line precharge signal output from each bit line precharge controller is at a logic “high” deactivated level.  
         [0021]     When the bit line precharge signal is at a logic “low” activated level, the plurality of bit line precharging units may be activated to precharage the bit lines, and when the bit line precharge signal is at a logic “high” deactivated level, the plurality of bit line precharging units may be deactivated.  
         [0022]     In other embodiments of the present invention, the ROM integrated circuit device further includes a plurality of discharge controllers that receive a discharge control signal and an address signal and output the discharge signal.  
         [0023]     In further embodiments, when either the discharge control signal or the address signal is at a logic “low”, the plurality of discharge controllers output the discharge control signal at a logic “high” activated level, and when the discharge control signal and the address signal are both at a logic “high” level, the plurality of discharge controllers output the discharge signal at a logic “low” deactivated level.  
         [0024]     When the discharge signal is at a logic “high” activated level, the switches may be activated to couple a corresponding virtual ground line to ground, and when the discharge signal is at a logic “low” deactivated level, the switches may be deactivated.  
         [0025]     According to some embodiments of the present invention, the operational speed of a ROM semiconductor device may increase and power consumption may decrease. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]      FIG. 1  is a block diagram illustrating a ROM integrated circuit device according to some embodiments of the present invention;  
         [0027]      FIG. 2  is a circuit diagram illustrating the first virtual ground line precharge controller and the first virtual ground line precharging unit illustrated in  FIG. 1 , according to some embodiments of the present invention;  
         [0028]      FIG. 3  is a circuit diagram illustrating the bit line precharge controller and a first bit line precharging unit illustrated in  FIG. 1 , according to some embodiments of the present invention;  
         [0029]      FIG. 4  is a circuit diagram illustrating the first discharge controller and the first switch illustrated in  FIG. 1 , according to some embodiments of the present invention;  
         [0030]      FIG. 5  is a timing diagram illustrating operations of the device illustrated in  FIG. 1 , according to some embodiments of the present invention;  
         [0031]      FIG. 6  is a block diagram illustrating a ROM integrated circuit device according to further embodiments of the present invention;  
         [0032]      FIG. 7  is a circuit diagram illustrating the first bit line precharge controller and the first bit line precharging unit illustrated in  FIG. 6 , according to some embodiments of the present invention;  
         [0033]      FIG. 8  is a circuit diagram illustrating the first bit line precharge controller and the first bit line precharging unit illustrated in  FIG. 6 , according to some embodiments of the present invention; and  
         [0034]      FIG. 9  is a timing diagram illustrating operations of the device illustrated in  FIG. 6 , according to some embodiments of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0035]     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set froth herein; rather, theses embodiments are provided so that this disclosure will be through and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or “directly coupled” to another element, there are no intervening elements present.  
         [0036]     Each embodiment described and illustrated herein includes its complementary conductivity type and/or complementary logic embodiment as well. References to source and drain of transistors herein are interchangeable and intended to encompass complementary conductivity type transistors or alternate technology type transistors except where a specific transistor type is referenced.  
         [0037]     Some embodiments of the present invention will now be further described with reference to  FIG. 1-5 .  
         [0038]      FIG. 1  is a block diagram illustrating a read only memory (ROM) integrated circuit device according to some embodiments of the present invention. As shown in  FIG. 1 , a ROM integrated circuit device  101  includes a ROM cell block  111 , virtual ground lines VGL 1 , VGL 2 , etc., bit lines BL 1 , BL 2 , etc., a sense amplifier  181 , a virtual ground line precharge controller  121 , a virtual ground line precharging units  131 ,  132 , etc., bit line precharge controller  141 , bit line precharging units  151 ,  152 , etc., discharge controllers  161 ,  162 , etc. and switches  171 ,  172 , etc.  
         [0039]     The ROM cell block  111  stores data in one or more storage cells. In the ROM cell block  111 , writing of data is not supported due to its read only configuration. The virtual ground lines VGL 1 , VGL 2 , etc. and the bit lines BL 1 , BL 2 , etc. are connected to the storage cell(s) of the ROM cell block  111 .  
         [0040]     Data stored in the ROM cell block  11  may be transmitted to the sense amplifier  181  via the bit lines BL 1 , BL 2 , etc. As will be understood by those of skill in the art, respective bit lines BL 1 , BL 2 , etc. may be associated with individual storage cell(s), such as a column of storage cells, of the ROM cell block  111 . The sense amplifier  181  amplifies the transmitted data and transmits the amplified data Dout to an external device.  
         [0041]     For the embodiments illustrated in  FIGS. 1-5 , the virtual ground line precharge controller  121  receives a virtual ground line precharge control signal VPCON and an address control signal ACON 0  and outputs a virtual ground line precharge signal VPRE 0 . When the virtual ground line precharge control signal VPCON and the address control signal ACON 0  are at a logic “high” activated level, the virtual ground line precharge controller  121  outputs the virtual ground line precharge signal VPRE 0  at a logic “low” activated level. If either of the virtual ground line precharge control signal VPCON and the address control signal ACON 0  is at a logic “low”, the virtual ground line precharge controller  121  outputs the virtual ground line precharge signal VPRE 0  at a logic “high” deactivated level.  
         [0042]     The virtual ground line precharging units  131 ,  132 , etc. precharge the virtual ground lines VGL 1 , VGL 2 , etc. in response to activation of the virtual ground line precharge signal VPRE 0  output from the virtual ground line precharge controller  121 . In other words, if the virtual ground line precharge signal VPRE 0  is at a logic “low” level, the virtual ground line precharging units  131 ,  132 , etc. are activated to precharge the virtual ground lines VGL 1 , VGL 2 , etc. When the virtual ground line precharge signal VPRE 0  is at a logic “high” level, the virtual ground line precharging units  131 ,  132 , etc. are deactivated and thus do not couple the virtual ground lines VGL 1 , VGL 2 , etc. to a precharge voltage.  
         [0043]     For the embodiments of  FIGS. 1-5 , the bit line precharge controller  141  receives a bit line precharge control signal BPCON and outputs a bit line precharge signal BPRE. When the bit line precharge control signal BPCON is at a logic “high” level, the bit line precharge controller  141  outputs the bit line precharge signal BPRE at a logic “low” activated level. When the bit line precharge control signal BPCON is at a logic “low” level, the bit line precharge controller  141  outputs the bit line precharge signal BPRE at a logic “high” deactivated level.  
         [0044]     The bit line precharging units  151 ,  152 , etc. precharge the bit lines BL 1 , BL 2 , etc. in response to the bit line precharge signal BPRE output from the bit line precharge controller  141 . In other words, if the bit line precharge signal BPRE is at a logic “low” level, the bit line precharging units  151 ,  152 , etc. are activated to couple the bit lines BL 1 , BL 2 , etc. to a precharge voltage. When the bit line precharge signal BPRE is at a logic “high” level, the bit line precharging units  151 ,  152 , etc. are deactivated and, thus, do not couple the bit lines BL 1 , BL 2 , etc. to the precharge voltage.  
         [0045]     In some embodiments of the present invention, the discharge controllers  161 ,  162 , etc. receive a discharge control signal DCON and address signals ADD 0 , ADD 1 , etc. and output discharge signals DIS 0 , DIS 1 , etc. In particular, for example, the discharge controller  161  receives the discharge signal DCON and address signal ADD 0  and outputs the discharge signal DIS 0 . If either the discharge control signal DCON or the address signal ADD 0  is at a logic “low” level, the discharge controller  161  outputs the discharge signal DIS 0  at a logic “high” activated level. If the discharge control signal DCON and the address signal ADD 0  are both at a logic “high” level, the discharge controller  161  outputs the discharge signal DIS 0  at a logic “low” deactivated level.  
         [0046]     Similarly, the discharge controller  162  receives the discharge control signal DCON and the address signal ADD 1  and outputs the discharge signal DIS 1 . If either the discharge control signal DCON or the address signal ADD 1  is at a logic “low” level, the discharge controller  162  outputs the discharge signal DIS 1  at a logic “high” activated level. When the discharge control signal DCON and the address signal ADD 1  are both at a logic “high” level, the discharge controller  162  outputs the discharge signal DIS 1  at a logic “low” deactivated level. Thus, as described above, the discharge controller  161 , 162 , etc. may be selectively activated responsive to the address signals ADD 0 , ADD 1 , etc.  
         [0047]     For the embodiments shown in  FIGS. 1-5 , the switches  171 ,  172 , etc. selectively couple the virtual ground lines VGL 1 , VGL 2 , etc. to ground responsive to the discharge signals DIS 0 , DIS 1 , etc. In other words, when the discharge signal DIS 0  is at a logic “high” level, the switch  171  is activated to ground the virtual ground line VGL 1 . When the discharge signal DIS 0  is at a logic “low” level, the switch  171  is deactivated, and, thus, the virtual ground line VGL 1  is not grounded. Similarly, when the discharge signal DIS 1  is at a logic “high” level, the switch  172  is activated to ground the virtual ground line VGL 2 . When the discharge signal DIS 1  is at a logic “low” level, the switch  172  is deactivated, and, thus, the virtual ground line VGL 2  is not grounded.  
         [0048]      FIG. 2  is a circuit diagram illustrating the virtual ground line precharge controller  121  and the virtual ground line precharging unit  131  shown in  FIG. 1  according to some embodiments of the present invention. Referring to the embodiments of  FIG. 2 , the virtual ground line precharge controller  121  includes a NAND gate which receives the virtual ground line precharge control signal VPCON and the address control signal ACON 0  as inputs and outputs the virtual ground line precharge signal VPRE 0  (i.e., generates VPRE 0  as a Boolean NAND operation of VPCON and ACON 0 ). The virtual ground line precharging unit  131  includes a PMOS transistor that has a source coupled to a power voltage VDD, a gate coupled to the virtual ground line precharge signal VPRE, and a drain coupled to the virtual ground line VGL 1 .  
         [0049]      FIG. 3  is a circuit diagram illustrating the bit line precharge controller  141  and the bit line precharging unit  151  shown in  FIG. 1  according to some embodiments of the present invention. Referring to the embodiments of  FIG. 3 , the bit line precharge controller  141  includes an inverter that receives the bit line precharge control signal BPCON and outputs the bit line precharge signal BPRE. The bit line precharging unit  151  includes a PMOS transistor that has a source coupled to the power voltage VDD, a gate coupled to the bit line precharge signal BPRE, and a drain coupled to the bit line BL 1 .  
         [0050]      FIG. 4  is a circuit diagram illustrating the discharge controller  161  and the switch  171  shown in  FIG. 1  according to some embodiments of the present invention. Referring to the embodiments of  FIG. 4 , the discharge controller  161  includes a NAND gate that receives the discharge control signal DCON and the address signal ADD 0  as inputs and outputs the discharge signal DIS 0 .  
         [0051]     The switch  171  includes a NMOS transistor that has a drain coupled to the virtual ground line VGL 1 , a gate coupled to the discharge signal DIS 0 , and a source coupled to ground.  
         [0052]      FIG. 5  is a timing diagram illustrating operations of the device  101  of  FIG. 1  according to some embodiments of the present invention. As shown in section (a) of the embodiments of  FIG. 5 , the virtual ground line-precharge signals VPREi(I=0,1,2 . . . ), the bit line precharge signal BPRE, and the discharge signal DISi are at a logic “low” level. The virtual ground lines VGLi and the bit lines Bli are precharged to a precharge voltage Vpre. As shown In section (b), the virtual ground line precharge signal VPRE and the discharge signal DISi are transitioned, substantially concurrently, to a logic “high” level, and the virtual ground lines (VGL 1 , VGL 2 , etc. shown in  FIG. 1 ) are grounded. Here, the virtual ground lines VGLi are selectively grounded depending on whether their respective address signals (ADD 0 , ADD 1 , etc. shown in  FIG. 1 ) are activated. However, as VPRE is deactivated (shown as a logic “high” level), the supply of the precharge voltage Vpre to the virtual ground lines VGLi stops substantially at the same time as when the virtual ground lines VGLi are grounded. Thus, a short-circuit condition, in which current would flow from Vpre to the virtual ground lines VGLi, may be reduced or prevented.  
         [0053]     Even though for the embodiments described above, the virtual ground lines VGLi are grounded and decoupled from the precharge voltage Vpre, the supply of the precharge voltage Vpre to the bit lines Bli (BL 1 ,BL 2 , etc. illustrated in  FIG. 1 ) is maintained. Thus, although the virtual ground lines VGLi may be adjacent to the bit lines BLi, the voltage of the bit lines Bli may not drop when the virtual ground lines VGLi are grounded. In other words, any electronic coupling effect between the virtual ground and bit lines may be reduced.  
         [0054]     As shown in section (c) of the embodiments of  FIG. 5 , the bit line precharge signal BPRE is transitioned to a logic “high” deactivated level so the virtual ground line precharge signal VPRE, the bit line precharge signal BPRE and the discharge signal DISi are still at a logic “high” level. Thus, the virtual ground lines VGLi are still selectively grounded and the supply of the precharge voltage to the bit lines BLi stops. Therefore, in section (c), data stored in the ROM cell block  111  may be read.  
         [0055]     As described above, the timing of precharging of the virtual ground lines (VGL 1 , VGL 2 , . . . shown in  FIG. 1 ) and the bit lines (BL 1 , BL 2 , . . . shown in  FIG. 1 ) may be independently controlled. Thus, when the virtual ground lines (VGL 1 , VGL 2 , . . . shown in  FIG. 1 ) are grounded, a short-circuit current may be reduced or prevented from flowing through the virtual ground lines VGLi. As a result, the operational speed of the ROM integrated circuit device  101  (illustrated in  FIG. 1 ) may be increased and power consumption may be decreased. Furthermore, when the virtual ground lines (VGL 1 , VGL 2 , . . . shown in  FIG. 1 ) are grounded, the supply of the precharge voltage Vpre to the bit lines (BLI, BL 2 , . . . shown in  FIG. 1 ) may be continued. Thus, dropping of the precharge voltage Vpre of the bit lines BLi may be reduced or prevented.  
         [0056]     Further embodiments of the present invention will now be further described with reference to  FIGS. 6-9 .  
         [0057]      FIG. 6  is a block diagram illustrating a ROM integrated circuit device according to some embodiments of the present invention. As shown in the embodiments of  FIG. 6 , a ROM integrated circuit device  601  includes a ROM cell block  611 , virtual ground lines VGL 1 , VGL 2 , etc., bit lines BL 1 , BL 2 , etc., virtual ground line precharge controllers  621 ,  622 , etc., virtual ground line precharging units  631 ,  632 , etc., bit line precharge controllers  641 ,  642 , etc., bit line precharging units  651 ,  652 , etc., discharge controllers  661 ,  662 , etc., switches  671 ,  672 , etc. and a sense amplifier  681 .  
         [0058]     The ROM cell block  611  stores data in one or more storage cells. In the ROM cell block  611 , writing of data is not supported due to its read only configuration. The virtual ground lines VGL 1 , VGL 2 , etc. and the bit lines BL 1 , BL 2 , etc. are connected to the storage cell(s) of the ROM cell block  611 .  
         [0059]     Data stored in the ROM cell block  611  may be transmitted to the sense amplifier  681  via the bit lines BL 1 , BL 2 , etc. As will be understood by those of skill in the art, respective bit lines BL 1 , BL 2 , etc. may be associated with individual storage cell(s), such as a column of storage cells, of the ROM cell-block  611 . The sense amplifier  681  amplifies the transmitted data and transmits the amplified data Dout to an external device.  
         [0060]     The virtual ground line precharge controller  621  in the illustrated embodiments of  FIG. 6  receives a virtual ground line precharge control signal VPCON and an address control signal ACON 0  as inputs and outputs a virtual ground line precharge signal VPRE 0 . When the virtual ground line precharge control signal VPCON and the address control signal ACON 0  are both at a logic “high” activated level, the virtual ground line precharge controller  621  outputs the virtual ground line precharge signal VPRE 0  at a logic “low” activated level. If either the virtual ground line precharge control signal VPCON or the address control signal ACON 0  is at a logic “low”, the virtual ground line precharge controller  621  outputs the virtual ground line precharge signal VPRE 0  at a logic “high” deactivated level.  
         [0061]     For the embodiments illustrated in  FIG. 6 , the virtual ground line precharge controller  622  receives a virtual ground line precharge control signal VPCON and an address control signal ACON 1  as inputs and outputs a virtual ground line precharge signal VPRE 1 . When the virtual ground line precharge control signal VPCON and the address control signal ACON 1  are both at a logic “high” activated level, the virtual ground line precharge controller  621  outputs the virtual ground line precharge signal VPRE 1  at a logic “low” activated level. If either the virtual ground line precharge control signal VPCON or the address control signal ACON 1  is at a logic “low”, the virtual ground line precharge controller  621  outputs the virtual ground line precharge signal VPRE 1  at a logic “high” deactivated level.  
         [0062]     In the illustrated embodiments of  FIG. 6 , the virtual ground line precharging unit  631  precharges the virtual ground lines VGL 1  responsive to activation of the virtual ground line precharge signal VPRE 0 . In other words, when the virtual ground line precharge signal VPRE 0  is at a logic “low” level, the virtual ground line precharging unit  131  is activated to precharge the virtual ground lines VGL 1 . When the virtual ground line precharge signal VPRE 0  is at a logic “high” level, the virtual ground line precharging unit  131  is deactivated and thus does not couple the virtual ground line VGL 1  to a precharge voltage. Also, the virtual ground line precharging unit  631  inverts the virtual ground line precharge signal VPRE 0  and outputs as bit line precharge control signal VPU 0 .  
         [0063]     For the embodiments illustrated in  FIG. 6 , the virtual ground line precharging unit  632  precharges the virtual ground lines VGL 2  responsive to activation of the virtual ground line precharge signal VPRE 1 . In other words, when the virtual ground line precharge signal VPRE 1  is at a logic “low” level, the virtual ground line precharging unit  631  is activated to precharge the virtual ground lines VGL 2 . When the virtual ground line precharge signal VPRE 1  is at a logic “high” level, the virtual ground line precharging unit  631  is deactivated and thus do not couple the virtual ground line VGL 2  to a precharge voltage. Also, the virtual ground line precharging unit  632  inverts the virtual ground line precharge signal VPRE 1  and outputs a bit line precharge control signal VPU 1 .  
         [0064]     The bit line precharge controller  641 , in the embodiments of  FIG. 6 , receives bit line precharge control signals VPU 0  &amp; VPU 1  and outputs a bit line precharge signal BPRE 0 . When the bit line precharge control signals VPU 0  &amp; VPU 1  are both at a logic “high” level, the bit line precharge controller  641  outputs the bit line precharge signal BPRE 0  at a logic “low” activated level. When either of the bit line precharge control signals VPU 0  and VPU 1  is at a logic “low” level, the bit line precharge controller  641  outputs the bit line precharge signal BPRE 0  at a logic “high” deactivated level.  
         [0065]     For the embodiments illustrated in  FIG. 6 , the bit line precharge controller  642  receives a bit line precharge control signals VPU 1  &amp; VPU 2  and outputs a bit line precharge signal BPRE 1 . When the bit line precharge control signals VPU 1  &amp; VPU 2  are both at a logic “high” level, the bit line precharge controller  642  outputs the bit line precharge signal BPRE 1  at a logic “low” activated level. When either of the bit line precharge control signals VPU 1  and VPU 2  is at a logic “low” level, the bit line precharge controller  642  outputs the bit line precharge signal BPRE 1  at a logic “high” deactivated level.  
         [0066]     The bit line precharging units  651 ,  652 , etc., in the embodiments illustrated in  FIG. 6 , precharge the bit lines BL 1 , BL 2 , etc. responsive to the bit line precharge signals BPRE 0 , BPRE 1 , etc. In other words, when the bit line precharge signals BPREi(I=0,1,2, . . . ) are at a logic “low” level, the bit line precharging units  651 ,  652 , etc. are activated to couple the bit lines BL 1 , BL 2 , etc. to a precharge voltage. When the bit line precharge signals BPREi are at a logic “high” level, the bit line precharging units  651 ,  652 , etc. are deactivated and, thus, do not couple the bit lines BL 1 , BL 2 , etc. to the precharge voltage.  
         [0067]     For the embodiments illustrated in  FIG. 6 , the discharge controllers  661 ,  662 , etc. receive a discharge control signal DCON and address signals ADD 0 , ADD 1 , etc. and output discharge signals DIS 0 , DIS 1 , etc. In particular, for example, the discharge controller  661  receives the discharge signal DCON and address signal ADD 0  and outputs the discharge signal DIS 0 . If either the discharge control signal DCON or the address signal ADD 0  is at a logic “low” level, the discharge controller  161  outputs the discharge signal DIS 0  at a logic “high” activated level. If the discharge control signal DCON and the address signal ADD 0  are both at a logic “high” level, the discharge controller  661  outputs the discharge signal DIS 0  at a logic “low” deactivated level.  
         [0068]     Similarly, the discharge controller  662 , for the embodiments illustrated in  FIG. 6 , receives the discharge control signal DCON and the address signal ADD 1  and outputs the discharge signal DIS 1 . If either the discharge control signal DCON or the address signal ADD 1  is at a logic “low” level, the discharge controller  662  outputs the discharge signal DIS 1  at a logic “high” activated level. When the discharge control signal DCON and the address signal ADD 1  are both at a logic “high” level, the discharge controller  662  outputs the discharge signal DIS 1  at a logic “low” deactivated level. Thus, as described above, the discharge controller  661 , 662 , etc. may be selectively activated responsive to the address signals ADD 0 , ADD 1 , etc.  
         [0069]     For the embodiments illustrated in  FIG. 6 , the switches  671 ,  672 , etc. selectively couple the virtual ground lines VGL 1 , VGL 2 , etc. to ground responsive to the discharge signals DIS 0 , DIS 1 , etc. In other words, when the discharge signal DIS 0  is at a logic “high” level, the switch  671  is activated to ground the virtual ground line VGL 1 . When the discharge signal DIS 0  is at a logic “low” level, the switch  671  is deactivated, and, thus, the virtual ground line VGL 1  is not grounded. Similarly, when the discharge signal DIS 1  is at a logic “high” level, the switch  672  is activated to ground the virtual ground line VGL 2 . When the discharge signal DIS 1  is at a logic “low” level, the switch  672  is deactivated, and, thus, the virtual ground line VGL 2  is not grounded.  
         [0070]      FIG. 7  is a circuit diagram illustrating the bit line precharge controller  641  and the bit line precharging unit  651  illustrated in  FIG. 6  according to some embodiments of the present invention. Referring to the embodiments of  FIG. 7 , the bit line precharge controller  641  includes inverters  711  &amp;  712  that receive the bit line precharge control signals VPU 0  &amp; VPU 1  and a NAND gate that outputs the bit line precharge signal BPRE 0 . The bit line precharging unit  651  includes a PMOS transistor that has a source coupled to the power voltage VDD, a gate coupled to the bit line precharge signal BPRE 0 , and a drain coupled to the bit line BL 1 .  
         [0071]      FIG. 8  is a circuit diagram illustrating the bit line precharge controller  641  and the bit line precharging unit  651  illustrated in  FIG. 6  according to further embodiments of the present invention. Referring to the embodiments of  FIG. 8 , the bit line precharge controller  641  includes a NAND gate  811  that receives the bit line precharge control signals VPU 0  &amp; VPU 1  and a buffer  821  that outputs the bit line precharge signal BPRE 0 . The bit line precharging unit  651  includes a PMOS transistor that has a source coupled to the power voltage VDD, a gate coupled to the bit line precharge signal BPRE 0 , and a drain coupled to the bit line BL 1 .  
         [0072]      FIG. 9  is a timing diagram illustrating operations of the device illustrated in  FIG. 6  according to some embodiments of the present invention.  
         [0073]     As shown in section (a) of  FIG. 9 , the virtual ground line precharge signals VPREi(I=0,1,2, . . . ), the bit line precharge signals BPREi(I=0,1,2, . . . ), and the discharge signal DISi(I=0,1,2, . . . ) are at a logic “low” level. The virtual ground lines VGLi(I=0,1,2, . . . ) and the bit lines Bli(I=0,1,2, . . . ) are precharged to a precharge voltage Vpre. For the illustrated embodiments of  FIG. 9 , the virtual ground lines VGLi and the bit lines Bli are selectively precharged depending on whether their respective address signals (ACON 0 , ACON 1 , etc. shown in  FIG. 6 ) are activated.  
         [0074]     As shown In section (b) of  FIG. 9 , the virtual ground line precharge signals VPREi and the discharge signals DISi are transitioned, substantially concurrently, to a logic “high” level, and the virtual ground lines VGLi are grounded. For the illustrated embodiments of  FIG. 9 , the virtual ground lines VGLi are selectively grounded depending on whether their respective address signals (ADD 0 , ADD 1 , etc. shown in  FIG. 1 ) are activated. However, as VPREi are deactivated (shown as a logic “high” level), the supply of the precharge voltage Vpre to the virtual ground lines VGLi stops substantially at the same time as when the virtual ground lines VGLi are grounded. Thus, a short-circuit condition, in which current would flow from Vpre to the virtual ground lines VGLi, may be reduced or prevented.  
         [0075]     As shown in the embodiments of  FIG. 9 , even though the virtual ground lines VGLi are grounded and decoupled from the precharge voltage Vpre, the supply of the precharge voltage Vpre to the bit lines Bli (BL 1 ,BL 2 , etc. illustrated in  FIG. 1 ) is maintained. Thus, although the virtual ground lines VGLi may be adjacent to the bit lines BLi, the voltage of the bit lines Bli may not drop when the virtual ground lines VGLi are grounded. In other words, any electronic coupling effect between the virtual ground and bit lines may be reduced.  
         [0076]     As shown in section (c) of the embodiments of  FIG. 9 , the bit line precharge signals BPREi are transitioned to a logic “high” deactivated level, so the virtual ground line precharge signals VPREi, the bit line precharge signals BPREi and the discharge signal DISi are still at a logic “high” level. Thus, the virtual ground lines VGLi are still selectively grounded and the supply of the precharge voltage to the bit lines BLi stops. Therefore, in section (c), data stored in the ROM cell block  111  may be read.  
         [0077]     As described above, the timing of precharging of the virtual ground lines VGLi and the bit lines BLi for some embodiments of the present invention are independently controlled. Thus, when the virtual ground lines VGLi are grounded, a short-circuit current may be reduced or prevented from flowing through the virtual ground lines VGLi. As a result, the operational speed of the ROM integrated circuit device  601  (illustrated in  FIG. 6 ) may be increased and power consumption may be decreased. Furthermore, when the virtual ground lines VGLi are grounded, the supply of the precharge voltage Vpre to the bit lines BLi may be continued. Thus, a drop in the precharge voltage Vpre of the bit lines BLi may be reduced or prevented.  
         [0078]     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purpose of limitation, the scope of the invention being set forth in the following claims.