Abstract:
Disclosed is a system and related methodology for providing fast low frequency jitter rejection in the measurement of signals under test. A signal under test may be sampled alternately with a reference signal under similar conditions. The resulting sampled signal blocks may then be processed to subtract the known calibrated value of the reference signal from the average signal under test.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority under 35 U.S.C. § 119(e) of Provisional U.S. Patent Application Ser. No. 60/986,147 filed Nov. 7, 2007, entitled “FAST LOW FREQUENCY JITTER REJECTION METHODOLOGY,” which is incorporated herein by reference in its entirety for all purposes. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The present subject matter is directed to a system and related methodology for reducing the impact of very low frequency jitter for measuring timing parameters, such as relative average signal period, skew, propagation delay, and time interval error (TIE). The method uses interleaved sampling to compare two average values without being subject to very low frequency jitter while maintaining short sampling time. 
       BACKGROUND OF THE INVENTION 
       [0003]    Many parametric measurements are subject to different types of noise. The sources of the noise could be from the signal or circuit under test, or from the measurement instrument. Averaging has been used to increase the measurement precision and repeatability for static parameters. Examples of such parameters include DC voltage or current, clock period, signal skew, or device propagation delay. 
         [0004]    Typically, when an average quantity is to be measured, a number of samples are taken within the data acquisition window and the results averaged. If the noise frequency is larger than the inverse of the averaging window, the standard deviation of the average quantity from one measurement to the next will reduce as below: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    where s i  are the individual samples of the parameter to be measured, N is the number of samples,  s  is the average over N samples, and σ x  denotes the standard deviation of parameter x. 
         [0005]      FIG. 1  illustrates an exemplary frequency response of an averaging process. As evident from  FIG. 1 , the averaging process is effective for reducing noise or jitter at frequencies greater than 1/10 th  of the inverse of the averaging window. This means that the lower frequency noise can result in measurement error, especially if the low frequency noise power is substantial. Examples of such noises include 1/f flicker noise in CMOS devices and 1/f 2  phase noise in oscillators. 
         [0006]    One solution for reducing the impact of low frequency noise is to use a longer averaging window. This, however, has the disadvantages of increased measurement time and reduced effectiveness if the low frequency noise power spectrum has 1/f n  (n≧1) characteristics. 
         [0007]    While various methodologies for compensating for low frequency jitter have been developed, no design has emerged that generally encompasses all of the desired characteristics as hereafter presented in accordance with the subject technology. 
       SUMMARY OF THE INVENTION 
       [0008]    In view of the recognized features encountered in the prior art and addressed by the present subject matter, an improved measurement system and related methodology for reducing the impact of very low frequency jitter for measuring timing parameters. 
         [0009]    In an exemplary configuration, samples of a signal under test are taken alternately with samples of a reference signal. 
         [0010]    In one of their simpler forms, alternating signals under test and a known reference signal are coupled to a measurement instrument. 
         [0011]    In accordance with aspects of certain embodiments of the present subject matter, methodologies are provided to sample plural signals under test in a repeating sequence with a single reference signal. 
         [0012]    It should be appreciated that the present subject matter equally concerns an apparatus and system for implementing the aforementioned exemplary steps. For example, a processor circuit may be coupled to an input circuit and a measurement channel that obtains signal measurements. Such hardware components are configured to implement an alternate sampling technique whereby at least one signal under test and a reference signal are alternately sampled in an interleaved fashion such that the signal under test is sampled in one block and the reference signal is sampled in a subsequent block. This alternate sampling process is repeated until N samples (for some positive integer N) of the at least one signal under test and the reference signal are collected in a series of interleaved sampled waveform blocks. At least one measurement characteristic is obtained for the interleaved sampled waveform blocks. An output, such as visually provided on a display device or printed by a peripheral device may be provided to a user to indicate the measurement characteristics. In one embodiment, the measurement characteristics correspond to an average value of samples of the reference signal (from which a reference signal calibration value is subtracted), and an average vale of samples of the signal under test. The average of the reference signal samples may then be subtracted from the average of the signal under test samples to provide a measurement with reduced low frequency noise or jitter. 
         [0013]    In one embodiment, the processor circuit within a measurement instrument more particularly includes a computer-readable medium for storing executable instructions corresponding to the aforementioned steps and other steps desired in the subject signal analysis. The computer-readable medium may correspond to one or more of a server database, a magnetic tape or disk, a CD-ROM, a flash or other nonvolatile memory, etc. The exact type of memory or storage medium should not be limiting to the present invention. The processor circuit further includes a computer coupled to the readable medium that is adapted to execute the software instructions stored on the computer-readable medium. 
         [0014]    Additional objects and advantages of the present subject matter are set forth in, or will be apparent to, those of ordinary skill in the art from the detailed description herein. Also, it should be further appreciated that modifications and variations to the specifically illustrated, referred and discussed features and elements hereof may be practiced in various embodiments and uses of the invention without departing from the spirit and scope of the subject matter. Variations may include, but are not limited to, substitution of equivalent means, features, or steps for those illustrated, referenced, or discussed, and the functional, operational, or positional reversal of various parts, features, steps, or the like. 
         [0015]    Still further, it is to be understood that different embodiments, as well as different presently preferred embodiments, of the present subject matter may include various combinations or configurations of presently disclosed features, steps, or elements, or their equivalents (including combinations of features, parts, or steps or configurations thereof not expressly shown in the figures or stated in the detailed description of such figures). 
         [0016]    Additional embodiments of the present subject matter, not necessarily expressed in the summarized section, may include and incorporate various combinations of aspects of features, components, or steps referenced in the summarized objects above, and/or other features, components, or steps as otherwise discussed in this application. Those of ordinary skill in the art will better appreciate the features and aspects of such embodiments, and others, upon review of the remainder of the specification. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0017]    A full and enabling disclosure of the present invention, including the best mode thereof, directed to one of ordinary skill in the art, is set forth in the specification, which makes reference to the appended figures, in which: 
           [0018]      FIG. 1  illustrates an averaging filter frequency response; 
           [0019]      FIG. 2A  illustrates a portion of exemplary measurement apparatus for use in an interleaved sampling methodology in accordance with the present technology; 
           [0020]      FIG. 2B  illustrates representative interleaved sampled waveform blocks as may be presented to measurement equipment in accordance with the present technology; and 
           [0021]      FIG. 3  provides a schematic diagram illustration of exemplary hardware components for obtaining and analyzing signal measurements in accordance with aspects of the present invention. 
       
    
    
       [0022]    Repeat use of reference characters throughout the present specification and appended drawings is intended to represent same or analogous features or elements of the invention. 
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0023]    As discussed in the Summary of the Invention section, the present subject matter is particularly concerned with a measurement methodology that is effective in reducing any type of low frequency noise or jitter that may be due to the measurement equipment. In accordance with the present technology, this method is based on interleaved sampling techniques where samples of a signal under test (SUT) and a reference signal are interleaved in multiple blocks. In an exemplary configuration, the present methodology has been applied for the measurement of relative propagation delay in delay line devices using the continuous time interval analyzer (CTIA) from Guidetech, Inc. This method is generally applicable to any measurement that requires averaging to improve measurement precision and accuracy. 
         [0024]    Selected combinations of aspects of the disclosed technology correspond to a plurality of different embodiments of the present invention. It should be noted that each of the exemplary embodiments presented and discussed herein should not insinuate limitations of the present subject matter. Features or steps illustrated or described as part of one embodiment may be used in combination with aspects of another embodiment to yield yet further embodiments. Additionally, certain features may be interchanged with similar devices or features not expressly mentioned which perform the same or similar function. 
         [0025]    Reference will now be made in detail to the presently preferred embodiments of the subject interleaved sampling methodology. Referring now to the drawings,  FIGS. 2A and 2B  illustrate, respectively, a portion of exemplary sampling circuitry  200  and resultant representative sampled waveform blocks  220  as may be presented to a measurement instrument  210  in accordance with the present technology. 
         [0026]    As previously mentioned, one example of a measurement instrument  210  that may be utilized to implement the processing steps described herein is a CTIA offered for sale by Guidetech Inc. of Sunnyvale, Calif., such as but not limited to a FEMTO® 2000 or GT 4000 model time interval analyzer.  FIG. 3  provides a schematic representation of exemplary hardware components contained within such a measurement unit. Although some aspects of the hardware components of  FIG. 3  are discussed herein, additional discussion of these and other components of a measurement instrument that may be utilized in conjunction with certain aspects of the present invention are disclosed in U.S. Pat. No. 6,091,671 (Kattan), which is incorporated herein by reference for all purposes. 
         [0027]    The time interval analyzer  10  of  FIG. 3  includes two channels indicated at  12  and  14 . Each channel includes a control computer  16 , for example a 200 MHz DSP processor, with associated memory  18 , for example a high performance FIFO memory, and logic circuit  20 . Alternatively, the channels may share a common computer, memory and logic circuit, which may collectively be referred to as a processor circuit. Each channel, in turn, includes parallel measurement circuits having comparators  22   a  and  22   b , multiplexers  24   a  and  24   b  and interpolators  26   a  and  26   b . That is, each channel includes multiple, in this case, two measurement circuits. An arming circuit  28  is controlled by computer  16  to trigger the interpolators. A continuous time counter  30  and continuous event counter  32  provide time and event counts to both channels  12  and  14 . Alternatively, each measurement circuit may have its own time counter and event counter, provided that the respective counters for each measurement circuit are synchronized. 
         [0028]    The first measurement circuit  22   a - 26   a / 20  of each channel may be referred to as the “start” measurement circuit, while the second measurement circuit  22   b - 26   b / 20  may be referred to as the “stop” measurement circuit. Generally, time interval analyzer  10  measures characteristics of a desired signal by comparing the time and/or event measurements of the start circuit with that of the stop circuit. The particular measurement depends upon the signal selected at multiplexers  24   a  and  24   b  and upon the manner in which arming circuit  28  arms the interpolators. For example, if the start circuit passes the A in  signal from comparator  22   a  as shown in  FIG. 3 , if the stop circuit multiplexer passes the inverse of the A in  signal from comparator  22   b , and if the interpolator  26   b  is armed immediately following interpolator  26   a , but before the expiration of a period equal to the input signal pulse width, the difference between the time portions of the start and stop measurement tags is equal to the pulse width. Other exemplary measurements of various signal characteristics may include but are not limited to signal skew, signal period, propagation delay and time interval error (TIE). 
         [0029]    Once an interpolator has measured a signal edge, the logic circuit  20  instructs computer  16  to read the interpolator measurement from a capacitor within the interpolator whose charge or discharge is representative of a time signal that corresponds to the occurrence of the measured signal edge relative to a predetermined time reference. Computer  16  is also instructed to read the time and event counts from counters  30  and  32 . It then downloads the time and event counts to memory  18 , from which computer  16  retrieves the information to assign to the signal measurement. In this manner, the processor circuit correlates the measured signal edge with time and event measurements from the counters. Thus a “measurement tag” indicates the time the signal edge occurred and the edge&#39;s position within the sequence of edges. Control computer  16  repeatedly reads the memory to perform a desired analysis and/or to display the measured information at a display device  150 , for example a video monitor. 
         [0030]    Time interval analyzers such as the one illustrated in  FIG. 3  are capable of generating time interval error (TIE) data as well as absolute time tags (referenced to the first sample) for selected edges within a data stream. TIE can be generally described as the time displacement between a given signal edge (or event) and its ideal location determined from an average unit interval, or average bit time. The sampling rate of a data stream is typically much less than the bit rate for a data stream since the measurement circuitry must have an opportunity to settle and recharge (or discharge) after a given measurement to ensure the accuracy of a subsequent measurement. Since the sampling rate is lower than the bit rate, TIE data obtained by a time interval analyzer is effectively an undersampled sequence of total TIE. 
         [0031]    Referring again to  FIG. 2A , the interleaved sampling methodology of the present technology uses a reference signal with small low frequency noise and interleaved block sampling methodology to compare the desired parameters in the signal under test (SUT)  202  with that of a reference signal (REF)  204 . In interleaved sampling, the total samples are divided into multiple sampling blocks. The sampling process includes measuring the SUT  202  signal in one block, sampling the reference signal  204  in the next, and repeating the process until N samples of the SUT  202  signal is collected. 
         [0032]    In an alternative configuration, this methodology can be extended to measuring parameters of more than one SUT. For example, for two SUTs, the interleaved sampling can be implemented by sampling the first SUT 1  in one block, the SUT 2  in the next block, the reference signal in the third block, and then repeating the sequence until desired number of samples for each of SUT 1  and SUT 2  are collected. 
         [0033]    Once the sampling is completed, the average of REF samples minus the known calibrated value of the REF parameter is subtracted from the average of SUT samples, as below: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0000]    where s avg  is the SUT parameter average that is to be measured, s i  (i=1, . . . , N s ) are the SUT samples, N s  is the total number of SUT samples taken, r j  (j=1, . . . , N r ) are the REF samples, N r  is the total number of REF samples taken, and r cal  is the calibrated value of the REF signal parameter. The r cal  may be eliminated from the Equation 2 when the objective is to measure the difference of the SUT and REF parameter averages or SUT 1  and SUT 2  parameter averages. 
         [0034]    In an exemplary configuration, the time duration of each sampling blocks may be set to be at least 10 times smaller than the inverse of the upper threshold of the low frequency noise that is to be filtered. This effectively ensures that the low frequency noise impacts the SUT samples and the reference samples is a similar fashion, and will be cancelled out to a large extent due to the subtraction process shown in Equation 2. 
         [0035]    In one example, the following conditions are met for effective low frequency rejection using interleaved sampling:
       1. The duration of each of SUT and REF sampling blocks should be less than 1/20 f LF , where f LF  is the upper threshold of the low frequency noise to be filtered.   2. The combined time duration for a pair of SUT and REF blocks should be less than 1/10   3. The time between pairs of block can be large, because the closely sampled SUT and REF blocks already share the same low frequency noise impact.       
 
         [0039]    An example of measurement subject to low frequency noise is propagation delay measurement for programmable delay lines. In an exemplary configuration, a GuideTech CTIA may be used for such measurement. A typical test parameter for such devices is to compare the device delays for two or more delay settings. This application lends itself very well to the interleaved sampling methodology because:
       1. The delay for one delay control setting can be used as reference. This means that there is no need to have a separate calibrated reference.   2. No need for a switch in front of the test instrument. The switching between two different delay values is achieved through the delay control input signals.       
 
         [0042]    In accordance with present technology, the input and output signals of a device under test (DUT) are connected to two inputs of the CTIA. The CTIA is programmed to measure multiple blocks of skew between the input and output of the DUT, which determines the propagation delay of the DUT. The block arming capability of the CTIA is used to synchronize the block measurements with the DUT delay switching. Multiple blocks of skew data are collected in the interleaved fashion, as described previously. The average skew for one delay setting is subtracted from the average skew for the other delay setting. Using this approach, the propagation difference between the two settings can be measured within 100 fs RMS accuracy in less than 50 ms. 
         [0043]    In accordance with the present technology, there has been disclosed a methodology for fast and very high precision average parametric measurements in the presence of the low frequency noise in the measurement instrument. This methodology relies on interleaved sampling of the signal user test and that of a reference signal. This effectively provides an estimate of low frequency noise in the reference signal, which can be used to eliminate it in the SUT measurements. While specific examples of potential use for the methodology of the present subject matter have been presented, those of ordinary skill in the art will appreciate that the methodology can be used in many different applications. 
         [0044]    While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, the scope of the present disclosure is by way of example rather than by way of limitation, and the subject disclosure does not preclude inclusion of such modifications, variations and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art.