Abstract:
The invention relates to a level converter for converting a signal (in) comprising a first voltage level (Vint) and supplied to the level converter, to a signal (Out) including a second voltage level (Vsupply) differing from the first voltage level (Vint). The level converter includes an amplifier device. The level converter is additionally supplied with a signal obtained from the signal (in) and delayed for compensating for distortions contained in said signal (in).

Description:
CLAIM FOR PRIORITY  
       [0001]     This application claims priority to German Application No. 10349464.2 filed Oct. 23, 2003, which is incorporated herein, in its entirety, by reference.  
       TECHNICAL FIELD OF THE INVENTION  
       [0002]     The invention relates to a level converter for converting a signal (in) including a first voltage level (Vint) and supplied to the level converter, to a signal (Out) including a second voltage (Vsupply).  
       BACKGROUND OF THE INVENTION  
       [0003]     With semiconductor devices, in particular with memory devices such as DRAMS (DRAM=Dynamic Random Access Memory or dynamic read-write memory, respectively), a voltage level used internally in the device may differ from an external voltage level used outside the device.  
         [0004]     In particular, the internally used voltage level may be smaller than the externally used voltage level—for instance, the internally used voltage level may be 1.8 V, and the voltage level used externally may be 2.5 V.  
         [0005]     The reason for this may, for instance, may be that the external voltage supply is subject to relatively strong fluctuations, and, therefore—in order that the device can be operated without fault—has to be converted, by a voltage regulator, to an internal voltage (that is subject to relatively minor fluctuations only and that is regulated at a particular, constant value).  
         [0006]     By the use of voltage regulators, a loss of voltage may occur, which may result in the voltage level used internally in the device being smaller than the external voltage level.  
         [0007]     An internal voltage level that is reduced vis-à-vis the externally used voltage level has the advantage of reducing power loss in the semiconductor device.  
         [0008]     If a lower voltage level is used internally in the device than is used externally, the signals generated internally in the device typically—before being output outside—are conconverted to corresponding, higher-level signals by so-called level converters.  
         [0009]     Such level converters may, for instance, an amplifier circuit that includes cross-coupled p- or n-channel field effect transistors.  
         [0010]     By using the amplifier circuit, internal, low-level signals generated in the device can leave afflicted with certain delay times—be converted to corresponding higher-level signals.  
         [0011]     However, the delay time occurring with a positive edge of an internal signal may differ from the delay time occurring with a negative edge of the internal signal. The result thereof is that the higher-level signals output by the amplifier circuit are distorted.  
         [0012]     To compensate for this effect, the signals output by the amplifier circuit may be supplied to a driver stage comprising a plurality of, e.g. two, inverters connected in series.  
         [0013]     The inverters are designed such that a compensation of the distortions contained in the signals output by the amplifier circuit is achieved.  
         [0014]     The driver stage does, however, result in a relatively high-additional—signal delay; furthermore, the above-mentioned signal distortions may, for instance due to changes in the characteristics of the level converter devices caused by temperature fluctuations, in general be compensated for only incompletely by a level converter of the above-described type.  
       SUMMARY OF THE INVENTION  
       [0015]     The present invention provides a novel level converter.  
         [0016]     In accordance with a basic idea of the invention, a level converter is provided for converting a signal (in) comprising a first voltage level (Vint) and supplied to the level converter, to a signal (Out) comprising a second voltage level (Vsupply) that differs from the first voltage level (Vint), wherein the level converter includes an amplifier device, and wherein, for compensating distortions contained in the signal (in), the level converter is additionally also supplied with a signal obtained from the signal (in) and delayed by a delay means.  
         [0017]     In a particularly advantageous manner, for generating the signal (Out) including the second voltage level (Vsupply), except for a first output signal (B) of the amplifier device, a second amplifier device output signal (A) differing therefrom is additionally used.  
         [0018]     Preferably, a first transmission gate is triggered with the first amplifier device output signal (B), and/or a signal derived therefrom, and a second transmission gate with the second amplifier device output signal (A), and/or a signal derived therefrom.  
         [0019]     With such a level converter it may, for instance, be achieved that distortions—that are already contained in the signal (in) supplied to the level converter, and/or are caused by the amplifier circuit—can be compensated for almost completely. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The invention can be understood by reference to the Detailed Description of the Invention when taken together with the attached drawings, wherein:  
         [0021]      FIG. 1  is a schematic representation of a typical circuit arrangement of a level converter;  
         [0022]      FIG. 2   a  is a schematic representation of a first section of a circuit arrangement of a level converter in accordance with an embodiment of the present invention;  
         [0023]      FIG. 2   b  is a schematic representation of a further section of the circuit arrangement of the level converter in accordance with the embodiment of the present invention;  
         [0024]      FIG. 2   c  is a schematic representation of a third section of the circuit arrangement of the level converter in accordance with the embodiment of the present invention;  
         [0025]      FIG. 3   a  is a schematic representation of the time characteristics of the input and output signals of the amplifier circuit contained in the level converter illustrated in  FIGS. 2   a,    2   b,    2   c,  and of the straightened output signal of the level converter, with a first, exemplary characteristic of the input signals; and  
         [0026]      FIG. 3   b  is a schematic representation of the time characteristics of the input and output signals of the amplifier circuit contained in the level converter illustrated in  FIGS. 2   a,    2   b,    2   c,  and of the straightened output signal of the level converter, with a second, exemplary characteristic of the input signals. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0027]      FIG. 1  shows a schematic representation of a typical circuit arrangement of a level converter  1 . The level converter  1  is incorporated in a DDR memory device—that is, for instance, based on CMOS technology. It serves to convert an internal voltage level (Vint) used inside the memory device to an external voltage level (Vsupply) used outside the memory device, wherein the internally used voltage level (Vint) is smaller than the externally used voltage level (Vsupply). The internal voltage level (Vint) may, for instance, be 1.8 V, and the external voltage level (Vsupply) may, for instance, be 2.5 V.  
         [0028]     As is illustrated in  FIG. 1 , the level converter  1  includes an amplifier circuit  2 , and a driver stage  8  with a first and a second inverter  3   a ,  3   b  (and, alternatively, with further, not illustrated inverters).  
         [0029]     The amplifier circuit  2  includes four cross-coupled transistors, namely a first and a second p-channel field effect transistor  4   a ,  4   b  (here: two p-channel MOSFETs  4   a ,  4   b ), and a first and a second n-channel field effect transistor  5   a ,  5   b  (here: two n-channel MOSFETS  5   a ,  5   b ).  
         [0030]     The source of the first n-channel field effect transistor  5   a  is connected to the ground (Gnd). Correspondingly, the source of the second n-channel field effect transistor  5   b  is also connected to the ground (Gnd).  
         [0031]     Furthermore, the gate of the first n-channel field effect transistor  5   a  is connected with a first input  6   a  of the amplifier circuit  2 , and the gate of the second n-channel field effect transistor  5   b  is connected with a second amplifier circuit input  6   b.    
         [0032]     The drain of the first n-channel field effect transistor  5   a , the gate of the second p-channel field effect transistor  4   b , and the drain of the first p-channel field effect transistor  4   a  are connected to a first output  7   a  of the amplifier circuit  2 . Correspondingly, a second amplifier circuit output  7   b  is connected with the drain of the second n-channel field effect transistor  5   b , with the gate of the first p-channel field effect transistor  4   a , and with the drain of the second p-channel field effect transistor  4   b.    
         [0033]     The source of the first and of the second p-channel field effect transistor  4   a ,  4   b  is connected to the supply voltage. This supply voltage has, as has already been explained above, a relatively high voltage level (Vsupply) as compared to the internally used voltage.  
         [0034]     At the first input  6   a  of the amplifier circuit  2 , a first internal signal (in) of the DRAM memory device is applied, and at the second input  6   b  of the amplifier circuit  2 , a second device-internal signal (bin) is applied.  
         [0035]     The first and second internal signals (in or bin, respectively) may be complementary, or substantially complementary to one another, respectively.  
         [0036]     The “logically high” states of the first or second internal signal (in or bin, respectively) should—in the ideal case—be substantially of equal duration as their “logically low” states. The internal signals (in or bin, respectively) include—as has already been explained above—the relatively low, internally used voltage level (Vint) as compared to the externally used voltage level (Vsupply).  
         [0037]     The amplifier circuit  2  converts the internal signal (in) applied at the first input  6   a  of the amplifier circuit  2  to a signal (out) that corresponds to the signal (in) and can be tapped at the second output  7   b  of the amplifier circuit  2  and has the above-mentioned—relatively high—external voltage level (Vsupply).  
         [0038]     When the internal signal (in) applied at the first input  6   a  of the amplifier circuit  2  changes from a “logically low” state to a “logically high” state (and the complementary internal signal (bin) from a state “logically high” to a state “logically low”), the corresponding signal (out) that can be tapped at the output  7   b  of the amplifier circuit  2  changes, due to internal signal running times in the amplifier circuit  2 , its state from “logically low” to “logically high” after a certain delay time d 1 ′ only.  
         [0039]     Correspondingly, when the state of the internal signal (in) changes from “logically high” to “logically low” (and the complementary internal signal (bin) changes from “logically low” to “logically high”), the corresponding signal (out) that can be tapped at the output  7   b  changes its state from “logically high” to “logically low” after a certain delay time d 2 ′ only.  
         [0040]     The delay time d 1 ′—occurring with a positive edge of the internal signal (in)—differs, due to differing signal running times in the delay circuit  2 , from the delay time d 2 ′ occurring with a negative edge of the internal signal (in). The result thereof is that the signal (out) that can be tapped at the output  7   b  is distorted (in particular, that its “logically low” state lasts longer than its “logically high” state—and is not, as desired, of substantially equal duration).  
         [0041]     In order to compensate for this effect, in the level converter  1  the signal (out) that can be tapped at the output  7   b  of the amplifier circuit  2  is supplied, via a line  9 , to an input of the first inverter  3   a  of the driver stage  8 , the output  11  of which is connected, via a line  10 , to an input of the second inverter  3   b.    
         [0042]     When the state of the signal (out) that can be tapped at the output  7   b  of the amplifier circuit changes from “logically low” to “logically high” (- or, vice versa, when the state of the signal (out) changes from “logically high” to “logically low”-) (after respective delay times differing from one another), the signal at the output  11  of the first inverter  3   a  changes its state from “logically high” to “logically low” (- or, vice versa, from “logically low” to “logically high”-), and, consequently, the output signal (DatoV) that can be tapped at an output  12  of the second inverter  3   b  changes from a state “logically low” to a state “logically high”, or, vice versa, from a state “logically high” to a state “logically low” (again after respective delay times differing from one another).  
         [0043]     The inverters  3   a ,  3   b —in particular the delay times caused thereby, which are different for positive and negative signal edges—are designed such that the delay time d 1  occurring altogether between a positive signal edge of the signal (in) applied at the input  6   a  of the amplifier circuit  2  and a corresponding, positive signal edge of the output signal (DatoV) output at the output  12  of the second inverter  3   b  is substantially as large as the delay time d 2  occurring altogether between a negative signal edge of the signal (in) and a corresponding, negative signal edge of the output signal (DatoV).  
         [0044]     The result thereof is a compensation of the distortion contained in the signal (out) applied at the output  7   b  of the amplifier circuit  2  (so that e.g. the “logically low” state of the output signal (DatoV) applied at the output  12  of the second inverter  3   b  then last substantially as long as its “logically high” state).  
         [0045]     However, the driver stage  8  leads to a relatively high—additional—signal delay; furthermore, for instance due to component inaccuracies, or due to changes in the characteristics of the components used that are caused by temperature fluctuations, the signal distortion can, in general, be compensated for only incompletely by a level converter of the above-described type.  
         [0046]     Further problems may occur when—deviating from the above-mentioned “ideal case”, and as illustrated by way of example in  FIG. 3   a , top, and  FIG. 3   b , top—the “logically high” and the “logically low” states of the first or the second internal signal (in or bin, respectively) are of a differently long duration.  
         [0047]     If—as is, for instance, illustrated in  FIG. 3   a , top—the “logically high” state of the signals in, bin lasts shorter than the “logically low” state, both the first signal in and the second signal bin are—as results from  FIG. 3   a —“logically low” during a particular period T, which results in a “floating” of the signals bout, out that are output at the outputs  7   a ,  7   b.    
         [0048]     If—vice versa, and as is illustrated, for instance, in  FIG. 3   b , top—the “logically high” state of the signals in, bin lasts longer than the “logically low” state, both the first signal in and the second signal bin are—as results from  FIG. 3   b —“logically high” during a particular period T, which results in that the outputs  7   a ,  7   b  are—simultaneously—pulled down.  
         [0049]      FIG. 2   a  is a schematic representation of a first section  101   a  of a circuit arrangement of a level converter in accordance with an embodiment of the present invention.  
         [0050]     The level converter is incorporated into a semiconductor device that is, for instance, based on CMOS technology, in particular a DRAM memory device (e.g. a DDR-DRAM (“Double Data Rate” DRAM or DRAM with double data rate, respectively)), and may especially be used for an OCD device of the DRAM memory device (OCD=Off Chip Driver), or e.g. for a DLL device (DLL=Delay Locked Loop).  
         [0051]     The level converter converts an internal voltage level (Vint) used inside the DRAM memory device to an external voltage level (Vsupply) used outside the memory device, wherein the internally used voltage level (Vint) is smaller than the externally used voltage level (Vsupply).  
         [0052]     The internal voltage level (Vint) may, for instance, be 1.8 V—or, alternatively, e.g. 1.5 V or 1.4 V—, and the external voltage level (Vsupply) may, for instance, be 2.5 V—or, alternatively, e.g. 1.8 V or 2.0 V.  
         [0053]     In accordance with  FIG. 2   a , the first section  101   a  of the level converter includes an amplifier circuit  102  and—as will be explained in detail in the following—two input delay means  103   c ,  103   d , and two output switching elements  103   a ,  103   b  (here: two latches  103   a ,  103   b ).  
         [0054]     Furthermore, a second level converter section  101   b —illustrated in  FIG. 2   b —includes two transmission gates  113   a ,  113   b , and a third level converter section  101   c —illustrated in  FIG. 2   c —also includes two transmission gates  113   c ,  113   d.    
         [0055]     Referring again to  FIG. 2   a , the amplifier circuit  102  provided in the level converter includes a plurality of cross-coupled transistors, namely a first and a second p-channel field effect transistor  104   a ,  104   b  (here: two p-channel MOSFETs  104   a ,  104   b ), furthermore a first and a second n-channel field effect transistor  105   a ,  105   b  (here: two n-channel-MOSFETs  105   a ,  105   b ), and a third and fourth n-channel field effect transistor  105   c ,  105   d  (here: two further n-channel MOSFETs  105   c ,  105   d ).  
         [0056]     The source of the third n-channel field effect transistor  105   c  is connected to the ground (Gnd). Correspondingly, the source of the fourth n-channel field effect transistor  105   d  is also connected to the ground (Gnd).  
         [0057]     Furthermore, the gate of the third n-channel field effect transistor  105   c  is—via a line  106   e —connected with a first input  106   a  of the amplifier circuit  102 , and the gate of the fourth n-channel field effect transistor  105   d  is—via a line  106   h —connected with a second amplifier circuit input  106   b.    
         [0058]     As results further from  FIG. 2   a , the source of the first n-channel field effect transistor  105   a  is connected to the drain of the third n-channel field effect transistor  105   c . Correspondingly, the source of the second n-channel field effect transistor  105   b  is connected with the drain of the fourth n-channel field effect transistor  105   d.    
         [0059]     The gate of the first n-channel field effect transistor  105   a  is, via a line  106   d , connected with the output of the input delay means  103   c , the input of which is—via a line  106   c —connected to the first input  106   a  of the amplifier circuit  102 .  
         [0060]     Correspondingly similar, the gate of the second n-channel field effect transistor  105   b  is—via a line  106   g —connected with the output of the input delay means  103   d , the input of which is—via a line  106   f —connected to the second input  106   b  of the amplifier circuit  102 .  
         [0061]     In accordance with  FIG. 2   a , each of the input delay means  103   c ,  103   d  includes a plurality of (in particular an odd number, here: three) inverters connected in series.  
         [0062]     The drain of the first n-channel field effect transistor  105   a , the gate of the second p-channel field effect transistor  104   b , and the drain of the first p-channel field effect transistor  104   a  is connected to a first output  107   a  of the amplifier circuit  102 . Correspondingly, a second amplifier circuit output  107   b  is connected with the drain of the second n-channel field effect transistor  105   b , the gate of the first p-channel field effect transistor  104   a , and the drain of the second p-channel field effect transistor  104   b.    
         [0063]     The source of the first and second p-channel field effect transistors  104   a ,  104   b  is connected to a supply voltage which—as has already been explained above—has a relatively high voltage level (Vsupply) (as compared to the internally used voltage).  
         [0064]     A first internal signal (in) of the DRAM memory device is applied at the first input  106   a  of the amplifier circuit  102 , and a second device-internal signal (bin) is applied at the second input  106   b  of the amplifier circuit  102 .  
         [0065]     The first and second internal signals (in and bin) are complementary to one another. The first and second signals may, for instance, be differential clock signals (CLK, bCLK) that are complementary to one another, or any other signals.  
         [0066]     The “logically high” states of the first or the second internal signal (in or bin, respectively) may, for instance, last substantially as long as their “logically low” states, or—as is illustrated in  FIG. 3   a , top—the “logically high” state of the signals in, bin may (for instance, due to signal distortions) be shorter than the “logically low” state, or—as is illustrated in  FIG. 3   b , top—the “logically high” state of the signals in, bin may last longer than the “logically low” state, etc.  
         [0067]     As has already been explained above, the internal signals (in and bin) have—as compared to the externally used voltage level (Vsupply)—the relatively low, internally used voltage level (Vint).  
         [0068]     The amplifier circuit  102  converts the internal signal (in) applied at the fist amplifier circuit input  106   a  to a corresponding signal (B) that can be tapped at the second output  107   b  of the amplifier circuit  102  (and the internal signal (bin) applied at the second amplifier circuit input  106   b  is converted to a corresponding signal (A) that can be tapped at the first output  107   a  of the amplifier circuit  102 ).  
         [0069]     The signals (A or B, respectively) that can be tapped at the first and at the second amplifier circuit output  107   a ,  107   b  comprise the external voltage level (Vsupply) that is, as compared to the voltage level (Vint) used with the internal signals (in or bin, respectively), relatively high.  
         [0070]     By the—odd—number of inverters contained in the input delay means  103   c ,  103   d  it is achieved that—after a particular delay time T 1  caused by the input delay means  103   c ,  103   d —inverse input signals are applied at the line  106   d  and the line  106   e  (i.e. at the gate of the n-channel field effect transistor  105   a  and at the gate of the n-channel field effect transistor  105   c ), or at the line  106   g  and the line  106 h (i.e. at the gate of the n-channel field effect transistor  105   b  and at the gate of the n-channel field effect transistor  105   d ).  
         [0071]     The delay time T 1  caused by the input delay means  103   c ,  103   d  is chosen such that it corresponds substantially to the switching time (tipping time) T 2  of the amplifier circuit  102 , or is somewhat larger, respectively.  
         [0072]     As results from  FIG. 2   a , with the level converter according to the present embodiment, the signal (B) that can be tapped at the second output  107   b  of the amplifier circuit  102  is supplied, via a line  109   b , to an input of the output switching element  103   b  (here: the latch  103   b ), and the complementary signal (A) that can be tapped at the first output  107   a  of the amplifier circuit  102  is supplied, via a line  109   a , to an input of the output switching element  103   a  (here: the latch  103   a ).  
         [0073]     Each of the output switching elements or latches  103   a ,  103   b , respectively, includes a first inverter, the input of which is connected with the input of the respective output switching element  103   a , and the output of which is connected to the output of the respective output switching element  103   a , as well as a second inverter feeding back the signal (bA, bB) output at the output of the respective first inverter of the respective output switching element  103   a ,  103   b  to the input of the respective first inverter of the respective output switching element  103   a ,  103   b.    
         [0074]     As is illustrated in  FIGS. 2   a  and  2   b , the signal (B) that can be tapped at the second output  107   b  of the amplifier circuit  102  is—except from being supplied to the input of the output switching element  103   b  via the line  109   b —additionally supplied to a first control input of the transmission gate  113   b  via a line  111   b.    
         [0075]     Furthermore, the signal (bB) output at the output of the output switching element  103   b  is—via a line— 110   b —supplied to a second, complementary control input of the transmission gate  113   b.    
         [0076]     As is further illustrated in  FIGS. 2   a  and  2   b , the signal (A) that can be tapped at the first output  107   a  of the amplifier circuit  102  is—via a line  111   a —supplied to a first control input of the transmission gate  113   a.    
         [0077]     Furthermore, the signal (bA) output at the output of the output switching element  103   a  is—via a line  110   a —supplied to a second, complementary control input of the transmission gate  113   a.    
         [0078]     Furthermore—as is illustrated in  FIGS. 2   a  and  2   c —the signal (A) that can be tapped at the first output  107   a  of the amplifier circuit  102  is—except from being supplied to the input of the output switching element  103   b  via the line  109   b , and to the first control input of the transmission gate  113   a  via the line  111   a —additionally supplied—also via the line  111   a —to a first control input of the transmission gate  113   c.    
         [0079]     Moreover, the signal (bA) output at the output of the output switching element  103   a  is—except from being supplied to the second, complementary control input of the transmission gate  113   a —additionally also supplied (also via the line  110   a ) to a second, complementary control input of the transmission gate  113   c.    
         [0080]     As is further illustrated in  FIGS. 2   a  and  2   c , the signal (B) that can be tapped at the second output  107   b  of the amplifier circuit  102  is (except from being supplied to the first control input of the transmission gate  113   b ) additionally supplied—also via the line  111   b —to a first control input of the transmission gate  113   d.    
         [0081]     Furthermore, the signal (dB) output at the output of the output switching element  103   b  is—via the above-mentioned line  110   b —supplied to a second, complementary control input of the transmission gate  113   d.    
         [0082]     Each transmission gate  113   a ,  113   b ,  113   c ,  113   d  includes an n- and a p-channel field effect transistor, wherein the first control input of the respective transmission gate  113   a ,  113   b  is respectively connected to the gate of the first field effect transistor, and the second, complementary control input of the respective transmission gate  113   a ,  113   b  is respectively connected to the gate of the second field effect transistor.  
         [0083]     As results from  FIG. 2   b , with the transmission gate  113   a , the drain or the source, respectively, of the n- or the p-channel field effect transistor, respectively (i.e. the input or output of the transmission gate  113   a , respectively) is connected to the ground (Gnd), or, via a line  114   a , to a first output  112  of the level converter at which a first output signal (signal Out) corresponding to the input signal (in) is output.  
         [0084]     Contrary to this, with the transmission gate  113   b , the drain or the source, respectively, of the n- or p-channel field effect transistor, respectively (i.e. the input or output of the transmission gate  113   b , respectively) is connected to the supply voltage (Vsupply), or, via a line  114   b , to the above-mentioned first level converter output  112 .  
         [0085]     Correspondingly similar as with the transmission gate  113   a , with the transmission gate  113   d —as results from  FIG. 2   c —the drain or the source, respectively, of the n- or p-channel field effect transistor, respectively (i.e. the input or output of the transmission gate  113   d , respectively) is connected to the ground (Gnd), or, via a line  114   c , to a second output  115  of the level converter at which a second output signal (signal bOut) corresponding to the input signal (bin) is output.  
         [0086]     Contrary to this, with the transmission gate  113   c , the drain or the source, respectively, of the n- or p-channel field effect transistor, respectively (i.e. the input or output of the transmission gate  113   c , respectively) is connected to the supply voltage (Vsupply), or, via a line  114   d , to the above-mentioned second level converter output  115 .  
         [0087]     In order to compensate for the effect of differently long signal running times caused by the amplifier circuit  102  (which depend on whether the signal (in) applied at the input  106   a  of the amplifier circuit  102  changes from “logically low” to “logically high” (“positive” edge of the signal (in)), or—vice versa—from “logically high” to “logically low” (“negative” edge of the signal (in)) (or—correspondingly inversely—the signal (bin) applied at the input  106   b  of the amplifier circuit  102 )), only the positive edges of the input signals (signal (in) and signal (bin)) are used for triggering the transmission gates  113   a ,  113   b ,  113   c ,  113   d  (or—alternatively—e.g. only the negative signal edges). With respect to the positive signal edges (or the negative signal edges, respectively), the signal running times occurring and caused by the amplifier circuit  102  are—due to the symmetrical construction of the amplifier circuit  102 —substantially of equal duration.  
         [0088]     When the internal signal (in) applied at the first input  106   a  of the amplifier circuit  102  changes from a “logically low” state to a “logically high” state (and the complementary internal signal (bin) from a state “logically high” to a state “logically low”), the signal (A) that can be tapped at the first output  107   a  of the amplifier circuit  102  changes, in accordance with  FIGS. 3   a  and  3   b , its state from “logically high” to “logically low”, with the consequence that—since the transmission gate  113   a  will then be locking, and the transmission gate  113   b  will then be conducting—a “logically high” signal (Out) is output at the output  112  (and—since the transmission gate  113   c  will then be locking, and the transmission gate  113   d  will then be conducting—a “logically low” signal (bOut) is output at the output  115 ).  
         [0089]     When the internal signal (bin) applied at the second input  106   b  of the amplifier circuit  102  changes from a “logically low” state to a “logically high” state (and the complementary internal signal (in) from a state “logically low” to a state “logically high”), the signal (B) that can be tapped at the amplifier circuit  102  changes, in accordance with  FIGS. 3   a  and  3   b , its state from “logically high” to “logically low”, with the consequence that—since the transmission gate  113   a  will then be conducting, and the transmission gate  113   b  will then be locking—a “logically low” signal (Out) is output at the output  112  (and—since the transmission gate  113   c  will then be conducting, and the transmission gate  113   d  will then be locking—a “logically high” signal (bOut) is output at the output  115 ).  
         [0090]     By the output switching elements or latches  103   a ,  103   b , respectively, it is achieved that the corresponding levels (- during a “logically high” level at the output  107   a  or  107   b , respectively) are maintained appropriately, so that a “floating” of the outputs  107   a  or  107   b , respectively, is avoided.  
         [0091]     By the fact that only the positive clock edges of the signal (in) and of the signal (bin) are used for triggering the transmission gates  113   a ,  113   b ,  113   c ,  113   d , distortions of the output signals (Out or bOut, respectively) which otherwise result from running time differences caused by the amplifier circuit  102 , may be avoided.  
         [0092]     Furthermore, distortions contained in the input signals (in or bin, respectively) (which, for instance, result in that the “logically high” state of the signals in, bin may be shorter than the “logically low” state, or vice versa) may be compensated for by signal delays caused by the input delay means  103   c ,  103   d.