Abstract:
A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application is a continuation-in-part of copending U.S. patent application Ser. No. 12/072,109 filed Feb. 22, 2008, and entitled Method and Apparatus for Initialization of Read Latency Tracking Circuit in High-Speed DRAM, which is a continuation of U.S. patent application Ser. No. 11/429,856 filed May 8, 2006 and entitled Method and Apparatus for Initialization of Read Latency Tracking Circuit in High Speed DRAM, now U.S. Pat. No. 7,355,922, which is a continuation of U.S. patent application Ser. No. 10/910,838 filed Aug. 4, 2004 and entitled Method and Apparatus for Initialization of Read Latency Tracking Circuit in High Speed DRAM, now U.S. Pat. No. 7,065,001, all of which are incorporated by reference in their entireties for all purposes. The present disclosure is related to U.S. patent application Ser. No. 10/389,807 filed Mar. 18, 2003, and entitled Method and Apparatus for Establishing and Maintaining Desired Read Latency in High-Speed DRAM, now U.S. Pat. No. 6,762,974, and which is assigned to the same assignee as the present disclosure. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to DRAM circuits and, more specifically, to a circuit and method for maintaining a desired read latency in a high-speed DRAM. 
         [0003]    A typical DRAM memory system has an external DRAM controller that makes read and write requests to a DRAM memory device. When making a read request, the controller expects data within the memory device to be available on a data bus within a predetermined read latency, which is usually a predetermined number of system clock cycles, which are external to the DRAM device, after a read request is made by the controller, e.g., eight external clock cycles. 
         [0004]    Problems with maintaining read data latency in high-speed DRAM arise from the necessity to align data with the external clock using an internal delay locked loop (DLL), which generates timing signals, including a read clock signal, for internal DRAM operations. The phase relationship between the external clock, an internal command/address capture clock and the DLL output clock, which is used to generate the read clock signal, is completely arbitrary and dependent on frequency and process, voltage, and temperature (PVT) variations. The command capture clock is delayed relative to the external clock by the clock receiver and other clock distribution delays. The DLL is back timed relative to the external clock by the delay of the data output circuits, but receives its input from an internal clock receiver and also has adjustments made to its output signals that are not synchronized with the external clock. A difference in phase near or greater than a complete clock cycle creates difficulty in controlling timing between the command/address capture clock domain and the DLL clock domain. 
         [0005]    Internally the DRAM memory device has its own DLL driven clock system that receives the external clock signal and develops from the external clock several different internal clock signals, including a read clock signal, for internal operation of the memory device. The internal clock system of known, high-speed memory devices produces at least two clock domains. The first clock domain represents the timing used in the bulk of the logic circuits and to drive the memory array. The timing for the first domain is produced from the internal clock receiver, which is buffered from the external free running system clock. The phase of the clock signal in the first domain relative to the external clock is dependent upon delays in the clock receiver that receives the external clock signal. The second domain, also derived from the external system clock, represents the timing of a back-timed read clock signal. This clock domain is produced by the delay locked loop DLL and associated clock trees. This second clock domain produces a read clock for operating data read latches. The read clock is provided to the read latch with a desired phase relationship relative to the external system clock. The second clock domain compensates for delays in the data output path to produce a read clock signal that operates the output data latches to achieve a specified phase alignment with the external system clock. 
         [0006]    Neither of these two clock domains accurately reflects the timing of the external system clock, particularly at high frequencies of operation. The timing of the clock signals in the two domains may crisscross one another during memory device operation due to process, voltage and temperature (PVT) variations. Consequently, a problem may arise in that the clock domain responsible for delivery of read data to an output latch may cause this data to be delivered at a different time from when the back-timed read clock for latching that data is present at the latch, or when the data is actually required to be driven to an external bus. 
         [0007]    To meet a specified read latency the memory device must be able to count clock signals following receipt of a READ command and activate the output latch and data driver to latch output data with the back-timed read clock and drive the bus at the precise time necessary to produce the specified read latency. 
         [0008]    Because the amount of read clock back-timing relative to the data availability becomes indeterminate during high-speed operation, it is very difficult to control the read clock and guarantee a correct data output and a specific read latency as measured in external clock cycles. 
         [0009]    One solution to these problems is disclosed in U.S. patent application Ser. No. 10/389,807 entitled Method and Apparatus for Establishing and Maintaining Desired Read Latency in High-Speed DRAM which is assigned to the same assignee as the present invention. That document discloses a method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read latency. A reset signal is generated at DRAM initialization and starts a first counter, which counts external clock cycles, and is also passed through a slave delay line of a delay lock loop to start a second counter. The counters run continuously once started and the difference in count values represent the internal delay as an external clock signal passes through the delay lock loop to produce an internal read clock signal. An internal read latency value is used to offset either counter to account for the internal read latency of the DRAM circuit. Once the non-offset counter is equivalent to the offset counter, read data is placed on an output line with a specified read latency and synchronized with the external read clock. 
         [0010]    Another solution to these problems is disclosed in U.S. Pat. No. 6,687,185 which discloses an apparatus and method for coordinating the variable timing of internal clock signals derived from an external clock signal to ensure that read data and a read clock used to latch the read data arrive at the data latch in synchronism and with a specified read latency. A read clock is produced from the external clock signal in a delay lock loop circuit and a start signal, produced in response to a read command, is passed through a delay circuit slaved with the delay lock loop so that the read clock signal and a delayed start signal are subject to the same internal timing variations. The delayed start signal is used to control the output of read data by the read clock signal. 
       BRIEF SUMMARY OF THE INVENTION 
       [0011]    One aspect of the present disclosure is directed to a method of synchronizing a first counter located in a read clock domain and a second counter located in a control clock domain of a memory device. The method is comprised of preloading a value into one or both counters such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead 
         [0012]    Another aspect of the present disclosure is a method of controlling the output of data from a memory device. The method is comprised of deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock are each comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing. 
         [0013]    According to another embodiment of the present disclosure, an apparatus for synchronizing a first counter located in a read clock domain and a second counter located in a control clock domain of a memory device is comprised of a circuit for determining a value equal to a column address strobe latency (L) minus a synchronization (SP) overhead, and means for connecting said circuit to at least one of the counters such that the difference in starting counts between the two counters is equal to the value. The apparatus may be used in a variety of devices, and in particular, solid state memory devices. 
         [0014]    The various embodiments of the present disclosure compensate, for example, for uncertainty and variation in the amount of read clock back-timing in the DRAM memory device by delivering data to a bus output which is properly timed and synchronized with an external clock to ensure that data is properly delivered to the data bus with a specified read latency. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    For the present disclosure to be easily understood and readily practiced, the present disclosure will now be described, for purposes of illustration and not limitation, in conjunction with the following figures, wherein: 
           [0016]      FIG. 1  is a block diagram of a memory device employing one embodiment of the present disclosure; 
           [0017]      FIG. 2  is a detailed block diagram of a circuit for implementing an embodiment of the present disclosure; 
           [0018]      FIGS. 3A-3J  are a timing diagram of various signals present in the circuit of  FIG. 2 ; 
           [0019]      FIG. 4  illustrates another embodiment of the present disclosure; and 
           [0020]      FIG. 5  is a system employing memory devices employing the present disclosure. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Reference will now be made in detail to certain embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Those of ordinary skill in the art will understand that the figures and descriptions of the present disclosure included herein illustrate and describe elements that are of particular relevance to the present disclosure, while eliminating for the sake of clarity other elements found in typical solid-state memories or memory-based systems. 
         [0022]      FIG. 1  illustrates an external memory controller  10  in communication with a memory device  12  through buses  14 ,  14 ′. Memory device  12  may include any of the known high-speed solid state memory devices including, but not limited to, various types of DRAM memories. The bus  14  is comprised of a line for carrying an external clock signal  16  (“external” with respect to memory device  12 ) and command/address lines  18  while bus  14 ′ is a data bus. Buses  14 ,  14 ′ may be a single bus in certain systems. Those of ordinary skill in the art will recognize that many different types of bus configurations are possible. The present invention is not intended to be limited by any particular type of bus configuration. Those of ordinary skill in the art will recognize that many DQs are provided on the memory device  12  and that the data bus  14 ′ is a multi-line bus, although a single DQ is shown in memory device  12  and a single line is shown within data bus  14 ′. 
         [0023]    The external clock signal  16  is received by a clock receiver  28  which receives and buffers the external clock signal  16  to produce a control clock signal  30 . A command and address receiver  32  receives and buffers command and address signals appearing on bus  14 . A command decoder  34  is responsive to the command/address receiver  32  for latching and decoding incoming commands from the memory controller  10 . An address decoder  36  is provided for latching and decoding incoming addresses from external memory controller  10 . 
         [0024]    When a read command is decoded by the command decoder  34 , that command is used to initialize a read operation on a memory array  38 . A read operation is initiated through the read logic  40  which operates the memory array  38  to read out data from one or more addresses identified by the address decoder  36 . The command decoder  34 , addressed decoder  36  and read logic  40  are driven by the control clock  30 . 
         [0025]    Data output from the memory array  38  is input to a data pipeline  42 . Data output from the data pipeline  42  is received by a read latch  44  which, in turn, provides the data to an output driver  46  for driving an output pad DQ. Both the data pipeline  42  and read latch  44  are driven by read clocks  48 . 
         [0026]    The read clocks  48  are produced by a circuit  52  which includes a locked loop, shown in  FIG. 2 , such that the control clock  30  is on one side, the upstream side, of the locked loop while the read clocks  48  are on the other side of the locked loop, referred to as the downstream side. The phase locked loop as used herein refers to a DLL, PLL or any other clock alignment circuit. The control clock  30  represents one clock domain while the read clocks  48  represent another clock domain. It is important that the read latch  44  be driven by the read clocks  48  in a manner so that the data is presented on the data output pad DQ with a read latency which has been anticipated by the external memory controller  10 . If the data is not provided at the DQ with the proper read latency, i.e., it is presented sooner than or later than when the external memory controller  10  expects to receive it, the data will be corrupted and unusable. It is therefore important to establish the proper read latency. The establishment of the proper read latency is complicated by the fact that data is output from the memory array  38  in response to a clock (control clock  30 ) which is in a different clock domain than the read clocks  48  which are used to drive the data to the output driver  46  and ultimately on to the data output pad DQ. 
         [0027]    Those of ordinary skill in the art will recognize that the read latch  44  and output driver  46  form an output data path  54 . Only one output data path  54  is illustrated in  FIG. 1  although an actual memory device  12  would have a plurality of such output data paths  54  to enable data to be output in a parallel manner on a plurality of data output pads DQ. Additionally, in some devices, the pads DQs are also used for write operations in which data output from the external memory controller  10  is intended to be written into memory array  38 . For purposes of simplicity, the data input paths and the various logic needed to operate the memory array  38  for write operations are not shown in  FIG. 1 . 
         [0028]    Completing the description of  FIG. 1 , a QED strobe signal  56  is produced by the circuit  52  as described below. The QED strobe signal  56  is used to enable output driver  46 . The QED strobe signal  56  is in sync with the read clocks  48  as will be described below. 
         [0029]    In  FIG. 2 , the circuit  52  is shown in greater detail. The circuit  52  is comprised of a locked loop  70 . The locked loop  70  has a forward path comprised of a phase detector  72 , a delay line  74  and a clock distribution circuit or clock distribution tree  76  which produces a plurality of read clock signals. The locked loop  70  is also comprised of a feedback path comprised of an input/output model  78  connected between the clock distribution circuit  76  and one input of the phase detector  72 . The phase detector  72  receives the control clock signal  30  and, via the feedback path, one of the plurality of read clocks. The locked loop  70  defines an upstream side which is driven by one clock domain, i.e., the control clock signal  30 , as well as a downstream side which is driven by another clock domain, i.e., the plurality of read clocks. The locked loop  70  is of a known construction and operation and is therefore not further described herein. 
         [0030]    The phase detector  72  produces a lock signal  80  which is input to an initialization circuit  82 . The initialization circuit  82  also receives one of the read clock signals from the clock distribution circuit  76 . The purpose of the initialization circuit  82  is to produce a start signal  84  in response to the lock signal  80 . Turning briefly to  FIG. 3 , the read clock signal input to the initialization circuit  82  is shown in  FIG. 3A . The lock signal  80  which is also input to the initialization circuit  82  is shown in  FIG. 3B . As seen in  FIG. 3B , the lock signal goes high, or otherwise changes state, at time t 1 . At time t 4  the start signal  84  illustrated in  FIG. 3D  goes high. Thus, the initialization circuit  82  is effectively responsible for delaying and synchronizing the lock signal  80  from time t 1  to time t 4 , and thereafter allowing the lock signal  80  to propagate as the start signal  84 . 
         [0031]    The start signal  84 , in one embodiment, is input to a first or downstream counter  90  through an offset down counter  92  although, in other embodiments, the offset down counter  92  may be eliminated. Both the downstream counter  90  and the offset down counter  92  receive one of the plurality of read clock signals. The offset down counter also receives a load command  94  from the initialization circuit  82 . Turning to  FIG. 3C , it is seen that the initialization circuit  82  produces the load command  94  at time t 3 . Thus, the load command  94  is a pulse produced after a time delay measured from time t 1  to time t 3  upon the initialization circuit&#39;s  82  receipt of the lock signal  80 . The initialization circuit  82  may be implemented using a state machine. The load command  94  causes the offset down counter to load a value which is program latency, i.e., a column address strobe latency, (L) minus a synchronization overhead (SP). That can be seen in  FIG. 3E . The SP value is a structural part of the control path and is a constant that is dependent on the particular design. The SP value can vary with frequency, and that is part of the design. After receiving the load command, the offset down counter  92  begins counting clock pulses at time t 5  upon receipt of the first rising edge of the read clock shown in  FIG. 3A  after receipt of the start signal  84  illustrated in  FIG. 3D . After the offset down counter  92  has counted down from the loaded value, as shown at time t 7  in  FIG. 3E , a “done” signal is produced which is input to a reset input terminal of the downstream counter  90  as shown in  FIG. 3F . That causes the downstream counter  90  to begin counting clock pulses of the read clock signal at time t 8 . 
         [0032]    The start signal  84  is also input into another I/O model  78 ′. The I/O model  78 ′ introduces the same amount of delay as the I/O model  78 , namely, the time necessary for a signal to propagate through the I/O circuit of the device. The output of the I/O model  78 ′ is input to a reset input terminal of a second or upstream counter  86 . Referring again to  FIG. 3 , the start signal  84  shown in  FIG. 3D  is input to the I/O model  78 ′ which produces the upstream counter reset signal  88  shown in  FIG. 31 , synchronized to the control clock  30 , at time t 6  after the delay imposed by the I/O model  78 ′. The upstream counter  86  receives the control clock  30  and thus is producing a running count of the clock pulses comprising the control clock  30 . That running count is initialized by the upstream counter reset signal  88 . When the upstream counter  86  receives the upstream counter reset signal  88  shown in  FIG. 31 , the upstream counter  86  begins counting the clock pulses of the control clock  30  as shown in  FIG. 3J , upon receipt of the next rising clock edge. The upstream counter  86  thus produces a running count of clock pulses of the control clock signal  30  in response to the start signal  84  after a delay introduced by I/O model  78 ′. 
         [0033]    By time t 8 , both the upstream counter  86  and the downstream counter  90  have received signals at their respective reset input terminals and are each producing a running count; the upstream counter  86  is producing a running count of the pulses of the control clock  30  while the downstream counter  90  is producing a running count of the pulses of the read clock. 
         [0034]    When a read command is received and decoded by the command decoder  34  of  FIG. 1 , the read command or other appropriate signal is sent to a FIFO  96 . The purpose of the FIFO  96  is to latch or otherwise hold a then current value of the running count of the upstream counter  86 . That held value from the upstream counter  86  is compared by a comparator  98  to the running count of the downstream counter  90 . When the two values are equal, or some other known relationship is reached, a “valid” signal is produced. The “valid” signal is input to an unload input terminal of the FIFO  96  and a driver enable counter  100 . The driver enable counter  100  produces the QED strobe signal  56  which is used to enable the output driver  46 . The construction and operation of the driver enable counter  100  is known in the art and is not described further herein. After the output driver  46  is enabled, the read clock signal may be used to output data from the memory device. Thus, the output of data is in response to the read clock signal and the digital comparator  98 . 
         [0035]    In the current disclosure, the counters  86  and  90  are initialized such that the upstream count value leads the downstream count value by an integer number of clock cycles minus the delay through the I/O model  78 ′ which, as previously stated, is the same as the delay of I/O model  78 , namely, the time it takes for a signal to propagate through the I/O circuit of the device. By establishing this known relationship between the counters, the time when the output driver enable signal is required to synchronize the DRAM output data with the external clock  16  can be determined. 
         [0036]    The current disclosure establishes the relationship between the upstream counter  86  and the downstream counter  90  by sending a reset signal  88  that is synchronized to the upstream counter after passing through the I/O model  78 ′. Thus, in addition to providing a method and apparatus for controlling the output of data from memory device  12 , the present disclosure provides a method and apparatus for synchronizing counters in two different clock domains within a memory device. 
         [0037]    Another embodiment is illustrated in  FIG. 4 . The embodiment of  FIG. 4  eliminates the offset down counter  92  of  FIG. 2  by loading either one of the upstream counter  86  or the downstream counter  90  with the value of the column address strobe CAS latency (L) minus the synchronization overhead (SP). If the calculated offset value is loaded into the upstream counter  86 , it is loaded as L-SP. This causes the count value in the upstream counter  86  to start from the value L-SP and have the correct tracking orientation relative to the downstream counter  90 . If, instead of loading the upstream counter  86 , the downstream counter  90  is loaded, the load value becomes −(L-SP). In either case, the relative timing difference between the two counters is correct according to the L value and the number of synchronization points in the timing control path. 
         [0038]    In  FIG. 4 , a line  402  illustrates the case where the upstream counter  86  is preload with the correct offset value while the line  404  illustrates the case where the downstream counter  90  is preloaded with the correct offset value. Those of ordinary skill in the art will realize that even though the above discussion contemplates the entire offset value being preloaded into one or the other of the counters, the offset value could be apportioned between the two counters, with the upstream counter  86  being advanced by a portion of the offset amount and the downstream counter retarded by the remainder of the offset amount. Finally,  FIG. 4  illustrates a circuit  400  for calculating the necessary offset values. The lines  402 ,  404  represent means such as conductors or traces for connecting the circuit  400  with either the upstream counter  86  or with the downstream counter  90 , respectively. Any known means for connecting, either directly or through other circuits, may be used. 
         [0039]      FIG. 5  illustrates an exemplary processing system  500  that utilizes DRAM memory device  12  in accordance with the embodiments of the present invention disclosed above in  FIGS. 1-4 .  FIG. 5  depicts an exemplary personal computer or work station architecture. The processing system  500  includes one or more processors  501  coupled to a local bus  504 . A memory controller  10  and a primary bus bridge  503  are also coupled to the local bus  504 . The processing system  500  may include multiple memory controllers  10  and/or multiple primary bus bridges  503 . The memory controller  10  and the primary bus bridge  503  may be integrated as a single device  506 . 
         [0040]    The memory controller  10  is also coupled to one or more memory buses  507 . Each memory bus accepts memory components  508  that include at least one memory device  12 . The memory components  508  may be a memory card or a memory module. Examples of memory modules include single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). The memory components  508  may include one or more additional devices  509 . For example, in a SIMM or DIMM, the additional device  509  might be a configuration memory, such as serial presences detect SPD memory. The memory controller  502  may also be coupled to a cache memory  505 . The cache memory  505  may be the only cache memory in the processing system. Alternatively, other devices, for example, processors  501  may also include cache memories, which may form a cache hierarchy with cache memory  505 . If the processing system  500  includes peripherals or controllers, which are bus masters or which support direct memory access DMA, the memory controller  10  may implement a cache coherency protocol. If the memory controller  10  is coupled to a plurality of secondary memory buses  516 , each secondary memory bus  516  may be operated in parallel, or different address ranges may be mapped to different memory buses  507 . 
         [0041]    The primary bus bridge  503  is coupled to at least one peripheral bus  510 . Various devices, such as peripherals or additional bus bridges may be coupled to the peripheral bus  510 . These devices may include a storage controller  511 , a miscellaneous I/O device  514 , a secondary bus bridge  515 , a multimedia processor  518 , and a legacy device interface  520 . The primary bus bridge  503  may also be coupled to one or more special purpose high-speed ports  522 . In a personal computer, for example, the special purpose port might be the Accelerated Graphics Port AGP, used to couple a high performance video card to the processing system  500 . 
         [0042]    The storage controller  511  couples one or more storage devices  513 , via a storage bus  512 , to the peripheral bus  510 . For example, the storage controller  511  may be a SCSI controller and storage devices  513  may be SCSI discs. The I/O device  514  may be any type of peripheral. For example, the I/O device  514  may be a local area network interface, such as an Ethernet card. The secondary bus bridge  515  may be used to interface additional devices  517  via a secondary bus  516  to the processing system. For example, the secondary bus bridge  515  may be a universal serial port USB controller used to couple USB devices  517  via bus  516  to the processing system  500 . The multimedia processor  518  may be a sound card, a video capture card, or any other type of media interface, which may also be coupled to an additional device such as speakers  519 . The legacy device interface  520  is used to couple legacy devices  521 , for example, older style keyboards and mice, to the processing system  500 . 
         [0043]    The processing system  500  illustrated in  FIG. 5  is only an exemplary processing system with which the present disclosure may be used. While  FIG. 5  illustrates a processing architecture especially suitable for a general purpose computer, such as a personal computer or a workstation, it should be recognized that well-known modifications could be made to configure the processing system  500  to become more suitable for use in a variety of applications. For example, many electronic devices that require processing may be implemented using a simpler architecture that relies on a CPU  501  coupled to memory components  508 . These electronic devices may include, but are not limited to, audio/video processors and records, gaming consoles, digital television sets, wired or wireless telephones, navigation devices (including system based on the global positioning system (GPS) and/or inertial navigation), and digital cameras and/or recorders. The modifications may include, for example, elimination of unnecessary components, addition of specialized devices or circuits, and/or integration of a plurality of devices. 
         [0044]    While the present invention has been described in connection with preferred embodiments thereof, those of ordinary skill in the art will recognize that many modifications and variations are possible. The present invention is intended to be limited only by the following claims and not by the foregoing description which is intended to set forth the presently preferred embodiment.