Abstract:
A charge pump circuit is provided which includes a plurality of successively coupled charge pump stages. Each of these successively coupled charge pump stages receives at least one input signals and at least one clock input signals, and in accordance therewith, conveys at least one output signal. Significantly, at least one output signal of a prior charge pump stage is substantially equal to at least one input signal of a next adjacent charge pump stage, so that the prior adjacent charge pump stage will be effectively shut off, so that reverse current flow can be prevented through the charge pump circuit.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention relates to voltage generation circuits, and more particularly, to a charge pump circuit suitable for use in flash memories which can be used for very low voltage operation. 
     BACKGROUND OF THE INVENTION 
     A flash memory is a type of nonvolatile memory cell that is electrically reprogrammable. Typically, the memory cells are arranged in an array of rows and columns. These memory cells typically include floating gate transistors. These transistors can be programmed or erased by applying voltage between a control electrode and the drain, source or substrate. The voltage applied during programming (V p ) or erasing (V e ) is a “high” voltage, higher than the input voltage, or V cc , necessitating a charge pump to pump the voltage from V cc  to V p  or V e . 
     The charge pump increases a small input voltage (for example, V cc ) into the larger voltages that are passed to the word lines and bit lines of semiconductor devices. These voltages affect the writing or erasing of data to and from the memory device. The charge pump usually includes a number of serially-connected pump stages that are driven by two non-overlapping clock signals. The serially-connected pump stages multiply the amplitude of the clock signals. The actual voltage obtained at the charge pump output terminal depends upon the number of pump stages, the clock frequency, and on the charge transfer efficiency of each pump stage. 
     Currently, charge pumps are constructed using several bootstrap capacitors having the same size capacitance (C) at each respective node of the charge pump. A bootstrap capacitor is simply a capacitor connected to each respective node of a charge pump. 
     As the input voltage V cc  decreases, due to the flash memory being used in low voltage environments, such as battery operation, the number of stages necessary to generate the same high output voltages also increases. Typically, the voltage required to program or erase a flash memory array is in the range of about 10 volts. 
     FIG. 1 shows a conventional prior art charge pump  1 . The prior art charge pump  1  consists of n stages, each stage is comprised of a diode means  2  and a capacitor  3 . Typically, the diode means  2  is a field effect transistor  2  with the gate terminal connected to a source/drain terminal causing the FET to act as a diode, and the capacitor  3  is coupled to the source/drain terminal of the field effect transistor  2 . 
     This capacitor  3  stores a charge V cc −V Th  at each successive stage, thereby increasing the voltage potential by V cc −V Th  at each successive stage. Thus, the current, I, across one stage n of the charge pump  1  is proportional to n(V cc −V Th ), where V Th  is the threshold voltage of the transistor  2  and n is the number of stages. Thus, at each stage, the voltage is pumped up proportional to n(V cc −V Th ). However, in this prior art charge pump  1 , reverse current flow is not prevented since adjacent transistors  2  are not switched OFF. 
     Thus, a drawback to prior art charge pumps is that as the number of stages increases, the power required to drive the charge pump also increases due to the increased number of capacitors in the charge pump and the reverse current flow. There is a need to reduce the size of these power supplies, by designing a more sophisticated charge pump which operates at a lower voltage than previous charge pumps, thereby reducing the amount of power needed to drive the device. 
     It is therefore desirable to provide a pump voltage circuit which can be used for very low voltage operation. 
     SUMMARY OF THE INVENTION 
     A charge pump circuit is provided which includes a plurality of successively coupled charge pump stages. Each of these successively coupled charge pump stages receives at least one input signal and at least one clock input signal, and in accordance therewith, generates at least one output signal. Significantly, at least one output signal of a prior adjacent charge pump stage is substantially equal to at least one input signal of a next adjacent charge pump stage, so that the prior adjacent charge pump stage will be effectively shut off, so that reverse current flow can be prevented through the charge pump circuit. 
     For example, the gate of transistor  110   a  is bootstrapped to avoid a threshold voltage drop V t  between input/output stages A and C. Therefore, the output current and voltage depend on V cc  and not on V cc −V t . 
     Additionally, the main capacitor  100   a  (referred to as the charge pump capacitor  100   a ) is utilized in stage n to precharge the capacitor  100   b  (referred to as the bootstrap capacitor  100   b ) at stage n+1 through transistor  100   b  thereby effectively negating the threshold voltage drop V t  between input/output stages A and D. Therefore, the precharge depends on V cc  and not on V cc −V t . 
     Moreover, different clock phases are not necessary for the charge pump capacitor  100   a  and the gate terminals of transistors  110   a  and  110   b . Therefore, the charge pump can operate at a very high frequency. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified charge pump circuit of the prior art. 
     FIG. 2A is a simplified circuit diagram of one embodiment of the initial charge pump stage component module of the charge pump circuit of the present invention, 
     FIG. 2B is a simplified circuit diagram of one embodiment of the clock signal generator component module of the charge pump circuit of the present invention. 
     FIG. 2C is a simplified schematic diagram showing the inputs and outputs of a charge pump stage of the charge pump circuit of the present invention. 
     FIG. 3 is a circuit diagram of a boost inverter circuit component of the clock signal generator shown in FIG.  2 B. 
     FIG. 4 is a detailed circuit diagram of one stage of the charge pump circuit shown in FIG.  2 C. 
     FIG. 5 is a circuit diagram of another embodiment of the clock signal generator component module of the charge pump circuit of the present invention. 
     FIG. 6 is a schematic diagram of a charge pump of the present invention using the components shown in FIG. 2A,  2 B and  2 C. 
     FIG. 7A is a representation of two successive charge pump stages of the charge pump circuit. 
     FIG. 7B is a diagram of the potentials at various nodes shown in FIG. 7A during the time variance t 1  to t 4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Several separate circuit components  11 ,  12 ,  14  comprise the charge pump circuit  10  which is shown in FIG.  6 . FIG. 6 shows a simple schematic diagram of the charge pump circuit  10 . Note that the charge pump circuit is composed of the various circuit modules described herein with reference to FIGS. 2A-C. Note also that the input clock signals CLK 1 /CLK 2  and CLK 3 /CLK 4  are received by alternate circuit stages (represented by the block “FIG.  2 C” in FIG.  6 ). 
     FIG. 2A shows a voltage source coupling circuit  11 . This circuit  11  comprises first and second transistors  20  having their input terminals connected to voltage source V cc . The gate terminals of these transistors  20  are connected to a clock signal, i.e. CLK 1  or CLK 3  (clock signal CLK 3  will be the complemented signal of clock signal CLK 1 ). Thus, depending on the logic level of the clock signal, the transistors  20  will be switched ON passing V cc  to the component  14 , or switched OFF, in which case no voltage is passed to the component  14 . 
     Another component  12 , shown in FIG. 2B, is a clock signal generator circuit  12 . That is, the clock signal CLKIN is split into four separate signals, CLK 1 , CLK 2 , CLK 3  and CLK 4 . The circuit  12  comprises a plurality of inverters  30  and a voltage amplification inverter circuit  13 . In the signal splitting circuit  12 , the signal CLK 1  is generated from a pair of series connected inverters  30  which receives as its input the signal CLKIN. Therefore, CLK 1  has the same characteristics as CLKIN. However, signal CLK 2  is generated from voltage amplification inverter circuit  13  (which will be explained in detail later in reference to FIG.  3 ). Thus, signal CLK 2  will be the amplified complementary signal of CLK 1 . Signals CLK 3  and CLK 4  mirror respective signals CLK 1  and CLK 2 , except that signals CLK 3  and CLK 4  are the inverse of signals CLK 1  and CLK 2 . This is accomplished by addition of another inverter  30  prior to a node  31 . 
     Referring to FIG. 2C, a charge pump cell component  14  is shown. The charge pump cell  14  receives input signals A and B from the voltage source coupling circuit  11 , or from outputs C and D of another pump cell  14 , and signals CLK 1  and CLK 2 , or CLK 3  and CLK 4  from the clock splitting circuit  12 . Signals C and D will be output to the next stage n+1, in which signal C is supplied as input signal A, and signal D is supplied as input signal B of the previous stage n. Stage n+1 will receive clock signals CLK 3  and CLK 4  which mirror clock signals CLK 1  and CLK 2  except that signals CLK 3  and CLK 4  are the inverse of signals CLK 1  and CLK 2 . Thus, adjacent stages will receive inverted clock signals CLK 1 /CLK 3  and CLK 2 /CLK 4 . 
     FIG. 3 shows the boost inverter circuit  13 . This circuit  13  comprises a CMOS inverter  50 , an inverter  60 , a capacitor  70 ; and a transistor  80 . The CMOS inverter  50  has its gate terminals controlled by signal CLKIN or the signal at node  31 . 
     Transistor  80  has its source terminal connected to voltage source V cc . The cathode terminal of a capacitor  70  is coupled to the drain terminal of transistor  80  which is coupled to the CMOS inverter  50  at a common node  51 . The anode terminal of the capacitor  70  is connected to the output of inverter  60  whose input receives signal CLKIN or the inverse thereof at node  31 . it should be noted that transistor  80  is a depletion type p-channel device, as is the p-channel device of the CMOS inverter  50 . 
     In operation, when the input signal at node A is V cc , the inverter  50  is ON. This leads to node B pulled down to 0V. With node B at 0V, transistor  80  turns ON causing V cc  to be supplied to the cathode terminal of capacitor  70 . The anode terminal of capacitor  70  is at 0V (the output of inverter  60 ). This then causes the difference of V cc  to be stored in the capacitor  70 . 
     When the input signal at node A is 0V, the output of inverter  60  is at V cc . This then pumps the cathode terminal of capacitor  70  to 2V cc . With node A at 0V, it turns ON the PMOS transistor of the inverter and causes node B to be connected to the cathode terminal of capacitor  70  (2V cc ) 
     Thus, referring back to FIG. 2B, clock signals CLK 2  and CLK 4  will range from 0V to 2V cc , where CLK 4  is the inverse of signal CLK 2 . 
     FIG. 4 shows the voltage pump cell  14 . Each voltage pump cell  14  is one stage n of the charge pump  10 . Each charge pump cell  14  comprises a first and second capacitor  100   a  and  100   b , a first and second transistor  110   a  and  110   b , a diode  120  and an inverter  130 . First and second transistors  110   a  and  110   b  have their drain terminals connected to the input terminal A, whereas the source terminal of transistor  110   a  is connected to the output terminal C and the source terminal of transistor  110   b  is connected to the output terminal D. The gate terminals of transistors  110   a  and  110   b  are connected to input terminal B. Further, a capacitor  100   b  is coupled to the gates of transistors  110   a  and  110   b  and to input terminal B at a common node  111 . Clock signal CLK 2  or CLK 4  is supplied to another terminal of capacitor  100   b.    
     The cathode terminal of capacitor  100   a  is coupled to the drain terminals of transistors  110   a  and  110   b , through common node  101 , whereas the anode terminal of the capacitor  100   a  is connected to an inverter  130  which is connected to a clock input terminal to receive clock signal CLK 1  or CLK 3 . The diode  120  has its first end coupled to the drain terminals of transistors  110   a  and  110   b , through the common node  101 , whereas its second end is connected to a voltage source V cc . 
     Capacitor  100   b  is a bootstrap type, which pulls down the stage, when the transistors switch OFF, thereby ensuring no reverse current flows through the charge pump cell  14 . This shutting off feature is effectuated by the like amplitudes of input signal B of a prior adjacent stage and input signal A of a successive adjacent stage. Since they are equal, this ensures the transistors  110   a  and  110   b  are OFF and that no reverse current flows. 
     For example, FIG. 7A shows two successive charge pump stages, referenced “Stage 1” and “Stage 2” in FIG.  7 A. In FIG. 7A, Stage 1 is intended to be the initial stage of the charge pump circuit  10  and Stage 2 is intended to be a charge pump cell  14  in the charge pump circuit  10 . Each of the charge pump stages shown in FIG. 7A comprises a charge pump cell  14  as illustrated in FIG. 4, and described herein. With reference to FIG. 7A, the following nodes are of interest in illustrating the switching feature of the present invention. Node  150  represents an input of Stage 1, in this case signal CLK 1 . Node  151  represents another input of Stage 1, in this case signal CLK 2 . Node  152  represents the output of the inverter  130  of Stage 1. Node  153  represents the potential at the cathode terminal of capacitor  100   a . Finally, node  154  represents yet another input of Stage 1, in this case input B. 
     Node  155  represents an input of Stage 2, in this case signal CLK 3 . Node  156  represents another input of Stage 2, in this case signal CLK 4 . Node  157  represents yet another input of Stage 2, in this case input B, which is the output D of Stage 1. Node  158  represents yet another input of Stage 2, in this case input A, which is the output C of Stage 1. Node  159  represents the output of the inverter  130  of Stage 2. Node  160  represents an output of Stage 2, in this case output D. Finally, node  161  represents another output of Stage 2, in this case output C. 
     FIG. 7B is a diagram of the potentials of each of the nodes referenced in FIG. 7A at different times t 1 , to t 4 . As shown in FIG. 7B, at a time t 1 , the nodes have the following potentials: node  150 , V cc  (signal CLK 1 ); node  151 , 0 (complementary relationship between signal CLK 1  and CLK 2 ); node  152 , 0; nodes  153  and  154 , V cc ; node  155 , 0 (signal CLK 3  and signal CLK 1  are complementary); node  156 , 2V cc  (due to the effects of circuit  13  shown in FIG.  3 ); node  159 , V cc . The potentials at nodes  157 ,  158 ,  160  and  161  are unknown since these nodes are effectively blocked due to the switching feature described earlier. 
     At time t 2 , the nodes have the following potentials. Node  150 , 0; node  151 , 2V cc  (due to the effect of circuit  13  shown in FIG.  3 ); node  152 , V cc ; node  153 , 2V cc  (due to the charge on the capacitor  100   a  of Stage 1); node  154 , 3V cc  (due to the charge on capacitor  100   b  of Stage 1); node  155 , V cc ; node  156 , 0; node  159 , 0. 
     At time t 2 , node  157  has a potential of 2V cc , which is the output D from Stage 1. Also, node  158  has a potential of 2V cc  which is the output C from Stage 1. However, nodes  160  and  161  are still blocked and their potentials are unknown due to the switching feature of the present invention. 
     At time t 3 , the nodes will have the same potentials as the nodes at time t 1 , except that at time t 3 , node  157  has a potential of 4V cc , which is the output D from Stage 1. Node  158  has a potential of 3V cc  which is the output: C from Stage 1. 
     At time t 3 , Stage 1 and Stage 2 are no longer blocked, and now the potentials at nodes  160  and  161  can be determined, and are each 3V cc . 
     Finally, at time t 4 , the nodes will have the same potentials as the nodes at time t 2 , except that at time t 4 , since Stage 1 and Stage 2 are no longer blocked, the potentials at nodes  160  and  161  can be determined, and are each 3V cc . 
     A second embodiment of the clock signal generator component of the charge pump  10  is shown in FIG.  5 . Similarities between this embodiment and the previous embodiment need not be explained here, as their operation is the same. However, what is different in this embodiment is the composition of the clock splitting circuit  16 , shown in FIG.  5 . In the second embodiment, the clock signal CLKIN is split into four separate signals, CLK 1 , CLK 2 , CLK 3  and CLK 4 , just as in the first embodiment. However, in this second embodiment, the circuit  16  comprises a plurality of inverters  30 , a boost inverter circuit  13 , and a plurality of NAND gates  40   a ,  40   b.    
     Initially, the CLKIN signal, together with an enable signal EN and clock signal CLK 3  are compared through a three-input NAND gate  40   a , and the signal CLK 1  is generated by propagating the output of the NAND gate  40   a  through a pair of series connected inverters  30 . 
     However, signal CLK 2  is generated propagating the output of the NAND gate  40   a  through voltage amplification inverter circuit  13 . Thus, signal CLK 2  will be the amplified complementary signal of CLK 1 . 
     Likewise, signals CLK 3  and CLK 4  mirror respective signals CLK 1  and CLK 2 , except that signals CLK 3  and CLK 4  are the inverse of signals CLK 1  and CLK 2 . This is accomplished by inverting the CLKIN signal and comparing that inverted signal with enable signal EN and signal CLK 1  by NAND gate  40   b . This output from the NAND gate  40   b  is then propagated through two inverters  30  to generate signal CLK 3 , or a voltage amplification circuit  13  to generate signal CLK 4 . Thus, this ensures CLK 1 /CLK 3  and CLK 2 /CLK 4  do not overlap, i.e. CLK 1 /CLK 3  are complementary and CLK 2 /CLK 4  are complementary. 
     In this disclosure, there is shown and described only the preferred embodiment of the invention, but, as aforementioned, it is to be understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.