Abstract:
A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W 2  and a second dimension W 3  in the reference direction, wherein CD&lt;W 2 &lt;2D&lt;W 3.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to SIT (sidewall image transfer) processes and more particularly to SIT processes for forming multiple line-widths. 
   BACKGROUND OF THE INVENTION 
   In the prior art, a conventional lithographic process can be used to form a first line-width greater than or equal to a minimum CD (critical dimension) associated with the lithographic process, or a SIT process can be used to form a second line-width smaller than the CD. Therefore, there is a need for a method for simultaneously forming multiple line-widths greater than and smaller than the CD. 
   SUMMARY OF THE INVENTION 
   The present invention provides a structure fabrication method, comprising providing a structure which includes (a) a memory layer, and (b) a sidewall image transfer (SIT) layer on top of the memory layer; patterning the SIT layer, resulting in a SIT region, wherein said patterning comprises a lithographic process; directionally etching the memory layer with the SIT region as a mask, resulting in a first memory region; and retreating a side wall of the SIT region a retreating distance D in a reference direction, resulting in a SIT portion comprising said side wall, wherein the retreating distance D is less than a critical dimension CD associated with the lithographic process, wherein the first memory region includes a first dimension W 2  and a second dimension W 3  in the reference direction, and wherein CD&lt;W 2 &lt;2D&lt;W 3 . 
   The present invention provides a method for simultaneously forming multiple line-widths greater than and smaller than the CD. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIGS. 1-14A  illustrate the formation of a first semiconductor structure, in accordance with embodiments of the present invention. 
       FIGS. 15-23  illustrate the formation of a second semiconductor structure, in accordance with embodiments of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIGS. 1-14A  (perspective views) illustrate the fabrication of an integrated circuit component  100 , in accordance with embodiments of the present invention. The fabrication of the integrated circuit component  100  can be started with the component  100  of  FIG. 1  which comprises (i) a gate electrode layer  110 , (ii) a memory layer  120  on top of the gate electrode layer  110 , and (iii) a SIT (sidewall image transfer) layer  130  on top of the memory layer  120 . It should be noted that the gate electrode layer  110  is formed on a wafer which is not shown for simplicity. In one embodiment, the gate electrode layer  110  comprises polysilicon, the memory layer  120  comprises silicon nitride, and the SIT layer  130  comprises SiO 2  (silicon dioxide). 
   Next, with reference to  FIG. 2 , in one embodiment, a photo resist layer  210  is formed on top of the SIT layer  130 . The photo resist layer  210  can be formed by spin applying a photo resist material on top of the integrated circuit component  100  of  FIG. 1 . 
   Next, in one embodiment, the photo resist layer  210  is patterned using a conventional lithographic process, resulting in a patterned photo resist layer  210 ′ as shown in  FIG. 3 . 
   With reference to  FIG. 3 , assume that W 1  and W 2  are two dimensions of the patterned photo resist layer  210 ′. It should be noted that W 1  and W 2  are greater than CD (critical dimension). Critical dimension is a smallest dimension of geometrical features (width of interconnect line, contacts, trenches, etc.) which can be practically formed without any deformation or distortion during semiconductor device/circuit manufacturing. It should be noted that the critical dimension is associated with said patterning process described in  FIG. 3 . 
   Next, with reference to  FIG. 3 , in one embodiment, the patterned photo resist layer  210 ′ is used as a mask during directional etching of the SIT layer  130 , resulting in a SIT region  130 ′, as shown in  FIG. 4 . This directional etching process can be a RIE (reactive ion etching) process. 
   Next, with reference to  FIG. 4 , in one embodiment, the patterned photo resist layer  210 ′ is removed using a wet etching process, resulting in the component  100  of  FIG. 5 . 
   Next, with reference to  FIG. 5 , in one embodiment, the SIT region  130 ′ is used as a mask during directional etching of the memory layer  120 , resulting in a memory region  120 ′, as shown in  FIG. 6 . This etching process can be a RIE process. 
   Next, with reference to  FIG. 6 , in one embodiment, SIT regions  130 ′ is isotropically etched, using a process such as COR (chemical oxide removal), resulting in a SIT region  130 ″, as shown in  FIG. 7   
   With reference to  FIG. 7 , it should be noted that a portion  125  and a portion  126  of the memory region  120 ′ have the widths W 1  and W 2 , respectively. D is a distance by which the sidewalls of the SIT region  130 ″ retreat from their original positions as a result of the COR process. Assume that D&lt;W 1 &lt;W 2 &lt;2D&lt;W 3 , wherein W 3  is the width of portion  127  of the memory region  120 ′. Assume further that D&lt;CD. As a result, the COR process results in the SIT portion  130 ″ of the SIT region  130 ′ ( FIG. 6 ) only on the region  127  of the memory region  120 ′ as shown in  FIG. 7 . For example, CD=10 nm (nanometer), W 1 =14 nm, W 2 =16 nm, W 3 =30 nm, and D=9 nm. 
   Next, with reference to  FIG. 8 , in one embodiment, a protective layer  810  is formed on top of the component  100  of  FIG. 7 . The protective layer  810  can comprise polymer. Illustratively, the protective layer  810  is formed by spin applying polymer on top of the component  100  of  FIG. 7 . 
   Next, in one embodiment, the protective layer  810  is etched back such that a top surface  131  of the SIT region  130 ″ is exposed to the surrounding ambient as shown in  FIG. 9 . This etching process can be wet etching or RIB process. In one embodiment, the etching process is selective to the SIT region  130 ″. What remains of the protective layer  810  of  FIG. 8  after this etching process can be referred to as a protective layer  810 ′ as shown in  FIG. 9 . Memory layer  120 ′ ( FIG. 7 ) must remain everywhere protected by the protective layer  810 ′ following this etching process. A reference direction  101  is directed from a planar side wall  128  of the memory layer  120 ′ to a plane comprising a side wall  136  of the SIT region  130 ″, wherein the reference direction  101  is perpendicular to the planar side wall  128 . 
   Next, with reference to  FIG. 9 , in one embodiment, the SIT region  130 ″ is removed. The SIT region  130 ″ can be removed using a wet etching process, resulting in a hole  1010  in the protective layer  810 ′, as shown in  FIG. 10 . In one embodiment, this wet etching process is selective to the protective layer  810 ′ and the memory region  120 ′ such that a top surface  121 ′ of the memory region  120 ′ (can also be seen in  FIG. 7 ) is exposed to the surrounding ambient through the hole  1010 . 
   Next, with reference to  FIG. 10 , in one embodiment, the protective layer  810 ′ is used as a blocking mask during directional etching of the memory region  120 ′, resulting in a hole  1010 ′ and a memory region  120 ″, as shown in  FIG. 11 . More specifically, the memory region  120 ′ ( FIG. 10 ) is etched using RIE process such that a top surface  111  of the gate electrode layer  110  is exposed to the surrounding ambient through the hole  1010 ′ ( FIG. 11 ). 
   Next, with reference to  FIG. 11 , in one embodiment, the protective layer  810 ′ is removed, resulting in component  100  of  FIG. 12 . More specifically, the protective layer  810 ′ is removed by a wet etching process. 
   Next, with reference to  FIG. 12 , in one embodiment, the memory region  120 ″ is further patterned, resulting in a memory region  120 ′″, as shown in  FIG. 13 . More specifically, the memory region  120 ″ can be patterned using lithographic and etching processes. This patterning removes undesired portions of the memory region  120 ″. 
   Next, with reference to  FIG. 13 , in one embodiment, the memory region  120 ′″ is used as a blocking mask during directional etching of the gate electrode layer  110 , resulting in a patterned gate electrode region  110 ′, as shown in  FIG. 14 . Illustratively, the gate electrode layer  110  can be etched using a RIE process. 
   Next, with reference to  FIG. 14 , in one embodiment, the memory region  120 ′″ is removed using a wet etching process, resulting in the patterned gate electrode region  110 ′ of component  100  of  FIG. 14A . 
   As a result of the fabrication process from  FIG. 1  to  FIG. 14A , a portion  115 , a portion  116  and a portion  117  of the patterned gate electrode layer  110 ′ has the widths W 1 , W 2 , and D, respectively. As mentioned above, the width D is less than critical dimension. Besides, the widths W 1  and W 2  are greater than CD. In other words, the fabrication process of  FIG. 1-14A  forms the patterned gate electrode region  110 ′ having different dimensions greater and smaller than CD. In one embodiment, the portion  115  can be used to form a gate electrode of a pFET (not shown), the portion  116  can be used to form a connection, and the portion  117  is used to form a gate electrode of an nFET (not shown). 
   In summary, the fabrication process of  FIGS. 1-14A  provides the component  100  of  FIG. 14A  having dimensions greater than and less than CD (W 1 &gt;CD, W 2 &gt;CD, D&lt;CD). These portions can be used for different purposes. 
     FIGS. 15-20  (perspective views) illustrate a fabrication process of an integrated circuit component  1500 , in accordance with embodiments of the present invention. More specifically, with reference to  FIG. 15 , the fabrication process can be started with providing a gate electrode layer  1510 . The gate electrode layer  1510  can comprise polysilicon. It should be noted that the gate electrode layer  1510  is formed on a wafer which is not shown for simplicity. 
   Next, with reference to  FIG. 16 , in one embodiment, a mandrel layer  1610  is formed on top of the gate electrode layer  1510 . The mandrel layer  1610  can be formed by CVD (chemical vapor deposition) of SiO 2  everywhere on top of the gate electrode layer  1510 . 
   Next, in one embodiment, the mandrel layer  1610  is patterned, resulting in mandrel regions  1610   a  and  1610   b , as shown in  FIG. 17 . More specifically, the mandrel layer  1610  can be patterned using lithographic and etching processes. 
   It should be noted that, a dimension W 5  is a distance between the mandrel regions  1610   a  and  1610   b . The dimension W 5  is greater than the CD associated with the lithography processes above 
   Next, with reference to  FIG. 18 , in one embodiment, a spacer layer  1810  is formed on top of the component  1500  of  FIG. 17 . The spacer layer  1810  can comprise silicon nitride. In one embodiment, the spacer layer  1810  is formed by CVD of silicon nitride everywhere on top of the component  1500  of  FIG. 17  such that the silicon nitride material covers all the mandrel regions  1610   a  and  1610   b.    
   Next, in one embodiment, the spacer layer  1810  is anisotropically etched back, resulting in spacer regions  1810   a  and  1810   b  on side walls of the mandrel regions  1610   a  and  1610   b , respectively, as shown in  FIG. 19 . More specifically, the spacer layer  1810  can be etched using RIE process. 
   It should be noted that, a dimension D 5  is a width of the spacer regions  1810   a  and  1810   b . In one embodiment, this etching back process is performed such that D 5 &lt;CD, and W 5 &lt;2×D 5 . The condition that W 5 &lt;2=D 5  ensures that the two spacer regions  1810   a  and  1810   b  remain in direct physical contact with each other. For example, CD=10 nm, W 5 =14 nm, and D 5 =8 nm. 
   Next, with reference to  FIG. 19 , in one embodiment, the mandrel regions  1610   a  and  1610   b  are removed, resulting in component  1500  of  FIG. 20 . More specifically, the mandrel regions  1610   a  and  1610   b  can be removed using a wet etching process. The wet etching process is selective to the spacer regions  1810   a  and  1810   b.    
   Next, with reference to  FIG. 20 , in one embodiment, the spacer regions  1810   a  and  1810   b  are used as masks during directional etching of the gate electrode layer  1510 , resulting in gate electrode regions  1510   a  and  1510   b , as shown in  FIG. 21 . The gate electrode layer  1510  can be patterned using a RIE process. 
   Next, with reference to  FIG. 21 , in one embodiment, the spacer regions  1810   a  and  1810   b  are removed, resulting in component  1500  of  FIG. 22 . More specifically, the spacer regions  1810   a  and  1810   b  can be removed using a wet etching process. 
   Next, with reference to  FIG. 22 , in one embodiment, the gate electrode regions  1510   a  and  1510   b  are further patterned using lithographic and etching processes, resulting in a gate electrode region  1510 ′ of  FIG. 23 . This further patterning removes undesired portions of the spacer regions  1810   a  and  1810   b.    
   Next, in one embodiment, additional fabrication steps can be performed on different portions of the gate electrode region  1510 ′ of  FIG. 23  to form different semiconductor devices (not shown). 
   In summary, the fabrication process of  FIGS. 15-23  provides the component  1500  of  FIG. 23  having different portions with different dimensions greater than and less than CD (W 5 &gt;CD, and D 5 &lt;CD). These portions can be used for different purposes. 
   While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.