Abstract:
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, a first gate insulating layer, a second gate insulating layer, a first gate electrode, and a second gate electrode. The semiconductor substrate is divided into a first region and a second region. The first gate insulating layer is formed on the first region. The second gate insulating layer is formed on the second region and formed thinner than the first gate insulating layer. The first gate electrode is formed on the first gate insulating layer. The second gate electrode is formed on the second gate insulating layer and formed thicker than the first gate electrode

Description:
RELATED APPLICATION  
       [0001]     This application claims the benefit, under 35 U.S.C. §119(e), of Korean Patent Application Number 10-2005-0061708 filed Jul. 8, 2005, which is incorporated herein by reference in its entirety.  
       FIELD OF INVENTION  
       [0002]     The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.  
       BACKGROUND OF INVENTION  
       [0003]     Generally, a metal-oxide semiconductor (MOS) device includes channels that are passages for current flowing immediately beneath an oxide layer of a semiconductor substrate. The channels are formed by a bias applied between a metal layer and the semiconductor substrate. Additionally, the channels are controlled by bias values.  
         [0004]     Precipitated by recent developments in semiconductor manufacturing, gate oxide layers are becoming thinner, and dual gate oxide layers are being used.  
         [0005]     Specifically, dual gate oxide layers are being formed with different thicknesses in order to form transistors having different operating voltage characteristics on the same substrate.  
         [0006]     When the thickness of the gate oxide layer is made relatively thin, depletion of polysilicon used as gate electrodes and penetration of boron or other dopants into the silicon occur.  
         [0007]     It should be noted that the polysilicon depletion and boron penetration are mutually contradictory phenomena.  
         [0008]     When the dopant concentration of the gate electrode polysilicon is reduced near the gate oxide layer, capacitance values between inversion and accumulation of a transistor become different. That is, the capacitance value during transistor inversion decreases, inducing deterioration of the transistor&#39;s characteristics.  
         [0009]     On the other hand, when the dopant concentration of the gate electrode polysilicon is increased near the gate oxide layer, dopants for the gate electrode spread to a silicon interface of the transistor. In this way, the transistor&#39;s characteristics deteriorate. This phenomenon becomes severe as the thickness of the gate oxide layer becomes increasingly thinner.  
       BRIEF SUMMARY OF THE INVENTION  
       [0010]     An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can increase the concentration of poly around a gate oxide layer at a region where the gate oxide thickness of the gate oxide layer is high.  
         [0011]     Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can increase poly depletion characteristics and reduce resistance.  
         [0012]     Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof capable of blocking dopant penetration at a region of a gate oxide layer having a low gate oxide thickness.  
         [0013]     To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a semiconductor device including: a semiconductor substrate having a first region and a second region; a first gate insulating layer formed on the first region; a second gate insulating layer formed on the second region and formed thinner than the first gate insulating layer; a first gate electrode formed on the first gate insulating layer; and a second gate electrode formed on the second gate insulating layer and formed thicker than the second gate electrode.  
         [0014]     In another aspect of the present invention, there is provided a manufacturing method of a semiconductor device, including: forming a first gate insulating layer on a first region of a semiconductor substrate; forming a second gate insulating layer that is thinner than the first gate insulating layer on a second region of the semiconductor substrate; forming a first gate electrode on the first gate insulating layer; forming a second gate electrode on the second gate insulating layer by forming an insulating layer on the first region of the semiconductor substrate including the first gate electrode, forming a polysilicon layer on an entire surface of the semiconductor substrate, and selectively etching the polysilicon layer; removing the insulating layer on the first region after forming the second gate electrode; and doping the first gate electrode and the second gate electrode with dopant ions. 
     
    
     BRIEF DESCRIPTION OF DRAWINGS  
       [0015]      FIG. 1  is a sectional view of a semiconductor device according to an embodiment of the present invention.  
         [0016]      FIGS. 2A through 2G  are sectional views showing a manufacturing method of a semiconductor device according to an embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]      FIG. 1  is a sectional view of a semiconductor device according to an embodiment of the present invention.  
         [0018]     Referring to  FIG. 1 , a semiconductor device according to an embodiment of the present invention can incorporate a semiconductor substrate  101  having a first region and a second region. The first region can be used to form transistors having one type of operating voltage characteristics and the second region can be used to form transistors having another type of voltage characteristics. The device can incorporate a first gate insulating layer  103  and a second gate insulating layer  102  formed respectively on the first region and the second region of the semiconductor substrate  101  where the first gate insulating layer  103  and the second gate insulating layer  102  can have different thicknesses. The device can also incorporate a first gate electrode  104  and a second gate electrode  106  formed respectively on the first and second regions where the first gate electrode  104  and the second gate electrode  106  can have different thicknesses.  
         [0019]     In one embodiment, the first gate insulating layer  103  formed on the first region can be formed thicker than the second gate insulating layer  102  formed on the second region.  
         [0020]     In a specific embodiment, the second gate insulating layer  102  can be 30-50% of the thickness of the first gate insulating layer  103 .  
         [0021]     In an embodiment example, the second gate insulating layer  102  may be 21 Å, and the first gate insulating layer  103  may be 52 Å.  
         [0022]     In one embodiment, the second gate electrode  106  formed on the second region can be formed thicker than the first gate electrode  104  formed on the first region.  
         [0023]     In a specific embodiment, the second gate electrode  106  can be formed to be 110-130% of the thickness of the first gate electrode  104 .  
         [0024]     In an embodiment example, the second gate electrode  106  may be 1800 Å, and the first gate electrode may be 1500 Å.  
         [0025]     In an embodiment, the concentration of dopant in the first gate insulating layer  103  can be higher than the concentration of dopant in the second gate insulating layer  102 .  
         [0026]     In a specific embodiment, an ion implantation target point “A” can be set at different points for the first gate electrode  104  and the second gate electrode  106  such that the concentration of dopant on the first gate insulating layer  103  is higher than that of dopant on the second gate insulating layer  102 .  
         [0027]     Accordingly, embodiments of the present invention can increase the poly (dopant) concentration near a gate oxide at a high gate oxide thickness region to improve the poly depletion characteristics and reduce resistance.  
         [0028]     The gate electrode can be thickly formed at the region where the gate oxide thickness is low in order to prevent dopant penetration.  
         [0029]     Below, a manufacturing method of a semiconductor device according to an embodiment the present invention will be described with reference to the  FIGS. 2A through 2G .  
         [0030]     Referring to  FIG. 2A , a first gate insulating layer  103  and a second gate insulating layer  102  with mutually different thicknesses can be formed on a semiconductor substrate  101 . The first gate insulating layer  103  can be formed in a first region of the semiconductor substrate  101  and the second gate insulating layer  102  can be formed in a second region of the semiconductor substrate  101 .  
         [0031]     In a specific embodiment, the second gate insulating layer  102  can have a thickness of approximately 30-50% of the first gate insulating layer  103 .  
         [0032]     In an embodiment example, the second gate insulating layer  102  may be 21 Å, and the first gate insulating layer  103  may be 52 Å.  
         [0033]     In one embodiment, the forming method of the first and second insulating layers  102  and  103  having different respective thicknesses can be as follows.  
         [0034]     A first oxidation process can be performed to form a predetermined original insulating layer (not shown) on the entire surface of semiconductor substrate  101  intended for a predetermined gate insulating layer.  
         [0035]     Then, the portion of the original insulating layer on the second region can be etched and removed to form a stepped insulating layer between the first and second regions.  
         [0036]     In a further embodiment, a second thermal oxidation can be performed to form a secondary insulating layer on the entire surface of the semiconductor substrate  101  including where the original insulating layer is etched away on the second region. Accordingly, the first gate insulating layer  103  can be made of the original insulating layer and the secondary insulating layer on the first region, and the second gate insulating layer  102  can be made of the secondary insulating layer on the second region.  
         [0037]     The first gate insulating layer  103  and the second gate insulating layer  102  can be formed of an oxide layer or a nitride layer.  
         [0038]     In another embodiment, the forming method of the first and second gate insulating layers  103  and  102  can be described as follows.  
         [0039]     First, a first oxidation process can be performed on the entire surface of the semiconductor substrate  101  to form an original insulating layer (not shown) for a predetermined gate insulating layer.  
         [0040]     Then, oxide ions can be implanted into the original insulating layer on the first region.  
         [0041]     Subsequently, a second oxidation process can be performed to form the first gate insulating layer  103  higher on the first region than the remaining surface of the semiconductor substrate.  
         [0042]     Accordingly, the original insulating layer forms the second gate insulating layer  102 , and the original insulating layer that undergoes oxide ion implantation and a second thermal process forms the first gate insulating layer  103 .  
         [0043]     Referring to  FIG. 2B , a first polysilicon layer can be deposited on the entire surface of the semiconductor substrate  101 . The first polysilicon layer can be selectively removed through photo and etching processes, whereupon a first gate electrode can be formed on a certain portion of the first region.  
         [0044]     Referring to  FIG. 2C , an insulating layer  105  can be formed on the entire surface of the semiconductor device  101  including the first gate electrode  104 . A selective patterning using photo and etching processes can be performed so that the insulating layer  105  only remains on the first region. In a specific embodiment, the insulating layer  105  of the first region can be a nitride layer.  
         [0045]     Referring to  FIG. 2D , a second polysilicon layer  106   a  can be deposited on the entire surface of the semiconductor substrate including the remaining insulating layer  105 .  
         [0046]     Referring to  FIG. 2E , in a further embodiment, an anti-reflection layer  107  can be formed on the second polysilicon layer  106   a.  A photoresist  108  can be applied to the anti-reflection layer  107  and a gate region defined through patterning with light exposing and developing processes.  
         [0047]     The anti-reflection layer  107  can be used to ensure that the pattern for the photoresist is formed properly.  
         [0048]     Referring to  FIG. 2F , the anti-reflection layer  107  and the second polysilicon layer  106   a  can be selectively removed using the patterned photoresist  108  as a mask to form a second gate electrode  106  on a predetermined portion of the second region.  
         [0049]     In one embodiment, the second gate electrode  106  can be formed to be thicker than the first gate electrode  104 .  
         [0050]     In a specific embodiment, the second gate electrode  106  can be formed to be 110-130% the thickness of the first gate electrode  104 .  
         [0051]     In an embodiment example, the second gate electrode  106  may be formed to be 1800 Å, and the first gate electrode  104  may be formed to be 1500 Å.  
         [0052]     In embodiments, when the second polysilicon layer  106   a  for forming the second gate electrode  106  is etched, the first gate electrode  104  can be protected by the insulating layer  105  formed on the first region.  
         [0053]     Also, when the second polysilicon layer  106   a  is etched, an etching selection ratio for the insulating layer  105  can be used. In a further embodiment, a fluorine (F)-type gas can be used for etching the second polysilicon layer  106   a.    
         [0054]     Then, the photoresist  108 , the anti-reflection layer  107 , and the insulating layer  105  can be removed.  
         [0055]     Referring to  FIG. 2G , ions can be implanted into the first and second gate electrodes. In one embodiment, the dopant ion can be boron.  
         [0056]     In a specific embodiment, in order to raise the dopant, an implanted ion implantation target point (A) can be different at the first gate electrode  104  formed on the first gate insulating layer  103  and the second gate electrode  106  formed on the second gate insulating layer  102 .  
         [0057]     That is, in the stage of doping the dopant ions, in the case of the first region, an ion implantation target point can be disposed above the boundary between the first gate insulating layer  103  and the first gate electrode  104 . The dopant concentration at the first gate insulating layer  103  is made higher then that of the second gate insulating layer  102 .  
         [0058]     For example, in the doping process of the dopant ions, the ion implantation target point rises 10-100 Å from the boundary between the first gate insulating layer  103  and the first gate electrode  104 , so that the dopant concentration at the first gate insulating layer  103  is higher than that of the second gate insulating layer  102 .  
         [0059]     Additionally, the ion implantation target point is disposed at the bottom of the second gate electrode  106  on the second region, so that the dopant concentration at the second gate insulating layer  102  is lower than that at the first gate insulating layer  103 .  
         [0060]     The present invention can produce the following effects.  
         [0061]     First, embodiment of the present invention can raise the concentration of dopant at the thicker first gate insulating layer  103  having low dopant penetration, so that polysilicon depletion can be reduced, which increases the characteristics of the semiconductor device. Also, the thickness of the first gate electrode  104  can be reduced to produce the effect of lowering the gate resistance.  
         [0062]     On the other hand, the dopant concentration at the thin second gate insulating layer  102  with a high dopant penetration is reduced, so that the effects of dopant penetration can be reduced.  
         [0063]     In another embodiment of the present invention, a gate insulating layer having another thickness can be formed, a thin gate insulating layer can be formed on a thick gate insulating layer, and conversely, a thick gate electrode can be formed on a thin gate insulating layer.  
         [0064]     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.