Abstract:
A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data address pointers for evaluating a polynomial, to load loading a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates in general to digital signal processing, and more particularly to a method and apparatus for providing a processor based nested form polynomial engine.  
         [0003]     2. Description of Related Art  
         [0004]     A microprocessor is a circuit that combines the instruction-handling, arithmetic, and logical operations of a computer on a single semiconductor integrated circuit. Microprocessors can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microprocessors. General-purpose microprocessors are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central processing unit (CPU) in equipment such as personal computers.  
         [0005]     In contrast, special-purpose microprocessors are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microprocessor. By knowing the primary function of the microprocessor, the designer can structure the microprocessor architecture in such a manner that the performance of the specific function by the special-purpose microprocessor greatly exceeds the performance of the same function by a general-purpose microprocessor regardless of the program implemented by the user.  
         [0006]     One such function that can be performed by a special-purpose microprocessor at a greatly improved rate is digital signal processing. Digital signal processing generally involves the representation, transmission, and manipulation of signals, using numerical techniques and a type of special-purpose microprocessor known as a digital signal processor (DSP). Digital signal processing typically requires the manipulation of large volumes of data, and a digital signal processor is optimized to efficiently perform the intensive computation and memory access operations associated with this data manipulation. For example, computations for evaluating polynomials include to a large degree repetitive operations such as multiply-and-add and multiple-bit-shift. DSPs can be specifically adapted for these repetitive functions, and provide a substantial performance improvement over general-purpose microprocessors in, for example, real-time applications such as image, speech, video and data processing.  
         [0007]     DSPs are central to the operation of many of today&#39;s electronic products, such as high-density disk drives, digital cellular phones, complex audio and video equipment and automotive systems. The demands placed upon DSPs in these and other applications continue to grow as consumers seek increased performance from their digital products, and as the convergence of the communications, computer and consumer industries creates completely new digital products. In addition, digital systems designed on a single integrated circuit are referred to as an application specific integrated circuit (ASIC). Currently, the design of ASICs include complex digital systems implemented on a single chip, e.g. SRAMs, FIFOs, register files, RAMs, ROMs, universal asynchronous receiver-transmitters (UARTs), programmable logic arrays, field programmable gate arrays and other such logic circuits.  
         [0008]     Designers have succeeded in increasing the performance of DSPs, and microprocessors in general, by increasing clock speeds, by removing data processing bottlenecks in circuit architecture, by incorporating multiple execution units on a single processor circuit, and by developing optimizing compilers that schedule operations to be executed by the processor in an efficient manner. For example, a DSP generally has a specialized multiply-accumulate (MAC) unit in order to improve the performance of repetitive digital signal processing algorithms. The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, application systems and methods of operation and manufacture.  
         [0009]     In algebra, a polynomial function, or polynomial for short, is a function of the form: 
 
 f ( x )= a   n   x   +a   n−1   x   n−1   + . . . +a   1   x+a   0 , 
 
 where x is a scalar-valued variable, n is a nonnegative integer, and a 0 , . . . , a n  are fixed scalars, called the coefficients of the polynomial f(x). Polynomial functions, or polynomials, are an important class of simple and smooth functions. Simple means they are constructed using only multiplication and addition. Smooth means they are infinitely differentiable, i.e., they have derivatives of all finite orders. Because of their simple structure polynomials are very easy to evaluate and are used extensively in numerical analysis for polynomial interpolation or to numerically integrate more complex functions. 
 
         [0010]     In a polynomial as described above, the highest occurring power of x (n if the coefficient an is not zero) is called the degree of f(x); its coefficient is called the leading coefficient. Where the leading coefficient is 1, we describe the polynomial as monic. a 0  is called the constant coefficient of f(x). Each summand of the polynomial of the form a k x k  is called a term. Here the variable x is, properly speaking, an indeterminate; it is on occasion replaced by something other than a scalar, e.g., some matrix or operator.  
         [0011]     A root or zero of the polynomial f(x) is a number r such that f(r)=0. Determining the roots of polynomials, or “solving algebraic equations”, is among the oldest problems in mathematics. Some polynomials, such as f(x)=x 2 +1, do not have any roots among the real numbers.  
         [0012]     Approximations for the real roots of a given polynomial can be found using Newton&#39;s method, or more efficiently using Laguerre&#39;s method, which employs complex arithmetic and can locate all complex roots. There is a difference between approximating roots and finding concrete closed formulas for them. Formulas for the roots of polynomials of degree up to 4 have been known since the sixteenth century. However, formulas for degree 5 polynomials are much difficult to obtain.  
         [0013]     A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing generally in real-time. DSPs can also be used to perform general-purpose computation, but they are not optimized for this function. Rather than general computations, DSPs usually have an instruction set (ISA) optimized for the task of rapid signal processing, such as the multiply-accumulate function.  
         [0014]     An instruction set, or instruction set architecture (ISA), is a specification detailing the commands that a computer&#39;s CPU should be able to understand and execute, or the set of all commands implemented by a particular CPU design. The term describes the aspects of a computer or microprocessor typically visible to a programmer, including the native data types, instructions, registers, memory architecture, interrupt and fault system, and external I/O (if any). “Instruction set architecture” is sometimes used to distinguish this set of characteristics from the Micro-Architecture, which are the elements and techniques used to implement the ISA, e.g. microcode, pipelining, cache systems, etc.  
         [0015]     The multiply-accumulate operation computes a product and adds it to an accumulator. In a CPU, an accumulator is a register in which intermediate results are stored. Without an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory and read them back. Access to main memory is slower than access to the accumulator, which usually has direct paths to and from the arithmetic logic unit (ALU). However, computing polynomials of single variables can be time consuming because of the number of cycles required and sizeable because of the number of bytes required to write code.  
         [0016]     For example, consider the 3rd order polynomial f(x)=ax 3 +bx 2 +cx 1 +d. To evaluate the polynomial, i.e., to solve for f(x)=y for a given x. When using the monomial form of the polynomial, n additions and n2+n/2 multiplications are needed for the calculation of p(x). To increase the speed of evaluating the polynomial, the number of multiplications must be decreased because multiplications are slow and numerically instable compared to the additions. The Horner algorithm rearranges the polynomial into the recursive form x(c+x(b+x(a)))+d. This form is more suited to fast computation because there are no wasted stores of x 2  and x 3 . For polynomials that could take on n orders there are two possibilities for writing this code. A hard coded form could be explicitly coded as follows: 
 
 y =( c   n   *x+c   n−1 ) 16   , y =( y*x+c   n2 ) 16   , y =( y*x+c   n3 ), . . . ,  y=y*x+c   0 . 
 
 However, such a code would get costly as the order grows. 
 
         [0017]     The second possibility is to use the loop form. If in loop form, the code could be expressed in pseudo c as: 
 
for (int i=n−1; y=c[n]x; i&gt;=0; i—) {y=( y*x+c[i])   16 }. 
 
         [0018]     Still, this form is expensive in terms of cycles because i must be tested and a conditional branch back to the top of the loop must occur.  
         [0019]     It can be seen then that there is a need for a method and apparatus for providing a processor based nested form polynomial engine.  
       SUMMARY OF THE INVENTION  
       [0020]     To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and apparatus for providing a processor based nested form polynomial engine.  
         [0021]     The present invention solves the above-described problems by providing a concise instruction format to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine.  
         [0022]     A method for providing a processor based nested form polynomial engine in accordance with the principles of the present invention includes setting coefficient and data address pointers for evaluating a polynomial, loading a coefficient and data operand into a coefficient register and a data register, respectively, multiplying the contents of the coefficient register and data register to produce a product, adding a next coefficient operand to the product to produce a sum, providing the sum to an accumulator and repeating the loading, multiplying, adding and providing until evaluation of the polynomial is complete.  
         [0023]     In another embodiment of the present invention, a processor based nested form polynomial engine is disclosed. The processor based nested form polynomial engine includes memory for providing a counter for calculating completion of a polynomial evaluation, a coefficient address pointers register for maintaining a coefficient address pointer and a data address pointers register for maintaining a data address pointer, a coefficient register and a data register, coupled to the memory, for loading a coefficient and data operand therein, respectively, a multiplier, coupled to the coefficient register and data register, for multiplying the contents of the coefficient register and data register to produce a product, an adder, coupled to the multiplier, for adding a next coefficient operand to the product to produce a sum, an accumulator, coupled to the adder, for accumulating the produced sum to produce an accumulated value and a state machine, coupled to the memory, for repeating the loading, multiplying, adding and accumulating until evaluation of the polynomial is complete.  
         [0024]     In another embodiment of the present invention, a processor unit is disclosed. The processor unit includes memory for storing data and instructions therein and a processor configured for performing evaluation of a polynomial using a nested form, the processor being configured to set coefficient and data address pointers for evaluating a polynomial, to load a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.  
         [0025]     In another embodiment of the present invention, a data storage system is disclosed. The data storage system includes a translatable recording medium for storing data thereon, a motor for translating the recording medium, a transducer disposed proximate the recording medium for reading and writing data on the recording medium, an actuator, coupled to the transducer, for moving the transducer relative to the recording medium and a storage control device for controlling operation of the data storage system, the storage control device further including a storage controller for processing read and write signals and a processor unit, coupled to the storage controller, the processor unit performing evaluation of a polynomial using a nested form, the processor being configured to set coefficient and data address pointers for evaluating a polynomial, to load a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.  
         [0026]     In another embodiment of the present invention, another processor unit is disclosed. This processor unit includes means for storing data and instructions therein, means for setting coefficient and data address pointers for evaluating a polynomial, means for loading a coefficient and data operand into a coefficient register and a data register, respectively, means for multiplying the contents of the coefficient register and data register to produce a product, means for adding a next coefficient operand to the product to produce a sum, means for providing the sum to an accumulator, and means for repeating the loading, multiplying, adding and providing until evaluation of the polynomial is complete.  
         [0027]     In another embodiment of the present invention, a polynomial instruction for controlling a processor based nested form polynomial engine for evaluating a polynomial is disclosed. The polynomial instruction includes a first field for designating whether to use absolute value of data, a second field for indicating that a result of a polynomial evaluation be stored in memory at a memory address, a third filed for providing the memory address for storing the result of the polynomial evaluation when directed, a fourth field for indicating an order of a polynomial to be evaluated, a fifth field for providing a coefficient address pointer and a sixth field for providing a data address pointer.  
         [0028]     These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     Referring now to the drawings in which like reference numbers represent corresponding parts throughout:  
         [0030]      FIG. 1  illustrates a processor based nested form polynomial engine for evaluating fixed point polynomials according to an embodiment of the present invention;  
         [0031]      FIG. 2  illustrates the format for a polynomial instruction according to an embodiment of the present invention;  
         [0032]      FIG. 3  illustrates a block diagram of a digital signal processing circuit for implementing an arithmetic shifter and saturation detection circuit according to an embodiment of the present invention;  
         [0033]      FIG. 4  is a flow chart of the method for evaluating fixed-point polynomials using a processor based nested form polynomial engine according to an embodiment of the present invention; and  
         [0034]      FIG. 5  shows a schematic block diagram showing a hard disk storage system according to one embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0035]     In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention.  
         [0036]     The present invention provides a method and apparatus for providing a processor based nested form polynomial engine. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine.  
         [0037]      FIG. 1  illustrates a processor based nested form polynomial engine  100  for evaluating fixed point polynomials according to an embodiment of the present invention. In  FIG. 1 , a memory  110  is provided for data storage. For example, a SRAM  100  can be used for the data storage. The SRAM  100  may be implemented as a unified SRAM, as two separate SRAMS, i.e., Coefficient SRAM and Data SRAM, for higher performance, or as a three port SRAM, i.e., two read ports and one write port. The coefficient and data can be either 16 bits or 32 bits wide depending on the application and the arithmetic resolution. A multiplier  140  multiplies the input from the coefficient register  120  and from the data register  130 . The multiplier  140  may be, for example, implemented as a single cycle or as a multi-cycle pipeline multiplier for area/speed depending on the application. Furthermore, the multiplier  140  may be a 16×16, 32×16, or 32×32 multiplier.  
         [0038]     Next, an adder  150  is provided to add the output of the multiplier  140  and output from the SRAM  110 . The adder may be a 3:2 adder, i.e., three inputs and two outputs, and may include a single or a multi-cycle adder for area/speed depending on the application. An accumulator  160  receives the sum from the adder  150  and accumulates the sum therein. A finite state machine (FSM)  170  controls the dataflow. The finite state machine  170  includes a counter  172 , a coefficient address pointer register  174  and a data address pointer register  176 . The pointer registers  174 ,  176  have capability of pre/post increment or decrement.  
         [0039]     To illustrate the operation of the processor based nested form polynomial engine, the following polynomial equation will be used: 
 
 y=ax   4   +bx   3   +cx+dx+e.  
 
         [0040]     In this example, the ADR register has the address 0x200, the coefficient pointer will have the address 0x000, and the data pointer will have the address 0x100. The content of the SRAM is as follows:  
                                                 RAM contents                Description   Address   SRAM Contents                       Coefficient pointer ==&gt;   0x000   a               0x002   b               0x004   c               0x006   d               0x008   e           Data pointer ==&gt;   0x100   x           Result ==&gt;   0x200   y                      
 
         [0041]     For illustration herein, two separate SRAMs are used for the coefficients and for the data, respectively. Based on the polynomial give above, the processor based nested form polynomial engine will use the one cycle multiplier: 
 
 Y =((( ax+b ) x+c ) x+d ) x+e.  
 
 A concise instruction format is used to control the processor based nested form polynomial engine, wherein the concise instruction format significantly decreases the amount of memory required and allows for instruction pipelining without branch penalty. 
 
         [0042]      FIG. 2  illustrates the format for a polynomial instruction  200  according to an embodiment of the present invention. The polynomial instruction may be realized in a 32-bit instruction format. The results will be saturated to the max/maxmin value if the overflow/underflow is detected. The polynomial instruction  200  includes an Ab field  210 , an Up field  220 , an address pointer register field  230 , a polynomial order field  240 , a coefficient address pointer  250  and a data address pointer  260 .  
         [0043]     Possible variations for the instruction format illustrated in  FIG. 2  are as follows:  
                                       Instruction   Flags   Description                   Poly   Ab = 0, Up = 0,   Evaluate nth order polynomial equation.               When overflow/underflow are detected,               the result is saturated to the max/max.       Polyu   Ab = 0, Up = 0,   Evaluate nth order polynomial equation               and store the result where specified by               ADR register. When               overflow/underflow are detected, the               result is saturated to the max/max.       Polyabs   Ab = 1, Up = 0,   Evaluate nth order polynomial equation               using the absolute value of data. When               overflow/underflow are detected, the               result is saturated to the max/min. The               original sign of data is applied to the               final result so that the sign of the final               result and data are the same.       Polyabsu   Ab = 1, Up = 0,   Evaluate nth order polynomial equation               using the absolute value of data and               store the result where specified by ADR               register. When overflow/underflow are               detected, the result is saturated to the               max/max. The original sign of data is               applied to the final result so that the sign               of the final result and data are same.                  
 
 If Ab is set, the absolute value of the data is used. If Up is set, the result is saved where the address is specified by the address pointer register. 
 
         [0044]     Returning again to  FIG. 1 , the explanation of the operation of the processor based nested form polynomial engine will continue. In the first cycle, the counter  172  is set to the polynomial order. The coefficient pointer  174  is set to the coefficient address and the data pointer  176  is set to the data address. The coefficient and data operands are fetched. The sign is the most significant bit of the data.  
         [0045]     In the second cycle, a is loaded into the coefficient register  120  and x, or |x| if Ab=1, is loaded into the data register  130 . Coefficient b is fetched. The contents of the coefficient register  120  and the data register  130  are multiplied by the multiplier and the product is added to coefficient b, which was fetched. If the overflow/underflow is detected, the accumulator  160  is saturated to either the maximum or minimum value depending upon which is determined to be appropriate.  
         [0046]     In the third cycle, the upper most significant 16 bits of the accumulator  160  is loaded into the coefficient register  120 . The data register  130  is loaded with x. Coefficient c is fetched. The contents of the coefficient register  120  and the data register  130  are multiplied by the multiplier and the product is added to coefficient c, which was fetched. The sum is provided to the accumulator  160 . Again, if the overflow/underflow is detected, the accumulator is saturated to either the maximum or minimum value depending upon which is determined to be appropriate.  
         [0047]     In the fourth cycle, the upper most significant 16 bits of the accumulator  160  is loaded into the coefficient register  120 . The data register  130  is loaded with x. Coefficient d is fetched. The contents of the coefficient register  120  and the data register  130  are multiplied by the multiplier and the product is added to coefficient d, which was fetched. The sum is provided to the accumulator  160 . Again, if the overflow/underflow is detected, the accumulator is saturated to either the maximum or minimum value depending upon which is determined to be appropriate.  
         [0048]     In the fifth cycle, the upper most significant 16 bits of the accumulator  160  is loaded into the coefficient register  120 . The data register  130  is loaded with x. Coefficient e is fetched. The contents of the coefficient register  120  and the data register  130  are multiplied by the multiplier and the product is added to coefficient e, which was fetched. The sum is provided to the accumulator  160 . Again, if the overflow/underflow is detected, the accumulator is saturated to either the maximum or minimum value depending upon which is determined to be appropriate.  
         [0049]     In the sixth cycle, if Ab is set to 1, the two&#39;s compliment of the contents of the accumulator  160  is provided if the sign of the data was negative. If Up is set to 1, the contents of the accumulator  160  are stored in the SRAM at an address specified by the address pointer register  178 .  
         [0050]     Thus, the processor based nested form polynomial engine  100  according to an embodiment of the present invention evaluates fixed-point polynomials by using the nested loop form without the test and branch penalties. Accordingly, the processor based nested form polynomial engine  100  consumes a minimum number of cycles with a minimum amount of code via the concise instruction format. However, those skilled in the art will recognize that the processor based nested form polynomial engine for evaluating fixed point polynomials according to an embodiment of the present invention may be implemented in software, hardware or a combination thereof.  
         [0051]      FIG. 3  illustrates a block diagram of a digital signal processing circuit  300  for implementing an arithmetic shifter and saturation detection circuit according to an embodiment of the present invention.  FIG. 3  shows a control unit  310 , a data unit  320  and an address unit  330 . The control unit  310  directs the operation of the digital signal processor based on an instruction set (ISA) optimised for the task of rapid signal processing. The signal processing is divided between the control unit  310  that directs program flow and one or more execution units that perform operations on data. Almost always, a collection of registers/memory  340  is included to hold operands and intermediate results. One of the execution units is the address unit  330 . The address unit  330 , AU, directs the operand fetch for all variables which are defined and used by the executing instructions or program. Another execution unit is the data unit  320 , which includes at least one arithmetic logic unit  322 , shifter  324  and multiplier-accumulator (MAC)  326 . The data unit  320  accepts as inputs the data to be operated on and a code from the control unit  310  indicating what operation to perform. The ALU  322  takes as inputs, the data to be operated on and a code from the control unit indicating which operation to perform, and for output provides the result of the computation. The shifter  324  performs logical and arithmetic shifts, bitmanipulation, and other operations on input operands. The MAC  326  implements the processor based nested form polynomial engine according to an embodiment of the present invention and evaluates fixed-point polynomials by using the nested loop form without the normal test and branch penalties. The MAC  326  performs multiply/add and multiply/subtract operations on the input operands and stores the result in the specified result register.  
         [0052]      FIG. 4  is a flow chart  400  of the method for evaluating fixed-point polynomials using a processor based nested form polynomial engine according to an embodiment of the present invention. First, a counter is set to the polynomial order, the coefficient pointer is set to the coefficient address and the data pointer is set to the data address  410 . The coefficient and data operands are fetched  412 . The sign is the most significant bit of the data. The fetched operands are loaded into the coefficient and data registers as appropriate  414 . The data value used is x, or |x| if Ab=1. The next coefficient is fetched  416 . Then, the contents of the coefficient register and the data register are multiplied and the next coefficient operand that was fetched is added to the product  418 . A determination is made whether overflow/underflow is detected  420 . If overflow is detected  422 , the content of the accumulator is set to the maximum value  430 . If underflow is detected  424 , the content of the accumulator is set to the minimum value  440 . The counter is decremented and compared to zero to determine whether the evaluation is completed  450 . A determination if made whether the counter is equal to zero  460 . If yes  462 , the evaluation is complete, the appropriate sign is accommodated and the accumulator contents is loaded into memory when directed  470 . For example, if Ab is set to 1, the two&#39;s compliment of the contents of the accumulator is provided if the sign of the data was negative. If Up is set to 1, the contents of the accumulator are stored in the SRAM at an address specified by an address pointer register. If no,  463 , the process recycles to include the next operands  480 .  
         [0053]      FIG. 5  shows a schematic block diagram showing a hard disk storage system  500  according to one embodiment of the present invention. The hard disk storage system  500  is connected to a host computer  590 . The hard disk storage system  500  responds to the write request by the host computer  590  and records the recording data from the host computer  590  on a magnetic disk  510 , which serves as a recording medium. The hard disk storage system  500  further responds to the read request from the host computer  590 , reads the data recorded on the magnetic disk  510 , and sends the data to the host computer  590 . The hard disk storage system  500  includes the magnetic disk  510 , first and second motors  512 ,  516 , a head device  514 , a signal processing circuit  520 , a servo circuit  530 , a microprocessor (MPU)  540 , a memory (RAM)  550 , a hard drive controller (HDC)  560 , and an interface circuit  570 . The circuits  520 - 570  are connected to one another by a bus  580 .  
         [0054]     The magnetic disk  510  is rotated by the first motor  512  at a constant rotating speed. The second motor  516  controls the head device  514  so that it moves in the radial direction with respect to the magnetic disk  510 . The head device  514  reads the data recorded on the magnetic disk  510  and sends a read signal, RD, to the signal processing circuit  520 .  
         [0055]     The signal processing circuit  520  samples the read signal, RD, in synchronism with a clock signal and generates a digital read signal. The signal processing circuit  520  carries out a decoding process on the digital read signal and outputs the decoded data signal. The servo circuit  530  controls the first motor  512  and rotates the magnetic disk  510  at a constant speed. The servo circuit  530  further receives the decoded data signal from the signal processing circuit  520  via the bus  580  and controls the second motor  516  based on the servo data included in the digital read signal so that the head device  514  is on track at the target position.  
         [0056]     The MPU  540  analyzes the write/read processing command sent from the host computer  590  in accordance with the program data stored in the RAM  550  and sends a control signal to the HDC  560  via the bus  580 . The HDC  560  controls the signal processing circuit  520  and the servo circuit  530  in accordance with the control signal from the MPU  540 . The HDC  560  further receives a data signal from the signal processing circuit  520  via the bus  580 . The HDC  560  processes date, e.g., performs an error correcting code (ECC) process on the data signal. The HDC  560  then sends the processed data to the interface circuit  570  via the bus  580 . The interface circuit  570  converts the data from the HDC  560  to a predetermined communication mode and sends the converted data to the host computer  590 . The MPU  540  includes multiplier-accumulator as illustrated in  FIG. 1  for providing a processor based nested form polynomial engine according to an embodiment of the present invention. A concise instruction format is used to significantly decrease the amount of memory required and allow for instruction pipelining without branch penalty. The use of the nested form for evaluating polynomials allows the MPU  540  to evaluate fixed-point polynomials with a minimum amount of code via the concise instruction format and without the test and branch penalties normally associated with traditional loop form polynomial evaluations. The MPU  540  may also be configured so that the processor based nested form polynomial engine may be run by firmware of the HDC  560 .  
         [0057]     It should be appreciated that the MPU  540  could include a standalone processor or an embedded processor, e.g., the MPU  540  could be embedded in the HDC  560 . The MPU  540  could be part of a system on a chip (SOC). Further, the MPU  540  could be an ASIC, which would be hardware circuits that perform the function of the processor operating pursuant to memory  550 . In such a situation, memory  550  may be used but is not required, as the ASIC is designed to perform any assigned functions. It should also be appreciated that memory  550  could be either volatile or non-volatile memory. The MPU  540  controls the operation of the voice coil motor  516  and spindle motor  512  via the servo unit  530 .  
         [0058]     The foregoing description of the exemplary embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not with this detailed description, but rather by the claims appended hereto.