Abstract:
Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit.

Description:
BACKGROUND 
     Field of the Invention 
     The invention relates to integrated circuit memory. In particular, the invention relates to the repair of defective locations of a memory. 
     SUMMARY 
     One aspect of the technology is an integrated circuit, with multiple sets of memory cells, and control circuitry (coupled to the sets of memory cells) with an instruction set for controlling the integrated circuit. The multiple sets of memory cells include a first set of memory cells storing data during regular operation of the integrated circuit, a second set of repair memory cells available to substitute for the defective locations of the first set of memory cells, and a third set of memory cells storing defective locations of the first set of memory cells. In some embodiments, at least the first and second sets of memory cells are nonvolatile. In various embodiments, the various sets of memory cells are variously positioned on the same array or on different arrays. 
     The instruction set of the control circuitry includes at least a repair instruction. The control circuitry is responsive to the repair instruction by substituting the defective locations of the first set of memory cells with the second set of memory cells. The repair instruction omits the defective locations of the first set of memory cells. In some embodiments, this omission decreases the amount of data which must be communicated with the integrated circuit to repair the defective locations of the first set of memory cells. 
     In some embodiments, the control circuitry is responsive to the repair instruction, by reading the defective locations of the first set of memory cells from the third set of memory cells. In this manner, the control circuitry knows the appropriate locations of the first set of memory cells which must be replaced. 
     The instruction set of some embodiments of the control circuitry further includes a test instruction. The control circuitry is responsive to the test instruction by detecting whether memory cells of the first set of memory locations meet margin requirements. Further, some embodiments store the defective locations of the first set of memory cells in the third set of memory cells, in response to the test instruction. 
     Another aspect of the technology is a method of testing integrated circuits in parallel, comprising the step of:
         sending a repair instruction from a tester to multiple integrated circuits undergoing testing. Each integrated circuit is responsive to the repair instruction by substituting defective locations of a first set of memory cells in each integrated circuit with a second set of memory cells in each integrated circuit. The repair instruction omits the defective locations of the first set of memory cells of any of the integrated circuits. In some embodiments each integrated circuit is further responsive to the repair instruction, by reading the defective locations of the first set of memory cells from a third set of memory cells in each integrated circuit. Because the repair instruction omits the defective locations of memory which would be specific to each integrated circuit, in some embodiments the same instruction is sent to each integrated circuit.       

     Some embodiments further include the step of:
         sending a test instruction from the tester to the multiple integrated circuits undergoing testing. Each integrated circuit is responsive to the test instruction by detecting whether memory cells of the first set of memory locations meet margin requirements. In some embodiments each integrated circuit is further responsive to the test instruction by storing the defective locations of the first set of memory cells in a third set of memory cells. In some embodiments, the test instruction is sent to prior to sending the repair instruction.       

     Another aspect of the technology is a method of integrated circuit testing, comprising the steps of:
         receiving a repair instruction, from a tester, at an integrated circuit undergoing testing. The integrated circuit is responsive to the repair instruction by substituting defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit. The repair instruction omits the defective locations of the first set of memory cells of the integrated circuit. In some embodiments, the integrated circuit is further responsive to the repair instruction, by reading the defective locations of the first set of memory cells from a third set of memory cells in the integrated circuit.       

     Some embodiments further include the step of:
         receiving a test instruction, from the tester, at the integrated circuit undergoing testing. The integrated circuit is responsive to the test instruction by detecting whether memory cells of the first set of memory locations meet margin requirements. In some embodiments the integrated circuit is further responsive to the test instruction by storing the defective locations of the first set of memory cells in a third set of memory cells. In some embodiments, the test instruction is sent to prior to sending the repair instruction.       

     Other embodiments of the various aspects are as disclosed herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a tester sending a repair instruction to an integrated circuit, and the integrated circuit receiving the repair instruction from the tester. 
         FIG. 2  is a block diagram of a tester sending a test instruction to an integrated circuit, and the integrated circuit receiving the test instruction from the tester. 
         FIG. 3  is a block diagram of a tester sending a repair instruction in parallel to multiple integrated circuits, and the multiple integrated circuits receiving the repair instruction in parallel from the tester. 
         FIG. 4  is a block diagram of a tester sending a test instruction in parallel to an integrated circuit, and the integrated circuit receiving the test instruction in parallel from the tester. 
         FIG. 5  is a block diagram of an example integrated circuit including control circuitry that replaces defective memory cells in response to a repair instruction that omits the defective locations. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram of a tester sending a repair instruction to an integrated circuit, and the integrated circuit receiving the repair instruction from the tester. A tester  100  sends a repair instruction  105 , which is received by an integrated circuit  110 . The repair instruction  105  does not specify the defective memory addresses to be repaired. The integrated circuit  110  has several sets of memory cells—1 st  set  120 , 2 nd  set  122 , and 3 rd  set  124 —coupled to memory cell control circuitry  130 . Although the sets of memory cells are shown together, in various embodiments, the sets of memory cells are contiguous, noncontiguous, or selectively contiguous (e.g., 1 st  set  120  and 2 nd  set  122 , 2 nd  set  122  and 3 rd  set  124 , and 1 st  set  120  and 3 rd  set  124 ). The repair instruction  105  does not specify the defective memory addresses to be repaired, but the memory cell control circuitry  130  reads out, from the 3 rd  set of memory cells, the locations of defective locations of the 1 st  set of memory cells  120 , such as those that failed to meet margin requirements. In various embodiments, the sets of memory cells are all nonvolatile, all volatile, or selectively nonvolatile. The defective locations of the 1 st  set of memory cells  120  are replaced with the 2 nd  set of memory cells  122 , as needed. The replacement of addresses is schematically shown by the ‘pointers’  160  and  162  from memory cell control circuitry  130  to the sets of memory cells. Addresses pointing to defective locations  162  of the 1 st  set of memory cells  120  are replaced as needed with replacement locations  160  of the 2 nd  set of memory cells  122 . 
       FIG. 2  is a block diagram of a tester sending a test instruction to an integrated circuit, and the integrated circuit receiving the test instruction from the tester. The test instruction precedes the repair instruction. A tester  100  sends a test instruction  205 , which is received by an integrated circuit  110 . The memory cell control circuitry  130  tests for defective locations of the 1 st  set of memory cells  120 , such as those that fail to meet margin requirements. The defective locations of the 1 st  set of memory cells  120  are stored in the 3 rd  set of memory cells  124 . The defective locations of the 1 st  set of memory cells  120  are schematically shown by the ‘pointer’  162  from memory cell control circuitry  130  to the 1 st  set of memory cells  120 . Addresses pointing to defective locations  162  of the 1 st  set of memory cells  120 . 
       FIG. 3  is a block diagram of a tester sending a repair instruction in parallel to multiple integrated circuits, and the multiple integrated circuits receiving the repair instruction in parallel from the tester. The repair operation in  FIG. 3  resembles the repair operation in  FIG. 1 , but occurs in parallel across multiple integrated circuits—integrated circuit  111 , integrated circuit  112 , integrated circuit  113 , integrated circuit  114 , and integrated circuit  115 . Parallel operation is supported by the omission from the repair instruction of the defective locations of the first set of memory cells in each of the integrated circuits. 
       FIG. 4  is a block diagram of a tester sending a test instruction in parallel to an integrated circuit, and the integrated circuit receiving the test instruction in parallel from the tester. The test operation in  FIG. 4  resembles the test operation in  FIG. 2 , but occurs in parallel across multiple integrated circuits—integrated circuit  111 , integrated circuit  112 , integrated circuit  113 , integrated circuit  114 , and integrated circuit  115 . 
       FIG. 5  is a block diagram of an example integrated circuit including control circuitry that replaces defective memory cells in response to a repair instruction that omits the defective locations. 
     The integrated circuit  550  includes a memory array  500  implemented using memory cells with defective locations that are replaced responsive to a repair command that does not specify the defective addresses. Addresses are supplied on bus  505  to column decoder  503  and row decoder  501 . Sense amplifiers and data-in structures in block  506  are coupled to the column decoder  503  via data bus  507 . Data is supplied via the data-in line  511  from input/output ports on the integrated circuit  550 , or from other data sources internal or external to the integrated circuit  550 , to the data-in structures in block  506 . Data is supplied via the data-out line  515  from the block  506  to input/output ports on the integrated circuit  550 , or to other data destinations internal or external to the integrated circuit  550 . The control circuitry  509  also has a program, erase, and read bias arrangement state machine that replaced defective locations of the memory cell array  500 . 
     While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.