Abstract:
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/881,472, filed Jul. 26, 2007, which is a continuation of U.S. patent application Ser. No. 11/087,293, filed Mar. 22, 2005, U.S. Pat. No. 7,262,637. These applications are incorporated by reference herein. 

   TECHNICAL FIELD 
   This invention relates generally to integrated circuits and, more particularly, to an integrated circuit output buffer circuit generating an output signal having a slew-rate that is substantially insensitive to variations in the voltage of power supplied to the integrated circuit. 
   BACKGROUND OF THE INVENTION 
   Today&#39;s electronic components are designed so that they will function properly when used with components from a variety of manufacturers. For example, memory devices, such as dynamic random access memory (“DRAM”) devices, are designed to function properly with memory controllers and other components available from a variety of sources. 
   To ensure performance and allow component compatibility, the operating characteristics and parameters of electronic devices are specified in substantial detail. Other electronic devices are then designed to properly interface with the electronic device based on the specification. For example, specifications for Synchronous Dynamic Random Access Memory (SDRAM) devices generally specify a range of supply voltages that can be used to power the SDRAM devices. The specification also identifies the acceptable ranges of the rise- and fall-time slew rates (Volts/nanosecond) of read data signals output from the SDRAM devices. To meet the specification, an SDRAM device must be capable of meeting each parameter at any value of each of the other specified parameters. Therefore, SDRAM devices must be capable of outputting read data signals having the specified rise- and fall-time slew rates throughout the range of specified supply voltages. It can also be important that the slew rates of the read data signals not vary as operating parameters, such as the supply voltage, are varied. Unfortunately, both the rise-time and fall-time slew rates of read data signals output from conventional SDRAM devices often vary significantly with supply voltage variations. These variation can make it difficult to meet the slew rate specifications at all supply voltages within the specified range. 
   As the operating speed of SDRAM devices and associated devices continues to increase, the variations in slew rate as a function of supply voltage variations can become a more significant problem. Problems resulting from slew rate variations have also become more significant in double-data rate (DDR) SDRAM devices, which output read data on both the rising edge and the falling edge of a read data strobe that is synchronized to a master clock signal. 
     FIG. 1  shows a conventional output buffer  10  commonly in use in DDR SDRAMs. The output buffer  10  includes a first pre-driver  14  containing a first inverter  16  that receives an active high D_PUP signal, and a second inverter  18  that receives an active low D_PDN_signal. As explained below, the D_PUP signal is activated high to output a high read data output signal, and the D_PDN_signal is activated low to output a low read data output signal. 
   The inverter  16  generates an active low PUPEN_signal from the D_PDN signal, and the inverter  18  generates an active low PDNEN_signal from the D_PDN_signal. These signals are applied to a second pre-driver  20 . The PUPEN_signal is applied to one input of a NOR gate  22  having an output that drives an inverter  24 , which, in turn, outputs an active low PUP_signal. A second input of the NOR gate  22  receives a DQEN_signal, which is active low when read data are to be output from the output buffer  10 . Thus, the PUP_signal is active low to cause the output buffer  10  to output a high read data signal whenever the NOR gate  22  is enabled by a low DQEN_signal and the D_PUP signal is active high. Similarly, the PUPEN signal is applied to one input of a NAND gate  26  having an output that drives an inverter  28 , which, in turn, outputs an active high PDN signal. A second input of the NAND gate  26  receives a DQEN signal, which the compliment of the DQEN_signal. The DQEN signal is active high when read data are to be output from the output buffer  10 . Thus, the PDN signal is active high to cause the output buffer  10  to output a low read data signal whenever the NAND gate  26  is enabled by a high DQEN signal and the D_PDN signal is active high. 
   The output buffer  10  includes a final driver  30  having a PMOS transistor  32  coupled between a positive supply voltage VCCQ and a data output terminal DQ_OUT through a resistor  34 . The output buffer  10  also includes an NMOS transistor  36  coupled between a negative supply voltage VSSQ, which will assumed to be ground, and the data output terminal DQ_OUT through a resistor  38 . The data output terminal DQ_OUT is biased to a suitable voltage, which is typically VCCQ/2, through a resistor  40 . 
   The DQ_OUT terminal is normally at VCCQ/2 when the PUP_signal is inactive high and the PDN signal is inactive low. When the PUP_signal is active low and the PDN signal is inactive low, the PMOS transistor  32  turns ON to couple the DQ_OUT terminal to VCCQ. When the PDN signal is active high and the PUP_signal is inactive high, the NMOS transistor  36  turns ON to couple the DQ_OUT terminal to ground. As long as the slew rate at which the signal at the DQ_OUT terminal transitions to VCCQ and to ground, the buffer  10  shown in  FIG. 1  provides adequate performance. However, if maintaining the slew rate constant despite variations in the magnitude of the supply voltage VCCQ is important, the buffer  10  may not provide adequate performance. 
   The manner in which the slew rate of read data signals from the output buffer  10  varies will now be explained with reference to  FIGS. 2A and 2B , which shows the timing of the signals in the output buffer  10  at two different levels of supply voltage. The time delay through the gates are ignored in  FIG. 2A  and  FIG. 2B  for simplicity. As illustrated in  FIG. 2A , the voltage at the DQ_OUT terminal begins transitioning from low-to-high responsive to the D_PDN_signal transitioning low-to-high at time t 0  and the D_PUP signal transition from low-to-high after a short delay t dr  at time t 1 . As further shown in  FIG. 2A , the low-to-high transition of the D_PDN_signal causes the PDNEN signal at the output of the inverter  18  ( FIG. 1 ) to transition low, and the low-to-high transition of the D_PUP signal causes the PUPEN_signal at the output of the inverter  16  to also transition low. As a result, the PDNEN signal transitions low before the PUPEN_transitions low with the same delay t dr . The PDNEN signal is coupled through the NAND gate  26  and the inverter  28  to generate a PDN signal, which transitions from high-to-low at time t 0 . Similarly, The PUPEN_signal is coupled through the NOR gate  22  and the inverter  24  to generate a PUP_signal, which transitions from high-to-low at time t 1 . The low PDN signal turns OFF the NMOS transistor  36 , and the low PUP_signal turns ON the PMOS transistor  32 . The delay t dr  between the time to at which the NMOS transistor  36  is turned OFF and the time t 1  at which the PMOS transistor  32  is turned ON ensures that the NMOS transistor  36  has turned OFF before the PMOS transistor  32  is turned ON. 
   When the NMOS transistor  36  turns OFF at time t 0 , the voltage at the DQ_OUT terminal begins increasing even through the PMOS transistor  32  has not yet been turned ON because of the VCCQ/2 bias applied to the DQ_OUT terminal. When the PMOS transistor  32  turns ON at time t 1 , the transition of the DQ_OUT terminal to a high logic level corresponding to VCCQ continues, and the DQ_OUT terminal reaches the VCCQ voltage at time t 2 . In reality, DG_OUT may reach VCCQ voltage before of after t 2 . The rising edge slew rate of the signal at the DQ_OUT terminal is the ratio of the voltage change, i.e., VCCQ, to the transition time, i.e., t 2  less t 0 . 
   In a similar manner, the voltage at the DQ_OUT terminal begins transitioning from high-to-low at time t 3  when the PUP_signal transitions low-to-high responsive to the D_PUP signal transitioning low, thereby turning OFF the PMOS transistor  32 . 
   In a similar manner, the voltage at the DQ_OUT terminal begins transitioning from high-to-low responsive to the D_PUP signal transitioning from high-to-low at time t 3  and the D_PDN_signal transitioning high-to-low after a short delay t df  at time t 4 . The high-to-low transition of the D_PDN_signal causes the PDNEN signal at the output of the inverter  18  ( FIG. 1 ) to transition high, and the high-to-low transition of the D_PUP signal causes the PUPEN_signal at the output of the inverter  16  to also transition high. The PUPEN_signal causes the PUP_signal to transitions from low-to-high at time t 3 , and the PDNEN signal causes the PDN signal to transition from low-to-high at time t 4 . The high PUP_signal turns OFF the PMOS transistor  32 , and the high PDN signal turns ON the NMOS transistor  36 . Again, the delay t df  between the time t 3  at which the PMOS transistor  32  is turned OFF and the time  4  at which the NMOS transistor  36  is turned ON ensures that the PMOS transistor  32  has turned OFF before the NMOS transistor  36  is turned ON. When the PMOS transistor  32  turns OFF at time t 3 , the voltage at the DQ_OUT terminal begins decreasing even through the NMOS transistor  38  has not yet been turned ON because of the VCCQ/2 bias voltage. When the NMOS transistor  38  turns ON at time t 4 , the transition of the DQ_OUT terminal to a low logic level corresponding to ground continues, and the DQ_OUT terminal reaches zero volts at time t 5 . The falling edge slew rate of the signal at the DQ_OUT terminal is again the ratio of the voltage change, i.e., VCCQ, to the transition time, i.e., t 5  less t 3 . 
   The switching characteristics of the output buffer  10  when the magnitude of the power supply voltage VCCQ increases to VCCQ′ is shown in  FIG. 2B . The switching times t 0 -t 5  of all signals are labeled in the same manner as in  FIG. 2A . The falling edge transition time t 2  less t 0  and the rising edge transition time t 5  less t 3  for a supply voltage of VCCQ′ are shown in  FIG. 2B  as being the same as the falling edge transition time t 2  less t o  and the rising edge transition time t 5  less t 3  for a supply voltage of VCCQ as shown in  FIG. 2A  although in practice they may be longer or shorter. In any case, since the transitions between ground the supply voltage is greater when VCCQ′ is larger as shown in  FIG. 2B , the slew rates of the signal at the DQ_OUT terminal are also greater. The signal at the output terminal is able to transition between ground the VCCQ′ at this high rate with the greater supply voltage VCCQ′ primarily because the PMOS transistor  32  is turned ON with a greater gate-to-source voltage. The voltage at the DQ_OUT terminal is able to transition low from VCCQ′ to ground at this high rate with the greater supply voltage VCCQ′ primarily because the NMOS transistor  36  is turned ON with a greater gate-to-source voltage because the inverter  28  is normally also powered by the greater supply voltage VCCQ′. 
   This variation in the slew rate at the DQ_OUT terminal can create problems at high speeds where timing is critical, and it can make it more difficult for memory devices and other integrated circuits containing the output buffer  10  from meeting slew-rate specifications. There is therefore a need for an output buffer that is capable of providing an output signal having rising edge and falling edge slew rates that are substantially insensitive to variations in the magnitude of a voltage supplying power to the output buffer. 
   SUMMARY OF THE INVENTION 
   An output buffer and method generates an output signal at an output terminal in a manner that makes the slew rate of the output signal substantially insensitive to variations in a power supply voltage coupled to the output buffer. The output buffer includes a first switch that closes to couple the output terminal to a first level, and a second switch that closes to couple the output terminal to a second level that is different from the first level. The output terminal being biased to a third level that is intermediate the first and second levels so that the output terminal is at the third level when both of the first and second switches are open. Unfortunately, the rate at which the output signal generated at the output terminal transitions to at least one of the first and second levels varies with the magnitude of the power supply voltage. To compensate for this variation in slew rate, at least one of the switches is closed a delay period after opening the other of the switches. The duration of the delay period is adjusted as a function of the supply voltage so that the slew rate of the output signal is substantially insensitive to variations in the magnitude of the supply voltage. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a logic diagram and schematic diagram of a conventional output buffer. 
       FIGS. 2A and 2B  are timing diagrams showing the switching characteristics of the output buffer of  FIG. 1  with two different magnitudes of a voltage supplying power to the output buffer. 
       FIG. 3  is a logic diagram and schematic diagram of an output buffer according to one embodiment of the invention. 
       FIGS. 4A and 4B  are timing diagrams showing the switching characteristics of the output buffer of  FIG. 1  with two different magnitudes of a voltage supplying power to the output buffer. 
       FIG. 5  is a schematic diagram of one embodiment of a pre-driver circuit usable in the output buffer of  FIG. 3 . 
       FIG. 6  is a schematic diagram of one embodiment of a voltage compensation circuit usable in the pre-driver of  FIG. 5 . 
       FIG. 7  is a block diagram of one embodiment of a memory device using an output buffer, such as the output buffer of  FIG. 3 , in accordance with the present invention. 
       FIG. 8  is a block diagram of an embodiment of a computer system using the memory device of  FIG. 7  or some other memory device having an output buffer in accordance with the present invention. 
   

   DETAILED DESCRIPTION 
   An output buffer  50  according to one embodiment of the invention is shown in  FIG. 3 . The output buffer  50  uses most of the same components operating in the same manner as the output buffer  10  shown in  FIG. 1 . Therefore, in the interest of brevity, these common components have been provided with the same reference numerals, and a description of their structure and operation will not be repeated. 
   The output buffer  50  differs from the conventional output buffer  10  by using a first pre-driver  54  containing a first inverter  56  receiving the D_PUP signal that has voltage controlled switching characteristics, and a second inverter  58  receiving the D_PDN_signal that also has voltage controlled switching characteristics. In contrast, the corresponding inverters  16 ,  18  in the output buffer  10  of  FIG. 1  have fixed switching characteristics. The switching characteristics of the inverters  56 ,  58  are controlled by the magnitude of the supply voltage VCCQ in a manner that will be described with reference to  FIGS. 4A and 4B  to make the rising and falling edge slew rates of the signal at the DQ_OUT terminal substantially insensitive to variations in the magnitude of the supply voltage VCCQ. 
   The switching characteristics of the output buffer  50  for two different magnitudes of the supply voltage VCCQ and VCCQ′ respectively are shown in  FIGS. 4A and 4B . The signals for the magnitude of the supply voltage VCCQ shown in  FIG. 4A  are identical to the signals shown in  FIG. 2A . Therefore, in the interest of brevity, an explanation of these signals will not be repeated. However, it will be noted that the falling edge of the PUP_signal is delayed from the falling edge of the PDN signal by the delay time t dr , and the rising edge of the PDN signal is delayed from the rising edge of the PUP_signal by the same time delay t df . Again, similar to the description for  FIG. 2A , the time delays through the gates are ignored for simplicity in  FIG. 4A . As previously explained, these delays are the result of the rising edge of the D_PUP signal being delayed from the rising edge of the D_PDN_signal by the delay t dr , and the falling edge of the D_PDN_signal being delayed from the falling edge of the D_PUP signal by the delay t df . 
   The signals shown in  FIG. 4A  are shown in  FIG. 4B  when the supply voltage VCCQ is increased to VCCQ′. As can be seen from  FIG. 4B , the falling edge of the D_PUP signal is still delayed from the falling edge of the D_PDN_signal by the delay t dr , and the rising edge of the D_PDN_signal is still delayed from the rising edge of the D_PUP signal by the delay t df . However, the inverters  56 ,  58  in the first pre-driver  54  respond to the increased supply voltage by selectively increasing the delays of the inverters  56 ,  58 . More specifically, the delay of the falling edge of the PUPEN_signal after the falling edge of the PDNEN signal is increased to t dr ′, and the delay of the rising edge of the PDNEN signal after the rising edge of the PUPEN_signal is increased to t df ′. This may be accomplished by designing the inverter  56  so that it increases the delay in outputting falling edges when the supply voltage increases, and by designing the inverter  58  so that it increases the delay in outputting rising edges when the supply voltage increases. However, other techniques can be used. For example, the inverters  56 ,  58  may be designed with a predetermined minimum delay. The inverter  56  can then be designed so that it decreases the delay in outputting rising edges when the supply voltage increases, and the inverter  58  can be designed so that it decreases the delay in outputting falling edges when the supply voltage increases. 
   The manner in which adjusting the delay of the inverters  56 ,  58  as a function of supply voltage VCCQ can maintain the slew rate constant can be seen from an examination of  FIG. 4B . By increasing the delay of the falling edge of the PUPEN_signal so that it transitions at t 1 ′, the delay of the falling edge of the PUP_signal from the falling edge of the PDN signal is increased to t dr ′. As a result, the delay in turning on the PMOS transistor  32  after turning OFF of the NMOS transistor  36  is also increased to t dr ′. As can be seen in  FIG. 4B , this increased delay has the effect of increasing the low-to-high switching time of the signal at the DQ_OUT terminal commensurate with the increase in supply voltage. Similarly, by increasing the delay of the rising edge of the PDNEN signal so that it transitions at t 4 ′, the delay of the rising edge of the PDN signal from the falling edge of the PUP_signal is increased to t df ′. As a result, the delay in turning ON of the NMOS transistor  36  after the turning OFF of the PMOS transistor  32  is also increased to t df ′. Again, this has the effect of increasing the high-to-low switching time of the signal at the DQ_OUT terminal commensurate with the increase in supply voltage. By increasing switching times of the signal at the DQ_OUT terminal commensurate with the increase in supply voltage, the rate at which the voltage changes, i.e., the slew rate, is maintained substantially constant. 
   One embodiment of a pre-driver  60  that may be used as the pre-driver  54  containing the inverters  56 ,  58  is shown in  FIG. 5 . The pre-driver  60  includes a voltage compensation circuit  64 , an example of which will be explained with reference to  FIG. 5 . The voltage compensation circuit  64  includes two output lines  70 ,  74  that provide respective signals VBIAS_PUP_P, VBIAS_PUP_N having magnitudes that decrease responsive to an increase in the magnitude of the supply voltage VCCQ. The voltage compensation circuit  64  also includes two output lines  76 ,  78  that provide respective signals VBIAS_PDN_P, VBIAS_PDN_N having magnitudes that increase responsive to an increase in the magnitude of the supply voltage VCCQ. 
   A first inverter  80  in the pre-driver  60  includes a first inverter section  82  formed by a PMOS transistor  84  and an NMOS transistor  86  coupled to each other and to an output port  88 . The transistors  84 ,  86  have their gates coupled to receive the D_PUP signal, and they provide the PUPEN_signal at the output port  88 . The transistors  84 ,  86  are coupled in series with a PMOS transistor  90  and an NMOS transistor  92 . The VBIAS_PUP_P signal is applied to the gate of the PMOS transistor  90 , and the VBIAS_PUP_N signal is applied to the gate of the NMOS transistor  92 . As explained in greater detail below, these transistors  90 ,  92  control the load impedance of the transistors  84 ,  86 , which has the effect of controlling the switching time of the first inverter section  82 . The transistors  84 ,  86  in the first inverter section  82  are coupled to a PMOS transistor  94  and an NMOS transistor  96  in a second inverter section  98 . The second inverter section  98  is essentially connected in parallel with the first inverter section  82  since the inverter section likewise has the gates of its transistors  94 ,  96  coupled to receive the D_PUP signal and their drains coupled to the output port  88 . However, the sources of the transistors  94 ,  96  are coupled to the supply voltage VCCQ and VSSQ, respectively, instead of load transistors like transistors  90 ,  92 . 
   The pre-driver  60  also includes a second inverter  100  that receives the D_PDN_signal, and it provides the PDNEN signal. The second inverter  100  is structurally and functionally identical to the first inverter  80  except that it receives the VBIAS_PDN_P and VBIAS_PDN_N, signals instead of the VBIAS_PUP_P and VBIAS_PUP_N, signals, respectively. Therefore, in the interest of brevity, these common components have been provided with the same reference numerals. 
   In operation, an increase in the magnitude of the supply voltage VCCQ causes a decrease in the magnitude of the VBIAS_PUP_P and VBIAS_PUP_N signals that are coupled to the PMOS transistor  90  and the NMOS transistor  92  in the inverter  80 . The decrease in the VBIAS_PUP_P signal causes an increase in the current through the transistor  90  when the transistor  84  is turned ON, thereby decreasing the load impedance of the transistor  90 . The decrease in the VBIAS_PUP_N signal causes a decrease in the current through the transistor  92  when the transistor  86  is turned ON, thereby increasing the load impedance of the transistor  92 . These changes in the load impedances have the effect of decreasing the time required for the PUPEN_signal to transition high and increasing the time required for the PUPEN_signal to transition low. An increase in the magnitude of the supply voltage VCCQ also causes an increase in the magnitude of the VBIAS_PDN_P and VBIAS_PDN_N signals that are coupled to the PMOS transistor  90 ′ and the NMOS transistor  92 ′ in the inverter  100 . The increase in the magnitude of the VBIAS_PDN_P signal causes the current through the transistor  90 ′ to decrease, thereby increasing the load impedance of the transistor  90 ′. The increase in the magnitude of the VBIAS_PDN_N signal causes the current through the transistor  92 ′ to increase, thereby decreasing the load impedance of the transistor  92 ′. Therefore, the time required for the PDNEN signal to transition high increases and the time required for the PDNEN signal to transition low decreases. The increased time required for the PUPEN_signal to transition low coupled with the decreased time required for the PDNEN signal to transition low has the effect of increasing the rising edge delay time t dr  responsive to an increase in the supply voltage VCCQ. Similarly, the increased time required for the PDNEN signal to transition high coupled with the decreased time required for the PUPEN_signal to transition high increases the falling edge delay time t df  responsive to an increase in the supply voltage VCCQ. 
   One embodiment of a voltage compensation circuit  120  that may be used as the voltage compensation circuit  64  in the pre-driver  60  of  FIG. 5  is shown in  FIG. 6 . The voltage compensation circuit  120  includes a comparator  122  formed by a pair of differential NMOS transistors  126 ,  128  having their sources coupled to each other and to a current sinking NMOS transistor  130 . A pair of diode-coupled PMOS load transistors  134 ,  136  are coupled between the supply voltage VCCQ and the drains of the transistors  126 ,  128 , respectively. The gate of the current sinking transistor  130  is coupled to the drain of a diode coupled NMOS transistor  138  through which a reference current I ref  flows. The transistor  138  provides a relatively constant bias voltage to the gate of the transistor  130  so that the sum of the currents flowing through the transistors  126 ,  128  is substantially constant. 
   The gate of the differential transistor  126  is coupled to receive a reference voltage v ref  from a suitable source, such as a bandgap reference generator (not shown). The gate of the differential transistor  128  is coupled to a voltage divider  140  formed by a pair of resistors  144 ,  146 . The voltage divider  140  is coupled to the supply voltage VCCQ so that the magnitude of the voltage applied to the gate of the transistors is proportional to the magnitude of the supply voltage VCCQ. 
   In operation, the voltage at the drain of the transistor  134  increases responsive to an increase in supply voltage VCCQ to provide the VBIAS_PDN_P signal, which is applied to the gate of the PMOS transistor  90 ′ ( FIG. 5 ). The bias current through the transistor  90 ′ thus decreases, as previously explained with reference to  FIG. 5 . The voltage at the drain of the transistor  136  decreases responsive to an increase in supply voltage VCCQ to provide the VBIAS_PUP_P signal, which is applied to the gate of the PMOS transistor  90 , thereby increasing the bias current through the transistor  90 . 
   The VBIAS_PDN_P signal at the drain of the transistor  134  is also coupled to the gate of a PMOS transistor  150 , which has its drain coupled to the drain of a diode-coupled NMOS transistor  152 . As a result, the increasing VBIAS_PDN_P signal decreases the magnitude of the VBIAS_PUP_N signal as well as the current through the NMOS transistor  152 . The PMOS transistor  92  ( FIG. 5 ) is coupled to the transistor  152  in a current mirror configuration. Thus, in response to the reduced VBIAS_PUP_N signal, the bias current through the transistor  152  also decreases. 
   In a similar manner, the VBIAS_PUP_P signal is applied to the gate of a PMOS transistor  156 , which has its drain coupled to the drain of a diode-coupled NMOS transistor  158 . As a result, the decreasing VBIAS_PUP_P signal causes the transistor  156  to increase the magnitude of the VBIAS_PDN_N signal as well as the current through the NMOS transistor  158 . The PMOS transistor  92 ′ ( FIG. 5 ) is coupled to the transistor  158  in a current mirror configuration. Thus, in response to the increases in the magnitude of the VBIAS_PDN_N signal, the bias current through the transistor  92 ′ also increases. The increased bias currents reduce the impedances of the transistors  90 ,  92 ′, and the decreased bias currents reduce the impedances of the transistors  90 ′,  92  to alter the delay characteristics of the pre-driver  60  ( FIG. 5 ) as previously explained. 
     FIG. 7  shows one embodiment of a memory device using that may use an output buffer in accordance with the present invention. The memory device is a conventional synchronous dynamic random access memory (“SDRAM”)  300 . However, it will be understood that output buffers according to the present invention can also be used in other types of memory devices or other circuits. The operation of the SDRAM  300  is controlled by a command decoder  304  responsive to high level command signals received on a control bus  306 . These high level command signals, which are typically generated by a memory controller (not shown in  FIG. 7 ), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, in which the “*” designates the signal as active low. The command decoder  304  generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. 
   The SDRAM  300  includes an address register  312  that receives either a row address or a column address on an address bus  314 . The address bus  314  is generally coupled to a memory controller (not shown in  FIG. 7 ). Typically, a row address is initially received by the address register  312  and applied to a row address multiplexer  318 . The row address multiplexer  318  couples the row address to a number of components associated with either of two memory arrays  320 ,  322  depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory arrays  320 ,  322  is a respective row address latch  326 , which stores the row address, and a row decoder  328 , which decodes the row address and applies corresponding signals to one of the arrays  320  or  322 . 
   The row address multiplexer  318  also couples row addresses to the row address latches  326  for the purpose of refreshing the memory cells in the arrays  320 ,  322 . The row addresses are generated for refresh purposes by a refresh counter  330 , which is controlled by a refresh controller  332 . The refresh controller  332  is, in turn, controlled by the command decoder  334 . 
   After the row address has been applied to the address register  312  and stored in one of the row address latches  326 , a column address is applied to the address register  312 . The address register  312  couples the column address to a column address latch  340 . Depending on the operating mode of the SDRAM  300 , the column address is either coupled through a burst counter  342  to a column address buffer  344 , or to the burst counter  342  which applies a sequence of column addresses to the column address buffer  344  starting at the column address output by the address register  312 . In either case, the column address buffer  344  applies a column address to a column decoder  348 , which applies various column signals to corresponding sense amplifiers and associated column circuitry  350 ,  352  for one of the respective arrays  320 ,  322 . 
   Data to be read from one of the arrays  320 ,  322  is coupled to the column circuitry  350 ,  352  for one of the arrays  320 ,  322 , respectively. The read data is then coupled to a data output buffer  356 , which applies the read data to a data bus  358 . In accordance with the present invention, the data output buffer  356  provides read data signals having slew rates that are substantially insensitive the power supply voltage changes. Data to be written to one of the arrays  320 ,  322  are coupled from the data bus  358  through a data input register  360  to the column circuitry  350 ,  352  where the write data are transferred to one of the arrays  320 ,  322 , respectively. A mask register  364  may be used to selectively alter the flow of data into and out of the column circuitry  350 ,  352 , such as by selectively masking data to be read from the arrays  320 ,  322 . 
     FIG. 8  shows an embodiment of a computer system  400  that may use the SDRAM  300  or some other memory device that contains one or more examples of the signal accelerate system of the present invention. The computer system  400  includes a processor  402  for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor  402  includes a processor bus  404  that normally includes an address bus  406 , a control bus  408 , and a data bus  410 . In addition, the computer system  400  includes one or more input devices  414 , such as a keyboard or a mouse, coupled to the processor  402  to allow an operator to interface with the computer system  400 . Typically, the computer system  400  also includes one or more output devices  416  coupled to the processor  402 , such output devices typically being a printer or a video terminal. One or more data storage devices  418  are also typically coupled to the processor  402  to store data or retrieve data from external storage media (not shown). Examples of typical storage devices  418  include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor  402  is also typically coupled to a cache memory  426 , which is usually static random access memory (“SRAM”) and to the SDRAM  300  through a memory controller  430 . The memory controller  430  includes an address bus coupled to the address bus  314  ( FIG. 7 ) to couple row addresses and column addresses to the SDRAM  300 , as previously explained. The memory controller  430  also includes a control bus that couples command signals to a control bus  306  of the SDRAM  300 . The external data bus  458  of the SDRAM  300  is coupled to the data bus  410  of the processor  402 , either directly or through the memory controller  430 . 
   Although the present invention has been described with reference to the disclosed embodiments, persons skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. For example, the switching times of the signal at the DQ_OUT terminal can be adjusted by other means, such as by adjusting the delays of the NOR gate  22  and the NAND gate  26  or the delays of the inverters  24 ,  28  as a function of supply voltage. The relative timing of the D_PUP and D_PDN signals applied to the output buffer  50  could also be adjusted commensurate with the magnitude of the supply voltage. These and other modifications are well within the skill of those ordinarily skilled in the art. Accordingly, the invention is not limited except as by the appended claims.