Abstract:
One embodiment of a magnetic memory cell includes a first line and a sense layer in electrical communication with the first line. A reference layer line is configured to carry a sense current received from the sense layer. The sense current flows from the first line through the sense layer and away from the memory cell via the reference layer to determine a resistive state of the memory cell.

Description:
BACKGROUND OF THE INVENTION 
   One type of non-volatile memory known in the art relies on magnetic memory cells. These devices, known as magnetic random access memory (MRAM) devices, include an array of magnetic memory cells. The magnetic memory cells may be of different types. For example, a magnetic tunnel junction (MTJ) memory cell or a giant magnetoresistive (GMR) memory cell. 
   Generally, the magnetic memory cell includes a layer of magnetic film in which the magnetization is alterable and a layer of magnetic film in which the magnetization may be fixed or “pinned” in a particular direction. The magnetic film having alterable magnetization may be referred to as a sense layer or data storage layer and the magnetic film that is fixed may be referred to as a reference layer or pinned layer. 
   Conductive traces (commonly referred to as word lines and bit lines or collectively referred to as write lines) are routed across the array of memory cells. Word lines extend along rows of the memory cells and bit lines extend along columns of the memory cells. A memory cell stores the bit of information as an orientation of magnetization at each intersection of a word line and a bit line. The orientation of magnetization in the sense layer aligns along an axis of the sense layer that is commonly referred to as its easy axis. Magnetic fields are applied to flip the orientation of magnetization in the sense layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer. 
   The orientation of magnetization of each memory cell will assume one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logical values of “1” and “0”. The orientation of magnetization of a selected memory cell may be changed by supplying current to a word line and a bit line crossing the selected memory cell. The currents create magnetic fields that, when combined, switch the orientation of magnetization of the selected memory cell from parallel to anti-parallel or vice versa. 
   The resistance of the memory cell differs according to the parallel or anti-parallel orientation of magnetization. When the orientation is anti-parallel, i.e., the logic “0” state, the resistance of the memory cell is at its highest. The resistance of the memory cell is at its lowest when the orientation is parallel, i.e., the logic “1” state. As a consequence, the logic state of the data bit stored in the memory cell can be determined by measuring its resistance. 
   In one configuration, conductive traces (commonly referred to as sense conductors) are routed across the array of memory cells. These sense conductors extend along rows of the memory cells and are electrically coupled to the reference layers of the memory cells. The bit lines, which extend along columns of the memory cells, are electrically coupled to the sense layers of the memory cells. A memory cell is situated at each intersection of a sense conductor and a bit line. 
   In operation, a read circuit for sensing the resistance of a memory cell is electrically coupled to each sense conductor and bit line. The read circuit selects one sense conductor and one bit line to determine the resistance and state of a particular memory cell. In one configuration, the read circuit supplies a sense current that flows through the bit line and memory cell stack to sense conductor, and back to the read circuit, where a voltage is detected. This voltage is used to determine the resistance and state of memory cell. 
   A write circuit for writing the state of each memory cell is electrically coupled to each word line and bit line. During a write operation, the write circuit selects one word line and one bit line to set the orientation of magnetization in the sense layer of the memory cell at the cross point of the selected bit line and word line. The orientation of magnetization in the sense layer of the selected memory cell is rotated in response to currents on the selected bit line and word line. These currents generate magnetic fields according to the right hand rule, which act in combination to rotate the orientation of magnetization in the sense layer. A larger current in a write line produces a stronger magnetic field around the write line. This magnetic field drops off in strength with increasing distance from the write line. 
   The magnetic field present at the sense layer is a strong function of the spacing between the sense layer and the write lines. The greater the distance between the sense layer and the write line, the larger the current must be to maintain the same magnetic field strength in the sense layer. However, larger currents and resulting stronger magnetic fields may affect the state of adjacent memory cells in the array of memory cells. Additionally, larger currents may cause electro-migration problems in the write lines, and larger currents also require using bigger drive transistors, which consume valuable space on the magnetic memory device. Larger currents and stronger magnetic fields are not always a viable option for increasing magnetic field strength to write a memory cell. 
   SUMMARY OF THE INVENTION 
   One embodiment of a magnetic memory cell includes a first line and a sense layer in electrical communication with the first line. A reference layer line is configured to carry a sense current received from the sense layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. 
       FIG. 1  is a block diagram illustrating one exemplary embodiment of a magnetic memory device, according to the present invention. 
       FIG. 2  is a perspective view illustrating one exemplary embodiment of two magnetic memory cells, according to the present invention. 
       FIG. 3  is a cross section illustrating one exemplary embodiment of two magnetic memory cells and a read circuit, according to the present invention. 
       FIG. 4  is a cross section illustrating another exemplary embodiment of two magnetic memory cells and a read circuit, according to the present invention. 
       FIG. 5  is a graph illustrating magnetic field strength versus distance from the surface of a conductor originating the magnetic field. 
   

   DETAILED DESCRIPTION 
     FIG. 1  is a block diagram illustrating one exemplary embodiment of a magnetic memory device  40 , according to the present invention. The magnetic memory device  40  includes a magnetic memory cell array  42  electrically coupled to a write circuit  44  and a read circuit  46 . The exemplary embodiment of a magnetic memory cell, indicated at  48  and described herein, has a write conductor positioned in closer proximity to a sense layer. This makes it possible to present a stronger magnetic field at the sense layer, without increasing the write current. The exemplary embodiment of the magnetic memory cell  48  is accomplished by removing a sense conductor from the memory cell. This brings one write conductor closer to the sense layer. In this configuration, the same write current can be provided through the write conductor to generate an increased magnetic field at the sense layer. This increased magnetic field combines with a second magnetic field to switch the magnetic orientation of the sense layer. The sense current for sensing the resistance and state of the memory cell  48  propagates out of the memory cell  48  through the reference layer instead of the removed sense conductor. 
   Magnetic memory cell array  42  includes a plurality of magnetic memory cells  48 . The memory cells  48  are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Only a relatively small number of memory cells  48  are shown to simplify the illustration of the magnetic memory device  40 . In practice, arrays of many different sizes can be used. 
   First lines, which are bit lines  52   a–c  extend along the y-direction in a plane on one side of the array  42 . Second lines, which are word lines  50   a–c  extend along the x-direction in a plane on an opposing side of the array  42 . There is one word line  50   a–c  for each row of the array  42 , and one bit line  52   a–c  for each column of the array  42 . Each memory cell  48  is located at a cross point of a word line  50   a–c  and a bit line  52   a–c . In one aspect, word lines  50   a–c  and bit lines  52   a–c  are in the form of conductive traces. 
   The write circuit  44  includes a row decoder  54  for selecting word lines  50   a–c , and a column decoder  56  for selecting bit lines  52   a–c  during a write operation. The write circuit  44  also supplies write currents to the selected word line  50   a–c  and bit line  52   a–c , during a write operation. 
   The read circuit  46  is for sensing the resistance of a selected memory cell  48  during a read operation. The sensed resistance is representative of the information stored at the memory cell  48 . Reference layer lines  58   a–c  extend along the x-direction in a plane on one side of the array  42  and are electrically coupled to the read circuit  46 . Bit lines  52   a–c  extend along the y-direction in a plane on an opposing side of the array  42  and are also electrically coupled to the read circuit  46 . There is one reference layer line  58   a–c  for each row of the array  42  and one bit line  52   a–c  for each column of the array  42 . Each memory cell  48  is located at a cross point of a reference layer line  58   a–c  and a bit line  52   a–c.    
   In another exemplary embodiment, each magnetic memory cell has its own independent reference layer line. This reference layer line is tied to an isolation transistor, which is turned on to sense the resistance in the magnetic memory cell. In other embodiments, one reference layer line can be tied to two or more magnetic memory cells. 
   In the present described embodiment, each reference layer line  58   a–c  extends across the memory cells  48  in one row of array  42 . During a read operation, the read circuit  46  selects a reference layer line  58   a–c  and a bit line  52   a–c  for sensing the resistance  60  of the memory cell  48  that lies at the cross point of the selected reference layer line  58   a–c  and bit line  52   a–c . The use of a reference layer line  58   a–c  to carry a sense current for determining the state of a memory cell  48  is described in detail in this application. A separate sense conductor is no longer required to carry the sense current for determining the state of a memory cell  48 . 
     FIGS. 2–4  illustrate in further detail a memory cell having a reference layer line configured to carry a sense current for determining the state of the cell, according to the present invention.  FIG. 2  is a diagram illustrating an exemplary embodiment of an array section, indicated at  70 . Array section  70  includes two magnetic memory cells, indicated at  48   a  and  48   b . Memory cells  48   a  and  48   b  include first lines, which are bit lines  52   a  and  52   b , and a second line, which is word line  50   a . Memory cells  48   a  and  48   b  include reference layer line  58   a , isolation layer  76  and word line  50   a . Isolation layer  76  is located between reference layer line  58   a  and word line  50   a.    
   Memory cell  48   a  includes bit line  52   a , sense layer  72   a , barrier layer  74   a,  reference layer line  58   a , isolation layer  76  and word line  50   a . Barrier layer  74   a  is located between sense layer  72   a  and reference layer line  58   a . Sense layer  72   a  is electrically coupled to bit line  52   a . Memory cell  48   b  includes bit line  52   b,  sense layer  72   b , barrier layer  74   b , reference layer line  58   a , isolation layer  76  and word line  50   a . Barrier layer  74   b  is located between sense layer  72   b  and reference layer line  58   a . Sense layer  72   b  is electrically coupled to bit line  52   b.    
   In the present described embodiment, reference layer line  58   a  and word line  50   a  have similar patterns, however in other embodiments reference layer line  58   a  and word line  50   a  do not have similar patterns. In one aspect, isolation layer  76  is a sheet film insulating layer and in other embodiments, isolation layer  76  can be patterned. Also, bit lines  52   a  and  52   b  are illustrated as essentially orthogonal to word line  50   a . However, bit lines  52   a  and  52   b  may lie in other angular relations to word line  50   a.    
     FIG. 3  is a cross section diagram illustrating one exemplary embodiment of the two magnetic memory cells  48   a  and  48   b  with read circuit  46 . Memory cells  48   a  and  48   b  include memory cell stacks  80   a  and  80   b  located between isolation layer  76  and bit lines  52   a  and  52   b , respectively. Isolation layer  76  is located between reference layer line  58   a  and word line  50   a.    
   Memory cell stack  80   a  includes sense layer  72   a , barrier layer  74   a  and reference layer line  58   a . Barrier layer  74   a  is located between sense layer  72   a  and reference layer line  58   a . Sense layer  72   a  is located next to bit line  52   a , and reference layer line  58   a  is located next to isolation layer  76 . Memory cell stack  80   b  includes sense layer  72   b , barrier layer  74   b  and reference layer line  58   a.  Barrier layer  74   b  is located between sense layer  72   b  and reference layer line  58   a.  Sense layer  72   b  is located next to bit line  52   b , and isolation layer  76  is next to reference layer line  58   a . Reference layer line  58   a  is electrically coupled to both memory cells  48   a  and  48   b . In other embodiments, each reference layer line is electrically coupled to only one memory cell and an isolation transistor, which is selectively activated (i.e., turned on) to read the memory cell. 
   In the present embodiment, there is not a sense conductor between the reference layer line  58   a  and isolation layer  76 . Reference layer line  58   a  serves as the sense conductor. Removing the sense conductor brings word line  50   a  closer to sense layers  72   a  and  72   b.    
   Although, bit lines  52   a  and  52   b  and sense layers  72   a  and  72   b  are illustrated as above reference layer line  58   a  and word line  50   a , in another embodiment, word line  50   a  and reference layer line  58   a  can be above the sense layers  72   a  and  72   b  and bit lines  52   a  and  52   b . Also in another embodiment, word lines  50   a–c  and bit lines  52   a–c  can be switched, such that word lines  50   a–c  are near sense layers  72   a  and  72   b , and bit lines  52   a–c  are near reference layer lines  58   a–c.    
   In the present described embodiment, bit lines  52   a  and  52   b  are next to sense layers  72   a  and  72   b , which have an alterable orientation of magnetization. The reference layer line  58   a  has a pinned orientation of magnetization. In other embodiments, the sense layers  72   a  and  72   b  and the reference layer line  58   a  both may be alterable. 
   During a read operation of memory cell  48   b , reference layer line  58   a  and bit line  52   b  are coupled to read circuit  46  for sensing the resistance and state of memory cell  48   b . A sense current  84  flows from read circuit  46  to bit line  52   b  and through sense layer  72   b  and barrier layer  74   b . Reference layer line  58   a  is configured to carry sense current  84 . Sense current  84  passes to reference layer line  58   a  and out of memory cell  48   b  to read circuit  46 . In another embodiment, the sense current can flow in a different direction. The read circuit  46  provides a constant sense current and detects the voltage magnitude between bit line  52   b  and reference layer line  58   a . This voltage is directly proportional to the resistance of memory cell  48   b . In this manner, the resistance or state of the memory cell  48   b  is determined. In a different embodiment the read circuit may employ a different method of reading the memory cell  48   b , such as providing a constant voltage and detecting the difference in sense current magnitudes for determining different states of the memory cell  48   b . Circuits and methods for sensing the resistance and state of memory cells  48  are disclosed and described in U.S. Pat. No. 6,259,644, issued Jul. 10, 2001, entitled Equipotential Sense Methods For Resistive Cross Point Memory Cell Arrays, incorporated herein by reference. 
   During a write operation for writing the memory cell  48   b , word line  50   a  and bit line  52   b  are coupled to write circuit  44 . Write currents are provided through bit line  52   b  and word line  50   a  to generate magnetic fields according to the right hand rule around the bit line  52   b  and word line  50   a . With the sense conductor removed from between the reference layer line  58   a  and isolation layer  76 , word line  50   a  is closer to sense layer  72   b . This increases the strength of the magnetic field from word line  50   a  in sense layer  72   b  using the same write current. The magnetic fields set the orientation of magnetization of the sense layer  72   b  to parallel or anti-parallel, relative to the orientation of magnetization in the reference layer line  58   a . These two stable states, parallel and anti-parallel, present different resistance values during a read operation and represent logical values of “1” and “0”. In one configuration, a higher detected resistance value represents a logical “0” state, and a lower detected resistance value represents a logical “1” state. 
   Reference layer lines  58   a–c  are made of a ferromagnetic film or a multi-layer stack of material including two or more layers of ferromagnetic material, where each pair of magnetic layers are separated by a layer of non-magnetic material. Suitable exemplary materials for the non-magnetic layers include Ru, Re, Os, Cu or Cr, or alloys of these materials. Suitable exemplary materials for reference layer lines  58   a–c  as a ferromagnetic film include NiFe or CoFe. Suitable exemplary multi-layer stacks include CoFe/Ru/CoFe or Co/Cu/Co. Additionally, these could be coupled to an anti-ferromagnetic material such as IrMn, PtMn, CrPtMn or NiMn, resulting in stacks such as NiFe/IrMn or CoFe/Ru/CoFe/IrMn. Further examples and descriptions of suitable reference layer lines  58   a–c  are disclosed in U.S. patent application Ser. No. 10/283559 entitled “Magnetic Memory Device And Methods For Making Same.” This application is incorporated herein by reference. Reference layer lines  58   a–c  may further include thin seed layers such as Ta, Ru, Ta/Ru, or Ta/NiFe. Such seed layers establish preferred crystallographic texture in reference layer lines  58   a–c . An example of a reference layer line  58   a–c  with a seed layer is NiFe/IrMn/Ru/Ta, where Ta is the first layer deposited in the film stack. The preferred thickness range for the seed layer is 1–10 nm. It will be apparent to one skilled in the art after reading this application that other suitable materials may be used for reference layer lines  58   a–c.    
   Suitable exemplary materials for sense layers  72   a  and  72   b  include NiFe, CoFe or CoFeB and alloys of these. Suitable exemplary materials for barrier layers  74   a  and  74   b  include AlO or AlN. Suitable exemplary materials for isolation layer  76  include SiN, SiO or SiON. Word lines and bit lines  50   a–c  and  52   a–c  are made of conductive trace material, such as copper. It will be apparent to one skilled in the art that other suitable materials may be used for memory cell stacks  80   a  and  80   b  after reading this application. 
     FIG. 4  is a cross section illustrating another exemplary embodiment of two magnetic memory cells  148   a  and  148   b  with a read circuit  146 . Memory cells  148   a  and  148   b  include memory cell stacks  180   a  and  180   b  located between isolation layer  176  and, in this embodiment, first lines that are sense conductors  177   a  and  177   b , respectively. Second isolation layers  179   a  and  179   b  are located between sense conductors  177   a  and  177   b  and third lines that are bit lines  152   a  and  152   b , respectively. Isolation layer  176  is located between reference layer line  158   a  and, in this embodiment, a second line that is word line  150   a.    
   Memory cell stack  180   a  includes sense layer  172   a , barrier layer  174   a  and reference layer line  158   a . Barrier layer  174   a  is located between sense layer  172   a  and reference layer line  158   a . Sense layer  172   a  is located next to sense conductor  177   a , and reference layer line  158   a  is located next to isolation layer  176 . Memory cell stack  180   b  includes sense layer  172   b , barrier layer  174   b  and reference layer line  158   a . Barrier layer  174   b  is located between sense layer  172   b  and reference layer line  158   a . Sense layer  172   b  is located next to sense conductor  177   b , and isolation layer  176  is located next to reference layer line  158   a . Reference layer line  158   a  is electrically coupled to both memory cells  148   a  and  148   b . In other embodiments, each reference layer line is electrically coupled to only one memory cell and an isolation transistor, which is turned on to read the memory cell. 
   In the present embodiment, there is not a sense conductor between the reference layer line  158   a  and isolation layer  176 . Reference layer line  158   a  serves as the sense conductor. Removing the sense conductor brings word line  150   a  closer to sense layers  172   a  and  172   b.    
   Reference layer line  158   a  and word line  150   a  have similar patterns. However, in other embodiments reference layer line  158   a  and word line  150   a  do not have similar patterns. Also, isolation layer  176  is a sheet film insulating layer and in other embodiments isolation layer  176  can be patterned. Sense layers  172   a  and  172   b  have an alterable orientation of magnetization and reference layer line  158   a  has a pinned orientation of magnetization. In other embodiments, the sense layers  172   a  and  172   b  and the reference layer line  158   a  may both be alterable. 
   Although bit lines  152   a  and  152   b  and memory cell layers through sense layers  172   a  and  172   b  are illustrated as above reference layer line  158   a , isolation layer  176  and word line  150   a , in another embodiment word line  150   a , isolation layer  176  and reference layer line  158   a  can be above sense layers  172   a  and  172   b  and other memory cell layers through bit lines  152   a  and  152   b . Also, in another embodiment, word lines such as  150   a , and bit lines such as  152   a  and  152   b  can be switched so word lines  150   a  are near sense layers  172   a  and  172   b  and bit lines  152   a  and  152   b  are near reference layer lines such as  158   a.    
   In the present described embodiment, reference layer line  158   a  and sense conductors  177   a  and  177   b  are electrically coupled to read circuit  146  for reading memory cells  148   a  and  148   b . Word line  150   a  and bit lines  152   a  and  152   b  are electrically coupled to a write circuit (not shown) for writing memory cells  148   a  and  148   b . Word line  150   a  and bit lines  152   a  and  152   b  are isolated from sense layers  172   a  and  172   b  and reference layer line  158   a . In other words, a read operation is electrically isolated from a write operation. Read operations and write operations can occur simultaneously or at different times. 
   In one example read operation of memory cell  148   b , reference layer line  158   a  and sense conductor  177   b  are coupled to read circuit  146  for sensing the resistance and state of memory cell  148   b . A sense current  184  flows from read circuit  146  to sense conductor  177   b  and through sense layer  172   b  and barrier layer  174   b . Reference layer line  158   a  is configured to carry sense current  184 . Sense current  184  passes to reference layer line  158   a  and out of memory cell  148   b  to read circuit  146 . In another embodiment, the sense current can flow in a different direction. The read circuit  146  provides a constant sense current and detects the voltage magnitude between sense conductor  177   b  and reference layer line  158   a . This voltage is directly proportional to the resistance of memory cell  148   b . In this manner, the resistance and state of the memory cell  148   b  is determined. In a different embodiment, the read circuit can employ a different method of reading the memory cell  148   b , such as providing a constant voltage and detecting the difference in sense current magnitudes for determining different states of the memory cell  148   b . Circuits and methods for sensing the resistance and state of memory cell  148   b  are disclosed and described in U.S. Pat. No. 6,259,644, issued Jul. 10, 2001, entitled Equipotential Sense Methods For Resistive Cross Point Memory Cell Arrays, incorporated herein by reference. 
   During a write operation for writing the memory cell  148   b , word line  150   a  and bit line  152   b  are coupled to a write circuit. Write currents are provided through bit line  152   b  and word line  150   a  to generate magnetic fields according to the right hand rule around the bit line  152   b  and word line  150   a . With the sense conductor removed from between the reference layer line  158   a  and isolation layer  176 , word line  150   a  is closer to sense layer  172   b . This increases the strength of the magnetic field from word line  150   a  in sense layer  172   b  using the same write current. The magnetic fields set the orientation of magnetization of the sense layer  172   b  to parallel or anti-parallel, relative to the orientation of magnetization in the reference layer line  158   a . These two stable states, parallel and anti-parallel, present different resistance values during a read operation and represent logical values of “1” and “0”. In one configuration, a higher detected resistance value represents a logical “0” state, and a lower detected resistance value represents a logical “1” state. 
   Reference layer line  158   a  is made of a ferromagnetic film or a multi-layer stack of material including two or more layers of ferromagnetic material. Suitable exemplary materials for reference layer line  158   a  as a ferromagnetic film include NiFe or CoFe. Suitable exemplary multi-layer stacks include CoFe/Ru/CoFe or Co/Cu/Co. Additionally, these could be coupled to an anti-ferromagnetic material such as IrMn, PtMn, CrPtMn or NiMn, resulting in stacks such as NiFe/IrMn or CoFe/Ru/CoFe/IrMn. Further examples and descriptions of suitable reference layer line  158   a  are disclosed in U.S. patent application Ser. No. 10/283559 entitled “Magnetic Memory Device And Methods For Making Same”, previously incorporated herein by reference. Reference layer line  158   a  can further include thin seed layers such as Ta, Ru, Ta/Ru, or Ta/NiFe. Such seed layers establish preferred crystallographic texture in reference layer line  158   a . An example of a reference layer line  158   a  with a seed layer is NiFe/IrMn/Ru/Ta, where Ta is the first layer deposited in the film stack. The preferred thickness range for the seed layer is 1–10 nm. It will be apparent to one skilled in the art after reading this application that other suitable materials may be used for reference layer line  158   a.    
   Suitable exemplary materials for sense layers  172   a  and  172   b  include NiFe, CoFe or CoFeB and alloys of these. Suitable exemplary materials for barrier layers  174   a  and  174   b  include AlO or AlN. Suitable exemplary materials for isolation layer  176  and second isolation layers  179   a  and  179   b  include SiN, SiO or SiON. Suitable exemplary materials for sense conductors  177   a  and  177   b  include Ta, W, Al or Cu, and word lines and bit lines  150   a  and  152   a–b  are made of conductive trace material, such as copper. It will be apparent to one skilled in the art that other suitable materials may be used for memory cell stacks  180   a  and  180   b  after reading this application. 
     FIG. 5  is a graph illustrating magnetic field strength versus distance from the surface of a conductor originating the magnetic field. Magnetic field strength drops with increasing distance from the surface of bit lines and word lines. Since reference layer lines  58   a–c  and  158   a  are configured to carry a sense current, a separate sense conductor is no longer required. By removing the sense conductor from between the reference layer and isolation layer, the word lines are located physically closer to sense layers, such as  72   a  and  72   b , and  172   a  and  172   b . With all else held constant including the write current, the magnetic field strength from a word line is greater at sense layers  72   a  and  72   b , and  172   a  and  172   b . Alternatively, a smaller write current can be used through the word line to generate a magnetic field of sufficient strength to alter the magnetic orientation of sense layers  72   a  and  72   b , and  172   a  and  172   b  (i.e., to change or set the state of the memory cell).