Abstract:
A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a memory element, and more particularly to a phase-change memory element. 
         [0003]    2. Description of the Related Art 
         [0004]    Most electronic equipment uses different types of memories, such as DRAM, SRAM and flash memory or a combination of these memories based on the requirements of the application, the operating speed, the memory size and the cost considerations of the equipment. The current developments in the memory technology field include FeRAM, MRAM and phase-change memory. Among these alternative memories, phase-change memory will be the most likely to be mass manufactured in the near future. 
         [0005]    Phase-change memory is targeted for applications currently utilizing flash non-volatile memory. Such applications are typically mobile devices which require low power consumption, and hence, minimal programming currents. A phase-change memory cell should be designed with several goals in mind: low programming current, higher reliability (including electromigiation risk), smaller cell size, and faster phase transformation speed. These requirements often set contradictory requirements on feature size, but a careful choice and alignment of materials used for the components can often widen the tolerance. 
         [0006]    In order to reduce the programming current, the most straightforward way is to shrink the heating area. A benefit of this strategy is simultaneous reduction of cell size. Assuming a fixed required current density, the current will shrink in proportion to the area. In reality, however, cooling becomes significant for smaller structures, and loss to surroundings becomes more important due to increasing surface/volume ratio. As a result, the required current density must increase as heating area shrinks. This poses an electromigration concern for reliability. Hence, it is important to use materials in the cell which do not pose an electromigration concern. It is also important to improve the heating efficiency, by increasing heating flux in the active programming region while reducing heat loss to the surroundings. 
         [0007]    The requirements above are best served by sandwiching the heating region between two regions of phase-change material, preferably the chalcogenide Ge 2 Sb 2 Te 5  (GST). The thermal conductivity of this material is notably low, ˜0.2-0.3 W/m-K, due to the 20% presence of vacancies in the crystalline (fcc phase) microstructure. Heating is confined to a small area between a bottom and top portion of the chalcogenide material. A key aspect of this invention is the method of forming such a small area. The bottom portion is contained within a trench formed over the drain in one dimension, and the drain width in the other dimension. The top portion is ail extended chalcogenide line perpendicularly oriented with respect to the trench formed over the drain. Preferably, this line is parallel to, of equal width to, and directly under the metal bit-line used to access the memory cell. 
         [0008]    U.S. Pat. No. 5,789,758 assigned to Micron (“Chalcogenide Memory Cell with a Plurality of Chalcogenide Electrodes”) utilizes a pore in a dielectric layer positioned between an upper and lower chalcogenide electrode, both of which have greater cross-sectional areas than the pore. Formation of the pore in a dielectric layer is a very difficult task to do, and filling it with chalcogenide is even harder. Alternatively, formation of a chalcogenide island to be covered with dielectric is also difficult. Generally, three lithographic steps are needed to form this chalcogenide structure. It is desirable to minimize the number of lithographic steps to manufacture the device. 
         [0009]    U.S. Pat. No. 7,034,332 assigned to HP (“Nanometer-Scale Memory Device Utilizing Self-Aligned Rectifying Elements and Method of Making”) utilizes rectifying elements disposed between a set of first electrodes and a set of second electrodes. In this case, it is difficult to form the rectifying element due to lithographic difficulty. 
         [0010]    In order that fabrication process not be complicated, a phase-change memory element with a minimal number of process steps is called for. 
       BRIEF SUMMARY OF THE INVENTION 
       [0011]    An exemplary embodiment a phase-change memory element comprises a transistor, and a phase-change material layer. Particularly, the phase-change material layer is directly in contact with one terminal of the transistor. In an embodiment of the invention, the transistor comprises a field effect transistor comprising a drain electrode, a source electrode, and a gate electrode, and the phase-change material layer is directly in contact with the drain or source electrode of the field effect transistor. In another embodiment of the invention, the transistor comprises a bipolar junction transistor comprising an emitter electrode, a collector electrode, and a base electrode, and the phase-change material layer is directly in contact with the emitter or collector electrode of the bipolar junction transistor. 
         [0012]    Methods of manufacturing phase-change memory element are also provided. An exemplary embodiment of a method comprises the following steps. A substrate with a transistor formed thereon is provided. A dielectric layer is formed on the substrate. A trench passing through the dielectric layer is formed, exposing one terminal of the transistor. A phase-change material layer is formed on the dielectric layer and completely fills the trench. A conductive layer is formed on the phase-change material layer. A patterned hardmask layer with first width is formed on the conductive layer, wherein the patterned hardmask layer is perpendicular to the trench. The phase-change material layer and the conductive layer are etched using the patterned hardmask layer with first width as mask. The patterned hardmask layer is trimmed until a second width of the patterned hardmask layer is achieved, obtaining a tapered profile hardmask layer/conductive layer/phase-change material layer stack, with a bottom phase-change material pedestal. The tapered profile hardmask layers/conductive layer/phase-change material layer stack is then etched using the patterned hardmask layer with the second width as mask, obtaining a straight profile hardmask layer/conductive layer/phase-change material layer stack with the bottom phase-change material pedestal. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor, wherein the field effect transistor comprises a drain electrode, a source electrode, and a gate electrode, and the bipolar junction transistor comprises an emitter electrode, a collector electrode, and a base electrode. Therefore, the trench exposes the drain or source electrode of the field effect transistor. Alternatively, the trench exposes the emitter or collector electrode of the bipolar junction transistor. 
         [0013]    According to another embodiment of the invention, the method of manufacturing phase-change memory element comprises forming a patterned hardmask layer with first width on a phase-change material layer. The phase-change material layer is etched using the patterned hardmask layer with first width as mask. The patterned hardmask layer is trimmed until a second width of the patterned hardmask layer is achieved, obtaining a tapered profile hardmask layer/phase-change material layer stack with a bottom phase-change material pedestal. The tapered profile hardmask layer/phase-change material layer stack is etched using the patterned hardmask layer with the second width as mask, obtaining a straight profile hardmask layer/phase-change material layer stack with the bottom phase-change material pedestal. 
         [0014]    A detailed description is given in the following embodiments with reference to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
           [0016]      FIGS. 1   a - 1   g  are top view of showing a method of fabricating a phase-change memory element according to an embodiment of the invention. 
           [0017]      FIGS. 2   a - 2   e  are cross sections are sectional diagrams of  FIGS. 1   a - 1   g  along line A-A′. 
           [0018]      FIGS. 3   a - 3   g  are cross sections are sectional diagrams of  FIGS. 1   a - 1   g  along line B-B′. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0019]    The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
         [0020]    The invention provides a memory cell comprising a heated phase-change element. Heating takes place at the intersection of phase-change regions. The heating area is defined by a trench on top of the driving transistor drain, along with the width of a chalcogenide line oriented perpendicularly to said trench. The structure allows for simplification of photolithographic patterning as the critical phase-change layers can be defined as line patterns rather than area patterns. 
         [0021]    The manufacturing process of the phase-change memory element of an embodiment of the invention is disclosed below. First, referring to  FIG. 1   a  showing a schematic top view, a substrate  100  with a first dielectric layer  110  formed completely thereon is provided.  FIG. 2   a  is a sectional diagram along line A-A′ of  FIG. 1   a . Referring to  FIG. 2   a  , there are a plurality of transistors  120  formed on the substrate  100 , wherein the transistors  120  at least comprises a source electrode  121 , a drain electrode  122 , a channel  123 , a gate electrode  124 , and a gate insulator  125 . The choices for the transistor  120  are unlimited, and can be amorphous-silicon thin film transistor, low temperature poly-silicon thin film transistor (LTPS-TFT), or organic thin film transistor (OTFT). Alternatively, bipolar junction transistors may be used. The structure of the field effect transistor is illustrated as an example, but not intended to be limitative of the invention. In  FIG. 1   a  , there is a plurality of word line gates  130  comprising gate electrodes  124  extending along a Y direction. 
         [0022]    Next, referring to  FIGS. 1   b  and  2   b  , an oxide protective layer preferably at least 20 nm thick is applied over a planarized surface with the formed structures underneath for the purpose of protection from subsequent processing. A trench  140  is formed over the drain electrode  122  by etching the first dielectric layer  110  and the gate insulator  125  with a patterned photoresist as mask. Herein, the trenches  140  extend along the Y direction parallel to the gate lines  130 , and pass through the first dielectric layer  110  and the gate insulator  125  over the drain electrode  122  exposing the top surface of the drain electrode  122 , referring to  FIG. 3   a  showing a sectional diagram along line B-B′ of  FIG. 1   b  . The trench can has a depth D between 20˜150 nm, preferably 100 nm. It should be noted that the patterning of narrow trench  140  is easier than the patterning of a small contact hole used in the conventional fabricating method, since the normalized image log slope is better. It call be improved ever more so by use a negative photoresist, where a larger exposed feature leads to narrower trench. 
         [0023]    Next, referring to  FIG. 1   c  , a phase-change material layer  150  is deposited on the substrate  100  so as to completely fill the trench  140 . Specifically, referring to  FIG. 2   c  , the phase-change material layer  150  over the drain electrode  122  has a height H larger than the depth D of the trench  140 . The difference between the height H and the depth D is 10˜100 nm, preferably 50 nm. The phase-change layer can comprise In, Ge, Sb, Te or combinations thereof, such as GeSbTe or InGeSbTe. 
         [0024]    Next, referring to  FIGS. 1   d ,  2   d  and  3   b , a conductive layer  160  is formed ob the phase-change material layer  150 . Suitable material of the conductive layer  160  can be TaN, W, TiN, or TiW. 
         [0025]    Next, referring to  FIGS. 1   e  ,  2   e , and  3   c , a plurality of patterned hardmask layers  170  is formed on the conductive layer  160  over the source and drain electrode  121  and  122  of the transistor  120 . Particularly, the patterned hardmask layers  170  are perpendicular to the gate lines  130  and the trenches  140 , and has a width W 1  greater than the width of the thin film transistor  120  (the width of the source and drain electrodes  121  and  122 ). The patterned hardmask layers  170  can be an oxide or oxynitride layer and formed by PECVD. 
         [0026]    Next, referring to  FIGS. 1   f  and  3   d , the phase-change material layer  150  and the conductive layer  160  is etched with the patterned hardmask layers  170  as mask and the first dielectric layer  110  and the gate insulator  125  acting as an etch stop. After etching, the patterned phase-change material layer  150   a  and the conductive layer  160   a  with the width W 1  is obtained. Herein, a chlorine-base etch (preferably Ar/Cl2) is then used to etch through the phase-change material layer  150  and the conductive layer  160  without etching the patterned hardmask layers  170  appreciably. The etching until all the phase-change material layer  150  is removed outside the patterned hardmask layers  170  (outside the thin film transistors  120 ). 
         [0027]    Next, referring to  FIG. 3   e , a trimming process is performed to the patterned hardmask layers  170 , as well as the underlying exposed the patterned phase-change material layer  150   a  and the conductive layer  160   a  . Specifically, the hardmask layer  170  is trimmed by etching with fluorine-rich etchant until the desired final width W 2  is achieved. The results is a tapered profile hardmask layers  170   a /conductive layer  160   b /phase-change material layer  150   b  stack on top with a wider bottom phase-change material pedestal. 
         [0028]    Next, referring to  FIGS. 1   g  and  3   f , an etching is optionally performed to the hardmask layers  170   a /conductive layer  160   b /phase-change material layer  150   b  stack  200  to straighten the profile and tune the height of phase-change material pedestal if desired. In the etching step, the hardmask layer  170   a  serves as etching mask with chlorine-based etchant. Further, the etching method can be dry etching if the hardmask layer  170   a  has sufficient thickness. It should be noted that the hardmask layer  170   a  is patterned by photolithography process and trimmed by trimming process such as a dry trimming process or solution trimming process, resulting in a photoresist pattern with a width less than the resolution limit of the photolithography process. Then, the conductive layer  160   b  and phase-change material layer  150   b  are etched with the reduced hardmask layer  170   a  as a mask, obtaining conductive layer  160   c  and phase-change material layer  150   c  with reduced width W 2 . After etching, referring to  FIG. 1   g , the conductive layer  160   c  comprises a plurality of bit lines. 
         [0029]    Finally, referring to  FIG. 3   g  , a second dielectric layer  190  is formed on the substrate  100  to fill the trench  140  around the phase-change material layer  150   c  , in preparation for continued backed-end processing. 
         [0030]    Accordingly, in the embodiments of the invention, there is no additional bottom electrode contact with the phase-change material layer in the structure of the phase-change memory element, thereby saving a round of difficult lithographic processing. Furthermore, the critical lithography steps are all based on defining lines and spaces. This enables more aggressive and flexible scaling. Moreover, the top portion of the phase-change material layer  150   c  can have a diameter less than the resolution limit of photolithography process. The crystallization time is minimized due to very good heating uniformity in the small volume between the bit lines and bottom pedestal of the phase-change material layer. As a result, an operation current and duration for a state conversion of the phase-change material layer may be reduced so as to decrease power dissipation of the phase-change memory element. 
         [0031]    While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.