Abstract:
A system for routing a data packet between N elements includes N network interfaces respectively connected to the N elements, with N being an even integer, and an on-chip packet-switched communication network arranged in a ring structure. The packet-switched communication network includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each pair of ring links couples two adjacent routers in the ring structure, and each ring link provides two virtual channels. There are N/2 pairs of opposite uni-directional crossing links, with each pair of crossing links coupling two diametrically opposite routers in the ring structure. Processing circuitry is distributed within the N routers and the N network interfaces for determining direction of the data packet to be transmitted over a path from a source element to a destination element in the ring structure, and for determining at each router in the path which virtual channel is to be used to avoid deadlocks in the transmission

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates in general to on-chip communication networks, and more particularly, to a packet-switched network.  
       BACKGROUND OF THE INVENTION  
       [0002]     There are two fundamental approaches toward building a network core: circuit switching and packet switching. In circuit-switched networks, the resources needed along a path (buffers, links) for providing communication between the end systems are reserved for the duration of the communication session.  
         [0003]     European Patent No. 1,257,100 discloses a circuit-switched network, partly scalable, with a number of the nodes being a multiple of eight. More precisely, eight nodes form a ring. It is necessary to connect several different rings with each other when more than eight nodes (still multiple of eight) are to be used  
         [0004]     In packet-switched networks, the resources are not reserved. Packets use the resources on demand, and as a consequence, may not have to wait for access to a communication link. However, in conventional packet-switched networks, problems exist, such as a lack of scalability and deadlock.  
         [0005]     Deadlock is a situation where a group of data packets are unable to make progress because they are waiting on one another. In other words, a data packet is unable to make progress because other data packets block resources which are necessary for the data packet to progress toward its destination.  
         [0006]     Approaches exist, including a general purging of resources, but this causes a loss of data. Moreover, the current shared bus systems show their limitations in terms of performance, scalability, power consumption and reliability.  
       SUMMARY OF THE INVENTION  
       [0007]     An object of the present invention is to provide an on-chip communication architecture based on micro-networks implementing a flexible packet-switched communication, which is free of deadlock.  
         [0008]     Another object of the present invention is to provide a scalable packet-switched system having a low cost, even if the number of nodes is large, such as more than eight, for example.  
         [0009]     The system for routing data packets between elements comprises N network interfaces respectively adapted to be connected to N elements, with N being an even integer, and an on chip packet-switched communication network is arranged in a unique ring structure.  
         [0010]     The ring structure includes N routers respectively connected to the N interfaces, and N pairs of opposite uni-directional ring links. Each ring link may carry two virtual channels, and one pair of ring links may couple two adjacent routers on the ring. The ring structure may also include N/2 pairs of opposite uni-directional crossing links, with one pair of crossing links coupling two diametrically opposite routers of the ring.  
         [0011]     The system may further comprise processing means or circuitry, distributed within the routers and the network interfaces, and adapted upon the presence of a data packet to be transmitted from a source element to a destination element. This determines the direction characteristics of the path of the data packet on the ring, and if necessary, to determine at each router belonging to the path which virtual channel is to be used so as to avoid deadlocks in the transmission.  
         [0012]     The system thus combines a unique ring regardless of the value of N, two virtual channels per each ring link, and an appropriate determination of the path within the ring structure using the virtual channels. Of course, the ring according to the invention is not necessarily circular and can have, once implemented on the chip, any geometrical form.  
         [0013]     According to a preferred embodiment of the invention, which permits any deadlock to be easily avoided, the processing is adapted to define the path for the transmitted data packet, such that the path includes at least one transition on the ring between two adjacent routers, or a crossing transition between two diametrically opposite routers followed by a circular path on the ring having at least one transition. The direction of a circular path is identical for all the transitions of the circular path.  
         [0014]     A circular path is a path on the ring, regardless of the geometrical form of the ring. The choice between the two virtual channels, if necessary, is a function of the index of the router on the ring, for example.  
         [0015]     According to a preferred embodiment, the processing may be adapted to define the path for the transmitted data packet, such that the path comprises at the most d transitions between routers, with d being equal to ceil (N/4).  
         [0016]     According to one embodiment, a data packet may comprise a header including a first field defining the presence of a crossing transition and/or the direction of a circular path on the ring, and a second field defining the destination router. The distributed processing comprises local preprocessing modules in the network interfaces. The local preprocessing module of the network interface connected to the source element is adapted for determining the content of the first field and the second field. The processing may also comprise a local router within the routers for routing such data packets in accordance with the content of the first and second fields.  
         [0017]     In a preferred embodiment, the successive routers may be indexed with consecutive indexes, and the local preprocessing module of the source network interface may comprise a calculating module for calculating a value r equal to the difference modulo N between the index of the destination router and the index of the source router, and a determining module for determining the content of the first field from the value of r.  
         [0018]     Advantageously, the indexes may be increased in the right or clockwise direction, and the determining module may be adapted to provide the content of the first field with a plurality of different values. The different values are discussed below.  
         [0019]     A first value is representative of the right or clockwise direction on the ring if the value r belongs to the set {1,2, . . . ,d}. A second value is representative of the left or counter-clockwise direction on the ring if the value r belongs to the set {N−d,N−d+1, . . . ,N−1}. A third value is representative of the crossing transition between two diametrically opposite routers if the value r is equal to N/2.  
         [0020]     A fourth value is representative of the crossing transition between two diametrically opposite routers followed by the left or counter-clockwise direction on the ring if the value r belongs to the set {d+1,d+2 . . . ,N/2−1}. The fifth value is representative of the crossing transition between two diametrically opposite routers followed by the right or clockwise direction on the ring otherwise if the value r belongs to the set {N/2+1,N/2+2, . . . ,N−d−1}.  
         [0021]     Furthermore, each router may be adapted for routing the data packet to its coupled network interface if the index of the corresponding router is equal to the content of the second field of the header of the data packet. Otherwise, each router may route the data packet according to the content of the first field of the header of the data packet on a first virtual channel if the index is greater than the content of the second field of the header of the data packet, and on a second virtual channel otherwise.  
         [0022]     Each router may comprise at least two queues connected to a uni-directional ring link connected to the router. Each virtual channel may be defined by at least one queue and the corresponding uni-directional ring link.  
         [0023]     Advantageously, indexes may be binary encoded, and the routers may be adapted to process indexes with the last ceil(log 2 (d)) bits of the indexes. Reducing the size of this data optimizes the use of the bandwidth of the network, and the processing time. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0024]     Other advantages and features of the invention will appear on examining the detailed description of embodiments, which are in no way limiting, and of the appended drawings in which:  
         [0025]      FIG. 1  illustrates a system according to the present invention;  
         [0026]      FIG. 2  illustrates routers with virtual channels for the system shown in  FIG. 1 ;  
         [0027]      FIG. 3   a  illustrates a network interface for a system according to the present invention;  
         [0028]      FIG. 3   b  illustrates a data packet according to the present invention;  
         [0029]      FIG. 4  illustrates a first path for a packet according to the present invention;  
         [0030]      FIG. 5  illustrates a second path for a packet according to the present invention;  
         [0031]      FIG. 6  illustrates a third path for a packet according to the present invention;  
         [0032]      FIG. 7  illustrates a fourth path for a packet according to the present invention; and  
         [0033]      FIG. 8  illustrates a fifth path for a packet according to an aspect of the invention.  
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0034]     Referring now to  FIG. 1 , the illustrated system  1  is incorporated on a chip IC. The system comprises N=10 routers r 0 ,r 1 , . . . ,r N-1  indexed from 0 to N−1=9 in the clockwise or right direction. Each of the routers r 0 ,r 1 , . . . ,r N-1  is connected to a respective network interface NI 0 ,NI 1 , . . . ,NI N-1 . Each of the network interfaces NI 0 ,NI 1 , . . . ,NI N-1  is connected to a corresponding element E 0 ,E 1 , . . . ,E N-1 . Elements E 0 ,E 1 , . . . ,E N-1 , can be, for example, a processor, a memory, an input, an output, a sub-system bus, or any other element.  
         [0035]     The routers r 0 ,r 1 , . . . ,r N-1  form a unique ring RG. Two adjacent routers r i ,r j  of the ring RG are linked with a pair of opposite uni-directional ring links rl ij  (from r i  to r j ) and rl ji  (from r j  to r i ) Each ring link rl kl  carries two virtual channels vl 1   kl , vl 2   kl .  
         [0036]     More precisely,  FIG. 2  represents three adjacent routers r i ,r j ,r k  of the ring RG. Each router of the system comprises a routing circuit rmi. Each router further comprises at least two queues q 1   ij , q 2   ij  and a multiplexer Mux ij  connected to the uni-directional ring link for transmitting a data packet from a router r i  to a router r j . The multiplexer Mux ij  is controlled by the routing circuit rm i . Each of the at least two queues q 1   ij , q 2   ij  permits definition of a virtual channel associated with the uni-directional ring link. Each virtual channel has at least one queue, and each uni-directional ring link rl ij  has two virtual channels vl 1   ij , vl 2   ij .  
         [0037]     Referring back to  FIG. 1 , two routers r i  and r j , diametrically opposite each other (j-i) mod N=N/2) on the ring RG are linked with a pair of opposite uni-directional crossing links cl ij  (from r i  to r j ) and cl ji  (from r j  to r i ).  
         [0038]     In  FIG. 3   a , a network interface NI i  is illustrated in greater detail. The system comprises processing circuitry, which is distributed within the routers r 0 ,r 1 , . . . ,r N-1 , and the network interfaces NI 0 ,N 1 , . . . ,NI N-1 . More precisely, the processing circuitry comprises N identical local preprocessing modules ppm 0 ,ppm 1 , . . . ,ppm N-1  located within the N network interfaces NI 0 ,NI 1 , . . . ,NI N-1 , and N identical routing modules rm 0 ,rm 1 , . . . ,rm N-1  located within the N routers r 0 ,r 1 , . . . ,r N-1 . The processing circuitry is adapted to determine the path of a data packet P from a source element E source  to a destination element E destination  of the system.  
         [0039]     The path comprises at most d transitions between routers, with d being equal to ceil(N/4). The ceil function of a variable x, when y−1&lt;x&lt;y, is equal to y, with x being a real number and y being an integer number.  
         [0040]     As illustrated in  FIG. 3   b , a data packet P comprises a header H having a first field f 1  and a second field f 2 . The network interface NI i  of a source element E source  comprises a preprocessing module ppm source  which is capable of determining the content of the two fields f 1 ,f 2  of the header H of the data packet P for a data packet P to be transmitted. The first field f 1  defines the presence of a crossing transition and/or the direction of a circular path on the ring RG. Once on the ring, the data packet P keeps the same sense clockwise or counter-clockwise. The second field f 2  contains the index of the destination router r destination  corresponding to the destination network interface NI destination  and the destination element E destination  with its index.  
         [0041]     Preprocessing modules ppm 0 ,ppm 1 , . . . ,ppm N-1  use a specific process to determine the content of the two fields f 1 ,f 2  of the header H of the data packet P to be transmitted from a source network interface NI source  to a destination network interface NI destination . Each preprocessing means ppm i  comprises a calculating module Calc i  which calculates a value r equal to the difference between the index of the destination router and the index of the source router modulo N: r=(destination−source) modulo N.  
         [0042]     Furthermore, each preprocessing module ppm i  comprises a determining module Det i  for determining the content of the first field f 1  from the value of r. More precisely:  
         [0043]     If r belongs to the set {1,2, . . . ,d}, a first value R representative of the right or clockwise direction on the ring RG is set to the first field f 1 .  
         [0044]     If r belongs to the set {N−d,N−d+1, . . . ,N−1}, a second value L representative of the left or counter-clockwise direction on the ring RG is set to the first field f 1 .  
         [0045]     If r is equal to N/2, a third value A representative of the crossing ring direction RG is set to the first field f 1 .  
         [0046]     If r belongs to the set {d+1,d+2 . . . ,N/2−1}, a fourth value (AL) representative of the crossing ring direction followed by the left or counter-clockwise direction on the ring RG is set to the first field f 1 .  
         [0047]     A fifth value AR representative of the crossing ring direction followed by the right or clockwise direction on the ring is otherwise set to the first field f 1 , i.e., if r belongs to the set {N/2+1,N/2+2, . . . ,N−d−1}.  
         [0048]     In the present example, the direction (R,L) corresponds to the increasing indexation direction of the routers r 0 ,r 1 , . . . ,r N-1 . If the indexation direction is opposite, the content of the field f 1  has the opposite value.  
         [0049]     There are five possible values for the content of the first field f 1 . Theoretically, three bits are necessary, but it is advantageously possible to encode the first field f 1  on 2 bits. This is because the case of the third value A can be joined either with the case of the fourth value AL, or with the case of the fifth value AR. In case A, after the crossing transition, the data packet P will be directly send to the corresponding network interface.  
         [0050]     An example of an algorithm illustrating this method, wherein case A (only a crossing transition) is joined with case AL (a crossing transition followed by at least one transition in the left or counter-clockwise direction on the ring RG) is shown below:  
                                                   r           (destination − source) mod N;           if ( r ∈ {1,2,3,...,d} )            then             f 1             R;            else             if ( r ∈ {N−1,N−2,N−3,...,N−d} )              then              f 1             L;             else              if ( r ∈ {d+1,d+2,...,N/2} )               then                f 1             AL;               else                f 1             AR;              endif;            endif;           endif;                      
 
         [0051]     Each routing module rm i  is capable of routing the data packet to its coupled network interface if the index i of the corresponding router is equal to the content (destination) of the second field f 2  of the header H of the data packet P. Otherwise, if its index i is greater than the content (destination) of the second field f 2  of the header H of the data packet p, the routing module rm i  routes the data packet P on the first virtual channel. If the destination is greater than its index I, then the routing module rm i  routes the data packet P on the second virtual channel.  
         [0052]     In fact, the choice of a virtual channel corresponds to the choice of the corresponding queue for temporary storing the data packet P before its transmission on the ring link.  
         [0053]     An example of an algorithm implemented in the routing module and illustrating this method is:  
                                                   if ( i = f 2  )            then             route packet P to the NI i  direction;            else             if ( i &gt; f 2  )              then               route packet P according to f 1  and               on the corresponding first virtual channel;              else               route packet P according to f 1  and               on the corresponding first virtual channel;             endif;           endif;                      
 
         [0054]     The preprocessing modules and the routing modules can be implemented by software within microcontrollers, or can be realized with logic circuits by using, for example, logic synthesis tools from the algorithm described above and converted in a specific language, like VHDL.  
         [0055]     Furthermore, all indexes used in the invention are binary encoded with bits. However, the routing modules need to use, because there is at the most d transitions in a path, only the last ceil(log 2 (d)) bits.  
         [0056]     This topology of the network associated to a method for routing data packets permits deadlock problems to be avoided. The resource dependency graph, in which the virtual channel dependency graph has no cycle, the corresponding network is deadlock free. The generic scalable network proposed in this invention has a channel dependency graph cycle free, in particular, because of the use of two virtual channels per uni-directional ring link and because of the fact that a crossing transition is always performed before eventual transitions on a circular path.  
         [0057]     Five cases of a data packet transmission according to the invention will be now illustrated. In  FIG. 4 , the path of a data packet P from the source element E 0  to the destination element E 2  is highlighted. The preprocessing module ppm 0  of the network interface NI 0  sets the value R in the first field f 1  of the header H of the data packet P. Then the routing module rm 0  of the router r 0  sends the data packet P on the ring RG in the right or clockwise direction R on the second virtual channel vl 2   01 . The router r 1  receives the data packet P. The routing module rm 1  of the router r 1  sends the data packet P on the ring RG in the right direction R on the second virtual channel vl 2   12 . When the data packet P is received by the routing module rm 2  of the router r 2 , this data packet P is transmitted to the network interface NI 2  to the destination element E 2 .  
         [0058]     In  FIG. 5 , the path of a data packet P from the source element E 1  to the destination element E 9  is highlighted. The preprocessing module ppm 1  of the network interface NI 1  sets the value L in the first field f 1  of the header H of the data packet P. Then the routing module rm 1  of the router r 1  sends the data packet P on the ring RG in the left or counter-clockwise direction L on the first virtual channel vl 1   10 . The router r 0  receives the data packet P. The routing module rm 0  of the router r 0  sends the data packet P on the ring RG, in the left direction L, on the second virtual channel vl 2   09 . When the data packet P is received by the routing module rm 9  of the router r 9 , this data packet P is transmitted to the network interface NI 9  to the destination element E 9 .  
         [0059]     In  FIG. 6 , the path of a data packet P from the source element E 8  to the destination element E 3  is highlighted. The preprocessing module ppm 8  of the network interface NI 8  sets the value A in the first field f 1  of the header H of the data packet P. Then the routing module rm 8  of the router r 8  sends the data packet P on the crossing link cl 83 . The router r 3  receives the data packet P. The routing module rm 3  of the router r 3  then transmits the data packet P to the network interface NI 3  to the destination element E 3 .  
         [0060]     In  FIG. 7 , the path of a data packet P from the source element E 1  to the destination element E 7  is highlighted. The preprocessing module ppm 1  of the network interface NI 1  sets the value AR in the first field f 1  of the header H of the data packet P. Then the routing module rm 1  of the router r 1  sends the data packet P on the crossing link cl 16 . The router r 6  receives the data packet P. The routing module rm 6  of the router r 6  sends the data packet P on the ring RG in the right direction R on the second virtual channel vl 2   67 . When the data packet P is received by the routing module rm 7  of the router r 7 , this data packet P is transmitted to the network interface NI 7  to the destination element E 7 .  
         [0061]     Finally, in  FIG. 8 , the path of a data packet P from the source element E 1  to the destination element E 5  is highlighted. The preprocessing module ppm 1  of the network interface NI 1  sets the value AL in the first field f 1  of the header H of the data packet P. Then the routing module rm 1  of the router r 1  sends the data packet P on the crossing link cl 16 . The router r 6  receives the data packet P. The routing module rm 6  of the router r 6  sends the data packet P on the ring RG in the left direction L on the first virtual channel vl 1   65 . When the data packet P is received by the routing module rm 5  of the router r 5 , this data packet P is transmitted to the network interface NI 5  to the destination element E 5 .