Abstract:
A power-saving apparatus according to the operating mode of an embedded memory is provided for solving the problems of the prior art, such as the embedded memory only being able to reduce power consumption in a normal operating mode and being unable to save power in other operating modes. The present invention divides the control circuit of the embedded memory unit into an embedded memory, a self-testing circuit and a scanning other-circuit circuit according to the operating mode. Furthermore, the present invention depends on the operating mode to determine whether the embedded memory is operating or not to reduce power consumption.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a power-saving apparatus according to the operating mode of an embedded memory. In particular, an apparatus that makes an embedded memory enter a corresponding power-saving mode according to the operating mode of the embedded memory.  
         [0003]     2. Description of the Related Art  
         [0004]     Application specific integrated circuits (ASICs) are applied to a variety of electronic elements and including a memory system. There are two methods for testing the embedded memory in ASICs. The first method uses an external testing device to connect with external pins of the ASICs and generates a variety of testing patterns to test the embedded memory. If the data read from the memory system is different from the data written to the memory system, the memory system is adjusted to a defect system by the testing devices. In order for the external testing devices to test the embedded memory, additional pins are necessary for connecting to the testing devices. Therefore, the loading of the circuit and the number of pins increases.  
         [0005]     The second method includes a built-in self-testing unit (BIST) in the ASIC for testing the embedded memory. When the ASIC receives power or an external triggering signal, the built-in self-testing unit is started, and outputs a testing pattern to test the embedded memory and compares the testing pattern with the data read from the embedded memory. The built-in self-testing unit assigns a pin to indicate whether the embedded memory is defective or not. This method requires fewer pins for testing and can test a lot of memory modules at the same time. Therefore, the testing time is reduced.  
         [0006]     A built-in self-testing unit (BIST) or a circuit thereof embedded in the ASIC was disclosed in U.S. Pat. No. 6,226,211 “Merged memory-logic semiconductor device having a built-in self test circuit.” It disclosed a technology of merging a memory and a logic circuit in a single semiconductor device. Another U.S. Pat. No. 6,226,764B1 “Integrated circuit memory devices including internal stress voltage generating circuits and methods for built-in self test”, disclosed a built-in self test circuit and method for the integrated circuit memory devices.  
         [0007]     A further U.S. Pat. No. 6,668,347B1 “Built-in self-testing for embedded memory”, discloses a built-in self-testing circuit for embedded memory.  
         [0008]     The conventional embedded memory only considers a power-saving method for a normal operating mode. The control signal stops the operation of the embedded memory in the normal operating mode to save power consumption. However, as power consumption during the testing becomes more and more important, the conventional method cannot reduce power consumption of the embedded memory according to the different operation modes (normal operating mode, scanning testing mode and memory self-test mode).  
       SUMMARY OF THE INVENTION  
       [0009]     One particular aspect of the present invention is to provide a power-saving apparatus according to the operating mode of an embedded memory to reduce power consumption of embedded memory according to different operation modes (normal operating mode, scanning testing mode and memory self-test mode).  
         [0010]     The power-saving apparatus according to the operating mode of an embedded memory includes a memory enable unit, a memory clock control unit, a self-testing circuit control unit and a scanning other-circuit control unit. The memory enable unit receives an external control signal and a selection signal of a scanning mode for outputting an enable signal to a memory enable port of an embedded memory unit. The memory clock control unit receives a clock signal and an inverse-selection signal of the scanning mode for outputting a memory clock signal to the memory of the embedded memory unit. The self-testing circuit control unit receives a self-testing selection signal, the selection signal of the scanning mode, a control signal of the scanning mode and the clock signal for outputting a self-testing circuit clock signal to a memory self-testing circuit of the embedded memory unit. The scanning other-circuit control unit receives the clock signal and the selection signal of the scanning mode for outputting an other-circuit clock signal to a scanning other-circuit circuit of the embedded memory unit.  
         [0011]     For further understanding of the invention, reference is made to the following detailed description illustrating the embodiments and examples of the invention. The description is only for illustrating the invention and is not intended to be considered limiting of the scope of the claim. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     The drawings included herein provide further understanding of the invention. A brief introduction of the drawings is as follows:  
         [0013]      FIG. 1A  is a schematic diagram of a power-saving apparatus according to the operating mode of an embedded memory of the present invention;  
         [0014]      FIG. 1B  is a schematic diagram of a self-testing circuit control unit;  
         [0015]      FIG. 1C  is a schematic diagram of a clock gate unit;  
         [0016]      FIG. 2  is a schematic diagram of a single-port power-saving structure according to the operating mode of an embedded memory of the present invention; and  
         [0017]      FIG. 3  is a schematic diagram of a dual-port power-saving structure according to the operating mode of an embedded memory of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]     Please refer to  FIG. 1 , which shows a schematic diagram of a power-saving apparatus according to the operating mode of an embedded memory of the present invention. The power-saving apparatus according to the operating mode of an embedded memory  10  includes a memory enable unit  100 , a memory clock control unit  102 , a self-testing circuit control unit  104  and a scanning other-circuit control unit  106 . The memory enable unit  100  receives an external control signal  1000  and a selection signal of a scanning mode  1002  for outputting an enable signal  1004  to an enable input port  1200  of a memory  120  of an embedded memory unit  12 . The memory enable unit  100  is an OR gate. The embedded memory unit  12  includes a memory  120 , a memory self-testing circuit  122  and a scanning other-circuit circuit  124 . The memory self-testing circuit  122  is electrically connected with the memory  120  and the scanning other-circuit circuit  124 . The memory  12  can be an SRAM or a DRAM.  
         [0019]     The memory clock control unit  102  receives a clock signal  1020  and an inverse-selection signal of the scanning mode  1022  for outputting a memory clock signal  1024  to a clock input port  1202  of the memory  120  of the embedded memory unit  12 . The memory clock control unit  102  is an AND gate. The self-testing circuit control unit  104  receives a self-testing selection signal  1040 , a selection signal of the scanning mode  1042 , a control signal of a scanning mode  1044  and the clock signal  1020  for outputting a self-testing circuit clock signal  1046  to a memory self-testing circuit  122  of the embedded memory unit  12 . The scanning other-circuit control unit  106  receives the clock signal  1020  and the selection signal of the scanning mode  1042  for outputting an other-circuit clock signal  1060  to the scanning other-circuit circuit  124  of the embedded memory unit  12 . The scanning other-circuit control unit  106  is an AND gate.  
         [0020]     Please refer to  FIG. 1B , which shows a schematic diagram of the self-testing circuit control unit. The self-testing circuit control unit  104  includes an OR gate  1041  and a clock gate unit  1043 . The OR gate  1041  receives the self-testing selection signal  1040  and the selection signal of the scanning mode  1042 . The clock gate unit  1043  receives an output control signal generated from the OR gate  1042 , the control signal of the scanning mode  1044  and the clock signal  1020  for outputting the self-testing circuit clock signal to the memory self-testing circuit  122  of the embedded memory unit  12 . Please refer to  FIG. 1C , which shows a schematic diagram of a clock gate unit. The clock gate unit  1043  further includes an OR gate  10430 , a latch circuit  10432  and an AND gate  10434 . The OR gate  10430  is used for receiving the output control signal  10410  of the OR gate  1041  and the control signal of the scanning mode  1044 . A data input port of the latch circuit  10432  is electrically connected with an output port of the OR gate  10430  and receives the clock signal  1020  via an enable input port. The latch circuit  10432  is composed of a D-type circuit and is triggered by low levels. The AND gate  10434  is electrically connected with an output port of the latch circuit  10432  and receives the clock signal  1020 .  
         [0021]     Please refer to  FIG. 2 , which shows a schematic diagram of a single-port power-saving structure according to the operating mode of an embedded memory of the present invention. The single-port power-saving structure according to the operating mode of an embedded memory includes a first clock gate unit  20 , a power-saving control circuit  22  and an embedded memory unit  24 . The first clock gate unit  20  receives a control signal  2000  and a clock signal  2002 . The first clock gate unit  20  further includes an OR gate, a latch circuit, and an AND gate. The OR gate receives the control signal  2000  and the clock signal  2002 . A data input port of the latch circuit is electrically connected with an output port of the OR gate. The latch circuit is composed of a D-type circuit. The AND gate is electrically connected with an output port of the latch circuit and a clock input port. The inner circuit of the first clock gate unit  20  is the same as  FIG. 1C .  
         [0022]     The power-saving control circuit  22  is electrically connected with the first clock gate unit  20  for receiving an output signal  206  outputted from the first clock gate unit  20 . The embedded memory unit  24  is electrically connected with the power-saving control circuit  22  for receiving a plurality of control signals outputted from the power-saving control circuit  22  to make the embedded memory unit  24  enter one of the power-saving modes according to the control signals. The embedded memory unit  24  further includes a memory  240 , a memory self-testing circuit  242  and a scanning other-circuit circuit  244 . The memory self-testing circuit  242  is electrically connected with the memory  240  and the scanning other-circuit circuit  244 . The memory  240  is an SRAM or a DRAM. The power-saving modes include a normal operating mode, a scanning mode and a self-testing mode.  
         [0023]     The power-saving control circuit  22  further includes a first OR gate  220  and a first AND gate  222 , a second clock gate unit  224 , a second OR gate  226  and a second AND gate  228 . The first OR gate  220  receives the control signal  2000  and a selection signal of a scanning mode  2200  and outputs an enable signal  2204  to an enable an input port  2400  of the memory  240  of the embedded memory unit  24 . The first AND gate  222  receives the output signal  206  of the first clock gate unit  20  and an inverse-selection signal of the scanning mode for outputting a system clock signal  2222  to a memory clock input port  2402  of the memory  240  of the embedded memory unit  24 .  
         [0024]     A second clock gate unit  224  receives an output control signal of the second OR gate  226 , a scanning mode control signal  2240  and the clock signal  2002  for outputting a self-testing signal to a self-testing clock input port  2420  of the memory self-testing circuit  242  of the embedded memory unit  24 . The second clock gate unit  224  further includes an OR gate, a latch circuit, and an AND gate. The OR gate receives a self-testing selection signal and the selection signal of the scanning mode. A data input port of the latch circuit is electrically connected with an output port of the OR gate. The AND gate is electrically connected with an output port of the latch circuit and a clock input port. The inner circuit of the second clock gate unit  224  is the same as the ones in  FIG. 1C .  
         [0025]     The second OR gate  226  receives the self-testing selection signal  2260  and the selection signal of the scanning mode  2200  for outputting the output control signal to the second clock gate unit  224 . A second AND gate  228  receives the clock signal  2002  and the selection signal of the scanning mode  2200  for outputting a clock control signal  2280  to a scanning other-circuit input port  2440  of the scanning other-circuit circuit of the embedded memory unit  24 .  
         [0026]     Please refer to  FIG. 3 , which shows a schematic diagram of a dual-port power-saving structure according to the operating mode of an embedded memory of the present invention. The dual-port power-saving structure according to the operating mode of an embedded memory includes a first clock gate unit  30 , a second clock gate unit  32 , a power-saving control circuit  34  and an embedded memory unit  36 . The first clock gate unit  30  receives a control signal  3000  and a first clock signal  3002 . The second clock gate unit  32  receives the control signal  3000  and a second clock signal  3008 . The first clock gate unit  30  and the second clock gate unit  32  further include an OR gate, a latch circuit and an AND gate. The OR gate receives the control signal  3000  and the first clock signal  3002  and the second clock signal  3008 . A data input port of the latch circuit is electrically connected with an output port of the OR gate. The AND gate is electrically connected with an output port of the latch circuit and a clock input port. The latch circuit is composed of a D-type circuit. The inner circuit of the first clock gate unit  30  and the second clock gate unit  32  are the same as the ones in  FIG. 1C .  
         [0027]     The power-saving control circuit  34  is electrically connected with the first clock gate unit  30  and the second clock gate unit  32  for receiving a first clock signal  302  outputted from the first clock gate unit  30  and a second clock signal  320  of the second clock gate unit  3 . The power-saving control circuit  34  further includes a first OR gate  340 , a first AND gate  341 , a multiplexer  342 , a second AND gate  343 , a second OR gate  344 , a third clock gate unit  345  and a second AND gate  346 . The first OR gate  340  receives the control signal  3000  and a selection signal of a scanning mode  3402  and outputs an enable signal  360  to an enable input port  3600  of the memory  360  of the embedded memory unit  36 . The first AND gate  341  receives the first clock signal  302  outputted from the first clock gate unit  30  and an inverse-selection signal of the scanning mode  3004  for outputting a first system clock signal  3410  to a first clock input port  3602  of the memory  360  of the embedded memory unit  36 .  
         [0028]     The multiplexer  342  receives the first system clock signal  3410  outputted from the first AND gate  341  and the second clock signal  320  outputted from the second clock gate unit  32 . A second AND gate  343  receives the output signal  3420  outputted from the multiplexer  342  and the inverse-selection signal of the scanning mode  3004  for outputting a second system clock signal  3430  to a second clock signal input port  3604  of the memory  36  of the embedded memory unit  36 . The second OR gate  344  receives the self-testing selection signal  3440  and the selection signal of the scanning mode  3402  for enabling the operation of the multiplexer  342 . The self-testing selection signal  3440  is electrically connected with an enable input port of the multiplexer  342 . The third clock gate unit  345  receives an output control signal  3442  of the second OR gate  344 , a control signal of the scanning mode  3006  and the output signal  3420  of the multiplexer  342  for outputting a self-testing signal  3450  to a self-testing clock input port  3620  of a memory self-testing circuit  362  of the embedded memory unit  36 .  
         [0029]     The second AND gate  346  receives the first clock signal  3002  and the selection signal of the scanning mode  3402 . An embedded memory unit  36  is electrically connected with the power-saving control circuit  34  for receiving a plurality of control signals outputted from the power-saving control circuit  34  to make the embedded memory unit  36  enter one of the power-saving modes according to the control signals. The power-saving modes include a normal operating mode, a scanning mode and a self-testing mode. The third clock gate unit  345  further includes an OR gate, a latch circuit, and an AND gate. The OR gate receives the control signal, a first clock, and a second clock. A data input port of the latch circuit is electrically connected with an output port of the OR gate. The AND gate is electrically connected with an output port of the latch circuit and a clock input port.  
         [0030]     When the dual-port power-saving structure according to the operating mode of an embedded memory executes a self-testing mode, it utilizes the multiplexer to make the signals synchronize due to the signals outputted from the two clock gate units (the first clock gate unit and the second clock gate unit) are asynchronous. When the dual-port power-saving structure according to the operating mode of an embedded memory executes a normal operating mode, it needs asynchronous signals. Therefore, the multiplexer is used for selecting the self-testing mode or the normal operating mode.  
         [0031]     However, the embedded memory unit needs to reduce power consumption in the normal operating mode, it also needs to reduce power consumption in both the memory self-testing mode and the scanning testing mode. The present invention divides the control circuit of the embedded memory unit into an embedded memory, a self-testing circuit, and a scanning other-circuit circuit according to the operating mode. The present invention depends on the operating mode to determine whether the embedded memory is operating or not to reduce power consumption.  
         [0032]     The description above only illustrates specific embodiments and examples of the invention. The invention should therefore cover various modifications and variations made to the herein-described structure and operations of the invention, provided they fall within the scope of the invention as defined in the following appended claims.