Abstract:
A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.

Description:
TECHNICAL FIELD 
       [0001]    The present invention relates in general to semiconductor devices and fabrication and more particularly to a transistor providing different threshold voltages and method of fabrication thereof. 
       BACKGROUND 
       [0002]    The threshold voltage of a transistor has an effect on the ON current and the OFF leakage current for the transistor. Typically for low voltage applications, it is desirable to have a relatively high ON current. The ON current is affected in simplified terms by a scale factor of (V gs −V th ) m  where V gs  is the gate to source voltage, V th  is the threshold voltage, and m is an exponent between 1 and 2. V gs  typically can be the supply voltage. The ON current can be increased by lowering the threshold voltage. However, it is also desirable to have a relatively low OFF leakage current. Lowering the threshold voltage causes an increase in the OFF leakage current. The OFF leakage current is affected in simplified terms by a scale factor of 10 (Vgs−Vth)/S  where S is the subthreshold slope V th ×ln 10. In this case, V gs  typically can be the voltage of the source. Thus, a change in the threshold voltage causes a desirable change in scale for the ON current but an undesirable change in scale for the OFF leakage current of the transistor and vice versa. 
       SUMMARY 
       [0003]    From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for maintaining or increasing the ON current of a transistor without also increasing the OFF current of the transistor. In accordance with the present invention, a transistor providing different threshold voltages and method of fabrication thereof are provided that substantially eliminate or greatly reduce disadvantages and problems found in conventional transistor designs. 
         [0004]    According to an embodiment of the present invention, there is provided a transistor that includes a channel region with a first portion and a second portion. A length of the second portion can be smaller than a length of the first portion. The second portion has a higher threshold voltage than the first portion. The lower threshold voltage of the first portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the second portion maintains a relatively low OFF current for the transistor. 
         [0005]    The present invention provides various technical advantages over conventional transistor designs. Some of these technical advantages are shown and described in the description of the present invention. Certain embodiments of the present invention may enjoy some, all, or none of these advantages. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    For a more complete understanding of the present invention and the advantages thereof, reference is made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which: 
           [0007]      FIGS. 1A-1C  illustrate a process for fabricating an embodiment of a channel region of a transistor; 
           [0008]      FIGS. 2A-2C  illustrate an alternative process for fabricating an embodiment of a channel region of the transistor; 
           [0009]      FIG. 3  shows a schematic circuit diagram for the transistor; 
           [0010]      FIG. 4  shows an alternative embodiment for the channel region; 
           [0011]      FIG. 5  shows an alternative embodiment for the channel region. 
       
    
    
     DETAILED DESCRIPTION 
       [0012]      FIGS. 1A-1C  show a process for fabricating an embodiment of a channel region  100  of a transistor  10 . In  FIG. 1A , channel region  100  is implanted with a dopant selected to provide a relatively low threshold voltage for transistor  10 . In  FIG. 1B , a photoresist mask  102  is formed over channel region  100  to establish a first portion  120  and leave a second portion  122  exposed. The second portion  122  of channel region  100  is implanted with a dopant selected to provide a relatively high threshold voltage. In  FIG. 1C , a finished channel region  100  is shown with first portion  120  and second portion  122 . The remainder of transistor  10  to include a gate region  104 , a source region  106 , and a drain region  108  can be formed in a conventional manner. 
         [0013]      FIGS. 2A-2C  show an alternative process for fabricating an embodiment of channel region  100  of transistor  10 . In  FIG. 2A , channel region  100  is implanted with a first dopant selected to provide a relatively low threshold voltage for transistor  10 . In  FIG. 2B , a gate region  104  is formed over channel region  100 . A photoresist mask  102  is formed over channel region  100  and gate region  104  to establish a first portion  120  and leave a second portion  122  exposed. The second portion  122  of channel region  100  is implanted with a second dopant selected to provide a relatively high threshold voltage. The implanting of the second dopant may be performed at an angle relative to transistor  10  to assist in establishing second portion  122  and first portion  120 . In  FIG. 2C , a finished channel region  100  is shown with first portion  120  and second portion  122 . The remainder of transistor  10  to include gate region  104 , source region  106 , and drain region  106  can be formed in a conventional manner. 
         [0014]    In one embodiment, second portion  122  is shown in closer proximity to source region  106  of transistor  10  than first portion  120 . Though shown in this manner, transistor  10  can also be fabricated with second portion  122  being in closer proximity to drain region  108  than first portion  120 . 
         [0015]      FIG. 3  shows a schematic circuit diagram of transistor  10 . By establishing first portion  102  and second portion  104  within channel region  100 , transistor  10  logically becomes a dual transistor device with a lower threshold voltage transistor  112  serially connected with a higher threshold voltage transistor  114 . The total length of channel region  100  is similar to channel lengths of conventional transistors. Higher threshold voltage transistor  114  has a channel length of α×L, where L is the total channel length of channel region  100  and α is a fraction less than one. Lower threshold voltage transistor  112  has a channel length of L−(α×L). By optimizing a to be a small fraction (such as approximately 0.1 to 0.15), the ON current can mainly be determined by lower threshold voltage transistor  112  having a longer channel length and the OFF current can mainly be determined by higher threshold voltage transistor  114  having the shorter channel length. 
         [0016]    Higher threshold voltage transistor  114  reduces leakage current exponentially as the threshold voltage is increased. However, this has a minimal affect on the ON current of transistor  10  because the ON current is a quadrature or linear function of threshold voltage as well as from higher threshold transistor  114  having a smaller channel length. The increase resistance provided by higher threshold transistor  114  enables the threshold voltage of lower threshold transistor  112  to become even lower and still maintain a lower OFF current than a traditional transistor design with a uniform channel region. Thereby, the ON current can be further increased. In addition, the OFF leakage current from lower threshold voltage transistor  112  is essentially blocked by higher threshold voltage transistor  114 . In essence, higher threshold voltage transistor  114  acts somewhat as an insulator in the OFF state to absorb the leakage current flowing through lower threshold voltage transistor  112 . If maintaining low leakage current is of primary interest, then α can be larger (e.g., greater than 0.5). 
         [0017]      FIG. 4  shows an alternate embodiment of channel region  100  of transistor  10 . Though shown in  FIG. 3  as having higher threshold voltage transistor  114  in series with lower threshold voltage transistor  112 , channel region  100  may be implanted in a manner to provide any number of transistors within physical transistor  10 . For example, channel region  100  may have a first portion  220 , a second portion  222 , and a third portion  224 . Second portion  222  may establish a lower threshold voltage transistor  212 . First portion  220  and third portion  224  may establish higher threshold transistors  214  and  216 . First portion  220  and third portion  224  may be of equal or different lengths. Similarly, second portion  222  may establish a higher threshold voltage transistor  212 . First portion  220  and third portion  224  may establish lower threshold transistors  214  and  216 . In essence, this is an extension of the configuration discussed above with reference to  FIGS. 1A-1C  and  2 A- 2 C, where second portion  122  can be formed to separate first portion  120  into two sub-portions with each sub-portion having a similar doping profile or further processed to have different doping profiles. Further, second portion  122  may be positioned such that each sub-portion may have similar or different lengths. 
         [0018]      FIG. 5  shows an alternative embodiment of channel region  100  of transistor  10 . In this embodiment, second portion  122  has a lesser depth than first portion  120 . Second portion  122  may be implanted to provide a relatively higher threshold voltage. Second portion  122  may also be formed to include a relatively same number of dopants as it would have if it were fabricated with the same depth as first portion  120 . The amount of dopant in second portion  122  is merely confined to a smaller area, resulting in higher dopant concentration. This provides an advantage when the drain voltage of second portion  122  becomes higher. Without this embodiment, the higher drain voltage will cause more DIBL (Drain Induced Barrier Lowering) and CLM (Channel Length Modulation) effects. 
         [0019]    By selecting dopants to establish different threshold voltages in transistor  10 , the ON current for transistor  10  can be increased without causing a corresponding increase in the OFF leakage current of transistor  10 . In one example embodiment having a 100 nm length for second portion  122  and an 800 nm length for first portion  120  providing a 900 nm length for channel region  100 , second portion  122  can provide a 150 mV higher threshold voltage and first portion  120  can provide a 150 mV lower threshold voltage than a single dopant implanted channel region. The OFF leakage current may be reduced by a factor of five with a corresponding 35% increase in ON current. Moreover, this technique can be applicable for any type of transistor, including junction field effect and metal oxide semiconductor field effect transistor designs. 
         [0020]    Thus, it is apparent that there has been provided, in accordance with the present invention, a transistor with dual threshold voltages and method of fabrication thereof that satisfies the advantages set forth above. Although the present invention has been described in detail, various changes, substitutions, and alterations may be readily ascertainable by those skilled in the art and may be made herein without departing from the spirit and scope of the present invention as set out in the appended claims. Moreover, the present invention is not intended to be limited in any way by any statement made herein that is not otherwise reflected in the following claims.