Abstract:
Methods of forming electrically conductive interconnections and electrically interconnected substrates are described. In one implementation, a first substrate having an outer surface is provided and a layer of material is formed thereover. Openings are formed within the layer of material and conductive masses are formed within the openings. A second substrate having conductive interconnect surfaces is provided. The conductive interconnect surfaces are then contacted with the conductive masses and deformed thereby. In one aspect, the interconnect surfaces are deformed in part by portions of the layer of material proximate the conductive masses. In another aspect, the layer of material is removed and the interconnect surfaces are deformed by the conductive masses themselves.

Description:
TECHNICAL FIELD  
         [0001]    This invention relates to methods of forming electrically conductive interconnections and electrically interconnected substrates.  
         BACKGROUND OF THE INVENTION  
         [0002]    One method of integrated circuit interconnection is called flip chip bonding. Here, bumps of solder or other conductive material are deposited onto conductive pads of a semiconductor wafer or chip. After separation of individual dies from the wafer, the individual dies or chips are turned upside down, and the bumps are properly aligned ii with a metallization pattern on another substrate. The aligned bumps are then joined to appropriate points on the pattern.  
           [0003]    This invention arose out of concerns associated with improving flip chip bonding techniques and the substrates which are interconnected thereby.  
         SUMMARY OF THE INVENTION  
         [0004]    Methods of forming electrically conductive interconnections and electrically interconnected substrates are described. In one implementation, a first substrate having an outer surface is provided and a layer of material is formed thereover. Openings are formed within the layer of material and conductive masses are formed within the openings. A second substrate having conductive interconnect surfaces is provided. The conductive interconnect surfaces are then contacted with the conductive masses and deformed thereby. In one aspect, the interconnect surfaces are deformed in part by portions of the layer of material proximate the conductive masses. In another aspect, the layer of material is removed and the interconnect surfaces are deformed by the conductive masses themselves. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0005]    Preferred embodiments of the invention are described below with reference to the following accompanying drawings.  
         [0006]    [0006]FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment undergoing processing in accordance with one implementation of the invention.  
         [0007]    [0007]FIG. 2 is a view of the FIG. 1 wafer fragment at a different processing step.  
         [0008]    [0008]FIG. 3 is a view of the FIG. 1 wafer fragment at a different processing step.  
         [0009]    [0009]FIG. 4 is a view of the FIG. 1 wafer fragment at a different processing step.  
         [0010]    [0010]FIG. 5 is a view of the FIG. 1 wafer fragment at a different processing step.  
         [0011]    [0011]FIG. 6 is a view of the FIG. 1 wafer fragment at a different processing step.  
         [0012]    [0012]FIG. 7 is a view of the FIG. 1 wafer fragment undergoing processing in accordance with another implementation of the invention.  
         [0013]    [0013]FIG. 8 is a view of the FIG. 7 wafer fragment at a different processing step.  
         [0014]    [0014]FIG. 9 is a view of the FIG. 7 wafer fragment at a different processing step.  
         [0015]    [0015]FIG. 10 is a view of the FIG. 7 wafer fragment at a different processing step.  
         [0016]    [0016]FIG. 11 is a view of the FIG. 7 wafer fragment at a different processing step.  
         [0017]    [0017]FIG. 12 is a view of the FIG. 7 wafer fragment at a different processing step. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]    This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).  
         [0019]    Referring to FIG. 1, a semiconductor wafer fragment is shown generally at  10  and comprises a semiconductive substrate  12  which supports integrated circuitry which is not specifically shown. A pair of integrated circuitry bond pads  14 ,  16  are formed within and supported by substrate  12 . The illustrated bond pads are disposed below a substrate outer surface  18 . For purposes of the ongoing discussion, substrate  12  constitutes a first substrate.  
         [0020]    Referring to FIG. 2, a layer of material  20  is formed over outer surface  18  and bond pads  14 ,  16 . The illustrated layer has a generally planar outer surface  22 . Exemplary materials for layer  20  include insulative materials and/or photoresist. Layer  20  is formed to a height over outer surface  18  which is a desired height for conductive masses which are to be subsequently formed. An exemplary height is between about 10-30 μm.  
         [0021]    Referring to FIG. 3, portions of layer  20  are removed thereby forming openings  24 ,  26  and outwardly exposing selected substrate portions which include respective bond pads  14 ,  16 . If layer  20  is photoresist, it would simply be patterned and portions removed in accordance with conventional photoresist processing. If layer  20  is a material other than photoresist, it would be patterned and etched accordingly.  
         [0022]    Referring to FIG. 4, conductive material is provided into the openings and forms respective conductive masses  28 ,  30  received within layer  20 . The conductive material replaces the portions of layer  20  which were removed to form openings  24 ,  26 . In one aspect, the conductive material which comprises each mass is homogeneously distributed within layer  20  sufficiently to fill the respective openings. To achieve adequate filling of the openings, a non-solidified conductive material such as a silver-filled polymer epoxy material can be used. Exemplary methods for filling openings  24 ,  26  include stencil printing and screen printing. In addition, conductive material can be deposited into the openings and over the substrate and subsequently planarized as by chemical-mechanical or other polishing. If necessary, the substrate can be exposed to conditions, such as curing conditions, which are effective to harden the conductive material within openings  24 ,  26 .  
         [0023]    The illustrated masses have outermost surfaces which include respectively, outwardly exposed uppermost surface portions  32 ,  34  and sidewalls or sidewall portions  36 ,  38 . Uppermost surface portions  32 ,  34  are generally planar and coplanar with proximate portions of outer surface  22 . The individual sidewall portions for each mass face generally oppositely one another and extend generally transversely away from the substrate where each joins therewith.  
         [0024]    Referring to FIG. 5, substrate  12  is inverted or flipped over a second substrate  40 . Second substrate  40  includes an outer surface  42 . A pair of conductive structures  44 ,  46  are formed over substrate  40  and comprise respective conductive interconnect surfaces  48 ,  50 . The interconnect surface of each structure defines a respective shape which extends away from outer surface  42  and includes respective uppermost surfaces  52 ,  54 . The uppermost surfaces face generally away from substrate  40  and join with respective sidewalls  56 ,  58 . Structures  44 ,  46  have a surface area consisting of a first portion which makes physical contact with outer surface  42 . The first portion corresponds to that portion of a structure&#39;s surface area which is disposed atop and in physical contact with substrate  40 . The structures also include a second portion which does not make physical contact with substrate  40 . Such second portions include first surface areas A, A′ which are defined by uppermost surfaces  52 ,  54  respectively and sidewalls  56 ,  58 . The second portions are substantially outwardly exposed. The uppermost surfaces also define respective first heights h 1  over outer surface  42 . In one aspect, structures  44 ,  46  comprise homogeneously distributed conductive material.  
         [0025]    Referring to FIG. 6, the substrates are moved toward one another and the respective interconnect surfaces  48 ,  50  (FIG. 5) are physically contacted with the outermost surfaces of respective masses  30 ,  28 . Such moving changes the shapes of conductive structures  44 ,  46  and accordingly deforms interconnect surfaces  48 ,  50 . In the illustrated example, the conductive structures are squeezed between the first and second substrates. This generally flattens the structures relative to the structures&#39; shapes. Portions  22   a  of outer surface  22  also engage the conductive structures to effect the deformation thereof. Such deformation effectively defines different respective uppermost surfaces  53 ,  55 , and different sidewalls  57 ,  59 . Uppermost surfaces  53 ,  55  respectively define different second surface areas A 1 , A 1 ′ which are greater than first surface areas A, A′ respectively. Accordingly, uppermost surfaces  53 ,  55  define respective second heights h 2  which are less than first heights h 1 .  
         [0026]    Referring to FIG. 7, an alternate embodiment is set forth generally at  10   a . Like numerals from the above-described embodiment have been utilized where appropriate, with differences being indicated by the suffix “a” or with different numerals. Accordingly, a layer of material  20   a  is formed over first substrate  12 . Layer  20   a  can be formed to a height from between about 100 μm to 200 μm.  
         [0027]    Referring to FIG. 8, openings  24   a ,  26   a  are formed in layer  20   a  and outwardly expose bond pads  14 ,  16 .  
         [0028]    Referring to FIG. 9, conductive masses  28   a ,  30   a  are formed over substrate  12  and received within layer  20   a . Accordingly, the masses have respective heights which are defined by each masses&#39; vertically extending sidewalls  36   a ,  38   a  which are substantially the same as the height of layer  20   a , e.g., between about 100 μm to 200 μm.  
         [0029]    Referring to FIG. 10, material of layer  20   a  is removed sufficiently By to leave masses  28   a ,  30   a  over substrate  12 . Layer  20   a  can be removed through conventional techniques such as resist stripping (when photoresist is used) or through a selective etch of the layer relative to material of both the masses and the outer surface of substrate  12 .  
         [0030]    Referring to FIG. 11, a second substrate  40   a  is provided with conductive structures  44   a ,  46   a  thereover. The conductive structures include uppermost surfaces  52   a ,  54   a  which define respective surface areas B, B′.  
         [0031]    Referring to FIG. 12, substrates  12  and  40   a  are moved toward each other and masses  30   a ,  28   a  are respectively extended into and deform conductive structures  44   a ,  46   a . The masses are extended into the respective structures to below the uppermost surfaces  52   a ,  54   a  thereof a distance which is less than the respective height of each mass. The uppermost surface  34   a ,  32   a  of each mass is disposed closer to the second substrate than some portions of sidewalls  56   a ,  58   a . Accordingly, the respective structures are bonded with the uppermost surface  52   a ,  54   a  of each mass, as well as a portion of at least one of the sidewalls of each mass. In the illustrated example, portions of each sidewall of each mass are bonded with the respective conductive structures. Accordingly, less than all of each mass sidewall has conductive material of an associated conductive structure disposed laterally adjacent thereto and is disposed laterally between respective structure sidewalls  56   a ,  58   a . The portions of each mass which are not disposed within the conductive structures are disposed elevationally over those portions which are disposed within the conductive structures.  
         [0032]    Each conductive structure  44   a ,  46   a  is deformed by and through |the engagement with the respective conductive interconnect surfaces of the conductive masses. Accordingly, such defines respective second surface areas B 1  (for conductive structure  44   a ) and B 1 ′ (for conductive structure  46   a ) which are less than the respective first surface areas B, B′ in FIG. 11.  
         [0033]    The above-described embodiments provide flip chip bonding methods which improve upon techniques which are currently utilized. Material of layers  20 ,  20   a  is easily formed through commonly-employed techniques and formation of the masses therewithin is thought to be much simpler and more cost effective than current methods. In addition, desirable epoxy connections can be achieved without significant additional capacitance.  
         [0034]    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.