Abstract:
An operational amplifier achieves higher operating speed by using an all NPN transistor output drive stage. A control circuit in output drive stage receives an input signal and providing first and second control signals. The first and second control signals in turn drive first and second NPN output drive transistors arranged in a totem pole configuration between first and second power supply conductors.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to operational amplifiers, and more particularly, to an operational amplifier having an all NPN transistor output stage. 
     Operational amplifiers (op amps) are well known in electronic circuit design. A conventional op amp receives first and second input signals at its inverting and non-inverting inputs and provides an output signal as an amplified difference of the first and second input signals. The first and second input signals are typically processed through one or more differential amplifier stages and then through a differential-to-single-ended converter. An output drive stage takes the single-ended output signal and enables upper and lower output drive transistors serially coupled between first and second power supply potentials. The upper drive transistor in the output drive stage is typically NPN and the bottom drive transistor is PNP. 
     A significant problem experienced by op amps with the aforedescribed PNP-NPN transistor output stage is a limited operating frequency, say 1 MHz. The problem is principally due to the slow frequency response of the PNP transistor in the output drive stage. NPN transistors are known to operate at a much higher frequency. As the need for higher speed op amps continues to grow, it becomes advantageous to eliminate any PNP transistors from the output drive stage to allow the op amp to operate at higher frequencies. 
     SUMMARY OF THE INVENTION 
     Briefly stated, the invention comprises an output stage of an operational amplifier including a control circuit responsive to an input signal for providing first and second control signals. A first transistor includes a base receiving the first control signal, a collector coupled to a first power supply conductor, and an emitter coupled to an output of the output stage. A second transistor includes a base receiving the second control signal, an emitter coupled to a second power supply conductor, and a collector coupled to the output of the output stage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The sole FIGURE is a simplified operational amplifier with an all NPN transistor output stage. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     An op amp 10 is shown in the sole FIGURE suitable for manufacturing as an integrated circuit using conventional integrated circuit processes. Op amp 10 receives first and second input signals at its inverting and non-inverting inputs. The first and second input signals are processed through a differential input stage 12 typically comprising one or more differential transistor pairs (not shown). The output of the last differential transistor pair is coupled to differential-to-single-ended converter 14 for providing a single-ended signal to output drive stage 16. 
     As part of the present invention, output drive stage 16 uses all NPN transistors for increased operating speed. The single-ended signal from converter 14 is applied at the base of transistor 18. The collector of transistor 18 is coupled to power supply conductor 20 operating at a positive potential V CC , say +15 VDC. The emitter of transistor 18 is coupled to the output of current supply 22 at node 24. Transistor 26 includes a collector coupled to power supply conductor 20, an emitter coupled to node 24, and a base coupled to the output of current supply 28. The base of transistor 26 is also coupled through diodes 30 and 32 to power supply conductor 34 operating at a negative potential -V EE , say -15 VDC. Transistor 36 includes a collector coupled to power supply conductor 20, a base coupled to the output of current supply 28, and an emitter coupled to the collector of transistor 38. The emitter of transistor 38 is coupled through resistor 40 to power supply conductor 34, while its collector is coupled to the output of current supply 44 at the base of transistor 46. The base of transistor 38 is coupled to the bases of transistors 48 and 50 at node 24. 
     Continuing with the upper output drive, transistor 46 includes a collector coupled to power supply conductor 20 and an emitter coupled through resistor 54 to output 56 of output stage 16. Transistor 46 is the upper output drive transistor. The base of transistor 46 is also coupled to the collector of transistor 58 which includes a base coupled to the emitter of transistor 46 and an emitter coupled to output 56. Capacitor 60 is coupled between output 56 and the base of transistor 18 for compensation. 
     For the lower output drive, the collectors of transistors 48 and 50 are coupled to output 56, while the emitter of transistor 48 is coupled to power supply conductor 34 and the emitter of transistor 50 is coupled to the base of transistor 18. Capacitor 62 is coupled between the collector and base of transistor 48 for compensation. Transistor 48 has an emitter area &#34;m&#34; times the reference emitter area of transistor 26 and diodes 30 and 32, where &#34;n&#34; may be equal to six. Transistor 38 has an emitter area &#34;2n&#34; times the same reference emitter area. 
     The operation of output drive stage 16 proceeds as follows. Current supply 28 sinks a predetermined current of say 20 μa through diodes 30 and 32 and establishes a fixed voltage at the base of transistors 26 and 36. By writing voltage equation around diodes 30 and 32 and transistors 26 and 48, it can be shown that: 
     
         I.sub.28.sup.2 =I.sub.26 * I.sub.48 /n                     (1) 
    
     where 
     I 28  is the current from current supply 28 
     I 26  is the current flowing through transistor 26 
     I 48  is the current flowing through transistor 48 
     n is the emitter area ratio of transistor 48 to the reference emitter area 
     A current I 44  from current supply 44 of say 400 μa substantially flows through transistor 38 and resistor 40. 
     The base voltage necessary for transistor 38 to conduct 400 μa also drives transistor 48 and establishes its quiescent (&#34;Q&#34;) current I 48 . The relationship between the current flowing through transistor 38 and current I 48  is represented as: ##EQU1## where: R 40  is the value of resistor 40 
     q is electron charge 
     k is Boltzmann constant 
     T is absolute temperature 
     Thus, current I 26  may be determined from equation (1) at the &#34;Q&#34; of output drive stage 16. The currents I 28 , I 26 , and I 48  are thus well defined to maintain good DC stability. 
     Now consider an increasing signal from differential-to-singled-ended converter 14. Transistor 18 conducts more current and increases the voltage at node 24. Accordingly, transistor 48 turns on harder and conducts more current I 48 . Current I 26  must decrease as per equation (1). Transistor 38 also conducts more current and decreases the base voltage of transistor 46. With transistor 46 conducting less current and transistor 48 conducting more current, the voltage at output 56 decreases. 
     As the voltage at node 24 continues to increase with the increasing signal from differential-to-singled-ended converter 14, transistor 38 conducts a ratio (less than unity) of current I 48  because of degenerative resistor 40 and the difference in emitter areas. When current supply 44 can no longer source transistor 38, it starts to saturate and lowers its collector voltage. Transistor 36 turns on to supply additional collector current for transistor 38 and keep it out of saturation. If the voltage at node 24 becomes too high and transistor 48 starts to saturate, transistor 50 turns on in inverse-active mode and sources current away from the base of transistor 18, thereby limiting the base drive for transistor 48. The maximum negative voltage at output 56 is output is V EE  +V SAT48 , where V SAT48  is the saturation potential of transistor 48. 
     When the output signal from differential-to-single-ended converter 14 decreases, transistor 18 conducts less current and the voltage at node 24 falls. Transistor 26 sources current I 26  into current supply 22 to maintain its constant 80 μa current flow. Transistor 36 conducts substantially no current at this time. Transistors 38 and 48 each conduct less current with less voltage at node 24. With less current flowing through transistor 38, current supply 44 provides more base current into transistor 46, causing more current I 46  to flow through transistor 46. The voltage at output 56 increases. 
     If the sourcing current from the emitter of transistor 46 becomes to high, resistor 54 biases transistor 58 into conduction. The collector of transistor 58 then sinks current away from the base of transistor 46 to provide a current limit. The maximum positive voltage at output 56 is V CC  -V SAT44  -V be46  -I 46  *R 54 , where V SAT44  is the saturation potential of the transistor in current supply 44, V be46  is the base-emitter junction potential of transistor 46, and R 54  is the value of resistor 54. 
     Thus, a key feature of the present invention is the all NPN transistor output stage for op amp 10. The use of an NPN transistor for the upper and lower output drive allows op amp 10 to approach operating speed in the range of 100 MHz, depending on the speed of the NPN transistors. 
     While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. It is understood that the invention is not limited to the particular forms shown and it is intended for the appended claims to cover all modifications which do not depart from the spirit and scope of this invention.