Abstract:
A power factor correction device, and a controller and a total harmonic distortion (THD) attenuator used by same. The power factor correction device comprises a converter and a controller ( 320 ) connected to the converter to obtain an input voltage. The controller ( 320 ) comprises a THD attenuator ( 407 ) for automatic THD optimization. The converter comprises an input current detection resistor ( 3 R 8 ), a power switch tube ( 3 NMOS) and an output circuit. The input current detection resistor ( 3 R 8 ), the power switch tube ( 3 NMOS) and the output circuit form a feedback control loop to maintain a constant output voltage. A THD optimization function is built in the device so that the entire device is capable of being accurately offset to a designed voltage so as to be used for THD optimization, thereby dispensing with external manual adjustment and overcoming internal technical deviations while achieving high consistency.

Description:
FIELD OF THE INVENTION 
     The present invention relates to power factor correction (PFC) technology, and more particularly, to a power factor correction device, and a controller and a total harmonic distortion (THD) reducer used in the same. 
     BACKGROUND OF THE INVENTION 
     The increasing demand of active power factor devices (APFD) is driven by the concern for the quality of the power line supplies. Injection of high harmonics into the power line is well-known to cause many problems. Among these are the lower efficiency of power transmission, possible interference to other units connected to the power line, and distortion of the voltage shape that is undesirable. In addition to resolve these issues, APFD offers another advantage to increase the power level that can be drawn from the power line. 
     One of the main contributors of total harmonic distortion (THD) in active power factor correction system (APFCS) is the so-called “crossover distortion”. The root cause of the crossover distortion is due to the residual voltage across the capacitor  1 C 1  after the bridge rectifier. This residual voltage blocks the current flowing from bridge rectifier as long as the absolute AC voltage is lower than the summation of residual voltage and offset voltage of the bridge diode  1 BD 1 . During this blocking period, APFCS is equivalent to non power factor correction system. The magnitude of the residual voltage is depend on the capacitance of the total parasitic capacitor at the drain  106  of power switch tube  1 NMOS (refer to  FIG. 1 ), inductance of a boost inductor  121 , AC voltage and output load  1 RL. 
       FIG. 1  shows the prior art of the active power factor correction system for minimizing the crossover distortion. Controller  120  receives feedback signals through the various lines  104 ,  111 ,  109 ,  105 . Signal  104  is a rectified voltage derived from a voltage divider comprised of resistors  1 R 1  and  1 R 2 , and its waveform pattern is used as the reference for the desired shape of the input current. Signal  111  is the summation of boost inductor current sense signals  112  and  108  from crossover distortion reducer (CDR). The signal  112  serves to sense current flow through boost inductor  121  by sensing the voltage drop across the inductive resistor R 8 . Negative voltage at node  108  generated from CDR is proportional to the rectified main voltage and the turn ratio of the auxiliary winding of the boost inductor  121 . Symbol  109  represents a scale down boosted output signal at node  113  from the voltage divider consisting of the resistors  1 R 9  and  1 R 10 . Signal  105  obtained with an auxiliary winding on the boost inductor  121  serves to monitor the zero voltage crossing the boost inductor  121 . Controller  120  is then based on these feedback signals to generate output signal at node  110  which defines the on-off switching period of the power switch tube  1 NMOS. Capacitor  1 Cdrain is the equivalent parasitic capacitance connected between the node  106  and ground. 
     A detail functional block diagram of controller  120  which is designed to maintain the output voltage at node  113  constant by feedback control is shown in  FIG. 2 . It is consist of an error amplifier  201 , multiplier  202 , comparator  203 , zero crossing detector  204 , RS flip-flop register  205  and gate driver  206 . The error amplifier receives signal from node  109  or pin  1  which is compared with build-in reference voltage, for example 2.5V, to generate an error signal at node  107  or pin  2 . The multiplier  202  serves to multiply the error signal with the scale-down rectified signal at node  104  or pin  3  and to produce a rectified sinusoidal reference signal  2 Cr. Comparator  203  compares the rectified sinusoidal reference signal  2 Cr with signal received at node  111  or pin  4  from the CDR to create a logic signal for power switch tube  1 NMOS off control. Signal from node  105  or pin  5  is monitored by zero crossing detector  204 . At the time when a positive to negative voltage event or so-called “zero crossing” occurs, a logic high signal is generated from zero crossing detector  204  to set RS flip-flop register  205  that turns to switch on power switch tube  1 NMOS. The boost inductor current and its sense signal voltage at node  111  or pin  4  starts to rise at the time of the power switch tube  1 NMOS on. When the sense signal voltage rises up to equal to the rectified sinusoidal reference signal  2 Cr, a reset signal is produced from comparator  203  to reset the RS flip-flop register  205  that turns to switch off the power switch tube  1 NMOS. The power switch tube  1 NMOS stays off until next “zero crossing” event and the on-off switching cycle for switch tube starts over again. 
     The main concept of this prior art implementation is to fully discharge capacitor  1 C 1  at zero crossing of AC voltage. This can be done by artificially increasing the on-time of the power switch tube  1 NMOS with a negative offset on the current sense input pin  4  of controller  120  at node  111 . The negative offset voltage is introduced by CDR and its operation principle is described below: 
     During the on-time period of power switch tube  1 NMOS, voltage across the auxiliary winding  121  is negative that forward bias diode  1 D 2  to charge the capacitor  1 C 4 . A negative voltage which is proportional to RMS value of voltage and the turn ratio of the auxiliary winding  121  is maintained by capacitor  1 C 4 . This negative voltage turns to extend the on-time of power switch tube  1 NMOS through a voltage divider consisting of resistors  1 R 6  and  1 R 5 , which generates a control signal at node  111  and presents to controller  120  by pin  4 . 
     A major drawback of the prior art design is the need of manual adjustment on the resistance value of resistor  1 R 6  to find the optimum solution due to the inconsistent compensation voltage resulting from process variations between different ICs, external components and internal modules, which is not propitious to large scale production, increases system components for adding an outer power factor correction device, and as a result increases costs. 
     Accordingly, a power factor correction device requiring no manual adjustment, overcoming process variations and processing high consistency is desired. 
     SUMMARY OF THE INVENTION 
     The objective of this invention is to provide a power factor correction device requiring no manual adjustment, overcoming process variations and processing high consistency aiming at above defects in the prior art. 
     In one aspect, the power factor correction device according with the present invention comprises a converter and a controller coupled to the converter to obtain an input voltage, wherein, the controller comprises a THD reducer capable of achieving an automatic THD optimization, the converter comprises an input current sense resistor, a power switch tube and an output circuit, wherein, the input current sense resistor, power switch tube and output circuit form a feedback control loop to maintain a constant output voltage level. 
     Advantageously, the converter further comprises a bridge rectifier connected to an AC voltage to have a rectified sinusoidal voltage, and a rectified main voltage divider connected to the bridge rectifier to scale down the rectified sinusoidal voltage such that a scale-down rectified sinusoidal voltage is provided to the controller. 
     Advantageously, the output circuit comprises an output diode, an output voltage divider and an output filtering capacitor, wherein, an anode of the output diode is connected to a drain of the power switch tube, and a cathode of the output diode is connected to the output voltage divider to scale down an output voltage and provide a scale-down output voltage to the controller, and the output filtering capacitor is connected with the output voltage divider in parallel to filter high frequency components of a switching ripple voltage and store an DC output voltage. 
     Advantageously, the converter further comprises a first capacitor and a boost inductor. The first capacitor is connected with the rectified main voltage divider in parallel to filter high frequency components of the rectified sinusoidal voltage. The boost inductor has an auxiliary winding with a first terminal connected the controller and a second terminal grounded, and a primary winding with a first terminal connected an output end of the bridge rectifier, and a second terminal connected the drain of the power switch tube. 
     Advantageously, the controller comprises: 
     an error amplifier for generating a voltage error signal corresponding to a deviation between the scale-down output voltage and a predetermined reference voltage; 
     a multiplier for multiplying the scale-down rectified sinusoidal voltage with the voltage error signal to generate a sinusoidal reference signal; 
     a comparator for generating a logic signal for setting the power switch tube on period by comparing a received current sense signal received by the input current sense resistor with the sinusoidal reference signal; 
     a zero crossing detector for generating an edge logic signal to turn on the power switch tube; 
     a RS flip-flop register and a gate driver combined to create a required analog waveform pattern for driving the power switch tube and thereby approximating the shape of the current running through the boost inductor to the sinusoidal waveform of the rectified sinusoidal voltage; 
     a THD reducer for setting a THD optimization set offset voltage never changing with process variations via feedback control so as to minimize residual charges on the first capacitor at a valley of the rectified sinusoidal voltage. 
     Advantageously, the THD reducer further comprises: 
     a sampling module for sampling an output detuning voltage signal when the multiplier receives a zero input; 
     a double direction offset compensation voltage generating module for receiving two opposite voltage signals generated by a logic control module to generate a double direction offset voltage signal; 
     a comparator for generating a logic signal by comparing a summation of the output detuning voltage signal from the sampling module and the double direction offset voltage signal with the THD optimization set offset voltage; and 
     the logic control module for receiving the logic signal outputted by the comparator to generate the two opposite voltage signals. 
     Advantageously, the double direction offset compensation voltage generating module further comprises a voltage-controlled voltage source, a current source, a current sink and a second capacitor, wherein, the current source and the current sink are connected in series, the second capacitor and the current sink are connected in parallel. Wherein, the two opposite voltage signals control the current source and the current sink to charge or discharge the second capacitor for generating an offset voltage signal. The voltage-controlled voltage source receives the offset voltage signal and a fixed voltage signal to generate the double direction offset voltage signal. 
     In other aspect, a controller capable of obtaining an automatic THD optimization used by a power factor correction device according with the present invention comprises: 
     an error amplifier for generating a voltage error signal corresponding to a deviation between a scale-down output voltage and a predetermined reference voltage; 
     a multiplier for combining a scale-down rectified sinusoidal voltage with the voltage error signal to generate a sinusoidal reference signal; 
     a comparator for generating a logic signal for setting a power switch tube on period by comparing a received current sense signal received by an input current sense resistor with the sinusoidal reference signal; 
     a zero crossing detector for generating an edge logic signal to turn on the power switch tube; 
     a RS flip-flop register and a gate driver combined to create a required analog waveform pattern for driving the power switch tube and thereby approximating the shape of the current running through a boost inductor to the sinusoidal waveform of the rectified sinusoidal voltage; 
     a THD reducer for setting a THD optimization set offset voltage never changing with process variations via feedback control so as to minimize residual charges on a first capacitor at a valley of the rectified sinusoidal voltage. 
     One skilled in the art knows that the controller adapts to the preceding power factor correction device. 
     Advantageously, the THD reducer further comprises: 
     a sampling module for sampling an output detuning voltage signal when the multiplier receives a zero input; 
     a double direction offset compensation voltage generating module for receiving two opposite voltage signals generated by a logic control module to generate a double direction offset voltage signal; 
     a comparator for generating a logic signal by comparing a summation of the output detuning voltage signal from the sampling module and the double direction offset voltage signal with the THD optimization set offset voltage; and 
     the logic control module for receiving the logic signal outputted by the comparator to generate the two opposite voltage signals. 
     In another aspect, a THD reducer capable of obtaining an automatic THD optimization used by a power factor correction device according with the present invention comprises: 
     a sampling module for sampling an output detuning voltage signal when a multiplier receives a zero input; 
     a double direction offset compensation voltage generating module for receiving two opposite voltage signals generated by a logic control module to generate a double direction offset voltage signal; 
     a comparator for generating a logic signal by comparing a summation of the output detuning voltage signal from the sampling module and the double direction offset voltage signal with a THD optimization set offset voltage; and 
     the logic control module for receiving the logic signal outputted by the comparator to generate the two opposite voltage signals. 
     One skilled in the art knows that the THD reducer adapts to the preceding controller and power factor correction device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So as to further explain the invention, an exemplary embodiment of the present invention will be described with reference to the below drawings, wherein: 
         FIG. 1  is a circuit schematic of a prior art active power factor correction device for minimizing crossover distortion; 
         FIG. 2  is a functional block diagram of a prior art PFC controller; 
         FIG. 3  is a functional block diagram of a power factor correction device according to present invention; 
         FIG. 4  is a functional block diagram of a PFC controller with a built-in THD reducer according to present invention; 
         FIG. 5  is a functional block diagram of a THD reducer according to present invention; 
         FIG. 6  shows the operation waveforms of the THD Reducer 
         FIG. 7   a  shows the THD value for the prior-art PFC of  FIG. 1  with differing input voltages Vin and equivalent parasitic capacitance; 
         FIG. 7   b  shows the THD value for the present invention PFC of  FIG. 3  with differing input voltages Vin and equivalent parasitic capacitance. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     These and other advantage, aspect and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understand from the following description and drawings. Various embodiments of the present invention have only been presented by way of example instead of limitation. 
     A device equipped with an automatic THD optimization function for the correction of the power factor in an AC-DC power converter is proposed. It is an innovative solution for resolving crossover distortion problem in Active Power Factor Correction AC-DC Converter System (APFCS) without the need of manual adjustment on CDR resistor value R 6  ( FIG. 1 ) for THD optimization like the prior art described in the  FIG. 1 . The built-in THD optimization function enable the system precisely offsetting to the designed voltage for THD optimization without external manual adjustment, overcoming internal process variations, and obtaining high consistency. The operation principle of the device and method is described as following. 
       FIG. 3  illustrates a functional block diagram for APFCS in the present invention, wherein a functional block diagram of its controller  320  is shown in  FIG. 4 . This device consists of bridge rectifier  3 BD 1 , filter capacitor  3 C 1 , rectified main voltage divider consisting of resistors  3 R 1  and  3 R 2 , boost inductor  321 , controller  320 , power switch tube  3 NMOS, inductor current sense resistor  3 R 8 , output diode  3 D 3 , output capacitor  3 C 5 , output voltage divider consisting of resistors  3 R 9  and  3 R 10 , and an equivalent parasitic capacitor  3 Cdrain connected between the node  306  and ground. As the auto THD optimization is a built-in function in controller  320 , crossover distortion reducer circuit shown in  FIG. 1  is no longer required in this embodiment. 
     The AC voltage is rectified by the bridge rectifier  3 BD 1  to have a rectified sinusoidal voltage at node  302 . Filter capacitor  3 C 1  connected at the output end of the bridge rectifier  3 BD 1  is used to filter the high frequency components of the rectified sinusoidal voltage. Rectified main voltage divider consisting of resistors  3 R 1  and  3 R 2  connected in parallel with the filter capacitor  3 C 1  is to scale down rectified sinusoidal voltage such that the scale-down voltage can be used by controller  320  at pin  3 . The boost inductor  321  has a primary winding with one terminal connected an output end of the bridge rectifier  3 BD 1 , and the other terminal connected the drain of the power switch tube  3 NMOS, and further has an auxiliary winding with one terminal connected the controller  320  at pin  5  and the other terminal grounded. The power switch tube  3 NMOS has its gate connect the controller  320  at pin  7 , its source connect the controller  320  at pin  4  and grounded via inductor current sense resistor  3 R 8 . An anode of the output diode  3 D 3  is connected to a drain of the power switch tube  3 NMOS, and a cathode of the output diode  3 D 3  is connected to the output voltage divider consisting of resistors  3 R 9  and  3 R 10 . The capacitor  3 C 3  is connected between the pins  1  and  2  of the controller  320 , while the controller  320  has its pin  1  connected at the middle of resistors  3 R 9  and  3 R 10 . The pin  6  of the controller  320  is grounded. The power switch tube  3 NMOS and boost inductor  321  with auxiliary winding form a high frequency boost converter. Energy is stored in the boost inductor  312  when power switch tube  3 NMOS is on and energy is released from the boost inductor  321  transferring to the output capacitor  3 C 5  and the load  3 RL when power switch tube  3 NMOS is off The output capacitor  3 C 5  is used to filter out the high frequency contents of switching ripple voltage and store the DC output voltage. 
     Constant DC output voltage level at node  313  is maintained by DC output feedback control loop  340  formed by power switch tube  3 NMOS, output diode  3 D 3 , inductor current sense resistor  3 R 8 , output voltage divider consisting of resistors  3 R 9  and  3 R 10 , error amplifier  401  in controller  320 , multiplier  402 , comparator  403 , zero crossing detector (ZCD)  404 , RS flip-flop register  405 , and gate driver  406  ( FIG. 4 ). Its operation principle is described as following: 
     The error amplifier  401  receives a signal from pin  1  which is compared with build-in reference voltage VREF, for example 2.5V, to generate an error signal  307  at pin  2 . The multiplier  402  serves to multiply the error signal  307  received from error amplifier  401  with the scale-down rectified sinusoidal voltage  304  induced by resistors  3 R 1  and  3 R 2  of rectified main voltage divider at pin  3  to produce a sinusoidal reference signal  4 Mo which is proportional to RMS value of the AC voltage and the error signal  307  at pin  2 . As the multiplier has a complicated circuit which is seriously affected by the process variations and matching detuning, it output a detuning voltage Voff 1  of uncertain value rather than zero when receiving a zero input. Accordingly, the multiplier  402  should output Mo+Voff 1 . THD reducer  407  samples output error Voff 1  of multiplier  402  when the multiplier  402  receives a zero input, and outputs a signal Voff 2 . It is mentioned Voff 2 =Vr−Voff 1 , wherein, Vr is a fixed value independent of temperature (such as 33 mV). A summation Mo+Vr of the output Vof from THD reducer  407  and the output Mo+Voff 1  from multiplier  402  forms the sinusoidal current reference signal of comparator  403 . The comparator  403  compares the sinusoidal current reference signal with a signal from pin  4  to generate a logic signal for switching off the power switch tube  3 NMOS. Signal from pin  5  is monitored by zero crossing detector  405 . At the time when a positive to negative voltage event or so-called “zero crossing” is detected at pin  5 , a logic high signal is generated from zero crossing detector  405  to set RS flip-flop register  405  that turns to switch on power switch tube  3 NMOS. The boost inductor current and its sense signal  312  at pin  4  start to rise at the time of the power switch tube  3 NMOS on. When the sense signal  312  rises up to sinusoidal current reference signal Mo+Vr, a reset signal is produced from comparator  403  to reset the RS flip-flop register  405  that turns to switch off power switch tube  3 NMOS. The power switch tube  3 NMOS stays off until next “zero crossing” event and the switch on-off cycle for switch tube starts again. At steady state, the voltage level of error signal  307  and the on-off switching period of power switch tube  3 NMOS are determined by the input AC voltage and output load  3 RL. 
     THD optimization can be achieved by adding an appropriate offset voltage signal any where around the DC output feedback control loop  340  such that the added offset voltage forces current to pass through boost inductor when AC voltage is near zero voltage point, and thereby the residual voltage across  3 C 1  is reduced close to zero for achieving system THD optimization. 
     THD reducer  407  is the key component to enable the system depicted in  FIG. 3  built-in automatic THD optimization. The functional block diagram and operational principle of THD reducer  407  are illustrated in  FIG. 5  and  FIG. 6  respectively. THD reducer comprises a sampling module  501 , double direction offset compensation voltage generating module  502 , comparator  503  and logic control module  504 . Wherein, the double direction offset compensation voltage generating module  502  further comprises a voltage-controlled voltage source  5021 , a current source  5 I 1 , a current sink  5 I 2  and a capacitor  5 C 1 , wherein, the current source  5 I 1  and the current sink  5 I 2  are connected in series, and the second capacitor  5 C 1  and the current sink  5 I 2  are connected in parallel. 
     THD reducer  407  receives output Mo+Voff 1  from multiplier  402 , and samples output detuning voltage signal Voff 1  when the multiplier receives a zero input via the sampling module  501 . The double direction offset compensation voltage generating module  502  receives two opposite voltage signals VH and VL from logic control module  504 , and controls the current source  5 I 1  and current sink  5 I 2  to discharge and charge the capacitor  5 C 1  to generate an offset voltage signal Va. The voltage-controlled voltage source  5021  receives a difference (such as but not limited to 2.5V, one skilled in the art can set such difference according to actual requirement) between the offset voltage signal Va and a fixed voltage signal Vb, and generates a double direction offset voltage signal Voff 2  as the output of the THD reducer. The comparator  503  receives a summation Voff of the output Voff 1  from the sampling module  501  and the double direction offset voltage signal Voff 2  from the double direction offset compensation voltage generating module  502 , and compares the summation Voff with the THD optimization set offset voltage Vr to generate a logic signal Vg. The logic control module  504  receives the logic signal Vg outputted by the comparator  503  to generate the two opposite voltage signals VH and VL. The double direction offset voltage signal Voff 2  from the double direction offset compensation voltage generating module  502  is determined by the feedback loop of the THD optimization module, that is, the THD reducer  407 . Referring to  FIG. 6 , the work process is listed as follows. 
     When the summation Voff is higher than the THD optimization set offset voltage Vr, logic signal Vg outputted by the comparator  503  is a logic low signal. Two opposite voltage signals VH and VL are generated by the logic control module  504 , wherein, voltage signal VH switches off current source  5 I 1  and voltage signal VL switches on the current sink  5 I 2  to discharge the capacitor  5 C 1 , in such a way that the offset voltage signal Va is adjusted to lower than the fixed voltage signal Vb. Then the feedback control can be realized via reducing the double direction offset voltage signal Voff 2  from the double direction offset compensation voltage generating module  502  by the control of the voltage-controlled voltage source  5021 . When the summation Voff is lower than the THD optimization set offset voltage Vr, logic signal Vg outputted by the comparator  503  is a logic high signal. At this time, voltage signal VH switches on current source  5 I 1  and voltage signal VL switches off the current sink  5 I 2  to charge the capacitor  5 C 1 , in such a way that the offset voltage signal Va is adjusted to higher than the fixed voltage signal Vb. Then the summation Voff is enabled to accord with the THD optimization set offset voltage Vr or fluctuate slightly near the THD optimization set offset voltage Vr via increasing the double direction offset voltage signal Voff 2  from the double direction offset compensation voltage generating module  502  by the control of the voltage-controlled voltage source  5021 . In this way, the double direction offset voltage signal Voff 2  can be represented as Vr−Voff 1 , and then the summation of the output detuning voltage Voff 1  from multiplier and double direction offset voltage signal Voff 2  from THD reducer, that is, the THD optimization set offset voltage Vr will never change with process variations and matching detuning while obtain high consistency. 
     The summation Mo+Cr of the outputs from the THD reducer and multiplier produces a sinusoidal reference signal for comparator  403  which is used to set the off period of power switch tube  3 NMOS such that the residual voltage across the capacitor  3 C 1  after the bridge rectifier is eliminated, crossover distortion is decreased and THD optimization is achieved. 
       FIGS. 7   a  and  7   b  show the THD value for the prior-art PFC of  FIG. 1  and the present invention PFC of  FIG. 3  with differing input voltages, equivalent parasitic capacitances and chips. For the circuit depicted in  FIG. 1 , different chips have large differentia between their THD optimization values due to the affect of internal process variations and detuning. However, for the circuit depicted in  FIG. 3  of present application, its built-in system can overcome the affect of internal process variations and detuning, set appropriate fixed offset voltage for THD optimization with better effect, have substantially consistent THD optimization result between different chips and be propitious to production. 
     Although the present invention is explained by specific embodiments, one skilled in the art should understand that various modifications and equivalents can be made to this invention without departing the scope of the present invention. Accordingly, the present invention is not limited to the disclosed specific embodiments while falls into all the implementations in the scope of the claims of the present invention.