Abstract:
A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin−) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Description:
FIELD OF THE INVENTION 
   The present invention relates to analog circuits and more particularly to an improved differential sampling circuit based on a switched-capacitor approach that directly generates the real differential signal DC offset value. 
   BACKGROUND OF THE INVENTION 
   With the continuous frequency increase of signals used in modern communication links, unwanted effects such as cross talk, false ringing, parasitic reflection, offsets occur more and more often due to the distributed nature of the media which transports these signals. In the particular case of coupled lines, a major contributor is the differential input DC offset which is the result of different amplitudes and common modes on each of the lines. For instance, according to the SCSI standard for hard-disk applications (SPI4) effective to date, data are transported at 80 MHz (frequency of the system clock). At this speed, the data integrity on the bus is high enough so as to generally not require any offset cancellation technique. On the contrary, according to the next SCSI standard to be implemented in the future (SPI5), data will be transported at 160 MHz. At such a high speed, compensation of the differential input signal DC offset becomes necessary. This differential input signal DC offset is sampled and stored in a capacitor; an analog to digital converter (ADC) then converts this value to binary digits and stores it in a register latch. 
     FIG. 1  illustrates the definition of the differential input signal DC offset. As shown in  FIG. 1 , the amplitudes and common modes of a differential signal VP-VN are different between the first half and the second half of the period T of the system clock. The differential input signal DC offset is defined as being equal to the half sum of the differential amplitude ΔV 1  in the first half period and the differential amplitude ΔV 2  in the second half period. The differential input signal DC offset ΔVoffset is given by: 0.5*[(VP 1  +VP 2 )−(VN 2 +VN 1 )]=0.5*[(VP  1 −VN 1 )+(VP 2 −VN 2 )]=0.5*[ΔV 1 +ΔV 2 ]. This calculation can be performed by a sampling circuit which samples the differential input signal twice within a clock cycle and has a gain of ½. 
   The conventional differential input signal sampling circuit disclosed in “A ratio-independent algorithmic analog-to-digital conversion technique” (IEEE JSSC, vol 19, pp 828-836, December 1984) by P. W. Li, M. J. Chin, P. R. Gray, and R. Castello is of interest in some respects. It is constructed around a differential operational amplifier (opamp) provided with a switched-capacitor network in order to sample twice the differential input signal in four phases to generate 2*ΔV, if the input signal keeps its value at times of sampling, or [ΔV 1 +ΔV 2 ] if not. However, it does not aim to calculate the differential input signal DC offset, and its gain is independent of both the opamp DC offset and the capacitor values which is a determining advantage. 
     FIG. 2  shows the single-ended version (simplified diagram) of this conventional differential input signal sampling circuit  20 , which samples twice the input signal Vin, to generate a signal Vout=Vin+Vin=2*Vin, if input signal Vin remains unchanged during the sampling operations. The single ended version has been chosen in lieu of the differential one for the sake of simplicity of the description. Circuit  20  is organized around an operational amplifier (opamp)  21  and a switched-capacitor network comprising two capacitors C 1 , C 2  and six switches S 1 -S 6  connected as shown in FIG.  2 . The positive input of the opamp  21  is coupled to ground. A first capacitor C 1 , usually referred to as the holding capacitor, is coupled to its negative input and a first node  22 . A first switch S 1  is coupled between first node  22  and the input signal Vin. A second switch S 2  is coupled to first node  22  and ground. A second capacitor C 2  is coupled between a second node  23  and the opamp  21  negative input. A third switch S 3  is coupled between this negative input and the output of opamp  21 . A fourth switch S 4  is coupled to second node  23  and the output. A fifth switch S 5  is coupled between second node  23  and ground. Finally, a sixth switch S 6  is coupled to first node  22  and the output in a feedback loop. Output signal Vout that is generated by circuit  20  is independent of the opamp  21  DC offset Voff and also independent of the value of capacitors C 1  and C 2 . Operation of circuit  20  will be described by reference to  FIGS. 3   a - 3   d . In successive drawings, the status of switches S 1 -S 6  changes. They can be opened or closed according to the application algorithm. 
   Full operation of circuit  20  requires four phases: two input signal sampling and two charge transfers. Considering  FIG. 3   a , let us assume the input signal to be sampled Vin is equal to V 1 . It is easy to calculate voltage Vc 1  across capacitor C 1 , voltage Vc 2  across capacitor C 2  and output voltage Vout. At the end of the first input signal sampling, we have:
 
 Vc   1 =V−Voff
 
 Vc   2 =− V off
 
Vout=Voff
 
The charge Q 1  stored into capacitor C 1  is equal to C 1 *(V 1 −Voff).
 
   After the first sampling, the first charge transfer is performed using the configuration shown in  FIG. 3   b . The charge variation DQ 1 =C 1 *V 1  is transferred to capacitor C 2 . We then have:
 
 Vc   1 =− V off
 
 Vc   2 =− V off+ V   1 * C   1 / C   2 
 
 V out= V   1 * C   1 / C   2 
 
The first sampling and the first charge transfer described above by reference to  FIGS. 3   a - 3   b  are performed during the first half period of the system clock.
 
   Next, the second input signal sampling is performed using the configuration depicted in  FIG. 3   c . After the second input sampling, we assume that Vin has changed and is now equal to V 2 . We have:
 
 Vc   1 = V   2 − V off
 
 Vc   2 =− V off+ V   1 * C   1 / C   2  ( Vc   2  remains unchanged)
 
Vout=Voff
 
   Finally, the second charge transfer is performed using the configuration shown in  FIG. 3   d . At the end of this step, the charge Q 2  stored on C 2  is transferred to capacitor C 1  so that we have:
 
Vc 2 =−Voff
 
 DQ   2 = V   1 * C   1 
 
 Vc   1 = V   2 − V off+ DQ   2 / C   1 = V   2 − V off+ V*C   1 / C   1 = V   1 + V   2 − V off
 
 V out= V off+ Vc   1 = V   1 + V   2 
 
   The second sampling and the second charge transfer described above by reference to  FIGS. 3   c - 3   d  are performed during the second half period of the system clock. The operations described above by reference to  FIGS. 3   a-d  are thus performed at each system clock cycle. 
   Consequently, using circuit  20 , Vout equals the sum of the two sampled input values V 1  and V 2 . It is to be noted that Vout is independent of both the opamp  21  DC offset Voff and the values of capacitors C 1  and C 2 , which is beneficial. However, should we consider the differential version of circuit  20  applied to the calculation of the differential DC offset ΔVoffset, it would generate a differential voltage equal to [ΔV 1 +ΔV 2 ], so that it would have the inconvenience of requiring a ½ gain opamp connected in series at its outputs before obtaining the differential offset value which is equal to 0.5*[ΔV 1 +ΔV 2 ]. 
   SUMMARY OF THE INVENTION 
   According to the present invention there is described an improved differential sampling circuit based on a switched-capacitor network approach that directly generates the real differential input signal DC offset value. It is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an innovative block to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal that is output therefrom is equal to the real differential input signal DC offset value. 
   It is therefore a primary object of the present invention to provide an improved differential sampling circuit based on a switched-capacitor network approach that directly generates the real differential input signal DC offset value. 
   It is another object of the present invention to provide an improved differential sampling circuit configured around a differential operational amplifier and a pair of switched-capacitor network wherein the differential input signal DC offset value is independent of the differential operational amplifier DC offset. 
   It is still another object of the present invention to provide an improved differential sampling circuit based on a switched-capacitor network approach that directly generates the differential input signal DC offset value with a high accuracy to meet the SCSI-PI5 specifications. 
   In accordance with the present invention, a differential sampling circuit is provided for generating a real differential input signal DC offset value at each period of a system clock. The circuit includes a differential operational amplifier and two capacitors. The operational amplifier has an input terminal and an output terminal, and is characterized by a DC offset voltage; the capacitors each have a first terminal connected to the input terminal, and are matched with respect to capacitance value. During an input signal sampling operation in a portion of each system clock period, the charge on the first capacitor is proportional to the DC offset voltage, and the first capacitor and the second capacitor are connected in parallel during a charge transfer operation in a subsequent portion of each system clock period. The output terminal voltage during the charge transfer operation is proportional to a sum of a first input voltage applied to the input terminal during the first signal sampling operation and a second input voltage applied to the input terminal during a second signal sampling operation in another portion of the system clock period; this output terminal voltage is independent of the DC offset voltage. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates the general definition of the differential input signal DC offset. 
       FIG. 2  is a schematic diagram of a conventional single-ended input signal sampling circuit. 
       FIGS. 3   a-d  shows different configurations of the circuit of  FIG. 2 , to illustrate four operational phases of that circuit respectively. 
       FIG. 4  shows a single-ended input signal sampling circuit in accordance with an embodiment of the present invention. 
       FIGS. 5   a-d  show different configurations of the  FIG. 4  circuit to illustrate four operational phases thereof. 
       FIG. 6  is a schematic diagram of a differential sampling circuit embodying the present invention and derived from the circuit of  FIG. 4 , for generating the real differential input signal DC offset value. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Like reference numerals (with prime) are used in the drawings to designate identical (corresponding) parts. For the sake of illustration, the circuit  20  shown in  FIG. 2 , will be first modified to generate 0.5*(V 1 +V 2 ) instead of (V 1 +V 2 ) according to the present invention. 
   As apparent from  FIG. 4 , where a circuit embodying the invention is referenced  40 , the circuit of  FIG. 2  has been modified to add circuit block  41 . Circuit block  41  comprises one extra capacitor C 0  and two extra switches S 7  and S 8 . Capacitor C 0  is coupled to the opamp  21  negative input and to a third node  42 . Switch S 7  is coupled to second node  42  and ground. Switch S 8  is connected between the first and third nodes. 
   The operation of circuit  40  is still based upon four operational phases that will be now described with reference to  FIGS. 5   a - 5   d ; these phases are performed at each system clock cycle. 
   Let us consider  FIG. 5   a  which illustrates the first input signal sampling. It may still be assumed that Vin=V 1 . When V 1  is sampled, the capacitor C 0  is floating as switches S 7  and S 8  are open. Switches S 2 , S 4  and S 6  are open while switches S 1 , S 3  and S 5  are closed. After the first input signal sampling, we have:
 
 Vc   1 = V   1 − V off
 
 Vc   2 =− V off
 
Vout=Voff
 
The charge Q 1  stored into holding capacitor C 1  is equal to C 1 *(V 1 −Voff).
 
     FIG. 5   b  illustrates the configuration of circuit  40  during the first charge transfer when switches S 1 , S 3  and S 5  are opened and switches S 2  and S 4  are closed. During this phase, the charge variation DQ 1 , equal to C 1 *V 1 , is transferred into capacitor C 2 , so that:
   Vc   1 =− V off   Vc   2 =− V off+ V   1 * C   1 / C   2     V out= V   1 * C   1 / C   2   
   During the second input sampling, switches S 1 , S 3  and S 7  are closed and switches S 2  and S 4  are opened, circuit  40  then has the configuration depicted in  FIG. 5   c . Let us assume now that Vin has changed and equals V 2 . The capacitor C 0  is connected to ground because switch S 7  is closed, so that:
 
Vc 0 =−Voff
 
 Vc   1 = V   2 − V off
 
 Q   1 = C   1 *( V   2 − V off)
 
 Vc   2 =− V off+ V   1 * C   1 / C   2  ( Vc   2  remains unchanged)
 
 Vout=Voff
 
The charge Q 0  stored into capacitor C 0  is equal to −C 0 *Voff. This is an important feature of the present invention as will be discussed in more detail below. The charge stored in capacitor C 2  is equal to V 1 *C 1 −C 2 *Voff.
 
   Finally, during the second charge transfer (see  FIG. 5   d ), switches S 1 , S 3  and S 7  are opened while switches S 5 , S 6  and S 8  are closed. The capacitor C 0  is put in parallel with capacitor C 1  because switch S 8  is closed. Then:
 
Vc 2 =−Voff
 
 Q   2 =− V off* C   2 
 
 Vc   0 = Vc   1 =( Q   0 + Q   1 )/( C   0 + C   1 )=( C   1 * V   2 − V off( C   0 + C   1 ))/( C   0 + C   1 )= V   2 *  C   1 /( C   0 + C   1 )− V off
 
There is a charge transfer equal to the charge variation DQ 2  to capacitors C 0  and C 1 . Consequently, the voltages Vc 0  and Vc 1  change as follows:
 
 DQ   2 = C   1 * V   1 
 
 Vc   0 = Vc   1 =( DQ   2 + Q   0 + Q   1 )/( C   0 + C   1 )= C   1 * V   1 /( C   0 + C   1 )+ V   2 * C   1 /( C   0 + C   1 )− V off
 
 Vc   0 = Vc   1 =( V   1 + V   2 )/(1+ C   0 / C   1 )− V off, and finally
 
 V out= Vc   0 + V off=( V   1 + V   2 )/(1+ C   0 / C   1 ).
 
   Because Q 0 =−C 0 *Voff is present in the calculation of Vc 0 , the opamp  21  DC offset Voff does not appear in Vout. As a result, the signal output from circuit  40  is still independent of the opamp  21  offset, and is independent of the value of capacitor C 2  as well. It is noteworthy that, if C 0 =C 1 , i.e. if there is a perfect matching between these capacitors, then Vout=0.5*(V 1 +V 2 ); otherwise, the error on Vout is divided by two. For instance, if the mismatch between C 0  and C 1  is equal to about 2%, the error on Vout will be only about 1%. Only the ratio C 0 /C 1  of capacitor values must be as close as possible to 1. An improved differential sampling circuit embodying the present invention and derived from circuit  40 , for generating the real differential input signal DC offset, embodying the present invention, will be now described in detail. 
   Circuit  60 , shown in  FIG. 6 , may be viewed as a combination of two identical circuits  40  driven by first and second input signals Vin+ and Vin− respectively. However, in the embodiment of the present invention shown in  FIG. 6 , the two opamps have been merged in a single differential opamp referenced  61 , having thus two inputs and two outputs, for greater optimization. As apparent in  FIG. 6 , the upper switched-capacitor network  62 ′, which includes circuit block  41 ′, is connected between the positive input and the negative output. Likewise, the lower switched-capacitor network  62 ″, which includes block  41 ″, is connected between the negative input and the positive output. In the upper network, the extra devices are referenced C 0 ′, S 7 ′ and S 8 ′. In the lower network, the extra devices are referenced C 0 ″, S 7 ″ and S 8 ″. It is highly desirable that the corresponding components in the upper and lower networks be matched. The input signals applied to circuit  60 , forming the differential input signal pair, are labeled Vin+ and Vin−. Corresponding output signals are labeled Vout− and Vout+ respectively, defining a differential output signal ΔVout therebetween. By construction, this differential output signal ΔVout that is generated by circuit  60  is equal to the differential input signal DC offset ΔVoffset, as soon as the four operational phases have been completed. Vout−=0.5*[(Vin+1)+(Vin+2)], Vout+=0.5*[(Vin−1)+(Vin−2)] using the calculations and the notations given above for the improved circuit  40  described by reference to  FIGS. 4 and 5   a-d , so that ΔVout=(Vout−)−(Vout+)=ΔVoffset=0.5*[ΔV 1 +ΔV 2 ], wherein ΔV 1 =[(Vin+1)−(Vin−1)] and +ΔV 2 =[(Vin+2)+(Vin−2)], i.e. to the half sum of the two sampled differential input signal values. 
   Simulations have demonstrated that it is possible to measure the real value of the differential input signal DC offset and then to meet the SCSI-PI5 specifications. 
   The advantages of the invention are as follows: The differential input signal DC offset value is measured during only one system clock period. The DC offset is independent of the differential opamp  61  DC offset and the values of capacitors. Only the capacitor value ratio C 0 /C 1  should be equal to 1; a mismatch in this ratio of x % would lead to an error of x/2% in the measured DC offset value. 
   While the invention has been particularly described with respect to a preferred embodiment thereof, it should be understood by one skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.