Abstract:
A differential input receiver having normal and common mode impedance balanced inputs and a common mode rejection ratio approaching infinity is provided. The receiver includes a differential input operational amplifier across which is connected a fixed gain inverting amplifier. The fixed gain, inverting amplifier being connected in a feedback configuration across the differential input amplifier. Additionally, the values and ratios of the various resistors being selected to provide the balanced differential input and the substantially zero common mode gain of the receiver.

Description:
BACKGROUND OF THE INVENTION 
     A typical mode of transmitting information is by means of a balance wire pair. The wire pair is excited by a generator which applies a complementary, or out of phase, signal on each of the wires. These signals are referred to as differential mode signals. Telephone systems typically use this type of system. 
     Signals which are introduced electrostatically or magnetically into the two wire system produce a signal on each of the two wires which are in-phase with each other. These signals are referred to as common mode signals. 
     The problem in a receiving device is to distinguish between the differential mode signals and the undesirable common mode signals. The ability of a particular system component, such as an amplifier, to ignore the common mode interference is referred to as common mode rejection. Common mode rejection is defined as the ratio of the differential mode gain to the common mode gain. 
     In addition to providing a high common mode rejection ratio, a balanced input impedance to both the differential and common mode signals (i.e. an equivalent impedance to ground looking into each terminal of the differential input node) is desired. The classic single operational amplifier circuit presents this undesirable imbalance situation. Previous solutions to the problem include open loop non-feedback amplifiers and transformers both of which are expensive and, in the case of transformers, do not operate for low frequency and D.C. signals. Additionally, there ave been circuits having three or more operational amplifiers with voltage dividers. These circuits act to cancel the in-phase common mode interference within the accuracy to which the voltage dividers were matched. The differential, or normal, mode voltages were passed through to the next circuit stage. These circuits were commonly used as line receivers and in lower frequency ranges. 
     However these circuits have the problem that the input impedances to differential mode signals are not balanced at the two input terminals. Attempts to maintain the desired common mode rejection and balance the impedances at the two signal input terminals involved increasing the complexity of the circuit. In particular, at least three operational amplifiers were required to approach the desired performance objectives. 
     SUMMARY OF THE INVENTION 
     The present invention includes two operational amplifiers, a differential input amplifier and a fixed gain inverting amplifier which are interconnected to provide a balanced impedance differential input and a substantially zero common mode gain (substantially infinity common mode rejection ratio). 
     The differential input amplifier provides the forward signal path with the ratio of the resistance values having been selected to provide a substantially zero common mode gain. To balance the differential input impedances the fixed gain inverting amplifier is used to provide a feedback path. 
    
    
     DESCRIPTION OF THE DRAWING 
     FIG. 1 is a schematic diagram of the circuit of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to FIG. 1 there is shown a differential input amplifier 10 and a fixed gain inverting amplifier 22 connected thereacross in a feedback configuration. 
     Amplifier 10 includes an operational amplifier 12 with one end of resistors 14 and 16 connected to its inverting and non-inverting input terminals, respectively. The other end of these resistors provide the differential input terminals of amplifier 10, T 1  and T 2 , respectively. In addition, feedback resistor 18 is connected between the inverting input terminal and the positive output terminal of operational amplifier 12, and resistor 20 is connected between the non-inverting terminal of operational amplifier 12 and ground. The positive output terminal of operational amplifier 12 provides the output terminal T 3  of amplifier 10. Fixed gain inverting amplifier 22 includes an operational amplifier 24 with its non-inverting input terminal connected to ground. Amplifier 22 also includes a feedback resistor 26 connected between the inverting input terminal and the non-inverting output terminal of operational amplifier 24, an input resistor 28 having one end connected to the inverting input terminal of operational amplifier 24 and its other end providing the input terminal T 4  of amplifier 22, and a pair of output resistors 30 and 32 each having one end connected to the positive output terminal of operational amplifier 24. The other ends of each of resistors 30 and 32 provide the output terminals T 1  &#39; and T 2  &#39;, respectively, of amplifier 22. 
     Amplifiers 10 and 22 are interconnected with each other by connecting the output terminal T 3  of amplifier 10 with the input terminal T 4  of amplifier 22, and the output terminals T 1  &#39; and T 2  &#39; of amplifier 22 with terminals T 1  and T 2  of amplifier 10. Thus, in the overall system, the differential input terminals are T 1  and T 2 , and the output terminal is T 3 . 
     In order to have a balanced receiver for all signals and to have a common mode rejection ratio that approaches infinity, amplifier 22 has been connected in a feedback configuration across amplifier 10 and the values of each of the resistors are selected as discussed below to achieve those results. 
     The first step in the analysis is to look at amplifier 10 independent of amplifier 22. First we want to look at the gain from input terminals T 1  and T 2  to output terminal T 3 . These gains are: ##EQU1## 
     By definition the common mode gain of an operational circuit like amplifier 10 is: ##EQU2## and the differential, or normal, mode gain is: ##EQU3## Thus, by substituting the results of equations (1) and (2) into equations (3) and (4) we obtain: ##EQU4## where v in  =V T .sbsb.1 -V T .sbsb.2. 
     Additionally, the input impedances at T 1  and T 2   are: ##EQU5## Converting impedances Z 1  and Z 2  to admittances we have: ##EQU6## 
     Next, consider the effect of the interconnection of terminals T 1  and T 2  with T 1  &#39; and T 2  &#39;; the gain and common mode balance of amplifier 10 remain unchanged. Now, ##EQU7## 
     We can see that ##EQU8## 
     From these current values we see that the combined input admittances at T 1  and T 2  are: ##EQU9## where R 3  =R 4 . 
     The addition of R 3  and R 4  does not unbalance the common mode input impedance. 
     Next, we want to find R 3  /R 1  for ##EQU10## The equating of the input admittances of the system is necessary to achieve differential mode balance. Substituting into equation (17) we have: ##EQU11## for R 1  =R 2  and R 3  =R 4 . 
     In summary, the conditions on the circuit of FIG. 1 included in the above analysis for zero common mode gain and a balanced input impedance are: ##EQU12## 
     This circuit was built and its operation was successfully demonstrated with the following parameter values: 
     R 1  =R 2  =10K 
     n=4 
     nR 1  =nR 2  =40K 
     R 3  =R 4  =100K. 
     R 5  =R 6  =10K. 
     While the above analysis was conducted for a unity ratio of the values of R 1  to R 2 , R 3  to R 4  and R 5  to R 6 , it could have been done for other ratios of those values. 
     If the ratio of R 5  to R 6  was other than unity, the gain of amplifier 22 would be other than unity resulting in 
     
         v.sub.1 =-kv.sub.0                                         (24) 
    
     This would simply add the constant value of k to equations 12 through 23. With respect to the ratios of R 1  to R 2  and R 3  to R 4 , the unity ratio is selected to maintain the desired common mode balance. However, if a specific imbalance is desired, a general solution can be found through the variation of those ratios, but it is believed that such a circuit would be of limited practical value. 
     While there has been shown and described the preferred embodiment of the present invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from the invention in its broader aspects. Therefore, the appended claims are intended to cover all such modifications and changes that fall within the true spirit and scope of the invention.