Abstract:
An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before outputting at least one n-bit word from a memory device while ignoring those certain address bits before inputting at least one n-bit word into the plurality of memory cells. The apparatus may additionally comprise examining at least two of the least significant bits of a column address and wherein the reordering is responsive to the examining. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA 0 –CA 2  identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA 0 –CA 2  being “don&#39;t care” bits assumed to be 000.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of application Ser. No. 10/832,083 entitled “Memory Device Having Different Burst Order Addressing For Read and Write Operations”, filed 26 Apr. 2004 now U.S. Pat. No. 6,931,483, which is a continuation of U.S. application Ser. No. 09/905,004 entitled “Memory Device Having Different Burst Order Addressing For Read and Write Operations”, filed 13 Jul. 2001, now U.S. Pat. No. 6,779,074. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is directed to memory devices and, more particularly, to methods and circuits for reading information out of and writing information into the memory device. 
     2. Description of the Background 
     Computer designers are continually searching for faster memory devices that will permit the design of faster computers. A significant limitation on a computer&#39;s operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory devices such as dynamic random access memories (DRAMs), synchronous dynamic random access memories (SDRAMs), flash memories, etc. typically include a large number of memory cells arranged in one or more arrays, each array comprised of rows and columns. Each memory cell provides a location at which the processor can store and retrieve one bit of data, sometimes referred to as a memory bit or mbit. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data. 
       FIG. 1  shows, in part, a typical computer system architecture. A central processing unit (CPU) or processor  10  is connected to a processor bus  12 , which in turn is connected to a system or memory controller  14 . The memory controller  14  may be connected to an expansion bus  16 . The memory controller  14  serves as interface circuitry between the processor  10  and a memory device  18 . The processor  10  issues a command and an address which are received and translated by the memory controller  14 . The memory controller  14  applies the translated command signals on a plurality of command lines  20  and the translated address on a plurality of address lines  22  to the memory device  18 . These command signals are well known in the art and include, in the case of a DRAM, RAS (row address strobe), CAS (column address strobe), WE (write enable) and OE (output enable). A clock signal is also provided on CLK lines  24 . Corresponding to the processor-issued command and address, data is transferred between the controller  14  and the memory  18  via datapath lines  26 . 
     The memory  18  typically comprises a number of memory ranks  27 , a representative one of which is illustrated in  FIG. 2 . In this example, the memory rank  27  is configured for a 64-bit system, having eight 8-bit memory circuits  28 ( 0 )– 28 ( 7 ). The command signals RAS, CAS and WE are applied to all memory circuits  28 ( 0 )– 28 ( 7 ) in the rank  27 . In a memory  18  ( FIG. 1 ) having additional ranks, separate CS command signals would be provided for each rank. Hence, the command signal CS is often referred to as a rank-specific command signal. The address bus  22  is connected to all the memory circuits  28 ( 0 )– 28 ( 7 ) in the rank  27  and to all other memory circuits (not shown) in all other ranks (not shown) of the memory  18 . Hence, the address bus  22  is often referred to as globally connected. 
     A synchronous DRAM (SDRAM) is a memory device capable of sequentially accessing, by virtue of internal operations, a certain range of addresses at high speeds. In a typical SDRAM, a read/write rate of 100 Mbytes/sec or greater is possible. To achieve such speeds, the read/write of an SDRAM is performed in a burst mode. Burst mode is a mode of address access where data having the same row addresses are read or written continuously in blocks of 2, 4, or 8 bit words. In addition, the access for such words in the block is made by simply providing the start address of the block. Afterward, the remaining addresses are generated automatically in the SDRAM in accordance with its mode of operation: sequential or interleave. The mode of operation is determined by an address sequence from the CPU. Addresses for each burst address sequence method are generated, in the sequential mode, by addition of the burst start address and an output of an internal counter. In the interleave mode, the addresses are generated by an exclusive OR of the burst start address and an output of an internal counter. The same wrap mode is used for both read and write operations, with all column address bits used for both read and write operations. 
     As clock speeds increased above 200 MHz (i.e. RDRAM or SLDRAM), the core operation of the DRAM did not increase at the same rate. Therefore, the DRAMs completed the reads and writes on 4 or 8 words internally and then output the word sequentially onto the external bus. As entire groups of data words were being transferred, the least significant column addresses were no longer transmitted to the DRAM. 
     That solution works well for write data from a controller to the DRAM as it can be aligned to a cache fill. However, because a complete block of data words is transferred at the same time for reads, the most critical word is not always received first by the controller, which can add latency to the system. The need exists for a high clock rate DRAM memory supporting the block transfers of data words while delivering the most critical word first to the controller. Additional need exists for a communication protocol between the memory controller and the DRAM to support such a new feature. 
     SUMMARY 
     An addressing scheme to allow for two different types of access, one for reading and one for writing, to take place. A method comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device. In an exemplary embodiment, the method is for accessing a DRAM and is comprised of the following:
         using the values on the bank address inputs to select an array bank;   using the column address provided on inputs A 3 –Ai, where i is the most significant column address;   using the column address provided on inputs A 0 –A 2  to identify a burst order for a read access; and   ignoring the column address provided on inputs A 0 –A 2  during a write access.
 
Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA 0 –CA 2  identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA 0 –CA 2  being “don&#39;t care” bits assumed to be 000. Other implementation schemes are possible.
       

     An important feature that results from having a read access that differs from the write access is that reads are carried out in a manner so that the critical word is available to the memory controller such that an interleaved burst mode is supported. Writes, on the other hand, can be simplified based on a start sequential burst as the write data may be generated from data held in cache. The present invention supports improved latency for the system by providing the memory controller with the critical word first. Also, the system does not have to reorder the column address bits between read and write commands. Those, and other advantages and benefits, will be apparent from the Description of the Preferred Embodiments appearing hereinbelow. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For the present invention to be easily understood and readily practiced, the present invention will now be described, for purposes of illustration and not limitation, in conjunction with the following figures, wherein: 
         FIG. 1  is a functional block diagram of a computer system architecture as is known in the art; 
         FIG. 2  is a block diagram of a bank of memory circuits as is known in the art; 
         FIG. 3  is simplified block diagram of an architecture for implementing the burst read ordering of the present invention; 
         FIGS. 4A ,  4 B and  4 C illustrate addressing in a 512 megabit ×4 part, ×8 part, and ×16 part, respectively, to identify the wrap start location for the critical word; and 
         FIG. 5  is a simplified block diagram of a computer system in which the present invention may be used. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 3  illustrates a simplified block diagram of an architecture for a DRAM capable of implementing the burst read ordering of the present invention. The DRAM memory device  29  is comprised of a command/address input buffer  30  responsive to a command bus or command lines and an address bus or address lines. A command decoder and sequencer  32  and an address sequencer  34  are each responsive to the command/address input buffer  30 . 
     A bank address decoder  36  is responsive to the address sequencer  34  while bank control logic  38  is responsive to the bank address decoder  36 . A series of row latch/decoder/drivers  40  are responsive to the bank control logic  38  and the address sequencer  34 . One row latch/decoder/driver  40  is provided for each memory array  42 . Illustrated in  FIG. 3  are eight memory arrays labeled bank  0  through bank  7 . Accordingly, there are eight row latch/decoder/driver circuits  40  each responsive to one of bank  0  through bank  7 . 
     A column latch/decode circuit  44  is responsive to the address sequencer  34 . An I/O gating circuit  46  is responsive to the column latch/decode circuit  44  for controlling sense amplifiers within each of the memory arrays  42 . The command/address input buffer  30 , command decoder and sequencer  32 , address sequencer  34 , bank address decoder  36 , bank control logic  38 , the row latch/decoder/drivers  40 , column latch decode circuit  44  and I/O gating circuit  46  are considered to be a first plurality of peripheral devices responsive to the command bus and the address bus. The description of the forgoing elements as a first plurality of peripheral devices is intended to provide a description of the presently preferred embodiment, and is not intended to limit the scope of the invention to only the recited devices. Those of ordinary skill in the art will recognize that other combinations of devices may be used to implement the first plurality of peripheral devices. 
     The DRAM  29  may be accessed through a plurality of data pads  48  for either a write operation or a read operation. For a write operation, data on data pads  48  is received by receivers  50  and passed to input registers  52 . Write buffers  54  buffer the received data which is then input to a write latch and driver circuit  56  for input to the memory arrays  42  through the I/O gating circuit  46 . 
     Data which is to be read from the memory arrays  42  is output through the I/O gating circuit  46  to a read latch  58 . From the read latch  58 , the information is input to a multiplexer/reorder circuit  60  which outputs the data onto the data pads  48  through drivers  62 . The receivers  50 , input registers  52 , write buffers  54 , write latch and driver circuit  56 , I/O gating circuit  46 , read latch  58 , mux/reorder circuit  60  and drivers  62  comprise a second plurality of peripheral devices responsive to data. The description of the forgoing elements as a second plurality of peripheral devices is intended to provide a description of the presently preferred embodiment, and is not intended to limit the scope of the invention to only the recited devices. Those of ordinary skill in the art will recognize that other combinations of devices may be used to implement the second plurality of peripheral devices. 
     In general terms, the purpose of the reorder circuit  60  is to reorder a block of n-bit words output from the memory arrays  42  according to information in certain address bits. As seen in  FIG. 3 , there are eight, 8 bit words available at the input of mux/reorder circuit  60 . Mux/reorder circuit  60  also receives the three least significant bits of the column address (CA 0 –CA 2 ). Those three least significant bits identify the most critical word in the block of eight, 8 bit words to identify the word to be output first and where the wrap is to begin, i.e., the read begins with the critical word and if the critical word is any word other than the word at position  0 , the read wraps around from position  7  to position  0  to complete the read. 
     More particularly, and in accordance with a preferred embodiment of the invention, when a read command is received, the value on the bank address inputs BA 0  and BA 1  (not shown) selects one of the memory arrays  42 . Address information is then received which identifies a row or rows within each array  42 . The address provided on inputs A 3  through Ai (where i equals 8 for a ×16 part, 9 for an ×8 part and 10 for an ×4 part) selects the starting column location. Referring to  FIG. 3 , the values on inputs A 0  through Ai for a ×8 part are CA 3 –CA 9 . The information in the least significant bits (CA 0 –CA 2 ) is input to the mux/reorder circuit  60 . Those values are available at inputs A 0  through A 2 . That information identifies the most critical word which is output first by the mux/reorder circuit  60 .  FIGS. 4A ,  4 B, and  4 C illustrate the addressing for a 512 megabit ×4 part, ×8 part, and an ×16 part, respectively. 
     For a write operation, the bank is identified in the same manner as for a read operation. Similarly, the starting column address is identified in the same manner. However, during a write operation, the signals available at inputs A 0 –A 2  are ignored and assumed to be low. 
     The present invention is an addressing scheme that allows reads to incorporate interleaved burst mode so that the critical word is available to the controller while writes are simplified to a start sequential burst. In a preferred embodiment, access to the DRAM is always with a burst length of 8 bits. All write bursts are indexed to starting locations equal to CA 0 =0, CA 1 =0 and CA 2 =0. For reads, CA 0 , CA 1  and CA 2  specify the first data word read from the DRAM  29 . The remaining seven data words are read as shown in Table 1. 
     
       
         
               
             
               
               
               
             
           
               
                 TABLE 1 
               
             
             
               
                   
               
               
                 WRITE AND READ INTERLEAVE SEQUENCES 
               
             
          
           
               
                 Starting Column 
                 Data Word 
                 Data Word 
               
               
                 (CA0-CA1-CA2) 
                 Write Sequence 
                 Read Sequence 
               
               
                   
               
               
                 000 
                 0-1-2-3-4-5-6-7 
                 0-1-2-3-4-5-6-7 
               
               
                 001 
                 0-1-2-3-4-5-6-7 
                 1-0-3-2-5-4-7-6 
               
               
                 010 
                 0-1-2-3-4-5-6-7 
                 2-3-0-1-6-7-4-5 
               
               
                 011 
                 0-1-2-3-4-5-6-7 
                 3-2-1-0-7-6-5-4 
               
               
                 100 
                 0-1-2-3-4-5-6-7 
                 4-5-6-7-0-1-2-3 
               
               
                 101 
                 0-1-2-3-4-5-6-7 
                 5-4-7-6-1-0-3-2 
               
               
                 110 
                 0-1-2-3-4-5-6-7 
                 6-7-4-5-2-3-0-1 
               
               
                 111 
                 0-1-2-3-4-5-6-7 
                 7-6-5-4-3-2-1-0 
               
               
                   
               
             
          
         
       
     
       FIG. 5  is a block diagram of one example of a computer system  110  in which the present invention may be implemented. The computer system  110  includes a processor  112 , a memory subsystem  114 , and an expansion bus controller  116 . The memory subsystem  114  and the expansion bus controller  116  are coupled to the processor  112  via a local bus  118 . The expansion bus controller  116  is also coupled to at least one expansion bus  120 , to which various peripheral devices  121 – 123  such as mass storage devices, keyboard, mouse, graphic adapters, and multimedia adapters may be attached. Processor  112  and memory subsystem  114  may be integrated on a single chip. 
     The memory subsystem  114  includes a memory controller  124  which is coupled to a plurality of memory modules  125 ,  126  via a plurality of signal lines  129 ,  130 ,  129   a,    130   a,    129   b,    120   b,    129   c  and  130   c.  The plurality of data signal lines  129 ,  129   a,    129   b,    129   c  are used by the memory controller  124  and the memory modules  125 ,  126  to exchange data DATA. Addresses ADDR are signaled over a plurality of address signal lines  132 , clock signals CLK are applied on a clock line  133 , and commands CMD are signaled over a plurality of command signal lines  134 . The memory modules  125 ,  126  include a plurality of memory devices  136 – 139 ,  136 ′– 139 ′ and a register  141 ,  141 ′, respectively. Each memory device  136 – 139 ,  136 ′– 139 ′ may be a high speed synchronous memory device. Although only two memory modules  125 ,  126  and associated signal lines  129 – 129   c,    130 – 130   c  are shown in  FIG. 5 , it should be noted that any number of memory modules can be used. 
     The plurality of signal lines  129 – 129   c,    130  – 130   c,    132 ,  133 ,  134  which couple the memory modules  125 ,  126  to the memory controller  124  are known as the memory bus  143 . The memory bus  143  may have additional signal lines which are well known in the art, for example chip select lines, which are not illustrated for simplicity. Each column of memory devices  136 – 139 ,  136 ′– 139 ′ spanning the memory bus  143  is known as a rank of memory. Generally, single side memory modules, such as the ones illustrated in  FIG. 5 , contain a single rank of memory. However, double sided memory modules containing two ranks of memory may also be used. 
     Read data is output serially synchronized to the clock signal CLK, which is driven across a plurality of clock signal lines,  130 ,  130   a,    130   b,    130   c.  Write data is input serially synchronized to the clock signal CLK, which is driven across the plurality of clock signal lines  130 ,  130   a,    130   b,    130   c  by the memory controller  124 . Commands and addresses are also clocked using the clock signal CLK which is driven by the memory controller  124  across the registers  141 ,  141 ′ of the memory modules  125 ,  126 , respectively, to a terminator  148 . The command, address, and clock signal lines  134 ,  132 ,  133 , respectively, are directly coupled to the registers  141 ,  141 ′ of the memory modules  125 ,  126 , respectively. The registers  141 ,  141 ′ buffer those signals before they are distributed to the memory devices  136 – 139 ,  136 ′– 139 ′ of the memory modules  125 ,  126 , respectively. 
     While the present invention has been described in conjunction with preferred embodiments thereof, those of ordinary skill in the art will recognize that many modifications and variations are possible. Such modifications and variations fall within the scope of the present invention which is limited only by the following claims.