Abstract:
A multi-level converter includes first and second DC buses, a plurality of transistors coupled in series between the first and second DC buses and a clamp circuit configured to clamp a node joining a first transistor and a second transistor of the plurality of transistors. The converter further includes a bias circuit coupled to the clamped node, which may reduce or prevent voltage stress on the transistors. Related methods of operation are also described.

Description:
BACKGROUND 
       [0001]    The inventive subject matter relates to power conversion circuits and methods and, more particularly, to inverter apparatus and methods. 
         [0002]    Rectifier and inverter circuits are used in uninterruptible power supply (UPS) systems, motor drives and other power apparatus. Some inverters and rectifiers have a multilevel architecture that uses multiple commutation states. Various multilevel inverter and rectifier circuits are described, for example, in U.S. Pat. No. 5,361,196 to Tamamachi et al., U.S. Pat. No. 6,031,738 to Lipo et al., U.S. Pat. No. 6,795,323 to Tanaka et al., U.S. Pat. No. 6,838,925 to Nielsen, U.S. Pat. No. 7,145,268 to Edwards et al. and U.S. Pat. No. 7,573,732 to Teichmann et al. 
       SUMMARY 
       [0003]    Some embodiments of the inventive subject matter provide a multi-level converter including first and second DC buses, a plurality of transistors coupled in series between the first and second DC buses and a clamp circuit configured to clamp a node joining a first transistor and a second transistor of the plurality of transistors. The converter further includes a bias circuit coupled to the clamped node. 
         [0004]    The second transistor may be coupled between the clamped node and an AC node. The converter may be configured to operate as a rectifier and the second transistor may be coupled between the clamped node and a phase input. In further embodiments, the converter may be configured to operate as an inverter and the second transistor may be coupled between the clamped node and a phase output. 
         [0005]    In further embodiments, the bias circuit may be configured to couple the clamped node to the first DC bus and the first and second transistors may be coupled between the second DC bus and an AC node. The bias circuit may include a resistor coupling the clamped node to the first DC bus. The bias circuit may be further configured to discharge a capacitance coupled to the first DC bus using the clamp circuit. 
         [0006]    Further embodiments provide a multi-level converter including first and second DC buses, an AC node, a neutral node, first and second transistors coupled in series between the first DC bus and the AC node, a diode coupled between the neutral node and a neutral clamped node joining the first and second transistors, and a resistor coupling the neutral clamped node to the second DC bus. The converter may further include third and fourth transistors coupled in series between the second DC bus and the AC node, a second diode coupled between the neutral node and a second neutral clamped node joining the third and fourth transistors, and a second resistor coupled between the second neutral clamped node and the first DC bus. 
         [0007]    Still further embodiments provide methods of operating a multi-level converter including biasing a clamped node joining a first transistor and a second transistor of the converter to limit a voltage developed across the second transistor. The second transistor may be coupled between the clamped node and an AC node of the converter. Biasing the clamped node may include coupling the clamped node to a DC bus of the converter using, for example, a resistor, 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a schematic diagram illustrating a converter according to some embodiments of the inventive subject matter. 
           [0009]      FIG. 2  is a schematic diagram illustrating a converter according to further embodiments. 
           [0010]    FIG,  3  is a schematic diagram illustrating an uninterruptible power supply (UPS) including an inverter according to some embodiments. 
           [0011]      FIG. 4  is a schematic diagram illustrating a UPS including a rectifier according to some embodiments. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0012]    Specific exemplary embodiments of the inventive subject matter now will be described with reference to the accompanying drawings. This inventive subject matter may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive subject matter to those skilled in the art. In the drawings, like numbers refer to like elements. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0013]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive subject matter. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms “includes,” “comprises,” “including” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0014]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0015]      FIG. 1  illustrates a multi-level converter  100  according to some embodiments. The converter  100  may be utilized as an inverter and/or rectifier, and includes a plurality of transistors, here shown as first, second, third and fourth insulated gate bipolar transistors (IGBTs) Q 1 , Q 2 , Q 3 , Q 4 . The first and second transistors Q 1 , Q 2  are coupled between a first DC bus  115   a  and an AC node  114  and the third and fourth transistors Q 3 , Q 4  are coupled between a second DC bus  115   b  and the AC node  114 . The AC node  114  may be coupled to an external source and/or load via an inductor L. The transistors Q 1 , Q 2 , Q 3 , Q 4  may be controlled by a control circuit  118 . Anti-parallel diodes paired with the transistors Q 1 , Q 2 , Q 2 , Q 4  may be integrated with the transistors or may be separate components. Nodes  112   a ,  112   b  between first and second transistors Q 1 , Q 2  and third and fourth transistors Q 3 , Q 4 , respectively, are neutral clamped using respective diodes D 1 , D 2  coupled between the nodes  112   a ,  112   b  and a neutral node N. The neutral clamping supports multilevel operation. 
         [0016]    As further shown, the converter  100  includes bias circuits  116   a ,  116   b  coupled to the neutral clamped nodes  112   a ,  112   b . The bias circuits  116   a ,  116   b  are configured to bias the neutral clamped nodes  112   a ,  112   b  to a predetermined voltage when the first and fourth transistors Q 1 , Q 4  are off. As explained in greater detail below, the bias circuits  116   a ,  116   b  may serve to limit voltage developed across the inner transistors Q 2 , Q 3  under certain conditions. 
         [0017]      FIG. 2  illustrates a multilevel converter  200  according to further embodiments, wherein clamped node biasing is provided by resistors coupled to DC buses. The converter  200  includes first and second DC buses  115   a ,  115   b , first, second, third and fourth transistors Q 1 , Q 2 , Q 3 , Q 4 , neutral clamping diodes D 1 , D 2 , inductor L, AC node  114  and first and second neutral clamping nodes  112   a ,  112   b  as described above with reference to  FIG. 1 . A first bias resistor R 1  is coupled between the first neutral clamped node  112   a  and the second DC bus  115   b . A second bias resistor R 2  is coupled between the second neutral clamped node  112   b  and the first DC bus  115   a , The bias provided by the resistors R 1 , R 2  can prevent damaging voltage levels from developing across the inner second and third transistors Q 2 , Q 3  if, for example, a voltage surge occurs in a line coupled to the AC node  114  while the converter  200  is in an inactive state with all of the transistors Q 1 , Q 2 , Q 3 , Q 4  off. The resistors R 1 , R 2  may have resistance values sufficient to provide bias to protect the inner second and third transistors Q 2 , Q 3 , without supporting unduly large currents between the buses  115   a ,  115   b  and the neutral N. The first and second bias resistors R 1 , R 2  may also support discharging (bleeding) of capacitors C 1 , C 2  coupled to the first and second DC buses  115   a ,  115   b  via the neutral clamping diodes D 1 , D 2  to de-energize the buses  115   a ,  115   b  for maintenance and other purposes. 
         [0018]    Converter circuits according to some embodiments may be advantageously used in UPS applications. For example,  FIG. 3  illustrates a UPS  300  including a rectifier  310 , which has phase inputs  311   a ,  311   b ,  311   c  configured to be coupled to an AC source, such as a utility or generator. An output of the rectifier  310  is coupled to an inverter circuit  330  by first and second DC buses  315   a ,  315   b . The inverter circuit has phase outputs  331   a ,  331   b ,  331   c  configured to be coupled to a load. As further shown, an auxiliary power source  420 , such as a battery or battery converter configured to be coupled to a battery, may also be coupled to the first and second DC buses  315   a ,  315   b . Storage capacitors C 1 , C 2  are coupled between respective ones of the first and second DC buses  315   a ,  315   b  and a neutral N. 
         [0019]    As shown, the rectifier  310  may be a multi-level rectifier having phase inputs  311   a ,  311   b ,  311   c  and including input inductors La, Lb, Lc, upper transistors Q 1   a , Q 2   a , Q 1   b , Q 2   b , Q 1   c , Q 2   c  coupled between the first DC bus  315   a  and the neutral N, and lower transistors Q 3   a , Q 4   a , Q 3   b , Q 4   b , Q 3   c , Q 4   c  coupled between the second DC bus  315   b  and the neutral N. Diodes D 1   a , D 2   a , D 1   b , D 2   b , D 1   c , D 2   c  provide neutral clamping of respective nodes  312  between respective ones of the upper and lower transistor pairs. Resistors R 1   a , R 2   a , R 1   b , R 2   b , R 1   c , R 2   c  bias the neutral clamped nodes  312  and provide current paths for discharging the first and second DC buses  315   a ,  315   b . The UPS  300  may also include control circuitry (not shown for clarity of illustration) for driving the transistors Q 1   a , Q 2   a , Q 1   b , Q 2   b , Q 1   c , Q 2   c , Q 3   a , Q 4   a , Q 3   b , Q 4   b , Q 3   c , Q 4   c , as well as additional circuitry, such as bypass circuitry. 
         [0020]      FIG. 4  illustrates a UPS  400  including a rectifier  410  having phase inputs  411   a ,  411   b ,  411   c  configured to be coupled to an AC source, such as a utility or generator. An output of the rectifier  410  is coupled to an inverter circuit  430  by first and second DC buses  415   a ,  415   b . The inverter circuit has phase outputs  431   a ,  431   b ,  431   c  configured to be coupled to a load. As further shown, an auxiliary power source  420  may also be coupled to the first and second DC buses  415   a ,  415   b . Storage capacitors C 1 , C 2  are coupled between respective ones of the first and second DC buses  415   a ,  415   b  to a neutral N. 
         [0021]    The inverter  430  may be a multi-level inverter including output inductors La, Lb, Lc, upper transistors Q 1   a , Q 2   a , Q 1   b , Q 2   b , Q 1   c , Q 2   c  coupled between the first DC bus  415   a  and the neutral N, and lower transistors Q 3   a , Q 4   a , Q 3   b , Q 4   b , Q 3   c , Q 4   c  coupled between the second DC bus  415   b  and the neutral N. Diodes D 1   a , D 2   a , D 1   b , D 2   b , D 1   c , D 2   c  provide neutral clamping of respective nodes  412  between respective ones of the upper and lower transistor pairs. Resistors R 1   a , R 2   a , R 1   b , R 2   b , R 1   c , R 2   c  bias the neutral clamped nodes  412  and provide discharge paths for the first and second DC buses  415   a ,  415   b . The UPS  400  may also include control circuitry for driving the transistors Q 1   a , Q 2   a , Q 1   b , Q 2   b , Q 1   c , Q 2   c , Q 3   a , Q 4   a , Q 3   b , Q 4   b , Q 3   c , Q 4   c  (not shown for clarity of illustration), along with other circuitry, such as bypass circuitry. 
         [0022]    It will be appreciated that converters according to some embodiments of the inventive subject matter may be used in any of a number of different applications, such as rectifiers, inverters, motor drives and the like. Further embodiments may use bias circuits other than the resistor connections described above with reference to  FIGS. 2-4 , such as bias circuits that use other passive networks and/or active devices to provide similar biasing. It will further appreciated that, although the illustrated example embodiments include three-level converters with neutral clamped nodes, some embodiments of the inventive subject matter may provide other types of multi-level converters, such as converters with more than four transistors and/or more than three states, having nodes that are clamped in other ways and biased using bias circuitry similar to that described above, 
         [0023]    In the drawings and specification, there have been disclosed exemplary embodiments of the inventive subject matter. Although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the inventive subject matter being defined by the following claims.