Abstract:
An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for reducing power consumption. 
       DESCRIPTION OF RELATED ARTS 
       [0002]    Typical semiconductor memory devices receive a read command or a write command after an active command is input and operations caused by the active command are completed. Hereinafter, a delay between an input timing of the active command and an input timing of the read command or the write command is referred to as tRCD. An address input with the read command or the write command is also input after tRCD. 
         [0003]    However, it is possible for a semiconductor memory device including DDR2 SDRAM to set an input timing of the read command or the write command at any timing even before tRCD. The semiconductor memory device holds the read command or the write command input before tRCD for a predetermined time and generates an internal read command or an internal write command respectively corresponding to the read command and the write command after tRCD passes from the timing of the active command. The predetermined time between an input timing of the read command or the write command and a generation timing of the internal read command or the internal write command is referred as an additive latency (AL). Further, an address input with the read command or the write command is also held for the additive latency (AL) and, then, an internal address corresponding to the address is generated. 
         [0004]    For example, in order to perform a read operation, DDR2 SDRAM generates an internal read address and an internal read command after the additive latency passes from the input timing of a read command. After a predetermined time from a generation time of the internal read command and the internal read address, DDR2 SDRAM starts to read valid data. The predetermined time between the generation timing of the internal read command and the internal address and a start timing of the read operation is referred to a column address strobe (CAS) latency (CL). DDR2 SDRAM starts to perform the read operation after the additive latency (AL) and the CAS latency (CL) from the input timing of the read command and the address. A value obtained by adding the CAS latency (CL) to the additive latency (AL) is referred to a read latency (RL). 
         [0005]    In the case of a write operation, DDR2 SDRAM generates an internal write command and an internal write address and performs the write operation after a write latency (WL) from an input timing of a write command and an address. The write latency (WL) is less by one clock than the read latency (RL). That is, WL=RL−1=(AL+CL)−1. 
       SUMMARY OF THE INVENTION 
       [0006]    Embodiments of the present invention are directed to an internal signal generator for reducing current consumption. 
         [0007]    In accordance with an aspect of the present invention, there is provided an internal signal generator for use in a semiconductor memory device including an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay address to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a predetermined latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address. 
         [0008]    In accordance with another aspect of the present invention, there is provided a semiconductor memory device including an internal signal generation unit and a drive clock generation unit. The internal signal generation unit generates a plurality of delay signals by delaying an external signal for a predetermined latency shorter than a latency set by the semiconductor memory device in synchronism with a drive signal and selects one of the delay signal to thereby output an internal signal. The drive clock generation unit outputs an internal clock as the drive signal in response to the latency set by the semiconductor memory device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0009]    The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which: 
           [0010]      FIG. 1  is a block diagram describing an internal address generator of a semiconductor memory device in accordance with an embodiment of the present invention; 
           [0011]      FIG. 2A  is a schematic circuit diagram depicting a additive clock generator shown in  FIG. 1 ; 
           [0012]      FIG. 2B  is a schematic circuit diagram showing a latch unit  22  shown in  FIG. 1 ; 
           [0013]      FIG. 2C  is a schematic circuit diagram describing a first flip-flop included in a read address generation unit shown in  FIG. 1 ; 
           [0014]      FIG. 2D  is a schematic circuit diagram describing a first selection unit shown in  FIG. 1 ; 
           [0015]      FIG. 3  is a timing diagram demonstrating a read operation of the internal address generator shown in  FIG. 1 ; 
           [0016]      FIG. 4  is a timing diagram demonstrating a write operation of the internal address generator shown in  FIG. 1 ; 
           [0017]      FIG. 5  is a block diagram showing an internal address generator in accordance with another embodiment of the present invention; 
           [0018]      FIG. 6  is a schematic circuit diagram depicting a flip-flop in a first flip-flop unit shown in  FIG. 5 ; 
           [0019]      FIG. 7  is a block diagram describing an internal address generator in accordance with still another embodiment of the present invention; and 
           [0020]      FIG. 8  is a schematic circuit diagram depicting the flip-flop shown in  FIG. 7 . 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0021]    Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings. 
         [0022]      FIG. 1  is a block diagram describing an internal address generator of a semiconductor memory device in accordance with an embodiment of the present invention. 
         [0023]    The internal address generator includes a drive clock generation unit  10 , a read address generation unit  20 , a write address generation unit  30 , and an output unit  40 . 
         [0024]    The drive clock generation unit  10  outputs an additive drive clock AL_CLK or a CAS drive clock CL_CLK based on an internal clock CLK respectively in response to a zero additive latency signal AL&lt;0&gt; or a write state signal WTS. The zero additive latency signal AL&lt;0&gt; is a first bit of an additive latency signal AL&lt;0:N&gt; and is active when an additive latency of the semiconductor memory device is set to zero clocks. The write state signal WTS is activated during a write operation. The read address generation unit  20  delays an external address EXT_ADDR in response to the additive drive clock AL_CLK and outputs an internal read address RD_IADD corresponding to the additive latency of the semiconductor memory device. The write address generation unit  30  delays the internal read address RD_IADD in response to the CAS drive clock CL_CLK and outputs an internal write address WT_IADD corresponding to a CAS latency of the semiconductor memory device. The output unit  40  selects one of the internal read address RD_IADD and the internal write address WT_IADD in response to the write state signal WTS to thereby output an internal column address CA. 
         [0025]    The drive clock generation unit  10  includes an additive clock generator  12  and a CAS clock generator  14 . The additive clock generator  12  outputs the additive drive clock AL_CLK based on the internal clock CLK when the zero additive latency signal AL&lt;0&gt; is inactive. The CAS clock generator  14  outputs the CAS drive clock CL_CLK based on the internal clock CLK when the write state signal WTS is active. 
         [0026]    The read address generation unit  20  includes a latch unit  22 , a first flip-flop unit  24 , and a first selection unit  26 . The latch unit  22  latches the external address EXT_ADDR in response to a read/write flag RDWT. The read/write flag RDWT is active when the read command RD or the write command WT is input. The first flip-flop unit  24  receives an output of the latch unit  22  and delays the output in response to the additive drive clock AL_CLK to thereby output a plurality of delay addresses B&lt;1:N&gt;. The first selection unit  26  selects one of the delay addresses B&lt;0:N&gt; in response to activated one of the additive latency signal AL corresponding to the additive latency AL&lt;0:N&gt; of the semiconductor memory device and outputs the internal read address RD_IADD. The first delay address B&lt;0&gt; has the same phase with the external address EXT_ADDR. In other words, the external address EXT_ADDR is input as the first delay address B&lt;0&gt; to the first selection unit  16 . 
         [0027]    The first flip-flop unit  24  includes a plurality of flip-flops  24   a  to  24   e  serially connected to one another and a latch unit  24   f . The first flip-flop  24   a  receives the output of the latch unit  22 . The latch unit  24   f  is connected to the last flip-flop  24   e.    
         [0028]    The write address generation unit  30  includes a second flip-flop unit  32  and a second selection unit  34 . The second flip-flop unit  32  receives the internal read address RD_IADD and delays the internal read address RD_IADD in response to the CAS drive clock CL_CLK to thereby output a plurality of CAS delay addresses. The second selection unit  34  selects one of the CAS delay addresses in response to activated one of CAS latency signals CL corresponding to the CAS latency of the semiconductor memory device. 
         [0029]    The second flip-flop unit  32  includes a plurality of flip-flops  32   a  to  32   e  and a latch unit  32   f . The first flip-flop  32   a  receives the internal read address RD_IADD. The latch unit  32   f  is connected to the last flip-flop  32   e.    
         [0030]    The output unit  40  has similar circuitry to the first and the second selection blocks  26  and  34  except for receiving the internal read address RD_IADD and the internal write address WT_IADD and outputting the internal column address CA in response to the write state signal WTS. 
         [0031]      FIG. 2A  is a schematic circuit diagram depicting the additive clock generator  12  shown in  FIG. 1 . 
         [0032]    The additive clock generator  12  includes a first inverter I 1  and a first AND gate AD 1 . The first inverter I 1  inverts the zero additive latency signal AL&lt;0&gt;. The first AND gate AD 1  logically combines an output of the first inverter I 1  and the internal clock CLK to thereby output the additive drive clock AL_CLK. The additive drive clock AL_CLK is active when the active latency of the semiconductor memory device is set to more than zero clocks. The CAS clock generator  14  has similar circuitry to that of the additive clock generator  12  except for receiving the write state signal WTS and the additive drive clock AL_CLK instead of the zero additive latency signal AL&lt;0&gt; and the internal clock CLK. 
         [0033]      FIG. 2B  is a schematic circuit diagram showing the latch unit  22  shown in  FIG. 1 . 
         [0034]    The latch unit  22  includes a first transmission gate TG 1  and a latch  22   a . The first transmission gate TG 1  transmits the external address EXT_ADDR when the read/write flag RDWT is active as a logic high level. The read/write flag RDWT is active when the read or the write command is input. The latch  22   a  latches an output of the first transmission gate TG 1 . The latch unit  22  transmits the external address EXT_ADDR in response to an activation of the read/write flag RDWT. The latch units  24   f  and  32   f  respectively included in the first and the second flip-flop units  24  and  32  have similar circuitry to that of the latch unit  22 . 
         [0035]      FIG. 2C  is a schematic circuit diagram describing the first flip-flop  24   a  included in the read address generation unit  20  shown in  FIG. 1 . 
         [0036]    The first flip-flop  24   a  includes two transmission gates TG 2  and TG 3  and two latches  24   a _ 1  and  24   a _ 2 . The second transmission gate TG 2  transmits data input through an input terminal D in response to the additive drive clock AL_CLK of a logic low level. The first latch  24   a _ 1  inverts and latches an output of the second transmission gate TG 2  and outputs a first output /Q. The third transmission gate TG 3  transmits the first output /Q in response to the additive drive clock AL_CLK of a logic high level. The second latch  24   a _ 2  inverts and latches an output of the third transmission gate TG 3  and outputs a second output Q. That is, the first flip-flop  24   a  outputs the first output /Q synchronism with a falling edge of the additive drive clock AL_CLK and the second output Q synchronized with a rising edge of the additive drive clock AL_CLK. The other flip-flops included in the first flip-flop unit  24  and the second flip-flop unit  32  have similar circuitry to that of first flip-flop  24   a.    
         [0037]      FIG. 2D  is a schematic circuit diagram describing the first selection unit  26  shown in  FIG. 1 . 
         [0038]    The first selection unit  26  includes a plurality of transmission gates TG 4  to TG 8 . Each of the transmission gates TG 4  to TG 8  transmits corresponding delay addresses B&lt;0:N&gt; in response to corresponding additive latency signal AL&lt;0:N&gt;. For example, when the second additive latency signal AL&lt;1&gt; is activated as a logic high level, the fifth transmission gate TG 5  transmits the first output /Q of the first flip-flop  24   a , i.e., the second delay address B&lt;1&gt;, to thereby output the internal read address RD_IADD. The second selection unit  34  and the output unit  40  have similar circuitry to that of the first selection unit  32 . 
         [0039]      FIG. 3  is a timing diagram demonstrating a read operation of the internal address generator shown in  FIG. 1 . 
         [0040]    It is presumed that a burst length, denoting the number of data output by one read command RD, is four; the additive latency AL is four clocks; and the CAS latency is two clocks. 
         [0041]    First, when a read command RD and an address ADDR are input, an external read signal EXT_RD and the external address EXT_ADDR are activated in synchronism with the internal clock CLK. Because the additive latency AL is not zero, the drive clock generation unit  10  outputs the additive drive clock AL_CLK based on the internal clock CLK. The write state signal WTS is inactive because the read command RD is input. Therefore, the drive clock generation unit  10  does not output the CAS drive clock CL_CLK. 
         [0042]    The latch unit  22  transmits the external address EXT_ADDR in response to the read/write flag RDWT activated by the read command RD. The first flip-flop unit  24  outputs the delay addresses B&lt;0:N&gt; serially activated in response to the additive drive clock AL_CLK. The first selection unit  26  selects the fifth delay address B&lt;4&gt; in response to the fifth additive latency signals AL&lt;4&gt; corresponding to the additive latency AL of the semiconductor memory device, i.e., 4 clocks, and outputs the internal read address RD_IADD. The output unit  40  outputs the internal column address CA based on the internal read address RD_IADD. 
         [0043]    That is, the internal column address CA is activated after 4 clocks corresponding to the additive latency AL of the semiconductor memory device is passed from an input timing of the external address EXT_ADDR. An internal read command IRD is activated after 4 clocks corresponding to the selected additive latency signal, i.e., AL&lt;4&gt;, is passed from an input timing of the external read signal EXT_RD. 
         [0044]    The CAS clock generator  14  in the drive clock generation unit  10  does not activate the CAS drive clock CL_CLK. Therefore, the second flip-flop unit  32  in the write address generation unit  30  is not activated and, therefore, the internal write address WT_IADD is not activated. 
         [0045]    After two clocks corresponding to the CAS latency AL of the semiconductor memory device is passed from an activation timing of the internal read command IRD is passed, four bit address D 0  to D 3  are output. 
         [0046]      FIG. 4  is a timing diagram demonstrating a write operation of the internal address generator shown in  FIG. 1 . 
         [0047]    As in the case shown in  FIG. 3 , it is presumed that a burst length, denoting the number of data bits output by one read command RD, is four; the additive latency AL is four clocks; and the CAS latency is two clocks. 
         [0048]    First, when a write command WT and an address are input, an external write signal EXT_WT and the external address EXT_ADDR are activated. Because the additive latency AL is not zero, the drive clock generation unit  10  outputs the additive drive clock AL_CLK based on the internal clock CLK. Further, the drive clock generation unit  10  outputs the CAS drive clock CL_CLK based on the additive drive clock AL_CLK in response to an activation of the write state signal WTS. 
         [0049]    The latch unit  22  transmits the external address EXT_ADDR in response to the read/write flag RDWT activated by the write command WT. The first flip-flop unit  24  outputs the delay addresses B&lt;0:N&gt; serially activated in response to the additive drive clock AL_CLK. The first selection unit  26  selects the fifth delay address B&lt;4&gt; in response to the fifth additive latency signals AL&lt;4&gt; corresponding to the additive latency AL of the semiconductor memory device, i.e., 4 clocks, and outputs the internal read address RD_IADD. 
         [0050]    The second flip-flop unit  32  in the write address generation unit  30  outputs the plurality of CAS delay addresses serially activated in response to the CAS drive clock CL_CLK. The second selection unit  34  selects one of the CAS delay addresses corresponding to the second CAS latency CL&lt;2&gt; and outputs the internal write address WT_IADD. The output unit  40  outputs the internal column address CA based on the internal write address WT_IADD in response to the write state signal WTS. 
         [0051]    That is, the internal column address CA is activated after 5 clocks corresponding to a write latency WL of the semiconductor memory device is passed from an input timing of the external address EXT_ADDR. Further, an internal write command IWT is activated after 5 clocks are passed from an input timing of the external write signal EXT_WT. The data D 0  to D 3  starts to be input at an activation timing of the internal write command IWT. 
         [0052]    The internal address generator shown in  FIG. 1  drives all flip-flops in the first and the second flip-flop units  24  and  32  without reference to the additive latency AL and the CAS latency CL. For example, when the additive latency AL is four clocks and the CAS latency CL is two clocks, the internal address generator uses four flop-flops in the first flip-flop unit  24 , i.e., the first to the fourth flip-flops, in case of the read operation. In the case of the write operation, the internal address generator uses five flip-flops, i.e., the first to the fourth flip-flops in the first flip-flop unit  24  and the first flip-flop in the second flip-flop unit  32 . However, the internal address generator drives all flip-flops including those not being used. Therefore, the internal address generator is wasteful of power consumption. 
         [0053]      FIG. 5  is a block diagram showing an internal address generator in accordance with an embodiment of the present invention. 
         [0054]    The internal address generator includes a drive clock generation unit  100 , a read address generation unit  200 , a write address generation unit  300 , and an output unit  400 . 
         [0055]    The drive clock generation unit  100  outputs an additive drive clock AL_CLK or a CAS drive clock CL_CLK based on an internal clock CLK respectively in response to a zero additive latency signal AL&lt;0&gt; and a write state signal WTS. The read address generation unit  200  delays an external address EXT_ADDR in response to an additive latency signal AL&lt;1:N−1&gt; in synchronism with the additive drive clock AL_CLK and outputs an internal read address RD_IADD corresponding to the additive latency of the semiconductor memory device. The write address generation unit  300  delays the internal read address RD_IADD in response to a CAS latency signal CL&lt;2:N−1&gt; in synchronism with the CAS drive clock CL_CLK and outputs an internal write address WT_IADD corresponding to a CAS latency of the semiconductor memory device. The output unit  400  selects one of the internal read address RD_IADD and the internal write address WT_IADD in response to the write state signal WTS and outputs an internal column address CA. 
         [0056]    The drive clock generation unit  100  includes an additive clock generator and a CAS clock generator. The additive clock generator outputs the additive drive clock AL_CLK based on the internal clock CLK when the zero additive latency signal AL&lt;0&gt; is inactive. The CAS clock generator outputs the CAS drive clock CL_CLK based on the internal clock CLK when the write state signal WTS is active. 
         [0057]    The read address generation unit  200  includes a latch unit  220 , a first flip-flop unit  240 , and a first selection unit  260 . The latch unit  220  latches the external address EXT_ADDR in response to a read/write flag RDWT. The first flip-flop unit  240  receives an output of the latch unit  220  and delays the output in response to the additive drive clock AL_CLK and to thereby output a plurality of delay addresses. The first selection unit  260  selects one of the delay addresses in response to active one of the additive latency signal AL&lt;0:N&gt; and outputs the internal read address RD_IADD. 
         [0058]    The first flip-flop unit  240  includes a plurality of flip-flops, e.g.,  241 , serially connected one another and a latch unit  246 . The first flip-flop  241  receives the output of the latch unit  22 . Each flip-flop delays an input signal input through an input terminal D and outputs a second output through its second output terminal /Q and a first output through its first output terminal Q. The second output /Q is output as the delay address. The latch unit  246  receives the first output of the last flip-flop  245  and outputs the last delay address B&lt;N&gt;. 
         [0059]    The write address generation unit  300  includes a second flip-flop unit  320  and a second selection unit  340 . The second flip-flop unit  320  receives the internal read address RD_IADD and delays the internal read address RD_IADD in response to the CAS drive clock CL_CLK to thereby output a plurality of CAS delay addresses. The second selection unit  340  selects one of the CAS delay addresses in response to activated one of CAS latency signals CL&lt;2:N&gt;. 
         [0060]    The second flip-flop unit  320  includes a plurality of flip-flops, e.g.,  321 , and a latch unit  326 . The first flip-flop  321  receives the internal read address RD_IADD through its input terminal D. Each flip-flop receives an input signal through its input terminal D and outputs a second output through its second output terminal /Q and a first output through its first output terminal Q. The second output is output as the CAS delay address. The latch unit  32   f  receives the first output of the last flip-flop  325  and outputs the last CAS delay address. 
         [0061]      FIG. 6  is a schematic circuit diagram depicting the flip-flop in the first flip-flop unit  240  shown in  FIG. 5 . 
         [0062]    Every flip-flop included in the first flip-flop unit  240  and the second flip-flop unit  320  has similar structure as that shown in  FIG. 6 . 
         [0063]    As shown, the first flip-flop  241  includes two transmission gate TG 9  and TG 10  and two latches  241   a  and  241   b . The ninth transmission gate TG 9  transmits the input signal input through its input terminal D in response to the additive drive clock AL_CLK of a logic low level. The first latch  241   a  latches an output of the ninth transmission gate TG 9  and outputs the second output as the delay address through the second output terminal /Q when a reset signal RST is inactive. When the reset signal RST is active, the first latch  241   a  resets the second output as a logic high level. The tenth transmission gate TG 10  transmits an output of the first latch  241   a  in response to the additive drive clock AL_CLK of a logic high level. The second latch  241   b  latches an output of the tenth transmission gate TG 10  and outputs the first output through the first output terminal Q when the reset signal RST is inactive. When the reset signal RST is active, the second latch  241   b  resets the first output as a logic low level. 
         [0064]    The first latch  241   a  includes two inverters I 2  and I 3  and a first NAND gate ND 1 . The second inverter I 2  inverts the reset signal RST. The first NAND gate ND 1  logically combines an output of the second inverter I 2  and the output of the ninth transmission gate TG 9 . The third inverter I 3  inverts the output of the first NAND gate ND 1 . An output terminal of the third inverter I 3  is connected to an output terminal of the ninth transmission gate TG 9 . The second latch  241   b  includes a first NOR gate NR 1  and a fourth inverter I 4 . The first NOR gate NR 1  logically combine the reset signal RST and the output of the tenth transmission gate TG 10 . The fourth inverter I 4  inverts an output of the first NOR gate NR 1 . An output terminal of the fourth inverter I 4  is connected to an output terminal of the tenth transmission gate TG 10 . 
         [0065]    When the reset signal RST is active, the first flip-flop  241  resets the first output as the logic low level and the second output as the logic high level. When the reset signal RST is inactive, the first flip-flop  241  outputs an input signal through the second output terminal /Q in synchronism with a falling edge of the additive drive clock AL_CLK. The first flip-flop  241  outputs the input signal through the first output terminal Q in synchronism with a rising edge of the additive drive clock AL_CLK. When the reset signal RST is active, the other flip-flops included in the first flip-flop unit  240 , e.g.,  242 ,  243 , 244 , and  245 , receiving the first output of logic low level, are turned off. The reset signal RST is correspond to the additive latency signal AL&lt;1:N−1&gt;. 
         [0066]    For example, when the additive latency of the semiconductor memory device is set to three clocks and the read command RD and an external address EXT_ADDR are input, the drive clock generation unit  100  enables the additive drive clock AL_CLK. The CAS drive clock CL_CLK is inactive because the write state signal WTS is inactive. The latch unit  220  latches the external address EXT_ADDR in response to the read/write flag RDWT which is enabled by an input of the read command RD. Because the additive latency of the semiconductor memory device is set to three clocks, the fourth additive latency signal AL&lt;3&gt; is active and the second and the third additive latency signals AL&lt;1&gt; and AL&lt;2&gt; are inactive. Therefore, the first and the second flip-flops  241  and  242  are serially turned on and serially outputs the delay addresses B&lt;1&gt; and B&lt;2&gt; in response to the additive drive clock AL_CLK. The first output of the third flip-flop  243  which receives the fourth additive latency signal AL&lt;3&gt; is reset to the logic low level. Accordingly, the flip-flops, e.g.,  244  and  245 , connected behind the third flip-flop  243  are turned off. The first selection unit  260  selects one of the delay addresses corresponding to the fourth additive latency signal AL&lt;3&gt; and outputs as the internal read address RD_IADD. The internal read address is output through the output driver  400  as the internal column address CA. 
         [0067]    As above described, the internal address generator of the present invention reduces current consumption by using flip-flops reset by the additive latency signal AL and the CAS latency signal CL. That is, the flip-flops which are not used to generate the delay address corresponding the additive latency or the CAS latency of the semiconductor memory device are turned off and, thus, the current consumed by the flip-flops can be reduced. As the internal address generator shown in  FIG. 5  is respectively provided for every bit of the external address EXT_ADDR, the current consumption effect is dramatically increased by the present invention. 
         [0068]      FIG. 7  is a block diagram describing an internal address generator in accordance with another embodiment of the present invention. 
         [0069]    In  FIG. 7 , the same or similar elements as those of  FIG. 5  are designated by the same reference numerals, and a detailed description thereof will not be made in order to avoid redundancy. Drive clock generation unit  100 , write address generation unit  300 , and output unit  400  included in the internal address generator shown in  FIG. 7  are similar with those shown in  FIG. 5 . Internal structure of a read address generation unit  500  is different from that shown in  FIG. 5 . 
         [0070]    The read address generation unit  500  includes a latch unit  520 , an input control unit  540 , an additive flip-flop unit  560 , and a first selection unit  580 . The latch unit latches the external address EXT_ADDR in response to the read/write flag RDWT. The input control unit  540  transmits an output of the latch unit  520  controlled by the zero additive latency signal AL&lt;0&gt;. The additive flip-flop unit  560  receives an output of the input control unit  540  and delays the output in response to the additive drive clock AL_CLK to thereby output a plurality of delay addresses. The first selection unit  580  selects one of the delay addresses in response to active one of the additive latency signal AL&lt;0:N&gt; and outputs the internal read address RD_IADD. 
         [0071]    The input control unit  540  includes a fifth inverter I 5  and a second NOR gate NR 2 . The fifth inverter I 5  inverts the output of the latch unit  520 . The second NOR gate NR 2  logically combines an output of the fifth inverter I 5  and the zero additive latency signal AL&lt;0&gt;. The additive flip-flop unit  560  includes a plurality of flip-flops, e.g.,  561 , and a latch unit  566 . Each flip-flop, e.g.,  561 , reset by corresponding additive latency signal, e.g., AL&lt;1&gt;, receives an input signal through its input terminal D and outputs a first and a second output respectively through a first and a second output terminal Q and /Q in response to the additive drive clock AL_CLK. The second output of each flip-flop output through the second output terminal /Q is the delay address. The latch unit  566  latches the first output of the last flip-flop  565  and outputs the last delay address. 
         [0072]      FIG. 8  is a schematic circuit diagram depicting the flip-flop shown in  FIG. 7 . 
         [0073]    The flip-flop, e.g.,  561 , includes two transmission gates TG 11  and TG 12  and two latches  561   a  and  561   b . The eleventh transmission gate TG 11  transmits the input signal in response to the additive drive clock AL_CLK of a logic low level. The first latch  561   a  latches an output of the eleventh transmission gate TG 11  and output as the delay address through the second output terminal /Q. The twelfth transmission gate TG 12  transmits an output of the twelfth transmission gate TG 12  in response to the additive drive clock AL_CLK of a logic high level. The second latch  561   b  resets the first output of the flip-flop when the reset signal RST is active and latches and outputs an output of the twelfth transmission gate TG 12  when the reset signal RST is inactive. The second latch  561   b  includes a third NOR gate NR 3  and a sixth inverter I 6 . The third NOR gate NR 3  logically combines the reset signal RST and the output of the twelfth transmission gate TG 12 . The sixth inverter I 6  inverts an output of the third NOR gate NR 3 . An output terminal of the sixth inverter I 6  is connected to an output terminal of the twelfth transmission gate TG 12 . 
         [0074]    The flip-flop shown in  FIG. 8  resets the first output as a logic low level when the reset signal is active as a logic high level. When the reset signal is inactive, the flip-flop outputs the input signal through the second output terminal /Q in synchronism with the falling edge of the additive drive clock AL_CLK and through the first output terminal Q in synchronism with the rising edge of the additive drive clock AL_CLK. Similar to the flip-flop shown in  FIG. 6 , the flip-flop shown in  FIG. 8  is reset by the corresponding additive latency signal. For example, when the additive latency of the semiconductor memory device is set to two clocks, the third additive latency signal AL&lt;2&gt; is active. The first output of the second flip-flop  562  receiving the third additive latency signal AL&lt;2&gt; is reset as a logic low level. Accordingly, the flip-flops, e.g.,  563 , connected behind of the second flip-flop  562  and the latch unit  566  are turned off. As a result, an internal address generator using the flip-flops shown in  FIG. 8  is possible to reduce current consumption. 
         [0075]    Though the internal address generators are only used for generating an internal column address in the abovementioned embodiments, the present invention is also used for generating internal commands and an internal bank address. 
         [0076]    The present invention reduces the current consumption by using delay elements which are reset by corresponding additive latency and CAS latency. 
         [0077]    The present application contains subject matter related to Korean patent application No. 2005-091582 and No. 2005-133960, filed in the Korean Patent Office on Sep. 29, 2005 and on Dec. 29, 2005, respectively, the entire contents of which are incorporated herein by references. 
         [0078]    While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.