Abstract:
An internal voltage control circuit includes active drivers, a control unit, and a time interval adjustment unit. The active drivers are configured to receive a common internal voltage. The control unit is configured to control respective enable operations of the active drivers. The time interval adjustment unit is configured to respectively supply enable signals, generated by the control unit, to the active drivers at respective predetermined time intervals.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2009-0133386, filed on Dec. 29, 2009, which is incorporated herein by reference in its entirety. 
       BACKGROUND OF THE INVENTION 
       [0002]    Exemplary embodiments of the present invention relate to an internal voltage control circuit which may reduce an operating current by distributing an operating time. 
         [0003]    Semiconductor devices are used in various fields. For example, semiconductor devices are used to store a variety of data. Since such semiconductor devices are used in various portable devices, including laptop computers and notebook computers, they are required to be high-capacity, high-speed, compact, and low-power. 
         [0004]    Semiconductor devices use an external power supply voltage to generate internal voltages having various levels. Specifically, a semiconductor memory device (DRAM) generates a core voltage (VCORE) which is to be used in a bank region (CORE) and a peripheral region (PERI), a high voltage (VPP) which is higher than an external voltage (VDD) and is to be applied to a gate of a cell transistor (word line), and a back bias voltage (VBB) which is lower than a ground voltage (VSS) and is to be used in a bulk portion of a cell transistor. 
         [0005]    In order to generate these internal voltages, a charge pumping scheme for VBB and VPP and a down converting scheme for VCORE are used. Without regard to the schemes, an internal reference voltage (VREF) is primarily generated, and new internal voltages (VBB, VPP, VCORE) are secondarily generated from the internal reference voltage (VREF). 
         [0006]    Ideally, such an internal reference voltage should have a constant level with regard to process, voltage and temperature (PVT) variations at a low operating voltage. 
         [0007]      FIG. 1  is a configuration block diagram of a conventional internal voltage control circuit. 
         [0008]    Referring to  FIG. 1 , core voltage (VCORE) active drivers  10  and  11  for generating a core voltage are provided in a bank core region  40 , the bank core region  40  being a first bank region. Also, (VCORE) active drivers  16  and  21  for generating a core voltage are provided in a bank core region  60 , the bank core region  60  being a second bank region. 
         [0009]    In a peripheral region  50  in which bank control circuits are provided, a plurality of core voltage (VCORE) active drivers  12  to  15  and  17  to  20  are provided around a core voltage (VCORE) control unit  30 . The core voltage control unit  30  controls the driving of the core voltage active drivers provided in the bank regions  40  and  60  and the peripheral region  50 , on the basis of bank active flag signals BANK_ACT_FLAG&lt;0:X&gt;. 
         [0010]    The conventional internal voltage control circuit having the above-described configuration operates as follows. 
         [0011]    The semiconductor device includes a plurality of banks, stores data in the banks, and reads out data stored in the banks. The core voltage active drivers are used for supplying voltages to the plurality of banks and for supplying voltages to be used in control circuits of the banks. 
         [0012]    Accordingly, the core voltage control unit  30  determines a bank to be operated by decoding the bank active flag signals BANK_ACT_FLAG&lt;0:X&gt;. The core voltage control unit  30  enables the core voltage active driver to supply a voltage to the selected bank, and the core voltage active driver supplies a voltage to the control circuit of the selected bank. 
         [0013]    There is no problem when the single bank and its control circuit are activated. However, in a case in which all banks are activated, as in an auto-refresh operation mode, that is, when all of the bank active flag signals BANK_ACT_FLAG&lt;0:X&gt; are enabled, the core voltage control unit  30  simultaneously drives all of the core voltage active drivers  10  to  21  provided in the first and second bank regions  40  and  60  and the peripheral region  50 . 
         [0014]    In this case, a large amount of IDD current is required when all of the core voltage active drivers  10  to  21  are simultaneously driven. Specifically, in the auto-refresh operation mode, excessive IDD current and VCORE peak current are caused when all of the core voltage active drivers simultaneously operate, resulting in a VDD voltage level drop. If the VDD voltage level drop is caused by the generation of the core voltage, a current to be supplied to other circuits (e.g.—the VPP pump circuit) becomes insufficient. Thus, other circuits may fail to operate. 
       SUMMARY OF THE INVENTION 
       [0015]    An embodiment of the present invention is directed to an internal voltage control circuit which may reduce an operating current by distributing a drive operating time according to an amount of core current and Locations of active drivers. 
         [0016]    In accordance with an embodiment of the present invention, an internal voltage control circuit includes active drivers configured to receive a common internal voltage, a control unit configured to control enable operations of the respective active drivers, and a time interval adjustment unit configured to respectively supply an enable signal, generated by the control unit, to the active drivers at respective predetermined time intervals. 
         [0017]    In accordance with another embodiment of the present invention, an internal voltage control circuit includes active drivers configured to receive a common internal voltage and a control block configured to control enable operations of the active drivers at respective predetermined time intervals during simultaneous operations of a number of banks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0018]      FIG. 1  is a block diagram illustrating an overall configuration of a conventional internal voltage control circuit. 
           [0019]      FIG. 2  is a block diagram illustrating an overall configuration of an internal voltage control circuit in accordance with an embodiment of the present invention. 
           [0020]      FIG. 3  is a detailed configuration diagram illustrating a delay control unit of  FIG. 2 . 
       
    
    
     DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0021]    Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0022]      FIG. 2  is a block diagram of an internal voltage control circuit in accordance with an embodiment of the present invention. 
         [0023]    Referring to  FIG. 2 , core voltage (VCORE) active drivers  100  and  101  for generating a core voltage are provided in a bank core region  400 , the bank core region  400  being a first bank region. Also, core voltage (VCORE) active drivers  106  and  107  for generating a core voltage are provided in a bank core region  600 , the bank core region  600  being a second bank region. 
         [0024]    In a peripheral region  500  in which bank control circuits are provided, a plurality of core voltage (VCORE) active drivers  102  to  105  and  108  to  111  are provided around a core voltage (VCORE) control unit  300 . The core voltage control unit  300  controls the driving of the core voltage active drivers provided in the bank regions  400  and  600  and the peripheral region  500 , on the basis of bank active flag signals BANK_ACT_FLAG&lt;0:X&gt;. 
         [0025]    Meanwhile, the operation of the core voltage active drivers is controlled, while adjusting time intervals of their operating times. Specifically, when a large amount of IDD current is needed, as in an auto-refresh operation mode in which all banks simultaneously operate, an operating time of each core voltage active driver may be adjusted according to its location and an amount of current needed. 
         [0026]    Therefore, the internal voltage control circuit is divided into a core voltage active driver group which may be operated in response to a first enable signal (output A) of the core voltage control unit  300 , a core voltage active driver group which may be operated in response to a second enable signal (output B) generated by delaying the first enable signal generated by the core voltage control unit  300  for a predetermined time (i.e. 1 hour), and a core voltage active driver group which may be operated in response to a third enable signal (output C) generated by delaying the second enable signal for the predetermined time (i.e. 1 hour). 
         [0027]    To this end, the internal voltage control circuit includes delay control units  201  and  202  configured to generate the second enable signal (output B) by delaying the first enable signal (output A) for the predetermined time, and delay control units  200  and  203  configured to generate the third enable signal (output C) by delaying the second enable signal for the predetermined time. 
         [0028]    The core voltage active driver group operated in response to the first enable signal (output A) includes the core voltage active drivers  100  and  101  disposed in the first bank area  400 , and the core voltage active drivers  106  and  107  disposed in the second bank  600 . 
         [0029]    The core voltage active driver group operated in response to the second enable signal (output B) includes the core voltage active drivers  104  and  105  and the core voltage active drivers  108  and  110  disposed in the peripheral region  500 . 
         [0030]    The core voltage active driver group operated in response to the third enable signal (output C) includes the core voltage active drivers  102  and  103  and the core voltage active drivers  111  and  109  disposed in the peripheral region  500 . 
         [0031]    The operation time intervals of the core voltage active drivers may be set because the drivers can be controlled based on their locations. To this end, the delay control units  200  to  203  are configured as illustrated in  FIG. 3 . 
         [0032]    Each of the delay control units  200  to  203  includes an input section  410 , first and second switches  403  and  404 , a delay section  401  (DELAY  1 ), and an output section  402 . The input section  410  is configured to input the enable signal A generated by the core voltage control unit  300 , or the enable signal B outputted by the delay control units  201  and  202 . The first and second switches  403  and  404  are configured to transfer the enable signal received from the input section  410 . The delay section  401  is configured to delay the enable signal transferred from the second switch  404  by a predetermined time. The output section  402  is configured to output the signal transferred from the first switch  403 , or the delayed signal outputted from the delay section  401 . The first and second switches  403  and  404  may be configured with transmission gates, and the output section  402  may be configured with a NOR gate. The first switch  403  transfers the inputted enable signal when an auto-refresh entry flag signal or an all-bank enable flag signal, for example, is not inputted. On the other hand, the second switch  404  transfers the inputted enable signal when the auto-refresh entry flag signal or the all-bank enable flag signal, for example, is inputted. 
         [0033]    The operation of the internal voltage control circuit having the above-described configuration in accordance with the embodiment of the present invention will be described below. 
         [0034]    The operation of the internal voltage control circuit is divided into two control operations. The first control operation corresponds to a case in which the auto-refresh entry flag signal or the all-bank enable flag signal, for example, is not applied. In this case, the enable signal generated by the core voltage control unit  300  is directly provided to the corresponding core voltage active driver, without being delayed. Typically, this case corresponds to a case in which a specific bank is activated. 
         [0035]    That is, one of the bank active flag signals BANK_ACT FLAG&lt;0:X&gt; is inputted to the core voltage control unit  300 , and the core voltage control unit  300  decodes the inputted address and generates the enable signal which activates the core voltage active driver of the corresponding bank. The auto-refresh entry flag signal or the all-bank enable flag signal, for example, are not provided by the device which provides a control signal, such as a mode register set (MRS). The second switch  404  maintains a turned-off state, and the first switch  403  is turned on. 
         [0036]    Therefore, the enable signal generated by the core voltage control unit  300  passes through the first switches  403  included in the delay control units  200  to  203 , and is provided to the corresponding core voltage active drivers. In this case, the enable signal generated by the core voltage control unit  300  is provided to the corresponding core voltage active driver, without any delay procedure. 
         [0037]    The second control operation is a case in which the auto-refresh entry flag signal or the all-bank enable flag signal, for example, is applied. In this case, the enable signal generated by the core voltage control unit  300  is delayed and provided to the core voltage active driver at time intervals. Typically, this case corresponds to a case in which all banks are activated when in the auto-refresh operation mode, for example. 
         [0038]    That is, when all addresses included in the bank active flag signals BANK_ACT_FLAG&lt;0:X&gt; are inputted to the core voltage control unit  300 , the core voltage control unit  300  generates the enable signal which activates all of the core voltage active drivers. 
         [0039]    The auto-refresh entry flag signal and the all-bank enable flag signal are provided by the device which provides a control signal, such as a mode register set (MRS). The second switch  404  is turned on, and the first switch  403  is turned off. 
         [0040]    Preferentially, the enable signal generated by the core voltage control unit  300  activates the core voltage active drivers  100 ,  101 ,  106  and  107  disposed in the first bank region  400  and the second bank region  600  which require a fast response. 
         [0041]    Then, the enable operation of the core voltage active driver disposed in the peripheral region  500  which does not require a fast response is controlled. That is, the enable signal (output A) generated by the core voltage control unit  300  is inputted to the delay control units  201  and  202 . 
         [0042]    Since the second switch  404  inside the delay control units  201  and  202  maintain a turned-on state, the enable signal A is delayed through the delay section  401  by a first delay time and outputted as the enable signal B. The enable signal B enables the core voltage active drivers  104 ,  105 ,  110  and  108  to operate. The enable signal B is a signal generated by delaying the signal A by the first delay time. 
         [0043]    Subsequently, the enable signal B having passed through the delay section  401  is inputted to the delay control units  200  and  203 . Since the second switch  404  maintains the turned-on state, the signal B is delayed through the delay section  401  by a second delay time and outputted as the enable signal C. The enable signal C enables the core voltage active drivers  102 ,  103 ,  111  and  109  to operate. The enable signal C is a signal generated by delaying the enable signal A by the sum of the first delay time and the second delay time. 
         [0044]    Therefore, when using the core voltage current, the drive disposed in the bank region (core region) which requires a fast response is operated quickly. The driver disposed in the peripheral region which does not require a relatively fast response compared with the bank region is controlled to operate at predetermined time intervals in a distributed manner. Thus, it is possible to suppress the generation of IDD peak current which may be caused by the simultaneous operations of many or all of the banks. 
         [0045]    When all of the banks are simultaneously operated when in the auto-refresh operation mode, for example, the operating time of the active drivers disposed in each region is distributed while dividing the regions into a region which requires a fast response, such as the bank region, and a peripheral region in which a relatively slow response is possible as compared with the bank region. Therefore, the peak current value due to the instantaneous operation of many or all of the banks can be reduced. 
         [0046]    While the present invention has been described with respect to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the following claims.