Abstract:
A DC-DC converter operates outside of an audible frequency range under light current load conditions with reduced switching frequency by reducing supply current and regulating output voltage. A control for the converter maintains the switching frequency above an audible frequency range and reduces supply current by modulating switch on-time, sinking supply current, or permitting negative supply current values. The output voltage of the converter is regulated by modulating switch on-time, clamping output voltage, or modifying feedback detector thresholds. The power converter operates with improved efficiency under light current load conditions, while avoiding operation in an audible frequency range to prevent the generation of audible noise in converter components.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims the benefit of U.S. Provisional Application No. 60/632,921, filed Dec. 3, 2004. 
     
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     N/A  
       BACKGROUND OF THE INVENTION  
       [0003]     1. Field of the Invention  
         [0004]     The present invention relates generally to high efficiency power converters for use in supplying a wide range of load current, and relates more particularly to a DC-DC converter that avoids operation in an audible frequency range when supplying loads current.  
         [0005]     2. Description of Related Art  
         [0006]     High efficiency demands are often placed on power converters, especially DC-DC converters for use in a number of applications. One particular application that produces a broad range of load current demand conditions is in the area of portable equipment products, such as notebook computers. The power demands of portable equipment can change dramatically from moment to moment, due to the focus on power efficiency, extending battery life and reducing power consumption. A number of solutions for portable equipment using DC-DC converters have been proposed, typically focusing on efficiency and handling dramatic changes in load current demands. For example, one way to handle rapidly changing load current demands, while maintaining high efficiency is to skip clock pulses or change switching frequency of the DC-DC converter as a function of load current. As load current demand decreases, more pulses are skipped, or frequency is further reduced resulting in a lower amount of output current.  
         [0007]     As apparent switching frequency decreases, it is possible to enter an audible frequency range, resulting in the production of audible output from components of the DC-DC converter. In particular, output components such as inductors or capacitors can be driven at an audible frequency, resulting in audible buzzing or ringing of the components which is highly undesirable in generally, and particularly undesirable in the case of portable equipment.  
         [0008]     Referring to  FIG. 1 , a circuit  10  illustrates the operation of a DC-DC converter according to a conventional design that presents challenges related to operation in the audible frequency range. Circuit  10  is generally efficient in continuous conduction mode related to high current demand through the operation of switches M 1 , M 2  configured in a switching half bridge arrangement. In the case of low current demand, circuit  10  operates in discontinuous conduction mode, and can still maintain a high efficiency as the frequency decreases in a proportional relationship to the load current demand.  FIG. 2  illustrates voltage and current weight forms for low current demand with a low switching frequency and discontinuous mode.  
         [0009]     As the switching frequency of circuit  10  continues to decrease, it can enter the audible frequency range producing audible sound in external components such as inductor Lx or capacitor Cout. However, if the switching frequency range is limited to be above the audible frequency range, an over voltage condition may be generated where circuit  10  supplies a greater current than is demanded by the load. If the additional current output is shunted, the efficiency of circuit  10  decreases dramatically.  
         [0010]     It would be desirable to obtain a DC-DC converter for portable equipment that does not suffer from the drawbacks of the conventional art.  
       SUMMARY  
       [0011]     In accordance with the present invention, there is provided a power converter for portable equipment that has a switching frequency range of operation outside of an audible frequency range. The power converter provides DC-DC power converter operation with current and voltage output limits in relation to the demand from the load application. With low load current demand, as the proportional switching frequency decreases toward a predetermined value, a control is applied to turn on a switch to deliver current to the load. Turning on the switch tends to maintain on the switching frequency of the converter and avoid operation in the audible frequency range. By maintaining a particular switching frequency, output current, and potentially output voltage, increase to induce an over voltage condition. The present invention applies an additional control to regulate or decrease output current and/or voltage.  
         [0012]     According to an aspect of the present invention, a timer monitors an interval when a switch is in an off state to determine switching frequency. At the end of the timer interval, a flag is set to indicate that the limits of low frequency operation have been reached. On the basis of the flag indication, the switch is turned on to maintain a desired switching frequency minimum.  
         [0013]     According to another aspect of the present invention, increased output voltage or current produced when operating near the low frequency limit is monitored. An on-time of the switch is modified to avoid higher output voltage values, and limit or reduce output current.  
         [0014]     According to an advantage of the present invention, the switch on-time control is regulated by a feedback signal from the output voltage with a multiplier. The multiplier permits consistent load regulation in a number of input and output voltage combinations.  
         [0015]     According to an embodiment of the present invention, output voltage produced when operating near the low frequency limits is regulated with a clamping circuit. The clamping circuit clamps the output voltage and sinks output current to maintain a regulated voltage while permitting operation of the converter near the low frequency limits.  
         [0016]     According to an advantage of the present invention, the clamping circuit is activated when both switches in a switching half bridge configuration are off. By applying the clamping control when both half bridge switches are off, the circuit avoids discharging the output inductor to avoid reducing the efficiency of the power converter.  
         [0017]     According to another embodiment of the present invention, there is provided a control for sinking current through the output inductor by allowing negative inductor current. The control operates by modulating a threshold voltage applied to a zero crossing detection comparator, so that a rectifying switch coupled to the inductor may be conducting for a longer time than usual. The longer conduction time allows for circumstances where the inductor current is negative.  
         [0018]     According to an aspect of the present invention, a threshold voltage for a zero crossing of a low side switch in a switching half bridge is modified to prevent the low side switch from turning off after reaching an on-time limit. By extending the on-time of the low time switch, current is discharged from the output inductor and the output voltage remains regulated.  
         [0019]     Other objects features and advantages of the present invention will be apparent from the detailed description of the invention that follows. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The invention will be more fully understood with reference to the detailed of the invention, when read in conjunction with the accompanying drawings, in which:  
         [0021]      FIG. 1  is a circuit block diagram of a conventional power converter;  
         [0022]      FIG. 2  is a set of graphs illustrating output voltage and current for the converter of  FIG. 1 .  
         [0023]      FIG. 3  is a circuit block diagram of a converter according to the present invention;  
         [0024]      FIG. 4  is a set of graphs showing output voltage and current way forms relating to the circuit of  FIG. 3 ;  
         [0025]      FIG. 5  is a circuit block diagram of a power converter according to another embodiment of the present invention;  
         [0026]      FIG. 6  is a set of graphs showing output current and voltage wave forms related to the circuit of  FIG. 5 ;  
         [0027]      FIG. 7  is a circuit block diagram of a power converter according to another embodiment of the present invention; and  
         [0028]      FIG. 8  is a set of graphs showing output voltage and current weight forms related to the circuit of  FIG. 7 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0029]     The entire contents of U.S. Application No. 60/632,921 is hereby incorporated herein by reference.  
         [0030]     The present invention provides a system and technique for avoiding operation at a switching frequency in an audible frequency range. Challenges relating to the regulation of output current and voltage are handled with innovative approaches that maintain a high operational efficiency even at light load currents.  
         [0031]     Referring now to  FIG. 3 , a circuit block diagram  20  illustrates an embodiment of the power converter according to the present invention. Circuit  20  includes a number of elements that are substantially similar to the conventional DC-DC power converter of  FIG. 1 . For example, circuit  20  includes zero crossing comparator  11 , loop comparator  12 , minimum off-time timer  13 , on-time timer  15 , cross conduction control  16  and high and low side drivers  14  and  18 , respectively. In addition, according to the present invention, circuit  20  includes a time-out timer  22  and an on-time shaver  24 .  
         [0032]     Timer  22  includes an inverter  21  that drives a MOSFET switch  23  coupled across timing capacitor CTO. Inverter  21  is driven by an output signal from cross-conduction control  16 , indicative of a state of high side switch M 1 . When high side switch M 1  is off, the input to inverter  21  receives a logic high signal, resulting in switch  23  switching to a high impedence state, which permits timing capacitor CTO to be charged with current source Ito. Accordingly, timer  22  is started when high side switch M 1  is turned off. If the voltage on timing capacitor CTO reaches a given threshold value indicated as the input to the inverting side of comparator  25 , the output of comparator  25  becomes a logic high, which in turn enables the set input of PWM latch flip-flop  26  side so that high switch M 1  can be turned on. Accordingly, time out timer  22  measures an interval of time after high side switch M 1  turns off, that is related to a particular switching frequency, indicative of operation near an audible frequency range. An exemplary value for the time internal is 32 μs, so that switching frequency is outside of the audible frequency range.  
         [0033]     With the addition of timer  22  in circuit  20 , a switching frequency minimum is obtained to avoid operation in an audible frequency range. However, by causing high side switch M 1  to turn on at a shorter interval that is indicated by the low level of current demand, additional current is delivered to inductor Lx. The additional current supplied to the output of the switching half bridge increases the output voltage Vout which can lead to an over voltage condition in the output.  
         [0034]     In accordance with the present invention, on-time shaver  24  modulates the on-time of high side switch M 1  to perform the dual function of permitting current to decrease while regulating output voltage. On-time shaver  24  operates by monitoring output voltage Vout and decreases, or shaves, the on-time of switch M 1  if the output voltage becomes higher than a predetermined value. As illustrated in circuit  20 , the output voltage value for voltage Vout that activates on-time shaver  24  is equal to reference voltage Vref of loop comparator  12  plus offset threshold voltage Voff 1 . The cumulative reference voltage is applied to the non-inverting input of the comparator in on-time shaver  24 . As the on-time for switch M 1  is shaved, or decreased, the current delivered to the output for each cycle of the control becomes smaller. Accordingly, on-time shaver  24  provides an additional feedback loop to regulate output voltage.  
         [0035]     On-time shaver  24  includes a multiplier  27  that provides a dynamic range of operation for input and output values. Multiplier  27  can be viewed as a compensator for use of on-time shaver  24  with on-time timer  15 , in the event a conversion is needed. That is, on-time timer  15  operates with a feedback from output voltage Vout, which may be on a different scale, or different dynamic range, than that used with on-time shaver  24 . Accordingly, multiplier  27  can compensate the output of the comparator in on-time shaver  24  to provide a suitable input for the comparator in on-time timer  15 . Multiplier  27  thus provides additional flexibility in the operation of the converter at a frequency that is above the audible frequency range. Multiplier  27  permits approximately the same load regulation for all input and output combinations. However, it should be apparent that circuit  20  can be configured to operate without multiplier  27 , such that on-time shaver  24  simply indicates when high side switch M 1  should be turned off by appropriately resetting PWM latch flip-flop  26 .  
         [0036]     Referring now to  FIG. 4 , two sets of graphs illustrating output voltage and current for circuit  20  are illustrated. Graphs  44  and  46  illustrate operation of circuit  20  with time-out timer  22  being active to prevent the switching frequency from falling into the audible frequency range. Graph  46  indicates high peak voltages on the output due to the high currents seen in graph  44 . The high currents in graph  44  and the high peak voltages in graph  46  are the result of turning high side switch M 1  on early to avoid operation in a lower frequency range.  
         [0037]     Graphs  40  and  42  of  FIG. 4  illustrate operation of circuit  20  with on-time shaver  24  being active. As can be seen in graph  40 , the output current is greatly reduced as are the peak voltages in graph  42 . Thus, the goals of reducing current, while regulating output voltage is achieved.  
         [0038]     Referring now to  FIG. 5 , another embodiment according to the present invention is illustrated generally as circuit  50 . Circuit  50  prevents operation of the power converter in an audible frequency range and also accommodates situations in which the load current demand becomes very small. When the control of the converter illustrated in circuit  50  prevents operation in the audible frequency range, supply current may increase, producing a corresponding output voltage increase. As the on-time of switch M 1  is reduced according to the embodiment illustrated in  FIG. 3 , output current can be reduced while output voltage is regulated. However, as load current becomes very small, the limitations of the on-time of switch M 1  prevents the on-time from becoming less than a particular value. For example, the on-time may be limited by the response time of switch M 1  formed as a semiconductor device. Accordingly, since a shorter on-time may not be available due to a minimum on-time constraint, the output voltage increases as a result of when load current demand becomes very small.  
         [0039]     In accordance with the control illustrated in circuit  50 , an over voltage in the presence of low current demand is detected in an over voltage (OV) clamp circuit  56 . OV clamp circuit  56  includes two n-channel MOSFETs M 3 , M 4  arranged in a stacked configuration and are connected to the power converter output node. When switches M 3 , M 4  are both conducting, they sink current from the output of circuit  50  to reduce output current and provide output voltage regulation for very low load current demand. Switch M 3  is operated by the output of a toggle flip-flop  54 , arranged in a series of toggle flip-flops in time-out timer circuit  52 . Timer circuit  52  is enabled when high side switch M 1  is turned off, at which point oscillator  57  is activated to propagate a pulse through toggle flip-flops  53 - 55 . As switch M 3  becomes activated, clamp circuit  56  can respond to over voltage output conditions by causing switch M 4  to conduct to sink output current to reduce output voltage. Clamp circuit  56  includes an op-amp  58  with a reference voltage applied to the inverting input terminal to detect when a converter output voltage exceeds the given threshold value. The reference voltage is represented by offset reference voltage Voff 2  plus reference voltage Vref. Once the converter output voltage exceeds offset reference voltage Voff 2  plus reference voltage Vref, switch M 4  conducts and clamp circuit  56  sinks current from the converter output to reduce output voltage and maintain a regulated voltage output.  
         [0040]     Time-out timer  52  also acts to turn on high side switch M 1  after a particular time interval has passed, to avoid operation in an audible frequency range. Toggle flip-flop  55  provides the enable for setting PWM latch flip-flop  26  to cause the output of flip-flop  26  to become a logic high level, turning on switch M 1 . Accordingly, toggle flip-flop  54  enables clamp circuit  56  before the time out for operation in an audible frequency range occurs. Preferably, toggle flip-flop  54  enables clamp circuit  56  when both switches M 1 , M 2  are off to avoid additional voltage discharge that may lower converter efficiency. That is, it is preferable to sink current out of the converter output when both switches M 1  and M 2  are in a non-conducting state to avoid additional output component discharge that would lower converter efficiency. In addition, the reference voltage applied to the inverting input of op-amp  58  in clamp circuit  56  is equal to the total of reference voltage Vref plus offset reference voltage Voff 2 , which determines when clamp circuit  56  is activated. Voff 2  is preferably higher than first offset voltage Voff 1 , related to time shaving. As such, the clamping circuit is activated after the on-time shaver has been activated.  
         [0041]     Referring to  FIG. 6 , a number of current and voltage waveforms are illustrated that show how clamp circuit  56  impacts the converter output. In graphs  62  and  64 , the inductor current and output voltage in a low current load demand situation are illustrated. As can be seen from graphs  62  and  64 , the inductor current ILx is somewhat large, even with a low load current demand, and output voltage Vout has high peak values. Graphs  62  and  64  illustrate the output of circuit  50  in a low current load demand state, when clamp circuit  56  is inactive.  
         [0042]     Graphs  66  and  68  illustrate inductor current ILx and output voltage Vout, respectively, in a low current load demand state, when clamp circuit  56  is active. As can be seen from graph  66  inductor current ILx is greatly reduced over substantially the same switching interval. In addition, output voltage Vout is clamped to the voltage value represented by the sum of voltage references Vref and Voff 2 . Graph  68  also illustrates how the clamp is applied on the output voltage after the passage of a particular interval, which is related to the activation of the non-inverting output of toggle flip-flop  54  to enable clamp circuit  56 . In addition, the clamp on the output voltage is released once the output voltage drops below the given threshold value related to operation of clamp circuit  56 . Graph  68  illustrates how output voltage is regulated using clamp circuit  56  and time-out timer circuit  52  in the case of very low current load demand situations.  
         [0043]     Referring for a moment to  FIG. 3 , the role of zero crossing comparator circuit  11  is to monitor the output node of the switching half bridge composed of switches M 1  and M 2 , and turn off low side switch M 2  when the node voltage is zero. Turning off switch M 2  when the node voltage is zero prevents negative inductor current in the output. Circuit  11  thus provides a technique for operating the power converter in discontinuous conduction mode.  
         [0044]     Referring now to  FIG. 7 , another embodiment of the present invention is illustrated as circuit  70 . Circuit  70  is similar to the embodiment of  FIG. 3 , with threshold shifting circuitry added. A modified zero crossing comparator circuit  72  achieves the same function as circuit  11 , but can also have a shifted reference threshold in the event that load currents become very small. As discussed above, very small load currents tend to cause the converter to operate at a switching frequency outside the audible frequency range in accordance with the present invention, which tends to cause the on-time of switch M 1  to be shortened to maintain proper voltage regulation with reduced current output. A zero crossing shifter circuit  76  is activated when the on-time for switch M 1  is reduced beyond a predetermined time, to change the threshold voltage of zero crossing comparator circuit  72 . The predetermined time can be related to switch response time limitations, for example. Zero crossing shifter circuit  76  permits current to flow from its output through resistor Rzc once the on-time for switch M 1  reaches a minimum on-time threshold. The current flow and subsequent threshold modulation reduces average current delivered to the output and regulates output voltage. Shifter circuit  76  monitors node A, which is the output of multiplier  27  in on-time shaver  24 . The voltage value of node A is applied to the inverting input of an amplifier, such as a source only transconductance amplifier  77  in shifter circuit  76 . Offset reference voltage Voff 3  provides a reference voltage to the non-inverting input of amplifier  77 , and serves as a threshold for determining when the threshold of zero crossing comparator circuit  72  should be shifted. Accordingly, when the voltage on node A is less than reference voltage Voff 3 , amplifier  77  begins sourcing current to the inverting input of the comparator in zero crossing comparator circuit  72 . As current flows through resistor Rzc, the apparent ground point reference for comparator  73  rises above zero or ground potential. Accordingly, the output of comparator  73  is not activated until the voltage across M 2  rises to the new, lower threshold value. The implication for operation of the circuit is that negative inductor current is allowed for some period of time before low side switch M 2  turns off. When high side switch M 1  turns on, the switching node between switches M 1  and M 2  returns to input voltage Vin, which causes the inductor current to begin reversing and eventually become zero. It should be apparent that any type of component can be used in place of resistor Rzc, including passive components such as capacitors or inductors, or active components such as switches, including MOSFETs, or diodes, or any combination of the above.  
         [0045]     Referring now to  FIG. 8 , the voltage, and current graphs for operation of circuit  70  in low current load conditions are illustrated. Graphs  82  and  84  illustrate current and voltage for circuit  70  when zero crossing shifting circuit  76  is inactive and the threshold applied to the inverting input of comparator  73  remains zero. Current graph  82  shows that the current remains above zero, in keeping with a comparator threshold of zero in zero crossing comparator circuit  72 . Similarly, the voltage output in graph  84  has high peak voltages. The current illustrated in graph  82  is greater than that desired for low current load demand situations.  
         [0046]     When zero crossing shifting circuit  76  is active, the threshold of comparator  73  can be shifted in low current load conditions to permit switch M 2  to remain on longer, when a minimum on-time limitation has been reached for high side switch M 1 . Activation of zero crossing shifter circuit  76  permits inductor current to become negative and limits the amount of current supplied to the load in the low current load condition, as can be seen in graph  86 . Graph  88  illustrates regulated output voltage with smaller peak variations. Accordingly, the embodiment of the present invention illustrated in circuit  70  provides a control for low load current demand, without moving the switching frequency into the audible frequency range, even when the limits of on-time for switch for M 1  have been reached. By permitting the threshold of comparator  73  to be changed, by sourcing current through resistor Rzc, the on-time for switch M 1  can be kept equal to or higher than a minimum limitation, while reducing supply current and maintaining a regulated voltage output.  
         [0047]     In general, the present invention reduces switching frequency on light current load conditions to the point where the switching frequency is near the audible frequency range, meaning a switching interval of approximately 32 microseconds for both switching MOSFETs. When the switching frequency of the converter approaches an audible frequency range, a switching frequency outside of the audible frequency range is maintained, even if the output voltage is higher than a target value. Since the output voltage tends to be higher according to this technique, the power converter control compensates for overvoltage conditions and modulates the on-time of a high side switch in the switching half bridge to maintain the output voltage at a particular level. For example, the output voltage may become 1% higher than normal light load operation to prevent operation in the audible frequency range. When the converter control has a feedback amplifier and is operated in a current mode, the output voltage can be maintained at approximately the desired level through the additional influence applied by the gain of a feedback amplifier in the current control loop.  
         [0048]     A power converter controller in accordance with the present invention produces greater efficiency than previous power converters operating outside an audible frequency range in low current load conditions. Table 1 below illustrates relative efficiency levels for low current loads during operation at frequencies outside of an audible frequency range.  
                       TABLE 1                       Load (MA)   Present Invention   Prior Converters                    1 mA   35%   10%        5 mA   70%   35%       10 mA   79%   50%       30 mA   86%   70%                  
 
         [0049]     Although the present invention has been described in relation to particular embodiments thereof, other variations and modifications and other uses will become apparent to those skilled in the art from the description. It is intended therefore, that the present invention not be limited not by the specific disclosure herein, but to be given the full scope indicated by the appended claims.