Abstract:
The present invention relates to a ring oscillator having a variable frequency allowing its use in a variety of application circuits. The ring oscillator produces an oscillating pulse signal having a frequency adjustable by an external input voltage. The ring oscillator includes an oscillating signal for generating an oscillating pulse signal, a frequency adjusting circuit, and an inverting circuit. The frequency adjusting circuit adjusts the frequency of the oscillating pulse signal responsive to the external input voltage, the external input voltage being different than a source voltage. The inverting circuit inverts the oscillating pulse signal.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a ring oscillator and, more particularly, to a ring oscillator having a variable frequency. 
     2. Description of the Related Art 
     Ring oscillators are widely used in electronic equipment such as computers, televisions, videocassette recorders (VCRs) and the like. Typically, a ring oscillator comprises a series of discrete components including transistors, capacitors, etc. For a predetermined combination of discrete components, a conventional ring oscillator only produces a fixed frequency. That is, once assembled, the frequency of the oscillating signal generated by a ring oscillator cannot be externally adjusted. The result is that a conventional ring oscillator can only be used in a limited manner in electronic equipment. 
     Accordingly, a need remains for a ring oscillator having an externally adjustable variable frequency. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to overcome problems associated with prior art ring oscillators. 
     Another object of the invention is to provide a ring oscillator having a variable frequency capable of use in different application circuits. The ring oscillator according to the present invention comprises an oscillating circuit for producing an oscillating pulse signal and a frequency adjusting circuit coupled to the oscillating circuit for varying a frequency of the oscillating pulse signal. The oscillating pulse signal includes a constant duty cycle. 
     The oscillating circuit comprises a current supply means for supplying a current and a charging/discharging means coupled to the current supply means for generating a first and a second node voltages by charging and discharging a first and second capacitors with the current responsive to an internal voltage. A switching means is coupled to the charging/discharging means for selectively providing either the first or a second node voltage as a switching means output signal responsive to a control signal. An inverting means including a first inverter for inverting the switching means output signal. The frequency adjusting circuit varies the frequency of the oscillating pulse signal by adjusting a charge/discharge time of the first capacitor. 
     The frequency adjusting circuit comprises a reference voltage means for supplying a reference voltage, a voltage comparator for comparing the reference voltage with an externally input voltage and adjusting the charge/discharge time of the first capacitor, and a current mirror coupled to the differential amplifier for adjusting a charge/discharge current. The frequency adjusting circuit may also comprise a current mirror having first and second NMOS transistors, a third NMOS transistor connected in parallel to the first NMOS transistor, and a first PMOS transistor coupled to the first NMOS transistor. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The foregoing and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of a preferred embodiment that proceeds with reference to the following drawings. 
     FIG. 1 is a circuit diagram of a ring oscillator having a variable frequency according to a first preferred embodiment of the present invention. 
     FIG. 2 is a timing diagram of the output signal OUT 1  shown in FIG.  1 . 
     FIG.  3 ( a ) is a timing diagram of the input signal VIN 1  and the voltage signal at node A 6  for the circuit shown in FIG.  1 . 
     FIG.  3 ( b ) is a timing diagram of the output signal OUT 1  for the circuit shown in FIG.  1 . 
     FIG. 4 is a circuit diagram of a ring oscillator having a variable frequency according to a second preferred embodiment of the present invention. 
     FIGS.  5 ( a ) and  5 ( b ) are timing diagrams of the input signal VIN 1  and the output signal OUT 1  for the circuit shown in FIG.  4 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 is a circuit diagram of a ring oscillator having a variable frequency according to a first preferred embodiment of the present invention. Referring to FIG. 1, the ring oscillator having a variable frequency includes an oscillating circuit  1  for producing an oscillated pulse signal, a frequency adjusting circuit  3  for adjusting the frequency of the oscillating circuit  1  while maintaining constant the duty cycle of the oscillated pulse signal, and an inverting output circuit  2  for inverting the oscillated pulse signal output from the oscillating circuit  1 . 
     The oscillating circuit  1  includes a current supply means  31 , a charging/discharging means  32 , a first switch  33 , a second switch  34 , a first inverter  35 , a second inverter  36 , and a third inverter  37 . The current supply means  31  includes a current source IS 1 , P-type Metal Oxide Semiconductor (PMOS) transistors Q 6  and Q 7 , and N-type Metal Oxide Semiconductor (NMOS) transistors Q 8 . The charging/discharging means  32  includes capacitors C 1  and C 2 , PMOS transistors Q 9  and Q 11 , and an NMOS transistor Q 12 . The first switch  33  includes a PMOS transistor Q 13  and an NMOS transistor Q 14 . The second switch  34  includes a PMOS transistor Q 15  and an NMOS transistor Q 16 . The first inverter  35  includes a PMOS transistor Q 17  and an NMOS transistor Q 18 . The second inverter  36  includes a PMOS transistor Q 19  and an NMOS transistor Q 20 . The third inverter  37  includes a PMOS transistor Q 21  and an NMOS transistor Q 22 . 
     The frequency adjusting circuit  3  includes a resistor R 1  connected to a supply voltage VCC 1 , a resistor R 2  connected between the resistor R 1  and a ground voltage GND 1 , and a PMOS transistor Q 1  forming a current mirror with the PMOS transistor Q 6  of the current supply means  31 . A PMOS transistor Q 2  has a source connected to a drain of the PMOS transistor Q 1  and a gate connected to a node between the resistors R 1  and R 2 . An NMOS transistor Q 4  has a source and gate connected to a drain of the PMOS transistor Q 2 . A PMOS transistor Q 3  has a source connected to a drain of the PMOS transistor Q 1  and a gate provided with an external input voltage VIN 1 . A PMOS transistor Q 5  has a drain connected to node A 1  between the drains of PMOS transistors Q 3  and Q 9 , a gate connected to a drain of the PMOS transistor Q 2 , and a source connected to a ground voltage GND 1 . 
     The inverting output circuit  2  includes a PMOS transistor Q 23  having a gate connected to an output terminal OUT 1  of the third inverter  37  and a source connected to the supply voltage VCC 1 . A NMOS transistor Q 24  has a gate connected to the output terminal OUT 1  of the third inverter  37 , a drain connected to a drain of the PMOS transistor Q 23 , and a source connected to a ground voltage GND 1 . 
     The first embodiment of ring oscillator of the present invention operates as follows. When a supply voltage VCC 1  is applied to the ring oscillator, the PMOS transistor Q 6  turns on and the current source IS 1  provides a current to the PMOS transistor Q 7  and transistor Q 11  that form a current mirror with the PMOS transistor Q 6 . 
     At the same time, the current flowing through the PMOS transistor Q 7  turns on the NMOS transistor Q 8 . The NMOS transistor Q 10 , mirroring the current from the NMOS transistor Q 8 , turns on and a current flows through the transistor Q 10 . The PMOS transistor Q 11  turns on and charges the capacitor C 2 . The charging time of the capacitor C 2  depends on the amount of current flowing through PMOS transistor Q 11  and the capacitance of the capacitor C 2 . 
     Initially, the voltage level of node A 5  is in a low state. The charging voltage of the capacitor C 2  is transmitted to node A 4  of the first inverter  35  through the PMOS transistor Q 13  of the first switch  33 . As the voltage stored in the capacitor C 2  increases, the voltage level of node A 4  changes from a low to a high state. When the voltage of node A 4  changes to a high state, node A 3  of the first inverter  35  changes to a low state. If the voltage of node A 3  changes to a low state, node A 5  of the second inverter  36  changes to a high state and, simultaneously, the output voltage of the third inverter  37  becomes low. 
     If node A 3  is in a low state, the NMOS transistor Q 14  of the first switch  33  turns off and the PMOS transistor Q 15  turns on. Furthermore, if node A 3  is in a low state, node A 5  is in a high state turning off the PMOS transistor Q 13  of the first switch  33  and turning on the NMOS transistor Q 16  of the second switch  34 . Therefore, both the PMOS transistor Q 13  and the NMOS transistor Q 14  of the first switch  33  turn off and both the PMOS transistor Q 15  and the NMOS transistor Q 6  turn on. 
     If node A 5  is in a high state, the PMOS transistor Q 9  of the charging/discharging circuit  32  turns off and the NMOS transistor Q 12  of the charging/discharging circuit  32  turns on charging the capacitor C 1  and discharging the capacitor C 2 . The charging time of the capacitor C 1  is determined by the amount of current flowing through the transistor Q 10  and the capacitance of the capacitor C 1 . The discharging time of the capacitor C 2  is determined by the amount of current flowing through the transistor Q 12  and the capacitance of the capacitor C 2 . 
     When the second switch  34  turns on, the voltage of node A 1  is transmitted to node A 4  through the second switch  34 . Therefore, if the PMOS transistor Q 9  turns off and node A 1  changes from a high to low state simultaneously, node A 4  changes from a high to low state and the output of the first inverter  35  changes node A 3  from a low to high state. Then the NMOS transistor Q 14  of the first switch  33  turns on and the PMOS transistor Q 15  of the second switch  34  turns off. 
     Furthermore, the output of the second inverter  36  changes node A 5  from a high to low state, the PMOS transistor Q 13  of the first switch  33  turns on, the NMOS transistor Q 16  of the second switch  34  turns off, the PMOS transistor Q 9  of the charging/discharging circuit  32  turns on, and the NMOS transistor Q 12  turns off. Thereafter, the first switch  33  turns on and the second switch  34  turns off. The voltage of node A 2  is transmitted to node A 4  through the first switch  33  repeating the above-described circuit operations. 
     The oscillating output signal OUT 1  is generated as shown FIG. 2 in accordance with the operation of the charging/discharging circuit  32 , the first switch  33 , the second switch  34 , the first inverter  35 , the second inverter  36 , and the third inverter  37 . 
     The inverting output circuit  2  generates the output signal OUT 2  by inverting the output signal OUT 1 . The duty cycle of the output signal OUT 2  is constant as shown in FIG.  2 . 
     The PMOS transistor Q 1  of the frequency adjusting circuit  3  forms a current mirror with the PMOS transistor Q 6  causing a current corresponding to the current source IS 1  to flow through PMOS transistor Q 1 . A voltage divider is formed at node A 6  between the first resistor R 1  and the second resistor R 2 . The voltage divider formed by the first and second resistor R 1  and R 2 , respectively, generate a reference voltage at node A 6  by dividing down the supply voltage VCC 1 . The reference voltage is provided to the gate of the PMOS transistor. The reference voltage at node A 6  is shown in FIG.  3 ( a ). The gate of the PMOS transistor Q 3  is provided with the external input voltage VIN 1 . The external input voltage VIN 1  is compared with the reference voltage at node A 6 . This comparison determines the amount of current flowing through the PMOS transistors Q 3  and Q 2 . 
     The current flowing through the PMOS transistor Q 2  flows through the NMOS transistor Q 4 . The amount of current flowing through the NMOS transistor Q 4  is substantially equal to the current flowing through the NMOS transistor Q 5  because NMOS transistor Q 5  forms a current mirror with the NMOS transistor Q 4 . The current is supplied to or from node A 1  of the charging/discharging means  32  according to the amount of current flowing through the NMOS transistor Q 5 . That is, an increase in the external input voltage VIN 1  decreases the current flowing through the PMOS transistor Q 3  and increases the current flowing through the PMOS transistor Q 2 . Since the amount of current flowing through both NMOS transistors Q 4  and Q 5  must be equal, an appropriate amount of current is provided from node A 1  of the charging/discharging circuit  32 . Therefore, the capacitor C 1  charges rapidly and the output signal OUT 1  has an increased frequency as shown in FIG.  3 ( b ). Conversely, if the external input voltage VIN 1  is lower than the voltage at node A 6 , the capacitor C 1  charges slowly and the output signal OUT 1  has a reduced frequency. Thus, if the external input voltage VIN 1  is high, the output signal OUT 1  has a high frequency. If the external input voltage VIN 1  is low, the output signal OUT 1  has a low frequency. Users can obtain output signals having a variable frequency by adjusting the external input voltage. 
     Since the capacitance of the capacitor C 2  and the amount of current flowing through the PMOS transistor Q 11  and the NMOS transistor Q 12  do not change in the first preferred embodiment, the duty cycle of the output signal OUT 1  is constant. 
     FIG. 4 is a circuit diagram of a ring oscillator having a variable frequency according to the second preferred embodiment of the present invention. Referring to FIG. 4, the ring oscillator of the second preferred embodiment includes the same configuration of an oscillating circuit  51  (oscillating circuit  1  in FIG. 1) and an inverting output circuit  52  (inverting output circuit  2  in FIG. 1) of the first preferred embodiment. However, the second embodiment of the ring oscillator includes a different configuration frequency adjusting circuit  53 . 
     The frequency adjusting circuit  53  includes a PMOS transistor Q 31  forming a current mirror with the PMOS transistor Q 35  of the current supply means. An NMOS transistor Q 32  has a drain connected to a drain of the PMOS transistor Q 31 , a gate applied with an external voltage VIN 2  and a source connected to ground voltage GND 2 . An NMOS transistor Q 33  has a drain and gate connected to the drain of the PMOS transistor Q 31  and a source connected to ground voltage GND 2 . An NMOS transistor Q 34  has a drain connected to the drain of the PMOS transistor Q 38  of the oscillating circuit  51 , a gate connected to the drain of the PMOS transistor Q 31 , and a source connected to ground voltage GND 2 . 
     The second embodiment ring oscillator operates as follows. The oscillating circuit  51  and the inverting output circuit  52  operate in the same manner explained above with reference to the first preferred embodiment. The operation of frequency adjusting circuit  53  is simpler than that of frequency adjusting circuit  3 . 
     Since the PMOS transistor Q 31  forms a current mirror with the PMOS transistor Q 35 , the current flowing through the PMOS transistor Q 31  is same as that of current source IS 2  of the oscillating circuit  51 . A voltage VIN 2  is externally input, as shown in FIG.  5 ( a ). If the voltage level of the external input voltage VIN  2  is high, the NMOS transistor Q 32  turns on. When this happens, most of the current flows through the NMOS transistor Q 32  and a small amount of current flows through the NMOS transistor Q 33 . The output signal OUT 3  is shown in FIG.  5 ( b ). Conversely, if the external input voltage VIN 2  is in a low state, the NMOS transistor Q 32  turns off. Hence, the current does not flow through the NMOS transistor Q 32  and flows through the NMOS transistor Q 33 . 
     Since the same amount of current that flows through the NMOS transistor Q 33  flows through the NMOS transistor Q 34  because of the current mirror formed therebetween, the current is input from node P 1  of the oscillating circuit  51 . As a result, the charging speed of the capacitor C 3  and thus the frequency of output signal OUT 3 , increases, as shown in FIG.  5 ( b ). The second preferred embodiment of the ring oscillator provides for two frequencies allowing easy implementation in an application circuit. 
     As described above, the present invention provides a ring oscillator having a variable frequency by adjusting the input voltage so that the ring oscillator can be used in various types of application circuits. 
     Having illustrated and described the principles of my invention in a preferred embodiment thereof, it should be readily apparent to those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. I claim all modifications coming within the spirit and scope of the accompanying claims.