Abstract:
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The invention relates to a semiconductor device, and more particularly, to a semiconductor device of using gate structure having different orientation ratio for achieving different threshold voltages. 
         [0003]    2. Description of the Prior Art 
         [0004]    In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers. 
         [0005]    Typically, threshold voltage in conventional planar metal gate transistors is adjusted by the means of ion implantation. With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Nevertheless, threshold voltages in current FinFET cannot be easily adjusted by using ion implantation. Hence, how to resolve this issue in today&#39;s FinFET architecture has become an important task in this field. 
       SUMMARY OF THE INVENTION 
       [0006]    According to a preferred embodiment of the present invention, a method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess. 
         [0007]    According to another aspect of the present invention, a method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; and forming a first work function layer, a second work function layer, and a third work function layer in the first recess, the second recess, and the third recess, in which the first work function layer, the second work function layer, and the third work function layer are formed by different deposition temperature. 
         [0008]    According to another aspect of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate; and a first gate structure, a second gate structure, and a third gate structure on the substrate and an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure, in which the orientation ratio of the first gate structure, the second gate structure, and the third gate structure are different from each other. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIGS. 1-3  illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention. 
           [0011]      FIGS. 4-6  illustrate a method for fabricating semiconductor device according to another embodiment of the present invention. 
           [0012]      FIG. 7  illustrates a method for fabricating semiconductor device according to another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Referring to  FIGS. 1-3 ,  FIGS. 1-3  illustrate a method for fabricating semiconductor device according to a preferred embodiment of the present invention. As shown in  FIG. 1 , a substrate  12 , such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided, and three transistor regions  18 ,  20 ,  22  are defined on the substrate. The three transistor regions  18 ,  20 ,  22  are preferably composed of same conductive type, such as PMOS regions or NMOS regions, and the transistor regions  18 ,  20 ,  22  are utilized for fabricating gate structures having different threshold voltages afterwards. At least a first fin-shaped structure  14  and an insulating layer (not shown) are formed on the substrate  12 , in which the bottom of the fin-shapes structure  14  is preferably enclosed by the insulating layer, such as silicon oxide to form a shallow trench isolation (STI). 
         [0014]    The formation of the fin-shaped structure  14  could be accomplished by first forming a patterned mask (now shown) on the substrate,  12 , and an etching process is performed to transfer the pattern of the patterned mask to the substrate  12 . Next, depending on the structural difference of a tri-gate transistor or dual-gate fin-shaped transistor being fabricated, the patterned mask could be stripped selectively or retained, and deposition, chemical mechanical polishing (CMP), and etching back processes are carried out to form an insulating layer surrounding the bottom of the fin-shaped structure  14 . Alternatively, the formation of the fin-shaped structure  14  could also be accomplished by first forming a patterned hard mask (not shown) on the substrate  12 , and then performing an epitaxial process on the exposed substrate  12  through the patterned hard mask to grow a semiconductor layer. This semiconductor layer could then be used as the corresponding fin-shaped structure  14 . In another fashion, the patterned hard mask could be removed selectively or retained, and deposition, CMP, and then etching back could be used to form an insulating layer to surround the bottom of the fin-shaped structure  14 . Moreover, if the substrate  12  were a SOI substrate, a patterned mask could be used to etch a semiconductor layer on the substrate until reaching a bottom oxide layer underneath the semiconductor layer to form the corresponding fin-shaped structure. If this means is chosen the aforementioned steps for fabricating the insulating layer could be eliminated. 
         [0015]    Next, a metal gate fabrication process could be conducted to form three metal gates on the substrate  12 , in which the fabrication of the metal gates could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, three dummy gates (not shown) composed of interfacial layer selected from the group consisting of SiO 2 , SiN, and SiON and polysilicon material could be first formed on the fin-shaped structure  14  and the insulating layer, and liner, lightly doped drain (LDD) (not shown), and spacer  24  are formed adjacent to the dummy gates. A source/drain region  26  and epitaxial layer (not shown) are then formed in the fin-shaped structure  14  and/or substrate  12  adjacent to two sides of the spacer  24 , a contact etch stop layer (CESL)  30  is formed on the dummy gates, and an interlayer dielectric (ILD) layer (not shown) composed of tetraethyl orthosilicate (TEOS) is formed on the CESL  30 . 
         [0016]    Next, part of the ILD layer  32  and CESL  30  are planarized and a selective dry etching or wet etching process is conducted by using etchants including ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the polysilicon layer from dummy gates for forming three recesses  38 ,  40 ,  42  in the ILD layer  32 . 
         [0017]    Next, the interfacial layer could be remove selectively and re-grown, and a high-k dielectric layer  44 , a bottom barrier metal (BBM) layer  46 , and a material layer  48  are formed sequentially on the ILD layer  32  to fill into the recesses  38 ,  40 ,  42 . 
         [0018]    In this embodiment, the high-k dielectric layer  44  is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer  44  may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) or a combination thereof. The BBM layer  46  could be a single-layered structure or a double-layered structure, and is preferably composed of TiN and/or TaN, but not limited thereto. 
         [0019]    The material layer  48  of this embodiment is preferably a material layer formed prior to the formation of work function layer, such as a BBM layer composed of TaN or TiN. Nevertheless, it should be noted that despite the material layer  48  is composed of a BBM layer in this embodiment, the material layer  48  could also be composed of a work function layer directly depending on the demand of the product, which is also within the scope of the present invention. 
         [0020]    If the material layer  48  were to be a work function layer, various compositions could be chosen for tuning the work function of the metal gate so that the device could be adapted in an NMOS or a PMOS transistor. For an NMOS transistor, the work function layer having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafniumaluminide (HfAl), or titanium aluminum carbide (TiAlC), but is not limited thereto. For a PMOS transistor, the work function layer having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but is not limited thereto. 
         [0021]    Next, a patterned hard mask, such as a patterned resist  50  is formed on the transistor regions  20  and  22 , and the patterned resist  50  is used as mask to perform a treatment on the material layer  48  exposed in the recess  38  for altering the surface energy of the material layer  48  so that the work function layer grown on the material layer  48  thereafter could have different orientation ratio. In this embodiment, the treatment process could include using gas to carry out a plasma bombardment on the material layer  48 , in which the gas utilized in the plasma bombardment is selected from the group consisting of ammonia, hydrogen, and nitrogen. 
         [0022]    Next, as shown in  FIG. 2 , the patterned resist  50  is stripped, another patterned resist  52  is formed to cover the transistor region  22 , and another treatment is conducted thereafter on the material layer  48  exposed in the recesses  38  and  40  by using the patterned resist  52  as mask. The parameters of the treatment, including gas content and amount of energy used could be the same as the ones used in the previous treatment process, but not limited thereto. 
         [0023]    Next, as shown in  FIG. 3 , the patterned resist  52  is stripped, a work function layer  34  and a low resistance metal layer  36  are formed sequentially on the material layer  48 , and a planarizing process is conducted to form three gate structures  54 ,  56 ,  58 . It should be noted that another barrier layer (not shown) could be formed between the work function layer  34  and low resistance metal layer  36 , in which the barrier layer could be selected from the group consisting of Ti, TiN, Ta, and TaN. The low resistance metal layer  36  could be selected from the group consisting of Cu, Al, W, TiAl, and CoWP. 
         [0024]    According to a preferred embodiment of the present invention, the gate structures  54 ,  56 ,  58  are composed of same conductive type, such as all being n-type gates or all being p-type gates. Since the material layer  48  within the recess  38  has been processed twice by two treatment processes, the material layer  48  within the recess  40  has been processes once by one single treatment process, and the material layer  48  within the recess  42  has not been processed by any treatment process, the work function layer  34  formed within each of the recesses  38 ,  40 ,  42  would reveal different orientation ratio so that each of the gate structures  54 ,  56 ,  58  could have different threshold voltages. For instance, the gate structure  54  being processed by two treatment processes becomes a low threshold voltage (LVT) gate, the gate structure  56  being processed by one treatment process becomes a standard threshold voltage (SVT) gate, and the gate structure  58  not being process by any treatment process becomes a high threshold voltage (HVT) gate. 
         [0025]    Referring to  FIGS. 4-6 ,  FIGS. 4-6  illustrate a method for fabricating semiconductor device according to another embodiment of the present invention. As shown in  FIG. 4 , a substrate  12 , such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided, and three transistor regions  18 ,  20 ,  22  are defined on the substrate. The three transistor regions  18 ,  20 ,  22  are preferably composed of same conductive type, such as PMOS regions or NMOS regions, and the transistor regions  18 ,  20 ,  22  are utilized for fabricating gate structures having different threshold voltages afterwards. Three dummy gates (not shown) could then be formed on the substrate  12  similar to  FIG. 1 , transistor elements such as source/drain region  26  is formed in the substrate  12 , an ILD layer  32  is formed to cover the dummy gates, and polysilicon material in the dummy gates are removed to form three recesses  38 ,  40 ,  42  in the transistor regions  18 ,  20 ,  22 . 
         [0026]    Next, a high-k dielectric layer  44  and a BBM layer  46  are formed on the ILD layer  32  to fill into the recesses  38 ,  40 ,  42 . The composition of the high-k dielectric layer  44  and BBM layer  46  could be the same as the ones disclosed in the aforementioned embodiment, and the details of which are not explained herein for the sake of brevity. 
         [0027]    Next, a work function layer (not shown) is formed on the transistor regions  18 ,  20 ,  22 , a patterned mask, such as a patterned resist  60  is covered on the transistor region  18 , and the patterned resist  60  is used as mask to remove part of the work function layer in the transistor regions  20 ,  22  for forming a work function layer  34  in the recess  38  of the transistor region  18 . 
         [0028]    Next, as shown in  FIG. 5 , after stripping the patterned resist  60  and forming another work function layer (not shown) in the transistor regions  18 ,  20 ,  22 , another patterned resist  62  is formed on the transistor region  20 , and the patterned resist  62  is used as mask to remove part of the work function layer in the transistor regions  18  and  22  for forming a work function layer  34  in the recess  40  of the transistor region  20 . 
         [0029]    Next, as shown in  FIG. 6 , aforementioned steps are repeated by stripping the patterned resist  62 , forming a work function layer (not shown) on the transistor regions  18 ,  20 ,  22 , forming another patterned resist (not shown) on the transistor region  22 , and then using the patterned resist as mask to remove part of the work function layer in the transistor regions  18 ,  20  for forming another work function layer  34  in the recess  42  of the transistor region  22 . After stripping the patterned resist from the transistor region  22 , a low resistance metal layer  36  is formed on the work function layer  34  and a planarizing process is conducted to form three gate structures  54 ,  56 ,  58 . 
         [0030]    It should be noted that the gate structures  54 ,  56 ,  58  of this embodiment are preferably composed of same conductive type, such as all being n-type gates or all being p-type gates. Moreover, the deposition processes conducted in  FIGS. 4-6  are preferably accomplished by using different temperature with corresponding bias voltages to form work function layers consisting of same material while demonstrating different threshold voltages. For instance, the work function layers  34  in recesses  38 ,  40 ,  42  are formed by different deposition temperatures respectively, and the work function layers  34  in each of the recesses  38 ,  40 ,  42  preferably have different orientation so that each of the gate structures  54 ,  56 ,  58  would have different threshold voltage. For fabricating p-type gate structures, gate structures fabricated by lower deposition temperature preferably constitute a low threshold voltage (LVT) gate, whereas gate structures fabricated by higher deposition temperatures preferably constitute a standard threshold voltage (SVT) gate or a high threshold voltage (HVT) gate. 
         [0031]    Referring to  FIG. 7 ,  FIG. 7  illustrates a method for fabricating semiconductor device according to another embodiment of the present invention. As shown in  FIG. 7 , three dummy gates (not shown) are formed on a substrate  12  similar to  FIG. 1 , transistor elements such as source/drain region  226  is formed in the substrate  12 , an ILD layer  32  is covered on the dummy gates, and polysilicon material are removed from the dummy gates to form three recesses (not shown) in transistor regions  18 ,  20 ,  22 . It should be noted that the transistor regions  18  and  20  of this embodiment are composed of same conductive type while the transistor region  22  is composed of different conductive type. For instance, the transistor regions  18  and  20  could be PMOS region while the transistor region  22  could be a NMOS region. 
         [0032]    Next, a high-k dielectric layer  44  and a BBM layer  46  are formed on the ILD layer  32  to fill into the recesses  38 ,  40 ,  42 . The composition of the high-k dielectric layer  44  and BBM layer  46  could be the same as the ones disclosed in the aforementioned embodiment, and the details of which are not explained herein for the sake of brevity. 
         [0033]    Next, p-type work function layers of different thickness are formed in the recesses of the transistor regions  18 ,  20 ,  22 . For instance, a first p-type work function layer (not shown) is formed on transistor regions  18 ,  20 ,  22 , and a patterned mask (not shown) such as a patterned resist is covered on the transistor regions  18  and  20 . An etching process is then conducted by using the patterned resist as mask to remove the p-type work function layer from the transistor region  22  so that the remaining first p-type work function layer (not shown) is formed on the transistor regions  18 ,  20 . 
         [0034]    After stripping the patterned resist, a second p-type work function layer (not shown) is formed in the recesses of the transistor regions  18 ,  20 ,  22 . This forms a thicker p-type work function layer  64  on the transistor regions  18  and  20  and a thinner p-type work function layer  64  on the transistor region  22 . A n-type work function layer  66  and a low resistance metal layer  68  are then deposited sequentially on the p-type work function layer  64  of the transistor regions  18 ,  20 ,  22 , and a planarizing process is conducted to form three gate structures  54 ,  56 ,  58 . 
         [0035]    It should be noted that the p-type work function layer  64  deposited on the transistor region  22  (or NMOS region) is preferably thinner than the p-type work function layer  64  deposited on the transistor regions  18  and  20  (or PMOS regions), or the p-type work function layer  64  of the PMOS regions are thicker than the p-type work function layer  64  of the NMOS region. By forming p-type work function layer of different thickness in the two transistor regions respectively, it would be desirable to allow the gate structures  54  and  56  of PMOS region and the gate structure  58  of NMOS region to have different threshold voltage. Moreover, the p-type work function layer  64  of the PMOS region and the p-type work function layer  64  of the NMOS region could also be composed of same material or different material, which is also within the scope of the present invention. 
         [0036]    Overall, the present invention preferably performs a treatment process on a work function layer directly or a material layer formed prior to work function layer while fabricating three or more gate structures. This creates gate structures with different orientation ratio so that threshold voltage of each of the gate structures would be different. According to a preferred embodiment of the present invention, the treatment process conducted on the work function layer or the material layer formed prior to the work function layer include plasma bombardment or deposition temperature adjustment. Alternatively, gate structures having different threshold voltage could also be achieved by adjusting the thickness of work function layer in each transistor region. 
         [0037]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.