Abstract:
A control circuit (10) controls a voltage controlled oscillator (15) to cause the signal at the output of the oscillator to have slopes of frequency variation in accordance with biphase encoded data to be transmitted. The control circuit (10) limits abrupt frequency shifts in the oscillator output signal by inverting a sign multiplying the slope of frequency variation, utilizing an amplifier (50) with a controllable inversion state, in response to whether the state of the data to be transmitted, and a state, indicative of whether a frequency control voltage exceeds a zero threshold at sampling instants synchronous with the biphase data, are the same or different.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to an information transmission arrangement using frequency modulation, the arrangement being formed by at least one sending unit comprising: 
     a sending circuit built up around an oscillator having a frequency control input, for sending an information transmission wave, 
     a frequency control circuit to supply to said control input signals having frequency-variation amplitudes and variation slopes depending on the information to be transmitted, 
     and at least one receiving unit comprising: 
     a receiving circuit to receive said wave and produce a signal to be demodulated, 
     a demodulation circuit to receive the signal to be demodulated and recover said information for supply to a user circuit. 
     Such arrangements are well known. For example, on this subject the reader be referred to the article by G. DAVID et al. entitled &#34;Transmission radioelectrique au moyen d&#39;une modulation lineaire en frequence&#34; published in the journal L&#39;ONDE ELECTRIQUE, March 1971, Vol. 51, Fascicle 3, pp. 233-242. 
     In this known arrangement, the information constituted by bits having the values &#34;1&#34; and &#34;0&#34; is transmitted by assigning slopes having the value &#34;p&#34; to the &#34;1&#34; bits and slopes having the value &#34;-p&#34; to the &#34;0&#34; bits. 
     The above article deals with all the advantages of this type of transmission link: more specifically, resistance to jamming and improvement of the signal-to-noise ratio at the receiving end when using correlation techniques. However, with an arrangement of this type one is confronted with disturbing effects produced at each discontinuity of the frequency occurring abruptly between the successive bits having the same value. 
     SUMMARY OF THE INVENTION 
     The present invention proposes an arrangement of the type mentioned in the preamble which avoids any discontinuity in the frequency variations, whatever the bit sequence to be transmitted may be. 
     To this purpose an arrangement is characterized in that the control circuit comprises means for changing the slope sign controlled by means for detecting amplitude variations. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The following description together with the accompanying drawings, all given by way of non-limiting example, will make it better understood how the invention can be realized. In the drawings: 
     FIG. 1 shows the diagram of a sending unit forming part of the arrangement according to the invention; 
     FIG. 2 shows the shape of signals which are present inside the sending unit of FIG. 1; 
     FIG. 3 shows the diagram of a receiving unit forming part of an arrangement according to the invention; 
     FIG. 4 shows the shape of signals present inside the receiving unit of FIG. 3; 
     FIG. 5 shows an arrangement comprising transceiver units each constituted by a sending unit and a receiving unit shown in FIGS. 1 and 3. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In FIG. 1 is shown a sending unit suitable for use in an arrangement according to the invention. Reference numeral 1 indicates the input terminal to which a signal A representing the data to be transmitted is applied, for example, a sequence of &#34;1&#34; and &#34;0&#34; like: 
     1, 0, 0, 0, 1, 1, . . . 
     as represented in FIG. 2, line A. In order to facilitate the recovery of the data after of their transmission, these data are encoded in a biphase code by the encoder 3 by means of a signal F from a frequency doubler 5 doubling the frequency of the clock signals H applied to the terminal 7 and accompanying the data to terminal A. The biphase code thus formed is represented at B in FIG. 2. This signal develops from -V to +V Volts. Each of these values will be transmitted by means of a variable slope frequency modulation. The signals B are applied to a freqency control circuit 10 which produces, in response to the signals B, the signal at the control input 12 of an oscillator 15 whose frequency varies in response to the voltage applied to its control input 12. An aerial 17 sends a wave 18 produced by the oscillator 15. 
     The receiving unit, shown in FIG. 3, comprises a receiving aerial 20 to capture wave 18 so that receiving circuit 22 can produce a signal which is easy to demodulate. The circuit effects a frequency change obtained by means of a mixer 25 and an oscillator 27 and an intermediate-frequency amplification provide by an amplifier 29. The output signals R of this circuit 22 are applied to a demodulation circuit 35 which applies the demodulated signals to an output terminal 37 and the clock signals correpsonding to these demodulated signals to terminal 38. 
     The modulation used by the arrangement according to the invention is a frequency modulation which makes a slope p1 of frequency variation dF1 for a period of time dt1 correspond to a first signal value B (+V): ##EQU1## and a slope p2 of a frequency variation dF2 for a period of time dt2 correspond to a second signal value B (-V): ##EQU2## 
     According to the invention, in order to avoid frequency discontinuities occurring at the changes of the slopes, the control circuit 10 (FIG. 1) comprises means to change the slope sign which are constituted by a programmable amplifier 50 whose gain may assume two values +1 and -1 in response to logic signals &#34;1&#34; and &#34;0&#34; respectively, applied to its programming input 51. The input of this amplifier receives a signal C from a summing circuit 55 which adds a voltage (1/5)V to the signal B. The signal D at the output of the amplifier 50 is applied to an integrating circuit 58 supplying a signal E in the direction of the frequency control input 12 of the osciallator 15. This signal is a voltage Vf varying from -Vf a  to +Vf b  volts. This corresponds, according to a linear relationship, to frequencies f o  -f a  and f o  +f b , where f o  corresponds to a zero voltage. The signal E is also supplied to the input of a threshold circuit 60 which produces a logic signal &#34;0&#34; at its output for a negative voltage applied to its input and a logic signal &#34;1&#34; for a positive or zero voltage. A D-flip-flop 62 receives at its data input the signal produced by the circuit 60 and at its clock input the signal F. The output signal of this flip-flop is applied to the input of the programming input 51 of the amplifier 50 via an EXCLUSIVE-OR gate 63 also receiving a signal from a second threshold circuit 64 whose input receives the signal C. This threshold circuit 64 produces a logic signal &#34;0&#34; for a negative voltage applied to its input and a logic signal &#34;1&#34; for a positive or zero voltage. 
     Now it is possible to explain the operation of the control circuit 10. Reference is made to FIG. 2 where signal B is examined; this develops from +V to -V and it is proposed to associate to the value +V a variation slope p1 and to the value -V a variation slope p2, p1 and p2 being considered as absolute values. 
     By means of the summing circuit 55 the levels are shifted by (1/5)V such that when the signal B is equal to +V the signal C is equal to (6/5)V and when the signal B is equal to -V the signal C is equal to -(4/5)V. The rest of the arrangement will make the values (6/5)V and -(4/5)V correspond proportionally to the slopes p1 and p2: 
     
         p1=±k(6/5).V 
    
     
         p2=±k(4/5).V 
    
     The choice of the signs + or - specifically depends on the signal applied to the contoller 51 and k is a proportionality constant. 
     The instant t 0  is considered at which the voltage is assumed to be Vf&gt;0. At this instant an active edge of the signal F appears; this causes a value &#34;1&#34; coming from the circuit 60 to be written into the flip-flop 62. The gate 63, also receiving a signal &#34;1&#34; from the circuit 64, thus produces a &#34;0&#34;. The amplifier 50 is put in the inverting position so that the signal D assumes the value (-6/5).V corresponding to the value of the signal C. The signal E linearly develops from a positive value Vf to a negative value between the instants t 0  and t 1 , the latter occurring when the next active edge of the clock signal F appears. Since the value E is negative before instant t 1 , the amplifier 50 is put in the inverting position after this instant because the EXCLUSIVE-OR gate produces a signal of the value &#34;0&#34; in response to signals &#34;0&#34; from the flip-flop 62 and the threshold circuit 64, respectively. The voltage E develops with the slope p2 from a negative voltage to an other, positive voltage at the instant t 2  where an active edge of the signal F occurs. After this instant the signal at the output of the gate 63 becomes &#34;1&#34; because the signals at the outputs of the elements 62 and 64 become equal to &#34;1&#34; and &#34;0&#34;, respectively. At the instant t 3  the voltage E is negative which causes the signal at the output of the flip-flop 62 to be &#34;0&#34; and, since the signal C becomes positive, at this instant the amplifier 50 is put in the non-inverting position so that the voltage E becomes positive again after a period of time Δt and so on. The sequel of the argumentation could be given by means of that which has been set forth above. It is to be noted that the voltage Vf could never exceed the values Vf b  and -Vf a  during the selected values of the edges p1 and p2 and the amplitude values of the signal C. 
     In FIG. 3 is shown diagrammatically the structure of the demodulation circuit 35. It comprises a delay line 100 to delay the signal R at the output of the circuit 22 by τ. A mixer 102 carriers out the mixing of the signals R and S (at the output of line 100). 
     In FIG. 4a the frequency variations of the signals R and S are represented; it can be shown that the signal T from the mixer 102 produces signals of frequency ff1 and ff2 representing the slopes p1 and p2 according to: 
     
         ff1=p1.τ 
    
     
         ff2=p2.τ 
    
     Fig. 4b shows the corresponding frequency variations of the signal T. A conventional FSK receiver 105 connected to the output of the mixer 102 restores the data at the terminal 37 and the clock signal at the terminal 38. 
     FIG. 5 shows how such an arrangement can alternately operate in the send and receive modes. In this Figure are shown two transceiver units 200 and 201 having identical structures. Only unit 200 is shown in detail. As for its sending part it comprises a control circuit 202 of an identical structure to that of circuit 10 receiving already biphase-encoded data. The output signal of this circuit 202 is applied to the frequency control input of a send oscillator 204 via a switch circuit 205 in the send position (E). An aerial 207 transmits the wave generated in response to the output signals of the oscillator 204. 
     The receiving part comprises a receiving aerial 210, a mixer 212, an intermediate-frequency amplifier 215 and an FSK receiver 220 to recover the data. In this arrangement the send oscillator 204 is also used as a local oscillator for the receiving part. To this purpose, a directional coupler 230 derives a part of the wave at the output of the oscillator 204 whereas its frequency control signal receives a fixed voltage via the switch circuit 205 which has been put in the receive position (R). 
     To illustrate the above explanation, the following orders of magnitude are given: 
     
         carrier wave frequency 18: ˜55 GHz 
    
     
         dF1˜180 MHz 
    
     
         dF2˜120 MHz 
    
     
         ff1=18 MHz 
    
     
         ff2=12 MHz 
    
     for τ=50 ns and dt1=dt2=Δt=0.5 μs. 
     Although an example has been described in which the biphase code is used for transmitting the data, it will be evident that this invention also covers any further encoding methods: HDB3 codes or the like, codes obtained after scrambling, etc.