Abstract:
A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Description:
BACKGROUND OF THE INVENTION 
     The present invention generally relates to semiconductor devices, more particularly to packaging of semiconductor devices, and more particularly to a package having low electrical resistance and inductance. 
     Power semiconductor packages have evolved from through hole to surface mounted packages with the evolution of printed circuit board technology. Surface mounted packages generally include a lead frame on which a semiconductor device is mounted. The semiconductor device and a portion of the lead frame are generally encapsulated with a resin material. In a leaded package, lead terminals extend outside the resin body and include bonding pads for providing a wire bond connection from the semiconductor device to the lead terminal. 
     Major considerations in the packaging of semiconductor devices include high thermal dissipation, low parasitic inductance, low electrical resistance between the semiconductor device and the circuit environment, good reliability in terms of thermal cycling and thermal shock/fatigue, and minimal consumption of circuit board space. 
     By way of illustration and with reference to  FIG. 1 , a conventional semiconductor package generally designated  1  includes a lead frame generally designated  7  having a lead frame pad  10  to which is coupled a die  8 . A portion of the lead frame  7  may be molded in a resin body  2 . In this embodiment, the die  8  embodies a MOSFET device and the lead frame  7  includes a source terminal  18 , a gate terminal  26 , and a drain terminal  11 . Source terminal  18  of the lead frame  7  includes a plurality of separate source lead frame leads  18   a  external to the resin body  2  and a plurality of separate internal source bonding areas  16  where bonding wires  6  are bonded. Drain terminal  11  includes a plurality of separate drain lead frame leads  11   a  which are connected to the lead frame pad  10 . The gate terminal  26  is connected to an internal gate bonding area  20  which in turn is connected to a gate pad  17  by means of wire  28 . 
       FIG. 2  illustrates a top view of another conventional semiconductor package generally designated  4  including a lead frame generally designated  9 . In this embodiment, in lieu of a plurality of separate source bonding areas  16  as shown in  FIG. 1 , the source bonding areas  16  are joined to form a single source bonding area  30  for bonding wires  6  to die  8 . As with the embodiment of  FIG. 1 , the separate source lead frame leads  18   a  and the separate lead frame drain leads  11   a  are separate narrow metal strips that radiate externally from the resin body  2  and are adapted to be inserted into the same receptacle location on a printed circuit board as the device shown in  FIG. 1 . 
     Similar to the embodiment of  FIG. 1 , the lead frame  9  has die  8  disposed thereon and provides a generally narrow border frame around the perimeter of die  8 . Moreover, the bonding area  20  of gate  26  is coupled via wire  28  to gate pad  17  formed at a nearest corner. In the prior art embodiment, the source and gate bonding areas  16 ,  30  and  20  respectively share the same left side of the die  8 . Likewise, the source leads  18   a  and the gate lead  26  radiate from the same left side. 
     With reference to  FIG. 3 , a cross sectional view of a conventional semiconductor package such as semiconductor package  1  is shown. Die  8  is shown having a top surface  22  to which bonding wire  6  is coupled. Die  8  may be coupled to lead frame pad  10  by means of conventional material  32 . As is conventional in the art, lead frame generally designated  7  has a thickness of about 8 mils requiring that bonding wires  6  be made from gold or copper. Furthermore, source bonding area  16  is conventionally disposed above top surface  22  requiring a relatively long bonding wire  6 . As is well known in the art, long bonding wires  6  generally provide for increased electrical resistance and source inductance, particularly in high frequency applications. 
     Referring now to  FIG. 4 , a top view of a conventional dual-die semiconductor package generally designated  5  having a lead frame generally designated  13  is shown. The dual-die semiconductor package  5  includes a pair of dies  40   a  and  40   b  mounted on a lead frame pad  42  and molded in a resin body  2 . A first source terminal  48   a  includes a first source terminal bonding area  46   a  distributed along a left side of the first die  40   a . The first source terminal bonding area  46   a  is connected to the first die  40   a  via bonding wires  41   a . A first gate terminal  44   a  includes a first gate bonding area  43   a  that shares the left side of the first die  40   a  and is connected to the first die  40   a  via bonding wire  45   a . A plurality of first drain terminals  47   a  are coupled to lead frame pad  42 . 
     A second source terminal  48   b  includes a second source terminal bonding area  46   b  distributed along a left side of the second die  40   b . The second source terminal bonding area  46   b  is connected to the second die  40   b  via bonding wires  41   b . A second gate terminal  44   b  includes a second gate bonding area  43   b  that shares the left side of the second die  40   b  and is connected to the second die  40   b  via bonding wire  45   b . A plurality of second drain terminals  47   b  are coupled to lead frame pad  42 . 
     With reference to  FIG. 5 , a semiconductor package generally designated  50  is shown. Semiconductor package  50  is described in commonly assigned application Ser. No. 10/189,333 which is incorporated herein in its entirety by reference. Semiconductor package  50  includes a lead frame generally designated  51  having an “L” shaped source bonding area  52 . The “L” shaped source bonding area  52  provides for an increase in the number of source bonding wires  53  interconnecting a source lead  54  with a die  55 . Additionally, the distance between bonding wires  53  is not compromised thereby providing lower electrical resistance and inductance. 
     A prior art leaded package is disclosed in U.S. Pat. No. 6,291,262 entitled “Surface Mount TO-220 Package and Process for the Manufacture Thereof”. The disclosed package includes leads which are bent within the molded housing and formed prior to molding the housing around the lead frame. The bend is located inside the package body to minimize mechanical stresses on the package body. A lead frame is formed of a material having a single gauge. 
     Another prior art leaded package is disclosed in U.S. Pat. No. 6,211,462 entitled “Low Inductance Power Package for Integrated Circuits”. The package includes a flat lead frame with internal leads formed upward to be in very close proximity to the lead frame pad. The external leads are flat and extend beyond the package edge so that good solder connections to a printed circuit board can be made and inspected. 
     As can be seen, there remains a need in the art for a semiconductor package that minimizes electrical resistance and inductance. Such a semiconductor package also preferably allows for reduced package height and improved thermal resistance properties. 
     SUMMARY OF THE INVENTION 
     In accordance with one aspect of the invention, a semiconductor package includes a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame. 
     In accordance with another aspect of the invention, a semiconductor package includes a relatively thick lead frame having a plurality of leads and a pair of lead frame pads, each lead frame pad including a die coupled thereto, bonding wires connecting each die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame. 
     In accordance with yet another aspect of the invention, a semiconductor package housing an electronic device includes a relatively thick lead frame having a thickness greater than 8 mils and including a plurality of leads and a lead frame pad, the lead frame pad having the electronic device coupled thereto, bonding wires connecting the electronic device to the plurality of leads, the bonding wires being aluminum wires having a thickness up to 20 mils, and a resin body encapsulating the electronic device, bonding wires and at least a portion of the lead frame. 
     These and other features, aspects and advantages of the present invention will become better understood with reference to the following drawings, description and claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is top view of a prior art semiconductor package; 
         FIG. 2  is top view of another prior art semiconductor package; 
         FIG. 3  is a cross sectional view of a conventional semiconductor package; 
         FIG. 4  is a top view of a prior art dual-die semiconductor package; 
         FIG. 5  is a top view of a prior art semiconductor package; 
         FIG. 6A  is a top view of a semiconductor package in accordance with the present invention; 
         FIG. 6B  is a cross sectional view of the semiconductor package of  FIG. 6A  in accordance with the present invention; 
         FIG. 6C  is a bottom view of the semiconductor package of  FIG. 6A  in accordance with the present invention; 
         FIG. 7A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 7B  is a cross sectional view of the semiconductor package of  FIG. 7A  in accordance with the present invention; 
         FIG. 7C  is a bottom view of the semiconductor package of  FIG. 7A  in accordance with the present invention; 
         FIG. 8A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 8B  is a cross sectional view of the semiconductor package of  FIG. 8A  in accordance with the present invention; 
         FIG. 8C  is a bottom view of the semiconductor package of  FIG. 8A  in accordance with the present invention; 
         FIG. 9A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 9B  is a cross sectional view of the semiconductor package of  FIG. 9A  in accordance with the present invention; 
         FIG. 9C  is a bottom view of the semiconductor package of  FIG. 9A  in accordance with the present invention; 
         FIG. 10A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 10B  is a cross sectional view of the semiconductor package of  FIG. 10A  in accordance with the present invention; 
         FIG. 10C  is a bottom view of the semiconductor package of  FIG. 10A  in accordance with the present invention; 
         FIG. 11A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 11B  is a cross sectional view of the semiconductor package of  FIG. 11A  in accordance with the present invention; 
         FIG. 11C  is a bottom view of the semiconductor package of  FIG. 11A  in accordance with the present invention; 
         FIG. 12A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 12B  is a cross sectional view of the semiconductor package of  FIG. 12A  in accordance with the present invention; 
         FIG. 12C  is a bottom view of the semiconductor package of  FIG. 12A  in accordance with the present invention; 
         FIG. 13  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 14A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 14B  is a cross sectional view of the semiconductor package of 
         FIG. 14A  in accordance with the present invention; 
         FIG. 15  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 16  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 17  is a cross sectional view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 18  is a cross sectional view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 19  is a cross sectional view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 20  is a cross sectional view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 21A  is a cross sectional view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 21B  is a top view of the semiconductor package of  FIG. 21A  in accordance with the present invention; 
         FIG. 21C  is a cross sectional view of the semiconductor package of  FIG. 21A  in accordance with the present invention; 
         FIG. 22A  is a top view of an alternative embodiment of a semiconductor package in accordance with the present invention; 
         FIG. 22B  is a cross sectional view of the semiconductor package of  FIG. 22A  in accordance with the present invention; and 
         FIG. 22C  is a bottom view of the semiconductor package of  FIG. 22A  in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following detailed description is of the best modes of carrying out the invention. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention, since the scope of the invention is best defined by the appended claims. 
     The present invention generally provides a semiconductor package having a lead frame formed of a single gauge material having a thickness greater than the conventional 8 mils. Advantageously, a thicker lead frame facilitates the bonding of larger diameter aluminum bonding wires. The use of aluminum bonding wires decreases package resistance dramatically over conventional gold wire configurations. Bonding wires may be up to 20 mils in diameter. A thicker lead frame material further provides for improved package thermal behavior by facilitating heat flow laterally out a drain lead. This is so even in a case where a bottom portion of lead frame pad is exposed. Further, a source bonding area and a gate bonding area may be disposed at a substantially same height as a height of a die. In this manner, a short length of bonding wires may be used to thereby reduce electrical resistance and inductance. 
     With reference to  FIG. 6A , a semiconductor package generally designated  600  may include a lead frame generally designated  630  having a lead frame pad  602  to which may be coupled a die  601 . A portion of the lead frame  630  may be molded in a resin body  608 . The lead frame  630  may include a source lead  616 , a gate lead  612 , and a drain lead  626 . Source lead  616  may be disposed externally of resin body  608  and coupled to an internal source bonding area  618  which in turn may be coupled to a device source (not shown) by means of bonding wires  610 . Source lead  616  may be formed as a single lead to facilitate the use of a maximum number of bonding wires  610  to thereby reduce on-resistance and inductance. Drain lead  626  may be connected to the lead frame pad  602 . Gate lead  612  may be connected to an internal gate bonding area  620  which in turn may be connected to a gate pad  627  by means of wire  606 . A source locking hole  614  and a drain locking hole  624  may be formed in source lead  616  and drain lead  626  respectively. Locking notches  628  may be formed in drain lead  626 . 
     With reference to  FIG. 6B , lead frame  630  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. Advantageously, a thicker lead frame  630  facilitates the bonding of larger diameter aluminum bonding wires  610  and  606  and/or a greater number of bonding wires  610  and  606 . The use of aluminum bonding wires  610  and  606  decreases package inductance and resistance dramatically over conventional gold wire configurations. Bonding wires  610  and  606  may be up to 20 mils in diameter. A thicker lead frame material further provides for improved package thermal behavior by facilitating heat flow laterally out drain lead  626 . This is so even in a case where a bottom portion  650  of lead frame pad  602  is exposed as shown in  FIG. 6C . 
     With continued reference to  FIG. 6B , source bonding area  618  and gate bonding area  620  (not shown) may be disposed at a substantially same height as a height of die  601 . In this manner, a short length of bonding wires  610  and  606  may be used to thereby reduce electrical resistance and inductance. 
     With reference to  FIG. 7A ,  FIG. 7B , and  FIG. 7C , a second alternative embodiment of the present invention generally designated  700  is shown. A die  701  may be bonded to a lead frame pad  752 . Source lead  716  and gate lead  712  may be configured in similar fashion to source lead  616  and gate lead  612  as in the embodiment shown in  FIG. 6A . A source locking hole  714  may be formed in source lead  716 . A drain lead  756  may be connected to lead frame pad  752 . Locking notches  728  may be formed in drain  756  to secure leadframe  752  to resin body  708 . A notch  760  may be formed along a length of drain lead  756  on a bottom portion  750  of lead frame pad  752 . This embodiment advantageously provides for a means of holding the semiconductor package  700  during solder reflow. Lower inductance and resistance is achieved in the embodiment by straight current flow through drain lead  756  and thick and/or a greater number of bonding wires  710  and  706 . As in the embodiment shown in  FIG. 6 , high heat dissipation is achieved by exposed bottom portion  750 . 
     A third alternative embodiment of the present invention generally designated  800  including a lead frame generally designated  830  is shown in  FIG. 8A ,  FIG. 8B , and  FIG. 8C . Semiconductor package  800  may be implemented as an isolated dual die device. A pair of lead frame pads  872 A and  872 B may be provided, each lead frame pad  872 A and  872 B having bonded thereto devices  870 A and  870 B respectively. Leadframe  830  may include a source lead  876 A, a gate lead  812 A, and drain lead  886 A. Leadframe  830  may further include a source lead  876 B, a gate lead  812 B, and drain lead  886 B. Locking holes  814 A and  814 B may be formed in drain lead  886 A and  886 B respectively. As shown in  FIG. 8B , semiconductor package  800  may include a lead frame  830  formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  830  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding pads  878 A and  878 B and gate bonding pads  820 A and  820 B may be disposed at a substantially same height as a height of dice  870 A and  870 B. In this manner, a short length of bonding wires  810 A,  806 A,  810 B, and  806 B may be used to thereby reduce electrical resistance and inductance. 
     A fourth alternative embodiment of the present invention generally designated  900  is shown in  FIG. 9A ,  FIG. 9B , and  FIG. 9C . In contrast to semiconductor package  800 , semiconductor package  900  may include a notch  950 A formed along a length of lead frame pad  992 A on a bottom surface  960 A thereof and a notch  950 B formed along a length of lead frame pad  992 B on a bottom surface  960 B thereof. As noted with reference to semiconductor package  700 , notches  950 A and  950 B may provide for a means of holding the semiconductor package  900  during solder reflow. Lower inductance and resistance is achieved in the embodiment by straight current flow through drain leads  996 A and  996 B. 
     With reference to  FIG. 10A ,  FIG. 10B , and  FIG. 10C , a fifth alternative embodiment of the present invention generally designated  1000  is shown. Semiconductor package  1000  may include a lead frame generally designated  1030  having a lead frame pad  1098  to which may be coupled a die  1001 . A portion of the lead frame  1030  may be molded in a resin body  1008 . The lead frame  1030  may include a source lead  1016 , a gate lead  1012 , and a drain lead  1099 . Source lead  1016  may be disposed externally of resin body  1008  and coupled to an internal source bonding area  1018  which in turn may be coupled to a device source (not shown) by means of bonding wires  1010 . Drain lead  1099  may be connected to the lead frame pad  1098 . Gate lead  1012  may be connected to an internal gate bonding area  1020  which in turn may be connected to a gate pad  1027  by means of wire  1006 . A source locking hole  1024  and a drain locking hole  1026  may be formed in source lead  1016  and drain lead  1099  respectively. Locking notches  1028  may be formed in drain lead  1099 . With particular reference to  FIG. 10B  and  FIG. 10C , a bottom portion  1009  of lead frame pad  1098  may be encapsulated in resin body  1008  by resin portion  1011 . 
     Lead frame  1030  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1030  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding area  1018  and gate bonding area  1020  may be disposed at a substantially same height as a height of die  1001 . In this manner, a short length of bonding wires  1010  and  1006  may be used to thereby reduce electrical resistance and inductance. 
     A sixth alternative embodiment of the present invention generally designated  1100  is shown in  FIG. 11A ,  FIG. 11B , and  FIG. 11C . Semiconductor package  1100  may include a lead frame generally designated  1150 . Lead frame  1150  may include a lead frame pad  1108  having a die  1101  coupled thereto. A portion of lead frame  1150  may be molded in resin body  1109 . The lead frame  1150  may include a pair of source leads  1116 A and  1116 B, a gate lead  1112 , and a drain lead comprising the lead frame pad  1108 . Source leads  1116 A and  116 B may be disposed opposite one another and externally of resin body  1109  and coupled to internal source bonding areas  1118 A and  1118 B which in turn may be coupled to a device source (not shown) by means of bonding wires  1110 A and  1110 B. Gate lead  1112  may be connected to internal gate bonding area  1120  which in turn may be connected to a gate pad  1127  by means of bonding wire  1106 . A source locking hole  1124 A may be formed in source lead  1116 A and source locking holes  1124 B may be formed in source lead  1116 B. 
     Lead frame  1150  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1150  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding areas  1118 A and  1118 B and gate bonding area  1120  may be disposed at a substantially same height as a height of die  1101 . In this manner, a short length of bonding wires  111 A,  1110 B, and  1106  may be used to thereby reduce electrical resistance and inductance. Further, a greater number of source bonding wires  1110 A and  1110 B reduces electrical resistance and inductance. 
     With reference to  FIG. 12A ,  FIG. 12B , and  FIG. 12C , a seventh embodiment of the present invention generally designated  1200  is shown. Semiconductor package  1200  may include a lead frame generally designated  1250 . Lead frame  1250  may include a lead frame pad  1208  having a die  1201  coupled thereto. A portion of lead frame  1250  may be molded in resin body  1209 . The lead frame  1250  may include a pair of source leads  1216 A and  1216 B, a gate lead  1212 , and a drain lead comprising the lead frame pad  1208 . Source leads  1216 A and  1216 B may be disposed opposite one another and externally of resin body  1209  and stitch bonded to internal source bonding areas  1218 A and  1218 B which in turn may be stitch bonded to a device source (not shown) by means of bonding wires  1210 . Gate lead  1212  may be connected to internal gate bonding area  1220  which in turn may be connected to a gate pad  1227  by means of bonding wire  1206 . A source locking hole  1224 A may be formed in source lead  1216 A and source locking holes  1224 B may be formed in source lead  1216 B. This embodiment advantageously provides for reduced electrical resistance by reducing metal spreading resistance at a die surface  1260  and providing uniform current distribution. 
     Lead frame  1250  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1250  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding areas  1218 A and  1218 B and gate bonding area  1220  may be disposed at a substantially same height as a height of die  1201 . In this manner, a short length of bonding wires  1210  and  1206  may be used to thereby reduce electrical resistance and inductance. 
     With reference to  FIG. 13  an eighth alternative embodiment of the present invention generally designated  1300  is shown. Semiconductor package  1300  may be implemented as a common drain dual die device. Semiconductor package  1300  may include a lead frame generally designated  1360 . Lead frame  1360  may include a lead frame pad  1368  having a pair of devices  1330 A and  1330 B bonded thereto. Device  1330 A may include a source lead  1316 A, a gate lead  1312 A, and shared drain lead comprising lead frame pad  1368 . Device  1330 B may include a source lead  1316 B, a gate lead  1312 B, and shared drain lead. Source locking holes  1340 A and  1340 B may be formed in source leads  1316 A and  1316 B respectively. 
     Lead frame  1350  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1350  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding areas  1318 A and  1318 B and gate bonding areas  1320 A and  1320 B may be disposed at a substantially same height as a height of dice  1330 A and  1330 B. In this manner, a short length of bonding wires  1310 A,  1310 B,  1306 A and  1306 B may be used to thereby reduce electrical resistance and inductance. Further a greater number of bonding wires  1310 A and  1310 B may be used to further reduce electrical resistance and inductance. 
     A ninth alternative embodiment of the present invention generally designated  1400  is shown in  FIG. 14A  and  FIG. 14B . Semiconductor package  1400  may be implemented as a dual die device. Semiconductor package  1400  may include a lead frame generally designated  1460 . Lead frame  1460  may include lead frame pads  1408 A and  1408 B having devices  1430 A and  1430 B bonded respectively thereto. Leadframe  1460  may include a source lead  1416 A, a gate lead  1412 A, and a drain lead comprising lead frame pad  1408 A. Leadframe  1460  may further include a source lead  1416 B, a gate lead  1412 B, and a drain lead comprising lead frame pad  1408 B. Source locking holes  1440 A and  1440 B may be formed in source leads  1416 A and  1416 B respectively. 
     Lead frame  1460  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1460  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding areas  1418 A and  1418 B and gate bonding areas  1420 A and  1420 B may be disposed at a substantially same height as a height of dice  1430 A and  1430 B. In this manner, a short length of bonding wires  1410 A,  1410 B,  1406 A and  1406 B may be used to thereby reduce electrical resistance and inductance. Further a greater number of bonding wires  1410 A and  1410 B may be used to further reduce electrical resistance and inductance. 
     With reference to  FIG. 15 , a tenth alternative embodiment of the present invention generally designated  1500  is shown. Semiconductor package  1500  may include a large package occupying the footprint of an SO14 to SO20 package. Semiconductor package  1500  may include a lead frame generally designated  1530 . Lead frame  1530  may include lead frame pads  1502 A and  1502 B having devices  1501 A and  1501 B bonded respectively thereto. Leadframe  1530  may include a source lead  1516 A, a gate lead  1512 A, and a drain lead  1526 A. Leadframe  1530  may further include a source lead  1516 B, a gate lead  1512 B, and a drain lead  1526 B. Source lead  1516 A and gate lead  1512 A may be disposed on a same first side  1560  of semiconductor package  1500  as source lead  1516 B and gate lead  1512 B. Drain lead  1526 A and drain lead  1526 B may be disposed on a second side  1570  of semiconductor package  1500 . Source locking holes  1540 A and  1540 B may be formed in source leads  1516 A and  1516 B respectively. Drain locking holes  1550 A and  1550 B may be formed in drain leads  1526 A and  1526 B respectively. Locking notches  1528 A and  1528 B may be formed in drain leads  1526 A and  1526 B respectively. Lead frame  1530  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1530  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding areas  1518 A and  1518 B and gate bonding areas  1520 A and  1520 B may be disposed at a substantially same height as a height of dice  1501 A and  1501 B. In this manner, a short length of bonding wires  1510 A,  1510 B,  1506 A and  1506 B may be used to thereby reduce electrical resistance and inductance. 
     An eleventh alternative embodiment of the present invention generally designated  1600  is shown in  FIG. 16 . Semiconductor package  1600  may include a large package occupying the footprint of an SO14 to SO20 package. Semiconductor package  1600  may include a lead frame generally designated  1630 . Lead frame  1630  may include lead frame pads  1602 A and  1602 B having devices  1601 A and  1601 B bonded respectively thereto. Leadframe  1630  may include a source lead  1616 A, a gate lead  1612 A, and a drain lead  1626 A. Leadframe  1630  may further include a source lead  1616 B, a gate lead  1612 B, and a drain lead  1626 B. Source lead  1616 A and gate lead  1612 A may bed is posed on an opposite side of semiconductor package  1600  from source lead  1616 B and gate lead  1612 B. Drain lead  1626 A may be disposed on an opposite side of semiconductor package  1600  from drain lead  1626 B. Source locking holes  1640 A and  1640 B may be formed in source leads  1616 A and  1616 B respectively. Drain locking holes  1650 A and  1650 B may be formed in drain leads  1626 A and  1626 B respectively. Locking notches  1660 A and  1660 B may be formed in drain leads  1626 A and  1626 B respectively. Lead frame  1630  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame  1630  advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally source bonding areas  1618 A and  1618 B and gate bonding areas  1620 A and  1620 B may be disposed at a substantially same height as a height of dice  1601 A and  1601 B. In this manner, a short length of bonding wires  1610 A,  1610 B,  1606 A and  1606 B may be used to thereby reduce electrical resistance and inductance. 
     With reference to  FIG. 17 , a twelfth alternative embodiment of the present invention generally designated  1700  is shown. Semiconductor package  1700  is similar to semiconductor package  1100  ( FIG. 11A ,  FIG. 11B , and  FIG. 11C ) except that a bottom portion  1720  of lead frame pad  1708  is encapsulated in resin body  1709 . 
     A thirteenth alternative embodiment of the present invention generally designated  1800  is shown in  FIG. 18 . Semiconductor package  1800  may include a lead frame pad  1858  having mounted thereon a semiconductor device  1851 . A resin body  1808  may encapsulate a portion of a lead frame (not shown). A plurality of contact regions  1872  may be used to connect a lead portion  1868  of lead frame to a device region. Contact regions  1872  may include solder, brazing, Au bump, Ag epoxy, Cu bump or other means of connection. The device region may be a source region in the case of a vertical device and a drain region in the case of a lateral device. A lead  1866  may be coupled to lead portion  1868 . A lead  1816  may be coupled to a lead bonding area  1818  which may in turn be coupled to a device region by means of bonding wire  1818 . The lead frame may be formed of a single gauge material having a thickness greater than the conventional 8 mils. A thicker lead frame advantageously provides for reduced package resistance and inductance as described with reference to semiconductor package  600 . Additionally lead bonding area  1818  may be disposed at a substantially same height as a height of device  1851 . In this manner, a short length of bonding wire  1810  may be used to thereby reduce electrical resistance and inductance. 
     With reference to  FIG. 19 , a fourteenth alternative embodiment of the present invention generally designated  1900  is shown. A lead portion  1918  may be connected to a device region (such as a source or drain region) of device  1951  by means of contact regions  1972 . Advantageously, package  1900  provides for improved thermal dissipation through leads  1916 . 
     With reference to  FIG. 20 , a fifteenth alternative embodiment of the present invention generally designated  2000  is shown. A first lead portion  2068 A may be connected to a device region (such as a source or drain region) of device  2051  by means of contact regions  2072 A. A second lead portion  2068 B may be connected to a device region of device  2051  by means of contact regions  2072 B. 
     A sixteenth alternative embodiment of the present invention generally designated  2100  is shown in  FIG. 21A ,  FIG. 21B , and  FIG. 21C . Semiconductor package  2100  may include a lead frame generally designated  2130 . A resin body  2152  may encapsulate a portion of lead frame  2130 . Lead frame  2130  may include a source lead  2116 , a gate lead  2112 , and a drain lead  2126 . Drain lead  2126  may include a pair of opposing drain lead portions  2150 . Drain lead portions  2150  may be exposed through resin body  2152  by cutouts  2156  to provide for locking of package  2100 . 
     A seventeenth alternative embodiment of the invention generally designated  2200  is shown in  FIG. 22A ,  FIG. 22B , and  FIG. 22C . Semiconductor package  2200  may include a lead frame generally designated  2230  having a lead frame pad  2202  to which may be coupled a die  2201 . A portion of the lead frame  2230  may be molded in a resin body  2208 . The lead frame  2230  may include a source lead  2216 , a gate lead  2212 , and a drain lead  2226 . Source lead  2216  may be disposed externally of resin body  2208  and coupled to an internal source bonding area  2218  which in turn may be coupled to a device source by means of bonding wires  2210 . Source lead  2216  may be formed as a single lead to facilitate the use of a maximum number of bonding wires  2210  to thereby reduce on-resistance and inductance. Drain lead  2226  may be connected to the lead frame pad  2202 . Gate lead  2212  may be connected to an internal gate bonding area  2220  which in turn may be connected to a gate pad  2227  by means of bonding wire  2206 . Locking notches  2228  may be formed in source lead  2216 . 
     With particular reference to  FIG. 22B , lead frame  2230  may be formed of a single gauge material having a thickness greater than the conventional 8 mils. Advantageously, a thicker lead frame  2230  facilitates the bonding of larger diameter aluminum bonding wires  2210  and  2206  and/or a greater number of bonding wires  2210  and  2206 . The use of aluminum bonding wires  2210  and  2206  decreases package inductance and resistance dramatically over conventional gold wire configurations. Bonding wires  2210  and  2206  may be up to 20 mils in diameter. A thicker lead frame material further provides for improved package thermal behavior by facilitating heat flow laterally out drain lead  2226 . This is so even in a case where a bottom portion  2250  of lead frame pad  2202  is exposed as shown in  FIG. 22C . 
     With continued reference to  FIG. 22B , source bonding area  2218  and gate bonding area  2220  (not shown) may be disposed at a substantially same height as a height of die  2201 . In this manner, a short length of bonding wires  2210  and  2206  may be used to thereby reduce electrical resistance and inductance. 
     As will be appreciated by those skilled in the art, the present invention generally provides a semiconductor package having a lead frame formed of a single gauge material having a thickness greater than the conventional 8 mils. Advantageously, a thicker lead frame facilitates the bonding of larger diameter aluminum bonding wires. The use of aluminum bonding wires decreases package resistance dramatically over conventional gold wire configurations. Bonding wires may be up to 20 mils in diameter. A thicker lead frame material further provides for improved package thermal behavior by facilitating heat flow laterally out a drain lead. This is so even in a case where a bottom portion of lead frame pad is exposed. Further, a source bonding area and a gate bonding area may be disposed at a substantially same height as a height of a die. In this manner, a short length of bonding wires may be used to thereby reduce electrical resistance and inductance. 
     It should be understood, of course, that the foregoing relates to preferred embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.