Abstract:
A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the power supply slips below its design tolerance range.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]     Not applicable.  
       STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT  
       [0002]     Not applicable.  
       REFERENCE TO AN APPENDIX  
       [0003]     Not applicable.  
       BACKGROUND  
       [0004]     1. Technical Field  
         [0005]     The technology described herein is generally related to the field of integrated circuits (“IC”); IC structures and devices are also referred to hereinafter as “chip(s),” and “dice” or “die.” 
         [0006]     2. Description of Related Art  
         [0007]     The integrated circuit field of technology is well established. Many publications describe the details of commonly known techniques used in the fabrication of integrated circuits that can be generally employed in the fabrication of complex, three-dimensional, IC structures and devices; see e.g.,  Silicon Processes,  Vol. 1-3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation, Hillsboro, Oreg. Moreover, the individual steps of such a process can be performed using commercially available IC fabrication machines. The use of such machines and commonly used fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art.  
         [0008]     Certain commercial products employing IC chips require the state of a digital output signal stays at a predetermined logic signal, “HIGH” or “LOW,” even when supply voltages are below the threshold voltage of the output stage driver field effect transistors (“FETs”). For example, a voltage monitoring instrument needs to transmit accurately the true output of the circuitry being monitored. Other examples of such products are power-on reset generators, microprocessor supervisors, and chip-select drivers.  
         [0009]     Known manner complementary metal-oxide-semiconductor (“CMOS”) circuit designs may not result in a “guaranteed” output state when the supply voltage falls below a threshold voltage of the output stage driver FETs. On the other hand, lowering the threshold voltage may improve performance of an IC, but generally requires a change to the wafer-level IC dice fabrication processes. However, lowering the threshold voltage may have undesired electrical effects such as increasing leakage currents. Therefore, there are competing interests for the IC designer to consider.  
         [0010]     There is a need for improved electronic circuits for commercial products where output stage signals are a critical factor of performance.  
       BRIEF SUMMARY  
       [0011]     The present invention generally provides for an integrated circuit output driver stage for ensuring a predetermined output when power supply voltage falls below an expected level.  
         [0012]     The foregoing summary is not intended to be inclusive of all aspects, objects, advantages and features of the present invention nor should any limitation on the scope of the invention be implied therefrom. This Brief Summary is provided in accordance with the mandate of 37 C.F.R. 1.73 and M.P.E.P. 608.01(d) merely to apprise the public, and more especially those interested in the particular art to which the invention relates, of the nature of the invention in order to be of assistance in aiding ready understanding of the patent in future searches. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]      FIG. 1  is an electrical schematic diagram in accordance with an exemplary embodiment of the present invention.  
         [0014]      FIG. 2  is an electrical schematic diagram in accordance with another exemplary embodiment of the present invention. 
     
    
       [0015]     Like reference designations represent like features throughout the drawings. The drawings in this specification should be understood as not being drawn to scale unless specifically annotated as such.  
       DETAILED DESCRIPTION  
       [0016]      FIG. 1  is an electrical schematic diagram for a circuit  100  in accordance with a first exemplary embodiment of the present invention. Standard electrical engineering symbols and conventions are shown in this layout such that a person skilled in the art will recognize the components and their respective interconnections. While the exemplary embodiments described herein is illustrative of using semiconductor devices having a specific transistor polarity implementation, it will be recognized by those skilled in the art that an implementation of reverse polarity devices can be made. No limitation on the scope of the invention is intended by the exemplary embodiments and none should be implied therefrom. An experimental implementation was constructed in a BiCMOS technology process; device sizes and the like may be adjusted as would be evident to persons skilled in the art for scaling the components and adapting the present invention to a specific implementation.  
         [0017]     A CMOS Output Driver  101  is a typical known manner, output driver having four metal oxide semiconductor field effect transistors (“MOSFET”) MP 1 , MP 2 , MN 1 , MN 2  and forming an output driver stage on-board a chip, not shown. The Driver  101  is designed for receiving digital logic signals—represented by “In” symbol  105 —at an input node  103  from on-board chip circuitry, not shown, and providing an amplified output signal at the output driver stage output node  107 . A power supply voltage, Vss, for example, a known manner DC volt source, not shown, provide a nominal design voltage, or can be an electrical ground. A drain-source bias voltage, V DD , for the MOSFETs MP 1 , MP 2 , MN 1 , MN 2  of this embodiment is, for example, a known manner 3.3 volt±0.3 DC source, not shown.  
         [0018]     Generally, when the voltage V DD  is at its design nominal value, it is well above the threshold voltage for the MOSFETs MP 1 , MP 2 , MN 1 , MN 2 , the voltage at the output driver stage output node  107  will be LOW when the signal In  105  is LOW and HIGH when the signal In  105  is HIGH. However, when the signal In  105  is LOW and the voltage V DD  approaches or falls below the threshold voltage, the state of the output driver stage at output node  107  can float up from the LOW state since there is not enough voltage on the gate line  109  of MOSFET MN 2  to keep MOSFET MN 2  in the ON state.  
         [0019]     In accordance with the exemplary embodiment of the present invention in a bipolar-CMOS (“BiCMOS”) implementation, an Auxiliary Driver  111  is added to the chip output stage. The function of the Auxiliary Driver  111  is to supplement output signal driving at low V DD  voltages and to ensure that output at the output pad  113  of the chip remains LOW. The output pad  113  of the chip is connected to CMOS Output Driver  101  output node  107  via line  115  and Auxiliary Driver output node  117 .  
         [0020]     When the voltage V DD  is at or above its design nominal value, the gate  119  of Auxiliary Driver MOSFET MN 4  is pulled up; that is, it may be considered at a logic HIGH level. This removes the base drive signal from npn-type bipolar transistor Q 3 .  
         [0021]     Removing the base drive signal from bipolar transistor Q 3  removes the base drive signal from pnp-type bipolar transistor Q 2 . Therefore, for V DD =HIGH, the Auxiliary Driver  111  is OFF and so it does not influence the state of the output signal at output pad  113 .  
         [0022]     When the voltage V DD  drops below the threshold voltage for Auxiliary Driver MOSFET MN 4 , the drain  121  is pulled up by the voltage drop across bias resistor R 16 , sized appropriately to the specific implementation. The current, “I,” through resistor R 16 , represented by arrow  123 , is forced on a circuit path to the base  125  of npn-type bipolar transistor Q 3 . The collector  127  of bipolar transistor Q 3  draws current out of the base  126  of the transistor Q 2 . The collector  129  of transistor Q 2  pushes current into the base  131  of npn-type bipolar transistor Q 1 . The collector  133  of transistor Q 1  now draws node  117  LOW. Thus, the output pad  113  LOW condition is maintained appropriately. In other words, by turning on the Auxiliary Driver  111  whenever the voltage V DD  falls below the design threshold voltage for driving the CMOS Output driver  101 , a LOW output signal is guaranteed at the associated output pad  113 .  
         [0023]     Note that another advantage of the circuit  100  of the present invention is that the output pad  113  LOW condition remains at the LOW digital signal value even if there is significant external impedance from the device output to the positive supply, such as via a pull-up resistor, not shown.  
         [0024]     In the preferred embodiment, the threshold voltage of Auxiliary Driver MOSFET MN 4  should be substantially equivalent to the threshold voltage of CMOS Output Driver MOSFET MN 2 . In this manner, the Auxiliary Driver  111  begins to operate at the supply voltage when it is most needed.  
         [0025]     In the preferred embodiment, another MOSFET transistor M 13  is connected in Auxiliary Driver  111  so that leakage current from the collector  127  to the emitter  128  will not erroneously turn transistors Q 1  and Q 2  ON.  
         [0026]     Similarly, in the preferred embodiment, another MOSFET transistor M 12  is connected in Auxiliary Driver  111  so that leakage current in transistor Q 2  from the collector  129  to the emitter  130  will not erroneously turn transistor Q 1  ON.  
         [0027]     In the preferred embodiment a resistor, “Resd,”  133 , is provided to protect the gate of Auxiliary Driver MOSFET MN 4  from electrostatic discharge into the supply voltage V DD  or V SS .  
         [0028]     Thus, it can be recognized that the circuit  100  is capable of providing a substantial amount of sink current so that the output voltage will be a logic LOW even when the voltage V DD  falls lower that specified. Any pull-up resistance voltage drop that this circuit  100  may have to drive will also be established at logic LOW. The maximum amount of drive is determined by the gains of the bipolar transistors and the value of the bias resistor R 16 .  
         [0029]      FIG. 2  is an electrical schematic diagram in accordance with another exemplary embodiment. It will be recognized by those skilled in the art that this is a complementary version of the circuit  100  shown in  FIG. 1 , built to guarantee that an output  213  stays HIGH at node  217  at low power supply voltage levels.  
         [0030]     As with  FIG. 1 , a CMOS Output Driver  101  is a typical known manner, output driver having four metal oxide semiconductor field effect transistors (“MOSFET”) MP 1 , MP 2 , MN 1 , MN 2  and forming an output driver stage on-board a chip, not shown. It may similarly be advantageous to ensure a logic signal HIGH on the Output Driver output signal line  115 . Again, however, when the In signal  105  is HIGH and the voltage V DD  approaches or falls below output driver MOSFET MP 1 , MP 2 , MN 1 , MN 2  threshold voltage, the state of the output of the CMOS Output Driver  101  can float down on its output line  115  as there will then not be enough voltage on the gate  209  of driving MOSFET MP 2  to maintain an ON condition. The Auxiliary Driver  211  is added to supplement the CMOS Output Driver  101  when the voltage V DD  falls below the threshold voltage level needed for the output driver stage MOSFETs MP 1 , MP 2 , MN 1 , MN 2 .  
         [0031]     When the voltage V DD  is at its design nominal level, the gate  219  of auxiliary driver MOSFET MP 4  is pulled down, viz., to a logic LOW level. This removes base drive signal from a pnp-type bipolar transistor Q 3 ′. Consequently, the base drive signal is removed from a npn-type bipolar transistor Q 2 ′ which in turn remove the base drive signal from a pnp-type bipolar transistor Q 1 ′. Thus, for voltage V DD  at its nominal level, the Auxiliary Driver remains in an OFF condition.  
         [0032]     When the voltage V DD  drops below its design nominal level and, therefore is not sufficient for operation of the CMOS Output Drive  101 , the drain  221  of transistor MP 4  is pulled down by bias resistor R 16 ′. The current, represented by arrow  223  labeled “I,” through R 16 ′ can come from nowhere else but the base  225  of bipolar transistor Q 3 ′. The collector  227  of transistor Q 3 ′ then pushes current into the base  226  of transistor Q 2 ′. In turn, the collector  229  of transistor Q 2 ′ pulls current out of the base  231  of transistor Q 1 ′. The collector  233  of transistor Q 1 ′ is pulled to a logic level HIGH; this occurs even if there is significant external impedance, such as a pull-down resistor, not shown, from the output pad  213  to ground.  
         [0033]     As with the embodiment of  FIG. 1 , the threshold voltage for Auxiliary Driver  211  transistor MP 4  should be substantially the same as the threshold voltage for CMOS Output Driver  201  transistor MP 2  in order for the Auxiliary Driver  211  to begin to operate only when the supply voltage V DD  is out of its nominal design value.  
         [0034]     In a preferred embodiment, electrostatic discharge protection resistor, “Resd,”  232  is provided to protect the gate  219  of transistor MP 4 .  
         [0035]     In a preferred embodiment, an auxiliary driver MOSFET transistor M 13 ′ is connected so that leakage current from the emitter  228  to collector  227  of transistor Q 3 ′ will not errantly turn transistor Q 2 ′ and Q 1 ′ ON.  
         [0036]     In a preferred embodiment, an auxiliary driver MOSFET transistor M 12 ′ is connected so that leakage current from collector  230  to emitter  229  in Q 2 ′ will not erroneously turn transistor Q 1 ′ ON.  
         [0037]     Thus, it can be recognized that the circuit  200  is capable of providing a substantial amount of source current so that the output voltage will be a logic HIGH even when the supply voltage V DD  falls lower that specified. Any pull-down resistance voltage drop that this circuit  200  may have to drive will also be established at logic HIGH. The maximum amount of drive is determined by the gains of the bipolar transistors and the value of the bias resistor R 16 ′.  
         [0038]     It is important to note for both described exemplary embodiments that once the supply voltage drops to the level where the Auxiliary Driver  111  or  211  becomes activated, the output state  113 ,  213 , respectively, will be at the desired state—namely, LOW in  FIG. 1  or HIGH in  FIG. 2 —independent of the input state. In many cases, once the supply voltage gets too low, whatever is driving the input  105  may no longer be a known, defined state.  
         [0039]     The foregoing Detailed Description of exemplary and preferred embodiments is presented for purposes of illustration and disclosure in accordance with the requirements of the law. It is not intended to be exhaustive nor to limit the invention to the precise form(s) described, but only to enable others skilled in the art to understand how the invention may be suited for a particular use or implementation. The possibility of modifications and variations will be apparent to practitioners skilled in the art. No limitation is intended by the description of exemplary embodiments which may have included tolerances, feature dimensions, specific operating conditions, engineering specifications, or the like, and which may vary between implementations or with changes to the state of the art, and no limitation should be implied therefrom. Applicant has made this disclosure with respect to the current state of the art, but also contemplates advancements and that adaptations in the future may take into consideration of those advancements, namely in accordance with the then current state of the art. It is intended that the scope of the invention be defined by the Claims as written and equivalents as applicable. Reference to a claim element in the singular is not intended to mean “one and only one” unless explicitly so stated. Moreover, no element, component, nor method or process step in this disclosure is intended to be dedicated to the public regardless of whether the element, component, or step is explicitly recited in the Claims. No claim element herein is to be construed under the provisions of 35 U.S.C. Sec. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for . . . ” and no method or process step herein is to be construed under those provisions unless the step, or steps, are expressly recited using the phrase “comprising the step(s) of . . . ”