Abstract:
The present invention relates to a method for controlling an amplifier unit having at least one drive signal input connection  1 , at least one power supply voltage input connection  2  and an output connection  4 . The amplifier unit comprises at least one amplifier, and the method comprises the steps of: feeding each amplifier by a drive signal from said at least one drive signal input connection  1 , and feeding each amplifier by a power supply voltage from said at least one power supply voltage input connection, whereby said amplifier unit has defined output characteristics at the output connection  4  and a predetermined power supply voltage at a maximum RF output power for a RF signal. The method further comprises the steps of: operating at least one amplifier with RF output voltage characteristics to obtain a reduced shunt loss, compared to a reference shunt loss, at the output connection  4 . The reference shunt loss is obtained when operating each amplifier as a class B amplifier having the defined output characteristics at the output connection  4  and the predetermined power supply voltage at a maximum RF output power for the RF signal, and modulating the power supply voltage to each amplifier to reduce excessive voltage drop over the amplifier.

Description:
TECHNICAL FIELD 
     The present invention is related to a method for controlling an amplifier unit, especially amplifier units adapted for use in radio communication networks. 
     BACKGROUND 
     Description of Related Art 
     Traditional efficient linear Power Amplifiers (PAs) usually have constant supply voltage and operate in (or near) class B. In class B Operation, i.e. half-wave rectified sine transistor current waveform, the DC (supply) current is proportional to the RF output current (which is the fundamental harmonic component of the half-wave rectified sine). The RF output voltage is also proportional to the RF output current (for the usual linear load resistance). This in turn makes the efficiency proportional to the amplitude of the output signal. 
     The average efficiency for a class B amplifier, outputting a signal whose average signal level is well below the maximum (peak) level, i.e. that has high peak-to-average ratio, is low compared to the efficiency at maximum output. 
     In an article with the title, “High-efficiency modulation System,” by R. B. Dome, published in Proc. IRE, vol. 26, no. 8, pp. 963-982, August 1938, Load Modulation (LM) PA is disclosed with a variable load which improve upon the basic class B amplifier. A way to achieve a variable load is to have a matching network that can be varied at signal envelope speeds. The average efficiency is increased, if the matching network transforms the load resistance into a high resistance (at the transistor output node) at low output levels and a low resistance (equal to the optimal class B resistance) at high output levels. This decreases the transistor RF output current at all output levels except the maximum, while producing the same RF voltage and current in the load. The RF voltage at the transistor output is at the same time increased. Reduced transistor RF output current is translated into reduced DC current since class B Operation is used. 
     Examples of PAs having an increased average efficiency are Doherty and Chireix Radio Frequency (RF) PAs. An article with the title “A new high efficiency power amplifier for modulated waves,” by W. H. Doherty, published in  Proc. IRE . vol. 24, no. 9, pp. 1163-1182. September 1936, describe the Doherty RF PA, and an article with the title “High power outphasing modulation,” by H. Chireix, published in  Proc. IRE . vol. 23, no. 11, pp. 1370-1392, November 1935, describes the Chireix RF PA. These PAs are efficient for amplitude-modulated Signals, since they have a lower average sum of RF Output currents from the transistors than a conventional amplifiers output current. This reduced output current is obtained by using two transistors that influence each others output voltages and currents through a reactive output network (that is also coupled to the load). By driving the constituent transistors with the right amplitudes and phases, the sum of RF output currents is reduced at all levels except the maximum. Also for these amplifiers the RF voltage at one or both transistor outputs is increased. 
     Both LM and Chireix/Doherty amplifiers have constant supply voltage. The amount of output current reduction for these systems is limited by the accompanying RF voltage increase; the RF voltage amplitude cannot generally be larger than the supply voltage other than by a small factor. 
     Envelope Elimination and Restoration (EER), or Dynamic Drain Biasing (DDB), as described in an article with the title “Single sideband transmission by envelope elimination and restoration”, by L R. Kahn, published in Proc. IRE, vol. 40, pp. 803-806. July 1952, uses a supply voltage that varies with the signal envelope. By this, there is no or little excessive voltage drop over the power transistor; all voltage is “used up” by the output RF voltage. 
     Doherty, Chireix, and LM amplifiers are efficient through reduced average transistor RF output current, which gives a reduced average DC supply current and therefore reduced DC power consumption. Reducing RF current also reduces resistive loss that is effectively in series at the output node. Unfortunately, this effect is accompanied by an increase in at least one of the transistor&#39;s RF output voltages, which increases resistive loss that is effectively in shunt (coupled from node to ground) at the transistor output node. Such shunt loss is common in practical RF power transistors, so the theoretical efficiency gains of Doherty, Chireix. and LM amplifiers are often in practice reduced by this type of loss. 
     EER and DDB amplifiers neither reduce nor increase any of these resistive loss mechanisms, since both RF voltage and RF current at the transistor output node are unaltered from those of the basic amplifier. Although this is better than Doherty, Chireix, and LM amplifiers in case of transistors with large shunt loss, it does nothing to improve the situation. 
     Until now, the choice has been between using the EER or DDB amplifiers when shunt losses dominates, and Doherty, Chireix, or LM amplifiers when series losses dominate (the success of the method and its implementation in reducing the original “Class B loss” also taken into account). 
     SUMMARY 
     An object with the present invention is to provide a power amplifier having an increased efficiency compared to the described prior art power amplifiers. 
     A solution to the object is provided by combining reverse Doherty, Chireix, or LM techniques with EER or DDB amplifiers. Operating Doherty, Chireix, or LM amplifiers in reverse, i.e. increasing RF current and decreasing RF voltage, decreases the efficiency instead of increasing it. This idea on its own thus produces super-inefficient amplifiers. It does however reduce one loss mechanism, the shunt loss, by reducing the RF voltage at an output node. By then applying EER or DDB, the loss due to excessive voltage drop can still be minimized, provided a dynamic supply voltage is used that varies as a new function of the signal envelope. 
     An advantage with the present invention is that by addition of EER/DDB, reverse Doherty, reverse Chireix, or reverse Load Modulation can be used to increase efficiency even in situations where transistor shunt losses would render the regular Doherty, Chireix, or Load Modulation methods more or less useless. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a block diagram illustrating the general concept of the present invention. 
         FIG. 2  shows a first embodiment of an amplifier according to the invention. 
         FIGS. 3   a - 3   c  show the RF characteristics of the embodiment in  FIG. 2 . 
         FIG. 4  shows a graph with the efficiency of the embodiment in  FIG. 2  in comparison with LM and EER power amplifier efficiency. 
         FIGS. 5   a - 5   c  show the RF characteristics of the embodiment in  FIG. 2  with a knee voltage. 
         FIG. 6  shows a graph with the efficiency of the embodiment in  FIG. 2  with a knee voltage in comparison with LM and EER power amplifier efficiency. 
         FIG. 7  shows a graph with the efficiency of the embodiment in  FIG. 2  in comparison with LM and EER power amplifier efficiency when the shunt resistance is 20 times the optimal load. 
         FIG. 8  shows a graph with the efficiency of the embodiment in  FIG. 2  in comparison with LM and EER power amplifier efficiency with a knee voltage when the shunt resistance is 20 times the optimal load. 
         FIG. 9  shows a second embodiment of an amplifier according to the invention. 
         FIGS. 10   a - 10   c  show the RF characteristics of the embodiment in  FIG. 9 . 
         FIG. 11  shows a graph with the efficiency of the embodiment in  FIG. 9  in comparison with reverse LM/EER and EER power amplifier efficiency. 
         FIGS. 12   a - 12   c  show the RF characteristics of the embodiment in  FIG. 9  with a knee voltage. 
         FIG. 13 . shows a third embodiment of an amplifier according to the invention. 
         FIGS. 14   a - 14   c  show the RF characteristics of the embodiment in  FIG. 13 . 
         FIG. 15  shows a graph with the efficiency of the embodiment in  FIG. 13  in comparison with reverse LM/EER and EER power amplifier efficiency. 
     
    
    
     DETAILED DESCRIPTION 
     Introducing Doherty, Chireix, or LM techniques to EER or DDB amplifiers has so far been considered ineffective, since when EER or DDB performs well on its own, and Doherty, Chireix, or LM techniques do not significantly contribute to the efficiency. 
     In essence, two methods that solve the same problem in different ways are turned into a combination that solves two different problems, by using one of the methods in reverse. 
     The invention combines reverse Doherty, Chireix, or LM techniques with EER or DDB amplifiers. Operating Doherty, Chireix, or LM amplifiers in reverse, i.e. increasing RF current and decreasing RF voltage, decreases the efficiency instead of increasing it. This idea on its own thus produces super-inefficient amplifiers, and thus has never been considered for implementation. It does however reduce one loss mechanism, the shunt loss, by reducing the RF voltage at the output node(s), compared to a reference shunt loss, such as the shunt loss obtained when operating the amplifier as a class B amplifier having the same output characteristics at the output node(s) and the same power supply voltage at a maximum RF output power for the RF signal. By then applying EER or DDB, the loss due to excessive voltage drop can still be minimized, provided a dynamic supply voltage is used that varies as a new function of the signal envelope. 
       FIG. 1  shows a block diagram illustrating the general concept of the invention. A signal amplifying system  10  comprises an amplifier unit  11  and a signal processing unit  15  being supplied with an input information signal  5 . An output connection  4  of the amplifier unit  11  is connected to an antenna  14 , and signals  16 ,  17  and  18  are fed from the signal processing unit  15  to respective input connections  1 ,  2  and  3  of the amplifier unit  11 . The amplifier unit  11  further comprises at least one amplifier  12  and a matching network  13 . 
     At least one drive signal  16 , which contains the signal information to be amplified and transmitted from the antenna  14 , is fed to drive signal input connection  1  of the amplifier unit  11 . Each drive signal is connected to an amplifier  12  as described below. At least one power supply voltage  17  is provided to the amplifier unit  11  and is fed to respective amplifier  12  and at least one control signal  18  is provided to a control signal input connection  3 . In some of the preferred embodiments described below, the control signal  18  is combined with the drive signals  16 , whereby a separate control signal input connection  3  may be omitted. 
     The purpose of the matching network  13  is to reduce a load impedance seen from each amplifier output to be below an optimal load impedance at maximum output power from each amplifier  12 , at least in a part of an output power amplitude range. This is illustrated in described preferred embodiments below. 
     Preferred Embodiments 
     1) Reverse Load Modulation System Combined with EER/DDB 
       FIG. 2  shows a first embodiment of a signal amplifying system  20  comprising a reverse Load Modulation system combined with EER/DDB. An amplifier unit  21  comprises a power amplifier (PA)  22  fed by a controlled power supply voltage through line  23 , and connected via a controlled matching network  24  to a load, such as an antenna  14 . An input of the PA  22  is connected to a drive signal input connection  1  of the amplifier unit, and an output of the PA  22  is connected to the matching network  24 . The line  23  for feeding the power supply voltage to the PA  22  is connected to a power supply input connection  2  and the matching network is connected to a control signal input connection  3 . 
     The creation of all control and drive (RF) signals is in this embodiment implemented in one signal processing unit  25 . This is convenient also in practice, since all signals originate from the same input information signal  5 . Knowledge and subsequent correction of the behavior of one component affect the control and drive signals to the others. 
     The signal processing unit  25  is provided with means to form the necessary control and drive signals to be supplied to the amplifier unit  21  from the input information signal  5 . In this embodiment a drive signal  26 , a control signal  28  and a controlled power supply voltage  27  needs to be provided to the amplifier unit  21 . All signals are created digitally in the signal processing unit  25  and are converted to analog signals using separate Digital-to-Analog converters (D/A). The drive signal  26  is processed in an upconverter  26   A  before the drive signal is fed to the drive signal input connection  1  of the amplifier unit  21 . The power supply voltage is processed in a power supply unit  27   A  before the power supply voltage is applied to the power supply input connection  2 , and the control signal  28  is processed in a control unit  28   A  before the control signal is fed to the control signal input connection  3 . Optional control signals may be fed to the matching network from the control unit  28   A  as indicated by the dashed line  29 . 
     Reactances in the matching network are controlled (at envelope speeds) so that the network dynamically transforms the load impedance at the output connection  4  into another impedance at the PA transistor&#39;s output. Typically, the controlled reactances are voltage-controlled capacitors. Reverse LM means that this impedance is lower than the optimal “class B” load for a wide range of output levels. 
     To get the right output amplitude at the load (usually an antenna) the drive signal to the PA must have higher amplitude than the usual class B amplitude at these output levels. This produces the greater RF output current needed. 
     The supply voltage is controlled in the same manner as in an ordinary EER application, but with even lower supply voltage for a wide range of output levels to accommodate the lower RF voltage swings due to the reverse dynamic load matching. 
     An exemplary reverse Load Modulation system combined with EER/DDB is built with a transistor that has an optimal load resistance R opt  (i.e. that gives maximum Output in class B Operation) of 1, a shunt loss resistance R loss  of 2, a maximum RF voltage at the transistor Output of 1, no “knee” voltage V knee =0 (maximum transistor RF output voltage amplitude assumed to be supply voltage minus knee voltage), and a maximal RF output current of 1.5. Pertinent currents, voltages, powers and efficiencies are shown versus the PA&#39;s normalized Output Signal amplitude, in  FIGS. 3   a - 3   c  and  4 . 
       FIG. 3   a  shows a output RF voltage v d  of the transistor (lowest trace) and the RF output current i d  (constant at 1.5). The PA&#39;s output signal voltage v out  (linear, middle dashed trace) is included as a reference. 
       FIG. 3   b  shows the transformed load R load,d  as seen at the transistor output. Due to the absence of a knee voltage (V knee =0), the transformed load can at all levels be as low as possible so that it gets as much of the RF current as possible. The only limiting factor is the maximum current the transistor can deliver. (In practice there can also be a limit to the ratio of lowest to highest transformation. The transformed load can then be kept constant at its lowest below a certain output level, and the RF output current should consequently be a linearly increasing function in this range.) 
       FIG. 3   c  shows the DC supply power P DC  (top trace), the output power P out  (middle dashed trace) and the loss power P loss  (bottom trace). 
       FIG. 4  shows the efficiency curve of the PA (top trace). The efficiency at the lowest output level is the ideal class B efficiency 78.5%. At maximum output, the efficiency is ⅔ of the class B efficiency, which indicates that ⅔ of the transistor output power goes to the load (transformed to 1 at this level) and ⅓ feeds the shunt loss resistance. 
       FIG. 4  also shows, for the transistor described in connection with  FIGS. 3   a - 3   c , the efficiency of a regular LM system (bottom trace), and EER system (middle trace). The absence of a knee voltage gives the EER system a constant efficiency. The Load Modulation system suffers heavily from the low shunt loss resistance and is only marginally better than a plain class B stage. The EER system is seen to benefit greatly from the addition of reverse Load Modulation, the combination being 50% more efficient than EER alone at low output levels. 
     The next example is identical to the previous one except for the addition of a constant “knee” voltage, here modeled as an addition of 10% of the maximum DC supply voltage to the supply voltage at all levels. This gives an extra DC power loss proportional to the DC current (and hence RF) which must be considered for optimal Operation.  FIGS. 5   a - 5   c  show the transistor&#39;s RF output voltage and current, the dynamically transformed load impedance, and the supply voltage, versus the normalized power amplifier output signal amplitude. 
       FIG. 5   a  shows the transistor&#39;s output RF voltage v d  (lowest trace) and the RF output current i d  (top trace). The PA&#39;s output signal voltage v out  (linear, dashed trace) is included as a reference. The current i d  is seen to increase much more slowly at low levels (up to the point of being the maximal possible) than in the previous example, in order not to feed the knee voltage loss via the proportional DC current. 
       FIG. 5   b  shows the transformed load R load,d  as seen at the transistor output. At the lowest (5%) output levels, the LM System operates regularly, i.e. increasing the transformed load. This region is insignificant to the efficiency, so the transformed load can in practice be kept below the optimal (here normalized to 1) in this region too, to keep the ratio of lowest to highest transformation as low as possible. In the upper 95% output levels, reverse load modulation is optimal. From 5% to 67% of the maximum output level, the reverse load modulation is determined by a balance between shunt loss (that is low for a low transformed load) and knee voltage loss (that is low for a high transformed load). Above 67%, the RF current is the limiting factor, so the transformed load must increase to provide increasing RF output signal amplitude. 
       FIG. 5   c  shows the DC supply power P DC  (continuous top trace), the output power P out  (dashed trace) and the loss power P loss  (continuous bottom trace). 
       FIG. 6  shows, for the transistor with knee voltage, the efficiency of a regular Load Modulation System (bottom trace), EER system (middle trace) and reverse Load Modulation System combined with EER (top trace). The knee voltage lowers the efficiency of the EER System more at low levels than at high levels. The EER system is here seen to benefit most from the addition of reverse Load Modulation at medium to high output levels. 
     A higher shunt resistance gives lower shunt loss, which decreases the benefit of adding reverse Load Modulation to the EER system. This is shown in  FIG. 7 , for systems built with a transistor with a shunt resistance 20 times the optimal load, but with no knee voltage. (The order of the traces the same as in  FIG. 4 .)  FIG. 8  shows the same, but with an added knee voltage of 10%. (Same order of the traces.) 
     2) Reverse Chireix System Combined with EER/DDB 
     A reverse Chireix system combined with EER/DDB consists of a Chireix PA fed by a controlled voltage supply. Since the RF voltages on the outputs of the constituent transistors in the reverse Chireix amplifier have equal amplitudes, only one controlled supply voltage is needed (as opposed to the reverse Doherty/EER amplifier discussed in a later section).  FIG. 9  shows a second embodiment of a signal amplifying system  30  comprising a reverse Chireix system combined with EER/DDB. An amplifier unit  31  comprises a first power amplifier T 1  and a second power amplifier T 2 . Both T 1  and T 2  are fed by a controlled common power supply voltage through lines  32  and  33 , respectively. An output of the first power amplifier T 1  is connected to an output connection  4  of the amplifier unit  31  via a first transmission line L 1 , and an output of the second power amplifier T 2  is connected to the output connection  4  of the amplifier unit  31  via a second transmission line L 2 . The output connection  4  is connected to a load, such as an antenna  14 . An input of the first power amplifier T 1  is connected to a first drive signal input connection  1   a  of the amplifier unit  31 , and an input of the second power amplifier T 2  is connected to a second drive signal input connection  1   b  of the amplifier unit  31 . The lines  32  and  33  for feeding the power supply voltage to T 1  and T 2  are connected to a power supply input connection  2 . In contrast to the first described embodiment, there is no need for a separate control signal in this embodiment, since the drive signals fed to the power amplifiers T 1  and T 2  are used for this purpose. 
     The signals are also here regarded as coming from a combined “Signal Processing” block  35 . The signal processing unit  35  is provided with means to form the necessary control and drive signals to be supplied to the amplifier unit  31  from the input information signal  5 . In this embodiment a first drive signal  36   1 , a second drive signal  36   2  and a controlled power supply voltage  37  needs to be provided to the amplifier unit  31 . The drive signals to each amplifier may be modified in both phase and amplitude in such a way that the phase and amplitude is altered relative to the phase and amplitude desired at the output connection. All signals are created digitally in the signal processing unit  35  and are converted to analog signals using separate Digital-to-Analog converters (D/A). The drive signals  36   1  and  36   2  are processed in two separate upconverters  36   A  and  36   B  before the drive signals are fed to the first and second drive signal input connection  1   a  and  1   b , respectively, of the amplifier unit  31 . The power supply voltage is processed in a power supply unit  37   A  before the power supply voltage is applied to the power supply input connection  2 . 
     The reverse Chireix system can be built with the same components as the regular Chireix system. It is however generally not dimensioned equally. The Chireix can be defined by two transmission lines from the transistors outputs to the common load, the sum of electrical lengths being a half wavelength, i.e. L 1 +L 2 =λ/2. The examples give the lengths for these prototypical transmission lines. 
     Reverse Chireix action causes the transistors&#39; RF currents to be higher than conventional class B currents in a wide range of output levels. The RF voltages are consequently lowered. The effect is the same as in the previously discussed reverse Load Modulation system. In the Chireix amplifier, varying the relative phases of the transistors&#39; output currents and voltages causes this effect. The supply voltage must follow the lowered voltage amplitudes for the system to be efficient. 
     An exemplary reverse Chireix system combined with EER/DDB is built with two power amplifiers that each have an optimal load resistance of 2, a shunt loss resistance of 4 (the same relation to the optimal load as in the first LM/EER example), a maximum RF voltage at the transistor output of 1, no “knee” voltage, and a maximal RF output current of 0.75. Transmission lines having characteristic impedance equal to the optimum load for each transistor connect the transistors to a common load equal to the parallel connection of these two optimal loads. The electrical lengths of these transmission lines are 0.07λ from power amplifier T 1  and 0.43λ from power amplifier T 2 . The behaviour of the amplifier unit is shown in  FIGS. 10   a - 10   c.    
       FIG. 10   a  shows the power amplifiers output RF voltage amplitudes v d  (lowest trace), which is equal for the power amplifiers, and summed RF output current amplitude i d .  FIG. 10   b  shows the phase of the voltage φ v2  at the second amplifier output relative to the voltage phase at the common output  4 , and the phase of the current φ i1  of first amplifier output relative to the current phase at the common output  4 . The non-plotted phases are symmetrical to the plotted ones about π/2. We see that the Operation mode is the same in the lower 60% of the output range, above which the system gradually changes phases of the currents and voltages to cope with the output current limitations at 0.75. 
       FIG. 10   c  shows the DC supply power (continuous top trace), the output power (dashed middle trace) and the loss power (continuous bottom trace). 
       FIG. 11  shows the efficiency curve of the reverse Chireix/EER PA. The efficiency in the lower 60% output region is constant after which it starts to fall off towards ⅔ of class B efficiency.  FIG. 11  also includes the efficiency curve of reverse Load Modulation/EER and ordinary EER from  FIG. 4 . The reverse Load Modulation system is more efficient at all levels, and the reverse Chireix variant reaches that efficiency at two points in the output range (of which one is always at the topmost level) when only two amplifiers are used. 
     The next example is identical to the previous one except for the addition of a constant, additional 10% “knee” voltage. The electrical lengths of the transmission lines have been changed and are here 0.085λ from the first amplifier and 0.415λ from the second amplifier. The behaviour of the amplifier unit is shown in  FIGS. 12   a - 12   c.    
       FIG. 12   a  shows the power amplifiers output RF voltage amplitudes v d  (lowest trace), which is equal for the power amplifiers, and summed RF output current amplitude i d .  FIG. 12   b  shows the phase of the voltage φ v2  at the second amplifier output relative to the voltage phase at the common output  4 , and the phase of the current φ i1  of first amplifier output relative to the current phase at the common output  4 . The non-plotted phases are symmetrical to the plotted ones about π/2. The operation is different compared to the previous example in the lowest range. The voltage is increasing faster due to the phases being closer to those of class B operation to overcome the knee voltage loss. 
       FIG. 12   c  shows the DC supply power (continuous top trace), the output power (dashed trace) and the loss power (continuous bottom trace). 
     The efficiency curve of the reverse Chireix/EER PA according to the example is almost identical to the efficiency curve for the reverse LM/EER PA shown in connection with  FIG. 6 . 
     3) Reverse Doherty System Combined with EER/DDB 
     A third embodiment of a signal amplifying system  40  is shown in  FIG. 13  comprising a reverse Doherty system combined with EER/DDB. An amplifier unit  41  comprises a first power amplifier T 1  and a second power amplifier T 2 . Both T 1  and T 2  are fed by a controlled separate power supply voltage through lines  42  and  43 , respectively. An output of the first power amplifier T 1  is connected to an output connection  4  of the amplifier unit  41 , and an output of the second power amplifier T 2  is connected to the output connection  4  of the amplifier unit  41  via a transmission line L. The output connection  4  is connected to a load, such as an antenna  14 . An input of the first power amplifier T 1  is connected to a first drive signal input connection  1   a  of the amplifier unit  41 , and an input of the second power amplifier T 2  is connected to a second drive signal input connection  1   b  of the amplifier unit  41 . The lines  42  and  43  for feeding the power supply voltage to T 1  and T 2  are connected to a respective power supply input connection  2   a  and  2   b . In contrast to the first described embodiment, there is no need for a separate control signal in this embodiment, since the drive signals fed to the power amplifiers T 1  and T 2  are used for this purpose. Two independent supply voltages are needed since the RF voltages on the outputs of the amplifiers T 1  and T 2  have different amplitudes. 
     The signals are also here regarded as coming from a combined “Signal Processing” block  45 . The signal processing unit  45  is provided with means to form the necessary control and drive signals to be supplied to the amplifier unit  41  from the input information signal  5 . In this embodiment a first drive signal  46   1 , a second drive signal  46   2 , a first controlled power supply voltage  47   1  and a second controlled power supply voltage  47   2  needs to be provided to the amplifier unit  41 . The drive signals to each amplifier may be modified in amplitude in such a way that the amplitude is altered relative to the amplitude desired at the output connection. All signals are created digitally in the signal processing unit  45  and are converted to analog signals using separate Digital-to-Analog converters (D/A). The drive signals  46   1  and  46   2  are processed in two separate upconverters  46   A  and  46   B  before the drive signals are fed to the first and second drive signal input connection  1   a  and  1   b , respectively, of the amplifier unit  41 . The power supply voltage is processed in two separate power supply units  47   A  and  47   B  before the power supply voltages is applied to the power supply input connections  2   a  and  2   b , respectively. 
     The reverse Doherty system can be built with the same components as a regular Doherty system, wherein the electric length of the transmission line L is selected to be λ/4. 
     Reverse Doherty action causes one amplifier RF voltage to be lower than the class B voltage for a wide range of output levels. The other amplifier RF voltage is largely unaffected. The RF voltage lowering effect is thus weaker than in the previously discussed reverse Load Modulation system and the reverse Chireix system. 
     An exemplary reverse Doherty system combined with EER/DDB is built with two transistors that each has an optimal load resistance of 2, a shunt loss resistance of 4, a maximum RF voltage at the transistor Output of 1. no “knee” voltage, and a maximal RF output current of 0.75. A quarter wavelength transmission line having characteristic impedance equal to its optimum load connects the second transistor to a common load equal to the parallel connection of the two optimal loads. The first transistor is connected directly to the common load. The behaviour of the PA is shown in  FIGS. 14   a - 14   c.    
       FIG. 14   a  shows the amplifier output RF voltage amplitudes, and  FIG. 14   b  shows the RF output current amplitudes. The phase relations are not shown, but have no variation and are always 0 or π/2. The Operation mode is the same in the lower 60% of the output range, with zero voltage on the output of the second transistor, above which this voltage rises linearly to end at the same voltage as the first transistor. The current limitation of the first transistor is what causes the end of the zero-voltage region. 
       FIG. 14   c  shows the DC supply power (continuous top trace), the output power (dashed trace) and the loss power (continuous bottom trace). 
       FIG. 15  shows the efficiency curve of the reverse Chireix/EER PA. The efficiency in the lower 60% output region is constant after which it starts to fall off towards ⅔ of class B efficiency. The efficiency of the reverse LM/EER and ordinary EER from  FIG. 4  is also included in  FIG. 15  The reverse Doherty System do not reach the reverse LM efficiency except at the topmost level. This is due to the weaker RF voltage lowering effect of reverse Doherty Systems. 
     Reverse Doherty, reverse Chireix, or reverse Load Modulation reduces the loss due to shunt resistance (conductance) at the transistor output nodes of the amplifier and can vastly improve the efficiency of EER/DDB Systems. It gives higher efficiency than either constituent method by itself, and also gives higher efficiency than the methods combined in the regular way. 
     By addition of EER/DDB, reverse Doherty, reverse Chireix, or reverse Load Modulation can be used to increase efficiency even in situations where transistor shunt losses would render the regular Doherty, Chireix, or Load Modulation methods (almost) useless. 
     For reverse Load Modulation and reverse Chireix Systems, the EER/DDB supply voltage vs. Output level gets a more parabolic shape, which is beneficial since it reduces the (voltage) bandwidth. 
     The amplifier unit may naturally comprise more than two combined amplifiers, and the claims should not be limited to only two amplifiers. Examples of Chireix and Doherty amplifiers that contain more than two amplifiers are disclosed in the PCT publications WO 2004/057755 and WO 2004/023647, both assigned to Telefonaktiebolaget LM Ericsson and hereby incorporated by reference.