Abstract:
Systems for multi-mode phase modulation are disclosed. Systems provide for direct modulation of a multi-mode voltage controlled oscillator (VCO). A fractional-N counter may be used in a phase-locked loop (PLL) to synthesize a radio frequency carrier signal. The multi-mode VCO may be characterized by a first frequency gain during operation in a first mode and by a second frequency gain during operation in a second mode where signals controlling the first and second operating modes are provided by a control circuit. The control circuit may include a switch to provide control signals to the VCO.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     This application claims priority under 35 U.S.C. §119(e) of co-pending U.S. Provisional Patent Application Ser. No. 60/800,970, entitled A MULTI-MODE VCO FOR DIRECT FM SYSTEMS, filed on May 16, 2006.  
         [0002]     This application is also related to U.S. patent application entitled “DIRECT SYNTHESIS TRANSMITTER” Ser. No. 10/265,215, U.S. patent application entitled “HIGHLY LINEAR PHASE MODULATION” Ser. No. 10/420,952, and U.S. Provisional Patent Application entitled “LINEAR, WIDEBAND PHASE MODULATION SYSTEM” Ser. No. 60/658,898, the disclosures of which are incorporated herein by reference for all purposes. 
     
    
     FIELD OF THE INVENTION  
       [0003]     The present invention relates generally to phase/frequency modulators, and more particularly, to a multi-mode architecture for direct phase/frequency modulation of a phase-locked loop.  
       BACKGROUND OF THE INVENTION  
       [0004]     Phase modulation schemes are very effective and are therefore widely used in communication systems. A simple example of a phase modulation scheme is quaternary phase shift keying (QPSK).  FIG. 1  shows a constellation diagram that illustrates how QPSK maps two-bit digital data to one of four phase offsets.  FIG. 2  shows a typical QPSK (or in-phase (I)/quadrature (Q)) modulator used to generate a phase-modulated signal. This technique relies on orthogonal signal vectors to realize the phase offsets—an inherently linear technique, since it depends solely on the matching of these orthogonal signals.  
         [0005]     The I/Q modulator provides a straightforward approach to generating phase-modulated signals that is also suitable for more complex schemes such as wideband Code-Division Multiple Access (CDMA) and Orthogonal Frequency Division Multiplexing (OFDM) systems. It is also possible to generate the phase-modulated signals using a phase-locked loop (PLL). This approach offers reduced circuitry and lower power consumption and, as a result, finds widespread use in narrowband systems. Unfortunately, the flexibility of the voltage-controlled oscillator (VCO) within the PLL architecture is limited. This is a severe disadvantage in multi-mode systems. It would therefore be advantageous to have a flexible, multi-mode VCO for use by a phase modulator.  
       SUMMARY OF THE INVENTION  
       [0006]     A very efficient system for multi-mode phase modulation is provided. Embodiments of the inventive system include circuitry for direct modulation of a multi-mode voltage-controlled oscillator (VCO) used in a phase-locked loop (PLL) to synthesize a radio frequency carrier signal.  
         [0007]     In one aspect the present invention is directed to a phase-locked loop module which includes a multi-mode voltage-controlled oscillator for generating an output signal of a frequency determined at least in part by a control voltage. The multi-mode voltage-controlled oscillator is characterized by a first frequency gain during operation in a first mode and a second frequency gain during operation in a second mode. The phase-locked loop module also includes divider circuit for dividing the output signal to produce a frequency-divided signal. A phase/frequency detector is disposed to compare phases between an input reference signal and the frequency-divided signal and to produce at least one phase error signal. A charge pump circuit produces a charge pump signal in response to the at least one phase error signal. A loop filter produces the control voltage in response to the charge pump signal.  
         [0008]     In another aspect the invention relates to a multi-mode voltage-controlled oscillator including a first input port, a second input port and an LC tank circuit. The LC tank circuit is configured to operate in accordance with a first frequency gain in response to a first signal received at the first input port and in accordance with a second frequency gain in response to a second signal received at the second input port.  
         [0009]     The present invention also pertains to a multi-mode modulation apparatus comprising a phase-locked loop and a switching network. The phase-locked loop includes a multi-mode voltage-controlled oscillator configured to realize a first frequency gain in response to a first control signal and a second frequency gain in response to a second control signal. The switching network is disposed to generate the first control signal during operation in a first mode and the second control signal during operation in a second mode.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     The foregoing aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:  
         [0011]      FIG. 1  shows a constellation diagram that illustrates how quaternary phase shift keying (QPSK) maps two-bit digital data to one of four offsets;  
         [0012]      FIG. 2  shows a diagram of a typical I/Q modulator;  
         [0013]      FIG. 3  shows a phase-locked loop (PLL) that is used to synthesize a radio frequency carrier signal;  
         [0014]      FIG. 4  shows a mathematical model of the PLL shown in  FIG. 3 ;  
         [0015]      FIG. 5  shows an integration filter;  
         [0016]      FIG. 6  shows one embodiment of a fractional-N PLL using a □□ modulator;  
         [0017]      FIG. 7  illustrates one embodiment of a fractional-N PLL that supports direct frequency or phase modulation;  
         [0018]      FIG. 8  shows a graph of the phase noise spectrum produced by a fractional-N PLL supporting direct modulation;  
         [0019]      FIG. 9  shows a graph that illustrates the relationship between PLL bandwidth and modulation accuracy of a fractional-N PLL supporting direct modulation;  
         [0020]      FIG. 10   a  shows a detailed view of a voltage-controlled oscillator (VCO);  
         [0021]      FIG. 10   b  shows one embodiment of a VCO tank circuit that includes an auxiliary port to support linear phase/frequency modulation;  
         [0022]      FIG. 11  shows the capacitance-voltage relationship for an accumulation-mode MOSFET device;  
         [0023]      FIG. 12  shows the linear capacitance-voltage response from back to back MOSFET devices;  
         [0024]      FIG. 13  shows one embodiment of a VCO tank circuit that includes two auxiliary ports to support direct phase/frequency modulation; and  
         [0025]      FIG. 14  shows one embodiment of a multi-mode phase/frequency modulator.  
     
    
     DETAILED DESCRIPTION  
       [0026]      FIG. 3  is a phase-locked loop (PLL)  305 . The PLL  305  includes a voltage-controlled oscillator (VCO)  310 , a feedback counter  320 , a phase/frequency detector (P/FD)  330 , a charge pump (CP)  340 , and an integration filter (LPF)  350 . Elements of the PLL  305  of  FIG. 3  are described by the mathematical model shown in  FIG. 4 .  
         [0027]     The PLL  305  uses feedback to minimize the phase difference between a very accurate reference signal and its output (RF) signal. As such, it produces an output signal at a frequency given by 
 
f VCO =Nf REF , 
 
 where f vco  is the frequency of the VCO  310  output signal, N is the value of the feedback counter  320 , and f REF  is the frequency of the reference signal. 
 
         [0028]     The VCO  310  produces an output signal at a frequency set by the control voltage v ctrl  according to 
 
 v   out ( t )= A  cos(ω 0   t+K   vco   ∫v   ctrl ( t ) dt ), 
 
 where ω o  is the free-running frequency of the VCO  310  and K vco  is the gain of the VCO  310 . The gain K vco  describes the relationship between the excess phase of the carrier Φ out  and the control voltage V ctrl  with  
               Φ   out     ⁡     (   s   )           v   ctrl     ⁡     (   s   )         =       K   vco     s       ,       
 
 where K vco  is in rads/V. The VCO  310  drives the feedback counter  320 , which simply divides the output phase Φ out  by N. 
 
         [0029]     When the PLL  305  is locked, the phase detector  330  and charge pump  340  generate an output signal i CP  that is proportional to the phase difference Δθ between the two signals applied to the phase detector  330 . The output signal i CP  can therefore be expressed as  
             i   CP     ⁡     (   s   )       =       K   pd     ⁢       Δ   ⁢           ⁢   θ   ⁢           ⁢     (   s   )         2   ⁢           ⁢   π           ,       
 
 where K pd  is in A/radians and Δθ is in radians. 
 
         [0030]     Attention is now drawn to  FIG. 5 , which depicts an implementation of the integration filter  350 . The integration filter  350  includes a resistor R 1    510  and capacitors C 1    520  and C 2    530 . As shown, the integration filter  350  transforms the output signal i CP  to the control voltage v ctrl  as follows  
             v   ctrl     ⁡     (   s   )       =         i   out     ⁡     (   s   )       ⁢     (           sR   1     ⁢     C   1       +   1           s   2     ⁢     R   1     ⁢     C   1     ⁢     C   2       +     s   ⁡     (       C   1     +     C   2       )           )         ,       
 
 where a zero (e.g., at 1/R 1 C 1 ) has been added to stabilize the second order system and the capacitor C 2    530  has been included to reduce any ripple on the control voltage V crtl . Combining the above relationships yields the composite open-loop transfer function  
           GH   ⁡     (   s   )       =       K   PD     ⁢         K   VCO     s     ⁡     [           sR   1     ⁢     C   1       +   1           s   2     ⁢     R   1     ⁢     C   1     ⁢     C   2       +     s   ⁡     (       C   1     +     C   2       )           ]           ,       
 
 which includes two poles at the origin (due to the VCO  310  and the integration filter  350 ). The closed-loop response of the system is  
           T   ⁡     (   s   )       =         NK   PD     ⁢       K   VCO     ⁡     (         sR   1     ⁢     C   1       +   1     )               s   3     ⁢     NR   1     ⁢     C   1     ⁢     C   2       +       s   2     ⁢     N   ⁡     (       C   1     +     C   2       )         +       K   PD     ⁢       K   VCO     ⁡     (         sR   1     ⁢     C   1       +   1     )               ,       
 
 which includes the stabilizing zero and two complex poles. The equation T(s) describes the response of the PLL  305  to the low-noise reference signal. 
 
         [0031]     The value N of the feedback counter  320  sets the output frequency of the PLL  305 . Its digital structure restricts N to integer numbers. As a result, the frequency resolution (or frequency step size) of the integer-N PLL  305  is nominally set by f REF . Fortunately, it is possible to dramatically decrease the effective frequency step by manipulating the value of N to yield a non-integer average value. This is the concept of a fractional-N PLL described with respect to  FIGS. 6, 7  and  14 .  
         [0032]      FIG. 6  is a fractional-N PLL  605  that uses a ΔΣ modulator  660  to develop non-integer values of N. The ΔΣ modulator  660  advantageously pushes spurious energy (created by the changing values of the feedback counter  620 ) to higher frequencies to be more effectively attenuated by the integration filter  650 . It can be shown that the effective value of N is simply the average value described by  
         N   =         ∑     x   =   1     P     ⁢     N   ⁡     [   x   ]         P       ,         
 where N[x] is the sequence of values of the feedback counter  620 . This expands to 
   N[x]=N   int   +n[x],    
 where N int  is the integer part and n[x] is the fractional part of N[x]. The ΔΣmodulator  660  generates the sequence n[x], that satisfies  
               ∑     x   =   1     P     ⁢           ⁢     n   ⁡     [   x   ]         P     =     k   M       ,         
 where k is the input to the ΔΣ modulator  660  with resolution M. In practice, the order of the ΔΣ modulator  660  dictates the range of n[x]. 
 
         [0033]     The ΔΣ modulator  660  introduces quantization noise that appears at the output of the PLL  605  along with other noise sources. These noise sources all map differently to the output of the PLL  605 , depending on the associated transfer function. Noise applied with the reference signal is affected by the transfer function described earlier. This transfer function is represented by  
             T   1     ⁡     (   s   )       =         NK   PD     ⁢       K   VCO     ⁡     (         sR   1     ⁢     C   1       +   1     )               s   3     ⁢     NR   1     ⁢     C   1     ⁢     C   2       +       s   2     ⁢     N   ⁡     (       C   1     +     C   2       )         +       K   PD     ⁢       K   VCO     ⁡     (         sR   1     ⁢     C   1       +   1     )               ,       
 
 which shows a low pass response. The above transfer function similarly shapes any noise at the output of the feedback counter  620 . Noise generated by the VCO  610  is subject to a different transfer function  
             T   2     ⁡     (   s   )       =         s             ⁢   2       ⁢     N   ⁡     (         sR             ⁢   1       ⁢     C             ⁢   1       ⁢     C             ⁢   2         +     C             ⁢   1       +     C             ⁢   2         )                     s             ⁢   2       ⁢     NR             ⁢   1       ⁢     C             ⁢   1       ⁢     C             ⁢   2         +                 s   ⁡     [       N   ⁢     (       C             ⁢   1       +     C             ⁢   2         )       +       K             ⁢   PD       ⁢     K             ⁢   VCO       ⁢     R             ⁢   1       ⁢     C             ⁢   1           ]       +       K             ⁢   PD       ⁢     K             ⁢   VCO                     ,       
 
 which shows a high pass response. 
 
         [0034]     The noise at the output of the feedback counter  620  is dominated by the ΔΣ modulator  660 . It creates a pseudo-random sequence n[x] possessing a quantization error approximately equal to ±½ N or  
         Δ   =     1   N       ,       
 
 It follows that the quantization noise spectral density for this error, assuming a uniform distribution, is expressed by  
           ⅇ   rms   2     ⁡     (   f   )       =       1     6   ⁢     N   2     ⁢     f   REF         .         
 
 over the frequency range of dc to f REF /2. This quantization noise is advantageously shaped by an L th  order ΔΣ modulator  660  according to 
 
 DS ( z )=(1 −z   −1 ) L . 
 
 In the PLL  605 , the feedback counter  620  acts as a digital accumulator and reduces the effects of the ΔΣ modulator  660 . That is, the output phase from the feedback counter  620  depends on its previous output phase. The transfer function for the feedback counter  620  is therefore  
           P   ⁡     (   z   )       =     2   ⁢           ⁢   π   ⁢       z     -   1         1   -     z     -   1               ,       
 
 Combining these terms shows that the output noise of the feedback counter  620  is equal to 
 
 n   2 ( f )= rms   2 ( f )[ DS ( f )] 2   [P ( f )] 2 , 
 
 which yields  
             n   2     ⁡     (   f   )       =       2   3     ⁢           π   2         N   2     ⁢     f   REF         ⁡     [     2   ⁢           ⁢     sin   ⁡     (       π   ⁢           ⁢   f       f   REF       )         ]       L         ,       
 
 and appears at the output of the PLL  605  shaped by transfer function T 1 (s) presented above. Direct phase/frequency modulation further increases phase noise because an additional noise source is added to the system of  FIG. 6 . 
 
         [0035]      FIG. 7  shows a fractional-N PLL  705  supporting direct VCO modulation. The system of  FIG. 7  directly modulates the VCO  710  and thereby controls the frequency of the VCO  710 . To realize phase modulation, the modulation signal PM(t) must therefore be differentiated (e.g., via a differentiator device  770 ) with  
         fm   ⁡     (   t   )       =         ⅆ     ⅆ   t       ⁡     [     pm   ⁡     (   t   )       ]       .           
 This is due to the fundamental relationship  
           θ   ⁢           ⁢     (   t   )       =       ∫   0   t     ⁢       f   ⁡     (   t   )       ⁢           ⁢     ⅆ   t           ,         
 which shows that frequency integrates over time. 
 
         [0036]     Any noise present at the frequency modulation (FM) port of the VCO  710  appears at the output of the PLL  705  (e.g., RF signal), modified by the following transfer function  
           T   3     ⁡     (   s   )       =           s   2     ⁢       NK   FM     ⁡     (         sR   1     ⁢     C   1     ⁢     C   2       +     C   1     +     C   2       )                     s   2     ⁢     NR   1     ⁢     C   1     ⁢     C   2       +     s   [       N   ⁡     (       C   1     +     C   2       )       +                         K   PD     ⁢     K   VCO     ⁢     R   1     ⁢     C   1       ]     +       K   PD     ⁢     K   VCO                 .         
 
 As shown in chart  800  of  FIG. 8 , any noise associated with an FM signal v FM  adds to the system and increases the phase noise spectrum. 
 
         [0037]     The feedback of the PLL  705  naturally resists the direct phase/frequency modulation of the VCO  710 . To avoid this effect, the FM signal is also applied to the feedback counter  720  through the ΔΣ modulator  760 . This ideally subtracts the frequency modulation applied at the VCO  710  so that the output of the counter  720  represents only the RF carrier frequency.  
         [0038]     Direct VCO modulation requires near exact control of the frequency of the VCO  710 . This is because frequency errors produce phase deviations that accumulate with time. Fortunately, the feedback of the PLL  705  helps to reduce any frequency error. This is because the output of the VCO  710  is driven by the feedback of the PLL  705  to exactly 
 
 f   VCO   =Nf   REF   +RMf   REF , 
 
 which is also essentially equal to 
 
 f   VCO   =K   VCO   v   ctrl   +K   FM   v   FM , 
 
 where v ctrl  is the error signal produced by the phase/frequency detector  730 , v FM  is the FM signal applied to the VCO  710 , and K FM  is the gain of the VCO  710  associated with the FM signal. Consequently, the error signal v ctrl  compensates for any VCO  710  gain errors within the bandwidth of the integration filter  750 . 
 
         [0039]     Outside the bandwidth of the PLL  705 , the effect of the feedback decreases. This makes setting the gain K FM  of the VCO  710  (“VCO gain K FM ”) to its designed value critical. As illustrated by chart  900  of  FIG. 9 , it also means a wider bandwidth can achieve better modulation accuracy. In the EDGE transmit system, the modulation accuracy (measured using error vector magnitude (EVM)) improves significantly as the bandwidth of the PLL  705  increases from 25 k to 75 kHz.  
         [0040]     Calibration is required to accurately set the VCO gain K FM . This can be accomplished by scaling the FM signal (e.g., by α in  FIG. 7 ) to compensate for variations in the VCO gain K FM  and thereby stabilizing the K FM v FM  product. Ideally, the VCO gain K FM  should be set low to minimize the added noise from the FM signal. This is because the VCO gain K FM  amplifies the added noise (due to circuit and quantization effects) associated with the FM signal. In practice, the VCO gain K FM  cannot be set too low as there are linearity issues as well as FM signal amplitude limits.  
         [0041]     The K FM v FM  product sets the range of the frequency modulation. That is, the maximum frequency deviation Δf max  is simply 
 
Δ f   max   =K   FM max( v   FM ), 
 
 where max(v FM ) represents the peak or amplitude of the FM signal. In general, the required Δf max  for reasonable performance is about four to five times the system&#39;s symbol rate. 
 
         [0042]     The design shown in  FIG. 7  of the direct VCO modulation system for multi-mode applications is complicated. It requires the ability to achieve different Δf max  ranges and as such different K FM v FM  products. In practice, the VCO gain K FM  must be set for the largest required Δf max  since the FM signal amplitude is limited. This means any different K FM v FM  products are achieved by changing α and thereby scaling the FM signal. Unfortunately, scaling (e.g., reducing) the amplitude of the FM signal may increase the added noise in the system of  FIG. 7 . This can be unacceptable when the symbol rate and Δf max  change dramatically. For example, the symbol rate for GSM/EDGE is 270 ksps while it is 3.84 Msps, or about 14 times larger, for WCDMA.  
         [0043]     The multi-mode VCO  710  provides selectable gains K FM  to optimally accommodate the different frequency modulation ranges Δf max . This advantageously allows the amplitude of the FM signal to remain close to its maximum limit, which minimizes added noise.  
         [0044]     A detailed view of the VCO  710  is shown in  FIG. 10   a . The VCO  710  oscillates at a frequency  
           f   osc     =     1     2   ⁢           ⁢   π   ⁢         (       L   1     +     L   2       )     ⁢     C   eq               ,       
 
 which is set by the resonance of the LC tank circuit shown in  FIG. 10   a , where C eq  is the equivalent shunt capacitance (comprised of capacitor C 1  and varactors C 2a -C 2b  plus any parasitic capacitance). The equivalent capacitance C eq  may also include coarse-tuning capacitors (not shown) to subdivide the tuning range. The varactor C 2  (shown as C 2a  and C 2b ) allows the VCO  710 , by way of the control signal v ctrl , to be tuned to different radio frequencies. 
 
         [0045]     The LC tank circuit shown in  FIG. 10   b  includes an auxiliary port to support linear phase/frequency modulation. As illustrated in chart  1100  of  FIG. 11 , the LC tank circuit uses the capacitance of accumulation-mode MOSFET devices N 3  and N 4  to achieve linear behavior even though these devices display an abrupt response. The accumulation-mode MOSFET devices present a low capacitance C min  at applied gate-to-bulk voltages V GB  below the threshold voltage V T  while they display a high capacitance C max  at applied voltages above V T . Capacitors C 4   a  and C 4   b  block the dc level present at the output of the VCO  710 . Resistors Z 1 -Z 2  provide some isolation between the gates of MOSFET devices N3 and N4.  
         [0046]     The gate-to-bulk voltage VGB applied to each MOSFET device N 3 -N 4  depends on the VCO&#39;s  710  output signal Asin ωt, the FM signal v FM , and the common-mode voltage V cm  that exists at the connection of the back-to-back devices. The symmetric structure of the VCO  710  means that signals VLO+ and VLO− V 1  and V 2  are differential with 
 
V LO+ =A sin ωt &amp; V LO− =−A sin ωt, 
 
 where A is the peak signal of each sinusoidal output and is the oscillation frequency. It follows then that 
 
 V   C3   =A  sin ω t+v   FM   −v   cm   &amp; V   C3   =−a  sin ω t+v   FM   −v   cm , 
 
         [0047]     which describe the gate-to-bulk voltages V GB  applied to MOSFET devices N 3  and N 4 . The two MOSFET devices N 3  and N 4  connect back-to-back in the VCO  710 , so their individual capacitances behave oppositely.  
         [0048]     The modulation signal v FM  affects the MOSFET devices N 3  and N 4  as follows. The devices nominally present a capacitance equal to  
         C   mid     =         C   FM     ⁡     (       v   FM     =   0     )       =           C   min     ⁢     C   max           C   min     +     C   max         .           
 
 As the FM signal v FM  moves positive, both MOSFET devices N 3  and N 4  reach their maximum capacitance values C max , so that for a period of time of approximately  
         t   =       1   ω     ⁢       sin     -   1       ⁡     (     -       v   FM     A       )           ,       
 
 the structure in  FIG. 10   b  presents a capacitance equal to C max /2. A similar response occurs as the FM signal moves negative, which results in the structure in  FIG. 10   b  presenting a capacitance equal to C min /2. It is worth noting that the structure in FIG.  10   b  linearizes the overall response of the accumulation-mode MOSFET devices N 3  and N 4  to yield the behavior shown in  FIG. 12 . 
 
         [0049]      FIG. 13  depicts two auxiliary ports (VFM 1  and VFM 2 ) in the VCO  710  that each support a different frequency modulation range Δf max . As shown in  FIG. 13 , the additional auxiliary port is formed by simply adding another branch of accumulation-mode MOSFET devices N 5  and N 6  to the resonant tank of the VCO  710 .  
         [0050]     As illustrated in  FIG. 14 , a simple switch network  1480  enables the FM signal to drive the multi-mode VCO  1410 . One or more filters  1490  may be included to smooth the FM signal after it is scaled by α, and to attenuate any alias signals. Each mode of the VCO  1410  requires calibration to operate accurately. Since the VCO gain K FM  is constant in each of the modes, the calibration scales the FM signal by a, where different values for by α are applied for each mode. Ideally, the system illustrated in  FIG. 14  produces similar FM signal amplitudes for the different modes, thus minimizing added noise. As a benefit of the present invention, the multi-mode VCO  1410  enables direct VCO modulation architecture to meet stringent phase noise and modulation accuracy requirements in vastly different modes.  
         [0051]     Those skilled in the art can readily recognize that numerous variations and substitutions may be made in the invention, its use and its configuration to achieve substantially the same results as achieved by the embodiments described herein. Accordingly, there is no intention to limit the invention to the disclosed exemplary forms. Many variations, modifications and alternative constructions fall within the scope and spirit of the disclosed invention as expressed in the claims.