Abstract:
A current limiting circuit for limiting an output current in response to a control current includes a detection circuit to detect a detection voltage responsive to an output voltage, and a control current generating circuit to generate a control current responsive to the detection voltage, wherein the control current generating circuit includes a first transistor through which the control current flows, a second transistor that becomes conductive upon a voltage responsive to an amount of the control current being greater than a predetermined voltage above the detection voltage, and a resistor connecting between a base and an emitter of the second transistor to raise a potential at the base of the second transistor above a predetermined level, wherein the amount of the control current flowing through the first transistor decreases as an amount of a current flowing through the second transistor increases.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The disclosures herein relate to a current limiting circuit which includes a detection circuit for detecting a detection voltage responsive to an output voltage and a control current generating circuit for generating a control current responsive to the detection voltage thereby to limit an output current in response to the control current, and also relate to a power-supply circuit having such a current limiting circuit. 
     2. Description of the Related Art 
       FIG. 3  is a drawing illustrating an example of a related-art power supply circuit. A power supply circuit  10  includes a reference voltage generating circuit  11 , a bias circuit  12 , a detection circuit  13 , a control circuit  14 , a current limiting circuit  15 , and a current control transistor Q 1 . 
     The reference voltage generating circuit  11  and the bias circuit  12  are situated between an input terminal Tin and a ground terminal Tgnd. The detection circuit  13  includes resistors R 5  and R 6  situated between an output terminal Tout and the ground terminal Tgnd, thereby dividing an output voltage Vout appearing between the output terminal Tout and the ground terminal Tgnd. The voltage resulting from potential division by the resistors R 5  and R 6  is a voltage responsive to the output voltage Vout. This voltage is supplied to the control circuit  14  as a detection voltage Vs. 
     The control circuit  14  includes a differential amplifier circuit  21  and a transistor Q 2 . The non-inverted input node of the differential amplifier circuit  21  receives a reference voltage Vref from the reference voltage generating circuit  11 , and the inverted input node of the differential amplifier circuit  21  receives the detection voltage Vs from the detection circuit  13 . 
     The differential amplifier circuit  21  outputs an electric current responsive to a difference between the reference voltage Vref and the detection voltage Vs. The output current of the differential amplifier circuit  21  is supplied to a transistor Q 2 . The transistor Q 2  is an NPN transistor. 
     The base of the transistor Q 2  receives the output of the differential amplifier circuit  21  and the output of the current limiting circuit  15 . The collector of the transistor Q 2  is connected to the base of the current control transistor Q 1  and to the base of a transistor Q 3  that is part of the current limiting circuit  15 . The emitter of the transistor Q 2  is connected to the ground terminal Tgnd, so that the collector current of the transistor Q 2  is converted into a voltage (i.e., I-V conversion). 
     In response to the outputs of the differential amplifier circuit  21  and the current limiting circuit  15 , the transistor Q 2  controls the potential of the bases of the current control transistor Q 1  and the transistor Q 3  that is part of the control circuit  14 . The transistor Q 1  is a PNP transistor. The current control transistor Q 1  has the emitter thereof connected to the input terminal Tin, the collector thereof connected to the output terminal Tout, and the base thereof connected to the collector of the transistor Q 2 . The current control transistor Q 1  supplies a current responsive to the collector potential of the transistor Q 2  from the input terminal Tin to the output terminal Tout. 
     The current limiting circuit  15  includes transistors Q 3  through Q 6  and resistors R 1  through R 4 . The resistors R 3  and R 4  are connected in series between the output terminal Tout and the ground terminal Tgnd, thereby dividing the output voltage Vout. The voltage obtained by the division is supplied to the base of a transistor Q 4 . 
     The transistor Q 4  is a PNP transistor. The transistor Q 4  has the base thereof connected to the joining point between the resistor R 3  and the resistor R 4 , the emitter thereof coupled via the resistor R 2  to the collector of the transistor Q 3 , and the collector thereof connected to the collector and base of the transistor Q 5 . 
     The transistor Q 5  is an NPN transistor. The transistor Q 5  has the collector thereof connected to the collector of the transistor Q 4 , the emitter thereof connected to the ground terminal Tgnd, and the base thereof connected to the collector of the transistor Q 4  and to the base of the transistor Q 6 . 
     The transistor Q 6  is an NPN transistor. The transistor Q 6  has the collector thereof connected to the base of the transistor Q 2 , the emitter thereof connected to the ground terminal Tgnd, and the base thereof connected to the base and collector of the transistor Q 5 . The transistors Q 5  and Q 6  constitute a current mirror circuit, which pulls from the base of the transistor Q 2  a current responsive to the collector current Ic 4  of the transistor Q 4 . 
     The resistor R 1  connects between the collector of the transistor Q 3  and the ground terminal Tgnd. The transistor Q 3  is a PNP transistor. The transistor Q 3  has the emitter thereof connected to the input terminal Tin, the collector thereof connected to the resistors R 1  and R 2 , and the base thereof connected to the collector of the transistor Q 2 . The transistor Q 3  supplies a current responsive to the collector potential of the transistor Q 2  to the resistor R 1  and the resistor R 2 . The transistors Q 1  and Q 3  have such device areas that when the collector current of the current control transistor Q 1  is Io, the collector current of the transistor Q 3  is equal to Io/n. 
     In the power supply circuit  10 , as the voltage Vt obtained by the I-V conversion of the collector current of the transistor Q 3  rises to a threshold voltage of the current limiting circuit  15  that is equal to (R 4 /(R 3 +R 4 ))Vout+Vbe 4 , the transistor Q 4  is turned on to activate a current limiting function. Here, Vbe 4  is the base-emitter voltage of the transistor Q 4 . 
     Upon the activation of the current limiting function, the output voltage Vout drops, resulting in a drop of the voltage (=R 4 /(R 3 +R 4 )Vout) at the joining point between the resistor R 3  and the resistor R 4 . This arrangement is expected to provide current-to-voltage characteristics as illustrated in  FIG. 4 .  FIG. 4  is a drawing illustrating the current-to-voltage characteristics of the related-art power supply circuit. 
     A power supply circuit that has a current limiting circuit expected to provide the current-to-voltage characteristics illustrated in  FIG. 4  is disclosed in Japanese Patent Application Publication No. 2002-304225, for example. 
     In the related-art power supply circuit described above, a drop of the output voltage Vout to the ground potential results in the base potential of the transistor Q 4  being at the ground potential, which places the transistor Q 4  in the saturated region. As the transistor Q 4  is placed in the saturated region, a parasitic device Q 7  as illustrated in  FIG. 5  is turned on.  FIG. 5  is a drawing illustrating an example of a related-art power supply circuit that includes a parasitic device. 
     With the parasitic device Q 7  being turned on, the current-to-voltage characteristics of the power supply circuit  10  become the characteristics as illustrated in  FIG. 6 , thereby failing to provide the desired characteristics illustrated in  FIG. 4 .  FIG. 6  is a drawing illustrating the current-to-voltage characteristics of a related-art power supply circuit that includes a parasitic device. 
     Accordingly, it may be desirable to provide a power supply circuit and a current limiting circuit that can provide desired current-to-voltage characteristics. 
     SUMMARY OF THE INVENTION 
     According to an embodiment, a current limiting circuit for limiting an output current in response to a control current includes a detection circuit to detect a detection voltage responsive to an output voltage, and a control current generating circuit to generate a control current responsive to the detection voltage, wherein the control current generating circuit includes a first transistor through which the control current flows, a second transistor that becomes conductive upon a voltage responsive to an amount of the control current being greater than a predetermined voltage above the detection voltage, and a resistor connecting between a base and an emitter of the second transistor to raise a potential at the base of the second transistor above a predetermined level, wherein the amount of the control current flowing through the first transistor decreases as an amount of a current flowing through the second transistor increases. 
     According to an embodiment, a power supply circuit includes a first detection circuit to detect a first detection voltage responsive to an output voltage, a control circuit to control the output voltage to keep the output voltage constant in response to the first detection voltage, and a current limiting circuit to limit an amount of a control current to which an amount of an output current is proportional, wherein the current limiting circuit includes a second detection circuit to detect a second detection voltage responsive to the output voltage, and a control current generating circuit to generate the control current in response to the second detection voltage, wherein the control current generating circuit includes a first transistor through which the control current flows, a second transistor that becomes conductive upon a voltage responsive to an amount of the control current being greater than a predetermined voltage above the second detection voltage, and a resistor connecting between a base and an emitter of the second transistor to raise a potential at the base of the second transistor above a predetermined level, wherein the amount of the control current flowing the first transistor decreases as an amount of a current flowing through the second transistor increases. 
     According to at least one disclosed embodiment, desired output-current-to-output-voltage characteristics are obtained. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a drawing illustrating a power supply circuit according to the first embodiment; 
         FIG. 2  is a drawing illustrating a power supply circuit according to the first embodiment; 
         FIG. 3  is a drawing illustrating an example of a related-art power supply circuit; 
         FIG. 4  is a drawing illustrating the current-to-voltage characteristics of the related-art power supply circuit; 
         FIG. 5  is a drawing illustrating an example of a related-art power supply circuit that includes a parasitic device; and 
         FIG. 6  is a drawing illustrating the current-to-voltage characteristics of the related-art power supply circuit that includes a parasitic device. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     In embodiments disclosed herein, provision is made such that the parasitic device of the current limiting circuit is not turned on. 
     First Embodiment 
     In the following, a first embodiment will be described with reference to the accompanying drawings.  FIG. 1  is a drawing illustrating a power supply circuit according to the first embodiment. 
     A power supply circuit  100  of the present embodiment includes a reference voltage generating circuit  110 , a bias circuit  120 , a detection circuit  130 , a control circuit  140 , a current limiting circuit  150 , and a current control transistor Q 10 . 
     The reference voltage generating circuit  110  and the bias circuit  120  are situated between an input terminal Tin and a ground terminal Tgnd. The detection circuit  130  includes resistors R 50  and R 60  situated between an output terminal Tout and the ground terminal Tgnd, thereby dividing an output voltage Vout appearing between the output terminal Tout and the ground terminal Tgnd. The voltage resulting from potential division by the resistors R 50  and R 60  is a voltage responsive to the output voltage Vout. This voltage is supplied to the control circuit  140  as a detection voltage Vs. 
     The control circuit  140  includes a differential amplifier circuit  141  and a transistor Q 20 . The non-inverted input node of the differential amplifier circuit  141  receives a reference voltage Vref from the reference voltage generating circuit  110 , and the inverted input node of the differential amplifier circuit  141  receives the detection voltage Vs from the detection circuit  130 . 
     The differential amplifier circuit  141  outputs an electric current responsive to a difference between the reference voltage Vref and the detection voltage Vs. The output current of the differential amplifier circuit  141  is supplied to a transistor Q 20 . The transistor Q 20  is an NPN transistor. 
     The base of the transistor Q 20  receives the output of the differential amplifier circuit  141  and the output of the current limiting circuit  150 . The collector of the transistor Q 20  is connected to the base of the current control transistor Q 10  and to the base of a transistor Q 30  that is part of the current limiting circuit  150 . The emitter of the transistor Q 20  is connected to the ground terminal Tgnd, so that the collector current of the transistor Q 20  is converted into a voltage (i.e., I-V conversion). 
     In response to the outputs of the differential amplifier circuit  141  and the current limiting circuit  150 , the transistor Q 20  controls the potential of the bases of the current control transistor Q 10  and the transistor Q 30  that is part of the control circuit  140 . The transistor Q 10  is a PNP transistor. The current control transistor Q 10  has the emitter thereof connected to the input terminal Tin, the collector thereof connected to the output terminal Tout, and the base thereof connected to the collector of the transistor Q 20 . The current control transistor Q 10  supplies a current responsive to the collector potential of the transistor Q 20  from the input terminal Tin to the output terminal Tout. 
     The current limiting circuit  150  includes transistors Q 30  through Q 60  and resistors R 10 , R 20 , R 30 , R 40 , and R 70 . The resistors R 30  and R 40  are connected in series between the output terminal Tout and the ground terminal Tgnd, thereby dividing the output voltage Vout. The voltage obtained by the division is supplied to the base of a transistor Q 40 . 
     The transistor Q 40  is a PNP transistor. The base of the transistor Q 40  is connected to the joining point between the resistor R 30  and the resistor R 40  and to the resistor R 70 . The transistor Q 40  has the emitter thereof coupled to the collector of the transistor Q 30  via the resistor R 20 , and has the collector thereof connected to the collector and base of the transistor Q 50 . The resistor R 70  connects between the base and emitter of the transistor Q 40 . 
     The transistor Q 50  is an NPN transistor. The transistor Q 50  has the collector thereof connected to the collector of the transistor Q 40 , the emitter thereof connected to the ground terminal Tgnd, and the base thereof connected to the collector of the transistor Q 40  and to the base of the transistor Q 60 . 
     The transistor Q 60  is an NPN transistor. The transistor Q 60  has the collector thereof connected to the base of the transistor Q 20 , the emitter thereof connected to the ground terminal Tgnd, and the base thereof connected to the base and collector of the transistor Q 50 . The transistors Q 50  and Q 60  constitute a current mirror circuit, which pulls from the base of the transistor Q 20  a current responsive to the collector current of the transistor Q 40 . 
     The resistor R 10  connects between the collector of the transistor Q 30  and the ground terminal Tgnd. The transistor Q 30  is a PNP transistor. The transistor Q 30  has the emitter thereof connected to the input terminal Tin, the collector thereof connected to the resistors R 10  and R 20 , and the base thereof connected to the collector of the transistor Q 20 . The transistor Q 30  supplies a current responsive to the collector potential of the transistor Q 20  to the resistor R 10  and the resistor R 20 . The current control transistors Q 10  and the transistor Q 30  have such device areas that when the collector current of the current control transistor Q 10  is Io, the collector current of the transistor Q 30  is equal to Io/n. 
     In the power supply circuit  100 , as the voltage Vt obtained by the I-V conversion of the collector current of the transistor Q 30  rises to the voltage (R 40 /(R 30 +R 40 ))Vout+Vbe 40 , the transistor Q 40  is turned on to activate a current limiting function. Namely, as the current flowing through the transistor Q 40  increases, the control current flowing through the transistor Q 30  decreases, and so does the output current. Here, Vbe 40  is the base-emitter voltage of the transistor Q 40 . 
     Upon the activation of the current limiting function, the output voltage Vout drops, resulting in a drop of the voltage Vb at the joining point between the resistor R 30  and the resistor R 40  applied to the base of the transistor Q 40 . 
     In the present embodiment, the voltage Vb is represented as follows.
 
 Vb =( R 40/( R 30+ R 40))×( V out+( R 30/ R 70)× Vbe 40)
 
When the output voltage Vout becomes 0 V, i.e., when the output is short-circuited, the voltage Vb is expressed as follows.
 
 Vb =(( R 30× R 40)/( R 30+ R 40))×( Vbe 40/ R 70)
 
In the present embodiment, the provision of the resistor R 70  between the emitter and base of the transistor Q 40  produces a constant current equal in amount to Vbe 40 /R 70 . This constant current is supplied to the joining point between the resistor R 30  and the resistor R 40  to raise the voltage Vb. The rise of the voltage Vb prevents the parasitic device Q 70  from being turned on in response to a drop in the potential at the base of the parasitic device Q 70  below the threshold voltage.
 
     According to the present embodiment described above, a simple configuration prevents the parasitic device Q 70  from being turned on, thereby providing the desired current-to-voltage characteristics as illustrated in  FIG. 4 . 
     In the present embodiment, the use of a lateral PNP transistor serves to simplify the configuration of a transistor, and, at the same time, the parasitic device Q 70  resulting from the use of the lateral PNP transistor is kept turned off. 
     Second Embodiment 
     In the following, a second embodiment will be described with reference to the accompanying drawings. The second embodiment differs from the first embodiment only in that a diode is provided in the current limiting circuit for the purpose of improving the temperature characteristics of transistors. In the description of the second embodiment in the following, differences from the first embodiment are only described. The same or similar elements as those of the first embodiment are referred to by the same or similar reference symbols, and a description thereof will be omitted. 
       FIG. 2  is a drawing illustrating a power supply circuit according to the second embodiment. 
     A power supply circuit  100 A of the present embodiment includes a current limiting circuit  150 A. The current limiting circuit  150 A of the present embodiment includes a diode D 1  arranged between the resistor R 10  and the ground terminal Tgnd. The diode D 1  serves to compensate for temperature with respect to the collector current Ic 40  of the transistor Q 40 . 
     The threshold voltage Vt at which the current limiting function of the current limiting circuit  150 A is activated is expressed as follows.
 
 Vt =( R 40/( R 40+ R 30))× V out+ Vbe 40
 
Further, a voltage Vt 1  detected by the current control transistor Q 10  and the transistor Q 30  is expressed as follows.
 
 Vt 1= VD 1+ R 10× Ic 30
 
Here, VD 1  is the forward voltage of the diode D 1 , and Ic 30  is the collector current of the transistor Q 30 .
 
     The temperature characteristics of the forward voltage VD 1  of the diode D 1  and the temperature characteristics of the base-emitter voltage Vbe 40  of the transistor Q 40  cancel each other. The present embodiment thus improves the temperature characteristics of the current limiting circuit  150 A. 
     Further, the present invention is not limited to these embodiments disclosed herein, but various variations and modifications may be made without departing from the scope of the present invention. 
     The present application is based on Japanese priority application No. 2010-258672 filed on Nov. 19, 2010, with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.