Abstract:
A semiconductor device for electrostatic discharge protection includes a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The first, second, third, and fourth heavily-doped regions have the first, second, second, and first conductivity types, respectively. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface.

Description:
FIELD OF THE INVENTION 
       [0001]    The present disclosure relates to a semiconductor device for electrostatic discharge (ESD) protection. 
       BACKGROUND OF THE INVENTION 
       [0002]    Electrostatic discharge (ESD) is a natural phenomenon occurring frequently in daily life. ESD can generate a large current in a short period of time. For example, a human body model (HBM) electrostatic discharge usually occurs within several hundreds of nanosecond, with a peak current of several amperes. Electrostatic discharge of some other modes, such as a machine model (MM) and a charged device model (CDM), may occur in a shorter period of time and may have a larger current. 
         [0003]    When the large current generated by the ESD passes through an integrated circuit in a short period of time, it may result in a power consumption much higher than what the integrated circuit can bear, causing physical damage to the integrated circuit and, possibly, circuit failure. In fact, ESD has become a major factor that causes failure of integrated circuits during their manufacture and use. 
         [0004]    In practice, two approaches have been followed to reduce or prevent damage caused by ESD: the environment and the circuit itself. With regard to the environment, the approach mainly involves reducing the production of static electricity and timely removing the generated static electricity, such as using materials that do not easily generate static electricity, increasing the environment humidity, or grounding operators and/or apparatuses. With regard to the circuit, the approach mainly involves improving the ESD resistivity of the circuit, such as by using an ESD protection device or circuit to protect the internal circuit from ESD damages. 
         [0005]    With regard to using an. ESD protection device, a trigger voltage of the ESD protection device should be lower than that of the device being protected. The ESD protection device should also have a capability of discharging current. In addition, the DC breakdown voltage of the ESD protection device should be higher than the power source voltage. The ESD protection device should meet such conditions so as to not impact the operation of the device being protected. To avoid a problem of latching up, a holding voltage of the ESD protection device should be higher than the power source voltage. 
       SUMMARY OF THE INVENTION 
       [0006]    Consistent with embodiments of the present disclosure, there is provided a semiconductor device for electrostatic discharge protection. The semiconductor device comprises a substrate, a first well and a second well formed in the substrate. The first and second wells are formed side by side, meeting at an interface, and have a first conductivity type and a second conductivity type, respectively. A first heavily doped region and a second heavily-doped region are formed in the first well. The first and second heavily-doped regions have the first and the second conductivity types, respectively, and are positioned at a first distance and a second distance from the interface, respectively. A third heavily doped region and a fourth heavily-doped region are formed in the second well. The third and fourth heavily-doped regions have the second and the first conductivity types, respectively, and are positioned at a third distance and a fourth distance from the interface, respectively. The fourth distance is different from the third distance. Positions of the first and second heavily-doped regions are staggered along a direction parallel to the interface. 
         [0007]    Features and advantages consistent with the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosure. Such features and advantages will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
         [0008]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
         [0009]    The accompanying drawings, which are incorporated, in and constitute a part of this specification, illustrate several embodiments and together with the description, serve to explain the principles of the invention. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]      FIG. 1A  is a plan view schematically showing a layout of an SCR structure according to an exemplary embodiment. 
           [0011]      FIG. 1B  is an enlarged plan view schematically showing a portion of the SCR structure of  FIG. 1A . 
           [0012]      FIGS. 2A and 2B  are schematic cross-sectional views of the SCR structure of  FIG. 1A  along section line AA′ and line BB′, respectively. 
           [0013]      FIG. 3  shows an equivalent circuit of the SCR structure of  FIG. 1A . 
           [0014]      FIG. 4  is a plan view schematically showing a layout of an SCR structure according to an exemplary embodiment. 
           [0015]      FIG. 5  is a plan view schematically showing a layout of an SCR structure according to an exemplary embodiment. 
           [0016]      FIG. 6  is a plan view schematically showing a layout of an SCR structure according to an exemplary embodiment. 
           [0017]      FIG. 7  is a plan view schematically showing a layout of an SCR structure according to an exemplary embodiment. 
       
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       [0018]    Embodiments consistent with the disclosure include a silicon-controlled rectifier (SCR) structure for electrostatic discharge (ESD) protection. 
         [0019]    Hereinafter, embodiments consistent with the disclosure will be described with reference to drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
         [0020]    An silicon-controlled rectifier (SCR) is a device that can be used for ESD protection. As used herein, an SCR comprises an N-well and a P-well formed adjacent to each other, with a heavily doped P-type (P + ) region and a heavily doped N-type (N + ) region formed in the N-well and the P-well, respectively. Therefore, the basic structure of the SCR comprises a PNPN structure, where the P +  region, the N-well, and the P-well form a PNP transistor, while the N-well, the P-well, and the N +  region form an NPN transistor. 
         [0021]    In operation, the SCR is usually connected in parallel with the circuit to be protected. When ESD occurs, excessive charges are generated by ESD, which increase the voltage applied to the SCR. When the voltage applied to the SCR becomes higher than a trigger voltage of the SCR, avalanche breakdown may occur at the N-P junction formed by the N-well and the P-well. The generated current turns on one of the PNP transistor or the NPN transistor. Both of the PNP and the NPN transistors then become saturated. As a result, the SCR enters into a low-resistance state, and starts to conduct the major portion of the charges generated by the ESD. Consequently, the circuit being protected bears only a minor portion of the ESD charges, and thus avoids being damaged. After the SCR enters into the low-resistance state and the ESD charges are being conducted by the SCR, the voltage applied to the SCR decreases. When the voltage applied to the SCR becomes lower than a holding voltage of the SCR, the SCR turns off. 
         [0022]      FIG. 1A  is a plan view schematically showing a layout of an SCR structure  100  consistent with embodiments of the present disclosure.  FIG. 1B  is an enlarged plan view schematically showing a portion of the SCR structure  100 .  FIGS. 2A and 2B  are cross-sectional views of the SCR. structure  100  along line AA′ and line BB′ in  FIG. 1A , respectively. The SCR structure  100  includes an N-well  102  and a P-well  104  formed in a substrate  106 . The N-well  102  and P-well  104  are arranged side by side and meet at an interface  110 . 
         [0023]    In some embodiments, the N-well  102  and the P-well  104  may be formed by doping N-type impurities and P-type impurities, respectively, into the substrate  106  via, for example, implantation or diffusion. In some embodiments, the substrate  106  may be an N-type substrate. The P-well  104  may be formed by doping P-type impurities into a portion of the N-type substrate  106 , while another portion of the N-type substrate  106  that is not doped with the P-type impurities may be used as the N-well  102 . 
         [0024]    Alternatively, in some embodiments, the substrate  106  may be a P-type substrate. The N-well  102  may be formed by doping N-type impurities into the P-type substrate  106 , and another portion of the P-type substrate  106  that is not doped with the N-type impurities may be used as the P-Well  104 . 
         [0025]    In some embodiments, the substrate  106 , whether P-type or N-type, may be a silicon substrate or a silicon-on-insulator (SOI) substrate. The N-type impurities for forming N-well  102 , and those in substrate  106  when substrate  106  is provided as N-type, include phosphorus, arsenic, or antimony. The P-type impurities for forming P-well  104 , and those in substrate  106  when substrate  106  is provided as P-type, include boron or aluminum. The impurity concentrations in the N-well  102  and the P-well  104  may be about 1×10 15  cm −3  to about 1×10 17  cm −3  and about 1×10 16  cm −3  to about 1×10 17  cm −3 , respectively. 
         [0026]    As shown in  FIG. 1A , a heavily-doped N-type region (N +  region)  122  and a heavily-doped P-type region (P +  region)  124  are formed in the N-well  102 . Similarly, a heavily-doped P-type region (P 3+  region)  142  and a heavily-doped N-type region (N +  region)  144  are formed in the P-well  104 . The heavily-doped regions  122 ,  124 ,  142 , and  144  have a doping level (impurity concentration) higher, for example, more than two orders of magnitude higher, than that of the N-well  102  and the P-well  104 . The N +  regions  122  and  144  are doped with N-type impurities, such as phosphorus, arsenic, or antimony. The P +  regions  124  and  142  are doped with P-type impurities, such as boron or aluminum. In some embodiments, the impurity concentration in each of the region  122 , P +  region  124 , P +  region  142 , and N +  region  144  may be about 1×10 10  cm 3  to about 5×10 20  cm −3 . The concentrations in these heavily-doped regions may be the same as or different from each other. 
         [0027]    As shown in  FIG. 1A , the N +  region  122  and the P +  region  124  in the N-well  102  are staggered along a direction perpendicular to the interface  110 , i.e., staggered along the x-direction depicted in  FIG. 1A . That is, as shown in the enlarged view in  FIG. 1B , a left edge  1222  of the N +  region  122  does not align with a left edge  1242  of the P +  region  124 . Similarly, a right edge  1224  of the N +  region  122  does not align with a right edge  1244  of the P +  region  124 . The N +  region  122  and the P +  region  124  are also staggered along a direction parallel to the interface  110 , i.e., staggered along the y-direction depicted in  FIG. 1A . That is, as shown in the enlarged view in  FIG. 1B , an upper edge  1226  of the N +  region  122  does not align with an upper edge  1246  of the P +  region  124 . Similarly, a lower edge  1228  of the N +  region  122  does not align with a lower edge  1248  of the P +  region  124 . As also shown in  FIG. 1A , the P +  region  142  and the N +  region  144  in the P-well  104  are also staggered along the x-direction and the y-direction. 
         [0028]    In some embodiments, the N +  region  122  and the P +  region  124  do not overlap in either the x-direction or the y-direction. Similarly, the P region  142  and the N +  region  144  do not overlap in either the x-direction or the y-direction. As used in the present disclosure, two regions “overlapping” does not mean that one region is physically formed over the other region. Instead, for example, two regions “overlapping in the x-direction” means that at least one of the left edge or the right edge of one region is positioned along the x-direction between the left edge and the right edge of the other region. Thus, two regions “not overlapping in the x-direction” means that neither the left edge nor the right edge of any of the two regions is positioned along the x-direction between the left edge and the right edge of the other region. As shown in  FIG. 1B , for example, the right edge  1244  of the P +  region  124  is positioned along the x-direction to the left of the left edge  1222  of the N +  region  122 . With regard to positioning along the y-direction, in the present embodiment, the upper edge  1246  of the P +  region  124  is positioned along the y-direction to align with the lower edge  1228  of the N +  region  122 . 
         [0029]    The relative arrangement of the N +  region  122  and the P +  region  124  does not need to be the same as shown in  FIGS. 1A and 1B . For example, in some embodiments, the position of the right edge  1244  of the P +  region  124  along the x-direction may align with the left edge  1222  of the N +  region  122 . As another example, in some embodiments, the position of the upper edge  1246  of the P +  region  124  along the y-direction may be higher or lower than the lower edge  1228  of the N +  region  122 . As a further example, while holding L 24  unchanged and all other dimensions the same, if the position of the upper edge  1246  of the P +  region  124  along the y-direction is higher than the lower edge  1228  of the N +  region  122  (and thus the lower edge  1248  of the P +  region  124  is also positioned higher than that shown in  FIGS. 1A and 1B ), the SCR effect of the SCR structure is suppressed and the diode effect of the SCR structure is enhanced. That is, the ESD level of the SCR structure, i.e., the highest voltage at which the SCR structure can still safely discharge electrostatic, becomes lower than that in the situation shown in  FIGS. 1A and 1B , and the holding voltage of the SCR structure becomes higher. On the other hand, while holding L 24  unchanged and all other dimensions the same, if the position of the upper edge  1246  of the P +  region  124  along the y-direction is lower than the lower edge  1228  of the N +  region  122  (and thus the lower edge  1248  of the region  124  is also positioned lower than that shown in  FIGS. 1A and 1B ), the SCR effect of the SCR structure is enhanced, and both the trigger voltage and the holding voltage of the SCR structure become lower than those in the situation shown in  FIGS. 1A and 1B . 
         [0030]    Similar relative positioning also applies to the P +  region  142  and the N +  region  144  in the P-well  104 . However, the positions of the heavily doped regions  142  and  144  in the P-well  104  do not need to he mirror reflections of the positions of the heavily doped regions  122  and  124  in the N-well  102 . That is, D 22  and D 42  may be different from each other, and D 24  and D 44  may be different from each other. 
         [0031]    As shown in FIG IA, the N +  region  122 , the P +  region  124 , the P +  region  142 , and the N +  region  144  have an elongated shape extending in the y-direction. However, in accordance with other embodiments of the present disclosure, the heavily-doped regions  122 ,  124 ,  142 , and  144  may have other shapes, such as a square shape, or an elongated shape extending in the x-direction. 
         [0032]    In the present disclosure, the dimension of a region in the x-direction is referred to as the width of that region, and the dimension of a region in the y-direction is referred to as the length of that region. In some embodiments, each of the width W 22  of the N +  region  122 , the width W 24  of the P +  region  124 , the width W 42  of the P +  region  142 , and the width W 44  of the N +  region  144  may be about 0.1 μm to about 10 μm. These widths may be the same as or different from each other. Each of the length L 22  of the N +  region  122 , the length L 24  of the P +  region  124 , the length L 42  of the P +  region  142 , and the length L 44  of the N +  region  144  may be about 10 μm to about 100 μm. These lengths may be the same as or different from each other. 
         [0033]    As shown in  FIG. 1A , the N +  region  122  is positioned at a distance D 22  from the interface  110 , the P +  region  124  is positioned at a distance D 24  from the interface  110 , the P +  region  142  is positioned at a distance D 42  from the interface  110 , and the N +  region  144  is positioned at a distance D 44  from the interface  110 . In some embodiments, distances D 22 , D 24 , D 42 , and D 44  may be about 4 μm to about 10 μm, about 4 μm to about 80 μm, about 4 μm to about 10 μm, and about 4 μm to about 80 μm, respectively. 
         [0034]      FIG. 3  shows an equivalent circuit of the SCR structure  100  consistent with embodiments of the present disclosure. As shown in  FIG. 3 , the equivalent circuit of the SCR structure  100  includes an NPN transistor  302 , a PNP transistor  304 , an N-well resistor  306 , and a P-well resistor  308 . The base of the NPN transistor  302  is connected with the collector of the PNP transistor  304 . The base of the PNP transistor  304  is connected with the collector of the NPN transistor  302 . 
         [0035]    Referring also to  FIG. 1A , the N-well  102  functions as the collector of the NPN transistor  302 , the P-well  104  functions as the base of the NPN transistor  302 , and the N +  region  144  in the P-well  104  functions as the emitter of the NPN transistor  302 . The N +  region  122  in the N-well  102  functions as an ohmic contact layer for the collector of the NPN transistor  302 . Similarly, the P-well  104 , N-well  102 , and P +  region  124  in the N-well  102  function as the collector, base, and emitter of the PNP transistor  304 , respectively. In addition, the P +  region  124  in the P-well  104  functions as an ohmic contact layer for the collector of the PNP transistor  304 . 
         [0036]    The characteristics of the SCR structure  100  mainly depend on the characteristics of the NPN transistor  302  and the PNP transistor  304 . Consistent with embodiments of the present disclosure, adjusting the length L 44  and the distance D 44  may affect the characteristics of the NPN transistor  302 , and adjusting the length L 24  and the distance D 24  may affect the characteristics of the PNP transistor  304 . By varying the characteristics of the NPN transistor  302  and the PNP transistor  304 , the characteristics of the SCR structure  100  can be varied. For example, increasing the distance D 44  may increase the holding voltage of the SCR structure  100 . Changing the length L 44  may affect the turn-on voltage of the NPN transistor  302 , so as to affect the trigger voltage of the SCR structure  100 . The whole length of the SCR structure  100  in the y-direction, i.e., the distance in the y-direction from the upper edge  1226  of the N +  region  122  to the lower edge  1248  of the P +  region  124 , may also affect the characteristics of the SCR structure  100 . As the whole length of the SCR structure  100  increases, the total current conducting area of the SCR structure  100  increases. Therefore, the ESD current can spread in a larger area. Accordingly, the SCR structure  100  can sustain higher current and higher voltage. As a result, the ESD level of the SCR structure  100  increases. 
         [0037]    By adopting a layout consistent with embodiments of the present disclosure, the characteristics of the NPN transistor  302  and the PNP transistor  304  can be adjusted individually, and appropriate trigger voltage and holding voltage of the SCR structure  100  can be set at the same time. Therefore, the ESD performance of the SCR structure  100  can be set without increasing the footprint. 
         [0038]      FIG. 1A  shows an exemplary layout consistent with embodiments of the present disclosure. Other layouts may also provide similar benefits as the layout in  FIG. 1A  does. In some embodiments, any one or more of the heavily-doped regions  122 ,  124 ,  142 , and  144  may be provided as two or more separate segments. For example, in an SCR structure  400  shown in  FIG. 4 , the N +  region in the N-well  102  has two segments  122 - 1  and  122 - 2 , and the P +  region in the P-well  104  has two segments  142 - 1  and  142 - 2 . The total length of the two segments  122 - 1  and  122 - 2  may be larger than the length L 22  in  FIG. 1 . Similarly, the total length of the two segments  142 - 1  and  142 - 2  may be larger than the length L 42  in  FIG. 1 . 
         [0039]    As shown in  FIG. 4 , each of the two segments  122 - 1  and  122 - 2  in the N-well  102  is staggered along both the x-direction and the y-direction with respect to the P +  region  124 . In some embodiments, each of the two segments  122 - 1  and  122 - 2  in the N-well  102  does not overlap with the P +  region  124  in either the x-direction or the y-direction. In some embodiments, the lower edge of segment  122 - 1  may be positioned along the y-direction to align with the upper edge of the P +  region  124 ; and the upper edge of segment  122 - 2  may be positioned along the y-direction to align with the lower edge of the P +  region  124 . The relative arrangement of the N +  region segments  122 - 1  and  122 - 2 , and the P +  region  124  does not need to be exactly the same as shown in  FIG. 4 . For example, in some embodiments, the position of the right edge of the P +  region  124  along the x-direction may align with the left edges of the N +  region segments  122 - 1  and  122 - 2 . As another example, in some embodiments, the position of the upper edge of the P +  region  124  along the y-direction may be higher or lower than the lower edge of the N +  region segment  122 - 1 , and the position of the lower edge of the P +  region  124  along the y-direction may be higher or lower than the upper edge of the N +  region segment  122 - 2 . Similar relative positioning also applies to the N +  region  144  and the two segments  142 - 1  and  142 - 2  in the P-well  104 . However, similar to the situation with respect to  FIG. 1A , the positions of the P +  region segments  142 - 1 . and  142 - 2  and the N +  region  144  in the P-well  104  do not need to be mirror reflections of the positions of the N +  region segments  122 - 1  and  122 - 2  and the P +  region  124  in the N-well  102 . 
         [0040]    As another example, in an SCR structure  500  shown in  FIG. 5 , all of the heavily-doped regions in both the N-well  102  and the P-well  104  have multiple segments. The total length of the segments of one heavily-doped region in the SCR structure  500  may be larger than the length of the corresponding heavily-doped region in the SCR structure  100 . Therefore, the SCR structure  500  may be considered as an integration of multiple SCR structures  100 , and thus may have an even higher ESD level. 
         [0041]    Consistent with embodiments of the present disclosure, a conventional layout may be adopted for the heavily-doped regions in one of the two wells, so as to simplify the entire layout design, while at the same time achieving the benefits taught in the present disclosure. For example, in an SCR structure  600  shown in  FIG. 6 , a conventional layout is adopted for the heavily-doped regions in the N-well  102 , i.e., an N +  region  622  and a P +  region  624  in the N-well  102  are formed parallel to each other and completely overlap along the y-direction (that is, the upper and lower edges of the N +  region  622  align with the upper and lower edges of the P +  region  624 , respectively). However, the P +  and N +  regions in the P-well  104  are arranged consistent with embodiments of the present disclosure. 
         [0042]    Similarly, in an SCR structure  700  shown in  FIG. 7 , a traditional layout is adopted for the heavily-doped regions in the P-well  104 , i.e., a P +  region  742  and an N +  region  744  are formed parallel to each other and completely overlap in the y-direction. However, the P +  and N +  regions in the N-well  102  are arranged consistent with embodiments of the present disclosure. 
         [0043]    Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.