Abstract:
A pulse regulation loop for a clocked switching power converter where the loop is around a bridge converter. The loop features a comparator, a charge pump and a filter in series, feeding a pulse modulator controlling the clock duty cycle of the bridge. Ripple in the bridge converter output is feed to the comparator which causes the charge pump to inject or remove charge from the filter at the clock rate providing control over the modulator that establishes converter efficiency. The charge pump is of the PLL type, having switches responsive to voltage output from the comparator, evaluating the converter ripple relative to a reference voltage.

Description:
FIELD OF INVENTION  
         [0001]    This invention relates generally to voltage regulation of switching power converters.  
         BACKGROUND OF INVENTION  
         [0002]    Switching power converters (SPCs) are widely used in electronic systems to convert a direct current (DC) voltage into a different DC voltage, or an alternating current (AC) voltage into a DC voltage, or a DC voltage into an AC voltage. SPCs are widely used in both portable and non-portable applications for a wide range of power and voltage ranges. There are numerous architectures for each application such as buck (step down), boost (step up), H-bridge, and fly back. Yet, regardless of the type of converter, they all need a controller so that a regulated and well maintained voltage at the output is created. The generated output voltage is often used as a power supply to an specific load within the electronic system. There could be different types of SPCs in one system, each with its own particular load and controller and its particular set of specifications.  
           [0003]    [0003]FIG. 1 shows block diagram of a typical prior art step-down (or buck) DC/DC switching power converter (SPC) that converts a DC voltage with value of V in  from a power source  11 , such as an AC to DC full wave bridge rectifier, into a lowered DC voltage with value of V out  (where V out &lt;V in ). For example, 12V DC input to power source  11  may be converted to 10V. DC output as V in . A prior art power converter might convert V in  to a DC output voltage, V out , of 2 volts DC. The core of a buck SPC is made of two transistor switches; M 1  and M 2 , along with inductor  18 A, having a value L 0 , and capacitor  18 B, having a value C 0 . Transistor M 1  can be either a p-channel or a n-channel device, while M 2  is customarily a n-channel device. The type selection for M 1 , between n-channel or p-channel, is heavily dependent on design requirements and availability of devices within the system.  
           [0004]    [0004]FIG. 2 shows a timing diagram of voltages at nodes  19 B,  19 C (V out ),  20 A and  20 B during a steady state condition of the SPC of FIG. 1. By opening and closing transistor switches M 1  and M 2  in a complementary fashion, at a rate set by a clock oscillator associated with drivers  12  in FIG. 1, where only one device is on at any given moment, the voltage at node  19 B would be a pulse with the same frequency of the signal at node  20 A or  20 B. Yet, the magnitude of the voltage at node  19 B would alter from zero to V in . This pulse voltage would be filtered by inductor  18 A and capacitor  18 B at node  19 C to an approximate value of  
             V   out   =V   in ( T   on   /T )  (1)  
           [0005]    where T on  is the duration for which M 1  is kept conducting (in this case while signal at node  20 A is at zero), and T is the total period of signal at node  20 A (or period of signal at node  20 B). Referring to FIG. 2, the ratio of Ton/T is called “duty cycle” of the clock. So, for a 20 percent “duty cycle”, output voltage V out  would be V out =0.2V in  assuming no losses.  
           [0006]    Returning to FIG. 1, a regulation loop for a prior art SPC is often made of an error amplifier (EA)  23 , having an input load Z 1 , represented by block  14 A, and a feedback load Z 2 , represented by block  14 B, a pulse width modulator (PWM) or a pulse frequency modulator (PFM) controller  15 , and a driver  12  to turn M 1  and M 2  on and off. The error amplifier may be an analog or digital device which evaluates a sample of power ripple on one input to the error amplifier versus a reference voltage on node  22 C from a reference supply  16 . This regulation configuration is frequently seen in buck, boost, and fly-back switching power converter designed of the prior art. An entire SPC system can be built on a printed circuit board using discrete components or it can be built as an integrated circuit using CMOS, BiCMOS, BCD, or any other process technology suitable for such a design.  
           [0007]    Referring again to FIG. 2, if value of T is held constant for a constant clock period, or frequency, and T on  (or T off ) is varied to control voltage at node  19 C (V out ), then the controller is called a PWM or pulse width modulator controller. Yet, if T is varied and T on  (or T off ) is held constant, then the controller is a PFM or pulse frequency modulator controller. In either case, PWM or PFM, transistor switches M 1  and M 2  are operated in a manner that creates a voltage pulse at node  19 B. Inductor  18 A, having a value L 0 , and capacitor  18 B, having a value C 0 , are connected in a manner to form a low-pass filter so that pulse signal at node  19 B is converted into a fairly constant DC voltage at  19 C defined by Equation 1 and depicted in FIG. 2. Voltage at node  19 C is used to power up any possible load, such as load  13 .  
           [0008]    Using small-signal analysis, the low-pass filter created by inductor  18 A and capacitor  18 B produces two poles at f P1  and f P2  that can be calculated from  
               f   P1     =       f   P2     =     1     2                 π            L   0          C   0                       (   2   )                               
 
           [0009]    Now, since there are two poles within the regulation loop, this system would be unstable in a closed loop configuration if there is no change made to the loop. So, the loop must be compensated.  
           [0010]    Referring again to FIG. 1, error amplifier  23  along with two loads  14 A and  14 B, with values Z1 and Z2, respectively, serve as the main compensation circuitry to add stability to the loop. This is a very commonly practiced scheme to compensate a SPC regulator loop. Using small-signal analysis, in the frequency domain, the voltage gain of error amplifier  23  considering its loads can be calculated as  
               A   1     =       -   Z2     Z1             (   3   )                               
 
           [0011]    By using a proper combination of active and passive components, primarily capacitors and resistors for loads Z 1  and Z 2 , proper additional poles and zeros can be added within the regulation loop in order to stabilize it.  
           [0012]    [0012]FIG. 3 shows one possible method of implementing a complex value for Z 2  with a capacitor  101 , having a value C 11 , in series with a resistor  103 , having a value R 11 , both the capacitor  101  and resistor  103  in parallel with capacitor  105 , having a value of C 12 . So. assuming a simple resistor is used for Z 1  with value of R Z1 , and assuming Z 2  is set to be a combination of one resistor and capacitors shown in FIG. 4, then A 1  (in Equation 3) is  
               A   1     =     -       1   +     sRC   11           R   Z1          s        [         sRC   11          C   12       +     (       C   12     +     C   11       )       ]                     (   4   )                               
 
           [0013]    with one zero at 1/( 2 πRC 11 ), and two poles. However, it must be noted that the DC voltage gain of error amplifier  23  is simply equal to its open loop voltage gain, and is not calculated from Equation 4. Furthermore, capacitor  18 B, in FIG. 1, having value C 0 , has series parasitic resistances, not shown in FIG. 1, with a value of R ser  which would add another zero at 1/( 2 πC 0 R ser ). There are effectively two poles created by L 0  and C 0  (at f P1  and f P2 ) and two additional poles created by Z 1  and Z 2  which yield a number of poles totaling four, with two zeros within the loop. Hence, by adjusting the values of passive components L 0 , C 0 , (both associated with the bridge converter), C 11 , C 12 , R 11 , (the latter three values seen to be associated with the components of FIG. 3), and R Z1 , (the resistance value of the impedance Z 1  in block  14 A of FIG. 1) a regulation loop can be compensated to ensure a stable operation for all conditions.  
           [0014]    The same analysis can be used for any other converter such a fly back, or H-bridge which uses this common type of regulation. One of the main problems in a regulation loop is the error amplifier itself. The error amplifier must have a high voltage gain, and adequate bandwidth in order to be effective. If the voltage gain or speed of the error amplifier is compromised for any reason, then additional error terms are introduced, which in turn may not produce a stable controller. So, performance of the error amplifier is a very crucial and important issue that must be considered for any regulator.  
           [0015]    A power supply for an amplifier plays a very crucial role in its gain and bandwidth. A reduced power supply voltage often lowers either the gain or speed, or both gain and speed. Traditionally, error amplifiers in a regulation loop need a minimum power supply voltage of around 2V to operate properly. Furthermore, in a typical buck SPC the entire regulation loop may be powered by the provided power source, which has a value of V in . Thus, the minimum voltage for power source or (V in ) is often limited to around 2V for a conventional buck SPC. So, if value of V in  drops below this critical limit of around 2V then error amplifier that is used in the buck SPC regulation loop could have a reduced voltage gain or bandwidth, which could hinder the performance of the entire converter, or may prevent operation of the converter.  
           [0016]    In a boost converter, where V in  is increased to a larger value at the output and V out &gt;V in , if V in  is less than a critical voltage which is need to run all of the internal circuitry, such as error amplifier or reference circuitry, then the output voltage V out  may not be regulated until its value reaches an specific value high enough that can be used as the power source to the regulator itself. Then, the loop is activated to regulate value of V out  at its targeted value.  
           [0017]    Thus, general use of an architecture similar to that shown in FIG. 1 in buck SPCs is limited mainly to system where V in  is, at a minimum, around 2V. Nevertheless, there are applications where a buck SPC is needed to convert a lower voltage power source, such as household batteries that are used as a main power source. In this case V in  could be as low as 1.3V. A desired output voltage (V out ) could be anything from 1.2V to as low as 0.4V.  
           [0018]    In such systems, one available scheme could be simply to use a linear voltage regulator. However, efficiency linear voltage regulators is approximated by  
           η= V   Out   /V   in   (5)  
           [0019]    where V in  and V out  are their respective input an output voltages. Thus, linear regulator are considered very inefficient for large voltage drops and may not be suitable for a system where V in =1.3V and V out =0.65V, since η=50%. An SPC efficiency should be as high as 95% for similar voltage drop ratios. Another available method could be to employ a boost SPC to increase the provided power source by stepping up a value of V in  as previously mentioned to voltage of around 2V, or higher, and then use a buck SPC to regulate the created 2V level back to a voltage lower than the initial V in . Such an approach would need two sets of SPCs which increases the cost and would reduce the entire efficiency of power converter circuitry. This may not be acceptable, yet it could be the only effective “efficient” solution.  
           [0020]    Other approaches to regulate a SPC involve using a digital architecture. In some digital schemes a PLL has been used to monitor and adjust a power supply for a digital system. The goal was to “dynamically” adjust V out  in order to optimize the power consumption of the load which were a large digital circuits. Hence, these approaches are not used to keep V out  at a constant value, but to change it according to the need of an specific digital load in order to minimize the amount of power consumed within such load, such as a micro-controller or microprocessor circuits. An analog-to-digital converter (ADC) has been used to sample the output voltage of a circuit and voltage regulation was done through digital circuitries. However, the input voltage was still kept to a value around 3V to keep an analog-to-digital converter operational. The cost of the die was fairly large.  
           [0021]    An object of the invention is to create a new control loop to regulate the output voltage of a switching power converters (SPC), even at low input power supply voltage, particularly lower than 2V, to reduce design complexity, and to lower power consumption and facilitate design portability of the regulator between different manufacturing methods and processes (i.e. CMOS, BiCMOS and such).  
         SUMMARY OF THE INVENTION  
         [0022]    The above object has been satisfied with a control loop for a SPC that uses a bridge rectifier to provide rectified DC to a filter loop having a simple voltage comparator instead of a traditional operational amplifier, along with a simple filter to linearize nonlinear response of the comparator. The filter has poles and zeros offsetting the poles and zeros of the bridge rectifier to promote stability in the loop. The new circuit can tolerate process, temperature and voltage variations, and is capable of operating with reduced power supply voltage with no degradation in performance. The circuit can easily be ported into different technologies without major design modifications. The circuit can be applied to any SPC circuit including DC-DC, DC-AC and AC-DC converters. By using this new regulation circuit the power supply voltage applied into the SPC can easily be lowered without harming regulated V out . 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0023]    [0023]FIG. 1 is a circuit diagram of a buck type of switching power converter of the prior art.  
         [0024]    [0024]FIG. 2 is a timing diagram of voltage versus time at various nodes in the circuit of FIG. 1.  
         [0025]    [0025]FIG. 3 is a circuit diagram of a complex impedance load for an error amplifier of the prior art.  
         [0026]    [0026]FIG. 4 is a circuit diagram of a boost type of switching power converter with a stabilization loop of the present invention.  
         [0027]    [0027]FIG. 5 is a circuit diagram of an alternate switching power converter with a stabilization loop of the present invention, including a charge pump.  
         [0028]    [0028]FIG. 6 is a circuit diagram of a typical filter in the stabilization loop of FIGS. 4, 5, or  7 .  
         [0029]    [0029]FIG. 7 is a circuit diagram of a switching power converter with another embodiment of a stabilization loop of the present invention.  
         [0030]    [0030]FIG. 8 is a circuit diagram of a charge-pump used in the circuit of FIG. 7.  
         [0031]    [0031]FIG. 9 is a circuit diagram of principal regulation components shown in the stabilization loop illustrated in FIG. 7.  
         [0032]    [0032]FIG. 10 is an expanded circuit diagram of showing a voltage comparator illustrated as a block in FIG. 9.  
         [0033]    [0033]FIG. 11 is a further expanded circuit diagram showing the voltage comparator illustrated in FIG. 10. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0034]    With reference to FIG. 4, the present invention came about with the realization that the function of the linear error amplifier  23  in FIG. 1 and the compensation loads Z 1  and Z 2  can be replaced with a simple high gain detection circuit with a non-linear response, and a proper filter to create a pseudo linear behavior to regulate the loop. At very low frequencies near DC, the error amplifier behaves like a simple voltage comparator with a very large voltage gain. Yet, it is only at higher frequencies that it can assist in compensating the loop. So, the same behavior can be implemented with components that may not suffer from shortcomings of typical error amplifiers. A non-linear detection circuit such as a voltage comparator is typically more robust to variations in headroom voltage, temperature, and process variations. Hence, its adaptability to these changes can be used to make the entire compensation loop more robust.  
         [0035]    A high gain voltage comparator  44  is used to detect an error involving output voltage (V out ) at node  45  or a fraction of it, at node  47  after a portion of the output voltage at node  45  is dropped across resistor  49 . This first voltage is a first input to comparator  44 . A second input is a reference voltage on line  51 . Assuming that the voltage comparator has a sensitivity of ε (where ε≅0) and has very small propagation delay, then if the first voltage is greater than the second, then the comparator output, V2, is at logic level 0, and when the first voltage is less than the second, the comparator output, V2, is at V in , logic level 1. So, V2 can be viewed as a pulse voltage modulating from a positive voltage to zero or a negative voltage (if the comparator is powered by two separate power supplies, one positive and one negative). This pulse can be a few volts in magnitude. If the comparator is solely powered with a single power source such as V in , then the pulse would merely vary from zero to V in . By placing a simple low-pass filter in the path of the comparator, not shown, the pulse voltage at the comparator output node  65 , V 2 , can be averaged out to create a fairly constant voltage which can be fed into the PWM or PFM controller  63  to eventually regulate the loop. Conceptually, the comparator  44  and filter  61  would effectively replace the error amplifier  23  and its loads Z 1  and Z 2  in FIG. 1. The primary goal is to create a constant voltage at the input of PWM or PFM controller  63  so the loop is stabilized. However, the same issues related to the poles and zeros in the regulation loop still exist and must be dealt with. The filter block inside FIG. 4 can be built to have the following response:  
               H     (   s   )       =       1   +     s   /     ω   z1             (     1   +     s   /     ω   p1         )          (     1   +     s   /     ω   p2         )                 (   6   )                               
 
         [0036]    where H(s) is the output transform of the filter, s is a complex variable and w is a frequency term (ω z1  being a frequency term associated with a pole and ω p1  and ω p2  being frequency terms associated with pole one and pole two respectively, such that the inverse Laplace transform L −1 [H (S) ] yields expressions that characterize behavior of filter components in the time domain, such as a circuit arrangement of capacitors, inductors and resistors. Equation 6 is similar to Equation 4 and it is the simplest form of such filter, with one zero and two poles. One such filter network could be similar to the circuit shown in FIG. 3, with one end of it connected to ground, as shown in FIG. 6. One main issue of implementing the filter is the magnitude of V 2 , the voltage of comparator output node  65 . Since magnitude of V 2  is modulated from zero to V in  or −5 volts to +5 volts, the voltage at input node  52 A can cause a challenge in design, despite that fact it can be viewed as a constant for a short period of time. However, if a battery is used as power source for the power converter, its output voltage will normally change as charge is depleted. So, even though implementing a filter with a variable V in  is possible, it still can be difficult task from practical point of view.  
         [0037]    A simpler approach would be to insert a simple charge-pump circuit  45  in FIG. 5 that can add (or remove) a constant amount of charge into or out of a node, depending of magnitude of V 2 , the voltage on node  65  at the output of comparator  44 . Then, in accordance with the invention, a stabilized regulation loop includes a comparator, a charge-pump and a filter to deal with that constant yet modulating charge instead of dealing with a pulse-like voltage, V 2 . A charge-pump is commonly used in the design of traditional phase locked loops (PLLs) where the phase or frequency of a reference clock is compared to the phase or frequency of the generated clock signal out of a voltage controlled oscillator (VCO) and accordingly, charge is added or subtracted from a node by the charge-pump. Note that this type of “charge pump” is different from another type of charge pumps used to increase voltage from a low value to a high value using a series of phased switches controlling charge transfer from connected capacitors. The present invention employs charge adding and subtracting charge pumps, not the other type of charge pump. So, this particular approach with some simple modifications can easily be applied here in SPC regulation design.  
         [0038]    Referring to FIG. 7, power source  41  may be a full wave bridge converting an AC voltage to some DC level. This DC level is being regulated by a buck SPC which is made of two transistors switches M 1  and M 2 . M 1  is shown as a p-channel device and M 2  is shown as a n-channel device for this example, yet both can be n-channel devices if needed with some possible extra circuitry to drive M 2 .  
         [0039]    Transistors M 1  and M 2  are connected to inductor  55 A, having a value L 0 , and capacitor  55 B, having a value C 0 . Input voltage at node  52 A with value of V in  is reduced to a lower voltage at node  52 C with value of V out  and can be connected to a possible load, in this case load  43 . Value of V out  is regulated by a loop that is made of components that can either be built on a printed circuit board or in an integrated form in CMOS, BiCMOS, or bipolar processes (or any other technology suitable for such a design such as silicon carbide, silicon-on-insulator, silicon germanium, and bipolar-CMOS-DMOS).  
         [0040]    A network is used to provide a voltage which is directly proportional V out , in this case with two series connected resistors  54 A and  54 B, having respective values R1 and R2. The voltage at node  52 D and the reference voltage provided by reference voltage supply  48  at node  22 B from reference supply  48  are compared to each other by voltage comparator  44 . Voltage comparator  44  compares these two voltages at nodes  52 D and  22 B and provides a signal at its output at node  52 E. If voltage at node  52 D (V 52D ) is larger than voltage at node  22 B (V 22B ) then voltage at node  52 E (V 52E ) is set to a logic zero. However, if V 52D  is less than V 22B , then V 52E  is set to a logic 1. The comparator is connected to a charge-pump which can provide or remove charge to or from node  52 F.  
         [0041]    Now, at simple circuit diagram shown in FIG. 8 illustrates a charge-pump used herein. If the comparator  44  output voltage at node  52 E is at 0, then current I up  generated by charge-pump  45  flows into node  52 F. Assuming capacitor  91  in the filter of FIG. 6, having value C 12 , is much larger than capacitor  93 , having value C 11 , then the voltage variation at the output node  52 F of charge-pump  45  for V 52E =0 would be  
         Δ V   52F =( I   up   T   up )/C 12   (7)  
         [0042]    where I up  if value of current source in charge-pump  45  and Tup is the duration for which I up  if flowing into node  52 F. And if the output of comparator  44  is high, i.e. V 52E =1, then capacitor C 12  would be discharged by an amount calculated by  
         Δ V   52F =( I   dn   T   dn )/ C   12   (8)  
         [0043]    similarly, I dn  and T dn  are values of current sink and the duration for charge-pump  45  in which I dn  is flowing out of C 12 , respectively. It must be noted that in the frequency domain, a single capacitor would add another pole to the regulation loop which would cause an additional reason for the entire system to be unstable and is not recommended for this system. Filter  46  must be able to smooth the voltage at node  52 F, and in frequency domain provide a zero to compensate the loop and prevent oscillation.  
         [0044]    By using a frequency domain analysis, a zero is added at  
               f   Z1     =     1     2                 π                   RC   12                 (   9   )                               
 
         [0045]    where f Z1  is the frequency of the zero and a single pole is added at  
               f   P3     =         C   11     +     C   12         2                 π                   RC   11          C   12                 (   10   )                               
 
         [0046]    where f P3  is the frequency of the added pole. Thus, by selecting proper values for R, C 11 , and C 12  values of the created pole and zero can be placed such that an stable system is obtained. Furthermore, parasitic resistance of the output capacitor  55 B, having value C 0 , would add an extra zero within the network that would be used in stabilizing the system, along with the values of C 11 , C 12 , and R).  
         [0047]    Values of I dn  and I up  would contribute to the overall gain of system in frequency domain or in time domain. By increasing their values, overall gain is increased and the locations of poles and zeros must be modified in response to those changes. Consequently, all of these parameters become design criteria and must be dealt with for any system.  
         [0048]    Clearly a voltage comparator is inherently a non-linear circuit, unlike an error amplifier. However, it must be noted that an error amplifier that operates as an open loop can be used in a voltage comparator mode within this system, without any noticeable problem. So, voltage comparator  44  can be of any manner and design, as long as it can perform the voltage detection needed in this system, as described above.  
         [0049]    Filter  61  is used to smooth the voltage created at node  52 F, the charge-pump output, and apply it to a controller block. Voltage at node  52 F out of filter  61  is applied to PWM or PFM controller  63  which provides the needed signals through data line  53  to driver  42 . The controller controls the duty cycle for transistor switches M 1  and M 2  established by driver  42 .  
         [0050]    [0050]FIG. 8 shows a simplified operational diagram of a well known charge pump used in FIG. 7 having a characteristic design primarily used in phased lock loop (PLL) and delay locked loop (DLL) systems. Any circuit that can perform the function of injecting and retracting current or charge, through a constant current source, such as switch MP, and sink, such as switch MN, could be used as the charge-pump within the system  40 .  
         [0051]    In operation, charge-pump  45  has an input node  52 E having a voltage, VA, from the comparator  44  in FIG. 7. This voltage is either high or low, say 2 volts or zero volts. A high voltage signal causes transistor MP and MN to pull current, I up  from current source  81  associated with bias voltage supply V DD  at terminal  83 . The current I p  flows through transistor  81  and toward output terminal  52 F. Because comparator  44  is being driven by a signal with ripple from a half bridge or similar converter, the comparator output can rapidly fluctuate high and low. This causes short bursts of current I p  to be delivered to node  52 F. When the comparator output is low, the transistors sink current I Dn  into current sink  85  toward ground terminal  86 . The current I Dn  is pulled from node  52 F.  
         [0052]    Variations on the charge-pump construction are many. Filter  46  in FIG. 7 is of the type commonly used in the design of PLL systems. FIG. 6 shows the simplest circuit that can be used for the filter, with a capacitor  91  in one branch in parallel with a second branch having resistor  92  in series with capacitor  93 . However, there are many variations on this filter and other filters can provide the needed poles and zeros and smooth out the voltage at node  52 F by providing an additional zero in the stabilization loop to stabilize the entire regulation loop.  
         [0053]    Controller  47  in FIG. 7 can be either a PFM or PWM modulator. Driver  42  in FIG. 7 amplifies pulses that can have either fixed frequency and variable width (PWM), or fixed pulse width and variable frequency (PFM) established by controller  47 . The controller  47  adjusts pulse width for a PWM or pulse frequency for a PFM. Reference voltage  48  sets a target voltage, adjusted for voltage drop R1 of resistor  54 , for V out  at node  52 C. The controller  47  is making adjustments to driver  42  to minimize the ripple in V out  at node  52 C and into load  43 . The invention would work with either a PWM or PFM, and for any SPC converter. The present invention provides a stabilized regulation loop for a SPC with a non-linear voltage comparator, a charge-pump of the type commonly used in PLL circuitry, and a low pass filter with the combination having poles and zeros offsetting the poles and zeros of the bridge rectifier. Blocks that are typically used in the regulation loop shown in system  40  such as voltage comparator  44 , charge-pump  45 , filter  46  and PWM or PFM controller  47  and driver  42  are common circuitry.  
         [0054]    In general, system  40  may be built on PC board from discrete components, or in an integrated circuit form in any technology suitable for such a system, such as but not limited to CMOS, BiCMOS, GaAs, Bipolar (or BJT), SiGe, Silicon on Insulator (SOI), or any other integrated circuit process capable of producing system  20  in an integrated form. Or, entire system  20  can be built as a combination of discrete components and integrated circuits built in different process technologies that are proper for such a system.  
         [0055]    With reference to FIG. 9, comparator  44  is to have a voltage signal input  52  from terminal  47  where terminal  47  is an output node of a bridge converter, such as a half-bridge, as seen in FIG. 5. Comparator  44  also has a reference voltage input on line  51  associated with a voltage reference source, such as battery  50 . Comparator  44  is made of a plurality of CMOS transistors of the type shown and described in U.S. Pat. No. 6,198,312. A more elaborate version of such as comparator is shown in FIG. 10 and a still more sophisticated version is shown in FIG. 11.  
         [0056]    The output of comparator  44  on line  60  feeds charge pump  45 , similar to the charge pump shown in FIG. 8. The charge pump features a pair of CMOS transistor switches  62  and  64 . Transistor  62  is a p-channel device connected to a p-channel current sourcing transistor  66  biased by a reference voltage on gate line  76  to provide a supply voltage  80  and current when the gate of switch  62  is biased negative. The provided current flows toward filter  61  and specifically into capacitors  91  and  93 . Transistor  64  is an n-channel device connected to an n-channel current sinking transistor  68  biased by a reference voltage on a gate line  78  to provide access to ground  86  for sinking current when the gate of switch  64  is biased positive by the output of comparator  44 . In this case, current is drawn from filter  61 . The filter  61  is shown to be the same as the filter of FIG. 6. This filter is a typical simple filter and equivalent filters, more or less sophisticated, analog or digital, may be used. So feedback from the pulse modulator appear at terminal  47  of comparator  44 , at the clock rate, causing small amounts of current to be injected into or removed from filter  61 . Since filter  61  has components selected to provide offsetting poles and zeros to counterparts in the power supply, a stable feedback loop is provided.