Abstract:
A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circuit scale and high in expandability and besides the time required for adjustment of components is reduced significantly to reduce the man-hours for arrangement significantly to reduce the man-hours for development significantly and the same basic parts are used so as to achieve augmentation of the yield and promote reduction of the production cost.

Description:
BACKGROUND OF THE INVENTION 
   1) Field of the Invention 
   This invention relates to a logic circuit suitable for use with a magnitude comparison circuit, a carrier production circuit, a full adder circuit and an increment circuit. 
   2) Description of the Related Art 
   A great number of magnitude comparison circuits, carry generation circuits, full adder circuits and increment circuits are used as basic circuits in a processor. The processor requires a large number of basic circuits in order to perform addition and subtraction with operation commands. For example, a magnitude comparison circuit is used for floating point arithmetic. In particular, when floating point arithmetic is performed, positioning of two parts including a characteristic and a mantissa of a numeral must be performed. Therefore, the magnitude comparison circuit is used when it is required to compare two parts of a numeral to discriminate which one of the two parts is a characteristic or a mantissa in order to perform the positioning. An adder circuit is used, in order to perform address calculation to effect load/store, to add two or three kinds of operands to determine an address to load data from a memory. A carry generation circuit is used to make it possible to perform high speed arithmetic where the bit length on an adder circuit is great. Further, an increment circuit is used principally for a command register and has an increment of several lower figures which varies at random. In this point, the increment circuit is different from an ordinary counter circuit. In particular, an increment circuit having a great bit length of 64 bits is used. Therefore, an ordinary counter such as a register is not used for the increment circuit. Further, while the counter circuit increments one by one, the increment circuit has an increment which exhibits a variation among 2, 4, 8, 16 and so forth. 
   Since the working speeds of such basic circuits as described above determine the processing speed of the processor, they must be constructed as circuits which operate at high speeds. However, since generally the bit widths of the circuits are different depending upon places where they are used, many kinds of magnitude comparison circuits, carrier production circuits, adder circuits and increment circuits must be developed. As the technology progresses year by year, it is demanded to efficiently develop those kinds of circuits which have different bit widths and operate at high speeds. Therefore, minimized numbers of leaf cells are required to be used to construct circuits which operate at high speeds. 
   The leaf cell (also called functional cell) is a cell of a hierarchy in which layout thereof must be performed on the transistor level and is a cell of the lowest layer of a module which exhibits a function. For example, a module in a hierarchy below a circuit which has a 64-bit addition function is a 16-bit adder circuit, and a module of a hierarchy below the circuit having the 16-bit addition function is a 4-bit adder circuit. And, where there is no module in a hierarchy below the circuit having the 4-bit addition function, the 4-bit adder circuit is formed from a leaf cell of the lowest hierarchy. 
   Now, an example of an adder circuit is described with reference to  FIGS. 26 to 29  and an example of an increment circuit is described with reference to  FIG. 30 . 
   First, since a look-ahead carry full adder circuit is used for an adder circuit, the adder circuit requires a great number of parts. The look-ahead carry full adder circuit signifies a circuit which performs arithmetic using a carry generation function G and a carry propagation function P for a unit of a block which is formed from 4 groups each formed from 4 bits. The reason why the look-ahead carry full adder circuit just described is used is that a carry propagation adder circuit cannot perform high speed processing. In particular, the carry propagation adder circuit performs addition simply and propagates a carry signal successively from the lowest order figure to the highest order figure and requires excessive time for the addition. In contrast, the look-ahead carry full adder circuit is used so that processing of the carry can be performed at a high speed. This is described more specifically with reference to  FIGS. 26 to 29 . 
     FIG. 26  is a block diagram showing an example of a functional block of an 8-bit look-ahead carry full adder circuit. Referring to  FIG. 26 , the 8-bit look-ahead carry full adder circuit  90  shown includes a carry generation/propagation unit  91 , an 8-bit CLA (look-ahead carry) unit  92  and a sum unit  93 . 
   An 8-bit signal A [A 7  A 6  A 5  A 4  A 3  A 2  A 1  A 0 ] and another 8-bit signal B [B 7  B 6  B 5  B 4  B 3  B 2  B 1  B 0 ] are inputted to the carry generation/propagation unit  91 , and a carry for each bit number n is outputted in accordance with the following expression from the 8-bit CLA unit  92 :
 
 C   n+1   =C   n   ·P   n   +G   n  
 
where G n  is the carry signal, P n  is a carry propagation function, and C n  is a carry generation function. Results of the arithmetic of the 8-bit CLA unit  92  are supplied as a plurality of carries to the sum unit  93 , and results of addition from the carries are outputted from the sum unit  93 .
 
   The units  91  to  93  have such constructions as shown in  FIGS. 27 to 29 , respectively. In particular,  FIG. 27  is a block diagram showing a detailed construction of the carry generation/propagation unit  91 ;  FIG. 28  is a block diagram showing a general construction of a 4-bit CLA unit; and  FIG. 29  is a block diagram showing a general construction of the sum unit. As can be seen from  FIGS. 27 to 29 , each of the units includes a large number of logic gates. 
   Similarly,  FIG. 30  is a block diagram showing a construction of a 16-bit increment circuit which employs a multi-input AND gate. Referring to  FIG. 30 , a gate  94  logically exclusively ORs a result of half addition arithmetic at each of the 0th to nth figures (0≦n&lt;16) and a carry signal from the lower order figures and outputs a result of the logical exclusive ORing as a full addition arithmetic result. The “carry signal from the lower order figures” is, for example, a signal denoted by C&lt; 1 &gt; in  FIG. 30 , and the signal C&lt; 1 &gt; is determined as an AND value of all of the 15 bits A&lt; 1 &gt;, A&lt; 2 &gt;, A&lt; 3 &gt;, . . . , A&lt; 15 &gt; lower than the 0th figure (A&lt; 0 &gt;). Similarly, the gate  94  logically exclusively ORs a half addition arithmetic result at the first figure (A&lt; 1 &gt;) and a carry signal C&lt; 2 &gt; determined from an AND value of all of the 14 bits A&lt; 2 &gt;, A&lt; 3 &gt;, . . . , A&lt; 15 &gt;. Further, a carry signal C&lt; 13 &gt; at the 12th figure from the lower order figures is an AND value of the 3 bits A&lt; 13 &gt;, A&lt; 14 &gt;, A&lt; 15 &gt;; a carry signal C&lt; 14 &gt; at the 13th figure from the lower order figures is an AND value of the 2 bits A&lt; 14 &gt;, A&lt; 15 &gt;; and a carry signal C&lt; 15 &gt; at the 14th figure from the lower figures is a value of the 15th bit itself. Accordingly, a large number of AND gates are required to determine AND values at the individual figures. 
   However, since such an adder circuit or an increment circuit as described above requires many kinds of basic circuits and has a complicated structure, it has a subject to be solved in that the processing speed is low. For example, the 4-bit CLA unit shown in  FIG. 28  has a complicated structure and requires many kinds of leaf cells. In particular, as seen from a broken line block, the unit shown includes ten AND gates and four OR gates, and where a multi-input gate circuit employs a NOR gate or the like to invert an OR output, the speed is retarded because a delay of propagation by one clock is caused by the NOR gate or the like. The reason is that two PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) are connected in series. Further, as seen from  FIG. 30 , also the increment circuit includes many basic parts and has a complicated structure with a comparatively low degree of repetitiveness of wiring lines, and consequently, many man-hours are required for the layout (arrangement) of the gates and so forth. 
   Meanwhile, many proposals have been made in order to raise the speed of an entire circuit. Japanese Patent Laid-Open No. 187129/1994 (hereinafter referred to as document 1) discloses a technique wherein, in order to provide a semiconductor device wherein logic circuits such as full adders and so forth having a high speed and a small circuit scale are integrated, a logic production section composed of four NMOS transistors and a latch circuit composed of two PMOS transistors are combined to form a high speed logic circuit including a small number of elements as a basic circuit and such basic circuits are combined to form several function circuits such as a full adder. The document 1, however, does not disclose a technique for expanding the function circuits. 
   In order to achieve reduction of the number of elements used and augmentation of the operation speed, a technique regarding a pass transistor logic circuit is disclosed in Japanese Patent Laid-Open No. 162722/1997 (hereinafter referred to as document 2). The object of the document 2 is such as follows. In particular, it is an object of the document 2 to provide a pass transistor logic circuit which exhibits an improved H level and simultaneously allows operation with a low power supply voltage without using a pull-up circuit, reduces the load to an outputting circuit in the preceding stage to achieve augmentations of the operation speed, prevention of failure in transmission of a signal to a next stage and augmentation of the resistance to noise, suppresses the number of stages of transistors in a logical arithmetic system of a logic circuit composed only of pass transistors as far as possible to augment the operation speed while comparatively complicated logic can be implemented and particularly logic which cannot be implemented readily with a logic circuit which is formed only from pass transistors can also be augmented comparatively readily, and allows implementation of a logic circuit which includes a reduced number of necessary elements and operates with a comparatively high operation speed even in comparison with an alternative circuit formed from a CMOS (Complementary Metal Oxide Semiconductor) logic circuit. According to the technique of the document 2, however, a plurality of pass transistors whose outputs exhibit on or off in response to logical values of inputs thereto are connected in series or in parallel to form a circuit which performs logical AND arithmetic or logical OR arithmetic to obtain a desired logic circuit. Therefore, the technique of the document 2 still is complicated in construction and lacks in expandability. 
   Different techniques relating to a pass transistor are disclosed in U.S. Pat. No. 4,566,064 (hereinafter referred to as document 3), Japanese Patent Laid-Open No. 226/1984 (hereinafter referred to as document 4) and U.S. Pat. No. 4,622,648 (hereinafter referred to as document 5). The techniques disclosed in the documents 3 to 5 have an object to provide a novel logic circuit construction method. According to the techniques of the documents 3 to 5, a pass transistor is used to form a logic circuit, and the regularity of resultant logic circuits formed in this manner is increased to the maximum. Where logic circuits obtained using the techniques are used to form a combination circuit, the combination circuit is augmented significantly in terms of the configuration, power and operation speed when compared with ordinary logic circuits. However, the documents 3 to 5 do not disclose a functional circuit such as an adder circuit, a magnitude comparison circuit, an increment circuit or a like circuit. 
   Meanwhile, a technique for reducing the number of transistors which form an EXOR or EXNOR circuit is disclosed in Japanese Patent Laid-Open No. 201527/1984 (hereinafter referred to as document 6) and U.S. Pat. No. 4,621,338 (hereinafter referred to as document 7) which has claimed the priority based on an application based on which also the document 6 has claimed the priority. However, the documents 6 and 7 are directed toward providing an EXOR or EXNOR circuit which requires a smaller number of transistors than an ordinary device and providing a CMOS full adder stage in which such an EXOR or EXNOR circuit is used, and do not disclose a technique relating to high speed operation or expandability. 
   In addition, the documents mentioned above do not disclose any technique for saving time required for tuning (adjustment) of components. In particular, where a great number of components are involved, there is a subject to be solved in that much time is required for tuning of the components. Besides, if it is tried to form adder circuits of different bit lengths for an increment circuit which are formed from adder circuits of different bit lengths such as a 64-bit adder circuit and a 4-bit adder circuit, much variation is required for circuit arrangement. Therefore, in order to evaluate a circuit ready for new technology, many basic circuits such as leaf cells must be re-evaluated and connected. Thus, there is a subject to be solved in that the efficiency in development is low. 
   SUMMARY OF THE INVENTION 
   It is an object of the present invention to provide a logic circuit wherein the number of kinds of basic parts is suppressed to five so that a circuit which operates at a high speed can be designed. 
   It is another object of the present invention to provide a logic circuit wherein repetitiveness of wiring lines is increased so that a circuit which is simple in circuit scale and has a high degree of expandability can be designed. 
   It is a further object of the present invention to provide a logic circuit wherein the time required for tuning of components is reduced significantly to reduce the man-hours for layout significantly and reduce the man-hours for development significantly. 
   It is a still further object of the present invention to provide a logic circuit wherein the same basic parts are used so that augmentation of the yield can be achieved and reduction of the production cost can be promoted. 
   In order to attain the objects described above, according to an aspect of the present invention, there is provided a logic circuit, comprising a first inversion section for inverting a first input signal having one of positive logic and negative logic and outputting the inverted signal, a second inversion section for inverting a second input signal having the other of the positive logic and the negative logic and outputting the inverted signal, and a transmission section for selectively outputting one of the output of the first inversion section and the output of the second inversion section in accordance with a logical value which depends upon an externally controllable selection signal and an inverted signal of the selection signal. 
   The logic circuit having the construction described is advantageous in that it operates at a high speed. Further, since it includes double inverters, the isolation between a circuit following the transmission section and another circuit preceding to the first and second inversion sections is strengthened. Furthermore, since the necessity for provision of an inverter circuit in the circuit preceding to the first and second inversion sections is eliminated, there is an advantage that the circuit configuration can be simplified. 
   The logic circuit may further comprise a first switching section provided on an input side of the first inversion section and capable of performing switching of whether the first input signal should be passed or blocked in accordance with an external control signal, and a second switching section provided on an input side of the second inversion section and capable of performing switching of whether the second input signal should be passed or blocked in accordance with the external control signal. 
   The logic circuit having the construction just described operates at a high speed. Further, since it includes double inverters, the isolation between a circuit following the transmission section and another circuit preceding to the first and second switching sections is strengthened. Furthermore, since the necessity for provision of an inverter circuit in the circuit preceding to the first and second switching sections is eliminated, there is an advantage that the circuit configuration can be simplified. 
   According to another aspect of the present invention, there is provided a logic circuit, comprising a first inversion section for inverting a first input signal and outputting the inverted signal, a second inversion section for inverting a second input signal and outputting the inverted signal, a first outputting section for selectively outputting one of the output of the first inversion section and the output of the second inversion section in accordance with a logical value which depends upon an externally controllable first selection signal and an inverted signal of the first selection signal, and a second outputting section for selectively outputting one of the output of the first inversion section and the output of the second inversion section in accordance with a logical value which depends upon an externally controllable second selection signal and an inverted signal of the second selection signal. 
   Also the logic circuit having the construction described is advantageous in that it can achieve high speed operation, strengthening of the isolation and simplification in circuit configuration. 
   According to a further aspect of the present invention, there is provided a logic circuit, comprising a first inversion section for inverting a first input signal and outputting the inverted signal, a second inversion section for inverting a second input signal and outputting the inverted signal, and a transmission section capable of discriminating a magnitude relationship of 1 bit between the first input signal and the second input signal and outputting a result of the discrimination using a plurality of status signals. 
   Also the logic circuit having the construction described is advantageous in that it can achieve high speed operation, strengthening of the isolation and simplification in circuit configuration. 
   The transmission section may include a first gate section for indicating whether or not the first input signal is equal to or greater than the second input signal, a second gate section for indicating whether or not the first input signal is greater than the second input signal, a third gate section for indicating whether or not the first input signal is equal to or smaller than the second input signal, and a fourth gate section for indicating whether or not the first input signal is smaller than the second input signal. 
   With the logic circuit, since the double inverters are formed from CMOS logics, there is an advantage that high speed operation and strengthening of the isolation can be achieved. The logic circuit is further advantageous in that it can be simplified in circuit configuration. 
   According a still further aspect of the present invention, there is provided a logic circuit, comprising a first comparison section for receiving a first input signal of n 1  bits and a second input signal of n 1  bits, performing magnitude comparison between a predetermined number of bits of the first input signal and the predetermined number of bits of the second input signal and outputting results of the comparison of the predetermined number of bits as a p 1 th comparison result, a p 2 th comparison result, a p 3 th comparison result and a p 4 th comparison result using a plurality of status signals, n 1  being an integer equal to 2 to the m 1 th power, m 1  being an even number equal to or greater than 2, a second comparison section for performing magnitude comparison between a number of bits equal to twice the predetermined number of bits of the first input signal and a number of bits equal to twice the predetermined number of bits of the second input signal from the p 1 th comparison result and the p 2 th comparison result and outputting a result of the comparison of the predetermined number of bits as a p 5 th comparison result using the plurality of status signals and for performing magnitude comparison between a number of bits equal to twice the predetermined number of bits of the first input signal and a number of bits equal to twice the predetermined number of bits of the second input signal from the p 3 th comparison result and the p 4 th comparison result and outputting a result of the comparison of the predetermined number of bits as a p 6 th comparison result using the plurality of status signals, and a third comparison section for performing magnitude comparison between the n 1  bits of the first input signal and the n 1  bits of the second input signal from the p 5 th comparison result and the p 6 th comparison result and outputting a result of the comparison of the n 1  bits using the plurality of status signals. 
   The logic circuit having the construction described is simplified in circuit configuration and can make much use of repetitiveness of wiring lines. Further, a circuit configuration having a high degree of expandability can be produced and magnitude comparison circuits having different bit widths can be designed simply and efficiently. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly, and besides it is possible to design a circuit having a high degree of expandability. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Further, since the same leaf cells can be used, the logic circuit is advantageous in that it contributes to augmentation of the yield and so forth upon production. Furthermore, since each of the leaf cells normally produces two kinds of signals of a regular phase signal and an inverted phase signal in the inside thereof, there is an advantage that the entire circuit operates at a high speed. 
   According to a yet further aspect of the present invention, there is provided a logic circuit, comprising a half addition arithmetic section for receiving a first input signal of n 2  bits and an inverted signal of a second input signal of n 2  bits and performing half addition arithmetic of the first input signal and the inverted signal of the second input signal, n 2  being an integer equal to 2 to the m 2 th power, m 2  being an even number equal to or greater than 2, a first arithmetic section for performing full addition arithmetic of the first input signal and the inverted signal of the second input signal separately for each predetermined number of bits and outputting a result of the full addition arithmetic as a q 1 th carry, a q 2 th carry, a q 3 th carry and a q 4 th carry using a plurality of status signals, a second arithmetic section for outputting logical AND information of the q 1 th carry and the q 2 th carry as a q 5 th carry using the plurality of status signals and outputting logical AND information of the q 3 th carry and the q 4 th carry as a q 6 th carry using the plurality of status signals, a third arithmetic section for outputting logical AND information of the carries of all of the n 2  bits as a q 7 th carry using the plurality of status signals from at least the q 5 th carry and the q 6 th carry and, and a fourth arithmetic section for performing logical exclusive ORing of the output of the half addition arithmetic section and the q 7 th carry and outputting a full addition arithmetic result. 
   With the logic circuit having the construction described, adder circuits and magnitude comparison circuits of different bit widths can be obtained simply and efficiently and besides circuits which operate at a high speed can be designed. Further, since the same leaf cells are used, the yield and so forth upon production are improved. Furthermore, since the number of kinds of leaf cells can be suppressed, the development man-hours for leaf cells is reduced significantly, and besides, since the circuit scale is reduced as a whole, a layout can be designed with increased repetitiveness of wiring lines, and consequently, the man-hours can be reduced remarkably. 
   According to a yet further aspect of the present invention, there is provided a logic circuit, comprising a first inversion section for inverting a first input signal and outputting the inverted signal, a second inversion section for inverting the inverted signal of the first input signal and outputting a resulting signal, a first outputting section for performing NANDing arithmetic between the output of the first inversion section and a second input signal and outputting a resulting signal, and a second outputting section for performing NANDing arithmetic between the output of the second inversion section and an inverted signal of the second input signal and outputting a resulting signal, the first outputting section and the second outputting section being switched with the second input signal and the inverted signal of the second input signal. 
   The logic circuit having the construction described is advantageous in that, if input signals are applied appropriately to the first and second inversion sections, then the logic circuit can output a logical AND value and an inverted value of the AND value of the two high order bits based on positive logic and negative logic values of the 2 high order bits inputted thereto. Further, since the double inverters of the logic circuit are formed from CMOS logics, the logic circuit operates at a high speed, and besides, the isolation between a circuit on the output side and another circuit preceding to the logic circuit is strengthened. Furthermore, since the necessity for provision of an inverter circuit in the circuit preceding to the logic circuit is eliminated, there is an advantage that the burden on the circuit in the preceding stage can be reduced and the circuit configuration can be simplified. 
   According to a yet further aspect of the present invention, there is provided a logic circuit, comprising a first carry generation section for receiving a first input signal A&lt; 0 : n 3 &gt; of n 3  bits and an inverted signal XA&lt; 0 : n 3 &gt; of the first input signal of n 3  bits and outputting a first logical AND result and a first logical AND inversion result as a logical AND result at least of bits A&lt; 0 &gt; to A&lt; 2  to the m 3 th power−1&gt; from the first input signal bits A&lt; 0 :  2  to the m 3 th power−1&gt; and the inverted signal bits XA&lt; 0 :  2  to the m 3 th power−1&gt;, n 3  being an integer equal to 2 to the m 3 th power, m 3  being an even number equal to or greater than 2, a second carry generation section for outputting a second logical AND result and a second logical AND inversion result as a logical AND result at least of bits A&lt; 2  to the m 3 th power&gt; to A&lt; 2 ×2 to the m 3 th power−1&gt; from the first input signal bits A&lt; 2  to the m 3 th power: 2×2 to the m 3 th power−1&gt; and the inverted signal bits XA&lt; 2  to the m 3 th power: 2×2 to the m 3 th power−1&gt;, a third carry generation section for outputting a third logical AND result and a third logical AND inversion result as a logical AND result at least of bits A&lt; 2 ×2 to the m 3 th power&gt; to A&lt; 3 ×2 to the m 3 th power−1&gt; from the first input signal bits A&lt; 2 ×2 to the m 3 th power: 3×2 to the m 3 th power−1&gt; and the inverted signal bits XA&lt; 2 ×2 to the m 3 th power: 3×2 to the m 3 th power−1&gt;, a fourth carry generation section for outputting a fourth logical AND result and a fourth logical AND inversion result as a logical AND result at least of bits A&lt; 3 ×2 to the m 3 th power&gt; to A&lt; 4 ×2 to the m 3 th power−1&gt; from the first input signal bits A&lt; 3 ×2 to the m 3 th power: 4×2 to the m 3 th power−1&gt; and the inverted signal bits XA&lt; 3 ×2 to the m 3 th power: 4×2 to the m 3 th power−1&gt;, a first logical AND generation section for receiving the first logical AND result and the first logical AND inversion result as well as the second logical AND result and the second logical AND inversion result and outputting a fifth logical AND result and a fifth logical AND inversion result as a logical AND result at least of the bits A&lt; 0 &gt; to A&lt; 2 ×2 to the m 3 th power−1&gt;, a second logical AND generation section for receiving the third logical AND result and the third logical AND inversion result as well as the fourth logical AND result and the fourth logical AND inversion result and outputting a sixth logical AND result and a sixth logical AND inversion result as a logical AND result at least of the bits A&lt; 2 ×2 to the m 3 th power&gt; to A&lt; 4 ×2 to the m 3 th power−1&gt;, a third logical AND generation section for outputting a seventh logical AND result and a seventh logical AND inversion section as a logical AND result at least of the bits A&lt; 0 &gt; to A&lt; 2 ×2 to the m 3 th power−1&gt; from the fifth logical AND result and the fifth logical AND inversion result as well as the sixth logical AND result and the sixth logical AND inversion result, a fourth logical AND generation section for outputting an eighth logical AND result and an eighth logical AND inversion result as a logical AND result at least of the bits A&lt; 2  to the m 3 th power&gt; to A&lt; 3 ×2 to the m 3 th power−1&gt; from the second logical AND result and the second logical AND inversion result as well as the sixth logical AND result and the sixth logical AND inversion result, and a full addition arithmetic section for outputting a full addition arithmetic result of n 3  bits from a first gate signal of n 3  bits which includes the seventh logical AND result, the eighth logical AND result, the sixth logical AND result and the fourth logical AND result and a second gate signal of n 3  bits which includes the seventh logical AND inversion result, the eighth logical AND inversion result, the sixth logical AND inversion result and the fourth logical AND result. 
   The logic circuit having the construction described is simple in circuit configuration, and a designer can design a circuit which is simple and efficient. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Further, since the same leaf cells can be used, the logic circuit is advantageous in that it contributes to augmentation of the yield and so forth upon production. Furthermore, since two kinds of signals of a regular phase signal and an inverted phase signal are normally produced and used in the inside of each of the leaf cells, there is an advantage that the entire circuit operates at a high speed. 
   The plurality of status signals may include a first gate signal for indicating whether or not the first input signal is equal to or greater than the second input signal, a second gate signal for indicating whether or not the first input signal is greater than the second input signal, a third gate signal for indicating whether or not the first input signal is equal to or smaller than the second input signal, and a fourth gate signal for indicating whether or not the first input signal is smaller than the second input signal. 
   The logic circuit having the construction described is advantageous in that it operates at a high speed and besides the individual cells can be linked to each other readily. Further, by utilizing same status signals for different output signals, the linking property between the cells is raised, and this increases the expandability of the circuit. Further, the hierarchy can be made deeper. 
   The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements denoted by like reference symbols. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing a construction of a first leaf cell according to an embodiment of the present invention; 
       FIG. 2  is a block diagram showing a construction of a second leaf cell according to the embodiment of the present invention; 
       FIG. 3  is a block diagram showing a construction of a third leaf cell according to the embodiment of the present invention; 
       FIG. 4  is a diagrammatic view illustrating logic values of a cell LGEN; 
       FIG. 5  is a block diagram showing a construction of a 4-bit magnitude comparison circuit according to the embodiment of the present invention; 
       FIG. 6  is a block diagram showing a construction of a link selector circuit according to the embodiment of the present invention; 
       FIG. 7  is a block diagram showing a construction of a 4-bit magnitude comparison circuit according to the embodiment of the present invention; 
       FIG. 8  is a block diagram showing a construction of a 16-bit magnitude comparison circuit according to the embodiment of the present invention; 
       FIG. 9  is a block diagram showing a construction of another 16-bit magnitude comparison circuit according to the embodiment of the present invention; 
       FIG. 10  is a block diagram showing an n 1 -bit (n 1 =64) magnitude comparison circuit according to the embodiment of the present invention; 
       FIG. 11  is a block diagram showing a construction of a 4-bit full adder circuit according to the embodiment of the present invention; 
       FIG. 12  is a diagrammatic view illustrating logic values of another cell LGEN; 
       FIG. 13  is a block diagram showing a construction of a 4-bit full adder circuit according to the embodiment of the present invention; 
       FIG. 14  is a block diagram showing a construction of a 16-bit full adder circuit according to the embodiment of the present invention; 
       FIG. 15  is a block diagram showing a construction of a first arithmetic section, a second arithmetic section, and a third arithmetic section of another 16-bit full adder circuit according to the embodiment of the present invention; 
       FIG. 16  is a block diagram showing a construction of an n 2 -bit (n 2 =64) full adder circuit according to the embodiment of the present invention; 
       FIG. 17  is a block diagram showing a construction of a fourth leaf cell according to the embodiment of the present invention; 
       FIG. 18(   a ) is a diagrammatic view illustrating logic values at input side terminals S, XS, A 1  and an output side terminal X 1  of a cell A 001 ; 
       FIG. 18(   b ) is a diagrammatic view illustrating logic values at input side terminals S, XS, A 2  and an output side terminal X 2  of the cell A 001 ; 
       FIG. 19  is a diagrammatic view illustrating logic values of the fourth leaf cell according to the embodiment of the present invention; 
       FIG. 20  is a block diagram showing a construction of a fifth leaf cell according to the embodiment of the present invention; 
       FIG. 21  is a diagrammatic view illustrating logic values of a cell A 002  according to the embodiment of the present invention; 
       FIG. 22  is a block diagram showing a construction of a 4-bit carry generation circuit according to the embodiment of the present invention; 
       FIG. 23  is a block diagram showing a construction of a 16-bit carry generation circuit according to the embodiment of the present invention; 
       FIG. 24  is a block diagram showing a construction of a 64-bit increment circuit according to the embodiment of the present invention; 
       FIG. 25  is a block diagram showing a construction of a 68+bit+4-bit adder circuit according to the embodiment of the present invention; 
       FIG. 26  is a block diagram showing an example of a functional block of an 8-bit look-ahead carry full adder circuit; 
       FIG. 27  is a block diagram showing a detailed construction of a carry generation/propagation unit; 
       FIG. 28  is a block diagram showing a general construction of a 4-bit CLA unit; 
       FIG. 29  is a block diagram showing details of a sum unit; and 
       FIG. 30  is a block diagram showing a construction of a 16-bit increment circuit in which a multi-input AND gate is used. 
   

   DESCRIPTION OF THE PREFERRED EMBODIMENT 
   A. First Embodiment of the Invention 
     FIG. 1  is a block diagram showing a construction of a first leaf cell according to an embodiment of the present invention. Referring to  FIG. 1 , the cell LEOR shown is a CMOS logic circuit composed of a first inversion section  1   a , a second inversion section  1   b , and a transmission section  1   c , and has terminals A, XS, S, XA and X. 
   The first inversion section  1   a  inverts a first input signal having one of positive logic and negative logic and outputs the inverted signal. The first inversion section  1   a  includes two CMOS logics  1   aa  and  1   ab  connected in parallel. A signal inputted from the terminal A is inputted to the transistor gates of the two CMOS logics  1   aa  and  1   ab . When the input signal from the terminal A is 1, a gate T 1  has an off state and a gate T 2  has an on state, and a signal line P 100  has a ground potential. On the other hand, when the input signal from the terminal A is 0, the gate T 1  is on and the gate T 2  is off, and the signal line P 100  has a high bias. The signal line P 100  thus outputs the input signal with the inverted logic value, and the two CMOS logics  1   aa  and  1   ab  function as a double inverter circuit. It is to be noted that the mark ◯ at the gate T 1  represents an inversion operation. It is to be noted that the gates T 1  and T 2  or like transistors in pair may be hereinafter referred to as pair transistors. 
   The second inversion section  1   b  inverts a second input signal having the other of the positive logic and the negative logic and outputs the inverted signal. The second inversion section  1   b  includes two CMOS logics connected in parallel and functions as a double inverter circuit. The transmission section  1   c  selectively outputs one of an output of the first inversion section  1   a  and an output of the second inversion section  1   b  in accordance with a logical value provided by an externally controllable selection signal and an inverted signal of the selection signal and is formed from pair transistors T 3 , T 4  and T 7 , T 8 . 
   In the cell LEOR, an input signal is inputted from the terminal A of the first inversion section  1   a  to the two CMOS logics and inverted by and outputted from the CMOS logics. Meanwhile, the inverted signal of the input signal is inputted from the terminal XA of the second inversion section  1   b  to the two CMOS logics and is inverted by and outputted from the CMOS logics. Then, when the selection signal from the terminal S is 1 and the inverted signal of the selection signal from the terminal XS is 0, the pair transistors T 3 , T 4  in the transmission section  1   c  exhibit an on-state while the pair transistors T 7 , T 8  exhibit an off state, and an input inversion signal on the signal line P 100  in the transmission section  1   c  is outputted from the output terminal X. On the contrary when the selection signal from the terminal S is 0 and the inverted signal of the selection signal from the terminal XS is 1, the pair transistors T 3 , T 4  exhibit an off-state and the pair transistors T 7 , T 8  exhibit an on-state, and an input inversion signal on another signal line P 101  in the transmission section  1   c  is outputted from the output terminal X. Accordingly, the cell LEOR functions as a selector circuit which selectively outputs one of two input signals in accordance with a control signal. Further, the transmission section  1   c  functions as a driver which outputs the logical value of 0 or 1. 
   The cell LEOR is advantageous in that it operates at a high speed because the double inverters thereof are formed from CMOS logics in this manner. Further, since the cell LEOR includes double inverters, the isolation (reverse current prevention) between a circuit following the transmission section  1   c  and another circuit preceding to the cell LEOR is strengthened. Furthermore, the cell LEOR eliminates the necessity for provision of an inverter circuit in the circuit preceding to the cell LEOR, and consequently, it is advantageous in that the circuit configuration can be simplified. 
     FIG. 2  is a block diagram showing a construction of a second leaf cell according to the embodiment of the present invention. Referring to  FIG. 2 , the cell LSEL 2  shown is a CMOS logic circuit composed of a first inversion section  2   a , a second inversion section  2   b , a first outputting section  2   c  and a second outputting section  2   d  and has terminals S 1 , A 1 , XS 1 , S 2 , A 2 , XS 2 , X 1  and X 2 . The reference symbols S 1 , A 1 , XS 1 , S 2 , A 2 , XS 2 , X 1  and X 2  may sometimes denote signals at the respective terminals. 
   The first inversion section  2   a  outputs a signal XA 1  inverted from a first input signal A 1  and is composed of two CMOS logics connected in parallel. The second inversion section  2   b  outputs a signal XA 2  inverted from a second input signal A 2  and is composed of two CMOS logics connected in parallel. Each of the first inversion section  2   a  and the second inversion section  2   b  functions as a double inverter circuit. The first outputting section  2   c  selectively outputs one of an output XA 1  of the first inversion section  2   a  and an output XA 2  of the second inversion section  2   b  in accordance with a logic value which depends upon an externally controllable first selection signal S 1  and an inverted signal XS 1  of the first selection signal S 1 . The second outputting section  2   d  selectively outputs one of the output XA 1  of the first inversion section  2   a  and the output XA 2  of the second inversion section  2   b  in accordance with an externally controllable second selection signal S 2  and an inverted signal XS 2  of the second selection signal S 2 . 
   When the first selection signal S 1  is 0 and the inverted signal XS 1  of the first selection signal S 1  is 1, gates T 11  and T 12  are on and gates T 13  and T 14  are off, and the inverted signal XA 1  of the first input signal A 1  is outputted to the output terminal X 1  of the first outputting section  2   c . On the contrary, when the first selection signal S 1  is 1 and the inverted signal XS 1  of the first selection signal S 1  is 0, the gates T 11  and T 12  are off and the gates T 13  and T 14  are on, and the inverted signal XA 2  of the input signal A 2  is outputted to the output terminal X 1  of the first outputting section  2   c.    
   Similarly, when the second selection signal S 2  is 0 and the inverted signal XS 2  of the second selection signal S 2  is 1, gates T 17  and T 18  are off and gates T 19  and T 20  are on, and the inverted signal XA 2  of the input signal A 2  is outputted to the output terminal X 2  of the second outputting section  2   d . On the contrary, when the second selection signal S 2  is 1 and the inverted signal XS 2  of the second selection signal S 2  is 0, the gates T 17  and T 18  are on and the gates T 19  and T 20  are off, and the inverted signal XA 1  of the input signal A 1  is outputted to the output terminal X 2  of the second outputting section  2   d . Accordingly, the cell LSEL 2  functions as a selector which selectively outputs one of the inverted signals XA 1  and XA 2  of the two input signals A 1  and A 2  in accordance with the first selection signal S 1  and the second selection signal S 2 . 
   In this manner, the first outputting section  2   c  and the second outputting section  2   d  of the cell LSEL 2  commonly use the double inverter circuits for obtaining inverted signals, and consequently, the cell LSEL 2  can be produced in a reduced circuit scale. Further, since the circuits in the stage preceding to the first outputting section  2   c  and the second outputting section  2   d  do not have a complicated circuit configuration and may be formed with low loads, the cell LSEL 2  can be formed in a simple circuit configuration. 
     FIG. 3  is a block diagram showing a construction of a third leaf cell according to the embodiment of the present invention. Referring to  FIG. 3 , the cell LGEN shown is a CMOS logic circuit composed of a first inversion section  3   a , a second inversion section  3   b  and a transmission section  3   c , and has input terminals A 1  and A 2  and output terminals GE, GT, LE and LT. Also the reference symbols A 1 , A 2 , GE, GT, LE and LT are sometimes used to denote signals at the respective terminals. 
   The first inversion section  3   a  inverts a first input signal A (signal from the terminal A) and outputs the inverted signal. The second inversion section  3   b  inverts a second input signal B (signal from the terminal B) and outputs the inverted signal. Each of the first inversion section  3   a  and the second inversion section  3   b  functions as a double inverter circuit. The transmission section  3   c  can discriminate a relationship in magnitude of one bit between the first input signal A and the second input signal B and output a result of the discrimination using four kinds of status signals. The transmission section  3   c  is composed of a first gate section  3   d , a second gate section  3   e , a third gate section  3   f  and a fourth gate section  3   g . The four kinds of status signals are four different status signals of GE (Greater or Equal), GT (Greater Than), LE (Less or Equal) and LT (Less Than). For example, when comparison discrimination in magnitude between a bit J 1  and another bit J 2  is to be performed, if J 1 =1 and J 2 =0 are given, then since J 1 ≧J 2 , only the GE signal exhibits 1 while the other signals GT, LE and LT exhibit 0. Then, the GE signal is outputted from the first gate section  3   d ; the GT signal is outputted from the second gate section  3   e ; the LE signal is outputted from the third gate section  3   f ; and the LT signal is outputted from the fourth gate section  3   g.    
   In particular, the first gate section  3   d  indicates whether or not the input signal A is equal to or higher than the input signal B (A≧B), and outputs 1, for example, when the input signal A is 1 and the input signal B is 0, when the input signal A is 1 and the input signal B is 1, or when the input signal A is 0 and the input signal B is 0. The second gate section  3   e  indicates whether or not the input signal A is higher than the input signal B (A&gt;B), and outputs 1, for example, when the input signal A is 1 and the input signal B is 0. The third gate section  3   f  indicates whether or not the input signal A is equal to or lower than the input signal B (A≦B) and outputs 1, for example, when the input signal A is 0 and the input signal B is 1, when the input signal A is 1 and the input signal B is 1 or when the input signal A is 0 and the input signal B is 0. The fourth gate section  3   g  indicates whether or not the input signal A is lower than the input signal B (A&lt;B) and outputs 1, for example, when the input signal A is 0 and the input signal B is 1. 
     FIG. 4  is a diagrammatic view illustrating logical values of the cell LGEN described above. A relationship between magnitude comparison results between the signals A and B and logical arithmetic is described below with reference to the logical value table shown in  FIG. 4 . The symbol A appearing in  FIG. 4  represents a logical value of the first input signal and XA represents an inverted logical value of the first input signal, and B represents a logical value of the second input signal and XB represents an inverted logical value of the second input signal. The symbols OR(GE), AND(GT), NAND(LE) and NOR(LT) represent output logic values of the first gate section  3   d , second gate section  3   e , third gate section  3   f  and fourth gate section  3   g , respectively. In the column denoted by OR(GE) in  FIG. 4 , the value 1 appears when A is equal to or greater than B, and this coincides with a result of ORing arithmetic between A and XB. In the column denoted by AND(GT) in  FIG. 4 , the value 1 appears when A is greater than B, and this coincides with a result of ANDing operation between A and XB. In the column denoted by NAND(LE) in  FIG. 4 , the value 1 appears when A is equal to or smaller than B, and this coincides with a result of NANDing arithmetic between A and XB. In the column denoted by NOR(LT) in  FIG. 4 , the value 1 appears when A is smaller then B, and this coincides with a result of NORing arithmetic between A and XB. Thus, a result of magnitude comparison of one bit is represented by a result of logical arithmetic between A and XB. In other words, the cell LGEN functions as a magnitude comparison circuit which performs magnitude comparison between the input signal A and the input signal B by comparison between the input signal A and the inverted signal XB of the input signal B. 
   Where the four kinds of status signals are used in this manner, there are advantages that the circuit operates at a high speed and that connection between cells is facilitated. In particular, as the output signal uses the same status signals, the connection facility between cells is increased, and this increases the expandability of the circuit. Consequently, the depth of the hierarchy of the circuit can be increased. 
   Referring back to  FIG. 3 , when the input signal A is 1 and the input signal B is 0, the gates operate in the following manner. Since a signal line P 102  shown in  FIG. 3  exhibits 0, the gates directly connected to the signal line P 102  exhibit the following logical values. In particular, a gate T 23  is on; another gate T 24  is off; a further gate T 25  is on; a still further gate T 26  is off; a yet further gate T 29  is on; and a yet further gate T 30  is off. Meanwhile, since the gate T 23  is off and another signal line P 104  has a high bias state, another gate T 27  exhibits an off-state and a further gate T 28  exhibits an on-state. Accordingly, a high bias is applied to the first gate section  3   d  through the gate T 25 , and “1” is outputted from the first gate section  3   d . Further, since the gates T 28  and T 29  both exhibit an on-state, “1” on a further signal line P 103  is outputted to the second gate section  3   e.    
   Further, since the signal line P 103  shown in  FIG. 3  exhibits 1, the gates directly connected to the signal line P 103  exhibit the following logical values. In particular, a gate T 33  is off; another gate T 34  is on; a further gate T 35  is off; a still further gate T 36  is on; a yet further gate T 39  is off; and a yet further gate T 40  is on. Further, since the gate T 33  is off and the gate T 34  is on, another gate T 37  is grounded and turned on, and consequently, a further gate T 38  is turned off. Accordingly, since the gates T 36  and T 37  are on, “0” on the signal line P 102  is outputted to the third gate section  3   f . Further, since the gate T 40  is grounded, “0” is outputted to the fourth gate section  3   g.    
   For any other combination of the bits A and B, the gates logically operate similarly as described above except that different logical values are inputted to the gates, and accordingly, detailed description of the operations of the gates is omitted here. 
   In this manner, in the cell LGEN, logical values on the signal lines P 102  and P 103  are inputted to the transmission section  3   c  and the logical values and inverted logical values of them are used in pairs in the transmission section  3   c . Therefore, the cell LGEN is advantageous in that inversion processing for inverting positive phase signals again is not required and the processing speed is augmented. Further, since the outputs of the first inversion section and the second inversion section are used commonly by the upper and lower side blocks, there is an advantage that the circuit scale can be reduced. Furthermore, thanks to the presence of the gate sections T 21 , T 22 , T 31  and T 32  of  FIG. 3 , the isolation between the input side and the output side is improved very much, and possible leakage of a signal of the output side to the input side is eliminated. 
   Now, a magnitude comparison circuit is described as an arithmetic circuit which uses the three kinds of leaf cells described above. 
     FIG. 5  is a block diagram showing a construction of a 4-bit magnitude comparison circuit according to the embodiment of the present invention. Referring to  FIG. 5 , the 4-bit magnitude comparison circuit (ICMP 4 )  13  is a CMOS logic circuit which compares 4-bit signals in magnitude and outputs four kinds of status signals GE, GT, LE and LT. The 4-bit magnitude comparison circuit  13  includes a first carry generation section  14 , a second carry generation section  15 , and a third carry generation section  16 . It is to be noted here that, in  FIG. 5 , reference symbols A&lt; 0 :  3 &gt; and B&lt; 0 :  3 &gt; denote 4-bit signals different from each other, and GT, GE, LE and LT denote output signals different from one another. Also reference symbols &lt; 0 &gt;, &lt; 1 &gt;, &lt; 2 &gt; and &lt; 3 &gt; denote different signals. 
   The first carry generation section  14  receives a 4-bit input signal A&lt; 0 :  3 &gt; and another 4-bit input signal B&lt; 0 :  3 &gt;, performs comparison between the 4-bit input signal A&lt; 0 :  3 &gt; and the 4-bit input signal B&lt; 0 :  3 &gt; in magnitude for each bit and outputs results of the comparison of the individual bits as a first comparison result, a second comparison result, a third comparison result and a fourth comparison result using the four kinds of status signals. The first carry generation section  14  includes four magnitude discrimination circuits  14   a ,  14   b ,  14   c  and  14   d , each of which is formed from a cell LGEN described hereinabove. Two kinds of signals A and B (denoted by &lt; 0 &gt;&lt; 0 &gt;, &lt; 1 &gt;&lt; 1 &gt;, &lt; 2 &gt;&lt; 2 &gt;, &lt; 3 &gt;&lt; 3 &gt; in  FIG. 5 ) are inputted to the input terminals A, B of the magnitude discrimination circuits  14   a ,  14   b ,  14   c ,  14   d , respectively. 
   The second carry generation section  15  performs comparison in magnitude between the two high order bits A&lt; 0 :  1 &gt; of the first input signal and the two high order bits B&lt; 0 :  1 &gt; of the second input signal from the first comparison result and the second comparison result and output results of the comparison of the 2 bits as a fifth comparison result using the four kinds of status signals. Further, the second carry generation section  15  performs comparison in magnitude between the two low order bits A&lt; 2 :  3 &gt; of the first input signal and the two low order bits B&lt; 2 :  3 &gt; of the second input signal from the third comparison result and the fourth comparison result and output results of the comparison of the 2 bits as a sixth comparison result using the four kinds of status signals. The second carry generation section  15  includes four selector circuits  15   a ,  15   b ,  15   c  and  15   d , each of which is formed from a cell LSEL 2  described hereinabove. It is to be noted that the two high order bit comparison function is exhibited by the two selector circuits  15   a  and  15   b  while the two low order bit comparison function is exhibited by the two selector circuits  15   c  and  15   d.    
   The third carry generation section  16  performs comparison in magnitude between the four bits A&lt; 0 :  3 &gt; of the first input signal and the two four bits B&lt; 0 :  3 &gt; of the second input signal from the fifth comparison result and the sixth comparison result and outputs a result of the comparison of the 4 bits using the four kinds of status signals. The third carry generation section  16  includes two selector circuits  16   a  and  16   b , each of which is formed from a cell LSEL 2  described hereinabove. 
   In the 4-bit magnitude comparison circuit  13  described above, an input signal A&lt; 0 :  3 &gt; and another input signal B&lt; 0 :  3 &gt; are inputted to the first carry generation section  14 . In the first carry generation section  14 , the magnitude discrimination circuits  14   a  performs comparison discrimination in magnitude between the bit A&lt; 0 &gt; and the bit B&lt; 0 &gt; and outputs a first comparison result using the four kinds of status signals GE, GT, LE and LT (refer to an alternate long and short dash line *A in  FIG. 5 ). Similarly, the magnitude discrimination circuit  14   b  performs comparison discrimination in magnitude between the bit A&lt; 1 &gt; and the bit B&lt; 1 &gt; and outputs a second comparison result using the four kinds of status signals GE, GT, LE and LT. Also, the magnitude discrimination circuit  14   c  performs comparison discrimination in magnitude between the bit A&lt; 2 &gt; and the bit B&lt; 2 &gt; and outputs a third comparison result using the four kinds of status signals GE, GT, LE and LT, and the magnitude discrimination circuit  14   d  performs comparison discrimination in magnitude between the bit A&lt; 3 &gt; and the bit B&lt; 3 &gt; and outputs a fourth comparison result using the four kinds of status signals GE, GT, LE and LT. 
   Subsequently, connection destinations of the output signals of the first carry generation section  14  are described. For the convenience of description below, signal terminals of the cells LSEL 2  in the second carry generation section  15  are defined in the following manner. In particular, A 1 , A 2 , S, XS 1 , S 2  and XS 2  are referred to as first input terminal, second input terminal, first selection signal terminal, first selection signal inversion terminal, second selection signal terminal and second selection signal inversion terminal, respectively. 
   A GT signal from the cell LGEN  14   a  in the first carry generation section  14  is inputted to the fist input terminal A 1  of the selector circuit  15   b ; a GE signal is inputted to the second input signal A 2  of the selector circuit  15   b ; an LE signal is inputted to the first input terminal A 1  of the selector circuit  15   a ; and an LT signal is inputted to the second input signal A 2  of the selector circuit  15   a . Meanwhile, connection destinations of the second comparison result from the cell LGEN  14   b  in the first carry generation section  14  are such as follows. In particular, the GT signal is inputted to the first selection signal terminal S 1  of the selector circuit  15   a  and the first selection signal terminal S 1  of the selector circuit  15   b ; the GE signal is inputted to the second selection signal inversion terminal XS 2  of the selector circuit  15   a  and the second selection signal inversion terminal XS 2  of the selector circuit  15   b ; the LE signal is inputted to the first selection signal inversion terminal XS 1  of the selector circuits  15   a  and the first selection signal inversion terminal XS 1  of the selector circuit  15   b ; and the LT signal is inputted to the second selection signal terminal S 2  of the selector circuit  15   a  and the second selection signal terminal S 2  of the selector circuit  15   b.    
   The selector circuits  15   a  and  15   b  cooperate to perform magnitude comparison discrimination between the two high order bits A&lt; 0 :  1 &gt; of the first input signal and the two high order bits B&lt; 0 :  1 &gt; of the second input signal. Results of the comparison of the 2 bits are outputted as a fifth comparison result from the output terminals X 1  and X 2  of the selector circuit  15   a  and the output terminals X 1  and X 2  of the selector circuit  15   b  using the four kinds of status signals (refer to an alternate long and short dash line *B in  FIG. 5 ). 
   Similar comparison is performed for the two low order bits A&lt; 2 ;  3 &gt;. In particular, as seen from  FIG. 5 , the four kinds of status signals of the third comparison result and the fourth comparison result are inputted from predetermined terminals to the input terminals of the selector circuits  15   c  and  15   d  in the second carry generation section  15 . Then, the two selector circuits  15   c  and  15   d  perform magnitude comparison discrimination between the two low order bits A&lt; 2 :  3 &gt; of the first input signal and the two low order bits B&lt; 2 :  3 &gt; of the second input signal and outputs a result of the comparison of the 2 bits as a sixth comparison result from the output terminals X 1  and X 2  of the selector circuit  15   c  and the output terminals X 1  and X 2  of the selector circuit  15   d  using the four kinds of status signals. 
   Further, the four kinds of status signals of the fifth comparison result are inputted to predetermined terminals of the selector circuits  16   a  and  16   b  in the third carry generation section  16 . In particular, the output terminal X 1  of the selector circuit  15   a  is inputted to the first input terminal A 1  of the selector circuit  16   b ; the output terminal X 2  of the selector circuit  15   a  is inputted to the second input signal A 2  of the selector circuit  16   b ; the output terminal X 1  of the selector circuit  15   b  is inputted to the first input terminal A 1  of the selector circuit  16   a ; and the output terminal X 2  of the selector circuit  15   b  is inputted to the second input signal A 2  of the selector circuit  16   a . Also the four kinds of status signals of the sixth comparison result are inputted similarly. In particular, the output terminal X 1  of the selector circuit  15   c  is inputted to the first selection signals S 1  of the selector circuits  16   a  and  16   b ; the output terminal X 2  of the selector circuit  15   c  is inputted to the second selection signal inversion terminals XA 2  of the selector circuits  16   a  and  16   b ; the output terminal X 1  of the selector circuit  15   d  is inputted to the first selection signal inversion terminals XS 1  of the selector circuits  16   a  and  16   b ; and the output terminal X 2  of the selector circuit  15   d  is inputted to the second selection signal terminals S 2  of the selector circuits  16   a  and  16   b.    
   Then, the third carry generation section  16  performs magnitude comparison discrimination between the input signal A&lt; 0 :  3 &gt; and the input signal B&lt; 0 :  3 &gt; from the fifth comparison result and the sixth comparison result, and outputs a comparison result of the 4 bits using the four kinds of status signals (GE, GT, LE, LT) (refer to an alternate long and short dash line *C in  FIG. 5 ). 
   Since the 4-bit magnitude comparison circuit  13  is formed from the cells LGEN and LSEL 2  and two kinds of signals of a positive phase signal and an inverted phase signal are normally produced and used in the cells in this manner, it has an advantage that high speed circuit operation can be achieved. Further, since such cells LGEN and LSEL 2  as described above are used, the 4-bit magnitude comparison circuit  13  has a simple circuit configuration. 
   It is to be noted that it is possible to use some other circuit representation.  FIG. 6  is a block diagram showing a construction of a link selector circuit according to the embodiment of the present invention. Referring to  FIG. 6 , the link selector circuit (LSEL 2 ×2)  6  is composed of to such cells LSEL 2  as shown in  FIG. 2  connected to each other, and includes a first branch section  6   a , a second branch section  6   b , a third branch section  6   c , a fourth branch section  6   d , and a pair of selector circuits  6   e  and  6   f.    
   The first branch section  6   a  receives two kinds of comparison result information using four kinds of status signals (GE 0 , GT 0 , LE 0 , LT 0  and GE 1 , GT 1 , LE 1 , LT 1 ) and branches the GT1 signal; the second branch section  6   b  branches the GE1 signal; the third branch section  6   c  branches the LE1 signal; and the fourth branch section  6   d  branches the LT1 signal. The selector circuit  6   e  receives signals outputted from the first branch section  6   a , second branch section  6   b , third branch section  6   c  and fourth branch section  6   d , and the LE0 signal and the LT0 signal. The selector circuit  6   f  receives signals outputted from the first branch section  6   a , second branch section  6   b , third branch section  6   c  and fourth branch section  6   d , and the GT0 signal and the GE0 signal. Each of the selectors  6   e  and  6   f  is formed from a cell LSEL 2  described hereinabove. 
   If the 4-bit magnitude comparison circuit  13  of  FIG. 5  is re-arranged using the link selector circuit  6 , then such a circuit configuration as shown in  FIG. 7  is obtained.  FIG. 7  is a block diagram showing a construction of the 4-bit magnitude comparison circuit (ICMP 4 )  13  according to the embodiment of the present invention. A second carry generation section  17  shown in  FIG. 7  corresponds to the second carry generation section  15  shown in  FIG. 5 , and a third carry generation section  18  corresponds to the third carry generation section  16  shown in  FIG. 5 . Referring to  FIG. 7 , the second carry generation section  17  is composed of a link selector circuit  17   a  which receives the first comparison result and the second comparison result as input signals and outputs the fifth comparison result, and a link selector circuit  17   b  which receives the third comparison result and the fourth comparison result as input signals and outputs the sixth comparison result, and the third carry generation section  18  is composed of a link selector circuit  18   a  which receives the fifth comparison result and the sixth comparison result as input signals and outputs a result of comparison of the four bits. It is to be noted that, while some other elements may possibly be denoted by like reference symbols to those given above, they have similar or equivalent functions to those described above, and therefore, overlapping description of them is omitted herein. Employment of the link selector circuit  6  makes it possible to design a circuit having a high degree of expandability. 
   Now, a circuit which performs magnitude comparison of 16 bits is described with reference to  FIGS. 8 and 9 . 
     FIG. 8  is a block diagram showing a construction of a 16-bit magnitude comparison circuit according to the embodiment of the present invention. Referring to  FIG. 8 , the 16-bit magnitude comparison circuit (ICPM 16 )  20  compares 16-bit signals with each other in magnitude and outputs four kinds of status signals GE, GT, LE and LT. The 16-bit magnitude comparison circuit  20  is composed of a first comparison section  21 , a second comparison section  22 , and a third comparison section  23 . In  FIG. 8 , reference symbol A&lt; 0 :  15 &gt; denotes an input signal of 16 bits and B&lt; 0 :  15 &gt; denotes another input signal of 16 bits, and GT, GE, LE and LT appearing in  FIG. 8  denote output signals. The same references may also be used as the names of the signal terminals. The input signals A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt; are divided into 4 bits A&lt; 0 :  3 &gt; and B&lt; 0 :  3 &gt;, 4 bits A&lt; 4 :  7 &gt; and B&lt; 4 :  7 &gt;, 4 bits A&lt; 8 :  11 &gt; and B&lt; 8 :  11 &gt;, and 4 bits A&lt; 12 :  15 &gt; and B&lt; 12 :  15 &gt; in the first comparison section  21 . 
   The first comparison section  21  receives a 16-bit input signal A&lt; 0 : 15 &gt; and another 16-bit input signal B&lt; 0 : 15 &gt;, performs magnitude comparison between the four high order bits A&lt; 0 :  3 &gt; of the former input signal and the four high order bits B&lt; 0 :  3 &gt; of the latter input signal, and outputs a result of the comparison of the four bits as a first comparison result, a second comparison result, a third comparison result and a fourth comparison result using the four kinds of status signals. The first comparison section  21  is composed of four kinds of 4-bit magnitude comparison circuits  21   a ,  21   b ,  21   c  and  21   d , each of which is formed from the 4-bit magnitude comparison circuit  13  (refer to  FIG. 5  or  7 ) described hereinabove. 
   The second comparison section  22  performs magnitude comparison between the eight high order bits A&lt; 0 :  7 &gt; of the input signal A&lt; 0 :  15 &gt; and the eight high order bits B&lt; 0 :  7 &gt; of the input signal B&lt; 0 :  15 &gt; from the first comparison result and the second comparison result and outputs a result of the comparison of the eight high order bits as a fifth comparison result using the four kinds of status signals. Further, the second comparison section  22  performs magnitude comparison between the eight low order bits A&lt; 8 :  15 &gt; of the input signal A&lt; 0 :  15 &gt; and the eight low order bits B&lt; 8 :  15 &gt; of the input signal B&lt; 0 :  15 &gt; from the third comparison result and the fourth comparison result and outputs a result of the comparison of the eight low order bits as a sixth comparison result using the four kinds of status signals. The second comparison section  22  is composed of four such cells LSEL 2  as described hereinabove. The third comparison section  23  performs magnitude comparison between the 16 bits of the input signal A&lt; 0 :  15 &gt; and the 16 bits of the input signal B&lt; 0 :  15 &gt; from the fifth comparison result and the sixth comparison result and outputs a result of the comparison of the 16 bits using the four kinds of status signals. The third comparison section  23  is composed of two cells LSEL 2 . 
   In the 16-bit magnitude comparison circuit  20  described above, such magnitude relationships of 4 bits as described hereinabove with reference to  FIG. 5  are determined on an alternate long and short dash line *A in  FIG. 8 ; magnitude relationships of 8 bits are determined on another alternate long and short dash line *B; and a magnitude relationship of 16 bits is determined on a further alternate long and short dash line *C. 
   If the 16-bit magnitude comparison circuit  20  of  FIG. 8  is re-arranged using the link selector circuit  6  shown in  FIG. 6 , then such a circuit configuration as shown in  FIG. 9  is obtained.  FIG. 9  is a block diagram showing a construction of the 16-bit magnitude comparison circuit (ICMP 16 )  20  according to the embodiment of the present invention. A second comparison section  24  shown in  FIG. 9  corresponds to the second comparison section  22  shown in  FIG. 8 , and a third comparison section  25  corresponds to the third comparison section  23  shown in  FIG. 8 . Referring to  FIG. 9 , the second comparison section  24  is composed of a link selector circuit  24   a  which receives the first comparison result and the second comparison result as input signals and outputs the fifth comparison result, and a link selector circuit  24   b  which receives the third comparison result and the fourth comparison result as input signals and outputs the sixth comparison result, and the third comparison section  25  is composed of a link selector circuit  25   a  which receives the fifth comparison result and the sixth comparison result as input signals and outputs a result of the comparison of the 16 bits. It is to be noted that, while some other elements may possibly be denoted by like reference symbols to those given above, they have similar or equivalent functions to those described above, and therefore, overlapping description of them is omitted herein. 
   Flows of signals are described with reference to  FIG. 9 . In particular, an input signal A&lt; 0 :  15 &gt; and another input signal B&lt; 0 :  15 &gt; are inputted to the first comparison section  21 . In the first comparison section  21 , the 4-bit magnitude comparison circuit (ICMP 4 )  21   a  performs magnitude comparison discrimination between the bits A&lt; 0 :  3 &gt; and B&lt; 0 :  3 &gt; and outputs a first comparison result using the four kinds of status signals GE, GT, LE and LT. Similarly, the 4-bit magnitude discrimination circuit  21   b  performs magnitude comparison discrimination between the bits A&lt; 4 :  7 &gt; and B&lt; 4 :  7 &gt; and outputs a second comparison result using the four kinds of status signals GE, GT, LE and LT; the 4-bit magnitude discrimination circuit  21   c  performs magnitude comparison discrimination between the bits A&lt; 8 :  11 &gt; and B&lt; 8 :  11 &gt; and outputs a third comparison result using the four kinds of status signals GE, GT, LE and LT; and the 4-bit magnitude discrimination circuit  21   d  performs magnitude comparison discrimination between the bits A&lt; 12 :  15 &gt; and B&lt; 12 :  15 &gt; and outputs a fourth comparison result using the four kinds of status signals GE, GT, LE and LT. 
   The first comparison result and the second comparison result are inputted to the link selector circuit  24   a , by which magnitude comparison discrimination between the bits A&lt; 0 :  7 &gt; and B&lt; 0 :  7 &gt; is performed, and a result of the comparison of the 8 bits is outputted as a fifth comparison result using the four kinds of status signals. Similarly, the third comparison result and the fourth comparison result are inputted to the link selector circuit  24   b , by which magnitude comparison discrimination between the bits A&lt; 8 :  15 &gt; and B&lt; 8 :  15 &gt; is performed, and a result of the comparison of the 8 bits is outputted as a sixth comparison result using the four kinds of status signals. Then, the third comparison section  25  performs magnitude comparison discrimination between the signals A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt; from the fifth comparison result and the sixth comparison result and outputs a comparison result of the 16 bits using the four kinds of status signals (GE, GT, LE, LT). 
   Since the 16-bit magnitude comparison circuit  20  is constructed without varying the basic constructions of the 4-bit magnitude comparison circuits  21   a ,  21   b ,  21   c  and  21   d  and the link selector circuits  24   a ,  24   b  and  25   a  and besides makes much use of repetitiveness of wiring lines in this manner, it is advantageous in that it can be formed with a simple circuit configuration. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly, and besides it is possible to design a circuit having a high degree of expandability. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Furthermore, since the 4-bit magnitude comparison circuits  21   a ,  21   b ,  21   c  and  21   d  and the link selector circuits  24   a ,  24   b  and  25   a  are formed from cells LGEN and LSEL 2 , respectively, and each of the leaf cells normally produces two kinds of signals of a regular phase signal and an inverted phase signal in the inside thereof as described hereinabove, there is an advantage that the entire circuit operates at a high speed. 
   A magnitude comparison circuit wherein the construction described above is expanded to general n 1  bits is described taking a magnitude comparison circuit wherein n 1 =64 as an example. The symbol n 1  represents 4, 16, 64, 256, . . . , 2 to the m 1 th power (m is an even number equal to or greater than 2). However, the expansion to any number of bits is possible. For example, the expansion to 200 bits is possible if predetermined bits of 256 bits are used.  FIG. 10  is a block diagram showing a construction of an n 1 -bit (n 1 =64) magnitude comparison circuit according to the embodiment of the present invention. Referring to  FIG. 10 , the 64-bit magnitude comparison circuit  26  shown performs magnitude comparison of 64 bits and outputs a result of the comparison using the four kinds of status signals GE, GT, LE and LT. The 64-bit magnitude comparison circuit  26  is composed of a first comparison section  27 , a second comparison section  24 , and a third comparison section  25 . In  FIG. 10 , reference symbol A&lt; 0 :  63 &gt; denotes an input signal of 64 bits and B&lt; 0 :  63 &gt; denotes another input signal of 64 bits, and GT, GE, LE and LT appearing in  FIG. 10  denote output signals. The same references may also be used as the names of signal terminals. 
   The first comparison section  27  receives a 64-bit input signal A&lt; 0 :  63 &gt; and another 64-bit input signal B&lt; 0 :  63 &gt;, performs magnitude comparison between the 16 bits A&lt; 0 :  15 &gt; of the former input signal and the 16 bits B&lt; 0 :  15 &gt; of the latter input signal, and further performs magnitude comparison between the 16 bits A&lt; 16 :  31 &gt; and B&lt; 16 :  31 &gt;, A&lt; 32 :  47 &gt; and B&lt; 32 :  47 &gt;, and A&lt; 48 :  63 &gt; and B&lt; 48 :  63 &gt;, and outputs a result of the comparison of the 64 bits as a p 1 th comparison result, a p 2 th comparison result, a p 3 th comparison result and a p 4 th comparison result using the four kinds of status signals. The first comparison section  27  is composed of four 16-bit magnitude comparison circuits  27   a ,  27   b ,  27   c  and  27   d , each of which is formed from a 16-bit magnitude comparison circuit  20  (refer to  FIG. 8  or  9 ) described hereinabove. 
   The second comparison section  24  performs magnitude comparison between the bits A&lt; 0 :  31 &gt; whose bit number is twice that of the 16 bits A&lt; 0 :  15 &gt; of the input signal and the bits B&lt; 0 :  31 &gt; whose bit number is twice that of the 16 bits B&lt; 0 :  15 &gt; of the input signal from the p 1 th comparison result and the p 2 th comparison result and outputs a result of the comparison of the 32 bits as a p 5 th comparison result using the four kinds of status signals. Further, the second comparison section  24  performs magnitude comparison between the bits A&lt; 32 :  63 &gt; whose bit number is twice that of the 16 bits A&lt; 32 :  47 &gt; of the input signal and the bits B&lt; 32 :  63 &gt; whose bit number is twice that of the 16 bits B&lt; 32 :  47 &gt; of the input signal from the p 3 th comparison result and the p 4 th comparison result and outputs a result of the comparison of the 32 bits as a p 6 th comparison result using the four kinds of status signals. Also those functions are exhibited by the link selector circuits  24   a  and  24   b  described hereinabove. 
   Further, the third comparison section  25  performs magnitude comparison between the 64 bits of the input signal A&lt; 0 :  63 &gt; and the 64 bits of the input signal B&lt; 0 :  63 &gt; from the p 5 th comparison result and the p 6 th comparison result and outputs a comparison result of the 64 bits using the four kinds of status signals. Also this function is exhibited by the link selector circuit  25   a  described hereinabove. 
   Consequently, the 64 bits of the input signal A&lt; 0 :  63 &gt; and the 64 bits of the input signal B&lt; 0 :  63 &gt; are branched into four groups by the first comparison section  27 , and magnitude comparison discrimination is performed for the four branched 16-bit signals by the 16-bit magnitude comparison circuits  27   a ,  27   b ,  27   c  and  27   d . Consequently, a p 1 th comparison result, a p 2 th comparison result, a p 3 th comparison result and a p 4 th comparison result are outputted using the four kinds of status signals from the 16-bit magnitude comparison circuits  27   a ,  27   b ,  27   c  and  27   d , respectively. The p 1 th comparison result and the p 2 th comparison result are inputted to the link selector circuit  24   a , by which magnitude comparison discrimination between the bits A&lt; 0 :  31 &gt; and B&lt; 0 :  31 &gt; is performed, and a comparison result of the 32 bits is outputted as a p 5 th comparison result using the four kinds of status signals from the link selector circuit  24   a . Similarly, the p 3 th comparison result and the p 4 th comparison result are inputted to the link selector circuit  24   b , by which magnitude comparison discrimination between the bits A&lt; 32 :  63 &gt; and B&lt; 32 :  63 &gt; is performed, and a comparison result of the 32 bits is outputted as a p 6 th comparison result using the four kinds of status signals from the link selector circuit  24   b . Further, the third comparison section  25  performs magnitude comparison discrimination between the bits A&lt; 0 :  63 &gt; and B&lt; 0 :  63 &gt; from the p 5 th comparison result and the p 6 th comparison result and outputs a comparison result of the 64 bits using the four kinds of status signals (GE, GT, LE and LT). 
   Since generally a magnitude comparison circuit for n 1  bits is formed from 16-bit magnitude comparison circuits (ICMP 16 ) and cells LSEL 2  in this manner, it is simple in circuit configuration and repetitiveness of wiring lines can be utilized well. Further, a circuit configuration having a high degree of expandability can be produced and magnitude comparison circuits for different bit widths can be designed simply and efficiently. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly, and besides it is possible to design a circuit having a high degree of expandability. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Further, since the same leaf cells can be used, the magnitude comparison circuit is advantageous in that it contributes to augmentation of the yield and so forth upon production. Furthermore, since each of the leaf cells normally produces two kinds of signals of a regular phase signal and an inverted phase signal in the inside thereof as described hereinabove, there is an advantage that the entire circuit operates at a high speed. 
   Subsequently, an adder circuit as a functional circuit which uses the three kinds of leaf cells described above is described.  FIG. 11  is a block diagram showing a construction of a 4-bit full adder circuit according to the embodiment of the present invention. The 4-bit full adder circuit is different from the 4-bit magnitude comparison circuit shown in  FIG. 5  in that it additionally includes a circuit in the block construction in the third stage. It is to be noted here that, in  FIG. 11 , reference symbol A&lt; 0 :  3 &gt; denotes an input terminal or an input signal, and XB&lt; 0 :  3 &gt; denotes another input terminal or an inverted signal of another input signal. 
   Referring to  FIG. 11 , the 4-bit full adder circuit (IADD 4 )  30  shown is a CMOS logic circuit which performs full addition arithmetic of 4 bits and outputs the four kinds of status signals GE, GT, LE and LT. The 4-bit full adder circuit  30  includes a first carry generation section  31 , a second carry generation section  32 , a third carry generation section  33 , and a fourth carry generation section  34 . 
   The first carry generation section  31  receives a 4-bit input signal A&lt; 0 :  3 &gt; and an inverted signal XB&lt; 0 : 3 &gt; of another 4-bit input signal, performs magnitude comparison for each one bit and outputs results of the magnitude comparison of the individual bits as a first carry, a second carry, a third carry and a fourth carry using a plurality of status signals. The first carry generation section  31  includes four magnitude discrimination circuits  31   a ,  31   b ,  31   c  and  31   d , each of which is formed from a cell LGEN described hereinabove. 
     FIG. 12  is a diagrammatic view illustrating logical values of the cell LGEN when notice is take of the cell LGEN as a full adder circuit of 1 bit. Since a carry is outputted only when the input signals are (A, B)=(1, 1), arithmetic wherein 1 is outputted only with the combination just described and 0 is outputted with any other combination is required. Therefore, the GT signal which exhibits the same logical values is used. 
   Referring back to  FIG. 11 , the second carry generation section  32  outputs logical AND information of the first carry and the second carry as a fifth carry using the four kinds of status signals and outputs logical AND information of the third carry and the fourth carry as a sixth carry using the four kinds of status signals. The second carry generation section  32  is composed of four selector circuits  32   a ,  32   b ,  32   c  and  32   d , each of which is formed from a cell LSEL 2  described hereinabove. It is to be noted that also each of the four selector circuits  32   a ,  32   b ,  32   c  and  32   d  has, although not shown in  FIG. 11 , input terminals S 1 , XS 1  and A 1  and input terminals S 2 , XS 2  and A 2  and has output terminals X 1  and X 2  similarly to those shown in  FIG. 5 . The two selector circuits  32   a  and  32   b  cooperate to perform logical ANDing of full addition arithmetic results of the two high order bits of the first input signal and the second input signal from the first carry and the second carry and outputs a result of the logical ANDing as a fifth carry. Similarly, the two selector circuits  32   c  and  32   d  cooperate to perform logical ANDing of full addition arithmetic results of the two low order bits of the first input signal and the second input signal from the third carry and the fourth carry and outputs a result of the logical ANDing as a sixth carry. 
   The third carry generation section  33  outputs logical AND information of the first carry, second carry, third carry and fourth carry as a seventh carry from the fifth carry and the sixth carry using the four kinds of status signals, and outputs logical AND information of the second carry, third carry and fourth carry as an eighth carry from the second carry and the sixth carry using the four kinds of status signals. The third carry generation section  33  is composed of four selector circuits  33   a ,  33   b ,  33   c  and  33   d , each of which is formed from a cell LSEL 2  described hereinabove. The logical AND information signifies a logically ANDed value or values. Then, the 4-bit full adder circuit  30  outputs the fourth carry, sixth carry, seventh carry and eighth carry using the four kinds of status signals GE&lt; 0 :  3 &gt;, GT&lt; 0 :  3 &gt;, LE&lt; 0 :  3 &gt; and LT&lt; 0 :  3 &gt;. 
   If the 4-bit full adder circuit  30  of  FIG. 11  is re-arranged using the link selector circuit  6  shown in  FIG. 6 , then such a circuit configuration as shown in  FIG. 13  is obtained.  FIG. 13  is a block diagram showing a construction of a 4-bit full adder circuit (IADD 4 ) according to the embodiment of the present invention. A second carry generation section  35  shown in  FIG. 13  corresponds to the second carry generation section  32  shown in  FIG. 11 , and a third carry generation section  36  corresponds to the third carry generation section  33  shown in  FIG. 11 . Referring to  FIG. 13 , the second carry generation section  35  is composed of a link selector circuit  35   a  which receives the first carry and the second carry as input signals and outputs the fifth carry, and another link selector circuit  35   b  which receives the third carry and the fourth carry as input signals and outputs the sixth carry, and the third carry generation section  36  is composed of a link selector circuit  36   a  which receives the fifth carry and the sixth carry as input signals and outputs the seventy carry, and another link selector circuit  36   b  which receives the second carry and the sixth carry as input signals and outputs the eighth carry. It is to be noted that, while some other elements may possibly be denoted by like reference symbols to those given above, they have similar or equivalent functions to those described above, and therefore, overlapping description of them is omitted herein. 
   Flows of signals when full addition arithmetic of an input signal A&lt; 0 : 3 &gt; and another input signal B&lt; 0 : 3 &gt; is performed are described below with reference to  FIG. 13 . In particular, an input signal A&lt; 0 : 3 &gt; and an inverted signal XB&lt; 0 : 3 &gt; of another input signal are inputted to the first carry generation section  31 . In the first carry generation section  31 , the magnitude comparison discrimination circuit  31   a  performs magnitude comparison discrimination between the bits A&lt; 0 &gt; and XB&lt; 0 &gt; to perform full addition arithmetic of the bits A&lt; 0 &gt; and B&lt; 0 &gt;. Information of whether or not a carry appears then is outputted as a first carry using the four kinds of status signals GE, GT, LE and LT. Similarly, the magnitude comparison discrimination circuit  31   b  performs magnitude comparison discrimination of the bits A&lt; 1 &gt; and XB&lt; 1 &gt; to perform full addition arithmetic of the bits A&lt; 1 &gt; and B&lt; 1 &gt;, and outputs presence or absence of a carry then as a second carry using the four kinds of status signals GE. GT, LE and LT. The magnitude comparison discrimination circuit  31   c  performs magnitude comparison discrimination of the bits A&lt; 2 &gt; and XB&lt; 2 &gt; to perform full addition arithmetic of the bits A&lt; 2 &gt; and B&lt; 2 &gt;, and outputs presence or absence of a carry then as a third carry using the four kinds of status signals GE. GT, LE and LT, and also the magnitude comparison discrimination circuit  31   d  performs magnitude comparison discrimination of the bits A&lt; 3 &gt; and XB&lt; 3 &gt; to perform full addition arithmetic of the bits A&lt; 3 &gt; and B&lt; 3 &gt;, and outputs presence or absence of a carry then as a fourth carry using the four kinds of status signals GE. GT, LE and LT. 
   The first carry and the second carry are inputted to the link selector circuit  35   a , by which the carry from the bits A&lt; 0 &gt; and B&lt; 0 &gt; and the carry from the bits A&lt; 1 &gt; and B&lt; 1 &gt; are logically ANDed, and a logical AND result then is outputted as a fifth carry using the four kinds of status signals. Similarly, the third carry and the fourth carry are inputted to the link selector circuit  35   b , by which the carry from the bits A&lt; 2 &gt; and B&lt; 2 &gt; and the carry from the bits A&lt; 3 &gt; and B&lt; 3 &gt; are logically ANDed, and a logical AND result then is outputted as a sixth carry using the four kinds of status signals. 
   Further, the link selector circuit  36   a  in the third carry generation section  36  logically ANDs all of the four carries including the carry between the bits A&lt; 0 &gt; and B&lt; 0 &gt;, the carry between the bits A&lt; 1 &gt; and B&lt; 1 &gt;, the carry between the bits A&lt; 2 &gt; and B&lt; 2 &gt; and the carry between the bits A&lt; 3 &gt; and B&lt; 3 &gt; using the fifth carry and the sixth carry, and outputs a logical AND result then as a seventh carry using a status signal of 4 bits. Also, the link selector circuit  36   b  in the third carry generation section  36  logically ANDs the three carries including the carry between the bits A&lt; 1 &gt; and B&lt; 1 &gt;, the carry between the bits A&lt; 2 &gt; and B&lt; 2 &gt; and the carry between the bits A&lt; 3 &gt; and B&lt; 3 &gt; using the second carry and the sixth carry, and outputs a logical AND result then as an eighth carry using a status signal of 4 bits. 
   Then, the logical AND result of 4 bits of the carry between the bits A&lt; 0 &gt; and B&lt; 0 &gt;, the carry between the bits A&lt; 1 &gt; and B&lt; 1 &gt;, the carry between the bits A&lt; 2 &gt; and B&lt; 2 &gt; and the carry between the bits A&lt; 3 &gt; and B&lt; 3 &gt; is outputted to the terminal GT&lt; 0 &gt;. The logical AND result of 3 bits of the carry between the bits A&lt; 1 &gt; and B&lt; 1 &gt;, the carry between the bits A&lt; 2 &gt; and B&lt; 2 &gt; and the carry between the bits A&lt; 3 &gt; and B&lt; 3 &gt; is outputted to the terminal GT&lt; 1 &gt;. The logical AND result of 2 bits of the carry between the bits A&lt; 2 &gt; and B&lt; 2 &gt; and the carry between the bits A&lt; 3 &gt; and B&lt; 3 &gt; is outputted to the terminal GT&lt; 2 &gt;. The carry between the bits A&lt; 3 &gt; and B&lt; 3 &gt; is outputted to the terminal GT&lt; 3 &gt;. 
   In this manner, the 4-bit full adder circuit (IADD 4 )  30  merges logical AND results of the input signal A&lt; 0 :  3 &gt; and the inverted signal B&lt; 0 :  3 &gt; successively in the successive stages and outputs a full addition arithmetic result of all of the 4 bits from the final stage. 
   Since the 4-bit full adder circuit  30  is formed from cells LGEN and LSEL 2  and two kinds of signals of a regular phase signal and an inverted phase signal are normally produced and used in the inside of each of the cells of the 4-bit full adder circuit  30  as described hereinabove, there is an advantage that the 4-bit full adder circuit  30  operates at a high speed. Further, since such cells LGEN and LSEL 2  as described above are used, the 4-bit full adder circuit  30  is simple in circuit configuration. 
   Subsequently, a circuit which performs full addition arithmetic of 16 bits is described with reference to  FIGS. 14 and 15 .  FIG. 14  is a block diagram showing a construction of a 16-bit full addition arithmetic circuit according to the embodiment of the present invention. Referring to  FIG. 14 , the 16-bit full addition arithmetic circuit (IADD 16 )  37  shown is a CMOS logic circuit which performs full addition arithmetic of 16 bits and is composed of a half addition arithmetic section  38 , a first arithmetic section  39 , a second arithmetic section  40 , a third arithmetic section  41  and a fourth arithmetic section  42 . It is to be noted that reference symbol A&lt; 0 :  14 &gt; denotes an input terminal or an input signal, and XB&lt; 0 :  16 &gt; denotes another input terminal or an inverted signal of another input signal. 
   The half addition arithmetic section  38  receives a first input signal A&lt; 0 :  15 &gt; of 16 bits and an inverted signal XB&lt; 0 :  15 &gt; of a second input signal of 16 bits and performs half addition arithmetic of the signals A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt;. The half addition arithmetic section  38  includes a first inversion section  38   a , a second inversion section  38   b  and a half addition processing section  38   c . The first inversion section  38   a  outputs an inverted logic value of the signal A&lt; 0 :  15 &gt; and is formed from an ordinary inverter. The second inversion section  38   b  outputs a signal B&lt; 0 :  15 &gt; inverted from the inverted signal XB&lt; 0 :  15 &gt; and is formed from an ordinary inverter. The half addition processing section  38   c  performs half addition arithmetic between the output XA&lt; 0 :  15 &gt; of the first inversion section  38   a  and the output B&lt; 0 :  15 &gt; of the second inversion section  38   b  and is formed from a cell LEOR described hereinabove. 
   The first arithmetic section  39  performs full addition arithmetic of the signals A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt; separately for each four bits and outputs full addition arithmetic results for the four bits as a first carry, a second carry, a third carry and a fourth carry using the four kinds of status signals. The first arithmetic section  39  is composed of four 4-bit full adder circuits  39   a ,  39   b ,  39   c  and  39   d , each of which is formed from a 4-bit full adder circuit (IADD 4 ) described hereinabove. The second arithmetic section  40  outputs logical AND information of the first carry and the second carry as a fifth carry using the four kinds of status signals and outputs logical AND information of the third carry and the fourth carry as a sixth carry using the four kinds of status signals. The third arithmetic section  41  outputs logical AND information of all of the 16 bits at least from the fifth carry and the sixth carry as a seventh carry using the four kinds of status signals. 
   It is to be noted that each of the selector circuits (LSEL 2 ) in the second arithmetic section  40  and the third arithmetic section  41  has input terminals S 1 , XS 1  and  41  and input terminals S 2 , XS 2  and A 2 , and output terminals X 1  and X 2  similarly to those shown in  FIG. 5 . 
   The fourth arithmetic section  42  performs logical exclusive ORing of the output of the half addition arithmetic section  38  and the seventh carry and outputs a full addition arithmetic result. The fourth arithmetic section  42  includes an inversion section  42   a  and full addition arithmetic outputting sections  42   b  and  42   c . The inversion section  42   a  outputs an inverted logical value of an input signal and is formed from an inverter which, for example, may be selected from within a standard library equipped in a circuit designing tool. The full addition arithmetic outputting section  42   b  performs full addition arithmetic between the output of the inversion section  42   a  and the output of the third arithmetic section  41 . The full addition arithmetic outputting section  42   b  is formed from a cell LEOR described hereinabove. The full addition arithmetic outputting section  42   c  performs full addition arithmetic between the output of the half addition arithmetic section  38  and the output of the inversion section  42   a.    
   If the first arithmetic section  39 , second arithmetic section  40  and third arithmetic section  41  shown in  FIG. 14  are re-arranged using the link selector circuit  6  shown in  FIG. 6 , then such a circuit configuration as shown in  FIG. 15  is obtained.  FIG. 15  is a block diagram showing a construction of the first arithmetic section  39 , second arithmetic section  43  and third arithmetic section  44  of a 16-bit full adder circuit (IADD 16 ) according to the embodiment of the present invention. A second arithmetic section  43  shown in  FIG. 15  corresponds to the second arithmetic section  40  shown in  FIG. 14 , and a third arithmetic section  44  corresponds to the third arithmetic section  41  shown in  FIG. 14 . Referring to  FIG. 15 , the second arithmetic section  43  is composed of a link selector circuit  43   a  which receives the first carry and the second carry as input signals and outputs the fifth carry, and another link selector circuit  43   b  which receives the third carry and the fourth carry as input signals and outputs the sixth carry, and the third arithmetic section  44  is composed of a link selector circuit  44   a  which receives the fifth carry and the sixth carry as input signals and outputs the seventy carry, and a link selector circuit  44   b  which receives the second carry and the sixth carry as input signals and outputs the eighth carry. It is to be noted that, while some other elements may possibly be denoted by like reference symbols to those given above, they have similar or equivalent functions to those described above, and therefore, overlapping description of them is omitted herein. 
   Flows of signals are described with reference to  FIG. 14 . In particular, a first input signal A&lt; 0 :  15 &gt; and an inverted signal XB&lt; 0 :  15 &gt; of a second input signal B&lt; 0 :  15 &gt; are inputted to the first arithmetic section  39 . In the first arithmetic section  39 , the 4-bit full adder circuit  39   a  performs full addition of the bits A&lt; 0 :  3 &gt; and B&lt; 0 :  3 &gt; and outputs a signal including logical AND information at least of the bits A&lt; 0 &gt;–B&lt; 0 &gt; as a first carry (refer to an alternate long and short dash line *A in  FIG. 14 ). The 4-bit full adder circuit  39   b  performs full addition of the bits A&lt; 4 :  7 &gt; and B&lt; 4 :  7 &gt; and outputs a signal including logical AND information at least of the bits A&lt; 4 &gt;–B&lt; 4 &gt; as a second carry. The 4-bit full adder circuit  39   c  performs full addition of the bits A&lt; 8 :  11 &gt; and B&lt; 8 :  11 &gt; and outputs a signal including logical AND information at least of the bits A&lt; 8 &gt;–B&lt; 8 &gt; as a third carry. The 4-bit full adder circuit  39   d  performs full addition of the bits A&lt; 12 :  15 &gt; and B&lt; 12 :  15 &gt; and outputs a signal including logical AND information at least of the bits A&lt; 12 &gt;–B&lt; 12 &gt; as a fourth carry. 
   The first carry and the second carry are inputted to the second arithmetic section  40 , by which the carry from the bits A&lt; 0 :  3 &gt; and B&lt; 0 :  3 &gt; and the carry from the bits A&lt; 4 :  7 &gt; and B&lt; 4 :  7 &gt; are logically ANDed, and a logical AND result then is outputted as a fifth carry which has the carry information from the bits A&lt; 0 :  7 &gt; and B&lt; 0 :  7 &gt; using the four kinds of status signals (refer to an alternate long and short dash line *B in  FIG. 14 ). Similarly, the third carry and the fourth carry are inputted to the second arithmetic section  40 , by which the carry from the bits A&lt; 8 :  11 &gt; and B&lt; 8 :  11 &gt; and the carry from the bits A&lt; 12 :  15 &gt; and B&lt; 12 :  15 &gt; are logically ANDed, and a logical AND result then is outputted as a sixth carry which has the carry information from the bits A&lt; 8 :  15 &gt; and B&lt; 8 :  15 &gt; using the four kinds of status signals. Further, the third arithmetic section  41  produces from the fifth carry and the sixth carry and outputs a seventh carry which has the carry information from the bits A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt; (refer to an alternate long and short dash line *C in  FIG. 14 ). 
   Meanwhile, the first input signal A&lt; 0 :  15 &gt; and the inverted signal XB&lt; 0 :  15 &gt; of the second input signal B&lt; 0 :  15 &gt; are inputted to the half addition arithmetic section  38 . In the half addition arithmetic section  38 , the half addition processing section  38   c  performs half addition arithmetic of the signals A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt;. The fourth arithmetic section  42  performs logical exclusive ORing of the half addition output of the half addition processing section  38   c  and the seventh carry from the third arithmetic section  41  and outputs a full addition arithmetic result (refer to an alternate long and short dash line *D in  FIG. 14 ). 
   In this manner, since the 16-bit full adder circuit  37  is formed from 4-bit full adder circuits, cells LSEL 2  and cells LEOR, it is advantageous in that it is simple in circuit configuration utilizing repetitiveness of wiring lines much. Further, the 16-bit full adder circuit  37  can be formed so as to receive a minimized number of input signals and so as to cope with various hierarchies from comparison of 1 bit to comparison of 16 bits. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly, and besides it is possible to design a circuit having a high degree of expandability. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. In particular, the 16-bit full addition arithmetic circuit  37  requires only tuning of parts limited to the several kinds and significantly reduces the man-hours for arrangement or layout transistors (graph patterning) upon development. Further, since the same leaf cells can be used, the 16-bit full addition arithmetic circuit  37  is advantageous in that it contributes to augmentation of the yield and so forth upon production. Furthermore, since two kinds of signals of a regular phase signal and an inverted phase signal are normally produced and used in the inside of each of the leaf cells as described hereinabove, there is an advantage that the entire circuit operates at a high speed. 
   A full adder circuit wherein the construction described above is expanded to that for general n 2  bits is described taking a full adder circuit wherein n 2 =64 as an example. The symbol n 2  represents 4, 16, 64, 256, . . . , 2 to the m 2 th power (m 2  is an even number equal to or greater than 2). However, the expansion to any number of bits is possible. For example, the expansion to 200 bits is possible if predetermined bits of 256 bits are used.  FIG. 16  is a block diagram showing a construction of an n 2 -bit (n 2 =64) full adder circuit according to the embodiment of the present invention. Referring to  FIG. 16 , the 64-bit full adder circuit  45  shown is a CMOS logic circuit which performs full addition arithmetic of 64 bits and is composed of a half addition arithmetic section  46 , a first arithmetic section  47 , a second arithmetic section  48 , a third arithmetic section  49  and a fourth arithmetic section  50 . In  FIG. 16 , reference symbol A&lt; 0 :  63 &gt; denotes an input terminal or an input signal and B&lt; 0 :  63 &gt; denotes an inverted signal of another input terminal or another input signal. 
   The half addition arithmetic section  46  receives a first input signal A&lt; 0 :  63 &gt; of 64 bits and an inverted signal XB&lt; 0 :  63 &gt; of a second input signal of 64 bits and performs half addition arithmetic of the signals A&lt; 0 :  63 &gt; and B&lt; 0 :  63 &gt;. 
   The first arithmetic section  47  performs full addition arithmetic of the signals A&lt; 0 :  63 &gt; and B&lt; 0 :  63 &gt; separately for each 16 bits and outputs full addition arithmetic results as a q 1 th carry, a q 2 th carry, a q 3 th carry and a q 4 th carry using four kinds of status signals. The first arithmetic section  47  is composed of four 16-bit full adder circuits  47   a ,  47   b ,  47   c  and  47   d . The second arithmetic section  48  outputs logical AND information of the q 1 th carry and the q 2 th carry as a q 5 th carry using the four kinds of status signals and outputs logical AND information of the q 3 th carry and the q 4 th carry as a q 6 th carry using the four kinds of status signals. The second arithmetic section  48  is composed of link selector circuits  48   a  and  48   b . The third arithmetic section  49  produces at least from the q 5 th carry and the q 6 th carry and outputs logical AND information of the carries from all of the 64 bits as a q 7 th using the four kinds of status signals. The fourth arithmetic section  50  performs logical exclusive ORing of the output of the half addition arithmetic section  46  and the q 7 th carry and outputs a full addition arithmetic result. The fourth arithmetic section  50  is composed of a pair of link selector circuits  49   a  and  49   b.    
   Flows of signals are described with reference to  FIG. 16 . In particular, a first input signal A&lt; 0 :  63 &gt; and an inverted signal XB&lt; 0 :  63 &gt; of a second input signal B&lt; 0 :  63 &gt; are inputted to the first arithmetic section  47 . In the first arithmetic section  47 , the 16-bit full adder circuits  47   a ,  47   b ,  47   c  and  47   d  perform full addition separately for each 16 bits and output resulting carries as a q 1 th carry, a q 2 th carry, a q 3 th carry and a q 4 th carry of 16 bits, respectively. The q 1 th carry and the q 2 th carry are inputted to the second arithmetic section  48 , by which the carry from the bits A&lt; 0 :  15 &gt; and B&lt; 0 :  15 &gt; and the carry from the bits &lt; 16 :  31 &gt; and B&lt; 16 :  31 &gt; are logically ANDed, and a result of the logical ANDing is outputted as a q 5 th carry of 16 bits. Further, the q 3 th carry and the q 4 th carry are inputted to the second arithmetic section  48 , by which the carry from the bits A&lt; 32 :  47 &gt; and B&lt; 32 :  47 &gt; and the carry from the bits A&lt; 48 :  63 &gt; and B&lt; 48 :  63 &gt; are logically ANDed, and a result of the logical ANDing is outputted as a q 6 th carry of 16 bits. Furthermore, the third arithmetic section  49  produces from the q 5 th carry and the q 6 th carry and outputs a q 7 th carry having at least the carry information of the bits A&lt; 0 :  63 &gt; and B&lt; 0 :  63 &gt;. 
   Meanwhile, the first input signal A&lt; 0 :  63 &gt; and the inverted signal XB&lt; 0 :  63 &gt; of the second input signal B&lt; 0 :  63 &gt; are inputted to the half addition arithmetic section  46 , by which half addition arithmetic of the bits A&lt; 0 :  63 &gt; and B&lt; 0 :  63 &gt; is performed, and a result of the half addition arithmetic is outputted from the half addition arithmetic section  46 . The fourth arithmetic section  50  performs logical exclusive ORing of the half addition output of the half addition arithmetic section  46  and the q 7 th carry from the third arithmetic section  49  and outputs a full addition arithmetic result. 
   In this manner, since the n 2 -bit full adder circuit is formed from 16-bit full adder circuits (IADD 16 ), cells LSEL 2  and cells LEOR, adder circuits and magnitude comparison circuits of different bit widths can be obtained simply and efficiently and besides circuits which operate at a high speed can be designed. Further, since the same leaf cells are used, the yield and so forth upon production are improved. Furthermore, since the number of kinds of leaf cells can be suppressed, the development man-hours for leaf cells is reduced significantly, and besides, since the circuit scale is reduced as a whole, a layout can be designed with increased repetitiveness of wiring lines, and consequently, the man-hours can be reduced remarkably. 
   Subsequently, an increment circuit to which the present invention is applied is described. The increment circuit is used principally as a command register in a processor or the like and may have, for example, a 64-bit length. Further, the increment circuit counts up while the increment thereupon varies to 2, 4, 8, 16 and so forth and is different in this regard from a counter circuit formed from a register or the like and having a constant increment of 1. The increment circuit is composed of a carry generation circuit and a full adder circuit. As details of the increment circuit, leaf cells which form the carry generation circuit are first described with reference to  FIGS. 17 to 21 , and then a carry generation circuit is described with reference to  FIGS. 22 and 23 , whereafter an actual increment circuit is described with reference to  FIGS. 24 and 25 . 
     FIG. 17  is a block diagram showing a construction of a fourth leaf cell according to the embodiment of the present invention. Referring to  FIG. 17 , the cell A 001  shown is a CMOS logic circuit for implementing the logic described below and includes a first inversion section  4   a , a second inversion section  4   b , a first outputting section  4   c  and a fourth outputting section  4   d . The cell A 001  shown in  FIG. 17  has input terminals A 1 , S, XS and A 2 . A first signal of 2 bits A&lt; 0 :  1 &gt; and a second signal of 2 bits XA&lt; 0 :  1 &gt; are inputted to the cell A 001 . 
   The first inversion section  4   a  inverts the first input signal A&lt; 0 &gt; and outputs the inverted signal. The second inversion section  4   b  inverts an inverted signal XA&lt; 0 &gt; of the first input signal and outputs the inverted signal. The first outputting section  4   c  performs NANDing arithmetic of the output of the first inversion section  4   a  and the second input signal and outputs a resulting signal. The fourth outputting section  4   d  performs NANDing arithmetic of the output of the second inversion section  4   b  and an inverted signal of the second input signal and outputs a resulting signal. The first outputting section  4   c  and the fourth outputting section  4   d  are changed over with the second input signal A&lt; 1 &gt; and the inverted signal XA&lt; 1 &gt; of the second input signal, respectively. Outputs of the fourth outputting section  4   d  and the first outputting section  4   c  of the cell A 001  are connected output terminals X 1  and X 2  of the cell A 001 , respectively. 
     FIG. 18(   a ) illustrates logical values at the input side terminals S, XS and A 1  and the output side terminal X 1  of the cell A 001 .  FIG. 18(   b ) illustrates logical values at the input side terminals S, XS and A 2  and the output side terminal X 2  of the cell A 001 . It is inhibited that the same logical value be inputted to the terminal Sand the terminal XS of the cell A 001 . Meanwhile,  FIG. 19  illustrates logical values of the cell A 001 . More specifically,  FIG. 19  illustrates logical values when the bits A&lt; 0 &gt;, XA&lt; 0 &gt;, A&lt; 1 &gt; and XA&lt; 1 &gt; are applied to the input terminals A 2 , A 1 , XS and S of the cell A 001 , respectively. As seen from  FIG. 19 , an ANDing arithmetic result of the bits A&lt; 0 &gt; and A&lt; 1 &gt; is outputted from the output terminal X 1 . Similarly, a NANDing arithmetic result of the bits A&lt; 0 &gt; and A&lt; 1 &gt; is outputted from the output terminal X 2 . 
   Consequently, if input signals are applied appropriately to the cell A 001 , then the cell A 001  can output an AND value and an inverted value of the AND value of the bits A&lt; 0 &gt; and A&lt; 1 &gt; based on positive logic and negative logic values of the 2 bits A&lt; 0 &gt; and A&lt; 1 &gt; inputted thereto. Further, since the double inverters of the cell A 001  are formed from CMOS logics in this manner, the cell A 001  operates at a high speed, and besides, the isolation between a circuit on the output side and another circuit preceding to the cell A 001  is strengthened. Furthermore, since the necessity for provision of an inverter circuit in a circuit preceding to the cell A 001  is eliminated, there is an advantage that the burden on the circuit in the preceding stage can be reduced and the circuit configuration can be simplified. 
     FIG. 20  is a block diagram showing a construction of a fifth leaf cell according to the embodiment of the present invention. Referring to  FIG. 20 , the cell A 002  shown is a CMOS logic circuit for implementing the logic described below and includes a first switching section  5   a , a second switching section  5   b  and a transmission section  5   c . It is to be noted that, although reference symbols XA, S, XS, A, I and XI in  FIG. 20  denote terminals, in the following description, they are sometimes used as signal names. 
   The first switching section  5   a  is provided on the input side of a first inversion section  1   a  in the transmission section  5   c  and can perform changing over of whether or not a first input signal XA is to be passed therethrough in accordance with external control signals I and XI. The first switching section  5   a  is formed from pair transistors. The second switching section  5   b  is provided on the input side of a second inversion section  1   b  in the transmission section  5   c  and can perform changing over of whether or not a second input signal A is to be passed therethrough in accordance with the external control signals I and XI. The second switching section  5   b  is formed from pair transistors. The transmission section  5   c  selectively outputs one of the outputs of the first switching section  5   a  and the second switching section  5   b  in accordance with a logic value which depends upon the externally controllable selection signal S and an inverted signal XS of the selection signal S. The transmission section  5   c  is formed from a cell LEOR described hereinabove. Subsequently, operation of the cell A 002  is described with reference to a logical value table. 
     FIG. 21  is a view illustrating logical values of the cell A 002 . Referring to  FIG. 21 , when the control signals I and XI are I=0 and XI=1, the input signal A is outputted from the output terminal X, but when I=1 and XI=0, a logical exclusive OR value of the input signal A and the terminal S is outputted from the output terminal X. It is to be noted that, also with regard to the cell A 002 , it is inhibited to input the same logic value to the input terminals I and XI, the input terminals A and XA, and the input terminal S and XS similarly as in the cell A 001 . 
   Since the double inverters of the cell A 002  are formed from CMOS logics in this manner, the cell A 002  has an advantage that it operates at a high speed. Further, since the cell A 002  has double inverters, the isolation between a circuit following the transmission section  5   c  and another circuit preceding to the cell A 002  is strengthened. Furthermore, since the necessity for provision of an inverter circuit in a circuit preceding to the cell A 002  is eliminated, there is an advantage that the circuit configuration can be simplified. 
     FIG. 22  is a block diagram showing a construction of a 4-bit carry generation circuit according to the embodiment of the present invention. Referring to  FIG. 22 , the 4-bit carry generation circuit (CARRY 001 )  51  shown is a CMOS logic circuit which receives a 4-bit signal A&lt; 0 :  3 &gt; and an inverted signal XA&lt; 0 : 3 &gt; of the 4-bit signal A&lt; 0 :  3 &gt; as input signals and outputs a carry GE&lt; 0 :  3 &gt; from lower order bits appearing upon incrementing and an inverted value LT&lt; 0 :  3 &gt; of the carry GE&lt; 0 :  3 &gt;. The 4-bit carry generation circuit  51  is composed of a first logical AND generation section  51   a , a second logical AND generation section  51   b , a third logical AND generation section  51   c  and a fourth logical AND generation section  51   d . It is to be noted that reference symbols A&lt; 0 :  3 &gt;, XA&lt; 0 :  3 &gt;, &lt; 0 &gt;, &lt; 1 &gt;, &lt; 2 &gt; and &lt; 3 &gt; denote different signals, and X 1 , X 2 , GE&lt; 0 :  3 &gt; and LT&lt; 0 :  3 &gt; denote different terminals. 
   The first logical AND generation section  51   a  receives the two high order bits A&lt; 0 :  1 &gt; of the signal A&lt; 0 :  3 &gt; and the two high order bits XA&lt; 0 :  1 &gt; of the inverted signal XA&lt; 0 :  3 &gt; as inputs thereto and outputs a first logical AND result (AND value of the bits A&lt; 0 &gt; and A&lt; 1 &gt;) and a first logical AND inversion result (NAND value of the bits A&lt; 0 &gt; and A&lt; 1 &gt;) as logical AND results of the two high order bits of the signal A&lt; 0 :  3 &gt;. This function of the first logical AND generation section  51   a  is exhibited by the cell A 001 . Similarly, the second logical AND generation section  51   b  receives the two low order bits A&lt; 2 :  3 &gt; of the signal A&lt; 0 :  3 &gt; and the two low order bits XA&lt; 2 :  3 &gt; of the inverted signal XA&lt; 0 :  3 &gt; as inputs thereto and outputs a second logical AND result (AND value of the bits A&lt; 2 &gt; and A&lt; 3 &gt;) and a second logical AND inversion result (NAND value of the bits A&lt; 2 &gt; and A&lt; 3 &gt;) as logical AND results of the two low order bits of the signal A&lt; 0 :  3 &gt;. Also this function of the second logical AND generation section  51   b  is exhibited by the cell A 001 . 
   The third logical AND generation section  51   c  receives the first logical AND result and the first logical AND inversion result as well as the second logical AND result and the second logical AND inversion result as inputs thereto and outputs a third logical AND result (AND value of the 4 bits A&lt; 0 &gt; to A&lt; 3 &gt;) and a third logical AND inversion result (NAND value of the 4 bits A&lt; 0 &gt; to A&lt; 3 &gt;) as logical AND results of the 4 bits of the signal A&lt; 0 :  3 &gt;. This function of the third logical AND generation section  51   c  is exhibited by the cell A 001 . The fourth logical AND generation section  51   d  receives the bit A&lt; 1 &gt; and the inverted bit XA&lt; 1 &gt; as well as the third logical AND result and the third logical AND inversion result as inputs thereto and outputs a fourth logical AND result (AND value of the 3 bits A&lt; 1 &gt; to A&lt; 3 &gt;) and a fourth logical AND inversion result (NAND value of the 3 bits A&lt; 1 &gt; to A&lt; 3 &gt;) as logical AND results of the three high order bits of the signal A&lt; 0 :  3 &gt;. This function of the fourth logical AND generation section  51   d  is exhibited by the cell A 001 . The 4-bit carry generation circuit  51  thus outputs the third logical AND result (AND value of the 4 bits A&lt; 0 &gt; to A&lt; 3 &gt;), the fourth logical AND result (AND value of the 3 bits A&lt; 1 &gt; to A&lt; 3 &gt;), the second logical AND result (AND value of the bits A&lt; 2 &gt; and A&lt; 3 &gt;) and the bit A&lt; 3 &gt; as a first gate signal of 4 bits, and outputs the third logical AND inversion result (NAND value of the 4 bits A&lt; 0 &gt; to A&lt; 3 &gt;), the fourth logical AND inversion result (NAND value of the 3 bits A&lt; 1 &gt; to A&lt; 3 &gt;), the second logical AND inversion result (NAND value of the bits A&lt; 2 &gt; and A&lt; 3 &gt;) and the bit XA&lt; 3 &gt; as a second gate signal of 4 bits. 
   Signal flows are described below with reference to  FIG. 22 . The first logical AND generation section  51   a  performs ANDing arithmetic of the bit A&lt; 0 &gt; and the bit A&lt; 1 &gt; and outputs a result of the ANDing arithmetic to the terminal X 1  and further outputs an inverted value of the signal X 1  to the terminal X 2  (refer to the logical value table of  FIG. 19 ). The second logical AND generation section  51   b  outputs an AND value of the bit A&lt; 2 &gt; and the bit A&lt; 3 &gt; to the terminal X 1  and outputs an inverted value of the signal X 1  to the terminal X 2 . Further, the third logical AND generation section  51   c  outputs an AND value of the logic value at the terminal X 1  of the first logical AND generation section  51   a  and the logic value at the terminal X 1  of the second logical AND generation section  51   b  to the terminal X 1 . Consequently, an AND value of the 4 bits A&lt; 0 &gt;, A&lt; 1 &gt;, A&lt; 2 &gt; and A&lt; 3 &gt; is outputted to the terminal X 1 . Simultaneously, an inverted value of the AND value X 1  is outputted to the terminal X 2 . The fourth logical AND generation section  51   d  outputs an AND value of the logic value of the bit A&lt; 1 &gt; and the logic value at the terminal X 1  of the second logical AND generation section  51   b  to the terminal X 1 . Consequently, an AND value of the 3 bits A&lt; 1 &gt;, A&lt; 2 &gt; and A&lt; 3 &gt; is outputted to the terminal X 1 . Thereupon, an inverted value of the AND value X 1  is outputted to the terminal X 2 . Accordingly, the output signal GE&lt; 0 :  3 &gt; and the output signal LT&lt; 0 :  3 &gt; of the 4-bit carry generation circuit  51  exhibit the following logic values. 
   An AND value of all of the 4 bits of the signal A&lt; 0 :  3 &gt; is outputted to the terminal GE&lt; 0 &gt;; an AND value of the 3 bits A&lt; 1 :  3 &gt; is outputted to the terminal GE&lt; 1 &gt;; an AND value of the 2 bits A&lt; 2 :  3 &gt; is outputted to the terminal GE&lt; 2 &gt;; and the value of the bit A&lt; 3 &gt; is outputted to the terminal GE&lt; 3 &gt;. Meanwhile, an inverted value of the AND value of all of the 4 bits of the signal A&lt; 0 :  3 &gt; is outputted to the terminal LT&lt; 0 &gt;; an inverted value of the AND value of the 3 bits A&lt; 1 :  3 &gt; is outputted to the terminal LT&lt; 1 &gt;; an inverted value of the AND value of the 2 bits A&lt; 2 :  3 &gt; is outputted to the terminal LT&lt; 2 &gt;; and an inverted value of the value of the bit A&lt; 3 &gt; is outputted to the terminal LT&lt; 3 &gt;. 
   The 4-bit carry generation circuit  51  having the construction described above thus produces an AND value and a NAND value of the 4-bit signal A&lt; 0 :  3 &gt; at a high speed and outputs the resulting values to the terminals GE&lt; 0 :  3 &gt; and LE&lt; 0 :  3 &gt;, respectively. Accordingly, since a carry (AND value of the bits A&lt; 0 &gt; to A&lt; 3 &gt;) necessary for counting up is delivered at a high speed to the next stage, for example, an increment circuit having a bit length longer than 4 bits can produce a carry, which appears as a result of addition of the four low order bits, at a high speed. Further, by expanding the circuit construction described above, a carry generation circuit of an N-bit length can be constructed. 
     FIG. 23  is a block diagram showing a construction of a 16-bit carry generation circuit according to the embodiment of the present invention. Referring to  FIG. 23 , the 16-bit carry generation circuit (CARRY 002 )  52  shown is a CMOS logic circuit which receives a 16-bit signal A&lt; 0 :  15 &gt; and an inverted signal XA&lt; 0 :  15 &gt; of the signal A&lt; 0 : 15 &gt; and outputs a carry GE&lt; 0 :  15 &gt; from low order bits, which appears as a result of incrementing, and an inverted value LT&lt; 0 :  15 &gt; of the carry GE&lt; 0 :  15 &gt;. The 16-bit carry generation circuit  52  includes a first carry generation section  52   a , a second carry generation section  52   b , a third carry generation section  52   c , and a fourth carry generation section  52   d  as well as a first logical AND generation section  53   a , a second logical AND generation section  53   b , a third logical AND generation section  54   a  and a fourth logical AND generation section  54   b . It is to be noted that reference symbols A&lt; 0 : 15 &gt;, XA&lt; 0 : 15 &gt;, &lt; 0 :  3 &gt;, &lt; 4 :  7 &gt;, &lt; 8 :  11 &gt; and &lt; 12 :  15 &gt; denote signals or terminals. Further, reference symbols A&lt; 0 :  3 &gt;, XA&lt; 0 :  3 &gt;, GE&lt; 0 :  3 &gt; and LT&lt; 0 :  3 &gt; in the CARRY 002 , A 1 , XS, S, A 2 , X 1  and X 2  in the cells A 001  and GE&lt; 0 :  15 &gt; and LT&lt; 0 :  15 &gt; which are outputs of the 16-bit carry generation circuit  52  denote different terminals or signals. 
   The first carry generation section  52   a  receives a first input signal A&lt; 0 :  15 &gt; of 16 bits and an inverted signal XA&lt; 0 :  15 &gt; of the first input signal of 16 bits as inputs thereto and outputs an AND value at least of the bits A&lt; 0 &gt; to A&lt; 3 &gt; and an inverted value (NAND value) of the AND value as a first logical AND result and a first logical AND inversion result, respectively. The second carry generation section  52   b  outputs an AND value at least of the bits A&lt; 4 &gt; to A&lt; 7 &gt; and an inverted value of the AND value as a second logical AND result and a second logical AND inversion result, respectively. The third carry generation section  52   c  outputs an AND value at least of the bits A&lt; 8 &gt; to A&lt; 11 &gt; and an inverted value of the AND value as a third logical AND result and a third logical AND inversion result, respectively. The fourth carry generation section  52   d  outputs an AND value at least of the bits A&lt; 12 &gt; to A&lt; 15 &gt; and an inverted value of the AND value as a fourth logical AND result and a fourth logical AND inversion result, respectively. Each of the first carry generation section  52   a , second carry generation section  52   b , third carry generation section  52   c  and fourth carry generation section  52   d  is formed from a cell CARRY  001  described hereinabove. 
   The first logical AND generation section  53   a  produces from the first logical AND result and the second logical AND result and outputs a fifth logical AND result and a fifth logical AND inversion result as a result of an AND value at least of the bits A&lt; 0 &gt; to A&lt; 7 &gt;. The first logical AND generation section  53   a  is formed from four cells A 001 . The second logical AND generation section  53   b  produces from the third logical AND result and the fourth logical AND result and outputs a sixth logical AND result and a sixth logical AND inversion result as a result of an AND value at least of the bits A&lt; 8 &gt; to A&lt; 15 &gt;. The second logical AND generation section  53   b  is formed from four cells A 001 . The third logical AND generation section  54   a  produces from the fifth logical AND result, the fifth logical AND inversion result, the sixth logical AND result and the sixth logical AND inversion result and outputs a seventh logical AND result and a seventh logical AND inversion result as a result of an AND value at least of the bits A&lt; 0 &gt; to A&lt; 15 &gt;. The third logical AND generation section  54   a  is formed from four cells A 001 . The fourth logical AND generation section  54   b  produces from the second logical AND result, the second logical AND inversion result, the sixth logical AND result and the sixth logical AND inversion result and outputs an eighth logical AND result and an eighth logical AND inversion result as a result of an AND value at least of the bits A&lt; 4 &gt; to A&lt; 15 &gt;. The fourth logical AND generation section  54   b  is formed from four cells A 001 . 
   Thus, the 16-bit carry generation circuit  52  outputs the seventh logical AND result, the eighth logical AND result, the sixth logical AND result and the fourth logical AND result as a first gate signal of 16 bits, and outputs the seventh logical AND inversion result, the eighth logical AND inversion result, the sixth logical AND inversion result and the fourth logical AND result as a second gate signal of 16 bits. 
   Signal flows are described below with reference to  FIG. 23 . The first carry generation section  52   a  outputs an AND value of all of the 4 bits A&lt; 0 :  3 &gt; to the terminal GE&lt; 0 &gt;, outputs an AND value of the 3 bits A&lt; 1 :  3 &gt; to the terminal GE&lt; 1 &gt;, outputs an AND value of the 2 bits A&lt; 2 :  3 &gt; to the terminal GE&lt; 2 &gt;, and outputs the value of the bit A&lt; 3 &gt; to the terminal GE&lt; 3 &gt;. The second carry generation section  52   b  outputs an AND value of all of the 4 bits A&lt; 4 :  7 &gt; to the terminal GE&lt; 0 &gt;, outputs an AND value of the 3 bits A&lt; 5 :  7 &gt; to the terminal GE&lt; 1 &gt;, outputs an AND value of the 2 bits A&lt; 6 :  7 &gt; to the terminal GE&lt; 2 &gt;, and outputs the value of the bit A&lt; 7 &gt; to the terminal GE&lt; 3 &gt;. Similarly, the third carry generation section  52   c  outputs an AND value of all of the 4 bits A&lt; 8 :  11 &gt; to the terminal GE&lt; 0 &gt;, outputs an AND value of the 3 bits A&lt; 9 :  11 &gt; to the terminal GE&lt; 1 &gt;, outputs an AND value of the 2 bits A&lt; 10 :  11 &gt; to the terminal GE&lt; 2 &gt;, and outputs the value of the bit A&lt; 11 &gt; to the terminal GE&lt; 3 &gt;. The fourth carry generation section  52   d  outputs an AND value of all of the 4 bits A&lt; 12 :  15 &gt; to the terminal GE&lt; 0 &gt;, outputs an AND value of the 3 bits A&lt; 13 :  15 &gt; to the terminal GE&lt; 1 &gt;, outputs an AND value of the 2 bits A&lt; 14 :  15 &gt; to the terminal GE&lt; 2 &gt;, and outputs the value of the bit A&lt; 15 &gt; to the terminal GE&lt; 3 &gt;. 
   Further, the first logical AND generation section  53   a  receives the signals GE&lt; 0 &gt; to GE&lt; 3 &gt; of the first carry generation section  52   a  and the signal GE&lt; 4 &gt; from the second carry generation section  52   b  as inputs thereto. The signal GE&lt; 4 &gt; is an AND value of the bits A&lt; 4 &gt; to A&lt; 7 &gt;. Accordingly, the four cells A 001  of the first logical AND generation section  53   a  output four kinds of logical values including an AND value of the bits A&lt; 0 &gt; to A&lt; 7 &gt;, an AND value of the bits A&lt; 1 &gt; to A&lt; 7 &gt;, an AND value of the bits A&lt; 2 &gt; to A&lt; 7 &gt; and an AND value of the bits A&lt; 3 &gt; to A&lt; 7 &gt; to the output terminals X 1 . Similarly, the second logical AND generation section  53   b  receives the signals GE&lt; 0 &gt; to GE&lt; 3 &gt; of the third carry generation section  52   c  and the signal GE&lt; 12 &gt; from the fourth carry generation section  52   d  as inputs thereto. The signal GE&lt; 12 &gt; is an AND value of the bits A&lt; 12 &gt; to A&lt; 15 &gt;. Accordingly, the four cells A 001  of the second logical AND generation section  53   b  output four kinds of logical values including an AND value of the bits A&lt; 8 &gt; to A&lt; 15 &gt;, an AND value of the bits A&lt; 9 &gt; to A&lt; 15 &gt;, an AND value of the bits A&lt; 10 &gt; to A&lt; 15 &gt; and an AND value of the bits A&lt; 11 &gt; to A&lt; 15 &gt; to the output terminals X 1 . 
   Further, the third logical AND generation section  54   a  receives an AND value of the bits A&lt; 0 &gt; to A&lt; 7 &gt; at the terminal A 2  thereof and receives the signal GE&lt; 8 &gt; at the terminal XS thereof. The signal GE&lt; 8 &gt; is an AND value of the bits A&lt; 8 &gt; to A&lt; 15 &gt;. Accordingly, the four cells A 001  of the third logical AND generation section  54   a  output four kinds of logical values including an AND value of the bits A&lt; 0 &gt; to A&lt; 15 &gt;, an AND value of the bits A&lt; 1 &gt; to A&lt; 15 &gt;, an AND value of the bits A&lt; 2 &gt; to A&lt; 15 &gt; and an AND value of the bits A&lt; 3 &gt; to A&lt; 15 &gt; to the output terminals X 1 . The fourth logical AND generation section  54   b  receives an AND value of the bits A&lt; 4 &gt; to A&lt; 7 &gt; at the terminal A 2  thereof and receives the signal GE&lt; 8 &gt; at the terminal XS thereof. The signal GE&lt; 8 &gt; is an AND value of the bits A&lt; 8 &gt; to A&lt; 15 &gt;. Accordingly, the four cells A 001  of the fourth logical AND generation section  54   b  output four kinds of logical values including an AND value of the bits A&lt; 4 &gt; to A&lt; 15 &gt;, an AND value of the bits A&lt; 5 &gt; to A&lt; 15 &gt;, an AND value of the bits A&lt; 6 &gt; to A&lt; 15 &gt; and an AND value of the bits A&lt; 7 &gt; to A&lt; 15 &gt; to the output terminals From the foregoing, the output terminals GE&lt; 0 : 15 &gt; and LT&lt; 0 : 15 &gt; of the 16-bit carry generation circuit  52  exhibit the following logical values. In particular, the signal GE&lt; 0 &gt; is an AND value of all of the 16 bits A&lt; 0 :  15 &gt;, and the signal LT&lt; 0 &gt; is an inverted value of the AND value of all of the 16 bits A&lt; 0 :  15 &gt;; the signal GE&lt; 1 &gt; is an AND value of the 15 bits A&lt; 1 :  15 &gt;, and the signal LT&lt; 1 &gt; is an inverted value of the AND value of the 15 bits A&lt; 1 :  15 &gt;; . . . ; and the signal GE&lt; 14 &gt; is an AND value of the 2 bits A&lt; 14 :  15 &gt;, and the signal LT&lt; 14 &gt; is an inverted value of the AND value of the 2 bits A&lt; 14 :  15 &gt;. The signal GE&lt; 15 &gt; is a value of the bit A&lt; 15 &gt;, and the signal LT&lt; 1 &gt; is an inverted value of the value of the bit A&lt; 15 &gt;. 
   The 16-bit carry generation circuit  52  having the construction described above produces an AND value and a NAND value of the 16-bit signal A&lt; 0 :  15 &gt; at a high speed and outputs the resulting values to the terminals GE&lt; 0 :  15 &gt; and LE&lt; 0 :  15 &gt;. Accordingly, since a carry (AND value of the bits A&lt; 0 &gt; to A&lt; 15 &gt;) necessary for counting up is successively delivered at a high speed to the next stage, for example, an increment circuit having a bit length longer than 16 bits can produce a carry, which appears as a result of addition of the 16 low order bits, at a high speed. 
   In this manner, the 16-bit carry generation circuit  52  is formed only from 4-bit carry generation circuits ( 52   a , on  52   b ,  52   c  and  52   d ) and cells A 001  ( 53   a ,  53   b ,  54   a  and  54   b ), and repetitiveness of wiring patterns can be increased and the expandability can be raised. In other words, the 16-bit carry generation circuit  52  is advantageous in that it can be expanded to a carry generation circuit of N bits and the man-hours for circuit designing can be reduced significantly. 
   An increment circuit can be formed using such 16-bit carry generation circuit (CARRY 002 ), cell A 001  and cell A 002  as described above. It is to be noted that a carry generation circuit of a universal bit length n 3  can be formed. The bit number n 3  is an integer equal to 2 to the m 3 th power (here m 3  is an even number equal to or greater than 2). Thus, an increment circuit of the bit length n 3  where n 3  is n 3 =64 is described below. 
     FIG. 24  is a block diagram showing a construction of a 64-bit increment circuit according to the embodiment of the present invention. Referring to  FIG. 24 , the 64-bit increment circuit  55  shown is a CMOS logic circuit for use with, for example, a command register for a processor and so forth and includes a pair of inverters  61   a  and  61   b , a first carry generation section  56   a , a second carry generation section  56   b , a third carry generation section  56   c , a fourth carry generation section  56   d , a first logical AND generation section  57 , a second logical AND generation section  58 , a third logical AND generation section  59 , and a fourth logical AND generation section  60  as well as a full addition arithmetic section  62 . 
   It is to be noted that reference symbol A&lt; 0 : 63 &gt; on the input side shown in  FIG. 24  is a signal name, and A and X of the inverters  61   a  and  61   b  are signal names. Further, reference symbols XA&lt; 0 :  63 &gt; and XXA&lt; 0 :  63 &gt; as well as &lt; 0 :  15 &gt;, &lt; 16 :  31 &gt;, &lt; 32 :  47 &gt; and &lt; 48 :  63 &gt; connected to the outputs of the inverters  61   a  and  61   b  are signal names. Meanwhile, reference symbols A&lt; 0 :  15 &gt;, XA&lt; 0 :  15 &gt;, GE&lt; 0 :  15 &gt; and LT&lt; 0 :  15 &gt; in the CARRY 002 , A 1 , XS, S, A 2 , X 1  and X 2  in the cell A 001  and GE&lt; 0 :  15 &gt; and LT&lt; 0 :  15 &gt; which are outputs of the 16-bit carry generation circuit  52  denote terminals. It is to be noted that the first logical AND generation section  57 , the second logical AND generation section  58 , the third logical AND section  59  and reference symbols &lt; 16 &gt;, GE 16 – 31 &lt; 16 :  31 &gt;, &lt; 48 &gt; and &lt; 32 &gt; on the input side of the fourth logical AND generation section  60  and &lt; 0 :  62 &gt;, &lt; 1 :  63 &gt; and &lt; 63 &gt; on the input side of the full addition arithmetic section  62  denote signals. Further, reference symbols XA, S, XS, A, I, XI and X in the full addition arithmetic section  62  denote terminals, and &lt; 0 :  62 &gt; and &lt; 63 &gt; on the output sides of them denote signals. 
   Each of the inverters  61   a  and  61   b  outputs an inverted logical value of an inputted logic value and is formed from such an inverter as may be selected, for example, from within a standard library provided in a circuit designing tool. The first carry generation section  56   a  receives a first input signal A&lt; 0 :  63 &gt; of 64 bits and an inverted signal XA&lt; 0 :  63 &gt; of the first input signal of 64 bits as input signals and outputs a first logical AND result and a first logical AND inversion result as a logical AND result at least of the bits A&lt; 0 &gt; to A&lt; 15 &gt; from the signals A&lt; 0 :  15 &gt; and XA&lt; 0 :  15 &gt;. The first carry generation section  56   a  is formed from a 16-bit carry generation circuit (CARRY 002 ) shown in  FIG. 23 . Similarly, the second carry generation section  56   b  produces from the bits A&lt; 16 :  31 &gt; and XA&lt; 16 :  31 &gt; and outputs a second logical AND result and a second logical AND inversion result as a logical AND result at least of the bits A&lt; 16 &gt; to A&lt; 31 &gt;; the third carry generation section  56   c  produces from the bits A&lt; 32 :  47 &gt; and XA&lt; 32 :  47 &gt; and outputs a third logical AND result and a third logical AND inversion result as a logical AND result at least of the bits A&lt; 32 &gt; to A&lt; 47 &gt;; and the fourth carry generation section  56   d  produces from the bits A&lt; 48 :  63 &gt; and XA&lt; 48 :  63 &gt; and outputs a fourth logical AND result and a fourth logical AND inversion result as a logical AND result at least of the bits A&lt; 48 &gt; to A&lt; 63 &gt;. Each of the carry generation sections  56   a ,  56   b  and  56   c  is formed from a 16-bit carry generation circuit (CARRY 002 ). 
   The first logical AND generation section  57  receives the first logical AND result and the first logical AND inversion result as well as the second logical AND result and the second logical AND inversion result as inputs and outputs a fifth logical AND result and a fifth logical AND inversion result at least of the bits A&lt; 0 &gt; to A&lt; 31 &gt;. The first logical AND generation section  57  is composed of 16 cells A 001  (denoted by  57 - 1  to  57 - 16 ). Similarly, the second logical AND generation section  58  receives the third logical AND result and the third logical AND inversion result as well as the fourth logical AND result and the fourth logical AND inversion result as inputs and outputs a sixth logical AND result and a sixth logical AND inversion result at least of the bits A&lt; 32 &gt; to A&lt; 47 &gt;. The second logical AND generation section  58  is composed of 16 cells A 001  (denoted by  58 - 1  to  58 - 16 ). The third logical AND generation section  59  produces from the fifth logical AND result and the fifth logical AND inversion result as well as the sixth logical AND result and the sixth logical AND inversion result and outputs a seventh logical AND result and a seventh logical AND inversion result as a logical AND result at least of the bits A&lt; 0 &gt; to A&lt; 63 &gt;. The third logical AND generation section  59  is composed of 16 cells A 001  (denoted by  59 - 1  to  59 - 16 ). The fourth logical AND generation section  60  produces from the second logical AND result and the second logical AND inversion result as well as the sixth logical AND result and the sixth logical AND inversion result and outputs an eighth logical AND result and an eighth logical AND inversion result as a logical AND result at least of the bits A&lt; 16 &gt; to A&lt; 63 &gt;. The fourth logical AND generation section  60  is composed of 16 cells A 001  (denoted by  60 - 1  to  60 - 16 ). 
   The full addition arithmetic section  62  produces from a first gate signal of 64 bits composed of the seventh logical AND result, the eighth logical AND result, the sixth logical AND result and the fourth logical AND result and a second gate signal of 64 bits composed of the seventh logical AND inversion result, the eighth logical AND inversion result, the sixth logical AND inversion result and the fourth logical AND inversion result and outputs a full addition arithmetic result of 64 bits. The full addition arithmetic section  62  is formed from 63 cells A 002  (denoted by  62 - 1  to  62 - 63 ). 
   In the 64-bit increment circuit  55  described above, an input signal A&lt; 0 :  63 &gt; is inverted by the inverter  61   a  to produce an inverted signal XA&lt; 0 :  63 &gt; and then is inverted by the inverter  61   b  again to obtain a signal XXA&lt; 0 :  63 &gt; (that is, the signal A&lt; 0 :  63 &gt;). From within the signals A&lt; 0 :  63 &gt; and XA&lt; 0 :  63 &gt;, the bits A&lt; 0 :  15 &gt; and XA&lt; 0 :  15 &gt; are inputted to the first carry generation section  56   a . Similarly, the bits A&lt; 16 :  31 &gt; and XA&lt; 16 :  31 &gt; are inputted to the second carry generation section  56   b ; the bits A&lt; 32 :  47 &gt; and XA&lt; 32 :  47 &gt; are inputted to the third carry generation section  56   c ; and the bits A&lt; 48 :  63 &gt; and XA&lt; 48 :  63 &gt; are inputted to the fourth carry generation section  56   d . Of the outputs of the first carry generation section  56   a , at the output GE&lt; 0 &gt;, an AND value of the 16 bits A&lt; 0 :  15 &gt; appears; at the output GE&lt; 1 &gt;, an AND value of the 15 bits A&lt; 1 :  15 &gt; appears; . . . ; at the output GE&lt; 14 &gt;, an AND value of the 2 bits A&lt; 14 :  15 &gt; appears; and at the output GE&lt; 15 &gt;, the bit value of the bit A&lt; 15 &gt; appears. Similarly, of the outputs of the second carry generation section  56   b , at the output GE&lt; 0 &gt;, an AND value of the 16 bits A&lt; 16 :  31 &gt; appears; at the output GE&lt; 1 &gt;, an AND value of the 15 bits A&lt; 17 :  31 &gt; appears; . . . ; at the output GE&lt; 14 &gt;, an AND value of the 2 bits A&lt; 30 :  31 &gt; appears; and at the output GE&lt; 15 &gt;, the bit value of the bit A&lt; 31 &gt; appears. Of the outputs of the third carry generation section  56   c , at the output GE&lt; 0 &gt;, an AND value of the 16 bits A&lt; 32 :  47 &gt; appears; at the output GE&lt; 1 &gt;, an AND value of the 15 bits A&lt; 33 :  47 &gt; appears; . . . ; at the output GE&lt; 14 &gt;, an AND value of the 2 bits A&lt; 46 :  47 &gt; appears; and at the output GE&lt; 15 &gt;, the bit value of the bit A&lt; 47 &gt; appears. Of the outputs of the fourth carry generation section  56   d , at the output GE&lt; 0 &gt;, an AND value of the 16 bits A&lt; 48 :  63 &gt; appears; at the output GE&lt; 1 &gt;, an AND value of the 15 bits A&lt; 49 :  63 &gt; appears; . . . ; at the output GE&lt; 14 &gt;, an AND value of the 2 bits A&lt; 62 :  63 &gt; appears; and at the output GE&lt; 15 &gt;, the bit value of the bit A&lt; 63 &gt; appears. 
   Then, the first logical AND generation section  57  (cells  57 - 1  to  57 - 16 ) and the second logical AND generation section  58  (cells  58 - 1  to  58 - 16 ) merge the outputs of the first carry generation section  56   a  and the outputs of the second carry generation section  56   b . Thus, an AND value of the 32 bits A&lt; 0 :  31 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  57 - 1 ); an AND value of the 31 bits A&lt; 1 :  31 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  57 - 2 ); . . . ; and an AND value of the 17 bits A&lt; 15 :  31 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  57 - 16 ). Meanwhile, an AND value of the 32 bits A&lt; 32 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  58 - 1 ); an AND value of the 31 bits A&lt; 33 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  58 - 2 ); . . . ; and an AND value of the 17 bits A&lt; 47 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  58 - 16 ). 
   Further, the third logical AND generation section  59  (cells  59 - 1  to  59 - 16 ) and the fourth logical AND generation section  60  (cells  60 - 1  to  60 - 16 ) merge the outputs of the second logical AND generation section  57  and the outputs of the third logical AND generation section  58 . Consequently, an AND value of the 64 bits &lt; 0 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  59 - 1 ); an AND value of the 63 bits &lt; 1 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  59 - 2 ); . . . , and an AND value of the 49 bits &lt; 15 : 63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  59 - 16 ). An AND value of the 48 bits &lt; 16 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  60 - 1 ); an AND value of the 47 bits &lt; 17 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  60 - 2 ); . . . , and an AND value of the 33 bits &lt; 31 :  63 &gt; is outputted to the output X 1  of the cell A 001  (denoted by  60 - 16 ). In this manner, an AND value of all of the 64 bits A&lt; 0 :  63 &gt; appears at the output GE&lt; 0 &gt; and an inverted value of the AND value of all of the 64 bits A&lt; 0 :  63 &gt; appears at the output LT&lt; 0 &gt;; an AND value of all of the 63 bits A&lt; 1 :  63 &gt; appears at the output GE&lt; 1 &gt; and an inverted value of the AND value of all of the 63 bits A&lt; 1 :  63 &gt; appears at the output LT&lt; 1 &gt;; . . . ; an AND value of all of the 2 bits A&lt; 62 :  63 &gt; appears at the output GE&lt; 14 &gt; and an inverted value of the AND value of all of the 2 bits A&lt; 62 :  63 &gt; appears at the output LT&lt; 14 &gt;; and the value of the bit A&lt; 63 &gt; appears at the output GE&lt; 15 &gt; and an inverted value of the value of the bit A&lt; 63 &gt; appears at the output LT&lt; 15 &gt;. 
   The signals in which the carries of the low order bits are merged are logically exclusively ORed by the full addition arithmetic section  62 . In particular, the original data A&lt; 0 :  62 &gt; and the carry GE&lt; 1 :  63 &gt; are logically exclusively ORed. More particularly, the cell A 002  (denoted by  62 - 1 ) logically exclusively ORs the highest order bit A&lt; 0 &gt; and the carry GE&lt; 1 &gt; from the figure next to it and outputs a result of full addition arithmetic. Here, the logical value 1 is inputted to the terminal I of the cell A 002  and the logical value 0 is inputted to the terminal X 1  of the cell A 002  so that the cell A 002  may perform logical exclusive ORing arithmetic between the input signal S and the input signal A (refer to the logical value table of  FIG. 21 ). Similarly, the cell A 002  (denoted by  62 - 1 ) logically exclusively ORs the bit A&lt; 1 &gt; and the carry GE&lt; 2 &gt; from the figure next to it and outputs a result of full addition arithmetic; . . . ; and the cell A 002  (denoted by  62 - 63 ) logically exclusively ORs the bit A&lt; 62 &gt; and the carry GE&lt; 63 &gt; from the lowest figure and outputs a result of full addition arithmetic. It is to be noted that arithmetic processing in the lowest figure is performed by the cell A 002  (denoted by  62   a ). A result of incrementing with the input signal A&lt; 0 :  63 &gt; appears at the output X&lt; 0 :  63 &gt; of the full addition arithmetic section  62 . 
   The 64-bit increment circuit  55  having such a construction as described above performs an incrementing operation. In particular, where the input to the increment circuit is A&lt; 0 :  63 &gt;, the output of the increment circuit is X&lt; 0 :  63 &gt;, the bit  0  is the highest order bit and the bit  63  is the lowest order bit, the value X&lt;K&gt; of the bit K (0≦K&lt;63) of the output X is determined as a logical exclusive OR of the bit A&lt;K&gt; and a carry GE&lt;K+1&gt; brought there from the lower order bits as a result of incrementing. Here, the carry GE&lt;K+1&gt; is an AND value of all of the bits A&lt;K+1:  63 &gt;. 
   Since the 64-bit increment circuit  55  is formed from leaf cells of 16-bit carry generation circuits (CARRY 002 ), cells A 001  and cells A 002  in this manner, the expandability is utilized. Further, since the 64-bit increment circuit  55  is simple in circuit configuration, a designer can design a circuit which is simple and efficient. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Further, since the same leaf cells can be used, the 64-bit increment circuit  55  is advantageous in that it contributes to augmentation of the yield and so forth upon production. Furthermore, since two kinds of signals of a regular phase signal and an inverted phase signal are normally produced and used in the inside of each of the leaf cells, there is an advantage that the entire circuit operates at a high speed. 
   Further, it is possible to add another adder circuit to the 64-bit increment circuit  55  to form an adder circuit of the 68+4-bit length. The “adder circuit of the 68+4-bit length” is a circuit which receives two kinds of signals including a 68-bit signal and a 4-bit signal as inputs thereto and performs addition arithmetic between the four low order bits of the 68-bit signal and the 4-bit signal. A value which corresponds to a command operand is placed in the four low order bits, and the value normally varies. 
     FIG. 25  is a block diagram showing a construction of a 68-bit+4-bit adder circuit according to the embodiment of the present invention. Referring to  FIG. 25 , the 68-bit+4-bit adder circuit (68-bit+4-bit ADDER)  63  is an adder circuit which performs full addition arithmetic of an input signal A&lt; 0 :  67 &gt; of 68 (64+4) bits and another input signal B&lt; 64 :  67 &gt; of 4 bits, and is composed of a 64-bit increment circuit  55 , an inverter  61   c  and a 4-bit full adder circuit  65 . 
   It is to be noted that reference symbols A&lt; 0 :  63 &gt;, A&lt; 64 :  67 &gt; and B&lt; 64 :  67 &gt; are signal names, and A and X of the inverter  61   c  denote an input terminal and an output terminal, respectively. Further, reference symbols A&lt; 0 :  3 &gt;, XB&lt; 0 :  3 &gt;, C&lt; 0 &gt;, XC&lt; 0 &gt; and S&lt; 0 :  3 &gt; of the 4-bit full adder circuit  65  denote signals (or terminals). It is to be noted that reference symbols applied to the 64-bit increment circuit  55  are similar to those described hereinabove, and therefore, overlapping description of them is omitted here. 
   The inverter  61   c  inverts the input signal &lt; 64 :  67 &gt; and outputs the inverted signal. The inverter  61   c  is formed from such an inverter as may be selected, for example, from within a standard library provided in a circuit designing tool. The 4-bit full adder circuit  65  performs full addition arithmetic of the four low order bits of the input signal A&lt; 0 :  67 &gt; and the 4 bits from the inverter  61   c  and inputs a resulting carry generation signal C&lt; 0 &gt; to the full addition arithmetic section  62  of the 64-bit increment circuit  55 . The 4-bit full adder circuit  65  is formed from a 4-bit full adder circuit (IADD 4 ) described hereinabove. The carry generation signal C&lt; 0 &gt; is inputted to the input terminals I of the 63 cells A 002  (denoted by  62 - 1  to  62 - 63 ) in the full addition arithmetic section  62  and the input terminal I of the cell A 002  (denoted by  62   a ). Also an inverted signal XC&lt; 0 &gt; of the carry generation signal C&lt; 0 &gt; is inputted to the input terminals XI of the pertaining cells A 002  similarly. It is to be noted that the 4-bit full adder circuit  65  may be formed from such an adder circuit which is selected, for example, from within a standard library provided in a circuit designing tool. 
   Flows of the input signals A&lt; 64 :  67 &gt; and B&lt; 64 :  67 &gt; in the 68-bit+4-bit adder circuit  63  described above are described below with reference to  FIG. 25 . First, the 4-bit full adder circuit  65  performs full addition arithmetic of the bits A&lt; 64 :  67 &gt; and bits XB&lt; 64 :  67 &gt; inverted by the inverter  61   c , and a carry generation signal C&lt; 0 &gt; which thereupon appears from the 4-bit full adder circuit  65  is inputted to the cell A 002  (denoted by  62 - 63 ) in the full addition arithmetic section  62 . If the carry from the 4-bit full adder circuit  65  is 0, then the cell A 002  receives 0 at the terminal I thereof and receives 1 at the terminal XI thereof, and consequently, the bits A&lt; 0 :  63 &gt; are outputted as they are to the output terminal X&lt; 0 :  63 &gt; of the cell A 002 . On the other hand, if the carry from the 4-bit full adder circuit  65  is 1, then the cell A 002  receives 1 at the terminal I thereof and receives 0 at the terminal XI thereof, and consequently, a value equal to a sum of the bits A&lt; 0 :  63 &gt; and 1 appears at the output terminal X&lt; 0 :  63 &gt; of the cell A 002 . 
   In the 68-bit+4-bit adder circuit  63  having the construction described above, the carry C&lt; 0 &gt; which is a result of addition of the four low order bits A&lt; 64 :  67 &gt; of the signal A&lt; 0 :  67 &gt; and the bits &lt; 64 :  67 &gt; is delivered to the lowest order bit A&lt; 63 &gt; of the bits A&lt; 0 :  63 &gt; while a result of addition of the four lower order bits A&lt; 64 :  67 &gt; and the bits B&lt; 64 :  67 &gt; is obtained. Further, in each of the cells A 002  in the full addition arithmetic section  62 , logical exclusive ORing of a half addition arithmetic result at each of the 64 higher order figures and a carry brought there from the lower order figures is executed, and a full addition arithmetic result of the 64 higher order figures is outputted. Then, the 68-bit+4-bit adder circuit  63  outputs the outputs of the 64-bit increment circuit  55  as values of the 64 higher order figures and outputs the outputs of the 4-bit full adder circuit  65  as values of the four lower order figures. 
   In this manner, the full adder circuit of 64+4 bits is composed of the 64-bit increment circuit  55  and the 4-bit full adder circuit  65 , and a terminal for a carry generation signal of the 4-bit full adder circuit  65  is connected to the terminal I of the cell A 002  in the 64-bit increment circuit  55  while a terminal for an inverted signal of the carry generation signal is connected to the terminal XI of the cell A 002 . Further, since the full adder circuit has increased repetitiveness of wiring lines, the circuit configuration is simplified. Consequently, the full adder circuit is advantageous in that the man-hours for layout upon development can be reduced significantly and the period for development can be reduced significantly. Furthermore, since the number of parts can be suppressed and the expandability is raised, there is another advantage that the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Besides, since the component circuits described above are formed from leaf cells A 001  and A 002  and two kinds of signals of a regular phase signal and an inverted phase signal are normally produced in each of the leaf cells as described hereinabove, there is an advantage that high speed circuit operation can be achieved. 
   Further, since the bit number can be expanded in such a manner as described above, an n 3 -bit increment circuit can be constructed and a universal (N+M)-bit+M-bit adder circuit (N and M are natural numbers) can be constructed. 
   It is to be noted that the positive and negative signs of the logical values appearing on the cells, the circuits and the logical value tables described hereinabove are mere examples, and inverted logical values of them may be used instead. 
   B. In connection with the foregoing description, the following items (1) to (6) are disclosed. 
   (1) A CMOS logic circuit of the present invention comprises a first carry generation section for receiving a first input signal of 4 bits and a second input signal of 4 bits, performing comparison of them in magnitude for each bit and outputting results of the comparison of the individual bits as a first comparison result, a second comparison result, a third comparison result and a fourth comparison result using a plurality of status signals, a second carry generation section for performing comparison in magnitude between two high order bits of the first input signal and two high order bits of the second input signal from the first comparison result and the second comparison result and outputting results of the comparison of the 2 bits as a fifth comparison result using the plurality of status signals and for performing comparison in magnitude between two low order bits of the first input signal and two low order bits of the second input signal from the third comparison result and the fourth comparison result and outputting results of the comparison of the 2 bits as a sixth comparison result using the plurality of status signals, and a third carry generation section for performing comparison in magnitude between the four bits of the first input signal and the four bits of the second input signal from the fifth comparison result and the sixth comparison result and outputting a result of the comparison of the 4 bits using the plurality of status signals. 
   The first carry generation section may include a plurality of magnitude discrimination circuits each of which is formed from a first inversion section for inverting the first input signal and outputting the inverted signal, a second inversion section for inverting the second input signal and outputting the inverted signal, and a transmission section capable of discriminating a magnitude relationship of one bit between the first input signal and the second input signal and outputting a result of the discrimination using the plurality of status signals. 
   Accordingly, the CMOS logic circuit of the present invention is advantageous in that it performs circuit operation at a high speed since the 4-bit magnitude comparison circuit is formed from cells LGEN and LSEL 2  and each of the cells normally produces and uses two kinds of signals of a regular phase signal and an inverted phase signal in the inside thereof as described hereinabove. Further, since such cells LGEN and LSEL 2  as described above are used, the CMOS logic circuit is advantageous in that it can be formed in a simple circuit configuration. 
   The second carry generation section may be composed of a first link selector circuit for receiving the first comparison result and the second comparison result as input signals and outputting the fifth comparison result, and a second link selector circuit for receiving the third comparison result and the fourth comparison result as input signals and outputting the sixth comparison result, and the third carry generation section may be composed of a third link selector circuit for receiving the fifth comparison result and the sixth comparison result as input signals and outputting a result of comparison of the four bits. 
   Each of the first link selector circuit, second link selector circuit and third link selector circuit may include a first branch section for receiving two kinds of comparison result information using four kinds of status signals and branching a first signal of one of the two kinds of comparison result information, a second branch section for branching a second signal of the one of the two kinds of comparison result information, a third branch section for branching a third signal of the one of the two kinds of comparison result information and a fourth branch section for branching a fourth signal of the one of the two kinds of comparison result information, a first selector circuit for receiving signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a third signal and a fourth signal of the other of the two kinds of comparison result information, and a second selector circuit for receiving the signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a first signal and a second signal of the other of the two kinds of comparison result information, the first selector circuit and the second selector circuit being formed from cells LSEL 2 . 
   Accordingly, by using the link selector circuits, a circuit having a high degree of expandability can be designed. 
   (2) Another CMOS logic circuit of the present invention comprises a first comparison section for receiving a first input signal of 16 bits and a second input signal of 16 bits, performing comparison in magnitude between 4 high order bits of the first input signal and 4 high order bits of the second input signal and outputting results of the comparison of the 4 bits as a first comparison result, a second comparison result, a third comparison result and a fourth comparison result using a plurality of status signals, a second comparison section for performing comparison in magnitude between 8 high order bits of the first input signal and 8 high order bits of the second input signal from the first comparison result and the second comparison result and outputting results of the comparison of the 8 high order bits as a fifth comparison result using the plurality of status signals and for performing comparison in magnitude between 8 low order bits of the first input signal and 8 low order bits of the second input signal from the third comparison result and the fourth comparison result and outputting a result of the comparison of the 8 low order bits as a sixth comparison result using the plurality of status signals, and a third comparison section for performing comparison in magnitude between the 16 bits of the first input signal and the 16 bits of the second input signal from the fifth comparison result and the sixth comparison result and outputting a result of the comparison of the 16 bits using the plurality of kinds of status signals. 
   The first comparison section may include a plurality of 4-bit magnitude comparison circuits, each of which is formed from a cell ICMP 4  described hereinabove. 
   The CMOS logic circuit of the present invention is advantageous in that it can be formed with a simple circuit configuration since the 16-bit magnitude comparison circuit is constructed without varying the basic constructions of the 4-bit magnitude comparison circuits and the link selector circuits and besides makes much use of repetitiveness of wiring lines. Further, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly, and besides it is possible to design a circuit having a high degree of expandability. Furthermore, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Besides, since the 4-bit magnitude comparison circuits and the link selector circuits are formed from cells LGEN and LSEL 2 , respectively, and each of the leaf cells normally produces two kinds of signals of a regular phase signal and an inverted phase signal in the inside thereof as described hereinabove, there is an advantage that the entire circuit operates at a high speed. 
   The second comparison section may be composed of a first link selector circuit for receiving the first comparison result and the second comparison result as input signals and outputting the fifth comparison result, and a second link selector circuit for receiving the third comparison result and the fourth comparison result as input signals and outputting the sixth comparison result, and the third comparison section may be composed of a third link selector circuit for receiving the fifth comparison result and the sixth comparison result as input signals and outputting a result of the comparison of the 16 bits. 
   Each of the first link selector circuit, second link selector circuit and third link selector circuit may include a first branch section for receiving two kinds of comparison result information using two kinds of status signals and branching a first signal of one of the two kinds of comparison result information, a second branch section for branching a second signal of the one of the two kinds of comparison result information, a third branch section for branching a third signal of the one of the two kinds of comparison result information and a fourth branch section for branching a fourth signal of the one of the two kinds of comparison result information, a first selector circuit for receiving signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a third signal and a fourth signal of the other of the two kinds of comparison result information, and a second selector circuit for receiving the signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a first signal and a second signal of the other of the two kinds of comparison result information, the first selector circuit and the second selector circuit being formed from cells LSEL 2 . 
   Accordingly, a circuit of a high degree of expandability can be designed by using link selector circuits. 
   (3) A further CMOS logic circuit of the present invention comprises a first carry generation section for receiving a first input signal of 4 bits and an inverted signal of a second input signal of 4 bits, performing magnitude comparison of them for each one bit and outputting results of the magnitude comparison of the individual bits as a first carry, a second carry, a third carry and a fourth carry using a plurality of status signals, a second carry generation section for outputting logical AND information of the first carry and the second carry as a fifth carry using a plurality of kinds of status signals and outputting logical AND information of the third carry and the fourth carry as a sixth carry using the plurality of kinds of status signals, and a third carry generation section for outputting logical AND information of the first carry, second carry, third carry and fourth carry as a seventh carry from the fifth carry and the sixth carry using the plurality of kinds of status signals and outputting logical AND information of the second carry, third carry and fourth carry as an eighth carry from the second carry and the sixth carry using the plurality of kinds of status signals, the fourth carry, the sixth carry, the seventy carry and the eighth carry being outputted using the plurality of status signals. 
   The first carry generation section may include a plurality of magnitude discrimination circuits, each of which is formed from a cell LGEN. 
   The CMOS logic circuit of the present invention is advantageous in that it performs circuit operation at a high speed and has a simplified circuit configuration since the 4-bit full adder circuit is formed from cells LGEN and LSEL 2  and each of the cells normally produces and uses two kinds of signals of a regular phase signal and an inverted phase signal in the inside thereof. 
   The second carry generation section may be composed of a first link selector circuit for receiving the first carry and the second carry as input signals and outputting the fifth carry, and a second link selector circuit for receiving the third carry and the fourth carry as input signals and outputting the sixth carry, and the third carry generation section may be composed of a third link selector circuit for receiving the fifth carry and the sixth carry as input signals and outputting the seventh carry, and a fourth link selector for receiving the second carry and the sixth carry as input signals and outputting the eighth carry. 
   Each of the first link selector circuit, second link selector circuit, third link selector circuit and fourth link selector circuit may include a first branch section for receiving two kinds of comparison result information using a plurality of kinds of status signals and branching a first signal of one of the two kinds of comparison result information, a second branch section for branching a second signal of the one of the two kinds of comparison result information, a third branch section for branching a third signal of the one of the two kinds of comparison result information and a fourth branch section for branching a fourth signal of the one of the two kinds of comparison result information, a first selector circuit for receiving signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a third signal and a fourth signal of the other of the two kinds of comparison result information, and a second selector circuit for receiving the signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a first signal and a second signal of the other of the two kinds of comparison result information, the first selector circuit and the second selector circuit being formed from cells LSEL 2 . 
   Accordingly, a circuit of a high degree of expandability can be designed by using link selector circuits. 
   (4) A further CMOS logic circuit of the present invention comprises a half addition arithmetic section for receiving a first input signal of 16 bits and an inverted signal of a second input signal of 16 bits and performing half addition arithmetic of the first input signal and the inverted signal of the second input signal, a first arithmetic section for performing full addition arithmetic of the first input signal and the inverted signal of the second input signal separately for each four bits and outputting full addition arithmetic results for the four bits as a first carry, a second carry, a third carry and a fourth carry using a plurality of status signals, a second arithmetic section for outputting logical AND information of the first carry and the second carry as a fifth carry using the plurality of status signals and outputting logical AND information of the third carry and the fourth carry as a sixth carry using the plurality of status signals, a third arithmetic section for outputting logical AND information of all of the 16 bits at least from the fifth carry and the sixth carry as a seventh carry using the plurality of status signals, and a fourth arithmetic section for performing logical exclusive ORing of the output of the half addition arithmetic section and the seventh carry and outputting a full addition arithmetic result. 
   The first arithmetic section may be composed of a plurality of 4-bit full adder circuits, each of which is formed from a circuit IADD 4 . The second arithmetic section may be composed of a first link selector circuit for receiving the first carry and the second carry as input signals and outputting the fifth carry, and a second link selector circuit for receiving the third carry and the fourth carry as input signals and outputting the sixth carry, and the third arithmetic section may be composed of a third link selector circuit for receiving the fifth carry and the sixth carry as input signals and outputting the seventh carry, and a fourth link selector for receiving the second carry and the sixth carry as input signals and outputting the eighth carry. 
   Each of the first link selector circuit, second link selector circuit, third link selector circuit and fourth link selector circuit may include a first branch section for receiving two kinds of comparison result information using a plurality of kinds of status signals and branching a first signal of one of the two kinds of comparison result information, a second branch section for branching a second signal of the one of the two kinds of comparison result information, a third branch section for branching a third signal of the one of the two kinds of comparison result information and a fourth branch section for branching a fourth signal of the one of the two kinds of comparison result information, a first selector circuit for receiving signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a third signal and a fourth signal of the other of the two kinds of comparison result information, and a second selector circuit for receiving the signals outputted from the first branch section, second branch section, third branch section and fourth branch section and a first signal and a second signal of the other of the two kinds of comparison result information, the first selector circuit and the second selector circuit being formed from cells LSEL 2 . 
   The half addition arithmetic section may include a first inversion section for outputting an inverted logic value of the first input signal, a second inversion section for outputting a second signal, and a half addition processing section for performing half addition arithmetic between the output of the first inversion section and the output of the second inversion section, and the half addition processing section may be formed from a cell LEOR. The fourth arithmetic section may include an inversion section for outputting an inverted logical value of an input signal, and a half addition arithmetic outputting section for performing half addition arithmetic between the output of the inversion section and the output of the third arithmetic section. The half addition arithmetic outputting section may be formed from a cell LEOR. 
   The CMOS logic circuit of the present invention is advantageous in that it is simple in circuit configuration making most of utilizing repetitiveness of wiring lines since the 16-bit full adder circuit is formed from 4-bit full adder circuits IADD 4 , cells LSEL 2  and cells LEOR. Further, the 16-bit full adder circuit can be formed so as to receive a minimized number of input signals and so as to cope with various hierarchies from comparison of 1 bit to comparison of 16 bits. Consequently, the layout man-hours upon development can be reduced significantly and the development man-hours can be reduced significantly, and besides it is possible to design a circuit having a high degree of expandability. Further, since the number of parts can be suppressed, the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Furthermore, the man-hours for arrangement or layout of transistors upon development are reduced significantly. Further, since the same leaf cells can be used, the CMOS logic circuit is advantageous in that it contributes to augmentation of the yield and so forth upon production. Furthermore, since two kinds of signals of a regular phase signal and an inverted phase signal are normally produced and used in the inside of each of the leaf cells, there is an advantage that the entire circuit operates at a high speed. Further, by using the link selector circuits, a circuit having a high degree of expandability can be designed. 
   (5) A yet further CMOS logic circuit of the present invention comprises a first logical AND generation section for receiving two high order bits of a first input signal of 4 bits and two high order bits of an inverted signal of the first input signal of 4 bits as inputs and outputting a first logical AND result and a first logical AND inversion result as logical AND results of the two high order bits of the first input signal, a second logical AND generation section for receiving two low order bits of the first input signal and two low order bits of the inverted signal as inputs thereto and outputting a second logical AND result and a second logical AND inversion result as logical AND results of the two low order bits of the first input signal, a third logical AND generation section for receiving the first logical AND result and the first logical AND inversion result as well as the second logical AND result and the second logical AND inversion result as inputs thereto and outputting a third logical AND result and a third logical AND inversion result as logical AND results of the 4 bits of the first input signal, and a fourth logical AND generation section for receiving the second bit of the first input signal and the second bit of the second input signal as well as the third logical AND result and the third logical AND inversion result as inputs thereto and outputting a fourth logical AND result and a fourth logical AND inversion result as logical AND results of the three high order bits of the first input signal, the CMOS logic circuit outputting the third logical AND result, the fourth logical AND result, the second logical AND result and the fourth bit of the first input signal as a first gate signal of 4 bits while outputting the third logical AND inversion result, the fourth logical AND inversion result, the second logical AND inversion result and the fourth bit of the first input signal as a second gate signal of 4 bits. 
   The CMOS logic circuit of the present invention is advantageous in that carries can be produced at a high speed since the 4-bit carry generation circuit CARRY 001  is formed from cells A 001  and a carry necessary for counting up is successively delivered to a next stage at a high speed. 
   A yet further CMOS logic circuit of the present invention comprises a first carry generation section for receiving a first input signal A&lt; 0 :  15 &gt; of 16 bits and an inverted signal XA&lt; 0 :  15 &gt; of the first input signal of 16 bits as inputs thereto and outputting a logical AND value at least of the bits A&lt; 0 &gt; to A&lt; 3 &gt; and an inverted value of the logical AND value as a first logical AND result and a first logical AND inversion result, respectively, a second carry generation section for outputting a logical AND value at least of the bits A&lt; 4 &gt; to A&lt; 7 &gt; and an inverted value of the logical AND value as a second logical AND result and a second logical AND inversion result, respectively, a third carry generation section for outputting a logical AND value at least of the bits A&lt; 8 &gt; to A&lt; 11 &gt; and an inverted value of the logical AND value as a third logical AND result and a third logical AND inversion result, respectively, a fourth carry generation section for outputting a logical AND value at least of the bits A&lt; 12 &gt; to A&lt; 15 &gt; and an inverted value of the logical AND value as a fourth logical AND result and a fourth logical AND inversion result, respectively, a first logical AND generation section for producing from the first logical AND result and the second logical AND result and outputting a fifth logical AND result and a fifth logical AND inversion result as a result of a logical AND value at least of the bits A&lt; 0 &gt; to A&lt; 7 &gt;, a second logical AND generation section for producing from the third logical AND result and the fourth logical AND result and outputting a sixth logical AND result and a sixth logical AND inversion result as a result of a logical AND value at least of the bits A&lt; 8 &gt; to A&lt; 15 &gt;, a third logical AND generation section for producing from the fifth logical AND result, the fifth logical AND inversion result, the sixth logical AND result and the sixth logical AND inversion result and outputting a seventh logical AND result and a seventh logical AND inversion result as a result of a logical AND value at least of the bits A&lt; 0 &gt; to A&lt; 15 &gt;, and a fourth logical AND generation section for producing from the second logical AND result, the second logical AND inversion result, the sixth logical AND result and the sixth logical AND inversion result and outputting an eighth logical AND result and an eighth logical AND inversion result as a result of a logical AND value at least of the bits A&lt; 4 &gt; to A&lt; 15 &gt;, the CMOS logic circuit outputting the seventh logical AND result, the eighth logical AND result, the sixth logical AND result and the fourth logical AND result as a first gate signal of 16 bits while outputting the seventh logical AND inversion result, the eighth logical AND inversion result, the sixth logical AND inversion result and the fourth logical AND result as a second gate signal of 16 bits. 
   The first carry generation section, second carry generation section, third carry generation section and fourth carry generation section may each be formed from a 4-bit carry generation circuit CARRY 001 . 
   The CMOS logic circuit of the present invention is advantageous in that carries can be produced at a high speed since the 16-bit carry generation circuit CARRY 002  is formed from 4-bit carry generation circuits CARRY 001  and cells A 001  and a carry necessary for counting up is successively delivered as a carry from the lower order bits to a next stage at a high speed. The CMOS logic circuit is advantageous also in that repetitiveness of wiring patterns can be increased and the CMOS logic circuit can be expanded to a CMOS logic circuit of N bits and the man-hours for circuit designing can be reduced significantly. 
   (6) In addition, as a yet further CMOS logic circuit of the present invention, in regard to the increment circuit described above, an adder circuit for performing full addition arithmetic of a first input signal of (n 3 +m 4 ) bits (n 3  is an integer equal to 2 to the m 3 th power, here m 3  is an even number equal to or greater than 2; m 4  is an integer equal to or greater than 1) and a second input signal of m 4  bits, may comprise an n 3 -bit increment circuit, an inversion section provided on the input side of the n 3 -bit increment circuit for inverting the second input signal and outputting the inverted signal, and an m 4 -bit full adder circuit for performing full addition arithmetic of low order m 4  bits of the first input signal and m 4  bits from the inversion section and inputting a carry generation signal produced upon the full addition arithmetic to a full addition arithmetic section of the n 3 -bit increment circuit, an output of the n 3 -bit increment circuit being outputted as a value of the high order n 3  bits while an output of the m 4 -bit full addition circuit is outputted as a value of the low order m 4  bits. 
   The m 4 -bit full adder circuit may be formed from a 4-bit full adder circuit IADD 4 . 
   With the CMOS logic circuit of the present invention, since the full adder circuit of 64+4 bits is composed of a 64-bit increment circuit and a 4-bit full adder circuit, there is an advantage that repetitiveness of wiring lines is increased and the circuit configuration is simplified, and consequently, the man-hours for layout upon development can be reduced significantly and the period for development can be reduced significantly. Further, since the number of parts can be suppressed and the expandability is raised, there is another advantage that the time required for tuning of parts is reduced significantly when compared with a circuit which includes many parts. Besides, since the component circuits described above are formed from leaf cells A 001  and A 002  and two kinds of signals of a regular phase signal and an inverted phase signal are normally produced in each of the leaf cells, there is an advantage that high speed circuit operation can be achieved. The CMOS logic circuit is advantageous also in that a full adder circuit for a first input signal of (n 3 +m 4 ) bits (m 4  is an integer equal to or greater than 1) and a second signal of m 4  bits can be constructed. 
   The present invention is not limited to the embodiment specifically described above, and variations and modifications can be made without departing from the scope of the present invention.