Abstract:
In a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and first and second MOSFETs connected in series between a clock pulse terminal and ground. The first MOSFET conducts in response to the terminal voltage of the capacitor to transmit a clock pulse from its drain and supplies an output to a word line. The terminal voltage of the capacitor in one decoder is applied to the gate of the second MOSFET of another decoder and the word line output of the other decoder is grounded even during the discharging period of the capacitor in the non-selection mode of the other decoder, enabling a synchronous supply of the address and the clock pulses.

Description:
BACKGROUND OF THE INVENTION 
     1. FIELD OF THE INVENTION 
     This invention relates to a metal-insulator-semiconductor (MIS) logic circuit and more particularly to a MIS decoder circuit. 
     2. DESCRIPTION OF THE PRIOR ART 
     A variety of random access memories (referred to as RAM, herein below) formed in ICs have been developed along with the recent remarkable progresses in microcomputers. A representative example is the Intel 1103 1 kbit MOS dynamic IC memory. The decoder circuit of such a RAM utilizes the dynamic ratioless circuit and is formed of a plurality of address circuits including a NAND type logic circuit. 
     An example of such a conventional MOS decoder logic circuits will be described referring to FIGS. 1A to 1C. 
     FIG. 1A shows the circuit structure and FIGS. 1B and 1C show the timing waveforms of an information output operation in the case of the address selection mode. 
     In this circuit, at first, a first pulse P is applied to the gate of a metal-oxide-semiconductor field effect transistor (MOSFET) Q 1 . Then, a parasitic capacitor C o  is charged with the voltage V DD  (precharge period t 1 ). In the address selection mode, no second pulses A to E are applied to the gates of the MOSFETS Q 2  to Q 6 . Thus, the capacitor C o  remains charged. Here, the first pulse no longer exists and the FET Q 1  is turned off. Then, a third pulse CE such as a socalled chip enable signal is applied to the drain of the MOSFET Q 7 . As a result, a signal of a logic value &#34;1&#34; is derived from a word line WL on the source side of said MOSFET Q 7 . For discharging the word line, the gate of the MOSFET Q 8  is applied with another pulse CE to bring it into the &#34;on&#34; state and hence to ground the word line WL. 
     Next, in the address non-selection mode, at least one second pulse as shown by A to E in FIG. 1B is applied to the gate of at least one MOSFET Q 2  (sampling period t 2 ). Therefore, the stored charge in the capacitor C o  is discharged through the one turned-on MOSFET among the MOSFETS Q 2  to Q 6 . At this time, the first pulse has already disappeared. When a third pulse CE is applied to the drain of the MOSFET Q 7  (information outputting period t 3 ), a signal of a logic &#34;O&#34; is derived from the word line WL connected to the source of the MOSFET Q 7 . In this way, the logical result of the MOS logic circuit Q 2  to Q 6  is stored in and read out from the capacitor C o . 
     In this way, the decoder circuit using the dynamic drive operates in a time sharing manner: in three periods made up of a charging period (t 1 ), a sampling period (t 2 ) and an information outputting period (t 3 ). The dynamic ratioless circuit used in this circuit is described in Japanese Patent Publication No. 47463/1972 (based on U.S. Ser. No. 523,767 filed on Jan. 28, 1966 and U.S. Ser. No. 10,966 filed on Feb. 11, 1970 ) and has such advantages that the power consumption is small, and that there is no need to consider the voltage ratio of the MOSFETS constituting the circuit. 
     In such a conventional circuit, however, in the address non-selection mode, there is a possibility of generating a signal of a logic &#34;1&#34; on the word line unless the third pulse CE is applied after the charge stored on the capacitor C o  has been completely discharged, as shown in FIG. 1C. Accordingly, there must be a sufficient delay in the input period of the third pulse CE as shown by the dotted line. Therefore, this leads to an elongated access time (FIG. 1C). 
     For solving these problems, the time constant for discharging the capacitor C o  in the address non-selection mode should preferably be made small. For reducing the time constant, the &#34;on&#34; resistance of all the MOSFETS Q 2  to Q 6  should be made sufficiently small. Here, it is not desirable from the design of an integrated circuit to make the size of the MOSs in the respective logic blocks disposed in rows and columns different. Thus, it becomes necessary to reduce the resistance of all the MOSFETs Q 2  to Q 6  and to manufacture all the logic blocks with the same ratings. 
     According to the above method, however, the time required for completely discharging the capacitor C o  cannot yet be precisely controlled. Hence, a malfunction may occur unless the third pulse CE is applied with a considerable time margin. Thus, the access time could not have been improved much. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of this invention is to provide a logic circuit utilizing dynamic drive, having a short access time and being free from malfunctions. 
     Another object of this invention is to provide a NAND type decoder circuit utilizing dynamic drive, having a simple circuit structure and capable of high speed accessing. 
     According to an embodiment of this invention, in an MOS logic circuit of dynamic drive type of conventional structure, a MOSFET means for discharging a charge stored on a word line is connected to the source side of a MOSFET means for outputting the stored information, and is also applied with a voltage at its gate to ground the source of the output MOSFET means during a predetermined discharging period of a precharge capacitor in the non-selection mode from the precharge period. In the period of grounding the source of the output MOSFET means, the word line is also grounded so that there exists no possiblity of causing a malfunction and that an address pulse and an information output enabling pulse can be supplied in synchronism. Thus, the access time can be shortened. 
     The above and other objects, features and advantages of this invention will become apparent from the following description of the embodiments of the invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a circuit diagram of a 5-bit decoder showing an example of the prior art. 
     FIGS. 1B and 1C are timing chart diagrams for explaining the operation of the circuit of FIG. 1A. 
     FIG. 2 is a basic logic circuit diagram for explaining the principle of this invention. 
     FIG. 3 is a circuit diagram of a 5-bit decoder according to an embodiment of this invention. 
     FIG. 4 is a circuit diagram of a plurality of decoders according to another embodiment of this invention. 
     FIG. 5 is a timing chart diagram for explaining the operation of the circuit of FIG. 4. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Throughout the figures, like reference numerals indicate like parts. 
     Prior to a detailed description of the embodiments of this invention, the basic structure of this invention will be described referring to FIG. 2. The circuit structure of FIG. 2 resembles that of the conventional NAND decoder circuit of FIG. 1. In the figure, letter G represents a logic circuit block corresponding to MOSFETs Q 2  to Q 6 . In this circuit, when an input signal is applied to an input terminal V in  of the logic circuit block G, the charge stored on a parasitic capacitor C o  charged by the voltage V DD  supplied through a precharging MOSFET Q 11  is discharged through that MOSFET of the logic circuit block to which the input signal is applied. During this period, called a sampling period, a signal φ&#39; is applied to the gate of the MOSFET Q 31  and turns on the FET Q 31  to drop the output of the decoder circuit, i.e. to short-circuit the word line output WL to the ground level until MOSFET Q 31  becomes cut off. By this arrangement, even if a control pulse φ (e.g., a chip enable signal or a clock signal) is applied to the drain of a word line selecting MOSFET Q 21  immediately after the precharge of the capacitor C o , the decoder does not cause a malfunction and an output signal is provided only after the signal φ&#39; becomes lower than the threshold voltage V th  of the MOSFET Q 31 . Therefore, if the time constants of the applied signal φ&#39; and the capacitor C o  are determined to be the same, the decoder causes no malfunction and the speed-up of accessing becomes possible. Naturally, the FET Q 31  can discharge any charge stored on the word line WL (due to parasitic capacitance) in the address selection operation by a CE pulse applied to the gate thereof. Here, it will be noted that the CE pulse has a different timing from that of the applied signal φ&#39;. 
     Next, an embodiment of this invention will be described referring to FIG. 3. In FIG. 3, a timing pulse generator circuit T is connected through an inverter consisting of MOSFETs Q 22  and Q 23  to the gate of a word line grounding MOSFET Q 8  for controlling the gate of the FET Q 8 . The timing pulse generator circuit T includes a ratioless circuit consisting of a precharging MOSFET Q 25  having a drain applied with the voltage V DD  and a MOSFET Q 26  receiving a signal of the same level as that of the address pulse, and an inverter consisting of MOSFETs Q 27  and Q 28  for inverting the output of the ratioless circuit. 
     In the operation of the address non-selective mode, the capacitor C o  is charged by a precharging signal P and at the same time the MOSFETs Q 25  and Q 28  of the timing pulse generator circuit T are also turned on by a similar signal P. Then, the gate of the FET Q 23  is at ground level and this FET Q 23  is turned off. Here, the gate level of the FET Q 8  is at a high level by the source voltage V DD  supplied through the FET Q 22 , the gate of which is opened by the terminal voltage of the capacitor C o , and hence the FET Q 8  is turned on. Thus, the word line WL is grounded to keep it at the ground (GND) level. 
     Next, an address signal is applied to at least one of the MOSFETs Q 2  to Q 6  of the logic block to drive the above-mentioned one MOSFET into the &#34;on&#34; state. At that time, the FET Q 26  is also turned on by a similar signal VIN to ground the output line. Thus, the charge stored in a parasitic capacitance C p  &#39; is discharged through the conducting FET Q 26  with a time constant determined by the on-resistance of MOSFET Q 26  and the capacitance C&#39;. The gate of the FET Q 28  is at GND level and the FET Q 28  is turned off. Thus, the FET Q 23  is turned on. Here, however, since the gate of the FET Q 8  is applied with an operating voltage V DD  through the FET Q 22  until the gate level of the FET Q 22  which is determined by the terminal voltage of the discharging capacitor C o  becomes lower than the threshold voltage V th  of the MOSFET Q 22 , the FET Q 8  remains in the &#34;on&#34; state during the period when the output of the generator T is disabled and, simultaneously, the terminal voltage of capacitor C o  is at the threshold voltage V th  or greater. As a result, the word line WL remains to be grounded through the &#34;on&#34; state of the FET Q 8  and hence is held at the GND level. This will also be understood from the operation timing chart of FIG. 5. 
     On the other hand, when the capacitor C o  is precharged after an address signal is applied to either of the gates of the MOSFETS Q 2  to Q 6 , a common MOSFET may be connected between the sources of MOSFETs Q 2  to Q 6  and ground and be supplied with a pulse P at its gate. The timing pulse generator circuit T may be used in common to a plurality of decoder circuits with MOS FETs Q 22  and Q 23  as shown in FIG. 3. 
     As has been described above, the MOSFET Q 8  is held in the &#34;on&#34; state by the timing pulse generator circuit T which is constructed to have the same discharge time constant for capacitor C p  &#39; as that for capacitor C o  in the logic circuit during its manufacturing process until the MOSFETs Q 26 , Q 2  to Q 6  and Q 7  have all turned off consequently, MOSFET Q 8  holds the output level of the word line at the GND level, thus, preventing the word line from floating. Therefore, a malfunction never occurs in the present circuit. Further, even though such a timing pulse generator cicuit is provided, there is no need for increasing the transconductance g m  of the MOSFETs which constitute the logic circuit. Thus, the degree of integration per chip does not decrease. Yet further, since it becomes unnecessary to await the application of the CE pulse until the full discharge of the capacitor, the timing of inputting or applying the CE pulse for the initiation of readout can be made earlier, thus providing a short access time. 
     FIG. 4 shows a circuit diagram of 5-bit decoders according to another embodiment of this invention, in which a pair of decoder circuits are coupled considering the fact that a memory circuit such as a RAM generally uses a plurality of similar decoder circuits consisting of logic gates. 
     In the figure, a pair of decoder circuits having a structure similar to that of FIG. 1 are coupled in parallel. One end of each of capacitors C o  and C o  &#39; connected, respectively, to the gate of grounding MOSFETs Q 8  &#39; and Q 8  so as to apply the terminal voltages of the capacitors C o  and C o  &#39; to the grounding MOSFETs for the word lines of the different decoder circuits. 
     The operation of this circuit will be described referring to the operational waveforms of FIG. 5. As is the case with the decoder of a dynamic drive type RAM, a first pulse called the precharging signal P is applied to the gates of the MOSFETs Q 1  and Q 1  &#39; preceding the application of an address signal. Then, the capacitors C o  and C o  &#39; are charged up at the supply voltage V DD . Now, assuming that the word line WL1 of the upper MOS logic circuit is selected, i.e. all the MOSFETs Q 2  to Q 6  are turned off after precharging, no input is applied to the input terminal I IN  of the gate circuit G and a second pulse called the address signal is supplied to the input terminal I IN  &#39; of the gate circuit G&#39; for the non-selected word line WL2. At this time, the first pulse for the dynamic drive has disappeared from the gates of the MOSFETs Q 1  and Q 1  &#39;. Thus, the capacitor C o  is held to be charged up while the other capacitor C o  &#39; is discharged through a logic gate FET applied with the second pulse A&#39;, B&#39;, . . . or E&#39; among the logic gate FETs Q 2  &#39; to Q 6  &#39;. Then, the MOSFET Q 8  &#39; is turned on by the charge stored on the capacitor C o  to ground the source of the MOSFET Q 7  &#39;. The non-selected output word line WL2 is grounded in this manner and hence a signal of a logic &#34;O&#34; is supplied to the next stage MOS circuit by a third control pulse, e.g. a chip enable (CE) signal, applied to the drain of the MOSFET Q 7  &#39; even when the capacitor C o  &#39; has not yet fully discharged and the malfunction is prevented. 
     The MOSFET Q 8  is kept in the &#34;on&#34; state until the charge stored on the capacitor C o  &#39; is discharged below the threshold voltage V th , but thereafter it is turned off. Therefore, when a third pulse CE is supplied to the drain of the MOSFET Q 7  in this state, a signal of a logic &#34;l&#34; is obtained from the word line WL1 on the source side of the MOSFETs Q 7  to achieve the address selection. 
     Next, when neither of the word lines WL1 and WL2 of the MOS logic circuit is selected (non-selection mode), a second (address) pulse is supplied to the input terminals I IN  and I IN  &#39; of the gate circuits G and G&#39; and at least each one of the MOSFETs Q 2  to Q 6  and the MOSFETs Q 2  &#39; to Q 6  &#39; is turned on. Here, the first pulse has disappeared from the gates of the MOSFETs Q 1  and Q 1  &#39;. Then, the precharged capacitors C o  and C o  &#39; are both discharged. The MOSFETs Q 8  and Q 8  &#39; are both turned on by the charge stored on the capacitors C o  and C o  &#39; similar to the MOSFETs Q 7  and Q 7  &#39;. These MOSFETs Q 8  and Q 8  &#39; retain the &#34;on&#34; state until the terminal voltages of the capacitors C o  &#39; and C o  decrease below the respective threshold voltages V th . Thus, the MOSFETs Q 8  and Q 8  &#39; are turned on, to ground the word lines WL1 and WL2 of the MOSFETs Q 7  and Q 7  &#39; until the MOSFETs Q 7  and Q 7  &#39; have been turned off. Thus, a third pulse CE may be applied to the drains of the MOSFETs Q 7  and Q 7  &#39;  even during the discharging period. In this case, signals of logic &#34;O&#34; are obtained on the respective word lines. Thus, the MOS circuit of the next stage never causes malfunction. 
     Further, in the circuit of FIG. 4, the MOSFETs Q 8  and Q 8  &#39; for grounding the word lines can be driven by the use of the charge stored on the capacitors C o  &#39; and C o  of the other part of the pair of decoders. Therefore, the prescribed objects can be achieved only by simple connections without complicating the circuit structure. 
     It will be apparent that the concept of the present invention can be applied to the read only memories (ROM) as well as to the RAMs. 
     In the above description, by way of example, MOSFETs are used as one kind of metal-insulator-semiconductor MISFETs. Therefore it should be understood that this invention is applicable to the case of using MISFET components other than MOS components.