Abstract:
An apparatus and method for determining a linear position from a linear variable differential transformer (LVDT) including a primary coil driven by an excitation signal, and two secondary coils coupled to two correlated signals. The method includes converting the correlated signals to a digital estimate, for each of the correlated signals, and evaluating an amplitude of the correlated signals to determine the linear position. The process of converting the correlated signals comprises comparing the correlated signal to an analog feedback signal to generate a comparison result and incrementally adjusting the digital estimate in response to sampling the comparison result at an estimation frequency. The converting process also includes converting the digital estimate to the analog feedback signal, collecting a digital estimate history at a sample frequency that is a binary multiple of the excitation frequency, and analyzing the digital estimate history to determine the amplitude substantially near the excitation frequency.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present application is related to concurrently filed U. S. patent application Ser. No. (2507-7532US) (22154-US) and entitled DIGITAL METHOD AND APPARATUS FOR RESOLVING SHAFT POSITION.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     This invention relates generally to determining linear position and, more particularly, to using digital means for determining linear position.  
         [0004]     2. Description of Related Art  
         [0005]     This invention relates to determining linear position by using the electrical outputs of a a Linear Variable Differential Transformer (LVDT). It may be desireable to determine a linear position for many applications. For example, actuation systems on aircraft or rocket motors. One method of doing this is to use a LVDT to sense the position. The LVDT may use a sinusoidal excitation and measurement of two inductively coupled output signals. LVDTs have one primary winding and two secondary windings. The two secondary windings are mechanically arranged so an excitation signal on the primary winding will proportionally couple onto the secondary windings based on the position of a ferrous core. By measuring the voltages on the secondary windings it is possible to determine the linear position of the LVDT.  
         [0006]     These output signals from the two secondary windings are generally analog signals, which may require a significant amount of analog electronics to evaluate the signal amplitudes and derive the shaft position. As a result, many proposals use analog-to-digital converters to convert the analog signals to digital signals, which may then be manipulated digitally to determine the respective amplitudes and calculate arithmetic functions to determine the shaft position. However, even these solutions may require complex analog-to-digital converters, and complex arithmetic engines for determining the signal amplitudes.  
         [0007]     There is a need for a method and apparatus that reduces the complexity and number of analog components used in determining linear position by using simple analog components coupled to flexible digital logic and digital signal processing.  
       BRIEF SUMMARY OF THE INVENTION  
       [0008]     The present invention reduces the complexity and number of analog devices needed to resolve linear position.  
         [0009]     An embodiment of the present invention comprises an apparatus for determining a linear position of a LVDT. The apparatus includes a first signal analyzer, a second signal analyzer, and a result calculator. The LVDT includes an excitation input coupled to an excitation signal with an excitation frequency, a first positional output coupled to an analog input of the first signal analyzer, and a second positional output coupled to an analog input of the second signal analyzer. Each of the first signal analyzer and the second signal analyzer includes a comparator, a digital estimator, a digital-to-analog converter, and an amplitude analyzer. The comparator is configured for comparing the analog input to an analog feedback signal and generating a comparison result. The digital estimator uses the comparison result to modify a digital estimate by an incremental adjustment amount at an estimation frequency in response to the comparison result. The digital estimate is converted to the analog feedback signal by the digital-to-analog converter. The amplitude analyzer collects a digital estimate history at a sample frequency that is a binary multiple of the excitation frequency and determines an amplitude of the digital estimate substantially near the excitation frequency. With the amplitudes determined, the result calculator evaluates the amplitude for each of the first signal analyzer and second signal analyzer to generate the linear position.  
         [0010]     Another embodiment of the present invention comprises a method for determining a linear position. The method comprises resolving an excitation signal at an excitation frequency into at least two correlated signals, converting the at least two correlated signals to a digital estimate for each of the correlated signals, and evaluating an amplitude of the digital estimate of the correlated signals to determine the linear position. The process of converting the correlated signals comprises comparing the correlated signal to an analog feedback signal to generate a comparison result and incrementally adjusting the digital estimate in response to sampling the comparison result at an estimation frequency. The converting process also includes converting the digital estimate to the analog feedback signal, collecting a digital estimate history at a sample frequency that is a binary multiple of the excitation frequency, and analyzing the digital estimate history to determine the amplitude of the digital estimate substantially near the excitation frequency.  
         [0011]     Yet another embodiment, in accordance with the present invention comprises a method of determining a linear position. This method includes resolving an excitation signal at an excitation frequency into a first signal and a second signal, converting the first signal to a first digital estimate, converting the second signal to a second digital estimate, evaluating a first amplitude and a second amplitude to determine the linear position. Converting the first signal includes comparing the first signal to a first analog feedback signal to generate a first comparison result. Converting the first signal also includes incrementally adjusting the first digital estimate in response to sampling the first comparison result at an estimation frequency, converting the first digital estimate to the first analog feedback signal, and analyzing the first digital estimate to determine the first amplitude of the first signal substantially near the excitation frequency. Similarly, converting the second signal includes comparing the second signal to a second analog feedback signal to generate a second comparison result. Converting the second signal also includes incrementally adjusting the second digital estimate in response to sampling the second comparison result at the estimation frequency, converting the second digital estimate to the second analog feedback signal, and analyzing the second digital estimate to determine the second amplitude of the second signal substantially near the excitation frequency. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]     In the drawings, which illustrate what is currently considered to be the best mode for carrying out the invention:  
         [0013]      FIG. 1  is a schematic depiction of a linear variable differential transformer (LVDT);  
         [0014]      FIG. 2A  illustrates a representative excitation waveform for input to a LVDT;  
         [0015]      FIG. 2B  illustrates a representative first positional output waveform from a LVDT when the excitation input is the excitation waveform of  FIG. 2A  and the core of the LVDT is moving at a constant rate;  
         [0016]      FIG. 2C  illustrates a representative second positional output waveform from a LVDT when the excitation input is the excitation waveform of  FIG. 2A  and the core of the LVDT is moving at a constant rate;  
         [0017]      FIG. 3  is a schematic depiction of a representative embodiment of the present invention including a LVDT;  
         [0018]      FIG. 4  is a schematic depiction of a representative embodiment of a signal analyzer according to the present invention;  
         [0019]      FIG. 5  is a schematic depiction of a representative embodiment of a digital converter according to the present invention;  
         [0020]      FIG. 6  is a schematic depiction of a representative embodiment of a digital-to-analog converter according to the present invention;  
         [0021]      FIG. 7A  illustrates a representative pulse width modulation signal for generating a sine wave;  
         [0022]      FIG. 7B  illustrates a sine wave that may be produced by low pass filtering the pulse width modulation signal of  FIG. 7A ;  
         [0023]      FIG. 8  is a schematic depiction of a representative embodiment of an excitation signal generator according to the present invention; and  
         [0024]      FIG. 9  is a schematic depiction of a representative embodiment of an amplitude analyzer according to the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0025]     The present invention reduces the complexity and number of analog devices needed to resolve linear position obtained from a linear variable differential transformer (LVDT).  
         [0026]     In the following description, circuits and functions may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. Conversely, specific circuit implementations shown and described are exemplary only and should not be construed as the only way to implement the present invention unless specified otherwise herein. Additionally, block definitions and partitioning of logic between various blocks is exemplary of a specific implementation. It will be readily apparent to one of ordinary skill in the art that the present invention may be practiced by numerous other partitioning solutions. For the most part, details concerning timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present invention and are within the abilities of persons of ordinary skill in the relevant art.  
         [0027]     In this description, some drawings may illustrate signals as a single signal for clarity of presentation and description. It will be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, wherein the bus may have a variety of bit widths and the present invention may be implemented on any number of data signals including a single data signal. Furthermore, signals may be referred to as asserted and negated. Those of ordinary skill in the art will recognize that in most instances, the selection of asserted or negated may be arbitrary and the invention could be implemented with the opposite states for such signals.  
         [0028]      FIG. 1  illustrates a LVDT  100 . The LVDT  100  includes an excitation input  110  attached to a primary coil  102  and at least two secondary coils  104  attached to modulation outputs ( 120  and  130 ). The LVDT also includes a ferrous core  115 , which moves linearly relative to the primary coil  102  and secondary coils  104 . Generally, the core may be attached to a linkage or other means for mechanical linking (not shown) to external parts (not shown). The primary coil  102  and secondary coils  104  include windings positioned such that when an electrical signal is induced in the primary coil  102  inductive coupling produces electrical signals in the secondary coils  104  windings. The secondary coils  104  may be positioned such that, the amount of inductive coupling to each secondary coils  104  may be different and dependent on the position of the core  115 . Thus, by measuring the voltages on the secondary coils  104  it is possible to determine the linear position of the core  115  and, as a result, the linear position of a linkage attached thereto. Throughout this description, the modulation outputs ( 120  and  130 ) may also be referred to as correlated signals ( 120  and  130 ) or as a first positional output  120  and a second positional output  130 .  
         [0029]     By way of example,  FIG. 2A  illustrates an excitation signal  112  that may be applied to the excitation input  110  coupled to the primary coil. In this example, the excitation signal  112  is a sinusoidal signal driven through the primary coil, which inductively induces modulated signals in the correlated outputs ( 120  and  130 ).  FIGS. 2B and 2C  illustrate the modulation outputs that may be present when the primary coil  102  is moving at a substantially constant rate from one extreme to the other. A first signal  122  on the first positional output  120  includes a modulated amplitude that is modulated along an increasing envelope  106  having a substantially linear rate corresponding to the movement of the core  115 . Similarly, a second signal  132  on the second positional output includes a modulated amplitude that is modulated along a decreasing envelope  108  having a substantially linear rate corresponding to the movement of the core  115 .  FIGS. 2A, 2B , and  2 C are simple examples illustrating general operation with a simple constant linear movement. Those of ordinary skill in the art will recognize that the envelopes ( 106  and  108 ) representing movement of the core  115  may be complex, and perhaps vibratory waveforms. As a result, the excitation frequency should be substantially higher than an expected rate of change of the core  115  displacement. For example, the excitation signal  112  may have an excitation frequency generally in the range of about 1 to 10 kHz, but the scope of the invention is not limited to this range.  
         [0030]      FIG. 3  illustrates a representative embodiment of the present invention. The excitation input  110  couples to the primary coil of the LVDT  100 . The secondary coils of the LVDT  100  are coupled to a first positional output  120  and a second positional output  130 . Each of the first positional output  120  and the second positional output  130  are coupled to a signal analyzer ( 200 A and  200 B). Each signal analyzer ( 200 A and  200 B) generates an amplitude ( 290 A and  290 B) for its respective input signal.  
         [0031]     A result calculator  300  receives the outputs from the signal analyzers ( 200 A and ( 200 B) to calculate the linear position  340 . The position of the core  115  may be determined by the difference between the two secondary windings divided by their sum. Thus, the result calculator  300  may comprise an arithmetic unit configured for calculating the equation (A−B)/(A+B) wherein A represents the amplitude  290 A from the first signal analyzer  200 A, B represents the amplitude  290 B from the second signal analyzer  200 B, and the calculation result represents the linear position  340 .  
         [0032]     The result calculator also may comprises dedicated circuitry for calculating the linear position as illustrated in  FIG. 3 . In  FIG. 3 , a subtractor subtracts the second amplitude  290 B from the first amplitude  290 A. Similarly, an adder add the first amplitude  290 A and second amplitude  290 B. A divider  320  divides the result from the subtractor by the result from the adder to determine the linear position  340 . The final result is a digital representation of the linear position  340 . An optional filter  336  may be used to filter the linear position  340  with a conventional digital filtering algorithm to further reduce noise and generate a filtered linear position  350 .  
         [0033]      FIG. 4  illustrates a representative embodiment of the signal analyzer  200 . The signal analyzer  200  is the same for both the first signal analyzer  200 A and the second signal analyzer  200 B. Thus, the first positional output  120  and the second positional output  130  couple to the input signal  205  of their respective signal analyzers ( 200 A and  200 B). Similarly, the amplitude  290  output from the signal analyzer  200  couples to the corresponding amplitude output of the first signal analyzer  200 A and the second signal analyzer  200 B.  
         [0034]     In the signal analyzer  200 , the input signal  205  couples to a digital converter  210 , which converts the analog input signal to a digital estimate  240 . The digital estimate  240  is used by an amplitude analyzer  400  to generate the amplitude of the input signal  205 .  
         [0035]     The amplitude analyzer  400  repeatedly samples the digital estimate  240  using the sample clock  405  to create a digital estimate history, which may be used to convert the time varying digital estimate  240  from the time domain to the frequency domain. The outputs of the amplitude analyzer  400  is a digital signal indicating the amplitude  290  of the modulated signal substantially near the excitation frequency. In other words, the output of the first amplitude analyzer is a digital value indicating the amplitude  290 A of the first positional output  120  substantially near the excitation frequency and the output of the second amplitude analyzer is a digital value indicating the amplitude  290 B of the second positional output  130  substantially near the excitation frequency. The amplitude analyzer  400  is explained more fully below.  
         [0036]     A digital converter  210  is used to provide a continuously available estimate of the input signal  205  accurate to within one bit. A continuously available estimate may be advantageous in that it does not have the sample and hold characteristics of many conventional analog-to-digital converters and may not need to be synchronized to other clocks within the system.  
         [0037]     Details of a representative embodiment of the digital converter  210  are illustrated in  FIG. 5 . In the digital converter  210 , the input signal  205  couples to a simple fast analog comparator  220 . The other input of the analog comparator  220  is coupled to an analog feedback signal  260 . The comparison result  225  is a digital signal that may be asserted if the input signal  205  is larger than the analog feedback signal  260  and negated if the input signal  205  is smaller than the analog feedback signal  260 .  
         [0038]     A digital estimator  230 , which is controlled by an estimation clock  215 , analyzes the comparison result  225  to update the digital estimate  240 . The update rate at which the estimation clock  215  runs is selected such that the estimate will always be able to track the input signal  205 . Thus, the estimation frequency may be a substantially higher frequency than the excitation frequency. For example, and not limitation, the estimation clock  215  may run at or above one Mhz for an excitation frequency of about 10 Khz.  
         [0039]     The digital converter  210  is a feedback loop that begins by selecting a starting digital estimate  240  of the signal amplitude, which is stored in an estimate register  238 . The comparison result  225  is used by adjustment logic  232  to determine whether the digital estimate  240  should be improved by modifying the digital estimate  240  by an incremental adjustment amount. Thus, based on the comparison result  225 , the adjustment logic  232  may generate an adjustment signal  236  for incrementing, decrementing, or maintaining the digital estimate  240 . The resulting new digital estimate couples to a digital-to-analog converter  250 , which generates the analog feedback signal  260  for comparison in the comparator  220 . The feedback loop continues until the digital estimate  240  is an accurate representation of the input signal  205 . Then, as the input signal  205  changes, the digital converter  210  can easily track the changes through the adjustment logic  232  and feedback loop.  
         [0040]     For many applications, this method may be unacceptably slow. However, the present invention takes advantage of the A Priori knowledge that the input signal will be substantially a sinusoidal wave of known frequency and limited, but varying, amplitude. The update rate (i.e., the estimation frequency) is selected such that the estimate will always be able to accurately track the input signal. As a result, this method is faster than other conversion methods, provides an estimate accurate to within one bit, and provides an estimate that is continuously available to other circuitry in the system.  
         [0041]     The digital-to-analog converter  250  may be implemented in a variety of ways known to those of ordinary skill in the art. One representative embodiment of the digital-to-analog converter  250  that may be simple to implement is illustrated in  FIG. 6 . The digital estimate  240  is used by a pulse-width modulator  252  (PWM), which converts the digital estimate  240  into a pulse-width modulated estimate  254 , which is a series of pulses with varying duty cycles corresponding to the digital estimate values. An analog filter  256  filters the pulse-width modulated estimate  254  to generate the analog feedback signal  260  to represent variations in the digital estimate  240 .  
         [0042]      FIG. 7A  illustrates an example pulse-width modulated signal  254 . The width of the pulses (i.e., the duty cycle) is varied in proportion to the magnitude of the digital estimate to generate the pulse train with varying pulse widths. As a result, the pulse-width modulated estimate  254  includes a varying amount of energy, which corresponds to the high portion of the pulses. Therefore, the pulse-width modulated estimate  254  may be filtered by a simple low pass analog filter  256  to generate the analog feedback signal  260  (shown as signal plot  285  in  FIG. 7B ).  
         [0043]     Returning to  FIG. 3 , the excitation input  110  may be configured as a sine wave with an excitation frequency. A simple excitation generator  500  may be used for generating the excitation input  110 , as illustrated in  FIG. 8 . An amplitude generator  510  creates a digital excitation signal  520  with values that vary at a generation frequency. The digital excitation signal  520  is used by a PWM  252 ′, which converts the digital excitation signal  520  into a pulse-width modulated signal  530 . An analog filter  256 ′ filters the pulse-width modulated signal  530  to generate the excitation input  110 .  
         [0044]     The function of the amplitude generator  510  including the pulse-width modulator  252 ′ and analog filter  256 ′ is similar to what was described for the digital-to-analog converter  250  of  FIGS. 6, 7A  and  7 B. However, for the excitation generator  500  the amplitude generator  510  creates the desired signal. Thus, in  FIG. 8  the amplitude generator  510  creates a digital excitation signal  520 , which is a time varying digital representation for emulating a sine wave. The amplitude generator  510  may be some type of arithmetic unit for calculating sine waves, or it may be a simple look-up table with the proper amplitudes for generating a sine wave.  
         [0045]     Returning to  FIG. 4 , the amplitude analyzer  400  converts the time varying digital estimate  240  from the time domain to the frequency domain. Generally, converting a time domain signal to the frequency domain generates a function with amplitudes at a variety of frequencies. The output of the amplitude analyzer  400  is a digital signal indicating the amplitude  290  of the modulated signal substantially near the excitation frequency. A number of implementation for finding the amplitude  290  of the modulated signal substantially near the excitation frequency may be used, such as, for example, implementing a conventional Fast Fourier Transform (FFT). However, a simpler implementation may be used for the present invention because only the amplitude  290  at the excitation frequency is needed.  
         [0046]      FIG. 9  illustrates an implementation of an amplitude analyzer  400 . A sample clock  405  running at a sample frequency feeds a history shift register  420  configured to sample and shift values of the digital estimate  240 . Thus, the history shift register  420  generates a digital estimate history ( 425 ) N bits long.  
         [0047]     The digital estimate history  425  is coupled to a set of summing units  430  in a butterfly pattern recognizable to those of ordinary skill in the art in performing a Discrete Fourier Transform (DFT), except that only the calculations necessary to determine the amplitude at the excitation frequency are performed. A first set of difference units  435  perform subtractions on the results from the first set of summing units. A set of multipliers  440  multiply the subtraction results from the first set of difference units by the appropriate constants for a DFT. A second set of difference units  445  perform subtractions on the results from the multipliers  440 . A third set of difference units  450  perform subtractions on the results from the second set of difference units  445 . A set of squaring units  455  square the absolute value of the results from the third set of difference units  450 . A summing unit  460  adds the results from the set of squaring units  455 , and a square root unit  465  calculates the square root of the result from the summing unit  460  to arrive at the final amplitude  290 .  
         [0048]     The number of bits N in the digital estimate history  425  may be chosen to be a binary multiple. In the example of  FIG. 9 , the number of bits is chosen as  16  to generate the digital estimate history  425  of signals td 0 -td 15 . In addition, the sample frequency of the sample clock  405  is chosen to correspond to the number of bits such that the sample frequency is a binary multiple of the excitation frequency. Thus, in the example of  FIG. 9 , the sample frequency is set at 16 times the excitation frequency such that digital estimate history  425  comprises samples of one full cycle of the excitation frequency.  
         [0049]     In operation, the implementation of  FIG. 9  performs a limited DFT in that it only calculates the amplitude at the excitation frequency. For each sample point, the limited DFT is taken to provide the instantaneous amplitude of the input signal at the base excitation frequency. As each sample is taken, the new value is operated on along with the previous 15 samples using the limited DFT.  
         [0050]     Those of ordinary skill in the art will recognize that embodiments of the amplitude analyzer  400  may encompass other bit widths and sample rates for the limited DFT. For example, and not limitation, the limited DFT may use a sample frequency that is of  2   N  times the sample frequency wherein N may be in a range from 2 to 10. In addition, as stated earlier, the amplitude analyzer  400  also encompasses implementations that perform a full DFT or FFT to determine the amplitude of the digital estimate at the excitation frequency.  
         [0051]     Although this invention has been described with reference to particular embodiments, the invention is not limited to these described embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods that operate according to the principles of the invention as described.