Abstract:
An output circuit is provided for outputting, based on a first drive signal, an output signal with an amplitude smaller than a source voltage, comprising: a first type MOS transistor whose gate is impressed with a first drive signal and whose drain outputs a signal; a second type MOS transistor whose gate is impressed with a second drive signal and whose drain outputs a signal; and feedback circuits generating the second drive signal by feeding an output signal obtained by synthesizing the signal outputted by the first type MOS transistor and the signal outputted by the second type MOS transistor back to the gate of the second type MOS transistor.

Description:
RELATED APPLICATIONS 
   This applications claims priority to Japanese Patent Application Nos. 2003-158252 filed Jun. 3, 2003 and 2004-011396 filed Jan. 20, 2004 which are hereby expressly incorporated by reference herein in their entirety. 
   BACKGROUND 
   1. Field of the Invention 
   This invention relates to an output circuit for outputting a signal to an external circuit, and more particularly to a semiconductor integrated circuit with such an output circuit built-in. 
   2. Related Art 
   Interface signals are available at very high speed in recent years, and measures to cope with interface signal noise and EMI (electromagnetic interference) have been needed. As a countermeasure for such noise and EMI, there is implemented a measure to reduce an amplitude of an interface signal. However, as described in Japanese Published Patent No. Hei-6-326591 (Page 1, FIG. 1), when the amplitude of a signal is lowered by reducing a source voltage supplied to an output circuit, a power circuit becomes complicated. Further, there is a risk that reference levels of signals between a circuit of a high source voltage type and a circuit of a low source voltage type may not be in agreement. 
   Furthermore, there is a case where a differential signal is used as an interface signal.  FIG. 18  is a diagram showing an example of a prior art differential signal output circuit. A differential signal output circuit  81  shown in  FIG. 18  is a circuit for outputting, based on one input signal J 1 , a pair of differential signals of a first output signal J 4  and a second output signal J 4  bar. However, in the differential signal output circuit  81 , a drive signal J 3  is delayed from a drive signal J 2  by a delay time of an inverter INV  82 , hence, the first output signal J 4  and the second output signal J 4  bar have skewing. 
   A differential signal output circuit capable of reducing the skewing mentioned above is also used.  FIG. 19  is a diagram showing another example of a conventional differential signal output circuit. A differential signal output circuit  91  shown in  FIG. 19  is a circuit for outputting, based on one input signal K 1 , a pair of differential signals of a first output signal K 4  and a second output signal K 4  bar. The interface signal output circuit  91  is, by comparison to the interface signal output circuit  81  (refer to  FIG. 1 ), further constituted by a capacitor C 91 , and by this capacitor C 91 , a drive signal K 2  is delayed to reduce skewing of drive signals K 2  and K 3 , thereby decreasing skewing of the first output signal K 4  and the second output signal K 4  bar. 
   Nevertheless, in the interface signal output circuit  91 , due to a scattering of a manufacturing process, an electrostatic capacity required to reduce the skewing of the first output signal K 4  and the second output signal K 4  bar may not be in agreement with an electrostatic capacity of the capacitor C 91 . As a result, there were cases where yield dropped or a product defect occurred at a client&#39;s side. Also, it was necessary to be stringent about allowing margins of a source potential fluctuation and a temperature fluctuation, sometimes leading to a yield drop. 
   In view of the above-mentioned considerations, it is a first object of this invention to make high-speed operation possible through a simple circuit configuration in an output circuit for outputting signals of a small amplitude. Further, it is a second object of this invention to prevent a yield drop and the like in a differential signal output circuit for outputting a pair of differential signals. Still further, it is a third object of this invention to provide a semiconductor integrated circuit having such an output circuit built-in. 
   SUMMARY 
   To solve the above-mentioned problems, an output circuit according to a first aspect of this invention is an output circuit for outputting, based on a first drive signal, an output signal of an amplitude smaller than a source voltage, comprising: a first MOS transistor of a first type which outputs a signal from its drain as a first drive signal is impressed on its gate; a second MOS transistor of a second type which outputs a signal from its drain as a second drive signal is impressed on its gate; and a feedback circuit generating a second drive signal by feeding an output signal obtained by synthesizing the signal outputted by the first MOS transistor and the signal outputted by the second MOS transistor back to the gate of the second MOS transistor. 
   At this point, the feedback circuit may be adapted to include a passive element connected to a first terminal at a node of the drain of the first MOS transistor and the drain of the second MOS transistor as well as a buffer circuit buffering a signal supplied from a second terminal of the passive element. 
   The output circuit according to a second aspect of this invention is an output circuit for outputting, based on the first drive signal, an output signal having an amplitude smaller than the source voltage, comprising the first MOS transistor of the first type which outputs a signal from its drain as the first drive signal is impressed on its gate; the second MOS transistor of the second type which outputs a signal from its drain as the second drive signal is impressed on its gate; and the feedback circuit generating the second drive signal by inverting an output signal obtained by synthesizing the signal outputted by the first MOS transistor and the signal outputted by the second MOS transistor and feeding the signal back to the gate of the second MOS transistor. 
   At this point, the feedback circuit may be adapted to include a passive element connected to the first terminal at the node of the drain of the first MOS transistor and a source of the second MOS transistor and an inverter inverting a signal supplied from the second terminal of the passive element. 
   The output circuit according to a third aspect of this invention is an output circuit for outputting, based on the first and the second drive signal constituting the pair of differential signals, the first and the second output signal, having an amplitude smaller than the source voltage and constituting the pair of differential signals, comprising: the first MOS transistor of the first type which outputs a signal from its drain as the first drive signal is impressed on its gate; the second MOS transistor of the second type which outputs a signal from its drain as a third drive signal is impressed on its gate; a first feedback circuit generating the third drive signal by inverting the first output signal obtained by synthesizing the signal outputted by the first MOS transistor and the signal outputted by the second MOS transistor and feeding the signal back to the gate of the second MOS transistor; a third MOS transistor of the first type which outputs a signal from its drain as the second drive signal is impressed on its gate; a fourth MOS transistor of the second type which outputs a signal from its drain as a fourth drive signal is impressed on its gate; and a second feedback circuit generating the fourth drive signal by feeding the second output signal obtained by synthesizing the signal outputted by the third MOS transistor and the signal outputted by the fourth MOS transistor back to the gate of the second MOS transistor. 
   The output circuit according to a fourth aspect of this invention is an output circuit for outputting, based on the first and the second drive signal constituting the pair of differential signals, the first and the second output signal having an amplitude smaller than the source voltage and constituting the pair of differential signals, comprising: the first MOS transistor of the first type which outputs a signal from its drain as the first drive signal is impressed on its gate; the second MOS transistor of the first type which outputs a signal from its drain as the third drive signal is impressed on its gate; the first feedback circuit generating the third drive signal by inverting the first output signal obtained by synthesizing the signal outputted by the first MOS transistor and the signal outputted by the second MOS transistor and feeding the signal back to the gate of the second MOS transistor; the third MOS transistor of the first type which outputs a signal from its drain as the second drive signal is impressed on its gate; the fourth MOS transistor of the first type which outputs a signal from its drain as the fourth drive signal is impressed on its gate; and the second feedback circuit generating the fourth drive signal by inverting the second output signal obtained by synthesizing the signal outputted by the third MOS transistor and the signal outputted by the fourth MOS transistor and feeding the signal back to the gate of the fourth MOS transistor. 
   The output circuit according to the third or the fourth aspect of this invention may be adapted to further include a first inverting circuit inverting an input signal and outputting the first drive signal and the second inverting circuit inverting the first drive signal and outputting the second drive signal. 
   The output circuit according to a fifth aspect of this invention is a circuit for outputting, based on the first and the second drive signal constituting the pair of differential signals, the first and the second output signal constituting the pair of differential signals, comprising: a first and a second signal level conversion circuit respectively converting the first and the second drive signal to a signal of a prescribed level and outputting the signal; a first differential circuit for outputting a signal corresponding to a difference between a signal outputted by the first signal level conversion circuit and a signal outputted by the second signal level conversion circuit; a second differential circuit for outputting a signal corresponding to a difference between a signal outputted by the second signal level conversion circuit and a signal outputted by the first signal level conversion circuit; a first output signal generating circuit generating a first output signal based on a signal outputted by the first differential circuit; and a second output signal generating circuit generating a second output signal based on a signal outputted by the second differential circuit. 
   At this point, the first or the second signal level conversion circuit may be adapted to include a single-end sense amplifier, the first or the second differential circuit may be adapted to include a current mirror type differential amplifier circuit, and the first or the second output signal generating circuit may be adapted to include an inverter. 
   Also, the invention may be adapted to further comprise the first inverting circuit inverting an input signal and outputting the first drive signal as well as the second inverting circuit inverting the first drive signal and outputting the second drive signal. 
   In that case, the invention may be adapted so that the first and the second inverting circuit operate upon receipt of power supply from a first and a second source potential, and that the first and the second signal level conversion circuit, the first and the second differential circuit, and the first and the second output signal generating circuit operate upon receipt of power supply from the first and the third source potential. 
   Or the invention may be adapted so that the first and the second inverting circuit operate upon receipt of power supply from the first and the second source potential, that the first and the second signal level conversion circuit operate upon receipt of power supply from the first and the third source potential, and that the first and the second differential circuit and the first and the second output signal generating circuit operate upon receipt of power supply from the first and a fourth source potential. 
   At this time, the invention may be adapted so that the third source potential is at a higher potential than the second source potential, and that the fourth source potential is at a higher potential than the third source potential. Or it may be adapted such that the third source potential is at a lower potential than the second source potential, and that the fourth source potential is at a lower potential than the third source potential. 
   Furthermore, a semiconductor integrated circuit according to this invention has any of the above-mentioned signal output circuits built-in. 
   According to the first to the fourth aspect of this invention, in an output circuit for outputting a signal of a small amplitude, through application of a negative feedback by using a feedback circuit, it is possible to achieve high-speed operation in terms of a simple circuit configuration. Further, according to the fifth aspect of this invention, in a differential signal output circuit for outputting a pair of differential signals, it is possible to prevent a yield drop and the like. Still further, in the pair of differential signals which are obtained according to the fifth aspect of this invention, even if fluctuations of a source voltage, operating temperature and process should occur, it is possible to maintain its eye pattern shape. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram showing a configuration of an output circuit according to a first embodiment of this invention; 
       FIG. 2  is a diagram showing a waveform of the output circuit shown in  FIG. 1 ; 
       FIG. 3  is a diagram showing a configuration of an output circuit according to a second embodiment of this invention; 
       FIG. 4  is a diagram showing a waveform of the output circuit shown in  FIG. 3 ; 
       FIG. 5  is a diagram showing a configuration of an output circuit according to a third embodiment of this invention; 
       FIG. 6  is a diagram showing a configuration of an output circuit according to a fourth embodiment of this invention; 
       FIG. 7  is a diagram showing a configuration of an output circuit according to a fifth embodiment of this invention; 
       FIG. 8  is a diagram showing a configuration of an output circuit according to a sixth embodiment of this invention; 
       FIG. 9  is a diagram showing a configuration of an output circuit according to a seventh embodiment of this invention; 
       FIG. 10  is a timing chart showing an operation of a differential signal output circuit shown in  FIG. 9 ; 
       FIG. 11  is a diagram showing a configuration of an output circuit according to an eighth embodiment of this invention; 
       FIG. 12  is a diagram showing a configuration of an output circuit according to a ninth embodiment of this invention; 
       FIG. 13  is a diagram showing a configuration of an output circuit according to a tenth embodiment of this invention; 
       FIG. 14  is a diagram showing a configuration of an output circuit according to a eleventh embodiment of this invention; 
       FIG. 15  is a diagram showing a configuration of an output circuit according to a twelfth embodiment of this invention; 
       FIG. 16  is a diagram showing a configuration of an output circuit according to a thirteenth embodiment of this invention; 
       FIG. 17  is a diagram showing a configuration of an output circuit according to a fourteenth embodiment of this invention; 
       FIG. 18  is a diagram showing a configuration example of a conventional differential signal output circuit; and 
       FIG. 19  is a diagram showing another configuration example of a conventional differential signal output circuit. 
   

   DETAILED DESCRIPTION 
   Preferred embodiments according to this invention will be described in detail below with reference to drawings, wherein like reference numerals designate identical or corresponding parts throughout to omit duplicate explanation. 
     FIG. 1  is a diagram showing a configuration of an output circuit according to a first embodiment of this invention. An output circuit  10  includes an n-channel transistor QN 10  to which a drive signal is supplied, a p-channel transistor QP 10  serially connected to the transistor QN 10 , an output terminal connected to drains of the transistor QP 10  and the QN 10  and a protection device  101 , and a buffer circuit  102  to which an output signal of the output circuit  10  is supplied through the protection device  101 . It is to be noted that the buffer circuit  102  consists of a 2-stage inverter connected in series. 
   A source of the transistor QP 10  is connected to a source potential V DD , and the source of the transistor QN 10  is connected to a source potential V SS  (to be set as a grounding potential in this embodiment). The protection device  101  is an element to protect an input of the buffer circuit  102  from static electricity impressed upon the output terminal, and, as the protection device  101 , for example, a resistance is used. An output signal of the output circuit  10  is supplied to input of the buffer circuit  102  through the protection device  101 , and a signal outputted by the buffer circuit  102  is supplied to a gate of the transistor QP 10 , whereby a self feedback circuit is formed. 
     FIG. 2  is a diagram showing a waveform of an output signal of an output circuit shown in  FIG. 1 . When a drive signal is at a low level, the transistor QN 10  is in an “off” state, and a potential of the output signal is nearly (V DD −V SS )/2. When the drive signal is at a high level, the transistor QN 10  is in an “on” state, and the potential of the output signal decreases to near the source potential V SS . Consequently, an amplitude of the output signal becomes a half swing which is approximately half of the source potential (V DD −V SS ). Further, this output circuit is capable of performing high-speed operation by operation of self feedback. 
   In this embodiment, it is possible to set the high level of the drive signal as the source potential V DD  and the low level of the drive signal as the source potential V SS . Or, the high level of the drive signal may be set as a potential other than the source potential V DD . In that case, the output circuit according to this embodiment will have a function as a level shifter, too. Now, the output signal of the output circuit  10  may be set to receive from an output of either of the inverters constituting the buffer circuit  102 . 
   Next, a second embodiment of this invention will be described. 
     FIG. 3  is a diagram showing a configuration of an output circuit according to the second embodiment of this invention. The output circuit includes a p-channel transistor QN 10  to a gate of which a drive signal is supplied, a n-channel transistor QP 10  serially connected to the transistor QN 10 , an output terminal connected to drains of the transistor QP 10  and the QN 10  and a protection device  101 , and a buffer circuit  102  to which an output signal of the output circuit  10  is supplied through the protection device  101 . 
   A source of the transistor QP 10  is connected to a source potential V DD , and the source of the transistor QN 10  is connected to a source potential V SS  (to be set as a grounding potential in this embodiment). An output signal of the output circuit is supplied to input of the buffer circuit  102  through the protection device  101 , and a signal outputted by the buffer circuit  102  is supplied to the gate of the transistor QP 10 , whereby a self feedback circuit is formed. 
     FIG. 4  is a diagram showing a waveform of an output signal of an output circuit shown in  FIG. 3 . When a drive signal is at a high level, the transistor QN 10  is in the “off” state, and a potential of the output signal is nearly (V DD −V SS )/2 due to a self feedback operation. When the drive signal is at a low level, the transistor QN 10  is in the “on” state, and the potential of the output signal increases to near the source potential V SS . Consequently, an amplitude of the output signal becomes a half swing which is approximately half of the source potential (V DD −V SS ). Further, this output circuit is capable of performing high-speed operation by the self feedback operation. 
   In this embodiment, it is possible to set the high level of the drive signal as the source potential V DD  and the low level of the drive signal as the source potential V SS . Or, the low level of the drive signal may be set as a potential other than the source potential V SS . In that case, the output circuit according to this embodiment will have a function as a level shifter, too. Now, the output signal of the output circuit may be set to receive from an output of either of the inverters constituting the buffer circuit  102 . 
   Next, a third embodiment of this invention will be described. 
     FIG. 5  is a diagram showing a configuration of an output circuit according to the third embodiment of this invention. The output circuit includes a n-channel transistor QN 10  to a gate of which a drive signal is supplied, a n-channel transistor QN 20  serially connected to the transistor QN 10 , an output terminal connected to drains of the transistor QP 10  and the QN 20  and a protection device  101 , and an inverter  103  to which an output signal of the output circuit  10  is supplied through the protection device  101 . 
   A drain of the transistor QN 20  is connected to the source potential V DD , and the source of the transistor QN 10  is connected to the source potential V SS  (to be set as a grounding potential in this embodiment). An output signal of the output circuit is supplied to input of the inverter  103  through the protection device  101 , and a signal outputted by the inverter  103  is supplied to a gate of the transistor QN 20 , whereby a self feedback circuit is formed. 
   When a drive signal is at a low level, the transistor QN 10  is in the “off” state, and a potential of the output signal is nearly (V DD −V SS )/2 due to the self feedback operation. When the drive signal is at a high level, the transistor QN 10  is in the “on” state, and the potential of the output signal decreases to near the source potential V SS . Consequently, an amplitude of the output signal becomes a half swing which is approximately half of the source potential (V DD −V SS ). Further, this output circuit is capable of performing high-speed operation by the self feedback operation. 
   In this embodiment, it is possible to set the high level of the drive signal as the source potential V DD  and the low level of the drive signal as the source potential V SS . Or, the high level of the drive signal may be set as a potential other than the source potential V SS . In that case, the output circuit according to this embodiment will have a function as a level shifter, too. Now, the output signal of the output circuit may be set to receive from an output of the inverter  103 . 
   Next, a fourth embodiment of this invention will be described. 
     FIG. 6  is a diagram showing a configuration of an output circuit according to the fourth embodiment of this invention. This output circuit includes a p-channel transistor QP 10  to a gate of which a drive signal is supplied, a p-channel transistor QP 20  serially connected to the transistor QP 10 , an output terminal connected to a drain of the transistor QP 10  and a source of the transistor QN 20  and a protection device  101 , and an inverter  103  to which an output signal of the output circuit is supplied through the protection device  101 . 
   The source of the transistor QP 10  is connected to the source potential V DD , and the source of the transistor QP 20  is connected to the source potential V SS  (to be set as a grounding potential in this embodiment). An output signal of this output circuit is supplied to an input of the inverter  103  through the protection device  101 , and a signal outputted by the inverter  103  is supplied to the gate of the transistor QP 20 , whereby a self feedback circuit is formed. 
   When a drive signal is at a high level, the transistor QP 10  is in the “off” state, and a potential of the output signal is nearly (V DD −V SS )/2 due to the operation of self feedback. When the drive signal becomes a low level, the transistor QP 10  is in the “on” state, and the potential of the output signal increases to near the source potential V SS . Consequently, an amplitude of the output signal becomes a half swing which is approximately half of the source potential (V DD −V SS ). Further, this output circuit is capable of performing high-speed operation by the self feedback operation. 
   In this embodiment, it is possible to set the high level of the drive signal as the source potential V DD  and the low level of the drive signal as the source potential V SS . Or, the high level of the drive signal may be set as a potential other than the source potential V SS . In that case, the output circuit according to this embodiment will have a function as a level shifter, too. Now, the output signal of the output circuit may be set to receive from an output of the inverter  103 . 
   Now, an embodiment of this invention as applied to a differential signal output circuit will be described below. 
     FIG. 7  is a diagram showing a configuration of an output circuit according to a fifth embodiment of this invention. This differential signal output circuit is configured such that by using two output circuits of a single configuration mentioned above, a differential signal is inputted to output a differential signal. 
   In a differential signal output circuit shown in  FIG. 7 , there are included two output circuits according to the first embodiment shown in  FIG. 1 . Differential drive signals AI and AI bar are inputted to two output circuits  10  which output differential output signals AO and AO bar. By this means, it is possible to output a differential signal of a half swing, which is nearly half of (V DD −V SS ). Now, instead of the output circuit  10 , any of the output circuits shown in  FIG. 3 ,  FIG. 5 , and  FIG. 6  according to the second to the fourth embodiments may be used. 
     FIG. 8  is a diagram showing a configuration of an output circuit according to a sixth embodiment of this invention. This differential signal output circuit is configured such that a signal of one system is inputted to output a differential signal. 
   A differential signal output circuit shown in  FIG. 8  includes inverters  104  and  105  as well as two output circuits  10  according to the first embodiment shown in  FIG. 1 . The inverter  104  inverts an input signal A 1  and generates a drive signal A 2 , while the inverter  105  inverts an input signal A 2  and generates a drive signal A 3 . 
   Two output circuits  10  are inputted by differential drive signals A 2  and A 3 , outputting differential output signals A 4  and A 5 . By this means, it is possible to output a differential signal of a half swing, which is approximately half of the source voltage (V DD −V SS ). Now, instead of the output circuit  10 , any of the output circuits shown in  FIG. 3 ,  FIG. 5 , and  FIG. 6  according to the second to the fourth embodiments may be used. 
     FIG. 9  is a diagram showing a configuration of an output circuit according to a seventh embodiment of this invention. This differential signal output circuit  1  is a circuit for outputting, based on the input signal A 1 , a first output signal A 8  and a second output signal A 8  bar as a pair of differential signals, comprising inverters INV  1 , INV 2 , INV 7 , INV 8 , single-end sense amplifiers  2  and  3 , and current mirror type differential amplifier circuits  4  and  5 . Each of these circuits operates upon receipt of a power supply from the source potential V DD  of the high source potential side and the source potential V SS  of the low source potential side. 
   As shown in  FIG. 9 , to the inverter INV 1  is supplied the input signal A 1 , and the inverter INV 1  outputs the drive signal A 2  which is the input signal A 1  inverted. Now, in this embodiment, this input signal A 1  and the drive signal A 2  undergo a change between the low level (in this case, the source potential V SS  of the low source potential side) and the high level (in this case, the source potential V DD  of the high source potential side). 
   The drive signal A 2  is supplied to the inverter INV 2 , and the inverter INV 2  outputs the drive signal A 3  which is the drive signal A 2  inverted. Now, in this embodiment, the drive signal A 3  undergoes a change between the low level and the high level. 
   The single-end sense amplifier  2  comprises a p-channel transistor QP 1 , an n-channel transistor QN 1 , and the inverters INV 3  and INV 4 . This single-end sense amplifier  2  has nearly the same configuration as the output circuit  10  shown in  FIG. 1 , supplying a signal A 4 , which is the drive signal A 2  inverted and further converted to a prescribed level, to differential amplifier circuits  4  and  5 . Now, as a single-end sense amplifier in this embodiment and the following, in addition to the output circuit  10  shown in  FIG. 1 , any of the output circuits shown in  FIG. 3 ,  FIG. 5 , and  FIG. 6  may be used. 
   In the single-end sense amplifier  2 , a source-drain path of the transistor QP 1  and a source-drain path of the transistor QN 1  are serially connected to between the source potential V DD  of the high source potential side and the source potential V SS  of the low source potential side, and to a gate of the transistor QN 1 , there is supplied the drive signal A 2 . A node of the transistor QP 1  and the transistor QN 1  is connected to an input of the inverter INV 3 , and an output signal of the inverter INV 3  is supplied to the inverter INV 4 . 
   An output of the inverter INV 4  is connected to a gate of the transistor QP 1 , and the transistor QP 1  constitutes a negative feedback group associated with an inverter INV 4  output and an inverter INV 3  input. Consequently, a level of the signal A 4  outputted by the inverter INV 4  is a level corresponding to a gain of the above-mentioned feedback group. The signal A 44  outputted by the inverter INV 4  is feedback inputted to the gate of the transistor QP 1 , and in addition, it is supplied to the differential amplifier circuits  4  and  5 . 
   A single-end sense amplifier  3  comprises a p-channel transistor QP 2 , an n-channel transistor QN 2 , and the inverters INV 5  and INV 6 . This single-end sense amplifier  3  supplies a signal A 5 , which is the drive signal A 3  inverted and further converted to a prescribed level, to the differential amplifier circuits  4  and  5 . 
   The transistors QP 2  and QN 2 , and the inverters INV 5  and INV 6  in the single-end sense amplifier  3  are connected in the same way as the transistors QP 1  and QN 1 , and the inverters INV 3  and INV 4  in the single-end sense amplifier  2 . As a result, the single-end sense amplifier  3  has the same circuit configuration as the single-end sense amplifier  2 . 
   A differential amplifier circuit  4  comprises p-channel transistors QP 3  and QP 4  and n-channel transistors QN 3 –QN 5 , supplying a signal A 6  corresponding to a difference between the signal A 4  and the signal A 5  to an inverter INV 8 . Specifically, the signal A 6  outputted by the differential amplifier circuit  4  becomes a low level when the signal A 4  is at a lower potential than the signal A 5  and becomes a high level when the signal A 4  is at a higher potential than the signal A 5 . 
   To sources of the transistors QP 3  and QP 4 , there is supplied the source potential V DD  of the high potential side, and a gate and a drain of the transistor QP 3  and a gate of the transistor QP 4  are mutually connected. A drain of the transistor QN 3  is connected to the drain and the gate of the transistor QP 3 , and to the gate of the transistor QN 3 , there is supplied the signal A 4 . A drain of a transistor QN 4  is connected to a drain of a transistor QP 4 , and to the gate of the transistor QN 4 , there is supplied the signal A 5 . A potential of a node between the drain of this transistor QN 4  and the drain of the transistor QP 4  is supplied, as the signal A 6 , to an inverter INV 8 . 
   To a source of a transistor QN 5 , there is supplied the source potential V SS  of the low potential side, and a drain of the transistor QN 5  is connected to sources of the transistors QN 3  and QN 4 . 
   Also, to a gate of the transistor QN 5 , there is supplied an enable signal EN 1 . When the enable signal EN 1  is at a high level, the transistor QN 5  assumes the “on” state, operating the differential amplifier circuit  4 . 
   A differential amplifier circuit  5  comprises p-channel transistors QP 5  and QP 6  and n-channel transistors QN 6 –QN 8 , supplying a signal A 7  corresponding to a difference between the signal A 5  and the signal A 4  to an inverter INV 7 . Specifically, the signal A 7  outputted by the differential amplifier circuit  5  becomes a high level when the signal A 4  is at a lower potential than the signal A 5  and becomes a low level when the signal A 4  is at a higher potential than the signal A 5 . 
   The transistors QP 5  and QP 6 , and the transistors QN 6 –QN 8  in the differential amplifier circuit  5  are connected in the same way as the transistors QP 3  and QP 4 , and the transistors QN 3 –QN 5  in the differential amplifier circuit  4 . As a result, the differential amplifier circuit  5  has the same circuit configuration as the differential amplifier circuit  4 . 
   The signal A 7  is supplied to the inverter INV 7 , and the inverter INV 7  outputs a signal, which is this signal A 7  inverted, as a first output signal A 8 . The signal A 6  is supplied to an inverter INV 8 , and the inverter INV 8  outputs a signal, which is this signal A 8  inverted, as a second output signal A 8  bar. 
     FIG. 10  is a timing chart showing operation of a differential signal output circuit  1 . 
   As  FIG. 10  shows, when the input signal A 1  changes from low level to high level at time t 0 , the drive signal A 2  outputted by the inverter INV 1 , after a prescribed delay time, changes from high level to low level. When the drive signal A 2  changes from high level to low level, the signal A 4  outputted by the single-end sense amplifier  2  changes from a first level, which is at a higher potential than the source potential V SS  of the low potential side, to a second level which is at a higher potential than the first level and at a lower potential than the source potential V DD  of the high potential side. 
   On the other hand, when the drive signal A 2  changes from high level to low level, the signal A 3  outputted by the inverter INV 2 , after a prescribed delay time, changes from low level to high level. When the drive signal A 3  changes from low level to high level, the signal A 5  outputted by the single-end sense amplifier  3  changes from the second level to the first level. 
   At an initial state, a potential of the signal A 4  is lower than a potential of the signal A 5 , and the signal A 7  outputted by the differential amplifier circuit  5  is at a high level, while the first output signal A 8  outputted by the inverter INV 7  is at a low level. Further, the signal A  6  outputted by the differential amplifier circuit  4  is at a low level, whereas the second output signal A 8  bar outputted by the inverter INV 8  is at a high level. 
   Thereafter, when the input signal A 1  changes from a low level to a high level at time t 0  as mentioned above, the potential of the signal A 4  becomes higher than the potential of the signal A 5 . By this means, the signal A 7  changes from a high level to a low level, and the first output signal A 8  changes from a low level to a high level. Further, the signal A 6  changes from a low level to a high level, while the second output signal A 8  bar changes from a high level to a low level. 
   Next, when the input signal A 1  changes from a high level to a low level at time t 0 , the drive signal A 2 , after a prescribed delay time, changes from a low level to a high level. When the drive signal A 2  changes from a low level to a high level, the signal A 4  outputted by the single-end sense amplifier  2  changes from the second level to the first level. 
   On the other hand, when the drive signal A 2  changes from a low level to a high level, the signal A 3  outputted by the inverter INV 2 , after a prescribed delay time, changes from a high level to a low level. When the drive signal A 3  changes from a high level to a low level, the signal A 5  outputted by the single-end sense amplifier  3  changes from the first level to the second level. 
   Consequently, the potential of the signal A 4  becomes lower than the potential of the signal A 5 , and the signal A 7  changes from a low level to a high level, while the first output signal A 8  changes from a high level to a low level. Further, the signal A 6  changes from a high level to a low level, whereas the second output signal A 8  bar changes from a low level to a high level. 
   At this point, since the differential amplifier circuits  4  and  5  output signals A 6  and A 7  according to the potentials of the signal A 6  and the signal A 5 , skewing will not occur between the signal A 6  and the signal A 7 . Therefore, there will occur no skewing between the first output signal A 8  and the second output signal A 8  bar. 
   Now, there is a case of an occurrence of a timing fluctuation by which the signals A 2 –A 5  change due to such factors as a scattering of a manufacturing process, temperature fluctuation, and fluctuation of a source potential (in this case, V DD  or V SS ) . However, even in such a case, since the differential amplifier circuits  4  and  5  output the signals A 6  and A 7  according to a difference of potentials between the signal A 4  and the signal A 5 , even though a timing by which the first output signal A 8  and the second output signal A 8  bar change may fluctuate before or after that, no skewing will occur between the first output signal A 8  and the second output signal A 8  bar. 
   As described above, insofar as the differential signal output circuit according to this invention is concerned, there is no requirement of a capacitor as required in the conventional differential signal output circuit  91  (refer to  FIG. 19 ), hence, it is possible to prevent a yield drop and the like. 
   Next, an eighth embodiment of this invention will be described.  FIG. 11  is a diagram showing an output circuit according to the eighth embodiment of this invention. This differential signal output circuit  11  is a circuit for outputting, based on an input signal B 1 , a first output signal B 8  and a second output signal B 8  bar as a pair of differential signals, comprising inverters INV 1 , INV 2 , INV 7 , INV 8 , single-end sense amplifiers  12  and  13 , and current mirror type differential amplifier circuits  14  and  15 . Each of these circuits operates upon receipt of power supply from the source potential V DD  of the high source potential side and the source potential V SS  of the low source potential side. 
   As compared to the differential signal output circuit  1  (refer to  FIG. 9 ) described above, the single-end sense amplifier  2  in the differential signal output circuit  1  outputs the drive signal A 2  and the signal A 4  inverted, and the single-end sense amplifier  3  outputs the drive signal A 3  and the signal A 5  inverted. On the other hand, the single-end sense amplifier  12  in the differential signal output circuit  11  outputs the drive signal B 2  and the signal B 4  of the same phase, and the single-end sense amplifier  13  outputs the drive signal B 3  and the signal B 5  of the same phase. Further, the differential amplifier circuits  14  and  15  are of an inverted circuit configuration to the differential amplifier circuits  4  and  5  in the differential signal output circuit  1  as well as the source potentials V DD  and V SS . 
   The differential signal output circuit  11  is, like the differential signal output circuit  1 , able to output a first output signal B 8  and a second output signal B bar having no skewing, also being capable of preventing a yield drop and the like because there is no requirement of a capacitor which is required in the conventional interface signal output circuit  91  (refer to  FIG. 19 ). 
   Next, a ninth embodiment of this invention will be described.  FIG. 12  is a diagram showing an output circuit according to the ninth embodiment of this invention. This differential signal output circuit  21  is a circuit for outputting, based on an input signal C 1 , a first output signal C 8  and a second output signal C 8  bar as a pair of differential signals, comprising inverters INV  1 , INV 2 , INV 7 , INV 8 , single-end sense amplifiers  22  and  23 , and current mirror type differential amplifier circuits  4  and  5 . Each of these circuits operates upon receipt of power supply from the source potential V DD  of the high source potential side and the source potential V SS  of the low source potential side. 
   As compared to the differential signal output circuit  11  (refer to  FIG. 11 ) described above, the differential signal output circuit  21  has different configurations of the single-end sense amplifier  22  and the single-end sense amplifier  23 . The single-end sense amplifier  22  comprises n-channel transistors QN 21  and QN 21  and inverters INV 23  and INV 24 , supplying a signal, which is a drive signal C 2  inverted, to the differential amplifier circuits  4  and  5 . 
   Source-drain paths of the transistors QN 21  and QN 22  are connected in series to between the source potential V DD  of the high source potential side and the source potential V SS  of the low source potential side, and the drive signal C 2  is supplied to a gate of the transistor Q 22 . A node of the transistor QN 21  and the transistor QN 22  is connected to an input of the inverter INV 23 . 
   An output of the inverter INV  23  is connected to a gate of the transistor QN 21 , and the transistor QN 21  constitutes a negative feedback group associated with an output and an input of the inverter INV 23 . Consequently, a level of a signal outputted by the inverter INV 23  becomes a level corresponding to a gain of the above-mentioned feedback group. An output signal of the inverter INV 23  is also supplied to the inverter INV 24 , and the inverter INV 24  supplies the signal C 4 , which is an output signal of the inverter INV 23  inverted, to the differential amplifier circuits  4  and  5 . 
   The single-end sense amplifier  23  comprises p-channel transistors QN 23  and QN 24  and inverters INV 25  and INV 26 , supplying a signal C 5 , which is a drive signal C 3  inverted, to the differential amplifier circuits  4  and  5 . The transistors QN 23  and QN 24  as well as the inverters INV 25  and INV 26  in the single-end sense amplifier  23  are connected in the same way as the transistors QN 21  and QN 22  as well as the inverters INV 23  and INV 24  in the single-end sense amplifier  22 . As a result, the single-end sense amplifier  23  has the same circuit configuration as the single-end sense amplifier  22 . 
   The differential signal output circuit  21  is able to output a first output signal B 8  and a second output signal B 8  bar having no skewing in the same way as the differential signal output circuit  11 . Further, since there is no requirement of a capacitor as required in the conventional differential signal output circuit  91  (refer to  FIG. 19 ); it is possible to prevent a yield drop and the like. 
   Next, a tenth embodiment of this invention will be described.  FIG. 13  is a diagram showing an output circuit according to the tenth embodiment of this invention. This differential signal output circuit  31  is a circuit for outputting, based on an input signal D 1 , a first output signal D 8  and a second output signal D 8  bar as a pair of differential signals, comprising inverters INV 31 , INV 32 , INV 37 , and INV 38 , single-end sense amplifiers  32  and  33 , and current mirror type differential amplifier circuits  34  and  35 . 
   The single-end sense amplifier  32  comprises a p-channel transistor QP 31 , an n-channel transistor QN 31 , and inverters INV 33  and INV 34 , 
   having the same circuit configuration as the single-end sense amplifier  2  in the above-mentioned differential signal output circuit  1  (refer to  FIG. 9 ). Likewise, the single-end sense amplifier  33  comprises a p-channel transistor QP 32 , an n-channel transistor QN 32 , and inverters INV 35  and INV 36 , having the same circuit configuration as the single-end sense amplifier  3  in the above-mentioned differential signal output circuit  1  (refer to  FIG. 9 ). 
   Further, the differential amplifier circuit  34  comprises p-channel transistors QP 33  and QP 34 , and n-channel transistors QN 33 –QN 35 , having the same circuit configuration as the differential amplifier circuit  4  in the above-mentioned signal output circuit  1  (refer to  FIG. 9 ). Likewise, the differential amplifier circuit  35  comprises a p-channel transistors QP 35  and QP 36 , and n-channel transistors QN 36 –QN 38 , having the same circuit configuration as the differential amplifier circuit  5  in the above-mentioned signal output circuit  1  (refer to  FIG. 9 ). 
   In the differential signal output circuit  31 , as compared to the above-mentioned signal output circuit  1  (refer to  FIG. 9 ), power is supplied by a source potential V DD1  of the high source potential side and the source potential V SS  of the low source potential side to the inverters INV 31  and INV 32 , whereas it is different in that power is supplied by a source potential V DD2  of the high source potential side and the source potential V SS  of the low source potential side to the single-end sense amplifiers  32  and  33 , the differential amplifier circuits  34 , and  35 , and the inverters INV 37  and INV 38 . 
   At this time, if we assume
 
V DD2 &gt;V DD1   (1)
 
   then the differential signal output circuit  31  will have a function as a booster circuit. For example, assume that a source potential V SS  is 0V, a source potential V DD1  is 1.8V, and a source potential V DD2  is 2.5V, then it becomes possible, based on an input signal D 1  of a 1.8V level, to output a first output signal D 8  and a second output signal D 8  bar of a 2.5V level. 
   Further, if we assume
 
V DD1 &gt;V DD2   (2)
 
   then the differential signal output circuit  31  will have a function as a step-down circuit. For example, assume a source potential V SS  of 0V, a source potential V DD2  of 1.8V, and a source potential V DD1  of 2.5V, then it becomes possible, based on an input signal D 1  of a 2.5V level, to output a first output signal D 8  and a second output signal D 8  bar of a 1.8V level. 
   Next, an eleventh embodiment of this invention will be described.  FIG. 14  is a diagram showing an output circuit according to the eleventh embodiment of this invention. This differential signal output circuit  41  is a circuit for outputting, based on an input signal E 1 , a first output signal E 8  and a second output signal E 8  bar as a pair of differential signals, comprising inverters INV 31 , INV 32 , INV 47 , and INV 48 , single-end sense amplifiers  32  and  33 , and current mirror type differential amplifier circuits  44  and  45 . 
   The differential amplifier circuit  44  comprises p-channel transistors QP 43  and QP 44 , and n-channel transistors QN 43 –QN 45 , having the same circuit configuration as the differential amplifier circuit  4  in the above-mentioned differential signal output circuit  1  (refer to  FIG. 9 ). Likewise, the differential amplifier circuit  45  comprises p-channel transistors QP 45  and QP 46 , and n-channel transistor QN 46 – 48 , having the same circuit configuration as the differential amplifier circuit  5  in the above-mentioned differential signal output circuit  1  (refer to  FIG. 9 ). 
   In the differential signal output circuit  41 , as compared to the above-mentioned signal output circuit  1  (refer to  FIG. 9 ), power is supplied by the source potential V DD1  of the high source potential side and the source potential V SS  of the low source potential side to the inverters INV 31  and INV 32 , and power is supplied by the source potential V DD2  of the high source potential side and the source potential V SS  of the low source potential side to the single-end sense amplifiers  32  and  33 , whereas it is different in that power is supplied by a source potential V DD3  of the high source potential side and the source potential V SS  of the low source potential side to the differential amplifier circuits  44  and  45  as well as the inverters INV 47  and INV 48 . 
   At this time if we assume
 
V DD3 &gt;V DD2 &gt;V DD1   (3)
 
   then the differential signal output circuit  41  will have a function as a booster circuit. For example, as compared to the differential signal output circuit  1  (refer to  FIG. 9 ) described above, this differential signal output circuit  41  is particularly effective in a case of a large potential difference between an input signal E 1 , and a first output signal E 8  and a second output signal E 8  bar. 
   For example, in the differential signal output circuit  31  (refer to  FIG. 13 ) described above for outputting, based on the input signal D 1  of the 1.8V level, the first output signal D 8  and the second output signal D 8  bar of a 5V level, it is necessary to supply 0V as the source potential V SS  of the low potential side, 1.8V as the source potential V DD1  of the high potential side, and 5V as the source potential V DD2  of the low potential side. However, supplying such source potentials would cause the single-end sense amplifiers  22  and  23  operating on the 5V source potential to receive the drive signals D 2  and D 3  of the 1.8 level, thus making it difficult to perform a desired operation. 
   On the other hand, if it is adapted in the differential signal output circuit  41  such that 0V as the source potential V SS  of the low potential side, 1.8V as the source potential V DD1  of the high potential side, 3.3V as the source potential V DD2 , and 5V as the source potential V DD3  of the low potential side are supplied, then it would become easy to output, based on the input signal E 1  of the 1.8V level, the first output signal E 8  and the second output signal E 8  bar of the 5V level. 
   Further, if we assume
 
V DD1 &gt;V DD2 &gt;V DD3   (4)
 
   then the differential signal output circuit  41  will have a function as a step-down circuit. As compared to the differential signal output circuit  31  (refer to  FIG. 13 ) described above, this differential signal output circuit  41  is particularly effective in a case of a large potential difference between the input signal E 1 , and the first output signal E 8  and the second output signal E 8  bar. 
   For example, in the differential signal output circuit  31  (refer to  FIG. 13 ) described above for outputting, based on the input signal D 1  of the 5V level, the first output signal D 8  and the second output signal D 8  bar of a 1.8V level, it is necessary to supply 0V as the source potential V SS  of the low potential side, 5V as the source potential V DD1  of the high potential side, and 1.8V as the source potential V DD2  of the high potential side. However, supplying such source potentials would cause the single-end sense amplifiers  32  and  33  operating on the 1.8V source potential to receive the drive signals D 2  and D 3  of the 5 level, thus making it difficult to perform a desired operation. 
   On the other hand, if it is adapted in the differential signal output circuit  41  such that 0V as the source potential V SS  of the low potential side, 5V as the source potential V DD1 , 3.3V as the source potential V DD2 , and 1.8V as the source potential V DD3  are supplied, then it would become easy to output, based on the input signal E 1  of the 5V level, the first output signal E 8  and the second output signal E 8  bar. 
   Next, a twelfth embodiment of this invention will be described.  FIG. 15  is a diagram showing an output circuit according to the twelfth embodiment of this invention. This differential signal output circuit  51  is a circuit for outputting, based on the input signal E 1 , a first output signal F 8  and a second output signal F 8  bar as a pair of differential signals, comprising inverters INV 1 , INV 2 , INV 7 , and INV 8 , single-end sense amplifiers  52  and  53 , and current mirror type differential amplifier circuits  14  and  15 . Each of these circuits receives power supplied by the source potential V DD  of the high potential side and the source potential V SS  of the low potential side and operates. 
   As compared to the above-mentioned differential amplifier circuit  11  (refer to  FIG. 11 ), the signal output circuit  51  has different configurations of the single-end sense amplifiers  52  and  53 . The single-end sense amplifier  52  comprises n-channel transistors QN 51  and QN 52  and an inverter INV 53 , supplying a signal F 4 , which is a drive signal F 2  converted to a prescribed potential level, to differential amplifier circuits  14  and  15 . 
   Source-drain paths of the transistors QN 51  and QN 52  are serially connected to between the source potential V DD  of the high source potential side and the source potential V SS  of the low source potential side, and to a gate of the transistor QN 51 , there is supplied the drive signal F 2 . A node of the transistor QN 51  and the transistor QN 52  is connected to an input of the inverter INV 53 . 
   An output of the inverter INV 53  is connected to the gate of the transistor QN 51 , and the transistor QN 51  constitutes a negative feedback group associated with an input and an output of the inverter INV 53 . Consequently, a level of the signal A 4  outputted by the inverter INV 53  is a level corresponding to a gain of the above-mentioned feedback group. 
   A single-end sense amplifier  53  comprises n-channel transistors QN 53  and QN 54 , and an inverters INV 55 , supplying a drive signal F 5 , which is a drive signal F 3  converted to a prescribed level, to the differential amplifier circuits  14  and  15 . 
   The transistors QN 53  and QN 54 , and the inverter INV 55  in the single-end sense amplifier  53  are connected in the same way as the transistors QN 51  and QN 52  as well as the inverter INV 53  in the single-end sense amplifier  52 . As a result, the single-end sense amplifier  53  has the same circuit configuration as the single-end sense amplifier  52 . 
   In this manner, according to the differential signal output circuit  51 , it is possible to realize an equivalent function as the differential signal output circuit  11  with fewer elements than the differential signal output circuit  11 . 
   Next, a thirteenth embodiment of this invention will be described.  FIG. 16  is a diagram showing an output circuit according to the thirteenth embodiment of this invention. This differential signal output circuit  61  is a circuit for outputting, based on an input signal G 1 , a first output signal G 8  and a second output signal G 8  bar as a pair of differential signals, comprising inverters INV 31 , INV 32 , INV 37 , and INV 38 , single-end sense amplifiers  62  and  63 , and the current mirror type differential amplifier circuits  34  and  35 . 
   As compared to the above-mentioned differential amplifier circuit  31  (refer to  FIG. 13 ), the signal output circuit  61  has different configurations of the single-end sense amplifiers  62  and  63 . The single-end sense amplifier  62  comprises n-channel transistors QN 61  and QN 62  as well as an inverter INV 63 , supplying a signal G 4 , which is a drive signal G 2  converted to a prescribed potential level, to the differential amplifier circuits  34  and  35 . 
   Source-drain paths of the transistors QN 61  and QN 62  are serially connected to between the source potential V DD2  of the high source potential side and the source potential V SS  of the low source potential side, and to a gate of the transistor QN 62  there is supplied the drive signal G 2 . A node of the transistor QN 61  and the transistor QN 62  is connected to an input of the inverter INV 63 . 
   An output of the inverter INV 63  is connected to the gate of the transistor QN 61 , and the transistor QN 61  constitutes a negative feedback group associated with an output and an input of the inverter INV 63 . Consequently, a level of the signal G 4  outputted by the inverter INV 63  is a level corresponding to a gain of the above-mentioned feedback group. 
   A single-end sense amplifier  63  comprises n-channel transistors QN 63  and QN 64 , and an inverters INV 55 , supplying a drive signal G 5 , which is a drive signal G 3  converted to a prescribed level, to the differential amplifier circuits  34  and  35 . 
   The transistors QN 63  and QN 64 , and the inverter INV 65  in the single-end sense amplifier  63  are connected in the same way as the transistors QN 61  and QN 62  as well as the inverter INV 53  in the single-end sense amplifier  62 . As a result, the single-end sense amplifier  63  has the same circuit configuration as the single-end sense amplifier  62 . 
   In this manner, according to the differential signal output circuit  61 , it is possible to realize an equivalent function as the differential signal output circuit  31  with fewer elements than the differential signal output circuit  31 . 
   Next, a fourteenth embodiment of this invention will be described. 
     FIG. 17  is a diagram showing an output circuit according to the fourteenth embodiment of this invention. This differential signal output circuit  71  is a circuit for outputting, based on an input signal HI, a first output signal H 8  and a second output signal H 8  bar as a pair of differential signals, comprising inverters INV 31 , INV 32 , INV 47 , and INV 48 , the single-end sense amplifiers  62  and  63 , and the current mirror type differential amplifier circuits  44  and  45 . 
   The signal output circuit  51  is that which makes use of the single-end sense amplifiers  32  and  33  in the above-mentioned differential amplifier circuit  61  (refer to  FIG. 16 ) instead of the single-end sense amplifiers  62  and  63  in the above-mentioned differential amplifier circuit  41  (refer to  FIG. 14 ). 
   According to a differential output circuit  71 , it is possible to realize an equivalent function as the differential signal output circuit  41  with fewer elements than the differential signal output circuit  41 . 
   INDUSTRIAL APPLICABILITY 
   Among other possibilities, this invention may be utilized in an output circuit for outputting a signal to an external circuit and a semiconductor integrated circuit having such an output circuit built-in.