Abstract:
A laser driver. The laser driver comprises a diode driver, a power detector, a first extreme detector, a second extreme detector and a current controller. The diode driver receives bias and modulation currents to control a laser diode for generating light signals. The power detector detects optical power of the light signals. The first and second extreme detectors, both coupled to the power detector, detect the first and second extreme values among detected optical power. The first extreme value is either the maximum or the minimum optical power of the light signals, while the second extreme value is the other.

Description:
BACKGROUND 
   The disclosure relates to a laser driver, and more particularly to a laser driver with automatic laser power control of laser diodes. 
   Laser diodes have been widely adopted in optical communication due to their high brightness and low dispersion. 
   Laser diodes are generally driven by a laser driver. A laser driver receives a digital signal to control or vary the current flowing through the laser diode, thus controlling the brightness thereof (i.e. optical output power) and a light emitting signal is then generated. A receiver identifies the digital signal according to the received optical output power. For example, when the optical output power of the laser diode is P 1 , which is relatively large, it represents a logical high state ‘1’. When the optical output power of the laser diode is P 0 , which is relatively small, it represents a logical low state ‘0’. 
   The greater the difference between P 1  and P 0 , the better the identification of transmitted data. The quality of the light emitting signal is examined based upon the extinction ratio (ER=P 1 /P 0 ). That is, the greater the ER, the better the quality of light emitting signals. 
   Laser diodes, however, have drawbacks, such as aging effect and temperature effect. That is, when a laser diode is driven with a constant current, the optical output power generated thereby decreases with the increase of operating temperature. Consequently, there is feedback mechanism in the related art to detect the light emitting signal of the laser diode for varying the driving current thereof to fix the average optical output power of the light emitting signal. 
   Though such feedback mechanism fixes the average optical output power, it, however, fails to solve the impact on ER which is incurred by aging and temperature effects.  FIG. 1  shows characteristic curves of the optical power to driving current in a laser diode. With the increase of the operating temperature or aging of components, the optical power-to-driving current characteristic curve may vary from a curve with a greater slope, L 1 , to a curve with a smaller slope, L 2 . Assuming the feedback mechanism of the related art fixes the average optical output power of the laser diode, P avg , the average driving current hence varies from I 1   avg  to I 2   avg  automatically with the variation of the characteristic curve from L 1  to L 2 . The difference between different driving currents (i.e. the magnitude of modulation current), however, does not vary in response to the increase of temperature or aging of components, that is, I 1   1 −I 1   0 =I 2   1 −I 2   0 . With reference to  FIG. 1 , the optical output power of light emitting signal varies from P 1   1  and P 1   0  to P 2   1  and P 2   0  respectively. It can be easily found that with the variation of slopes, ER 2  (=P 2   1 /P 2   0 ) is smaller than ER 1  (=P 1   1 /P 1   0 ). In other words, if only the average driving current is controlled, the quality of the light emitting signal degrades in response to the increase of temperature or aging of components. 
   SUMMARY 
   In view of the above, the invention provides a laser driver. The laser driver comprises a diode driver, a power detector, a first extreme detector, a second extreme detector and a current controller. The diode driver receives bias and modulation currents to control a laser diode for generating light signals. The power detector detects optical power of the light signals. The first and second extreme detectors, both coupled to the power detector, detect the first and second extreme values in the detected optical power. The first extreme value is either the maximum or the minimum optical power of the light signals, while the second extreme value is the other. The current controller comprises a bias current generator and a modulation current generator. The bias current generator generates the bias current according to the first extreme value. The modulation current generator generates the modulation current according to the difference between the first and second extreme values. A first loop constituted by the bias current generator, the diode driver, the laser diode, the power detector and the first extreme detector confines the first extreme value to a first requirement. A second loop constituted by the modulation current generator, the diode driver, the laser diode, the power detector and the first and second extreme detectors confines the difference between the first and second extreme values to a second requirement. 

   
     DESCRIPTION OF THE DRAWINGS 
     The invention is described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: 
       FIG. 1  is a schematic diagram of the optical power to driving current characteristic curves of a laser diode. 
       FIG. 2  is a block diagram illustrating a circuit according to an embodiment of the invention. 
       FIG. 3  is a block diagram illustrating a bias current generator. 
       FIG. 4  is a block diagram illustrating an embodiment of a computation comparison unit and a voltage-to-current converter in  FIG. 3 . 
       FIG. 5  is a block diagram illustrating an embodiment of a modulation current generator. 
       FIG. 6  is a block diagram illustrating an embodiment of a computation comparison unit and a voltage-to-current converter in  FIG. 5 . 
       FIG. 7  is a block diagram illustrating another embodiment of a computation comparison unit and a voltage-to-current converter in  FIG. 5 . 
   

   DETAILED DESCRIPTION 
     FIG. 2  shows a block diagram of a circuit according to an embodiment of the invention. A laser driver  12  to drive a laser diode LD comprises a diode driver  10 , a photo diode PD, a current-to-voltage converter  40 , a peak detector  20 , bottom detector  30  and a current controller  50 . 
   The diode driver  10  receives bias current I bias  and modulation current I mod  to determine the magnitude of driving current I 1 , when logic state is ‘1’ and I 2  when logic state is ‘0’ respectively. The diode driver  10  then generates I 1 , and I 0  in response to the logic state of received digital signal to modulate the optical output power of laser diode LD for generating a light emitting signal. 
   The photo diode PD disposed in the laser diode LD module converts the optical output power of the laser diode LD to a current. That is the received light emitting signal is converted to a current signal. The current-to-voltage converter  40  then converts the current signal to a voltage signal. Thus, each voltage signal corresponds to the optical output power of the light emitting signal. The photo diode PD and current-to-voltage converter  40  can be seen as a whole as a power detector for detecting the power of the light emitting signal. 
   The peak detector  20  detects the maximum voltage V H  of the voltage signal during one period, thus obtaining the maximum optical output power of the light emitting signal in that period. Conversely, the bottom detector  30  detects the minimum voltage V L  of the voltage signal during one period, thus obtaining the minimum optical output power of the light emitting signal. It is assumed in the following that the maximum optical output power corresponds to optical power P 1 , when logic state is “1” and the minimum optical output power corresponds to optical power P 0  when the logic state is “0”. It is, however, obvious for those skilled in art that if the described relationship changes, there is no effect on the enablement of the invention and thereupon the claim construction would not change. 
   The current controller  50  comprises I bias  generator  70  and I mod  generator  60 . I bias  generator  70  generates current I bias  in response to voltage V L , whereas I mod  generator  60  generates current I mod  in response to voltages V L  and V H . 
   Two loops in  FIG. 2  have partially shared routes. The first loop comprises I bias  generator  70 , diode driver  10 , laser diode LD, photo diode PD, current-to-voltage converter  40  and bottom detector  30 . The first loop utilizes a feedback mechanism to clamp (V L -V thb ) to a fixed value N 1 , corresponding to fixing the value of P 0 , wherein voltage V thb  is the reference voltage detected by bottom detector  30  or peak detector  20  when no output is generated by laser diode LD. The second loop comprises I mod  generator  60 , diode driver  10 , laser diode LD, photo diode PD, current-to-voltage converter  40 , peak detector  20  and bottom detector  30 . The second loop also utilizes a feedback mechanism to clamp (V H -V L ) to a fixed value N 2 , corresponding to fixing (P 1 -P 0 ). Thus the following equations are obtained.
 
 V   L   =R   f   ×R×P   0   +V   thb   =N   1   +V   thb   (1)
 
 V   H   =R   f   ×R×P   1   +V   thb   =N   2   +N   1   +V   thb   (2)
 
where R f  is the gain of current-to-voltage converter  40  and R is the responsivity of photo diode PD.
 
From equations (1) and (2), the following equation is derived.
 
   
     
       
         
           
             
               
                 
                   
                     
                       ER 
                       = 
                       
                         
                           
                             P 
                             1 
                           
                           / 
                           
                             P 
                             0 
                           
                         
                         = 
                         
                           
                             ( 
                             
                               
                                 V 
                                 H 
                               
                               - 
                               
                                 V 
                                 thb 
                               
                             
                             ) 
                           
                           / 
                           
                             ( 
                             
                               
                                 V 
                                 L 
                               
                               - 
                               
                                 V 
                                 thb 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
                 
                   
                     
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                             ( 
                             
                               
                                 V 
                                 H 
                               
                               - 
                               
                                 V 
                                 L 
                               
                             
                             ) 
                           
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                             ( 
                             
                               
                                 V 
                                 L 
                               
                               - 
                               
                                 V 
                                 thb 
                               
                             
                             ) 
                           
                         
                         + 
                         1 
                       
                     
                   
                 
                 
                   
                     
                       = 
                       
                         
                           
                             
                               N 
                               2 
                             
                             / 
                             
                               N 
                               1 
                             
                           
                           + 
                           1 
                         
                         = 
                         
                           K 
                           + 
                           1 
                         
                       
                     
                   
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
   
   From equation (3) it can be found that with the first and second loops, the extinction ratio ER is fixed and independent of V H , V L  and V thb . It does not vary in response to either the aging of components or an increase in operating temperature. 
     FIG. 3  is a block diagram of a bias current I bias  generator. The I bias  generator  70  comprises a reference voltage generator  76 , a computation comparison unit  72  and a voltage-to-current converter  74 . The reference voltage generator  76  provides the characteristics of photo diode PD as a basis for adjusting voltage V L . For example, as depicted, reference voltage generator  76  generates a corresponding reference voltage V thb  when photo diode PD detects no light. It is obvious that voltage V thb  is smaller than voltage V L  since voltage V thb  is the voltage detected just before laser diode is turned on and voltage V L  is the minimum voltage when laser diode is already turned on. Moreover, it is advantageous that voltage V L  is greater than voltage V thb  because the turn on delay of laser diode LD is reduced thereby. The reference voltage generator  76  in  FIG. 3  comprises a photo diode PD dark  which detects no light, a current-to-voltage converter  40 , and a bottom detector  32 . The reference voltage V thb  can be obtained only by photo diode PD dark  and current-to-voltage converter  40 . It is, however, more stable with the bottom detector  32  and the disturbance incurred by noise is thus reduced. 
   The computation comparison unit  72  subtracts V thb  from V L  and then has ΔV real . The computation comparison unit  72  also subtracts V refL  from V refH  and then yields ΔV exp . The comparator  78  then compares ΔV real  and ΔV exp , and the output thereof is desirable only when ΔV real  equals to ΔV exp . The following equation is then derived.
 
 V   L   =V   thb   +ΔV   exp   =V   thb +( V   refH   −V   refL )  (4)
 
   V refH  abd V refL  can be seen as two adjustable predetermined voltages. A user can adjust the difference between voltage V L  and reference voltage V thb  by setting voltages V refH  abd V refL . 
   The voltage-to-current converter  74  converters the output of comparator  78  to a current and then outputs it to the diode driver  10  as a bias current I bias . 
     FIG. 4  is an embodiment of computation comparison unit  72  and voltage-to-current converter  74  in  FIG. 3 . 
   The PMOS transistors PS 1  and PS 2  in upper half of  FIG. 4  are two mirroring current sources. The lower half of  FIG. 4  can be divided into two parts, right half and left half. The left half is voltage-to-current converter  80   a  converting the difference between V L  and V thb  to current I c  and outputting it to voltage-to-current converter  80   b  in the right half through PMOS transistors PS 1  and PS 2 . The voltage-to-current converter  80   b  is controlled by voltages V refH  and V refL  to limit the magnitude of current I c . 
   Because the circuits of voltage-to-current converters  80   a  and  80   b  are the similar and thus only the operation of voltage-to-current converters  80   a  is described in the following. It should be appreciated for those skilled in the art to contemplate other similar parts under the operating principle introduced below. 
   The NMOS transistors NS 1  and NS 2  in voltage-to-current converters  80   a  can be seen as two current sources providing currents of the same magnitude. Two identical switch modules  82   a  and  82   b  are connected to NMOS transistors NS 1  and NS 2  via nodes A and B respectively. The switch module  82   a  comprises an operating amplifier OP 1  and a NMOS transistor N 11 . The output of operating amplifier OP 1  is connected to the control gate of transistor N 11 ; the negative input terminal thereof is connected to node A and the positive input terminal thereof receives voltage V L . When voltage V L  is smaller than the voltage at node A, transistor N 11  is turned off. The node A is then discharged by the current source, PMOS PS 2 , and thus the voltage of node A is decreased. Conversely, when voltage V L  is greater than the voltage at node A, transistor N 11  is turned on. The node A is then charged by the current source, PMOS PS 2 , and thus the voltage of node A is increased. Hence, the voltage of node A is clamped to V L  when in stable condition, that is, switch module  82   a  shifts voltage V L  to node A. In the same manner, switch module  82   b  shifts voltage V thb  to node B. 
   The resistor R 1  connected between nodes A and B is used to generate a differential current I c (=(V L −V thb )/R 1 ). Because of the blocking of current sources NS 1  and NS 2 , the differential current I c  flows into NMOS transistor N 11  from node XA and then flows out from node XB via NMOS transistor N 12  as shown. 
   In a similar way, the voltage-to-current converter  80   b  generates a current with a value equal to (V refH −V refL )/R 2  through resistor R 2 . When the magnitude of differential current I c  is not equal to (V refH -V refL )/R 2 , nodes XA or XB will be charged or discharged and thus the voltage at nodes XA and XB changes. The current I bias  is then changed by voltage-to-current converter  74  (taking the NMOS transistor NC in  FIG. 4  as an example). By the described first loop, the variation of current I bias  changes the voltage V L  which in turn changes differential current I c . The variation of differential current I c  then changes current I bias . By such a feedback mechanism, I c  will equal (V refH −V refL )/R 2  when in stable condition and the following equation is derived.
 
 I   c =( V   L   −V   thb )/ R 1=( V   refH   −V   refL )/ R 2
 
 V   L   =V   thb +( V   refH   −V   refL )* R 1 /R 2  (5)
 
   Voltages V thb , V refH  and V refL  and resistors R 1  and R 1  are fixed, so voltage V L  is confined to a constant by the first loop. Equation (5) can be simplified into equation (4) by equaling of R 1  and R 2 . 
   Refer to  FIG. 5 , a block diagram of I mod  generator. With reference to  FIG. 3 , the computation comparison unit  62  and voltage-to-current converter  64  in  FIG. 5  are similar to computation comparison unit  72  and voltage-to-current converter  74  in  FIG. 3  except that some input signals are different and there is a multiplier  68  at the positive input terminal of comparator  66  in computation comparison unit  62  to multiply the difference between V refH  and V refL  by K. According to the operating description of  FIG. 3 , computation comparison unit  62  implements the following equation when the output of comparator  66  is desirable.
 
 V   H   −V   L   =K *( V   refH   −V   refL)   (6)
 
     FIG. 6  is an embodiment of computation comparison unit  62  and voltage-to-current converter  64  in  FIG. 5 . Because  FIG. 6  is similar to  FIG. 4 , only some main points are introduced in the following. Those skilled in the art should understand the operating of  FIG. 6  in accordance with the description of FIG.  4  and the discussion below. Current source NMOS NS 5  corresponds to current source NMOS NS 6  and current source NMOS NS 7  corresponds to current source NMOS NS 8 . The current provided by NMOS transistor NS 5  however is K times the current provided by NMOS transistor NS 7 . This is generally achieved by varying the component size according to the desired ratio. PMOS transistors PS 5  and PS 7  constitute a current mirror and the current flowing through transistor PS 5  is K times that flowing through transistor PS 7  for the K time component size. Similarly, the current flowing through transistor PS 6  is K times that flowing through transistor PS 8 . 
   Current I m  flowing through resistor R 3  is (V H −V L )/R 3  and is diverted to node XC for the blocking of current source NMOS NS 6 . Current I n  flowing through R 4  is (V refH −V refL )/R 4  and flows through PMOS transistor PS 8 . A current which is K times the current I n , is then mirrored by PMOS transistor PS 6  and flows out of node XC. Whenever current I m  is not equal to I n *K, nodes XC will be charged or discharged and thus the voltage at nodes XC is changed. The current I mod  is then changed by voltage-to-current converter  64  in  FIG. 6 . With the second loop discussed above, the variation of current I mod  changes the difference between voltages V L  and V H , which in turn changes the current I m . The variation of current I m  then changes current I mod . With such feedback mechanism, current I m  will equal I n *K when in stable condition and the following equation is derived.
 
( V   H   −V   L )/ R 3 =K *( V   refH   −V   refL )/ R 4
 
 V   H   −V   L   =K *( V   refH   −V   refL )* R 3 /R 4  (7)
 
   Voltages V thb , V refH  and V refL  and resistors R 3  and R 4  are fixed, so the second loop confines (V H −V L ) to a constant. Equation (7) can be simplified into equation (6) by equaling R 3  and R 4 . 
     FIG. 7  is another embodiment of computation comparison unit  62  and voltage-to-current converter  64  in  FIG. 5 .  FIG. 7  is similar to  FIG. 6  except that the magnitude of currents provided by NMOS transistor NS 5 ˜NS 8  is the same, the size of PMOS transistors PS 5 ˜PS 8  is the same and the resistance of resistor R 3  is K times that of resistor R 4 . In stable condition, the following equation is derived in  FIG. 7  by this feedback mechanism.
   V   H   −V   L =( V   refH   −V   refL ) R 3 /R 4 =K *( V   refH - V   refL ) 
   So (V H −V L ) is also limited to a constant which is K times (V refH −V refL ). 
   From the foregoing discussion, an embodiment of laser driver according to the invention comprises two loops. One loop locks voltage V L , corresponding to lock of P 0 , and the other locks voltage (V H −V L ), corresponding to lock of (P 1 −P 0 ). Consequently, utilizing embodiments of the invention, the extinction ratio ER(=P 1 /P 0 ) regarding the quality of the light emitting signal is confined to a constant and thus would not vary with aging of components or increase of operating temperature. 
   While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.