Abstract:
The present invention relates to a semiconductor memory device and, more particularly, to package and test technique of a semiconductor memory device. An object of the present invention to provide a semiconductor memory device capable of performing a package test with bandwidth except for default bandwidth without any wiring modification with respect to package option pads. The present invention can implement the other package options except for the default package option determined by the wire bonding with internal option. When the package level test is to be performed using the other bandwidth except for the bandwidth corresponding to the default package option, it is unnecessary to modify the wiring. Since the test can be performed with the upper bandwidth than the bandwidth corresponding to the default package option, the package test time can be reduced. For this, the buffer control signals are used which control the VDD or VSS applied to the package option pads via the wire bonding according to the operation mode. The buffer control signal can be generated using the mode register reset. The buffer receiving the buffer control signal outputs the signal corresponding to the wiring state of the package option pad, blocks the signal path from the package option pads, and outputs the signal corresponding to the package option except for the default package option.

Description:
FIELD OF THE INVENTION  
         [0001]    The present invention relates to a semiconductor memory device and, more particularly, to package and test technique of a semiconductor memory device.  
         DESCRIPTION OF THE PRIOR ART  
         [0002]    Recently, main issue in semiconductor memory fields tends to change from an integrity to an operating speed. Therefore, high-speed synchronous memory devices such as double data rate synchronous DRAM (DDR SDRAM) and RAMBUS DRAM have been focused as a new topic subject. The synchronous memory device is a memory operating in synchronization with an external system clock and SDRAM among the DRAMs has been a main stream in commercially available memory market. In input/output operations, the SDRAM performs data access one time at every clock in synchronization with rising edges of clocks. On the other hand, the high-speed synchronous memory device such as the DDR SDRAM which progresses mass-production operates in synchronization with falling edges as well as rising edges of clocks so that data access can be performed two times at every clock.  
           [0003]    The DRAM products that are being manufactured have X4/X8/X16 bandwidths. In other words, the bandwidth of product is determined according to customer&#39;s demand, and the DRAM product has specific pin arrangement and wiring according to the bandwidth.  
           [0004]    [0004]FIG. 1 is a diagram showing a pin arrangement of conventional X4 and X16 SDRAMs (54 pins).  
           [0005]    Referring to FIG. 1, an X16 SDRAM includes data I/O pins DQ 0  to DQ 15 , address pins A 0  to A 12 , bank address pins BA 0  and BA 1 , power pins VDD, VSS, VDDQ and VSSQ, data mask pins LDQM and UDQM, command pins /WE, /CAS, /RAS and ICS, a clock pin CK, and a clock enable pin CKE, and each of them are wire-bonded with pads of a die via lead frames. In case of the X16 SDRAM, 16 DQ pins are all used, and only one pin among the 54 pins is no-connection (NC).  
           [0006]    Meanwhile, since an X4 SDRAM uses only 4 DQ pins (i.e., DQ 0 , DQ 1 , DQ 2  and DQ 3 ), the other 12 DQ pins are in no-connection state. Since the lower data mask pin LDQM among the data mask pins LDQM and UDQM remains in the NC state, the total 14 pins of the 54 pins remains in the NC states.  
           [0007]    Since data mask signals are controlled by bit unit, one data mask pin (DQM) is used in the X4 or X8 SDRAM and two data mask pins (LDQM, UDQM) are used in the X16 SDRAM.  
           [0008]    [0008]FIG. 2 is a diagram showing a pin arrangement of conventional X4/X8/X16 DDR SDRAMs (66 pins).  
           [0009]    Referring to FIG. 2, the pin arrangement of DDR SDRAM is almost similar to that of SDRAM except that the DDR SDRAM uses data strobe pins LDQS, UDQS and DQS, a reference voltage pin VREF, a clock bar pin /CK. In other words, the X16 DDR SDRAM uses 16 DQ pins and the X8 DDR SDRAM uses 8 DQ pins. The X4 DDR SDRAM uses 4 DQ pins.  
           [0010]    While the X16 DDR SDRAM uses two bonded data mask pins LDM and UDM, the X4 or X8 DDR SDRAM does not use the lower data mask pin LDM and remains in the NC state. In addition, the X4 or X8 DDR SDRAM uses one data mask pin DM. While the X16 DDR SDRAM uses two bonded data strobe pins LDQS and UDQS, the X4 or X8 DDR SDRAM does not use the lower strobe pin LDQS and remains in the NC state so that only one data strobe pin DQS is used.  
           [0011]    As shown in FIGS. 1 and 2, all the semiconductor memory devices have respectively specific pin arrangements and wirings according to the bandwidths.  
           [0012]    Meanwhile, the integrity of semiconductor memory device is increased and several ten millions of cells are integrated within one memory chip. If the number of memory cells is increased, it takes much time to test whether the memory cells are normal or defective. In this package test, the package test time as well as the accuracy of test results must be considered.  
           [0013]    To meet these demands in view of the package test time, there is proposed a parallel test which can perform multi-bit access at the same time. However, since the parallel test performs a test operation through data compression, a screen ability is degraded. In addition, the parallel test has a disadvantage that a relativity due to difference between data paths or power noise is not reflected.  
           [0014]    Accordingly, in order to more accurately check characteristics of product, non-compression method whose test time is long must be used. A following description is made on the assumption of the non-compression method.  
           [0015]    [0015]FIG. 3 is a conventional wire bonding diagram according to package options.  
           [0016]    Referring to FIG. 3, in case of an X4 product  100 , a package option pad (PAD X4)  101  is wire-bonded with a VDD pin and another package option pad (PAD X8)  102  is wire-bonded with a VSS pin. In FIG. 3, dark portions represent pads wire-bonded with package leads, and bright portions represent floating states. Meanwhile, in case of an X8 product  110 , a package option pad (PAD X4)  111  is wire-bonded with a VSS pin, and another package option pad (PAD X8)  112  is wire-bonded with a VDD pin. In case of an X16 product  120 , package option pads (PAD X4)  121  and (PAD X8)  122  are wire-bonded with VSS pin.  
           [0017]    [0017]FIG. 4 is a circuit diagram of a conventional package option signal generation block.  
           [0018]    Referring to FIG. 4, VDD or VSS applied to the package option pads PAD X4 and PAD X8 are buffered through buffer units  130  and  140  and outputs as package option signals sX 4  and sX 8 . Here, the buffer units  130  and  140  are provided with two inverters.  
           [0019]    A following table 1 is a package option table of an operation bandwidth according to the wire bonding.  
                                                     TABLE 1                                   X4   X8   X16                                        PAD X4   VDD   VSS   VSS           PAD X8   VSS   VDD   VSS           SX4   H   L   L           SX4   L   H   L                      
 
           [0020]    Referring to the table 1, if the package option signals sX 4  and sX 8  are a logic high (H) level and a logic low (L) level, respectively, corresponding chip operates as X4. The package option signals sX 4  and sX 8  are a logic low (L) level and a logic high (H) level, respectively, corresponding chip operates as X8. The package option signal sX 4  and sX 8  are all a logic low (L) level, and corresponding chip operates as X16.  
           [0021]    A following table 2 is an address scramble of a conventional SDRAM (DDR SDRAM).  
                                                               TABLE 2                       ADDRESS   A0   A1   A2   A3   A4   A5   A6   A7   A8   A9   A11   A12                   X4 PACKAGE   Y0   Y1   Y2   Y3   Y4   Y5   Y6   Y7   Y8   Y9   Y11   Y12       X8 PACKAGE   Y0   Y1   Y2   Y3   Y4   Y5   Y6   Y7   Y8   Y9   Y11   NC       X16 PACKAGE   Y0   Y1   Y2   Y3   Y4   Y5   Y6   Y7   Y8   Y9   NC   NC                  
 
           [0022]    Referring to the table 2, in case of the X16 package, 10 Y addresses (column addresses) Y0 to Y9 are sequentially counted with respect one word line. The entire cells connected to the word line can be screened by performing test 1024 times. At this time, 16 data are inputted/outputted through the bonded pads. In addition, in case of the X8 package, 11 Y addresses Y0 to Y11 are sequentially counted with respect one word line. The entire cells connected to the word line can be screened by performing test 2048 times. At this time, 8 data are inputted/outputted through the bonded pads, so that the test time is taken longer two times compared with the X16 package. In case of the X4 package, 12 Y addresses Y0 to Y12 are sequentially counted with respect one word line. The entire cells connected to the word line can be screened by performing test 4096 times. At this time, 4 data are inputted/outputted through the bonded pads, so that the test time is taken longer four times compared with the X16 package. In other words, as the bonded number of DQ pads with respect to the number of physical DQ pads is smaller, the number of data inputted/outputted at one time is reduced so that the entire test time is increased.  
           [0023]    According to the above-described prior art, once the wiring with respect to the package option pads is completed, the test can be performed by using only one package option corresponding to the wiring state at a test mode operation as well as a normal mode operation. Therefore, the X8 or X4 package option needs a long test time.  
           [0024]    Meanwhile, in another aspect, if performing only a test with respect to one package option determined by the wire bonding of the package option pads, it is difficult to detect failure according to change of bandwidths. Therefore, there are many cases that the test is performed with respect to other package options as well as corresponding package option. In particular, in case of product bonded with the X4 or X8 package, since some of the DQ pins are in the NC states, it is difficult to test the package characteristic of upper bandwidth. However, in case of products bonded with the X16 package, it is possible to test the characteristic of the bandwidth of X8 or X4 package.  
           [0025]    When assuming characteristic of the products bonded with X16 package is tested, in order to test the X4 or X8 package characteristic, the wiring with respect to the package option pad must be modified. In other words, after testing the X8 package characteristic, the wiring is again modified and then the X4 package characteristic is tested. In this case, since the wiring modifications corresponding to the respective package options are needed, there is a problem that the packing cost and test time are increased.  
         SUMMARY OF THE INVENTION  
         [0026]    It is, therefore, an object of the present invention to provide a semiconductor memory device capable of performing a package test with bandwidth except for default bandwidth without any wiring modification with respect to package option pads.  
           [0027]    In accordance with an aspect of the present invention, there is provided a semiconductor memory device which comprises: at least one package option pad wire-bonded in a default package option; a buffer control signal generation means for generating a buffer control signal; and a buffering means for buffering a signal applied to the package option pad in a normal mode in response to the buffer control signal and outputting the buffered signal as a package option signal, blocking the signal applied to the package option pad in a test mode, and outputting a signal corresponding to package option pads except for the default package option as the package option signal.  
           [0028]    In accordance with another aspect of the present invention, there is provided a semiconductor memory device which comprises: first and second package option pads wire-bonded in a default package option; a buffer control signal generation means for generating a buffer control signal; a first buffering means for buffering a signal applied to the first package option pad in a normal mode in response to the buffer control signal and outputting the buffered signal as a first package option signal, blocking the signal applied to the first package option pad in a test mode, and outputting a signal corresponding to package option pads except for the default package option as the first package option signal; and a second buffering means for buffering a signal applied to the second package option pad in a normal mode in response to the buffer control signal and outputting the buffered signal as second a package option signal, blocking the signal applied to the second package option pad in a test mode, and outputting a signal corresponding to package options except for the default package option as the second package option signal.  
           [0029]    In accordance with further another aspect of the present invention, there is provided a semiconductor memory device which comprises: at least one package option pad wire-bonded in a default package option; a buffer control signal generation means for generating a buffer control signal; a buffering means for buffering signals applied to the package option pad; and a switching means for transferring an output of the buffering means and a signal corresponding to package options except for the default package option in response to the buffer control signal as a package option signal. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0030]    Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:  
         [0031]    [0031]FIG. 1 is a diagram showing a pin arrangement of conventional X4 and X16 SDRAMs (54 pins);  
         [0032]    [0032]FIG. 2 is a diagram showing a pin arrangement of conventional X4/X8/X16 DDR SDRAMs (66 pins);  
         [0033]    [0033]FIG. 3 is a conventional wire bonding diagram according to package options;  
         [0034]    [0034]FIG. 4 is a circuit diagram of a conventional package option signal generation block;  
         [0035]    [0035]FIG. 5 is a diagram of a wire bonding structure according to package option in accordance with an embodiment of the present invention;  
         [0036]    [0036]FIG. 6 a block diagram of a package option signal generation circuit in accordance with an embodiment of the present invention;  
         [0037]    FIGS.  7  to  12  are exemplary circuit diagrams of the buffer unit in accordance with a first embodiment of the present invention; and  
         [0038]    [0038]FIG. 13 is a circuit diagram of a package option signal generation circuit in accordance with a second embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0039]    Hereinafter, preferred embodiments of the present invention will be descried in detail with reference to attached drawings.  
         [0040]    [0040]FIG. 5 is a diagram of a wire bonding structure according to package option in accordance with an embodiment of the present invention.  
         [0041]    Referring to FIG. 5, in case of an X4 product  200 , a package option pad (PAD X4)  201  is wire-bonded with a VDD pin and another package option pad (PAD X8)  202  is wire-bonded with a VSS pin. Meanwhile, in case of an X8 product  210 , a package option pad (PAD X4)  211  is wire-bonded with a VSS pin, and another package option pad (PAD X8)  212  is wire-bonded with a VDD pin. In case of an X16 product  220 , package option pads (PAD X4)  221  and (PAD X8)  222  are wire-bonded with VSS pin.  
         [0042]    In the wire bonding structure applied to the present invention, the structure of the package option pads and the applied signals are the same as the prior art shown in FIG. 3. However, the present invention has the same wire bonding structure of DQ pin as the X16 product  220  having maximum bandwidth without regard to the X4 product  200  or the X8 product  210 . In other words, all the DQ pins are wire-bonded without regard to the package options.  
         [0043]    [0043]FIG. 6 a block diagram of a package option signal generation circuit in accordance with an embodiment of the present invention.  
         [0044]    Referring to FIG. 6, the package option signal generation circuit in accordance with the present invention includes: at least one package option pad  60  wire-bonded in a default package option; a buffer control signal generation unit  64  for generating a buffer control signal; and a buffer unit  62  for buffering a signal applied to the package option pad  60  in response to the buffer control signal and outputting the buffered signal, or blocking the signal applied to the package option pad  60  and outputting a signal corresponding to package option pads except for the default package option as the package option signal. Here, the buffer control signal generation unit  64  is a test mode signal generation circuit using a mode register set.  
         [0045]    The buffer control signal is disabled during a normal mode operation so that the buffer unit  62  buffers the signal applied to the package option pad  60  via a bonding wire to generate the buffered signal to the package option signal. In other words, during the normal mode operation, the semiconductor memory device operates with bandwidth corresponding to the default package option. Meanwhile, during a test mode operation, the buffer control signal is enabled so that the buffer unit  62  blocks the signal inputted from the package option pad  60  and outputs the package option signal corresponding to the package options except for the default package option. In other words, during the test mode operation, the semiconductor memory device operates with bandwidth except for the default bandwidth. At this time, in case where the buffer control signal generation unit  64  outputs one buffer control signal, the bandwidth that can be selected during the test mode is also one. On the contrary, in case where the buffer control signal generation unit  64  outputs two or more buffer control signals, it is possible to perform the test with respect to a plurality of bandwidths during the test mode.  
         [0046]    [First Embodiment] 
         [0047]    In the first embodiment of the present invention, two package option pads PAD X4 and PAD X8 are used. There is proposed a circuit which selectively outputs package option signals sX 4  and sX 8  according to the operation modes through a logic combination of signals applied to the two package option pads PAD X4 and PAD X8 from the buffer unit  62  of FIG. 6 and buffer control signals enX 8  and enX 16 .  
         [0048]    [0048]FIG. 7 is a first exemplary circuit diagram of the buffer unit  62  in accordance with the first embodiment of the present invention.  
         [0049]    Referring to FIG. 7, the buffer unit  62  includes: a first buffer unit  230  for buffering a signal applied to the package option pads PAD X4 wire-bonded according to the package options and a signal applied to the package option pad PAD X4 in the normal mode in response to the buffer control signal enX 16  to output the buffered signal as a package option signal sX 4 , and outputting the PAD X4 option signal corresponding to the maximum bandwidth (i.e., X16 package) in the test mode as the package option signal sX 4 ; and a second buffer unit  240  for buffering a signal applied to the package option pad PAD X8 in the normal mode in response to the buffer control signal enX 16  to output the buffered signal as the package option signal sX 8 , and outputting the PAD X8 option signal corresponding to the maximum bandwidth (i.e., X16 package) in the test mode as the package option signal sX 8 . Meanwhile, a mode register set (MRS) control circuit  250  is contained in the buffer control signal generation unit  64  of FIG. 6. Here, it is assumed that the buffer control signal enX 16  is a high active signal.  
         [0050]    Meanwhile, the first buffer  230  includes: an inverter INV 1  receiving the buffer control signal enX 16 ; a NAND gate NAND 1  receiving an output of the inverter INV 1  and the signal applied to the package option pad PAD X4; and an inverter INV 2  receiving an output of the NAND gate NAND 1  to output the package option signal sX 4 . The second buffer  240  includes: an inverter INV 3  receiving the buffer control signal enX 16 ; a NAND gate NAND 2  receiving an output of the inverter INV 3  and the signal applied to the package option pad PAD X8; and an inverter INV 4  receiving an output of the NAND gate NAND 2  to output the package option signal sX 8 .  
         [0051]    Hereinafter, an operation of the semiconductor memory device with the circuit of FIG. 7 will be described in detail.  
         [0052]    In case of a default X4 package in which the package option pads PAD X4 and PAD X8 are respectively bonded with the VDD pin and the VSS pin, since the buffer control signal enX 16  is a logic low level in the normal mode, the NAND gates NAND 1  and NAND 2  operate like an inverter with respect to the signals applied to the package option pads PAD X4 and PAD X8 so that the package option signals sX 4  and sX 8  are a logic high (H) level and a logic low (L) level, respectively. As a result, the corresponding chip operates as the X4. On the other hand, in the test mode, since the buffer control signal enX 16  is enabled to a logic high (H) level, the NAND gates NAND 1  and NAND 2  block the signals applied to the package option pads PAD X4 and PAD X8 and always output a logic high level. Therefore, all of the package option signals sX 4  and sX 8  are a logic low (L) level, so that the corresponding chip operates as X16.  
         [0053]    In case of a default X8 package in which the package option pads PAD X4 and PAD X8 are respectively bonded with the VSS pin and the VDD pin, since the buffer control signal enX 16  is a logic low (L) level in the normal mode, the NAND gates NAND 1  and NAND 2  operate like an inverter with respect to the signals applied to the package option pads PAD X4 and PAD X8 so that the package option signals sX 4  and sX 8  are a logic low (L) level and a logic high (H) level, respectively. As a result, the corresponding chip operates as the X8. On the other hand, in the test mode, since the buffer control signal enX 16  is enabled to a logic high (H) level, the NAND gates NAND 1  and NAND 2  block the signals applied to the package option pads PAD X4 and PAD X8 and always output a logic high level. Therefore, all of the package option signals sX 4  and sX 8  are a logic low (L) level, so that the corresponding chip operates as X16.  
         [0054]    In case of a default X16 package in which all of the package option pads PAD X4 and PAD X8 are bonded with the VSS pin, since the buffer control signal enX 16  is a logic low level in the normal mode, the NAND gates NAND 1  and NAND 2  operate like an inverter with respect to the signals applied to the package option pads PAD X4 and PAD X8 so that all of the package option signals sX 4  and sX 8  are a logic low (L) level. As a result, the corresponding chip operates as the X16. On the other hand, in the test mode, since the buffer control signal enX 16  is enabled to a logic high (H) level, the NAND gates NAND 1  and NAND 2  block the signals applied to the package option pads PAD X4 and PAD X8 and always output a logic high level. Therefore, all of the package option signals sX 4  and sX 8  are a logic low (L) level, so that the corresponding chip operates as X16.  
         [0055]    A following table 3 is an operation table of an operation bandwidth in the normal mode and the test mode according to the package option (in case of using the enX 16 ).  
                                                                                                                                       TABLE 3                           PACKAGE   X4   X8   X16   X4   X8   X16            OPTION   NORMAL MODE   TEST MODE (enXl6 ″H″)                    PAD X4   VDD   VSS   VSS   VDD   VSS   VSS       PAD X8   VSS   VDD   VSS   VSS   VDD   VSS            SX4   H   L   L   L       SX8   L   H   L   L            OPERATION   X4   X8   X16   X16   X16   X16       BANDWIDTH                  
 
         [0056]    Referring to the table 3, in case of the normal mode, the operation bandwidth of the corresponding chip is determined according to the bonding state of the package option pads PAD X4 and PAD X8. However, in case of the test mode, the corresponding chip operates as the X16 without regard to the bonding state of the package option pads PAD X4 and PAD X8.  
         [0057]    A following table 4 is an address scramble of an SDRAM (DDR SDRAM) in the test mode in accordance with the circuit configuration of FIG. 7.  
                                                               TABLE 4                       ADDRESS   A0   A1   A2   A3   A4   A5   A6   A7   A8   A9   A11   A12                   X4 PACKAGE   Y0   Y1   Y2   Y3   Y4   Y5   Y6   Y7   Y8   Y9   NC   NC       X8 PACKAGE   Y0   Y1   Y2   Y3   Y4   Y5   Y6   Y7   Y8   Y9   NC   NC       X16 PACKAGE   Y0   Y1   Y2   Y3   Y4   Y5   Y6   Y7   Y8   Y9   NC   NC                  
 
         [0058]    In the normal mode, the address scramble is the same as the table 2.  
         [0059]    However, in the test mode, since all of the X4/X8/X16 packages input/output 16 data via the bonded pads, 10 Y addresses Y0 to Y9 are sequentially counted with respect to one word line. If the test is performed 1024 times, the entire cells connected to the word line can be screened. Therefore, in current maximum bandwidth (i.e., in case of the X16 product), the test time is not different from the prior art. However, in case of the X8 product, since the entire cells connected to one word line can be screen by performing the test 1024 times, the test time can be reduced to ½ of the prior art. In addition, in case of the X4 product, the test time can be reduced to ¼ of the prior art.  
         [0060]    [0060]FIG. 8 is a second exemplary circuit diagram of the buffer unit  62  in accordance with the first embodiment of the present invention.  
         [0061]    A difference between FIG. 8 and FIG. 7 is configurations of first and second buffer units  430  and  440 . The first buffer unit  430  includes: an inverter INV 5  receiving a signal applied to the package option pad PAD X4; and a NOR gate NOR 1  receiving the buffer control signal enX 16  outputted from the MRS control circuit  450  and an output of the inverter INV 5  to output the package option signal sX 4 . The second buffer unit  440  includes: an inverter INV 6  receiving a signal applied to the package option pad PAD X8; and a NOR gate NOR 2  receiving the buffer control signal enX 16  outputted from the MRS control circuit  450  and an output of the inverter INV 6  to output the package option signal sX 4 .  
         [0062]    Although the first and second buffer units  430  and  440  are implemented using the NOR gates, the buffer units operate in the same manner as those of FIG. 7 so that the operation table is also the same as the table 3. In other words, since the buffer control signal enX 16  is a logic low level in the normal mode, the NOR gates NOR 1  and NOR 2  operate like an inverter so that the package option signals sX 4  and sX 8  are determined according to the bonding state of the package option pads PAD X4 and PAD X8. On the other hand, in the test mode, since the buffer control signal enX 16  is enabled to a logic high (H) level, the NOR gates NOR 1  and NOR 2  block the signals applied to the package option pads PAD X4 and PAD X8. Therefore, all of the package option signals sX 4  and sX 8  are a logic low (L) level, so that the corresponding chip operates as X16.  
         [0063]    [0063]FIG. 9 is a third exemplary circuit diagram of the buffer unit  62  in accordance with the first embodiment of the present invention.  
         [0064]    [0064]FIG. 9 illustrates the case of outputting the buffer control signal enX 8  for selecting the X8 option in the test mode. A first buffer unit  530  includes: an inverter INV 7  receiving the buffer control signal enX 8 ; a NAND gate NAND 3  receiving an output of the inverter INV 7  and the signal applied to the package option pad PAD X4; and an inverter INV 8  receiving an output of the NAND gate NAND 3  to output the package option signal sX 4 . A second buffer unit  540  includes: an inverter INV 9  receiving the signal applied to the package option pad PAD X8; an inverter INV 10  receiving the buffer control signal enX 8 ; and a NAND gate NAND 4  receiving outputs of the inverters INV 9  and INV 10  to output the package option signal sX 8 .  
         [0065]    It is assumed that the package option pads PAD X4 and PAD X8 are respectively bonded with the VSS pin and the VSS pin so that the corresponding chip operates as the default X4. Since the buffer control signal enX 8  is a logic low (L) level in the normal mode, the package option signals sX 4  and sX 8  are respectively a logic high (H) level and a logic low (L) level so that the corresponding chip operates as the X4 package. Meanwhile, since the buffer control signal enX 8  is a logic high (H) level in the test mode, the package option signals sX 4  and sX 8  are respectively a logic low (L) level and a logic high (H) level so that the corresponding chip operates as the X8 package.  
         [0066]    A following table 5 is an operation table of an operation bandwidth in the normal mode and the test mode according to the package option (in case of using the enX 8 ).  
                                                                                                                       TABLE 5                                       X4   X8   X4   X8            PACKAGE   NORMAL       TEST MODE           OPTION   MODE       (enX8 ″H″)                    PAD X4   VDD   VSS   VDD   VSS       PAD X8   VSS   VDD   VSS   VDD            sX4   H   L   L       sX8   L   H   H            OPERATION   X4   X8   X8   X8       BANDWIDTH                  
 
         [0067]    Referring to the table 5, in case of the X4 product, since the entire cells connected to one word line can be screen by performing the test 1024 times, the test time can be reduced to ½ of the prior art. Meanwhile, in case where the above buffer control signal enX 8  is used in the X16 product, there is not profitable so that the table 5 does not consider the X16 product.  
         [0068]    [0068]FIG. 10 is a fourth exemplary circuit diagram of the buffer unit  62  in accordance with the first embodiment of the present invention.  
         [0069]    A difference between FIG. 10 and FIG. 9 is configurations of first and second buffer units  630  and  640 . The first buffer unit  430  includes an inverter INV 11  receiving the signal applied to the package option pad PAD X4, and a NOR gate NOR 3  receiving the buffer control signal enX 8  outputted from the MRS control circuit  650  and an output of the inverter INV 11  to output the package option signal sX 4 . The second buffer unit  640  includes a NOR gate NOR 4  receiving the signal applied to the package option pad PAD X8 and the buffer control signal enX 8  outputted from the MRS control circuit  650 , and an inverter INV 12  receiving an output of the NOR gate NOR 4  to output the package option signal sX 8 .  
         [0070]    Although the first and second buffer units  630  and  640  are implemented using the NOR gates, the buffer units operate in the same manner as those of FIG. 9 so that the operation table is also the same as the table 5. In other words, since the buffer control signal enX 8  is a logic low level in the normal mode, the NOR gates NOR 3  and NOR 4  operate like an inverter so that the package option signals sX 4  and sX 8  are determined according to the bonding state of the package option pads PAD X4 and PAD X8. On the other hand, in the test mode, since the buffer control signal enX 8  is enabled to a logic high (H) level, the NOR gates NOR 3  and NOR 4  block the signals applied to the package option pads PAD X4 and PAD X8. Therefore, the package option signals sX 4  and sX 8  are respectively a logic low (L) level and a logic (H) level, so that the corresponding chip operates as X8.  
         [0071]    [0071]FIG. 11 is a fifth exemplary circuit diagram of the buffer unit  62  using first and second MRS control circuits  750  and  760  in accordance with a first embodiment of the present invention, in which two buffer control signals enX 16  and enX 8  are used.  
         [0072]    Referring to FIG. 11, the first buffer unit  730  includes: a NOR gate NOR  5  receiving the first and second buffer control signals enX 16  and enX 8 ; a NAND gate NAND 5  receiving an output of the NOR 5  and the signal applied to the package option pad PAD X4; and inverter INV 13  receiving an output of the NAND gate NAND 5  to output the package option signal sX 4 . The second buffer unit  740  includes: an inverter INV 14  receiving the first buffer control signal enX 16 ; an inverter INV 15  receiving the second buffer control signal enX 8 ; a NAND gate NAND 6  receiving an output of the inverter INV 14  and the signal applied to the package option pad PAD X8; and a NAND gate NAND 7  receiving outputs of the NAND gate NAND 6  and inverter INV 15  to output the package option signal sX 8 .  
         [0073]    Hereinafter, an operation of the semiconductor memory device with the circuit of FIG. 11 will be described in detail.  
         [0074]    In the normal mode, since all of the first and second buffer control signals enX 16  and enX 8  are a logic low (L) level, all of the NAND gates NAND 5 , NAND 6  and NAND 7  operate like an inverter so that the package option signals sX 4  and sX 8  represent the signal levels corresponding to the default bandwidth according to the bonding states of the package option pads PAD X4 and PAD X8. As a result, the corresponding chip operations as the default bandwidth.  
         [0075]    In the test mode, the first and second buffer control signals enX 16  and enX 8  are selectively enabled.  
         [0076]    First, in case where the first buffer control signal enX 16  is enabled, since the first buffer control signal enX 16  is a logic high (H) level and the second buffer control signal enX 8  is a logic low (L) level, the NOR gate NOR 5  of the first buffer unit  730  outputs a logic low level. The NAND gate NAND 5  blocks the signal applied to the package option pad PAD X4 and outputs a logic high level. This signal is inverted by the inverter INV 13  and then outputted as the package option signal sX 4  of a logic low level. Meanwhile, the NAND gate NAND 6  of the second buffer  740  blocks the signal applied to the package option pad PAD X8 and outputs a logic high level. This signal is inverted by the NAND gate NAND 7  and then outputted as the package option signal sX 8  of a logic low level. Accordingly, the corresponding chip operates as the X16 in the test mode.  
         [0077]    Second, in case where the second buffer control signal enX 8  is enabled, since the first buffer control signal enX 16  is a logic low (L) level and the second buffer control signal enX 8  is a logic high (H) level, the NOR gate NOR 5  of the first buffer unit  730  outputs a logic low level. The NAND gate NAND 5  blocks the signal applied to the package option pad PAD X4 and outputs a logic high level. This signal is inverted by the inverter INV 13  and then outputted as the package option signal sX 4  of a logic low level. Meanwhile, the NAND gate NAND 7  of the second buffer  740  receives the logic low level via the inverter INV 15  so that the package option signal sX 8  of a logic high (H) level is outputted with regard to other inputs. Accordingly, the corresponding chip operates as the X8 in the test mode.  
         [0078]    A following table 6 is an operation table of an operation bandwidth in the normal mode and the test mode according to the package option (in case of using the enX 16  and the enX 8 ).  
                                                                                                                                                                           TABLE 6                                       X4   X8   X16   X4   X8   X4   X8   X16                NORMAL   TEST   TEST           MODE   MODE   MODE       PACKAGE   enX8 ″L″, enX16   enX8 ″L″,   enX8 ″8″, enX16       OPTION   ″L″   enX16 ″L″   ″L″                    PAD X4   VDD   VSS   VSS   VDD   VSS   VDD   VSS   VSS       PAD X8   VSS   VDD   VSS   VSS   VDD   VSS   VDD   VSS            SX4   H   L   L   L   L       SX8   L   H   L   H   L            OPERATION   X4   X8   X16   X8   X8   X16   X16   X16       BANDWIDTH                  
 
         [0079]    Referring to the table 6, in case of the product packaged in the default X4, if the package option signal enX 8  is enabled, the test time can be reduced to ½ of the prior art. If the package option signal enX 16  is enabled, the test time can be reduced to ¼ of the prior art.  
         [0080]    [0080]FIG. 12 is a sixth exemplary circuit diagram of the buffer unit  62  using first and second MRS control circuits  850  and  860  in accordance with a first embodiment of the present invention, in which two buffer control signals enX 16  and enX 8  are used.  
         [0081]    Referring to FIG. 12, the first buffer unit  830  includes: an inverter INV 16  receiving the signal applied to the package option pad PAD X4, and a 3-input NOR gate NOR 6  receiving an output of the inverter INV 16  and the first and second buffer control signals enX 16  and enX 8 . The second buffer  840  includes: an inverter INV 17  receiving the signal applied to the package option pad PAD X8; a NOR gate NOR 7  receiving an output of the inverter INV 17  and the first buffer control signal enX 16 ; a NOR gate NOR 8  receiving an output of the NOR gate NOR 7  and the second buffer control signal enX 8 ; and an inverter INV 18  receiving an output of the NOR gate OR 8  to output the package option signal sX 8 .  
         [0082]    Since the above circuit operates in the same manner as that of FIG. 11, a detailed description about that will be omitted. The operation table is also the same as the table 6. In accordance with the first embodiment of the present invention, it is possible to perform the package test with the bandwidth except for the default bandwidth without modification of wiring with respect to the package option pads. Accordingly, the time taken to modify the wiring can be saved. Meanwhile, in accordance with the first embodiment of the present invention, it is possible to reduce the test time so that the test can be performed with upper bandwidth than the default package, so that the test time is remarkably reduced. In this case, it is possible to perform the failure detection using one test program (for maximum bandwidth) without regard to the package option.  
         [0083]    [Second Embodiment] 
         [0084]    In the second embodiment of the present invention, there is proposed a buffer unit  62  using two package option pads PAD X4 and PAD X8. The buffer unit with a switching structure controlled by buffer control signals test_mode_X8z and test_mode_X4z buffers and outputs the signals applied to two package option pads PAD X4 and PAD X8 (normal mode), or provides the package option signals sX 4  and sX 8  corresponding to desired bandwidth (test mode).  
         [0085]    [0085]FIG. 13 is a circuit diagram of the package option signal generation circuit in accordance with a second embodiment of the present invention, showing the case wired with the default X16 product.  
         [0086]    Referring to FIG. 13, the package option signal generation circuit includes: a package option pad PAD X4 wire-bonded with VSS pin; a package option pad PAD X8 wire-bonded with the VSS pin; a test mode generation unit  310  for generating two buffer control signals test_mode_X8z and test_mode_X4z for selecting X8 and X4 package options in the test mode; and a buffer unit  300  for buffering the signals applied to the package option pads PAD X4 and PAD X8 in response to the two buffer control signals test_mode_X8z and test_mode —X 4z to output the buffered signals as the package option signals sX 4  and sX 8  (normal mode), or for providing the package option signals sX 4  and sX 8  corresponding to the desired bandwidth (test mode).  
         [0087]    The buffer unit  300  includes: a first buffer  302  for buffering an external signal applied to the package option pad PAD X4 to generate the package option signal sX 4 ; and a second buffer  304  for buffering an external signal applied to the package option pad PAD X8 to generate the package option signal sX 8 . Here, the first and second buffers  302  and  304  are respectively provided with two inverters connected in series to each other.  
         [0088]    In addition, the buffer  300  includes: first to third switching unit SW 1 , SW 2  and sW 3  performing a selective switching operation; a logic gate for logically combining the two buffer control signals test_mode_X8z and test_mode_X4z and controlling the first to third switching unit SW 1 , SW 2  and SW 3 . If the package option is two, there is needed only one package option pad and one buffer control signal. In this case, the logic gate for combining the buffer control signals is not needed. Therefore, in the buffer unit  300 , the others except for the first and second buffer  302  and  304  can be considered as the switching structure.  
         [0089]    The first switching unit SW 1  includes transmission gates TG 1  and TG 2  for transferring outputs of the first and second buffers  302  and  304  to an output stage in response to an output of a NAND gate NAND 1  receiving the buffer control signals test_mode —X 8z and test_mode_X4z. The transmission gates TG 1  and TG 2  receive an output of the NAND gate NAND 1  and an inverted signal outputted from an inverter INV 1  in the same polarity and are simultaneously turned on/off. The second switching unit SW 2  includes transmission gates TG 3  and TG 4  for transferring VSS and VDD to the output stage in response to the buffer control signal test_mode_X8z. The transmission gates TG 3  and TG 4  receive the buffer control signal test_mode_X8z and an inverted signal outputted from an inverter INV 2  in the same polarity and are simultaneously turned on/off. The third switching unit SW 3  includes transmission gates TG 5  and TG 6  for transferring VSS and VDD to the output stage in response to the buffer control signal test_mode —X 4z. The transmission gates TG 5  and TG 6  receive the buffer control signal test_mode_X4z and an inverted signal outputted from an inverter INV 3  in the same polarity and are simultaneously turned on/off.  
         [0090]    Here, the NAND gate NAND 1  can be implemented with an AND gate and an inverter, and can be replaced with other logic gates (for example, NOR gate). Further, the transmission gates TG 1  to TG 6  can be replaced with other switching devices (for example, MOS transistor).  
         [0091]    Hereinafter, an operation of the semiconductor memory device with the package option signal generation circuit will be described.  
         [0092]    First, in case of the normal mode, all of the buffer control signal test_mode_X8z and test_mode_X4z are a logic high level. Therefore, since an output of the NAND gate NAND 1  and an output of the inverter INV 1  are respectively a logic low level and a logic high level, two transmission gates TG 1  and TG 2  are turned on so that the buffer units  302  and  304  generate their outputs as the package option signals sX 4  and sX 8 . In FIG. 7, since the package option pads PAD X4 and PAD X8 are wire-bonded with the VSS pin so that the package option signals sX 4  and sX 8  are a logic low level, the chip operates as the X16.  
         [0093]    In the test mode, by enabling one of the buffer control signals test_mode_X8z and test_mode_X4z to a logic low level, the transmission gates TG 1  and TG 2  are tuned on by setting the outputs of the NAND gate NAND 1  and inverter INV 1  to a logic high level and a logic low level, respectively.  
         [0094]    In case where the buffer control signal test_mode_X8z is outputted in a logic high level and the buffer control signal test_mode_X4z is outputted in a logic low level, the transmission gates TG 1  and TG 2  of the first switching unit are all turned off so that the path of the first and second buffers  302  and  304  are blocked. Meanwhile, the transmission gates TG 3  and TG 4  of the second switching unit SW 2  are turned on so that the VSS and the VDD are outputted, respectively. At this time, the package option signals sX 4  and sX 8  are a logic low level and a logic high level, respectively, so that the chip operates as the X8.  
         [0095]    In case where the buffer control signal test_mode_X8z is outputted in a logic low level and the buffer control signal test_mode_X4z is outputted in a logic high level, the transmission gates TG 1  and TG 2  of the first switching unit are all turned off so that the path of the first and second buffers  302  and  304  are blocked. Meanwhile, the transmission gates TG 5  and TG 6  of the second switching unit SW 2  are turned on so that the VDD and the VSS are outputted, respectively. At this time, the package option signals sX 4  and sX 8  are a logic high level and a logic low level, respectively, so that the chip operates as the X4.  
         [0096]    A following table 7 is an operation table of an operation bandwidth in the test mode in the X16 package of the semiconductor memory device having the package option signal generation circuit in accordance with the second embodiment of the present invention.  
                                                     TABLE 7                                   X4   X8   X16                                        test_mode_X4   L   H   H           test_mode_X8   H   L   H           sX4   H   L   L           sX8   L   H   L                      
 
         [0097]    Referring to the table 7, in case where the default package is X16, if the buffer control signals test_mode_X4z and test_mode_X8z are respectively a logic low level and a logic high level, the corresponding package operates as the X4, so that a characteristic of the X4 package can be tested. If the buffer control signals test_mode_X4z and test_mode_X8z are respectively a logic high level and a logic low level, the corresponding package operates as the X8 so that a characteristic of the X8 package can be tested. In the present invention, the test mode means a test mode for changing the package option. The characteristic of the X16 package is tested in the normal mode state. Accordingly, with respect to one chip in which the default package is completed, it is possible to simply test a characteristic of other bandwidths as well as the default bandwidth without modifying the wiring.  
         [0098]    Meanwhile, although the table 7 illustrates the test mode operation in the X16 package, it is also applicable to the X8 package and the X4 package. For example, in the X8 package, the VSS pin and the VDD pin is wire-bonded with the package option pads PAD X4 and PAD X8, respectively. To control the test mode bandwidth, the buffer control signals test_mode_X4 and test_mode_X16z are used.  
         [0099]    Following tables 8 and 9 are operation tables of an operation bandwidth in the test mode in the X8 package and the X4 package, respectively. It is noted that the wire bonding is performed with respect to all the DQ pins as shown in FIG. 5 in case where the present invention is applied to the X8 package and the X4 package.  
                                                     TABLE 8                                   X4   X8   X16                                        test_mode_X4   L   H   H           test_mode_X1   H   H   H           sX4   H   L   L           SX8   L   H   L                      
 
         [0100]    [0100]                                                     TABLE 9                                   X4   X8   X16                                        test_mode_X8   H   L   H           test_mode_X1   H   H   L           sX8   H   L   L           SX8   L   H   L                        
         [0101]    In the first and second embodiments of the present invention, since the package test can be performed with the bandwidth except for the default bandwidth without modifying the wiring with respect to the package option pads, the time required to modify the wiring can be saved.  
         [0102]    Although the above embodiments describes the case the X4/X8/X16 package options are determined using the X4 PAD and the X8 PAD as the package option pad, the present invention is also applicable the case of using the X4 PAD and the X16 PAD as the package option pad or using the X8 PAD and the X16 PAD as the package option pad. In this case, combinations of the logic gates constituting the buffer unit can be varied.  
         [0103]    Meanwhile, the NAND gates used in the above embodiments can be implemented with an AND gate and an inverter, and the NOR gate can be implemented with an OR gate and an inverter.  
         [0104]    Further, the present invention is also applicable to the case the number of the package option pads increase or decreases according to the number of the operation bandwidth.  
         [0105]    According to the present invention, the test cost can be reduced so that the manufacturing cost can be reduced. Further, the test time is reduced so that the productivity is remarkably increased.  
         [0106]    While the present invention has been described with respect to certain preferred embodiments only, other modifications and variation may be made without departing from the spirit and scope of the present invention as set forth in the following claims.