Abstract:
An interconnect circuit for communicating data. The interconnect circuit including at least one driver to receive and transmit data. At least one termination device in communication with each driver. A first power supply having an output to supply power to the driver. A second power supply having an output to supply power to the termination device. A first decoupling capacitor in communication with the first power supply output and the second power supply output.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001]    This application claims the benefit of the filing date of U.S. provisional application No. 60/413891 filed Sep. 25, 2002, the content of which is herein incorporated by reference in its entirety. 
     
    
     
       TECHNICAL FIELD  
         [0002]    An aspect of this invention relates to power systems for high-frequency interconnect circuits.  
         BACKGROUND  
         [0003]    Today&#39;s electronics systems contain many complex integrated circuits operating at very high clock frequencies. Already today the data rates on the chip-to-chip interconnects operate at more than 300 Mb/s. It is expected that these data rates will approach 1 Gb/s in the next few years. At these data rates, chip-to-chip interconnects behave like RF transmission lines. As such, proper termination is a must. For longer distance interconnects, parallel termination is often used. Some well known examples include CPU to North Bridge chip interconnect, North Bridge to DDR (Double Data Rate SDRAM) memory interconnect and Graphic processor to DDR memory.  
           [0004]    As the width of interconnects gets wider, the amount of power needed to operate these transmission lines may become one of the largest power users of the systems. For example, an advanced graphic processor today may use a 256 bit wide interconnect to the DDR memory. The amount of current flowing through the termination resistors is so staggering that DC/DC converters are often used to provide the termination voltage.  
           [0005]    Conventional DC/DC converters typically do not provide fast enough response to the changing demand of the termination current. Even for interfaces running at 300 Mb/s data rates, the current loading may transition from almost zero to full power and back to zero in a matter of a few clock cycles when all of the data bits switch from zeroes to ones and back to zeroes. The problem that faces the DC/DC power supply for the termination voltage is also encountered at the DC/DC power supply for the driver circuits that drive the transmission line.  
           [0006]    [0006]FIG. 1 shows a conventional driver power system  10  that includes a driver power supply, V DDQ ,  12  and capacitor  13  to supply energy to high speed line drivers  14  (one of many shown), and a termination power supply, V TT ,  16  and capacitor  15  to supply energy to termination devices  18 .  
           [0007]    In operation, the drivers  16  draw current from the driver power supply  12  as a function of the state of the data lines  19 . Small currents flow when all or most of the data lines are in the low state. When most of the data lines are in the high state, a large DC load current flows. During a high load current mode, the current flows from the V DDQ  power supply  12  through the termination resistors  18 , and into the termination power supply  16 , which sinks the current. The current flowing into the V TT  power supply  16  from the V DDQ  power supply  12  is negative and about one-half the magnitude of the current flowing out of the V DDQ  power supply  12 .  
           [0008]    When the data lines  19  switch to the low state, the current from the V DDQ  power supply  12  to the termination resistors  18  virtually immediately decreases to zero. This causes the voltage output from the V DDQ  power supply  12  to spike upwards, causing the V DDQ  power supply to transition to an emergency transient recovery mode to protect the power supply output from increasing beyond the voltage regulation limits. Almost simultaneously, the current through the V TT  power supply  16  reverses in direction, causing the voltage of the V TT  power supply  16  to spike downwards, sending the V TT  power supply  16  into an emergency transient recovery mode to prevent the V TT  power supply voltage from decreasing below the voltage regulation limits. The emergency V TT  emergency transient recovery operation in return may cause a huge transient current to flow back into the V DDQ  power supply  12 , further exasperating the voltage spike at the output of the V DDQ  power supply  12 . The magnitude of the power supply fluctuations during the transient load changes may be decreased by employing high speed DC/DC converters for the V TT  and V DDQ  power supplies  12  and  16 . However, the magnitude of the power supply fluctuations may still be significant and high speed DC/DC converters are generally very costly.  
         SUMMARY  
         [0009]    An interconnect circuit for communicating data. The interconnect circuit including at least one driver to receive and transmit data. At least one termination device in communication with each driver. A first power supply having an output to supply power to the driver. A second power supply having an output to supply power to the termination device. A first decoupling capacitor in communication with the first power supply output and the second power supply output.  
           [0010]    The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. 
       
    
    
     DESCRIPTION OF DRAWINGS  
       [0011]    [0011]FIG. 1 is a block diagram of a conventional high-frequency interconnect circuit.  
         [0012]    [0012]FIG. 2 is a block diagram of an aspect of a high-frequency interconnect circuit.  
         [0013]    [0013]FIG. 3 shows waveforms associated with an aspect of a high-frequency interconnect circuit.  
         [0014]    [0014]FIG. 4 is a two-dimensional view of an aspect of a high-frequency interconnect circuit mounted on a printed circuit board (PCB). 
     
    
       [0015]    Like reference symbols in the various drawings indicate like elements.  
       DETAILED DESCRIPTION  
       [0016]    [0016]FIG. 2 shows an aspect of a power system  20  for supplying power to one or more high-speed drivers  24 . The drivers  24  may be employed in interconnect systems that operate at data rates where interconnections may behave as transmission lines. A driver power supply  22  with a filter capacitor  32  may supply power to the high-speed drivers  24 . A termination power supply  26  with a filter capacitor  34  may supply power to the termination devices  28 .  
         [0017]    The present invention recognizes that the transient load response of the power system  20  may be dramatically improved by connecting a decoupling capacitor, C 1 ,  30  between the V TT  power supply  26  and the V DDQ  power supply  22 . In addition, the size of the filter capacitors  32  and  34  between ground and the power supplies  22  and  26  may be greatly reduced or eliminated. The capacitance of the decoupling capacitor  30  may be equal to or much greater than the capacitance of the filter capacitor  34 . Intuitively, this would seem to aggravate the power supply output voltage glitch problem. However, including the decoupling capacitor  30  actually may drastically reduce any need for using very high speed DC/DC converters and the size of the filter capacitors  32  and  34 . In fact, including the decoupling capacitor  30  may simultaneously solve the power regulation problems seen by both the V DDQ  and V TT  power supplies  22  and  26 . The decoupling capacitor  30  may be any type of high-frequency capacitance device such as ceramic capacitors, silicon-based capacitors, and the like.  
         [0018]    [0018]FIG. 3 shows waveforms associated with the operation of an aspect of the power system  20 . A first waveform  50  shows the current flowing into the drivers  24 . A second waveform  52  shows the output voltage of the VDDQ power supply  22 . A third waveform  54  shows the current flowing through the decoupling capacitor, C 1 ,  30 .  
         [0019]    In operation, when the data on the data lines  29  is all or mostly ones, a large DC current, I 1 , flows from the V DDQ  power supply  22  to the drivers  24  and through the termination resistors  28  to the V TT  power supply  26 . About half of the DC current flows back from the V TT  power supply  26  to the V DDQ  power supply  22 .  
         [0020]    When the data switches to all or mostly zeroes, the current flowing into the drivers  24  almost instantly decreases to zero. However, the current flowing from the V DDQ  power supply  22  may not immediately decrease to zero due to limitations of the power supply  22  such as parasitic inductances and a finite transient load response. The decoupling capacitor  30  provides a transient current path, I 0 , for the current flowing from the V DDQ  power supply  22 . The current flows from the V DDQ  power supply  22 , through the decoupling capacitor  30 , through the termination resistors  28 , and finally through the drivers  24 . As the output voltage of the V TT  power supply  22  begins to drift upwards due to the finite value of the decoupling capacitor  30 , the V TT  power supply  26  starts to respond. Since the decoupling capacitor  30  provides an alternate current path, the V TT  power supply  22  does not have to respond as fast to load current changes to prevent output voltage spikes. Also, since the V TT  power supply  26  is able to respond slower to load changes than in power systems that do not include the decoupling capacitor  30 , the V DDQ  power supply  22  does not have to respond as fast to load changes either.  
         [0021]    The power system  20  is preferably implemented on an assembly  40  such as a printed circuit board (PCB) as shown in FIG. 4. The assembly  40  may include a V TT  power plane  42  and a V DDQ  power plane  44  to distribute power from the V TT  and V DDQ  power supplies  22  and  26  respectively. The V TT  power plane  42  is preferably laid next to the V DDQ  power plane  44 . Insulating layers  48  may separate the power planes  42  and  44 . Arranging the V TT  power plane  42  next to the V DDQ  power plane  44  may advantageously increase the distributed capacitance between V TT  and V DDQ  adding further capacitance in shunt with the decoupling capacitor  30 .  
         [0022]    In conventional power systems, the V TT  power plane is typically referred to a ground plane leading to an increase in the distributed capacitance between the V TT  power plane and the ground plane, but almost no increase between the V TT  power plane and the V DDQ  power plane.  
         [0023]    Data lines  46  on the PCB  40  may also be routed adjacent to the V TT  power plane  44  to indirectly increase the effective decoupling capacitance  30 . The data lines  46  may be formed on a signal layer that is adjacent to the V TT  power plane  44 . The data lines  46  may also be formed as a portion of the V TT  power plane  44 .  
         [0024]    A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.