Abstract:
In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

Description:
This application claims the benefit of provisional patent application Ser. No. 60/843,305 filed on Sep. 8, 2006, and entitled “Fully Integrated AC Coupling Circuit with Hybrid Stable Common Mode Generation and Zero Load Kick Back Immune Baseline Wander Compensation” which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to the field of data transmission and more particularly to circuits for on-chip AC coupling, stable common-mode voltage generation and baseline wander compensation for high-speed receivers. The invention can provide a full suite AC coupling solution including AC coupling, common mode generation, and baseline wander compensation. The solution can be fully integrated, meaning it is all on-chip, does not require any off-chip components, and meets the stringent requirements of preceding a DFE based high-speed transceiver. 
     2. Description of the Related Art 
     In high-speed transceiver design, AC coupling in the channel between the transmitter and the receiver connection is typically preferred and is often required for the functioning of the transmission link. This is particularly true for decision feedback equalization (DFE) based receivers. The DFE receiver operates as a nonlinear equalizer, and is effective to recover data that have been severely damaged by channel loss, reflections and high-frequency crosstalk. Such receivers are particularly useful in high speed backplane transceivers of 6 Gbps and beyond, especially for challenging applications that involve long-range legacy channels. A DFE receiver functions by subtracting the inter-symbol interference (ISI) arising from previously detected data from data that is being currently received. A receiver of this type is susceptible to noise and fluctuations in the DC and low frequency contents of the signal. AC coupling is an effective way of removing the ineluctable common-mode voltage mismatch and the low frequency disturbance. Such coupling insulates the DFE receiver from the channel, and allows for separate receiver common-mode voltage optimization from the transmitter. 
     One phenomenon that is a problem in an AC coupled system is baseline wander (BLW), which is signal dependent and varies over time. BLW affects the low frequency contents of the received signal and can cause errors in the detected data. The baseline wander is even more severe for an on-chip AC coupled system. This is due to the high AC coupling corner frequency resulting from the small devices that can be afforded on-chip. 
     The BLW in an on-chip AC coupled system must be mitigated for reliable link functioning. In the prior art, baseline wander compensation can be partitioned into the following major categories: DSP (digital signal processing) based; adaptive equalizer based; peak-detector based; and quantized feedback methods. 
     Digital BLW compensators, exemplified by U.S. Pat. No. 6,415,003, cancel baseline wander effects in the digital domain. The entire signal processing including the BLW compensation and the equalization are done by DSP algorithms. A high-resolution ADC is required to detect the tiny BLW change over time. This type of compensator is not practical for multi-Gbps transceivers using current CMOS technology, due to the unrealistic simultaneous requirements of ultra high-speed and high-resolution ADC. 
     The adaptive equalizer based BLW compensator, exemplified by U.S. Pat. No. 6,047,026, treats the baseline wander as a common source of ISI, and uses adaptive FIR or IIR filters to cancel BLW. For the FIR case, this type of compensator would require a large number of filter taps, that may be on the order of thousands, to track the tiny slowly varying baseline change. One solution to this problem is to use an IIR unit inside the DFE FIR filter to deal with the BLW. However, the BLW correction interacts and brings difficulty to the DFE adaptation loop. Both methods are not suitable for high-speed transceivers because of associated cost or interference. 
     The peak-detector based BLW compensators, exemplified by U.S. Pat. No. 5,940,442, are based on the assumption that the baseline wander is the dominating source of error. The amount of baseline wander is controlled by detecting the peak pulse against a predetermined threshold voltage, and subtracting the low-pass filtered version of the pulse. The scheme works well on equalized data. But when large amount of channel-limiting ISI coexist, the nonlinearly subtracted feedback peak-currents includes both the BLW and the channel-limiting ISI information. As a result, the ISI can not be linearly passed to the next stage, and is permanently damaged for DFE. These compensators are not suitable for our application. 
     Quantized feedback theory for baseline wander compensation is well known and is exemplified by U.S. Pat. No. 5,699,386. However, previous arts in this category are limited to simple circuits, wherein little signal processing is done between the AC coupling corner and the quantization device. Critical circuit issues such as stable common-mode voltage maintenance, mitigation of high-frequency feed-through from the quantized feedback, and prevention of excess current and capacitive loading from the baseline restoration circuit are not addressed. 
     When implementing a BLW correction circuit in the signal path before a DFE receiver, a number of design considerations preclude the use of existing methods such as those referred to above. These design considerations include the following: 
     1) A well defined common-mode voltage is needed before the DFE. The common-mode voltage has fundamental impact on the key performance measures of an analog circuitry, including linearity, bandwidth, signal-swing and many others. The DFE functions only when the transistors are biased in the saturation region. The common-mode voltage (Vcm) has to be stable, to guarantee consistent performance and maintain the dynamic range. 
     2) The clock feed-through or kick-back noise from the BLW correction circuit to the high-speed signal path needs to be mitigated. This is even more critical if DFE is used. If unprotected, the high frequency noise appears as jitter and distortion, and damages the data for proper DFE. 
     3) The current loading to the high-pass filter output node has to be well controlled. In a high-speed SERDES, the clock is recovered from the received data. The high-pass filter corner frequency has to be sufficiently low in order to pass through enough information to set up the timing loop before the BLW loop setup. The high-pass transfer function is given by H hp (s)=sRC/(1+sRC). With a limited size capacitor available on the chip, the equivalent impedance R has to be large to maintain the corner frequency. 
     4) The capacitive loading must be minimized, because of the difficult return-loss and bandwidth requirement at multi-Gbps high data rate. The total parasitic budget drops quickly with the increase of the transmission rate. At 6.4 Gb/s, even with the favorite exact resistive matching, it is far from comfortable to accommodate all the essential elements without damage returnloss performance. Zero additional capacitive loading is the prerequisite of BLWC for 6.4 Gb/s+ transceivers. It is desirable for the capacitive loading from the BLW correction circuitry to be exempt from the high-speed signal path. 
     In view of the above, it would be desirable to offer a complete integrated AC coupling solution for applications of both DC balanced and non-DC balanced transmission. It would also be beneficial to provide a better technique for BLW correction that does not impose clock feed-through to the high-speed data path, and does not add extra capacitive or resistive loading. Moreover, it would be desirable to offer on-chip common-mode voltage generation and maintenance that is not dependent on gain, temperature or other IC process variations. 
     SUMMARY OF THE INVENTION 
     The current invention provides an AC coupling solution that uses a hybrid circuit structure for simultaneously providing both baseline wander compensation and common-mode voltage generation and maintenance. Embodiments of the invention are fully integrated, that is, are included in the same IC as the receiver of a transceiver system, such as a high-speed transceiver. In a useful embodiment, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high impedance linear network, such as a single large resistor, is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the high impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the voltage level of received data. This voltage correction circuit is controlled by the feedback of data that is detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. A reference voltage is used to set the common-mode voltage. In one embodiment associated with a receiver having an input signal, a compensation circuit is provided that comprises a first feedback loop. The first feedback loop is adapted to receive a feedback signal, corresponding to data detected from the receiver input signal, and is further adapted to generate a specified correction component in response to the received feedback signal. The circuit further comprises a second feedback loop configured to generate a common-mode voltage that is determined by a reference voltage generator associated with the receiver. A mechanism combines the correction component with the common-mode voltage, in order to provide a reconstructed low frequency component for the receiver input signal. 
     A fully-integrated AC-coupling circuit with hybrid common-mode voltage (Vcm) generation and BLW compensation is proposed. The on-chip generated Vcm eliminates the requirement of an extra chip-pin and additional board-supply for the common-mode voltage, and offers the maximum freedom for circuit optimization. In addition, the heavy penalty resulted from large by-pass capacitors typically required in conventional on-chip Vcm-generation-circuit is avoided. Additional circuitry is included to cancel the BLW by feedback of the recovered data readily available in the receiver. Unlike the previous methods, the proposed circuit mitigates the contamination to the sensitive high-speed data from the high-frequency kick-back noise inherent to the quantized feedback. It also imposes ‘zero’ resistive or capacitive loads to the AC-coupling node. These qualities are of primary concern for 6.4 Gb/s+ high-speed transceivers, where the incoming signal is small and highly sensitive to noise and interference, and the difficult return-loss performance critically depends on the total parasitic capacitance seen at the pin. Endorsed by the little resistive loading, low intrinsic AC-coupling corner frequency for clock recovery can be implemented with limited on-chip capacitor. The circuit is particularly useful for compensation of BLW immersed in excess channel-limiting ISI, where most previous methods fail. A data compressor is offered for parallel to single-bit conversion to extend the application to the popular parallel data recovery architectures. A formula is provided to compute the proper BLW feedback gain. With the proposed circuit inside the receiver, both DC and AC-coupled paths can exist simultaneously for the optimal operation of all circuits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
         FIG. 1  is a block diagram showing components of a high speed receiver, together with a circuit comprising an embodiment of the invention that is fully integrated with the receiver. 
         FIG. 2  is a block diagram showing the embodiment of  FIG. 1  in greater detail. 
         FIG. 3  is a table exemplifying values that may be selected for baseline wander correction gain settings, in the embodiment of  FIG. 1 . 
         FIG. 4  is a block diagram showing a further embodiment of the invention that uses data compression. 
         FIGS. 5 and 6  are block diagrams showing respective components for the embodiment of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION 
     With reference now to  FIG. 1 , there is shown a block diagram depicting a receiver  100 , provided with a circuit  102  comprising an embodiment of the invention. Receiver  100  usefully comprises the receiver in a high speed backplane transceiver, such as a transceiver operating at 6 Gbps or greater, but the invention is not limited thereto. Moreover, all components of receiver  100  including circuit  102  are usefully integrated together on a single chip or IC. As a further feature, the input signal to the receiver, coupled from the transmitter through a transmission channel, usefully comprises a differential input having positive and negative analog voltage components, RXDP and RXDN, respectively, and a common-mode voltage. The input signal is equal to (RXDP−RXDN), and the common-mode voltage associated with the components is (RXDP+RXDN)/2. 
     Referring further to  FIG. 1 , there is shown the receiver input signals RXDP/RXDN coupled to an input buffer  106  through capacitors  104   a  and  b , respectively. Thus, the receiver input signal is AC-coupled to buffer  106 , so that only the AC components of input signal RXDP/RXDN, comprising Vinp and Vinn, respectively, are connected to input buffer  106 . Capacitors  104   a  and  b  also substantially diminish the low frequency component of input signal RXDP/RXDN coupled to buffer  106 . Buffer  106  is shown to include a clock/data recovery unit (CDRU), and further includes receiver equalizers, such as a linear equalizer, and/or a decision feedback equalizer (DFE). The CDRU detects and recovers both data content and the clock information from the input signal Vinp/Vinn, to thereby provide digital output signal DATA and its complementary DATA_BAR (DATAB), and the associated clock signal CLKOUT. These signals are coupled to additional receiver circuits (not shown) as are required for receiver operation.  FIG. 1  also shows buffer  106  provided with a termination voltage  108 , termination resistors  110   a  and  110   b , and ESD protection  114 . 
     As discussed above, baseline wander (BLW) is a significant problem in on-chip AC coupled systems, such as receiver system  100  shown in  FIG. 1 . BLW affects the low frequency contents of the received signal and can cause errors in the detected data. Accordingly, to provide correction for BLW, circuit  102  is coupled to the receiver input, through high impedance linear resistive networks  116   a  and  116   b . As hereinafter described in connection with  FIG. 2 , circuit  102  is used in producing a reconstructed data signal to cancel effects of baseline wander in the receiver input signal. In addition, circuit  102  is a hybrid circuit that also generates an optimal common-mode voltage for the reconstructed signal. The reconstructed signal includes the differential components Vcmp and Vcmn, which are connected through high impedance resistive networks  116   a  and  116   b , and combined with receiver inputs Vinp and Vinn, respectively. The combined signals thus comprise the complete receiver input signal RXDP/RXDN, wherein the effects of baseline wander have been canceled from such input signal. Also, the common-mode voltage that was removed from the original receiver input signal, by the coupling capacitors  104   a  and  b , is replaced by the optimal common-mode voltage provided by the reconstructed signal. 
     In the configuration shown by  FIG. 1 , the input to circuit  102  is provided by signals BLWCP and BLWCN, which are coupled back to circuit  102  from the digital output data signals DATA/DATAB. 
       FIG. 1  further shows circuits of receiver  100  that need the AC-coupled input signal Vinp/Vinn, collectively represented in  FIG. 1  as item  118 . Similarly, circuits of receiver  100  that need the DC-coupled input signal RXDP/RXDN are collectively represented in  FIG. 1  as item  120 . As further discussed hereinafter, by placing the capacitor  104  within or integral to receiver  100 , the need for a capacitor external to the IC containing receiver  100 , in order to provide AC-coupling to the receiver input signal, is eliminated. 
     Referring to  FIG. 2 , there is shown a baseline wander correction and voltage generation circuit  200 , wherein circuit  200  comprises circuit  102  and the connected impedance networks  116   a  and  116   b , as described above in connection with  FIG. 1 . Thus, circuit  200  receives the digital feedback signals BLWP and BLWN, as likewise described above.  FIG. 2  also collectively represents the components  108 ,  110   a ,  110   b  and  114  of  FIG. 1  as ESD Protection and termination circuitry  226 . 
       FIG. 2  further shows digital feedback signal BLWP coupled to operate a switch  202   a  in circuit  200 , so that switch  202   a  is opened when BLWP is a digital 0 and is closed when BLWP is 1. Switch  202   a  is connected in series with an enable switch  204   a , operated by BLWC enable  206 . Thus, when enable switch  204   a  is closed and BLWP is 1, a current i blwc  flows through the switches to a summer  208   a . The current i blwc  is supplied by a BLWC gain control  210 , and coupled through a current-mode digital-to-analog (D/A) converter  212 . When BLWP is 0, switch  202   a  is open and the current i blwc  cannot flow. Accordingly, as digital bits of feedback signal BLWP are successively applied to operate switch  202   a , a pulsed current i cp  flows through switch  202   a , wherein the current i cp  represents the receiver recovered data content. BLWN is complementary to BLWP. BLWN operates a switch  202   b , similar to operation of switch  202   a , to provide pulsed current i cn . 
     The low frequency amplitude of the receiver input signal can be corrected for baseline wander effects by applying a BLWC correction gain thereto. The required BLWC correction gain can be determined from the transmitter (TX) amplitude swing and the DC loss of the transmission channel, by the following relationship:
 
BLW correction gain=TX swing/10^(channel DC loss in dB/20)  Eqn. (1)
 
     From Eqn. (1), correction gain values can be computed for use with circuit  200 . For example,  FIG. 3  comprises a table showing 16 pre-programmed settings for BLW correction gain. In its operation, BLWC gain control  210  selects the gain value from the table that is closest to the BLW correction gain calculated using Eqn. (1). Gain control  210  then generates a current i blwc  that is proportional to or otherwise represents the selected gain value. Thus, current i blwc  is adapted to compensate for BLW in the receiver input signal. 
     Referring further to  FIG. 2 , there are shown summers  208   a  and  208   b  adding the currents i cp  and i cn , respectively, to a current i cm , which represents the common-mode voltage as described hereinafter. The combined currents are then converted to voltages Vcmp and Vcmn, by respective current-to-voltage (I/V) converters  214   a  and  214   b . Vcmp is connected through high impedance linear network  116   a  to receiver input Vinp. Similarly, Vcmn is connected through high impedance linear network  116   b  to receiver input Vinn.  FIG. 2  shows networks  116   a  and  116   b  comprising resistors R. 
     It is thus seen that certain elements of circuit  200 , together with buffer  106 , form a feedback loop to produce the signal Vcmp/Vcmn. These elements include switches  202   a  and  202   b , switches  204   a  and  204   b , summers  208   a  and  208   b , I/V converters  214   a  and  214   b , and the impedance networks  116   a  and  116   b . Relationships pertaining to the operation of this feedback loop are set forth hereinafter. Moreover, by providing the signal Vcmp/Vcmn with BLW correction gain, and by then combining Vcmp/Vcmn with the input signal Vinp/Vinn, BLW effects in the input signal are corrected or compensated for. 
     In order to generate the current i cm , representing the common-mode voltage, circuit  200  further includes a programmable generator  216 , for supplying a reference voltage Vref. Usefully, generator  216  comprises a resistor ladder (not shown) consisting of identical elements. The ladder is connected between the power supply and ground of circuit  200 , and has multiple tap points controlled by switches to provide adjustability of the output voltage. Generator  216  is thereby programmable to provide a particular value of Vref, by coupling a digital command thereto through a Vref control  218 . The digital command may be supplied by a bit register or the like. The Vref value provided for a particular application is coupled from the Vref generator  216  to an input of a comparator, such as operational amplifier  220 . 
       FIG. 2  further shows a common-mode voltage detection circuit  222  placed between the P and N gain-adjusted feedback paths described above. Detection circuit  222  determines the common-mode voltage between Vcmp and Vcmn, such as by computing the value (Vcmp+Vcmn)/2. This value is applied to comparator  220  as a second input, and is thus compared with reference voltage Vref. Accordingly, the output of comparator  220  represents the difference between Vref and the detected voltage. Such output is used to dynamically adjust a common-mode current injection circuit  224 , which produces current i cm  coupled to summers  208   a  and  208   b.    
     It is thus seen that generator  216 , comparator  220  and circuits  222  and  224 , together with summers  208   a  and  208   b  and I/V converters  214   a  and  214   b , form a second feedback loop that maintains a steady common-mode voltage between the voltages Vcmp and Vcmn produced by the first feedback loop, as described above. It is to be emphasized that the common-mode voltage has profound impact on the functioning of an analog circuit. Such voltage affects the linearity, bandwidth, signal swing and many other key performance measures. The on-chip common-mode voltage generation and maintenance provided by circuit  200  eliminates the requirement to have an extra chip pin and additional board power supply for the common-mode of the AC-coupled path. Since the common-mode voltage generated on-chip is programmable and can be set by register bits, it significantly enhances freedom of circuit operation and optimization. 
     In describing operation of the feedback loops of circuit  200 , it is to be understood that R pflt  and R nflt  are the resistances of high impedance networks  116   a  and  116   b , respectively, where R pflt =R nflt =R. R p  and R n  are the respective resistances of I/V converters  214   a  and  214   b , and R 1  and R 2  are the resistances of detection circuit  222 . The following are valid for these resistance values:
 
R p =R n &lt;&lt;R 1 =R 2   Eqn. (2)
 
R 1 =R 2 &lt;&lt;R nflt =R pflt   Eqn. (3)
 
     If C PVCM  is the parasitic capacitance seen at the voltage node Vcmp and Vcmn, V feedback  is reconstructed by BLWCP/BLWCN routed to circuit  200 , and V in  is the input receiver signal (RXDP−RXDN) before the AC-coupling capacitors  104   a  and  b , then in the frequency domain the complete reconstructed signal V(s) is given by: 
     
       
         
           
             
               
                 
                   
                     V 
                     ⁡ 
                     
                       ( 
                       s 
                       ) 
                     
                   
                   ≅ 
                   
                     
                       
                         sRC 
                         
                           1 
                           + 
                           sRC 
                         
                       
                       ⁢ 
                       Vin 
                     
                     + 
                     
                       
                         1 
                         
                           1 
                           + 
                           sRC 
                         
                       
                       · 
                       
                         1 
                         
                           1 
                           + 
                           
                             
                               sR 
                               p 
                             
                             ⁢ 
                             
                               C 
                               pvcm 
                             
                           
                         
                       
                       · 
                       G 
                       · 
                       
                         V 
                         feedback 
                       
                     
                   
                 
               
               
                 
                   Eqn 
                   . 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     4 
                     ) 
                   
                 
               
             
           
         
       
     
     In Equation (4) G denotes the feedback gain. Assuming the feedback latency is much smaller than the AC coupling time-constant, and the feedback gain G is tuned to match the Vin low-frequency amplitude, then at steady state the following approximation is true: 
                       V   ⁡     (   s   )       ≅         sRC     1   +   sRC       ⁢   Vin     +       1     1   +   sRC       ·     1     1   +       sR   p     ⁢     C   pvcm           ·   Vin         ⁢     
     ⁢         Given   ⁢           ⁢       R   p     ·     C   pvcm       ⁢       &lt;&lt;     R   nfilt       ·     C     a   ⁢           ⁢   c           =   RC     ;             Eqn   .           ⁢     (   5   )                     V   ⁡     (   s   )       ≅         sRC     1   +   sRC       ⁢   Vin     +       1     1   +   sRC       ⁢   Vin         =   Vin           Eqn   .           ⁢     (   6   )                 
Therefore, the high-speed signal V(S) is reconstructed without loss of information.
 
     To emphasize features of the embodiment shown by circuit  200 , it is noted that the P and N feedback voltage is first filtered by the low-pass filter formed naturally by the parasitic capacitor and total impedance seen at the node. The corner frequency of this filter is typically several orders higher than the AC coupling corner frequency. It filters the high-frequency noise and jittering from the digital feedback signal and other coupling sources. Then the feedback signal is further heavily low-pass filtered by the high-impedance element and the AC coupling capacitors  104   a  and  104   b , and adds the residual voltage adjustment to the high-speed data line to cancel out the baseline wander accumulation in real time as previously described. The high-pass filtering of the high-speed input signal and the dominant low-pass filtering of the feedback signal enjoys the same corner frequency since they are formed by the same set of circuit elements, that is, capacitors  104   a  and  104   b  and high impedance resistive network  116   a / 116   b . The feedback correction voltage is developed locally in the common-mode generation circuitry from current pulses. The high-impedance element  116   a / 116   b  is used to connect the correction to the high-speed data line, so that no significant current is drawn. The intrinsic AC coupling corner frequency is related to the time-constant formed by the AC capacitor and the high-impedance element, and can be made low with limited on-chip capacitance. The parasitic capacitance loading from the Vcm generation and BLW cancellation circuit  200  is greatly attenuated by the high-impedance element. The high-speed data line is also immune from the clock-feedthrough or kick-back noise from the digital feedback signal. The kick-back noise is by-passed by the much lower impedance path to the gnd/power supply, and would not traverse the high-impedance path to the highly sensitive high-speed data line. 
     These qualities are of primary concern for high-speed transceivers of multi-Gbps and beyond, where the received signal is small and highly sensitive to noise and interference, and the difficult return-loss performance is critically dependent on the total parasitic capacitance seen at the pin. The low intrinsic high-pass AC coupling corner frequency is important in the system where the clock has to be recovered from the received data, which is the case for most Gbps Serdes standards. 
     Besides the features mentioned above, the fully integrated complete AC coupling solution provided by embodiments of the invention offers other important advantages. Compared with external AC coupling, it possible that only a selective set of the circuitries on the receiver are AC coupled. DC coupled paths could coexist by tapping directly to the input pin. As a result, circuit functions that would benefit from DC coupling can be implemented. 
     Referring to  FIG. 4 , there is shown a receiver configuration  400  which includes circuit  102 , and is very similar to receiver  100  shown in  FIG. 1 . However, receiver  400  includes a buffer  402  with receiver equalizers and a CDRU that has a parallel data recovery receiver architecture. Thus, the CDRU provides output data signals DATA and DATAB in parallel multi-bit form, such as the form of four parallel bits. However, feedback signals BLWCP and BLWCN, comprising information content of the signals DATA and DATAB and required for BLW correction, as described above, must be in the form of serialized single bits. This form is necessary, since the feedback content must be converted to analog form by circuit  102 , as likewise described above. 
     Accordingly,  FIG. 4  shows a data compressor  404  coupled to receive the N-bit output data signal DATA. Compressor  404  is also shown by  FIG. 5 , in further detail. The de-serialized N-bit output data is coupled at a frequency n times slower than the input data from the CDRU, and is combined together by data compressor  404  to generate the single-bit feedback data signal BLWCP/N for BLW correction. 
     Referring to  FIG. 6 , there is shown a data compressor implementation example for 4-bit parallel data. The implementation consists of a look-up table  602  and a counter  604 , for generating correct data for each 4-bit pattern. 
     The description of the preferred embodiment of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.