Abstract:
A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention provides a common pass gate layout of a D flip-flop, and more particularly, a common pass gate layout capable of increasing layout density. 
   2. Description of the Prior Art 
   In order to design a circuit more efficiently, logic cell libraries composed of commonly used logic circuits are used in the prior art. According to different requirements, a designer must select adaptive logic cell libraries to synthesize logic circuits. In the logic cell libraries, a layout of a master-slave D flip-flop is very important because it occupies a noticeable area in a random logic synthesis block. 
   Please refer to  FIG. 1 , which illustrates a schematic diagram of a prior art master-slave D flip-flop  10 . The master-slave D flip-flop  10  includes terminals D, CK, Q, and QB for performing a logic operation, which is well known by those skilled in the art, and will not be narrated in detail. As shown in  FIG. 1 , the master-slave D flip-flop  10  includes four common pass gates  12 ,  14 ,  16 , and  18 , composed by eight MOS (metal oxide semiconductor) transistors, whose gate signals CK 1  and CKB are provided by a cell&#39;s internal clock buffer  19 . Both of the signals CK 1  and CKB are transmitted to two p and two n MOS transistors. In a chip implemented by standard logic cell libraries, the master-slave D flip-flop may need a considerable layout area. However, the prior art does not include an efficient method for laying the master-slave D flip-flop, so that chip density is low, and system resources are wasted. 
   SUMMARY OF THE INVENTION 
   It is therefore a primary objective of the claimed invention to provide common pass gate layouts of D flip-flops. 
   An exemplary embodiment of a common pass gate layout a D flip-flop comprises a first n diffusion region, a second n diffusion region, a first poly-silicon conductor, a second poly-silicon conductor, a first p diffusion region, a second p diffusion region, a third poly-silicon conductor, a fourth poly-silicon conductor, a first clock output pin, and a second clock output pin. The first poly-silicon conductor extends from the first n diffusion region to the second n diffusion region, and is utilized for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively. The second poly-silicon conductor extends from the first n diffusion region to the second n diffusion region, and is utilized for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively. The first p diffusion region is adjacent to the second n diffusion region. The third poly-silicon conductor extends from the first p diffusion region to the second p diffusion region, and is utilized for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively. The fourth poly-silicon conductor extends from the first p diffusion region to the second p diffusion region, and is utilized for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively. The first clock output pin is coupled to the first poly-silicon conductor and the fourth poly-silicon conductor, and utilized for outputting a first clock signal. The second clock output pin is coupled to the second poly-silicon conductor and the third poly-silicon conductor, and utilized for outputting a second clock signal. 
   An exemplary embodiment of a common pass gate layout a D flip-flop comprises a first semiconductor cell, a second semiconductor cell, a fifth poly-silicon conductor, and a sixth poly-silicon conductor. The first semiconductor cell comprises a first n diffusion region, a second n diffusion region, a first poly-silicon conductor, a second poly-silicon conductor, a first p diffusion region, a second p diffusion region, a third poly-silicon conductor, and a fourth poly-silicon conductor. The first poly-silicon conductor extends from the first n diffusion region to the second n diffusion region, and is utilized for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively. The second poly-silicon conductor extends from the first n diffusion region to the second n diffusion region, and is utilized for forming two gates by bisecting the first n diffusion region and the second n diffusion region respectively. The first p diffusion region is adjacent to the second n diffusion region. The third poly-silicon conductor extends from the first p diffusion region to the second p diffusion region, and is utilized for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively. The fourth poly-silicon conductor extends from the first p diffusion region to the second p diffusion region, and is utilized for forming two gates by bisecting the first p diffusion region and the second p diffusion region respectively. The second semiconductor cell comprises a first clock output pin and a second clock output pin. The first clock output pin is utilized for outputting a first clock signal. The second clock output pin is utilized for outputting a second clock signal. The fifth poly-silicon conductor extends from the first clock output pin to the first poly-silicon conductor and the fourth poly-silicon conductor. The sixth poly-silicon conductor extends from the second clock output pin to the second poly-silicon conductor and the third poly-silicon conductor. 
   An exemplary embodiment of a semiconductor layout comprises a p substrate, a first semiconductor cell, and a second semiconductor cell. The first semiconductor cell is formed over the p substrate. The second semiconductor cell is formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell. 
   These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  illustrates a schematic diagram of a prior art master-slave D flip-flop. 
       FIG. 2  illustrates a schematic diagram of a common pass gate layout of a D flip-flop in accordance with a first embodiment of the present invention. 
       FIG. 3  illustrates a schematic diagram of a common pass gate layout of a D flip-flop in accordance with a second embodiment of the present invention. 
   

   DETAILED DESCRIPTION 
   The present invention increases layout density of a D flip-flop with a common pass gate layout. 
   Please refer to  FIG. 2 , which illustrates a schematic diagram of a common pass gate layout  20  of a D flip-flop in accordance with a first embodiment of the present invention. The common pass gate layout  20  includes a first n diffusion region  202 , a second n diffusion region  204 , a first p diffusion region  206 , a second p diffusion region  208 , a first poly-silicon conductor  210 , a second poly-silicon conductor  212 , a third poly-silicon conductor  214 , a fourth poly-silicon conductor  216 , a first clock output pin  218 , and a second clock output pin  220 . Both of the first poly-silicon conductor  210  and the second poly-silicon conductor  212  extend from the first n diffusion region  202  to the second n diffusion region  204 , and bisect the first n diffusion region  202  and the second n diffusion region  204  to form four n MOS transistors. Similarly, both of the third poly-silicon conductor  214  and the fourth poly-silicon conductor  216  extend from the first p diffusion region  206  to the second p diffusion region  208 , and bisect the first p diffusion region  206  and the second p diffusion region  208  to form four p MOS transistors. The first clock output pin  218  outputs a clock signal to the first poly-silicon conductor  210  and the fourth poly-silicon conductor  216 , and the second clock output pin  220  outputs another clock signal to the second poly-silicon conductor  212  and the third poly-silicon conductor  214 . 
   In the common pass gate layout  20 , each poly-silicon conductor forms two MOS transistors. Therefore, the common pass gate layout  20  includes four n and four p MOS transistors. Both of the first clock output pin  218  and the second clock output pin  220  transmit the clocks signals (CK 1  and CKB) to two p and two n MOS transistors to implement the common pass gate of the D flip-flop. By forming two MOS transistors with a poly-silicon conductor, the present invention can efficiently lay the common pass gate on a semiconductor cell. However, when compressing the semiconductor cell, there must be spaces between units of the semiconductor cell for preventing inter-effect between the units. In this case, the common pass gate layout  20  cannot be compressed efficiently. Therefore, the present invention further provides another embodiment to solve the above problem. 
   Please refer to  FIG. 3 , which illustrates a schematic diagram of a common pass gate layout  30  of a D flip-flop in accordance with a second embodiment of the present invention. The common pass gate layout  30  includes a first semiconductor cell  300  and a second semiconductor cell  302 . The first semiconductor cell  300  includes a first n diffusion region  304 , a second n diffusion region  306 , a first p diffusion region  308 , a second p diffusion region  310 , a first poly-silicon conductor  312 , a second poly-silicon conductor  314 , a third poly-silicon conductor  316 , and a fourth poly-silicon conductor  318 . Both of the first poly-silicon conductor  312  and the second poly-silicon conductor  314  extend from the first n diffusion region  304  to the second n diffusion region  306 , and bisect the first n diffusion region  304  and the second n diffusion region  306  to form four n MOS transistors. Similarly, both of the third poly-silicon conductor  316  and the fourth poly-silicon conductor  318  extend from the first p diffusion region  308  to the second p diffusion region  310 , and bisect the first p diffusion region  308  and the second p diffusion region  310  to form four p MOS transistors. The second semiconductor cell  302  includes a first clock output pin  320  and a second clock output pin  322  for outputting clock signals (CK 1  and CKB). The common pass gate layout  30  further includes a fifth poly-silicon conductor  324  and a sixth poly-silicon conductor  326 . The fifth poly-silicon conductor  324  extends from the first clock output pin  320  to the first poly-silicon conductor  312  and the fourth poly-silicon conductor  318 , and the sixth poly-silicon conductor  326  extends from the second clock output pin  322  to the second poly-silicon conductor  314  and the third poly-silicon conductor  316 . 
   As shown in  FIG. 3 , the common pass gate layout  30  is a layout with double cell height, and includes four common pass gates in the first semiconductor cell  300  and output terminals of the clock signals in the second semiconductor cell  302 . Therefore, when compressing the common pass gate layout  30 , a height H 2  of the second semiconductor cell  302  is adjusted based on a height H 1  of the first semiconductor cell  300 . That is, if the first semiconductor cell  300  cannot be compressed to half the height of the common pass gate layout  30 , a designer can reduce the height H 2  of the second semiconductor cell  302 , so as to lay the first semiconductor cell  300  and the second semiconductor cell  302  within the required height, and construct a high-density cell library. 
   In summary, the common pass gate layout of the present invention can increase layout density, decrease layout area, and save system resources. 
   Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.