Abstract:
A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

Description:
PARTIES TO A JOINT RESEARCH AGREEMENT 
     International Business Machines Corporation, a New York corporation, Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement 
     BACKGROUND 
     1. Field of the Invention 
     This invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other materials, and to methods for manufacturing such devices. 
     2. Description of Related Art 
     Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change. 
     Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access. 
     The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and by reducing the size of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element. 
     One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000. 
     Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, and a method for manufacturing such structure 
     SUMMARY 
     Generally, the invention features a memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes. In embodiments of a memory cell device of the invention, the top electrode includes a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. The area of electrical contact is defined by the dimensions of the stem of the electrode, near the base, and not by the dimensions of the memory material, which can have a significantly greater area. The dimensions of the stem portion of the top electrode, and of the area of contact of the base of the stem with the memory material can according to the invention be made very small, and are not dependent upon masking technologies. 
     In one general aspect, the invention features a memory cell device including a bottom electrode, a memory material element over the bottom electrode, and a top electrode including a body portion and a stem portion, in which a base of the stem portion of the top electrode is in electrical contact with a small area of a surface of the memory material. 
     In another general aspect the invention features a method for making a memory cell device, by: forming a bottom electrode layer over a surface of a substrate; forming a memory material layer over the bottom electrode layer; forming a cap layer over the memory material layer; patterning the bottom electrode layer, the memory material layer and the cap layer to define a bottom electrode overlain by a memory element overlain by a cap; forming an intermetal dielectric fill layer over the memory material; forming an etch stop layer over the dielectric fill; forming a via through the etch stop layer and the dielectric fill to expose a surface of the cap, the via including an opening in the etch stop layer; removing a quantity of dielectric fill material from walls of the via, forming a cavity and resulting in an undercut beneath the margin of the opening in the etch stop layer; depositing a thermal isolation material in the cavity over the surface of the memory material, whereby a void is formed in the thermal isolation material; anisotropically etching the thermal isolation material and the cap to expose a small area of the surface of the memory material, forming a pore in the thermal isolation material and the cap adjacent the memory element and a wider cavity in the thermal isolation material; and depositing an electrode material in the pore and the wider cavity to form the top electrode. 
     According to the invention, a masking step establishes the openings in the silicon nitride layer over the memory cell vias. The remainder of the process is self-aligning, and highly repeatable. The area of contact between the top electrode and the memory material is determined by width of the stem portion of the top electrode, which in turn is determined by anisotropic etch conditions and by the size and shape of the void in the thermal insulator, which can be readily and repeatably controlled. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagrammatic sketch in a sectional view showing a memory cell device according to an embodiment of the invention. 
         FIGS. 2-10  are sketches in a sectional view showing stages in a process for making a phase change memory cell according to an embodiment of the invention. 
         FIGS. 11A and 11B  are sketches in a sectional view showing a portion of a memory array according to an embodiment of the invention;  FIG. 11B  shows a programming current flow. 
         FIG. 12  is a schematic diagram for a memory array having phase change memory elements. 
         FIG. 13  is a diagrammatic sketch in a layout or plan view showing a part of a memory array having phase change memory elements. 
     
    
    
     DETAILED DESCRIPTION 
     The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGs. illustrating embodiments of the invention, features corresponding to features shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGs. 
     Turning now to  FIG. 1 , there is shown generally at  10  a memory cell structure according to an embodiment of the invention. Memory cell structure  10  includes a bottom electrode  12  overlain by a memory element  14 , a top electrode  18  including a body portion  19  and a stem portion  17 . The stem portion  17  of the top electrode  18  is in contact with a small area  13  of the surface  15  of the memory material layer  14 . The top electrode may optionally include a core portion  21  and a liner (heater) portion  23 . The top electrode  18  is surrounded by a thermal isolation material  16 . The top electrode and the surrounding thermal isolation material are formed within a via in an interlayer dielectric fill, or separation layer,  11 , which is overlain by an electrically insulative layer  20 . 
     The memory cell structure  10  is formed over a semiconductor substrate including access transistors, and electrical connection of the surface  22  of the top electrode  18  is made by way of patterned metallization, as described for example below with reference to  FIG. 11A . 
     The conductive path in the memory cell passes from the surface  22  of the top electrode  18  through the top electrode body portion  19  and the top electrode stem portion  17  and then into the memory element  14  at the area of contact  13  of the base of the stem portion  17  with the surface of the memory element  14 , then through the memory element to the bottom electrode  12 . 
     This memory cell structure according to the invention provides several advantageous features. The top electrode is well isolated thermally from the surrounding dielectric fill. The area of contact of the top electrode with the memory material is small, so that the reset program current can be reduced. The area of contact between the top electrode and the memory material is determined by width of the stem portion of the top electrode, which in turn is determined by anisotropic etch conditions and by the size and shape of the void in the thermal insulator. The size of the void in the thermal insulator is determined by the width of an undercut  320  at the margin of the opening in the electrically insulative layer, which can be readily and repeatably controlled. 
     Embodiments of memory cell device  10  include phase change based memory materials, including chalcogenide based materials and other materials, for memory material  14 . Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly. 
     Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In the disclosure herein, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory device described herein is Ge 2 Sb 2 Te 5 . 
     With reference again to  FIG. 1 , access circuitry, such as described with reference to  FIG. 12 , can be implemented to contact the first electrode  12  and the second electrode  18  in a variety of configurations for controlling the operation of the memory cell, so that it can be programmed to set the phase change material  14  in one of the two solid phases that can be reversibly implemented using the memory material. For example, using a chalcogenide-based phase change memory material, the memory cell may be set to a relatively high resistivity state in which at least a portion of the bridge in the current path is an amorphous state, and a relatively low resistivity state in which most of the bridge in the current path is in a crystalline state. For example, application of an electrical pulse having a suitable shorter, high amplitude profile, for example, results in changing the phase change material  14  locally to a generally amorphous state, as indicated at  29  in  FIG. 1 . 
     Manufacture of a memory cell device  10  will be described with reference to  FIGS. 2-10 , in which various stages in an exemplary process are shown in sectional view. 
     Referring to  FIG. 2 , a layer  212  of a material suitable as a bottom electrode is formed over a surface  211  of a substrate  210 ; a layer  214  of a phase change memory material is formed over the bottom electrode material layer  212 ; and a layer  226  of a protective cap material is formed over the layer  214  of phase change memory material. 
     The bottom electrode material layer  212  may be formed by a thin film deposition technique such as, for example, sputtering or atomic layer deposition onto surface  211  of the substrate  210 . A suitable bottom electrode layer  212  may include layers of two or more materials, selected for their properties, among others, of adhesion to materials on adjacent layers. The bottom electrode layer  212  may include, for example, a film of titanium, followed by a film of titanium nitride on the surface of the titanium film. Titanium adheres well to materials in the underlying semiconductor substrate (such as a silicide); and titanium nitride adheres well to the overlying GST phase change material. Additionally, titanium nitride serves as a good diffusion barrier. A wide variety of materials can be used for the bottom electrode, including for example Ta, TaN, TiAlN, TaAlN; or the material of the bottom electrode may include one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni and Ru, and alloys thereof; or may include a ceramic. The conditions of the deposition processes are established to provide suitable thickness of, and coverage by, the material(s) of the electrode layer, and to provide good thermal isolation. The bottom electrode at the surface of the substrate may have a thickness in a range about 200 nm to about 400 nm. 
     The layer  214  of phase change memory material may be formed over the bottom electrode layer  212  by a thin film deposition technique such as, for example, sputtering or atomic layer deposition. The conditions of the deposition processes are established to provide a suitable thickness of the phase change material layer over the bottom electrode. The phase change material layer at the surface of the bottom electrode over the substrate may have a thickness in a range about 20-200 nm. 
     The protective cap layer  226  protects the underlying phase change memory material during subsequent processes. Suitable materials for the protective cap layer  226  include, for example, silicon nitride, SiO 2 , Al 2 O 3 , Ta 2 O 5 , and the layer may be formed by, for example a CVD or PVD process. The protective cap layer  226  may have a thickness in the range about 5 nm to about 50 nm. Formation of the bottom electrode layer, the phase change memory material layer, and the protective cap layer results in a structure as shown in  FIG. 2   
     Then a mask and etch process is used to define a bottom electrode  12  overlain by a phase change material element  14  and a cap  326  approximately at the site  30  of the memory cell, resulting in a structure as shown in  FIG. 3 . The cap  326 , which has a surface  315 , protects the phase change material element during the mask and etch process and, particularly, in some embodiments, during removal (stripping) of the photoresist. 
     Then, an interlayer dielectric fill is formed over the surface of the substrate and over the patterned bottom electrode, memory element, and cap, and an etch stop layer is formed over the interlayer dielectric fill. The interlayer dielectric fill may include, for example, a low-K dielectric material such as silicon dioxide, silicon oxynitride, silicon nitride, Al 2 O 3 , or other low K dielectric. Alternatively, the material of the interlayer dielectric fill may include one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. The material of the etch stop layer may include, for example, silicon nitride. Vias are formed through the etch stop layer and the dielectric fill, using a mask and etch process.  FIG. 4  shows a resulting memory cell via  200 , formed through the etch stop layer  20 , and the dielectric fill layer  211 . The via reaches to the surface  315  of the cap  326  over the phase change material element  14 . Then, a wet etch process, such as, for example, a hydrofluoric acid dip, is applied to undercut the dielectric fill material and to widen the cavity  300  in the dielectric fill  11 , as shown in  FIG. 5 . 
     The dimensions of the completed memory cell will be determined in part by the dimensions of the memory cell via and, particularly, in part by the extent of the undercut, as described with reference particularly to  FIGS. 6 and 7 , below. 
     The interlayer dielectric fill may have a thickness in a range about 100 nm to about 300 nm, and the silicon nitride layer may have a thickness in a range about 10 nm to about 40 nm. The via  200  may have a width in a range about 30 nm to about 300 nm. The size of the opening  220  through the silicon nitride layer is established, within a variation (typically +/−about 20 nm for example), by the design rules for the particular lithographic process used to form the via  200 . The diameter  220  of the opening in the silicon nitride layer may be generally circular, for example, with a diameter  220  about 200 nm +/−about 20 nm, for example. The material of the etch stop layer  20  is selected to be selectively etched relative to the dielectric fill material; that is, the wet etch process that removes the dielectric material to form the undercut  320  may have substantially no effect on the etch stop layer  20 . Where silicon dioxide is the dielectric fill material, for example, silicon nitride provides a suitable material for the etch stop layer. The extent of the undercut can be controlled by timing the wet etch process, within a variation typically +/−about 1.5 nm, for example. The conditions of the wet etch are established to provide an undercut  320  having a width  321  in a range about 5 nm to about 50 nm beneath the margin in the opening of the silicon nitride layer, resulting in a width  311  of the cavity  300  about the sum of the width  220  of the opening in the silicon nitride layer plus 2 times the width  321  of the undercut  320 . 
     The protective cap layer  326  may protect the underlying phase change memory element  14  during the etch process that forms the via  200 , and during the wet etch process that widens the cavity  300  in the dielectric fill. 
     Then a suitable thermal isolation material is formed over the structure of  FIG. 5 , and within the via, using a conformational deposition process such as a chemical vapor deposition (CVD), resulting in a structure as shown  FIG. 6 . The geometry of the undercut, and the conditions of the deposition process, result in formation of a void  610  in the thermal isolation material  600 . The void  610  is approximately centered within the cavity in the memory cell via. The shape and width  613  of the void (or diameter, where the void is generally round, for example circular) is related to the width of the undercut  320 ; for example, where the opening  220  in the etch stop layer  20  is generally circular, for example, the void can be expected to be generally circular, and can be expected to have a diameter  613  about two times the width of the undercut  321 . 
     Suitable thermal isolation materials  600  include dielectric materials, and may be an oxide, such as a silicon dioxide, for example. Other thermal isolation materials may be preferred, and selection of a thermal isolation material depends in part on the material of the interlayer dielectric fill; particularly, thermal isolation material  600  is a better thermal insulator than the interlayer dielectric fill  11 , preferably at least 10% better. Therefore, when the interlayer dielectric comprises silicon dioxide, the thermal insulator  600  preferably has a thermal conductivity value “kappa” less than that of silicon dioxide, which is 0.014 J/cm*K*sec. Representative materials for thermal insulator  600  include low permittivity (low-K) materials, including materials that are a combination of the elements silicon (Si), carbon (C), oxygen (O), fluorine (F), and hydrogen (H). Examples of thermally insulating materials which are candidates for use as thermal insulator  600  include SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for thermal insulator  600  include fluorinated SiO 2 , silsesquioxane, polyarylene ethers, parylene, fluoropolymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. A single layer or combination of layers can provide thermal insulation. In other preferred embodiments, the thermal insulator has a thermal conductivity less than that of the amorphous state of the phase change material, that is, less than about 0.003 J/cm*K*sec where the phase change material is a GST. 
     Then an anisotropic etch is performed, such as a reactive ion etch, to remove some of the thermal isolation material. The etch proceeds until an area of the surface of the cap  316  is exposed, and then proceeds until an area  13  of the surface  15  of the phase change element  14  is exposed. In some embodiments a first etch is performed under conditions that remove the thermal isolation material, and a second etch is performed under conditions that remove a portion of the cap (different etch chemistries may be used, for example).  FIG. 7  shows a resulting structure. All the thermal isolation material overlying the etch stop layer  20  has been removed; and some of the thermal isolation material has been removed from the cavity in the memory cell via forming a pore  712  near the surface of the phase change material, which will define the stem portion of the top electrode; and a wider cavity  710 , which will define the body portion of the top electrode The undercut  320  protects the thermal isolation material beneath it, leaving a residual portion  720  adjacent the wall of the cavity and adjacent the portion of the phase change material next to the wall of the cavity. The etch is stopped when a small area  13  of the surface of the phase change material is exposed at the bottom of the pore  712 ; a residual portion  722  remains after the etch is stopped, and this defines the shape and dimensions of the pore  712 . The dimensions of the stem portion of the top electrode—and, consequently, the area of the contact of the top electrode with the phase change material—are determined in part by the position and the size of the void and by the deposition conformality of the thermal insulator material  600 . Particularly, the width of the exposed small area  13  (diameter, if the area is circular, for example) of the phase change material  14  exposed at the bottom of the pore  712  results from the shape and width  713  of the pore  712 , which in turn results from the shape and size of the void, as well as from the conditions of the etch. As noted above, the width (or diameter) of the void relates to the width of the undercut, and is not dependent upon the width of the via; typically the width of the void is about twice the width of the undercut. The position of the void (and, consequently, the position of the pore  712 ) is approximately at the center of the via and, because the memory material element has a significantly greater area, it is not necessary for the via to be precisely aligned with the memory material element. 
     The exposed small area  13  need not have any particular shape; it may, for example, be generally round (e.g., circular) or it may have some other shape, or it may have an irregular shape. Where the small area is circular, for example, the small area  13  may have a diameter in a range about 10 nm to about 100 nm, such as about 20 nm to about 50 nm, for example about 30 nm. Under conditions described herein, these dimensions may be expected where the width of the undercut is in a range about 5 nm to about 50 nm, such as about 10 nm to about 25 nm, for example about 15 nm. 
     Then the top electrode is formed in the memory cell cavity. In embodiments as shown in the FIGs., the top electrode includes a core surrounded by a liner (heater). In such embodiments, the liner is formed by depositing a suitable liner material over the structure of  FIG. 7 , resulting in a structure as shown in  FIG. 8 . The liner material fills the pore  712 , forming the stem portion  17  of the top electrode; and forms a film  723  over the other surfaces of the structure. Suitable liner materials include, for example, tantalum nitride, titanium nitride, tungsten nitride, TiW. The conditions of the deposition processes are established to provide suitable thickness of, and coverage by, the material(s) of the electrode layer. Then the core of the top electrode is formed by depositing a suitable electrode material within the cavity and over the structure of  FIG. 7 , as shown at  900  in  FIG. 9 . The core material may be deposited by, for example, chemical vapor deposition (CVD). The top electrode  900  may be, for example, tungsten. Other suitable top electrode core materials include, for example, other metals such as copper, platinum, ruthenium, iridium, and alloys thereof. 
     A wide variety of materials can be used for the top electrode, including for example Ta, TaN, TiAlN, TaAlN; or the material of the top electrode may include one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni and Ru, and alloys thereof; or may include a ceramic. 
     Then a planarizing process is used to remove the upper material, down to the surface  922  of the silicon nitride layer  20 , resulting in a completed memory cell structure as shown in  FIG. 10 . 
       FIG. 11A  shows a sectional view of two phase change random access memory cells  100 ,  102  according to the invention. The cells  110 ,  102  are formed on a semiconductor substrate  110 . Isolation structures such as shallow trench isolation (“STI”) dielectric trenches  112  isolate pairs of rows of memory cell access transistors in the substrate. The access transistors are formed by common source region  116  in the substrate  110 , and drain regions  115  and  117  in the substrate  112 . Polysilicon word lines  113  and  114  constitute the gates of the access transistors. Common source line  119  is formed over the source region  116 . A first dielectric fill layer  111  is deposited over the polysilicon word lines and the common source line on the substrate  110 . Contact plugs  103 ,  104  (e.g., tungsten) are formed in vias in the fill layer  111  over the drain regions. Memory cells  100 ,  102  are formed, generally as described above with reference to  FIGS. 2-10 , and the memory cells  101 ,  102  are structured generally each like memory cell  10  as described with reference to  FIG. 1 : a bottom electrode material layer is deposited over the first dielectric fill layer, a memory material layer is deposited over the bottom electrode material layer, and a protective cap material layer is deposited over the memory material layer; the layers are patterned to form bottom electrode in contact with the contact plug, memory elements over the bottom electrode, and a cap over the memory element; a second dielectric fill layer  121  is deposited over these structures, an etch stop layer  120  is deposited over the second dielectric fill layer, and the etch stop layer and second dielectric fill are masked and etched to form vias and then wet etched to form cavities with undercuts beneath the margins of the via openings in the etch stop layer; then the thermal isolation material is deposited in the cavities (forming voids), anisotropic etch is formed through the thermal isolation material and the cap to form a cavity and to expose a small area of the surface of the memory element; the top electrode is formed in the cavity; the upper surface of the structure is planarized, and bit line  141  is formed over the memory cells, in contact with the upper surfaces of the top electrodes. 
       FIG. 11B  shows a programming current path (arrow  129 ) through memory cells according to the invention, as described with reference to  FIGS. 1 and 11A . The current flows from the M1 common source line  119  to the source region  116 , then to the drain region  115 , and from the drain region  115  through the contact plug  103  to the memory cell  100  and through the memory cell  100  to the bit line  141 . 
       FIG. 12  is a schematic illustration of a memory array, which can be implemented as described herein. In the schematic illustration of  FIG. 2 , a common source line  128 , a word line  123  and a word line  124  are arranged generally parallel in the Y-direction. Bit lines  141  and  142  are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block  145  are coupled to the word lines  123 ,  124 . An X-decoder and a set of sense amplifiers in block  146  are coupled to the bit lines  141  and  142 . The common source line  128  is coupled to the source terminals of access transistors  150 ,  151 ,  152  and  153 . The gate of access transistor  150  is coupled to the word line  123 . The gate of access transistor  151  is coupled to the word line  124 . The gate of access transistor  152  is coupled to the word line  123 . The gate of access transistor  153  is coupled to the word line  124 . The drain of access transistor  150  is coupled to the bottom electrode member  132  for memory cell  135 , which has top electrode member  134 . The top electrode member  134  is coupled to the bit line  141 . Likewise, the drain of access transistor  151  is coupled to the bottom electrode member  133  for memory cell  136 , which has top electrode member  137 . The top electrode member  137  is coupled to the bit line  141 . Access transistors  152  and  153  are coupled to corresponding memory cells as well on bit line  142 . It can be seen that in this illustrative configuration the common source line  128  is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data. 
       FIG. 13  is a layout or plan view of a memory array as shown in the schematic diagram of  FIG. 12 , showing the structure above the semiconductor substrate layer  110  of  FIG. 11A . Certain of the features are omitted, or are shown as transparent. Word lines  123 ,  124  are laid out substantially parallel to the source line  28 . Metal bit lines  141  and  142  are laid out over, and substantially perpendicular to, the word lines. The positions of memory cell devices  135  below the metal bit lines are indicated, although they would not be visible in this view. 
     Embodiments of memory cell device  10  include phase change based memory materials, including chalcogenide based materials and other materials, for memory material  14 . Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te a Ge b Sb 100−(a+b) . One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky &#39;112 patent, columns 10-11.) Particular alloys evaluated by another researcher include Ge 2 Sb 2 Te 5 , GeSb 2 Te 4  and GeSb 4 Te 7 . (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”,  SPIE  v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky &#39;112 at columns 11-13, which examples are hereby incorporated by reference. 
     The invention has been described with reference to phase change materials. However, other memory materials, also sometimes referred to as programmable materials, can also be used. As used in this application, memory materials are those materials having electrical properties, such as resistance, that can be changed by the application of energy; the change can be a stepwise change or a continuous change or a combination thereof. Other programmable resistive memory materials may be used in other embodiments of the invention, including N 2  doped GST, Ge x Sb y , or other material that uses different crystal phase changes to determine resistance; Pr x Ca y MnO 3 , PrSrMnO, ZrOx, or other material that uses an electrical pulse to change the resistance state; 7,7,8,8-tetracyanoquinodimethane (TCNQ), methanofullerene 6,6-phenyl C61-butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse. Further examples of programmable resistive memory materials include GeSbTe, GeSb, NiO, Nb—SrTiO 3 , Ag—GeTe, PrCaMnO, ZnO, Nb 2 O 5 , Cr—SrTiO 3 . 
     For additional information on the manufacture, component materials, use and operation of phase change random access memory devices, see U.S. patent application Ser. No. 11/155,067, filed 17 Jun. 2005, titled “Thin film fuse phase change RAM and manufacturing method”. 
     Other embodiments are within the scope of the invention.