Abstract:
A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates generally to through-wafer vias and more particularly to the formation of through-wafer vias that have high-aspect ratios. 
       BACKGROUND OF THE INVENTION 
       [0002]    In a conventional semiconductor wafer, there is a need to form through-wafer vias that electrically connect from a top surface of the semiconductor wafer to a bottom surface of the semiconductor wafer (hence the name through-wafer vias). If through-wafer vias have high-aspect ratios (i.e., the heights of through-wafer vias are much greater than their widths), the through-wafer vias are very difficult to form. Therefore, there is a need for a method to form the through-wafer vias that is better than the method of the prior art. 
       SUMMARY OF THE INVENTION 
       [0003]    The present invention provides a structure, comprising (a) a wafer which includes (i) an opening and (ii) a top wafer surface, wherein the top wafer surface defines a first reference direction perpendicular to the top wafer surface; and (b) a through-wafer via in the opening, wherein the through-wafer via has a shape of a rectangular plate, wherein a height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction, wherein a length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction, wherein said height of the through-wafer via is at least ten times greater than said width of the through-wafer via, wherein the second reference direction and the third reference direction are perpendicular to each other, and wherein the second reference direction and the third reference direction are both perpendicular to the first reference direction. 
         [0004]    The present invention provides a method to form through-wafer vias that is better than the method of the prior art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]      FIGS. 1A-1G  show top down views and cross-section views of a semiconductor structure going through different steps of a via fabrication process, in accordance with embodiments of the present invention. 
           [0006]      FIG. 2A  shows a top down view of a through-wafer via structure, in accordance with embodiments of the present invention. 
           [0007]    FIG.  2 A′ shows a perspective view of the through-wafer via structure of  FIG. 2A , in accordance with embodiments of the present invention. 
           [0008]      FIG. 2B  shows a top down view of a through-wafer via system, in accordance with embodiments of the present invention. 
           [0009]      FIG. 2C  shows a top down view of a through-wafer via system of  FIG. 2B , in accordance with embodiments of the present invention. 
           [0010]      FIG. 3A  shows a top down view of another through-wafer via, in accordance with embodiments of the present invention. 
           [0011]      FIG. 3B  illustrates a top down view of a through-wafer via structure utilizing the through-wafer via of  FIG. 3A , in accordance with embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0012]      FIGS. 1A-1G  show top down views and cross-section views of a semiconductor structure  100  going through different steps of a via fabrication process, in accordance with embodiments of the present invention. 
         [0013]    More specifically, with reference to  FIG. 1A  (top down view), the via fabrication process starts with a semiconductor structure  100  which comprises a silicon wafer  105  and a through-wafer via trench  110  in the silicon wafer  105 . The through-wafer via trench  110  can be formed by lithographic and etching processes. 
         [0014]    In one embodiment, a length  110   b  of the through-wafer via trench  110  is much larger (e.g., at least ten times greater) than a width  110   a  of the through-wafer via trench  110 . For example, the width  110   a  can be 4 μm, whereas the length  110   b  can be at least 40 μm. 
         [0015]    FIG.  1 Ai shows a cross section view of the semiconductor structure  100  of  FIG. 1A  along a first line  1 Ai- 1 Ai, in accordance with embodiments of the present invention. In one embodiment, a depth  110   c  of the through-wafer via trench  110  is about 180 μm or about one fourth a thickness  105   a  of the silicon wafer  105 . 
         [0016]    FIG.  1 Aii shows a cross section view of the semiconductor structure  100  of  FIG. 1A  along a second line  1 Aii- 1 Aii, in accordance with embodiments of the present invention. In one embodiment, the depth  110   c  of the through-wafer via trench  110  is at least ten times the width  110   a  of the through-wafer via trench  110 . 
         [0017]    Next, with reference to FIG.  1 Bi, in one embodiment, a dielectric layer  115  is formed on exposed surfaces of the semiconductor structure  100  of FIG.  1 Ai. The dielectric layer  115  can comprise silicon dioxide. In one embodiment, the dielectric layer  115  can be formed by CVD (Chemical Vapor Deposition) of silicon dioxide on top of the exposed surfaces of the semiconductor structure  100  of FIG.  1 Ai. Alternatively, the dielectric layer  115  can be formed by thermally oxidizing the exposed surfaces of the semiconductor structure  100  of FIG.  1 Ai. 
         [0018]    FIG.  1 Bii shows the semiconductor structure  100  resulting from the formation of the dielectric layer  115  on the exposed surfaces of the semiconductor structure  100  of FIG.  1 Aii. 
         [0019]    Next, with reference to FIG.  1 Ci, in one embodiment, a through-wafer via layer  120  is formed on top of the semiconductor structure  100  of FIG.  1 Bi (including in the through-wafer via trench  110 ). The through-wafer via layer  120  can comprise tungsten. The through-wafer via layer  120  can be formed by CVD of tungsten on top of the semiconductor structure  100  of FIG.  1 Bi (including in the through-wafer via trench  110 ). 
         [0020]    FIG.  1 Cii shows the semiconductor structure  100  resulting from the formation of the through-wafer via layer  120  on top of the semiconductor structure  100  of FIG.  1 Bii (including in the through-wafer via trench  110 ). 
         [0021]    Next, with reference to FIG.  1 Ci, in one embodiment, a top portion  120   a  of the through-wafer via layer  120  outside the through-wafer via trench  110  is removed such that a top surface  115   a  of the dielectric layer  115  is exposed to the surrounding ambient as shown in FIG.  1 Di. What remains of the through-wafer via layer  120  after the removal can be referred to a through-wafer via  120 ′ (FIG.  1 Di). The top portion  120   a  of the through-wafer via layer  120  outside the through-wafer via trench  110  can be removed by chemical mechanical polishing (CMP). 
         [0022]    FIG.  1 Dii shows the semiconductor structure  100  resulting from the removal of the top portion  120   a  of the through-wafer via layer  120  of FIG.  1 Cii. 
         [0023]    Next, with reference to  FIG. 1E , in one embodiment, additional conventional steps are performed on the semiconductor structure  100  of FIG.  1 Di resulting in the semiconductor structure  100  of  FIG. 1E . 
         [0024]    In one embodiment, the semiconductor structure  100  in  FIG. 1E  comprises the silicon wafer  105 , the dielectric layer  115 , the through-wafer via  120 ′, an insulating layer  125 , atop pad structure  130 , and a glass handler  135 . The handler  135  can also be made of silicon. 
         [0025]    More specifically, the top pad structure  130  can comprise Cu, whereas the dielectric layer  115  can comprise silicon dioxide. The glass handler  135  is attached to the insulating layer  125  and the top pad structure  130  by an adhesive layer (not shown). 
         [0026]    Next, in one embodiment, a bottom surface  105 ″ of the silicon wafer  105  is mechanically ground until a bottom surface  120   b  of the through-wafer via  120 ′ is exposed to the surrounding ambient resulting in the semiconductor structure  100  of  FIG. 1F . 
         [0027]    Next, with reference to  FIG. 1G , a bottom pad structure  140  is formed on the bottom surface  120   b  of the through-wafer via  120 ′. More specifically, the bottom pad structure  140  can comprise Cu. The bottom pad structure  140  can be formed by using lithography and etching processes. As seen in  FIG. 1G , the through-wafer via  120 ′ provides an electrical path through a thickness  105   b  of the wafer  105 . 
         [0028]      FIG. 2A  shows a top down view of a through-wafer via structure  200  formed in a wafer (not shown) in accordance with embodiments of the present invention. More specifically, the through-wafer via structure  200  can comprise multiple through-wafer vias  220  (seven are shown for illustration) each of which is similar to the through-wafer via  120 ′ of  FIG. 1G , to form the composite through-wafer via structure  200 . 
         [0029]    Each of the multiple through-wafer vias  220  of the composite through-wafer via structure  200  can be formed in a manner similar to the manner in which the through-wafer via  120 ′ (of  FIG. 1G ) is formed. In one embodiment, the multiple through-wafer vias  220  are formed simultaneously. 
         [0030]    It should be noted that each of the multiple through-wafer vias  220  comprises other layers (not shown) similar to the silicon wafer  105 , the dielectric layer  115 , the insulating layer  125 , and the glass handler  135  of  FIG. 1G . However these layers are not shown in  FIG. 2A  for simplicity. In one embodiment, the multiple through-wafer vias  220  have a same length  221 . 
         [0031]    FIG.  2 A′ shows a perspective view of the composite through-wafer via structure  200  of  FIG. 2A , in accordance with embodiments of the present invention. It should be noted that a top pad structure  230  and a bottom pad structure  240  are respectively similar to the top pad structure  130  and the bottom pad structure  140  of  FIG. 1G . More specifically, all the multiple through-wafer vias  220  are electrically coupled to the top pad structure  230  and the bottom pad structure  240 . 
         [0032]      FIG. 2B  illustrates a top down view of a through-wafer via system  279 , in accordance with embodiments of the present invention. More specifically, the through-wafer via system  279  comprises four composite through-wafer via structures  270 . Each of the four composite through-wafer via structures  270  can comprise seven through-wafer vias  271 . 
         [0033]    In one embodiment, each of the four composite through-wafer via structures  270  is similar to the through-wafer via structure  200  of  FIG. 2A . It should be noted that, the top pad structure  230 , the bottom pad structure  240 , and other layers of the four composite through-wafer via structures  270  are not shown in  FIG. 2B  for simplicity. 
         [0034]    For each of the four composite through-wafer via structures  270 , the seven through-wafer vias  271  can be formed simultaneously. Each of the four composite through-wafer via structures  270  can be formed in a manner similar to the manner in which the through-wafer via structure  200  of  FIG. 2A  is formed. In one embodiment, all the 28 through-wafer vias  271  of the through-wafer via system  279  have the same length  272 . All the 28 through-wafer vias  271  of the through-wafer via system  279  can run in the same direction  273 . The four composite through-wafer via structures  270  can be arranged in an array of 2 rows and 2 columns as shown. 
         [0035]      FIG. 2C  shows a top down view of a through-wafer via system  289  in accordance with embodiments of the present invention. More specifically, the through-wafer via system  289  can comprise four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d . Each of the four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d  can comprise seven through-wafer vias  281 . 
         [0036]    In one embodiment, each of the four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d  is similar to the composite through-wafer via structure  200  of FIG.  2 A′. It should be noted that, the top pad structure  230 , the bottom pad structure  240 , and other layers of the four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d  are not shown in  FIG. 2C  for simplicity. 
         [0037]    For each of the four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d , the seven through-wafer vias  281  can be formed simultaneously in a wafer (not shown). Each of the four through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d  can be formed in a manner similar to the manner in which the composite through-wafer via structure  200  of  FIG. 2A  is formed except that for each of the four through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d , the lengths of the seven through-wafer vias  281  are not the same. 
         [0038]    More specifically, for each of the four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d , when going from the center to the outside of the structure, the lengths of the seven through-wafer vias  281  become shorter and shorter. 
         [0039]    For example, in the composite through-wafer via structure  280   a , the length of a first through-wafer via  281   a   1  is greater than the length of a second through-wafer via  281   a   2 , which is in turn greater than the length of a third through-wafer via  281   a   3 , which is in turn greater than the length of a fourth through-wafer via  281   a   4 . 
         [0040]    For another example, the length of a first through-wafer via  281   b   1  is greater than the length of a second through-wafer via  281   b   2 , which is in turn greater than the length of a third through-wafer via  281   b   3 , which is in turn greater than the length of a fourth through-wafer via  281   b   4 . 
         [0041]    With reference to  FIG. 2C , in one embodiment, the four composite through-wafer via structures  280   a ,  280   b ,  280   c , and  280   d  are arranged in a manner similar to the manner in which the four composite through-wafer via structures  270  of  FIG. 2B  are arranged (i.e., in an array of 2 rows and 2 columns) except that when going from one structure to the next structure in the same row or the same column, the orientation of the seven through-wafer vias  281  changes 90 degrees. 
         [0042]    For example, the seven through-wafer vias  281  of the composite through-wafer via structure  280   a  run in a direction  282   a , whereas the seven through-wafer vias  281  of the composite through-wafer via structure  280   b  run in a direction  282   b  which is perpendicular to the direction  282   a . In other words, when going from the composite through-wafer via structure  280   a  to composite through-wafer via structure  280   b  in a same row, the direction of the seven through-wafer vias  281  changes from the direction  282   a  to the direction  282   b  (i.e., changing 90 degrees). 
         [0043]    For another example, the seven through-wafer vias  281  of the composite through-wafer via structure  280   a  run in the direction  282   a , whereas the seven through-wafer vias  281  of the composite through-wafer via structure  280   d  run in the direction  282   b  which is perpendicular to the direction  282   a . In other words, when going from the composite through-wafer via structure  280   a  to the composite through-wafer via structure  280   d  in a same column, the direction of the seven through-wafer vias  281  changes from the direction  282   a  to the direction  282   b  (i.e., changing 90 degrees). 
         [0044]      FIG. 3A  shows a top down view of a through-wafer via  300  in accordance with embodiments of the present invention. More specifically, the through-wafer via  300  has a sinusoidal shape. In one embodiment, the through-wafer via structure  300  has a wave length  303  of about 12 μm, a width  301  of about 4 μm, and a thickness  302  of about 3 μm. In one embodiment, an angle  304  formed by a centerline  305  and a segment axis  306  is about 45°. In one embodiment, the ends  311  of the through-wafer via  300  are rounded. 
         [0045]    Assume that a trench is formed in place of the through-wafer via  300  (i.e., the trench has a same size, shape and location as the through-wafer via  300 ). Assume further that the trench is being filled with a filling material using CVD. As the result, the filling material grows from the side walls of the trench and converges to a convergence surface  307  in the trench. A plane parallel to a top surface of the semiconductor wafer would intersect the convergence surface  307  through a convergence curve  308 . A length of the convergence curve  308  can be considered the length of the through-wafer via  300 . A convergence distance  309  is the distance by which the filling material grows from a side wall  310  of the trench to the convergence surface  307 . In one embodiment, the length of the through-wafer via  300  is at least twenty times greater than the convergence distance  309 . 
         [0046]      FIG. 3B  illustrates a top down view of a composite through-wafer via structure  390 , in accordance with embodiments of the present invention. The composite through-wafer via structure  390  can be formed in a wafer (not shown). More specifically, the through-wafer via structure  390  can comprise multiple (seven shown here for illustration) through-wafer vias  391 . Each of the seven through-wafer vias  391  is similar to the through-wafer via  300  of  FIG. 3A . In one embodiment, the composite through-wafer via structure  390  has the shape of a rectangle. More specifically, four of the seven through-wafer vias  391  are at the four sides of the rectangle, the other three through-wafer vias  391  are arranged inside of the rectangle. 
         [0047]    In summary, with reference to  FIG. 1A , the length  110   b  of the through-wafer via trench  110  is much greater than the width  110   a  of the through-wafer via trench  110 . As a result, although the depth  110   c  (FIG.  1 Aii) of the through-wafer via trench  110  is much greater than the width  110   a  of the through-wafer via trench  110  (high-aspect ratio), the through-wafer via trench  110  can be filled with a metal (preferably tungsten) with high quality due to the length  110   b  being much greater than the width  110   a.    
         [0048]    In the embodiments above, with reference to  FIG. 2B , the number of through-wafer vias  271  in each composite through-wafer via structures  270  is seven. In general, the through-wafer via structures  270  can have different numbers of through-wafer vias  271 . For example, a first through-wafer via structure  270  can have 5 through-wafer vias  271 , a second through-wafer via structure  270  can have 6 through-wafer vias  271 , a third through-wafer via structure  270  can have 7 through-wafer vias  271 , and a fourth through-wafer via structure  270  can have 8 through-wafer vias  271 . 
         [0049]    It should be noted that the present invention may also be applied to thin wafers and to wafers of any material (such as glass, metal, and ceramic) for which a suitable etching process can be found. 
         [0050]      FIG. 4  shows a perspective view of a through-wafer via  410 , in accordance with embodiments of the present invention. The through-wafer via  410  is similar to the through-wafer via  120 ′ of  FIG. 1G  (i.e., having a shape of a rectangular plate) except that the vertical edges  417  of the through-wafer via  410  are rounded. Similar to the through-wafer via  120 ′ of  FIG. 1G , the through-wafer via  410  has its length  411  being much greater (e.g., at least 10 times greater) than its width  412 . 
         [0051]      FIG. 5  shows a top-down view of a through-wafer via  500 , in accordance with embodiments of the present invention. The through-wafer via  500  can have multiple branches  505  and multiple intersections  520 . Although the intersections  520  are all 4-way in  FIG. 5 , in general the intersections of the through-wafer via  500  can be N-way (N is an integer greater than 2). 
         [0052]    Assume that a trench is formed in place of the through-wafer via  500  (i.e., the trench has a same size, shape and location as the through-wafer via  500 ). Assume further that the trench is being filled with a filling material using CVD. As the result, the filling material grows from the side walls of the trench and converges to a convergence surface  510  in the trench. A plane parallel to a top surface of the semiconductor wafer would intersect the convergence surface  510  through a convergence curve (which coincides with the convergence surface  510  due to the top down view. Therefore, the same numeral  510  can be used for both). Because the through-wafer via  500  has multiple branches  505  and multiple intersections  520 , the convergence curve  510  also has multiple branches and multiple intersections. In one embodiment, the total length of the convergence curve  510  is at least twenty times a convergence distance  530 . 
         [0053]    It should be noted that there is no closed loop in the convergence curve  510 . Also, in one embodiment, the intersections  520  of the through-wafer via  500  are tailored such that the intersections  520  can be filled by a CVD process. 
         [0054]    While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.