Abstract:
A system and method for improving and optimizing current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The system and method enables rapid C4 bump current estimation and placement including generating a one-time computed sensitivity matrix that includes all of the contributions of macros (or groups of components) to C4 current. The system and method further enables the calculation of a C4 current changes using the one-time computed sensitivity matrix and redistributed currents due to deletion of one or more C4 connectors. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application is a continuation-in-part of U.S. patent application Ser. No. 13/526,194, filed Jun. 18, 2012, the entire content and disclosure of which is incorporated herein by reference. 
    
    
     BACKGROUND 
     The present disclosure relates to semiconductor device design, manufacture and packaging methods to improve electrical current delivery into a semiconductor chip. 
     Flip chip generally uses the Controlled Collapse Chip Connection or, C4, technology to interconnect semiconductor devices of IC chips or Microelectromechanical systems (MEMS), or alternatively, the chip die, to packages for connection to external circuitry with solder bumps that have been deposited onto the chip pads. Power (i.e., power and ground) and signals have to be delivered to die from package through these C4 connectors or “bumps”. 
     Like other interconnects, C4 bumps are susceptible to electromigration and the susceptibility is strongly affected by the amount of current carried by the bumps. According to the Black&#39;s equation, the mean-time-to-failure of the bumps is a power of their current density. This means that reducing the amount of current carried by the bumps significantly lowers their susceptibility to electromigration. Thus, there is a limit as to how much current each C4 bump can carry and this limit must be managed to meet target chip lifetime. 
     The current density of C4 bumps is determined by two factors: the amount of current carried by the bumps and the dimension of the bumps. The amount of current carried by the bumps has increased, as the current drawn per unit area has increased due to high transistor integration (by aggressive technology scaling) and high clock frequency. Recently, nominal clock frequency tends to saturate but most microprocessor chips enable a frequency boost mode in which most cores are turned off and the frequency of one or only a few cores is boosted for better single-thread performance. The boost mode prevents total chip power from increasing by turning off most cores, but it causes high power dissipated or high current drawn in the boosted region of the chip. As a result, the concern of excessive C4 current remains. The dimension of C4 bumps between package substrates and chips has been slightly shrunk, but emerging 3D integration technology has introduced much smaller C4 bumps to bond the chips stacked vertically. In addition to smaller dimensions, the so-called mini or micro bumps need to carry current drawn by one or multiple chips in the stack. As a result, the effective current density of these bumps increases significantly. 
     In addition to the current density concern, the susceptibility of the C4 bumps to electromigration increases if the bumps are lead-free due to “green” regulations. The lead-free bumps are reportedly more vulnerable to electromigration than the traditional ones by creating non-uniform current distribution in the bumps. As a result, the current limit of lead-free bumps is set significantly lower than that of the traditional bumps in order to achieve the same chip lifetime. The challenging limit makes it even more critical to consider C4 current awareness in designing microprocessor chips and packages. 
     C4 current limit may be set by the target electromigration lifetime governed by several key factors. As shown in  FIG. 1 , key factors  10  that effect C4 lifetime electromigration reliability  11  include: C4 technologies  12  (e.g., lead-free, design structure/mechanics, pad shape/structure); C4 operating currents  14 , and C4 operating temperatures  16 —all which effect electromigration reliability of the chip over time. Factors effecting C4 operating currents include the amount of current drawn by integrated circuit devices  14   a  on the chip or die, the density and location of the C4 bumps  14   c , and the power grid networks  14   b  that connect the devices and the C4 bumps. That is, the power dissipated or current drawn by the devices is delivered from the package pins through substrate wires therein through the C4 connections (bumps) to distribute current to the chip die through one or multiple chip wiring levels. Thus, current delivery design factors include the amount of current drawn by and the location of operating devices at the die, how they are wired (designed power grid between C4s and devices), and how many C4s are populated in a unit area and how they are placed, all effect C4 current draw and ultimately chip reliability susceptible to electromigration. 
     As described above, in semiconductor chip manufacturing, C4 current limits are becoming difficult to meet due to a variety of factors including: increasing use of Pb-free C4; higher target frequencies of IC chip operation; and frequency boosted modes of operation. As C4 current reduction is critical during chip planning, a system and method that expediently performs integrated circuit current and sensitivity estimation would be highly desirable. 
     It would also be highly desirable to provide an automated system and method that optimizes semiconductor chip floorplans and C4 bump footprints with respect to current draw through the bumps. However, there are currently no known automated mechanisms that place standard cells composed of devices or higher-level units composed of cells for the balanced current or reliability of C4 bumps. 
     There are dynamic management mechanisms used in other areas such as power or temperature, but none for current management. Such existing mechanisms may indirectly control the exposure to excessive current delivery, but they cannot directly keep C4 current to be met the limit. 
     In addition, dynamic current management mechanisms can be coupled with static design methodologies such as C4 current-aware floorplanning and C4 placement optimization in order to improve current delivery into a chip as well as performance. 
     SUMMARY 
     There is provided a system and design methodology for improving current delivery into a chip, which is limited by the physical properties of the physical connections such as C4 bumps between chips and the package, micro bumps or TSVs (through silicon vias) between two chips or any other electrical connections for power delivery. Further implemented is a dynamic mechanism for measuring or estimating power consumption at a certain granularity within a chip, converting the power information into the connections current, and triggering throttling mechanisms where applicable, to limit the current delivery per connection beyond pre-established limits or periods. 
     The design methodology also includes providing automated design aids to floorplan individual or a set of devices drawn current based on the current delivery requirements. 
     The design methodology further includes a methodology that allocates the connections even or unevenly over units or cores and exploits the distinct current delivery requirements to the units or cores by dynamic workload scheduling. 
     The design methodology also includes providing automated design aids for rapid C4 bump current estimation including sensitivity analysis to macro power dissipation, and C4 footprint evaluation and optimization. 
     Thus, according to one embodiment, there is provided a system, method and computer program product for integrated circuit (IC) chip and IC package design. The method comprises: generating, at a computer system, a data structure representing a current distribution relation between one or more current sources and one or more physical structures that deliver electrical current drawn by the current sources as connected via grid networks; and evaluating, using said data structure, a design plan and optimizing, using said data structure, said design plan with respect to electrical current drawn by said current sources, 
     In a further embodiment, the method includes: quantifying the amount of current flowing through physical structures under one or more operating conditions, the operating conditions represented by a set of vectors of current, I S , drawn by the current sources; and quantifying the amount of current flowing through physical structures as a product of the set of vectors of current drawn by the current sources and the current distribution relation data structure, wherein the evaluating the design plan comprises: determining a target reduction of the current drawn by blocks including one or more current sources by: identifying, using the current distribution relation data structure, the physical structures with current exceeding a specified amount; profiling the contribution of blocks to the excessive current amount by inversing the current distribution relation data structure; examining a cost of the current reduction of the blocks, the cost based on a time to change the IC design of the blocks; and determining, based on the cost, the amount of the target current reduction of the design blocks. 
     In a further embodiment, the design plan includes a placement of the physical structures in the integrated circuit chip, the method further comprises: automatically evaluating, using the data structure, physical structure placement alternatives, and optimizing, using the data structure, a placement of the physical structures in the integrated circuit chip, wherein a placement alternative of the physical structures includes an array of physical structures, the current distribution relation being further represented by a further data structure for determining an amount of additional current to distribute to remaining physical structures of the array based on removing a single physical structure from the array. 
     In a further embodiment, the determining an amount of the additional current comprises comparing a total computed current of the physical structures without the removed physical structure against a total computed current of the physical structures with the removed physical structure, storing a ratio of additional current distribution in the data structure, and multiplying the data structure by a vector having entries corresponding to deleted and undeleted physical structures, the entries corresponding to the deleted physical structures represented by virtual current amount and the entries corresponding to the undeleted physical structures represent a zero current, wherein the virtual current amount comprises: if a single physical structure is deleted, a same amount as the amount of current flowing through the deleted physical structure when no physical structure is deleted; and if two or more the physical structures are deleted, the method further comprising: generating a subset of the data structure consisting of the only entries associated with the deleted physical structures, multiplying the inversion of the subset by the amount of current flown through the deleted physical structures when none are deleted. 
     A computer program product is provided for performing operations. The computer program product includes a storage medium readable by a processing circuit and storing instructions run by the processing circuit for running a method. The method is the same as listed above. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be described with reference to  FIG. 1-21 . When referring to the figures, like elements shown throughout are indicated with like reference numerals. 
         FIG. 1  shows those factors  10  that effect C4 lifetime electromigration reliability in a semiconductor chip; 
         FIG. 2  illustrates an example method  100  performing calculations that obtain the C4 number and placement options given C4 current optimization and/or other constraints in one embodiment; 
         FIG. 3  depicts an equation for calculating the C4 currents vector I C4  associated with the bins given matrix A, and current sources vector I S , in accordance with one embodiment; 
         FIG. 4  shows, in one embodiment, the binning approach to generate the sensitivity matrix A of  FIG. 3 ; 
         FIG. 5  shows, in one embodiment, an algorithm  200  for generating matrix A of  FIG. 3 ; 
         FIG. 6  shows, in one embodiment, an example C4 Current-Aware Floorplanning Implementation example  300 ; 
         FIGS. 7A-7C  depict alternative hardware embodiments for dynamically measuring the C4 current drawn at various chip regions operating under various workload conditions, and for providing dynamic current delivery control at operating units in the regions; 
         FIGS. 8A-8D  depict various chip architectures for implementing the current delivery control solutions of  FIGS. 7A-7C  to regions of the chip in various embodiments; 
         FIG. 9  shows a further example of a further implementation of a chip control loop architecture in one embodiment; 
         FIG. 10  depicts an implementation of a token-based current delivery control solution in a further embodiment for a chip or chip portion; 
         FIG. 11  particularly shows a method  500  that, in a sliding window of time, a particular unit is issued tokens when a unit is to perform high activity for a unit of time; 
         FIG. 12A  shows one embodiment of a vertically stacked chip configuration  40  in which the methods and chip architectures of the present embodiments may be employed; 
         FIG. 12B  shows one embodiment of a horizontally extended “flip chip” package  30  in which the methods and chip architectures of the present embodiments may be employed; 
         FIG. 13  shows an embodiment of a chip architecture for implementing the current delivery control solutions as in  FIG. 8B , however, further interfaced with an operating system level scheduler to effect host O/S or hypervisor power throttling operations; 
         FIG. 14  shows an example multi-core processor chip  20  where the allocation of C4 connections to a given functional unit is varied across cores; and 
         FIG. 15  is a flow chart depicting a method to generate a reusable matrix (A) that represents the contribution of macros or bins to current in C4 physical structures, in a chip design; 
         FIG. 16  depicts a method to compute current (k) in C4 physical structures with one-time computed matrix (A) and source current (I S ); 
         FIG. 17A  conceptually depicts a single deleted C4 physical structure&#39;s current distribution; 
         FIG. 17B  conceptually depicts multiple deleted C4 physical structure&#39;s current distributions and  FIG. 17C  depicts a revised current re-distribution as a result of deleting; 
         FIG. 18  depicts a C4 current change (ΔI C ) calculation with one-time computed matrix (A) and redistributed currents (I D ); 
         FIG. 19  is a flow chart depicting a method of generating one-time computed matrix (A) that contains current distribution relation between C4 bumps; 
         FIG. 20  is a flow chart depicting a method of optimizing C4 placement; and 
         FIG. 21  illustrates an exemplary computing system  400  configured for designing a semiconductor chip floorplan and monitoring C4 current draw at various functional units and C4 connections of a semiconductor chip. 
     
    
    
     DETAILED DESCRIPTION 
     The present system and method addresses the criticality of C4 current reduction during “pre-Silicon” chip planning and design as well as during “post-Silicon” (after chip designs are fixed and applications are run) phases, e.g., through dynamic workload optimization techniques. 
     Further, the electrical current delivery aware chip design methodologies include “pre-Silicon” and “post-Silicon”, and hybrid (combination of pre- and post-Silicon) approaches to analysis, design, implementation and optimization of chip and package designs. 
     Current-Aware Floorplanning 
     For example, as shown in  FIG. 2 , the pre-Silicon approach includes the floorplanning, designing where the devices, or standard cells or blocks composed of multiple devices are placed, with respect to power dissipation and C4 placement. The “pre-Silicon” floorplanning approach is “current aware” because the location of the devices, cells or blocks is determined by current profiles across the chip and thus they are placed to minimize maximum C4 current or balance C4 currents. For example, certain blocks that draw high current may be placed apart or under higher dense C4 area. 
     Current-Aware Floorplanning 
     For example, as shown in  FIG. 2 , the pre-Silicon approach includes the floorplanning, designing where the devices, or standard cells or blocks composed of multiple devices are placed, with respect to power dissipation and C4 placement. The “pre-Silicon” floorplanning approach is “current aware” because the location of the devices, cells or blocks is determined by current profiles across the chip and thus they are placed to minimize maximum C4 current or balance C4 currents. For example, certain blocks that draw high current may be placed apart or under higher dense C4 area. 
     An exemplary implementation of the current-aware floorplanning methodology is shown in  FIGS. 2 and 6 . Instead of the iterative approach shown in  FIG. 6 , an analytical solver can be used to find the optimal location of blocks. In an embodiment of the method  100  of  FIG. 2 , there are two major steps: 1) creating a one-time computed matrix that captures current distribution relation between a set of current sources (represented as a plurality of “bins” covering the active IC semiconductor area), and a set of voltage sources (e.g., pin interconnect structures such as C4 bumps), and 2) formulating objective functions and constraints and solving them to find the optimal floorplan by minimizing the cost while satisfying the constraints. In one embodiment, in the automated current-aware floorplanning methodology, the current distribution relation remains the same while the location of the devices cells or blocks may change to find the optimal solution, and is captured in a one-time computed matrix. This is done by associating the current sources not with the moving blocks but with the stationary “bins” or regions which the floorplan region is divided into. As referred to herein, a “block” includes a current source including, but not limited to, one or more electrical or integrated circuit devices that draw current or dissipate power while operational or non-operational (via transistor current leakage, for example). More specifically, the moving or locatable “block” or “blocks” during floorplanning may include, but are not limited to: a transistor device(s), gates comprising a plurality of transistor devices, standard cells comprising a plurality of gates, macros comprising a plurality of standard cells, a unit comprising a plurality of macros, a processing “core” or cores comprising one or more units, and a Central Processing Unit (CPU) including one or more cores, accelerator units, on-chip bus/network units, controller units, I/O units. 
     The floorplan region is divided into a sufficiently large number k of “bins” at  105 . A data structure such as a matrix capturing the current distribution relation between the bins and the C4 bumps is generated at  110  by using, in one embodiment, a sensitivity analysis methodology such as described herein with respect to  FIG. 15 . 
       FIG. 4  shows the binning approach to generate the sensitivity matrix A. The example die floorplan or floorplan portion  50  shown in  FIG. 4  includes IC blocks  55   a ,  55   b ,  55   c , and  55   d , for example, overlayed with a uniform grid shown as a pattern or network of grid lines  60  that define and fix locations of the bins  75 . The grid (and consequently, the bins) can be irregular in size as well. The blocks  55   a ,  55   b ,  55   c , and  55   d  are movable during floorplanning, but the bins  75  are fixed. The current demand of the blocks is distributed per bin, such that as the two or more bins overlap a block the current demand of that block is divided proportionately among the overlapped bins. For examples, as shown in  FIG. 4 , the overlap of portions  55   d   1  and  55   d   2  of block  55   d  with the respective bins  75   a ,  75   b  drives the respective current of respective bins  75   a ,  75   b  according the ratio of the overlapped portion to the total area of the unit  55   d  and the current drawn in each bin. 
       FIG. 5  shows an exemplary implementation of the sensitivity matrix generation process. There is generated a sensitivity matrix A that represents the current distribution relation between bins and the C4 bumps. That is, the sensitivity matrix A, an n×m matrix, represents a resistive network between m bins and n C4 bumps, e.g., structures like pins of chip packages, pins between chips and packages, pins between chips, etc. 
     To compute the sensitivity of C4 currents with respect to each bin, the current of the selected bin is assumed a unit current (e.g., 1A) and that of the other bins no current, i.e., 0A. Then, the C4 currents obtained by power grid analysis and divided by 1 A (i.e., the applied current to the selected bin) indicate what portion of the bin current is distributed to each C4 bump. This sensitivity of C4 currents with respect to the selected bin is a weighted vector saved to the corresponding column of matrix A. Once this matrix A is created, the C4 currents vector I C4  associated with the bin currents vector I S  is calculated in accordance with the equation depicted in  FIG. 3 , as follows:
 
 I   C4   =A·I   S .
 
     Returning back to  FIGS. 2 and 6 , the current-aware floorplanning starts with the matrix, block information (such as current, dimension and initial location) and objectives (such as max C4 current) at  310 . In  FIG. 6 , as an example, a programmed computer running a set of stored processing instructions receives at  310  the following inputs: I M : block currents; D M : the block dimensions in width and height (w, h); L M : the initial block locations coordinates (x, y) in the floorplan; A: the one-time computed matrix (n×m); and I C4     —     max : the initial max C4 current. At  312  there is performed setting a new solution variable, L M     —     n32  indicating a new chip layout design (new macro location coordinates providing current sources). 
     The loop composed of  312  to  335  implements an iterative approach to find the optimal floorplan. At  315 , the mapping of the moving blocks to the stationary bins is performed in the form of a loop that iterates over all bins i such that, for all i, 0≦i≦m−1 the total current of bin i, I S (i), is the summation of a product of the I M : Macro j  current portion and the ratio of Macro j  overlapping with Bin i  (i.e., summed over all overlapping blocks at that bin i). Then, at  320 , each C4 current is computed by sum of currents contributed by each bin, based on the computed sensitivity matrix A. The cost (Cost C4 ) is additionally generated at  320  (with constraints) as a function of max i  I C4 (i), the maximum current among the n C4 bumps. Continuing at  325 ,  FIG. 6 , a determination is made as to whether the maximum current, i.e., Cost C4 , is smaller than the C4 current limit, I C4     —     max . If at  325  it is determined that the maximum current is larger than the C4 current limit, the process returns to step  312  and steps  315 ,  320  and  325  are repeated. As such, the new block locations are ignored. Otherwise, at  325  if it determined that the I C4     —     max  is larger than the cost, then the process continues at step  330  where an iteration is performed over all blocks i to set the current L M : macro locations to L M     —     new  and I C4     —     max  is set to the maximum current. The process proceeds to  335  where it is determined whether a maximum iteration count has been reached for obtaining for iterating among floorplan designs. If the maximum count has not been reached, then the process returns again to  312  to select a new solution L M     —     n32 . Otherwise, if the maximum iteration count has been reached, then the latest L M  floorplan locations are output and/or saved to memory at  340  indicating where to place the blocks for this design example. 
     If an analytical solver is used,  312  to  335  are replaced with the evaluation of the following cost functions with the solver:
 
Cost C4 =max k   i   c     4       k    
         subject to the C4 current limit constraint: where n is the number of C4 bumps.       

     
       
         
           
             
               
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     C4 Current Reduction Through Instruction/Workload Based Optimizations 
     A post silicon approach is “current aware,” i.e., given the fixed layout (floor plan of devices, macros, units, cores, CPUs, etc. and C4 layout), by proper dispatching of the instructions or scheduling workloads properly on the CPU to balance and lower C4 current draw. This guarantees that the C4 current limit is met at any time or never exceeds a determined value for a period of time of operation. 
     Hybrid: Chip Design and Workload Based Optimization 
     Thus, in one aspect, in the “pre-Silicon” approach of a multi-core processor chip, C4s are designed and allocated unevenly to cores or units, and in the “post-Silicon” approach, workload based optimization is performed to exploit the heterogeneity. 
     Adaptive C4 Current-Reduction Utilizing Workload Behavior 
     In pre-Silicon phase, currents and costs can be optimized, but there are cases in chip design in which current may not be optimized, e.g., one or more C4 connections can not meet the C4 current limitations if operated under some work load condition. 
     Thus, in a further embodiment, instead of designing a floorplan for worst-case corner or condition (e.g. a work load that stresses C4 connection the most), the floorplan could be designed for average case behavior (a relaxed C4 current limit condition) and the C4 connections are monitored dynamically. In such a design, the C4 current reduction is obtained through workload based optimizations. In one embodiment, the method will identify which C4 connections are non-optimized, i.e., currents may exceed the current limit condition in a particular location. 
     In one embodiment, as shown in  FIG. 7A , a chip, such as an electronic control device or as part of an on-chip micro-controller, is formed in the die to monitor the C4 usage at various locations and ensure that the C4 current limits are not exceeded at those locations. In other embodiments, this can be performed by an operating system or hypervisor scheduler or under software program control. In each embodiment, the controller will stop operations in the functional unit, for example, to prevent the amount of current flowing through the corresponding C4 connections from exceeding their designed C4 current limits. 
     In one embodiment, there is dynamically measured the C4 current as a workload runs. More particularly, in a hardware implementation as shown in  FIG. 7A , during run time, the on-chip controller (which may be firmware) or global Current Delivery Control Unit  80  (CDCU), is a processing loop, performs both current control and a current measurement technique that measures activity levels at various functional blocks and/or C4 connections of the die. In one embodiment, the CDCU control block  81  implements a current control delivery algorithm  83  that operates to control the built in actuators  85  that invoke measuring operations  90 . In the embodiment of  FIG. 7A , the operations include invoking power estimation sensors that directly sense and perform power sensor estimation of the power consumption based under workload conditions at  93 , and at  95 , corresponding estimated power levels are subject to power to current conversion operation to obtain the real-time C4 current measures at the die under the workload conditions. Systems and methods for estimating power in a chip is known in the art (power proxies). 
     In an alternative or additional embodiment as shown in  FIG. 7B , a global CDCU control block  80 ′, as in the CDCU  80  of  FIG. 7A , implements a current control delivery algorithm  83  that operates to control the built in actuators  85  for invoking the measuring operations  90  which include: at  94 , the measuring of activity levels at various functional blocks and/or C4 connections of the die. In one embodiment, the measuring of activity levels at various functional blocks and/or C4 connections of the die address the C4 connections that are shared across blocks or blocks with non uniform current demands. Further, at  96 , there are performed operations to convert the measured activity levels to a power level. Then, at  95 , the corresponding converted power levels are converted to current levels to obtain the real-time C4 current measures at the die under the workload conditions. More specifically, at the end of the conversion process, a matrix (not shown) is obtained that provides a current map depending on the dynamic activity when a workload is run. Such a dynamic current map can be used in leverage with certain actuators to solve current delivery problem. 
     In an alternative or additional embodiment as shown in  FIG. 7C , the CDCU control block  80 ′ itself is implemented as a Local Current Delivery Control Unit (L U1 ) configured to implement a local current delivery control part of the processing loop, and specifically the actuation of local current limiting mechanisms at functional blocks in pre-determined area or grid regions as will be described herein below. Thus, as shown in  FIG. 7C , plural Local Current Delivery Control Units L U1  to L UN  are configured to act in a respective local region of the chip for current delivery control. The power estimation/activity measurement part is performed in the local CDCU shown as  80 ′ such as described with respect to  FIGS. 7A ,  7 B wherein measuring operations  90  are performed that include: the measuring of activity levels at various functional blocks and/or C4 connections of the die, and the performing an operation to convert the activity levels to a power level which are then converted to current levels to obtain the real-time C4 current measures at the die under the workload conditions. The global current control algorithm  83  operating in a global CDCU  80 ″ processes activity measurement signals from each of the L U1  to L UN  to determine local current level controls. The global CDCU  80 ″ interfaces with a CDCU control block  81 ′ of each individual L U1  to L UN  to control, via respective control signals  89 , the built in actuators  85  therein for invoking the local current delivery controls in a respective functional block, e.g., macro, unit, core, or CPU in pre-determined area or grid regions. 
     It should be understood that various other implementations for global CDCU are possible. For example, the current control delivery mechanisms in  FIG. 7A-7C  may be implemented alone or in any combination. They may be located off-chip as well but preferably as part of the on-chip power controller. Moreover, the CDCU units may be implemented by software and monitored by host system. 
     In the embodiments described herein, the CDCU units guarantee that the current limit is met at any time or never exceeds for a longer period of time by dispatching/scheduling the instructions or scheduling workloads properly. Control/actuation can be performed locally/globally or a combination of both. 
     The architecture for implementing the current delivery control solutions of  FIGS. 7A-7C  is now described with respect to  FIGS. 8A-8C . In an embodiment of  FIG. 8A , a chip or chip portion  60  having C4 bumps  62  distributed on the chip is shown divided into non-uniform grid regions  61 , for example regions  61  labeled 1, . . . , 9. In the embodiment of  FIG. 8A , the CDCU  80  of  FIG. 7A  is situated and configured to send control/actuation signals to and receive sensor measurement data signals  69  from the distributed power estimation (e.g., activity) sensors  64  for estimating current drawn in the each region  61  of the grid to obtain a C4 current at each C4 bump  62 . 
     From the collected sensor measurement values, the control algorithm will initiate corrective action to prevent exceeding a maximum C4 current limit at any C4 connection (bump). For example, the algorithm processes the measured or sensed values and implements an actuator to generate a control signal  88  to effect a local actuation such as a preventive response. For example, if it is sensed, or if an activity counter&#39;s count values indicate that C4 current limit is being exceeded when performing an operation, e.g., multiplying, the control algorithm is invoked to address the situation. In one embodiment, the algorithm may responsively generate a control signal to throttle timing of execution of an operation, e.g., operate on every other clock cycle, or effectively reducing its frequency of operation. Other operations may be actuated including: providing instruction sequencing control which is part of the chip control loop architecture described in connection with an example instruction sequencing unit (ISU) described herein with respect to  FIG. 9 . 
     In an embodiment of  FIG. 8B , a chip or chip portion  60 ′ having C4 bumps  62  distributed on the chip is shown divided into non-uniform grid regions  61 , for example regions  61  labeled 1, . . . , 9. In the embodiment of  FIG. 8B , the CDCU  80 ′ of  FIG. 7B  is situated and configured to send and receive control and data signals  69  to the distributed activity counters  66  for controlling activity monitoring and generating count values used for estimating current drawn in the each region  61  of the grid. The types of activity that count values are generated by activity sensor or counter includes: the number of times or occurrences of certain chip activities, e.g., a memory access, a CPU issuing an instruction, an access to a cache, the performing a multiplication operation or arithmetic operation in a functional unit such as an arithmetic logic unit. It is from a set of specially architected activity counters that deduce C4 current measurement. In a non-limiting example, the power to C4 current conversion algorithm is the same as described herein with respect to  FIG. 3  showing how bin currents (current sources vector I S ) convert to C4 currents I C4 . However, in the power to C4 current conversion algorithm, I S  indicates a vector of currents of the estimated power in the divided regions. That is, the chip layout is first divided into regions of the chip having located one or more physical connectors that deliver electrical current drawn by the current sources in the regions as connected via the grid network(s). As for the floorplanning, the sensitivity matrix A may be pre-computed to capture current distribution relation between the current sources, e.g., macros/units and physical connectors, e.g., C4 bumps. Then the power estimation measurement is made, e.g., to obtain a power consumption vector, e.g., P S , in Watts or mW which is stored in vector I S  in Amperes or mA of the current drawn for the divided regions (i.e., I S =P S /Vdd) where Vdd is a power supply voltage value powering the chip blocks. Then matrix A is used to obtain the current flow through the physical connectors I C4  with respect to an amount of current drawn for divided regions I S  according to I C4 =A*I S . 
     Different correlation and power proxy functions converting power from activity levels can be found in references to M. Floyd, M. Ware, K. Rajamani, T. Gloekler, B. Brock, P. Bose, A. Buyuktosunoglu, J. Rubio, B. Schubert, B. Spruth, J. Tierno, L. Pesantez. Adaptive Energy Management Features of the IBM POWER7 Chip. IBM Journal of Research and Development, Vol. 55, May/June 2011; and, M. Floyd, M. Ware, K. Rajamani, B. Brock, C. Lefurgy, A. Drake, L. Pesantez, T. Gloekler, J. Tierno, P. Bose, A. Buyuktosunoglu. Introducing the Adaptive Energy Management Features of the POWER7 chip. IEEE Micro, March/April 2011. In one embodiment, in the uniform or non-uniform grid regions, the activity is measured in those grid regions  61  and the conversion computations/actuations may be performed at a global central current manager through the current delivery control unit  80  or  80 ′. 
     In another form, the chip can be divided into uniform grids where the activity is measured in those grids and conversion computations are performed globally. Thus, in an embodiment of  FIG. 8C , a chip or chip portion  60 ″ having C4 bumps  62  distributed on the chip is shown divided into uniform grid regions  63 , for example regions  63  labeled 1, . . . , 9. In the embodiment of  FIG. 8C , the CDCU  80  of  FIG. 7A  or CDCU  80 ′ of  FIG. 7B  is situated and configured to send and receive control and data signals  69  to the distributed activity counters or like power estimation devices  88  for controlling current activity monitoring and estimating current drawn in the each uniform grid region  63 . 
     In either uniform or non-uniform grid regions, the regions  61 ,  63  in  FIGS. 8A-8C  may be of a size according to granularity of a macro, a functional unit, or a core. In a further embodiment, the activity that is measured in those grids  61 ,  63  and the conversion computations/actuations may be performed at a global central current manager through the current delivery control unit  80  or  80 ′. 
     In an embodiment of  FIG. 8D , a chip or chip portion  60 ′″ having C4 bumps  62  distributed on the chip is shown divided into uniform grid regions  63 , for example regions  63  labeled 1, . . . , 9 (e.g. at macro level or functional unit level). There is a global CDCU  80 ′ of  FIG. 7C  that may be part of an on-chip microcontroller to perform the measurement part of the loop that is situated and configured to receive power measurement signals obtained by activity counting mechanisms from the distributed power estimation (e.g., activity) sensors for estimating current drawn in the each respective region  63  of the grid to obtain an estimated C4 current level value in one embodiment. However, further included at each region  63  labeled 1, . . . , 9, for example, is a Local Current Delivery Control Unit LU 1 , . . . LU 9 , such as shown in  FIG. 7C , that is configured to locally implement the control part of the processing loop at each grid region  63 , and specifically the actuation of current limiting features at each local grid region  63 . 
       FIG. 9  depicts a further implementation of a chip control loop architecture in one embodiment for a chip or chip portion  60 ″″ having C4 bumps  62  distributed on the chip and shown divided into non-uniform grid regions  61 , for example regions  61  labeled 1, . . . , 9. In each region is an activity counter that monitors activity of various functional units including, but not limited to: an ISU: Instruction Sequencing Unit; an LSU: Load/Store Unit; an FXU: Fixed Point Unit; and a FPU: Floating Point Unit, located in a respective region  61  of the grid. In an example implementation, a C4 current measurement is autonomously obtained from the activity counters and power conversion algorithms in the CDCU  80 ′. If a C4 current measurement in a region is less than a programmed threshold, then in one embodiment, the actuation of a current limiting mechanism is not invoked. For example, in one embodiment, for a region  61  having the LSU, if it is determined that a C4_current_region_LSU&gt;threshold_i, then the LSU instruction issue rate may be throttled, i.e., reduced, otherwise, the normal LSU instruction issue rate is maintained at that region having the LSU. In one embodiment, to reduce issue rate: the actuators  85  in  FIG. 7A-7C  are programmed to throttle, i.e., reduce, a number of LSU instructions issued at a time, e.g., LSU instructions are issued every other cycle, or every other X cycles (X: can be any number). In one embodiment, the C4_current_region_LSU current may be computed as a sum of C4 current across all the macros of LSU or sum of C4 currents across a specified set of macros in LSU. That is, the granularity of the activity monitoring is at the unit level, or macro within the LSU unit. 
     It is understood that, without loss of generality, the throttling mechanism described with respect to  FIG. 9  additionally applies to other units ISU, FPU, FXU, etc., in a grid region, and any sub-block within the macro or unit. 
     It is understood that several of the architecture forms shown herein with respect to  FIGS. 8A-8D  can be deployed in an architecture, alone or in combination. 
     In a further embodiment, there is obviated the need to use CDCU and activity monitoring system as shown in  FIGS. 7A-7C  by implementing a token-based monitoring approach. This approach is based on the insight that is may be acceptable to exceed the C4 current limit for a very short period of time, but not for a long duration. Therefore, there is performed controlling the activity in a sliding window of time which permits use of a given unit for short periods with high activity, as long as the average in the time window is below a given threshold. 
     In one embodiment, in the C4-Aware Token-Based operation, each block e.g., macro, unit, core, CPU etc., gets or receives Tokens. Tokens may be issued and received at the blocks periodically. For example, one block may issue tokens to another block, or an Operating System of hypervisor unit may issue tokens to blocks. A block may additionally be programmed to allocate tokens to itself, e.g., periodically. When the block is used to perform an operation, one of the Tokens gets exhausted (i.e., a token count associated with that unit gets decremented). This allows the unit to be operated at high utilization for a short time (as long as there are enough tokens). The tokens are allocated to functional units, macros, cores, at a constant token generation rate. Given that tokens are allocated to a unit at a constant rate, this ensures that the overall activity does not exceed that of the rate at which tokens are generated. The time window determines how many unused Tokens can be kept at a given unit. 
       FIG. 10  depicts a token-based control loop implementation in one embodiment for a chip or chip portion  70  having C4 bumps  62  is distributed on the chip is shown divided into non-uniform grid regions  61 , for example regions  61  labeled 1, . . . , 9. In each region  61 , there is located various functional units including, but not limited to: an ISU: Instruction Sequencing Unit; an LSU: Load/Store Unit; an FXU: Fixed Point Unit; and a FPU: Floating Point Unit, located in a respective region  61 . Further associated with a respective region  61  are the issued reserve tokens  71  associated with the particular unit, e.g., ISU. In an example implementation, instruction throttling of the various functional units show in the architecture of  FIG. 10 , is performed according to a method  500  shown in  FIG. 11 . 
       FIG. 11  particularly shows a method that, in a sliding window of time, a particular unit is issued given tokens when a unit is to perform high activity for a unit of time. With a token, the unit can perform activity. The tokens ensure that the C4 current limits are not exceeded. 
     For example, as shown in  FIG. 11 , based on either the presilicon/postsilicon modeling results, which provide knowledge of high activity areas, for example, the token currency is issued to a unit in a grid that is representative of C4 current. In a first initialization  510 , there is performed initializing a token_generation/cycle variable to a value “X”; initializing a token_generation_amount variable to a value “T”; initializing a token_expiry_period variable to a value T_exp; and, for an example LSU functional block in a grid  61 , initializing the LSU reserve token LSU_tresv variable to a value of 0, for that functional unit. It is understood that X, T and T_exp variable values may be varied when run-time measurement is available. Then, at  515 , during real-time workload operations, at each X cycle, there is generated for issuance to the functional unit, e.g., LSU unit, the LSU_tresv amount of tokens  71  to the reserve. Then, at  520 , it is autonomously determined for each issuance by an ISU an LSU instruction and the LSU_tresv is greater than 0, then it is permitted for the ISU to issue an LSU instruction as the token reserve  71  for the LSU is greater than 1. After issuance of the LSU instruction the LSU_tresv variable is decremented by 1 token (e.g., LSU_tresv-1). Otherwise, if it is determined at  520  that upon issuance by an ISU of an LSU instruction, the corresponding LSU_tresv is not greater than 0, then the ISU is prevented from issuing the LSU instruction as exceeding the current limit. Finally, as indicated at  530 ,  FIG. 11 , for each token issued to a LSU, a determination is made as to whether the token_lifetime value is greater than the T_exp value. Each instance a token_lifetime value has exceeded the T_exp value then the LSU_tresv variable is decremented by 1 token (e.g., LSU_tresv-1). 
     It is understood that there may be an amount of tokens initialized that is commensurate with expected activity levels. For example, based on pre-Silicon modeling, or other knowledge, it may be deduced that LSU may be initially assigned a greater amount of tokens than another unit for example that is not as active. For example, the LSU may issue four (4) load instructions at one time (accessing logic or memory), which is converted to a C4 current estimation, and giving this knowledge, the number of tokens issued to the LSU every X cycles will be sufficient to accommodate the expected behavior of the functional unit during workload conditions. 
     It is further understood that, without loss of generality, the token-based throttling mechanism  500  described with respect to  FIG. 11  additionally applies to other units ISU, FPU, FXU, etc., in a grid region, and any sub-block within the macro or unit. 
     In a further embodiment, both the CDCU and token-based current monitoring and current delivery throttling methods and chip architectures described herein, can be extended to a 3D/Silicon carrier micro-architectures (e.g., “stacked” chip or 3-D memory implementations) including settings where different C4 pitch and dimension exist. For example, in a 3D package CDCU can operate both on lower C4s as well as upper layer C4s, or micro C4s. 
       FIG. 12A  shows one embodiment of a vertically stacked chip configuration  40  having first chip  41  of functional units in silicon or semiconductor material including a first lower C4 connection layer of C4 bumps  42  over a semiconductor substrate  45 , and a second chip  43  of functional units in Silicon or semiconductor material including a second upper C4 connection bump layer of C4 bumps  44  over the first chip  41 . In either embodiment, the CDCU units  80  and  80 ′ or LU of  FIGS. 7A-7C  may be implemented in each chip at each level. 
       FIG. 12B  shows one embodiment of a horizontally extended “flip chip” package  30  having multiple dies that communicate, e.g., chips  31  and  33  mounted on a Silicon substrate or carrier  35  via respective first C4 connection layer of C4 bumps  32  and second C4 connection layer of C4 bumps  34 . In this configuration, the chips  31  and  33  communicate to each other over carrier  35 . Via the embodiment  30  of  FIG. 12 , the CDCU units  80  and  80 ′ or LU of  FIGS. 7A-7C  may be implemented in each chip. 
     Current Delivery Aware Scheduling 
     In this approach to C4 current limiting, there is leveraged the fact that in the case of large time periods where C4 current can be exceeded, the previous “measurement” apparatus is used with a scheduler device (not shown) to optimize C4 current problem. That is, given a large number of cores, and even large number of applications to run on it, the scheduler can choose to co-schedule applications such that the likelihood of exceeding current delivery limit is minimized.  FIG. 13  shows an embodiment as in  FIG. 8B , however, the CDCU  80 ′ is interfaced with an operating system level scheduler device  98  via signaling  97  between the CDCU provided in the chip and a host operating system of a computing system or computing device  99 . Thus, in the embodiment shown in  FIG. 13 , the control delivery algorithm is implemented in the OS with scheduling decisions as the actuators. In a further embodiment, the “Activity Counting” as proxy for C4 current “measurement” maybe used. 
     Further to this embodiment, depicted in  FIG. 13 , there may be first performed a profile analysis of the application, running standalone, by measuring activity (without converting it into actual C4 current) in each C4 domain and store activity profile information in a table. Otherwise, a profile analysis of the application, running standalone, may include measuring C4 current in each C4 domain and storing profile activity of the region in a table. In accordance with a first embodiment of a scheduling policy: for every scheduling quantum: a determination is made as to whether the C4_current draw corresponding to operations at a region is greater than a threshold_C4 current draw for that region. A C4_current_region may be of a size according to granularity of a macro, a unit comprising one or more macros, a core comprising one or more units, or a central processing unit (CPU) having one or more cores and accelerator units, on-chip bus/network units, controller units, I/O units. A threshold_C4 current draw represents a maximum C4 current one can operate within. If it is determined that the C4_current draw corresponding to operations at a region is greater than a threshold_C4 current draw for that region then the scheduler device  98  will schedule the application operations at the O/S level or hypervisor level according to a min_C4_current profile. Otherwise, if it is determined that the C4_current draw corresponding to operations at a region is not greater than a threshold_C4 for that region then the scheduler device  98  will schedule the application operations at the O/S or hypervisor level according to its default policy. It is understood that the scheduling of operations in this embodiment, is according to a workload granularity level, as opposed to an instruction granularity level as in the hardware embodiments. 
     In accordance with a further embodiment of a scheduling policy: for every scheduling quantum: a determination is made as to whether the previous scheduling quantum activity in a C4 region is greater than a threshold activity level (threshold act), then application operations are scheduled by scheduler device  98  at the O/S or hypervisor level according to a min activity profile for that C4 region. Otherwise, if it is determined that the previous scheduling quantum of activity in a C4 region is not greater than a threshold activity level, then for that region then the scheduler device  98  will schedule the application operations according to its default policy. It is understood that the scheduling of operations in this embodiment, is according to a workload granularity level, as opposed to an instruction granularity level as in the hardware embodiments. 
     Hybrid: Chip Design+Workload Based Optimization 
     As mentioned above, in one aspect, in the “pre-Silicon” approach of a multi-core processor chip, C4s are designed and allocated unevenly to blocks, e.g., cores or units, and in the “post-Silicon” approach, workload based optimization is performed to exploit the heterogeneity. 
     In a current aware chip design and workload based optimization technique, during pre-silicon design, there is heterogeneous allocation of C4s (unevenly or non-uniformly) corresponding to respective cores or blocks that works harder, so the more C4s can handle the increased current draws. Thus, there is stressed workload or workload operations scheduled according to the allocated C4s. For example, at O/S, hypervisor or scheduler level, there is viewed the applications and types of instructions at workload, and the scheduler may schedule more work intensive instructions at the regions having more C4s allocated, e.g., load and multiply operations, and schedule less work intensive instructions at the regions having as less C4s allocated. 
     Considering now  FIG. 14 , there is depicted an example processor chip  20  where the allocation of C4 structures to a given functional unit is varied across cores. For example, some cores have more C4 structures for FPU, e.g., Core A  22 , and some cores have more C4 for load/store instructions, e.g., Core B  24 ; another core has more C4 for Integer Unit, e.g., Core C 26; and, another core, Core D  28 , has C4 allocation based in proportion to the average activity across FUBs. In one embodiment, all the cores  22 ,  24 ,  26 ,  28  are functionally identical. However, power delivery design for each core may be run at a different power corner application. The C4 structure footprint and power grid is optimized with respect to different power corners. Power and performance is improved by allocating the applications to cores based on the type of instructions in the workload. For example, instructions for FPU-heavy applications can be issued to run on core B. 
     For example, if C4s can be placed in a particular area of the chip, and all populated, then during a post-silicon phase, the method can be optimized. For example, given an IC die of 4 microprocessor cores (each core, having multiple functional units therein, e.g., bus, cache memory, fetch unit, decode unit, instruction sequencing unit, execution units such as fixed point unit, floating point unit, load/store unit) and amount, e.g., 100, of C4s can be implemented, e.g., to typically provide an equal distribution, e.g., 25, of C4 connections allocated to a core—this is a homogeneous arrangement. In one embodiment, this can be modified to heterogeneous C4 populated cores, i.e., an unequal distribution of C4 connections, where a single core may have, e.g., 50 of C4 connections associated, and another core may have 25 C4s associated, etc. Thus, during a “post-Silicon” approach, a program running on the chip may be designed and scheduled to operate higher power operations on the processor core having the more C4 allocated. That is, in this embodiment, there is an intentional distribution of cores non-uniformly and operations on the chip are designed/programmed accordingly to exploit the heterogeneity. 
     In a further embodiment, in an Extended Cache Option (ECO) mode of operation, only a few cores are turned on and the caches of the other cores is used to provide an effective cache capacity. The C4 current-aware design can provide a higher performance for such ECO mode rather than a C4-oblivious or homogenous or uniform architectures. For example, Core A  22  and Core C 26 are located in a region that can be allocated more C4, whereas Core B  24  and Core D  28  may be in a region that allocates fewer C4s. In the ECO mode Cores A and C are kept on, and B and D are turned off. This way the overall throughput is determined by cores that have received a larger number of C4s, resulting in higher overall performance (as those cores leverage more activity). 
     In one embodiment, referred to as an overclocking mode of operation, only a few (blocks, e.g., cores) are turned on and these cores are run at a higher clock frequency compared to nominal clock frequency. The C4-aware design can provide a higher performance for such a mode rather than a C4-oblivious arch. For example, Core A and Core C can get more C4 whereas Core B, Core D get fewer C4s. Thus, in the overclock mode, cores A and C may be kept on, and B and D are turned off. This way the overall throughput is determined by cores that have received a larger number of C4s, resulting in higher overall performance. 
     In a further mode of operation, both overclocking and ECO modes of operation are combined, e.g., Core A and Core C can be overclocked as well as use the caches of other (turned off) cores. 
     In a further embodiment, the methods described herein includes generating a matrix that represents power distribution networks and that can be repeatedly used for C4 current and sensitivity analysis. The methods and matrix implementation are easily integrated with any Power estimation tools and can be used with any analytical solver. In addition, the generated matrix is “sparse,” i.e., many entries with zero value because current distributes only to limited distance due to resistance. Thus, in one embodiment, only non-zero entries can be generated and stored for faster matrix generation. 
     Current-Aware Integrated Circuit Design Automation 
     The high power density of microprocessor chips has been a great challenge in power delivery as well as cooling. In particular, the macros dissipating several watts due to frequent activities create localized hot spots. Not only are they blamed for high temperature, but they also create high current flow around the area, resulting in high voltage drop and increased vulnerability to electromigration. To prevent excessive current flow, these macros may be designed in such a way so as to dissipate less power or draw less current. 
     However, such low power design often causes performance loss and high design cost. Therefore, it is important to plan carefully what macros to tune for power reduction and how much power to reduce. For efficient and effective planning, there is provided automated method to estimate the contribution of each macro to the amount of current flowing through individual C4 bumps. 
       FIG. 15  is a flow chart depicting a one-time computation method  600  to generate the sensitivity matrix (A) that represents the contribution of macros (current sources) to C4 current. Suppose that there are m macros drawing the current of I S (i) (0≦i≦m−1) and n C4 bumps which the current of I C (i) (0≦i≦n−1) flows through. At the end of the programmed implementation of the method, the current contribution of macro j will be stored in the jth column of n×m matrix A, where A(i, j) will indicate the ratio of the current drawn by macro j and contributed to the current of C4 i. 
     As shown in  FIG. 15 , first, at  605 , after initializing the I S  (i) current source (macro) and I C (i) current arrays, and matrix A (m×n), the macro iteration index j is reset at  610  before entering the loop in which one iteration quantifies each macro&#39;s contribution. This includes, at  615 , solving C4 current with a single macro S j . For each iteration, the current of the selected macro S j  is set to a unit value, e.g., 1 Ampere (A), and that of all the other macros 0 A (i.e., no current drawn by them). The power grid analysis is conducted by using any available tool to obtain the current of C4 bumps. Then, at  620 , the C4 bump currents as a result of the power grid analysis are stored in I C (i). Next, at  625 , I C (i) is divided by 1 A, the total current applied to the power grid analysis, and stored in A(i, j). As a result, A&#39;s jth column stores the ratio of the current contributed to individual C4 bumps to the total current drawn by macro S j . That is, A(i, j)* I S (j) indicates the amount of the current of C4 i contributed by macro S j . At  630 , the index j is incremented, and a determination made at  635  as to whether all columns for matrix A have been computed all macros, i.e., whether j&lt;m. If not all macros have been evaluated to compute matrix A, the process returns to step  615  and the process repeats for the next macro. When the contribution of every macro is quantified, as determined at step  635 , the program ends by saving matrix A at  640 . 
     Alternatively, the same matrix A can also be created by setting the selective macro&#39;s current 0 A and the other macro&#39;s current any value (e.g., 1A), and comparing with the case in which the selective macro draws current. In addition, the matrix generation can be more efficient in terms of generation time and matrix size by exploiting the attributes of power grid: e.g., limited current propagation due to resistance (sparse matrix), similarity in power grid among the iterations (speed up). 
       FIG. 16  illustrates the formulation of computing C4 current (k) with the generated matrix A and the current of macros (I S ): 
     
       
         
           
             
               
                 
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     Since matrix A includes the ratio of the contribution of macros, the sum of each column must be 1. 
     The method enables efficient low power design planning based on the above equation: 
     
       
         
           
             
               
                 
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             where A(i, j) −1 *I C (i) indicate the amount of C4 i&#39;s current contributed by macro j. Based on this information, it may be decided what macros to target for low power design and how much current reduction to achieve, in order to minimize design cost. 
           
         
       
    
     In addition to the low power design planning, the method allows to speed up C4 current analysis under many operating conditions. The power grid analysis generally takes long simulation time (hours to days). The long simulation time often delays design time and limits the number of operating conditions for evaluation. Rather, the method allows C4 current analysis to be performed by a mere matrix multiplication for each condition, since matrix A needs to be computed only one time and I S  under each condition is represented in the equation depicted in  FIG. 16  to obtain C4 current under the condition. 
     C4 Placement Automation 
     In addition to integrated circuit design, the location of C4 bumps strongly affects current distribution between macros and the bumps, and thus the amount of current flowing through each bump. For instance, if a single C4 bump is placed right beneath a hot macro, a significant portion of the current drawn by the hot macro goes to the C4 bump, resulting in excessive C4 current. If more than one bump is placed around the hot macro, the macro&#39;s current is likely to be shared by the bumps. 
     In general, manufacturing technology restricts the total number of C4 bumps to be populated per chip and the upper bound of their current in order to meet target lifetime. Such constraints often evolve over design time, affecting chip and package design. As a result, C4 footprint needs to be repeatedly adjusted with respect to design changes and technological constraintchange. 
     The C4 placement has been traditionally conducted in a manual manner, relying on an expert&#39;s experience. However, the manual method takes long turn-around time that limits the number of alternatives to be evaluated. There is now described the method essential to automate C4 placement as the method enables rapid evaluation of C4 footprint alternatives, thus finding the optimal placement solution. The automation of C4 placement enables to efficiently explore many C4 footprint alternatives under constraints such as current limit and C4 count limit, and to do trade-off analysis for C4 reliability such as peak current vs. C4 count. 
       FIGS. 17A-17C  illustrate the underlying idea of the method: current distribution between an array of C4 bumps  175  if one or multiple bumps  176 ,  178 , for example, are deleted. 
     When one bump, e.g., C4 bump  176  is deleted or depopulated from the fully populated footprint, the current flown through the deleted bump  176 ′ would be delivered by the other bumps ( FIG. 17A ), e.g., bump  177 . The amount of the additional current due to the C4 deletion can be quantified by comparing C4 current of the full population case with that of the deleted case. In one embodiment, the ratio of additional current distribution is stored in matrix A, and A ij  indicates the ratio of the additional current distributed to C4 i to the total current originally delivered by C4 j: 
     
       
         
           
             
               
                 
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                 1. 
               
             
           
         
       
     
     When more than one bump is deleted, using matrix A results in under-estimation of the current of the remaining bumps because the current re-distribution relation captured in A assumes only one bump deleted and thus the other deleted bump(s) sharing the re-distributed current. As such, the current re-distribution needs to be revised so that the current re-distributed falsely to the deleted bumps is carried by the undeleted bumps.  FIGS. 17B and 17C  depict the case of two C4 bumps,  176 ′ and  178 ′, being deleted.  FIG. 17B  illustrates revised current re-distribution to  178 ′ as a result of deleting  176 ′. The current  171  falsely re-distributed to the deleted bump  178 ′ by the deletion of bump  176 ′ is distributed to the other bumps  177  and  176 ′, denoted by currents  173  in  FIG. 17B .  FIG. 17C  illustrates revised current re-distribution to  176 ′ as a result of deleting  178 ′. The current  174  assumed for the deleted bump  176 ′ by the deletion of bump  178 ′ is distributed to the other bumps  177  and  178 ′, denoted by  179  in  FIG. 17C . 
     For example, in  FIG. 17B , the darker lines  172  indicate current distribution from the deleted C4 bump  176 ′ to placed C4 bumps  177 , and the lighter line  171  indicates an attempted current distribution from the deleted C4 bump  176 ′ to another deleted C4  178 ′. Since, at C4 bump structure  178 ′ there is no C4 to absorb the distributed current as it had already been deleted, that current has to be distributed to the other C4s as indicated by lighter lines  173  in  FIG. 17B . 
     Now with respect to the attempted current redistribution of  FIG. 17B , the same issue occurs from the deleted C4 bump&#39;s  178 ′ point of view as indicated in  FIG. 17C , where the current from deleted C4 bump  178 ′ is attempted to be redistributed to (added to) deleted C4 bump  176 ′. In this case, as shown in  FIG. 17C , as there is no C4 at  176 ′ to absorb the distributed current as it had already been deleted, that current has to be distributed to all the other undeleted C4s as indicated by lighter lines  179  in  FIG. 17C . 
     This phenomenon can be expressed by the inversion of a subset of matrix A: 
     
       
         
           
             
               
                 Δ 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   I 
                   
                     D 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     _ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     subset 
                   
                 
               
               = 
               
                 
                   A 
                   subset 
                   
                     - 
                     1 
                   
                 
                 · 
                 
                   [ 
                   
                     
                       
                         
                           - 
                           
                             i 
                             
                               full 
                               i 
                             
                           
                         
                       
                     
                     
                       
                         ⋮ 
                       
                     
                     
                       
                         
                           - 
                           
                             i 
                             
                               full 
                               j 
                             
                           
                         
                       
                     
                   
                   ] 
                 
               
             
             , 
           
         
       
         
         
           
             where A subset   −1  indicates inversed matrix of a subset of A with the elements corresponding to deleted bumps, and i full  (I f ) the original amount of current flown through the deleted bumps (in full population). 
           
         
       
    
     Then, as shown in  FIG. 18 , the additional current of C4 i due to a C4 bump deletion becomes: 
     
       
         
           
             
               
                 Δ 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   I 
                   
                     C 
                     i 
                   
                 
               
               = 
               
                 
                   ∑ 
                   
                     j 
                     = 
                     0 
                   
                   
                     n 
                     - 
                     1 
                   
                 
                 ⁢ 
                 
                   
                     
                       A 
                       ij 
                     
                     · 
                     Δ 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     I 
                     
                       D 
                       j 
                     
                   
                 
               
             
             , 
           
         
       
         
         
           
             where ΔI D  is expanded from ΔI D     —     subset  by setting the element corresponding to undeleted bumps 0. As shown in  FIG. 18 , the total current of C4 bumps becomes the sum of the original current in full population, I F , and the additional current due to the C4 bump deletion, ΔI C  where:
 
 I   C   =ΔI   C   +I   F .
 
           
         
       
    
       FIG. 19  is a flow chart of generating one-time computed matrix (A) that contains current distribution relation between C4 bumps according to one embodiment. In this embodiment, there are assumed n C4 bumps which the current of I 11 (i) (0≦i≦n−1) flows through in full population. At the end of the programmed implementation of the method, the current redistribution relation between C4 j and the other C4 bumps will be stored in the jth column of n×n matrix A, where A(i, j) indicates the ratio of the current distributed to C4 i to the original current of C4 j. The matrix A is initialized and I full (i) values (i.e., the C4 j current in full population) are accessed and/or received as input into a computer system at  705 . 
     Then, at  710 , index j is reset before entering the loop in which one iteration quantifies each C4 bump&#39;s current redistribution. For each iteration, the selected bump C4 j is deleted from the fully populated footprint at  715 . Then, the power grid analysis is conducted by using any available tool to obtain the current of C4 bumps. That is, a solver is run in the loop at  715 , and then at  720  for each i (0≦i≦n−1), there is calculated I C4 (i) as equal to C4 i current if i does not equal j; and there is calculated I C4 (i) as equal to 0 current if i equals j. The C4 bump currents as a result of the power grid analysis are stored in I C4 (i) as indicated at  720 . Next, at  725 , there is calculated matrix A(i, j) value as equal to the value of I full (i) subtracted from I C4 (i) with the result divided by I full (j), and stored as matrix A(i, j). As a result, A&#39;s jth column stores the ratio of current redistribution of C4 j to the other bumps. Then, at  730 , index j is incremented, and at  735 , a determination made as to whether index j is less than n. If it is determined that j is less than n, the process returns back to  715  to delete the next C4 bump. Otherwise, once j is equal to or exceeds n, i.e., when the current redistribution of every bump is quantified, the program ends by saving matrix A at  740 . 
     Alternatively, the matrix A generation can be more efficient in terms of generation time and matrix size by exploiting the attributes of power grid: e.g., limited current propagation due to resistance (sparse matrix), similarity in power grid among the iterations (which speeds up execution time). 
     Once the matrix A is generated, any C4 footprint under evaluation can be represented with the set of deleted bumps as well as the fully populated footprint, the current re-distribution due to C4 deletion can be quantified with A subset   −1 , and finally the C4 current of the evaluated C4 footprint can be computed as describe above. That is, the evaluation no longer requires long-time power grid analysis. 
     C4 Placement Optimization 
     While the above method to automate C4 placement is useful for optimization, as well as rapid C4 current analysis, any other methods to rapidly and accurately evaluate C4 footprint alternatives can be used in combination of the optimization methodology described here. 
     C4 bumps footprint can be optimized in terms of various aspects while satisfying constraints: maximum current, electromigration reliability, the total number of bumps, or the number of bumps per unit area. If the number of footprint alternatives is limited and evaluation time is fast, the best one can be chosen by considering all alternatives, e.g., conducting an exhaustive search. 
     If the number of footprint alternatives is large and/or evaluation time is slow, considering all possible alternatives is infeasible. Thus, it is necessary to choose and evaluate an effective subset of the alternatives. In one embodiment, there are provided several algorithms that effectively choose and evaluate footprint alternatives and find the optimal footprint or a one very close to optimal within feasible run time. 
     The placement optimization starts with creating the list of available bumps which are candidates for placement if desired by the algorithms. The available bumps are identified as those neither in the list of pre-placed bumps which are compulsory, nor in the list of one or more excluded bumps which are never considered for placement (e.g., reserved for signal or other nets). Then, the provided algorithms choose one or more of available bumps, and the output footprint is to place the chosen bumps, in addition to the pre-placed ones. 
     The provided algorithms select one or more candidate sets consisting one or more available bumps, evaluate the candidates, choose the best, and place the bump(s). This process repeats until the constraints are met or all available bumps are placed. The candidate sets consist of one or more of: all available bumps, only available bumps in defined hot spots, or only available bumps closest to the bumps violating the constraints most (e.g., highest current or worst reliability). The footprint including the bump(s) of each candidate, the pre-placed ones, and if any, the bump(s) chosen in the previous iterations is evaluated. Then, the best footprint is chosen by one of: largest reduction on max current, lowest max current, largest improvement on reliability, or best reliability. Finally, the bump(s) of the chosen candidate is (are) added to the placed list, and the entire process (i.e., candidate selection, evaluation, and chosen bumps placement) repeats if needed. 
       FIG. 20  is an example flow chart of C4 placement optimization with the lowest maximum current by using the minimum number of bumps. At  805 , the C4 footprint of full population is provided with a list of C4 bumps to be always included (i.e., pre-placed) or excluded (i.e., never placed) in the final footprint. In addition, C4 current and count limits, I limit  and N limit , are given as constraints. At  810 , the list of C4 bumps that can be considered for placement, C4 avail , is created by deleting the bumps in the list of those included or excluded from the full list. In addition, the list of C4 bumps that are chosen for placement, C4 added , are initially created from the included list. 
     At  815 , there is performed evaluating the C4 added  footprint and obtaining the max C4 current I max (C4 added ). At  820 , it is determined whether I max (C4 added ) is smaller than I limit . If I max (C4 added )≦I limit , the process proceeds to  850  where the added bumps C4 added  is saved to the footprint. Otherwise, if it is determined at  820  that I max (C4 added )&gt;I limit  then the process proceeds to  825  where it is determined whether N(C4 added )≦N limit . If N(C4 added )&gt;N limit , the process proceeds to  850  where the added bumps C4 added  is saved to the footprint. Otherwise, if it is determined at  825  that N(C4 added )≦N limit , then the process proceeds to  830  where it is determined whether C4 avail  is empty (i.e., there is still any available bump that has not been added to C4 added ). If C4 avail  is empty, the process proceeds to  850  where the added bumps C4 added  is saved to the footprint. Otherwise, if it is determined at  830  that C4 avail  is not empty, then the process proceeds to  835  where for each candidate set of one or more bumps, C4 candi , in C4 avail , there is performed evaluating the C4 current of the footprint that consists of the bumps of C4 added  and C4 candi . Then there is performed choosing the best footprint from all alternatives by using exhaustive search or one of the methods described herein above. Finally, the process proceeds to  840  where C4 added  is updated by adding the bumps of C4 chosen , the chosen C4 candi  at  835 , and then returning to  815  to repeat the loop with the updated C4 added . 
     A similar methodology is constructed for different aspects and constraints such as electromigration reliability or the number of bumps per unit area. 
       FIG. 21  illustrates an exemplary hardware configuration of a computing system  400  running and/or implementing the method steps described herein with respect to  FIGS. 2 ,  5 ,  6 ,  11 ,  15 ,  19  and  20 . The hardware configuration preferably has at least one processor or central processing unit (CPU)  411 . The CPUs  411  are interconnected via a system bus  412  to a random access memory (RAM)  414 , read-only memory (ROM)  416 , input/output (I/O) adapter  418  (for connecting peripheral devices such as disk units  421  and tape drives  440  to the bus  412 ), user interface adapter  422  (for connecting a keyboard  424 , mouse  426 , speaker  428 , microphone  432 , and/or other user interface device to the bus  412 ), a communication adapter  434  for connecting the system  400  to a data processing network, the Internet, an Intranet, a local area network (LAN), etc., and a display adapter  436  for connecting the bus  412  to a display device  438  and/or printer  439  (e.g., a digital printer of the like). 
     As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system.” Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. 
     Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with a system, apparatus, or device running an instruction. 
     A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with a system, apparatus, or device running an instruction. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing. 
     Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may run entirely on the user&#39;s computer, partly on the user&#39;s computer, as a stand-alone software package, partly on the user&#39;s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user&#39;s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). 
     Aspects of the present invention are described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which run via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. 
     The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which run on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. 
     The flowcharts and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more operable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be run substantially concurrently, or the blocks may sometimes be run in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. 
     While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the scope of the invention not be limited to the exact forms described and illustrated, but should be construed to cover all modifications that may fall within the scope of the appended claims.