Abstract:
The present invention demonstrates a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN can be determined and presented to the output CLKOUT. If used for data sampling, a phase clock that lags the phase clock most in synchronization may be selected to appear at CLKOUT. This guarantees that sampled data are static during sampling. This system is less complex and consumes minimal power over systems using variable delay circuits.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention generally relates to a method used in semiconductor manufacturing and, more particularly, to a phase-locked loop (PLL) method used to synchronize circuit timing in the fabrication of integrated circuits (ICs).  
           [0003]    2. Description of Prior Art  
           [0004]    Because sequential data may vary in both frequency and phase, phase-locked loops with both frequency and phase locking are typically used to sample that data. The design of these systems is complex and the circuits consume substantial power. One application where this is utilized is in the transfer of data to a display in a portable computer. Here, especially, the excessive power dissipation is undesirable.  
           [0005]    Refer now to FIG. 1 showing a typical PLL system for generating an internal synchronization clock (CLKOUT). The reference clock (CLKIN) is applied to the input of a variable delay circuit  10  and the input of a phase comparator  12 . The output, CLKOUT, of the variable delay circuit  10  is applied to a second input of the phase comparator  12 . The phase comparator  12  output, PCOUT, is an error signal that indicates whether the rising edge of CLKOUT leads or lags CLKIN. PCOUT is then applied to the variable delay circuit  10  to either advance or retard CLKOUT in order to maintain the proper phase relationship. One problem with this circuit is the complexity of the phase comparator and variable delay circuit. The variable delay circuit is typically composed of a plurality of series connected inverter pairs where phase and frequency are changed by adding or removing inverter pairs. Another problem is that the circuit corrects the phase relationship even when the phase difference is small. This results in output jitter and substantial power dissipation during the correction cycle. Finally, this method is poor for applications requiring a wide frequency range and where the frequency of CLKOUT is N times that of CLKIN.  
           [0006]    Other approaches related to improving PLL circuits exist. U.S. Pat. No. 6,157,690 to Yoneda teaches a method where a PLL phase correction circuit has three modes of operation. When the phase difference between the input and output clock are within a first minimum range, no phase correction is performed. When the phase difference between the input and output clocks exceed the first minimum range, but fall within a second larger range, a slow correction method that consumes a low level of power is employed. When the phase difference exceeds the second range, a faster method using more power is used. U.S. Pat. No. 5,694,068 to Rokugo teaches a method where the input and output frequencies are each applied to frequency dividers. The frequency dividers generate multiple phases of the divided signal, which are applied to a plurality of quantized phase comparators. The output of the quantized comparators are added and when the sum reaches a certain upper (or lower) limit, a pulse is decremented (or added) to a pulse train which is later divided to create the output frequency. U.S. Pat. No. 5,923,715 to Ono teaches a method where both frequency and phase differences are used to control the PLL signal output. A variable delay circuit with both inverters and capacitors to adjust phase is used. U.S. Pat. No. 6,384,650 B1 to Fukunaga et al. teaches a method using an additional control loop with an adder and differentiator to calculate the frequency difference between the fixed oscillator and PLL output, memory to store that difference, and another circuit to compare the current frequency difference with the previously memorized difference. The result from this additional control loop contributes to the voltage controlled output oscillator frequency. U.S. Pat. No. 6,389,091 B1 to Yamaguchi et al. teaches a method of PLL where the variable controlled oscillator (VCO) frequency is varied by connecting and disconnecting paralleled transistors in a loop containing an odd number of inverters. Using this method, more precise control of the frequency may be made thereby minimizing jitter.  
         SUMMARY OF THE INVENTION  
         [0007]    A principal object of the present invention is to provide a method that produces a PLL clock with a phase nearest to that of an external clock.  
           [0008]    Another object of the present invention is to provide a circuit that produces a PLL clock with a phase nearest to that of an external clock.  
           [0009]    A further object of the present invention is to provide a method that produces a PLL clock with a phase nearest to that of an external clock while consuming minimal power.  
           [0010]    A still further object of the present invention is to provide a circuit that produces a PLL clock with a phase nearest to that of an external clock while consuming minimal power.  
           [0011]    Another object of the present invention is to provide a method that identifies a PLL clock with a phase that follows an external clock by a specific interval in order to assure proper data sampling.  
           [0012]    A yet further object of the present invention is to provide a circuit that identifies a PLL clock with a phase that follows an external clock by a specific interval in order to assure proper data sampling.  
           [0013]    These objects are achieved by using a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN can be determined and presented to the output CLKOUT. If used in sampling, a phase clock which lags the phase clock most in synchronization may be selected to appear at CLKOUT. This guarantees that sampled data are static during the sampling interval. This system is less complex than prior art designs and consumes less power over systems using variable delay circuits. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    In the accompanying drawings forming a material part of this description, there is shown:  
         [0015]    [0015]FIG. 1 schematically illustrating a block diagram representation of a typical PLL system;  
         [0016]    [0016]FIG. 2 schematically illustrating a block diagram of the phase synchronizing system of the present invention;  
         [0017]    [0017]FIGS. 3 a  and  3   b  illustrating a schematic representation of a first and second four bit example of the phase selector circuit used in FIG. 2; and  
         [0018]    [0018]FIG. 4 illustrating the timing diagram of the phase selector circuit of FIGS. 3 a  and  3   b.   
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]    Refer now to FIG. 2, depicting in block diagram the phase selection method of the present invention. Two identical phase selectors, PSA  60  and PSB  62  are provided. A detailed description of the operation of the phase selector ( 60  and  62 ) will be discussed later. An external clock, CLKIN from a “frequency lock only” PLL is applied to PSA  60  and also to a delay circuit  64 . The output of the delay circuit  64  is then applied to PSB  62 . Both PSA  60  and PSB  62  have a plurality (n) of phase clocks (PH 0  through PH n−1 ) applied. These phase clocks are approximately n times the frequency of CLKIN and are shifted equally by approximately 360°/n (PH 1  lags PH 0  by 360°/n, PH 2  lags PH 1  by 360°/n, etc.). PSA  60  has an output bus FLAGA with n bits labeled FLAGA 0  through FLAGA n−1 ; similarly, PSB  62  has an output bus FLAGB with n bits labeled FLAGB 0  through FLAGB n−1 . CLKIN, FLAGA and FLAGB are applied to a judgment logic circuit  66 . The output of the judgment logic circuit  66  is an m-bit select signal that is applied along with PH 0  through PH n−1  to a multiplexer (MUX)  68 . The output of the MUX  68  is the CLKOUT signal.  
         [0020]    Refer to FIG. 3 a  showing the circuit for each phase selector ( 60  or  62 ). For this example, four phase clocks will be used so that phase clock signals PH 0  through PH 3  will be inputs (n=4). It will be understood by those skilled in the art that more phase clocks and corresponding additional circuitry could be achieved without departing from the spirit and scope of the invention. Four input D flip-flops (DFF)  80 - 83  are provided all having CLKIN connected to the D inputs and each having PH 0 , PH 1 , PH 2 , and PH 3 , respectively, connected to the clock input. The outputs of the four DFFs  80 - 83  are CLKPH 0 , CLKPH 1 , CLKPH 2 , and CLKPH 3 , respectively. Four (4) output DFFs  85 - 88  are connected as follows:  
         [0021]    CLKPH 0  provides the clock input for DFF 85  and the D input for DFF  88 ,  
         [0022]    CLKPH 1  provides the clock input for DFF 86  and the D input for DFF  85 ,  
         [0023]    CLKPH 2  provides the clock input for DFF 87  and the D input for DFF  86 , and  
         [0024]    CLKPH 3  provides the clock input for DFF 88  and the D input for DFF  87 .  
         [0025]    The outputs of DFFs  85 ,  86 ,  87  and  88  are FLAG 0 , FLAG 1 , FLAG 2 , and FLAG 3 , respectively. In the broader embodiment where n phase clocks are provided, the first output DFF has its D input connected to the clock of the second output DFF, the second output DFF has its D input connected to the clock of the third output DFF, etc, and the n th  output DFF has its D input connected to the clock of the first output DFF.  
         [0026]    A second embodiment depicted in FIG. 3 b  would have the four (4) output DFFs  85 - 88  connected such that:  
         [0027]    CLKPH 0  provides the clock input for DFF 85  and the D input for DFF  87 ,  
         [0028]    CLKPH 1  provides the clock input for DFF 86  and the D input for DFF  88 ,  
         [0029]    CLKPH 2  provides the clock input for DFF 87  and the D input for DFF  85 , and  
         [0030]    CLKPH 3  provides the clock input for DFF 88  and the D input for DFF  86 .  
         [0031]    The outputs of DFFs  85 ,  86 ,  87  and  88  are FLAG 0 , FLAG 1 , FLAG 2 , and FLAG 3 , respectively. In the broader embodiment where n phase clocks are provided, the first output DFF has its D input connected to the clock of the third output DFF, the second output DFF has its D input connected to the clock of the fourth output DFF, etc, the n−1 th  output DFF has its D input connected to the clock of the first output DFF and the n th  output DFF has its D input connected to the clock of the second output DFF.  
         [0032]    Referring to FIGS. 3 and 4, the operation of the phase selector ( 60  or  62 ) is now discussed. Since n is four (4) signals PH 0  through PH 3  will differ in phase by 90° (360°/4) as shown in FIG. 4. Each input DFF  80 - 83  uses its respective phase clock input (phase clocks PH 0 , PH 1 , PH 2 , and PH 3 ) to store the value of CLKIN at its respective output (CLKPH 0 , CLKPH 1 , CLKPH 2 , and CLKPH 3 ). Storing takes place on the rising edge (for example) of each phase clock, thus, if on the rising edge of PH x . CLKIN is a logic  1  (high), CLKPH x , will become a logic  1 . If on the rising edge of PH, CLKIN is a logic  0  (low), CLKPH x , will become a logic  0 . As previously described, the output DFFs  85 - 88  are connected such that CLKPH. provides a D input for one output DFF and the clock input for an adjacent output DFF. On the rising edge of CLKPH 0 , FLAG 0  will assume the logic level on CLKPH 1 , on the rising edge of CLKPH 1 , FLAG 1 , will assume the logic level on CLKPH 2 , on the rising edge of CLKPH 2 , FLAG 2  will assume the logic level on CLKPH 3 , and on the rising edge of CLKPH 3 , FLAG 3  will assume the logic level on CLKPH 0 . As shown in the example timing diagram of FIG. 4, because of the position of CLKIN with respect to the phase clocks (PH 0  through PH n ) in this example, CLKPH 2  leads the other CLKPH x  signals. Additionally, each of the remaining CLKPH X  signals lags behind its previous (CLKI x−1 ) signal. In this example, on the rising edge of CLKPH 1 , CLKPH 2  is high so FLAG 1  will become a logic high thereby indicating that PH 2  is most in phase with CLKIN. All the remaining FLAG X  signals stay low.  
         [0033]    Referring again now to FIG. 2, each phase selector PSA  60  and PSB  62  will generate a FLAG bus (FLAGA and FLAGB) each of which will have a single high level indicating which PH X  is most in phase with either CLKIN (on PSA  60 ) or the delayed CLKIN (on PSB  62 ). The judgment logic circuit  66  in conjunction with MUX  68  is used to determine which PH X  to select as CLKOUT. If the system is being used to sample data, and phase clock PH X  is found to be most in phase with CLKIN, a later phase clock such as PH X+2  (for example) might be used to guarantee that data is present prior to sampling. By using both PSA  60  and PSB  62 , the best PH X  can be chosen to minimize jitter on CLKOUT. In case metastability occurs with PSA  60  (all FLAG X  are ‘0’), the delay circuit  64  will result in a valid CLKPH X  and FLAG X  pattern on PSB  62 . In certain applications, where metastability is not a problem, the PSB  62  and delay  64  circuits may be eliminated.  
         [0034]    These objects of the present invention are thus achieved using a method where a phase selector identifies which internally generated phase clock is most in phase with the input clock CLKIN. Once this phase clock is identified, it may be selected using a MUX and presented at the output CLKOUT. The system does not require a feedback loop, or series of inverter pairs to generate the PLL circuitry and is therefore less complex and uses less power. If used in a sampling application, a phase clock which lags behind the in phase clock may be used to assure data presence.  
         [0035]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.