Abstract:
An apparatus for emulating, testing, interrogating, debugging, and programming an integrated circuit is provided. The apparatus has a boundary scan adapter in association with a host computer for accepting a control signal from the host computer, and for generating an intermediate signal for acceptance by the integrated circuit which intermediate signal is compliant with the specifications of the integrated circuit. Also, the apparatus has an interface associated with the integrated circuit for accepting the intermediate signal from the boundary scan adapter. The control signal from the host computer has a magnitude greater than the magnitude of the intermediate signal which intermediate signal is specific to and compliant with the operation of the integrated circuit.

Description:
FIELD OF THE INVENTION  
       [0001]     The present invention relates to boundary scan interface logic on integrated circuits and how the defined signal levels are used. Specifically, the present invention relates to integrated circuits operating at low voltages with a boundary scan interface, and providing for the integrated circuit to be emulated, tested, interrogated, debugged, and programmed.  
       BACKGROUND OF THE INVENTION  
       [0002]     The present invention relates to the type of integrated circuits which operate at a low voltage level. Typically, such integrated circuits are used in portable communications devices such as cellular telephones and hand held video games.  
         [0003]     To reduce the cost of the customer&#39;s end product in high volume production, the integrated circuit with a boundary scan interface operates at a low voltage. The boundary scan interface may be, for example, a microprocessor, a gate array or Digital Signal Processor. A low voltage may be considered as 1.8 or 2.5 volts DC. Such an arrangement has no logic to interface to the boundary scan interface which operates at a higher voltage, such as for example, +5 volts DC.  
         [0004]     If an existing boundary scan adapter were attached to the customer&#39;s end product, the boundary scan adapter and the customer&#39;s end product may be damaged because of the potential difference of +5 VDC, on one hand, and +1.8 or 2.5 VDC, on the other hand, between the two pieces of logic. For the engineer to develop the product safely, a two step process would have to take place. A prototype would need to be designed with special voltage logic for boundary scan emulation so the software algorithms for the integrated circuit could be debugged. And thereafter, the real end product must be designed without specialized voltage logic. Such a designing procedure means the “existing” boundary scan emulator cannot be used. This approach is time consuming and expensive. Two different products have to be developed, and the final product cannot be completely debugged and tested.  
         [0005]     The referenced type of integrated circuits operate at a voltage lower than +3.3 or +5 volts DC, such as for example, 2.5 or 1.8 volts DC. These lower voltages used by the integrated circuit preclude the use of existing boundary scan adapters. Existing boundary scan adapters expect to interface with boundary scan logic operating at 3.3 or 5.0 volts DC. This means existing boundary scan adapters cannot be used to test, interrogate, debug software algorithms, and program non-volatile memories in the system.  
         [0006]     It is, therefore, a feature of the present invention to provide an adjustable voltage boundary scan adapter, used for emulation and test, that can operate with integrated circuit boards having low voltages.  
         [0007]     A feature of the present invention is to provide an adjustable voltage boundary scan adapter, when used for emulation and test, that does not require additional support circuitry around the integrated circuit.  
         [0008]     Another feature of the present invention is to provide an adjustable voltage boundary scan adapter that can be have its interface logic voltage levels adjusted to match the voltage levels present on the integrated circuit.  
         [0009]     Another feature of the present invention is to provide an adjustable voltage boundary scan adapter to allow low voltage integrated circuits with a boundary scan interface to be tested.  
         [0010]     Another feature of the present invention is to provide an adjustable voltage boundary scan adapter to allow low voltage integrated circuits with a boundary scan interface to be interrogated.  
         [0011]     Yet another feature of the invention is to provide an adjustable voltage boundary scan adapter to allow low voltage integrated circuits with a boundary scan interface to debug software algorithms.  
         [0012]     Still another feature of the present invention is utilizing an adjustable voltage boundary scan adapter to allow low voltage integrated circuits with a boundary scan interface to program non-volatile memory in the system without special logic in the system.  
         [0013]     Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will become apparent from the description, or may be learned by practice of the invention. The features and advantages of the invention may be realized by means of the combinations and steps particularly pointed out in the appended claims.  
       SUMMARY OF THE INVENTION  
       [0014]     To achieve the foregoing objects, features, and advantages and in accordance with the purpose of the invention as embodied and broadly described herein, an adjustable voltage boundary scan adapter that can be used for emulation and test is provided. The purpose of the adjustable voltage boundary scan adapter of the present invention is to allow low voltage integrated circuits with a boundary scan interface to be tested, interrogated, software algorithms debugged, and non-volatile memory in the system programmed without special logic in the system.  
         [0015]     The adjustable voltage boundary scan adapter of the present invention allows the user to select the voltage level at which an integrated circuit boundary scan interface will operate. In one embodiment, this selection is done with a rotary selection switch on the adjustable voltage boundary scan adapter. Other embodiments could include making this selection with a potentiometer or physical jumper connection. The adjustable voltage boundary scan adapter has a programmable integrated circuit which reads the switch setting selections and adjusts its boundary scan signal levels accordingly.  
         [0016]     In one embodiment, an apparatus for emulating, testing, interrogating, debugging, and programming an integrated circuit is provided comprising a boundary scan adapter and an interface associated with the integrated circuit. The boundary scan adapter is in association with a host computer for accepting a control signal from the host computer, and for generating an intermediate signal for acceptance by the integrated circuit. The intermediate signal is compliant with the specifications of the integrated circuit. The interface associated with the integrated circuit is for accepting the intermediate signal from the boundary scan adapter. The control signal from the host computer has a magnitude greater than the magnitude of the intermediate signal which intermediate signal is specific to and compliant with the operation of the integrated circuit.  
         [0017]     In another embodiment, an apparatus for emulating, testing, interrogating, debugging, and programming an integrated circuit is provided comprising a host computer, a boundary scan adapter and an interface associated with the integrated circuit. The host computer generates a control signal for the apparatus. The boundary scan adapter is in association with the host computer for accepting the control signal from the host computer, and for generating an intermediate signal for acceptance by the integrated circuit. The intermediate signal is compliant with the specifications of the integrated circuit. The boundary scan adapter comprises a controller for accepting the control signal from the host computer and for generating a driver signal, the driver signal being at least one of equal to or not equal to the control signal, and a pin driver/receiver for receiving the driver signal from the controller and for generating an intermediate signal for acceptance by the integrated circuit which intermediate signal is compliant with the specifications of the integrated circuit. The interface associated with the integrated circuit accepts the intermediate signal from the boundary scan adapter. The control signal from the host computer has a magnitude greater than the magnitude of the intermediate signal which intermediate signal is specific to and compliant with the operation of the integrated circuit.  
         [0018]     The following sequence is an example used by the adjustable voltage boundary scan adapter to determine the voltage at which to set its boundary scan signal levels.  
         [0019]     1. When the cable from the adjustable voltage boundary scan adapter is plugged into a logic card resident in a personal computer and power is applied to the adjustable voltage boundary scan adapter, LEDs (light emitting diodes) will flash for a specified period of time.  
         [0020]     2. A multi-position rotary switch is read by a microprocessor and the voltages are set per an appropriate table of values.  
         [0021]     3. The presence/power detect (PD) signal is monitored until its voltage level exceeds the Power Detect Input Threshold. An LED under the control of a microprocessor will flash until this condition is met.  
         [0022]     4. When the integrated circuit power is detected the JTAG outputs of the adjustable voltage boundary scan adapter will be enabled.  
         [0023]     5. Once the JTAG outputs are enabled, the test-reset-input (TRST) line is monitored and the microprocessor will flash an LED until the TRST line is taken high by the software driver of the adapter in the personal computer. Once the TRST line is taken high, EMU0 will be released from its Wait-In-Reset value and return to a tri-state condition. The LED will then turn off.  
         [0024]     6. When target power is detected and TRST is high and the LEDs will reflect the rotary switch setting.  
         [0025]     7. The PD and TRST pins are monitored continuously. If either signal drops below its high threshold then the power detection sequence will start over at step #2. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0026]     The accompanying drawings which are incorporated in and constitute a part of the specification, illustrate a preferred embodiment of the invention and together with the general description of the invention given above and the detailed description of the preferred embodiment given below, serve to explain the principles of the invention.  
         [0027]      FIG. 1A  is an illustration of the system of the present invention.  
         [0028]      FIG. 1B  is a block diagram of the system illustrated in  FIG. 1A .  
         [0029]      FIG. 1C  is an illustration of the relationship of the boundary scan apparatus with the integrated circuit.  
         [0030]      FIG. 2  is an illustration of another embodiment of the software development system of the present invention.  
         [0031]      FIG. 3A  is an illustration of one embodiment of a generic pin driver/receiver.  
         [0032]      FIG. 3B  is an illustration of another embodiment of a pin driver/receiver.  
         [0033]      FIG. 4A  illustrates a generic pin receiver.  
         [0034]      FIG. 4B  is another embodiment of a pin receiver.  
         [0035]      FIG. 4C  is yet another embodiment of a pin receiver.  
         [0036]      FIG. 5  is another embodiment of a master control block.  
         [0037]      FIG. 6  illustrate still another embodiment of the master control block.  
         [0038]      FIG. 7  illustrates a more complex version of the embodiment of the present invention.  
         [0039]      FIG. 8  illustrates yet another embodiment of the present invention. 
     
    
       [0040]     The above general description and the following detailed description are merely illustrative of the generic invention, and additional modes, advantages, and particulars of this invention will be readily suggested to those skilled in the art without departing from the spirit and scope of the invention.  
       DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]     Reference will now be made in detail to the present preferred embodiments of the invention as described in the accompanying drawings.  
         [0042]     The present invention relates to the boundary scan interface logic on integrated circuits defined in accordance with the IEEE 1149.1 standard and how the defined signal levels are used. With the boundary scan interface on the integrated circuit, a boundary scan adapter, and the appropriate software, the integrated circuit can be controlled. With this software controlling the boundary scan adaptor the integrated circuit can be emulated, tested, interrogated, software algorithms can be debugged, and non-volatile memory in the system can be programmed.  
         [0043]      FIG. 1A  is an illustration of the system  10  of the present invention. The system  10  comprises a host computer  12  with software connected to the boundary scan adapter  100  of the present invention. The boundary scan adapter  100  is connected to an integrated circuit  14 . The host computer  12  is connected to the boundary scan adapter  100  by a conductor cable  16 . The boundary scan adapter  100  is connected to the integrated circuit by a cable  18  and JTAG connector.  
         [0044]      FIG. 1B  is a block diagram of the system  10  illustrated in  FIG. 1A .  FIG. 1B  illustrates the host computer  12  with software being connected via the conductor cable  16  to the boundary scan adapter  100 . The boundary scan  100  is connected to the integrated circuit  14  via the JTAG connector  18 .  
         [0045]      FIG. 1C  is an illustration of the relationship of the boundary scan apparatus  100  with the integrated circuit  12 . A cable  16  provides communication between the host computer (not shown) and the boundary scan apparatus  100 . The cable  16  has an input line  102  and from the host computer to the boundary scan apparatus  100 , and an output line  108  from the boundary scan apparatus  100  to the host computer. Similarly, the conductor cable  18  provides communication between the boundary scan apparatus  100  and the integrated circuit  12 . The conductor cable  18  has an input line  104  from the boundary scan apparatus  100  to the integrated circuit  12 , and an output line  106  from the integrated circuit  12  to the boundary scan apparatus  100 .  
         [0046]     The signal A 1  is a data stream from the host computer to the boundary scan apparatus  100 . Typical voltage levels for the data stream A 1  are from 0 to 5 volts, or TTL compatible. The data stream B 1  from the boundary scan apparatus  100  to the host computer is also typically between 0 and 5 volts, or TTL compatible. The data stream A 2  from the boundary scan apparatus  100  to the integrated circuit  12  is carried by the conductor  104  in the cable  18 . The data stream A 2  has voltage levels that are variable. Also, the data stream A 2  is required not to exceed the specifications for the integrated circuit  12 . Typically, the voltage levels required by the data stream A 2  in practicing the present invention are from 0 volts to a maximum of approximately 3.3 volts. Typically, the 0 volts is for the −V signal and the higher level voltage, for example the 3.3 volts, is for the +V signal. The digital data stream B 2  is provided as an output from the integrated circuit  12  to be accepted by the boundary scan apparatus  100 . The digital data stream B 2  is carried by the conductor  106  of the cable  18 . The voltage levels associated with the digital data stream B 2  are set and determined by the voltage requirements of the integrated circuit  12 . The voltage levels for the digital data stream B 2  are generally between 0 volts and 5 volts. The 0 volt level is associated with the −V signal and the higher, for example 5 volt signal, is associated with the +V signal.  
         [0047]     The boundary scan apparatus  100  provides a unique method of converting the digital data stream A 1  from the host computer to the apparatus  100  to a different voltage level, digital data stream A 2  for acceptance by a particular integrated circuit  12 . Similarly, the adjustable voltage boundary scan adapter of the present invention provides a unique way of converting the voltage levels B 2  from the particular integrated circuit  12  to a voltage level B 1  which is usable by the host computer. Typically, the digital data streams between the host computer and the boundary scan apparatus  100  are fixed by the host computer. It is important to note that the digital data streams between the boundary scan apparatus  100  and the integrated circuit  12  are variable. The variable data streams A 2 , B 2  are set by the integrated circuit  12  or “target” device. The digital data streams between the boundary scan apparatus  100  and the integrated circuit  12  are required at specific levels based on the technology of the integrated circuit  12 .  
         [0048]      FIG. 2  is an illustration of another embodiment of a software development system  200  of the present invention. The software development system  200  comprises a master control block  201  and a pin driver/receiver  203 . The signal A 1  is input through a line  202  into a master control  201 . The signal A 1  is a digital data stream form the host computer. Typical voltages for data stream A 1  are from 0 to 5 volts, or TTL compatible. The digital data stream B 1  from the master control block  201  to the host computer is transferred along line  208 . The digital data stream B 1  has typical voltages from 0 to 5 volts, or TTL compatible. The data stream from the master control block  201  to the pin driver/receiver  203  are implementation or application specific. The data stream A 3  may, or may not, be equal to A 1  or A e . The data stream B 3  from the pin driver/receiver  203  to the master control block  201  is the converse signal of data stream A 3 , but is in the reverse direction. Typically, the amplitude or levels of the data streams A 3  and B 3  are approximately the same. The data stream A 2  from the pin driver/receiver  203  to the integrated circuit  12  are variable and can not exceed the specifications for the integrated circuit  12 . The levels of the data stream A 2  vary generally from 0 to approximately 3.3 volts for the −V value and the +V value, respectively. The digital data stream B 2  from the integrated circuit  12  to the pin driver/receiver  203  are variable and set by the voltage requirements of the integrated circuit  12 . The levels of the data stream B 2  are generally over the values of −V and up to 5 volts for the +V value.  
         [0049]     The connections  212 ,  214 ,  216  and  218  provide specific control characteristics for the system  200  of the present invention. The voltage supply/level V 1  is for the signal output A 2 . The voltage supply/level V 1  sets the voltage of A 2 . The voltage threshold V 2  is for the signal input B 2  from the integrated circuit  12  to the pin driver/receiver  203 . The voltage threshold V 2  sets the threshold voltage for the inputs B 1 . The voltage threshold V 3  is for sensing the integrated circuit voltage level, V cc . The voltage threshold V 3  can be used to determine when power is applied to the integrated circuit or for automatic sensing of the integrated circuit voltage level V cc . The voltage feedback V 4  from the voltage supply level V 1 , the voltage threshold V 2  and the voltage threshold V 3  is to provide a closed loop system.  
         [0050]     The master control block  201  has various functions. The master control block  201  formats the data stream A 1  into an internal voltage level A 3  format. The data stream A 1  can be parallel, serial, or some higher level compound format. The data stream A 3  is a 1-to-1 representation of the data stream A 2 , except for the internal voltage levels. Further, the master control block  201  provides a reverse function for the return data streams B 2 , B 2 , and B 3 . The master control block  201  generates the appropriate voltage levels for the voltage supply/level V 1 , the voltage threshold V 2  for the signal input B 2 , and the voltage threshold V 3  for the sensing of the integrated circuit voltage level. Also, the master control block  201  uses the feedback voltage V 4  to create a closed loop system. The closed loop system protection from over-voltage or under-voltage conditions at the integrated circuit  12 . Control implantation from the host computer, user or other input device is provided to the master control block  201 . The master control block  201  uses the information from the host computer, user or other input device to offset voltage discrepancies at the voltage supply/level V 1 , the voltage threshold V 2  or the voltage threshold V 3 .  
         [0051]     The pin driver/receiver  203  also has several functions. The pin driver/receiver  203  converts the data stream A 3  from an internal fixed voltage level to the voltage level of the integrated circuit  12  based on the voltage supply/level V 1 . Also, the pin driver/receiver  203  converts the data stream B 2  from the integrated circuit voltage level to the data stream B 3  voltage level based on the threshold voltage B 2 . The pin driver/receiver  203  generates a target power on/off indicator based on the threshold voltage V 3 . Further, the pin driver/receiver  203  creates the feedback information V 4  on the line  218  based upon the voltages V 1 , V 2  and V 3  and the data streams A 2  and A 3 .  
         [0052]      FIG. 3A  is an illustration of a generic pin driver/receiver  203 A. The generic pin driver/receiver  203 A has a data stream A 3  as an input signal source. The resulting output driver signal A 2  is created. A voltage source V 1 + sets the upper voltage level of A 2  which can be indicated as A 2(VOH)  . The voltage level V 1 − sets the lower voltage level of A 2  or A 2(VOL) . By adjusting the voltage levels V 1 +, V 1 −, the resulting A 2  can swing between the voltage levels V 1 + and V 1 −.  
         [0053]      FIG. 3B  is an illustration of an inexpensive pin driver/receiver  203 B using off-the-shelve components. The voltage V 1 − is set to 0 volts. The voltage V 1 + is programmed to match the input voltage requirements of the integrated circuit  12  or data stream A 2 . Thus, the signal A 3  drives the enable pin of the gate G 1 . When A 3  is high, the gate G 1  is “off” and the voltage level A 2  is equal to the voltage V 1 +. When A 3  is low, the gate G 1  is “on” and the voltage A 2  is equal the voltage V 1 −. The resistor R 1  provides a current limit for the voltage V 1 +. The value of the resistor R 1  is chosen to match the requirements of the gate G 1 . The resistor R 2  is optional. The resistor R 2  can be used to effect the impedance of the data stream or signal A 2 . The simplicity and cost of the pin driver/receiver  203 B is an important feature. At about 15 cents per output pin, you get variable voltage for most common integrated circuit families whose levels range from 1.0 to 5.0 volts. The value of V 1 + may also have infinite adjustments within this range.  
         [0054]      FIG. 4A  illustrates a generic pin receiver  203 C. The generic pin receiver  203 C has the data stream V 2  input from the integrated circuit  12  or target. The voltage V 2  sets the output/input switch threshold B 2 . The data stream B 3  is the resulting signal. The signal B 3  has a level that matches that of the master control block  201 . The logic “0/1” state of the signal B 2  can be set by the voltage applied to V 2 . When the level on B 2  exceeds the level on V 2 , then B 2  is considered a “1” and the corresponding level on B 3  is set to “1.” When the level on B 2  falls below V 2 , then B 2  is considered a “0” and the corresponding level on B 3  is set to “ 0 .” The voltage associated with the V+/V− relationship sets the overall range of B 2  and B 3 . By controlling the voltage of V 2 , the “0/1” level of B 2  can be varied. The level on B 2  is independent of the A 2  levels. Thus, the voltage V 2  may be set above or below B 2  associated with the integrated circuit  12 . The typical “0/1” level to provide additional noise immunity is a noisy or lossy environment.  
         [0055]      FIG. 4B  is a specific implementation of a pin receiver  203 D. Such a specific embodiment provides that the voltage V+ is equal to +5 volts and the voltage V− is equal to 0. The embodiment with the pin receiver  203 D provides for a B 2  range of 0 to 5 volts.  
         [0056]      FIG. 4C  illustrates yet another embodiment of a pin receiver  203 E. The pin receiver  203 E provides an integrated circuit power detect device. By setting the value of voltage V 3 , the present invention can detect when the integrated circuit  12  is “on,” “off,” or in a “brown out” condition. Such condition information is generally necessary as feedback to control the signals A 3 , B 3 , V 1 , V 2 , A 2  and A 3 . For example, the most obvious control would be to “disable” output drivers A 2  in the case of an integrated circuit “off” or “brown out” condition. Such control would help prevent latch up of voltage back driving into the integrated circuit.  
         [0057]      FIG. 5  is another embodiment of a master control block  501 . The master control block  501  comprises a digital processing member  502  and an analog member  504 . The analog member  504  comprises a digital to analog converter  508  and an analog to digital converter  506 .  
         [0058]     The digital processing member  502  sends CMDS/data to the digital-to-analog converter  508  to generate the necessary voltage levels on V 1 , V 2 , V 3 , Also, the digital processing member  502  reads the levels on the V 4  inputs as digital data. The V 4  inputs represent the feedback path for V 1 , V 2 , V 3 , A 3  and B 3 .  
         [0059]     The digital processing member  502  provides overall control for the apparatus of the present invention. The digital processing member may be as simple as a bank of switches or as complicated as a full micro-processor/micro-computer control.  
         [0060]      FIG. 6  illustrates another embodiment of the master control block  600 . In a simple serial stream from the host computer, signal A 1  passes through to signal A 3 . Similarly, the signal B 3  passes through to signal B 1 . Thus, the data-in value is equal to the data-out value. No data value formatting is required. The V 1 -V 3  voltage levels are set by values on the digital to analog converter  608 . Alternately, the V 1 -V 3  voltage levels may be set by a device as simple as a resistor network. The voltage level V 4  may only represent the presence or the absence of power on the integrated circuit. In the event of no power on the integrated circuit, the A 3 /B 1  signal may be driven to “0” volts for safety reasons.  
         [0061]      FIG. 7  illustrates a more complex version of an embodiment of an adjustable voltage boundary scan adapter of the present invention. The signal A 2 , B 1  present high level commands and data. The micro-processor  702  processes the commands and data. The result of the processing of the micro-processor  702  may be sent or transferred to a particular test or emulation sequence to the integrated circuit  12 . Alternately, the result of the micro-processor  702  may be to adjust the voltage level on V 1 , V 2 , V 3 . When utilizing the micro-processor  702 , the actions on the feedback path can become complex. For example, all the leads V 1 , V 2, , V 3  may be determined by voltage levels on the integrated circuit supply. If the integrated circuit power turns “off” or “browns out,” the micro-processor  702  may respond by setting all the digital to analog converter outputs to “0” volts. The addition of a micro-processor  702  creates an overall smarter system with respect to the present invention. The voltage levels can be finely tuned to compensate for noise, drift, lossy lines, etc. It also enables the present invention to implement actions based on integrated circuit events or internal events. Typical micro-processor actions which are available when using the present invention are to set V 1 , V 2 , V 3 , based on integrated circuit power supply requirements; continually monitoring the integrated circuit power level looking for a loss of integrated circuit power; with respect to integrated circuit power loss, reprogramming the digital to analog converters to levels which protect the integrated circuit from damage; setting levels on V 1 , V 2 , V 3 , independent of integrated circuit power such that the integrated circuit power seen by the boundary scan apparatus of the present invention may not represent the true integrated circuit power; and making adjustments in V 1 , V 2 , V 3 , over time if drift compensation is required.  
         [0062]      FIG. 8  illustrates yet another embodiment of the present invention. With a modified integrated circuit  12 A. The modified integrated circuit  12 A has a test emulation interface  12 B and an integrated “core” function  12 C. The integrated circuit  12 A has an integrated circuit as simple as an SSI logic gate or as complex as a RISC or DSP processor. As changes in integrated circuit technology occur, the integrated circuits will operate at lower and lower voltages. Today, typical integrated circuits have 5 volt, 3.3 volt and 2.5 volt input output interfaces. Future devices will continue to reduce the voltage of the input output interfaces. It is expected that future devices will reduce the input output interfaces of the integrated circuits to 1.8 volts, 1.5 volts and 1.0 volts. With such a wide variety of voltage interfaces, a test/emulation interface is required to support the full range of interface voltages.  
         [0063]     Additional advantages and modification will readily occur to those skilled in the art. The invention in its broader aspects is therefore not limited to the specific details, representative apparatus, and the illustrative examples shown and described herein. Accordingly, the departures may be made from the details without departing from the spirit or scope of the disclosed general inventive concept.