Abstract:
A sequence circuit includes first through third signal terminals, first through ninth resistors, and first through fifth electronic switches. The sequence circuit receives a first signal through the first signal terminal. The sequence circuit receives a second signal through the second signal terminal. The sequence circuit outputs a third signal through the third signal terminal. The sequence circuit is used to ensure the sequence of the first through third signals.

Description:
FIELD 
     The subject matter herein generally relates to a sequence circuit. 
     BACKGROUND 
     Most signals for electronic devices are in a particular sequence. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached FIGURE. 
       The drawing is a circuit diagram of an embodiment of the sequence circuit. 
     
    
    
     DETAILED DESCRIPTION 
     Numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawing is not necessarily to scale and the proportions of certain parts have been exaggerated to better illustrate details and features of the present disclosure. 
     Several definitions that apply throughout this disclosure will now be presented. 
     The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series and the like. 
     The present disclosure is described in relation to a sequence circuit  10 . 
     The drawing illustrates the sequence circuit  10  can comprise resistors R 1 -R 9 , electronic switches Q 1 -Q 5 , a first signal terminal S 1 , a second signal terminal S 2 , a third signal terminal S 3 , a first power terminal V 1 , and a second power terminal V 2 . 
     The first signal terminal S 1  is coupled to a first terminal of the electronic switch Q 1  through the resistor R 1 . A second terminal of the electronic switch Q 1  is coupled to ground. A third terminal of the electronic switch Q 1  is coupled to a second terminal of the electronic switch Q 2 . A first terminal of the electronic switch Q 2  is coupled to the second signal terminal S 2  through the resistor R 3 . A third terminal of the electronic switch Q 2  is coupled to the first power terminal V 1  through the resistor R 4 . The third terminal of the electronic switch Q 2  is also coupled to a first terminal of the electronic switch Q 3 . A second terminal of the electronic switch Q 3  is coupled to ground. A third terminal of the electronic switch Q 3  is coupled to the first power terminal V 1  through the resistor R 5 . The third terminal of the electronic switch Q 3  is also coupled to a second terminal of the electronic switch Q 4 . A first terminal of the electronic switch Q 4  is coupled to a third terminal of the electronic switch Q 5 . A third terminal of the electronic switch Q 4  is coupled to the third signal terminal S 3 . The third terminal of the electronic switch Q 4  is also coupled to the first power terminal V 1  through the resistor R 6 . The third terminal of the electronic switch Q 5  is coupled to the first power terminal V 1  through the resistor R 7 . A second terminal of the electronic switch Q 5  is coupled to ground. A first terminal of the electronic switch Q 5  is coupled to the second power terminal V 2  through the resistor R 8 . The first terminal of the electronic switch Q 5  is coupled to ground through the resistor R 9 . The electronic switch is activated when the first terminal of the electronic switch is at logic 1 and the electronic switch is deactivated when the first terminal of the electronic switch is at logic 0. 
     The first signal terminal S 1 , the second signal terminal S 2 , and the third signal terminal S 3  are connected to a chip of a motherboard. The first power terminal V 1  and the second power terminal V 2  are connected to a power source of the motherboard. 
     In at least one embodiment, a first signal and a second signal are transmitted to the sequence circuit  10  from the chip of the motherboard. A third signal is transmitted to the chip of the motherboard from the sequence circuit  10 . The first signal, the second signal, and the third signal are used to control the motherboard to enter or quit a first mode. 
     When the motherboard is ready to enter the first mode, no voltage is output to the second power terminal V 2  and the electronic switch Q 5  is deactivated. The chip of the motherboard outputs the second signal of low level to the sequence circuit  10  through the second signal terminal S 2 . The electronic switch Q 2  is deactivated. The electronic switch Q 3  and the electronic switch Q 4  are activated. The chip receives the third signal of low level through the third signal terminal S 3 . After a preset period of time, the chip of the motherboard outputs the first signal of low level to the first signal terminal S 1 . Thus, when the motherboard is entering the first mode, the first signal, the second signal, and the third signal are at low level. The second signal is earlier than the third signal. The third signal is earlier than the first signal. 
     When the motherboard is ready to quit the first mode, the chip of the motherboard outputs a first signal of high level to the sequence circuit  10  through the first signal terminal S 1 . The electronic switch Q 1  is activated. After a preset time, the chip of the motherboard outputs the second signal of high level to the sequence circuit  10  through the second signal terminal S 2 . The electronic switch Q 2  is activated. The electronic switch Q 3  and the electronic switch Q 4  are deactivated. The chip of the motherboard receives the third signal of high level through the third signal terminal S 3 . Thus, when the motherboard is quitting the first mode, the first signal, the second signal, and the third signal are at high level. The first signal is earlier than the second signal. The second signal is earlier than the third signal. 
     In at least one embodiment, the electronic switches Q 1 -Q 5  are NPN transistors. 
     The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a sequence circuit  10 . Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, including in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.