Abstract:
A method for communicating via a bus including a first channel, a second channel, and a third channel is disclosed. The method includes addressing a slave device via the first channel, receiving from the slave device via the second channel, and writing to the slave device via the third channel. The method further includes selecting between first and second bus transmission modes. In the first bus transmission mode, payload write data is to be sent to the slave device via the first channel or the third channel. In the second bus transmission mode, during a first clock cycle, second payload write data associated with a second write operation is to be sent to the slave device via the first channel and first payload write data associated with a first write operation is to be concurrently sent to the slave device via the third channel.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims priority from and is a continuation of U.S. patent application Ser. No. 11/468,933, filed Aug. 31, 2006, which claims priority to U.S. Provisional Application No. 60/776,517 filed Feb. 24, 2006, the contents of both of which are expressly incorporated by reference herein in their entirety. 
         [0002]    The present application is related to co-pending U.S. patent application Ser. No. 11/468,908 filed on Aug. 31, 2006. 
     
    
     BACKGROUND 
       [0003]    1. Field 
         [0004]    The present disclosure relates generally to processing systems, and more specifically, to systems and techniques for performing auxiliary writes over the address channel of a bus. 
         [0005]    2. Background 
         [0006]    At the heart of most modern processing systems is an interconnect referred to as a bus. The bus moves information between various processing entities in the system. Today, most bus architectures are fairly standardized. These standardized bus architectures typically have independent and separate read, write and address channels. 
         [0007]    This type of bus architecture is often found in processing systems with one or more general purpose processors supported by memory. In these systems, the memory provides a storage medium that holds the programs and data needed by the processors to perform their functions. A processor may read or write to the memory by placing an address on the address channel and sending the appropriate read/write control signal. Depending on the state of the read/write control, the processor either writes to the memory over the write channel or reads from the memory over the read channel. In these types of processing systems, as well as many others, it is desirable to reduce the write latency and increase the write bandwidth. 
       SUMMARY 
       [0008]    One aspect of a processing system is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device. 
         [0009]    Another aspect of a processing system is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, means for addressing the receiving device on the first channel, means for reading a payload from the receiving device on the second channel, and means for selecting between the first and third channels to write a payload to the receiving device. 
         [0010]    An aspect of a method of communicating between a sending device and one or more receiving devices over a bus is disclosed. The bus includes first, second and third channels. The method includes addressing a receiving device on the first channel, reading a payload from the receiving device on the second channel, and selecting between the first and third channels to write a payload to the receiving device. 
         [0011]    An aspect of a bus mastering device is disclosed. The bus mastering device includes a processor, and a bus interface configured to interface the processor to a bus having first, second and third channels, the bus interface being further configured to address a slave on the first channel, receive a payload from the slave on the second channel, and select between the first and third channels to send a payload to the slave. 
         [0012]    Another aspect of a bus mastering device is disclosed. The bus mastering device includes a processor, and means for interfacing the processor to a bus having first, second and third channels, the means for interfacing the processor to the bus comprising means for addressing a slave on the first channel, means for receiving a payload from the slave on the second channel, and means for selecting between the first and third channels to send a payload to the slave. 
         [0013]    An aspect of a slave device is disclosed. The slave device includes memory, and a bus interface configured to interface the memory to a bus haying first, second and third channels, the bus interface being configured to receive a memory address and a first payload from a bus mastering device on the first channel, receive a second payload from the bus mastering device on the second channel, and send a payload to the bus mastering device on the third channel. 
         [0014]    Another aspect of a slave device is disclosed. The slave device includes memory, and means for interfacing the memory to a bus having first, second and third channels, the means for interfacing the memory to the bus comprising means for receiving a memory address and a first payload from a bus mastering device on the first channel, means for receiving a second payload from the bus mastering device on the second channel, and means for sending a payload to the bus mastering device on the third channel. 
         [0015]    It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein: 
           [0017]      FIG. 1  is a simplified block diagram illustrating an example of two devices in a processing system communicating over a bus; 
           [0018]      FIG. 2  is an illustration showing information flowing on the address and write channels of a bus in the processing system of  FIG. 1  with the address channel providing a generic medium for addresses and payloads; 
           [0019]      FIG. 3  is a timing diagram showing three write operations over a bus in the processing system of  FIG. 1 ; 
           [0020]      FIG. 4  is a simplified block diagram illustrating a sending device in communication with two receiving devices in a processing system; 
           [0021]      FIG. 5  is an illustration showing information flowing on the address and write channels of a bus in the processing system of  FIG. 4 ; 
           [0022]      FIG. 6  is a simplified block diagram illustrating an example of two devices in a processing system communicating over a 4-channel bus; 
           [0023]      FIG. 7  is a timing diagram showing three write operations over a bus in the processing system of  FIG. 6 ; 
           [0024]      FIG. 8  is a simplified block diagram illustrating a sending device in communication with three receiving devices in a processing system; and 
           [0025]      FIG. 9  is an illustration showing information flowing on the read and write address channels and write channels of a bus in the processing system of  FIG. 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0026]    The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. 
         [0027]      FIG. 1  is a simplified block diagram illustrating an example of two devices in a processing system communicating over a bus. The processing system  100  may be a collection of hardware devices that cooperate to perform one or more processing functions. Typical applications of the processing system  100  include, but are not limited to, desktop computers, laptop computers, servers, cellular phones, personal digital assistants (PDA), game consoles, pagers, modems, audio equipment, medical devices, automotive, video equipment, industrial equipment, or any other machine or device capable of processing, retrieving and storing information. 
         [0028]    The processing system  100  is shown with a sending device  102  in communication with a receiving device  104  over a bus  106 . The bus  106  includes three channels: an address channel  106   a , a write channel  106   b , and a read channel  106   c . A “channel” is defined as a set of electrical conductors used to carry information between two devices and which has a set of common control signals. In this example, the address channel is 32-bits wide, and the write and read channels are each 64-bits wide. Typically, a bus interconnect (not shown) will be used to establish a point-to-point communications path between the sending device  102  and the receiving device  104  over the bus  106 . Alternatively, the bus  106  may be a dedicated bus, a shared bus, or any other type of suitable bus architecture. 
         [0029]    The sending device  102  may be any type of bus mastering device. In this example, the sending device  102  includes a processor  108  and a bus interface  110 . The processor  108  may be a general purpose processor, such as a microprocessor, a special purpose processor, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), a direct memory access (DMA) controller, a bridge, a programmable logic component, or any other entity that requires access to the bus  106 . The bus interface  110  is used to drive the address and write channels  106   a ,  106   b , as well as provide the appropriate control signals. The bus interface  110  also serves as a receiver for the read channel  106   c.    
         [0030]    The receiving device  104  may be any type of slave device. The receiving device  104  may be temporary memory, such as SDRAM, DRAM, or RAM, or a longer term storage device such as flash memory, ROM memory, EPROM memory, EEPROM memory, CD-ROM, DVD, magnetic disk, rewritable optic disk and the like. Alternatively, the receiving device  104  may be a bridge or any other device capable of retrieving and storing information. In this example, the receiving device  104  includes a bus interface  112  and memory  114 . The bus interface  112  is used to drive the read channel  106   c  and the appropriate control signals. The bus interface  112  also serves as a receiver for the address and write channels  106   a ,  106   b . The memory  114  may be any device whose contents can be accessed (i.e., read and written to) randomly. 
         [0031]    In this bus architecture, the sending device  102  may read or write to the receiving device  104 . When the sending device  102  performs a write operation, it sends the address to the receiving device  104  on the address channel  106   a  with the appropriate control signals. The payload may be sent either on the address channel  106   a  or the write channel  106   b . The “payload” refers to the data associated with a particular read or write operation, and in this case, a write operation. When the sending device performs a read operation, it sends the address to the receiving device  104  on the address channel  106   a  with the appropriate control signals. In response, the receiving device  104  sends the payload to the sending device  102  on the read channel  106   c.    
         [0032]    An example of three write operations will now be described with reference to  FIG. 2 .  FIG. 2  is an illustration showing the information flowing on the address and write channels. In this example, the sending device initiates a 32-byte write operation followed by two 8-byte write operations. 
         [0033]    Referring to  FIG. 2 , on the first clock cycle  202 , the device initiates the 32—byte write operation by sending a 4-byte address A 1  to the receiving device on the address channel  106   a  with the appropriate control signals. During the same clock cycle  202 , the sending device also sends the first 8-bytes of the first payload W 1 ( 1 ) to the receiving device on the write channel  106   b.    
         [0034]    The sending device initiates the next write operation during the second clock cycle  204  by sending a 4-byte address A 2  to the receiving device before completion of the first write operation on the address channel  106   a  with the appropriate control signals. The sending device continues to transmit the first payload during the same clock cycle by sending the second 8-bytes W 1 ( 2 ) to the receiving device on the write channel  106   b.    
         [0035]    The sending device then uses the next two clock cycles  206  and  208  to send the second payload to the receiving device on the address channel  106   a , while concurrently completing the transmission of the first payload on the write channel  106   b . In particular, in the third clock cycle  206 , the sending device sends to the receiving device the first 4-bytes of the second payload W 2 ( 1 ) on the address channel  106   a  and the third 8-bytes of the first payload W 1 ( 3 ) on the write channel  106   b . On the fourth clock cycle  208 , the sending device sends to the receiving device the final 4-bytes of the second payload W 2 ( 2 ) on the address channel  106   a  and the final 8-bytes of the first payload W 1 ( 4 ) on the write channel  106   b.    
         [0036]    The sending device initiates the third write operation on the fifth clock cycle  210  by sending a 4-byte address A 3  to the receiving device on the address channel  106   a  with the appropriate control signals. During the same clock cycle  210 , the sending device also sends the third payload W 3  to the receiving device on the write channel  106   b.    
         [0037]    Two control signals may be added to the address channel  106   a  to create a medium to support the transmission of both addresses and payloads. The first control signal, referred to as an “Address/Data” signal is used to indicate whether the information being transmitted on the address channel  106   a  is an address or a payload. In this example, when the Address/Data signal is asserted, an address is being transmitted on the address channel  106   a . Conversely, when the Address/Data signal is deasserted, the payload is being transmitted on the address channel  106   a . The second control signal, referred to as a “Transfer Attribute,” is used when transmitting an address on the address channel  106   a . When an address is being transmitted, the “Transfer Attribute” signal is used to indicate whether the payload for that address will be transmitted on the address channel  106   a  or the write channel  106   b.    
         [0038]    An example illustrating how these control signals may be used will now be described with reference to  FIG. 3 . The bus protocol for the address and write channels  106   a ,  106   b  is shown below in Table 1. This bus protocol is being used to illustrate the inventive aspects of a processing system, with the understanding that such inventive aspects may be used with other bus protocols. Those skilled in the art will readily be able to vary and/or add signals to this protocol in the actual implementation of the bus architectures described herein. 
         [0000]    
       
         
               
               
               
             
               
             
               
               
               
             
               
             
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Signal 
                 Definition 
                 Driven By 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Address Channel 
               
             
          
           
               
                 Address 
                 32-bit medium to transmit 
                 Sending Device 
               
               
                   
                 addresses and payloads. 
               
               
                 Address/Data 
                 Indicates whether the 
                 Sending Device 
               
               
                   
                 information being 
               
               
                   
                 transmitted on the address 
               
               
                   
                 channel is an address or a 
               
               
                   
                 payload. 
               
               
                 AValid 
                 Indicates whether valid 
                 Sending Device 
               
               
                   
                 information is being 
               
               
                   
                 transmitted on the address 
               
               
                   
                 channel. 
               
               
                 Transfer Attribute 
                 Indicates whether the 
                 Sending Device 
               
               
                   
                 payload for the current 
               
               
                   
                 address will be transmitted 
               
               
                   
                 on the address channel or 
               
               
                   
                 the write channel. 
               
               
                 Read/Write 
                 Indicates whether a read or 
                 Sending Device 
               
               
                   
                 write operation is being 
               
               
                   
                 requested. 
               
               
                 Payload Size 
                 Indicates the size of the 
                 Sending Device 
               
               
                   
                 payload for the current 
               
               
                   
                 address. 
               
               
                 Address Transfer Ack 
                 Indicates whether the 
                 Receiving Device 
               
               
                   
                 receiving device has 
               
               
                   
                 successfully received 
               
               
                   
                 information transmitted on 
               
               
                   
                 the address channel. 
               
             
          
           
               
                 Write Channel 
               
             
          
           
               
                 Write 
                 64-bit medium to transmit 
                 Sending Device 
               
               
                   
                 payloads. 
               
               
                 WValid 
                 Indicates whether valid 
                 Sending Device 
               
               
                   
                 information is being 
               
               
                   
                 transmitted on the write 
               
               
                   
                 channel. 
               
               
                 Write Transfer Ack 
                 Indicates whether the 
                 Receiving Device 
               
               
                   
                 receiving device has 
               
               
                   
                 successfully received 
               
               
                   
                 information transmitted on 
               
               
                   
                 the write channel. 
               
               
                   
               
             
          
         
       
     
         [0039]      FIG. 3  is a timing diagram showing the control signaling for the same three write operations described above in connection with  FIG. 2 . A System Clock  306  may be used to synchronize communications between the sending and receiving devices. The System Clock  306  is shown with five clock cycles, with each clock cycle numbered sequentially. 
         [0040]    A write operation may be initiated on the address channel  106   a  by the sending device during the first clock cycle  301 . This operation may be achieved by transmitting the address A 1  for the first write operation on the 32-bit Address medium  308 . Concurrently, the sending device asserts the AValid, Address/Data, and Transfer Attribute signals  312 ,  313 ,  314 . The asserted AValid signal  312  indicates that valid information is being transmitted on the address channel  106   a , the asserted Address/Data signal  313  indicates that the information is an address A 1 , and the asserted Transfer Attribute signal  314  indicates that the payload for the address A 1  will be transmitted on the write channel  106   b . The sending device also deasserts the Read/Write signal  316  to request a write operation. The Payload Size  318  signal may be used to indicate the size of the payload, which in this case is 32-bytes. 
         [0041]    During the same first clock cycle  301 , the sending device uses the Write medium  320  to transmit the first 8-bytes of the first payload W 1 ( 1 ). The sending device also asserts the WValid signal  324  to indicate that valid information is being transmitted on the write channel  106   b.    
         [0042]    At the end of the first clock cycle  301 , the sending device checks for an asserted Address Transfer Ack signal  310  to confirm the successful delivery of the address A 1  over the address channel  106   a  to the receiving device. The sending device also checks for an asserted Write Transfer Ack signal  322  to confirm the successful delivery of the first 8-bytes of the first payload W 1 ( 1 ) over the write channel  106   b  to the receiving device. 
         [0043]    On the second clock cycle  302 , the sending device transmits the address A 2  for the second write operation on the 32-bit Address medium  308  before the first write operation completes. The sending device asserts the AValid signal  312  to indicate that valid information is being transmitted on the address channel  106   a . The sending device also asserts the Address/Data signal  313  to indicate that the information is an address A 2 . The Transfer Attribute  314  is deasserted to indicate that the payload for the address A 2  will be transmitted on the address channel  106   a . The sending device also deasserts the Read/Write signal  316  to request a write operation. The Payload Size  318  signal may be used to indicate the size of the payload, which in this case is 8-bytes. 
         [0044]    During the same second clock cycle  302 , the sending device uses the Write medium  320  to send the second 8-bytes of the first payload W 1 ( 2 ). The sending device also asserts the WValid signal  324  to indicate that valid information is being transmitted on the write channel  106   b.    
         [0045]    At the end of the second clock cycle  302 , the sending device checks for an asserted Address Transfer Ack signal  310  to confirm the successful delivery of the address A 2  over the address channel  106   a  to the receiving device. The sending device also checks for an asserted Write Transfer Ack signal  322  to confirm the successful delivery of the second 8-bytes of the first payload W 1 ( 2 ) over the write channel  106   b  to the receiving device. 
         [0046]    On the third clock cycle  303 , the sending device transmits the first 4-bytes of the second payload W 2 ( 1 ) on the 32-bit Address medium  308 . The sending device asserts the AValid signal  312  to indicate the valid information is being transmitted on the address channel  106   a  and deasserts the Address/Data signal  313  to indicate that the information is part of a payload. The state of the Transfer Attribute signal  314 , Read/Write signal  316 , and Payload Size  318  signal can be ignored during this clock cycle. In  FIG. 3 , the states for these signals remain unchanged, but could be set to any state. 
         [0047]    During the same third clock cycle  303 , the sending device uses the Write medium  320  to send the third 8-bytes of the first payload W 1 ( 3 ). The sending device also asserts the WValid signal  324  to indicate that valid information is being transmitted on the write channel  106   b.    
         [0048]    At the end of the third clock cycle  303 , the sending device checks for an asserted Address Transfer Ack signal  310  to confirm the successful delivery of the first 4-bytes of the second payload W 2 ( 1 ) over the address channel  106   a  to the receiving device. The sending device also checks for an asserted Write Transfer Ack signal  322  to confirm the successful delivery of the third 8-bytes of the first payload W 1 ( 3 ) over the write channel  106   b  to the receiving device. 
         [0049]    On the fourth clock cycle  304 , the sending device transmits the final 4-bytes of the second payload W 2 ( 2 ) on the 32-bit Address medium  308 . The sending device asserts the AValid signal  312  to indicate the valid information is being transmitted on the address channel  106   a  and deasserts the Address/Data signal  313  to indicate that the information is part of a payload. The state of the Transfer Attribute signal  314 , Read/Write signal  316 , and Payload Size  318  signal can be ignored during the payload tenure. 
         [0050]    During the same fourth clock cycle  304 , the sending device uses the Write medium  320  to send the final 8-bytes of the first payload W 1 ( 4 ). The sending device continues to assert the WValid signal  324  to indicate that valid information is being transmitted on the write channel  106   b.    
         [0051]    At the end of the fourth clock cycle  304 , the sending device checks for an asserted Address Transfer Ack signal  310  to confirm the successful delivery of the final 4-bytes of the second payload W 2 ( 2 ) over the address channel  106   a  to the receiving device. The sending device also checks for an asserted Write Transfer Ack signal  322  to confirm the successful delivery of the final 8-bytes of the first payload W 1 ( 4 ) over the write channel  106   h  to the receiving device. 
         [0052]    On the fifth clock cycle  305 , the sending device transmits the address A 3  for the third write operation on the 32-bit Address medium  308 . The sending device asserts the AValid signal  312  to indicate that valid information is being transmitted on the address channel  106   a . The sending device also asserts the Address/Data signal  313  to indicate that the information being transmitted on the address channel  106   a  is an address A 3 . The Transfer Attribute signal  314  is also asserted by the sending device to indicate that the payload for the address A 3  will be transmitted on the write channel  106   b . The Read/Write signal  316  remains deasserted to request a write operation. The Payload Size  318  signal may be used to indicate the size of the payload, which in this case is 8-bytes. 
         [0053]    During the same fifth clock cycle  305 , the sending device uses the Write medium  320  to send the payload W 3 . The sending device also asserts the WValid signal  324  to indicate that valid information is being transmitted on the write channel  106   b.    
         [0054]    At the end of the fifth clock cycle  305 , the sending device checks for an asserted Address Transfer Ack signal  310  to confirm the successful delivery of the address A 3  over the address channel  106   a  to the receiving device. The sending device also checks for an asserted Write Transfer Ack signal  322  to confirm the successful delivery of the third payload W 3  over the write channel  106   b  to the receiving device. 
         [0055]      FIG. 4  is a simplified block diagram illustrating a sending device  402  in communication with two receiving devices  404   a ,  404   b  through a bus interconnect  416  in a processing system  400 . In this example, the sending device  402  can write to both receiving devices  404   a ,  404   b  concurrently using the 32-bit address channel  406   a  as a medium for transmitting addresses and payloads to the bus interconnect  416 . The bus interconnect  416  can then use the 32-bit address channels  406   a   1 ,  406   a   2  to address the receiving devices  404   a ,  404   b  and the 64-bit write channels  406   b   1 ,  406   b   2  to transmit the payloads. In the case where the bus interconnect  416  needs to perform multiple write operations to one or both receiving devices  404   a ,  404   b , the address channels  406   a   1 ,  406   a   2  may also be used as media to transmit both addresses and payloads. 
         [0056]    An example will now be described with reference to  FIG. 5 .  FIG. 5  is an illustration showing the information flowing on the address and write channels. In this example, the bus interconnect  416  will provide point-to-point connections that allow each transmission from the sending device  402  to reach one of the receiving devices  404   a ,  404   b  in the same clock cycle. In practice, however, the bus interconnect  416  may be a clocked device with buffering (see  FIG. 4 ). 
         [0057]    Referring to  FIG. 5 , the sending device initiates a 32-byte write operation followed by an 8-byte write operation. On the first clock cycle  502 , the sending device initiates the 32-byte write operation by sending an address A 1  to the bus interconnect on the address channel  406   a  with the appropriate control signals. During the same clock cycle  502 , the sending device also sends the first 8-bytes of the first payload W 1 ( 1 ) to the bus interconnect on the write channel  406   b . The bus interconnect transmits the address A 1  to the first receiving device  404   a  on the first receiving device&#39;s address channel  406   a   1 , and transmits the first 8-bytes of the first payload W 1 ( 1 ) to the first receiving device  404   a  on the first receiving device&#39;s write channel  406   b   1 . 
         [0058]    On the second clock cycle  504 , the sending device initiates the next write operation by sending an address A 2  to the bus interconnect on the address channel  406   a  with the appropriate control signals. During the same clock cycle  504 , the sending device also sends the second 8-bytes of the first payload W 1 ( 2 ) to the bus interconnect on the write channel  406   b . The bus interconnect  416  transmits the address A 2  to the second receiving device  404   b  on the second receiving device&#39;s address channel  406   a   2 , and transmits the second 8-bytes of the first payload W 1 ( 2 ) to the first receiving device  404   a  on the first receiving device&#39;s write channel  406   b   1 . 
         [0059]    On the third and fourth clock cycles  506 ,  508 , the sending device sends the remainder of the first payload W 1 ( 3 ), W 1 ( 4 ) through the bus interconnect to the first receiving device  404   a  on the write channels  406   b ,  406   b   1 . During the same third and fourth clock cycles  506 ,  508 , the sending device transmits the second payload W 2 ( 1 ), W 2 ( 2 ) to the bus interconnect on the address channel  406   a . The second payload W 2 ( 1 ), W( 2 ), being only 8-bytes, may be transmitted in the third and fourth clock cycles  506 ,  508  by the bus interconnect to the second receiving device over half the byte lanes on the second receiving device&#39;s write channel  406   b   2 . Alternatively, the bus interconnect can transmit the entire payload during the fourth clock cycle  508  on the 64-bit write channel  406   b   2  for the second receiving device, as shown. 
         [0060]      FIG. 6  is a simplified block diagram illustrating an example of two devices in a processing system  600  communicating over a 4-channel bus. A separate and independent address channel is provided for each of the read and write channels. In this example, each channel is 32—bits wide, but may be any width in practice depending upon the particular application and overall design constraints. A write operation over the 4-channel bus may be performed in the same way described earlier in connection with the 3-channel bus. That is, the sending device  602  transmits address on the write address channel  606   a  and payloads on both the write address channel  606   a  and the write channel  606   b . The difference between the two bus architectures is the manner in which the read operation is performed. A read operation over the 4-channel bus is performed by sending to the receiving device  604  the address on a read address channel  606   d . In response, the receiving device  604  sends the payload to the sending device  602  on the read channel  606   c.    
         [0061]    An example will now be described with reference to  FIG. 7 . The bus protocol for the address and write channels  606   a ,  606   b ,  606   d  is listed below in Table 2. This bus protocol is being used to illustrate the inventive aspects of a processing system, with the understanding that such inventive aspects may be used with other bus protocols. Those skilled in the art will readily be able to vary and/or add signals to this protocol in the actual implementation of the bus architectures described herein. 
         [0000]    
       
         
               
               
               
             
               
             
               
               
               
             
               
             
               
               
               
             
               
             
               
               
               
             
           
               
                 TABLE 2 
               
               
                   
               
               
                 Signal 
                 Definition 
                 Driven By 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Write Address Channel 
               
             
          
           
               
                 Write Address 
                 32-bit medium to transmit 
                 Sending Device 
               
               
                   
                 write addresses and 
               
               
                   
                 payloads. 
               
               
                 Write Address/Data 
                 Indicates whether the 
                 Sending Device 
               
               
                   
                 information being 
               
               
                   
                 transmitted on the write 
               
               
                   
                 address channel is a write 
               
               
                   
                 address or a payload. 
               
               
                 Transfer Attribute 
                 Indicates whether the 
                 Sending Device 
               
               
                   
                 payload for the current 
               
               
                   
                 address will be transmitted 
               
               
                   
                 on the write address 
               
               
                   
                 channel, read address 
               
               
                   
                 channel or the write 
               
               
                   
                 channel. 
               
               
                 Write AValid 
                 Indicates whether valid 
                 Sending Device 
               
               
                   
                 information is being 
               
               
                   
                 transmitted on the write 
               
               
                   
                 address channel. 
               
               
                 Write Payload Size 
                 Indicates the size of the 
                 Sending Device 
               
               
                   
                 payload for the current 
               
               
                   
                 write address. 
               
               
                 Write Address Transfer 
                 Indicates whether the 
                 Receiving Device 
               
               
                 Ack 
                 receiving device has 
               
               
                   
                 successfully received 
               
               
                   
                 information transmitted on 
               
               
                   
                 the write address channel. 
               
             
          
           
               
                 Read Address Channel 
               
             
          
           
               
                 Read Address 
                 32-bit medium to transmit 
                 Sending Device 
               
               
                   
                 read addresses and 
               
               
                   
                 payloads. 
               
               
                 Read Address/Data 
                 Indicates whether the 
                 Sending Device 
               
               
                   
                 information being 
               
               
                   
                 transmitted on the read 
               
               
                   
                 address channel is a read 
               
               
                   
                 address or a payload. 
               
               
                 Read AValid 
                 Indicates whether valid 
               
               
                   
                 information is being 
               
               
                   
                 transmitted on the read 
               
               
                   
                 address channel. 
               
               
                 Read Payload Size 
                 Indicates the size of the 
                 Sending Device 
               
               
                   
                 payload for the current read 
               
               
                   
                 address. 
               
               
                 Read Address Transfer 
                 Indicates whether the 
                 Receiving Device 
               
               
                 Ack 
                 receiving device has 
               
               
                   
                 successfully received 
               
               
                   
                 information transmitted on 
               
               
                   
                 the read address channel. 
               
             
          
           
               
                 Write Channel 
               
             
          
           
               
                 Write 
                 32-bit medium to transmit 
                 Sending Device 
               
               
                   
                 payloads. 
               
               
                 WValid 
                 Indicates whether valid 
                 Sending Device 
               
               
                   
                 information is being 
               
               
                   
                 transmitted on the write 
               
               
                   
                 channel 
               
               
                 Write Transfer Ack 
                 Indicates whether the 
                 Receiving Device 
               
               
                   
                 receiving device has 
               
               
                   
                 successfully received 
               
               
                   
                 information transmitted on 
               
               
                   
                 the write channel. 
               
               
                   
               
             
          
         
       
     
         [0062]    The protocol for the Transfer Ack signal on the write address channel is shown below in Table 3. 
         [0000]    
       
         
               
               
             
           
               
                 TABLE 3 
               
               
                   
               
               
                 Transfer Attribute 
                 Definition 
               
               
                   
               
             
             
               
                 000 
                 Payload for the current address will be transmitted on 
               
               
                   
                 the write channel. 
               
               
                 001 
                 Payload for the current address will be transmitted on 
               
               
                   
                 the write address channel. 
               
               
                 010 
                 Payload for the current address will be transmitted on 
               
               
                   
                 the read address channel. 
               
               
                 011 
                 Reserved 
               
               
                   
               
             
          
         
       
     
         [0063]      FIG. 7  is a timing diagram showing the control signaling for a 16-byte write operation followed by a 12-byte write operation and then a 4-byte write operation. A System Clock  706  may be used to synchronize communications between the sending and receiving devices. The System Clock  706  is shown with four clock cycles, with each clock cycle numbered sequentially. 
         [0064]    A write operation may be initiated on the address channel  606   a  by the sending device during the first clock cycle  701 . This operation may be achieved by transmitting the address A 1  for the first write operation on the 32-bit Write Address medium  708 . During the same clock cycle  701 , the sending device asserts the Write AValid signal  712  to indicate that valid information is being transmitted on the write address channel  606   a . The sending device also asserts the write Address/Data signal  713  to indicate that the information is an address A 1 . The sending device also sets the Transfer Attribute signal  714  to “000” to indicate that the payload for the address A 1  will be transmitted on the write channel  606   b . The Payload Size  718  signal may be used to indicate the size of the payload, which in this case is 16-bytes. 
         [0065]    During the same first clock cycle  701 , the sending device uses the Write medium  720  to transmit the first 4—bytes of the first payload W 1 ( 1 ). The sending device also asserts the WValid signal  724  to indicate that valid information is being transmitted on the write channel  606   b.    
         [0066]    At the end of the first clock cycle  701 , the sending device checks for an asserted Write Address Transfer Ack signal  710  to confirm the successful delivery of the address A 1  over the address channel  606   a  to the receiving device. The sending device also checks for an asserted Write Transfer Ack signal  722  to confirm the successful delivery of the first 4-bytes of the first payload W 1 ( 1 ) over the write channel  606   b  to the receiving device. 
         [0067]    On the second clock cycle  702 , the sending device transmits the address A 2  for the second write operation on the 32-bit Address medium  708  before the first write operation completes. The sending device asserts the Write AValid signal  712  to indicate that valid information is being transmitted on the write address channel  606   a . The sending device also asserts the Address/Data signal  713  to indicate that the information is an address A 2 . The sending device sets the Transfer Attribute signal  711  to “010” to indicate that the payload for the address A 2  will be transmitted on the read address channel  606   d . The Payload Size  718  signal may be used to indicate the size of the payload, which in this case is 12-bytes. 
         [0068]    During the same second clock cycle  702 , the sending device uses the Write medium  720  to transmit the second 4-bytes of the first payload W 1 ( 2 ), and asserts the WValid signal  724  to indicate that valid information is being transmitted on the write channel  606   b . The sending device uses the Read Address medium  730  to send the first 4-bytes of the second payload W 2 ( 1 ), and asserts the Read AValid signal  728  to indicate that valid information is being transmitted on the read address channel  606   d . The sending device deasserts the Read Address/Data signal  729  to indicate that the information being transmitted on the read address channel  606   d  is payload data. 
         [0069]    At the end of the second clock cycle  702 , the sending device checks for an asserted Write Address Transfer Ack signal  710  to confirm the successful delivery of the address A 2  over the address channel  606   a  to the receiving device. The sending device also checks for asserted Write Transfer Ack and Read Address Transfer Ack signals  722 ,  726  to confirm the successful delivery of the payload data over the write and read address channels  606   b ,  606   d.    
         [0070]    On the third clock cycle  703 , the sending device asserts the Write AValid signal  712  to indicate that valid information is being transmitted on the write address channel  606   a . The sending device also asserts the Address/Data signal  713  to indicate that the information is an address A 3 . The sending device sets the Transfer Attribute signal  714  to “001” to indicate that the payload for the address A 3  will be transmitted on the write address channel  606   a . The Payload Size  718  signal may be used to indicate the size of the payload, which in this case is 4-bytes. 
         [0071]    During the same third clock cycle  703 , the sending device uses the Write medium  720  to transmit the third 4-bytes of the first payload W 43 ), and asserts the WValid signal  724  to indicate that valid information is being transmitted on the write channel  606   b . The sending device uses the Read Address medium  730  to send the second 4-bytes of the second payload W 2 ( 2 ), and asserts the Read AValid signal  728  to indicate that valid information is being transmitted on the read address channel  606   d . The sending device deasserts the Read Address/Data signal  729  to indicate that the information being transmitted on the read address channel  606   d  is payload data. 
         [0072]    At the end of the third clock cycle  703 , the sending device checks for an asserted Write Address Transfer Ack signal  710  to confirm the successful delivery of the address A 3  over the address channel  606   a  to the receiving device. The sending device also checks for asserted Write Transfer Ack and Read Address Transfer Ack signals  722 ,  726  to confirm the successful delivery of the payload data over the write and read address channels  606   b ,  606   d.    
         [0073]    On the fourth clock cycle  704 , the sending device uses the Write medium  720  to send the final 4-bytes of the first payload W 1 ( 4 ), and the Read Address medium  730  to send the final 4-bytes of the second payload W 2 ( 3 ). The sending device asserts the WValid and Read AValid signals  724 ,  728  to indicate that valid information is being transmitted on the write and read address channels  606   b ,  606   d . The sending device deasserts the Read Address/Data signal  729  to indicate that the information being transmitted on the read address channel  606   d  is payload data. 
         [0074]    The sending device uses Write address medium  708  to send the third payload W 3 , and asserts the Write AValid signal  712  to indicate that valid information is being sent on the write address channel  606   a . The sending device deasserts the Address/Data, signal  713  to indicate that the information transmitted on the write address channel  606   a  is payload data. The state of the Transfer Attribute signal  714  and Payload Size  718  signal may ignored. 
         [0075]      FIG. 8  is a simplified block diagram illustrating a sending device  802  in communication with three receiving devices  804   a - 804   c  through a bus interconnect  816  in a processing system  800 . In this example, the sending device  802  can write to all three receiving devices  804   a - 804   c  concurrently using the read and write address channels  806   d ,  806   a  as media for transmitting addresses and payloads. The bus interconnect  816  can then use the write address channels  806   a   1 ,  806   a   2 ,  806   a   3  to address the receiving devices  804   a ,  804   b ,  804   c  and the write channels  806   b   1 ,  806   b   2 ,  806   b   3  to transmit the payloads. In the case where the bus interconnect  816  needs to perform multiple write operations to one or more receiving devices  804   a ,  804   b ,  804   c , the read and write address channels  806   d   1 ,  806   d   2 ,  806   d   3 ,  806   a   1 ,  806   a   2 ,  806   a   1  may also be used as generic media to transmit both addresses and payloads. 
         [0076]    An example of will now be described with reference to  FIG. 9 .  FIG. 9  is an illustration showing the information flowing on the address and write channels. In this example, the bus interconnect  816  will provide point-to-point connections that allow each transmission from the sending device  802  to reach one of the receiving devices  804   a ,  804   b ,  804   c  in the same clock cycle. In practice, however, the bus interconnect  816  may be a clocked device with buffering (see  FIG. 8 ). 
         [0077]    Referring to  FIG. 9 , on the first clock cycle  902 , the sending device initiates the 16-byte write operation by sending an address A 1  to the bus interconnect on the address channel  806   a  with the appropriate control signals. During the same clock cycle  902 , the sending device also sends the first 4-bytes of the first payload W 1 ( 1 ) to the bus interconnect on the write channel  806   b . The bus interconnect transmits the address A 1  to the first receiving device  804   a  on the first receiving device&#39;s address channel  806   a   1 , and transmits the first 4-bytes of the first payload W 1 ( 1 ) to the first receiving device  804   a  on the first receiving device&#39;s write channel  806   b   1 . 
         [0078]    On the second clock cycle  904 , the sending device initiates the next write operation by sending an address A 2  to the bus interconnect on the address channel  806   a  with the appropriate control signals. During the same clock cycle  904 , the sending device also sends the second 4-bytes of the first payload W 1 ( 2 ) to the bus interconnect on the write channel  806   b  and the first 4-bytes of the second payload W 2 ( 1 ) to the bus interconnect on the read address channel  806   d . The bus interconnect  816  transmits the address A 2  to the second receiving device  804   b  on the second receiving device&#39;s address channel  806   a   2 , transmits the second 4-bytes of the first payload W 1 ( 2 ) to the first receiving device  804   a  on the first receiving device&#39;s write channel  806   b   1 , and transmits the first 4-bytes of the second payload W 2 ( 1 ) to the second receiving device  804   b  on the second receiving device&#39;s write channel  806   b   2 . 
         [0079]    On the third clock cycle  906 , the sending device initiates the next write operation by sending an address A 3  to the bus interconnect on the address channel  806   a  with the appropriate control signals. At the same time, the sending device also sends the third 4-bytes of the first payload W 1 ( 3 ) to the bus interconnect on the write channel  806   b , and the second 4-bytes of the second payload W 2 ( 2 ) to the bus interconnect on the read address channel  806   d . The bus interconnect  816  transmits the address A 3  to the third receiving device  804   c  on the third receiving device&#39;s address channel  806   a   3 , transmits the third 4-bytes of the first payload W 1 ( 3 ) to the first receiving device  804   a  on the first receiving device&#39;s write channel  806   b   1 , and transmits the second 4-bytes of the second payload W 2 ( 2 ) to the second receiving device  804   b  on the second receiving device&#39;s write channel  806   b   2 . 
         [0080]    On the fourth clock cycle  908 , the sending device sends the final 4-bytes of the first payload W 1 ( 4 ) to the bus interconnect on the write channel  806   b , the final 4-bytes of the second payload W 2 ( 3 ) to the bus interconnect on the read address channel  806   d , and the third payload W 3  to the bus interconnect on the write address channel  806   a . The bus interconnect  816  transmits the final 4-bytes of the first payload W 1 ( 4 ) to the first receiving device  804   a  on the first receiving device&#39;s write channel  806   b   1 , transmits the final 4-bytes of the second payload W 2 ( 3 ) to the second receiving device  804   b  on the second receiving device&#39;s write channel  806   b   2 , and transmits the third payload W 3  to the third receiving device  804   c  on the third receiving device&#39;s write channel  806   b   3 . 
         [0081]    The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing components, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. 
         [0082]    The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in the sending and/or receiving component, or elsewhere. In the alternative, the processor and the storage medium may reside as discrete components in the sending and/or receiving component, or elsewhere. 
         [0083]    The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.