Abstract:
An apparatus for quadrature tuner error correction includes an offset correction circuit adapted to receive a digital in-phase signal and a digital quadrature signal from a quadrature tuner. The offset correction circuit has an in-phase circuit comprising a summer adapted to receive the digital in-phase signal, subtract an in-phase offset estimate therefrom, and generate an offset corrected in-phase signal, and a feedback loop adapted to integrate the offset corrected in-phase signal, multiply the integrated offset corrected in-phase signal by a first adjustable constant, and generate the in-phase offset estimate. The offset correction circuit has a quadrature circuit comprising a summer adapted to receive the digital quadrature signal, substract a quadrature offset estimate therefrom, and generate an offset corrected quadrature signal, and a feedback loop adapted to integrate the offset corrected quadrature signal, multiply the integrated offset corrected quadrature signal by a second adjustable constant, and generate the quadrature offset estimate.

Description:
TECHNICAL FIELD OF THE INVENTION 
     This invention is related in general to the field of electrical and electronic circuits. More particularly, the invention is related to apparatus and a method for quadrature tuner error correction. 
     BACKGROUND OF THE INVENTION 
     A block diagram of an ideal quadrature tuner  10  and digitizer  12  is shown in FIG.  1 . An unmodulated input carrier signal  14  is represented by A cos (ω C t+θ). Unmodulated input carrier signal  14  has a peak amplitude A, radian frequency ω C , and an arbitrary phase of θ radians. Input carrier signal  14  is mixed by mixers  16  and  17  with two signals  18  and  19  generated by a local oscillator (LO)  20 . Signals  18  and  19  are represented by cos(ω LO t) and −sin(ω LO t), which both have a normalized amplitude of 1, radian frequency ω LO , and normalized phase of 0 radians. The resulting signals are: 
     
       
           A  cos(ω C   t +θ)cos(ω LO   t )=( A/ 2)cos[(ω C −ω LO ) t +θ]+( A /2)cos[(ω C +ω LO ) t+θ]   
       
     
     and 
     
       
           −A  cos(ω C   t +θ)sin(ω LO   t )=( A /2)sin[(ω C −ω LO ) t +θ]−( A /2)sin[(ω C +ω LO ) t+θ]   (1) 
       
     
     Ideal lowpass filters (LPFs)  24  and  25  receive these resultant signals and remove only the high frequency components, resulting in analog in-phase (I) and quadrature (Q) signals  26  and  27 : 
     
       
           I =( A /2)cos[(ω C −ω LO ) t+θ]   
       
     
     and 
     
       
           Q =( A /2)sin[(ω C −ω LO ) t+θ]   (2) 
       
     
     Analog in-phase and quadrature signals  26  and  27  are converted to digital form by analog-to-digital converters (ADC)  28  and  29  for further processing. 
     On the other hand, a real quadrature tuner produces offset, gain, and phase errors which reduce the accuracy of the resulting in-phase and quadrature signals. The worst case gain and phase errors of several commercially available tuner devices are in the ±0.5 dB and ±5.0° range, respectively. 
     Conventional attempts to correct these errors may use. analog trimming, adjustments, or calibration. These methods are undesirable due to high cost. Another conventional method uses analog-to-digital converters with wide bandwidths and high speed to digitize the in-phase and quadrature output signals. The requirement of high performance analog-to-digital converters adds substantially to cost and the complexity of the circuit. 
     SUMMARY OF THE INVENTION 
     Accordingly, there is a need for a circuit and method that efficiently correct quadrature tuner offset, gain, and phase errors. In accordance with the present invention, apparatus and a method of quadrature tuner error correction are provided which eliminate or substantially reduce the disadvantages associated with prior circuits or algorithms. 
     In one aspect of the invention, apparatus for quadrature tuner error correction includes an offset correction portion adapted to receive a digital in-phase signal and a digital quadrature signal from a quadrature tuner. The offset correction portion has an in-phase portion comprising a summer adapted to receive the digital in-phase signal, subtract an in-phase offset estimate therefrom, and generate an offset corrected in-phase signal, and a feedback loop adapted to integrate the offset corrected in-phase signal, multiply the integrated offset corrected in-phase signal by a first adjustable constant, and generate the in-phase offset estimate. The offset correction portion has a quadrature portion comprising a summer adapted to receive the digital quadrature signal, substract a quadrature offset estimate therefrom, and generate an offset corrected quadrature signal, and a feedback loop adapted to integrate the offset corrected quadrature signal, multiply the integrated offset corrected quadrature signal by a second adjustable constant, and generate the quadrature offset estimate. 
     In another aspect of the invention, a method of correcting errors in a quadrature tuner includes an offset correction process which receives a digital in-phase signal and a digital quadrature signal from the quadrature tuner. The offset correction process has an in-phase portion which includes the steps of receiving the digital in-phase signal, subtracting an in-phase offset estimate therefrom, and generating an offset corrected in-phase signal, and feeding back the offset corrected in-phase signal through a first feedback loop, the feedback loop integrating the offset corrected in-phase signal, multiplying the integrated offset corrected in-phase signal by a first adjustable constant, and generating the in-phase offset estimate. The offset correction process also has a quadrature portion with the steps of receiving the digital quadrature signal, subtracting a quadrature offset estimate therefrom, and generating an offset corrected quadrature signal, and feeding back the offset corrected quadrature signal through a feedback loop, the feedback loop integrating the offset corrected quadrature signal, multiplying the integrated offset corrected quadrature signal by a second adjustable constant, and generating the quadrature offset estimate. 
     In yet another aspect of the invention, apparatus for quadrature tuner error correction includes an offset correction portion adapted to receive a digital in-phase signal and a digital quadrature signal from a quadrature tuner and generating offset corrected in-phase and quadrature signals, a gain correction portion coupled to the offset correction portion adapted to receive the offset corrected in-phase and quadrature signals and generating offset and gain corrected in-phase and quadrature signals, and a phase correction portion coupled to the gain correction portion adapted to receive the gain corrected in-phase and quadrature signals and generating offset, gain and phase corrected in-phase and quadrature signals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a better understanding of the present invention, reference may be made to the accompanying drawings, in which: 
     FIG. 1 is a functional block diagram of an ideal quadrature tuner and digitizer; 
     FIG. 2 is a functional block diagram of an embodiment of an offset correction circuit and algorithm constructed according to an embodiment of the present invention; 
     FIG. 3 is a functional block diagram of an embodiment of a gain correction circuit and algorithm constructed according to an embodiment of the present invention; 
     FIG. 4 is a functional block diagram of an embodiment of a gain control multiplier constructed according to an embodiment of the present invention; and 
     FIG. 5 is a functional block diagram of an embodiment of a phase correction circuit and algorithm constructed according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The in-phase and quadrature offset errors produced by a real quadrature tuner may be represented by adding O I  and O Q , to the respective output signals. The offset errors are DC signals typically in the range of ±10 millivolts. The offsets are not necessarily matched, and may vary as a function of operating temperature. 
     The gain error may be represented by multiplying the respective in-phase and quadrature signals by constants G I  and G Q . Gain mismatch can be expressed in dB using the equation: 
     
       
         Gain mismatch (db)=20 log 10 ( G   I   /G   O )  (3) 
       
     
     Gain mismatch is typically in the range of ±1 dB, and may vary as a function of operating temperature. 
     A phase error of φ radians can be represented by adding half of its value to the phase of the in-phase output signal, and subtracting half of its value from the phase of the quadrature output signal. 
     Therefore, the equations which represent the in-phase and quadrature outputs with offset, gain and phase error sources are: 
     
       
           I=O   I   +G   I ( A /2)cos[(ω C −ω LO ) t +θ+φ/2] 
       
     
     
       
           Q=O   Q   +G   Q ( A /2)sin[(ω C −ω LO ) t +θ−φ/2]  (4) 
       
     
     Combining the gain and amplitude terms and normalizing results in: 
     
       
           I=O   I   +A   I  cos[(ω C −ω LO ) t +θ+φ/2] 
       
     
     
       
           Q=O   Q   +A   Q  sin[(ω C −ω LO ) t +θ−φ/2]  (5) 
       
     
     Input of these uncorrected signals with offset, gain and phase errors into a standard demodulator results in substantially degraded performance. 
     Offset Correction 
     A functional block diagram of an embodiment of the digital offset correction circuit and algorithm  40  according to the present invention is shown in FIG.  2 . The in-phase and quadrature signals may both be corrected for offset error with the circuit or algorithm shown in FIG. 2. A summer  42  receives the in-phase or quadrature signal from analog-to-digital converter  28  or  29  (FIG. 1) as input signal  41  and subtracts an offset estimate  44  from it. Offset estimate  44  is supplied by a multiplier  46 , which in effect multiplies an input  48  thereto by a constant 2 −N  Multiplier  46  is coupled to an integrator  50 , which receives its input from the output of summer  42 . 
     In operation, a near zero offset estimate  44  is first subtracted from the in-phase or quadrature signal input  42 , and the resultant output  52  is integrated and fed back through multiplier  46  to form the offset estimate  44 . Multiplier  46  maybe implemented by a shifter which shifts its input signal right N bits. This circuit and algorithm in essence implement a high pass filter with a cut-off frequency that can be made arbitrarily low by increasing N (and consequently the width of the integrator). 
     Offset correction circuit and algorithm of the present invention is adapted to function properly with no input signal or noise-only input. However, the circuit or algorithm may not function properly if an unmodulated carrier signal is applied to mixers  16  and  17  with frequency closely matching the frequency of local oscillator  20  (i.e. ω C ≈ω LO ). This condition can be avoided by slightly off-tuning local oscillator  20  from the expected range of input frequencies. 
     In an embodiment of the present invention, an offset correction value controller  45  such as a symmetric limiter as known in the art may be incorporated at the output of multiplier  46  to limit the range of offset correction values if needed. 
     In an embodiment of the present invention, offset correction value controller  45  may include a correction register, multiplexer, processor and other components (not shown) to allow processor control of the value of offset correction  44  during certain operating conditions, such as temperature variation. The offset correction value may be computed or determined in response to a control input such as a temperature measurement. 
     Gain Correction 
     A functional block diagram of an embodiment of a gain correction circuit and algorithm  60  according to the present invention is shown in FIG.  3 . Preferably, gain correction follows offset correction and uses, as input, the in-phase and quadrature output from offset correction circuit and algorithm  40  shown in FIG.  2 . The offset corrected in-phase and quadrature signals  61  and  62  are provided to multipliers  63  and  64 , respectively, to be multiplied by initial correction values (near 1). The resulting gain corrected output signals are each squared by a squaring network including squarers  66  and  67 , and a difference between the squared values is determined by a summer  68 . The difference result is then fed to an integrator  70  and multiplier  72  (shown implemented as a shifter). The output from multiplier  72  is provided as a gain correction signal to mixer  64  to be mixed with quadrature signal  62 . The output from multiplier  72  is also supplied to mixer  63  to be mixed with in-phase signal  61  after it is inverted, as in ( ) −1 , by an inverter  74 . 
     A feedback loop enable circuit  65  may be needed to disable the feedback loop when no signal or noise inputs are present. For example, feedback loop enable circuit may include a lowpass filter to detect the absence of signal or noise input or to compare the squarer output with a reference signal at the output of squarer  66 . Only when the detected power output of the squarer exceeds the predetermined reference value, is the feedback loop enabled. 
     Preferably, gain correction follows offset correction, since an uncorrected offset value in the in-phase or quadrature signals may erroneously contribute to the squaring power measurement calculations. It may be desirable to disable the gain correction feedback loop until the offset correction loops have settled and stabilized. 
     An embodiment of the gain offset algorithm may include a gain correction value controller  73  such as a symmetric limiter coupled to the output of shifter  72  to limit the range of gain correction values. Gain correction value controller  73  may also include processor controlled calibration to account for control input such as operating temperature date. 
     The embodiment of gain correction multipliers  63  and  64  may take advantage of the limited range of the gain control values. Assume that the maximum allowable corrected error is ±0.1 dB. Correction of an overall (I/Q) gain imbalance of ±1 dB with a maximum error of ±0.1 dB requires I and Q multipliers  63  and  64  each having a maximum gain range of ±0.5 dB and setting error of ±0.05 dB. Given a logarithmic gain control signal and multiplier, settings of −0.45 dB in 0.1 dB steps (10 total) meet the requirement. A maximum gain of +0.5 dB corresponds to a maximum linear correction value of 1.059254, and a minimum gain of −0.5 dB corresponds to a minimum linear correction value of 0.944061. 
     The maximum input gain control value corresponds to a right shift of −log 2 (0.059)=4.08, or just over 4 bits. The maximum value of K is then just under 1/16. Assuming 3 magnitude bits and 1 sign bit (16 total steps) are adequate for representing the control value, the possible gain selections are shown in Table A below: 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE A 
               
               
                   
               
               
                 Control 
                 Control 
                   
                   
                 Δ Gain, 
               
               
                 Bits 
                 Value 
                 Gain = 1 + (val/128) 
                 Gain (db) 
                 Prev. Value 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 0111 
                 +7 
                 1.054688 
                 0.4625 
                 N/A 
               
               
                 0110 
                 +6 
                 1.046875 
                 0.3979 
                 0.0646 
               
               
                 0101 
                 +5 
                 1.039063 
                 0.3328 
                 0.0651 
               
               
                 0100 
                 +4 
                 1.031250 
                 0.2673 
                 0.0655 
               
               
                 0011 
                 +3 
                 1.023438 
                 0.2012 
                 0.0661 
               
               
                 0010 
                 +2 
                 1.015625 
                 0.1347 
                 0.0665 
               
               
                 0001 
                 +1 
                 1.007813 
                 0.0676 
                 0.0671 
               
               
                 0000 
                 0 
                 1.000000 
                 0.0000 
                 0.0676 
               
               
                 1111 
                 −1 
                 0.992188 
                 −0.0681 
                 0.0681 
               
               
                 1110 
                 −2 
                 0.984375 
                 −0.1368 
                 0.0687 
               
               
                 1101 
                 −3 
                 0.976563 
                 −0.2060 
                 0.0692 
               
               
                 1100 
                 −4 
                 0.968750 
                 −0.2758 
                 0.0698 
               
               
                 1011 
                 −5 
                 0.960938 
                 −0.3461 
                 0.0703 
               
               
                 1010 
                 −6 
                 0.953125 
                 −0.4170 
                 0.0709 
               
               
                 1001 
                 −7 
                 0.945313 
                 −0.4885 
                 0.0715 
               
               
                 1000 
                 −8 
                 0.937500 
                 −0.5606 
                 0.0721 
               
               
                   
               
             
          
         
       
     
     The results show that the maximum gain setting of 0.4625 dB is less than the specified maximum of 0.5 dB. However, it is 0.5−0.4625=0.0375 dB from that level, which is within the ±0.05 dB error toleranice. The minimum gain setting of −0.5606 dB is just under the specified minimum of −0.5 dB. The worst case gain step due to resolution limits is 0.0721 dB. The worst case setting error due to resolution limitations is then ±0.721/2=±0.036 dB, which is within the specified limit of ±0.5 dB. 
     A functional block diagram of an embodiment of a circuit for efficiently implementing this linear range is shown in FIG.  4 . Multiplier  80  is used to implement multipliers  63  and  64  in FIG.  3  and includes a multiplier  82  receiving a gain, K, and the in-phase or quadrature signal from offset correction circuitry. The output from multiplier  82  is supplied to a summer  84 , which sums the in-phase or quadrature input and the output from multiplier  82 . 
     Multiplier  80  may have a 4-bit two&#39;s complement control value input. The output of multiplier  80  is shifted right 7 bits (1/128) from the LSB (least significant bit) of the input in-phase or quadrature signal. Further multiplier logic reductions can be realized through truncation and/or rounding prior to the output, since the 6 or 7 multiplier output LSB&#39;s are normally not utilized by output summer  84 . 
     The use of the multiplier  80  also allows the multiplicative inversion, ( ) −1 , of gain correction circuit shown in FIG. 3 to be replaced by an additive inversion (two&#39;s complement) function, which generally has less complexity. 
     Phase Correction 
     A complete phase correction loop requires phase error detection and phase error correction functions. Phase error detection is accomplished by multiplying the in-phase and quadrature signals. Following offset and gain correction, the equations for the in-phase and quadrature signals are: 
     
       
           I=A  cos[(ω C −ω LO ) t +θ+φ/2] 
       
     
     
       
           Q=A  sin[(ω C −ω LO ) t +θ−φ/2]  (6) 
       
     
     Multiplying the two signals together results in: 
     
       
           I·Q=A  cos[(ω C −ω LO ) t +θ+φ/2 ]·A  sin[(ω C −ω LO ) t +θ−φ/2] 
       
     
     
       
           I·Q =( A   2 /2)sin[2·(ω C −ω LO ) t +2θ]−( A   2 /2)sin(φ)  (7) 
       
     
     The first term has no DC component, and can be removed by a lowpass filter (or integrator), resulting in the phase error signal: 
     
       
         Filtered  I·Q =−( A   2 /2)sin(φ)  (8) 
       
     
     The remaining unknown value is the amplitude of the input signal. The filtered output of the in-phase or quadrature squarer used to determine signal and/or noise presence for the gain correction algorithm is approximately A 2 /2 when there is a sufficiently high input signal to noise ratio (SNR). Dividing the filtered I·Q signal by the filtered in-phase or quadrature squarer output results in a phase error detection signal that is approximately equal to −sin(φ). Greater accuracy may be achieved by using a power estimate value generated by a coherent demodulator utilizing the corrected signals. 
     For every corresponding pair of in-phase and quadrature samples, the cosine and sine terms differ only in the φ/2 term. The identical terms are represented by Θ to simplify the phase error correction equations. The equations for the offset and gain corrected in-phase and quadrature values are: 
     
       
           I=A  cos(Θ+φ/2) 
       
     
     
       
           Q=A  sin(Θ−φ/2)  (9) 
       
     
     Given the trigonometric identities: 
     
       
         cos(α+β)=cos(α)cos(β)−sin(α)sin(β) 
       
     
     
       
         sin(α−β)=sin(α)cos(β)−cos(α)sin(β)  (10) 
       
     
     Substituting Equations (10) into Equations (9) results in Equations (11): 
     
       
           I=A  cos(Θ)cos(φ/2)− A  sin(Θ)sin(φ/2) 
       
     
     
       
           Q=A  sin(Θ)cos(φ/2)− A  cos(Θ)sin(φ/2)  (11) 
       
     
     Solving Equations (11) for A cos Θ and A sin Θ results in: 
     
       
           A  cos(Θ)=[ I+A  sin(Θ)sin(φ/2)]/cos(φ/2) 
       
     
     
       
           A  sin(Θ)=[ Q+A  cos(Θ)sin(φ/2)]/cos(φ/2)  (12) 
       
     
     Substituting Equations (12) into Equations (11) results in: 
     
       
           I=A  cos(Θ)cos(φ/2)−[ Q+A  cos(Θ)sin(φ/2)]sin(φ/2)/cos(φ/2) 
       
     
     
       
           Q=A  sin(Θ)cos(φ/2)−[ I+A  sin(Θ)sin(φ/2)]sin(φ/2)/cos(φ/2)  (13) 
       
     
     Expanding Equations (13) and using the relationship tan (φ/2)=sin(φ/2)/cos(φ/2) results in: 
     
       
           I=A  cos(Θ)cos(φ/2)− Q  tan(φ/2)− A  cos(Θ)sin(φ/2)tan(φ/2) 
       
     
     
       
           Q=A  sin(Θ)cos(φ/2)− I  tan(φ/2)− A  sin(Θ)sin(φ/2)tan(φ/2)  (14) 
       
     
     Rearranging Equations (14) results in: 
     
       
           A  cos(Θ)cos(φ/2)− A  cos(Θ)sin(φ/2)tan(φ/2)= I+Q  tan(φ/2) 
       
     
     
       
           A  sin(Θ)cos(φ/2)− A  sin(Θ)sin(φ/2)tan(φ/2)= Q+I  tan(φ/2)  (15) 
       
     
     Isolating A cos Θ and A sin Θ in Equations (15) results in: 
     
       
           A  cos(Θ)=[ I+Q  tan(φ/2)]/[cos(φ/2)−sin(φ/2)tan(φ/2)] 
       
     
     
       
           A  sin(Θ)=[ Q+I  tan(φ/2)]/[cos(φ/2)−sin(φ/2)tan(φ/2)]  (16) 
       
     
     The left hand sides of Equations (17) are defined as the corrected in-phase and quadrature values I and Q: 
     
       
           I=A  cos(Θ)=[ I+Q  tan(φ/2)]/[cos(φ/2)−sin(φ/2)tan(φ/2)] 
       
     
     
       
           Q=A  sin(Θ)=[ Q+I  tan(φ/2)]/[cos(φ/2)−sin(φ/2)tan(φ/2)]  (17) 
       
     
     The denominators of both expressions in Equations (17) are identical, so the in-phase and quadrature gains are the same if neither are calculated. The maximum denominator value is 1 when φ=0°, and the minimum value is 0.997144 when φ is 5°, for a maximum signal power effect of 0.025 dB. The denominator value only needs to be calculated if extremely accurate carrier power measurements are needed. Removing the denominators results in the final correction equations: 
     
       
           I=A  cos(Θ)=[ I+Q  tan(φ/2)] 
       
     
     
       
           Q=A  sin(Θ)=[ Q+I  tan(φ/2)]  (18) 
       
     
     A functional block diagram of an embodiment of a phase correction circuit and algorithm  90  of the present invention is shown in FIG.  5 . Circuit and algorithm  90  include summers  92  and  93  receiving the in-phase and quadrature signals, respectively, which already have been corrected for offset and gain errors. Summers  92  and  93  are coupled to the inputs of a multiplier  96 , the output is coupled to an integrator  98 . Integrator  98  is coupled to a multiplier implemented by a shifter  100 , and the output is supplied to a circuit block  102  which divides the shifter output by −1 and multiplies it by the I 2  or Q 2  value from squarer  66  or  67  and passed through a lowpass filter from gain correction circuit  60  shown in FIG.  3 . The output from block  102  is an estimate of tan(φ/2), and is provided to both multipliers  104  and  105 , which also receives the quadrature or in-phase input signals, respectively. The output of multipliers  104  and  105  are coupled to summers  92  and  93 , respectively. 
     In operation, the in-phase and quadrature inputs are both multiplied by the estimate of tan(φ/2) at multipliers  104  and  105 , and the result is summed with the other input to form the corrected in-phase and quadrature values. The corrected outputs are multiplied together at multiplier  96  to detect the phase error, and the resulting signal is integrated and shifted. The shifter output is divided by minus 1 times the filtered I 2  or Q 2  output from the gain correction algorithm, resulting in the estimate of tan(φ/2). 
     Since the loop bandwidth is narrow, divider  102  may be operated at a lower sample rate than the signal paths, allowing a low complexity serial divider to be used in implementation. 
     The phase correction algorithm of the present invention may not function properly when no signal input is present. The presence of an input signal may be detected by a feedback loop enable circuit  97  shown coupled to the output of multiplier  96 , for example. The phase correction loop may be disabled until an input signal is detected. Feedback loop enable circuit  97  may also be used to disable the phase correction loop until the gain correction loop has stabilized and produces errors less than a predetermined threshold, for example. 
     Preferably, phase correction follows gain correction, since the amplitude values are assumed to be equal in derivation. 
     In implementation, it may be desirable to couple a phase correction value controller  101 , such as a symmetric limiter, at the output of shifter  100  to limit the range of phase correction values. Processor controlled calibration may be added to this circuit to compensate for temperature variation using an approach similar to those described above for offset and gain correction. 
     The implementation of the phase correction multipliers may take advantage of the limited range of the tan(φ/2) value. Assume that the maximum allowable corrected error is ±0.2°. Correction of a maximum phase range of ±5° and setting error of ±0.2° requires phase correction multipliers having a maximum gain of ±tan(2.5°) and setting error of ±tan(0.1°). Given a tangent-linear control signal and multiplier, settings of −tan(2.4° degrees) to ±tan(2.4° degrees) in 0.20 degree steps (25 total) meet the requirement. 
     A maximum phase error of +5° corresponds to a maximum linear correction value of tan(+2.5°)=+0.043661, and a minimum phase error of −5° corresponds to a minimum linear correction value of tan(−2.5°)=−0.043661. The maximum input control value corresponds to a right shift of −log 2 (0.043661)=4.52, or over 4 bits. The maximum value of tan(φ/2) is then less than 1/16. Assuming four magnitude bits and one sign bit (32 total steps) are adequate for representing the control value, some possible multiplication factors are shown in Table B below 
     
       
         
               
               
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
               
               
               
               
               
             
           
               
                 TABLE B 
               
               
                   
               
               
                 Control 
                 Control 
                 Factor = 
                 tan −1  (Factor), 
                 Δ Deg., 
               
               
                 Bits 
                 Value 
                 Value/256 
                 deg. 
                 Prev. tan −1   
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 01100 
                 +12 
                 +0.046875 
                 +2.6838 
                 N/A 
               
               
                 01011 
                 +11 
                 +0.042969 
                 +2.4604 
                 0.2234 
               
               
                 01010 
                 +10 
                 +0.039063 
                 +2.2370 
                 0.2234 
               
               
                 01001 
                 +9 
                 +0.035156 
                 +2.0135 
                 0.2235 
               
             
          
           
               
                 — 
                 — 
                 — 
                 — 
                 — 
               
             
          
           
               
                 00010 
                 +2 
                 +0.007813 
                 +0.4476 
                 N/A 
               
               
                 00001 
                 +1 
                 +0.003906 
                 +0.2238 
                 0.2238 
               
               
                 00000 
                 0 
                 0.000000 
                 0.0000 
                 0.2238 
               
               
                 11111 
                 −1 
                 −0.003906 
                 −0.2238 
                 0.2238 
               
               
                 11110 
                 −2 
                 −0.007813 
                 −0.4476 
                 0.2238 
               
             
          
           
               
                 — 
                 — 
                 — 
                 — 
                 — 
               
             
          
           
               
                 10111 
                 −9 
                 −0.035156 
                 −2.0135 
                 N/A 
               
               
                 10110 
                 −10 
                 −0.039063 
                 −2.2370 
                 0.2235 
               
               
                 10101 
                 −11 
                 −0.042969 
                 −2.4604 
                 0.2234 
               
               
                 10100 
                 −12 
                 −0.046875 
                 −2.6838 
                 0.2234 
               
               
                   
               
             
          
         
       
     
     The results show that the required range can be met with control settings of +12 to −12, well within the five-bit range of +15 to −16. The worst case phase step due to resolution limits is 0.2238°. The worst case setting error due to resolution limitations is then ±0.2238/2=±0.1119°, which is just over the specified limit of ±0.1°. 
     Phase correction multipliers  104  and  105  may have a five-bit two&#39;s complement control value inputs. The outputs of the multipliers are shifted right 8 bits (1/256) from the LSB of the input signal. Further multiplier logic reductions can be realized through truncation and/or rounding prior to the output, since several of the multiplier output LSBs may not be utilized by correction summers  92  and  93 . 
     Simulation of phase correction circuit and algorithm  90  showed that worst case theoretical performance may be achieved with a correction signal from multipliers  104  and  105  having higher resolution than the input signal. A signal-to-noise ratio of at least the minimum theoretical value of 43.9 dB is not achieved until a correction value quantization of 1/4 input LSB is reached. 
     Simulation also shows that tan(φ/2) must be quantized to at least rnd(tan*256)/256 to achieve a signal-to-noise ratio that is at least the minimum theoretical value of 43.9 dB. The maximum value of rnd(tan(φ/2)*256) is 12 for φ=5°, indicating that a five-bit two&#39;s complement value may be used to represent both positive and negative values of tan(φ/2). 
     It may be advantageous to note that the description set forth above is directed to the functional aspects of the various circuit blocks and the algorithm used to accomplish the error correction. Therefore, the present invention is not limited to any specific implementation of the functional blocks or the algorithms. 
     Although several embodiments of the present invention and its advantages have been described in detail, it should be understood that mutations, changes, substitutions, transformations, modifications, variations, and alterations can be made therein without departing from the teachings of the present invention, the spirit and scope of the invention being set forth by the appended claims.