Abstract:
A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This Application is a Continuation of prior application Ser. No. 12/114,589 filed on May 2, 2008 to Sailesh Chittipeddi, et al. entitled, “TRANSISTOR FABRICATION METHOD” which is a continuation of prior application Ser. No. 10/224,220 filed on Aug. 20, 2002, now abandoned, which is a Divisional of application Ser. No. 08/587,061 filed on Jan. 16, 1996, now U.S. Pat. No. 6,498,080 issued on Dec. 24, 2002. The above-listed Applications are commonly assigned with the present invention and is incorporated herein by reference as if reproduced herein in its entirety under Rule 1.53(b). 
     
    
     TECHNICAL FIELD 
       [0002]    This application is directed, in general, to semiconductor integrated circuits and to methods for their fabrication. 
       BACKGROUND 
       [0003]    Semiconductor integrated circuits are often fabricated by creating raised topographic features upon a substrate. Then a dopant species is introduced into the substrate with the raised topographic features serving to mask a portion of the substrate. For example, in the fabrication of semiconductor integrated circuits using field effect transistors (FETS), a gate stack (typically including a gate oxide with an overlying body of polysilicon) is formed upon a silicon substrate. Then a dopant species is introduced into a silicon substrate by diffusion or ion implantation to create the source and drain regions on both sides of the gate stack. As the dopant species is introduced, the gate stack serves as a self-aligned mask shielding the channel under the gate from the dopant species. 
         [0004]    Of course, during the above-described dopant introduction, the gate stack is subjected to the same environment as the to-be-formed source and drain regions are subjected. For example, if ion implantation techniques are employed to create the source and drain, the gate stack is exposed to ion implantation of the same dopant species as the to-be-formed source and drain regions. 
         [0005]    In the past, exposure of the gate stack to ion implantation species has not generally created a problem because the implanted species have been completely absorbed by the gate polysilicon. However, as integrated circuit geometries have continued to shrink, the thickness of gate stacks has also shrunk. If the thickness of the gate is too low relative to the implant dose energy, the implanted species may penetrate through the gate. 
         [0006]    Penetration of the implanted species through the gate is often termed “channeling.” If the energy of the implanted species is great enough and the polysilicon grains are oriented with the direction of the implant species, then the range of implanted species becomes greater than the thickness of the gate stack, and the implanted species may arrive at the gate oxide-silicon interface with enough energy to penetrate into or perhaps through the gate oxide. Thus, channeling depends upon the size and orientation of the polysilicon, as well as the energy of the implant species. A single large grain, if oriented parallel to the implant direction, can permit channeling. 
         [0007]    When channeling occurs, the silicon surface beneath the gate may be inverted, leading to transistor leakage and/or shifts in the threshold voltage. Another adverse affect of channeling is gate oxide degradation. In addition, channeling may cause flat band voltage shifts in polysilicon capacitors in the same integrated circuit. Heretofore, the channeling problem has not posed a serious obstacle to integrated circuit designers because gate stacks in previous generation integrated circuits have been thick enough to prevent channeling. 
       SUMMARY 
       [0008]    These problems are alleviated by the present invention which illustratively includes: forming a dielectric layer upon a substrate; forming a conductive layer upon the dielectric layer; forming a material layer overlying the conductive layer; forming a patterned resist upon the material layer; at least partially etching the material layer to form a raised feature; removing the resist; using the raised feature as a mask, anisotropically etching the conductive layer and the dielectric layer, thereby forming a gate; forming a source and drain region; and removing the mask. 
     
    
     
       BRIEF DESCRIPTION 
         [0009]    Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0010]      FIGS. 1-20  are cross-sectional views presenting illustrative embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0011]    In  FIG. 1 , reference numeral  11  denotes a substrate which may, typically, be silicon, epitaxial silicon, polysilicon, amorphous silicon, or doped silicon. In general, the term substrate refers to a body having a surface upon which other materials may be formed. 
         [0012]    Reference numeral  13  denotes an oxide layer which may typically have a thickness between 30 Å and 300 Å. 
         [0013]    Reference numeral  15  denotes a polysilicon layer which may or may not be doped. The thickness of polysilicon layer  15  is typically desirably between 200 Å and 5000 Å. 
         [0014]    Reference numeral  17  denotes a doped silicon dioxide layer. The thickness of layer  17  is typically desirably between 100 Å and 4000 Å. 
         [0015]    Desirably, layer  17  may be formed as a single layer or sometimes as a bilayer. For example, layer  17  may be formed from BPSG having approximately 4% boron and 4% phosphorous by weight. Alternatively, layer  17  may be formed from BPSG, having approximately 1% boron and 5% phosphorus. Furthermore, layer  17  may; be formed from PSG having a doping of approximately 2% or greater phosphorous. Other suitable materials for layer  17  are BPSG, plasma enhanced doped or undoped oxide, spin-on glass, silicon nitride (LPCVD or plasma enhanced CVD), or silicon oxynitride. Generally, layer  17  may be a doped silicon dioxide formed from a variety of precursors such as TEOS, silane, DADBS, etc. 
         [0016]    Layer  17  may be formed as a bilayer, as mentioned above. For example, layer  17  may be one of the forms of doped silicon oxide mentioned above formed over an undoped silicon oxide. Alternatively, layer  17  may be a single silicon oxide layer whose doping gradually increases from bottom to top. Layer  17  may also be a layer of silicon nitride with an underlying layer of silicon oxide which serves as an etch stop during subsequent etching steps. 
         [0017]    Layer  21  is a patterned photoresist layer. 
         [0018]    Turning to  FIG. 2 , a gate stack is defined, preferably by utilizing patterned photoresist  21  to either partially or completely etch through layer  17 . If layer  17  is a bilayer, typically, only the upper layer is etched while photoresist  21  is in place. If layer  17  is a single layer, it may be etched completely. 
         [0019]    In any case, after layer  17  has been subjected to the etch process for an appropriate period of time, resist  21  may be removed and the portion  117  of layer  17  beneath resist  21  may be used as a mask for subsequent etching which ultimately defines gate  23  shown in  FIG. 3 . Alternatively, resist  21  may be permitted to remain in place during the entire etching process. (Removal of resist  21  often provides superior linewidth control.) 
         [0020]    In  FIG. 3 , after gate  23  is defined, implantation species  25  is directed at gate  23  and substrate  11 , forming shallow junctions  27  and  29 . (Definition of gate  23  is usually accomplished by dry etching of layers  15  and  17  followed by wet etching of layer  13 .) Layer  17  helps to prevent channeling through gate stack  23 . 
         [0021]    Turning to  FIG. 4 , spacers  31  and  33  are formed, preferably, from undoped silicon dioxide by depositing and then anisotropically etching a layer of silicon dioxide. Spacers  31  and  33  abut gate stack  23 . Implantation species  35  is directed at gate stack  23  and substrate  11 , forming deep junctions  31  and  33 . 
         [0022]    Turning to  FIG. 5 , annealing steps, understood by those skilled in the art, are performed to drive in the combined junctions which, for convenience, are now designated by reference numerals  37  and  39 . Next, layer  17  is removed by etching processes with high selectivity to silicon dioxide. 
         [0023]    Wet etching formulas based upon HF tend to attack doped glass more quickly than undoped glass. However, such processes nevertheless do etch undoped glass and may cause undesirable reduction of the bird&#39;s beak, leading to transistor leakage. 
         [0024]    Layer  17  may also be removed utilizing NH 4 OH/H 2 O 2 . The use of NH 4 OH/H 2 O 2  is termed an ammonium peroxide (AP) clean. The preferred formula is eight parts H 2 O, two parts H 2 O 2  (30% concentrated), and one part concentrated NH 4 OH at approximately 80° C. Dry etch recipes may also be employed to remove layer  17 . P-glass may be removed by unbuffered HF or NH 4 OH/H 2 O 2 . 
         [0025]    If silicon nitride is used as layer  17 , it can be removed in hot phosphoric acid or in plasma using chemistries selective to oxide. In such an event a protective oxide layer may be previously formed on top of layer  15  to protect it from an attack by the plasma. Alternately, plasmaless dry etching using gas phase fluorides such as chlorine trifluoride, bromine trifluoride, iodide pentafluoride and xenon difluoride can be used. 
         [0026]    If silicide is not desired upon gate stack  23  or over junctions  37  and  39 , conventional processing may begin at this point. For example, a dielectric may be blanket deposited, windows opened to expose junctions  37  and  39 , and first level metallization formed. 
         [0027]    Layer  17  has prevented channeling through the gate which consists of layers  13 , and  15 . Furthermore, layer  17  has been removed without risk of damage to the gate, the substrate, or the field oxide. 
         [0028]    If silicide is desired, either upon gate stack  23  or over junctions  37  and  39 , a variety of processing options are available. The next few paragraphs will explain how silicide may be formed upon the gate  23  and junctions  37  and  39 . 
         [0029]    Turning to  FIG. 6 , layer  41  of refractory metal is blanket deposited. 
         [0030]      FIG. 7  illustrates that silicide regions  43 ,  45  and  47  have been formed after heat treatments known to those skilled in the art. No silicide forms upon oxide spacers  31  and  33 . Unreacted refractory metal remaining upon spacers  33  and  31  may be removed by methods known to those skilled in the art. 
         [0031]    Alternatively, if it is desired to form a silicide over junctions  37  and  39  without forming a silicide over gate stack  23 , a slightly different process may be employed. Starting from  FIG. 3 , a drive in step is performed to create regions  37  and  39  shown in  FIG. 8 . However, layer  17  is not removed. After regions  37  and  39  are formed, layer  49  of refractory metal, for example, titanium or cobalt, is deposited. 
         [0032]    After appropriate heat treatment, silicide regions  51  and  55  in  FIG. 9  are formed over junctions  37  and  39 . No silicide is formed upon gate stack  23 , because refractory metal  49  does not react to form a silicide with layer  17 . Unreacted refractory metal is removed by methods known to those skilled in the art. Subsequently, layer  17  can be removed to lower the stack height. 
         [0033]    Should it be desired to form a silicided gate without silicided source or drain, the structure of  FIG. 10  (which is similar to  FIG. 3 ) is created by the processes described above in the creation of  FIGS. 1 ,  2  and  3 . In  FIG. 10 , oxide layer  17  is positioned above conductor  15  and gate oxide  13 . Source and drain regions are denoted by reference numerals  27  and  29 , respectively. Spacers  200  are formed. 
         [0034]    Next, turning to  FIG. 11 , the structure of  FIG. 10  is subjected to an oxidizing ambient and thermal oxide  57  is grown upon substrate  11 , covering source and drain regions  27  and  29 . In  FIG. 12 , oxide  17  is removed by techniques described above. 
         [0035]    Because oxide  17  is doped, it may be singly removed without a risk of damaging thermal oxide  57 . 
         [0036]    Turning to  FIG. 13 , refractory metal layer  59  is deposited on top of conductor  15  and thermal oxide  57 . In  FIG. 14 , the structure has been exposed to a furnace treatment or a rapid thermal anneal process, thereby causing silicidation of polysilicon  15  by refractory metal  59 . Silicidation cannot occur over source and drain region  27 ,  29  because of the presence of oxide  57 . Next, the unsilicided refractory metal is removed, leaving only silicide  16  on top of conductor  15 . 
         [0037]    Should a silicided gate be desired with silicided source or drains, the procedure initially depicted in  FIG. 15  may also be followed. This procedure permits the formation of a silicided gate having, for example, titanium silicide and source/drain regions having a different type of silicide, e.g., cobalt silicide. In  FIG. 15 , reference numeral  11  denotes a silicon substrate covered by an oxide layer  13  having a typical thickness of 150 Å, a polysilicon layer  15  having a typical thickness of 2000 Å, and a silicide layer  73  having a typical thickness of 1000 Å. Silicide layer  73  is formed by chemical vapor deposition or sputtering. Alternatively, a refractory metal may be deposited and reacted to form a silicide. Doped silicon dioxide layer  17  is deposited upon silicide layer  73 . The oxide helps to prevent blistering or lifting of silicide  73  in subsequent processing. 
         [0038]    Turning to  FIG. 16 , gate  77  is formed utilizing the technique described above. 
         [0039]    The presence of layer  17  upon gate stack  77  serves to protect the silicide from ion implantation. If a spacer  200  is formed, it will protect the silicide in further processing, e.g., HF cleans where the silicide is titanium-silicide. 
         [0040]    In  FIG. 17 , blanket layer  100  of refractory metal silicide, which may be a different refractory metal than that utilized in silicide  17 , is deposited. Refractory metal  100  is reacted by either rapid thermal annealing or furnace heating to form silicide  101  depicted in  FIG. 18 . Next, oxide  17  is removed. Subsequent processing may include the blanket deposition of a dielectric in the creation of contact openings to the silicided source and drains. 
         [0041]    The present invention may also be employed to form a transistor without a silicided source or drain region. In  FIG. 19 , a gate having oxide  13 , polysilicon conductor  15 , and silicon oxide masking layer  17  is formed by the processes described previously. Spacers  200  are formed by the blanket deposition of a dielectric and subsequent anisotropic etching of the dielectric. Ion implantation with dopant species  79  is performed to form gates  81  and  83 . The presence of layer  17  serves to protect the gate comprised of polysilicon  15  and  13  and the underlying portion of substrate  11  from channeling. Subsequently, layer  17  is removed by the processes described above, leaving a gate comprised of polysilicon  15  which may, for example, have a thickness of 2000 Å, and oxide  13  which may, for example, have a thickness of 90 Å.