Abstract:
A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.

Description:
FIELD OF THE INVENTION 
     The present disclosure relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present disclosure relates to a method using carbon-containing spacers for critical dimension (CD) reduction. 
     BACKGROUND OF THE INVENTION 
     Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETS). ICs often include flash memory cells. 
     Generally, a transistor is covered by a high temperature oxide (HTO) and an interlevel dielectric to insulate it from subsequently formed metal layers. An aperture or hole is etched through the interlevel dielectric and the high temperature oxide. The hole is filled with a conductive material to provide connections to the transistor, to conductors, or other circuit structures. For example, a contact can extend from the bit line through the interlevel dielectric to the drain of the transistor. In another example, a contact or conductive via can extend through the interlevel dielectric to connect to the gate stack. 
     As transistors disposed on integrated circuits (ICs) become smaller (e.g., transistors with gate lengths approaching 50 nm), CMOS fabrication processes must scale the dimensions of the transistors. That is, there must be proportional operational characteristics of structural elements in the ultra-small dimensions of a sophisticated transistor. 
     One problem associated with CMOS scaling involves forming of smaller and smaller apertures or spaces used in a variety of ways during the IC fabrication process. One way to shrink the critical dimension of “space” features, such as holes and trenches, is with the formation of spacers. However, the high temperature deposition process involved in conventional spacer formation requires additional etch and deposition steps. 
     In a conventional process, patterned photoresist is located above a spacer template of, for example, SiO 2  that is above a polysilicon substrate. The spacer template is etched, the photoresist is removed, and spacer film is deposited. The spacer structures are formed from the spacer film and serve to shrink the aperture size associated with the spacer template. The substrate is etched using the spacer structures in the patterning. The spacers and spacer template are removed after the trench in the substrate is formed. 
     There is a need for a simplified spacer process for reducing critical dimensions. Further, there is a need to deposit carbon and form spacers directly on the photoresist pattern. Yet further, there is a need to reduce critical dimensions in integrated circuit fabrication using low temperature amorphous carbon spacers. 
     SUMMARY OF THE INVENTION 
     An exemplary embodiment relates to a method of using carbon spacers for critical dimension reduction. The method can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch. 
     Another exemplary embodiment relates to a method of reducing critical dimensions of holes or trenches. The method can include patterning photoresist above a substrate, depositing low temperature film including carbon above the patterned photoresist, etching the film to form spacers, etching the substrate or a layer above the substrate using the spacers and patterned photoresist as a mask, and removing the patterned photoresist and the spacers. 
     Another exemplary embodiment relates to a method of forming spacers directly on patterned photoresist to reduce critical dimensions in integrated circuit fabrications. The method can include depositing amorphous carbon material on patterned photoresist over a substrate, etching the deposited amorphous carbon spacer material to form carbon spacers, etching an aperture in the substrate using the carbon spacers and patterned photoresist as a mask, and removing the mask. 
     Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The exemplary embodiments of the disclosure will hereafter be described with reference to the accompanying drawings, wherein like numerals denote like elements, and: 
         FIG. 1  is a flow diagram depicting an exemplary process for forming reduced width trenches in accordance with an exemplary embodiment; 
         FIG. 2  is a schematic cross-sectional view representation of the portion of an integrated circuit, showing a stack application step in accordance with an exemplary embodiment; 
         FIG. 3  is a schematic cross-sectional view representation of the portion of the integrated circuit of  FIG. 2 , showing a photoresist patterning step; 
         FIG. 4  is a schematic cross-sectional view representation of the portion of the integrated circuit of  FIG. 2 , showing a spacer film material layer deposition step; 
         FIG. 5  is a schematic cross-sectional view representation of the portion of the integrated circuit of  FIG. 2 , showing a spacer formation step; and 
         FIG. 6  is a schematic cross-sectional view representation of the portion of the integrated circuit of  FIG. 2 , showing a trench formation step. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       FIG. 1  illustrates a flow diagram  10  depicting exemplary steps and a method of forming reduced width trenches. Flow diagram  10  illustrates by way of example, some steps that may be performed. Additional steps, fewer steps, or combinations of steps may be utilized in various different embodiments. 
     In an exemplary embodiment, in a step  15 , a photoresist layer is applied above a substrate. A variety of different techniques may be used to apply the photoresist layer above the substrate layer, such as spin coating. One photoresist application step is described below with reference to  FIG. 2 . In a step  25 , the photoresist layer is patterned to form apertures. Any of a variety of different patterning steps may be used to form the apertures in the photoresist layer, such as UV exposure and aqueous alkaline development. One photoresist patterning step is described below with reference to  FIG. 3 . 
     In a step  35 , an amorphous carbon layer is applied above the photoresist layer. Any of a variety of different application techniques may be used to form the amorphous carbon layer above the photoresist layer, such as chemical vapor deposition. The amorphous carbon layer can be deposited at temperatures below the flow temperature of the photoresist pattern, or at temperatures that do not alter the photoresist pattern. One amorphous carbon layer application step is described below with reference to  FIG. 4 . 
     In a step  45 , the amorphous carbon layer is etched to leave spacers in the apertures of the pattern photoresist layer. The amorphous carbon layer can be etched using a variety of different techniques, such as Reactive Ion Etching (RIE). One spacer formation step is described below with reference to  FIG. 5 . 
     In a step  55 , the substrate is etched using the pattern photoresist layer and spacers as a mask. The spacers help to provide a smaller dimension to the etched trench in the substrate. Any of a variety of techniques may be used, such as Reactive Ion Etching (RIE). One substrate etching step is described below with reference to  FIG. 6 . In a step  65 , the photoresist layer and spacers are removed. In a step  75 , the substrate is further processed. The trench can be used as an isolation trench, as a contact hole or via, or a dielectric trench to be filled with a conductor. 
     Referring to  FIG. 2 , a portion  100  of an integrated circuit includes a substrate  110  and a photoresist layer  120 . Photoresist layer  120  can be applied above substrate  110  using any of a variety of different techniques. In an exemplary embodiment, photoresist layer  120  has a thickness of 500 to 10,000 Angstroms. Substrate  110  can be a silicon-containing material or any of a variety of suitable materials. 
       FIG. 3  illustrates portion  100  after a patterning step in which apertures  130  are formed by the patterning of photoresist layer  120 . In an exemplary embodiment, apertures  130  have critical dimensions of 200 nm. Alternatively, apertures  130  can have a wide variety of different widths. Photoresist layer  120  can be patterned using a variety of different techniques, including the use of reticles or masks or direct writing. 
       FIG. 4  illustrates portion  100  after a spacer material film has been applied over photoresist layer  120  and substrate  110 . Spacer material layer  140  can include a low temperature spacer material including a carbon material. Alternatively, spacer material layer  140  can include a crystalline (diamond-like) composition. Any of a variety of deposition processes may be used to apply spacer material layer  140  over a photoresist layer  120  and substrate  110 . By way of example, chemical vapor deposition or physical vapor deposition may be utilized in applying spacer material layer  140 . 
       FIG. 5  illustrates portion  100  after a spacer formation process. In an exemplary embodiment, the spacer formation process includes an etching of spacer material layer  140  described with reference to  FIG. 4 . Spacers  150  are formed in apertures  130  formed during the patterning of photoresist layer  120  described with reference to  FIG. 3  and filled with spacer material layer  140  described with reference to  FIG. 4 . 
     Spacers  150  can be formed by using a variety of different techniques. For example, CVD deposition of a carbon film from a hydrocarbon source gas followed by reactive ion etching (RIE) with an oxidizing plasma can be used. In an exemplary embodiment, spacers  150  have a rounded shape. Alternatively, spacers  150  can have a rectangular or any other shape. Spacers  150  can have a width at the point of contact with substrate  110  of, for example, 50 nm or more. Accordingly, spacers  150  can reduce the exposed portion of substrate  110  to 100 nm or less. The width of spacers  150  are determined by the resist pattern shape, the CVD deposition conditions and the spacer etch process. After substrate etching, spacers  150  and photoresist layer  120  are removed by an oxidizing plasma or other chemical processes that do not damage the substrate. 
       FIG. 6  illustrates portion  100  after etching of substrate  110  is performed using spacers  150  and photoresist layer  120  as a mask. Etching of substrate  110  can form trenches  180 . Advantageously, trenches  180  have a critical dimension (i.e., width) of 100 nm or less. Once trenches  180  are formed, spacers  150  and photoresist layer  120  can be removed using, for example, an oxidizing etch. Advantageously, an oxidizing etch does not damage substrate  110 . 
     The process described with reference to the FIGURES results in a trench  180  in substrate  110  having a reduced width. Further, the process described uses carbon spacers  150  and helps to simplify the process of reducing critical dimensions. For example, conventional processes typically deposit spacer film, pattern photoresist on the spacer film, etch the spacer template, remove the photoresist, deposit spacer file, etch the spacer, etch the substrate, and remove the template film and spacer. In contrast, the process described with reference to the FIGURES includes patterning photoresist on the substrate, deposited a spacer film, etching the spacer, etching the substrate, and removing the photoresist and spacer. Advantageously, using a carbon spacer allows the spacer to be formed directly on the photoresist. Thus, some of the benefits of such a process include a reduced critical dimension, a simplified process, less expensive process equipment, reduced process time, reduced thermal cycling, lower defect levels, more simple re-work, etc. 
     While the exemplary embodiments illustrated in the FIGURES and described above are presently preferred, it should be understood that these embodiments are offered by way of example only. Other embodiments may include, for example, formation of gates or other integrated circuit features. The invention is not limited to a particular embodiment, but extends to various modifications, combinations, and permutations that nevertheless fall within the scope and spirit of the appended claims.