Abstract:
A current-mode buck converter is disclosed, wherein the current-mode buck converter operates in a pulse width modulation (PWM) mode or a pulse frequency modulation (PFM) mode. When the current-mode buck converter enters into the PFM mode, the voltage level of the parking voltage is maintained at the voltage level of compensation voltage, so as to decrease switch loss of the current-mode buck converter operating between PWM mode and PFM mode, and stabilize the output voltage of the current-mode buck converter.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The instant disclosure relates to a current-mode buck converter; in particular, to current-mode buck converter smoothly switched between a pulse width modulation mode and a pulse frequency modulation mode. 
         [0003]    2. Description of Related Art 
         [0004]    The electronic device usually comprises different components, and operating voltages of each component are different. Therefore, the electronic device is able to achieve regulation of the voltage level through a DC-to-DC voltage conversion circuit, and make the voltage be stabilized at a preset voltage value. According to different power requirements, it may be extended to many different types of DC-DC voltage conversion circuit, e.g. Buck/Step Down Converter and Boost/Step Up Converter. Furthermore, buck/step down converter may make the DC voltage of the input terminal decrease to a preset voltage level, and boost/step up converter may elevate DC voltage of the input terminal. There are many case of buck/step down converter or boost/step up converter has already evolved for adapting different architecture or meeting different demands as evolution of the circuit technology. 
         [0005]    For example, referring to  FIG. 1 ,  FIG. 1  shows circuit schematic view of the current-mode buck converter according to prior art. The current-mode buck converter comprises an oscillator  110 , an input terminal IT′, an output terminal OT′, a feedback module  160 , a switch module  150 , a current detecting circuit  130 , a slope compensating circuit  140 , a detection resistor RU, an error amplifier E 1 ′ a modulation compensating circuit  170 , a first comparator COP 1 ′, a modulation control circuit  120 , a zero-crossing detecting circuit ZT′, a current source ISET and a resistor RS. The modulation compensating circuit  170  comprises a compensation switch S 1 ′, a compensation resistor ROP′ and a compensation capacitor COP′. The feedback module  160  comprises a first resistor R 1 ′ and a second resistor R 2 ′. The switch module  150  comprises a buffer amplifier  152 , an up-bridge switch transistor MP′ and a down-bridge switch transistor MN′, wherein the up-bridge switch transistor MP′ is a P type metal-oxide semiconductor transistor and the down-bridge switch transistor MN′ is an N type metal-oxide semiconductor transistor. 
         [0006]    In prior art, the current-mode buck converter  100  receives an input voltage VIN′ via an input terminal IT′, and outputs an output voltage VOUT′ via an output terminal OT′. The feedback module  160  generates a feedback signal VFB′ according to the output voltage VOUT′. The switch module  150  determines an electrical connection of the input terminal IT′, a ground voltage GND′ and the output terminal OT′ according to a next-stage switch signal SWB′. The current detecting circuit  130  amplifies an input current ISNP′ received so as to generate an image current ISP′. The slope compensating circuit  140  receives a pre-stage switch signal SW′ and operates correspondingly according to the pre-stage switch signal SW′, and then generates a slope compensating current ISC′ accordingly. The current-mode buck converter  100  gather the image current ISP′ and the slope compensating current ISC′ via an adder AD′ and then it flows into one terminal of the detection resistor RU so as to generate a detection voltage VC′. The detection voltage VC′ is electrically connected to an input terminal of the first comparator COP 1 ′. The error amplifier E 1 ′ is used for amplifying a difference of the feedback signal VFB′ and the first reference voltage VREF 1 ′ so as to generate a difference voltage ΔV′. The modulation compensating circuit  170  compensates frequency response of the current-mode buck converter  100  according to the difference voltage ΔV′, and accordingly generates a compensation voltage EAO′, wherein one terminal of the compensation switch S 1 ′ of the modulation compensating circuit  170  is switched and connected to one of the PWM terminal T 1 ′ and the PFM terminal T 2 ′ according to a mode switch signal PF′. The first comparator COP 1 ′ receives the detection voltage VC′ and the compensation voltage EAO′ and compares the detection voltage VC′ with the compensation voltage EAO′, so as to the PWM signal PS′. The modulation control circuit  120  is used for generating the pre-stage switch signal SW′ according to the PWM signal PS′ and the oscillation signal VOSC′, wherein the oscillation signal VOSC′ is generated from the oscillator  110 . The zero-crossing detecting circuit ZT′ is used for detecting a source current ISNN′ of the down-bridge switch transistor MN′, and transmits the mode switch signal PF′ to the modulation control circuit  120 , the compensation switch S 1 ′, the current detecting circuit  130  and the slope compensating circuit  140  according to a detection result. 
         [0007]    However, when the current-mode buck converter  100  is changed from the pulse width modulation (PWM) mode to the pulse frequency modulation (PFM) mode, one terminal of the compensation switch S 1 ′ is switched and connected to the PFM terminal T 2 ′ from the PWM terminal T 1 ′ so as to receive a constant voltage FV. Because, a fixed current is generated from the current source ISET, a constant voltage FV is generated at the PFM terminal T 2 ′ when the fixed current flows through a fixed resistor RS, wherein the constant voltage FV does not carry any information about the detection voltage VC′ and the compensation voltage EAO′. Accordingly, when the current-mode buck converter  100  is switched between the PFM mode and the PWM mode, the output voltage VOUT′ will be not stable or be oscillated between the PFM mode and the PWM mode. 
       SUMMARY OF THE INVENTION 
       [0008]    The instant disclosure provides a current-mode buck converter. The current-mode buck converter comprises an oscillator, an input terminal, an output terminal, a feedback module, a switch module, a current detecting circuit, a slope compensating circuit, a detection resistor, an error amplifier, a modulation compensating circuit, a first comparator, a second comparator, a modulation control circuit, a zero-crossing detecting circuit and a buffer. The modulation compensating circuit comprises a compensation switch, a compensation resistor and a compensation capacitor. The oscillator is used for generating an oscillation signal. The input terminal is used for receiving an input voltage. The output terminal is used for receiving an output voltage. The feedback module is connected to the output terminal, and the feedback module is used for generating a feedback signal according to the output voltage. The switch module is used for determining an electric connection of the input terminal, ground voltage and the output terminal according to a next-stage switch signal. The current detecting circuit is connected to the input terminal so as to receive an input current, and is used for generating an image current. The slope compensating circuit is used for receiving a pre-stage switch signal and accordingly generating a slope compensating current. One terminal of the detection resistor is connected to the current detecting circuit and the slope compensating circuit for transforming a sum of the image current and the slope compensating current to a detection voltage. The error amplifier is connected to the feedback module for amplifying a difference of the feedback signal and a first reference voltage so as to generate a difference voltage. The modulation compensating circuit is connected to the error amplifier for compensating frequency response of the current-mode buck converter according to the difference voltage and then generating a compensation voltage. A control terminal of the compensation switch receives a mode switch signal and accordingly makes one terminal of the compensation switch be switched to one of a PWM terminal and a PFM terminal. One terminal of the compensation resistor is connected to another terminal of the compensation switch. A first terminal of the compensation capacitor is connected to another terminal of the compensation resistor, and a second terminal of the compensation capacitor is connected the ground voltage. The first comparator receives the detection voltage and compares the detection voltage with the compensation voltage so as to generate a PWM signal accordingly. The second comparator receives and compares the compensation voltage with a threshold voltage so as to generate and transmit a sleep-trigger signal to the current detecting circuit and the slope compensating circuit. The modulation control circuit is connected to the oscillator, the slope compensating circuit, the first comparator and the second comparator, for generating the pre-stage switch signal according to the PWM signal and the oscillation signal. The zero-crossing detecting circuit is connected to switch module for detecting current. The buffer receives the detection voltage and outputs the detection voltage to the PFM terminal. When the current-mode buck converter enters into a pulse frequency modulation mode from a pulse width modulation mode, one terminal of the compensation switch is switched and connected to the PFM terminal from the PWM terminal for receiving the detection voltage, and voltage level of the detection voltage is equal to voltage level of the compensation voltage at this time, and thus reduces switch loss of the current-mode buck converter and stabilizes a transition between the pulse frequency modulation mode and the pulse width modulation mode. 
         [0009]    In an embodiment of the instant disclosure, wherein when current-mode buck converter is in the pulse width modulation mode, the zero-crossing detecting circuit outputs the mode switch signal with low voltage level to the modulation control circuit and the compensation switch, so that one terminal of the compensation switch is switched and connected to PWM terminal, and when the current-mode buck converter is in the pulse frequency modulation mode, the zero-crossing detecting circuit outputs the mode switch signal with high voltage level to the modulation control circuit and the compensation switch, so that one terminal of the compensation switch is switched and connected to the PFM terminal. 
         [0010]    In an embodiment of the instant disclosure, wherein when the compensation voltage is smaller than the threshold voltage, the second comparator transmits the sleep-trigger signal with high voltage level to the current detecting circuit and the slope compensating circuit so as to shut down work. 
         [0011]    In an embodiment of the instant disclosure, wherein the PWM signal is a signal generated by interacting peak value which is a sum of the compensation voltage, the image current and the slope compensating current. 
         [0012]    In an embodiment of the instant disclosure, wherein the switch module comprises a buffer amplifier, a up-bridge switch transistor and a down-bridge switch transistor. The buffer amplifier is connected to the modulation control circuit for amplifying the pre-stage switch signal so as to generate the next-stage switch signal. The up-bridge switch transistor is connected to the input terminal and the buffer amplifier is used for receiving the next-stage switch signal. The down-bridge switch transistor is connected to the ground voltage and the buffer amplifier for receiving the next-stage switch signal, and the down-bridge switch transistor determines electric connection of the ground voltage and the output terminal according to an in-phase signal or an anti-phase signal. 
         [0013]    In an embodiment of the instant disclosure, wherein the up-bridge switch transistor is a P type metal-oxide semiconductor transistor and the down-bridge switch transistor is an N type metal-oxide semiconductor transistor. 
         [0014]    In an embodiment of the instant disclosure, wherein the feedback module comprises a first resistor and a second resistor. One terminal of the first resistor is connected to the output terminal for receiving the output voltage. One terminal of the second resistor is connected to another terminal of the first resistor and outputs the feedback signal to the error amplifier, and another terminal of the second resistor is connected to the ground voltage. Voltage of the feedback signal is partial voltage of the output voltage. 
         [0015]    In an embodiment of the instant disclosure, wherein the modulation control circuit generates the pre-stage switch signal according to the PWM signal and the oscillation signal when the PWM signal is in high voltage level. 
         [0016]    In an embodiment of the instant disclosure, wherein the threshold voltage is a fixed voltage. 
         [0017]    The instant disclosure provides another electronic system. The electronic system comprises a current-mode buck converter and a load. The current-mode buck converter receives an input voltage and the input voltage is step down to output voltage. The load is connected to the current-mode buck converter for receiving the output voltage. 
         [0018]    In summary, the current-mode buck converter and the electronic system using the same provided by the instant disclosure is able to reduce switch loss when the current-mode buck converter is switched between the pulse width modulation mode and the pulse frequency modulation mode, and the output voltage of the current-mode buck converter is stabilized. 
         [0019]    For further understanding of the instant disclosure, reference is made to the following detailed description illustrating the embodiments and examples of the instant disclosure. The description is only for illustrating the instant disclosure, not for limiting the scope of the claim. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which: 
           [0021]      FIG. 1  shows circuit schematic view of the current-mode buck converter according to prior art; 
           [0022]      FIG. 2  shows a block schematic view of the current-mode buck converter according to the embodiment of the instant disclosure; 
           [0023]      FIG. 3  shows a time-varying schematic view of the detection voltage to the embodiment of the instant disclosure; and 
           [0024]      FIG. 4  shows block schematic view of the electronic system according to the embodiment of the instant disclosure. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0025]    The aforementioned illustrations and following detailed descriptions are exemplary for the purpose of further explaining the scope of the instant disclosure. Other objectives and advantages related to the instant disclosure will be illustrated in the subsequent descriptions and appended drawings. 
         [0026]    It will be understood that, although the terms first, second, third, and the like, may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only to distinguish one element, component, region, layer or section from another region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0027]    [One Embodiment of the Current-Mode Buck Converter] 
         [0028]    Referring to  FIG. 2 ,  FIG. 2  shows a block schematic view of the current-mode buck converter according to the embodiment of the instant disclosure. The current-mode buck converter  200  comprises an oscillator, an input terminal, an output terminal, a feedback module, a switch module, a current detecting circuit, a slope compensating circuit, a detection resistor, an error amplifier, a modulation compensating circuit, a first comparator, a second comparator, a modulation control circuit, a zero-crossing detecting circuit and a buffer. The modulation compensating circuit comprises a compensation switch, a compensation resistor and a compensation capacitor. The feedback module  260  comprises a first resistor R 1  and a second resistor R 2 . The switch module  250  comprises a buffer amplifier  252 , an up-bridge switch transistor MP and a down-bridge switch transistor MN, wherein the up-bridge switch transistor MP is a P type metal-oxide semiconductor transistor and the down-bridge switch transistor MN is an N type metal-oxide semiconductor transistor. 
         [0029]    The oscillator  210  is connected to the modulation control circuit  220 . The modulation control circuit  220  is electrically connected to the slope compensating circuit  240  and an input terminal of the buffer amplifier  252  in the switch module  250  respectively. The output terminal of the buffer amplifier  252  is electrically connected to gate of the up-bridge switch transistor MP and the down-bridge switch transistor MN respectively. Source of the up-bridge switch transistor MP is connected to the input terminal IT for receiving the input voltage VIN. Drain of the down-bridge switch transistor MN is electrically connected to drain of the up-bridge switch transistor MP, and output terminal OT. Source of the down-bridge switch transistor MN is connected to the ground voltage GND and the input terminal of the zero-crossing detecting circuit ZT. One terminal of the first resistor R 1  is electrically connected to the output terminal OT and one terminal of the output capacitor COUT, and another terminal of the first resistor R 1  is electrically connected to one terminal of the second resistor R 2  and an negative input terminal of the error amplifier E 1 , and another terminal of the second resistor R 2  is electrically connected to the ground voltage GND, wherein another terminal of the output capacitor COUT is electrically connected to the ground voltage GND. A positive input terminal of the error amplifier E 1  receives a first reference voltage VREF 1 , and output terminal of the error amplifier E 1  is electrically connected to a negative input terminal of the first comparator COP 1 , wherein the output terminal of the error amplifier E 1  is a PWM terminal T 1 . The output terminal of the first comparator COP 1  is electrically connected to the modulation control circuit  220 . 
         [0030]    The output terminal of the zero-crossing detecting circuit ZT is connected to the modulation control circuit  220  and a control terminal of the compensation switch  51  in the modulation compensating circuit  270 . The slope compensating circuit  240  is electrically connected to one terminal of the detection resistor RT, and the current detecting circuit  230  is electrically connected to the input terminal IT and one terminal of the detection resistor RT. One terminal of the detection resistor RT is electrically connected to a positive terminal of the first comparator COP 1 , and another terminal of the detection resistor RT is electrically connected to the ground voltage GND. One terminal of the compensation resistor ROP is electrically connected to another terminal of the compensation switch S 1 . A first terminal of the compensation capacitor COP is electrically connected to another terminal of the compensation resistor ROP, and a second terminal of the compensation capacitor COP is electrically connected to the ground voltage GND. The input terminal of the buffer B 1  is electrically connected to the first terminal of the detection resistor RT, and the output terminal of the buffer B 1  is PFM terminal T 2 . The input terminal of the second comparator COP 2  is electrically connected to the output terminal of the error amplifier E 1 , the input terminal of the second comparator COP 2  is electrically connected to the threshold voltage VTH, and the output terminal of the second comparator COP 2  is electrically connected to the current detecting circuit  230  and the slope compensating circuit  240 , wherein the threshold voltage VTH is a fixed voltage. 
         [0031]    In the present embodiment, the current-mode buck converter  200  receives the input voltage VIN through the input terminal IT, and outputs the output voltage VOUT through the output terminal OT. The feedback module  260  generates a feedback signal VFB according to the output voltage VOUT. Furthermore, the feedback module  260  receives the output voltage VOUT through the first resistor R 1 , and outputs the feedback signal VFB to the negative input terminal of the error amplifier E 1 , wherein voltage of the feedback signal VFB is a partial voltage of the output voltage VOUT, and ratio of the partial voltage is that resistor value of the second resistor R 2  is divided by the sum of the first resistor R 1  and the second resistor R 2 . The switch module  250  determines electric connection of the input terminal IT, the ground voltage GND and the output terminal OT according to the next-stage switch signal SWB. The current detecting circuit  230  amplifies an input current ISNP received so as to generate an image current ISP. The slope compensating circuit  240  receives a pre-stage switch signal SW so as to operate correspondingly according to the pre-stage switch signal SW, and accordingly generates the slope compensating current ISC. In the present embodiment, the current-mode buck converter  200  gathers image current ISP and the slope compensating current ISC together according to the adder AD and make it flow from the detection resistor RT to the ground voltage GND. Referring to  FIGS. 2 and 3  concurrently,  FIG. 3  shows that peak value of the sum of the image current ISP and the slope compensating current ISC may be changed with magnitude of the input voltage VIN and the output voltage VOUT. Next, the instant disclosure transforms a sum of the image current ISP and the slope compensating current ISC to the detection voltage VC through the detection resistor RT, wherein the detection voltage VC is electrically connected to the input terminal of the first comparator COP 1  and the input terminal of the buffer B 1 . The error amplifier E 1  is used for amplifying a difference of the feedback signal VFB and the first reference voltage VREF 1  so as to generate a difference voltage ΔV. The modulation compensating circuit  270  compensates frequency response of the current-mode buck converter  200  so as to generate a compensation voltage EAO, wherein one terminal of the compensation switch S 1  of the modulation compensating circuit  270  is switched and connected to one of the PWM terminal T 1  and the PFM terminal T 2 . 
         [0032]    Next, the first comparator COP 1  receives the detection voltage VC and the compensation voltage EAO, and then compares the detection voltage VC with the compensation voltage EAO so as to generate the PWM signal PS, wherein the PWM signal PS is a signal generated by interacting peak value which is a sum of the compensation voltage, the image current and the slope compensating current. The second comparator COP 2  receives the compensation voltage EAO and the threshold voltage VTH, and then compares the compensation voltage EAO with the threshold voltage VTH and accordingly generates the sleep-trigger signal SLE, which is transmitted to the current detecting circuit  230  and the slope compensating circuit  240 . The modulation control circuit  220  is used for generating the pre-stage switch signal SW according to the PWM signal PS and the oscillation signal VOSC, wherein the oscillation signal VOSC is generated from the oscillator  210 . The zero-crossing detecting circuit ZT is used for detecting a source current ISNN of the down-bridge switch transistor MN, and transmits the mode switch signal PF to the modulation control circuit  220  and the compensation switch S 1  according to a comparison result. The buffer B 1  receives the detection voltage VC and outputs the detection voltage VC to the PFM terminal T 2 . It is to be noted that when the current-mode buck converter  200  is in the pulse width modulation (PWM) mode, the buffer B 1  is in a disable state. When the current-mode buck converter  200  is in the pulse frequency modulation (PFM) mode, the second comparator COP 2  transmits the sleep-trigger signal SLE with low voltage level to current detecting circuit  230  and the slope compensating circuit  240  according to the comparison result of the compensation voltage EAO and the threshold voltage VTH, so as to enable or disable the current detecting circuit  230  and the slope compensating circuit  240 . 
         [0033]    In the following description is further instruction in teaching a work mechanism of the current-mode buck converter  200 . 
         [0034]    When the current-mode buck converter  200  enters into the PFM mode from the PWM mode, one terminal of the compensation switch S 1  is switched and connected to the PFM terminal T 2  from the PWM terminal T 1  so as to receive the detection voltage VC and voltage level of the detection voltage VC is substantially close to or equal to voltage level of the compensation voltage EAO in the PWM mode; which means, the detection voltage VC is able to carry information related to the voltage of the compensation voltage EAO so as to reduce oscillation of the current-mode buck converter  200  switched between the PWM mode and the PFM mode. Furthermore, when the current-mode buck converter  200  is in the PWM mode, the zero-crossing detecting circuit ZT outputs the mode switch signal PF with low voltage level to the modulation control circuit  220  and the compensation switch S 1  according to a detection result, so that one terminal of the compensation switch S 1  is switched and connected to the PWM terminal T 1 . When the current-mode buck converter  200  is in the PFM mode, the zero-crossing detecting circuit ZT outputs the mode switch signal PF with high voltage level to the modulation control circuit  220  and a control terminal of the compensation switch S 1  according to the detection result, so that one terminal of the compensation switch S 1  is electrically connected to the PFM terminal T 2 , wherein the buffer B 1  may output a detection voltage VC, and voltage level of the detection voltage VC is equal to voltage level of the compensation voltage EAO. It is worth noticing that, when the current-mode buck converter  200  enters into the PFM mode from the PWM mode, the second comparator COP 2  transmits the sleep-trigger signal SLE with high voltage level to the current detecting circuit  230  and the slope compensating circuit  240  according to the comparison result of the compensation voltage EAO and the threshold voltage VTH (i.e. when the compensation voltage EAO is smaller than the threshold voltage VTH), so as to disable the current detecting circuit  230  and the slope compensating circuit  240 ; which means, the current detecting circuit  230  and the slope compensating circuit  240  may temporarily shut down work. 
         [0035]    Regarding the switch module  250  in the present embodiment, people skilled in the arts should be understood that, the buffer amplifier  252  is used for amplifying the pre-stage switch signal SW so as to generate the next-stage switch signal SWB. The up-bridge switch transistor MP is used for receiving the next-stage switch signal SWB, and the down-bridge switch transistor MN is used for determining electric connection of the ground voltage GND and the output terminal according to an in-phase signal or an anti-phase signal of the next-stage switch signal SWB. 
         [0036]    Accordingly, when the current-mode buck converter  200  of the instant disclosure is changed from the PWM mode to the PFM mode, i.e. one terminal of the compensation switch S 1  is changed and connected to the PFM terminal T 2  from the PWM terminal T 1 , the current-mode buck converter  200  is able to make one terminal of the compensation switch S 1  be connected to the detection voltage VC so that voltage level of the compensating capacitor COP is equal to that of compensation voltage EAO and thus reduces switch loss of the current-mode buck converter  200  switched between the PWM mode and the PFM mode, and stabilizes the output voltage VOUT of the current-mode buck converter  200 . 
         [0037]    [One Embodiment of the Electronic System] 
         [0038]    Referring to  FIG. 4 ,  FIG. 4  shows block schematic view of the electronic system according to the embodiment of the instant disclosure. The electronic system  400  comprises a load  420  and the current-mode buck converter  410  connected to the load  420 , wherein the current-mode buck converter  410  receives the input voltage VIN and makes the input voltage VIN be step down to the output voltage VOUT. The current-mode buck converter  410  may be the current-mode buck converter  200  in  FIG. 2 . In the present embodiment, through operation mechanism of the current-mode buck converter  410 , the electronic system  400  is able to do that when the current-mode buck converter  410  is switched between the PFM mode and the PWM mode, switch loss of the electronic system  400  is reduced and the output voltage VOUT is maintained stably. 
         [0039]    To sum up, the current-mode buck converter and the electronic system using the same provided by the instant disclosure is able to reduce switch loss when the current-mode buck converter is switched between the pulse width modulation mode and the pulse frequency modulation mode, and the output voltage of the current-mode buck converter is stabilized. 
         [0040]    The descriptions illustrated supra set forth simply the preferred embodiments of the instant disclosure; however, the characteristics of the instant disclosure are by no means restricted thereto. All changes, alternations, or modifications conveniently considered by those skilled in the art are deemed to be encompassed within the scope of the instant disclosure delineated by the following claims.