Abstract:
A two-wire load control device, such as a dimmer, is operable to control the amount of power delivered to an electrical load, such as a magnetic low-voltage (MLV) load, and comprises a bidirectional semiconductor switch, a timing circuit, a trigger circuit having a variable voltage threshold, and a clamp circuit. When a timing voltage signal of the timing circuit exceeds an initial magnitude of the variable voltage threshold, the trigger circuit is operable to render the semiconductor switch conductive, reduce the timing voltage signal to a predetermined magnitude less than the initial magnitude, and to increase the variable voltage threshold to a second magnitude greater than the first magnitude. The clamp circuit limits the magnitude of the timing voltage signal to a clamp magnitude between the initial magnitude and the second magnitude, thereby preventing the timing voltage signal from exceeding the second magnitude. Accordingly, multiple attempted firings of the semiconductor switch are avoided, and the MLV dimmer is prevented from conducting asymmetric current when an MLV transformer of the MLV load is unloaded.

Description:
RELATED APPLICATIONS 
       [0001]    This application is a divisional application of commonly-assigned U.S. patent application Ser. No. 11/705,477, filed Feb. 12, 2007, entitled METHOD AND APPARATUS FOR PREVENTING MULTIPLE ATTEMPTED FIRINGS OF A SEMICONDUCTOR SWITCH IN A LOAD CONTROL DEVICE, which claims priority to U.S. Provisional Application Ser. No. 60/783,538, filed Mar. 17, 2006, entitled DIMMER FOR PREVENTING ASYMMETRIC CURRENT FLOW THROUGH AN UNLOADED MAGNETIC LOW VOLTAGE TRANSFORMER. The entire disclosures of both applications are hereby incorporated by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    The present invention relates to load control devices for controlling the amount of power delivered to an electrical load. More specifically, the present invention relates to a drive circuit for a two-wire analog dimmer that includes a trigger circuit having a variable voltage threshold for preventing multiple attempted firings of a bidirectional semiconductor switch of the dimmer. 
         [0004]    2. Description of the Related Art 
         [0005]    A typical lighting dimmer is coupled between a source of alternating-current (AC) power (typically 50 or 60 Hz line voltage AC mains) and a lighting load. Standard dimmers use one or more semiconductor switches, such as triacs or field effect transistors (FETs), to control the amount of power delivered to the lighting load and thus the intensity of the light emitted by the load. The semiconductor switch is typically coupled in series between the source and the lighting load. Using a phase-control dimming technique, the dimmer renders the semiconductor switch conductive for a portion of each line half-cycle to provide power to the lighting load, and renders the semiconductor switch non-conductive for the other portion of the line half-cycle to disconnect power from the load. 
         [0006]    Some dimmers are operable to control the intensity of low-voltage lighting loads, such as magnetic low-voltage (MLV) and electronic low-voltage (ELV) loads. Low-voltage loads are generally supplied with AC power via a step-down transformer, typically an isolation transformer. These step-down transformers step the voltage down to the low-voltage level, for example 12 to 24 volts, necessary to power the lamp or lamps. One problem with low-voltage lighting loads employing a transformer, specifically MLV loads, is that the transformers are susceptible to any direct-current (DC) components of the voltage provided across the transformer. A DC component in the voltage across the transformer can cause the transformer to generate acoustic noise and to saturate, increasing the temperature of the transformer and potentially damaging the transformer. 
         [0007]      FIG. 1A  is a simplified schematic diagram of a prior art magnetic low-voltage dimmer  10 . The prior art dimmer  10  is coupled to an AC power source  12  via a HOT terminal  14  and an MLV load  16  via a DIMMED HOT terminal  18 . The MLV load  16  includes a transformer  16 A and a lamp load  16 B. The dimmer  10  further comprises a triac  20 , which is coupled in series electrical connection between the source  12  and the MLV load  16  and is operable to control the power delivered to the MLV load. The triac  20  has a gate (or control input) for rendering the triac conductive. Specifically, the triac  20  becomes conductive at a specific time each half-cycle and becomes non-conductive when a load current i L  through the triac becomes substantially zero amps, i.e., at the end of the half-cycle. The amount of power delivered to the MLV load  16  is dependent upon the portion of each half-cycle that the triac  20  is conductive. An inductor L 22  is coupled in series with the triac  20  for providing noise filtering of electromagnetic interference (EMI) at the HOT terminal  14  and DIMMED HOT terminal  18  of the dimmer  10 . 
         [0008]    A timing circuit  30  includes a resistor-capacitor (RC) circuit coupled in parallel electrical connection with the triac  20 . Specifically, the timing circuit  30  comprises a potentiometer R 32  and a capacitor C 34 . As the capacitor C 34  charges and discharges each half-cycle of the AC power source  12 , a voltage v C  develops across the capacitor. A plot of the voltage v C  across the capacitor C 34  and the load current i L  through the MLV load  16  is shown in  FIG. 2 . The capacitor C 34  begins to charge at the beginning of each half-cycle (i.e., at time to in  FIG. 2 ) at a rate dependent upon the resistance of the potentiometer R 32  and the capacitance of the capacitor C 34 . 
         [0009]    A diac  40 , which is employed as a trigger device, is coupled in series between the timing circuit  30  and the gate of the triac  20 . As soon as the voltage v C  across the capacitor C 34  exceeds a break-over voltage V BR  (e.g., 30V) of the diac  40 , the voltage across the diac quickly decreases in magnitude to a break-back voltage V BB . The quick change in voltage across the diac  40  and the capacitor C 34  causes the diac to conduct a gate current i GATE  to and from the gate of the triac  20 . The gate current i GATE  flows into the gate of the triac  20  during the positive half-cycles and out of the gate of the triac during the negative half-cycles. 
         [0010]      FIG. 1B  is a plot of the voltage-current characteristic of a typical diac. The values of the break-over voltage V BR  and the break-back voltage V BB  may differ slightly during the positive half-cycles and the negative half-cycles. Thus, the voltage-current characteristic of  FIG. 1B  shows the positive break-over voltage V BR+  and the positive break-back voltage V BB+  occurring during the positive half-cycles and the negative break-over voltage V BR−  and the negative break-back voltage V BB−  occurring during the negative half-cycles. 
         [0011]    The charging time of the capacitor C 34 , i.e., the time constant of the RC circuit, varies in response to changes in the resistance of potentiometer R 32  to alter the times at which the triac  20  begins conducting each half-cycle of the AC power source  12 . The magnitude of the gate current i GATE  is limited by a gate resistor R 42 . The gate current i GATE  flows for a period of time T PULSE , which is determined by the capacitance of the capacitor C 34 , the difference between the break-over voltage V BR  and the break-back voltage V BB  of the diac  40 , and the magnitude of the gate current i GATE . After the voltage v C  across the capacitor C 34  has exceeded the break-over voltage V BR  of the diac  40  and the gate current i GATE  has decreased to approximately zero amps, the voltage v C  decreases by substantially the break-back voltage V BB  of the diac  40 . 
         [0012]    While the gate current i GATE  is flowing through the gate of the triac  20 , the triac will begin to conduct current through the main load terminals, i.e., between the source  12  and the MLV load  16  (as shown at time t 1  in  FIG. 2 ). In order for the triac  20  to remain conductive after the gate current i GATE  ceases to flow, the load current i L  must exceed a predetermined latching current I LATCH  of the triac before the gate current reaches zero amps. When the MLV lamp  16 B is connected to the MLV transformer  16 A, the load current i L  through the main load terminals of the triac  20  is large enough such that the load current exceeds the latching current I LATCH  of the triac. Thus, when the magnitude of the gate current i GATE  falls to substantially zero amps after the gate current period T PULSE , the triac  20  remains conductive during the rest of the present half-cycle, i.e., until the load current i L  through the main load terminals of the triac  20  nears zero amps (e.g., at time t 2  in  FIG. 2 ). 
         [0013]    When the MLV lamp  16 B is not connected to the MLV transformer  16 A, i.e., the MLV transformer is unloaded, the MLV load  16  will have a larger inductance than when the MLV lamp is connected to the MLV transformer. The larger inductance L causes the load current i L  through the main load terminals of the triac  20  to increase at a slower rate since the rate of change of the current through an inductor is inversely proportional to the inductance, i.e., di L /dt=v L /L (assuming the instantaneous voltage v L  across the inductor remains constant). Accordingly, when the MLV lamp  16 B is not connected, the load current i L  may not rise fast enough to exceed the latching current of the triac  20 , and the triac may stop conducting when the gate current i GATE  falls to substantially zero amps. 
         [0014]      FIG. 3  is a plot of the voltage v C  across the capacitor C 34  and the load current i L  when the MLV transformer  16 A is unloaded. After the voltage v C  exceeds the break-over voltage V BR  of the diac  40  (as shown by a peak A 1 ), the load current i L  begins to increase slowly (as shown by a peak B 1 ). However, the load current i L  does not reach the latching current I LATCH  of the triac  20  before the gate current I GATE  stops flowing, and thus the triac  10  does not latch on and the load current i L  will begin to decrease. Because the triac  20  did not latch and becomes non-conductive, the voltage across the timing circuit  20  will be a substantially large voltage, i.e., substantially equal to the voltage of the AC power source  12 , and the capacitor C 34  will begin to charge again (as shown by a peak A 2 ). Note that the load current i L  does not have enough time to drop to zero amps. When the voltage v C  exceeds the break-over voltage V BR  for the second time in the present half-cycle, the gate current i GATE  flows through the gate and the triac  20  will once again attempt to fire (as shown by a peak B 2 ). Because the load current i L  is not zero amps when the gate current i GATE  begins to flow, the load current rises to a greater value than was achieved at peak B 1 . Nonetheless, the load current i L  does not reach the latching current I LATCH , and thus the cycle repeats again (as shown by peaks A 3  and B 3 ). A similar, but complementary, situation occurs during the negative half-cycles. As shown in  FIG. 3 , the load current i L  does not exceed the latching current I LATCH  during any of the AC line half-cycles. 
         [0015]    As the situation of  FIG. 3  repeats for multiple half-cycles, i.e., the triac  20  attempts to repeatedly fire from one half-cycle to the next, the load current i L  through the main load terminals of the triac may acquire either a positive or a negative DC component. Eventually, the DC component will cause the load current i L  to exceed the latching current I LATCH  during some half-cycles, e.g., the negative half-cycles as shown in  FIG. 4 . Thus, an asymmetric load current i L  will flow through the MLV load  16 , causing the MLV transformer  16 A to generate acoustic noise and to overheat, which can potentially damage the MLV transformer. 
         [0016]    Thus, there exists a need for an MLV dimmer that prevents the conduction of asymmetric currents through an MLV load when the MLV transformer is unloaded. 
       SUMMARY OF THE INVENTION 
       [0017]    According to an embodiment of the present invention, a trigger circuit operable to control a semiconductor switch in a load control device is characterized by a variable voltage threshold. The trigger circuit comprises a break-over circuit and an offset circuit. The break-over circuit is characterized by a break-over voltage and is operable to conduct a control current when a voltage across the break-over circuit exceeds the break-over voltage. The semiconductor switch is operable to change between the non-conductive and conductive states in response to the control current. The offset circuit is coupled in series with the break-over circuit and is operable to conduct the control current, whereby an offset voltage develops across the offset circuit. The trigger circuit is characterized by an initial voltage threshold before the break-over circuit and the offset circuit conduct the control current. The initial voltage threshold has a magnitude substantially equal to the magnitude of the break-over voltage. The trigger circuit is further characterized by a second voltage threshold after the break-over circuit and the offset circuit conduct the control current. The second voltage threshold has a maximum magnitude substantially equal to the break-over voltage of the break-over circuit plus the offset voltage. 
         [0018]    The present invention further provides a drive circuit for controlling a semiconductor switch in a load control device. The drive circuit comprises a break-over circuit characterized by a break-over voltage and operable to conduct a control current when a voltage across the break-over circuit exceeds the break-over voltage, and an offset circuit coupled in series with the break-over circuit and operable to conduct the control current, whereby an offset voltage develops across the offset circuit. The semiconductor switch is operable to change between the non-conductive and conductive states in response to the control current. The break-over circuit is operable to conduct the control current when a voltage across the series combination of the break-over circuit and the offset circuit exceeds a initial voltage threshold and to conduct the control current again only if the voltage across the series combination of the break-over circuit and the offset circuit subsequently exceeds a second voltage threshold. The initial voltage threshold has a magnitude approximately equal to the magnitude of the break-over voltage of the break-over circuit, and the second voltage threshold has a magnitude approximately equal to the break-over voltage of the break-over circuit plus the offset voltage. In addition, the drive circuit may also comprise a clamp circuit operable to limit the magnitude of the voltage across the series combination of the break-over circuit and the offset circuit to approximately a clamp magnitude greater than the initial voltage threshold and less than the second voltage threshold, such that the voltage across the series combination of the break-over circuit and the offset circuit is prevented from exceeding the second voltage threshold. 
         [0019]    Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]      FIG. 1A  is a simplified schematic diagram of a prior art MLV dimmer; 
           [0021]      FIG. 1B  is a plot of a voltage-current characteristic of a diac of the MLV dimmer of  FIG. 1A ; 
           [0022]      FIG. 2  is a plot of a voltage across a timing capacitor in and a load current i L  through the MLV dimmer of  FIG. 1A ; 
           [0023]      FIG. 3  is a plot of the voltage across the timing capacitor and the load current i L  when the MLV transformer is unloaded; 
           [0024]      FIG. 4  is a plot of the voltage across the timing capacitor and the load current i L  demonstrating asymmetric behavior when the MLV transformer is unloaded; 
           [0025]      FIG. 5A  is a simplified block diagram of an MLV dimmer according to the present invention; 
           [0026]      FIG. 5B  is a perspective view of a user interface of the MLV dimmer of  FIG. 5A ; 
           [0027]      FIG. 6  is a simplified schematic diagram of an MLV dimmer according to a first embodiment of the present invention; 
           [0028]      FIG. 7  is a diagram of waveforms demonstrating the operation of the MLV dimmer of  FIG. 6 ; 
           [0029]      FIG. 8  is a simplified schematic diagram of an MLV dimmer according to a second embodiment of the present invention; 
           [0030]      FIG. 9  is a plot of a timing voltage and a load current of the MLV dimmer of  FIG. 8 ; and 
           [0031]      FIG. 10  is a simplified schematic diagram of an MLV dimmer according to a third embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0032]    The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed. 
         [0033]      FIG. 5A  is a simplified block diagram of an MLV dimmer  100  according to the present invention. The MLV dimmer  100  comprises a semiconductor switch  120  coupled in series electrical connection between the AC power source  12  and the MLV load  16 . The semiconductor switch  120  may comprise a triac, a field effect transistor (FET) or an insulated gate bipolar transistor (IGBT) in a full-wave rectifier bridge, two FETs or two IGBTs in anti-series connection, or any other suitable type of bidirectional semiconductor switch. The semiconductor switch  120  has a control input for controlling the semiconductor switch between a substantially conductive state and a substantially non-conductive state. 
         [0034]    A timing circuit  130  is coupled in parallel electrical connection with the semiconductor switch  120  and provides a timing voltage signal v T  at an output. The timing voltage signal v T  increases with respect to time at a rate dependent on a target dimming level of the MLV load  16 . A user interface  125  provides an input to the timing circuit  130  to provide the target dimming level of the MLV load  16  and to control the rate at which the timing voltage signal v T  increases. A trigger circuit  140  is coupled between the output of the timing circuit  130  and the control input of the semiconductor switch  120 . As the timing voltage signal v T  increases, a trigger voltage signal develops across the trigger circuit  140 . The trigger voltage signal typically has a magnitude that is substantially equal to the magnitude of the timing voltage signal v T . 
         [0035]    The trigger circuit  140  is characterized by a variable voltage threshold V TH , which has an initial value of V 1 . When the timing voltage signal v T  at the output of the timing circuit  130  exceeds substantially the initial value V 1  of the voltage threshold V TH , the trigger circuit  130  conducts a control current i CONTROL , which causes the semiconductor switch  120  to become conductive. At this time, the timing voltage signal v T  is reduced to a level less than the initial voltage threshold V 1  and the voltage threshold V TH  is preferably increased by an increment ΔV. Accordingly, the timing voltage signal v T  will need to rise to a greater level to exceed the new incremented voltage threshold, i.e., V TH =V 1 +ΔV. Preferably, the voltage threshold V TH  is reset to the initial voltage threshold V 1  after a predetermined period of time after being increased to V 1 +ΔV. Preferably, the voltage threshold V TH  is reset to the initial voltage threshold V 1  prior to the start of the next line voltage cycle. 
         [0036]    The MLV dimmer  100  further comprises a clamp circuit  150  coupled between the output of the timing circuit  130  and the DIMMED HOT terminal  18 . The clamp circuit  150  limits the magnitude of the timing voltage signal v T  at the output of the timing circuit  130  to approximately a clamp voltage V CLAMP . Accordingly, the magnitude of the trigger voltage across the trigger circuit  140  is also limited. The clamp voltage V CLAMP  preferably has a magnitude greater than the initial voltage threshold V 1 , but less than the incremented voltage threshold, i.e., 
         [0000]    
       
      
       V 
       1 
       &lt;V 
       CLAMP 
       &lt;V 
       1 
       +ΔV.  
      
     
         [0037]    The MLV dimmer  100  also comprises a mechanical switch  124  coupled in series with the semiconductor switch  120 , i.e., in series between the AC power source  12  and the MLV load  16 . When the mechanical switch  124  is open, the AC power source  12  is disconnected from the MLV load  16 , and thus the MLV lamp  16 B is off. When the mechanical switch  124  is closed, the semiconductor switch  120  is operable to control the intensity of the MLV lamp  16 B. An inductor L 122  is coupled in series with the semiconductor switch  120  to providing filtering of EMI noise. 
         [0038]      FIG. 5B  is a perspective view of the user interface  125  of the MLV dimmer  100 . The user interface  125  includes a faceplate  126 , a pushbutton  127  (i.e., a toggle actuator), and a slider control  128 . Pressing the pushbutton  127  actuates the mechanical switch  124  inside the dimmer  100 . Consecutive presses of the pushbutton  127  toggle the mechanical switch  124  between an open state and a closed state. The slider control  128  comprises an actuator knob  128 A mounted for sliding movement along an elongated slot  128 B. Moving the actuator knob  128 A to the top of the elongated slot  128 B increases the intensity of the MLV lamp  16 B and moving the actuator knob  128 A to the bottom of the elongated slot  128 B decreases the intensity of the MLV lamp. 
         [0039]      FIG. 6  is a simplified schematic diagram of an MLV dimmer  200  according to a first embodiment of the present invention. The MLV dimmer  200  comprises a triac  220  having a pair of main terminals coupled in series electrical connection between the AC power source  12  and the MLV load  16 . The triac  220  has a control input, i.e., a gate terminal, for rendering the triac  220  conductive. The MLV dimmer  200  further comprises a timing circuit  230  coupled in parallel with the main terminals of the triac  220  and comprising a potentiometer R 232  in series with a capacitor C 234 . A timing voltage signal v T  is generated at an output, i.e., the junction of the potentiometer R 232  and the capacitor C 234 , and is provided to a trigger circuit  240 . The resistance of the potentiometer R 232  may be varied in response to the actuation of a slider control of a user interface of the dimmer  200  (for example, the slider control  128  of the user interface  125 ). 
         [0040]    The trigger circuit  240  is coupled in series electrical connection between the output of the timing circuit  230  and the gate of the triac  220 . The trigger circuit  240  includes a break-over circuit comprising a diac  260 , which operates similarly to the diac  40  in the prior art dimmer  10 , and an offset circuit  270 . As the timing voltage signal v T  increases, a trigger voltage signal develops across the trigger circuit  240 . Since the voltage across the gate-anode junction of the triac  220  (i.e., from the gate of the triac to the DIMMED HOT terminal  18 ) is a substantially small voltage, i.e., approximately 1 V, the magnitude of the trigger voltage signal is substantially equal to the magnitude of the timing voltage signal v T . 
         [0041]    When the timing voltage signal v T  exceeds the break-over voltage V BR  of the diac  260  (e.g., approximately 30V), a gate current i GATE  flows through the offset circuit  270 , specifically, through a diode D 272 A and a capacitor C 274 A into the gate of the triac  220  in the positive line voltage half-cycles, and out of the gate of the triac  220  and through a capacitor C 274 B and a diode D 272 B in the negative line voltage half-cycles. The capacitors C 274 A, C 274 B both have, for example, a capacitance of about 82 nF. The gate current i GATE  flows for a period of time T PULSE , e.g., approximately 1 μsec or greater. Discharge resistors R 276 A, R 276 B are coupled in parallel with the capacitors C 274 A, C 274 B, respectively. The MLV dimmer  200  further comprises a current limiting resistor R 280  in series with the gate of the triac  220  to limit the magnitude of the gate current i GATE , for example, to approximately 1 amp or less. 
         [0042]    The MLV dimmer  200  also includes a clamp circuit  250  coupled between the output of the timing circuit  230  and the DIMMED HOT terminal  18 . The clamp circuit  250  comprises two zener diodes Z 252 A, Z 252 B, each having the substantially the same break-over voltage V Z , e.g., approximately 40V. The cathodes of the zener diodes Z 252 A, Z 252 B are coupled together such that the clamp circuit  250  limits the timing voltage signal v T  to the same voltage, i.e., the break-over voltage V Z , in both line voltage half-cycles. 
         [0043]      FIG. 7  shows waveforms demonstrating the operation of the MLV dimmer  200 . At the beginning of a positive half-cycle (e.g., at time to), the voltage threshold V TH  of the trigger circuit  240  is at the initial voltage threshold V 1 . At first, the capacitor C 274 A of the offset circuit  270  has no charge, and thus, no voltage is developed across the capacitor. The timing voltage signal v T  increases until the initial voltage threshold V 1 , i.e., the break-over voltage V BR  of the diac  260  (plus the small forward drop of the diode D 272 A), is exceeded (at time t 1 ). At this time, the diac  260  conducts the gate current i GATE  through the diode D 272 A and the capacitor C 274 A into the gate of the triac  220 . A voltage ΔV develops across the offset circuit  270 , specifically, across the capacitor C 274 A, and has a maximum magnitude ΔV MAX  equal to 
         [0000]      Δ V   MAX   =I   GATE   ·T   PULSE   /C   274A , 
         [0000]    where C 274A  is the capacitance of the capacitor C 274 A. In a preferred embodiment, the maximum magnitude voltage offset ΔV MAX  of the voltage developed across the capacitor C 274 A is approximately 12 volts. 
         [0044]    After the diac  260  conducts the gate current i GATE , the voltage across the capacitor C 234  decreases by approximately the break-back voltage V BB  of the diac to a predetermined voltage V P . If the load current i L  through the triac  220  does not reach the latching current I LATCH  before the gate current i GATE  stops flowing (at time t 2 ), the timing voltage signal v T  will begin to increase again. Since the voltage threshold V TH  is increased to the initial voltage threshold plus the offset voltage ΔV across the capacitor C 274 A, in order to conduct the gate current i GATE  through the gate of the triac  220 , the timing voltage signal v T  must exceed V 1 +ΔV, i.e., approximately 42 volts. However, because the zener diode Z 252 A limits the timing voltage signal v T  to the break-over voltage V Z , i.e., 38 volts, the timing voltage v T  is prevented from exceeding the voltage threshold V TH . Accordingly, the triac  220  is prevented from repeatedly attempting to fire during each half-cycle and the load current i L  is substantially symmetric, even when the MLV transformer  16 A is unloaded. 
         [0045]    The timing voltage signal v T  is prevented from exceeding the voltage threshold V TH  until the voltage ΔV across the capacitor C 274 A decays to approximately the break-over voltage V Z  of the zener diode Z 252 A minus the break-over voltage V BR  of the diac  242 . The discharge resistor R 276 A preferably has a resistance of 68.1 kΩ, such that the capacitor C 274 A will discharge slowly, i.e., with a time constant of about 5.58 msec. Preferably, the time required for the voltage ΔV across the capacitor C 274 A to decay to approximately the break-over voltage V Z  of the zener diode Z 252 A minus the break-over voltage V BR  of the diac  242  is long enough such that the triac  220  only attempts to fire once during each half-cycle. As shown in  FIG. 7 , the voltage across the capacitor C 274 A decays to substantially zero volts during the negative half-cycle such that the voltage across the capacitor C 274 A is substantially zero volts at the beginning of the next positive half-cycle. 
         [0046]      FIG. 8  is a simplified schematic diagram of an MLV dimmer  300  according to a second embodiment of the present invention. The MLV dimmer  300  includes a triac  320  in series electrical connection between the HOT terminal  14  and DIMMED HOT terminal  18  and a timing circuit  330  coupled in parallel with the triac. The timing circuit  330  comprises a potentiometer R 332 , a capacitor C 334 , and a calibrating resistor R 336 . The timing circuit operates in a similar manner to the timing circuit  230  of the MLV dimmer  200  to produce a timing voltage signal v T  at an output. 
         [0047]    The MLV dimmer further includes a rectifier bridge comprising four diodes D 342 A, D 342 B, D 342 C, D 342 D; a trigger circuit comprising a break-over circuit  360  and an offset circuit  370 ; a current limit circuit  380 ; and an optocoupler  390 . The break-over circuit  360 , the current limit circuit  380 , and a photodiode  390 A of the optocoupler  390  are connected in series across the DC-side of the rectifier bridge. The offset circuit  370  is connected such that a first portion  370 A and a second portion  370 B are coupled in series with the break-over circuit  360 , the current limit circuit  380 , and the photodiode  390 A during the positive half-cycles and the negative half-cycles, respectively. The trigger circuit is coupled to the gate of the triac  320  via the optocoupler  390  and resistors R 392 , R 394 , R 396 . 
         [0048]    The break-over circuit  360  includes two bipolar junction transistors Q 362 , Q 364 , two resistors R 366 , R 368 , and a zener diode Z 369 . The break-over circuit  360  operates in a similar fashion as the diac  260  of the MLV dimmer  200 . When the voltage across the break-over circuit  360  exceeds a break-over voltage V BR  of the zener diode Z 369 , the zener diode begins conducting current. The break-over voltage V BR  of the zener diode Z 369  is preferably approximately 30V. The transistor Q 362  begins conducting as the voltage across the resistor R 366  reaches the required base-emitter voltage of the transistor Q 362 . A voltage is then produced across the resistor R 368 , which causes the transistor Q 364  to begin conducting. This essentially shorts out the zener diode Z 369  such that the zener diode stops conducting, and the voltage across the break-over circuit  360  falls to approximately zero volts. A pulse of current, i.e., a control current i CONTROL , flows from the capacitor C 334  through the break-over circuit  360  and the photodiode  390 A of the optocoupler  390 . 
         [0049]    A trigger voltage signal develops across the trigger circuit, i.e., the break-over circuit  360  and the offset circuit  370 , as the timing voltage signal v T  increases from the beginning of each line voltage half-cycle. The magnitude of the trigger voltage signal is substantially equal to the magnitude of the timing voltage signal v T  plus an additional voltage V +  due to the forward voltage drops of the diodes D 342 A, D 342 D, the forward voltage drop of the photodiode  390 A, and the voltage drop of the current limit circuit  380 . For example, the additional voltage V +  may total approximately 4 volts. The trigger circuit is operable to conduct the control current i CONTROL  through the photodiode  390 A of the optocoupler  390  when the timing voltage signal v T  exceeds the break-over voltage V BR  of the zener diode Z 369  of the break-over circuit  360  plus the voltage across the offset circuit  370  and the additional voltage V + . The voltage across the first portion  370 A of the offset circuit  370  is substantially zero volts at the beginning of each positive line voltage half-cycle and the voltage across the second portion  370 B of the offset circuit  370  is substantially zero volts at the beginning of each negative line voltage half-cycle. Accordingly, the initial voltage threshold V 1  is approximately 34 V. The control current i CONTROL  preferably flows through the photodiode  390 A for approximately 300 μsec. Accordingly, when the photodiode  390 A conducts the control current i CONTROL , a photosensitive triac  390 B of the optocoupler  390  conducts to allow current to flow into the gate of the triac  320  in the positive half-cycles, and out of the gate in the negative half-cycles. 
         [0050]    During the positive half-cycles, the control current i CONTROL  flows through the diode D 342 A, the break-over circuit  360 , the photodiode  390 A, the current-limit circuit  380 , a capacitor C 374 A (and a resistor R 376 A), and the diode D 342 D. During the negative half-cycles, the control current i CONTROL  flows through the diode D 342 B, a capacitor C 374 B (and a resistor R 376 B), the break-over circuit  360 , the photodiode  390 A, the current-limit circuit  380 , and the diode D 342 C. Therefore, an offset voltage ΔV develops across the capacitor C 374 A in the positive half-cycles, and across the capacitor C 374 B in the negative half-cycles. Discharge resistors R 376 A,  376 B are coupled in parallel with the capacitors C 374 A, C 374 B to allow the capacitors to discharge slowly. The capacitors C 374 A, C 374 B both preferably have capacitances of about 82 nF and the discharge resistors R 376 A, R 376 B preferably have resistances of about 68.1 kΩ. 
         [0051]    The current-limit circuit  380  comprises a bipolar junction transistor Q 382 , two resistors R 384 , R 386  and a shunt regulator zener diode Z 388 . After the voltage across the trigger circuit  330  drops to approximately zero volts, a voltage substantially equal to the timing voltage signal v T  develops across the current-limit circuit  380 . Current flows through the resistor R 384 , which preferably has a resistance of about 33 kΩ, and into the base of the transistor Q 382 , such that the transistor becomes conductive. Accordingly, the control current i CONTROL  will flow through the photodiode  390 A, the transistor Q 382 , and the resistor R 386 . The diode Z 388  preferably has a shunt connection coupled to the emitter of the transistor Q 382  to limit the magnitude of the control current i CONTROL . Preferably, the shunt diode Z 388  has a reference voltage of 1.25V and the resistor R 386  has a resistance of about 392Ω, such that the magnitude of the control current i CONTROL  is limited to approximately 3.2 mA. 
         [0052]    The MLV dimmer  300  further comprises a clamp circuit  350  similar to the clamp circuit  250  of the MLV dimmer  200 . The clamp circuit  350  includes two zener diodes Z 352 , Z 354  in anti-series connection. Preferably, the zener diodes Z 352 , Z 354  have the same break-over voltage V Z , e.g., 38V, such that the timing voltage signal v T  across the capacitor C 344  is limited to the break-over voltage V Z  in both half-cycles. Accordingly, the trigger voltage signal across the trigger circuit is limited to approximately the break-over voltage V Z  minus the additional voltage V +  due to the other components. 
         [0053]    The MLV dimmer  300  exhibits a similar operation to the MLV dimmer  200 . At the beginning of the positive half-cycles, the voltage ΔV across the capacitor C 374 A is approximately zero volts. Therefore, for the control current i CONTROL  to flow, the timing voltage signal v T  across the capacitor C 334  must exceed the initial voltage threshold V 1 , i.e., the break-over voltage V BR  of the zener diode Z 369  of the break-over circuit  360  plus the additional voltage V +  due to the other components of the MLV dimmer  300 . As noted above, the initial voltage threshold V 1  is approximately 34V. 
         [0054]    When the control current i CONTROL  flows through the first portion  370 A of the offset circuit  370 , the voltage ΔV, which preferably has a magnitude of approximately 12V, develops across the capacitor C 374 A. Therefore, the new voltage threshold V TH  is equal to the initial voltage threshold V 1  plus the voltage ΔV, i.e., approximately 42V. However, since the clamp circuit  350  limits the magnitude of the timing voltage signal v T  to 38V, the timing voltage signal will not be able to exceed the voltage threshold V TH . Thus, the triac  320  will not attempt to repeatedly fire within the same half-cycle, and the load current i L  will remain substantially symmetric. A plot of the timing voltage signal v T  and the load current i L  of the MLV dimmer  300  is shown in  FIG. 9 . 
         [0055]      FIG. 10  is a simplified schematic diagram of an MLV dimmer  400  according to a third embodiment of the present invention. The dimmer  400  includes the same or very similar circuits as the MLV dimmer  300 . However, the circuits of  FIG. 10  are coupled together in a different manner. 
         [0056]    The MLV dimmer  400  includes a clamp circuit  450 , which is coupled across the photodiode  390 A of the optocoupler  390 , the break-over circuit  360 , and an offset circuit  470  rather than across the AC-side of the rectifier bridge as in the MLV dimmer  200 . During the positive half-cycles, a capacitor C 474 A in the offset circuit  470  charges to a voltage ΔV, thus increasing the voltage threshold V TH  to the voltage ΔV plus an initial voltage threshold V 1 . Once again, the voltage ΔV across the capacitor C 474 A is substantially zero volts at the beginning of the positive half-cycles, and thus, the initial voltage threshold V 1  is equal to the break-over voltage V BR , e.g., approximately 30V, of the break-over circuit  360  plus the additional voltage drop V +  due to the other components. A first zener diode Z 452  of the clamp circuit  450  limits the magnitude of the trigger voltage (i.e., the voltage across the break-over circuit  360  and the capacitor C 474 A of the offset circuit  470 ) plus the forward voltage drop of the photodiode  390 A to the break-over voltage V Z  of the zener diode Z 452 , e.g., approximately 36V. Similarly, during the negative half-cycles, a capacitor C 474 B charges to a voltage ΔV and a zener diode Z 454  limits the magnitude of the trigger voltage (i.e., the voltage across the break-over circuit  360  and the capacitor C 474 B of the offset circuit  470 ) plus the forward voltage drop of the photodiode  390 B to the same break-over voltage V Z . 
         [0057]    Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.