Abstract:
A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a high voltage metal-oxide-semiconductor (hereinafter abbreviated as HV MOS) transistor device, and more particularly, to a high voltage lateral double-diffused metal-oxide-semiconductor (HV-LDMOS) transistor device. 
     2. Description of the Prior Art 
     Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are prevalently used in high operational voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low dopant concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, therefore the LDMOS transistor device can have higher breakdown voltage (BVD). 
     It is well-known that characteristics of low R ON  and high breakdown voltage are always required to the HV MOS transistor device. However, breakdown voltage and ON-resistance (hereinafter abbreviated as R ON ) are conflicting parameters with a trade-off relationship. Therefore, a HV LDMOS transistor device that is able to realize high breakdown voltage and low R ON  is still in need. 
     SUMMARY OF THE INVENTION 
     According to the claimed invention, a HV MOS transistor device is provided. The HV MOS transistor device includes a substrate having an insulating region formed therein, a gate formed on the substrate and covering a portion of the insulating region, a source and a drain formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and the body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. 
     According to the HV MOS transistor device provided by the present invention, the first implant region formed near the source region in the substrate, which is adjacent to the body region, includes the conductivity type the same with the source region and the drain region. Therefore, resistance in charge accumulation area is reduced and thus R ON  is reduced. Consequently, the R ON /BVD ratio is desirably lowered. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic drawing of a portion of a layout pattern of a HV MOS transistor device provided by a first preferred embodiment of the present invention. 
         FIG. 2  is a cross-sectional view of the HV MOS transistor device taken along a line A-A′ of  FIG. 1 . 
         FIG. 3  is a cross-sectional view of a HV MOS transistor device provided by a second preferred embodiment of the present invention. 
         FIG. 4  is a schematic drawing of a portion of a layout pattern of a HV MOS transistor device provided by a third preferred embodiment of the present invention. 
         FIG. 5  is a cross-sectional view of the HV MOS transistor device taken along a line B-B′ of  FIG. 4 . 
         FIG. 6  is a schematic drawing of a portion of a layout pattern of a HV MOS transistor device provided by a fourth preferred embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 1-2 , wherein  FIG. 1  is a schematic drawing of a portion of a layout pattern of a HV MOS transistor device provided by a first preferred embodiment of the present invention and  FIG. 2  is a cross-sectional view of the HV MOS transistor device taken along a line A-A′ of  FIG. 1 . As shown in  FIGS. 1-2 , a HV MOS transistor device  100  provided by the preferred embodiment is formed on a substrate  102 , such as a silicon substrate. The substrate  102  includes a first conductivity type. A deep well region  104  including a second conductivity type is formed in the substrate  102 . The first conductivity type and the second conductivity type are complementary to each other. In the preferred embodiment, the first conductivity type is p type and the second conductivity type is n type. A plurality of shallow trench isolations (STIs)  106  for electrically isolating the HV MOS transistor device  100  from other devices and an insulating region  108  are formed in the substrate  102 . According to the preferred embodiment, the insulating region  108  includes a STI, but not limited to this. The HV MOS transistor device  100  provided by the preferred embodiment includes a gate  110  formed on the substrate  102  and covering a portion of the insulating region  108 . A body region  112  having the first conductivity type is formed in the deep well region  104 . Accordingly, the body region  112  is a p-body region. A source region  114  and a drain region  118  are formed at respective sides of the gate  110  in the substrate  102 . The source region  114  and the drain region  118  include the second conductivity type, thus are an n-source region and an n-drain region, respectively. As shown in  FIG. 2 , the n-source region  114  is formed in the p-body region  112 . Furthermore, a p-doped region  116  is formed in the p-body region  112 . The p-doped region  116  is electrically connected to the n-source region  114 . The HV MOS transistor device  100  provided by the preferred embodiment further includes an n-well region  120  (shown in  FIG. 2 ) at the drain side in the deep well region  104 . As shown in  FIG. 2 , the drain region  118  is formed in the n-well region  120 . 
     Please still refer to  FIGS. 1-2 . More important, the HV MOS transistor device  100  provided by the preferred embodiment includes a first implant region  130  formed in the substrate  102  and adjacent to the body region  112 . As shown in  FIG. 1 , the first implant region  130  includes a continuous implant region in the preferred embodiment, but not limited to this. As shown in  FIG. 2 , the source region  114  and the first implant region  130  are spaced apart from each other by the body region  112 . Furthermore, the first implant region  130  and the insulating region  108  are spaced apart from each other by the deep well region  104 . In other words, a space is formed in between the first implant region  130  and the insulating region  108 , thus the first implant region  130  is prevented from contacting the insulating region  108 . A depth D 1  of the first implant region  130  is smaller than a depth D 2  of the insulating region  108  and a depth D 3  of the body region  112 . As shown in  FIG. 2 , the gate  110  covers the first implant region  130  entirely. The first implant region  130  includes the second conductivity type and thus is an n-typed implant region. A dopant concentration of the first implant region  130  is larger than a dopant concentration of the deep well region  104 , and a dopant concentration of the source region  114  and the drain region  118  is larger than the dopant concentration of the first implant region  130 . 
     According to the HV MOS transistor device  100  provided by the first preferred embodiment, the first implant region  130  formed in the substrate  102  under the gate  110  is adjacent to the body region  112  but spaced apart from the source region  114 . Since the first implant region  130  includes the second conductivity type that is the same with the source region  114  and the drain region  118 , resistance in charge accumulation area is reduced and thus R ON  is reduced. Consequently, the R ON /BVD ratio is desirably lowered. 
     Please refer to  FIG. 3 , which is a cross-sectional view of a HV MOS transistor device provided by a second preferred embodiment of the present invention. It is noteworthy that elements the same in both of the first and second embodiments are designated by the same numerals, and details such as material choice and conductivity types concerning those elements are omitted in the interest of brevity. The difference between the first preferred embodiment and the second preferred embodiment is: The HV MOS transistor device  100  provided by the second preferred embodiment further includes a second implant region  140  formed under the insulating region  108 , and the insulating region  108  covers the second implant region  140  entirely. The second implant region  140  includes the first conductivity type and thus is a p-typed implant region. According to the preferred embodiment, the second implant region  140  is a continuous implant region, but not limited to this. For example, the second implant region  140  also can be a non-continuous implant region extending along a direction parallel with an extending direction of the insulating region  108  and interrupted by the deep well region  104 . A plurality of implant regions are even allowed to interrupt the non-continuous second implant region  140 . 
     According to the HV MOS transistor device  100  provided by the second preferred embodiment, the second implant region  140  having the conductivity type complementary to the source region  114  and the drain region  118  is formed under the insulating region  108 . The second implant region  140  provides a reduced surface field (RESURF) effect, therefore the breakdown voltage of the HV MOS transistor device  100  is efficaciously improved. In the same time, the first implant region  130  formed in the substrate  102  under the gate  110  is adjacent to the body region  112  but spaced apart from the source region  114  in preferred embodiment. As mentioned above, since the first implant region  130  includes the second conductivity type that is the same with the source region  114  and the drain region  118 , resistance in the charge accumulation area is reduced and thus R ON  is reduced. Consequently, the breakdown voltage is improved while the R ON  is reduced according to the second preferred embodiment, and thus the R ON /BVD ratio is further lowered. 
     Please refer to  FIGS. 4-5 , wherein  FIG. 4  is a schematic drawing of a portion of a layout pattern of a HV MOS transistor device provided by a third preferred embodiment of the present invention and  FIG. 5  is a cross-sectional view of the HV MOS transistor device taken along a line B-B′ of  FIG. 4 . It is noteworthy that elements the same in the first, second and third embodiments are designated by the same numerals, and details such as material choice and conductivity types concerning those elements are also omitted in the interest of brevity. As shown in  FIGS. 4-5 , the HV MOS transistor device  200  provided by the third preferred embodiment is formed on a substrate  202 . A deep well region  204  is formed in the substrate  202 . A plurality of STIs  206  for electrically isolating the HV MOS transistor device  200  from other devices and an insulating region  208  are formed in the substrate  202 . The HV MOS transistor device  200  provided by the preferred embodiment includes a gate  210  formed on the substrate  202  and covering a portion of the insulating region  208 . A body region  212  is formed in the deep well region  204 . A source region  214  and a drain region  218  are formed at respective sides of the gate  210  in the deep well region  204  in the substrate  202 . As shown in  FIG. 5 , the n-source region  214  is formed in the p-body region  212 . Furthermore, a p-doped region  216  is formed in the p-body region  212  and electrically connected to the n-source region  214 . The HV MOS transistor device  200  provided by the preferred embodiment further includes an n-well region  220  (shown in  FIG. 5 ) at the drain side in the deep well region  204 . As shown in  FIG. 5 , the drain region  218  is formed in the n-well region  220 . 
     Please refer to  FIGS. 4-5  again. More important, the HV MOS transistor device  200  provided by the preferred embodiment includes a first implant region  230  formed in the substrate  202  and adjacent to the body region  212 . As shown in  FIG. 4 , the first implant region  230  includes a continuous implant region in the preferred embodiment, but not limited to this. As shown in  FIG. 5 , the source region  214  and the first implant region  230  are spaced apart from each other by the body region  212 . Furthermore, the first implant region  230  and the insulating region  208  are spaced apart from each other by the deep well region  204 . In other words, a space is formed in between the first implant region  230  and the insulating region  208 , thus the first implant region  230  is prevented from contacting the insulating region  208 . A depth D 1  of the first implant region  230  is smaller than a depth D 2  of the insulating region  208  and a depth D 3  of the body region  212 . As shown in  FIG. 5 , the gate  210  covers the first implant region  230  entirely. The first implant region  230  includes the second conductivity type and thus is an n-typed implant region. A dopant concentration of the first implant region  230  is larger than a dopant concentration of the deep well region  204 , and a dopant concentration of the source region  214  and the drain region  218  is larger than the dopant concentration of the first implant region  230 . 
     Please still refer to  FIGS. 4-5 . According to the third preferred embodiment, the HV MOS transistor device  200  further includes a plurality of second implant regions  240  formed in the substrate  202 . The insulating region  208  surrounds the second implant regions  240  as shown in  FIGS. 4-5 . A depth D 4  of the second implant regions  240  is smaller than the depth D 2  of the insulating region  208 . Consequently, the second implant regions  240  is taken as to be formed in the insulating region  208  and the insulating region  208  isolates the second implant regions  240  from each other. Thus, a gap G is formed in between any two adjacent second implant regions  240  according to the preferred embodiment. As mentioned above, the second implant regions  240  include the first conductivity type and thus are p-typed implant regions. 
     According to the HV MOS transistor device  200  provided by the third preferred embodiment, the second implant regions  240  having the conductivity type complementary to the source region  214  and the drain region  218  are formed under the insulating region  208 . The second implant regions  240  provide a RESURF effect, therefore the breakdown voltage of the HV MOS transistor device  200  is efficaciously improved. Additionally, since the second implant regions  240  are formed in the insulating region  208  and the depth D 4  of the second implant regions  240  is smaller than the depth D 2  of the insulating region  208 , current path is shortened, and thus R ON  is reduced. In the same time, the first implant region  230  formed in the substrate  102  under the gate  210  is adjacent to the body region  212  but spaced apart from the source region  214  in preferred embodiment. As mentioned above, since the first implant region  230  includes the second conductivity type that is the same with the source region  214  and the drain region  218 , resistance in the charge accumulation area is reduced and thus R ON  is further reduced. Consequently, the breakdown voltage is improved while the R ON  is further reduced according to the third preferred embodiment, and thus the R ON /BVD ratio is even further lowered. 
     Please refer to  FIG. 6 , which is a schematic drawing of a portion of a layout pattern of a HV MOS transistor device provided by a fourth preferred embodiment of the present invention. It is noteworthy that elements the same in the aforementioned embodiments and the fourth embodiments are designated by the same numerals, and details such as material choice and conductivity types concerning those elements are also omitted in the interest of brevity. The difference between the third preferred embodiment and the fourth preferred embodiment is: The first implant region  230  includes a plurality of islanding first implant regions  230   a  and each of the islanding first implant regions  230   a  is formed corresponding to the gap G in between the two adjacent second implant regions  240  as shown in  FIG. 6 . 
     According to the HV MOS transistor device  200  provided by the fourth preferred embodiment, the second implant regions  240  provide a RESURF effect, therefore the breakdown voltage of the HV MOS transistor device  200  is efficaciously improved. As mentioned above, since the second implant regions  240  are formed in the insulating region  208  and the depth D 4  of the second implant regions  240  is smaller than the depth D 2  of the insulating region  208 , current path is shortened, and thus R ON  is reduced. In the same time, the islanding first implant regions  230   a  formed in the substrate  102  under the gate  210  are adjacent to the body region  212  but spaced apart from the source region  214  in preferred embodiment. As mentioned above, since the islanding first implant regions  230   a  include the second conductivity type that is the same with the source region  214  and the drain region  218 , resistance in the charge accumulation area is reduced and thus R ON  is further reduced. Consequently, the breakdown voltage is improved while the R ON  is further reduced according to the fourth preferred embodiment, and thus the R ON /BVD ratio is even further lowered. 
     According to the HV MOS transistor device provided by the present invention, the first implant region formed near the source region in the substrate, which is adjacent to the body region, includes the conductivity type the same with the source region and the drain region. Therefore, resistance in charge accumulation area is reduced and thus R ON  is reduced. Consequently, the R ON /BVD ratio is desirably lowered. Furthermore, by forming the second implant region(s) having the conductivity type complementary to the source/drain, the breakdown voltage is improved while the R ON  is reduced, and thus the R ON /BVD ratio is further lowered. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.