Abstract:
A circuit and method are disclosed for controlling the slew rate of the output voltage of a driver in a push-pull configuration. The circuit includes a capacitive element and a current generator circuit for generating one or more currents. The circuit further includes a switching circuit for selectively charging and discharging the capacitive element in response to an input signal, wherein the voltage across the capacitive element is a voltage signal whose edge transitions have slopes which are controlled based upon the capacitance of the capacitive element and the current level of the one or more currents. The circuit further includes a conversion circuit for converting the voltage signal into one or more current signals, the one or more current signals being used to control a pull-up device and pull-down device of the driver so that the slopes of the edge transitions of the output voltage thereof is based upon the slopes of the edge transitions of the voltage signal appearing across the capacitive element.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a circuit for controlling the slew rate of the output voltage of a driver in a push-pull configuration. 
     2. Background of the Relevant Art 
     It is important to be able to control the slew rate of the output signal of a driver so that the edge transitions of the output signal are neither too fast nor too slow, in order to ensure accurate control of the output waveform as the load connected to the driver varies. 
     In particular, for RS232 serial interfaces, for example, the load is of the ohmic-capacitive type. 
     When operating at data rates on the order of 100 kbps, it is important to be able to precisely control the slew rate of the output signal of the driver in order to ensure a desired data transmission rate. 
     A known solution for controlling the slew rate of the output signal of a driver is shown in FIG. 1, wherein the input signal Tin of the driver is input to a first positive boost circuit  1 , which boosts the signal Tin to the voltage V+ obtained from a charge pump circuit, and is also input to a second negative boost circuit  2 , which pulls the level of the signal Tin down to the level V− by inverting the voltage obtained from the charge pump circuit. 
     Two capacitors C 1  and C 2  are respectfully connected between the output signal Tout of the driver and gate terminals of a PMOS transistor P 1  and of an NMOS transistor N 1 . The gate or control electrode of transistors P 1  and N 1  are respectively connected to the output of positive boost circuit  1  and negative boost circuit  2 . Transistors P 1  and N 1  form the final stage of the known driver circuit. 
     The load, of the ohmic-capacitive type and designated by the reference numeral  3 , is driven by the output signal Tout. 
     The known driver circuit is not without its shortcomings. 
     First, in order to be able to use capacitors C 1  and C 2 , whose capacitances are not excessively high, the connection thereof between the output terminal and the gate terminal of their corresponding final stage transistor is able to exploit the Miller effect stemming from the amplification provided by final stage transistors P 1  and N 1 . Because it is impossible to provide precise control of the amplification of final stage transistors P 1  and N 1 , the control over the slew rate of output signal Tout is imprecise. 
     In operation, when the final stage transistor P 1  is on, the transistor N 1  is off. Accordingly, the capacitor C 2  that intervenes during the rising edge of the output signal Tout is subjected to a potential difference given by 
     
       
         V 2 =(V+)−Vds(P 1 )−(V−),  
       
     
     where V 2  is the voltage across capacitor C 2  and Vds(P 1 ) is the voltage between the drain terminal and the source terminal of the transistor P 1 . 
     On the contrary, in the second mode wherein the transistor P 1  is in the off state and the transistor N 1  in the on state, the capacitor C 1  is subjected to a potential difference given by 
     
       
         V 1 =(V+)−[(V−)+Vds(N 1 )],  
       
     
     where V 1  is the voltage across capacitor C 1  and Vds(N 1 ) is the voltage between the drain terminal and the source terminal of the transistor N 1 . 
     In the context of the known driver being part of an RS232 serial interface, the difference in voltage between V+ and V− is high and it is therefore necessary to use high-voltage capacitors for capacitors C 1  and C 2 . Consequently, the area occupied by the capacitors C 1  and C 2  in an integrated circuit chip substantially increases. 
     Further, the charging and discharging currents for the two capacitors C 1  and C 2  cannot be accurately controlled, since they are respectively coupled to the output of the positive and negative boost circuits  1  and  2 . 
     SUMMARY OF THE INVENTION 
     Based upon the foregoing, the aim of the present invention is to provide a circuit for controlling the slew rate of the output of a driver in a push-pull configuration which maintains the slew rate within a predetermined interval even when the temperature varies. 
     The present invention provides a circuit for controlling the slew rate of the output of a driver in a push-pull configuration having reduced area with respect to known driver circuits in order to be integrated in a wide variety of applications. 
     The circuit controls the slope of the rising and falling transitions of the output signal of a driver independently of each other. 
     The circuit controls the slew rate of the output of a driver in a push-pull configuration in which the short-circuit currents can be controlled in a simple manner, thereby eliminating the need for additional circuits. 
     The present circuit for controlling the slew rate of the output of a driver in a push-pull configuration is relatively highly reliable and relatively easy to competitively manufacture. 
     This aim and others which will become apparent hereinafter are achieved by a circuit for controlling the slew rate of the output of a driver in a push-pull configuration, including a current generator for generating a pair of currents and a switching circuit which drives the current generator and is in turn driven by an input signal of the driver. The present circuit further includes at least one capacitor that is selectively charged and discharged according to the current generator so as to generate a first signal having a predetermined slew rate. The present circuit also includes a converter circuit for converting the first signal into at least one controlled current signal for driving the final stage of the driver. The resulting output signal of the driver has a slew rate which is substantially accurately controlled and is based upon the slew rate of the first signal. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Further characteristics and advantages of the invention will become apparent from the description of a preferred embodiment of the present invention, illustrated only by way of non-limitative examples in the accompanying drawings, wherein: 
     FIG. 1 is a schematic diagram of a conventional driver having a push-pull configuration; 
     FIG. 2 is a schematic diagram of a driver according to a preferred embodiment of the present invention; and 
     FIG. 3 illustrates the timing between various signals of the circuit shown in FIG.  2 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With reference to FIG. 2, there is shown the present circuit for controlling the slew rate of the output voltage signal of a driver, generally designated by the reference numeral  10 , including an operational amplifier  11  of the non-inverting type and at least one capacitor  12  that is connected between the non-inverting terminal of operational amplifier  11  and ground. 
     Two current sources I 1  and I 2  are provided in circuit  10  that are series-connected between a reference voltage Vref and ground. A common node of current sources I 1  and I 2  is connected to the non-inverting input terminal of the operational amplifier  11 . 
     Input signal Tin drives a switch T 3 , such as a field effect transistor, that is connected in series between the two current sources I 1  and I 2 . Capacitor  12 , current sources I 1  and I 2  and switch T 3  may be viewed as a switched-capacitive circuit for generating a voltage signal having a predetermined slew rate. Input signal Tin also drives a pair of switches T 1  and T 2  that may be implemented, for example, using field effect transistors. The specific function of switches T 1  and T 2  will described in detail below. 
     The output of the operational amplifier  11  is connected to a bipolar transistor  13 . Transistor  13  has a collector terminal that is connected to the supply voltage Vdd and an emitter terminal that is connected to the inverting input terminal of the operational amplifier  11 . 
     Each current source I 1  and I 2  provides a substantially constant current level. The substantially constant current flowing through current source I 2  is preferably greater than the substantially constant current flowing through current source I 1 . 
     The emitter terminal of the transistor  13  is also connected to two current mirrors which are formed respectively by P-channel field effect transistors  14  and  15  and by N-channel field effect transistors  16  and  17 . 
     The first current mirror, formed by the transistors  14  and  15 , is connected to a third current mirror formed by N-channel field effect transistors  18  and  19 . The second current mirror, formed by the field effect transistors  16  and  17 , is connected to a fourth current mirror formed by P-channel field effect transistors  20  and  21 . Transistors  19  and  21 , connected between power supply VDD and ground, form the final stage of the driver circuit having a push-pull configuration. 
     The emitter terminal of the bipolar transistor  13  is connected at a common node E between the first current mirror and the second current mirror. A resistor R 1  and the switch T 1  are series-connected between the node E and the first current mirror. A resistor R 2  and the switch T 2  are series-connected between the node E and the second current mirror. As mentioned, input signal Tin drives the switches T 1  and T 2  and thereby controls the activation thereof. 
     The first current mirror is connected to the supply voltage Vdd, and the second current mirror is connected to ground. 
     The third current mirror, formed by the transistors  18  and  19 , is connected to a low reference voltage Vss. The supply voltage VDD (obtained by use of a charge pump circuit) is connected to the fourth current mirror formed by the field effect transistors  20  and  21 . It is understood that supply voltage VDD may be different from supply voltage Vdd shown in FIG.  2 . 
     The P-channel field effect transistor  21  and the N-channel field-effect transistor  19  form the final stage of the driver and generates output signal Tout. Output signal Tout drives an ohmic-capacitive load (not shown). 
     The operation of circuit  10  for controlling the slew rate of the output signal Tout according to the invention will be described. 
     In contrast to known driver circuits, such as the driver circuit illustrated in FIG. 1, which perform voltage-based slew rate control, circuit  10  according to the present invention converts a voltage signal having a controlled and/or predetermined slew rate into a current signal that is used to drive transistors  19  and  21  of the final stage of the driver. In this manner it is possible to obtain an output signal Tout having a substantially precisely controllable slew rate. 
     It is accordingly possible to obtain positive (rising) and negative (falling) edge transitions each having a controlled slope by selectively charging and discharging the capacitor  12  using current sources I 1  and I 2  as controlled by and/or based upon the input signal Tin. 
     The voltage VE appearing at the emitter terminal of the transistor  13  and/or at node E varies between two values V 2  and V 1 . In the preferred embodiment of the present invention, the voltage levels of V 2  and V 1  are the supply voltage Vdd and ground, respectively. It is understood that voltage levels V 1  and V 2  may instead be within a range of voltages between supply voltage Vdd and ground. 
     Designating the value of the capacitor  12  as C for the sake of simplicity, the charging and discharging of capacitor  12  may be described mathematically. The current equation for charging of capacitor  12  may be represented as 
     
       
         I 1 = C *(V 2 −V 1 )/Δ T,    
       
     
     so that the charging time of capacitor  12  may be described by the equation 
     
       
         ΔVc/Δ T =I 1 / C,    
       
     
     where ΔVc is the voltage across capacitor  12 . The current equation for discharging capacitor  12  may be represented as 
     
       
         I 1 −I 2 = C *(V 2 −V 1 )/Δ T,    
       
     
     so that the equation for discharging capacitor  12  may be represented as 
     
       
         ΔVc/Δ T =(I 1 −I 2 )/ C.    
       
     
     Accordingly, by choosing the capacitance value for capacitor C and the current levels for each current source I 1  and I 2 , it is possible to adjust and/or set the slope of the edge transitions appearing on the signal at the non-inverting input terminal of operational amplifier  11 . In other words, the slew rate of the signal appearing at the non-inverting input terminal of operational amplifier  11  may be set based upon the chosen capacitance value of capacitor C and the current levels of current sources I 1  and I 2 . The slope of each edge transition appearing at node E is substantially unchanged from the slope of the corresponding edge transition appearing at the non-inverting input terminal of operational amplifier  11  by virtue of operational amplifier  11  being connected to a voltage follower formed by transistor  13 . 
     Further, it can be seen that the charging time and discharging time for capacitor  12  may be set independently from each other. The independently controlled charge and discharge times of capacitor  12  result in the slope of the rising and falling edge transitions of the signal appearing at the non-inverting input of operational amplifier  11  to be independently controlled. 
     The state of switch T 3  determines whether capacitor  12  is being charged or discharged. In particular, when switch T 3  is closed, the charge appearing on capacitor  12  is discharged therefrom through current source I 2 . Alternatively, when switch T 3  is open, capacitor  12  is charged from current source I 1 . As can be understood, the current passing through current source I 2  is greater than the current passing through current source I 1 . 
     The voltage appearing across capacitor  12 , whose positive (rising) and negative (falling) edge transitions have predetermined slopes, is then converted into a current signal. 
     The current that flows through the resistor R 1 , designated by I R1 (t), is given by the following relation: 
     
       
         I R1 ( t )=[Vdd−Vgs( 14 )−V E ( t )]/R 1 ,  
       
     
     where Vgs( 14 ) is the gate-to-source voltage of transistor  14  and V E (t) is voltage appearing at node E shown in FIG.  2 . 
     Similarly, the current I R2 (t) that flows across the resistor R 2  is given by 
     
       
         I R2 ( t )=[V E ( t )−Vgs( 16 )]/R 2 ,  
       
     
     where Vgs( 16 ) is the gate-to-source voltage of transistor  16 . 
     The current I R1  is then mirrored in the current through transistor  15  of the first current mirror. Similarly, the current I R2  is mirrored in the current through transistor  17  of the second current mirror. These current mirror currents are then mirrored at the output of the driver in order to obtain the currents I P  and I N . The current I P  may be represented as 
     
       
         I P =I R2 ( t )* n 1 *n 2,  
       
     
     where n1 is the ratio of the size of transistor  17  to the size of transistor  16 , and n2 is the ratio of the size of transistor  21  to the size of transistor  20 . Similarly, the current I N  may be represented as 
     
       
         I N =I R1 ( t )* n 3 *n 4,  
       
     
     where n3 is the ratio of the size of transistor  15  to the size of transistor  14 , and n4 is the ratio of the size of transistor  19  to the size of transistor  18 . 
     The switches T 1  and T 2  are driven by the input signal Tin such that when input signal Tin is at the higher voltage level to turn on switch T 3 , switch T 1  is also turned on and switch T 2  is turned off, which causes current to flow through the first current mirror (transistors  14  and  15 ) and through the third current mirror (transistors  18  and  19 ) so as to sink current I N  and/or cause a falling transition on output signal Tout. Alternatively, when input signal Tin is at a lower voltage level and turns off switch T 3 , switch T 1  is turned off and switch T 2  is turned on, which causes current to flow through the second current mirror (transistors  16  and  17 ) and the fourth current mirror (transistors  20  and  21 ) so as to source current I P  and/or cause a controlled rising edge transition on output signal Tout having a controlled slope. FIG. 3 illustrates the timing waveforms for input signal Tin, intermediate signal V E , and output signal Tout. In FIG. 3, the charge and discharge times for capacitor  12  are set to be roughly the same. 
     The present circuit produces substantially tight control of the slew rate of output signal Tout without loads or in conditions involving small load capacitances, such as data transmission over coaxial cables in an RS232 interface application. 
     Moreover, the control of the slew rate by the present invention occurs mostly in the initial portions of the edge transitions due to the variation of the voltage V E  between the two levels V 1  and V 2 . 
     Since the transistors in the final stage of the driver circuit, p-channel field-effect transistor  21  and n-channel field-effect transistor  19 , have the intrinsic technology-dependent characteristic of having different capacitances between their respective gate and source terminals, it is necessary to be able to independently control the slope of the output current edge transitions in order to obtain substantially the same rise and fall times for the output voltage Tout. This is achieved by keeping unchanged the value of the capacitor  12  and by varying only the currents I 1  and I 2 . 
     For very large load capacitances, the slew rate is instead linked to the capacitive value of the load and to the short-circuit currents that can be controlled by selecting the dimensions of the current mirrors and of IR 1  and IR 2 . This is because the variation in the voltage VE from the level V 1  to the level V 2  occurs in a much shorter period of time relative to the time the output signal Tout transitions from the value VSS to VDD. 
     In practice it has been observed that the circuit  10  according to the present invention allows for substantially tight control of the slew rate of the output signal Tout using parameters which can be modified easily and are highly precise. 
     Another advantage of the circuit  10  according to the invention is the fact that it is possible to control the short-circuit current very easily, thus eliminating the drawbacks arising from the use of additional circuits for controlling the short-circuit current. 
     Additionally, the use of a single capacitor  12  for controlling slew rate results in a reduced area on an integrated circuit chip relative to known solutions, thereby allowing better integration of circuit  10  in existing applications. 
     It is understood that circuit  10  is adapted for use not only in an RS232 interface but also in applications where it is necessary to drive the final stage of a driver having field-effect transistors in a push-pull configuration. 
     The circuit thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. It is understood that the components of circuit  10  may be replaced with other technically equivalent elements. It is also understood that the components of circuit  10  may have a wide variety of values and/or dimensions, so long as they are compatible with the specific operation described above.