Abstract:
Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to circuit board structures and fabrication methods thereof, and more particularly, to a circuit board structure without a core and a fabrication method thereof. 
         [0003]    2. Description of Related Art 
         [0004]    As electronic industry is ever-developing, a multilayer circuit board having a plurality of active elements, passive elements and circuits is provided to meet requirements of packaging for high integration and microminiaturization of a semiconductor package. More usable layout space of the multilayer circuit board in a limited area is obtained by interlayer connection technology so as to satisfy the requirements of high density of integrated circuit. A build-up method is disclosed in prior art to improve precision of the layout of a multilayer circuit board. The method comprises the steps of: Providing a core board having a plurality of inner circuit layers on the upper side and the lower side of the core board and conductive holes through the core board to connect electrically the inner circuit layers; stacking a plurality of dielectric layers and circuit layers alternately on upper and lower surfaces of the core board and forming conductive vias in the dielectric layers to establish electrical connection between the circuit layers. 
         [0005]    Referring to  FIG. 1A  to  FIG. 1H , there are shown schematic views of a process of fabricating a multiplayer circuit board according to the prior art. 
         [0006]    As shown in  FIG. 1A , a copper-coated laminated (CCL) core  100  with metallic thin layers  101  is provided, and a plurality of holes  102  are formed in the core  100  by drilling. 
         [0007]    As shown in  FIG. 1B , metallic layers  103  are formed on the surface of the metallic thin layers  101  and walls of the holes  102 . 
         [0008]    As shown in  FIG. 1C , plated-through holes (PTH)  102   a  are formed by filling the holes  102  with conducting or non-conducting stuffing materials  11 , such as insulating ink, copper-containing conductive paste or the like, so as to enable electrical conduction between the upper and lower metallic layers  103  on the core  100 . 
         [0009]    As shown in  FIG. 1D , the surfaces of the metallic layers  103  flatten out after a surplus portion of the stuffing material  11  has been removed by a scrubbing process. 
         [0010]    As shown in  FIG. 1E , a circuit patterning process is performed on the metallic thin layers  101  and the metallic layers  103  on the core  100 , so as to finalize a substrate  10  with inner circuit layers  104  formed on two opposing sides of the substrate  10 , respectively. 
         [0011]    As shown in  FIG. 1F , dielectric layers  12  are formed on the inner circuit layers  104  formed on upper and lower surfaces of the substrate  10 , and a plurality of vias  120  are formed in the dielectric layers  12  by laser drilling. 
         [0012]    As shown in  FIG. 1G , conductive layers  13  are formed on the surface of the dielectric layers  12  and the vias  120 . Resist layers  14  are formed on the conductive layers  13 . Opening regions  140  which expose a portion of the conductive layers  13  to the outside are formed in the resist layers  14  to allow an electroplating process to be performed. Circuit layers  15  are formed on the conductive layers  13  exposed from the opening regions  140  by the electroplating process, and conductive vias  151  are formed in the vias  120  such that the circuit layers  15  are electrically connected to the inner circuit layers  104 . 
         [0013]    As shown in  FIG. 1H , a multilayer circuit board is formed by removing the conductive layers  13  and the resist layers  14  thereon and repeating the steps of the formation of the dielectric layers and circuit layers of the  FIG. 1F  and  FIG. 1G . 
         [0014]    However, the manufacturing process of said multiplayer circuit board comprises the steps of providing the core  100  with the metallic thin layers  101  thereon, forming the plurality of plated-through holes  102   a  in the core  100 , and forming the inner circuit layers  104  on the surface of the core  100  to thereby require operations, such as drilling, plugging, and scrubbing, which render the manufacturing process complicated. 
         [0015]    In addition, the diameter of the plated-through holes  102   a  formed by circuit-electroplating in the substrate  10  is about 100 μm above and the diameter of the conductive vias  151  formed by circuit-electroplating in the dielectric layers  12  is around 50 μm. Therefore the structure of the plating-through holes  102   a  occupies more layout space than the conductive vias  151  to the detriment of formation of a fine-pitch circuit structure. 
         [0016]    Moreover, the dielectric layers  12  are composed of prepreg. The dielectric layers  12  are formed on the fine-pitch inner circuit layers  104  of the substrate  10 . However, it is difficult to stuff the prepreg into the space between the circuits in the inner circuit layers  104 . Hence, the dielectric layers  12  are not each sufficiently bonded to the substrate  10  and thus gaps are created therebetween, and in consequence the dielectric layers  12  are detachable from the substrate  10  during a follow-up process. 
         [0017]    Furthermore, the multilayer circuit board is unnecessarily thick to the detriment of miniaturization, because the core  100  occupies most of the substrate  10 . 
         [0018]    Therefore, it is imperative to provide a multilayer circuit board and a fabrication method thereof so as to overcome the above-described drawbacks, such as small layout density, the need for formation of the dielectric layers, and excessive thickness of the circuit board. 
       SUMMARY OF THE INVENTION 
       [0019]    Accordingly, an objective of the present invention is to provide a circuit board and a method for fabricating the circuit board structure so as to dispense with a core board and thus facilitate miniaturization. 
         [0020]    Another objective of the present invention is to provide a circuit board structure and a method for fabricating the same so as to stuff dielectric layers into a gap between circuits for preventing delamination of the circuit board structure. 
         [0021]    Yet another objective of the present invention is to provide a circuit board structure and a method for fabricating the same so as to increase layout density of the circuit board. 
         [0022]    In order to attain the above and other objectives, the present invention provides a first dielectric layer; a first circuit layer formed in the first dielectric layer and exposed from the surface of the first dielectric layer; a second dielectric layer formed on the first dielectric layer and the first circuit layer; and a second circuit layer formed on the second dielectric layer, wherein a plurality of first conductive vias are formed in the second dielectric layer so as to electrically connect to the first circuit layer. 
         [0023]    In the above-described structure, further comprises a first solder mask formed on the first circuit layer and the second dielectric layer-free side of the first dielectric layer, wherein a plurality of openings are formed in the first solder mask so as to expose a portion of the first circuit layer to thereby allow the exposed portion of the first circuit layer to be formed into a plurality of first electrical connecting pads. In another embodiment, the circuit board structure further comprises a second solder mask formed on the third dielectric layer and the second circuit layer, and a plurality of openings are formed in the second solder mask so as to expose a portion of the second circuit layer to thereby allow the exposed portion of the second circuit layer to be formed into a plurality of second electrical connecting pads. In yet another embodiment, the circuit board structure further comprises a third dielectric layer formed on the surface of sides of the second dielectric layer and the second circuit layer, wherein the second circuit layer is exposed from the surface of the third dielectric layer, a second solder mask formed on the third dielectric layer and the second circuit layer, wherein a plurality of openings are formed in the second solder mask so as to expose a portion of the second circuit layer to thereby allow the exposed portion of the second circuit layer to be formed into a plurality of second electrical connecting pads. 
         [0024]    In the above-described structure, further comprises a treatment layer formed on the first electrical connecting pads, wherein the treatment layer is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). 
         [0025]    In another embodiment, the present invention further provides a circuit board structure comprising a build-up layer assembly formed on the third dielectric layer and the second circuit layer, wherein the build-up layer assembly includes at least a fourth dielectric layer, a third circuit layer and a fifth dielectric layer formed on the fourth dielectric layer, and a plurality of second conductive vias formed in the fourth dielectric layer and electrically connected to the second circuit layer and the third circuit layer, wherein a plurality of third electrical connecting pads are formed on the third circuit layer which is situated on an outermost part of the build-up layer assembly, and a solder mask is formed on the outermost part of the build-up layer assembly and the solder mask is further formed with a plurality of openings so as for the third electrical connecting pads to be exposed from the openings, respectively. 
         [0026]    In the above-described structure, further comprises a treatment layer formed on the first electrical connecting pads and the third electrical connecting pads, wherein the treatment layer is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). 
         [0027]    The present invention further provides a method for fabricating a circuit board, comprising the steps of: providing a carrier board; forming a first circuit layer on the surface of the carrier board; forming a first dielectric layer on the carrier board and the first circuit layer in a manner that the first circuit layer is exposed from the surface of the first dielectric layer; forming a second dielectric layer on the first circuit layer and the first dielectric layer; forming a second circuit layer on the second dielectric layer, and forming a first conductive via in the second dielectric layer so as to electrically connect to the first circuit layer; and removing the carrier board so as to expose the first dielectric layer and the first circuit layer. 
         [0028]    In the above-described method, the fabricating process of forming the first circuit layer further comprising the steps of: forming a first conductive layer on the carrier board; forming a first resist layer on the first conductive layer, and forming a first opening region in the first resist layer; forming the first circuit layer in the first opening region; and removing the first conductive layer and the first resist layer thereon. 
         [0029]    In the above-described method, the fabricating process of forming the second circuit layer further comprising the steps of: forming a metallic layer on the second dielectric layer; forming a plurality of vias to penetrate the second dielectric layer and the metallic layer; forming a second conductive layer on the first circuit layer of the metallic layer, the vias and walls of the vias; forming an electroplating metallic layer on the second conductive layer; forming a second resist layer on the electroplating metallic layer, followed by forming a plurality of second opening regions to penetrate the second resist layer so as to expose correspondingly the portion of the electroplating metallic layer; removing the second conductive layer, the metallic layer, and the electroplating metallic layer thereon in the second opening region to form the second circuit layer, and forming the first conductive via in the via; and removing the second resist layer. 
         [0030]    In another embodiment, the step of forming the second circuit layer further comprises the sub-steps of: forming a metallic layer on the second dielectric layer; forming a plurality of vias to penetrate the second dielectric layer and the metallic layer; forming a second conductive layer on the first circuit layer of the metallic layer, the vias and walls of the vias; forming a second resist layer on the second conductive layer, followed by forming a plurality of second opening regions to penetrate the second resist layer so as to expose a portion of the electroplating metallic layer; forming a second resist layer on the electroplating metallic layer, followed by forming a plurality of second opening regions to penetrate the second resist layer so as to expose correspondingly the portion of the second conductive layer, wherein the portion of the second conductive layer corresponds to the via; forming the second circuit layer on the second conductive layer of the second opening region, and forming the first conductive via in the via; and removing the second conductive layer, metallic layer, and the resist layer thereon. 
         [0031]    In the above-described method, further comprises the steps of: forming a first solder mask on the first circuit layer and the second dielectric layer-free side of the first dielectric layer, forming a plurality of openings in the first solder mask so as to expose a portion of the first circuit layer to thereby allow the exposed portion of the first circuit layer to be formed into a plurality of first electrical connecting pads; forming a second solder mask on the third dielectric layer and the second circuit layer, and forming a plurality of openings in the second solder mask so as to expose a portion of the second circuit layer to thereby allow the exposed portion of the second circuit layer to be formed into a plurality of second electrical connecting pads. In another embodiment, a third dielectric layer is formed on the surface of sides of the second dielectric layer and the second circuit layer such that the second circuit layer is exposed from the surface of the third dielectric layer. Then, a second solder mask is formed on the third dielectric layer and the second circuit layer, and a plurality of openings are formed in the second solder mask to expose portions of the second circuit layer so as for the exposed portions of the second circuit layer to function as a plurality of second electrical connecting pads, respectively. 
         [0032]    In another embodiment, the method further comprises the step of forming a treatment layer on the second electrical connecting pads, wherein the treatment layer is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). 
         [0033]    The above-described method further comprises the step of forming a build-up layer assembly on the third dielectric layer and the second circuit layer, wherein the build-up layer assembly includes at least a fourth dielectric layer, a third circuit layer and a fifth dielectric layer formed on the fourth dielectric layer, and a plurality of second conductive vias formed in the fourth dielectric layer and electrically connected to the second circuit layer and the third circuit layer, wherein a plurality of third electrical connecting pads are formed on the third circuit layer which is situated on an outermost part of the build-up layer assembly, and a solder mask is formed on the outermost part of the build-up layer assembly and the solder mask is further formed with a plurality of openings so as for the third electrical connecting pads to be exposed from the openings, respectively. 
         [0034]    In another embodiment, the method further comprises the step of forming a treatment layer on the third electrical connecting pads, wherein the treatment layer is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). 
         [0035]    In view of the above, the method of the present invention essentially comprises the steps of: forming the non-solidifying first dielectric layer on the upper and lower surface of the carrier board at first, stuffing the first dielectric layer into the gap of the first circuit layer to expose the first circuit layer from the first dielectric layer, forming a second dielectric layer with prepreg on the first dielectric layer and the first circuit layer to embed the rough surface of the second dielectric layer in the non-solidifying first dielectric layer, and solidifying the first dielectric layer and the second dielectric layer so as to enhance bonding strength and prevent delamination, then forming a second circuit layer on the second dielectric layer, forming a first conductive via in the second dielectric layer to electrically connect to the first circuit layer, and removing the carrier board to form a circuit board structure. Therefore, the present invention discloses using a circuit board structure without a known thick core occupying the conductive holes so as to increase the layout density and decrease the thickness of the circuit board structure. Furthermore, the present invention overcomes the problems confronting the prior art, that is, it is difficult to stuff a dielectric layer into gaps between circuit layers of a conventional circuit board with a high layout density, which precludes fabrication of conventional circuit boards with high layout density. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0036]      FIGS. 1A to 1H  are schematic views of a conventional flip-chip circuit board structure; 
           [0037]      FIGS. 2A to 2R  are schematic views of a circuit board structure and a fabrication method thereof in a first embodiment according to the present invention, wherein FIG.  2 Q′ shows another embodiment of  FIG. 2Q ; 
           [0038]      FIGS. 3A to 3C  are schematic views of a circuit board structure and a fabrication method thereof in a second embodiment according to the present invention; and 
           [0039]      FIGS. 4A to 4D  are schematic views of a circuit board structure and a fabrication method thereof in a third embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0040]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. 
         [0041]      FIGS. 2A to 2R  are schematic views of a circuit board structure and a fabrication method thereof in a first embodiment according to the present invention. 
         [0042]    As shown in  FIG. 2A , a carrier board  20 , such as an insulating board or ceramic board, is provided. 
         [0043]    As shown in  FIG. 2B , a first conductive layer  21   a  is formed on the carrier board  20 . 
         [0044]    As shown in  FIG. 2C , a first resist layer  22   a  is formed on the first conductive layer  21   a , and a first opening region  220   a  is formed in the first resist layer  22   a.    
         [0045]    As shown in  FIG. 2D , a first circuit layer  23   a  is formed in the first opening region  220   a  by an electroplating process. 
         [0046]    As shown in  FIG. 2E , the first conductive layer  21   a  and the first resist layer  22   a  thereon are removed from the carrier board  20  to expose the first circuit layer  23   a  and the carrier board  20 . 
         [0047]    As shown in  FIG. 2F , a first dielectric layer  24   a  in a liquid state is formed on the carrier board  20  and the first circuit layer  23   a . Hence, the first dielectric layer  24   a  could be stuffed into circuit gaps of the first circuit layer  23   a  so as to prevent interstice which may otherwise occur because of incomplete filling. Then, the first dielectric layer  24   a  sets slightly but does not completely harden. The first circuit layer  23   a  is exposed from the first dielectric layer  24   a.    
         [0048]    As shown in  FIG. 2G , a second dielectric layer  24   b  comprising prepreg is formed on the first dielectric layer  24   a  and the first circuit layer  23   a , then the first dielectric layer  24   a  is heated up until hardened such that the first dielectric layer  24   a  is coupled to the rough surface of the second dielectric layer  24   b.    
         [0049]    As shown in  FIG. 2H , a metallic layer  25  is formed on the second dielectric layer  24   b . In another embodiment, by combining the steps illustrated with  FIGS. 2G and 2H , the second dielectric layer  24   b  made of prepreg and laminated thereto with the metallic layer  25  is formed on the first dielectric layer  24   a  and the first circuit layer  23   a  so as to simplify the fabrication process. 
         [0050]    As shown in  FIG. 2I , a plurality of vias  240  are formed to penetrate the second dielectric layer  24   b  and the metallic layer  25  so as to expose a portion of the first circuit layer  23   a.    
         [0051]    As shown in  FIG. 2J , a second conductive layer  21   b  is formed on the metallic layer  25 , walls of the vias  240 , and the exposed portion of the first circuit layer  23   a.    
         [0052]    As shown in  FIG. 2K , an electroplating metallic layer  26  is formed on the second conductive layer  21   b.    
         [0053]    As shown in  FIG. 2L , a second resist layer  22   b  is formed on the electroplating metallic layer  26 , and a plurality of second opening regions  220   b  are formed to penetrate the second resist layer  22   b  to correspondingly expose a portion of the electroplating metallic layer  26 . 
         [0054]    As shown in  FIG. 2M , the electroplating metallic layer  26 , the second conductive layer  21   b , and the metallic layer  25  are removed from the second opening regions  220   b , and the second circuit layer  23   b  is formed on the second dielectric layer  24   b . Then, first conductive vias  230   b  are formed in the vias  240 , respectively, so as for the second circuit layer  23   b  to be electrically connected to the first circuit layer  23   a.    
         [0055]    As shown in  FIG. 2N , the second resist layer  22   b  is removed to expose the second dielectric layer  24   b  and the second circuit layer  23   b , wherein the second circuit layer  23   b  is fabricated by an etching process. 
         [0056]    As shown in  FIG. 2O , the carrier board  20  is removed to divide the circuit board structure into two circuit board structures  2  so as to expose the first dielectric layer  24   a  and the first circuit layer  23   a . The present invention is hereunder illustrated and exemplified by single said circuit board structure  2   
         [0057]    As shown in  FIG. 2P , the first conductive layer  21   a  is removed form the surface of the exposed first circuit layer  23   a.    
         [0058]    As shown in FIGS.  2 Q and  2 Q′, a first solder mask  27   a  is formed on the first circuit layer  23   a  and the second dielectric layer-free side of the first dielectric layer  24   a . A plurality of openings  270   a  are formed in the first solder mask  27   a  to expose portions of the first circuit layer  23   a  so as for the exposed portions of the first circuit layer  23   a  to function as a plurality of first electrical connecting pads  231   a , respectively. A second solder mask  27   b  is formed on the second dielectric layer  24   b  and the second circuit layer  23   b , and a plurality of openings  270   b  are formed in the second solder mask  27   b  to expose portions of the second circuit layer  23   b  so as for the exposed portions of the second circuit layer  23   b  to function as a plurality of second electrical connecting pads  231   b , respectively, as shown in  FIG. 2Q . In another embodiment, a third dielectric layer  24   c  is formed on the second dielectric layer  24   b  and the second circuit layer  23   b , and the second circuit layer  23   b  is exposed from the third dielectric layer  24   c . Then, a second solder mask  27   b  is formed on the third dielectric layer  24   c  and the second circuit layer  23   b , and the plurality of openings  270   b  are formed in the second solder mask  27   b  to expose portions of the second circuit layer  23   b  so as for the exposed portions of the second circuit layer  23   b  to function as a plurality of second electrical connecting pads  231   b , respectively, as shown in FIG.  2 Q′. The present invention is hereunder illustrated and exemplified by the structure shown in  FIG. 2Q . 
         [0059]    As shown in  FIG. 2R , a treatment layer  28  is formed on the first electrical connecting pads  231   a  and the second electrical connecting pads  231   b , and the treatment layer  28  is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). The first electrical connecting pads  231   a  are electrically connected (not shown) to a semiconductor chip through solder bumps, or conductive wires. 
         [0060]    The present invention further provides a circuit board structure, comprising: a first dielectric layer  24   a ; a first circuit layer  23   a  formed in the first dielectric layer  24   a  and exposed from the first dielectric layer; a second dielectric layer  24   b  formed on the first dielectric layer  24   a  and the first circuit layer  23   a ; and a second circuit layer  23   b  formed on the second dielectric layer  24   b , wherein a plurality of first conductive vias  230   b  are formed in the second dielectric layer  24   b  so as for the second circuit layer  23   b  to be electrically connected to the first circuit layer  23   a.    
         [0061]    The above-described circuit board structure further comprises a first solder mask  27   a  formed on the first circuit layer  23   a  and the second dielectric layer-free side of the first dielectric layer  24   a , wherein the plurality of openings  270   a  are formed in the first solder mask  27   a  to expose portions of the first circuit layer  23   a  so as for the exposed portions of the first circuit layer  23   a  to function as the plurality of first electrical connecting pads  231   a , respectively. In another embodiment, a second solder mask  27   b  is formed on the second dielectric layer  24   b  and the second circuit layer  23   b , and the plurality of openings  270   b  are formed in the second solder mask  27   b  to expose portions of the second circuit layer  23   b  so as for the exposed portions of the second circuit layer  23   b  to function as the plurality of second electrical connecting pads  231   b , respectively. 
         [0062]    In yet another embodiment, the third dielectric layer  24   c  is formed on the second dielectric layer  24   b  and the second circuit layer  23   b , wherein the second circuit layer  23   b  is exposed from the third dielectric layer  24   c . Then, the second solder mask  27   b  is formed on the third dielectric layer  24   c  and the second circuit layer  23   b , wherein the plurality of openings  270   b  are formed in the second solder mask  27   b  to expose portions of the second circuit layer  23   b  so as for the exposed portions of the second circuit layer  23   b  to function as the plurality of second electrical connecting pads  231   b , respectively. 
         [0063]    The above-described circuit board structure further comprises a treatment layer  28  formed on the first electrical connecting pads  231   a  and the second electrical connecting pads  231   b , and the treatment layer  28  is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). 
         [0064]      FIGS. 3A to 3C  are schematic views of a fabrication method of the circuit board structure in a second embodiment according to the present invention. Unlike the first embodiment, the second circuit layer  23   b  of the second embodiment is fabricated by electroplating process. 
         [0065]    As shown in  FIG. 3A , the structure shown in  FIG. 2J  is provided first. A second resist layer  22   b  is formed on the second conductive layer  21   b , and a plurality of second opening regions  220   b  are formed to penetrate the second resist layer  22   b  and expose portions of the second conductive layer  21   b , respectively, wherein the second opening regions  220   b  corresponds in position to the vias  240 . 
         [0066]    As shown in  FIG. 3B , a second circuit layer  23   b  is formed on the second conductive layer  21   b  in the second opening regions  220   b , and a first conductive via is formed in the via  240 . 
         [0067]    As shown in  FIG. 3C , the second resist layer  22   b , the second conductive layer  21   b  and the metallic layer  25  are removed to expose the second dielectric layer  24   b  and the second circuit layer  23   b . The subsequent steps of the method start from the disclosure in  FIG. 2O  and therefore are omitted for the sake of brevity. 
         [0068]      FIGS. 4A to 4D  are schematic views of a fabrication method of the circuit board structure in a third embodiment according to the present invention. Unlike the second embodiment, a build-up layer assembly in the third embodiment is formed on the second dielectric layer  24   b  and the second circuit layer  23   b.    
         [0069]    As shown in  FIG. 4A , a circuit board such as the structure shown in  FIG. 2N  is provided. First, a third dielectric layer  24   c  is formed on the second dielectric layer  24   b  and the second circuit layer  23   b , and expose to the second circuit layer  23   b . Then, a build-up layer assembly  29  is formed on the third dielectric layer  24   c  and the second circuit layer  23   b  by the above-described etching process or electroplating process. The build-up layer assembly  29  includes at least a fourth dielectric layer  291 , a third circuit layer  292  and a fifth dielectric layer  293  formed on the fourth dielectric layer  291 , and a plurality of second conductive vias  294  formed in the fourth dielectric layer  291 , wherein the second conductive vias  294  electrically connect to the second circuit layer  23   b  and the third circuit layer  292 . 
         [0070]    As shown in  FIG. 4B , the carrier board  20  is removed to expose the first dielectric layer  24   a  and the first circuit layer  23   a , and the first conductive layer  21   a  exposed on the surface of the first circuit layer  23   a  is removed. 
         [0071]    As shown in  FIG. 4C , a first solder mask  27   a  is formed on the first circuit layer  23   a  and the second dielectric layer-free side of the first dielectric layer  24   a , and the openings  270   a  are formed in the first solder mask  27   a  to expose a portion of the first circuit layer  23   a  so as to form a plurality of first electrical connecting pads  231   a . A plurality of third electrical connecting pads  295  are formed on the third circuit layer  292  which is situated on the outermost part of the build-up layer assembly  29 . A second solder mask  27   b  is formed on the outermost part of the build-up layer assembly  29 . The second solder mask  27   b  is further formed with the openings  270   b  therein so as for the third electrical connecting pads  295  to be exposed from the openings  270   b , respectively. 
         [0072]    As shown in  FIG. 4D , a treatment layer  28  is formed on the first electrical connecting pads  231   a  and the third electrical connecting pads  295 , and the treatment layer  28  is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). The first electrical connecting pads  231   a  are electrically connected (not shown) to a semiconductor chip through solder bumps or conductive wires. 
         [0073]    A circuit board structure of present invention is provided, which comprising: a first dielectric layer  24   a ; a first circuit layer  23   a  formed in the first dielectric layer  24   a  and exposed to outside; a second dielectric layer  24   b  formed on the first dielectric layer  24   a  and the first circuit layer  23   a ; and a second circuit layer  23   b  formed on the second dielectric layer  24   b , wherein a plurality of first conductive vias are formed in the second dielectric layer  24   b  to electrically connect to the first circuit layer  23   a.    
         [0074]    In the above-described structure, a first solder mask  27   a  is formed on the first circuit layer  23   a  and the second dielectric layer-free side of the first dielectric layer  24   a , wherein the openings  270   a  are formed in the first solder mask  27   a  so as to expose a portion of the first circuit layer  23   a  to thereby allow the exposed portion of the first circuit layer  23   a  to be formed into a plurality of first electrical connecting pads  231   a . Then a third dielectric layer  24   c  is form on the second dielectric layer  24   b  and the second circuit layer  23   b  but exposes to the second circuit layer  23   b . A build-up layer assembly  29  is formed on the second dielectric layer  24   b  and the second circuit layer  23   b . The build-up layer assembly  29  includes at least a fourth dielectric layer  291 , a third circuit layer  292  and a fifth dielectric layer  293  formed on the fourth dielectric layer  291 , and a plurality of second conductive vias  294  formed in the fourth dielectric layer  291  and electrically connected to the second circuit layer  23   b  and the third circuit layer  292 , wherein a plurality of third electrical connecting pads  295  are formed on the third circuit layer  292  which is situated on the outermost part of the build-up layer assembly  29 . A second solder mask  27   b  is formed on the outermost part of the build-up layer assembly  29 . The second solder mask  27   b  is further formed with the openings  270   b  therein, so as for the third electrical connecting pads  295  to be exposed from the openings  270   b , respectively. 
         [0075]    A treatment layer  28  is formed on the first electrical connecting pads  231   a  and the third electrical connecting pads  295 , and the treatment layer  28  is made of tin (Sn), lead (Pb), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), nickel (Ni), palladium (Pd), or gold (Au). 
         [0076]    Therefore, the method of the present invention essentially comprises the steps of forming the first circuit layer on the upper and lower surface of the carrier board at first, next forming the liquid first dielectric layer on the carrier board with the first circuit layer, then stuffing the first dielectric layer into the gap of the first circuit layer to prevent form formation of voids, wherein the first dielectric layer exposes the first circuit layer. After that, the present invention further comprises the steps of forming a second dielectric layer on the first dielectric layer (a non-solidifying material) and the first circuit layer, then pressing the second dielectric layer composed of prepreg on the first circuit layer and the first dielectric layer to embed the rough surface of the second dielectric layer in the non-solidifying first dielectric layer, and solidifying the first dielectric layer and the second dielectric layer so as to enhance bonding strength and prevent delamination. Afterward, the present invention further comprises the steps of forming a second circuit layer on the second dielectric layer, next forming a first conductive via in the second dielectric layer to electrically connect to the first circuit layer, then removing the carrier board to form a circuit board structure. Therefore, the circuit board structure without a known thick core occupying the conductive holes could increase the layout density and decrease thickness of the structure. Furthermore, the present invention overcomes the prior problem that it is not easy to stuff the dielectric layer composed of prepreg into the gap of the circuit layer with high layout density so as to fabricate the circuit boards with high layout density. 
         [0077]    The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. All modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.