Abstract:
A fabrication method and a test method for a light emitting display that together produce a pixel portion of the display by fabricating pixel circuits, testing the pixel circuits, and subsequently fabricating light emitting diodes is disclosed.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of Korean Patent Application No. 2005-40310, filed on May 13, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a fabrication method and a test method for a light emitting display, more specifically to a fabrication method for a light emitting display that fabricates a pixel portion simply and conveniently using the results of testing the pixel portion in the fabrication method. 
     2. Description of the Related Technology 
     A light emitting display may be an organic light emitting display using an organic light emitting diode or may be an inorganic light emitting display using an inorganic light emitting diode. The organic light emitting diode is named as an OLED, and includes an organic light emitting layer located between an anode electrode and a cathode electrode. Within the light emitting layer electrons and holes recombine and release light of a desired color. The inorganic light emitting diode is an LED, and includes an inorganic light emitting layer. As one example, a light emitting layer is made up of a PN-junction semi-conductor, as opposed to an inorganic light emitting diode. 
       FIG. 1  illustrates a structure of a light emitting display according to the conventional art. Referring to  FIG. 1 , the light emitting display comprises a pixel portion  10 , a data driver  20 , a scan driver  30  and a power supply unit. 
     The pixel portion  10  comprises a plurality of pixels  11 , a plurality of scanning lines S, S 2  . . . Sn, a plurality of data lines D 1 , D 2  . . . Dm, a plurality of first power source lines ELVdd, and a plurality of second power source lines ELVss. The pixel  11  comprises a pixel circuit and a light emitting diode, wherein the pixel circuit is connected with a scanning line S, S 2  . . . Sn, a data line D 1 , D 2  . . . Dm and a first power source line ELVdd, receives a data signal and a first supply voltage, generates a current corresponding to the data signal and then transmits the data signal to a light emitting diode. The light emitting diode has a first electrode and a second electrode. When a current flows into the second electrode from the first electrode, the diode emits light in accordance with a brighness corresponding to the amount of current. The first electrode of the light emitting diode is connected with the pixel circuit and the second electrode of the light emitting diode is connected with the second power source line ELVss. Herein, the second power source line is expressed as a plurality of wires, but is represented equivalently. 
     A data driver  20  is connected with a plurality of data lines D 1 , D 2  . . . Dm, and transmits a data signal to the pixel portion  10 . 
     The scan driver  30  is connected with a plurality of scanning lines S 1 , S 2  . . . Sn, and transmits a scanning signal to the pixel portion  10 . 
     The power supply unit transmits the first supply voltage through a first wire L 1 , and transmits a second supply voltage through a second wire L 2 . The first wire L 1  is connected with the first power source line ELVdd and transmits the first supply voltage each pixel  11  of the pixel portion  10  through the first power source line ELVdd, and the second L 2  is connected with the second power source line ELVss and transmits the second supply voltage to each pixel  11  of the pixel portion  10  through the second power source line ELVss. Accordingly, the first supply voltage and the second supply voltage are respectively transmitted to each pixel  11  of the pixel portion  10  and thus the pixel portion  10  is driven. 
     The light emitting display in accordance with the conventional art comprises a plurality of pixels, which are connected with a plurality of wires on a substrate. TFT&#39;s are generally formed before forming the light emitting diodes of each pixel. Before forming the light emitting diodes, an electric state of the substrate is identified by transmitting an electrical signal through a wire and then sensing a corresponding output signal. If the electric state seems to be in order after the identifying process, the light emitting display is completed by forming the light emitting diodes. 
     However, a light emitting display in accordance with the conventional art cannot test individual pixels without forming the light emitting diodes. Particularly, there has been a problem that in order to enhance the picture quality of a light emitting display, a number of transistors are formed in each pixel, and a transmission path of a signal in accordance with a connection of each transistor is complicated and thus a test gets more difficult. 
     SUMMARY OF CERTAIN INVENTIVE ASPECTS 
     Accordingly, a fabrication method and a test method for a light emitting display that is able to test a light emitting display easily is presented. 
     One embodiment is a method of manufacturing a light emitting display. The method includes forming at least one pixel circuit, the pixel circuit including a thin film transistor, a capacitor connected to the thin film transistor, and a resistor connected to the thin film transistor. The method also includes forming a scanning line, a data line and a first power source line, where the scanning line, the data line, and the first power source line are each connected to the pixel circuit. The method also includes testing the pixel circuit by supplying a signal to the pixel circuit and measuring a response, forming an anode electrode for a light emitting diode, and removing the resistor, where forming the anode and removing the resistor are results of one or more common manufacturing steps. 
     Another embodiment is a method of manufacturing a pixel for a light emitting display, the method including forming a pixel circuit configured to provide a current to an output, where the amount of current corresponds to a pixel circuit input signal, forming a resistor connected to the output and to a signal line, determining the operational condition of the pixel circuit, and forming a light emitting diode so as to be connected to the pixel circuit output, where the resistor is removed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and/or other aspects and advantages will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings of which: 
         FIG. 1  is a schematic view which illustrates a structure of a light emitting display according to the conventional art; 
         FIG. 2  is a schematic view which illustrates an embodiment of a pixel portion in a state of not having the light emitting diodes formed; 
         FIG. 3  is a schematic view which illustrates another embodiment of a pixel portion in a state of not having the light emitting diodes formed; 
         FIG. 4  is a schematic view which illustrates another embodiment of a pixel portion in a state of not having the light emitting diodes formed; 
         FIGS. 5   a  through  5   c  are layout views which illustrate a fabrication process of the pixel portion depicted in  FIG. 2 ; and 
         FIG. 6  is a flowchart which illustrates a testing process of the pixel portion depicted in  FIG. 5 . 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The following Examples are given for the purpose of illustration only and are not intended to limit the scope of this invention. 
     Hereinafter, embodiments will be described with reference to the accompanying drawings. Herein, when a first element is connected to a second element, the first element may be directly connected to the second element or may be indirectly connected to the second element via a third element. Further, irrelative elements are omitted for clarity. Also, like reference numerals refer to like elements throughout. 
       FIG. 2  illustrates a first exemplary embodiment of a pixel portion having a state that the light emitting diodes are not yet formed. As shown in  FIG. 2 , parts of a pixel are seen and a pixel circuit of 3×3 size is shown. Referring to  FIG. 2 , a plurality of scanning lines S 1 , S 2 , S 3  are arranged in a row direction, and a plurality of data lines D 1 , D 2 , D 3  and a plurality of first power source lines ELVdd are arranged in a column direction. Furthermore, the scanning lines S 1 , S 2 , S 3 , the data lines D 1 , D 2 , D 3 , and the first power source lines ELVdd are each connected with a pixel circuit. 
     Each pixel circuit has a first transistor M 1 , a second transistor M 2  and a capacitor Cst, where the first transistor M 1  and the second transistor M 2  are PMOS transistors and have a source, a drain and a gate. The source and the drain of each transistor are electrically substantially identical, and any one of the source and the drain can be named as a first electrode and the other can be named as a second electrode. In addition, the capacitor Cst has a first terminal and a second terminal. For the simplified explanation, a first pixel circuit through a ninth pixel circuit is respectively named from left and to right and from up and to down. A structure of the pixel circuit will be explained using the first pixel circuit as follows. 
     A source of the first transistor M 1  is connected with the first power source line ELVdd, a drain of the first transistor M 1  is connected with the first contact point P 1 . The first contact point P 1  is connected with the first power source line ELVdd through a resistor, polyresistance R. A gate of the first transistor M 1  is connected with a drain of the second transistor M 2 , so that a current corresponding to a voltage supplied to the gate of the first transistor M 1  flows from the source and to the drain. Accordingly, the source and the drain of the first transistor M 1  received the first supply voltage from the first power source ELVdd. 
     A source of the second transistor M 2  is connected with a data line D 1 . A drain of the second transistor M 2  is connected with a gate of the first transistor M 1 . A gate of the second transistor M 2  is connected to a scanning line S 1 , and performs a switching operation corresponding to a scanning signal, and thus a data signal is transmitted to the gate of the first transistor M 1 . 
     A first terminal of the capacitor Cst is connected with the first power source line ELVdd, a second terminal of the capacitor Cst is connected with the gate of the first transistor M 1  A voltage corresponding to the difference between a voltage of the first power source line ELVdd transmitted through the first power source line ELVdd and a voltage of a data signal is stored during a pre-charge time. Accordingly, even though the second transistor M 2  cuts off the data signal through a switching operation, the data signal is maintained at the gate of the first transistor M 1  by the capacitor Cst. Thus, a current corresponding to the data signal can flows from the source of the first transistor M 1  to the drain of the first transistor M 1 . 
       FIG. 3  illustrates another embodiment of a pixel portion in a state such that the light emitting diodes are not yet formed. As shown in  FIG. 3 , parts of the pixel are shown and a pixel circuit of 3×3 size is shown. Referring to  FIG. 3 , a plurality of scanning lines S 1 , S 2 , S 3 , S 4  are arranged in a row direction, and a plurality of data lines D 1 , D 2 , D 3  and a plurality of first power source lines ELVdd are arranged in a column direction. The scanning lines S 1 , S 2 , S 3 , S 4 , the data lines D 1 , D 2 , D 3 , and the first power source lines ELVdd are each connected with the pixel circuits. For simplified explanation, a first pixel circuit through a ninth pixel circuit is respectively named from left and to right and from up and to down. A structure of the pixel circuit will be explained using t he first pixel circuit as follows. 
     Each pixel circuit has an identical structure, and has a first transistor M 1  through a fifth transistor M 5  and a first capacitor Cst and a second capacitor Cvth. The first transistor M 1  through the fifth transistor M 5  are embodied as a PMOS transistors and each have a source, a drain and a gate. The source and the drain of each transistor are electrically substantially identical, and any one of the source and the drain can be named as a first electrode and the other can be named as a second electrode. In addition, the first capacitor Cst and the second capacitor Cvth each have a first terminal and a second terminal. 
     For the simplified explanation, a structure of the pixel circuit will be explained using the first pixel circuit as follows. A source of the first transistor M 1  is connected with the first power source line ELVdd. A drain of the first transistor M 1  is connected with a first node A. A gate of the first transistor M 1  is connected with a third node C. Accordingly, a current corresponding to a voltage supplied to the third node C flows from the source and to the drain of the first transistor M 1 . 
     The source of the second transistor M 2  is connected with the data line D 1 , the drain of the second transistor M 2  is connected with a second node B, and a gate of the second transistor M 2  is connected with a second scanning line S 2 . A data signal is selectively supplied to the second node B according to the second scanning signal supplied through the second scanning line S 2 . 
     A source of a third transistor M 3  is connected with the first node A, a drain of the third transistor M 3  is connected with the third node C, a gate of third transistor M 3  is connected with the first scanning line S 1 , and thus the first transistor M 1  selectively becomes a diode connection by the first scanning signal supplied through the first scanning line S 1 . 
     A source of a fourth transistor M 4  is connected with the first power source line ELVdd, a drain of the fourth transistor M 4  is connected with the second node B, and a gate of fourth transistor M 4  is connected with the first scanning line S 1 . Thus, a voltage of the first power source line ELVdd is transmitted to the second node B according to the first scanning signal supplied through the first scanning line S 1 . 
     A source of a fifth transistor M 5  is transmitted to the first node A, a drain of the fifth transistor M 5  is connected with the first contact point P 1 . A gate of fifth transistor M 5  is connected with a light emission control line E 1 . Thus, a current which flows from the source of the first transistor M 1  to the drain of the first transistor M 1 , can be selectively transmitted to the first contact point P 1  by a light emission control signal which is selectively supplied through the light emission control line En. The first contact point P 1  is connected with the power source line ELVdd through the polyresistance R. Accordingly, if the fifth transistor M 5  is turned on, the drain of the first transistor M 1  receives the first supply voltage from the first power source line ELVdd, and thus the source and the drain of the first transistor M receive the first supply voltage. 
     The first electrode of the first capacitor Cst is connected with the first power source line ELVdd. The second electrode of the first capacitor Cst is connected with the second node B, and thus, if a data signal is transmitted to the second node B, the first capacitor Cst stores a voltage according to the difference between the data signal and the first power source line ELVdd. 
     The first electrode of the second capacitor Cvth is connected with the second node B. The second electrode of the capacitor Cst is connected with the third node C. Thus, if the first transistor M 1  is diode connected by the third transistor M 3 , the second capacitor Cvth stores a threshold voltage of the first transistor M 1 . 
       FIG. 4  illustrates another embodiment of a pixel portion in a state such that the light emitting diodes are not yet formed. Referring to  FIG. 4 , a plurality of scanning lines S 1 , S 2 , S 3 , S 4  are arranged in a row direction, and a plurality of data lines D 1 , D 2 , D 3  and a plurality of first power source lines ELVdd are arranged in a column direction. And, the scanning lines S 1 , S 2 , S 3 , S 4 , the data lines D 1 , D 2 , D 3 , and first power source lines ELVdd are each connected with pixel circuits. 
     Each pixel circuit has an identical structure, and has a first transistor M 1  through a sixth transistor M 6  and a capacitor Cst. 
     The first transistor M 1  through the sixth transistor M 6  are embodied as a PMOS transistor and have a source, a drain and a gate. The source and the drain of each transistor are electrically substantially identical, and any one of the source and the drain can be named as a first electrode and the other can be named as a second electrode. In addition, the first capacitor Cst has a first terminal and a second terminal. For the simplified explanation, a first pixel circuit through a ninth pixel circuit is respectively named from left and to right and from up and to down. A structure of the pixel circuit will be explained using the first pixel circuit as follows. 
     A source of the first transistor M 1  is connected with the first node A, a drain of the first transistor M 1  is connected with a second node B, and a gate of the first transistor M 1  is connected with a third node C. Accordingly, a current flows from the source and to the drain by a voltage supplied to the third node C. 
     The source of the second transistor M 2  is connected with the data line D 1 , the drain of the second transistor M 2  is connected with a first node A, and a gate of the second transistor M 2  is connected with the second scanning line S 2 . Thus, a data signal is selectively supplied to the first node A according to the second scanning signal supplied through the second scanning line S 2 . 
     A source of a third transistor M 3  is connected with the second node B, a drain of the third transistor M 3  is connected with the third node C, and a gate of third transistor M 3  is connected with the first scanning line S 1 . Thus, the first transistor M 1  is selectively diode-connected according to the first scanning signal supplied through the first scanning line S 1 . 
     A source of a fourth transistor M 4  is connected with the first scanning line S 1 , a drain of the fourth transistor M 4  is connected with the third node C, and a gate of fourth transistor M 4  is connected with the first scanning line S 1 . Thus, a signal corresponding to the first scanning signal supplied through the first scanning line S 1  selectively initializes the capacitor Cst. 
     A source of a fifth transistor M 5  is transmitted to the first power source line EVLdd, a drain of the fifth transistor M 5  is connected with the first node A, and a gate of fifth transistor M 5  is connected with a light emission control line En. Thus, a voltage, supplied from the first power source line ELVdd, is switched according to a light emission control signal selectively supplied through the light emission control line En. 
     A source of a sixth transistor M 6  is connected to the second node B, a drain of the sixth transistor M 6  is connected with the first contact point P 1 , and a gate of sixth transistor M 6  is connected with a light emitting control line En. Thus, a current from the first transistor M 1  is transmitted to the first contact point P 1  according to a light emission control signal selectively supplied through the light emission control line En. 
     The first contact point P 1  is connected with the first power source line ELVdd through the polyresistance R. In addition, the fifth transistor M 5  and the sixth transistor M 6  are turned on by an identical signal, and if the fifth transistor M 5  and the sixth transistor M 6  are turned on, the source and the drain of the first transistor M 1  receive the first supply voltage through the first power source line ELVdd. 
     The first electrode of the capacitor Cst is connected with the first power source line ELVdd, and the second electrode of the capacitor Cst is connected with the third node C. Thus, if a data signal is transmitted to the third node C, the first capacitor Cst stores a voltage according to the data signal and the first power source line ELVdd. 
       FIGS. 5   a  through  5   c  illustrate a fabrication process of a pixel portion depicted in  FIG. 2 . For simplified explanation, a fabrication process is limited to a pixel portion of  FIG. 2  but may be applied to a pixel portion of  FIGS. 3 and 4 , as well as other pixels not described herein. 
     Referring to  FIGS. 5   a  though  5   c,  a buffer layer is formed on a transparent substrate  200 , and a polysilicon layer is evaporated and patterned onto the substrate  200 . Thus, a polysilicon layer is formed as shown in  FIG. 5 . 
     The polysilicon layer comprises a channel  213  of a first transistor, a channel  211  of a second transistor, a first terminal  212  of a capacitor, and a polyresistance R. After a first insulating film is evaporated onto the substrate  200 , a first metal layer is evaporated onto the substrate and subsequently patterned. A gate electrode is generated as shown in  FIG. 5   b.  The gate electrode becomes a gate and a scanning line  211  of a first transistor, and a gate of a second transistor and a second terminal  222  of a capacitor. 
     After a second insulating film is evaporated onto the substrate, a second metal layer is evaporated onto the substrate and subsequently patterned. A first power source line  231 , a source and a drain metal  232  of the first transistor, and a source and a drain metal  233  of the second transistor are generated as shown in  FIG. 5   c.  The source and the drain metal are connected with a channel area of the first transistor and the second transistor through a contact hole. In addition, the first power source line is electrically connected with the polyresistance through a contact hole. 
       FIG. 6  illustrates a process of testing the pixel portion depicted in  FIG. 5 . 
     At a first step ST  100 , signals are supplied through a first power source line of a pixel portion, through a data line and through a scanning line. Accordingly, a predetermined voltage is stored across a capacitor Cst. A voltage corresponding to the signal supplied to the capacitor Cst through the data line is stored in a functioning pixel. However, a non-functioning pixel does not store the voltage at the capacitor Cst. 
     Some failure mechanisms for a non-functioning pixel are: an abnormal capacitor, an abnormal first transistor and an abnormal second transistor. If the capacitor Cst is opened, or not connected to, for example the drain of the second transistor M 2 , a voltage is not stored. Similarly, if the capacitor Cst is shorted, a voltage will not be stored. If the first transistor M is abnormal, or non-functional, for example, if a source and a gate of the first transistor M 1  are shorted, a source voltage of the first transistor M 1  becomes identical to a gate voltage of the first transistor M 1  and a voltage is not stored at the capacitor Cst. In addition, if a drain and a gate of the first transistor M 1  are shorted, a drain of the first transistor M is connected with the first power source line ELVdd through the polyresistance and thus, a gate voltage of the first transistor M 1  becomes identical to a source of the first transistor M 1 . Accordingly, a voltage is not charged at the capacitor Cst. If the second transistor M is non-functional, a signal transmitted to the capacitor through a data line by the second transistor M 2  is not passed to the capacitor Cst. 
     At second step ST  110  the capacitor Cst voltage is measured. While maintaining signals in the first power source line of the pixel portion  100  and in a scanning line, a voltage charged at the capacitor Cst is measured through a data line. 
     At third step ST  120  an operational condition, such as functionality of the pixel is determined. A normal, or functional, pixel outputs a voltage corresponding to a signal transmitted to the capacitor Cst through the data line. But a non-functional pixel does not charge a voltage at the capacitor Cst, or charges a voltage different from the voltage transmitted to the capacitor Cst and thus outputs a different voltage than that which is expected. Accordingly, if a certain signal is supplied, and a voltage read from a data line is not substantially identical to the expected voltage, a pixel is determined to be non-functional. Likewise, if the read voltage is substantially identical as the expected voltage, a pixel portion is determined to be functional. 
     After a pixel is determined to be functional, an LED anode electrode can be formed. In the process of forming the anode electrode, the polyresistance R can be eliminated. 
     An eliminating process of the polyresistance will be explained. Referring to  FIG. 5C , an insulating film is formed over data line  230 , the first power source ling  231 , the source and the drain metal  232  of the first transistor, the source and a drain metal  233  of the second transistor, and the polyresistance. After the insulating film between the channel of the first transistor M 1  and the power source line ELVdd is etched, a metal film is formed. The metal film is etched and patterned, and the remaining metal film becomes an anode electrode for the LED. In the process of patterning the anode electrode, if the metal film other than the anode electrode is etched, the polyresistance is etched. Thus, the desired result of creating the anode electrode and opening the connection between the drain of the first transistor M 1  and the first power source line ELVdd is attained in substantially the same processing operation. 
     Although a few embodiments have been shown and described, it would be appreciated by those skilled in the art that changes might be made in this embodiment without departing from the principles and spirit of the invention. 
     According to a fabrication method and a test method for a light emitting display, whether an non-functional pixel is formed is easily determined by testing functionality of pixels of a light emitting display before forming corresponding light emitting diodes.