Abstract:
Disclosed is an output driver, which comprises: a resistance element with resistance, coupled to an output terminal; a current mode driving circuit, coupled to the resistance element, for providing a first current to the output terminal, wherein at least one of the amount of the first current and the resistance of the resistance element is adjusted according to a control signal; and a control circuit for generating the control signal according to a mode signal, wherein the mode signal corresponds to at least two technology standards.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to an output driver, and particularly relates to an output driver of a memory. 
         [0003]    2. Description of the Prior Art 
         [0004]    Since the performance of modern processors is continuously improving, the memory bandwidth becomes a critical characteristic affecting the performance of a computer system. The technique of Double-Data-Rate (DDR) memory has developed from DDRI to DDRII and through to the newest: DDRIII. Each standard, however, has specific requirements. According to the DDR standard determined by JDEC, DDRI memory must follow the SSTL-25 standard, where the voltage on the I/O port of the memory must be 2.5 V. DDRII memory must follow the SSTL-18 standard, where the voltage on the I/O port of the memory must be 1.8 V. DDRIII memory must follow the SSTL-15 standard, where the voltage on the I/O port of the memory must be 1.5 V. 
         [0005]    Therefore, the width of a transistor and I/O pad area must be increased for meeting different standards, so the total area of a circuit and the cost thereof are increased. Also, different voltages or different circuits must be provided if memories of different standards need to be supported. Accordingly, the inconvenience of designing, and related costs, are increased. 
       SUMMARY OF THE INVENTION 
       [0006]    One objective of the present invention is to provide an output driving circuit, which utilizes a current mode driving circuit to cooperate with a load for providing suitable output voltage to input/output pads. 
         [0007]    Another objective of the present invention is to provide an output driving circuit, which can meet at least two different technical specifications. 
         [0008]    A further objective of the present invention is to provide an output driving circuit, which can meet at least two different technical specifications to decrease the layout area of a printed circuit board. 
         [0009]    Another objective of the present invention is to provide an output driving circuit, which can meet at least two different technical specifications, thereby different voltages or voltage reducing elements are not needed and the inconvenience and the cost are decreased. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a circuit diagram illustrating the output driving circuit according to a first embodiment of the present invention. 
           [0012]      FIG. 2  is a circuit diagram illustrating the current mode driving circuit of the output driving circuit shown in  FIG. 1 . 
           [0013]      FIG. 3  is a circuit diagram illustrating the adjustable current source according to one embodiment of the present invention. 
           [0014]      FIG. 4  is a circuit diagram illustrating the current source shown in  FIG. 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0015]      FIG. 1  is a circuit diagram illustrating the output driver  100  according to the first embodiment of the present invention. As shown in  FIG. 1 , the output driver  100  comprises a resistor  101 , an adjustable current mode driver  103 , a control circuit  106  and a switch  109 . The resistor  101  is coupled to an output terminal  102  and a first voltage level V tt . The adjustable driver  103  is coupled to a second voltage level V dd , the control circuit  106  and an output terminal  102  for selectively outputting a first predetermined current  1   a  or draining a second predetermined current  1   b  via the output terminal  102  to cooperate with at least one of the resistor  101 ,  107  to generate the output voltage level on the output terminal  102 . In one preferred embodiment, the first voltage level V tt  is half of the second voltage level V dd . The resistor  107  in  FIG. 1  represents the equivalent impedance of a memory device and the output driver  100  is located within a memory controller. For examples, the memory device can be a DDRI, DDRII, or DDRIII memory device, and the output driver  100  of the memory controller can output an output signal, which matches various standards (e.g. DDRI, DDRII, DDRIII standards). 
         [0016]    In one embodiment, the resistance element  101  is an adjustable resistance element or an ODT (On Die Termination) corresponding to a memory of DDR specification. The ODT can be a signal termination device, which is used for enhancing the completeness of a signal and for cutting off the spreading of the signal to stop interference signals. Since the sockets of a memory on a main board are coupled via a bus, the DRAM that needs to operate will receive the signal and process it, while the DRAM that does not need to operate also receives the signal but releases the signal at once when the data stream signal is transmitted to the memory socket. The signal released by the DRAM not needing to operate will keep transmitting on the bus, thus the DRAM will repeatedly receive the signal and noise interference may occur. Accordingly, the existence of the ODT is necessary to prevent interference. DDRII further integrates the above-mentioned resistance to the memory. The DRAM controller adjusts the resistance value of the ODT to decrease the signal when the signal enters DDRII and does not need to be processed by the DRAM, that is, the DRAM is in a standby state. By this method, the signal will not be transmitted back to the bus by the original line and is absorbed by the memory, such that the issue of signal interference can be avoided. Such a method is called an ODT mechanism. As described above, ODT can maintain the completeness of the signal to increase the stability of a system. Furthermore, since the ODT is inside the memory and can decrease the path and operation time of the memory, and the ODT can decrease the feedback when the memory operates at a high speed for increasing the performance of the memory and the clock limitations. Also, in one embodiment the resistance element  107  is an outside loading (for example, the input resistance of a memory). The output driving circuit  100  can utilize the switch of the switching element  109  to make the resistance devices  101 ,  107  meet the specification of the coupled memory. 
         [0017]    In one embodiment, the control circuit  106  receives a mode control signal C MODE , which is used for informing the output driving circuit  100  of the type of coupled memory, and an input data D IN . The control circuit  106  can therefore generate a control signal CS according to the mode control signal C MODE  in order to control the value of at least one of the first current  1   a  or the second current  1   b  of the adjustable current mode driving circuit  103  to cooperate with the resistance element  101  or  107  for generating desired voltage corresponding to different specifications such as SSTL-25, SSTL-18, SSTL-15 on the output terminal  102 . 
         [0018]    Also, the adjustable current mode driving circuit  103  controls the slew rate of at least one of the first current  1   a  or the second current  1   b  to meet different specifications such as SSTL-25, SSTL-18, SSTL-15 according to the control signal CS. By this adjusting method, the signal outputted from the output terminal  102  can control the inside capacitance of a memory to obtain suitable slew rates and voltage levels for generating signals corresponding to DDRI, DDRII or DDRIII. In other words, the state of the output signal of the output driving circuit  100 , i.e. high or low logic, corresponds to the input data D IN . Also, the variation of the output signal of the output driving circuit  100  (for example, the high or low of the voltage level, the slew rate, or both of them) relates to the mode control signal C MODE . 
         [0019]    In one embodiment, the output signal of the output driving circuit  100  is a data signal or a strobe signal of a memory. In this case, the I/O pad  105  is a data pin or a strobe pin of the memory controller. 
         [0020]    In one embodiment, the first switching element  205  and the second switching element  207  are transistors. The first predetermined current  1   a  equals a better value of the second predetermined current  1   b . A better value of the first voltage level V tt  is half of the second voltage level V dd , but this is not a limitation of the present invention. 
         [0021]      FIG. 2  is a circuit diagram illustrating the current mode driving circuit  103  of the output driving circuit  100  shown in  FIG. 1 . It should be noted that the preferred embodiment is only for illustration purposes and is not mean to limit the scope of the present invention. The current mode driving circuit  103  comprises a first current source  201 , a second current source  203 , a first switching element  205 , a second switching element  207 , and pre-drivers  209  and  211 . In this embodiment, the first current source  201  is adjustable, for providing a first current  1   a , and the second current source  203  is used for providing a second current  1   b . The pre-drivers  209  and  211  are used for controlling the first switching element  205  and the second switching element  207 . In this embodiment, the first switching element  205  and the second switching element  207  do not operate at the same time for avoiding floating of the output terminal of the output driving circuit  100 . The first current source  201  and the second current source  203  can be implemented by various kinds of circuits such as a current mirror. Examples are described as follows. 
         [0022]      FIG. 3  is a circuit diagram illustrating the adjustable current source according to one embodiment of the present invention. As shown in  FIG. 3 , the adjustable current source  300  comprises a plurality of current sources  301 ,  303  and  305 , a plurality of switches  307 ,  309  and  311 , and a slew rate control circuit  313 . The switches  307 ,  309  and  311  are used for controlling the current sources  301 ,  303  and  305  respectively to generate the first current  1   a . The slew rate control circuit  313  is used for controlling the slew rate (that is, the variation rate) of the first current  1   a  to meet corresponding specifications. In one embodiment, the slew rate control circuit  313  can comprise a plurality of delay units  315 ,  317  (only part of them are illustrated), to ensure the switches  307 ,  309  and  311  do not turn on at the same time. In this way, the slew rate of the first current  1   a  can meet corresponding specifications, but this is merely an example, not a limitation of the present invention. 
         [0023]    The current sources  301 ,  303  and  305  can be adjustable current sources.  FIG. 4  is a circuit diagram illustrating the current source shown in  FIG. 3 . The adjustable current source  305  comprises a plurality of current sources  401 ,  403  and  405 , and a plurality of switches  407 ,  409  and  411 . In this embodiment, the number of current sources  401 ,  403  and  405  is m and is controlled by an m-bit control signal. The circuits shown in  FIG. 3  and  FIG. 4  can be applied to the second current source  203 , and the structures of current sources  401 ,  404  or  405  can utilize the circuit shown in  FIG. 3 . 
         [0024]    Briefly speaking, the circuit shown in  FIG. 3  can be utilized for adjusting the slew rate of the first current  1   a  or the second current  1   b , and the circuit shown in  FIG. 4  can be utilized for adjusting the first current  1   a  or the second current  1   b . Therefore, the circuit according to the present invention can meet the voltage and the signal slew rate corresponding to different technical specifications. It should be noted that the circuits shown in  FIG. 3  and  FIG. 4  are only for examples and are not meant to limit the scope of the present invention. Persons skilled in the art can utilize other circuits to meet the same purposes. 
         [0025]    According to the above-mentioned circuits, the voltages and signal slew rates corresponding to different technical specifications can be met without providing different voltages or voltage reducing elements, such that the inconvenience of design, the associated cost, and the layout of printed circuit boards can be decreased. 
         [0026]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.