Abstract:
In an RC calibration circuit, a single reference current is used to generate voltages across both a resistive and capacitive element. The component value of one of the resistive and capacitive element is successively altered until the voltages are substantially equal. Additionally, parasitic capacitances in the circuit are precharged to the resistive element voltage prior to the comparison. The RC calibration circuit eliminates the errors due to current matching and parasitic capacitances in prior art calibration circuits. The circuit includes a comparator and a digital control circuit (DCW) including a successive approximation register (SAR) holding the value of the digital control word used to control the component value of the tunable resistive or capacitive element. The SAR alters the DCW in an iterative, bit-by-bit binary searching pattern in response to the comparator output.

Description:
PRIORITY CLAIM 
       [0001]    The present application claims priority to U.S. Application No. 61/515,181, titled “High Accuracy RC Calibration Circuit”, filed with the U.S. Patent Office on Aug. 4, 2011, the disclosure of which is incorporated herein by reference in its entirety. 
     
    
     TECHNICAL FIELD 
       [0002]    The present invention relates generally to electronic circuits, and in particular to an improved RC calibration circuit. 
       BACKGROUND 
       [0003]    In modern IC design, and in particular in the field of portable wireless transceivers, a very high degree of integration, with minimum external components, is mandatory for cost reduction. In current semiconductor process, without an expensive trimming process, the component values of raw passive resistive (R) and capacitive (C) devices can vary over a wide range. Temperature variation can also cause on-chip RC values to change. Such wide RC variation makes the design of a continuous time RC filter, with stable corner frequency, challenging. One known solution is to embed an automatic calibration mechanism within the chip to maintain the RC product constant. 
         [0004]      FIG. 1  depicts a functional circuit diagram of conventional RC calibration circuit  10 , the purpose of which is to calibrate the R or C value in another circuit, such as a slave filter  28 . The filter  28  may be used, for example, in a frequency-conversion mixer or the like. The circuit  10  accomplishes this by calibrating the values of a corresponding resistor R REF  or capacitor C C , and setting the R or C element in the slave filter  28  to the same value ( FIG. 1  depicts adjustment of C C ). A current mirror  12  generates two current sources supplying currents I REF1  and I REF2  into a resistor R REF  and a capacitor C C , respectively, to generate V R  and V C . In the resistor branch, the constant current flows into the resistor R REF  to generate V R =I REF1 *R REF . In the capacitor branch, the current will be integrated on the capacitor C C  for a fixed period of time T TAR . If the capacitor C C  initial voltage equals zero, at the end of current integration, V C =I REF2 *T TAR /C C . T TAR  is the target time constant, in general generated by a crystal oscillator (not shown), which can have high accuracy, with frequency errors well below 1%. 
         [0005]    A comparator  14  and sequential approximation register (SAR)  16  are the basis of a digital calibration circuit  10  using a binary searching algorithm to minimize the difference V RC  V R −V C . The searching process minimizes V RC  at the input of the comparator  14  by properly tuning the value of R or C. At the end of the searching processing, V R =V C  or equivalently I REF1 *R REF =I REF2 *T TAR /C C . If I REF1 =I REF2 , the reference current can be cancelled out and the proper calibration T TAR =R REF *C C  is achieved. The final digital control word (DCW) code output by the SAR  16  is distributed to the slave filter  18 . By periodically recalibrating the circuit  10  and adjusting the value of R or C in the slave filter  18 , the filter  18  is tuned to have a time constant independent of process and temperature variation. 
         [0006]    One problem with a conventional RC calibration circuit  10 , such as that of  FIG. 1 , is that it requires I REF1  to match to I REF2 . Any mismatch between I REF1  and I REF2  will result in an RC time constant calibration error. In order to improve the current source matching performance, the current source device size must increase. The problem with increasing the device size is that the parasitic capacitance C PM  associated with current source output node will increase with the device size. Any extra capacitance added to the current source output node will result in an RC time constant calibration error, because the charge delivered by the current source will be shared by C C  and C PM . Accordingly, the conventional RC time constant calibration circuit  10 , such as that of  FIG. 1 , cannot be optimized to achieve high calibration accuracy, even if the circuit layout size is not restricted. 
         [0007]    Another problem with the conventional RC calibration circuit  10  is that any parasitic capacitance present in the branch between the current source transistor and C C , e.g., the parasitic capacitance from the input of comparator C P , will result in calibration error, since the total charge sourced from the current source is shared by C C  and the parasitic capacitance. 
       SUMMARY 
       [0008]    According to one or more embodiments described and claimed herein, a current steering architecture eliminates the current source matching requirement. Compared with a conventional RC calibration circuit, embodiments of the present invention generate V R  and V C  from the same reference current. Accordingly, current matching performance is guaranteed by the architecture. 
         [0009]    Embodiments of the present invention also pre-charge the parasitic capacitance to I REF *R REF  (the resistor voltage). This process cancels out the parasitic capacitance, which eliminates the accuracy loss related to the parasitic capacitance of the current source output C PM  and the capacitive loading from the input loading of comparator C P . 
         [0010]    One embodiment relates to an RC calibration circuit. The circuit includes a resistive element and a capacitive element, where at least one of the resistive and capacitive elements is tunable. The circuit also includes a current source providing a single reference current selectively through the resistive or capacitive elements. The circuit further includes a comparator for determining a voltage difference by comparing the voltage drops across the resistive and capacitive elements, and a control circuit. The control circuit is operative to tune at least one of the resistive and capacitive elements so as to minimize the voltage difference determined by the comparator. 
         [0011]    Another embodiment relates to a method of tuning the component value of one of a resistive and capacitive element in an RC calibration circuit so as to equalize the voltage drops across the resistive and capacitive elements. A single reference current is provided. The reference current is directed through the capacitive element for a predetermined duration to charge the capacitive element to a first voltage. The reference current is directed through the resistive element to generate a second voltage. The first and second voltages are compared. The component value of one of the resistive and capacitive elements is altered in response to the comparison. This process is repeated with different component values until the first and second voltages are substantially equal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a functional schematic diagram of a prior art RC calibration circuit. 
           [0013]      FIG. 2  is a functional schematic diagram of an RC calibration circuit according to one embodiment of the present invention. 
           [0014]      FIG. 3  is a functional schematic diagram of variable capacitor as a tuning element. 
           [0015]      FIG. 4  is a functional schematic diagram of variable resistor as a tuning element. 
           [0016]      FIG. 5  is a timing diagram depicting the operation of the RC calibration circuit. 
           [0017]      FIG. 6  is a functional schematic diagram of the RC calibration circuit in reset phase. 
           [0018]      FIG. 7  is a functional schematic diagram of the RC calibration circuit in integration phase. 
           [0019]      FIG. 8  is a functional schematic diagram of the RC calibration circuit in comparison phase. 
           [0020]      FIG. 9  is a flow diagram of a method of operating the RC calibration circuit. 
           [0021]      FIG. 10  is a functional schematic diagram of an RC calibration circuit according to another embodiment of the present invention. 
           [0022]      FIG. 11  is a functional schematic diagram of an RC calibration circuit according to still another embodiment of the present invention. 
           [0023]      FIG. 12  is a functional schematic diagram of an RC calibration circuit according to yet another embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0024]      FIG. 2  depicts a functional schematic diagram of an RC calibration circuit  20  according to one embodiment of the present invention. In this embodiment, a current steering architecture is implemented to eliminate the current sources matching requirement. Compared with traditional RC calibration circuit  10 , the circuit  20  of  FIG. 2  generates V R  and V C  from the same current source M 1 , so excellent current matching performance is guaranteed by the architecture. 
         [0025]    During an initial reset phase, the RC calibration circuit  20  pre-charges the parasitic capacitance to I REF *R REF . This process will cancel out the parasitic capacitance, which eliminates the accuracy loss related to the parasitic capacitance of the current source output C PM  and the capacitive loading from the input of comparator C P− . This is more fully described herein. 
         [0026]    The RC calibration circuit  20  according to one embodiment of the present invention as depicted in  FIG. 2  includes: a tunable resistor  30  or tunable capacitor  32  (the capacitor  32  is depicted as the tunable element in  FIG. 2 ); current steering switches SW RC ; a comparator  24 ; digital control circuitry  27  including a successive approximation register (SAR)  26 ; a slave filter  28 , and a current mirror  22  including a single current source M 1  generating one reference current I REF . 
         [0027]    The tuneable element  30 ,  32  is the device that can be tuned based on the digital control word (DCW) stored in the SAR  26 . In the embodiment of  FIG. 2 , the capacitor C C    32  has been implemented as the tuning element. 
         [0028]      FIG. 3  depicts a representative 6-bit implementation of a variable capacitor turning element  32 , using capacitors and switches. In this example, the capacitors C 0 -C 5  increase in size in a binary fashion, and a capacitance is selected by applying a binary code to the bit switches. In another embodiment, the capacitor values may be equal, and a thermometer code applied to the switches. Those of skill in the art will recognize other implementations are possible. 
         [0029]    The tuning element is not limited to the capacitor. For example, the resistor R REF    30  can be implemented as the tuning element, a representative example of which is depicted in  FIG. 4 . In this embodiment, resistances R_ 1 -R_ 5  are selectively added in series to a fixed resistance R_FIX, by opening the associated bypass switch, and are selectively excluded from the resistance by closing the associated bypass switch. As described above, the resistances R_ 1 -R_ 5  may be binary weighted and the switches controlled by a binary value, or the resistances may be equal and the switches controlled by a thermometer coded value. Those of skill in the art will recognize that a digitally-controlled, tunable resistance may be implemented in other ways. 
         [0030]    Referring back to  FIG. 2 , the Single Pole Double Throw (SPDT) switch SW RC  controls the current flow of I REF . When INT=0 (as depicted in  FIG. 2 ), it steers current into the resistor  30  to generate the reference voltage V R =I REF *R REF . When INT=1, the switch SW RC  steers the current to capacitor C C    32 ; the capacitor will integrate the current into voltage, and the amount of voltage change equals 
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         [0031]    The comparator  24  compares V R  and V C  in response to the control signal CMP. The comparator output is set to 1, when V R &gt;V C , and 0 when V R &lt;V C . 
         [0032]    A digital control circuit  27  receives a clock signal (not shown), and generates the required digital control signals to control all of the switches, as well as the status of the RC calibration circuit  20 . 
         [0033]    The SAR circuit  26  within the digital control circuit  27  starts the binary searching process by setting the MSB (most significant bit) of DCW to 1 and setting the rest of the bits of DCW to 0. The RC calibration circuit  20  generates one set of V R  and V C  based on the current DCW code. The comparator  24  compares V R  and V C . If V O =1, the current RC time constant R REF *C C  set by the DCW code is higher than the target. This causes the SAR  26  to reset the MSB back to 0. If V O =0, the SAR  26  retains the MSB setting of 1. The SAR  26  then continues the binary searching process by sequentially moving from the MSB towards the LSB of the DCW code, setting the current bit to 1, and updating that bit value based on comparator  24  output. 
         [0034]      FIG. 5  is a timing diagram illustrating an example of this process for a 3-bit RC calibration circuit  20 . ENABLE is a signal (not shown in  FIG. 2 ) that enables the calibration circuit  20 . RST, INT, and COMP are control signals output by the digital logic  27 , as explained below. IAC is a control signal coupling the capacitor  32  output to the voltage comparator  24 , and V R  and V C  are the voltage drops across the resistor  30  and capacitor  32 , respectively. V RC  is the voltage difference at the input to the comparator  24 , and V O  is the comparator  24  output voltage. The three bits of the digital control word DCW are depicted separately. Initially (beginning at the left of  FIG. 5 ), the MSB, or DCW&lt;2&gt; is set to 1, and all other bits are 0. 
         [0035]    The RC calibration circuit  20  operates in three different phases, as applied to each DCW bit calibration: reset phase, integration phase and comparison phase. These are indicated in  FIG. 5  by alternate assertion of the signals (by the digital logic  27 ) RST, INT, and COMP, respectively. 
         [0036]      FIG. 6  illustrates the circuit  20  configuration during the reset phase ( FIGS. 6-8  explicate various phases of the calibration circuit  20 , and omit the slave filter  28  for clarity). During the reset phase (RST=1 in  FIG. 5 ), the current steering switch SW RC  steers the current I REF  into R REF    30 . The parasitic capacitances C PM  and C P−  will be charged up to I REF *R REF . The tunable capacitor C C    32  is also discharged. 
         [0037]      FIG. 7  illustrates the circuit  20  configuration during the integration phase. Integration phase follows the reset phase (INT=1 in  FIG. 5 ). During the integration phase, the current steering switch SW RC  steers the current I REF  into C C    32 . C C    32  integrates the current for T TAR  seconds. At the end of the integration phase, the current steering switch SW RC  steers current back to the resistor (i.e., INT=0). Note that, in  FIG. 5 , V R =0, and VC is rising, while INT=1. 
         [0038]      FIG. 8  illustrates the circuit  20  configuration during the comparison phase. Comparison phase follows the integration phase (CMP=1 in  FIG. 5 ). During the comparison phase, the comparator  24  compares V R  to V C . The comparison result feeds into the SAR  26  to update the DCW code. 
         [0039]    Referring again to  FIG. 5 , at the end of the reset phase, integration phase and comparison phase for the MSB of DCW&lt;2&gt;, V R &lt;V C , and DCW&lt;2&gt; remains a 1. The above-described process is repeated, with the next bit, DCW&lt;1&gt; set to 1. At the end of the comparison phase for this bit, V R &gt;V C , and DCW&lt;1&gt; is reset to 0. Finally, the process is repeated once again, with the LSB DCW&lt;0&gt; set to 1. Again, in the comparison phase, V R &gt;V C , and DCW&lt;0&gt; is reset to 0. The final value of DCW is then &#39;b100. This value is “locked in” for C C    32 , and is applied to the slave filter  28 . 
         [0040]    During the calibration process for each bit, since I REF  comes from the same current source M 1  in the current mirror  22 , the currents used to generate V R  and V C  are identical, and there is no current mismatch concern. 
         [0041]    In conventional RC calibration circuits (e.g.,  FIG. 1 ), during the current integration phase, C C  shares charge with C P− , and C PM . 
         [0042]    The total charge 
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         [0000]    sourced from current source M 1  is shared by C C , C P− , and C PM , so the actual calibrated time constant is R REF *(C C +C P− +C PM ), rather than the desired time constant R REF *C C . 
         [0043]    The present invention solves the parasitic capacitors (C P− , and C PM ) charge sharing problem by pre-charging C P− , and C PM  to I REF *R REF  during the reset phase. Let C P =C P− +C PM , at the end of the reset phase, the total charge accumulated on C P  is C P *I REF *R REF . This charge will be reserved to the integration phase. During the integration phase, total charge sourced from the current source is I REF *T TAR . At the end of integration cycle, V C  equals to 
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         [0044]    The differential voltage V RC  that feeds into the comparator  24  during the comparison cycle is 
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         [0045]    From equation (1), the sign of V RC  is determined by R REF *C C -T TAR . For a regular comparator  24 , the output is determined by the sign of the differential input. At the end of the SAR binary searching process, V RC  will be minimized close to zero, and R REF *C C  will be tuned to T TAR . In equation (1), if we set C P =0, it would be the V RC  of an ideal RC calibration circuit, without parasitic capacitance. Compared with an ideal RC calibration, embodiments of the present invention, such as that depicted in  FIG. 2 , attenuate V RC  by a factor of C C /(C C +C P ). Since comparator  24  output depends on the sign of input only, these embodiments will tune the RC time constant to the same DCW code as in the ideal RC calibration circuit. 
         [0046]      FIG. 9  depicts a method  100  of calibrating an RC circuit. A single reference current I REF  is generated (block  102 ). A SAR  26  clears (i.e., sets to 0) all bits in a DCW that tunes the resistance of a tunable resistive element  30  or the capacitance of a tunable capacitive element  32 , and sets the current bit position to the MSB (block  106 ). Within a calibration loop, the SAR  26  sets the current bit value of the DCW to 1, altering the component value of the tunable resistive or capacitive element (block  106 ). The reference current I REF  is directed through the capacitive element for a predetermined duration to charge the capacitive element to a first voltage (block  108 ). The reference current I REF  is then directed through the resistive element to generate a second voltage (block  110 ). The first and second voltages are compared, such as at the comparator  26  (block  112 ). If the voltage across the tunable resistive/capacitive element exceeds the voltage across the fixed resistive/capacitive element (block  114 ), then the DCW value for the tunable element is too high, and the current bit is set to 0 (block  116 ). Otherwise, the current bit remains a 1. If the current bit is not the LSB (that is, each bit in the DCW has not yet been adjusted) (block  118 ), the SAR  26  considers the next bit in the DCW (block  120 ), sets that bit to a 1 (block  106 ), and repeats the process. After adjusting the value all bits, and the current bit is the LSB (block  118 ), the full DCW code is stored, to be applied to the tunable resistive/capacitive element in the slave filter  28  (block  122 ). 
         [0047]      FIG. 10  depicts an alternative embodiment  40  of the present invention that can be used to calibrate the RC time constant for a parasitic insensitive RC filter or RC integrator application. The “parasitic” in this case refers to the parasitic capacitance of the capacitor itself. For example, in the RC integrator  42  in  FIG. 10 , the parasitic capacitance C INT     —     P  of capacitor C INT  is connected to the pseudo-ground of the OP amp input, so the transfer function of the integrator, 
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         [0000]    is insensitive to C INT     —     P . If a conventional RC calibration circuit  10  (e.g.,  FIG. 1 ) were used to maintain the integrator transfer function constant, the calibration circuit  10  would tune the RC time R INT *(C INT +C INT     —     P ) to a target value, rather than maintaining R INT *C INT  constant. For typical sub-micron CMOS process, C INT     —     P /C INT ˜=5% to 10% range, depend on the type of capacitor, which means the conventional RC time constant calibration circuit  10  cannot be accurate below the ratio of C INT     —     P  C INT . The calibration circuit  40  of  FIG. 10  solves this problem by disconnecting the ground terminal of C C  during the reset phase, and pre-charging parasitic capacitance C C     —     P  to I REF *R REF . The cancelling out of C C     —     P  in this embodiment is similar to the cancelling process of C PM  and C P−  of the embodiment  20  depicted in  FIG. 2 , as described above. Since the capacitors C C  and C INT  are of the same type, the ratio of C INT     —     P /C INT  equals to C C     —     P /C C . Cancelling the C C     —     P  in the RC calibration circuit is equivalent to controlling the time constant R INT *C INT  of the integrator without the influence of C INT     —     P . Accordingly, the architecture of the RC calibration circuit  40  can accurately control the time constant of R INT *C INT  and hence maintain the transfer function of the RC integrator  42  constant. 
         [0048]      FIG. 11  depicts an embodiment using a tunable sampling capacitor C R  to sample the voltage level I REF *R REF  during the reset phase. This reduces the noise level at the input terminals of the comparator  24  during the comparison phase. 
         [0049]      FIG. 12  depicts an embodiment implementing the RC calibration circuit  20  with cascade transistors in the current mirror  22 . 
         [0050]    The RC calibration circuits  20 ,  40  according to embodiments of the present invention described herein present numerous advantages over the prior art. No OP amplifier is required, so the calibration accuracy is not affected by the amplifier offset and settling. No major matching component is required. Since there is only one current source used in the current steering structure, it is self-matched. The overall circuit layout size can thus be reduced. In embodiments of the present invention, parasitic capacitances are pre-charged, so they do not adversely affect calibration accuracy. 
         [0051]    The present invention may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the invention. The present embodiments are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.