Abstract:
A motor-driven power steering system includes a power assisting motor; a motor current sensor, a sample-hold circuit that has sampling section and a holding section, a timing signal generating circuit that generates a timing signal to activate either the sampling section or the holding section and an alarming unit that generates an abnormality signal if the timing signal is not detected for a prescribed period.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     The present application is based on and claims priority from Japanese Patent Application 2004-40311, filed Feb. 17, 2004, the contents of which are incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a motor-driven or an electrical power steering system (hereinafter referred to as motor-driven power steering system) and, more particularly a sample-hold circuit that is controlled by an abnormality detecting function.  
         [0004]     2. Description of the Related Art  
         [0005]     A motor-driven power steering system for assisting operation of the steering wheel in which steering wheel operation is detected by means of steering torque to control motor rotation speed according to the steering torque is well known, as disclosed in JP-B2-2678377.  
         [0006]     Such a motor-driven power steering system has a sample-hold circuit for detecting motor current, which has a microcomputer. The sample-hold circuit cyclically samples motor current values according to a timing signal provided by the microcomputer and holds the motor current value for a preset period.  
         [0007]     When the current value is held by the sample-hold circuit, the current value, which is an analog signal, is converted to a digital signal by a separate A-D converter, thereby controlling operation of the motor.  
         [0008]     Although an abnormality detecting means is equipped with, the sample-hold circuit does not correctly operate if the timing signal is not sent to the sample-hold circuit due to disconnection or breaking of a timing signal wire. For example, if a command current value is larger than a detected current value that is detected a current sensor and held by a capacitor before the disconnection or breaking, a microcomputer increases the command current value further to narrow the difference between the command current value and the detected current value because the detected current value gradually decreases as the capacitor discharges. Accordingly the motor current is excessively increased, so that power assisting is not correctly carried out.  
       SUMMARY OF THE INVENTION  
       [0009]     In view of the above problem, it is an object to provide a motor-driven power steering system that has a highly reliable sample-hold circuit.  
         [0010]     According to a feature of the invention, a motor-driven power steering system includes a power assisting motor, a current sensor that detects motor current value, a timing signal generating circuit that generates bi-level timing signals at prescribed intervals, a sample-hold circuit for sampling and holding the detected motor current value at the prescribed time intervals set by the timing signal generating circuit, an abnormality detecting circuit that makes the sample-hold circuit keep holding the last sampled value if the timing signal is not detected for a prescribed period.  
         [0011]     In the above motor-driven power steering system, the abnormality detecting circuit may include a counter circuit connected to the timing signal generating circuit. In this case, the prescribed period is generated when the counter circuit counts a prescribed number.  
         [0012]     The above motor-driven power steering system may include a torque sensor that detects steering torque and an assist current calculating circuit that calculates a command current value to be applied to the motor from both the current value sent from the sample-hold circuit and the steering torque sent from the torque sensor to control the motor  15 . In this case, the maximum of the command current value is set to the detected motor current value if the timing signal is not detected for the prescribed period. The above described motor driven power steering system may further includes means for gradually lowering the command current value. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     Other objects, features and characteristics of the present invention as well as the functions of related parts of the present invention will become clear from a study of the following detailed description, the appended claims and the drawings. In the drawings:  
         [0014]      FIG. 1  is a schematic diagram illustrating an overall structure of a motor-driven power steering system according to a preferred embodiment of the invention;  
         [0015]      FIG. 2  is a block diagram illustrating a steer control circuit;  
         [0016]      FIG. 3  is a block diagram illustrating an abnormality detecting circuit and its peripheral portions; and  
         [0017]      FIG. 4  is a block diagram illustrating a counter circuit and a comparator circuit. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0018]     A motor-driven power steering system according to a preferred embodiment of the present invention will be described with reference to the appended drawings.  
         [0019]     As shown in  FIG. 1 , a steering wheel  10  is connected to a steering shaft  12   a . A torque sensor  11  is connected to the lower end of the steering shaft  12   a  and to the upper end of a pinion shaft  12   b . The pinion shaft  12   b  has a pinion (not shown) at the lower end thereof. The pinion is disposed in a steering gear box  16  and engages a rack bar  18 . The rack bar  18  has opposite ends respectively connected to one ends of tie rods  20 . The other ends of the tie rods  20  are respectively connected to steered wheels  24  via knuckle arms  22 . A motor  15 , such as a DC motor or a brushless motor, is also connected to the pinion shaft  12   b  via a gear (not shown) and driven by a motor driving circuit  14 . A current sensor  8  is provided to detect motor current of the motor  15  and connected to a steer control unit  30 . A vehicle speed sensor  17  is also connected to the steer control unit  30 . Thus, a column type motor-driven power steering system is formed.  
         [0020]     The torque sensor  11  includes a well-known torsion bar and a pair of resolvers that are spaced apart from each other in the axial direction of the torsion bar. When the steering wheel  10  is operated and the steering shaft  12   a  is turned, the torsion bar is twisted by an amount proportional to the turning. The resolver detects a difference in angle between opposite ends of the torsion bar, so that the steering torque applied to the torsion bar can be calculated from the difference in angle and the spring constant of the torsion bar. This signal is sent to the steer control unit  30 .  
         [0021]     The angular position of the motor  15  is detected by a motor angular position sensor  9 , which is composed of a well-known sensor such as a rotary encoder or a resolver. The angular position sensor  9  sends its output signal to the steer control unit  30 .  
         [0022]     As shown in  FIGS. 1 and 2 , the steer control unit  30  includes a CPU  31 , a RAM  32 , a ROM  33 , an input-output interface I/O  34  and their bus line  35 , a sample-hold circuit  41  and an abnormality detecting circuit  42  in addition to the current sensor  8 , the driving circuit  14 . The CPU  31  carries out its control according to programs and data stored in the ROM  33  and RAM  32 . The ROM  33  has a program storing section  33   a  and a data storing section  33   b . The program storing section  33   a  stores a steer control program  33   p . The data storing section  33   b  stores data necessary for carrying out the steer control program  33   p.    
         [0023]     The steer control unit  30  carries out the steer control program  33   p  to calculate a driving torque from the steering torque detected by the torque sensor  11 , so that the motor driver  14  can apply a suitable voltage to the motor  15  to operate at a driving torque that corresponds to the steering torque. The steer control unit  30  also calculates an actual motor torque from a motor current value detected by the current sensor  8  to carry out a feedback-control so that the actual motor torque can be equal to the driving torque.  
         [0024]     When the current sensor  8  detects motor current, the output signal of the sensor  8  is sent to a sample-hold circuit  41 . The CPU  31  includes an assist current calculating section  31   a  that provides the sample-hold circuit  41  with a timing pulse signal. The timing pulse signal has pulses generated at a predetermined cycle. The sample-hold circuit  41  operates at either a sampling state or a holding state.  
         [0025]     If the abnormality detecting circuit  42  detects an abnormality of the sample-hold circuit  41 , it sends a signal to the assist current calculating section  31   a . The assist current calculating section  31   a  calculates a command current value to be applied to the motor  15  from both the current value sent from the sample-hold circuit  41  and the steering torque sent from the torque sensor  11 , and controls the driving circuit  14  with the command current value to drive the motor  15 . When the system is stopped, the maximum of the command current value may be gradually lowered toward zero so that a driver or passengers do not feel a shock. Incidentally, the command current value can be calculated from the angular position signal sent from the angular position sensor  9 .  
         [0026]     As shown in  FIG. 3 , the current sensor is composed of a shunt resistor  8   a  that provides a voltage signal when motor current is supplied to the motor  15 . The sample-hold circuit  41  includes a voltage amplifying section  411  that includes a well-known operational amplifier  41   a  and a sample-hold section  412  that includes operational amplifiers  41   b ,  41   e , a switch  41   c  and a capacitor  41   d.    
         [0027]     The voltage signal sent from the current sensor  8  is amplified by the voltage amplifying circuit  411  and sent to the sample-hold section  412 . The sample-hold section  412  changes from one of the sampling and holding states to the other according to the timing signal sent from the CPU  31  via the abnormality detecting circuit  42 .  
         [0028]     When the timing signal provides an H-level, the switch  41   c  is turned on, so that the sample-hold section  412  stays at the sampling state. Accordingly, the capacitor  41   d  is charged until the capacitor voltage becomes as high as the output terminal of the operational amplifier  41   b . When the timing signal provides an L-level, the switch  41   c  is turned off. Accordingly, the electric charge of the capacitor  41   d  is discharged, and the output voltage of the operational amplifier  41   e  becomes as low as the voltage of the capacitor  41   d . The output voltage of the operational amplifier  41   e  is sent to the assist current calculating section  31   a , as a detected current signal.  
         [0029]     As shown in  FIG. 4 , the abnormality detecting circuit  42  includes a trigger circuit  42   a , a counter circuit  42   b , a comparator circuit  42   c  and a signal line  42   d . The abnormality detecting circuit  42  inputs the timing signal sent from the CPU  31  to the trigger circuit  42   a  that forms a trigger signal from a rising edge of a pulse when the timing signal changes from the L-level to the H-level or a falling edge of the pulse when the timing signal changes from the H-level to the L-level.  
         [0030]     The counter circuit  42   b  is composed of a counter clearing circuit  421  and an up counter  422 . The counter clearing circuit  421  is composed of an RS flip flop circuit, and the up counter  422  is a binary 10-bit free-run counter that is composed of a plurality of registers  422   a . The registers  422   a  are respectively defined as b 9 , b 8 , . . . b 0  from the highest bit register to the lowest bit register.  
         [0031]     The counter circuit  42   b  usually counts the number of clock signals provided by a clock CLK to provide binary digit output signal. When the binary digit output signal becomes a maximum or overflows, the counter circuit  42   b  is reset to count the clock signals from 0. When the counter circuit  42   b  receives a trigger signal of the trigger circuit  42   a , the output signal of the counter circuit  42   b  is reset or cleared to 0 to start counting again.  
         [0032]     The comparator circuit  42   c  examines whether the counted number of the counter circuit  42   b  exceeds a threshold value or not. If the counted number exceeds the threshold value, it is presumed that the timing signal is not sent from the CPU  31 . In this case, the comparator circuit  42   c  sends an H-level signal to the CPU  31 , which sends a command signal via the signal line  42   d  to the sample-hold section  412  to hold the timing signal unchanged and the switch  41   c  in the turn-off state. Incidentally, the H-level signal of the comparator circuit  42   c  can be sent to the sample-hold section  412  to hold the switching operation via a signal line instead of the signal line  42   d . On the other hand, if the counted number does not exceed the threshold value, it is presumed that the timing signal is normally sent from the CPU  31 . In this case, the comparator circuit  42   c  sends an L-level signal to the CPU  31 . The above-described structure is also useful when the signal line  42   d  comes down.  
         [0033]     The comparator circuit  42   c  is composed of an AND circuit  423  that has a plurality of input terminals D 0 , D 1  . . . D 9 , which are respectively connected to the output terminals of the registers b 0 , b 1 , . . . . b 9 . An inverter circuit  423   a , is connected between the register defined b 7  and the terminal D 7 . Other inverter circuits  423   b ,  423   c ,  423   d  are respectively connected between the corresponding registers defined b 6 , b 5 , b 4  and the terminals D 6 , D 5 , D 4  in the same manner as the inverter circuit  423   a . The AND circuit  423  is composed of a well-known logical circuit that provides an H-level (or 1) signal when an H-level (or 1) signal is sent to all the input terminals D 0 -D 9 . That is, if the counted number in binary code becomes 1100001111, the H-level signal is provided from the output terminal  423   e  of the comparator  42   c . Incidentally, if only one of the registers  422   a  becomes 1 when an abnormality is detected, such as 0010000000, the AND circuit  423  can be omitted if the output terminal of the register defined as b 7  is directly connected to the CPU  31 .  
         [0034]     In the foregoing description of the present invention, the invention has been disclosed with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made to the specific embodiments of the present invention without departing from the scope of the invention as set forth in the appended claims. Accordingly, the description of the present invention is to be regarded in an illustrative, rather than a restrictive, sense.