Abstract:
A method of fabricating an LCD includes providing first and second substrates. A gate electrode, a gate line, a connection electrode, a common electrode and a pixel electrode are formed on the first substrate through a first making process. A first insulation film is formed on the first substrate. A first insulation film pattern having multiple contact holes are formed through a second masking process. An active pattern is formed on the first substrate and source and drain electrodes are operationally connected with the active pattern through some of the contact holes. A gate electrode, a common electrode, and a pixel electrode may be formed substantially together through a slit exposure. An active pattern and source and drain electrodes may be formed substantially together. The number of masks needed to fabricate the display may be reduced to simplify a fabrication process and protect a channel region.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Priority Claim 
         [0002]    This application claims the benefit of priority from Korean Application No. 43149/2006, filed May 12, 2006, which is incorporated herein by reference. 
         [0003]    2. Technical Field 
         [0004]    The present invention relates to a liquid crystal display (LCD), and more particularly, to an improved fabrication method. 
         [0005]    3. Related Art 
         [0006]    Demand for information displays is growing as the demand for portable (mobile) information devices increases. In some devices thin flat panel displays (FPD) are used. These FPDs have Liquid Crystal Displays (LCD) that use an optical anisotropy of a liquid crystal. The medium exhibits excellent resolution, color, and picture quality. 
         [0007]    Some LCDs have multiple substrates in which a liquid crystal layer is formed between a color filter substrate and an array substrate. Thin film transistors (TFTs) are used as switching elements in these displays. The LCD in  FIG. 1  includes a color filter substrate  5 , an array substrate  10 , and a liquid crystal layer  30 . The color filter substrate  5  includes color filters (C) that have sub-color filters  7  that generate red, green, and blue colors. Black matrixes  6  separate the sub-color filters  7  and block light transmission to the liquid crystal layer  30 . A transparent common electrode  8  applies a voltage to the liquid crystal layer  30 . The array substrate  10  of  FIG. 1  includes a plurality of gate lines  16  and data lines  17  that form a plurality of pixel regions (P). TFTs are formed at each crossing of the gate lines  16  and data lines  17 , and pixel electrodes  18  are formed on each pixel region (P). 
         [0008]    The color filer substrate  5  and the array substrate  10  are attached in adjacent positions using a sealant. Two substrates  5  and  10  are attached through an attachment key. 
         [0009]    The LCD shown in  FIG. 1  is a twisted nematic (TN) type LCD in which nematic liquid crystal molecules are driven in a perpendicular direction relative to the substrates. When a voltage is applied to the liquid crystal display panel, liquid crystal molecules that have been aligned horizontally to the substrates are aligned in a vertical direction. 
         [0010]    In  FIG. 2 , the N number of gate lines and M number of data lines in a plane switch (IPS) mode LCD cross each other to from M×N number of pixels on an array substrate. A gate line  16  and a data line  17  positioned vertically and horizontally form a pixel region on a transparent glass substrate  10 . A TFT is formed at the crossing of the gate line  16  and the data line  17 . 
         [0011]    The TFT includes a gate electrode  21  connected to the gate line  16 . A source electrode  22  is connected to the data line  17 , and a drain electrode  23  is connected to a pixel electrode  18  through a pixel electrode line  181 . The TFT includes a first insulation film for insulating the gate electrode  21  and the source and drain electrodes  22  and  23 . An active pattern forms a conductive channel between the source electrode  22  and the drain electrode  23 . 
         [0012]    In the pixel region, a plurality of common electrodes  8  and a plurality of pixel electrodes  18  are alternately disposed in a direction parallel to the data line  17 . The pixel electrodes  18  are connected with the pixel electrode line  181  through a first contact hole  40   a . The pixel electrodes  18  are electrically connected with the drain electrode  23  and the common electrodes  8  are electrically connected to a common electrode line  81  in parallel with the gate line  16  through a second contact hole  40   b.    
         [0013]    In  FIG. 3A , a gate electrode  21 , a gate line, and a common line are formed on a substrate  10  through a photolithography process (a first making process). In  FIG. 3B , a first insulation film  15   a , an amorphous silicon thin film, and an n+ amorphous silicon thin film are sequentially deposited on the entire surface of the substrate  10  with the gate electrode  21 . The gate line and the common line are then formed, and the amorphous silicon thin film and the n+ amorphous silicon thin film are selectively patterned using photolithography (a second masking process) to form an active pattern  24 . At this stage, the n+ amorphous silicon thin film pattern  25  which has been patterned in the same form as the active pattern  24  is formed. 
         [0014]    Thereafter, as shown in  FIG. 3C , a conductive metal is deposited on the entire surface of the substrate  10  and then selectively patterned through photolithography (a third masking process). The photolithography forms a source electrode  22  and a drain electrode  23  at an upper portion of the active pattern  24 . At this stage, a certain portion of the n+ amorphous silicon thin film pattern formed on the active pattern  24  is removed through the third masking process to form an ohmic contact layer  25   n.    
         [0015]    In  FIG. 3   c , a portion of the source electrode  22  extends in one direction to form the data line  17 , and a portion of the drain electrodes  23  extends to the pixel region to form the pixel electrode line  181 . Next, in  FIG. 3D , a second insulation film  15   b  is deposited on the entire surface of the substrate  10  with the source electrode  22  and the drain electrode  23  formed. A portion of the second insulation film  15   b  is removed through photolithography (a fourth masking process) to form a contact hole  40   a  exposing a portion of the pixel electrode line  181 . At this stage, another portion of the second insulation film  15   b  is removed through the fourth masking process to form a second contact hole exposing a portion of the common line. 
         [0016]    Finally, as shown in  FIG. 3E , a transparent conductive metal material is deposited on the entire surface of the substrate  10  and then selectively patterned using photolithography (a fifth making process) to form pixel electrodes  18  that are electrically connected with the pixel electrode line  181  and the common electrodes  8  that are electrically connected with the common line in  FIG. 2 . 
         [0017]    When fabricating some array substrates that include TFTs, at least five photolithography processes are performed to pattern the gate electrode, the active pattern, the source and drain electrodes, the contact holes, and the pixel electrodes. Successive photolithography processes may degrade production yields, decrease reliability, and increase the likelihood of a defective TFT. Because the masks used to form pattern can be very expensive, as more masks are applied, the fabrication cost of the LCD increases. Therefore, there is a need for a cost efficient fabrication process that may increase production yields, improve reliability, and decrease production defects. 
       SUMMARY 
       [0018]    A method of fabricating an LCD includes forming a gate electrode, a gate line, a connection electrode, a common electrode and a pixel electrode, on a first substrate through a first making process. Once formed a first insulation film is formed on the first substrate. A first insulation film pattern having multiple contact holes is formed through a second masking process. An active pattern is then formed on the first substrate and source and drain electrodes that are coupled with a portion of the active pattern are then formed. The first substrate is then coupled to a second substrate. 
         [0019]    Other systems, methods, features and advantages of the invention will be, or will become, apparent to one with skill in the art upon examination of the following Figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the following claims. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0020]    The invention can be better understood with reference to the following drawings and description. The components in the Figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the Figures, like referenced numerals designate corresponding parts throughout the different views. 
           [0021]      FIG. 1  is an exploded perspective view of a liquid crystal display. 
           [0022]      FIG. 2  is a plan view of a portion of an array substrate. 
           [0023]      FIGS. 3A to 3E  are sectional views taken along line II-II′ of  FIG. 2 . 
           [0024]      FIG. 4  is a plan view showing a portion of an array substrate of one pixel of an LCD. 
           [0025]      FIG. 5A to 5C  are sectional views of a fabrication process taken along a line IV-IV′ of the array substrate in  FIG. 4 . 
           [0026]      FIG. 6A to 6E  are plan views of a fabrication process of the array substrate of  FIG. 4 . 
           [0027]      FIGS. 7A to 7E  are sectional views of a first masking process of  FIGS. 5A and 6A . 
           [0028]      FIGS. 8A to 8E  are sectional views of a second masking process of  FIGS. 5B and 6B . 
           [0029]      FIG. 9A to 9F  are sectional views showing a third masking process of  FIGS. 5C and 6C  to  6 E. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0030]    In  FIG. 4  the N number of gate lines and M number of data lines cross to form the M×N number of pixels on an array substrate. Gate lines  116  and data lines  117  are arranged vertically and horizontally to form a pixel region on an array substrate  110 . A switching element is positioned at a crossing of the gate line  116  and the data line  117 . In  FIG. 4  the switching element comprises a thin film transistor (TFT). 
         [0031]    The TFT includes a gate electrode  121  connected with the gate line  116 , a source electrode  122  connected with the data line  117 , and a drain electrode  123  connected with the pixel electrode  118  through the pixel electrode line  1181 . The TFT includes a first insulation film that insulates the gate electrode  121  the source/drain electrodes  122  and  123 , and an active pattern. The active pattern forms a conductive channel between the source and drain electrodes  122  and  123  when a gate voltage applied to the gate electrode  121 . In  FIG. 4 , a portion of the source electrode  122  is coupled to the data line  117 , and a portion of the drain electrode  123  extends into the pixel region to form the pixel electrode line  1181 . 
         [0032]    In the pixel region, two or more common electrodes  108  and two or more pixel electrodes  118  are alternately disposed to generate an in-plane field. In this figure the common electrodes  108  and the pixel electrodes  118  are arranged substantially parallel to the data line  117 . In alternate systems the common electrodes  108  and the pixel electrodes  118  are arranged substantially parallel to the gate line  116  or are configured in other arrangements. 
         [0033]    The pixel electrodes  118  are electrically or operationally connected with the pixel electrode line  1181  through a first contact hole. The common electrodes  108  are connected with the common line  1081  and are arranged substantially parallel to the gate line  116 . The common line  1081  is connected with the first connection lines  108   a  and  108   a ′. These lines are substantially parallel to the data line  117  near the left and right edges of the pixel region. The first left and right connection lines  108   a  and  108   a ′ are connected by a second connection line  108   b  arranged substantially parallel to the gate line  116 . 
         [0034]    The gate electrode  121 , the gate line  116 , the common line  1081 , the first connection lines  108   a  and  108   a ′ and the second connection line  108   b  are formed as a dual-layer. The dual layer comprises a lower layer made of a transparent conductive material and an upper layer made of an opaque conductive material. The common electrode  108  and the pixel electrode  118  exposed in the pixel region may be formed as a single layer made of the transparent conductive material. 
         [0035]    A portion of the side or upper or lower surface of the common electrode  108  extends downwardly from the common line  1081 , the first connections  108   a  and  108   a ′, or the second connection line  108   b  to form a connection with the common line  1081 , the first connection lines  108   a  and  108   a ′, or the second connection line  108   b . A portion of the common line  1081  overlaps a portion of the pixel electrode line  1181  with a first insulation film interposed therebetween to form a circuit element used to store charge or a storage capacitor (Cst). The storage capacitor (Cst) substantially sustains a voltage applied to a liquid crystal capacitor until a next signal is received. 
         [0036]    Besides sustaining the signal, the storage capacitor (Cst) may stabilize a gray scale representation and/or may reduce a residual image. In  FIG. 4   115 ″ denotes an etch stopper comprised of an insulating material. A etch stopper positioned near an upper portion of a channel region of the active pattern may prevents a back channel of the TFT from being damaged when an n+ amorphous silicon thin film is etched. 
         [0037]    The array substrate may be fabricated through a multi-step process. While the processes may be customized to specific elements and conditions, one process generated may pattern a circuit through less than five steps such as through three steps. Some processes form the gate electrode, the common electrode, and the pixel electrode substantially together and form the active pattern and the source and drain electrodes substantially together through a slit (diffraction) mask or half-tone mask. Other processes use other masks. 
         [0038]    In  FIGS. 4 ,  5 A, and  6 A, the gate electrode  121 , the gate line  116 , the common line  1081 , the first connection lines  108   a  and  108   a ′, the second connection line  108   b , the common electrode  108  and the pixel electrode  118  are formed on a substrate  110  comprising a transparent insulation material such as glass in these figures. 
         [0039]    The gate electrode  121 , the gate line  116 , the common line  1081 , the first connection lines  108   a  and  108   a ′, the second connection line  108   b , the common electrode  108  and the pixel electrode  118  are formed by patterning first and second films through a patterning process in which patterns are transferred to a wafer. In  FIGS. 5 and 6  a photolithograph patterning process is used. 
         [0040]    In some devices that use the first conductive film, a transparent conductive material with excellent transmittance such as indium tin oxide (ITO) and/or indium zinc oxide (IZO) may be used. In devices that use a second conductive film, a low resistance opaque conductive material such as aluminum (Al), an aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), and/or molybdenum (Mo), etc. may be used. 
         [0041]    In  FIGS. 5 and 6  near the lower portion of the gate electrode  121 , the gate line  116  and the common line  1081  are formed from the second conductive film. A gate electrode pattern  120 ′, a gate line pattern, and a common line pattern  120 ″ are patterned to form the gate electrode  121 , the gate line  116 , and the common line  1081 . 
         [0042]    A side or a portion of the upper and lower surfaces of the common electrode  108  formed of the first conductive film extends to the lower surface of the common line  1081 . The first connection lines  108   a  and  108   a ′ or the second connection line  108   b , and a portion of a lower surface of the pixel electrode  118  formed of the first conductive film extends to the lower surface of the connection electrode  130 ′″ formed of the second conductive film. 
         [0043]    The gate electrode  121 , the gate line  116 , the common line  1081 , the first connection lines  108   a  and  108   a ′and the second connection line  108   b  comprising the second conductive film may be formed simultaneously or nearly simultaneously with the common electrode  108  and the pixel electrode  118  formed of the first conductive film. 
         [0044]      FIGS. 7A to 7E  are sectional views showing the first masking process of  FIGS. 5A and 6A . In  FIG. 7A , the first and second conductive films  120  and  130  are deposited on the entire surface or nearly the entire surface of the substrate  110 . The conductive films may be made of a transparent insulation material such as glass and the process may occur sequentially. In some devices the first conductive film  120  comprises a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). A low resistance opaque conductive material such as aluminum (Al), an aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and/or a molybdenum alloy, etc. may comprise the second conductive film  130 . Thereafter, a photosensitive film  170  made of a photosensitive material such as photoresist is formed on the entire surface or nearly the entire surface of the substrate  110 , on which light is selectively allowed to pass through a plate covered with an array of patterns. A slit mask  180  (or a half-tone mask) or in an alternate process a multi-slit mask may be used. 
         [0045]    The slit mask  180  may include a transmission region (I) for allowing light to pass through, a slit region (II) with a slit pattern that transmits only a portion of light while blocking a portion of light, and a blocking region (III) for preventing light to pass through. In some processes only light that is transmitted through the slit mask  180  may irradiate the photosensitive film  170 . 
         [0046]    When a photosensitive film  170  that has been exposed through the slit mask  180  is developed, ( FIG. 7B ), photosensitive film patterns  170   a - 170   f  housing a certain thickness may remain at regions where light has been entirely blocked or partially blocked. Light may be blocked by the blocking region (III) and the slit region (II). Photosensitive film at the transmission region (I) to which light has been almost entirely transmitted or allowed to pass through has been almost completely removed due to the expose of the surface of the second conductive film  130 . 
         [0047]    At this stage, the first to fourth photosensitive film patterns  170   a  to  170   d  formed through the blocking region (III) are thicker than fifth and sixth photosensitive film patterns  170   e  and  170   f  formed at the slit region (II). The photosensitive film at the region to which light has been almost entirely transmitted through (the transmission region (I)) is almost completely removed. In this process a positive photoresist was used. In alternate processes a negative photoresist or a combination may be used. 
         [0048]    When the first and second conductive films  120  and  130  formed at the lower portion are patterned, that may use photosensitive film patterns  170   a  to  170   f  as masks ( FIG. 7C ), while the gate electrode  121 , the gate line, and the common line  1081  are formed from the second conductive film. The common electrode  108  and the pixel electrode  118  made from the first conductive film are also formed on the substrate  110 . 
         [0049]    Near the lower portion of the gate electrode  121 , the gate line, and the common line  1081 , a gate electrode pattern  120 ′, a gate line pattern, and a common line pattern  120 ″ are formed from the first conductive film. These elements have been patterned in the same form as the gate electrode  121  and the common line  1081 . 
         [0050]    Near an upper portion of the common electrode  108  and the pixel electrode  118  (formed from the first conductive film), a connection electrode conductive film pattern  130 ′, and connection line conductive film pattern  130 ″, are formed from the second conductive film. These elements have been patterned in the same form as the common electrode  108  and the pixel electrode  118 . 
         [0051]    When an ashing process is performed to remove a portion of the photosensitive film patterns  170   a  to  170   f  ( FIG. 7D ), the fifth photosensitive film pattern  170   e  and the sixth photosensitive film pattern  170   f  of the upper portion of the connection electrode conductive film pattern  130 ′ and the connection line conductive film pattern  130 ″ may be almost or completely removed. These areas may correspond the slit region (II) where the slit has been exposed to light. The areas expose the surface of the connection electrode conductive film pattern  130 ′ and the connection line conductive film pattern  130 ″. 
         [0052]    At this stage, the first to fourth photosensitive film patterns, respectively, remain as the seventh to tenth photosensitive film patterns  170   a ′ to  170   f ′ with a thickness obtained by removing the thickness of the fifth and sixth photosensitive film patterns at a certain portion that corresponds to the blocking region (III). The connection electrode conductive film pattern and the connection line conductive film patterns are then selectively removed through the seventh to tenth photosensitive film patterns  170   a ′ to  170   f ′ as masks to form a connection electrode  130 ′″. The connection electrode  130 ′″ is connected with a portion of the pixel electrode at an upper portion of the pixel electrode  118 . During the process the first connection line  108   a  which is electrically or operationally connected with a portion of the common electrode  108  and the second connection line are formed near an upper portion of the common electrode  108 . 
         [0053]    In  FIGS. 5B and 6B , on almost the entire surface or the entire surface of the substrate  110  on which the gate electrode  121 , the gate line  116 , the common line  1081 , the first connection lines  108   a  and  108 ′, the second connection line  108   b , the common electrode  108 , the pixel electrode  118  are supported, a first insulation film  115   a , an amorphous silicon thin film  124 , and a second insulation film are deposited. In some process, the film is deposited. In some processes these elements are deposited sequentially. Once deposited the first insulation film  115   a , the amorphous silicon thin film  124 , and the second insulation film are patterned by a patterning process such as photolithography (a second masking process) that may also occur sequentially. The process may form a first contact hole  140   a , a second contact hole  140   b , a third contact hole  140   c , a first hole Ha and a second hole Hb. Almost at the same time the process may form an etch stopper  115 ′ comprising the second insulation film in a desire form. 
         [0054]    At this stage, the first contact hole  140   a  exposes a portion of the connection electrode  130 ′″, and the second and third contact holes  140   b  and  140   c  expose a portion of the amorphous silicon thin film  124  near the left and right upper portions of the gate electrode  121 . The partial etch stopper  115 ′ remaining after patterning process between the second and the third contact holes  140   b  and  150   c  may prevent an infiltration of an etching solution or an etching gas into a back channel of the active pattern when the n+ amorphous silicon thin film is patterned. 
         [0055]    In some systems and processors, the slit exposure or multi-slit exposure is used for the second masking process.  FIGS. 8A to 8E  are sectional views of the second masking process of  FIGS. 5B and 6B . In  FIG. 8A , on almost the entire surface or the entire surface of the substrate  110  on which the gate electrode  121 , the gate line  116 , the common line  1081 , the first connection lines  108   a  and  108   a ′ are supported, the second connection line  108   b , the common electrode  108 , and the pixel electrode  118  are formed, and the first insulation film  115   a , the amorphous silicon thin film  124 , and the second insulation film  115  are deposited. In some systems this occurs sequentially. A photosensitive film  270  comprised of a photosensitive material such as a photoresist is formed on nearly the entire surface or the entire surface of the substrate  110 , on which light is selectively passed through a slit mask  280  (or a half-tone mask). 
         [0056]    The slit mask  280  may include a transmission region (I) for allowing light to pass through, a slit region (II) with a slit pattern that transmits only a portion of light while blocking a portion of light, and a blocking region (III) for preventing light to pass through. In some processes only light which is transmitted through the slit mask  280  may irradiate the photosensitive film  270 . 
         [0057]    When the photosensitive film  270  that has been exposed through the slit mask  280  is developed ( FIG. 8B ), photosensitive film patterns  270   a - 270   e  having a certain thickness remain at regions where light has been entirely blocked or partially blocked. Light may be blocked by the blocking region (III) and the slit region (II). Photosensitive film at the transmission region (I) to which light has been entirely transmitted or allowed to pass through has been almost completely or entirely removed due to the expose of the surface of the second insulation film  115 . 
         [0000]    At this stage, the first photosensitive film pattern  270   a  formed through the blocking region (III) is thicker than the second to fifth photosensitive film patterns  270   b  to  270   e  formed at the slit region (II). The photosensitive film at the region to which light has been almost entirely transmitted through (the transmission region (I)) is almost completely removed. In this process a positive photoresist is used. In alternate processes negative photoresist or a combination may be used. 
         [0058]    When the first insulation film  115   a , the amorphous silicon thin film  124 , and the second insulation film  115  are patterned, which may occur through photosensitive film patterns  270   a  to  270   e  that act as masks ( FIG. 8C ), the first contact hole  140   a  is formed exposing a portion of the connection electrode  130 ′″. 
         [0059]    When an ashing process is performed to remove a portion of the photosensitive film patterns  270   a  to  270   e  ( FIG. 8D ), the second to sixth photosensitive film patterns at the slit region (II) to which the slit exposure has been applied may be almost completely removed to expose the surface of the second insulation film  115 . 
         [0060]    At this stage, the first photosensitive film pattern remains as the sixth photosensitive film pattern  270   a ′ with a thickness obtained by removing the thickness of the second to fifth photosensitive film patterns at a certain portion corresponding to the blocking region (III). As shown in  FIG. 8E , when a portion of the second insulation film is removed by using the sixth photosensitive film pattern  270   a ′ as a mask, the second and third contact holes  140   b  and  140   c  are formed. The second and third contact holes  140   b  and  140   c  expose a portion of the amorphous silicon thin film  124  at the left and right upper portions of the gate electrode  121 . At the same time or nearly the same time, a first hole Ha exposing a portion of the amorphous silicon thin film  124  of the upper portion of the common line  1081  and a second hole Hb exposing a portion of the amorphous silicon thin film  124  where a data line is to be formed are formed. 
         [0061]    At this stage, the second insulation film where the first to third contact holes  140   a  to  140   c  and the first and second holes Ha and Hb have been patterned forms a first insulation film pattern  115 ′. In  FIGS. 5C ,  6 C and  6 E, an active pattern  124 ′ is formed. At the same time or nearly the same time the source and drain electrodes  122  and  123  that are electrically or operationally connected to a certain portion of the active pattern  124 ′ through the second and third contact holes are formed through a single patterning process or photolithography process (a third masking process). At this stage, a portion of the source electrode  122  extends in one direction and connects with the data line  117 . The data line is substantially perpendicular to the gate line  116 . A portion of the drain electrode  123  extends to the pixel electrode to form the pixel electrode line  1181  that is electrically or operationally connected with the connection electrode  130 ′″ and the lower pixel electrode  118  through the first hole. 
         [0062]    The first insulation film pattern formed of the second insulation film is patterned in a certain form through the third masking process to form an etch stopper  115 ″. The etch stopper  115 ″ positioned at the upper portion of the channel region of the active pattern  124 ′ may prevent or minimize a back channel of the TFT from being damaged when the n+ amorphous silicon thin film is etched. 
         [0063]      FIGS. 9A to 9F  are sectional views showing a third masking process in  FIGS. 5C and 6C  to  6 E. In  FIG. 9A , an n+ amorphous silicon thin film  125   b  and a third conductive film  150  are deposited on the entire surface or nearly the entire surface of the substrate  110 , a photosensitive film  370  made of a photosensitive material such as photoresist is formed on almost the entire surface or nearly the entire surface of the substrate  110 , and then light is selectively passed onto the photosensitive film  370  through the slit mask (or the half-tone mask)  380  in alternate processes a multi-slit mask may be used. 
         [0064]    The slit mask  380  may include a transmission region (I) for allowing light to pass through, a slit region (II) with a slit pattern for transmitting only a portion of light and blocking a portion of light, and a blocking region (III) for preventing light to pass through. In some processes only light that is transmitted through the slit mask  380  may be irradiated on the photosensitive film  370 . 
         [0065]    When the photosensitive film  370  that has been exposed through the slit mask  380  is developed. ( 9 B), photosensitive film patterns  370   a ˜ 370   d  with a certain thickness remain at regions where light has been entirely blocked or partially blocked through the blocking region (III) and the slit region (II). Photosensitive film at the transmission region (I) to which light has been almost entirely transmitted or allowed to pass through is almost completely removed due to the expose of the surface of the third conductive film  150 . 
         [0066]    At this stage, the first to third photosensitive film patterns  370   a  to  370   c  formed through the blocking region (III) are thicker than the fourth photosensitive film pattern  370   d  formed at the slit region (II). The photosensitive film at the region to which light has been almost entirely transmitted through the transmission region (I) is almost completely removed. For this process a positive photoresist is used. In alternate processes negative photoresist or a combination may be used. 
         [0067]    When the third conductive film  150  is patterned in which photosensitive film patterns  370   a  to  370   d  are used as masks ( FIG. 9C ), a third conductive film pattern  150 ′ formed of a third conductive film having a width narrower than a portion of the first photosensitive film pattern  370   a , the second photosensitive film pattern  370   b , and the fourth photosensitive film pattern  370   d  are formed. These patterns are formed at a lower portion of the first photosensitive film pattern  370   a , the second photosensitive film pattern  370   b , the fourth photosensitive film pattern  370   d , and the data line  117 . The data line  117  is formed of the third conductive film and has a width narrower than the other remaining portion of the first photosensitive film pattern  370   a  and the third photosensitive film pattern  370   c.    
         [0068]    When the n+ amorphous silicon thin film  125  and the first insulation film pattern  115 ′ are selectively patterned by a patterning process that may use photosensitive film patterns  370   a  to  370   d  as masks, as in  FIG. 9D , a first n+ amorphous silicon thin film pattern  125 ′ and a secondary insulation film pattern  115 ″ formed of the n+ amorphous silicon thin film and the second insulation film are formed. These elements are formed at the lower portion of the first photosensitive film pattern  370   a , the second photosensitive film pattern  370   b , and the fourth photosensitive film pattern  370   d . A second n+ amorphous silicon thin film pattern  125 ″ formed of the n+ amorphous silicon thin film is formed at the lower portion of the first photosensitive film pattern  370   a  and the third photosensitive film pattern  370   c . When an ashing process is performed to remove a portion of the photosensitive patterns  370   a  to  370   d , as in  FIG. 9E , the fourth photosensitive film pattern at the slit region (II) to which exposure occurs is almost completely removed. This removal expose the surface of the third conductive film pattern  150 ′. 
         [0069]    The first to third photosensitive film patterns, respectively, remain as fifth to seventh photosensitive film patterns  370   a ′ to  370   c ′. The thickness may be obtained by reducing the thickness of the fourth photosensitive film pattern only at a certain region corresponding to the blocking region (III) in some processes. The fifth to seventh photosensitive film patterns  370   a ′ to  370   c ′ may be reduced in their width through an ashing process. By controlling process conditions of the ashing process, the fifth to seventh photosensitive film patterns  370   a ′ to  370   c ′ may have about the same width as that of the lower third conductive film pattern  150 ′ and the data line  117 . 
         [0070]    In  FIG. 9F , when a portion of the third conductive film pattern is removed when the remaining fifth to seventh photosensitive film patterns  370   a ′ to  370   c ′ are used as masks, the source electrode  122  formed of a third conductive film is formed at a partial lower portion of the fifth sensitive film pattern  370   a ′. At the same time or nearly the same time the drain electrode  123  and the pixel electrode line  1181  formed of the third conductive film are formed at a lower portion of the sixth photosensitive film pattern  370   b′.    
         [0071]    When the first and second n+ amorphous silicon thin film patterns and the amorphous silicon thin film are selectively removed when using the fifth to seventh photosensitive film patterns  370   a ′ to  370   c ′ as masks, the active pattern  124 ′ are formed from the amorphous silicon thin film. The silicon patterns are patterned according to the side of the edge of the etch stopper  125 ′. In one process, the etch stopper  125 ′ is used as a mask in patterning the active pattern  124 ′, and the ohmic-contact layer  125 ′. The ohmic contact layer is formed of the n+ amorphous silicon thin film and ohmic-contacting a certain portion of the active pattern  124 ′. The source and drain electrodes  122  and  123  are formed at the upper portion of the active pattern  124 ′. 
         [0072]    The pixel electrode line  1181  is electrically connected with the lower connection electrode  130 ′″ through the ohmic-contact layer  125   n . The third n+ amorphous silicon thin film pattern  125 ′″ and the amorphous silicon thin film pattern  124 ″ are formed of the n+ amorphous silicon thin film and the amorphous silicon thin film is formed at the lower portion of the data line  117 . 
         [0073]    The amorphous silicon thin film pattern  124 ″ at the region where the second hole is formed is patterned in the same form as the upper data line  117 . When the active pattern  124 ′, the source and drain electrodes  122  and  123 , and the data line  117  are formed through the single masking process, few or no projections are formed at the amorphous silicon thin film pattern  124 ″ formed at the lower portion of the data line  117 . By minimizing or substantially eliminating the projections, noise and/or other interference may be minimized. The array substrate  110  is attached in a facing manner with a color filter substrate through a resin or a sealant positioned at an outer edge of an image display region to form a liquid crystal panel. The two substrates may be coupled or attached by an attachment key. The attachment key may be formed on the array substrate  110  and the color filter substrate. 
         [0074]    While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the invention. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.