Abstract:
A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Description:
BACKGROUND 
       [0001]    The invention relates to clock generation, and more particularly, to methods and systems for adjusting clock frequency. 
         [0002]    A clock generator is a circuit that produces a timing signal (known as a clock signal) for use in synchronizing operation of at least two hardware circuits. A clock generator generates symmetrical square waves to a number of electronic devices, such as central processing unit, north-bridge controller, south-bridge controller or others, to synchronize operations between these electronic devices. The clock generator can be configured to increase or decrease clock frequency. 
       SUMMARY 
       [0003]    Methods for adjusting clock frequency are disclosed. An embodiment of a method for adjusting clock frequency includes the following steps. A central processing unit (CPU) is halted while tuning a clock frequency, thereby enabling generation of multiple clock signals with the tuned clock frequency. 
         [0004]    Systems for adjusting clock frequency are provided. An embodiment of a system for adjusting clock frequency comprises a CPU and a chipset connecting to the CPU and comprising a south-bridge. The south-bridge comprises a microcontroller. The CPU is halted while the microcontroller tunes a clock frequency, thereby enabling to generate multiple clock signals with the tuned clock frequency. 
     
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0005]    The invention will become more fully understood by referring to the following detailed description with reference to the accompanying drawings, wherein: 
           [0006]      FIG. 1  is a diagram of a hardware environment of a system for adjusting clock frequency; 
           [0007]      FIG. 2   a  is a diagram illustrating exemplary frequency variations when a clock generator increasing clock frequency; 
           [0008]      FIG. 2   b  is a diagram illustrating exemplary frequency variations when a clock generator decreasing clock frequency; 
           [0009]      FIG. 3  is a diagram illustrating exemplary frequency variations tracked by a chipset when a clock generator increasing clock frequency; 
           [0010]      FIG. 4  is a flowchart illustrating a first embodiment of a method for adjusting clock frequency; 
           [0011]      FIG. 5  is a diagram illustrating exemplary frequency adjustment by a clock generator with reference to the first embodiment as shown in  FIG. 4 ; 
           [0012]      FIG. 6  is a flowchart illustrating a second embodiment of a method for adjusting clock frequency; 
           [0013]      FIG. 7  is a diagram illustrating exemplary frequency adjustment by a clock generator with reference to the second embodiment as shown in  FIG. 6 ; 
           [0014]      FIG. 8  is a flowchart illustrating a third embodiment of a method for adjusting clock frequency. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]      FIG. 1  is a diagram of a hardware environment of a system for adjusting clock frequency  100  comprising a clock generator  1100 , a central processing unit (CPU)  1300 , a chipset  1500  and a non-volatile memory  1700 . The chipset  1500  typically comprises a north-bridge  1510  and a south-bridge  1530 . The north-bridge  1510 , a controller, typically handles communications between the CPU  1300 , memory (not shown), AGP (accelerated graphics port, not shown) or PCI express, and the southbridge  1530 . The north-bridge  1510  connects to the CPU  1300  by CPU bus, and to the south-bridge  1530  by VLink bus. The south-bridge  1530  connects to the clock generator by SM Bus, known as system management bus. The clock generator  1100  generates symmetrical square waves (i.e. clock signals) with a frequency to the CPU  1300 , north-bridge  1510  and south-bridge  1530 , to synchronize operations therebetween. The south-bridge  1530  comprises a SM bus controller  1531 , a microcontroller  1511 , two timers  1535  and  1537 . A BIOS (basic input output system), a computer program, is executed by the CPU  1300  to direct the chipset  1500  to perform various tasks including adjusting clock frequency. 
         [0016]    When the SM bus controller  1531  issues a series of commands to the clock generator  1100  to increase or decrease clock frequency to a target level, the frequency of clock signals generated by the clock generator  1100  is smoothly increased or decreased to the target level as shown in  FIG. 2   a  or  FIG. 2   b . After issuing the commands to increase or decrease clock frequency, a PLL (phase-lock loop, not shown) disposed on the chipset  1500  tracks the frequency of clock signals generated by the generator  1100 . Jitters may be introduced by the chipset  1500  while tracking increasing clock signal frequencies of.  FIG. 3  is a diagram illustrating exemplary frequency variations tracked by the chipset  1500 . When introducing an excessive jitter as shown in t pulse  of  FIG. 3 , the tracking frequency may exceed an upper limit, resulting in malfunction of the chipset  1500 . That is, in the meantime, the chipset  1500  fails to execute commands issued by the CPU  1300  to perform particular tasks, resulting in an unexpected system shutdown. 
         [0017]    In order to avoid unexpected system shutdown, the invention halts the CPU  1300  while the chipset  1500  tracks clock frequency during adjustment (e.g. increased or decreased) by the clock generator  1100 .  FIG. 4  is a flowchart illustrating a first embodiment of a method for adjusting clock frequency. In step S 4110 , timers  1535  and  1537  ( FIG. 1 ) are set by the BIOS executed by the CPU  1300  ( FIG. 1 ). In step S 4130 , a clock frequency adjustment command is issued to the microcontroller  1533  in order to adjust (e.g. increase or decrease) clock frequency to a target level by the BIOS. In step S 4150 , the CPU  1300  is halted by the BIOS. Note that, when the CPU  1300  halts, the CPU  1300  can not issue any commands to direct the chipset  1500  to perform a particular task, thus, unexpected system shutdown while the chipset  1500  tracks clock frequency during adjustment by the clock generator  1100  ( FIG. 1 ) is prevented. In step S 4310 , the timer  1535  is activated by the microcontroller  1533  when receiving the clock frequency adjustment command, enabling the timer  1535  to start countdown. In step S 4330 , the SM bus controller  1531  is directed to issue a series of SM bus commands to the clock generator  1100  by the microcontroller  1533  after detecting that the timer  1535  reaches zero, directing the clock generator  110  to adjust clock frequency to the target level. Note that the timer  1535  is set to a relevant time, for example, about ten milliseconds (ms), by the BIOS in order to ensure that the BIOS can successfully halt the CPU  1300  before the timer  1535  reaches zero. In step S 4350 , the timer  1537  is activated by the microcontroller  1533  after detecting that the timer  1535  reaches zero, enabling the timer  1537  to start counting down. Note that the timer  1537  is set to a relevant time, for example, about twenty ms, by the BIOS in order to ensure that the clock generator  1100  can successfully adjust the clock frequency to the target level before the timer  1537  reaches zero. It is to be understood that the steps S 4330  and S 4350  may be simultaneously executed, or the S 4350  may be executed prior to the step S 4330 . In step S 4510 , an interrupt is triggered by the microcontroller  1533  in order to wake-up the CPU  1300  after detecting that the timer  1537  reaches zero, enabling the CPU  1300  to regain capability for directing the chipset  1500  to perform tasks. 
         [0018]      FIG. 5  is a diagram illustrating exemplary frequency adjustment by the clock generator  1100  with reference to the first embodiment as shown in  FIG. 4 . For example, steps S 4110  is performed before a time t 51  to set timers  1535  and  1537  ( FIG. 1 ). Steps S 4130  and S 4310  are performed at the time t 51  to activate the timer  1535 . The timer  1535  reaches zero at a time t 53 . Step S 4150  is performed at a time t 52  between a countdown duration by the timer  1535 , t 51  and t 53 . Steps S 4330  and S 4350  are performed at a time t 54  to activate the timer  1537  and direct the clock generator  110  ( FIG. 1 ) to adjust clock frequency to a target level. The timer  1537  reaches zero at a time t 55 . The clock frequency is successfully adjusted before the t 55 . Step S 4510  is performed at a time t 56  to wake-up the CPU  1300 . 
         [0019]      FIG. 6  is a flowchart illustrating a second embodiment of a method for adjusting clock frequency. In step S 6110 , timers  1535  and  1537  ( FIG. 1 ) are set by the BIOS executed by the CPU  1300  ( FIG. 1 ). The details of steps S 6130  to S 6150  may follow the description of steps S 4130  and S 4150 , and are only briefly described herein. The difference between this and the first embodiment as shown in  FIG. 4 , is the timer  1537  is set to a relevant time, for example, about thirty-five milliseconds (ms), by the BIOS in order to ensure that the BIOS can successfully halt the CPU  1300  and the clock generator  1100  can successfully adjust the clock frequency to the target level before the timer  1537  reaches zero. In step S 6310 , the timers  1535  and  1537  are simultaneously activated by the microcontroller  1533  after receiving the clock frequency adjustment command, enabling the timers  1535  and  1537  to start countdown. The details of steps S 6330  and S 6510  may follow the description of steps S 4330  and S 4510 , and are only briefly described herein. 
         [0020]      FIG. 7  is a diagram illustrating exemplary frequency adjustment by the clock generator  1100  with reference to the second embodiment as shown in  FIG. 6 . For example, step S 6110  is performed before a time t 71  to set timers  1535  and  1537  ( FIG. 1 ). Steps S 6130  and S 6310  are performed at the time t 71  to activate the timers  1535  and  1537 . The timer  1535  reaches zero at a time t 73 , and the timer  1537  reaches zero at a time t 75 . Step S 6150  is performed at a time t 72  between a countdown duration by the timer  1535 , t 71  and t 73 . Step S 6330  is performed at a time t 74  to direct the clock generator  110  ( FIG. 1 ) to adjust clock frequency to a target level. The clock frequency is successfully adjusted before between a countdown duration by the timer  1537 , t 71  and t 75 . Step S 6510  is performed at a time t 76  to wake-up the CPU  1300 . 
         [0021]    In a third embodiment, the non-volatile memory  1700  ( FIG. 1 ) stores a number of clock frequencies, such as 95, 100, 105, 110 and 120 MHz. The non-volatile memory  1700  may be an EEPROM (electrically erasable programmable read-only memory), a flash memory or similar.  FIG. 8  is a flowchart illustrating a third embodiment of a method for adjusting clock frequency. In step S 8110 , information indicating that one clock frequency is selected from the pre-stored clock frequencies as an initial clock frequency for the next booting is stored in the non-volatile memory  1700  ( FIG. 1 ) by software executed in the CPU  1300  ( FIG. 1 ). In step S 8130 , the entire system is powered down. In step S 8210 , the entire system is powered on. In step S 8230 , Reset# representing that the entire system resets is asserted by the microcontroller  1533  ( FIG. 1 ) of the south-bridge  1530  ( FIG. 1 ) before performing POST (power on self test), to halt the CPU  1300 . In step S 8250 , information regarding the selected clock frequency is acquired from the non-volatile memory  1700  by the microcontroller  1533 . In step S 8270 , the SM bus controller  1531  ( FIG. 1 ) is directed to issue a series of SM bus commands to the clock generator  1100  ( FIG. 1 ) by the microcontroller  1533 , enabling the clock generator  1100  to generate clock signals with the selected clock frequency. Note that, Reset# is continually asserted when performing steps S 8250  and S 8270 . In step S 8290 , the Reset# is de-asserted by the microcontroller  1533  after completely generating clock signals with the selected clock frequency, enabling the CPU  1300  to gain capability for directing the chipset  1500  ( FIG. 1 ) to perform tasks. 
         [0022]    Systems and methods, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine, such as a computer system and the like, the machine becomes an apparatus for practicing the invention. The disclosed methods and apparatuses may also be embodied in the form of program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to specific logic circuits. 
         [0023]    Certain terms are used throughout the description and claims to refer to particular system components. As one skilled in the art will appreciate, consumer electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. 
         [0024]    Although the invention has been described in terms of preferred embodiment, it is not limited thereto. Those skilled in this technology can make various alterations and modifications without departing from the scope and spirit of the invention. Therefore, the scope of the invention shall be defined and protected by the following claims and their equivalents.