Abstract:
A power supply system includes an a-c. power source and an off-line power supply for storing energy from the a-c. power source during first selected time intervals and converting at least a portion of the stored energy to a d-c. output during second selected time intervals. A diode or other switch disconnects the off-line power supply from the a-c. power source during the second selected time intervals to reduce conducted EMI. The first and second selected time intervals are preferably synchronized to the frequency of the a-c. power source.

Description:
FIELD OF THE INVENTION 
     The present invention relates generally to power supply systems and, more particularly, to off-line power supplies for supplying a d-c. output from an a-c. power source. A particularly useful application for the present invention is in bias supplies and other cost-sensitive applications such as appliances using microprocessors. 
     SUMMARY OF THE INVENTION 
     U.S. Pat. No. 5,790,390 describes a power supply system that includes an a-c. power source and an off-line power supply for storing energy from the a-c. power source during first selected time intervals and converting at least a portion of the stored energy to a d-c. output during second selected time intervals. A diode or other switch disconnects the off-line power supply from the a-c. power source during the second selected time intervals to reduce conducted EMI. The first and second selected time intervals are preferably synchronized to the frequency of the a-c. power source. 
     It is a primary object of the present invention to provide an improved off-line power supply of the general type described in the aforementioned patent but having improved efficiency. 
     Another important object of this invention is to provide an improved off-line isolated power supply which provides constant d-c. output power over a wide a-c. input voltage and temperature range. 
     It is yet another object of this invention to provide such an improved off-line power supply which is extremely reliable in operation, and can be made with a rugged construction. 
     Other objects and advantages of the invention will be apparent from the following detailed description and the accompanying drawings. In accordance with the present invention, the foregoing objectives are realized by providing a power supply system comprising an a-c. power source; an off-line power supply for storing energy from the a-c. power source during first selected time intervals and converting at least a portion of the stored energy to a d-c. output during second selected time intervals; means for disconnecting the off-line power supply from the a-c. power source during the second selected time intervals to reduce conducted EMI; and power-regulation means for preventing variations in the first and second selected time intervals due to a-c. input voltage and temperature variations. In the preferred embodiment of the invention, the power-regulation means is effective at operating a-c. input voltages ranging from 85 to 265 and temperatures ranging from below zero degrees C. to above 75 degrees C. 
     The off-line power supply of this invention preferably includes switching means for controlling the first and second selected time intervals, and energy-conserving means for storing energy for triggering the switching means during the second selected time intervals so as to avoid continuous power consumption during those intervals. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a bias-supply system embodying the invention; and 
     FIG. 2 is a schematic diagram of an alternative bias-supply system embodying the invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that it is not intended to limit the invention to the particular forms disclosed, but, on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the invention defined by the appended claims. 
     Turning now to the drawings, FIG. 1 illustrates a bias supply system for receiving a-c. power from an external source connected to a pair of input terminals  10   a  and  10   b  and supplying a regulated d-c. output at a pair of output terminals  11   a  and  11   b.  The a-c. signal from one input terminal is applied through a fuse F 1  and a resistor R 1  to the anode of a diode D 1  which functions as a half-wave rectifier to pass only the positive half cycles of the a-c. input. The resistor R 1  functions as a current-limiting resistor to limit the in-rush of energy from the input terminals when the diode D 1  is conducting. 
     From the diode D 1 , the rectified power input is passed to a storage capacitor C 1  to store the incoming energy. The capacitor C 1  is charged during each positive half cycle of the a-c. input, and is periodically discharged during the time intervals when D 1  is not conducting. This effectively disconnects the supply from the a-c. input line during the power transfer to the output. When the capacitor C 1  discharges, the stored energy flows through the primary winding L p  of a transformer T 1  connected in series with a FET Q 6 . The FET is controlled by a control circuit (described below) which controls the transfer of power to the d-c. output by turning the FET on and off. 
     The diode D 1  functions as a disconnect switch to disconnect the off-line power supply from the a-c. power source while the C 1  energy is being transferred to the output, which is when most of the conductive EMI is generated. Consequently, most of the conductive EMI generated by the off-line power supply is confined to the power supply itself, and cannot interfere with other circuits or devices. As will be apparent from the following description, most of the switching and inductive changes that produce EMI in the off-line power supply occur during the power transfer while the diode is in its disconnect mode. If desired, an active switching device may be used in place of the diode D 1 , which functions as a passive switch. 
     Whenever the FET Q 6  is turned on, current flows through the primary winding L p  of the transformer T 1  which stores energy as an inductor of inductance L p . This current ramps up to a peak value, I pk , which flows through a resistor R 2  connected between the FET Q 6  and common. I pk  produces a voltage across the resistor R 2  which causes the control circuit to turn off the FET Q 6 . With the FET Q 6  off, the magnetic field built up in the primary winding of the transformer T 1  collapses, and the energy present in the field is transferred to the secondary winding L s  of the transformer T 1 . This produces an output current which flows through a diode D 2  to the output terminal  11   a  and returning through terminal  11   b . A capacitor C 2  connected across the output terminals smoothes the output, and a zener diode D 3  in parallel with the capacitor C 2  regulates the output voltage. The diode D 2  prevents conduction in the secondary winding of the transformer T 1  while the capacitor C 1  is discharging through the primary winding. 
     The illustrative bias-supply system provides a constant power output. The control circuit  10  turns off the FET Q 6  when the voltage across the resistor R 2  builds up to a preselected level representing a maximum current value I pk  that is slightly below the level where the core of the transformer T 1  starts saturating. That is, the value of I pk  determines the power E out  stored in the primary winding L p , as can be seen from the following formula: 
     
       
           Eout= ½ L   p   I   pk   2    
       
     
     where L p  is the inductance of the primary winding of the transformer and I pk  is the maximum current through the resistor R 2 . 
     The control circuit controls the FET Q 6  to transfer energy from the capacitor C 1  to the transformer T 1  during a single time interval in each negative half cycle of the a-c. input. In this circuit, the voltage drop across a pair of resistors R 3  and R 4  determines when a transistor Q 1  is turned off, which occurs during positive half cycles of the a-c. input when the base-emitter voltage Vbe of the transistor Q 1  is positive. When the transistor Q 1  is off, the FET Q 6  and a pair of transistors Q 2  and Q 3  are held off while the capacitor C 1  is charging. During the negative half cycle of the a-c. input, the transistor Q 1  base-emitter voltage Vbe goes to negative, and Q 1  turns on, which enables the FET Q 6  to be turned on and the discharge of the capacitor C 1 . 
     The a-c. signal from one input terminal is applied through the resistors R 3  and R 4  to the anode of a diode D 4  which, like the diode D 1 , functions as a half-wave rectifier to pass only the positive half cycles of the a-c. input. From the diode D 4 , the rectified power input is passed to a storage capacitor C 3  to store the incoming energy. Like the capacitor C 1 , the capacitor C 3  is charged during each positive half cycle of the a-c. input. A zener diode D 5  limits the voltage across the capacitor C 3  and normalizes the stored charge relatively independent of the a-c. input voltage. When the transistor Q 1  turns on, the capacitor C 3  discharges through the emitter-collector circuit of the transistor Q 1  and a resistor R 5  to the gate of the FET. This circuit provides the necessary voltage to turn on the FET Q 6 . The capacitor C 3  and the zener D 5  are selected so that the capacitor C 3  stores only the amount of energy needed to turn on the FET Q 6  for the time interval required to reach the Ipk value. This improves the efficiency of the circuit by reducing the power consumption of the circuit. A capacitor C 4  connected across the diode D 4  filters the noise from the a-c. input power source. 
     When the FET Q 6  is on, current from the capacitor C 1  ramps through the FET Q 6  so as to convey energy to the primary winding of the transformer T 1 . The current ramp causes a transistor Q 3  to turn on when the voltage across R 2  builds up to the selected reference voltage Vref. When the transistor Q 3  turns on, it turns on the transistor Q 2 . The transistors Q 2  and Q 3  form a latch which turns off the FET Q 6  by pulling down the voltage at the gate connection of the FET Q 6 . This latch holds the FET Q 6  off until the capacitor C 3  is discharged and the supply current to the transistors Q 2  and Q 3  is depleted, thereby turning off the latch. Resistors R 6  and R 7  determine the current level at which the latch is turned off. A capacitor C 5  is connected in parallel with the resistor R 6  to reduce false triggering in the control circuit. When the FET Q 6  turns off, the magnetic field built up in the primary winding of the transformer T 1  collapses, and the energy in the primary winding transfers to the secondary winding. 
     A zener diode D 6  has its cathode connected to the gate of the FET Q 6  through R 5  to prevent the voltage at the gate of Q 6  from reaching a level which could damage Q 6  or cause improper operation. At the gate of the FET Q 6 , a diode D 7  is connected between the source and gate of the FET to protect against negative spikes, and another diode D 8  is connected in parallel with the resistor R 5  to cause the FET to turn off quickly when the voltage at the gate of the FET is reduced by the latch. 
     When the circuitry described thus far is used in applications involving a wide range of operating temperatures, the characteristics of the base-emitter junctions of the transistors Q 2  and Q 3  can vary with temperature, which in turn can change the time intervals during which the FET Q 6  is on and off. Specifically, the voltage at which the transistor Q 3  is turned on (the voltage across resistor R 7 ) can vary with temperature. To avoid such variations in the time intervals, a low-power comparator including a pair of transistors Q 4  and Q 5  is connected to the gate and source of the FET Q 6 . This comparator has the effect of producing a sharp step voltage change across the resistor R 7  so that the time at which the transistor Q 3  is turned on is always substantially the same, regardless of changes in the specific voltage level required to turn on the transistor Q 3  due to temperature changes. 
     The comparator includes a voltage divider formed by resistors R 8  and R 9 , which sets the comparator reference voltage Vref. This voltage divider applies a portion of the FET Q 6  turn-on voltage to the base of the transistor Q 4 , while the base of the second transistor Q 5  receives the voltage from the FET side of the resistor R 2 . When the voltage across the resistor R 2  builds up to equal the reference voltage Vref, the transistor Q 5  turns off and the transistor Q 4  turns on, directing the current, set by the resistor R 10 , to the resistor R 7 . The voltage developed across the resistor R 7  subsequently turns on the latch and turns off the FET Q 6 . The base-emitter voltages of both transistors Q 4  and Q 5  are sensitive to temperature, so they both change when the temperature changes, thereby preventing any change in the time intervals during which the FET is on or off due to temperature changes. 
     FIG. 2 illustrates a modified control circuit  10  for discharging the capacitor C 1  in multiple time increments within each negative half cycle of the a-c. input, rather than in a single increment as in the circuit of FIG.  1 . Discharging the capacitor C 1  in multiple time increments permits the discharge intervals to be shorter, with less energy per pulse, which in turn permits the use of a smaller transformer. This can be a significant advantage in applications having relatively large power requirements, which can cause the required transformer to become large in size. 
     In the circuit of FIG. 2, as in FIG. 1, the a-c. signal from one input terminal  10   a  is applied through a fuse F 1  and a resistor R 1  to the anode of a diode D 1  which functions as a half-wave rectifier to pass only the positive half cycles of the a-c. input. The resistor R 1  functions as a current-limiting resistor to limit the in-rush of energy from the input terminals when the diode D 1  is conducting. From the diode D 1 , the rectified power input is passed to a storage capacitor C 1  to store the incoming energy. The capacitor C 1  is charged during each positive half cycle of the a-c. input, and is periodically discharged during the time intervals when D 1  is not conducting. This effectively disconnects the supply from the a-c. input line during the power transfer to the output. When the capacitor C 1  discharges, the stored energy flows through the primary winding L p  of the transformer T 1  connected in series with an integrated circuit  20  containing a FET. 
     The integrated circuit  20  is an off-line switcher, such as the TNY253, 254 or 255 available from Power Integrations, Inc. of Sunnyvale, Calif. These integrated circuits include a high-voltage power MOSFET, an oscillator, a high-voltage switched current source, and current limit and thermal shutdown circuitry. The integrated circuit includes a drain pin D which is the drain connection to the MOSFET to provide internal operating current for both start-up and steady-state operation; a source pin S which is the source connection to the MOSFET; a bypass pin BP for connection to an external bypass capacitor C 10  for an internally generated supply, and an enable pin EN which enables the MOSFET to be turned on when the pin is high and permits the switching of the MOSFET to be terminated by pulling the pin low. As long as the enable pin EN remains high, the internal oscillator turns the MOSFET on at the beginning of each cycle of the oscillator output. The MOSFET is then turned off when the current ramps up to the current limit, and then on again at the beginning of the next cycle of the oscillator output. This cycling of the MOSFET on and off continues until the enable pin EN is pulled low. 
     Returning to FIG. 2, the voltage level on the enable pin EN is controlled by a transistor Q 10 . A pair of resistors R 10  and R 11  form a voltage divider which determines when the transistor Q 10  is turned on, which occurs when the voltage at the base of the transistor Q 10  reaches a selected threshold voltage V T1 . When the transistor Q 10  is on, the pin EN is pulled low to prevent switching of the MOSFET in the integrated circuit  20 . When the voltage at the base of the transistor Q 10  falls below the threshold voltage V T1 , the transistor Q 10  turns off, which causes the voltage on the enable pin EN to go high so that the MOSFET can be turned on at the beginning of the next cycle of the oscillator output. A resistor R 12  connected between the positive side of the capacitor C 1  and the pin EN determines the voltage level on the pin EN when the transistor Q 10  is off. 
     A zener diode D 10  has its cathode connected to the enable input EN of the integrated circuit  20  to prevent the voltage at the input EN from reaching a level which could damage the FET or cause improper operation. A capacitor C 10  is connected to ground from the BP terminal of the switching module  20  to reduce false triggering in that module. 
     While the invention has been described above with particular reference to the use of a fly-back power transfer system, it will be understood that other types of transfer systems may be used.