Abstract:
A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the to replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed is through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Description:
CROSS-REFERENCES TO RELATED APPLICATION 
       [0001]    The application is a continuation application of Ser. 13/602,257, filed Sep. 3, 2012, titled “SEMICONDUCTOR APPARATUS”, which is incorporated herein by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    1. Technical Field 
         [0003]    The present invention relates generally to a semiconductor integrated circuit, and more particularly, to a three-dimensional (3D) semiconductor apparatus. 
         [0004]    2. Related Art 
         [0005]    In order to meet high integration demands for semiconductor devices, a 3D semiconductor apparatus including a plurality of chips stacked and packaged inside a single package has been developed. Since the 3D semiconductor apparatus includes two or more chips stacked in a vertical direction, the higher integration levels may be provided without utilizing additional space. 
         [0006]    A variety of methods may be applied to implement the 3D semiconductor apparatus. One of the methods is to stack a plurality of chips having the same structure and connect the stacked chips through a metallic wire such that the stacked chips operate as one semiconductor apparatus. 
         [0007]    In particular, a chip stack method to form one semiconductor memory apparatus by stacking a plurality of semiconductor chips uses a through-chip via to transfer a signal in common to the plurality of semiconductor chips. In general, since a semiconductor chip is fabricated using a silicon wafer, the through-chip via may be referred to as a through-silicon via (TSV). 
         [0008]    In general, a semiconductor apparatus using the TSV may include a master chip and a plurality of slave chips which are electrically connected to the master chip through the TSV. In the case of a memory apparatus, the master chip includes all logic circuits in a peripheral circuit area for the operation of the memory apparatus, and the slave chips include a memory core to store data and circuits for a core operation, thereby operating as one is semiconductor apparatus. 
         [0009]    Although the 3D semiconductor apparatus includes a plurality of chips stacked therein, the plurality of chips share a data input/output line, in order to operate as a single semiconductor apparatus. In a semiconductor apparatus using wire connection, data outputted from a plurality of chips stacked therein may be transferred to a controller through one input/output line. In a semiconductor apparatus using a TSV, data of slave chips may be transferred to a master chip, and then outputted to the outside through a pad provided in the master chip. However, the semiconductor apparatus using a TSV has different signal transfer times and different driving abilities throughout the device, depending on the diameter and length of the TSV, thereby causing different performance levels among the individual chips. Therefore, it is necessary to measure a signal transfer time through the TSV. 
         [0010]      FIG. 1  is a diagram schematically illustrating the configuration of a conventional 3D semiconductor apparatus  10 . 
         [0011]    Referring to  FIG. 1 , the 3D semiconductor apparatus  10  includes a plurality of chips  11  to  13 , a plurality of TSVs  14  to  17  formed through the respective chips  11  to  13 , a plurality of connection pads BP 1  and BP 2  provided between the respective TSVs  14  to  17  and electrically connecting the corresponding TSVs, a plurality of external connection terminals BALL 1  and BALL 2  to electrically connect the plurality of chips  11  to  13  to a substrate  20 , and the substrate  20  electrically connected to the plurality of chips  11  to  13 . 
         [0012]    A TSV time delay measuring method of the conventional 3D semiconductor apparatus  10  is performed as follows: a total time delay is measured from where an input signal IN is transmitted to a specific external connection terminal to where the input signal IN is outputted to another external connection terminal, and is then divided by the number of TSVs  14  to  17  inside the 3D semiconductor apparatus  10 , in order to calculate the time delay of each TSV. 
         [0013]    However, the TSV time delay measuring method of the conventional 3D semiconductor apparatus  10  may not be accurate, since there is additional delay caused by the connection pads BP 1  and BP 2  or PVT (process, voltage, temperature) variation occurring in each chip while the input signal IN is transmitted. 
       SUMMARY 
       [0014]    In an embodiment of the present invention, a semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having a similar configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit. 
         [0015]    In another embodiment of the present invention, a semiconductor apparatus includes: a slave chip including having a signal transfer unit configured to determine whether to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit, a signal path selection unit configured to transmit the input signal to the signal transfer unit or the replica circuit unit in response to a control signal, and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and output an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the signal path selection unit and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    Features, aspects, and embodiments are described in conjunction with the attached drawings, in which: 
           [0017]      FIG. 1  is a diagram schematically illustrating the configuration of a conventional 3D semiconductor apparatus; 
           [0018]      FIG. 2  is a circuit diagram of a through-chip via delay measuring circuit according to an embodiment of the present invention; and 
           [0019]      FIG. 3  is a timing diagram of the through-chip via delay measuring circuit according to an embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Hereinafter, a semiconductor apparatus according to an embodiment of the present invention will be described below with reference to the accompanying drawings through various embodiments. 
         [0021]    In general, a 3D semiconductor apparatus may include a master chip and a plurality of slave chips. The plurality of slave chips are used as memory storage devices, and the master chip is used to control the plurality of slave chips. In order to select a desired slave chip, different chip IDs are allocated to the master chip and the plurality of slave chips. After the chip IDs are allocated to the respective chips, a system including the semiconductor apparatus to may input the chip select code to the semiconductor apparatus through a controller such that the semiconductor apparatus selects the desired chip. 
         [0022]      FIG. 2  is a circuit diagram of a through-chip via delay measuring circuit according to an embodiment of the present invention. The through-chip via may include a TSV. 
         [0023]    Referring to  FIG. 2 , the through-chip via delay measuring circuit according to embodiments of the present invention includes a plurality of TSVs  500 A and  500 B, a signal path selection unit  100 , a plurality of signal transfer units  200 A and  200 B, a replica circuit unit  300 , and a signal output unit  400 . 
         [0024]    The signal path selection unit  100 , the signal transfer unit  200 A, the replica circuit unit  300 , and the signal output unit  400  are included in a master chip, and the second transfer unit  200 B is included in a slave chip. 
         [0025]    The signal path selection unit  100  is configured to output an input signal IN to a first or second node n 1  or n 2  in response to a control signal CTRL. The first node n 1  is connected to the first signal transfer unit  200 A and the first TSV  500 A, which in turn is connected to the second signal transfer unit  200 B. The second node n 2  is connected to the replica circuit unit  300 . The control signal CTRL is generated using a test mode signal, and may be used to select a path to transmit the input signal IN to either the slave chip or the master chip. 
         [0026]    The signal path selection unit  100  includes a first controller  110  and a first driver  120 . The first controller  110  includes a first NAND gate ND 1 , a first inverter IV 1 , a first NOR gate NR 1 , a second inverter IV 2 , a second NAND gate ND 2 , a third inverter IV 3 , and a second NOR gate NR 2 . The first NAND gate ND 1  is configured to perform a NAND operation on the input signal IN and the control signal CTRL. The first inverter IV 1  is configured to invert and output the control signal CTRL. The first NOR gate NR 1  is configured to perform a NOR operation on an output signal of the first inverter and the input signal IN. The second inverter IV 2  is configured to invert and output the control signal CTRL. The second NAND gate ND 2  is configured to perform a NAND operation on an output signal of the second inverter IV 2  and the input signal IN. The third inverter IV 3  is configured to invert and output the control signal CTRL. The second NOR gate NR 2  is configured to perform a NOR operation on an output signal of the third inverter IV 3  and the input signal IN. 
         [0027]    The first driver  120  includes a first PMOS transistor P 1 , a first NMOS transistor N 1 , a second PMOS transistor P 2 , and a second NMOS transistor N 2 . The first PMOS transistor P 1  is connected between a driving voltage terminal VDD and the first node n 1  and configured to receive an output signal of the first NAND gate ND 1 . The first NMOS transistor N 1  is connected between the first node n 1  and a ground voltage VSS and configured to receive an output signal of the first NOR gate NR 1 . The second PMOS transistor P 2  is connected between the driving voltage terminal VDD and the second node n 2  and configured to receive an output signal of the NAND gate ND 2 . The second NMOS transistor N 2  is connected between the second node N 2  and the ground voltage VSS and configured to receive an output signal of the second NOR gate NR 2 . 
         [0028]    The signal path selection unit  100  outputs the input signal IN to the first node n 1  when the control signal CTRL is activated, and outputs the input signal IN to the second node n 2  when the control signal CTRL is deactivated. 
         [0029]    The first signal transfer unit  200 A includes a second controller  210 A and a second driver  220 A, and is configured to determine whether to transfer the signal outputted from the signal path selection unit  100  to the signal output unit  400 , in response to a first chip select signal TOP 1 . 
         [0030]    The second signal transfer unit  200 B includes a third controller  2108  and a third driver  220 B. The second signal transfer unit  200 B is configured to determine whether to transfer a signal inputted through the first TSV  500 A to the second TSV  500 B, in response to a second chip select signal TOP 2 . 
         [0031]    The first and second chip select signals TOP 1  and TOP 2  are generated from chip IDs which are allocated to the plurality of semiconductor chips included in the semiconductor apparatus. s Therefore, the number of chip select signals may correspond to the number of semiconductor chips included in the semiconductor apparatus. In this embodiment of the present invention, since the master chip and the slave chip are taken as an example, first and second chip select signals TOP 1  and TOP 2  are used. 
         [0032]    Each of the first and second chip select signals TOP 1  and TOP 2  inputted to the signal transfer units  200 A and  200 B are inputted in an activated state to enable the corresponding signal transfer units when a semiconductor chip including the signal transfer unit is stacked at the uppermost layer among the plurality of semiconductor chips, or inputted in a deactivated state to disable the corresponding signal transfer unit when a semiconductor chip including the signal transfer unit is not stacked at the uppermost layer. 
         [0033]    For example, a slave chip including the second signal transfer unit  200 B may be stacked at the uppermost layer among the plurality of slave chips. 
         [0034]    The second signal transfer unit  200 B to which the activated second chip select signal TOP 2  is inputted is enabled, and the first signal transfer unit  200 A to which the deactivated first chip select signal TOP 1  is inputted is disabled. 
         [0035]    The first TSV  500 A, which transfers a signal to the second signal transfer unit  200 B included in the semiconductor chip stacked at the uppermost layer among the plurality of semiconductor chips, may include a plurality of TSVs, because the signal passes through the plurality of TSVs included in other semiconductor chips. Similarly, the second TSV  500 B, which transfers a signal outputted from the second signal transfer unit  200 B, may include a plurality of TSVs, because the signal passes through the plurality of TSVs included in other semiconductor chips. 
         [0036]    The second controller  210 A includes a third NAND gate ND 3 , a fourth inverter IV 4 , a fourth NAND gate ND 4 , a fifth inverter IV 5 , and a third NOR gate NR 3 . The third NAND gate ND 3  is configured to perform a NAND operation on an output signal of the first node n 1  and the first chip select signal TOP 1 . The fourth inverter IV 4  is configured to invert and output an output signal of the third NAND gate ND 3 . The fourth NAND gate ND 4  is configured to perform a NAND operation on an output signal of the fourth inverter IV 4  and the first chip select signal TOP 1 . The fifth inverter IV 5  is configured to invert and output the first chip select signal TOP 1 . The third NOR gate NR 3  is configured to perform a NOR operation on an output signal of the fifth inverter IV 5  and an output signal of the fourth inverter IV 4 . 
         [0037]    The second driver  220 A includes a third PMOS transistor P 3  and a third NMOS transistor N 3 . The third PMOS transistor P 3  is connected between the driving voltage terminal VDD and a third node n 3  and configured to receive an output signal of the fourth NAND gate ND 4 . The third NMOS transistor N 3  is connected between the third node n 3  and the ground voltage VSS and configured to receive an output signal of the third NOR gate NR 3 . 
         [0038]    When the activated second chip select signal TOP 2  is inputted to the second signal transfer unit  200 B, a signal inputted through the first TSV  500 A from the signal path selection unit  100  is outputted to the third n 3  through the second TSV  500 B. Furthermore, the first chip select signal TOP 1  inputted to the first signal transfer unit  200 A included in the master chip is deactivated, at which point . the output signal of the first node n 1  is not outputted to the third node n 3  through the first signal transfer unit  200 A. Therefore, the second chip select signal TOP 2  enables the second signal transfer unit  220 B of the slave chip, and the first chip select signal TOP 1  disables the first signal transfer unit  200 A of the master chip, thereby transferring the signal outputted from the signal path selection unit  100  through the TSVs. 
         [0039]    The second signal transfer unit  200 B includes a third controller  210 B and a third driver  220 B. The third controller  210 B includes a tenth NAND gate ND 10 , a ninth inverter IV 9 , an eleventh NAND gate ND 11 , a tenth inverter IV 10 , and a fifth NOR gate NR 5 . The tenth NAND gate ND 10  is configured to perform a NAND operation on the signal outputted from the first TSV  500 A and the second select signal TOP 2 . The ninth inverter IV 9  is configured to invert an output signal of the tenth NAND gate ND 10 . The eleventh NAND gate ND 11  is configured to perform a NAND operation on an output signal of the ninth inverter IV 9  and the second chip select signal TOP 2 . The tenth inverter IV 10  is configured to invert the second chip select signal TOP 2 . The fifth NOR gate NR 5  is configured to perform a NOR operation on an output signal of the tenth inverter IV 10  and an output signal of the ninth inverter IV 9 . The third driver  220 B includes a fifth PMOS transistor P 5  and a fifth NMOS transistor N 5 . The fifth PMOS transistor P 5  is connected between the driving voltage terminal VDD and a fourth node n 4  and configured to receive an output signal of the eleventh NAND gate ND 11 . The fifth NMOS transistor N 5  is connected between the fourth node n 4  and the ground voltage VSS and configured to receive an output signal of the fifth NOR gate NR 5 . 
         [0040]    The second signal transfer unit  200 B outputs the output signal of the first node n 1 , received through the first TSV  500 A, to the fourth node n 4  in response to the second chip select signal TOP 2 . Since the fourth node n 4  is connected to the second TSV  500 B, an output signal of the fourth node n 4  is transferred to the third node n 3  and then inputted to the signal output unit  400 . 
         [0041]    The replica circuit unit  300  is configured to output the output signal of the second node n 2  to the fifth node n 5  in response to the control signal CTRL by modeling the second signal transfer unit  200 B of the slave chip, and determines whether to transfer a signal in response to the control signal CTRL. The replica circuit unit  300  transfers a signal outputted from the signal transfer selection unit  100  to the signal output unit  400 . Therefore, when the signal outputted from the first node n 1  and outputted through the first TSV  500 A, the second transfer unit  200 B, and the second TSV  500 B is compared to a signal outputted from the second node n 2  and outputted through the replica circuit unit  300 , it is possible to measure delay amounts of the first and second TSVs  500 A and  500 B. 
         [0042]    The replica circuit unit  300  includes a fourth controller  310  and a fourth driver  320 . The fourth controller  310  includes an eleventh inverter IV 11 , a fifth NAND gate ND 5 , a sixth inverter IV 6 , a fourth NOR gate NR 4 , a seventh inverter IV 7 , and a sixth NAND gate ND 6 . The eleventh inverter IV 11  is configured to invert the control signal CTRL. The fifth NAND gate ND 5  is configured to perform a NAND operation on the output signal of the second node n 2  and an output signal of the eleventh inverter IV 11 . The sixth inverter IV 6  is configured to invert the fifth NAND gate ND 5 . The fourth NOR gate NR 4  is configured to perform a NOR operation on an output signal of the sixth inverter IV 6  and the control signal CTRL. The seventh inverter IV 7  is configured to invert the control signal CTRL. The sixth NAND gate ND 6  is configured to perform a NAND operation on an output signal of the seventh inverter IV 7  and the output signal of the sixth inverter IV 6 . The fourth driver  320  includes a fourth PMOS transistor P 4  and a fourth NMOS transistor N 4 . The fourth PMOS transistor P 4  is connected between the driving voltage terminal VDD and the fifth node n 5  and configured to receive an output signal of the sixth NAND gate ND 6 . The fourth NMOS transistor N 4  is connected between the fifth node n 5  and the ground voltage VSS and configured to receive an output signal of the fourth NOR gate NR 4 . 
         [0043]    When the control signal CTRL is activated, the replica circuit unit  300  does not transfer the output signal of the signal path selection unit  100  to the signal output unit  400 . However, when the control signal CTRL is deactivated, the replica circuit unit  300  transfers the output signal of the signal path selection unit  100  to the signal output unit  400 . 
         [0044]    The signal output unit  400  is configured to receive the output signal of the third or fifth node n 3  or n 5  and output an output signal OUT in response to the control signal CTRL, receives the output signal of the third node n 3  when the control signal CTRL is activated, and receives the output signal of the fifth node n 5  to output the output signal OUT when the control signal CTRL is deactivated Therefore, the signal output unit  400  selectively outputs the signal outputted through the path of the first TSV  500 A, the second signal transfer unit  200 B, and the second TSV  500 B from the first node n 1  or the signal outputted through the replica circuit unit  300  from the second node n 2 , in response to the control signal CTRL. 
         [0045]      FIG. 3  is a timing diagram of the through-chip via delay measuring circuit according to an embodiment of the present invention. 
         [0046]    Referring to  FIGS. 2 and 3 , the operation of the through-chip via delay measuring circuit according to an embodiment of the present invention will be described as follows. 
         [0047]    The input signal IN is a pulse signal having a predetermined cycle. When the signal path selection unit  100  receives the high-level input signal IN and the high-level control signal CTRL, the operation of the through-chip via delay measuring circuit is performed as follows. 
         [0048]    When the high-level input signal IN and the high-level control signal CTRL are inputted to the first controller  110 , the first NAND gate ND 1  outputs a low level signal, the first NOR gate NR 1  outputs a low level signal, the second NAND gate ND 2  outputs a high level signal, and the second NOR gate NR 2  outputs a low level signal. The first PMOS transistor P 1  of the first driver  120  is turned on to drive the first node n 1  to the driving voltage level VDD. Furthermore, the second PMOS transistor P 2  and the first and second NMOS transistor N 1  and N 2  of the first driver  120  are turned off. Since the first PMOS transistor P 1  of the first driver  120  is turned on and the first NMOS transistor N 1  of the first driver  120  is turned off, the first node n 1  is driven to a high level. Furthermore, no signal is outputted to the second node n 2 . 
         [0049]    The first signal transfer unit  200 A determines whether to output the high-level output signal of the first node n 1  to the third node n 3 , in response to the first chip select signal TOP 1 . 
         [0050]    Among the plurality of chip select signals, only a chip select signal inputted to the semiconductor chip stacked at the uppermost layer among the plurality of semiconductor chips has a high level, and the other chip select signals inputted to the other semiconductor chips have a low level. In this embodiment of the present invention, the first chip select signal TOP 1  becomes a low level, and the second chip select signal TOP 2  becomes a high level. 
         [0051]    Referring back to  FIG. 2 , the first signal transfer unit  200 A included in the master chip determines whether to output the high-level output signal of the first node n 1  to the third node n 3 , in response to the low-level first chip select signal TOP 1 . 
         [0052]    The second controller  210 A receives the high-level output signal of the first node n 1  and the low-level first chip select signal TOP 1 , and controls the fourth NAND gate ND 4  and the third NOR gate NR 3  to output a high-level signal and a low-level signal, respectively. 
         [0053]    The third PMOS transistor P 3  of the second driver  220 A is turned off by receiving the high-level output signal of the fourth NAND gate ND 4 . Furthermore, the third NMOS transistor N 3  of the second driver  220 A is turned off by receiving the low-level output signal of the third NOR gate NR 3 . Therefore, the first signal transfer unit  200 A does not transfer the output signal of the first node n 1  to the third node n 3 . 
         [0054]    The second signal transfer unit  200 B determines whether to output the output signal of the first node n 1 , inputted through the first TSV  500 A, to the fourth node n 4  in response to the second chip select signal TOP 2 . The output signal from the fourth node n 4  is inputted to the third node n 3  through the second TSV  500 B. 
         [0055]    The third controller  210 B of the second transfer unit  200 B receives the high-level output signal of the first node n 1 , inputted through the first TSV  500 A, and the high-level second chip select signal TOP 2 . The third controller  210 B performs a logical operation on the high-level output signal of the first node n 1  and the high-level second chip select signal TOP 2 , and outputs low-level signals to the eleventh ND 11  and the fifth NOR gates NR 5 , respectively. The fifth PMOS transistor P 5  of the third driver  220 B is turned on to drive the fourth node n 4  to the driving voltage level VDD. Furthermore, the fifth NMOS transistor N 5  is turned off. Therefore, since the fifth PMOS transistor P 5  of the third driver  220 B is turned on and the fifth NMOS transistor N 5  of the third driver  220 B is turned off, the fourth node n 4  is driven to a high level. 
         [0056]    The signal output unit  400  receives the output signal of the third or fifth node n 3  or n 5  and outputs the output signal OUT in response to the control signal CTRL. The output signal of the fourth node n 4  is transferred to the third node n 3  through the second TSV  500 B. The signal output unit  400  receives the high-level output signal of the third node n 3 . 
         [0057]    The signal output unit  400  includes a seventh NAND gate ND 7 , an eighth inverter IV 8 , an eighth NAND gate ND 8 , and a ninth NAND gate ND 9 . The seventh NAND gate ND 7  is configured to perform a NAND gate on the output signal of the third node n 3  and the control signal CTRL. The eighth inverter IV 8  is configured to invert the control signal CTRL. The eighth NAND gate ND 8  is configured to perform a NAND operation on an output signal of the eighth inverter IV 8  and the output signal of the fifth node n 5 . The ninth NAND gate ND 9  is configured to perform a NAND operation on an output signal of the seventh NAND gate ND 7  and an output signal of the eighth NAND gate ND 8 . 
         [0058]    The seventh NAND gate ND 7  performs a logical operation on the high-level output signal of the third node n 3  and the high-level control signal CTRL, and outputs a low level signal. The ninth NAND gate ND 9  outputs the high-level output signal OUT in response to the low-level output signal of the seventh NAND gate ND 7 . 
         [0059]    When the output signal OUT outputted from the signal output unit  400  is compared to the input signal IN, the output signal OUT is delayed by a first delay amount A from the input signal IN. 
         [0060]    The first delay amount A is a delay amount which is generated by the first TSV  500 A, the second signal transfer unit  200 B, and the second TSV  500 B when the input signal IN transits from a low level to a high level. 
         [0061]    When the signal path selection unit  100  receives the low-level input signal IN and the high-level control signal CTRL, the operation of the through-chip via delay measuring circuit is performed as follows. 
         [0062]    When the low-level input signal IN and the high-level control signal CTRL are inputted to the first controller  110 , the first NAND gate ND 1  outputs a high level signal, the first NOR gate NR 1  outputs a high level signal, the second NAND gate ND 2  outputs a high level signal, and the second NOR gate NR 2  outputs a high level signal. The first NMOS transistor N 1  of the first driver  120  is turned on to pull down the first node n 1  to the ground voltage level VSS. Since the first NMOS transistor N 1  of the first driver  120  is turned on and the first PMOS transistor P 1  of the first driver  120  is turned off, the first node n 1  is driven to a low level. 
         [0063]    Furthermore, the second PMOS transistor P 2  is turned off, and the second NMOS transistor N 2  is turned on to pull down the second node n 2  to the ground voltage level VSS. Therefore, since the second NMOS transistor N 2  of the first driver  120  is turned on and the second PMOS transistor P 2  of the first driver  120  is turned off, the second node n 2  is driven to a low level. 
         [0064]    The first signal transfer unit  200 A determines whether to output the low-level output signal of the first node n 1  to the third node n 3 , in response to the first chip select signal TOP 1 . The first signal transfer unit  200 A included in the master chip determines whether to output the low-level output signal of the first node n 1  to the third node n 3 , in response to the low-level first chip select signal TOP 1 . 
         [0065]    The second control unit  210 A receives the low-level output signal of the first node n 1  and the low-level first chip select signal TOP 1 , and controls the fourth NAND gate ND 4  and the third NOR gate NR 3  to output a high level signal and a low level signal, respectively. 
         [0066]    The third PMOS transistor P 3  of the second driver  220 A is turned off by receiving the high-level output signal of the fourth NAND gate ND 4 . Furthermore, the third NMOS transistor N 3  of the second driver  220 A is turned off by receiving the low-level output signal of the third NOR gate NR 3 . Therefore, the first signal transfer unit  200 A does not transfer the output signal of the first node n 1  to the third node n 3 . 
         [0067]    The fourth controller  310  of the replica circuit  300  receives the low-level output signal of the second node n 2  and the high-level control signal CTRL, and controls the sixth NAND gate ND 6  and the fourth NOR gate NR 4  to output a high level signal and a low level signal, respectively. 
         [0068]    The fourth PMOS transistor P 4  of the fourth driver  320  is turned off by receiving the high-level output signal of the sixth NAND gate ND 6 . Furthermore, the fourth NMOS transistor N 4  of the fourth driver  320  is turned off by receiving the low-level output signal of the fourth NOR gate NR 4 , preventing the replica circuit  300  from transferring the output signal of the second node n 2  to the fifth node n 5 . 
         [0069]    The second signal transfer unit  200 B determines whether to output the output signal of the first node n 1 , inputted through the first TSV  500 A, to the fourth node n 4  in response to the second chip select signal TOP 2 . The output signal from the fourth node n 4  is inputted to the third node n 3  through the second TSV  500 B. 
         [0070]    The third control unit  210 B of the second signal transfer unit  200 B receives the low-level output signal of the first node n 1 , inputted through the first TSV  500 A, and the high-level second chip select signal TOP 2 , and performs a logical operation on the low-level output signal of the first node n 1  and the high-level second chip select signal TOP 2 , and outputs high level signals to the fifth NAND gate ND 11  and the fifth NOR gate NR 5 , respectively. The fifth NMOS transistor N 5  of the third driver  220 B is turned on to pull down the fourth node n 4  to the ground voltage level VSS, and the fifth PMOS transistor P 5  is turned off, thereby driving the fourth node n 4  to a low level. 
         [0071]    The signal output unit  400  receives the output signal of the third or fifth node n 3  or n 5 , and outputs the output signal OUT in response to the control signal CTRL. The output signal of the fourth node n 4  is transferred to the third node n 3  through the second TSV  500 B. The signal output unit  400  receives the low-level output signal of the third node n 3 . 
         [0072]    The signal output unit  400  includes the seventh NAND gate ND 7  configured to perform the output signal of the third node n 3  and the control signal CTRL, the eighth inverter IV 8  configured to invert the control signal CTRL, the eighth NAND gate ND 8  configured to perform a NAND operation on an output signal of the eighth inverter IV 8  and the output signal of the fifth node n 5 , and the ninth NAND gate ND 9  configured to perform a NAND operation on an output signal of the seventh NAND gate ND 7  and an output signal of the eighth NAND gate ND 8 . 
         [0073]    The seventh NAND gate ND 7  performs a NAND operation on the low-level output signal of the third node n 3  and the high-level control signal CTRL, and outputs a high level signal. The eighth NAND gate ND 8  receives the low-level control signal CTRL inverted by the eighth inverter IV 8 , and outputs a high level signal. The ninth NAND gate ND 9  outputs the output signal OUT in response to the high-level output signal of the seventh NAND gate ND 7  and the high-level output signal of the eighth NAND gate ND 8 . 
         [0074]    When the output signal OUT outputted from the signal output unit  400  is compared to the input signal IN, the output signal OUT is delayed by a second delay amount B from the input signal IN, which is a delay amount generated by the first TSV  500 A, the second signal transfer unit  200 B, and the second TSV  500 B when the input signal IN transits from a high level to a low level. 
         [0075]    When the signal path selection unit  100  receives the high-level input signal IN and the low-level control signal CTRL, the operation of the through-chip via delay measuring circuit is performed as follows. 
         [0076]    When the high-level input signal IN and the low-level control signal CTRL are inputted to the first controller  110 , the first NAND gate ND 1  outputs a high level signal, the first NOR gate NR 1  outputs a low level signal, the second NAND gate ND 2  outputs a low level signal, the second NOR gate NR 2  outputs a low level signal, and the second PMOS transistor P 2  of the first driver  120  is turned on to drive the second node n 2  to the driving voltage level VDD. Therefore, since the second PMOS transistor P 2  of the first driver  120  is turned on and the second NMOS transistor N 2  of the first driver  120  is turned off, the second node n 2  is driven to a high level. 
         [0077]    Since the first PMOS transistor P 1  and the first NMOS transistor N 1  are turned off, the signal path selection unit  100  does not output a signal to the first node n 1 . 
         [0078]    The fourth controller  310  of the replica circuit unit  300  receives the high-level output signal of the second node n 2  and the low-level control signal CTRL, and controls the sixth NAND gate ND 6  and the fourth NOR gate NR 4  to output low level signals, respectively. 
         [0079]    The fourth NMOS transistor P 4  of the fourth driver  320  is turned on by receiving the low-level output signal of the sixth NAND gate ND 6 , and drives the fifth node n 5  to the driving voltage level VDD. The fourth NMOS transistor N 4  of the fourth driver  320  is turned off by receiving the low-level output signal of the fourth NOR gate NR 4 . Therefore, since the fourth PMOS transistor P 4  of the fourth driver  320  is turned on and the fourth NMOS transistor N 4  of the fourth driver  320  is turned off, the fifth node n 5  is driven to a high level. 
         [0080]    The signal output unit  400  includes the seventh NAND gate ND 7  configured to perform the output signal of the third node n 3  and the control signal CTRL, the eighth inverter IV 8  configured to invert the control signal CTRL, the eighth NAND gate ND 8  configured to perform a NAND operation on an output signal of the eighth inverter IV 8  and the output signal of the fifth node n 5 , and the ninth NAND gate ND 9  configured to perform a NAND operation on an output signal of the seventh NAND gate ND 7  and an output signal of the eighth NAND gate ND 8 . 
         [0081]    The seventh NAND gate ND 7  performs a NAND operation on the output signal of the third node n 3  and the low-level control signal CTRL, and outputs a high level signal. The eighth inverter IV 8  inverts and outputs the low-level control signal CTRL. The eighth NAND gate ND 8  performs a NAND operation on an output signal of the eighth inverter IV 8  and the high-level output signal of the fifth node n 5 , and outputs a low level signal. The ninth NAND gate ND 9  outputs the high-level output signal OUT in response to the high-level output signal of the seventh NAND gate ND 7  and the low-level output signal of the eighth NAND gate ND 8 . 
         [0082]    When the output signal OUT outputted from the signal output unit  400  is compared to the input signal IN, the output signal OUT is delayed by a third delay amount C from the input signal IN, which is a delay amount of the input signal IN passing through the replica circuit unit  300 , when the input signal IN transits from a low level to a high level. Since the replica circuit unit  300  is a circuit configured by modeling the second signal transfer unit  200 B, the third delay amount C corresponds to a delay amount generated by the second signal transfer unit  200 B. 
         [0083]    When the signal path selection unit  100  receives the low-level input signal IN and the low-level control signal CTRL, the operation of the through-chip via delay measuring circuit is performed as follows. 
         [0084]    When the low-level input signal IN and the low-level control signal CTRL are inputted to the first controller  110 , the first NAND gate ND 1  outputs a high level signal, the first NOR gate NR 1  outputs a low level signal, the second NAND gate ND 2  outputs a high level signal, the second NOR gate NR 2  outputs a low level signal, the first PMOS transistor P 1 , the second PMOS transistor P 2 , the first NMOS transistor N 1 , and the second NMOS transistor N 2  of the first driver  120  are turned off, and do not output a signal to the first or second node n 1  or n 2 . The output signal OUT becomes a high level signal delayed by a fourth delay amount D from the input signal IN. 
         [0085]    In other words, when the input signal IN transits from a high level to a low level in a state where the control signal CTRL is at a low level, the signal output unit  400  outputs the low-level output signal OUT delayed by the fourth delay amount D. 
         [0086]    The fourth delay amount D is a delay amount of the input signal IN passing through the replica circuit unit  300 , when the input signal IN transits from a high level to a low level. Since the replica is circuit unit  300  is a circuit configured by modeling the second signal transfer unit  200 B, the fourth delay amount D corresponds to a delay amount generated by the second signal transfer unit  200 B. 
         [0087]    Specifically, the first delay amount A is a delay amount which is generated by the first TSV  500 A, the second signal transfer unit  200 B, and the second TSV  500 B when the input signal IN transits from a low level to a high level, and the third delay amount C is a delay amount of the input signal IN passing through the replica circuit unit  300  when the input signal IN transits from a low level to a high level. Since the replica circuit unit  300  is a circuit configured by modeling the second signal transfer unit  200 B, the third delay amount C corresponds to a delay amount generated by the second signal transfer unit  200 B. Therefore, when the third delay amount C is subtracted from the first delay amount A, it is possible to measure a delay amount caused by the first and second TSVs  500 A and  500 B when the input signal IN transits from a low level to a high level. 
         [0088]    The second delay amount B is a delay amount which is generated by the first TSV  500 A, the second signal transfer unit  200 B, and the second TSV  500 B when the input signal IN transits from a high level to a low level, and the fourth delay amount D is a delay amount of the input signal IN passing through the replica circuit unit  300  when the input signal IN transits from a high level to a low level. Since the replica circuit unit  300  is a circuit configured by modeling the second signal transfer unit  200 B, the fourth delay amount D corresponds to a delay amount generated by the second signal transfer unit  200 B. Therefore, when the fourth delay amount D is subtracted from the second delay amount B, it is possible to measure a delay amount caused by the first and second TSVs  500 A and  500 B when the input signal IN transits from a high level to a low level. 
         [0089]    While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the semiconductor apparatus described herein should not be limited based on the described embodiments and the semiconductor apparatus may be interpreted a computer system, a SIMM(single in-line memory module) or a DIMM (dual in-line memory module). Rather, the semiconductor apparatus described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.