Abstract:
An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to frequency synthesizers and in particular to an all digital frequency synthesizer and especially to techniques for design of all digital frequency synthesizers using standard automated logic design systems. 
     2. Description of Related Art 
     It is well known in the art that a multiple number of frequencies can be generated from a single source. These techniques may be either analog or digital and may have output signals that are either analog sine waves or purely digital pulse trains. 
     A typical application for a frequency synthesizer is a phase locked loop. In a phase locked loop the output of the frequency synthesizer is compared to a reference signal. An error signal that represents the difference in the phase and frequency of the output of the frequency synthesizer and the reference signal is used to vary the frequency of the frequency synthesizer. The error signal is passed through a loop filter to eliminate any response to unwanted transient signals. As the error signal approaches zero, the phase locked loop is said to be locked. 
     A digital phase locked loop originally contained a binary reference signal and a binary output signal with an analog frequency synthesizer, loop filter and comparator. As digital circuits have improved in performance, the components may now be implemented in digital circuitry or a software program on a microcomputer. 
     FIG. 1 shows a block diagram of an all digital phase locked loop as described in Phase Locked Loops: Theory, Design, and Application by Best, McGraw-Hill Inc. 1993. The phase detector compares the output u 2  &#39; of the digital control oscillator DCO with the digital reference signal u 1 . The output of the phase detector is connected to the DN/UP input of the counter which forms the loop filter. The K clock is an input to the K counter that is frequency that is a frequency that is a factor M times the desired output frequency F o  of the digital controlled oscillator DCO. The K Modulus Control sets the number at which the K counter will have a carry signal. 
     The DN/UP input to the K counter causes the K counter to count up to the value of the K Modulus if the DN/UP input has a level to activate the up counting. The DN/UP input causes the K counter to count down to zero if the DN/UP input has a level to activate the down counting. If the K counter exceeds the value of the K Modulus, the carry output is activated. If the K counter is decremented to less than zero, the borrow output is activated. 
     If the signals u 1  and u 2  &#39; are of identical frequency and phase, the output of the phase detector will be a square wave. This will cause the K counter to count up for the first level of the square wave and to count down for the second level of the square wave. As long as the DN/UP input signal is a balanced square wave, neither the carry or the borrow outputs will be triggered. If the signals u 1  and u 2  &#39; become out of phase and of unequal frequency, the period of the signal at the DN/UP input will not have equal period at the first level versus the second level and there will eventually be either a carry or a borrow signal. 
     The digital control oscillator DCO has and increment/decrement counter (ID counter). The ID clock input of the ID counter is a frequency that is a fraction of two times a factor N times the frequency F o  of the output signal u 2  &#39;. The output ID out will be a frequency that is one half of the input ID clock. 
     The carry output of the Loop Filter is connected to the increment input INC of the ID counter and the borrow output of the Loop Filter is connected to the decrement input DEC of the ID counter. If the carry signal is activated, a single pulse is added to the ID counter output signal ID out and conversely if the borrow signal is activated, a single pulse is subtracted from the ID counter output ID out. 
     The ID counter output ID out is connected to the input CP of the +N counter. The N control determines the factor of N that the input CP is divided by to form the frequency F o  of the output u 2  &#39;. 
     The variance of the phase and frequency of the output u 2  &#39; from the desired frequency is called jitter. As the phase detector compares the reference signal u 1  to the output signal u 2  &#39;, any difference in frequency will be a function of the weighted number of carry pulses from the K counter versus the number of borrow pulses. The size of the error maybe on the order of the pulse width of the two signals u 1  and u 2  &#39;. Also the time required to become totally locked to a new reference frequency u 1  will be a function of the frequency of the K clock and again maybe as long as the pulse width of the reference signal u 1  and the output signal u 2  &#39;. 
     U.S. Pat. No. 5,430,764 (Chren, Jr.) describes a frequency synthesizer using a residue number system to generate an address to find a value in a look-up table containing the digital values of a sine wave. These values are presented to a digital-to-analog converter to create an analog sine to wave output. 
     U.S. Pat. No. 5,467,294 (Hu, et al.) illustrates an apparatus for the programmable generation of sine waves. The digital values to describe the sine wave is maintained in a ROM lookup table. 
     SUMMARY OF THE INVENTION 
     An objective of this invention is the generation of a binary wave form of a frequency that is synchronized to a reference signal, wherein any change in the binary wave form is accomplished with little time. Another object of this invention is to have a binary wave form with minimal jitter. Still another object of this invention is the elimination of multiple reference clock frequencies. And further still another object of this invention is to have a structure for the generation of the binary wave form such that it can be implemented within a synthesizing automated logic design system. 
     To accomplish these and other objects, the present invention is a frequency synthesizing system that will generate a periodic output frequency. The periodic output frequency has a period that is composed of multiple periods of a periodic input reference frequency. 
     The frequency synthesizing system has a count compiler to generate a series of counting integers representing the number of periods of the periodic input reference frequency that compose the period of the periodic output frequency. The frequency synthesizing system also has a count series retention table to store a plurality of the series of counting integers; a count incrementing means to select the individual counting integers within the count series retention table; a frequency generation means that will count the number of periods in the period reference signal and when the count is equal to the integer of the from the count series retention table will force the periodic output frequency to change from one logic level to another. The count incrementing means will increment and the process will repeat continuously. If a different period for the periodic output frequency is required, then a count select signal will choose another series of counting integers and a different series of counting integers will be presented to the frequency generation means. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 2, a frequency generator 26 has an periodic input reference frequency (f i ) 24. The periodic out put frequency F o  is derived by creating each period of time that elapses between a transition of the output 28 from a logical 1 to a logical 0 or from a logical 0 to a logical 1. The period of time for the periodic output frequency F o  is determined by counting a number of pulses of the periodic input reference frequency (f i ) 24 and toggling the output 28 from one logic level to another, then counting the pulses of the periodic input reference frequency (f i ) 24 again and then toggling the output 28 again from the one logic level back to the original logic level. This process is repeated to form the periodic output frequency F o  at the output 28. 
     The number of pulses of the periodic input reference frequency (f i ) 24 to be counted is set by the count input 23 of the frequency generator 26. If the ratio (X n ) of the periodic output frequency F o  to the periodic input reference frequency (f i ) 24 is an integer, the count input 23 is set to the value of that integer. For example if: 
     
         F.sub.o =2.457 Mhz 
    
     
         f.sub.i =12.288 Mhz 
    
     
         count=f.sub.i /F.sub.o =X.sub.n =5. 
    
     Therefore, the count input 23 has the value of 5 and the frequency generator 26 will set the output 28 at the beginning of the sequence to a logic 1, then count 5 periods of the periodic input reference frequency (f i ) 24 then toggle the output 28 to a logic 0 and count 5 periods of the periodic input reference frequency (f i ) 24 and repeat this process continuously. 
     However, if the ratio X n  of the periodic input reference frequency (f i ) 24 to the periodic output frequency F o  is a mixed number of an integer and a fraction, it then must be decomposed into a series of numbers that is the weighted average of two integers, wherein the two integers are consecutive integers. The smaller of the two integers is the integer lesser than the mixed number and the larger number is the next larger integer. For example: 
     
         F.sub.o =2.560 Mhz 
    
     
         f.sub.i =12.288 Mhz 
    
     
         count=f.sub.i /F.sub.o =X.sub.n =44/5 
    
     
         r.sub.n =smallest number=4 
    
     
         s.sub.n =largest number=5 
    
     The numerator of the weighted average of the ratio X n  of the periodic input reference frequency (f i ) 24 to the periodic output frequency F o , will form a summation of a series S n  of the two integers r n  and s n . That is S n  =r n  +s n  +r n  +s n  +. . . +r n  +s n  the number of terms in the series S n  is the denominator q n  of the fraction of the mixed number and the number of the terms s n  in the series S n  is the residue of the division of the ratio X n  of the periodic input reference frequency (f i ) 24 to the periodic output frequency F o  divided by the denominator q n  of the fraction of the mixed number. 
     The above fraction is formed by simplifying of the mixed number by searching for the lowest common denominator of the fraction. From the example above: ##EQU1## From the above it can be seen that the q n  =5. Continuing the above example: 
     
         X.sub.n =44/5 
    
     
         q.sub.n =5 
    
     
         r.sub.n =4 
    
     
         s.sub.n =5 
    
     
         The number of s.sub.n terms=4 
    
     Therefore: ##EQU2## 
     
         S.sub.n =5,5,5,5,4. 
    
     The series S n  is stored in the count series retention table 14. The count series retention table may be implemented as a register based look-up table, a read-only memory, or other logic structure that can contain the series of counting integers. The output 22 of the count series retention table 14 is connected to the count input 23 of the frequency generator 26. 
     The count compiler 10 is a subfunction of an automated logic design system that will calculate the entries to be placed in the count series retention table 14. The count compiler 10 will have the value of the periodic input reference frequency (f i ) 24 and a listing of the desired periodic output frequencies F o  from which to compile each series of the counting integers as described above. The series of counting integers are placed in the count series retention table 14 through interface 12. Interface 12 may be a software compiling of the count series retention table 14 or a programming of the count series retention table 14 at the assembly of hardware for the frequency synthesizer. 
     The count select line 16 determines which series of the counting integers in the count series retention table 14 is to be sequentially presented to the frequency generator 26. 
     The periodic output frequency F o  of the frequency generator 26 will remain constant with the jitter of one periodic input reference frequency (f i ) 24 cycle, since the counting integers differ by a value of 1. This difference of 1 within the series of counting integers translates to the period of one cycle of the periodic input reference frequency (f i ) 24. 
     Referring to FIG. 3, the counts series table 14 has a plurality of look-up tables 6a, 6b, . . . , 6n that contain the plurality of series of counting integers. The output 8a, 8b, . . . , 8n of each look-up table 6a, 6b, . . . , 6n is connected to a multiplexer 5. The count select line 16 is decoded in the multiplexer 5 to place one of the outputs 8a, 8b, . . . , 8n at the output 22 of the multiplexer 5. 
     The output 20 of the count incrementer 18 is connected to the count look-up tables 6a, 6b, . . . , 6n, to increment the look-up tables 6a, 6b, . . . , 6n through the series of counting integers. 
     The count incrementer 18 has a decoder 4 and a counter 2. The decoder 4 determines the number of integers in the series of counting integers from the value of the count select input 16. The value of the number of integers in the series of counting integers is the input 13 to the counter 2. The count signal 20 that is the output of the counter 2 will increment at the end of the period of the periodic output frequency F o . The increment well reset to the beginning of the series of the counting integers when the counter 2 reaches the value of the output 13 of the decoder 4. 
     The frequency generator 26 has a counter 1 that will count the number of periods of the periodic input reference frequency (f i ) 24. The periodic input reference frequency (f i ) 24 is connected to the dock input clk of the counter 1 and the output 22 of the count series retention table 14 is connected to the maximum count input MAX of the counter 1. 
     The counter 1 will place a logical 1 on the output count when the number of periods of the periodic input reference frequency (f i ) 24 equal to the number at the input MAX. The counter 1 will reset and start counting again. The will continue iteratively. The output count is connected to the input clk of the clock generator 3 and the output 22 of the count series retention table 14 is connected to the input IN1 of the clock generator 3. The output OUT of the dock generator 3 is the periodic output frequency 28. The periodic output frequency 28 will toggle from one logic state to another logic state at the reception of the signal from the output count of the counter 1, a transition of the periodic input reference frequency (f i ) 24. The output 22 contains the &#34;divide by&#34; value for the clock generator 3 for the present counting period. This value changes as the series S n  is placed on the output 22 of the count retention table 14. 
     The counters 1 and 2 can be designed to switch at the positive edge, the negative edge, or beth the positive or the negative edges of the clock input clk. If both edges are used to trigger the counter 1, or 2, the periodic input reference frequency (f i ) 24 is effectively doubled. The only detriment of this doubling is that if the duty cycle, or the amount of time that the dock is at a logical 1 versus the amount of time it is a logical zero is not 50% or equal, the output jitter will be increased by the amount of the imbalance in this time. 
     The architecture of this invention is such that it can be easily synthesized using an automated logic design system or so called silicon compiler. The silicon compiler system allows the design of the frequency synthesizer system of this invention using a programming language like construct, or hardware description language, to describe the hardware function. 
     The silicon compiler will then compile this hardware description language into a technology specific hardware design. Table 1 is an example of a hardware description language for the counter 1 and 2 of FIG. 3 configured to respond to both the positive and negative edges of the transitions of the input reference frequency and is referred to as a dual edge counter. Table 2 is an example of the hardware description language for the clock generator 3. The hardware description language of these examples uses a construct that is similar t the constructs of the C programming language. This allows for definitions of the input and output buses, the relative timing of the switching signals for the input and outputs, and at which conditions of the inputs that the outputs will switch state. From these conditions the silicon compiler will select the circuits and configure the circuits for an implementation of the function. 
     
                       TABLE 1______________________________________//==============================================//Verilog HDL code for dual.sub.-- edge.sub.-- counter//==============================================module dual.sub.-- edge.sub.-- counter (max, clk, count):input clk;input  bussize:0!max;output  bussize:0!count; always @ (posedge clk or negedge clk) beginif (count + 1 == max) begin // wrap around countcount = 0;endelse begin    /increment countcount = count + 1;end endendmodule // dual.sub.-- edge.sub.-- counter______________________________________ 
    
     TABLE 
     
                       TABLE 2______________________________________//==============================================//Verilog HDL code for clock.sub.-- generator//==============================================module clock.sub.-- generator (clk, IN1, IN2, OUT);input clk;input  bussize:0!IN1;input  bussize:0!IN2;output  bussize:0!OUT; always @ (posedge clk or negedge clk) beginif (IN1 = 1 == IN2) begin // toggle output pinif (OUT == 0) beginOUT = 1endelse beginOUT = 0endend endendmodule // dual.sub.-- edge.sub.-- counter______________________________________ 
    
     While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.