Abstract:
An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is filed as a continuation-in-part of U.S. patent application Ser. No. 11/380,477 entitled “Three-Dimensional Packaging Scheme for Package Types Utilizing a Sacrificial Metal Base” filed Apr. 27, 2006. 
     
     TECHNICAL FIELD 
       [0002]    The invention relates to a three-dimensional stackable semiconductor package, and more particularly, to a three-dimensional stackable semiconductor package for package types having a sacrificial metal base 
       BACKGROUND ART 
       [0003]    As semiconductor integrated circuit chips become more multi-functional and highly integrated, the chips include more bonding pads (or terminal pads), and thus packages for the chips have more external terminals (or leads). When a conventional plastic package that has its leads along the perimeter of the package must accommodate a large number of leads, the footprint of the package increases. However, a goal in many electronic systems is to minimize an overall size of the systems. Thus, to accommodate a large number of pins without increasing the footprint of package, pin pitch (or lead pitch) of the package must decrease. However, a pin pitch of less than about 0.4 mm gives rise to many technical concerns. For example, trimming of a package having a pin pitch less than 0.4 mm requires expensive trimming tools, and the leads are prone to bending during handling of the package. In addition, surface-mounting of such packages demands a costly and complicated surface-mounting process due to a required critical alignment step. 
         [0004]    Thus, to avoid technical problems associated with conventional fine-pitch packages, packages that have area array external terminals have been suggested. Among these packages are ball grid array packages and chip scale packages. The semiconductor industry presently uses a number of chip scale packages. A micro ball grid array package (μBGA) and a bump chip carrier (BCC) are examples of the chip scale packages. The μBGA package includes a polyimide tape on which a conductive pattern is formed and employs a totally different manufacturing process from a conventional plastic packaging. The bump chip carrier package includes a substrate having grooves formed around a central portion of a top surface of a copper alloy plate and an electroplating layer formed in the grooves. Accordingly, chip scale packages use specialized packaging materials and processes that increase package manufacturing costs. 
         [0005]      FIGS. 1A through 1C  illustrate plan and cross-sectional views of a conventional apparatus for manufacturing leadless BCC packages. With reference to the plan view of  FIG. 1A , a conventional metal carrier matrix array  101  has an upper surface  103 , which includes an encapsulating matrix  105  with a plurality of sawing lines  107 . 
         [0006]    The cross-sectional view of  FIG. 1B  includes a plurality of bump pads  109  and a plurality of die pads  111  formed on the upper surface  103  ( FIG. 1A ) of the metal carrier  101  by plating. Back surfaces of integrated circuit dice  113  are attached to corresponding die pads  111 , and a plurality of bonding wires  115  connect a plurality of bonding pads  117  on active surfaces of the dice  113  to corresponding bump pads  109 . An encapsulant  119  encapsulates the encapsulating matrix  105  including the dice  113  and the bonding wires  115 . 
         [0007]    With reference to the underside plan view of  FIG. 1C , after etching away the metal carrier  101  (not shown in  FIG. 1C ), the bump pads  109  and the die pads  111  are exposed from the bottom surface  121  of the encapsulant  119 . Then, the encapsulant  119  is singulated by sawing along the sawing lines  107  to form a plurality of individual BCC packages. 
         [0008]    Therefore, a integrated circuit package that uses conventional packaging materials and processes can only be accessed for electrical interconnection, for example, to a printed circuit board, by the bump pads on the bottom surface  121  of the package. Consequently, what is needed to provide for a higher density of integrated circuit packaging into a given printed circuit board footprint is a means of allowing the integrated circuit packages to be stacked, one atop another. 
       SUMMARY 
       [0009]    In an exemplary embodiment, the present invention is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant. 
         [0010]    In another exemplary embodiment, the present invention is a method of packaging a semiconductor device. The method includes forming a plurality of electrical contact pads over a sacrificial base strip, mounting an electrical component to select ones of the plurality of electrical contact pads, forming an encapsulant over the electrical component, forming a plurality of holes from an uppermost portion of the encapsulant to at least an uppermost portion of one or more of the plurality of electrical contact pads, and at least partially filling the plurality of holes with an electrically conductive material. The holes are at least partially-filled such that the at least partially-filled plurality of holes is electrically conductive from a first end in electrical contact with the one or more of the plurality of electrical contact pads to a second end which is substantially coplanar with an uppermost surface of the encapsulant. 
         [0011]    In another exemplary embodiment, the present invention is a method of producing a three-dimensional package for mounting a plurality of electronic devices. The method includes forming a plurality of electrical contact pads over a sacrificial base strip, mounting the plurality of electronic devices to select ones of the plurality of electrical contact pads, attaching a plurality of bond wires from select ones of the plurality of electronic devices to select ones of the plurality of electrical contact pads, forming an encapsulant over the plurality of electronic devices, forming a plurality of holes from an uppermost portion of the encapsulant to at least an uppermost portion of one or more of the plurality of electrical contact pads, and at least partially filling the plurality of holes with an electrically conductive material. The holes are at least partially-filled such that the at least partially-filled plurality of holes is electrically conductive from a first end in electrical contact with the one or more of the plurality of electrical contact pads to a second end which is substantially coplanar with an uppermost surface of the encapsulant. The sacrificial base strip is removed after the encapsulant is formed over the plurality of electronic devices. 
     
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIGS. 1A-1C  show a bumped chip carrier (BCC) of the prior art. 
           [0013]      FIGS. 2A-2D  show cross-sectional views of exemplary fabrication steps of the present invention at a post-encapsulation phase. 
           [0014]      FIGS. 3A-3B  show an exemplary application of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0015]    Various common package types which utilize a sacrificial metal base strip connection do not have electrical connection pads on an uppermost surface of the completed package. Package types in this category include thin array plastic package (TAPP), ultra-thin land grid array (ULGA), and bumped chip carrier (BCC) packages. However, an application of the present invention to each of these and other packages allows packages to be arranged in three-dimensional stacks. Three-dimensional stacks allow a much smaller footprint of electronic devices when compared with a similar density of non-stacked devices. Further, individual packages may be individually tested prior to stacked packages being electrically connected thus improving final package test yield when compared with prior art non-stacked techniques. Additionally, rework of a stacked package module is possible simply by replacing components within the stack. Under the prior art, if one component in a package fails the entire package must be replaced. Utilizing the present invention, only one package within the stack is replaced. 
         [0016]    TAPP, ULGA, BCC, and similar families of packages are manufactured in multi-strip formats throughout an assembly process and then singulated into individual packages as a final step. Illustrations used herein focus on a single unit merely for clarity. However, a skilled artisan will recognize application of the present invention to a multi-strip application as well. 
         [0017]    With reference to  FIG. 2A , a sacrificial metal-type package is shown after components are mounted and encapsulated. Specifically, the exemplary package of  FIG. 2  includes a sacrificial base strip  201 , a plurality of attach/bond pads  203 , a plurality of discrete devices  205 , an integrated circuit device  207 , a plurality of bond wires  209 , and an encapsulant (i.e., mold compound)  211 . Any number and combination of integrated circuit dice and/or discrete components may be mixed in the package. In addition to using bond wires  209 , the dice may be, for example, flip-chip bonded and either mounted as a single die or in a stacked-die configuration. The sacrificial base strip  201  may be comprised of copper, copper alloys, or other types of materials such as nickel or iron and its alloys. In an alternative embodiment, the sacrificial base strip  201  may be formed from a non-conducting material. 
         [0018]    The plurality of attach/bond pads  203  may be plated-up metal layers. One desirable key property of the attach/bond pads  203  is to support a solder attach assembly for the package external connection pads and to support wire-bonding and/or flip-chip solder bonding and discrete component solder attach. There are situations where other electrical attachment techniques may not require solder attachment and thus the ability to solder to the attach/bond pads  203  is not an issue. For example, certain types of electrically-conductive epoxies will not required solder attachments. In any case, an ability to carry electrical current may be another parameter in determining a composition of the plated-up metal layers. Such determinations are known to one of skill in the art. However, typical metal layer compositions of the plated-up layer include, for example, gold-nickel-copper-nickel-gold (Au—Ni—Cu—Ni—Au) and gold-palladium-nickel-palladium (Au—Pd—Ni—Pd). 
         [0019]    In  FIG. 2B , holes (e.g., tunnels or vias)  213  are formed in the encapsulant  211  at one or more points where electrical connections need to be brought from a lowermost portion of the package to an uppermost portion of the package. The holes  213  may be produced by, for example, laser drilling or mechanical drilling through the encapsulant  211 . Other techniques may also be used to form the holes  213 . Alternative forms of producing the holes  213  include incorporating pins into the encapsulant  211  prior to curing the mold compound or an anisotropic chemical etch (depending upon chemical characteristics of a material chosen for the encapsulant  211 ). The holes  213  thus expose the electrically conductive surfaces of one or more of the attach/bond pads  203 . The holes  213  may either be formed to an uppermost surface of the attach/bond pads  203  or, alternatively, may be drilled past the attach/bond pads and into the sacrificial base strip  201 . 
         [0020]    In  FIG. 2C , the holes  213  ( FIG. 2B ) are at least partially-filled (e.g., filled sufficiently to provide a complete electrical path from the lowermost surface, i.e., the contact pads, to the uppermost surface that is substantially coplanar with the top surface of the encapsulant) with an electrically conductive material. A partial filling is electrically conductive from the lowermost surface to the uppermost surface and may be physically discontinuous in all areas (e.g., a cylindrical shape). The electrically conductive material thus forms a three-dimensional plug  215 . The three-dimensional plug  215  may be formed by, for example, an electrolytic copper plating. Metals or alloys other than copper may be used as well. Such metals include copper alloys, nickel, tin, tin alloys, tungsten, titanium-tungsten, and so on. Further, forming methods other than electrolytic plating may be used including physical or chemical vapor deposition (PVD or CVD). 
         [0021]    In  FIG. 2D , the sacrificial base strip  201  is removed, for example, by chemical etching. Using a high-selectivity etchant, the etchant will not etch any of the plated-up metal layers that form the plurality of attach/bond pads  203  or the electrically conductive plug  215 . In an alternative embodiment, if the sacrificial base strip  201  is formed from a non-conductive material, the sacrificial base strip  201  may be left in place. The multi-strip format (no shown) is singulated (typically by mechanical sawing or laser-scribing), forming individual packages having electrical connection pads on both an uppermost and a lowermost surface. The packages may be stacked and electrically connected, one atop another. 
         [0022]    With reference to  FIG. 3A , an exemplary application of the present invention is shown in use with other electronic devices. Three major components are a multi-component package  300  in accordance with the present invention, a four-layer thin core substrate  330 , and a system-in-package (SIP) module  350 . 
         [0023]    In this exemplary application, the multi-component module  300  includes a plurality of attach/bond pads  303 , a plurality of discrete electronic devices  305 , an integrated circuit  307 , a plurality of bond wires  309 , and encapsulant  311 , and a plurality of three-dimensional plugs  315 . The four-layer thin core substrate  330  is known in the art and includes a core  331 , a plurality of feed-through connectors  333 , and a plurality of contact pads  335 . The core is typically an epoxy laminate (e.g., FR-4) or ceramic. The SIP module  350  includes an externally-mounted crystal  351 , a plurality of attach/bond pads  353 , one or more internally-mounted discrete electronic devices  355 , an integrated circuit device  357 , a plurality of bond wires  359 , and an encapsulant  361 . The encapsulated package within the SIP module  350  may be virtually an type of electronic package including a BGA, quad flat-pack no-lead (QFN), quad flat package (QFP), and so on. 
         [0024]      FIG. 3B  shows a final three-dimensional package  390  made possible through the use of the multi-component module  300  of the present invention. A skilled artisan will recognize that a plurality of multi-component modules  300  ( FIG. 3A ), in this and other configurations, may be stacked in numerous ways. All dimensions shown in  FIGS. 3A and 3B  are merely exemplary and are based on thicknesses of may standard components. 
         [0025]    In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that embodiments of the present invention may be readily applied to modified versions of TAPP (thin array plastic package), ULGA (ultra-thin land grid array), BCC (bumped chip carrier), or other package types. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.