Abstract:
In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Description:
FIELD OF THE INVENTION 
     This invention relates to semiconductor devices that include a gate electrode formed in a trench, and in particular to trench-gated metal-oxide-silicon field-effect transistors (MOSFETs) and diodes. 
     BACKGROUND OF THE INVENTION  
     Power MOSFETs are the preferred switching devices for notebook computers and other portable electronic devices, and they are also widely used for switching currents in the automotive industry. In a common form of MOSFET, the gate electrode is formed in a trench that extends downward from the surface of the chip, and current flows primarily in a vertical direction between a source region on one surface of the chip and a drain region on the other surface of the chip. The source region is normally shown on the top surface of the chip and the drain region is shown on the bottom surface of the chip, although this orientation is arbitrary. The trench is lined with a dielectric layer (typically silicon dioxide), and a channel is formed in a body region adjacent a wall of the trench. When the gate is properly biased (positive in an enhancement-mode N-channel device, negative in an enhancement-mode P-channel device) the channel becomes inverted and allows current to flow between the source and the drain. In depletion-mode devices the MOSFET is normally turned on and is turned off by a proper gate bias (negative in a depletion-mode N-channel device, positive in a depletion-mode P-channel device). 
     Two of the principal performance criteria of a power MOSFET are its on-resistance resistance (R dson ) and its avalanche breakdown voltage V B . R dson  is a measure of the resistance through the MOSFET when it is turned on and V B  is a measure of its ability to block a reverse voltage. Another important performance criterion is the capacitance between the gate and drain (C gd ), which determines the MOSFET&#39;s ability to switch current quickly and operate at high frequencies. In normal trench-gated MOSFETs the gate-to-drain capacitance is measured across the gate oxide layer at the bottom of the trench, which separates the gate electrode from the drain. 
     It is known to increase the breakdown voltage V B  by including a “drift region” between the body and the drain of the device. The drift region is a relatively lightly-doped region of the same conductivity type as the drain. While the inclusion of a drift region in the device tends to improve V B , it also tends to increase R dson , since the drift region represents a relatively lightly-doped region that the current must traverse when the MOSFET is turned on. 
     Various techniques have been proposed for reducing C gd . One proposal, suggested in U.S. Pat. No. 4,914,058 to Blanchard, is to increase the thickness of the gate oxide layer at the bottom of the trench. This technique is illustrated by MOSFET  10 , shown in the cross-sectional view of  FIG. 1 . MOSFET  10  is formed in an epitaxial (epi) layer  102  that is grown on an N+ substrate  100 . A trench  104  extends through epi layer  102  and into N+ substrate  100 . Since MOSFET  10  is an N-channel device, epi layer  102  is generally doped with an N-type impurity such as phosphorus. Epi layer  102  also includes an N+ source region  106  and a P body  108 , both of which are contacted by a metal layer  115 . The background N-type doping of epi layer  102  is found in an N-drift region  110 . N+ substrate  100  and N-drift region  110  represent the drain of MOSFET  10 . 
     The sidewalls of trench  104  are lined with a gate oxide layer  112 , and trench  104  is filled with a gate electrode  114 , which is typically made of polycrystalline silicon (polysilicon) that is doped heavily to make it conductive. At the bottom of trench  104  is a thick oxide layer  116  that serves to reduce the capacitance between the polysilicon gate  114  and the drain (N+ substrate  100  and N-drift region  110 ). The R dson MOSFET  10  can be reduced somewhat by providing a graded doping concentration in N-drift region  100 , decreasing gradually in the direction from N+ substrate  100  to P body  108 , but nonetheless R dson  is still not below the silicon limit which is the minimum R dson  for a given breakdown voltage BV. The silicon limit is defined by the equation,
 
 R   dson =5.93×10 −9   *BV   2.5 .
 
     A two-step etching process was described for fabricating this device. First, a gate trench mask was used to form trenches of a desired width and depth. A thin gate oxide was grown on the walls and floor of trench  104 , and a nitride layer was deposited over the gate oxide layer. A directional etching process (e.g., reactive ion etching (RIE)) was used to remove the nitride and gate oxide from the floor of the trench, and a second trench was etched through the floor of the trench reaching to the N+ substrate  100 . Thick oxide layer  116  was formed in the second trench. The other process steps were similar to those customarily employed in trench MOSFET fabrication. 
     U.S. Pat. No. 5,637,898 to Baliga describes a process that uses a single-trench etch and an oxidation that creates a thick bottom oxide. Polysilicon is subsequently deposited and etched, leaving a recessed polysilicon layer at the bottom of the trench. The sidewall oxide is then etched away, and a new gate oxide layer is grown, followed by a selective RIE process to remove the oxide layer formed on top of the recessed polysilicon layer. Polysilicon is then deposited to form the desired thin-thick gate oxide layer realized by Blanchard in the two-step etch process described above. Baliga also uses a graded doping profile in the drift region to reduce the on-resistance. 
     U.S. Pat. No. 5,998,833 to Baliga teaches another type of trench MOSFET. The trench contains an upper gate electrode, which is generally aligned with the source and base regions, and a lower source electrode, which is generally aligned with the drift region. Again, the drift region is linearly graded and decreases in a direction from the drain region to the surface of the silicon. However, the bottom of the upper gate electrode is aligned with the junction between the P-base region and the N-drift region. This requires that both the polysilicon layer that is deposited to form the lower source electrode be etched and the oxide layer separating the upper and lower electrodes be formed to a high degree of accuracy. If, for example, the lower source is not etched deeply enough, or if the oxide layer separating the upper and lower electrodes is grown too thick, the bottom of the gate electrode will be located above the junction between the base and drift regions. As a result, the upper gate electrode will not invert the entire channel and the device will not turn on. U.S. Pat. No. 6,388,286 to Baliga describes a trench structure that has similar problems. 
     Recently, an article by X. Yang et al. (“Tunable Oxide-Bypassed Trench Gate MOSFET: Breaking the Ideal Superjunction MOSFET Performance Line at Equal Column Width,” IEEE Electron Device Letters, Vol. 24, No. 11, pp. 704–706, 2003) described a trench oxide bypass structure that had very low R dson . Drawing on a concept previously proposed by Y. C. Liang et al. (“Tunable oxide-bypassed VDMOS (OBVDMOS): Breaking the silicon limit for the second generation,” Proc. IEEE/ISPSD, pp. 201–204, 2002), this article reported the successful fabrication of a TOB-UMOS device having a 79 V rating. The device reportedly broke the ideal superjunction MOSFET performance line at an equal column width of 3.5 μm and potentially the ideal silicon limit as well. 
     Nonetheless, there is a clear need for a new type of MOSFET whose on-resistance is lower than what can be achieved following conventional MOSFET structures. 
     SUMMARY OF THE INVENTION 
     In a trench MOSFET according to this invention, the trench has an upper portion, which includes a gate electrode, and a lower portion, which includes a buried source electrode. The gate electrode is isolated from the body region by a gate dielectric layer, which is typically an oxide layer. The buried source electrode is isolated from the drift region by a second dielectric layer and from the gate electrode by a third dielectric layer, both of which are typically oxide layers. There is a vertical overlap between the buried source electrode and the gate electrode which provides a margin of error in the diffusion of the body region. 
     The buried source electrode is electrically connected to the source region. As a result, when the MOSFET is reverse-biased, the source electrode depletes the drift region in a direction transverse to the general direction of current flow. There is normally a similar trench on the opposite side of the drift region, so the drift region is depleted from both sides. This allows the doping concentration of the drift region to be significantly higher than it would otherwise need to be to block a reverse current flow between the drain and the source. Therefore, the resistivity of the drift region is far less when the device is turned on. 
     In addition, the buried source electrode separates the gate from the drain and thereby reduces the gate-to-drain capacitance, allowing the MOSFET to operate at high frequencies. 
     This structure is different from the structure proposed by X. Yang et al., supra, in that it does not suffer from the limitation relating to the width of the mesa. In the structure we propose, the unit cell is the sum of the trench MOSFET and the thick oxide buried source element. Our structure uses the silicon more effectively because we construct the trench MOSFET over the buried source. 
     According to another aspect of the invention, a MOSFET is fabricated by a process which includes: forming a trench at a first surface of a semiconductor substrate, the substrate including dopant of a first conductivity type; depositing a mask layer over the first surface, the mask layer lining the walls and floor of the trench; removing a portion of the mask layer adjacent the floor of the trench, remaining portions of the mask layer remaining attached to sidewalls of the trench; etching the substrate through the bottom of the trench with the remaining portions of the mask layer remaining attached to sidewalls of the trench so as to form a cavity in the substrate; heating the substrate with the remaining portions of the mask layer remaining attached to sidewalls of the trench so as to form a first dielectric layer in the cavity; removing the remaining portions of the mask layer; introducing conductive material into the cavity, the conductive material being separated from said substrate by the first dielectric layer; heating the substrate so as form a second dielectric layer at an exposed surface of the conductive material and a gate dielectric layer along walls of the trench; introducing conductive material into the trench; forming a body region of a second conductivity type opposite to the first conductivity type in the substrate, the body region abutting the gate dielectric layer; forming a source region of the first conductivity type abutting the gate oxide layer and forming a junction with the body region; covering the conductive material in the trench with a third dielectric layer; and depositing a metal layer over the substrate, the metal layer being in electrical contact with the source region. 
     Preferably, the device is laid out in a pattern of annular mesas and trenches. Contact to the gate electrodes can be made by an array of gate metal legs that extend outward from a central region of the die. The die can be made “self-terminating” by making a peripheral trench deeper than the remaining trenches and contacting the peripheral trench with the source metal layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a cross-sectional view of a MOSFET that illustrates a known technique for reducing the gate-to-drain capacitance. 
         FIG. 2  is a cross-sectional view of a MOSFET according to the invention. 
         FIG. 3  is a schematic view of the MOSFET of  FIG. 2  showing the expansion of the depletion regions that occurs when the device is turned off. 
         FIGS. 4A–4L  illustrate steps of a process that can be used to fabricate the MOSFET shown in  FIG. 2 . 
         FIGS. 5A–5G  illustrate steps of a process for making a connection between the buried source electrode and the source region in the MOSFET shown in  FIG. 2 . 
         FIG. 6  is a cross-sectional view of an alternative MOSFET according to the invention. 
         FIGS. 7A–7H  illustrate steps of a process that can be used to fabricate the MOSFET shown in  FIG. 6 . 
         FIG. 8  is a graph generated by computer simulation showing the variation of the specific on-resistance and breakdown voltage of a MOSFET according to this invention as a function of the width of the mesa. 
         FIGS. 9A–9E  illustrate the formation of source metal and gate metal layers over an annular arrangement of trenches in accordance with the invention. 
         FIG. 10  shows a cross-section taken at section line  10 — 10  shown in  FIG. 9C . 
         FIGS. 11A–11C  illustrate alternative annular arrangements of trenches in accordance with the invention. 
         FIG. 12  is a graph generated by computer simulation showing the variation of breakdown voltage of a device as a function of the radius of curvature of the trench corners in an annular layout. 
         FIGS. 13A and 13B  illustrate an annular arrangement of trenches similar to that shown in  FIGS. 9A–9E  but with a deeper peripheral trench which serves to “self-terminate” the device. 
         FIG. 14  is a cross-sectional view of another embodiment of a MOSFET in accordance with the invention. 
         FIG. 15  is a top view of a layout which includes the MOSFET of  FIG. 14 . 
         FIGS. 16A–16D  illustrate a process for fabricating the MOSFET of  FIG. 14 . 
     
    
    
     DESCRIPTION OF THE INVENTION 
       FIG. 2  illustrates a cross-sectional view of an N-channel MOSFET  20  in accordance with this invention. MOSFET  20  is formed in an epitaxial (epi) layer  202  that is grown on an N+ substrate  200 . Trenches  204 A and  204 B and are formed in epi layer  202 . Trenches  204 A and  204 B are separated by a mesa  206 . While  FIG. 2  shows only two trenches, it will be understood by those of skill in the art that the trenches and mesas shown in  FIG. 2  typically represent only a tiny fraction of the total number of trenches and mesas in the actual device, which may number in the millions. The trenches and mesas may be arranged in a variety of geometric patterns on the surface of epi layer  202 . In some of the most common of these patterns, the mesas are hexagons, squares or longitudinal stripes and are separated by trenches of uniform width and depth. As trenches  204 A and  204 B are identical, only trench  204 A will be described in detail. It will be understood that the structure of trench  204 B is identical to the structure of trench  204 A, with the similarly numbered components being identical. 
     The upper portion of trench  204 A includes a polysilicon gate  208 A that is separated from mesa  206  by a gate oxide layer  210 A, which lines the sidewalls of the upper portion of trench  204 A. The lower portion of trench  204 A includes a buried source electrode  212 A, which is electrically isolated from N-drift region  214  by a thick oxide layer  216 A and from gate  208 A by a thin oxide layer  218 A. As described below, buried source electrode  212 A is electrically connected to N+ source region  222  and P-body region  220  in the third dimension, outside the plane of  FIG. 2 . In this embodiment, buried source electrode  212 A is formed of doped polysilicon. Thick oxide layer  216 A lines the sidewalls and bottom of the lower portion of trench  204 A. 
     The upper portion of mesa  206  includes a P-body region  220  and an N+ source region  222 . The lower junction of P-body region  220  abuts N-drift region  214 . The drain of MOSFET  20  includes N+ substrate  200  and N-drift region  214 . 
     Overlying epi layer  202  is a source metal layer  224 , which contacts N+ source region  222  and P-body region  220 . A P+ region  228  provides an ohmic contact between metal layer  224  and P-body region  220 . Gate  208 A is insulated from source metal layer  224  by a borophosphosilicate glass (BPSG) layer  226 . 
     Gate oxide layer  210 A has a thickness that is selected to provide the desired threshold voltage V th  for MOSFET  20 . Thick oxide layer  216 A has a thickness that can withstand the maximum drain-to-source breakdown voltage without rupture or damage. 
     Since the buried source electrodes  212 A,  212 B are tied to the N+ source region  222 , the full source-to-drain voltage is seen across thick oxide layer  216 A when MOSFET  20  is turned off. The doping concentration of N-drift region  214  is selected such that N-drift region  214  is fully depleted when the maximum drain-to-source voltage is reached. This is illustrated in  FIG. 3 , a detailed view of N-drift region  214 , wherein the N+ substrate (drain) is shown schematically as biased to a positive voltage V 1  and the N+ source region  222  and buried source electrodes  212 A and  212 A are shown schematically as grounded. As indicated, depletion regions  230 A and  230 B spread laterally inward from the thick oxide layers  216 A,  216 B on both sides of N-drift region  214  until the depletion regions  230 A,  230 B meet at the center of N-drift region  214 . 
     This formation of depletion regions  230 A,  230 B allows the doping concentration of N-drift region  214  to be higher than it would otherwise be, thereby reducing the R dson  of MOSFET  20 . 
     Computer simulation, using such widely available programs as MEDICI and SUPREM-4, shows that by the properly choice of the mesa width and doping the R dson  can be made lower than the value can be attained in conventional silicon trench MOSFET.  FIG. 8  is a computer-generated graph which shows the variation of the specific on-resistance and breakdown voltage as a function of mesa width for a device having a doping concentration on the order of 3×10 16  cm −3 . The mesa width varied from zero up to 3 μm. At a mesa width of approximately 1.5 μm the specific on-resistance (R dson ) reaches a minimum value of less than 36 mohm-mm 2  and the breakdown voltage BV reaches a maximum of approximately 95 V. This may be compared with the ideal silicon limit of 65 mohm-mm 2  referenced in the above X. Yang et al. article. 
     This structure will yield R dson  values below that which can be achieved with conventional trench structures. This is the reason why we have coined the title super Trench MOSFET. Those of skill in the art will understand that better results can be obtained by optimizing the device parameters. Also, the structure is not limited to any particular voltage range. 
     Table 1 below provides several parameters that may be used to achieve breakdown voltages in the range of 60 to 250 V. The parameters can be varied somewhat (e.g., ±20%) and still achieve satisfactory results: 
     
       
         
               
               
             
               
               
               
               
               
               
               
             
               
               
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
             
             
               
                   
                   
               
               
                   
                 BV 
               
             
          
           
               
                   
                 60 
                 90 
                 100 
                 150 
                 200 
                 250 
               
               
                   
                   
               
             
          
           
               
                 Oxide Thickness (μm) 
                 0.3 
                 0.55 
                 0.6 
                 1.0 
                 1.6 
                 2.2 
               
               
                 Trench Width (μm) 
                 0.8 
                 1.3 
                 1.4 
                 2.2 
                 3.4 
                 4.6 
               
               
                 Drift Doping Conc. (cm −3 ) 
                 5.1e16 
                 2.7e16 
                 2.0e16 
                 1.1e16 
                 7.5e16 
                 4.5e15 
               
               
                 Mesa Width (μm) 
                 1.0 
                 1.4 
                 2.0 
                 2.9 
                 3.1 
                 4.4 
               
               
                 R dson  (mohm-mm 2 ) 
                 12.9 
                 33.8 
                 42.9 
                 82.1 
                 154.3 
                 283.3 
               
               
                 R dson  Silicon Limit (mohm-mm 2 ) 
                 13.0 
                 44.8 
                 58.7 
                 174 
                 373 
                 629s 
               
               
                   
               
             
          
         
       
     
     It is important to note that buried source electrode  212 A also shields gates  208 A,  208 B from the drain (N+substrate  200  and N-drift region  214 ) thereby reducing the gate-to-drain capacitance to near zero. The thickness of oxide layers  218 A and  218 B is selected in light of the desired gate-to-source capacitance between gate  208 A and buried source electrode  212 A. The gate-to-source capacitance is equal to Wp*W*εox/tox, where Wp is the perimeter of the gate  208 A and W is the width of the gate  208 A. Increasing oxide thickness will reduce gate-to-source capacitance. 
       FIGS. 4A–4L  illustrate several steps of a process that may be used to fabricate MOSFET  20 . As shown in  FIG. 4A , the process begins by growing N-epitaxial (epi) layer  202  on substrate  200 . Substrate  200  is heavily doped with N-type impurity to a resistivity in the range of 1 to 3 mohm-cm, and epi layer  202  is doped with an N-type impurity such as phosphorus to a doping concentration in the range of 2.5×10 16  cm 31 &#39; to 3.5×10 16  cm −3 , preferably about 3×10 16  cm −3  for a device with 80 V breakdown voltage. 
     Next, as shown in  FIG. 4B , a pad oxide layer  240  is thermally grown in the top surface of N-epi layer  202 . Oxide layer  240  can have a thickness of 5000 Å, for example for a 80V breakdown device, so that the maximum field supported by the thick oxide is below that of the oxide breakdown field. 
     As shown in  FIG. 4C , a photoresist mask layer  242  is formed over oxide layer  240 , and mask layer  242  is photolithographically patterned with openings where the trenches are to be located. 
     As shown in  FIG. 4D , oxide layer  240  is then etched through the openings in mask layer  242  to form openings which expose the top surface of epi layer  202 . Mask layer  242  may then be removed. 
     As shown in  FIG. 4E , trenches  204 A and  204 B are formed by directionally etching epi layer  202  through the openings in oxide layer  240 , preferably using a reactive ion etch (RIE) process. In the embodiment shown, trenches  204 A and  204 B extend into epi layer  202  but not all the way to N+ substrate  200 . Pad oxide layer  240  is then-removed using a buffered oxide wet etch. 
     As shown in  FIG. 4F , a second, thick silicon oxide layer  246  is thermally grown over the top surface of N-epi layer  202 , for example, by heating epi layer  202  to 1100° C. for 40 minutes. For example, oxide layer  246  could be 5000 Åthick. As shown, oxide layer  246  conforms to the contours of the trenches  204 A and  204 B. 
     As shown in  FIG. 4G , a conductive polysilicon layer  248  is deposited over the top surface of the structure, filling trenches  204 A and  204 B and overflowing the entire surface of oxide layer  246 . Polysilicon layer  248  can be doped with an N-type impurity such as phosphorus to a concentration of  — 10 21  cm −3 . 
     As shown in  FIG. 4H , polysilicon layer  248  is etched back until the surface of polysilicon layer  248  is located within trenches  204 A and  204 B, thereby forming buried source electrodes  212 A and  212 B in trenches  204 A and  204 B, respectively, which are electrically isolated from epi layer  202  by oxide layer  246 . This is done using a process that does not significantly attack oxide layer  246 . The polysilicon etches faster than silicondioxide, and the silcon dioxide layer  246  is made thick enough that there is a remaining layer of oxide left at the surface when the polysilcon layer  212 A and  212 B are etched inside the trenches. For reasons that are described below, to provide a contact with the buried silicon electrodes  212 A and  212 B, this etching process is preferably performed in two stages, with the surface of polysilicon layer  248  being approximately level with the surface of epi layer  202  following the first stage of etching. Polysilicon layer  248  is then etched again (except at the locations where the buried source electrodes are to be contacted) until the surface of polysilicon layer  248  reaches a final location. The final location of the surface of buried source electrodes is a matter of design, but in one embodiment it is located at a position corresponding to about one-sixth of the depth of trenches  204 A and  204 B. 
     As shown in  FIG. 4I , oxide layer  246  is etched until it is entirely removed form the top surface of epi layer  202  and the sidewalls of trenches  204 A and  204 B above polysilicon layer  248 , leaving thick oxide layers  216 A and  216 B in the lower portions of trenches  204 A and  204 B, respectively. Preferably, when the etch of oxide layer  246  has been completed, the surface of oxide layers  216 A and  216 B is located slightly (e.g., 2000 Å) below the top surfaces of buried source electrodes  212 A and  212 B. As described below, this provides a vertical overlap between buried source electrodes  212 A and  212 B and polysilicon gates  208 A and  208 B. Next, a sacrificial oxide layer (not shown) can be grown on and removed from the sidewalls of trenches  204 A and  204 B to repair any crystal damage resulting from the earlier RIE process. Thereafter, as shown in  FIG. 4J , the structure is annealed to form an oxide layer on the exposed silicon and polysilicon surfaces. This produces gate oxide layers  210 A and  210 B on the sidewalls of the upper portions of trenches  204 A and  204 B and oxide layers  218 A and  218 B on the top surfaces of buried source electrodes  212 A and  212 B. In addition, an oxide layer  254  is formed on the top surface of epi layer  202 . 
     Even if the etchant used on oxide layer  246  ( FIG. 4I ) is highly selective, it may nonetheless deform buried source electrodes  212 A and  212 B slightly, so as to form depressions in the top surfaces thereof, as shown by the dashed lines in  FIG. 4I . These depressions may make it difficult to grow oxide layers  218 A,  218 B uniformly on the top surfaces of buried source electrodes  212 A,  212 B. This problem can be avoided by annealing the structure shown in  FIG. 4I  in a hydrogen atmosphere, e.g., for about 10 seconds at 1050° C. The anneal returns the top surfaces of buried source electrodes  212 A,  212 B to the rounded shape shown by the solid lines in  FIG. 4I . 
     As shown in  FIG. 4K , a second polysilicon layer  250  is deposited over the structure, filling the upper portions of trenches  204 A and  204 B and overflowing the top surface of epi layer  202 . Polysilicon layer  250  can be doped with an N-type impurity such as phosphorus to a concentration of 10 20  cm −3 . 
     As shown in  FIG. 4L , polysilicon layer  250  is etched back until its top surface is approximately level with the top surface of epi layer  202 , thereby forming polysilicon gates  208 A and  208 B. As described above, the top surfaces of oxide layers  216 A and  216 B are recessed with respect to the top surface of buried source electrodes  212 A and  212 B, providing a vertical overlap between buried source electrodes  212 A and  212 B and gates  208 A and  208 B. 
     Thereafter, a P-type dopant such as boron with energy the order of 200 Kev and dose of 3×10 13  cm −2  is implanted into epi layer  202  and driven in until it forms a junction with the remaining N-type region of epi layer  202  adjacent gate oxide layers  210 A and  210 B, thereby forming P-body region  220 , shown in  FIG. 2 . The vertical overlap between buried source electrodes  212 A and  212 B and gates  208 A and  208 B provides a margin of error in this process, since the junction between P-body region  220  and N-drift region  214  must not be located adjacent thick oxide layers  216 A and  216 B. Otherwise, a portion of the channel will not be inverted when gates  208 A and  208 B are biased to turn the device on, and the device will not conduct current. 
     The top surface is appropriately masked, and an N-type dopant such as phosphorus is implanted to form N+ source regions  222 . After another mask, a P-type implant with energy on the order of 80 Kev and dose of 8×10 15  cm −2  is implanted to form P+ region  228 . After oxide layer  254  has been removed by dry plasma etching, a layer of BPSG is deposited over the top surfaces of gates  208 A and  208 B and epi layer  202 . A photoresist mask layer (not shown) is deposited and patterned over the BPSG layer, with an opening generally over mesa  206 . The BPSG layer is etched through the opening to form BPSG layers  226  overlying gates  208 A and  208 B and extending over adjacent portions of the N+ source regions  222 . Next, metal layer  224  is deposited to form contacts with the N+ source regions  222  and the P+ body contact region  228 . The resulting structure is MOSFET  20 , shown in  FIG. 2 . 
     As noted above, buried source electrodes  212 A and  212 B are electrically connected (i.e., shorted) to source regions  222 . This connection can be made in a number of ways, and this invention is not limited to any particular technique. One way of making the connection between buried source electrodes  212 A and  212 B and source regions  222  will now be described, with reference to  FIGS. 5A–5G . 
       FIGS. 5A–5G  show a trench  204 C which is connected to trenches  204 A and  204 B but is located where a connection to buried source electrodes  212 A and  212 B is to be made. 
     As noted in the description of  FIG. 4H , the etching of polysilicon layer  248  is preferably performed in two stages. At the completion of the first stage, polysilicon layer  248  appears as shown in  FIG. 5A  in trench  204 C, with the surface of polysilicon layer  248  being approximately coplanar with the top surface of epi layer  202 . 
     As shown in  FIG. 5B , a photoresist mask layer  260  is deposited and photolithographically patterned to cover the location where the connection to buried source electrodes  212 A and  212 B is to be made. This segment of photoresist layer  260  remains in place during the second stage of the etching of polysilicon layer  248  and prevents further etching of polysilicon layer  248  at this location. 
     After polysilicon layer  248  as been etched a second time, as shown in  FIG. 4H , photoresist layer  260  is removed. After oxide layer  246  has been etched, as shown in  FIG. 4I , the structure appears as shown in  FIG. 5C . 
     After oxide layer  254  has been grown (see  FIG. 4J ), the structure appears as shown in  FIG. 5D . It remains in this state until P-body region  220 , N+ source regions  222  and P+ body contact region  228  have been formed and BPSG layer  226  has been deposited. 
     As shown in  FIG. 5E , BPSG layer  226  is patterned with an opening  225  over polysilicon layer  248 . This is done in the same process step which forms the openings over N+ source regions  222  and P+ body contact region  228 . 
     As shown in  FIG. 5F , oxide layer  254  is etched through the opening in BPSG layer  226  to expose the top surface of polysilicon layer  248 . 
     As shown in  FIG. 5G , when source metal layer  224  is deposited, it contacts the top surface of polysilicon layer  248 , thereby establishing an electrical contact between buried source regions  212 A,  212 B and N+ source regions  222 . 
       FIG. 6  illustrates a cross-sectional view of an alternative MOSFET in accordance with this invention. N-channel MOSFET  30  is formed in epitaxial (epi) layer  202  that is grown on N+ substrate  200 . Trenches  304 A and  304 B and are formed in epi layer  202 . Trenches  304 A and  304 B are separated by a mesa  306 . The components of trenches  304 A and  304 B are identical. Again, only trench  304 A will be described. 
     The upper portion of trench  304 A includes a polysilicon gate  308 A that is separated from mesa  306  by a gate oxide layer  310 A, which lines the sidewalls of the upper portion of trench  304 A. The lower portion of trench  304 A includes a buried source electrode  310 A, which is separated from N-drift region  314  (in mesa  306 ) and from N+ substrate  200  by a thick oxide layer  316 A. Buried source electrode  312 A is electrically connected to N+ source region  322  and P-body region  320  in the third dimension, outside the plane of  FIG. 6 . Thick oxide layer  316 A lines the sidewalls and bottom of the lower portion of trench  304 A. Buried source electrode  312 A is separated from gate  308 A by a thin oxide layer  318 A. 
     The upper portion of mesa  306  includes a P-body region  320  and an N+ source region  322 . The lower junction of P-body region  320  abuts N-drift region  314 . The drain of MOSFET  30  includes N+ substrate  200  and N-drift region  314 . 
     Overlying epi layer  202  is a source metal layer  324 , which contacts N+ source region  322  and P-body region  320 . A P+ region  328  provides an ohmic contact between metal layer  324  and P-body region  320 . Gate  308 A is insulated from source metal layer  224  by a BPSG layer  326 . 
     As described above in connection with MOSFET  20 , gate oxide layer  310 A has a thickness that is selected to provide the desired threshold voltage V th  for MOSFET  30 . Thick oxide layer  316 A has a thickness that can withstand the maximum drain-to-source breakdown voltage without rupture or damage. 
     Since the buried source electrodes  312 A,  312 B are tied to the N+ source region  322 , the full source-to-drain voltage is seen across thick oxide layer  316 A when MOSFET  30  is turned off. The doping concentration of N-drift region  314  is selected such that N-drift region  314  is fully depleted when the maximum drain-to-source voltage is reached, in the same manner as illustrated in  FIG. 3 . 
       FIGS. 7A–7H  illustrate a process that may be used to fabricate MOSFET  30 . The process begins by growing N-epi layer  202  on N+ substrate  200 . 
     Next, as shown in  FIG. 7A , a pad oxide layer  340  is thermally grown in the top surface of N-epi layer  202 , and a silicon nitride layer  342  is deposited on oxide layer  340 . Oxide layer  340  can have a thickness in the range of 250–300 Åand nitride layer  342  can have a thickness in the range of 2000–4000 Å. A photoresist mask layer (not shown) is formed over nitride layer  342 , and nitride layer  342  and oxide layer  340  are then photolithographically patterned and etched to form two openings which expose the top surface of epi layer  202 . Trenches  344 A and  344 B are formed by directionally etching epi layer  202  through the openings, preferably using an RIE process. Trenches  344 A and  344 B extend into epi layer  202  but not all the way to N+ substrate  200 . Pad oxide layer  340  and nitride layer  342  can then be removed. 
     As shown in  FIG. 7B , a second silicon nitride layer  346  is deposited over the top surface of N-epi layer  202 , preferably by a chemical vapor deposition (CVD) process. As shown, nitride layer  346  conforms to the contours of the trenches  344 A and  344 B. 
     Next, as shown in  FIG. 7C , nitride layer  346  is directionally etched, preferably by means of an RIE process. This process removes the horizontal portions of nitride layer  346 , including the portions on the floor of trenches  344 A and  344 B, but leaves those portions of nitride layer  346  that are attached to the sidewalls of trenches  344 A and  344 B. 
     As shown in  FIG. 7D , epi layer  202  is etched through the bottoms of trenches  344 A and  344 B to form cavities  348 A and  348 B, which in this embodiment extend downward to N+ substrate  200 . Beforehand, a mask layer (not shown) is deposited and patterned to prevent the top surface of mesa  306  from being affected by a subsequent dry etch. Nitride layer  346  is unaffected by this etching process and remains attached to the walls of trenches  344 A and  344 B. 
     As shown in  FIG. 7E , a thermal process is now used to form thick oxide layers  316 A and  316 B along the walls and floors of cavities  348 A and  348 B, respectively. Since nitride layers  346  are still in place, the familiar tapered “bird&#39;s beak” structure forms where the oxide undercuts the nitride. Nitride layers  346  are then removed, leaving the structure shown in  FIG. 7F . 
     Cavities  348 A and  348 B and trenches  344 A and  344 B are then filled with polysilicon, and the polysilicon is etched back into trenches  344 A and  344 B, using a dry etch process. The doping concentration of the polysilicon can be on the order of 10 20  cm −3 . Preferably, the surface of the polysilicon ends up just below the bird&#39;s beak portions of oxide layers  316 A and  316 B, where oxide layers  316 A and  316 B reach their full thickness. The result is the formation of polysilicon buried source electrodes  312 A and  312 B, which are electrically isolated from epi layer  202  by oxide layers  316 A and  316 B, as shown in  FIG. 7G . 
     Next, as shown in  FIG. 7H , gate oxide layers  310 A and  310 B are thermally grown on the sidewalls of trenches  344 A and  344 B. (Before this, a sacrificial oxide layer may be grown on and removed from the exposed sidewalls of the trenches  344 A and  344 B.). During the same thermal process that forms gate oxide layers  310 A and  310 B, thin oxide layers  318 A and  318 B are grown at 1050° C. on the top surface of buried source electrodes  312 A and  312 B. In the final series of steps, trenches  344 A and  344 B are filled with a second polysilicon layer, and the polysilicon is etched back to the mouths of trenches  344 A and  344 B, forming polysilicon gates  308 A and  308 B. As described above, P body regions  320 , N+ source regions  322  and P+ regions  328  are implanted and diffused into epi layer  202  The upper surface of epi layer  202  is covered with BPSG layer  326  and BPSG layer  326  masked, patterned and etched so that segments of BPSG layer cover gates  308 A and  308 B and overlap a portion of N+ source regions  322 . Metal layer  324  is then deposited, yielding MOSFET  30  shown in  FIG. 6 . 
     The buried source electrode can be contacted in a manner similar to that described above for MOSFET  20 . In particular, the first polysilicon layer is etched back in two stages, and the surface of the first polysilicon layer is temporarily masked after the first etch stage at the locations where the buried source electrode is to be contacted. Later, openings are formed in BPSG layer  326  in these locations, so that source metal layer  324  abuts the polysilicon layer. 
     As described above, a photoresist layer (not shown) is formed over BPSG layer  226 , and the photoresist layer is photolithographically patterned with openings over the locations where the source metal layer  224  to contact the N+ source/P+ regions  222 ,  228  (as shown in  FIG. 2 ) and over the locations where source metal layer  224  is to contact the polysilicon layer  248  (as shown in  FIG. 5G ). Source metal layer  224  is then deposited to form an electrical contact with N+ source/P+ regions  222 ,  228  and buried source electrodes  212 A,  212 B (via polysilicon layer  248 ). Similarly, in the embodiment shown in  FIG. 6 , BPSG layer  326  is patterned and etched with openings to allow source metal layer  324  to form an electrical contact with N+ source/P+ regions  322 ,  328  and buried source electrodes  312 A,  312 B. 
     BPSG layer  226  is also patterned with openings where the gates  208 A,  208 B are to be contacted, and a gate metal layer (not shown) is deposited in those openings to establish an electrical contact with gates  208 A,  208 B. Similarly, BPSG layer  326  is patterned with openings where gates  308 A,  308 B are to be contacted by a gate metal layer. Preferably, the gate metal layer is a part of a single metal layer that is deposited over the surface of the die and then etched to separate the source metal layer  224 ,  324  and the gate metal layer. 
     The trenches and mesas described above can be arranged in a variety of patterns on the surface of semiconductor die. One possible layout is shown in  FIGS. 9A–9E , which shows an annular pattern of trenches and mesas in the top surface of a semiconductor die  50 . Trenches  500 ,  504 ,  508  are in the form of square annuli or rings having rounded corners and are separated by mesas  502 ,  506 , which are likewise in the form of square annuli or rings having rounded corners. The corners of trenches  500 ,  504 ,  508  and mesas  502 ,  506  are rounded to prevent the high electric fields that would occur if the corners were sharp right-angles. The trenches and mesas surround a central region  510 , and an edge termination region  512  is located near the perimeter of die  50 , outside the annular pattern of trenches and mesas. 
     It should be understood that for the sake of clarity the pattern of trenches and mesas is greatly enlarged in  FIGS. 9A–9E . In reality, there would typically be thousands of trenches in the pattern. For example, die  50  might measure 2 mm×2 mm, and the trenches and mesas might be 1.5 μm wide. The cross-section  2 — 2  in  FIG. 9A  could be represented by  FIG. 2 , for example, with trenches  500  and  504  containing the elements of trenches  204 A and  204 B and mesa  502  having the structure of mesa  206  in  FIG. 2 . 
     In the particular embodiment illustrated in  FIG. 9A , the width of mesas  502 ,  506  and trenches  500 ,  504 ,  508  is constant and the corners are rounded.  FIG. 12  is a graph generated by computer simulation showing the breakdown voltage of a device (BV) as a function of the radius of curvature of the rounded trench corners. For example, at a radius of 15 μm, the breakdown voltage was about 85V. 
     As explained above in connection with  FIG. 5B , a photoresist layer  260  is deposited in the areas where contact is to be made to the buried source electrodes, after the gate polysilicon is etched back to the level of the surface of the epi layer  202  but before the gate polysilicon is etched back into the trench.  FIG. 9B  shows an illustrative layout of photoresist layer  260 . Cross-section  5 B— 5 B in  FIG. 9B  could be the cross-sectional view of  FIG. 5B , for example, with photoresist layer  260  overlying the polysilicon layer  248 . After photoresist layer  260  has been removed, and after oxide layer  254  and BPSG layer  226  are deposited and patterned, as shown in  FIG. 5F , openings  225  are formed at the locations where the buried source electrode is to be contacted. A plurality of openings  225  are shown in  FIG. 9C .  FIG. 9C  also shows openings  520  in BPSG layer  226 , where metal contacts to the N+ source/P+ regions are made over mesas  502 ,  506 , and openings  522  in BPSG layer  226 , where metal contacts to the gate are made. In this embodiment, openings  522  extend outward along diagonal lines from the central region  510  to the corners of die  50 . 
       FIG. 10  shows the structure at cross-section  10 — 10  in  FIG. 9C , with metal layer  224  in contact with buried polysilicon layer  248 , which constitutes the buried source electrode and extends in both directions below the gate polysilicon  249 . 
       FIG. 9D  shows source metal layer  224  superimposed over the openings  225 ,  520  and a gate metal layer  524  superimposed over the openings  522 . Source metal layer  224  makes contact with the buried source electrodes via openings  225  and with the source/body regions via openings  520 . Gate metal layer makes contact with the gate electrodes via the openings  522 .  FIG. 9E  is a top view of source metal layer  224  and gate metal layer  524  the finished device. It is evident that gate metal layer  524  includes four radial gate metal legs  524 A– 524 D, each of which extends outward from the central region along a diagonal line and that the source metal layer  224  includes four sections  224 A– 224 D that are located, respectively, in the regions between the legs of the gate metal legs  524 A– 524 D. 
     The invention is not limited to the particular geometric pattern shown in  FIG. 9E . For example, the radial legs of the gate metal layer could extend outward along lines corresponding to the 12:00. 3:00, 6:00 and 9:00 positions instead of diagonal lines, and the source metal layer could be positioned in between the legs of the gate metal layer. Moreover, the pattern of the annular trenches and mesas could be circular, rectangular or hexagonal (or some other polygonal shape) as shown in  FIGS. 11A–11C . When straight-line polygons are used, it will often be advantageous to round the corners to prevent unduly high electric fields from developing at the corners. The legs of the gate metal layer may extend outward at various radial intervals—e.g., 15°, 30°, 45°, 60° or 90°—depending on the geometry selected. 
     The annular layout patterns exemplified in  FIGS. 9A–9E  and  FIGS. 11A–11C  may also be used with conventional trench-gated devices such as the MOSFET illustrated in FIG.  1 ., wherein there would be no need for openings to connect the source metal layer to the buried source electrodes. 
     According to another aspect of the invention, the peripheral trench in the annular pattern shown in  FIGS. 9A–9E  can be made deeper than the trenches in the “active” regions of the device. This, in effect, makes the device “self-terminating.” An example of this structure is shown in  FIGS. 13A and 13B , where the peripheral trench  508  has been replaced by a trench  508 W that is deeper than trenches  500  and  504 . Preferably, to avoid the need for an additional masking step, trench  508 W is also made wider than trenches  500  and  504 . This is accomplished by making the opening in photoresist mask layer  242  ( FIG. 4C ) that is used to form trench  508 W correspondingly wider than the openings that are used to form trenches  500  and  504 . Therefore, in a normal etching process used to form the trenches  500 ,  540  and  508 W, trench  508 W will be etched deeper than trenches  500  and  504 . Alternatively, a separate masking step can be used to form the deeper trench, in which case it may be the same width as trenches  500  and  504 . 
       FIG. 13B  is a cross-sectional view of trenches  500 ,  504  and  508 W, showing that trench  508 W is filled with polysilicon layer  248 . Polysilicon layer  248  in trench  508 W can be formed in the process sequence shown in  FIGS. 5A–5C . Polysilicon layer  248  is contacted by source metal layer  224 . 
     It will be understood that in other embodiments the termination area may include two or more deep trenches at the periphery of the chip, instead of just the single deep trench  508 W shown in  FIGS. 13A and 13B . 
       FIG. 14  illustrates a cross-sectional view of an alternative embodiment according to the invention, in which the control gate is embedded in an oxide layer on the sides of the trench. MOSFET  70  contains many of the same components of MOSFET  20 , shown in  FIG. 2 . In particular, N− epitaxial layer  202  is grown on N+ substrate  200 , and trenches  204 A and  204 B extend through N− epitaxial layer  202  into N+ substrate  200 . P body region  220 , N+ source regions  222  and P+ body contact regions  228  are formed in N− epitaxial layer  202 . 
     Trenches  204 A and  204 B contain source electrodes  702 A and  702 B, which extend upward to a source metal layer  706 . The lower portions of source electrodes  702 A and  702 B are insulated from the N+ substrate  200  and N−epitaxial layer  202  by thick oxide layers  704 A and  704 B. Above thick oxide layers  704 A and  704 B are multilayer structures, each of which includes a control gate  708  embedded in a thin oxide layers  710 . A first section of thin oxide layer  710  is in contact with epitaxial layer  202  and a second section of thin oxide layer  710  is in contact with the source electrode  702 A or  702 B. Each control gate  708  is sandwiched between the first and second sections of thin oxide layer  710  and is insulated from source metal layer  706  by oxide layer  712  at the surface of epitaxial layer  220 . Source metal layer  706  contacts source electrodes  702 A and  702 B through openings  714  in oxide layer  712 . Source metal layer  706  contacts N+ source regions  222  and P+ body contact regions  228  through openings  716  in oxide layer  712 . As shown in  FIG. 14 . the multilayer structures comprising control pate  708  and oxide layers  710  may be approximately the same thickness as oxide layers  704 A and  704 B. 
       FIG. 15  illustrates a layout of MOSFET  70 , the cross-sectional view shown in  FIG. 14  being designated  14 — 14 . The annular pattern of trenches and mesas is similar to that shown in  FIGS. 9A–9E . Openings  714  for contacting source electrodes  702 A and  702 B are shown, as are openings  716  for contacting N+ source regions  222  and P+ body contact regions  228 . Source metal layer  224 , shown in  FIG. 9E , would contact source electrodes  702 A and  702 B, N+ source regions  222  and P+ body contact regions  228  through openings  714  and  716 . Also shown in  FIG. 15  are openings  718  in oxide layer  712 , through which gate metal legs  524 A– 524 D contact control gates  708 . 
       FIGS. 16A–16D  illustrate a process for fabricating MOSFET  70 .  FIG. 16A  shows the structure at a stage similar to that shown in  FIG. 5A , with thick oxide layers  704 A and  704 B on the walls and floor of trenches  204 A and  204 B, respectively, and polysilicon layer  702  etched back to the level of N−epitaxial layer  202 . 
     As shown in  FIG. 16B , thick oxide layers  704 A and  704 B are etched a predetermined distance down into the trenches, using a BOE (buffer oxide etch) that attacks silicon dioxide in preference to polysilicon or epitaxial silicon. This forms cavities between source electrodes  702 A and  702 B, respectively, and epitaxial layer  202 . 
     Next, a thin oxide layer  710  is thermally grown on the top surface of the structure. In each cavity, a first section of thin oxide layer  710  abuts a sidewall of the trench and a second section of thin oxide layer  710  abuts a sidewall of the source electrode. A second polysilicon layer  720  is deposited in the space between the first and second sections of thin oxide layer  710  in each cavity, leaving the structure shown in  FIG. 16C . 
     As shown in  FIG. 16D , polysilicon layer  720  is etched back until its top surface is approximately level with the top surface of epitaxial layer  202  to form control gates  708 . Next, referring to  FIGS. 14 and 15 , P body region  220 , N+ source regions  222  and P+ body contact regions  228  are implanted and diffused as described above, and the portions of thin oxide layer  710  on the top surface of epitaxial layer  202  are then etched. Oxide layer  712  is deposited on the surface of epitaxial layer  202  and then masked and etched to form openings  714 ,  716  and  718  to source electrodes  702 A and  702 B, N+ source regions, and control gates  708 , respectively. To complete the device, a metal layer is deposited and then patterned to form source metal layer  224  and gate metal legs  524 , and the device may be covered with a passivation layer (not shown). This produces MOSFET  70 , shown in  FIG. 14 . Note that in MOSFET  70  contact to the source electrodes  702 A,  702 B is made in every MOSFET cell. 
     It will be understood by those of skill in the art that the above-described embodiments are illustrative only, and not limiting. Many additional embodiments with the broad scope of this invention will be obvious from the description above.