Abstract:
A system for detecting transmission errors in a data transmission system includes a receiver for receiving a data packet transmitted thereto by a corresponding transmitter and transmitting the data packet to a destination device and an error detection device for receiving a plurality of protocol signals that control the operation of the transmitter and the receiver. The error detection device applies at least one predetermined rule to the protocol signals, wherein a violation of the at least one rule by the protocol signals indicates that an error in the transmission of the packet has occurred, and asserts an error signal when the at least one rule has been violated by the protocol signals. The system further includes a packet filtering device coupled to receive the error signal from the error detection device and the data packet from the receiver, wherein, upon receiving the asserted error signal, the packet filtering device terminates the transmission of the data packet to the destination device.

Description:
FIELD OF THE INVENTION 
   The present invention is directed generally to a data transmission system and, more particularly, to a data transmission system having improved latency with a reduced gate count and minimal number of handshake signals. 
   BACKGROUND OF THE INVENTION 
   A prior art data transmission system  100   a  as shown in  FIG. 1  includes a transmitter  102   a  for transmitting data to a receiver  104   a  over a data bus  106   a . When data DATA[ 0 ]-DATA[N] is to be transmitted from the transmitter  102   a  to the receiver  104   a , the transmitter  102   a  sends, along with the data, a data valid signal DV to notify the receiver that it is transmitting new data. The receiver  104   a  samples the data on the data bus  106   a  when the DV signal is asserted by the transmitter. 
   The frequency determining delay between the registers of the transmitter  102   a  and the registers of the receiver  104   a  is determined by the wire delay of the DV signal plus the fan-out delay of the DV signal feeding all of the multiplexers of the receiver  104   a . When the DV signal must be input to many multiplexers, and the distance between the transmitter  102   a  and receiver  104   a  is long, the DV signal loses strength during its transmission, causing an operation frequency bottleneck. Therefore, this implementation of the DV signal causes the entire chip on which the transmitter and receiver are included to run at lower frequencies than may be desirable. The same principle applies to the WAIT signal (not shown in  FIG. 1 ), which is transmitted from the receiver  104   a  to the transmitter  102   a  in a similar fashion as the DV signal, when the receiver pauses an ongoing data transmission. 
   One approach to increase the frequency of the data transmission system  100   a  is shown in  FIG. 2 . As shown in  FIG. 2 , data transmission system  100   b  includes a transmitter  102   b  for transmitting data to a receiver  104   b  over a data bus  106   b . Receiver  104   b  includes a register stage  108  for registering the data on the data bus  106   b , including the DV signal and the data DATA[ 0 ]-DATA[N]. 
   In this data transmission system  100   b , the long distance delay between the transmitter and receiver is split into two delays, which allows the data transmission system  100   b  to operate at higher frequencies. In this system  100   b , the DV signal and data are transmitted concurrently and registered in the register stage  108  and then the data is transmitted to the inputs of the multiplexers concurrently with the DV signal, which is transmitted to the control input of the multiplexers. 
   While this system  100   b  reduces the delay in transmitting the DV signal and enables the system to operate at higher frequencies, the latency of the system is increased and the gate count is increased significantly over the system  100   a.    
   Data transmission systems such as  100   a  and  100   b  typically include several transmitters  102  that compete with each other for the ability to transmit data to the receiver  104 . The receiver must arbitrate between the transmitters to grant access to the receiver by one transmitter at a time. Typically, this involves a series of handshake signals between the transmitter and receiver. For example, in order to gain access to the receiver for a data transmission, the transmitter requests the data transfer by asserting a request signal. When the receiver grants access to a particular transmitter, it asserts a grant signal to the particular transmitter. The transmitter then begins the transmission of the data and the data valid signal DV. The receiver then receives the data, but can pause the transmission by asserting the WAIT signal for the particular transmitter. Accordingly, the number of handshake signals required in this data transmission is four. 
   The number of handshake signals is directly proportional to the design complexity and verification time of the data transmission system. Therefore, fewer handshake signals will result in a less complex system that is simpler to design and which results in shorter verification times. 
   In the event that a transmitter should fail or a packet being transmitted by the transmitter be faulty, it is important for the receiver to be able to notified of the error so that it can react appropriately to reduce or eliminate the possibility of losing data. Typically, transmitters do not have error recovery mechanisms because their implementation can tend to be complicated. Therefore, the natural response of a faulty transmitter is to reset itself and then wait for instructions from its control unit. The transmitter&#39;s sudden failure might cause an unpredictable behavior on the receiver side, which in turn could have a catastrophic impact on the entire data transmission system. 
   SUMMARY OF THE INVENTION 
   The present invention is directed to a data transmission system having low latency and increased frequency of operation while having a reduced number of gates in the data transmission system and a reduced number of handshake signals. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     These and other features of the invention will become more readily apparent from the following detailed description when read together with the accompanying drawings, in which: 
       FIG. 1  is a schematic diagram of a prior art data transmission system; 
       FIG. 2  is a schematic diagram of another prior art data transmission system; 
       FIG. 3  is a block diagram of the data transmission system according to the present invention; 
       FIG. 4  is a more detailed schematic diagram of the data transmission system according to the present invention; 
       FIG. 5  is a waveform diagram showing the signals transmitted between the transmitter and receiver in the data transmission system of  FIGS. 3 and 4  according to the present invention; 
       FIG. 6  is a schematic block diagram of the data transmission system of the present invention showing multiple transmitters; 
       FIG. 7  is a waveform diagram showing the signals transmitted between first and second transmitters and the receiver according to the present invention; 
       FIG. 8  is a schematic block diagram of the error reporting device according to the present invention; and 
       FIG. 9  is a waveform diagram showing the signals transmitted between the transmitter and receiver in the data transmission system of  FIGS. 3 and 4  according to the present invention. 
   

   DETAILED DESCRIPTION 
   As shown in  FIG. 3 , the data transmission system  10  according to the invention includes a transmitter  12  coupled to a receiver  14  via a data bus  16 . The data transmission system  10  operates to transmit data between a data source and a data destination. The data source and data destination may be any devices between which data is transmitted. In one embodiment of the invention, the data source is a PCI Express module which transmits data to a number of data destinations or clients. 
   Transmitter  12  includes a number N of transmission devices T 0 -T N , each of which receive a data bit D[ 0 ]-D[N], respectively, for transmission from a data source (not shown) to the receiver  14 . In one embodiment of the invention, the number N is 72, i.e. bits  0 - 71 . It will be understood, however, that the selection of the number N depends on the transmission requirements of the system and therefore, any number N may be utilized. Transmitter  12  also includes a request signal transmission register T REQ , a data valid signal transmission register T DV  and a WAIT signal receiving register T WAIT . Receiver  14  includes a corresponding number N of reception devices R 0 -R N , each coupled to the data bus  16  to receive data bits D[ 0 ]-D[N], respectively, from the corresponding transmission device T 0 -T N . Reception devices R 0 -R N  each include outputs for passing the data bits D[ 0 ]-D[N] to the data destination (not shown). Receiver  14  also includes a data valid signal reception register R DV  and a WAIT signal transmission register R WAIT . The system  10  further includes arbitration logic device  18 , WAIT logic device  20  and data valid logic device  22 . 
     FIG. 4  is a schematic diagram showing an embodiment of the invention in which each of the transmission devices T 0 -T N  includes a multiplexer  24  and a register  26 . One input of the multiplexer  24  receives the data input, D[ 0 ]-D[N], from the data source. The output of the multiplexer  24  is coupled to the input of the register  28  and the output of the register  28  is coupled to an input of a corresponding reception device via the data bus  16 , as well as to the second input of the multiplexer  24 . The control input of multiplexer  24  is coupled to the WAIT signal. 
   Likewise, each of the reception devices R 0 -R N  includes a multiplexer  28  and a register  30 . One input of the multiplexer  28  receives the data input D[ 0 ]-D[N] from the corresponding transmission device T 0 -T N , respectively, via the data bus  16 . The output of the multiplexer  28  is coupled to the input of the register  30  and the output of the register  30  is coupled to the data destination, as well as to the second input of the multiplexer  28 . The control input of multiplexer  28  is coupled to the DV signal. 
   The operation of the data transmission system  10  will be described with reference to  FIG. 5 , which is a waveform diagram showing the timing of the signals REQ, WAIT, DV and DATA, as well as the clock. When data is to be transmitted by the data source, the data source instructs the data valid logic  22  to assert the data valid signal DV from data valid transmission register T DV . At time to, the DV signal is asserted from the data valid signal transmission register T DV  and received by the data valid signal reception register R DV . On the next clock, at time t 1 , the asserted DV signal is transmitted from the data valid signal reception register R DV  to the control inputs of each of the multiplexers  28  of the reception devices R 0 -R N . On the same clock, the data bits D[ 0 ]-D[N] are transmitted from the transmission devices T 0 -T N , respectively, to the first inputs of the corresponding multiplexer  28  for each of the reception devices R 0 -R N . The asserted DV signal input to each of the control inputs of the multiplexers  28  causes the multiplexer to pass the data bits D[ 0 ]-D[N] through the reception devices R 0 -R N  to the destination device. As shown in  FIG. 5 , as long as the DV signal is asserted, the data packets d 0 , d 1 , d 2 , d 3 , etc., each of which comprise all of bits D[ 0 ]-D[N] for each clock cycle, are transmitted through the receiver  14  to the destination device. Since the DV signal is one clock cycle ahead of the data, when the DV signal is deasserted by the data valid logic  22 , on the next clock cycle, when the deasserted DV signal is transmitted to the control input of the multiplexers  28  from the data valid signal reception register R DV , the multiplexer will pass the data bits at the second input thereof, OLD_D[ 0 ]-OLD_D[N], which is fed back from the output of the register  30 . 
   [In a similar fashion, when the receiver  14  needs to pause the transmission of data by the transmitter  12 , for example to enable a previous transmission from another transmitter to complete, the wait logic  20  instructs the WAIT signal transmission register R WAIT  to assert the WAIT signal to the WAIT signal receiving register T WAIT . The WAIT signal is asserted to the WAIT signal receiving register T WAIT  at time t 2  and the WAIT signal is transmitted by the WAIT signal receiving register T WAIT  to the control inputs of multiplexers  24  on the next clock cycle. As shown in  FIG. 5 , the transmission of the data is paused on the clock cycle after the WAIT signal is asserted. Since, as shown in the figure, the WAIT signal is only asserted for one clock cycle, the data packet d 2  is only paused for one cycle. 
   When the asserted WAIT signal is transmitted to the control input of the multiplexer  24 , the multiplexer  24  stops passing the data D[ 0 ]-D[N] from the first input thereof and passes the data OLD_D[ 0 ]-OLD_D[N], which is fed back from the output of the register  30 . This acts to hold the current data packet, d 2  in  FIG. 5 , at the output of transmission devices T 0 -T N . 
   Based on the rules of the protocol under which the data transmission system operates, which is described in more detail below with reference to  FIG. 9 , the states of the WAIT and DV signals must be monitored by the data valid logic  22  and WAIT logic  20 , respectively. Therefore, the WAIT signal is input to the data valid logic  22  and the DV signal is input to the WAIT logic  20 . One of the rules of the protocol is that the data valid signal DV cannot be asserted or deasserted while the WAIT signal is asserted. Therefore, each of the data valid logic  22  and the WAIT logic  20  must be aware of the state of the other signal during the operation of the system. 
   Accordingly, because the DV and WAIT signals are asserted and registered one clock cycle before the data is transmitted and the registered DV and WAIT signals are transmitted to the reception devices R 0 -R N  and transmission devices T 0 -T N , respectively, on the same clock cycle that the data is transmitted by the transmission devices T 0 -T N , the data transmission system  10  operates at a low latency, since only one extra clock cycle is required to transmit the DV and WAIT signals. However, because the DV and WAIT signals are registered on the receiving side, there is no delay in transmitting the DV and WAIT signals to the multiplexers. This enables the system  10  to operate at high frequencies. Lastly, because the data transmitted from the transmitter  12  to the receiver  14  does not need to be registered, the gate count of the system  10  is minimized. 
   In addition to using the WAIT signal to pause a current transmission as described above, the data transmission system of the invention also utilizes the WAIT signal to grant data transmission requests to the transmitters and to arbitrate data transmissions from multiple transmitters to the receiver.  FIG. 6  is a schematic block diagram showing this aspect of the invention. Data transmission system  40  includes a number K of transmitters  12 , TRANS 0 -TRANS K . Each of transmitters TRANS 0 -TRANS K  are constructed as shown in  FIG. 4  and operate as described above. Also shown in  FIG. 6  is a receiver system  42  which includes a number K of receivers  14 , REC 0 -REC K . Each of receivers REC 0 -REC K  are constructed as shown in  FIG. 4  and operate as described above. Receiver system  42  also includes arbitration logic  18 , wait logic  20  and a multiplexer device  44 . It will be understood that the number K may be any number, depending on the transmission requirements of the system. 
   Each transmitter TRANS 0 -TRANS K  outputs its data transfer request signal REQ 0 -REQ K  to the arbitration logic  18  and outputs the data that is transmitted DATA 0 -DATA K  to the receivers REC 0 -REC K . Each transmitter TRANS 0 -TRANS K  receives as an input a WAIT signal WAIT 0 -WAIT K  from the WAIT logic  20 . Arbitration logic device  18  receives as inputs each of the transmission request signals REQ output by the request signal transmission register T REQ  Of each of the transmitters  12 . When a transmitter  12  needs to transmit data to the receiver, it asserts its REQ signal from the request signal transmission register T REQ  to notify the receiver that it is requesting permission to transmit data. Along with the assertion of the REQ signal, the transmitter transmits the address to which the data transmission is being requested. The address is transmitted over the data bus  16  in the same manner as the data itself. In one embodiment of the invention, the WAIT signal WAIT 0 -WAIT K  is normally asserted. Referring to  FIG. 5  As shown at time to, the WAIT signal is asserted. This will pause the transmission of data by the transmitter  12 . In this instance, since no data is being transmitted at time t 3 , the asserted WAIT signal will stop the transmitter from beginning a new data transmission. At time t 4 , the transmitter asserts its REQ signal to request permission from the receiver to begin a data transmission. The address “addr” is transmitted to the receiver at this time. However, since the WAIT signal is asserted, the address is held on the data bus  16 . 
   The WAIT signal is sampled only in certain states i.e. in the data transmission state. So, when the transmitter is putting the address on the data bus  16  it does not sample the WAIT signal. This is because the protocol rule states that the address can be put onto the data bus  16  without any regard to WAIT signal. Once the address is put on the bus, then the transmitter goes into the state where it sends the data but only when there is no WAIT signal asserted. 
   At time t 5 , the WAIT signal for the transmitter is deasserted and, at time t 6 , the data valid signal DV is asserted by the transmitter. Since the data valid signal DV is registered on the receiver side, as described above, the data transmission begins one clock cycle after the assertion of the DV signal, at time t 7 . For the same reason, when the DV signal is deasserted at time t 8 , the data transmission ends one clock cycle later. 
   Since several of the K transmitters TRANS 0 -TRANS K  may request permission to transfer data to the receiver at the same time, the arbitration logic  18  must determine which of the requesting transmitters will be granted permission to transmit data. The data transmission system  40  of the invention utilizes the WAIT signals to grant permission to the selected transmitter, while preventing the remaining transmitters from transmitting data until the arbitration logic grants one of them permission to transmit.  FIG. 7  is a waveform diagram showing the signals REQ, WAIT and DV, as well as the clock and DATA signal associated with each of the transmitters TRANS 0  and TRANS 1 . At time to, the signals WAIT 0  and WAIT 1  from the WAIT logic  20  to TRANS 0  and TRANS 1 , respectively, are asserted. This prevents any data transmission from either of the transmitters. At time t 1 , both transmitters assert their respective request signals REQ 0  and REQ 1 , thereby both requesting permission to transmit data to the receiver at the same time. Concurrently with the assertion of the REQ signals, each transmitter TRANS 0  and TRANS 1  also transmits the address to which its data is to be transmitted to its corresponding receiver REC 0  and REC 1 , respectively. 
   As shown in  FIG. 6 , arbitration logic  18  receives the REQ signals, as well as at least a portion of the address from each transmitter, shown at  46 , which is transmitted to the corresponding receiver REC 0  and REC 1  on the data lines DATA 0  and DATA 1 . The arbitration logic  18  determines which of the transmitters TRANS 0  and TRANS 1  it will grant permission based on an arbitration scheme implemented by the arbitration logic  18 . Any type of arbitration scheme may be used, depending on the requirements of the data transmission system  40 . For example, the arbitration scheme may be a round robin scheme; certain transmitters may always be given priority over other transmitters; reads may be given priority over writes, etc. The portion  46  of the address input to the arbitration logic  18  will provide information to the arbitration logic  18  that will enable the arbitration logic to make a determination as to which transmitter will be granted permission to transmit data. For example, the portion  46  may include a bit or bits that identify the transmitters or that indicate whether the request is for a data read or data write. The implementation of the arbitration logic  18  will depend on the actual scheme employed by the system, and will be known to those of skill in the art. 
   Based on the result of the arbitration process carried out by arbitration logic  18 , arbitration logic  18  outputs an arbitration signal ARB to the WAIT logic  20 . Signal ARB instructs the WAIT logic  20  to deassert the WAIT signal for the transmitter that has been granted permission to transmit its data. In the example of  FIG. 7 , the arbitration logic  18  outputs an ARB signal that instructs the WAIT logic  20  to deassert the wait signal WAIT 0 , to enable transmitter TRANS 0  to transmit its data. Accordingly, at time t 2 , signal WAIT 0  is deasserted from WAIT signal transmission register R WAIT  to the WAIT signal receiving register T WAIT . One clock cycle later, at time t 3 , the WAIT 0  signal is transmitted from the WAIT signal receiving register T WAIT  to the multiplexers  24  and the DV logic  22 . With the WAIT 0  signal deasserted, the transmitter asserts its data valid signal DV at time t 3  and the data transmission from transmitter TRANS 0  to receiver REC 0  begins one clock later. 
   As shown in  FIG. 6 , each of the outputs of receivers REC 0  to REC K  are input to a multiplexer device  44 . The output of the arbitration logic  18  is input to the control input of the multiplexer device  44  and it controls which of the inputs to the multiplexer device  44  will be passed through to the output  48  of the receiver system  42 . Since, in this example, the signal ARB has instructed the WAIT logic  20  to deassert wait signal WAIT 0  to enable transmitter TRANS 0  to transmit its data DATA 0 , the ARB signal also instructs the multiplexer device  44  to pass the data DATA 0  from receiver REC 0  through the multiplexer device to the output  46 . Multiplexer device  44  prevents any old data on any of the non-selected transmitter-receiver pairs from passing through to the output  48 . 
   Referring back to  FIG. 7 , when the transmitter TRANS 0  is about to complete its transmission, it deasserts its DV 0  signal at time t 4 , and the data transmission is completed one clock later, when the deasserted DV signal is input to the multiplexers  28  from the DV signal receiving register R DV . When the data transmission is complete, the transmitter deasserts its request signal REQ 0 , and the arbitration logic instructs the WAIT logic  20  to assert the wait signal WAIT 0  to prevent an unauthorized data transmission from transmitter TRANS 0 . 
   During the data transmission by the transmitter TRANS 0 , the address output by the transmitter TRANS 1  is held on the outputs of the transmitter TRANS 1  because its wait signal WAIT 1  remains asserted by WAIT logic  20 . At time t 5 , based on the arbitration scheme implemented by arbitration logic  18 , the signal ARB output to the WAIT logic  20  instructs WAIT logic  20  to deassert the wait signal WAIT 1 , thus granting the transmitter TRANS 1  permission to begin its data transmission. The ARB signal also instructs the multiplexer device  44  to pass the data DATA 1  from receiver REC 1  through the multiplexer device to the output  48 . One clock after wait signal WAIT 1  is deasserted, transmitter TRANS 1  asserts its data valid signal DV 1  at time t 6  and the data transmission begins one clock later. One clock before the data transmission is complete, transmitter TRANS 1  deasserts its data valid signal DV 1  and, one clock later, deasserts its request signal REQ 1 . This results in the arbitration logic  18  instructing the WAIT logic to assert the WAIT signal WAIT 1  to prevent an unauthorized data transmission from transmitter TRANS 1 . 
   Accordingly, the data transmission system  40  enables the use of the WAIT signals for the purposes of delaying the commencement of a data transmission from a transmitter, arbitrating data transmission permission between multiple transmitters, as well as pausing a data transmission as it is taking place. 
   As described above, typical transmitters do not have error recovery mechanisms because their implementation can tend to be complicated. Therefore, the natural response of a faulty transmitter is to reset itself and then wait for instructions from its control unit. The transmitter&#39;s sudden failure might cause an unpredictable behavior on the receiver side, which in turn could have a catastrophic impact on the entire data transmission system. 
     FIG. 8  is a schematic block diagram of an error recovery mechanism  49  of the present invention. Shown in  FIG. 8  is one of the receivers REC 0  through which the data DATA 0  is transmitted. An error logic device  50  receives as an input the request signal REQ 0 , the data valid signal DV 0  and the wait signal WAIT 0 . Output from the error logic device  50  is an error signal ERR 0  which is input to a packet filtering unit  52 , along with the data DATA 0 . Although only one error recovery mechanism  49  is shown in  FIG. 8 , there is preferably an error recovery unit associated with each of the receivers REC 0 -REC K . 
   Error logic device  50  monitors the states of the request signal REQ 0 , the data valid signal DV 0  and the wait signal WAIT 0  and applies protocol rules set forth below to the relative states of the signals to determine whether an error, either in the operation of the associated transmitter or in the data that is being transmitted, has occurred. 
   While not an exhaustive list of the protocol rules that may be applied by the error logic unit, the following are examples of such rules: 
   1. The request signal REQ must not be deasserted if the WAIT signal is asserted. 
   2. The request signal REQ and the data valid signal DV must not be deasserted at the same time unless the transmitter is transmitting an erroneous data packet. 
   3. The data valid signal must not be asserted or deasserted while the WAIT signal is asserted. 
   A violation of any of the above rules is indicative of a faulty transmitter, or in the case of Rule 2, that the transmitter has detected a fault in the data packet being transmitted. As each data packet is transmitted through the receiver, the error logic unit  50  monitors the relative states of the request signal REQ 0 , the data valid signal DV 0  and the wait signal WAIT 0  and applies the above protocol rules and/or any others that may be defined for the system to the relative states of the signals to determine whether an error either in the operation of the associated transmitter or in the data that is being transmitted has occurred. If any of the defined rules, such as those set forth above, are violated, the error logic device  50  asserts the error signal ERR 0  to the packet filtering unit  52 . During normal operation, the packet filtering unit  52  collects and stores the bits of each data packet before it is output to the multiplexer device  44  when the transmission of the entire data packet is completed. However, when the error signal ERR 0  is asserted, the packet filtering unit will drop the entire packet before it is output to the multiplexer  44 . The dropping of the entire packet will enable the receiver to continue operating normally, rather than the case where an erroneous or incomplete packet is transmitted through the receiver, in which case, the receiver may fail or cause erroneous data to be transmitted to the data destination. 
   As shown in  FIG. 9  at time to, when the request signal REQ 0  and the data valid signal DV 0  are deasserted at the same time in violation of Rule 2, the error logic device  50  asserts the error signal ERR 0  to the packet filtering unit  52 , which drops the entire packet from being transmitted to the multiplexer device  44 . As shown at time t 1 , if the request signal REQ 0  is deasserted while the WAIT signal WAIT 0  is asserted, in violation of Rule 1, the error logic device  50  again asserts the error signal ERR 1  to the packet filtering unit  52 , which drops the entire packet, which in this case is the address, from being transmitted to the multiplexer device  44 . 
   Alternatively, instead of dropping the entire packet, the packet filtering unit  52  may alter the packet in such a way as to notify downstream error-checking devices (not shown) that the packet is faulty. For example, the packet filtering unit  52  may introduce a parity error, a CRC error, etc. This would allow the faulty packet to be transmitted downstream, but would insure that the faulty packet is identified and possibly corrected by error checking devices of the system. 
   The implementation of the error logic device  50  and the packet filtering unit  52  will depend on the rules that will be monitored and the resulting action to be taken. It will be understood that such implementation will be known to those of skill in the art. 
   Accordingly, the error recovery mechanism  48  enables the data transmission system  40  to identify and react to errors on the transmission side of the system by monitoring the relative states of the request signal REQ 0 , the data valid signal DV 0  and the wait signal WAIT 0 . Predefined protocol rules are applied to the signals and action is taken when one or more of the rules are violated. The error recovery mechanism makes use of preexisting signals of the system to notify the receiver of errors in the transmitter and/or in the transmitted data. The receiver is then able to react accordingly and the possibility of a receiver failure resulting from a transmitter failure is greatly reduced. 
   The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, while the invention is described as having a one clock cycle delay between the assertion of the data valid and WAIT signals and the result of the assertion of these signals, it will be understood that the particular number of clock cycles can vary and that any number of clock cycles may be utilized for the delay, with the resulting variation in the operating frequency of the transmission system. The present embodiments are therefore to be considered in respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of the equivalency of the claims are therefore intended to be embraced therein.