Abstract:
A processor has a central processing unit and a first interface. The central processing unit sets a communication parameter in a configuration register in the communication interface. A direct memory access controller or a data transfer controller then sets the same parameter in a register in a communication setup interface or an output port controller, which transmits the parameter to an external device with which the processor communicates through the communication interface. Alternately, the central processing unit sets the communication parameter in the communication setup interface or output port controller, and the direct memory access controller or data transfer controller sets the same parameters in the configuration register in the communication interface. Either scheme reduces the load on the central processing unit.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of communication between a processor and an external device, and to a processor employing this method of communication.  
         [0003]     2. Description of the Related Art  
         [0004]     Japanese Unexamined Patent Application Publication No. 5-336296 discloses a communication method in which the functions of a communication terminal such as a facsimile machine are set up according to values sent through an interface that connects the terminal to a host computer.  
         [0005]     Japanese Unexamined Patent Application Publication No. 6-46103 discloses a communication method in which, upon reception of data according to a predetermined protocol, a central processing unit (CPU) sends a direct memory access (DMA) request signal to a DMA controller, which then transfers data between a memory device and a communication device without CPU intervention.  
         [0006]     In conventional communication methods such as these, when a processor transmits internal data to an external device, or receives data from an external device, it is first necessary to set configuration data, such as data specifying the data communication speed or bit rate, in both the external device and the processor&#39;s data communication interface. Both settings are conventionally carried out by the processor&#39;s CPU, but this places an undesirable burden on the CPU, particularly when the configuration data have to be set frequently.  
       SUMMARY OF THE INVENTION  
       [0007]     An object of the present invention is to provide a method of communication between a processor and an external device in which the processor&#39;s CPU does not have to set configuration data such as data specifying the communication speed both in the processor&#39;s data communication interface and in the external device.  
         [0008]     The invention pertains to a processor having a CPU, a first interface for transferring data between the processor and an external device, and a second interface for controlling the external device. In the invented communication method, the CPU sets a communication parameter in either the first interface or the second interface. The communication parameter is then transferred to either the second interface or the first interface without CPU intervention. The communication parameter is also transferred from the second interface to the external device, after which data are transferred between the processor and the external device through the first interface according to the communication parameter.  
         [0009]     The first interface is thus a data communication interface. The second interface may be a communication setup interface, for example, or an output port and its controller. The communication parameter may be specified by configuration data.  
         [0010]     As means of transferring the communication parameter without CPU intervention, the processor may have a DMA controller. The communication parameter may be stored in a memory and read from the memory by both the CPU and the DMA controller. A plurality of communication parameters, stored at different addresses in the memory, may be transferred in this way.  
         [0011]     Alternatively, as means of transferring the communication parameter without CPU intervention, the processor may have a data transfer controller that transfers the communication parameter from the first interface to the second interface, or from the second interface to the first interface, preferably over a dedicated bus. If the first or second interface is capable of transferring data on the dedicated bus, the means of transferring the communication parameter without CPU intervention may simply comprise the dedicated bus.  
         [0012]     According to the invention, the CPU processing load occasioned by communication with the external device is reduced because the CPU has to set the communication parameter in only one place. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0013]     In the attached drawings:  
         [0014]      FIG. 1  is a block diagram of a processor connected to an external device according to a first embodiment of the invention;  
         [0015]      FIG. 2  is a block diagram of a processor connected to an external device according to a second embodiment;  
         [0016]      FIG. 3  is a block diagram of a processor connected to an external device according to a third embodiment;  
         [0017]      FIG. 4  is a block diagram of a processor connected to an external device according to a fourth embodiment;  
         [0018]      FIG. 5  is a block diagram of a processor connected to an external device according to a fifth embodiment;  
         [0019]      FIG. 6  is a block diagram of a processor connected to an external device according to a sixth embodiment; and  
         [0020]      FIG. 7  is a block diagram of a processor connected to an external device according to a seventh embodiment. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0021]     Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.  
         [0022]     A first embodiment of the invention will be described with reference to  FIG. 1 , which shows a processor  1  connected to a digital-to-analog converter (DAC)  2  as part of a digital audio player  3 .  
         [0023]     The processor  1  includes a read-only memory (ROM)  4  storing control programs for implementing various functions of the player  3 , a CPU  5  that operates according to the control programs stored in the ROM  4  to function as the master controller of the player  3 , a random access memory (RAM)  6  for temporary data storage, and an interface unit  7 , these components being interconnected by a data bus DB and an address bus AB. The RAM  6  is used for storing audio data such as, for example, data in the well-known MP3 (Music Player 3) format.  
         [0024]     The interface unit  7  includes a data communication interface  11  that performs serial data communication with the digital-to-analog converter  2  according to the I 2 S protocol through a data interface channel  8 , and a communication setup interface  12  that performs serial data communication according to the I 2 C protocol through a control interface channel  9  to set configuration data in a configuration register in the digital-to-analog converter  2 . The interface unit  7  additionally includes a DMA (Direct Memory Access) controller  13 . Incidentally, I 2 S and I 2 C are registered trademarks, I 2 S denoting Inter-IC Sound and I 2 C denoting Inter-IC Control.  
         [0025]     The data communication interface  11  includes a configuration register  21  for configuration data storage and a communication data register  22  for storing data to be transmitted. The communication setup interface  12  includes a setup data register  23  for storing configuration data to be set in an external device.  
         [0026]     Audio data read from a medium (not shown) such as a CD (compact disc) or a DVD (digital versatile disc) are temporarily stored in the RAM  6 ; the stored audio data are transmitted to the digital-to-analog converter  2  through the data communication interface  11 , converted to an analog sound signal, and output through headphones (not shown) or another device, thereby reproducing music or other audible matter that has been recorded as the audio data.  
         [0027]     When audio data are transmitted from the processor  1  to the digital-to-analog converter  2  as described above, it is necessary to set configuration data, such as data specifying the data communication speed or bit rate, in both the data communication interface  11  and the digital-to-analog converter  2 . To set the configuration data in the digital-to-analog converter  2 , the configuration data are written in the setup data register  23  in the communication setup interface  12 , then transmitted to the digital-to-analog converter  2  through the control interface channel  9 .  
         [0028]     The first embodiment uses the following novel method of setting configuration data: the CPU  5  sets the configuration data in the data communication interface  11 ; then the DMA controller  13  sets the configuration data in the setup data register in the communication setup interface  12 .  
         [0029]     A description of the operation of the player will be given below, focusing on the procedure for setting the configuration data described above. This procedure can be divided into eleven steps, numbered S 1  to S 11  below. The configuration data are denoted D 2 , D 7   a , D 7   c , and D 8  in  FIG. 1 , different reference characters being used in different steps in the procedure.  
         [0030]     First, in step S 1 , the CPU  5  reads data to be transmitted from the RAM  6 , and writes the data (D 1 ) in the communication data register  22  in the data communication interface  11 . In the following description it will be assumed that the data D 1  are digital audio data.  
         [0031]     Next, in step S 2 , the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 2 ) in the configuration register  21  in the data communication interface  11 . In the following description it will be assumed that the configuration data D 2  specify a serial communication speed. Needless to say, the configuration data D 2  may specify other communication parameters as well.  
         [0032]     In step S 3 , when the data have been written in the configuration register  21  in the data communication interface  11 , the data communication interface  11  outputs a configuration setting signal (C 3 ) to the DMA controller  13 .  
         [0033]     In step S 4 , the DMA controller  13  responds to this configuration setting signal C 3  by sending the communication setup interface  12  a configuration setting notification signal (C 4 ). This signal notifies the communication setup interface  12  that the configuration data have been set in the configuration register  21  in the data communication interface  11 .  
         [0034]     In step S 5 , the communication setup interface  12  responds to this signal C 4  by sending a configuration request signal (C 5 ) to the DMA controller  13 .  
         [0035]     In step S 6 , upon receiving the configuration request signal C 5  from the communication setup interface  12 , the DMA controller  13  asserts a bus request signal (C 6 ). The CPU  5  then relinquishes the right to use the data bus DB and address bus AB, and the DMA controller  13  obtains this right.  
         [0036]     In step S 7 , the DMA controller  13  reads the configuration data (D 7   a ) from a prescribed address in the RAM  6  onto the data bus DB, outputs a write signal (C 7   b ) to the communication setup interface  12 , and thereby writes the configuration data (D 7   c ) from the data bus DB into the setup data register  23  in the communication setup interface  12 . The prescribed address in the RAM  6  may be given as a fixed value in the DMA controller  13  in advance, or the CPU  5  may inform the DMA controller  13  of the prescribed address prior to step S 1 .  
         [0037]     In step S 8 , when the configuration data have been written in the setup data register  23 , the communication setup interface  12  sends the configuration data (D 8 ) in the setup data register  23  to the digital-to-analog converter  2  by serial transmission.  
         [0038]     In step S 9 , when the serial transmission has been completed, the communication setup interface  12  outputs a configuration setting completion signal (C 9 ) to the DMA controller  13 .  
         [0039]     In step S 10 , upon receiving this completion signal C 9 , the DMA controller  13  outputs a configuration setting completion signal (C 10 ) to the data communication interface  11 .  
         [0040]     In step S 11 , upon receiving this configuration setting completion signal C 10 , the data communication interface  11  sends the audio (or other) data (D 11 ) stored in the communication data register  22  to the digital-to-analog converter  2  by serial transmission at the communication speed set in the configuration register  21 .  
         [0041]     The digital-to-analog converter  2  converts the received audio data to an analog signal, which is reproduced as music or the like. The data communication speed specified by the configuration data may be a comparatively low speed, corresponding to an audio sampling rate on the order of 50 KHz, for example.  
         [0042]     As described above, in the first embodiment, the CPU  5  only has to write transmit data in the communication data register  22  in the data communication interface  11  in step S 1  and configuration data in the configuration register  21  in the data communication interface  11  in step S 2 . The rest of the procedure, up to the start of serial transmission by the data communication interface  11  in step S 11 , is performed under control of the DMA controller  13 . The processing load on the CPU  5  is thereby reduced.  
         [0043]     It is particularly necessary to set the data communication speed in both the data communication interface  11  and the digital-to-analog converter  2 , but in the first embodiment, the CPU  5  has to set the data communication speed only in the data communication interface  11 ; the DMA controller  13  sets the data communication speed in the digital-to-analog converter  2 .  
         [0044]     Although only the data communication speed was mentioned as configuration data in the description above, if it is necessary to set other configuration information as well, such as information specifying the serial data format, and if the amount of configuration data is greater than the capacity of the setup data register  23 , steps S 7  and S 8  may be carried out repeatedly. For example, a plurality of items of configuration data may be stored in consecutive addresses in the RAM  6 . The DMA controller  13  transfers one item of configuration data from the RAM  6  to the setup data register  23 , increments the memory address value by one while the communication setup interface  12  is transmitting the item to the digital-to-analog converter  2 , and then transfers the next item of configuration data to the setup data register  23 .  
         [0045]     In a variation of the first embodiment, the CPU  5  relinquishes the right to use the data and address buses immediately after setting the configuration data (D 2 ) in the configuration register  21  in the data communication interface  11  in step S 2 . The DMA controller  13  can then obtain the right to use the buses immediately after asserting the bus request signal C 6  in step S 6 , without having to wait for the CPU  5  to relinquish the bus right.  
       Second Embodiment  
       [0046]     A second embodiment of the invention will be described with reference to  FIG. 2 .  
         [0047]     The processor  31  in the second embodiment differs from the processor in the first embodiment by replacing the DMA controller with a data transfer controller  32 , and including a dedicated data bus  33 . Whereas the DMA controller in the first embodiment transferred configuration data from the RAM  6  into the setup data register  23  in the communication setup interface  12 , the data transfer controller  32  in the second embodiment transfers configuration data from the configuration register  21  in the data communication interface  11  to the setup data register  23  in the communication setup interface  12 , using the dedicated data bus  33 .  
         [0048]     A description of the operation of a digital audio player will be given below, focusing on the procedure for setting configuration data. This procedure can be divided into ten steps, numbered S 21  to S 30  below. The configuration data are denoted D 2 , D 26   c , and D 8  in  FIG. 2 , different reference characters being used in different steps in the procedure.  
         [0049]     First, in step S 21 , the CPU  5  reads data to be transmitted from the RAM  6 , and writes the data (D 1 , digital audio data, for example) in the communication data register  22  in the data communication interface  11 .  
         [0050]     Next, in step S 22 , the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 2 ) in the configuration register  21  in the data communication interface  11 . As in the first embodiment, it will be assumed that the configuration data D 1  specify a serial communication speed.  
         [0051]     In step S 23 , when the data have been written in the configuration register  21  in the data communication interface  11 , the data communication interface  11  outputs a configuration setting signal (C 3 ) to the data transfer controller  32 .  
         [0052]     In step S 24 , the data transfer controller  32  responds to this configuration setting signal C 3  by sending the communication setup interface  12  a configuration setting notification signal (C 24 ), notifying the communication setup interface  12  that the configuration data have been set in the configuration register  21  in the data communication interface  11 .  
         [0053]     In step S 25 , the communication setup interface  12  responds to this signal C 24  by sending a configuration request signal (C 25 ) to the data transfer controller  32 .  
         [0054]     In step S 26 , upon receiving the configuration request signal C 25  from the communication setup interface  12 , the data transfer controller  32  outputs a read signal (C 26   a ) to the configuration register  21  in the data communication interface  11  and a write signal (C 26   b ) to the setup data register  23  in the communication setup interface  12 . As a result, the data transfer controller  32  reads the configuration data stored in the configuration register  21 , transfers the data (D 26   c ) to the setup data register  23  through the dedicated data bus  33 , and writes the data (D 26   c ) in the setup data register  23 .  
         [0055]     In step S 27 , when the configuration data have been written in the setup data register  23 , the communication setup interface  12  sends the configuration data (D 8 ) in the setup data register  23  to the digital-to-analog converter  2  by serial transmission.  
         [0056]     In step S 28 , when the serial transmission has been completed, the communication setup interface  12  outputs a configuration setting completion signal (C 9 ) to the data transfer controller  32 .  
         [0057]     In step S 29 , upon receiving this completion signal C 9 , the data transfer controller  32  outputs a configuration setting completion signal (C 10 ) to the data communication interface  11 .  
         [0058]     In step S 30 , upon receiving the configuration setting completion signal C 10 , the data communication interface  11  sends the data (D 11 ) stored in the communication data register  22  to the digital-to-analog converter  2  by serial transmission at the communication speed set in the configuration register  21 .  
         [0059]     If other configuration information, such as information specifying the serial data format, must be set in the digital-to-analog converter  2 , the CPU  5  transmits these configuration data to the digital-to-analog converter  2  through the communication setup interface  12 . The serial data format has to be set in the digital-to-analog converter  2  only, for example, when the device is turned on; the data communication speed must be set more frequently. Accordingly, even if the CPU  5  has to set the serial data format and other infrequently changed configuration information in the digital-to-analog converter  2 , the processing load on the CPU  5  is still significantly reduced.  
         [0060]     As described above, in the second embodiment, as in the first embodiment, the CPU  5  only has to write transmit data in the communication data register  22  in the data communication interface  11  in step S 21  and configuration data in the configuration register  21  in the data communication interface  11  in step S 22 . The rest of the procedure, up to the start of serial transmission by the data communication interface  11  in step S 30 , is performed without intervention by the CPU  5 , the processing load on which is reduced accordingly. Since the dedicated data bus  33  is used to transfer the configuration data, the CPU  5  does not have to relinquish the right to use the data bus DB and address bus AB; it can use these buses to perform other processing while the data transfer controller  32  is setting the communication speed in the setup data register  23  in the communication setup interface  12 .  
       Third Embodiment  
       [0061]     A third embodiment of the invention will be described with reference to  FIG. 3 .  
         [0062]     The processor  41  in the third embodiment differs from the processor  31  in the second embodiment in  FIG. 2  by inserting a decoder  34  on the dedicated data bus  33  between the configuration register  21  and the setup data register  23 . In the third embodiment, when configuration data are transferred from the configuration register  21  to the setup data register  23 , the decoder  34  reformats the transferred configuration data.  
         [0063]     When the configuration data format used in the data communication interface  11  differs from the format used in the digital-to-analog converter  2 , the decoder  34  receives the configuration data, converts the format of the received configuration data from the format suitable for the configuration register  21  in the data communication interface  11  to the format suitable for being set in the digital-to-analog converter  2 , and transfers the reformatted configuration data.  
         [0064]     Aside from this reformatting, the third embodiment operates in the same way as the second embodiment and provides the same effects.  
       Fourth Embodiment  
       [0065]     A fourth embodiment of the invention will be described with reference to  FIG. 4 .  
         [0066]     The processor  41  in the fourth embodiment differs from the processor  41  in the third embodiment by replacing the communication setup interface  12  and the digital-to-analog converter  2  with an output port controller  42  and a digital-to-analog converter  43  that does not include a register for storing configuration data. The digital-to-analog converter  43  operates according to control signals applied to a control input terminal  43   c.    
         [0067]     Whereas, in the third embodiment, configuration data to be set in the digital-to-analog converter  2  are written in the setup data register  23  in the communication setup interface  12 , and the setup data register  23  transmits the configuration data to the digital-to-analog converter  2 , in the fourth embodiment, configuration data, such as data specifying the data communication speed, are written in a control data register  44  in the output port controller  42 , the output port controller  42  outputs the configuration data from an output port  42   p  continuously to the control input terminal  43   c  in the digital-to-analog converter  43  as control signals, and the digital-to-analog converter  43  operates according to the control signals applied to the control input terminal  43   c . For example, the digital-to-analog converter  43  operates at the communication speed specified by the control signals applied to the control input terminal  43   c.    
         [0068]     A detailed description of the operation at the start of data communication will be given below, focusing on the procedure for setting configuration data in the configuration register  21  in the data communication interface  11  and in control data register  44  in the output port controller  42 . This procedure can be divided into six steps, numbered S 41  to S 46  below. The configuration data are denoted D 2 , D 43   b , D 43   c  and D 44  in  FIG. 4 , different reference characters being used in different steps in the procedure.  
         [0069]     First, in step S 41 , the CPU  5  reads data to be transmitted from the RAM  6 , and writes the data (D 1 , digital audio data, for example) in the communication data register  22  in the data communication interface  11 .  
         [0070]     Next, in step S 42 , the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 2 ) in the configuration register  21  in the data communication interface  11 . As in the preceding embodiments, it will be assumed that the configuration data D 1  specify a serial communication speed.  
         [0071]     In step S 43 , when the data have been written in the configuration register  21  in the data communication interface  11 , the data communication interface  11  outputs a write signal (C 43   a ) to control data register  44  in the output port controller  42 , and outputs the configuration data (D 43   b ) stored in the configuration register  21  onto the dedicated data bus  33 . The decoder  34  decodes (reformats) the configuration data on the dedicated data bus  33 , and outputs the reformatted data (D 43   c ) to the output port controller  42 . As a result, the configuration data that the decoder  34  has reformatted are written in control data register  44  in the output port controller  42  as control data.  
         [0072]     In step S 44 , when the configuration data have been written in control data register  44 , the output port controller  42  begins the output of the data (D 44 ) from the output port  42   p . As a result, the digital-to-analog converter  43  operates at the communication speed set according to the control signals applied to the control input terminal  43   c.    
         [0073]     In step S 45 , the output port controller  42  outputs an output port setting completion signal (C 45 ) to the data communication interface  11  immediately after beginning the output of the control signals.  
         [0074]     In step S 46 , upon receiving the output port setting completion signal C 45 , the data communication interface  11  sends the data (D 11 ) stored in the communication data register  22  to the digital-to-analog converter  43  by serial transmission at the communication speed specified by the configuration data set in the configuration register  21 .  
         [0075]     Although the data communication speed was mentioned as configuration data in the description above, if it is necessary to apply other configuration information as well, such as information specifying the serial data format, to a control input terminal  43   d  in the digital-to-analog converter  43 , the output port controller  42  may include another data register (control data register  46  in  FIG. 4 , for example); the CPU  5  sets the other configuration data in control data register  46 , and the output port controller  42  outputs these configuration data from an additional output port  42   q  to control input terminal  43   d.    
         [0076]     The serial data format has to be written in control data register  46  only, for example, when the device is turned on; the data communication speed must be set in control data register  44  more frequently. Accordingly, even if the CPU  5  has to write the serial data format and other infrequently changed configuration information in control data register  46 , the processing load on the CPU  5  is still significantly reduced.  
         [0077]     As described above, in the fourth embodiment, as in the first, second, and third embodiments, the CPU  5  only has to write transmit data in the communication data register  22  in the data communication interface  11  in step S 41  and configuration data in the configuration register  21  in the data communication interface  11  in step S 42 . The rest of the procedure, up to the start of serial transmission by the data communication interface  11  in step S 46 , is performed without intervention by the CPU  5 , the processing load on which is reduced accordingly.  
         [0078]     Although the fourth embodiment shown in  FIG. 4  includes the decoder  34 , if the configuration data format suitable for use in the data communication interface  11  and the format suitable to be applied to the control input terminal in the digital-to-analog converter  43  are the same, the decoder  34  may be omitted, and the data stored in the configuration register  21  in the data communication interface  11  may be written in the control data register  44  in the output port controller  42  without being reformatted.  
       Fifth Embodiment  
       [0079]     Although the CPU  5  sets configuration data in the configuration register in the data communication interface  11  in the embodiments described above, the invention also provides processors in which the CPU  5  writes configuration data in the setup data register in the communication setup interface  12  or in the control data register in the output port controller  42 , and the configuration data are written in the configuration register in the data communication interface by the DMA controller, the data transfer controller, or the decoder. The fifth, sixth, and seventh embodiments described below are examples of such processors. These embodiments also reduce the CPU processing load.  
         [0080]     The fifth embodiment, which is generally similar to the first embodiment, will be described with reference to  FIG. 5 .  
         [0081]     Whereas, in the first embodiment, a configuration setting signal (C 3 ) is output from the configuration register  21  in the data communication interface  11  to the DMA controller  13 , a configuration setting notification signal (C 4 ) and a write signal (C 7   b ) are output from the DMA controller  13  to the setup data register  23  in the communication setup interface  12 , and a configuration request signal (C 5 ) is output from the setup data register  23  to the DMA controller  13 , in the fifth embodiment, a configuration setting signal (C 53 ) is output from the setup data register  23  to the DMA controller  13 , a configuration setting notification signal (C 54 ) and a write signal (C 57   b ) are output from the DMA controller  13  to the configuration register  21 , and a configuration request signal (C 55 ) is output from the configuration register  21  to the DMA controller  13 .  
         [0082]     The communication data register  22  begins communication with the digital-to-analog converter when it receives a signal C 10  from the DMA controller  13  and a signal C 57   d  from the configuration register  21 .  
         [0083]     A description of the operation of the digital audio player will be given below, focusing on the procedure for setting the configuration data. This procedure can be divided into eleven steps, numbered S 51  to S 61  below. The configuration data are denoted D 52 , D 57   a , D 57   c , and D 8  in  FIG. 5 , different reference characters being used in different steps in the procedure.  
         [0084]     First, in step S 51 , the CPU  5  reads data to be transmitted from the RAM  6 , and writes the data (D 1 , digital audio data, for example) in the communication data register  22  in the data communication interface  11 .  
         [0085]     Next, in step S 52 , the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 52 ) in the setup data register  23  in the communication setup interface  12 . As in the preceding embodiments, it will be assumed that the configuration data D 1  specify a serial communication speed.  
         [0086]     In step S 53 , when the data have been written in the setup data register  23  in the communication setup interface  12 , the communication setup interface  12  outputs a configuration setting signal (C 53 ) to the DMA controller  13 .  
         [0087]     In step S 54 , the DMA controller  13  responds to the configuration setting signal C 53  by sending the data communication interface  11  a configuration setting notification signal (C 54 ). This signal notifies the data communication interface  11  that the configuration data have been set in the setup data register  23  in the communication setup interface  12 .  
         [0088]     In step S 55 , the data communication interface  11  responds to this signal C 54  by sending a configuration request signal (C 55 ) to the DMA controller  13 .  
         [0089]     In step S 56 , upon receiving the configuration request signal C 55  from the data communication interface  11 , the DMA controller  13  asserts a bus request signal (C 56 ). The CPU  5  then relinquishes the right to use the data bus DB and address bus AB, and the DMA controller  13  obtains this right.  
         [0090]     In step S 57 , the DMA controller  13  reads the configuration data (D 57   a ) from a prescribed address in the RAM  6  onto the data bus DB, outputs a write signal (C 57   b ) to the data communication interface  11 , and thereby writes the configuration data (D 57   c ) from the data bus DB into the configuration register  21  in the data communication interface  11 .  
         [0091]     When the configuration data have been written in the configuration register  21 , a configuration setting completion signal (C 57   d ) is output to the communication data register  22 .  
         [0092]     In step S 58 , when the configuration data (D 52 ) have been written in the setup data register  23  in step S 52 , the communication setup interface  12  sends the configuration data (D 8 ) in the setup data register  23  to the digital-to-analog converter  2  by serial transmission, concurrent with the operations in steps S 53  to S 57 .  
         [0093]     In step S 59 , when the serial transmission has been completed, the communication setup interface  12  outputs a configuration setting completion signal (C 9 ) to the DMA controller  13 .  
         [0094]     In step S 60 , upon receiving this configuration setting completion signal C 9 , the DMA controller  13  outputs a configuration setting completion signal (C 10 ) to the data communication interface  11 .  
         [0095]     In step S 61 , when the communication data register  22  has received both configuration setting completion signals C 10  and C 57   d  from the DMA controller  13  and from the configuration register  21 , the data communication interface  11  sends the audio (or other) data (D 11 ) stored in the communication data register  22  to the digital-to-analog converter  2  by serial transmission at the communication speed set in the configuration register  21 .  
         [0096]     As described above, in the fifth embodiment, when the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 52 ) in the setup data register  23  in the communication setup interface  12 , the DMA controller  13  reads the same configuration data from the RAM  6  and writes the data (D 57   c ) in the configuration register  21  in the data communication interface  11 . When the DMA controller  13  has written the data (D 57   c ) in the configuration register  21 , and the setup data register  23  in the communication setup interface  12  has sent the configuration data to the digital-to-analog converter  2  by serial transmission, the communication data register  22  begins the transmission of other data to the digital-to-analog converter  2 .  
       Sixth Embodiment  
       [0097]     The sixth embodiment, which is generally similar to the second embodiment, will be described with reference to  FIG. 6 .  
         [0098]     Whereas, in the second embodiment, a configuration setting signal (C 3 ) is output from the configuration register  21  in the data communication interface  11  to the data transfer controller  32 , a configuration setting notification signal (C 24 ) and a write signal (C 26   b ) are output from the data transfer controller  32  to the setup data register  23  in the communication setup interface  12 , a configuration request signal (C 25 ) is output from the setup data register  23  to the data transfer controller  32 , and a read signal (C 26   a ) is output from the data transfer controller  32  to the configuration register  21 , in the sixth embodiment, a configuration setting signal (C 53 ) is output from the setup data register  23  to the data transfer controller  32 , a configuration setting notification signal (C 54 ) and a write signal (C 76   b ) are output from the data transfer controller  32  to the configuration register  21 , a configuration request signal (C 55 ) is output from the configuration register  21  to the data transfer controller  32 , and a read signal (C 76   a ) is output from the data transfer controller  32  to the setup data register  23 .  
         [0099]     The communication data register  22  begins communication with the digital-to-analog converter when it receives a signal C 10  from the data transfer controller  32  and a signal C 76   d  from the configuration register  21 .  
         [0100]     A description of the operation of the digital audio player will be given below, focusing on the procedure for setting the configuration data. This procedure can be divided into ten steps, numbered S 71  to S 80  below. The configuration data are denoted D 72 , D 76   c , and D 8  in  FIG. 6 , different reference characters being used in different steps in the procedure.  
         [0101]     First, in step S 71 , the CPU  5  reads data to be transmitted from the RAM  6 , and writes the data (D 1 , digital audio data, for example) in the communication data register  22  in the data communication interface  11 .  
         [0102]     Next, in step S 72 , the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 72 ) in the setup data register  23  in the communication setup interface  12 . As in the preceding embodiments, it will be assumed that the configuration data D 1  specify a serial communication speed.  
         [0103]     In step S 73 , when the data have been written in the setup data register  23  in the communication setup interface  12 , the communication setup interface  12  outputs a configuration setting signal (C 53 ) to the data transfer controller  32 .  
         [0104]     In step S 74 , the data transfer controller  32  responds to the configuration setting signal C 53  by sending the data communication interface  11  a configuration setting notification signal (C 54 ). This signal notifies the data communication interface  11  that the configuration data have been set in the setup data register  23  in the communication setup interface  12 .  
         [0105]     In step S 75 , the data communication interface  11  responds to this signal C 54  by sending a configuration request signal (C 55 ) to the data transfer controller  32 .  
         [0106]     In step S 76 , upon receiving the configuration request signal C 55  from the data communication interface  11 , the data transfer controller  32  outputs a read signal (C 76   a ) to the setup data register  23  in the communication setup interface  12  and a write signal (C 76   b ) to the configuration register  21  in the data communication interface  11 . As a result, the data transfer controller  32  reads the configuration data stored in the setup data register  23 , transfers the data (D 76   c ) to the configuration register  21  through the dedicated data bus  33 , and writes the data (D 76   c ) in the configuration register  21 .  
         [0107]     When the configuration data have been written in the configuration register  21 , a configuration setting completion signal (C 76   d ) is output to the communication data register  22 .  
         [0108]     In step S 77 , when the configuration data (D 72 ) have been written in the setup data register  23  in step S 72 , the communication setup interface  12  sends the configuration data (D 8 ) in the setup data register  23  to the digital-to-analog converter  2  by serial transmission, concurrent with the operations in steps S 73  to S 76 .  
         [0109]     In step S 78 , when the serial transmission has been completed, the communication setup interface  12  outputs a configuration setting completion signal (C 9 ) to the data transfer controller  32 .  
         [0110]     In step S 79 , upon receiving this completion signal C 9 , the data transfer controller  32  outputs a configuration setting completion signal (C 10 ) to the data communication interface  11 .  
         [0111]     In step S 80 , when the communication data register  22  has received both configuration setting completion signals C 10  and C 76   d  from the data transfer controller  32  and from the configuration register  21 , the data communication interface  11  sends the audio (or other) data (D 11 ) stored in the communication data register  22  to the digital-to-analog converter  2  by serial transmission at the communication speed set in the configuration register  21 .  
         [0112]     As described above, in the sixth embodiment, when the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 72 ) in the setup data register  23  in the communication setup interface  12 , the configuration data stored in the setup data register  23  are transferred to the configuration register  21 . When the configuration data stored in the setup data register  23  have been transferred to the configuration register  21 , and the setup data register  23  has sent the configuration data to the digital-to-analog converter  2  by serial transmission, the communication data register  22  begins the transmission of other data to the digital-to-analog converter  2 .  
       Seventh Embodiment  
       [0113]     The seventh embodiment, which is generally similar to the fourth embodiment, will be described with reference to  FIG. 7 .  
         [0114]     Whereas, in the fourth embodiment, a write signal (C 43   a ) is output from the configuration register  21  in the data communication interface  11  to control data register  44  in the output port controller  42 , in the seventh embodiment, a write signal (C 93   a ) is output from control data register  44  to the configuration register  21 .  
         [0115]     The communication data register  22  begins communication with the digital-to-analog converter when it receives a signal C 45  from the output port controller  42  and a signal C 93   d  from the configuration register  21 .  
         [0116]     A detailed description of the operation at the start of data communication will be given below, focusing on the procedure for setting configuration data in the configuration register  21  in the data communication interface  11  and in control data register  44  in the output port controller  42 . This procedure can be divided into six steps, numbered S 91  to S 96  below. The configuration data are denoted D 92 , D 93   b , D 93   c  and D 44  in  FIG. 7 , different reference characters being used in different steps in the procedure.  
         [0117]     First, in step S 91 , the CPU  5  reads data to be transmitted from the RAM  6 , and writes the data (D 1 , digital audio data, for example) in the communication data register  22  in the data communication interface  11 .  
         [0118]     Next, in step S 92 , the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 92 ) in control data register  44  in the output port controller  42 . As in the preceding embodiments, it will be assumed that the configuration data D 1  specify a serial communication speed.  
         [0119]     In step S 93 , when the data have been written in control data register  44  in the output port controller  42 , the output port controller  42  outputs a write signal (C 93   a ) to the configuration register  21  in the data communication interface  11 , and outputs the configuration data (D 93   b ) stored in control data register  44  onto the dedicated data bus  33 . The decoder  34  decodes (reformats) the configuration data on the dedicated data bus  33 , and outputs the reformatted data (D 93   c ) to the data communication interface  11 . As a result, the configuration data that the decoder  34  has reformatted are written in the configuration register  21  in the data communication interface  11 .  
         [0120]     When the configuration data have been written in the configuration register  21 , the configuration register  21  outputs a configuration setting completion signal (C 93   d ) to the communication data register  22 .  
         [0121]     In step S 94 , when the configuration data have been written in control data register  44 , the output port controller  42  begins the output of the data (D 44 ) from the output port  42   p . As a result, the digital-to-analog converter  43  operates at the communication speed set according to the control signals applied to the control input terminal  43   c.    
         [0122]     In step S 95 , the output port controller  42  outputs an output port setting completion signal (C 45 ) to the data communication interface  11  immediately after beginning the output of the control signals.  
         [0123]     In step S 96 , when the communication data register  22  has received both output port setting completion signal C 45  and configuration setting completion signal C 93   d , the data communication interface  11  sends the data (D 11 ) stored in the communication data register  22  to the digital-to-analog converter  43  by serial transmission at the communication speed specified by the configuration data set in the configuration register  21 .  
         [0124]     Although the data communication speed was mentioned as configuration data in the description above, if it is necessary to apply other configuration information as well, such as information specifying the serial data format, to a control input terminal  43   d  in the digital-to-analog converter  43 , the output port controller  42  may include another data register (control data register  46  in  FIG. 7 , for example); the CPU  5  sets the other configuration data in control data register  46 , and the output port controller  42  outputs these configuration data from an additional output port  42   q  to control input terminal  43   d.    
         [0125]     As described above, in the seventh embodiment, when the CPU  5  reads configuration data from the RAM  6 , and writes the data (D 92 ) in control data register  44  in the output port controller  42 , the configuration data stored in control data register  44  are transferred to the configuration register  21  in the data communication interface  11 . When the configuration data stored in control data register  44  have been transferred to the configuration register  21 , and the control data register  44  has begun the output of the data to the output port  42   p , the communication data register  22  begins the transmission of audio or other data to the digital-to-analog converter  43 .  
         [0126]     The digital audio player to which the invention is applied in the embodiments above is only one an example of an apparatus, having a processor and an external device, in the invention can be practiced. Another example is a digital audio recorder. In a digital audio recorder, the external device is an analog-to-digital converter from which the data communication interface  11  receives data by serial transmission. The communication data register  22  temporarily stores the received data. The analog-to-digital converter converts an analog signal received from a microphone or another source to a digital signal, which is input to the processor  1  through the data communication interface  11 , undergoes signal processing, and is then stored in the RAM  6 .  
         [0127]     Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.