Abstract:
A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates generally to the filed of non-volatile memory technology. More particularly, the present invention relates to a magnetoresistive random access memory (MRAM) element with improved magnetization efficiency, and method for fabricating the same. 
         [0003]    2. Description of the Prior Art 
         [0004]    As known in the art, magnetoresistive random access memory (MRAM) is a non-volatile computer memory technology. MRAM is six times faster than the current industry-standard memory, dynamic RAM (DRAM). It is almost as fast as static RAM (SRAM) and is much faster and suffers less degradation over time than flash memory. Unlike these technologies, MRAM uses magnetism instead of electrical charges to store data. 
         [0005]    In general, the MRAM cells include a data layer and a reference layer. The data layer is composed of a magnetic material and during a write operation the magnetization of the data layer can be switched between two opposing states by an applied magnetic field and thus binary information can be stored. The reference layer usually is composed of a magnetic material in which the magnetization is pinned so that the magnetic field, which is applied to the data layer and in part penetrates the reference layer, is of insufficient strength to switch the magnetization in the reference layer. 
         [0006]    MRAM is physically similar to DRAM in makeup, although often does not require a transistor for the write operation. However, the most basic MRAM cell suffers from the half-select problem, which limits cell sizes. To be worth putting into wide production, however, it is generally believed that MRAM will have to move to the 65 nm size of the most advanced memory devices, which will require the use of spin-torque-transfer (STT) technology. 
         [0007]    Spin-torque-transfer (STT) or Spin Transfer Switching, uses spin-aligned (“polarized”) electrons to directly torque the domains. Specifically, if the electrons flowing into a layer have to change their spin, this will develop a torque that will be transferred to the nearby layer. This lowers the amount of current needed to write the cells, making it about the same as the read process. 
         [0008]    However, the prior art MRAM has several drawbacks. For example, the gap fill process of the reference layer using physical vapor deposition (PVD) methods becomes problematic when the aspect ratio of the gap is greater than 2 for example. Besides, as the cell packing density increases, the interference between neighboring cells is not negligible. Therefore, there is a need in this industry to provide an improved method for fabricating the MRAM devices in order to avoid the aforementioned PVD gap fill problem, as well as an improved MRAM structure that is capable of eliminating interference or coupling between neighboring cells. 
       SUMMARY OF THE INVENTION 
       [0009]    To address these and other objects and in view of its purposes, the present invention provides a magnetoresistive random access memory (MRAM) element comprising a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer. 
         [0010]    According to another aspect, the invention provides a method for fabricating a MRAM element, comprising: providing a substrate; depositing a first insulating layer on the substrate; forming a bottom electrode in the first insulating layer; depositing a second insulating layer on the first insulating layer and the bottom electrode; forming a first via hole in the second insulating layer; forming an annular reference layer in the first via hole; filling the first via hole with a first gap fill material layer; depositing a barrier layer on the second insulating layer, the annular reference layer and the first gap fill material layer; depositing a third insulating layer on the barrier layer; forming a second via hole in the third insulating layer; forming an annular free layer in the second via hole; filling the second via hole with a second gap fill material layer; and forming a top electrode on the annular free layer. 
         [0011]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
           [0013]      FIGS. 1-8  are schematic, cross-sectional diagrams illustrating a method for fabricating MRAM element in accordance with one preferred embodiment of this invention; 
           [0014]      FIGS. 9-13  are schematic, cross-sectional diagrams illustrating a method for fabricating MRAM element in accordance with another preferred embodiment of this invention; and 
           [0015]      FIGS. 14-18  are schematic diagrams illustrating a method for fabricating MRAM element in accordance with still another preferred embodiment of this invention. 
       
    
    
       [0016]    It should be noted that all the Figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. 
       DETAILED DESCRIPTION 
       [0017]    In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations and process steps are not disclosed in detail. 
         [0018]    Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the figures. Also, in which multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration and description thereof, like or similar features will ordinarily be described with like reference numerals. 
         [0019]    The term “horizontal” as used herein is defined as a plane parallel to the conventional major plane or surface of the semiconductor substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane 
         [0020]      FIGS. 1-8  are schematic, cross-sectional diagrams illustrating a method for fabricating a magnetoresistive random access memory (MRAM) element in accordance with one preferred embodiment of this invention. 
         [0021]    As shown in  FIG. 1 , a substrate  100  is provided. The substrate  100  may be a semiconductor substrate including but not limited to silicon substrate, silicon substrate with an epitaxial layer, SiGe substrate, silicon-on-insulator (SOI) substrate, gallium arsenide (GaAs) substrate, gallium arsenide-phosphide (GaAsP) substrate, indium phosphide (InP) substrate, gallium aluminum arsenic (GaAlAs) substrate, or indium gallium phosphide (InGaP) substrate. A semiconductor switching device  10  such as a field effect transistor is fabricated on a main surface of the substrate  100 . 
         [0022]    An insulating layer  14  is deposited on a main surface of the substrate  100  and covers the semiconductor switching device  10 . A bottom electrode  16  is inlaid in the insulating layer  14  and is electrically connected to a terminal  12  such as a source or a drain of the semiconductor switching device  10 . The bottom electrode  16  may be composed of metals such as tungsten, titanium, titanium nitride, tantalum or tantalum nitride, copper, gold, platinum, alloys thereof, or silicides thereof. It is to be understood that in other cases the bottom electrode  16  may be electrically connected to other types of control components. An insulating layer  18  overlies the insulating layer  14  and the bottom electrode  16 . For example, the insulating layer  18  may be a silicon oxide film that can be formed by conventional chemical vapor deposition (CVD) methods. 
         [0023]    As shown in  FIG. 2 , after the deposition of the insulating layer  18 , a via etching process such as a plasma dry etching process is carried out to form a via hole  18   a  in the insulating layer  18 . Via hole  18   a  exposes a top surface of the bottom electrode  16 . According to one embodiment, via hole  18   a  has substantially vertical sidewall with respect to the main surface of the substrate  100 . Via hole  18   a  may have a circular shape, an oval shape, a rectangular shape or a polygonal shape when viewed from the top. 
         [0024]    As shown in  FIG. 3 , after the formation of via hole  18   a  in the insulating layer  18 , a magnetic material layer  20  is conformally deposited on the insulating layer  18  and on the interior surface of via hole  18   a  by physical vapor deposition (PVD) or atomic layer deposition (ALD) methods. The magnetic material layer  20  is a thin film with uniform thickness and the magnetic material layer  20  does not fill up the via hole  18   a . According to one embodiment, the magnetic material layer  20  is a pinned magnetic layer, which may be composed of a material including but not limited to NiFe, NiFeCo, CoFe, CoFeB, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials. 
         [0025]    Subsequently, as shown in  FIG. 4 , an anisotropic dry etching process is carried out to etch the magnetic material layer  20  thereby forming an annular sidewall spacer  20   a  extending vertically along the sidewall of the via hole  18   a . The magnetic material layer  20  outside the via hole  18   a  is removed to reveal the top surface of the insulating layer  18 . After the etching back of the magnetic material layer  20 , an insulating layer  21  such as silicon oxide is deposited over the substrate  100 . The insulating layer  21  fills up the remaining space in the via hole  18   a  and covers the sidewall spacer  20   a  and the top surface of the insulating layer  18 . Thereafter, a chemical mechanical polishing (CMP) is performed to remove the insulating layer  21  outside the via hole  18   a , a top portion of the sidewall spacer  20   a  and a top portion of the insulating layer  18 . The remaining sidewall spacer  20   a  acts as a reference layer of the MRAM stack. 
         [0026]    As shown in  FIG. 5 , a barrier layer  22  such as MgO or Al 2 O 3  is deposited on the insulating layer  18  and the insulating layer  21 . An insulating layer  24  such as silicon oxide is then deposited on the barrier layer  22 . After the deposition of the insulating layer  24 , a via etching process such as a plasma dry etching process is carried out to form a via hole  24   a  in the insulating layer  24 . The via hole  24   a  exposes a portion of the barrier layer  22  and is situated directly above the sidewall spacer  20   a . According to the embodiment, the via hole  24   a  has substantially vertical sidewall with respect to the main surface of the substrate  100 . The via hole  24   a  may have a circular shape, an oval shape, a rectangular shape or a polygonal shape when viewed from the top. 
         [0027]    As shown in  FIG. 6 , after the formation of the via hole  24   a  in the insulating layer  24 , a magnetic material layer  26  is conformally deposited on the insulating layer  24  and on the interior surface of the via hole  24   a  by physical vapor deposition (PVD) or atomic layer deposition (ALD) methods. The magnetic material layer  26  is a thin film with uniform thickness and the magnetic material layer  26  does not fill up the via hole  24   a . According to the embodiment, the magnetic material layer  26  has a thickness that is greater than that of the magnetic material layer  20 . According to the embodiment, the magnetic material layer  26  may be composed of a material including but not limited to NiFe, NiFeCo, CoFe, CoFeB, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials. 
         [0028]    As shown in  FIG. 7 , an anisotropic dry etching process is carried out to etch the magnetic material layer  26  thereby forming an annular sidewall spacer  26   a  extending vertically along the sidewall of the via hole  24   a . The magnetic material layer  26  outside the via hole  24   a  is removed to reveal the top surface of the insulating layer  24 . After the etching back of the magnetic material layer  26 , an insulating layer  27  such as silicon oxide is deposited over the substrate  100 . The insulating layer  27  fills up the remaining space in the via hole  24   a  and covers the sidewall spacer  26   a  and the top surface of the insulating layer  24 . Thereafter, CMP is performed to remove the insulating layer  27  outside the via hole  24   a , a top portion of the sidewall spacer  26   a  and a top portion of the insulating layer  24 . The remaining sidewall spacer  26   a  acts as a free layer (or data layer) of the MRAM stack. 
         [0029]    As shown in  FIG. 8 , after the formation of the annular free layer of the MRAM stack, a top electrode  28  is formed on the sidewall spacer  26   a . A bit line (not shown) may be electrically connected to the top electrode  28 . The top electrode  28  may be composed of metals such as tungsten, titanium, titanium nitride, tantalum or tantalum nitride, copper, gold, platinum, alloys thereof, or silicides thereof. It is to be understood that in other cases the bottom electrode  16  may be electrically connected to other types of control components. Since the reference layer  20   b  and the free layer  26   a  are both annular, the close magnetic loop provides high magnetization efficiency and the interference between neighboring cells can be avoided. 
         [0030]      FIGS. 9-13  are schematic, cross-sectional diagrams illustrating a method for fabricating MRAM element in accordance with another preferred embodiment of this invention, wherein like numeral numbers designate like elements, layers or regions. 
         [0031]    As shown in  FIG. 9 , likewise, a substrate  100  is provided. The substrate  100  may be a semiconductor substrate including but not limited to silicon substrate, silicon substrate with an epitaxial layer, SiGe substrate, silicon-on-insulator (SOI) substrate, gallium arsenide (GaAs) substrate, gallium arsenide-phosphide (GaAsP) substrate, indium phosphide (InP) substrate, gallium aluminum arsenic (GaAlAs) substrate, or indium gallium phosphide (InGaP) substrate. A semiconductor switching device  10   a  and a semiconductor switching device  10   b  such as field effect transistors are fabricated on the main surface of the substrate  100 . 
         [0032]    An insulating layer  14  is deposited on the main surface of the substrate  100  and covers the semiconductor switching devices  10   a  and  10   b . A bottom electrode  16   a  and a bottom electrode  16   b  are inlaid in the insulating layer  14  and may be electrically connected to a terminal  12   a  and a terminal  12   b  respectively of the semiconductor switching devices  10   a  and  10   b . The bottom electrodes  16   a  and  16   b  may be composed of metals such as tungsten, titanium, titanium nitride, tantalum or tantalum nitride, copper, gold, platinum, alloys thereof, or silicides thereof. It is to be understood that in other cases the bottom electrodes  16   a  and  16   b  may be electrically connected to other types of control components. An insulating layer  18  overlies the insulating layer  14  and the bottom electrodes  16   a  and  16   b . For example, the insulating layer  18  may be a silicon oxide film that can be formed by conventional chemical vapor deposition (CVD) methods. 
         [0033]    After the deposition of the insulating layer  18 , a via etching process such as a plasma dry etching process is carried out to form a via hole  18   a  in the insulating layer  18 . The via hole  18   a  exposes a top surface of the bottom electrodes  16   a  and  16   b  and a portion of the insulating layer  18  between the bottom electrodes  16   a  and  16   b . According to the embodiment, the via hole  18   a  has substantially vertical sidewall with respect to the main surface of the substrate  100 . The via hole  18   a  may have a circular shape, an oval shape, a rectangular shape or a polygonal shape when viewed from the top. 
         [0034]    After the formation of the via hole  18   a  in the insulating layer  18 , a magnetic material layer  20  is conformally deposited on the insulating layer  18  and on the interior surface of the via hole  18   a  by PVD or ALD methods. The magnetic material layer  20  is a thin film with uniform thickness and the magnetic material layer  20  does not fill up the via hole  18   a . According to the embodiment, the magnetic material layer  20  is a pinned magnetic layer, which may be composed of a material including but not limited to NiFe, NiFeCo, CoFe, CoFeB, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials. 
         [0035]    Subsequently, as shown in  FIG. 10 , an anisotropic dry etching process is carried out to etch the magnetic material layer  20  thereby forming a sidewall spacer  20   a  and a sidewall spacer  20   b  extending vertically along two opposite sidewalls of the via hole  18   a . The sidewall spacer  20   a  is situated directly above the bottom electrode  16   a  and the sidewall spacer  20   b  is situated directly above the bottom electrode  16   b . The sidewall spacer  20   a  is separated from the sidewall spacer  20   b . The magnetic material layer  20  outside the via hole  18   a  is removed to reveal the top surface of the insulating layer  18 . The sidewall spacers  20   a  and  20   b  act as a reference layer. 
         [0036]    As shown in  FIG. 11 , an insulating layer  21  such as silicon oxide is then deposited over the substrate  100 . The insulating layer  21  fills up the remaining space in the via hole  18   a  and covers the sidewall spacers  20   a ,  20   b  and the top surface of the insulating layer  18 . Thereafter, the insulating layer  21  outside the via hole  18   a , a top portion of the sidewall spacer  20   a  and a top portion of the insulating layer  18  are removed by CMP. 
         [0037]    As shown in  FIG. 12 , after CMP, a barrier layer  22  such as MgO or Al 2 O 3  is deposited on the insulating layer  18  and the insulating layer  21 . 
         [0038]    As shown in  FIG. 13 , an insulating layer  24  such as silicon oxide is then deposited on the barrier layer  22 . A free layer  26   a  and a free layer  26   b  are inlaid in the insulating layer  24 . The free layer  26   a  is situated directly above the sidewall spacer  20   a  and the free layer  26   b  is situated directly above the sidewall spacer  20   b . For example, a magnetic material layer is first deposited on the barrier layer  22  in a blanket manner. The magnetic material layer is then patterned to form the free layers  26   a  and  26   b . Thereafter, the insulating layer  24  is deposited to cover the free layers  26   a  and  26   b  and the barrier layer  22 . The excess insulating layer  24  may be removed by CMP. The thin sidewall spacers  20   a  and  20   b  that act as a reference layer provide high magnetization efficiency. 
         [0039]      FIGS. 14-18  are schematic diagrams illustrating a method for fabricating MRAM element in accordance with still another preferred embodiment of this invention, wherein like numeral numbers designate like elements, layers or regions. 
         [0040]    As shown in  FIG. 14 , likewise, an insulating layer  14  is provided on a substrate (not shown). A bottom electrode  16   a  and a bottom electrode  16   b  are inlaid in the insulating layer  14 . The bottom electrodes  16   a  and  16   b  may be composed of metals such as tungsten, titanium, titanium nitride, tantalum or tantalum nitride, copper, gold, platinum, alloys thereof, or silicides thereof. An insulating layer  18  overlies the insulating layer  14  and the bottom electrodes  16   a  and  16   b . For example, the insulating layer  18  may be a silicon oxide film that can be formed by conventional CVD methods. After the deposition of the insulating layer  18 , a via etching process is carried out to form a via hole  18   a  in the insulating layer  18 . The via hole  18   a  exposes a top surface of the bottom electrodes  16   a  and  16   b  and a portion of the insulating layer  18  between the bottom electrodes  16   a  and  16   b . According to the embodiment, the via hole  18   a  has substantially vertical sidewall with respect to the main surface of the substrate. 
         [0041]    A magnetic material layer  20  is conformally deposited on the insulating layer  18  and on the interior surface of the via hole  18   a  by PVD or ALD methods. The magnetic material layer  20  is a thin film with uniform thickness and the magnetic material layer  20  does not fill up the via hole  18   a . According to the embodiment, the magnetic material layer  20  is a pinned magnetic layer, which may be composed of a material including but not limited to NiFe, NiFeCo, CoFe, CoFeB, Fe, Co, Ni, alloys or compounds thereof, and/or other magnetic materials. 
         [0042]    As shown in  FIG. 15 , an anisotropic dry etching process is then carried out to etch the magnetic material layer  20  thereby forming a sidewall spacer  20   a  and a sidewall spacer  20   b  extending vertically along two opposite sidewalls of the via hole  18   a . The sidewall spacer  20   a  is situated directly above the bottom electrode  16   a  and the sidewall spacer  20   b  is situated directly above the bottom electrode  16   b . The sidewall spacer  20   a  is separated from the sidewall spacer  20   b . The magnetic material layer  20  outside the via hole  18   a  is removed to reveal the top surface of the insulating layer  18 . Subsequently, a patterned sacrificial layer  32  such as silicon oxide, silicon nitride or photoresist is formed on the insulating layer  18  and the patterned sacrificial layer  32  covers a portion of the sidewall spacers  20   a  and  20   b.    
         [0043]    As shown in  FIG. 16 , a wet etching process is then carried out to etch the sidewall spacers  20   a  and  20   b  that are not covered with the patterned sacrificial layer  32 . Thereafter, a portion of the sidewall spacer  20   a  under the patterned sacrificial layer  32  and a portion of the sidewall spacer  20   b  under the patterned sacrificial layer  32  are etched away to form a pillar  120   a  and a pillar  120   b  respectively on the bottom electrodes  16   a  and  16   b . The pillar  120   a  and a pillar  120   b  act as a reference layer. 
         [0044]    As shown in the  FIG. 17 , after the formation of the pillars  120   a  and  120   b , the patterned sacrificial layer  32  is removed to reveal the pillars  120   a  and  120   b . Removal of the patterned sacrificial layer  32  may be implemented by methods known in the art, for example, wet etching, dry etching or plasma ashing. 
         [0045]    As shown in  FIG. 18 , an insulating layer  21  such as silicon oxide is then deposited. The insulating layer  21  fills up the remaining space in the via hole  18   a  and covers the pillars  120   a  and  120   b  and the top surface of the insulating layer  18 . Thereafter, at least the insulating layer  21  outside the via hole  18   a  is removed by CMP. A barrier layer  22  such as MgO or Al 2 O 3  is then deposited on the insulating layer  18  and the insulating layer  21 . An insulating layer  24  such as silicon oxide is then deposited on the barrier layer  22 . A free layer  26   a  and a free layer  26   b  are inlaid in the insulating layer  24 . The free layer  26   a  is situated directly above the sidewall spacer  20   a  and the free layer  26   b  is situated directly above the sidewall spacer  20   b . For example, a magnetic material layer is first deposited on the barrier layer  22  in a blanket manner. The magnetic material layer is then patterned to form the free layers  26   a  and  26   b . Thereafter, the insulating layer  24  is deposited to cover the free layers  26   a  and  26   b  and the barrier layer  22 . The excess insulating layer  24  may be removed by CMP. Top electrodes  28   a  and  28   b  are then formed on the free layers  26   a  and  26   b  respectively. The pillars  120   a  and  120   b  that act as the reference layer provide high polarization efficiency and magnetization efficiency. 
         [0046]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.