Abstract:
An oscillator system is provided to have a plurality of delay paths coupled in a loop. The oscillator system also has an improved AC feedforward path coupled in parallel with one or more delay paths in the loop. The AC feedforward path includes first and second parallel sections. The first parallel section has a plurality of parallel branches and is configured for receiving one or more control signals. The plurality of parallel branches is selectively conducted in response to the one or more control signals. The second parallel section is coupled in series with the first parallel section and is configured to remain conducting when any of the plurality of parallel branches becomes conducting. The first and second parallel sections are configured to transmit an AC feedforward signal when conducting.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates generally to phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) used in the PLLs, and more particularly, to a balanced interleaved feedforward VCO (BIFFVCO). 
     2. Description of the Related Art 
     High-frequency voltage-controlled oscillators (VCOs) are extremely important for applications such as processor clock generation and/or distribution, wired and/or wireless communication, system synchronization, and frequency synthesis. Research on VCos for the past decade has been concentrated in the areas of high frequency, lower jitter, lower operating voltage and power, and increasing the frequency tuning range. Many of these design goals are achieved only at the expense of some or all of the other performance objectives. As technology progresses toward shorter channel lengths and lower operating voltages, the headroom available for an analog design decreases to the point that cascading (stacking) is no longer feasible. High-frequency analog VCOs operating with properly biased current sources may have signal swings that are only a small fraction of the supply voltage, severely limiting their usefulness. 
     Current-starved ring-oscillators using 3 or 4 levels of stacking have become quite common, but they have extreme sensitivity to noise due to very high gain, are inherently nonlinear (especially near cutoff, where they often stop oscillating), are inherently limited to 2X max frequency range and are difficult to build in less than 4 levels. Multiphase oscillators offer advantages by pipelining operations using equally spaced phases at lower frequencies, but control mechanisms in delay interpolators introduce offsets from the ideal spacing. LC-based oscillators are capable of high frequency and extremely low jitter but are difficult to integrate and model and have tuning ranges of only a few percent. 
     Therefore, there is a need for a VCO that creates a frequency dither that is symmetric about a DC operating point and that interfaces directly to a common phase-frequency detector, resulting in more optimal PLL performance. 
     SUMMARY OF THE INVENTION 
     The present invention provides an oscillator system, which has a plurality of delay paths coupled in a loop. The oscillator system also has an AC feedforward path coupled in parallel with one or more delay paths in the loop. The AC feedforward path includes first and second parallel sections. The first parallel section has a plurality of parallel branches and is configured for receiving one or more control signals. The plurality of parallel branches is selectively conducted in response to the one or more control signals. 
     The second parallel section is coupled in series with the first parallel section and is configured to remain conducting when any of the plurality of parallel branches becomes conducting. The first and second parallel sections are configured to transmit an AC feedforward signal when conducting. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which: 
     FIG. 1 is a block diagram of a prior-art phase-locked loop; 
     FIG. 2 is a block diagram of a prior-art phase-locked loop in which a balanced interleaved feedforward voltage-controlled oscillator (BIFFVCO); 
     FIG. 3 is a block diagram of a prior-art five-stage oscillator; 
     FIG. 4 is a schematic diagram of a prior-art delay stage in accordance with the oscillator type described in FIG. 3; and 
     FIG. 5 is a schematic diagram of an AC path element used in the delay stage of FIG.  4 . 
    
    
     DETAILED DESCRIPTION 
     In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. 
     Referring to FIG. 1 of the drawings, the reference numeral  100  generally designates a block diagram incorporating a phase-locked loop (PLL)  102 . The PLL  102  is coupled to a reference clock generator  104  to receive a reference clock signal  106  having frequency F_REF and is configured to generate a PLL output signal  108  having frequency F_CLK. Generally, the PLL  102  uses a feedback loop  110  to lock a feedback signal  112  to the reference clock signal  106 . 
     Specifically, the feedback loop  110  includes a phase-frequency detector  114 , a charge pump  116 , a loop filter  118 , an interleaved voltage-controlled oscillator (IVCO)  120 , and optionally a frequency divider  122 . 
     In the PLL  102 , the phase-frequency detector  114  compares the reference clock signal  106  and the feedback signal  112  and generates an error signal  124 , which is proportional to the magnitude of the phase/frequency difference between the reference clock signal  106  and the feedback signal  112 . The error signal  124  is fed to the charge pump  116 . The charge pump  116  controls the magnitude of charge stored in the loop filter  118  using current, thereby converting the error signal  124  into a control voltage input V c    126 , which is recognizable by the IVCO  120 . For example, the loop filter  118  contains a series RC combination. The series RC combination produces a second order system. The IVCO  120  generates the PLL output signal  108 . Typically, the frequency F_CLK of the PLL output signal  108  is proportional to the control voltage input  126 . 
     Optionally, the frequency divider  122  further divides down the frequency F_CLK of the PLL output signal  108  before the PLL output signal  108  is fed back to the phase-frequency detector  122 . Provided that the frequency divider  122  is used in the PLL  102 , the frequency of the PLL output signal  108  is higher than that of the feedback signal  112  by a factor of the frequency divider  122 . For example, if the frequency divider  122  with a factor of N is used, the frequency of the PLL output signal  108  is approximately N times that of the feedback signal  112 . Therefore, F_CLK=N*F_REF, wherein N is a positive integer. This is because the PLL  102  locks the frequency of the feedback signal  112  to the frequency F_REF of the reference clock signal  106  in the feedback loop  110 . 
     Now referring to FIG. 2, a block diagram  200  includes an interleaved feedforward PLL (IFFPLL)  202 . The IFFPLL  200  includes the same components as those in the PLL  100  of FIG. 1, except for a loop filter  204 , an interleaved feedforward VCO (IFFVCO)  206 , and one or more control signals  208 . 
     The loop filter  204  has only capacitance C. The IFFVCO  206  has a feedforward input port FF for receiving the one or more control signals  208  from the phase-frequency detector  114 . Preferably, the one or more control signals  208  include UP and DN signals (not shown) to increase and decrease the output frequency of the IFFPLL  202 . 
     FIG. 3 shows a block diagram of a five-stage interleaved feedforward VCO (IFFVCO)  300 . The five-stage IFFVCO  300  is an example of the IFFVCO  206  of FIG.  2 . The five-stage IFFVCO  300  comprises five delay elements (DEs)  302 ,  304 ,  306 ,  308 , and  310  connected in a ring, with signal output  312  being fed back into input  314  of the DE  302  through a feedback connection  316 . 
     Each DE contains a feedforward path (not shown) and a delay path (not shown), as explained below in reference to FIG.  4 . Each feedforward path is coupled to an A input port of a different DE through a feedforward connection. Specifically, a feedforward connection  318  couples an output port C of the DE  302  to an input port A of the DE  308 . Similarly, a feedforward connection  320  couples an output port C of the DE  304  to an input port A of the DE  310 . Likewise, a feedforward connection  322  couples an output port C of the DE  306  to an input port A of the DE  312 . Other feedforward connections  324  and  326  are configured in a similar fashion as clearly shown in FIG.  3 . 
     Note that, although each DE in FIG. 3 contains both a delay path and a feedforward path, these paths do not have to reside in the same unit such as a DE. 
     FIG. 4 shows a schematic diagram of a delay element  400  in accordance with the oscillator type described in FIG.  3 . 
     The delay element  400  comprises an AC path  402 , a DC path  404 , and a delay path  405 . For example, the components on the AC path  402  may be selected to exhibit low capacitance for high-frequency operation and need low driver impedance, while the components on the DC path  404  are less critical since the large capacitor on Vc integrates the parasitic currents for low sensitivity to parasitic noise currents and large capacitance, which aids in setting the DC operating point and which aids in integrating or smoothing the effect of noise currents. 
     The DC path  404  comprises an inverter  408  and a gate  410 . The gate  410  can be either a transmission gate or a pass gate. Preferably, one or more Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs or MOSs) such as  410 ,  412 , and  414  are used either alone or in combination to function as an inverter, transmission gate, or pass gate. Typically, a transmission gate comprises a single PMOS or NMOS transistor, whereas a pass gate comprises a complementary device including a pair of PMOS and NMOS transistors. Note that a gate in the present description can be either a transmission gate or a pass gate. Similarly, the delay path  405  comprises an inverter similar to the inverter  408 . 
     The AC path  402  and DC path  404  together forms a feedforward path, which is coupled via a feedforward connection to another delay element in a ring oscillator such as the IFFVCO  300  as shown in FIG.  3 . 
     Now referring to FIG. 5, the AC path  402  of the delay stage  400  of FIG. 4 is shown. The AC path  402  largely comprises a first branch  502 , second branch  504 , third branch  506 , fourth branch  508 , and fifth branch  510 . The first, second, and third branches  502 ,  504 , and  506  are parallel branches coupled in series with the parallel combination of fourth branch  508  and fifth branch  510  to connect node A and C. The first branch  502  includes gate Q 1  controlled by an UP signal. The second branch  504  includes gates Q 2  and Q 3  respectively controlled by Vdd (bias voltage) and a DNB signal. The third branch  506  includes gate Q 4  controlled by Vdd. The fourth branch  508  includes gate Q 7 , which is controlled by Vdd. Finally, the fifth branch  510  includes gates Q 5  and Q 6  respectively controlled by FF_boost 2  and FF_boost 1  signals. As mentioned above, gates Q 1 -Q 7  each can be either a transmission gate or a pass gate. 
     Since gates Q 4  and Q 7  are always conducting, signals UP and DNB determine how many branch(es) in addition to the third branch  506  will be activated. 
     Signals UP and DNB are supplied by a phase-frequency detector, which supplies a pulse of width proportional to the phase error. Signal UP is asserted to increase frequency, whereas signal DN is asserted to decrease frequency. DNB is an inversion of DN. For PLL configurations that require a larger feedforward current, signals FF_BOOST 1  and FF_BOOST 2  may be individually or together asserted to increase the effective gain of the AC path  402  since the fifth branch  510  containing gates Q 5  and Q 6  is in parallel with the fourth branch  508 . Signals FF_boost 1  and FF_boost 2  are configured at power-on to provide the feedforward gain that is appropriate for the PLL application. The AC impedance of signals UP, DN, FF_boost 1 , FF_boost 2 , and Vdd are designed to be small so that the parasitic elements have little effect on operating frequency. The PFD has  3  possible states: (1) UP asserted, (2) DN asserted, and (3) neither UP nor DN asserted. 
     Ignoring the FF_boost signals for the sake of simplicity, when UP is asserted, gates Q 1 , Q 2 , Q 3 , Q 4 , and Q 7  are conducting. This activates all three branches, namely, the first, second, and third branches  502 ,  504 , and  506  for maximum gain through the AC path  402 . When signal DN is asserted, only gates Q 4  and Q 7  will conduct, providing the minimum gain through the AC path  402  by activating only one branch, namely, the third branch  506 . When neither UP nor DN is asserted, gates Q 2 , Q 3 , Q 4 , and Q 7  are conducting. In this case, two branches, namely, the second branch  504  and the third branch  506  are activated, and the gain should be at a level centered between the minimum and maximum levels. Gate Q 2  is cascaded with gate Q 3  to help attenuate the second branch  504  to maintain balance. For a Silicon On Insulator (SOI) process, gates Q 1 , Q 3 , and Q 4  are body-contacted to reduce the history effect as well as attenuate the signal, while the remaining gates are arranged to be insensitive to history effects. 
     It will be understood from the foregoing description that various modifications and changes may be made in the preferred embodiment of the present invention without departing from its true spirit. This description is intended for purposes of illustration only and should not be construed in a limiting sense. The scope of this invention should be limited only by the language of the following claims.