Abstract:
A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. A method for measuring temperature of a device using a comparator and converting the bitstream of the comparator to a digital output is also given. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application is a continuation of pending U.S. patent application Ser. No. 12/220,577, filed Jul. 25, 2008, which is a divisional of U.S. patent application Ser. No. 11/063,173, filed Feb. 22, 2005, and issued as U.S. Pat. No. 7,413,342. This application and patent are incorporated herein by reference, in their entirety, for any purpose. 
     
    
     BACKGROUND 
       [0002]    The present invention relates generally to a temperature measurement system for use in integrated circuits and more particularly to a temperature measurement system based on current mode sigma-delta modulation for use within dynamic random access memory (DRAM) devices. 
         [0003]    Temperature sensors are used within integrated circuits, for example, to protect against overcurrent damage, to compensate for cross sensitivity of other sensors, to reduce errors caused by self-heating, and to provide process data input, among others. Increasingly, complimentary-metal-oxide-semiconductor (CMOS) devices are used as temperature sensors due to the ease of incorporating these devices into the integrated circuit. 
         [0004]      FIG. 7  illustrates a temperature measurement system according to the prior art. The temperature measurement system includes a temperature sensor  100 , a bandgap voltage reference circuit  102 , a sigma-delta converter  104 , a counter  106 , and a controller  108 , among others. The temperature measurement system is used to convert an analog temperature reading, as produced by temperature sensor  100 , into a digital output. 
         [0005]    The forward voltage of a diode decreases linearly with temperature. Utilizing this characteristic, methods and circuits to derive temperature and reference signals from CMOS devices have been developed and are well known. Thus, a detailed discussion of such methods and circuits is omitted herein. Temperature sensor  100  may be a CMOS device comprised of p-channel and/or n-channel transistors. As seen in  FIG. 7 , temperature sensor  100  produces a temperature dependent current (I TEMP ) that is provided to sigma-delta converter  104 . 
         [0006]    Reference circuit  102  is comprised of precision analog components and produces a reference current (I REF ) and a reference voltage (V REF ). The reference current (I REF ) and the reference voltage (V REF ) may also be referred to as the bandgap reference current (I BGref ) and bandgap reference voltage (V BGref ), respectively. Both I REF  and V REF  are temperature independent. Although capable of producing a temperature independent current and a temperature independent voltage, the precision analog components used by reference circuit  102  are costly and require band-gap type tuning. As seen in  FIG. 7 , I REF  and V REF  are provided to sigma-delta converter  104 . 
         [0007]    Sigma-delta converter  104  uses I TEMP , I REF , and V REF  to produce a bitstream that is provided to counter  106 . Counter  106  uses the bitstream to produce a digital output representing the temperature sensed by temperature sensor  100 . Controller  108  controls the overall operation of the temperature measurement system. For example, controller  108  issues “power on”, “reset”, and “enable” signals (among others) to the other components of the temperature measurement system. 
         [0008]      FIG. 8  illustrates a simplified circuit diagram of the prior art sigma-delta converter  104  of  FIG. 7 . Sigma-delta converter  104  includes switches  120 ,  122 , a capacitor  124 , an op-amp  126 , a comparator  128 , and a flip-flop register  130 . In operation, Switch  120  is responsive to a feedback loop from the output of flip-flop register  130 . I TEMP  (e.g., from temperature sensor  100  as shown in  FIG. 7 ) is added to I REF  when switch  120  is closed. The combined signal is then fed to an integrator which, as shown in  FIG. 8 , is formed by the combination of op-amp  126 , capacitor  124 , and switch  122 . Switch  122  is responsive to a reset signal. If switch  122  is in its open state (and switch  120  is in its closed state), I TEMP  and I REF  cause a voltage to develop across capacitor  124 . This voltage also develops at the output of op-amp  126 , which is fed to the non-inverting input of comparator  126 . The output of the op-amp  126  is compared to a reference signal (e.g., ground) by comparator  128  and the output of the comparator  128  is fed to an input of flip-flop register  130 . The output of the flip-flop register  130  carries a bitstream which, as discussed above, is fed back to switch  120  and also fed to a counter (not shown in  FIG. 8 ). The counter (e.g., counter  106  as shown in  FIG. 7 ) tracks the number of “1” decisions made by comparator  128  in a predetermined time period and produces the digital output representing the temperature sensed by the temperature sensor  100 . 
         [0009]    The prior art temperature measurement system&#39;s resolution, power consumption, and need for band-gap type tuning, however, are not adequate for certain integrated circuit applications. Additionally, the sigma-delta converter&#39;s  104  use of I REF  and V REF  fails to insure adequate operation at low voltages (e.g., 1.2 V and below). With respect to resolution, for example, the output of comparator  122  is fed to counter  106  as discussed above. The counter  106  is activated for predetermined time period (e.g., 100 cycles of a self-generated clock signal). After this predetermined time period expires, the counter&#39;s  106  output is read and the sensing operation is completed. For a typical prior art temperature measurement system operated at a temperature range between approximately −40° C. and 110° C., the counter  106  range is approximately 15 for every 100 times a sample of the comparator output is taken. 
         [0010]    Accordingly, a need exists for a temperature measurement system which overcomes these problems and which overcomes other limitations inherent in prior art. 
       SUMMARY 
       [0011]    One aspect of the invention relates to a converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output, and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto. 
         [0012]    Another aspect of the invention relates to a temperature measurement system comprising a temperature sensor, a converter operable to receive one or more signals from the temperature sensor, and a counter, the converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a switch for sinking a portion of the first signal, wherein the switch is responsive to the output and an integrator connected to the first input, wherein the first signal is a voltage developed by the integrator when a current proportional to the absolute temperature is applied thereto, wherein the counter is responsive to the output for producing an output signal. 
         [0013]    Another aspect of the invention relates to a memory system comprising a memory module, a memory controller in communication with the memory module via a system bus, and a temperature measurement module. The temperature measurement module comprises a temperature sensor, a converter operable to receive one or more signals from the temperature sensor, and a counter responsive to the output for producing an output signal, wherein the converter comprises a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, and a switch for sinking a portion of said first signal, wherein said switch is responsive to said output, and an integrator connected to said first input, wherein said first signal is a voltage developed by said integrator when a current proportional to the absolute temperature is applied thereto. 
         [0014]    Another aspect of the invention relates to a method for measuring temperature comprising comparing a first signal, proportional to a sensed absolute temperature, to a reference signal, and generating a bitstream in response to said comparison. The reference signal may be inversely proportional to the absolute temperature. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    To enable the present invention to be easily understood and readily practiced, the present invention will now be described for purposes of illustration and not limitation, in connection with the following figures wherein: 
           [0016]      FIG. 1  is a simplified diagram of a temperature measurement module according to one embodiment. 
           [0017]      FIGS. 1A and 1B  are simplified diagrams of circuits for producing I PTAT  and I CTAT , respectively, according to one embodiment. 
           [0018]      FIG. 2  is a simplified diagram of a temperature measurement module according to another embodiment. 
           [0019]      FIG. 3  is a simplified diagram of a portion of the temperature measurement module of  FIG. 1  and/or  FIG. 2  according to one embodiment. 
           [0020]      FIG. 4A  is a simplified diagram illustrating the relationship between I PTAT  and temperature according to one embodiment. 
           [0021]      FIG. 4B  is a simplified diagram illustrating the relationship between I CTAT  and temperature according to one embodiment. 
           [0022]      FIG. 4C  is a simplified diagram illustrating the relationship between V CTAT  and temperature according to one embodiment. 
           [0023]      FIG. 5  is a simplified block diagram of a memory system according to one embodiment. 
           [0024]      FIG. 6  illustrates a simplified functional block diagram of an architecture for a memory device of  FIG. 1  according to one embodiment. 
           [0025]      FIG. 7  illustrates a temperature measurement system according to the prior art. 
           [0026]      FIG. 8  illustrates a simplified circuit diagram of the sigma-delta converter of  FIG. 7  according to the prior art. 
       
    
    
     DETAILED DESCRIPTION 
       [0027]    The detailed description sets forth specific embodiments that are described in sufficient detail to enable those skilled in the art to practice the present invention. It should be apparent to those skilled in the art that other embodiments may be utilized, and that logical, mechanical, and electrical changes may be made, while remaining within the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims. 
         [0028]      FIG. 1  is a simplified diagram of a temperature measurement module  4  according to one embodiment. The temperature measurement module  4  includes a CMOS temperature sensor  42 , a sigma-delta converter  44 , a counter  46 , and a controller  48 , among others. The temperature measurement module  4  converts an analog temperature reading (i.e., from the temperature sensor  42 ) into a digital output. 
         [0029]    In the current embodiment, the temperature sensor  42  includes a vertical bipolar transistor. It should be apparent to one skilled in the art, however, that other types of devices might be used (for example, a CMOS transistor operating in weak inversion, a lateral bipolar transistor, Schottky diodes, etc.) while remaining within the scope of the present invention. Temperature sensor  42  produces a current proportional to absolute temperature (I PTAT ), a current complementary to absolute temperature (I CTAT ), and a voltage complementary to absolute temperature (V CTAT ), each of which are provided to converter  44 . 
         [0030]      FIGS. 1A and 1B  are simplified diagrams of circuits for producing I PTAT  and I CTAT , respectively, according to one embodiment. Referring briefly to  FIG. 1A , current generator  60  includes an op amp  62 , PMOS transistors  64   a ,  64   b ,  64   c , resistor  66 , and diodes  68   a ,  68   b . In the current embodiment, diodes  68   a ,  68   b  are vertical p-n-p diodes. The non-inverting input of op-amp  62  is connected to a node located between PMOS transistor  64   b  and resistor  66  such that the voltage produced across resistor  66  is applied to the non-inverting input. The inverting input of op-amp  62  is connected to a node between PMOS transistor  64   a  and diode  68   a  such that the voltage (V diode ) produced across diode  68   a  is applied to the inverting input. The output of op amp  62  is applied to the gates of PMOS transistors  64   a ,  64   b ,  64   c . In the current embodiment, PMOS transistors  64   a ,  64   b ,  64   c  act as current sources. The output of PMOS transistor  64   c  is I PTAT . For clarity, the transistors  64   a ,  64   b ,  64   c  illustrated in  FIG. 1A  are single PMOS transistors, however, it should be apparent to one skilled in the art that other types of transistors may be used while remaining within the scope of the present invention. For example, cascaded PMOS transistors may be used for PMOS transistors  64   a ,  64   b ,  64   c  while remaining within the scope of the present invention. 
         [0031]    Referring briefly to  FIG. 1B , current generator  70  includes an op amp  72 , PMOS transistors  74   a ,  74   b , and resistor  76 . The non-inverting input of op-amp  62  is connected to a node located between PMOS transistor  74   a  and resistor  76  such that the voltage produced across resistor  76  is applied to the non-inverting input. The inverting input of op-amp  62  is connected to the voltage (V diode ) that is produced as discussed above. The output of op amp  72  is applied to the gates of PMOS transistors  74   a ,  74   b . In the current embodiment, PMOS transistors  74   a ,  74   b  act as current sources. The output of PMOS transistor  64   b  is I CTAT . For clarity, the transistors  74   a ,  74   b  illustrated in  FIG. 1A  are single PMOS transistors, however, it should be apparent to one skilled in the art that other types of transistors may be used while remaining within the scope of the present invention. For example, cascaded PMOS transistors may be used for PMOS transistors  74   a ,  74   b  for better power supply rejection and other performance parameters while remaining within the scope of the present invention. 
         [0032]    Returning to  FIG. 1 , converter  44  uses I PTAT , I CTAT , and V CTAT , to produce a bitstream that is provided to counter  46 . Counter  46  uses the bitstream output to produce a digital output representing the temperature reading. Controller  48  regulates the temperature sensor  42 , converter  44 , and counter  46  in the current embodiment. For example, controller  48  issues “clock” and “enable” signals (among others) to the temperature sensor  42 , converter  44 , and counter  46 . 
         [0033]    The temperature measurement module  4  illustrated in  FIG. 1  employs a single temperature sensor. In an alternative embodiment, the temperature measurement module  4  may employ a plurality of temperature sensors while remaining within the scope of the present invention.  FIG. 2  illustrates a temperature measurement module  4  having a plurality of temperature sensors  42  according to one embodiment. As seen in  FIG. 2 , each temperature sensor  42  is connected to a multiplexer  43 . In the current embodiment, controller  48  issues a “select” command to the multiplexer  43  such that multiplexer  43  passes the output from the selected temperature sensor  42  to the converter  44 . Once the particular temperature sensor  42  is selected, the temperature measurement module  4  shown in  FIG. 2  functions the same way as the temperature measurement module  4  shown in  FIG. 1 . It should be noted that the criteria used to select a particular temperature sensor  42  may vary according to certain design choices. For example, depending upon their locations within an integrated circuit, a first temperature sensor  42  may be selected twice as often as a second temperature sensor  42 . 
         [0034]      FIG. 3  is a simplified diagram of a portion of the temperature measurement module  4  of  FIG. 1  and/or  FIG. 2  according to one embodiment. More specifically,  FIG. 3  illustrates a more detailed view of the sigma-delta converter  44  in combination with the counter  46 . The converter  44  includes a capacitor  56 , a clocked comparator  52 , and a transistor  54 . The capacitor  56  acts as a signal integrator. It should be apparent to one skilled in the art that other types of integrators may be used while remaining within the scope of the present invention. Additionally, as previously discussed, a “clocked comparator” refers to a comparator that compares two inputs and asserts the output signal once every clock cycle (e.g., a comparator whose output changes only once per clock cycle). 
         [0035]    In operation, I PTAT  from temperature sensor  42  (as shown in  FIG. 1 ) or from the selected temperature sensor  42  (as shown in  FIG. 2 ) causes a voltage (“sigma”) to develop across capacitor  56  at node A. This voltage, which may also be referred to as V CAP , is provided to the non-inverting input of comparator  52 . When V CAP  exceeds V CTAT , the comparator output (i.e., the bitstream) goes high causing transistor  54  to conduct. When activated, transistor  54  sinks I CTAT  (i.e., “delta”), thus discharging capacitor  56  and causing V CAP  to decrease. When V CAP  falls below V CTAT , the comparator output goes low, thus de-activating transistor  54 . As seen in  FIG. 3 , the comparator output is also connected to an input of counter  46 . Counter  46  counts the number of “1” decisions made by the comparator  52  and produces a digital output representing the temperature as sensed by the temperature sensor  42  (i.e., counter  46  counts the number of times the comparator output goes high within a predetermined time period, such as 100 clock cycles). 
         [0036]      FIG. 4A  is a simplified diagram illustrating the relationship between I PTAT  and temperature for the temperature measurement module  4  according to one embodiment. As seen in  FIG. 4A , I PTAT  is directly proportional to temperature (i.e., as temperature increases, I PTAT  increases).  FIGS. 4B and 4C  are simplified diagrams illustrating the relationship between I CTAT  and temperature and between V CTAT  and temperature, respectively, for the temperature measurement module  4  according to one embodiment. As seen in  FIGS. 4B and 4C , I CTAT  and V CTAT  are inversely proportional to temperature (i.e., as temperature increases, I CTAT  and V CTAT  each decrease). 
         [0037]    The use of I CTAT  (i.e., as the delta current source) in combination with a reference voltage enables increased resolution for the temperature measurement module  4 . Additionally, using a capacitor as an integrator instead of an op-amp based integrator removes complexities associated with designing low voltage op-amps. In the current embodiment, for example, using I CTAT  (i.e., as the delta current source) and V CTAT  (i.e., as the reference in the comparator) in contrast to I REF  and V REF , respectively, increases the effective resolution of the temperature measurement module  4  without using precision analog components as required by the prior art. With increasing temperature, I PTAT  increases while I CTAT  decreases. This improves the resolution of the temperature sensor  42 . For example, when the comparator  52  is sampled 100 times, the counter range goes from about 15 when using I REF  and V REF  (as discussed above in conjunction with the prior art temperature measurement system) to approximately 55 when using I CTAT  and V CTAT  (e.g., for a temperature range between approximately −40° C. and 110° C.). It should be noted that another reference voltage may be used as the reference for the comparator while remaining within the scope of the present invention. It should further be noted that the reference voltage need not have the same properties as V CTAT  (e.g., as temperature increases, the reference voltage need not decrease) to remain within the scope of the present invention. 
         [0038]    Additionally, the use of I CTAT  and V CTAT  ensures adequate operation at lower voltages (e.g., 1.2 V and below) and eliminates the precision band-gap type tuning required to generate a fixed V REF  by the prior art circuits. 
         [0039]      FIG. 5  is a simplified block diagram of a memory system  1  according to one embodiment. The memory system  1  includes a memory controller  2 , two (2) dual-inline-memory-modules  3  (i.e., DIMM- 0 , DIMM- 1 ), and one or more temperature measurement modules  4  (as illustrated in  FIG. 1  and/or  FIG. 2 ). Each memory module  3  is divided into two (2) ranks (Rank- 0 , Rank- 1 ), each rank being comprised of nine (9) synchronous dynamic random access memory (SDRAM) devices  10 . The memory system  1  may be utilized as a component within a larger system, for example, within a computer system having a processor, a storage device, a display, etc. 
         [0040]    The memory controller  2  and memory modules  3  communicate via a system bus  5 . In the current embodiment, the system bus  5  carries command signals, address signals, and data signals, among others. The system bus  5  may be sub-divided into two or more buses, for example a command bus, an address bus, and a data bus. The command bus may carry the row address strobe (RAS#), column address strobe (CAS#), and write enable (WE#) command signals, among others. The address bus may carry bank address (BA 0 , BA 1 ) and address input (A 0 -A 12 ) signals, among others. The data bus may carry data input/output signals (DQ 0 -DQ 15 ), data strobe signals (LDQS, LDQS#, UDQS, UDQS#), and data mask signals (LDM, UDM), among others. Additionally, rank specific command signals, such as the chip select (CS#), clock enable (CKE), and on-die termination (ODT) signals may be carried by another portion of the system bus  5 . It should be apparent to one skilled in the art that the topology of the system bus  5  (and its component parts) may be varied while remaining within the scope of the present invention. 
         [0041]    The temperature measurement modules  4  may be distributed throughout the memory system  1 . For example as shown in  FIG. 5 , temperature memory modules  4  are shown located within the memory controller  2 , within each rank of each memory module  3 , and within the unused die space of the memory system  1 . Temperature memory modules  4  may also be incorporated into one or more of the SDRAMs  10  (not shown in  FIG. 5 ). Accordingly, the temperature memory modules  4  may be employed to protect the memory system  1  and/or its components against overcurrent damage, to compensate for cross sensitivity of other sensors, to reduce errors caused by self-heating, and to provide process data input, among others. For example, the output of one or more of the temperature measurement modules  4  may be used by the memory controller  2  and/or a microprocessor (not shown) to regulate power supplied to the memory device  1  and to prevent overheating, among others. 
         [0042]    It should be apparent to one skilled in the art the number of temperature measurement modules  4  employed and/or their location(s) within the memory system  1  may be varied while remaining within the scope of the present invention. Additionally, it should be apparent to one skilled in the art that a single temperature measurement module  4  having a plurality of temperature sensors (for example, as best illustrated in  FIG. 2 ) may be employed while remaining within the scope of the present invention. 
         [0043]    It should further be apparent to one skilled in the art that the use of the temperature measurement module  4  within a memory device is for exemplary purposes only and is not intended, in any manner, to limit the scope of the present invention. The temperature measurement module  4  may be used with other types of devices may be used while remaining within the scope of the present invention. 
         [0044]      FIG. 6  illustrates a simplified functional block diagram of an architecture for an SDRAM  10  of  FIG. 5  according to one embodiment. The SDRAM  10  may include a temperature measurement module  4  for measuring the temperature within the SDRAM  10 . The SDRAM  10  includes control logic  11  responsive to a plurality of command signals (e.g., CS#, RAS#, CAS#, WE#, CKE, CK, CK#, ADR, BA, etc.) from a command bus  12 . The control logic  11  includes a command decode circuit  13  and mode register circuits  14 , among others. Table 1 illustrates a truth table for the command coding of the SDRAM  10  according to the one embodiment. 
         [0000]                                                                TABLE 1                   SDRAM Coding Truth Table (L 0, active; H = 1, inactive).                CKE                    Previous   Current                       FUNCTION   Cycle   Cycle   CS#   RAS#   CAS#   WE#               Write   H   H   L   H   L   L       Read   H   H   L   H   L   H       Bank Activate   H   H   L   L   H   H       Load Mode   H   H   L   L   L   L       Refresh   H   H   L   L   L   H       Self-Refresh   H   L   L   L   L   H       Entry       Self-Refresh   L   H   H   X   X   X       Exit           L   H   H   H       Precharge   H   H   L   L   H   L       No Operation   H   X   L   H   H   H                    
Referring to Table 1 for example, when the memory controller  2  sets CS#=L, RAS#=H, CAS#=L and WE#=L, the command decode circuit  13  decodes the signals as a write command function. It should be apparent to those skilled in the art that different and/or additional signals (e.g., BA, ADR, etc.) may be used to encode each command function. It should further be apparent to one skilled in the art that the specific state of each command signal (i.e., CS#, RAS#, etc.) used to define each command function (i.e., write, read, etc.) may be altered while remaining within the scope of the present invention.
 
         [0045]    The SDRAM  10  also includes an address register  15  responsive to an address bus  16  that carries a plurality of address signals (e.g., A 0 -A 12 , BA 0 , BA 1 , etc.). The control  9  logic  11  and the address register  15  communicate with each other, and with a row address multiplexer circuit  17 , a bank control logic circuit  18 , and a column address counter/latch circuit  19 , via an internal bus  20 . 
         [0046]    The bank control logic  18  is responsive to the control logic  11 , the address register  15 , and a refresh counter  38 . The row address multiplexer  17  is also responsive to the control logic  11 , the address register  15 , and the refresh counter  38 . A series of row latch/decoders  21  are responsive to the bank control logic  18  and the row address multiplexer  17 . One row latch/decoder  21  is provided for each memory array  22 . Each memory array  22  is comprised of a plurality of memory cells each operable to store one bit of information. Four memory arrays  22 , labeled bank  0  through bank  3 , are illustrated in  FIG. 6 . Accordingly, there are four row latch/decoder circuits  21 , one each for controlling bank  0  through bank  3 . 
         [0047]    The column address counter/latch circuit  19  is responsive to the control logic  11  and the address register  15 . A series of column decoders  23  are responsive to the bank control logic  18  and the column address counter/latch  19 . One column decoder  23  is provided for each memory array  22 . As discussed above, SDRAM  10  includes four memory arrays  22  labeled bank  0  through bank  3 . Accordingly, there are four column decoder circuits  23 , one each for controlling bank  0  through bank  3 . An I/O gating circuit  24  is responsive to the column decoder circuits  23  for controlling sense amplifiers  40  within each of the memory arrays  22 . 
         [0048]    The SDRAM  10  may be accessed through a plurality of data pads  25  for either a write operation or a read operation. For a write operation, data on data pads  25  is received by receivers  26  and passed to input registers  27 . A write buffer/driver circuit  28  buffers the received data which is then input to the memory arrays  22  through the I/O gating circuit  24 . 
         [0049]    Data that is to be read from the memory arrays  22  is output through the I/O gating circuit  24  to a read latch  29 . From the read latch  29 , the information is input to a multiplexer circuit  30 , which outputs the data onto the data pads  25  through drivers  31 . The drivers  31  are responsive to a data strobe generator  32  and to a delay locked loop circuit  33 . The data strobe generator  32  is operable to produce data strobes for upper and lower bytes (i.e., UDQS, UDQS#, LDQS, and LDQS#) as is known in the art. The data strobes are also provided to data strobe output pads  34 , input registers  27 , and to the write buffer/driver  28 , among others. The SDRAM  10  also includes input data mask pads  35  for receiving upper data mask signals (UDM) and lower data mask signals (LDM) for the upper bytes (DQ 8 -DQ 15 ) and lower bytes (DQ 0 -DQ 7 ), respectively. The data pads  25 , data strobe output pads  34 , and data mask pads  35  may be part of a data bus  37 . 
         [0050]    The SDRAM  10  includes an on-die termination (ODT) circuit  36  that is operable to apply an effective resistance Rtt (e.g., RI or R 2 ) to the data pads  25 , data strobe output pads  34 , and input data mask pads  35  (or to another portion of the data bus). An ODT activation circuit  39  is used to control whether the ODT circuit  36  is enabled/disabled, and thus whether Rtt is applied. In the embodiment illustrated in  FIG. 6 , the ODT activation circuit  39  receives the WE# and CS# signals which are sent by the system controller  2  to the DIMMs  3  and to each SDRAM  10 . These signals may be rank specific (e.g., WEO# and CS# 0  for rank- 0 , WE# 1  and CS# 1  for rank- 1 , etc.). 
         [0051]    It should be apparent to one skilled in the art that the position of the temperature measurement module  4  within the SDRAM  10  (as illustrated in  FIG. 6 ) may be altered while remaining within the scope of the present invention. The positioning may be dependent upon the purpose to be served by the temperature measurement module  4  (e.g., to protect against overcurrent damage, to compensate for cross sensitivity of other sensors, to reduce errors caused by self-heating, to provide process data input, etc.). It should further be apparent to one skilled in the art that the use of SDRAM  10  is for exemplary purposes only and that other types of memory devices may be used while remaining within the scope of the present invention. 
         [0052]    It should be apparent to those of ordinary skill in the art that equivalent logic or physical circuits may be constructed using alternate logic elements while remaining within the scope of the present invention. It should further be recognized that the above-described embodiments of the invention are intended to be illustrative only. Those skilled in the art may devise numerous alternative embodiments without departing from the scope of the following claims.