Abstract:
In a neutral-point-clamped power inverter, gate drive circuit comprises four drive blocks providing bipolar DC signals to control switch gates. The first and third drive blocks are bootstrapped to the second and fourth. Inverter&#39;s neutral bus is commonly connected to the positive and negative DC buses through clamping capacitors. An arm of four serially-stacked-switches bridges DC buses. The switch arm midpoint is an output of the inverter. A first clamping diode connects the neutral bus to the first switch emitter; a second clamping diode connects the neutral bus to the third switch emitter. In one embodiment, a second switch arm mirrors the first, providing a second output; a second gate drive circuit mirrors the first. A bias circuit provides two reference voltages for the gate drive circuits. Three isolated DC sources provide signals that, when used by the gate drive circuit, result in seven isolated bipolar DC signals.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. provisional patent application No. 61/333,967 filed May 12, 2010, which is hereby incorporated by reference in its entirety. 
     
    
     BACKGROUND 
       [0002]    Full bridge NPC inverters are commonly used in applications such as, for example, motor drives to develop AC waveforms from DC power supplies. The full bridge NPC inverter includes 8 switches which demand seven different gate drive potentials. There is a need in the art to efficiently and inexpensively provide the multiple gate drive potentials required for the NPC inverter. 
       SUMMARY 
       [0003]    Described herein are full bridge neutral-point-clamped power inverters and bootstrapped gate drive circuits thereto. 
         [0004]    In one embodiment described herein, a full bridge neutral-point-clamped power inverter is provided comprising a DC bus structure, a switching structure, three isolated bipolar DC power sources, and a gate drive network to selectively activate or deactivate the switches. The DC bus structure comprises a positive DC bus supplying a first DC supply voltage, a negative DC bus supplying a second DC supply voltage, and a neutral bus that substantially maintains a DC voltage that is approximately midway between the first and second DC supply voltages and that is connected to the positive DC bus by capacitors C 1  and C 3  and to the negative DC bus by capacitors C 2  and C 4 . The switching structure comprises a first set of series-connected voltage-controlled switches S 1 -S 4 , where  51  is connected to the positive DC bus and to S 2 , S 4  is connected to the negative DC bus and to S 3 , and S 2  and S 3  are connected to the neutral bus. The switching structure also comprises a second set of series-connected voltage-controlled switches S 5 -S 8 , where S 5  is connected to the positive DC bus and to S 6 , S 8  is connected to the negative DC bus and to S 7 , and S 6  and S 7  are connected to the neutral bus. The output of the inverter is the center point of each set of series connected switches. Clamping diodes D 1 -D 4  are each connected to the neutral bus, where diode D 1  is also connected to emitter E 1  of switch S 1 , diode D 2  is also connected to emitter E 3  of switch S 3 , diode D 3  is also connected to emitter E 5  of switch S 5 , and diode D 4  is also connected to emitter E 7  of switch S 7 . 
         [0005]    The first, second, and third isolated power sources each provide a bipolar DC signal that is referenced to the emitters of switches S 2  and S 6 , and to negative DC bus, respectively. The gate drive network comprises a bias circuit that is connected across the DC bus from the positive to the negative bus signals that utilizes two zener diodes, filter capacitors, and current-limiting resistors to regulate voltage and provide two reference voltages to generate bootstrapped gate drive signals. 
         [0006]    A first gate drive block for providing a gate signal to switch S 1  has a first gate drive circuit and two capacitors connected to the emitter of switch S 1 , where the first capacitor is also connected to the gate drive circuit and indirectly to the first isolated DC power source through a first bootstrap diode, and where the second capacitor is also connected to the gate circuit and indirectly to the first reference voltage of the bias circuit. A second gate drive block for providing a gate signal to switch S 2  has a second gate drive circuit and two capacitors connected to the emitter of switch S 2 , where the first and second capacitors are also connected to the gate drive circuit and to the first isolated bipolar DC power source. A third gate drive block for providing a gate signal to switch S 3  has a first gate third gate drive circuit and two capacitors connected to the emitter of switch S 3 , where the first capacitor is also connected to the gate drive circuit and indirectly to the third isolated DC power source through a third bootstrap diode, and where the second capacitor is also connected to the gate circuit and indirectly to the second reference voltage of the bias circuit. A fourth gate drive block for providing a gate signal to switch S 4  has a fourth gate drive circuit and two capacitors connected to the emitter of switch S 4 , where the first and second capacitors are also connected to the gate drive circuit and to the third isolated DC power source. 
         [0007]    Finally, the gate drive network also has fifth, sixth, seventh, and eight drive blocks having the same topology as the first-fourth drive blocks, and each drive block selectively provides a bipolar DC input signal to a switch to activate or deactivate the gates of the switch in response to a control signal. 
         [0008]    Also described herein is a neutral-point-clamped power inverter having a positive DC bus, a negative DC bus, and a neutral bus commonly connected to the positive and negative DC buses through first and second clamping capacitors, and having a set of four serially-stacked switches between the positive and negative DC buses, where the midpoint of the set of switches is an output of the inverter and where the neutral bus is additionally connected between a pair of clamping diodes, where the first clamping diode is connected to emitter of the first switch and the second clamping diode is connected to the emitter of the third switch. The inverter has a gate drive circuit comprising a first, second, third, and fourth drive blocks. 
         [0009]    The first drive block has a first gate drive circuit and two capacitors connected to the emitter of the first switch. The first capacitor is also connected to the first drive circuit and indirectly to a positive signal of a first isolated DC source through a first bootstrap diode. The second capacitor is also connected to the first gate drive circuit and indirectly to a first reference signal through a second bootstrap diode. The second drive block has a second gate drive circuit and first and second capacitors connected to emitter of the second switch. The first capacitor is also connected to the second gate drive circuit and to the positive signal of the first isolated DC source, and the second capacitor is also connected to the second gate drive circuit and to a negative signal of the first isolated DC source. 
         [0010]    The third gate drive block has a third gate drive circuit and two capacitors connected to the emitter of the third switch. The first capacitor is also connected to the third gate drive circuit and indirectly to a positive signal of a second isolated DC source through third a bootstrap diode, and the second capacitor is also connected to the third gate drive circuit and indirectly to a second reference signal through a fourth bootstrap diode. The fourth gate drive block has a fourth gate drive circuit and two capacitors connected to the emitter of the fourth switch. The first capacitor is also connected to the fourth gate drive circuit and to the positive signal of the second isolated DC source. The second capacitor is also connected to the fourth gate drive circuit and to a negative signal of the second isolated DC source. 
         [0011]    Finally, the gate drive blocks provide bipolar DC gate input signals to the gates of the switches, thereby activating them or deactivating them in response to a control signal. The first and second reference signals are provided by a gate drive bias network. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0012]      FIG. 1  is a circuit diagram of a neutral point clamped full bridge inverter. 
           [0013]      FIG. 2  is a circuit diagram of an isolated DC/DC power supply. 
           [0014]      FIG. 3  is a circuit diagram of a gate drive bias network. 
           [0015]      FIG. 4  is a circuit diagram of a gate drive configuration for supplying gate voltages G 1 -G 4 . 
           [0016]      FIG. 5  is a circuit diagram of a gate drive configuration for supplying gate voltages G 5 -G 8 . 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    With reference now to  FIG. 1 , a neutral-point-clamped full bridge inverter is shown. The inverter may be used, for example, in solar applications as a solar power inverter. The inverter output is the center-point of each series connection of four switches (S 1 , S 2 , S 3 , S 4 ; and S 5 , S 6 , S 7 , S 8 ), represented in  FIG. 1  as voltage source AC. In one embodiment, the output of series S 1 , S 2 , S 3 , S 4  is 180° out of phase from the output of series S 5 , S 6 , S 7 , S 8 . It should be appreciated that the switches S 1 -S 8  are voltage controlled devices such as, for example, IGBTs or MOSFETs, and that each switch S 1 -S 8  has an emitter terminal E 1 -E 8 . For the sake of clarity, the terms “emitter” and “source” are used interchangeably herein, and denote analogous components of IGBTs and MOSFETs. 
         [0018]    With continued reference to  FIG. 1 , the DC bus UDC is connected to the top and bottom row switches S 1 , S 5  and S 4 , S 8  respectively. A mid-point/neutral point of the DC bus is connected to UDC+ and UDC− by a pair of capacitors C 1 /C 3  and C 2 /C 4  respectively. The mid-point is also connected between a pair of diodes D 1  and D 2 . Diode D 1  is connected to emitter E 1  of switch S 1  and diode D 2  is connected to emitter E 3  of switch S 3 . Likewise diode D 3  is connected to emitter E 5  of switch S 5  and diode D 4  is connected to emitter E 7  of switch S 7 . These four diodes (D 1 -D 4 ) are connected to the neutral bus and act to control the voltage distribution among the four switches in each series. 
         [0019]    In general, a switch (e.g., IGBT or MOSFET) requires a gate input signal to turn on (i.e. close), and the gate input signal must be referenced between the switch gate and emitter terminal. Thus, when a suitable gate signal is applied to a switch, it closes (i.e. conducts). With continued reference to  FIG. 1 , each switch S 1 - 58  is actuated by a gate input signal G 1 -G 8 , respectively. 
         [0020]    Referring to the left half-bridge of  FIG. 1 , if switches S 1  and S 2  are turned on, the output is connected to the positive bus UDC+. When switches S 3  and S 4  are turned on, the output is connected to the negative bus UDC−. When switches S 2  and S 3  are turned on, the output is connected to the neutral or mid-point bus UDC_M. By controlling the switches, waveforms are generated. 
         [0021]    With reference now to  FIG. 2 , a DC/DC converter  10  is shown which, as will be described below in greater detail, provides isolated and regulated voltages used for the gate input signals of the NPC inverter. Input power is provided by a DC supply voltage. Switch S 9  is modulated alternately on and off to produce a voltage waveform on the primary of transformer T 1 . A control circuit controls switch S 9  and includes a pulse width modulator. Energy is transferred by magnetic coupling to individual secondaries, which include diodes D 5 -D 11  to convert the AC waveforms to DC and capacitors C 5 -C 11  to store energy on the DC secondary circuits. 
         [0022]    As can be seen, a first power supply  12   a  outputs a first bi-polar isolated supply voltage (VL 1 _P and VL 1 _N) that is referenced to ground GND_L 1 . A second power supply  12   b  outputs a second bi-polar isolated supply voltage (VL 2 _P and VL 2 _N) that is referenced to ground GND_L 2 . A third power supply  12   c  outputs a third bi-polar supply voltage (VC_C and VC_E) that is referenced to negative DC bus UDC−. In one non-limiting embodiment, the VL 1 _P, VL 2 _P and VC_C are +15V and VL 1 _N, VL 2 _N and VC_E are −5V. Each of the voltage supplies are galvanically isolated from each other through the magnetic coupling for transformer T 1 . The third supply also outputs an additional voltage VC_ 2  that has the same reference as VC_C but a lower magnitude. 
         [0023]    As previously mentioned, gate input signals G 1 -G 8  must be referenced between the respective switch gate and emitter terminal. Referring to  FIG. 1  (NPC bridge) and  FIG. 2  (power supply), it may be appreciated that G 4  and G 8  are referenced to UDC−, G 2  is referenced to GND_L 1 , and G 6  is referenced to GND_L 2 . Conversely, G 1 , G 3 , G 5 , and G 7  are referenced to E 1 , E 3 , E 5 , and E 7 , which “float”: for example, when S 1  is ON, the E 1  signal is connected to UDC+; when S 1  is OFF and S 2  is ON, E 1  is connected to GND_ 1  potential. This illustrates the need for isolation. 
         [0024]    With reference now to  FIG. 3 , a gate drive bias network is shown. The bias network provides a balancing function for the capacitors C 1 -C 4  (e.g., there is no need for resistors to relieve any leakage current), a means to discharge the capacitor bank C 1 -C 4 , and a means to generate a pair of reference voltages Vref 1  and Vref 2 . As can be seen, a zener diode D 12  and a plurality of resistors R 10 -R 12  are connected in series between UDC+ and UDC_M. Likewise, a zener diode D 13  and a plurality of resistors R 20 -R 22  are connected in series between UDC_M and UDC−. The resistors R 10 -R 12  and R 20 -R 22  set up the proper bias current in the zener diodes D 12  and D 13  respectively, so that they properly regulate the voltage. Zener diodes D 12  and D 13  may be rated nominally, for example, from about 5-10 volts. Capacitor C 12  is connected across diode D 12  and capacitor C 13  is connected across diode D 13 . Capacitors C 12  and C 13  function as electrolytic filter capacitors, and provide energy storage at the same voltage as the respective diode. 
         [0025]    A reference voltage output Vref 1  is connected to C 12  and D 12  through a current limiting resistor R 1 . Likewise, a reference voltage output Vref 2  is connected to C 13  and D 13  through a current limiting resistor R 2 . As will be described below, the reference voltages Vref 1  and Vref 2  are used to generate gate drive signals. 
         [0026]    The gate drive bias network provides the voltage reference Vref 1  and Vref 2  to the bootstrap gate drives U 1  and U 3  (described below). Assuming diode D 12  regulates a voltage Vz, when measuring voltage from UDC−, the voltage at Vref 1  will be (UDC+)−Vz. Likewise, the voltage at Vref 2  will be (UDC_M)−Vz. 
         [0027]    With reference now to  FIG. 4 , the gate drive diagram is shown. Each gate drive circuit U 1 -U 4  receives control signals from a controller (not shown) and applies the appropriate gate input signal G 1 -G 4  to the associated gate of each switch S 1 -S 4 . Thus, each gate drive circuit is responsible for turning on and off a single switch. According to the present invention, when a control signal is sent to each gate drive block, the gate drive produces a bipolar output signal that the connected switch uses to either turn on or off. Because each switch S 1 -S 4  is at a different potential (due to the topology shown in  FIG. 1 ), each gate drive U 1 -U 4  must be isolated to avoid cross-conduction, which is accomplished by the secondary windings of the power supply and/or the boot-strap topology, as described below. 
         [0028]    As can be seen, the circuit shown in  FIG. 4  includes four boot-strap diodes D 14 -D 17  which allow the charge transfer between upper (floating) and lower gate drives (U 1 , U 3 , U 5 , U 7 ; and U 2 , U 4 , U 6 , U 8 , respectively) while preserving voltage isolation. Likewise, capacitors C 14 -C 21  function as energy storage capacitors for the gate drives. As shown in  FIG. 4 , the emitter E 1  of switch S 1  is connected between capacitors C 14  and C 15 . C 14  is connected to U 1  and also to VL 1 _P through diode D 14 . C 15  is connected to U 1  and also to Vref 1  through diode D 15 . The emitter E 2  (i.e. GND _L 1  of  FIG. 1 ) of switch S 2  is connected between capacitors C 16  and C 17 . C 16  is connected to U 2  and also directly connected to VL 1 _P. C 17  is connected to U 2  and VL 1 _N. The emitter E 3  of switch S 3  is connected between capacitors C 18  and C 19 . C 18  is connected to U 3  and also to VC_C through diode D 16 . C 19  is connected to U 3  and also to Vref 2  through diode D 17 . The emitter E 4  (i.e. connected to UDC− of  FIG. 1 ) of switch S 4  is connected between capacitors C 20  and C 21 . C 20  is connected to U 4  and also directly connected to VC_C. C 21  is connected to U 4  and VC_E. 
         [0029]    From  FIG. 4 , it may be seen that capacitors C 14  and C 15  are referenced to E 1  and capacitors C 18  and C 19  are referenced to E 3 —e.g., reflecting that gate drives U 1  and U 3  supply voltages for S 1  and S 3  that are floating. Diodes D 14 -D 17  are called bootstrap diodes and allow capacitors C 14  and C 18  to be charged when S 2  or S 4  are ON. When S 1  or S 3  are ON, the diodes D 14  and D 16  are reversed biased and do not allow current to flow but D 15  and D 17  are forward biased and allow C 15  and C 19  to be charged. 
         [0030]    As shown above, the power supply of  FIG. 2  produces three isolated bipolar supply voltages VL 1 _P/VL 1 _N, VL 2 _P/VL 2 _N and VC_C/VC_E. These supplies are galvanically isolated from each other through magnetic coupling of the transformer T 1 . As can be seen in  FIG. 4 , the first supply VL 1 _P/VL 1 _N powers the gate drive U 2  directly and U 1  through the bootstrap diode D 14 . Likewise, third supply VC_C/VC_E powers the gate drive U 4  directly and U 3  through the bootstrap diode D 16 . Thus, it may be appreciated that supply voltages for S 2 , S 4  are isolated by the secondary windings of the power supply, whereas supply voltages for S 1 , S 3  are isolated by the bootstrap topology previously described. 
         [0031]    With reference to  FIG. 5 , the topology for gate drives U 5 -U 8  (for controlling gates G 5 -G 8 ) is shown. As can be seen, the topology is substantially similar to gate drives U 1 -U 4 . 
         [0032]    An illustrative example of the charging of a gate drive is discussed below. If U 4  outputs a signal G 4  to close S 4 , the connection E 3  will go to the E 4  potential (i.e. UDC−). In so doing, C 18  will be charged by current flowing out of power supply VC_C, through diode D 16  and into C 18 . Because U 3  is commanded OFF by the controller (not shown), no charge is taken from C 18  and the voltage remains across C 18 . If S 4  is commanded OFF by the controller and instead S 2  and S 3  are commanded ON, the connection E 3  will be at UDC_M potential. Thus, capacitor C 19  will be charged by current flowing from capacitor C 13 , through D 1 , through S 2  and S 3 , through C 19 , through D 17  and back to Vref 2  potential. U 1  is charged in the same manner except that it uses Vref 1  circuitry. 
         [0033]    One of ordinary skill in the art will appreciate that prior to the inverter doing any useful work (i.e. modulating), all of the bootstrap capacitors should be charged. 
         [0034]    While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. It is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.