Abstract:
A phase detector includes a first control unit and a second control unit to generate a first control pulse and a second control pulse representative of a phase difference between a reference signal and a first clock signal. The first control unit receives the reference signal and the first clock signal and generates the first control pulse. The first control pulse has a first pulse width that varies depending on the phase difference between the reference signal and the first clock signal. The second control unit receives the reference signal and a second clock signal and generates the second control pulse such that the second control pulse substantially overlaps the first control pulse and has a second pulse width that is a preset value. The second clock signal has a frequency higher than that of the first clock signal.

Description:
[0001]     This application claims the benefit of the filing date of Taiwan Application Ser. No. 092125138, filed on Sep. 12, 2003, the content of which is incorporated herein by reference.  
       BACKGROUND  
       [0002]     The invention relates to a phase detector, a phase detection method and a PLL (Phase-Locked Loop) using the phase detector, and more particularly a phase detector using a high-frequency clock as a trigger signal to make the control signals UP and DN overlap with each other, and a PLL using the phase detector in order to reduce the jitter.  
         [0003]      FIG. 1  shows a block diagram of a conventional PLL. The PLL is for providing a recovery clock that is phase synchronized with the input signal (IN). For example, when the data of an optical disk medium is read, the PLL is utilized to lock the phase and frequency of the EFM (Eight-to-Fourteen Modulation) signal and to output a phase locked clock (PLCK) as a sampling clock for the EFM signal or a reference clock for other controls. Referring to  FIG. 1 , the conventional PLL  10  includes a phase detector  11 , a charge pump  12 , a loop filter  13 , a VCO (Voltage Control Oscillator)  14 , and optionally a frequency divider  15 .  
         [0004]     The phase detector  11  is used to detect a phase error between an input signal IN and a phase locked clock PLCK 2 , and output control pulses UP and DN to control the charge pump  12  according to the phase error. For example, when the phase of the phase locked clock PLCK 2  leads that of the input signal IN, the width of the control pulse UP outputted from the phase detector  11  is smaller than that of the control pulse DN so that the charge pump  12  generates a negative control current Icp. At this time, the loop filter  13  reduces the control voltage Vct 1  according to the negative control current Icp and thus lowers the frequency of the phase locked clock PLCK 1  outputted from the VCO  14 . On the contrary, when the phase of the phase locked clock PLCK 2  lags behind that of the input signal IN, the width of the control pulse UP outputted from the phase detector  11  is larger than that of the control pulse DN so that the charge pump  12  generates a positive control current Icp. The loop filter  13  increases the control voltage Vct 1  according to the positive control current Icp, and thus increases the frequency of the phase locked clock PLCK 1  outputted from the VCO  14 .  
         [0005]      FIG. 2  shows a conventional circuit of a phase detector, a charge pump, and a loop filter of the PLL. Referring to  FIG. 2 , the phase detector  11  includes three flip-flops  111 ,  112  and  113 , and two XOR (Exclusive OR) gates  114  and  115 . The flip-flop  111  uses the input signal IN as its input signal and outputs its output signal to the input terminal of the flip-flop  112 . The output signal of the flip-flop  112  is outputted to the input terminal of the flip-flop  113 . The flip-flops  111 ,  112  and  113  use the phase locked clock PLCK 2  as the trigger signal, wherein the flip-flop  111  is of the negative-edge trigger type and the flip-flops  112  and  113  are of the positive-edge trigger type. The XOR gate  114  receives the input signal IN and the output signal of the flip-flop  112 , and generates the control pulse UP. The XOR gate  115  receives the output signals of the flip-flops  112  and  113  and generates the control pulse DN. The charge pump  12  includes two current sources IUP and IDN, and two switches S 1  and S 2 . The control pulses UP and DN respectively control the switches S 1  and S 2  so as to generate the control current Icp. The loop filter  13  includes two capacitors C 1  and C 2  and a resistor R 1 . The loop filter  13  receives the control current Icp and then generates the control voltage Vct 1 .  
         [0006]      FIG. 3  shows waveforms of some signals of the circuit in  FIG. 2 , including the input signal IN, the oscillation clock PLCK 2 , the control pulses UP and DN, and the control voltage Vct 1  when the PLL is at the phase locked state. As shown in  FIG. 3 , because the control pulses UP and DN are not overlapped, the control voltage Vct 1  is still changed periodically and transiently even though the PLL has reached the phase locked state. Thus, the oscillation clock outputted from the VCO  14  has jitters.  
       SUMMARY  
       [0007]     In view of the above-mentioned problems, an object of the invention is to provide a phase detector using a high-frequency clock as a trigger signal to make the control signals UP and DN overlap with each other, and a PLL using the phase detector in order to reduce the jitter.  
         [0008]     To achieve the above-mentioned object, the phase detector of the invention includes a first control unit and a second control unit to generate a first control pulse and a second control pulse representative of a phase difference between a reference signal and an oscillation clock. The first control unit receives the reference signal and the oscillation clock and generates the first control pulse. The first control pulse has a first pulse width that varies depending on the phase difference between the reference signal and the oscillation clock. The second control unit receives the reference signal and the high-frequency clock and generates the second control pulse such that the second control pulse substantially overlaps the first control pulse and has a second pulse width that is a preset value. The high-frequency clock has a frequency higher than that of the oscillation clock. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  shows a block diagram of a conventional PLL.  
         [0010]      FIG. 2  shows conventional circuits of a phase detector, a charge pump, and a loop filter of the PLL.  
         [0011]      FIG. 3  shows waveforms of some signals of the circuit in  FIG. 2 , including an input signal IN, an oscillation clock PLCK 2 , control pulses UP and DN, and a control voltage Vct 1  when the PLL is at the phase locked state.  
         [0012]      FIG. 4  shows a phase detector according to a first embodiment of the invention.  
         [0013]      FIG. 5  shows exemplar waveforms of some signals of the circuit in  FIG. 4  when the input signal and the oscillation clock have the same phase, including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulse UP, the control pulse DN, and the control voltage Vct 1 .  
         [0014]      FIG. 6  shows exemplar waveforms of some signals of the circuit in  FIG. 4  when the phase of the input signal leads that of the oscillation clock, including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulse UP, the control pulse DN, and the control voltage Vct 1 .  
         [0015]      FIG. 7  shows exemplar waveforms of some signals of the circuit in  FIG. 4  when the phase of the input signal lags behind that of the oscillation clock, including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulse UP, the control pulse DN, and the control voltage Vct 1 .  
         [0016]      FIG. 8  shows a phase detector according to a second embodiment of the invention.  
         [0017]      FIG. 9  shows waveforms of some signals of the circuit in  FIG. 8  when the input signal and the oscillation clock have the same phase, including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulse UP, the control pulse DN, and the control voltage Vct 1 .  
         [0018]      FIG. 10  shows the PLL using the phase detector of the invention. 
     
    
     DETAILED DESCRIPTION  
       [0019]     The phase detector and PLL using the phase detector of the invention will be described with reference to the accompanying drawings.  
         [0020]      FIG. 4  shows a phase detector according to a first embodiment of the invention. Referring to  FIG. 4 , the phase detector  40  of the invention includes a first control unit  41  and a second control unit  42 . The first control unit  41  receives an input signal IN, is clocked by an oscillation clock PLCK 2  and generates a control pulse UP. The control pulse UP is enabled when the level change of the input signal IN is sensed by the first control unit  41 , and normally will be disabled at the positive edge next to the upcoming negative edge of the oscillation clock PLCK 2 . The second control unit  42  receives the input signal IN, is clocked by a high-frequency clock CLK_HF and generates a control pulse DN. The control pulse DN is enabled when the level change of the input signal IN is sensed by the second control unit  42 , and will be disabled after a period of first delay time. The time points that the control pulse DN is enabled/disabled are aligned at the edges of the high-frequency clock CLK_HF such that the first delay time can be easily implemented. The first delay time is typically one period of the oscillation clock PLCK 2  in this embodiment. Let the ratio of the frequency of the high-frequency clock CLK_HF to the frequency of the oscillation clock PLCK 2  be denoted by M. Either M or 2*M is preferably an integer such that the delay time could be designed easily. For example, if the frequency of the high-frequency clock CLK_HF is eight times that of the oscillation clock PLCK 2 , the first delay time may be set to eight cycles of the high-frequency clock CLK_HF.  
         [0021]     The first control unit  41  includes flip-flops  411  and  412  and an XOR gate  413 . The flip-flop  411  uses the input signal IN as its input signal and the oscillation clock PLCK 2  as its trigger signal. The flip-flop  411  is of a negative-edge trigger type in this embodiment, and the output signal is coupled to the input terminal of the flip-flop  412 . The flip-flop  412  uses the oscillation clock PLCK 2  as the trigger signal and is of a positive-edge trigger type in this embodiment. The XOR gate  413  receives the input signal IN and the output signal of the flip-flop  412  and generates the control pulse UP. Suppose the output signals of the XOR gate  413 , the flip-flop  411 , and the flip-flop  412  are initially at low level. According to the circuit of the first control unit  41 , once the input signal IN is changed from the low level to the high level, the XOR gate  413  will outputs the high level simultaneously to enable the control pulse UP. Next, when the oscillation clock PLCK 2  is changed from the high level to the low level, the flip-flop  411  outputs the high level. Thereafter, when the oscillation clock PLCK 2  is changed from the low level to the high level, the flip-flop  412  outputs the high level. At this time, because the two input terminals of the XOR gate  413  are both at the high level, the XOR gate  413  outputs the low level to disable the control pulse UP. After a period of time, when the input signal IN is further changed from the high level to the low level, the XOR gate  413  outputs the high level again to enable the control pulse UP because the output of the flip-flop  412  is the high level. Next, when the oscillation clock PLCK 2  is changed from the high level to the low level, the flip-flop  411  outputs the low level. Thereafter, when the oscillation clock PLCK 2  is changed from the low level to the high level, the flip-flop  412  outputs the low level. At this time, because the two input terminals of the XOR gate  413  are both at the low level, the XOR gate  413  outputs the low level to disable the control pulse UP.  
         [0022]     The second control unit  42  includes a flip-flop  421 , a delay unit  422 , and an XOR gate  423 . The flip-flop  421  uses the input signal IN as its input signal and the high-frequency clock CLK_HF as its trigger signal. The flip-flop  421  is of a negative-edge trigger type in this embodiment and the output signal is coupled to the input terminal of the delay unit  422 . The delay unit  422  includes a plurality of flip-flops  422   l  to  422   n  for delaying the output signal of the flip-flop  421  by a period of the first delay time. The XOR gate  423  receives the output signals of the flip-flop  421  and the delay unit  422 , and generates the control pulse DN whose pulse width will equal to the first delay time. Suppose the output signals of the XOR gate  423 , the flip-flops  421  and  422   n  are initially at low level. According to the circuit of the second control unit  42 , after the input signal IN is changed form the low level to the high level and when the high-frequency clock CLK_HF is changed from the high level to the low level, the flip-flop  421  outputs the high level. At this time, the XOR gate  423  outputs the high level simultaneously to enable the control pulse DN. Thereafter, the delay unit  422  outputs the high level after the first delay time has elapsed. At this time, because the two input terminals of the XOR gate  423  are both at the high level, the XOR gate  423  outputs the low level to disable the control pulse DN. After a period of time, when the input signal IN is changed from the high level to the low level and when the high-frequency clock CLK_HF is changed from the high level to the low level, the flip-flop  421  outputs the low level. At this time, the XOR gate  423  outputs the high level to enable the control pulse DN. Thereafter, the delay unit  422  outputs the low level after the first delay time has elapsed. At this time, because the two input terminals of the XOR gate  423  are both at the low level, the XOR gate  423  outputs the low level to disable the control pulse DN.  
         [0023]      FIG. 5  shows waveforms of some signals of the circuit in  FIG. 4  when the input signal IN and the oscillation clock PLCK 2  have the same phase, including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulses UP and DN, and the control voltage Vct 1 . The frequency of the high-frequency clock CLK_HF shown in  FIG. 5  is eight times that of the oscillation clock PLCK 2 , so the first delay time may be set to 8 cycles of the high-frequency clock CLK_HF. That is, the enable time of each control pulse DN equals one cycle of the oscillation clock PLCK 2 . For the example shown in the drawing, because the control pulses UP and DN have the same enable time and most of the time (7.5 cycles of the high-frequency clock CLK_HF cycle) is overlapped, the variation amount of the control voltage Vct 1  is much smaller than that of the PLL using the conventional phase detector. In addition, because the input signal and the oscillation clock have the same phase, the control voltage Vct 1  is always kept unchanged.  
         [0024]      FIG. 6  shows waveforms of some signals of the circuit in  FIG. 4  when the phase of the input signal IN leads that of the oscillation clock PLCK 2 , including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulses UP and DN, and the control voltage Vct 1 . For the example shown in the drawing, because the enable time of the control pulse UP is longer than that of the control pulse DN and is overlapped with that of the control pulse DN, the control voltage Vct 1  increases in a slowly manner. As can be seen in this example, the phase detector according to the present invention could be free from the jitter which would be greatly induced in the conventional phase detector owing to the control voltage Vct 1  is increasing greatly and then decreasing greatly. Because the phase of the input signal leads that of the oscillation clock, the control voltage Vct 1  increases to thereby increase the frequency of the oscillation clock PLCK 2  and thus shift the phase of the oscillation clock PLCK 2  forward accordingly.  
         [0025]      FIG. 7  shows waveforms of some signals of the circuit in  FIG. 4  when the phase of the input signal IN lags behind that of the oscillation clock PLCK 2 , including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulses UP and DN, and the control voltage Vct 1 . For the example shown in this drawing, because the enable time of the control pulse UP is shorter than that of the control pulse DN and most of the enable time of the control pulse UP is overlapped with the enable time of the control pulse DN, the control voltage Vct 1  slightly increases and then decreases. As can be seen in this example, the phase detector according to the present invention can greatly reduce the jitter which would be greatly induced in the conventional phase detector owing to the control voltage Vct 1  is increasing greatly and then decreasing greatly. Because the phase of the input signal IN lags behind that of the oscillation clock PLCK 2 , the overall control voltage Vct 1  is decreased so as to lower the frequency of the oscillation clock PLCK 2  and thus shift the phase of the oscillation clock PLCK 2  backward.  
         [0026]      FIG. 8  shows a phase detector according to a second embodiment of the invention. Referring to  FIG. 8 , the phase detector  40 ′ of the invention includes a first control unit  41 ′ and a second control unit  42 ′. The first control unit  41 ′ receives the input signal IN, is clocked by the oscillation clock PLCK 2  and generates the control pulse UP. The control pulse UP is enabled once the level change of the input signal IN is sensed by the first control unit  41 ′, and normally will be disabled at a next negative edge of the oscillation clock PLCK 2 . The second control unit  42 ′ receives the input signal IN, is clocked by a high-frequency clock CLK_HF and generates the control pulse DN. The control pulse DN is?? enabled -at a next negative edge of the high-frequency clock CLK_HF after the level change of the input signal IN is sensed by the second control unit  42 ′, and normally will be disabled after a period of second delay time. In this embodiment, the second delay time is one half of a cycle of the oscillation clock PLCK 2 . For example, if the frequency of the high-frequency clock CLK_HF is eight times that of the oscillation clock PLCK 2 , the second delay time is set to four cycles of the high-frequency clock CLK_HF. The difference between the phase detector  40 ′ of  FIG. 8  and the phase detector  40  of  FIG. 4  is that the enable widths of the control pulses UP and DN of the phase detector  40 ′ is only one half that of the phase detector  40 .  
         [0027]     The first control unit  41 ′ includes a flip-flop  411  and an XOR gate  413 . The flip-flop  411  uses the input signal IN as its input signal and the oscillation clock PLCK 2  as its trigger signal, and the flip-flop  411  is of a negative-edge trigger type in this embodiment. The XOR gate  413  receives the input signal IN and the output signal of the flip-flop  411  and generates the control pulse UP. Suppose the output signals of the XOR gate  413 , the flip-flop  411  are initially at low level. According to the circuit: of the first control unit  41 ′, once the input signal IN is changed form the low level to the high level, the XOR gate  413  outputs the high level simultaneously to enable the control pulse UP. Next, when the oscillation clock PLCK 2  is changed from the high level to the low level, the flip-flop  411  outputs the high level. At this time, because the two input terminals of the XOR gate  413  are at the high level, the XOR gate  413  outputs the low level to disable the control pulse UP. When the input signal IN is changed from the high level to the low level, the XOR gate  413  outputs the high level to enable the control pulse UP because the output of the flip-flop  411  is still the high level. Next, when the oscillation clock PLCK 2  is changed from the high level to the low level, the flip-flop  411  outputs the low level. At this time, because the two input terminals of the XOR gate  413  are at the low level, the XOR gate  413  outputs the low level to disable the control pulse UP.  
         [0028]     The second control unit  42 ′ includes a flip-flop  421 , a delay unit  422 ′, and an XOR gate  423 . The second control unit  42 ′ is similar to the second control unit  42  of  FIG. 4  except that the second delay time of the delay unit  422 ′ is one half that of the delay unit  422 .  
         [0029]      FIG. 9  shows waveforms of some signals of the circuit in  FIG. 8  when the input signal IN and the oscillation clock PLCK 2  have the same phase, including the input signal IN, the oscillation clock PLCK 2 , the high-frequency clock CLK_HF, the control pulses UP and DN, and the control voltage Vct 1 . The frequency of the high-frequency clock CLK_HF in this example is eight times that of the oscillation clock PLCK 2 , so the second delay time is set to four cycles of the high-frequency clock CLK_HF. That is, the enable time of each control pulse DN equals a half cycle of the oscillation clock PLCK 2 . As shown in this drawing, because the control pulses UP and DN have the same enable time and most of the time (3.5 cycles of the high-frequency clock CLK_HF) are overlapped, the variation amount of the control voltage Vct 1  is far smaller than the variation amount of the PLL using the conventional phase detector. In addition, because the input signal and the oscillation clock have the same phase, the control voltage Vct 1  is always kept unchanged.  
         [0030]      FIG. 10  shows the PLL using the phase detector of the invention. Referring to  FIG. 10 , the PLL  90  includes a phase detector  91 , a charge pump  92 , a loop filter  93 , a VCO  94 , and a frequency divider  95 . The architecture of the phase detector  91  is that of  FIG. 4  or  FIG. 8 . Because the PLL  90  includes the frequency divider  95 , the high-frequency clock required by the phase detector  91  may be acquired from the frequency divider  95  without adding additional circuit to produce the high-frequency clock.  
         [0031]     While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.