Abstract:
A method of for programming a push-pull memory cell to simultaneously program a p-channel non-volatile transistor and an n-channel non-volatile transistor includes driving to 0 v wordlines for any row in which programming of memory cells is to be inhibited; driving to a positive voltage wordlines any row in which programming of memory cells is to be performed; driving to a positive voltage the bitlines for any column in which programming of memory cells is to be inhibited; driving to a negative voltage the bitlines for any column in which programming of memory cells is to be performed; driving to one of 0 v and a negative voltage a center wordline for any row in which programming of memory cells is to be inhibited; and driving to one of 0 v and a positive voltage the center wordline for any row in which programming of memory cells is to be performed.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to non-volatile memory cells and to push-pull non-volatile memory cells. More particularly, the present invention relates to simultaneous programming of the n-channel and p-channel non-volatile memory devices in a push-pull non-volatile memory cell. 
         [0003]    2. The Prior Art 
         [0004]    Push-pull flash memory cells are known in the art. These memory cells have been previously programmed in two steps, e.g., first programming the p-channel non-volatile transistor and then programming the n-channel non-volatile transistor. 
         [0005]    Previous push-pull memory cells and programming methods have suffered from several drawbacks. First, the two-step programming of the p-channel non-volatile transistor and the n-channel non-volatile transistor takes additional time, especially in larger arrays. In addition, relatively higher gate-induced drain leakage and high p-channel volatile transistor gate stress of unselected cells might occur during programming. 
       BRIEF DESCRIPTION 
       [0006]    According to one illustrative aspect of the present invention, a push-pull memory cell includes a p-channel non-volatile transistor having a source coupled to a source line, a drain, a floating gate and a control gate, the control gate coupled to a p-channel word line, a p-channel volatile transistor having a source coupled to the drain of the p-channel non-volatile transistor, a drain, and a control gate coupled to a programming word line, and an n-channel non-volatile transistor having a source coupled to a bit line, a drain coupled to the drain of the p-channel volatile transistor, a floating gate and a control gate, the control gate coupled to an n-channel word line. 
         [0007]    According to another illustrative aspect of the present invention, an array of push-pull memory cells arranged in a plurality of rows and columns includes a V P  line associated with each row of the array, a p-word line associated with each row of the array, an n-word line associated with each row of the array, a program-word line associated with each row of the array, and a bit line associated with each column of the array. The array includes a plurality of memory cells, each memory cell uniquely associated with a row in the array and a column in the array. Each memory cell includes a p-channel non-volatile transistor having a source coupled to the V P  line associated with its row, a drain, a floating gate and a control gate, the control gate coupled to the p-word line associated with its row. A p-channel volatile transistor has a source coupled to the drain of the p-channel non-volatile transistor, a drain, and a control gate coupled to the program-word line associated with its row. An n-channel non-volatile transistor has a source coupled to the bit line associated with its column, a drain coupled to the drain of the p-channel volatile transistor, a floating gate and a control gate, the control gate coupled to an n-word line associated with its row. 
         [0008]    According to another illustrative aspect of the present invention, an array of push-pull memory cells arranged in a plurality of rows and columns includes a p-word line associated with each row of the array, an n-word line associated with each row of the array, a program-word line associated with each row of the array, a p-bit line associated with each column of the array, and an n-bit line associated with each column of the array. The array includes a plurality of memory cells, each memory cell uniquely associated with a row in the array and a column in the array. Each memory cell includes a p-channel non-volatile transistor having a source coupled to the p-bit line associated with its column, a drain, a floating gate and a control gate, the control gate coupled to the p-word line associated with its row. A p-channel volatile transistor has a source coupled to the drain of the p-channel non-volatile transistor, a drain, and a control gate coupled to the program-word line associated with its row. An n-channel non-volatile transistor has a source coupled to the n-bit line associated with its column, a drain coupled to the drain of the p-channel volatile transistor, a floating gate and a control gate, the control gate coupled to the n-word line associated with its row. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
         [0009]      FIG. 1  is a schematic diagram of an illustrative push-pull memory cell according to one aspect of the present invention. 
           [0010]      FIG. 2  is a schematic diagram of a portion of an illustrative array of push-pull memory cells according to one aspect of the present invention. 
           [0011]      FIG. 3  is a schematic diagram of a portion of another illustrative array of push-pull memory cells according to one aspect of the present invention. 
           [0012]      FIG. 4  is a table showing exemplary programming and operating conditions for the various operating modes of the array portions shown in  FIGS. 2 and 3 . 
       
    
    
     DETAILED DESCRIPTION 
       [0013]    Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
         [0014]    Referring now to  FIG. 1 , a schematic diagram shows an illustrative push-pull flash memory cell  10  according to one aspect of the present invention. Flash memory cell  10  includes p-channel non-volatile memory transistor  12  and n-channel non-volatile memory transistor  14 . P-channel non-volatile memory transistor  12  is formed in deep n-well  16  and n-channel non-volatile memory transistor  14  is formed in high-voltage p-well  18 . 
         [0015]    Memory cell  10  also includes a third transistor, p-channel transistor  20 . P-channel transistor  20  may be formed as a double gate structure like transistors  12  and  14 , having its floating gate shorted to its control gate as shown by the schematic symbol in which the two gates are connected. Such a geometry lowers the on-state V DS  of the transistor and allows p-channel transistor  20  to be formed without having to observe single-poly to double-poly design-rule spacing to allow for a smaller cell geometry. Persons skilled in the art will appreciate that P-channel transistor  20  may also be formed as a single-gate transistor. 
         [0016]    Memory cell  10  also includes n-channel switch transistor  22 , having its gate connected to the common drain connections of n-channel non-volatile transistor  14  and p-channel transistor  20 . N-channel switch transistor  22  is used to selectively connect together the circuit nodes identified as A and B in  FIG. 1 . Since switch transistor  22  is an n-channel device, it will be turned on during normal circuit operation when p-channel volatile transistor  20  is turned on and when the memory cell  10  is programmed such that p-channel non-volatile transistor  12  is turned on and n-channel non-volatile transistor  14  is turned off. 
         [0017]    The source of p-channel non-volatile transistor  12  is coupled to p bitline (reference numeral  24 ) that runs in the column direction of the array. The gate of p-channel non-volatile transistor  12  is coupled to p-channel wordline WL p  (reference numeral  26 ) that runs in the row direction of the array. The source of n-channel non-volatile transistor  14  is coupled to bitline BL (reference numeral  28 ) that runs in the column direction of the array. The gate of n-channel non-volatile transistor  14  is coupled to n-channel wordline WL n  (reference numeral  30 ) that runs in the row direction of the array. The gate of p-channel volatile transistor  20  is coupled to wordline WL pr  (reference numeral  32 ) that runs in the row direction of the array. 
         [0018]    As previously mentioned, p-channel volatile transistor  20  is turned on during normal circuit operation so that p-channel non-volatile memory transistor  12  and n-channel non-volatile memory transistor  14  are connected in series and act as a push-pull memory cell under the condition that one of them is turned on and the other one is turned off to drive the gate of n-channel switch transistor  22  to either ground through n-channel non-volatile memory transistor  14  to turn it off or to VDD through p-channel non-volatile memory transistor  12  and p-channel volatile transistor  20  (turned on during normal circuit operation) to turn it on. Thus, during normal circuit operation all of the wordlines WL pr  in the array are driven to zero volts. 
         [0019]    Programming of memory cell  10  is accomplished by placing the appropriate potentials on the various control lines WL p , WL n , and WL pr , and p bitline  24  and n bitline  28 . For example, by simultaneously applying about 12 v to about 16 v to the n-channel wordline  30  and about 6 v to about 9 v to the p-channel wordline  26  while applying about −2 v to about −4 v to the bitline line  24  and the bitline  28 , both p-channel non-volatile transistor  12  and p-channel non-volatile transistor  14  can be programmed simultaneously. 
         [0020]    Referring now to  FIG. 2 , a schematic diagram shows a portion  40  of an illustrative array of push-pull non-volatile memory cells according to one aspect of the present invention. Portion  40  of the array of push-pull non-volatile memory cells is shown having four memory cells arrayed in two rows and two columns although persons of ordinary skill in the art will recognize from this disclosure that arrays of any size may be fabricated using the principles of the present invention. The memory cell  42  in the first row of the first column of array  40  includes p-channel non-volatile memory transistor  44  and n-channel non-volatile memory transistor  46 . P-channel non-volatile memory transistor  44  is formed in deep n-well  48  and n-channel non-volatile memory transistor  46  is formed in high-voltage p-well  50 . 
         [0021]    Memory cell  42  also includes a third transistor, p-channel transistor  52 . P-channel transistor  52  may be formed as a double gate structure like transistors  44  and  46 , having its floating gate shorted to its control gate as shown by the schematic symbol in which the two gates are connected. Such a geometry lowers the on-state V DS  of the transistor and allows p-channel transistor  52  to be formed without having to observe single-poly to double-poly design-rule spacing to allow for a smaller cell geometry. Persons skilled in the art will appreciate that P-channel transistor  52  may also be formed as a single-gate transistor. 
         [0022]    Memory cell  42  also includes n-channel switch transistor  54 , having its gate connected to the common drain connections of n-channel non-volatile transistor  46  and p-channel transistor  52 . N-channel switch transistor  54  is used to selectively connect together the circuit nodes identified as A and B in  FIG. 2 . Since switch transistor  54  is a N-channel device, it will be turned on during normal circuit operation when p-channel volatile transistor  52  is turned on and when the memory cell  42  is programmed such that p-channel non-volatile transistor  44  is turned on and n-channel non-volatile transistor  46  is turned off. 
         [0023]    The memory cell  56  in the first row of the second column of array  40  includes p-channel non-volatile memory transistor  58  and n-channel non-volatile memory transistor  60 . P-channel non-volatile memory transistor  58  is formed in deep n-well  48  and n-channel non-volatile memory transistor  60  is formed in high-voltage p-well  50 . 
         [0024]    Memory cell  56  also includes a third transistor, p-channel transistor  62 . P-channel transistor  62  may be formed as a double gate structure like transistors  58  and  60 , having its floating gate shorted to its control gate as shown by the schematic symbol in which the two gates are connected. Such a geometry lowers the on-state V DS  of the transistor and allows p-channel transistor  62  to be formed without having to observe single-poly to double-poly design-rule spacing to allow for a smaller cell geometry. Persons skilled in the art will appreciate that P-channel transistor  62  may also be formed as a single-gate transistor. 
         [0025]    Memory cell  56  also includes n-channel switch transistor  64 , having its gate connected to the common drain connections of n-channel non-volatile transistor  60  and p-channel transistor  62 . N-channel switch transistor  64  is used to selectively connect together the circuit nodes identified as C and D in  FIG. 2 . Since switch transistor  64  is an n-channel device, it will be turned on during normal circuit operation when p-channel volatile transistor  62  is turned on and when the memory cell  56  is programmed such that p-channel non-volatile transistor  58  is turned on and n-channel non-volatile transistor  60  is turned off. 
         [0026]    The memory cell  66  in the second row of the first column of array  40  includes p-channel non-volatile memory transistor  68  and n-channel non-volatile memory transistor  70 . P-channel non-volatile memory transistor  68  is formed in deep n-well  48  and n-channel non-volatile memory transistor  70  is formed in high-voltage p-well  50 . 
         [0027]    Memory cell  66  also includes a third transistor, p-channel transistor  72 . P-channel transistor  72  may be formed as a double gate structure like transistors  68  and  70 , having its floating gate shorted to its control gate as shown by the schematic symbol in which the two gates are connected. Such a geometry lowers the on-state V DS  of the transistor and allows p-channel transistor  72  to be formed without having to observe single-poly to double-poly design-rule spacing to allow for a smaller cell geometry. Persons skilled in the art will appreciate that P-channel transistor  72  may also be formed as a single-gate transistor. 
         [0028]    Memory cell  66  also includes n-channel switch transistor  74 , having its gate connected to the common drain connections of n-channel non-volatile transistor  70  and p-channel transistor  72 . N-channel switch transistor  74  is used to selectively connect together the circuit nodes identified as E and F in  FIG. 2 . Since switch transistor  74  is an n-channel device, it will be turned on during normal circuit operation when p-channel volatile transistor  72  is turned on and when the memory cell  66  is programmed such that p-channel non-volatile transistor  68  is turned on and n-channel non-volatile transistor  70  is turned off. 
         [0029]    The memory cell  76  in the second row of the second column of array  40  includes p-channel non-volatile memory transistor  78  and n-channel non-volatile memory transistor  80 . P-channel non-volatile memory transistor  78  is formed in deep n-well  48  and n-channel non-volatile memory transistor  80  is formed in high-voltage p-well  50 . 
         [0030]    Memory cell  76  also includes a third transistor, p-channel transistor  82 . P-channel transistor  82  may be formed as a double gate structure like transistors  78  and  80 , having its floating gate shorted to its control gate as shown by the schematic symbol in which the two gates are connected. Such a geometry lowers the on-state V DS  of the transistor and allows p-channel transistor  82  to be formed without having to observe single-poly to double-poly design-rule spacing to allow for a smaller cell geometry. Persons skilled in the art will appreciate that P-channel transistor  82  may also be formed as a single-gate transistor. 
         [0031]    Memory cell  76  also includes n-channel switch transistor  84 , having its gate connected to the common drain connections of n-channel non-volatile transistor  80  and p-channel transistor  82 . N-channel switch transistor  84  is used to selectively connect together the circuit nodes identified as G and H in  FIG. 2 . Since switch transistor  84  is an n-channel device, it will be turned on during normal circuit operation when p-channel volatile transistor  82  is turned on and when the memory cell  76  is programmed such that p-channel non-volatile transistor  78  is turned on and n-channel non-volatile transistor  80  is turned off. 
         [0032]    In the portion  40  of the memory array shown in  FIG. 2 , the sources of the n-channel non-volatile transistors  46  and  70  in the first column of the array are coupled to a bitline  86 . The sources of the n-channel non-volatile transistors  60  and  80  in the second column of the array are coupled to a bitline  88 . The sources of the p-channel non-volatile transistors  44  and  58  in the first row of the array are connected to Vp line  90 , and the sources of the p-channel non-volatile transistors  68  and  78  in the second row of the array are connected to Vp line  92 . 
         [0033]    The control gates of the p-channel non-volatile transistors  44  and  58  in the first row of the array are coupled to wordline WL p0  at reference numeral  94 . The control gates of the p-channel non-volatile transistors  68  and  78  in the second row of the array are coupled to wordline WL p1  at reference numeral  96 . The control gates of the n-channel non-volatile transistors  46  and  60  in the first row of the array are coupled to wordline WL n0  at reference numeral  98 . The control gates of the n-channel non-volatile transistors  70  and  80  in the second row of the array are coupled to wordline WL n1  at reference numeral  100 . The control gates of the p-channel volatile transistors  52  and  62  in the first row of the array are coupled to wordline WL pr0  at reference numeral  102 . The control gates of the p-channel volatile transistors  72  and  82  in the second row of the array are coupled to wordline WL pr1  at reference numeral  104 . 
         [0034]    Referring now to  FIG. 3 , a schematic diagram shows a portion  110  of another illustrative array of push-pull memory cells according to an aspect of the present invention. The portion  110  of the array of  FIG. 3  is substantially similar to the array  40  of  FIG. 2  and, where appropriate structures in  FIG. 3  that correspond to like structures in  FIG. 2  are identified by the same reference numerals used in  FIG. 2 . The description accompanying  FIG. 2  applies for the most part to the array shown in  FIG. 3  except that there are some differences in the wiring of the cells in the portion  110  of the array of  FIG. 3 . Instead of V p  lines running in the row direction of the array being coupled to the sources of the p-channel non-volatile transistors in the same row, bitlines BL n0  (identified at reference numeral  112 ) and BL n1  (identified at reference numeral  114 ) run in the column direction and are coupled to the sources of the p-channel non-volatile transistors in the same column. 
         [0035]    Referring now to  FIG. 4 , a table shows exemplary programming conditions for the various operating modes of the array portions shown in  FIGS. 2 and 3 . The table of  FIG. 4  shows two alternate versions of biasing conditions for simultaneous programming for the array shown in  FIG. 3  and one version of biasing conditions for simultaneous programming for the array shown in  FIG. 2  according to the present invention. While specific voltages are shown in the table of  FIG. 4 , persons skilled in the art will appreciate that actual voltages used in any array will depend on device geometry and process considerations and that the numbers given in the table are merely illustrative and the values used herein relate to memory cells fabricated using a 0.65 micron process. 
         [0036]    In general, for programming the arrays shown in both  FIGS. 2 and 3 , to inhibit programming in row x, wordlines WL px , WL nx , and WL prx  for row x are driven to 0 v and to inhibit programming in column y, the bitlines BL py  and BL ny  for column y are driven to a positive voltage. To select programming in row x, wordlines WL px  and WL nx  for row x are driven to positive voltages, wordline WL prx  is driven to either 0 v or a negative voltage, and to enable programming in column y, the bitlines BL py  and BL ny  for column y are driven to a negative voltage. 
         [0037]    According to a first version of simultaneous programming for the array shown in  FIG. 3 , bitlines BL n0  and BL p0  are driven to a potential of −3.5 v and bitlines BL n1  and BL p1  are driven to a potential of 3.5 v. In the first row of the array, wordline WL p0  is driven to a potential of 8.5 v, wordline WL pr0  is driven to a potential of 0 v, and WL n0  is driven to a potential of 15.5 v. In the second row of the array, wordline WL p1  is driven to a potential of 0 v, WL pr1  is driven to a potential of between 0 v and 2 v, and WL n1  is driven to a potential of 0 v. The deep n-well  48  is driven to a potential of 3.5 v and the high-voltage p-well  50  is driven to a potential of −3.5 v. 
         [0038]    In memory cell  42  the V gs  of p-channel non-volatile transistor  44  is 12.0 v, the V gs  of n-channel non-volatile transistor  46  is 19.0 v, and the V gs  of p-channel volatile transistor  52  is 3.5 v. Under these conditions, transistors  44  and  52  will be turned off and transistor  46  will be turned on. In memory cell  56  the V gs  of p-channel non-volatile transistor  58  is 5.0 v, the V gs  of n-channel non-volatile transistor  60  is 12.0 v, and the V gs  of p-channel volatile transistor  62  is −3.5 v. Under these conditions, transistor  58  will be turned off and transistors  60  and  62  will be turned on. 
         [0039]    In memory cell  66  the V gs  of p-channel non-volatile transistor  68  is 3.5 v, the V gs  of n-channel non-volatile transistor  70  is 3.5 v, and the V gs  of p-channel volatile transistor  72  is 5.5 v. Under these conditions, if memory cell  66  is programmed, transistor  68  will be turned on or off depending on the V t  shift during the life cycle of the transistor, and transistors  70 , and  72  will be turned off. If memory cell  66  is erased, transistors  68  and  72  will be turned off and transistor  70  will be turned on or off depending on the V t  shift during the life cycle of the transistor. In memory cell  76  the V gs  of p-channel non-volatile transistor  78  is −3.5 v, the V gs  of n-channel non-volatile transistor  80  is −3.5 v, and the V gs  of p-channel volatile transistor  82  is −1.5 v. Under these conditions, if memory cell  76  is programmed, transistors  80  and  82  will be turned off and transistor  78  will be turned on. If memory cell  66  is erased, transistors  80  and  82  will be turned off and transistor  78  may be in either state. 
         [0040]    According to a second version of simultaneous programming for the array shown in  FIG. 3 , bitlines BLn 0  and BLp 0  are driven to a potential of −2.5 v and bitlines BLn 1  and BLp 1  are driven to a potential of 2.5 v. In the first row of the array, wordline WLp 0  is driven to a potential of 8.5 v, wordline WLpr 0  is driven to a potential of −4.5 v, and WLn 0  is driven to a potential of 14.5 v. In the second row of the array, wordline WLp 1  is driven to a potential of 0 v, WLpr 1  is driven to a potential of 0 v, and WLn 1  is driven to a potential of 0 v. The deep n-well  48  is driven to a potential of 2.5 v and the high-voltage p-well  50  is driven to a potential of −2.5 v. 
         [0041]    According to a version of simultaneous programming for the array shown in  FIG. 2 , bitline BL p0  is driven to a potential of 0 v, BL n0  is driven to a potential of −3 v, bitline BL p1  is driven to a potential of 0 v and BL n1  is driven to a potential of 3 v. In the first row of the array, wordline WL p0  is driven to a potential of 8.5 v, wordline WL pr0  is driven to a potential of −5 v, and WL n0  is driven to a potential of 15.5 v. In the second row of the array, wordline WL p1  is driven to a potential of 0 v, WL pr1  is driven to a potential of −3 v, and WL n1  is driven to a potential of 0 v. The deep n-well  48  is driven to a potential of 3 v and the high-voltage p-well  50  is driven to a potential of −3 v. 
         [0042]    In memory cell  42  the V gs  of p-channel non-volatile transistor  44  is 11.5, the V gs  of n-channel non-volatile transistor  46  is 18.5 v, and the V gs  of p-channel volatile transistor  52  is −2.0 v. Under these conditions, transistors  44  will be turned off and transistor  52  and  46  will be turned on. In memory cell  56  the V gs  of p-channel non-volatile transistor  58  is 8.0 v, the V gs  of n-channel non-volatile transistor  60  is 12.5 v, and the V gs  of p-channel volatile transistor  62  is −8.0 v. Under these conditions, transistor  58  will be turned off and transistors  60  and  62  will be turned on. 
         [0043]    In memory cell  66  the V gs  of p-channel non-volatile transistor  68  is 0 v, the V gs  of n-channel non-volatile transistor  70  is 3.0 v, and the V gs  of p-channel volatile transistor  72  is 0 v. Under these conditions, if memory cell  66  is programmed, transistor  68  will be turned on or off depending on the V t  shift during the life cycle of the transistor, and transistors  70  off and  72  will be turned on. If memory cell  66  is erased, transistors  68  and  72  will be turned off and transistor  70  will be turned on. In memory cell  76  the V gs  of p-channel non-volatile transistor  78  is 0 v, the V gs  of n-channel non-volatile transistor  80  is −3.0 v, and the V gs  of p-channel volatile transistor  82  is −3.0 v. Under these conditions, if memory cell  76  is programmed, transistors  80  will be turned off and transistor  82  turned on and transistor  78  will be turned on or off. If memory cell  66  is erased, transistors  80  and  78  will be turned off and transistor  82  turned on. 
         [0044]    According to a second version of simultaneous programming for the array shown in  FIG. 3 , bitlines BLn 0  and BLp 0  are driven to a potential of −2.5 v and bitlines BLn 1  and BLp 1  are driven to a potential of 2.5 v. In the first row of the array, wordline WLp 0  is driven to a potential of 8.5 v, wordline WLpr 0  is driven to a potential of −4.5 v, and WLn 0  is driven to a potential of 14.5 v. In the second row of the array, wordline WLp 1  is driven to a potential of 0 v, WLpr 1  is driven to a potential of 0 v, and WLn 1  is driven to a potential of 0 v. The deep n-well  48  is driven to a potential of 2.5 v and the high-voltage p-well  50  is driven to a potential of −2.5 v. 
         [0045]    While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.