Abstract:
An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is targeted at resonant clock distribution networks and allows for the adjustment of resonant clock waveform characteristics with no need to route an additional power grid. Such an architecture is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

Description:
CLAIM OF PRIORITY AND RELATED APPLICATIONS 
     This patent application is a conversion of and claims priority to U.S. Provisional Patent Application No. 61/250,830, entitled S YSTEMS AND  M ETHODS FOR  R ESONANT  C LOCKING  I NTEGRATED  C IRCUITS , filed Oct. 12, 2009, which is incorporated herein in its entirety. This patent application is related to the technologies described in the following patents and applications, all of which are incorporated herein in their entireties: 
     U.S. patent application Ser. No. 12/125,009, entitled R ESONANT  C LOCK AND  I NTERCONNECT  A RCHITECTURE FOR  D IGITAL  D EVICES WITH  M ULTIPLE  C LOCK  N ETWORKS , filed Oct. 12, 2009, which claims priority to U.S. Provisional Patent Application No. 60/931,582, entitled R ESONANT  C LOCK AND  I NTERCONNECT  A RCHITECTURE FOR  P ROGRAMMABLE  L OGIC  D EVICES , filed May 23, 2007; 
     U.S. patent application Ser. No. 12/903,154, entitled R ESONANT  C LOCK  D ISTRIBUTION  N ETWORK  A RCHITECTURE WITH  P ROGRAMMABLE  D RIVERS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,163, entitled M ETHOD FOR  S ELECTING  N ATURAL  F REQUENCY  IN R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS WITH NO  I NDUCTOR  O VERHEAD , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,166, entitled A RCHITECTURE FOR  A DJUSTING  N ATURAL  F REQUENCY IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,168, entitled A RCHITECTURE FOR  F REQUENCY -S CALED  O PERATION IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,172, entitled A RCHITECTURE FOR  S INGLE -S TEPPING IN  R ESONANT  C LOCK  D ISTRIBUTION  N ETWORKS , filed Oct. 12, 2010; 
     U.S. patent application Ser. No. 12/903,174, entitled A RCHITECTURE FOR  O PERATING  R ESONANT  C LOCK  N ETWORK IN  C ONVENTIONAL  M ODE , filed Oct. 12, 2010; and 
     U.S. patent application Ser. No. 12/903,188, entitled R ESONANT  C LOCK  D ISTRIBUTION  N ETWORK  A RCHITECTURE FOR  T RACKING  P ARAMETER  V ARIATIONS IN  C ONVENTIONAL  C LOCK  D ISTRIBUTION  N ETWORKS  filed Oct. 12, 2010. 
    
    
     FIELD OF INVENTION 
     This disclosure relates generally to clock distribution network architectures for digital devices with multiple clock networks and various clock frequencies such as microprocessors, application-specific integrated circuits (ASICs), and System-on-a-Chip (SOC) devices. 
     BACKGROUND OF THE INVENTION 
     Clock distribution networks are key elements of digital semiconductor devices. Clock signals are used to synchronize the operations performed in these devices and are typically distributed to thousands of clocked elements in the design. The characteristics of the clock waveform (for example, rise times of the clock edges, peak amplitude attained by the clock waveform, distance from power/ground rails, etc.) are critical to the overall performance of the device, as they determine the speed at which the clocked storage elements store data or propagate data to their outputs. As a consequence, significant design effort is expended on clock distribution networks, to ensure that clock waveforms conform to their specified characteristics. Furthermore, clock distribution networks tend to be significant sources of energy consumption in high-performance designs, as they usually include over-sized devices to ensure that they conform to their specified characteristics under all anticipated variations of fabrication and operational conditions. Consequently, in designs where it is desirable to minimize energy consumption, the design of clock distribution networks is especially challenging, because reductions in energy consumption of the clock distribution network will tend to negatively impact the ability of the clock distribution network to attain its specified characteristics. 
     Traditionally, a clock distribution network comprises a number of clock buffers that are used to propagate a reference clock signal from a single root point to multiple clocked storage elements. These clock buffers are supplied with power from the same power supply grid as the other circuitry in the device, and therefore, they operate at the same voltage level as the other circuitry. The arrival times of the clock signal to the storage elements are controlled by a variety of means, but generally at least in part by sizing the buffers so that the propagation delays of the various paths from the root to the storage elements are approximately equal. In addition to controlling the propagation delays of paths from the root to the storage elements, however, the sizing of the individual buffers is used to control the rise times of the clock signals as they are seen by the storage elements. In particular, the sizes of the buffers are typically made large enough to insure that the rise times and fall times of these clock signals cannot exceed a certain upper bound, because many types of storage elements will not attain their specified performance characteristics if the rise and/or fall times are too long. 
     In addition to the network of buffers, the system that supplies power to the buffers must also be considered as part of the overall clock distribution system. In most devices, the reference clock is distributed across the design to a set of final clock buffers, whose elements drive bufferless all-metal networks that deliver a clock signal directly to the inputs of storage elements; i.e., the last stage of buffers in the distribution network. These final buffers are typically large and draw large amounts of current within a relatively small window of time. These large current draws over a small time window can overwhelm the ability of the device&#39;s power-supply system, and cause variations in the voltage supplied to the final drivers, negatively impacting their performance. Moreover, since the final drivers typically share the power-supply system with other parts of the overall device, any variations in voltage that they cause will affect the operation of other parts of the device, and have additional negative impacts. As a consequence, ensuring that components of the clock-distribution network receive a stable power voltage, and in addition, ensuring that these components do not compromise the power voltage supplied to other parts of the overall device is an important part of the clock distribution network design effort. 
     Energy consumption in clock distribution networks can generally be reduced with the same methods as other circuitry in a design. For example, the energy consumption of other circuitry can be reduced by reducing the voltage of the power supplied to the circuitry. Similarly, by reducing the voltage supplied to the buffers in the clock distribution network, the energy consumption of the network can be reduced as well. Energy consumption of other circuitry can also be reduced by using smaller transistors to implement the circuitry, and similarly, by reducing the sizes of the transistors that implement the buffers of the clock distribution network, energy consumption of the clock distribution network can be reduced as well. Unfortunately, reduction of the voltage supplied to the clock distribution network buffers and reduction of the sizes of the transistors used to implement the buffers will have a negative impact on the ability of the network to realize suitable rise and/or fall times. Longer rise and/or fall times will generally have a negative impact on the performance of the storage elements that use the clock signal. Moreover, since a reduction in the power-voltage supplied to the buffers will typically directly translate into a reduction in the peak-to-peak “swing” of the voltage of the clock signal itself, the performance of the storage elements that use the clock signal will further be negatively impacted. 
     Given the sometimes large amount of energy consumed by clock distribution networks, and the secondary impact of their performance on the performance of the various storage elements in a device, it can be desirable to be able to control the operation of the clock distribution network independently from the operation of the other parts of a device. For example, in some contexts, it can be desirable to operate other parts of a device with a very low power-voltage supply, in order to drastically reduce energy consumption. However, if the clock buffers are on the same supply grid as the other circuitry in the device, the peak-to-peak voltage swing of the clock signal and rise and/or fall times of the clock signal may be so compromised by the low power-voltage, that performance of the storage elements using the clock will be too poor to be practical. In a situation such as this, it would be desirable to decouple the supply of the clock distribution network from the supply of other circuitry by dedicating to it a separate supply grid. Such a separate supply grid would traditionally need to be distributed across the entire design, however, due to the distributed nature of the buffers in the distribution network, and thus, represents an amount of additional metal-interconnection resources that is not practical in many designs. 
     Resonant clock distribution networks have been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through the reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance. 
     Architectures for resonant clock distribution networks have been described and empirically evaluated in several articles, including “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; “A 1 GHz filter with distributed resonant clock generator,” by Sathe V., et al., IEEE Symposium on VLSI Circuits, June 2007; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007; “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. Throughout these articles, driver sizing and duty cycle adjustment are used to minimize the amount of energy required to keep the resonant clock network swinging at the peak-to-peak power-voltage that would be realized by a traditional clock distribution network of buffers. 
     A hitherto unexploited characteristic of resonant clock distribution networks is that sizing of the resonant clock drivers and/or adjustment of the duty cycle of the reference clock will have an effect on the amplitude of the clock signal, without requiring the distribution of a separate voltage supply level. Consequently, by adjusting the size of the resonant clock drivers or the duty cycle of the reference clock in resonant clock networks, peak-to-peak clock levels can be made to be higher or lower than the voltage supplied to the other circuitry in the device, enabling higher performance at a given supply level, or higher energy efficiency at a given performance level. Specifically, for a given supply level, it is possible to operate the clock at a higher peak level, resulting in faster operation of the clocked storage elements and, therefore, faster operation of the device. Similarly, for a target performance level, it is possible to run the clock at a higher amplitude than the voltage supplied to the other circuitry, resulting in faster operation of the clocked storage elements, and thus, enabling further reduction in the voltage supply of the other circuitry. Moreover, unlike the distributed locations of clock buffers traditionally seen in non-resonant clock distribution networks, the locations of clock drivers in resonant clock distribution networks can be centralized at the locations of the requisite inductor elements, thereby avoiding the need for distributed-control solutions for the dynamic adjustment of clock driver sizing and/or duty-cycle of the reference clock. 
     In all prior art references, driver sizing and duty cycle adjustment are explored in the limited context of energy efficiency in the resonant clock network itself. They are not used to control clock rise and/or fall times or clock amplitude. Moreover, they are not used to impact overall power consumption in the device by operating the clock signal at a higher or lower voltage than the other circuitry in the device, with the objective of achieving higher performance at a target voltage level, or lower energy consumption at a target performance level. 
     Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description. 
     SUMMARY OF THE DESCRIPTION 
     An architecture for controlling the clock waveform characteristics, including but not limited to the clock amplitude and clock rise and/or fall times, of resonant clock distribution networks is proposed. This architecture relies on controlling the size of clock drivers and the duty cycles of reference clocks. It is generally applicable to semiconductor devices with multiple clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs. In some embodiments, the architecture can be realized with no need for routing additional power grids or additional control signals to clock-distribution network components whose physical locations are not centralized in the vicinity of the inductive elements of the resonant clock distribution network. 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Other advantages and features will become apparent from the following description and claims. It should be understood that the description and specific examples are intended for purposes of illustration only and not intended to limit the scope of the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       These and other objects, features and characteristics of the present invention will become more apparent to those skilled in the art from a study of the following detailed description in conjunction with the appended claims and drawings, all of which form a part of this specification. In the drawings: 
         FIG. 1  illustrates a typical architecture of a conventional buffered clock distribution network. 
         FIG. 2  illustrates a typical architecture of a conventional buffered clock distribution network in which the final buffers drive an all-metal mesh. 
         FIG. 3  illustrates a typical architecture of a resonant clock distribution network. 
         FIG. 4  illustrates a typical driver design for resonant clocking with the clock load modeled as a lumped capacitor. 
         FIG. 5  illustrates a typical architecture of a resonant clock distribution network, in which multiple resonant clock drivers operate in parallel to drive a large all-metal mesh. 
         FIG. 6  illustrates an embodiment of a resonant clock driver in the proposed architecture for controlling the characteristics of the resonant clock waveform by selectively enabling drivers of the clock node. 
         FIG. 7  illustrates the derivation of reference clock signals with various duty cycles from a reference clock signal with a given duty cycle. 
         FIG. 8  illustrates an embodiment of a resonant clock driver in the proposed architecture for controlling the characteristics of the resonant clock waveform by adjusting the size of the drivers and the duty cycle of the reference clocks. 
         FIG. 9  shows an exemplary embodiment of a driver in the proposed architecture for controlling the characteristics of the resonant clock waveform by adjusting the size of the drivers and the duty cycle of the reference clocks, but where the sizes and duty cycles of the reference clocks are independently adjusted for multiple sub-drivers, to account for variations in load over the resonant-clock distribution network. 
     
    
    
     The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. 
     In the drawings, the same reference numbers and any acronyms identify elements or acts with the same or similar structure or functionality for ease of understanding and convenience. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the Figure number in which that element is first introduced (e.g., element  204  is first introduced and discussed with respect to  FIG. 2 ). 
     DETAILED DESCRIPTION OF THE INVENTION 
     Various examples of the invention will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. One skilled in the relevant art will understand, however, that the invention may be practiced without many of these details. Likewise, one skilled in the relevant art will also understand that the invention can include many other obvious features not described in detail herein. Additionally, some well-known structures or functions may not be shown or described in detail below, so as to avoid unnecessarily obscuring the relevant description. 
     The terminology used below is to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the invention. Indeed, certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. 
       FIG. 1  shows a conventional network for distributing a reference clock signal to multiple clocked elements such as flip-flops and clock gaters. In this network, a collection of buffers is used to propagate a reference clock signal that is supplied at the root of the network to multiple clocked elements throughout a semiconductor device. The propagation delays of the paths from the root to the clocked elements are generally balanced, for example, so that the clock signal arrives at all these elements at approximately the same time. Propagation delays are controlled by adjusting the size of the buffers along the paths. The size of these buffers also determine the rise times of the clock signals, that is, the amount of time required for the clock signal to rise from 10% of its peak value to 90% of its peak value. Clock rise times are critical for overall device performance, as they determine the speed at which data are stored into clocked storage elements, and the speed at which data propagate to the outputs of clocked storage elements. 
     Typically, power is supplied to the clock buffers through the same grid that is used to supply power to the other circuitry in the device. Therefore, the peak amplitude of the clock signal is typically equal to that of any other signal in the design. In the case of high-performance devices, particular care is devoted to ensuring that clock buffers are supplied with as stable a voltage level as possible. In these devices, the reference clock is distributed across the entire design to a set of final clock buffers (or drivers), that is the last stage of buffers in the distribution network, which may in concert drive an all-metal mesh structure that delivers the clock signal to its final destinations.  FIG. 2  illustrates such a clock distribution network. Typically, these final buffers are large and draw significant levels of current within a narrow time interval. To ensure a stable supply, and therefore a stable clock signal, large decoupling capacitors may be placed in the vicinity of the final buffers, so that their operation remains relatively unaffected by the current draw requirements of other circuitry. 
       FIG. 3  depicts a resonant clock distribution network architecture for a semiconductor device. In this design, the buffered distribution network has been replaced by an all-metal distribution network. Typically, this all-metal network has an approximately symmetric topology, delivering the clock signal to the clocked elements (for example, flip-flops and clock gaters) of the semiconductor device with very low skew. The network includes a clock driver that is augmented by an inductor that provides additional drive strength with low energy consumption by resonating the parasitic capacitance of the load seen by the driver. The resulting combination of the buffer, inductor, and other ancillary circuitry is typically referred to as a resonant clock driver. In this figure, the final clock driver is an NMOS device that is driven by the reference clock signal, forcing the clock network to oscillate at the frequency of the reference clock. One terminal of the inductor is connected to the clock node, while the other terminal is connected to a supply node with voltage at approximately the mid-point of the clock signal oscillation. For example, if the clock signal oscillates between 0V and 1V, then the mid-point supply is approximately set to 0.5V. 
     Unlike the buffered clock distribution network of  FIG. 1 , the resonant clock distribution network in  FIG. 3  has a single buffer at its root. Therefore, the rise time of the clock waveform can be controlled by adjusting the size of that single buffer, instead of requiring the adjustment of all the final buffers in the clock network. Moreover, unlike the buffered clock distribution network of  FIG. 1 , in which the amplitude of the clock signal is equal to the voltage supplied to the rest of the design, the amplitude of the resonant clock can be controlled by adjusting the size of the resonant clock driver, or by adjusting the duty cycle of the reference clock that drives it. Specifically, by increasing the size of the NMOS device, a larger current builds up in the inductor, storing a larger amount of energy in its surrounding magnetic field. When the NMOS device turns off, the increased magnetic field is transformed into a larger electric field on the clock capacitor, resulting in a voltage level that exceeds the supply level. Conversely, by decreasing the size of the NMOS device, the current through the inductor is limited, and the amplitude of the clock signal can be kept below the supply voltage for the rest of the circuitry. In a similar manner, the duty cycle of the reference clock can be used to build up more or less current in the inductor, resulting in clock amplitudes that are greater or less than the supply voltage. In a buffered clock distribution, control of the clock rise times is achieved by adjusting each one of the individual final buffers. Moreover, it is not possible to independently control the amplitude of the clock signal from the maximum level of the other signals in the device, unless a separate supply is provided to the clock buffers. In a resonant clock distribution network, it is possible to control the rise time and the amplitude of the control signal from a single point in the design, namely the resonant clock driver, without requiring an additional power supply network. 
       FIG. 4  illustrates another embodiment of a resonant clock driver design, in which the clock distribution network is modeled as a lumped capacitor C in series with a lumped resistance R. This driver comprises a pull-up PMOS and a pull-down NMOS device for driving the clock. The PMOS device is connected between the clock node and the power supply terminal. The NMOS device is connected between the clock node and the ground terminal. Both devices are driven by the reference clock signal. An inductor L is connected between the clock node and the mid-point supply node. In the driver shown in this figure, the mid-point is implemented using two capacitors Cdd and Css. Capacitor Cdd is connected between the mid-point and the power supply terminal. Capacitor Css is connected between the mid-point and the ground terminal. To maximize energy savings, the value of the inductor is approximately chosen so that the LC tank set up by the inductor and the parasitic capacitance of the clock distribution network has a natural frequency that is approximately equal to the frequency of the reference clock signal. The switch S can be used to selectively decouple the inductor from the mid-point supply, thus providing the option of driving the clock network in non-resonant mode. When the control signal EN turns the switch on, the driver operates in resonant mode. When the switch is turned off, then the driver operates in non-resonant mode. In this figure, the switch is shown as a transmission gate. 
     For large clock loads, multiple resonant clock drivers are typically combined in parallel, as illustrated in  FIG. 5 . In this embodiment, the reference clock is distributed to the resonant clock drivers using a buffered distribution network. The resonant clock drivers are operated in parallel, driving the all-metal mesh to oscillate at the same frequency as the reference clock. 
       FIG. 6  shows an embodiment of the proposed architecture for controlling the characteristics of a clock waveform from a centralized point. In this embodiment, the resonant clock driver comprises a collection of NMOS and PMOS devices that can be selectively activated using control signals EN 1 , . . . , ENn. By increasing the size of the resonant driver, an increased current can be supplied to the resonant clock network, resulting in decreased rise time or increased clock amplitude. Conversely, by decreasing the size of the resonant clock driver, the current supplied to the resonant clock network decreases, resulting in increased rise time, or decreased clock amplitude. This control function is accomplished by adjustments that can occur at a centralized location within the resonant clock driver. Moreover, it can be accomplished without requiring a separate supply network for the driver. Note that in systems like that shown in  FIG. 5 , where multiple resonant clock drivers are employed, each resonant clock driver may have its driver size adjusted independently, in order to accommodate variation in the clock load presented by the local part of the overall clock network. 
       FIG. 7  shows another aspect of the proposed approach. In particular, the duty cycle of the reference clock signal (time at high level divided by clock period) can determine the amount of energy supplied to the resonant clock network, thus affecting the rise time or the amplitude of the clock waveform. By adjusting the duty cycle of the reference clock signal separately for the pull-up and for the pull-down drivers, it is possible to control rise time and amplitude from the centralized location of the resonant clock driver. As in the case of diver size adjustment, systems like that shown in  FIG. 5 , where multiple resonant clock drivers are employed, each resonant clock driver may have the duty cycle of its reference clock adjusted independently, in order to accommodate variation in the clock load presented by the local part of the overall clock network. In general, the reference clock may have an arbitrary duty cycle P&lt;1. The duty cycles Dn (time at high level divided by clock period) and Dp (time at low level divided by clock period) of the two derivative reference clocks are determined so that the amount of energy injected into the resonant clock network each clock cycle is sufficient to accommodate variation in the local clock load or meet a target clock rise and/or fall time, or a target clock amplitude. In general, the derivative reference clocks may have arbitrary duty cycles Dn and Dp that are not necessarily equal to each other. The programmable duty cycle adjustment box generates the two reference clocks with adjusted duty cycles Dn and Dp in accordance with the values of the control bits DC 1 , . . . , DCm. 
       FIG. 8  shows a preferred embodiment for a resonant clock driver that can be used to control the characteristics of a clock waveform through adjustment of the final driver size or through adjustment of the duty cycle of the reference clocks that drive the pull-up and pull-down devices in the driver. 
       FIG. 9  shows a preferred embodiment for a resonant clock driver in the proposed architecture for controlling the characteristics of the resonant clock waveform by adjusting the size of the drivers and the duty cycle of the reference clocks, but where the sizes and duty cycles of the reference clocks are independently adjusted for multiple sub-drivers, to account for variations in load over the resonant-clock distribution network. 
     Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense (i.e., to say, in the sense of “including, but not limited to”), as opposed to an exclusive or exhaustive sense. As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements. Such a coupling or connection between the elements can be physical, logical, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
     The above Detailed Description of examples of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific examples for the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. While processes or blocks are presented in a given order in this application, alternative implementations may perform routines having steps performed in a different order, or employ systems having blocks in a different order. Some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified to provide alternative or sub-combinations. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed or implemented in parallel, or may be performed at different times. Further any specific numbers noted herein are only examples. It is understood that alternative implementations may employ differing values or ranges. 
     The various illustrations and teachings provided herein can also be applied to systems other than the system described above. The elements and acts of the various examples described above can be combined to provide further implementations of the invention. 
     Any patents and applications and other references noted above, including any that may be listed in accompanying filing papers, are incorporated herein by reference. Aspects of the invention can be modified, if necessary, to employ the systems, functions, and concepts included in such references to provide further implementations of the invention. 
     These and other changes can be made to the invention in light of the above Detailed Description. While the above description describes certain examples of the invention, and describes the best mode contemplated, no matter how detailed the above appears in text, the invention can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the invention disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the invention with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification, unless the above Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the invention encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the invention under the claims. 
     While certain aspects of the invention are presented below in certain claim forms, the applicant contemplates the various aspects of the invention in any number of claim forms. For example, while only one aspect of the invention is recited as a means-plus-function claim under 35 U.S.C. §112, sixth paragraph, other aspects may likewise be embodied as a means-plus-function claim, or in other forms, such as being embodied in a computer-readable medium. (Any claims intended to be treated under 35 U.S.C. §112, ¶ 6 will begin with the words “means for.”) Accordingly, the applicant reserves the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the invention.