Abstract:
A neural network device includes internal data input lines, internal data output lines, coupling elements provided at the connections of the internal data input lines and the internal data output lines. The coupling elements couple, with specific programmable coupling strengths, the associated internal data input lines to the associated internal data output lines. In a program mode, the internal data output lines serve as signal lines for transmitting the coupling strength information. Each of the coupling elements includes storage elements, circuitry for writing a signal potential on an associated internal data output line, and circuitry for supplying a stored signal for a storage element into an associated internal data output line.

Description:
This application is a division of application Ser. No. 07/605,708 filed Oct. 30, 1990, and allowed Jun. 11, 1993, now U.S. Pat. No. 5,274,746, issued Dec. 28, 1993. 
    
    
     CROSS REFERENCE 
     This application is also related to copending application U.S. Pat. No. 5,202,956, and its divisional application, Ser. No. 08/005,454, filed Jan. 19, 1993 under the name of the same inventor, K. Mashiko, and assigned to the same applicant, Mitsubishi Denki. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to semiconductor neural networks, and more particularly, to coupling elements which couple with specific coupling strengths (synapse loads) internal data input lines to internal data output lines, and to improvements of a neural network driving method. 
     2. Description of Background Art 
     In recent years, a variety of circuits modeled on a neuron of a human being has been contrived. Among such neuron models, there is one called a Hopfield&#39;s model. This Hopfield&#39;s model will be briefly described below. 
     In FIG. 1, there is shown a schematic structure of a unit modeled on a neuron. A unit i comprises an input portion A for receiving signals from other units k, j, and the like, a converting portion B for converting applied input signals according to a certain rule, and an output portion C for outputting the conversion results. The input portion A has a weight (synapse load) W for each input unit which indicates a coupling strength between the units. Therefore, an input signal Sk from the unit k is loaded with a weight Wik at the input portion A before transmitted to the converting portion B. This weight Wik can take any of positive and negative values or 0. 
     The converting portion B make a total sum &#34;net&#34; of inputs S that have been loaded with the weights W (when generically termed, the weight is referred to as &#34;W&#34; hereinafter) undergo a predetermined function f for output. Output Si from the unit i at the time t is given as: ##EQU1## As the function f, a threshold function shown in FIG. 2A or a sigmoid function shown in FIG. 2B is often used. 
     The threshold function shown in FIG. 2A is a unit step function having characteristics that when the total sum &#34;net (i)&#34; of inputs becomes larger than a threshold value θ, &#34;1&#34; is output, and when it does reach the threshold value, &#34;0&#34; is output. 
     The sigmoid function shown in FIG. 2B is a non-linear monotonously increasing function and given by the following expression: 
     
         f=1/[1+exp (-net (i))]. 
    
     The range of values of the sigmoid function is from 0 to 1. Therefore, as the total sum &#34;net (i)&#34; of inputs becomes smaller, the output approaches to &#34;0&#34;, and as the total sum &#34;net (i)&#34; of inputs becomes larger, the output approaches to &#34;1&#34;. When the total sum &#34;net (i)&#34; of inputs is &#34;0&#34;, this sigmoid function outputs &#34;0.5&#34;. 
     Another function obtained by adding a predetermined threshold value θ to the above-mentioned sigmoid function, as given by the following expression, may be employed. 
     
         f=1/[1+exp (-net (i)+θ)] 
    
     The unit model above is modeled on a vital cell which receives stimuli from other neurons and fires when a total sum of the stimuli exceeds a certain value. The Hopfield&#39;s model provides an operational model to a network configured of a plurality of such neuron units. 
     In the expressions above, when one neuron is initialized, state of all the remaining neuron units is determined in principal by applying the above-mentioned two dynamic equations to each neuron unit and solving them simultaneously. When the number of units increases, however, it is almost impossible to investigate and catch hold of state of one unit after another, and to program weights and bias values such that an optimal solution can be provided for a target problem. Therefore, Hopfield has introduced, in place of state of each unit, an energy function E as a quantity for representing entire characteristics of a neural net, which is defined as follows. ##EQU2## In the expression above, Ii is a self-bias value specific to the unit i. Hopfield has demonstrated that when the weight (synapse load) Wij has a symmetry shown as Wij=Wji, each unit changes its own state such that the above-mentioned energy function E always takes minimum values (more correctly, local minima), and proposed that this model be applied to programming of the weight Wij. A model according to the energy function E as described above is called a Hopfield&#39;s model. The expression above are often restated for a discrete model as: ##EQU3## 
     In the expression above, n is a discrete time. Hopfield himself has demonstrated that the Hopfield&#39;s model above can work with good accuracy especially when the function f indicating input/output characteristics has a steep gradient (which is approximate to a unit step function in which most of the outputs take values close to either &#34;0&#34; or &#34;1&#34;). 
     Neural networks have been configured according to this Hopfield&#39;s model in VLSI (Very Large Scale Integration) technology. An example of such a neural network is disclosed in &#34;Computer&#34;, March, 1988, pp. 41 to 49, published by IEEE (Institute of Electrical and Electronics Engineers), or in &#34;A CMOS Associative Memory Chip Based on Neural Network&#34;, by H. P. Graf in &#34;87 ISSCC, Digest of Technical Papers&#34;, 1987 February, pp. 304 to 305, published by IEEE. 
     In FIG. 3, there is shown the entire schematic structure of a conventional integrated neural network circuit disclosed in the documents above. Referring to FIG. 3, the conventional integrated neural network circuit comprises a resistive matrix 100 having resistive coupling elements with predetermined weights arranged in a matrix, and an amplifying circuit 101 for amplifying potentials on internal data input lines included in the resistive matrix 100 and feeding back those amplified signals to the input portions of the respective resistive coupling elements. The resistive matrix 100 comprises the internal data input lines and internal data output lines arranged in a direction orthogonally intersecting the internal data input lines, as will be described in detail later. Interconnections between the internal data input lines and the internal data output lines made through the resistive coupling elements can be programmed by programming resistance values of the resistive coupling elements. 
     To select resistive coupling elements contained in the resistive matrix 100, there are provided a row decoder 102 and a bit decoder 103. The row decoder 102 selects one row of coupling elements in the resistive matrix 100. The bit decoder 103 selects one column of coupling elements in the resistive matrix 100. 
     To write coupling strength information in the resistive coupling elements selected by the row decoder 102 and the bit decoder 103, there are provided an input/output data register 104 for temporarily latching applied data, a multiplexer 105 for connecting the input/output data register 104, according to write/read mode of the data, to either the internal data input lines or the internal data output lines in the resistive matrix 100, an interface (I/O) 106 for connecting the input/output data register 104 to the outside of the device. This neural network is integrated on a semiconductor chip 200. 
     The row decoder 102 and the bit decoder 103 select a single resistive coupling element, to which information of coupling strength is written in through the input/output data register 104 and the multiplexer 105. Thus, states of the respective coupling elements contained in the resistive matrix 100 are determined, or interconnection states of the internal data input lines and the internal data output lines can be programmed in this manner. 
     FIG. 4 shows more specifically an example of structure of the resistive matrix 100 shown in FIG. 3. Referring to FIG. 4, the resistive matrix 100 comprises internal data input lines A1 to A4 and internal data output lines B1 and B1, B2 and B2, B3 and B3, and B4 and B4. At the connections between the internal data input lines A1 to A4 and the internal data output lines B1 and B1 to B4 and B4, there are provided resistive coupling elements 1. Each coupling element 1 can take three states; &#34;open state&#34;, &#34;excitatory state&#34; and &#34;inhibitory state&#34;. The state of each resistive coupling element 1 can be externally programmed according to an applied problem. Though in FIG. 4, those resistive coupling elements 1 that are in the open state are not shown, all the connections between the internal data input lines and the internal data output lines are provided with the resistive coupling elements 1. Each resistive coupling element 1 transmits, according to its own programmed state, signal potential level on the corresponding internal data output line Bi (Bi) onto the corresponding internal data input line Aj. 
     For the internal input lines A1 to A4, there are provided amplifying circuits C1 to C4 for amplifying signal potentials on the corresponding internal data input lines and transmitting the amplified potentials to the corresponding internal data output lines. Each of the amplifying circuits C1 to C4 has two inverting amplifiers 2a and 2b connected in series. The inverting amplifier 2a inverts potential on the input line Ai and transmits the inverted potential onto the internal data output line Bi. The inverting amplifier 2b transmits the signal potential on the input line Ai onto the complementary internal data output line Bi. 
     Each of the resistive coupling elements 1 couples output of one amplifier Ci to input of another amplifier Cj. A specific structure of the resistive coupling element 1 is shown in FIG. 5. 
     Referring to FIG. 5, the resistive coupling element 1 comprises current limiting resistive elements R+ and R-, random access memory cells 150 and 151 for storing coupling strength information, switching elements S1 and S2 responsive to an output signal of an amplifying circuit Ci to be turned on/off, and switching elements S3 and S4 responsive to the information stored in the random access memory cells 150 and 151 to be set in the on/off state. The resistive element R+ has one terminal connected to a supply potential V DD . The resistive element R- has one terminal connected to another supply potential (for example, ground potential) V SS . The switching element Sl is controlled by output of an inverting amplifier 2b for its on/off. The switching element S2 is turned on/off according to the information stored in the random access memory cell 150. The switching element S3 is set in the on/off state according to the information stored in the random access memory cell 151. The switching element S4 is controlled by output of another inverting amplifier 2a for its on/off. 
     In order to write information indicative of coupling strength into the random access memory cells 150 and 151, word lines WLP and WLQ and a bit line BL are provided. The random access memory cell 150 is provided at the crossing of the word line WLP and the bit line BL. The random access memory cell 151 is provided at the crossing of the word line WLQ and the bit line BL. The random access memory cell 150 stores information indicative of &#34;excitatory state&#34; and the random access memory cell 151 stores information indicative of the &#34;inhibitory state&#34;. Thus, two word lines are provided for a single coupling element. The word lines WLP and WLQ receive row select signals from the row decoder 102 shown in FIG. 3. The bit line BL is selected by the bit decoder 103 shown in FIG. 2 to receive coupling strength information. The word lines WLP and WLQ are provided in parallel with the internal data input line Ai, and the bit line BL is in parallel with the internal data output line Bi in the resistive matrix. 
     In the structure shown in FIG. 5, output of an amplifying circuit Ci does not directly supply current to a corresponding internal data input line, thereby reducing output load capacitance of the amplifying circuit Ci. The coupling element 1 can selectively take three states, as described above, according to the programmed states of the random access memory cells 150 and 151. That is, the &#34;excitatory state&#34; where the switching element S2 is in on the state (active state), the &#34;inhibitory state&#34; where the switching element S3 is in the on state (active state), and the &#34;open (don&#39;t care) state&#34; where both switching elements S2 and S3 are in the off state (non-active state). 
     When potential levels on output lines Bi and Bi of an amplifying circuit Ci coincide with a programmed coupling state of a certain resistive coupling element 1, current flows into a corresponding data input line Ai either from the supply potential V DD  or from the other supply potential (ground potential) V SS . When the programmed coupling state of the resistive coupling element 1 is &#34;open, no current flows through the input line Ai irrespective of output state of the amplifying circuit Ci. 
     When the above-mentioned circuit model is compared to a neuron model, the amplifying circuit Ci corresponds to a neuron body (the converting portion B in FIG. 1). The signal lines A1 to A4, and B1 to B4 and B1 to B4 correspond to the data input portion A and the data output portion C (or dendrite and axon) shown in FIG. 1, respectively. The resistive coupling element 1 corresponds to a synapse loading portion which provides weighting between neurons. Now, operation of the resistive matrix will be briefly described. 
     The model shown in FIG. 4 is often called a connectionists&#39; model. In this model, each neuron unit (amplifying circuit Ci) simply performs thresholding of an input signal, or outputs a signal corresponding to magnitude of the input signal compared with a predetermined threashold value. Each resistive coupling element couples output of one amplifying circuit Ci to input to another amplifier circuit Cj. Therefore, state of each amplifying circuit Ci is determined by states of all the remaining circuits Cj (i≠j). When a certain amplifying circuit Ci detects current on the corresponding input line Ai (i=1 to 4), output of the amplifying circuit Ci at that time is given as: ##EQU4## In the expression above, Vin (j), and Vout (j) represent input and output voltages, respectively, of the amplifying circuit Cj connected to an internal data input line Aj, Ij represents current flowing through a single resistive coupling element, Wij represents conductance of a resistive coupling element which couples the amplifying circuit Ci connected to the internal data input line Ai to the amplifying circuit Cj conected to the internal data input line Aj. The output voltage Vout of the amplifying circuit Ci is determined by transfer characteristics of the amplifying circuit Ci itself. The voltage applied to the amplifying circuit Ci from the input line Ai is given by a total sum of currents flowing into the input line Ai. This input voltage is adjusted such that the total current flowing in this network becomes 0. In such state, the total energy of the neural network reaches local minima. 
     Each of the amplifying circuits Ci is constituted of, for example, a CMOS inverter. When the CMOS inverter has a high input impedance and a non-linear monotonously increasing threshold function as described above, the following relational expression can be obtained from the above-described condition that the total current becomes 0. ##EQU5## In the expression above, Iij represents current flowing through the resistors of a resistive coupling element controlled by output of the amplifying circuit Ci connected to the input line Ai. ΔVij is a potential difference at the resistive coupling element and given by: ##EQU6## Rij represents resistance of the resistive coupling element and is given by R+ or R-. Therefore, the voltage Vin (i) is a total sum of all the outputs of the amplifying circuits connected to the data input line Ai. 
     The above-mentioned operation is analogical computation. This analogical computation is performed at a time in parallel in the resistive matrix 100. However, both input data and output data are digital data. Subsequently, a practical computing operation will be described with reference to FIG. 4. 
     Input data is applied to the respective internal data input lines A1 to A4 through a register 104. The respective internal data input lines A1 to A4 are charged to potential levels corresponding to the input data and thus the neural network is initialized. 
     Output potentials of the amplifying circuits C1 to C4 change according to charging potentials applied to the data input lines A1 to A4. These potential changes of the respective amplifying circuits C1 to C4, or potential changes on the internal data output lines are fed back to the internal data input lines A1 to A4 through the corresponding resistive coupling elements. The potential levels, or current values fed back to the internal data input lines A1 to A4 are defined by the programmed states of the respective resistive coupling elements. More specifically, when a resistive coupling element has been programmed to be in the &#34;excitatory state&#34;, current flows from the supply potential V DD  to a data input line Ai. On the other hand, when the resistive coupling element has been programmed to be in the &#34;inhibitory state&#34;, current flows from the supply potential V SS  to the data input line Ai. Such operations proceed in parallel except for those resistive coupling elements that have been set in the open state. Thus, currents flowing into the data input line Ai are analogically added together, causing a potential change on the data input line Ai. When the changed potential on the data input line Ai goes over a threshold voltage of the corresponding amplifying circuit Ci, output potential of this amplifying circuit Ci changes. By repeating such operation, output potential of each amplifying circuit Ci changes to meet the above-mentioned condition that the total sum of currents becomes 0, until the network settles in a state satisfying the above-described expression of the stable state. 
     After this neural network has been stabilized, the output voltage of the amplifying circuit Ci is stored in a register (the input/output register 104 shown in FIG. 3) and then read out. A determination as to whether the network has been stabilized or not is made, depending on whether or not a predetermined time has passed since the data input or by directly comparing succeeding output data stored in the output register and detecting difference therebetween in terms of time. In the latter case, it is determined that the network has been stabilized when differences between the compared output data get smaller than a predetermined value, and then output data is provided. 
     This neural network outputs such output data as allowing energy of the neural network to settle in minimum values (or local minima). Thus, according to the programmed states of the resistive coupling elements, the resistive matrix 100 stores some patterns or data and can determine match/mismatch between input data and the stored pattern or data. Therefore, such a neural network can also serve as an associative memory circuit or a pattern discriminator. 
     A structure obtained by removing the feedback paths between the internal data output lines Bi and Bi and the internal data input lines Aj in the resistive matrix 100 shown in FIG. 4 has been known as a perception circuit of a single layer. This perceptron circuit can have a simplified learning algorithm, and when multi-layered, a flexible system can be implemented. 
     FIG. 6 shows a specific example of a possible structure of the coupling element shown in FIG. 5. In FIG. 6, there is shown structure of a coupling element Tij disposed at a location of i row and j column in the resistive matrix, or at the connection of an internal data input line Ai and an internal data output line Bj, and the parts equivalent or corresponding to those in the conceptual structure of the coupling element shown in FIG. 5 are denoted by the same reference numerals. 
     In FIG. 6, each of the switching elements S1 to S4 is constituted of an insulated gate field effect transistor (MIS transistor). The internal data input line is formed of complementary signal lines Ai and Ai. Data complementary to each other are transmitted from the input register (see FIG. 3) onto these paired complementary signal lines. 
     The bit line BL is constituted of a complementary bit line pair of BLj and BLj receiving complementary data. 
     The random access memory cell(RAM1) 150 comprises two inverting amplifiers IN1 and IN2 for storing coupling strength information that are anti-parallel to each other, or cross-coupled with the input portion of one amplifier connected to the output portion of the other, and MIS transistors TR1 and TR2 responsive to a signal potential on the word line WLiP for being turned on to connect the input portions of the inverting amplifiers IN1 and IN2 to the bit lines BLj and BLj, respectively. The inverting amplifiers IN1 and IN2 constitute a latch circuit which stores coupling strength information. The information latched by the latch circuit is transmitted through a node N1 to the control electrode (gate electrode) of the switching element(MIS transistor) S2. 
     Likewise, the random access memory cell(RAM2) 151 comprises inverting amplifiers IN3 and IN4 constituting a latch circuit, and MIS transistors TR3 and TR4 responsive to a signal potential on the word line WLiQ for being turned on to connect the input portions of the inverting amplifiers IN3 and IN4 to the bit lines BLj and BLj, respectively. The information stored in the latch circuit constituted of the inverting amplifiers IN3 and IN4 is applied through a node N2 to the control electrode (gate electrode) of the switching element(MIS transistor) S3. In the following, operation of writing the coupling strength information into this coupling element Tij will be briefly described. 
     When the word line WLiP is selected by the row decoder 102 (see FIG. 3), the MIS transistors TR1 and TR2 are turned on together, connecting the input portions of the inverting amplifier IN1 and IN2 to the bit lines BLj and BLj, respectively. Subsequently, data of &#34;0&#34; and &#34;1&#34; are transmitted onto the bit line BLj and its complementary bit line BLj, respectively. Then, due to the latching function of the cross-coupled or anti-parallel inverting amplifiers IN1 and IN2, data of &#34;1&#34; is stored at the node N1. Thus, the &#34;excitatory state&#34; of the coupling element Tij is programmed. 
     When this coupling element Tij is to be programmed in the &#34;inhibitory state&#34;, the word line WLiQ is selected and data of &#34;0&#34; and &#34;1&#34; are transmitted onto the bit line BLj and the complementary bit line BLj, respectively. Due to the latching function of the cross-coupled inverting amplifiers IN3 and IN4, data of &#34;1&#34; is latched at the node N2. When the coupling element Tij is to be programmed to take the &#34;open state&#34;, the word lines WLiP and WLiQ are sequentially selected and data of &#34;1&#34; and &#34;0&#34; are transmitted onto the bit line BLj and the complementary bit line BLj, respectively. As a result, data of &#34;0&#34; are latched at the nodes N1 and N2. Meanwhile, information of &#34;1&#34; represents an &#34;H&#34;-level signal and information of &#34;0&#34; represents an &#34;L&#34;-level signal. 
     While the coupling element shown in FIG. 6 is configured such that signal potentials on the internal data input lines are transmitted to the internal data output lines, the structure becomes equivalent to that of the coupling element shown in FIG. 5 if it is adapted such that signals on the internal data output lines Bj are fed back to the internal data input lines Ai (Ai). 
     FIG. 7 shows the entire structure of a neural network obtained by arranging the coupling elements as shown in FIG. 6 in a matrix of 4 rows and 4 columns. 
     In FIG. 7, in order to write coupling strength information into the coupling elements, there are provided a RAM I/O 106b serving as interface for transmitting and receiving data to and from outside of the device, selective gates 111 responsive to a column select signal (column decode signal) from the bit decoder 103 for connecting the selected column to internal data buses I/O and I/O, data registers 104 provided corresponding to the respective columns for amplifying and latching the applied data, and transfer gates 112 responsive to an operation mode indicating signal MUX for connecting the data registers 104 to the resistive matrix 100. 
     A column select line is formed of a complementary bit line pair of BL and BL and, therefore, the selective gates 111 and the transfer gates 112 comprise one pair of MIS transistors for each column. Among the MIS transistor pairs contained in the selective gates 111, one pair of MIS transistors are rendered conductive in response to the column select signal from the bit recorder 103. The transfer gates 112 are rendered conductive in a program mode where information of coupling strength is written in the respective coupling elements of the resistive matrix 100, and turned off in a practical processing operation where input data to be processed by the neural network is externally applied. 
     The RAM I/O 106b transmits a complementary data pair to the internal data buses I/O and I/O. 
     Word lines WL1P to WL4P and WL1Q to WL4Q are connected to the output portion of the row decoder 102 to receive a row select signal from the row decoder 102. 
     An input register 106a, which corresponds to the input/output register in FIG. 3 or the data input portion of an interface, has its output portion connected to complementary internal input data line pairs of A1 and A1 to A4 and A4 for transmitting complementary input signals (input data signals to be processed). 
     Amplifying circuits 101 are provided corresponding to the respective internal data output lines B1 to B4 to amplify signal potentials thereon. 
     In writing the information of coupling strength, the signal MUX attains the &#34;H&#34; level indicative of the active state so that the transfer gates 112 are rendered conductive. Subsequently, the row decoder 102 and the bit decoder 103 select one row and one column, respectively, and then desired information is written in the storage elements of the coupling element located at the connection of the selected row and column. At this time, the data register 104 latches the complementary data transmitted to the bit lines BL and BL and at the same time, the data are written in the coupling elements. Though each storage element has a latch circuit constituted of cross-coupled inverters, the data register 104 has a larger driving capability than the latching capability of the storage elements. Therefore, desired coupling strength information is written in the respective coupling elements. 
     In operation, the signal MUX falls to the &#34;L&#34; level indicative of the &#34;inactive state&#34;, the transfer gates 112 are turned off. Subsequently, a neuron input signal, which has been applied from outside of the chip and temporarily stored in the input register 106A, is transmitted to the internal data input lines Ai and Ai as an input signal to be processed in the resistive matrix 100. In the resistive matrix 100, according to the combination of the information stored in the RAM1 and RAM2 contained in the respective coupling elements Tij, charging and discharging operations are performed for the internal data output lines Bi in parallel. Voltage values on the internal data output lines Bi are detected and amplified by the amplifying circuits 101 and the results are developed as output signals. 
     In the structure above, a non-Hopfield&#39;s type neural network has been described where paths for feeding back signal voltages on the internal data signal lines to the resistive matrix are not provided. However, also a Hopfield&#39;s type neural network can be configured in the same manner if only paths for feeding back the internal data output lines Bi to the internal data input lines Ai and Ai are added to the above-described structure. 
     A conventional coupling element comprises storage element portions for storing coupling strength information and a current supplying element portion responsive to the information stored in the storage element portions and a signal potential on an internal data input line (or internal data output line) for transmitting a predetermined current to an internal data output line (or internal data input line). Therefore, as the number of elements constituting a coupling element increases with its structure getting more complicated, the area occupied by the coupling element becomes larger. 
     Further, since the word lines and the bit lines for writing coupling strength information in the storage element portions and the internal data input lines and the internal data output lines for transferring data to be processed are provided individually, a large number of signal lines are required, occupying a large area. Furthermore, since the large number of signal lines have to be provided in a small area, layout of the signal lines becomes complicated, resulting in a significant obstacle in achieving higher integration. Thus, the provision of a large number of signal lines, combined with complicity of the structure of coupling element, brings about disadvantages also in terms of production yield. 
     Additionally, in the conventional semiconductor neural networks, the input data signal continues to be applied for a significant time to sufficiently charge or discharge the internal data inputs lines to the &#34;H&#34; or &#34;L&#34; level, so that when the internal data input lines and the internal data output lines are charged or discharged in operation, potential of each signal line may make a full-swing. As a result, the consumption power becomes large and fast operability can not be achieved, while taking a longer processing time (or convergence time). 
     A structure of synapse load expressive unit is disclosed in &#34;A Neuromorphic VLSI Learning System&#34; by J. Alspector et al, pp. 323 to 325 in &#34;Advanced Research in VLSI, 1987&#34; published by MIT Press, where an input signal and an output signal of neurons are coupled together through a transistor which is turned on/off under control of a flip-flop storing a synapse coupling strength. 
     SUMMARY OF THE INVENTION 
     An object of the present invention is to provide an improved semiconductor neural network from which disadvantages of the conventional semiconductor neural networks as described above have been eliminated. 
     Another object of the present invention is to provide a semiconductor neural network which comprises coupling elements of a simple structure. 
     Still another object of the present invention is to provide a semiconductor neural network whose resistive matrix has a reduced number of signal lines. 
     A further object of the present invention is to provide a semiconductor neural network operable at a high speed and with low consumption power, and a driving method thereof. 
     A semiconductor neural network according to the present invention comprises a plurality of internal data input lines, a plurality of internal data output lines, a plurality of word lines, bit lines shared with the internal data output lines, and coupling elements provided at the connections of the bit lines and the word lines. 
     A coupling element comprises storage means constituted of cross-coupled or anti-parallel inverting amplifiers for storing information indicative of a specific coupling strength, means responsive to a signal potential on a corresponding word line for being rendered conductive to write a signal potential on a corresponding bit line (internal data output line) in the storage means, and means responsive to a signal potential on a corresponding internal data input line for being rendered conductive to transmit the information stored in the storage means onto a corresponding internal data output line (bit line). 
     The coupling element has first and second storage means. 
     The bit lines have a structure constituted of complementary bit line pairs and thus also the internal data output lines have a structure constituted of complementary internal data output line pairs. The information stored in the first storage means is transmitted onto first internal data output lines of the complementary internal data output line pairs, and the information stored in the second storage means is transmitted onto second internal data output lines (second bit lines) of the bit line pairs (internal data output line pairs). 
     The semiconductor neural network according to the present invention further preferably comprises means for detecting a time of change of an externally applied input data signal, converting, in response to a detection signal, the externally applied input data signal into a one-shot pulse signal and transmitting the converted signal onto the internal data input lines. 
     The semiconductor neural network according to the present invention further preferably comprises means responsive to the signal detecting a change of the externally applied input data for equalizing potentials on the internal data output lines, and means responsive to the signal detecting a change of the input data signal for activating sense amplifiers provided to the internal data output lines. 
     As previously described, since the same signal lines are shared by the bit lines and the internal data output lines, a reduction in the number of signal lines becomes possible. For the coupling elements, since the information stored in the storage means is transmitted to the internal data output lines in response to signal potentials on the internal data input lines, the number of elements constituting a coupling element can be reduced. Thus, coupling elements occupying only a small area can be obtained. 
     Further, since in a coupling element, one out of the two storage means is connected to a positive internal data output line and the other storage means has its storage node connected to a negative bit line (internal data output line), a device structure where commonly use of the bit line pairs and the internal data output line pairs is realized can be obtained. 
     Furthermore, by converting the internal input data signal into a one-shot pulse signal, the full-swing of potentials on the internal signal lines can be prevented. As a result, low power consumption and fast operability can be achieved, while preventing inversion of the storage information in the storage elements constituted of inverting amplifiers. Thus, stable operation of the storage elements in the coupling elements is assured. 
     Furthermore, by equalizing potentials on the internal data output line pairs and activating the sense amplifiers in response to a change of the internal input data signal, low power consumption as well as fast operability can be achieved. 
     The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is diagram showing a neuron model. 
     FIGS. 2A and 2B are diagrams showing examples of threshold function of a neuron. 
     FIG. 3 is a diagram showing conceptual structure of a conventional semiconductor neural network chip. 
     FIG. 4 is a diagram showing conceptual structure of the major part of a conventional semiconductor neural network chip. 
     FIG. 5 is a diagram schematically showing structure of a basic synapse coupling element of the neural network shown in FIG. 4. 
     FIG. 6 is a diagram showing a specific structure of the basic synapse coupling element shown in FIG. 5. 
     FIG. 7 is a diagram showing structure of a conventional semiconductor neural network chip using the basic synapse coupling elements as shown in FIG. 6. 
     FIG. 8 is a diagram schematically showing the entire structure of a semiconductor neural network chip using the coupling elements as shown in FIG. 9. 
     FIG. 9 is a diagram showing structure of a coupling element used in a semiconductor neural network according to an embodiment of the present invention. 
     FIG. 10 is a signal waveform chart showing operation of the semiconductor neural network shown in FIGS. 8 and 9. 
     FIG. 11 is a diagram showing structure of a coupling element according to another embodiment of the present invention. 
     FIG. 12 is a diagram showing structure of a coupling element according to still another embodiment of the present invention. 
     FIG. 13 is a diagram showing the entire structure of a semiconductor neural network using the coupling elements as shown in FIG. 12. 
     FIG. 14 is a diagram schematically showing the entire structure of a semiconductor neural network chip which has a feedback circuit using the coupling elements as shown in FIG. 9. 
     FIG. 15 is a diagram schematically showing structure of a Hopfield&#39;s type semiconductor neural network using the coupling elements as shown in FIG. 12. 
     FIG. 16 is a diagram showing an example of structure of an inverting amplifier circuit constituting the storage element contained in a coupling element. 
     FIG. 17 is a diagram showing another structure of inverting amplifier circuit constituting the storage element contained in a coupling element. 
     FIG. 18 is a diagram showing a circuit structure for generating internal operation control signals in a semiconductor neural network, according to an embodiment of the present invention. 
     FIG. 19 is a signal waveform chart showing operation of the circuit shown in FIG. 18. 
     FIG. 20 is a diagram showing a circuit structure for generating other internal signals in a semiconductor neural network, according to the present invention. 
     FIG. 21 is a signal waveform chart showing operation of the circuit shown in FIG. 20. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 8 shows schematically the entire structure of a semiconductor neural network according to an embodiment of the present invention. The structure shown in FIG. 8 corresponds to that of the conventional semiconductor neural network shown in FIG. 7, and the same or equivalent parts are denoted by the same reference numerals. 
     In FIG. 8, the semiconductor neural network employs complementary bit line pairs of BL and BL also as internal data output line pairs. Output signal lines of an input register 106a are of a single line structure. Amplifying circuits 101 are provided corresponding to the bit line pairs and comprises amplifiers for differentially sensing and amplifying potentials on the corresponding bit line pairs. 
     Second transfer gates 115 are provided to connect the bit line pairs (internal data output line pairs) of BL1 and BL1 to BL4 and BL4 to the amplifying circuits 101 selectively according to operation modes. The second transfer gates 115 are rendered conductive in response to a connection control signal MUX. In operation modes such as learning mode, or self-organizing mode where coupling strengths of the respective coupling elements in the coupling matrix 100 are programmed, the control signal MUX falls to &#34;L&#34; to disconnect the coupling matrix 100 from the amplifying circuits 101. On the other hand, in operation modes such as recalling mode where operational processings are performed on externally applied input data signals, the control signal MUX attains the &#34;H&#34; level to connect the coupling matrix 100 to the amplifying circuits 101. That is, the first and second transfer gates 112 and 115 perform complementary operations to each other. 
     FIG. 9 shows a specific structure of the coupling element Tij shown in FIG. 8. In FIG. 9, the coupling element Tij comprises inverting amplifiers IN10 and IN11 for storing information for a complementary bit line BLj, and inverting amplifiers IN12 and IN13 for storing information for a bit line BL. The inverting amplifiers IN10 and IN11 are arranged anti-parallel with each other, or cross-coupled to each other to constitute a latch circuit. Likewise, the inverting amplifiers IN12 and IN13 are arranged anti-parallel with each other, or cross-coupled to each other to constitute another latch circuit. 
     The coupling element Tij further comprises a switching transistor S5 responsive to a signal potential on the word line WLiP for being turned on to connect a node N3 to the bit line BLj, a switching transistor S6 responsive to a signal potential on the word line WLiP for being turned on to connect another node N1 to the complementary bit line BLj, and a switching transistor S7 responsive to a signal potential on the internal data input line Ai for being turned on to connect the node N1 to the complementary bit line BLj. The coupling strength information stored in the latch circuit constituted of the inverting amplifiers IN10 and IN11 is transmitted to the complementary bit line BLj in response to the signal potential on the data input line Ai. 
     The coupling element Tij further comprises switching transistors S9 and S10 responsive to a signal potential on the word line WLiQ to connect nodes N2 and N4 to the bit line BLj and the complementary bit line BLj, respectively, and a switching transistor S8 responsive to the signal potential on the internal data input line Ai to connect the node N2 to the bit line BLj. The coupling strength information stored in the storage circuit portion constituted of the inventing amplifiers IN12 and IN13 is transmitted onto the bit line BLj in response to the signal potential on the internal data input line Ai. 
     The coupling state of the coupling element Tij is determined according to the combination of signal potentials stored at the storage nodes N1 and N2. When signal potentials of the &#34;L&#34; and the &#34;H&#34; levels have been stored at the nodes N1 and N2, respectively, the coupling element Tij indicates the &#34;excitatory state&#34;. When potentials of the same level have been stored at the storage nodes N1 and N2, no potential difference appears on the bit line pair of BLj and BLj so that the coupling element Tij indicates the &#34;don&#39;t care (open) state&#34;. When signal potentials of the &#34;H&#34; and &#34;L&#34; levels have been stored at the nodes N1 and N2, respectively, the coupling element Tij has been programmed to indicate the &#34;inhibitory state&#34;. 
     In the following, operation of the neural network shown in FIGS. 8 and 9 will be described with reference to the operation waveform chart of FIG. 10. 
     When the control signal MUX is set to the &#34;H&#34; level and the complementary control signal MUX is set to the &#34;L&#34; level, the semiconductor neural network is put in an operation mode where coupling strength data are written in or read out of the respective coupling elements contained in the coupling matrix 100. The control signal MUX determines a period for which storage contents in the storage elements are rewritten to change weighting of the synapse couplings in the self-organizing process, or learning. 
     When the control signal MUX attains &#34;H&#34;, the first transfer gates 112 are rendered conductive so that the data register 104 is connected to the coupling matrix 100. 
     Subsequently, a row address and a column address are externally applied to the row detector 102 and the bit decoder 103, respectively, to select a corresponding word line (WLiP or WLiQ) and a corresponding bit line pair of BLj and BLj. Meanwhile, the RAM I/O 106b converts externally applied information of coupling strength Din into a complementary data pair and transmits the converted data to the internal data buses I/O and I/O. The complementary data pair transmitted to the internal data buses I/O and I/O is transmitted through a selective gate (one pair of transistors contained in the gates 111) selected by the bit decoder 103 to a corresponding data register to be latched therein. 
     The switching transistors S5 and S6 associated with the selected word line (for example, WLiP) are turned on, connecting the latch circuits constituted of the inverting amplifier circuits to the bit line pairs of BLj and BLj. As a result, the data latched in the data register is transmitted through the switching transistors S5 and S6 to the storage nodes N1 and N3 to be latched therein. Meanwhile, the driving capability of the data register 104 is of course larger than the latching capability of the inverting amplifier circuit of IN10 and IN11 (IN12 and IN13). Therefore, it is possible to write signal potentials indicative of desired coupling strength information into the storage nodes N1 and N3. 
     When the word line WLiQ has been selected, information indicative of a desired coupling strength is written in the latch circuit constituted of the inverting amplifiers IN12 and IN13 so that signal potentials corresponding to the coupling strength information are stored in the nodes N2 and N4, respectively. By performing the above-described operation for the respective storage elements of the coupling elements T11 to T44 in the coupling matrix 100, information of coupling strengths can be programmed in the coupling matrix 100. This writing of the coupling strength information into the coupling matrix 100 is similar to the data writing operation in a general static random access memory. 
     Subsequently, when the control signal MUX falls to the &#34;L&#34; level and the complementary control signal MUX attains the &#34;H&#34; level, the first transfer gates 112 are put in the non-conductive state and the second transfer gates 115 are rendered conductive, putting the neural network in an operation mode specific to the neural network. An external data signal applied from outside of the neural network chip 200 is first held by the input register 106a and then the thus held external data signal is transmitted from the input register 106a to the internal data signal lines A1 to A4 as an internal data signal. In this operation mode, all the output potentials of the row decoder 102 are fixed at the &#34;L&#34; level so that all the switching transistors S5, S6, S9 and S10 (see FIG. 9) contained in the coupling elements are in the off-state. 
     Now, when the signal potential on the internal data input line Ai rises to the &#34;H&#34; level in response to the internal data signal, the switching transistors S7 and S8 of the coupling element Tij are turned on so that the signal potentials stored in the coupling element Tij are transmitted to the bit line pair (internal data output line pair) of BLj and BLj. When the coupling element Tij has been programmed to be in the &#34;excitatory state&#34;, the bit line BLj receives a signal potential of the &#34;H&#34; level and the complementary bit line BLj receives a signal potential of the &#34;L&#34; level. When the coupling element Tij has been programmed to be in the &#34;inhibitory state&#34;, the bit lines BLj and BLj receive signal potentials of the &#34;L&#34; and &#34;H&#34; level, respectively. When the coupling element has been programmed to be in the &#34;don&#39;t care (open) state&#34;, the bit lines BLj and BLj receive potentials of the same level. 
     When the signal potential on the internal data signal line Ai is at the &#34;L&#34; level, the switching transistors S7 and S8 are in the off state. Thus, the coupling element is in a state equivalent to the &#34;don&#39;t care (open) state&#34; since no potential change occurs on the bit line pair BLj and BLj, irrespective of the storage information of the coupling element Tij. Such changes of signal potentials on the bit line pairs (internal data output line pairs), which occur according to the signal potentials on the internal data signal lines, proceeds at a time and in parallel in the respective coupling elements of the matrix 100. The signal potentials appearing on the bit line pairs of BL1 and BL1 to BL4 and BL4 as a result of the parallel operation are sensed and amplified by the amplifying circuits 101 and then converted into corresponding data signals to be output as neuron output data. 
     In the structure of coupling element shown in FIG. 9, a word line, a bit line and an internal data input line are each connected to the same number of transistors and have the same stray capacitance associated therewith. However, the number of transistors connected to the input portion of one inverting amplifier circuit is different from the number of transistors connected to the output portion of the same circuit. This leads to an imbalanced stray capacitance in one storage element portion and also to imbalanced latching capability of the latch circuit. As a result, the writing or reading operation of the coupling strength information becomes unstable, and in some cases, the coupling strength information may not be precisely stored and read out. 
     In FIG. 11, there is shown a structure of coupling element which can avoid such an unbalanced stray capacitance in the storage element portion and stabilize the operations of reading and writing the coupling strength information in the storage element portion. In the structure of coupling element shown in FIG. 11, dummy capacitors C1 and C2 are connected between the nodes N3 and N4 and the internal data input line Ai, respectively. The dummy capacitors C1 and C2 are formed by connecting conductive terminals of MIS transistors and equalize stray capacitances in the inverting amplifier circuits of IN10 and IN11, and of IN12 and IN13. In this case, the switching transistors S5, S6, S7, S8, S9 and S10 and the dummy capacitors C1 and C2 are constituted of MIS transistors of the same size. With this structure, the stray capacitances in the storage element portions can be easily balanced, making the reading and writing operations of the coupling strength information stable. 
     FIG. 12 shows a second modified structure of the coupling element shown in FIG. 9. The coupling element comprises a switching transistor S5 responsive to a signal potential on a first word line WLiP(1) for being turned on to connect the node N3 to the bit line BLj, a switching transistor S6 responsive to a signal potential on a second word line WLiP(2) for being turned on to connect the node N2 to the complementary bit line BLj, and inverting amplifiers IN10 and IN11 cross-coupled to each other between the nodes N1 and N3. The coupling element further comprises a switching transistor S9 responsive to a signal potential on a third word line WLiQ(1) for being turned on to connect the node N2 to the bit line BLj, a switching transistor S10 responsive to a signal potential on a fourth word line WLiQ(2) to connect the node N4 to the complementary bit line BLj, and inverting amplifier IN12 and IN13 cross-coupled to each other between the nodes N12 and N4. 
     The first and second word lines WLiP(1) and WLiP(2) receive the same row select signal. The third and fourth word lines WLiQ(1) and WLiQ(2) receive the same row select signal. 
     Further, the word lines WLiP(2) and WLiQ(1) are used also as an internal data input line Ai to receive the same internal data signal. 
     In the basic element structure shown in FIG. 12, the stray capacitances in the storage element portions can be balanced without providing the dummy capacitors to balance them. Furthermore, since the number of transistors constituting a basic coupling element is less, the area occupied by the coupling element can be reduced. 
     Additionally, in the basic coupling element structures shown in FIGS. 9, 11 and 12, the double-end structure is employed so that the coupling strength information is written in through both bit line BLj and its complementary bit line BLj. Instead of such structure, a single-end structure may be employed which is obtained, for example, by eliminating the switching transistors S6 and S9 from the coupling element structure shown in FIG. 9 so that information of a desired coupling strength be written in through only one of the paired bit lines. 
     FIG. 13 shows the entire structure of a semiconductor neuron network with coupling matrix 100 having coupling elements as shown in FIG. 12 arranged in 4 rows and 4 columns. In the structure shown in FIG. 13, the word lines and the internal data input lines share the same signal lines. Therefore, in addition to the structure shown in FIG. 8, there are provided connection gates 116 responsive to control signal MUX for being turned on to connect row decoder 102 to the coupling matrix 100 and connection gates 117 responsive to complementary control signal MUX to connect neuron input register 106a to the coupling matrix 100. Further, since the internal data input lines are required to correspond to the respective two storage element circuit portions of the coupling elements, two signal lines transmitting the same internal data input signal are provided as internal data input lines for a single coupling element. Furthermore, a single coupling element requires four word lines, the output signal lines of the row decoder 102, or word lines are doubled in number when compared with the structure shown in FIG. 8. For the output signal lines, or the word lines of the row decoder 102 shown in FIG. 13, word lines denoted by the same reference numeral receive the same row select signal. 
     In such a structure as shown in FIG. 13 where either the neuron input register 106a or the row decoder 102 is connected to the coupling matrix 100 according to operation modes, the word lines and the internal data input lines can share the same signal lines, as previously described. Thus, in practice, a doubled number of signal lines are not required, but the number of signal lines increases by only one for one row, so that a coupling matrix occupying a small area can be realized. 
     Meanwhile, the semiconductor neural networks shown in FIGS. 8 and 13 have non-Hopfield&#39;s type structures where oaths for feeding back the internal output data signals into the coupling matrix are not provided. However, these structures can be easily modified to constitute Hopfield&#39;s type neural networks only with the provision of the feedback paths. FIG. 14 shows an example of structure of a Hopfield&#39;s type semiconductor neural network using coupling elements according to the present invention. 
     In FIG. 14, the Hopfield&#39;s type semiconductor neural network according to the present invention comprises inverting amplifiers 120a, 120b, 120c and 120d for inverting outputs of complementary bit lines BL1, Bl2, BL3 and BL4 and transmitting the inverted outputs to internal data input lines A1, A2, A3 and A4. The inverting amplifiers 120a and 120d allow the internal data output signals from the coupling matrix 100 to be fed back through the internal data input signal lines. Thus, a neural network according to the Hopfield&#39;s model is configured. 
     FIG. 15 shows an example of structure of a Hopfield&#39;s type semiconductor neural network obtained by modifying the non-Hopfield&#39;s type semiconductor neural network shown in FIG. 13. In the semiconductor neural network shown in FIG. 15, feedback amplifying circuits 121 are provided to transmit signal potentials on the respective bit line pairs of BL1 and BL1 to BL4 and BL4 to the internal data input line pairs A1 to A4. Each of the feedback amplifying circuits 121 comprises an inverting amplifier 20a for inverting potential on a complementary bit line BLi and transmitting the inverted potential onto a corresponding internal data input line Ai, and inverting amplifiers 20b and 20c connected in series over two stages for transmitting potential on a positive bit line BLi onto another corresponding input data signal line Ai. In the structure shown in FIG. 15, the feedback paths are provided in the same manner though both the internal data input lines and the internal data output lines form pairs, so that a Hopfield&#39;s type neural network is configured. 
     FIG. 16 shows an example of structure of an inverting amplifier comprised in the storage element portion of a coupling element. In FIG. 16, an inverting amplifier circuit is formed of a complementary (CMOS) logic circuit comprising a p-channel MIS transistor PMOS and an n-channel MIS transistor NMOS. The structure shown in FIG. 16 is characterized by its large output driving capability and large noise margin. These characteristics allow the circuit to transmit precise coupling strength information onto a corresponding bit line in a reliable manner. 
     FIG. 17 shows another structure of an inverting amplifier comprised in the storage element portion of a coupling element. In the structure shown in FIG. 17, an inverting amplifier circuit is constituted of a load resistor R1 formed of, for example, polysilicon and an n-channel MIS transistor NMOS. The resistor R1 transmits a predetermined supply potential Vcc to the output portion. The n-channel MIS transistor NMOS receives an input signal IN at its gate and drives the output portion according to its gate potential. Since in the structure of inverting amplifier shown in FIG. 17, the load resistor is employed, the circuit size can be made smaller than that of the inverting amplifier shown in FIG. 16. 
     While in all the embodiments described above, it has been simply stated that in the operational processings of the neural network, the data register 104 is disconnected from the coupling matrix 104 and instead, the amplifying circuits 101 are connected to the coupling matrix 100, no reference has been made to initialization of the bit line potentials. In initializing the bit lines that are to be held in the floating state, it takes a long time in the operational processings to establish potentials on the bit lines that have been held at the levels transmitted in programming the coupling strengths of the respective coupling elements in the coupling matrix 100. On the other hand, if all the bit lines are set either to the &#34;L&#34; or &#34;H&#34; level in the initialization, it takes a long time to establish the &#34;H&#34; or &#34;L&#34; level on the bit lines. This leads to longer charging and discharging time, resulting in an increased power consumption. To overcome such disadvantages, a circuit structure which can drive the bit lines reliably at a high speed and with low power consumption is shown in FIG. 18. 
     Referring to FIG. 18, the bit line driving circuit comprises a signal change detecting circuit 701 for detecting a time of change of an external or internal input data signal Ai and generating a one-shot pulse signal (input change detecting signal) ATD having a predetermined time interval, a BLEQ generating circuit 702 responsive to the input change detecting signal ATD for generating an equalize signal BLEQ having a predetermined time interval, and an SAE generating circuit 703 responsive to the input change detecting signal ATD and the equalize signal BLEQ for generating a sense amplifier activating signal SAE. The equalize signal BLEQ from the BLEQ generating circuit 702 is transmitted to equalize transistors EQT provided to short-circuit paired bit lines. 
     The signal change detecting circuit 701 has the same structure as that of a circuit for generating an address change detecting signal which generates internal operation signals, for example, in a random access memory. The generation of the input change detecting signal ATD allows a starting point of an computing operation cycle to be reliably detected. Since it is desirable that operation timings of the circuit can be detected as early as possible, an externally applied input data signal may be preferably supplied as the input data signal Ai to the signal change detecting circuit 701. In the following, operation of the circuit shown in FIG. 18 will be described with reference to the operation waveform chart of FIG. 19. 
     When the neural network enters the operational processing mode, or recalling operation mode, the control signal MUX falls to &#34;L&#34; and the complementary control signal MUX attains the &#34;H&#34; level. As a result, the transfer gates 115 are rendered conductive, connecting the bit lines BLj and BLj to the amplifying circuits 101. Subsequently, the input signal Ai is applied and then a point of change of the input signal Ai is detected by the signal change detecting circuit 701 to generate the input change detecting signal ATD. This input change detecting signal ATD has a predetermined time interval. In response to the input change detecting signal ATD, the BLEQ generating circuit 702 is activated to generate the equalize signal BLEQ. In response to this equalize signal BLEQ, the equalize transistors EQT are rendered conductive so that potentials on the paired bit lines BLj and BLj are equalized. Meanwhile, the signal waveform chart shown in FIG. 19 shows a case where the bit line pairs of BLj and BLj are equalized at an intermediate potential between the &#34;H&#34; and &#34;L&#34; levels. This can be realized by providing the respective bit lines with transistors which are rendered conductive, in response to the equalize signal BLEQ, to precharge the bit lines to the intermediate potential. The equalize signal BLEQ is a one-shot pulse signal having a predetermined time interval. Therefore, when the generation of the pulse signal terminates, subtle potential differences appear over the bit lines BLj and BLj due to functions of the coupling elements. 
     Subsequently, when the generation of the input change detecting signal ATD and the equalize signal BLEQ terminates, the SAE generating circuit 703 is activated to generate the sense amplifier activating signal SAE. Then, the amplifying circuits 101 are activated to differentially sense and amplify the subtle differences of signal potentials on the corresponding bit line pairs of BLj and BLj and output the results as neuron output signals. Meanwhile, in the operation waveform chart shown in FIG. 19, a case is shown where the signal potentials of the bit line pairs of BLj and BLj make full-swing between the &#34;H&#34; and &#34;L&#34; levels due to functions of the sense amplifier circuits 101. However, the differences of signal potentials can be sensed and amplified for output without the potentials on the bit lines being affected by such full-swing if only current-mirror type differential amplifier circuits are employed, for example. 
     As described above, by equalizing potentials on the bit line pairs immediately after the neuron input data signal has changed, potentials changes which might be caused under the influences of noise and the like on the bit line pairs can be prevented. Accordingly, it becomes possible to shorten the time taken until effective information appears on the bit lines, so that a neural network operable at a high speed and with low power consumption can be obtained. 
     If the equalize transistors EQT for equalizing the bit line pairs have been adapted to be able to function also in programming coupling strengths of the coupling elements in the coupling matrix 100, the programming of coupling states of the coupling matrix can be performed also at a high speed. Additionally, a circuit structure for precharging the bit line pairs to the predetermined potential may be separately provided. 
     Further, if the equalize/precharge transistors are provided as described above, subtle differences of the potentials can be differentially sensed and amplified in a reliable manner. Accordingly, activation timings of the amplifying circuits can be made earlier, so that a neural network operable at a high speed can be obtained. 
     When a large scale parallel operation is performed in the coupling matrix corresponding to the internal input data signal applied for a long time, potentials on the respective bit line pairs may have full-swing. In this case, since those coupling elements whose internal input data signals are at the &#34;H&#34; level have the storage nodes of their storage elements connected to the bit lines, the contents stored in the storage elements may be rewritten by the potentials on the bit lines due to the full-swing, and further, the storage contents of the storage elements may be even destructed. A circuit structure for stabilizing the storage information in the coupling elements in shown in FIG. 20. 
     Referring to FIG. 20, the circuit structure for stabilizing the storage information in the coupling elements comprises signal change detecting circuit 710 for detecting a time of change of an externally applied input data signal Ex. Ai and generating, in response to the detected change, input change detecting signal ATD of one-shot pulse having a predetermined time interval, and gate circuits 711 and 712 which receive the input change detecting signal ACD and the externally applied input data signal Ex. Ai for generating one-shot internal input data signals Int. Ai. The gate circuits 711, 712 and the like are provided corresponding to the respective bits of the external input data signal. An operation waveform chart of the circuit structure shown in FIG. 20 is shown in FIG. 21. When the internal input data signal Ai is formed as a one-shot pulse signal using such a circuit structure as shown in FIG. 20, the time taken to perform operational processings on the internal input data signal becomes short, no longer allowing the full-swing of signal potentials on the bit line pairs of BLj and BLj even if a large scale parallel operation is performed in the coupling matrix. That is, since the operation time is short, only small potential changes occur which appear usually before full-swing. Thus, the destruction of the storage information in the coupling elements can be prevented. Further, when the input data signal is converted into a one-shot pulse signal according to the input change detecting signal ACD, the switching transistors in the coupling elements are turned off at earlier timings. This means that the coupling elements are disconnected from the bit line pairs at earlier timings, preventing the destruction of the storage contents in the coupling elements. 
     In the signal waveform chart shown in FIG. 21, the signal potentials on the bit lines BLj and BLj are equalized every time the input change detecting signal is generated, because the equalize signal as shown in FIG. 18 is generated. When such a one-shot internal input data signal as shown in FIG. 21 is employed, the amplifying circuits can differentially sense and amplify signal potentials on the bit line pairs in a reliable manner, no matter how small the potential changes on the bit lines BLj and BLj may be. Accordingly, operation performance of the neural network can not be reduced. 
     When the circuit structure shown in FIG. 20 is employed, the input change detecting signal ACD shown in FIG. 20 is applied also to BLEQ generating circuit 702 generating bit line equalize signal BLEQ and to SAE generating circuit 703 generating activation signal SAE to activate amplifying circuits. 
     In the embodiments above, a circuit structure for programming coupling strengths in the coupling matrix has been described as allowing writing of the coupling strength information for one column after another, or bit by bit, with the use of bit line decoder 103. Instead of such structure, however, shift registers may be provided over a number of stages corresponding to the number of coupling elements in one row. In this case, coupling strength information of one row is written in the shift registers and then the coupling strength information is transferred from the shift registers to one row of coupling elements at a time. 
     As has been described above, according the present invention, each of the coupling elements contained in the coupling matrix of a neural network is constituted of storage element portions comprising cross-coupled inverting amplifiers, and elements responsive to potentials on word lines for writing signal potentials on bit lines into the storage elements and also responsive to potentials on internal input data signal lines for transmitting the storage information in the storage element portions onto the bit line. Further, the signal lines for transmitting coupling strength information in the learning mode where the coupling strength information is to be written and the data lines for outputting the internal data output signals in the neural network operating mode, or recalling mode share the same lines. Accordingly, the number of interconnections in the coupling matrix and also the number of elements constituting a coupling element can be reduced, so that coupling elements which have a simple structure and occupy a small area can be provided. Thus, a highly integrated and high-density semiconductor neural network can be obtained. 
     Furthermore, since the internal input data signal is formed as a one-shot pulse signal to be transmitted into the coupling matrix, the bit line potentials do not make full-swing and the coupling elements are disconnected from the bit lines, or internal data lines at earlier timings. Accordingly, the neural network can be driven at a high speed and with low consumption power and stable operation can be assured without causing destruction of the storage information in the coupling element. 
     Furthermore, since potentials on the bit lines are equalized in response to the input data signal change detecting signal, it becomes possible to sense and amplify the potentials on the bit lines at a high speed without being influenced by noise and the like. Consequently, a semiconductor neural network operable at a high speed and with low consumption power can be obtained. 
     Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.