Abstract:
There are provided methods of fabricating a metal-insulator-metal (MIM) capacitor employing a metal nitride layer as a lower electrode. The method includes forming an insulating layer on a semiconductor substrate. A metal source gas and a nitride gas are supplied to the insulating layer, thereby depositing a metal nitride. A flushing gas including nitrogen is supplied to the metal nitride to enhance nitridation reaction. Along with the supply of a metal source gas and a nitride gas, the operation of supplying a flushing gas is performed at least one time alternately and repeatedly, thereby forming a metal nitride layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims priority from Korean Patent Application Nos. 20054-0067640, filed Aug. 26, 2004 and 2005-0000996, filed Jan. 5, 2005, the disclosures of which are incorporated herein by reference in their entireties as if set forth fully herein.  
       FIELD OF THE INVENTION  
       [0002]     The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a metal-insulator-metal (MIM) capacitor.  
       BACKGROUND OF THE INVENTION  
       [0003]     A semiconductor memory device, particularly, a dynamic random access memory (DRAM) is a memory device for storing data in a capacitor of a unit cell. The unit cell of a DRAM is composed of one access transistor and one cell capacitor, which are connected in series.  
         [0004]     A conventional cell capacitor utilizes a metal-insulator-silicon (MIS) structure. In a capacitor having an MIS structure, a storage electrode as a lower electrode uses a polysilicon electrode, and a plate electrode as an upper electrode uses a metal electrode. A dielectric layer is disposed between the storage electrode and the plate electrode. Unfortunately, an MIS structure can change the electrical characteristics of a device due to oxidation reaction that can occur at the interface between the polysilicon electrode and the dielectric layer. Further, a capacitor having an MIS structure can exhibit a nonuniform capacitance depending on the magnitude of a voltage applied to the metal plate electrode. For example, if the polysilicon storage node electrode is doped with n-type impurities, and a negative voltage is applied to the metal plate electrode, holes are induced on the surface of the polysilicon storage node electrode. That is, a depletion layer may be formed on the surface of the lower electrode, and the thickness of the depletion layer may be varied depending on the magnitude of the negative voltage. Because of this, the capacitance of the capacitor is not uniform, and is varied depending on the magnitude of the voltage applied to the electrodes. That is, the capacitor having an MIS structure is not suitable to being employed to a semiconductor device requiring characteristics of an elaborate structure.  
         [0005]     Further, it can be difficult to increase a cell capacitance within a limited area in the case that a design rule of a DRAM device is reduced. In order to increase the cell capacitance, a height of a cell capacitor may be formed higher, and an equivalent oxide thickness (Toexq) of a dielectric layer may be reduced. In the case that the design rule is 100 nm or less, there is a limitation to increasing a height of the cell capacitor greater than 2.0 μm. Therefore, in order to implement a cell capacitor suitable to a highly integrated DRAM device, it is required to reduce the equivalent oxide thickness of the dielectric layer of the cell capacitor. In the capacitor having a conventional MIS structure, there is a limitation to forming a dielectric layer having an equivalent oxide thickness smaller than about 20 Å.  
         [0006]     In order to solve the problems related to an MIS structure, a metal-insulator-metal (MIM) structure, in which an upper electrode and a lower electrode are all formed of metal layers, has been employed. In specific, a technology in which the lower electrode is formed of a titanium nitride (TiN) layer is used in an MIM capacitor. The lower electrode, which is formed of a titanium nitride layer, shows an excellent electrical reliability because the lower electrode has a low resistivity, and suppresses the generation of a parasitic capacitance. Further, since the titanium nitride layer has a strong oxidation resistance, it is suppressed that a native oxide layer is formed on the titanium nitride layer. Thus, it is easy to reduce the equivalent oxide thickness of the dielectric layer formed on the titanium nitride layer. For this reason, a titanium nitride layer has been widely used as the lower electrode.  
         [0007]     However, when the titanium nitride layer replaces the polysilicon layer for the lower electrode, a contact resistance at the interface between the lower electrode, which is formed of the titanium nitride layer, and a polysilicon plug disposed thereunder is increased, thereby deteriorating the operation characteristics of a device. In order to improve the contact resistance, a titanium silicide (TiSi 2 ) layer as an ohmic contact layer may be formed on an upper surface of the polysilicon plug.  
         [0008]     A method of forming the titanium silicide layer on an upper surface of the polysilicon plug, and then, forming the lower electrode using a metal layer is disclosed in Korean Patent Publication No. 2002-84596 entitled “Method of fabricating capacitor.” 
         [0009]     According to Korean Patent Publication No. 2002-84596, an etch stop layer and a molding insulating layer are sequentially formed on a substrate having a polysilicon plug penetrating an interlayer insulating layer, and the molding insulating layer and the etch stop layer are patterned, thereby forming a capacitor hole exposing the polysilicon plug. A titanium layer is formed on an overall surface of the substrate having the capacitor hole, and concurrently, a titanium silicide layer is formed on the surface of the polysilicon plug. An unreacted titanium layer remaining on the surface of the molding insulating layer is removed, and the titanium silicide layer is exposed to ammonia (NH 3 ) plasma. As a result, a nitrified titanium silicide (Ti—Si—N) layer is formed on the surface of the titanium silicide layer. A titanium nitride layer and a sacrificial layer are sequentially formed on the substrate having the nitrified titanium silicide layer. The sacrificial layer and the titanium nitride layer are planarized, thereby forming a titanium nitride layer pattern, that is, lower electrode inside the capacitor hole. Then, the molding insulating layer and the sacrificial layer are removed, thereby exposing an inner wall and an outer sidewall of the lower electrode.  
         [0010]     In the method of fabricating a capacitor according to Korean Patent Publication No. 2002-84596, while removing the molding insulating layer and the sacrificial layer to expose the inner wall and the outer sidewall of the lower electrode, an etch solution may penetrate into the interface between the lower electrode and the etch stop (Si 3 N 4 ) layer, so as to further etch the interlayer insulating layer. As a result, a through hole may be formed in the interlayer insulating layer. Unfortunately, a through hole in the interlayer insulating layer may render a semiconductor device defective.  
         [0011]     In the case where a titanium nitride layer is formed using a chemical vapor deposition (CVD) method, a throughput may be improved, but a through hole may be formed in the interlayer insulating layer as described above. Further, since the CVD TiN layer is formed by continuous reaction of a tetrachlorotitanium (TiCl 4 ) gas and an ammonia (NH 3 ) gas, a chlorine content in the CVD TiN layer may be increased. In this case, the chlorine atoms may cause a crack of the CVD TiN layer.  
       SUMMARY OF THE INVENTION  
       [0012]     Therefore, an embodiment of the present invention is directed to a method of forming a metal nitride layer for completely nitrifying an unreacted metal layer that remains after forming a metal silicide layer functioning as an ohmic contact layer, thereby preventing the generation of etch defects caused by the unreacted metal layer.  
         [0013]     According to an embodiment of the present invention, a method is provided for fabricating an MIM capacitor wherein chlorine content is reduced in an electrode formed of a metal nitride layer, thereby improving productivity of devices incorporating same.  
         [0014]     According to an embodiment of the present invention, a method of forming a metal nitride layer is provided that includes forming an insulating layer on a semiconductor substrate. A metal source gas and a nitride gas are supplied to the insulating layer, thereby depositing a metal nitride. A flushing gas including nitrogen is supplied to the metal nitride to enhance nitridation reaction. Alternately and repeatedly, the operations of supplying a metal source gas and a nitride gas, and supplying a flushing gas are performed at least one time. As a result, a metal nitride layer is formed on the insulating layer by a sequential flow deposition (SFD) method.  
         [0015]     In accordance with embodiments of the present invention, the metal source gas may be a gas including titanium, tungsten, or tantalum. For example, the gas including titanium may be a tetrachlorotitanium (TiCl 4 ) gas.  
         [0016]     According to embodiments of the present invention, the nitride gas may be a nitrogen gas or ammonia (NH 3 ) gas, and the flushing gas may be a nitrogen gas or ammonia (NH 3 ) gas.  
         [0017]     In accordance with embodiments of the present invention, a purge gas may be supplied to the semiconductor substrate after the deposition of the metal nitride. Further, a purge gas may be supplied to the semiconductor substrate after the enhancement of nitridation reaction. The purge gas may be an inert gas, such as nitrogen.  
         [0018]     In accordance with embodiments of the present invention, a metal nitride layer may be additionally formed on the SFD metal nitride layer using a chemical vapor deposition (CVD) process. The CVD metal nitride layer may be formed by continuous reaction of the metal source gas and the nitride gas without a supply of the flushing gas.  
         [0019]     According to another embodiment of the present invention, a method of fabricating an MIM capacitor is provided that includes forming an interlayer insulating layer on a semiconductor substrate and forming a polysilicon contact plug that penetrates the interlayer insulating layer. A molding layer is formed on the contact plug and the interlayer insulating layer, and the molding layer is patterned, thereby forming a storage node hole exposing the contact plug. An ohmic contact layer is formed on an upper surface of the contact plug. A metal source gas and a nitride gas are supplied to the substrate having the ohmic contact layer, thereby depositing a metal nitride. A flushing gas including nitrogen is supplied to the substrate having the metal nitride, thereby enhancing nitridation reaction of a metal layer remaining in the lower portion of the metal nitride. Alternately and repeatedly, the operations of supplying a metal source gas and a nitride gas, and supplying a flushing gas are performed at least one time, thereby forming a lower electrode layer formed of a metal nitride layer. As a result, an SFD metal nitride layer is formed on the substrate having the ohmic contact layer.  
         [0020]     In accordance with embodiments of the present invention, the operation of forming the ohmic contact layer may include forming a metal layer on the substrate having the storage node hole by deposition. The contact plug may react with the metal layer during the operation of forming the metal layer by deposition, thereby forming a metal silicide layer.  
         [0021]     In accordance with embodiments of the present invention, the metal source gas may be a gas including titanium, tungsten, or tantalum. For example, the gas including titanium may be a tetrachlorotitanium (TiCl 4 ) gas, and the nitride gas may be an ammonia (NH 3 ) gas or a nitrogen gas. The metal nitride may be titanium nitride, and may be deposited with a thickness of 150 to 350 Å.  
         [0022]     Further, the flushing gas may be an ammonia (NH 3 ) gas or a nitrogen (N 2 ) gas.  
         [0023]     In accordance with embodiments of the present invention, after the operation of supplying a metal source gas and a nitride gas, a purge gas may be supplied. In addition, after the operation of supplying a flushing gas, a purge gas may be supplied. An exemplary purge gas is nitrogen.  
         [0024]     In accordance with embodiments of the present invention, a metal nitride layer may be additionally formed on the SFD metal nitride layer, using a CVD process. The CVD metal nitride layer may be formed by continuous reaction of the metal source gas and the nitride gas without a supply of the flushing gas. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]     The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail embodiments thereof with reference to the attached drawings in which:  
         [0026]      FIGS. 1A through 1F  are sectional views that illustrate formation processes sequentially in a method of fabricating an MIM capacitor according to embodiments of the present invention; and  
         [0027]      FIG. 2  is a timing diagram that illustrates a process of forming a lower electrode in a method of fabricating an MIM capacitor according to embodiments of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     The present invention now is described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.  
         [0029]     Like numbers refer to like elements throughout. In the figures, the thickness of certain lines, layers, components, elements or features may be exaggerated for clarity. Broken lines illustrate optional features or operations unless specified otherwise. All publications, patent applications, patents, and other references mentioned herein are incorporated herein by reference in their entireties.  
         [0030]     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, phrases such as “between X and Y” and “between about X and Y” should be interpreted to include X and Y. As used herein, phrases such as “between about X and Y” mean “between about X and about Y.” As used herein, phrases such as “from about X to Y” mean “from about X to about Y.” 
         [0031]     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Well-known functions or constructions may not be described in detail for brevity and/or clarity.  
         [0032]     It will be understood that when an element is referred to as being “on”, “attached” to, “connected” to, “coupled” with, “contacting”, etc., another element, it can be directly on, attached to, connected to, coupled with or contacting the other element or intervening elements may also be present. In contrast, when an element is referred to as being, for example, “directly on”, “directly attached” to, “directly connected” to, “directly coupled” with or “directly contacting” another element, there are no intervening elements present. It will also be appreciated by those of skill in the art that references to a structure or feature that is disposed “adjacent” another feature may have portions that overlap or underlie the adjacent feature.  
         [0033]     Spatially relative terms, such as “under”, “below”, “lower”, “over”, “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted, elements described as “under” or “beneath” other elements or features would then be oriented “over” the other elements or features. Thus, the exemplary term “under” can encompass both an orientation of “over” and “under”. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, the terms “upwardly”, “downwardly”, “vertical”, “horizontal” and the like are used herein for the purpose of explanation only unless specifically indicated otherwise.  
         [0034]     It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a “first” element, component, region, layer or section discussed below could also be termed a “second” element, component, region, layer or section without departing from the teachings of the present invention. The sequence of operations (or steps) is not limited to the order presented in the claims or figures unless specifically indicated otherwise.  
         [0035]     Referring to  FIG. 1A , an isolation layer (not shown) is formed in a semiconductor substrate  100 . The isolation layer may be formed using a typical shallow trench isolation (STI) process, and an active region is defined by the isolation layer, as would be understood by one skilled in the art. A gate insulating layer  102  and a gate conductive layer are sequentially formed on the semiconductor substrate having the isolation layer formed therein. The gate conductive layer may be formed of a refractory metal polycide layer. The gate conductive layer may be formed by sequentially stacking a polysilicon layer and a tungsten silicide layer. The gate conductive layer is patterned, thereby forming a gate electrode  108 . As a result, the gate electrode  108  may include a polysilicon pattern  104  and a tungsten silicide pattern  106 , which are sequentially stacked.  
         [0036]     Using the gate electrode  108  as an ion implantation mask, impurity ions are implanted into the active region, thereby forming low density impurity regions  110 . Insulating layer spacers  112  are formed on the sidewalls of the gate electrode  108  using a typical method, as would be understood by one skilled in the art. Using the insulating layer spacers  112  and the gate electrode  108  as ion implantation masks, impurity ions are implanted into the active region, thereby forming high density impurity regions  114  having a higher density than that of the low density impurity regions  110 . The low density impurity regions  110  and the high density impurity regions  114  constitute LDD-type source/drain regions  116 . The source/drain regions  116  and the gate electrode  108  constitute a MOS transistor.  
         [0037]     Referring to  FIG. 1B , an interlayer insulating layer  118  is formed on the substrate having the source/drain regions  116 . The interlayer insulating layer  118  is patterned, thereby forming a contact hole  120  exposing any one of the source/drain regions  116 . A conductive layer is formed on the interlayer insulating layer  118  to fill the contact hole  120 . The conductive layer is planarized using a chemical mechanical polishing (CMP) process to expose an upper surface of the interlayer insulating layer  118 . As a result, a contact plug  122  is formed inside the contact hole  120 . The contact plug  122  may be formed of a polysilicon layer.  
         [0038]     An etch stop layer  124  is formed on the contact plug  122  and the interlayer insulating layer  118 . The etch stop layer  124  may be a silicon oxynitride (SiON) layer or silicon nitride (SiN) layer, for example.  
         [0039]     Referring to  FIG. 1C , a molding layer  126  is formed on the etch stop layer  124 , and is preferably formed of a material having an etch selectivity with respect the etch stop layer  124 . For example, the molding layer  126  may be formed of a plasma enhanced tetraethylorthosilicate (PE-TEOS) oxide layer, or a silicon oxide layer such as a BPSG layer or PSG layer. The molding layer  126  and the etch stop layer  124  are patterned, thereby forming a storage node hole  128  exposing the contact plug  122 .  
         [0040]     A titanium layer is formed on the substrate having the storage node hole  128 . The titanium layer may be formed with a thickness of about 85 Å, using a chemical vapor deposition (CVD) method. During the deposition of the titanium layer, a titanium silicide layer  130  may be formed on a surface of the contact plug  122 . The titanium silicide layer  130  is formed by the reaction of the titanium layer and the contact plug  122 . The titanium silicide layer  130  functions as an ohmic contact layer to improve contact resistance between the contact plug  122  and a lower electrode to be formed in a subsequent process. The titanium silicide layer  130  may be formed by the thermal processing performed in an ammonia plasma (NH 3  plasma) atmosphere after the titanium layer is formed. During the thermal processing, the unreacted titanium layer that remains on a surface of the molding layer may be nitrified.  
         [0041]     Referring to  FIG. 1D , a lower electrode layer  152  is formed on the semiconductor substrate having the titanium silicide layer  130 . The lower electrode layer  152  may be formed of a metal nitride layer, for example, a titanium nitride layer, a tantalum nitride layer, or a tungsten nitride layer. The lower electrode layer  152  may be formed by sequentially stacking a first lower electrode layer  132  and a second lower electrode layer  151 . The first lower electrode layer  132  may be formed using a sequential flow deposition (SFD) method, and the second lower electrode layer  151  may be formed using a CVD method. A total thickness of the first and second lower electrodes  132 ,  151  may be formed in a range of 200 to 300 Å. For example, the first lower electrode layer  132  may be formed with a thickness of 70 to 200 Å, and the second lower electrode  151  layer may be formed with a thickness of 70 to 200 Å. Alternatively, the lower electrode layer  152  may be formed of only the first lower electrode layer  132 . That is, the second lower electrode layer  151  may be omitted. In this case, the first lower electrode layer  132  may be formed with a thickness of 150 to 350 Å.  
         [0042]     The CVD process for forming the second lower electrode layer  151  may be sequentially performed inside a chamber where the SFD process is performed to form the first lower electrode layer  132 . That is, the first and second lower electrode layers  132 ,  151  may be formed in an in-situ manner. Further, the first and second lower electrode layers  132 ,  151  may be formed at substantially the same temperature. Alternatively, the first and second lower electrode layers  132 ,  151  may be formed in two different chambers separately. However, the first and second lower electrode layers  132 ,  151  are preferably formed using the in-situ manner in the point of a throughput. After the lower electrode layer  152  is formed, the unreacted metal layer that remains on a surface of the molding layer  126  (for example, unreacted titanium layer) may be removed using a typical wet etch process, as would be understood by one skilled in the art. The titanium layer that remains after the wet etch process is performed may be plasma-treated using a gas including nitrogen. The nitrogen plasma processing may be performed using NH 3  gas or N 2  gas for about 80 seconds, for example. A sacrificial layer  133  is formed on the lower electrode layer  152  to fill the storage node hole  128 . The sacrificial layer  133  may be formed of the same material layer as the molding layer  126 .  
         [0043]     In another embodiment of the present invention, the titanium layer for forming the titanium silicide layer  130 , and the metal nitride layer for forming the lower electrode layer  152  may be sequentially formed in an in-situ manner.  
         [0044]     The first lower electrode layer  132  may be formed of a titanium nitride layer using the SFD method. In this case, a process of forming the first lower electrode layer  132  will be explained in detail with reference to a timing diagram of  FIG. 2 .  
         [0045]     First, a semiconductor substrate having the titanium silicide layer  130  is loaded into a process chamber. A metal source gas and a nitride gas are supplied into the process chamber in which the semiconductor substrate is loaded for about one hour (T1), for example, thereby forming a metal nitride on the semiconductor substrate by deposition (first step). The metal source gas uses TiCl 4 , and is supplied at a flow rate of 5 to 50 sccm, for example. The nitride gas may use NH 3  or N 2  gas. The nitride gas may be supplied at a flow rate of 10 to 50 sccm, for example. While the metal source gas and the nitride gas are supplied, the inside of the process chamber can be maintained with a pressure of 1 to 5 torr and at a temperature of 550 to 800° C., for example. Thus, a titanium nitride (the metal nitride) is deposited on the inner wall of the storage node holes  128  and on the upper surface of the molding layer  126 .  
         [0046]     Then, the metal source gas and the nitride gas that remains inside the process chamber with an unreacted layer can be purged for about two hours (T2) (second step), for example. The purge process may be performed using an inert gas, for example, nitrogen (N 2 ) gas.  
         [0047]     After the purge process, a gas such as ammonia (NH 3 ) is supplied into the process chamber for about three hours (T3) to perform a nitridation flushing process (third step). The nitridation flushing process is preferably performed for at least 5 seconds. The inner temperature of the process chamber during the nitridation flushing process may be between about 500 to 650° C., for example. The nitridation flushing process may be performed in an in-situ manner at the same temperature as that of the process in the first step.  
         [0048]     After the titanium silicide layer  130  is formed, even though an unreacted titanium layer remains on the inner wall of the storage node hole  128 , the unreacted titanium layer may be nitrified by the nitridation flushing process. After the nitridation flushing process, the nitride gas that remains inside the process chamber can be purged for about four hours (T 4 ) (fourth step), for example.  
         [0049]     One process cycle which is composed of the first through fourth steps described above is repeatedly performed at least twice. This is intended to repeatedly perform the nitridation flushing process while the titanium nitride layer is formed, and to completely nitrify the unreacted titanium layer that remains inside the storage node hole. The one process cycle may be performed for about 10 seconds, for example. During the one process cycle, the titanium nitride layer may be formed with a thickness of 20 to 25 Å, for example. At least one purge process in the purge processes (second and fourth steps) may be omitted during the one process cycle.  
         [0050]     As a result, when at least the first lower electrode layer  132  is formed by repeatedly performing the one process cycle, the titanium layer that remains on the surface of the molding layer can be completely nitrified. Thus, it can prevent the generation of etch defects caused by a wet etch solution during the removal of the molding layer and a sacrificial layer in a subsequent process. Furthermore, in the case that at least the first lower electrode layer  132  is formed by the SFD method, a chlorine content of the lower electrode layer  152  including the first lower electrode layer  132  can be minimized. Thus, it can prevent the generation of crack of the lower electrode layer  152 .  
         [0051]     In still another embodiment of the present invention, the first lower electrode layer  132  may be formed using an atomic layer deposition (ALD) method. While the first lower electrode layer  132  is formed using the ALD method, the nitridation flushing process is repeatedly performed at least twice.  
         [0052]     The CVD process for forming the second lower electrode layer  151  may be performed by a continuous reaction of the metal source gas and the nitride gas without using the flushing gas. Therefore, when the lower electrode layer  152  is formed by sequentially stacking the first and second lower electrode layers  132 ,  151 , a production yield can be improved in comparison with the case where the lower electrode layer  152  is formed of only the first lower electrode layer  132 .  
         [0053]     According to the embodiments of the present invention, while the lower electrode layer (metal nitride layer)  152  is formed, the nitridation flushing process is repeatedly performed at least twice. As a result, the titanium layer that remains inside the storage node hole  128  can be effectively nitrified.  
         [0054]     Referring to  FIG. 1E , the sacrificial layer  133  ( FIG. 1D ) and the lower electrode layer  152  ( FIG. 1D ) are planarized using a CMP process or a dry etch back process, thereby exposing an upper surface of the molding layer  126 . As a result, a storage node isolated inside the storage node hole  128 , that is, a lower electrode  152   a  is formed, as illustrated. Further, a sacrificial layer pattern (not shown) may remain inside a space surrounded by the lower electrode  152   a,  as would be understood by one skilled in the art.  
         [0055]     In the case that the lower electrode layer  152  is formed by sequentially stacking the first and second lower electrode layers  132 ,  151 , the lower electrode  152   a  may be formed to include a first lower electrode  132   a  and a second lower electrode  151   a  surrounding the inner wall of the first lower electrode  132   a.  Alternatively, in the case that the second lower electrode layer  151  is omitted, the lower electrode  152   a  may be formed of only the first lower electrode  132   a.    
         [0056]     After the lower electrode  152   a  is formed, the molding layer and the sacrificial layer pattern are removed, thereby exposing an inner wall and an outer sidewall of the lower electrode  152   a.  The molding layer and the sacrificial layer pattern may be removed using a wet etch solution such as fluoric acid solution. While the molding layer is removed, the wet etch solution may not penetrate into the interlayer insulating layer  118 . This is because a titanium layer does not exist at the interface between the first lower electrode  132   a  and the etch stop layer  124 . Thus, it can prevent the generation of etch defects inside the interlayer insulating layer  118 .  
         [0057]     Referring to  FIG. 1F , a dielectric layer  134  and an upper electrode  136  are sequentially formed on the semiconductor substrate from which the molding layer is removed, so as to cover the surface of the lower electrode  152   a.  Before the dielectric layer  134  is formed, the etch stop layer  124  may be selectively removed. The dielectric layer  134  may be formed of a high-k dielectric layer such as a hafnium oxide (HfO 2 ) layer, an aluminum oxide (Al 2 O 3 ) layer, a tantalum oxide (Ta 3 O 5 ) layer, a lanthanum oxide (La 2 O 3 ) layer, or a zirconium oxide (ZrO 2 ) layer. In order to improve the characteristics of the dielectric layer  134 , the dielectric layer  134  may be thermally processed, or plasma-treated. The upper electrode  136  may be formed of a metal layer such as a titanium layer, a tungsten layer, a tantalum layer, a titanium nitride layer, a tungsten nitride layer, or a tantalum nitride layer, for example.  
         [0058]     As described above, according to embodiments of the present invention, a nitridation flushing process is repeatedly performed at least twice during the process of forming the metal nitride layer as the lower electrode layer covering the inner wall of the storage node hole penetrating the molding layer. As a result, an unreacted metal layer can be completely nitrified during the nitridation flushing process even though the unreacted metal layer exists inside the storage node hole. Therefore, during the process of removing the molding layer using a wet etch solution, the wet etch solution is prevented from penetrating into the interlayer insulating layer via the interface between the lower electrode and the etch stop layer.  
         [0059]     Further, according to embodiments of the present invention, the lower electrode layer can be formed at least using an SFD process and a CVD process. Therefore, the lower electrode layer can be prevented from becoming cracked, thereby improving productivity of a semiconductor device incorporating the lower electrode.  
         [0060]     The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. The invention is defined by the following claims, with equivalents of the claims to be included therein.