Abstract:
A system-in-package (SIP) structure is described, including stacked circuit/insulator composite layers, bumps and a cover plate. Each circuit/insulator composite layer is lifted off from a semiconductor-on-insulator (SOI) substrate, including the insulator of the SOI substrate and a circuit layer based on the semiconductor of the SOI substrate. The circuit layer of a circuit/insulator composite layer is electrically coupled with the circuit layer of the underlying circuit/insulator composite layer. The bumps are disposed on the lower surface of the bottom circuit/insulator composite layer, electrically coupled with the circuit layer of the bottom circuit/insulator composite layer. The cover plate is disposed on the top circuit/insulator composite layer.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a semiconductor apparatus. More particularly, the present invention relates to a system-in-package (SIP) structure and a method for fabricating the same.  
         [0003]     2. Description of the Related Art  
         [0004]     SIP technique is very useful in compactification of electronic system, and reducing the thickness of SIP is very important in related fields. In the prior art, an SIP structure is formed with wire bonding or 3D solder-ball stacking.  
         [0005]      FIG. 1  illustrates a conventional SIP structure that is usually called stacked CSP (chip-scale package). Referring to  FIG. 1 , the stacked CSP includes a first chip  100 , a second chip  110  and a third chip  120  that are sequentially stacked on a carrier substrate  130  interposed by underfill  135 . Each chip ( 100 ,  110  or  120 ) is electrically connected to the circuit of the carrier substrate  130  using bumps (not shown) and bonding wires  140 , so that the size of the three chips  100 - 120  has to be reduced gradually. The circuit of the carrier substrate  130  is connected to ball pads  150  on the bottom surface of the carrier substrate  130 , and solder balls  160  are formed on the ball pads  150 .  
         [0006]      FIG. 2  illustrates another conventional SIP structure that is Sharp&#39;s 3D MCP (multi-chip package) for memory application. The 3D MCP consists of several stack units  200  that are stacked vertically. Each stack unit  200  includes a carrier substrate  210 , two memory chips  220  sealed in a sealing resin  230 , lead wires and bonding wires  240  electrically connecting the memory chips  220  and the circuit in the carrier substrate  210 , ball pads  250 , through plugs  260  and solder balls  270 . Each bonding wire  240  is electrically connected to the corresponding chip  220  via a bump (not shown). Each through plug  260  is electrically connected with the circuit in the carrier substrate  210 , and is connected between two ball pads  250  respectively on the upper side and the lower side of the carrier substrate  210 . The solder balls  270  are disposed on the ball pads  250  on the lower side of the carrier substrate  210  to contact with the ball pads  250  on the upper side of the carrier substrate  210  of the underlying stack unit  200 . As compared with the stacked CSP, Sharp&#39;s 3D MCP does not require each chip to be different in size, but does require more carrier substrates.  
         [0007]     Since the thickness of a chip is the same as that of a wafer, the thickness of the conventional SIP structures cannot be easily reduced. Moreover, the conventional carrier substrate is usually a printed circuit board (PBC) and the bump material for wire bonding is mostly gold, so that the costs of the conventional SIP structures are higher. Furthermore, the conventional carrier substrate, which is usually a printed circuit board (PBC), makes the conventional SIP structures difficult to thin down.  
       SUMMARY OF THE INVENTION  
       [0008]     In view of the foregoing, an object of this invention is to provide a SIP structure that has a reduced thickness.  
         [0009]     Another object of this invention is to provide a SIP structure that neither requires each stacked unit to be different in size nor needs any conventional carrier substrate, and uses less bumps.  
         [0010]     Still another object of this invention is to provide a SIP structure that allows a thinner carrier substrate to be used.  
         [0011]     This invention also provides a method for fabricating the SIP structure of this invention.  
         [0012]     The SIP structure of this invention includes stacked circuit/insulator composite layers, bumps and a cover plate. Each circuit/insulator composite layer is lifted off from a semiconductor-on-insulator (SOI) substrate, including the insulator of the SOI substrate and a circuit layer based on the semiconductor of the SOI substrate. The circuit layer of a composite layer is electrically coupled with the circuit layer of the underlying composite layer. The bumps are disposed on the lower surface of the bottom composite layer, electrically coupled with the circuit layer of the bottom composite layer. The cover plate is disposed on the top composite layer, serving as a carrier substrate.  
         [0013]     In an embodiment of this invention, the insulator of each composite layer faces down, the bumps are disposed on the lower surface of the insulator of the bottom composite layer, and the cover plate on the circuit layer of the top composite layer. In another embodiment, however, it is the circuit layer of each composite layer that faces down, while the bumps are disposed on the circuit layer of the bottom composite layer and the cover plate on the insulator of the top composite layer.  
         [0014]     The method for fabricating a SIP structure of this invention includes the following steps. In step (a), multiple semiconductor-on-insulator (SOI) substrates, each of which includes an insulator and a circuit layer on the insulator, are provided. In step (b), the insulator and the circuit layer of each SOI substrate are lifted off to be multiple circuit/insulator composite layers. In step (c), the composite layers are vertically stacked with the circuit layer of a composite layer being coupled with the circuit layer of the preceding composite layer. In step (d), a cover plate is bonded to the top circuit/insulator composite layer. In step (e), multiple bumps are formed on the bottom circuit/insulator composite layer electrically coupled with the circuit layer of the bottom composite layer.  
         [0015]     In an embodiment of this invention, the step (d) is performed before the step (b). That is, the top composite layer is lifted off after being bonded with the cover plate, and the cover plate and the top composite layer together serve as a base in subsequent stacking process, while the top composite layer is the firstly stacked composite layer in the case. In another embodiment, the step (d) is performed after the step (c), and the cover plate is bonded to the last stacked composite layer that turns to be the top composite layer. In the latter case, a preceding cover plate may serve as the base in the stacking process as in the former case, while the preceding cover plate is bonded with the firstly stacked composite layer (bottom composite layer) and is removed after the cover plate is bonded to the last stacked composite layer (top composite layer).  
         [0016]     Since the thickness of a circuit/insulator composite layer lifted off from a SOI substrate is much smaller than that of a chip divided from a wafer, the thickness of SIP structure can be significantly reduced in this invention. Moreover, a composite layer is directly stacked onto the preceding composite layer and the bumps are merely formed on the bottom circuit/insulator composite layer, so that conventional carrier substrates as illustrated in  FIGS. 1 and 2  can be saved and the number of bumps can be reduced. Therefore, the cost of SIP structure can be reduced. Furthermore, the cover plate serving as a carrier substrate in this invention can be a glass plate that is thinner than a PCB, so that the thickness of SIP structure can be further reduced.  
         [0017]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0019]      FIG. 1  illustrates a conventional SIP structure that is usually called stacked CSP.  
         [0020]      FIG. 2  illustrates another conventional SIP structure that is Sharp&#39;s 3D MCP.  
         [0021]     FIGS.  3 A(b) and  3 B- 3 H illustrates a process flow of fabricating an SIP structure according to a first embodiment of this invention in a local cross-sectional view, and  FIG. 3A (a) illustrates the whole wafer area corresponding to  FIG. 3A (b).  
         [0022]      FIGS. 4A-4C  illustrates a latter part of a process flow of fabricating an SIP structure according to a second embodiment of this invention in a local cross-sectional view, wherein  FIG. 4A  follows  FIG. 3E . 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0023]     The SIP structures and the corresponding fabricating processes according to the first and second embodiments of this invention are described as follows to further explain this invention, but not to restrict the scope of this invention. For example, the number of the stacked circuit/insulator composite layers is not restricted to 4 or 2 as illustrated in  FIG. 3H  or  4 C, and can be any number larger than one depending on the number of the repeated stacking-step cycles.  
       First Embodiment  
       [0024]     FIGS.  3 A(b) and  3 B- 3 H illustrates a process flow of fabricating an SIP structure according to the first embodiment of this invention in a local cross-sectional view, and  FIG. 3A (a) illustrates the whole wafer area corresponding to  FIG. 3A (b).  
         [0025]     Referring to  FIG. 3A (a)/(b), a semiconductor-on-insulator (SOI) wafer  300 , such as, a silicon-on-insulator wafer, is provided, including an insulator  310  and a semiconductor layer thereon. The insulator  310  is a buried oxide layer, for example, and the semiconductor layer is a part of the layer  320  described latter. The thickness of the insulator  310  ranges from 1 μm to 10 μm. The SOI wafer  300  is then subjected to a complete fabricating process to form a circuit layer  320  based on the semiconductor layer and to define multiple die regions  302 . The thickness of the circuit layer  320  ranges approximately from 10 μm to 100 μm, and the circuit layer  320  within each die region  302  has multiple bonding pads  330  formed thereon. Then, a cover plate  340 , such as, a glass plate, is bonded to the circuit layer  320 . The thickness of the cover plate ranges approximately from 1 mm to 10 mm, and the cover plate  340  may be bonded to the circuit layer  320  through thermocompression bond.  
         [0026]     Referring to  FIG. 3B , the circuit layer  320  and the insulator  310  are lifted off from the SOI substrate  300  together with the cover plate  340 . The lift-off method can be any suitable method known in the prior art, such as, a hydrogen implantation-annealing method that forms a quasi-continuous gaseous layer between the bulk portion of the SOI substrate  300  and the insulator  310  for their separation.  
         [0027]     Referring to  FIG. 3C , the composite structure consisting of the three parts  310 ,  320  and  340  is then flipped, making the insulator face up, to serve as a base for the latter stacking process, while the insulator  310  and the circuit layer  320  together constitute a firstly stacked circuit/insulator composite layer. Then, via holes  350  are formed through the insulator  310  and the circuit layer  320  to the bonding pads  330 , and then a conductive material  360  is formed over the insulator  310 , filling up the via holes  350  to form plugs  360   a.    
         [0028]     Referring to  FIGS. 3C and 3D , a patterned photoresist layer  361  that defines shoulder portions of the plugs  360   a  is formed on the conductive material  360 . The shoulder portion of a plug  360   a  is slightly wider than any other portions to ensure the contact between the plug  360   a  and the corresponding bonding pad of the next stacked circuit/insulator composite layer. The photoresist layer  361  is removed after the conductive material  360  is patterned using the photoresist layer  361  as a mask.  
         [0029]     Referring to  FIG. 3E , another SOI wafer/substrate  362  formed with an insulator  364  and a circuit layer  366  thereon is provided, wherein the circuit layer  366  is formed with bonding pads  368  thereon. The circuit/insulator composite layer  366 / 364  is then lifted off from the SOI substrate  362  and stacked on the insulator  310 , with the insulator  364  facing up and the die regions thereof aligned with the die regions  302  of the underlying circuit layer  320 . The bonding pads  368  on the circuit layer  366  contact with the shoulder portions of the plugs  360   a  that are electrically connected with the bonding pads  330  on the underlying circuit layer  320 , thus electrically connecting to the bonding pads  330 .  
         [0030]     Referring to  FIG. 3F , plugs  370  are formed through the insulator  364  and the circuit layer  366  to connect with the bonding pads  368  with the same steps mentioned above. The shape of each plug  370  can be the same as that of each plug  360   a  of the preceding circuit/insulator composite layer  320 / 310 .  
         [0031]     Referring to  FIG. 3G , more circuit/insulator composite layers  380 , each of which includes an insulator  384  and a circuit layer  386  formed with bonding pads  388  thereon, are lifted off from other SOI substrates and stacked over the insulator  364  with the same steps mentioned above. It is also required to align the die regions of each circuit/insulator composite layer  380  to the die regions  302  of the base circuit layer  320 . After each circuit/insulator composite layer  380  is stacked, plugs  390  are formed through the insulator  384  and the circuit layer  386  to connect with the bonding pads  388  on the circuit layer  386  of the same circuit/insulator composite layer  380 .  
         [0032]     Referring to  FIG. 3H , after the last circuit/insulator composite layer  380  is stacked, bumps  392  are formed on the plugs  390  of the last stacked composite layer  380 , wherein the material of the bumps  392  is preferably gold. Thereafter, the resulting stacked structure, which consists of multiple circuit/insulator composite layers from different SOI wafers, the cover plate  340  and the bumps  392 , is diced into many single dies  304  defined by the die regions  302  ( FIG. 3A (a)).  
       Second Embodiment  
       [0033]      FIGS. 4A-4C  illustrates a latter part of a process flow of fabricating an SIP structure according to the second embodiment of this invention in a local cross-sectional view, while the former part of the process flow may include the same steps as illustrated in  FIGS. 3A-3E .  
         [0034]     Referring to  FIG. 4A , another cover plate  400  is bonded to the insulator  364  of the secondly stacked circuit/insulator composite layer  366 / 364  ( FIG. 3E ). The cover plate  400  can be completely the same as the cover plate  340 . The material of the cover plate  400  may be glass, and the thickness of the cover plate  400  ranges approximately from 1 mm to 10 mm.  
         [0035]     Referring to  FIG. 4B , the original cover plate  340  is removed from the circuit layer  320  of the firstly stacked circuit/insulator composite layer  320 / 310  to expose the bonding pads  330  on the circuit layer  320 .  
         [0036]     Referring to  FIG. 4C , after the cover plate  340  is removed, bumps  410  are formed on the bonding pads  330  of the bottom circuit layer  320 , wherein the material of the bumps  392  is preferably gold. Thereafter, the resulting stacked structure, which consists of multiple circuit/insulator composite layers from multiple SOI wafers and the cover plate  400 , is diced into many single dies  420  defined by the die regions  302  ( FIG. 3A (a)).  
         [0037]     Though there are only two circuit/insulator composite layers being stacked in the above description of this embodiment, more composite layers can be stacked onto the insulator  364  with the same steps mentioned above before the cover plate  400  is applied. More specifically, plugs are formed through the insulator and the circuit layer of the preceding composite layer to connect with the bonding pads of the same, and then a new composite layer is stacked onto the preceding one with the circuit layer facing down and the bonding pads thereon electrically connecting with the plugs. However, since the bumps  410  are not formed on the last stacked composite layer  366 / 364  but on the firstly stacked composite layer  320 / 310  in this embodiment, no plug is formed through the insulator and the circuit layer of the last stacked composite layer  366 / 364  to provide electrical connection for the bumps as in the first embodiment.  
         [0038]     Moreover, in the above two embodiments of this invention, the circuit layer of each circuit/insulator composite layer may have a memory circuit therein, so that the SIP structure can be obtained as a highly compact memory module.  
         [0039]     Since the thickness of a circuit/insulator composite layer lifted off from a SOI substrate is much smaller than that of a chip divided from a wafer, the thickness of SIP structure can be significantly reduced in this invention. Moreover, a composite layer is directly stacked onto the preceding composite layer and the bumps are merely formed on the bottom circuit/insulator composite layer, so that conventional carrier substrates as illustrated in  FIGS. 1 and 2  can be saved and the number of bumps can be reduced. Therefore, the cost of the SIP structure can be reduced. Furthermore, the cover plate serving as a carrier substrate in this invention can be a glass plate that is thinner than a PCB, so that the thickness of SIP can be further reduced.  
         [0040]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.