Abstract:
Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connections. Instances of the generalized driver module may be included anywhere on the programmable logic device that driver circuitry having characteristics within the capabilities of the generalized module is needed. The circuitry of each instance of the module is hardware-customized to match the driver characteristics required for that instance. Driver circuits may be distributed throughout the interconnection conductor resources of the programmable logic device in such a way as to optimize re-buffering of signals propagating through those resources.

Description:
This is a continuation of U.S. patent application Ser. No. 09/516,866, filed Mar. 2, 2000, now U.S. Pat. No. 6,480,027 which is hereby incorporated by reference in its entirety. This application claims the benefit of U.S. provisional patent application No. 60/122,788, filed Mar. 4, 1999, and U.S. provisional patent application No. 60/142,516, filed Jul. 6, 1999, both of which are hereby incorporated by reference herein in their entireties. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates to programmable logic integrated circuitry devices, and more particularly to driver circuitry for use in such devices. 
     As is well known to those skilled in the art, programmable logic devices typically include many regions of programmable logic and programmable interconnection resources for selectively conveying signals to, from, and between the logic regions. Each logic region is programmable to perform any of several relatively simple logic operations on input signals applied to the logic region in order to produce one or more logic region output signals. The interconnection resources are programmable to interconnect the logic regions in any of many different configurations so that very complex logic tasks can be performed by concatenating the logic regions in various ways. 
     Examples of programmable logic devices are shown in Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Cliff et al. U.S. Pat. No. 5,963,049, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. patent application Ser. No. 09/516,921, filed Mar. 2, 2000, all of which are hereby incorporated by reference herein in their entireties. 
     At various locations in the interconnection resources of programmable logic devices signals may need to be strengthened in order to propagate along a relatively long interconnection conductor or to continue to propagate along such a conductor or succession of conductors. Such signal strengthening is variously referred to as buffering, re-buffering, driving, or the like, and it may be produced by circuit elements that are variously called buffers, drivers, tri-state drivers, or the like. In general, these various terms are used interchangeably herein. There are many different places in a programmable logic device at which signal buffering may be needed. For example, the output signal of a logic region may need buffering to enable it to better drive an interconnection conductor. A signal reaching the end of an interconnection conductor segment may need to be buffered so that it can drive the next interconnection conductor segment. A signal turning from a horizontal interconnection conductor segment to a vertical interconnection conductor segment (or vice versa) may need to be buffered so that it can drive the receiving segment. Signals received by the device from external circuitry may need buffering, and signals that will be output signals of the device may need buffering in order to drive external circuitry. 
     Heretofore the driver circuitry needed in each circuit context has generally been designed specifically for that context. This can lead to a proliferation of buffer circuit designs, which can in turn increase the difficulty of laying out and otherwise designing a new programmable logic device. 
     In view of the foregoing, it is an object of this invention to improve and simplify the design of programmable logic devices. 
     It is a more particular object of this invention to provide improved and simplified (e.g., by virtue of being more standardized) driver circuitry for programmable logic devices. 
     SUMMARY OF THE INVENTION 
     These and other objects of the invention are accomplished in accordance with the principles of the invention by providing a driver circuit module for programmable logic devices, which can be adapted to perform any of several different tasks, and which module can therefore be used in any of several different contexts in a programmable logic device. The generalized driver module of this invention has the capability of driving a signal from any of several sources (e.g., an adjacent region of programmable logic or adjacent ends of interconnection conductors) to any of several destinations (e.g., adjacent ends of interconnection conductors). Each instance of the driver module on the programmable logic device is hardware-configurable to meet the requirements of that particular instance. For example, the hardware configuration or hardware programming of an instance of the driver module may include providing the metal in the module needed to complete certain connections while omitting the metal needed for other connections. 
     Another aspect of the invention relates to the manner in which driver modules, interconnection conductors, and logic regions are disposed on a programmable logic device and inter-related. In this aspect the driver modules can be either the hardware-configurable modules described briefly in the preceding paragraph, or they can be software-programmable driver modules (e.g., of known design). A plurality of logic regions are disposed on the programmable logic device in a row. A plurality of interconnection conductor channels extend along the row. The interconnection conductors in each of the channels are interrupted at spaced locations along the row by driver modules. Each driver module is adjacent a respective one of the logic regions and can drive a signal from the adjacent logic region or the conductors interrupted by that driver module onto some or all of the conductors interrupted by that module. The modules in the various channels are preferably offset from one another along the row. The spacing of the spaced locations in each channel is preferably uniform for all channels and equal to the spacing between logic regions that are separated from one another by several other logic regions. This spacing is also preferably an optimal or at least desirable spacing for re-buffering signals that must be propagated more than one conductor-segment-length along a conductor channel. The driver modules are preferably the sole means by which signals can be driven onto the conductors. This arrangement of logic regions, interconnection conductors, and driver modules has a great many advantages such as improving signal propagation timing uniformity and predictability. 
    
    
     Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified schematic block diagram of an illustrative embodiment of a driver module in accordance with the invention. 
     FIG. 2 a  is a simplified schematic block diagram showing a first illustrative customization of the module of FIG. 1 in accordance with the invention. 
     FIG. 2 b  is similar to FIG. 2 a  but shows a second illustrative customization of the FIG. 1 module in accordance with the invention. 
     FIG. 2 c  is again similar to FIG. 2 a  but shows a third illustrative customization of the FIG. 1 module in accordance with the invention. 
     FIG. 2 d  is once again similar to FIG. 2 a  but shows a fourth illustrative customization of the FIG. 1 module in accordance with the invention. 
     FIG. 2 e  is similar to FIG. 2 d  but shows yet another illustrative customization of the FIG. 1 module in accordance with the invention. 
     FIG. 3 is a simplified schematic block diagram of another illustrative embodiment of a driver module in accordance with the invention. 
     FIG. 4 is a simplified schematic block diagram of representative portions of an illustrative embodiment of a programmable logic device constructed in accordance with the invention. 
     FIG. 5 is generally similar to FIG. 4 but illustrates other possible aspects of the invention. 
     FIG. 6 is a simplified block diagram of an illustrative system employing a programmable logic device in accordance with the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An illustrative embodiment of a driver module  10  in accordance with this invention is shown in FIG.  1 . Module  10  includes driver circuitry  20 , input selection circuitry  30  for selecting any one of several input signals  32   a ,  32   b , and  34  for application to the input terminal of driver circuitry  20 , and output routing circuitry  40  for routing the output signal of driver circuitry  20  to either or both of two output leads  42   a  and  42   b . Driver module  10  also includes four interconnection areas  50   a - 50   d . Within each of these areas  50  each lead  32 / 52 / 54  or  42 / 52 / 54  extending to the area is connectable to either one or both of the other leads extending to that area. Leads  54   a  and  54   b  are bridge connections extending between interconnection areas  50   a / 50   c  and  50   b / 50   d , respectively. 
     Driver module  10  has many possible uses within a programmable logic device. For example, each of leads  52   a-d  may be a different interconnection conductor of the programmable logic device. Thus lead  52   a  may be a relatively long horizontal interconnection conductor extending to the left from module  10 ; lead  52   b  may be a relatively long horizontal interconnection conductor extending to the right from module  10 ; lead  52   c  may be a relatively short horizontal interconnection conductor extending to the left from module  10 ; and lead  52   d  may be a relatively short horizontal interconnection conductor extending to the right from module  10 . Lead  34  may receive an output signal from a region of programmable logic adjacent to module  10 . 
     In the design of a programmable logic device, driver modules generally like module  10  can be placed anywhere that driver capabilities supportable by such a module are needed. Thereafter in the design of the programmable logic device, each of these generalized driver modules  10  can be customized to provide the connections needed at that particular driver module instance. This customization of each driver module includes making appropriate hardware connections to the module and configuring the hardware of the module in the manner appropriate to the task it must perform. For example, appropriate interconnection conductors may be used for leads  52 , and an appropriate logic region output signal may be used for lead  34 . Similarly, the hardware represented by elements  30  and  40  is configured to make the desired input and output connections to and from driver circuitry  20 . The hardware represented by each of elements  50  is also configured to make the desired connections among the leads to that element. In certain cases elements that are completely unneeded may be omitted. For example, one or both of conductors  54   a/b  may be omitted if not needed, or some of elements  50  may be similarly omitted. In the design and fabrication of the programmable logic device that uses driver module  10 , different metal connection selections may be made for the various instances of module  10  to hardware-customize each instance of the module as is appropriate for that instance. 
     Examples of specific hardware versions of generalized driver module  10  are shown in FIGS. 2 a - 2   e . For example, FIG. 2 a  shows hardware-configuration of a driver module  10   a  for use in driving relatively long left- and right-extending horizontal interconnection conductors  52   a  and  52   b  from a logic region output connected to lead  34 . In this example the hardware of element  30  is configured to apply the signal on lead  34  to the input of driver circuitry  20 ; the hardware of element  40  is configured to apply the output signal of driver circuitry  20  to both of leads  42 ; and each of areas  50   a  and  50   b  is configured to connect the associated leads  42  and  52 . Elements of generalized driver module  10  that are not used in FIG. 2 a  are omitted from that FIG. and can be similarly omitted from the actual circuitry of the programmable logic device for this instance of the driver module if desired. 
     FIG. 2 b  shows an example of customization of the hardware of a driver module  10  for use of the module to drive relatively long left- and right-extending horizontal interconnection conductors  52   a  and  52   b  from relatively short left-extending horizontal interconnection conductor  52   c . Thus in customized driver module  10   b  the hardware represented by elements  50   c  and  30  is configured to apply the signal on conductor  52   c  to the input terminal of driver circuitry  20 , and the hardware represented by elements  40 ,  50   a , and  50   b  is configured to apply the output signal of driver circuitry  20  to both of conductors  52   a  and  52   b . Again, elements of generalized driver module  10  that are not used in customized driver module  10   b  are not shown in FIG. 2 b  and can be omitted from the programmable logic device for this instance of the driver module if desired. 
     FIG. 2 c  shows an example of customization of the hardware of a generalized driver module  10  for use in re-buffering the signal from relatively long left-extending horizontal conductor  52   a  for application to relatively long right-extending horizontal conductor  52   b . In this instance the hardware represented by elements  50   a ,  50   c , and  30  is configured to apply the signal on conductor  52   a  to the input terminal of driver circuitry  20  via leads  54   a  and  32   a . Similarly, the hardware represented by elements  40  and  50   b  is configured to apply the output signal of driver circuitry  20  to conductor  52   b  via lead  42   b . (If desired to improve the driving capability, the circuitry shown in FIG. 2 c  can be further configured as indicated by the dotted line connection  42   a  to connect both output legs of the circuitry represented by element  40  to conductor  52   b .) Once again, elements of the generalized driver module  10  that are not used in FIG. 2 c  are omitted from that FIG. and can be similarly omitted from the programmable logic device for instances of customized driver module  10   c  if desired. 
     FIG. 2 d  is similar to FIG. 2 c  except that it shows hardware-configuration of a driver module for use in bi-directional re-buffering between two relatively long horizontal conductors  52   a  and  52   b.    
     FIG. 2 e  is similar to FIG. 2 d  except that it shows hardware-configuration of a driver module as what may be called a “tri-directional” buffer  10   e . Buffer  10   e  acts like a bi-directional buffer (as in FIG. 2 d ), plus a logic input via lead  34  can reach either or both of the left and right routing conductors  52   a  and  52   b.    
     FIG. 3 shows an alternative embodiment of a generalized driver module  100  in accordance with the invention. Driver module  100  has all the same (or similar) elements that driver module  10  has. In FIG. 3 those elements that are essentially repeated from FIG. 1 have the same reference numbers that are used in FIG.  1 . In addition to those elements, however, driver module  100  also has other elements. These additional elements have reference numbers in the  100  series. The additional elements of driver module  100  enable that module to additionally serve other interconnection conductors. For example, conductor  162   a  may be an upwardly extending vertical interconnection conductor on a programmable logic device, and conductor  162   b  may be a downwardly extending vertical interconnection conductor on the device. Each of elements  160   a  and  160   b  may be similar to any of above-described elements  50 . Leads  144  and  164   b  are additional output connections from element  40 , while leads  146  and  164   a  are additional inputs to element  30 . 
     With the addition of possible connections to vertical interconnection conductors  162 , driver module  100  can be hardware-customized to perform still more tasks. For example, driver module  100  can be used to drive the output signal  34  of a logic region onto one or both of vertical conductors  162   a  and  162   b . Alternatively, driver module  100  can be used to drive a signal from any of horizontal interconnection conductors  52   a-d  onto either or both of vertical interconnection conductors  162   a  and  162   b . As still another alternative, driver module  100  can be used to drive a signal from either of vertical interconnection conductors  162  onto any or all of horizontal conductors  52   a-d . Or driver module  100  can be use for uni-directional re-buffering in either direction between vertical interconnection conductors  162 , or for bi-directional re-buffering between those two vertical interconnection conductors. Whatever the task to be performed by any instance of driver module  100 , the hardware of the various elements of that driver module instance are configured appropriately to that task in the same general way that various exemplary instances of driver module  10  are customized in FIGS. 2 a - 2   e.    
     Although leads  34  are illustratively described above as conveying logic region output signals, leads  34  may be alternatively used for other types of signals such as input signals from circuitry that is external to the device that includes the driver modules or from other interconnection conductors on the device. Similarly, one or more of leads  52  or  162  may convey input and/or output pin signals of the device. 
     Another aspect of the invention is illustrated by FIG.  4 . This FIG. shows a representative portion of programmable logic and programmable interconnection circuitry on a programmable logic device  230 . In particular, FIG. 4 shows several representative regions of programmable logic  210  in one representative row of such regions on device  230 . FIG. 4 also shows horizontal interconnection conductors  220  that are associated with the depicted row of logic regions  210  and that are provided for conveying signals to, from, and/or between the logic regions in the row. Each of diamonds  200  represents one or more instances of driver modules  10  or  100  or any other suitable driver circuitry. Each of logic regions  210  can receive input signals from any of the adjacent conductors via programmable logic connectors  250  and region-feeding conductors  252 . (Only a very few representative ones of elements  250  and  252  are shown in FIG. 4 to avoid over-crowding the drawing.) 
     Each logic region  210  produces one or more output signals (i.e., M output signals in the general case) which are applied to N instances of driver modules  200  that are associated with that logic region. For example, logic region  210   a   1  produces M output signals that are applied to N instances  200   a   1  of the driver module. N is typically at least equal to M so that each logic region output signal is applied to at least a respective one of driver modules  200 . Preferably N is greater than M so that each logic region output signal can be applied to a respective two or more instances of driver module  200 . There may also be some overlap between the instances of driver modules  200  that are used for each logic region output signal. In other words, a driver module  200  may receive more than one of the associated logic region output signals. (For ease of reference herein it is assumed that M and N are both greater than one, although it will be understood that M can be one and that N can also be one if desired.) 
     Each instance of a driver module  200  is disposed between a leftward extending horizontal interconnection conductor  220  and a rightward extending horizontal interconnection conductor  220 . For example, each instance of driver module  200   a   1  is disposed between one of N horizontal conductors  220  extending to left from driver modules  200   a   1  and one of N horizontal conductors  220  extending to the right from those driver modules. 
     The driver modules  200  associated with each of logic regions  210  are located in the same layout tile. Thus, when, in the design of a device that uses the FIG. 4 circuitry, tiles are “copied and pasted” to form rows of regions  210 , driver modules  200  are automatically evenly distributed across each row. These hardware-configurable driver modules can then be metal-configured differently to meet the different requirements in different regions. In the depicted embodiment the pattern of driver modules  200  repeats after eight horizontally adjacent logic regions  210 . Thus each conductor  220  extends from a driver module  200  past seven adjacent logic regions  210  before encountering another driver module  200  associated with an eighth adjacent logic region  210 . As a specific example of this consider a conductor  220   e  located near the center of FIG.  4 . Such a conductor extends to the right from a driver module instance  200   e   1  past logic regions  210   f   1 ,  210   g   1 ,  210   h   1 ,  210   a   2 ,  210   b   2 ,  210   c   2 , and  210   d   2  to a driver module instance  200   e   2 . 
     The effect of the pattern of driver modules  200  and conductors  220  shown in FIG. 4 is to make all of conductors  220  the same length between horizontally adjacent driver modules. This conductor length can be chosen to be the optimal length for a conductor before the signal on that conductor needs to be re-buffered. With an arrangement of the type shown in FIG. 4 it is known that each logic region output signal is always driven onto the end of a conductor segment  220 . It is also known that the remote end of that conductor segment  220  is a fixed distance away from the input end and that a re-buffering driver module  200  is available at that remote end for re-buffering the signal onto another horizontally adjacent segment if the signal needs to be propagated beyond the circuitry reachable from the first segment. 
     As a specific example of the foregoing, consider an output signal from logic region  210   e   1 . Such a signal can be applied to the left-hand end of a conductor segment  220   e  extending to the right from a driver module  200   e   1 . The signal on that conductor segment  220   e  can be applied to any of the logic regions  210   f   1 - 210   d   2  (and possibly also  210   e   1  and  210   e   2 ) by logic-region-feeding conductors like conductors  252 . At the right-hand end of the conductor segment  220   e  being discussed that conductor segment encounters a driver module  200   e   2 . If the signal on the conductor segment  220   e  being discussed is needed by logic regions  210  farther to the right, the immediately above-mentioned driver module  200   e   2  can be used to re-buffer that signal and to apply the re-buffered signal to another conductor segment  220   e  extending to the right from that driver module. 
     Because the starting point of the signal on each conductor segment  220  is always adjacent one end of that segment, because the conductor segments are of known length, because a driver module  200  is available at each end of each segment, and because the conductor segment lengths are selected so that a signal traversing the length of a conductor segment will be in need of re-buffering as it reaches a driver module  200  capable of providing that re-buffering, an arrangement of elements like that shown in FIG. 4 helps make signal propagation throughout device  230  more uniform and predictable. In addition, once a signal is on a conductor segment  220 , it is known that the signal is available to a substantial number of logic regions  210  (i.e., all the logic regions passed by that conductor segment) without any further driver delays being introduced into at least that much propagation of the signal. All of these considerations facilitate reliable, high-speed operation of device  230 . 
     It will be appreciated that adjacent the edges of device  230  some of conductor segments  220  will have to be made shorter than the length otherwise used for such segments. However, at these locations bi-directional re-buffering capabilities may not be needed. Accordingly, instances of driver modules  200  adjacent the edges of device  230  can be hardware-configured as tri-state drivers (e.g., for selectively driving signals from input pins, input/output pins, or adjacent logic regions  210  onto conductor segments  220 , or for selectively driving signals from such conductor segments  220  onto output or input/output pins). FIG. 5 shows an example of inclusion of such tri-state drivers  240  near edges of device  230 . FIG. 5 also shows relatively short edge segments of conductors  220  short-circuited to the adjacent longer segments of those conductors to eliminate the overhead of re-buffering for very short segments of wire. This short-circuiting is shown for the two lower left and two upper right conductor groups in FIG.  5 . These are also the conductor groups shown with tri-state drivers  240 . 
     Some of the advantages of the circuitry of this invention are as follows: 1. it eliminates delay overhead of crossing fixed re-buffering or hierarchical boundaries; 2. it provides optimal buffering from source and destination points, whether the destination point is before or after several staggered drivers; 3. it provides higher noise immunity because it allows shielding of signal drivers from unused wires and also shields from unused diffusion loading; 4. it decreases routing channel requirements when unstitched metal lines (e.g., horizontally adjacent conductor segments  220 ) can be used independently; and 5. it can improve speed by re-distributing fan-out (because non-critical paths can be off-loaded by turning onto another driver using a lead  34  to convey a signal from one interconnection conductor to another). 
     FIG. 6 illustrates a programmable logic device  300  constructed in accordance with the present invention in a data processing system. Thus device  300  may be constructed using hardware-configurable driver modules like those shown in FIGS. 1-3 and/or with driver module arrangements like those shown in FIGS.  4  and/or  5 . Data processing system  302  may include one or more of the following components: a processor  304 ; memory  306 ; I/O circuitry  308 ; and peripheral devices  310 . These components are coupled together by a system bus  320  and are populated on a circuit board  330  which is contained in an end-user system  340 . 
     System  302  can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. Programmable logic device  300  can be used to perform a variety of different logic functions. For example programmable logic device  300  can be configured as a processor or controller that works in cooperation with processor  304 . Programmable logic device  300  may also be used as an arbiter for arbitrating access to a shared resource in system  302 . In yet another example, programmable logic device  300  can be configured as an interface between processor  304  and one of the other components in system  302 . It should be noted that system  302  is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims. 
     It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example the driver modules  200  used as shown in FIGS. 4 and 5 do not have to be the hardware-configurable driver modules shown in the earlier FIGS. Instead, driver modules  200  can be programmably controlled driver circuits (e.g., those shown in FIG. 8 of Reddy et al. U.S. Pat. No. 5,977,793, which is hereby incorporated by reference herein in its entirety). 
     Most programmable logic devices have more than one row of logic regions, thereby creating a two-dimensional array of intersecting rows and columns of logic regions. Vertical interconnection conductors (like conductors  162  in FIG. 3) may be associated with the columns of logic regions, and a vertically offset or staggered driver module pattern analogous to the horizontally offset or staggered patterns shown in FIGS. 4 and 5 may be alternatively or additionally employed in the vertical interconnection conductors. 
     It will be understood that various directional and orientational terms such as “vertical” and “horizontal”, “left” and “right”, “row” and “column”, and the like are used herein only for convenience, and that no fixed or absolute directional or orientational limitations are intended by the use of these words. For example, the devices of this invention can have any desired orientation. If reoriented, different directional or orientational terms may need to be used in their description, but that will not alter their fundamental nature as within the scope and spirit of the invention. 
     It will also be understood that any suitable logic can be used in logic regions  210 . For example, sum-of-products logic, look-up table logic, or any other type of logic can be used. Similarly, any of many different technologies can be used to make devices in accordance with the invention. Examples of suitable technologies include EPROMs, EEPROMs, pass transistors, transmission gates, fuses, antifuses, laser fuses, metal optional links, SRAMs, DRAMs, FIFO memories, function control registers (e.g., as in Wahlstrom U.S. Pat. No. 3,473,160), ferro-electric memories, and the like. The programmable logic devices of this invention can be one-time-only programmable or reprogrammable.