Abstract:
A field emission display apparatus includes a plurality of emitters formed on a substrate. Each of the emitters includes a titanium silicide nitride outer layer so that the emitters are less susceptible to degradation. A dielectric layer is formed on the substrate and the emitters, and an opening is formed in the dielectric layer surrounding each of the emitters. A conductive extraction grid is formed on the dielectric layer substantially in a plane defined by the emitters, and includes an opening surrounding each of the emitters. A cathodoluminescent faceplate having a planar surface is disposed parallel to the substrate.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a divisional of pending U.S. Patent Application Ser. No. 09/130,634, filed Aug. 6, 1998, now U.S. Pat. No. 6,323,000. 
    
    
     GOVERNMENT RIGHTS 
     This invention was made with government support under Contract No. DABT63-93-C-0025 awarded by Advanced Research Projects Agency (ARPA). The government has certain rights in this invention. 
    
    
     TECHNICAL FIELD 
     This invention relates in general to visual displays for electronic devices and more particularly to improved emitters for field emission displays. 
     BACKGROUND OF THE INVENTION 
     FIG. 1 is a simplified side cross-sectional view of a portion of a field emission display  10  including a faceplate  20  and a baseplate  21  in accordance with the prior art. FIG. 1 is not drawn to scale. The faceplate  20  includes a transparent viewing screen  22 , a transparent conductive layer  24  and a cathodoluminescent layer  26 . The transparent viewing screen  22  supports the layers  24  and  26 , acts as a viewing surface and as a wall for a hermetically sealed package formed between the viewing screen  22  and the baseplate  21 . The viewing screen  22  may be formed from glass. The transparent conductive layer  24  may be formed from indium tin oxide. The cathodoluminescent layer  26  may be segmented into pixels yielding different colors for color displays. Materials useful as cathodoluminescent materials in the cathodoluminescent layer  26  include Y 2 O 3 :Eu (red, phosphor P-56), Y 3 (Al, Ga) 5 O 12 :Tb (green, phosphor P-53) and Y 2 (SiO 5 ):Ce (blue, phosphor P-47) available from Osram Sylvania of Towanda Pa. or from Nichia of Japan. 
     The baseplate  21  includes emitters  30  formed on a planar surface of a substrate  32 . The substrate  32  is coated with a dielectric layer  34 . In one embodiment, this is effected by deposition of silicon dioxide via a conventional TEOS process. The dielectric layer  34  is formed to have a thickness that is less than a height of the emitters  30 . This thickness is on the order of 0.4 microns, although greater or lesser thicknesses may be employed. A conductive extraction grid  38  is formed on the dielectric layer  34 . The extraction grid  38  may be formed, for example, as a thin layer of doped polysilicon. The radius of an opening  40  created in the extraction grid  38 , which is also approximately the separation of the extraction grid  38  from the tip of the emitter  30 , is about 0.4 microns, although larger or smaller openings  40  may also be employed. 
     The baseplate  21  also includes a field effect transistor (“FET”)  50  formed in the surface of the substrate  32  for controlling the supply of electrons to the emitter  30 . The FET  50  includes an n-tank  52  formed in the surface of the substrate  32  beneath the emitter  30 . The n-tank  52  serves as a drain for the FET  50  and may be formed via conventional masking and ion implantation processes. The FET  50  also includes a source  54  and a gate electrode  56 . The gate electrode  56  is separated from the substrate  32  by a gate oxide  57  and a field oxide layer  58 . The emitter  30  is typically about a micron tall, and several emitters  30  are generally included together with each n-tank  52 , although only one emitter  30  is illustrated. 
     The substrate  32  may be formed from p-type silicon material having an acceptor concentration N A  ca. 1-5×10 15 /cm 3 , while the n-tank  52  may have a surface donor concentration N D  ca. 1-2×10 16 /cm 3 . 
     In operation, the extraction grid  38  is biased to a voltage on the order of 40-80 volts, although higher or lower voltages may be used, while the substrate  32  is maintained at a voltage of about zero volts. Signals coupled to the gate  56  of the FET  50  turn the FET  50  on, allowing electrons to flow from the source  54  to the n-tank  52  and thus to the emitter  30 . Intense electrical fields between the emitter  30  and the extraction grid  38  then cause field emission of electrons from the emitter  30 . A larger positive voltage, ranging up to as much as 5,000 volts or more but often 2,500 volts or less, is applied to the faceplate  20  via the transparent conductive layer  24 . The electrons emitted from the emitter  30  are accelerated to the faceplate  20  by this voltage and strike the cathodoluminescent layer  26 . This causes light emission in selected areas, i.e., those areas adjacent to where the FETs  50  are conducting, and forms luminous images such as text, pictures and the like. Integrating the FETs  50  in the substrate  32  to provide an active display  10  (i.e., a display  10  including active circuitry for addressing and providing control signals to specific emitters  30 , etc.) yields advantages in size, simplicity and ease of interconnection of the display  10  to other electronic componentry. 
     When the emitted electrons strike the cathodoluminescent layer  26 , compounds in the cathodoluminescent layer  26  dissociate. This causes outgassing of materials from the cathodoluminescent layer  26 . When the outgassed materials react with the emitters  30 , a barrier height of the emitters  30  may increase. When the emitter barrier height increases, the emitted current is reduced. This reduces the luminance of the display  10 . 
     Residual gas analysis indicates that the dominant materials outgassed from some display cathodoluminescent layers  26  include oxygen and hydroxyl radicals. This leads to oxidation of the emitters  30  and especially emitters  30  formed from silicon. Silicon emitters  30  are useful because they are readily formed and integrated with other electronic devices on silicon substrates. Electron emission is reduced when silicon emitters  30  oxidize. This degrades performance of the display  10 . 
     Therefore there is a need for a way to prevent degradation, and especially oxidation, of emitters  30  used in displays  10 . 
     SUMMARY OF THE INVENTION 
     In accordance with an aspect of the invention, a field emission display has a plurality of emitters including titanium silicide nitride. The plurality of emitters is formed on a substrate that is part of a baseplate. A dielectric layer is formed on the substrate, a semiconductor device formed in or on the substrate for controlling the flow of electrons to the emitters, and the plurality of emitters. The display includes an extraction grid formed in a plane defined by tips of the plurality of emitters. The extraction grid includes an opening surrounding and in close proximity to each tip of the plurality of emitters. Significantly, the tips include titanium silicide nitride. 
     As a result, the emitters are markedly more resistant to reaction with compounds released from the cathodoluminescent layer by electron bombardment than are silicon emitters. This results in a robust display that resists emitter degradation the emitters may also exhibit increased emissivity due to reduced work function provided by titanium silicide nitride compared to the work function of silicon. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified side cross-sectional view of a portion of a display including a faceplate and a baseplate in accordance with the prior art. 
     FIG. 2 is a simplified side cross-sectional view of a portion of a display according to an embodiment of the present invention. 
     FIG. 3 is a simplified side cross-sectional view of a portion of a baseplate for the display at one stage in manufacturing according to an embodiment of the present invention. 
     FIG. 4 is a simplified side cross-sectional view of a portion of a baseplate for the display at a later stage in manufacturing according to an embodiment of the present invention. 
     FIG. 5 is a simplified side cross-sectional view of a portion of a baseplate for the display at a still later stage in manufacturing according to an embodiment of the present invention. 
     FIG. 6 is a flow chart of a process for manufacturing a baseplate for the display according to an embodiment of the present invention. 
     FIG. 7 is a simplified block diagram of a computer using the emitter according to an embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2 is a simplified side cross-sectional view of a portion of a field emission display  10 ′ in accordance with one embodiment of the present invention. FIG. 2 is not drawn to scale. Many of the components used in the display  10 ′ shown in FIG. 2 are identical to components used in the display  10  of FIG.  1 . Therefore, in the interest of brevity, these components have been provided with the same reference numerals, and an explanation of them will not be repeated. 
     It has been discovered that coating at least the tips of the emitters  30  with a titanium silicide nitride layer  70  provides significant advantages when the emitter  30  is used in the display  10 ′. In one embodiment, the advantages include improved resistance to chemical poisoning of the emitters  30  from materials that are outgassed from the cathodoluminescent layer  26  in response to electron bombardment. This provides improved lifetime for the emitter  30  and therefore for the display  10 ′ incorporating the emitter  30 . Coating at least tips of the emitters  30  with the titanium silicide nitride layer  70  also provides a decreased work function compared to silicon emitters  30 , resulting in increased current from each emitter  30  together with reduced turn-on voltage. 
     FIGS. 3 through 6 illustrate a portion of the baseplate  21 ′ for the display  10 ′ of FIG. 2 at various stages in manufacturing according to an embodiment of the present invention. As shown in FIG. 3, an emitter  30  has been fabricated on the substrate  32 , and the substrate  32  and the emitters  30  are coated with the dielectric layer  34 . An extraction grid  38  including a conductive layer is then formed on the dielectric layer  34 . The extraction grid  38  may be formed, for example, as a thin layer of doped polysilicon, however, other materials can be employed. 
     As shown in FIG. 4, a conventional chemical-mechanical polish is carried out to remove the “hill” of dielectric material  34  and extraction grid  38  immediately above the tip of the emitter  30 . This is typically carried out via a potassium hydroxide solution that incorporates suspended particles of controlled size, which may be silicon particles. It is important that this chemical-mechanical polish not damage the tips of the emitters  30 , i.e., that the polishing process stops short of reaching these tips. 
     With reference to FIG. 5, following the chemical-mechanical polishing operation, the extraction grid  38  is used as a mask for etching the dielectric layer  34  to expose at least the tips of the emitters  30  in the openings  40 . This has the advantage of not requiring a separate photoresist application, exposure and development, thus reducing labor content and materials requirements. This also promotes increased yields by reducing the number of processing steps. When silicon dioxide is used to form the dielectric layer  34 , this step may be carried out by etching the wafer in a conventional buffered aqueous hydrogen fluoride oxide etch or BOE. 
     As also shown in FIG. 5, following etching of the dielectric layer  34  to expose at least the tip of the emitter  30 , a titanium silicide nitride layer  70  is formed on the emitter  30  by a process explained below with reference to FIG.  6 . 
     FIG. 6 is a flow chart of a process  80  for manufacturing emitters  30  according to an embodiment of the present invention. The substrate  32  having a plurality of the emitters  30  has been previously formed, and the surface of the substrate  32  and the emitters  30  have been previously coated with the dielectric layer  34 . The extraction grid  38  has been previously deposited, and the chemical-mechanical polish and etch have been previously carried out to expose at least the tips of the emitters  30 . Optional step  82  removes any native oxide from the emitters  30 , via, e.g., a conventional hydrogen fluoride etching step. Other methods for removal of native oxide are also suitable for use with the present invention, provided that the oxide removal process does not blunt the tips of the emitters  30 . 
     In step  84 , a layer of titanium is formed over the surface of the extraction grid  38  and also over at least the tips of the emitters  30 . The layer of titanium may be applied in any of several ways, including evaporation, chemical vapor deposition and the like, however, sputtering is preferred. The layer of titanium should not be so thick as to distort the tips of the emitters  30  and should be thick enough to ensure coating of the tips, i.e., to obviate formation of pinholes in the titanium layer. In one embodiment, the titanium layer is on the order of five hundred angstroms thick. 
     The titanium layer is then reacted in step  86  with the silicon forming the emitter  30  to form titanium silicide or TiSi 2 . This may be realized by rapid thermal annealing of the emitters  30  and the titanium layer, for example, at 670° C. for 30 seconds in nitrogen. Unreacted titanium may then be removed in optional step  88  by conventional etching, for example, with NH 4 OH:H 2 O 2 :H 2 O=1:1:5. 
     The titanium silicide is then reacted with nitrogen to form the titanium silicide nitride layer  70  (FIG. 5) in step  90 . This may be effected by rapid thermal annealing at a suitable temperature, such as 1050° C., in ammonia for a suitable period, such as 90 seconds. The process  80  then ends and other conventional processing steps for forming field emission displays  10 ′ are carried out. 
     It will be understood that while rapid thermal annealing is employed in one embodiment, other forms of heat treatment may be used to react the titanium to form titanium silicide and to react the titanium silicide to form titanium silicide nitride. For example, titanium and silicon may be reacted by heating in an oven at 700° C. for half an hour. It will also be understood that emitters  30  including titanium silicide nitride may be made via other processes. 
     The process  80  illustrated via FIG. 6 results in an emitter body  30  that is coated with a titanium silicide nitride layer  70 . This provides several advantages. The titanium silicide nitride layer  70  that is formed resists attack by BOE, which is useful in subsequent processing steps when BOE is used to pattern subsequent layers. Measurements of the titanium silicide nitride layers  70  formed by the process  80  provide sheet resistivities on the order of 3.4 ohms per square. 
     Emitters  30  having a titanium silicide nitride surface layer  70  thus provide lower turn-on voltages and higher currents compared with silicon. Moreover, titanium silicide nitride is very resistant to oxidation, especially when compared to silicon, leading to improved performance and a more robust emitter  30 . However, it will be understood that the emitter  30  may be coated with a work function decreasing layer formed by other materials. Additionally, forming the layer  70  from a layer that is metallurgically alloyed to the emitter  30  provides a robust emitter  30  having reproducible characteristics. 
     The process  80  does not require any photolithographic steps and therefore has minimal impact on labor content and materials requirements. The process  80  is also consistent with increased yields due to simplification of device processing. It is completely self aligned, promoting higher yields by avoiding some error sources. 
     FIG. 7 is a simplified block diagram of a portion of a computer  100  using the display  10 ′ fabricated as described with reference to FIGS. 2 through 6 and associated text. The computer  100  includes a central processing unit  102  coupled via a bus  104  to a memory  106 , function circuitry  108 , a user input interface  110  and the display  10 ′ including the emitters  30  having the titanium silicide nitride layer  70  according to the embodiments of the present invention. The memory  106  may or may not include a memory management module (not illustrated) and does include ROM for storing instructions providing an operating system and a read-write memory for temporary storage of data. The processor  102  operates on data from the memory  106  in response to input data from the user input interface  110  and displays results on the display  10 ′. The processor  102  also stores data in the read-write portion of the memory  106 . Examples of systems where the computer  100  finds application include personal/portable computers, camcorders, televisions, automobile electronic systems, microwave ovens and other home and industrial appliances. 
     Field emission displays  10 ′ for such applications provide significant advantages over other types of displays, including reduced power consumption, improved range of viewing angles, better performance over a wider range of ambient lighting conditions and temperatures and higher speed with which the display can respond. Field emission displays  10 ′ find application in most devices where, for example, liquid crystal displays find application. 
     Although the present invention has been described with reference to specific embodiments, the invention is not limited to these embodiments. Rather, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described.