Abstract:
A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface; forming a molding compound layer over the dies, wherein the top surface of the dies are covered by the molding compound layer; removing a first portion of the molding compound layer; removing a second portion of the molding compound layer such that the top surface of the dies is not covered by the molding compound layer; forming a redistribution layer (RDL) over the top surface of the dies; forming a plurality of solder balls over at least a portion of the RDL; and singulating the dies.

Description:
BACKGROUND 
       [0001]    Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
         [0002]    The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications. 
         [0003]    Thus, packages such as wafer level packaging (WLP) have begun to be developed, in which integrated circuits (ICs) are placed on a carrier having wiring for making connection to the ICs and other electrical components. In the WLP process, grinding may be used. In the formation of fan-out chip scale packages, device wafers may be sawed, and the known-good-dies are selected and attached onto a carrier, with the known-good-dies spaced apart from each other. The known-good-dies include copper posts for the formation of fan-out connections. A molding compound is then filled into the space between and over the known-good-dies to form a fan-out wafer. After the curing of the molding compound, a grinding process may be performed to remove the portions of the molding compound and other dielectric materials over the copper posts. After the copper posts are exposed, electrical connections may be made to connect to the copper posts, so that the connections to the fan-out wafer are extended into an area larger than the area of the known-good-dies. 
         [0004]    Since the layers that are subject to the grinding are often thin layers, accurately stopping the grinding process at the right time is vital to the yield of the integrated manufacturing process. For example, in the manufacturing of the fan-out wafer, the grinding needs to be stopped when the copper posts in substantially all known-good-dies throughout the fan-out wafer are fully exposed, and substantially no over-grinding occur. In the existing grinding technology, a gauge is used to detect the total thickness of the fan-out wafer during the grinding process. When the total thickness is reduced to a pre-determined value, it is assumed that the copper posts are fully exposed. This detection method, however, is inaccurate, and may result in yield loss. 
         [0005]    Thus, an improved grinding process is needed to increase the yield of the packaging process. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0006]    For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
           [0007]      FIG. 1  shows a flow chart of a method for packaging semiconductor dies according to embodiments of the present disclosure; and 
           [0008]      FIGS. 2 through 10  illustrate cross-sectional views of a method of packaging semiconductor dies in a FO-WLP at various stages in accordance with embodiments of the present disclosure. 
       
    
    
       [0009]    Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. 
       DETAILED DESCRIPTION 
       [0010]    The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure. 
         [0011]      FIG. 1  illustrates a flow chart of a method  100  for packaging semiconductor dies according to embodiments of the present disclosure. Method  100  begins with a step  110  in which semiconductor dies are attached to a carrier wafer. Method  100  continues with a step  120  in which a molding compound layer is formed on the carrier wafer. Method  100  continues with a step  130  in which a first portion of molding compound layer is removed at least from a top surface of semiconductor dies. Method  100  continues with a step  140  in which a second portion of molding compound layer is removed such that the top surface of each semiconductor die is exposed. Method  100  continues with a step  150  in which a passivation layer is formed over the molding compound layer and the top surface of each semiconductor die. Method  100  continues with a step  160  in which a RDL layer is formed over the passivation layer and the top surface of each semiconductor die. Method  100  continues with a step  170  in which solder balls are formed. Method  100  continues with a step  180  in which each packaged semiconductor die is singulated. 
         [0012]      FIGS. 2 through 10  show cross-sectional views of a method of packaging semiconductor dies in a FO-WLP in accordance with embodiments of the present disclosure. 
         [0013]    Referring back to  FIG. 1 , in step  110 , multiple semiconductor dies are attached to a carrier wafer via die attach film (DAF) in embodiments of the present disclosure. As shown in  FIG. 2 , several dozens or even hundreds of dies  1000  may have been manufactured and/or packaged on a substrate and then separated from the same substrate. In embodiments of the present disclosure, dies  1000  may comprise semiconductor devices or integrated circuits. Dies  1000  may comprise one or more layers of electrical circuitry and/or electronic functions formed thereon, and may include conductive lines, vias, capacitors, diodes, transistors, resistors, inductors, and/or other electrical components (not shown) in embodiments of the present disclosure. 
         [0014]    Referring to  FIG. 3 , a plurality of dies  1000  are attached to a carrier wafer  1020  via a DAF film  1010 . The number of dies  1000  attached to carrier wafer  1020  may depend on the size of dies  1000 , the size of carrier wafer  1020 , and the particular application(s) of each dies  1000  as disclosed in embodiments of the present disclosure. In embodiments of the present disclosure, carrier wafer  1020  may be made with Silicon (Si), Germanium (Ge), glass, III-V compound or other materials. Each die  1000  may have a front side and a back side for purposes of the discussion herein. A pick and place apparatus and method may be used to place each die  1000  in a predetermined location on carrier wafer  1020 , as shown in  FIG. 3 . Back side of dies  1000  are attached to DAF film  1010 , as shown in  FIG. 3 . 
         [0015]    In embodiments of the present disclosure, the top surface of each die  1000  may function as an active surface coupling active and passive devices, conductive layers, and dielectric layers according to the electrical design of each die  1000 , as illustrated in  FIG. 3 . In embodiments of the present disclosure, a conductive layer is formed as a contact pad  1025  on the top surface of each die  1000  using a patterning and deposition process. Dies  1000  may have a plurality of contact pads  1025 . Contact pads  1025  may be made with aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other electrically conductive material. The deposition of contact pads  1025  may use an electrolytic plating or electroless plating process. The size, shape, and location of contact pads  1025  illustrated in  FIG. 3  are only for illustration purposes and are not limiting. The plurality of contact pads  1025  of each die  1000  may be of the same size or of different sizes. 
         [0016]    It should be noted that in conventional a WLP packaging process, the top surface of each semiconductor die may be covered with a carrier tape to protect the top surface of the semiconductor dies. However, in embodiments of the present disclosure, the top surface of each die  1000  may not be covered with such carrier tape. 
         [0017]    Referring back to  FIG. 1 , in step  120 , multiple dies  1000  may be overmolded with a molding compound layer  1030  using a compression molding process, as shown in  FIG. 4 . Molding compound layer  1030  may be used for encapsulating dies  1000  by covering dies  1000  and filling the gaps between dies  1000 , as shown in  FIG. 4 . In embodiments of the present disclosure, molding compound layer  1030  may be made with epoxy resin or other encapsulating materials. 
         [0018]    Referring back to  FIG. 1 , in step  130 , a first portion of molding compound layer  1030  is removed at least from the top surface of dies  1000 , as shown in  FIG. 5 . In embodiments of the present disclosure, a grinding process may be performed to remove a portion of molding compound layer  1030  such that the remaining molding compound layer  1030  still covers the top surface of each die  1000  and the gaps between dies  1000 , as shown in  FIG. 5 . 
         [0019]    Referring back to  FIG. 1 , in step  140 , a second portion of molding compound layer  1030  is removed to expose the top surface of dies  1000 , as shown in  FIG. 6 . In embodiments of the present disclosure, an etching process may be performed to further remove a portion of molding compound layer  1030  such that the top surface of each die  1000  are uncovered and contact pads of each die  1000  are exposed, as shown in  FIG. 6 . In embodiments of the present disclosure, the etching process may be a single or a multiple step etching process. Further, the etching process may include wet etching, dry etching, or a combination thereof. The dry etching process may be an anisotropic etching process. The etching process may use reactive ion etch (RIE) and/or other suitable process. The RIE materials may be selected based on the materials of molding compound layer  1030 . In one example, a dry etching process used to etch molding compound layer  1030  includes fluorine-containing gas such as CF4, SF6, or NF3. 
         [0020]    In conventional die packaging methods, the top surface of each die may be covered with a carrier tape when dies are attached to DAF film. Then, molding compound layer is formed over the dies with the carrier tape. Then, a polishing process, using chemical mechanical polishing (CMP) process or a grinding process, for example, is performed to remove the molding compound layer deposited over dies such that the top surface of the dies will be uncovered (i.e. no longer covered by the molding compound layer). Accordingly, the top surface of molding compound layer and the top surface of dies are substantially the same. During the CMP process, the carrier tapes on the top surface of dies are used as a polishing stop indication. In embodiments of the present disclosure, a pad used in the CMP process includes a detecting device for detecting the change(s) of the materials being polished. For example, the detecting device is capable of detecting the density of the materials being polished. Accordingly, when the molding compounds are removed and the carrier tapes on the top surface of the dies are exposed to the pad during the CMP process, the detecting device will be able to detect the differences of the density between the molding compound material and the carrier tapes. Upon the detection of the carrier tapes on the top surface of dies, the CMP process will stop so that the carrier tapes will act like a polishing stop indication. In addition, the carrier tapes also function as protective layers to protect the dies from being damaged by the CMP process. After the CMP process, the carrier tapes attached on the top surface of the dies are removed such that contact pads of dies are exposed. 
         [0021]    Referring to  FIGS. 2 through 6 , in embodiments of the present disclosure, the top surface of each die  1000  may not be covered with the carrier tape when dies  1000  are singulated from the substrate and then attached to DAF film  1010  of carrier wafer  1020 . Accordingly, when molding compound layer  1030  is formed over carrier wafer  1020 , dies  1000  being covered by molding compound layer  1030  may not include carrier tape to protect the top surface of dies  1000 . In embodiments of the present disclosure, the removing of molding compound layer  1030  is performed by two steps, as shown in  FIGS. 5 and 6 . The first molding compound removal step may remove only a portion, but not all, of molding compound layer  1030  covering the top surface of dies  1000 , as shown in  FIG. 5 . The first molding compound removal step may be performed by a grinding process or a CMP process. In the second molding compound removal step, the remaining portion of molding compound layer  1030  covering the top surface of dies  1000  may be removed to expose contact pads  1025  of dies  1000 , as shown in  FIG. 6 . The second molding compound removal step may be performed by etching process. The etching process may be a single or a multiple step etching process. Further, the etching process may include wet etching, dry etching, or a combination thereof. The dry etching process may be an anisotropic etching process. The etching process may use reactive ion etch (RIE) and/or other suitable process. In one example, a dry etching process is used to etch the remaining portion of molding compound layer  1030 . In furtherance of the example, the chemistry of the dry etch includes CF4, SF6, or NF3. Compared to the grinding or CMP process, the etching process may be more selective and specific such that only molding compound layer  1030  may be removed without damaging dies  1000 . Accordingly, tape carriers for protecting the top surface of dies  1000  may not be needed in embodiments of the present disclosure. 
         [0022]    Referring back to  FIG. 1 , in step  150 , a passivation layer (not shown) is formed over dies  1000  and molding compound layer  1030 . In embodiments of the present disclosure, the passivation layer may be formed over dies  102  on the top surface and on top of contact pads  1025  for structural support and physical isolation. The passivation layer may be made with silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other insulating material. An opening  1040  of the passivation layer may be made by removing a portion of the passivation layer using a mask-defined photoresist etching process to expose opening  1040 . The size, shape, and location of openings  1040  are only for illustration purposes and are not limiting. It is advantageous to expose contact pads  1025  of dies  1000  within openings  1040 , as shown in  FIG. 7 . 
         [0023]    Referring back to  FIG. 1 , in step  160 , a RDL layer  1050  is formed over the passivation layer (not shown) and openings  1025 . As shown in  FIG. 7 , RDL layer  1050  may be deposited over the passivation layer and contact pads  1025 . RDL layer  1050  may be deposited following the contour of the passivation layer. In embodiments of the present disclosure, RDL layer  1050  may be made with, e.g., Al, Ni, nickel vanadium (NiV), Cu, or a Cu alloy. In other embodiments of the present disclosure, RDL layer  1050  may be made by an electrolytic plating or electroless plating process. In the embodiment illustrated in  FIG. 7 , RDL layer  1050  may be made with Cu. In addition, in embodiments of the present disclosure, RDL layer  1050  may be made with a single layer, or multiple layers using an adhesion layer of Ti, TiW, or Cr, for example. Each die  1000  may be connected to a number of RDL layers  1050  to form a network of interconnections which may electrically connect to contact pad(s)  1025  of dies  1000  according to the function of the semiconductor devices formed in each die  1000 . 
         [0024]    Referring back to  FIG. 1 , in step  170 , solder balls  1060  may be mounted on the top surface of RDL layer  1050  close to at least one stacking via, as illustrated in  FIG. 8 . In embodiments of the present disclosure, solder balls  1060  may be any metal or electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof, or mixtures of other electrically conductive material. In embodiments of the present disclosure, dies  1000  may comprise a plurality of contact pads  1025 , as shown in  FIG. 7 , connected to a plurality of solder ball/bumps  120  through a network of RDL layers  1050  according to the functional design of semiconductor devices in each die  1000 . The electrical signals from dies  1000  are routed through the network of RDL layers  1050  to one or more of the solder balls  1060  according to the function of the semiconductor devices in each die  1000 . 
         [0025]    Referring to  FIG. 1 , in step  180 , dies  1000  are singulated as separate packaged dies  1080 , as shown in  FIG. 10 . Dies  1000  may be separated along singulation lines  1070  to form individual packaged dies  1080  in embodiments of the present disclosure. 
         [0026]    Although some embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.