Abstract:
A charging circuit with an application system thereof provides an error amplifier to control a transistor switch for controlling the charging power source to charges the battery. When the voltage difference between the power source and load terminals of the transistor switch drops along with the transistor switch being turned on, the output voltage of the error amplifier changes as well to increase the turning-on resistance of the transistor switch such that the voltage difference between the power source and load terminals is capable of maintaining at a value above a certain reference level for avoiding the unstable state resulting from the charging circuit being turned on and off frequently.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a charging circuit, and particularly to a charging circuit with an application system capable of preventing from the circuit being frequently turned on and off. 
     2. Brief Description of the Related Art 
     The application of the power supply circuit employed in the field of the power generation with the solar energy usually provides a charging circuit to charge the battery for storing the superfluous electric power generated from the solar energy. When the generated power is insufficient at night or on the cloudy day, the stored power can be supplied to the load to achieve the purpose of power regulation. 
     Please referring to  FIG. 1 , the conventional charging circuit application system is illustrated. It can be seen in  FIG. 1  that the charging circuit utilizes the output voltage V C  of the comparator  14 , which connects with the gate of the PMOS field effect transistor  12 , to control if the PMOS field effect transistor  12  is in a state of being turned on to attain the purpose of controlling the charging power source  11  charging the battery  13 . When the voltage V IN  of the charging power source  11  gradually increases as shown in  FIG. 2  to a state of the voltage difference V 1-B  between the source voltage V I  and the drain voltage V B  of the PMOS field effect transistor  12  being higher than the preset upper limit voltage V RT , the PMOS field effect transistor  12  is controlled by the output voltage V C  of the comparator  14  to be turned on and start charging. 
     Meanwhile, the voltage divisions of the wire resistors  15 ,  16  allow the voltage difference V 1-B  entering the two input ends of the comparator  14  drops. Assume the resistance of the respective resistor  15 ,  16  is R WIRE , and the turning-on resistance of the PMOS field effect transistor  12  is R CHG , then the voltage difference V 1-B  is expressed in the following equation (1): 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       I 
                       ⁢ 
                       
                         - 
                       
                       ⁢ 
                       B 
                     
                   
                   = 
                   
                     
                       R 
                       CHG 
                     
                     × 
                     
                       
                         
                           V 
                           IN 
                         
                         - 
                         
                           V 
                           BAT 
                         
                       
                       
                         
                           R 
                           WIRE 
                         
                         + 
                         
                           R 
                           CHG 
                         
                         + 
                         
                           R 
                           WIRE 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     When the voltage difference V 1-B  drops to the lower limit voltage V FT , PMOS field effect transistor  12  is turned off due to being controlled by the output voltage V C  of the comparator  14 . This unstable state continues till the condition of the following equation (2) is reached. Hence, the preceding circuit is deficient. 
     
       
         
           
             
               
                 
                   
                     V 
                     IN 
                   
                   &gt; 
                   
                     
                       
                         
                           
                             R 
                             WIRE 
                           
                           + 
                           
                             R 
                             CHG 
                           
                           + 
                           
                             R 
                             WIRE 
                           
                         
                         
                           R 
                           CHG 
                         
                       
                       × 
                       
                         V 
                         FT 
                       
                     
                     + 
                     
                       V 
                       BAT 
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     SUMMARY OF THE INVENTION 
     Accordingly, an object of the present invention is to provide a charging circuit with an application system capable of preventing the circuit from the unstable state resulting from being frequently turned on and off. 
     In order to achieve the preceding object, the charging circuit with an application system thereof according to the present invention comprises a charging power source, a battery and a charging circuit capable of controlling the operation of charging; the charging circuit comprises a transistor switch and an error amplifier. 
     Wherein, the transistor switch has a power source terminal coupling with the charging power source, a load terminal coupling with the battery, and a gate terminal; the error amplifier has a first input end, a second input end and an output end, the first input end coupling with the power source terminal, the second input end coupling with the load terminal, and the output end coupling with the gate terminal for controlling the turning-on resistance of the transistor switch in accordance with a voltage difference between the power source terminal and said load terminal such that the voltage difference is capable of maintaining at a value above a reference level for controlling the charging power source to charge the battery. 
     According to a preferred embodiment of the present invention, the error amplifier of the charging circuit comprises a gate control amplifier having the first input end, the second input end, and a control end for amplifying the voltage difference and output a control voltage via the control end; a first current source being a constant current source and coupling with the power source terminal and the gate terminal; and a second current source coupling with the control end, the gate terminal, and a ground end to control the current of the second current source by means of said control voltage such that the turning-on resistance of the transistor can be controlled substantively. 
     According to a preferred embodiment of the present invention, the transistor switch of the charging circuit is a PMOS field effect transistor or a NMOS field effect transistor. 
     As the foregoing, a charging circuit with an application system thereof according to the present invention utilizes the error amplifier capable of controlling the turning-on resistance of the transistor switch via the voltage difference between the power source terminal and the load terminal of the transistor switch as the control circuit for the charging power source charging the battery such that the turning-on resistance of the transistor switch can be increased under a condition of the increase of the charging power source before reaching a certain reference level so as to prevent the circuit from being in the unstable state resulting from being turned on and off frequently. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detail structure, the applied principle, the function and the effectiveness of the present invention can be more fully understood with reference to the following description and accompanying drawings, in which: 
         FIG. 1  is a circuit diagram illustrating the conventional charging circuit application system; 
         FIG. 2  is a graph illustrating the operational wave shape of the charging circuit application system shown in  FIG. 1 ; 
         FIG. 3  is a circuit diagram illustrating a preferred embodiment of the charging circuit application system according to the present invention; 
         FIG. 4  is a graph illustrating the operational wave shape of the charging circuit application system shown in  FIG. 3 ; and 
         FIG. 5  is a diagram illustrating another embodiment of the charging circuit application system according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to  FIG. 3 , a charging circuit application system of a preferred embodiment according to the present invention is illustrated. The charging circuit application system comprises a charging circuit, which is composed of a transistor switch such as the transistor gate of a PMOS field effect transistor  12 , and an error amplifier  30 , in addition to the charging power source  11  and the battery  13 . The PMOS field effect transistor  12  has a power source terminal  121  coupling with the charging power source  11 , a load terminal  122  coupling with the battery  13 , and a gate terminal  123 . The error amplifier  30  has an output end coupling with the gate terminal  123  of the PMOS field effect transistor  12  in addition to a positive input end  311  and a negative input end  312 . The function of the error amplifier  30  is to amplify the voltage difference V I-B  between the power source terminal  121  and the load terminal  122  for controlling ON-state resistance of the PMOS field effect transistor  12  and further controlling the charging power source  11  to charge the battery  13 . 
     The error amplifier  30  shown in  FIG. 3  comprises a gate control amplifier  31  and two current sources  32 ,  33 . The gate control amplifier  31  provides a control end  313  in addition to the positive input end  311  and the negative input end  312 . The negative input end  312  couples with the power source terminal  121  of the PMOS field effect transistor  12  and the positive input end  311  couples with the load terminal  122  of the PMOS field effect transistor  12 . The current source  32  is a constant current source and couples with the power source terminal  121  and the gate terminal  123  of the PMOS field effect transistor  12 . The current source  33  couples with the control end  313  of the gate control amplifier  31 , the gate terminal  123  of the PMOS field effect transistor  12  and the ground end respectively. 
     Referring to  FIG. 4  in company with  FIG. 3 , when the voltage V IN  of the charging power source  11  increases gradually as shown in  FIG. 4  to a state of the voltage difference V I-B  between the voltage V 1  of the power source terminal 
       121  and the voltage V B  of the load terminal  122  of the PMOS field effect transistor  12  being greater than a preset upper limit voltage V RT , the PMOS field effect transistor  12  becomes in a state of ON to start the operation of charging under the control of the voltage V C  output from the error amplifier  30 . Although the voltage difference V 1-B , which enters the positive input end  311  and the negative input end  312 , has dropped due to the division voltages of the wire resistors  15 ,  16 , it still maintains at a voltage reference level V EA  greater than the low limit voltage V FT  for shutting off the PMOS field effect transistor  12 . The operation principle for the preceding charging circuit is explained hereinafter. 
     As the preceding description, when the PMOS field effect transistor  12  is in a state of ON, the voltage difference V I-B  between the voltage V I  of the power source terminal  121  of the PMOS field effect transistor  12  and the voltage V B  of the load terminal  12  of the PMOS field effect transistor  12  decreases. Thus, the current from the current source  33  becomes decreased along with the decrease of the output voltage of the control end  313  of the gate control amplifier  31 . In this way, it is capable of adapting to the constant current of the current source  32  to maintain the voltage difference V 1-B  above the voltage reference level V EA  by means of increasing the voltage of the gate terminal  123  of the PMOS field effect transistor  12  and then increase the ON-state resistance of the PMOS field effect transistor  12 . Under this circumference, the unstable state concerning the conventional circuit being frequently OFF and ON is incapable of being met. 
     Please referring to  FIG. 5 , a charging circuit application system or another preferred embodiment according to the present invention is illustrated. Similarly, the charging circuit application system of the second embodiment includes a charging power source  11 , a charging circuit, and a battery  13 . The difference of the second embodiment from the preceding first embodiment is in that the charging circuit is composed of a NMOS field effect transistor  62  and an error amplifier  50 . 
     The NMOS field effect transistor  62  shown in  FIG. 5  includes a power source terminal  621  coupling with the charging power source  11 , a load terminal  622  coupling with the battery  13  and a gate terminal  623 . The error amplifier  50  has an output end coupling with the gate terminal  623  of the NMOS field effect transistor  62  in addition to a positive input end  511  and a negative input end  512 . The function of the error amplifier  50  is to amplify the voltage difference V I-B  between the power source terminal  621  and the load terminal  622  of the NMOS field effect transistor  62  for controlling ON-state resistance of the NMOS field effect transistor  62  and further controlling the charging power source  11  to charge the battery  13 . 
     The error amplifier  50  shown in  FIG. 5  comprises a gate control amplifier  51  and two current sources  52 ,  53 . The gate control amplifier  51  provides a control end  513  in addition to the positive input end  511  and the negative input end  512 . The positive input end  511  couples with the power source terminal  621  of the NMOS field effect transistor  62  and the negative input end  512  couples with the load terminal  622 . The current source  52  is a constant current source and couples with the power source terminal  621  and the gate terminal  623  of the NMOS field effect transistor  62 . The current source  53  couples with the control end  513  of the gate control amplifier  51 , the gate terminal  623  of the NMOS field effect transistor  62  and the ground end respectively. 
     Similarly, referring to  FIG. 4  again in company with  FIG. 5 , when the voltage V IN  of the charging power source  11  increases gradually as shown in  FIG. 4  to a state of the voltage difference V 1-B  between the voltage V 1  of the power source terminal  621  and the voltage V B  of the load terminal  622  of the NMOS field effect transistor  62  being greater than a preset upper limit voltage V RT , the NMOS field effect transistor  62  becomes in a state of ON to start the operation of charging under the control of the output voltage V C  being sent out from the error amplifier  50 . Although the voltage difference V 1-B , which enters the positive input end  511  and the negative input end  512 , may drop due to the division voltages of the wire resistors  15 ,  16 , it still maintains at a voltage reference level V EA  greater than the low limit voltage V FT  that is for shutting off the NMOS field effect transistor  12 . The operation principle for the preceding charging circuit is explained hereinafter. 
     As the preceding description, when the NMOS field effect transistor  62  is in a state of ON, the voltage difference V I-B  between the voltage V 1  of the power source terminal  621  and the voltage V B  of the load terminal  622  of the NMOS field effect transistor  62  decreases. Thus, the current from the current source  53  becomes increased along with the decrease of the output voltage of the control end  513  of the gate control amplifier  51 . In this way, it is capable of adapting to the constant current of the current source  52  to maintain the voltage difference V 1-B  above the voltage reference level V EA  by means of decreasing the voltage of the gate terminal  623  of the NMOS field effect transistor  62  and then increase the ON-state resistance of the NMOS field effect transistor  62 . Under this circumference, the unstable state resulting from the conventional circuit being frequently OFF and ON is incapable of being met. 
     While the invention has been described with referencing to a preferred embodiment thereof, it is to be understood that modifications or variations may be easily made without departing from the spirit of this invention, which is defined by the appended claims.