Abstract:
A linear voltage regulator which includes on its input side an array of switched super capacitors coupled between the power source and the load. This apparatus is capable of delivering currents typically from milliamperes to greater than several amperes at very low switching frequencies. In addition by using capacitors rather than resistors or transistor devices to drop voltage on the input side, power consumption is reduced. The array of capacitors is switched by simple analog circuitry or a switching logic with or without a processor subsystem and the capacitors themselves are of the super capacitor type, thus providing very high capacitance, and are effectively series connected during certain phases of operation with the input terminal of the conventional linear voltage regulator portion of the apparatus. Energy stored in the super capacitors during the various phases of operation is reused.

Description:
FIELD OF THE INVENTION 
     This disclosure relates to voltage regulators (power supplies) used for supplying electric current. 
     BACKGROUND 
     Voltage regulators are well-known in the electrical engineering field. They are also referred to as “power supplies” and are electronic or electrical circuits which output electric current at a particular DC (direct current) voltage level. They are widely used in electrical and electronic devices. Typically the actual electricity source is mains current or a battery and these voltage regulators convert and condition the battery output or mains current to a particular voltage level. 
     All electronic circuits, analog or digital, require such a well-regulated and stabilized DC power supply. An ideal DC power supply provides a constant output voltage irrespective of the value of the load current and the nature of the load while the output is free of noise, ripple and transient dips or surges. In modern electronic systems, DC power requirements vary widely. In small portable electronic devices, DC power supplies carry multiple “rail” voltages and values may vary from ±15 V to sub 1 V levels. Common values of voltage rails (supply) are 48V, 24V, 12V, 9V, 6V, 5 V, 3.3 V, and 1.8 to 3 V. Typical current output capability varies from tens of milliamperes to several amperes. 
     For larger non-portable devices with processor subsystems, a DC power supply typically has an output voltage from +5 volts to less than 3.3 volts with current requirements of several to 150 amperes. Efficiency of a power supply, particularly in high current systems, is of primary concern to avoid power wastage. A requirement for a portable device of course is also to achieve compactness of the power supply along with efficiency so as to minimize battery drain. Typical DC power supplies are linear, switch mode, and switched capacitor type, although these all have various deficiencies. 
       FIG. 1  shows a prior art “low drop out” (LDO) linear voltage regulator of  FIG. 1  of LoCascio U.S. Pat. No. 4,779,037, incorporated herein by reference in its entirety. This is a low drop out voltage regulator with a switched redundant input. “Low drop out” refers to having a low dropout voltage. Such low dropout voltage regulators are of the type generally referred to as linear voltage regulators. The  FIG. 1  device includes error amplifier  1  to compare an input reference voltage applied at terminal  4  to a signal proportional to the output voltage. Error amplifier  1  controls transistor  2  through which output current flows by adjusting transistor  2  so the output voltage at terminal V out  equals a fixed multiple of the reference voltage. The source or input voltage, which is typically unregulated, is supplied here from a battery connected at terminal VBAT via a diode D 10  to the emitter of transistor  2 . 
     In  FIG. 1 , a redundant source voltage V in  is also supplied, although this is not always the case with such devices. In this case, the redundant voltage is supplied from capacitor C 1 . Capacitor C 2  is provided for filtering at the output terminal V out . Also in this case coupled at the collector of transistor  2  are two series connected resistors R 1  and R 2 . Such a voltage regulator is characterized by its “drop out” voltage, which is the lowest source voltage which allows the regulator output voltage to remain substantially constant at some proportion of the reference voltage. 
     Voltage regulators have several performance parameters. One is noise created by circuit elements in the regulator circuit. High noise levels are undesirable since they may be RF (radio frequency) signals which interfere with operation of other portions of an electronic device of which the voltage regulator is a part. Most switch mode regulators generate noise at a frequency of 100 kHz to 3 MHz, which is undesirable. Another parameter is the output current capability since it is important for certain applications that the voltage regulator output relatively high levels of current. Typically however, high levels of current require switching regulators rather than low noise linear regulators of the type shown in  FIG. 1 . It is a drawback that typically linear regulators are not capable of high amperage (current) output due to excessive heating effects in the series or the shunt transistor elements in the regulator. 
     Efficiency is also important and refers to the proportion of input power dissipated in the voltage regulator. The approximate efficiency of a typical linear voltage regulator (of the type shown in  FIG. 1 ) is proportional to V out /V D , where in  FIG. 1  V D  is the supply voltage of the battery VBAT. Often a minimum amount of voltage drop is needed between the supply voltage and output voltage to achieve regulation, hence there is a limit to the highest efficiency possible in a given design. However, use of a series resistor or allowing a larger voltage drop across the transistor to drop the voltage is inefficient since these are inherently power dissipation devices and inefficient. The present inventors have identified that it would be useful to be able to drop part of the difference between the supplied voltage and the regulated output in a non-resistive fashion to improve efficiency. Clearly the lower this effective input voltage to the voltage regulator, the higher its efficiency. 
     SUMMARY 
     In accordance with the invention, a linear voltage regulator circuit has its power input terminal series connected to one or more super capacitors. The super capacitors are coupled thereto by an array of switches. The super capacitor array functions as an input voltage dropper in lieu of a resistor or transistor with a large voltage drop as described above. A capacitor in series takes up part of the voltage drop which directly contributes to heat dissipation and it allows the circuit to reuse the energy stored in the capacitor. Once a capacitor is fully charged, it blocks DC current, so series capacitors have not been a practical means of reducing power dissipation of a linear regulator. However, very large capacity capacitors (so-called “super capacitors”) are now commercially available which take a longer time to charge and hence allow for a low switching frequency of the capacitors. This has the advantage of charging the super capacitors for a relatively longer time without blocking the DC current path and indirectly reducing high frequency noise generation, due to the low frequency switching of capacitors. 
     Since even a super capacitor alone and in series when subject to DC voltage charges up eventually and stops conducting, the capacitor alone is not suitable. However by using a switched capacitor array, the capacitors are cyclically charged and discharged to provide a suitable voltage drop with minimal loss. This provides a voltage regulator of the linear type that has high efficiency, low noise generation and outputs high current if needed. In embodiments of the present voltage regulator, the capacitor changeover frequency, which relates to the switching frequency, is only in the range of typically fractional Hz to 300 Hz, about 1/1000 of that of switched mode regulators and which advantageously is not RF. The present regulator in various embodiments delivers currents in excess of 1 ampere, up to 10 amperes or more. Typically such high current draw requirements in the past required switching voltage regulators, which are inherently noisy, rather than a low noise linear voltage regulator as used here. Furthermore efficiency of the present regulator is about 60-85% and especially high under no-load conditions. 
     Super capacitors are well-known devices also referred to as electric double-layer capacitors or ultracapacitors. The term “super capacitor” here is intended to include these. Such devices are electrochemical capacitors having an unusually high energy storage density compared to ordinary, for instance, electrolytic capacitors. They store charges thousands of times greater than a physically similar sized electrolytic capacitor. For instance, a typical D-cell sized electrolytic capacitor has a capacitance of only hundreds of microfarads, while the same size super capacitor has a capacitance range of 0.1 farads to several farads, or even up to a few hundreds of farads which is an improvement of about 10,000 times. Commercial double-layer capacitors are available having capacities as high as 5,000 farads. 
     Unlike traditional capacitors, electric double-layer or super capacitors do not have a conventional dielectric, but instead include a structure that contains an electrical double layer. Hence, the effective thickness of the dielectric is exceedingly thin, which combined with a very large surface area, is responsible for the high capacitances. Each of the two layers by itself is quite conductive, but at the interface where the layers are effectively in contact, no significant current can flow between the layers. However the double layer can typically only withstand a relatively low voltage, so such super capacitors typically have relatively low voltage ratings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows schematically a prior art linear voltage regulator of the low drop out type. 
         FIGS. 2A and 2B  show variations of the  FIG. 1  device, also in the prior art. 
         FIG. 3  shows in a combined schematic and block diagram a linear voltage regulator in accordance with the present invention. 
         FIGS. 4A-4D  show operation of the  FIG. 3  circuit. 
         FIGS. 5A and 5B  show graphically operation of the  FIG. 3  circuit. 
         FIGS. 6A ,  6 B and  6 C show variations of the  FIG. 3  regulator. 
         FIG. 7  shows graphically capacitor switching in accordance with  FIG. 6B . 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 2A and 2B  show schematically in the prior art variations of the  FIG. 1  LDO linear voltage regulator. The  FIG. 2A  type is referred to as a series type and is typically found in commercial-type integrated circuit voltage regulators, while  FIG. 2B  shows a shunt or parallel type voltage regulator. The  FIG. 2A  circuit includes input capacitor  10  coupled to a pass element  12 . The reference voltage terminal  14  and the feedback network  20  are coupled to the error amplifier  18 . On the output side, there is a second (output) capacitor  22  and dynamic load  24  (not shown in  FIG. 1 ). The  FIG. 2B  device includes an error amplifier based on transistors Q 1  and Q 2  and the current source  28 . Resistors RC 1  and RC 2  are part of this error amplifier. A charge pump  30  is connected to a third transistor Q 4  which may be inside an opto-isolator in this shunt regulator configuration. Power transistors Q 3  and Q 5  are connected between the unregulated input, regulated output terminal and ground, with the resistors R X  and R Y  as shown functioning as the feedback network to have closed loop regulation. 
       FIG. 3  shows schematically in accordance with the invention a low dropout type linear voltage regulator. The main portion of this is the conventional shunt or series LDO linear voltage regulator  50 , which corresponds for instance to the prior art devices of  FIGS. 1 ,  2 A or  2 B. In this case capacitance C Array    52  is a super capacitor array with associated switches  56  arranged according to the level of the unregulated input voltage applied at terminal Vin as explained below. Capacitor C BUFF    54  may be a super capacitor or any other suitable capacitor which is used to power the LDO for capacitor charging and discharging change-over points. Operation of switches  56  is controlled by conventional capacitor switching controller  58  which is, e.g., logic circuitry, mixed signal circuitry or a suitable microcontroller. The regulated output voltage is at terminal V reg , corresponding to V out  in  FIG. 1 . The load is shown generally at  60 . The capacitors in the array C Array  are switchably connected by switches  56  to the V D  input terminal of regulator  50  so as to take up the larger part of the voltage drop between terminals V in  and V D  so that efficiency is improved. 
     While charging such a series connected super capacitor array, it takes up most of the dropout voltage energy, related to (V in -V D )*I load , which is stored in the capacitors of the array C Array  and the voltage drop is taken over by the capacitors in the array C Array . This is in contrast to a conventional linear regulator where this drop is across a resistive element, such as a transistor or resistor and is responsible for the bulk of the efficiency loss. Thereby efficiency of the present regulator is high and comparable to that of a switching regulator. Using an array of super capacitors C Array  and switches  56  to charge up to approximately the voltage level of V in -V D , the  FIG. 3  circuit can operate with ideally no loss, except for whatever internal resistance is present in the super capacitor array C Array  and/or the switches  56 , and, any transient related energy losses. 
     During periods of charging and discharging, the voltage variation across the capacitor array, C Array , is 
                 Δ   ⁢           ⁢     V   C       =         I   L     ⁢   Δ   ⁢           ⁢   t     C       ,         
where I L  is the load current and Δt is the charge or discharge time. If the value C is high, which is of course the case with the super capacitors in C Array , then ΔV C  is small during the time of charging and discharging while passing a current through the capacitors to keep the regulator and load working. That is, there are no dropouts. The goal is to keep the effective ΔV C  within the value of V Dmax -V Dmin , where these refer respectively to the maximum and minimum voltages at terminal V D  during the charging or discharging modes.
 
     In this case the super capacitors in the array C Array  are switched by switches  56  at relatively low frequencies to minimize noise. The goal is to switch array C Array  to obtain the best effective ΔV C  over a full switching cycle, as explained below. 
       FIGS. 4A-4D  illustrates an exemplary capacitor switching cycle for the  FIG. 3  apparatus.  FIG. 4A  shows key elements of the  FIG. 3  circuit with like elements similarly labeled, except that here instead of showing C Array    52  and the switches  56  generally, a more detailed network is shown with two super capacitors C 1  and C 2  and associated switches  60 ,  62 ,  64 ,  66 ,  68 ,  70  and  72 . In one embodiment these switches are each a transistor or a solid state relay with sufficient capacity to carry the expected currents at the required voltages. Such transistors are generally referred to as “power transistors” and may be integrated or discrete devices. Possible switch devices are bipolar power transistors, power mosfets, insulated gate bipolar transistors, thyristors, or solid state relays. Any type of semiconductor switch with adequate capacity or even a mechanical relay is usable. In  FIG. 4D , load  60  is not shown, merely for simplicity.  FIG. 4A  shows the circuit itself, but not in any operating mode, and is only for purposes of circuit illustration. 
       FIGS. 4B-4D  show the three consecutive operating phases, labeled Phase 1, Phase 2 and Phase 3, through which the circuit cycles on a continuous basis. It is to be understood that each switch in  FIG. 4  is conventionally controlled by the capacitor switching controller  58  of  FIG. 3 , also omitted here for simplicity. Such control of switches is routine in the power supply field and so no further detail is provided. 
     In Phase 1 in  FIG. 4B , assume the input voltage V in  is 5.5 V, the capacitor array has no internal resistance and the resistance across each switch in its ON state is zero. In Phase 1, capacitor C 1 , which is connected by switch  60  to terminal V in , charges from 1.75 V to 2 V. Capacitor C 2  remains at its previous state (since it is disconnected by switches  68  and  70 ) at 1.75 V. The voltage at terminal V D , which is connected by switch  62  to capacitor C 1 , increases to 5.5−1.75 volts=3.75 V, then decreases linearly to 5.5−2 V=3.5 V. 
     In  FIG. 4C  which is Phase 2, capacitor C 1  is disconnected at all three of its terminals and capacitor C 2  as shown is series connected between terminals V in  and V D . At this point capacitor C 1  remains at 2 V since it is disconnected, while capacitor C 2  charges from 1.75 V to 2 V. Then V D  increases to 5.5−1.75 V=3.75 V, then decreases linearly to 5.5−2 V=3.5 V. Typically the voltage is cycling only between 3.75 and 3.5 volts in these two phases. In the last Phase 3 shown in  FIG. 4D , both capacitors C 1  and C 2  are disconnected from input terminal V in , but are connected to discharge via switch  72  to terminal V D . Capacitor C 1  discharges from 2 to 1.75 V and similarly capacitor C 2  discharges from 2 to 1.75 V. Hence the voltage at V D  increases to 4 V and then decreases linearly to 3.5 V. The total voltage swing here is only 3.5-4 V, which is a relatively modest, thereby providing relatively linear voltage. As pointed out above, the typical switching frequency is a fraction of a Hz to 300 Hz, so each phase is approximately a few seconds to 3 milliseconds in duration. 
       FIGS. 5A and 5B  show this operation graphically. In  FIG. 5A , the horizontal scale is time (in seconds) and the vertical scale is voltage (in volts). There are two plots, for capacitors C 1  and C 2 . 
       FIG. 5B  shows operation of the regulator at terminals V D  and V in  where again the horizontal scale is seconds and the vertical scale volts. The supply voltage at terminal V in  is constant, while the voltage at terminal V D  fluctuates within the relatively narrow range of 3.5-4 V. 
       FIGS. 6A ,  6 B and  6 C show schematically variations of the capacitor array and switches portion of the  FIG. 3  circuit, all being embodiments in accordance with this disclosure. For the  FIG. 6A  embodiment, the capacitor array C 1 , C 2 , . . . , C n  and switches are arranged for an input voltage V in  which is expected to be less than twice the capacitor array output voltage at terminal V D . The switches here are designated S 1   p1 , . . . , S 1   pn  (first row); S s1 , . . . , S sn  (second row) and S 2   p1 , . . . , S 2   pn  (third row), and switch S SG . The number of capacitors used here, illustrated as being “n” in number, is a design choice dependent on the value of V D /(V in −V D ) as explained in more detail below. Hence all the capacitors here are connected in parallel relative to the input terminal V in  when charging. All the parallel connected capacitors charge at once, not one by one as in the  FIG. 4  embodiment. However for discharge purposes, the switches are set so all the capacitors are coupled in series to terminal V D . 
       FIG. 6B  shows a simpler embodiment with only a single capacitor C 1  in the switched capacitor array which is used when the supply voltage at V in  is approximately twice the value of the voltage at V D . The four switches here are designated S 1   p1 , S 2   p1 , S s1  and S SG . 
       FIG. 6C  shows in another embodiment an arrangement of capacitors and switches for the case where the supply voltage at V in  is greater than twice that at V D . Here capacitors C 1 , C 2 , . . . , C n  are in series when connected to terminal V in . The switches here are arranged somewhat similar, but not the same, as in  FIG. 6A , again being arranged in three rows (banks). All the capacitors are connected in parallel to discharge to terminal V D . The number of capacitors n here again depends on the ratio of the voltage at terminal V in  to V D . 
     In the  FIG. 6C  embodiment for high voltage drop{(V in −V D )&gt;V D } recovery, all the capacitors in the array are connected in series and then that series connected capacitor array is connected between the power source and the input terminal, and then the capacitors are connected in parallel and discharged to the input terminal. For low voltage drop{(V in −V D )&lt;V D } recovery, all the capacitors in the array are connected in parallel and then that parallel connected capacitor array is connected between the power source and the input terminal, and then the capacitors are connected in series and discharged to the input terminal. 
     Table 1 indicates relationships for calculating the capacitor values, numbers, and other important technical parameters for design purposes: 
     
       
         
               
               
               
             
           
               
                 TABLE 1 
               
               
                   
               
               
                 Parameter 
                 V in  &lt;  2 V Dmin   
                 V in  &gt; 2V Dmin   
               
               
                   
               
             
             
               
                 n 
                 
                   
                     
                       
                         n 
                         ≥ 
                         
                           
                             
                               V 
                               
                                 D 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 min 
                               
                             
                             + 
                             
                               Δ 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 V 
                                 D 
                               
                             
                             + 
                             
                               I 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     3 
                                     ⁢ 
                                     
                                       R 
                                       ON 
                                     
                                   
                                   + 
                                   
                                     r 
                                     S 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             
                               V 
                               in 
                             
                             - 
                             
                               V 
                               
                                 D 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 min 
                               
                             
                             - 
                             
                               I 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     R 
                                     ON 
                                   
                                   + 
                                   
                                     r 
                                     S 
                                   
                                 
                                 ) 
                               
                             
                           
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         n 
                         ≤ 
                         
                           
                             
                               V 
                               in 
                             
                             - 
                             
                               V 
                               
                                 D 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 min 
                               
                             
                             - 
                             
                               I 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     3 
                                     ⁢ 
                                     
                                       R 
                                       ON 
                                     
                                   
                                   + 
                                   
                                     r 
                                     S 
                                   
                                 
                                 ) 
                               
                             
                           
                           
                             
                               V 
                               
                                 D 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 min 
                               
                             
                             ⁢ 
                             
                                
                               
                                 
                                   Δ 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     V 
                                     D 
                                   
                                 
                                 | 
                                 
                                   
                                     I 
                                     ( 
                                     
                                       R 
                                       ON 
                                     
                                      
                                   
                                   ⁢ 
                                   
                                     r 
                                     S 
                                   
                                 
                               
                               ) 
                             
                           
                         
                       
                     
                   
                 
               
               
                   
               
               
                 V Cmax   
                 
                   
                     
                       
                         
                           V 
                           in 
                         
                         - 
                         
                           V 
                           
                             D 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             min 
                           
                         
                         - 
                         
                           
                             I 
                             n 
                           
                           ⁢ 
                           
                             ( 
                             
                               2 
                               ⁢ 
                               
                                 R 
                                 ON 
                               
                             
                             ) 
                           
                         
                       
                     
                   
                 
                 
                   
                     
                       
                         
                           I 
                           n 
                         
                         ⁢ 
                         
                           { 
                           
                             
                               V 
                               in 
                             
                             - 
                             
                               V 
                               
                                 D 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 min 
                               
                             
                             - 
                             
                               
                                 I 
                                 ⁡ 
                                 
                                   ( 
                                   
                                     n 
                                     + 
                                     1 
                                   
                                   ) 
                                 
                               
                               ⁢ 
                               
                                 R 
                                 ON 
                               
                             
                           
                           } 
                         
                       
                     
                   
                 
               
               
                   
               
               
                 V Dmax, Dis   
                 n(V in  − V Dmin ) − I((n + 3)R ON  + (n + 1)r S ) 
                 
                   
                     
                       
                         
                           1 
                           n 
                         
                         ⁡ 
                         
                           [ 
                           
                             
                               ( 
                               
                                 
                                   V 
                                   in 
                                 
                                 - 
                                 
                                   V 
                                   
                                     D 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     min 
                                   
                                 
                               
                               ) 
                             
                             - 
                             
                               I 
                               ⁢ 
                               
                                 { 
                                 
                                   
                                     
                                       ( 
                                       
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                                         + 
                                         3 
                                       
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                                   + 
                                   
                                     
                                       ( 
                                       
                                         n 
                                         + 
                                         1 
                                       
                                       ) 
                                     
                                     ⁢ 
                                     
                                       r 
                                       S 
                                     
                                   
                                 
                                 } 
                               
                             
                           
                           ] 
                         
                       
                     
                   
                 
               
               
                   
               
               
                 V Dmax, Cha   
                 
                   
                     
                       
                         
                           1 
                           n 
                         
                         ⁡ 
                         
                           [ 
                           
                             
                               nV 
                               in 
                             
                             - 
                             
                               V 
                               
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                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 min 
                               
                             
                             - 
                             
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                                       ( 
                                       
                                         n 
                                         + 
                                         1 
                                       
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                                       r 
                                       S 
                                     
                                   
                                 
                                 } 
                               
                             
                           
                           ] 
                         
                       
                     
                   
                 
                 [V in  − nV Dmin  − I{(n + 3)R ON  + (n + 1)r S }] 
               
               
                   
               
               
                 Δt Dis   
                 
                   
                     
                       
                         
                           C 
                           n 
                         
                         ⁡ 
                         
                           [ 
                           
                             
                               
                                 
                                   nV 
                                   in 
                                 
                                 - 
                                 
                                   
                                     ( 
                                     
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                                       1 
                                     
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                         C 
                         ⁡ 
                         
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                                   V 
                                   in 
                                 
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                 Δt Cha   
                 
                   
                     
                       
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                         ⁡ 
                         
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                                   in 
                                 
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                 η r   
                 
                   
                     
                       
                         1 
                         + 
                         
                           1 
                           n 
                         
                       
                     
                   
                 
                 1 + n 
               
               
                   
               
               
                 In Table 1: 
               
               
                 V in  Input voltage to the circuit 
               
               
                 ΔV D  Expected minimum voltage fluctuation of V D   
               
               
                 R ON  On resistance of the switch 
               
               
                 r S  Internal resistance of the capacitors 
               
               
                 n Number of capacitors. 
               
               
                 V Cmax  Maximum voltage across each capacitor 
               
               
                 V Dmax, Dis  Maximum voltage at V D  when discharging 
               
               
                 V Dmax, Cha  Maximum voltage at V D  when charging 
               
               
                 Δt Dis  Time taken to discharge the capacitors to minimum V D  (V Dmin ) from V Dmax, Cha   
               
               
                 Δt Cha  Time taken to charge the capacitors from its discharged voltage until V D  reached to V Dmin.  When the discharged capacitors start charging V D  goes to V Dmax, Cha  and gradually decrease till V Dmin   
               
               
                 η r  Supercapacitor based efficiency improvement factor, which is the overall efficiency increasing factor of the present technique. 
               
               
                 
                   
                     
                       
                         
                           η 
                           r 
                         
                         = 
                         
                           
                             Input 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             power 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             when 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             directly 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             connect 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             the 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             regulator 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             to 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               V 
                               in 
                             
                           
                           
                             
                               Input 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               power 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               when 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               connect 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               the 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               regulator 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               to 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 V 
                                 in 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               through 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               this 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               technique 
                             
                             ⁢ 
                             
                                 
                             
                           
                         
                       
                     
                   
                 
               
             
          
         
       
     
     Table 1 thereby shows (for the two indicated voltage regimes) equations to select the number of capacitors (n) in the capacitor array, the voltage rating of each capacitor (V h Cmax) the parameters for finding the switching frequency (Δt Dis , Δt Cha ), the voltage variation limits of the regulator input (V Dmax.Dis , V Dmax.Cha ) and the relative efficiency increase (η r ) due to the present method. The two columns of Table 1 V in &lt;2V Dmin  and V in &gt;2V Dmin  show the relationship for the switching schemes of  FIGS. 6A and 6C  respectively. 
     These equations are derived based on these assumptions: the power consumed by the controller circuit is negligible compared with the output power; all the capacitors are identical and have equivalent series resistance of r s ; all the switches are identical and have ON resistance R ON . 
       FIG. 7  shows (similarly to  FIG. 5B ) graphically a waveform of the voltage V D  (for the embodiment of  FIG. 6B ) when a capacitor in the present apparatus is charging and discharging. When the output draws current through the capacitor, the voltage across the capacitor increases from its initial voltage until V D  reaches V Dmin . So voltage V D  starts decreasing from V Dmax Cha  to V Dmin . When voltage V D  reaches voltage V Dmin  the capacitor starts powering the regulator. At this instance the voltage V D  goes to value V Dmax dis  and with the discharging of the capacitor, V D  gradually decreases up to voltage V Dmin . 
     It has been determined that with the exemplary  FIG. 6B  apparatus overall efficiency is about 80%. In the prior art, efficiency is approximately 5/12, less than 42%. 
     A parallel combination (or a diode connection) of the present voltage regulator can be used for very high current operations, or redundancy of a power supply. Thereby, for very high current applications, multiple instances of the present apparatus are coupled in parallel. This arrangement may include single or multiple banks of super capacitors and controllers, for high current or high voltage output requirements. 
     This disclosure is illustrative and not limiting; further modifications and improvements will be apparent to those skilled in the art in light of this disclosure and are intended to fall within the scope of the appended claims.