Abstract:
A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

Description:
FIELD OF THE INVENTION 
   This invention relates to capacitors on semiconductor chips. More particularly, the invention relates to silicon semiconductor chip capacitor structures comprising multiple parallel divergent capacitors. 
   BACKGROUND OF THE INVENTION 
   To enhance the understanding of the discussion that follows, the abbreviations and terms listed below will have the definitions as shown, the meaning and significance of which will be readily apparent to one skilled in the art of circuit board capacitor structures: 
   ADC—Analog to digital converter; 
   BEOL—Back end of line; 
   CA—Tungsten contact between metal and polysilicon; 
   Csub—Adjustable capacitor; 
   DAC—Digital to analog converter; 
   FEOL—Front end of line; 
   MIMCAP—Metal-insulator-metal capacitor; 
   MOS—Metal oxide silicon; 
   RF—Radio frequency; 
   VNCAP—Vertical native capacitor. 
   On-chip capacitors are critical components of integrated circuits that are fabricated on silicon semiconductors. These capacitors are used for a variety of purposes including bypass and capacitive matching as well as coupling and decoupling. For example,  FIG. 1  illustrates three different silicon semiconductor chip functional capacitor structures: (a) a by-pass capacitor structure BPC; (b) an AC-coupling capacitor structure ACCC; and (c) a reactive capacitor structure RC for high frequency matching. More particularly, in the by-pass capacitor structure BPC in  FIG. 1(   a ), a capacitor  100  is configured to bypass AC noise signals  103  from a power supply  101 . As is well known, a power supply signal  102  from a power supply  101  may include AC noise signals  103 , including noise signals  103  from other neighboring circuits (not shown). It is preferable to remove the AC noise signals  103  from the power supply signal  101  prior to supply of power to the circuit structure  105 . Accordingly, the bypass capacitor  100  is provided to flow the AC noise signals  103  into ground G and provide a clean DC power signal  104  to the circuit  105 . 
     FIG. 1(   b ) illustrates an AC-coupling capacitor structure ACCC to de-couple a DC signal  107  and couple an AC signal  109  into a circuit input port  110 . By locating a DC de-coupling/AC coupling capacitor  106  in series between two ports  108  and  110 , the capacitor  106  blocks DC signal  107  flow, thereby allowing only an AC signal  109  to pass into the circuit  110 . And  FIG. 1(   c ) illustrates a reactive capacitor structure RC, wherein a capacitor  111  provides a high frequency capacitive component for a circuit input  113 , the signal coupling at a high frequency region based on characteristic impedance matching to reduce reflected power between ports  114  and  115 . 
   The design and implementation of by-pass capacitor, AC-coupling capacitor and reactive capacitor structures on silicon semiconductor chips may be dependent upon one or more symmetrical structural, target circuit quality and low parasitic resistance performance characteristics. In particular, a bypass capacitor structure is typically required to provide a highest capacitance possible relative to the physical structure of the circuit and device. However, the reactance resistance of the bypass capacitor is generally required to be as low as possible for a target AC noise signal frequency. More particularly, reactance resistance R_cap(f) may be computed through the following Equation 1:
 
 R _cap( f )=1/(2*pi  *f*C );   Equation 1
 
wherein pi is a constant, the ratio of a circle&#39;s circumference to its diameter (i.e. about 3.14); f is the frequency of the AC flowing through the circuit; and C is a capacitance value of the capacitor element in the circuit, for example capacitor  100  in  FIG. 1(   a ).
 
   It is known to use a metal oxide silicon (MOS) capacitor, or MOSCAP, for the capacitor element  100 . However, MOSCAP capacitors require large chip area footprints in integrated circuits (IC). Accordingly, prior art design requirements typically result in requiring large semiconductor chip footprint areas or real estate for a bypass capacitor structure, resulting in high production costs and reduced semiconductor chip area availability for other circuit structures. As the production cost of an IC is generally proportional to the real estate required, it is desired to reduce IC chip costs by reducing the footprint required for a MOSCAP structure. 
   Moreover, current leakage during a semiconductor circuit&#39;s idle mode is known to result in increased power consumption. Silicon semiconductor chip capacitor structures usually require large MOSCAP capacitor structures in order to avoid current leakage problems. 
   What is needed is a method and structure for providing high density, high yield on-chip capacitor structures for integrated circuits and, more particularly, for silicon-based semiconductor chips. 
   SUMMARY OF THE INVENTION 
   Aspects of the present invention address these matters, and others. 
   A capacitance circuit assembly mounted on a semiconductor chip, and method for forming the same, are provided comprising a plurality of divergent capacitors in a parallel circuit connection between first and second ports, the plurality comprising at least one Metal Oxide Silicon Capacitor and at least one capacitor selected from the group comprising a Vertical Native Capacitor and a Metal-Insulator-Metal Capacitor. 
   In one aspect, the plurality of parallel divergent capacitors has a vertical structure orientation with respect to the semiconductor chip, a Metal Oxide Silicon capacitor located at a bottom of the vertical structure and defining a capacitance circuit assembly footprint area on the semiconductor chip. A metal-oxide-silicon capacitor is formed at a bottom of a front end-of-line of a semiconductor chip by disposing a plurality of source, gate and drain regions within overall horizontal length, the gate regions each having a common horizontal length, the common lengths defining an effective horizontal width dimension, the effective horizontal width and the overall horizontal length defining a horizontal footprint on the semiconductor chip. A vertical-native capacitor is formed with horizontal metal layers in a back end-of-line of the semiconductor chip and vertically above the metal-oxide-silicon capacitor and within the footprint, each of the layers comprising parallel positive plates alternating with parallel negative plates. A metal-insulator-metal capacitor is formed in the back end-of-line of the semiconductor chip and vertically above the metal-oxide-silicon capacitor and the vertical-native capacitor and within the footprint, with a top negative plate horizontally spaced over a parallel bottom positive plate. 
   In the methods, the vertical-native capacitor parallel positive plates, the metal-insulator-metal capacitor bottom positive plate, and the metal-oxide-silicon capacitor drains and sources are electrically connected to a first port; and the vertical-native capacitor parallel negative plates, the metal-insulator-metal capacitor top negative plate and the metal-oxide-silicon capacitor gates are electrically connected with a second port. The metal-insulator-metal capacitor, the vertical-native capacitor and the metal-oxide-silicon capacitor thus define a composite capacitance density value between the first port and the second port about twice a capacitance density value of the metal-oxide-silicon capacitor. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The various drawings are intended to assist in a complete understanding of the features of the invention, and are not presented as a limitation on the scope thereof. 
       FIG. 1  is an electrical schematic illustration of different prior art silicon semiconductor chip capacitor structures. 
       FIG. 2  is an electrical schematic illustration of a prior art by-pass capacitor structure. 
       FIG. 3  is an electrical schematic illustration of a by-pass capacitor structure according to the present invention. 
       FIG. 4  is a top plan view of a MOS capacitor according to the present invention. 
       FIG. 5  is a top plan view of a MIM capacitor according to the present invention. 
       FIG. 6  is a perspective view of a VNCAP capacitor according to the present invention. 
       FIG. 7  is a perspective view of a capacitor structure according to the present invention. 
       FIG. 8(   a ) is a perspective illustration of the capacitor structure of  FIG. 7 . 
       FIG. 8(   b ) is an electrical schematic illustration of the capacitor structure of  FIG. 8(   a ). 
       FIG. 8(   c ) is perspective view of a VNCAP element according to the present invention. 
       FIG. 8(   d ) is an electrical schematic illustration of the VNCAP of  FIG. 8(   c ). 
       FIG. 9  is an electrical schematic illustration of a capacitor structure according to the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2  illustrates a prior art by-pass capacitor structure  200 , wherein a MOSCAP  210  is configured to bypass AC noise signals  203  from a noisy power signal  202  from a power supply  201  prior to supply of power to a circuit structure  205 . The bypass MOSCAP  210  flows AC noise signals  203  into ground G, thus providing a clean DC power signal  204  to the circuit  205 . Some of the noisy power signal  202  current is also lost as leakage  206  by the MOSCAP  210 . 
     FIG. 3  illustrates a by-pass capacitor structure  300  according to the present invention with a multicapacitor circuit element  310 , the multicapacitor element  310  comprising three capacitors  312 ,  314  and  316  arranged in parallel between a noisy power signal  302  and ground G. The multicapacitor element  310  bypasses AC noise signals  303  from the noisy power signal  302  from the power supply  301  into ground G prior to supply of power to a circuit structure  305 , thus providing a clean DC power signal  304  to the circuit  305 . Some of the noisy power signal  302  current is also lost as leakage  307  by the multicapacitor element  310 . 
   In one aspect, the multicapacitor element  310  requires less semiconductor chip real estate than a prior art single capacitor element  210 , thereby proportionally reducing chip production costs. In another aspect, the multicapacitor element  310  provides for a reduction in the amount of current  307  lost to leakage relative to a prior art single capacitor element  210  current leakage  206 , thereby increasing performance yield relative to component size as compared to the prior art single capacitor element  210 . 
   In one example, the multicapacitor element  310  comprises a MOSCAP, or CMOS,  312  in parallel with a metal-insulator-metal capacitor (CMIM)  314 , and a vertical native capacitor (CVNCAP)  316 . These elements will provide design advantages as described presently, but it will be apparent that other capacitor structures may be practiced with the present invention. In one aspect, a parallel CMOS  312 /CMIM  314 /CVNCAP  316  element  310  may achieve bypass capacitor functions with a CMOS  312  chip footprint of about, or less than, one-half that of a prior art single CMOS element  210 . And, furthermore, where the parallel CMOS  312 /CMIM  314 /CVNCAP  316  element  310  is configured in a vertical structure having a total footprint no greater than that of the CMOS  312 , then the chip footprint of the entire parallel CMOS  312 /CMIM  314 /CVNCAP  316  element  310  may also be about, or less than, one-half that of a prior art single CMOS element  210 . 
   In another aspect, independent of the vertical nature of the element  310 , the amount of parasitic leakage current  307  of the parallel CMOS  312 /CMIM  314 /CVNCAP  316  element  310  may be about one-half that of the amount of the prior art single CMOS element  210  leakage current  306 . Thus, although chip real estate concerns may indicate a preference for a vertical structure  310 , other embodiments (not shown) may have a horizontal on-chip structure. 
   Referring now to  FIG. 4 , a top plan view of a CMOS  400  on a chip is illustrated. A bottom substrate (not shown) is covered with a silicon layer RX  402  upon which a plurality of source  404 , gate  408  and drain regions  406  are disposed. The silicon layer RX  402  has an overall length dimension LR  410 . Each of the polysilicon gate regions  408  has a common width L 1   412  and a common length  414 , wherein the length  414  also defines an effective width W 1  of the CMOS  400 . Accordingly, the CMOS  400  has an effective footprint area defined by W 1 *LR. 
   In one aspect, the capacitance density CD MOS  of a single CMOS capacitor may be defined according to Equation 2:
 
 CD   MOS   =C   MOS /( W 1* L 1* n );  Equation 2
 
wherein n is the number of gate regions  408 .
 
   In one example for 65 nanometer node circuitry, the capacitance density C MOS  of prior art single MOS capacitor structure may be determined by Equation 2 as equal to 10 fF/um 2 . However, the actual effective capacitance density CD MOS     —     REAL  may be defined as a function of the effective C MOS    400  footprint area defined by W 1 *LR by Equation 3:
 
 CD   MOS     —     REAL   =C   MOS /( W 1* LR )  Equation 3
 
   Accordingly, for 65 nanometer node circuitry where the capacitance density CD MOS  of C MOS    400  is 10 fF/um 2 , the actual effective capacitance density CD MOS     —     REAL  determined by Equation 3 is 4 fF/um 2 . 
   Referring now to  FIG. 5 , a plan view of a MIM capacitor structure  500  on a chip is illustrated. For a top plate  502  width W 2   510  and length L 2   512 , wherein the top plate  502  has a smaller footprint area than the bottom plate  504 , the capacitance density CD MIM  may be defined as a function of the top plate  502  footprint according to Equation 4:
 
 CD   MIM   =C   MIM /( W 2* L 2)  Equation 4
 
   Accordingly, in one example for 65 nanometer node circuitry, the capacitance density CD MIM  of the MIM capacitor structure  500  may be determined by Equation 4 as 2 fF/um 2 . 
   Referring now to  FIG. 6 , a perspective view of a VNCAP capacitor structure  600  is illustrated. For overall capacitor width W 3   602  and overall capacitor length L 3   604 , the capacitance density CD VNCAP  may be defined according to Equation 5:
 
 CD   VNCAP   =C   VNCAP /( W 3* L 3)  Equation 5
 
   Accordingly, in one example for 65 nanometer node circuitry, the capacitance density CD VNCAP  of the VNCAP capacitor structure  600  may be determined by Equation 5 as 2 fF/um 2 . 
   Referring now to  FIG. 7 , a multilayer perspective illustration is provided of an embodiment of a parallel CMOS  312 /CMIM  314 /CVNCAP  316  element  310  discussed above. Although the present example is described with respect to specified numbers of metal layers within designated capacitor groupings, as well as overall metal layer totals, it is to be understood that the inventions described herein are not restricted to the specific embodiments: it will be readily apparent that more or less metal layers may be practiced within the teachings herein, and one skilled in the art may readily form alternative embodiments with different metal layer numbers and combinations. A CMOS  312  functions as a FEOL capacitor and comprises a first solid substrate  702  layer; a second silicon layer  703 , the silicon layer comprising source  704 , drain  706  and gate regions  708 ; and a third conductive polysilicon contact layer  705  comprising discrete contact regions disposed on each of the source  704 , drain  706  and gate regions  708 . A fourth layer of CA  712  provides a contact interface between the polysilicon contacts  705  and BEOL CMIM  314  and CVNCAP  316  capacitor structures. 
   The CVNCAP  316  is defined by three groups of progressively larger metal layers. A first bottom group  716  of four metal layers  718  (M 1  through M 4 , respectively the 1st, 2 nd , 3 rd  and 4 th  metal layers from the bottom of the multicapacitor element  310 ) are each separated by an insulator (or dielectric) material layer  720 , the first metal layer M 1  in circuit connection with the CA layer  712 . A second middle group of larger metal layers  726  (M 5  and M 6 , respectively the 5 th  and 6 th  metal layers) are mounted on the first group of layers  716  and separated by a dielectric material layer  728  from each other. Lastly, a third largest top group  740  of metal layers  742  (M 7  and M 8 , respectively the 7 th  and 8 th  metal layers) are mounted atop the second metal layer group  724  and separated by a dielectric material layer  734  from each other. 
   In another aspect each of the three CVNCAP metal levels  718 ,  726  and  742  further comprise parallel “−” signed and “+” signed metal plates. More particularly, the CVNCAP first level metal layers M 1  through M 4   718  further each comprise a plurality of “+” signed metal plates  820  in an alternative horizontal parallel relationship with a plurality of “−” signed metal plates  822 . CVNCAP second middle level metal layers M 5  and M 6  further each comprise a plurality of “+” signed metal plates  830  in an alternative horizontal parallel relationship with a plurality of “−” signed metal plates  832 . And CVNCAP third top level metal layers M 7  and M 8   742  further each comprise a plurality of “+” signed metal plates  840  in an alternative horizontal parallel relationship with a plurality of “−” signed metal plates  842 . 
   The MIMCAP  314  is also a part of the BEOL and has a top plate  752  and a bottom plate  754  and a dielectric  756  therebetween, with the MIMCAP  314  interfaced to the CVNCAP top metal layers  732 , as will be described presently. 
     FIG. 8(   a ) shows a representation of the multicapacitor chip element  310  as described in  FIG. 7  including the electrical connection  804  of circuit ports Port  1   801  and Port  2   802  (for clarity the CVNCAP middle metal layers  726  and dielectric layer  728  are omitted). A simplified electrical schematic of the element  310  of  FIG. 8(   a ) is shown in  FIG. 8(   b ).  FIG. 8(   c ) is another perspective view of the CVNCAP  316  of element  310  and further illustrating the parallel metal plate and composite capacitance structure, and  FIG. 8(   d ) is a schematic electrical illustration of the composite capacitor characteristic of the CVNCAP  316 . 
   In accordance with established practices, capacitor(s) in the BEOL of the chip assembly are connected with the design capacitance and the negative parasitic capacitances connected in series with one another and in parallel with the positive parasitic capacitance. Accordingly, Port  1   801  is connected electrically to the MOSCAP  312  gates  708 , the “−” signed CVNCAP first metal level plates  822 , the “−” signed VNCAP second metal level plates  832 , the “−” signed third top metal level plates  842  and to the CMIM top plate  752 . Port  2   802  is connected electrically to the “+” signed CVNCAP first metal level plates  820 , the “+” signed CVNCAP second metal level plates  830 , the “+” signed third top metal level plates  840  and to the CMIM bottom plate  754 , sources  704  and drains  706 . 
   As illustrated in  FIGS. 8(   c ) and  8 ( d ), in one aspect the three divergently sized CVNCAP  316  bottom  716 , middle  724  and top  740  metal layers each define a capacitor region. More particularly, the CVNCAP  316  bottom metal levels M 1  through M 4  together define a capacitor region  860 ; the CVNCAP  316  middle levels M 5  and M 6  together define a capacitor region  862 ; and the CVNCAP  316  top metal levels M 7  and M 8  together define a capacitor region  864 . The CVNCAP element  316  capacitance value, and parasitic capacitance nature, is thus that of parallel capacitor elements  860 ,  862  and  864 . 
   In one aspect, two passive capacitors (CMIM  314  and CVNCAP  316 ) and an active capacitor (CMOS  312 ) in a parallel circuit arrangement thus function as one on-chip capacitor between Port  1   801  and Port  2   802 , and thus in a circuit incorporating CMOS  312 /CMIM  314 /CVNCAP  316  element  310 . 
   In another aspect, the CMOS  312 /CMIM  314 /CVNCAP  316  element  310  comprises a vertical connection between a BEOL capacitor (CMIM  314 /CVNCAP  316 ) and an FEOL capacitor (CMOS  312 ), providing space saving advantages over other prior art structures, increasing capacitance density on an IC by a factor of 2 over a single CMOS on-chip capacitor, and thus providing improved manufacturing cost efficiencies. 
   In another aspect, by using a CVNCAP  316  to connect between a MIM capacitor  314  and a MOS capacitor  312 , performance is increased over other prior art structures. In one aspect, a new parasitic boost structure is accomplished through asymmetrical capacitor geometry according to the present invention. 
   As is well known in the design of on-chip capacitor structures, each on-chip capacitor inherently comprises two components: a main capacitor structure and at least one parasitic capacitor structure formed through proximity to at least one other capacitor or other electrically similar element. More particularly,  FIG. 9  provides an electrical schematic diagram illustrating the parasitic capacitance properties of CMOS  312 /CMIM  314 /CVNCAP  316  element  310 . Parasitic capacitors Cp 1  through Cp 6  ( 606  to  610 ) are effectively generated in each of Port  1   801  and Port  2   802  and, thus, there are two parasitic capacitors Cp for each main capacitor, wherein: 
   Cp 1    606  and Cp 4    607  are the parasitic capacitors for the CMOS capacitor  312 ; 
   Cp 2    608  and Cp 5    609  are the parasitic capacitors for CVNCAP capacitor  316 . 
   Cp 3    610  and Cp 6    611  are the parasitic capacitors for MIMCAP capacitor  314 . 
   However, due to the asymmetrical, parallel and vertical structure of CMOS  312 /CMIM  314 /CVNCAP  316  element  310  as described above and illustrated in the figures filed herewith, inherent parasitic capacitance is reduced. More particularly, total element  310  capacitance C TOTAL  and total element  310  parasitic capacitance C PAR  may be derived as follows from Equation Set 6:
 
 C   TOTAL   =C   MOS   //C   VNCAP   //V   MIM   //V   PAR  
 
 C   TOTAL   =C   MOS   +C   VNCAP   +V   MIM   +V   PAR  
 
 C   PAR   =Cp   1   +Cp   2   +Cp   3    Equation Set 6
 
   Thus, design leakage current reduction to one-half of the expected parasitic capacitance is achieved, thereby providing savings in chip power consumption, such as, for example, during the chipboard circuit&#39;s idle mode. 
   While specific embodiments of the present invention have been described herein, it is to be understood that variations may be made without departing from the scope thereof, and such variations may be apparent to those skilled in the art represented herein, as well as to those skilled in other arts. The materials identified above are by no means the only materials suitable for the manufacture of the MOS, VNCAP and MIMCAP capacitor structures, and substitute materials will be readily apparent to one skilled in the art.