Abstract:
Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    The present inventions are related to systems and methods for alleviating analog to digital converter mismatches. 
         [0002]    Analog to digital converters are a staple in mixed signal semiconductor designs as they allow for operation on signals in both the digital and analog domains. In some cases, a mixed signal semiconductor device may employ a large number of analog to digital converters allowing the implementation to accept and process a large number of inputs. When multiple analog to digital converters are utilized, such as in a read channel device, there may be some mismatch between one or more of the analog to digital converters. The mismatch is typically in the form of, among other things, different gains, different offsets, and/or different comparator threshold voltages. These mismatches pose a serious problem to adaptive digital loops that retain a preceding completion point in memory to be used as a succeeding initialization point. Thus, for example, this may be a problem where the completion point of a preceding sector is maintained as an initialization point for a succeeding sector in a read channel device as the previous sector may have relied on a different analog to digital converter than that utilized by the succeeding sector. Such a scenario may result in unacceptable servo burst demodulation problems and/or into undesirable timing and gain control effects. 
         [0003]    To address the aforementioned limitations, some designs have utilized a single analog to digital converter tasked with performing a wide array of operations. Turning to  FIG. 1 , a prior art system  100  relying on a single, complex analog to digital converter  110  covering a spectrum of operations is shown. Analog to digital converter  110  receives an analog input  105  and provides a digital representation of analog input  105  to a gain loop  120 . Gain loop  120  performs is particular function and provides a result to a shadow register  130 . Shadow register  130  stores the output of gain loop  120  whenever indicated by the completion of one of a number of events as denoted by the output of an OR gate  140 . Shrinking feature sizes in CMOS technologies pose severe limitations to system  100  where varied temperature, voltage and other factors can render the design of analog to digital comparator  110  complex and power inefficient. To avoid the limitations of system  100 , some designs have used multiple analog to digital comparators that may be relatively simple designs, but that include inherent mismatches. In addition, a dedicated microprocessor is used to implement a sophisticated calibration scheme to alleviate the effects of the inherent mismatches. Usually, the calibration procedure is done before the device resumes normal operation. It should be noted that even after extensive calibration, all mismatches will not necessarily be eliminated and may continue to adversely effect operation. 
         [0004]    Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for operating in relation to analog to digital converters. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    The present inventions are related to systems and methods for alleviating analog to digital converter mismatches. 
         [0006]    Various embodiments of the present invention provide adaptive loops that are capable of adapting to at least two distinct signal sets. Such adaptive loops include a generalized circuit including a signal input, an initialization input, and an output. Further, the adaptive loops include a first analog to digital converter, a first register, a second analog to digital converter, and a second register. An input is provided to both the first analog to digital converter and the second analog to digital converter. A signal input selector selects the first analog to digital converter to drive the signal input based on a first event, and selects the second analog to digital converter to drive the signal input based on a second event. In some cases, the signal input selector further selects the first register to drive the initialization input based on the first event, and selects the second register to drive the initialization input based on a second event. In some cases, the signal input selector is further operable to determine a first conclusion point associated with the first event and a second conclusion point associated with the second event. In such cases, the signal input selector is further operable to cause the first register to store the output whenever the first conclusion point is indicated, and wherein the signal input selector is further operable to cause the second register to store the output whenever the second conclusion point is indicated. In some cases, the adaptive loop includes a first multiplexer operable to provide an output of the first analog to digital converter or an output of the second analog to digital converter to drive the signal input; and the adaptive loop includes a second multiplexer operable to provide an output of the first register or an output of the second register to drive the initialization input. 
         [0007]    In some instances of the aforementioned embodiments, the generalized loop is a gain loop. In such cases, the adaptive loop may be implemented as part of a read channel device where the first event indicates a first sector of a storage medium and the second event indicates a second sector of the storage medium. In other cases, the first event may indicate a first region of a sector of a storage medium, and the second event may indicate a second region of the sector of the storage medium. 
         [0008]    In one or more instances of the aforementioned embodiments, the adaptive loop further includes a calibration control circuit that is operable to associate the first analog to digital converter with the first event, and to associate the second analog to digital converter with the second event. In such instances, the calibration control circuit may be implemented in one of a variety of ways including, but not limited to, a general purpose processor executing computer executable instructions, or a dedicated hardware circuit. 
         [0009]    Other embodiments of the present invention provide methods for adaptively processing a variety of input signals, the methods include providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated. In particular cases, the adaptive circuit is a gain loop. 
         [0010]    In some instances of the aforementioned embodiments, the adaptive loop circuit includes a signal input, an initialization input, and an output. An output of the first register drives the initialization input and an output of the first analog to digital converter drives the signal input when the first event is indicated. An output of the second register drives the initialization input and an output of the second analog to digital converter drives the signal input when the second event is indicated. In some instances, the method further includes receiving an indication of a conclusion of the first event; and writing the output to the first register; and receiving an indication of a conclusion of the second event, and writing the output to the second register. 
         [0011]    In various instances of the aforementioned embodiments, the methods further include performing a calibration process. In such instances, the calibration process includes associating the first analog to digital converter with the first event, and associating the second analog to digital converter with the second event. 
         [0000]    Yet other embodiments of the present invention provide storage systems. Such storage systems include a storage medium and a read channel circuit. The read channel circuit includes an adaptive control circuit having a signal input, an initialization input and an output. The adaptive control circuit includes a first circuit pair and a second circuit pair. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. The adaptive control circuit further includes a signal input selector that selects the first analog to digital converter to drive the signal input and the first register to drive the initialization input based on a first event, and selects the second analog to digital converter to drive the signal input and the second register to drive the initialization input based on a second event. The storage system includes an input signal derived from the storage medium and provided as an input to both the first analog to digital converter and the second analog to digital converter. 
         [0012]    This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0013]    A further understanding of the various embodiments of the present invention may be realized by reference to the figures which are described in remaining portions of the specification. In the figures, like reference numerals are used throughout several figures to refer to similar components. In some instances, a sub-label consisting of a lower case letter is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components or to a non-specific one of the referenced elements. 
           [0014]      FIG. 1  depicts a prior art system relying on a single, complex analog to digital converter covering a spectrum of operations; 
           [0015]      FIG. 2  depicts a system relying on multiple potentially mismatched analog to digital converters covering a spectrum of operations in accordance with some embodiments of the present invention; 
           [0016]      FIG. 3  is a flow diagram showing a method in accordance with various embodiments of the present invention for using multiple potentially mismatched analog to digital converters covering a spectrum of operations; and 
           [0017]      FIG. 4  depicts a hard disk drive system utilizing a read channel with matched analog to digital converters and initialization points in accordance with one or more embodiments of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0018]    The present inventions are related to systems and methods for alleviating analog to digital converter mismatches. 
         [0019]    Various embodiments of the present invention utilize paired analog to digital converters and initialization registers. Such an approach recognizes the possibility of mismatches, but reduces the effect of mismatches by decoupling the initialization point from one event from the completion point of an unrelated event, while at the same time assuring that useful initialization information is maintained. 
         [0020]    Turning to  FIG. 2 , a system  200  relying on multiple potentially mismatched analog to digital converters  210  covering a spectrum of operations is depicted in accordance with some embodiments of the present invention. Each of analog to digital converters  210  receive an analog input  205  and provide a corresponding digital output to a multiplexer  220 . The digital output from one of analog to digital converters  210  is selected using a select control  222  provided by an individual event selector circuit  250  to drive a generalized circuit  230 . Generalized circuit  230  may be any circuit that may be reused in relation to different events and/or operations. Generalized circuit  230  includes a signal input  232 , an initialization input  234  and an output  236 . As one example, generalized circuit  230  may be, but is not limited to, a gain control loop as are known in the art. Such a gain control loop provides output  236  based on a signal input  232  and an initialization input  234 . By implementing the circuit similar to that discussed in relation to  FIG. 2 , a generalized circuit may be used in relation to a number of operations or events thus saving power and/or semiconductor die space. 
         [0021]    Output  236  of generalized circuit  230  is provided to a number of registers  240  that may be individually selected to hold the results of generalized circuit  230  for later use to drive initialization input  234  of generalized circuit  230 . Each of registers  240  is controlled by a respective write line  242  driven by individual even selector input  250 . A multiplexer  260  receives outputs  244  from registers  240  and selects between outputs  244  based on a select control  262  from individual even selector input  250  to drive initialization input  234 . 
         [0022]    Event selector circuit  250  receives a number of event status signals  280  that indicate which of a number of events is ongoing. For example, in a read channel scenario, event status signals may be associated with data being received from respective sectors of a hard disk, or with different regions of a respective sector. Such regions may include, but are not limited to, a gray code region or a burst demodulation region as are known in the art. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of different events or operations that may be associated with respective event status signals  280  in accordance with different embodiments of the present invention. In response to event selector signals  280 , individual event selector circuit  250  asserts select control  222  and select control  262  such that a respective analog to digital converter  210  and register  240  is selected. This provides a matched signal input  232  and initialization input  234  pair. Further, once the particular event is complete, individual event selector circuit  250  asserts a selected write line  242  causing the associated register  240  to store the result available at output  236 . The stored value can be used as an initialization input the next time the corresponding analog to digital converter  210  and register  24  are selected by individual event selector circuit  250  based on event status signals  280 . 
         [0023]    In operation, predetermined signals may be applied at input  205  such that a calibration input  275  is generated. Calibration input  275  is provided to a calibration control circuit  270  which in turn selects an appropriate analog to digital converter  210  for use in relation to signals associated with different events or operations that are designated by event status signals  280 . In some cases, calibration control circuit  270  is a dedicated circuit, while in other cases, it may be implemented as software executed on a general purpose microprocessor. This calibration is performed using calibration techniques known in the art and generally at startup. The calibration results are used by calibration control  270  to establish static pairs of analog to digital converters  210  and registers  240 . This pairing may be maintained in a register set implemented as part of individual event selector circuit  250 . 
         [0024]    As previously mentioned, system  200  may be implemented as part of a read channel device in a magnetic storage medium. In such a scenario, input  205  may receive a serial stream of data derived from a magnetic storage medium. The data may be derived from different sectors on the magnetic storage medium, and from different regions within the aforementioned sectors. The different regions and/or sectors may be differentiated by the assertion of different event status inputs  280 . When a particular event status input  280  is asserted, a corresponding pair of analog to digital converter  210  and register  240  may be selected for operation. Selected register  240  provides initialization input  234  to generalized circuit  230  (e.g., a gain loop), and selected analog to digital converter  210  provides signal input  232  to generalized circuit  230 . At the end of the process implemented by generalized circuit  230 , output  236  is stored to selected register  240  for later use as initialization input  234 . This initialization input is used in subsequent processing when the event status input  280  corresponding to the selected register is again asserted. 
         [0025]    When data input  205  transitions to a different sector and/or region within a sector, individual event selector circuit  250  selects a different analog to digital converter  210  and register  240  pair. The newly selected register  240  provides initialization input  234  to generalized circuit  230 , and selected analog to digital converter  210  provides signal input  232  to generalized circuit  230 . Thus, an initialization input  234  specific to the asserted event status signal is used, and not merely the last state of output  236  of generalized circuit  230 . At the end of the process implemented by generalized circuit  230 , output  236  is stored to the newly selected register  240  for later use as initialization input  234 . Of note, it is not important that analog to digital converter  210  match as the output derived from one analog to digital converter  210  is not used as an initialization input  234  that is paired with signal input  232  derived from another analog to digital converter  210 . Rather, a particular register  240  is paired with a particular analog to digital converter  210  such that a given initialization input  234  derived from the output of a given analog to digital converter  210  is paired with a subsequent signal input  232  derived from the same analog to digital converter  210 . 
         [0026]    As an example, using only a single register  240  to capture the output of generalized circuit  230  implemented as a gain loop, an output having a positive one dB gain error may be derived from analog to digital converter  210   a . In subsequent processing, generalized processing circuit  230  will go in the negative direction to reduce the gain by one dB based on the previously recorded result even though signal input  232  is derived from a different generalized circuit  230 . If, in the next sector processed by analog to digital converter  210   b , analog to digital converter  210   b  exhibits a negative one dB error, generalized circuit  230  has to compensate for a negative two dB error where the previous output from generalized circuit  230  is used as an initialization input  234 . Since more error is to be corrected, generalized circuit  230  may take longer to settle and correct the error. This may negatively effect operation. For example, the servo burst demodulation is severely affected by the gain loop behavior due to mismatched analog to digital converters. Timing recovery is another area where the problem is noticed. When the mismatch between ADCs is large, the digital timing loop may not track the timing errors and may eventually lose lock of the timing information. Digital gain control loop may also be adversely affected. In general, any adaptive loop which has memory i.e. whose starting value depends on previous event (which uses a different analog to digital converter) will be stressed and affected. 
         [0027]    In contrast, embodiments of the present invention use output  236  generated from data derived from a particular analog to digital converter  210 . Thus, using the same example as that discussed above, an output having a positive one dB gain error may be derived from analog to digital converter  210   a . This error is stored in a register  240  associated with analog to digital converter  210   a . In subsequent processing of data derived from analog to digital converter  210   a , generalized processing circuit  230  will go in the negative direction to reduce the gain by one dB based on the previously recorded result. In the next sector processed by analog to digital converter  210   b , analog to digital converter  210   b  exhibits a negative one dB error, generalized circuit  230  will receive an initialization input  234  from a register  240  that is specifically paired with analog to digital converter  210   b . This register will presumably hold a value near the negative on dB error, and thus generalized circuit  230  will not have to compensate for a very large differential—regardless of what results were derived from processing the output of analog to digital converter  210   a.    
         [0028]    Turning to  FIG. 3 , a flow diagram  300  a calibration process is selected (block  305 ). The process of selecting calibration may be done automatically upon device startup, or at other times depending upon particular system needs. Once calibration is selected (block  305 ), the first event to be calibrated is selected (block  310 ). In the case of a read channel device, selecting the first event may include, for example, selecting a first sector of a magnetic storage medium. Based on the disclosure provided herein, one of ordinary skill in the art will recognize a variety of systems and associated events that may be calibrated in accordance with different embodiments of the present invention. A calibration input associated with the selected event is provided as the input (block  315 ). As is known in the art, a process of selecting between a number of analog to digital converter to use in relation to the calibration input is performed to find an analog to digital converter that is best suited to the particular event (block  320 ). The determined analog to digital converter is selected and the selection is stored in a register (block  325 ). Along with the selected analog to digital converter, a register is selected to receive the results from a generalized circuit when the particular event is selected. The selected register is paired with the analog to digital converter, and the pairing it stored in the register. Once the calibration for the particular event is completed, it is determined whether another event remains to be calibrated (block  330 ). Where another event remains to be calibrated (block  330 ), the next event is selected (block  310 ) and the processes of block  315 - 325  are repeated for the next event. Otherwise, where no more events remain to be calibrated (block  330 ), the calibration process ends and remains paused until another calibration is selected (block  305 ). 
         [0029]    The pairings stored in memory during the previously described calibration process are used during normal operation of the device. In particular, it is determined whether a new event is identified (block  335 ). As discussed above, an event may be anything that demands the use of a different analog to digital converter and/or output register. Thus, for example, in the cases of a read channel device, the new event may be the advent of data from a different sector of a magnetic storage medium. A new event may be identified, for example, by the assertion of an event status flag. Where a new event is identified (block  335 ), the analog to digital converter corresponding to the event is selected (block  340 ) and the register associated with the event is selected (block  345 ). This process includes querying the stored analog to digital converter and register pairs to determine the pair corresponding to the particular event, and selecting the output from the register and the output of the selected analog to digital converter as inputs to the generalized circuit (block  350 ). It is determined whether the ongoing event has completed ( 355 ). Where it has not yet completed (block  355 ), processing using the selected pairs continues. Otherwise, where the event has completed (block  355 ), the result from the generalized circuit is written to the selected register in preparation for the next time the event is selected (block  360 ). The processes of blocks  335 - 360  are repeated for different events using pairs of analog to digital converters and registers corresponding to the particular events. 
         [0030]    Thus, the starting value for a generalized circuit (e.g., digital loop) in a sector is not the value adapted from a preceding event (e.g., sector of a magnetic storage medium). Instead, embodiments of the present invention use the adapted value from a previous event that used the same analog to digital converter. Thus, in some cases, it may be that a given register is only used in relation to one particular sector, or may be used in relation to two or more sectors having similar qualities and each being associated with the same analog to digital converter. The generalized circuit is the same for each of the different events, and thus there is not a substantial need for circuit duplication. 
         [0031]    Different embodiments of the present invention provide one or more of the following advantages. First, an analog mismatch problem is solved in an efficient way in the digital domain. The approach mitigates the effect of mismatches between analog to digital converters, and yet is a relatively low cost approach. The approach adds a few registers (i.e., one for each analog to digital converter in the system) to hold the starting values of the generalized circuit (e.g., digital loops) corresponding to each ADC. It should be noted that different embodiments of the present invention may be used in relation to any adaptive loop which has memory maintaining a starting value for the adaptive loop. 
         [0032]    Turning to  FIG. 4 , a storage system  580  including a media defect and data regeneration system  587  is shown in accordance with various embodiments of the present invention. Storage system  580  may be, for example, a hard disk drive. Storage system  580  includes a read channel  587  with an incorporated matched analog to digital converter and register pair system in accordance with different embodiments of the present invention. The read channel device may include, for example, a system similar to that discussed above in relation to  FIG. 2 . In such a case, the input to the system may be derived from a preamp  591 . In addition, storage system  580  includes an interface controller  585 , a hard disk controller  589 , a motor controller  599 , a spindle motor  597 , a disk platter  595 , and a read/write head  593 . Interface controller  585  controls addressing and timing of data to/from disk platter  595 . The data on disk platter  595  consists of groups of magnetic signals that may be detected by read/write head assembly  593  when the assembly is properly positioned over disk platter  595 . In a typical read operation, read/write head assembly  593  is accurately positioned by motor controller  599  over a desired data track on disk platter  595 . Motor controller  599  both positions read/write head assembly  593  in relation to disk platter  595  and drives spindle motor  597  by moving read/write head assembly to the proper data track on disk platter  595  under the direction of hard disk controller  589 . Spindle motor  597  spins disk platter  595  at a determined spin rate (RPMs). 
         [0033]    Once read/write head assembly  593  is positioned adjacent the proper data track, magnetic signals representing data on disk platter  595  are sensed by read/write head assembly  593  as disk platter  595  is rotated by spindle motor  597 . The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter  595 . This minute analog signal is transferred from read/write head assembly  593  to read channel module  587  via preamp  591 . Preamp  591  is operable to amplify the minute analog signals accessed from disk platter  595 . In addition, preamp  591  is operable to amplify data from read channel module  587  that is destined to be written to disk platter  595 . In turn, read channel module  587  decodes (including media defect detection) and digitizes the received analog signal to recreate the information originally written to disk platter  595 . This data is provided as read data  583  to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data  581  being provided to read channel module  587 . This data is then encoded and written to disk platter  595 . 
         [0034]    In conclusion, the invention provides novel systems, devices, methods and arrangements for compensating for analog to digital converter mismatch. While detailed descriptions of one or more embodiments of the invention have been given above, various alternatives, modifications, and equivalents will be apparent to those skilled in the art without varying from the spirit of the invention. Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.