Abstract:
A method of transferring charges for a CCD image-sensing device. First, the K register elements (every k register elements) are defined as a charge-combining portion, thereby providing m charge-combining portions. The y image-sensing elements sense incident light energy to generate y charge packets proportional to the light intensity. Then, the y charge packets are transferred in a parallel manner to the CCD shift register. The charge packets coupled to each of the m charge-combining portions are accumulated into one specific register element when the k register elements have coupled the charge packets from the image-sensing elements, thereby generating m adding charge packets in the m charge-combining portions. Finally, each of the adding charge packets is serially delivered to the output of the CCD shift register, converting the adding charge packets into proportional voltage levels.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates in general to a control method of transferring charges. More specifically, it relates to a method of transferring charges for a CCD (Charge-Coupled Device) image-sensing device. 
     2. Description of the Related Art 
     CCD image-sensing devices are widely applied to image processing systems and digital signal processing systems, because they can serve as shift registers or sequential memory devices with high density. For example, CCD image-sensing devices are applied in scanners, digital cameras, copy machines, etc. 
     For conventional scanners or contact image scanners (CIS), their image processing portions comprise CCD image-sensing devices. FIG. 1 shows a schematic structure of a CCD image-sensing device. In general, a CCD image-sensing device at least comprises: a row of image-sensing elements (P 1 ˜Pn) for sensing the light energy falling thereon and generating charge packets proportional to the light intensity; a CCD analog shift register with plural register elements (SH 1 ˜SH 2n ) for receiving and storing the charge packets in parallel; and an output amplifier (OP) for converting each of the charge packets into proportional voltage level (Vim). The CCD shift register is controlled by two clock signals φ 1  and φ 2 , shifting the charge packets stored in the register elements serially to the output amplifier (OP). 
     FIGS.  2 ( a ) to  2 ( f ) show the charge transferring process in the CCD shift register depicted in FIG. 1, and the waveforms of the clock signals φ 1  and φ 2 . The structure of the CCD shift register is schematically depicted in FIG.  2 ( a ). For brevity, only 5 gate electrodes (E 1 ˜E 5 ) in the CCD shift register are shown, and the threshold voltage is 0. The 5 gate electrodes E 1 ˜E 5  and the p-type semiconductor substrate (hereinafter referred to as p-type substrate) P sub  form 5 register elements. 
     At time t 1 , φ 1  and φ 2  are at voltage levels 0 and V. The distribution of potential barriers in the p-type substrate P sub  is depicted as FIG.  2 ( b ). The potential barriers beneath the gate electrodes E 1 , E 3 , and E 5  are higher than those beneath the gate electrodes E 2  and E 4 . Hence, the charge packets (depicted as dash lines) will be stored in the regions beneath the gate electrodes E 2  and E 4 , in the p-type substrate P sub . 
     At time t 2 , both φ 1  and φ 2  are at voltage levels V/2, and the distribution of potential barriers in the p-type substrate P sub  is depicted as FIG.  2 ( c ). The arrows depicted in FIG.  2 ( c ) mean when the time changes form t 2  to t 3  the potential barriers beneath odd electrodes will decrease and those beneath even electrodes will increase. 
     At time t 3 , φ 1  and φ 2  are at voltage levels 3V/4 and V/4, and the distribution of potential barriers in the p-type substrate P sub  is depicted as FIG.  2 ( d ). Therefore, the charge packets stored beneath the gate electrodes E 2  and E 4  are transferred to the regions beneath the gate electrodes E 3  and E 5  with lower potential barriers. 
     Finally at time t 4 , φ 1  and φ 2  are at voltage levels V and 0, and the distribution of potential barriers in the p-type substrate P sub  is depicted as FIG.  2 ( e ). 
     During the period from t 1 , to t 4 , the charge packets are transferred toward right side for an electrode. Similarly, during the periods from t 5  to t 6  and t 7  to t 8 , the charge packets are also transferred toward right side for an electrode. 
     The resolution of scanners generally is 600 dpi (dot/inch) or more, however, the resolution of 300 dpi is accurate enough for scanners to scan figures of texts and documents. For a scanner of 600 dpi resolution, the images in every inch of the scanned object are converted into 600 charge packets stored in a CCD shift register. Then, the 600 charge packets are shifted serially to the output amplifier for processing. However, even if the demanded resolution for processing is 300 dpi, the 600 charge packets still must be transferred out one by one. Consequently, the total processing speed is reduced. 
     For the scanner of 600 dpi resolution, if every two or more adjacent charge packets stored in the CCD shift register can be combined by adjusting the potential barrier distribution depicted in FIGS.  2 ( a )˜ 2 ( e ), then only 300 or less adding (combined) charge packets stored in the CCD shift register must be transferred out to reconstruct the image of 300 dpi resolution, thereby improving the charge-transferring speed. 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a method of transferring charge for a scanner. 
     The present invention achieves the above-indicated objects by providing a method of transferring charge for a CCD image-sensing device, the CCD image-sensing device at least having plural (y) image-sensing elements and a CCD shift register with plural (n=2y) register elements, each of the image-sensing elements operating in conjunction with two of the register elements, the method comprising the following steps. 
     Defining a specific number of the register elements (every k register elements) as a charge-combining portion, thereby providing plural (m) charge-combining portions. 
     Make the y image-sensing elements sense light energy falling thereon to generate y charge packets proportional to the light intensity. 
     Transfer the y charge packets in parallel to the CCD shift register; wherein the charge packets coupled to each of the m charge-combining portions is accumulated into one specific register element in each of the m charge-combining portions when the k register elements in each of the m charge-combining portions have coupled the charge packets from the image-sensing elements, thereby generating m adding charge packets in the m charge-combining portions. 
     Deliver each of the adding charge packets serially to the output of the CCD shift register and converting the adding charge packets into proportional voltage levels. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The following detailed description, given by way of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: 
     FIG. 1 shows a schematic structure of a CCD image-sensing device; 
     FIGS.  2 ( a ) to  2 ( f ) show the charge transferring process in the CCD shift register depicted in FIG. 1, and the waveforms of the clock signals φ 1  and φ 2 ; 
     FIGS.  3 ( a ) to  3 ( f ) show the charge transferring process in the CCD shift register according to the first embodiment of the present invention; 
     FIG. 4 shows the waveforms of the control signals ψ 1  to ψ 4  according to the first embodiment of the present invention; 
     FIGS.  5 ( a ) to  5 ( d ) show the charge transferring process in the CCD shift register according to the second embodiment of the present invention; and 
     FIG. 6 shows the waveforms of the control signals Φ 1  to Φ 6  according to the second embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The first embodiment of the present invention will be described hereinafter in detail with reference to FIGS.  3 ( a ) to  3 ( f ) and FIG.  4 . The schematic structure of a CCD image-sensing device in this embodiment is similar with what is depicted in FIG. 1, except of the control signals. 
     The structure of the CCD shift register is schematically depicted in FIG.  3 ( a ). For brevity, only 12 gate electrodes (G 1 ˜G 12 ) in the CCD shift register are shown. The 12 gate electrodes G 1 ˜G 12  and the p-type substrate P sub  form 12 (n=12) register elements (hereinafter G 1 ˜G 12  are referred to as register elements). First, define the register elements (G 1 ˜G 12 ) into 3 (m=3) charge-combining portions, therefore each of the charge-combining portion has 4 (k=4) register elements. The first charge-combining portion comprises the register elements G 1 ˜G 4 ; the second charge-combining portion comprises the register elements G 5 ˜G 8 ; the third charge-combining portion comprises the register elements G 9 ˜G 12 . 
     The register elements G 1 , G 5 , and G 9  are assigned as the first specific register elements corresponding to the first, second and third charge-combining portions. The register elements G 2 , G 6 , and G 10  are assigned as the second specific register elements corresponding to the first, second and third charge-combining portions. 
     In addition, four control signals (ψ 1  to ψ 4 ) are respectively provided to each of the register elements in the charge-combining portions. The first control signal ψ 1  is provided to the first specific register elements G 1 , G 5 , and G 9 ; the second control signal ψ 2  is provided to the register elements G 2 , G 6 , and G 10 ; the third control signal ψ 3  is provided to the register elements G 3 , G 7 , and G 11 ; and the fourth control signal ψ 4  is provided to the register elements G 4 , G 8 , and G 12 . 
     FIG. 4 shows the waveforms of the control signals ψ 1  to ψ 4 . The first control signal ψ 1  is a clock signal with a voltage swing between a voltage level of 0 and a specific voltage level of V a . The second to fourth control signals ψ 2 ˜ψ 4  have a constant voltage level of 3V a /4, V a /2, and V a /4 respectively. 
     Assume that the threshold voltage of the register elements is 0, and the charge packets are transferred along the direction from the register element G 12  to the register element G 1 . 
     Before time T 0 , ψ 1 =V a , ψ 2 =3V a /4, ψ 3 =V a /2, and ψ 2 =V a /4 are provided to bias the register elements G 1 ˜G 12 , and the distribution (or profile) of potential barriers in the p-type substrate P sub  is depicted as FIG.  3 ( b ). 
     Input and Combination of the Charge Packets 
     Before time T 0 , let the image-sensing elements (in this embodiment: they are P 1 ˜P 6 ) of a CCD image-sensing device sense the light energy falling thereon to generate six charge packets proportional to the light intensity. 
     Then, the six charge packets are transferred in parallel to the CCD shift register of the CCD image-sensing device. The charge packets (depicted as dash lines) should be stored in the register elements G 1 , G 3 , G 5 , G 7 , G 9 , G 11 , i.e. the regions beneath the gate electrodes G 1 , G 3 , G 5 , G 7 , G 9 , G 11  in the p-type substrate P sub . However, the charge packets in the register elements G 3 , G 7 , G 11  immediately moves to the register elements G 1 , G 5 , G 9  respectively, because the distribution of potential barriers in the p-type beneath the electrodes G 1 ˜G 4 , G 5 ˜G 8 , G 9 ˜G 12  present stair-like profiles due to the bias of the first to fourth control signals ψ 1 ˜ψ 4 . Therefore, the charge packets stored in the register elements G 3 , G 7 , G 11  will move to the register elements G 1 , G 5 , G 9  and are combined with the charge packets stored in the register elements G 1 , G 5 , G 9  respectively. There are three charge packets stored in the register elements G 1 , G 5 , G 9 , as shown in FIG.  3 ( b ). 
     Charge Transferring 
     During the period between time T 0  and T 2 , the CCD shift register carried out charge transferring process. 
     At time T 1 , ψ 2 ˜ψ 4  keep constant (ψ 2 =3V a /4, ψ 3 =V a /2, and ψ 2 =V a /4), and ψ 1  decreases to V a /2. The distributions of potential barriers in the p-type substrate beneath the electrodes G 2 ˜G 4 , G 6 ˜G 8 , G 10 ˜G 12  still are downward stair-like, and the potential barriers beneath the electrodes G 1 , G 5 , and G 9  increase, as depicted in FIG.  3 ( c ). 
     At time T 2 , ψ 2 ˜ψ 4  keep constant (ψ 2 =3V a /4, ψ 3 =V a /2, and ψ 2 =V a /4), and ψ 1  decreases to 0. The distributions of potential barriers in the p-type substrate beneath the electrodes G 2 ˜G 4 , G 6 ˜G 8 , G 10 ˜G 12  still are downward stair-like, and the potential barriers beneath the electrodes G 1 , G 5 , and G 9  all increase to the level higher than those beneath the other electrodes, as depicted in FIG.  3 ( d ). The three charge packets stored in the register elements G 1 , G 5 , G 9  will move toward the low potential position. Therefore, the charge packets stored in the register elements G 5 , G 9  (and G 13  which is not shown in FIG.  3 ( d )) are transferred to the second specific register elements G 2 , G 6 , and G 10  respectively, and the charge packet stored in the register elements G 1  is moved out of the CCD shift register. 
     During the period between time T 3  and T 5 , the CCD shift register carried out charge transferring process. 
     At time T 4 , ψ 2 ˜ψ 4  keep constant (ψ 2 =3V a /4, ψ 3 =V a /2, and ψ 2 =V a /4), and ψ 1  increases from 0 to V a /2. The distributions of potential barriers in the p-type substrate beneath the electrodes G 2 ˜G 4 , G 6 ˜G 8 , G 10 ˜G 12  still are downward stair-like, and the potential barriers beneath the electrodes G 1 , G 5 , and G 9  decrease, as depicted in FIG.  3 ( e ). 
     At time T 5 , ψ 2 ˜ψ 4  keep constant (ψ 2 =3V a /4, ψ 3 =V a /2, and ψ 2 =V a /4), and ψ 1  increases to V a . The distributions of potential barriers in the p-type substrate beneath the electrodes G 2 ˜G 4 , G 6 ˜G 8 , G 10 ˜G 12  still are downward stair-like, and the potential barriers beneath the electrodes G 1 , G 5 , and G 9  further decrease to the level lower than those beneath the other electrodes (such as G 2 , G 6 , G 10 ) as depicted in FIG.  3 ( f ). Now, the three charge packets stored in the second specific register elements G 2 , G 6 , G 10  will move to the first specific register elements of lower potential barriers (i.e., G 1 , G 5 , and G 9 ). Therefore, the charge packets stored in the second specific register elements G 2 , G 6 , G 10  (in FIG.  3 ( e )) are transferred to the first specific register elements G 1 , G 5 , G 9  respectively, as shown in FIG.  3 ( f ). 
     Similarly, during the period between time T 6  and T 7 , the CCD shift register carried out charge transferring process. The charge transferring process between the time T 6  and T 7  is the same as that between the time T 0  and T 2 . 
     All charge packets stored in the CCD shift register can be serially shifted out by repeating the operations during the time periods T 0 ˜T 2  and T 3 ˜T 5 . 
     From above descriptions, it is quite clear that every two charge packets sensed by every two image-sensing elements are combined into an adding charge packets in each of the charge-combining portions by adjusting the distribution of potential barrier of the register elements in each of the charge-combining portions. Then, each of the adding charge packets is shifted out of the CCD shift register serially. 
     Using the method of transferring charges according to the present invention obtains the following advantages: 
     (1) Each of the adding charge packets is formed by combine two charge packets sensed by two adjacent image-sensing elements. Therefore, the exposure time required to sense images for the image-sensing elements in a CCD image-sensing device can be reduced in half. In the first embodiment, after the charge packets sensed by the image-sensing elements P 1  and P 2  are inputted to the register elements G 1  and G 3 , the two charge packets are combined into an adding charge packet and stored in the register element G 1 , and thus exposure time of the image-sensing elements P 1  and P 2  can be reduced in half. 
     (2) In the conventional art, the shift of each of the charge packets is only moved with a shift of a register element. According to the present invention, the shift of each of the adding charge packets is moved with an average shift more than two register element. The speed for shifting out the adding charge packets speeds up, therefore the processing speed of the CCD image-sensing device is improved. 
     (3) By appropriate providing and switching the control signals used to bias the register elements, a novel CCD register which can carries charge transferring process in conventional way or in the way of the present invention, depending on the choice of the resolution required by users. 
     In the first embodiment, every two charge packets sensed by every two adjacent image-sensing elements are combined into an adding charge packet and then shifted in aerial. Therefore, the CCD image-sensing device with the resolution of 600 dpi will output the adding charge packets in the resolution of 300 dpi. However, the present invention is not limited to only be able to combine every two charge packets into an adding charge packet. Any number of charge packets can be combined into an adding charge packet by providing appropriate control signals for bias register elements, and then each of the adding charge packets is shifted out of the CCD shift register serially. 
     FIGS.  5 ( a ) to  5 ( d ) show the charge transferring process in the CCD shift register according to the second embodiment of the present invention. FIG. 6 shows the waveforms of the control signals Φ 1  to Φ 6  according to the second embodiment of the present invention. In the second embodiment, every three (x=3) charge packets sensed by every three (x=3) adjacent image-sensing elements are combined into an adding charge packet and then shifted in aerial. Each of the charge-combining portion has six register elements. 
     In FIG. 6, the first control signal Φ 1  is a clock signal with a voltage swing between a voltage level of 0 and a specific voltage level of V b . The second to sixth control signals Φ 2 ˜Φ 6  have a constant voltage level of 5V b /6, 4V a /6, V a /2, 2V a /6, and V a /6 respectively. 
     If x charge packets sensed by x image-sensing elements are combined into an adding charge packets in a charge-combining portion comprising k (2x=6) register elements, the first control signal of the k control signals is a clock signal with a voltage swing between a voltage level of 0 and a specific voltage level of V b , and the j-th control signal of the k control signals has a constant voltage level of          (         k   +   1   -   j     k          V   a       )     ,                          
     where 2≦j≦k. 
     Referring to FIGS.  5 ( a )˜ 5 ( d ), the charge packets sensed by the image-sensing elements P 1 ˜P 6  are inputted in parallel to the CCD shift register. Due to the bias of the control signals Φ 1 ˜Φ 6 , the distributions of the potential barriers beneath the register elements G 1 ˜G 6  and G 7 ˜G 12  are downward stair-like. Therefore, the charge packets in the register elements G 3  and G 5  move to the register elements G 3  and combines with the charge packet in the register element G 1  to form an adding charge packet. The charge packets in the register elements G 9  and G 11  move to the register elements G 7  and combines with the charge packet in the register element G 7  to form an adding charge packet. Two adding charge packets are stored in the register elements G 1  and G 7 , as depicted in FIG.  5 ( b ). 
     Then the two adding charge packets are shifted out of the CCD shift register. The transferring process is depicted in FIGS.  5 ( c ) and  5 ( d ), and it is similar with the process described in the first embodiment. 
     While the invention has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. For example, the control signals used to bias the register elements can have different waveforms with what the two embodiments is proposed. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.