Abstract:
A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-175787 filed on Aug. 29, 2014, the disclosure of which is incorporated herein in its entirety by reference. 
     FIELD OF THE PRESENT INVENTION 
     The present invention relates to a semiconductor module, in particular, relates to a semiconductor module mounting a plurality of semiconductor chips on a module substrate. 
     DESCRIPTION OF THE PRIOR ART 
     A semiconductor module such as a memory module includes a plurality of semiconductor chips mounted on a module substrate. See JP 2004-62530A1. For example, a memory module called Registered DIMM (RDIMM) has a register chip which receives address signals and command signals supplied from outside. The register chip outputs the address signals and the command signals in common to a plurality of Dynamic Random Access Memories (DRAMs) via a wiring pattern on the module substrate. 
     On the contrary, a termination resistor is provided to an end of the wiring pattern in order to prevent reflection of the signals at the end. The termination resistor is mounted in the vicinity of an end of the module substrate. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1 a  and 1 b    are plan views showing a semiconductor module according to an embodiment of the present invention,  FIG. 1 a    is a drawing viewed from a first principal surface side, and  FIG. 1 b    is a drawing viewed from a second principal surface side; 
         FIG. 2  is a circuit diagram for explaining the connections of a register chip and semiconductor chips; 
         FIG. 3  is a schematic diagram showing a wiring layer provided on a first principal surface, which is an uppermost layer; 
         FIG. 4  is a schematic diagram showing a wiring layer provided in a second layer; 
         FIG. 5  is a schematic diagram showing a wiring layer provided in a third layer; 
         FIG. 6  is a schematic diagram showing a wiring layer provided in a fourth layer; 
         FIG. 7  is a schematic diagram showing a wiring layer provided in a fifth layer; 
         FIG. 8  is a schematic diagram showing a wiring layer provided in a sixth layer; 
         FIG. 9  is a schematic diagram showing a wiring layer provided in a seventh layer; 
         FIG. 10  is a schematic diagram showing a wiring layer provided in an eighth layer; 
         FIG. 11  is a schematic diagram showing a wiring layer provided in a ninth layer; 
         FIG. 12  is a schematic diagram showing a wiring layer provided in a tenth layer; 
         FIG. 13  is a schematic diagram showing a wiring layer provided in an eleventh layer; 
         FIG. 14  is a schematic diagram showing a wiring layer provided on a second principal surface, which is a lowermost layer; 
         FIG. 15  is a schematic diagram showing a layout of terminal electrodes provided on each of the semiconductor chips; 
         FIG. 16  is a schematic diagram for explaining the distance between data terminals and an external terminal in the present embodiment; 
         FIG. 17  is a schematic drawing for explaining the distance between data terminals and an external terminal in a reference example; 
         FIG. 18  is a graph showing simulation results of ringback margins; 
         FIG. 19  is a graph showing simulation results of ringback margins; 
         FIG. 20  is a graph showing simulation results of eye widths; 
         FIG. 21  is a graph showing simulation results of eye widths; 
         FIG. 22  is a graph showing simulation results of jitter; 
         FIG. 23  is a graph showing simulation results of jitter; 
         FIG. 24  is a graph showing simulation results of ringback margins; 
         FIG. 25  is a graph showing simulation results of eye widths; 
         FIG. 26  is a graph showing simulation results of jitter; 
         FIG. 27  is a graph showing simulation results of ringback margins; 
         FIG. 28  is a graph showing simulation results of eye widths; 
         FIG. 29  is a graph showing simulation results of jitter; 
         FIG. 30 a    is a table showing an example of parameters for calculating an optimum resistance value of a termination resistor Rterm, and  FIG. 30 b    is a table showing the values of the resistance value Rterm obtained; 
         FIG. 31  is a graph showing simulation results of ringback margins; 
         FIG. 32  is a graph showing simulation results of eye widths; and 
         FIG. 33  is a graph showing simulation results of jitter. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIGS. 1 a  and 1 b    are plan views showing a semiconductor module according to an embodiment of the present invention.  FIG. 1 a    is a drawing viewed from a first principal surface side, and  FIG. 1 b    is a drawing viewed from a second principal surface side. 
     The semiconductor module includes semiconductor chips M 1  to M 36  and one register chip RB mounted on a module substrate  10 . The semiconductor chips M 1  to M 36  are not particularly limited to, but are DRAMs. The module substrate  10  is a rectangular substrate using an X-direction as a longitudinal direction, the semiconductor chips M 1  to M 18  and the register chip RB are mounted on a first principal surface  11  thereof, and the semiconductor chips M 19  to M 36  are mounted on a second principal surface  12 . 
     In more detailed explanations, on the first principal surface  11  of the module substrate  10 , the register chip RB is mounted on an approximately central portion in the X-direction, the semiconductor chips M 1  to M 10  are mounted in a first side (left side) viewed from the register chip RB, and the semiconductor chips M 11  to M 18  are mounted in a second side (right side) viewed from the register chip RB. These semiconductor chips M 1  to M 18  are arranged in two levels in a Y-direction, the semiconductor chips M 1  to M 5  and M 11  to M 14  are arranged in the X-direction in a first row (upper level), and the semiconductor chips M 6  to M 10  and M 15  to M 18  are arranged in the X-direction in a second row (lower level). The lower level refers to the side close to a plurality of external terminals  20 , which are provided along a long side of the module substrate  10 . 
     The semiconductor chips M 19  to M 36  mounted on the second principal surface  12  of the module substrate  10  are mounted at the positions respectively overlapped with the above described semiconductor chips M 1  to M 18  in a planar view. Therefore, the semiconductor chips M 19  to M 23  and M 29  to M 32  are arranged in the X-direction in a first row (upper level), and the semiconductor chips M 24  to M 28  and M 33  to M 36  are arranged in the X-direction in a second row (lower level). 
     The planar shapes of the semiconductor chips M 1  to M 36  are oblong. The semiconductor chips in the first row (upper level) are vertical, in other words, are disposed so that the long sides thereof are directed toward the Y-direction, and the semiconductor chips in the second row (lower level) are horizontal, in other words, are disposed so that the long sides thereof are directed toward the X-direction. In this manner, the semiconductor chips mounted in the upper level and the semiconductor chips mounted in the lower level have mounting directions which are mutually different by 90°. 
     The plurality of external terminals  20  include command/address terminals to which address signals, command signals, etc. are input and data terminals which input/output data. The address signals and command signals input via the command/address terminals are once input to the register chip RB. The register chip RB buffers the input address signals and command signals and supplies them in common to the semiconductor chips M 1  to M 36  via a wiring pattern provided on the module substrate  10 . In other words, the address signals and the command signals are input in common to the semiconductor chips M 1  to M 36 . 
     On the other hand, part or all of the data output from the semiconductor chips M 1  to M 36  are output to outside via mutually different data terminals. Similarly, part or all of the data input from outside are supplied to the semiconductor chips M 1  to M 36  via mutually different data terminals. The present embodiment is not particularly limited to but does not provide register buffers or the like between the semiconductor chips M 1  to M 36  and the data terminals. 
     The module substrate  10  has mount regions TR 1  to TR 8  in which termination resistors Rterm are mounted. The termination resistors Rterm include extremely small chip parts and are used for terminating the address signals and the command signals output from the register chip RB. In the present embodiment, the mount region TR 1  is disposed between the semiconductor chips M 1  and M 2 , the mount region TR 2  is disposed between the semiconductor chip M 6  and the external terminal  20 , the mount region TR 3  is disposed between the semiconductor chips M 11  and M 12 , and the mount region TR 4  is disposed between the semiconductor chip M 15  and the external terminal  20 . Meanwhile, on the second principal surface  12 , the mount regions TR 5  to TR 8  are disposed at the positions overlapped with the mount regions TR 1  to TR 4  in the planar view. 
     Since the termination resistors Rterm include extremely-small-sized chip parts, the joint strength thereof with respect to the module substrate  10  is lower than that of the semiconductor chips M 1  to M 36 , and the risk of detachment is high in a case of contact upon handling, etc. Such a problem is particularly notable at the termination resistors Rterm in the upper level, which are readily contacted upon handling. However, since the mount regions TR 1 , TR 3 , TR 5 , and TR 7  positioned in the upper level are positioned not at ends of the module substrate  10 , but at the parts sandwiched by the two semiconductor chips, the risk of contact with the chip parts upon handling is low. This is for a reason that the heights of the chip parts of the termination resistors Rterm are lower than the heights of the semiconductor chips in addition to the fact that they are distant from the vicinities of the short sides which mainly serve as contact parts upon handling. 
       FIG. 2  is a circuit diagram for explaining the connections of the register chip RB and the semiconductor chips M 1  to M 10  and M 19  to M 28 . Since the connections of the register chip RB and the semiconductor chips M 11  to M 18  and M 29  to M 36  are almost the same, redundant explanations are omitted. 
     The address signals and command signals output from the register chip RB are supplied in common to the semiconductor chips M 1  to M 10  and M 19  to M 28  via a wiring pattern  30 . The same address signals and command signals are supplied also to the other semiconductor chips M 11  to M 18  and M 29  to M 36 , but illustration thereof is omitted. 
     The wiring pattern  30  first branches into wiring parts  31  and  32  at a branching point B 0 . The part between the register chip RB and the branching point B 0  includes a wiring part TL 0  provided in an inner layer or at a principal surface of the module substrate  10 . The length of the wiring part TL 0  is, for example, 3.3 mm. The wiring part  31  is connected to the semiconductor chips M 1  to M 5  and M 19  to M 23  disposed in the upper level, and the wiring part  32  is connected to the semiconductor chips M 6  to M 10  and M 24  to M 28  disposed in the lower level. 
     The wiring part  31  branches at branching points B 10  to B 15  and are connected to the semiconductor chips M 1  to M 5  and M 19  to M 23 , respectively. 
     The branching point B 10  is connected to the branching point B 0  via a wiring part TL 1  and is connected to the semiconductor chips M 5  and M 23  via wiring parts TL 2 . The wiring part TL 1  is provided in the inner layer of the module substrate  10 , and the length thereof is, for example, 20 mm. On the other hand, the wiring part TL 2  is provided on the principal surface  11  or  12 , which is a surface layer of the module substrate  10 , and length thereof is, for example, 3 mm. 
     The branching point B 11  is connected to the branching point B 10  via a wiring part TL 31  and is connected to the semiconductor chips M 4  and M 22  via wiring parts TL 2 . The wiring part TL 31  is provided in the inner layer of the module substrate  10 , and the length thereof is, for example, 23 mm. 
     The branching point B 12  is connected to the branching point B 11  via a wiring part TL 32  and is connected to the semiconductor chips M 3  and M 21  via wiring parts TL 2 . The wiring part TL 32  is provided in the inner layer of the module substrate  10 , and the length thereof is, for example, 18 mm. 
     The branching point B 13  is connected to the branching point B 12  via a wiring part TL 33  and is connected to the semiconductor chips M 2  and M 20  via wiring parts TL 2 . The wiring part TL 33  is provided in the inner layer of the module substrate  10 , and the length thereof is, for example, 18 mm. 
     The branching point B 14  is connected to the branching point B 13  via a wiring part TL 4  and is connected to a first end of the termination resistor Rterm via a wiring part TL 5 . A terminal power source VTT is supplied to a second end of the termination resistor Rterm. The wiring part TL 4  is provided in the inner layer of the module substrate  10 , and the length thereof is preferred to be 21 mm or less. The wiring part TL 5  is provided in the surface layer of the module substrate  10 , and the length thereof is preferred to be 21 mm or less. 
     The branching point B 15  is connected to the branching point B 14  via a wiring part TL 6  and is connected to the semiconductor chips M 1  and M 19  via wiring parts TL 2 . The wiring part TL 6  is provided in the inner layer of the module substrate  10 , and the length thereof is preferred to be shorter than that of the wiring part TL 4  and is particularly preferred to be 6 mm or less. The sum of the lengths of the wiring parts TL 4  and TL 6  is preferred to be longer than the wiring part TL 5 . 
     The termination resistor Rterm is connected to the wiring part  31 . The termination resistor Rterm is not connected to a terminal portion (part) or an end portion of the wiring part  31 , but to the part branched from the wiring parts TL 4  and TL 6  connecting the semiconductor chips M 1  and M 2  (M 19  and M 20 ). Therefore, the resistance value of the termination resistor Rterm may be required to be a value different from that of a prior case in which it is connected to the terminal or end portion. Furthermore, the lengths and interrelations of the wiring parts TL 4  to TL 6 , etc., which are close to the termination resistor Rterm also may have to be designed in consideration of the above described topology. 
     On the other hand, the wiring part  32  branches at branching points B 20  to B 24  and are connected to the semiconductor chips M 6  to M 10  and M 24  to M 28 , respectively. 
     The branching point B 20  is connected to the branching point B 0  via a wiring part TL 1  and is connected to the semiconductor chips M 10  and M 28  via wiring parts TL 2 . 
     The branching point B 21  is connected to the branching point B 20  via the wiring part TL 31  and is connected to the semiconductor chips M 9  and M 27  via wiring parts TL 2 . 
     The branching point B 22  is connected to the branching point B 21  via a wiring part TL 32  and is connected to the semiconductor chips M 8  and M 26  via wiring parts TL 2 . 
     The branching point B 23  is connected to the branching point B 22  via a wiring part TL 33  and is connected to the semiconductor chips M 7  and M 25  via wiring parts TL 2 . 
     The branching point B 24  is connected to the branching point B 23  via a wiring part TL 34  and is connected to the semiconductor chips M 6  and M 24  via wiring parts TL 2 . The wiring part TL 34  is provided in the inner layer of the module substrate  10 , and the length thereof is, for example, 18 mm. 
     The branching point B 24  is connected to a connecting point B 25  via a wiring part TL 7 , and the connecting point B 25  is connected to the termination resistor Rterm via a wiring part TL 8 . The wiring part TL 7  is provided in the inner layer of the module substrate  10 , and the length thereof is, for example, 12 mm. The wiring part TL 8  is provided in the surface layer of the module substrate  10 , and the length thereof is, for example, 1 mm. 
     In this manner, the termination resistor Rterm is connected to a terminal portion (part) or an end portion of the wiring part  32 . 
     Next, a multi-layer wiring structure formed in the surface layer and the inner layer of the module substrate  10  will be explained. 
       FIG. 3  to  FIG. 14  are schematic drawings respectively showing wiring layers formed in the surface layer or the inner layer of the module substrate  10 . All of  FIG. 3  to  FIG. 14  show the structures viewed from the first principal surface  11  side of the module substrate  10  and therefore transparently illustrate the wiring layers positioned in the back surface viewed from the first principal surface  11 . 
     As shown in  FIG. 3 , in the wiring layer provided on the first principal surface  11 , which is an uppermost layer, a VDD pattern is disposed at an approximately central part, and VSS patterns are disposed in both sides thereof. The VDD pattern is a power source pattern to which a power-source potential VDD of a high-potential side is supplied via the external terminal  20 . The VSS patterns are power source patterns to which a ground potential VSS is supplied via the external terminals  20 . 
     As shown in  FIG. 4 , in the wiring layer provided in a second layer, a VDD pattern is disposed in an approximately central part, and VSS patterns are disposed in both sides thereof. The VDD pattern provided in the second layer is connected to the VDD pattern of the principal surface  11  via a through-hole conductor. Similarly, the VSS patterns provided in the second layer are connected to the VSS patterns of the principal surface  11  via through-hole conductors. 
     As shown in  FIG. 5 , mainly a VPP pattern is disposed in the wiring layer provided in a third layer, and wiring patterns  41  and  42  for address signals and command signals and wiring patterns  51  for data are provided in the regions in which the VPP pattern is not disposed. The VPP pattern is a power source pattern to which a voltage-increasing potential VPP is supplied via the external terminal  20 . The wiring pattern  41  is used for supplying the address signals, command signals, etc., which are input via the external terminals  20 , to the register chip RB. The wiring patterns  42  are part of the wiring part TL 7  shown in  FIG. 2 . Furthermore, the wiring patterns  51  are used for connecting the semiconductor chips M 1  to M 5 , M 11  to M 14 , M 19  to M 23 , and M 29  to M 32  disposed in the upper level and data terminals. 
     As shown in  FIG. 6 , in the wiring layer provided in a fourth layer, part of the wiring patterns  30  for address signals and command signals is provided. The wiring patterns  30  are wiring for supplying the address signals and command signals, which are output from the register chip RB, to the semiconductor chips M 1  to M 36  as described above. The rest part of the wiring patterns  30  is provided in a sixth layer shown in  FIG. 8 , a seventh layer shown in  FIG. 9 , and a ninth layer shown in  FIG. 11 . 
     As shown in  FIG. 7  and  FIG. 10 , VDD patterns are provided in the wiring layers provided in a fifth layer and an eighth layer. A reason why the VDD patterns are provided in the fifth layer and the eighth layer is that the address signals, the command signals, etc. which transmit through the wiring patterns  30  are the signals using the power-source potential VDD as a reference. 
     As shown in  FIG. 12 , mainly a VPP pattern is disposed in the wiring layer provided in a tenth layer, and wiring patterns  42  for address signals and command signals and wiring patterns  52  for data are provided in the regions in which the VPP pattern is not disposed. The wiring patterns  52  are used for connecting the semiconductor chips M 6  to M 10 , M 15  to M 18 , M 24  to M 28 , and M 33  to M 36  disposed in the lower level and data terminals. 
     As shown in  FIG. 13 , in the wiring layer provided in an eleventh layer, as well as the second layer, a VDD pattern is disposed in an approximately central part, and a VSS pattern is disposed in both sides thereof. 
     Then, as shown in  FIG. 14 , in the wiring layer provided on the second principal surface  12 , which is a lowermost layer, a VSS pattern is disposed. The VSS pattern provided in the lowermost layer is connected to the VSS pattern of the eleventh layer via a through-hole conductor. 
     Hereinabove, the multi-layer wiring structure of the module substrate  10  has been described. 
       FIG. 15  is a schematic diagram showing a layout of terminal electrodes provided on the semiconductor chips M 1  to M 36 . 
     As shown in  FIG. 15 , a plurality of terminal electrodes  60  are laid out like a matrix on the back surfaces of the semiconductor chips M 1  to M 36 . The plurality of terminal electrodes  60  include command/address terminals CA for inputting address signals, command signals, etc. and data terminals DQ for inputting/outputting data. In addition to that, many power-source terminals, etc. may be included. The data terminals DQ are disposed in a first side of the long-side direction and in the side with an index IND. The command/address terminals CA are disposed in a second side of the long-side direction and in the side without the index IND. 
     As a result, as shown in  FIG. 16 , which is a schematic diagram, the distance between the data terminals DQ (shaded regions) of each of the semiconductor chips M 1  to M 5 , M 11  to M 14 , M 19  to M 23 , and M 29  to M 32  disposed in the upper level and the external terminal  20  is shortened, and signal quality of data can be therefore increased. On the other hand, in the case of a layout according to a reference example shown in  FIG. 17 , the effect of preventing detachment of the chip parts of the termination resistor Rterm can be obtained by some degree. However, since the distances between the data terminals DQ (shaded regions) of the semiconductor chips M 1  to M 5 , M 11  to M 14 , M 19  to M 23 , and M 29  to M 32  disposed in the upper level and the external terminal  20  become long, signal quality of data may be reduced. 
     In this manner, the semiconductor module according to the present embodiment can not only prevent detachment of the chip parts of the termination resistors Rterm, but also can increase the signal quality of data input/output to/from the semiconductor chips disposed in the upper level. 
     Next, a method of optimizing a signal terminating function by the termination resistor Rterm will be explained. 
     As described above, at the wiring part  31 , the termination resistor Rterm is connected not to the terminal part, but to the part branched from the wiring parts TL 4  and TL 6  connecting the semiconductor chips M 1  and M 2 , and M 19  and M 20 , respectively. Therefore, in order to correctly terminate signals by the termination resistor Rterm, an approach different from a normal one is required. 
     First, the position of the branching point B 14  will be examined. The branching point B 14  is an element which determines the lengths of the wiring part TL 4  and the wiring part TL 6 , and a ratio of the wiring part TL 4  and the wiring part TL 6  is determined by the position thereof. Signal quality can be increased by designing the position of the branching point B 14  so that the length of the wiring part TL 6  becomes shorter than the wiring part TL 4 . In other words, it is preferred to satisfy below expression (1).
 
 TL 6&lt; TL 4  (1)
 
     The branching point B 14  is also an element which determines the length of the wiring part TL 5  connected to the termination resistor Rterm. The wiring part TL 5  is preferred to be short and, specifically, is preferred to be shorter than the total length of the wiring parts TL 4  and TL 6 . In other words, it is preferred to satisfy a below expression (2).
 
 TL 5&lt; TL 4+ TL 6  (2)
 
     The resistance value of the termination resistor Rterm is preferred to be designed in consideration of the inductance of the wiring parts TL 4  to TL 6 . In this case, the wiring parts TL 4  and TL 6  are branched from the branching point B 14  when viewed from the termination resistor Rterm. Therefore, the influence of each of them can be estimated to be half. Furthermore, the resistance value of the termination resistor Rterm is preferred to be designed in consideration of the input capacitance of the closest semiconductor chips M 1 , M 2 , M 19 , and M 20  and the capacitance of the wiring parts TL 2  connected thereto in addition to the capacitance of the wiring parts TL 4  to TL 6 . Specifically, the resistance value of the termination resistor Rterm is preferred to satisfy a below expression (3). 
     
       
         
           
             
               
                 
                   Rterm 
                   ≅ 
                   
                     
                       
                         
                           Lo 
                           × 
                           TL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                         
                         + 
                         
                           
                             ( 
                             
                               Li 
                               × 
                               TL 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               4 
                             
                             ) 
                           
                           / 
                           2 
                         
                         + 
                         
                           
                             ( 
                             
                               Li 
                               × 
                               TL 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               6 
                             
                             ) 
                           
                           / 
                           2 
                         
                       
                       
                         
                           Co 
                           × 
                           TL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                         
                         + 
                         
                           Ci 
                           × 
                           TL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           6 
                         
                         + 
                         
                           Ci 
                           × 
                           TL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                         + 
                         
                           4 
                           × 
                           Co 
                           × 
                           TL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                         + 
                         
                           4 
                           × 
                           C_pkg 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     In the expression (3), Lo represents the inductance per unit length of the wiring part positioned in the surface layer, and Li represents the inductance per unit length of the wiring part positioned in the inner layer. Co represents the capacitance per unit length of the wiring part positioned in the surface layer, and Ci represents the capacitance per unit length of the wiring part positioned in the inner layer. Cpkg represents the input capacitance of the semiconductor chip. 
     Hereinafter, evaluation results according to simulations will be explained. 
       FIG. 18  and  FIG. 19  are simulation results showing ringback margins of the cases in which the lengths of TL 4  to T 16  are variously varied when TL 4 +TL 6 =18 mm. Herein,  FIG. 18  shows the case in which TL 4 =TL 6 =9 mm, and  FIG. 19  shows the case in which TL 4 =12 mm and TL 6 =6 mm. As shown in  FIG. 18  and  FIG. 19 , it can be understood that, when the length of the wiring part TL 5  and the resistance value Rterm are the same, larger ringback margins are obtained by the condition (TL 6 &lt;TL 4 ) shown in  FIG. 19  than by the condition (TL 4 =TL 6 ) shown in  FIG. 18 . In other words, it can be understood that the ringback margins are increased when the expression (1) is satisfied. 
       FIG. 20  and  FIG. 21  show simulation results showing eye widths (Eye Width) of the case in which the lengths of TL 4  to TL 6  are variously varied when TL 4 +TL 6 =18 mm. Herein,  FIG. 20  shows the case of TL 4 =TL 6 =9 mm, and  FIG. 21  shows the case of TL 4 =12 mm and TL 6 =6 mm. As shown in  FIG. 20  and  FIG. 21 , it can be understood that, when the length of the wiring part TL 5  and the resistance value Rterm are the same, larger eye widths are obtained by the condition (TL 6 &lt;TL 4 ) shown in  FIG. 21  than by the condition (TL 4 =TL 6 ) shown in  FIG. 20 . In other words, it can be understood that the eye widths are increased when the expression (1) is satisfied. 
       FIG. 22  and  FIG. 23  are simulation results showing jitter of the cases in which the lengths of the TL 4  to T 6  are variously varied when TL 4 +T 16 =18 mm. Herein,  FIG. 22  shows the case in which TL 4 =TL 6 =9 mm, and  FIG. 23  shows the case in which TL 4 =12 mm and TL 6 =6 mm. As shown in  FIG. 22  and  FIG. 23 , it can be understood that when the length of the wiring part TL 5  and the resistance value Rterm are the same, smaller jitter is obtained by the condition (TL 6 &lt;TL 4 ) shown in  FIG. 23  than by the condition (TL 4 =TL 6 ) shown in  FIG. 22 . In other words, it can be understood that jitter can be reduced when the expression (1) is satisfied. 
       FIG. 24  shows simulation results showing ringback margins of the cases in which the length of TL 5  is variously varied when TL 4 =12 mm and TL 6 =4 mm. As shown in  FIG. 24 , it can be understood that, when the resistance value Rterm is the same, larger ringback margins are obtained when the condition of TL 5 &lt;TL 4 +TL 6  is satisfied than the case of TL 5 &gt;TL 4 +TL 6 . In other words, it can be understood that the ringback margins are increased when the expression (2) is satisfied. 
       FIG. 25  shows simulation results showing eye widths of the cases in which the length of TL 5  is variously varied when TL 4 =12 mm and TL 6 =4 mm. As shown in  FIG. 25 , it can be understood that, when the resistance value Rterm is the same, larger eye widths are obtained when the condition of TL 5 &lt;TL 4 +TL 6  is satisfied than the case of TL 5 &gt;TL 4 +TL 6 . In other words, it can be understood that the eye widths are increased when the expression (2) is satisfied. 
       FIG. 26  shows simulation results showing jitter of the cases in which the length of TL 5  is variously varied when TL 4 =12 mm and TL 6 =4 mm. As shown in  FIG. 26 , it can be understood that, when the resistance value Rterm is the same, smaller jitter is obtained when the condition of TL 5 &lt;TL 4 +TL 6  is satisfied than the case of TL 5 &gt;TL 4 +TL 6 . In other words, it can be understood that jitter is reduced when the expression (2) is satisfied. 
       FIG. 27  shows simulation results showing ringback margins of the cases in which the length of TL 4  is variously varied when TL 5 =9 mm, TL 6 =4 mm, and Rterm=30Ω. As shown in  FIG. 27 , it can be understood that, when the conditions of TL 6 &lt;TL 4  and TL 5 &lt;TL 4 +TL 6  are satisfied, larger ringback margins are obtained compared with the case in which these conditions are not satisfied. In other words, it can be understood that the ringback margins are increased when the expressions (1) and (2) are satisfied. 
       FIG. 28  shows simulation results showing eye widths of the cases in which the length of TL 4  is variously varied when TL 5 =9 mm, TL 6 =4 mm, and Rterm=30Ω. As shown in  FIG. 28 , it can be understood that larger eye widths are obtained when the conditions of TL 6 &lt;TL 4  and TL 5 &lt;TL 4 +TL 6  are satisfied compared with the case in which these conditions are not satisfied. In other words, it can be understood that the eye widths are increased when the expressions (1) and (2) are satisfied. 
       FIG. 29  shows simulation results showing jitter of the case in which the length of TL 4  is variously varied when TL 5 =9 mm, TL 6 =4 mm, and Rterm=30Ω. As shown in  FIG. 29 , it can be understood that smaller jitter is obtained when the conditions of TL 6 &lt;T 14  and TL 5 &lt;TL 4 +TL 6  are satisfied compared with the case in which these conditions are not satisfied. In other words, it can be understood that jitter is reduced when the expressions (1) and (2) are satisfied. 
       FIG. 30 a    is a table showing an example of parameters for calculating an optimum resistance value of the termination resistor Rterm. In a case in which the parameters shown in  FIG. 30 a    are used, when the lengths of the wiring parts TL 2  and TL 4  to TL 6  are substituted into the expression (3), the value of the obtained resistance value Rterm becomes as shown in  FIG. 30   b.    
       FIG. 31  shows simulation results showing ringback margins of the cases of the resistance value of the termination resistor Rterm obtained by the expression (3) and those varied by ±5Ω under the conditions of Example 1 to Example 4 shown in  FIG. 30 b   . As shown in  FIG. 31 , it can be understood that, when the resistance value of the termination resistor Rterm is set to the value obtained by the expression (3) under all of the conditions of Example 1 to Example 4, larger ringback margins are obtained compared with the cases in which the resistance value is varied by ±5Ω. In other words, it can be understood that, when the resistance value of the termination resistor Rterm is set to the resistance value obtained by the expression (3), the ringback margins are increased. 
       FIG. 32  shows simulation results showing eye widths of the cases of the resistance value of the termination resistor Rterm obtained by the expression (3) and those varied by ±5Ω under the conditions of Example 1 to Example 4 shown in  FIG. 30 b   . As shown in  FIG. 32 , it can be understood that, when the resistance value of the termination resistor Rterm is set to the value obtained by the expression (3) under all of the conditions of Example 1 to Example 4, larger eye widths are obtained compared with the cases in which the resistance value is varied by ±5Ω. In other words, it can be understood that the eye widths are increased when the resistance value of the termination resistor Rterm is set to the resistance value obtained by the expression (3). 
       FIG. 33  shows simulation results showing jitter of the cases of the resistance value of the termination resistor Rterm obtained by the expression (3) and those varied by ±5Ω under the conditions of Example 1 to Example 4 shown in  FIG. 30 b   . As shown in  FIG. 33 , it can be understood that, when the resistance value of the termination resistor Rterm is set to the value obtained by the expression (3) under all of the conditions of Example 1 to Example 4, smaller jitter is obtained compared with the case in which the resistance value is varied by ±5Ω. In other words, it can be understood that, when the resistance value of the termination resistor Rterm is set to the resistance value obtained by the expression (3), jitter is reduced. 
     Hereinabove, the preferred embodiment of the present invention has been explained. However, the present invention is not limited to the above described embodiment, various modifications can be made within the range not departing from the gist of the present invention, and it goes without saying that they are also included in the range of the present invention. 
     For example, the above described embodiment has been explained by taking, as an example, the case in which the present invention is applied to a memory module; however, the application targets of the present invention are not limited thereto. Moreover, even if the present invention is applied to a memory module, the mounted memory devices are not limited to DRAMs.