Abstract:
A system and method are disclosed for measuring signal crosstalk in an electronic circuit device or Integrated Circuit (IC) device, correlating the results with modeled information, and accurately identifying one or more levels of coupling noise in the device. For example, a system is disclosed that provides data on levels of crosstalk between conductive lines in a device. The system uses programmable victim and aggressor lines, programmable drive capability, and programmable loading through one or more known crosstalk structures to compare an output signal with a reference signal and accurately identify one or more levels of coupling noise in the device.

Description:
GOVERNMENT LICENSE RIGHTS 
     The U.S. Government may have certain rights in the present invention as provided for by the terms of Contract No. DTRA01-02-D-0008 awarded by the Defense Threat Reduction Agency. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to the electronic circuit test field, and more particularly, but not exclusively, to a system and method for programmable signal integrity testing to identify levels of coupling noise in an electronic circuit such as, for example, a packaged electronic circuit device or semiconductor Integrated Circuit (IC) device. 
     2. Description of Related Art 
     In the design and manufacture of electronic circuit devices or IC devices including, for example, Application Specific IC (ASIC), Large-Scale IC (LSIC), or Very Large-Scale IC (VLSIC) devices, a significant problem encountered with such devices is that the input and output terminals of the logic circuit units (e.g., circuit cells, blocks, etc.) in the devices are interconnected with metallic wiring or other forms of conductive lines. Consequently, the very high integration and mounting densities required of the circuit cells, blocks and wiring in such devices create significant levels of signal crosstalk or coupling noise. Signal crosstalk and coupling noise are derived from signal interference in electronic circuit devices or IC devices, which is caused by the close proximities of the connecting wires or conductors throughout the device. Signal crosstalk and coupling noise have a major effect on the performance, signal integrity and reliability of the circuit devices involved. Also, signal crosstalk and coupling noise problems are exacerbated in high speed and very large-scale circuit devices. 
     Currently, levels of signal coupling between multiple layers of metal or other conductive materials in a circuit device can be difficult to quantify with any reasonable degree of accuracy. For example, no technique currently exists that can be used to measure signal crosstalk in a circuit device and correlate the results to estimated modeling information in order to identify levels of coupling noise in the device. Thus, it would be advantageous to have a system and method that can measure signal crosstalk in an electronic circuit device or IC device, correlate the results to modeled information, and accurately identify one or more levels of coupling noise in the device involved. As described in detail below, the present invention provides such a system and method. 
     SUMMARY OF THE INVENTION 
     The present invention provides a system and method for measuring signal crosstalk in an electronic circuit, electronic circuit device or IC device, correlating the results with reference information, and accurately identifying one or more levels of coupling noise in the device involved. In a preferred embodiment, a system is used to provide data on the level(s) of crosstalk between conductive lines in a device. Also, the system uses multiple programmable victim and aggressor lines, programmable drive capability, and programmable loading through one or more known crosstalk structures to compare an output signal with a reference signal and accurately identify one or more levels of coupling noise in the device. 
     For example, in an embodiment of the invention, an external reference signal is used to detect upsets or crosstalk in the circuit device involved. The external reference signal can be a steady state DC level or a switching signal. As such, using the programmability features of the present invention, numerous combinations of coupling can be measured at a time. For example, one or more lines in the device can be programmed to represent victim lines, while other lines in the device can be programmed to represent aggressor lines. An output signal of the system is compared to a known signal, or a DC offset voltage, to determine an exact level of upset or crosstalk that exists in the device. Alternatively, an AC clocking signal can be used to measure timing push-out or edge degradation in the device. Thus, the programmability features of the present invention enable testing of different noise coupling circuits in a device, and can provide both positive and negative responses to signal faults, as well as the levels at which the faults occurred. Also, the present invention can measure switching overshoot in the device, the level of the overshoot, and the length of time that the overshoot exceeded a predefined level. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
         FIG. 1  depicts a pictorial representation of a plurality of example electronic circuit layouts (or environments), each of which may be used to implement one or more embodiments of the present invention; 
         FIG. 2  depicts a schematic block diagram of an example signal integrity test system, which can be used to implement a preferred embodiment of the present invention; and 
         FIGS. 3A–3G  are related pictorial representations that depict a plurality of example circuit structures that can be used for signal integrity testing of electronic circuits or electronic circuit devices, in accordance with one or more embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     With reference now to the figures,  FIG. 1  depicts a pictorial representation of a plurality of example electronic circuit layouts (or environments)  100   a–   100   c , each of which may be used to implement one or more embodiments of the present invention. For example, electronic circuit layout  100   a  can represent a circuit board, which includes a plurality of electronic circuit devices  102   a ,  104   a  and  106   a . Each electronic circuit device  102   a ,  104   a  and  106   a  can be, for example, a packaged semiconductor device (e.g., including one or more chips) providing one or more logical functions. As shown, at least one terminal of each electronic circuit device  102   a ,  104   a  and  106   a  is connected via a conductive wire or line to at least one terminal of another electronic circuit device  102   a ,  104   a  and  106   a . Notably, at two areas or regions (e.g., indicated by the ellipses  108   a ,  110   a ) in electronic circuit layout  100   a , two interconnecting conductive wires or lines are arranged in close proximity to each other. Thus, at these proximal regions  108   a ,  110   a  in electronic circuit layout  100   a , significant levels of signal crosstalk and coupling noise can occur. Notably, although the example layout  100   a  shown in  FIG. 1  can represent a circuit board, it should be understood that the present invention can include any suitable circuit layout having interconnecting signal transmission lines or wires in proximity to each other, wherein signal crosstalk and/or coupling noise can occur. 
     As another example of an environment where the present invention may be implemented, electronic circuit layout  100   b  in  FIG. 1  can represent, for example, a packaged electronic device mounted on a semiconductor substrate (e.g., one or more of electronic circuit devices  102   a ,  104   a  and  106   a  in electronic circuit layout  100   a ). As shown, electronic circuit device layout  100   b  includes a plurality of component devices (e.g., flip-flops, gates, etc.)  102   b ,  104   b ,  106   b  and  108   b , which can perform certain logical functions in electronic circuit device layout  10   b . At least one terminal of each component device  102   b ,  104   b ,  106   b  and  108   b  is connected via a conductive wire or line to at least one terminal of another component device  102   b ,  104   b ,  106   b  and  109   b . Notably, at two regions (e.g., indicated by the ellipses  110   b ,  112   b ) in electronic circuit layout  100   b , two interconnecting conductive wires or lines are arranged in close proximity to each other. Thus, at these proximal regions  110   b ,  112   b  in electronic circuit layout  100   b , significant levels of signal crosstalk and coupling noise can occur. 
     Also, in electronic circuit layout  100   b , each component device  102   b ,  104   b ,  106   b  and  108   b  includes other electronic devices (e.g., transistors, resistors, capacitors, inductors) as subcomponents, which are internally interconnected with conductive wires or lines. Therefore, signal crosstalk and coupling noise can also occur in those regions where the subcomponents&#39; internal interconnecting wires or lines are arranged in close proximity to each other. 
     As yet another example of an environment where the present invention may be implemented, electronic circuit layout  100   c  in  FIG. 1  can represent, for example, an IC  102   c . IC  102   c  can be an ASIC, LSIC, VSLIC or any suitable type of semiconductor IC device in which significant levels of signal crosstalk and coupling noise can occur. For example, the integration densities and mounting densities of the cells, blocks or units arranged in IC  102   c  are typically maximized to minimize the size of IC  102   c . Consequently, the interconnecting wires or lines between the cells, blocks or units in IC  102   c  are arranged in very close proximity to one another. Furthermore, given the high integration and mounting densities desired, the polysilicon conductors within the cells, blocks or units in IC  102   c  are also arranged in very close proximity to one another. Therefore, significant levels of signal crosstalk and coupling noise can occur due to the very close proximal arrangement of these conductive wires or lines. 
       FIG. 2  depicts a schematic block diagram of an example signal integrity test system  200 , which can be used to implement a preferred embodiment of the present invention. Notably, signal integrity test system  200  can be located internally or externally with respect to an electronic circuit, electronic circuit device or IC device to be tested. As shown, for this example embodiment, system  200  includes a plurality of variable drive circuits  202 ,  203 ,  205 ,  207  and  209  coupled to selected resistive and capacitive components (described in detail below), which in combination, function to provide a modeled or customized crosstalk circuit or path (indicated generally as  236 ). 
     Specifically, for this illustrative example, system  200  includes a variable drive circuit  202  connected to one end of a resistor  204 . The second end of resistor  204  is connected to one end of a resistor  206 , and the second end of resistor  206  is connected to a programmable load  208  and a first input of a comparator circuit  226 . For this example embodiment, comparator circuit  226  can be an analog differential amplifier. 
     For test purposes in this example, variable drive circuit  202  has been selected to function as a drive circuit for a victim line formed by resistors  204  and  206 . Also, for this example, the victim line can be driven by a digital signal (e.g., via variable drive circuit  202 ), an external analog signal, or a DC voltage level (e.g., through a transmission gate). Thus, for example, the victim line can be driven by a switching signal or a steady state DC level. Programmable load  208  provides a source for current flow through the victim line. Notably, by use of the variable drive circuit  202  and programmable load  208 , the victim line (e.g., composed of resistors  204 ,  206 ) is essentially passed through a customized crosstalk circuit or path ( 236 ) to comparator circuit  226 . 
     A programmable reference circuit  228  is connected to a second input of comparator circuit  226 , and an output of comparator circuit  226  is connected to the clock input of a (e.g., fault storage) flip-flop  230  and an output connection (e.g., raw output)  234  of system  200 . The programmable reference circuit  228  can provide, for example, crosstalk data based on one or more simulation models representing known victim and aggressor line structures. As such, the output of programmable reference circuit  228  can be set based on what is to be measured, and the type of signal at the input to the victim line. 
     The inverted Q output and D input of flip-flop  230  are connected together, and the Q output of flip-flop  230  is connected to a second output connection (e.g., captured output)  232  of system  200 . Thus, flip-flop  230  can toggle (e.g., to divide by 2) with each input signal received from the output of comparator circuit  226 . 
     For this embodiment, system  200  also includes a second variable drive circuit  203  connected to one end of a resistor  210 . The second end of resistor  210  is connected to one end of a resistor  212  and one end of a capacitor  216 . The second end of resistor  212  is connected to a programmable load  214 . The second end of capacitor  216  is connected to the junction between resistor  204  and resistor  206 . 
     For test purposes in this example, variable drive circuit  203  has been selected to function as a drive circuit for an aggressor line formed by resistors  210  and  212 . Also, for this example, similar to the victim line, this aggressor line can be driven by a digital signal (e.g., via variable drive circuit  203 ), an external analog signal, or a DC voltage level (e.g., through a transmission gate). Thus, this aggressor line can be driven by the same type of switching signal or steady state DC level that drives the victim line. Alternatively, this aggressor line can be allowed to float. Programmable load  214  provides a source for current flow through this aggressor line. Notably, by use of the variable drive circuit  203  and programmable load  214 , this aggressor line (e.g., composed of resistors  210 ,  212 ) is also passed through the customized crosstalk circuit or path  236 . In this example, capacitor  216  couples this aggressor line to the selected victim line. 
     System  200  also includes a variable drive circuit  207  connected to one end of a resistor  218 . The second end of resistor  218  is connected to one end of a resistor  220  and one end of a capacitor  224 . The second end of resistor  220  is connected to a programmable load  222 . The second end of capacitor  224  is connected to the junction between resistor  204  and resistor  206 . For test purposes in this embodiment, resistors  218  and  220  form a second aggressor line. Also, for this example, this aggressor line can be allowed to float or it can be driven by the same signal as the victim line (e.g., via variable drive circuit  207 , external analog signal, or DC voltage level). Programmable load  222  provides a source for current flow through this aggressor line. Notably, by use of the variable drive circuit  207  and programmable load  222 , this aggressor line (e.g., composed of resistors  218 ,  220 ) is also passed through the customized crosstalk circuit or path  236 . In this example, capacitor  224  couples this aggressor line to the selected victim line. 
     System  200  also includes a variable drive circuit  205  connected to one end of a resistor  213 . The second end of resistor  213  is connected to one end of a resistor  215  and one end of a capacitor  217 . The second end of resistor  215  is connected to a programmable load  223 . The second end of capacitor  217  is connected to the junction between resistor  210  and resistor  212 . For test purposes in this embodiment, resistors  213  and  215  form a third aggressor line. Also, for this example, this aggressor line can be allowed to float or it can be driven by the same signal as the victim line (e.g., via variable drive circuit  205 , external analog signal, or DC voltage level). Programmable load  223  provides a source for current flow through this aggressor line. Notably, by use of the variable drive circuit  205  and programmable load  223 , this aggressor line (e.g., composed of resistors  213 ,  215 ) is also passed through the customized crosstalk circuit or path  236 . In this example, capacitor  217  couples this aggressor line to the selected victim line (e.g., via capacitor  216 ). 
     Additionally, for this illustrative embodiment, system  200  includes a variable drive circuit  209  connected to one end of a resistor  217 . The second end of resistor  217  is connected to one end of a resistor  219  and one end of a capacitor  221 . The second end of resistor  219  is connected to a programmable load  225 . The second end of capacitor  221  is connected to the junction between resistor  218  and resistor  220 . For test purposes in this embodiment, resistors  217  and  219  form a fourth aggressor line. Also, for this example, this aggressor line can be allowed to float or it can be driven by the same signal as the victim line (e.g., via variable drive circuit  209 , external analog signal, or DC voltage level). Programmable load  225  provides a source for current flow through this aggressor line. Notably, by use of the variable drive circuit  209  and programmable load  225 , this aggressor line (e.g., composed of resistors  217 ,  219 ) is also passed through the customized crosstalk circuit or path  236 . In this example, capacitor  221  couples this aggressor line to the selected victim line (e.g., via capacitor  224 ). 
     At this point, it is important to stress that the example embodiment shown for system  200  in  FIG. 2  of a single victim line and four aggressor lines is provided for illustrative purposes only, and the present invention is not intended to be so limited. For example, if multiple victim lines are arranged in the same path block, one or more of these victim lines can be switched to function as aggressor lines for other selected victim lines. As such, the aggressor lines can be driven in any of a number of arrangements, and with any one aggressor line to all of the aggressor lines switching, for example, to try to cause a given level of upset due to line crosstalk with the selected victim line. Also, system  200  can include any suitable number of resistive, capacitive and/or inductive circuit components that form a signal crosstalk combination for one or more victim lines and one or more aggressor lines (e.g., represented as an array of 30 metal lines arranged as 6 lines deep by 5 lines wide). For example, the embodiment illustrated by system  200  can be represented with an m by n array, with m=1 and n=2 for the arrangement shown. A plurality of example metal wire structures that can be used for victim and aggressor lines in system  200  are illustrated in  FIGS. 3A–3G . 
       FIGS. 3A–3G  are related pictorial representations that depict a plurality of example circuit structures that can be used for signal integrity testing of electronic circuits or electronic circuit devices, in accordance with one or more embodiments of the present invention. For example, the circuit structures depicted in  FIGS. 3A–3G  can represent metal lines arranged in parallel and/or orthogonally in electronic circuit devices such as, for example, packaged electronic circuit devices, ASICs, LSICs or VLSICs. As such, these example structures represent predefined wiring circuits that can be used to test for signal crosstalk and coupling noise in electronic circuit devices through parallel, orthogonal and fill metal coupling. 
     Specifically,  FIG. 3A  depicts an example signal integrity test circuit structure  300   a  for signal crosstalk and noise coupling testing, which includes a parallel arrangement of five metal lines (horizontally) stacked in parallel six layers high (vertically). This example circuit can represent a predetermined arrangement of metal wires or lines within different layers in an electronic circuit device (e.g., VSLIC). For example, with respect to system  200  in  FIG. 2 , the lighter shaded lines (e.g., line  302   a ) in  FIG. 3A  can represent selectable victim or aggressor lines, and the darker shaded lines (e.g., lines  304   a ,  306   a ) can represent aggressor only lines. 
       FIG. 3B  depicts a second example signal integrity test circuit structure  300   b  for signal crosstalk and noise coupling testing, which includes a parallel arrangement of five metal lines (horizontally) staggered six layers high (vertically). For example, with respect to system  200  in  FIG. 2 , the lighter shaded lines (e.g., line  302   b ) in  FIG. 3B  can represent selectable victim or aggressor lines, and the darker shaded lines (e.g., lines  304   b  and  306   b ) can represent aggressor only lines. 
       FIG. 3C  depicts a third example signal integrity test circuit structure  300   c  for signal crosstalk and noise coupling testing, which includes a parallel arrangement of five metal lines (horizontally) on three alternating layers (vertically) with a predetermined fill metal inserted between layers. For example, with respect to system  200  in  FIG. 2 , the lighter shaded lines (e.g., line  302   c ) in  FIG. 3C  can represent selectable victim or aggressor lines, and the darker shaded lines (e.g., lines  304   c  and  306   c ) can represent aggressor only lines. 
       FIG. 3D  depicts a fourth example signal integrity test circuit structure  300   d  for signal crosstalk and noise coupling testing, which includes a second parallel arrangement of five metal lines (horizontally) on three alternating layers (vertically) with a predetermined fill metal between layers. For example, the three layers shown in  FIG. 3D  can be interleaved with the three layers shown in  FIG. 3C  to define six layers for one test circuit. In any event, with respect to system  200  in  FIG. 2 , the lighter shaded lines (e.g., line  302   d ) in  FIG. 3D  can represent selectable victim or aggressor lines, and the darker shaded lines (e.g., lines  304   d  and  306   d ) can represent aggressor only lines. 
       FIG. 3E  depicts a fifth example signal integrity test circuit structure  300   e  for signal crosstalk and noise coupling testing, which includes two groupings of parallel arrangements of five metal lines (horizontally) on alternating layers (vertically) with floating wire lines between layers. For example, with respect to system  200  in  FIG. 2 , lines  302   e ,  312   e  in  FIG. 3E  can represent selectable victim or aggressor lines, and lines  304   e ,  314   e  and  306   e ,  316   e  (and all of the horizontally arranged lines) can represent aggressor only lines. 
       FIG. 3F  depicts a sixth example signal integrity test circuit structure  300   f  for signal crosstalk and noise coupling testing, which includes three groupings of parallel arrangements of five metal lines (horizontally) on three alternating layers (vertically). For example, with respect to system  200  in  FIG. 2 , the lighter shaded lines (e.g., lines  302   f ,  312   f ,  322   f  in  FIG. 3F  can represent selectable victim or aggressor lines, and the darker shaded lines (e.g., lines  304   f ,  306   f ,  314   f ,  316   f ,  324   f ,  326   f ) can represent aggressor only lines. 
       FIG. 3G  depicts a seventh example signal integrity test circuit structure  300   g  for signal crosstalk and noise coupling testing, which includes parallel, stair-stepping arrangements of two groupings of five metal lines overlapping in alternating directions. For example, with respect to system  200  in  FIG. 2 , the lines denoted as  302   g  in  FIG. 3G  can represent victim lines, and the other lines in  FIG. 3G  can represent aggressor lines. 
     Returning now to an operation of system  200  in  FIG. 2 , for this example embodiment, a signal (e.g., from variable drive circuit  202 ) is applied to the victim line (e.g., resistors  204 ,  206 ) and a predetermined load (e.g., programmable load  208 ). For example, the drive signal can be a switching signal (digital or analog signal), or steady state DC level. The drive signal can be set at a predetermined strength (e.g., high level, low level, or any level in between) to determine, for example, high levels of coupling noise or low levels of coupling noise. The programmable load  208  can be adjusted to dampen the drive signal applied, if desired. A DC offset drive signal can be applied to the victim line in system  200  for determining an exact level of upset or crosstalk between the victim line and one or more aggressor lines. Alternatively, a switching signal (e.g., digital signal or analog AC signal) can be applied to the victim line in system  200  to measure timing push-out or edge degradation for a signal in the victim line, as a result of the coupling noise from the one or more aggressor lines involved. 
     For this example embodiment, four aggressor lines have been selected and associated with the selected victim line. Each aggressor line can be driven by its respective variable drive circuit (e.g.,  203 ,  205 ,  207 ,  209 ). Thus, each aggressor line involved can be driven by a signal or level similar to the signal or level that is driving the victim line. Each programmable load connected to an aggressor line (e.g.,  214 ,  222 ,  223 ,  225 ) can be adjusted to a desired level and used, if desired, to dampen the drive signal in the respective line. As shown in  FIG. 2 , the resulting signal in the victim line (e.g., at the junction between resistor  206  and programmable load  208 ) is applied to an input of comparator circuit  226 . This signal applied at the input of comparator  226  is the resultant signal in the victim line, which is influenced by the signal crosstalk between the victim line and the one or more proximal aggressor lines involved (e.g., up to four aggressor lines in this example). Thus, in accordance with the present invention, data on the level(s) of signal crosstalk through or between the victim and aggressor lines can be provided. 
     Also, for this example, a predetermined reference signal from programmable reference  228  (e.g., data based on a simulation model of a known victim and aggressor line structure) is applied to the second input of comparator circuit  226 . This reference signal can represent, for example, a standard, predefined level of signal crosstalk for the particular victim and aggressor line structures involved. Consequently, the output of comparator circuit  226  provides a signal level representing a difference (e.g., positive or negative error) between the measured and predefined signal crosstalk signal information applied to the respective inputs of comparator circuit  226 . The difference signal from comparator circuit  226  is output directly by system  200  (e.g., raw output  234 ), and also applied to the clock input of flip-flop  230 . In response to a difference signal (e.g., positive or negative fault or error) received from comparator circuit  226 , flip-flop  230  toggles, and provides that result as an output (e.g., captured output) from system  200 . Thus, in accordance with the present invention, system  200  uses the data on the level(s) of crosstalk between the victim and aggressor lines, compares that data to predetermined reference data (e.g., based on a known victim/aggressor line structure), and uses the result of that comparison to identify levels of coupling noise in the victim and aggressor lines involved. 
     It is important to note that while the present invention has been described in the context of a fully functioning signal integrity test system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies equally regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable media include recordable-type media, such as a floppy disk, a hard disk drive, a RAM, CD-ROMs, DVD-ROMs, and transmission-type media, such as digital and analog communications links, wired or wireless communications links using transmission forms, such as, for example, radio frequency and light wave transmissions. The computer readable media may take the form of coded formats that are decoded for actual use in a particular signal integrity test system. 
     The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.