Abstract:
A memory module is formed on an integrated circuit by arranging memory cells in columns, and routing signal wires from module pins at an edge of the module to respective memory cells. The module pins are optimally positioned relative to the memory cells, and routing wires extend from the pins along routing lines to the cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.

Description:
FIELD OF THE INVENTION  
         [0001]    This invention relates to placement of memory matrices in integrated circuits, and particularly to wire routing and buffer placement for memory matrices in integrated circuits.  
         BACKGROUND OF THE INVENTION  
         [0002]    An integrated circuit chip (herein referred to as an “IC” or “chip”) comprises cells and connections between cells supported by a substrate. A cell is a group of one or more circuit elements, such as transistors, capacitors, memories and other basic circuit elements, grouped to perform a function. Each cell may have one or more pins, which in turn may be connected to one or more pins of other cells by wires. A net comprises circuitry coupling an input pin to one or more output pins. A typical IC includes a large number of cells and requires complex wire connections between the cells. A typical chip has thousands, tens of thousands and even hundreds of thousands of pins which are connected in various combinations.  
           [0003]    ICs include multiple layers of metal, semiconductor and insulator material, each configured so that it cooperates with other layers to define circuit elements, such as buffers, memory devices, gates and routing wires. The metal layers define routing wires for connecting together various elements, including memory matrices. Usually certain metal layers, such as even-numbered metal layers, are dedicated to horizontal routing wires, and other metal layers, such as odd-numbered metal layers, are dedicated to vertical routing wires. At least one insulator layer between adjacent metal layers insulates the metal layers from each other, and metal posts or channels between horizontal and vertical routing wires provide connection between them so signals and power can propagate through the IC.  
           [0004]    One problem in designing ICs with memory matrices is that the memory usually must be a “standard” size, fitting standard parameters. Consequently, it has not been practical to employ a large number of memory matrices on ICs, nor to fabricate ICs with large non-standard memories.  
         SUMMARY OF THE INVENTION  
         [0005]    The present invention is directed to a technique for placement of plural memory cells, including any necessary buffers, on ICs. The technique is useful in ICs with large percentages of memories to design compact layouts of groups of heterogeneous memories, as well as to ICs that require large memories with a non-standard parameters using smaller standard memory elements.  
           [0006]    The invention includes pin placement, signal routing, power routing and repeater buffer insertion, to complete a memory module layout.  
           [0007]    In accordance with an embodiment of the invention, a memory module is formed on an integrated circuit from a plurality of memory cells. The memory cells are arranged in columns, and signal wires are routed from module pins at an edge of the module to respective memory cells. Buffer channels are defined between memory cells and orthogonal to the columns, and buffers are selectively inserted into the routing wires in the buffer channels.  
           [0008]    In preferred embodiments, the signal wires are routed by positioning module pins along the edge of the module at optimal coordinates to the respective memory cells. First signal wires are routed along respective routing lines from the respective module pins to positions adjacent respective farthest memory cells to be coupled to the module pin. Second signal wires are routed in local routing regions for each memory cell from the respective memory cell to the respective first signal wire.  
           [0009]    The buffers are selectively inserted by placing a plurality of buffers in each buffer channel. Signal wires to be buffered at a buffer channel are identified, and the signal wires are routed through each buffer channel so that (i) a signal wire to be buffered is re-routed to an input and output of a buffer, and (ii) all other signal wires are routed along their respective routing lines.  
           [0010]    In some embodiments, power wires are routed between columns and between memory cells and are coupled to the memory cells and buffers. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    [0011]FIG. 1 is a flowchart of a process of laying out memory matrices in accordance with an embodiment of the present invention.  
         [0012]    FIGS.  2 - 9  illustrate application of the process to laying out a memory matrix in an IC. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0013]    [0013]FIG. 1 is a flowchart illustrating a process according to one embodiment of the invention. The process is preferably carried out in a computer processor using a computer program containing program code that enables the processor to perform the steps of the process. The process commences at step  100  with the input of a definition of a module consisting of memory macro cells, such as module  10  containing cells  12 ,  14 ,  16 ,  18 ,  20 ,  22  and  24  arranged in non-overlapping columns  26 ,  28  and  30 , shown in FIG. 2. At step  102 , the memory cells in each column are ordered in the vertical direction and assigned approximate vertical coordinates so that adjacent memories do not overlap. The memory cells  12 - 24  are arranged so that cells within a column can share signals, but only within a column  26 ,  28  or  30 . The memory cells are positioned so that signal pins are along the top and/or bottom of the module.  
         [0014]    At step  104  a power ring  32  is created, comprising vertical power wires  34 ,  36 ,  38  and  40  and horizontal power wires  42  and  44 , shown in FIG. 3. For example, vertical wires  34 ,  36 ,  38  and  40  may be routed on the fifth metal layer of the IC, and horizontal wires may be on the fourth metal layer. The horizontal and vertical power wires are coupled together at power posts or columns  46 . At step  106 , each memory  10  is connected to this structure. Memory power routing depends on the type of the memory and its power pin distribution. A typical situation is illustrated in FIG. 4 where the memory power pins  48  are coupled by vertical wires  50  to horizontal wires  42  or  44  of the power ring structure. Typically, the memory module  10  is also coupled to a ground plane (not shown) through other power pins to complete the power connection.  
         [0015]    At step  108 , module pins are assigned and placed along the bottom (and/or top) of memory module  10 . Since no signal sharing is permitted between memory cells in different columns, pin assignment process is carried out on each column separately. The ideal location for a column pin is defined as the average horizontal coordinate of all memory cell pins connected to the column pin. For example, if three memory cell pins having respective horizontal coordinates of x=1.3, 1.5 and 1.6 are to be connected to a given column pin for the module, the ideal horizontal coordinate for the column pin will be x=1.5. To resolve pin position conflict, such as if two or more pins have the same ideal horizontal (x) coordinate, each pin is assigned a coordinate such that:  
         [0016]    no two pins are assigned the same coordinate,  
         [0017]    the distance between ideal and assigned pin coordinate is minimized, and  
         [0018]    no pin coordinate intersects a power line.  
         [0019]    One useful technique for assigning pin coordinates is described in U.S. application Ser. No. 09/833,143 filed Apr. 11, 2001 for “Process for Solving Assignment Problems in Integrated Circuit Designs with Unimodal Object Penalty Functions and Linearly Ordered Set of Boxes” by Andreev et al., and assigned to the same assignee as the present invention, the disclosure of which is herein incorporated by reference.  
         [0020]    Next, each column pin is connected to one or more memory pins in that column. Routing consists of two parts. At step  110 , a vertical routing wire, such on the fifth metal layer, is extended along respective routing lines that extend from the respective column pin to the last or farthest memory cell of the column that needs to be connected to the pin. For example, if the column pin is at the bottom of the module, the vertical routing wire extends upward to the highest memory cell in the column requiring connection to that column pin.  
         [0021]    At step  112 , a horizontal pin channel is defined adjacent each memory cell to connect memory input/output pins to the respective vertical wire from the column pin. The pin channel is routed on three layers, such as metal layers  1 ,  2  and  3 , using a simple greedy procedure. In this step, the memory cell pins are processed one by one, with each pin being assigned a horizontal wire on the first available grid line from the top of the pin channel, taking into account wires that have already been placed, as well as applicable design rules related to adjacent via placement. The horizontal wire is coupled to the vertical routing wire established at step  110  using a metal post, and a vertical wire is established, such as on metal layer  2 , to couple the horizontal wire to the memory cell pin.  
         [0022]    An example of a net routing performed through steps  110  and  112  is illustrated in FIG. 5. In FIG. 5, each memory cell  12  and  14  has respective a vertical signal line  60  and  62 , such as on the first or third metal layer of the IC. A vertical routing wire  64  is routed from the module pins through the IC core, such as on the fifth metal layer of the IC, in the manner described in connection with step  110 . Horizontal routing wires  66  and  68  are routed along local routing or pin channels  70  and  72 , such as in the second metal layer of the IC, and the conductive posts or channels are formed at points  74  between horizontal wire  66  and lines  60  and  64  and between horizontal wire  68  and lines  60  and  64 .  
         [0023]    Next, the repeater buffers are inserted into the memory matrix. Repeater buffers, such as buffers  82  or  82   a  illustrated in FIG. 7, are placed in horizontal channels between memories cells, and are used to break long vertical wires from column pins. At step  114 , wherever a vertical wire crosses a channel between two memory cells, a decision is made whether or not to insert a buffer. The decision is based on design rules, primarily based on the position of the previous buffer on the vertical wire and the maximum distance that a buffer can drive The vertical wire is considered from the module pin toward the highest memory cell on the vertical wire. Thus, all vertical wires crossing a buffer channel can be considered in two groups: those that need to be buffered and those that pass through the buffer channel without buffering. At step  116 , vertical wires that require buffering are broken at the buffer channel and diverted to other metal layers. Buffers  82  and  82   a  are inserted and coupled to the broken vertical wires to buffer signals on those wires. Wires that do not need to be buffered continue through the buffer channel along their original routing lines. Thus, FIG. 6 illustrates wires  1 - 7  passing through buffer channel  80  between two memory cells  12  and  14  in a channel  26  (see FIG. 2). Wires  2 ,  3  and  5  are broken, as shown in dotted lines in FIG. 6, for connection to a buffer in the buffer channel, and wires  1 ,  4 ,  6  and  7  pass through the buffer channel.  
         [0024]    [0024]FIG. 7 illustrates buffers  82  and  82   a  of the same design, buffer  82  buffers signals from the memory cells and buffer  82   a  buffers signals to the memory cells. Each buffer  82 , 82   a  is locally routed to vertically align the wires  84  coupled to the input and output pins. In the example where the module pins are at the bottom of the module, the vertical wire  84  at the bottom of the buffer will be coupled to the output pin of buffer  82  or the input pin of buffer  82   a.    
         [0025]    As shown in FIG. 8, buffer channel  80  contains horizontal rows  86  and  88  for buffers  82 , 82   a . The number of rows required for a buffer channel is determined upon the number of wires that need to be buffered and the buffer size. Typically, the number of rows is between 1 and 3. Vertical wires are first assigned to buffer rows uniformly. Following that, all wires assigned to one row are assigned to specific buffers from that row. The process described in the aforementioned Andreev et al. application is appropriate for this wire assignment. The vertical wires are connected to their respective buffers using the same greedy method used to route pin channels described earlier.  
         [0026]    [0026]FIG. 8 illustrates an example of a buffer channel routing with two rows of buffers. Wires  1 ,  3 , and  5  are assigned to the first row  86  and wires  2 ,  4 , and  6  are assigned to the second row  88 . In row  86 , wires  1 ,  3 , and  5  are connected to their corresponding buffers  82  and  82   a  using the first and third metal routing layers for horizontal routing wires  90  and the second metal routing layer for vertical routing wires  92 . Wires  2 ,  4 , and  6  pass through row  86  on the fifth metal layer. Similarly, in row  88 , wires  2 ,  4 , and  6  are connected to their corresponding buffers  82  and  82   a  using the first and third metal routing layers for horizontal routing wires  90  and the second metal routing layer for vertical routing wires  92 . Wires  1 ,  3 , and  5  pass through row  88  on the fifth metal layer. Due to the symmetry of the buffers, connections on the two sides of the buffer are symmetrical. A vertical power rail is shown through each buffer channel  94  is illustrated in FIG. 8 for connection to buffers  82  and  82   a  using a standard approach.  
         [0027]    Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.