Abstract:
Image transformation is performed via a video display controlling device. Image data is transformed from an image storage memory having a matrix size of (N+a)×(M+b) onto a display screen sized to display an image according to N×M size matrix. The video display controlling device operates according to any one (or a combination of) several image transformation modes, including a normal mode, an expansion mode, a compression mode, and a moving image mode. These transformations are accomplished by first setting vertical and horizontal addresses of a reference pixel among pixel data stored in the storage memory, and setting an image mode for transforming an original image in a predetermine pattern. Addresses are then generated, in accordance with the set reference pixel and the set image mode, for selecting an N×M set of pixel data from among the (N+a)×(M+b) pixel data in the storage memory.

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a device for displaying a video signal, and more particularly, to a video display controlling device which enables an arbitrarily transformed image to be displayed on a monitor based upon a user&#39;s command. 
     This application regarding a video display controlling device is based upon Korean Patent Application No. 95-32198, filed Sep. 27, 1995, which is incorporated by reference herein for all purposes. 
     When a video signal is input to a video displaying device it is displayed on a monitor. In such a situation, a function of transforming the image upon a user&#39;s command and then displaying the transformed image is desirable. 
     SUMMARY OF THE INVENTION 
     Accordingly, it is an object of the present invention to provide a video display controlling device which can perform an image transformation, such as image compression or expansion, by manipulating a video signal to be displayed on a screen. 
     To accomplish the above object, there is provided a video display controlling device comprising a display means, a storing means, a reference pixel setting means, an image mode setting means, and an address generating means. The display means displays an image constituted by (N×M) pixel data on a screen. The storing means stores  (N+a)×(M+b)! pixel data associated with an image, where addresses for reading the pixel data are composed of vertical addresses from 0 to (N+a-1) and horizontal addresses from 0 to (M+b-1), and the reference letters a and b are positive integers. The reference pixel setting means sets vertical and horizontal addresses of a reference pixel data among pixel data stored in the storing means. The image mode setting means sets an image mode for transforming an original image according to a predetermined pattern and displaying the transformed image on the screen of the displaying means. The address generating means generates addresses for selecting a predetermined pixel data among the  (N+a)×(M+b)! pixel data, in accordance with the reference pixel data and the image mode. The pixel data read from the storing means at the vertical and horizontal addresses, which are generated by the address generating means, is displayed on the screen of the displaying means. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above object and advantage of the present invention will become more apparent as a preferred embodiment of thereof is described in detail with reference to the attached drawings in which: 
     FIG. 1 is a block diagram of a video display controlling device according to the present invention; 
     FIG. 2 shows an (N×M) pixel of a monitor and a  (N+a)×(M+b)! pixel stored in a memory, respectively; 
     FIG. 3 shows an image which can be displayed using the  (N+a)×(M+b)! pixel stored in the pixel memory; 
     FIGS. 4A &amp; 5A each show address settings in accordance with a normal image display mode; 
     FIGS. 4B &amp; 5B each show an image to be displayed in accordance with the normal mode address settings shown in FIGS. 4A &amp; 5A, respectively; 
     FIGS. 6A and 6B show, respectively, an address setting and an image to be displayed according to the address setting, according to a vertical compression mode; 
     FIGS. 7A and 7B show, respectively, an address setting and an image to be displayed according to the address setting, according to a horizontal compression mode; 
     FIGS. 8A &amp; 9A each show address settings according to a full compression mode; 
     FIGS. 8B &amp; 9B each show an image to be displayed in accordance with the full compression mode address settings of FIGS. 8A &amp; 9A, respectively; 
     FIGS. 10A &amp; 11A each show an address setting according to an expansion mode; 
     FIGS. 10B &amp; 11B each show an image to be displayed in accordance with the expansion mode address settings of FIGS. 10A &amp; 11A, respectively; and 
     FIG. 12 shows a progression of address settings according to a &#34;moving&#34; mode. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Referring to FIG. 1, the video display controlling device according to the present invention includes a monitor 18 which is a display device capable of displaying a video image composed of (N×M) pixel data. Pixel memory 17 stores  (N+a)×(M+b)! pixel data associated with an image, wherein an address for reading the pixel data is comprised of vertical addresses from 0 to (N+a-1) and horizontal addresses from 0 to (M+b-1) (here, the reference letters a and b are positive integers). The initial value setting unit 11 sets vertical and horizontal addresses of reference pixel data among pixel data stored in the pixel memory 17. An image mode setting unit 16 sets an image mode, such as a mode for compressing or expanding an original image and then displaying it. Vertical address generating unit 12 sequentially generates vertical addresses, for accessing the pixel memory 17, starting from the vertical address set by the initial value setting unit 11. Likewise, horizontal address generating unit 13 sequentially generates horizontal addresses, for accessing the pixel memory 17, starting from the horizontal address set by the initial value setting unit 11. An address selection controlling unit 15 generates a control signal for controlling the selection of a predetermined pixel data among the  (N+a)×(M+b)! pixel data in the pixel memory 17, depending on the address of the reference pixel data and the image mode. The address selecting unit 14 selects the vertical addresses generated by the vertical address generating unit 12 and the horizontal addresses generated by the horizontal address generating unit 13 (depending on the control signal form the address selection controlling unit 15) in sequence or in a predetermined interval unit, and then generates addresses for accessing the pixel memory 17. 
     The present invention is capable of operation according to the following image modes. In a normal mode, an original image is displayed without transformation. In a vertical compression mode the original image is compressed in a vertical direction before displaying it. In contrast, the horizontal compression mode compresses the original image in a horizontal direction before displaying it. The full compression mode compresses the original image in horizontal and vertical directions and displaying it, whereas the expansion mode expands a portion of the original image and displaying it. A moving mode is provided for displaying the original image with respect to an image stored in the pixel memory 17 as a plurality of images on the screen of the monitor 18. 
     FIG. 2 shows an (N×M) pixel matrix to be shown on the monitor 18, and a  (N+a)×(M+b)! pixel matrix stored in the pixel memory 17. Here, the variable &#34;N&#34; represents the amount of pixels capable of being vertically displayed on the monitor 18, and thus the term (N+a) represents an amount of pixels which exceeds the capacity of the monitor 18. Likewise, the term (M+b) represents an amount of pixels which exceeds the amount &#34;M&#34; capable of being horizontally displayed on the monitor 18. The drawings show a display of pixel data having addresses from (0, 0) to (N-1, M-1) in the pixel memory 17. 
     FIG. 3 shows a full image representing image data which can be displayed by using the  (N+a)×(M+b)! pixel data stored in the pixel memory 17. The pixel memory 17 stores more pixel data than will fit on the screen of the monitor 18. 
     Hereinbelow, address settings according to settings of an image mode and a reference pixel data, and an image to be displayed according to the address settings will be described referring to the drawings. 
     FIG. 4A shows an address setting for sequentially selecting the (N×M) pixel from the pixel memory 17 starting from address (0, 0). FIG. 4B shows the image displayed on the monitor 18 according to the address set shown in FIG. 4A. In this case, the image mode setting unit 16 sets the image mode as a normal mode. Accordingly, the initial value setting unit 11 sets the vertical and horizontal addresses of the reference pixel data to &#34;0&#34;. The address selecting unit 14 sequentially generates vertical addresses from &#34;0&#34; to (N-1) and horizontal addresses from &#34;0&#34; to (M-1). That is, the pixel data of the pixel memory 17, having addresses from (0, 0) to (N-1, M-1), is selected and displayed on the screen of the monitor 18. In FIG. 4B, the shaded portion denotes pixel data stored in the pixel memory 17 which is not displayed on the monitor 18. Hereinbelow, this explanation is applied in a similar manner to the following drawings. 
     FIG. 5A shows an address setting for sequentially selecting the (N×M) pixel data from the pixel memory 17, starting from an arbitrary position, and FIG. 5B shows an image displayed on the monitor 18 according to the address set shown in FIG. 5A. In this case, the image mode is set as a normal mode as in FIGS. 4A and 4B, but the vertical and horizontal addresses of the reference pixel data are set as K1 and K2 (here, K1 and K2 are integers larger than zero), respectively. Here, the address selecting unit 14 sequentially generates vertical addresses from K1 to (N-1+K1) and horizontal addresses from K2 to (M-1+K2). That is, the pixel data, having addresses from (K1, K2) to (N-1+K1, M-1+K2) in the pixel memory 17, are selected and displayed on the screen of the monitor 18. 
     FIG. 6A shows an address setting for producing a vertically compressed image, and FIG. 6B shows the image displayed on the monitor 18 according to the address set shown in FIG. 6A. Here, the image mode setting unit 16 sets the image as a vertical compression mode, and the initial value setting unit 11 sets both the vertical and horizontal addresses of the reference pixel data to &#34;0&#34;. The address selecting unit 14 sequentially generates horizontal addresses from &#34;0&#34; to (M-1) and vertical addresses starting from &#34;0&#34; and increasing by predetermined constant intervals. Here, the interval is set as 2. That is, when the pixel data of the pixel memory 17 is selected as described above, an original image is vertically compressed and displayed on the upper portion of the screen of the monitor 18. 
     FIG. 7A shows an address setting for producing a horizontally compressed image, and FIG. 7B shows the image displayed on the monitor 18 in accordance with the address set shown in FIG. 7A. Here, the image mode setting unit 16 sets the image as a horizontal compression mode, and the initial value setting unit 11 sets both the vertical and horizontal addresses of the reference pixel data to &#34;0&#34;. The address selecting unit 14 sequentially generates vertical addresses from &#34;0&#34; to (M-1) and vertical addresses starting from &#34;0&#34; and increasing by predetermined constant intervals. Here, the interval is set as 2. That is, when the pixel data of the pixel memory 17 is selected as described above, an original image is horizontally compressed and displayed on the left side of the screen of the monitor 18. 
     FIG. 8A shows an address setting for producing a fully compressed image, and FIG. 8B shows the image displayed on the monitor 18 according to the address set shown in FIG. 8A. In this case, the image mode setting unit 16 sets the image mode as a full compression mode. The initial value setting unit 11 sets both the vertical and horizontal addresses of the reference pixel data as &#34;0&#34; and the address selecting unit 14 generates vertical addresses starting from &#34;0&#34; and increasing by first predetermined constant intervals and horizontal addresses starting from &#34;0&#34; and increasing by second predetermined constant intervals. Here, the first and second constant intervals are both set as being 2. That is, when the pixel data of the pixel memory 17 is selected as described above, an original image is horizontally and vertically compressed and displayed on the upper-left-most portion of the screen of the monitor 18. 
     FIG. 9A shows an address setting for producing a fully compressed screen with respect to an arbitrarily selected portion of an image, and FIG. 9B shows the image displayed on the monitor 18 according to the address set shown in FIG. 9A. In this case, the image mode is set as a full compression mode as in FIGS. 8A and 8B. However, both the vertical and horizontal addresses of the reference pixel data are set as being 20. 
     FIG. 10A shows an address setting for producing an expanded image, and FIG. 10B shows the image displayed on the monitor 18 according to the address set shown in FIG. 10A. In this case, the image mode setting unit 16 sets the image mode as an expansion mode. The initial value setting unit 11 sets both the vertical and horizontal addresses of the reference pixel data as &#34;0&#34;, and the address selecting unit 14 sequentially selects both vertical and horizontal addresses starting from &#34;0&#34; and repeatedly generates the selected vertical addresses by a predetermined first repetition number and the selected horizontal addresses by a predetermined second repetition number. Here, the first and second repetition numbers (or repeating intervals) are both set as being 2, respectively. That is, when the pixel data of the pixel memory 17 is selected as described above, a partial original image is horizontally and vertically expanded and displayed on the screen of the monitor 18. 
     FIG. 11A shows an address setting for producing an expanded image of an arbitrarily selected image portion, and FIG. 11B shows the image displayed on the monitor 18 in accordance with the address set shown in FIG. 11A. In this case, the image mode is set as an expansion mode as in FIGS. 10A and 10B. However, both the vertical and horizontal addresses of the reference pixel data are set as being 20. 
     FIG. 12 shows an address setting for producing a moving image, wherein the upper row of illustration blocks each show an address setting for producing an image composed of (N×M) pixel data, and the lower row of illustration blocks each show which pixel data from the pixel memory 17 is accessed according to the address set shown directly above it. In this case, the image mode setting unit 16 sets the image mode as a moving mode. In the moving mode, pixel data corresponding to an original image stored in the pixel memory 17 is sequentially accessed and displayed so that the image on the screen of the monitor 18 moves by a predetermined interval of displacement upon incrementing the addresses. 
     According to the example of FIG. 12, the initial value setting unit 11 sets both the vertical and horizontal addresses of the reference pixel data to &#34;0&#34;, and the address selecting unit 14 sequentially generates vertical addresses from &#34;0&#34; to (N-1) and horizontal addresses from &#34;0&#34; to (M-1) (shown in the left-most upper block of FIG. 12). That is, pixel data having addresses from (0, 0) to (N-1, M-1) in the pixel memory 17 (as shown in the left-most lower block of FIG. 12), is selected and displayed on the screen of the monitor 18. Next, the initial value setting unit 11 increases the vertical and horizontal addresses of the reference pixel data by one and the address selecting unit 14 sequentially generates an address capable of selecting (N×M) pixel data from the increased reference address. That is, pixel data of the pixel memory 17, accessed by the following addresses, are sequentially displayed on the screen of the monitor 18. The following is an example of the sequential address matrices according to the incrementing method. 
     (0, 0)×(N-1, M-1); (1, 1)×(N, M); (2, 2)×(N+1, M+1); . . . ; (20, 20)×(N+19, M+19); . . . 
     The progression of block from left to right in FIG. 12 illustrates this concept. 
     As described above, the video display controlling device of the present invention stores more pixel data than that capable of being displayed by a monitor and generates an address for accessing the pixel data of the memory, depending on the image modes, thus easily realizing functions such as image compression or extension in a video display device. 
     Although the present invention has been described with respect to a preferred embodiment, it will be appreciated that various modifications and changes may be made to the described embodiment without departing from the spirit and scope of the invention.