Abstract:
A method and system for operating a pixel array having at least one pixel circuit is provided. The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period. The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 14/263,628, filed Apr. 28, 2014, now allowed, which is a continuation of U.S. patent application Ser. No. 13/909,177, filed Jun. 4, 2013, now U.S. Pat. No. 8,743,096, which is a continuation of U.S. patent application Ser. No. 11/736,751, filed Apr. 18, 2007, now U.S. Pat. No. 8,477,121, issued Jul. 2, 2013, which claims priority to Canadian Patent Application No. 2,544,090, filed Apr. 19, 2006; the entire contents of each of the foregoing are incorporated herein by reference in their respective entireties. 
    
    
     FIELD OF INVENTION 
     The present invention relates to light emitting device displays, and more specifically to a method and system for driving a pixel circuit. 
     BACKGROUND OF THE INVENTION 
     Electro-luminance displays have been developed for a wide variety of devices, such as cell phones. In particular, active-matrix organic light emitting diode (AMOLED) displays with amorphous silicon (a-Si), poly-silicon, organic, or other driving backplane have become more attractive due to advantages, such as feasible flexible displays, its low cost fabrication, high resolution, and a wide viewing angle. 
     An AMOLED display includes an array of rows and columns of pixels, each having an organic light emitting diode (OLED) and backplane electronics arranged in the array of rows and columns. Since the OLED is a current driven device, the pixel circuit of the AMOLED should be capable of providing an accurate and constant drive current. 
     However, the AMOLED displays exhibit non-uniformities in luminance on a pixel-to-pixel basis, as a result of pixel degradation, i.e., aging caused by operational use over time (e.g., threshold shift, OLED aging). Depending on the usage of the display, different pixels may have different amounts of the degradation. There may be an ever-increasing error between the required brightness of some pixels as specified by luminance data and the actual brightness of the pixels. The result is that the desired image will not show properly on the display. 
     Therefore, there is a need to provide a method and system that is capable of suppressing the aging of the pixel circuit. 
     SUMMARY OF THE INVENTION 
     It is an object of the invention to provide a method and system that obviates or mitigates at least one of the disadvantages of existing systems. 
     In accordance with an aspect of the present invention there is provided a method of operating a pixel array having at least one pixel circuit. The method includes the steps of: repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit; and relaxing a stress effect on the pixel circuit, prior to a next frame period. 
     In accordance with another aspect of the present invention there is provided a display system. The display system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The display system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period. 
     This summary of the invention does not necessarily describe all features of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features of the invention will become more apparent from the following description in which reference is made to the appended drawings wherein: 
         FIG. 1  is a timing chart for suppressing aging of a pixel circuit, in accordance with an embodiment of the present invention 
         FIG. 2  is a diagram illustrating an example of a pixel circuit to which the timing schedule of  FIG. 1  is suitably applied; 
         FIG. 3  is an exemplary timing chart for a compensating driving scheme in accordance with an embodiment of the present invention; 
         FIG. 4  is a diagram illustrating an example of a display system for implementing the timing schedule of  FIG. 1  and the compensating driving scheme of  FIG. 3 ; 
         FIG. 5  is a graph illustrating measurement results for a conventional driving scheme and the compensating driving scheme of  FIG. 3 ; 
         FIG. 6  is a timing chart illustrating an example of frames based on the timing schedule of  FIG. 1  and the compensating driving scheme of  FIG. 3 ; 
         FIG. 7  is a graph illustrating the measurement result of threshold voltage shift based on the compensating driving scheme of  FIG. 6 ; 
         FIG. 8  is a graph illustrating the measurement result of OLED current based on the compensating driving scheme of  FIG. 6 ; 
         FIG. 9  is a diagram illustrating an example of a driving scheme applied to a pixel array, in accordance with an embodiment of the present invention; 
         FIG. 10( a )  is a diagram illustrating an example of array structure having top emission pixels applicable to the display system of  FIG. 4 ; and 
         FIG. 10( b )  is a diagram illustrating an example of array structure having bottom emission pixels applicable to the display system of  FIG. 4 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention are described using a pixel circuit having an organic light emitting diode (OLED) and a plurality of thin film transistors (TFTs). The pixel circuit may contain a light emitting device other than the OLED. The transistors in the pixel circuit may be n-type transistors, p-type transistors or combinations thereof. The transistors in the pixel circuit may be fabricated using amorphous silicon, nano/micro crystalline silicon, poly silicon, organic semiconductors technologies (e.g., organic TFT), NMOS/PMOS technology, CMOS technology (e.g., MOSFET) or combinations thereof. A display having the pixel circuit may be a single color, multi-color or a fully color display, and may include one or more than one electroluminescence (EL) element (e.g., organic EL). The display may be an active matrix light emitting display (e.g., AMOLED). The display may be used in DVDs, personal digital assistants (PDAs), computer displays, or cellular phones. The display may be a flat panel. 
     In the description below, “pixel circuit” and “pixel” are used interchangeably. In the description below, “signal” and “line” may be used interchangeably. In the description below, the terms “line” and “node” may be used interchangeably. In the description below, the terms “select line” and “address line” may be used interchangeably. In the description below, “connect (or connected)” and “couple (or coupled)” may be used interchangeably, and may be used to indicate that two or more elements are directly or indirectly in physical or electrical contact with each other. 
       FIG. 1  illustrates a timing schedule for suppressing aging for a pixel circuit, in accordance with an embodiment of the present invention. The pixel circuit, which is operated using the timing schedule of  FIG. 1 , includes a plurality of transistors and an OLED (e.g.,  22 ,  24 ,  26  of  FIG. 2 ). In  FIG. 1 , a frame  10  is divided into three phases: a programming cycle  12 , a driving (i.e., emitting) cycle  14 , and a relaxing cycle  16 . The frame  10  is a time interval or period in which a display shows a frame of a video signal. During the programming cycle  12 , a pixel circuit is programmed with required data to provide the wanted brightness. During the driving cycle  14 , the OLED of the pixel circuit emits required brightness based on the programming data. Finally, during the relaxing cycle  16 , the pixel circuit is OFF or biased with reverse polarity of the driving cycle  14 . Consequently, the aging effect causes by the driving cycle  14  is annealed. This prevents aging accumulation effect from one frame to the other frame, and so the pixel life time increases significantly. 
     To obtain the wanted average brightness, the pixel circuit is programmed for a higher brightness since it is OFF for a fraction of frame time (i.e., relaxing cycle  16 ). The programming brightness based on wanted one is given by: 
                     L   CP     =       (       T   F         T   F     -     T   R         )     ⁢     L   N               (   1   )               
where “L CP ” is a compensating luminance, “L N ” is a normal luminance, “T R ” is a relaxation time ( 16  of  FIG. 1 ), and “T F ” is a frame time ( 10  of  FIG. 1 ).
 
     As described below, letting the pixel circuit relax for a fraction of each frame can control the aging of the pixel, which includes the aging of driving devices (i.e., TFTs  24  and  26  of  FIG. 2 ), the OLED (e.g.,  22  of  FIG. 1 ), or combinations thereof. 
       FIG. 2  illustrates an example of a pixel circuit to which the timing schedule of  FIG. 1  is applicable. The pixel circuit  20  of  FIG. 2  is a 2-TFT pixel circuit. The pixel circuit  20  includes an OLED  22 , a drive TFT  24 , a switch TFT  26 , and a storage capacitor  28 . Each of the TFTs  24  and  26  have a source terminal, a drain terminal and a gate terminal. In  FIG. 2 , C LD  represents OLED capacitance. The TFTs  24  and  26  are n-type TFTs. However, it would be appreciated by one of ordinary skill in the art that the driving schemed of  FIG. 1  is applicable to a complementary pixel circuit having p-type transistors or the combination of n-type and p-type transistors. 
     One terminal of the drive TFT  24  is connected to a power supply line VDD, and the other terminal of the drive TFT  24  is connected to one terminal of the OLED  22  (node B 1 ). One terminal of the switch TFT  26  is connected to a data line VDATA, and the other terminal of the switch TFT  26  is connected to the gate terminal of the drive TFT  24  (node A 1 ). The gate terminal of the switch TFT  26  is connected to a select line SEL. One terminal of the storage capacitor  28  is connected to node A 1 , and the other terminal of the storage capacitor  28  is connected to node B 1 . 
       FIG. 3  illustrates an exemplary time schedule for a compensating driving scheme in accordance with an embodiment of the present invention, which is applicable to the pixel of  FIG. 2 . In  FIG. 3 , “ 32 ” represents “V CP -Gen cycle”, “ 34 ” represents “V T -Gen cycle”, “ 36 ” represents “programming cycle” and associated with the programming cycle  12  of  FIG. 1 , and “ 38 ” represents “driving cycle” and associated with the driving cycle  14  of  FIG. 1 . 
     The waveforms of  FIG. 3  are used, for example, in the cycles  12  and  14  of  FIG. 1 . During the V CP -Gen cycle  32 , a voltage is developed across the gate-source voltage of a drive TFT (e.g.,  24  of  FIG. 2 ). During the V T -Gen cycle  34 , voltage at node B 1  becomes −V T  of the drive TFT (e.g.,  24  of  FIG. 2 ) where V T  is the threshold voltage of the drive TFT (e.g.,  24  of  FIG. 2 ). During the programming cycle  36 , node A 1  is charged to V P  which is related to Lcp of ( 1 ). 
     Referring to  FIGS. 2 and 3 , during the first operating cycle  32  (“V CP -Gen”), VDD changes to a negative voltage (−V CPB ) while VDATA has a positive voltage (V CPA ). Thus, node A 1  is charged to V CPA , and node B 1  is discharged to −V CPB . V CPA  is smaller than V TO +V OLEDO , where the V TO  is the threshold voltage of the unstressed drive TFT  24  and the V OLEDO  is the ON voltage of the unstressed OLED  22 . 
     During the second operating cycle  34  (“V T -Gen”), VDD changes to V dd2  that is a voltage during the driving cycle  38 . As a result, node B 1  is charged to the point at which the drive TFT  24  turns off. At this point, the voltage at node B 1  is (V CPA −V T ) where V T  is the threshold of the drive TFT  24 , and the voltage stored in the storage capacitor  28  is the V T  of the drive TFT  24 . 
     During the third operating cycle  36  (“programming cycle”), VDATA changes to a programming voltage, V CPA +V P . VDD goes to V dd1  which is a positive voltage. Assuming that the OLED capacitance (C LD ) is large, the voltage at node B 1  remains at V CPA −V T . Therefore, the gate-source voltage of the drive TFT  24  ideally becomes V P +V T . Consequently, the pixel current becomes independent of (ΔV T +ΔV OLED ) where ΔV T  is a shift of the threshold voltage of the drive TFT  24  and ΔV OLED  is a shift of the ON voltage of the OLED  22 . 
       FIG. 4  illustrates an example of a display system for implementing the timing schedule of  FIG. 1  and the compensating driving scheme of  FIG. 3 . The display system  1000  includes a pixel array  1002  having a plurality of pixels  1004 . The pixel  1004  corresponds to the pixel  20  of  FIG. 2 . However, the pixel  1004  may have structure different from that of the pixel  20 . The pixels  1004  are arranged in row and column. In  FIG. 4 , the pixels  1004  are arranged in two rows and two columns. The number of the pixels  1004  may vary in dependence upon the system design, and does not limited to four. The pixel array  1002  is an active matrix light emitting display, and may form an AMOLED display. 
     “SEL[i]” is an address line for the ith row (i= . . . k, k+1 . . . ) and corresponds to SEL of  FIG. 2 . “VDD[i]” is a power supply line for the ith row (i= . . . k, k+1 . . . ) and corresponds to VDD of  FIG. 2 . “VDATA[j]” is a data line for the jth row (i= . . . 1, 1+1 . . . ) and corresponds to VDATA of  FIG. 2 . 
     A gate driver  1006  drives SEL[i] and VDD[i]. The gate driver  1006  includes an address driver for providing address signals to SEL[i]. A data driver  1008  generates a programming data and drives VDATA[j]. The controller  1010  controls the drivers  1006  and  1008  to drive the pixels  1004  based on the timing schedule of  FIG. 1  and the compensating driving scheme of  FIG. 3 . 
       FIG. 5  illustrates lifetime results for a conventional driving scheme and the compensating driving scheme. Pixel circuits of  FIG. 2  are programmed for 2 μA at a frame rate of ˜60 Hz by using the conventional driving scheme ( 40 ) and the compensating driving scheme ( 42 ). The compensating driving scheme ( 42 ) is highly stable, reducing the total aging error to less than 10%. By contrast, in the conventional driving scheme ( 40 ), while the pixel current becomes half of its initial value after 36 hours, the aging effects result in a 50% error in the pixel current over the measurement period. The total shift in the OLED voltage and threshold voltage of the drive TFT (i.e.,  24  of  FIG. 2 ), Δ(V OLED +V T ), is ˜4 V. 
       FIG. 6  illustrates an example of frames using the timing schedule of  FIG. 1  and the compensating driving scheme of  FIG. 3 . 
     In  FIG. 6 , “i” represents the ith row in a pixel array, “k” represents the kth row in the pixel array, “m” represents the mth column in the pixel array, and “l” represents the lth column in the pixel array. The waveforms of  FIG. 6  are applicable to the display system  1000  of  FIG. 4  to operate the pixel array  1002  of  FIG. 4 . It is assumed that the pixel array includes more than one pixel circuit  20  of  FIG. 2 . 
     In  FIG. 6 , “ 50 ” represents a frame for the ith row and corresponds to “ 10 ” of  FIG. 1 , “ 52 ” represents “V CP -Gen cycle” and corresponds to “ 32 ” of  FIG. 3 , “ 54 ” represents “V T -Gen cycle” and corresponds to “ 34 ” of  FIG. 3 , and “ 56 ” represents “programming cycle” and corresponds to “ 36 ” of  FIG. 3 . In  FIG. 6 , “ 58 ” represents “driving cycle” and corresponds to “ 38 ” of  FIG. 3 . In  FIG. 6 , “ 66 ” represents the values of the corresponding VDATA lines during the operating cycle  56 . 
     In  FIG. 6 , “ 60 ” represents a relaxing cycle for the ith row and corresponds to “ 16 ” of  FIG. 1 . The relaxing cycle  60  includes a first operating cycle “ 62 ” and a second operating cycle “ 64 ”. During the relaxing cycle  60  for the ith row, SEL[i] is high at the first operating cycle  62  and then is low at the second operating cycle  64 . During the frame cycle  62 , node A 1  of each pixel at the ith row is charged to a certain voltage, such as, zero. Thus, the pixels are OFF during the frame cycle  64 . “V CP -Gen cycle”  52  for the kth row occurs at the same timing of the first operating cycle  62  for the ith row. 
     During the first operating cycle  52  for the kth row, which is the same as the first operating cycle  62  for the ith row, SEL[i] is high, and so the storage capacitors of the pixel circuits at the ith row are charged to V CPA . VDATA lines have V CPA . Considering that V CPA  is smaller than V OLEDO +V TO , the pixel circuits at the ith row are OFF at the second operating cycle  64  and also the corresponding drive TFTs ( 24  of  FIG. 2 ) are negatively biased resulting in partial annealing of the V T -shift at the cycle  64 . 
       FIGS. 7 and 8  illustrate results of a longer lifetime test for a pixel circuit employing the timing cycles of  FIG. 6 . To obtain data of  FIGS. 7 and 8 , a pixel array having more than one pixel  20  of  FIG. 2  was used. 
     In  FIG. 7 , “ 80 ” represents the measurement result of the shift in the threshold voltage of the drive transistor (i.e.,  24  of  FIG. 2 ). The result signifies that the above method and results in a highly stable pixel current even after 90 days of operation. Here, the pixel of  FIG. 2  is programmed for 2.5 μA to compensate for the luminance lost during the relaxing cycle. The Δ(V OLED +V T ) is extracted once after a long timing interval (few days) to not disturb pixel operation. It is clear that the OLED current is significantly stable after 1500 hours of operation which is the results of suppression in the aging of the drive TFT (i.e.,  24  of  FIG. 2 ) as shown in  FIG. 7 . 
     In  FIG. 8 , “ 90 ” represents the measurement result of OLED current of the pixel (i.e.,  20  of  FIG. 2 ) over time. The result depicted in  FIG. 8  confirms that the enhanced timing diagram suppresses aging significantly, resulting in longer lifetime. Here, Δ(V OLED +V T ) is 1.8 V after a 90 days of operation, whereas it is 3.6 V for the compensating driving scheme without the relaxing cycle after a shorter time. 
       FIG. 9  is a diagram illustrating an example of the driving scheme applied to a pixel array, in accordance with an embodiment of the present invention. In  FIG. 9 , each of ROW (i), ROW(k) and ROW (n) represents a row of the pixel array. The pixel array may be the pixel array  1002  of  FIG. 4 . The frame  100  of  FIG. 9  includes a programming cycle  102 , a driving cycle  104 , and a relaxing cycle  106 , and has a frame time “t F ”. The programming cycle  102 , the driving cycle  104 , and the relaxing cycle  106  may correspond to the operation cycles  12 ,  14 , and  16  of  FIG. 1 , respectively. The programming cycle  102  may include the operating cycles  32 ,  34  and  36  of  FIG. 3 . The relaxing cycle  106  may be similar to the relaxing cycle  60  of  FIG. 6 . 
     The programming cycle  102  for the kth row occurs at the same timing of the relaxing cycle  106  for the ith row. The programming cycle  102  for the nth row occurs at the same timing of the relaxing cycle  106  for the kth row. 
       FIG. 10( a )  illustrates an example of array structure having top emission pixels.  FIG. 10( b )  illustrates an example of array structure having bottom emission pixels. The pixel array of  FIG. 4  may have the array structure of  FIG. 10( a )  or  10 ( b ). In  FIG. 10( a ) ,  200  represents a substrate,  202  represents a pixel contact,  203  represents a (top emission) pixel circuit, and  204  represents a transparent top electrode on the OLEDs. In  FIG. 10( b ) ,  210  represents a transparent substrate,  211  represents a (bottom emission) pixel circuit, and  212  represents a top electrode. All of the pixel circuits including the TFTs, the storage capacitor, the SEL, VDATA, and VDD lines are fabricated together. After that, the OLEDs are fabricated for all pixel circuits. The OLED is connected to the corresponding driving transistor using a via (e.g., B 1  of  FIG. 2 ) as shown in  FIGS. 10( a ) and 10( b ) . The panel is finished by deposition of the top electrode on the OLEDs which can be a continuous layer, reducing the complexity of the design and can be used to turn the entire display ON/OFF or control the brightness. 
     In the above description, the pixel circuit  20  of  FIG. 2  is used as an example of a pixel circuit for implementing the timing schedule of  FIG. 1 , the compensating driving schedule of  FIG. 3 , and the timing schedule of  FIG. 6 . However, it is appreciated that the above timing schedules of  FIGS. 1, 3 and 6  are applicable to pixel circuits other than that of  FIG. 2 , despite its configuration and type. 
     Examples of the driving scheme, compensating and driving scheme, and pixel/pixel arrays are described in G. R. Chaji and A. Nathan, “Stable voltage-programmed pixel circuit for AMOLED displays,” IEEE J. of Display Technology, vol. 2, no. 4, pp. 347-358, December 2006, which is hereby incorporated by reference. 
     One or more currently preferred embodiments have been described by way of example. It will be apparent to persons skilled in the art that a number of variations and modifications can be made without departing from the scope of the invention as defined in the claims.