Abstract:
A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    None. 
       STATEMENT REGARDING FEDERALLY SPONSORED-RESEARCH OR DEVELOPMENT 
       [0002]    None. 
       INCORPORATION BY REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC 
       [0003]    None. 
       FIELD OF THE INVENTION 
       [0004]    The invention disclosed broadly relates to the field of integrated circuit fabrication, and more particularly relates to improving the reliability of high-k transistors using a replacement gate fabrication process. 
       BACKGROUND OF THE INVENTION 
       [0005]    In the semiconductor industry, Moore&#39;s law states that the number of transistors on a chip doubles approximately every two years. These exponential performance gains present a challenge to the semiconductor manufacturing industry, along with the dual challenges of promoting power savings and providing cooling efficiency. The industry addresses these challenges in multiple ways. Selecting the gate dielectric and gate electrode are critical choices in enabling device scaling, and compatibility with CMOS technology. Two main approaches have emerged in high-k and metal gate (HKMG) integration: gate-first and gate-last. Gate-last is also called replacement metal gate (RMG) where the gate electrode is deposited after S/D junctions are formed and the high-k gate dielectric is deposited at the beginning of the process (high-k first). 
         [0006]    A high-k first gate-last process is when the high-k dielectric is deposited first and the metal is deposited last (gate-last method). Gate-last is often referred to as the replacement gate option. “First” and “last”-gate denotes whether the metal gate electrode is deposited before or after the high temperature anneal process. Typically, reliability of high-k gate stacks improve as a result of dopant activation anneal at temperatures around 1000° C., which is built in for gate-first or high-k first gate-last processes. The high-k last gate-last (replacement gate) process, however, lacks such built-in high temperature treatment, and thus reliability is a big challenge. 
         [0007]    Referring now in specific detail to the drawings, and particularly to  FIGS. 1A and 1B , there is provided a simplified pictorial illustration of the gate fabrication process using a hydrogen (H2) anneal, according to the known art. Hydrogen gas is favored for its gate oxide reliability.  FIG. 1A  shows H2  150  annealed directly on a high-k layer  110 . The problems with this process are twofold: 1) the formation of oxygen vacancies in the high-k dielectric  110 ; and 2) an undesired Vt shift, causing gate leakage degradation. 
         [0008]    In  FIG. 1B  we provide a simplified illustration of another gate fabrication process using an H2 anneal  150  on a full structure with a replacement gate  130  in place, according to the known art. In this method, the supply of hydrogen is blocked by the metal layers. Moreover, the degree of interface passivation depends on the device size (large devices can be un-passivated). 
         [0009]    We provide a glossary of terms used throughout this disclosure: 
       GLOSSARY 
       [0000]    
       
         k—dielectric constant value 
         high-k—having a ‘k’ value higher than 3.9 k, the dielectric constant of silicon dioxide 
         CMOS—complementary metal-oxide semiconductor 
         FET—field effect transistor 
         FinFET—a fin-based, multigate FET 
         MOSFET—a metal-oxide semiconductor FET 
         CMP—chemical/mechanical polishing 
         Dit—interface states 
         RTA—rapid thermal anneal 
         HfO2—hafnium oxide 
         H2—hydrogen 
         D2—deuterium 
         A-Si—amorphous silicon 
         ALD—atomic layer deposition 
         PVD—physical vapor deposition 
         SiOx—silicon oxide 
         SiGe—silicon germanide 
         SiC—silicon carbide 
         RIE—reactive ion etching 
         ODL—optically dense layer; organically dielectric layer 
         STI—shallow trench isolation 
         S/D—source and drain terminals 
         NiSi—nickel silicide 
         C (DLC)—metal-free diamond-like carbon coating 
         SiN—silicon nitride 
         TDDB—time dependent dielectric breakdown 
         NBTI—negative bias temperature instability 
         PBTI—positive bias temperature instability 
         RTA—rapid thermal annealing 
         IL/HK—interfacial layer/high-k dielectric layer 
         TiN—titanium nitride 
         TiC—titanium carbide 
         TaN—tantalum nitride 
         TaC—tantalum carbide 
         TiAl—titanium aluminide 
         N2—nitrogen 
         Al—aluminide 
         W—tungsten 
         HfO2—Hafnium-based high-k dielectric 
       
     
       SUMMARY OF THE INVENTION 
       [0049]    Briefly, according to an embodiment of the invention a method of fabricating a gate stack for a semiconductor device includes the following steps performed after removal of a dummy gate. Providing a replacement gate structure includes: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer. 
         [0050]    According to another embodiment of the present invention a method of fabricating a gate stack for a semiconductor device includes the following steps performed after removal of a dummy gate. Providing a replacement gate structure includes: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; removing the thin metal layer after annealing; depositing a metal layer of low resistivity metal; and depositing a gap fill layer. 
         [0051]    According to an embodiment of the invention a method of fabricating a gate stack for a FinFET device includes the following steps performed after removal of a dummy gate. Providing a replacement gate structure includes: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer. 
     
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         [0052]    To describe the foregoing and other exemplary purposes, aspects, and advantages, we use the following detailed description of an exemplary embodiment of the invention with reference to the drawings, in which: 
           [0053]      FIGS. 1A and 1B  show schematics for conventional methods of H2 anneal on RMG devices; 
           [0054]      FIGS. 2A through 2F  show a gate structure undergoing the replacement gate process, according to an embodiment of the present invention; 
           [0055]      FIGS. 3A through 3D  show a gate structure undergoing the replacement gate process, according to another embodiment of the present invention; 
           [0056]      FIG. 4  is a flowchart of a method according to an embodiment of the invention; 
       
    
    
       [0057]    While the invention as claimed can be modified into alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention. 
       DETAILED DESCRIPTION 
       [0058]    Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Thus, it will be appreciated that for simplicity and clarity of illustration, common and well-understood elements that are useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of these various embodiments. 
         [0059]    We discuss a gate-last, high-k metal gate fabrication with a novel improvement in reliability. We achieve this reliability by incorporating hydrogen (H2) only in the thin metal and the high-k layer. Additionally, the H2 remains in the final film. We perform a passivation anneal with ambient H2 after the thin metal deposition. Our anneal process is performed at temperatures of 600 to 700 C on thin metal (TiN, TiC, TaN, TaC). The metal&#39;s thickness is between 10 and 50 angstroms. This fabrication method can be advantageously implemented in various CMOS devices, including FinFET devices. We use only an intermediate thermal treatment after dopant activation. This removes any dopant activation or S/D junction diffusion concerns. 
         [0060]    Referring now to  FIGS. 2A through 2F , we describe a gate-last, high-k metal gate.  FIG. 2A  we show the gate structure  200  after removal of the dummy (sacrificial) gate. We grow an interfacial layer and deposit a high-k dielectric  110 . In  FIG. 2B , we show the gate structure  200  after deposition of a gate metal layer  120 . The gate metal layer  120  in this embodiment is a thin metal layer with a thickness of approximately 10 to 50 angstroms. It is preferably a thermally stable metal alloy, such as TiN, TiC, TaN, or TaC. The gate metal layer  120  can be deposited via atomic layer deposition (ALD) or physical vapor deposition (PVD). After deposition of the thin metal layer  120 , we follow with an anneal in an ambient atmosphere containing H2 at 600-700 C. 
         [0061]    In  FIG. 2C  we show an optional step of removing the thin metal layer  120  after it has been annealed in H2  150 . After optionally removing the thin metal layer  120  we follow with deposition of a work function metal  140 . This is shown in  FIG. 2D . The work function metal  140  can be a metal alloy, such as TiAl or TiN. It serves the purpose of setting the threshold voltage of the device to appropriate values. In  FIG. 2E  we show the gate structure  200  after deposition of a gap fill metal  145  to finish the replacement gate  200 . The gap fill metal  145  can be Al, or W. Lastly, in  FIG. 2F  we show the gate structure  200  after performing chemical/mechanical polishing (CMP), a planarization process. 
         [0062]    Referring now to  FIGS. 3A through 3D  we describe another gate-last, high-k metal gate with a novel improvement in reliability. In  FIG. 3A , just as in  FIG. 2A , we show the gate structure  300  after removal of the dummy (sacrificial) gate. We grow an interfacial layer and deposit a high-k dielectric  110 . In  FIG. 3B , we show the gate structure  200  after deposition of a gate metal layer  120 . The gate metal layer  120  in this embodiment is a thin metal layer  120  with a thickness of approximately 10 to 50 angstroms. It is preferably a thermally stable metal alloy, such as TiN, TiC, TaN, or TaC. 
         [0063]    The gate metal layer  120  can be deposited via atomic layer deposition (ALD) or physical vapor deposition (PVD). After deposition of the thin metal layer  120 , we follow with an anneal in an ambient atmosphere containing H2 at 600°-700° C. The H2 anneal with the presence of the thin metal layer  120  enables a direct supply of active H species to the interface while suppressing reduction of HfO2. We show a reliability improvement without degradation in the effective work function and gate leakage current. 
         [0064]    In  FIG. 3C  we show the gate structure  300  after deposition of a gap fill metal  145  to finish the replacement gate  300 . The gap fill metal  145  can be Al, or W. Lastly, in  FIG. 3D  we show the gate structure  300  after performing chemical/mechanical polishing (CMP), a planarization process. 
         [0065]    We will now discuss the process steps for gate last high-k gate fabrication with respect to the flowcharts of  FIG. 4 . Optional steps are depicted in dotted boxes. It will be apparent to those with knowledge in the art that the fabrication of a gate stack on a semiconductor device involves more steps than are shown in  FIG. 4 . For example, we skip over the source/drain junction formation and show the process after the dummy gate has been removed. For clarity, we concentrate our explanation on those steps that deviate from the conventional fabrication of the high-k gate. 
         [0066]    Referring now to  FIG. 4 , we show a flowchart  400  of the process for fabricating a gate-last high-k metal gate according to the embodiment of  FIGS. 2A through 2F . In step  410  we grow an interfacial layer and deposit a high-k metal  110  after the dummy gate removal. In step  420  we deposit the gate metal layer  120 . This is followed by an H2 anneal at a range of 600° C. to 700° C. in step  430 . 
         [0067]    Next, we can optionally remove the thin metal layer  120  in step  440 . If we remove the metal  120  in step  440 , then in step  450  we deposit a work function setting metal. Next, we deposit a gap fill metal  140  of low resistivity in step  460  and finish with CMP planarization in step  470 . The benefits and advantages to this embodiment are: 
         [0068]    1. Enables a direct supply of active H species to the interface while suppressing reduction of HfO2. 
         [0069]    2. Reliability improvement without degradation in the effective work function and gate leakage current. 
         [0070]    Therefore, while there has been described what is presently considered to be the preferred embodiment, it will understood by those skilled in the art that other modifications can be made within the spirit of the invention. The above description(s) of embodiment(s) is not intended to be exhaustive or limiting in scope. The embodiment(s), as described, were chosen in order to explain the principles of the invention, show its practical application, and enable those with ordinary skill in the art to understand how to make and use the invention. It should be understood that the invention is not limited to the embodiment(s) described above, but rather should be interpreted within the full meaning and scope of the appended claims.