Abstract:
A dynamic threshold voltage p-channel MOSFET (PMOS) for ultra-low power ultra-low voltage applications is disclosed. These applications are of low-to-moderate performance requirements; hence ultra-low voltage subthreshold operation, where the supply voltage is less than the transistors threshold voltage, is suitable. By tying the PMOS body to the output node of the transistor circuit in which this PMOS is part of will provide the necessary body bias for this PMOS threshold voltage to change dynamically with the circuit&#39;s output status. The dynamic change of the PMOS transistor threshold voltage will consequently dynamically increase or decrease the subthreshold leakage current which is the switching current in subthreshold circuits.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     This invention relates generally to MOSFET devices and integrated circuits and particularly to MOSFET devices with adaptive body biases for operating- and off-conditions. More particularly, this invention relates to a method of generating the MOSFET device body bias which leads to low threshold operating voltage and high threshold voltages during off-conditions. The devices in the present invention exhibit low currents during off-conditions and high currents during on-conditions which makes them suitable for ultra-low operating voltage ultra-low power operations.  
         [0003]     2. Description of the Background Art  
         [0004]     The continuing growth of battery-operated devices market has increased the demand for low-energy VLSI design. Battery-operated low-to-moderate performance requirements applications (such as pacemakers, hearing aids, wrist watches, and calculators) have very strong demands on battery lifetime and consequently on power consumption.  
         [0005]     The main method of reducing power consumption is through reducing the power supply voltage (V DD ) since power consumption is proportional to the square of V DD . Reducing the supply voltage to below three times the threshold voltage of the transistor (3V TH ) Will greatly degrade circuits&#39; speed and performance and it is generally avoided in regular MOSFET operation.  
         [0006]     A suitable solution to reach the ultra-low power requirements of the said applications is through operating the circuit in the subthreshold region where V DD  is lowered to below V TH . The operating current in this case is the subthreshold leakage current (I sub ) since under these operating conditions there is no strong inversion channel and the device is operating in the weak inversion region. This subthreshold leakage current is orders of magnitude lower than the strong inversion current which leads to the desired ultra-low power consumption; however, it also leads to a much slower circuit. The subthreshold leakage current in an N-channel MOSFET is expressed as follows: 
 
 I   sub =μ.( W/L ). C   ox   .e   1.8   .V   t   2 .exp(( V   GS   −V   TH )/ n.V   t ).(1−exp(− V   DS   /V   t )).exp(η. V   DS   /n.V   t ) 
 
 Where μ is the carrier mobility, W is the MOSFET&#39;s width, L is its length, C ox  is the gate oxide capacitance, e is the electron charge, V GS  and V DS  are the gate to source and gate to drain voltages respectively, V t  is the thermal voltage, n is a subthreshold slope parameter and it depends on the bulk to source and drain to source voltages, and η is the Drain-Induced Barrier Lowering (DIBL) coefficient. 
 
         [0007]     The N-channel MOSFET&#39;s threshold voltage is expressed as follows: 
 
 V   TH   =V   TH0 +γ.(√(|2Φ F   |+V   SB )−√(|2Φ F |))−η. V   DS  
 
 Where V TH0  is the zero-bias threshold voltage and mainly depends on the manufacturing process; γ is the body effect coefficient (typically equals to 0.4V 0.5 ) and it depends on the gate oxide capacitance, silicon permittivity, doping level, and other parameters; Φ F  is the surface potential at threshold (typically |−2Φ F | equals 0.6V); V SB  is the source-to-body voltage; and the ηV DS  term represents the effect of Drain-Induced Barrier Lowering (DIBL). 
 
         [0008]     Due to their operation in the weak-inversion region, subthreshold CMOS circuits behave differently if compared to the strong inversion CMOS circuits; they become more sensitive to voltage supply variations, temperature variations, and process parameters variations.  
         [0009]     One technique well known in the prior art is the dynamic threshold-voltage MOSFET (DTMOS) for MOSFETs fabricated using the Silicon-On-Insulator Complementary Metal Oxide Semiconductor (SOI-CMOS) Technology, which was described in Assaderaghi, F. et al, “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI,”  IEEE Transaction on Electron Devices , volume 44, pages 414-421, 1997. Referring to  FIG. 1 , DTMOS  100 , applied to a N-channel MOSFET (NMOS), and includes a gate  101  tied to an input  102 , a drain  103 , a source  104 , and a body  105 .  
         [0010]     In the DTMOS technique, the transistor&#39;s threshold voltage can be changed dynamically by connecting the gate  101  to the body  105 . More particularly, the transistor threshold voltage will change dynamically as input  102  switches between high and low (V DD  and ground). When input  102  switches to the high state, transistor&#39;s threshold voltage will be lowered as a result of the input being connected to the transistor&#39;s body and enabling the transistor to be turned on at a lower input voltage. Consequently, the subthreshold leakage current (switching current) will be dynamically increased and, as a result, more driving current will be supplied to the drain  103  enhancing performance and lowering circuit&#39;s delay.  
         [0011]     If input  102  goes lower than the transistor&#39;s threshold voltage, thus switching off the transistor, the transistor&#39;s body  105  will also be low raising the transistor&#39;s threshold voltage, lowering the subthreshold leakage current, improving noise immunity, and saving power.  
         [0012]     The effective gate capacitance at the gate  101  of a DTMOS is larger than the gate capacitance of a regular MOSFET, but the higher driving current available when input  102  is high diminishes this problem and causes the DTMOS circuit to have less delay than the regular MOS circuits. DTMOS circuits are more robust against temperature and process parameter variations and have better noise immunity as compared to the conventional subthreshold CMOS circuits.  
         [0013]     DTMOS technique can be applied to P-channel MOSFET transistors fabricated in Bulk-CMOS technology since NMOS transistors in the said technology require extra fabrication steps to isolate them from neighboring transistors, while PMOS transistors in said technology do not require such extra fabrication steps. P-channel DTMOS technique was introduced by Elgebaly, M. and Sachdev, M. in “ A sub -0.5  V dynamic threshold PMOS  ( DTPMOS )  scheme for bulk CMOS technologies ,” The 13 th  International Conference on Microelectronics, pages 75-78, 2001.  
         [0014]      FIG. 2  shows a 3-input CMOS OR transistor circuit  200  constructed by connecting the output  214  of a 3-input CMOS NOR transistor circuit  200 - 1  to the input of a CMOS inverter  200 - 2 .  
         [0015]     The 3-input NOR transistor circuit  200 - 1  consists of three DTPMOS transistors  201 ,  202 , and  203  of the DTPMOS in  FIG. 1  connected in series between the supply voltage node V DD  and the transistor circuit  200 - 1 &#39;s output node  214 , and three NMOS transistors  204 ,  205 , and  206  connected in parallel between the output node  214 , which is defined as the common connection between the drains of the three NMOS transistors  204 ,  205 , and  206 , and the node  216  which is connected to the ground node GND. Source node  216  is defined as the common connection between the sources of the three NMOS transistors  204 ,  205 , and  206  and is connected to the ground node GND.  
         [0016]     The DTPMOS transistor  201  has the same input  211  as the NMOS transistor  204  and its source  209  is connected to the supply voltage node V DD  and its drain is connected to the internal signal node  210  which is connected to the source of the DTPMOS transistor  202 . The DTPMOS transistor  202  has the same input  213  as the NMOS transistor  205  and its source is connected to the internal signal node  210  and its drain is connected to the internal signal node  212  which is connected to the source of the DTPMOS transistor  203 . The DTPMOS transistor  203  has the same input  215  as the NMOS transistor  206  and its source is connected to the internal signal node  212  and its drain is connected to the transistor circuit  200 - 1 &#39;s output node  214 .  
         [0017]     The inverter  200 - 2  consists of a DTPMOS transistor  207  of the DTPMOS in  FIG. 1  and an NMOS transistor  208 . The DTPMOS transistor  207  has the same input as the NMOS transistor  208  which is the output  214  of the 3-input NOR transistor circuit. The DTPMOS transistor  207 &#39;s source  217  is connected to the supply voltage node V DD  and its drain  218  is connected to the inverter  200 - 2 &#39;s output node  220 . The NMOS transistor  208  drain is connected to the inverter  200 - 2 &#39;s output node  220  and its source  219  is connected to the ground node GND.  
       SUMMARY OF THE INVENTION  
       [0018]     The principle object of the present invention is to provide a method for controlling a PMOS transistor body dynamically for ultra-low voltage ultra-low power operation. In a preferred embodiment of the invention, the PMOS transistor body bias signal is generated on the circuit level; more specifically the PMOS transistor body is tied to the output node of the transistor circuit which contains the said transistor. In another embodiment of the invention, all PMOS transistors&#39; bodies in a transistor circuit are connected to the transistor circuit&#39;s output to provide the necessary body bias for the PMOS transistors. This body bias will increase transistor circuit&#39;s speed, reduce transistor circuit&#39;s power dissipation, and improve transistor circuit&#39;s stability and robustness against different physical and environmental parameters variations compared to the prior art schemes. The present invention has several novel features and advantages when compared to the prior art schemes.  
         [0019]     One advantage of the present invention is that it eliminates unnecessary PMOS transistors&#39; bodies switching activity when their corresponding inputs to the PMOS gates switch.  
         [0020]     Another advantage of the present invention is that it minimizes or eliminates glitches at the output node.  
         [0021]     Another advantage of the present invention is that uses less power than the prior art schemes.  
         [0022]     One more advantage of the present invention is that it reduces the load on the input signals at the PMOS transistors&#39; gates leading to faster operation and lower circuit delay.  
         [0023]     One further advantage of the present invention is that it reduces the unnecessary high current which was supplied in the prior art schemes even when the transistor circuit&#39;s output has made the switching.  
         [0024]     These and other objects, advantages, and features of this invention will be apparent from the following description. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]      FIG. 1  illustrates a MOSFET transistor circuit scheme of DTMOS known in the prior art.  
         [0026]      FIG. 2  depicts a 3-input OR transistor circuit schematic using the DTPMOS scheme known in the prior art.  
         [0027]      FIG. 3  depicts a 3-input OR transistor circuit schematic using the first preferred embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0028]     In the following detailed description of the embodiments reference is made to the accompanying drawings. The drawings are intended to show, by way of illustration, specific embodiments in which the invention may be practiced; like reference numerals in text refer to like elements in drawings. It is to be understood that other embodiments of the invention may be utilized and structural changes may be made without departing from the scope of the present invention.  
         [0029]      FIG. 3  illustrates the use of the first preferred embodiment of the present invention in constructing a 3-input OR transistor circuit  300 . The 3-input OR transistor circuit  300  comprises a 3-input NOR transistor circuit  300 - 1  and a CMOS inverter  300 - 2 . The output of the 3-input NOR transistor circuit  300 - 1  is connected to the input of the CMOS inverter  300 - 2 .  
         [0030]     The 3-input NOR transistor circuit comprises three PMOS transistors  301 ,  302 , and  303  connected in series between the internal signal nodes  311  and  320 , and three NMOS transistors  304 ,  305 , and  306  connected in parallel between the two internal signal nodes  320  and  322 . The internal signal node  320  is defined as the common connection between the drains of the three NMOS transistors  304 ,  305 , and  306 . Source node  322  is defined as the common connection between the sources of NMOS transistors  304 ,  305 , and  306  and is connected to the ground node GND.  
         [0031]     The PMOS transistor  301 &#39;s gate  309  is connected to the input node  310  which is the same input node connected to the NMOS transistor  304 &#39;s gate, its source node  311  is connected to the supply voltage node V DD , and its drain is connected to the internal signal node  312  which is connected to the source of the PMOS transistor  302 . The PMOS transistor  302 &#39;s gate  314  is connected to the input node  315  which is the same input node connected to the NMOS transistor  305 , its source is connected to the internal signal node  312 , and its drain is connected to the internal signal node  316  which is connected to the source of the PMOS transistor  303 . The PMOS transistor  303 &#39;s gate  318  is connected to the input node  319  which is the same input node connected to the NMOS transistor  306 , its source is connected to the internal signal node  316 , and its drain is connected to the transistor circuit  300 - 1 &#39;s output node  320 .  
         [0032]     The CMOS inverter  300 - 2  consists of a PMOS transistor  307  and an NMOS transistor  208 . The PMOS transistor  307 &#39;s gate  323  is connected to the inverter  300 - 2 &#39;s input  320 , which is the 3-input NOR  300 - 1  output. PMOS transistor  307  has the same input node  320  which is connected to the NMOS transistor  208  gate. The PMOS transistor  307 &#39;s source  324  is connected to the supply voltage node V DD  and its drain  325  is connected to the inverter  300 - 2 &#39;s output node  328 . The NMOS transistor  308  drain is connected to the inverter  300 - 2 &#39;s output node  328  and its source  327  is connected to the ground node GND.  
         [0033]     In the first preferred embodiment of this invention and in reference to the illustration example shown in  FIG. 3 , the bodies nodes  313 ,  317 , and  321  of the three PMOS transistors  301 ,  302 , and  303  respectively in the 3-input NOR transistor circuit  300 - 1 , are connected to the output node  320  of the circuit  300 - 1  to provide the necessary dynamic change in the threshold voltage of transistors  301 ,  302 , and  303  to ensure correct operation of the circuit as will be described in details hereafter. Likewise, the body node  326  of the PMOS transistor  307  in the CMOS inverter  300 - 2  is connected to the output node  328  of the circuit  300 - 2 .  
         [0034]     In one embodiment of the present invention, the three PMOS transistors  301 ,  302 , and  303  should share the same n-well during the Bulk-CMOS fabrication process in order to have the same body bias signal from the internal signal node  320 . The PMOS transistor  307  will have its own n-well in isolation from the other PMOS transistors in this specific circuit since it is tied to the inverter  300 - 2 &#39;s output node  328  and it is different than the body bias signal supplied to other PMOS inverter in this transistor circuit example. It is to be understood that the feature related to this embodiment should be applied to all PMOS transistors sharing the same body bias signal in any circuit other than the one described in this text and in  FIG. 3 .  
         [0035]     In the prior art and in reference to  FIG. 2 , DTPMOS transistors  201 ,  202 ,  203 , and  207  bodies are biased individually by connecting these bodies to their respective inputs  211 ,  213 ,  215 , and  214 ; respectively, so that each transistor may have a high or low threshold voltage depending on its input state, hence low or high subthreshold leakage current, independent of the transistor circuit, in which these transistor are part of, state. Consequently, a transistor circuit may experience a high current even though it may not be needed due to individual PMOS transistors states and to the circuit output(s) state(s) (output nodes  214  and  220  in  FIG. 2 ). Moreover, such high currents introduce glitches in the output signals  214  and  220  waveforms which further increase circuit&#39;s power consumption.  
         [0036]     In the present invention and in reference to  FIG. 3 , the bodies of all PMOS transistors are connected to their corresponding transistor circuit output. In the first preferred embodiment of the present invention a body biasing signal is generated on the transistor circuit level by the circuit output itself so that the used biasing signal will not vary from a transistor to a transistor within the same circuit as in the prior art, thus the subthreshold leakage current (the operating current) will change dynamically according only to the circuit output state and not to individual transistors operating states.  
         [0037]     The operation of the present invention is different than that of the prior art and it will be described in details hereafter with reference to  FIG. 3 . Throughout the following detailed description of the present invention the term “PMOS network” will refer to the PMOS transistor(s), PMOS transistor configuration, and PMOS transistors connection in a transistor circuit. For example, in  FIG. 3  there is a PMOS network comprising PMOS transistors  301 ,  302 , and  303  in circuit  300 - 1  and there is another PMOS network comprising only PMOS transistor  307  in circuit  300 - 2 .  
         [0038]     In reference to  FIG. 3 , when the PMOS network comprising transistors  301 ,  302 , and  303  is off (in the case of any of the inputs are high in the  FIG. 3 ), the circuit  300 - 1  output node  320  will be low and since this output node is connected to the said PMOS transistors bodies then the PMOS transistors bodies&#39; bias will be low giving some rise to the subthreshold leakage current to some intermediate value. This variation in body bias will lead to a decrease in the PMOS transistors threshold voltage and hence an increase in the subthreshold leakage current, which is the switching current in the subthreshold circuits to which the present invention is related. However, this intermediate subthreshold leakage current value is less than the current value experienced by the circuit in the prior art scheme. In the prior art scheme,  FIG. 2 , and when the PMOS transistors inputs are low (PMOS transistors are on and PMOS network is on) the subthreshold leakage current is increased exponentially due to the dual effect of lower body bias, hence lower threshold voltage) and increase in the gate-to-source voltage (V GS ); in the present invention the increase in the subthreshold leakage current when the PMOS network is off is due only to the effect of lower body bias and V GS  still has no effect since the transistors are off. Therefore, the said intermediate subthreshold current value is less than the high current value in the prior art when the PMOS network is on.  
         [0039]     In the present invention and in reference to  FIG. 3 , as soon as the PMOS network of circuit  300 - 1  switches on (inputs  310 ,  315 , and  319  are low and all PMOS transistors  301 ,  302 , and  303  are on simultaneously), the said PMOS transistors bodies are already biased low from the previous state when the PMOS network was off and instantaneous high subthreshold leakage current will flow in the PMOS network leading the output node  320  to charge causing circuit  300 - 1  to switch faster and the output to rise faster than the prior art scheme ( FIG. 2 ). When the transistor circuit  300 - 1  output node  320  rises to logic high (V DD ), the PMOS transistors  301 ,  302 , and  303  bodies will be forced to rise to V DD  and this, consequently, will suppress the subthreshold leakage current afterwards, since it will lead to higher PMOS transistors threshold voltage; however, this will happen only after this extra current is not needed anymore and the circuit  300 - 1  output node  320  has already evaluated correctly.  
         [0040]     In the prior art ( FIG. 2 ), and when the PMOS network switches on, PMOS transistors  201 ,  202 , and  203  bodies need some time to discharge after being charged in the previous state when the PMOS network was off which causes the prior art circuit to be slower than the present invention. After the prior art circuit  200 - 1  ( FIG. 2 ) has finished switching and its output node  214  has risen to V DD , still a high subthreshold leakage current will continue to flow, since the PMOS transistors bodies are still connect to the transistors inputs which are still low, causing the circuit to dissipate more power than necessary as long as the PMOS transistors are on. Also, high drain currents in the prior art scheme come at the expense of much larger currents drawn from the input sources which add to the circuit total power dissipation.  
         [0041]     Similar discussions and illustrations relating to the present invention can be demonstrated on the inverter circuit  300 - 2  in  FIG. 3  and in comparison to the inverter circuit  200 - 1  in  FIG. 2  of the prior art.  
         [0042]     In the prior art scheme and in reference to  FIG. 2 , all PMOS transistors bodies are tied to their corresponding inputs, this will cause the output node  214  to experience signal glitches when any of the PMOS transistors inputs make a switching regardless of the circuit output state. This leads the prior art scheme to experience more power dissipation, more noise generation within the circuit, and lower reliability. The present invention minimizes or completely eliminates such glitches because the PMOS transistors bodies, and hence the circuit&#39;s subthreshold leakage current, are not a function of the applied input signals, instead they depend only on the circuit&#39;s output state.  
         [0043]     Due to the fact that the present invention circuits have some intermediate current value during the time in which the PMOS network is off, the present invention will work best if the circuit has a moderate-to-high switching activity. This way it will continuously save more power than the prior art scheme while if it had a low activity factor then it would still outperform the prior art scheme in terms of speed and power consumption, but it will suffer from some high currents and hence its power consumption will increase during circuit idle durations causing gained savings to be reduced.  
         [0044]     There are of course other alternate embodiments that are obvious from the foregoing descriptions and illustrations of the invention, which are intended to be included within the scope of the invention, as defined by the following claims.