Abstract:
A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. A control gate is connected to each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. An array of such memory cells comprises rows of cells in active regions adjacent to one another separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the source/drain region in common, the drain/source region in common and a first and second control gates in each of the trenches in common. Cells in adjacent columns have the source/drain in common and the first control gate in common.

Description:
TECHNICAL FIELD 
   The present invention relates to a bi-directional read/program non-volatile memory cell, that uses a floating gate for storage of charges capable of storing a plurality of bits in a single cell. More particularly, the present invention relates to an array of such non-volatile memory cell with no isolation regions between active regions, and a method of manufacturing. 
   BACKGROUND OF THE INVENTION 
   Uni-directional read/program non-volatile memory cells using floating gate for storage are well known in the art. See for example, U.S. Pat. No. 5,029,130, assigned to the present assignee. Typically, each of these types of memory cells uses a conductive floating gate to store one bit, i.e. either the floating gate stores charges or it does not. The charges stored on a floating gate control the conduction of charges in a channel of a transistor. In a desire to increase the storage capacity of such non-volatile memory cells, the floating gate of such memory cell is programmed to store some charges, with the different amount of charges stored being determinative of the different states of the cell, thereby causing a plurality of bits to be stored in a single cell. The problem with programming a cell to one of a multilevel state and then reading such a state is that the amount of charge stored on the floating gate differentiating one state from another must be very carefully controlled. 
   Bi-directional read/program non-volatile memory cells capable of storing a plurality of bits in a single cell are also well known in the art. See, for example, U.S. Pat. No. 6,011,725. Typically, these types of memory cells use an insulating trapping material, such as silicon nitride, which is between two other insulation layers, such as silicon dioxide, to trap charges. The charges are trapped near the source/drain also to control the conduction of charges in a channel of a transistor. The cell is read in one direction to determine the state of charges trapped near one of the source/drain regions, and is read in the opposite direction to determine the state of charges trapped near the other source/drain region. Hence, these cells are read and programmed bi-directionally. The problem with these types of cells is that to erase, holes or charges of the opposite conductivity must also be “programmed” or injected into the trapping material at precisely the same location where the programming charges were initially trapped in order to “neutralize” the programming charges. Since the programming charges and the erase charges are injected into a non-conductive trapping material, the charges do not move as in a conductive material. Therefore, if there is any error in injecting the erase charges to the location of the programming charges, the erase charges will not neutralize the programming charges, and the cell will not be completely erased. Moreover, to inject the erase charges, the cell must be erased bi-directionally, thereby increasing the time required for erasure of one cell. 
   The present invention is an improvement to the invention disclosed in U.S. patent application Ser. No. 10/409,333 published on Oct. 7, 2004, whose disclosure is incorporated herein by reference in its entirety. Although the present invention is an improvement to the aforementioned reference, the aforementioned reference is not prior art to the present invention since the present application is assigned to the same assignee as that reference. 
   SUMMARY OF THE INVENTION 
   In the present invention, an array of non-volatile memory cells is arranged in a plurality of rows and columns. The array comprises a substantially single crystalline semiconductive substrate material of a first conductivity type. A plurality of non-volatile memory cells are arranged in a plurality of rows and columns in the semiconductive substrate material with each cell for storing a plurality of bits. Each cell comprises a first region of a second conductivity type, different from the first conductivity type in the material, and a second region of the second conductivity type in the material, spaced apart from the first region. A channel region has a first portion, a second portion and a third portion and connects the first and second regions for the conduction of charges. A dielectric is on the channel region. A first floating gate is on the dielectric, spaced apart from the first portion of the channel region. The first portion of the channel region is adjacent to the first region. The first floating gate is for the storage of at least one of the plurality of bits. A second floating gate is on the dielectric, spaced apart from the second portion of the channel region. The second portion of the channel region is adjacent to the second region. The second floating gate is for the storage of at least another of the plurality of bits. A gate electrode is on the dielectric, spaced apart from the third portion of the channel region. The third portion of the channel region is between the first portion and the second portion. A first gate electrode is electrically connected to the first region and is capacitively coupled to the first floating gate. A second gate electrode is electrically connected to the second region and is capacitively coupled to the second floating gate. Cells in the same row have the gate electrode in common. Further cells in adjacent rows are separated from one another by the semiconductive substrate material without any isolation material. Cells in the same column have the first region in common, the second region in common, the first gate electrode in common, and the second gate electrode in common. Finally, cells in adjacent columns have the first region in common and the first gate electrode in common. 
   The present invention also relates to a method of making the non-volatile memory array. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS.  1 -A( 1 - 10 ) and  1 -B( 1 - 10 ) are cross sectional views of the steps to process a semiconductor substrate before the steps showing the method of the present invention. 
     FIGS.  1 -A( 1 - 10 ) are cross-sectional views shows the processing steps in the memory array portion, whereas FIGS.  1 -B( 1 - 10 ) are cross-sectional views showing the corresponding processing steps in the periphery portion showing the formation of shallow trench isolation in the peripheral region. 
       FIGS. 2A-2K  are cross sectional views of the semiconductor structure in FIG.  1 -A 10  taken along the line  2 - 2  showing in sequence the steps in the processing of the semiconductor structure in the formation of a non-volatile memory array of floating gate memory cells of the present invention. 
       FIG. 3  is a schematic circuit diagram of the memory cell array of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The present invention relates to an array of non-volatile memory cells, without any isolation between rows of adjacent active regions, and a method of making thereof, which is illustrated in  FIGS. 2A to 2K . However, as is well known in the art, an array of non-volatile memory cells is typically integrated with peripheral circuits on an integrated circuit. Further, typically, isolation regions must be formed in the peripheral circuit portion of an integrated circuit memory device. Thus, before discussing the method of manufacturing the array of the present invention, a discussion will be made as to the methods for the formation of the isolation regions in the peripheral circuits. 
   The method begins with a semiconductor substrate  10 , which is preferably of P type and is well known in the art. The thickness of the layers described below will depend upon the design rules and the process technology generation. What is described herein is for the 90 nm process. However, it will be understood by those skilled in the art that the present invention is not limited to any specific process technology generation, nor to any specific value in any of the process parameters described hereinafter. 
   Isolation Region Formation in the Peripheral Region 
   FIGS.  1 -B 1  to  1 -B 10  illustrate the processing of a substrate  10  in the formation of the isolation regions in the peripheral region  10 B while FIGS.  1 -A 1  to  1 -A 10  illustrate the corresponding processing steps in the memory array portion 
   Referring to FIGS.  1 -A 1  and  1 -B 1 , there is shown a cross sectional view of a semiconductor substrate  10  (or a semiconductor well), which is preferably of P type and is well known in the art. A first layer  12  of silicon dioxide (hereinafter “oxide”) of approximately 110 {acute over (Å)} is deposited or grown on the substrate  10 . Thereafter a layer  14  of polysilicon  14  (hereinafter “poly”) of approximately 200 {acute over (Å)} is grown or deposited on the oxide  12 . A layer  16  of silicon nitride (hereinafter “nitride”) of approximately 1400 {acute over (Å)} is grown or deposited on the layer  14 . Another layer  18  of oxide of approximately 300 {acute over (Å)} is deposited. The layer  18  can be TEOS deposited oxide. Finally, a layer  20  of Silicon Oxynitride (SiON) of approximately 480 {acute over (Å)} is deposited on the layer  18 . The resultant structure is shown in FIGS.  1 -A 1  and  1 -B 1 . 
   Photoresist  22  is then applied to cover the structure shown in FIGS.  1 -A 1  and  1 -B 1 . The memory array portion  10 A is covered and an opening  26  of approximately 90 nm (or any other desired lithographic size) is made in the peripheral portion  10 B. The resultant structure is shown in FIGS.  1 -A 2  and  1 -B 2 . 
   Through the opening  26 , the layer  20  of SiOn is etched, the layer  18  of oxide is etched, the layer  16  of nitride is etched, the layer  14  of polysilicon is etched, the layer  12  of oxide is etched, and the substrate  10  is etched to formed a trench  28  of approximately 2000-3000 {acute over (Å)} deep. The photoresist  22  is then removed. The layer  20  of SiON is also removed. The resultant structure is shown in FIGS.  1 -A 4  and  1 -B 4 . 
   The layer  18  of TEOS oxide is removed by dipping the structure in DHF. The resultant structure is shown in FIGS.  1 -A 5  and  1 -B 5 . 
   Photoresist  30  is then applied again to the entire structure. A masking step is performed in the memory array portion  10 A, creating openings in the photoresist  30 . The resultant structure is shown in FIGS.  1 -A 6  and  1 -B 6 . 
   Using the openings in the memory array portion  10 A, the layer  16  of nitride is etched, the layer  14  of polysilicon is etched, and the layer of oxide  12  is etched. Further, the silicon substrate  10  may be optionally etched. The photoresist  30  is then removed, resulting in the structure shown in FIGS.  1 -A 7  and  1 -B 7 . 
   Sacrificial oxide is then deposited. This is followed by a dilute HF acid dip. Then a High Density Plasma Chemical Vapor Deposition step of oxide  32  is performed. Finally a two step CMP step with high selectivity of oxide  32  and nitride  16  is performed. The resultant structure is shown in FIGS.  1 -A 8  and  1 -B 8 . 
   The memory array portion  10 A is covered again, and the STI  32  in the peripheral portion is reduced by selective etching. The resultant structure is shown in FIGS.  1 -A 9  and  1 -B 9 . 
   The structure shown in FIGS.  1 -A 9  and  1 -B 9  is subject to a process to remove the SiN  16  and the polysilicon  14 . This results in trenches  40  being formed in the memory array portion  10 A. The resultant structure is shown in FIGS.  1 -A 10  and  1 -B 10 . 
   Memory Cell/Array Formation 
   The structure shown in FIG.  1 -A 10  is further processed as follows.  FIGS. 2A to 2K  show the cross sections of the structure in the active regions  40  from a view orthogonal to that of FIG.  1 -A 10  (along line  2 - 2  as shown in FIG.  1 -A 10 ). 
   The active region  40  portion of the substrate  10  can be doped at this time for better independent control of the cell array portion of the memory device relative to the periphery region. Such doping is often referred to as a V t  implant or cell well implant, and is well known in the art. During this implant, the periphery region is protected by a photo resist layer, which is deposited over the entire structure and removed from just the memory cell array region of the substrate. 
   Next, a thick layer (e.g. ˜1650 Å thick) of hard mask material  42  such as silicon nitride is formed over oxide layer  12 . This is followed by deposition of another layer of oxide  44  of approximately 800 {acute over (Å)} thick. A plurality of parallel second trenches  50  are formed in the oxide layer  44 , the nitride layer  42  and the oxide layer  12 , by applying a photo resist (masking) material on the oxide layer  44 , and then performing a masking step to remove the photo resist material from selected parallel stripe regions. An anisotropic oxide etch is used to remove the oxide layer  44 , then an anisotropic nitride etch is used to remove the exposed portions of nitride layer  42  in the stripe regions, leaving second trenches  50  that extend down to and expose oxide layer  12 . After the photo resist is removed, an anisotropic oxide etch is used to remove the exposed portions of oxide layer  12  and extend second trenches  50  down to the substrate  10 . A silicon anisotropic etch process is then used to extend second trenches  50  down into the substrate  10  in each of the active regions  40  (for example, down to a depth of approximately one feature size deep, e.g. about 0.15 um deep with 0.15 um technology). Alternately, the photo resist can be removed after trenches  50  are formed into the substrate  10 . The resulting active region  40  is shown in  FIG. 2A . 
   A layer of insulation material  36  is next formed (preferably using a thermal oxidation process) along the exposed silicon in second trenches  50  that forms the bottom and lower sidewalls of the second trenches  50  (e.g. ˜70 Å to 120 Å thick). A thick layer of polysilicon  38  is then formed over the structure, which fills second trenches  50 . Poly layer  38  can be doped (e.g. n+) by ion implant, or by an in-situ process. The resulting active region  40  is shown in  FIG. 2B . 
   A poly etch process (e.g. a CMP process using oxide layer  44  as an etch stop) is used to remove poly layer  38  except for blocks  60  of the polysilicon  38  left remaining in second trenches  50 . A controlled poly etch is then used to lower the height of poly blocks  60 , where the tops of poly blocks  60  are disposed above the surface of the substrate, but below the tops of STI blocks  32  in the adjacent rows. The resultant structure is shown in  FIG. 2C . 
   Another poly etch is then performed to create sloped portions  62  on the tops of poly block  60  (adjacent the second trench sidewalls). Oxide spacers  64  are then formed along the second trench sidewalls  50  and over the sloped portions  43  of poly blocks  60 . Formation of spacer is well known in the art, and involves the deposition of a material over the contour of a structure, followed by an anisotropic etch process, whereby the material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure. Spacers  64  can be formed of any dielectric material, such as oxide, nitride, etc. In the present embodiment, insulating spacers  64  are formed by depositing a layer of oxide over the entire structure, followed by a anisotropic oxide etch process, such as the well known Reactive Ion Etch (RIE), to remove the deposited oxide layer except for spacers  64 . The resulting active region  40  is shown in  FIG. 2D   
   An anisotropic poly etch is next performed, which removes the center portions of the poly blocks  60  that are not protected by oxide spacers  64 , leaving a pair of opposing poly blocks  60   a  in each of the second trenches  50 , as shown in  FIG. 2E . 
   An insulation deposition (approximately 100 {acute over (Å)}) and anisotropic etch-back process (preferably using oxide is then used to form an insulation layer  66  along the exposed sides of poly blocks  60   a  inside second trenches  50  (shown in  FIG. 2F ). The insulation material could be any insulation material (e.g. ONO—oxide/nitride/oxide, or other high dielectric materials). Preferably, the insulation material is oxide, so that the oxide deposition/etch process also thickens the oxide spacers  64 . A polysilicon deposition (approximately 100 {acute over (Å)}) and anisotropic etch-back process is then used to form layer  68  along the exposed sides of oxide  64  and inside the trenches  50 . The resultant structure is shown in  FIG. 2F . 
   The structure shown in  FIG. 2F  is subject to an anisotropic etch process which removes the polysilicon  68  from the bottom wall of the trenches  50 . Thereafter, an anisotropic etch of the oxide  36  from the bottom wall of the trench  50  is performed, exposing the substrate  10 . The resultant structure is shown in  FIG. 2G   
   Suitable ion implantation (and possible anneal) is then made across the surface of the structure to form first (source) regions  52  in the exposed substrate portions at the bottom of second trenches  50 . The source regions  52  are self-aligned to the second trenches  50 , and have a second conductivity type (e.g. N type) that is different from a first conductivity type of the substrate (e.g. P type). The ions have no significant effect on the nitride layer  42 . The resulting active region  40  is shown in  FIG. 2H . 
   A poly deposition step, followed by a poly CMP etch (using the nitride layer  42  as an etch stop) are used to fill second trenches  50  with poly blocks  54 , as shown in  FIG. 2I . In situ doping of the polysilicon  54  is also performed. Thereafter, the polysilicon is etched back in the trench  40  A layer (approximately 170 {acute over (Å)}) of oxide  58  is grown on the structure capping the polysilicon  54  in the trench  50 . This is followed by CMP so that the oxide  58  is planar with respect to the nitride  42 . The resultant structure is shown in  FIG. 2I . 
   A nitride etch follows, which removes nitride layer  42 . A poly deposition step is used to form a poly layer  70  over the structure (e.g. approximately 500 {acute over (Å)} thick). Photo resist deposition and masking steps follow to form strips of poly layer  70  that are spaced apart from one another each over an active region  40 . The resulting active region  40  is shown in  FIG. 2K . Each poly layer  70  functions as a word line for the memory array. 
   As shown in  FIG. 2K , the process of the present invention forms an array of memory cells, with each memory cell  15  being between a pair of spaced apart source/drain regions  52 ( a,b ) (those skilled in the art would appreciated that the term source and drain may be interchanged during operation.) A non-planar channel region connects the two source regions  52 ( a,b ), with the channel region having three portions; a first portion, a second portion and a third portion. The first portion of the channel region is along one of the sidewall of one of the trenches  50 , and is adjacent to the first source region  52   a.  The second portion of the channel region is along one of the sidewall of the other trench  50 , and is adjacent to the second source region  52   b.  A third portion of the channel region is between the first portion and the second portion and is substantially along the top surface of the substrate  10 . A dielectric layer is over the channel region. Over the first portion of the channel region, the dielectric is the layer  36   a.  Over the second portion of the channel, the dielectric is the layer  36   b.  Over the third portion of the channel region, the dielectric is the layer  12 . A first floating gate  60   a  is on the layer  36   a,  and is over the first portion of the channel region, which is adjacent to the first source region  52   a.  A second floating gate  60   b  is on the layer  36   b,  and is over the second portion of the channel region, which is adjacent to the second source region  52   b.  A gate electrode  70 , formed by the poly layer  70 , is over the dielectric layer  12  and is over the third portion of the channel region. A first control gate  54   a  is connected to the first source region  52   a,  and is capacitively coupled to the first floating gate  60   a.  A second control gate  54   b  is connected to the second source region  52   b,  and is capacitively coupled to the second floating gate  60   b.  Further, each of the floating gates  60   a  and  60   b  is substantially perpendicular to the gate electrode  70  and to the surface of the substrate  10 . Finally, each source region, e.g. first source region  52   a,  and its associated control gate, e.g. first control gate  54   a  is shared with an adjacent memory cell  15  in the same active region  40 . 
   The floating gates  60  ( a,b ) are disposed in trenches  50 , with each floating gate facing and insulated from a portion of the channel region. Further, each floating gate  60  ( a,b ) includes an upper portion that extends above the substrate surface and terminates in an edge that faces and is insulated from one of the control gates  70 , thus providing a path for Fowler-Nordheim tunneling through oxide layer  36 . Each control gate  54  extends along and are insulated from floating gates  50 , for enhanced voltage coupling therebetween. 
   With respect to the plurality of memory cells  15  that form an array, the interconnection is as follows. For memory cells  15  that are in the same column, i.e. in the same active region  22 , the word line  70  that forms the gate electrode for each memory cell  15  is extended in the Y direction to each of the memory cells  15 . For memory cells  15  that are in the same row, i.e. across the active regions  40 , the source lines  52  ( a,b ) and/or the associated control gates  54  ( a,b ) are extended in the X direction to each of those memory cells  15 . Because the source regions  52 ( a,b ) are in a trench  50 , they are in the active regions  40  and extend to an adjacent active region  40 . Thus, the formation of the source regions  52  form a continuous connection between the memory cells  15  that are in the row direction and extend in the X direction. Of course, the subsequent formation of the associated control gates  54  ( a,b ) would also connect the memory cells  15  in the row direction. Finally, as can be seen from the foregoing, memory cells  15  in adjacent rows, share the same source region  52  and the same associated control gate  54 . 
   The operation of the memory cell  15  and the array shown in  FIG. 2P  is identical to that shown and described in U.S. patent application Ser. No. 10/409,333 published on Oct. 7, 2004, whose disclosure is incorporated herein by reference in its entirety.