Abstract:
A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the benefit of Korean Patent Application No. 10-2005-0001092, filed Jan. 6, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.  
       BACKGROUND  
       [0002]     1. Technical Field  
         [0003]     This application relates to semiconductor memory devices, methods for controlling the same, and more particularly, to a semiconductor memory device and a method for controlling the same in which core control signals controlling read or write operations in semiconductor memory devices are enabled by one master signal.  
         [0004]     2. Discussion of Related Art  
         [0005]     In general, read and write operations in semiconductor memory devices are performed repeatedly. In the read operation, data in selected memory cells is read from the semiconductor memory device. In the write operation, external input data is stored in selected memory cells. Data input and output speed of semiconductor memory devices are key factors in determining the operational speed of a system that uses the semiconductor memory devices. Studies for improving the operational speed of semiconductor memory devices are ongoing. These studies have resulted in synchronous semiconductor memory devices (e.g., synchronous DRAMs; SDRAMs) having internal circuits synchronized with an external clock signal.  
         [0006]     The synchronous semiconductor memory devices may be classified into single data rate synchronous memory devices (single data rate SDRAM; SDR SDRAM) and double data rate synchronous memory devices (double data rate SDRAM; DDR SDRAM). In SDR SDRAM, one set of data is input or output during one cycle of an external clock signal in response to a rising edge or a falling edge of the external clock signal. The DDR SDRAM, two sets of data are input or is output during one cycle of an external clock signal, one in response to a rising edge and one in response to a falling edge of the external clock signal. Consequently, DDR SDRAM may have a bandwidth that is two times greater than that of SDR SDRAM.  
         [0007]     Several control signals are necessary for read and write operations in a semiconductor memory device. The semiconductor memory device is generally divided into a cell array area, a core area and a ferry area. The control signals are called core control signals since most of the control signals are generated in the core area.  
         [0008]      FIG. 1  is a schematic block diagram of a data input and output path from a memory cell to input and output lines and associated circuits in a synchronous semiconductor memory device.  
         [0009]     The data input and output path will be described with reference to  FIG. 1 . First, a data output path when data in a memory cell  10  is read in a read operation in a semiconductor memory device will be described.  
         [0010]     The memory cell  10  is basically composed of one transistor and one capacitor. When a word line WL is selected and enabled in response to a row address, the transistor of the memory cell  10  is turned on and data in the capacitor is loaded on a bit line BL. The bit line BL forms a bit line pair with a complementary bit line BLB. The data on the bit line BL is sensed and amplified by a bit line sense amplifier  20 . The amplified data on the pair of bit lines BL and BLB is loaded onto a pair of local input and output lines LIO and LIOB via transistors N 1  and N 2  responsive to a column select signal (CSL). For example, when the column select signal CSL for a specific column is enabled by a column address, data on bit line pair BL and BLB of the column is loaded onto the local input and output lines LIO and LIOB. The loaded data on the pair of the local input and output line LIO and LIOB is sensed and amplified by an input and output sense amplifier  40 . Here, it is necessary to precharge the pair of the local input and output lines LIO and LIOB by means of the local input and output line precharge circuit  30  responsive to a local input and output line precharge signal LIOPRB before the column select signal CSL is enabled so that the sense amplifier  40  correctly senses data. The amplified data from the input and output sense amplifier  40  is loaded onto a pair of global input and output lines GIO and GIOB and is output outside the memory device. It is also necessary to precharge the global input and output lines GIO and GIOB prior to data transmission by means of the global input and output line precharge circuit  50  responsive to the global input and output line precharge signal GIOPRB.  
         [0011]     A data input path, when data is written to a semiconductor memory cell, will be now described. When external data is input at the start of a write operation, the global input and output line driver circuit  60  sends external input data to the global input and output line pair GIO and GIOB. The global input and output line driver circuit  60  is enabled in response to a first data loading signal PDT. The data on the global input and output line pair GIO and GIOB is loaded to the local input and output line pair LIO and LIOB by a local input and output line driver circuit (not shown) responsive to a second data loading signal LGIOCON. The data on the local input and output line pair LIO and LIOB is loaded to the bit line pair BL and BLB by the transistors N 1  and N 2  responsive to the column select signal CSL and is stored in the memory cell  10 .  
         [0012]     As described above, to perform such read and write operations, the semiconductor memory device requires core control signals controlling the data input and output path.  
         [0013]     Examples of the core control signals include a read/write identifying signal PWRD for identifying reading operation and writing operation, a first data loading signal PDT, a second data loading signal LGIOCON, input and output line precharge signals LIOPRB and GIOPRB for precharging input and output lines LIO, LIOB, GIO and GIOB, a sense amplifier enable signal LSAEN for enabling an input and output line sense amplifier, and a column select signal CSL for data transmission between a bit line pair BL and BLB and local input and output lines LIO and LIOB. These core control signals are generated in control signal generating circuits responsive to a master signal.  
         [0014]     As used herein, a master signal is a signal for controlling generation of specific control signals. For example, a signal input to the column select signal CSL generating circuit in order to enable or disable the column select signal CSL is called a master signal for the column select signal CSL.  
         [0015]      FIG. 2  is a timing diagram illustrating generation of the control signals.  
         [0016]     As shown in  FIG. 2 , when an external clock signal CLK is applied, an internal clock signal PCLK is generated in synchronization with the external clock signal CLK. When read or write operation is initiated, a bank address BA for selecting one of memory banks constituting a cell array of a semiconductor memory device, and a first control signal PCLKCD as a delayed version of the internal clock signal PCLK are generated in response to a rising edge of the internal clock signal PCLK. Further, a second control signal PCSLD as a delayed version of the internal clock signal PCLK is generated in response to a rising edge of the next cycle of the internal clock signal. The column select signal CSL is enabled with a certain delay in response to a rising edge of the first control signal PCLKCD as a master signal and disabled with a certain delay in response to a rising edge of a second control signal PCSLD as a master signal. Core control signals IOPR and PWRD are enabled with a certain delay in response to a rising edge of the bank address signal BA as the master signal and disabled with a certain delay in response to a falling edge of the bank address signal BA. The core control signal IOPR is a complementary signal of input and output line precharge signals LIOPRB and GIOPRB. Other core control signals PDT, LGIOCON and LSAEN, which are not shown, either have a different master signal, or one of the above-described master signals.  
         [0017]     As described above, the core control signals LIOPRB, GIOPRB, PWRD, PDT, LGIOCON and LSAEN have a different master signal from that for the column select signal CSL. Delay variation or power, voltage, and temperature (PVT) variation in core control signal generation circuits result in increased design time for the master signals. In addition, in the delay variation or the PVT variation makes it difficult to obtain the absolute margin between the signals.  
       SUMMARY  
       [0018]     Embodiments include a control unit of a semiconductor memory device including control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.  
         [0019]     Other embodiments include semiconductor memory devices and methods of controlling semiconductor memory devices using the aforementioned control unit. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0020]     The above and other features and advantages of the invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:  
         [0021]      FIG. 1  is a schematic block diagram of a data input and output path from a memory cell to input and output lines and associated circuits in a typical synchronous semiconductor memory device;  
         [0022]      FIG. 2  is a timing diagram of core control signals for controlling the circuits of  FIG. 1 ;  
         [0023]      FIG. 3  is a block diagram of a control unit in a semiconductor memory device according to an embodiment;  
         [0024]      FIG. 4  is a circuit diagram of an input and output precharge signal generating circuit constituting the control unit of  FIG. 3 ; and  
         [0025]      FIG. 5  is a timing diagram showing generation of the core control signals of  FIG. 3 . 
     
    
     DETAILED DESCRIPTION  
       [0026]     Embodiments will now be described with reference to the accompanying drawings, in which preferred embodiments are shown. However, the invention should not be construed as limited to only the embodiments set forth herein. Rather, these embodiments are presented as teaching examples.  
         [0027]      FIG. 3  is a block diagram of a control unit  100  for generating core control signals in a semiconductor memory device. The semiconductor memory device includes an array of a memory cells, and a number of other circuits, in addition to the circuits for controlling the data input and output path of  FIG. 1 . In the following discussion, only portions of the semiconductor memory device sufficient to enable one skilled in the art to understand the invention will be described.  
         [0028]     As shown in  FIG. 3 , the control unit  100  of the semiconductor memory device includes an input and output line precharge signal (LIOPRB) generating circuit  110 , a read/write identifying signal (PWRD) generating circuit  120 , a first data loading signal (PDT) generating circuit  130 , a second data loading signal (LGIOCON) generating circuit  140 , an input and output line sense amplifier enable signal (LSAEN) generating circuit  150 , and a column select signal (CSL) generating circuit  160 . Although the listed control signals will be described below, one of ordinary skill in the art will understand that embodiments may encompass other control signals used in controlling a semiconductor memory device.  
         [0029]     The core control signals LIOPRB, PWRD, PDT, LGIOCON, LSAEN and CSL are enabled in response to a first master signal PCLKCD after a delay specific to each core control signal and are disabled in response to a second master signal PCSLD after another delay specific to each core control signal. The first master signal PCLKCD is a single pulse delayed from an edge of an internal clock signal synchronized to an external clock signal. The second master signal PCSLD is also a single pulse delayed from an edge of the internal clock signal, generated after the first master signal PCLKCD is generated.  
         [0030]     The input and output line precharge signal (LIOPRB) generating circuit  110  is configured so that the input and output line precharge signal LIOPRB is enabled in response to the first master signal PCLKCD after a delay and is disabled in response to the second master signal PCSLD after another delay. The input and output line precharge signal LIOPRB is a control signal for precharging an input and output line to a specific voltage. The input and output line precharge signal LIOPRB may include the precharge signal LIOPRB for the pair of the local input and output lines LIO and LIOB, and the precharge signal GIOPRB for the pair of the global input and output lines GIO and GIOB of  FIG. 1 . Alternatively, the input and output line precharge signal LIOPRB may include only the precharge signal LIOPRB for the pair of the local input and output lines LIO and LIOB. The input and output line precharge signal (LIOPRB) generating circuit  110  having the above-described function may be implemented in various methods by those skilled in the art.  
         [0031]     The read/write identifying signal (PWRD) generating circuit  120  is configured so that the read/write identifying signal PWRD is enabled in response to the first master signal PCLKCD after a delay and disabled in response to the second master signal PCSLD after another delay. The read/write identifying signal PWRD is a signal that indicates whether a read or write operation is to be performed. For example, the read/write identifying signal PWRD at a high level may indicate that the write operation is to be performed while the read/write identifying signal PWRD at a low level may indicate that the read operation is to be performed. The read/write identifying signal (PWRD) generating circuit  120  having the above-described function may be implemented in various methods by those skilled in the art.  
         [0032]     The first data loading signal (PDT) generating circuit  130  is configured so that the first data loading signal PDT is enabled in response to the first master signal PCLKCD after a delay and is disabled in response to the second master signal PCSLD after another delay. The first data loading signal PDT is a master signal for loading external input data onto the input and output lines in the writing operation. For example, where the input and output line is divided into the local input and output lines LIO and LIOB and the global input and output lines GIO and GIOB as in  FIG. 1 , the first data loading signal PDT loads the data onto the pair of the global input and output lines GIO and GIOB. The first data loading signal (PDT) generating circuit  130  having the above-described function may be implemented in various methods by those skilled in the art.  
         [0033]     The second data loading signal (LGIOCON) generating circuit  140  is configured so that the second data loading signal LGIOCON is enabled in response to the first master signal PCLKCD after a delay and is disabled in response to the second master signal PCSLD after another delay. The second data loading signal LGIOCON is a signal for loading the data on the global input and output line GIO and GIOB onto the local input and output lines LIO and LIOB in the write operation. The second data loading signal LGIOCON, when enabled, loads the data on the global input and output lines GIO and GIOB onto the input and output lines LIO and LIOB. The second data loading signal (LGIOCON) generating circuit  140  having the above-described function may be implemented in various methods by those skilled in the art.  
         [0034]     The input and output sense amplifier enable signal (LSAEN) generating circuit  150  is configured so that the input and output sense amplifier enable signal LSAEN is enabled in response to the first master signal PCLKCD after a delay and is disabled in response to the second master signal PCSLD after another delay. The input and output sense amplifier enable signal LSAEN is a signal for enabling the input and output sense amplifier in the read operation in order to perform a data sensing and amplifying operation. The input and output sense amplifier enable signal LSAEN generating circuit  150  having the above-described function may be implemented in various methods by those skilled in the art.  
         [0035]     The column select signal CSL generating circuit  160  is configured so that the column select signal CSL is enabled in response to the first master signal PCLKCD after a delay and disabled in response to the second master signal PCSLD after another delay. The column select signal CSL is a signal for controlling data transmission between bit lines BL and BLB and the input and output lines LIO and LIOB. The column select signal CSL loads the data on the bit line BL and BLB onto the input and output lines LIO and LIOB in the read operation and the data on the input and output lines LIO and LIOB onto the bit lines BL and BLB in the write operation. For example, a high column select signal CSL may allow data transmission between the bit lines BL and BLB and the local input and output lines LIO and LIOB. The column select signal (CSL) generating circuit  160  having the above-described function may be implemented in various methods by those skilled in the art.  
         [0036]     The core control signals LIOPRB, PWRD, PDT, LGIOCON, LSAEN and CSL, which are enabled and disabled in response to the first master signal PCLKCD and the second master signal PCLSD, each may have independent delays, one for delaying enabling and another for delaying disability. Each delay may be individually set to be suitable for the operation of the semiconductor memory device.  
         [0037]      FIG. 4  illustrates an exemplary implementation of an input and output precharge signal (LIOPRB) generating circuit  110  constituting the control unit.  
         [0038]     The input and output line precharge signal (LIOPRB) generating circuit  110  may be implemented as a circuit having a connection structure as shown in  FIG. 4  that includes logic NAND circuits NA 2  to NA 15 , logic NOR circuits NO 2  to N 08 , inverter circuits  12  to  113 , first to fourth delay circuits D 1  to D 4 , and logic AND circuits A 2  and A 3 .  
         [0039]     While an exemplary implementation of the input and output line precharge signal (LIOPRB) generating circuit  110  is illustrated in  FIG. 4 , other circuits constituting the control unit  100 , i.e., the read/write identifying signal (PWRD) generating circuit  120 , the first data loading signal (PDT) generating circuit  130 , the second data loading signal (LGIOCON) generating circuit  140 , the input and output line sense amplifier enable signal (LSAEN) generating circuit  150 , and the column select signal (CSL) generating circuit  160  may be implemented by adjusting the delay of the first to fourth delay circuits D 1  to D 4  in the configuration of the  FIG. 4 .  
         [0040]      FIG. 5  is a timing diagram of core control signals generated in the control unit of  FIG. 3 .  
         [0041]     Referring to  FIG. 5 , when an external clock signal CLK is applied, an internal clock signal PCLK is generated in synchronization with the external clock signal CLK. If a read or write operation is initiated, a bank address BA for selecting one of memory banks constituting a cell array of the semiconductor memory device and a first master signal PCLKCD as a delayed version of the internal clock signal PCLK are generated in response to a rising edge of the internal clock signal PCLK. Further, a second master signal PCSLD as a delayed version of the internal clock signal PCLK is generated in response to a rising edge of a next cycle of the internal clock signal.  
         [0042]     The column select signal CSL is enabled after a delay in response to a rising edge of a first master signal PCLKCD and is disabled after another delay in response to a rising edge of a second master signal PCSLD. The other core control signals such as IOPR and PWRD are enabled after a delay in response to the rising edge of the first master signal PCLKCD, and are disabled after another delay in response to the rising edge of the second master signal PCSLD, unlike the prior art. Here, the core control signal IOPR is a complementary signal of the input and output line precharge signals LIOPRB and GIOPRB. Similarly, other core control signals PDT, LGIOCON and LSAEN that are not shown are enabled within a delay in response to a rising edge of the first master signal PCLKCD and are disabled within another delay in response to a rising edge of the second master signal PCSLD as another master signal.  
         [0043]     As described above, the core control signals may have the same features such as the same delay or PVT variation by enabling the core control signals with a single master signal and disabling the core control signals with another single master signal. As a result, design time is reduced when designing different master signals, and while maintaining a correct absolute margin between the signals.  
         [0044]     The invention has been described using preferred exemplary embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, the scope of the invention is intended to include various modifications and alternative arrangements within the capabilities of persons skilled in the art using presently known or future technologies and equivalents. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.