Abstract:
A charge coupled device includes an integrated circuit substrate and a transfer circuit, in the integrated circuit substrate, that transfers charge signals in the charge coupled device to provide transferred charge signals. An amplifier, in the integrated circuit substrate and electrically coupled to the transfer circuit, amplifies the transferred charge signals to generate amplified charge signals. Related methods are also discussed.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 98-39100, filed Sep. 21, 1998, the entire disclosure of which is hereby incorporated herein by reference. 
     FIELD OF THE INVENTION 
     The present invention relates to the field of integrated circuits in general, and more particularly to charge coupled devices. 
     BACKGROUND OF THE INVENTION 
     Solid state image pickup devices, such as Charge Coupled Devices (CCDs), can be relatively small, light weight, and consume less power than other image pickup type devices such as an electron gun. Therefore, it is known to use CCDs in broadcasting, domestic video cameras, monitoring camera systems, digital still cameras, and the like. 
     The CCD shown in FIG. 1 is arranged in the form of a charge coupled array that includes a horizontal transfer section  10 . The horizontal transfer section  10  includes transfer gate electrodes  12  formed on an integrated circuit substrate such as a semiconductor substrate  11 . An output gate electrode  13  is disposed adjacent to the last one of the transfer gate electrodes  12  on the semiconductor substrate  11 . An n type impurity region  14  is formed in the semiconductor substrate  11  adjacent to the output gate electrode  13 . The n type impurity region  14  is a floating diffusion region. 
     A reset gate electrode  16  is disposed between the floating diffusion region  14  and an n type impurity region  15 . The n type impurity region  15  is formed in the surface region of the semiconductor substrate  11  adjacent to the reset gate electrode  16 . The floating diffusion region  14 , the n type impurity region  15  and the reset gate electrode  16  form a Field Effect Transistor (FET)  20 . 
     In operation, the potential at the floating diffusion region  14  is reset to the voltage level VOD by application the reset signal φR. Signal charges are transferred from the array by the horizontal transfer section  10  and converted from signal charges into signal voltages in accordance with the respective variation of the input potential from the reset voltage level. In particular, clock signals φH applied at the output gate electrode  13  cause electrons (charge signals) to enter the floating diffusion region  14 . The electrons are stored in the floating diffusion region  14  in accordance with the capacitance associated with the floating diffusion region  14 . 
     The presence of the charge signals in the floating diffusion region  14  may  10  cause the voltage level thereon to be lowered compared with the initial reset voltage level which is provided by the reset signal φR. The output circuit  30  detects the lowering of the potential of the floating diffusion region  14  and outputs a corresponding voltage level. The voltage level at the floating diffusion region is reset by the application of the reset signal φR before reading the next charge signals. 
     It is known to use CCDs in situations having relatively low levels of illumination, wherein respective weak signal charges may need to be converted into signal voltages for output. Unfortunately, as the area occupied by the CCDs decreases, the capacitance of the floating diffusion region  14  may make it difficult to provide adequate signal voltages in situations involving low level illumination. Accordingly, there is a need to allow improved CCDs and methods of transferring charge signals in CCDs. 
     SUMMARY OF THE INVENTION 
     It is, therefore, an object of the present invention to allow improved charge coupled devices and methods of transferring charge signals from charge coupled devices. 
     It is another object of the present invention to allow charge coupled devices having increased sensitivity. 
     These, and other objects of the present invention, may be achieved by charge coupled devices that include an integrated circuit substrate and a transfer circuit, in the integrated circuit substrate, that transfers charge signals in the charge coupled device to provide transferred charge signals. An amplifier, in the integrated circuit substrate and electrically coupled to the transfer circuit, amplifies the transferred charge signals to generate amplified charge signals. 
     According to the present invention, the amplifier can provide improved sensitivity by amplifying the transferred charge signals. The amplified charge signals can be amplified by a gain factor (β) of the amplifier. The sensitivity of the charge coupled device may also be increased by reducing the associated capacitance. 
     In another aspect of the present invention, the charge coupled device includes an output circuit, electrically coupled to the amplifier, that outputs the amplified charge signals from the charge coupled device. 
     In another aspect of the present invention, the charge coupled device includes a reset circuit, electrically coupled to the amplifier, that resets a level of the amplified charge signals in response to a reset signal applied to the reset circuit. 
     In one embodiment, the reset circuit is a field effect transistor that includes a drain region electrically coupled to a reset voltage level and a gate region electrically coupled to a reset signal line. A source region is electrically coupled to the amplifier and the n type semiconductor source region electrically couples the amplifier to the reset voltage level in response to a reset signal applied to the reset signal line. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is an enlarged cross-sectional view of a conventional CCD. 
     FIG. 2 is an enlarged cross-sectional view of a first embodiment of a CCD according to the present invention. 
     FIG. 3 is a circuit schematic diagram of the first embodiment of a CCD shown in FIG.  1 . 
     FIG. 4 is an enlarged cross-sectional view of a second embodiment of a CCD according to the present invention. 
     FIG. 5 is a circuit schematic diagram of the second embodiment of a CCD shown in FIG.  4 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. 
     In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. 
     FIG. 2 is an enlarged cross-sectional view of a first embodiment of a CCD according to the present invention. According to FIG. 2, a plurality of electrodes  202  are formed on an integrated circuit substrate such as on a p type semiconductor substrate (substrate)  201  to transfer signal charges in response to clock signals φH provided to the plurality of gate electrodes  202  by a plurality of n respective clock lines. The clock signals φH cause charge signals stored in the substrate  201  opposite the respective transfer gate electrodes  202  to be transferred toward the output electrode  204 . The output electrode  204  receives an output gate voltage level VOG which may allow the charge signals to be transferred from the charge coupled array. It will be understood that the signal charges are transferred, according to techniques well known in the art, through a moving or shifting potential well structure by, for example, three other clocks applied to the plurality of electrodes  202 . 
     The charge signals are transferred to Bipolar Junction Transistor (BJT) BT 1  or amplifier which includes an n type impurity region in the substrate  201  which serves as a base region  206 . The base region  206  is formed in the substrate  201  which serves as a collector region of the BJT BT 1 . A p type impurity region in the n type impurity region provides a first floating diffusion region which serves as a emitter region  208  of the BJT BT 1 . 
     A Field Effect Transistor (FET) M 1   210  (or reset circuit) is formed in the substrate  201  adjacent to the BJT BT 1 . The FET M 1  includes a second floating diffusion region formed in the substrate  201  which serves a source region  210   a adjacent to the base region  206 . A reset gate electrode  210   c  is formed between the source region  210   b  and an n type impurity region, which serves as a drain region  21   b . The reset gate electrode  210   c  receives reset clocks φR. The drain region  210   b  is biased by a drain voltage level VOD. 
     The emitter region  208  and the source region  210   a  are electrically coupled (at a node N 1 ) to an output circuit  300 . The output circuit  300  can be a source follower circuit. The output circuit  300  converts signal charges from the emitter region  208  and source region  210   a  to signal voltages which are output as output voltage Vout. 
     The signal charges transferred by the transfer gate electrodes  202  are injected into the emitter region  208 . Under this condition, the drain  210   b  receives the voltage VOD, and therefore, the emitter region  208  is reset to the potential of the voltage VOD when the reset clocks φR is applied to the reset gate electrode  210 . 
     When a high level reset clock φR is supplied to the reset gate electrode  210   c , the emitter region  208 , the source region  210   a , and the gate of the output circuit  300  are charged to the VOD voltage level. Under this condition, the output gate electrode  204  is blocked and, therefore, signal charges are not transferred to the base region  206 . Further, the base region  206  and the substrate  201  (collector region of BJT BT 1 ) are reverse biased, and therefore, current does not flow to the node N 1 . Under this condition, the voltage level at the node N 1  is sampled. 
     When a low level reset clock signal φR is supplied, the signal charges cross the output gate electrode  204  to the base region  206 . When the signal charges are transferred to the base region  206 , current i flows to the ground based on the following equations: 
     
       
           i   c   =βi   B   (1) 
       
     
     
       
           i   E   =i   C   +i   B   (2) 
       
     
     
       
           i   E =(1+β) i   B   (3) 
       
     
     In the above formulas, β is a constant for a particular transistor, i.e., a common emitter current gain. The value of β can depend on the width of the base region  206  and on the relative doping between the emitter region  208  and the base region  206 . Preferably, the base region  206  is relatively thin, and is doped with an N impurity at low concentration, while the emitter region  208  is doped with a p type impurity at a high concentration. According to equations (1)-(3), the collector current i c  is the product of β and the base current i B , and therefore, the potential at the emitter region  208  is amplified by about β. Therefore, the detection sensitivity can be increased. 
     When charge is transferred to the emitter region  208  the potential at the node N 1  varies from the voltage VOD (provided via the reset transistor) according to the number of signal charges that flow into the emitter region  208 . The potential at the emitter region  208  is supplied to the output circuit  300 , and the corresponding signal voltages are output from the output circuit  300 . The potential at the emitter region  208  can be expressed as:                Δ                 V     =       Δ                 Q     C             (   4   )                                
     where ΔV indicates the potential variation from the potential established by the reset transistor, ΔQ is the amount of charge introduced into the first floating diffusion region  208  and C indicates the sum of the input capacitance of the source follower circuit and the capacitance of the diffusion injection region. 
     According to equation (4), if C is small, ΔV becomes large for a given amount of charge that flows into the emitter  208 . Therefore, the detection sensitivity can be improved by decreasing the total capacitance associated with the floating diffusion regions (the emitter region  208  of the BJT BT 2  and the source region of the FET M 1 ). The total capacitance of the entire floating diffusion region is formed from the capacitance between the emitter region  208  and the substrate  201  (Cs), the capacitance between the emitter region  208  and the output circuit  300  (C 1 ), the capacitance between the source region  210   a  and the reset gate (C 2 ), and the capacitance between the gate electrode and a drain region of a transistor in the output circuit  300  (C 3 ). C 1 , C 2  and C 3  are connected in series in the signal path between the emitter region  208  and the output circuit  300 . The resulting series capacitance is less than the smallest capacitance of capacitances C 1 , C 2 , and C 3 . The addition of the series capacitance associated with the emitter region  208  thus can reduce total capacitance in comparison to conventional devices. 
     FIG. 3 is a circuit schematic diagram of a CCD of FIG.  2 . As shown in FIG. 3, the CCD includes the FET M 1  and the BJT BT 1 . The FET M 1  receives reset lock signals φR at the gate electrode  210   c  and receives voltage levels VOD at the rain region  210   b . The base region  206  of the BJT BT 1  is electrically connected to a transfer circuit  100  and the emitter region  208  is electrically coupled to the source region  210   a  of the FET M 1  and the collector region (substrate  201 ) is grounded. 
     The CCD can include an output circuit  300  which includes NMOS transistors M 2  and M 3  which can provide serially connected channels between a power source voltage level VDD and a ground voltage level VSS. The gate of the NMOS transistor M 2  is electrically coupled to the node N 1  and the emitter region  208  of the BJT BT 1 , while the gate of the NMOS transistor M 3  is electrically coupled to a voltage level Vg applied via a control terminal. Vg preferably is a fixed voltage, e.g., 2V such that the MOS transistor M 3  acts as a resistance element. 
     FIG. 4 is an enlarged cross-sectional view of a second embodiment of a CCD according to the present invention. FIG. 5 is a circuit schematic diagram of a CCD shown in FIG.  4 . As shown in FIG. 4, the CCD includes a horizontal transfer section  100 , the first BJT BT 1 , the first FET M 1 , a second BJT BT 2 , a second FET M 2 , and the output circuit  300 . 
     The horizontal transfer section  100  includes the plurality of gate electrodes  202  on the substrate  201 , which transfer signal charges in response to clock signals φH and output voltages VOG. The first BJT BT 1  and the first FET M 1  are located in a first region  200 - 1  of the substrate  201  adjacent to the output gate electrode  204  which is preferably the last one of the plurality of gate electrodes  202 - 204 . 
     The first BJT BT 1  includes the first base region  206  adjacent to the output gate electrode  204  and the first emitter region  208  within base region  206 . The first FET M 1  includes the drain region  210   b  biased by a power source voltage level VDD or by the drain voltage VOD. The gate electrode  210   c  receives the reset clock signal φR and the source region  210   b  is electrically coupled to the emitter region  208  and to the node N 1 . 
     The second BJT BT 2  and the second FET M 2  are located in a second region  200 - 2  of the substrate  201 . The second BJT BT 2  and the second FET M 2  have structures which are analogous to the respective structures of the first BJT BT 1  and the first FET M 1 . The first emitter region  208  is electrically coupled to a second base region  212  of the second BJT BT 2  so that the emitter current generated by the first BJT BT 1  flows to the second base region  212  of the second BJT BT 2 . 
     When reset clock signal φR 1  is supplied to reset gate electrodes  210   c  and  216   c , the capacitance associated with the gate of the source follower circuit and the floating diffusion regions  208 ,  210   a ,  214  and  216   c  are charged to a the voltage level associated with VOD. Under this condition, the output gate electrode  204  is blocked, and the base and the collector are reverse biased, thereby reducing the signal charges transferred to the base region  208 . Accordingly, current may not flow to the first and second nodes N 1 , N 2 . 
     When the φH clock signals are supplied, the charge signals cross the output gate electrode  204  to first base region  206 . The charge signals flow to the ground as described in equation ( 1 ), thereby generating a first current of βi B  which causes a second current of i B β 2  to be generated by the second BJT BT 2 . 
     According to the present invention, amplifiers are included in CCDs to amplify the potential variation of the floating diffusion regions. Consequently, the signal charge detection sensitivity of the output circuit can be improved. 
     In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.