Abstract:
In this pixel structure, a metal layer/a dielectric layer/a heavily doped silicon layer constitutes a bottom electrode/a capacitor dielectric layer/a top electrode of a storage capacitor. At the same time, a metal shielding layer is formed under the thin film transistor to decrease photo-leakage-current.

Description:
RELATED APPLICATIONS 
   This application claims priority to Taiwan Application Serial Number 96119417, filed May 30, 2007, which is herein incorporated by reference. 
   BACKGROUND 
   1. Field of Invention 
   The present invention relates to a liquid crystal display and a fabrication method thereof. More particularly, the present invention relates to a pixel structure of the liquid crystal display and a fabrication method thereof. 
   2. Description of Related Art 
   In pixel structure of a conventional liquid crystal display (LCD), the bottom electrode of the storage capacitor and the silicon island of the thin film transistor (TFT) are usually made by the same silicon layer. The top electrode of the storage capacitor and the gate electrode of the TFT are usually made by the same metal layer. Since the bottom electrode is covered by the top electrode, implanting dopants into the bottom electrode cannot be effectively performed. Therefore, the capacity of the storage capacitor cannot be effectively increased, and leakage current is easily generated when the transistor is exposed to light. 
   SUMMARY 
   In one aspect of this invention, a pixel structure of a liquid crystal display and a fabrication method thereof are provided. 
   A first metal layer, a first dielectric layer, and a first silicon layer are sequentially formed on a substrate. The first metal layer, the first dielectric layer, and the first silicon layer are then patterned to form an active stack and a capacitive stack respectively on an active area and a capacitive area of the substrate and to form a capacitive line connecting the capacitive stack. A gate dielectric layer and a second metal layer are sequentially formed on the substrate, the active stack, the capacitive stack, and the capacitive line stack. The second metal layer is patterned to form a gate on the active stack and a scan line connecting the gate. The silicon layer of the active stack, the capacitive stack and the capacitive line stack are heavily doped by using the gate and the scan line as a mask to form heavily doped regions. The heavily doped regions on both terminals of the silicon layer in the active stack are respectively source and drain, and the first metal layer and the heavily doped regions are respectively a first electrode and a second electrode of a storage capacitor. 
   A second dielectric layer is formed on the gate dielectric layer, the gate, and the scan line. The second dielectric layer is then patterned to form a first opening, a second opening and a third opening to respectively expose the drain, the source and the second electrode. A third metal layer is formed over the second dielectric layer and in the first, the second and the third openings. Next, the third metal layer is patterned to form a data line, a first conductive line connecting the data line and the source, and a second conductive line connecting the drain and the second electrode. A planar layer is formed on the second dielectric layer, the data line, the first conductive line and the second conductive line and then patterned to form a fourth opening to expose the second conductive line. A transparent conductive layer is formed on the planar layer and in the fourth opening and then patterned to form a pixel electrode connecting the second conductive line. 
   It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
       FIGS. 1A-6B  are diagrams showing a process for fabricating a pixel array for use in an LCD, according to a single-gate embodiment of this invention; and 
       FIGS. 7A-7B  are diagrams showing a process for fabricating a pixel array for use in an LCD, according to a double-gate embodiment of this invention. 
   

   DETAILED DESCRIPTION 
   Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. 
   Single Gate Embodiment 
     FIGS. 1A-6B  are diagrams showing a process for fabricating a pixel array for use in an LCD, according to a single-gate embodiment of this invention. 
     FIG. 1A  is a plan view, and  FIG. 1B  are cross-sectional views of sections AA′, BB′, and CC′. In  FIGS. 1A-1B , a first metal layer, a first dielectric layer, and a silicon layer are sequentially formed on a substrate  100  and then patterned to form an active stack  118   a , a capacitive stack  118   b  and a terminal stack  118   c  respectively on an active area (section AA′), a capacitive area (section BB′), and a terminal area (section CC′). In addition, a capacitive line stack  118   d  is also formed to connect the capacitive stack  118   b  and the terminal stack  118   c  at the same time. The material of the silicon layer can be polysilicon or amorphous silicon, for example. The material of the first dielectric layer can be silicon oxide, for example. 
   The active stack  118   a  is obtained by stacking a metal light-shielding layer  105   a , a first dielectric layer  110   a  and a silicon island  115   a . The metal light-shielding layer  105   a  is made by the first metal layer, and the silicon island  115   a  is made by the silicon layer. The capacitive stack  118   b  is obtained by stacking a first electrode  105   b , a capacitive dielectric layer  110   b  and a silicon layer  115   b . The first electrode  105   b  is made by the first metal layer, and the capacitive dielectric layer  110   b  is made by the first dielectric layer. The terminal stack  118   c  is obtained by stacking a first terminal  105   c , a first dielectric layer  110   c  and a silicon layer  115   c . The first terminal  105   c  is made by the first metal layer. In  FIG. 1A , the capacitive line stack  118   d  above is obtained by stacking the first metal layer, the first dielectric layer and the silicon layer, and only the silicon layer  115   d  on the top can be seen in  FIG. 1A . 
     FIG. 2A  is a plan view, and  FIG. 2B  are cross-sectional views of sections AA′, BB′, and CC′. In  FIGS. 2A-2B , a gate dielectric layer  120  and a second metal layer are sequentially formed on the substrate  100 , the active stack  118   a , the capacitive stack  118   b , the terminal stack  118   c  and the capacitive line stack  118   d . The second metal layer is then patterned to form a gate  125   a  on the active stack  118   a , a scan line  125   b  connecting the gate  125   a , and a second terminal  125   c  connecting the scan line  125   b . Next, the silicon island  115   a , and the silicon layers  115   b ,  115   c ,  115   d  undergo ion implanting process to form heavily doped regions by using the gate  15   a  as the implanting mask. The heavily doped regions in the silicon island  115   a  serve as source  130   a  and drain  130   b . The heavily doped silicon layer  115   b  serves as a second electrode  130   c . The heavily doped silicon layers  115   c  and  115   d  are heavily doped regions  130   d  and  130   e , respectively. Accordingly, the first electrode  105   b  and the second electrode  130   c  constitute a storage capacitor. The material of the gate dielectric layer  120  above can be silicon oxide, silicon nitride, or silicon oxynitride, for example. 
   Optionally, the gate  125   a  with the scan line  125   b , can be further isotropically etched. Then, the reduced gate  125   a  can be served as a mask for lightly doping the silicon island  115   a  to form lightly doped regions  135  between the source  130   a  and the drain  130   b.    
   In  FIG. 3 , a second dielectric layer  140  is formed on the gate dielectric layer  120 , the gate  125   a , the scan line  125   b  and the second terminal  125   c . Next, the second dielectric layer  140  is patterned to form a first opening  145   a , a second opening  145   b , a third opening  145   c  and a forth opening  145   d  to respectively expose the source  130   a , the drain  130   b , the second electrode  130   c , and the heavily doped region  130   d . The material of the second dielectric layer  140  can be silicon oxide, for example. 
     FIG. 4A  is a plan view, and  FIG. 4B  are cross-sectional views of sections AA′, BB′, and CC′. In  FIGS. 4A-4B , a third metal layer is formed on the second dielectric layer  140  and in the first opening, the second opening  145   b , the third opening  145   c  and the forth opening  145   d . The third metal layer is patterned to form a data line  150   b , a third terminal  150   d  at the end of the data line  150   b , a first conductive line  150   a  connecting the data line  150   b  and the source  130   a  via the first opening  145   a , and a second conductive line  150   c  connecting the drain  130   b  (via the second opening  145   b ) and the second electrode  130   c  (via the third opening  145   c ). At the same time, the second metal layer in the fourth opening  145   d  and the exposed heavily doped region  130   d  are removed to expose the first dielectric layer  110   c.    
   In  FIG. 5 , a planar layer  155  is formed on the second dielectric layer  140 , the data line  150   b , the first conductive line  150   a , the second conductive line  150   c , the third terminal  150   d , and in the fourth opening  145   d . The planar layer  155  is then patterned to form a fifth opening  160   a  to expose the second conductive line  150   c  and a sixth opening  160   b  to expose the first terminal  105   c.    
     FIG. 6A  is a plan view and  FIG. 6B  are cross-sectional views of sections AA′, BB′, and CC′. In  FIGS. 6A-6B , a transparent conductive layer is formed on the planar layer  155 , and in the fifth opening  160   a  and the sixth opening  160   b . The transparent conductive layer is patterned to form a pixel electrode  165   a  and a protective layer  165   b  on the first terminal  105   c . The material of the transparent conductive layer can be indium tin oxide, indium zinc oxide, or aluminum zinc oxide, for example. 
   Double Gate Embodiment 
     FIGS. 7A-7B  are diagrams showing a process for fabricating a pixel array for use in an LCD, according to a double-gate embodiment of this invention.  FIG. 7A  is a plan view, and  FIG. 7B  are cross-sectional views of sections AA′, BB′, and CC′. 
   The pixel structure in double gate embodiment is structurally identical (e.g. elements shown in sections BB′ and CC′) to the pixel structure disclosed in single gate embodiment. The only difference is that transistor in the single-gate pixel structure possess single gate, while the transistor in the double-gate pixel structure possess double gates (shown in section AA′). Therefore, elements in double gate embodiment ( FIGS. 7A-7B ) identical to those in single gate embodiment ( FIGS. 1A-6B ) are numbered identically. Furthermore, since the process for fabricating the double-gate embodiment is basically the same as the process for fabricating the single-gate embodiment, the detailed descriptions of the double-gate embodiment is omitted and only the transistor&#39;s structure is discussed below. 
   In  FIG. 7A , the active stack  118   a  of the transistor is bent to overlap with the gate  125   a  and the scan line  125   b  to form a double gate structure. In section AA′ of  FIG. 7B , gate  125   a , overlapped portion of the scan line  125   b , source  130   a , drain  130   b , and heavily doped region  130   f  constitute the double-gate transistor. In addition, lightly doped regions  135  can be formed on both sides of the gate  125   a  and the overlapped portion of the scan line  125   b.    
   Accordingly, the bottom electrode, i.e. the first electrode  105   b , of the storage capacitor is made by metal, and the upper electrode, i.e. the second electrode  130   c , is made by heavily doped silicon layer. Hence, compared with a conventional capacitor composed of non-doped silicon layer, gate dielectric layer, and metal, the storage capacity is greatly increased. Moreover, a metal light-shielding layer is under the transistor to reduce the light-induced leakage current. 
   It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.