Abstract:
A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material; and sintering the ceramic material. A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material so that the ceramic material is disposed between the first conductive material and the second conductive material; thermal processing at a temperature sufficient to sinter the ceramic material and form a film of the second conductive material; and coating an exposed surface of at least one of the first conduct material and the second conductive material with a different conductive material. An apparatus including first and second electrodes; and a ceramic material between the first electrode and the second electrode, wherein the ceramic material is sintered directly on one of the first and second electrode.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is a divisional application of U.S. patent application Ser. No. 10/971,829, filed Oct. 21, 2004, issued as U.S. Pat. No. 7,290,315 on Nov. 6, 2007. 

   FIELD 
   Circuit structures and passive devices. 
   BACKGROUND 
   It is desirable to provide decoupling capacitance in a close proximity to an integrated circuit chip or die. The need for such capacitance increases as the switching speed and current requirements of chips or dies becomes higher. Thus, the need for a high number of passive components for high density integrated circuit chips or dies, the resultant increasing circuit density of printed wiring boards (PWB), and a trend to higher frequencies in the multi-gigaHertz range are among the factors combining to increase pressure on passive components surface-mounted on package substrates or PWBs. By incorporating embedded passive components (e.g., capacitors, resistors, inductors) into the package substrate or PWB, improved performance, better reliability, smaller footprint, and lower cost can be achieved. 
   Capacitors are the predominant passive component in most circuit designs. Typical materials for suitable embedded capacitor components, such as polymer and high-dielectric constant (high-k) ceramic powder composites or high-k ceramic powder and glass powder mixtures, are generally limited to a capacitance density on the order of nanoFarad/cm 2  and 0.1 microFarad/cm 2 . Attempts have been made to embed thin film capacitors into organic substrates, such as utilizing ceramic fillers in polyimide or epoxy resins in thin laminate form. However, processing and handling of thin-core laminates has proved to be difficult. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Features, aspects, and advantages of embodiments will become more thoroughly apparent from the following detailed description, appended claims, and accompanying drawings in which: 
       FIG. 1  shows a cross-sectional schematic side view of an embodiment of a chip or die package suitable for mounting on a printed circuit or wiring board. 
       FIG. 2  shows a cross-sectional schematic side view of the package substrate of  FIG. 1 . 
       FIG. 3  describes a process flow for forming an embedded capacitor. 
       FIG. 4  shows a schematic side view of a first conductor sheet having a layer of conductive material formed thereon. 
       FIG. 5  shows a ceramic powder deposited on the first conductor sheet of  FIG. 4 . 
       FIG. 6  shows a schematic side view of a second conductor sheet having a layer of conductive material formed thereon. 
       FIG. 7  shows the structure of  FIG. 5  with the first conductor ( FIG. 4 ) and the second conductor ( FIG. 6 ) connected to opposite sides of a ceramic material. 
       FIG. 8  shows the structure of  FIG. 7  after sintering and having an overlay of conductor material on the first conductor and the second conductor. 
   

   DETAILED DESCRIPTION 
     FIG. 1  shows a cross-sectional side view of an integrated circuit package that can be physically and electrically connected to a printed wiring board or printed circuit board (PCB) to form an electronic assembly. The electronic assembly can be part of an electronic system such as a computer (e.g., desktop, laptop, hand-held, server, etc.), wireless communication device (e.g., cellular phone, cordless phone, pager, etc.), computer-related peripheral (e.g., printers, scanner, monitors, etc.), entertainment device (e.g., television, radio, stereo, tape and compact disc player, videocassette recorder, MP3 (Motion Picture Experts Group, Audio Layer 3) player, etc.), and the like.  FIG. 1  illustrates the package as part of a desktop computer. 
     FIG. 1  shows electronic assembly  100  including die  110  physically and electrically connected to package substrate  101 . Die  110  is an integrated circuit die, such as a processor die. Electrical contact points (e.g., contact pads on a surface of die  110 ) are connected to package substrate  101  through conductive bump layer  125 . Package substrate  101  may be used to connect electronic assembly  100  to printed circuit board  130 , such as a motherboard or other circuit board. 
   In one embodiment, package substrate  101  includes one or more capacitor structures. Referring to  FIG. 1 , package substrate  101  includes capacitor structure  140  and capacitor structure  150  embedded therein. Capacitor structure  140  and capacitor structure  150  are connected to opposite sides of core substrate  160 . In one embodiment, core substrate  160  is an organic core such as an epoxy including a fiberglass reinforced material, also called pre-preg. This configuration may be referred to as an integrated thin film capacitor (iTFC) system, where the capacitor(s) is(are) integrated into the package substrate rather than, for example, an interposer between the die and the package substrate. Overlying capacitor structure  140  is adhesion layer  175  (e.g., a pre-preg material). Underlying capacitor structure  150  is adhesion layer  185 . Overlying adhesion layer  175  is build-up layer  176 . Underlying adhesion layer  185  is build-up layer  186 . Adhesion layer  175  and adhesion layer  185  act as adhesion layers to the overlying and underlying build-up layers  176  and  186 , respectively. Each build-up layer includes traces (e.g., copper traces) for lateral translation of contact points between die  110  and package substrate  101 , and package substrate  101  and printed circuit board  130 , respectively. The region made up of the combination of layers,  185 ,  150 ,  160 ,  140  and  175 , is referred to herein as functional core  120 . 
     FIG. 2  shows a magnified view of a portion of functional core  120 . Functional core  120  includes core substrate  160  and having a thickness, in one embodiment, on the order of 200 microns (μm) to 700 μm. In another embodiment, core substrate  160  has a thickness on the order of 200 μm to 300 μm. In one embodiment, core substrate  160  includes core  162 , such as a glass-fiber reinforced epoxy, and shell  165 , such as a silica-particle filled epoxy. In another embodiment, core substrate  160  includes only core  162 . 
   Capacitor structure  140  is connected to one side of core substrate  160  (a top side as viewed). Capacitor structure  140  includes first conductor  210  proximal to core substrate  160  and second conductor  230 . Disposed between first conductor  210  and second conductor  230  is dielectric material  220 . Capacitor structure  150  is connected to an opposite side of core substrate  160  (a bottom side as viewed) and has a similar configuration of a dielectric material disposed between two conductors. Overlying capacitor structure  140  and capacitor structure  150  of functional core  120  (on sides opposite sides facing core substrate  160 ) is adhesion layer  175  and adhesion layer  185 , respectively, made of, for example, an organic material and having a representative thickness on the order of 10 microns (μm) to 50 μm. Build-up layer  176  and build-up layer  186  of  FIG. 1  would be deposited on these adhesion layers. As noted above, the build-up layers may include traces and contact points to connect package substrate to a chip or die and to a printed circuit board, respectively. 
   In one embodiment, first conductor  210  and second conductor  230  of capacitor structure  140  are electrically conductive material. Suitable materials include, but are not limited to, a nickel or a copper material. In one embodiment, dielectric material  220  is a ceramic material having a relatively high dielectric constant (high-k). Representatively, a high-k material is a ceramic material having a dielectric constant on the order of 100 to 1,000. Suitable materials for dielectric material  220  include, but are not limited to, barium titanate (BaTiO 3 ), barium strontium titanate ((Ba, Sr)TiO 3 ), and strontium titanate (SrTiO 3 ). 
   In one embodiment, capacitor structure  140  includes first conductor  210  and second conductor  220  having a thickness on the order of 20 μm to 50 μm, and dielectric material  220  of a high-k ceramic material of a thickness on the order of 1 μm and, in another embodiment, less than 1 μm. Capacitor structure  150 , in one embodiment, is similar to capacitor structure  140 . 
   In the embodiment of functional core  120  shown in  FIG. 2 , capacitor structure  140  includes overlayer  240  on second conductor  230 . Overlayer  240  is an optional electrically conductive layer that may be used in an instance where second conductor  230  is a material that may not be compatible or may be less compatible with materials or processing operations to which functional core  120  may be exposed. For example, in one embodiment, second conductor  230  is a nickel material. To render functional core  120  transparent to subsequent processing operations or compatible with materials to which functional core  120  may be exposed, overlayer  240  is a copper material. Representatively, overlayer  240 , if present, may have a thickness on the order of a few microns. 
     FIG. 2  shows a number of conductive vias extending through functional core  120  between surface  280  and surface  290 . Representatively, conductive via  250  and conductive via  260  are electrically conductive materials (e.g., copper or silver) of suitable polarity to be connected to power or ground contact points of die  110  (e.g., through conductive bump layer  125  to contact pads on die  110  of  FIG. 1 ). In this manner, conductive via  250  and conductive via  260  extend through capacitor structure  140 , core substrate  160 , and capacitor structure  150 . Conductive vias  250  and  260  may be insulated, where desired, from portions of capacitor structure  140  or capacitor structure  150  by sleeves  270  of a dielectric material. 
     FIG. 3  presents a process for forming a package substrate, such as package substrate  120 . In one embodiment, capacitor structure such as the capacitor structure  140  and capacitor structure  150  are formed and then separately connected to core substrate  160 .  FIGS. 4-8  show formation processes in connection with portions of the process flow described in  FIG. 3 , notably an embodiment of forming a capacitor structure. 
   In one embodiment of forming a capacitor structure of a package structure, a sheet (e.g., foil) of a first conductor material is provided as an initial substrate. Representatively, a sheet (e.g., foil) of nickel having a desired thickness is provided. Representative thickness are on the order of several microns to tens of microns depending on the particular design parameters. In one embodiment, the nickel sheet would be a standard rolled or plated nickel sheet. The dimensions of a sheet suitable as a first conductor may vary depending, for example, on the requirements of board shops involved in their production. For example, it may be desirable to process a sheet having a length and width dimension on the order of 200-400 millimeters from which a number of capacitor structures can be singulated. Individual capacitor could have sizes varying between silicon die dimensions to substrate dimensions. 
   Directly onto a surface of the first conductor, a ceramic material is deposited as a green sheet dielectric material (block  310 ). Representatively, ceramic powder particles may be deposited onto a surface, including an entire surface of a first conductor sheet or foil. In one embodiment, it is desired to form a dielectric layer of high-k material having a thickness on the order of one micron, ceramic powder particles having an average diameter on the order of 0.05 μm to 0.3 μm are deposited on the first conductor layer. In another embodiment, where a thickness of a dielectric layer is less than one micron, smaller ceramic powder particles are utilized. For example, to form a dielectric layer having a thickness on the order of 0.1 μm to 0.2 μm, grains having a grain size of 30 nanometers (nm) to 40 nm are appropriate. 
     FIG. 4  shows structure  425  made up of a first conductor  410  of, for example, a nickel sheet or foil having layer  420  of nickel paste on a surface of first conductor  410  (a top surface as viewed). In one embodiment nickel paste layer  420  of  FIG. 4  will have barium titanate powder additions in order to provide a adhesion layer between the underlying nickel foil and the soon-to-be-deposited overlying barium titanate green sheet. 
     FIG. 5  shows structure  435  with ceramic layer  430  having a high dielectric constant (e.g., BaTiO 3 ) deposited on structure  425 . Ceramic layer  430  or green sheet in one embodiment is laminated on underlying Ni paste layer  420 . 
     FIG. 6  shows structure  455  similar to structure  425  shown in  FIG. 4 , including second conductor (e.g., a nickel sheet or foil)  440  having layer  450  of nickel paste formed thereon. Nickel paste-nickel foil laminate  455  would be subsequently laminated on top (as viewed) of structure  435  in order to form structure  475  in  FIG. 7 . In one embodiment, following lamination, structure  475  is thermally treated to burn-off organic contents. Representatively, a thermal treatment would involve a temperature range of 300 to 500° C. for a duration of between two hours and a day. 
   Referring again to  FIG. 3 , following the formation of a high-k dielectric material between conductor materials, the composite structure is subsequently heat-treated in a reducing atmosphere in order to densify (e.g., reduce the surface energy of) barium titanate green sheet and nickel paste layers simultaneously. Once this heat treatment is completed, the product will have sufficient strength for packaging and handling purposes, and will have sufficiently dense microstructure, with very little amount of porosity, resulting in a ceramic having a high dielectric constant.  FIG. 7  shows composite structure  475  including ceramic layer  430  disposed between first conductor  410  and layer  420 , and layer  440  and second conductor  450 . 
   Following heat treatment, the method of  FIG. 3  provides that one or both of layer  410  and layer  440  are coated with a different electrically conductive material.  FIG. 8  shows structure  495  where two copper layers have been deposited on top and bottom surfaces of the structure  475 , respectively. Copper layer  460  and copper layer  470  are deposited, in one embodiment, through electroless deposition. Subsequent copper layers  480  and  490  are subsequently deposited on respective surfaces of copper layer  460  and copper layer  470  by electroplating. Copper overlayers  480  and  490  may have a thickness on the order of a few microns. Alternatively, a copper layer may b e formed by depositing copper paste including copper particles and sintering the paste. 
   Copper coating may be desirable to make the capacitor structure transparent to subsequent processing operations to which the capacitor structure or the package substrate may be exposed. In the example where first conductor  410  and second conductor  450  are a nickel material, for example, it may be desirable to coat an exposed surface of the first or second conductor with a copper material. 
   Referring to technique or method  300  of  FIG. 3 , the capacitor structure may be attached to a core substrate, such as an organic core substrate as discussed above (block  350 ). In the example where a copper layer overlays a conductor, the copper surface may need to be roughened (e.g., by etching) in order to enhance lamination. The capacitor structure may be attached to one surface of the base substrate. A separate capacitor structure formed in a similar manner could be laminated to another surface, such as shown above in  FIG. 2  and described in the accompanying text. 
   Following laminating of one or more capacitor structures to a core substrate, the package substrate may be patterned (block  360 ). Conventional patterning operations, such as mechanical drilling, drilling via holes in epoxy with laser, lithography and copper plating operations used in via formation may be employed. The capacitor structure may also be patterned to form individual capacitors. A complete organic substrate may be formed by adding build-up layers of an organic material (e.g., epoxy or glass particle-filled epoxy) onto the substrate. 
   The above description is related to forming capacitor structures within package substrates. Similar techniques may be used in the formation of capacitors in other environments, such as in printed wiring boards (e.g., printed circuit boards). The techniques described avoid a processing operation whereby ceramic and conductor powder pastes are deposited on carrier sheets and laminated to one another (such as in traditional manufacturing multi layer ceramic capacitors (MLCC). Instead, the ceramic and possibly both conductor materials are formed directly on one another. 
   In the preceding detailed description, reference is made to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.