Abstract:
A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 12/367,216, which was filed on Feb. 6, 2009, which is scheduled to issue as U.S. Pat. No. 8,619,485 on Dec. 31, 2013. which is a continuation of U.S. patent application Ser. No. 10/796,111, which was filed on Mar. 10, 2004, which issued as U.S. Pat. No. 7,583,551 on Apr. 17, 2007, the disclosures of which are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates generally to memory, and more particularly controlling memory refresh operations in memory. 
     BACKGROUND OF THE INVENTION 
     An essential data processing component is memory, such as a random access memory (RAM). RAM allows the user to execute both read and write operations on memory cells. Typically, semiconductor RAM devices are volatile, in that stored data is lost once the power source is disconnected or removed. Typical examples of RAM devices include dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) and static random access memory (SRAM). 
     In recent years, the memory capacity, i.e., the number and density of memory cells in memory devices have been increasing. Accordingly, the size of each cell (including storage capacitor size) has been shrinking, which also shortens the cell&#39;s data holding time. Typically, each row in a memory device receives a stabilizing refresh command in the conventional standardized cycle, about every 64 milliseconds. However, with increasing cell number and density, it is becoming more and more difficult to stabilize all memory cells at least once within the stabilizing cycle, e.g., it requires more power as well as a significant portion of the available bandwidth. 
     DRAMS and SDRAMs are volatile in the sense that the stored data, typically in the form of charged and discharged capacitors contained in memory cells arranged in a large array, will dissipate the charge after a relatively short period of time because of a charge&#39;s natural tendency to distribute itself into a lower energy state. DRAM is particularly volatile in that each cell should be stabilized, i.e., refreshed, typically every 64 milliseconds, in order to retain information stored on its memory cells. 
     Recently, studies have been conducted on the use of chalcogenide glasses as ionic conductors which can be used to build non-volatile memory cells. One such non-volatile memory device, which uses chalcogenide glass to form non-volatile memory cells is known as a programmable conductor RAM (PCRAM). See, for example, U.S. Patent publication number 2002/0123248. 
     Although referred to as non-volatile memory elements, the PCRAM memory elements are more accurately nearly non-volatile memory (“NNV memory”). The NNV memory elements do require periodic refreshing, although the refreshing operations occur significantly more infrequently than refresh operations in standard volatile DRAM or SDRAM memory elements. Once a refreshing operation is complete, a memory device incorporating the NNV memory elements can be placed into an extremely low power state until either the system is returned to a normal operating state or until another refreshing operation is required. 
     A memory system may comprise many memory devices. Although the amount of time allotted to a refresh operation is conventionally pre-determined and therefore static, each memory device may require a different amount of time to complete the refresh operation. The difference in the amount of time required for a refresh operation is caused by a variety of factors. For example, the difference may stem from inaccuracies and inefficiencies in the performance of a refresh operation, or it may be caused by differences in memory architectures of a memory device. Furthermore, the time a device requires for a refresh operation may vary due to various factors, such as amount of memory that needs refreshing. For example, if a refresh operation is performed as a burst operation, with all cells in all devices being refreshed in a series of sequential operations, even a small variation of individual cell refresh times accumulates into significant differences in the refresh times for the entire device containing the individual cells. 
     The time allotted to perform a refresh operation is generally set at the maximum amount of time the devices could require to perform the refresh operation. Otherwise, if the time period is set too short, some devices may not complete the refresh operation before the time period expires. Thus, there is wasted time when the amount of time required for a refresh operation is shorter than the pre-determined, allotted refresh operation time. 
     Similarly, the frequency of refreshing a memory system is conventionally static and predetermined. However, many factors affect the minimum frequency necessary to ensure retention of stored information. For example, in a memory system that includes NNV memory elements, ambient temperature affects the volatility of the NNV memory elements—the ambient temperature affects the ability of the memory elements to retain a stored state. 
     It would be advantageous to have memory refresh techniques that reduce wasted time. 
     BRIEF SUMMARY OF THE INVENTION 
     Exemplary embodiments of the present invention provide memory refresh and power management circuitry whose operation can be affected by dynamic factors. The circuitry can also reduce time delays in refresh operations. The various embodiments of the invention may be used with any memory requiring refresh. 
     Rather than allotting a pre-determined amount of time to complete the refresh operation, the memory refresh circuitry of an exemplary embodiment provides a refresh complete signal indicating when a burst self-refresh operation is complete. In a system with multiple memory devices, the refresh complete signals from the devices are combined. A power management circuit receives the refresh complete signal when the refresh operation has been completed. 
     In another exemplary embodiment of the invention, a memory system monitors a condition, such as ambient or internal temperature, and initiates refresh operations based on the temperature. The system can include a circuit monitoring the ambient and internal temperatures, and the refresh circuitry can initiate a refresh operation in response. The refresh circuitry initiates a refresh operation based on either established set temperature points or the integration of temperature. 
     Another exemplary embodiment of the invention is a combination of the embodiments described above. For example in this exemplary embodiment, a memory system provides memory refresh circuitry whose operation can be affected by dynamic factors and monitors a condition, such as ambient or internal temperature, and initiates refresh operations based on the temperature. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which: 
         FIG. 1  depicts a block diagram of a memory system in accordance with an exemplary embodiment of the invention; 
         FIG. 2  shows a block diagram of a memory device in  FIG. 1  in greater detail in accordance with an exemplary embodiment of the invention; 
         FIG. 3  shows a block diagram of the refresh counter of  FIG. 2  in greater detail; 
         FIG. 4  shows a block diagram of the power management controller of  FIG. 1  in greater detail in accordance with an exemplary embodiment of the invention; 
         FIG. 5  shows a block diagram of the power management controller of  FIG. 1  in greater detail in accordance with another exemplary embodiment of the invention; 
         FIG. 6  shows a memory system as in  FIGS. 1-5  integrated on a semiconductor chip; and 
         FIG. 7  shows a memory system as in  FIGS. 1-5  integrated in a processing system. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or procedural changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention. 
       FIG. 1  depicts a memory system  510  in accordance with an exemplary embodiment of the invention. Memory system  510  includes a memory controller  520 , memory devices  530 , memory bus  540 , power management controller  550 , resistor  552 , system controller  559 , logic power supply  553 , and memory power supply  555 . Although shown with four (4) memory devices  530 , memory system  510  can have any number of memory devices  530 . Memory systems with larger numbers of memory devices  530 , may require additional circuit, for example, the system may require multiple memory buses  540  and memory power supplies  555 . A memory device  530  is described in greater detail below. The memory controller  520  is coupled to the memory devices  530  through memory bus  540 . Through the memory bus  540 , the memory controller  520  exchanges data and control signals with memory devices  530 . For example, memory controller  520  provides a command indicating that data is to be written to a certain location of a particular memory device  530 . Further, memory controller  520  also provides a command indicating when a memory device  530  should perform a refresh operation, or enter a standby self-refresh mode of operation. Data and other signals from memory devices  530  are provided to different parts of the memory system  510  through memory bus  540 . Although the memory controller  520  is depicted as being incorporated into system controller  559 , other implementations of the memory controller  520  and system controller  559  are possible. 
     As seen in  FIG. 1 , memory devices  530  are coupled to a memory power supply  555  (Vdd3) through line  557 . Power supply  555  provides power to each memory device  530 . Although shown as a single line in  FIG. 1 , line  557  is representative of several power lines that may couple the power supply  555  to a memory device  530 . In implementation, multiple lines  557  are used for different power plane paths, where each line  557  is associated with a respective power plane. There may be a single or multiple power plane paths to each memory device  530 . 
     Power management circuit  550  is coupled to memory power supply  555  and controls the supply voltage and therefore power provided to each memory device  530 . Further, power management circuit  550  controls the power supplied to each memory device  530  on each power plane through each line  557 . Power management circuit  550  is coupled to and exchanges control signals with system controller  559 /memory controller  520  and other system components through communications bus  560 . Power management circuit  550  is discussed in greater detail below. 
     The power management circuit  550  is coupled to memory devices  530  through line  551  to each memory device  530 . The pullup resistor  552  is also coupled to line  551  and line  557 . Through line  551  power management circuit  550  receives a “refresh complete” signal from the memory devices  530  indicating that the memory devices  530  have completed a burst self-refresh operation. The refresh complete signal is advantageous, especially for NNV memory devices, because it allows for improved refresh operations, as described below. In an exemplary embodiment, line  551  carries a signal to power management circuit  550  indicating first and second states. In the first state, the signal carried on line  551  indicates to the power management circuit  550  that the burst self-refresh operation is under way. In a second state, the signal carried on line  551  indicates to the power management circuit  550  that the burst self-refresh operation is no longer under way, i.e., the burst self-refresh operation is completed. 
     In one embodiment of the invention, described below in relation to  FIG. 1 , the signal carried on line  553  is either at a supplied voltage level Vdd3 or the signal is at or near signal ground. The Refresh Complete outputs of all of the memory devices  530  on lines  551  are in effect logically ORed to provide a signal on line  551  indicating whether any of memory devices  530  is currently performing burst self-refresh, a configuration referred to as “wired-OR” or “dynamic OR.” Each memory device  530  can selectively couple line  551  to signal ground thus pulling it down from Vdd3. If any of the memory devices  530  couples line  551  to signal ground, then the signal on line  551  received by the power management circuit  550  is at or near signal ground, indicating that a refresh operation is currently underway. If none of the memory devices  530  couple line  551  to ground, resistor  552  pulls down the refresh complete line  551  to the voltage on Vdd3 and the signal on line  551  received by the power management circuit  550  will be approximately Vdd3, indicating that all memory devices  530  have completed their burst self-refresh operation. 
       FIG. 2  depicts a portion of the memory device  530  of  FIG. 1  in greater detail. Memory device  530  includes a control logic circuit  610 , a memory array  620 , an address multiplexer  630  and a refresh counter  605 . Although shown with only one representative memory array  620 , memory device  530  can include any number of memory arrays  620 . Although shown with representative elements, memory device  530  may include additional memory or logic circuits not shown or described. Control logic circuit  610  controls access to the memory array(s)  620 , and more specifically to the storage elements of the memory array  620 . Although not shown, control logic  610  receives control signals from memory controller  520  ( FIG. 1 ), which indicate the memory operation to occur, e.g., a read, write, or refresh operation. Further, the control logic  610  receives control signals from refresh counter  605  during a self-refresh or burst self-refresh operation. Further, the memory controller  520  ( FIG. 1 ) provides a desired memory address to the memory device  530  ( FIG. 2 ) which in turn is provided through multiplexer  630  to the memory array  620  to enable and control access to desired memory element(s) of the memory array  620 . The memory address provided by the memory controller  520  is either multiplexed or un-multiplexed. If the address is multiplexed, it may be multiplexed with itself and/or with other signal lines, including, but not limited to, the data lines of the device as is conventionally known. 
     Control logic  610  provides a signal to the address multiplexer  630  to indicate the source of the inputted address that is provided to access a row in the memory array  620 . For example, in a first, standard operational mode, the address multiplexer  630  provides row addresses received from an outside circuit, e.g., the memory controller  520  ( FIG. 1 ), to the memory array  620 . In a second, refresh operation mode, the address multiplexer  630  provides row addresses received from the refresh counter  605  to the memory array  620 . During the refresh operation, control logic  610  also provides signals to sense/refresh components of memory array  620  so that the value stored in a complete row of addressed memory elements is sensed and refreshed. Column addresses and column decoding are not shown or described with respect to  FIG. 2 , but are well known by those with skill in the art. 
     Refresh counter  605  ( FIG. 2 ) controls the operation of its associated memory device  530  by providing a single address during a single self-refresh cycle or a series of addresses during a burst self-refresh operation. The addresses can be obtained by incrementing the refresh counter  605  at the completion of a refresh cycle to the memory array  620 . The control logic circuit  610  may receive commands from the memory controller  520  ( FIG. 1 ) indicating that a refresh operation should begin. These commanded refresh cycles may occur as in standard dynamic random access memory (DRAM) devices that are currently available. In a preferred embodiment of the invention, a burst self-refresh operation is included, which allows the entire memory array to be refreshed by a single command. A value of the refresh circuit  605  corresponds to an address in the memory array  620 . For a commanded burst self-refresh operation, the refresh counter  605  is automatically reset to a value corresponding to the first row in a memory array  620 , which is then refreshed. The value in the refresh counter  605  is incremented for each refresh of a row in the memory array  620  until the maximum value of the refresh counter  605  is reached. When the value of the refresh counter  605  is the maximum value then all of addresses of the memory array  620  will have been refreshed. 
     The automatic burst self-refresh operation is initiated by the control logic  610  as it senses certain conditions. These conditions may include, for example, time or temperature factors. For example, the condition of all inputs to the control logic  610  being held near signal ground would indicate to the control logic  610  the condition for an automatic burst self-refresh. During a burst self-refresh, refresh counter  605  is initially reset and will pull the signal on line  551  to ground. Following the refresh of each row of the memory array  620  the refresh counter  605  is incremented. The value of refresh counter  605  is provided as a row address to the address multiplexer  630  to access a row of the memory array  620  that is to be refreshed. For example, in operation, the refresh counter  605  first provides an address corresponding to the first row of the memory array  620  to the address multiplexer  630 . After each row of the memory array  620  has been refreshed, the refresh counter  605  provides a new address corresponding to the next row of the memory array  620 . When the memory array  620  has completed a refresh operation, e.g., all the elements of the memory array  620  have been refreshed, the refresh counter  605  will overflow, indicated by the release of signal on line  551 , allowing it to return to Vdd3 if all other memory devices  530  have completed the refresh operation. This provides a signal to the power management circuit  550  ( FIG. 1 ) indicating that the refresh operation is complete in all of the memory devices  530 . 
       FIG. 3  depicts an implementation of the refresh counter  605  of  FIG. 2  in greater detail. Refresh counter  605  includes an address and control counter circuit  695  and a refresh complete circuit  615 . Address and control counter circuit  695  is coupled to the refresh complete circuit  615 , the control logic circuit  610  ( FIG. 2 ), and the address multiplexer  630  ( FIG. 2 ) and also receives a clock signal. As is conventionally known, address and control circuit  695  provides and receives control signals from control logic  610  including a reset signal as shown, and provides address signals (used for a refresh operation) to address multiplexer  630 . Address and control circuit  695  provides a signal to the refresh complete circuit  615  indicating the status of the burst self-refresh operation. Address and control circuit  695  can therefore be implemented as a conventional counter or other suitable circuitry that can reset a count to zero, provide the count as an address, increment the count to the next address in response to a clock signal, and provide a signal on line  616  when the count reaches a maximum address value. 
     In an exemplary embodiment of the present invention, refresh complete circuit  615  includes a switch  617 , e.g., a transistor, where the source region of the transistor is coupled to signal ground through line  618 . The drain region of switch  617  is coupled to line  551 . When transistor switch  617  is closed, or turned on, line  551 , is coupled to signal ground through line  618 . When switch  617  is open, line  551  is isolated from signal ground through line  618 . 
     Line  616  can control switch  617  based on the value in a counter  696  in circuit  695 . For example, line  616  indicates when the maximum value of the N-bit refresh counter  696  has been reached, i.e., when all of the addresses have been refreshed. In a preferred embodiment, when a burst self-refresh operation is underway in the memory device  530 , the flip-flop  697  output Q will be off, and output Q* will be on, and line  616  can close switch  617 , coupling line  553  to ground. When the burst self-refresh operation has been completed in the memory device  530 , as indicated by the maximum value being reached in the counter  696 , the flip-flop  697  output Q will be on, and output Q* will be off, and line  616  can open switch  617 , not coupling line  553  to ground. Thus, memory device  530  provides a signal indicating whether its burst self-refresh operation has been completed by either coupling line  553  to ground or not coupling line  553  to ground. In one embodiment, refresh complete circuit  615  is an open drain comprised of an N-channel MOSFET whose source is tied to ground, e.g., VSS, and whose drain is tied to line  553  ( FIG. 1 ) through line  551 . 
       FIG. 4  shows an implementation of the power management controller  550  of  FIG. 1  in greater detail. Power management controller  550  includes a microcontroller  680 , bus  640 , I/O ports  650 , ROM  660 , RAM  670 , and inter IC ( 12 C) interface  690 . Microcontroller  680  controls the operation of the power management controller  550  based on predetermined, preprogrammed criteria. Bus  640  couples I/O ports  650 , ROM  660 , RAM  670 , and inter IC ( 12 C) interface  690  enabling these devices to exchange data and control signals. I/O ports  650  provide input and output connections to other devices and signals. For example, an output is coupled to a memory power plane controller (not shown) within the power supply  555  ( FIG. 1 ) to enable the power management controller  550  to control the supply voltage provided to a memory device  530 . If a memory system  510  has more than one memory power plane, the power management controller  550  is coupled to the memory power plane controller for each power plane within the power supply  555 . 
     As seen in  FIG. 4 , the power management controller  550  includes storage areas ROM  660  and RAM  620 . Further, the power management controller  550  includes an inter IC ( 12 C) interface  690  to permit coupling the power management controller  550  to another IC bus (or busses). Most often such a bus will allow communication with a main system processor. 
     A burst self-refresh operation of a NNV memory device(s)  530  may be initiated during a time when the system is in a standby, power-saving mode. The burst self-refresh capability allows most of the memory system to remain in a power-down state while the burst self-refresh operation occurs. During an operation to burst self-refresh a memory device  530 , the power management controller  550  provides a signal to the memory power supply  555  indicating that power should be provided to memory device(s)  530  or a particular memory power plane coupled to memory device(s)  530 . Further, the control logic  610  ( FIG. 2 ) of each memory device  530  will detect the conditions indicating that a refresh operation should occur. The control logic  610  ( FIG. 2 ) provides a reset signal pulse to the refresh counter  605  and begins performing refresh operations. 
     The refresh counter  605  provides addresses for refresh operation of memory array  620  ( FIG. 2 ) through address multiplexor  630  ( FIG. 2 ) and is incremented after receiving the appropriate clock signal from control logic  610 . When the refresh operation is completed, memory device  530  provides its ‘refresh complete’ signal by releasing its line  551  ( FIG. 3 ). If memory device  530  is the last memory devices  530  to complete a refresh operation or if only one memory device  530  is being refreshed, line  551  returns to Vdd3, providing a refresh complete signal to I/O port  650 . When the power management controller  550  receives the refresh complete signal through I/O port  650 , the power management controller  550  returns the memory devices  530  and power supply  555  to the power-off state. 
     A memory system in a higher power setting does not require burst self-refresh and may be refreshed through conventional refresh cycles as understood by those with skill in the art. 
     Power management circuit  550  differs from conventional power management circuits in that power management circuit  550  receives a refresh complete signal that indicates when all the memory devices  530  have completed refreshing their respective memory arrays  620 . In one embodiment, a refresh complete signal is received through I/O ports  650 . Although referred to as a single signal, the refresh complete signal received can be at least two different voltages signifying different statuses. A first signal indicates that a refresh operation has been completed (i.e., ‘refresh complete’ signal) and the second signal indicates that a refresh operation in progress has not been completed (i.e., ‘refresh not complete’ signal). Systems with multiple memory planes may have a refresh complete signal for each memory plane. 
     Power management circuit  550  also differs from conventional power management circuits in that the microcontroller  680  is programmed to respond to the dynamic input of the refresh complete signal. Rather than waiting a predetermined time period to return the memory to its state prior to initiating the memory refresh operation, microcontroller  680  waits until it receives a refresh complete signal and then returns the memory to its state prior to initiating the memory refresh operation. Thus, the memory system responds dynamically to the completion of a memory refresh operation and can reduce the amount of time between the completion of a memory refresh operation and the return of the memory to its state prior to initiating the memory refresh operation. This is desirable because it allows a non-static time for the refresh operation as may be required due to the nature of the NNV memory technology, and can reduce wasted time by reducing or eliminating time delay after completion of a refresh operation before power management is initiated. 
     In another exemplary embodiment of the present invention, the initiation of a refresh operation is done dynamically.  FIG. 5  depicts the power management controller  850 . Similar to power management controller  550  ( FIG. 4 ), power management controller  850  includes a microcontroller  880 , bus  640 , I/O ports  650 , ROM  660 , RAM  670 , and inter IC ( 12 C) interface  690 . Further, power management controller  850  includes a temperature integrator  892  and may include optional internal and external temperature sensors  893 ,  894 . 
     Power management circuit  850  differs from power management circuit  550  in that the microcontroller  880  is programmed to respond to the input of the temperature integrator  892 . In addition to other events that cause a burst self-refresh operation to occur in the memory device  530 , microcontroller  880  is adapted to receive a signal from the temperature integrator  892  indicating that a burst self-refresh operation should occur. In other words, microcontroller  880  dynamically determines frequency of burst self-refresh operations, based on factors such as ambient or internal temperature or other conditions occurring during memory system operation. 
     Temperature integrator  892  provides a signal indicating that a burst self-refresh operation should occur based on predetermined criteria. In an aspect of the exemplary embodiment of the invention, the temperature integrator  892  receives temperature sensor signals from an internal temperature sensor  893 , an external temperature sensor  894 , or both an internal and external temperature sensor  893 ,  894 . An external temperature sensor  894  is located off of the memory device  530  and measures the ambient temperature conditions. An internal temperature sensor  893  is located on the memory device  530  and measures the temperature conditions within the memory device  530 . In another embodiment the internal temperature sensor  893  is incorporated into the memory device  530 . In another embodiment, the temperature sensor  893  integrated into the power management control. 
     Temperature may affect different NNV memory differently; hence, each NNV memory may require a memory refresh operation at a different temperature based on the effects of temperature on memory elements. In one embodiment, the temperature integrator  892  is preprogrammed to require differing rates of refresh operation at predetermined temperatures, e.g., trip points measured by one of the temperature sensors  893 ,  894 . For example, when one of the temperature sensors  893 ,  894  indicates 80 degrees Celsius, then the temperature integrator  892  provides a signal to the microcontroller  880  that refresh operations should be initiated at a different rate than for temperatures below 80 degrees Celsius. Similarly, in another embodiment, the temperature integrator  892  is preprogrammed to require a refresh operation based on predetermined values of the integration of temperatures and times spent at each temperature. The programming also incorporates the time since the last refresh operation occurred. In either embodiment, the chemistry of the memory cells affects the required frequency of refreshing. For example, a first type of memory having a first memory cell chemistry may need to be refreshed more often and starting at a lower temperature than a second type of memory having a second memory cell chemistry. Although described with reference to temperatures, other conditions can be monitored to initiate refresh operations. For example, ambient humidity can be monitored and trip points established at which refresh is monitored. 
       FIG. 6  depicts a memory system  510 , such as described in connection with  FIGS. 1-5 , included on an integrated circuit (IC) substrate  1210  to form a complete System-On-a-Chip (SOC) device. The IC  1210  includes CPU  511  with a cache, ROM  520 , Bus  514 , I/O devices  515 ,  516 , and memory system  510 . The resulting IC  1210  may be developed to perform a specific function or a wide range of programmable functions. IC  1210  may be incorporated into a processor system or stand-alone as a complete system. 
       FIG. 7  shows system  2000 , a typical processor based system modified to include a NNV memory system having burst self-refresh capabilities  510 . Processor based systems exemplify systems of digital circuits that could include and benefit greatly from such a memory device. System  2000  includes central processing unit (CPU)  2010 , system controller  559 , AGP graphics device  2015 , CD ROM drive  2030 , hard disk  20220 , ROM  2012 , I/O controller  2011 , RAM  2060 , NNV memory  509 , power management controller  550 , I/O devices  2050 ,  2051 , and Voltage regulators Vreg2  2025 , Vreg3  2026 . CPU  2010 , such as an Intel™ Pentium-4™, Centurion™ or XScale™ processor, that communicate directly or indirectly with various devices over bus  2070 . Input/output (I/O) devices  2050  and  2051  and other devices provide communication into and out of system  2000 . Other devices provide memory, illustratively including an optional dynamic random access memory (RAM)  2060 , and one or more peripheral storage devices such as hard disk drive  2020  and compact disk (CD) ROM drive  2030 . This system also includes one or more instances of NNV memory  530 . 
     While the invention has been described in detail in connection with preferred embodiments known at the time, it should be readily understood that the invention is not limited to the disclosed embodiments. Rather, the invention can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope of the invention. For example, although the invention has been described in connection with specific circuits that dynamically OR refresh complete signals, the invention may be practiced with many other configurations without departing from the spirit and scope of the inventions, such as keeping refresh complete signals separate or by combining them in other ways, such as dynamic Ending or daisy-chaining. Accordingly, the invention is not limited by the foregoing description or drawings, but is only limited by the scope of the appended claims. 
     Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.