Abstract:
A capacitance to frequency converter includes a switching capacitor circuit, a charge dissipation circuit, a comparator, and a signal generator. The switching capacitor circuit charges a sensing capacitor and transfers charge from the sensing capacitor to a circuit node of the charge dissipation circuit. The comparator is coupled to the charge dissipation circuit to compare a potential at the circuit node to a reference voltage. The signal generator is coupled to an output of the comparator and to the charge dissipation circuit. The signal generator is responsive to the output of the comparator to generate a signal fed back to control the charge dissipation circuit. A frequency of the signal is proportional to a capacitance of the sensing capacitor.

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of U.S. Provisional Application No. 60/947,871, filed on Jul. 3, 2007, the contents of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to electronic circuits, and in particular but not exclusively, relates to capacitance measurement circuits. 
     BACKGROUND INFORMATION 
     Capacitance sensors are used to implement a variety of useful functions including touch sensors (e.g., touch pad, touch dial, touch wheel, etc.), determining the presence of an object, accelerometers, and other functions. In general, capacitive sensors are intended to replace mechanical buttons, knobs, and other similar mechanical user interface controls. A capacitive sensor permits eliminating complicated mechanical switches and buttons, providing reliable operation under harsh conditions. Capacitive sensors are widely used in the modern consumer applications, providing new user interface options in the exiting products (cell phones, digital music players, personal digital assistances, etc.). 
     One class of capacitive sensor uses a charge transfer technique. Referring to  FIG. 1A , the charge transfer technique charges a sensing capacitor Cx in one phase (switch SW 1  closed, switch SW 2  open) and discharges the sensing capacitor Cx into a summing capacitor Csum in a second phase (SW 1  open, SW 2  closed). Switches SW 1  and SW 2  are operated in a non-overlapping manner repeating the transfer of charge from Cx to Csum. 
     Capacitance sensor  100  is operated to measure the capacitance of Cx in the following manner. In an initial stage, Csum is reset by discharging Csum by temporarily closing switch SW 3 . Then, switches SW 1  and SW 2  commence operating in the two non-overlapping phases that charge Cx and transfer the charge from Cx into Csum. The voltage potential on Csum rises with each charge transfer phase, as illustrated in  FIG. 1B . The voltage on Csum can by calculated according to equation 1. 
                     V   Csum     =       V   dd     ⁡     (     1   -     ⅇ       -   N     ⁢     Cx   Csum           )               (     Equation   ⁢           ⁢   1     )               
where V Csum  represents the voltage on Csum, N represents the cycle count, Cx and Csum represent capacitance values, and Vdd represents a power supply voltage. Accordingly, the capacitance of Cx can be determined by measuring the number of cycles (or time) required to raise Csum to a predetermined voltage potential.
 
     The charge transfer method is advantageous due to its relative low sensitivity to RF fields and RF noise. This relative noise immunity stems from the fact that the sensing capacitor Cx is typically charged by a low-impedance source and the charge is transferred to a low-impedance accumulator (i.e., the summing capacitor Csum). However, conventional capacitance sensors have the disadvantage that that voltage on the summing capacitor Csum rises versus time/cycles in an exponential manner (see  FIG. 1B  and Equation 1). The exponential relationship between the accumulated voltage potential on Csum and the charge transfer time/cycles requires some linearization if the capacitance of Cx is calculated as a function of the voltage potential on Csum after a predetermined time or number of cycles. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. 
         FIG. 1A  is a circuit diagram illustrating a conventional capacitance sensor circuit. 
         FIG. 1B  is a graph illustrating the exponential relationship between voltage on a summing capacitor and charge transfer cycles. 
         FIG. 2  is a circuit diagram illustrating a capacitance to frequency converter, in accordance with an embodiment of the invention. 
         FIG. 3  is a flow chart illustrating a process of operation of a capacitance to frequency converter, in accordance with an embodiment of the invention. 
         FIG. 4  is a circuit diagram illustrating the equivalent circuit resistance of a switching capacitor circuit, in accordance with an embodiment of the invention. 
         FIG. 5  is a line graph illustrating the output of a pulse generator having a zero level fixed length pulse during an active mode of operation, in accordance with an embodiment of the invention. 
         FIG. 6  includes two line graphs illustrating the relationship between a MOD_EN signal generated by a comparator and a feedback pulse signal generated by a pulse generator, in accordance with an embodiment of the invention. 
         FIGS. 7A-C  are circuit diagrams illustrating alternative dissipation circuit implementations, in accordance with embodiments of the invention. 
         FIG. 8  is a functional block diagram illustrating a demonstrative processing system for implementing a capacitive sense user interface using a capacitance to frequency converter, in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of an apparatus and method of operation for a capacitance to frequency converter are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. 
       FIG. 2  is a circuit diagram illustrating a capacitance to frequency converter  200 , in accordance with an embodiment of the invention. Capacitance to frequency converter  200  is capable of converting the measurement of the capacitance of sensing capacitor (Cx) into the measurement of the frequency of a feedback pulse signal (FB). Furthermore, the relationship between the frequency of FB (f FB ) and the capacitance of Cx is substantially linear. However, it should be appreciated that capacitance to frequency converter  200  may also be used for other functions such as a voltage to frequency converter or current to the frequency converter. Although the system of  FIG. 2  is referred to as a capacitance to “frequency” converter, it should be appreciated that the system of  FIG. 2  may also be referred to as a capacitance to period converter, since period is merely the reciprocal of frequency. 
     The illustrated embodiment of capacitance to frequency converter  200  includes a switching capacitor circuit  205 , a charge dissipation circuit  207 , an analog comparator (“CMP”)  210 , a pulse generator  215  with enable input, and a frequency measurement circuit  220 . The illustrated embodiment of switching capacitor circuit  205  includes sensing capacitor (Cx), a charging switch (SW 1 ), a charge transfer switch (SW 2 ), and a clocking circuit  209 . The illustrated embodiment of charge dissipation circuit  207  includes a modulation capacitor (Cmod), a discharge resistor (Rd), and a discharge switch (SW 3 ). While component values of switching capacitor circuit  205  may vary based on the particular application, in general, the capacitance of Cmod will be substantially larger than the capacitance of Cx. Since Cmod acts to accumulate charge transferred from Cx over multiple cycles, it is often referred to as a summing capacitor or an integrating capacitor. Pulse generator  215  generates fixed length pulses synchronized to MOD_EN output from CMP  210 . Pulse generator  215  may also be referred to as a sync generator due to the sync waveform it generates. 
       FIG. 3  is a flow chart illustrating a process  300  for operating capacitance to frequency converter  200 , in accordance with an embodiment of the invention. The order in which some or all of the process blocks appear in each process should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated, or even in parallel. 
     In a process block  305 , capacitance to frequency converter  200  is powered on and the output of comparator  210  (MOD_EN) is initially low, assuming Cmod is initially discharged and the voltage Umod on the non-inverting input of CMP  210  is less than Vref on its inverting input. In this state, pulse generator  215  is “disabled” generating a constant logic value for the feedback signal FB, which open circuits switch SW 3  (process block  310 ). 
     With power provided to the circuit, switches SW 1  and SW 2  also commence operation. Switches SW 1  and SW 2  switch, under control of a clock signal CLK distributed by clocking circuit  209  as two non-overlapping phases Phi 1  and Phi 2 , to reciprocally charge Cx and then transfer the charge from Cx onto Cmod (process block  315 ). The non-overlapping charge and charge transfer phases may be sufficiently spaced to prevent cross conduction or latch up between SW 1  and SW 2 . During operation, switching capacitor circuit  205  has an equivalent resistance Rc given by equation 2. 
                     R   C     =     1       f   CLK     ⁢     C   x                 (     Equation   ⁢           ⁢   2     )               
where f CLK  represents the frequency of the clock signal CLK and Cx represents the capacitance of the sensing capacitor Cx.  FIG. 4  illustrates the circuit equivalent resistance Rc. The clock signal CLK may be a fixed frequency signal, a spread spectrum clock signal, or otherwise.
 
     As switching capacitor circuit  205  begins charging Cmod, the voltage potential Umod at node N 1  begins to rise gradually with each charge transfer through switch SW 2 . Cmod continues to accumulate charge transferred from Cx until Umod reaches Vref, as determined by CMP  210  (decision block  320 ). When Umod reaches or passes Vref, CMP  210  toggles its output (MOD_EN) to enable pulse generator  215  (process block  325 ). 
     The illustrated embodiment of pulse generator  215  produces the FB signal having fixed width negative pulses (e.g., active is logic zero level). However, it should be appreciated that pulse generator  215  may also be implemented as an active high sync generator for generating fixed length positive pulses. With reference to  FIG. 5 , the duration of the zero level pulses are always fixed at a value t 0 . Since pulse generator  215  outputs an active low signal, the duty cycle of FB of the illustrated embodiment of pulse generator  215  is defined according to equation 3. 
                     Duty   ⁢           ⁢   Cycle     =       t   0     T             (     Equation   ⁢           ⁢   3     )               
where T is the period of the FB signal and t o  represents the duration of the zero level pulses.
 
     Pulse generator  215  operates in one of three operation modes: 1) when the MOD_EN signal is active constantly, FB is switched with a minimal fixed period having a fixed duty cycle, 2) when the MOD_EN signal is switched from the active state (e.g., ON) to the inactive state (e.g., OFF), FB returns to the inactive high state only after completing the current zero level pulse, and 3) while the MOD_EN signal is in the inactive state (e.g., OFF), FB is output as a static logical high.  FIG. 6  illustrates how the active state of the MOD_EN signal generates zero level pulses from pulse generator  215 . When the MOD_EN signal transitions from the active state to the inactive state, the current zero level pulse is completed, as illustrated by arrow  605 . 
     As FB continues to toggle while the MOD_EN signal is in the active state, switch SW 3  toggles between open and closed states discharges Cmod through discharge resistor Rd (process block  335 ). Cmod continues to periodically discharge through Rd until Umod drops below Vref (decision block  340 ). At this point, CMP  210  toggles the MOD_EN signal, deactivating pulse generator  215  (process block  310 ) and returning FB to the inactive state. With FB returned to the high level inactive state, switch SW 3  is open circuited and the charging of Cmod repeats in process block  315 . 
     After an initial transitory startup phase, capacitance to frequency converter  200  enters its steady state phase where the voltage potential Umod on Cmod oscillates or dithers about Vref. This oscillation about Vref creates the modulation signal MOD_EN used to enable/disable pulse generator  215  to thereby modulate the frequency of the feedback pulse signal FB. Once operating in the steady state phase, the frequency of the feedback pulse signal is directly proportional to the capacitance of Cx as seen by equations 4, 5, and 6 below. The current I Cx  through the equivalent resistance Rc is 
                     I   Cx     =         Vdd   -   Vref     Rc     =       (     Vdd   -   Vref     )     ·       f     CLK   Cx       .                 (     Equation   ⁢           ⁢   4     )               
Since the sum of currents into and out of node N 1  must equal zero, the average current I Rd  through discharge resistor Rd is
 
                       I   RD     =         Vref   Rd     ·       t   0     T       =           Vref   Rd     ·     t   o       ⁢   F     =     I   cx           ,           (     Equation   ⁢           ⁢   5     )               
where F represents the frequency or 1/T of the FB signal. Finally, by rearranging equation 5 and plugging in equation 4 to eliminate the I Cx  variable,
 
     
       
         
           
             
               
                 
                   F 
                   = 
                   
                     
                       ( 
                       
                         
                           Vdd 
                           Vref 
                         
                         - 
                         1 
                       
                       ) 
                     
                     · 
                     
                       
                         
                           f 
                           CLK 
                         
                         ⁢ 
                         
                           R 
                           d 
                         
                       
                       
                         t 
                         o 
                       
                     
                     · 
                     
                       Cx 
                       . 
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     6 
                   
                   ) 
                 
               
             
           
         
       
     
     As can be seen from equation 6, at fixed values for Vdd, Vref, Rd, and fclk, the dependence of F on Cx is linear. In short, pulse generator  215  is synchronized to MOD_EN and produces pulses FB with a frequency directly proportional to the capacitance of Cx. Accordingly, in a process block  345 , frequency measurement circuit  220  measures the frequency of the feedback pulse signal FB. The measured frequency values can then be used to determine the capacitance Cx or capacitance change ΔCx of the sensing capacitor (process block  350 ). In one embodiment, frequency measurement circuit  220  may include a simple counter to measure the frequency of the feedback pulse signal FB. For fixed values of Vdd, Rd, and Cx, capacitance to frequency converter  200  operates as a voltage (Vref) to frequency converter where the output frequency of FB is selected by appropriate selection of Vref. 
       FIGS. 7A-C  are circuit diagrams illustrating alternative implementations of charge dissipation circuit  207 , in accordance with embodiments of the invention.  FIG. 7A  illustrates a charge dissipation circuit  705 , which replaces SW 3  and discharge resistor Rd with a current source  707  controlled by feedback pulse signal FB. When FB is a logic HIGH, current source  707  sinks a current I D  from modulation capacitor Cmod to ground. When FB is logic LOW, current source  707  is disabled. 
       FIG. 7B  illustrates a charge dissipation circuit  710  including a switching capacitor resistor circuit  712  with a gated clock source. When FB is logic HIGH, the clock signal CLK is applied to the switches SW 4  and SW 5  with non-overlapping pulses (e.g., such as clock signals Phi 1  and Phi 2 ), causing a discharging current to flow to ground from modulator capacitor Cmod. At a logic LOW value for FB, the clock signal CLK is gated and switching capacitor circuit  712  does not sink current from modulator capacitor Cmod. 
       FIG. 7C  illustrates a charge dissipation circuit  715  where the non-overlapping clock phases Phi 1  and Phi 2  are applied constantly to switches SW 4  and SW 5 , but SW 4  and SW 5  are selectively connected in series between Umod and either Vref or ground by the multiplexor MUX, depending on the value of the feedback pulse signal FB. The principle of operating of charge dissipation circuit  715  is similar to charge dissipation circuit  710  in that SW 4 , SW 5 , and Ccomp operate as a switching capacitor resistor circuit. 
       FIG. 8  is a functional block diagram illustrating a demonstrative system  1100  for implementing a capacitive sense user interface, in accordance with an embodiment of the invention. The illustrated embodiment of system  1100  includes a processing device  1110 , a capacitive sense pad  1120 , a capacitive sense linear slider  1130 , a capacitive sense radial slider  1140 , a host processor  1150 , an embedded controller  1160 , and non-capacitance sensor elements  1170 . Processing device  1110  may include analog and/or digital general purpose input/output (“GPIO”) ports  1107 . GPIO ports  1107  may be programmable. GPIO ports  1107  may be coupled to a Programmable Interconnect and Logic (“PIL”), which acts as an interconnect between GPIO ports  1107  and a digital block array of processing device  1110  (not illustrated). The digital block array may be configured to implement a variety of digital logic circuits (e.g., DAC, digital filters, digital control systems, etc.) using, in one embodiment, configurable user modules (“UMs”). The digital block array may be coupled to a system bus. Processing device  1110  may also include memory, such as random access memory (RAM)  1105  and program flash  1104 . RAM  1105  may be static RAM (“SRAM”), and program flash  1104  may be a non-volatile storage, which may be used to store firmware. Processing device  1110  may also include a memory controller unit (“MCU”)  1103  coupled to memory and the processing core  1102 . 
     Processing device  1110  may also include an analog block array (not illustrated). The analog block array is also coupled to the system bus. The analog block array also may be configured to implement a variety of analog circuits (e.g., ADC, analog filters, etc.) using, in one embodiment, configurable UMs. The analog block array may also be coupled to the GPIO  1107 . 
     As illustrated, capacitance sensor  1101 , which includes an implementation of capacitance to frequency converter  200  may be integrated into processing device  1110 . Capacitance sensor  1101  may include analog I/O for coupling to an external component, such as capacitive sense pad  1120 , capacitive sense linear slider  1130 , capacitive sense radial slider  1140 , and/or other capacitive sense devices. Capacitive sense pad  1120 , capacitive sense linear slider  1130 , and/or capacitive sense radial slider  1140  may each include one or more sensing capacitors Cx to implement the individual capacitive sense buttons therein. 
     Processing device  1110  may include internal oscillator/clocks  1106  and communication block  1108 . The oscillator/clocks block  1106  provides clock signals to one or more of the components of processing device  1110 . Communication block  1108  may be used to communicate with an external component, such as a host processor  1150 , via host interface (I/F) line  1151 . Alternatively, processing device  1110  may also be coupled to embedded controller  1160  to communicate with the external components, such as host  1150 . Interfacing to the host  1150  can be through various methods. In one exemplary embodiment, interfacing with the host  1150  may be done using a standard PS/2 interface to connect to embedded controller  1160 , which in turn sends data to the host  1150  via low pin count (LPC) interface. In some instances, it may be beneficial for processing device  1110  to do both touch-sensor pad and keyboard control operations, thereby freeing up the embedded controller  1160  for other housekeeping functions. In another exemplary embodiment, interfacing may be done using a universal serial bus (USB) interface directly coupled to host  1150  via host interface line  1151 . Alternatively, processing device  1110  may communicate to external components, such as host  1150  using industry standard interfaces, such as USB, PS/2, inter-integrated circuit (I2C) bus, or system packet interfaces (SPI). Host  1150  and/or embedded controller  1160  may be coupled to processing device  1110  with a ribbon or flex cable from an assembly, which houses the sensing device and processing device. 
     In one embodiment, processing device  1110  is configured to communicate with embedded controller  1160  or host  1150  to send and/or receive data. The data may be a command or alternatively a signal. In an exemplary embodiment, system  1100  may operate in both standard-mouse compatible and enhanced modes. The standard-mouse compatible mode utilizes the HID class drivers already built into the Operating System (OS) software of host  1150 . These drivers enable processing device  1110  and sensing device to operate as a standard cursor control user interface device, such as a two-button PS/2 mouse. The enhanced mode may enable additional features such as scrolling (reporting absolute position) or disabling the sensing device, such as when a mouse is plugged into the notebook. Alternatively, processing device  1110  may be configured to communicate with embedded controller  1160  or host  1150 , using non-OS drivers, such as dedicated touch-sensor pad drivers, or other drivers known by those of ordinary skill in the art. 
     Processing device  1110  may reside on a common carrier substrate such as, for example, an integrated circuit (IC) die substrate, a multi-chip module substrate, or the like. Alternatively, the components of processing device  1110  may be one or more separate integrated circuits and/or discrete components. In one exemplary embodiment, processing device  1110  may be a Programmable System on a Chip (PSoC™) processing device, manufactured by Cypress Semiconductor Corporation, San Jose, Calif. Alternatively, processing device  1110  may be one or more other processing devices known by those of ordinary skill in the art, such as a microprocessor or central processing unit, a controller, special-purpose processor, digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”), or the like. In an alternative embodiment, for example, processing device  1110  may be a network processor having multiple processors including a core unit and multiple microengines. Additionally, processing device  1110  may include any combination of general-purpose processing device(s) and special-purpose processing device(s). 
     Capacitance sensor  1101  may be integrated into the IC of processing device  1110 , or alternatively, in a separate IC. Descriptions of capacitance sensor  1101  may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing capacitance sensor  1101 , or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium (e.g., CD-ROM, hard disk, floppy disk, etc.). Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe capacitance sensor  1101 . 
     In one embodiment, electronic system  1100  may be used in a notebook computer. Alternatively, system  1100  may be used in other applications, such as a mobile handset, a personal data assistant (PDA), a keyboard, a television, a remote control, a monitor, a handheld multi-media device, a handheld video player, a handheld gaming device, or a control panel. 
     The processes explained above are described in terms of computer software and hardware. The techniques described may constitute machine-executable instructions embodied within a machine (e.g., computer) readable medium, that when executed by a machine will cause the machine to perform the operations described. Additionally, the processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”) or the like. 
     A machine-accessible medium includes any mechanism that provides (e.g., stores) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-accessible medium includes recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). 
     The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. 
     These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.