Abstract:
Power control circuits and methods are disclosed, suitable for a power supplier. A power control circuit has a clock generator, a phase controller and a power limiter. The clock generator provides a clock signal, substantially determining switching cycles of a power supply. The phase controller outputs a burst signal based on a group reference signal and a burst initiation signal, and makes a burst period corresponding to a burst signal not less than a group reference period corresponding to the group reference signal. The burst signal is capable of switching the power supplier between a switching state and a non-switching state. The power limiter limits the power transferred by the power supply in every switching cycle, during a burst-up duration after the power supply is switched from the non-switching state to the switching state. The burst initiation signal correlates to an output voltage of the power supplier.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to control methods of a power supply, and more particularly relates to control methods when operating under light load or no load conditions of the power supply. 
         [0003]    2. Description of the Prior Art 
         [0004]    A power supply is used to convert power to within a specific level to power electronic devices or components. The power consumed by the power supply should be as low as possible to improve conversion efficiency. Even small power consumption will decrease conversion efficiency by a great deal, particularly under light load or no load conditions of the power supply. Consequently, a major consideration of designing the power supply is to lower power consumption for light load or no load conditions of the power supply. 
         [0005]    A switching mode power supply is designed to operate in skip mode or burst mode under light load or no load conditions.  FIG. 1  illustrates a flyback power supply  60  of the prior art. A power management controller  74  controls a power switch  72  to store power from AC input or deliver power to output through a transformer  65 . A compensation signal S COM  is controlled by an output voltage V OUT  through a feedback loop comprising LT 431  and a photo coupler  63 .  FIG. 2  is a simplified block diagram illustrating a power management controller  74   a  of the prior art according to one embodiment of  FIG. 1 . When a burst signal S BST  is asserted, a clock generator  86  generates a clock signal S CLK  to periodically switch the power switch  72  on and off by a logic controller  62 ; this is referred to as a switching state. The clock signal S CLK  substantially defines switching cycles of the power supply  60 . On time of the power switch  72  is controlled by a limiting signal S CS-L  and a comparator  82 . The limiting signal S CS-L  is generated by a level shifter  67 , and can be regarded as equivalent to the compensation signal S COM . A resistor  61  forms a path to a power source Vcc for the compensation signal S COM . When the compensation signal S COM  is lower than a burst reference voltage V BST-REF , a comparator  84  sets a burst signal S BST  to logic  0 , hence turning off the power switch  72  regardless of the clock signal S CLK , and maintaining the power switch  72  in a non-switching state.  FIG. 3  illustrates possible waveforms of signals S CLK , V G , V CS  of the power management controller  74   a  of  FIG. 2  operating under light load or no load. As the compensation signal S COM  varies, a control signal V G  of the power management controller  74   a  forces the power switch  72  to conduct for one or consecutive switching cycles, then turns off the power switch  72  for the following one or consecutive switching cycles. The above described mode is referred to as skip mode or burst mode, and is referred to as burst mode hereinafter. 
         [0006]    Burst mode is dedicated to stopping consecutive mostly ineffective switching cycles and focuses power conversion on consecutive more effective switching cycles. Burst mode can cause annoying audible noise without proper control of power conversion in effective switching cycles. For instance, audible noise occurs if the sum of the switching state period T B  and the non-switching state period T S , period T G , corresponding to frequency f G , falls within the audible frequency range. 
       SUMMARY OF THE INVENTION 
       [0007]    The embodiment of the present invention presents a power control circuit adapted to a power supply. The power control circuit comprises a clock generator, a phase controller, a power limiter. The clock generator provides a clock signal to substantially determine switching cycles of the power supply. The phase controller generates a burst signal having a period not smaller than a period of a group reference signal according to the group reference signal and a burst initiation signal. The burst signal switches the power supply to either a switching state or a non-switching state. The power limiter limits a power output of the power supply in every switching cycle during a burst up duration after the power supply switches from the non-switching state to the switching state. The burst up duration is not smaller than the period of the group reference signal. The burst initiation signal relates to a power output of the power supply. 
         [0008]    The embodiment of the present invention also extends to a power control method adapted to a power supply, comprising: generating a burst initiation signal related to a power output of the power supply; generating a burst signal having a period not smaller than a period of a group reference signal according to the burst initiation signal and the group reference signal, wherein the burst signal can switch the power supply to either a non-switching state or a switching state; limiting the power output of the power supply in every switching cycle within a burst up duration after the power supply switches from the non-switching state to the switching state, wherein the burst up duration is not smaller than the period of the group reference signal. 
         [0009]    The embodiment of the present invention extends further to a power control circuit adapted to a power supply, comprising: a clock generator, a group reference signal generator, a burst timer, and a power limiter. The clock generator provides a clock signal for substantially determining switching cycles of the power supply. The group reference signal generator generates a group reference signal having a period longer than a switching cycle of the clock signal. The burst timer determines a burst up duration after the power supply switches from a non-switching state to a switching state, wherein the burst up duration is not smaller than the period of the group reference signal. The power limiter limits a power output of the power supply in every switching cycle within the burst up duration. 
         [0010]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a diagram illustrating a flyback power supply of the prior art. 
           [0012]      FIG. 2  is a diagram illustrating a power management controller of the prior art. 
           [0013]      FIG. 3  is a diagram illustrating possible signal waveforms of the power management controller of  FIG. 2  operating under light load or no load. 
           [0014]      FIG. 4  is a diagram illustrating a power management controller according to the embodiment of the power supply of  FIG. 1 . 
           [0015]      FIG. 5  is a diagram illustrating the phase controller and the peak limiter of  FIG. 4 . 
           [0016]      FIG. 6  is a diagram illustrating possible signal waveforms under different load conditions of the power management controller of  FIG. 4 . 
           [0017]      FIG. 7  is a diagram illustrating a power management controller adapted to the power supply of  FIG. 1  of the present invention. 
           [0018]      FIG. 8  is a diagram illustrating signal waveforms related to a clock generator of  FIG. 7 . 
           [0019]      FIG. 9  is a diagram illustrating a power management controller adapted to the power supply of  FIG. 1  of the present invention. 
           [0020]      FIG. 10  is a diagram illustrating the loop compensation controller of  FIG. 9 . 
           [0021]      FIG. 11  is a diagram illustrating a power management controller adapted to the present invention. 
           [0022]      FIG. 12  is a diagram illustrating a power management controller adapted to the power supply of  FIG. 1  of the present invention. 
           [0023]      FIG. 13  is a diagram illustrating a phase controller of  FIG. 12 . 
           [0024]      FIG. 14  is a diagram illustrating a power management controller adapted to the power supply of  FIG. 1  of the present invention. 
           [0025]      FIG. 15  is a diagram illustrating the phase controller and the peak limiter of  FIG. 14 . 
           [0026]      FIG. 16  is a diagram illustrating a burst timer of  FIG. 15 . 
           [0027]      FIG. 17  is a diagram illustrating timing diagram of certain signals of  FIG. 16  and  FIG. 14 . 
           [0028]      FIG. 18  is a diagram illustrating a group reference signal generator of  FIG. 15 . 
           [0029]      FIG. 19  is a diagram illustrating timing diagram of certain signals of  FIG. 18 . 
       
    
    
     DETAILED DESCRIPTION 
       [0030]    Embodiments of the present invention are illustrated by a flyback (converter) power supply, but the invention is not limited thereto, and may be adapted to, boost, buck, or other converter topologies. 
         [0031]      FIG. 4  is a simplified block diagram illustrating a power management controller  74   b  according to the embodiment of the power supply  60  of  FIG. 1 . The power management controller  74   b  can limit group frequency f G  to lower than a certain value. For instance, group frequency f G  is lower than 1 kHz to reduce audible noise within harmonic frequencies of f G  between 5 kHz and 15 kHz range. 
         [0032]    Comparing  FIG. 4  and  FIG. 2 ,  FIG. 4  comprises a phase controller  64 , a peak limiter  66 , and an exit comparator  68 . Other components are well known to those of ordinary skill in the art. 
         [0033]    The phase controller  64  comprises three input terminals, individually receiving a clock signal S CLK  (from a clock generator  86 , a burst initiation signal S BST-INN  from a comparator  84 , and an exit signal S EXT  from an exit comparator  68 , and hence generating a burst signal S BST  and a suppression signal S DPS . The power supply  60  should switch to a non-switching state or to a switching state when the burst initiation signal S BST-INN  changes, but the phase controller  64  may or may not change the state of the burst signal S BST  instantly. The state of the burst signal S BST  is changed according to a phase difference of the burst initiation signal S BST-INN  and a group reference signal S SCLK . Under some circumstances, the phase controller  64  may enable the suppression signal S DPS  to limit the peak of a current sense signal V CS  to be a certain value and to not vary with a compensation signal S COM  by the peak limiter  66 . Detailed illustration of the phase controller  64  and the peak limiter  66  will be shown in a later section. 
         [0034]      FIG. 5  illustrates a simplified block diagram of the phase controller  64  and the peak limiter  66  of  FIG. 4 . 
         [0035]    The phase controller  64  comprises a frequency divider  28 , a suppression signal generator  26 , and a frequency limiter  24 . The frequency divider  28  generates the group reference signal S SCLK  with a frequency lower than the clock signal S CLK  according to the clock signal S CLK . For instance, the frequency of the group reference signal S SCLK  is set to 1 kHz when the frequency of the clock signal S CLK  is 25 kHz. The suppression signal generator  26  sets the suppression signal S DPS  to logic  0  when a release signal S FREE  or the exit signal S EXT  is logic  1 . 
         [0036]    The frequency limiter  24  limits the frequency of the burst signal S BST  to be lower than the frequency of the group reference signal S SCLK . The frequency limiter  24  comprises a phase comparator  22  to compare the phase difference of the group reference signal S SCLK  and the burst initiation signal S BST-INN . In  FIG. 5 , the phase comparator  22  compares the time difference of the rising edge of the group reference signal S SCLK  and the rising edge of the burst initiation signal S BST-INN . If the group reference signal S SCLK  rises earlier, the release signal S FREE  is asserted (logic  1 ). On the contrary, if the burst initiation signal S BST-INN  rises earlier, a standby signal S STD  is asserted. 
         [0037]      FIG. 6  illustrates possible signal waveforms under different load conditions of the power management controller  74   b  of  FIG. 4  to explain the operation of circuit of  FIG. 5 . From top to bottom,  FIG. 6  shows the current sense signal V CS , the clock signal S CLK , the group reference signal S SCLK , the compensation signal S COM , the burst initiation signal S BST-INN , the release signal S FREE , the standby signal S STD , a reset signal S R , the suppression signal S DPS , and the burst signal S BST . Other waveforms can be inferred from the assumed waveform of the compensation signal S COM , of  FIG. 6  with reference to the circuit of  FIG. 1 ,  FIG. 4 , and  FIG. 5 . 
         [0038]    As illustrated in group period T G1  from t 1  to t 3 , even though the compensation signal S COM  has risen above a burst reference voltage V BST-REF , the burst signal S BST  does not rise, and the power supply  60  remains in the non-switching state until the reference clock signal S SCLK  rises at t 3 . The group frequency (inverse of group period T G1 ) is equal to the frequency of the group reference signal S SCLK . 
         [0039]    As illustrated in group period T G2  from t 3  to t 5 , due to the release signal S FREE  having risen at t 4 , the burst signal S BST  rises as the compensation signal S COM  rises above the burst reference voltage V BST-REF . The group frequency (inverse of group period T G2 ) is lower than the frequency of the group reference signal S SCLK . 
         [0040]    Concluding from group period T G1  and T G2 , the burst signal S BST  does not rise before the rising edge of the group reference signal S SCLK . Therefore, the burst signal S BST  corresponds to a group frequency not higher than the frequency of the group reference signal S SCLK . 
         [0041]    As illustrated, at t 1  and t 3 , peaks of the current sense signal V CS  remain at a fixed value and do not vary with the compensation signal S COM , even though the power supply  60  is in the switching state. The reason is that whenever the burst signal S BST  is asserted, the reset signal S R  is also asserted, thereby disasserting the release signal S FREE  and asserting the suppression signal S DPS , which causes an input signal S COMSEL  of level shifter  67  to be fixed at a reference voltage V DPS-REF . At t 4 , the release signal S FREE  is asserted, so the input signal S COMSEL  of level shifter  67  becomes the compensation signal S COM  coming from the peak limiter  66 , and peaks of the current sense signal V CS  vary with the compensation signal S COM . 
         [0042]    In  FIG. 4 , the power supply  60  should enter the switching state under heavy load conditions instantly when the compensation signal S COM  is above an exit reference voltage V EXT-REF . For instance, the burst reference voltage V BST-REF  is 2V and the exit reference voltage V EXT-REF  is 3V. In  FIG. 5 , when the exit signal S EXT  is asserted, the burst signal S BST  is also asserted, and the compensation signal S COM  of the peak limiter  66  becomes the input signal S COMSEL . 
         [0043]      FIG. 7  is one embodiment of a power management controller  74   c  adapted to the power supply  60  of  FIG. 1  of the present invention.  FIG. 7  is similar to  FIG. 4 , the difference being that the clock generator  86   a  in  FIG. 7  receives the burst initiation signal S BST-INN . The clock generator  86   a  generates the clock signal S CLK  with its frequency varying with the state of the burst initiation signal S BST-INN .  FIG. 8  shows waveforms of the clock generator  86   a  of  FIG. 7 . When the burst initiation signal S BST-INN  is asserted, the clock signal S CLK  is at a normal frequency higher than a reduced frequency when the burst initiation signal S BST-INN  is disasserted. The function is achieved by varying the slope of a ramp signal V RMP  as shown in  FIG. 8 . In another embodiment, the clock generator generates the clock signal S CLK , with its frequency varying with the state of the burst signal S BST . One of the advantages of the design is to save power in the non-switching state. Another advantage is to reduce noise in burst mode. When in burst mode, the frequency of the group reference signal S SCLK  may not be a fixed value, but depends on the burst initiation signal S BST-INN  or the disasserted duration of the burst signal S BST . Therefore the group frequency may jitter and disperse audio energy. 
         [0044]      FIG. 9  is a power management controller  74   d  adapted to the power supply  60  of  FIG. 1  of the present invention.  FIG. 9  is similar to  FIG. 4 , the difference being an additional loop compensation controller  69  connected between a resistor  61  and a power source Vcc.  FIG. 10  illustrates the loop compensation controller  69  of  FIG. 9 . When the burst initiation signal S BST-INN  is asserted, a switch  32  is short circuited. The short circuited switch  32  provides the power source Vcc to the compensation signal S COM . When the burst initiation signal S BST-INN  is disasserted, and the power supply  60  operates in the non-switching state, a divider  30  enables clock signal S CLK  to short circuit the switch  32  for one switching cycle once every four switching cycles, and the switch  32  remains open circuited for the rest of the time. In so doing, more power can be saved in the non-switching state. 
         [0045]      FIG. 11  is a power management controller  74   e  adapted to the present invention.  FIG. 11  integrates parts of circuits in  FIG. 4 ,  FIG. 7 , and  FIG. 9 . Operation of the circuit in  FIG. 11  can be inferred from the illustration and explanation of  FIG. 4 ,  FIG. 7 , and  FIG. 9 . 
         [0046]      FIG. 12  is a power management controller  74   f  adapted to the power supply  60  of  FIG. 1  of the present invention.  FIG. 13  illustrates a phase controller  70  of  FIG. 12 . The phase controller  64  compares the rising edges of the group reference signal S SCLK  and the burst initiation signal S BST-INN . The phase controller  70  of  FIG. 13  comprises inverters  42  and  44 . The phase controller compares the falling edges of the group reference signal S SCLK  and the burst initiation signal S BST-INN . The phase controller  70  limits the frequency of two consecutive falling edges of the burst signal S BST  to be smaller than the frequency of the group reference signal S SCLK . 
         [0047]      FIG. 14  is a power management controller  74   g  adapted to the power supply  60  of  FIG. 1  of the present invention. The burst signal S BST  switches the power supply  60  between the switching state and the non-switching state.  FIG. 14  is similar to the embodiments hereinbefore. A phase controller  64   a  in  FIG. 14  provides the group reference signal S SCLK  and limits the group period corresponding to the burst signal S BST  to be not smaller than the period of the group reference signal S SCLK . The period indicates the duration between two consecutive rising edges or falling edges of the corresponding signal. The phase controller  64   a  also generates the suppression signal S DPS  to set a peak limit signal V CS-LIMIT  of a peak limiter  66   a . A comparator  83  limits the current sense signal V CS  to be smaller than the peak limit signal V CS-LIMIT  in every switching cycle (equivalent to the cycle of the clock signal S CLK ). So, the peak limiter  66   a  and the comparator  83  can be regarded as a power limiter, limiting the power conversion of the power supply  60  in every switching cycle. 
         [0048]      FIG. 15  illustrates the phase controller  64   a  and the peak limiter  66   a  of  FIG. 14 . Simply said, the phase controller  64   a  controls the group period and the peak limiter  66   a  controls the power output in every switching cycle. Audible noise can be reduced by proper adjustment of the said controller and limiter. 
         [0049]    The phase controller  64   a  comprises the reference generator  33 , a suppression signal generator  26   a , a burst timer  35 , and the frequency limiter  24 . The group reference signal generator  33  generates the group reference signal S SCLK  with a frequency lower than the frequency of the clock signal S CLK , which is explained in detail later. The frequency limiter  24  limits the group period corresponding to the burst signal S BST  to be not lower than the period of the group reference signal S SCLK . The burst timer  35  determines the burst up duration when the power supply  60  switches from the non-switching state to the switching state. A release signal S DPSX  is disasserted (logic  0 ) within the burst up duration. If the exit signal S EXT  remains at logic  0  within the burst up duration, the suppression signal S DPS  remains at logic  1  and forces the peak limiter  66   a  to select a peak limit value V CS−LIMIT−L , thus suppressing the power output to a very low level in every switching cycle. For instance, assumes the peak limit value V CS−LIMIT−L  is 0.2V, if the suppression signal S DPS  is logic  0 , the peak limiter  66   a  selects a higher peak limit value V CS−LIMIT−H . If the peak limit value V CS−LIMIT−H  is 0.85V, and under normally heavy load conditions, the current sense signal V CS  is limited by the compensation signal S COM  and does not reach the peak limit value of V CS−LIMIT−H . 
         [0050]      FIG. 16  illustrates one embodiment of a burst timer  35 .  FIG. 17  illustrates some signal waveforms of  FIG. 16  and  FIG. 14 . Assumes a plurality of outputs Q of D flip-flops  90 ,  92 ,  94 , and  96  are initially logic  0 . Only when the power supply  60  switches from the non-switching state to the switching state, and thereby asserts the burst signal S BST  to logic  1 , can the output Q of D flip-flop  96  being asserted to logic  1 , and thereby transmits the group reference signal S SCLK  to a plurality of clock inputs of D flip-flops  90 ,  92 , and  94 . D flip-flops  90 ,  92 , and  94  can be regarded as a shift register, and the output Q is asserted to logic  1  in sequence according to the number of rising edges of the group reference signal S SCLK . For instance, when the burst signal S BST  changes from logic  0  to logic  1  and the group reference signal S SCLK  rises for the first time, signal Q 1  changes from logic  0  to logic  1 ; when the group reference signal S SCLK  rises for the second time, signal Q 2  changes from logic  0  to logic  1 , as illustrated in  FIG. 17 . In  FIG. 16 , when signal Q 2  changes from logic  0  to logic  1 , a single pulse generator  98  outputs a short pulse signal S PLS  to reset outputs Q of D flip-flops  90 ,  92 ,  94 , and  96 , to logic  0 . From  FIG. 17 , as the burst signal S BST  changes from logic  0  to logic  1 , the release signal S DPSX  changes from logic  1  to logic  0  and remains at logic  0  for over one reference cycle. The release signal S DPSX  changes from logic  0  to logic  1  when signal Q 2  changes from logic  0  to logic  1 . The burst up duration is determined by the duration for which the release signal S DPSX  remains  0 .  FIG. 17  also illustrates that, during the burst up duration, the peak value of the current sense signal V CS  is fixed to around 0.2V (peak limit value V CS−LIMIT−L ) in every switching cycle. The peak value of the current sense signal V CS  varies with the limit signal S CS-L  outputted by the level shifter  67  in every switching cycle after the burst up duration. 
         [0051]      FIG. 18  illustrates the group reference signal generator  33 .  FIG. 19  illustrates certain signal waveforms of  FIG. 18 . A charge and discharge control circuit  52  generates the group reference signal S SCLK  according to a charge and discharge time of capacitor  58 . In one embodiment, the charge and discharge circuit  52  is in a single chip integrated circuit, and connected to an externally connected capacitor through one pin of the single chip integrated circuit. A counter  54  counts the time T sense  required for the terminal voltage V CT  of capacitor  58  to climb from initial ground voltage to a predetermined voltage, and a result is indicated by SS. The larger the capacitor  58 , the longer T sense  is, and therefore the larger SS is. A peak limit selector  56  selects one reference voltage from V REF-1 , V REF-2 , V REF-3 , and V REF-4  to be set as the peak limit value V CS−LIMIT−L  according to the counting result SS. In other words, the peak limit value V CS−LIMIT−L  is determined by proper selection of the externally connected capacitor  58 . 
         [0052]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.