Abstract:
A copper damascene process for a mechanically weak low k dielectric layer is described. Electropolishing is used to etch back the copper. A sacrificial conductive layer beneath the barrier layer assures complete planarization of the copper.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to the field of interlayer connections in semiconductor devices using a copper damascene structure. 
     2. Prior Art 
     In current integrated circuits, several layers of interconnect structures fabricated above a substrate containing active devices are often used. Each interconnect layer is fabricated in, or on, an interlayer dielectric (ILD). Vias are formed in each ILD to make contact with conductors in underlying layers. It is generally accepted that the dielectric material in each ILD should have a low dielectric constant (k) to obtain low capacitance between the conductors. 
     Copper damascene structures are often used in conjunction with the ILDs to provide the interconnect structure. Typically, the copper is planarized using chemical-mechanical polishing (CMP) because of the difficulties of chemically etching copper. 
     A problem arises where low k dielectrics are used in conjunction with a copper damascene structure. The low k dielectrics are inherently mechanically weak, and consequently, not particularly suitable for the stresses associated with the CMP. 
     Articles discussing low k dielectrics are: “From tribological coatings to low-k dielectrics for ULSI interconnects,” by A. Grill, Thin Solid Films 398-399 (2001) pages 527-532; “Integration Feasibility of Porous SiLK Semiconductor Dielectric,” by J. J. Waeterloos, et al., IEEE Conference Proceedings, IITC, (June 2001) pages 253-254; and “Low-k Dielectrics Characterization for Damascene Integration,” by Simon Lin, et al., IEEE Conference Proceedings, IITC, (June 2001) pages 146-148. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a cross-sectional elevation view of an interlayer dielectric (ILD) with a sacrificial metal layer formed thereon. 
     FIG. 2 illustrates the structure of FIG. 1 after a trench has been etched in the ILD. 
     FIG. 3 illustrates the structure of FIG. 2 after the formation of a barrier layer and a seed layer. 
     FIG. 4 illustrates the structure of FIG. 3 after the formation of a copper layer. 
     FIG. 5 illustrates the structure of FIG. 4 after electropolishing. 
     FIG. 6 illustrates the structure of FIG. 5 after the removal of several layers. 
    
    
     DETAILED DESCRIPTION 
     A method for forming a damascene structure on a low k dielectric is described. In the following description, numerous specific details are set forth, such as specific materials and thicknesses in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known processing steps, such as masking and etching steps, have not been described in detail in order not to unnecessarily obscure the present invention. 
     Referring first to FIG. 1, an ILD  10  is illustrated, which may be any one of a plurality of known dielectric layers. Conductors are formed in the layer  10  which provide conductive paths with vias extending to conductors lying below the layer  10  and vias lying above the layer  10 . For purposes of the description below, only the formation of a conductor is described within the layer  10  using a damascene process. It will be apparent that contacts to underlying structures are formed simultaneously with the formation of the conductors, as is well-known in the art. The processing described below is used to simultaneously form not only the conductors in the layer  10 , but also the vias which contact structures below the layer  10 . 
     The layer  10  may be formed from any one of a plurality of known dielectric materials. In one embodiment of the present invention, layer  10  is formed from a low k dielectric such as a polymer based dielectric. In another embodiment an inorganic material such as a carbon-doped oxide is used. 
     One category of low k materials, the organic polymers, are typically spun-on. A discussion of perfluorocyclobutane (PFCB) organic polymers is found in “Integration of Perfluorocyclobutane (PFCB)”, by C. B. Case, C. J. Case, A. Komblit, M. E. Mills, D. Castillo, R. Liu, Conference Proceedings, ULSI XII.COPYRGT. 1997, Materials Research Society, beginning at page 449. These polymers are available from companies such as Dupont, Allied Signal, Dow Chemical, Dow Corning, and others. 
     Another category of low k materials that may be used in the present invention are silica-based such as the nanoporous silica aerogel and xerogel. These dielectrics are discussed in “Nanoporous Silica for Dielectric Constant Less than 2”, by Ramos, Roderick, Maskara and Smith, Conference Proceedings ULSI XII.COPYRGT. 1997, Materials Research Society, beginning at page 455 and “Porous Xerogel Films as Ultra-Low Permittivity Dielectrics for ULSI Interconnect Applications”, by Jin, List, Lee, Lee, Luttmer and Havermann, Conference Proceedings ULSI XII.COPYRGT. 1997, Materials Research Society, beginning at page 463. 
     A conductive layer  11  is formed on the ILD  10 . This layer is sometimes referred to in this application as a sacrificial layer since as will be seen, it serves as a conductive layer for processing purposes, and does not appear in the final structure. A metal layer having relatively high conductivity is used for layer  11 , since as will be seen, it is needed for the electropolishing. In one embodiment, layer  11  is a tungsten layer or tungsten alloy layer. The layer may have a thickness of, for example, 100-2,000 Å. 
     As shown in FIG. 2, a trench such as trench  12  is etched into the layer  10  through the sacrificial layer  11 . Ordinary masking and etching processing is used to form the trench  12  and other trenches and via openings needed within the layer  10 . 
     As shown in FIG. 3, a blanket barrier layer  13  is formed on the dielectric, which covers not only the sacrificial layer  11 , but also lines the trench formed in the layer  10 . The barrier layer  13  is used to prevent copper from diffusing into the dielectric material, as is well-known. For this purpose, 200 Å of tantalum or tantalum nitride may be used, as shown by the layer  13  of FIG.  3 . 
     Now, a copper or copper alloyed seed layer  14  is deposited to carry the electrical current for the electroplating of the copper. The copper alloy seed layer  14  may be formed using numerous conventional processes such as chemical vapor deposition (CVD), sputtering, etc. to uniformly deposit a relatively thin layer  14 . This layer may be formed from nickel, gold, or other materials. Layer  14  improves the electro-migration resistance of the entire interconnect structure. 
     Next, an ordinary plating process is used to form the copper or copper alloy layer  16  shown in FIG.  4 . 
     In typical prior art processing, CMP is now used to planarize the structure of FIG. 4, removing the copper  16 , copper seed layer and barrier layer, from the upper surface of the dielectric. However, as mentioned earlier, because of the mechanical weakness of the low k dielectric layer  10 , CMP is not an ideal way to planarize the structure of FIG.  4 . 
     Electropolishing is also known to planarize layers such as a copper layer. Electropolishing and related technology is described in U.S. Pat. Nos. 5,096,550; 6,017,437; 6,143,155; and 6,328,872. This type of process may be looked at as being the reverse of electroplating, and as such requires conduction through the layer  16 . One problem in using electropolishing is that islands of copper form which become disconnected and electrically isolated. Thus, in using electropolishing on the layer  16 , several islands of copper may remain on the dielectric  10 . The barrier layer  13 , such as a tantalum or titanium layer, does not provide sufficient conduction to prevent the formation of the copper islands. 
     With the present invention, however, the sacrificial layer  11  provides additional conduction which allows the electropolishing to be more effective, and consequently, allows the layer  16  to be planarized. The resultant structure is shown in FIG.  5 . 
     Now as shown in FIG. 6, the barrier layer  13  where exposed, is removed using well-known selective chemical etchants. Then, additional chemical etching are used to remove the sacrificial conductive layer  11 . An etchant that does not attack either the dielectric  10  or the copper  16  is used for removal of the layer  11 . 
     The sacrificial layer  11  protects the low k dielectric when the barrier layer  13  is etched. It is known that the barrier materials such as tantalum and titanium can be chemically etched in HF-based solutions. These solutions, however, also attack the low k dielectric. Since the sacrificial layer  11  remains intact at the time that the barrier layer is etched, it protects the low k dielectric. Finally, the sacrificial layer is etched selectively, for instance, in an H 2 O 2  based solution without damaging the low k dielectric. 
     Thus, as shown above, the role of the sacrificial layer  11  is to carry electrical current across the wafer, particularly during the final copper removal from the field regions during electropolishing. The added conductivity of the sacrificial layer ensures an efficient electrical path to the copper islands that often form towards the end of the electropolishing. The sacrificial layer  11  provides higher conductivity when compared to the traditional barrier materials of tantalum or titanium, thus assuring sufficient electrical current across the wafer during the electropolishing.