Abstract:
The output current of a fixed-frequency DC to DC converter is sensed, creating a voltage representative of the load current. This voltage is then compared to one or more threshold voltages using a plurality of comparators, creating a plurality of logic signals indicative of which of a plurality of ranges the output current falls within. These logic signals are coupled to a multiplexer which decodes the logical inputs to one-of-n and selects one gate drive voltage from a plurality of such voltages, each optimized for its corresponding current range. The selected gate drive voltage is then used as the gate drive in a known art DC to DC converter, thereby increasing efficiency over a wide range of output current.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of U.S. Provisional Application No. 60/824,872, filed Sep. 7, 2006. 
     
     BACKGROUND OF THE INVENTION 
       [0002]    1. Field of the Invention 
         [0003]    This invention relates generally to DC to DC voltage conversion, and more specifically to increasing the efficiency of such conversion by optimizing the MOSFET gate drive signal of a switching DC to DC converter as a function of output voltage load current. 
         [0004]    2. Description of the Related Art 
         [0005]    Conversion of direct current (DC) voltage from one voltage level to another is a common requirement in many electronic systems. One type of voltage converter is referred to as dissipative, wherein a voltage Vin higher than the desired output voltage Vout is applied to a first input terminal of a pass transistor, while a second output terminal of the pass transistor is connected to the load to be driven at voltage Vout. The output voltage applied to the load is sampled, scaled, and compared to a reference voltage, developing an error signal which then drives a third control terminal of the transistor in such a manner as to cause the scaled output voltage to become very close to the desired reference voltage, even with variation in Vin and/or current Iout drawn by the load. The current through the pass transistor in a dissipative converter is typically constant and substantially equal to the load current. One disadvantage of the dissipative converter is that significant power, approximated by P=Iout*(Vin−Vout), is dissipated in the pass transistor, creating undesired heat and inefficiency. 
         [0006]    A preferred type of voltage converter has become the switching converter, wherein the pass transistor is rapidly switched on and off to control the current flow to the load, hence voltage applied to the load. A switching converter having an output voltage lower than its input voltage is commonly referred to as a buck converter, while one having an output voltage higher than the input voltage is referred to as a boost converter. The ability of the switching converter to boost an input voltage to a higher level is another advantage over the dissipative converter. The efficiency of a switching converter is also typically much higher than a dissipative converter, especially in applications having a large difference between input and output voltages. 
         [0007]    In operation, a switching converter samples and scales the output voltage and compares this scaled voltage to a reference voltage, developing an error signal. This error signal then modulates the width of a pulse-width-modulated signal which drives the control terminal of the pass transistor, for example the gate if the pass transistor is a MOSFET. The gate drive signal causes the typical enhancement-mode MOSFET to have a very low drain to source resistance during the gate drive high state, and a very high resistance during the gate drive low state. By controlling the relative on/off time of the pulse-width-modulated gate drive, the amount of average current flowing through the pass transistor to the load is adjusted to drive the output (load) voltage to the desired value. As the input voltage decreases, increasing on time of the gate drive keeps the output voltage at the desired level. Conversely, increasing input voltage causes a decrease in on time. The frequency of the gate drive signal is typically in the hundreds of kilohertz to many megahertz range. 
         [0008]    Ideally, the pass transistor in a switching converter is either fully on, in which case its ideal resistance is zero, or fully off, in which case its ideal current flow is zero. In both ideal cases, no energy is lost in the pass transistor. Available non-ideal pass transistors, however, have non-zero on resistance Rds(on), where Rds refers to the drain to source resistance of a metal-oxide field-effect transistor (MOSFET). This non-zero Rds(on) leads to conduction loss, increasing with increasing load current. Because Rds(on) is reduced as the gate voltage is increased in an enhancement-mode MOSFET, conduction loss may be reduced by driving the gate at a higher voltage. However, the MOSFET gate capacitance must be charged or discharged at each transition. For a given gate capacitance, gate charge time increases with increasing gate voltage. As the transition times of the pass transistor become a significant fraction of the total switching signal period, the switching losses due to gate charging/discharging increase substantially. 
         [0009]    It is desirable therefore to optimize the gate drive voltage dependent on output current, keeping the gate drive voltage as low as practical while still achieving low Rds(on). At heavy load currents, efficiency degradation is dominated by MOSFET conduction losses due to non-zero Rds(on), so it is advantageous to apply a higher gate drive voltage to decrease Rds(on). At lighter load currents, switching losses due to gate capacitance dominate, so it is advantageous to apply a lower gate drive voltage, reducing the charge and discharge times of the gate. 
       SUMMARY OF THE INVENTION 
       [0010]    The invention provides a method and apparatus for automatically optimizing the gate drive voltage in a constant-frequency switching DC to DC converter dependent on output load current. 
         [0011]    In an embodiment of the invention described in greater detail below, load current flows through a current sensing resistor, generating a voltage proportional to load current. This voltage is compared to a plurality of voltage ranges by a plurality of comparators, for example ranges representing load currents of less than 30% of max, 30-60% of max, and over 60% of max. The outputs of the comparators are logically decoded into selection signals for a multiplexer. The multiplexer inputs are coupled to a plurality of gate drive voltages, one of which is selected depending on the selection signals, thereby coupling the selected voltage to the multiplexer output. Depending into which range the load current falls, a gate drive voltage appropriate to that current range is thus selected from a plurality of voltages, and applied to the gate drive circuitry. 
         [0012]    As further described below, the disclosed embodiments provide a combination of desirable properties not available in the known art, including a means of optimizing the gate drive voltage which in turn increases efficiency of the switching voltage converter. Another advantage is the ability to tailor the gate drive voltages to MOSFETs having different enhancement characteristics. 
         [0013]    Further benefits and advantages will become apparent to those skilled in the art to which the invention relates. 
     
     
       DESCRIPTION OF THE VIEWS OF THE DRAWINGS 
         [0014]    Example embodiments of the invention are described below with reference to the accompanying drawings, wherein: 
           [0015]      FIG. 1  (prior art) is a block diagram of a representative known art switching DC to DC converter; 
           [0016]      FIG. 2  is a block diagram of a switching DC to DC converter having gate drive voltage selected from a plurality of voltages, responsive to output load current; and 
           [0017]      FIG. 3  is a block diagram of a switching DC to DC converter having gate drive voltage selected from a plurality of voltages, responsive to output load current sensed by voltage drop across Rds(on) of switching MOSFET. 
       
    
    
       [0018]    Throughout the drawings, like elements are referred to by like numerals. 
       DETAILED DESCRIPTION 
       [0019]    In  FIG. 1 , a block diagram of a known DC to DC converter  100 , a first end of resistor Rscale 1   106  is connected to the output terminal Vout  104 , and a second end of resistor Rscale 1   106  is connected to a first end of resistor Rscale 2   108  and the inverting input of amplifier  110 . The second end of resistor Rscale 2   108  is coupled to ground. The non-inverting input of amplifier  110  is coupled to a reference voltage Vref_v  112 . The output of amplifier  110  is coupled to the control input CONTR of pulse-width modulator  114 . The pulse width modulator  114  has two outputs, PWM and a substantially equal but inverted signal PWM/. The output PWM of pulse-width modulator  114  is coupled to the select input SEL of switch S 1   118  and to terminal PWM  138 . A gate drive voltage input Vgd  120  is coupled to the anode of diode  130  and input IN 1  of switch S 2   116 . The cathode of diode  130  is coupled both to a first end of capacitor  132  and the input IN 1  of switch S 1   118 . A second input IN 2  of S 1   118  is coupled to a node also including the second end of capacitor  132 , the source S of first transistor Q 1   122 , the drain D of a second transistor Q 2   124 , terminal T 1   134 , and a first end of inductor Lfilter  126 . The drain D of first transistor Q 1   122  is coupled to terminal Vin  102 . The second end of inductor Lfilter  126  is connected to terminal T 2   136 . A wire couples terminal T 2   136  to Vout  104 . A first terminal of capacitor Cfilter  128  is connected to Vout  104 , and a second end of capacitor Cfilter  128  is connected to ground. The output OUT of S 1   118  is coupled to the gate G of transistor Q 1   122 , typically an enhancement-mode field effect transistor. The output PWM/ of pulse-width modulator  114  is connected to the select input SEL of switch S 2   116 ; a first input IN 1  of S 2   116  is connected to a gate drive voltage Vgd  120  and the anode of diode  130 ; a second input IN 2  of S 2   116  is connected to the source S of second transistor Q 2   124  (typically an enhancement-mode field effect transistor) and ground. The output OUT of switch S 2   116  is connected to the gate G of transistor Q 2   124 . The drain D of the second transistor Q 2   124  is connected as described above to the node including the source S of Q 1   122 . 
         [0020]    In operation, an input voltage Vin is applied to terminal Vin  102 , and an output voltage Vout at terminal  104  is coupled to a load. The voltage Vout at  104  is scaled (divided) by resistors Rscale 1   106  and Rscale 2   108  such that, when Vout is at the desired nominal output voltage, the voltage at the inverting input of amplifier  110  is substantially equal to the reference voltage Vref_v at the non-inverting input of amplifier  110 . When the output voltage Vout differs from its nominal voltage, the difference between the scaled representation of Vout and reference Vref_v is amplified by amplifier  110 , having its output coupled to the control input CONTR of pulse-width modulator  114 . The frequency of the waveform generated in pulse width modulator  114  is substantially constant, while the duty cycle (percentage of the period in a logical high state) of pulses varies responsive to the control input CONTR. The duty cycle of output PWM increases as Vout increases and decreases as Vout decreases. 
         [0021]    During the logical high of output PWM, which controls the state of switch S 1   118 , the complementary output PWM/, which controls the state of switch S 2   116 , is low, causing switch S 2  to couple the gate of Q 2   124  to ground, cutting off current flow in Q 2   124 . Concurrently, switch S 1   118  couples the end of capacitor  132  at IN 1  of S 1   118  to the output OUT of S 1   118  and to the gate G of transistor Q 1   122 , typically an enhancement-mode field effect transistor. The other end of capacitor  132  is coupled to the source of transistor  122 . As described in the next paragraph, capacitor  132  has been charged to a voltage approximating gate drive voltage Vgd during the previous logical low portion of PWM, thus providing a gate to source voltage for transistor Q 122 . During this logical high of PWM, transistor Q 1   122  is thus turned on and provides a very low resistance from drain D to source S, allowing flow of current from Vin at terminal  102  to Vout at terminal  104  through inductor Lfilter  126 . 
         [0022]    When the logical high state of PWM ends, a logical low state is entered. During the logical low of output PWM, the gate G and source S of Q 1   122  are coupled together through S 1   118 , which is now in the IN2 position, thereby causing Q 1   122  to be cut off and enter a high-resistance state. Concurrently, PWM/ is in a logical high state, causing switch S 2  to be in its IN1 position, coupling the gate of transistor Q 2   124  to Vgd  120  through S 2   116 . Transistor Q 2   124  is thus turned on by gate drive Vgd  120 , and provides a very low resistance from drain D to source S of Q 2   124 . The second end of capacitor  132  is thus coupled through transistor  124  to ground, while the first end of capacitor  132  is coupled through diode  130  to the gate drive voltage Vgd. Capacitor  132  is thereby charged to a voltage approximating Vgd minus a diode drop. 
         [0023]    The complementary switching of transistors Q 1  and Q 2  thereby modulates the flow of current through inductor Lfilter  126  to Vout  104 , which modulates the voltage at Vout according to Ohm&#39;s law. When the voltage Vout drops below the nominal value, the operation described above causes an increase in current, thus raising the voltage. Conversely, when the voltage Vout rises above the nominal value, a decrease in current through Lfilter  126  decreases the voltage Vout. A voltage Vin at terminal  102  is thus reduced to a lower voltage Vout at terminal  104 , and Vout is driven to its desired voltage by the action of the feedback loop described above. 
         [0024]    In  FIG. 2 , circuitry configured in a novel manner is added to the converter of  FIG. 1 , facilitating modifying the gate drive voltage Vgd as the load current at Vout changes. 
         [0025]    A resistor Rsense  202  replaces the wire coupling terminal T 2   136  and Vout  104  in  FIG. 1 . Rsense, typically having a resistance very low compared to the load resistance at output Vout  104 , has a first end connected to terminal T 2   136 , the second end of inductor Lfilter  126 , and the non-inverting input of differential amplifier  204 . The second end of resistor Rsense  202  is connected to output terminal Vout  104 , the first end of resistor Rscale 1   106 , the first end of capacitor Cfilter  128 , and the inverting input of differential amplifier  204 . 
         [0026]    The output of differential amplifier  204  is coupled to the non-inverting inputs of first comparator  206  and second comparator  208 . Resistor  212  has a first end connected to a reference voltage Vref_t  210 , and a second end connected to the inverting input of first comparator  206 , a first end of resistor  214 , and a terminal Vt 2   218 . The second end of resistor  214  is connected to the inverting input of comparator  208 , a first end of resistor  216 , and terminal Vt 1   220 . The second end of resistor  216  is connected to a reference voltage lower than Vref_t, such as ground. 
         [0027]    The output of comparator  208  is coupled to the select input SEL 1  of multiplexer  222 , and the output from comparator  206  is coupled to the select input SEL 2  of multiplexer  222 . A gate drive voltage Vgd 1  is coupled to IN 1   224  of multiplexer  222 ; gate drive voltage Vgd 2  is coupled to IN 2   226 , and gate drive voltage Vgd 3  is coupled to IN 3   228 . The output OUT of multiplexer  222  is coupled to the gate drive input Vgd  120  of the known DC-DC converter as described in  FIG. 1 . 
         [0028]    In operation, load current flowing through Rsense  202  produces a voltage drop across resistor Rsense  202  substantially proportional to current. The voltage generated across Rsense  202  is amplified in differential amplifier  204  and the amplified voltage is coupled to the non-inverting inputs of first comparator  206  and second comparator  208 . The resistive ladder comprising resistors  212 ,  214 , and  216  divides reference voltage Vref_t into a plurality of threshold voltages which are applied to the plurality of comparators, each voltage threshold corresponding to a desired output load current threshold level. At load currents below that corresponding to the first threshold voltage at the inverting input of comparator  208 , comparator  208  and comparator  206  both have a logic low output. For load currents causing the voltage out of amplifier  204  to be greater than the voltage at the inverting input of comparator  208  but less than the voltage at the inverting input of comparator  206 , comparator  208  output is logical high while comparator  206  output is logical low. For load currents causing the voltage out of amplifier  204  to be greater than the voltage at the inverting input of comparator  208  and greater than the voltage at the inverting input of comparator  206 , comparator  208  output and comparator  206  output are both logical high. The outputs of comparators  206  and  208  thus indicate which of a plurality of ranges the load current falls within. Comparators  206  and  208  incorporate hysteresis to reduce undesired rapid switching (chatter) when the input voltage is near a comparator threshold voltage. 
         [0029]    The outputs from comparators  206  and  208 , coupled to the select inputs of multiplexer  222 , are decoded in multiplexer  222  such that IN 1  is coupled to OUT for SEL 1  and SEL 2  having logical states 0, 0 respectively, corresponding to a first output current range; IN 2  is coupled to OUT for SEL 1  and SEL 2  having logical states 1, 0 respectively, corresponding to a second output current range; IN 3  is coupled to OUT for SEL 1  and SEL 2  having logical states 1, 1 respectively, corresponding to a third output current range. Gate drive Vgd 1  at input IN 1   224  is thus coupled to the output of multiplexer  222  when the load current is in the first range, Vgd 2  at input IN 2   226  when the load current is in the second range, and Vgd 3  at input IN 3   228  when the load current is in the third range. 
         [0030]    The gate drive voltage applied to the converter of  FIG. 1  is thus chosen from a plurality of gate drive voltages, depending on which of a plurality of ranges the load current falls within. By choosing a gate drive Vgd 1  which is lower in voltage than Vgd 2  or Vgd 3 , and applying it when the load current is in its first (lowest) range, the dominant switching losses may be minimized. Conversely, when load current is in its highest range, a gate drive Vgd 3  is chosen which is higher than Vgd 1  or Vgd 2 , to minimize the dominant conduction losses at the high load current. One or more intermediate current ranges and gate voltages may be applied as described above, but significant efficiency improvement is achieved even with a single threshold, two current ranges, and two gate drive voltages. 
         [0031]    In  FIG. 3 , circuitry configured in a novel manner is added to the converter of  FIG. 1 , in yet another embodiment facilitating modifying the gate drive voltage Vgd as the load current at Vout changes, using the Rds(on) of the switching transistor rather than a separate current sense resistor as in the circuit described in  FIG. 2 . 
         [0032]    Current sense resistor Rsense  202  of  FIG. 2  is omitted, being replaced by a wire connecting terminal T 2   136  and Vout  104  as in  FIG. 1 . The non-inverting input of an amplifier  302  is connected to Vin  102 , and thereby also to the drain of output transistor Q 1   122 . The inverting input of amplifier  302  is connected to terminal T 1   134  and thereby to the node including the source of output transistor Q 1   122 . A voltage proportional to current through Q 1   122  is developed across the non-zero drain to source resistance of this transistor Q 1   122 , which is proportional to output current at Vout  104 . The output of amplifier  302  is coupled to the input of sample/hold  304 . The trigger input of sample/hold  304  is coupled at terminal PWM  138  to the PWM signal of the known converter of  FIG. 1 . The output of sample/hold  304  is coupled to the non-inverting input of the comparator  306 . The inverting input of comparator  306  is coupled to the output OUT of threshold modifier  312 , and the output of comparator  306  is coupled to the select input SEL 1  of multiplexer  314 . A first end of resistor  308  is coupled to the reference voltage Vref_t; a second end of resistor  308  is coupled both to a first end of resistor  310  and input Vt of threshold modifier  312 . A first gate drive voltage Vgd 1  is coupled to IN 1   316  of multiplexer  314 , and a second gate drive voltage Vgd 2  is coupled to IN 2   318  of multiplexer  314 . The output OUT of multiplexer  314  is coupled both to the input Vgd of threshold modifier  312  and the Vgd input  120  of the converter of  FIG. 1 . 
         [0033]    In operation, pulse width modulator  114  provides, in a known manner, substantially complementary signals PWM and PWM/ at a nominal frequency. During the high state of PWM as described above, current flows to the load through transistor Q 1   122 . Because the drain-source resistance Rds(on) is non-zero, a voltage is developed between the drain and source proportional to current flow. This voltage is amplified in differential amplifier  302 . During the low state of PWM, transistor Q 1  is cutoff, and the drain-source voltage is no longer representative of the output current. The voltage out of amplifier  302  therefore is indicative of current only during the time PWM is high, turning on transistor Q 1 . Sample/hold  304  is triggered during this time by signal PWM or a substantially equivalent signal, causing sample/hold  304  to hold the voltage indicative of output current. This voltage is coupled to one input of comparator  306 , while the other input of comparator  306  is at a modified threshold voltage from threshold modifier  312 . If the held voltage indicative of output current is above this modified threshold voltage, the output of comparator  306  goes to a high state for the next period of PWM. Comparator  306  incorporates hysteresis to reduce undesired rapid switching (chatter) when the input voltage is near the comparator threshold voltage. When the output of comparator  306  goes high, multiplexer  314  couples Vgd 2   318  to the Vgd input  120  of the converter of  FIG. 1 . 
         [0034]    Threshold modifier  312  has as a first input a voltage Vt set by Vref_t and the resistive divider comprising resistors  308  and  310 . The second input of threshold modifier  312  is gate drive voltage Vgd as applied to converter  100 . Circuitry within threshold modifier  312  modifies the voltage Vt as a function of Vgd, thereby compensating for the change in the drain-source on resistance of transistor  122  as a function of gate drive voltage. 
         [0035]    It should also be understood that the use of Vdd, Vref, ground, etc., are illustrative only, and that implementations using dual power supplies and the like are equally possible. Moreover, reference voltages developed either internal to the circuit or external to the circuit will suffice. 
         [0036]    Those skilled in the art to which the invention relates will appreciate that yet other substitutions and modifications can be made to the described embodiments, without departing from the spirit and scope of the invention as described by the claims below. Alternative forms of hysteresis may be employed to preclude instability when the load current is substantially equal to one of the threshold levels. The number of threshold levels may be changed as appropriate. Many other alternatives to the circuits and sub circuits described are possible while retaining the scope and spirit of the invention.