Abstract:
A novel magnetic memory cell utilizing nanotubes as conducting leads. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry.

Description:
This application claims the benefit of priority to U.S. Provisional Patent Application No. 60/969,375, filed Aug. 31, 2007, the entire specification of which is hereby incorporated by reference. 
    
    
     FIELD 
     Embodiments of the present invention relate to solid state memories. 
     BACKGROUND 
     Referring to  FIG. 1  of the drawings, there is shown a magnetic memory cell  10 , known to the inventor. As will be seen, the cell  10  includes a magnetic storage element in the form of a magnetic tunnel junction (MTJ)  12 . The cell  10  also includes a Y write/read line  14  for carrying a write/read current. The line  14  lies in the plane of the page. An X write line  16  extends into the plane of the page and carries a current for performing a write operation. A bottom electrode  18  is in contact with the storage element  12  as is shown in  FIG. 1 . The electrode  18  is coupled to an access transistor  22  by means of a conductive via  20 . The access transistor  22  is made of drain terminal  23 , source terminal  24 , gate terminal  25  and conductor  26 . The access transistor and other circuitry required to make memory devices are realized on semiconductor substrate  27  and are well known to one skilled in the art. 
     In the memory cell  10  the structures  14 ,  16 ,  18 ,  20 , and  26  are realized by using metallic materials such as copper. In the quest to achieve high density memory devices, the physical dimensions of the cell  10  have to be reduced. Efforts to reduce the dimensions of the magnetic memory cell  10  in order to produce high density memory devices are being hampered by the phenomena of electro-migration in the metallic structures  14 ,  16 ,  18 ,  20  and  26  when the dimensions of these structures are reduced. 
     SUMMARY 
     A novel magnetic memory cell utilizing nanotubes as conducting leads is disclosed. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry. 
     Other aspects of the invention will be apparent from the detailed description below: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a cross-section through a conventional magnetic memory cell; 
         FIG. 2  shows a cross-section through a CNT magnetic memory cell, in accordance with one embodiment of the invention; 
         FIG. 3  shows the structure of an access transistor constructed using on CNTs in accordance with one embodiment of the invention; 
         FIGS. 4 and 5  illustrate write and read operations in accordance with one embodiment of the invention; 
         FIGS. 6 and 7  illustrates write and read operations in accordance with one embodiment of the invention; 
         FIG. 8  illustrates a method for fabricating an MRAM device using CNTs, in accordance with one embodiment of the invention; and 
         FIG. 9  shows processing steps for manufacturing semiconducting nanotube based transistors and a method to integrate them into an MRAM array, in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form only in order to avoid obscuring the invention. 
     Reference in this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearance of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments. 
     Although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to said details are within the scope of the present invention. Similarly, although many of the features of the present invention are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the invention is set forth without any loss of generality to, and without imposing limitations upon, the invention. 
       FIG. 1  of the drawings shows a cross-section through a typical magnetic memory cell. In the cell  10 , the conductive structures  14 ,  16 ,  18 ,  20  and  21  are the conductive wires in the backend of the semiconductor processing which in general are made of Aluminum, Aluminum alloy, Copper, Tungsten etc. The gate electrode  25  of a transistor  22  and in general is fabricated with metals or doped poly silicon or similar materials. The access transistor  22  which represents all the semiconductor memory access circuitry essential for the function of a memory device is fabricated using semiconductor process technology. 
       FIG. 2  of the drawings shows a cross-section through a magnetic memory cell  30 , in accordance with one embodiment of the invention. As will be seen, the magnetic memory cell  30  includes nanotube structures, and is thus referred to as a nanotube-based memory cell. In the cell  30 , the metallic structures  14 ,  16  and  18 , have been fabricated using nanotubes as opposed to metallic materials. Further, the access transistor  22  of  FIG. 1  is replaced with a semiconducting nanotube access transistor  32 . The structure of the transistor  32 , in accordance with one embodiment is shown in  FIG. 3  of the drawings. The gate electrode  25  of access transistor is fabricated using nanotube as well. 
     Because the structures  14 ,  16 ,  18 , and  25  have been fabricated using nanotubes, the dimensions of these structures may be reduced to a much greater extent than the equivalent metallic structures, without the problems of electromigration, due to the highly conductive nature of nanotubes. 
     The nanotubes may be Single Wall NanoTubes or Multi Wall NanoTubes. In one embodiment, the nanotubes may be formed by rolling graphene sheets into long tubes, in accordance with one embodiment. 
     In one embodiment, the carbon nanotubes may be grown by Chemical Vapor Deposition (CVD) techniques from Carbon rich gases like (CH4, C2H4 etc.). In one embodiment, a catalyst for growing the nanotubes may be Molybdenum, Iron or materials with similar properties for extruding excess carbon from their grains at high temperature). 
     For illustrative purposes, the nanotubes described hereinafter will be limited to carbon nanotubes (CNTs), and the MRAM cells that include these CNTs are thus CNT-based MRAM cells. 
       FIG. 8A  shows a cross section through a MRAM cell  40  in accordance with one embodiment of the invention. The MRAM cell comprises many structures in common with the MRAM cell  10 , and for the sake of clarity, these structures have been indicated with the same reference numerals. The process steps to manufacture the MRAM cell  40  will now be described with reference to  FIGS. 8B to 8I . 
     Referring to  FIG. 8B  the process begins with the fabrication of the components necessary for implementing addressing, sensing, and logic functions essential for the functioning of the MRAM cell. The components may be manufactured on a substrate  27  comprising, e.g. Si, Ge, GaAs, glass, ceramic, etc. In one embodiment the components may be fabricated using standard semiconductor device fabrication techniques know to one skilled in the art. 
     Thus in  FIG. 8B , the transistor circuitry  22 , and the metal layer indicated by M 1  are fabricated using standard semiconductor device fabrication techniques. Thereafter, an insulating layer  43  comprising, e.g. SiO2 is deposited over the layer M 1  as shown in  FIG. 8C . Next, a carbon nanotube  16  (see  FIG. 8D ) is fabricated by CVD, PECVD, or other techniques. In one embodiment the carbon nanotubes may be formed and connected with the help of Scanning Electron Microscopy techniques. In one embodiment, the carbon nanotubes may be a few tens of nanometers to a few hundred nanometers in cross sectional diameter. They may be of few hundred microns long. Referring to  FIG. 8E  a via  20  is formed in the layer  43  by standard lithographic and etching techniques. Thereafter, a bottom electrode  18  typically made of conductors is formed as shown in  FIG. 8F . Then a magnetic stack  12 , e.g. comprising a Magnetic Tunnel Junction of various structures is deposited and patterned as shown in  FIG. 8G . Referring to  FIG. 8H , a CNT  14  is grown horizontally on top of the magnetic stack  12 . Then a dielectric  44  is grown and the magnetic stack  12  with catalyst  28  is exposed with a mask. The magnetic stack typically would have a catalytic material  28  to initiate CNT growth  29  vertically, which in turn would join with the horizontally grown CNT  14 . According to  FIG. 8I  an insulating layer  45  is deposited on top of the device thus fabricated. 
     In another embodiment the access transistor  22  of  FIG. 1  can be replaced by a semiconducting nanotube transistor  32  which is illustrated in  FIG. 3 . The semiconducting NT transistor of  FIG. 3  is made of a semiconducting nanotube such as Carbon, Si, Ge, GaAs, CdTe etc. The semiconducting NT does not conduct current until a charge is inserted or induced into it. Referring to  FIG. 3  there is no current flow when a nominal voltage for example 1 to 3V is applied between the two ends of the tube indicated as metal island  1  and metal island  2 . When a small positive voltage for example 0.5 to 1V is applied to the gate it induces negative charge in the NT and increases the current flow. If a negative voltage of same magnitude was applied to the gate a positive charge is induced in the NT which reduces the current flow. Thus, transistor functionality is achieved. The fabrication of the semiconducting nanotube transistor is illustrated in  FIG. 9 . 
     Initially an array of islands made of insulating materials  47  is created as shown in  FIG. 9A  and  FIG. 9B . In  FIG. 9A  a photo resist  46  is coated and patterned using lithographic techniques. Then either a metallic layer or an insulating layer  48  with different etch rate with respect to the insulating islands  47  is deposited as shown in  FIG. 9C . Then an anisotropic etch is done as shown in  FIG. 9D . This leaves a thin sidewall on the sides of the insulating islands. Then a semiconducting material or materials  49  which will form the NT is/are deposited as shown in  FIG. 9E . Then the semiconducting layer is patterned to leave the material on top of the island and side walls. This step is not illustrated as it is know to one skilled in the art. Referring to  FIG. 9F  an isotropic etch is done to selectively etch the material  48  but not the material(s)  49 . When the material underneath the semiconducting materials is removed in this fashion the semiconducting material  49  curls up into a nanotube  50 .  FIG. 9G  shows the nanotubes thus formed in plan view. The semiconducting NT created thus can be patterned with a thin gate oxide  15  and a gate material  25  as shown in  FIG. 9G , which shows a 2×5 array of transistors formed in this process. The three terminals of the semiconducting NT transistors are gate  25 , source  24  and drain  23 . In  FIG. 9H  the respective contacts for the respective terminals are shown. In one embodiment, the sources of all the transistors may be contacted with source line  18  and can be tied to ground potential. The gates may be contacted and tied together by conductive line  52  for a row of cells as shown in  FIG. 9H . In one embodiment, the drain contacts  21  may be tied to the individual memory cells through the bottom electrodes  18  as illustrated in  FIG. 8I . At this point the same process flow shown in  FIG. 8F to 8I  may be followed to achieve the MRAM devices illustrated in  FIGS. 2 ,  4 ,  5 ,  6 , and  7 . Simple differences in process steps which are obvious to one skilled in art may be ignored. 
     Embodiments of the present invention also extend to a memory device comprising an array on nanotube-based MRAM cells as disclosed herein. 
     Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader spirit of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense.