Abstract:
The present invention proposes the use of a silicon nitride layer on top of a second conductive layer. After a step of etching a second conductive layer, an oxide spacer is formed to define a gap. Then, another silicon nitride layer fills up the gap. After that, the oxide spacer is removed. Later, a first conductive layer is etched to separate the digit line to cell contact line.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to a method of fabricating a digit line and a cell contact. 
         [0003]    2. Description of the Prior Art 
         [0004]    A dynamic random access memory (DRAM) device comprises an arrangement of individual memory cells. Each memory cell includes a capacitor capable of holding data as an electrical charge and an access transistor for accessing the charge stored on the capacitor. The data is transmitted on signal lines, referred to as bit lines, or digit lines. The digit line is coupled directly to a source doping region of an access transistor for a particular memory cell. A cell contact couples to a drain doping region of the access transistor for transfer the data from the digit line to the capacitor. The digit line and the cell contact are usually fabricated as metal, silicide or polysilicon. 
         [0005]    As the market pressure to increase the memory cell density is continuously growing. A unique fabrication process is needed to reduce the size of the memory cells, and provide an easier approach to form digit lines and cell contacts. 
       SUMMARY OF THE INVENTION 
       [0006]    The present invention aims at fabricating a cell contact and a digit line for a semiconductor device such as a DRAM. 
         [0007]    According to one aspect of the invention, a method of fabricating a cell contact and a digit line for a semiconductor device comprises the step as follows. First, a substrate is provided. Then, a first conductive layer, a second conductive layer, a first silicon nitride layer are formed from bottom to top on the substrate. Next, the first silicon nitride layer and the second conductive layer are patterned to form a plurality of line-shaped masks. Later, a pair of spacers are formed at two sides of each of the line-shaped masks respectively, wherein a gap is defined between the spacers. After that, a second silicon nitride layer is formed to fill up the gap. Then, the spacers are removed. Finally, part of the first conductive layer is removed by taking the second silicon nitride layer and the line-shaped masks as a mask. 
         [0008]    According to another aspect of the invention, a method of fabricating a cell contact and a digit line for a semiconductor device is provided, wherein the cell contact and the digit line are formed on a substrate, the substrate includes an active area extending along a first direction, a plurality of trench isolations and a plurality of STI structures arranged in the substrate alternately and extending along a second direction, the trench isolations and the STI structures intersect the active area respectively, a drain doping region is disposed in the active area between one of the trench isolations and one of the STI structures, a source doping region is disposed in the active area between one of the trench isolations and one of the STI structures next to the drain doping region. The method comprises the steps as follows. First, a first conductive layer, a second conductive layer, a first silicon nitride layer are formed from bottom to top on the active area, the trench isolations, and the STI structures. Then, the first silicon nitride layer and the second conductive layer are patterned to form a plurality of line-shaped masks extending along the second direction. Later, a pair of spacers are formed at two sides of each of the line-shaped masks so as to form a first gap between the spacers. Next, a second silicon nitride layer is formed to fill up the first gap. Subsequently, the spacers are removed to form a second gap between one of the line-shaped masks and the second silicon nitride layer, wherein the first conductive layer directly above the trench isolations and the STI structures is exposed through the second gap. Finally, the exposed first conductive layer is removed by taking the line-shaped masks and the second silicon nitride layer as a mask. 
         [0009]    These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0010]    The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: 
           [0011]      FIG. 1  to  FIG. 14  are schematic diagrams showing a method of fabricating a cell contact and a digit line for a semiconductor device. 
       
    
    
       [0012]    It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. 
       DETAILED DESCRIPTION 
       [0013]    In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations and process steps are not disclosed in detail. 
         [0014]    Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the figures. Also, in which multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration and description thereof, like or similar features will ordinarily be described with like reference numerals. 
         [0015]      FIG. 1  to  FIG. 14  are schematic diagrams showing a method of fabricating a cell contact and a digit line for a semiconductor device.  FIG. 1  is a schematic layout diagram showing a portion of a cell array in accordance with one preferred embodiment of this invention.  FIG. 2  shows a schematic, cross-sectional view of the cell array of the invention, which are taken along line AA′ (reference x-axis direction). 
         [0016]    Please refer to  FIG. 1  and  FIG. 2 , a substrate  10  is provided. The substrate  10  may be a semiconductor substrate including but not limited to silicon substrate, silicon substrate with an epitaxial layer, SiGe substrate, silicon-on-insulator (SOI) substrate, gallium arsenide (GaAs) substrate, gallium arsenide-phosphide (GaAsP) substrate, indium phosphide (InP) substrate, gallium aluminum arsenic (GaAlAs) substrate, or indium gallium phosphide (InGaP) substrate. The substrate  10  includes a first active area  12 , a second active area  14 , and an insulating  16  area such as a field oxide sandwiched between the first active area  12  and the second active area  14 . The first active area  12 , the second active area  14  and the insulating area  16  extend along the reference x-axis direction. Numerous trench isolations  18  and STI structures  20  are arranged in the substrate  10  alternately and extend along the reference y-axis direction. The reference x-axis direction is perpendicular to the reference y-axis direction. The trench isolations  18  and the STI structures  20  intersect with the first active area  12 , the insulating area  16 , and the second active area  14 . A gate electrode  22  is embedded in the insulating area  16  and extends along the reference x-axis direction. 
         [0017]    A first drain doping region  24  is disposed in the first active area  12  between one of the trench isolations  18  and one of the STI structures  20 . A first source doping region  26  is disposed in the first active area  12  between one of the trench isolations  18  and one of the STI structures  20 , and the first source doping region  26  is next to the first drain doping region  24 . A second drain doping region  28  is disposed in the second active area  14  between one of the trench isolations  18  and one of the STI structures  20 . A second source doping region  30  is disposed in the second active area  14  between one of the trench isolations  18  and one of the STI structures  20 , and the second source doping region  30  is next to the second drain doping region  28 . For the sake of brevity,  FIG. 2  only shows a cross-sectional view of the first active area  12 , because the cross-sectional view of the second active area  14  is substantially identical to that of the first active area  12 . 
         [0018]      FIG. 3  is a schematic layout diagram showing a portion of a cell array covered with a patterned photoresist in accordance with one preferred embodiment of this invention.  FIG. 4  shows a schematic, cross-sectional view of  FIG. 3 , which are taken along line BB′ (reference x-axis direction). 
         [0019]    As shown in  FIG. 3  and  FIG. 4 , a first conductive layer  32 , a second conductive layer  34  and a silicon nitride layer  36  are formed from bottom to top on the surface of the substrate  10 . The first conductive layer  32 , the second conductive layer  34  and the silicon nitride layer  36  cover the first active area  12 , the second active area  14 , the STI structures  20 , the trench isolations  18  and the insulating area  16 . The first conductive layer  32  may comprise TiN, W, Ti, WN, polysilicon or combinations thereof. The second conductive layer  34  may be W. Then, a patterned photoresist  38  is formed on the silicon nitride layer  36 . The patterned photoresist  38  is line-shaped and overlaps with the first drain doping region  24 , the second drain doping region  28 , part of the STI structures  20  and part of the trench isolations  18 . The patterned photoresist  38  extends along the reference y-axis direction. 
         [0020]    As show in  FIG. 5 , the silicon nitride layer  36  and the second conductive layer  34  are etched by taking the patterned photoresist  38  as a mask so that a plurality of line-shaped masks  40  extends along the reference y-axis direction are formed. The line-shaped masks  40  are composed of the silicon nitride layer  36  and the second conductive layer  34 . Furthermore, the width of one line-shaped mask  40  is preferably about 20 nm. The space between two adjacent line-shaped masks  40  is preferably around 40 nm. 
         [0021]    Moreover, the line-shaped masks  40  cover the first conductive layer  32  directly on the first drain doping region  24  and the second drain doping region (not shown). In other words, the first conductive layer  32  directly on the first source doping region  26 , the second source doping region (not shown), part of the STI structures  20  and part of the trench isolations  18  is exposed. 
         [0022]    Later, a pair of spacers  42  are formed on the two opposite sides of each of the line-shaped masks  40 . The width of one of the spacers  42  is preferably 10 to 12 nm. In this way, a first gap G 1  is defined between the spacers  42 . Now, the first conductive layer  32  directly on the first source doping region  26  and the second source doping region (not shown) is exposed through first gap G 1 . Next, a silicon nitride layer  44  is formed blankly to fill up the first gap G 1 . 
         [0023]    As shown in  FIG. 6 , the silicon nitride layer  44  is planarized so that the top surface of the silicon nitride layer  44  is aligned with the silicon nitride layer  36 . Then, the spacers  42  are removed so as to form a second gap G 2  between one of the line-shaped masks  42  and the silicon nitride layer  44 . The spacers  42  can be removed by a wet etch process with excellent selectivity to the first conductive layer  32 , the second conductive layer  34  and the silicon nitride layer  36 . Now, the first conductive layer  32  directly on the trench isolations  18  and STI structures  20  is exposed. 
         [0024]      FIG. 7  is a schematic layout diagram showing a formation of a digit line and a cell contact line.  FIG. 8  shows a schematic, cross-sectional view of  FIG. 7 , which is taken along line CC′ (reference x-axis direction).  FIG. 8  shows a schematic, cross-sectional view of  FIG. 7 , which is taken along line DD′ (reference x-axis direction). 
         [0025]    As shown in  FIG. 7 , the line CC′ crosses the first active area  12  and the line DD′ crosses one of the insulating areas  16 . 
         [0026]    As shown in  FIG. 7  and  FIG. 8 , the first conductive layer  32  directly on the trench isolations  18  and STI structures  20  is etched by taking the line-shaped masks  40  and the silicon nitride layer  44  as a mask. Now, the first contact layer  32  directly on the first source doping region  26  and the second source doping region  30  serves as a digit line DL. The first conductive layer  32  and the second conductive layer  34  directly on the first drain doping region  24  and the second drain doping region  28  becomes a cell contact line CL, which will be segmented to become many individual cell contacts afterwards. Furthermore, as shown in  FIG. 7  and  FIG. 9 , the cell contact line CL and the digit line DL both extend along the reference y-axis direction continuously. 
         [0027]      FIG. 10  is a schematic layout diagram showing a step of segmenting the cell contact line.  FIG. 11  shows a schematic, cross-sectional view of  FIG. 10 , which is taken along line EE′ (reference x-axis direction).  FIG. 12  shows a schematic, cross-sectional view of  FIG. 10 , which is taken along line FF′ (reference x-axis direction). The line EE′ crosses the first active area  12  and the line FF′ crosses the insulating area  16 . 
         [0028]    Please refer to  FIGS. 10 to 12 . The cell contact line CL is separated into individual cell contacts CC by removing the cell contact line CL directly on the insulating area  16  partly without chopping off the digit line DL. The cell contact line CL may be removed by a dry etch process. 
         [0029]      FIG. 13  is a schematic layout diagram showing a step of forming a capacitor.  FIG. 14  shows a schematic, cross-sectional view of  FIG. 13 , which is taken along line GG′ (reference x-axis direction). 
         [0030]    Please refer to  FIG. 13  and  FIG. 14 , the silicon nitride layer  36  on the cell contacts CC is removed. Then, at least one capacitor  46  is formed to couple one of the cell contacts CC. Now, a DRAM is completed. 
         [0031]    Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.