Abstract:
An amplitude detector is disclosed passing only video input signals whose voltage amplitudes are within specified minimum and maximum limits, and is particularly useful in a secondary radar system for filtering out FRUIT, friendly replies to unintentionally interogated targets. A pair of comparators (4 and 31) compare the video input signal (2) against respective first and second threshold voltages (V th1 ) and V th2 ). The outputs (30 and 33) of the comparators (4 and 31) and AND&#39;ed (34) with each other and with a digitized video signal (32) to actuate a one-shot pulse generator (12) for gating (36) a delayed digital video signal (40) through an output AND gate (22) to yield a video output signal (42).

Description:
BACKGROUND AND SUMMARY 
     The invention arose during development efforts relating to amplitude detectors for secondary radar systems for filtering out replies responding to other systems, i.e. FRUIT, friendly replies to unintentionally interrogated targets, though the invention is not limited thereto. 
     It is known in the prior art to filter out some of the FRUIT by establishing a minimum threshold voltage that the reply video signal must exceed in order to be accepted. The problem with this system is that there is no upper limit. 
     The present invention provides a system which establishes both minimum and maximum limits that the reply video signal must be between in order to be accepted. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is circuit diagram of a secondary radar system peak detector known in the prior art. 
     FIG. 2 is a timing diagram illustrating operation of the circuit of FIG. 1. 
     FIG. 3 is a circuit diagram showing a secondary radar system amplitude detector in accordance with the invention. 
     FIG. 4 is a timing diagram illustrating operation of the circuit of FIG. 3. 
    
    
     DETAILED DESCRIPTION 
     Description of Prior Art 
     FIG. 1 shows an amplitude detector circuit for passing only the log video input signal coming from the transponder of a secondary radar system whose voltage amplitude is greater than a level slightly below the given limit, i.e. is greater than a level slightly below the expected amplitude. This helps to filter out FRUIT. The video input signal on line 2 is shown in the first timing line in FIG. 2, showing a series of first, second, third and fourth pulses, with a typical pulse width of 450 nanoseconds. The amplitude of the first pulse is above level &#34;a&#34; but below the minimum expected value at level &#34;b&#34;. The amplitude of the second pulse is much greater than the highest expected value &#34;b&#34; and is in fact higher than the highest expected level &#34;c&#34;. The third and fourth pulses have amplitudes at approximately the expected value, namely greater than &#34;b&#34; and less than &#34;c&#34;. The circuit in FIG. 1 will pass the second, third and fourth pulses. 
     Comparator 4 in FIG. 1 compares the video input signal on line 2 against a given threshold voltage V th  on line 6 provided by curve generator 8 as a function of time when triggered by its trigger input responsive to the video input signal on line 2. As shown in the third timing line in FIG. 2, the threshold voltage on line 6 is initially at level &#34;b&#34; and decays with time, as shown by the downward slope of the solid line, representing V th , relative to the dashed horizontal reference line. When the video input signal voltage on line 2 rises above the threshold voltage on line 6, or above a given value relative thereto, comparator 4 generates an output signal on line 10 which triggers retriggerable one-shot element 12, for example an edge transition sensitive Schmitt trigger which responds to the leading edge of the pulse on line 10 to generate a pulse of given width, which pulse is Or&#39;ed at Or gate 14 with the signal on line 10 to produce the video gate signal on line 16 as shown in the fourth timing line in FIG. 2. Video processor 18 quantizes the video input signal on line 2 to a digital video signal on line 20, as shown in the second timing line in FIG. 2, which digital video signal has a typical 450 nanosecond pulse width and a typical 100 nanosecond delay from the leading edge of the pulse on line 2. The digital video signal on line 20 is AND&#39;ed with the video gate signal on line 16 at output AND gate 22 to yield a video output signal on line 24, as shown in the last timing line in FIG. 2. One-shot element 12 maintains a given pulse width to ensure gating of digital video signal 20 even if the output of comparator 4 has stabilized. OR gate 14 provides minimum initial delay of video gating signal 16. The circuit passes the second, third and fourth pulses, as shown in the last timing line in FIG. 2. 
     DESCRIPTION OF THE INVENTION 
     FIG. 3 shows a dual threshold amplitude detector circuit for a secondary radar system for filtering out FRUIT by passing only video input signals whose voltage amplitudes are within specified minimum and maximum limits. The first timing line in FIG. 4 is identical to that in FIG. 2. The circuit in FIG. 3 pssses only the third and fourth pulses. 
     Curve generator 8 in FIG. 3 provides a first threshold voltgge, V th1 , on line 6 as in FIG. 1. There is additionally provided a second voltage threshold, V th2 , on line 26 by means of voltage offset element 28, such as an amplifier. In the preferred embodiment, V th1  is initially set at level &#34;b&#34; as in FIG. 1, and an additional &#34;+b&#34; offset is selected to raise V th2  up to level &#34;c&#34;, as shown in the third timing line in FIG. 4. V th1  and V th2  decay with time, as shown by the downward slope of the respective solid lines, relative to the respective dashed horizontal reference lines. Alternatively, the curve generator means may include a second curve generator to generate V th2  when it is desired that V th1  and V th2  be independent of each other. 
     First comparator 4 compares the video input signal on line 2 against the first threshold voltage on line 6 and generates an output signal on line 30 when the input video signal voltage is greater than the first threshold voltage V th1 , or greater than a given value relative thereto. A second comparator 31 compares the video input signal on line 2 against the second threshold voltage on line 26 and generates an output signal on line 33 when the input video signal voltage is less than the second threshold voltage V th2 , or less than a given value relative thereto. Video processor 18 quantizes the video input signal on line 2 to a digital video signal on line 32, as in FIG. 1, and as shown in the second timing line in FIG. 4. 
     First AND gate 34 AND&#39;s the output signal on line 30 from first comparator 4 and the output signal on line 33 from second comparator 31 and the digital video signal on line 32 from video processor 18, and generates an output signal on line 35 when each of the three last mentioned signals are in a given state. For example, when the video input signal on line 2 has an amplitude between levels &#34;b&#34; and &#34;c&#34;, as shown in the third and fourth pulses in FIG. 4, the output of comparator 4 on line 30 will be high because the video input signal voltage is greater than V th1 , and the output of comparator 31 on line 33 will be high because the video input signal voltage will be less than V th2 . Lines 30 and 33 will thus be high, and line 32 is also high, and hence the output of AND gate 34 on line 35 goes high. 
     Retriggerable one-shot element 12 receives the high output signal on line 35 from AND gate 34 and is triggered by the leading edge thereof to generate an output signal of given pulse width on line 36, as shown in the fourth timing line in FIG. 4, with a delay due to the propagation delay of elements 34 and 12. Delay element 38, for example a counter or the like, delays the digital video signal on line 32 and outputs a delayed digital video signal on line 40, as shown in the fifth timing line in FIG. 4. The amount of delay &#34;d&#34; is selected to compensate for the propagation delay through elements 34 and 12, and is preferably greater than the sum of such propagation delays but less than 100 nanoseconds. 
     Output AND gate 22 ANDs the delayed digital video signal on line 40 and the output of one-shot element 12 on video gate line 36 and generates the video output signal on line 42, as shown in the last timing line in FIG. 4. As shown in the first and the last timing lines in FIG. 4, the circuit in FIG. 3 does not pass signals below the minimum limit &#34;b&#34; or above the maximum limit &#34;c&#34;, for example, the first and second pulses, respectively. The circuit passes only those pulses within such minimum and maximum limits, for example, the third and fourth pulses. 
     The invention reduces FRUIT beyond prior techniques, and yields higher target capacities, higher detection probabilities and lower false alarm rates than prior secondary radar systems. 
     It is recognized that various equivalents, alternatives and modifications are possible within the scope of the appended claims.