Abstract:
A gate line driving module used on a liquid crystal display uses clock signal sources in replacement of a high level gate power source, such that the phenomenon of device characteristic drift occurring in the foregoing related art is avoided. The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. A pair of neighboring odd-pixel gate line driving circuit and even-pixel gate line driving circuit exchange output signals thereof with each other in a forward or feedback manner for ensuring that each the odd-pixel gate line driving circuit and each the even-pixel gate line driving circuit are driven once. The auxiliary gate line driving circuit is used for ensuring that signal iteration of the gate line driving module is under normal operation.

Description:
BACKGROUND OF THE DISCLOSURE 
     1. Field of the Disclosure 
     The disclosure relates to a gate line driving module for a liquid crystal display (LCD), and more particularly, the disclosure relates to a gate line driving module and an LCD which use clock signals to serve as a high level gate power source. 
     2. Description of Related Art 
       FIG. 1  is a schematic view of a typical thin film transistor liquid crystal display (TFT-LCD)  100 . As shown in  FIG. 1 , the TFT-LCD  100  includes a liquid crystal (LC) panel  110 , a gate line driver  120 , and a plurality of data line drivers  130 ,  140 , and  150 . The gate line driver  120  and the data line drivers  130 ,  140 , and  150  drive corresponding thin film transistors (TFTs) on the LC panel  110 . In order to reduce the cost of manufacturing TFT-LCDs, it is currently considered that the gate line driver and the LC panel are fabricated on the glass substrate in an identical process. By such a manner, the cost of additionally disposing the gate line driver on the LCD and the area of the integrated circuit are both saved. 
     However, fabricating the gate line driver on the glass substrate in the amorphous silicon process has the limitation of which the gate line driver is simply implemented by N-type TFTs. As a result, a high level gate power source of the gate line driver must be supplied, such that the switch states of the internal switches are determined. However, the electron mobility of amorphous silicon is relatively low, width to length (W/L) ratios of the N-type TFTs adopted in the gate line driver must be relatively high to offset the low electron mobility of amorphous silicon. As a result, internal parasitic capacitance of the gate line driver is increased, such that the phenomenon of coupling between internal signals of the gate line driver is easily generated due to the increase of the parasitic capacitance. Accordingly, the output signals of the gate line driver creates a ripple effect, such that the display quality of the LC panel is affected. Furthermore, in the gate line driver, the N-type TFTs which are affected by bias over a long period of time have the phenomenon of device characteristic drift, so as to affect the operation of the gate line driver. 
     SUMMARY OF THE DISCLOSURE 
     An exemplary embodiment of the disclosure provides a gate line driving module for a liquid crystal display (LCD). The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. A signal input source is coupled to a signal input end of a first-stage odd-pixel gate line driving circuit of the odd-pixel gate line driving circuits or a signal input end of a first-stage even-pixel gate line driving circuit of the even-pixel gate line driving circuits, and the signal input source is also coupled to a signal feedback end of the auxiliary gate line driving circuit. A first clock signal source is coupled to a first clock signal input end of each of the odd-pixel gate line driving circuits, a first clock signal input end of each of the even-pixel gate line driving circuits, and a first clock signal input end of the auxiliary gate line driving circuit. A second clock signal source is coupled to a second clock signal input end of each of the odd-pixel gate line driving circuits, a second clock signal input end of each of the even-pixel gate line driving circuits, and a second clock signal input end of the auxiliary gate line driving circuit. The first clock signal source and the second clock signal source are inverted from each other. The first clock signal source and the second clock signal source serve as a high level gate power source of the odd-pixel gate line driving circuits, the even-pixel gate line driving circuits, or the auxiliary gate line driving circuit. Transistors of the odd-pixel gate line driving circuits, the even-pixel gate line driving circuits, and the auxiliary gate line driving circuit are N-type thin film transistors (TFTs). The gate line driving module is fabricated with a liquid crystal (LC) panel of the LCD in an identical amorphous silicon process. 
     Another exemplary embodiment of the disclosure provides an LCD. The LCD includes a plurality of data line driving circuits and an LC panel module. The LC panel module includes an LC panel and a gate line driving module. The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. The gate line driving module and the data line driving circuits drive corresponding TFTs on the LC panel. A signal input source is coupled to a signal input end of a first-stage odd-pixel gate line driving circuit of the odd-pixel gate line driving circuits or a signal input end of a first-stage even-pixel gate line driving circuit of the even-pixel gate line driving circuits. The signal input source is also coupled to a signal feedback end of the auxiliary gate line driving circuit. A first clock signal source is coupled to a first clock signal input end of each of the odd-pixel gate line driving circuits, a first clock signal input end of each of the even-pixel gate line driving circuits, and a first clock signal input end of the auxiliary gate line driving circuit. A second clock signal source is coupled to a second clock signal input end of each of the odd-pixel gate line driving circuits, a second clock signal input end of each of the even-pixel gate line driving circuits, and a second clock signal input end of the auxiliary gate line driving circuit. The first clock signal source and the second clock signal source are inverted from each other. The first clock signal source and the second clock signal source serve as a high level gate power source of the odd-pixel gate line driving circuits, the even-pixel gate line driving circuits, or the auxiliary gate line driving circuit. Transistors of the odd-pixel gate line driving circuits, the even-pixel gate line driving circuits, and the auxiliary gate line driving circuit are N-type thin film transistors (TFTs). The gate line driving module is fabricated with a liquid crystal (LC) panel of the LCD in an identical amorphous silicon process. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. 
         FIG. 1  is a schematic view of a typical TFT-LCD. 
         FIG. 2  is a schematic diagram of a TFT-LCD using a gate line driving module according to an embodiment of the disclosure. 
         FIG. 3  is a schematic diagram of the gate line driving module according to an embodiment of the disclosure. 
         FIG. 4  illustrates a schematic circuit diagram which is implemented as one odd-pixel gate line driving circuit of the odd-pixel gate line driving circuits shown in  FIG. 3 . 
         FIG. 5  illustrates a schematic circuit diagram which is implemented as one even-pixel gate line driving circuit of the odd-pixel gate line driving circuits shown in  FIG. 3 . 
         FIG. 6  illustrates schematic waveforms of each nodes of the odd-pixel gate line driving circuit implemented with the odd-pixel gate line driving circuit shown in  FIG. 4 . 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
       FIG. 2  is a schematic diagram of a TFT-LCD  200  using a gate line driving module  300  according to an embodiment of the disclosure. As shown in  FIG. 2 , the TFT-LCD  200  includes a liquid crystal (LC) panel module  210  and a plurality of data line driving circuits  230 ,  240 , and  250 . The LC panel module  210  includes an LC panel  220  and the gate line driving module  300 . The LC panel  220  and the gate line driving module  300  are fabricated into the LC panel module  210  in an identical (or substantially similar) amorphous silicon process. 
       FIG. 3  is a schematic diagram of the gate line driving module  300  according to an embodiment of the disclosure. As shown in  FIG. 3 , the gate line driving module  300  has 240 gate line driving circuits including a 1 st  stage gate line driving circuit C_ 1 , a 2 nd  stage gate line driving circuit C_ 2 , a 3 rd  stage gate line driving circuit C_ 3 , . . . , a 239 th  stage gate line driving circuit C_ 239 , and a 240 th  stage gate line driving circuit C_ 240  and an auxiliary gate line driving circuit  350 . Herein, internal devices and physical wiring of the 240 gate line driving circuits and the auxiliary gate line driving circuit  350  are identical, and the difference thereof simply lies in the clock input sources or the signal input sources coupled thereto. In  FIG. 3 , it is assumed that the odd th  stage gate line driving circuits, such as the 1 st  stage gate line driving circuit C_ 1  and the 3 rd  stage gate line driving circuit C_ 3 , are odd-pixel gate line driving circuits, and also, it is assumed that the even th  stage gate line driving circuits, such as the 2 nd  stage gate line driving circuit C_ 2  and the 240 th  stage gate line driving circuit C_ 240 , are even-pixel gate line driving circuits. However, in other embodiments of the disclosure, the odd th  stage gate line driving circuits may be the even-pixel gate line driving circuits, and the even th  even stage gate line driving circuits may be the odd-pixel gate line driving circuits. In other words, in the gate line driving module  300  disclosed in the disclosure, except for the auxiliary gate line driving circuit, one of the two neighboring gate line driving circuits is the odd-pixel gate line driving circuit, and the other is the even-pixel gate line driving circuit. 
     In the gate line driving module  300  shown in  FIG. 3 , four different kinds of signal sources or power sources including a signal input source STV, a low level gate power source VGL, a positive clock signal source CLK, and a negative clock signal source CLKB are further used. 
     The signal input source STV is a start driving signal which is externally inputted and is directly inputted to a signal input end FA of a 1 st  stage gate line driving circuit C_ 1  and a signal feedback end FB of the auxiliary gate line driving circuit  350 . 
     The positive clock signal source CLK is coupled to a positive clock signal input end CLK′ of the odd-pixel gate line driving circuits C_ 1 , C_ 3 , . . . , and C_ 239 , a positive clock signal input end CLK′ of the even pixel gate line driving circuits C_ 2 , C_ 4 , . . . , and C_ 240 , and a positive clock signal input end CLK′ of the auxiliary gate line driving circuit  350 . The negative clock signal source CLKB is coupled to a negative clock signal input end CLKB′ of the odd-pixel gate line driving circuits C_ 1 , C_ 3 , . . . , and C_ 239 , a negative clock signal input end CLKB′ of the even pixel gate line driving circuits C_ 2 , C_ 4 , . . . , and C_ 240 , and a negative clock signal input end CLKB′ of the auxiliary gate line driving circuit  350 . The positive clock signal source CLK and the negative clock signal source CLKB are inverted from each other. That is, the phase difference thereof is 180 degrees. It should be noted that, the high levels of the positive clock signal source CLK and the negative clock signal source CLKB both approximate to the level of the high level gate power source used in the foregoing related art. Accordingly, the positive clock signal source CLK and the negative clock signal source CLKB can be used to start each of the gate line driving circuits of the gate line driving module  300 . 
     The low level gate power source VGL is coupled to a low level gate power source input end VGL′ of the odd-pixel gate line driving circuits C_ 1 , C_ 3 , . . . , and C_ 239 , a low level gate power source input end VGL′ of the even pixel gate line driving circuits C_ 2 , C_ 4 , . . . , and C_ 240 , and a low level gate power source input end VGL′ of the auxiliary gate line driving circuit  350 . 
     Additionally, the configuration of signal input and output between each gate line driving circuit of the gate line driving module  300  adopts both of forward and feedback. Except for the 1 st  stage gate line driving circuit C_ 1  and the auxiliary gate line driving circuit  350 , a signal input end FA of each stage gate line driving circuit is coupled to a signal output end Output of the gate line driving circuit of the previous stage thereof, and a signal output end Output of each stage gate line driving circuit is coupled to a signal feedback end FB of the gate line driving circuit of the previous stage thereof. Accordingly, each of the gate line driving circuits forwards the output signal thereof to the gate line driving circuit of the next stage thereof and feeds back the output signal thereof to the gate line driving circuit of the previous stage thereof. However, because the 1 st  stage gate line driving circuit C_ 1  has no the gate line driving circuit of the previous stage, the output signal of the 1 st  stage gate line driving circuit C_ 1  is unnecessarily fed back to the gate line driving circuit of the absent previous stage thereof, and the output signal is simply forwarded to the gate line driving circuit C_ 2  of the next stage thereof. 
       FIG. 4  illustrates a schematic circuit diagram which is implemented as one odd-pixel gate line driving circuit C_Odd of the odd-pixel gate line driving circuits shown in  FIG. 3 . In other words, the odd-pixel gate line driving circuit C_Odd may be one of the odd-pixel gate line driving circuits C_ 1 , C_ 3 , . . . , and C_ 239  shown in  FIG. 3 . As shown in  FIG. 4 , the odd-pixel gate line driving circuit C_Odd includes a 1 st  N-type TFT M 1 , a 2 nd  N-type TFT M 2 , a 3 rd  N-type TFT M 3 , a 4 th  N-type TFT M 4 , a 5 th  N-type TFT M 5 , a 6 th  N-type TFT M 6 , a 7 th  N-type TFT M 7 , an 8 th  N-type TFT M 8 , and a capacitor C 1 . The gate of the 1 st  N-type TFT M 1  is coupled to the drain of the 1 st  N-type TFT M 1 . The drain of the 2 nd  N-type TFT M 2  is coupled to the source of the 1 st  N-type TFT M 1 . The gate of the 3 rd  N-type TFT M 3  is coupled to the drain of the 3 rd  N-type TFT M 3 . The source of the 3 rd  N-type TFT M 3  is coupled to the gate of the 2 nd  N-type TFT M 2 . The drain of the 4 th  N-type TFT M 4  is coupled to the source of the 3 rd  N-type TFT M 3 . The source of the 5 th  N-type TFT M 5  is coupled to the gate of the 2 nd  N-type TFT M 2 . The gate of the 6 th  N-type TFT M 6  is coupled to the source of the 1 st  N-type TFT M 1 . The source of the 6 th  N-type TFT M 6  is coupled to the gate of the 4 th  N-type TFT M 4 . The gate of the 7 th  N-type TFT M 7  is coupled to the gate of the 2 nd  N-type TFT M 2 . The drain of the 7 th  N-type TFT M 7  is coupled to the source of the 6 th  N-type TFT M 6 . The drain of the 8 th  N-type TFT M 8  is coupled to the source of the 6 th  N-type TFT M 6 . The first end of the capacitor C 1  is coupled to the gate of the 6 th  N-type TFT. The second end of the capacitor C 1  is coupled to the source of the 6 th  N-type TFT. 
     When the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4  is the 1 st  stage gate line driving circuit C_ 1 , the signal input source STV is coupled to the drain of the 1 st  N-type TFT M 1 . However, when the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4  is the other stage gate line driving circuit, e.g. C_ 3 , instead of the 1 st  stage gate line driving circuit C_ 1 , the signal end coupled to the drain of the 1 st  N-type TFT M 1  is the signal output end Output of the even-pixel gate line driving circuit of the previous stage thereof, e.g. C_ 2 . In other words, in each of the odd-pixel gate line driving circuits, the drain of the 1 st  N-type TFT M 1  is coupled to the signal input end FA of the odd-pixel gate line driving circuit. 
     In the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4 , the positive clock signal input end CLK′ is coupled to the drain of the 3 rd  N-type TFT M 3  and the drain of the 6 th  N-type TFT M 6 , and the negative clock signal input end CLKB′ is coupled to the gate of the 5 th  N-type TFT M 5  and the gate of the 8 th  N-type TFT M 8 . 
     In the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4 , the low level gate power source input end VGL′ is coupled to the source of the 2 nd  N-type TFT M 2 , the source of the 4 th  N-type TFT M 4 , the source of the 7 th  N-type TFT M 7 , and the source of the 8 th  N-type TFT M 8 . 
     In the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4 , the signal output end Output thereof is coupled to the drain of the 8 th  N-type TFT M 8 , and the signal feedback end FB thereof is coupled to the drain of the 5 th  N-type TFT M 5 . 
       FIG. 5  illustrates a schematic circuit diagram which is implemented as one even-pixel gate line driving circuit C_Even of the odd-pixel gate line driving circuits shown in  FIG. 3 . In other words, the even-pixel gate line driving circuit C_Even may be one of the even-pixel gate line driving circuits C_ 2 , C_ 4 , . . . , and C_ 240  shown in  FIG. 3 . As shown in  FIG. 5 , the even-pixel gate line driving circuit C_Even includes a 9 th  N-type TFT M 9 , a 10 th  N-type TFT M 10 , a 11 th  N-type TFT M 11 , a 12 th  N-type TFT M 12 , a 13 th  N-type TFT M 13 , a 14 th  N-type TFT M 14 , a 15 th  N-type TFT M 15 , a 16 th  N-type TFT M 16 , and a capacitor C 2 . It should be noted that, the 9 th  N-type TFT M 9  corresponds to the 1 st  N-type TFT M 1 , the 10 th  N-type TFT M 10  corresponds to the 2 nd  N-type TFT M 2 , the 11 th  N-type TFT M 11  corresponds to the 3 rd  N-type TFT M 3 , the 12 th  N-type TFT M 12  corresponds to the 4 th  N-type TFT M 4 , the 13 th  N-type TFT M 13  corresponds to the 5 th  N-type TFT M 5 , the 14 th  N-type TFT M 14  corresponds to the 6 th  N-type TFT M 6 , the 15 th  N-type TFT M 15  corresponds to the 7 th  N-type TFT M 7 , the 16 th  N-type TFT M 16  corresponds to the 8 th  N-type TFT M 8 , and the capacitor C 2  corresponds to the capacitor C 1 . The connection between each device shown in  FIG. 5  corresponds to that between each device shown in  FIG. 4 , and thus, it will not be described again herein. It should be noted that, the difference of the even-pixel gate line driving circuit C_Even and the odd-pixel gate line driving circuit C_Odd lies in that the positions coupled to the positive clock signal end CLK′ and the negative clock signal end CLKB′ are opposite. For example, in  FIG. 5 , the positive clock signal end CLK′ is coupled to the gate of the 13 th  N-type TFT M 13  and the gate of the 16 th  N-type TFT M 16 , and the negative clock signal end CLKB′ is coupled to the drain of the 11 th  N-type TFT M 11  and the drain of the 14 th  N-type TFT M 14 . 
     When the 240 th  stage gate line driving circuit C_ 240  is an odd-pixel gate line driving circuit, the configuration and the signal connection of the auxiliary gate line driving circuit  350  are the same as those of the even-pixel gate line driving circuit C_Even shown in  FIG. 5 . When the 240 th  stage gate line driving circuit C_ 240  is an even-pixel gate line driving circuit, the configuration and the signal connection of the auxiliary gate line driving circuit  350  are the same as those of the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4 . Accordingly, the configuration and the signal connection of the auxiliary gate line driving circuit will not be described again herein. The functions of the auxiliary gate line driving circuit  350  are to receive the output signal of the 240 th  stage gate line driving circuit C_ 240  by the signal input end FA thereof, to feed back the output signal thereof to the 240 th  stage gate line driving circuit C_ 240 , and to forward the output signal thereof to the 1 st  stage gate line driving circuit C_ 1 . In other words, the function of the auxiliary gate line driving circuit  350  is to serve as a dummy gate line driving circuit to maintain the normal operation of the gate line driving module  300 . That is, the auxiliary gate line driving circuit  350  is not used to drive any gate line in fact. 
       FIG. 6  illustrates schematic waveforms of each nodes of the odd-pixel gate line driving circuit C_ 1  implemented with the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4 . The operation of the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4  is described according to  FIG. 6  as follows. It should be noted that, the level of the positive clock signal input end CLK′ is synchronic with that of the positive clock signal input source CLK, and the level of the negative clock signal input end CLKB′ is synchronic with that of the negative clock signal input source CLKB. The levels OutPut_C_ 1 , Output_C_ 2 , and Output_C_ 3  respectively correspond to the levels of the signal output ends of the gate line driving circuits C_ 1 , C_ 2 , and C_ 3 . 
     First of all, the signal input source STV used to start the gate line driving module  300  has the high level during the period P 1  shown in  FIG. 6  because it is triggered at start. Accordingly, the 1 st  N-type TFT M 1  is turned on, and the level of the node t 11  shown in  FIG. 4  is raised up by a specific degree as shown in  FIG. 6 . The raised level of the node t 11  during the period P 1  approximates to the high level of the positive clock signal source CLK or the negative clock signal source CLKB. Next, the 6 th  N-type TFT M 6  is turned on by the high level of the node t 11 , and further, because the 8 th  N-type TFT M 8  is turned on by the high level of the negative clock signal end CLKB′, the level of the signal output end Output approximates to the low level of the positive clock signal end CLK′ or the low level gate power source VGL in the meanwhile, so as to form the low level of the level OutPut_C_ 1  shown in  FIG. 6  during the period P 1 . 
     Thereafter, when the timing goes into the period P 2 , and the signal input source STV becomes low, the positive clock signal end CLK′ becomes high, and the negative clock signal end CLKB′ becomes low, such that the 5 th  N-type TFT M 5  and the 8 th  N-type TFT M 8  are turned off, and the 3 rd  N-type TFT M 3  is turned on. At this time, because the voltage difference between the gate and the source of the 6 th  N-type TFT M 6  is stored in the capacitor C 1 , the level of the node t 11  is raised up again during the period P 2  as shown in  FIG. 6 , and the raised level of the node t 11  is substantially equal to two times of the high level of the positive clock signal input end CLK′ or the negative clock signal input end CLKB′. Because the positive clock signal input end CLK′ becomes high, and the 6 th  N-type TFT M 6  is still turned on, the signal output end Output is also raised from the low level to the high level. In order to avoid the level of the signal output end Output falling down during the period P 2 , the 2 nd  N-type TFT M 2  and the 7 th  N-type TFT M 7  are necessarily turned off at this time. That is, maintaining the node  12  at the low level is necessary. However, because the 3 rd  N-type TFT M 3  is turned on by the positive clock signal end CLK′ with the high level, and the 4 th  N-type TFT M 4  is turned on by the signal output end Output with the high level through the gate of the 4 th  N-type TFT M 4 , a higher duty is necessary for the 4 th  N-type TFT M 4  at this time to pull down the level of the node t 12  as far as possible. Accordingly, regarding the design of the circuit in the embodiment of the disclosure, a width to length (W/L) ratio of the 4 th  N-type TFT M 4  is relatively greater than that of the 3 rd  N-type TFT M 3 , such that a large amount of current flows through the 4 th  N-type TFT M 4 , and thus, the level of the node t 12  is pulled down. Accordingly, the 2 nd  N-type TFT M 2  and the 7 th  N-type TFT M 7  are turned off, and further, the path of which the level of the signal output end Output is pulled down is cut off. 
     During the period P 3 , the positive clock signal end CLK′ becomes low again, and the negative clock signal end CLKB′ becomes high again, such that the 5 th  N-type TFT M 5  is turned on. In the meanwhile, the 8 th  N-type TFT M 8  is turned on, such that the level of the signal output end Output is pulled down. The signal feedback end FB receives an output signal with the high level transmitted by the even-pixel gate line driving circuit of the next stage, and the level of the node t 12  is pulled up through the 5 th  N-type TFT M 5  which is turned on, such that the 2 nd  N-type TFT M 2  and the 7 th  N-type TFT M 7  are turned on, and the levels of the node t 11  and the signal output end Output are pulled down in the meanwhile. Accordingly, a cycle has been finished. Because the 1 st  N-type TFT M 1  does not receives the signal with the high level transmitted from the signal input end FA and is not turned on, the level of the signal output end Output does not return to the high level during the period P 2  again. 
     The operations of the even-pixel gate line driving circuit C_Even shown in  FIG. 5  and the odd-pixel gate line driving circuit C_Odd shown in  FIG. 4  are similar. The difference thereof simply lies in that the positions coupled to the positive clock signal end CLK′ and the negative clock signal end CLKB′ are exactly opposite, and the operation of the even-pixel gate line driving circuit C_Even shown in  FIG. 5  will be simply described as follows, and the same portion which has been described in the foregoing embodiment will not be repeated herein. It is assumed that during the period P 2  shown in  FIG. 6 , the signal input end FA receives the output signal transmitted from the odd-pixel gate line driving circuit of the previous stage, so as to turn on the 9 th  N-type TFT M 9 . Accordingly, the level of the node t 11  shown in  FIG. 5  is raised up. Next, the 14 th  N-type TFT M 11  is turned on by the high level of the node t 11 , and further, because the 16 th  N-type TFT M 16  is turned on by the high level of the positive clock signal end CLK′, the level of the signal output end Output approximates to the low level of the negative clock signal end CLKB′ or the low level gate power source VGL in the meanwhile. 
     Thereafter, when the timing goes into the period P 3 , and the signal input end FA becomes low, the positive clock signal end CLK′ becomes low, and the negative clock signal end CLKB′ becomes high, such that the 13 th  N-type TFT M 13  and the 16 th  N-type TFT M 16  are turned off, and the 11 th  N-type TFT M 11  is turned on. At this time, because the voltage difference between the gate and the source of the 14 th  N-type TFT M 14  is stored in the capacitor C 2 , the level of the node t 11  is raised up again, and the raised level of the node t 11  is also substantially equal to two times of the high level of the positive clock signal input end CLK′ or the negative clock signal input end CLKB′. Because the negative clock signal input end CLKB′ becomes high, and the 14 th  N-type TFT M 14  is still turned on, the signal output end Output is also raised from the low level to the high level. In order to avoid the level of the signal output end Output falling down during the period P 3 , the 10 th  N-type TFT M 10  and the 15 th  N-type TFT M 15  are necessarily turned off at this time. That is, maintaining the node  12  at the low level is necessary. However, because the 11 th  N-type TFT M 11  is turned on by the negative clock signal end CLKB′ with the high level, and the 12 th  N-type TFT M 12  is turned on by the signal output end Output with the high level through the gate of the 12 th  N-type TFT M 12 , a higher duty is necessary for the 12 th  N-type TFT M 12  at this time to pull down the level of the node t 12  as far as possible. Accordingly, a W/L ratio of the 12 th  N-type TFT M 12  is relatively greater than that of the 11 th  N-type TFT M 11 , such that a large amount of current flows through the 12 th  N-type TFT M 12 , and thus, the level of the node t 12  is pulled down. Accordingly, the 10 th  N-type TFT M 10  and the 15 th  N-type TFT M 15  are turned off, and further, the path of which the level of the signal output end Output is pulled down is cut off. 
     During the period P 4 , the positive clock signal end CLK′ becomes high again, and the negative clock signal end CLKB′ becomes low again, such that the 13 th  N-type TFT M 13  is turned on. In the meanwhile, the 16 th  N-type TFT M 16  is turned on, such that the level of the signal output end Output is pulled down. The signal feedback end FB receives an output signal with the high level transmitted by the odd-pixel gate line driving circuit of the next stage, and the level of the node t 12  is pulled up through the 13 th  N-type TFT M 13  which is turned on, such that the 10 th  N-type TFT M 10  and the 15 th  N-type TFT M 15  are turned on, and the levels of the node t 11  and the signal output end Output are pulled down in the meanwhile. Accordingly, a cycle has been finished. Because the 9 th  N-type TFT M 9  does not receives the signal with the high level transmitted from the signal input end FA and is not turned on, the level of the signal output end Output does not return to the high level again. 
     The foregoing operations of the gate line driving circuits shown in  FIG. 4  and  FIG. 6  proceed in each odd-pixel gate line driving circuit and each even-pixel gate line driving circuit of the gate line driving module  300  in an iterative manner to drive the corresponding gate lines until the gate lines corresponding to the gate line driving circuits are all driven at a time. It should be noted that, when the foregoing iteration proceeds to the auxiliary gate line driving circuit  350 , the auxiliary gate line driving circuit  350  forwards the output signal thereof to the signal input end FA of the 1 st  stage gate line driving circuit C_ 1  again to restart the cycle. 
     As known from the schematic waveforms shown in  FIG. 6 , among any of the odd-pixel gate line driving circuit C_Odd or the even-pixel gate line driving circuit C_Even of the gate line driving module  300  or the auxiliary gate line driving circuit  350 , no N-type TFT continuously stays in the state of being turned on. Accordingly, the device characteristic drift due to N-type TFTs continuously biased in the foregoing related art is not generated, such that the disadvantage is overcome. Besides, in the foregoing related art, each gate line driving circuit adopts about more than 13 transistors as elements. However, in the exemplary embodiments of the disclosure, each gate line driving circuit simply adopts 8 transistors and 1 capacitor. Accordingly, the effect of reducing area is achieved regarding the integration of the LC panel and the gate line driving circuit. Furthermore, in the exemplary embodiments of the disclosure, each gate line driving circuit of the gate line driving module adopts the clock signal sources as the power source thereof, such that it is unnecessary to adopt the high level gate power source which continuously supplies the electric power in the foregoing related art. 
     In summary, the disclosure has met the patentability requirements stipulated in the Patent Act, and this application is being filed in accordance with relevant regulations. The embodiments described hereinbefore are chosen and described in order to best explain the principles of the disclosure and its best mode practical application. It is not intended to be exhaustive to limit the disclosure to the precise form or to the exemplary embodiments disclosed. Namely, persons skilled in the art are enabled to understand the disclosure through various embodiments with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the disclosure be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated.