Abstract:
The present system comprises a device and a method for increasing the performance and utilization in a field programmable gate array (FPGA). The device of the present system comprises an FPGA having logic clusters, wherein each logic cluster further comprises a buffer. The method of the present system comprises a method of determining which buffers situated in each logic cluster are located in the best position in the post-placement user netlist to decrease the capacitance in the user netlist.

Description:
BACKGROUND OF THE SYSTEM 
     1. Field of the System 
     The present system relates to field programmable gate array (FPGA) devices. More specifically, the system relates to a buffer module to increase the performance and utilization of an FPGA and a method of distributing buffer modules within an FPGA. 
     2. Background 
     FPGAs are known in the art. An FPGA comprises any number of logic modules, an interconnect routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. An FPGA is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit. 
     A field programmable gate array circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user&#39;s system, through input buffers and through the circuit, and finally back out the user&#39;s system via output buffers. Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hystersis. 
     An FPGA core tile may be employed as a stand-alone FPGA, repeated in a rectangular array of core tiles, or included with other functions in a system-on-a-chip (SOC). The core FPGA tile may include an array of logic modules. An FPGA core tile may also include other components such as static random access memory (SRAM) modules. Horizontal and vertical routing channels provide interconnections between the various components within an FPGA core tile. Programmable connections are provided by programmable elements between the routing resources. 
     The programmable elements in an FPGA can be either one-time programmable or re-programmable. Re-programmable elements used in FPGA technologies include SRAM, EPROM, flash and other cell-controlled pass transistors or other re-programmable elements as is well known to those of ordinary skill in the art. One-time programmable elements used in FPGA technologies may comprise antifuse devices. 
     Antifuse devices are well known in the integrated circuit art. Antifuse devices comprise a pair of conductive electrodes separated by one or more layers of dielectric material. During programming, antifuses exhibit very high resistance between the two electrodes and may be considered to be small capacitators. For antifuses that are to be programmed, a programming process ruptures the dielectric material and creates a low-impedance connection between the two conductive electrodes. 
     In antifuse FPGAs, long tracks are problematic for both programming and normal operation. When programming, if there are too many antifuses on a track, the small amount of leakage current per antifuse can add up and cause the track not to remain at the proper voltage level when precharged or driven. 
     During normal operation, long routing tacks are problematic due to their large parasitic capacitances and resistances. This is exacerbated because unprogrammed antifuses act as small capacitors. The longer the routing track, the more antifuses the track will have. 
     Another issue when programming and operating an antifuse FPGA is high “fanout” nets. This is a two-dimensional version of the long routing track problem. In a core tile, there are many logic modules, one of which may be a source module. The source module originates a signal that has to travel to any number of destination modules. The number of destination modules is known as the “fanout.” The paths between the source module and the destination modules is referred to as the net. 
     FIG. 1 is a simplified drawing showing the connectivity between a source module  2  and several destination modules  4  in an FPGA core tile. Source module  2  is located on a row adjacent to horizontal track  6 . A row adjacent to single vertical track  8  is coupled to the output of source module  2  by means of an antifuse (not shown). Vertical track  8  is also coupled to a horizontal track in every channel by means of additional antifuses (not shown). This causes great capacitive loading and substantial series resistance resulting in a very slow propagation delay. 
     In prior-art FPGAs, the solution to the problem was buffering. In synthesis-based designs, if the auto-buffering tool was enabled, the design software would automatically insert buffers into the user netlist to comply with the maximum fanout rules and any timing data provided. In schematic-based designs, the user would have to enter the buffers into the schematics manually or let place-and-route software enter the buffers into the netlist for the user. The effect of adding the buffers in either the synthesis based designs or the schematic based designs is to break one long, complicated net driven by one driver, such as the one illustrated in FIG. 1, into multiple nets driven by multiple drivers. 
     However, there are problems with the approach set forth above. First, The logic modules in the FPGA core tile are used to buffer signals. Thus, the logic modules that are used to buffer signals are consequently unavailable to perform logic operations. In prior art antifuse FPGAs, approximately 12% of the logic modules are used as simple buffers. In some of the larger antifuse FPGAs the percentage of logic modules used as simple buffer modules could be as high as 25% or more. Also, logic modules are much more complicated and thus slower than simple buffers by a factor of approximately three. This significantly hinders performance when logic modules are used as buffers. 
     Hence there is a need for an FPGA buffering scheme that allows more of the logic modules in the FPGA to be used for logic functions rather than buffering, while maintaining a net size low enough to reduce the negative effects of long tracks. 
     SUMMARY OF THE SYSTEM 
     The present system comprises a device and a method for increasing the performance and flexibility in a field programmable gate array. The device comprises a field programmable gate array having a plurality of interconnect conductors, a plurality of programmable elements, a plurality of input/output modules, and a plurality of logic clusters. The logic clusters each have a plurality of logic modules, at least one flip-flop, at least one buffer. Other modules, such as long distance transmitter and receiver modules may also be present. 
     The method of the present system comprises implementing buffers into an FPGA device comprised of a plurality of logic clusters. Each of said logic clusters has a buffer module. The method further comprises inputting a function netlist defining and optimizing a user circuit, which may or may not have gone through a round of auto buffering. Next, the cells comprising the user input are placed into the FPGA logic clusters. The function netlist is then analyzed to determine the placement of the buffer modules. At least one of the buffers is then selected for a post-placement function netlist. Next, at least one of the buffers is placed in the post-placement netlist. Next, a routing structure to interconnect the logic clusters to implement the user circuit is defined and a programming data file is generated. Finally, the programmable elements of one or more FPGA devices are programmed using the programming data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified drawing showing the connectivity between a source module  2  and several destination modules  4  in an FPGA core tile. 
     FIG. 2 a  is a schematic diagram of an antifuse programming circuit before programming. 
     FIG. 2 b  is a simplified schematic diagram of an antifuse circuit-programming path prior to programming. 
     FIG. 2 c  is a simplified schematic diagram of an antifuse circuit-programming path during programming and soaking. 
     FIG. 3 is a block diagram of a one-tile antifuse FPGA of the present system. 
     FIG. 4 is a block diagram of an antifuse FPGA of the present system including multiple core tiles. 
     FIG. 5 is a simplified block diagram of a logic cluster of the present system. 
     FIG. 6 is a simplified schematic diagram of the multi-level routing architecture of the present system through a logic cluster of FIG.  3 . 
     FIG. 7 is a simplified schematic diagram of a transmitter module (TX) as shown in FIG.  5 . 
     FIG. 8 is a simplified schematic diagram of the interconnect architecture of a receiver module (RX) as shown in FIG.  5 . 
     FIG. 9 is a schematic diagram illustrating a buffer module of the present system. 
     FIG. 10 is a flowchart illustrating a method of choosing appropriately situated buffer modules located in the logic clusters and including the buffer modules in the post placement netlist. 
    
    
     DETAILED DESCRIPTION 
     Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons. 
     This disclosure may relate to data communications. Various disclosed aspects may be embodied in various computer and machine-readable data structures. Furthermore, it is contemplated that data structures embodying the teachings of the disclosure may be transmitted across computer and machine-readable media, and through communications systems by use of standard protocols such as those used to enable the Internet and other computer networking standards. 
     The disclosure may relate to machine-readable media on which are stored various aspects of the disclosure. It is contemplated that any media suitable for retrieving instructions is within the scope of the present disclosure. By way of example, such media may take the form of magnetic, optical, or semiconductor media, and may be configured to be accessible by a machine as is known in the art. 
     Various aspects of the disclosure may be described through the use of flowcharts. Often, a single instance of an aspect of the present disclosure may be shown. As is appreciated by those of ordinary skill in the art, however, the protocols, processes, and procedures described herein may be repeated continuously or as often as necessary to satisfy the needs described herein. Accordingly, the representation of various aspects of the present disclosure through the use of flowcharts should not be used to limit the scope of the present disclosure. 
     FIG. 2 a  is a schematic diagram illustrating antifuse circuit  10  prior to programming in an antifuse FPGA. Logic module  40  having an output buffer  42  is coupled to horizontal routing track  14 . Logic module  40  and load-capacitance-management buffer  42  will be discussed in greater detail below. 
     Antifuse  12 , to be programmed, is coupled between horizontal routing track  14  and vertical routing track  16 . Horizontal routing track  14  and vertical routing track  16  are used to route signals in the FPGA after programming. Each routing track has a direct-address transistor associated with it having a source/drain terminal coupled to the routing track. For example, in circuit  10 , direct address transistor  18  has one source/drain coupled to horizontal track  14  and its other source/drain coupled to programming voltage line  22  which generally runs perpendicular to horizontal routing track  14 . Programming voltage line  22  can be coupled to Vpp through programming voltage driver  30 . Vpp is an external power supply for the programming voltage circuits. Direct-address transistor  18  has its gate coupled to horizontal direct-address line  26  which runs perpendicular to programming voltage line  22 . Direct-address transistor  20  has its source/drain coupled to vertical routing track  16  and its other source/drain coupled to programming voltage line  24  which generally runs perpendicular to vertical routing track  16 . Programming voltage line  24  can be coupled to Vpp through programming voltage driver  32 . Direct-address transistor  20  has its gate coupled to vertical direct-address line  28  which runs perpendicular to programming voltage line  24 . 
     During programming, the horizontal direct address lines, vertical direct address lines, horizontal programming voltage lines and vertical programming voltage lines form a two level decoding scheme that uniquely addresses each antifuse. All of the horizontal programming voltage and vertical programming voltage lines are charged to Vpp/2 for programming. Next, the two relevant direct address lines are driven to a super voltage (V SV ) to allow propagation of Vpp to the antifuse. Super voltage (V SV ) is an external power supply which is sufficiently higher than V PP  t allow the programming voltage to flow to the fuse. Next, one of the two relevant (horizontal programming voltage or vertical programming voltage) lines is driven to Vpp and the other is driven to ground by the respective programming voltage drivers. This ruptures the antifuse dielectric and programs the antifuse. Which of the programming voltage lines is driven to Vpp or ground depends on the structure and programming circuitry of the antifuse and is beyond the scope of this disclosure. 
     FIG. 2 b  is a simplified schematic illustrating the programming path of antifuse  12  prior to programming. Antifuse  12  is the fuse being programmed. As illustrated, programming voltage driver  30  supplies Vpp to the source/drain of direct address device  18 . Super voltage, V SV , will be applied to the gate of direct address device  18  during programming. Programming voltage driver  32  is driven to ground pulling the source/drain of direct address device  20  to ground. Thus, circuit  10  supplies Vpp to the track  14  side of antifuse  12  and ground to the track  16  side of antifuse  12  until the dielectric ruptures and an electrical connection is formed. 
     FIG. 2 c  is a simplified schematic illustrating circuit  10  after the programming of antifuse  12 . As current flows through antifuse  12 , the effective resistance drops, the current through the fuse increases and the voltage across the fuse drops. This is called “soaking” the fuse. Eventually, the current settles into an equilibrium value known as I soak . In actual practice, Vpp and ground can be reversed (called a “reverse soak”). 
     Because currents are repeatedly applied through an antifuse during normal operation, the programming process could reverse and the antifuse could become unprogrammed. In general, if the maximum current (I peak ) allowed to flow through an antifuse during normal operation is limited to 50% of I soak  then the antifuse will operate reliably for the life of the FPGA. 
     The load-capacitance-management buffer of the present system is provided as a buffer dedicated to addressing the capacitance problems associated with long lines and large fan out nets. As will be illustrated in greater detail below, load-capacitance-management buffers are included in every logic cluster, and thus available to be programmed into the circuit when ever there is a need to drive a load or to break a very long line into smaller, more manageable increments. 
     FIG. 3 is a block diagram of a core tile in an antifuse FPGA  100  of the present system. Antifuse FPGA core tile comprises an array of logic clusters  110  and an array of random access memory modules  106 . Input/output clusters  102  and input/output banks  104  surround the FPGA core tile. Logic clusters  110  are connected together by a routing interconnect architecture (not shown) that may comprise multiple levels of routing interconnects. FIG. 4 is a block diagram of an antifuse FPGA including multiple core tiles of the type shown in FIG.  3 . As shown in FIG. 4, antifuse FPGA  200  comprises four core tiles  100 , though other numbers of tiles are possible. 
     FIG. 5 is a simplified block diagram of a logic cluster  110  of the present system. As would be clear to those of ordinary skill in art having the benefit of this disclosure, logic cluster  110  may comprise any number of the logic components indicated below. The example set forth below is for illustrative purposes only and in no way limits the scope of the present invention. Logic cluster  110  comprises two sub-clusters  112  and  114 . Sub-clusters  112  and  114  each contain two logic modules  116 , a flip-flop  118 , two receiver modules  122  and two transmitter modules  120 . Sub-cluster  112  contains a buffer module  130 . In FPGAs designed in accordance with an embodiment of the present invention, there is one buffer module  130  for every N logic modules  116 . In this example, for illustrative purposes only, N=4. Having one buffer for every four logic modules can increase the logic capability of the FPGA core tile by 25% and is the equivalent of being able to auto buffer at a 25% rate. 
     FIG. 6 is a simplified schematic diagram of the multi-level routing architecture  200  of the present system through a logic cluster  110  of FIG.  3 . Multi-level routing architecture  200  has multiple levels of routing architecture running over each row and column of logic clusters  110 . In this illustrative example, there are two levels of routing architecture. In the horizontal routing channel through logic cluster  110 , there are eight first-level horizontal channels  204  spanning each logic cluster  110 . Individual first-level horizontal channels in first-level horizontal channels  204  have a varying number of tracks. In addition, there is an output routing channel  209 , a set of horizontal tracks  208  coupled to ground and Vcc respectively, and a routed clock channel  206 . The routed clock tracks  206  may drive the clock, preset and enable (not shown) pins of flip-flop  118  in logic cluster  110  as shown in FIG.  5 . 
     Four second-level channels  202  cover each row of logic clusters  110  spanning the entire width of FPGA core  100  (as shown in FIG.  3 ). Each second-level routing channel  202  has five tracks. The second-level horizontal channels  202  contain a track coupled to Vcc for tie-offs of unused buffer inputs (discussed in greater detail below). 
     In the vertical routing channel through logic cluster  110 , there are two first-level horizontal channels, divided into a left, first-level vertical channel  212  and a right, first-level vertical channel  214 , spanning each logic cluster  110 . Left, first-level vertical channel  212  comprises four sets of tracks each having a varying number of tracks. Right, first-level vertical channel  214  comprises three sets of tracks each having a varying number of tracks. In addition, there is a set of vertical track  216  coupled to ground and vertical track  218  coupled to Vcc, and two hard-wired clock channels  220  and  222  respectively. The hard-wired clock tracks  220  and  222  are coupled to the clock pins in every flip-flop  126  in each logic cluster  110  as shown in FIG.  3 . Eight second-level vertical channels  210  cover each column of logic clusters  110  spanning the entire width of FPGA core  100  (as shown in FIG.  1 ). Each second-level vertical routing channel  210  has five tracks. 
     FIG. 7 is a simplified schematic diagram of a transmitter module (TX) as shown in FIG.  5 . Transmitter module  250  provides transmission capability to second-level horizontal channels  256  and second-level vertical channels  268 . Transmitter module  250  comprises a three-input AND gate  276 . One input of three-input AND gate  276  is coupled to first-level horizontal channel  258  in the same row  254  as transmitter module  250  and another input of three-input AND gate is coupled to first-level horizontal channel  258  in the row  252  above transmitter module  250 . Therefore, transmitter module  250  may receive a signal from first-level horizontal channel  258  in the same row as transmitter module  250  or from the row above by programming one of either programmable elements  284  or  286 . The third input of three-input AND gate  276  may be coupled to either second-level horizontal channel  256  in row  254  or second-level vertical channel  268 . Three-input AND gate has an output coupled to an input of buffer  282 . Buffer  282  has an output coupled to either second-level vertical channel through programmable element  288  or to second-level horizontal channel in row  254  through programmable element  275 . As those of ordinary skill in the art having the benefit of this disclosure will recognize, direct address devices  270 ,  272 ,  278  and  280  are employed to program the respective programmable elements. 
     As stated above, transmitter module  250  may receive a signal from first-level horizontal channel  258  in the same row as transmitter module  250  or from the row above by programming either programmable elements  284  or  286 . In one illustrative example, if programmable element  284  is programmed to receive a signal from first-level horizontal channel  258 , programmable element  286  is left unprogrammed and is coupled to Vcc through track  264  in row  254 . The signal is received through a first input of three-input AND gate  276 . The second and third inputs of three-input AND gate  276  are tied to Vcc. The signal received from horizontal channel  258  in row  252  is then passed through buffer  282  and either routed to a second-level vertical channel  268  through programmable elements  288  and  290  or to a second-level horizontal channel  256  in row  254  through programmable elements  288  and  275 . Thus, transmitter module  250  is programmably couplable to second-level vertical tracks  268  at intersection  292  through programmable elements  290  and programmably couplable to second-level horizontal tracks at intersection  294  through programmable elements  274  and  275 . As one of ordinary skill in the art having the benefit of this disclosure will recognize, not all programmable elements in groups  288 ,  290 ,  275  and  294  will be programmed at once. This example is illustrative only, the actual circuit programmed through the programmable elements will depend on the user circuit mapped into the FPGA core. 
     Transmitter module  250  may also transfer a signal from second-level vertical channel  268  to second-level horizontal channel  256  in the same row  254  as transmitter module  250  and vice versa. For example, if a signal travels from second-level vertical channel  268  to second-level horizontal channel  256 , one of programmable elements  290  is programmed and one of programmable elements  274  is programmed and fed through a second input of three-input AND gate  276 . The other two inputs of three-input AND gate are tied to either Vcc via track  264 . The signal from second-level vertical channel travels through three-input AND gate  276  through buffer  282  and is transferred to second-level horizontal channel through programmable element  275 . 
     FIG. 8 is a simplified schematic diagram of the interconnect architecture  300  of a receiver module (RX)  310  as shown in FIG.  5 . Receiver module  310  comprises a buffer  312 . Buffer  312  has an input  322  coupled to one of either second-level horizontal channel  312  through programmable elements  314  in the same row as RX  310  or second-level vertical channel  316  through programmable elements  318  in same logic cluster column RX  410 . Buffer  312  has an output  324  coupled to its own output track  320 . Output track  320  is coupled to the first-level routing architecture. Therefore, RX module  310  receives a signal from the second level routing architecture and transfers the signal back into the first-level routing architecture. As one of ordinary skill in the art having the benefit of this disclosure will recognize, not all programmable elements in groups  314  and  318  will be programmed at once. This example is illustrative only, the actual circuit programmed through the programmable elements will depend on the user circuit mapped into the FPGA core. 
     As is clearly illustrated in FIG. 8, the coupling between receiver module  310  and one channel (a set of five tracks) in each second-level vertical channel  316  and second-level horizontal channel  312  is shown. The representation shown is illustrative of all connections between all eight second-level vertical channels  316  and all four second-level horizontal channels  312 . 
     FIG. 9 is a schematic diagram illustrating load-capacitance-management buffer module  330  and load-capacitance-management buffer module  330  interconnects of a system according to an embodiment of the present invention. In one illustrative embodiment, load-capacitance-management buffer module  330  comprises a two input NAND gate  332 . NAND gate  332  has inputs  334  and  336  and output  342 . NAND gate  332  allows connection to either row  344  above load-capacitance-management buffer module  330  through programmable element  331  or in the same row  346  as load-capacitance-management buffer module  330  through programmable element  339 . If input  334  of NAND gate  332  is used for an active signal to couple load-capacitance-management buffer module  330  to row  344  through programmable element  331 , then input  336  of NAND gate  332  is tied to V CC  through programmable element  343 . V CC  is an external power supply, which supplies the operating voltage for the FPGA tile. If input  336  of NAND gate  332  is used for an active signal to couple load-capacitance-management buffer module  330  to row  346  through programmable element  339 , then input  334  of NAND gate  332  is tied to V CC  through programmable element  335 . 
     Referring still to FIG. 9, input signals from row  344  above load-capacitance-management buffer module  330  may be from a horizontal track  350  through programmable element  331 , ground  352  through programmable element  333 , Vcc  154  through programmable element  335  or from an output track  356  through programmable element  337 . Input signals from row  346  below load-capacitance-management buffer module  330  may be from a horizontal track  358 , ground  360 , Vcc  162  or from an output track  364  through programmable element  337 . However, output  342  is coupled to an output track  364  in row  346  below load-capacitance-management buffer module  330  through inverter  338 . As a result, load-capacitance-management buffer module  330  receives a signal from row  346  through programmable element  339  or row  344  above load-capacitance-management buffer module  330  through programmable element  331  and drives its own output track  364  through line  340 . As those skilled in the art having the benefit of the disclosure will know, the circuit configuration set forth above is an example only and many other configurations are obtainable. 
     FIG. 10 is a flowchart illustrating a method of choosing appropriately situated load-capacitance-management buffer modules located in the logic clusters and including the load-capacitance-management buffer modules in the post-placement netlist. Once included in the user&#39;s post placement netlist, the load-capacitance-management buffers become part of the user circuit. The method shown in FIG. 10 may be implemented in software. Thus, a software module, which may be stored on a computer hard drive, on a floppy disk or on a CD ROM, performs the method disclosed. 
     At reference numeral  400 , the software module inputs a function netlist defining a user circuit into the FPGA circuit. Next, at reference numeral  402 , the software module optimizes the user circuit by determining the most efficient means to implement the desired circuit. At reference numeral  404 , the software module places the function netlist defining the user circuit into the FPGA logic clusters. Next, at reference numeral  404 , the software module examines the user netlist to determine which load-capacitance-management buffer modules  430  located within each logic cluster  110  are situated in the best location to buffer the circuit as generated from the user netlist. At reference numeral  406 , the software module analyzes the function netlist to determine the placement of the load-capacitance-management buffer modules in the circuit. Each user netlist may vary. Thus, the determination of which load-capacitance-management buffer modules  430  are used to buffer each individual user circuit will vary depending on the circuit. 
     Next, at reference numeral  408 , the software module selects the appropriately located load-capacitance-management buffer modules. At reference numeral  410 , the software module includes the selected load-capacitance-management buffer modules into the post-placement netlist. At reference numeral  412 , the software module routes the FPGA circuit. At reference numeral  414 , the software module generates the data file. Finally, at reference numeral  416 , the software module programs the FPGA. 
     While embodiments and applications of this system have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The system, therefore, is not to be restricted except in the spirit of the appended claims.