Abstract:
A method for forming a semiconductor structure is disclosed wherein a masking layer used to form the gate contact of a Metal Electrode Semiconductor Field Effect Transistor (MESFET) is formed by selectively depositing particles into separated regions of the masking layer, diffusing the particles into the portions of the masking layer to reduce the separation between the regions to a predetermined separation and exposing the masking layer to a chemical etchant to selectively remove the portions of the masking layer which have a particle concentration below a predetermined concentration, producing an aperture in the masking layer having a predetermined width. With such method a well controlled diffusion process and selective chemical etching process are used to form such aperture which, in turn, is used to form a gate contact for a MESFET having a gate channel length in the order of a micron.

Description:
CROSS-REFERENCE TO RELATED CASES 
     This is a continuation of application Ser. No. 864,294, filed Dec. 27, 1977, now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention relates generally to integrated circuit manufacturing methods. 
     As is known in the art, high speed, digital logic circuits have been designed using gallium-arsenide (GaAs) Schottky-gate MESFET (metal electrode semiconductor field effect transistor) technology by combining the high mobility characteristics of GaAs and the short channel lengths of Schottky-gate depletion mode transistors. However, yields have been relatively low because, in order to achieve channel lengths in the order of a micron, complex photolithographic techniques are at their diffraction imposed limits, and, further, gallium arsenide material is relatively difficult material to prepare and cannot readily be subjected to temperatures required for solid state diffusion. 
     As is further known in the art, it is frequently desirable to form at the output portion of a logic gate an N channel and P channel field effect transistor in order to form a &#34;complementary&#34; pair of interconnected transistors on a single crystal substrate which provides low static power dissipation and large output capacitance drive capability. Such complementary pair formation is not generally practical with a substrate of GaAs. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, a masking layer for a semiconductor device is formed by the steps of: Selectively depositing particles into separate regions of the masking layer; diffusing the particles into the masking layer to reduce the separation between the regions to a predetermined separation, such regions having a predetermined particle concentration; and exposing the masking layer to a chemical etchant, selectively removing the portions of the masking layer which have a particle concentration below the predetermined particle concentration, producing an aperture in such masking layer having a predetermined width. 
     In a preferred embodiment of the invention, the masking layer is used to form the gate electrode contact region of a field effect transistor. An insulating layer is formed over a layer of semiconductor material. The masking layer is then formed over the insulating layer. A mask is then formed over a portion of the masking layer. The unmasked portions of the masking layer have particles deposited therein to form the separated regions. The particles are next diffused into the masked portion of the masking layer extending the separated regions, symmetrically, partially into the masked portions of the masking layer. The diffusion is carried out until the regions having a particle concentration equal to the predetermined particle concentration are separated a length in the order of the desired gate channel width. The unmasked portions of the masking layer are then removed. Particles are implanted into portions of the semiconductor layer which are unmasked by the remaining portion of the masking layer to form source and drain regions for the transistor; the remaining portion of the masking layer is then exposed to a chemical etchant to selectively remove the portions of such masking layer which have a particle concentration below the predetermined particle concentration, producing an aperture in such masking layer having a width in the order of the desired channel width. Apertures are formed in the insulating layer (previously formed between the semiconductor layer and the masking layer) to form source and drain electrode contact regions for the transistor, and the remaining portion of the masking layer is used as a mask to form the gate electrode contact region for the transistor. A metallization layer is then formed on the insulating layer and through the apertures formed therein to the source, drain and gate contact regions of the semiconductor layer. 
     With such method, a well-controlled diffusion process and selective chemical etching process are used to obtain gate channel widths in the order of a micron. Further, the method is self-aligning because of the symmetrical nature of the diffusion process so that the gate channel is disposed symmetrically with respect to the source and drain regions of the transistor. Such method is used to form an N channel depletion mode Schottky Metal Electrode Semiconductor Field Effect Transistor (MESFET) having a gate channel width in the order of a micron. Such transistor is formed in the semiconductor layer of silicon formed on an insulator of sapphire. Because such transistor is formed in a silicon semiconductor layer, a P channel enhancement mode Metal Oxide Semiconductor Field Effect Transistor (MOSFET) may concurrently be formed on such substrate, thereby enabling the formation of N channel and P channel &#34;complementary&#34; field effect transistors on a common substrate. Such &#34;complementary&#34; field effect transistors may be used in the output portion of a logic gate with the advantages of low static power dissipation and large output capacitance drive capability. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above-mentioned and other features of the invention will become more apparent by reference to the following description taken together in conjunction with the accompanying drawings, in which: 
     FIGS. 1a-1i are cross-sectional elevational views, somewhat distorted, of a field effect device at various steps in the manufacture thereof; 
     FIG. 1j is a plane view of the completed field effect device; 
     FIGS. 2a-2h are cross-sectional elevational views, somewhat distorted, of a pair of field effect devices at various steps in the manufacture thereof; 
     FIG. 3 is a schematic diagram of a logic gate according to the prior art; and 
     FIG. 4 is a schematic diagram of a logic gate using the pair of field effect devices manufactured in accordance with the steps described in connection with FIGS. 2a-2h. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Referring now to FIGS. 1a-1j, the steps in forming an N channel depletion-mode Schottky Metal Electrode Semiconductor Field Effect Transistor (MESFET) are shown. As indicated in FIG. 1a, a sapphire (Al 2  O 3 ) substrate 10 has an epitaxial semiconductor layer 12, here N type conductivity silicon, formed on the surface of such substrate 10. The epitaxial layer 12 is here formed on a plane parallel to a &lt;1102&gt; crystallographic plane of the substrate 10 and the surface of the semiconductor layer 12 is parallel to a &lt;100&gt; crystallographic plane of the semiconductor layer 12. The sapphire substrate 10 with the epitaxial layer 12 formed thereon as described is here manufactured by Union Carbide Corporation, San Diego, Cal. The epitaxial layer 12 has a thickness here in the order of 0.75 microns and an N type conductivity concentration in the order of 10 14  atoms/cm 3 . The surface of the epitaxial layer 12 is oxidized in a conventional manner to form an insulating layer 14 of silicon dioxide on such surface having a thickness of here 1000- 2000 A. Next, a layer 16 of silicon nitride (Si 3  N 4 ) is formed, here chemically vapor deposited, on the surface of the insulating layer 14. Here the thickness of the silicon nitride layer 16 is in the order of 1000 A. A mask 20 of photoresist 22 is formed on the surface of the silicon nitride layer 16 using conventional photolithography to form apertures 24 in such photoresist 22. The apertures 24 are formed in the mask 20 where isolation regions are to be formed about the field effect transistor. 
     Referring now also to FIG. 1b, the portions of the silicon nitride layer 16 exposed by the apertures 24 are removed using R.F. (radio frequency) plasma etching techniques. The photoresist layer 22 is then removed in a conventional manner. The exposed portions of the insulating layer 14 are then removed, here chemically etched away, by bringing such exposed portions of the insulating layer 14 in contact with a suitable etchant, here a solution of hydrofluoric acid (HF). Next, the exposed portions of the epitaxial layer are brought in contact with an anisotropic etchant, here an ethylene diamine-pyrocatechol solution. Alternatively, other anisotropic etchants, such as a saturated solution of sodium hydroxide (NaOH) in water or potassium hydroxide (KOH), 1-Propanol and water, may be used. It is noted that the remaining portions of the insulating layer 14 and the silicon nitride layer 16 provide an etch resistant mask used in forming isolation regions about the transistor. The mask is oriented to enable etching of the epitaxial layer 12 along the &lt;110&gt; crystallographic axis of such layer 12. The anisotropic etchant etches away the portions of the epitaxial layer 12 exposed by the mask with extremely little etching occurring to the epitaxial layer 12 which is underneath the mask. The anisotropic etchant produces isolation grooves in the epitaxial layer 12 which have truncated wedge-shaped cross-sections, as shown. The side walls of the grooves are parallel to the &lt;111&gt; crystallographic plane of the epitaxial layer and make an acute angle, 54.7°, with respect to the surface of the epitaxial layer 12. The width of the grooves is here in the order of 2.5 μm to 5.0 μm. The etching process continues until the bottom walls of the grooves reach a depth in the order of 0.3-0.4 μm from the upper exposed surface of the epitaxial layer 12, as shown in FIG. 1b. 
     Referring now also to FIG. 1c, the structure thus formed is placed in an oxidizing environment to oxidize the side walls and bottom walls of the grooves producing silicon dioxide material 28 in such grooves, i.e., in the isolation regions between transistors. It is noted that during the oxidizing process the grooves &#34;fill in&#34; with silicon dioxide. 
     Referring now also to FIG. 1d, the silicon nitride layer 16 is removed, here by plasma etching in a conventional manner, and a layer 30 of polycrystalline silicon, here having a thickness of 3000 A, is deposited over the surface of the structure as shown, here by chemical vapor deposition in a conventional manner. (It is noted that the polycrystalline silicon layer 30 will sometimes be referred to herein also as a masking layer 30 for reasons to become apparent.) Next, a layer 32 of silicon nitride is deposited over the polycrystalline silicon layer 30, as shown, here using conventional chemical vapor deposition. Here such layer 32 has a thickness of 1000 A. A mask 34 of photoresist material 36, here having a width of 5 μm, is formed over the relatively central portion of the transistor, as shown, using conventional photolithography. 
     Referring now also to FIG. 1e, the portions of the silicon nitride layer 32 exposed by the photoresist mask 34 are brought in contact with a suitable etchant, here by plasma etching, to remove such exposed portions as shown. The surface of the structure is exposed to boron ions using suitable ion implanting apparatus, not shown. The ion implant is illustrated in FIG. 1e by the arrows, not numbered. The photoresist 36 and silicon nitride layer 32 serve as an ion implantation mask so that the boron ions become implanted into the polycrystalline silicon or masking layer 30 as shown. The energy level of the ion implanting apparatus is here in the order of 100 KeV and the dose is in the order of 3×10 15  atom/cm 2  so that the minimum carrier density of boron atoms 38 in the exposed portions of the masking layer 30 is greater than 7×10 19  atoms/cm 3 . It is noted that two P type regions are thus formed, such regions being separated by the portion 40 of the polycrystalline silicon layer 30 disposed beneath the photoresist 36 and silicon nitride layer 32, as shown in FIG. 1e. 
     Referring now also to FIG. 1f, the photoresist layer 36 is removed, using any conventional solution. Then the structure is heated for about two hours at a temperature in the range of 1000° C.-1100° C. to diffuse the boron atoms 38 under the silicon nitride layer 32. That is, the heating process causes the boron atoms 38 in the masking layer 30 to diffuse under the nitride layer 32 so that regions 42, 44 having boron ion concentrations of at least 7×10 19  atoms/cm 3  are separated a predetermined width related to the gate channel length of the transistor. The minimum separation between the regions 42, 44 is here 1 μm. It is noted that the diffusion process drives the boron ions into the polycrystalline silicon layer 32 so that the edges of the regions 42, 44 (indicated by dotted lines, not numbered) are equidistant from the sides of the layer 32. It is also noted that the region 46 of the layer 30 has a boron ion concentration less than 7×10 19  atoms/cm 3  and that the width of such region 46 is here 1 μm. The width is established by the time duration and temperature of the heating (i.e. diffusion) process. Such process is a well-controlled process, and the diffusion of boron atoms in the polycrystalline silicon layer 30 thereby accurately controls the extent to which such boron atoms diffuse into such layer 30. 
     Referring now to FIG. 1g, the surface of the structure is then brought in contact with a suitable chemical etchant, here HNO 3  :HF:H 2  O, to remove the portions of the masking layer 30 exposed by the silicon nitride layer 32, as shown. The structure is placed in an ion implantation apparatus to implant phosphorous atoms into the epitaxial layer 12 to form the N+ type source and drain regions 50, 52 for the transistor. The silicon nitride layer 32 and masking layer 30 provide a masking layer 30 provide a mask for the ion implantation process. The ion implantation of the phosphorous atoms 54 is illustrated in FIG. 1g by arrows, not numbered. The concentration of phosphorus atoms in the regions 50, 52 of epitaxial layer 12 is here 10 20  atoms/cm 3 . It is noted that the region 46 in the masking layer 30 is symmetrically disposed with respect to the source and drain regions 50, 52 because the silicon nitride layer 32 served as the mask for the implantation of the boron atoms, the diffusion of such boron atoms under such layer 32 was symmetrical so that the region 46 is formed in the center of the layer 30, and such layer 32 was used for the mask in ion implanting the phosphorous atoms into the epitaxial layer 12 to form the source and drain regions 50, 52. 
     Referring now to FIG. 1h, the silicon nitride layer 32 is removed using a suitable chemical etchant (here hot phosphoric acid). The structure is then immersed in a solution, here of potassium hydroxide-1 propanol and water, to selectively remove only those portions of the polycrystalline silicon layer 30 having a boron atom concentration of less than 7×10 19  atoms/cm 3 . Alternatively, a solution of ethylene diamine, pyrocatechol and water, may be used. As shown, the region 46 is removed by the chemical etchant and the regions 42, 44 of the layer 30 remain. The width of the region 46 is determined by the diffusion profile of boron atoms after the diffusion process and therefore such width is affected by the initial implant profile. Therefore, the diffusion profile established by the boron atoms in the polycrystalline silicon layer 30 establishes the width of the aperture formed in such layer 30 by the selective etching process. It is noted, therefore, that the aperture formed by the removal of region 46 is disposed symmetrically with respect to the source and drain regions 50, 52 and has a width less than 1 μm. Next, a photoresist contact mask 60 is formed over the structure using conventional photolithography. 
     The portions of the silicon dioxide layer 14 exposed by apertures in mask 60 are brought in contact with a suitable etchant, here hydrofluoric acid (HF), to etch apertures in such silicon dioxide layer 14 as shown in FIG. 1i. It is noted that the layer 30 provides a mask for the etching of the silicon dioxide layer 14 and, therefore, the width of the apertures formed in such layer 14 is in the order of 1 μm. The photoresist mask 60 is then removed and a metallization layer 62, here aluminum, is formed over the silicon dioxide layer 14 and through the aperture therein onto the exposed portions of the epitaxial layer 14. The metallization layer 62 is then masked and such layer 62 suitably processed in a conventional manner to form drain, gate and source electrodes 64, 66, 68, respectively, as shown. Ohmic drain, ohmic source and Schottky gate contacts 70, 72, 74, respectively, are formed between the aluminum-silicon (epitaxial layer) interface in a conventional manner as shown in FIG. 1a and FIG. 1j. 
     Referring now to FIGS. 2a-2h, the steps used in forming an N channel depletion mode MESFET and a P channel enhancement mode metal oxide silicon field effect transistor (MOSFET) concurrently on a common substrate are shown. As indicated in FIG. 2a, a sapphire (Al 2  O 3 ) insulating substrate 10&#39; has an epitaxial semiconductor layer 12&#39;, here of N type conductivity silicon formed on the surface of the substrate 10&#39;. The epitaxial layer 12&#39; is here formed on a plane parallel to a &lt;1102&gt; crystallographic plane of the substrate 10&#39; and the surface of the semiconductor layer 12&#39; is parallel to a &lt;100&gt; crystallographic plane of the semiconductor layer 12&#39;. The epitaxial semiconductor layer 12&#39; has a thickness here of 0.75 microns and an N type conductivity concentration in the order of 10 15  atoms/cm 3 . The surface of the epitaxial layer 12&#39; is oxidized in a conventional manner to form an insulating layer 14&#39; of silicon dioxide on such surface, here having a thickness of 1000 A. Next a layer 16 of silicon nitride (Si 3  N 4 ) is formed, here by chemical vapor deposition, on the surface of insulating layer 14&#39;. Here the thickness of the silicon nitride layer 16&#39; is in the order of 1000 A. A mask of photoresist 22&#39; is formed on the surface of the structure using conventional photolithography to form apertures in the mask where isolation regions are to be formed about the two transistors as described above in connection with FIG. 1a. That is, two isolated regions 78, 79 are formed in the epitaxial semiconductor layer 12&#39;. 
     That is, the silicon nitride layer 16&#39; exposed by the apertures is brought in contact with a suitable etchant, here plasma etching, to remove such exposed portions, the photoresist layer 22&#39; is removed, the thin exposed portions of the insulating layer 14&#39; are etched away by bringing such exposed portions in contact with a suitable etchant, here hydrofloric acid (HF), then an anisotropic etchant is brought in contact with the then exposed portions of the epitaxial layer 12&#39; to form grooves having walls parallel to the &lt;111&gt; crystallographic planes of the epitaxial layer 12&#39; and finally the structure thus formed is placed in an oxidizing environment to oxidize the side walls and bottom walls of the grooves producing the structure shown in FIG. 2a in a similar manner to that described in connection with FIGS. 1b and 1c. 
     Referring now also to FIG. 2b, the silicon nitride layer 16&#39; is removed, here by plasma etching in a conventional manner, and a layer 80 of photoresist is deposited over the surface of the structure. The portion of the layer 80 disposed over the region 79 is removed, as shown, using conventional photolithography. The surface of the structure, partially covered by the photoresist layer 80, is exposed to phosphorous ions using suitable ion implanting apparatus (not shown). The ion implant is illustrated by arrows, not numbered. The thickness of the photoresist layer 80 covering region 78 prevents such ions from penetrating, substantially, into the portion of the epitaxial layer 12&#39; in the region 78; however, such ions penetrate into the uncovered portion of epitaxial layer 12&#39;, i.e. into the portion of the epitaxial layer 12&#39; in the region 79 to enable the N type conductivity of the epitaxial layer 12&#39; in such region 79 to increase from 10 15  atoms/cm 3  to 10 16  atoms/cm 3 . The photoresist layer 80 is then removed using any conventional process. The surface of the structure is brought in contact with a suitable chemical etchant, here buffered hydrofloric acid (NH 4  F:HF) to remove 1000 A of the insulating layer 14&#39;. That is, the portions of the insulating layer 14&#39; which are on the surface of the epitaxial layer 12&#39; are removed. The surface of the structure is then oxidized to form a gate oxide layer 14&#34; on the surface of the epitaxial layer 12&#39;. Here such gate oxide layer 14&#34; is 1000 A thick formed in a conventional manner by oxidizing the surface of epitaxial layer 14&#39; in an atmosphere of a mixture of oxygen and hydrogen chloride (HCl). 
     Referring now also to FIG. 2c a layer 30&#39; of polycrystalline silicon, here having a thickness of 3000 A, is deposited over the surface of the structure as shown in FIG. 2c, using here a chemical vapor deposition. Then a layer 32&#39; of silicon nitride, here having a thickness of 1000 A, is deposited on polycrystalline silicon layer 32&#39;. A layer 36&#39; of photoresist material is then formed over the surface of the structure and portions thereof are suitably removed, using conventional photolithography, to form a pair of masks 34 1  &#39;, 34 2  &#39;. Mask 34 1  &#39; has a width, W 1 , of here 3 μm and mask 34 2  &#39; has a width, W 2 , of here 5 μm. The mask 34 1  &#39; is formed over the relatively central portion of the region 78, as shown, and the mask 34 2  &#39; is formed over the relatively central portion of the region 79, as shown, using conventional photolithography. 
     Referring now also to FIG. 2d, the portions of the silicon nitride layer 32&#39; exposed by masks 34 1  &#39;, 34 2  &#39; are brought in contact with a suitable etchant, here plasma etching, to remove such exposed portions, as shown. The surface of the structure is then exposed to boron ions using suitable ion implanting apparatus, not shown. The ion implant is illustrated in FIG. 2d by arrows, not numbered. The masks 34 1  &#39;, 34 2  &#39; and the remaining portions of the silicon nitride layer 32&#39; serve as ion implantation masks so that the boron ions become implanted into the polycrystalline silicon or masking layer 30&#39;, as shown. The energy level of the ion implanting apparatus is here in the order of 100 KeV and the dose is in the order of 3×10 15  atoms/cm 2  so that the minimum carrier density of the boron atoms 38&#39; in the exposed portions of the masking layer 30&#39; is greater than 7×10 19  atoms/cm 3 . It is noted that two P type conductivity regions are thus formed in the polycrystalline silicon layer 30&#39;, the P type conductivity regions in region 79 being separated from each other a width, W 2 , here 5 μm, and the P type conductivity regions in region 78 being separated from each other a width, W 1 , here 3 μm, by processes equivalent to that described in connection with FIGS. 1d and 1e above. 
     Referring now also to FIG. 2e, the photoresist masks 34 1  &#39; and 34 2  &#39; are removed using any conventional process. The structure is then heated for about two hours at a temperature of 1000° C.-1100° C. to diffuse the boron atoms 38&#39; under the silicon nitride layer 32&#39; in the masking layer 30&#39;, as shown. That is, the heating process causes the boron atoms 38&#39; in the masking layer 30&#39; to diffuse completely under the portion of the nitride layer 32&#39; which covers region 78 and diffuse partially under the portion of the nitride layer 32&#39; which covers region 79. That is, the heating process causes the boron atoms 38&#39; in the masking layer 30&#39; to diffuse into such layer 30&#39; so that regions 42&#39;, 44&#39; have boron atom concentrations of at least 7×10 19  atoms/cm 3  and such regions are separated from each other a predetermined width related to the gate channel length of the transistor being formed in region 79. The minimum separation between such regions 42&#39;, 44&#39; is here 1 μm. That is, the boron atoms are diffused in the order of 2 μm, laterally, into the masking layer 30&#39; from each side. Therefore, it follows that the boron atoms are diffused to produce a 7× 10 19  atoms/cm 3  concentration in the entire portion of the masking layer 30&#39; which is disposed over region 78 while regions 42&#39;, 44&#39; with such concentration are separated by 1 μm separation (i.e. region 46&#39;) formed centrally with respect to the portion of the masking layer 30&#39; which is disposed over the region 79. As discussed in connection with FIG. 1f above, the diffusion process drives the boron atoms into the polycrystalline silicon layer 32&#39; so that the edges of regions 42&#39;, 44&#39; (indicated by the dotted lines, not numbered) are equidistant from the sides of the portion of layer 32&#39; which is disposed over region 79, as shown. It is also noted that the region 46&#39; of the layer 30 has a boron atom concentration less than 7×10 19  atoms/cm 3  and that the width of such region 46&#39; is here 1 μm. As discussed above in connection with FIG. 1f, the width is established by the time duration and temperature of the heating (i.e. diffusion) process. Such process is a well controlled process and the diffusion of boron in the polycrystalline silicon layer 30&#39; thereby accurately controls the extent to which the boron diffuses into the layer 30&#39;. 
     The surface of the structure is then brought in contact with a suitable chemical etchant, here HNO 3  :HF:H 2  O to remove the portions of the masking layer 30&#39; which are exposed by the silicon nitride layer 32&#39;, as shown, in a manner similar to that described in connection with FIG. 1g. Photoresist material is then deposited over the surface of the structure and selectively removed, using conventional photolithography, to form a mask 90 over the region 78, as shown. The structure is placed in a conventional ion implanting apparatus to implant phosphorus ions into the portions of region 79 of epitaxial layer 12&#39; which is exposed by the remaining portions of the silicon nitride layer 32&#39; and polycrystalline silicon layer 30&#39;. The ion implantation of phosphorous ions is illustrated by arrows, not numbered, in FIG. 2e. The silicon nitride layer 32&#39; and masking layer 30&#39; provide a mask for the ion implantation process to enable the formation of N+ type conductivity source and drain regions, 52&#39;, 50&#39; of the transistor being formed in the region 79 of epitaxial layer 12&#39; in a manner similar to that described in connection with FIG. 1g. Here, however, the concentration of phosphorous atoms in regions 52&#39;, 50&#39; of epitaxial layer 12&#39; is 10 21  atoms/cm 3 . It is again noted that the region 46&#39; in the masking layer 30&#39; is symmetrically disposed with respect to the source and drain regions 52&#39;, 50&#39; because: The silicon nitride layer 32&#39; served as the mask for the implantation of the boron atoms; the diffusion of such boron atoms under the layer 32&#39; was symmetrical so that the region 46&#39; is formed in the center of such layer 32&#39;; and such layer 32&#39; was used for the mask in ion implanting the phosphorous atoms into the portion 79 of the epitaxial layer 12&#39; to form the source and drain regions 52&#39;, 50&#39; in such layer 12&#39;. The photoresist mask is then stripped away using any conventional process. The structure is then placed in a conventional ion implanting apparatus to implant boron ions into the surface of such structure. It is first noted that the layers 30&#39;, 32&#39; provide masks for such boron implantation. Therefore, the boron atoms become implanted into regions 81, 83 to form P+ type conductivity regions in the region 78 of epitaxial layer 12&#39; and in the N+ type conductivity regions 50&#39;, 52&#39; of region 79 of epitaxial layer 12&#39;. The P+ type concentration formed in the P+ regions 81, 83 is 10 20  atoms/cm 3  and hence is an order of magnitude less than the 10 21  atoms/cm 3  concentration in the N+ type conductivity regions 50&#39;, 52&#39;. Therefore, the implanted boron ions do not counter the N+ conductivity in regions 50&#39;, 52&#39;. Alternatively, a photoresist mask may be formed over the region 79 in FIG. 2f, using conventional photolithography, prior to the implantation process to prevent any significant implantation in the region 79. (Such mask would then be removed in a conventional manner after the implantation process.) 
     Referring now also to FIG. 2g, the silicon nitride layer 32&#39; is removed, using a suitable chemical etchant, here hot phosphoric acid. The structure is then immersed in a solution of potassium hydroxide, 1-propanol and water to selectively remove only those portions of the polycrystalline silicon or masking layer 30&#39; having a boron ion concentration of less than 7×10 19  atoms/cm 3 . Alternatively, a solution of ethylene diamine, pyrocatechol and water may be used. As shown, the region 46&#39; is removed by the chemical etchant and the regions 42&#39;, 44&#39; of the layer 30&#39; remain together with the portion of such layer 30&#39; which is disposed over the region 79. The width of the region 46&#39; is determined by the diffusion profile of the boron atoms after the diffusion process as described in connection with FIG. 1h. Next, a photoresist contact mask (not shown) is formed over the surface of the structure using conventional photolithography. 
     The portions of the silicon dioxide layer 14&#39; exposed by apertures in such mask are brought in contact with a suitable etchant, here hydrofloric acid (HF), to etch apertures in such silicon dioxide layer 14&#39; as shown in FIG. 2h. It is noted that the masking layer 30&#39; provides a mask for the etching of the silicon dioxide layer 14&#39; and, therefore, the width of the aperture formed in layer 14&#39; is in the order of 1 μm for reasons discussed above in connection with FIGS. 1g-1i. The photoresist mask is then removed and a metallization layer 62&#39;, here aluminum, is formed over the silicon dioxide layer 14&#39; and through the apertures therein onto the exposed portions of the epitaxial layer 12&#39;. The metallization layer 62&#39; is then masked and suitably processed in a conventional manner to form drain, gate and source electrodes 64&#39;, 66&#39;, 68&#39;, respectively, as shown for the N channel depletion mode MESFET 200 formed in region 79 of the epitaxial layer 12&#39; and drain and source electrodes 90, 94, respectively, as shown, for the P channel enhancement mode MOSFET 202 formed in region 78 of epitaxial layer 12&#39;, as shown. A gate contact 92 is also formed by the aluminum, as shown. Ohmic drain, ohmic source and Schottky gate contacts 70&#39;, 72&#39; and 74&#39;, respectively, are formed in a conventional manner between the aluminum-silicon interfaces. Ohmic source and ohmic drain contacts for MOSFET 202 are formed in a conventional manner between the aluminum-silicon interfaces. It is noted that here the source electrode of MOSFET 202 is connected to the drain electrode of MESFET 200 for reasons to be discussed in connection with FIG. 4. However, such devices need not be so connected in the more general case. 
     Referring now to FIG. 3, logic gate 204 according to the prior art is shown. Such logic gate 204 includes a plurality of MESFET devices Q 1 , Q 2 , Q 3 , Q 4 , Q 5  and Schottky diodes D 1 , D 2 , D 3  arranged as shown and formed on a gallium arsenide (GaAs) substrate. Transistors Q 1 , Q 2  have source electrodes connected to ground and drain electrodes coupled to a +V DD  supply through a depletion load transistor Q 3 . The gate electrodes of transistors Q 1 , Q 2  are connected to logical signal sources A, B, respectively, as indicated. The drain electrode of transistor Q 3  is connected to the +V DD  supply, and the source electrode is connected to the gate electrode of such transistor and to the gate electrode of transistor Q 4 , as shown. The drain electrode of transistor Q 4  is connected to the +V DD  supply and the source electrode is connected to a +V SS  supply through serially connected diodes D 1 , D 2 , D 3  and transistor Q 5 , as shown. Transistor Q 5  acts as a current source such that the diodes D 1 , D 2  and D 3  act to shift the output voltage at the source of the Q 4  source follower negatively by three diode voltage drops. The transistors Q 1 , Q 2  serve as inverters. In operation, if A (or B) is &#34;high&#34;, transistor Q 1  (or Q 2 ) goes &#34;on&#34;, pulling the source electrode of transistor Q 3  to ground. Transistor Q 4  is a depletion mode device and, as noted above, serves as a source follower; therefore, the source electrode of the transistor Q 4  will be one threshold voltage, here 1 volt, more positive than ground potential. That is, if V DD  is here +4 volts and V SS  is -3 volts, then the drain electrode of transistor Q 5  will be (assuming each one of the diodes D 1 , D 2 , D 3  provides a 0.7 volt drop) 1 volt -(3) (0.7) volts =-1.1 volt (i.e., a &#34;low&#34; or logic &#34;0&#34; signal). Conversely, if the logic signals A and B are both &#34;low,&#34; transistor Q 1  and transistor Q 2  have no current flow through them and the drain electrodes of transistors Q 1  and Q 2  go to +V DD . This causes the source electrode of transistor Q 4  to go to (+V DD  -(3)(0.7) volts)=1.9 volts, a &#34;high&#34; or logic &#34;1&#34; signal. (However, such voltage will be clamped to the Schottky diode voltage of another logic gate similar to gate 204 (not shown) which is driven by logic gate 204. Here the Schottky diode voltage is +0.7 volts which is still a &#34;high&#34; or logic &#34;1&#34; signal). Therefore, the logic gate 204 provides the logic function (A+B). 
     While such logic gate 204 may be adequate in some applications, it generally requires relatively large amounts of current to flow through transistors Q 4 , Q 5  and diodes D 1 , D 2 , D 3  in order for the gate to provide rapid switching, particularly where such gate 204 is used to drive high capacitance loads due to long interconnects or large fan output. Such requirement, however, results in such logic gate 204 requiring relatively large amounts of power. 
     Referring now to FIG. 4, a logic gate 206 is shown to include a pair of N channel depletion mode MESFET&#39;s 210, 212, arranged as source followers, serially connected Schottky diodes D A , D B , D C , a P channel enhancement mode MOSFET 202 and an N channel depletion mode MESFET 200 arranged as inverters as shown and formed on a single crystal substrate. Here sapphire substrate 10&#39; is used and the MOSFET 202 and MESFET 200 are here formed by the process described above in connection with FIGS. 2a-2h. As shown, the drain electrodes of transistors 210, 212 are connected to a +V DD  supply and the gate electrodes of such transistors are connected to logic signal sources A, B, respectively, as indicated. The source electrodes of transistors 210, 212 are connected to a V SS  supply through the serially connected Schottky diodes D A , D B , D C  and transistor 214, as shown, and the gate electrode of MOSFET 202, as shown. Transistor 214 acts as a current source and diodes D A , D B , D C  act as voltage level shifters in the manner described above for the prior art gate 204. The drain electrode of MOSFET 202 is connected to the +V DD  supply as shown and the source electrode of MOSFET 202 is connected to the drain electrode of MESFET 200 as shown in FIG. 4 (and FIG. 2h). The source electrode of MOSFET 202 is connected to output conductor 216. The source electrode of MESFET 200 is connected to ground. The gate electrode of MESFET 200 is connected to diode D C  and the drain electrode of transistor 214, as shown. The source electrode of transistor 214 is connected to the -V SS  supply and the gate electrode of such transistor, as shown. 
     In operation, transistors 210, 212 serve, as mentioned above, as source followers and therefore because their source electrodes are tied together the output voltages produced on such source electrodes represent the &#34;AND&#34; logical operation of the logic signals A, B (i.e. A.B). The diodes D A , D B , D C  serve as offset diodes because they translate the output levels of transistors 210, 212, negatively, to compensate for the depletion type threshold voltages of transistors 200, 210 and 212. Transistor 214 serves as a current source for the level shifting diodes D A , D B , D C  and insures that such diodes remain forward-biased at all times. MESFET 200 serves as an inverter with MOSFET 202 serving as a &#34;pull up&#34; device. Because MOSFET 202 is a P channel enhancement mode device, it also operates as an inverter. 
     In operation, if both logic signals (A and B) are &#34;high&#34; the source electrode of transistors 210 and 212 go to +V DD . (Here +V DD  is +4 volts and -V SS  is -3 volts). Diodes D A , D B , D C  try to translate this voltage to +1.9 volts because each one of the diodes D A , D B , D C  provides a 0.7 volt drop (i.e. V DD  -(3)(0.7) volts=+1.9 volts). However, at 0.7 volt the Schottky diode of transistor 200 will forward conduct clamping the input of transistor 200 at 0.7 volt. The MESFET 200 goes &#34;on&#34; and the drain electrode therefore goes to ground potential so that the output on line 216 is &#34;low&#34; or at logic &#34;0&#34; level. It is noted that MOSFET 202 is &#34;off&#34; because the gate electrode of such MOSFET 202 is at, or near, +V DD . Alternatively, if logical A and B are low (i.e., near ground potential), the source electrodes of transistors 210, 212 will go to +1 volt more positive than the &#34;low&#34; logic signal A or B because such transistors 210, 212 are depletion mode source followers. This +1 volt level becomes translated by the diodes D A , D B , D C  to -2.1 volts (i.e., +1 volt -(3)(0.7) volts=-2.1 volts) and therefore MESFET 200 turns &#34;off.&#34; MOSFET 202 turns &#34;on&#34; because of the +1 volt level on its gate electrode and therefore output line 216 goes to +V DD  volts to produce a &#34;high&#34; or logic &#34;1&#34; signal. Therefore, the logic gate 206 provides the logic function AB. 
     It is noted that the serially connected diode circuits D A , D B , D C  and 214 can now be a high impedance circuit because such circuit does not drive the load (i.e., other logic gates and interconnects, not shown) connected to output line 216. Such connected logic gate (or gates), not shown, are driven in complementary fashion by the MOSFET 202 and MESFET 200 and, hence, the power required by gate 206 is significantly lower than that required for gate 204 (FIG. 3) for the same switching speed performance under systems operating conditions. 
     Having described preferred embodiments of this invention, it is now evident that other embodiments incorporating its concepts may be used. For example, while the process has been described above in the formation of a depletion mode field effect transistor, such process may be used in the formation of an enhancement mode field effect transistor. It is felt, therefore, that this invention should not be restricted to the preferred embodiments but rather should be limited only by the spirit and scope of the appended claims.