Abstract:
The drilling and plating of high aspect ratio blind via holes in a multilayer printed circuit board are disclosed. A via hole is drilled through a sub-composite structure. The walls of the via hole are plated with a conductive material, and the hole is filled with a conductive medium. The sub-composite structure proceeds through the remainder of the processing that is necessary to manufacture the printed circuit board up to the completion of the solder mask step. The conductive medium of the via hole is drilled out to achieve a hole size that is of the desired diameter as required by the printed circuit board design.

Description:
CROSS REFERENCE TO RELATED APPLICATION(S)  
       [0001]     This application claims the benefit of U.S. Ser. No. 60/654,591 entitled, “Systems and Methods For A Blind Via In A Printed Circuit Board” by inventors, Suzanne Knight and Douglas Thomas, filed Feb. 17, 2005, incorporated herein by reference in its entirety. 
     
    
     BACKGROUND  
       [0002]     Printed circuit boards, backplanes, midplanes, printed wiring boards, flex circuits, rigid flex-circuits, multi-chip modules (MCM), interposers and the like are herein referred to collectively as “PCBs”.  
         [0003]     A via structure typically provides a conductive path between conductive layers in the z-axis direction (orthogonal to the x-y plane of a PCB). Via holes are formed by a variety of techniques including but not limited to laser drilling, mechanical drilling, and techniques based on photo definition. Via holes are subsequently partially or wholly filled or coated with a conductive material, usually metal. Such via structures may be blind, buried, through-hole and may or may not include pads on the conductive layers, as is well known to those skilled in the art of PCB design.  
         [0004]     Specifically, a blind via hole is an interconnect structure that provides a conductive path between two or more conductive layers in a PCB. One of the two or more conductive layers is an external conductive layer of the PCB. The other conductive layers of the two or more conductive layers are internal layers within the PCB. In other words, a blind via does not extend through all the layers of the PCB.  
         [0005]      FIG. 1  is a schematic that illustrates a drilled and plated blind via hole.  FIG. 1  shows a laminated PCB  102  comprising conductive layers  104 , dielectric layers  106 , a blind via hole  108  and a conductive metal  110  palted over via hole  108 . In one approach, the via hole of  FIG. 1  is drilled by indexing from the surface of laminated PCB  102  and drilling down to the conductive layer  112  to which the blind via  108  is required to connect. Such a blind via should be drilled no further into the PCB than the conductive plane to which the blind is required to connect. Thus, accuracy in drilling is required. Next, a layer of conductive material is deposited on the walls of the blind via hole as part of the normal processing of the PCB.  
         [0006]     However, one of the disadvantages of the above approach is that the depth of the via hole that can be formed in the PCB is limited by the aspect ratio of the blind via hole. The aspect ratio of the blind via hole is the ratio of the depth of the blind via hole to the diameter of the blind via hole before any conductive material is deposited in the via hole. The limitation of the aspect raito is due the current approaches of depositing conductive material in the blind via hole in order to make the blind via a conductive interconnect structure between conductive layers of the PCB. For aspect ratios that are greater than 2:1 for small blind vias, currebt deposition approaches are unable to guarantee that a functionally adequate conductive layer will be deposited on the walls of the via hole. This limitation is due to an increased incidence of chemical contamination as the aspect ratio of the blind via hole increases. Further, under conventional plating methods, there is an increased difficulty in gaining adequate thickness in the deposited conductive layer in the via hole due to hole shielding.  
         [0007]     Another disadvantage of current approaches of depositing conductive material in blind via holes is that the blind via hole must be accurately drilled down to the desired conductive layer in the PCB to which the blind via is required to connect. In order to ensure that that the blind via hole terminates at the desired conductive layer that the via hole is required to contact, the thickness of dielectric layers above and below the desired conductive layer must be at least 5 mils.  
         [0008]     Thus, in view of the foregoing, a plated through hole of a blind via with a high aspect ratio that is greater than 8:1 and that allows for using dielectric layers that have thicknesses less than 5 mils is needed.  
       SUMMARY OF EXEMPLARY EMBODIMENTS  
       [0009]     In certain exemplary embodiments, a high aspect ratio plated through hole (PTH) or blind via hole in a PCB stackup is made by building a sub-composite structure that includes an external conductive layer and an inner conductive layer in the PCB stackup. The inner conductive layer of the PCB is the conductive layer to which the PTH or blind via hole is required to connect. A via hole is drilled through the sub-composite structure such that the via hole is open at both ends and extending from the external conductive layer through the inner conductive layer.  
         [0010]     The walls of the via hole are plated with a conductive material. The plated via hole is then filled with a conductive medium. The sub-composite structure proceeds through the remainder of the processing that is necessary to manufacture the printed circuit board up to the completion of the solder mask step. The conductive medium of the via hole is then drilled out to achieve a hole size that is of the desired diameter as required by the printed circuit board design.  
         [0011]     These and other embodiments and other features disclosed herein will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0012]      FIG. 1  is a schematic that illustrates a drilled and plated blind via hole.  
         [0013]      FIG. 2  is a schematic of a plated through hole at the initial stages of building a PCB stackup, according to certain embodiments.  
         [0014]      FIG. 3  is a schematic of a plated through hole that is filled with a conductive medium, according to certain embodiments.  
         [0015]      FIG. 4  is a schematic that illustrates a drilled hole through a conductive medium filling a plated through hole in a PCB, according to certain embodiments.  
         [0016]      FIG. 5  is a flowchart that illustrates some high-level steps in making a plated through hole in a PCB, according to certain embodiments.  
         [0017]      FIG. 6  is a schematic that shows a plated through hole in a PCB with a connector pin.  
         [0018]      FIG. 7  is a schematic that shows a plurality of plated through holes in a PCB stackup.  
     
    
     DETAILED DESCRIPTION  
       [0019]      FIG. 2  is a schematic of a plated through hole at the initial stages of building a PCB stackup, according to certain embodiments. Specifically,  FIG. 2  shows that a plated blind via of a desired aspect ratio that is greater than 8:1 can be made by first forming a sub-composite structure  209  that comprises conductive layers  204  and dielectric layers  206 . A blind via hole is then drilled through the sub-composite layer, extending from the top layer to the bottom layer  212 . Bottom layer  212  will subsequently form the inner conductive layer of the PCB after one or more additional laminate structures, such as laminate  216 , is added to sub-composite structure  209 . The initial stages of building a PCB stackup in the context of making a high aspect plated through hole in the PCB is described in greater detail herein with reference to the flowchart of  FIG. 5 .  
         [0020]      FIG. 3  is a schematic of a plated through hole that is filled with a conductive medium, according to certain embodiments.  FIG. 3  shows a sub-composite structure  309  comprising conductive layers  304  and dielectric layers  306 . A via hole  308  is drilled through the sub-composite structure  309 , extending from the surface of the sub-composite structure through the conductive layer  312 . The via hole  308  is plated with a conductive layer  310 , after which the via hole  308  is filled with a conductive medium  318 . After the via hole  308  is filled with a conductive medium  318 , one or more additional cores that make up the PCB, such as laminate  316 , is added to sub-composite structure  309 . The process of plating and filing the via hole  308  is described in greater detail herein with reference to the flowchart of  FIG. 5 .  
         [0021]      FIG. 4  is a schematic that illustrates a drilled hole through a conductive medium filling a plated through hole in a PCB, according to certain embodiments.  FIG. 4  shows sub-composite structure  409  comprising conductive layers  404 , and dielectric layers  406 .  FIG. 4  also shows that a core  416  of the PCB has been added to the sub-composite structure at layer  412  after filing the previously plated hole  408  with a conductive medium  418 . After completing the manufacturing of the PCB and applying a layer of solder mask  420  to protect the PCB, the conductive medium  418  is drilled out to form a hole  426 . The process of drilling through the conductive medium is described in greater detail herein with reference to the flowchart of  FIG. 5 .  
         [0022]      FIG. 5  is a flowchart that illustrates some high-level steps in making a plated through hole in a PCB, according to certain embodiments. The flowchart of  FIG. 5  is not limited to the making of one plated through hole in a PCB. The method described with reference to  FIG. 5  may apply to the making of one or more plated through holes in a PCB.  
         [0023]     At block  502 , a sub-composite structure comprising several layers, such as sub-composite structure  209  of  FIG. 2 , is made through normal PCB processes. The conductive layers can be copper foil layers or some other suitable conductive layer. The dielectric layers can be layers of prepreg material.  
         [0024]     At block  504 , a via hole of a desired aspect ratio is drilled through the sub-composite structure. For example, a via hole with an aspect ratio greater than 8:1 is drilled through the sub-composite  209  by indexing from the surface of the sub-composite structure and drilling down to the conductive layer  112  of  FIG. 2  to which the via hole is required to connect.  
         [0025]     At block  506 , the drilled holes are cleaned and desmeared. For example, a chemical process by which the coating of resin that is produced by the heat of drilling is removed from the drilled hole walls and edges of the drilled hole. Additionally, metal burrs and other debris caused by the drilling can be removed and cleaned from the drilled hole.  
         [0026]     At block  508 , the drilled hole is catalyzed in preparation for deposition of an activation layer. As a non-limiting example, a thin coating of electroless copper is chemically deposited on the surface of the sub-composite structure and on the walls of the drilled hole. Such an activation layer creates a metallic base for subsequent electroplating operations.  
         [0027]     At block  510 , an image of a desired circuit is deposited on the inner conductive layer, such as conductive layer  212  of  FIG. 2 . For example, the desired image can be deposited by applying a light sensitive film, using heat and pressure, to the inner conductive layer of the sub-composite structure. The light sensitive film is exposed and developed. Since the drilled hole is to be plated, any film that is tenting the hole is developed off. Areas that are not to be plated are protected by the hardened polymerized resist coat.  
         [0028]     At block  512 , a layer of conductive material is deposited on the exposed areas of the imaged inner conductive layer, the surface of the external conductive layer and walls of the drilled hole. For example, additional copper is electrically plated through an electroplating process onto the exposed electroless copper surfaces of the sub-composite structure including the walls of the drilled hole.  
         [0029]     At block  514 , a protective metal is deposited on the exposed electroplated areas of the sub-composite structure. For example, solder or tin-lead can be plated onto the copper plated surfaces.  
         [0030]     At block  516 , the resist coat described at block  510  is removed from the patterned inner layer of the sub-composite structure. For example, the plating resist can be chemically removed from the patterned inner layer.  
         [0031]     At block  518 , any unwanted base conductive material is etched away from the patterned inner layer at areas that are not protected by the solder or tin-lead protective layer.  
         [0032]     At block  520 , the protective metal layer (solder or tin-lead) is removed. For example, the solder or tin-lead is chemically stripped from all the surfaces.  
         [0033]     At block  536 , the plated via hole, such as hole  308  is filled with a conductive medium, such as conductive medium  318  of  FIG. 3 . As a non-limiting example, a conductive polymer compound that includes silver is deposited as a paste into the plated hole and then cured. The conductive polymer compound protects the plated through hole against chemical degradation during subsequent manufacturing processes for completing the PCB. Further, the conductive polymer compound fills in any holes or thin spots in the plated copper layer on the walls the via hole.  
         [0034]     At block  538 , one or more additional cores that make up the PCB stackup, such as core  316  of  FIG. 3  is attached to layer  312  of the sub-composite structure  310 .  
         [0035]     At block  540 , normal PCB manufacturing steps are performed until after the process of depositing a layer of soldermask, such as layer  420  of  FIG. 4 , to the PCB. As a non-limiting example, a photo-sensitive liquid mask, such as probimer, is applied to the surfaces of the PCB.  
         [0036]     At block  542 , a hole, such as hole  426  of  FIG. 4 , is controlled drilled, by indexing for example, through the conductive medium, such as conductive medium  418  of  FIG. 4 , up to a desired depth. At block  544 , normal PCB manufacturing processes are followed, thereafter.  
         [0037]     As an alternate process, according to certain embodiments, after the process of block  508 , a conductive layer is deposited on all exposed surfaces of the sub-composite structure at block  522 . Next at block  524 , an image of a desired circuit is deposited on the inner conductive layer, such as conductive layer  212  of  FIG. 2 . Next, control is returned to previously described block  514 .  
         [0038]     The process as described with reference to  FIG. 5  results is the creation pf a blind via hole that can serve as a receptacle for a press fit connector pin as in a connector assembly. Further, the process of  FIG. 5  allows blind via holes of a wide variety of aspect ratios to be created with accurate diameter size in order to accommodate many types of press fit connector pins. The accuracy in the diameter size of the blind vias provides improved retention force of the press fit connector pins.  
         [0039]      FIG. 6  is a schematic that shows a plated through hole in a PCB with a connector pin.  FIG. 6  shows a PCB with soldermask layer  620 , conductive layers  604 , dielectric layers  606  and plated through hole  608  that connects conductive layer  603  with conductive layer  612 .  FIG. 6  also shows a connector pin  622  that is inserted into plated through hole  608 .  
         [0040]      FIG. 7  is a schematic that shows a plurality of plated through holes in a PCB stackup.  FIG. 7  shows several plated through holes  708  in which are inserted corresponding connector pins  722 .  FIG. 7  also shows that the PCB stackup is connected to an electrical component  724 .  
         [0041]     In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.