Abstract:
Disclosed is a field effect compound semiconductor device wherein both reduction of sheet resistance due to high-concentration δ-doping, and reduction of remote Coulomb scattering are achieved. A planar doped layer that is planarly doped with impurity atoms to be a channel electron supply source is provided in a lower barrier layer and/or an upper barrier layer, and a barrier layer portion in contact with a channel layer is formed as a III-V compound semiconductor spacer layer wherein a group V element is Sb.

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
       [0001]    This application is a continuation application of International Application PCT/JP2013/072061 filed on Aug. 19, 2013 and designated the U.S., the entire contents of which are incorporated herein by reference. 
     
    
     FIELD 
       [0002]    The present invention relates to a field-effect compound semiconductor device such as a high-electron-mobility transistor (HEMT) which is a high-speed transistor. 
       BACKGROUND 
       [0003]    High-electron-mobility transistors (HEMTs) using III-V group compound semiconductors are high-speed transistors capable of operating in a milliwave (30 GHz to 300 GHz) to sub-milliwave (300 GHz to 3 THz) range. Among them, InP HEMTs using an InAlAs/InGaAs junction structure are field-effect transistors which presently have the world&#39;s highest speed at a cut-off frequency f T =688 GHz (see, for example, Non-Patent Literature 1). 
         [0004]    The cut-off frequency f T , which is one of the indicators of high speed ability of the HEMTs, can be represented as 
         [0000]        f   T =1/{2π( L   g /ν+τ ex )}  (1)
 
         [0000]    where L g  is a gate length, ν is an electron velocity under the gate electrode, and τ ex  is a parasitic delay time. The increase in HEMT speed is mainly achieved by miniaturizing the gate length L g  and increasing the electron velocity ν by using a semiconductor with a small effective mass of electrons for the channel. Those measures are equivalent to the reduction of the intrinsic delay time (=L g /ν) of the HEMT. 
         [0005]    However, the ratio of the parasitic delay time τ ex  in the total delay time has recently become relatively large due to a significant decrease in the intrinsic delay time, and the decrease in the parasitic delay time has also become an important problem in terms of speed increase. 
         [0006]    The effect of source resistance or drain resistance is one of the factors contributing to the parasitic delay time τ ex . The source (drain) resistance is constituted by an ohmic contact resistance and sheet resistance of the channel layer. Among them, the sheet resistance can be reduced by increasing the electron density in the channel layer. Accordingly, an attempt has been made to increase the Si-δ doping amount in the InAlAs electron supply layer above the InGaAs channel layer. 
         [0007]    High-concentration doping of 1×10 13  cm −2  or higher is presently performed as the Si-δ doping. An InP HEMT will be explained hereinbelow with reference to  FIG. 22 .  FIG. 22  is a schematic cross-sectional view of the conventional InP HEMT. As illustrated in the figure, an i-type In 0.52 Al 0.48 As buffer layer  72 , an i-type In 0.52 Al 0.48 As lower barrier layer  73 , an i-type InGaAs channel layer  74 , and an i-type In 0.52 Al 0.48 As spacer layer  75  are successively deposited on a semi-insulating InP substrate  71 . 
         [0008]    Then, a δ doped layer  76  is formed by δ doping Si, and an i-type In 0.5 Al 0.48 As barrier layer  77  and an i-type InP layer  78  are thereafter successively deposited. Those i-type In 0.52 Al 0.48 As spacer layer  75  through the i-type InP layer  78  serve as an upper barrier layer. The i-type InP layer is provided to prevent the exposure of the i-type In 0.52 Al 0.48 As barrier layer  77  which is an Al-containing layer. Then, a source electrode  80  and a drain electrode  81  are provided, with an n-type InGaAs cap layer  79  being located therebelow. A gate electrode  83  is provided in a gate recess portion  82 . 
         [0009]    The sheet resistance R sheet  of the HEMT can be represented as 
         [0000]        R   sheet =1/( eN   s μ)   (2)
 
         [0000]    where N s  is an electron density, μ is an electron mobility, and e is an elementary charge. As a result of performing the high-concentration Si-δ doping, the electron density in the channel layer could be increased. However, the problem arising due to the high-concentration Si-δ doping is that the diffusion amount of Si increases. This issue will be described hereinbelow with reference to  FIGS. 23A and 23B . 
         [0010]      FIGS. 23A and 23B  is an explanatory drawing illustrating the distribution of Si after δ doping,  FIG. 23A  is the distribution diagram in the case of low-concentration δ doping, and  FIG. 23B  is the distribution diagram in the case of high-concentration δ doping. As illustrated in  FIG. 23A , Si introduced by δ doping does not remain “as is” at the initial doping position. Since the growth of the barrier layer or cap layer is performed at a high temperature after the Si-δ doping, the Si which had a substantially δ-function distribution immediately after the doping diffuses up and down in the thickness direction of the grown layer. 
         [0011]    Even when the growth temperature or growth time is the same, where the Si-δ doping concentration is high, Si diffuses closer to the channel layer, as illustrated in  FIG. 23B . Si which is a donor is ionized and, even while remaining in the spacer layer, exerts a Coulomb force to the electrons in the channel layer and causes the remote Coulomb scattering. In particular, since the Coulomb force is inversely proportional to the square of the distance, where the scattering source present in the upper barrier layer approaches the channel layer, the channel electron mobility is greatly reduced and the sheet resistance increases. 
         [0012]    The Si-δ doping method can also have another configuration. In the aforementioned Non-Patent Literature 1 describing how the world&#39;s highest speed has been achieved, Si-δ doping, which is the source of electron supply to the channel layer, is provided in two locations in the InAlAs barrier layer. With such a method, it is possible to increase the electron concentration in the channel layer and reduce the sheet resistance. 
         [0013]    However, since the Si doping amount is increased, the diffusion of Si in the channel layer direction in the crystal growth or processing increases over that in the case of a single location of Si-δ doping. This is because the diffusion of Si in the up-down direction becomes asymmetric due to Si-δ doping in two locations. In particular, with the Si-δ doping dose to the channel, the diffusion in the channel direction is large, whereas the diffusion in the opposite direction is small. 
         [0014]    Si is prevented from diffusing into the channel layer by providing the spacer layer. However, since the amount of Si at a position close to the channel layer increases, the effect of remote Coulomb scattering is enhanced and the electron mobility in the channel layer decreases. For this reason, since the electron mobility μ decreases even when the electron concentration N s  is increased by the double Si-δ doping, the double doping fails to reduce the resistance by half. 
         [0015]    Meanwhile, a double doped structure is also known in which Si-δ doping has been performed above and below an InGaAs channel layer in order to increase the electron concentration in the channel layer. In a HEMT using such a structure the cut-off frequency f T  is reported to be 660 GHz (see, for example, Non-Patent Literature 2). However, in this structure, the diffusion of Si-δ doping in the lower barrier layer is larger than the diffusion of Si-δ doping in the upper barrier layer. As a result, the channel electron concentration is difficult to increase while suppressing the effect of Si diffusion. 
       CITATION LIST 
     Non-Patent Literature 
       [0016]    Non-Patent Literature 1: Kim et al., IEDM Tech. Dig., no. 13.6, December 2011 
         [0017]    Non-Patent Literature 2: Leuther et al., Proc. 23rd IPRM, no. Tu-4. 2. 2, p. 295, May 2011 
         [0018]    Non-Patent Literature 3: M. E. Greiner and J. F. Gibbonset, Appl. Phys. Lett. Vol. 44, p. 750, 1984 
       SUMMARY 
       [0019]    As mentioned hereinabove, because of high-concentration δ doping of Si, the diffusion of Si increases and the ionized Si comes closer to the channel layer. As a result, the remote Coulomb scattering caused by the ionized Si in the barrier layer increases. Since the Coulomb force is inversely proportional to the square of the distance, the ionized Si which has approached the channel layer demonstrates a prominent effect, and the remote Coulomb scattering causes the decrease in the channel electron mobility. The resultant problem is that sheet resistance increases and does not decrease as expected. 
         [0020]    A field-effect compound semiconductor device comprising: 
         [0021]    a semiconductor substrate; 
         [0022]    a lower barrier layer that is provided on the semiconductor substrate; 
         [0023]    a channel layer that is provided in contact with the lower barrier layer; 
         [0024]    an upper barrier layer that is provided in contact with the channel layer; 
         [0025]    a cap layer that is provided in contact with the upper barrier layer; 
         [0026]    a source electrode and a drain electrode that are provided on the cap layer; and 
         [0027]    a gate electrode that is arranged between the source electrode and the drain electrode, wherein 
         [0028]    a planar doped layer that is planarly doped with impurity atoms, which are to be a channel electron supply source, is provided in at least one of the lower barrier layer and the upper barrier layer; and 
         [0029]    a portion of the barrier layer, where the planar doped layer has been provided, is a III-V group compound semiconductor spacer layer in which a V group element is Sb, with this portion being in contact with the channel layer. 
         [0030]    In the disclosed field-effect compound semiconductor device, both the reduction in the sheet resistance, which is due to high-concentration doping, and the reduction in the remote Coulomb scattering can be achieved. 
         [0031]    The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
         [0032]    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0033]      FIG. 1  is a schematic cross-sectional view of a field-effect compound semiconductor device of an embodiment of the present invention. 
           [0034]      FIG. 2  is an explanatory drawing of an impurity diffusion model. 
           [0035]      FIG. 3  is an explanatory drawing of impurity diffusion calculation results. 
           [0036]      FIG. 4  is an explanatory drawing of remote Coulomb scattering calculation model. 
           [0037]      FIG. 5  is a schematic cross-sectional view of the HEMT of Example 1 of the present invention. 
           [0038]      FIG. 6  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention. 
           [0039]      FIG. 7  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 6 . 
           [0040]      FIG. 8  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 7 . 
           [0041]      FIG. 9  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 8 . 
           [0042]      FIG. 10  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 9 . 
           [0043]      FIG. 11  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 10 . 
           [0044]      FIG. 12  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 11 . 
           [0045]      FIG. 13  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 12 . 
           [0046]      FIG. 14  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 13 . 
           [0047]      FIG. 15  is an explanatory drawing illustrating first part of the process for manufacturing the HEMT of Example 1 of the present invention after the process illustrated by  FIG. 14 . 
           [0048]      FIG. 16  is a schematic cross-sectional view of the HEMT of Example 2 of the present invention. 
           [0049]      FIG. 17  is a schematic cross-sectional view of the HEMT of Example 3 of the present invention. 
           [0050]      FIG. 18  is a schematic cross-sectional view of the HEMT of Example 4 of the present invention. 
           [0051]      FIG. 19  is a schematic cross-sectional view of the HEMT of Example 5 of the present invention. 
           [0052]      FIG. 20  is a schematic cross-sectional view of the HEMT of Example 6 of the present invention. 
           [0053]      FIG. 21  is a schematic cross-sectional view of the HEMT of Example 7 of the present invention. 
           [0054]      FIG. 22  is a schematic cross-sectional view of the conventional HEMT. 
           [0055]      FIG. 23A  and  FIG. 23B  are is schematic diagrams illustrating the diffusion of impurities. 
       
    
    
     DESCRIPTION OF EMBODIMENTS 
       [0056]    The field-effect compound semiconductor devices of the embodiments of the present invention will be described hereinbelow with reference to  FIGS. 1 to 4 .  FIG. 1  is a schematic cross-sectional view of a field-effect compound semiconductor device of an embodiment of the present invention. As illustrated in the figure, a buffer layer  2 , a lower barrier layer  3 , and a channel layer  4  are successively formed on a semiconductor substrate  1 . Then, a III-V group compound semiconductor spacer layer  6  in which a V group element is Sb and a spacer layer  7  are successively deposited, a planar doped layer  8  is thereafter formed by δ doping of Si, and then a barrier layer  9  is formed. Layers from the III-V group compound semiconductor spacer layer  6  through the barrier layer  9  constitute an upper barrier layer  5 . Then, a source electrode  11  and a drain electrode  12  are provided, with a cap layer  10  being disposed therebelow, and a gate electrode  13  is provided in a gate recess portion. When the lower barrier layer  3  is lattice matched to the semiconductor substrate  1 , the buffer layer  2  and the lower barrier layer  3  become the same semiconductor layer. However when the lattices are not matched, using a composition-graded semiconductor layer as the buffer layer  2  and forming the layer such that the lattice constant of the uppermost portion of the buffer layer  2  matches the lattice constant of the lower barrier layer  3  are needed. A molecular beam epitaxy (MBE) method is typically used for layer deposition, but a metalorganic vapor phase epitaxy method (MOVPE) may be also used. 
         [0057]    Since Si does not act as a donor in the III-V group compound semiconductor spacer layer  6  in which a V group element is Sb, the ionized Si which causes the remote Coulomb scattering is not present in the III-V group compound semiconductor spacer layer  6 . Therefore, the decrease in channel electron mobility caused by the remote Coulomb scattering can be suppressed. Incidentally, in the III-V group compound semiconductor in which a V group element is Sb, Te is used as a donor impurity. 
         [0058]      FIG. 2  is an explanatory drawing of an impurity diffusion model. The rectangle in the figure illustrates the state in which an impurity is δ doped at a concentration of n 0  in a range with a position x in the lamination direction from −L to +L, that is, the state with (Dt) 1/2 =0. Here D is the diffusion coefficient of the impurity, t is a heat treatment time, that is, the period of time in which crystal growth is performed on the planar doped layer, and (Dt) 1/2  is a diffusion length. 
         [0059]    The impurity concentration distribution n(x, t) after the diffusion caused by the heat treatment is represented as: 
         [0000]        n ( x, t )=( n   0 /2){erf( A )+erf( B )} @ | x|≦L    (3)
 
         [0000]        n ( x, t )=( n   0 /2){erf( A )−erf( B )} @ | x|≧L    (4).
 
         [0000]    Here, erf(x) is an error function, and A and B are 
         [0000]        A =( L+|x |)/{2( Dt ) 1/2 } 
         [0000]        B =( L−|x |)/{2( Dt ) 1/2 }. 
         [0000]    As illustrated in the figure, as the diffusion length increases, the impurity concentration distribution deviates from the steep δ function. 
         [0060]    In the fabrication of an InP HEMT, the crystal growth is performed at about 480° C. to 540° C., and the growth time after Si-δ doping is 2 min to 3 min. Under such conditions, the diffusion length is about (Dt) 1/2 =0.5 nm (see, for example, Non-Patent Literature 3). 
         [0061]      FIG. 3  is an explanatory drawing of impurity diffusion calculation results. The calculations were performed with respect to combinations of three temperature conditions, namely, 500° C., 520° C., and 540° C., and two growth times of 2 min and 3 min. In this case, L is about 0.3 nm where the Si-δ doping amount is taken as 1×10 13  cm −2 , Si is assumed to be δ doped within ±1 monolayer from the center, and the unevenness of an underlayer is taken to be of one monolayer. Therefore, n 0 =1.66×10 20  cm −3 .  FIG. 3  illustrates the results obtained by calculating the distribution of Si from Expressions (3) and (4) above by using the aforementioned numerical values. In the case of an average temperature of 520° C. and a time of 3 min, (Dt) 1/2 =0.5 nm. 
         [0062]      FIG. 4  is an explanatory drawing of a remote Coulomb scattering calculation model. In the mode, the spacer layer, that is, the distance from the interface of the channel layer and the upper barrier layer to the planar doped layer is 3 nm, the III-V group compound semiconductor spacer layer in which a V group element is Sb is 2 nm, and the remaining spacer layer is 1 nm. This configuration is compared with that in which the III-V group compound semiconductor spacer layer in which a V group element is Sb is not present and all 3 nm are taken by the composition same as that of the barrier layer. The calculation in this case is conducted under as assumption that the III-V group compound semiconductor spacer layer in which a V group element is Sb is AlSb and the remaining spacer layer is InAlAs. 
         [0063]    In the calculation, the Coulomb farce received by electrons on the channel layer/AlSb heterojunction interface from the ionized donor at each position x is integrated. Therefore, the total remote Coulomb force F total  is a sum of Coulomb forces F(x) created by the donors present in regions divided by the width Δx. Where x 0  denotes the position of the heterojunction interface, e denotes an elementary charge, and ε denotes a dielectric constant of the semiconductor, 
         [0000]        F   total   =ΣF ( x )=Σ(4πε) −1   ×n ( x )Δ xe   2   /|x   0   −x|   2   =e   2 /(4πε)Σ n ( x )Δ x/|x   0   −x|   2 .
 
         [0064]    In the case of 520° C., 3 min, and (Dt) 1/2 =0.5 nm, the ratio of the electron concentration n total(with AlSb)  obtained when AlSb is introduced to the electron concentration n total(without AlSb)  obtained without the introduction of AlSb, that is, n total(with AlSb) /n total(without AlSb) , is about 0.914. It is clear that the reduction in the number of channel electrons caused by the introduction of AlSb is 10% or less. 
         [0065]    As for the ratio of Coulomb forces which are created by ionized donors and received by channel electrons, where the ionized donor distribution is taken into account, the Coulomb forces appear to change significantly from the inverse proportionality to the square of the distance. The ratio of the Coulomb force F total(with AlSb)  obtained when AlSb is introduced to the Coulomb force F total(without AlSb)  obtained without the introduction of AlSb, that is, F total(with AlSb) /F total(without AlSb) , is about 0.573, that is, reduces to about half. Therefore, it is clear that the remote Coulomb scattering can be suppressed. 
         [0066]    Incidentally, where the thickness of the AlSb spacer layer is taken as 2.5 nm, n total(with AlSb) /n total(without AlSb)  is about 0.754 and F total(with AlSb) /F total(without AlSb)  is about 0.410 and the Coulomb force is small, but the channel electron concentration decreases significantly. Therefore, it is desirable that the thickness of the III-V compound semiconductor spacer layer be 50% to 80% of the thickness between the channel layer/upper barrier layer interface and the planar doped layer. 
         [0067]    Another advantage is that since the energy at the conduction band edge of AlSb is higher than that of InAlAs as a barrier, quantum-mechanical penetration of channel electrons into the barrier layer or the real spatial transition between the upper barrier layer and channel layer can be suppressed. The lattice constant of AlSb is significantly different from that of other layers, but when it is used as a spacer layer, a thickness of about 2 nm to 2.5 nm is sufficient. Therefore, strained AlSb can be grown without the degradation of crystal quality. 
         [0068]    In the above-described embodiment, the planar doped layer is provided in one location in the upper barrier layer, but it may be also provided in the lower barrier layer or in the upper and lower barrier layers. Further, the planar doped layer may be provided in two or more locations in the same barrier layer, rather than in one location. When the planar doped layer is provided in two or more locations in the same barrier layer, the distance between the planar doped layers is set to 2 nm to 3 nm. 
         [0069]    As a specific structure, the semiconductor substrate  1  is a semi-insulating InP substrate, semi-insulating GaAs substrate, or Si substrate. In the case of an InP HEMT, an InAlAs/InGaAs heterostructure is formed on the semi-insulating InP substrate, semi-insulating GaAs substrate, or Si substrate. When the heterostructure is formed on the semi-insulating InP substrate, the buffer layer  2  can use In 0.52 Al 0.48 As same as in the lower barrier layer  3 . By contrast, when the heterostructure is formed on the semi-insulating GaAs substrate or Si substrate, using a composition-graded semiconductor layer (in this case, the lattice constant is made to increase gradually) as the buffer layer  2  and forming the layer such that the lattice constant of the uppermost portion of the buffer layer  2  matches the lattice constant of the In 0.52 Al 0.48 As lower barrier layer  3  are needed. In the case of a GaAs HEMT, an AlGaAs/(In)GaAs heterostructure is formed on the semi-insulating GaAs substrate or Si substrate. When the heterostructure is formed on the semi-insulating GaAs substrate, the buffer layer  2  can use AlGaAs same as in the lower barrier layer  3 . By contrast, when the heterostructure is formed on the Si substrate, using a composition-graded semiconductor layer (in this case, the lattice constant is made to increase gradually) as the buffer layer  2  and forming the layer such that the lattice constant of the uppermost portion of the buffer layer  2  matches the lattice constant of the AlGaAs lower barrier layer  3  are needed. There are a great variety of buffer layer structures, and the structure of this layer cannot be uniquely defined. 
         [0070]    When a semi-insulating InP substrate is used, the lower barrier layer  3  is an InAlAs layer, and the channel layer  4  is an InGaAs layer or a laminated structure of an InGaAs layer and an InAs layer. Further, a portion of the upper barrier layer  5  other than the III-V compound semiconductor spacer layer  6  is an InAlAs layer or a laminated structure of an InAlAs layer and an InP layer. The cap layer  10  is an n-type InGaAs layer or a laminated structure of an n-type InGaAs layer and an n-type InAlAs layer. 
         [0071]    When a semi-insulating GaAs substrate is used, the lower barrier layer  3  is an AlGaAs layer, and the channel layer  4  is a GaAs layer or an InGaAs layer. A portion of the upper barrier layer  5  other than the III-V compound semiconductor spacer layer  6  is an AlGaAs layer, and the cap layer  10  is an n-type GaAs layer. 
         [0072]    Further, the III-V compound semiconductor spacer layer is any one of the AlSb layer, AlGaSb layer, AlInSb layer, and AlGaInSb layer. A GaSb layer is conductive, but when the Ga composition ratio is small, no problem is associated with the AlGaSb layer or AlGaInSb layer. 
         [0073]    An insulating film may be provided on the exposed flat surface of the cap layer, and the foot portion of the gate electrode can be supported by causing the side end surface of the opening provided in the insulating film to abut against the side end surface of the gate electrode. 
         [0074]    In the embodiments of the present invention, a very thin layer of AlSb in which Si is ionized and does not become a donor is provided in the spacer portion in the barrier layer. Therefore, where the electron concentration in the channel layer is to be increased by increasing Si-δ doping which provides an electron supply layer, even though Si diffuses close to the channel layer in the spacer layer, it does not become the remote Coulomb scattering source and the electron mobility in the channel layer does not decrease. 
       EXAMPLE 1 
       [0075]    The HEMT of Example 1 of the present invention will be explained hereinbelow with reference to  FIGS. 5 to 15 .  FIG. 5  is a schematic cross-sectional view of the HEMT of Example 1 of the present invention. As illustrated in the figure, an i-type In 0.52 Al 0.48 As buffer layer  22 , an i-type In 0.52 Al 0.48 As lower barrier layer  23 , and an i-type InGaAs channel layer  24  are successively deposited on a semi-insulating InP substrate  21 . Then, an i-type AlSb spacer layer  25  and an i-type In 0.52 Al 0.48 As spacer layer  26  are successively deposited, and a δ doped layer  27  is thereafter formed by δ doping of Si. 
         [0076]    Then, an i-type In 0.52 Al 0.48 As barrier layer  28  and an i-type InP layer  29  are successively deposited. The i-type AlSb spacer layer  25  through the i-type InP layer  29  constitute the upper barrier layer. The i-type InP layer  29  is provided to prevent the exposure of the i-type In 0.52 Al 0.48 As barrier layer  28  which is an Al-containing layer. Then, a source electrode  31  and a drain electrode  32  are provided, with an n-type InGaAs cap layer  30  being provided therebelow. A gate electrode  41  is provided in a gate recess portion  40 . 
         [0077]    Thus, in Example 1 of the present invention, the i-type AlSb spacer layer in which Si is ionized and does not become a donor is provided at the interface with the i-type InGaAs channel layer  24 . Therefore, the effect of remote Coulomb scattering can be greatly reduced. 
         [0078]    A process for manufacturing the HEMT of Example 1 of the present invention will be explained hereinbelow with reference to  FIGS. 6 to 15 . Initially, as illustrated in  FIG. 6 , the i-type In 0.52 Al 0.48 As buffer layer  22  with a thickness of 1000 nm, the i-type In 0.52 Al 0.48 As layer lower barrier layer  23  with a thickness of 200 nm, and the i-type InGaAs channel layer  24  with a thickness of 10 nm are deposited by the MBE method on the semi-insulating InP substrate  21 . Then, the i-type AlSb spacer layer  25  with a thickness of 2 nm and the i-type In 0.52 Al 0.48 As spacer layer  26  with a thickness of 1 nm are deposited. 
         [0079]    Then, the δ doped layer  27  is formed by using a cell containing a solid Si source and performing doping of Si. The δ doping amount of Si is taken as 1×10 13  cm −2 . Then, the i-type In 0.52 Al 0.48 As barrier layer  28  with a thickness of 6 nm, the i-type InP layer  29  with a thickness of 3 nm, and the n-type InGaAs cap layer  30  with a thickness of 20 nm are deposited. The composition of the i-type InGaAs channel layer  24  is In x Ga 1-x As (0.8≧x≧0.53), and the composition of the n-type InGaAs cap layer  30  is In 0.53 Ga 0.47 As. The time of the growth process after the δ doping is about 3 min. The impurity concentration in the n-type InGaAs cap layer  30  is 2×10 19  cm −3 . 
         [0080]    Then, the laminated structure provided on the wafer is divided into element regions, and the source electrode  31  and the drain electrode  32  are thereafter formed by depositing metal electrodes constituted by a Ti/Pt/Au laminated structure on the n-type InGaAs cap layer  30 , as illustrated in  FIG. 7 . 
         [0081]    Then, as illustrated in  FIG. 8 , a SiO 2  film  33  with a thickness of 20 nm is formed on the n-type InGaAs cap layer  30  between the source electrode  31  and the drain electrode  32  by using a plasma CVD method. 
         [0082]    Then, as illustrated in  FIG. 9 , a first resist layer  34  is formed on the SiO 2  film  33  in the recess portion between the source electrode  31  and the drain electrode  32 , and a second resist layer  35  and a third resist layer  36  are formed on the first resist layer. In this case, an electron beam resist ZEP (trade name, ZEON CORPORATION) is used as the first resist layer  34  and the third resist layer  36 . Further, PMGI (Poly-dimethylglutarimide: manufactured by MicroChem Corp., trade name) is used as the second resist layer  35 . The thickness of the first resist layer  34  changes depending on the length of the foot portion of the gate electrode. For this reason, in  FIGS. 9 to 14 , the thickness of the first resist layer  34  represents the uppermost portion of the metal used for the source electrode  31  and the drain electrode  32 , but the thickness can be larger or smaller than this. When the thickness is large, the first resist layer  34  covers both the source electrode  31  and the drain electrode  32 . When the thickness is small, the second resist layer  35  penetrates between the source electrode  31  and the drain electrode  32 . 
         [0083]    Then, as illustrated in  FIG. 10 , the head portion of the T-shaped gate electrode is exposed by the electron beam exposure method and an opening  37  is formed by developing the third resist layer  36  and the second resist layer  35 . Then, as illustrated in  FIG. 11 , highly accurate exposure of the first resist layer  34  is further performed by the electron beam exposure method to match the target gate length, and an opening  38  corresponding to the foot portion of the T-shaped gate electrode is formed. 
         [0084]    Then, as illustrated in  FIG. 12 , an opening  39  is formed by removing the exposed portion of the SiO 2  film  33  by reactive ion etching by using the first resist layer  34 , in which the opening  38  has been formed, as a mask. CF 4  is used as the etching gas. 
         [0085]    Then, as illustrated in  FIG. 13 , the n-type InGaAs cap layer  30  is etched by performing wet etching using the SiO 2  film  33 , in which the opening  39  has been formed, as a mask, thereby forming a gate recess portion  40  and electrically separating the n-type InGaAs cap layer  30 . A mixed solution of citric acid (C 6 H 8 O 7 ) and hydrogen peroxide (H 2 O 2 ) is used as the etching solution. 
         [0086]    Then, as illustrated in  FIG. 14 , a Ti/Pt/Au laminated film is vapor deposited as a gate electrode  41 . Then, as illustrated in  FIG. 15 , layers from the third resist layer  36  through the first resist layer  34  are removed and the Ti/Pt/Au laminated film deposited on the third resist layer  36  is also removed by lift-off, thereby producing the basic structure of the HEMT of Example 1 of the present invention. 
       EXAMPLE 2 
       [0087]    The HEMT of Example 2 of the present invention will be explained hereinbelow with reference to  FIG. 16 . In the HEMT of Example 2, Si-δ doping is performed twice in the upper barrier layer. Other features, namely, the thickness of the layers, impurity concentrations, and compositions are the same as in Example 1.  FIG. 16  is a schematic cross-sectional view of the HEMT of Example 2 of the present invention. As illustrated in the figure, the i-type In 0.52 Al 0.48 As buffer layer  22 , the i-type In 0.52 Al 0.48 As lower barrier layer  23 , and the i-type InGaAs channel layer  24  are successively deposited on the semi-insulating InP substrate  21 . Then, the i-type AlSb spacer layer  25  and the i-type In 0.52 Al 0.48 As spacer layer  26  are successively deposited, and the δ doped layer  27  is thereafter formed by δ doping of Si. 
         [0088]    Then, the i-type In 0.52 Al 0.48 As spacer layer  42  with a thickness of 2 nm is deposited and then the δ doped layer  43  is formed by again performing the Si-δ doping to about 1×10 13  cm −2 . Then, again, the i-type In 0.52 Al 0.48 As barrier layer  28  and the i-type InP layer  29  are successively deposited in the same manner as in Example 1. The layers from the i-type AlSb spacer layer  25  through the i-type InP layer  29  constitute the upper barrier layer. Then, the source electrode  31  and the drain electrode  32  are provided, with the n-type InGaAs cap layer  30  being provided therebelow. The gate electrode  41  is provided in the gate recess portion  40 . 
         [0089]    Thus, in Example 2 of the present invention, the i-type AlSb spacer layer is provided at the interface with the i-type InGaAs channel layer  24 . Therefore, although two I doped layers are provided and the carrier supply capacity is increased, the effect of remote Coulomb scattering can be greatly reduced. 
       EXAMPLE 3 
       [0090]    The HEMT of Example 3 of the present invention will be explained hereinbelow with reference to  FIG. 17 . In the HEMT of Example 3, the Si-δ doping is performed in the lower barrier layer. Other features, namely, the thickness of the layers, impurity concentrations, and compositions are the same as in Example 1.  FIG. 17  is a schematic cross-sectional view of the HEMT of Example 3 of the present invention. As illustrated in the figure, the i-type In 0.52 Al 0.48 As buffer layer  22  and the i-type In 0.52 Al 0.48 As lower barrier layer  23  are successively deposited on the semi-insulating InP substrate  21 . 
         [0091]    Then, a δ doped layer  44  is formed by performing the Si-δ doping to about 1×10 13  cm −2 , and an i-type In 0.52 Al 0.48 As spacer layer with a thickness of 1 nm and an i-type AlSb spacer layer  46  with a thickness of 2 nm are thereafter formed. The i-type InGaAs channel layer  24 , i-type AlSb spacer layer  25 , and i-type In 0.52 Al 0.48 As spacer layer  26  are then successively formed and the δ doped layer  27  is formed by δ doping of Si in the same manner as in Example 1. 
         [0092]    Then, the i-type In 0.52 Al 0.48 As barrier layer  28  and the i-type InP layer  29  are successively deposited. The source electrode  31  and the drain electrode  32  are then provided, with the n-type InGaAs cap layer  30  being provided therebelow. The gate electrode  41  is provided in the gate recess portion  40 . 
         [0093]    Thus, in Example 3 of the present invention, the carrier supply capacity is increased by providing the δ doped layer in the upper and lower barrier layers, but because the AlSb spacer layer is provided on the interfaces of the upper and lower barrier layers with the channel layer, the effect of remote Coulomb scattering can be greatly reduced. 
       EXAMPLE 4 
       [0094]    The HEMT of Example 4 of the present invention will be explained hereinbelow with reference to  FIG. 18 . In the HEMT of Example 4, the Si-δ doping is performed on the lower barrier layer side, by contrast with Example 1. Other features, namely, the thickness of the layers, impurity concentrations, and compositions are the same as in Example 1.  FIG. 18  is a schematic cross-sectional view of the HEMT of Example 4 of the present invention. As illustrated in the figure, the i-type In 0.52 Al 0.48 As buffer layer  22  and the i-type In 0.52 Al 0.48 As lower barrier layer  23  are successively deposited on the semi-insulating InP substrate  21 . 
         [0095]    Then, a δ doped layer  44  is formed by performing the Si-δ doping to about 1×10 13  cm −2 , and the i-type In 0.52 Al 0.48 As spacer layer  45  with a thickness of 1 nm and the i-type AlSb spacer layer  46  with a thickness of 2 nm are thereafter formed. The i-type InGaAs channel layer  24 , the i-type In 0.52 Al 0.48 As barrier layer  28  and the i-type InP layer  29  are then successively deposited. The source electrode  31  and the drain electrode  32  are then provided, with the n-type InGaAs cap layer  30  being provided therebelow. The gate electrode  41  is provided in the gate recess portion  40 . 
         [0096]    Thus, in Example 4 of the present invention, the δ doped layer is provided in the lower barrier layer, but because the AlSb spacer layer is provided on the interface of the lower barrier layer with the channel layer, the effect of remote Coulomb scattering can be greatly reduced. 
       EXAMPLE 5 
       [0097]    The HEMT of Example 5 of the present invention will be explained hereinbelow with reference to  FIG. 19 . In the HEMT of Example 5, the Si-δ doping is performed twice in either of the upper and lower barrier layers. Other features, namely, the thickness of the layers, impurity concentrations, and compositions are the same as in Example 1.  FIG. 19  is a schematic cross-sectional view of the HEMT of Example 5 of the present invention. As illustrated in the figure, the i-type In 0.52 Al 0.48 As buffer layer  22  and the i-type In 0.52 Al 0.48 As lower barrier layer  23  are successively deposited on the semi-insulating InP substrate  21 . 
         [0098]    Then, a δ doped layer  47  is formed by performing the Si-δ doping to about 1×10 13  cm −2 , and then the i-type In 0.52 Al 0.48 As spacer layer  48  with a thickness of 2 nm is formed. The δ doped layer  44  is then formed by again performing the Si-δ doping to about 1×10 13  cm −2 , and the i-type In 0.52 Al 0.48 As spacer layer  45  with a thickness of 1 nm and the i-type AlSb spacer layer  46  with a thickness of 2 nm are thereafter formed. 
         [0099]    The i-type InGaAs channel layer  24 , the i-type AlSb spacer layer  25 , and the i-type In 0.52 Al 0.48 As spacer layer  26  are then successively deposited, and the δ doped layer  27  is then formed by δ doping of Si. The i-type In 0.52 Al 0.48 As spacer layer  42  with a thickness of 2 nm is then deposited, and the δ doped layer  43  is then formed by again performing the Si-δ doping to about 1×10 13  cm −2 . The i-type In 0.52 Al 0.48 As spacer barrier  28  and the i-type InP layer  29  are then successively deposited in the same manner as in Example 1. The source electrode  31  and the drain electrode  32  are then provided, with the n-type InGaAs cap layer  30  being provided therebelow. The gate electrode  41  is provided in the gate recess portion  40 . 
         [0100]    Thus, in Example 5 of the present invention, the carrier supply capacity is further increased by providing two δ doped layers in the upper and lower barrier layers, but because the AlSb spacer layer is provided on the interfaces of the upper and lower barrier layers with the channel layer, the effect of remote Coulomb scattering can be greatly reduced. 
       EXAMPLE 6 
       [0101]    The HEMT of Example 6 of the present invention will be explained hereinbelow with reference to  FIG. 20 . In the HEMT of Example 6, the Si-δ doping is performed twice only in the lower barrier layer. Other features, namely, the thickness of the layers, impurity concentrations, and compositions are the same as in Example 1.  FIG. 20  is a schematic cross-sectional view of the HEMT of Example 6 of the present invention. As illustrated in the figure, the i-type In 0.52 Al 0.48 As buffer layer  22  and the i-type In 0.52 Al 0.48 As lower barrier layer  23  are successively deposited on the semi-insulating InP substrate  21 . 
         [0102]    Then, the δ doped layer  47  is formed by performing the Si-δ doping to about 1×10 13  cm −2 , and then the i-type In 0.52 Al 0.48 As spacer layer  48  with a thickness of 2 nm is formed. The δ doped layer  44  is then formed by again performing the Si-δ doping to about 1×10 13  cm −2 , and the i-type In 0.52 Al 0.48 As spacer layer  45  with a thickness of 1 nm and the i-type AlSb spacer layer  46  with a thickness of 2 nm are thereafter formed. 
         [0103]    The i-type InGaAs channel layer  24 , the i-type In 0.52 Al 0.48 As spacer barrier  28 , and the i-type InP layer  29  are then successively deposited. The source electrode  31  and the drain electrode  32  are then provided, with the n-type InGaAs cap layer  30  being provided therebelow. The gate electrode  41  is provided in the gate recess  40 . 
         [0104]    Thus, in Example 6 of the present invention, the carrier supply capacity is increased by providing two δ doped layers in the lower barrier layer, but because the AlSb spacer layer is provided on the interface of the lower barrier layer with the channel layer, the effect of remote Coulomb scattering can be greatly reduced. 
       EXAMPLE 7 
       [0105]    The HEMT of Example 7 of the present invention will be explained hereinbelow with reference to  FIG. 21 . The HEMT of Example 7 is a GaAs HEMT with a GaAs substrate. The basic configuration thereof is the same as in Example 1.  FIG. 21  is a schematic cross-sectional view of the HEMT of Example 7 of the present invention. As illustrated in the figure, and i-type AlGaAs buffer layer  52  with a thickness of 1000 nm and an i-type AlGaAs lower barrier layer  53  with a thickness of 200 nm are successively deposited on a semi-insulating GaAs substrate  51 . 
         [0106]    Then, an i-type InGaAs channel layer  54  with a thickness of 10 nm, an i-type AlSb spacer layer  55  with a thickness of 2 nm, and an i-type AlGaAs spacer layer  56  with a thickness of 1 nm are successively deposited, and a δ doped layer  57  is formed by δ doping of Si. An i-type AlGaAs buffer layer  58  with a thickness of 6 nm and an n-type GaAs cap layer  59  with an impurity concentration of 2×10 19  cm −3  and a thickness of 20 nm are then deposited. A source electrode  60  and a drain electrode  61  are then provided, with an n-type GaAs cap layer  59  being provided therebelow. A gate electrode  64  is provided in the gate recess  63 . In the GaAs HEMT, a SiO 2  film  62  is also provided on the exposed fiat surface of an n-type GaAs cap layer  59 . 
         [0107]    Thus, in Example 7 of the present invention, a GaAs HEMT is provided in which the substrate is from GaAs, but the circumstances of remote Coulomb diffusion which follows the increase in impurity concentration in the δ doped layer are the same as in the InP HEMT. In this case, since the AlSb spacer layer is provided on the interface of the AlGaAs barrier layer, which has been provided with the δ doped layer, with the channel layer, the effect of remote Coulomb scattering can be greatly reduced. Further, in this Example 7, the δ doped layer is provided only on the upper barrier layer side, as in the above-described Example 1. However, the δ doped layer may be also provided in the lower barrier layer or the upper and lower barrier layers, or a plurality of δ doped layers may be provided in the same barrier layer in the same manner as in Examples 2 to 6. Further, in Example 7, the channel layer is from InGaAs, but GaAs may be also used therefor. 
         [0108]    All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.