Abstract:
An asymmetric Static Random Access Memory (SRAM) cell is provided. The SRAM cell comprises first and second storage nodes, drive transistors and access transistors. The first and second storage nodes are configured to store complementary voltages. The drive transistors are configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop. The access transistors are configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents. A method for reading from and writing to the SRAM cell are also provided.

Description:
[0001]     The present invention relates generally to four-transistor Static Random Access Memory (SRAM) cells and specifically to an improved asymmetric four-transistor SRAM cell topology.  
       BACKGROUND  
       [0002]     Static Random Access Memories (SRAMs) are one of the most popular ways to store data in electronic systems. Similarly, embedded SRAMs are a vital building block in integrated circuits. SRAMs are popular due to a relatively high speed, robust design and ease of integration. However, SRAMs, in general, occupy a significantly large portion of a chip&#39;s die area, making it an important block in terms of area, yield, reliability and power consumption. With increasing demand for highly integrated System on Chip designs, improving various aspects of embedded SRAMs has received significant interest.  
         [0003]     A six-transistor (6T) SRAM cell is a popular configuration because of its high speed and robustness. This configuration, however, suffers from relatively high area due to the large number of transistors. Large cell area leads to longer bit-lines, word-lines and other control wires that run across an SRAM array. A long wire has relatively large capacitive load which either increases the dynamic power consumption or reduces the operational speed. Therefore, reducing the size of an SRAM cell is important and researchers have proposed several methods and techniques to do so.  
         [0004]     Dynamic random access memory (DRAM) cells, which require less area than SRAMs have been developed. However, DRAMs require a special semiconductor manufacturing process and are, therefore, not easily integrated with conventional complementary metal-oxide-semiconductor (CMOS) digital circuits.  
         [0005]     Conventional four-transistor (C4T) SRAMs have also been developed. Since SRAM can be implemented in a conventional CMOS technology, a C4T SRAM configuration it can easily be integrated into digital circuits. However, poor stability of the C4T cell makes its configuration less desirable.  
         [0006]     Accordingly, it is an object of the present invention to obviate or mitigate at least some of the above-mentioned disadvantages.  
       SUMMARY  
       [0007]     An asymmetric, four-transistor (A4T) SRAM cell topology provides an improved cell stability and reduced cell read time as compared to the conventional 4T cell topology. Further, the A4T SRAM cell topology provides a reduced cell area as compared to conventional 6T SRAM cells, thereby allowing a higher cell density.  
         [0008]     In accordance with an aspect of the present invention there is provided a Static Random Access Memory (SRAM) cell comprising: first and second storage nodes configured to store complementary voltages; drive transistors configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and maintain a first logic state through a feedback loop; and access transistors configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines and maintain a second logic state through relative transistor leakage currents.  
         [0009]     In accordance with a further aspect of the present invention there is provided A method for reading a logic value from an SRAM cell comprising first and second storage nodes configured to store complementary voltages, drive transistors configured to selectively couple each of the first and second storage nodes to corresponding high and low voltage power supplies, and access transistors configured to selectively couple each of the first and second storage nodes to corresponding first and second bit-lines, the method comprising the steps of: pre-charging the bit-lines to a predetermined pre-charge voltage; accessing the cell by activating at least one of the access transistors; and sensing a change on the corresponding bit-line to determine the logic value stored in the cell. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0010]     Embodiments of the invention will now be described by way of example only with reference to the following drawings in which:  
         [0011]      FIG. 1  is a circuit diagram illustrating a conventional 4T SRAM cell;  
         [0012]      FIG. 2  is a circuit diagram illustrating an asymmetric 4T SRAM cell in accordance with one embodiment;  
         [0013]      FIG. 3  is a graph illustrating a waveform plot for a read operation on a 4T SRAM cell as illustrated in  FIG. 2  holding a logic zero;  
         [0014]      FIG. 4  is a graph illustrating a waveform plot for a read operation on a 4T SRAM cell as illustrated in  FIG. 2  holding a logic one;  
         [0015]      FIG. 5  is a graph illustrating a waveform plot for a write operation on a 4T SRAM cell as illustrated in  FIG. 2  for writing a logic zero;  
         [0016]      FIG. 6  is a graph illustrating a waveform plot for a write operation on a 4T SRAM cell as illustrated in  FIG. 2  for writing a logic one;  
         [0017]      FIG. 7  is a block diagram illustrating a column of 4T SRAM cells illustrated in  FIG. 2 ;  
         [0018]      FIG. 8  is a block diagram illustrating an array of 4T SRAM cells as a plurality of columns illustrated in  FIG. 7 ; and  
         [0019]      FIG. 9  is a block diagram illustrating an SRAM unit comprising a plurality of arrays illustrated in  FIG. 8 . 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0020]     For convenience, like numerals in the description refer to like structures in the drawings. Referring to  FIG. 1 , a conventional four-transistor (C4T) SRAM cell is illustrated generally by numeral  100 .  
         [0021]     The C4T cell  100  comprises a pair of access p-channel metal-oxide-semiconductor (PMOS) transistors M 4  and M 3  and a pair of drive n-channel metal-oxide-semiconductor (NMOS) transistors M 1  and M 2 .  
         [0022]     The C4T cell  100  is coupled between a pair of complementary bit-lines BL and  BL . Specifically, the access transistor M 3  and the drive transistor M 1  are serially coupled between one of the bit-lines  BL  and ground V L , respectively. Similarly, the access transistor M 4  and the drive transistor M 2  are serially coupled between the other bit-lines BL and ground V L , respectively. The gate of drive transistor M 2  is coupled to node A, located between the access transistor M 3  and the drive transistor M 1 . The gate of drive transistor M 1  is coupled to node B, located between the access transistor M 4  and the drive transistor M 2 . The gates of access transistors M 3  and M 4  are coupled to a word-line (not shown).  
         [0023]     Accordingly, the C4T cell is able to store two states on its internal nodes A and B when the access transistors M 3  and M 4  are turned off. For example, when node A carries a high voltage V H  it turns on drive transistor M 2 . In turn, drive transistor M 2  forces a low voltage V L  at node B. This effect results in a gate source voltage Vgs of drive transistor M 1  to be equal to zero volts. Hence drive transistor M 1  remains off. The pre-charge voltage V H  of the bit-line pair BL and  BL  will remain at node A as long as the leakage current through access transistor M 3  overcomes that of drive transistor M 1 .  
         [0024]     In this configuration the stability of the cell depends on the relative leakage through access and driver transistors. Therefore, threshold voltage fluctuations of NMOS and PMOS transistors can affect the stability of the cell significantly. For example, if node A stores a high voltage V H  and node B stores a low voltage V L , a higher threshold voltage for access transistor M 3  or a lower threshold voltage for drive transistor M 1  may result in a poor stability at node A. In addition, the Vgs of drive transistor M 1  is equal to zero volts at best and, therefore, it is difficult to control the leakage through circuit means. If, due to an imperfection, node A cannot hold a proper high voltage V H , the node voltage will drop. This drop affects the current of driver transistor M 2 , which results in poor stability at node B, as well as slower and non-robust read operation. In extreme circumstances, the positive feedback in the C4T cell  100  may force the C4T cell  100  to lose its data.  
         [0025]     In accordance with present embodiment an asymmetric four-transistor (A4T) SRAM cell is provided. The A4T SRAM cell operates asymmetrically in holding a logic one and logic zero and occupies a smaller area than a common six transistor SRAM cell. Further, A4T SRAM cell is more stable than conventional four-transistor SRAM cells.  
         [0026]     In the proposed configuration, the A4T cell comprises of two NMOS and two PMOS transistors. The transistors are connected such that they have two internal nodes, which are each capable of holding two states. One NMOS transistor and one PMOS transistor are used as access transistors, which connect the internal nodes to a complementary bit-line pair. The other PMOS and NMOS transistors are used as drive transistors. The PMOS drive transistor connects one of the two internal nodes to a high voltage V H  and the NMOS drive transistor connects the other internal node to a low voltage V L . The pre-charge voltages of the bit-lines are set accordingly.  
         [0027]     Referring to  FIG. 2 , an implementation of the A4T SRAM cell (also referred to hereafter as “the cell”) is illustrated by numeral  200 . The cell  200  comprises two PMOS transistors MP 1  and MP 2 , two NMOS transistors MN 1  and MN 2 , and two internal nodes A and B. The cell  200  is coupled between a complementary bit-line pair BL and  BL . Further, cell  200  access is facilitated by a word-line pair WL and  WL .  
         [0028]     The drain terminals of transistors MN 1  and MP 2 , and the gate terminal of transistor MP 1  are electrically connected at node A. Similarly, the drain terminals of transistors MN 2  and MP 1 , and the gate terminal of MN 1  are electrically connected at node B.  
         [0029]     The source terminals of transistors MN 1  and MP 1  are coupled to a low voltage supply V L  and a high voltage supply V H , respectively, and are referred to as the drive transistors. The gate terminals of MN 1  and MP 1  are driven by nodes B and A, respectively. Therefore, there is an internal loop between the internal nodes of the circuit through the drive transistors.  
         [0030]     The source terminals of transistors MN 2  and MP 2  are coupled to the bit-line pair  BL  and BL, respectively, and are referred to as the access transistors. A nominal high pre-charge voltage VBL H  of the bit-line BL is a high voltage and a nominal low pre-charge voltage VBL L  of the bit-line  BL  is a low voltage.  
         [0031]     The gate terminals of transistors MN 2  and MP 2  are driven by complementary word-line signals WLB and WLA, respectively. The cell can be accessed when either one or both of the access transistors MN 2  and MP 2  are turned on. As will be appreciated, this may improve the stability of the cell  200  during a read operation, as it is less exposed to the outside influence of the bit-lines  BL  and BL.  
         [0032]     Since transistor MP 2  is a PMOS transistor the voltage V WLA  of the word-line WLA is reduced to turn on transistor MP 2 . Conversely, since transistor MN 2  is an NMOS transistor, the voltage V WLB  the word-line WLB is increased to turn on transistor MN 2 . The voltage level applied to the gate terminal of the access transistors MN 2  and MP 2  can differ for read and write access.  
         [0000]     Bit Storage  
         [0033]     The cell  200  operates asymmetrically holding a logic one and a logic zero when is not accessed. In the present embodiment, the cell is considered to hold a logic one if the voltage at node A is higher than the voltage at node B. The cell is considered to hold a logic zero if the voltage at node B is higher than the voltage at node A.  
         [0034]     In order for the cell  200  to hold the logic zero, drive transistors MP 1  and MN 1  should be on. When MN 1  and MP 1  are on, they construct a positive feedback loop. This loop improves the stability of the cell  200  such that it can hold the state under transistor threshold voltage fluctuation.  
         [0035]     The cell holds the logic one when both drive transistors MP 1  and MN 1  are off. Leakage currents through the access transistors MP 2  and MN 2  are sufficiently high to keep the internal nodes A and B close to the corresponding pre-charged bit-line voltages. In this case, since the access transistors MP 2  and MN 2  dominate the internal node voltages of nodes A and B, the voltage appearing at these two nodes will be close to the high voltage VBL H  of bit-line BL and the low voltage VBL L  of  BL , respectively. Since VBL H  is kept higher than VBL L  the cell  200  holds a logic one.  
         [0000]     Cell Access  
         [0036]     In order for access transistor MP 2  to turn on, the voltage on word-line WLA has to drop to a sufficiently low voltage. In the present example, this voltage is VBL H −Vth P2  or lower, where Vth P2  is the threshold voltage of access transistor MP 2 .  
         [0037]     In order for access transistor MN 2  to turn on, the voltage on word-line WLA has to rise to a sufficiently high voltage. In the present example, this voltage is VBL H +Vth N2  or higher, where Vth N2  is the threshold voltage of access transistor MN 2 .  
         [0038]     When the cell  200  is to be access for either a read or write operation, the access transistors MP 2  and MN 2  are activated by the word-lines WLA and WLB, as described above.  
         [0000]     Read Operation  
         [0039]     If the cell  200  is accessed for read operation, the bit-lines BL and  BL  may be affected, depending on the logic value stored in the cell.  
         [0040]     If, for example, the cell  200  stores a logic zero, node A is at a lower voltage than node B. Both drive transistors MP 1  and MN 1  force the corresponding bit-line voltages towards the voltage at their source terminals. That is, dive transistor MP 1  sources the current towards bit-line  BL  and MN 1  sinks current from bit-line BL. A current or voltage mode sense amplifier can be used to detect current flow on the bit-line pair BL and  BL .  
         [0041]     Referring to  FIG. 3 , a waveform plot of a sample read operation for a cell  200  storing a logic zero is shown.  FIG. 3   a  illustrates the current of the drive transistor MN 1 .  FIG. 3   b  illustrates the voltage at nodes A and B.  FIG. 3   c  illustrates the voltage at word-line WLA.  FIG. 3   d  illustrates the voltage at word line WLB.  
         [0042]     At a given time, the cell is accessed by reducing the voltage on word-line WLA and increasing the voltage of word-line WLB. As illustrated in  FIG. 3   a,  the current driven through the drive transistor MN 1  onto bit-line  BL  increases. Further, as shown in  FIG. 3   b,  the cell  200  maintains the proper voltages at each of nodes A and B for the duration of the read operation.  
         [0043]     If, for example the cell  200  stores a logic one, node A is at a higher voltage than node B. Both drive transistors MP 1  and MN 1  are off. Accordingly, when the cell  200  is accessed for a read operation there is no current passing through the drive transistors MP 1  and MN 1 . Therefore, the corresponding bit-lines BL and  BL  do not experience a current flow from the cell  200 . A current or voltage mode sense amplifier can be used to detect the lack of current flow on the bit-line pair BL and  BL .  
         [0044]     Referring to  FIG. 4 , a waveform plot of a sample read operation for a cell  200  storing a logic zero is shown.  FIG. 4   a  illustrates the voltage at nodes A and B.  FIG. 4   b  illustrates the voltage at word-line WLA.  FIG. 4   c  illustrates the voltage at word line WLB.  
         [0045]     At a given time, the cell is accessed by reducing the voltage on word-line WLA and increasing the voltage of word-line WLB. As shown in  FIG. 4   a,  the cell  200  maintains the proper voltages at each of nodes A and B for the duration of the read operation.  
         [0046]     Accordingly, it can be seen that accessing a cell  200  that stores a logic one reinforces the same logical value on the cell  200 . In contrast, accessing a cell  200  that stores a logic zero drives current onto the bit-line pair BL and  BL . However, the internal loop prevents the logic value of the cell  200  from being flipped.  
         [0047]     In an alternate embodiment, rather than use both word-lines WLA and WLB to activate both access transistors MP 2  and MN 2 , only one of the access transistors MP 2  and MN 2  is activated. Experimental evidence indicates that activating only one of the access transistors MP 2  and MN 2  improves the stability of the cell  200  and further reduces the likelihood that the logic value of the cell  200  will flip during a read operation.  
         [0000]     Write Operation  
         [0048]     The following describes a write operation to the cell  200 . If the logic value being written to the cell  200  is the same as the logic value already stored therein, little happens. Accordingly, the write operation will be will described for a cell  200  that stores an opposite value of the logic value to be written.  
         [0049]     If, for example, the cell  200  stores a logic one and a logic zero is to be written to the cell  200 , the write operation is described as follows. The state of the cell  200  can be flipped to a logic zero if the voltage applied to the bit-line BL is sufficiently below the high voltage supply V H  of the cell  200  the voltage applied to the bit line  BL  is sufficiently above the low voltage supply V L  of the cell  200  before the cell  200  is accessed. A sample voltage sufficiently below V H  is V H −Vth P , where Vth P  is the absolute value of the threshold voltage for drive transistor MP 1 . A sample voltage sufficiently above V L  is V L +Vth N , where Vth N  is the absolute value of the threshold voltage for drive transistor MN 1 .  
         [0050]     Referring to  FIG. 5 , a waveform plot of a sample logic zero write operation for a cell  200  storing a logic one is shown.  FIG. 5   a  illustrates the voltage at nodes A and B.  FIG. 5   b  illustrates the voltage at word-line WLA.  FIG. 5   c  illustrates the voltage at word line WLB. Once the bit-lines have been sufficiently pre-charged to the voltages, as described above, the cell  200  is accessed by decreasing the voltage on word-line WLA and increasing the voltage on word-line WLB.  
         [0051]     In the present example, the voltage applied to the word-lines WLA and WLB is the same voltage that is applied for a read operation. The voltage on bit-line BL is sufficiently low to turn on drive transistor MP 1 . Similarly, the voltage on bit-line  BL  is sufficiently high to turn on drive transistor MN 1 . Therefore, the voltage at node A is driven to low voltage V L  by drive transistor MN 1  and the voltage at node B is drive to high voltage V H  by drive transistor MP 1 . The logic zero is maintained by the internal loop of the cell  200 .  
         [0052]     If, for example, the cell  200  stores a logic zero and a logic one is to be written to the cell  200 , the write operation is described as follows. The state of the cell  200  can be flipped to a logic one if the voltage applied to the bit-lines BL and  BL  overcomes the drive of the drive transistors MP 1  and MN 1  and turns them off. This operation can be accomplished in a number of ways.  
         [0053]     One way to accomplish this operation is to increase the overdrive voltage of the access transistors MN 2  and MP 2  such that the charge introduced into the loop from the bit lines BL and  BL  when they are activated turns off the drive transistors MN 1  and MP 1 . Since the high voltage supply V H  and the low voltage supply V L  can differ from high bit-line voltage VBL H  and the low bit line voltage VBL L , a negative gate source voltage can be generated over the drive transistors MN 1  and MP 1 .  
         [0054]     Referring to  FIG. 6 , a waveform plot of a sample logic one write operation for a cell  200  storing a logic zero is shown.  FIG. 6   a  illustrates the voltage at nodes A and B.  FIG. 6   b  illustrates the voltage at word-line WLA.  FIG. 6   c  illustrates the voltage at word line WLB. Once the bit-lines have been sufficiently pre-charged to their nominal pre-charge voltages the cell  200  is accessed by decreasing the voltage on word-line WLA and increasing the voltage on word-line WLB.  
         [0055]     In the present example, the voltage applied to the word-lines WLA and WLB is the same voltage that is applied for a read operation. The voltage on bit-line BL is sufficiently high to turn off drive transistor MP 1 . Similarly, the voltage on bit-line  BL  is sufficiently low to turn off drive transistor MN 1 . Therefore, the voltage at node A is maintained at a high voltage VBL H  by virtue of the access transistor MP 2  being turned on. Similarly, the voltage at node B is maintained at a high voltage VBL L  by virtue of the access transistor MN 2  being turned on. Once the access transistors MN 2  and MP 2  are turned off, the voltages at nodes A and B are maintained by the leakage current through the access transistors MN 2  and MP 2  as described with reference to storing a logical one in a cell  200 .  
         [0056]     Referring to  FIG. 7 , a block diagram illustrating a column of cells  200  is shown generally by numeral  700 . The column  700  illustrates an example how a plurality of the cells  200  can be organized. The bit-lines are shared among the cells  200  located on the column  700 . Therefore, read and write operations are carried out by enabling the word-line voltages for a given cell  200  and by pre-charging the bit-line voltages appropriately. The arrangement of the column is similar to a that for standard SRAM cells, as will be appreciated by a person skilled in the art.  
         [0057]     Referring to  FIG. 8 , a block diagram illustrating an array of cells  200  in columns  700  is shown generally by numeral  800 . Referring to  FIG. 9 , a plurality of the arrays  800  can be organized in a complete SRAM unit. The column, array and SRAM unit configuration may include a number of different conventional configurations as well as proprietary configurations modified as necessary to work with the cell  200 , as will be appreciated by a person of ordinary skill in the art.  
         [0058]     Although the invention has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art without departing from the scope of the invention as defined by the appended claims.