Abstract:
A nonvolatile memory includes a substrate, stacked gate structures, spacers, control gates, a composite dielectric layer and source region/drain regions. Each of stack gate structures is formed on the substrate and is consisted of a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stack gate structure. The composite dielectric layer including a bottom dielectric layer, a charge trapping layer and upper dielectric layer is formed on the substrate. The control gates, which filled in the spaces between the stacked gate structures, are disposed on the composite dielectric layer and connected to each other. The source region/drain region is configured in the substrate near the outer two stacked gate structures.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This application claims the priority benefit of Taiwan applications serial no. 93113274, filed on May 12, 2004, and serial no.  94100956 , filed on Jan. 13, 2005. This application is a continuation-in-part of a prior application Ser. No. 10/904,478, filed Nov. 12, 2004. All disclosures are incorporated herewith. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory (NVM), a non-volatile memory array and a manufacturing method thereof.  
         [0004]     2. Description of Related Art  
         [0005]     Electrically erasable programmable read only memory (EEPROM) is a type of non-volatile memory that allows multiple data reading, writing and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, electrically erasable programmable read only memories have been broadly applied in personal computers and electronic equipment.  
         [0006]     A typical flash memory device has a floating gate and a control gate fabricated with doped polysilicon. During an erasing operation by a typical EEPROM device, a critical over-erasure often occurs, leading to a misinterpretation of the data. To prevent such an event from occurring, a select gate is designed on the sidewalls of the control gate and the floating gate and the substrate to form a split gate structure.  
         [0007]     Currently, the industry provides a fabrication method for a split-gate memory cell of the AG-AND type of memory array structure as described in U.S. Pat. No. 6,567,315.  FIG. 1  is a schematic cross-sectional view of a portion of a conventional AG-AND type of memory cell structure.  
         [0008]     Referring to  FIG. 1 , an AG-AND type of memory cell structure includes a substrate  100 , a well region  102 , and an auxiliary gate transistor Qa 1  (Qa 2 ), a memory device Qm 1  (Qm 2 ), and source/drain regions  104   a,    104   b  ( 104   c ) that are disposed in the substrate  100  besides the two sides of the auxiliary gate transistor Qa 1  (Qa 2 ) and the memory device Qm 1  (Qm 2 ). The auxiliary gate transistor Qa 1  (Qa 2 ) includes an auxiliary gate  106   a  ( 106   b ). The memory device Qm 1  (Qm 2 ) includes a floating gate  108   a  ( 108   b ) and a word line  110 , wherein the word line  110  serves as a control gate of the memory device Qm 1  (Qm 2 ). The auxiliary gate transistor Qa 1  (Qa 2 ) and the memory device Qm 1  (Qm 2 ) constitute a memory cell Q 1  (Q 2 ). Further, the neighboring memory cells along a same row in the AG-AND array share a common source/drain region.  
         [0009]     In the above AG-AND type of memory cell structure, when a memory cell Q 1  is performing the programming operation, a bias voltage of 13 volts is applied to the word line, a bias voltage of 1 volt is applied to the auxiliary gate  106   a,  a bias voltage of 0 volt is applied to the source/drain region  104   a,  and a bias voltage of 5 volts is applied to the source/drain region  104   b  for electrons to be injected into the floating gate  108   a  of the memory device Qm 1  to program the memory cell Q 1 . Since no voltage is applied to the auxiliary gate  106   b,  the memory cell Q 2  is not programmed.  
         [0010]     However, in the above AG-AND type of memory cell structure, the source/drain regions ( 104   a,    104   b  or  104   c ) are formed in the substrate  100  beside the two sides of the memory cell Q 1  (Q 2 ). To prevent the source/drain regions ( 104   a,    104   b  or  104   c ) from being too close and the channel underneath the memory cell from being conductive, the source/drain regions need to be parted at a certain distance. Accordingly, the dimension of the memory cell can not be further reduced.  
       SUMMARY OF THE INVENTION  
       [0011]     The present invention provides a non-volatile memory device and a non-volatile memory array and a fabrication method thereof. No only the fabrication of the non-volatile memory array is simple, this type of non-volatile memory device can also apply source-side injection (SSI) to perform the programming operating in order to increase the programming speed and to improve efficiency of the memory cell.  
         [0012]     The present invention also provides a non-volatile memory, a non-volatile memory array and a fabrication method thereof, wherein the operation voltage of the memory can increase to raise the efficiency of the device.  
         [0013]     The present invention further provides a non-volatile memory, a non-volatile memory array and a fabrication method thereof, wherein the memory cell device can be reduced to increase the integration of the device.  
         [0014]     The present invention provides a non-volatile memory. The non-volatile memory includes a first row of memory cells, a first source/drain region and a second source/drain region. The first row of memory cells includes a plurality of stacked gate structures, a spacer, a plurality of control gates, a composite dielectric layer. The plurality of stacked gate structures is disposed on the substrate, wherein each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer, sequentially formed from the substrate. The spacer is disposed on the sidewall of the stacked gate structure. The composite dielectric layer is disposed on the substrate, wherein the composite dielectric layer includes a bottom dielectric layer, a charge trapping layer and a top dielectric layer. A control gate line is disposed above the composite dielectric layer, filling the gaps between every two stacked gate structures. The first source/drain region and the second source/drain region are respectively disposed in the substrate beside the two sides of the first row of memory cells. The above non-volatile memory further includes a second row of memory cells and a third second source/drain region and a third source/drain region disposed on the substrate. The second row of memory cells and the first row of memory cells have similar structures. The second source/drain region and the third source/drain region are disposed in the substrate respectively besides two sides of the second row of memory cells, wherein the first row of memory cells and the second row memory cells share the second source/drain region.  
         [0015]     In the structure of the non-volatile memory of the present invention, no isolation structure and no contact are formed between each row of the memory cells. The integration of the memory cell array can thereby increase.  
         [0016]     The present invention also provides a non-volatile memory cell array. The memory cell array includes a substrate, a plurality of rows of memory cells, a plurality of control gate lines, a plurality of select gate lines, a plurality of source lines and a plurality of drain lines. The plurality of rows of memory cells is arranged into a memory array, wherein the memory array includes a plurality of stacked gate structures disposed on the substrate. Each stacked gate structure includes, sequentially from the substrate, a select gate dielectric layer, a select gate and a cap layer. A spacer is disposed on the sidewall of the stacked gate structure, and the composite dielectric layer is disposed on the substrate. The composite dielectric layer includes a bottom dielectric layer, a charge trapping layer and a top dielectric layer. A plurality of control gates is disposed above the composite dielectric layer between every two stacked gate structures. The source/drain regions are disposed in the substrate respectively beside one side of the two outer stacked gate structures. The plurality of the control gate lines connects the control gates of a same row of the memory cells. A plurality of select gate lines connects the select gates of a same column of the memory cells. A plurality of source lines connects the source regions along a same column, while a plurality of drain lines connects the drain regions along a same column.  
         [0017]     The above-mentioned non-volatile memory array can be divided into at least a first memory block and a second memory block. The drain regions of different rows of memory cells in the first memory block are connected through the first drain line, and the drain regions of different rows of memory cells in the second memory block are connected through the second drain line. Further, the first memory block and the second memory block share a source line.  
         [0018]     The above-mentioned memory array can apply the source-side injection to inject electrons into the charge trapping layer of a selected memory cell to program the selected memory cell. Further, the above-mentioned memory array can also apply the channel F-N tunneling to eject electrons from the charge trapping layer of the memory cell to the substrate to erase all information from the entire memory cell array.  
         [0019]     In the non-volatile memory cell array of the present invention, there is no gap presents in between the memory cell structures. The integration of the memory cell array can thereby increased.  
         [0020]     The present invention provides a fabrication method for a non-volatile memory, wherein a substrate is first provided and a plurality of stacked gate structures is already formed over the substrate. Each of the stacked gate structures includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are subsequently formed in the substrate. The source region and the drain region are separated by at least two stacked gate structures. A composite dielectric layer is formed over the substrate, followed by forming a conductive layer over the substrate. The conductive layer is further patterned to form a plurality of connecting control gates that fill the gaps between the stacked gate structures.  
         [0021]     During the fabrication method of a non-volatile memory of the present invention, a charge trapping layer (silicon nitride) is used as a charge storage unit. Accordingly, the operating voltage required by an operation can be reduced and the operating speed and efficiency of the memory cell can be improved.  
         [0022]     Moreover, using the charge trapping layer (silicon nitride) as a charge storage unit, the process for defining a floating gate when a floating gate is used as a charge storage unit can be omitted. Ultimately, not only the fabrication process is simpler, the integration of the memory array is increased.  
         [0023]     Further, no device isolation structure is formed between each row of the memory cells. Therefore, the process is simpler and the integration of the memory array is enhanced.  
         [0024]     It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.  
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0025]     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.  
         [0026]      FIG. 1  is a schematic, cross-sectional view of a portion of a conventional AG-AND type of memory cell structure.  
         [0027]      FIG. 2A  is a schematic top view of a non-volatile memory array of the present invention.  
         [0028]      FIG. 2B  is a schematic, cross-sectional view of  FIG. 2A  along the cutting line A-A′.  
         [0029]      FIG. 3A through 3D  are schematic cross-sectional views showing the steps for fabricating a non-volatile memory according to an embodiment of the present invention.  
         [0030]      FIG. 4  is a simplified circuit diagram of the non-volatile memory of the present invention. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0031]     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.  
         [0032]      FIG. 2  is a schematic top view of a non-volatile memory array of the present invention.  FIG. 2B  is a schematic, cross-sectional view of  FIG. 2A  along the cutting line A-A′. As shown in  FIGS. 2A and 2B , the memory cell array can be divided into memory block  200   a  and memory block  200   b,  wherein the memory block region  200   a  and the memory block region  200   b  share a source region  220  (source line S). The following disclosure is directed to only memory block  200   a.    
         [0033]     Referring to  FIG. 2A , the non-volatile memory array of the invention includes a substrate  200 , a plurality of rows of memory cells QL 1  to QL 4 , a plurality of control gate lines CG 1  to CG 4 , a plurality of select gate lines SG 1  to SG 5 , a source line S and a drain line D.  
         [0034]     The rows of memory cells QL 1  to QL 4  are arranged in a memory array. Each of the control gate lines CG 1  to CG 4  connects the control gates of the memory cells of a same row. The select gates along a same column of the memory cells are respectively connected by the select gate lines SG 1  to SG 5 . The source line S connects the source regions of a same column of the memory cells and the drain line connects the drain regions of a same column of the memory cells.  
         [0035]     The structure of the non-volatile memory cell array of the present invention is illustrated herein with the row of the memory cells QL 1 .  
         [0036]     Referring concurrently to  FIGS. 2A and 2B , the non-volatile memory structure of the present invention is at least formed with a substrate  200 , a plurality of stacked gate structures  202   a  to  202   e  (each of the stacked gate structures  202   a  to  202   e  includes, sequentially from the substrate  200 , a select gate dielectric layer  204 , a select gate  206 , a cap layer  208 ), a spacer  210 , a composite dielectric layer  212  (the composite dielectric layer  212  includes, sequentially from the substrate  200 , a bottom dielectric layer  212   a,  a charge trapping layer  212   b  and a top dielectric layer  212   c ), a plurality of control gates  214   a  to  214   d,  source regions  216 , and drain regions  218 .  
         [0037]     The substrate  200  is, for example, a silicon substrate. The plurality of stacked gate structures  202   a  to  202   e  are disposed on the substrate  200 , wherein the stacked gate structures  202   a  to  202   e  display, for example, a strip pattern. The thickness of the stacked gate structures  202   a  to  202   e  is about 2000 angstroms to 3500 angstroms. The material of the select gate dielectric layer  204  includes silicon oxide, for example, and the select gate dielectric layer  204  is about 160 angstroms to about 170 angstroms thick. The select gate  206 , which is about 600 angstroms to about 1500 angstroms thick, is formed with, for example, doped polysilicon. The material of the cap layer  208  includes silicon oxide, and the cap layer  208  is about 1000 angstroms to about 1500 angstroms thick. The spacer  210  is disposed on the sidewall of each stacked gate structure  202   a  to  202   e,  wherein the material of the spacer  210  includes but not limited to silicon oxide or silicon nitride.  
         [0038]     The composite dielectric layer  212  is disposed on the substrate  200 . The composite dielectric layer  212  is formed with, sequentially from the substrate  200 , a bottom dielectric layer  212   a,  a charge trapping layer  212   b  and a top dielectric layer  212   c.  The material of the bottom dielectric layer  212   a  includes silicon oxide, for example. Further, the bottom dielectric layer  212   a  is about 20 angstroms to about 60 angstroms thick. The charge trapping layer  212   b  is about 30 angstroms to about 70 thick, and is formed with silicon nitride, for example. The material of the top dielectric layer  212   c  is silicon oxide, for example, and the thickness of the top dielectric layer is about 30 angstroms to about 60 angstroms. The material of the charge trapping layer  212  can also be any other materials that have the charge trapping function.  
         [0039]     The plurality of control gates  214   a  to  214   d  are disposed on the composite dielectric layer  212 , filling the gaps between the stacked gate structures  202   a  to  202   e.  Further, the control gates  214   a  to  214   d  are connected together by the control gate line  214 . The plurality of the control gates  214   a  to  214   d  and the control gate line  214  are integrated together, for example. In other words, the plurality of the control gates  214   a  to  214   d  extends to above the stacked gate structures  202   a  to  202   e  and are connected to the stacked gate structure to form the control gate line  214 . The control gate line  214  is substantially perpendicular to the stacked gate structures  202   a  to  202   e,  for example. The material of the control gates is doped polysilicon, for example.  
         [0040]     The plurality of stacked gate structures  214   a  to  214   d,  the spacer  210 , the composite dielectric layer  212 , the plurality of control gates  214   a  to  214   d  constitute a row of the memory cells  220 . The source region  218 /drain region  216  are respectively disposed in the substrate  200  beside both sides of the row of the memory cells  220 . For example, the drain region  216  is disposed in the substrate  200  beside one side of the stacked gate structure  202   a  of the row of the memory cells  220 , while the source region  218  is disposed in the substrate  200  beside one side of the stacked gate structure  202   e  of the row of the memory cells  220 . In other words, the drain region  216  and the source region  218  are disposed in the substrate  200  respectively beside the sides of the two outer stacked gate structures  202   a,    202   e.    
         [0041]     In the structure of the above row of memory cells, each of the control gates  214   a  to  214   d  and the composite dielectric layer  212  form the memory cell structure  222   a  to  222   d,  respectively, and each of the stacked gate structures  202   a  to  202   d  form the memory cell structure  222   a  to  222   d,  respectively. The stacked gate structure  202  disposed closest to the source region  218  serves as a switch transistor, for example. Since there is not gap in between the memory cell structures  222   a  to  222   d  and the stacked gate structures  202   e,  the level of integration of memory cells can be increased. Further, the conductive layer  214   f  and the conductive layer  214   e  above the source region and the drain region are not used as control gates. The composite dielectric layer  212  disposed above the source region  216  and the drain region  218  can insulate the conductive layer  214   f  from the drain region  218 , and the conductive layer  214   e  from the source region  216 , respectively.  
         [0042]     In the above row of memory cells, a charge trapping layer (silicon nitride) is used as a charge storing unit. The required operating voltage for an operation can be lower to enhance the operating speed and efficiency of the memory cell.  
         [0043]     Although the above-mentioned embodiments refer to four memory cell structures  222   a  to  222   d  connecting together, it is to be understood that these embodiments are presented by way of example and not by way of limitation. In other words, the number of memory cell structures connecting together depends on the actual demand. For example, one common control gate line can connect 32 to 64 memory cell structures.  
         [0044]     As shown in  FIG. 2A , in the entire memory array, no isolation structure and no contact are formed between each row of the memory cells. The level of integration of the memory array can be increased.  
         [0045]     A method for fabrication a memory array according to the present invention is disclosed herein.  FIGS. 3A  to  3 E are schematic diagram along the cutting line A-A′ of  FIG. 2A  showing the steps for fabricating a non-volatile memory according to an embodiment of the present invention.  
         [0046]     Referring to  FIG. 3A , a substrate  300  is provided. The substrate  300  is a silicon substrate, for example. A dielectric layer  302 , a conductive layer  304  and a cap layer  306  are sequentially formed on the substrate  300  to form a plurality of stacked gate structures  308 . Forming the stacked gate structures  308  include sequentially forming a dielectric layer a conductive layer and a cap layer over the substrate  300 , followed by performing a photolithography and etching process. The material of the dielectric layer includes silicon oxide, for example, and is formed by thermal oxidation. The material of the conductive layer includes doped polysilicon. The conductive layer is formed by forming an undoped polysilicon layer with chemical vapor deposition, followed by performing an ion implantation process. The cap layer is formed with silicon oxide, for example, by reacting tetraethyl orthosilicate (TEOS)/ozone (O3) in a chemical vapor deposition process. The conductive layer  304  serves as a select gate, while the dielectric layer  302  serve as a select gate dielectric layer.  
         [0047]     Referring to  FIG. 3B , a spacer  310  is formed on the sidewall of each stacked gate structure  308 . The material of the spacer  310  includes silicon oxide or silicon nitride. The spacer  310  is formed by forming an insulation material layer on the substrate  300 , followed by performing an anisotropic etching process. A mask layer  312  is then formed over the substrate  300 . The mask layer  312  has an opening  314  exposing the part of the substrate  300  predetermined for forming the source region  316  and the drain region  318 . The material of the mask layer is a photoresist material, for example. Further using the mask layer  312  as a mask, the source region  316  and the drain region  318  are formed in the substrate  300 . The source region  316  and the drain region  318  are formed by ion implantation, for example. The source region  316  and the drain region  318  are separated by at least two stacked gate structures  308 .  
         [0048]     Referring to  FIG. 3C , after removing the mask layer  312 , a composite dielectric layer  320  is formed over the substrate  300 . The composite dielectric layer  320  is formed with, from bottom to top, a bottom dielectric layer  320   a,  a charge trapping layer  320   b  and a top dielectric layer  320   c.  The bottom dielectric layer  320   a  is formed with silicon oxide, for example, while the charge trapping layer  320   b  is formed with a material includes but not limited to silicon nitride. The material of the top dielectric layer  320   c  includes silicon oxide, for example. The composite dielectric layer  320  is formed by, for example, performing chemical vapor deposition to sequentially form the bottom dielectric layer  320   a,  the charge trapping layer  320   b  and the top dielectric layer  320   c.  the other hand, the composite dielectric layer  320  can also form by performing thermal oxidation to form the bottom dielectric layer  320   a,  followed by performing chemical vapor deposition to form the charge trapping layer  320   b  and the top dielectric layer  320   c.  If thermal oxidation is used to form the bottom dielectric layer  320   a,  the bottom dielectric layer  320   a  formed on the surface of the source region  316  and the drain region  318  is thicker than the bottom dielectric layer  320   a  formed at other region. This is due to the fact that the source region  316  and the drain region  318  are doped with dopants and their oxidation rate is faster than other regions not doped with dopants. Accordingly, the bottom dielectric layer  320   a  at the source region  316  and the drain region  318  are thicker.  
         [0049]     Continuing to  FIG. 3D , a conductive layer (not shown) is formed on the substrate  300 , and the conductive layer fills the gaps between the stacked gate structures  308 . The conductive layer is formed by forming a conductive material layer on the substrate  300 , followed by using chemical mechanical polishing or back etching to planarize the conductive material layer. The conductive material layer is a doped polysilicon layer, for example, and is formed by performing chemical vapor deposition to form a layer of undoped polysilicon layer, followed by performing an ion implantation process. Thereafter, the conductive layer is patterned to form a control gate line  322  (word line), wherein the control gate line  322  (word line) fills the gap between the stacked gate structures  308 . Beside the control gate line positioned above the source region  316  and the drain region  318 , the control gate line  322  positioned in the gap between two neighboring stacked gate structures serves as a control gate  330   a.  In other words, the control gate  330   a  extends to the surface of the stacked gate structure  308  to connect with the stacked gate structure  308 . The subsequent fabrication process of a memory array is well known to those skilled in the art; therefore, the detail thereof will not be reiterated herein.  
         [0050]     In the above row of memory cells, the charge trapping layer (silicon nitride) serves as the charge storing unit. The operating voltage required for an operation can be lower to increase the operating speed and efficiency of the memory cell.  
         [0051]     Comparing the process in which a charge trapping layer (silicon nitride) is formed as a charge storing unit with the process in which a floating gate (doped polysilicon) is formed as a charge storing unit, the step for defining the floating gate can be reduced. Accordingly, the process of the invention is simpler and the level of integration is improved.  
         [0052]     Although the above-mentioned embodiments refer to four memory cell structures  222   a  to  222   d  connecting together, it is to be understood that these embodiments are presented by way of example and not by way of limitation. In other words, the number of memory cell structures connecting together depends on the actual demand. For example, one common control gate line can connect 32 to 64 memory cell structures.  
         [0053]      FIG. 4  is a simplified circuit diagram of the memory array of the present invention.  FIG. 4  is divided into memory block BLOCK 1  and memory block BLOCK 2 . The memory block BLOCK 1  is used herein to illustrate the operation of the memory array of the present invention; and as an example, the memory block BLOCK 1  has 16 memory cells.  
         [0054]     Referring to  FIG. 4 , the rows of memory cells includes 16 memory cells Q 11  Q 44 , (LOCOS), switch transistors T 1  to T 4 , select gate lines SG 1  to SG 5 , control gate lines CG 1  to CG 4 , a source line D and a drain line D.  
         [0055]     Each of the memory cells Q 11  to Q 44  includes a select gate, a control gate and a charge trapping layer.  
         [0056]     The source line S and the drain line D extend along the direction of the column of the array. Each row of the memory cells includes four memory cells and a switch transistor connected together. For example, the memory cells Q 11  to Q 14  and the switch transistor T 1  are connected together; the memory cells Q 21  to Q 24  and the switch transistor T 2  are connected together; the memory cells Q 31  to Q 34  and the switch transistor T 3  are connected together; the memory cells Q 41  to Q 44  and the switch transistor T 4  are connected together.  
         [0057]     Each of the control gate lines CG 1  to CG 4  connects the control gates along the same row of the memory cells. For example, the control gate line CG 1  connects the control gates of the memory cells Q 11  to Q 14 ; the control gate line CG 2  connects the control gates of the memory cells Q 21  to Q 24 ; the control gate line CG 3  connects the control gates of the memory cells Q 31  to Q 34 ; the control gate line CG 4  connects the control gates of the memory cells Q 41  to Q 44 .  
         [0058]     Each of the select gate lines SG 1  to SG 4  connects the select gates along the same column of the memory cells. For example, the select gate line SG 1  connects the select gates of the memory cells Q 11  to Q 41 ; the select gate line SG 2  connects the select gates of the memory cells Q 12  to Q 44 ; the select gate line SG 3  connects the select gates of the memory cells Q 13  to Q 43 ; the select gate line SG 1  connects the select gates of the memory cells Q 14  to Q 44 ; the select gate line SG 5  connects the gates of the switch transistors T 1  to T 4  along a same column.  
         [0059]     Although the disclosure hereafter refers to certain embodiments for illustrating the operating method of the non-volatile memory of the present invention, it is to be understood that these embodiments are presented by way of example and not by way of limitation.  
         [0060]     Memory cell Qn 2  is used herein to illustrate the programming operation of the invention. A bias voltage of 5 volts is applied to the source lines. A bias voltage of 1.5 volts is applied to the selected select gate line SG 2 , while a bias voltage of about 8 volts is applied to the non-selected select gate lines SG 1 , SG 3 , SG 4 . A bias voltage of about 8 volts is applied to the select gate line SG 5 . A bias voltage of about 7 volts is applied to the selected control gate line CG 1 , while a bias voltage of about 0 to 2 volts is applied to the non-selected control gate lines CG 2 , CG 3 , CG 4 . The substrate and the drain line are grounded. Source-side injection (SSI) is used to inject electrons into the charge trapping layer of the memory cell to program the memory cell Qn 2 .  
         [0061]     During a reading operation, a bias voltage of about 0 volt is applied to the source line; a bias voltage of about 4.5 volts is applied to the select gate lines SG 1  to SG 5 , respectively; a bias voltage of about 3 volts is applied to the control gate line CG 1 ; and a bias voltage of 2 volts is applied to the drain line. Since the channel of the memory cell is closed and the current is small when the total amount of charges in the charge trapping layer is negative, and the channel is opened and the current is large when the total amount of charges in the charge trapping layer is slightly positive, the opening or closing/large or small current flow at the channel can be used to determine the digital information stored in the memory cell is “1” or “0”.  
         [0062]     During the erasing operation, a bias voltage of about −20 volts is applied to the control gate line CG 1  and a bias voltage of about 0 volt is applied to the substrate. The channel F-N tunneling is used to pull the electrons from the charge trapping layer of the memory cell to erase the information in the memory cell.  
         [0063]     The operation of the memory array includes using the hot carrier effect to program a single memory cell with a single bit as a unit, and the channel F-N tunneling to erase the entire array of the memory cells. Accordingly, the electron injection rate is higher to lower the current flow of the memory cell during an operation. Further, the operating rate is concurrently increased. Therefore, the current consumption is small to effectively lower the power consumption of the entire wafer.  
         [0064]     Further, in the above memory array, the charge trapping layer (silicon nitride) is used as a charge storing unit. The operating voltage required for an operation can thereby lowered and the operating speed and efficiency of the memory cell are improved.  
         [0065]     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.