Abstract:
An embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance.

Description:
BACKGROUND 
     Technical Field 
     The present invention relates generally to data communication links. More particularly, the present invention relates to phase detection in a clock-data recovery circuit with decision feedback equalization. 
     Description of the Background Art 
     High-speed serial interfaces may be used to communicate data between devices in a system. Such serial interfaces may provide a high data bandwidth across backplanes or between chip devices. 
     However, challenges and problems are faced due to the high-speed signaling that may be used by these serial interfaces. One challenge relates to obtaining sufficient timing error information for timing recovery in a high-speed transceiver with speculative decision feedback equalization (DFE). 
     SUMMARY 
     One embodiment of the invention relates to a method of phase detection in a receiver circuit with decision feedback equalization. Partial-equalization and full-equalization edge signals are generated. The feedback from the first tap of the decision feedback equalizer is separated from the feedback of the remaining plurality of taps. The feedback from the plurality of taps (not including the first tap) is used to generate partial-equalization edge signals, while the feedback from all the taps is used to generate full-equalization edge signals. The partial-equalization and full-equalization edge signals are utilized by phase-detection circuitry to provide highly-accurate data sampling locations for improved performance. 
     Other embodiments, aspects and features are also disclosed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a high-level block diagram of an exemplary receiver circuit with speculative DFE in accordance with an embodiment of the invention. 
         FIG. 2  shows exemplary circuitry for recovering data signals and generating edge signals in accordance with an embodiment of the invention. 
         FIG. 3  shows exemplary circuit structure that uses the data and edge signals for phase detection for use in the clock data recovery (CDR) circuit in accordance with an embodiment of the invention. 
         FIG. 4  is an example timing diagram depicting the three data signals and the two edge signals input to each phase-detector (PD) logic module in accordance with an embodiment of the invention. 
         FIGS. 5A and 5B  provide truth tables for each of the two phase-detector (PD) logic modules in accordance with an embodiment of the invention. 
         FIG. 6A  depicts an eye diagram and data sampling locations using a receiver circuit with speculative DFE and conventional phase detection. 
         FIG. 6B  depicts an eye diagram and data sampling locations using a receiver circuit with speculative DFE and optimized phase detection in accordance with an embodiment of the invention. 
         FIG. 7  depicts a multi-tap feedback filter for decision feedback equalization in accordance with an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The present disclosure provides circuitry and methods for optimizing timing recovery performance in a high-speed transceiver with speculative decision feedback equalization. Data transmission reliability is substantially improved using the circuitry and methods disclosed herein. 
     Insufficient timing error information was used previously for timing recovery in a high-speed transceiver with speculative decision feedback equalization with an analog PLL based CDR. The use of such insufficient timing error information results in degradation of data transmission performance. This is because in an analog PLL based CDR, there are fewer options for adjusting the sampling location. 
     In accordance with an embodiment of the invention, timing error information in the signal is used from different zero-crossing locations to provide optimized data sampling positioning. Specific data pattern filtering is used for the timing error information processing. Decision multiplexing over a multiple symbol period is used to generate an appropriate signal for analog phase-locked loop (PLL) based clock-data recovery (CDR). 
     Advantageously, the circuits and methods disclosed herein substantially improve the performance of a high-speed transceiver with speculative DFE implemented. The data transmission reliability is improved due to better recovered signal quality and optimized data sampling positioning. 
       FIG. 1  is a high-level block diagram of an exemplary receiver circuit  100  with speculative DFE in accordance with an embodiment of the invention. The exemplary receiver circuit is on an integrated circuit device and receives a data signal over a serial link from a partner integrated circuit device. As depicted, the receiver circuit  100  includes a continuous-time linear equalizer (CTLE)  102 , a variable gain amplifier (VGA)  104 , a summation circuitry  106 , a clock-data recovery (CDR) loop circuit  108 , a deserializer (Deser) circuit  110 , and a decision feedback equalizer (DFE) circuit  112 . 
     The CTLE  102  is an analog equalizer circuit that receives an analog serial data signal (received data) transmitted over a serial link from a transmitter circuit of the partner device. The CTLE  102  performs continuous-time (i.e. analog) linear equalization on the analog serial data signal. 
     The VGA  104  amplifies the analog data signal output from the CTLE  102 . The output of the VGA  104  is summed with a feedback signal from the DFE circuit  112  by the summation circuitry  106  to generate an analog summation data signal, and the analog summation data signal from the summation circuitry  106  is provided to the CDR circuit  108 . 
     The CDR circuit  108  recovers a clock signal from the analog summation data signal and provides the recovered clock signal to sampler (slicer) circuitry within the CDR circuit  108 . The sampler circuitry samples the analog data signal (received data) in response to the recovered clock signal to obtain a digital data signal. 
     In accordance with an embodiment of the invention, a circuit structure within the CDR circuit  108  for phase detection and sampling is disclosed that effectively improves the accuracy of the data sampling locations. The disclosed circuit structure is described in detail below in relation to  FIGS. 2, 3 and 4 . 
     The deserializer circuit  110  receives and de-serializes the recovered (sampled) digital data signal from the CDR circuit  108  to obtain a parallel digital data signal. The parallel digital data signal may be provided to further circuitry in the integrated circuit for further processing and use. 
     The DFE circuit  112  also receives the recovered digital data signal output by the CDR circuit  108 . In further accordance with an embodiment of the invention, the DFE circuit  112  provides a first tap signal (H 1 ) to the CDR circuit  108  for use by the phase detection and sampling circuit structure and provides remaining tap signals (H 2 , H 3 , . . . ) as feedback to the summation node  106 . In one implementation, the remaining tap signals include the ten tap signals from taps  2  through  11  (i.e. H 2 , H 3 , H 4 , . . . , H 10 , H 11 ). 
       FIGS. 2 and 3  depict exemplary circuitry for providing optimized phase detection in a clock-data recovery (CDR) circuit  108  with speculative DFE in accordance with an embodiment of the invention.  FIG. 2  shows circuitry for recovering data signals and generating edge signals, and  FIG. 3  shows circuitry that uses the data and edge signals for phase detection for use in the CDR circuit. 
     Referring to  FIG. 2 , an analog data signal may be received from the VGA circuit  104  at positive polarity inputs of odd and even summer circuits (odd_summer and even_summer). These odd and even summer circuits correspond to the summation circuit  106  in  FIG. 1 . 
     As further shown in  FIG. 2 , DFE feedback signals for odd data from DFE taps H 2 , H 3 , etc. (dfe_fb_to_odd) are provided to a negative polarity input of the odd summer circuit. Similarly, DFE feedback signals for even data from DFE taps H 2 , H 3 , etc. (dfe_fb_to_even) are provided to a negative polarity input of the even summer circuit. In other words, the DFE feedback signals from DFE taps, other than the first DFE tap (H 1 ), are provided to negative polarity inputs of the odd and even summer circuits. The odd summer circuit subtracts the odd-data DFE feedback (for H 2 , H 3 , etc.) signals from the analog data signal so as to generate an odd-feedback partially-equalized data signal. The even summer circuit subtracts the even-data DFE feedback signals (for H 2 , H 3 , etc.) from the analog data signal so as to generate an even-feedback partially-equalized data signal. 
     Further shown in  FIG. 2  are six sampler circuits (slicer 0 , slicer 1 , slicer 2 , slicer 3 , slicer 4 , and slicer 5 ). These arrangement and operation of these six sampler circuits are described as follows. 
     A pair of data sampling circuits (slicer 2  and slicer 3 ) generate the even and odd data signals (d 0  and d 180 , respectively). The slicer 2  circuit subtracts the DFE feedback signal from the first DFE tap (H 1 ) from the odd-feedback partially-equalized data signal (output from odd_summer) to generate a resultant odd-feedback fully-equalized data signal. The resultant odd-feedback fully-equalized data signal is sampled by the slicer 2  circuit using the 0-degree recovered clock (cdr_clk_ 0 ) to obtain the even data signal (d 0 ). Similarly, the slicer 3  circuit subtracts the DFE feedback signal from the first DFE tap (H 1 ) from the even-feedback partially-equalized data signal (output from even_summer) to generate a resultant even-feedback fully-equalized data signal. The resultant even-feedback fully-equalized data signal is sampled by the slicer 3  circuit using the 180-degree recovered clock (cdr_clk_ 180 ) to obtain the odd data signal (d 180 ). Together, these even and odd data signals form the recovered signal that may be output from the CDR circuit  108  to the deserializer circuit  110  in  FIG. 1 . 
     A pair of partial-equalization edge-generating sampling circuits (slicer 0  and slicer 1 ) sample the odd-feedback partially-equalized and even-feedback partially-equalized signals (outputs from odd_summer and even_summer, respectively) to generate a pair of partial-equalization edge signals (edge_B 90  and edge_B 270 , respectively). The slicer 0  circuit samples the odd-feedback partially-equalized signal (output from odd_summer) using the recovered 90-degree clock signal (cdr_clk_ 90 ) to obtain a 90-degree partially-equalized edge signal (edge_B 90 ). Similarly, the slicer 1  circuit samples the even-feedback partially-equalized signal (output from even_summer) using the recovered 270-degree clock signal (cdr_clk_ 270 ) to obtain a 270-degree partially-equalized edge signal (edge_B 270 ). 
     A pair of full-equalization edge-generating sampling circuits (slicer 4  and slicer 5 ) generates a pair of full-equalization edge signals (edge_A 90  and edge_A 270 , respectively). The slicer 4  circuit subtracts the DFE feedback signal from the first DFE tap (H 1 ) from the odd-feedback partially-equalized data signal (output from odd_summer) to generate a resultant odd-feedback fully-equalized data signal. The resultant odd-feedback fully-equalized data signal is sampled by the slicer 4  circuit using the 90-degree recovered clock (cdr_clk_ 90 ) to obtain the 90-degree full-equalization edge signal (edge_A 90 ). Similarly, the slicer 5  circuit subtracts the DFE feedback signal from the first DFE tap (H 1 ) from the even-feedback partially-equalized data signal (output from even_summer) to generate a resultant even-feedback fully-equalized data signal. The resultant even-feedback fully-equalized data signal is sampled by the slicer 5  circuit using the 270-degree recovered clock (cdr_clk_ 270 ) to obtain the 270-degree full-equalization edge signal (edge_A 270 ). 
     Referring to  FIG. 3 , the output signals of  FIG. 2  correspond to the input signals in  FIG. 3  (label in  FIG. 2 →label in  FIG. 3 ) as follows: d 0 →d 0 ; d 180 →d 180 ; edge_A 90 →a 90 ; edge_A 270 →a 270 ; edge_B 90 →b 90 ; and edge_B 270 →b 270 . The circuit structures depicted in  FIG. 3  include: an edge selection circuit module; a 4T data module; two phase-detector (PD) logic modules; an output multiplexer (mux); a charge pump (CP) circuit; and a voltage-controlled oscillator (VCO). 
     The edge selection circuit module receives the data signals (d 0  and d 180 ) and the edge signals (a 90 , a 270 , b 90  and b 270 ). In an exemplary implementation, the edge selection circuit module may be in one of two modes, as controlled by the edge mode control signal. 
     When the edge mode control signal is logical one, then the edge selection control module outputs edge signals b 90  and b 270 . In other words, in this mode, the output X includes the two partial-equalization edge signals. In this mode, power used may be reduced by powering down unused samplers (slicer 4  and slicer  5  in  FIG. 2 ) at the cost of less accurate timing error information (and so reduced performance). Hence, this mode may be referred to as a low-power mode. 
     When the edge mode control signal is logical zero, then the edge selection control module outputs the two partial-equalization edge signals b 90  and b 270  or the two full-equalization edge signals a 90  and a 270 , depending on the values of the previous, current and next bits as indicated by data signals d 0  and d 180 . If the previous, current and next bits are, respectively, 1, 0, and 1, or if they are, respectively, 0, 1, and 0, then the output X includes the two partial-equalization edge signals b 90  and b 270 . On the other hand, if the previous, current and next bits are, respectively, 0, 0, and 1, or if they are, respectively, 1, 1, and 0, then the output X includes the two full-equalization signals a 90  and a 270 . In this mode, timing error information may be more accurate (resulting in improved performance) at the cost of increased power consumption due to the use of the additional samplers (slicer 4  and slicer  5  in  FIG. 2 ). Hence, this mode may be referred to as a high-performance mode. 
     The 4T data module receives data input signals (D) and edge input signals (X). The data input signals (D) include the even and odd data signals d 0  and d 180 , respectively. The edge input signals (X) are the signals output by the edge selection module and include either partial-equalization edge signals b 90  and b 270 , or full-equalization edge signals a 90  and a 270 , as described above. Every two clock cycles (i.e. every four bits of the data stream), the 4T data module loads four new data bits [d(k- 3 ), d(k- 2 ), d(k- 1 ) and d(k)] and four new edge bits [x(k- 4 ), x(k- 3 ), x(k- 2 ) and x(k- 1 )]. Based on these inputs (plus the previously input data bit d(k- 4 ), the 4D data module outputs five binary signals (three data bits and two edge bits) to each phase-detector (PD) logic module. 
     The five binary signals provided to the lower PD logic module in  FIG. 3  are: C=d(k); T 2 =x(k- 1 ); B=d(k- 1 ); T 1 =x(k- 2 ); and A=d(k- 2 ). The three data bits are as follows: d(k) is the kth (current) data bit; d(k- 1 ) is the data bit before the kth data bit; and d(k- 2 ) is the data bit that is two bits before the kth data bit. The two edge bits are as follows: x(k- 1 ) is the edge bit that is sampled at the edge between d(k) and d(k- 1 ); and x(k- 2 ) is the edge bit that was sampled at the edge between d(k- 1 ) and d(k- 2 ). 
     For example, assume that at cycle k, d(k) is an even data bit from d 0 . In this case, d(k- 1 ) is the odd data bit from d 180  that precedes d(k) in the data bit stream, and d(k- 2 ) is the even data bit from d 0  that precedes d(k- 1 ) in the data bit stream. In this case, x(k- 1 ) is the edge bit from either a 270  or b 270  that was sampled at the edge between d(k- 1 ) and d(k), and x(k- 2 ) is the edge bit from either a 90  or b 90  that was sampled at the edge between d(k- 2 ) and d(k- 1 ). 
     As another example, assume that at cycle k, d(k) is an odd data bit from d 180 . In this case, d(k- 1 ) is the even data bit from d 0  that precedes d(k) in the data bit stream, and d(k- 2 ) is the odd data bit from d 180  that precedes d(k- 1 ) in the data bit stream. In this case, x(k- 1 ) is the edge bit from either a 90  or b 90  that was sampled at the edge between d(k- 1 ) and d(k), and x(k- 2 ) is the edge bit from either a 270  or b 270  that was sampled at the edge between d(k- 2 ) and d(k- 1 ). 
     Similarly, the five binary signals provided to the upper PD logic module in  FIG. 3  are: C=d(k- 2 ); T 2 =x(k- 3 ); B=d(k- 3 ); T 1 =x(k- 4 ); and A=d(k- 4 ). The three data bits are as follows: d(k- 2 ) is the data bit that is two bits before the kth data bit; d(k- 3 ) is the data bit that is three bits before the kth data bit; and d(k- 4 ) is the data bit that is four bits before the kth data bit. The two edge bits are as follows: x(k- 3 ) is the edge bit that was sampled at the edge between d(k- 2 ) and d(k- 3 ); and x(k- 4 ) is the edge bit that was sampled at the edge between d(k- 3 ) and d(k- 4 ). 
       FIG. 4  is an example timing diagram depicting the three data bit signals (A, B, and C) and the two edge bit signals (T 1  and T 2 ) input to each Phase-detector logic module in accordance with an embodiment of the invention. In this example, the first (A or Bit(n)) and third (C or Bit(n+2)) data bits are even data bits (from d 0 ), and the second data bit, B or Bit(n+1), is an odd data bit (from d 180 ). Further in this example, the first edge bit (T 1 ) is the sampled edge (from either a 90  or b 90 ) between the first and second data bits, and the second edge bit (T 2 ) is the sampled edge (from either a 270  or b 270 ) between the second and third data bits. 
       FIGS. 5A and 5B  provide truth tables for each of the two phase-detector (PD) logic modules in accordance with an embodiment of the invention. Each PD logic module uses five binary inputs (A, T 1 , B, T 2 , and C) to generate four intermediate binary signals (UP 1 , DN 1 , UP 2 , and DN 2 ), and uses the four intermediate binary signals to generate two binary outputs (UP and DN). 
     As shown by the two truth tables in  FIG. 5A , a first pair of intermediate signals UP 1  and DN 1  depend on the input signals A, T 1  and B, while a second pair of intermediate signals UP 2  and DN 2  depend on the input signals B, T 2  and C. 
     As shown in the top truth table of  FIG. 5A : 
     when A=0, T 1 =0, and B=0, then UP 1 =0 and DN 1 =0; 
     when A=0, T 1 =0, and B=0, then UP 1 =0 and DN 1 =0; 
     when A=0, T 1 =0, and B=1, then UP 1 =0 and DN 1 =1; 
     when A=0, T 1 =1, and B=0, then UP 1 =0 and DN 1 =1; 
     when A=0, T 1 =1, and B=1, then UP 1 =1 and DN 1 =0; 
     when A=1, T 1 =0, and B=0, then UP 1 =1 and DN 1 =0; 
     when A=1, T 1 =0, and B=1, then UP 1 =0 and DN 1 =1; 
     when A=1, T 1 =1, and B=0, then UP 1 =0 and DN 1 =1; and 
     when A=1, T 1 =1, and B=1, then UP 1 =0 and DN 1 =0. 
     As shown in the bottom truth table of  FIG. 5A : 
     when B=0, T 2 =0, and C=0, then UP 2 =0 and DN 2 =0; 
     when B=0, T 2 =0, and C=0, then UP 2 =0 and DN 2 =0; 
     when B=0, T 2 =0, and C=1, then UP 2 =0 and DN 2 =1; 
     when B=0, T 2 =1, and C=0, then UP 2 =0 and DN 2 =1; 
     when B=0, T 2 =1, and C=1, then UP 2 =1 and DN 2 =0; 
     when B=1, T 2 =0, and C=0, then UP 2 =1 and DN 2 =0; 
     when B=1, T 2 =0, and C=1, then UP 2 =0 and DN 2 =1; 
     when B=1, T 2 =1, and C=0, then UP 2 =0 and DN 2 =1; and 
     when B=1, T 2 =1, and C=1, then UP 2 =0 and DN 2 =0. 
     As shown by the truth table in  FIG. 5B , the pair output signals (UP and DN) depend on the four intermediate signals (UP 1 , DN 1 , UP 2  and DN 2 ). In particular, as shown in the truth table of  FIG. 5B : 
     when UP 1 =0, DN 1 =0, UP 2 =0 and DN 2 =0, then UP=0 and DN=0; 
     when UP 1 =0, DN 1 =0, UP 2 =0 and DN 2 =1, then UP=0 and DN=1; 
     when UP 1 =0, DN 1 =0, UP 2 =1 and DN 2 =0, then UP=1 and DN=0; 
     when UP 1 =0, DN 1 =1, UP 2 =0 and DN 2 =0, then UP=0 and DN=1; 
     when UP 1 =0, DN 1 =1, UP 2 =0 and DN 2 =1, then UP=0 and DN=1; 
     when UP 1 =0, DN 1 =1, UP 2 =1 and DN 2 =0, then UP=1 and DN=1; 
     when UP 1 =1, DN 1 =0, UP 2 =0 and DN 2 =0, then UP=1 and DN=0; 
     when UP 1 =1, DN 1 =0, UP 2 =0 and DN 2 =1, then UP=1 and DN=1; and 
     when UP 1 =1, DN 1 =0, UP 2 =1 and DN 2 =0, then UP=1 and DN=0. 
     Referring back to  FIG. 3 , the output multiplexer (mux) receives a first pair of UP and DN signals from the lower PD logic module and a second pair of UP and DN signals from the upper logic module. The output multiplexer is driven by the 4T_CLK which has a clock period that is twice as long as the recovered clock signal. 
     During one edge (for example, the rising edge) of 4T_CLK, the output multiplexer may switch the UP and DN signals from the lower PD logic module to be the output signals up and dn, respectively. During the other edge (for example, the falling edge) of 4T_CLK, the output multiplexer may switch the UP and DN signals from the upper PD logic module to be the output signals up and dn, respectively. 
     As further shown in  FIG. 3 , the up and dn output signals from the output multiplexer may be provided to the charge pump (CP) circuit, and the output from the charge pump may be provided to a voltage-controlled oscillator (VCO). The VCO may generate the recovered (0-degree) clock signal (cdr_clk_ 0 ). Note that the 90-degree, 180-degree, and 270-degree clock signals (cdr_clk_ 90 , cdr_clk_ 180 , and cdr_clk_ 270 , respectively) may be obtained from the recovered clock signal. For example, 90-degree, 180-degree, and 270-degree phase delays may be applied to the recovered clock signal. 
       FIG. 6A  depicts an eye diagram and data sampling locations using a receiver circuit with speculative DFE and conventional phase detection. In particular, the eye diagram is for an even DFE-equalized data signal. Data sampling locations  602  using conventional bang-bang phase detection are shown, along with the conventional bang-bang CDR locked locations  604 . 
     As seen, the data sampling locations in  FIG. 6A  are biased to the right side of the equalized eye. This disadvantageously reduces the margin of error and may result in difficulty in achieving a very low bit error rate (BER), such as a BER smaller than 10 −12 . 
       FIG. 6B  depicts an eye diagram and data sampling locations using a receiver circuit with speculative DFE and optimized phase detection in accordance with an embodiment of the invention. As in  FIG. 6A , the eye diagram of  FIG. 6B  is for an even DFE-equalized data signal. Data sampling locations  612  using the phase detection circuitry disclosed herein are shown, along with improved bang-bang CDR locked locations  614 . 
     As seen, the data sampling locations  612  in  FIG. 6B  are at the center of the equalized eye. This advantageously increases the margin of error (both horizontal and vertical) and so supports the achievement of a lower BER, such as a BER smaller than 10 −12 . 
       FIG. 7  depicts a multi-tap feedback filter for decision feedback equalization in accordance with an embodiment of the invention. The multi-tap feedback filter of  FIG. 7  is an example of circuitry that may be part of DFE circuit  112  of  FIG. 1 . As illustrated, the recovered data signal may be fed back and input into a multiple-stage tapped delay line of an exemplary filter structure. Each Z −1  delay is a unit delay circuit. 
     After the first unit delay, the data signal is weighted by tap weight w 1 , and the result is provided as the first tap output H 1 . After the second unit delay, the data signal is weighted by tap weight w 2 , and the result is provided as the second tap output H 2 . After the third unit delay, the data signal is weighted by tap weight w 3 , and the result is provided as the third tap output H 3 . And so on for further tap outputs. In this way, a set of tap outputs may be produced. 
     In the above description, numerous specific details are given to provide a thorough understanding of embodiments of the invention. However, the above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. One skilled in the relevant art will recognize that the invention can be practiced without one or more of the specific details, or with other methods, components, etc. 
     In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. These modifications may be made to the invention in light of the above detailed description.