Abstract:
A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.

Description:
PRIORITY CLAIM 
     This application claims priority from European patent application No. 03425390.6, filed Jun. 16, 2003, which is incorporated herein by reference. 
     TECHNICAL FIELD 
     The present invention relates to a writing circuit for a phase change memory (PCM) device. 
     BACKGROUND 
     As is known, phase change memory (PCM) arrays are based upon memory elements which use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material forming the memory element, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values. 
     Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as calcogenides or calcogenic materials, can be used advantageously in phase change memory cells. The currently most promising calcogenide is formed from an alloy of Ge, Sb and Te (Ge 2 Sb 2 Te 5 ), which is now widely used for storing information on overwritable disks. 
     In the calcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa. In the amorphous state, moreover, the resistivity depends to a marked extent upon the temperature, with variations of approximately one order of magnitude every 100° C. with a behavior typical of P-type semiconductors. 
     Phase change can be obtained by locally increasing the temperature. Below 150° C., both the phases are stable. Above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the calcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the calcogenide. 
     From the electrical standpoint, it is possible to reach the crystallization and melting temperatures by causing a current to flow through a resistive element (also called a heater) that heats the calcogenic material by the Joule effect.  FIG. 1  illustrates, in a simplified way, the behavior of the resistance of a calcogenic material as a function of the heating current and the logic values associated thereto, wherein RR indicates the resistance corresponding to the amorphous state (reset state or logic “0”) and R S  indicates the resistance corresponding to the crystalline or polycrystalline state (set state or logic “1”). 
     The programming curve of a phase change memory element is shown in  FIG. 2 . Curve A represents the behavior of a PCM element in the reset state (high resistivity) and curve B represents the behavior of a PCM element in the set state (low resistivity), when a voltage of an increasing value is applied. 
     As shown, when a voltage higher than a threshold value (Vth) is applied to an element in the reset state, with Vth being a function of the material and the geometry of the element, the cell changes its state and switches from the high resistivity curve A to the low resistivity curve B. 
     When the cell is in the set state along curve B, it is necessary to apply a voltage/current pulse of suitable length and high amplitude (greater than Vreset/Imelt) so as to cause the element to switch to the amorphous phase associated to a high resistivity. The resetting pulse should be interrupted in a short time (quench time) of about 1–10 ns. 
     To bring the element in the set state (so as to cause crystallization of the calcogenic material and thus switching to a low resistivity state) it is necessary to apply a voltage/current pulse of a suitable length and amplitude (portion of curve B comprised between I 1  and I 2 ), however avoiding any quenching and allowing the element to cool slowly. 
       FIG. 3  shows the current amplitudes (I S , I R ) of typical set and reset current pulses and the respective set and reset time lengths (t S , t R ). 
     The structure of a phase change memory array using a calcogenic element as a storage element is shown in  FIG. 4 . The memory array  1  of  FIG. 4  comprises a plurality of memory cells  2 , each including a memory element  3  of the phase change type and a selection element  4  formed here by an NMOS transistor. Alternatively, the selection element  4  may be formed by a bipolar junction transistor or a PN diode. 
     The memory cells  2  are arranged in rows and columns. In each memory cell  2 , the memory element  3  has a first terminal connected to an own bitline  11  (with addresses BLn−1, BLn, . . . ), and a second terminal connected to a first conduction terminal of an own selection element  4 . The selection element  4  has a control terminal connected to an own control line, also referred to as wordline  12  (with addresses WLn−1, WLn, . . . ), and a second conduction terminal connected to ground. 
     For biasing the memory element  3  belonging to a specific cell  2 , for example the one connected to the bitline BLn−1 and to the wordline WLn−1, to a suitable voltage (V 2 −V 1 ), the bitline  11  connected to the selected cell is brought to a first voltage V 1  and the wordline  12  connected to the selected cell is brought to a high voltage, so that the second terminal of the memory element  2  is biased to a second voltage V 2  close to zero. 
     Writing is effected by applying to a selected cell the current pulses shown in  FIG. 3 . 
     The application of the constant current pulses of  FIG. 3  is however disadvantageous since variations in the manufacturing process may cause a considerable variation in the current requested for programming a memory cell. The programming current depends on the contact area between the calcogenic material and the heater; in particular, bigger contact areas require higher programming currents and vice-versa. As a matter of facts, the requested programming current ranges between I 1  and I 2  in  FIG. 2 , considering a safety margin. Thus, the application of a single programming current value may not be able to ensure programming of all the memory cells (all bits). 
     U.S. Pat. No. 6,487,113 describes a method for programming a phase-change memory with a short quench time based on applying a high current pulse to all the cells, to bring them in a first state, decreasing some of the currents to lower levels at sufficiently high rates to cause the corresponding cells to be programmed to the first state and decreasing the other currents at sufficiently low rates to cause the other cells to be programmed to a second state. 
     The above solution allows the quench time to be reduced, but has the drawback of requiring a complex and bulky programming circuit. The programming circuits shown therein also dissipate high currents. 
     SUMMARY 
     An aspect of the invention is therefore to overcome the drawbacks referred to above, devising a simple writing circuit requiring a small integration area. 
     According to another aspect of the present invention a phase change memory device and a corresponding write method are provided. 
     According to one aspect of the invention, programming of a memory cell is carried out using the discharge current of a capacitive circuit to generate the pulse necessary to set or reset the memory cell. Thus, programming is no longer obtained by applying a rectangular pulse having at least one portion with constant amplitude ( FIG. 3 ), but the programming current has a substantially exponential behavior, as discussed in more detail later on. 
     In practice, with reference to  FIG. 2 , during programming the cell characteristic is caused to follow the plot of curve B in the decreasing direction for a suitable long time. 
     According to another aspect of the invention, an RC pulse is obtained using the capacitors already present in the charge pump used for biasing the selected bit line(s). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a better understanding of the present invention, there are now described preferred embodiments, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
         FIG. 1  shows the plot of the resistance in set PCM cells and reset PCM cells as a function of the current; 
         FIG. 2  shows a current versus voltage plot of PCM cells during programming; 
         FIG. 3  shows the shape of programming pulses according to the prior art; 
         FIG. 4  is a circuit diagram of an array of PCM cells; 
         FIG. 5  illustrates a block diagram of the architecture of the present memory device according to an embodiment of the present invention; 
         FIG. 6  illustrates a more detailed diagram of a part of the memory device of  FIG. 5  according to an embodiment of the present invention; 
         FIG. 7  is more detailed diagram of a block of  FIG. 6 , according to a first embodiment of the present invention; 
         FIG. 8  illustrates the plot of the programming current versus time according to an embodiment of the invention; 
         FIG. 9  illustrates a more detailed diagram of a block of  FIG. 6 , according to a second embodiment of the present invention; and 
         FIG. 10  illustrates a more detailed diagram of a block of  FIG. 6 , according to a third embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following discussion is presented to enable a person skilled in the art to make and use the invention. Various modifications to the embodiments will be readily apparent to those skilled in the art, and the generic principles herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     According to  FIG. 5 , a phase change memory (PCM) device  20  comprises a memory array  1  having the structure illustrated in  FIG. 4 , the memory cells  2  whereof are addressed through wordlines  12  (having addresses WLn−1, WLn, . . . ) and through bitlines  11  (having addresses BLn−1, BLn, . . . ). 
     The bitlines  11  extend from a column decoder  22  formed by a plurality of selection switches implemented by NMOS or PMOS transistors, connected in series between biasing nodes  14  and the bitlines  11  and controlled by respective column selection signals so as to select and bias each time some selected bitlines  11  (of a number equal to the number of cells that are read/written simultaneously). The number of selection switches forming the column selector  22  depends upon the dimensions of the memory array or of each sector and upon the memory organization. For example, in  FIG. 5  each path between a biasing node  14  and a bitline  11  comprises two PMOS transistors  15  and  16 , controlled by respective column selection signals Yin, Yn, and an NMOS transistor  17 , operating also as a cascode and controlled by a respective column selection signal Yo. NMOS transistor  17  may be of the natural type, that is low threshold type, as discussed in European Patent Application No. 01830808.0 filed on 27 Dec., 2001, which is incorporated herein by reference. 
     Each bitline  11  is moreover connected to a first conduction terminal of an own discharge transistor  18 . Each discharge transistor  18  has a second terminal grounded and a control terminal receiving control signal Dsn−1, Dsn, so as to be selectively enabled. 
     The column decoder  22  is selectively connected to a write stage  24  or to a read stage  25  through a read/write selector  26 . 
     The read/write selector  26  comprises a plurality of pairs of PMOS transistors selectively connecting each biasing node  14  to an own write line  30  or to an own read line  31 . Each pair of PMOS transistors include a write transistor  32  and a read transistor  33 . All the write transistors  32  are controlled by a same write enable signal Yw, and all the read transistors  33  are controlled by a same read enable signal Yr. The write lines  30  are connected to as many outputs of the write stage  24 ; the read lines  31  are connected to as many outputs of the read stage  25 . 
     The write stage  24  (described in greater detail with reference to  FIG. 6 , and receiving a write enable signal WE) generates the currents necessary for writing. In detail, the write stage  24  comprises a charge accumulation stage  35  including RC circuits that store the writing charges and are discharged when so enabled by a control circuitry. 
     The read stage  25 , having e.g. the structure disclosed in European Patent Application No. 03425098.5 filed on 21 Feb. 2003 in the name of the same applicant, which is incorporated herein by reference, has the function of reading the information content of the selected memory cells and is controlled by a read enable signal OE. 
     When memory array  1  is accessed, the bitlines  11  connected to the memory cells to be read/written are selected by suitably switching PMOS transistors  15 ,  16  and NMOS transistor  17 . 
     During writing, the write transistors  32  are on and the read transistors  33  are off. The PMOS transistors  15 ,  16  and the NMOS transistors  17  corresponding to the selected bitlines  11  (as well as the write transistors  32 ) are biased so as to reduce as much as possible the voltage drop across them; i.e., the signals Ym, Yn, Yw are brought low (for example to ground), and the signals Yo are brought high (to a value such as not to significantly limit the writing current). The current supplied to the memory cell  2  is supplied by the write stage  24 . The current value depends on the datum to be written. For example, if the datum is “1”, a set current is applied; if the datum is “0”, a reset current is applied. 
     During reading, the read transistors  33  are turned on, and the write transistors  32  are turned off. Reading takes place in a per se known manner. 
       FIG. 6  shows the block diagram of a first embodiment of the write stage  24 . The write stage  24  comprises a charge pump  37 , a voltage regulator  38  and the charge accumulation stage  35 . 
     The charge pump  37  has any known structure and generates the voltages necessary for operation of the write stage  24  and read stage  25 . 
     The voltage regulator  38  is connected to the charge pump  37  and has the task of stabilizing the operating voltages. 
     The charge accumulation stage  35  comprises a plurality of bitline write circuits  39 , one for each selected bitline  11  (N for words of N bits). Each bitline write circuit  39  has a data input  40  receiving a datum to be written (D 0 , D 1 , . . . , DN), a charging input  41  connected to the charge pump  37 , and a write output  42  connected to an own write line  30 . 
     Each bitline write circuit  39 , one embodiment whereof is shown in  FIG. 7 , comprises a set circuit  43 , a reset circuit  44  and a logic circuit  45 . 
     As shown in  FIG. 7 , the set circuit  43  and the reset circuit  44  have the same structure and are formed essentially by a capacitive branch  46   a  and a resistive branch  46   b.    
     Each capacitive branch  46   a  is connected between the charging input  41  and ground and comprises a plurality of capacitors  47 , connected in parallel via a plurality of controlled switches  48  allowing selection of the number of connected capacitors  47  and thus the overall capacitance of the capacitive branch  45 . 
     Each resistive branch  46   b  is connected between the charging input  41  and the write output  42  and comprises a plurality of resistors  50  connected in series. A corresponding plurality of switches  51  are provided, each connected in parallel to a respective resistor  50  for bypassing it  50  and thus modify the overall resistance of the resistive branch  46   b.    
     A first input switch  52  is connected between the charging input  41  and the set circuit  43  and receives a control signal T 1 ; a first output switch  53  is connected between the set circuit  43  and the write output  42  of the bitline write circuit  39  and receives a control signal T 2 ; analogously, a second input switch  54  is connected between the charging input  41  and the reset circuit  44  and receives a control signal T 3 ; a second output switch  55  is connected between the reset circuit  44  and the write output  42  of the bitline write circuit  39  and receives a control signal T 4 . 
     The logic circuit  45  has an input connected to data input  40  and outputs connected to switches  52 – 55  and outputting control signals T 1 –T 4 . The logic circuit  45  also receives the write enable signal WE as well as timing signals from a control unit of the memory device  20 , not shown. 
     As indicated, by controlling the state of the switches  48 ,  51  (and thus the number of capacitors  47  and resistors  50  connected in the capacitive branch  46   a  and in the resistive branch  46   b ) it is possible to trim the overall capacity of the capacitive branch  46   a  and the overall resistance of the resistive branch  46   b . By suitably selecting the overall capacitance and resistance, as well as by suitably selecting the charging voltage of the capacitors it is possible to shape the desired current pulse, as below discussed, and to compensate for any variation in the circuit parameters due to process spread. 
     During writing, according to the value of the datum to be written, fed on data input  40 , the logic circuit  45  activates selectively the set circuit  43  or the reset circuit  44 , through control signals T 1 –T 4 . 
     If the datum to be written is a “1”, the logic circuit  45  activates the set circuit  43 , by closing switches  52 ,  53 . In this condition, the set circuit  43  is connected to the charge pump  37 , causing the capacitors  47  and any parasitic capacitance associated with the bitline write circuit  39  and the selected bitline  11  to be charged. 
     Then, control signal T 1  switches, disconnecting the set circuit  43  from the charge pump  37 . After biasing the selected wordlines  12 , the capacitors  47  discharge through the resistive branch  46   b , any parasitic resistance and the resistance of the selected memory cell  2 , generating a current I having the plot shown in  FIG. 8 . After the current I has reached value I 2 , it is possible to disconnect the selected bitline  11  from the set circuit  43 , by opening switch  53 . Thereby it is possible to maintain the residual charge in the capacitive branch  46   a , and so obtain an energy saving. 
     At the end of writing, the set circuit  43  is connected again to the charge pump  37  by closing switch  52 . Recharging of the capacitive branch  46   a  is thus carried out only from the residual voltage. 
     As indicated, by using the relationship describing the behavior of the discharge current in an RC circuit, it is possible to suitably dimension the set circuit. Specifically, since the current values I 1  and I 2  (see  FIG. 2 ) as well as the set time tset (time necessary to set a memory cell  2 ) are preset physical parameters, by fixing the resistance R (including the resistance of the resistive branch  46   b  and the resistance of the memory cell  2 ) and the voltage Vp supplied by the charge pump, it is possible to calculate the capacitance C of the capacitive branch  46   a  that causes the discharge current I to follow the discharge curve shown in  FIG. 8 . 
     Specifically, by neglecting the parasitic resistances and capacitance, we have:
 
 t 2 −t 1 =t set
 
( R*I 1) /Vp =exp(− t 1 /RC )
 
( R*I 2)/ Vp =exp(− t 2 /RC )
 
By defining:
 
 K =In( R*I 1 /Vp )/In( R*I 2 Np )= t 1 /t 2
 
it follows:
 
 t 1 =t set* K /( K −1)  (1)
 
 t 2= t set/( K −1)  (2)
 
 RC=[K*t set/( K −1)]/In( R*I 1 /Vp )  (3)
 
From equations (1)–(3) it is thus possible to calculate the capacitance C of the capacitive branch  46   a.  
 
     If the datum to be written is a “0”, the logic circuit  45  activates the reset circuit  44 , by closing switches  54 ,  55 . In this condition, the reset circuit  44  is connected to the charge pump  37 , causing the capacitors  47  and any parasitic capacitance associated with the bitline write circuit  39  and the selected bitline  11  to be charged. 
     Then, control signal T 3  switches, disconnecting the reset circuit  44  from the charge pump  37 . After biasing the selected wordlines  12 , the capacitors  47  of the reset circuit  44  discharge through the resistive branch  46   b , any parasitic resistance and the resistance of the selected memory cell  2 , generating a current also having the plot shown in  FIG. 8 . To allow a correct operation of the reset circuit, pump voltage Vp should be higher than voltage Vreset of  FIG. 2 . In particular, reset occurs in a portion of curve B of  FIG. 2  above the melting point (Imelt, Vreset). The reset current may have such a high value to ensure reset of all the memory cells  2 , taking into account any spread in the reset current due to process variation, or move along curve B (but remaining above Imelt) in a very short time. In both cases, the value of the programming current at the end of the reset is very near to the beginning value, so as to practically consider the reset current to be an approximately constant pulse. 
     After a preset time, when the memory cell  2  has changed to the reset state, the discharge transistor  18  ( FIG. 5 ) is switched on by the respective control signal Ds, thus allowing the quench. Then, also switch  55  is opened, and switch  54  is closed to allow connection of the reset circuit  44  to the charge pump  37 . 
     In order to reduce the memory access time during writing, it is possible to use an architecture that allows a reduction in the waiting time due to the charging of the capacitors  47  of the set and reset circuits  43 ,  44  of  FIG. 7 , as shown in  FIG. 9 , illustrating a different embodiment of a bitline write circuit  39 . 
     According to  FIG. 9 , each bitline write circuit  39  comprises, in addition to the logic circuit  45 , set circuit  43  and reset circuit  44 , a further set circuit  43   a  and a further reset circuit  44   a . Further set circuit  43   a  has the same structure as set circuit  43 ; further reset circuit  44   a  has the same structure as reset circuit  44 . 
     Thus, the logic circuit  45  generates further control signals T 1   a –T 4   a  for further input and output switches  52   a – 55   a.    
     The logic circuit  45  alternately activates the set circuit  43  and the further set circuit  43   a  in subsequent set operations; analogously, the reset circuit  44  and the further reset circuit  44   a  are controlled alternately by the logic circuit  45 . Thereby, after a set operation carried out using e.g. set circuit  43 , the further set circuit  43   a  is immediately ready to generate the discharge current I; meanwhile the set circuit  43  is charged again by charge pump  37  to the pump voltage Vp. Analogously, if reset circuit  44  is used to carry out a reset step, the following reset current is generated through the further reset circuit  44   a.    
     Thus, no time is lost during two subsequent set or reset operations to allow charging of the relative circuit. 
     According to another embodiment of the invention, the capacitor  47  may be formed by the output capacitor of the charge pump, that has here the double function of voltage generator and charge accumulator. 
     Accordingly,  FIG. 10  illustrates a write stage  24  including a plurality of bitline write circuits  59 , one for each selected bitline  11 . Each bitline write circuit  59  includes a charge pump  60  and a resistive circuit  61  cascade-connected. A switch  65  is coupled between the resistive circuit  61  and the write output  42 . 
     Each charge pump  60  includes a plurality of cascade-connected pumping stages  67 , each formed by a switch  63 , coupled between the input and the output of the respective stage, and by a capacitor  62 , having a first terminal connected to the output of the respective stage and a second terminal receiving a phase signal F 0 , F 1 . In a per se known manner, the phase signal F 0 , F 1  fed to the second terminal of each capacitor  62  is in phase opposition to the phase signal F 1 , F 0  supplied to the neighboring capacitors and is also in phase opposition to the control signals fed to the switch  63  belonging to the same pumping stage  67 . 
     The last capacitor  62   a  belonging to an output stage  67   a  defines an accumulation capacitor connected to the resistive circuit  61 . 
     The resistive circuit  61  has the same structure as the resistive branch  46   b  of  FIG. 7  and comprises a plurality of resistors  64  that are connected in series and may be selectively bypassed by respective switches  66 . 
     In the circuit of  FIG. 10 , the charge pump  60  charges the accumulation capacitor  62   a  to the pump voltage Vp in a per se known manner; during writing, the switch  65  is closed and allow discharge of the accumulation capacitor  62   a  (which is now disconnected from the preceding capacitors  62  by switch  63   a ) through the resistive circuit  61 , analogously to what described with reference to  FIGS. 7 and 8 . In practice, the bitline write circuits  59  of  FIG. 10  initially generate equal programming currents for all the memory cells  2  connected to the selected bitlines  11 , by activating the discharge of all the accumulation capacitors  62   a . Only for the memory cells  2  that should be reset, the programming current is interrupted by activating the respective discharge transistor  18  through the respective control signal Dsn−1, Dsn ( FIG. 5 ), while for the memory cells  2  that should be set, the discharge goes on until current value I 2  of  FIG. 2 , analogously to what described above for the circuit of  FIG. 7 . 
     The advantages of the memory device described herein are at least the following. The set operation is very reliable and setting of the memory cells is always ensured, by virtue that programming involves supplying a programming current that follows the plot of curve B shown in  FIG. 2  so that the voltage/current operating point necessary for setting is always crossed. 
     The write stage is simple and does not require a big integration area; this advantage is particularly evident for the embodiment of  FIG. 10 , where the capacitors already present in the output stage are exploited also for generating the RC type current. 
     The regulation circuits are reduced, so that the present memory device affords a current and an area saving. 
     By interrupting the discharge of the charge accumulation components when the memory cells to be written have been set (instant t 2  in  FIG. 8 ), it is possible to obtain a current saving and thus both dissipation and the subsequent charging time are reduced. 
     Finally, it is clear that numerous modifications and variations can be made to the embodiments of the PCM device described and illustrated herein, all of which fall within in the scope of the invention, as defined in the annexed claims. Moreover, the PCM device may be contained in a variety of different types of electronic systems, such as a computer system. 
     As indicated, the charge accumulation stage may be implemented through an own circuitry, or exploiting any suitable components already present in the memory device. 
     A same write stage may be used both for the set and the reset operations; in this case, the reset operation may be interrupted after a preset time (before reaching the set portion of the curve B in  FIG. 2 ) or by adapting the electrical parameters and thus the specific set and reset currents according to the operation to be carried out, e.g. by modifying the charging voltage and/or the number of capacitors/resistors connected in the capacitive/resistive branch. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention.