Abstract:
A method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore.

Description:
FIELD 
     This disclosure relates generally to the field of field effect transistor based sensors for sequencing deoxyribonucleic acid (DNA) and proteins. The sensors can also be used for detection of biological molecules such as proteins and viruses. 
     DESCRIPTION OF RELATED ART 
     Mapping the sequences of bases of a DNA strand is of great importance in life sciences. Since a single base is about 0.7 nanometers (nm) long when the DNA strand is stretched, it is important that a sensor for sequencing has spatial resolution of about 1 nm or less. Fabricating such a sensor is challenging. Another area of great importance in life sciences is detection of proteins and viruses. For protein and viruses detection, a disadvantage of many FET-based sensors is that a sensing surface of the sensor must to be covered with a biological coating that specifically binds the biomolecules to be detected. Applying the appropriate coating may be labor intensive and expensive. Further, the sensor may only be used to detect the particular biomolecules that bind with the coating, limiting the usefulness of the sensor. 
     A biomolecule sensor may comprise a field effect transistor (FET). However, for protein and viruses detection, a disadvantage of many FET-based sensors is that a sensing surface of the sensor must to be covered with a biological coating that specifically binds the biomolecules to be detected. Applying the appropriate coating may be labor intensive and expensive. Further, the sensor may only be used to detect the particular biomolecules that bind with the coating, limiting the usefulness of the sensor. A FET sensor may comprise highly doped source and drain regions formed by ion implantation followed by high temperature annealing (about 1000° C.). Though this method is standard for forming source and drain regions in longer channel (greater than 10 nm) FET devices, ion implantation and anneal may pose a problem for fabrication of relatively short FET channel (less than about 5 nm) required for high sensitivity FET devices, as ion implantation and high temperature activation annealing produce dopant density profiles in the source/drain regions that may extend several nanometers into the channel region of the FET. Consequently, the sensitivity of a FET sensor formed in this manner may be degraded, making the FET sensor inappropriate for use for sequencing DNA. 
     SUMMARY 
     In one aspect, a method of using a sensor comprising a field effect transistor (FET) embedded in a nanopore includes placing the sensor in an electrolyte comprising at least one of biomolecules and deoxyribonucleic acid (DNA); placing an electrode in the electrolyte; applying a gate voltage in the sub-threshold regime to the electrode; applying a drain voltage to a drain of the FET; applying a source voltage to a source of the FET; detecting a change in a drain current in the sensor in response to the at least one of biomolecules and DNA passing through the nanopore. 
     In one aspect, a method of forming a sensor comprising a field effect transistor (FET) sensor embedded in a nanopore includes epitaxially growing a FET stack comprising a source layer, a drain layer, and a channel layer on a silicon on insulator (SOI) wafer; forming a top silicon nitride layer over the FET stack; forming a bottom silicon nitride layer under the SOI wafer; forming a window in the bottom silicon nitride and the SOI wafer; forming a nanopore in the FET stack; and coating the nanopore with a gate dielectric to form the FET sensor. 
     In one aspect, a method of forming a sensor comprising a field effect transistor (FET) sensor embedded in a nanopore includes forming a silicon membrane; forming an oxide layer on the silicon membrane; forming a first metal layer on a side of the silicon membrane opposite the oxide layer, and a first capping layer over of the first metal layer; removing the oxide layer; forming a second metal layer on a side of the silicon membrane opposite the first metal layer, and a second capping layer over of the second metal layer; annealing the silicon membrane and first and second metal layers to form first and second metal silicide layers on opposite sides of the silicon membrane; removing the first and second capping layers; forming a nanopore through the silicon membrane and the first and second metal silicide layers; and coating the nanopore with a gate dielectric to form the FET sensor. 
     Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
         FIG. 1  illustrates an embodiment of a method of forming a FET nanopore sensor. 
         FIG. 2  illustrates an embodiment of a FET stack grown on a silicon-on-insulator (SOI) wafer after deposition of silicon nitride. 
         FIGS. 3A-F  illustrate embodiments of a FET stack. 
         FIG. 4  illustrates an embodiment of the device of  FIG. 2  after formation of a window in the bottom silicon nitride, silicon, and buried silicon oxide layers. 
         FIG. 5  illustrates an embodiment of the device of  FIG. 4  after formation of a nanopore in the FET stack and gate dielectric layer. 
         FIG. 6  illustrates an embodiment of the device of  FIG. 4  after removal of the silicon nitride. 
         FIG. 7  illustrates an embodiment of the device of  FIG. 6  after formation of a nanopore in the FET stack and gate dielectric layer. 
         FIG. 8  illustrates an embodiment of a method of forming a FET nanopore sensor comprising a metal silicide source/drain FET stack. 
         FIG. 9  illustrates an embodiment of a silicon membrane with an oxide layer. 
         FIG. 10  illustrates an embodiment of the device of  FIG. 9  after formation of a metal layer and a capping layer. 
         FIG. 11  illustrates an embodiment of the device of  FIG. 10  after removal of the oxide layer and formation of a second metal layer and a second capping layer. 
         FIG. 12  illustrates an embodiment of the device of  FIG. 11  after annealing to form silicide. 
         FIG. 13  illustrates an embodiment of the device of  FIG. 12  after removal of the capping layers, formation of a nanopore, and formation of the gate dielectric. 
         FIG. 14  illustrates an embodiment of a method of operating a FET nanopore sensor. 
         FIG. 15  illustrates an embodiment of a FET nanopore sensor immersed in an electrolyte. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of systems and methods for a FET nanopore sensor are provided, with exemplary embodiments being discussed below in detail. A FET nanopore sensor may be used to detect various types of biomolecules without requiring a sensing surface covered with a biological coating to bind the biomolecules. A FET nanopore sensor may also be used to sequence DNA strands. The FET nanopore sensor may have a relatively short channel length (less than about 3 nm in some embodiments, and less than about 1 nm in some preferred embodiments), so that the sensitivity of the FET nanopore sensor is appropriate for sequencing DNA. The FET nanopore sensor may be fabricated in a manner that results in abrupt junctions between highly doped source and drain regions that are separated by a relatively thin channel region. 
     The FET nanopore sensor may comprise a FET stack with a nanopore located in the FET stack. The FET stack comprises a channel region located in between a source and a drain region. The channel region may have a doping type (p-type or n-type) that is opposite a doping type (p-type or n-type) of the source and drain regions. To form abrupt junctions between the source/drain regions and the channel region, the diffusion of dopant atoms between the source/drain regions and the channel region may be minimized during the fabrication process by using epitaxial growth on a silicon-on-insulator (SOI) substrate to form the FET stack. Epitaxial growth is performed at a relatively low temperature (less than about 600° C.), which reduces the diffusion of dopant atoms. Layers of materials including but not limited to silicon germanium (SiGe), carbon-doped silicon germanium (SiGe:C), or silicon carbide (SiC) may be formed to act as barriers to diffusion of dopant atoms during fabrication of the FET nanopore sensor. Alternately, the FET stack may comprise a silicon channel between a metal silicide source and drain. 
       FIG. 1  illustrates an embodiment of a method  100  of making a FET nanopore sensor.  FIG. 1  is discussed with respect to  FIGS. 2-7 . In block  101 , a FET stack  205  is epitaxially grown on a SOI wafer (comprising a relatively thick silicon layer  202 , buried silicon oxide layer  203 , and top silicon layer  204 ), as is shown in  FIG. 2 . Various methods of forming FET stack  205  are discussed below in further detail with respect to  FIGS. 3A-F . Top silicon nitride layer  206  and bottom silicon nitride layer  201  are formed on FET stack  205  and under silicon layer  202 , respectively. 
       FIGS. 3A-F  illustrate embodiments of FET stacks  300 A-F that may comprise FET stack  205  of  FIG. 2 . FET stack  300 A shown in  FIG. 3A  comprises an nFET comprising a drain layer  303 A comprising heavily doped n-type silicon, under a channel layer  302 A comprising lightly doped p-typed SiGe or SiC doped with boron, under a source layer  301 A comprising heavily doped n-type silicon. The drain layer  303 A is first epitaxially grown on silicon layer  204  (of  FIG. 2 ), then channel layer  302 A is epitaxially grown on drain layer  303 A, and source layer  301 A is epitaxially grown on channel layer  302 A. Channel layer  302 A comprises abrupt junctions with both source layer  301 A and drain layer  303 A. Channel layer  302 A may have a thickness of less than 3 nm in some embodiments, and less than 1 nm in some preferred embodiments. Source layer  301 A is formed over the channel layer  302 A in such a manner that minimizes n-type dopant diffusion from n-type source layer  301 A into p-type channel region  302 A. Additionally, as shown in  FIG. 3C , an nFET stack  300 C comprising an n-type drain  301 C, n-type source  303 C, and p-type channel  302 C may also be formed in a manner similar to pFET stack  300 A, with the source on the bottom and the drain on the top. 
     In some embodiments, a boron-doped channel layer  302 A may be formed by the epitaxial growth of a layer of p-type material on an existing n-type drain layer  303 A; drain layer  303 A may be formed using a chemical vapor deposition (CVD) process. The wafer may be pre-baked in a purified hydrogen (H2) ambient at a temperature greater than about 750° C., and more typically greater than about 850° C. The temperature may then be lowered to about 650° C. or less; for monolayer level growth and doping control, temperatures below about 550° C. are preferred. The dopant gas may comprise diborane (B2H6) and the semiconductor precursors may comprise silane, disilane, trisilane, germane, or any combination thereof. In other embodiments, combinations of intrinsic (undoped) multilayer growth and boron exposure may be used to form p-type channel layer  302 A. To preserve the boron doping concentration at the monolayer level, channel layer  302 A may be grown using a material in which boron has a relatively low diffusivity, such as Si alloyed with Ge or C (or mixtures thereof). Ge content in channel layer  302 A may be adjusted to tune the threshold voltage of the FET nanopore sensor. The subsequent growth of the n-type source layer  301 A on channel layer  302 A may be performed at as low a temperature as possible. Growth of source layer  301 A may be preformed using phosphine or arsine as dopant gases and silane, disilane, trisilane, any chlorosilane, or germane (or mixtures thereof) as the semiconductor precursors. Preferably, the use of low-temperature growth using higher-order silanes (di- and tri-silanes) allows the source region  301 A to be grown at temperature below about 600° C. 
     FET stack  300 B shown in  FIG. 3B  comprises a pFET comprising a heavily doped p-type drain layer  303 B, on a channel layer  302 B comprising n-doped Si, on a heavily doped p-type source layer  301 B. The drain layer  303 B is first epitaxially grown on silicon on insulator (SOI) of  FIG. 2 , then channel layer  302 B is epitaxially grown on drain layer  303 B, and source layer  301 B is epitaxially grown on channel layer  302 B. The formation of channel region  302 B and the subsequent formation of source layer  301 B may be performed at relatively low temperature, less than about 600° C. to limit diffusive broadening of the abrupt profile. Source and drain layers  301 B and  303 B may be doped with boron in some embodiments. The source layer  301 B and drain layer  303 B may comprise p-type SiGe, SiGe:C or SiC in some embodiments, which may act to reduce boron diffusion into channel layer  302 B. Channel layer  302 B comprises abrupt junctions with both source layer  301 A and drain layer  303 B. Channel layer  302 B may have a thickness of less than 3 nm in some embodiments, and less than 1 nm in some preferred embodiments. Additionally, as shown in  FIG. 3D , a pFET stack  300 D comprising an p-type drain  301 D, p-type source  303 D, and n-type channel  302 D may also be formed in a manner similar to pFET stack  300 B, with the source on the bottom and the drain on the top. 
     Boron diffusion into channel layer  302 B may also be limited by formation of source/drain cladding layers adjacent to channel layer  302 B to contain the boron from source layer  301 B and drain layer  303 B. For example, before growth of channel region  302 B, a cladding layer of SiGe, SiGe:C, or SiC layer may be grown at a relatively low temperature on drain layer  303 B before formation of channel layer  302 B, which may limit the diffusivity of the boron from drain layer  303 B. A second cladding layer may then be formed on channel region  302 B before formation of source layer  301 B. Channel layer  302 B may comprise silicon doped n-type dopants such as phosphorus or arsenic, which have relatively low diffusivity. Channel layer  302 A may be formed by growing a layer of undoped silicon on drain layer  303 B, and then growing source layer  301 B on undoped channel layer  302 B. The FET stack  300 B may then be exposed to the n-type dopants through methods including but not limited to ion implantation, channeled implant, gas-phase diffusion, or other ex-situ methods of inserting n-type dopants. Diffusion of n-type dopants is greater in SiGe alloys than in Si, therefore, the n-type dopants may be transported to the channel layer  302 B through source layer  301 B at a relatively low temperature to maintain the boron abruptness in the FET stack  300 B. Any n-type dopants that diffuse into in the source layer  301 B and drain layer  303 B are insignificant, as source layer  301 B and drain layer  303 B are already degenerately doped with boron. 
     In other embodiments, the FET stack  205  may comprise dual FETs, as are shown in  FIGS. 3E-F .  FIG. 3E  illustrates a dual nFET stack  300 E, comprising an n-type source  301 E over a p-type channel  302 E over a n-type drain  303 E over a second p-type channel  304 E over an n-type source  305 E. Channel regions  302 E and  304 E may have the same channel length; the channel length may be less than about 1 nm in some embodiments.  FIG. 3F  illustrates a dual pFET stack  300 F, comprising a p-type source  301 F over a n-type channel  302 F over a p-type drain  303 F over a second n-type channel  304 F over an p-type source  305 F. Channel regions  302 F and  304 F may have the same channel length; the channel length may be less than about 1 nm in some embodiments. 
     Returning to  FIG. 1 , in block  102 , photolithography and reactive ion etching are performed on bottom silicon nitride  201 , then silicon layer  202  and buried silicon oxide layer  203  are etched to form window  401  as is shown in  FIG. 4 . Etching may comprise use of a potassium hydroxide (KOH) or a Tetramethylammonium hydroxide (TMAH) solution at 80° C. In block  103 , bottom silicon nitride  201  and/or top silicon nitride  206  may be optionally removed using reactive ion etching, as is shown in  FIG. 6 . 
     In block  104 , a nanopore ( 501 ,  701 ) is formed in FET stack  205  and silicon  204 , as is shown in  FIGS. 5 and 7 . In the embodiment of  FIG. 5 , top silicon nitride  206  is present, and the nanopore  501  is formed in FET stack  205 , silicon  204 , and top silicon nitride  206 . In the embodiment of  FIG. 7 , top silicon nitride  206  has been removed (as shown in  FIG. 6 ), and the nanopore is formed in FET stack  205  and silicon  204 . Nanopore ( 501 ,  701 ) may be sized according to the type of biomolecules or DNA the sensor is used to detect in some embodiments. The gate dielectric layer ( 502 ,  702 ) is then formed to coat the surface of the nanopore ( 501 ,  701 ). Gate dielectric layer ( 502 ,  702 ) may comprise a high-k oxide material in some embodiments, and may comprise a bilayer of SiO2/HfO2 in some embodiments. The gate dielectric layer ( 502 ,  702 ) may be formed by atomic layer deposition (ALD) in some embodiments. 
       FIG. 8  illustrates an embodiment of a method  800  for forming a FET nanopore sensor comprising a metal silicide source and drain.  FIG. 8  is discussed with respect to  FIGS. 9-13 . In block  801 , a silicon membrane  901  is formed between isolation regions  902 A-B, as shown in  FIG. 9 . The top and bottom surfaces of silicon membrane  901  may be cleaned using SC1 or SC2-based chemistry without use of megasonics, to preserve the integrity of silicon membrane  901 . In some embodiments, the cleaning may comprise a 10 part per million (ppm) O3/Di water+1:1:40 NH4OH:H2O2:H2O, at 35° C., for 5 minutes, followed by 1:100 HCl:Di water, at 60° C., for 5 minutes. A silicon oxide layer  903  is then formed on the top side of the cleaned silicon membrane  901 . Silicon oxide layer  903  may be formed at a relatively low temperature. After formation of silicon oxide layer  903 , any native oxide located on the bottom side of silicon membrane  903  is etched using, for example, hydrofluoric acid. 
     In block  802 , a metal layer  1001  and a capping layer  1002  are formed on the bottom side of silicon membrane  901 , as shown in  FIG. 10 . Metal layer  1001  may comprise platinum (Pt), nickel (Ni), cobalt (Co), titanium (Ti), erbium (Er), ytterbium (Yb) or nickel platinum (NiPt) in some embodiments. Capping layer  1002  may comprise titanium nitride (TiN), or tungsten (W) in some embodiments, and may have a thickness of about 15 nm. In block  803 , silicon oxide layer  903  is removed, as shown in  FIG. 11 . Silicon oxide layer  903  may be removed using hydrofluoric acid in some embodiments. Metal layer  1101  and capping layer  1102  are then formed on the top side of silicon membrane  901 . Metal layer  1101  may comprise platinum (Pt), nickel (Ni), cobalt (Co), titanium (Ti), or nickel platinum (NiPt) in some embodiments. Capping layer  1102  may comprise titanium nitride (TiN), or tungsten (W) in some embodiments, and may have a thickness of about 15 nm. 
     In block  804 , the device  1100  of  FIG. 11  is annealed to form metal silicide layers  1201 A-B, as shown in  FIG. 12 . Portions of silicon membrane  901  react with metal layers  1001  and  1101  to form metal silicide layers  1201 A-B. The annealing may comprise rapid thermal annealing, or furnace annealing in some embodiments. In block  805 , capping layers  1002  and  1102  are removed, as shown in  FIG. 13 . Capping layers  1002  and  1102  may be removed by wet etching using, for example, a mixture of sulphuric acid and hydrogen peroxide, or aqua regia. Any unreacted portions of metal layers  1001  and  1101  that may be present on metal silicide layers  1201 A-B are also removed. Then, a nanopore  1301  is formed in the FET stack comprising metal silicide layers  1201 A-B and silicon membrane  901 . Nanopore  1301  may be sized according to the type of biomolecules or DNA the sensor is used to detect in some embodiments. Metal silicide layer  1201 A comprises the FET source, silicon membrane  901  comprises the FET channel, and metal silicide layer  1201 B comprises the FET drain. The gate dielectric layer  1302  is then formed to coat the surface of the nanopore  1301 . Gate dielectric layer  1302  may comprise a silicon dioxide or high-k oxide material in some embodiments, and may comprise a bilayer of SiO2/HfO2 in some embodiments. The gate dielectric layer  1302  may be formed by atomic layer deposition (ALD) in some embodiments. 
       FIG. 14  illustrates an embodiment of a method  1400  of operating a nanopore FET sensor.  FIG. 14  is discussed with respect to  FIG. 15 . In block  1401 , sensor  1500  is placed in electrolyte  1505 . Electrolyte  1505  may contain one or more DNA strands  1509 , and/or biomolecules  1508 . Sensor  1500  comprises nanopore  1507  through source  1501   a - b , channel  1502   a - b , and drain  1503   a - b , surrounded by gate dielectric  1504 . Channel  1502   a - b  may have a channel length of less than about 3 nm in some embodiments, and less than about 1 nm in some preferred embodiments. Source  1501   a - b , channel  1502   a - b , and drain  1503   a - b  may comprise a FET stack formed in accordance with any of the embodiments discussed above with respect to  FIGS. 1-13 . In some embodiments, sensor  1500  may further comprise top silicon nitride  206  as is shown in  FIG. 5 . 
     In block  1402 , electrode  1506  is placed in electrolyte  1505 . Electrode  1506  may comprise silver or silver chloride in some embodiments. In block  1403 , a gate voltage in the sub-threshold regime is applied to electrode  1506 , a source voltage is applied to source  1501   a - b , and a drain voltage is applied to drain  1503   a - b . The drain voltage may be about 50 millivolts (mV) in some embodiments. The source, gate, and drain voltages may comprise constant voltages. The applied voltages cause a drain current to flow between source  1501   a - b  to drain  1503   a - b , across the interface between channel  1502   a - b  and gate dielectric  1504 . 
     In block  1404 , a DNA strand  1509  or a biomolecule  1508  pass through nanopore  1507 . A vacuum pump (not shown) may be used to force the DNA strands  1509  and/or biomolecules  1508  through nanopore  1507  in some embodiments. As DNA  1509  or biomolecules  1508  pass the channel layer  1502   a - b  in the nanopore  1507 , the drain current in sensor  1500  changes due to the presence of DNA strand  1509  or biomolecules  1508 . In block  1405 , the biomolecules  1508  are detected based on the change in the drain current, or the DNA strand  1509  is sequenced based on the change in the drain current. 
     The technical effects and benefits of exemplary embodiments include formation of a biomolecule sensor that may also be used to sequence DNA, and does not require a coating to bind the biomolecules. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.