Abstract:
A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    This invention relates to a method and system using delay signals to reduce or eliminate interference between paths in a communication network, in particular to an electronic circuit.  
           [0003]    2. Description of the Related Art  
           [0004]    Communication networks, in particular communication networks on integrated circuits, have numerous paths carrying signals from one device to other devices. Multiple paths that are placed near one another can lead to problems related to coupling and capacitative interference. The situation becomes more problematic when multiple paths carrying signals switch in the same direction run parallel to a single path switching in the opposite direction.  
           [0005]    In cases of multiple paths carrying signals that switch opposite of a single path, the multiple paths are referred to as aggressors and the single path is referred to as a victim. Coupling effects do not have a noticeable effect upon aggressor signals with one another, because the signals of the aggressors are switching in the same direction. In a digital signal transmission, the rise of the signal from a driver connected to an aggressor path is not affected by signals from the other aggressor paths. Coupling effects, however, can have an effect upon the victim path&#39;s signal. In particular coupling effects lead to slower rise times of victim path signals. To compensate for slower rise times, victim path driver power is increased. The victim path driver is required to provide additional power to compensate for a slower rise time in order to get the signal out and to achieve proper signal level and timing requirements.  
           [0006]    To alleviate the effects on victim paths by aggressor paths, the paths can be laid out to allow paths that carry signals that switch in the same direction to be placed near one another. This approach, however, leads to design constraints that require paths to be placed in limited positions and limit network architecture. In most situations, paths have opposing signals placed next to each other (e.g., send and receive signals to and from devices).  
           [0007]    In certain designs, neutral paths such as ground paths (also known as shield lines) are available and placed between aggressors and victim paths, effectively shielding the victim path. Shield lines typically serve no function but are merely used to shield the victim path. The use of neutral paths or shield lines also leads to design considerations and network architecture constraints in laying out paths. Adding shield lines further adds to an increase in the space of the network. In an integrated circuit, minimizing size is highly desirable, and adding non-functional shield lines becomes counter productive to meeting the goal of minimizing size.  
         SUMMARY OF THE INVENTION  
         [0008]    In one embodiment, a method of transmitting a signal is disclosed. The method includes assigning priorities to transmitted signals. Signals that have a lower prior compared to signals with a higher priority are delayed until the higher priority signals are switched. In certain embodiments, a delay pulse is sent to by the higher priority signal or signals to the lower priority signal or signals.  
           [0009]    In another embodiment, a signal driver is disclosed. The signal driver includes a delay signal that is sent to lower priority signals that are adjacent to and can interfere with the signal generated by the signal driver. The delay signals prevents the lower priority signals from switching while the signal driver switches the signal.  
           [0010]    The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.  
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0011]    The present invention may be better understood, and it&#39;s numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the figures designates a like or similar element.  
         [0012]    [0012]FIG. 1 is a block diagram illustrating a network with priority delay insertion circuits.  
         [0013]    [0013]FIG. 2 is a block diagram illustrating a network layout with using priority delay insertion circuits and wires.  
         [0014]    [0014]FIG. 3 is a block diagram illustrating a network architecture incorporating disable logic signals.  
         [0015]    [0015]FIG. 4 is a block diagram illustrating multiple priority delay insertion circuits.  
         [0016]    [0016]FIG. 5 is a timing diagram illustrating a priority 0 signal that disables a priority 1 signal.  
         [0017]    [0017]FIG. 6 is a timing diagram illustrating multiple priority 0 signals and disabling a priority 1 signal.  
         [0018]    [0018]FIG. 7 is a flow chart illustrating when a disable pulse is generated. 
     
    
       [0019]    While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail, it should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present invention as defined by the appended claims.  
       DETAILED DESCRIPTION  
       [0020]    Digital signals, rise from a zero value to a set value that correlates to a digital value of “1.” There is a slight rise time and an associated rising edge, as well as a slight fall time and an falling edge associated with the transmitted signal. When a signal is transitioning during rise or fall time, the signal is said to be switching.  
         [0021]    This invention provides for a delay between signals, specifically signals that are close to one another that are switching in opposite signals. While a signal is switching, an adjacent signal is delayed while the transmitting signal completes switching. To determine which signal is delayed, signals are given priorities as to which signal is allowed to switch and which signal is delayed. The delay places the signals out of phase with one another, to allow signals to be transmitted with minimal coupling and capacitance effects from opposite switching signals. Reducing or eliminating the coupling and capacitance effects allows signal paths to be placed closer to one another.  
         [0022]    [0022]FIG. 1 is a block diagram illustrating a network with priority delay insertion circuits. In embodiments of the invention, the signal drivers incorporate a priority delay. Such signal drivers in embodiments of this invention are referred to as priority delay insertion circuits (PDIC). PDICs can be part of a network and can be designed as a part of a larger integrated circuit. This particular example shows a network that includes PDIC  100 , PDIC  105 , and PDIC  110 . PDICs  100 ,  105  and  110  have specific priority values. PDIC  105  has a signal  120 , signal  120  having a priority value of 0. A priority value of 0 takes precedence over all other priority values (e.g., binary values of 1, 10, 11, etc.). PDIC  100  has a signal  115  and signal  115  has a priority value 1. Likewise PDIC  110  has signal  125  and signal  125  has a priority value of 1. Whenever PDIC  105  switches a signal (i.e., transition in the rising or falling edge of signal transmission), that signal takes precedence over signals that are transmitted by PDIC  100  and PDIC  110 . PDIC  100  and  110  respectively have priority value of 1.  
         [0023]    [0023]FIG. 2 is a block diagram illustrating a network layout with using PDICs and wires. A cell  200  contains PDICs  100 ,  105 , and  110 . In certain applications, cell  200  can be part of a larger integrated circuit or system. Cell  200  is consider a subsystem that includes PDICs  100 ,  105 , and  110  interconnected to one another, and setting priority as to signal transmission. PDICs  100 ,  105 ,  110  act as drivers to transmit signals. PDIC  100  transmits signals along a path  205 . PDIC  105  transmits signals along a path  210 . PDIC  110  transmits signals along a path  215 . Signal paths that are relatively longer in length can require priority over all other paths. For example path  210  can be a longer path, therefore path  210  is given the highest priority of 0. Path  210  can also be a victim path to paths  205  and  215 , therefore path  210  is given priority of 0. Priority delay logic within PDICs  100 ,  105 , and  110  allow paths  205 ,  210 , and  215  to be placed relatively close to one and avoid coupling effects in signal transmission. Allowing the signals to be placed closer to one another provides for a denser architecture and smaller sized circuits.  
         [0024]    [0024]FIG. 3 is a block diagram illustrating a network architecture incorporating disable logic signals. This embodiment of the invention provides for PDICs  100 ,  105 , and  110  to act as drivers driving particular signals. PDIC  100  drives a signal A  300 . PDIC  105  drives a signal B  305 . PDIC  110  drives a signal C  310 . PDIC  105  and signal B  305  have priority of 0. Whenever signal B  305  is switched, PDIC  105  provides a disable signal D 0   315  to PDIC  100 , and a disable signal D 0   320  to PDIC  110 . Delaying switching of signal A  300  and signal C  310 , allows signal C  305  to be transmitted without interference. Once signal C  305  is switched, delay signal D 0   315  and delay signal D 0   320  are disable. Hardware, firmware, and/or software logic can provide delay signals. For example, a shot flip-flop device can provide a hardware delay sufficient for switching to occur. Since rise and fall times are known and/or can be accurately estimated, the necessary time delay can be provided that accounts for the rise and fall times.  
         [0025]    [0025]FIG. 4 is a block diagram illustrating multiple PDICs. Several PDICs can be connected to one another in the same cell. Priority logic connects the PDICs and contention is set among PDICs that are adjacent to one another. This particular system includes PDIC  100 , PDIC  105 , PDIC  110 , PDIC  400 , PDIC  405 , PDIC  410  and PDIC  415 . PDIC  100  drives signal A  300 . PDIC  105  drives signal B  305 . PDIC  110  drives signal C  417 . PDIC  400  drives signal D  420 . PDIC  405  drives signal E  425 . PDIC  410  drives signal F  430 . PDIC  415  drives signal G  435 . In this example, the PDICs are placed in a manner such that PDICs and signals with priority value 0 are placed between PDICs and signals with priority value 1. Signals B  120 , D  460 , and F  470  have values of 0. Signals S  115 , C  125 , E  465 , and G  475  have values of 1. Whenever signals B  305 , D  420  and F  430  are switching (i.e., on the rising or falling edge), signals A  300 , C  417 , E  425 , and G  435  are temporarily disabled. In this example, disabling of signals is limited to signals that are adjacent to one another. PDIC  105  can disable PDIC  100  and PDIC  110 , but is not able nor is it necessary (i.e., necessary to avoid coupling interference) to disable PDIC  405  or any PDTC that is not directly adjacent to PDIC  105 . A PDIC with a lower priority value of 1, such as PDIC  110  can be disabled by adjacent PDICs having a priority value of 0, in particular PDIC  105  and PDIC  400 . PDIC  400  can send disable signal  440  to PDIC  110  and PDIC  105  can send disable signal  320  to PDIC  110 . PDIC  400  can also disable PDIC  405  with a disable signal  445 . PDIC  405  can also be disabled by PDIC  410  by a disable signal  450 . PDIC  410  through disable signal  455  is able to disable PDIC  415 .  
         [0026]    [0026]FIG. 5 is a timing diagram illustrating a priority 0 signal that disables a priority 1 signal. Signal B  500  is a priority 0 signal. In a digital signal such as signal B  500 , relative minimum voltage values exist that relate to a “0” value (i.e., off value), or a “1” value (i.e., on value). In this example the relative minimum voltage values are V 1   505  that relates to a “0” value and V 2   510  that relates to a “1” value. When signal B  500  falls below V 1   505 , the signal is considered to have a value of “0” (i.e., the signal is off). When signal B  500  reaches or exceeds V 2   510 , the signal is considered to have a value of “1” (i.e, the signal is on). If coupling effects and capacitance effects are present, a greater requirement is placed on a driver to get signal B  500  to reach V 2   510 .  
         [0027]    The rising edge of signal B  500  begins at time-voltage value  507 . The rising edge ends at time-voltage value  512 . The falling edge of signal B  500  begins at time-voltage value  517 , and the falling ends at time-voltage value  515 . A disable signal  535  is activated whenever signal B is switching on the rising or falling edge. Between time-voltage values  507  and  512 , a disable pulse  540  is transmitted. The time of transmission of disable pulse  540  is represented by the time period D 0   r    550 . Between time-voltage values  517  and  515 , a disable pulse  545  is transmitted. The time of transmission of disable pulse  545  is represented by the time period D 0   f    555 . Disable pulses  540  and  545  are received by adjacent PDICs that are transmitting lower priority signals. The lower priority signals are then delayed during the time disable pulses  540  and  545  are transmitted.  
         [0028]    [0028]FIG. 6 is a timing diagram illustrating multiple priority 0 signals and disabling a priority 1 signal. When two priority 0 signals switch at or near the same time, a disable signal is provided to a common PDIC that is adjacent to the priority 0 signals. In this example, signals B  500  and D  600  are a priority 0 signals, and a disable pulse is sent to common adjacent priority 1 PDIC C  110 . Signal D  600  is a signal with relative threshold values V 1   605  and V 2   610 . Signal B  600  has a rising edge that begins at time-voltage value  607  and ends at time-voltage value  612 . Signal B  600  has a falling edge that begins at time-voltage value  517  and ends at time-voltage value  515 . The rising edge of signal D  600  is represented by the time period D 1   r    650 . The falling edge of signal D  600  is represented by time period D 1   f    630 . Time period D 0   r    550  has some overlap with time period Dl r    650 . D 0 r  550  begins and ends before Dl r    650 . D 0   f    555  and D 1   f    630  also overlap in this example. D 0   f    555  in this particular case begins and ends before D 1 f  630 . In other cases the time periods may or may not overlap. Overlap depends when the signals are transmitted. Disable signal D 0   l    660  is activated and sent to PDIC  100  during the overlap of rising and falling edges of signal B  500  and signal D  600 . An activated disable signal D 0   l    660  is represented by a disable pulse  675  and a disable pulse  680 . Time period Dcr  665  represents the time period overlap of the rising edges of signal B  500  and signal D  600 . Time period Dcf  670  represents the time period overlap of the falling edges of signal B  500  and signal D  600 . PDIC  100  is disabled from transmitting during the time periods Dcr  665  and Dcf  670 .  
         [0029]    [0029]FIG. 7 is a flow chart illustrating when a disable pulse is generated. A disable pulse is activated based on the condition of a signal having priority value of 0. The disable pulse is generated while the signal having a priority value of 0 switches. Signals having a priority value of 1 that are adjacent or can interfere with the signal having a priority value of 0 are prevented from switching by the disable pulse. The priority value 0 signal begins transmission or is being sent and received, step  700 . A threshold value, V 1  must be reached by priority value 0 signal. V 1  in this case can be either a relative minimum or a maximum value. A relative minimum value represents a digital 0 value and a relative maximum value of 1. Switching by the priority 0 signal is made either during the rising edge or the falling edge of transmission. The disable pulse remains at a zero initial state prior to the signal reaching V 1 , step  705 . A determination is made as to whether the signal has reached V 1 , step  710 . When the disable pulse reaches V 1 , the disable pulse is generated, in specific the rising edge of the disable pulse is started, step  715 . When the priority value 0 signal reaches a voltage value of V 2 , switching of the priority value 0 signal is considered complete. V 2  can be either a relative minimum or a maximum value; however, V 2  will be a relative minimum if V 1  is a relative maximum or V 2  will be a relative maximum if V 1  is a relative minimum. When V 2  is reached, switching is complete, a determination is made as to whether V 2  has been reached, step  720 . Once V 2  is reached the disable pulse is turned off. Turning off the disable pulse is represented by generating a falling edge of the disable pulse, step  725 . The process continues until transmission of the priority value signal is complete, step  730 .  
         [0030]    Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.