Abstract:
The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
       [0001]    This invention relates to semiconductor structures, and, more particularly, to a semiconductor structure having conductive pillars. 
       2. Description of Related Art 
       [0002]    Currently, semiconductor packages contain a wire-bonding package, a flip-chip package, etc. Compared to the wire-bonding package, the flip-chip package is better to reduce the overall volume of semiconductor devices. 
         [0003]    A general flip-chip package acts as a semiconductor-chip surface by conductive bumps electrically bonded to conductive pads of the package substrate, and then fills in the primer between the role surface of the semiconductor chip and the package substrate, in order to cover the conductive bump. And, in order to increase the accuracy of counterpoint of the flip chip, the material of the conductive bump is very important. 
         [0004]    Conventional semiconductor chips provide for a technology by use of copper pillars for combination, referring to  FIGS. 1A to 1D . 
         [0005]    As shown in  FIG. 1A , a chip  10  having conductive pads  100  is provided.  FIG. 1A  shows only one conductive pad for description. The outer surface is constituted by silicon-nitride (SiN) layer  101 , which exposes the conductive pads  100  through the opening of the SiN layer  101 . Then, a dielectric layer  12  is formed on the silicon-nitride layer  101  and on the wall surface of the opening. A titanium (Ti) layer  11  is formed on all the surfaces of the dielectric layer  12  and on the conductive pads  100 . A copper (Cu) layer  13  is formed on all the surfaces of the titanium layer  11 . 
         [0006]    As shown in  FIG. 1B , a resist layer  14  is formed on the copper layer  13 , and an opening area  140  is formed on the resist layer  14 , in order to expose a portion of the copper layer  13 . Copper pillars  15  are formed on the copper layer  13  within the opening area  140 . A solder material  16  is formed on a top surface of the copper pillars  15 . 
         [0007]    As shown in  FIG. 1C , the resist layer  14  is removed, in order to expose the copper layer  13 . 
         [0008]    As shown in  FIG. 1D , the copper pillars  15  function as stopper portions in order to remove the exposed copper layer  13  and the underneath titanium layer  11  by etching. In the follow-up fabrication process, the solder bump can be formed on the copper pillars  15  and solder material  16  in order for butt joint to the package substrate (not shown). Then a reflow process is performed in order to form the conductive bump which is for immobilization and for electrical connection between the chip  10  and the package substrate. 
         [0009]    When the reflow process is performed, the copper pillars  15  would not deform so they can avoid melt and collapse. The copper pillars  15  can prevent traditional chips  10  from deviating. Thus, the copper pillars  15  in the conductive bump can increase the accuracy of counterpoint of the flip chip. 
         [0010]    However in the method of fabricating the semiconductor structure, the incident of inward etching would occur because there is isotropy if using etching liquid to etch. So when the exposed copper layer  13  and the underneath titanium layer  11  are removed by etching, the titanium layer  11  would lead to the problem of overlarge undercut (as shown in the undercut area K of  FIG. 1D ). It results in non-enough support of the copper pillars  15  and results in decreased product reliability because of the bad conductive bump. 
         [0011]    Hence, the problem of overlarge undercut which decreases product reliability in prior art is indeed a target to be solved. 
       SUMMARY OF THE INVENTION 
       [0012]    To override various deficiencies of the traditional technology, the invention herein provides a method of fabricating a semiconductor structure, comprising: providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings; forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads; forming on a portion of the metal layer a first passivation layer that has a plurality of first openings, with a portion of the metal layer exposed from the first openings; forming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings; and removing a portion of the metal layer, with a portion of the metal layer under the conductive pillars and the first passivation layer remained 
         [0013]    This invention further provides a method of fabricating a semiconductor structure, comprising: providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings; forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads, with a portion of the protective layer exposed from the metal layer; forming on a portion of the metal layer and on the protective layer a first passivation layer that covers a lateral side of the metal layer, and forming a plurality of first openings in the first passivation layer, with a portion of the metal layer exposed from the first openings; and forming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings. 
         [0014]    This invention also provides a semiconductor structure, comprising: a chip having a plurality of conductive pads and a protective layer that has protective-layer openings, with each of the conductive pads exposed from each of the protective-layer openings; a metal layer formed on the protective layer and electrically connected to the conductive pads; a first passivation layer formed on the metal layer and having a plurality of first openings, with a portion of the metal layer exposed from the first openings; and a plurality of conductive pillars formed on the exposed portion of the metal layer in the first openings and electrically connected to the metal layer. 
         [0015]    From above, this invention “semiconductor structure and fabrication method thereof” provides for the efficacy as follows. The metal layer in contact with the under portion of conductive pillars is protected by the passivation layer. So the metal layer can avoid the problem of overlarge undercut when the follow-up fabrication (e.g. etching) is processed, in order to provide for enough support of the conductive pillars. After formation of the conductive bump used for immobilization and electrical connection between the semiconductor structure and the package substrate, the product reliability can be increased because the conductive bump is good. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]      FIGS. 1A to 1D  are cross-sectional schematic diagrams illustrating a traditional method of fabricating a semiconductor structure; 
           [0017]      FIGS. 2A to 2G ″ are cross-sectional schematic diagrams illustrating a method of fabricating a semiconductor structure of an embodiment according to the present invention; and 
           [0018]      FIGS. 3A to 3F ″ are cross-sectional schematic diagrams illustrating a method of fabricating a semiconductor structure of another embodiment according to the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0019]    By the following specific examples illustrating specific embodiments of the present invention, people familiar with this skill revealed by the contents of this specification can easily understand other advantages and effectiveness of the present invention. 
         [0020]    For notice in this specification, the structures depicted in the accompanying drawings, scale, size, etc., are revealed only to match the content of the instructions for the readers to become familiar with the skills. The structures are not intended to limit the implementation and qualification of this invention. The adjustment, not technically meaningful, of any structural modification or the size ratio without affecting the efficacy of the present invention can be generated and achieve the purpose. The adjustment and modification of these should still fall within this technical content of the disclosed invention and can be obtained within the scope of coverage. At the same time, such terms as “on”, “top”, “lateral side”, “the first”, “the second” and “the third” this specification refers to are also for the apparent ease of description only. These are not to limit the scope of the present invention and so may be implemented. 
         [0021]      FIGS. 2A to 2G  are cross-sectional schematic diagrams illustrating a method of fabricating a semiconductor structure of an embodiment according to the present invention. 
         [0022]    As shown in  FIG. 2A , a chip  20  is provided that has conductive pads  200  made of aluminum (Al), for example, and a protective layer  201 . In an embodiment, the chip  20  can be one of a plurality of chips of a wafer. In  FIG. 1A , the specification is roughly described only by a chip  20  that has a conductive pad  200  and a protective layer  201 . The surface of the chip  20  is constituted with such protective layer  201  as Silicon nitride (SiN). The protective layer  201  has a protective-layer opening  2010  to expose a portion of the conductive pad  200 . However, there are many types of chip structures known to the industry so they are not necessarily described again. 
         [0023]    As shown in  FIG. 2B , a metal layer  21  made of Titanium and Copper, for example, is formed on the protective layer  201  and on the exposed portion of the conductive pads  200 . The metal layer  21  is electrically connected to the conductive pads  200 . In an embodiment, the metal layer  21  is formed by sputter. 
         [0024]    As shown in  FIG. 2C , a passivation layer  22  is formed on a portion of the metal layer  21 . The passivation layer  22  has a passivation layer opening  220 , and a portion of the metal layer  21  is exposed from the passivation layer opening  220 . The passivation layer opening  220  is positioned above the protective-layer opening  2010 , and has a width greater than or equal to a width of the protective-layer opening  2010 . 
         [0025]    In an embodiment, in addition to the metal layer  21  within the passivation layer opening  220 , the other portion of the metal layer  21  is also exposed from the passivation layer  22 . In other words, the passivation layer  22  is only formed on a portion of the metal layer  21 , such that the first passivation layer  22  between two neighboring ones of the conductive pads  200  is discontinuous. Preferably, the width of the passivation layer  22  is 5-10 μm. 
         [0026]    As shown  FIG. 2D , a resist layer  23  such as a photoresistor is formed on the metal layer  21  and on the passivation layer  22 . A resist-layer opening  230  is formed by an exposure development process, and a portion of a surface of the metal layer  21  is thus exposed. The resist-layer opening  230  is above the passivation layer opening  220 . In an embodiment, the width of the resist-layer opening  230  is greater than or equal to that of the passivation layer opening  220 , and a portion of the passivation layer  22  and a portion of the metal layer  21  within the passivation layer opening  220  are exposed. 
         [0027]    As shown in  FIG. 2E , conductive pillars  24  are formed on a portion of the passivation layer  22  within the resist-layer opening  230  and on the metal layer  21  in an electroplating process. In an embodiment, the conductive pillars  24  are copper pillars. Owing to the fact that the width of the resist-layer opening  230  is greater than that of the passivation layer opening  220 , a portion of the passivation layer  22  would be embedded into the conductive pillars  24  when the conductive pillars  24  are formed. 
         [0028]    In an embodiment, the conductive material  25  can also be formed on the top surface of the conductive pillars  24 . In an embodiment, the conductive material  25  can comprise nickel (Ni) material  250  and solder material  251 . 
         [0029]    As shown in  FIG. 2F , the resist layer  23  is removed, to expose a portion of the metal layer  21  which is not covered by the conductive pillars  24  and the passivation layer  22  as well as to expose a portion of the passivation layer  22  which is not covered by the conductive pillars  24 . 
         [0030]    As shown in  FIG. 2G , a portion of the metal layer  21  which is not covered by conductive pillars  24  and the passivation layer  22  is etched and remove, to retain the metal layer  21   a  below the conductive pillars  24  and the passivation layer  22  as well as to partially expose the protective layer  201  in order to obtain a semiconductor structure  2 . In an embodiment, the width D 1  of the metal layer  21   a  which is retaining owing to not being etched/removed is greater than the width D 2  of the conductive pillars  24 . Besides, the lateral side  211  of the non-removed/retained metal layer  21   a  is flush with the lateral side  221  of the passivation layer  22 . 
         [0031]    In the follow-up fabrication process, the solder bump can be formed on the conductive pillars  24  and conductive material  25 . The solder bump is for butt joint to the package substrate (not shown in the FIG.) and then for proceeding with the fabrication process of the reflow process. These are to form the conductive bump for immobilization and for electrical connection between the semiconductor structure and the package substrate. 
         [0032]    In another embodiment, after a chip  20  is provided as shown in  FIG. 2A , the passivation layer  26  can be formed on the protective layer  201  and the conductive pads  200 , as shown in  FIG. 2G ′. The passivation layer  26  covers the protective layer  201 , and has a passivation layer opening  260  to expose a portion of each of the conductive pads  200 . The metal layer  21  is formed by a sputtering process on the passivation layer  26  and on the exposed portion of each of the conductive pads  200  within the passivation layer opening  260 . Further fabrication process is the same as shown in  FIGS. 2C-2G  so it is not necessarily described again. 
         [0033]    In another embodiment, after the passivation layer  26  as shown in  FIG. 2G ′ is formed, a re-distribution layer (RDL)  27  is formed on the passivation layer  26  and on the exposed portion of each of the conductive pads  200  within the passivation layer opening  260 , as shown in  FIG. 2G ″. Then, the passivation layer  28  is formed on the re-distribution layer  27 . The passivation layer  28  has a passivation layer opening  280  to expose a portion of the re-distribution layer  27 . Then, the metal layer  21  is formed by a sputtering process on the passivation layer  28  and on the exposed portion of the re-distribution layer  27  within the passivation layer opening  280 . Further fabrication process is the same as shown in  FIGS. 2C-2G  so it is not necessarily described again. In an embodiment, the passivation layer openings  260  and  280  are dislocated mutually in order to achieve the purpose of moving contact location, so that the layout/wiring can be achieved with the method to be more densely packed. 
         [0034]      FIGS. 3A-3F  are cross-sectional schematic diagrams illustrating a method of fabricating a semiconductor structure of another embodiment according to the present invention. In an embodiment, a portion of fabrication process is the same as those in the embodiment as shown in  FIGS. 2A to 2G ″, so the following only shows the portion of difference without showing the same parts. 
         [0035]    As shown in  FIG. 3A , the process follows up the description as shown in  FIG. 2A . The metal material  21 ′ is formed on each of the conductive pads  200  of the chip  20  and on the protective layer  201 . Then the resist layer  29  is formed on the metal material  21 ′, and a portion of the metal material  21 ′ is exposed. The resist layer  29  is above the metal material  21 ′, and is electrically connected to each of the conductive pads  200 . 
         [0036]    As shown in  FIG. 3B , the metal material  21 ′ that is not covered by the resist layer  29 , i.e., the exposed portion of the metal material  21 ′, is removed in an etching process. The resist layer  29  is then removed, and the remaining metal material  21 ′ can be as a metal later  21   a.    
         [0037]    As shown in  FIG. 3C , the passivation layer  22  is formed on a portion of the metal layer  21   a  and on the protective layer  201  of the chip  20 . The passivation layer  22  has a passivation layer opening  220 , with a portion of the metal layer  21   a  exposed from the passivation layer opening  220 . In an embodiment, the passivation layer  22  covers the lateral side  211  of the metal layer  21   a . Preferably, the width of the passivation layer  22  is 5-10 μm. 
         [0038]    In an embodiment, in addition to the metal layer  21   a  within the passivation layer opening  220 , the passivation layer  22  also exposes a portion of the protective layer  201 . In other words, the passivation layer  22  is formed only on a portion of the metal layer  21   a  and on the protective layer  201 . The passivation layer  22  covers the lateral side  211  of the metal layer  21   a  in order for the passivation layer  22  between two neighboring ones of the conductive pads  200  to be discontinuous. 
         [0039]    In another embodiment, as shown in  FIG. 3C ′, the passivation layer  22 ′ only exposes the metal layer  21   a  within the passivation layer opening  220 . The protective layer  201  is covered by the passivation layer  22 ′, and is thus not exposed. In other words, the passivation layer  22 ′ between two neighboring ones of the conductive pads  200  is continuous. 
         [0040]    As shown  3 D, a resist layer  23  is formed as a photoresistor on the protective layer  201  of the chip  20  and on the passivation layer  2 . The resist-layer opening  230  is formed in an exposure development process, in order to expose a portion of a surface of the metal layer  21   a . The resist-layer opening  230  is above the passivation layer opening  220 . In an embodiment, the width of the resist-layer opening  230  is greater than or equal to that of the passivation layer opening  220  in order to expose a portion of the passivation layer  22  and a portion of the metal layer  21   a  within the passivation layer opening  220 . 
         [0041]    As shown in  FIG. 3E , the conductive pillars  24  and the conductive material are formed. The fabrication process is the same as shown in  FIG. 2E  so it is not necessarily described again. 
         [0042]    As shown in  FIG. 3F , after the resist layer  23  is removed, a semiconductor structure  2  can be obtained, wherein the width D 1  of metal layer  21   a  is greater than or equal to the width D 2  of the conductive pillars  24 . The difference between this embodiment and prior embodiment is shown as follows. Before the metal layer  21   a  in this embodiment is in contact with the conductive pillars  24 , this embodiment has obtained the desired metal layer  21   a  through the fabrication process of etching. This embodiment which is different from the prior embodiment is that after the conductive pillars  24  are disposed on the metal layer  21  and the resist layer  23  is removed, the wanted metal layer  21   a  can be obtained only through the etching fabrication process. 
         [0043]    In the other embodiment, after such a chip  20  is provided, as shown in  FIG. 2A , the passivation layer  26  can be formed on the protective layer  201  and each of the conductive pads  200 , as shown in  FIG. 3F ′. The passivation layer  26  covers the protective layer  201 , and has a passivation layer opening  260  to expose a portion of each of the conductive pads  200 . Furthermore, it is then to process the formation of such metal layer  21   a  as shown in  FIG. 3A  on the passivation layer  26  and on the exposed portion of each of the conductive pads  200  within the passivation layer opening  260 . Further fabrication process is the same as shown in  FIGS. 3C-3F  so it is not necessarily described again. 
         [0044]    In the other embodiment, after the passivation layer  26  as shown in  FIG. 3F ′ is formed, the embodiment can first form the re-distribution layer (RDL)  27  on the passivation layer  26  and on the exposed portion of each of the conductive pads  200  within the passivation layer opening  260 , as shown in  FIG. 3F ″. Then, the passivation layer  28  is formed on the re-distribution layer  27 . The passivation layer  28  has a passivation layer opening  280  to expose a portion of the re-distribution layer  27 . Then, it is to process the formation of such metal layer  21   a  as shown in  FIG. 3A  on the passivation layer  28  and on the exposed portion of the re-distribution layer  27  within the passivation layer opening  280 . Further fabrication process is the same as shown in  FIGS. 3C-3F  so it is not necessarily described again. In this embodiment, the passivation layer openings  260  and  280  are dislocated mutually. 
         [0045]    This invention further provides a semiconductor structure  2 , as shown in  FIG. 2G  The semiconductor structure  2  further comprises a chip  20 , a metal layer  21   a , a passivation layer  22  and conductive pillars  24 . 
         [0046]    The chip  20  has conductive pads  200  made of aluminum materials, and a protective layer  201  made of silicon nitride (SiN). The protective layer  201  has a protective-layer opening  2010  to expose a portion of each of the conductive pads  200 . 
         [0047]    The metal layer  21   a  is formed on the protective layer  201  and on the exposed portion of each of the conductive pads  200  in order to electrically connect to each of the conductive pads  200 . In an embodiment, the metal layer  21   a  are made of titanium (Ti) and copper (Cu), for example. 
         [0048]    The passivation layer  22  is formed on a portion of the metal layer  21   a . The passivation layer  22  has a passivation layer opening  220  in order to expose a portion of the metal layer  21   a  within the passivation layer opening  220 . 
         [0049]    The conductive pillars  24  are formed on the exposed portion of the metal layer  21   a  within the passivation layer opening  220 . The conductive pillars  24  electrically connect to the exposed portion of the metal layer  21   a  within the passivation layer opening  220  of the passivation layer  22 . In an embodiment, the conductive pillars  24  are copper pillars. In another embodiment, the width D 1  of the metal layer  21   a  is greater than the width D 2  of the conductive pillars  24 . The top surface of conductive pillars  24  forms the conductive material  25 . The conductive material  25  may comprise nickel (Ni) material  250  and solder material  251 . In another embodiment, the conductive material  25  may be the solder material. 
         [0050]    In an embodiment, a portion of passivation layer  22  is embedded into the conductive pillars  24 . The passivation layer  22  may also be not embedded into the conductive pillars  24 , i.e., the width D 2  of the conductive pillars  24  being equal to the width of the passivation layer opening  220 . 
         [0051]    In an embodiment, as shown in  FIG. 2G , the lateral side  211  of the metal layer  21   a  is flush with the lateral side  221  of the passivation layer  22 . In another embodiment, as shown  3 F, the passivation layer  22  covers the lateral side  211  of the metal layer  21   a.    
         [0052]    This invention further provides a semiconductor structure  2 ′, as shown in  FIGS. 2G ′ and  3 F′. The following describes the difference between the semiconductor structure  2 ′ of this embodiment and the semiconductor structure  2 . The same portions are not described again. 
         [0053]    The semiconductor structure  2 ′ further comprises the passivation layer  26  which is formed on the chip  20 , i.e., formed between the protective layer  201  and the metal layer  21 . The passivation layer  26  has the passivation layer opening  260  to expose a portion of each of the conductive pads  200  of the chip  20  and covers the protective layer  201  of the chip  20 . The metal layer  21  of the semiconductor structure  2 ′ is formed on the passivation layer  26  and on the exposed portion of each of the conductive pads  200  within the passivation layer opening  260 . 
         [0054]    This invention again provides a semiconductor structure  2 ″, as shown in  FIGS. 2G ″ and  3 F″. The following only describes the difference between the semiconductor structure  2 ″ of this embodiment and for the semiconductor structure  2 ′. The same portions are not described again 
         [0055]    The semiconductor structure  2 ″ further comprises the re-distribution layer  27  and the passivation layer  28 . The embodiment forms the re-distribution layer (RDL)  27  on the passivation layer  26  and on the exposed portion of each of the conductive pads  200  within the passivation layer opening  260 . The passivation layer  28  is formed on the re-distribution layer  27 . The passivation layer  28  has a passivation layer opening  280  to expose a portion of the re-distribution layer  27 . In this embodiment, the passivation layer openings  260  and  280  are dislocated mutually. 
         [0056]    In summary, this invention provides for the efficacy as follows. The metal layer in contact with the under portion of conductive pillars is protected by the passivation layer. So the metal layer can avoid the problem of overlarge undercut when the follow-up fabrication (e.g., etching) is processed, in order to provide for enough support of the conductive pillars. After formation of the conductive bump used for immobilization and electrical connection between the semiconductor structure and the package substrate, the product reliability can be increased because the conductive bump is good. 
         [0057]    The embodiments described above are to illustrate and explain the principles and efficacy of the invention by examples, but do not intend to limit the invention. Any person familiar with the art of this can make the modifications to the embodiments described above without violating the spirit and scope of the invention. Therefore, the scope of protection for rights about this invention should be listed in the claims shown as follows.