Abstract:
Disclosed is an output stage, and associated apparatus, for a voltage regulator that includes a clamp circuit that is operable to ensure that the output voltage recovers quickly, i.e. that the perturbation of this voltage is limited and remains within a given specification, when entering a standby mode and which is controlled in a supply independent manner.

Description:
FIELD OF THE INVENTION 
       [0001]    The invention relates to voltage regulator clamps, and in particular to a voltage regulator clamp that is operable to ensure that the output voltage recovers quickly, i.e. that the perturbation of this voltage is limited and remains within a given specification, when entering a standby mode. 
       BACKGROUND OF THE INVENTION 
       [0002]    Voltage regulators which supply the digital core logic in mobile devices (for example a camera phone) often operate in a low power ‘standby’ mode. They should be able to transition ‘gracefully’ into and out of this mode without introducing undesirable transient voltage changes and a consequent loss of data. 
         [0003]    A known type of architecture for realizing this incorporates a pair of regulators in parallel, an auxiliary (low power) PMOS output regulator which provides regulation in the low power ‘standby’ mode, and a main NMOS output regulator which handles the high load current requirement during normal operation, that is in the ‘streaming’ mode. The outputs of these two regulators are connected together. The PMOS output regulator is set to provide a slightly lower voltage than the stronger NMOS output regulator and is forced off when the latter regulator is enabled, during a transition from the ‘standby’ mode to the ‘streaming’ mode. A return to the ‘standby’ mode from the ‘streaming’ mode is completed when the NMOS output regulator is disabled and the PMOS output regulator regains control of the output. 
         [0004]    It is highly desirable for the regulated output voltage to remain within specification at all times. This requirement poses specific design challenges during the transitions between the ‘standby’ and ‘streaming’ modes of operation. In particular, during the transition from ‘streaming’ mode to ‘standby’ mode, the auxiliary regulator should turn on quickly enough, as the main regulator turns off, to take over the regulation of the output and help prevent its voltage from falling below specification. 
       SUMMARY OF THE INVENTION 
       [0005]    In a first aspect of the invention there is an output stage for an auxiliary voltage regulator operable to provide a regulated supply to an apparatus when in a standby mode comprising at least one output device having a control electrode. A clamping circuit comprises a clamping device operable to reduce voltage swings on the control electrode when the apparatus is not operating in the standby mode, therefore allowing faster switching on of the output device when the apparatus is switched into the standby mode. The clamping device is preferably controlled in a supply independent manner. 
         [0006]    The clamping device may be controlled according to the signal level on the control electrode of the output device. The clamping circuit may comprise a further device operable to force the clamping device off when the apparatus operates in the standby mode. The clamping circuit may be arranged such that a control electrode of the clamping device is controlled by an output terminal of the further device, the further device having a control electrode controlled by the signal level on the control electrode of the output device. 
         [0007]    The clamping device may be arranged to ensure that the output device is prevented from turning off completely when the apparatus is not in the standby state. The output stage may additionally comprise a current sink from the clamping circuit to allow adjustment, if helpful with feedback control, for a variation in the load current at the output of the output stage when the apparatus is in the standby mode. 
         [0008]    The output device, clamping device, and further device may comprise PMOS transistor devices, the clamping device for sinking current at the control electrode of the output device when the device is not in the standby mode. Each PMOS device may be paired with a NMOS biasing device. The clamping circuit may further comprise an offset device for providing a voltage offset at the location of the current sink. The offset device may be a transistor in a source follower configuration. 
         [0009]    The clamping circuit may be operable such that, as the apparatus switches into standby mode and the signal on the control electrode of the output device rises, the consequent action of the clamping circuit causes the clamping device to sink an increasing amount of current at the control electrode of the output device until a state of equilibrium is reached in which the output device may be prevented from switching completely off. 
         [0010]    In a further aspect, there is an auxiliary voltage regulator for providing a regulated supply to an apparatus when in a standby mode. The auxiliary voltage regulator comprises a differential amplifier circuit which outputs a control signal in accordance with a signal feedback from the voltage regulator&#39;s output and a reference signal, and an output stage. The output stage includes at least one output device having a control electrode controlled by the control signal, and a clamping circuit comprising a clamping device operable to reduce voltage swings on the control electrode when the apparatus is not operating in the standby mode, and to therefore allow faster switching on of the output device when the apparatus is switched into the standby mode. The clamping device may be controlled in a supply independent manner. 
         [0011]    The clamping circuit may be operable such that, as the apparatus switches out of standby mode and the control signal output from the differential amplifier circuit rises, the action of the clamping circuit causes the clamping device to sink an increasing amount of current at the control electrode of the output device until a state of equilibrium is reached in which the output device is prevented from switching completely off. 
         [0012]    In a further aspect, there is a mobile apparatus comprising a main voltage regulator for a main operating mode and an auxiliary voltage regulator for a standby mode. The auxiliary voltage regulator comprises a differential amplifier circuit which outputs a control signal in accordance with a signal feedback from the voltage regulator&#39;s output and a reference signal, and an output stage. The output stage includes at least one output device having a control electrode controlled by the control signal, and a clamping circuit comprising a clamping device operable to reduce voltage swings on the control electrode when the device is operating in the main operating mode, to therefore allow faster switching on of the output device when the apparatus is switched into the standby mode. The clamping may be controlled in a supply independent manner. 
         [0013]    In another aspect, there is a method for controlling the signal level on the control electrode of an output device comprised within an output stage of an auxiliary voltage regulator for operating an apparatus in a standby mode. The method comprises sinking current from the input of the control electrode in a supply independent manner when the apparatus is not operating in the standby mode, so as to reduce voltage swings on the control electrode and to therefore allow faster switching on of the output device when the apparatus is switched into the standby mode. 
         [0014]    It should be understood that the sinking of current at the input of the control electrode should also cover the sourcing of current at the input of the control electrode, depending on the characteristics of the output device, for example if the output device is a NMOS transistor, forming part of a negative voltage regulator, where the other transistor devices will also be of opposite type. 
         [0015]    The sinking current at the input of the control electrode in a supply independent manner may comprise sinking current from the input of the control electrode using a clamping device, the clamping device being controlled so as to force the clamping device off when the apparatus operates in the standby mode. The clamping device may be controlled according to the signal level on the control electrode of the output device. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0016]    Embodiments of the invention will now be described, by way of example only, by reference to the accompanying drawings, in which: 
           [0017]      FIG. 1  shows a prior art circuit for providing a quick recovery auxiliary voltage regulator; 
           [0018]      FIG. 2  shows a circuit for providing a quick recovery auxiliary voltage regulator according to a first embodiment of the invention; and 
           [0019]      FIG. 3  shows a circuit for providing a quick recovery auxiliary voltage regulator according to a second embodiment of the invention. 
       
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       [0020]      FIG. 1  shows a known PMOS output stage for an auxiliary regulator. It comprises output PMOS transistor M_OUT, capacitor C 3 , and bias transistor M_BIASOUT arranged as shown. The circuit incorporates a ‘quick recovery’ clamp PMOS transistor M 4  (with accompanying NMOS transistor M 9 ), to act as a clamp. The regulated output VOUT is taken from the drain of output transistor M_OUT, this signal also being fed back to the input of the regulator differential pair (not shown) while also controlling the gate of transistor M 4 . The output of the regulator differential pair is fed to the gate of transistor M_OUT, with transistor device M 4 &#39;s source electrode also connected here. Also shown are the power rails VDD and VSS, bias input VBIAS and power down line PDN. 
         [0021]    The purpose of this clamp is to sink the current from one half of a current mirror load of the input differential amplifier when the main regulator forces a slightly higher voltage at the output, so as to over-ride the auxiliary regulator and take control, forcing the auxiliary regulator out of its closed loop state. This helps prevent the voltage at the gate of the output transistor M_OUT from rising up to the supply voltage VDD, thereby helping to prevent the magnitude of the gate-source voltage of this output transistor M_OUT from falling much below its threshold value. Consequently, there is a reduction in the voltage excursion at the gate of the output transistor M_OUT and therefore the magnitude of the transient dip in the output voltage on re-entry into the ‘standby’ mode, when the main regulator relinquishes control of the output. 
         [0022]    When the auxiliary regulator is working normally, transistor M 4  may remain switched off. This is useful if the supply voltage VDD remains below a level given by the aggregate of output voltage VOUT and the gate-source threshold voltages of transistors M 4  and MOUT. However if supply voltage VDD is increased above this level, the gate-source voltage across transistor M 4  will increase to a value which may cause it to enter its ‘on’ state and the auxiliary regulator may in this case fail to regulate correctly. 
         [0023]      FIG. 2  shows a circuit which addresses this drawback of the circuit in  FIG. 1 . The applicant has found that the underlying cause of the limitation of the circuit of  FIG. 1 , when faced with an increased supply voltage VDD, is that the gate of the ‘quick recovery’ clamp transistor (M 4 ) is connected to output node VOUT and is therefore constrained, under closed loop conditions, to remain at a fixed level for all values of supply voltage VDD. 
         [0024]    In  FIG. 2  the gate of the clamp transistor MCLMP, is not connected to node VOUT. Instead it is connected to a bias point at the connection between the drain nodes of a PMOS/NMOS transistor pair MSENSE and MCLMBIAS placed across the supply rails VDD and VSS. The PMOS device MSENSE senses the magnitude of the gate-source voltage of the output device M_OUT and, when in standby mode, drives the voltage at the node CLAMPGATE high to force the clamp transistor MCLMP off, helping to ensure that it does not interfere with the normal operation of the auxiliary regulator. The NMOS device MCLMPBIAS is configured as a current source or conceptually as a very high value ‘pull-down’ resistor. The capacitor CLCPN is a compensation capacitor which helps ensure that the clamp circuit remains stable. 
         [0025]    During the transition out of standby mode, when the main regulator is taking control of the output VOUT, by driving this node to a slightly higher voltage, the feedback loop of the auxiliary regulator may cause the level at the DIFF_OUT node to be driven towards the supply voltage VDD. Both output device M_OUT and device MSENSE may therefore begin to turn off. As the device MSENSE turns off however, the signal at the node CLAMPGATE falls. This causes the clamp device MCLMP to turn on and sink an increasing amount of current from the DIFF_OUT node (the output of the auxiliary regulator&#39;s ‘input differential amplifier’) until a state of equilibrium is reached and the rise at node DIFF_OUT and the fall at node CLAMPGATE are arrested. The output device M_OUT may not be turned off completely in this state of equilibrium which ensures that the auxiliary regulator can recover relatively quickly to its closed loop “on”-state when required. Note that, when the main regulator is in control, the auxiliary regulator may be in an ‘open loop’ state. 
         [0026]    When the auxiliary regulator is in an ‘open loop’ state, and the output device M_OUT is not completely turned off, it is evident that the output device M_OUT may operate as a current source and provide current to the load. The magnitude of this current will depend on the extent to which M_OUT is on and can be set, for a given reference voltage VBIAS by adjusting the width-to-length ratios of one or more associated transistors. The ability to control the magnitude of the ‘open loop’ output current of the auxiliary regulator is a particularly useful feature of this circuit. It may, in particular, be exploited to control the magnitude of the ‘negative’ glitch which can occur in the regulator output voltage during a transition from the ‘streaming’ mode to the ‘standby’ mode, that is when the main regulator output falls and the auxiliary regulator regains control. 
         [0027]    If the magnitude of the load current at output node VOUT in ‘standby’ mode is known, then the auxiliary regulator can be ‘primed’, whereby its ‘open loop’ output current is set to a value which is close to but less than the ‘standby’ current. When the main regulator is disabled and its output falls, following a reduction in load current to the ‘standby’ value, the change in the magnitude of the current into the load (which the auxiliary regulator must provide as it takes control) may in this case be relatively small. As a consequence the change in the voltage across the loop compensation capacitor CCPN may also be relatively small, facilitating a fast recovery of the auxiliary regulator and a reduction in the magnitude of the ‘negative’ glitch. 
         [0028]    An additional feature of this circuit is that it lends itself to being primed for ‘minimum glitch’ by the sinking of an appropriate amount of current from its CLAMPGATE node via the optional current sink, as shown in  FIG. 2 . This feature may be used to adjust for variation in the regulator&#39;s ‘standby’ load current, by sensing its value and appropriately increasing or decreasing the current being drawn from this node, if necessary using automatic feedback control. 
         [0029]    However the voltage level at the CLAMPGATE node, for a given setting of the clamp, may cause voltage compliance issues for an associated current sink circuit.  FIG. 3  shows a variation on the circuit of  FIG. 2  to address the voltage compliance issue. It incorporates an additional source follower transistor MSF (with corresponding bias transistor MSFBIAS). The source follower transistor MSF is arranged to provide a positive offset to the voltage at the CLAMPGATE node. 
         [0030]    The above embodiments were provided for illustration only, and other embodiments and examples can be envisaged without departing from the spirit and scope of the invention. For example, while the example above describes positive output voltage regulation with a PMOS final stage, the invention is equally applicable to a negative output voltage regulation with a NMOS final stage, and all other device types reversed (PMOS to NMOS and NMOS to PMOS). In such a case it will be appreciated that the clamping device will source current at the gate of the output NMOS device to prevent it switching completely off.