Abstract:
A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

Description:
BACKGROUND 
     This disclosure relates generally to the field of semiconductor device fabrication, and more particularly to formation of complementary metal oxide semiconductor (CMOS) devices having interfacial oxide of different thicknesses on the same chip or substrate. 
     State of the art integrated circuit (IC) chips must be able to allow a wide range of on-chip voltages across devices on the chip, while increasing circuit performance and design flexibility. An increasing demand exists for providing semiconductor chips having devices, such as field effect transistors (FETs), with interfacial oxide layers of various thicknesses. Interfacial oxide thickness between the device gate and the substrate on which the device is located is a major concern in terms of reliability considerations for devices operating at different voltage levels. Device scaling trends have led to low voltage operation in devices having relatively thin interfacial oxides, such as devices that are used for memory or logic. Other applications may require a relatively thick interfacial oxide, such as driver/receiver circuitry at a chip input/output (I/O) and analog output devices. Thick interfacial oxide is necessary for high voltage devices to ensure reliability, while thin interfacial oxide is desirable for the relatively fast logic devices that use low voltages at the gate. However, the use of relatively thick interfacial oxide for lower voltage devices can cause poor device performance and significantly decrease speed. 
     Moreover, with the trend of to forming as many different circuits as possible on the same substrate, or chip, to achieve more functionality and/or improve performance, there are even more different possible combinations for different parts of circuits in the same chip to have different interfacial oxide thicknesses to achieve the optimized performance and reliability at the system level. 
     One method of forming different interfacial oxide thicknesses on the same substrate involves multiple masking, strip, and oxide formation steps. However, such an approach may significantly increase the overall manufacturing cost and degrade the reliability and yield of the manufacturing process. The interfacial oxide thickness may also be difficult to control because the thick oxide layer results from the combination of multiple oxide formation cycles. 
     Another method for providing multiple interfacial oxide thicknesses employs a nitrogen implant for retarding the oxidation rate on the thin interfacial oxide devices, while permitting a thicker oxide to grow where the nitrogen implant has been blocked. However, the use of nitrogen implants may cause problems. For example, implanting nitrogen at high doses may introduce beam damage in the channel region of FET devices. This damage in turn results in changes in the channel impurity distributions as well as introducing silicon defects which can degrade sub-threshold voltage leakage (off current), interfacial oxide breakdown voltage, and device reliability. 
     BRIEF SUMMARY 
     In one aspect, a method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide. 
     In one aspect, a semiconductor device includes a first field effect transistor (FET) and a second FET located on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer, wherein the second interfacial oxide layer of the second FET is thicker than the first interfacial oxide layer of the first FET; and a recess located in the substrate adjacent to the second FET. 
     Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Referring now to the drawings wherein like elements are numbered alike in the several FIGURES: 
         FIGS. 1A-B  are flowcharts illustrating embodiments of methods for fabrication of devices having different interfacial oxide thicknesses via lateral oxidation. 
         FIG. 2  is a cross sectional view illustrating an embodiment of devices formed on a substrate. 
         FIG. 3  is a cross sectional view illustrating an embodiment the device of  FIG. 2  after encapsulation of the thin interfacial oxide device. 
         FIG. 4  is a cross sectional view illustrating an embodiment the device of  FIG. 3  after lateral oxidation of the interfacial oxide of the thick interfacial oxide device. 
         FIG. 5  is a cross sectional view illustrating an embodiment the device of  FIG. 4  after removal of excess oxide from the substrate. 
         FIG. 6  is a cross sectional view illustrating an embodiment the device of  FIG. 2  after oxide liner deposition. 
         FIG. 7  is a cross sectional view illustrating an embodiment the device of  FIG. 6  after removal of the oxide liner from the thin interfacial oxide device. 
         FIG. 8  is a cross sectional view illustrating an embodiment the device of  FIG. 7  after nitride spacer formation. 
         FIG. 9  is a cross sectional view illustrating an embodiment the device of  FIG. 8  after partial removal of the oxide liner from the thick interfacial oxide device. 
         FIG. 10  is a cross sectional view illustrating an embodiment the device of  FIG. 9  after lateral oxidation of the interfacial oxide of the thick interfacial oxide device. 
         FIG. 11  is a cross sectional view illustrating an embodiment the device of  FIG. 10  after removal of excess oxide from the substrate. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of methods for fabrication of devices having different interfacial oxide thicknesses via lateral oxidation, and a substrate including devices having different interfacial oxide thicknesses, are provided, with exemplary embodiments being discussed below in detail. Lateral oxidation may be used to increase the interfacial oxide thickness of devices selected to have a relatively thick interfacial oxide on a substrate. Other devices selected to have a relatively thin interfacial oxide on the substrate are protected during the lateral oxidation of the thick gate oxide devices. Lateral oxidation may be performed at a relatively high temperature, which may be about  700 ° C. in some embodiments. The lateral oxidation time period may be relatively long, about an hour in some embodiments, and the lateral oxidation process may include a relatively slow ramp up to the lateral oxidation temperature. 
       FIG. 1A  illustrates an embodiment of a method  100 A for fabrication of devices having different interfacial oxide thicknesses via lateral oxidation.  FIG. 1A  is discussed with reference to  FIGS. 2-5 . In block  101 A, a plurality of devices are formed on a substrate, such as the devices shown in  FIG. 2 .  FIG. 2  shows a cross section of a chip  200  that includes a first device  207 A, including interfacial oxide  203 A, dielectric layer  204 A, gate metal  205 A, and gate silicon  206 A, and a second device  207 B, including interfacial oxide  203 B, dielectric layer  204 B, gate metal  205 B, and gate silicon  206 B. First device  207 A is a thin interfacial oxide device, and second device  207 B is a thick interfacial oxide device. The first device  207 A and second device  207 B are both located on substrate  201 , and are separated by a shallow trench isolation (STI) region  202 . Interfacial oxides  203 A-B may include but is not limited to silicon oxide (SiO 2 ) or silicon oxynitride (SiON) in some embodiments, and may be formed by growing the oxide on the substrate  201 . High-k dielectrics  204 A-B may include but is not limited to hafnium oxide (HfO 2 ), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO 2 ), zirconium silicate (ZrSiO), zirconium silicon oxynitride (ZrSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), dysprosium oxide (Dy 2 O 3 ), or mixtures or multilayers thereof, in various embodiments, and may be formed by deposition. High-k dielectric materials that allow for relatively facile diffusion of oxidizing species, such as FfO 2 , may be used in some exemplary embodiments for high k dielectrics  204 A-B. Gate metals  205 A-B may include but is not limited to titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W) in some embodiments, and may be formed by deposition. Gate silicons  206 A-B may include polysilicon or amorphous silicon in various embodiments. Substrate  201  may include but is not limited to silicon or silicon germanium. 
     In block  102 A, any devices on the substrate selected to have relatively thin interfacial oxide are encapsulated with an oxidation-resistant material. As shown in  FIG. 3 , first device  207 A, including interfacial oxide  203 A, is encapsulated by a spacer comprising an oxidation-resistant material  301 . Oxidation-resistant material  301  may include a nitride such as silicon nitride (Si 3 N 4 ), and may be formed by deposition of the oxidation-resistant material, photoresist and/or hardmask patterning followed by reactive ion etching to form the spacer, and wet removal of any oxidation-resistant material formed on the thick interfacial oxide devices, such as second device  207 B. 
     In block  103 A, lateral oxidation of the interfacial oxide  203 B of second device  207 B is performed, resulting in the device  400  as shown in  FIG. 4  including thick interfacial oxide  401  in second device  207 B. The lateral oxidation of block  103 A converts a portion of substrate  201  that is located underneath second device  207 B into interfacial oxide for second device  207 B, and also forms excess oxide in substrate  201  adjacent to second device  207 B. Conditions for the lateral oxidation of block  103 A may be chosen such that the interfacial oxide  401  grows into substrate  201  by a pre-determined amount. The lateral oxidation may be performed in a chamber at a low oxygen partial pressure at an appropriately chosen temperature in a range from about 400° C. to about 800° C. (about 700° C. in some embodiments), such that lateral diffusion of oxygen into the gate stack of second device  207 B is sufficiently rapid compared to the oxidation rate of the substrate  201  to nearly equilibrate the effective oxygen partial pressure in the stack across the second device  207 B. The lateral oxidation of block  103 A may include an initial slow temperature ramp-up in an environment that contains the low partial pressures of oxygen. The lateral oxidation time, including the relatively slow ramp up to the relatively high temperature, may be in a range from about 1 minute to about 1 day (about 1 hour in some embodiments). The lateral oxidation time and temperature may be adjusted depending on the gate length of the thick interfacial oxide devices. A high temperature and a relatively long time period for the lateral oxidation of block  103 A allows for formation of thickened interfacial oxide, such as interfacial oxide  401 , for devices having relatively large gate lengths. 
     Lastly, in block  104 A, the excess oxide formed in block  103 A adjacent to second device  207 B is removed from substrate  201 , forming recesses  501  adjacent to second device  207 B in the substrate  201 , as shown in  FIG. 5 . After the excess oxide is removed to form recesses  501 , oxidation-resistant material  301  may be removed from first device  207 A, and gate silicons  206 A-B and source/drain regions in substrate  201  adjacent to devices  207 A-B may be silicided in some embodiments; source/drain silicide for second device  207 B is formed in recesses  501 . After formation of the gate and source/drain silicide, spacers (not shown) may then be formed on both first device  207 A and second device  207 B. 
       FIG. 1B  illustrates another embodiment of a method  100 B for fabrication of devices having different interfacial oxide thicknesses via lateral oxidation, including deposition of an oxide liner to protect the gate of the second device during the lateral oxidation step.  FIG. 1B  is discussed with respect to FIGS.  2  and  6 - 11 . In block  101 B, a plurality of devices are formed on a substrate, such as the devices shown in  FIG. 2 , as discussed above with respect to block  101 A of  FIG. 1A . In block  102 B, an oxide liner  601  is formed over both the first device  207 A and the second device  207 B, as shown in  FIG. 6 . Oxide liner  601  may be formed by deposition. Then, in block  103 B, the portion of oxide liner  601  that is located on first device  207 A is selectively removed, as shown in  FIG. 7 , and spacers comprising oxidation-resistant material  801 A and  801 B are formed on both first device  207 A and second device  207 B. Oxidation-resistant materials  801 A-B may be a nitride such as Si 3 N 4 , and may be formed by deposition of the oxidation-resistant material, and photoresist and/or hardmask patterning followed by reactive ion etching to form the spacers. Oxidation-resistant material  801 A encapsulates the interfacial oxide region  203 A of first device  207 A. In block  104 B, oxide liner  601  is partially removed from second device  207 B to allow access through recess  901  to interfacial oxide  203 B, as shown in  FIG. 9 . Oxidation-resistant material  801 B prevents removal of oxide liner  601  from the gate region (including dielectric layer  204 B, gate metal  205 B, and gate silicon  206 B) of second device  207 B. 
     In block  105 B, lateral oxidation of the interfacial oxide  203 B of second device  207 B is performed, resulting in thick interfacial oxide  1001  in second device  207 B as shown in  FIG. 10 . Oxide liner  601  prevents oxidation of dielectric layer  204 B, gate metal  205 B, and gate silicon  206 B during lateral oxidation of interfacial oxide  203 B. The lateral oxidation of block  105 B converts a portion of substrate  201  that is located underneath second device  207 B into interfacial oxide for second device  207 B, and also forms excess oxide in substrate  201  adjacent to second device  207 B. Conditions for the lateral oxidation of block  105 B may be chosen such that the interfacial oxide  1001  grows into substrate  201  by a pre-determined amount. The lateral oxidation may be performed in a chamber at a low oxygen partial pressure at an appropriately chosen temperature in a range from about 400° C. to about 800° C. (about 700° C. in some embodiments), such that lateral diffusion of oxygen into the gate stack of second device  207 B is sufficiently rapid compared to the oxidation rate of the substrate  201  to nearly equilibrate the effective oxygen partial pressure in the stack across the second device  207 B. The lateral oxidation of block  105 B may include an initial slow temperature ramp-up in an environment that contains the low partial pressures of inadvertent oxygen. The lateral oxidation time, including the relatively slow ramp up to the relatively high temperature, may be in a range from about 1 minute to about 1 day (about 1 hour in some embodiments). The lateral oxidation time and temperature may be adjusted depending on the gate length of the thick interfacial oxide devices. A high temperature and a relatively long time period for the lateral oxidation of block  105 B allows for formation of thickened interfacial oxide, such as interfacial oxide  1001 , for devices having relatively large gate lengths. 
     Lastly, in block  106 B, excess oxide is removed from substrate  201 , forming recesses  1101  adjacent to second device  207 B in the substrate  201 , as shown in  FIG. 11 . After the excess oxide is removed to form recesses  1101 , oxidation-resistant material  801 A may be removed from first device  207 A, and oxide liner  601  and oxidation-resistant material  801 B may be removed from second device  207 B. Gate silicons  206 A-B and source/drain regions in substrate  201  adjacent to first and second devices  207 A-B may then be silicided in some embodiments; source/drain silicide for second device  207 B is formed in recesses  1101 . After formation of the gate and source/drain silicide, spacers (not shown) may then be formed on both first device  207 A and second device  207 B in some embodiments. 
     First device  207 A and second device  207 B are shown for illustrative purposes only; embodiments of method  100  may be used to thicken an interfacial oxide layer that is located on a semiconductor substrate for any appropriate type of device. For example, method  100  may be applied to gate-first devices such as metal-inserted poly-Si stack (MIPS) or full metal gate devices, or alternatively to replacement gate devices, in various embodiments. Further, any appropriate number of thin and thick interfacial oxide devices may be formed on the substrate. 
     The technical effects and benefits of exemplary embodiments include formation of devices with differing interfacial oxide thickness that may be applied to devices having a wide range of gate lengths. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.