Abstract:
The invention relates generally to a nanolaminate structure involving Al 2 O 3  thin films as a main component. The nanolaminate is used between a top electrode and a bottom electode to form a capacitor. The naonolaminate layer comprises alternating layers of Al 2 O 3  and TiO 2  and an interfacial layer.

Description:
STATEMENT OF GOVERNMENT INTEREST 
       [0001]    The United States Government claims certain rights in this invention pursuant to Contract No. W-31-109-ENG-38 between the United States Government and the University of Chicago and/or pursuant to DE-AC02-06CH11357 between the United States Government and UChicago Argonne, LLC representing Argonne National Laboratory. 
     
    
     FIELD OF THE INVENTION 
       [0002]    The invention relates generally to a nanolaminate structure involving Al 2 O 3  thin films as a main component. More particularly, the invention relates to a nanolaminate structure and method of manufacture of an Al 2 O 3/ TiO 2  layered structure with selected placement of an Al 2 O 3 , layer and in some cases other oxides layers, at the interface of the Al 2 O 3 -based nanolaminate structure with a metallic top and/or bottom contact layer to provide a capacitor-like structure. 
       BACKGROUND OF THE INVENTION 
       [0003]    Extensive basic and applied research is currently being performed in several industrial, national, and university laboratories around the world to develop next-generation low voltage, low energy consumption, high efficiency integrated circuits for advanced microelectronic devices. The heart of every integrated circuit, thus microelectronic devices, is the transistor. The most used transistor scheme in current microelectronic devices is the metal-oxide-semiconductor field-effect-transistor (MOSFET). 
         [0004]    For decades, the key element enabling the scaling of the Si-based MOSFET has been the material properties (and resultant electrical properties) associated with the amorphous SiO 2  layer used as a gate oxide. The use of the amorphous SiO 2  gate oxide layer offered key advantages in the processing and operation of complementary metal-oxide-semiconductor (CMOS) devices, including a stable high-quality Si—SiO 2  interface as well as superior electrical isolation properties. Until recently, CMOS devices were based on SiO 2  gates that exhibit defect charge densities of ˜10 10 /cm 2  and mid-bandgap interface state densities of ˜10 10 /cm 2 . Despite the attributes of SiO 2 , CMOS devices with gate width ≦45 nm required a 1 nm thick SiO 2  layer. The problem with such an extremely thin SiO 2  gate layer was that the electron moving from the source to the drain of the CMOS device were leaked to the gate due to quantum tunneling across the extremely thin SiO 2  gate. Therefore, the SiO 2  gate layer needed to be replaced by a high-dielectric constant (k) layer that could be as thick as 5-10 nm and still keep a high capacitance for a shorter gate because of the higher k value of the dielectric layer, based on the formula for capacitance C=k·A/t, where A and t are the area and thickness of the gate layer, respectively. 
         [0005]    For a metal-oxide layer on a p-type semiconductor, when there are no surface electronic states at the oxide-semiconductor interface (see  FIG. 1 ) nor charge accumulation in the oxide, there is no bending of the conduction and valence bands in the semiconductor, and the Fermi level in the metal and the p-type semiconductor lines up. With a small positive bias, V g , applied to the electrode, part of the gate voltage is in the oxide layer (V ox ) and the rest part is in the semiconductor (V s ), such that V g =V ox +V s ; and the electric field in the oxide layer is E ox =V ox /t, where t is the oxide layer thickness. The presence of a voltage V s  in the semiconductor leads to the extraction of electrons from a region in the semiconductor underneath the SiO 2 , gate oxide layer resulting in the establishment of a depletion layer. The name of the depletion layer is due to the fact that this layer is depleted of free electrons but populated with fixed negative donor ions of the p-type semiconductor layer. The electric field is expressed as E s =−Q/k, where k is the dielectric constant of the gate layer. Q s =−eN A d p  is the number of negatively charged acceptors per unit area in the depletion layer, where N A  is the number of acceptors and d p  is the width of the depletion layer in the p-type Si. 
         [0006]    Increasing V G  to a threshold V T  that produces enough band bending in the depletion layer results in the appearance of enough free electrons at the semiconductor-oxide interface. The voltage applied between the source and the drain then sweeps the electrons generated in the n-channel, establishing a current that corresponds to the transistor state “on”. If we make the assumption that all the gate voltage above V T  is used to accumulate electrons in the depletion layer without increasing its thickness, we can determine the number of free electrons based on the concept of charge on the plates of a capacitor. The value of the capacitance per unit area corresponding to the oxide layer is: 
         [0000]        C   ox   =k   ox   /t,   (1)
 
         [0000]    Where t is the oxide thickness and k ox  is the dielectric constant of SiO 2 . From the general relation of a capacitor VC=Q, we can calculate Q n , the charge density per unit area of electrons as: 
         [0000]        Q   n   =C   ox ( V   G   −V   T ),  (2)
 
         [0007]    For a gate voltage V G &lt;V T  there is no n-channel connection between the source and drain (i.e., the source-drain current I sd =0 irrespective of the drain voltage V D  (this is not exactly true because there is always a small leakage current across the reverse bias p-n junction). For V G &gt;V T  and V D &lt;V T  the n-type channel between the source and drain behaves like a resistor, for which the resistance R is given by: 
         [0000]        R=−L/W μ   n   Q   n   e,   (3)
 
         [0000]    where L and W are the length and width of the channel, respectively. The conductance g d  of the channel is given by: 
         [0000]        g   d   =dI   D   /dV   D ( for V   G =constant),  (4)
 
         [0000]    and for the linear regime for which I D =V D /R, g d  is given by: 
         [0000]        g   d =1 /R=eμ   n   Q   n   W/L,   (5)
 
         [0000]    where μ n  is the mobility of the electrons in the channel between the source and the drain. 
         [0008]    The actual physical thickness of a high-k layer needed to achieve the equivalent capacitance of a 1 nm thick SiO 2  layer is give by the following equation: 
         [0000]        t   high-k   =k   high-k   ·t   eq /3.9,  (6)
 
         [0000]    so a dielectric layer with a dielectric constant k=16 results in a required physical thickness of ˜4 nm to obtain a t eq =1 nm. Therefore, the higher the dielectric constant k the thicker the gate dielectric layer can be, while still possessing the equivalent oxide thickness of a 1 nm SiO 2  layer. 
         [0009]    The HfO 2  layer currently used in the first generation of commercial CMOS devices with gate width ˜45 nm exhibits a dielectric constant k=20. However, for the next generation of CMOS devices with shorter gates, there will be a need for materials with dielectric constant k≧30. A TiAlO x  alloy has been developed with k=30 and low leakage, providing an alternative gate oxide for nanoscale CMOS devices. However, the TiAlO x  alloy exhibits a bandgap of about 4 eV, which is still below the 5.5 eV bandgap needed for reliable operation of a high-k dielectric gate layer. 
         [0010]    Even, more recently, it has been demonstrated that Al 2 O 3 /TiO 2  nanolaminates exhibit dielectric constants of up to k=1000. However, the capacitive structures fabricated with those Al 2 O 3 /TiO 2  nanolaminates on Si substrates exhibit relatively high leakage, and the high dielectric constant of ˜1000 decreased rapidly below about 100 at about 1 kHz, giving only a limited frequency range of operation. The limited operation of the Al 2 O 3 /TiO 2  nanolaminates without the interfacial Al 2 O 3  layer at the top electrode/nanolaminate interface is due to the fact that there is a substantial charge injection into the nanolaminates. 
         [0011]    In early 2007, INTEL announced the deployment of HfO 2 -based high-k dielectrics in conjunction with a metallic gate for components built on 45 nm CMOS technologies, and shipped it in the 2007 processor series codenamed Penryn. However, although the first generation of nanoscale CMOS devices with high-k dielectric gates are already in the market, the dielectric constant of HfO 2  and most amorphous oxide dielectric known today is much less than 100. 
         [0012]    Another critical technological application of the Al 2 O 3 /TiO 2  nanolaminates can be a new generation of supercapacitors for energy storage in industrial applications and for biocompatible (TiO 2  and Al 2 O 3 ) energy storage capacitors embedded in microchips implantable in humans as part of biomedical devices for restoring sight to blind people, or restoring hearing to deaf people, or restoring other degraded human functions. 
       SUMMARY OF THE INVENTION 
       [0013]    A nanolaminate structure is made of Al 2 O 3 /TiO 2  multilayered thin films and an oxide layer preferably at the interface between the top electrode and the nanolaminate. The nanolaminate thin films have individual layer thicknesses in the range of about 0.1 to 1 nm and beyond, as required to achieve the combined properties of giant dielectric constant (k=100-1000 or higher), low leakage current, and low losses for extended frequency range operation. The combined properties mentioned above are achieved by inserting an Al 2 O 3 , or in selected cases can be achieved by inserting another oxide (e.g., HfO x , BaO x , TaO x , NbO x , etc.) at the interface of the Al 2 O 3 /TiO 2  nanolaminate with a metallic (e.g., Pt, Ti, W, or any other metal) bottom and/or top contact layers to produce capacitor-like structures. Such structures can be used in several new technologies for which the giant-k dielectric Al 2 O 3 /TiO 2  nanolaminate provides a critical component, namely: 1) as a gate oxide for the new generation of nanoscale CMOS transistors for integrated circuits in nanoelectronics; 2) as a dielectric layer for fabrication of high-capacitance capacitors embedded in microchips implantable in the human body (using the biocompatible properties of Al 2 O 3  and TiO 2  films); 3) as a dielectric layer for fabrication of high-capacitance capacitors for energy storage systems; 4) as a nanoscale insulator layer for magnetic multilayer memory devices; and 5) for any other application where an atomic scale thick layer with high-dielectric constant is required. A great advantage of the Al 2 O 3 /TiO 2  nanolaminates is that the individual layers are amorphous, thus being much simpler and less costly to produce on different substrates used for the fabrication of devices. The Al 2 O 3 /TiO 2  nanolaminates with the interfacial Al 2 O 3  layer at the nanolaminate/metallic contact layer solve the problem of the high leakage/losses and limited frequency range operation of the nanolaminates without the interfacial Al 2 O 3  layer, thus making the nanolaminates suitable for commercial devices. 
         [0014]    These and other advantages and features of the invention, together with the organization and manner of operation thereof, will become apparent from the following detailed description when taken in conjunction with the accompanying drawings. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  shows a schematic of a field effect CMOS transistor with a critical gate oxide layer; 
           [0016]      FIG. 2(   a ) shows a schematic of a metal-insulator capacitor structure including a TAO (Al 2 O 3 /TiO 2 ) nanolaminate structure as a dielectric layer;  FIG. 2(   b ) shows a bright field TEM image of a reference TAO sample; and  FIG. 2(   c ) shows a Ti-map obtained from an energy filtered TEM image including line scans calculated from an elemental map of Ti; 
           [0017]      FIG. 3(   a ) shows a high resolution cross-section TEM image of the TAO nanolaminate with 0.5 nm thick individual layers of Al 2 O 3  and TiO 2 ;  FIG. 3(   b ) and  FIG. 3(   c ) show, respectively, a high resolution TEM image and a corresponding schematic image of a series of Al 2 O 3 /TiO 2  nanolaminate structures; 
           [0018]      FIG. 4(   a ) shows dielectric constant versus frequency;  FIG. 4(   b ) shows loss vs. frequency;  FIG. 4(   c ) shows leakage current density vs. applied voltage as a function of a thickness of the additional Al 2 O 3  layer on top of the TAO nanolaminate;  FIG. 4(   d ) shows combined dielectric constant and loss at 100 Hz, and leakage current density at 1 V as a function of the thickness of the top Al 2 O 3  layer on TAO nanolaminate (the top Al 2 O 3  layer thickness was determined by the summation of the additional Al 2 O 3  layer thickness and 0.5 nm of Al 2 O 3  layer in TAO); and 
           [0019]      FIG. 5(   a ) shows a schematic of various positions of additional Al 2 O 3  layer to the TAO nanolaminate structure;  FIG. 5(   b ) shows leakage current density vs. applied voltage;  FIG. 5(   c ) shows dielectric constant versus frequency as a function of the position of the additional Al 2 O 3  layer to the TAO nanolaminate structure; and  FIG. 5(   d ) shows loss versus frequency as a function of the position of the additional TiO 2  layer to the TAO nanolaminate structure. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0020]      FIGS. 2(   a ),  2 ( b ),  3 ( a ) and  3 ( b ) show a nanolaminate structure  100  having a plurality of Al 2 O 3 /TiO 2  thin films  110 / 120  having layer thicknesses of about 0.1-1 nm, although greater nm thicknesses can also be used, provided combined properties of the nanolaminate structure  100  achieve a giant dielectric constant of k−100-1000 or higher, low leakage currents and low losses for extended frequency range operation. 
         [0021]    In addition to the application for the next generation of nanoscale CMOS devices, the new Al 2 O 3 /TiO 2  nanolaminates  110 / 120  can include an interfacial Al 2 O 3  layer  140  to provide a reliable dielectric layer for microchip embedded capacitors for implantable biomedical devices, and for high capacitance capacitor for energy storage systems, and for other future applications requiring high-k dielectric layers with all the properties shown for the new nanolaminates reported here. 
         [0022]    In one preferred embodiment shown in  FIG. 5(   a ) the Al 2 O 3 /TiO 2  nanolaminate structure  100  comprises alternating 0.5 nm thick TiO 2  and 0.5 nm thick Al 2 O 3  sublayers (hereinafter, TAO) synthesized by atomic layer deposition, and include most preferably a 5 nm thick form of the Al 2 O 3  interfacial layer  140  at a nanolaminate/top electrode contact  150  (hereinafter, “the top electrode contact”). The nanolaminate structure  100  exhibits a high dielectric constant (&gt;550) with significantly low loss (&lt;0.04) and leakage current density (&lt;10 −7  A/cm 2  up to 1.0 V). Without limiting the scope of the invention, the unusually high dielectric constant is attributed to the Maxwell-Wagner relaxation between conducting TiO 2  and insulating Al 2 O 3 , while the low loss and low leakage current density are likely due to blockage of leakage current by the Al 2 O 3  interfacial layer  140  at the top electrode contact  150 . 
         [0023]    The Al 2 O 3 /TiO 2  nanolaminate structure  100  is preferably grown using atomic layer deposition (ALD), which is the technique capable of growing films with atomic layer precision. All layers were grown at 300° C., although lower temperatures (100-200° C.) can also produce the Al 2 O 3 /TiO 2  nanolaminates. The ALD process uses trimethylaluminum [Al(CH 3 ) 3 ] and titanium tetrachloride (TiCl 4 ) as Al and Ti precursors, respectively, and H 2 O as the oxidant. 
         [0024]    For the preferred Al 2 O 3 /TiO 2  nanolaminate structure  100 , 5 cycles of Al 2 O 3  and 15 cycles of TiO 2  sublayers were deposited alternately to achieve equal sublayer thicknesses of 0.5 nm. A reference Al 2 O 3 /TiO 2  nanolaminate was used to precisely elucidate the effect of the Al 2 O 3  interfacial layer the between Al 2 O 3 /TiO 2  nanolaminate structure  100  and the top electrode contact  150 . Nanolaminates with additional layers associated with the top electrode contact  150 , a middle layer  170 , and a bottom Al 2 O 3  interfacial electrode contact  180  can be referred to as A-TAO, TAO-A-TAO, and TAO-A, respectively. Therefore, for example, 4.5A-TAO designates that a 4.5 nm thick Al 2 O 3  interfacial layer  140  is deposited adjacent the top electrode contact  150  of the reference TAO nanolaminate structure  100 . A Pt form of the top electrode contact  150  and the bottom electrode contact  180  can be grown by RF-magnetron sputtering, electron beam evaporation, or atomic layer deposition for both the bottom and top electrode contact  150 , using a shadow mask to define a circular or any other geometrical shape of the top Pt electrodes 150 and 180; thickness and diameter (defined by a shadow mask) of the top electrode contact  150  was 100 nm and 250 mm, respectively. Alternatively, the patterned top electrodes can be produced by growing a blanket metal film on the nanolaminate and then do lithography and reactive ion etching (RIE) to define the geometry and dimensions of the electrodes. X-ray diffraction (XRD, Philips X-Pert 8856) and Transmission Electron Microscopy (TEM, FEI Tecnai F20ST TEM/STEM) revealed that the Al 2 O 3  and TiO 2  layers of the nanolaminate structure  100  are amorphous. Dielectric properties were measured using an Agilent 4294A precision impedance analyzer at room temperature. The leakage current was measured using a Keithley 237 unit. 
         [0025]      FIG. 2(   a ) illustrates a representative Pt/TAO/Pt capacitor nanolaminate structure  220  on a TiO 2 -coated Si substrates  230 . A reference TAO nanolaminate structure  100  was terminated by 0.5 nm thick top and bottom Al 2 O 3  interfacial layers  140  with a symmetric layered structure, as depicted in  FIG. 2(   a ).  FIG. 2(   b ) shows a cross-sectional TEM image of the nanolaminate structure  220  as such an example capacitor. No discernable crystalline phases in the reference TAO structure  240  were detected by selected area electron diffraction in TEM, as well as by XRD (data not shown). Alternating Al 2 O 3  and TiO 2  sublayers 110 and 120, respectively, and their compositional variation, using Ti X-ray L line as the trace, are shown in high-resolution TEM images and component mapping, respectively, in  FIG. 2(   c ). 
         [0026]      FIG. 3(   a ) shows a high resolution cross-section TEM image of the TAO nanolaminate structure  220  with 0.5 nm thick individual layers of the Al 2 O 3  layer  110  and the TiO 2  layer  120 ;  FIGS. 3  ( b ) and ( c ) show high resolution TEM images and corresponding schematics of images of a series of the Al 2 O 3 /TiO 2  nanolaminate layers  110 / 120  with different individual layer thickness, produced to determine the optimum structure to achieve the highest dielectric constant and the lowest leakage current and losses needed for commercial devices. 
         [0027]    The effects of top Al 2 O 3  interfacial layers  140  on dielectric constant, loss, and leakage current density of the TAO nanolaminates  100  are shown in  FIG. 4 . Similar to prior results, a reference TAO nanolaminate  100  without an Al 2 O 3  (A) interfacial layer  140  showed very high dielectric constant (&gt;800) in the frequency range of 100 Hz ˜10 kHz, high leakage current density (˜10 −1  A/cm 2  at 1 V) and high loss (&gt;0.1 in 100 Hz 1 MHz), plotted as black lines in  FIGS. 4(   a )-( c ). The dielectric constant of TAO nanolaminates  100  with an “A” interface layer  140  (A-TAO) at the electrode/Al 2 O 3  interface remains high (&gt;500), when the thickness of the additional Al 2 O 3  layer  140  is less than 4.5 nm ( FIG. 4  ( a )). However, the insertion of the Al 2 O 3  interfacial layer  140  at the top electrode  150  interface produces a dramatic reduction in loss and leakage.  FIG. 4(   b ) shows that the Al 2 O 3  top layer  140  that is only 2.5 nm thick reduces the dielectric loss from &gt;1.0 to &lt;0.05 in the low frequency region. The most significant effect of the additional Al 2 O 3  interface layer  140  at the top electrode contact  150 /TAO nanolaminate  100  interface is shown in  FIG. 4  ( c ), six orders of magnitude reduction in leakage current density at 1.0 V (i.e., from ˜10 −1  to ˜10 −7  A/cm 2 ) is produced with an additional 4.5 nm thick Al 2 O 3  top layer (i.e., 4.5A-TAO). Trends of dielectric constant and loss at 100 Hz, and leakage current density at 1.0 V are plotted in  FIG. 4  ( d ). Increasing the thickness of the Al 2 O 3  interfacial layer  140  results in a gradual decrease of the dielectric constant, while the loss and leakage current density decrease exponentially. Therefore, the adequate additional thickness of the Al 2 O 3  interfacial layer  140  for optimizing the dielectric properties of the TAO nanolaminates  100  is in the range of 2.5 to 5.5 nm. In particular, it was found that the 4.5 nm thick Al 2 O 3  interfacial layer  140  can significantly reduce the leakage current density (&lt; 10   −7  A/cm 2  when voltage &lt;1.5 V) and loss (&lt;0.04 when f&lt;10 kHz) while maintaining high dielectric constant (&gt;600 when f&lt;100 kHz). 
         [0028]    It was observed that a 1.5 nm Al 2 O 3  interfacial layer  140  is too thin to block leakage current between a top electrode contact  150  and the dielectric interfacial film layer  140 . Such behavior is likely related to conduction mechanisms of ALD Al 2 O 3  ultrathin films reported in the art (but such suppositions are not meant to limit the claims) wherein direct tunneling occurred when ALD Al 2 O 3  ultrathin interfacial films  140  are thinner than 2.5 nm. It is also reported that the dielectric strength of the ALD Al 2 O 3  ultrathin films  140  could reach ˜10 MV/cm when deposited on very smooth conductive substrates. In the case, of the dielectric interfacial films  140  discussed herein, since the substrate has been coated with sputtered polycrystalline Pt films, thus exhibiting surface roughness larger than the conventional atomic scale roughness of a Si surface, the thickness of the ALD Al 2 O 3  film  140  that can effectively reduce tunneling seems to be 3.5 nm. This is probably due to high electric fields developed on nanoscale asperities resulting from the sputter-deposition process of Pt films. To further reduce the tunneling current (&lt;10 −7  A/cm 2  at 1 V), it is necessary to increase the thickness of the Al 2 O 3  interfacial layers  140  approximately to &gt;4.5 nm. 
         [0029]    The following non-limiting examples illustrate various aspects of the invention. 
       EXAMPLES 
       [0030]    In order to optimize the effect of the Al 2 O 3  interfacial layer, experiments were performed to determine the optimum position of the Al 2 O 3  interfacial layer, considering effects of surface roughness or sputter-deposition-induced topography during the electrode layer growth. In this respect, studies focused on determining the effect of inserting the 4.5 nm thick Al 2 O 3  interfacial layer at different positions in the TAO nanolaminates, as schematically depicted in  FIG. 5  ( a ). The structures investigated were: (i) 4.5A-TAO (4.5 nm Al 2 O 3  interfacial layer on the top of TAO at the top Pt electrode/TAO interface), (ii) TAO-4.5A (4.5 nm interfacial Al 2 O 3  layer at the bottom Pt electrode/TAO interface), and (iii) TAO-4.5A-TAO (4.5 nm interfacial Al 2 O 3  layer in the middle of TAO structure).  FIG. 5  ( b ) shows the leakage current density of all three TAO nanolaminates described above, including the reference TAO. The TAO-4.5A still exhibits high current density, similar to the reference TAO. In contrast, the leakage current density of TAO-4.5A-TAO and 4.5A-TAO is dramatically reduced. Because the top electrode was deposited by rf-magnetron sputter-deposition, energetic species from the plasma were created in front of the target to induce the sputtering process, thus there was ejection of Pt atoms for subsequent deposition on the TAO layer. The energetic plasma species can impact on the TAO surface, producing damage that can be destructive on the TAO film during the deposition process. Without limiting the scope of the invention, this defective interface and high surface energy state can contribute to high leakage current density. The insertion of a highly insulating and suitably thick Al 2 O 3  layer on top of the TAO, however, likely can minimize or eliminate the defective surface state of the TAO film from the sputtering process and reduce the leakage current density effectively, as shown in  FIG. 5  ( b ). The effect of the sputter-induced damage effect mentioned above was tested by growing the top Pt electrode using electron beam (e-beam) evaporation, which involves deposition of Pt atoms with ≦1 eV bombardment energy. 
         [0031]    The capacitor structures produced with the top Pt electrode deposited by e-beam evaporation result in substantial less leakage current density (not shown here) than that of the electrode produced by sputter-deposition. On the other hand, for the case of insertion of the Al 2 O 3  interfacial layer at the bottom electrode (TAO-4.5A), it does not make a big difference because the interface is very rough as seen in  FIG. 2  ( b ) and large comparative to that of the top electrode. Therefore, it is difficult to prevent the charge injection by inserting the 4.5 nm thick bottom Al 2 O 3  interface layer. In this respect, the Al 2 O 3  layer in the middle of TAO (TAO-4.5A-TAO), as insulating layer, can have a medium effect compared with the layers inserted at the between top and bottom electrode interfaces. The possibility exists for minimizing the effects of electrode interface roughness by growing the bottom and top electrodes using ALD. 
         [0032]    The present invention has the potential of providing a whole new generation of nanoelectronic devices, which require high-k dielectric layers with the combined properties demonstrated for the Al 2 O 3 /TiO 2  nanolaminates. The high dielectric constant TAO nanolaminates also provide the basis for new embedded supercapacitors in a new generation of microchips implantable in the human body, due to the biocompatibility of TiO 2  and Al 2 O 3 . Also, the TAO-based supercapacitors can provide a new generation of energy storage systems. Because the component layers are biocompatible, these nanolaminates provide a broad range of applications to both non-biologically and biologically compatible devices and systems. 
         [0033]    The foregoing description of embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the present invention. The embodiments were chosen and described in order to explain the principles of the present invention and its practical application to enable one skilled in the art to utilize the present invention in various embodiments, and with various modifications, as are suited to the particular use contemplated.