Abstract:
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Description:
FIELD 
       [0001]    This invention claims all rights and priority on prior pending U.S. patent application Ser. No. 12/828,460 filed 1 Jul. 2001. This invention relates to the field of integrated circuits. More particularly, this invention relates to an integrated circuit for switching between two clock sources without producing a glitch on the output clock line and while maintaining an exact pulse number ratio and phase alignment for the divided clocks. 
     
    
     INTRODUCTION 
       [0002]    Low power consumption and high performance are desired features in serializer-deserializer and other such systems. To provide the high performance that is needed, a phase lock loop is typically used as the system clock generator, which transmits data with very tight jitter performance. Unavoidably, the phase lock loop will consume a considerable amount of power when running at several gigahertz. However, data traffic is not always active, and there are often long periods of time when the system only needs to listen or transmit at relatively low frequencies in order to maintain the link or stand by. During these times, not only can the system clock frequency be substantially reduced, but the jitter requirement is also much less. To achieve the goal of low power consumption during such periods, a low frequency source such as a digital phase lock loop is implemented. A clock multiplexer (MUX) block is typically used to switch between these two clock sources. 
         [0003]    In a simple implementation of a clock MUX, a select signal is used to select the clock source. For example, when the select line high, then clock one is selected, and when the select line is low, then clock two is selected. However, when the select line is toggled between the synchronized rising and falling of the two clock signals, a small width pulse, called a glitch, may be generated on the output line. The glitch can also be thought of as a truncated version of one or the other of the input clocks. In other words, the glitch is any pulse on the output line that is not a wholly-formed pulse of one of the input clocks. In an ideal switching circuit, the perfectly-formed last pulse of a preceding first clock signal is followed by a perfectly-formed first pulse of a succeeding second clock signal. A glitch pulse in the system clock can cause severe problems in modern digital systems. 
         [0004]    In a typical serializer-deserializer system there are several synchronous clocks that are divided down from one common source, which are used for multiple data rates. After being multiplexed, such clocks typically required a phase alignment to maintain the exact pulse number ratio. If these multiple clocks are to be multiplexed, and it is required to concurrently maintain phase alignment and pulse ratio, the circuit becomes more complicated to implement than the simple case described above. 
         [0005]    One existing solution uses a select signal such that when clock one is to be selected, clock  2  is stopped first after one rising edge and one falling edge, then after one rising edge and one falling edge of clock one, clock one is enabled and output. An AND operation is executed after the falling edge of clock one, and an OR operation is executed after clock two is stopped so that there is no glitch on the output clock signal. 
         [0006]    The problem with this method is that both clocks must be active at the time that the clocks are multiplexed. If clock two is stopped at the time that the select signal is toggled, then clock one will be stopped and there will be no signal on the output clock. 
         [0007]    What is needed, therefore, is a system that reduces problems such as those described above, at least in part. 
       SUMMARY 
       [0008]    The above and other needs are met by a clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output. 
         [0009]    According to another aspect of the invention there is described a clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, a first switch for receiving and selecting between relatively lower frequency clock sources on the inputs, and for generating control signals for selecting between relatively higher frequency clocks on the inputs, the first switch including elements that prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output, and at least one second switch for receiving the control signals from the first switch, and for receiving and selecting between the higher frequency clock sources on the inputs, based at least in part upon the control signals received from the first switch. 
     
    
     
       DRAWINGS 
         [0010]    Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein: 
           [0011]      FIG. 1  is a circuit diagram of a clock switching circuit including a MUX, according to an embodiment of the present invention. 
           [0012]      FIG. 2  is a more detailed circuit diagram of the MUX of  FIG. 1 , according to an embodiment of the present invention. 
           [0013]      FIG. 3  is a timing diagram for the circuit of  FIG. 1 , according to an embodiment of the present invention. 
       
    
    
     DESCRIPTION 
       [0014]    The various embodiments of the present invention as described herein multiplex multiple synchronous clocks from two clock sources with glitch-free phase alignment and exact pulse ratio requirements. 
         [0015]    With reference now to  FIG. 1 , there is depicted a switching circuit  100 , including a first switch  102 , having as inputs a select line SEL, a first relatively slower clock source CK 0 _X 1 , a second relatively slower clock source CK 1 _X 1 , and reset line RESET. The first switch  102  outputs first and second clock enable lines ENCK 0  and ENCK 1 , and a first output clock line MCK-X 1  through a delay  104 . 
         [0016]    A second switch  116  has as inputs a first relatively faster clock source CK 0 _X 2  that is a multiple of CK 1 _X 1 , a second relatively faster clock source CK 1 _X 2  that is a multiple of CK 1 _X 1 . The two clock sources are each input through two separate delays  106  and  108 , the outputs of which are input to two separate AND gates  110  and  112 , which also receive as inputs the two enable lines ENCK 0  and ENCK 1  respectively. The outputs of the two AND gates  110  and  112  are input to an OR gate  114 , the output of which is a second output clock line MCK-X 2 . 
         [0017]    With reference now to  FIG. 2 , there is depicted a more detailed embodiment of the first MUX  102 . The first switch  102  can be divided into three logical sections, which are (1) a multiplexing section, (2) a control signal generation section, and (3) an enable signal generation section. 
         [0018]    The multiplexing section includes a first delay flip flop DFF 1  that receives as input SEL, CK 1 _X 1 , and a second delay flip flop DFF 2  that receives as input SEL through a first inverter INV 1 , CK 0 _X 1 , and RESET. DFF 1  and DFF 2  output respectively to AND gates AND 1  and AND 2 , which also receive as input CK 0 _X 1  and CK 1 _X 1 , respectively, and provide output to an OR gate OR 1 , the output of which is MCK-X 1 . 
         [0019]    The control signal generation section includes a second inverter INV 2  that receives as input the output from AND 1  and a third inverter INV 3  that receives as input the output from AND 2 . The output of INV 2  controls the gate electrodes of both first n-channel MOS transistor MN 1  and first p-channel MOS transistor MP 1 . The source electrode of MP 1  is VDD, and the drain electrode of MN 1  is the drain electrode of a first CMOS transistor MC 1 . The source electrode of MC 1  is logical ground GND. The drain electrode of MP 1  and the source electrode of MN 1  are tied together and input to both the gate electrode of MC  1  and a fourth inverter INV 4 . A fifth delay flip flop DFF 5  receives as input the output of INV 4 , CK 0 _X 1 , and RESET, and provides as output a signal CT 0 . 
         [0020]    Similarly, the output of INV 3  controls the gate electrodes of both second n-channel MOS transistor MN 2  and second p-channel MOS transistor MP 2 . The source electrode of MP 2  is VDD, and the drain electrode of MN 2  is the drain electrode of a second CMOS transistor MC 2 . The source electrode of MC 2  is GND. The drain electrode of MP 2  and the source electrode of MN 2  are tied together and input to both the gate electrode of MC 2  and a fifth inverter INV 5 . A sixth delay flip flop DFF 6  receives as input the output of INV 5 , CK 1 _X 1 , and RESET, and provides as output a signal CT 1 . 
         [0021]    The enable signal generation section includes a third AND gate AND 3 , which receives as input the output from DFF 1  and CT 1 . A fourth AND gate AND 4  receives as input the output from DFF 2  and CT 0 . A third delay flip flop receives as input the output from AND 3 , CK 1 _X 1 , and RESET, and provides as output ENCK 1 . Similarly, a fourth delay flip flop DFF 4  receives as input the output of AND 4 , CK 0 _X 1 , and RESET, and provides as output ENCK 0 . 
         [0022]    The first MUX  102  multiplexes the two relatively lowest frequency clocks and generates two enable signals ENCK 0  and ENCK 1  that multiplex the relatively higher frequency clocks. The enable signals ENCK 0  and ENCK 1  are toggled at the rising edge of the lowest frequency clock. Because the input clocks on the MUX  102  are synchronous, and the delay  104  is inserted on the output clock line of MUX  102 , one of the enable signal on either ENCK 0  or ENCK 1  toggles to high earlier than the rising edge of the clock, which ensures that no glitch is generated after the AND operation. 
         [0023]    Because the disable signal on either ENCK 0  or ENCK 1  changes to low earlier than the enable signal, the MUX  116  for the higher frequency clocks is also a glitch-free MUX. Because all the clocks are multiplexed before the rising edge of the lowest frequency clock, the clock paths are all matched, and the clocks from each of the two clock sources are synchronous, the phase alignment and exact number ratio requirements are also met. 
         [0024]    SEL is first synchronized at the falling edge of the clock, such that the AND operation will always be executed at the low level of the clock, which ensures that no glitch signal will be generated at the AND gate. 
         [0025]    No glitch generated at the OR gate is guaranteed by the control signal generated from the control signal generation section. When SEL is toggled from low to high, such that CK 1 _X 1  is multiplexed to the output line MCK_X 1 , SELB (the output of INV 1 ) passes through to AND 2  after one falling edge of CK 0 _X 1 , and the output of AND 2  is low, and the output of INV 3  is high. Then MP 2  is off and MN 2  is on and MC 2  is discharged to low level after some time, and the output of INV 5  is high. At the falling edge of CL 1 _X 1 , line CT 1  is high and passes through to AND 1 . Because SEL is high and passes through to AND 1 , CK 1 _X 1  is passed to the input of OR 1 , and CK 0 _X 1  is stopped earlier. Thus, there is no glitch after OR 1 . 
         [0026]    If CK 0 _X 1  is stopped when the SEL toggles high, the outputs of DFF 2  and DFF 5  will stay high due to a lack of a clock edge, but CK 0 _X 1  will be at a low level (this can be easily guaranteed from the clock source design and is also favorable for low leakage consideration), so that again there is no glitch. As long as CK 1 _X 1  is active, CT 1  will be high after several cycles, so that the clock will not be blocked if the other clock is stopped. 
         [0027]    For simplicity, only two clocks from each of the two clock sources are illustrated. However if more frequency-multiplied clocks are to be multiplexed, the design can be extended with additional instances of the MUX  116  for the additional higher frequency clocks. 
         [0028]    In this embodiment, MN 1 /MN 2  is designed to have a relatively smaller W/L ratio, so that it won&#39;t charge the gate of MC 1 /MC 2  to a low level for the half period of the high level. This reduces the size needed for MC 1 /MC 2 . MP 1 /MP 2  is designed to be a relatively larger W/L ratio, so that it can charge the gate of MC 1 /MC 2  to be high for a relatively brief period of time. So if there is an active clock, the gate voltage of MC 1 /MC 2  will always be high; otherwise, the gate voltage of MC 1 /MC 2  will be discharged to a low level after some number off clock cycles. The size of these devices is not critical when MP 1 /MP 2  is kept stronger than MN 1 /MN 2 .  FIG. 3  depicts a representative timing diagram for this embodiment. 
         [0029]    According to various embodiments of the present invention, a glitch-free MUX  102  is presented, which has robust performance against clock blocking when one clock source is stopped. Based on these designs, a clock source switching circuit is presented, which has the characteristics of glitch-free, phase alignment, maintaining exact pulse number ratio and cost-saving. This block can be widely used in current SERDES systems when the clock sources will be switched for working between low power mode and normal mode. 
         [0030]    The foregoing description of embodiments for this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.