Abstract:
An image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS  
       [0001]     The present invention is related to commonly-owned co-pending U.S. patent application Ser. No. 10/904,807 (BUR920040161US1 (17976)) filed Nov. 30, 2004 and entitled A DAMASCENE COPPER WIRING IMAGE SENSOR, the whole contents and disclosure of which is incorporated by reference as if fully set forth herein. 
     
    
     FIELD OF THE INVENTION  
       [0002]     The present invention relates to semiconductor image sensors, and particularly, to a novel CMOS (complementary metal oxide semiconductor) image sensor array structure exhibiting reduced reflectivity and increased light sensitivity, and a process for manufacturing such image sensor array.  
       DESCRIPTION OF THE PRIOR ART  
       [0003]     CMOS image sensors are beginning to replace conventional CCD sensors for applications requiring image pick-up such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption for that can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized.  
         [0004]      FIG. 1  depicts a CMOS image sensor pixel array  10  according to the prior art. As shown, the array comprises a plurality of microlenses  12 , each having a hemisphere shape, arranged on a smooth planarization layer  17 , e.g., a spin on polymer, that is formed on top of a color filter array  15  enabling formation of the microlens array. The color filter array  15  includes individual red, green and blue filter elements  25  (primary color filters) or alternately, cyan, magenta and yellow filter elements (complementary color filter). Each microlens  22  of the microlens array  12  is aligned with a corresponding color filter element  25  and comprises an upper light receiving portion of a pixel  20 . The pixel  20  includes a cell portion fabricated upon a semiconductor substrate  14  portion including a stack of comprising one or more interlevel dielectric layers  30   a - 30   c  incorporating metallization interconnect levels M 1 , M 2  Aluminum (Al) wire layers  35   a ,  35   b . Interlevel dielectric materials may comprise a polymer or SiO2, for example. As Al metallization interconnect layers  35   a ,  35   b  do not require passivation, no respective barrier layers are shown. As further shown in  FIG. 1 , each pixel cell  20  having the Al metallizations  35   a,b  further includes a final Aluminum metal level  36  that enables wire bonding to the M1 and M2 metallizations between each pixel  20 , and a final passivation layer  28  is formed above the wire bonding level  36 . This final passivation layer  28  may comprise SiN, SiO2, or combinations of these. Although not shown in detail, each pixel  20  includes a photoelectric converting device including a light sensitive element such as a photodiode  18  that performs photoelectric conversion and a CMOS transistor (not shown) that performs charge amplification and switching. Each of the pixels  20  generates a signal charge corresponding to the intensity of light received by each pixel and is converted to a signal current by the photoelectric conversion (photodiode) element  18  formed on semiconductor substrate  14 . A further barrier or capping layer, e.g., a nitride such as SiN layer  38 , is formed above unsilicided diffusion regions formed at the Si substrate  14  surface.  
         [0005]     The use of Aluminum metal levels  35   a ,  35   b  in current CMOS image sensors require a taller dielectric stack due to the increased resistivity of the Al metal. The taller the dielectric means thicker dielectric layers  30   a - 30   c  are required which results in a reduced intensity of light that reaches the pixel photoconversion element (photodiode), i.e., the sensitivity of the pixel  20  is compromised.  
         [0006]     As the semiconductor industry is staying with AlCu for the 0.18 mm node CMOS image sensor technology, it would be highly desirable to provide a CMOS image sensor having Copper (Cu) metal lines for the M1, M2 levels which would require a thinner interlevel dielectric stack thus increasing the sensitivity of the pixel array as more light will reach the photodiode. However, as passivation levels are required on Cu metals due to copper&#39;s susceptibility to oxidation and contamination, a SiN, SiC, SiCN or like passivation layer is required above the copper wires. However, as passivation layers provide a refractive index mismatch, their presence will tend to reflect light in the optical path of the pixel cell thus degrading device sensitivity.  
         [0007]     It would thus be further highly desirable to provide a CMOS image sensor and method of manufacture wherein the sensor comprises Copper (Cu) metal lines for the metallization M1, M2 levels which would enable a thinner interlevel dielectric stack and, further having respective ultra-thin barrier layer portions in the pixel cell optical path or removed from the pixel cell optical path to thereby increase the sensitivity of the pixel cell.  
       SUMMARY OF THE INVENTION  
       [0008]     It thus an object of the invention to provide an image sensor having Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. Improved photosensitivity is possible due to simple geometry; as the height is reduced, the amount of light that arrives in the correct pixel is higher for any given angle.  
         [0009]     It is a further object of the invention to resolve the refractive index mismatch problem caused by the provision of additional Copper metal passivation layers, and, at the same time, increase the sensitivity of the optical image sensors by optimizing the thickness of the dielectric layers under the lenses.  
         [0010]     It a further object of the invention to provide a method of fabricating an image sensor having Copper (Cu) metallization levels that allow for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity.  
         [0011]     A number of embodiments are described that include structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. For instance, in one embodiment, the barrier layer metal for the Cu interconnect metal wire in the array is formed to be equal to or less than 20 nm in thickness. Alternately, implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, barrier metal layer may be formed by a self-aligned electroless Cu cap deposition, i.e., self-aligned to the Cu, or by using the same mask to selectively pattern and remove the barrier in the pixel areas.  
         [0012]     According to one aspect of the invention, there is provided an image sensor including an array of pixels comprising:  
         [0013]     a semiconductor substrate including a light sensitive element formed therein at each location of a corresponding pixel in the array for receiving incident light;  
         [0014]     a first interlevel dielectric layer formed atop the substrate;  
         [0015]     at least one metal interconnect layer formed atop the first interlevel dielectric layer, the metal interconnect layer including a Cu metal wire structure formed between each light sensitive element in the array; and,  
         [0016]     a second interlevel dielectric layer formed between the Cu metal interconnect layer in the array and a top layer for receiving incident light,  
         [0017]     wherein the Cu metal interconnect layer enables thin first and second interlevel dielectric layers to shorten an optical path and thereby increase an amount of light received by each light sensitive element in the array.  
         [0018]     In one embodiment, a barrier material layer is formed atop each said Cu metal wire structure that traverses the optical path of each pixel of said array.  
         [0019]     In a further embodiment, portions of the barrier material formed atop the metal interconnect layer is selectively removed from regions that traverse an optical path of each array pixel. Further to this embodiment, there is optionally provided for each pixel of the array, a layer of light reflective material formed on pixel sidewalls, the light reflective material layers increasing an amount of light received by the light sensitive element of the pixel.  
         [0020]     According to another aspect of the invention, there is provided a method for fabricating an image sensor array of pixels, the method comprising the steps of:  
         [0021]     a. forming a corresponding light sensitive element in a semiconductor substrate for each array pixel, the element adapted to receive light incident to a respective pixel;  
         [0022]     b. forming a first interlevel dielectric layer formed atop the substrate;  
         [0023]     c. forming at least one metal interconnect layer formed atop the first interlevel dielectric layer, the formed metal interconnect layer including a Cu metal wire structure formed between each light sensitive element in the array; and,  
         [0024]     d. forming a second interlevel dielectric layer atop the Cu metal interconnect layer in the array,  
         [0025]     wherein the Cu metal interconnect layer enables formation of thin first and interlevel dielectric layers to shorten an optical path and thereby increase an amount of light received by each light sensitive element in the array.  
         [0026]     In one embodiment, a barrier material layer is formed on top each Cu metal wire structure of the metal interconnect layer in a self-aligned process.  
         [0027]     In another embodiment, a thin barrier material layer is blanket deposited atop the Cu metal wire structures and atop the first interlevel dielectric layer thereby traversing an optical path of each array pixel.  
         [0028]     In further embodiments, the thin barrier material layer is selectively removed at portions that traverse the optical path of each pixel of said array by a variety of processing including implementing one or more masks or in a self-aligned mask process. Further to these embodiments, there is optionally provided for each pixel of the array, a layer of light reflective material formed on pixel sidewalls, the light reflective material layers increasing an amount of light received by said light sensitive element of the pixel. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0029]     The objects, features and advantages of the present invention will become apparent to one skilled in the art, in view of the following detailed description taken in combination with the attached drawings, in which:  
         [0030]      FIG. 1  depicts a CMOS image sensor pixel array  10  according to the prior art;  
         [0031]      FIG. 2  illustrates, through a cross-sectional view, the image sensor array  100  according to a first embodiment of the invention;  
         [0032]      FIG. 3 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   a  formed by a method in accordance with a second embodiment of the invention;  
         [0033]      FIG. 3 ( b ) illustrates, through a cross-sectional view, an alternate second embodiment of the image sensor array  100   b  of  FIG. 3 ( a );  
         [0034]      FIG. 4 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   c  formed by a method in accordance with a third embodiment of the invention;  
         [0035]      FIG. 4 ( b ) illustrates, through a cross-sectional view, an alternate third embodiment of the image sensor array  100   d  of  FIG. 4 ( a );  
         [0036]      FIG. 5 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   e  formed by a method in accordance with a fourth embodiment of the invention;  
         [0037]      FIG. 5 ( b ) illustrates, through a cross-sectional view, an alternate fourth embodiment of the image sensor array  100   f  of  FIG. 5 ( a );  
         [0038]      FIG. 6 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   g  formed by a method in accordance with a fifth embodiment of the invention;  
         [0039]      FIG. 6 ( b ) illustrates, through a cross-sectional view, an alternate fifth embodiment of the image sensor array  100   h  of  FIG. 6 ( a );  
         [0040]      FIG. 7 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   i  formed by a method in accordance with a sixth embodiment of the invention;  
         [0041]      FIG. 7 ( b ) illustrates, through a cross-sectional view, an alternate sixth embodiment of the image sensor array  100   j  of  FIG. 6 ( a ); and,  
         [0042]      FIG. 8  illustrates, through a cross-sectional view, alternate embodiments of the image sensor array of the invention incorporating a self-aligned mask process to selectively deposit a barrier material on the Cu metallizations. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0043]      FIG. 2  illustrates, through a cross-sectional view, a back end of line image sensor array stack  100  according to a first embodiment of the invention. While the upper light receiving portion of the pixels  20  (microlens and color filters) are the same as the prior art depicted in  FIG. 1 , the invention includes the formation of Cu metallization interconnects M 1 , M 2  allowing for the formation of thinner stack of interlevel dielectric layers  130   a - 130   c  formed on the substrate  14 . The substrate  14  may be a bulk semiconductor including, for example, Si, SiGe, SiC, SiGeC, GaAs, InP, InAs and other III-V compound semiconductors, II-V compound semiconductors, or layered semiconductors such as silicon-on-insulators (SOI), SiC-on-insulator (SiCOI) or silicon germanium-on-insulators (SGOI). Preferably, the interlevel dielectric material may comprise an organic or inorganic interlevel dielectric (ILD) material which may be deposited by any of number of well known techniques such as sputtering, spin-on, or PECVD and may include a conventional spun-on organic dielectrics, spun-on inorganic dielectrics or combinations thereof which have a dielectric constant of about 4.2 or less. Suitable organic dielectrics that can be employed in the present invention include dielectrics that comprise C, O, F and/or H. Examples of some types of organic dielectrics that can be employed in the present invention include, but are not limited to: aromatic thermosetting polymeric resins, for example, resins sold by DOW Chemical Company under the tradename SiLK®, Honeywell under the tradename Flare®, and similar resins from other suppliers, and other like organic dielectrics. The organic dielectric employed as interlevel dielectric layers may or may not be porous, with porous organic dielectric layers being highly preferred due to the reduced k value. Suitable inorganic dielectrics that may be employed as the interlevel dielectric typically comprise Si, O and H, and optionally C, e.g., SiO2, FSG (fluorosilicate glass), SiCOH, SiOCH, carbon-doped oxides (CDO), silicon-oxicarbides, organosilicate glasses (OSG) deposited by plasma enhanced chemical vapor deposition (CVD) techniques. Illustrative examples of some types of inorganic dielectrics that can be employed include, but are not limited to: the silsesquioxane HOSP (sold by Honeywell), methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), MSQ-HSQ copolymers, SiO2 deposited using tetraethylorthosilicate (TEOS) or SiH4 as a silicon source and O2, N2O, NO, etc. as an oxidizer; organosilanes and any other Si-containing material. For purposes of discussion it is assumed that the inorganic dielectric material is SiO2.  
         [0044]     Referring to  FIG. 2 , the methodology for forming the M1 layer includes first depositing the SiO2 dielectric layer  130   c , e.g., to a thickness ranging between about 2 k{acute over (Å)} to 20 k{acute over (Å)} with a range of between 4 k{acute over (Å)} and 5 k{acute over (Å)} preferred, on top of the substrate capping layer  38 , patterning trenches in the SiO2 layer  130   c  using known lithography and RIE techniques, and, lining the formed trenches with a metal liner such as one or more refractory metals, e.g., Ta, TaN, TiN, TiSiN, W, WCN, Ru. Then, the lined trenches are filled with a copper material to form the Cu M1 layer  135   b  which is subsequently polished using known CMP technique. Thereafter, a barrier or Cu diffusion layer  132   b , such as SiN, is deposited on top of the Cu M1 metallization, e.g., to a thickness ranging between about 20 {acute over (Å)} to 2 k{acute over (Å)} with a range of between 100 {acute over (Å)} and 200 {acute over (Å)} preferred. In this embodiment, the thickness of the nitride layer  132   b  on top of the Cu interconnect is reduced to minimize reflectance. It is understood that other barrier layers materials may be used including, but not limited to, SiON, SiC, SiCN, SiCON, SiCO materials etc. The process is repeated for the subsequent Cu M2 metallization layer whereby a thin M2 dielectric layer  130   b , e.g., SiO2, is deposited over the Cu diffusion layer  132   b , to a thickness ranging between about 2 k{acute over (Å)} to 20 k{acute over (Å)}, preferably 1 micron, and then the M2 metallization layer is formed by patterning trenches in the SiO2 layer  130   b  using known lithography and RIE techniques, lining the formed trenches with a metal liner such as a refractory metal, and, filling the lined trenches with a copper material to form the Cu M 2   135   a  layer which is subsequently polished using known CMP technique. Thereafter, a barrier or Cu diffusion layer  132   a , such as SiN, is deposited on top of the Cu M2 layer  135   a , e.g., to a thickness ranging between about 20 {acute over (Å)} to 2 k{acute over (Å)}. The subsequent steps include forming the interlevel dielectric layer  130   a  on top of the diffusion layer  132   a  and the final Al metallization according to known techniques. It is preferred that, in the embodiment depicted in  FIG. 2 , the total thickness of both the M1 and M2 diffusion barriers be about 20 nm or less, in order to minimize reflectance. Further to the embodiment depicted in  FIG. 2 , it should be understood that an additional layer of materials with an index of refraction that is in between that of SiN (1.98) and SiO2 (1.46), such as SiON, can be formed on top of the thin SiN layers  132   a,b  to comparable thicknesses (e.g., about 20 {acute over (Å)} to 2 k{acute over (Å)}) to further reduce reflections. According to this first embodiment, the provision of Cu metallization and corresponding thin interlevel dielectric layers  130   a - 130   c  and minimum diffusion barrier layers  132   a,b  in the optical path minimizes light reflectance, thus allowing greater amounts of light  13  to flow through the optical path of pixel  20  and reach underlying photodiode  18 . As further shown in  FIG. 2 , in an alternate embodiment, each the pixel array  100  may include an additional STI isolation dielectric region  138  formed in the substrate on top of the light sensitive element, e.g., photodiode  18 . In this alternate embodiment, the bottom nitride capping layer  38  is removed from the pixel optical path.  
         [0045]     In a second embodiment of the invention, there is performed a selective removal of those portions of the barrier SiN layers  132   a,b  formed in the pixel array optical paths to avoid the refraction index mismatch problem. In this second embodiment of the image sensor array  100   a , depicted in  FIG. 3 ( a ), additional masks (a resist mask or a hardmask) are used at each level of processing to create openings  50  in the SiN barrier layers  132   a,b  at the location of each pixel&#39;s optical path. That is, after each respective barrier layer  132   a,b  is formed, an additional lithography patterning and etching step (wet or dry etch) is implemented to open up the SiN at the select locations. It is understood however, that a maskless process may be implemented for removing select portions of the SiN layers  132   a,b , e.g., using clustered ion beam etching. Preferably, a fluorine-based dry etch (e.g., CF4 plus an oxygen plasma), however, a wet etch is desirable to minimize damage or roughness at the surface after the etch (which might cause reflections or scattering of the light). The wet etch may comprise of a dilute HF “smoothing” etch after SiN RIE, or it could be an H3PO4 etch to remove the SiN, using SiO2 as a hardmask. Thus, in this embodiment, process steps of forming the interlevel dielectric layer  130   b , the Cu M1 metallization layer  135   b , and corresponding SiN barrier layer deposition  132   b  is conducted, and selective removal of the barrier SiN layer  132   b  in the pixel array is performed. These process steps are then repeated for the subsequent M2 dielectric  130   b , metal layer M 2  and barrier layer  132   a . After the M1 SiN barrier layer  132   b  is etched, however, the surface of that layer may not be perfectly flat which may compromise the subsequent formed M2 dielectric and, potentially effect the lithography or the polishing of the subsequent Cu for the subsequent M2 level  135   a . Thus, after the SiO2 layer  130   b  for M2 is patterned and deposited, an additional polishing step is performed at the surface of the SiO2 dielectric  130   b  level before the M2 metallization  135   a  is patterned. It is further shown in the embodiment depicted  FIG. 3 ( a ) that the thin top nitride layer  28  and nitride capping layer  38  shown on top of the substrate  14  (each ranging between about 20 {acute over (Å)} to 2 k{acute over (Å)} in thickness) remain without affecting the pixel array sensitivity assuming the photodiode element  18  is situated in an active area directly in the silicon substrate without provision of an dielectric insulator layer  138 , e.g., an STI isolation, in the substrate  14  formed on top of the photodiode  18 .  
         [0046]     Thus, in an alternate second embodiment of pixel array  100   b  depicted in  FIG. 3 ( b ), for the embodiment including STI isolation dielectric regions  138  formed on top of the light sensitive element, e.g., photodiode  18 , it is advantageous to remove the substrate capping layer  38  in the optical path on top of the substrate  14  image sensor array  100   a  in addition to the M1 and M2 level dielectrics  132   a,b  in the optical path. Thus, in the manner described herein with respect to  FIG. 3 ( a ), an additional mask is required and additional lithographic patterning and etching steps (wet or dry etch) implemented to provide additional openings  50   a  in the SiN capping layer  38  at the locations of the pixel&#39;s optical path.  
         [0047]      FIG. 4 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   c  according to a third embodiment of the invention which corresponds to the image sensor embodiment depicted in  FIG. 3 ( a ) without the STI regions  138  above the pixel&#39;s light sensitive element (photodiode)  18  in the substrate  14 . According to this embodiment, the substrate capping layer  38 , interlevel dielectric layer  130   a , interlevel metallization  135   b  (M 1 ) and corresponding barrier layer  132   b , e.g., SiN, are formed without the M1 barrier etching. Then, the M2 dielectric layer  130   b , metallization M 2   135   a  and corresponding barrier layer  132   a , e.g., SiN, are formed. A mask is subsequently patterned and an etch is conducted to create an opening  51  to remove that portion of the Nitride barriers  132   a  for the M2 layer from the pixels&#39; optical paths. However, in the same etch process step, the M2 dielectric layer  130   b  and the M1 barrier opening  51   a  is created so that the only one mask is needed to remove both metallization barrier layers  132   a,b  in the optical path. After this etch, the interlevel dielectric (e.g., oxide) is deposited back into the etched path, e.g. a spin-on SiO2 refill process, and a planarization step is performed. It is understood that the fill dielectric may alternately comprise a polymer dielectric (polyimide, Dow Chemical&#39;s SiLK®, etc.) and that other techniques for depositing the interlevel dielectric (oxide, SiO2, or carbon-based oxides, etc.) having excellent gap fill capability such as CVD or (plasma enhanced) PE-CVD processing may be used.  
         [0048]     In an alternate third embodiment depicted in  FIG. 4 ( b ), where the image sensor array  100   d  includes STI isolation dielectric regions  138  formed on top of the light sensitive element, e.g., photodiode  18 , it is advantageous to remove the bottom nitride layer  38  shown on top of the substrate  14  in addition to the M1 and M2 level dielectrics  132   a,b . Thus, in the manner described herein with respect to  FIG. 4 ( a ), after formation of the M2 barrier level  132   a , a lithographic patterning of a single mask is performed and an etch is conducted to create openings  51 ,  51   a  and  51   b  in each of the barrier levels in the pixel&#39;s optical path. That is, the etch is conducted to remove the M2 Nitride barrier, and at the same time the M2 dielectric layer  130   b , the M1 barrier, the M1 dielectric layer  130   c  and, the additional bottom nitride layer using the preferred dry etch techniques described herein (e.g., CF4 and O2 plasma). It is understood that a wet etch may be optionally performed to remove the barrier layer materials. Thereafter, the etched path is again filled with an interlevel dielectric, e.g. a spin-on SiO2 or polymer dielectric (polyimide, Dow Chemical&#39;s SiLK®, etc.) refill process, and a planarization step is performed. It is understood that other techniques for depositing the interlevel dielectric (oxide, SiO2, or carbon-based oxides, etc.) having excellent gap fill capability such as CVD or (plasma enhanced) PE-CVD processing may be used.  
         [0049]      FIG. 5 ( a ), through a cross-sectional view, illustrates the image sensor array  100   e  according to a fourth embodiment of the invention which corresponds to the image sensor embodiment depicted in  FIG. 3 ( a ) without formed dielectric (e.g., STI) regions  138  above the pixel&#39;s light sensitive element (photodiode)  18  in the substrate  14 . According to this embodiment, the substrate capping layer  38 , interlevel dielectric layers  130   a - 130   c , interlevel metallizations  35   a ,  35   b  (M 2  and M 1 ) and corresponding barrier layers  132   a,b , e.g., SiN, are formed. However, after the formation of the top interlevel dielectric layer  130   a , a lithographic patterning and application of a single mask is performed and an etch is conducted to create openings  52  and  52   a  in each of the respective M2 and M1 barrier levels in the pixel&#39;s optical path. That is, in a single etch step, each of the barrier layers  132   a,b  for each of the metallizations are removed in addition to each of the interlevel dielectric layers  130   a - 130   c  (using a single mask). Further, in this embodiment, after opening the hole in the optical path and prior to filling the hole with the interlevel dielectric (e.g., oxide), a thin nitride liner  140  is deposited that conforms to the sidewalls and bottom of the etched hole. Preferably, a SiN material or a thin liner material having light reflective properties may be deposited to line the bottom and sidewalls of the etched opening using known deposition techniques such as PE-CVD. For example, other liner materials having light reflective properties include but are not limited to: SiC, certain metals, e.g. Al, TiN, Tungsten, Ru, Poly-Si, Poly-Ge, etc. This thin liner  140  may be deposited to a thickness ranging between 50 {acute over (Å)} to 2 k{acute over (Å)} and effectively functions to prevent mobile ion ingress and additionally act as a mirror surface to reflect scattered light so that any light that enters the lens at an angle will reach the photodiode. In a subsequent step, after depositing the thin nitride liner, the interlevel dielectric material is deposited back into the lined hole utilizing, e.g. a spin-on SiO2 refill process, and a final planarization step is performed.  
         [0050]     In an alternate fourth embodiment depicted in  FIG. 5 ( b ), where the image sensor array  100   f  includes STI isolation dielectric regions  138  formed on top of the light sensitive element, e.g., photodiode  18 , it is advantageous to remove those portions of the bottom nitride layer  38  shown on top of the substrate  14  in the pixel optical path in addition to the M1 and M2 level barriers  132   a,b . Thus, in the manner described herein with respect to  FIG. 5 ( a ), after lithographically patterning and applying a single mask, a single etch is conducted to create openings  52 ,  52   a  and  52   b  in each of the barrier levels in the pixel&#39;s optical path. That is, the single etch process is conducted to remove the M2 Nitride barrier, and at the same time the M2 dielectric layer  130   b , the M1 barrier, the M1 dielectric layer  130   c  and, the additional bottom nitride layer  38  using the preferred dry etch techniques described herein (e.g., CF4 and O2 plasma). It is understood that a wet etch may be performed to remove the barrier layer materials. Then, after opening the hole in the optical path and prior to filling the hole with the interlevel dielectric, thin nitride spacers  141  are deposited that conforms to the sidewalls and bottom of the etched hole. Preferably, a SiN material or a thin liner material having light reflective properties may be deposited to line the hole using known deposition techniques. Thereafter, the reflective liner material conforming to the bottom of the hole is removed by a spacer etch, i.e., any directional etch that is used to form SiN spacers along the sidewalls of an etched opening. For example, a F-based directional etch is used to form SiN spacers. In a subsequent step, after depositing the thin nitride and etching to form spacers  141 , the interlevel dielectric material is deposited back into the lined hole utilizing, e.g. a spin-on SiO2 refill process, and a final planarization step is performed.  
         [0051]      FIG. 6 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   g  according to a fifth embodiment of the invention which corresponds to the image sensor embodiment depicted in  FIG. 3 ( a ) without the formed STI regions above the pixel&#39;s light sensitive element (photodiode)  18  in the substrate  14 . According to this embodiment, the substrate capping layer  38 , interlevel dielectric layers  130   a - 130   c , interlevel Cu metallizations  135   a ,  135   b  (M 2  and M 1 ) and corresponding barrier layers  132   a,b , e.g., SiN, are formed. Additionally formed is the top metal conductor (i.e., Aluminum) layer  36  patterned as shown in  FIG. 6 ( a ) between each pixel. However, after the patterning of the top Aluminum layer  36 , a single etch process is conducted to create openings  53  and  53   a  in each of the respective M2 and M1 barrier levels in the pixel&#39;s optical path. That is, in the single etch step, each of the barrier layers  132   a,b  for each of the metallization levels are removed, in addition to each of the interlevel dielectric layers  130   a - 130   c  using the patterned Al layer  36  which functions as a self-aligned mask. Then, in a subsequent step, the interlevel dielectric material is deposited back into the etched hole utilizing, e.g. a spin-on SiO2 refill process, and a final planarization step is performed.  
         [0052]     In an alternate fifth embodiment depicted in  FIG. 6 ( b ), where the image sensor array  100   h  includes STI isolation dielectric regions  138  formed on top of the light sensitive element, e.g., photodiode  18 , it is advantageous to remove those portions of the bottom nitride layer  38  shown on top of the substrate  14  in the pixel optical path in addition to the M1 and M2 level barriers  132   a,b . Thus, in the manner described herein with respect to  FIG. 6 ( a ), after lithographically patterning the Al layer  36  that additionally functions as a single self-aligned mask, a single (wet or dry) etch is conducted to create openings  53 ,  53   a  and  53   b  in each of the barrier levels in the pixel&#39;s optical path. That is, the etch is conducted to remove the M2 Nitride barrier, and at the same time the M2 dielectric layer  130   b , the M1 barrier, the M1 dielectric layer  130   c  and, the additional bottom nitride layer  38  using the preferred dry etch techniques described herein (e.g., CF4 and O2 plasma). It is understood that a wet etch process may be performed to remove the barrier layers  132   a,b  and capping layer  38 .  
         [0053]      FIG. 7 ( a ) illustrates, through a cross-sectional view, the image sensor array  100   i  according to a sixth embodiment of the invention which corresponds to the image sensor embodiment depicted in  FIG. 3 ( a ) without the STI regions above the pixel&#39;s light sensitive element (photodiode)  18  in the substrate  14 . According to this embodiment, the substrate capping layer  38 , interlevel dielectric layers  130   a - 130   c , interlevel metallizations  135   a ,  135   b  (M 2  and M 1 ) and corresponding barrier layers  132   a,b , e.g., SiN, are formed. Additionally formed is the top metal conductor (i.e., Aluminum) layer  36  patterned as shown in  FIG. 7 ( a ) between each pixel. However, after the patterning of the top Aluminum layer  36 , a single etch process is conducted to create openings  54  and  54   a  in each of the respective M2 and M1 barrier levels in the pixel&#39;s optical path. That is, in the single etch step, each of the barrier layers  132   a,b  for each of the metallization levels are removed in addition to each of the interlevel dielectric layers  130   a - 130   c  using the patterned Al layer  36  which functions as a self-aligned mask. Further, in this embodiment, after opening the hole in the optical path and prior to filling the hole with the interlevel dielectric (e.g., oxide), a thin nitride liner  140  is deposited that conforms to bottom and sidewalls of the etched hole. Preferably, a SiN material or a thin liner material having light reflective properties may be deposited to line the hole using known deposition techniques such as PE-CVD, as described. This thin reflecting liner  140  may be deposited to a thickness ranging between 50 {acute over (Å)} to 2 k{acute over (Å)} and effectively acts as a mirror surface to reflect scattered light so that any light that enters the pixel lens at an angle will reach the photodiode. In a subsequent step, after depositing the thin nitride liner, the interlevel dielectric material is deposited back into the lined hole utilizing, e.g. a spin-on SiO2 refill process, and a final planarization step is performed.  
         [0054]     In an alternate sixth embodiment depicted in  FIG. 7 ( b ), where the image sensor array  100   j  includes STI isolation dielectric regions  138  formed on top of the light sensitive element, e.g., photodiode  18 , it is advantageous to remove those portions of the bottom nitride layer  38  shown on top of the substrate  14  in the pixel optical path in addition to the M1 and M2 level dielectrics  132 . Thus, in the manner described herein, after lithographically patterning the Al layer  36  that additionally functions as a single self-aligned mask, a single (wet or dry) etch is conducted to create openings  54 ,  54   a  and  54   b  in each of the barrier levels in the pixel&#39;s optical path. That is, the etch is conducted to remove the M2 Nitride barrier, and at the same time the M2 dielectric layer  130   b , the M1 barrier, the M1 dielectric layer  130   c  and, the additional bottom nitride layer  38  using the preferred dry etch techniques described herein (e.g., CF4 and O2 plasma). It is understood that a wet etch process may be performed to remove the barrier layers  132   a,b  and capping layer  38 . Further, in this embodiment, after opening the hole in the optical path and prior to filling the hole with the interlevel dielectric (e.g., oxide), thin nitride spacers  141  are deposited that conform to the sidewalls of the etched hole. Preferably, a SiN material or a thin liner material having light reflective properties may be deposited to line the hole using known deposition techniques such as PE-CVD, as described. This thin reflecting spacer  141  may be deposited to a thickness ranging between 50 {acute over (Å)} to 2 k{acute over (Å)} and effectively acts as a mirror surface to reflect scattered light so that any light that enters the lens at an angle will reach the photodiode. In a subsequent step, after depositing the thin nitride spacers, the interlevel dielectric material is deposited back into the lined hole utilizing, e.g. a spin-on SiO2 refill process, and a final planarization step is performed.  
         [0055]     It should be understood that in each of the embodiments described herein with respect to FIGS.  3 ( a )- 7 ( b ) a self-aligned Cu metal cap, e.g., CoWP, may be formed, for example, by electroless plating, rather than forming a blanket SiN cap and removing the select portions of the barrier levels  132   a,b  in the optical paths as described. Thus, as shown in  FIG. 8 , after the patterning formation of each Cu metallization layer and polishing thereof, an electroless plating may be performed in a self-aligned process to selectively deposit a barrier material  142 , e.g., a compound such as NiWP, CoWP, CoWB directly on the Cu which protects the Cu against oxidation. Alternately, a deposition process, e.g., a CVD may be performed for selectively depositing a barrier layer material such as a refractory metal including but not limited to W. Alternately, after each Cu CMP step, the Cu is recessed by either a wet etch, electropolishing, or dry etch. Then, a blanket capping layer (Ta, TaN, W, SiN, SiC) is deposited and a polishing step conducted to remove those capping layer portions formed in the regions between the metal lines.  
         [0056]     While there has been shown and described what is considered to be preferred embodiments of the invention, it will, of course, be understood that various modifications and changes in form or detail could readily be made without departing from the spirit of the invention. It is therefore intended that the invention be not limited to the exact forms described and illustrated, but should be constructed to cover all modifications that may fall within the scope of the appended claims.