Abstract:
A frequency compensated operational amplifier includes: an input stage, for receiving an input signal; an output stage, coupled to the input stage, for generating an output signal according to an output of the input stage; a first current source, for providing a first bias current; a second current source, for providing a second bias current identical to the first bias current; an Ahuja compensation circuit, comprising: a matched transistor pair, coupled to the first current source and the second current source; a capacitor coupled between the matched transistor pair and the output stage; and a transconductance boosting circuit, coupled to the matched transistor pair, for boosting transconductance of the matched transistor pair.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an Ahuja compensation scheme, and in particular, an Ahuja compensated operational amplifier that eliminates the bias problem inherent in previous implementations. 
     2. Description of the Prior Art 
     The Ahuja frequency compensation scheme is a well-known frequency compensation for operational amplifiers. The Ahuja frequency compensation was developed to improve upon the well-known Miller compensation, which consists of coupling a capacitor across an output stage of an operational amplifier. The Ahuja frequency compensation implements an indirect coupling of this capacitor, by providing a third stage consisting of a compensating transistor coupled to the capacitor. 
     For a clearer representation of the Miller compensation and Ahuja compensation, please refer to  FIG. 1 .  FIG. 1  is a diagram representing a Miller compensation scheme  100  and an Ahuja compensation scheme  200 . As can be seen from the diagram, the Ahuja compensation scheme  200  implements a compensating transistor g m3  coupled to the capacitor C C  and to a bias voltage V BIAS . The transistor itself is supplied with a bias current I BIAS . The benefits of the Ahuja compensation over the Miller compensation are a better ability to cope with high resistive and capacitive loading, reduced size of the capacitor C C , and better PSRR (power supply rejection ratio). 
     Please refer to  FIG. 2 .  FIG. 2  shows the Ahuja compensation  200  in  FIG. 1  implemented in a related art two stage operational amplifier  300 . The operational amplifier  300  comprises an input stage coupled to a differential current source, the input stage comprising transistors MP 5 , MP 1   a , MP 1   b , MN 1   a  and MN 1   b . The input stage is coupled to an output stage comprising transistors MP 2  and MN 2 , and coupled between a supply voltage V DD  and ground. The compensating transistor MP 3  is coupled to bias voltage V BP2  and compensating capacitor C C . MP 3  is further coupled to MP 4  which is coupled between V DD  and bias voltage V BP1  for supplying MP 3  with the bias current I BIAS . The circuit further comprises transistors MN 3  and MN 4 , which are coupled to MP 3 , MN 2 , MN 1   b , and respectively coupled to bias voltages V BN1  and V BN2 . The purpose of MN 3  and MN 4  is to provide a path for the current I BIAS  in MP 3  and MP 4  to ground. 
     The disadvantage of this circuit is that MN 3  and MN 4  must be biased using VBN 1  and VBN 2  to carry exactly the current I BIAS  in MP 3  and MP 4  biased separately using VBP 2  and VBP 1 . Since it is not practically possible to bias a p-channel transistor and an n-channel transistor separately to carry exactly the same current, this objective is never met. The consequence of this is that the DC offset voltage of the operational amplifier is high. 
     Furthermore, the Ahuja compensation scheme  200  illustrated in  FIG. 1  does not achieve the desired benefits under certain conditions such as light capacitive loading. Therefore, both the original Ahuja compensation  200  and the Ahuja compensated operational amplifier  300  need to be improved. 
     SUMMARY OF THE INVENTION 
     With this in mind, the present invention aims to provide an updated Ahuja compensation scheme that has good compensation under a variety of conditions, and an implementation of this updated scheme in an operational amplifier that does not have the bias problem inherent in previous implementations. 
     A first embodiment of a frequency compensated operational amplifier comprises: an input stage, for receiving an input signal; an output stage, coupled to the input stage, for generating an output signal according to an output of the input stage; a first current source, for providing a first bias current; a second current source, for providing a second bias current identical to the first bias current; an Ahuja compensation circuit, comprising: a matched transistor pair, coupled to the first current source and the second current source; a capacitor coupled between the matched transistor pair and the output stage; and a transconductance boosting circuit, coupled to the matched transistor pair, for boosting transconductance of the matched transistor pair. The matched transistor pair comprises: a first transistor, having a control node coupled to a first bias voltage, a first node coupled to the first current source, and a second node; and a second transistor, having a control node coupled to the first bias voltage, a first node coupled to the second current source, and a second node, wherein the second nodes of the first and second transistors are coupled across the input stage. The transconductance boosting circuit comprises: a first amplifier, having an output node coupled to the control node of the first transistor, a first input node coupled to the first node of the first transistor, and a second input node coupled to a second bias voltage; and a second amplifier, having an output node coupled to the control node of the second transistor, a first input node coupled to the first node of the second transistor, and a second input node coupled to the second bias voltage. 
     In a second embodiment of the present invention, the first current source and second current source provide a first current and a second current, respectively. The operational amplifier further comprises a current mirror coupled between the input stage and the output stage, and the matched transistor pair comprises: a first transistor, having a control node coupled to a first bias voltage, a first node coupled to a first bias current, and a second node; and a second transistor, having a control node coupled to the first bias voltage, a first node coupled to a second bias current, and a second node, wherein the second nodes of the first and second transistors are coupled to the current mirror. The transconductance boosting circuit comprises: a first amplifier, having an output node coupled to the control node of the first transistor, a first input node coupled between the first node of the first transistor and the first current source, and a second input node coupled to a second bias voltage; and a second amplifier, having an output node coupled to the control node of the second transistor, a first input node coupled between the first node of the second transistor and the second current source, and a second input node coupled to the second bias voltage. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of Miller compensation and Ahuja compensation schemes according to the related art. 
         FIG. 2  is a diagram of an Ahuja compensation implemented in a two stage operational amplifier. 
         FIG. 3  is a diagram of an updated Ahuja compensation scheme according to the present invention. 
         FIG. 4  is a diagram of the updated Ahuja compensation scheme of  FIG. 3  implemented in an operational amplifier that solves the bias problem of  FIG. 2  according to a first embodiment of the present invention. 
         FIG. 5  is a diagram of the updated Ahuja compensation scheme of  FIG. 3  implemented in an operational amplifier according to a second embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 3 .  FIG. 3  is a diagram of an improved Ahuja compensation scheme  400 . This scheme aims to improve the compensation offered by the original Ahuja compensation  200 , by indirectly multiplying the transconductance of the compensating transistor MP 3 . The effect of this indirect multiplying is to move the non-dominant poles and zeros to higher frequencies and to increase damping for the non-dominant poles. 
     The improved scheme shown in  FIG. 3  provides an amplifier A having a first input coupled to the bias current I BIAS , a second input coupled to the bias voltage V BIAS , and an output coupled to the gate of the compensating transistor MP 3 . The source voltage is therefore amplified, and this amplified voltage is then applied to the gate of the compensating transistor MP 3 . If the amplifier A has a gain of −A and the source voltage is v s , then the gate-source voltage vgs is equal to −(1+A) v s . The gate-source voltage has therefore been multiplied by a factor of (1+A). As long as the gain of the amplifier A is large enough, the source voltage of the compensating transistor MP 3  will remain at V BIAS . As the drain current of the compensating transistor MP 3  is a factor of the transconductance and the gate-source voltage, and the source voltage remains at V BIAS , the presence of the amplifier A effectively increases the transconductance by a factor of (1+A). The gate-source capacitance C 3  of the compensating transistor MP 3  is also increased by the same factor. Now, transconductance depends on the size of a device and on the bias current. Therefore, the present invention utilizes an indirect method of increasing the transconductance of the compensating transistor MP 3  without having to change its size or bias current. This saves power consumption and, to some extent, silicon area. 
     The effect of this increase in transconductance of circuit  400  in  FIG. 3  will be shown below with reference to the circuit  300  shown in  FIG. 2 . The transfer function for the circuit  300  shown in  FIG. 2  is written as: 
                     A   ⁡     (   s   )       =       A   0     ⁢       [       s     s   z       +   1     ]         [       s     s     p   ⁢           ⁢   1         +   1     ]     ⁡     [         s   2       ω   n   2       +     s     [       ω   n       2   ⁢           ⁢   ξ       ]       +   1     ]                   (   1   )               
A 0= DC gain of the operational amplifier=g m1 g m2 r 1 r 2   
     
       
         
           
             
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                       A 
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                       C 
                       C 
                     
                   
                 
               
             
           
         
       
     
     
       
         
           
             
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                 non 
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                   dominant 
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                   zero 
                 
               
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                     g 
                     
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                       3 
                     
                   
                   
                     C 
                     C 
                   
                 
               
             
           
         
       
     
     
       
         
           
             
               ω 
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                 unity 
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                 gain 
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                 bandwidth 
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                 of 
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                 the 
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                 operational 
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                 amplifier 
               
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                   g 
                   
                     m 
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                   C 
                   C 
                 
               
             
           
         
       
     
                     ω   n     =           g     m   ⁢           ⁢   2       ⁢     g     m   ⁢           ⁢   3           ρ   ⁢           ⁢     C   1     ⁢     C   2                       ξ   =       1   2     ⁢             C   1     ⁢     g     m   ⁢           ⁢   3           ρ   ⁢           ⁢     C   2     ⁢     g     m   ⁢           ⁢   2             ⁡     [     1   +       C   2       C   C         ]                     ρ   =     1   +       C   3       C   eq                       1     C   eq       =       1     C   2       +     1     C   C                     
where ξ and ω n  are the standard 2 nd  order parameters associated with non-dominant poles S p2  and S p3 .
 
     The circuit in  FIG. 2  has three poles of which S p1  is the dominant pole and S p2 , S p3  are the non-dominant poles. For Miller compensation the non-dominant poles are always real, but for the Ahuja compensation they can be real or complex. This depends on the 2 nd  order parameter ξ. If it is greater or equal to 1 then this corresponds to a damped frequency response and therefore the non-dominant poles are real; if it is less than 1 then the non-dominant poles are complex, meaning there is an under-damped frequency response. 
     To achieve good compensation, the non-dominant poles and non-dominant zeros need to be as far away as possible from the unity gain bandwidth (ω 0 ). The frequency response also needs to be as damped as possible. Effectively, the magnitudes of s z  and ω n  need to be as high as possible, the frequency response of S p2  and S p3  needs to be as damped as possible, so ξ needs to be as high as possible (at least greater than 1) to ensure there is sufficient frequency damping. 
     As the capacitance C 3  and transconductance g m3  (and therefore ρ) have been shown to increase by a factor of (1+A) as demonstrated in the above, s z  will increase by a factor of 1+A, and ξ and ω n  will increase by a factor of 
               1   +       C   eq     ⁢     /     ⁢     C   3               
as long as 1+A&gt;&gt;C eq /C 3 . Therefore, the improved Ahuja compensation scheme  400  shown in  FIG. 3  improves over the related art of scheme  200  in  FIG. 1  by providing increased compensation.
 
     Please refer to  FIG. 4 .  FIG. 4  is a diagram of an operational amplifier  500  that solves the bias problem of the circuit  300  in  FIG. 2  and implements the improved Ahuja compensation scheme  400  of  FIG. 3 . The circuit  500  in  FIG. 4  is similar to the circuit  300  in  FIG. 2  but with some important differences. The single transistor MP 4  has been replaced with a pair of P transistors MP 4   a  and MP 4   b , that are both coupled to the bias voltage V BP1  and the supply voltage V DD . Therefore they both supply a bias current I BIAS . Furthermore, the single compensating transistor MP 3  has been replaced by a pair of compensating transistors, MP 3   b  and MP 3   a . It can be seen that it is now possible to make MP 4   a , MP 3   a  and MP 4   b , MP 3   b  to carry identical currents IBIAS since they are all p-channel devices and biased from common or matching bias nodes. Thus, this amendment ensures that the bias problem does not exist, as MP 3   a  is coupled between MP 1   a  and MN 1   a , and MP 3   b  is coupled between MP 1   b  and MN 1   b . The circuit  500  in  FIG. 4  further shows the Ahuja compensation scheme consisting of a first amplifier A 1  and a second amplifier A 2 . The use of two amplifiers in this embodiment is for matching or balance, as the circuit  500  comprises two compensating transistors (MP 3   a  and MP 3   b ). 
     The effect of the improved Ahuja compensation scheme in this circuit  500  is as described above—by indirectly increasing the transconductance of the compensating transistors MP 3   a  and MP 3   b , the non-dominant poles and zeros are moved to be as far as possible from w 0  and therefore the compensation is improved. Removing the offset problem of the related art allows this improved scheme to be practically implemented in the circuit  500  to obtain these desired results. 
     Please refer to  FIG. 5 .  FIG. 5  is another implementation of the improved Ahuja compensation scheme in a circuit  600  that does not have the bias problem inherent in the circuit  300  shown in  FIG. 2 . As will be seen from the diagram, the improved Ahuja compensation scheme of the present invention also has the effect of increasing transconductance and having improved compensation. The circuit  600  shown in  FIG. 5  is an operational amplifier consisting of an input stage comprising the transistor MN 4  and the differential pair MN 1   a  and MN 1   b , and further comprising a pair of P transistors MP 1   a , MP 1   b  coupled to bias voltage V BP1  and respectively coupled to a pair of compensating transistors MP 3   a , MP 3   b , which are in turn coupled to a current mirror formed by transistors MN 3   a , MN 3   b , and also coupled across the differential pair. The amplifiers A 1 , A 2 , respectively coupled to the compensating transistors MP 3   a , MP 3   b , have a first input coupled to a bias voltage V BP2  and a second input respectively coupled to the source of transistors MP 3   a , MP 3   b , and also coupled to the differential pair MN 1   a , MN 1   b . Again, the improved Ahuja compensation scheme enhances compensation by indirectly increasing the transconductance of the compensating transistors MP 3   a , MP 3   b  through amplifying the gate-source voltage. 
     The present invention therefore provides an improved Ahuja compensation scheme that increases the transconductance of the compensating transistor though the addition of an amplifier, thereby ensuring good compensation, and further provides an implementation of the improved Ahuja compensation in an operational amplifier that solves the bias problem associated with a conventional operational amplifier that implements Ahuja compensation. Furthermore, the improved Ahuja compensation can be implemented in other conventional operational amplifier circuits while still having the effect of improved compensation through indirect increase of the transconductance of the compensating transistor. 
     The benefits of the improved Ahuja compensation over the related art are increased power efficiency, increased area efficiency, better PSRR, and better ability to cope with light capacitive loading. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.