Abstract:
A transistorized master slave flip-flop having a threshold offset generated through circuit size variations. The area of the emitter regions of selected bipolar transistors in the master and slave flip-flops are varied to provide preferred sequencing and thereby avoid untimely changes in state. Adjusting the area of the emitter regions provides the necessary offset without increasing the number of components or circuit crossovers.

Description:
FIELD OF THE INVENTION 
     The invention relates with particularity to the use of circuit size variations to inhibit untimely changes of state within logic circuits. 
     BACKGROUND OF THE INVENTION 
     In a transistorized master slave flip-flop circuit operated in the divide-by-two mode a first gate circuit which controls the master flip-flop is itself controlled both by clock signals and by the output of the slave flip-flop. A second gate circuit is provided to control the slave flip-flop and it is also controlled by the clock signals as well as by the output of the master flip-flop. Quite often these master slave flip-flop circuits are formed by integrated circuit techniques to decrease their size, increase their reliability and improve their performance. 
     Many of the prior art master slave flip-flops have encountered the problem that in the instance of a change of state of one flip-flop its associated voltage, which is applied through a gate circuit to the other flip-flop, is also changed and may result in an unstable state or incorrect state switching. It has been a common practice in prior art bipolar master slave flip-flops to provide a voltage offset within each flip-flop to create two different switching thresholds for the clock transistors in the flip-flops. One prior art technique has been to generate two distinct voltage levels which are routed through separate lines to one of the transistors in the master flip-flop and one of the transistors in the slave flip-flop. This creates separate switching levels for the gate circuits and by creating a preferred, stable state will inhibit any erroneous changes in the flip-flops caused by simultaneous switching of both, master and slave circuit elements. These different voltage thresholds are normally supplied by a voltage source external to the integrated circuit of the flip-flop but still within the monolithic implementation. It is apparent that such a method of inhibiting erroneous changes in state requires additional crossovers within the integrated circuit of the master slave flip-flop to route the voltages to the proper transistors and will thus increase the complexity of the circuit. It is also expensive and cumbersome to utilize an additional separate voltage source. There are obvious shortcomings in this prior art technique due to the increased complexity of the integrated circuit and the heat generated by the additional voltage source. 
     A second technique was developed in the prior art to establish a voltage offset between the bipolar transistors in the master slave flip-flop. This technique contemplated the use of additional resistors within the master slave flip-flop circuits to create the voltage offset. A resistor would be placed in one side of the current switch if it is the master flip-flop and with an additional resistor being placed in the other side of the current switch of the slave flip-flop to thereby generate with extra components the required offset. While this technique does not require any additional crossovers within the integrated circuit it does require the fabrication of additional circuit elements within each flip-flop circuit. The presence of the resistor slows down the operation of the current switch, increases the component count on the chip and further complicates the fabrication process. 
     A third prior art technique has been developed in master slave flip-flops which are fabricated from MOS transistors or other insulated-gate field-effect transistors. The required offset is provided by a suitable choice of the length-width ratio of the channels in the field effect transistors within the gate circuit to thereby provide the required load resistances. It is apparent, however, that this technique cannot be employed in master slave flip-flops which are fabricated from bipolar transistors. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to generate a threshold offset in a bipolar transistorized master slave flip-flop through the use of circuit size variations. 
     It is a further object of this invention to generate a threshold offset in a bipolar transistorized master slave flip-flop which reduces the component count and increases the circuit speed over prior art devices. 
     It is an additional object of this invention to provide a bipolar transistorized master slave flip-flop wherein a threshold offset is generated by varying the size of the emitters in selected bipolar transistors. 
     It is also an object of this invention to provide a bipolar transistorized master slave flip-flop wherein untimely changes of state resulting from variations in the properties of the circuit elements are avoided by generating a threshold offset through changes in the area of the emitters of selected bipolar transistors. 
     It is yet another object of this invention to provide a bipolar transistorized master slave flip-flop having a well defined switching sequence. 
     These and other objects are accomplished by a transistorized bipolar master slave flip-flop wherein a threshold offset is created within each flip-flop to inhibit erroneous sequencing. The master flip-flop has an emitter of increased area in the data intake branch of the flip-flop. The slave flip-flop has a bipolar transistor with an emitter of increased area in the data latch branch of the flip-flop. A two to one differential area between the emitters of the two bipolar transistors which are interconnected to form the flip-flops has been found to create a sufficient offset to inhibit erroneous sequencing. Generating the threshold offsets by varying the size of the emitters results in a faster flip-flop circuit which has a reduced number of circuit elements and a reduced number of crossovers. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The novel features which are characteristic of this invention are set forth with particularity in the appended claims. The invention itself, however, both in its organization and method of operation, together with further objects and advantages thereof, may best be understood with reference to the following description when considered in conjunction with the accompanying drawings wherein: 
     FIG. 1 shows a circuit diagram of a transistorized bipolar master slave D-type flip-flop according to the invention. 
     FIG. 2 shows a timing diagram of a transistorized bipolar master slave D-type flip-flop according to the invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1 exhibits a D-type flip-flop which employs circuit size variations to prevent erroneous and untimely switching. The circuit elements in FIG. 1 are interconnected between an upper circuit rail 11 which is maintained at a ground level and a lower circuit rail 13 which is held at sufficient negative potential, e.g. -3.6 to -6.0 volts. The transistors employed in the exhibited flip-flop are bipolar and elements I1, I2, I3 and I4 are designations of current sources. The clock signal for the flip-flop is entered at the base of transistor T 6 . This clock signal is employed to switch on the multi-emitter transistors T 7  and T 14 . In FIG. 1 the multi-emitter transistors are pictured as having three emitter leads which is intended to imply that the emitter size of the transistors T 7  and T 14  is approximately three times the size of the other transistors employed in the flip-flop. One skilled in the art will understand that the size of the emitter is varied according to the voltage offset which is desired for switching on selected transistors. 
     The master flip-flop generally indicated 15 is essentially a D-type latch as is the slave flip-flop 17. When coupled together the master and slave flip-flops function as an edge trigger, dual rank or master slave flip-flop. The master flip-flop and the slave flip-flop each employ a clock data intake switch and a latch switch and, as will hereinafter be explained, the circuit size variations employed in transistor T 7  and T 14  insure that the master and slave latches are maintained in opposite states. This is intended to mean that the master and slave flip-flops are never both in the data intake state but are rather maintained such that when the master flip-flop is in the data intake mode the slave flip-flop will be latched and vice versa. It is also possible during a certain portion of each clock period for both the master and slave flip-flops to be in the latch mode. Race conditions are avoided by the instant circuit insuring that the master flip-flop and the slave flip-flop will not coincidently be in the data intake mode. 
     The signal which triggers the changes in state within the D-type flip-flop is supplied as a signal to the base of transistor T 1 . This signal is D in . The collector of T 1  is coupled to the ground rail through load resistor R 1 . The emitter of transistor T 1  is connected to the collector of multiple emitter transistor T 7 . The emitter of T 1  is also coupled with the emitter of T 4  and as will hereinafter be explained this coupling forms the data intake switch for the master flip-flop. The latch switch for the master flip-flop is formed by transistors T 2  and T 3 . The emitters of these transistors are coupled together to the collector of T 5 . The collector of T 2  is coupled to the ground rail through resistor R 1  and its base is coupled to the ground rail through resistor R 2 . Similarly the base of T 3  is coupled to the ground rail through load resistor R 1  and its collector is coupled to the ground rail through R 2 . Transistor T 4  functions differentially with T 1  as will subsequently be described to form the data intake switch. The base of T 4  is held at a permanent DC bias of -200 millivolts. This value of - 200 millivolts will be referred to as V T . Finally, in explanation of the connections of the master flip-flop 15, the emitters of multiple emitter transistor T 7  are coupled through the current source I 2  to the negative supply rail 13. The emitter of T 5  is likewise coupled to the negative supply rail 13. The base of T 5  is maintained at a permanent DC bias equal to -1.0 volts. This bias is referred to as V T* . V T*  is equal to the sum of the V BE  of D1 and the -200 millivolts of V T . The value of V T  and V T*  can be provided through resistor R 5 , diode D1 and current source I 4 . 
     The slave flip-flop also includes a data intake switch and a latch switch. It can be observed that the multi-emitter transistor of the slave flip-flop T 14  is coupled into the opposite leg of the circuit of the slave flip-flop 17 as is the multiple emitter transistor T 7  in the master flip-flop circuit 15. As will be subsequently explained this will insure that the master and slave flip-flops are maintained in opposite modes through the major portion of each clock cycle. In the slave flip-flop the base of transistor T 8  is coupled to the collector of transistor T 1 . The emitter of T 8  forms the data intake switch by being coupled with the emitter of transistor T 11 . The collector of transistor T 8  is coupled with D out  and the ground rail through resistor R 3 . The latch switch of the slave flip-flop is formed by transistors T 9  and T 10 . The emitters of T 9  and T 10  are coupled together with the collector of multi-emitter transistor T 14 . The base of T 9  is coupled to D out  which is coupled to the ground rail through R 4 . The base of T 10  is coupled to the ground rail through R 3 . Transistor T 11  has its collector coupled to D out  and is coupled also with the ground rail through resistor R 4 . The base of transistor T 11  is coupled to the collector of transistor T 4 . Transistor T 12  and the multi-emitter transistor T 14  comprise the clock switch for the slave flip-flop. The base of T 12  is coupled to the DC bias V T* . The emitter of transistor T 12  is coupled to the negative supply rail through the current source I 3 . As was previously mentioned, the base of multi-emitter transistor T 14  is coupled to the emitter of the clock transistor T 6 . 
     In order to more fully understand how the D-type flip-flop of FIG. 1 functions it should be interpreted with the timing diagrams of FIG. 2. The first timing diagram is the input to the base of the clock transistor T 6 . The clock signal has a voltage swing between a low of -400 millivolts and a high of 0 volts. The first intermediate level indicated in the clock signal is equal to a -230 millivolts and the second intermediate level is a -170 millivolts. As indicated in the timing diagram of the clock signal the master flip-flop is maintained in data intake mode and the slave flip-flop is maintained in the latch mode during the interval between the clock signal attaining -170 millivolts or the second intermediate level on the rise of the waveform and until it falls below a -170 millivolts on the fall of the clock signal. Similarly, the slave flip-flop is maintained in data intake mode and the master flip-flop is latched during that portion of the clock signal when its value is -230 millivolts or below. The portion of the clock signal between the first intermediate level of -230 millivolts and the second intermediate level of -170 millivolts finds the master and slave flip-flops both latched to avoid race conditions in the circuit. 
     The second waveform in FIG. 2 is D in  which is supplied to the base of transistor T 1 . This waveform is a square wave with a voltage swing between -400 millivolts and 0 volts. The outputs of the D-type flip-flop are shown as D out  and D out  and are, of course, complements of each other. Their voltage swing is also between -400 millivolts and 0 volts. 
     In describing how the D-type master slave flip-flop of FIG. 1 operates it is important to recognize that the master flip-flop and slave flip-flops are implemented in such a manner that they each function as a D-type latch. The master latch and the slave latch when combined in the circuit of FIG. 1 function as an edge triggered dual rank or master slave flip-flop. The function of one of the latches is such that if the clock is activating the data intake switch of the latch then whatever logic level is present at the input D in  will be copied through to the output. If the clock is activating the latch switch, then the input of the latch is completely disconnected from the output and the output will carry the signal that was previously latched up within the latch. 
     The above-described switching is accomplished through the clock switch which, in the case of the master latch or flip-flop, steers current either through the multi-emitter transistor T 7  or the transistor T 5 . If the current flow is through T 7  the data intake switch will be activated and if the current flow is through T 5  the latch function of the master latch will be implemented. In order to steer current in the clock switch of the master latch through either transistor T 7  or transistor T 5  the clock input of transistor T 6  is moved up or down by virtue of the clock signal. The input from the clock moves from a low of -400 millivolts to a high of 0 volts thus causing the emitter of transistor T 6  and also the base of transistor T 7  to move from -800 millivolts to -1.2 volts. This is in essence a ±200 millivolt swing about -1.0 volts which drives the differential amplifier formed from the transistors T 5  and T 7 . One input of the differential amplifier is biased by V T*  at -1.0 volts and the base of T 7  is switched from -800 millivolts to -1.2 volts. This steers the current through either transistor T 5  to latch the master flip-flop or through transistor T 7  to place the master flip-flop in data intake mode. If the input to the base of transistor T 7  is at a -800 millivolts current will flow through the transistor T 7 , if the input to the base of transistor T 7  is at a -1.2 volts current will flow through the transistor T 5 . This is how the master flip-flop is switched between the data intake mode and the latch mode. 
     If the master flip-flop is in data intake mode, i.e. current is flowing from the collector of transistor T 7  it will be subject to another differential amplifier. This differential amplifier is formed from the emitter coupled switch of transistors T 1  and T 4 . The base of the transistor T 4  is maintained at a constant DC threshold of -200 millivolts while the base to transistor T 1  is maintained at either 0 volts or -400 millivolts depending upon the logic state of D in . If the base of transistor T 1  is maintained at 0 volts, current will flow through transistor T 1 , and if the base is maintained at -400 millivolts the current will flow through transistor T 4 . When the master flip-flop is in data intake mode the value of D in  will be directly copied over the load resistor R 2  which runs between the ground rail and the collectors of transistor T 3  and T 4 . This is the in-phase output of the master latch. The out-of-phase output of the master latch is provided at the collector tie of transistors T 1  and T 2 . 
     If the clock input to transistor T 6  is in the -400 millivolt state then the switch current of the master latch will flow through current source I 2 , the emitter of T 5  and out the collector of T 5 . This current will flow to the emitter coupled switch which is labeled latch switch and depending upon the regenerative feedback connections created between the collector and base nodes of T 2  and T 3  will maintain the previous state for the master latch. In essence there is no current flowing through the data intake switch since all the current is flowing through the latch switch of transistors T 2  and T 3 . Any change in D in  supplied to the base of transistor T 1  will not affect the collector nodes of T 2  and T 3  because T 1  is not switching any current. This in essence decouples the output of the master latch from the input and the information existing in the master latch will be retained. 
     If the same operational analysis is applied to the slave flip-flop or latch it can be seen that since the multi-emitter transistor T 14  is coupled to the latch switch and the DC biased transistor T 12  is coupled to the data intake switch formed by transistors T 8  and T 11  that the slave flip-flop will be in data intake during those clock intervals when the input to T 6  is between -400  millivolts and approximately -230 millivolts. It is during the same time period that the master latch will be in a latch mode. Similarly, the slave latch will be in a latch state in those periods when the clock signal is between -170 millivolts and 0 volts. Because of the differential switching between the transistors T 7  and T 5  and transistors T 12  and T 14  and considering the -1.0 volt bias of the V T*  both the master and slave latches will be in a latch state for that part of the clock signal between -230 millivolts and -170 millivolts. Permitting both the master and slave flip-flops to be in the latch mode simultaneously during this transition period successfully avoids any race condition and erroneous changes in state for the D-type flip-flop formed by the combination of master and slave latches. 
     The above-described system for accomplishing switching the master and slave latches in an out-of-phase manner is accomplished without the requirement of inserting a resistor in opposite legs of the clock switches of the master and slave flip-flops or by employing a voltage source to produce an offset for the transistors T 7  and T 14  in the clock switches of the master and slave flip-flops. The generation of a threshold offset within the master and slave flip-flops is accomplished by using circuit size variations in the form of enlarged emitters in opposite bipolar transistors of the clock switches of the master and slave flip-flops. No additional circuit interconnection or crossovers are required by the disclosed apparatus. By tripling the size of the emitters of the transistors T 7  and T 14  an approximate offset of 60 millivolts is generated. This 60 millivolts comprises the V BE  drop of transistor T 5  which is approximately 30 millivolts greater than transistor T 7  and the V BE  drop of transistor T 12  which is approximately 30 millivolts greater than the V BE  drop of transistor T 14 . This is assuming that the switch current from the current sources I 2  and I 3  are held constant. The generation of this voltage offset through circuit size variations has the advantage of speeding up the operation of the D-type flip-flop by employing switching devices which have a lower V BE  drop than would result in the case of insertion of resistors in the legs of the clock switches. 
     The foregoing description of a D-type flip-flop which employs circuit size variations to generate switching differentials to avoid erroneous changes in state is intended to be explanatory of a preferred embodiment for implementing the instant invention. One skilled in the art would understand that this technique of employing circuit size variations in the form of enlarged emitters can be readily adapted to digital devices other than the disclosed D-type flip-flop. The scope of the invention is defined by the following claims.