Abstract:
A microcomputer system has a microprocessor whose functions are implemented by instructions and data from a directly connected random access memory (RAM). The capacity of the RAM is less than the typical total instruction list for the microprocessor. A read-only mass memory is connected to the RAM and has permanently stored instructions set therein for the microprocessor. A controller controls the flow of instructions from the mass memory to the RAM as required and also controls the flow of instructions and data between the RAM and microprocessor. The instructions from the mass memory are overlayed in the RAM in areas no longer required for instruction execution.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to microcomputers and in particular to virtual memory arrangements for microcomputers. 
     2. Description of the Prior Art 
     In the early days of digital computers, very slow main memories were used for storing data and instructions for the computer. These memories took the form of magnetic drums, magnetic tapes and mercury delay lines. Later, magnetic switch core memories were commonly used. As the size of programs increased, magnetic drums, magnetic tapes and magnetic discs were used to store the programs for subsequent calling in to the main core memory. 
     Miniaturization of computer architecture included memory miniaturization resulting in integrated circuit random access main memories. In many cases these were replaced by read-only memories in which were stored the instructions for the microcomputer. As the microcomputer systems grew larger and program memories were required to grow larger, the larger ROM became expensive and contained much of the program that was not needed at the moment. 
     This virtual architecture uses a RAM and a low cost, large read-only mass memory for the mass storage of instructions. The instructions from the mass memory can be downloaded and overlayed onto a portion of the RAM space not immediately required for program execution. 
     BRIEF SUMMARY OF THE INVENTION 
     A microcomputer system is extremely versatile and useful in data processing apparatus such as input and output terminals. A microprocessor system controls the operation of the data processing apparatus in accordance with a list of instructions received. These instructions come from a main memory which has a random access memory (RAM) for storing a portion of this list of instructions. In this preferred embodiment, the main memory also has read-only memory containing start-up instructions to enable the microprocessor system to begin operation. The RAM must also have storage available for data and constants required in computations. 
     A large scale read-only mass memory has the entire instruction list for the microprocessor system permanently stored therein. As the instructions from the RAM are used and the sequence is no longer necessary, new instruction sequences are brought in from the mass memory to the RAM for ultimate execution by the microprocessor system. A controller is employed to address the mass memory for transferring instructions to the RAM and further has means for addressing the RAM to affect transfers between the RAM and the microprocessor system. 
     As the microcomputer system requires additional program functions, these functions are continuously downloaded from the mass memory and overlayed onto a portion of the RAM storage space not required for immediate program execution. The overlay process continues as long as new program functions are required. 
     The principal object of this invention is to provide the microprocessor system of a microcomputer system with executable instructions at a high access rate. 
     Another object is to provide the microprocessor system of a microcomputer system with instructions through a directly accessed memory whose capacity is less than the list of instructions. 
     Still another object of this invention is to provide the microprocessor system of a microcomputer system with a random access memory for direct access by the microprocessor system and a read-only memory for bulk storage of an instruction list. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIGS. 1a and 1b form a block diagram of an electronic terminal employing the virtual memory microcomputer architecture. 
     FIG. 2a is a schematic diagram of the circuitry used in accessing the read-only mass memory. 
     FIG. 2b is a schematic diagram of the circuitry for controlling the accessing of the random access memory. 
     FIGS. 3a-3i form a map, in hexidecimal code, of the contents of the read-only mass memory. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The invention described herein is of a virtual memory microcomputer architecture for controlling a microcomputer which in turn is useful in controlling data processing apparatus. A random access memory (RAM) is directly accessed by a microprocessor system which uses instructions and data from the RAM for carrying out a program. The RAM does not have sufficient capacity for storing all of the instructions in the program. Instead, a read-only mass memory has all of the instructions permanently set therein, those instructions being readable into the RAM to overlay portions of the RAM as the instructions are used in the program and no longer required in the program routine. This overlaying technique is continued until the program is completed. The following preferred embodiment illustrates the invention. 
     Referring now to FIG. 1, a block diagram of an electronic input/output terminal employing the invention is shown. Microprocessor 25a, timer 25b, parallel input/output unit 25c, serial input/output unit 25d and timer 25e form the total microprocessor system of this invention. The particular microprocessor system selected for implementing this invention is the Zilog Company Z80A made up of components 25a through 25e, all described in &#34;Zilog Microcomputer Components Data Book&#34; dated February, 1980. System control bus 27 extends from microprocessor 25a to timer 25b, to parallel input/output unit 25c, to serial input/output unit 25d, to timer 25e and to IO controller 22. System address bus 13 extends from microprocessor 25a to timer 25b, to parallel input/output unit 25c, to serial input/output unit 25d, to timer 25e and to IO controller 22. IO controller 12 is a Texas Instruments Incorporated type TMS5501 and is used for communication with function timing generator 45 for use with bubble memory 44. Bubble memory 44 is comprised of units 47a-47h controlled by drive sense modules 46a -46h. The bubble memory is peripheral to this invention and need not be described in detail here. 
     The system data bus 19 from microprocessor 25a is serially connected to microprocessor units 25b-25e, terminating in IO controller 22. Buffers 28 and 29 are connected to system data bus 19 and are Texas Instruments type SN74LS 245 octal bus transceivers described in detail beginning at page 7-349 of &#34;TTL Data Book for Design Engineers&#34; Texas Instruments Incorporated, copyrighted 1976. Buffer 28 interconnects memory data bus 18 with system data bus 19. Buffer 29 interconnects I/O data bus 32 with system data bus 19. I/O data bus 32 is connected to keyboard controller 34, printhead drivers 36, mechanism control latch 37 and line feed bubble select latch 38. Latch 38 has an output connected to the input of bubble selector 43 which in turn is connected to the bubble memory 44. An output from latch 38 provides an input to line feed motor driver 42 which is part of a printer having an output to the printer mechanism 40. Printhead drivers 36 also are connected to printer mechanism 40. Latch 37 has one output connected to printhead voltage control 39 which in turn has an output connected to the printer mechanism 40. Latch 37 also has an output to slew motor control 41 whose output is connected to the printer mechanism 40. The printer mechanism is well known and need not be described in detail. 
     Keyboard controller 34 is connected to keyboard 35. The keyboard 35 and keyboard controller 34 are well known and need not be described in detail. 
     I/O decode 30 is made up of a programmable logic array and a decoder. The combination of these two components provides output signals in response to command and address input signals from microprocessor 25a. 
     EIA port 49 is connected to EIA driver-receiver 35 which in turn is connected through bus 33a to parallel input/output unit 25c and through bus 33b to serial input/output unit 25d. A baud rate source multiplexer 48 is connected to unit 35 and also to unit 25d to provide synchronization. The EIA port 49 and associated hardware described is for communication involving 24 volt levels. This is old in the art and need not be described in detail here. 
     Mass controller 20a is connected to buffer 29 through I/O data bus 32. Mass store 1 through mass store 5 (14a-14e) form the read-only mass memory 14 and are connected by bus 15 to mass controller 20a. 
     RAM controller 20b is connected to I/O decode 30 and microprocessor system 25 by way of system control bus 27. RAM controller 20b is also connected by way of the system address bus 13 to microprocessor 25a and I/O decode 30. Start-up ROM 17 is connected to memory data bus 18 and to system address bus 13. Its permanently stored instructions form a boot strap program to enable the microprocessor 25a to utilize preliminary instructions. In this preferred embodiment, a Texas Instruments Incorporated type TMS4764 read-only memory is employed. 
     RAM multiplexer 11 receives its inputs from system address bus 13 and addresses RAM 12 which is connected by RAM address bus 16 to RAM mux 11. Memory data bus 18 is connected to RAM 12 as well. RAMs 12a-12c, in this preferred embodiment, are Texas Instruments type TMS4116 described in detail beginning at page 101 of the &#34;The MOS Memory Data Book for Design Engineers&#34; of Texas Instruments, copyright 1977. RAM multiplexer 11 is a Texas Instruments type SN74SL257 quadruple Data Selector/Multiplexer described beginning at Page 7-372 of the &#34;TTL Data Book&#34;. 
     The read-only mass memory 14a-14e, in this preferred embodiment is made of up five Texas Instruments TMS6100 read-only memories fully described in the Texas Instruments publication &#34;TMS6100 Voice Synthesis Memory Data Manual&#34;, dated June, 1980. Presently, as many as 16 such units could be used. Each of the mass stores 14a-14e have a capacity of sixteen thousand three hundred eighty four bytes. When so ordered, the contents of any of the mass stores 14a-14e is transferred by way of bus 15 through I/O data bus 32 and buffer 29 to microprocessor 25a. According to this invention, no processing is done at this time, the information being simply assembled into bytes and then transferred via buffer 28 to the RAM 12 via memory data bus 18. Subsequently, the instructions are read into microprocessor system 25, from the RAM 12 for execution of instructions. 
     Referring now to FIG. 2a, mass controller 20a is illustrated schematically. Data bus lines D0-D3 are connected through amplifiers 102, 104, 106 and 108 respectively to the inputs of &#34;fall-through&#34; flip flops 119-122, respectively. Data bus line D4 is connected through amplifier 116 to the DC input of &#34;fall-through&#34; flip flop 129. Finally, data bus line D5 is connected through amplifier 117 to the D input of D type flip flop 131. &#34;Fall-through&#34; flip flops 119-122 and 129, and D type flip flop 131 from a data latch. A common clock signal &#34;GRML-&#34;, from I/O decode 30, is applied through amplifier 113 and inverter 114 as the clock inputs of flip flops 119-122 and through inverter 115 to the clock inputs of flip flops 129 and 131. Flip flop 131 is a D type flip flop to ensure that a transfer to subsequent sync latch flip flops does not occur until all of the data is stable. 
     &#34;Fall-through&#34; flip flops 132 through 135 have their DC inputs provided by the Q- outputs from &#34;fall-through&#34; flip flops 119 through 122 respectively. &#34;Fall-through&#34; flip flop 141 has its DC input provided by the Q output of flip flop 129. Flip flop 142 has its DC input provided by the Q output from flip flop 131. These six last mentioned flip flops form a sync latch. The clock signal GCK at 200KHZ from a clock (not shown) is applied through amplifier 111 and inverted through amplifier 112, then applied to one-shot multivibrator 126 whose output is amplified through inverter 127 and provides the clock inputs to flip flops 132 through 135. The output of one-shot multivibrator 126 is also amplified by amplifier 128 and provides the clock inputs to flip flops 141 and 142. These six flip flops, together with one-shot multivibrator 126 synchronize input signals to the mass memory clock. 
     NAND gates 150-153 each have one input provided from the Q output of each of flip flops 132-135 respectively. The other input to each of NAND gates 150-153 is provided by the Q output of flip flop 142, such output identified as signal Ii. The outputs from NAND gates 150-153 are applied to terminals AD1, AD2, AD4 and AD8 respectively, the mass memory bus. The Q outputs from flip flop 141 is applied to terminal Io and the Q- terminal of flip flop 142 is inverted through inverter 143 and is applied to terminal Ii. NAND gates 150-153 form a mass memory output buffer which places information onto the mass memory bus when the synchronized Ii signal goes high. A mass memory bus lines are low only when Ii is high and the corresponding data bit is low. 
     The signals on mass memory lines AD1, AD2, AD4 and AD8 are amplified through amplifiers 136-139 respectively, the outputs of which provide one input to each of NOR gates 118, 123, 124, and 125. The other input to these four NOR gates is provided by signal GRMB- which is amplified through amplifier 109. These four NOR gates enable instructions from the mass memory to be placed on the processor data bus when signal GRMB- goes low. 
     FIG. 2b schematically illustrates the RAM controller 20b. In this preferred embodiment, mass controller 20a and RAM controller 20b are formed on the same integrated circuit chip. A system clock (not shown) operating at a frequency of 4MHz has output signal PHAS- applied to amplifier 61 whose output is inverted through inverter 62 and applied as a clock input to flip flop 63. Signal PHAS- is also applied as one input to NOR gate 67. The output from inverter 62 provides one input to NOR gate 66. The output from amplifier 61 providing signal PHAS-, is inverted through inverter 93 to clock flip flop 97. Signal MREQ- from microprocessor 25a  is amplified by amplifier 71 and provides the DC input to &#34;fall-through&#34; flip flop 63 whose Q output provides an ROW signal that is applied to RAM multiplexer 11, causing the multiplexer to address row or column depending upon the state of signal ROW. 
     Signal MI from microprocessor 25a is amplified by amplifier 65 and provides another input to NOR gate 66. Signal MI indicates that the microprocessor 25a is executing an operation code fetch or responding to an interrupt. Signal MREQ-, from microprocessor system 25, which signifies that the a memory request is pending, is amplified through amplifier 71 and provides still another input to NOR gate 66. The ROW signal provides the fourth input to NOR gate 66 whose output provides an input to a latch formed of NOR gates 68 and 69. The other input to latch 69 is provided by the output of amplifier 71, namely signal MREQ-. The output of NOR gate 68 provides one input to NOR gate 67 whose other input is the system clock signal PHAS-. 
     Signal MREQ- is amplified through amplifier 72 whose output provides an input to each of the NOR gates 81, 82, 88 and 87. The output of NOR gate 67 provides one input to each of NOR gates 81, 82 and 88. 
     Signal RFSH-, from microprocessor 25a is a memory refresh cycle signal inverted through inverter 74 and applied as an input to each of NOR gates 78, 79 and 86. 
     Address line A14 provides an input to each of AND gates 76 and 84. The signal on A14 is inverted through inverter 75 providing one input to AND gate 77 and one input to NAND gate 85. Address line A15 provides an input to each of AND gates 76 and 77, and after having been inverted through inverter 83 provides one input to AND gate 84 and one input to NAND gate 85. Address line A13 provides an input to NAND gate 89 and, inverted through inverter 91, provides an input to NAND gate 92. The outputs of NAND gates 76, 77 and 84 provide inputs to NOR gates 78, 79 and 86 respectively. The output from NAND gate 85 provides an input to NOR gate 87 and to NOR gate 94. The outputs from NOR gates 78, 79 and 86 provide inputs to NOR gates 81, 82 and 88 respectively. The output from NOR gate 87 provides one input to NAND gate 89 and one input to NAND gate 92. The output from NOR gate 94 provides the D input to flip flop 97 whose Q output provides another input to NOR gate 94. The output from NOR gate 94 provides one input to NOR gate 96. Signal WIN-(wait input) generated in the bubble memory, inverted through inverter 95 provides one input to NOR gate 96. Signal WEN, (wait enable) from microprocessor system 25, provides the 7 enable input to flip flop 97. 
     The outputs from NOR gates 81, 82 and 88 provide outputs RASC, RAS8 and RAS4 respectively. The output from NAND gate 92 provides output ROM0-. The output from NAND gate 89, in this preferred embodiment is not used. ROM0 selects the start-up ROM 17 and outputs RAS4, RAS8, and RASC select RAMS 12a, 12b and 12c respectively. NOR gate 96 provides a WAIT- signal for the microprocessor system 25 to slow that device down when a memory reference is made to the read-only mass memory. It is also used for other purposes such as referencing the bubble memory which is not important to this invention. 
     PREFERRED MODE OF OPERATION 
     FIGS. 3a-3i form a map, in hexidecimal code, of the contents of the read-only mass memory 14. These contents are instructions that cause the terminal to operate in a prescribed way. The instructions include a nucleus of the system, device service system, application programs, protocols, command processors, etc. Such instruction lists are well known for causing peripheral devices to operate in a desired manner. These instructions are sent to the main memory 12 via microprocessor system 25 of FIG. 1. When the microprocessor 25 recognizes that a reference must be made to the mass memory 14, then a memory reference is made. This is accomplished through the I/O data bus 32, data lines D0-D5. Referring to FIG. 2a, it can be seen that signals D0-D3 provide the actual address lines AD1, AD2, AD4 and AD8 respectively. Data lines D4 and D5 provide sync signals Io and Ii, respectively. When D5 is high, then Ii permits signals D0 through D3, by virtue of gating NAND gates 150-153, to address the mass memory 14 in four bit increments. The outputs from lines AD1, AD2, AD4 and AD8 provide inputs to an address register for the mass memory 14. For any one access, five sequences of these four bits is made to fill the register with twenty bits. In this preferred embodiment, the two most significant bits are not used. The next four bits select which of the sixteen read-only memories is to be selected. In this preferred embodiment, only five such memories (14a-14e) are present. The next fourteen bits select the particular address. The information (instructions) are then read out of the memory in four bit increments (nibbles). With signal Io high, as a result of data line D4 being high, a nibble is presented on lines AD1-AD8 and ultimately lines D0-D3. These signals are gated by the signal GRMB- which is generated by the I/O decode 30. Signal GRML- for transfer in the other direction, is also generated by I/O decode 30. This memory referencing is continued in this manner until the microprocessor system 25, through its instructions, stops the process. The buffer 29 is activated by signals IBUF- and WEB- from I/O decode 30 to permit the information on lines D0-D3 to be taken into microprocessor system 25 which then assembles these nibbles into bytes (eight bits) for transfer through buffer 28 to the main memory. Buffer 28 is enabled by signal MREQ- and its direction is set by signal RD-. FIG. 2b illustrates the circuitry for selecting which of the RAMS (12a-12c) is to be addressed. Also, the ROW signal is developed to switch from ROW address to column address. Specific addressing is accomplished through the RAM multiplexer 11 in a standard manner. 
     The virtual memory microcomputer architecture of this invention has been shown in connection with an input/output terminal utilizing a thermal printer, keyboard and a bubble memory. It may be used for any microcomputer, which, for economic purposes, requires a RAM for the main memory, such RAM being too small to hold the entire instruction list required, and accordingly having a read-only mass memory to hold all of the instructions required, with such mass memory available to provide instructions as they are needed through the RAM. The particular component types shown here are of course only illustrative and not limiting. Anyone of ordinary skill in the art can readily understand this invention and make substitutions of hardware without departing from the scope of the appended claims.