Abstract:
Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
       [0001]    The parent of the present application (Ser. No. 13/243,880, filed Sep. 23, 2011) is related to the U.S. application Ser. No. 13/243,908 entitled “A High Performance Divider Using Feed Forward, Clock Amplification and Series Peaking Inductors”, and the U.S. application Ser. No. 13/243,986 entitled “Method and Apparatus of Minimizing Extrinsic Parasitic Resistance in 60 GHz Power Amplifier Circuits” both filed on Sep. 23, 2011, which are invented by the same inventor as the present application and incorporated herein by reference in their entireties. This present application is a divisional of U.S. application Ser. No. 13/916,535, filed Jun. 12, 2013, which is a continuation and claims the benefit of U.S. application Ser. No. 13/243,880, filed Sep. 23, 2011, which has been granted a U.S. Pat. No. 8,487,695 on Jul. 16, 2013, entitled “A Differential Source Follower having 6 dB Gain with Applications to WiGig Baseband Filters” all invented by the same inventor as the present application and incorporated herein by reference in their entireties. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS) or Silicon-Germanium (SiGe) technology to form the dice in these designs. At 60 GHz, achieving the desired parameters of gain (G), bandwidth (BW) and noise figure (NF) present difficult challenges. These parameters can be traded against the other in the design of these high frequency circuits. 
         [0003]    A source follower, also known as a common drain amplifier, is a circuit configuration of an active device that is used in circuit designs to provide a voltage butter or to transform impedances. A CMOS source follower circuit provides high input impedance, moderate current gain, low output impedance and a voltage gain approaching one. Such a device can be fabricated using the CMOS 40 nm technology designed to operate at a VDD of 1.2V. 
         [0004]    A Sallen-Key topology is a second-order active filter that presents a finite input impedance and a small output impedance in its external filter characteristics. The filters can be designed as a low-pass, band-pass or high-pass filter. Such active filters avoid the use of inductors which can consume large areas in integrated circuits. A higher filter gain is achieved by cascading two or more Sallen-Key filter stages. 
       BRIEF SUMMARY OF THE INVENTION 
       [0005]    Various embodiments and aspects of the inventions will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the present invention. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions. 
         [0006]    As the power supply voltage reduces in the scaling of integrated circuits, the voltage headroom for analog integrated circuits decreases correspondingly. This makes the design of high performance systems in a low power supply integrated circuit much more challenging. A source follower amplifier can be formed from two series stacked devices coupled between the VDD and GRD where one device translates the input signal (active device) while the second device is the load (load device). For example, a CMOS source follower is formed by placing two series stacked n-channel (NMOS) devices coupled between VDD and GRD with the lower device presenting a controlled current load to the upper device that is driven by the input. If the supply voltage (VDD-GRD) is 1.2V, the headroom, or available output signal swing, is an important concern. With only two devices between the power supplies, the source follower generates an output signal with a maximum voltage swing of 400 mV to 500 mV. This maximum voltage swing is called the headroom. 
         [0007]    One of the embodiments of the disclosure modifies the load device in a source follower so that the load device also allows the introduction an input signal that enhances the gain of the source follower. Thus, the load device provides a DC (Direct Current) bias to operate the source follower and introduces an AC (Alternating Current) gain when the load device is driven by a signal with the proper phase (180°) compared to the signal being applied to the active device. The AC voltage gain of the load device is added constructively to the AC voltage gain of the conventional source follower to provide an improvement in the gain of the source follower by 6 dB. Thus, the AC voltage gain of a source follower using this inventive concept can be increased from 0 dB to 6 dB. 
         [0008]    Another one of the embodiments of the disclosure is to incorporate the source follower with AC voltage in the load device into a differential amplifier configuration. A differential configuration amplifies an AC input signal and a complement AC input signal and generates an AC output signal and a complement AC output signal. The complement AC input signal is phase shifted 180° from the AC input signal and the complement AC output signal is phase shifted 180° from the AC output signal. The complement AC output signal is also referred as an inverse AC output signal. Overall, the gain of the source follower differential amplifier can be as large as a 6 dB gain. 
         [0009]    A different one of the embodiments of the disclosure is to incorporate the source follower into the design of a Sallen-Key filter. The operational amplifier  1 - 15  in the Sallen-Key filter in  FIG. 1   b  limits the high frequency behavior of the filter. The inventive source follower can significantly extend the range of the high frequency behavior of this filter. This source follower has input/output characteristics similar to that of the operational amplifier. The operational amplifier presents infinite input impedance, good current drive and a small output impedance at its input and output terminals. Similarly, the source follower has attributes that include having a high input impedance, good current drive and a low output impedance at its input and output terminals. The operational amplifier is replaced with the source follower and is utilized to create a Sallen-Key filter that provides an 880 MHz bandwidth filter. The source follower itself would require an overall bandwidth of 8.8 GHz to achieve this filter bandwidth. A conventional operational amplifier is typically uses two cascaded stages and requires a negative feedback network to compensation for any potential stability issues. Such additional networks increase capacitance, increase die area, and limits high frequency performance. However, the source follower uses a single stage using two series coupled devices between VDD and GRD and furthermore does not require a negative feedback network. These features allow the Sallen-Key filter with the source follower to have a bandwidth that can filter baseband WiGig signals. The WiGig signal content is within a bandwidth of 0 to 880 MHz. The inventive technique removes the first 2 MHz by the use of an RC network but does not cause any performance degradation. 
         [0010]    In accordance with another embodiment of the invention, the features of the differential signal output stage using the first and second source follower stages are advantageously leveraged to form the Sallen-Key filter topology. The overall front end gain of the receiver of the LNA, Mixer and BaseBand amplifier of devices fabricated at 40 nm CMOS fails to deliver the desired gain to design a receiver that can operate with 60 GHz signals at low power. Additional gain was required in the RF link. The Sallen-Key LPF (Low Pass Filter) uses the inventive source followers to provide 6 dB of AC voltage gain per differential signal. Furthermore, two Sallen-Key LPFs are concatenated in series to provide 12 dB of additional AC voltage gain. Other aspects and features of the inventions are also presented. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]    Please note that the drawings shown in this specification may not necessarily be drawn to scale and the relative dimensions of various elements in the diagrams are depicted schematically. The inventions presented here may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be through and complete, and will fully convey the scope of the invention to those skilled in the art. In other instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiment of the invention. Like numbers refer to like elements in the diagrams. 
           [0012]      FIG. 1   a  depicts an on-chip RF link. 
           [0013]      FIG. 1   b  illustrates a Sallen-Key filter. 
           [0014]      FIG. 1   c  illustrates a low-pass Sallen-Key filter. 
           [0015]      FIG. 2   a  shows a two device source follower in accordance with the present invention. 
           [0016]      FIG. 2   b  presents the current mirror generating the voltage bias in accordance with the present invention. 
           [0017]      FIG. 2   c  depicts a 6 dB AC voltage gain in a source follower in accordance with the present invention. 
           [0018]      FIG. 2   d  illustrates the 6 dB AC voltage gain in a source follower with RC networks in accordance with the present invention. 
           [0019]      FIG. 2   e  shows the current source and a dynamic source follower block in accordance with the present invention. 
           [0020]      FIG. 2   f  illustrates a differential source follower with 6 dB of AC voltage gain in accordance with the present invention. 
           [0021]      FIG. 2   g  shows a differential source follower with the biasing and RC networks in place in accordance with the present invention. 
           [0022]      FIG. 2   h  presents  FIG. 2   e  with dynamic source follower blocks in accordance with the present invention. 
           [0023]      FIG. 3   a  presents the two pole Sallen-Key filter in accordance with the present invention. 
           [0024]      FIG. 3   b  presents a cascaded two pole Sallen-Key filter in accordance with the present invention. 
           [0025]      FIG. 3   c  depicts an implementation of the differential two pole Sallen-Key filter cascaded in accordance with the present invention. 
           [0026]      FIG. 4   a  illustrates the two pole Sallen-Key filter in accordance with the present invention. 
           [0027]      FIG. 4   b  illustrates the two pole Sallen-Key filter using a source follower as an operational amplifier in accordance with the present invention. 
           [0028]      FIG. 4   c  depicts a low pass Sallen-Key filter as in  FIG. 4   b  replaced with a dynamic source follower block in accordance with the present invention. 
           [0029]      FIG. 4   d  illustrates a generalized Sallen-Key filter replaced with a dynamic source follower block in accordance with the present invention. 
           [0030]      FIG. 5   a  presents the second cascaded stage of  FIG. 3   c  in accordance with the present invention. 
           [0031]      FIG. 5   b  illustrates the second cascaded stage of  FIG. 3   c  replaced with dynamic source follower blocks in accordance with the present invention. 
           [0032]      FIG. 6   a  shows a differential cascaded low pass Sallen-Key filter using the dynamic source follower with the biasing, RC networks and components in accordance with the present invention. 
           [0033]      FIG. 6   b  depicts a differential cascaded low pass Sallen-Key filter with dynamic source follower blocks in accordance with the present invention. 
           [0034]      FIG. 7   a  illustrates a differential cascaded low pass Sallen-Key filter using the dynamic source follower as in  FIG. 6   a  but modified with two independent current biasing voltages and the RC networks and components in accordance with the present invention. 
       
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       [0035]    The inventions presented in this specification can be used in any wired or wireless high frequency system design. One application of the inventions can be applied to the front end of a receiver circuit  1 - 1  as illustrated in  FIG. 1   a . The Low Noise Amplifier (LNA)  1 - 2  can receive a weak signal at its input  1 - 3 . This signal may have been be provided by an antenna or a wired line and is amplified by the LNA and applied to the Mixer  1 - 4 . The CMOS design of an LNA at millimeter waves with a gain greater than 30 dB is very difficult. Afterwards, the signal is demodulated into a baseband signal. The baseband signal is amplified by the Base Band Amplifier (BBAMP)  1 - 5  and sent to the Low Pass Filter (LPF)  1 - 6 . The LPF filters the signal and also provides an additional gain before the signal is sent to the Programmable Gain Amplifier (PGA)  1 - 7  which generates an output  1 - 8 . In either case, the weak signal is amplified, demodulated, amplified, filtered and amplified as an output  1 - 8  before being applied to an A/D (Analog to Digital) convertor (not shown). The block diagram can be operated using a single signal stream or differential signal stream. 
         [0036]      FIG. 1   b  illustrates a Sallen-Key filter  1 - 9  which has a large input impedance and small output impedance. The input  1 - 10  to the filter is via Z 1    1 - 11  whose output is coupled to Z 2    1 - 12  and Z 3    1 - 14 . Z 3    1 - 14  couples to the output  1 - 16 . Z 2    1 - 12  is coupled to Z 4    1 - 13  and the positive input of the operational amplifier  1 - 14 . The other end of Z 4    1 - 13  is grounded. The output  1 - 16  is also coupled to the negative input of the operational amplifier  1 - 15 . The operational amplifier offers high gain and allows the construction of a second order filter without the use of inductors. In  FIG. 1   c , the impedances are replaced with resistors or capacitors in the Sallen-Key filter  1 - 17  to form a low pass filter. 
         [0037]      FIG. 2   a  depicts two n-channel devices (N-MOS) coupled in series forming a path between the power supplies VDD and GRD (ground). This configuration is known as a source follower. The lower device N 1  acts as a load device and is biased by a DC bias voltage V bias  while the upper device N 2  acts as an active device and is driven by V in1    2 - 2 . The output signal V out    2 - 3  is in phase (non-inverted) with V in1 . The AC voltage gain of V out1 /V in1  is almost one or 0 dB and behaves very linearly. 
         [0038]      FIG. 2   b  illustrates how the current source is formed using device N 3  and N 1 . A bias current I bias  can be applied to the device N 3  that is connected in saturation where the gate is connected to the drain. The generated voltage V bias  is then applied to the device N 1  which scales the current carried in N 1  of the stacked devices N 2  and N 1 . The stacked devices form a path between the power supplies. The load device (lower device) and the reference transistor form a current mirror. The active device (upper device) has first signal V in1    2 - 2  applied to the input. The first signal V in1  causes the generation of an output signal V out    2 - 3  that is in phase with the input signal V in1  and has a AC voltage gain approaching one (0 dB). The maximum swing of the output signal V out  equals the headroom. Since the gain is 0 dB, the input voltage has a voltage swing equal to the headroom. 
         [0039]    In accordance with one inventive concept of the invention, a source follower stage is modified to provide an AC voltage gain that approaches two (6 dB) as illustrated in  FIG. 2   c . The bias voltage V bias  as is applied to the load device N 1  as before. However, an RC network (not illustrated) provides two functions: 1) in one case the RC network presents a low pass filter that filters the bias voltage V bias  applied to N 1 ; and 2) in a second case presents a high pass filter (using the same RC network) to a couple a second input signal  V in    to the load device, simultaneously. The second input signal  2 - 8 , and the filter bias voltage are applied to load device N 1 . Similarly, the first input signal V in    2 - 6  is applied to the active device N 2  and generates a first output signal component V outt    2 - 7 . The load device N 1  inverts the signal  V in     2 - 8  at its input and generates a second output signal component V outb    2 - 9 . Thus, the active device N 2  generates a first output signal component V outt  of the output signal that is in phase with the input signal V in  and the load device N 1  generates the second output signal component V outb  of the output signal that is out of phase with the input signal  V in   . Since the load device inverts the input signal  V in    and generates a second output signal component of the output signal that is in phase with the first output signal component of the output signal, the overall gain of the active and load devices is in phase causing the first and second output signal components of the output signal to be summed constructively. Note that the summation of V outt    2 - 7  and V outb    2 - 9  has an overall maximum amplitude equal to the headroom or in this case the magnitude of V out    2 - 3 . The maximum amplitude of the summation equals the headroom mentioned earlier. However, the input signals V in    2 - 6  and  V in     2 - 8  each have half the magnitude of V in1    2 - 2 . Assuming the magnitude of the AC voltage gain of the active load is almost one while the magnitude of the AC voltage gain of the load device can be designed to be one, thereby allowing this inventive source follower stage to have an AC voltage gain equal to 6 dB. 
         [0040]    The circuit  2 - 17  in  FIG. 2   d  illustrates the addition of the RC networks and current source with the bias current to  FIG. 2   c . Note that the two output voltages V outt    2 - 7  and V outb    2 - 9  of  FIG. 2   c  are combined into V out  into  FIG. 2   d , the bias current I bias  creates a DC bias voltage across the device N 3  and is applied to the device N 1  in the first source follower through a low pass filter comprising of R n2  and C n2  (see arrow  2 - 18 ). Assume the impedance of the voltage source  V in     2 - 8  is very low, thereby effectively grounding the far end of the capacitor C n2  forming the low pass filter. Simultaneously, the high frequency input signal  V in     2 - 8  is applied to the load device N 1  through the high pass filter comprising the same two components C n2  and R n2  (see arrow  2 - 19 ). The far end of the resistor R n2  is coupled to AC ground forming the high pass filter. Thus, the load device N 1  is biased to the correct bias voltage and simultaneously the high frequency signal  V in     2 - 8  is also applied to the load device N 1 . 
         [0041]    The second RC network of  FIG. 2   d  comprising R n1  and C n1  also presents a low pass or high pass filter to the input DC bias voltage from VDD and the high frequency signal of V in    2 - 6 . The voltage VDD is applied to the device N 2  in the first source follower through a low pass filter comprising of R n1  and C n1 . Assume the impedance of the voltage source V in    2 - 6  is very low, thereby effectively grounding the far end of the capacitor C n1  forming the low pass filter. Simultaneously, the high frequency input signal V in    2 - 6  and is applied to the load device N 2  through the high pass filter comprising the same two components C n1  and R n1 . The far end of the resistor R n1  is coupled to AC ground forming the high pass filter. Thus, the load device N 2  is biased to the correct DC bias voltage and simultaneously the high frequency signal V in    2 - 6  and is also applied to the load device N 2 . 
         [0042]    The circuit  2 - 20  in  FIG. 2   e  depicts the replacement of the inventive source follower and RC networks by the Dynamic Source Follower which has several terminals: VDD  2 - 22 , signal V in    2 - 6 , complementary signal  V in     2 - 8 , GRD (not shown) and DC bias voltage  2 - 21 . The signal is applied to the positive terminal while the complementary signal is applied to the negative terminal. The output of the Dynamic Source Follower is V out    2 - 23 . By comparing  FIG. 2   d  and  FIG. 2   e , The Dynamic Source Follower comprises the two series devices N 1  and N 2  coupled between two power supplies VDD and GRD (ground). In addition, a first RC network C n2  and R n2  acts as a high pass filter and couples the high frequency components of a first input signal (  V in     2 - 8 ) to the N 1  device. The first RC network also acts as a low pass filter and couples a first biasing DC voltage component to the N 1  device. 
         [0043]    The second RC network C n1  and R n1  acts as a high pass filter and couples the high frequency components of a second input signal (V in    2 - 6 ) to the N 2  device. The second RC network also acts as a low pass filter and couples a second biasing DC voltage component (from VDD) to the N 2  device. An output signal  2 - 23  is generated at the output of the Dynamic Source Follower. 
         [0044]    In accordance with another embodiment of the invention, the differential source follower  2 - 10  as illustrated in  FIG. 2   f  can offer an overall AC voltage gain of 6 dB and improved noise immunity by extending the inventive concept to a differential network. In accordance with another embodiment of the invention, a differential signal output stage is created by using a first  2 - 13  and second  2 - 14  inventive source follower stage forming a differential interface  2 - 10 . The first source follower  2 - 13  is driven by the signals V in    2 - 6  and  V in     2 - 8  and generates a first output signal by the summation of the generated output signal components V outt    2 - 7  and V outb    2 - 9 , respectively. The second source follower  2 - 14  is also driven by the same two input signals  V in     2 - 8  and V in    2 - 6  and but these inputs are applied to the second source follower  2 - 14  in a complementary manner when compared to the first source follower  2 - 13 . The second source follower  2 - 14  is driven by the input signals  V in     2 - 8  and V in    2 - 6  to generate the output signal components  V outt     2 - 12  and  V outb     2 - 11 , respectively. The summation of the output signal components  2 - 11  and  2 - 12  has the same magnitude as the summation of the output signal components  2 - 7  and  2 - 9 , but with a phase reversal since the inputs to the second source follower are flipped. The differential peak to peak AC voltage gain measured between the two outputs of the invention is 6 dB. The AC voltage gain of the differential stage in  FIG. 2   f  is given by equation (1): differential stage in  FIG. 2   f  is given by equation (1): 
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         [0045]      FIG. 2   g  depicts the circuit  2 - 15 S with RC networks and the current source applied to the circuit shown in  FIG. 2   f  in accordance with another embodiment of the invention. The device N 3    2 - 16  is connected in a saturation configuration and is part of the current mirror with devices N 1  and N 4 . By scaling the size of the load device N 1  with respect to N 3  allows the current in the first source follower to be adjusted. Note the bias current I bias  creates a DC voltage due to the device N 3  and is applied to the device N 1  in the first source follower through a low pass filter comprising of R n2  and C n2 ; simultaneously, the input signal  V in     2 - 8  is applied through the high pass filter to the load device N 1  comprising of the same two components C n2  and R n2 . Thus, the load device N 1  is biased to the correct voltage and simultaneously the signal  V in     2 - 8  is also applied to the load device N 1 . 
         [0046]    The RC network of R n1  and C n1  in first source follower of  FIG. 2   g  provides a high pass and low pass function for the active device N 2 . The low pass circuit filters VDD to the active device N 2  enabling the n-channel device. Concurrently, the input V in  is applied through the RC high pass network of C n1  and R n1 . The second source follower operates in a similar way except that the inputs are applied to the second source follower using complementary inputs. 
         [0047]    The differential circuit  2 - 27  in  FIG. 2   h  depicts the replacement of both of the inventive source follower and RC networks by the Dynamic Source Followers  2 - 28  and  2 - 29  which each have several terminals: VDD, signal V in , complementary signal  V in   , GRD (not shown) and a DC bias voltage. The outputs of the differential Dynamic Source Follower are V out  and  V out   . By comparing  FIG. 2   g  and  FIG. 2   h , one of the Dynamic Source Follower  2 - 28  comprises the two series devices N 1  and N 2  coupled between two power supplies VDD and GRD (ground). In addition, a first RC network C n2  and R n2  acts as a high pass filter and couples the high frequency components of a first input signal (  V in   ) to the N 1  device. The first RC network also acts as a low pass filter and couples a first biasing DC voltage component to the N 1  device. The second RC network C n1  and R n1  acts as a high pass filter and couples the high frequency components of a second input signal (V in ) to the N 2  device. The second RC network also acts as a low pass filter and couples a second biasing DC voltage component (from VDD) to the N 2  device. An output signal  2 - 23  is generated at the output of the Dynamic Source Follower. The other Dynamic Source Follower  2 - 29  operates the same way except that the two inputs V in  and  V in    are flipped when compared to  2 - 28 . 
         [0048]    The Sallen-Key filter  3 - 1  is depicted in  FIG. 3   a  which corresponds to a portion of the filter  1 - 6  in  FIG. 1   a  in accordance with another embodiment of the inventive idea. The second filter cascaded between the output of the first filter and the input to the Programmable Gain Amplifier PGA  1 - 7 . Note that the source follower in the first filter provides the low output impedance of 
         [0000]    
       
         
           
             1 
             
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         [0000]    as required for the impedance of Z 1  in the second filter. The impedance of Z 1  in the second filter is also called the source impedance. The remaining components of the second filter: Z 2 -Z 4  and the operational amplifier are similar to that which was depicted in  FIG. 1   b.    
         [0049]    In accordance with another embodiment of the inventive concept, the  FIG. 3   b  illustrates the first and second Sallen-Key filters cascaded together. The Low Pass Filter LPF  1 - 6  in  FIG. 1   a  is formed by replacing the impedances with the appropriate capacitors and resistors in  FIG. 3   b . The LPF is between the BBAMP base band amplifier  1 - 5  and the Programmable Gain Amplifier PGA  1 - 7  as shown in  FIG. 1   a . The output impedance Z 6  of the BBAMP at node V inf  is designed to provide a low impedance meeting the specification criteria required for the first element of the first filter. This low impedance is also called the source impedance. The output impedance Z 1  of the first filter at node V′ outf  is also provides the low impedance of 
         [0000]    
       
         
           
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         [0000]    which is also the first element of the second filter. 
         [0050]      FIG. 3   c  illustrates the differential Sallen-Key filter  3 - 4  coupled between the differential outputs of the BBAMP  3 - 5  at nodes V inf  and  V inf    and the differential inputs of the PGA  3 - 10  at nodes V outf  and  V outf   . The BBAMP  3 - 5  provides the low output impedance (Z 6  and Z′ 6 ) that is required to satisfy the design requirements of the first filters ( 3 - 6  and  3 - 8 ). Inside the top filter chain are two cascaded Sallen-Key filters  3 - 6  and  3 - 7 . In between the cascaded filters  3 - 6  and  3 - 7 , at node V′ outf , the output impedance of the first filter  3 - 6  is the input impedance of the second filter  3 - 7 . Similarly, the lower filter chain also contains two Sallen-Key filters  3 - 8  and  3 - 9 . Identically positioned elements have the same characteristics; for example, the impedances Z 9 =Z 4 =Z′ 9 =Z′ 4 . 
         [0051]      FIG. 4   a  illustrates a Sallen-Key filter  4 - 1  in accordance with another embodiment of the inventive idea. The resistance R 1  is not illustrated but is presented to this circuit when the previous stage is coupled to the input node V′ outf . The capacitance C 3  couples the input signal V′ outf  to the output signal V outf  while the impedances R 2  and C 4  form a voltage divider between V′ outf  and GRD (or VSS) generating V in . The operational amplifier requires both an input signal V in    4 - 4  and its complement  V in     4 - 5 . 
         [0052]    By comparing the equivalent Sallen-Key filter  4 - 1  depicted in  FIG. 4   a  with the circuit  4 - 3  in  FIG. 4   b  illustrates that the operational amplifier  1 - 15  in  FIG. 4   a  can be substituted by the RC networks of C n1 -R n1  and C n2 -R n2  along with the devices N 1  and N 2  in  FIG. 4   b . The reason for the substitution is that the output and input impedances of the operational amplifier and the RC networks of C n1 -R n1  and C n2 -R n2  along with the devices N 1  and N 2  have similar characteristics. Both have a high input impedance and a low output impedance. Furthermore, due to the current mirror formed by N 3  and N 1 , the reference current I bias  adjusts the current flow in N 1 . In turn, the output impedance Z 5  or 
         [0000]    
       
         
           
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         [0000]    can be altered by adjusting the current flow through the two series coupled devices N 1  and N 2 . 
         [0053]    The distribution of sheet resistance values over process variations causes variations in the desired value of the resistance R 2  which can affect the operation of the Sallen-Key filter in the field. To maintain one desired behavior in the filter, the ratio of R 2  to Z 5  needs to be matched. Since the output impedance of the inventive Sallen-Key filter can be changed by altering the I bias  reference current, the current I bias  can be adjusted until the value of 
         [0000]    
       
         
           
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               m 
             
           
         
       
     
         [0000]    or Z 5  matches the required ratio compared to R 2 . Thus, the inventive concept can compensate the filter for process variations. 
         [0054]      FIG. 4   c  illustrates the Dynamic Source Follower  4 - 7  replacing the RC networks of C n1 -R n1  and C n2 -R n2  along with the devices N 1  and N 2  given in  FIG. 4   b . As depicted in  FIG. 4   c , when the Dynamic Source Follower  4 - 7  is substituted for the operational amplifier  1 - 15 , the signal V in    4 - 4  is applied to the positive input Dynamic Source Follower. However, a signal  V in     4 - 5  is required for the negative input of the Dynamic Source Follower but is currently not available. As will be seen shortly, this signal is available in a differential filter design.  FIG. 4   d  presents a generalized Sallen-Key filter  4 - 8  since the resistors and capacitors of  FIG. 4   c  are replaced by impedances. 
         [0055]    As depicted in  FIG. 5   a , a differential Sallen-Key filter (for example, the 3-7 and 3-9 filters of  FIG. 3   c ) generates both signals  V in    and V in  internally. As discussed earlier, in order to achieve the negative feedback to the operational amplifier, the negative input to the operational amplifiers would require a feedback signal from the output of the operational amplifier. The operational amplifier  1 - 15  as illustrated in  FIG. 5   a  requires an internal feedback path to maintain the stability of the operational amplifier. A differential amplifier typically contains several devices, incorporates a input and output stage, and uses an RC feedback path to maintain stability. The device count and feedback adds additional circuit components and limits the high frequency performance of the operational amplifier since the delay in the feedback loop limits the maximum performance that can be achievable in the operational amplifier and ultimately the Sallen-Key filter. 
         [0056]    The operational amplifiers  1 - 15  and  1 - 15 ′ can be replaced by the Dynamic Source Followers  5 - 3  and  5 - 3 ′ as illustrated in  FIG. 5   b . In contrast, the Dynamic Source Followers  5 - 3  and  5 - 3 ′ in  FIG. 5   b  use feed forward signals to control the filter&#39;s operation and each Dynamic Source Follower only requires two devices. Since the Dynamic Source Follower does not use internal feedback and only two devices, the maximum performance limiting the operational amplifier due to the feedback path and large device count has been eliminated and thereby allows the Dynamic Source Follower to achieve a higher performance. In addition, the Dynamic Source Followers  5 - 3  and  5 - 3 ′ provide the feed forward signals  5 - 5  and  5 - 4  between the differential path. For example,  V in     5 - 5  is provided to the negative input of the Dynamic Source Follower  5 - 3  while V in    5 - 4  is provided to the negative input of the Dynamic Source Follower  5 - 3 ′. Thus, since the operational amplifiers  1 - 15  and  1 - 15 ′ have been eliminated thereby eliminating the internal stability feedback loop issue and reducing the device count, the circuit in  FIG. 5   b  should outperform the circuit shown in  FIG. 5   a  since the Dynamic Source Followers only requires a feed forward signal and a minimum of two devices. 
         [0057]    The cascaded differential Sallen-Key filter presented in  FIG. 3   c  when used as a low pass filter  6 - 1  is further illustrated in  FIG. 6   a  after the operational amplifiers are replaced by the source followers and the impedances replaced by resistors or capacitors to form the LPF. This is one of the circuits used for the LPF  1 - 6  in  FIG. 1 . On the left side is the BBAMP Differential Output  3 - 7  while the right side couples to the PGA Differential Input  3 - 10 . The voltage of the current source caused by I bias  is duplicated to devices N 6 , N 1  and N 4  through the symbols C 2 -C 4  defined in  FIG. 6   b . Similar subscript numbers of the impedances correspond to each other in the two FIGS., for example, Z 8 , Z 7 , Z 9 , Z 3 , Z 2  and Z 4  in  FIG. 3   c  corresponds to C 8 , R 7 , C 9 , C 3 , R 2  and C 4  in  FIG. 6   a . Each differential section of the Sallen-Key filter contains two cascaded filters. The feedback paths joining the first two differential filters are paths  6 - 4  (joined by A) and  6 - 2 . The second cascaded differential filters have feedback paths  6 - 3  and  6 - 5  (joined by B). 
         [0058]    The gain of the second cascaded filter in  FIG. 6   a  is given by equation (2): 
         [0000]    
       
         
           
             
               
                 
                   
                     20 
                      
                     
                         
                     
                      
                     
                       log 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               outf 
                             
                             - 
                             
                               
                                 V 
                                 outf 
                               
                               _ 
                             
                           
                           
                             
                               V 
                               outf 
                               ′ 
                             
                             - 
                             
                               
                                 V 
                                 outf 
                                 ′ 
                               
                               _ 
                             
                           
                         
                         ) 
                       
                     
                   
                   ≅ 
                   
                     6 
                      
                     
                         
                     
                      
                     dB 
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
         [0000]    while the gain of the first and second cascaded filters are given by ( 3 ) as: 
         [0000]    
       
         
           
             
               
                 
                   
                     20 
                      
                     
                         
                     
                      
                     
                       log 
                        
                       
                         ( 
                         
                           
                             
                               V 
                               outf 
                             
                             - 
                             
                               
                                 V 
                                 outf 
                               
                               _ 
                             
                           
                           
                             
                               V 
                               inf 
                             
                             - 
                             
                               
                                 V 
                                 inf 
                               
                               _ 
                             
                           
                         
                         ) 
                       
                     
                   
                   ≅ 
                   
                     12 
                      
                     
                         
                     
                      
                     dB 
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0059]    The cascaded differential LPF Sallen-Key filter is designed to have a cutoff frequency of about 900 MHz. This cutoff is determined by the low pass filter consisting of Z 1  (output impedance of the previous filter), R 2  and C 4 . However, V in2  is coupled to the device N 2  by the high pass filter formed by C n1 -R n . The high pass filter is designed to pass frequencies greater than 1 to 2 MHz. Thus, the initial 900 MHz bandwidth signal of the Sallen-Key filter is notched out at DC and up to 2 MHz. However, this loss of signal content does not affect the operation of the system since the design can still meet performance specifications. The I bias  current can also be adjusted to alter the bandwidth of the overall filter by altering the output impedance of the Dynamic Source Followers 
         [0000]    
       
         
           
             ( 
             
               1 
               
                 g 
                 m 
               
             
             ) 
           
         
       
     
         [0000]    by adjusting the current through the four mirrored devices; N 1 , N 4 , N 6  and N 8 . The bandwidth of the filter can be changed through I bias  to control the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of these four devices. 
         [0060]      FIG. 6   b  replaces all four source followers in  FIG. 6   a  with the block symbol Dynamic Source Followers  6 - 7  through  6 - 10 . The feed forward paths  6 - 4  provides the signal V in1  from the positive input of the Dynamic Source Followers  6 - 7  to the negative input of the Dynamic Source Followers  6 - 9 . Simultaneously, the feed forward paths  6 - 2  provides the signal  V in1    from the positive input of the Dynamic Source Followers  6 - 9  to the negative input of the Dynamic Source Followers  6 - 7 . Likewise, in the second differential cascaded filter the feed forward paths  6 - 5  provides the signal V in2  from the positive input of the Dynamic Source Followers  6 - 8  to the negative input of the Dynamic Source Followers  6 - 10 . Simultaneously, the feed forward path  6 - 3  provides the signal  V in2    from the positive input of the Dynamic Source Followers  6 - 10  to the negative input of the Dynamic Source Followers  6 - 8 . Thus, this differential double cascaded Sallen-Key LPF filter provides gain, increased bandwidth and a more stable system. 
         [0061]      FIG. 7   a  illustrates a circuit  7 - 1  where several current bias circuits ( 7 - 2  through  7 - 5 ) are used. The first bias current I bias  adjusts the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of the first cascaded stage of the filter while the second bias current I bias2  adjusts the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of the second cascaded stage of the filter. The two independent controls of the current bias I bias1  and I bias2  allow the bandwidth of the Sallen-Key filter to be altered in another dimension when compared to the circuit given in  FIG. 6   a . I bias1  controls the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of the first cascaded stage and I bias2  control the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of the second cascaded stage. In practice, the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of the first stage is slightly difference from the 
         [0000]    
       
         
           
             1 
             
               g 
               m 
             
           
         
       
     
         [0000]    of the second stage due to loading of PGA Differential Input  3 - 10 . The loading of the PGA  3 - 10  on the second cascaded Sallen-Key filter is different than the loading the second cascaded Sallen-Key presents to the first cascaded Sallen-Key filter. Thus, the total bandwidth of the entire chain (from BBMAP  3 - 7 , to the first Sallen-Key filter, to the second Sallen-Key filter to the PGA  3 - 10  and including the A to D (not shown) must be adjusted by the these filter controls. The independent adjustment of the two current biases I bias1  and I bias2  provides additional control to the adjustment of the bandwidth. 
         [0062]    Finally, it is understood that the above description are only illustrative of the principle of the current invention. Various alterations, improvements, and modifications will occur and are intended to be suggested hereby, and are within the sprit and scope of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the arts. It is understood that the various embodiments of the invention, although different, are not mutually exclusive. In accordance with these principles, those skilled in the art may devise numerous modifications without departing from the spirit and scope of the invention. Although the circuits were described using CMOS, the same circuit techniques can be applied to depletion mode devices and BJT or biploar circuits, since this technology allows the formation of current sources and source followers. When a device is specified, the device can be a transistor such as an N-MOS or P-MOS. The CMOS or SOI (Silicon on Insulator) technology provides two enhancement mode channel types: N-MOS (n-channel) and P-MOS (p-channel) devices or transistors. The implimentation of a low pass Sallen-Key filter was presented, although the Sallen-Key filter can be used to form bandpass and high pass filters. In addition, a network and a portable system can exchange information wirelessly by using communication techniques such as TDMA (Time Division Multiple Access), FDMA (Frequency Division Multiple Access), CDMA (Code Division Multiple Access), OFDM (Orthogonal Frequency Division Multiplexing), UWB (Ultra Wide Band), WiFi, WiGig, Bluetooth, etc. The network can comprise the phone network, IP (Internet protocol) network, LAN (Local Area Network), ad hoc networks, local routers and even other portable systems.