Abstract:
A communication data processing device according to an aspect of the invention comprises a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a communication data transfer device, and more particularly to a data transfer device acquiring data stored in memory and executing an alignment process for packet communications.  
         [0003]     2. Description of Related Art  
         [0004]     In association with progress and wide use of network technology as represented by the Internet, many computers are connected to networks for data communication with other computers. Typically, a computer is connected to a LAN (Local Area Network), as represented by Ethernet, for data communications with other computers within the LAN, and connected to external networks via the LAN.  
         [0005]     Data is transferred via a network controller within the computer. The network controller executes the necessary processing for data acquired from the main memory, and outputs the created packet data to the LAN. Furthermore, the necessary processing for the packet data acquired from the LAN is executed, and that data is stored in the main memory.  FIG. 4  is a block diagram illustrating data processing for data transfer using a related technique.  
         [0006]      FIG. 4  shows the aligner  310  which consists a part of the network controller, and the main memory  350  which stores data. The aligner  310  and main memory.  350  send and receive data via the data bus  360 . The aligner  310  incorporates alignment logic  311  to align acquired data in a sequence for packet communications on the network. Furthermore, the aligner  310  also incorporates the FIFO  312  temporarily store data from the alignment logic  311  and output the stored data in the order of storage, and the sequencer  313  controlling reading of data from the main memory  350  and output of data from the FIFO  312 .  
         [0007]     In  FIG. 4 , aligned data is stored in the FIFO  312 . Each square in the FIFO  312  represents one byte of data. Furthermore, the hatched squares represent communication data valid for transfer, and the white squares represent communication data invalid for transfer. The alignment logic  311  aligns valid data into a contiguous sequence of data as shown in  FIG. 4  from data comprising both invalid and valid data.  
         [0008]     Data transfer processing in the system shown in  FIG. 4 , in particular, output processing of data stored in the main memory  350 , is described below. Firstly, the sequencer  313  issues a request to read data from the main memory  350  (MReq) ([1]). In response to the request, the data RDATA is read from the main memory  350 , and provided to the alignment logic  311  of the aligner  310  ([2]). The alignment logic  311  aligns the acquired data, and outputs ALRDATA to FIFO  312  ([3]).  
         [0009]     After transfer of data from the main memory  350  to the aligner  310  is completed, MAck indicating the completion is sent to the sequencer  313  ([4]). In response to MAck, the sequencer  313  outputs the Ct 1  signal controlling the FIFO  312  so that the data in the FIFO  312  is output in the next data processing block ([5]). This processing is repeated until no data remains to transfer. Additionally, a storage buffer with a plurality of data registers which processes a store request from the CPU to the memory is disclosed in Japanese Patent Application Laid-open No. 61-118853.  
         [0010]     In the technique described with reference to  FIG. 4 , data input from the main memory main memory  350  to the alignment logic  311  requires waiting for completion of output of the prescribed number of bytes from the FIFO  312 . For example, when 64 bytes of data are read from the main memory  350 , it is needed that the full FIFO  312  outputs 64 bytes of data to prepare free space sufficient for storage of 64 bytes of data, and data is then transferred from the main memory  350 .  
         [0011]     It has now been discovered that, however, since other circuit configurations also use data bus  360 , it may not be possible to start data transfer from the main memory  350  at the timing when free space becomes available in the FIFO  312 . If data cannot be read from the main memory  350  at the desired timing, dead time is introduced to delay data transfer.  
         [0012]     In particular, the speed of data transfer in networks is increasing in association with recent progress in semiconductor technology and data processing technology. For example, Ethernet data transfer speed has increased from 10 Mbps, to 100 Mbps, and subsequently to 1 Gbps. Thus, latency from the main memory  350  to the aligner  310  can form a bottleneck, and cause an inability to accommodate external data transfer speeds.  
         [0013]     Additionally, it is necessary to input data read from the main memory  350  to the FIFO in the sequence in which it was read. Thus, read commands must be issued and completed individually and independently, and the efficiency of the bus use cannot be improved by interleaving the commands.  
       SUMMARY OF THE INVENTION  
       [0014]     According to an aspect of the invention, there is provided a data transfer device transferring data acquired from a memory comprising a plurality of buffer memories temporarily storing data from a memory and being capable of receiving and providing data independently of each other, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.  
         [0015]     According to another aspect of the invention, there is provided a communication data processing device comprising, a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.  
         [0016]     According to still another aspect of the invention, there is provided a data transfer method for transferring data acquired from a memory to a packet communication network comprising, storing data acquired from a memory in a plurality of buffer memories being capable of receiving and providing data independently of each other, selecting a buffer memory from the plurality of buffer memories, and aligning input data from the selected buffer memory in a sequence corresponding to a packet communication.  
         [0017]     With the plurality of buffer memories, alignment processing for data acquired from the memory, and transfer of aligned data, can be executed efficiently. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:  
         [0019]      FIG. 1  is a block diagram showing the configuration in outline of the communication data processing system in the first embodiment;  
         [0020]      FIG. 2  is a diagram describing transfer processing of communication data in the communication data processing system in the first embodiment;  
         [0021]      FIG. 3  is a diagram describing transfer processing of communication data in the communication data processing system in the second embodiment; and  
         [0022]      FIG. 4  is a diagram describing transfer processing of communication data in the communication data processing system with conventional technology. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     First Embodiment  
       [0023]      FIG. 1  is a schematic block diagram showing the configuration of the communication data processing system  100  according to the present embodiment. As shown in  FIG. 1 , the communication data processing system  100  comprises a main memory  110  storing communication data, and a data transfer section  120  transferring data acquired from the main memory  110 . A typical example of the data transfer section  120  is a network controller connected to a LAN and the like. The data transfer section  120  has an aligner  130  to align data acquired from the main memory  110  to form the packet data to be sent. The main memory  110  and the aligner  130  execute data communications via the data bus  140 .  
         [0024]     The main memory  110  stores communication data input from an external source, and communication data to output to an external destination. The main memory  110  also stores the necessary data in response to requests from other circuit configurations (not shown in the figure). While communication packet data is in the form of a byte stream, data is read from the main memory  110  in 32-bit width or 64-bit width, for example.  
         [0025]     The aligner  130  has a plurality of register files  131   a  through  131   n  (hereafter referred to collectively as ‘register file  131 ’) which are examples of buffer memories temporarily storing data acquired from the main memory  110 . The register files  131  can receive and provide data independently of each other. Each register file  131  operates individually, and can write and read data independently of other register files. While data is being written to a register file  131 , the aligner  130  read data from another register file  131 .  
         [0026]     The aligner  130  also has alignment logic  132  to align data from the register files  131  in the prescribed sequence. The alignment logic  132  aligns, for example, acquired data in sequence for Ethernet packet communications. Data acquired from the main memory  110 , which is 32-bit width or 64-bit width for example, includes both valid data and invalid data as communication data. The alignment logic  132  reorders this data and arranges it in the prescribed byte width for the communication protocol, allowing efficient creation of packet data in subsequent processing. Output data from the alignment logic  132  is transferred to block  125  in which the next data processing within the data transfer section  120  is executed.  
         [0027]     Data from the register files  131  is input to the alignment logic  132  via the selector  133 . The selector  133  selectively outputs data from a plurality of register files  131  to the alignment logic  132 . Thus, data stored in a plurality of register files  131  can be transferred to the alignment logic  132  in the required sequence. The selector  133  selects one of a plurality of register files  131  according to a request queued in the alignment request queue  134 . In  FIG. 1 , three requests are placed in the alignment request queue  134 , however the number of requests is not limited to three.  
         [0028]     The sequencer  135  executes control processing in the communication data processing system  100 . In particular, it controls reading data from the main memory  110  to the register files  131 , and controls output of data from the register files  131  to the alignment logic  132 . Control of input of data from the main memory  110  to the register files  131  is executed by placing a request in the bus request queue  136 . Furthermore, by placing a request in the alignment request queue  134 , the sequencer  135  controls selection of data read from the register files  131  and provided to the alignment logic  132 . The number of requests placed in the bus request queue  136  is selected through design to allow efficient processing.  
         [0029]     As mentioned before, the sequencer  135  executes the control processing in response to control signals from other elements of the configuration. In practice, the sequencer  135  controls transfer of data within the communication data processing system  100  in response to, for example, the request reception completion signal from the bus arbiter  141 , and the ready signal from the register files  131 .  
         [0030]     The data bus  140  is shared in common by a plurality of circuit configurations, including circuit configurations not shown in the figures. Thus, data communications via the data bus  140  is controlled by the bus arbiter  141 . The bus arbiter  141  arbitrates use of the data bus  140 .  
         [0031]     In  FIG. 1 , the bus arbiter  141  controls data transmission on the data bus  140  in response to a request queued in the bus request queue  136 . The bus system of the present embodiment can issue differing data read requests, and execute and complete readings of data from the main memory  110  corresponding to these requests in a order different from the request issue. In other words, the bus system can determine the issue sequence of data read requests and the execution sequence of actual reading independently.  
         [0032]     For example, when the first read command is issued for the bus arbiter  141 , followed by issue of the second read command, reading of data corresponding to the second read command can be completed first, followed by completion of reading of data corresponding to the first read command (as mentioned before, this out of sequence processing is generally referred to as a ‘split transaction’). Thus, the efficiency of use of the data bus  140 , and the overall efficiency of data transfer, are improved.  
         [0033]     Processing in the communication data processing system  100  of the present embodiment is described below in reference to  FIG. 2 .  FIG. 2  shows the sequence of control data and read data from the main memory  110  in the communication data processing system  100 . In the present example, the communication data processing system  100  has two register files  131   a  and  131   b.  Each register file  131   a  and  131   b  can store 64 bytes of data. One square in each register file  131   a  and  131   b  represents one byte of data.  
         [0034]     The request Req (Reg 0 ) requesting reading of data from the main memory  110  to the register file  131   a  (Reg 0 ), and the request Req (Reg 1 ) requesting reading of data from the main memory  110  to the register file  131   b  (Reg 1 ), are each queued in the bus request queue  136 . The issuing order is Req (Reg 0 ) followed by Req (Reg 1 ).  
         [0035]     The bus request queue  136  issues the Req (Reg 0 ), which is a data read request to Reg 0 , to the bus arbiter  141  ([1]) in response to a request from the sequencer  135 . In response to the Req (Reg 0 ), the bus arbiter  141  returns Ack (Reg 0 ), indicating that reception of the request has been completed, to the sequencer  135  ([2]) In response to Ack (Reg 0 ) from the bus arbiter  141 , the sequencer  135  requests the bus request queue  136  to issue the Req (Reg 1 ) which is a request for reading of data to the register file  131   b  (Reg 1 ) ([3]).  
         [0036]     The bus request queue  136  issues Req (Reg 1 ) to the bus arbiter  141  ([4]) in response to a request from the sequencer  135 . The bus arbiter  141  returns Ack (Reg 1 ), indicating that reception of the request has been completed, to the sequencer  135  in relation to Req (Reg 1 ) ([5]). Here, Req (Reg 1 ) is issued before the data response is returned to the register file  131   a  (Reg 0 ) for Req (Reg 0 ) Read data has not therefore been written to the register file  131   a  (Reg 0 ) at this timing.  
         [0037]     Then, in response to Req (Reg 0 ) from the bus arbiter  141  to the main memory  110 , read data corresponding to Req (Reg 0 ) is written to the register file  131   a  (Reg 0 ) from the main memory  110  via the data bus  140  ([6]).  FIG. 2  shows the state in which data has been written to the register file  131   a  (Reg 0 ). In the present example, data of 64 bits width can be read from the main memory  110 , and the register file  131   a  stores 64 bits of data. In the register file  131   a,  data valid as transferred communication data is represented by hatched squares, and invalid data is represented by white squares.  
         [0038]     In response to writing data, the register file  131   a  sends a ready signal (Rdy 0 ) to the sequencer  135  indicating that preparations for data transfer (output) are completed ([7]). In response to Rdy 0 , the sequencer  135  places the alignment request ALReq 0  in the alignment request queue  134  ([8]). ALReq 0  is a request to execute alignment processing of data stored in the register file  131   a.    
         [0039]     The control signal (Sel 0 ) corresponding to ALReq 0  is output from the alignment request queue  134  to the selector  133  ([9]) The selector  133  selects the register file  131   a  in accordance with the control signal, and transfers the data read from the register file  131   a  to the alignment logic  132 . The alignment logic  132  executes alignment processing to align the sequence of the input data.  
         [0040]     Data can be transferred from the main memory  110  to the register file  131   b  while data is being transferred from the register file  131   a  to the alignment logic  132 , or while the alignment logic  132  is executing alignment processing. In response to Req (Reg 1 ) sent from the bus arbiter  141  to the main memory  110 , read data corresponding to Req (Reg 0 ) is written to the register file  131   b  (Reg 1 ) from the main memory  110  via the data bus  140  ([10]).  FIG. 2  shows the state in which 64-byte data is stored in the register file  131   b,  similar to the register file  131   a.    
         [0041]     The register file  131   b  outputs Rdy 1  to the sequencer  135  in response to completion of data storage ([11]). The sequencer  135  places ALReq 1  in the alignment request queue  134  in response to Rdy 1  ([12]). The sequencer  135  waits for completion of alignment processing of data from the register file  131   a  if the alignment processing is not yet completed.  
         [0042]     When the processing is completed, or when the processing has already been completed, the sequencer  135  requests output of the control signal corresponding to ALReq 1  to the alignment request queue  134 . In response to the request, the alignment request queue  134  outputs a control signal (Sel 1 ) to the selector  133  instructing selection of the register file  131   b  ([13]). The selector  133  selectively outputs data read from the register file  131   b  to the alignment logic  132 . Alignment logic  132  processing is similar to that described above.  
         [0043]     As described above, the data transfer section  120  of the present embodiment has a plurality of register files  131 , wherein data read from the main memory is being stored in one register file during data reading from another register file and its alignment processing. Thus, data can be efficiently transferred from the main memory to the alignment logic, and the data transfer section  120  can accommodate high-speed communications.  
         [0044]     Although two register files are shown in  FIG. 2 , as shown in  FIG. 1 , the data transfer section  120  can have three or more register files. The greater number of register files, the more efficient data transfer from the main memory  110  to the alignment logic  132  is achieved. This is similar in the following embodiment.  
       Second Embodiment  
       [0045]     Other features of the communication data processing system  100  are described in reference to  FIG. 3 . As described above, the bus system of the present embodiment accommodates split transactions. As mentioned before, data is read from the main memory  110  in accordance with the sequence of the request, however in the present embodiment, data is read from the main memory  110  in a sequence differing from the request. The process until the bus arbiter  141  returns Ack (Reg 1 ) to the alignment logic  132  ([5]) is similar to the process described in reference to  FIG. 2  and the detailed description is therefore omitted.  
         [0046]     The main memory  110  transfers read data corresponding to Req (Reg 1 ) to the register file  131   b  before transferring read data corresponding to Req (Reg 0 ) ([6]). Responsive to completing storage of read data from the main memory  110 , the register file  131   b  sends Rdy 1  to the sequencer  135  ([7]). Alignment processing by the alignment logic  132  is required to follow the sequence in which the Req was issued to the main memory  110 . Thus, the sequencer  135  waits for transfer of data corresponding to Req (Reg 0 ) without placing ALReq 1  in the alignment request queue  134 .  
         [0047]     When the register file  131   a  stores data transferred from the main memory  110  ([8]), the register file  131   a  sends Rdy 0  to the sequencer  135  ([9]). In response to acquisition of Rdy 0 , the sequencer  135  places the alignment request ALReq 0  in the alignment request queue  134  ([10]). The control signal Sel 0  corresponding to ALReq 0  is [then] output to the selector  133  from the alignment request queue  134  ([11]). The selector  133  selects the register file  131   a  in accordance with the control signal, and transfers data read from the register file  131   a  to the alignment logic  132 . The alignment logic  132  executes alignment processing in which the sequence of the input data is rearranged.  
         [0048]     After queuing ALReq 0 , the sequencer  135  places ALReq 1  in the alignment request queue  134  ([12]). When alignment processing of the data from the register file  131   a  is complete, the alignment request queue  134  outputs the control signal Sel 1  in related with ALReq 1  to the selector  133  in response to the request from the sequencer  135  ([13]). The selector  133  selects and outputs data from the register file  131   b  to the alignment logic  132  in response to the control signal. The alignment logic  132  executes alignment processing to align the sequence of the input data.  
         [0049]     In the present embodiment, the communication data processing system  100  reads data from the main memory  110  in a sequence differing from the sequence of the requests queued in the bus request queue  136  with the use of split transactions according to the usage status of the data bus  140 . Thus, a combination of a data transfer section  120  having a plurality of register files, and a bus system conducting split transaction processing make it possible to execute overall processing in the communication data processing system  100  efficiently.  
         [0050]     It is apparent that the present invention is not limited to the above embodiment that may be modified and changed without departing from the scope and spirit of the invention.