Abstract:
A device includes a serial port for connecting as a slave to a master device through a serial link. The device further includes a detection circuit for detecting the presence of an impedance of the master device, linked to a terminal of the serial port. The device can be used with microprocessor cards comprising a USB port.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to peripherals comprising a serial port for connecting to a master device, like a computer or a hub, via a serial link.  
         [0003]     2. Description of the Related Art  
         [0004]     The present invention more particularly relates to peripherals comprising a serial port of the USB type (Universal Serial Bus), for connecting to a master device.  
         [0005]     A serial port of the USB type comprises four connection terminals, that is two differential data transmission terminals, and two positive and negative power supply terminals able to supply continuous current to the peripheral.  
         [0006]     Usually, a master device comprises means for detecting the connection and disconnection of a peripheral device of the USB type. This detection function does not exist on the side of a peripheral of the USB type. However, a peripheral can be connected to a master device with one and/or the other transmission links faulty, so that the peripheral is powered by the USB link but cannot communicate with the master device. If it is a secured device, like microprocessor cards memorizing secret information, fraudsters can try to discover these secret information by powering on the card and taking measures on the data transmission terminals.  
         [0007]     It is therefore desirable to be able to adapt the operating mode of the peripheral depending on whether it is connected to a master device, and particularly to determine whether the peripheral can securely communicate through the serial link.  
         [0008]     The detection by a peripheral of a master device connected to the peripheral via a USB link sometimes raises several issues.  
         [0009]     First, the USB standard 2.0 provides three data transmission speeds, that is a Low Speed of 1.2 Mb/s, a Full Speed of 12 Mb/s and a High Speed of 480 Mb/s. The master device must be able to detect the transmission speed used by the peripheral. However, according to the USB standard, the selection of one of these transmission speeds is performed by the master device according to some features of the serial port of the peripheral. In particular, a peripheral of the USB type comprises a pull-up resistor connectable to one or the other data transmission terminal of the USB port, according to the transmission speed compatible with the peripheral. This speed is determined by the master device by detecting whether one or the other positive or negative data transmission terminal is connected to this resistor. If this resistor is connected to the positive transmission terminal, the USB port of the peripheral operates at full speed. If this resistor is connected to the negative transmission terminal, the USB port of the peripheral operates at low speed. At last, if this resistor is not connected to any transmission terminals, the peripheral operates at high speed.  
         [0010]     Next, the USB standard imposes voltage levels on data transmission terminals. Particularly, the voltage must not simultaneously exceed 0.8 Volt on both data transmission terminals.  
       BRIEF SUMMARY OF THE INVENTION  
       [0011]     One embodiment of the present invention overcomes these problems and enables a peripheral to detect the presence of a master device to which it is connected through a serial link.  
         [0012]     One embodiment of the invention is a device comprising a serial port for connecting itself as a slave to a master device via a serial link. According to one embodiment of the invention, the device comprises a detection circuit for detecting the presence of an impedance of a master device, linked to a terminal of the serial port.  
         [0013]     According to one embodiment, the impedance detected by the detection circuit is a pull-down resistor.  
         [0014]     According to one embodiment, the impedance detected by the detection circuit is a resistor with a value comprised within a range of values.  
         [0015]     According to one embodiment, the detection circuit comprises a bias stage for generating a measure voltage on the terminal of the serial port, and a detection stage comprising at least one comparator for comparing the measure voltage to a reference voltage.  
         [0016]     According to one embodiment, the detection stage comprises two comparators for comparing the measure voltage to a high reference voltage and a low reference voltage, and means for generating a detection signal indicating whether the measure voltage is comprised between the high and low reference voltages.  
         [0017]     According to one embodiment, the detection circuit comprises a first detection stage of a first pull-down resistor of a master device, linked to a first terminal of the serial port, and a second detection stage of a second pull-down resistor of the master device, linked to a second terminal of the serial port.  
         [0018]     According to one embodiment, the detection circuit comprises a bias stage for generating a first measure voltage on the first terminal of the serial port, and a second measure voltage on the second terminal of the serial port, each detection stage comprising at least one comparator for comparing the measure voltage to a reference voltage.  
         [0019]     According to one embodiment, each measure voltage is lower than 0.8 Volt, even if there is not any pull-down resistors of a master device connected to the terminals of the serial port.  
         [0020]     According to one embodiment, the detection circuit comprises means for generating a detection signal indicating whether the two detection stages detect the presence of a pull-down resistor with a value comprised within a range of values.  
         [0021]     According to one embodiment, each detection stage comprises two comparators for comparing the measure voltage to a high reference voltage and a low reference voltage, and means for generating a detection signal indicating whether the measure voltage is comprised between the high and low reference voltages.  
         [0022]     According to one embodiment, the first and second terminals of the serial port are dedicated to data transmission in differential form.  
         [0023]     According to one embodiment, the detection circuit is powered through third and fourth terminals of the serial port.  
         [0024]     According to one embodiment, the detection circuit is deactivated after detecting a master device, and before establishing a communication through the serial link.  
         [0025]     According to one embodiment, the serial port is of the Universal Serial Bus type.  
         [0026]     According to one embodiment, the device is an integrated circuit.  
         [0027]     According to another embodiment, a method for establishing data communication between a master device coupled to a slave device via a serial link, where the slave device has a serial port and the serial port has data terminals, includes determining whether an impedance of the master device is between a low impedance value and a high impedance value, and establishing data communication if the impedance of the master device is between the low impedance and high impedance values.  
         [0028]     According to a further embodiment of the invention, a system for establishing data communication over a serial link connecting a master device and a slave device, where the master device has a means for detecting data transmission speed and the slave device has a serial port having a data terminal, includes a means for disabling the data transmission speed detection means, a means for determining whether an impedance of the master device is between a low impedance value and a high impedance value, a means for enabling the data transmission speed detection means if the impedance is between the low impedance value and the high impedance value, and a means for establishing data communication over the serial link if the impedance is between the low and high impedance values. 
     
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)  
       [0029]     These and other advantages and features of the present invention will be presented in greater detail in the following description of the invention in relation to, but not limited by the following figures:  
         [0030]      FIG. 1  shows, in block form, a master device connected to a peripheral through a USB linked at full speed, according to an embodiment of the invention;  
         [0031]      FIG. 2  shows, in block form, a master device connected to a peripheral through a USB link at low speed, according to an embodiment of the invention;  
         [0032]      FIG. 3  shows, in block form, an interface circuit of a USB port of a peripheral equipped with a master device detection circuit according to an embodiment of the invention;  
         [0033]      FIG. 4  shows an embodiment of a detection circuit according to the invention; and  
         [0034]      FIG. 5  is a diagram of a startup procedure executed by a peripheral equipped with a detection circuit according to an embodiment of the invention. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0035]      FIGS. 1 and 2  show a master device H constituted by a computer or a hub, connected through a serial link SL of the USB type to a slave device or peripheral P. The master device H comprises an interface circuit USBT1 connected to a serial port comprising two positive and negative data transmission terminals D+, D−. Each terminal D+ and D− is connected to a line of differential data transmission of the serial link SL. The master device comprises two pull-down resistors Rpd. Each resistor respectively links a data terminal D+, D− of the serial port to the ground.  
         [0036]     The peripheral P also comprises an interface circuit USBT2 connected to a serial port comprising two terminals D+, D− connected to the data transmission lines of the serial link SL.  
         [0037]      FIG. 1  illustrates the case where the transmission between the master device H and the peripheral P is performed at full speed. In that case, the positive data transmission terminal D+ of the peripheral P is linked to the supply voltage Vcc supplied by the link USB by means of a pull-up resistor Rpu mounted in series with a switch  11 .  
         [0038]      FIG. 2  illustrates the case where the link USB SL between the master device H and the peripheral P is at low speed. In that case, the pull-up resistor Rpu connected to the power supply Vcc is linked to the negative data transmission terminal D− via a switch  12 .  
         [0039]      FIG. 3  shows the interface circuit USBT2 of the peripheral P.  FIG. 3  shows the four connection terminals of the USB serial port of the peripheral. These four terminals comprise two positive and negative continuous power supply terminals VBUS, GND at about  3 . 3  Volts, and the two differential data transmission terminals D+, D− described hereinbefore and shown in  FIGS. 1 and 2 . The circuit USBT 2  comprises send buffer memories DPT, DMT, single-ended receivers DPR, DMR, and a differential receiver DIFR. The positive data transmission terminal D+ is connected to the output of the send buffer memory DPT, to the input of the receiver DPR, and to a positive input of the differential receiver DIFR. The negative data transmission terminal D− is connected to the output of the send buffer memory DMT, to the input of the receiver DMR, and to a negative input of the differential receiver DIFR. The power supply terminals VBUS and GND power a DC voltage regulator DCREG. The regulator DCREG supplies a supply voltage of 3 Volts to the receivers DPR, DIFR, DMR and to the send buffer memories DPT, DMT. The receivers DPR, DIFR, DMR respectively supply data signals DPRO, DIFO and DMRO carrying the data transmitted by the link SL. The send buffer memories DPT, DMT receive from the peripheral P data signals DPOS, DMOS to be emitted on the link SL.  
         [0040]     The interface circuit USBT2 comprises a detection circuit DCT enabling the peripheral P to detect whether it is connected to a master device H through a link of the USB type.  
         [0041]      FIG. 4  shows an embodiment of the detection circuit DCT shown in  FIG. 3 . The detection circuit DCT comprises a DC voltage generator VGEN, powered by the power supply terminals VBUS, GND of the USB port. The voltage generator VGEN supplies a continuous voltage Vg+, through a resistor Rd+, to the positive data terminal D+ of the USB port of the peripheral. Likewise, the voltage generator VGEN supplies a continuous voltage Vg−, through a resistor Rd−, to the negative data terminal D− of the USB port.  
         [0042]     The voltage generator VGEN thus applies to the positive and negative data terminals measure voltages Vm+ and Vm− with resistors Rpd possibly connected by a serial link SL to the terminals D+ and D−.  
         [0043]     The voltage generator VGEN also applies a continuous voltage Vg to a group of three resistors R 1 , R 2 , R 3  mounted in series, the resistor R 1  being connected to the generator VGEN, and the resistor R 3  being connected to the ground, that is the ground terminal GND of the USB port of the peripheral P. The resistors R 1  and R 2  form a first divider bridge supplying a high reference voltage VH in their junction node. In the same way, the resistors R 2  and R 3  form a second divider bridge supplying a low reference voltage VL in their junction node.  
         [0044]     The detection circuit DCT also comprises two detection stages DST 1 , DST 2 , each comprising two comparators C 1 , C 2 , C 3 , C 4  which outputs are connected to the inputs of an AND gate AG 1 , AG 2 . The outputs ER+, ER− of the gates AG 1 , AG 2  are connected to the inputs of another AND gate AG 3  which output supplies a signal of detection ER of a master device.  
         [0045]     The terminal D+ is connected to the negative input of the comparator C 1  and to the positive input of the comparator C 2 . In addition, the high reference voltage VH is applied to the positive input of the comparator C 1 , and the low reference voltage VL is applied to the negative input of the comparator C 2 . That way, the output of the gate AG 1  is pulled up if the value of the measure voltage Vm+ applied to the terminal D+ is comprised between the low VL and high VH reference voltages, and otherwise pulled down.  
         [0046]     In the same way, the terminal D− is connected to the negative input of the comparator C 4  and to the positive input of the comparator C 3 . The high reference voltage VH is applied to the positive input of the comparator C 4 , and the low reference voltage VL is applied to the negative input of the comparator C 3 . The output of the gate AG 2  is thus pulled up if the value of the measure voltage Vm− applied to the terminal D− is comprised between the low VL and high VH reference voltages, and otherwise pulled down.  
         [0047]     The detection signal ER at the output of the detection circuit is pulled up if the following conditions are simultaneously satisfied:
 
 VL&lt;Vm+&lt;VH   (1)
 
 VL&lt;Vm−&lt;VH   (2)
 
 and otherwise pulled down. 
 
         [0048]     If pull-down resistors Rpd are connected to the data lines D+, D− of the serial link SL, each forms with the resistor Rd− to which it is connected, a divider bridge to divide the voltage Vg+, Vg−. The data terminal D+, D− connected to the junction node of the resistors Rdp and Rd+ (or Rdp and Rd−) thus supplies a measure voltage Vm+, Vm− depending on the value of the resistor Rpd connected to the data terminal.  
         [0049]     If the resistors Rd+, Rd−, R 1 , R 2 , R 3  are all chosen substantially equal to a predefined resistor R, and if the voltages Vg+, Vg− and Vg supplied by the generator VGEN are substantially equal, the conditions (1) and (2) are equivalent to the following conditions:
 
⅓ &lt;Rpd /( Rpd+R )&lt;⅔  (3)
 
 or:
 
 R/ 2 &lt;Rpd&lt; 2 R   (4)
 
         [0050]     If the value of the resistor R is chosen near the one of the pull-down resistors, recommended by the USB standard, that is 15 kOhms, and if pull-down resistors Rpd are present on the USB link connected to the peripheral P, the conditions (4) are satisfied for each data terminal D+ and D−. On the other hand, these conditions are not satisfied if the data terminals D+ and D− are not connected to a USB port of a master device, that is if one and/or the other terminal D+ and/or D− of the peripheral is not connected to a pull-down resistor Rpd, or is in short-circuit with the ground.  
         [0051]     The detection circuit DCT which has just been described thus makes it possible to detect the presence of pull-down resistors Rpd of a master device H, connected to the positive D+ and negative D− data terminals of the USB port of the peripheral.  
         [0052]     In addition, if the continuous voltages Vg+, Vg− and Vg supplied by the generator VGEN are lower than 0.8 Volts, the detection circuit which has just been described complies with the condition SE1 specified in the USB standard, which imposes that the voltages applied to the terminals D+ and D− must not exceed a voltage Vose1 equal to 0.8 Volt at the same time.  
         [0053]      FIG. 5  shows a procedure  10  for starting-up the peripheral P according to the invention. At the startup of the peripheral, the peripheral controls the opening of the switch I 1  or I 2  depending on whether the USB link of the peripheral is at full or low speed, to disconnect the pull-up resistor Rpu (step  11 ). At the following step  12 , the peripheral tests the output signal ER of the detection circuit DCT. If the output signal is pulled up, it means that pull-down resistors Rpd of a master device H are linked by the link SL to the data terminals D+, D− of the peripheral P. In that case, the peripheral closes the switch I 1  or I 2  (step  13 ), and tries to establish a communication through its USB port with the master device thus detected (step  14 ).  
         [0054]     If at step  12  the detection signal ER is pulled-down (ER=0), it means that the detection circuit DCT has not detected, on each terminal D+, D−, the presence of a pull-down resistor Rpd having a correct value (conditions (4) not satisfied). The procedure  10  then ends without the peripheral trying to establish a communication through its serial port.  
         [0055]     The detection circuit DCT can also comprise a deactivation switch  13  controlled by the peripheral P ( FIG. 4 ). This switch allows the detection circuit to be deactivated when the peripheral is live and has detected the presence of a master device H.  
         [0056]     The switch  13  is for example interposed on a supply line of the voltage generator VGEN connected to the power supply terminal VBUS of the serial port. The switch  13  is closed at the start-up of the peripheral, and opened before establishing a communication with the master device, after the detection of the latter.  
         [0057]     It will be clear to those skilled in the art that the device according to the invention is susceptible of several variations. Thus, the invention does not necessarily apply to a USB link: it more globally applies to any serial link connecting a master device to a slave device. In addition, the impedance detected is not necessarily a pull-down resistor.  
         [0058]     The detection of the impedance is not necessarily performed on a data transmission line of the serial link. It can alternately be performed on a supply line of the serial link.  
         [0059]     In the case of a differential serial link, it is not necessary to detect the presence of an impedance on each data terminal D+ and D−. Only one of these two terminals can be subjected to the detection performed by the detection circuit. In that case, the voltage generator VGEN generates one measure voltage Vm+ or Vm− only, and the detection circuit DCT comprises one detection stage DST 1  or DST 2  only.  
         [0060]     In addition, it is not necessary to compare the measure voltage Vm+, Vm− to a high reference voltage and a low reference voltage. To simply detect the presence or the lack of a resistor, comparing the measure voltage with a high reference voltage is sufficient. To detect if a terminal of the serial port is linked to the ground, comparing the measure voltage to a low reference voltage is sufficient.