Abstract:
A power conversion apparatus, such as an uninterruptible power supply, included first and second DC busses, a neutral node and an inductor configured to be coupled to a load. The apparatus further includes an inverter circuit coupled to the first and second DC busses, to the neutral node and to the inductor and configured to selectively couple the first and second DC busses and the neutral node to a first terminal of the inductor to generate an AC voltage at a second terminal of the inductor such that, in a given half-cycle of the AC voltage, the inverter circuit uses a switching sequence wherein the first DC bus, the second DC bus and the neutral node are successively coupled to the first terminal of the inductor.

Description:
BACKGROUND 
       [0001]    The inventive subject matter relates to power conversion circuits and methods and, more particularly, to inverter apparatus and methods. 
         [0002]    UPS systems are commonly used in installations such as data centers, medical centers and industrial facilities. UPS systems may be used in such installations to provide backup power to maintain operation in event of failure of the primary utility supply. These UPS systems common have an “on-line” configuration including a rectifier and inverter coupled by a DC link that is also coupled to an auxiliary power source, such as a battery, fuel cell or other energy storage device. 
         [0003]    UPS systems, motor drives and other power conversion devices commonly use an inverter that generates an AC output from a DC power source, such as a rectifier and/or battery. A “two level” bridge inverter may be use to selectively connected these DC buses to the output of the inverter to generate an AC voltage waveform. Multilevel inverters may provide for additional voltages between the DC bus voltages. Various multilevel inverter circuits are described, for example, in U.S. Pat. No, 5,361,196 to Tamamachi et al., U.S. Pat. No. 6,795,323 to Tanaka et al., U.S. Pat. No. 6,838,925 to Nielsen, U.S. Pat. No. 7,145,268 to Edwards et al. and U.S. Pat. No. 7,573,732 to Teichmann et al. 
         [0004]    A UPS may use a split DC link arrangement including two DC voltage busses having positive and negative voltages with respect to a neutral. A potential issue with split link inverter arrangements is that unbalanced loads, such as loads having input half-wave rectification, may cause voltage imbalances of the DC link bus voltages with respect to the load neutral. Imbalances in DC busses feeding an inverter may be addressed by a balancer circuit as described, for example, in U.S. Pat. No. 3,775,663 to Turnbull and U.S. Pat. No. 6,314,007 to Johnson, Jr. et al. 
       SUMMARY 
       [0005]    Some embodiments of the inventive subject matter provide a power conversion apparatus including first and second DC busses, a neutral node and an inductor configured to be coupled to a load. The apparatus further includes an inverter circuit coupled to the first and second DC busses, to the neutral node and to the inductor and configured to selectively couple the first and second DC busses and the neutral node to a first terminal of the inductor to generate an AC voltage at a second terminal of the inductor such that, in a given half-cycle of the AC voltage, the inverter circuit uses a switching sequence wherein the first DC bus, the second DC bus and the neutral node are successively coupled to the first terminal of the inductor. In some embodiments, the inverter circuit may be configured to couple the first DC bus to the first terminal of the inductor to increase a magnitude of the AC voltage and then to couple the second DC bus to the first terminal of the inductor to discharge the inductor. Discharge of the inductor may counteract an imbalance of the first and second DC busses with respect to the neutral node. For example, discharge of the inductor may cause a charge rebalance between first and second capacitors coupled between respective ones of the first and second DC busses and the neutral node. In some embodiments, the inverter circuit may be configured to decouple the second DC bus from the first terminal of the inductor and then couple the neutral node to the first terminal of the inductor responsive to a current in the inductor. 
         [0006]    In some embodiments, a power conversion apparatus includes first and second DC busses and an inverter circuit coupled to the first and second DC busses and to a first terminal of the inductor and configured to selectively transition between different inverter level modes of operation to compensate for imbalance of the first and second DC busses with respect to a neutral node. The apparatus may further include an inductor configured to couple an output of the inverter to a load, and the inverter circuit may be configured to transition between inverter level modes to route current from the inductor to compensate for the imbalance. The inverter circuit may be configured to selectively route current from the inductor to first and second capacitances coupled between a neutral node and respective ones of the first and second DC busses. The inverter circuit may be configured to transition between inverter level modes responsive to a current in the inductor. 
         [0007]    Related power conversion methods are also described. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0008]      FIG. 1  is a schematic diagram illustrating a power conversion apparatus according to some embodiments of the inventive subject matter. 
           [0009]      FIG. 2  is a graph illustrating operations of the power conversion apparatus of  FIG. 1 . 
           [0010]      FIG. 3  is a schematic diagram illustrating operations of the power conversion apparatus of  FIG. 1 . 
           [0011]      FIG. 4  is a schematic diagram illustrating an uninterruptible power supply (UPS) according to further embodiments of the inventive subject matter. 
       
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
       [0012]    Specific exemplary embodiments of the inventive subject matter now will be described with reference to the accompanying drawings. This inventive subject matter may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive subject matter to those skilled in the art. In the drawings, like numbers refer to like elements. It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. 
         [0013]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive subject matter. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms “includes,” “comprises,” “including” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
         [0014]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0015]      FIG. 1  illustrates a power conversion apparatus  100  according to some embodiments of the inventive subject matter. The apparatus  100  includes first and second DC busses  115   a ,  115   b,  which have respective first and second DC voltages V DC+ , V DC−  associated therewith. The DC busses  115   a,    115   b  may be powered by, for example, a rectifier circuit and/or a DC energy storage and/or generation device, such as a battery, fuel cell or photovoltaic device. A variable mode inverter circuit  110  is coupled to the first and second DC busses  115   a,    115   b  and to an output filter  120  that includes an inductor L out  and a capacitor C out . The inverter circuit  110  produces an AC output voltage v out  at an output node  122  of the filter  120  from the DC voltages V DC+ , V DC− . 
         [0016]    The inverter circuit  110  includes a first serially-connected pair of transistors Q 1 , Q 2  that are coupled between the first DC bus  115   a  and the inductor L out  and a second serially-connected pair of transistors Q 3 , Q 4  that are coupled between the second DC bus  115   b  and the inductor L out . Respective first and second diodes D 1 , D 2  couple respective nodes between the transistors of the respective pairs to a neutral node N. Respective capacitors C 1 , C 2  are coupled between respective ones of the first and second DC busses  115   a,    115   b  and the neutral node N. 
         [0017]    It will be appreciated that the arrangement of the transistors Q 1 , Q 2 , Q 3 , Q 4  illustrated in  FIG. 1  is one conventionally used to implement a three-level inverter in which three voltages, i.e., the DC bus voltages V DC+ , V DC−  and the voltage at the neutral node N, are applied to the output filter inductor L out . According to some embodiments of the inventive subject matter, however, an inverter control circuit  112  controls the transistors Q 1 , Q 2 , Q 3 , Q 4  to support different inverter level modes of operation such that the inverter circuit  110  may compensate for imbalance of the first and second DC busses  115   a,    115   b  with respect to the neutral node N. According to some embodiments, the inverter control circuit  112  may apply control signals to the transistors Q 1 , Q 2 , Q 3 , Q 4  such that, within a given half cycle of the AC output voltage v out , the inverter circuit  110  selectively transitions between a two-level inverter mode and a three-level inverter mode. 
         [0018]    Referring to  FIGS. 2 and 3  in conjunction with  FIG. 1 , the inverter control circuit  112  may implement an output voltage control loop that conforms the output voltage v out  to a desired AC voltage waveform. In a positive half cycle  210  of the output voltage v out , the control circuit  112  may turn the first and second transistors Q 1 , Q 2  “on” during a first period  211  such that the first DC bus  115   a  is coupled to the output inductor L out  and a current i L  flows through the inductor L out  towards the output node  122 , causing the magnitude of the output voltage v out  to increase toward the value of the desired AC voltage waveform. This current flow A is illustrated in  FIG. 3 . 
         [0019]    When the output voltage control loop determines that the output voltage v out  has reached a desired level, the inverter control circuit  112  turns off the first and second transistors Q 1 , Q 2 . At this point, the output inductor L out  has accumulated a certain amount of stored energy from the current flowing therethrough. The inverter control circuit  112  uses this energy to equalize the DC busses  115   a,    115   b  by momentarily transitioning to a two level inverter mode by closing both the third and fourth transistors Q 3 , Q 4  during an interval  212  such that energy is transferred between the first and second capacitors C 1 , C 2  by a current flow B illustrated in  FIG. 3 . After most or all of the energy stored in the inductor L out  is delivered, the inverter control circuit  112  turns of the fourth transistor Q 4  and turns on the second transistor Q 2  for an interval  213  such that the inverter circuit  110  transitions to a three-level inverter mode. Referring to  FIG. 1 , this transition may be triggered by the inverter control circuit  112  responsive to the current i L , through the output inductor L out , e.g., when the inductor current i L  approaches zero, the inverter control circuit  112  may turn off the fourth transistor Q 4  and turn on the second transistor Q 2 . This feedback may be provided, for example, using a current sensor or other device that generates a signal representative of the inductor current i L . 
         [0020]    A similar sequence of operations occurs for a negative half-cycle  220  of the output voltage v out . In the negative half cycle  220  of the output voltage v out , the control circuit  112  may turn the third and fourth transistors Q 3 , Q 4  “on” during a first period  221  such that the second DC bus  115   b  is coupled to the output inductor L out  and a current i L  flows through the inductor L out  towards the output node  122 , causing the magnitude of the output voltage v out  to increase toward the value of the desired AC voltage waveform. 
         [0021]    When the output voltage control loop determines that the output voltage v out  has reached a desired level, the inverter control circuit  112  turns off the third and fourth transistors Q 3 , Q 4 . At this point, the output inductor L out  has accumulated a certain amount of stored energy from the current flowing therethrough. The inverter control circuit  112  uses this energy to equalize the DC busses  115   a,    115   b  by momentarily transitioning to a two level inverter mode by turning on the first and second transistors Q 1 , Q 2  during an interval  222  such that energy is transferred between the first and second capacitors C 1 , C 2 . After most or all of the energy stored in the inductor L out  is delivered, the inverter control circuit  112  turns of the first transistor Q 1  and turns on the third transistor Q 3  for an interval  223  such that the inverter circuit  110  transitions to a three-level inverter mode. 
         [0022]    It will be appreciated that, although the above discussion relates to inverter configuration that support two- and three-level inverter mode operation, the inventive subject matter is applicable to inverter configurations that support inverter levels greater than three. It will also be understood that the inventive subject matter may be embodied in a wide variety of power conversion apparatus, including, but not limited to, motor drives, power supplies and auto and marine inverter systems. 
         [0023]    Embodiments of the inventive subject matter may be used to particular advantage in uninterruptible power supply (UPS) applications.  FIG. 4  illustrates a UPS  400  including a three phase variable mode inverter circuit  420  along the lines discussed above. The inverter circuit  420  includes three legs  422   a,    422   b,    422   b  controlled by a control circuit (not illustrated for purposes of clarity). Respective ones of the legs are coupled to respective output filter circuits  440   a,    440   b,    440   c,  each of which include an output inductor L out  and capacitor C out . The respective filter circuits  440   a,    440   b,    440   c  produce respective output phase voltages V outa , v outb , v outc . The inverter circuit  420  is coupled to first and second DC busses  415   a,    415   b  and to a neutral node N. Respective capacitors C 1 , C 2  are coupled between respective ones of the DC voltage busses  415   a,    415   b  and the neutral node N. A rectifier circuit  410  generates DC voltages V DC+  , V DC−  on the DC voltage busses  415   a ,  415   b  from a three-phase AC source having phase voltages v ina , v inb , v inc . An auxiliary DC power source  430  is coupled to the DC busses  415   a,    415   b  and provides power thereto. The auxiliary source  430  may include, for example, a battery coupled to the DC busses  415   a,    415   b  by a battery converter/charger circuit. 
         [0024]    Operating the inverter circuit  420  in a variable level mode along the lines described with reference to  FIGS. 1-3  may eliminate a need to provide a separate balancer circuit to maintain a balance of the DC bus voltages V DC+ , V DC− . Instead, energy stored in the output filter inductors L out  may be used to balance the DC bus voltages V DC+ , V DC−  along the lines discussed above. This may be particularly useful when the UPS  400  is used to drive unbalanced loads. 
         [0025]    In the drawings and specification, there have been disclosed exemplary embodiments of the inventive subject matter. Although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the inventive subject matter being defined by the following claims.