Abstract:
The embodiments of the present invention introduced and taught herein are directed to a whole-chip ESD protection arrangement that is independent of relative supply rail voltage and supply sequencing, thereby enabling ESD conduction path during ESD event and isolating the ESD conduction path during the power up and power down modes of the chip. An embodiment of the present invention uses the bi-directional R-C clamp with transistorized arrangements between powered rails and avoids the drawback of using uni-directional Clamps or diode array for clamping that consumes large silicon area, requires power sequencing and is prone to noise coupling between power rails.

Description:
FIELD OF THE INVENTION 
   This invention relates to Electrostatic Discharge (“ESD”) protection arrangements for semiconductor integrated circuits. In particular, the invention relates to systems and methods for whole-chip ESD protection that is independent of relative supply rail voltages and supply sequencing. 
   BACKGROUND OF THE INVENTION 
   Electrostatic Discharge (“ESD”) is a serious problem for CMOS semiconductor devices since it has the potential to destroy an entire device. Therefore, protection from ESD discharge has become an important issue in CMOS ICs. The advanced processes of sub-micron CMOS technologies greatly degrade the ESD protection strength of CMOS ICs. Circuit designers have concentrated their efforts on developing adequate protection mechanisms. 
   In general, an IC should be protected for ESD discharge between any pair of pins. A protection circuit should behave as an ideal switch in parallel with the nodes to be protected; such that when an ESD event occurs, it behaves as a shortcircuit while during normal operation of the IC, it remains in a high impedance state. 
   An existing option is to use an RC-controlled ESD clamp that would sink the ESD current by switching ‘on’ during the ESD event while remaining ‘off’ during normal operation.  FIG. 1  illustrates an R-C controlled ESD clamp circuit according to the PRIOR ART. The ESD conduction path is provided from Rail 11  to Rail 12  through NMOS transistor N 12 . The gate of N 12  is controlled by an inverter formed by PMOS transistor P 11  and NMOS transistor N 11 . The inverter itself is driven by ESD-transient detection circuit formed by resistor R 11  and capacitor C 11 . 
   Initially, the nodes VG and VX are floating because the IC is in the floating condition without power supplies. An ESD event on Rail 11  with respect to Rail 12  will very slowly charge capacitor C 11  and slowly raise the voltage level of node VG. The RC time constant of the RC-circuit R 11 -C 11  is kept higher than the rise time of ESD voltage pulse at Rail 11 . Thus the voltage level of VG is increased much slower than the voltage level on Rail 11 . Due to the delay of voltage increase on node VG, PMOS P 11  is turned-on by the ESD voltage and conducts ESD voltage into the node VX to turn ‘on’ the ESD clamping NMOS transistor N 12 . The turned-on N 12  provides a low impedance path between rails Rail 11  and Rail 12  that discharges the ESD current and clamps the ESD voltage across them. 
   The turn-on time of ESD-clamp N 12  is kept at least equal to half the energy discharging time of the ESD event. The turn-on time of N 12  can be adjusted by the RC time constant of the RC-circuit and the relative sizing of P 11  and N 11 . Generally P 11  is kept strong and N 11  is kept relatively much weaker to ensure a faster response and longer duration turn-on of N 12 . The symbol used for the clamp is shown in  FIG. 1 . 
   IEEE paper “Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Sub micron CMOS VLSI” by Ming-Dou Ker provides a detailed description of such a circuit. This paper also describes a whole chip ESD protection design using such a clamp, in which the clamp is placed between VDD and VSS rails with Rail 11  as VDD and Rail 12  as VSS. 
   One limitation to this clamp is that it cannot be used to provide ESD conduction path from rails that are normally at lower voltage to rails that are at higher voltage. This means that in normal operation, Rail 11  should always be at voltage higher than or equal to that at Rail 12 . 
   This is because if in normal operation we have Rail 11  at lower voltage and Rail 12  at higher voltage, node VX is pulled-down to the lower voltage through PMOS transistor P 11 . Thus voltage at node VX will always be one Vtp (PMOS transistor&#39;s threshold voltage) higher than the lower voltage, keeping N 12  in its sub-threshold region. N 12  is large enough to conduct significant amount of static current, even though operating in its sub-threshold region. 
   U.S. Pat. Nos. 5,946,177, 5,610,791, 6,104,588, 5,953,190 show existing methods of providing ESD conduction paths between VDD and VSS Rails: 
     FIG. 2(   a ) shows how an ESD discharge on the VDD rail with respect to VSS is conducted through RC-clamp C 2   a , while an ESD discharge on VSS rail with respect to VDD is conducted through diode D 2   a . This scheme is applicable to single supply ICs. As more circuits and functions are integrated into a single chip, a chip often has more than one power supply with different voltage levels. For example, chips have their internal core circuitry operating at one supply voltage level and interfacing I/O circuitry operating at different supply voltage. For such mixed-voltage ICs it becomes important to provide ESD conduction paths between separate supplies to have a robust whole chip ESD protection design. 
     FIG. 2(   b ) shows the conventional method to provide ESD conduction path between two separate supply rails. Here I/O supply voltage VDDO is assumed to be at higher supply voltage than core supply VDD. ESD conduction path from VDD rail to VDDO rail is provided through diode D 21   b  and the conduction path from VDDO to VDD through diode chain D 22   b , D 23   b , D 24   b . This scheme requires the IC to be powered-up and powered-down sequentially because of the presence of diode D 21   b  (refer application note “Power-Up Behavior of Pro-ASIC 500K Devices” by ACTEL). Also, diodes in series will degrade the ESD performance and will require larger area for low resistance ESD conduction path. Further, if the voltage difference between VDDO and VDD is large, more than one diode will be required in series. The diode chain will also cause problems during power-up and power-down of the IC. For large differences between VDDO and VDD supplies, an RC-clamp is sometimes used instead of a diode chain, as shown in  FIG. 2(   c ). But this too does not overcome the power sequence requirement. 
   In some ICs, it is required to have separate isolated power supply and ground rails for different sections of the IC, to avoid noise coupling between ‘noisy’ and ‘quiet’ rails. For example power/ground rails of the analog section of an IC are kept isolated from power/ground rails of the digital section to prevent the noisy digital section from affecting the performance of the quiet analog section. Here too it becomes necessary to provide ESD conduction paths between the normally isolated supplies rails. 
     FIG. 3(   a ) shows another method to provide an ESD conduction path between two isolated power rails. Here the ESD conduction path between quiet analog section supply voltage VDDQ and noisy digital section supply VDD is provided through diodes D 31   a  and D 32   a . However these diodes do not provide perfect isolation during normal operations. Any noise greater than the voltage threshold of the diodes will overcome the isolation barrier. Further, this scheme requires both supplies VDDQ and VDD to be powered-up and powered-down simultaneously. 
   To give a better isolation, a chain of diodes is used instead of a single diode, as shown in  FIG. 3(   b ). However this degrades the ESD performance and requires a larger area for providing a low resistance ESD conduction path. This scheme also requires both supplies VDDQ and VDD to be powered-up and powered-down simultaneously. 
   A perfect isolation is provided in normal operation by using RC-clamps for ESD conduction, as shown in  FIG. 3(   c ). One such similar scheme is described in U.S. Patent Application No. 2002/0085328 A1. However an RC-clamp uses a large area and therefore using two separate RC-clamps will require excessively large area. 
   The same problem occurs when this scheme is used for isolated ground rails, as shown in  FIGS. 3(   d ),  3 ( e ),  3 ( f ). 
   SUMMARY OF THE INVENTION 
   To address the above-discussed deficiencies of the PRIOR ART, an object of the present invention is to obviate the shortcomings of the PRIOR ART and provide an arrangement that provides an ESD protection that is independent of relative power supply rail voltages. 
   Another object of the present invention is to provide a bi-directional ESD clamp that consumes minimum area. 
   Yet another object of the invention is to provide an ESD protection path that is free from power sequencing. 
   To achieve the said objectives the present invention provides a system for whole-chip ESD protection that is independent of relative supply rail voltages and supply sequencing comprising:
         a pair of head-to-head diodes connected across the pair of supply rails with their common cathodes connected to the N-well bulk of the p type devices of the ESD protection arrangement,   a first series RC network connected across the supply rails,   a first pair of complementary PMOS and NMOS transistors connected in series across the supply terminals and having their drain terminals joined together and their control terminals connected together to the mid point of said first series RC network,   a second series RC network connected in anti-parallel across said first series RC network,   a second pair of complementary NMOS and PMOS transistors connected in anti-parallel across said first pair of complementary PMOS and NMOS transistors and having their common control terminals connected to the midpoint of said second series RC network while their common drain terminals are joined to the common drain terminals of said first pair of complementary transistors,   a pair of PMOS transistors connected in series across the supply rail terminals and having their drain terminals connected together,   a first control transistor connected across the capacitor of said first RC network and having its control terminal connected to the drain terminals of said series connected PMOS transistors,   a second control transistor connected across the capacitor of said second RC network and having its control terminal connected to the drain terminals of said series connected PMOS transistors, and   a clamped transistor connected across the supply terminal having its control terminal connected to the common output terminal of said first and second pair of complementary terminals,   the above arrangement being replicated for each pair of supply rails used in the device.       

   The said pair of rails are powered by similar or different voltages. 
   The instant invention further provides a method for whole-chip ESD protection that is independent of relative supply rail voltages and supply sequencing comprising the steps of:
         connecting a pair of head-to-head diodes across the pair of supply rails with their common cathodes connected to the N-well bulk of the p type devices of the ESD protection arrangement,   connecting a first series RC network across the supply rails,   joining a first pair of complementary PMOS and NMOS transistors in series across the supply terminals with their drain terminals joined together and their control terminals connected together to the mid point of said first series RC network,   attaching a second series RC network in anti-parallel across said first series RC network,   connecting a second pair of complementary NMOS and PMOS transistors in anti-parallel across said first pair of complementary PMOS and NMOS transistors with their common control terminals connected to the midpoint of said second series RC network while their common drain terminals are joined to the common drain terminals of said first pair of complementary transistors,   connecting a pair of PMOS transistors in series across the supply rail terminals and having their drain terminals joined together,   attaching a first control transistor across the capacitor of said first RC network with its control terminal connected to the drain terminals of said series connected PMOS transistors,   connecting a second control transistor across the capacitor of said second RC network with its control terminal connected to the drain terminals of said series connected PMOS transistors,   connecting a clamped transistor across the supply terminal with its control terminal connected to the common output terminal of said first and second pair of complementary terminals, and   replicating the above arrangement for each pair of supply rails used in the device.       

   Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; and the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will now be described with reference to the accompanying drawings, in which like reference numerals represent like parts, and, in which: 
       FIG. 1  shows the circuit diagram of the PRIOR ART; 
       FIGS. 2 and 3  show the PRIOR ART circuits using diode arrays to provide ESD conduction path; 
       FIG. 4   a  shows the circuit diagram of the present invention that is a used for whole chip ESD protection arrangement that is independent of relative supply rail voltage and supply sequencing; 
       FIG. 4   b  shows a section of the circuit diagram of  FIG. 4   a  that is a reference circuit to be used for the analysis of the present invention; 
       FIGS. 5 and 6  show waveforms for ESD simulations between the two rails; and 
       FIG. 7  shows a whole chip ESD protection scheme using proposed ESD Clamp of  FIG. 4   a.    
   

   DETAILED DESCRIPTION 
     FIGS. 1 ,  2  and  3  have already been explained in the context of the PRIOR ART in the Background to the Invention.  FIGS. 4   a  through  7 , discussed below, and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged systems for whole-chip ESD protection. 
     FIG. 4   a  shows the schematic diagram of a bi-directional RC-clamp  400  according to the present invention. The complete circuitry is placed across Rail 41  and Rail 42 , between which the ESD conduction path is required. Starting from the right-hand side, the circuitry includes two head-to-head connected diodes D 41  and D 42  with their cathodes connected together at node Pbulk. All the PMOS transistors in the circuitry have their N-wells biased with Pbulk. ESD-clamping NMOS transistor N path  is connected between Rail 41  and Rail 42 , with its gate connected to node VX. The Gate of N path  i.e., net VX is driven by two RC-filter circuits  401  and  402 . 
   In RC-filter circuit  401 , a capacitor C 41  is connected to Rail 41  with its other end connected to a resistor R 41 , which in turn is connected to Rail 42 . The common node VG 41  of C 41  and R 41  is connected to the gate inputs of transistors N 41  and P 43 . N 41  and P 43  are placed in series between the rails with their common node connected at node VX. A PMOS transistor P 41  is placed in parallel with capacitor C 41  with its gate controlled by node VZ. 
   It can be seen from  FIG. 4   a  that RC-filter circuit  402  is identical to  401 , except that its connectivity to Rail 41  and Rail 42  is swapped. 
   Node VZ controls the gates of P 41  and P 42  of RC-filter circuits  401  and  402  respectively. Node VZ forms the common node of P 45  and P 46 , connected in series between Rail 41  and Rail 42 . The gates of PMOS transistors P 45  and P 46  are connected to nodes VG 41  and VG 42  respectively. 
   To understand the working of circuitry shown in  FIG. 4   a , we first analyze the circuitry shown in  FIG. 4   b , which is a subset of the circuitry in  FIG. 4   a . Here diodes D 41 , D 42  and PMOS transistors P 41 , P 42 , P 45 , P 46  are removed. 
   Referring to  FIG. 4   b , transistor N path # and RC-filter circuit  402 # forms a simple unidirectional RC-controlled ESD clamp as shown in PRIOR ART  FIG. 1 . For an ESD event on Rail 41 # with respect to Rail 42 #,  402 # will pull the node VX# to a high voltage, causing N path # to start conducting. 
   To make the circuitry bi-directional, i.e. to provide conduction path for ESD current on Rail 42 # with respect to Rail 41 #, an identical RC-filter circuit  401 # is placed in parallel with  402 #, with swapped connectivity to Rail 41 # and Rail 42 #. For ESD event on Rail 42 # with respect to Rail 41 #,  401 # will pull the net VX# to a high voltage, causing N path # to start conducting. 
   However there are two major problems with this circuit: 1) In the case of an ESD event on Rail 41 # with respect to Rail 42 #, P 44 # turns-on, pulling up node VX# to the high ESD voltage. Since the bulk of P 43 # connected to lower Rail 42 # voltage, its intrinsic bulk diode will get forward biased. This forward biased bulk diode of P 43 # will pull down the voltage at net VX#. Lowering of voltage at net VX# will lower the conduction capability of ESD-clamping transistor N path #, degrading its ESD performance. 
   A similar situation will arise when we have an ESD event on Rail 42 #. In this case the intrinsic bulk diode of P 44 # will become forward biased. 
   2) Connecting two parallel RC-filter circuits  402 # and  401 # in this way will cause them to interfere with each other&#39;s performance. An ESD event on Rail 41 # will couple high voltage on node VG 41 # through capacitor C 41 #, causing P 43 # to turn ‘off’. On the other hand a low voltage will exist at node VG 42 # because of its slower rise, causing P 44 # to conduct a high voltage into node VX# to turn ‘on’ the ESD clamping transistor N path #. However, as capacitor C 42 # starts charging and capacitor C 41 # starts discharging, the conduction capability of P 44 # decreases while that of P 43 # increases. This results in a rapid decrease of voltage at node VX# thus reducing the turn-on time of ESD-clamping N path #. The RC time constant can be increased to increase the turn-on time of ESD-clamping NMOS N path #. However for large RC time constants, very large values of R and C are required, which are difficult to implement practically. 
   A similar situation will exist for an ESD event on Rail 42 #. In this case P 44 # will affect the performance of P 43 #. It is to be noted that size of devices in  402 # are exactly equal to the size of devices in  401 # to obtain similar ESD performance of the clamp in both the directions. 
   Thus, due to the problems discussed above, modifications in the circuitry of  FIG. 4   b  are required such that they do not interfere in the normal operation of the IC. The required modifications are implemented in bi-directional RC-clamp  400  shown in  FIG. 4   a . (Structural description of circuitry shown in  FIG. 4   a  is already explained earlier.) 
   Referring to  FIG. 4   a , diodes D 41  and D 42  are used to prevent intrinsic bulk diodes of P 44  and P 43  from getting forward biased. The Nwells of all the PMOS transistors in the circuitry are biased by node Pbulk. Diodes D 41  and D 42  ensure that node Pbulk always remains at voltage higher of Rail 41  and Rail 42 . In this way Nwells of P 44 , P 43  and other PMOS transistors in the circuitry are always connected to the highest existing voltage in the circuitry and their intrinsic bulk diodes never get forward biased. 
   To resolve the second problem, two PMOS transistors P 42  and P 41  are connected in parallel with capacitors C 42  and C 41  respectively. The Gates of P 42  and P 41  are controlled by P 45  and P 46 . To understand the operation of the circuitry formed by P 41 , P 42 , P 45  and P 46 , we consider the case when there is an ESD potential on Rail 41  with respect to Rail 42 . 
   The ESD potential on Rail 41  will couple a high voltage on node VG 41  through capacitor C 41 , causing P 43  and P 45  to turn ‘off’. On the other hand, a low voltage will exist on node VG 42  because of its slower rise, making P 44  conduct high voltage into node VX and P 46  to conduct low voltage into node VZ. The high voltage on node VX will turn ‘on’ the ESD clamping NMOS N path  and the low voltage on node VZ will turn ‘on’ P 41 . (It is to be noted that voltage at node VZ will be one Vtp higher than the voltage at node VG 42 , where Vtp is threshold voltage of PMOS transistors. But this voltage is low enough to turn-on P 41 ) 
   The turned-on P 41  will pull-up the node voltage at VG 41  and as the resistor value of R 41  is very high, voltage at node VG 41  will become nearly equal to the ESD potential generated at Rail 11 . 
   As capacitor C 42  starts charging, the voltage at node VG 42  will rise, decreasing the conduction capability of P 44  and turning-off P 46 . As P 46  turns-off and as P 45  is already off, node VZ will become floating and the existing low voltage at node VZ will remain for some period of time. For this period of time P 41  will remain ‘on’, keeping node VG 41  at the high ESD voltage. The high voltage on node VG 41  will keep P 43  perfectly ‘off’ and therefore the voltage at node VX will not decrease rapidly. As a result, the turn-on time of ESD-clamping N path  will become sufficiently long. It is to be noted that the time period for which the low voltage exists at node VZ is long enough to allow sufficient time for ESD discharge. As the circuitry viewed from Rail 42  side is exactly symmetrical to that viewed from Rail 41  side, the operation of clamp  400  for ESD potential on Rail 42  with respect to Rail 41  will be similar to that for ESD potential on Rail 41  with respect to Rail 42 . In this case P 44  will remain perfectly ‘off’ and P 43  will conduct high voltage into the node VX, turning ‘on’ ESD clamp NMOS N path . 
   The symbol for the bi-directional clamp is shown along side in  FIG. 4   a.    
     FIG. 5(   a ) shows voltage and current waveforms for 2 kV HBM ESD-potential simulations on Rail 41  with respect to Rail 42 . 
   In the voltage waveforms, it can be seen that voltage on node VZ is low enough to keep P 41  ‘on’ and voltage on node VG 41  remains close to ESD-potential voltage developed on Rail 41 . 
   In current waveform, I ESD  is the Source/Drain current through ESD clamping NMOS transistor N path . 
     FIG. 5(   b ) shows voltage and current waveforms for 2 kV HBM ESD-event simulations on Rail 42  with respect to Rail 41 . In this case, it can be seen that the performance of this clamp is similar to that in the earlier case. The voltage on node VZ is low enough to keep P 42  ‘on’ and the voltage on node VG 42  remains close to ESD-potential voltage developed on Rail 42 . 
   In the current waveform, I ESD  is the Source/Drain current through ESD clamping N path . 
   The ESD clamp  400  in  FIG. 4   a  can be used to discharge ESD energy between any pair of supply rails. For example between VDD-VDDO, VDDO-VDDQ, VDDQ-VDD, VDD-VSS, VDDQ-VSSQ, etc. 
   To understand its working in normal power-up condition of IC, consider the following two examples. The first condition arises when it is placed across the VDD-VSS rail and the second when it is placed across the VDD-VDDO rails. 
   Referring to  FIG. 4   a , in the first case Rail 41  is connected to core supply voltage VDD and Rail 42  is connected to ground supply voltage VSS. The VDD power-up voltage waveform has a rise time of the order of milliseconds (ms). With such a slow rise time, the voltage level on the node VG 42  in the RC-filter circuit  402  will follow the VDD voltage in time because the RC-time constant of RC circuit R 42 -C 42  is much lower than the power-up rise time. Because the node voltage on VG 42  is simultaneously increased to VDD voltage level in the VDD power-up condition, P 44  and P 46  remain ‘off’ and N 42  is turned ‘on’ to keep node VX at a ground voltage level VSS. 
   In RC-filter circuit  401 , node VG 41  will remain at ground level, keeping N 41  ‘off’ and P 43  and P 45  ‘on’. This will keep node VX at a ground voltage level and P 45  will pull node VZ to high VDD voltage. This high voltage on node VZ will ensure that P 42  and P 41  remain ‘off’. 
   As node VX remains at ground voltage level, the ESD clamping NMOS transistor N path  is guaranteed to remain ‘off’ while the IC is under the VDD power-on condition or in normal operating condition. 
   Because of the bi-directional and symmetrical nature of the circuitry, the supply connections can be interchanged, i.e. Rail 41  can be connected to VSS and Rail 42  can be connected to VDD. Therefore there is no limitation of connecting Rail 41  always at higher voltage and Rail 42  always at lower voltage in normal operation, as we had in conventional clamps shown in  FIG. 1 . 
   Due to the difference in the rise times between the ESD voltage and the VDD power-up voltage, the VDD-to-VSS ESD clamp circuit provides a low-impedance path between the VDD and VSS power lines in ESD stress conditions, but becomes an open circuit between the power lines in the VDD power-up conditions. 
     FIG. 6  shows the curve for maximum voltage appearing on node VX for varying rise times of 0-3.3V voltage ramp. A voltage ramp is applied on Rail 41  with respect to Rail 42 . It can be seen from the graph that for ramp rise times of 100 ns or less, the voltage on node VX is large enough to turn-on ESD clamping NMOS transistor N path  and for ramp rise time of 1 us or more, the voltage on node VX is small enough to keep ESD clamping NMOS transistor N path  ‘off’. 
   In the second case, Rail 41  is connected to the higher 3.3V I/O voltage VDDO and Rail 42  is connected to the lower 1.8V core voltage VDD. Connecting bi-directional clamp  400  between separate power supply rails like VDD and VDDO, does not require any power-up sequence to be followed. 
   When 3.3 V VDDO supply at Rail 41  is powered-up first, node VG 42  will follow VDDO supply rise, turning-on N 42  and pulling down node VX to the lower VDD voltage, which is still not powered-up. Now, when the 1.8V VDD supply at Rail 42  is powered-up, the VDD voltage will be conducted to node VX through N 42 . Even when VX is pulled to 1.8V, ESD clamping NMOS transistor N path  remains ‘off’, as its source is connected to the same voltage. 
   When the 1.8 V VDD supply is powered-up first, the node voltage at VG 41  will follow the VDD supply in time, turning-on N 41  and pulling down node VX to the lower VDDO voltage, which is still not powered-up. Now, when the 3.3V VDDO supply is powered-up, it will be conducted to node VX through N 41 , until it reaches 1.8V. When the VDDO voltage rises above 1.8V, N 41  will turn-off and as node VG 42  will increase simultaneously with VDDO, N 42  will turn-on. Now N 42  will conduct lower 1.8V VDD supply to node VX keeping N path  ‘off’. 
   So, it is seen that for any power-up sequence, node VX always remains at the lower of two power supplies. So for any sequence followed to power-up VDD and VDDO, the ESD clamping N path  is guaranteed to remain ‘off’. 
   Here again, because of the bi-directional and symmetrical nature of the circuitry, the supply connections can be interchanged. 
   It will apparent to those skilled in this field that in the conventional RC-controlled clamps as shown in  FIG. 1 , 70% to 80% of the total clamp layout area is taken by ESD-clamping NMOS transistor N 12  and only 20% to 30% by RC-filter circuitry. As, in bi-directional RC-controlled clamp according to present invention shown in  FIG. 4   a , an extra RC-filter circuit in added, this clamp will require only 20% to 30% more area compared to conventional clamp. The four extra PMOS transistors added in bi-directional RC-controlled clamp are of small sizes and therefore take negligible area compared to total area of the clamp. 
   But when the area of the proposed bi-directional clamp is compared with the combined area taken by conventional ESD protection devices placed between two rails, it is much smaller. For example to provide ESD conduction paths between VDD and VSS rails, conventionally a diode and a unidirectional clamp are used as shown in  FIG. 2(   a ), which can be replaced by a single proposed bi-directional clamp. The area taken by bi-directional clamp will be less than the combined area taken by diode and a unidirectional clamp. 
     FIG. 7  shows a whole chip ESD protection scheme using proposed bi-directional RC-controlled clamps. The example here is of a mixed voltage IC, having three separate supply pairs including, I/O supply pair VDDO-VSSO for I/O circuitry, noisy supply pair VDD-VSS for the digital section and quiet supply pair VDDQ-VSSQ for the analog section. 
   Bi-directional clamps are placed between every separate supply pair, between every pair of power rails and between every pair of ground rails. Each I/O pin is connected to the corresponding ground and power rails through diode, which remain reverse biased during normal operation. 
   An ESD event on I/O pin 1  will be conducted to VDDO rail through diode D 1 , from VDDO rail to VSSO rail through bi-directional clamp BC 75  and finally from VSSO rail to I/O pin 4  through diode D 4 . ESD energy discharge path is shown by dotted lines in  FIG. 7 . 
   The scheme shown in  FIG. 7  is very general and simple modifications can be made to it if desired. For example if perfect isolation between ground rails is not required, then bi-directional clamps BC 77 , BC 78  and BC 79  can be replaced by diodes. It is intended that the present invention encompass such changes and modifications as fall within the scope of the appended claims.