Abstract:
The present invention provides a bandgap reference circuit. The bandgap reference circuit includes a first bipolar junction transistor, a first resistor, for generating a proportional to absolute temperature current, a second resistor, for generating a complementary to absolute temperature current, a first operational amplifier, coupled with the first bipolar junction transistor and the first resistor, a second operational amplifier, coupled with the first bipolar junction transistor and the second resistor, and a zero temperature correlated current generator, for summing the proportional to absolute temperature current and the complementary to absolute temperature current, to generate a zero temperature correlated current.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a bandgap reference circuit and bandgap reference current source, and more particularly, to a bandgap reference circuit and bandgap reference current source with reduced layout area. 
     2. Description of the Prior Art 
     A stable reference voltage source or current source immune to temperature variation, e.g. a bandgap reference circuit, is usually applied in analog circuits to provide a reference voltage or reference current, for maintaining accurate operations of a power source or other circuits. In short, a bandgap reference current source sums a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current at a proper ratio, such that a PTAT component and a CTAT component are cancelled, generating a zero temperature correlated (zero-TC) current. 
     In detail, please refer to  FIG. 1 , which is a schematic diagram of a bandgap reference current source  10  in the prior art. The bandgap reference current source  10  includes a start-up circuit  100  and a bandgap reference circuit  102 . The start-up circuit  100  activates operations of the bandgap reference circuit  102  when a system voltage VDD is greater than source-to-gate voltages of P-type metal oxide semiconductor (MOS) transistors  104 ,  106 , i.e. VDD&gt;2 VSG. As shown in  FIG. 1 , since input voltages VA, VB of positive and negative input terminals of an operational amplifier (OP)  108  are identical in the bandgap reference circuit  102 , i.e. VA=VB=VEB 1 , a PTAT current Iptat can be generated from base-to-emitter voltages VEB 1 , VEB 2  of BJTs Q 1 , Q 2  and a resistor Rptat with a resistance R as shown in Eq. 1: 
     
       
         
           
             
               
                 
                   
                     Iptat 
                     = 
                     
                       
                         
                           
                             V 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             B 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           - 
                           
                             V 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             B 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         R 
                       
                       = 
                       
                         
                           
                             V 
                             T 
                           
                           ⁢ 
                           ln 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           K 
                         
                         R 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
     where K denotes that the BJT Q 2  can be taken as K BJTs Q 1  connected in parallel. Since a threshold voltage V T  is PTAT, by referring to Eq. 1, the PTAT current Iptat carried by the resistor Rptat is also PTAT. 
     On the other hand, a CTAT current Ictat can be generated from the base-to-emitter voltage VEB 1  of the BJT Q 1  and a resistor Rctat with a resistance L*R as shown in Eq. 2: 
     
       
         
           
             
               
                 
                   
                     
                       I 
                       CTAT 
                     
                     = 
                     
                       
                         VEB 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                       
                         L 
                         * 
                         R 
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
     where the CTAT current Ictat carried by the resistor Rctat is CTAT, since the base-to-emitter voltage VEB 1  is CTAT. As a result, if the resistance L*R of the resistor Rctat is properly adjusted, a zero-TC current Iref can be generated by summing the PTAT current Iptat and the CTAT current Ictat as shown in Eq. 3: 
     
       
         
           
             
               
                 
                   
                     Iref 
                     = 
                     
                       
                         Iptat 
                         + 
                         Ictat 
                       
                       = 
                       
                         
                           
                             
                               V 
                               T 
                             
                             ⁢ 
                             ln 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             K 
                           
                           R 
                         
                         + 
                         
                           
                             V 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             B 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                           
                             L 
                             * 
                             R 
                           
                         
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       
                         ∂ 
                         Iref 
                       
                       
                         ∂ 
                         T 
                       
                     
                     = 
                     
                       
                         
                           
                             
                               ln 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               K 
                             
                             R 
                           
                           * 
                           
                             
                               ∂ 
                               
                                 V 
                                 T 
                               
                             
                             
                               ∂ 
                               T 
                             
                           
                         
                         + 
                         
                           
                             1 
                             
                               L 
                               * 
                               R 
                             
                           
                           * 
                           
                             
                               
                                 ∂ 
                                 V 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               E 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               B 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             
                               ∂ 
                               T 
                             
                           
                         
                       
                       = 
                       0 
                     
                   
                   , 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       ⇒ 
                       L 
                     
                     = 
                     
                       
                         - 
                         
                           
                             
                               
                                 ∂ 
                                 V 
                               
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               E 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               B 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                             
                               ∂ 
                               T 
                             
                           
                           
                             
                               
                                 ∂ 
                                 
                                   V 
                                   T 
                                 
                               
                               
                                 ∂ 
                                 T 
                               
                             
                             ⁢ 
                             ln 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             K 
                           
                         
                       
                       ≈ 
                       
                         - 
                         
                           
                             - 
                             1.6 
                           
                           
                             0.085 
                             ⁢ 
                             ln 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             K 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Eq 
                     . 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   ) 
                 
               
             
           
         
       
     
     where a component of the base-to-emitter voltage VEB 1  and a component of the threshold voltage V T  after partial differential operations of time are −1.6 mv/C and 0.085 mv/C, respectively. Therefore, as can be seen from Eq. 3, when L=1.6/0.085 lnK, the zero-TC current Iref is zero-TC, and the zero-TC current Iref can be mirrored for output by current mirrors M 1 , M 2 , M 3 . 
     Please refer to  FIG. 2A  and  FIG. 2B , which are schematic diagrams of the OP  108  shown in  FIG. 1  optionally including an input pair of PMOS or NMOS transistors, respectively. When the OP  108  includes an input pair of PMOS transistors, the input voltages VA, VB of the input pair of the PMOS transistors Q 3 , Q 4  are required to be less than VDD−VDS 5 −VSG 3 , and when the OP  108  includes an input pair of NMOS transistors, the input voltages VA, VB of the input pair of the NMOS transistors Q 6 , Q 7  are required to be greater than VDS 8 +VGS 7 . Therefore, the input voltages VA, VB of the OP  108  including an input pair of PMOS transistors can be lower than those of the OP  108  including an input pair of NMOS transistors, such that power consumption of the BJTs Q 1 , Q 2  shown in  FIG. 1  can be reduced. 
     However, as shown in  FIG. 1  and  FIG. 2A , if the OP  108  includes an input pair of PMOS transistors, since the output voltage Vo equals the system voltage VDD minus a source-to-gate voltage VSGM 1  of the current mirror M 1 , the input pair of the PMOS transistors will operate in linear region when the system voltage VDD rises, such that the OP  108  will not operate as expected. As a result, the OP  108  including an input pair of PMOS transistors can not be applied for a wider range of the system voltage VDD. In comparison, although the OP  108  including an input pair of NMOS transistors can be applied for a wider range of the system voltage VDD, the input voltages VA, VB can not be reduced, such that power consumption of the BJTs Q 1 , Q 2  is increased. 
     Besides, in the bandgap reference current source  10 , since the start-up circuit  100  starts operating when VDD&gt;2 VGS, the start-up circuit  100  may not operate well due to process or temperature variation. In addition, the bandgap reference circuit  102  further needs to utilize a resistor with a resistance L*R to balance the CTAT current, wasting layout area. Thus, there is a need for improvement of the prior art. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the present invention to provide a bandgap reference circuit and bandgap reference current source. 
     The present invention discloses a bandgap reference circuit with less layout area. The bandgap reference circuit includes a first bipolar junction transistor (BJT), comprising a first terminal and a second terminal coupled to a ground, a first resistor, for generating a proportional to absolute temperature (PTAT) current, a second BJT, comprising a first terminal coupled to the first resistor, and a second terminal and a third terminal coupled to a ground, a second resistor, having a resistance with a specific ratio to a resistance of the first resistor, for generating a complementary to absolute temperature (CTAT) current, a first operational amplifier (OP), comprising a first input terminal coupled to a third terminal of the first BJT, and a second input terminal coupled to the first resistor, a second OP, comprising a first input terminal coupled to the first BJT the third terminal, and a second input terminal coupled to the second resistor, and a zero temperature correlated (zero-TC) current generator, for summing the PTAT current and the CTAT current, to generate a zero-TC current. 
     The present invention further discloses a bandgap reference current source. The bandgap reference current source includes a bandgap reference circuit with less layout area, for generating a zero-TC current, and a start-up circuit, for activating the bandgap reference circuit. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a bandgap reference current source in the prior art. 
         FIG. 2A  and  FIG. 2B  are schematic diagrams of an OP shown in  FIG. 1  optionally including an input pair of PMOS or NMOS transistors, respectively. 
         FIG. 3  is a schematic diagram of a bandgap reference current source according to an embodiment of the present invention. 
         FIG. 4  is a schematic diagram of OPs shown in  FIG. 3  according to an embodiment of the present invention. 
         FIG. 5  is a schematic diagram of a bandgap reference current source according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 3 , which is a schematic diagram of a bandgap reference current source  30  according to an embodiment of the present invention. The bandgap reference current source  30  includes a start-up circuit  300  and a bandgap reference circuit  302 . Compared with the start-up circuit  100 , the start-up circuit  300  can activate operations of the bandgap reference circuit  302  when VDD&gt;VSG, and the start-up circuit  300  further includes a PMOS transistor  304  utilized for gradually being turned off to avoid DC power consumption after the bandgap reference circuit  302  steadily outputs a zero temperature correlated (zero-TC) current Iref′. In the bandgap reference circuit  302 , methods for generating a proportional to absolute temperature (PTAT) current Iptat′ and a complementary to absolute temperature (CTAT) current Ictat′ are similar to those of the bandgap reference circuit  102 , and are not narrated hereinafter. Differences between the bandgap reference circuit  302  and the bandgap reference circuit  102  are that the bandgap reference circuit  102  only utilizes the OP  108  to generate the PTAT current Iptat and the CTAT current Ictat, while the bandgap reference circuit  302  utilizes OPs  306 ,  308  to generate the PTAT current Iptat′ and the CTAT current Ictat′, respectively. As a result, the bandgap reference circuit  302  does not need to utilize an extra resistor with a resistance L*R to balance the CTAT current, which reduces layout area. 
     In detail, since input voltages VA′ and VB′ of positive and negative input terminals of the OP  306  are the same as input voltages VC′ and VB′ of positive and negative input terminals of the OP  308 , i.e. VA′=VB′=VC′=VEB 1 ′, it can be derived that the PTAT current Iptat′ is PTAT by calculations similar to those of the prior art. The CTAT current Ictat′ is generated by a voltage-current converter, i.e. the OP  308 , a current mirror M 4  and a resistor Rctat′ combined, converting a CTAT voltage VC′=VEB 1 ′ into a CTAT current Ictat′. Thus, a zero-TC current generator  310  can utilize current mirrors M 1 ′, M 2 ′, M 3 ′ and current mirrors M 4 , M 5  to mirror the PTAT current Iptat′ and the CTAT current Ictat′, respectively, so as to sum the PTAT current Iptat′ and the CTAT current Ictat′ and thus generate the zero-TC current Iref′. In comparison, the bandgap reference circuit  102  in the prior art needs the extra resistor Rctat for balancing the CTAT current Ictat, since the current mirrors M 1 , M 2  and M 3  simultaneously mirror the PTAT current Iptat and the CTAT current Ictat. As a result, the bandgap reference circuit  302  does not need to utilize an extra resistor with a resistance L*R to balance CTAT current, and thus requires less layout area. 
     Furthermore, please refer to  FIG. 4 , which is a schematic diagram of the OPs  306 ,  308  shown in  FIG. 3  according to an embodiment of the present invention. As shown in  FIG. 4 , the OPs  306 ,  308  include an input pair of PMOS transistors Q 9 , Q 10  and a folded-cascode structure. Therefore, lower input voltages VA′, VB′ can be applied for reducing power consumption of BJTs Q 1 ′ and Q 2 ′ shown in  FIG. 3 , and an output voltage Vo′ can rise normally without affecting operations of the input pair of the PMOS transistors Q 9 , Q 10  when the system voltage VDD rises, such that the OPs  306 ,  308  can be applied for a wider range of the system voltage VDD. As a result, the present invention can be applied for a wider range of the system voltage VDD with low power consumption. 
     Noticeably, the spirit of the present invention is to utilize the OPs  306 ,  308  to generate the PTAT current Iptat′ and the CTAT current Ictat′, respectively, so as to reduce layout area, wherein the OPs  306 ,  308  include an input pair of PMOS transistors and a folded-cascode structure, such that the bandgap reference circuit  302  can be applied for a wider range of the system voltage VDD with low power consumption. Those skilled in the art should make modification or alterations accordingly. For example, components of the present invention can be applied as a whole or separately, to achieve respective effects. That is, even if the OPs  306 ,  308  of the bandgap reference circuit  302  do not include an input pair of PMOS transistors and a folded-cascode structure as mentioned above, layout area can still be reduced, and if the OP  108  of the bandgap reference circuit  102  includes an input pair of PMOS transistors and a folded-cascode structure, the bandgap reference circuit  102  can be applied for a wider range of the system voltage VDD with low power consumption as well. Besides, circuits of the start-up circuit  100  and the zero-TC current generator  310  are not limited to the embodiment of the present invention, as long as functions of the start-up circuit  100  and the zero-TC current generator  310  can be achieved. Furthermore, the BJTs Q 1 ′ and Q 2 ′ are realized by PNP BJTs as shown in  FIG. 3 , but can also be realized by NPN BJTs as shown  FIG. 5  as long as the structure are correspondingly modified. 
     In the prior art, since the current mirrors M 1 , M 2  and M 3  simultaneously mirror the PTAT current Iptat and the CTAT current Ictat, the extra resistor Rctat is required for balancing the CTAT current Ictat; and, if the OP  108  includes an input pair of PMOS transistors, the power consumption of the BJTs Q 1  and Q 2  can be reduced, but the OP  108  can not be applied for a wider range of the system voltage VDD, whereas if the OP  108  includes an input pair of NMOS transistors, the OP  108  can be applied for a wider range of the system voltage VDD, but the power consumption of the BJTs Q 1  and Q 2  is high. In comparison, the present invention utilizes the current mirrors M 1 ′, M 2 ′, M 3 ′ and the current mirrors M 4 , M 5  to mirror the PTAT current Iptat′ and the CTAT current Ictat′ respectively, so as to sum the PTAT current Iptat′ and the CTAT current Ictat′ and thus generate the zero-TC current Iref′. Therefore, the present invention does not need to utilize an extra resistor with a resistance L*R to balance CTAT current, and thus requires less layout area. Besides, the OPs  306 ,  308  include an input pair of PMOS transistors and a folded-cascode structure, such that the bandgap reference circuit  302  can be applied for a wider range of the system voltage VDD with low power consumption. 
     To sum up, the bandgap reference current source of the present invention requires less layout area, and can be applied for a wider range of a system voltage with low power consumption. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.