Abstract:
According to an aspect of the present disclosure, a method includes: receiving a plurality of groups of one or more phase signals, each group of phase signals having a different phase relative to other groups of one or more phase signals; generating a plurality of interpolated phase shifted signals based on the plurality of groups of one or more phase signals, wherein the plurality of interpolated phase shifted signals do not have an associated common mode component; receiving data bits and precompensating each data bit in accordance with a given interpolated phase shifted signal; and selecting a precompensated data bit for output.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 13/012,422, filed Jan. 24, 2011, and issued as U.S. Pat. No. 8,358,478, which is a continuation of U.S. application Ser. No. 12/538,056, filed Aug. 7, 2009, and issued as U.S. Pat. No. 7,880,986, which is a continuation of U.S. application Ser. No. 10/993,106, filed Nov. 18, 2004, and issued as U.S. Pat. No. 7,583,459. The disclosures of the applications referenced above are incorporated herein by reference. 
    
    
     BACKGROUND 
     The following disclosure relates to electrical circuits and signal processing. 
     In a magnetic recording system (e.g., a magnetic recording channel), data is typically written on or read from one or more data tracks of a magnetic storage medium such as a hard disk. The data tracks generally form concentric rings on the surface of the hard disk. When writing data onto a data track, a hard disk is rotated at a predetermined speed, and electrical signals applied to a magnetic read/write head floating over the data track are converted to magnetic transitions on the data track. The magnetic transitions can represent encoded digital data. For example, each transition (e.g., a rising edge or a falling edge) can correspond to a ONE bit value and the absence of a transition can correspond to a ZERO bit value, realizing a non return to zero inverted (NRZI) encoding of the data. 
     To obtain high density recording, magnetic transitions representing data bits are closely packed onto a magnetic storage medium. Such closely packed data bits may influence each other so that a non-linear magnetic shifting of transitions and bit interference may occur during recording. As a result, the reading of the high density recorded data bits may be adversely affected. 
     When writing data onto a high density magnetic recording medium, the position of transitions in a data stream can be adjusted (or precompensated) by a write precompensation circuit to correct for the influence of nearby transitions so that transitions in a recovered data stream are evenly placed. Precompensation of data being recorded can include offsetting a magnetic transition shift. The offset of the magnetic transition shift of a bit due to the pattern of preceding and/or succeeding bits can be anticipated and the bit recording time changed to compensate for the magnetic transition shift due to the effects of surrounding bits. 
     A typical write precompensation circuit has plural interpolators, each providing a predetermined delay (or phase shift) of a write clock cycle for a magnetic transition shift according to a given data bit pattern. For example, in the recording of a data stream, one of the interpolators can be selected to provide a predetermined phase shift (early, nominal, or late) of a write clock cycle for recording a present data bit according to one or more data bit patterns surrounding the present data bit. 
       FIG. 1  shows a conventional interpolator  100  of a write precompensation circuit. Interpolator  100  includes a differential pair having a pair of differential inputs PH 1 , PH 1 Bar (complement of PH 1 ), PH 2 , PH 2 Bar (complement of PH 2 ), and differential outputs OUT 1 , OUT 1 Bar (complement of OUT 1 ). Interpolator  100  includes bias currents I 1 -I 2 , transistors M 1 -M 4 , and resistors R 1 -R 2 . In general, interpolator  100  provides a phase shift for a write clock cycle that is an interpolation between phase signals PH 1  and PH 2 . Interpolator  100  provides the phase shift based on bias currents I 1  and I 2 . For example, if bias current I 1  is turned off, then interpolator  100  provides a phase shift that is substantially equal to that of phase signal PH 2 . And if bias currents I 1  and I 2  are substantially equal, then interpolator  100  provides a phase shift that is substantially in between those of phase signals PH 1  and PH 2 . 
     As bias current I 1  or I 2  is changed, a common mode component of output signals OUT 1  and OUT 1 Bar varies, and interpolator  100  therefore requires a certain amount of time to settle in order to output an accurate phase shift. The time to settle can be on the order of a few clock cycles. To avoid such delays due to settling, conventional write precompensation circuits typically require 2 N  interpolators, in which each interpolator provides a different phase shift for precompensation of a predetermined data pattern of N data bits. Accordingly, while four interpolators (for generating four different phase shifts) are needed to precompensate a corresponding (2) data bit pattern (e.g., [00], [01], [10] and [11]), the number of required interpolators increases as the data bit pattern is increased. For example, in a conventional write precompensation circuit, eight interpolators are needed to precompensate a (3) data bit pattern and sixteen interpolators are needed to precompensate a (4) data bit pattern. The increased number of interpolators to precompensate larger data bit patterns may add to the cost and complexity of a magnetic recording system. 
     SUMMARY 
     In general, in one aspect, this specification describes a write precompensation circuit including a plurality of interpolators. Each interpolator is operable to receive a plurality of groups of one or more phase signals and generate a plurality of interpolated phase shifted signals. Each group of phase signals have a different phase relative to other groups of one or more phase signals. The write precompensation circuit further includes a precompensation circuit and a selector. The precompensation circuit is operable to receive a data stream including one or more data bits and precompensate each data bit in accordance with a given interpolated phase shifted signal. The selector is operable to select a precompensated data bit output from the precompensation circuit. 
     Particular implementations can include one or more of the following. Each interpolated phase shifted signal generated by the plurality of interpolators can not have an associated common mode component or can not contain a current bias. Each of the plurality of interpolators can be operable to generate a given interpolated phase shifted signal corresponding to one or more data bit patterns assigned to each interpolator. The one or more data bit patterns can be assigned to each interpolator based on a criteria. The criteria can allow for at least a 2 clock cycle settling time before a given interpolator is selected to provide a next interpolated phase shifted signal. The multiplexer can be operable to select a precompensated data bit based on a data bit pattern. The data bit pattern can be one of a (2) bit data pattern, a (3) bit data pattern, or a (4) bit data pattern. The selector can be a multiplexer. 
     The write precompensation circuit can further include a write driver operable to receive the selected precompensated data bit and record the precompensated data bit onto a magnetic medium. The precompensation circuit can include a latch or flip-flop operable to precompensate each data bit. The flip-flop can be one of a D flip-flop, a T flip-flop, SR flip-flop, or a JK flip-flop. Each interpolator can include a plurality of phase input circuits and a plurality of switches corresponding to the plurality of phase input circuits. Each phase input circuit can be operable to receive a given phase signal. Each switch can be operable to couple a given phase signal to an output of the interpolator for interpolation. Each phase input circuit can be operable to convert a differential phase signal into a single-ended phase signal. 
     In general, in another aspect, this specification describes an interpolator. The interpolator includes an output node operable to provide an interpolated output signal. The interpolator further includes a plurality of phase input circuits and a plurality of switches corresponding to the plurality of phase input circuits. Each phase input circuit is operable to receive a given phase signal. Each switch is operable to couple a given phase signal to the output node. Each phase signal coupled to the output node by the plurality of switches are joined to form the interpolated output signal. 
     In general, in another aspect, this specification describes a disk drive system. The disk drive system includes a read channel, a write precompensation circuit, and a read/write head. The read channel is configured to provide a data stream to be recorded onto a surface of a disk. The write precompensation circuit is operable to precompensate each data bit of the data stream. The write precompensation circuit includes a plurality of interpolators, in which each interpolator is operable to receive a plurality of groups of one or more phase signals and generate a plurality of interpolated phase shifted signals. Each group of phase signals has a different phase relative to other groups of one or more phase signals. The interpolator further includes a precompensation circuit and a multiplexer. The precompensation circuit is operable to receive each data bit of the data stream and precompensate each data bit in accordance with a given interpolated phase shifted signal. The multiplexer is operable to select a precompensated data bit output from the precompensation circuit. The read/write head is operable to write each selected precompensated data bit onto the surface of the disk. 
     Implementations can include one or more of the following advantages. An interpolator circuit is provided that does not include a current bias and which has an output that does not contain a common mode component. The interpolator therefore has a quick settling time in providing differing phase shifts for precompensating a data bit. In one implementation, a write precompensation circuit is provided that includes a predetermined number of interpolators that is independent of a size of data bit patterns used for precompensation. In one implementation, a phase interpolator is provided that has reduced pulse pairing errors. Pulse pairing errors result from an asymmetry between positive and negative flux transitions—i.e., a different delay for rising and falling edges. 
     The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIG. 1  is a schematic diagram of a conventional interpolator of a write precompensation circuit. 
         FIG. 2  is block diagram of a write precompensation circuit. 
         FIG. 3  is a schematic diagram of an interpolator of  FIG. 2 . 
         FIG. 4  is a timing diagram illustrating the phase signals of the interpolator of  FIG. 3 . 
         FIG. 5  is a schematic diagram of a phase signal input circuit of the interpolator of  FIG. 3 . 
         FIG. 6  is block diagram of a write precompensation circuit. 
         FIG. 7  is a schematic block diagram of a hard disk drive system. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
       FIG. 2  illustrates a block diagram of write precompensation circuit  200 . In one implementation, write precompensation circuit  200  receives successive data bits and precompensates each data bit DATA(i) according to a bit pattern of one or more preceding data bits DATA(i−1), DATA(i−2), DATA(i−3), and so on, as discussed in greater detail below. Write precompensation circuit  200  can also precompensate each data bit DATA(i) according to a bit pattern including one or more succeeding data bits, e.g., data bits DATA(i+1), DATA(i+2), DATA(i+3), and so on. 
     Write compensation circuit  200  includes one or more interpolators  202 ( a )- 202 ( n ), a selector  204 , a control unit  206  and a write driver  208 . An output of each of interpolators  202 ( a )- 202 ( n ) is in communication with an input of selector  204 . A control input of selector  204  is in communication with control unit  206 . An output of selector  204  is in communication with an input of write driver  208 . 
     Each interpolator  202 ( a )- 202 ( n ) includes circuitry for generating one or more interpolated phase shifted signals to precompensate a given data bit DATA(i). Each interpolator  202 ( a )- 202 ( n ) generates a given interpolated phase shifted signal based on one or more input phase signals without using any current biases, and provides the phase shifted signal on a single-ended output, as discussed in greater detail below. Unlike a conventional interpolator that may include one or more current biases and/or a differential output, each interpolator  202 ( a )- 202 ( n ) does not require settling time in order to provide different interpolated phase shifted signals for write precompensation. 
     In one implementation, selector  204  receives precompensated data bits  210 ( a )- 210 ( n ) from each of interpolators  202 ( a )- 202 ( n ), respectively, and provides a selected precompensated data bit  214  to write driver  208  for recording onto a magnetic storage medium (not shown). Selector  204  is operable to select one of precompensated data bits  210 ( a )- 210 ( n ) in response to a control signal  212  from control unit  206 . Selector  204  can be a multiplexer. In one implementation, control unit  206  includes circuitry for generating control signal  212  based on a bit pattern of one or more preceding data bits DATA(i−1), DATA(i−2), DATA(i−3) and so on. For example, in a 2-bit look ahead implementation, control unit  206  can generate control signal  212  based on data bits DATA(i−1) and DATA(i−2). Control unit  206  can also include circuitry for generating control signal  206  in accordance with a bit pattern including one or more succeeding data bits, e.g., data bits DATA(i+1), DATA(i+2), DATA(i+3) and so on. 
       FIG. 3  illustrates one implementation of interpolator  202 ( a ). In one implementation, interpolator  202 ( a ) includes phase input circuits  300 - 330  and switches  350 - 380 . Switches  350 - 380  can include CMOS transistors (e.g., PMOS or NMOS transistors). Though interpolator  202 ( a ) is shown as having (16) phase input circuits  300 - 330  and (16) corresponding switches  350 - 380 , interpolator  202 ( a ) can contain any number of phase input circuits and corresponding switches to provide various granularities of resolution of a (interpolated) phase shifted signal. For example, in one implementation, interpolator  202 ( a ) includes (8) phase input circuits and (8) corresponding switches for each differential pair of input phase signals. In one implementation, each phase input circuit includes circuitry for converting a pair of differential phase input signals (e.g., phase signals PH 1 -PH 1 Bar) into only a single-ended phase signal (e.g., phase signals PH 1 ). 
     Each phase input circuit  300 - 306  has a first input in communication with phase signal PH 1  and a second input in communication with phase signal PH 1 Bar (complement of PH 1 ). Each phase input circuit  308 - 314  has a first input in communication with phase signal PH 2  and a second input in communication with phase signal PH 2 Bar. Each phase input circuit  316 - 322  has a first input in communication with phase signal PH 3  and a second input in communication with phase signal PH 3 Bar. Each phase input circuit  324 - 330  has a first input in communication with phase signal PH 4  and a second input in communication with phase signal PH 4 Bar. An output of each phase input circuit  300 - 330  is in communication with an input of switches  350 - 380 , respectively. An output of each of switches  350 - 380  is coupled together to form a single-ended output  390 . Output  390  represents an interpolated phase shifted signal based on one or more of phase signals PH 1 -PH 4 . 
       FIG. 4  shows a timing diagram, for one implementation, of phase signals PH 1 -PH 4 , PH 1 Bar-PH 4 Bar (respective complements of PH 1 -PH 4 ). As shown in  FIG. 4 , each phase signal PH 1 -PH 4 , PH 1 Bar-PH 4 Bar has a delay time of ΔT*(i+1) [i=0, 1, . . . , 0] with respect to phase signal PH 1 . In the example of  FIG. 4 , in which a cycle of PH 1  is T, the delay time ΔT is approximately equal to T/8 (e.g., 45°). 
     In operation, interpolator  202 ( a ) provides an interpolated output (e.g., output  390 ) based on a setting of switches  350 - 380 . For example, to provide an interpolated output between phase signal PH 1  and PH 2 , interpolator  202 ( a ) can operate as follows. Phase input circuits  300 - 306  respectively convert a group of (e.g., four) differential input phase signals PH 1 -PH 1 Bar into a single-ended phase signal PH 1  and phase input circuits  308 - 314  respectively convert a group of differential input phase signals PH 2 -PH 2 Bar into a single-ended phase signal PH 2 . A group of differential input phase signals can contain one or more differential input phase signals. Further, interpolator  202 ( a ) closes at least one of switches  350 - 364  and opens at least one of switches  366 - 380  to generate an interpolated output (e.g., output  390 ) having a phase between those of phase signals PH 1  and PH 2 . To provide a interpolated output having a phase closer to that of phase signal PH 2 , interpolator  202 ( a ) can close, e.g., each of switches  358 - 360  and switch  356 , while leaving switches  350 - 354  and  366 - 380  open. The interpolated output can be combined with a given data bit (e.g., data bit DATA (i)) using conventional techniques to generate a precompensated data bit (e.g., precompensated data bit  210 ( a ) of  FIG. 2 ). The interpolated output can be combined with a given data bit through a precompensation circuit that includes a latch or flip-flop. In one implementation, a D flip-flop is used to generate a precompensated data bit, as discussed in greater detail below. Other types of flip-flops can be used within the precompensation circuit, e.g., a T flip-flop, SR flip-flop, or a JK flip-flop. 
       FIG. 5  illustrates one implementation of phase input circuit  300 . In one implementation, phase input circuit includes PMOS transistors M 5 -M 6  and NMOS transistors M 7 -M 8 . A gate input of NMOS transistor M 7  is in communication with phase signal PH 1  and a gate input of NMOS transistor M 8  is in communication with phase signal PH 1 Bar. A source of each NMOS transistor M 7 -M 8  is in communication with a low voltage source VSS (e.g., 0 Volts). A drain of NMOS transistor M 7  is in communication with a drain and a gate input of PMOS transistor M 5  and a gate input of PMOS transistor M 6 . A source of each PMOS transistor M 5 -M 6  is in communication with a high voltage source VDD (e.g., 1.2 Volts). A drain of NMOS transistor M 8  is in communication with a drain of PMOS transistor M 6 . The drain of PMOS transistor M 6  forms an output of phase input circuit  300 . 
     Phase input circuit  300  converts a differential input signal (e.g., phase signals PH-PH 1 Bar) into a single-ended signal (e.g., phase signal PH 1 ) as follows. As NMOS transistor M 7  is enabled (e.g., turned on) (by a rising transition of phase signal PH 1 ), NMOS transistor M 8  is turned off (by a falling edge of phase signal PH 1 Bar). The gates of each of PMOS transistors M 5 -M 6  are pulled low (e.g., to ground) through NMOS transistor M 7 , and each of PMOS transistors are turned on. The output of phase input circuit is pulled high (e.g., to VDD) through PMOS transistor M 6 . As NMOS transistor M 7  is turned off by a falling transition of phase signal PH 1 , NMOS transistor M 8  is turned on by a rising edge of phase signal PH 1 Bar. The output of phase input circuit  300  is pulled low through NMOS transistor M 8 . The output of phase input circuit  300  therefore tracks the rising and falling edges of phase signal PH 1 . The output of phase circuit  300  does not contain a common mode component, and, therefore, the output settles quickly to a steady value. 
       FIG. 6  illustrates one implementation of a write precompensation circuit  600 . Write precompensation circuit  600  includes two interpolators  602 ,  604 , D flip-flops (D-FFs)  620 ,  622 , a selector  606 , a control unit  608  and a write driver  610 . D flip-flops (D-FFs)  620 ,  622 , form a precompensation circuit  624 . In one implementation, write precompensation circuit  600  includes at least two interpolators to prevent a loss of a write clock pulse when consecutive data bit patterns require a write clock shift of ½T and −½T within a single clock cycle. 
     Interpolator  600  generally operates substantially the same as write precompensation circuit  200  of  FIG. 2 . That is, each interpolator  602 ,  604  includes circuitry for generating one or more interpolated phase shifted signals to precompensate a given data bit DATA(i). Selector  606  receives precompensated data bits  612 ,  614  from each of interpolators  602 ,  604 , respectively, and provides a selected precompensated data bit  618  to write driver  610  for recording onto a magnetic storage medium (not shown). Selector  204  is operable to select one of precompensated data bits  210 ( a )- 210 ( n ) in response to a control signal  212  from control unit  206 . 
     In one implementation, each interpolator  602 ,  604  is operable to provide a given interpolated phase shifted signal corresponding to data bit patterns (or transitions). In one implementation, each interpolator  602 ,  604  is operable to provide a given interpolated phase shifted signal corresponding to one or more data bit patterns assigned to each interpolator  602 ,  604 . Which data patterns assigned to a given interpolator  602 ,  604  depends on a criteria. In one implementation, the criteria used to assign a data pattern to an interpolator allows for at least a 2 clock cycle settling time before the interpolator is selected to provide a next interpolated phase shifted signal. For example, in a (2) bit pattern implementation, interpolator  602  provides an interpolated phase shifted signal for each of data patterns [00], [10], and [11], while interpolator  604  provides an interpolated phase shifted signal corresponding to data pattern [01]. In a (3) bit pattern implementation, interpolator  602  provides an interpolated phase shifted signal for each of data patterns [000], [010], [011], [100], and [110]; interpolator  604  provides an interpolated phase shifted signal for each of data patterns [001], [101], and [111]. In a (4) bit pattern implementation, interpolator  602  provides an interpolated phase shifted signal for each of data patterns [0000], [0010], [0011], [0100], [0110], [1000], [1010], [1011], [1100], [1110], and [1111]; interpolator  604  provides an interpolated phase shifted signal for each of data patterns [0001], [0101], [0111], [1001], and [1101]. Accordingly, each interpolator  602 ,  604  therefore has at least 2 clock cycles to settle before providing a next interpolated phase shifted signal. According to one particular transition—i.e., a [1]) to [11]transition or a [111] to [111]transition, and so on—a given interpolator must provide an interpolated output (interpolated phase shifted signal) within a single clock cycle delay. In this case, however, because each interpolator output does not contain a common mode component, each interpolator can provide a steady interpolated output within a single clock cycle. Such a quick settling time reduces pulse pairing errors. 
     In one implementation, precompensated data bits  612 ,  614  are respectively generated through D-FFs  620 ,  622 . More specifically, D-FFs  620 ,  622  receive as input data bits DATA(i), and the output of interpolators  602 ,  604  are used to respectively clock data bits DATA(i) through D-FFs  620 ,  622  to generate precompensated data bits  612 ,  614 . In one implementation, only a single D-FF (not shown) is used to generate precompensated data bits. In such an implementation, MUX  606  selects an interpolated output directly from one of interpolators  602 ,  604 . The selected interpolated output is used to clock the single D-FF to generate the precompensated data bits. 
     Write precompensation circuits  200 ,  600  can be used with circuitry of a disk drive system  700 , as shown in  FIG. 7 . Disk drive system  700  includes a read/write head  702 , a write precompensation circuit (e.g., precompensation circuits  600 ) and a read channel  704 . 
     In a write operation, an data stream to be recorded is provided by read channel  704  to write precompensation circuit  600 . Write precompensation circuit precompensates each data bit of the data stream and provides precompensated data to read/write head  702 . Read/write head  702  locates an appropriate sector of a disk (not shown) and writes the precompensated data onto the disk. 
     A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the step of methods described above may be performed in a different order and still achieve desirable results. Accordingly, other implementations are within the scope of the following claims.