Abstract:
A microelectronic assembly includes a substrate having a first surface, a plurality of first conductive pads exposed thereon, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to one of the conductive pads. Each metal post extends along a side wall from the base to ends remote from the conductive pad. The assembly further includes a dielectric material layer having a plurality of openings and extending along the first surface of the substrate. The first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries thereof. Fusible metal masses contact the ends of some of first metal posts and extend along side walls towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically can be connected the conductive pads.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This invention is a continuation of U.S. patent application Ser. No. 12/286,102, filed Sep. 26, 2008, which claims the benefit of U.S. Provisional Patent Application No. 60/995,849 filed Sep. 28, 2007, the disclosures of which is hereby incorporated herein by reference. 
     
    
     BACKGROUND OF THE INVENTION 
       [0002]    The present invention relates to microelectronic apparatuses and packaging microelectronic components for microelectronic packages and assemblies. 
         [0003]    Microelectronic devices generally comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a die or a semiconductor chip. Semiconductor chips are commonly provided as individual, prepackaged units. In some unit designs, the semiconductor chip is mounted to a substrate or chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board. 
         [0004]    In one face of the semiconductor chip is fabricated the active circuitry. To facilitate electrical connection to the active circuitry, the chip is provided with bond pads on the same face. The bond pads are typically placed in a regular array either around the edges of the die or, for many memory devices, in the die center. The bond pads are generally made of a conductive metal, such as gold or aluminum, around 0.5 μm thick. The size of the bond pads will vary with the device type but will typically measure tens to hundreds of microns on a side. 
         [0005]    Flip-chip interconnection is a commonly used scheme for conductively connecting bond pads on the semiconductor chip to contact pads on a substrate. In flip-chip interconnection, lumps of metal are typically placed on each bond pad. The die is then inverted so the metal lumps provide both the electrical pathway between the bond pads and the substrate as well as the mechanical attachment of the die to the substrate. 
         [0006]    There are many variations of the flip-chip process, but one common configuration is to use solder for the lumps of metal and fusion of the solder as the method of fastening it to the bond pads and the substrate. When it melts the solder flows to form truncated spheres. 
         [0007]    Despite the advances that have been made in flip chip interconnections, there is still need for improvements in order to minimize the package thickness, while enhancing joint reliability. These attributes of the present invention are achieved by the construction of the microelectronic packages as described hereinafter. 
       SUMMARY OF THE INVENTION 
       [0008]    According to an embodiment of the invention, there is a packaged microelectronic element that includes a microelectronic element having a front surface and a plurality of first solid metal bumps extending away from the front surface. Each of the posts has a width in a direction of the front surface and a height extending from the front surface, wherein the height is at least half of the width. There is also a substrate that has a top surface and a plurality of second solid metal posts extending from the top surface and joined to the first solid metal posts with a fusible metal. The second posts have top surfaces and edge surfaces extending abruptly away from said top surface of the substrate. 
         [0009]    The posts of this embodiment may be etched and comprised essentially of copper. Additionally, underbump metallizations may underly the first bumps. A ratio of a diameter of the first posts to a pitch between the first posts may be no more than 3:4. Furthermore, a diameter of the first posts may be less than one-half of a pitch between each of the first posts. 
         [0010]    In another embodiment, a packaged microelectronic element comprises a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each post has a width in a direction of the front surface and a height extending from the front surface, wherein the height is at least half the width. There is also a substrate having a top surface and a plurality of second solid metal posts extending from the top surface and joined to the first solid metal posts. In this embodiment, the first and second posts are diffusion-bonded together. 
         [0011]    The ratio of a diameter of the first posts to a pitch between the first posts may be no more than 3:4. The distance between the front surface of the microelectronic element and the top surface of the substrate may be greater than 80 microns. Furthermore, each of the first posts may have a diameter that is equal to a diameter of each of the second metal posts. Finally, an underfill material may be deposited between the front surface of the microelectronic element and the top surface of the substrate. 
         [0012]    In still another embodiment, a packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each post has a width in a direction of the front surface and a height extending from the front surface. The posts consist essentially of metal other than solder, lead, or tin. There is also a substrate that has a top surface. A plurality of second solid metal posts extend from the top surface and are joined to the first solid metal posts with a fusible metal. A ratio of a diameter of the first or second solid metal posts to a pitch between the plurality of the first or second solid metal posts is no more than 3:4. 
         [0013]    In an alternative to this embodiment, the substrate may be a multilayer substrate. Additionally, a diameter of the first posts may be less than one-half of a pitch between each of the first posts. Furthermore, each of said first posts may have a diameter that is equal to a diameter of the second metal posts. 
         [0014]    In another embodiment, a packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. Each post has a width in a direction of the front surface and a height extending from the front surface. There is a substrate that has a top surface. A plurality of second solid metal posts extend from the top surface and are joined to the first solid metal posts. A pitch of the first posts ranges between 50 and 200 microns and a distance between the bottom surface of the microelectronic element and the top surface of the substrate is greater than 80 microns. 
         [0015]    In an alternative of this embodiment, a fusible metal may be used to join the second posts to the first posts. Each of the first posts may have a diameter that is equal to a diameter of the second metal posts. Furthermore, a diameter of the first posts may be less than one-half of a pitch between each of the first posts. 
         [0016]    In another embodiment, a packaged microelectronic element includes a microelectronic element, a substrate, and a plurality of pillars extending between the microelectronic element and the substrate. Each of the plurality of pillars comprise a first metal post portion attached to the microelectronic element, a second metal post portion attached to the substrate, and a metal fusion portion, wherein the first and second metal portions are joined together. The plurality of pillars having a length not less than 50 microns. The height of the first and second metal post portions is at least half of the width. 
         [0017]    In an alternative of this embodiment, a distance between the front surface of the microelectronic element and the top surface of the substrate is greater than 80 microns. The substrate may also be a multilayer substrate. 
         [0018]    Each of the first posts may have a diameter that is equal to a diameter of the second metal posts. A diameter of the first posts may be less than one-half of a pitch between each of the first posts. Additionally, the first or second posts may be etched. 
         [0019]    A method of fabricating a packaged microelectronic element assembly includes providing a microelectronic element having a plurality of conductive posts extending away from a first surface of a microelectronic element. The posts have top surfaces and edge surfaces extending abruptly away from the top surfaces. A fusible metal cap is attached to an end of each of the plurality of conductive posts. Another next step includes at least substantially aligning the posts of the microelectronic element with a plurality of posts extending from a first surface of a substrate. The last step includes joining the posts of the microelectronic element with the posts of the substrate. 
         [0020]    In an alternative method, step (c) includes heating the fusible metal to a melting temperature, wherein the fusible metal flows onto exposed portions of the edge surfaces of the posts. 
         [0021]    In another alternative method, a passivation layer and an underbump metallization layer are deposited over the microelectronic element. 
         [0022]    A further embodiment relates to a microelectronic assembly including a substrate having a first surface, a plurality of first conductive pads exposed on the first surface, and a plurality of first metal posts. Each metal post defines a base having an outer periphery and is connected to a respective one of the first conductive pads. Each metal post extends along a side wall from the base to ends remote from the first conductive pad. The assembly further includes a dielectric material layer having an inner surface, an outer surface, and a plurality of openings. The inner surface extends along the first surface of the substrate, the outer surface being remote from the substrate. Respective ones of the first metal posts project through the openings such that the dielectric material layer contacts at least the outside peripheries of the first metal posts. A plurality of fusible metal masses contact the ends of at least some of first metal posts and extend along side walls of the first metal posts towards the outer surface of the dielectric material layer. A microelectronic element is carried on the substrate and is electronically connected to at least some of the first conductive pads. 
         [0023]    The microelectronic element can include a first side facing the first surface of the first substrate and can have a plurality of contacts exposed thereon. Further, the contacts can be electrically and mechanically connected to at least some of the first fusible metal masses. Additionally, the first surface of the substrate can include a first region and a second region. At least two fusible metal masses can be located within the first region and at least two of the fusible metal masses can be located within the second region. The plurality of contacts on the microelectronic element can be connected to the fusible metal masses located within the second region such that the microelectronic region overlies the second region. The substrate can further include a plurality of second metal posts extending from the second region of the first surface thereof. In such an instance, the microelectronic element can include a first surface and a plurality of second metal posts extending away from the first surface thereof that can be joined to the second metal posts of the substrate with a fusible metal. 
         [0024]    Each of the plurality of openings in the dielectric material layer can define an inside surface that extends along a portion of the sidewall of a respective one of the first metal posts in substantial contact therewith. Further, the side walls of the first posts are substantially straight along a cross-sectional portion thereof and can taper inward from the bases to the ends thereof or be substantially perpendicular to the faces of the conductive pads. Alternatively, each of the first metal posts can include a substantially straight portion extending from the end thereof and a transition portion extending from the outer periphery of the base. In such an arrangement, the transition portion can be substantially arcuate along a cross-sectional profile of the first metal post. At least one of the first conductive posts can include a plating layer forming the end surface and at least a portion of the side wall thereof. 
         [0025]    In a further embodiment, a microelectronic assembly, as described above is included in stacked microelectronic assembly along with at least a second microelectronic assembly. The second microelectronic assembly includes a substrate having an outer surface with a plurality of second conductive pads exposed thereon. The plurality of second conductive pads are affixed to respective ones of the plurality of fusible metal masses, thereby electronically connecting the plurality of second conductive pads to respective ones of the first metal posts. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0026]      FIGS. 1A and 1B  are sectional views of the components of a microelectronic assembly in accordance with one embodiment. 
           [0027]      FIG. 1C  is a sectional view illustrating  FIGS. 1A and 1B  being joined together. 
           [0028]      FIG. 2  is a sectional view illustrating a microelectronic assembly in accordance with the embodiment of  FIGS. 1A-1C . 
           [0029]      FIG. 2A  is an exploded sectional view of a portion of  FIG. 2 . 
           [0030]      FIG. 3  is a sectional view illustrating a completed microelectronic assembly in accordance with a variation of the embodiment shown in  FIG. 2 . 
           [0031]      FIG. 4  is a sectional view illustrating a completed microelectronic assembly in accordance with in accordance with a variation of the embodiment shown in  FIG. 2 . 
           [0032]      FIG. 5  is a sectional view illustrating the components of a microelectronic assembly in accordance with another embodiment. 
           [0033]      FIG. 6  is a sectional view illustrating components of a microelectronic assembly in accordance with a variation of the embodiment shown in  FIG. 5 . 
           [0034]      FIG. 7  is a sectional view illustrating a completed microelectronic assembly in accordance with one embodiment. 
           [0035]      FIG. 8  is a sectional view illustrating a completed microelectronic assembly in accordance with another embodiment. 
           [0036]      FIG. 9  is a sectional view illustrating a completed microelectronic assembly in accordance with another embodiment. 
           [0037]      FIG. 10  is a sectional view illustrating a completed microelectronic assembly in accordance with another embodiment. 
           [0038]      FIG. 11  is a sectional view illustrating a completed microelectronic assembly in accordance with another embodiment. 
           [0039]      FIG. 12  is a sectional view illustrating a completed microelectronic assembly in accordance with another embodiment. 
           [0040]      FIG. 13  is a sectional view illustrating a completed microelectronic assembly in accordance with another embodiment. 
       
    
    
     DETAILED DESCRIPTION 
       [0041]    Reference is now made to  FIGS. 1A-1C , which illustrate cross-sectional views of the components of the packaged microelectronic assembly  100  shown in  FIG. 2 . As shown, the packaged microelectronic assembly  100  includes a substrate  102 , a microelectronic element  104  in a face down or flip chip position, and conductive columns  106  joining the substrate with the microelectronic element. The conductive columns include conductive bumps or posts  108  which protrude above a fact  105  of the substrate  102  that are aligned with conductive bumps or posts  110  protruding above a face  107  of the microelectronic element  104 . The conductive columns  106  provide for increased height for chip-on-substrate packaging by increasing the standoff or vertical distance between the microelectronic element  104  and substrate  102 , while at the same time allowing for a decrease in the center-to-center horizontal distance or pitch P between conductive columns  106 . As will be discussed in further detail below, the ability to increase the distance between the substrate  102  and the microelectronic element  104  may help reduce stress at the conductive columns, may help ease the application of underfill material  112  (see  FIG. 2A ), and allow for a greater variety of underfills to be used. 
         [0042]    With reference to  FIG. 1A , the substrate  102  preferably includes a dielectric element  102 A. The dielectric element  102 A having a top surface  101  and an oppositely facing bottom surface  103 . A plurality of conductive traces  109  may extend along the top or bottom surfaces or both. The dielectric element  102 A may be rigid or flexible. The dielectric element  102  may be comprised of a polyimide or other polymeric sheet. Although the thickness of the dielectric element  102  may vary, the dielectric element  102 A most typically up to 2 millimeters. The substrate  102  may include other conductive elements such as external contacts (not shown) exposed at the bottom surface  103 . The bond traces may be created using the methods illustrated in commonly assigned U.S. Published application Ser. No. 11/014,439, the disclosure of which is hereby incorporated by reference herein. In the particular embodiment illustrated, the conductive elements (not shown) are disposed on the top surface  101  of substrate  102 . However, in other embodiments, the conductive elements may also extend along the bottom surface  103  of substrate  102 ; on both the top and bottom surfaces  101 ,  103  or within the interior of the substrate  102 . Thus, as used in this disclosure, a statement that a first feature is disposed “on” a second feature should not be understood as requiring that the first feature lie on a surface of the second feature. Additionally, descriptive words such as “top,” “bottom,” “upper,” and “lower” are used only for illustration purposes. 
         [0043]    Solid metal bumps or conductive posts  108  also extend from the top surface  101  of the substrate  102  to form the first portion of the conductive columns  106  ( FIGS. 2 and 2A ). The conductive posts  108  have top surfaces  111  and edge surfaces  113  extending abruptly away from the top surface of the substrate  102  such that a distinct angle is created where the edge surfaces  113  meet the top surfaces  101  of the substrate  102 . For example, in the embodiment shown, an angle greater than 90 degrees is created between the top surfaces  101  of the substrate  102  and the edge surfaces  113  of the conductive posts  108 . The angle will differ based upon the shape of the conductive post  108 . For example, a cylindrical post may have an angle of 90 degrees between the top surface  101  of the substrate  102  and the conductive post  108 . Exemplary processes and posts are described in Provisional Applications Nos. 60/875,730, filed on Dec. 19, 2006, and entitled Chip Capacitor Embedded PWB; 60/964,916, filed on Aug. 15, 2007, and entitled Multilayer Substrate with Interconnection Vias and Method of Manufacturing the Same; 60/964,823 filed on Aug. 15, 2007, and entitled Interconnection Element with Posts Formed by Plating; the disclosures all of which are incorporated herein by reference. For example, the conductive posts  108  may be formed by etching processes, as described in more detail herein. Alternatively, conductive posts  108  may be formed by electroplating, in which posts  108  are formed by plating a metal onto a base metal layer through openings patterned in a dielectric layer such as a photoresist layer. 
         [0044]    The dimensions of the conductive posts  108  can vary over a significant range, but most typically the height H 1  of each conductive post  108  extending from the top surface  103  of dielectric element  102 A is at least 50 microns and can extend up to 300 micrometers. These conductive posts  108  may have a height H 1  that is greater than its diameter or width W 1 . However, the height H 1  may also be smaller than the width W 1 , such as at least half the size of the width W 1 . 
         [0045]    The conductive posts  108  may be made from any electrically conductive material, such as copper, copper alloys, gold and combinations thereof. The conductive posts  108  may include at least an exposed metal layer that is wettable by solder. For example, the posts may be comprised of copper with a layer of gold at the surfaces of the posts. Additionally, the conductive posts  108  may include at least one layer of metal having a melting temperature that is greater than a melting temperature of the solder to which it will be joined. For example, such conductive posts  108  would include a layer of copper or be formed entirely of copper. 
         [0046]    The conductive posts  108  may also take on many different shapes, including frustoconical. The base  114  and tip  116  of each of the conductive posts  108  may be substantially circular or have a different sha+pe, e.g. oblong. The bases  114  of the conductive posts  108  typically are about 50-300 μm in diameter, whereas the tips  116  typically are about 25-200 μm in diameter. Each conductive post  108  may have a base  114  adjacent the dielectric substrate  102  and a tip  116  remote from the dielectric substrate. Additionally, the height H 1  of the conductive posts from the top surface  101  of the dielectric element  102 A (excluding any solder mask) typically ranges from as little as 30 μm up to 200 μm. 
         [0047]    As shown, solder mask  118  ( FIG. 2 ) may be disposed over the substrate  102  and adjacent the conductive posts  108 . The solder mask  118  helps to prevent solder overflow and bridging between adjacent columns  106  during the reflow phase. 
         [0048]    Referring to  FIG. 1B , the microelectronic element  104  has a front surface  122  and a rear surface  124 . The microelectronic element  104  is preferably a semiconductor chip or the like prior to its packaging and interconnection with another element. For example, the microelectronic element is a bare die. 
         [0049]    Exemplary conductive posts and methods of making conductive posts capable of extending from a microelectronic element or the like are described on the website of Advanpak Solutions Pte. Ltd. (“Advanpak”), as well as in U.S. Pat. Nos. 6,681,982; 6,592,109; and 6,578,754 that are assigned to Advanpak, and the disclosures of which are incorporated herein by reference. For example, the conductive posts  110  may be formed by etching processes. Alternatively, conductive posts  110  may be formed by electroplating, in which posts  110  are formed by plating a metal onto a base metal layer through openings patterned in a photoresist layer. Like the conductive posts  108  extending from the substrate, the posts  110  extending from the microelectronic element  104  may have top surfaces  111  and edge surfaces  113  extending abruptly away from said top surface  122  of the microelectronic element such that a distinct angle is created between the microelectronic element and the conductive posts. 
         [0050]    To provide a metal contact between the conductive posts  110  and the microelectronic element  104 , an underbump metallization layer  120  may be provided on the front surface  122  of the microelectronic element  104 . The underbump metallization layer  120 , is typically composed of a material including titanium, titanium-tungsten, chromium. The underbump metallization layer  120  operates as the conducting metal contact for the conductive columns  106 . A passivation layer  119  may also be provided on the front surface  122  of the microelectronic element  104  between the microelectronic element  104  and the underbump metallization layer  120  using known methods in the art. 
         [0051]    Referring to  FIGS. 1B ,  1 C, and  2 , the dimensions of the conductive posts  110  extending from the microelectronic element  104  may also vary over a significant range, but most typically the height H 2  of each conductive post  110  is not less than 50 microns. The conductive posts  110  may have a height H 2  that is greater than its width W 2 . However, the height may also be smaller than the width W 2 , such as at least half the size of the width. 
         [0052]    The conductive posts  110  are preferably made from copper or copper alloys, but may also include other electrically conductive materials, such as gold or combinations of gold and copper. Additionally, the conductive posts  110  may include at least one layer of metal having a melting temperature that is greater than a melting temperature of the solder to which it will be joined. For example, such conductive posts would include a layer of copper or be formed entirely of copper. 
         [0053]    In a particular embodiment, the conductive posts  110  can be cylindrical, so that the diameter of the bases  126  of the post and tips  128  of the posts are substantially equal. In one embodiment, the bases  126  and tips  128  of the conductive posts can be about 30-150 μm in diameter. Each conductive post  110  may have a base  126  adjacent the substrate  102  and a tip  128  remote from the substrate  102 . Alternatively, the conductive posts  110  may take on a variety of shapes, such as frustroconical, rectangular, or bar-shaped. 
         [0054]    A coating or cap of solder  130  may be attached to the tips  128  of the conductive posts  110  or the portion of the conductive posts that are not attached to the microelectronic element  104 . The cap of solder  130  can have the same diameter or width W 2  of the conductive posts  110  so that it becomes an extension of the conductive post  110 . In one example, the cap of solder  130  can have a height H 3  ranging from approximately 25-80 μm. 
         [0055]    It should be appreciated that the height H 2  of the conductive posts  110  extending from the front surface  122  of the microelectronic element  104  can be equal to the height H 1  of the conductive posts  108  extending from the top surface  101  of the dielectric element  102 A ( FIG. 1A ). However, the heights may alternatively differ, such that the height H 2  of the conductive posts  110  can be less than or greater than the height H 1  of the conductive posts  108 . In a particular illustrative example, the conductive posts  110  extending from the microelectronic element  104  may have a height H 2  of 50 μm in length, whereas the conductive posts  108  extending from the substrate may have a height H 1  of 55 μm ( FIG. 2 ). 
         [0056]    To conductively connect the microelectronic element  104  and substrate  102  together, the conductive posts  110  on the microelectronic element  104  must be connected to the conductive posts  108  on the substrate  102 . Referring to  FIG. 1C , the microelectronic element  104  is inverted so that the conductive posts  110  of the microelectronic element  104  and the conductive posts  108  of the substrate  102  are aligned with one another and brought into close proximity. The cap of solder  130  on the microelectronic element  104  is reflowed to allow the solder to wet the surfaces of the conductive posts  110  on the microelectronic element  104  and the conductive posts  108  on the substrate  102 . As shown in  FIGS. 2-2A , the solder will wet to the exposed surfaces of the conductive posts and create a conductive column  106  that extends from the microelectronic element to the substrate. The increased surface areas of the conductive columns  108 ,  110  on the microelectronic element  104  and substrate  102  to which the solder is joined can help reduce the current density at the solder interface. Such decrease in current density may help reduce electromigration and provide for greater durability. 
         [0057]    As shown, the conductive columns  106  include solder conductively interconnecting the conductive posts. The standoff or height H of the conductive columns extending between the base of the conductive post extending from the microelectronic element and the exposed portions of the base extending from the substrate in one example ranges 80-100 μm. 
         [0058]    As shown in  FIGS. 2 ,  2 A, the walls  132  of the conductive columns  106  can be convex or barrel shaped, wherein the midpoint region M of the conductive column (i.e., between the conductive posts  110  of the microelectronic element and conductive posts  108  of the substrate) has a width W that is greater than the widths W 1 , W 2  of the portions of the conductive columns  106  respectively adjacent the top surface  101  of the substrate  102  and front surface  102  of the microelectronic element  104 . 
         [0059]    As further shown in  FIG. 2A , contact pads  117  may be formed on the microelectronic element  104  and substrate  102  using known methods. In one embodiment, the lower post  108  that extends away from the substrate  102 , as well as the lower contact pad  117  may be formed by separate etching steps, such as disclosed in International Application PCT No. WO 2008/076428, which published on Jun. 28, 2008 and the disclosure of which is incorporated herein by reference. For example, a tri-metal substrate with top and bottom metal layers  123  and in intermediate etch stop layer or interior metal layer  121  may be utilized to create the conductive post  108  and contact pad  117 . In one such process, an exposed metal layer of a three-layer or more layered metal structure is etched in accordance with a photolithographically patterned photoresist layer to form the conductive post  108 , the etching process stopping on an interior metal layer  121  of the structure. The interior metal layer  121  includes one or more metals different from that of the top and bottom metal layers  123 , the interior metal layer being of such composition that it is not attached by the etchant used to etch the top metal layer  123 . For example, the top metal layer  123  from which the conductive posts  108  are etched consists essentially of copper, the bottom metal layer  123  may also consist essentially of copper, and the interior metal layer  121  consists essentially of nickel. Nickel provides good selectivity relative to copper to avoid the nickel layer from being attached with the metal layer is etched to form conductive posts  108 . To form the contact pad  117 , another etching step may be conducted in accordance with another photolithographically patterned photoresist layer. The post  108  may be further interconnected with other conductive features such as a via  115 , which is, in turn, further interconnected to other conductive features (not shown). 
         [0060]    Referring to  FIG. 3 , the walls  232  of the conductive columns  106  may also be straight, such that the width W 5  is about equal to the widths W 4 , W 4 ′ of the conductive columns  106 ′ respectively adjacent the top surface  101 ′ of the substrate  102 ′ and front surface  122 ′ of the microelectronic element  104 ′. It should be appreciated that the widths W 4 , W 4 ′ do not need to be equal. Alternatively, the walls  232  of the conductive columns  106  may be concave (see  FIG. 4 ), depending on the desired standoff to be achieved. 
         [0061]    The conductive columns  106  in accordance with the present invention allow for a greater standoff height between the dielectric element and the microelectronic element while permitting a significant reduction in the pitch P (see  FIGS. 1B ,  2 ) between each of the conductive posts  110  exposed at the front surface  122  of the microelectronic element  104 , as well as the pitch P between each of the conductive posts  108  exposed at the top surface  101  of the substrate  102 . In one embodiment, the pitch P may be as small as 50 μm or as large as 200 μm. It should be appreciated that by virtue of the fact that the conductive columns  108 ,  110  are aligned with one another, the pitch P between each of the conductive posts  108 ,  110  will be equal. 
         [0062]    The pitch P may also be a function of the diameter or width W 1 , W 2  of the conductive posts  108 ,  110 , such that the diameter W 1 , W 2  of the base of the conductive posts is up to 75% of the pitch P. In other words, the ratio of the diameter W 1 , W 2  to the pitch P can be up to 3:4. For example, if the pitch P is 145 μm, the diameter W 1 , W 2  of the conductive posts  108 ,  110  may range up to 108 μm or 75% of the pitch P. 
         [0063]    The increased standoff height reduces the strain on Low-k dielectric materials which can be present in the microelectronic element. Additionally, the increased standoff helps to minimize the problems typically associated with small pitches, such as electromigration and crowding. This is due to the fact that the conductive columns  106  are able to wet the surfaces of the conductive posts  108 ,  110 . 
         [0064]    Referring to  FIGS. 5-6 , alternative arrangements for joining the conductive bumps on the microelectronic element with the conductive bumps on the substrate are shown. With reference to  FIG. 5 , instead of the solder cap  230  being placed at the tip  228  of the conductive post  210  extending from the microelectronic element  204 , the solder cap  230  can be placed at the tip  216  of the conductive post  208  extending from the substrate  202 . In one embodiment, the width or diameter W 5  of the solder cap  230  is roughly equal to the diameter W 6  of the base  214  of the conductive post  208 . The solder cap  230  therefore extends beyond the tip  216  of the conductive post  208  extends from the substrate  202 . Once the solder is reflowed, however, the conductive column will preferably take the shape of the conductive column shown in  FIG. 2 . 
         [0065]    Referring to  FIG. 6 , in yet another alternative arrangement, solder caps  330  may be placed onto the conductive posts  310 ,  308  extending from both the microelectronic element  304  and the substrate  302 . The conductive posts  308 ,  310  are placed in close proximity to one another. Heat is applied causing the solder caps  330  to reflow, wet, and fuse to the conductive posts  308 ,  310 . Once reflowed, the conductive column  306  will preferably be similar to the conductive column  306  shown in  FIG. 2 . 
         [0066]    With reference to  FIG. 7 , an alternative arrangement for a microelectronic package is shown. The arrangement is similar to the one shown in  FIG. 2 , the only difference being the absence of a solder mask adjacent the conductive posts extending from the substrate. In this alternative arrangement, vias  307  can be used to conductively connect the conductive columns  406  to electronic circuitry (not shown) exposed at the bottom surface of the substrate  402 , as opposed to the top surface  401  of the substrate  402 . The use of vias  307  obviates the need for the solder mask. 
         [0067]    Referring to  FIG. 8 , an alternative embodiment is shown, wherein a metal-to-metal bond between the conductive posts is made without the use of solder. Instead, a bond may be formed between the conductive posts  508 ,  510  by deforming them into engagement with each other. The conductive posts  508 ,  510  are preferably formed from a malleable material with minimal resilience or spring-back as, for example, substantially pure gold. Furthermore, the conductive posts  508 ,  510  may be bonded together by eutectic bonding or anodic bonding between the posts and the material of the cover. For example, the tips  516 , S 17  of the conductive posts  508 ,  510  may be coated with a small amount of tin, silicon, germanium or other material which forms a relatively low-melting alloy with gold, and the posts may be formed entirely from gold or have a gold coating on their surfaces. When the conductive posts  508 ,  510  are engaged with one another and then heated, diffusion between the material of conductive posts  508 ,  510  and the material on the tips  516  of the conductive posts forms an alloy having a melting point lower than the melting points of the individual elements at the interfaces between the posts and walls. With the assembly held at elevated temperature, further diffusion causes the alloying element to diffuse away from the interface, into the bulk of the gold of the posts, thereby raising the melting temperature of the material at the interface and causing the interface to freeze, forming a solid connection between the parts. 
         [0068]    Referring to  FIG. 9 , which is identical to  FIG. 8 , except that the conductive posts  608 ,  610  are both preferably comprised of copper and are fused directly to one another without the presence of a low melting temperature metal such as a solder or tin between the conductive posts. Preferably, in order to achieve a strong bond, the joining surfaces of the conductive posts  608 ,  610  must be clean and substantially free of oxides, e.g., native oxides, before the conductive posts  608 ,  610  are joined to the terminals. Typically, a process characterized as a surface treatment of etching or micro-etching can be performed to remove surface oxides of noble metals such as copper, nickel, aluminum, and others, the surface etching process being performed without substantially affecting the thicknesses of the bumps or metal layer which underlies them. This cleaning process is best performed only shortly before the actual joining process. Under conditions in which the component parts are maintained after cleaning in a normal humidity environment of between about 30 to 70 percent relative humidity, the cleaning process can usually be performed up to a few hours, e.g., six hours, before the joining process without affecting the strength of the bond to be achieved between the bumps and the capacitor terminals. 
         [0069]    As illustrated in  FIGS. 10-11 , during a process performed to join the conductive posts  608 ,  610 , a spacer structure  726  is placed on the top surface  601  of the substrate  602 . The spacer structure  626  can be formed of one or more materials such as polyimide, ceramic or one or more metals such as copper. The microelectronic element  604  from which conductive posts  610  extend are placed above the spacer structure  626 , such that the tips  628  of the conductive posts  610  of the microelectronic element  604  overlie the tips  616  of the conductive posts  608  of the substrate  602 . Referring to  FIG. 10 , the spacer structure  626 , microelectronic element  604  and substrate  602  are inserted between a pair of plates  640  and heat and pressure are simultaneously applied to the conductive posts in the directions indicated by arrows  636 . As illustrated in  FIG. 9 , the pressure applied to plates  640  has an effect of reducing the height of the conductive posts to a height H 6  lower than an original height H 5  of the conductive posts  608 ,  610  as originally fabricated ( FIG. 10 ). An exemplary range of pressure applied to during this step is between about 20 kg/cm 2  and about 150 kg/cm 2 . The joining process is performed at a temperature which ranges between about 140 degrees centigrade and about 500 degrees centigrade, for example. 
         [0070]    The joining process compresses the conductive posts  608 ,  610  to an extent that metal from below the former top surfaces of the conductive posts  608 ,  610  comes into contact and joins under heat and pressure. As a result of the joining process, the height of the conductive posts  608 ,  610  may decrease by one micron or more. When the conductive posts  608 ,  610  consist essentially of copper, the joints between the conductive posts also consist essentially of copper, thus forming continuous copper structures including the bumps and terminals. Thereafter, as illustrated in  FIG. 9 , the plates and spacer structure are removed, leaving a subassembly  250  having conductive columns  606  formed from the conductive joinder of the conductive posts  608 ,  610 . 
         [0071]    Referring to  FIG. 12 , another alternative embodiment in accordance with the present invention is shown. The only difference here is that instead of a single layer substrate, a multilayer substrate may be used, such as the multilayer substrates described in U.S. Appln. No. 60/964,823, filed on Aug. 15, 2007, and entitled Interconnection Element with Posts Formed by Plating; U.S. Appln. No. 60/964,916 filed Aug. 15, 2007, and entitled Multilayer Substrate With Interconnection Vias and Method of Manufacturing the Same; and U.S. patent application Ser. No. 11/824,484, filed on Jun. 29, 2007, and entitled Multilayer Wiring Element Having Pin Interface, the disclosures of which are incorporated herein. As shown, the multilayer substrate  702  is joined in flip-chip manner with a microelectronic element  704 , e.g., a semiconductor chip having active devices, passive devices or both active or passive devices thereon. The tips  716  of the conductive posts  710 , which protrude from the top surface  701  of the multilayer substrate, are joined as described herein to conductive posts  710  extending from the microelectronic element. As shown, the conductive posts  708  of the multilayer substrate  702  can be joined directly to the conductive posts  710  extending from the front surface microelectronic element, such as through a diffusion bond formed between a finished metal at the tips  160  of the posts, e.g., gold, and another metal present in the conductive pads and the posts. Alternatively, the conductive posts  708 ,  710  posts can be joined together through a fusible metal such as a solder, tin or a eutectic composition, the fusible metal wetting the posts and the pads to form wetted or soldered joints. For example, the fusible metal can be provided in form of solder bumps (not shown), exposed at a front surface  722  of the microelectronic element  704 , the bumps being provided at the ends of either or both of the tips of the conductive posts. 
         [0072]    The conductive columns may also be utilized in stacked packaging, such as those packages described in commonly owned applications U.S. Appln. No. 60/963,209, filed Aug. 3, 2007, and entitled Die Stack Package Fabricated at the Wafer Level with Pad Extensions Applied To Reconstituted Wafer Elements; U.S. Appln. No. 60/964,069, filed Aug. 9, 2007, and entitled Wafer Level Stacked Packages with Individual Chip Selection; U.S. Appln. No. 60/962,200, filed Jul. 27, 2007, and entitled Reconstituted Wafer Stack Packaging with After-Applied Pad Extensions; and U.S. Appln. No. 60/936,617, filed Jun. 20, 2007, and entitled Reconstituted Wafer Level Stacking. 
         [0073]    For example, with reference to  FIG. 13 , in an alternative embodiment, a stacked package assembly includes a first subassembly  800  and a second subassembly  802 . The first and second subassemblies are virtually identical to the packaged microelectronic element shown in  FIG. 2 , except for the fact that the substrates  806 ,  806 ′ extend further out to accommodate conductive columns  808  extending between the substrates  806 ,  806 ′ of the first and second subassemblies. The conductive columns  808  also include a conductive post  812  extending from the substrate that connects to vias  814  extending through the top and bottom surfaces of the substrate on the second subassembly. As shown in  FIG. 13 , solder mask layer  818  can extend upwardly along and in contact with edge surface  813  of conductive post  812 . This arrangement keeps conductive columns  808  out of contact from substrate  806  in the area around post  812 , which as shown in previously-discussed Figures, such as  FIG. 2A , can have conductive elements, such as contact pad  117 , disposed thereon. Accordingly, the arrangement between solder mask layer  818  and conductive post  812  can further serve to keep conductive column  808  out of contact with a contact pad (or another conductive element such as a trace) that can be formed on substrate  806  and having post  812  affixed thereon. 
         [0074]    Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.