Abstract:
A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the semiconductor chip on the substrate inside the semiconductor package. A wire can be inside the semiconductor package, to connect the electrode pad to the semiconductor chip and a barrier member can be on the substrate fencing-in the semiconductor chip, where the electrode pad and the wire can be in an interior portion of the substrate. A sealing material can be in the interior portion of the substrate fenced-in by the barrier member, where the sealing material covering the semiconductor chip, the electrode pad, and the wire.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This application claims the benefit of State Intellectual Property Office (SIPO) of the People&#39;s Republic of China No. 201510295917.3, filed on Jun. 2, 2015, in State Intellectual Property Office (SIPO) of the People&#39;s Republic of China and Korean Patent Application No. 10-2016-0002767, filed on Jan. 8, 2016, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entireties by reference. 
       FIELD 
       [0002]    The inventive concept relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package capable of providing a structural stability and method of manufacturing the semiconductor package. 
       BACKGROUND 
       [0003]    A semiconductor package may include a sealing member that surrounds a semiconductor chip to protect the semiconductor chip from an external environment. Accordingly, dimensions and structural stability of the semiconductor package may be affected by the sealing member. 
       SUMMARY 
       [0004]    In some embodiments, a semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the semiconductor chip on the substrate inside the semiconductor package. A wire can be inside the semiconductor package, to connect the electrode pad to the semiconductor chip and a barrier member can be on the substrate fencing-in the semiconductor chip, where the electrode pad and the wire can be in an interior portion of the substrate. A sealing material can be in the interior portion of the substrate fenced-in by the barrier member, where the sealing material covering the semiconductor chip, the electrode pad, and the wire. 
         [0005]    In some embodiments, a semiconductor package can include a substrate, a first bonding member on the substrate, a second bonding member on the substrate and spaced apart from the first bonding member to surround the first bonding member, a semiconductor chip on the first bonding member, a barrier member on the second bonding member to surround the semiconductor chip, a groove defined by a space bounded by the first bonding member, the second bonding member, the barrier member, and the substrate, and a sealing member in the groove to seal the first bonding member and the semiconductor chip in the space. 
         [0006]    In some embodiments, a semiconductor package can include a substrate and a semiconductor chip on the substrate. An integral solder structure can be provided on the substrate to surround the semiconductor chip and a sealing member can be provided to seal the semiconductor chip in a space between the substrate and the integral solder structure. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0007]    Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
           [0008]      FIGS. 1A and 1B  are respectively a cross-sectional view and a plan view of a semiconductor package according embodiments; 
           [0009]      FIG. 2  is a cross-sectional view of a semiconductor package according to embodiments; 
           [0010]      FIG. 3A  is a cross-sectional view of a semiconductor package according to embodiments; 
           [0011]      FIG. 3B  is an enlarged cross-sectional view of a portion M of  FIG. 3A ; 
           [0012]      FIG. 4  is a cross-sectional view of a semiconductor package according to embodiments; 
           [0013]      FIGS. 5A to 5C  are respectively a cross-sectional view and plan views of semiconductor packages according to embodiments; 
           [0014]      FIGS. 6A to 6C  are cross-sectional views illustrating a method of manufacturing the semiconductor package illustrated in  FIGS. 1A and 1B ; 
           [0015]      FIGS. 7A to 7C  are cross-sectional views illustrating a method of manufacturing the semiconductor package illustrated in  FIGS. 3A and 3B ; 
           [0016]      FIGS. 8A and 8B  are cross-sectional views illustrating a method of manufacturing the semiconductor package illustrated in  FIG. 4 ; 
           [0017]      FIG. 9  is a perspective view of a smart card including a semiconductor package, according to embodiments; and 
           [0018]      FIG. 10  is a block diagram of a smart card including a semiconductor package, according to embodiments. 
       
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
       [0019]    Hereinafter, embodiments will be described with reference to the accompanying drawings. Like reference numerals denote like elements throughout the specification and drawings, and redundant descriptions thereof will be omitted. 
         [0020]    Embodiments may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those of ordinary skill in the art. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. 
         [0021]    In the accompanying drawings, the modifications of the illustrated shapes may be expected according to manufacturing technologies and/or tolerance. Therefore, the embodiments should not be construed as being limited to specific shapes of the illustrated regions. The shapes may be changed during the manufacturing processes. 
         [0022]    When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. 
         [0023]    The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the inventive concept. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that terms such as “comprise”, “include”, and “have”, when used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. 
         [0024]    Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
         [0025]    Also, though terms “first”, “second”, etc. are used to describe various members, components, regions, layers, and/or portions in various embodiments of the inventive concept, the members, components, regions, layers, and/or portions are not limited to these terms. These terms do not mean a specific order, an up-and-down order, or superiority and are used only to differentiate one member, component, region, layer, or portion from another one. Therefore, a first member, a first component, a first region, a first layer, or a first portion in an embodiment may refer to a second member, a second component, a second region, a second layer, or a second portion in another embodiment. For example, a first element may be referred to as a second element without departing from the scope of the inventive concept. Similarly, a second element may be referred to as a first element. 
         [0026]    Since various elements and regions in the drawings are schematically illustrated, the inventive concept is not limited to a relative size or spacing illustrated in the accompanying drawings. 
         [0027]      FIGS. 1A and 1B  are respectively a cross-sectional view and a plan view of a semiconductor package  10  according embodiments. 
         [0028]    Referring to  FIGS. 1A and 1B , the semiconductor package  10  may include a substrate  100 , first and second bonding members  101   a  and  101   b  and an electrode pad  105  on the substrate  100 , a semiconductor chip  102  on the first bonding member  101   a,  a barrier member  104  on the second bonding member  101   b,  a lead wire W that connects the semiconductor chip  102  to the electrode pad  105 , and a sealing member  103  in a space laterally defined on the substrate  100  by opposite portions of the barrier member  104 . 
         [0029]    Specifically, the substrate  100  may include a first surface  100 S 1  and a second surface  100 S 2  opposite to the first surface  100 S 1 . The substrate  100  may be a printed circuit board (PCB). Although not illustrated, external connection terminals may be on the first surface  100 S 1  of the substrate  100 . The semiconductor chip  102  may be on the second surface  100 S 2  of the substrate  100 . 
         [0030]    The first and second bonding members  101   a  and  101   b  having a certain thickness may be on the second surface  100 S 2  of the substrate  100 . The second bonding member  101   b  may include a first surface  101   b S 1  facing the substrate  100 , and a second surface  101   b S 2  opposite to the first surface  101   b S 1 . The second surface  101   b S 2  of the second bonding member  101   b  may be planar, but is not limited thereto. The second surface  101   b S 2  of the second bonding member  101   b  may have a concave-convex shape. Alternatively, the second surface  101   b S 2  of the second bonding member  101   b  may have a concave shape so as to accommodate the barrier member  104  entirely or partially. 
         [0031]    The second bonding member  101   b  may be disposed on the substrate  100  to surround (or fence-in) the first bonding member  101   a.  Accordingly, the second bonding member  101   b  may have a ring shape, but is not limited thereto. 
         [0032]    The first bonding member  101   a  and the second bonding member  101   b  may be spaced apart from each other in at least a partial region. Accordingly, a groove G may be provided along a space defined between first and second bonding members  101   a  and  101   b  spaced apart from each other. The top surface (i.e., the second surface  100 S 2 ) of the substrate  100  may be partially exposed in the groove G. 
         [0033]    The electrode pad  105  may be on the top surface (i.e., the second surface  100 S 2 ) of the substrate  100  that is exposed in the groove G. The electrode pad  105  may be electrically connected to the semiconductor chip  102  through the lead wire W. In this case, a depth of the groove G may be greater than a thickness of the electrode pad  105 . Therefore, the lead wire W may pass the groove G and be connected to the electrode pad  105 . The sealing member  103  may fill the groove G and seal the electrode pad  105  and the lead wire W. 
         [0034]    The electrode pad  105  may be electrically connected to the external connection terminal on the first surface  100 S 1  of the substrate  100 . In  FIG. 9 , an external connection terminal EP is illustrated as being on a first surface of a substrate SUB. The semiconductor chip  102  and the electrode pad  105  are disposed on a second surface opposite to the first surface of the substrate SUB on which the external connection terminal EP is disposed. 
         [0035]    A plurality of electrode pads  105  may be within the groove G, and at least some of the plurality of electrode pads  105  may be electrically connected to the semiconductor chip  102 . 
         [0036]    The semiconductor chip  102  may be on the first bonding member  101   a.  The semiconductor chip  102  may be fixed to the first bonding member  101   a  by an adhesive layer A 1  including a glue. 
         [0037]    In some embodiments, the first bonding member  101   a  may be omitted. That is, the semiconductor chip  102  may be directly fixed to the substrate  100  by the adhesive layer A 1 . In this case, the adhesive layer A 1  may serve as the first bonding member  101   a.  In other embodiments, the adhesive layer A 1  may be omitted. In this case, the first bonding member  101   a  may include a glue and directly fix the semiconductor chip  102  to the substrate  100 . 
         [0038]    The barrier member  104  may be on the second bonding member  101   b.  The barrier member  104  may be fixed to the second bonding member  101   b  by an adhesive layer A 2  including a glue. 
         [0039]    In some embodiments, the second bonding member  101   b  may be omitted. In this case, the barrier member  104  may be directly fixed to the substrate  100  by the adhesive layer A 2 . In other embodiments, the adhesive layer A 2  may be omitted. In this case, the second bonding member  101   b  may include a glue and directly fix the barrier member  104  to the substrate  100 . 
         [0040]    The barrier member  104  may have various shapes so as to surround the semiconductor chip  102 . For example, referring to  FIG. 1B , the barrier member  104  may have a ring shape. When the barrier member  104  has a ring shape, the semiconductor chip  102  may be in a central portion of the ring-shaped barrier member  104 . 
         [0041]    In addition, the second bonding member  101   b  may have a shape matching the barrier member  104 . In some embodiments, the second bonding member  101   b  may have a ring shape corresponding to the barrier member  104 , so that the barrier member  104  is stacked on the second bonding member  101   b.  However, the second bonding member  101   b  is not limited thereto. The second bonding member  101   b  may have various shapes so that the barrier member  104  is on the second bonding member  101   b.    
         [0042]    The barrier member  104  may be disposed like a ring-shaped dam to fence-in the chip  102 . The barrier member  104  may accommodate the sealing member  103  in the space laterally defined by opposing portions of the barrier member  104 . 
         [0043]    In order to adjust a volume of the semiconductor package  10 , a height of the barrier member  104  may be appropriately adjusted according to process requirements. However, even in this case, the height of the barrier member  104  may be appropriately determined so that the sealing member  103  seals the semiconductor chip  102 , the electrode pad  105 , and the lead wire W. Therefore, a level of the top surface of the barrier member  104  on the second bonding member  101   b  may be determined to be higher than a maximum level of the lead wire W. 
         [0044]    As described above, the sealing member  103  may be in the space defined by the second bonding member  101   b  and the barrier member  104 . The sealing member  103  may seal the semiconductor chip  102 , the electrode pad  105 , the first bonding member  101   a,  and the lead wire W in the space laterally defined by the second bonding member  101   b  and the barrier member  104 . In some embodiments, the sealing member  103  may include a glue to seal the semiconductor chip  102 , the first bonding member  101   a,  and the lead wire W in the space defined by the second bonding member  101   b  and the barrier member  104 . In this case, the sealing member  103  may be formed by a dotting process. 
         [0045]    In some embodiments, the barrier member  104  may include a plurality of separate barrier elements. Ends of the plurality of separate barrier elements may be connected to one another to constitute the barrier member  104  (having a continuous shape) in a lateral direction, for example, a ring shape. 
         [0046]    The barrier member  104  may be formed by connecting the plurality of separate barrier elements to one another through an adhesive layer including a glue. In this case, boundaries may appear between the plurality of separate barrier elements. 
         [0047]    On the other hand, the barrier member  104  may be formed by integrally connecting the plurality of separate barrier elements to one another through a solder print process and a reflow process. In the barrier member  104  formed through the solder print process and the reflow process, no boundaries may appear between the plurality of barrier members. The barrier member  104  may have an integrated (or continuous) shape as illustrated in  FIGS. 1A and 1B . The barrier member  104  including the plurality of separate barrier elements may provide a space for accommodating the sealing member  103 . 
         [0048]    The plurality of separate barrier elements may be a plurality of separate ring-shaped structures. The barrier member  104  may be formed by stacking the plurality of separate ring-shaped structures. (See  FIG. 4 ) In addition, the plurality of separate barrier elements may be a plurality of separate non-ring-shaped structures. The barrier member  104  may be formed by connecting sides of the plurality of separate non-ring-shaped structures to one another. (See  FIG. 5 ) 
         [0049]    The barrier member  104  may be a pre-manufactured ring-shaped structure. In some embodiments, the barrier member  104  may include at least one selected from a ceramic, plastic, a metal, and a solder. Since the ceramic, the plastic, the metal, and the solder have excellent mechanical strengths, the barrier member  104  including at least one selected from the ceramic, the plastic, the metal, and the solder may protect the electrode pad  105 , the semiconductor chip  102 , the lead wire W, and the sealing member  103  from being damaged by external impact. 
         [0050]    A cross-section of the barrier member  104  is illustrated as having a rectangular shape, but is not limited thereto. The cross-section of the barrier member  104  may have various shapes. For example, the cross-section of the barrier member  104  may have a rectangular shape or a bullet shape. 
         [0051]      FIG. 2  is a cross-sectional view of a semiconductor package  20  according to embodiments. The semiconductor package  20  of  FIG. 2  is similar to the semiconductor package  10  of  FIGS. 1A and 1B , except for a cross-sectional shape of a barrier member  204 . 
         [0052]    Referring to  FIG. 2 , the cross-section of the barrier member  204  may have various shapes. The cross-section of the barrier member  104  of  FIG. 1A  has a rectangular shape, but the cross-section of the barrier member  204  of  FIG. 2  may have a bullet shape. That is, the cross-section of the barrier member  204  may have a dome shape (at an end remote from the substrate  100 ) that has a uniform thickness in a lower portion thereof and becomes gradually narrower (i.e., tapers) toward an upper portion thereof 
         [0053]    The barrier member  204  having the bullet-shaped cross-section may be a pre-manufactured separate ring-shaped structure. The pre-manufactured separate ring-shaped structure may include at least one selected from a ceramic, plastic, and a metal. 
         [0054]    A sealing member  203  may be disposed in a space laterally defined by a second bonding member  101   b  and the barrier member  204 . Like the sealing member  103  of  FIG. 1A , the sealing member  203  may seal a semiconductor chip  102 , an electrode pad  105 , a first bonding member  101   a,  and a lead wire W. 
         [0055]      FIGS. 3A and 3B  are cross-sectional views of a semiconductor package  30  according embodiments. The semiconductor package  30  of  FIGS. 3A and 3B  is similar to the semiconductor package  10  of  FIGS. 1A and 1B , except for a material and a shape of a barrier member  304  and a connection member that connects the barrier member  304  to a second bonding member  301   b.  The barrier member  304  may be a solder, and the barrier member  304  may be connected to the second bonding member  301   b  by a metal pattern layer  306 .  FIG. 3B  is an enlarged cross-sectional view of a portion M of  FIG. 3A . 
         [0056]    Referring to  FIG. 3A , the semiconductor package  30  may include a substrate  100 , first and second bonding members  101   a  and  301   b  and an electrode pad  105  on the substrate  100 , a semiconductor chip  102  on the first bonding member  101   a,  the barrier member  304  on the second bonding members  301   b,  a lead wire W that connects the semiconductor chip  102  to the electrode pad  105 , and a sealing member  303  in a space laterally defined by the barrier member  304 . 
         [0057]    The second bonding member  301   b  may surround the first bonding member  101   a.  A groove G may be formed along a space defined by the first and second bonding members  101   a  and  301   b  spaced apart from each other. The electrode pad  105  may be on a top surface of the substrate  100  that is exposed through the groove G. 
         [0058]    The barrier member  304  may include a solder material such as a tin solder. The barrier member  304  may be formed through a reflow process after a solder print process. A cross-section of the barrier member  304  may be deformed to have a bullet shape by the reflow process, but is not limited thereto. 
         [0059]    In some embodiments, the barrier member  304  may be formed by integrally connecting a plurality of elements to one another. For example, the barrier member  304  may be formed in such a manner that a plurality of solders formed using a plurality of elements by a solder print process are made to have an integrated shape by a reflow process. The elements can be separate elements. 
         [0060]    The second bonding member  301   b  may include a first surface  301   b S 1  facing the substrate  100 , and a second surface  301   b S 2  opposite to the first surface  301   b S 1  and facing the barrier member  304 . In this case, in order to fix the barrier member  304  to the second bonding member  301   b,  the metal pattern layer  306  may be on the second surface  301   b S 2  of the second bonding member  301   b.    
         [0061]    The metal pattern layer  306  may include copper, but is not limited thereto. The metal pattern layer  306  may include any metal and/or an alloy formed by bonding the second bonding member  301   b  and the barrier member  304 . 
         [0062]    The second surface  301   b S 2  of the second bonding member  301   b,  on which the metal pattern layer  306  is formed, may have a planar shape, but is not limited thereto. The second surface  301   b S 2  of the second bonding member  301   b  may have a concave-convex shape. For example, a region overlapping the metal pattern layer  306  on the second surface  301   b S 2  of the second bonding member  301   b  may have a concave shape to accommodate the metal pattern layer  306  entirely or partially. 
         [0063]    The second bonding member  301   b  may include a glue and be fixed on the substrate  100 , but is not limited thereto. In some embodiments, the second bonding member  301   b  may be omitted. In this case, the metal pattern layer  306  may be directly fixed to the substrate  100  by an adhesive layer including a glue. In this case, the adhesive layer may serve as the second bonding member  301   b.    
         [0064]    In order to fix the barrier member  304  to the second bonding member  301   b,  the metal pattern layer  306  is used in the embodiment of  FIG. 3 , but is not limited thereto. The barrier member  304  may be fixed to the second bonding member  301   b  by an adhesive layer including a glue. 
         [0065]      FIG. 4  is a cross-sectional view of a semiconductor package  40  according to embodiments. The semiconductor package  40  of  FIG. 4  is similar to the semiconductor package  10  of  FIGS. 1A and 1B , except that a barrier member  404  includes a plurality of stacked barrier elements, such as first and second ring-shaped structures  404   a  and  404   b.    
         [0066]    Referring to  FIG. 4 , the barrier member  404  may include the plurality of stacked barrier elements. The plurality of stacked barrier elements may be the first and second ring-shaped structures  404   a  and  404   b.  In this case, the barrier member  404  may be formed by stacking the first and second ring-shaped structures  404   a  and  404   b.    
         [0067]    In this case, the first and second ring-shaped structures  404   a  and  404   b  may be connected to each other by an adhesive layer including a glue. The barrier member  404  formed using the plurality of stacked barrier elements may provide a space for accommodating a sealing member  403 . 
         [0068]    The barrier member  404  is illustrated in  FIG. 4  as being formed by stacking two ring-shaped structures, i.e., the first and second ring-shaped structures  404   a  and  404   b,  but is not limited thereto. In some embodiments, the barrier member  404  may be formed by stacking three or more ring-shaped structures. The stacked barrier members may be different sizes and may not be vertically designed. 
         [0069]      FIGS. 5A to 5C  are respectively a cross-sectional view and plan views of semiconductor packages  50 ,  50 A, and  50 B according to embodiments. The semiconductor packages  50 ,  50 A, and  50 B of  FIGS. 5A to 5C  are similar to the semiconductor package  10  of  FIGS. 1A and 1B , except that barrier members  504   a  and  504   b,    504   a ′ and  504   b ′, and  504   a ″ and  504   b ″ are formed using a plurality of separate barrier elements, such as arc-shaped structures. The barrier members  504   a  and  504   b,    504   a ′ and  504   b ′, and  504   a ″ and  504   b ″ respectively included in the semiconductor packages  50 ,  50 A, and  50 B of  FIGS. 5A to 5C  may be a combination of the barrier member  104  illustrated in  FIGS. 1A and 1B  and of the barrier member  304  illustrated in  FIGS. 3A and 3B . 
         [0070]    Referring to  FIG. 5A , the barrier members  504   a  and  504   b  may include a plurality of separate barrier elements, i.e., a first barrier element  504   a  and a second barrier element  504   b . Ends of the first and second barrier elements  504   a  and  504   b  may be connected to each other to form a shape isolated in a lateral direction. In this case, the first and second barrier elements  504   a  and  504   b  may be connected to each other by an adhesive layer including a glue, or may be integrally connected to each other through a reflow process. 
         [0071]    Cross-sections of the first and second barrier elements  504   a  and  504   b  may have different shapes. For example, the cross-section of the first barrier element  504   a  may have a rectangular shape and the cross-section of the second barrier element  504   b  may have a bullet shape. 
         [0072]    In addition, the first barrier element  504   a  and the second barrier element  504   b  may be formed using different materials. For example, the first and second barrier elements  504   a  and  504   b  may include at least one material selected from a ceramic, plastic, a metal, and an alloy. In this case, the material selected for the first barrier element  504   a  may be different from the material selected for the second barrier element  504   b.    
         [0073]    Furthermore, the first barrier element  504   a  and the second barrier element  504   b  may be formed by different manufacturing methods. For example, the first barrier element  504   a  may be a pre-manufactured independent dam-shaped structure. In this case, the first barrier element  504   a  may be fixed to a second bonding member  501   b   1 , corresponding to the first barrier element  504   a,  by an adhesive layer A 3 . 
         [0074]    On the other hand, the second barrier element  504   b  may be a solder formed by a solder print process and a reflow process. For example, the second barrier element  504   b  may be a tin solder. In this case, the second barrier element  504   b  may be fixed to the second bonding member  501   b   2 , corresponding to the second barrier element  504   b,  by a metal pattern layer  506 . In some embodiments, the second barrier element  504   b  may be fixed to the second bonding member  501   b   2  by an adhesive layer including a glue. 
         [0075]    The metal pattern layer  506  may include an alloy formed by bonding the second barrier element  504   b  and the second bonding member  501   b   2  and/or other metals. 
         [0076]    Top surfaces of the second bonding members  501   b   1  and  501   b   2  may have a planar shape, but are not limited thereto. The top surfaces of the second bonding members  501   b   1  and  501   b   2  may have a concave-convex shape. In particular, the top surface of the second bonding member  501   b   1  overlapping the first barrier element  504   a  may have a planar shape, and the top surface of the second bonding member  501   b   2  overlapping the second barrier element  504   b  may have a concave shape to accommodate the metal pattern layer  506  entirely or partially. 
         [0077]    An end of the first barrier element  504   a  and an end of the second barrier element  504   b  may be connected to each other to form a space isolated in a lateral direction. That is, the first and second barrier elements  504   a  and  504   b  may provide a space for accommodating the sealing member  503 . 
         [0078]    The first and second barrier elements  504   a  and  504   b  may be arc-shaped structures. That is, ends of the arc-shaped structures constituting the first and second barrier elements  504   a  and  504   b  may be connected to each other to form a ring-shaped structure. 
         [0079]    For example, the barrier members  504   a  and  504   b,    504   a ′ and  504   b ′, and  504   a ″ and  5041   b ″ respectively illustrated in  FIGS. 5A to 5C  may be a combination of pre-manufactured independent dam-shaped structures and solder structures. 
         [0080]    The first and second arc-shaped structures  504   a ′ and  504   b ′ of  FIG. 5B  may correspond to the first and second barrier elements  504   a  and  504   b  of  FIG. 5A , respectively. Each of the first and second arc-shaped structures  504   a ′ and  504   b ′ may have a semicircular shape, but is not limited thereto. The first and second arc-shaped structures  504   a ′ and  504   b ′, which have different cross-sectional shapes and/or include different materials, may occupy different areas. That is, a perimeter ratio of the first arc-shaped structure  504   a ′ to the second arc-shaped structure  504   b ′ may be variously designed according to process requirements. 
         [0081]    Specific regions occupied by second bonding members  501   b   1 ′ and  501   b   2 ′ and a metal pattern layer  506  may vary according to specific dimensions of the first and second arc-shaped structures  504   a ′ and  504   b′.    
         [0082]    Ends of the first and second arc-shaped structures  504   a ′ and  504   b ′ may be connected to each other to form a unitary ring-shaped structure. A sealing member  503  may be accommodated in a space laterally defined by the ring-shaped structure. 
         [0083]    The plurality of first and second arc-shaped structures  504   a ″ and  504   b ″ of  FIG. 5C  may correspond to the first and second barrier elements  504   a  and  504   b  of  FIG. 5A , respectively. A length of the plurality of first arc-shaped structures  504   a ″ may be greater than a length of the plurality of second arc-shaped structures  504   b″.    
         [0084]    Ends of the plurality of first and second arc-shaped structures  504   a ″ and  504   b ″ may be connected to each another to form a ring-shaped structure. A sealing member  503  may be accommodated in a space laterally defined by the ring-shaped structure. 
         [0085]    The first and second arc-shaped structures  504   a ″ and  500   b ″ are illustrated in  FIG. 5C  as each including two or more arc-shaped structures and being alternately arranged and connected to one another, but are not limited thereto. 
         [0086]    According to a configuration of a conventional semiconductor package as appreciated by the present inventor, a semiconductor chip, an electrode pad, and a lead wire on a substrate may be sealed by a sealing member. A sealing process may be performed by using a dotting process, but it may be difficult to control a shape and a dimension of the semiconductor package or to ensure a structural stability of the semiconductor package. In addition, when the sealing process is performed by molding, the electrode pad, the lead wire, or the like may be delaminated from the substrate due to a low binding force between a filling material and the substrate, thus degrading the reliability of the semiconductor package. 
         [0087]    In contrast, the semiconductor packages  10 ,  20 ,  30 ,  40 ,  50 ,  50 A, and  50 B according to the present embodiments herein, may provide the space for accommodating the sealing member that seals the semiconductor chip, the electrode pad, and the lead wire by arranging the barrier member that surrounds the semiconductor chip, the electrode pad, and the lead wire. Therefore, the accuracy of the dimensions of the semiconductor package may be ensured and the sealing member may be protected by the barrier member, thus effectively improving the mechanical strength of the semiconductor package. In addition, the use of the glue as the material of the sealing member may make it possible to suppress the delamination of the electrode pad, the lead wire, or the like while controlling the shape and the dimensions of the semiconductor package, thus ensuring the driving reliability of the semiconductor package. 
         [0088]      FIGS. 6A to 6C  are cross-sectional views for describing a method of manufacturing the semiconductor package  10  illustrated in  FIGS. 1A and 1B . A method of manufacturing the semiconductor package  20  illustrated in  FIG. 2  is described with reference to  FIGS. 6A to 6C . 
         [0089]    Referring to  FIG. 6A , a semiconductor chip  102  may be disposed on a substrate  100 . In this case, after a first bonding member  101   a  is disposed on the substrate  100 , the semiconductor chip  102  may be disposed on the first bonding member  101   a.  An adhesive layer A 1  may be disposed on the first bonding member  101   a  so as to fix the semiconductor chip  102  to the first bonding member  101   a,  but the present embodiment is not limited thereto. That is, various bonding methods may be used for fixing the semiconductor chip  102  to the substrate  100 . In some embodiments, the first bonding member  101   a  may be omitted, and the semiconductor chip  102  may be directly fixed to the substrate  100  by the adhesive layer A 1 . Alternatively, the first bonding member  101   a  may be a glue in itself. In this case, the adhesive layer A 1  may be omitted, and the semiconductor chip  102  may be directly fixed to the substrate  100  via the first bonding member  101   a.    
         [0090]    A second bonding member  101   b  may be spaced apart from the first bonding member  101   a  in at least a partial region of the substrate  100  while surrounding the first bonding member  101   a.  Accordingly, a groove G may be formed along a lateral space defined between the first bonding member  101   a  and the second bonding member  101   b  spaced apart from each other. An electrode pad  105  may be formed on the substrate  100 , and the electrode pad  105  may be exposed through the groove G. The electrode pad  105  may be electrically connected to an external connection terminal of the semiconductor package  10 . The elements described above may be formed in any order. 
         [0091]    Referring to  FIG. 6B , a barrier member  104  may be formed on the second bonding member  101   b.  In this case, an adhesive layer A 2  may be formed on the second bonding member  101   b  to fix the barrier member  104  to the second bonding member  101   b.  The adhesive layer A 2  may be disposed or coated on the second bonding member  101   b,  and the barrier member  104  may be disposed on the adhesive layer A 2 . 
         [0092]    A curing process may be performed to fix the barrier member  104  to the second bonding member  101   b.  However, the present embodiment is not limited thereto. Various bonding methods may be used for fixing the barrier member  104  to the substrate  100 . In some embodiments, the second bonding member  101   b  may be omitted, and the barrier member  104  may be directly fixed to the substrate  100  by the adhesive layer A 2 . Alternatively, the second bonding member  101   b  may be a glue in itself. In this case, the adhesive layer A 2  may be omitted, and the barrier member  104  may be directly fixed to the substrate  100  via the second bonding member  101   b.    
         [0093]    The barrier member  104  may be a pre-manufactured independent structure that surrounds the semiconductor chip  102 . For example, the barrier member  104  may be a pre-manufactured independent ring-shaped structure. When the barrier member  104  has a ring shape, the semiconductor chip  102  may be disposed in a central portion of the ring-shaped barrier member  104 . In addition, the second bonding member  101   b  may have a shape matching the barrier member  104 . For example, when the barrier member  104  has a ring shape, the second bonding member  101   b  may be formed to have a ring shape so that the barrier member  104  is formed on the second bonding member  101   b.    
         [0094]    The semiconductor chip  102  may be connected to the electrode pad  105  through a wire bonding process. The semiconductor chip  102  may be electrically connected to the electrode pad  105  through a lead wire W. A plurality of electrode pads  105  may be formed on the substrate  100 . At least some of the plurality of electrode pads  105  may be electrically connected to the semiconductor chip  102  through a plurality of lead wires W. 
         [0095]    A sealing member  103  may be formed in a space laterally defined by the substrate  100 , the second bonding member  101   b,  and the barrier member  104  to seal the semiconductor chip  102 , the electrode pad  105 , the first bonding member  101   a,  and the lead wire W. Since the sealing member  103  is supported by the groove G and the barrier member  104 , the dimensions of the semiconductor package  10  may be controlled and the semiconductor package  10  may be strengthened against external impact. In addition, since the sealing member  103  is stably fixed, it is possible to suppress delamination between the electrode pad  105  and the substrate  100  and between the electrode pad  105  and the lead wire W. 
         [0096]    In some embodiments, the sealing member  103  may be a glue. In this case, the sealing member  103  may be formed in such a manner that a glue is formed through a dotting process in the space laterally defined by the second bonding member  101   b  and the barrier member  104 . In other embodiments, the sealing member  103  may be a general molding material. In this case, the sealing member  103  may be formed in such a manner that a molding material is formed through a molding process in the space laterally defined by the second bonding member  101   b  and the barrier member  104 . In this manner, the semiconductor package  10  of  FIGS. 1A and 1B  may be manufactured. 
         [0097]    The method of manufacturing the semiconductor package  20  illustrated in  FIG. 2  may be similar to the method of  FIGS. 6A to 6C , except for a shape of a barrier member  204  on the second bonding member  101   b.  The barrier member  204  may be a pre-manufactured independent ring-shaped structure. The ring-shaped structure may be manufactured to have a bullet-shaped cross-section rather than a rectangular cross-section. 
         [0098]    The barrier member  204  of the pre-manufactured independent ring-shaped structure may be disposed on the second bonding member  101   b,  and the sealing member  203  may be formed in the space laterally defined by the substrate  100 , the second bonding member  101   b , and the barrier member  204 . In this manner, the semiconductor package  20  of  FIG. 2  may be manufactured. 
         [0099]      FIGS. 7A to 7C  are cross-sectional views for describing a method of manufacturing the semiconductor package  30  illustrated in  FIGS. 3A and 3B . Methods of manufacturing the semiconductor packages  50 ,  50 A, and  50 B illustrated in  FIGS. 5A to 5C  are described with reference to  FIGS. 6A to 8C . 
         [0100]    Referring to  FIG. 7A , a semiconductor chip  102  and a metal pattern layer  306  may be disposed on a substrate  100 . 
         [0101]    Specifically, a first bonding member  101   a  may be disposed on the substrate  100 , and the semiconductor chip  102  may be disposed on the first bonding member  101   a.  An adhesive layer A 1  may be disposed on the first bonding member  101   a  to fix the semiconductor chip  102  to the first bonding member  101   a,  but the present embodiment is not limited thereto. That is, various bonding methods may be used for fixing the semiconductor chip  102  to the substrate  100 . In some embodiments, the first bonding member  101   a  may be omitted, and the semiconductor chip  102  may be directly fixed to the substrate  100  by an adhesive layer A 1 . Alternatively, the first bonding member  101   a  may be a glue in itself. In this case, the adhesive layer A 1  may be omitted, and the semiconductor chip  102  may be directly fixed to the substrate  100  via the first bonding member  101   a.    
         [0102]    A second bonding member  301   b  may be disposed on the substrate  100 , and a metal pattern layer  306  may be disposed on the second bonding member  301   b.  A top surface of the second bonding member  301   b,  on which the metal pattern layer  306  is disposed, may have a planar shape, but is not limited thereto. The top surface of the second bonding member  301   b , on which the metal pattern layer  306  is disposed, may have a concave-convex shape. Specifically, the top surface of the second bonding member  301   b  may have a concave shape to accommodate the metal pattern layer  306  entirely or partially. The metal pattern layer  306  may include a metal, for example, copper that is capable of fixing a plurality of solders to the second bonding member  301   b.    
         [0103]    As described above, the second bonding member  301   b  may be spaced apart from the first bonding member  101   a  on the substrate  100  while surrounding the first bonding member  101   a.  Accordingly, a groove G may be formed in the substrate  100  along a space laterally defined by the first bonding member  101   a  and the second bonding member  301   b  spaced apart from each other. An electrode pad  105  may be formed on the substrate  100 , and the electrode pad  105  may be exposed via the groove G. The electrode pad  105  may be electrically connected to an external connection terminal of the semiconductor package  10 . 
         [0104]    Referring to  FIG. 7B , a barrier member  304  may be disposed on the second bonding member  301   b.  The barrier member  304  may be disposed on the second bonding member  301   b  to cover the metal pattern layer  306  on the second bonding member  301   b.  In this case, the barrier member  304  may be formed through a solder print process. That is, the barrier member  304  may include a solder. In some embodiments, the solder may be a metal or an alloy. 
         [0105]    The barrier member  304  including the solder may be more tightly bonded through a reflow process. 
         [0106]    Referring to  FIG. 7C , a sealing member  303  may be formed in a space laterally defined by the substrate  100 , the second bonding member  301   b,  and the barrier member  304 . The sealing member  303  may be formed through a dotting process or a molding process to seal the first bonding member  101   a,  the electrode pad  105 , the semiconductor chip  102 , and the lead wire W. In this manner, the semiconductor package  30  of  FIG. 3  may be manufactured. 
         [0107]      FIGS. 8A and 8B  are cross-sectional views for describing a method of manufacturing the semiconductor package  40  illustrated in  FIG. 4 . As described with reference to  FIG. 7A , first and second bonding members  101   a  and  101   b  may be formed on a substrate  100 . A semiconductor chip  102  may be fixed to the first bonding member  101   a  by an adhesive layer A 1 . An adhesive layer A 2  may be formed on the second bonding member  101   b.  Subsequent processes will be described with reference to  FIGS. 8A and 8B . 
         [0108]    Referring to  FIG. 8A , a first barrier element  404   a  may be disposed on the adhesive layer A 2  formed on the second bonding member  101   b.  The first barrier element  404   a  may have a ring-shaped structure. In this case, the ring-shaped structure may be a pre-manufactured independent ring-shaped structure. That is, the first barrier element  404   a  may be formed by fixing the pre-manufactured independent ring-shaped structure to the second bonding member  101   b.  However, the present embodiment is not limited thereto. The first barrier element  404   a  may be directly formed on the second bonding member  101   b.    
         [0109]    Referring to  FIG. 8B , a second barrier element  404   b,  which is a ring-shaped structure, may be laminated on the first barrier element  404   a.  In this case, the ring-shaped structure may be a pre-manufactured independent ring-shaped structure. That is, the second barrier element  404   b  may be formed by fixing the pre-manufactured independent ring-shaped structure to the first barrier element  404   a  to vertically stack thereon. However, the present embodiment is not limited thereto. The second barrier element  404   b  may be directly formed on the first barrier element  404   a.    
         [0110]    An adhesive layer may be further formed between the first barrier element  404   a  and the second barrier element  404   b  to connect the second barrier element  404   b  to the first barrier element  404   a.    
         [0111]    Before or after the first and second barrier elements  404   a  and  404   b  are formed, a wire bonding process may be performed to connect the semiconductor chip  102  to an electrode pad  105 . 
         [0112]    A sealing member  403  may be formed in a space laterally defined by the substrate  100 , the second bonding member  101   b,  and the first and second barrier elements  404   a  and  404   b.  The sealing member  403  may be formed through a dotting process or a molding process. In this manner, the semiconductor package  40  of  FIG. 4  may be manufactured. 
         [0113]    The methods of manufacturing the semiconductor packages  50 ,  50 A, and  50 B illustrated in  FIGS. 5A to 5C  will be described with reference to  FIGS. 7A to 8C . 
         [0114]    As described with reference to  FIG. 7A , first and second bonding members  101   a  and  301   b  may be formed on a substrate  100 . A semiconductor chip  102  may be fixed to the first bonding member  101   a  by an adhesive layer A 1 . An adhesive layer A 2  may be formed on the second bonding member  101   b.    
         [0115]    Referring to  FIGS. 5A and 7A , an adhesive layer A 3  may be formed on the second bonding member  501   b   1  corresponding to the first barrier member  504   a,  and a metal pattern layer  506  may be formed on the second bonding member  501   b   2  corresponding to the second barrier member  504   b.    
         [0116]    In this case, the top surface of the second bonding member  501   b   1  corresponding to the first barrier member  504   a  may have a planar shape. In addition, the top surface of the second bonding member  501   b   2  corresponding to the second barrier member  504   b  may have a ring shape so as to accommodate the metal pattern layer  506  entirely or partially. 
         [0117]    The first barrier member  504   a  may be a pre-manufactured independent ring-shaped structure. In this case, the first barrier member  504   a  may be an arc-shaped structure that surrounds the semiconductor chip  102 . 
         [0118]    The second barrier member  504   b  may be a solder formed by a solder print process and a reflow process. In this case, the second barrier member  504   b  may be an arc-shaped structure that surrounds the semiconductor chip  102 . An end of the first barrier member  504   a  and an end of the second barrier member  504   b  may be connected to each other to form a space isolated in a lateral direction. 
         [0119]    A sealing member  503  may be formed in a space laterally defined by the substrate  100 , the second bonding members  501   b   1  and  501   b   2 , and the first and second barrier members  504   a  and  504   b.  In this manner, the semiconductor package  50  of  FIG. 5A  may be manufactured. 
         [0120]    In the semiconductor packages  50 A and  50  illustrated in  FIGS. 5B and 5C , lengths of the first and second barrier members  504   a ′ and  504   b ′ may be different from lengths of the first and second barrier members  504   a ″ and  504   b ″. The adhesive layer A 3  or the metal pattern layer  506  may be formed corresponding to the lengths of the first and second barrier members  504   a ′ and  504   b ′ and the first and second barrier members  504   a ″ and  504   b ″ on the second bonding members  501   b   1  and  501   b   2 . 
         [0121]    The first and second barrier members  504   a ′ and  504   b ′ and the first and second barrier members  504   a ″ and  504   b ″ may be respectively formed on the adhesive layer A 3  or the metal pattern layer  506 . A sealing member  503  may be formed in a space laterally defined by the second bonding members  501   b   1  and  501   b   2  and the first and second barrier members  504   a ′ and  504   b ′ or the first and second barrier members  504   a ″ and  504   b ″. In this manner, the semiconductor packages  50 A and  50 B of  FIGS. 5B and 5C  may be manufactured. 
         [0122]      FIG. 9  is a perspective view of a smart card  1000  according to embodiments. 
         [0123]    Referring to  FIG. 9 , the smart card  1000  may include a semiconductor package  1  and a base substrate  2  on which the semiconductor package  1  is to be mounted. 
         [0124]    The semiconductor package  1  may be one of the semiconductor packages  10 ,  20 ,  30 ,  40 ,  50 ,  50 A, and  50 B respectively. A substrate SUB of the semiconductor package  1  may be one of the substrates  100  included in the semiconductor packages  10 ,  20 ,  30 ,  40 ,  50 ,  50 A, and  50 B. 
         [0125]    Referring to  FIGS. 1A to 5C and 9 , the semiconductor chip  102  may be mounted on the first surface  100 S 1  of the substrate  100 , and an external connection terminal EP may be formed on the second surface  100 S 2  opposite to the first surface  100 S 1  of the substrate  100 . In  FIG. 9 , a first surface of the substrate SUB, on which the semiconductor chip is mounted, is directed downward. The external connection terminal EP is disposed on the second surface opposite to the first surface of the substrate SUB. The external connection terminal EP may be a conductive pattern. 
         [0126]    The base substrate  2  may include a groove EG corresponding to the semiconductor package  1  to accommodate the semiconductor package  1 . The semiconductor package  1  may be mounted within the groove EG of the base substrate  2 . In the process of mounting the semiconductor package  1 , the surface of the semiconductor package  1 , on which the semiconductor chip, the barrier member, and the sealing member are mounted, faces the groove EG of the base substrate  2 . Accordingly, the surface of the semiconductor package  1 , on which the external connection terminal EP is formed, may be exposed to the outside. 
         [0127]      FIG. 10  is a perspective view of a smart card  2000  according to embodiments. 
         [0128]    Referring to  FIG. 10 , a controller  2010  and a memory  2020  may be configured to exchange electrical signals with each other. For example, the controller  2010  and the memory  2020  may be configured to exchange data with each other according to a command of the controller  2010 . The smart card  2000  may communicate with an external device in a non-contact or contact manner and store data in the memory  2020  or output data from the memory  2020  to the external device. For example, the memory  2020  may include at least one selected from among the semiconductor packages  10 ,  20 ,  30 ,  40 ,  50 ,  50 A, and  50 B. 
         [0129]    The smart card  2000  may be used for a memory card serving as a data storage medium or a credit card capable of inputting and outputting information. For example, the memory card may include a multimedia card (MMC) or a secure digital (SD) card. 
         [0130]    While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.