Abstract:
A random data generating apparatus which receives m bits, including: a first random data generator having: an m×2 m  decoder which receives the m bits and outputs n bits; registers arranged in series which shift and store the n bits, to generate shifted n bits; selection output circuits which receive the n bits from the m×2m decoder as selection signals, and provide a predetermined value with respect to valid bits among the n bits output from the m×2m decoder and provide the shifted n bits output from the registers with respect to invalid bits among the n bits output from the m×2 m  decoder, to generate selected n bits; and logic circuits which perform XOR operations on the selected n bits from the selection output circuits and respective ones of the shifted n bits output from the registers, and feed the results of the XOR operations back to a least significant one of the registers only in a case of valid bits among the n bits of output from the m×2 m  decoder. The registers generate the shifted n bits as random data.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of Korean Application No. 99-27886, filed Jul. 10, 1999, in the Korean Patent Office, the disclosure of which is incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to the field of data randomization, and more particularly, to a random data generator suitable for a high density optical disc system, and a scrambler using the random data generator, and method therefore. 
   2. Description of the Related Art 
   Random data generators, which are devices for converting the data of a particular input value into a random number, are being applied to scramblers of optical disc systems using optical discs such as a compact disc read only memory (CD-ROM) or a digital versatile disc (DVD). 
   Data scrambling is generally used to secure data from unauthorized users, and is a type of randomization which is being widely used for the purpose of secure communications. 
   The first essential reason for an optical disc system to scramble received data is to smoothly perform tracking control using differential phase detection (DPD). If the same data is received and thus the same modulated codes are recorded on adjacent tracks of a disc, a DPD signal is not detected upon reproduction, so that a servo unit cannot perform tracking control. For example, in the case of a CD-Audio which is not scrambled, the control of DPD is difficult in sections between tunes (that is, sections where all data is “00h”). 
   The second reason is to reduce the burden of DC suppression control, which is performed by a modulator. In the case where identical data is continuously received, digital sum value (DSV) control itself may be impossible with respect to particular values. Hence, data randomization is needed to prevent such a worst case. Here, DSV is a parameter predicting the DC direction of a codeword stream, and a modulated codeword preferably has the code characteristics of not having a DC component. 
   The third reason is to protect particular data. In the case of a CD-ROM, only the remaining data except for a sync is scrambled to protect a sync pattern (00h, FFh, FFh, . . . , FFh, 00h) within data. 
     FIG. 1  is a circuit diagram of a scrambler of a general DVD system and which uses a random data generator, wherein an exclusive OR gate  10  and registers r 0  through r 14  for providing random data are referred to as a random data generator, and the random data generator and exclusive OR gates  11  through  18  are referred to as the scrambler. 
   In  FIG. 1 , though not shown, 15 bit registers r 0  through r 14  are shifted left in synchronization with the input of a clock signal to be scrambled. The input of the least significant register r 0  is a value obtained by performing an exclusive OR operation with respect to the outputs of the most significant register r 14  and the eleventh least significant register r 10 , and is provided from the exclusive OR (XOR) gate  10 . 
   The random data generation cycle in the random data generator shown in  FIG. 1  is 32K (kilobytes), and is consistent with the size of one Error Correction Code (ECC) block of a DVD, 32K. That is, in the ECC block, a random value having no periodicity is generated, a register is shifted left eight times, and then the XOR gates  11  through  18  perform XOR operations with respect to the outputs of eight lower registers r 0  through r 7 , and input data D 0  through D 7 , whereby scrambled results are obtained. Here, though not shown, a data clock speed at which a data clock signal is input to the XOR gates  11  through  18  is ⅛ of a scramble clock speed at which a scramble clock signal is input to the registers r 0  through r 14 . 
     FIG. 2  is a table for showing the random data results of the registers r 0  through r 14  and scrambling results Do 0  through Do 7  when the initial values of the registers r 0  through r 14  shown in  FIG. 1  are set to be a hexadecimal number of “0001h” and input data D 0  through D 7  are “00h”. It can be seen from  FIG. 2  that the cycle of random data is 32K (32768). 
   Here, the values of the registers r 0  through r 14  are shifted left eight times, and then scrambling is performed. Accordingly, the registers r 0  through r 14  are initialized to initial values with reference to the four upper bits ID (7:4) within the last byte among a 4-byte identification code (ID) allocated to the head of a sector, which is a basic access unit. At this time, attention must be paid to select the initial values. That is, even if the same data is received, random data is generated from an initialized value within one sector, and values within the sector are equally repeated for a duration of 1 ECC block (16 sectors). 
   As shown in  FIG. 3 , the initial values of the registers r 0  through r 14  includes the first initial value “000h” “0001h” and values 0002h, 0004h, 0008h, 0010h, 0020h, 0040h and 0080h obtained by shifting the value “0001h” left seven times, the value “5500h” of registers r 0  through r 14  after a capacity of at least 16K (=2 KH8) is required to return the 7 shifted values, and values 2A00h, 5400h, 2800h, 5000h, 2001h, 4002h and 0005h obtained by shifting the value “5500h” left up to seven times. 
   However, a conventional random data generator and a scrambler using the same cannot cope with when generation and scrambling of random data having a cycle greater than 32K are required. 
   SUMMARY OF THE INVENTION 
   To solve the above problem, an object of the present invention is to provide a random data generator having a serial structure, which can generate a large amount of data as random data. 
   Another object of the present invention is to provide a scrambler of a high-density optical disc system employing a random data generator having a serial structure. 
   Still another object of the present invention is to provide a random data generator having a parallel structure, which can generate a large amount of data as random data. 
   Yet another objective of the present invention is to provide a scrambler of a high-density optical disc system employing a random data generator having a parallel structure. 
   Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention. 
   To achieve the first and other objects, the present invention provides a random data generator including: a m×2 m  table which receives m bits and outputs n bits; registers arranged in series which shift and store the n bits; selection output circuits which receive the n bits of output from the m×2 m  table as selection signals, and provides “0” with respect to valid bits among the n bits of output from the m×2 m  table and provides the outputs of the registers with respect to invalid bits; and logic circuits which perform XOR operations with respect to the n bits of output from the selection output circuits and the n bits of output from the registers, and feed the results of the XOR operations back to a least significant register only in the case of valid bits among the n bits of output from the m×2 m  table, wherein n bits of random data are generated from the registers. 
   To achieve the second and other objects, the random data generator having the serial structure is applied to the scrambler of a high-density optical disc system, and the scrambler comprises a random data generator and a predetermined number of logic gates which perform XOR operations with respect to input data and the outputs of as many lower registers as the predetermined number of logic gates to provide scrambling results. 
   To achieve the third and other objects, the present invention provides a random data generator including: p logic circuits arranged in parallel, which receive the outputs of n registers in parallel, perform XOR operations with respect to the outputs of the n registers which correspond to the results of left-shifting a number of times equal to the number of output data bits having correspondence to the number of effective branches according to a predetermined branch value, and provide 2 m  outputs; selection output circuits, each which select one output among 2 m  outputs provided from each of the logic circuits according to m-bit selection signals, which provide p outputs; and n registers arranged in parallel which generate random data, wherein (n–p) upper registers receive the outputs of p lower registers and the p lower registers receive the p outputs of the selection output circuits. Here, the outputs of registers corresponding to the number of effective branches having a predetermined branch value are fed back to the corresponding logic circuits. 
   To achieve the fourth and other objects, the random data generator having the parallel structure is applied to a scrambler of a high-density optical disc system, and the scrambler comprises the random data generator and a predetermined number of logic gates which perform XOR operations with respect to input data and the outputs of as many lower registers as the predetermined number of logic gates to provide scrambling results. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above objects and advantage of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: 
       FIG. 1  is a circuit diagram of a random data generator used in a scrambler for a general digital versatile disc (DVD) system; 
       FIG. 2  is a table showing the results of random data generated by the random data generator shown in  FIG. 1 , and scrambling results when input data is “0”; 
       FIG. 3  is a table showing initial values used in the registers shown in  FIG. 1 ; 
       FIG. 4  is a scrambler using a circuit diagram of a random data generator having a serial structure according to an embodiment the present invention; 
       FIG. 5  is a circuit diagram of an embodiment of the scrambler using the random data generator shown in  FIG. 4 ; 
       FIG. 6  is a table showing the inputs/outputs of a 3×8 table shown in  FIG. 5 ; 
       FIG. 7  is a circuit diagram of a scrambler using the random data generator when the output of the 3×8 table shown in  FIG. 5  is, for example, “CA00h”; 
       FIG. 8  is a table showing the results of random data generated by the random data generator shown in  FIG. 7 , and the results of scrambling by the scrambler of input data “00h”; 
       FIG. 9  is a table showing the outputs of a 3×8 table in all possible cases when the cycle of random data is 64K in the random data generator shown in  FIG. 5 , and the number of effective branches is four; 
       FIG. 10  is a table showing the outputs of a 3×8 table in all possible cases when the cycle of random data is 64K in the random data generator shown in  FIG. 5 , and the number of effective branches is six; 
       FIG. 11  is a circuit diagram of another embodiment of the present invention of the scrambler using random data generator shown in  FIG. 4 ; 
       FIG. 12  is a table showing an example of the 1×2 table shown in  FIG. 11 ; 
       FIG. 13  is a table showing the results of random data when the output of the 1×2 table shown in  FIG. 11  is “B400h”, and the results of scrambling of input data “00h”; 
       FIG. 14  is a table showing the results of random data when “B400h” and “CA00h” are used as the outputs of the 1×2 table shown in  FIG. 11 , and the results of scrambling of input data “00h”; 
       FIG. 15  is a circuit diagram of a scrambler using a random data generator having a parallel structure according to another embodiment of the present invention; and 
       FIG. 16  is a circuit diagram of an embodiment of the present invention in which a scrambler uses the random data generator and the scrambler using the same shown in  FIG. 15 . 
   

   DETAILED DESCRIPTION OF EMBODIMENTS 
   Reference will now made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures. 
     FIG. 4  is a circuit diagram of a scrambler using a random data generator having a serial structure according to the present invention. Here, the random data generator includes an m×2 m  table  100 , n multiplexers m 0  through M n-1 , n XOR gates G 0  through G n-1 , and n registers r 0  through r n-1 , and the scrambler includes the random data generator having such a configuration and XOR gates  101  through  108  for performing XOR operations with respect to input data D 0  through D 7  and the outputs of registers r 0  through r 7 , to output the results of scrambling. The n multiplexers can be referred to as selection output circuits for selecting and outputting either “0” or the output of each register in response to the n-bit output of the m×2 m  table  100 , and the n XOR gates G 0  through G n-1  can be referred to as logic circuits for providing the n-bit results of XOR operations. The m×2 m  table is, for example, a look up table (LUT) and may be embodied in a ROM memory to provide the desired outputs. 
   In  FIG. 4 , the m×2 m  table  100  receives m bits and outputs n bits. The n multiplexers m 0  through m n-1  receive n output bits Do 0  through Do n-1  as selection signals from the m×2 m  table  100 , and provide “0”, received via a first input port A, as output signals Mo 0  through Mo n-1  to one side of each of the XOR gates G 0  through G n-1  when the values of the n-bit outputs Do 0  through Do n-1  of the m×2 m  table  100  are “1”. At this time, the XOR gates G 0  through G n-1  output the outputs S 0  through S n-1  of the registers r 0  through r n-1  received via the other sides thereof, without change, and finally the output of an accumulated XOR gate G 0  is fed back to the least significant register r 0 . 
   Also, the n multiplexers m 0  through m n-1  provide the outputs S 0  through S n-1  of the registers r 0  through r n-1  received via the second input port B, as output signals Mo 0  through Mo n-1  to the XOR gates G 0  through G n-1  when the values of the n output bits Do 0  through Do n-1  of the m×2m table  100  are “0”. The XOR gates G 0  through G n-1  perform XOR operations with respect to the outputs S 0  through S n-1  of the multiplexers m 0  through m n-1 , and the outputs S 0  through S n-1  of the registers r 0  through r n-1 . Finally, the output of each of the XOR gates G 0  through G n-1  becomes “0”, so there are no values to be fed back to the least significant register r 0 . 
   The n registers r 0  through r n-1  generate n-bit random data, and the XOR gates  101  through  108  provide the scrambling results of XOR operations performed on input data D 0  through D 7  and the outputs of the 8 lower registers r 0  through r 7 , to generate the outputs So 1  through So 7 . 
     FIG. 5  is a circuit diagram of an embodiment of the scrambler using the random data generator shown in  FIG. 4 . Here, the input to a 3×8 table  110  is set to be 3 bits, and the output therefrom is set to be 16 bits Do 0  through Do 15  which are output into 8 combinations. The 3×8 table has 8 different possible outputs, each of which is output as 16 bits, thereby requiring 16 output lines. Here “16” corresponds to “n”. An example of the outputs according to the inputs of the 3×8 table  110  is shown in  FIG. 6 . In the example of  FIG. 6 , each of the output values Do 15  ˜Do 0  of the table  110  is chosen in advance such that no duplication occurs when the values are shifted 2 16  times. 
   If 3 bits having a value “100b” are received, the output value of the 3×8 table  110  is “CA00h” as shown in  FIG. 6 . Accordingly, only the outputs Do 9 , Do 11 , Do 14  and Do 15  of the 3×8 table  110  are “1”, so the outputs Mo 9 , Mo 11 , Mo 14  and Mo 15  of the multiplexers m 9 , m 11 , m 14  and m 15  become “0”. Hence, the XOR gates G 9 , G 11 , G 14  and G 15  provide the outputs S 9 , S 11 , S 14  and S 15  of the corresponding registers r 9 , r 11 , r 14  and r 15 , received via the other side of each of the XOR gates G 9 , G 11 , G 14  and G 15 , as their outputs, so that the output values of the upper XOR gates G 9 , G 11 , G 14  and G 15  are valid. The outputs of the remaining multiplexers m 0 , . . . , m 8 , m 10 , m 12  and m 13  are the outputs S 0 , . . . , S 8 , S 10 , S 12  and S 13  of the registers r 0 , . . . , r 8 , r 0 , r 12  and r 13 , so that the corresponding XOR gates G 0 , . . . , G 8 , G 10 , G 12  and G 13  perform XOR operations with respect to the outputs S 0 , . . . , S 8 , S 10 , S 12  and S 13  of the multiplexers m 0 , . . . , m 8 , m 10 , m 12  and m 13 , each of which is received via one side of each of the corresponding XOR gates, and the outputs S 0 , . . . , S 8 , S 10 , S 12  and S 13  of the registers r 0 , . . . , r 8 , r 10 , r 12  and r 13 , each of which is received via the other end of each of the XOR gates G 0 , . . . , G 8 , G 10 , G 12  and G 13 . The two sets of outputs S 0 , . . . , S 13  of the registers r 0 , . . . , r 13  and the multiplexers m 0 , . . . , m 13  are the same. As a result, the output values of the XOR gates G 1 , . . . , G 9 , G 11 , G 13  and G 14  become “0”. 
   For example, in the case of the multiplexer m 13 , the output Do 13  of the 3×8 table  110  is “0”, so that the output S 13  of the register r 13  received via the second input port B is provided as its output Mo 13 . Finally, the XOR gate G 13  performs a XOR operation with respect to the two data S 13  and S 13  and outputs “0”, which means that the branches S 13  and Mo 13  of the XOR gate G 13  become invalid. Consequently, the scrambler using the random data generator and the scrambler using the same shown in  FIG. 5  can have the structure shown in  FIG. 7  if they are realized in a simple structure with respect to the output value “CA00h” of the 3×8 table  110 . 
   As shown in  FIG. 7 , when the output value of the 3×8 table  110  shown in  FIG. 5  is “CA00h”, the registers r 0  through r 15  are shifted left eight times, and then random data is extracted. In this case, the random data of the registers r 0  through r 15  is as shown in  FIG. 8 , and it becomes evident that a cycle is 64K (65536). 
   The valid branches of the XOR gates G 0  through G 15  in the random data generator vary with the outputs of the 3×8 table  110  shown in  FIG. 5 , which changes the structure of the random data generator. Accordingly, generation of random data having an 8H64K cycle is enabled. This means that a random data generator for a long period can be realized with a structure of a type shown in  FIG. 5  without limit. If the values of the 3×8 table  110  capable of generating random data having a 64K cycle are arranged in the structure shown in  FIG. 5 , tables of  FIGS. 9 and 10  are obtained. 
     FIG. 9  is a table showing branch values in all possible cases, that is, the outputs Do 0  through Do 15  of the 3×8 table  110 , when the number of XOR gates having effective branches of the XOR gates G 0  through G 15  in the random data generator shown in  FIG. 5  is four.  FIG. 10  is a table showing branch values in all possible cases, that is, the outputs Do 0  through Do 15  of the 3×8 table  110 , when the number of XOR gates having effective branches of the XOR gates G 0  through G 15  in the random data generator shown in  FIG. 5  is six. There may be the cases that the number of effective branches is 8, 10 or 12. 
   Thus, the cycle of random data is set to be 64K as an embodiment of the present invention, branch values capable of realizing this embodiment are proposed, and an m×2m table is provided as shown in  FIG. 4  so as to extend the cycle of random data to 2 m H64K. 
   A circuit diagram of another embodiment of the scrambler using the random data generator shown in  FIG. 4  is shown in  FIG. 11 .  FIG. 11  shows a device for generating random data having a long cycle, which has a hardware structure that is as simple as possible. 
   In  FIG. 11 , “B400h” and “CA00h” having as many common parts as possible, among branch structures capable of a 64K random data cycle, are selected, and the contents of a 1×2 table  140  is shown in  FIG. 12 . The 1×2 table has two different possible outputs, each of which is output as 7 bits, thereby requiring 7 output lines. Branches corresponding to the outputs Do 0  through Do 8 , which are commonly 0, of the 1×2 table  140  are all removed. 
   If one bit “0b” is applied to the 1×2 table  140 , the output of the 1×2 table  140  becomes “B400h”, and thus branches Do 14 , Do 11 , and Do 9  become invalid. Random data results provided from registers r 0  through r 15 , and scrambling results So 1  through S 7  provided from XOR gates  151  through  158  when 8 bits of input data Do 0  through Do 7  are “00h”, are arranged in a table and shown in  FIG. 13 . 
   Hence, the table shown in  FIG. 13  has random data extracted whenever the registers r 0  through r 15  are shifted left eight times, and indicates that one cycle is 64K (65536). Consequently, the results So 0  through So 7  obtained by scrambling the input data D 0  through D 7  become data intended to be finally used. 
   On the other hand, if one bit “1b” is applied to the 1×2 table  140  shown in  FIG. 11 , the output of the 1×2 table  140  becomes “CA00h”. Random data results So 0  through So 7  provided from registers r 0  through r 15 , and scrambling results provided from XOR gates  151  through  158  when 8 bits of input data D 0  through D 7  are “00h”, are the same as the contents of  FIG. 8 . 
   Thus, the results of random data that can be obtained by the structure shown in  FIG. 11 , and the results of scrambling of input data “00h”, are arranged in a table and shown in  FIG. 14 . Here, the cycle can be simply extended to 2H64K. 
     FIG. 15  shows a scrambler using a random data generator having a parallel structure according to another embodiment of the present invention. The structures of the scrambler and the random data generator are preferable for systems requiring high-speed signal processing. 
   In the structure shown in  FIG. 15 , the results shifted left eight times are directly applied to each of the registers r 0  through r n-1  in parallel, so that the outputs S 0  through S n-1-8  of the registers r 0  through r n-1-8  are applied to upper registers r 8  through r n-1 . The input of the lower registers r 0  through r 7  depends on which branch structure is selected among the branch structures shown in  FIGS. 9 and 10 . Also, the number of lower registers r 0  through r 7  shown is 8, but can vary with an input data bit (p). 
   Multiplexers m 0  through m 7  each select one input among 2 m  inputs provided via XOR gates  201  through  208  according to m-bit selection signals, and provide the selected input to corresponding registers r 0  through r 7 . Here, the XOR gates  201  through  208  are a combination of several XOR gates. The XOR gates  211  through  218  perform XOR operations of the outputs S 0 , . . . , S 7  and inputs D 0 , . . . , D 6 , respectively, so that they output the final scrambling results S 0 , . . . , So 7 . 
   A circuit diagram of another embodiment of the serial-type random data generator and the scrambler using the same shown in  FIG. 11 , that is, a transformation of a serial type random data generator and a scrambler using the same into a parallel type, is shown in  FIG. 16 . 
   In  FIG. 16 , when a selection signal SEL of each of the multiplexers m 0  through m 7  corresponding to the output “CA00h” of the 1×2 table  140  shown in  FIG. 11  is “1”, the same contents as the contents of the registers r 0  through r 15  which were shifted left eight times in  FIG. 11  are applied in parallel as follows. 
   That is, the outputs S 0  through S 7  of the registers r 0  through r 7  are input to the registers r 8  through r 15  arranged in parallel, respectively. The XOR gates  211  through  236  perform XOR operations, and the results of (S 8 ⊕S 7 ⊕S 4 ⊕S 2 ), (S 9 ⊕S 8 ⊕S 5 ⊕S 3 ), (S 10 ⊕S 9 ⊕S 6 ⊕S 4 ), (S 11 ⊕S 10 ⊕S 7 ⊕S 5 ), (S 12 ⊕S 11 ⊕S 8 ⊕S 6 ), (S 13 ⊕S 12 ⊕S 9 ⊕S 7 ), (S 14 ⊕S 13 ⊕S 10 ⊕S 8 ) and (S 15 ⊕S 14 ⊕S 11 ⊕S 9 ) are applied to the registers r 0  through r 7  via the first input port A of each of the multiplexers m 0  through m 7 , respectively. 
   Also, when the selection signal SEL of each of the multiplexers m 0  through m 7  corresponding to the output “B400h” of the 1×2 table  140  shown in  FIG. 11  is “0”, the outputs S 0  through S 7  of the registers r 0  through r 7  are input to the registers r 8  through r 15 , respectively, and the results of (S 8 ⊕S 6 ⊕S 5 ⊕S 3 ), (S 9 ⊕S 7 ⊕S 6 ⊕S 4 ), (S 10 ⊕S 8 ⊕S 7 ⊕S 5 ), (S 11 ⊕S 9 ⊕S 8 ⊕S 6 ), (S 12 ⊕S 10 ⊕S 9 ⊕S 7 ), (S 13 ⊕S 11 ⊕S 10 ⊕S 8 ), (S 14 ⊕S 12 ⊕S 11 ⊕S 9 ) and (S 15 ⊕S 13 ⊕S 12 ⊕S 10 ) are applied to the registers r 0  through r 7  via the second input port B of each of the multiplexers m 0  through m 7 , respectively. 
   The random data results provided from the registers r 0  through r 15 , and the scrambling results So 0  through So 7  when the input data D 0  through D 7  provided from XOR gates  241  through  248  are “00b”, are the same as those shown in a table of  FIG. 14 . 
   In the serial structure shown in  FIG. 11 , random data results and scrambling results are obtained after shifting each of the registers r 0  through r 15  left eight times, and a scramble clock signal provided to each of the registers r 0  through r 15  must be eight times as fast as a data clock signal provided to the XOR gates  151  through  158 . Whereas, in the parallel structure of  FIG. 16 , the same results as those shown in  FIG. 11  can be obtained even with one shift, a scramble clock signal provided to each of the registers r 0  through r 15  is as fast as a data clock signal provided to the XOR gates  241  through  248 , and thus, a scramble clock signal having the same speed as the speed of the data clock signal of the serial structure can be used. 
   Accordingly, the serial structure shown in  FIG. 11  is simpler than a parallel structure, but may have a disadvantage in that it must operate fast. The parallel structure shown in  FIG. 16  operates at a speed of ⅛ of the operating speed of the serial structure, but may have a disadvantage in that the circuit is somewhat more complicated. Thus, they can be selected according to the circumstances. 
   According to the present invention, random data having a cycle of 64K or greater can be generated, and a random data generator for 2 m H64K can be realized with an m×2m table. Also, the present invention can be used as a random data generator for a scrambler of a high-capacity optical disc system such as an anticipated high density (HD)-DVD. 
   Although a few preferred embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.