Abstract:
This disclosure relates to a protective relaying system for a polyphase power transmission line in which at least two separate line operating conditions at a remote end of a protected line section are transmitted to a local end of the line section over a single communication channel. In the preferred illustrated embodiment, the operating conditions of three-line conductors are sequentially transmitted whenever a fault condition is sensed on any one or more of the three-line conductors. During the normal, non-faulted operation, a coded signal is continually transmitted to maintain the time derived signals at the receiver in substantial synchronism with the time derived signals of the transmitter. The coded signal also establishes a trip inhibiting or guard signal at the receiver.

Description:
This is a continuation of application Ser. No. 548,132 filed Feb. 7, 1975, and now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     A segregated phase comparison relaying system which is arranged to phase compare the current in each of the phase conductors as well as the ground fault current is described and claimed in an application for U.S. Pat. Ser. No 402,687, now allowed, and which has been assigned U.S. Pat. No. 3,893,008 and an issue date of July 1, 1975. As set forth therein, a separate communication channel is provided for each of the transmitted line operating conditions. In accordance with the teachings of this invention, a single channel is used to transmit a time divided multiplexed signal which sequentially contains all of the line operating conditions. The multiplexed signal is decoded at the receiver with a minimum time delay upon the occurrence of a fault. In the illustrated embodiment, a guard word of 6 data bits is continually transmitted in the absence of a fault, from the transmitter location (hereinafter sometimes referred to as the remote location). This guard word contains a synchronizing signal that maintains the 6 data bit counter at the receiver location (hereinafter sometimes referred to as the local location) in exact synchronism with the 6 data bit signal generator at the remote location. As long as the data bits of the guard word are being received, a guard or inhibit signal will be maintained at the local location. The data-bit arrangement of the guard word determines the time of the occurrence of the synchronizing signal at the local location. 
     When a fault condition is sensed at the remote location, the transmission of the guard word is terminated and the transmission of the proper fault word, which describes the existing fault operating condition, is initiated. The fault words contains three data-bits, each data-bit representing the line conducting condition of a different line conductor as determined by its sensor. The three data-bits for the three separate line conductor sensors are always generated in a predetermined order and exist for the same predetermined time interval. Since the time intervals of the demodulating or decoding network at the receiver are synchronized with the time intervals of the coding network at the transmitter, and the data-bits of the fault words are derived by scanning the outputs of the line sensors in an endless chain or loop, the data-bits from the remote location may be time decoded for determining at the local location the operating condition of the individual line conductors at the remote location. 
     It should be appreciated from the foregoing that under normal operating conditions, a code word from the transmitter maintains the decoder of the receiver synchronized so that when a fault occurs, the comparison of the operating conditions of the line conductors at the local and remote locations is initiated without delay whereby the proper circuit breakers may be acutated promptly to deenergize the faulted conductor or conductors, as the case may be. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a relaying network embodying apparatus for transmitting and receiving line operating information in accordance with the inventon; 
     FIG. 2 is a block diagram showing in greater detail certain of the features of the relaying apparatus for relaying the phase and residual currents more generally disclosed in FIG. 1; 
     FIG. 3 is a functional block diagram of the transmitter coder; and, 
     FIG. 4 is a functional block diagram of the receiver decoder. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Referring to the drawings by characters of reference, the numerals 1, 2 and 3 indicate the phase busses or conductors of a three-phase power supply which are suitably energized from one or more power sources (not shown). Phase conductors 4, 5 and 6 of a three-phase power transmission line are energized respectively from the phase busses 1, 2 and 3 through breakers 10, 11 and 12. The low pass filter 8 offers substantially no impedance to the transmission of power at the Hz of the transmitted power, but provides a high impedance to the carrier Hz which transmits intelligence to the remote relaying apparatus at the remote station (not shown)over the transmission line phase conductor. 
     For simplicity, only the relaying apparatus associated with one end of the protected line section is illustrated. It is to be distinctly understood, however, that a similar relaying apparatus is associated with the other end of the protected line section. It is also to be understood that the receiver at one end tuned to receive information transmitted by the transmitter at the other end of the protected line section and vice versa. 
     Current transformers 13, 14 and 15 are associated with the phase conductors 4, 5 and 6 and provide output quantities which are related to the phase of, and the magnitude of, the current in the phase conductors 4, 5 and 6. The output quantities of the current transformers 13, 14 and 15 are supplied to the primary windings of current isolating transformers 16, 17 and 18. Each of the current transformers 16, 17 and 18 have their secondaries individually connected to individual loading resistors so that the output quantities supplied to the phase current responsive relaying networks 20, 21 and 22 are voltage signals. 
     The networks 20-22 are provided with individual output conductors 25-27 and 28-30, respectively, which normally are deenergized to provide logical 0 output signals, but which will be energized to provide logical 1 output signals in response to the operation of its associated fault detector described more fully below in connection with the description of FIG. 2 
     A breaker tripping network 24 includes a plurality of OR networks 34, 36 and 38, and an ANY-2-OR network 40. Each of the OR networks 34, 36 and 38 has two input terminals. A first input terminal of these OR networks is connected respectively to the output conductors 25, 26 and 27 of the networks 20, 21 and 22 associated with phases A, B and C. Each of these OR networks 34, 36 and 38 has a second input terminal connected to the output terminal of the ANY-2-OR network 40. The ANY-2-OR network 40 has its three input terminals connected individually to the conductors 25, 26 and 27. 
     The networks 20-22 are each coupled to the receiver decoder 44 and to the transmitter coder 45. The receiver decoder 44 and the transmitter coder 45 are illustrated in greater detail in FIGS. 3 and 4. The receiver decoder 44 is connected to the output of the receiver portion of the transmitter-receiver 48 and the transmitter coder is connected to the transmitter portion of the transmitter-receiver 48. 
     As indicated more fully in FIG. 4, the illustrated receiver decoder 44 receives three sequentially arranged input signals in endless fashion during fault operation. These input signals or data-bits are sequentially supplied to the networks 20-22 through the conductors 25a-27a, respectively. It will be apreciated, however, that within the scope of the invention, the transmitter coder 45 as well as the receiver decoder 44, connected to the networks 20-22 by the conductors 28-30 respectively, may be arranged for any number of sequentially arranged output and input signals. The transmitter-receiver 48 transmits and receives signals over one of the phase conductors, illustrated in FIG. 1 as being the conductor 5. The output-input of the transmitter receiver 48 is connected to an intermediate tap of a coupling capacitor 50 which is connected between the line conductor 5 and a ground or earthed conductor. 
     While the transmission of intelligence between the remote and local stations is illustrated in this aplication as being by power line carrier it will be understood that other means may be used to transmit the intelligence, such as microwave or leased telephone circuit, among others. 
     For purposes of simplifying the disclosure, only a sungle relaying network 20 is illustrated in FIG. 2. The networks 21 and 22 are identical to the network 20. As illustrated in FIG. 1, the networks 20-22 have their switches SW1 positioned such that the fault detector 58 (see FIG. 2) controls the response of the network to a fault. This is the position when these networks are energized with phase current quantities. With the switch SW1 in its other position, the network could be used as a ground fault responding relay. In this instance, the I L  overcurrent network 60 would provide the fault signal thereby making this network sensitive to a lower current than it would be if the fault detector 58 were used. This is possible because any ground current flow above a predetermined magnitude, as represented by the setting of the I L  overcurrent network 60, is indicative of a ground fault. 
     The relaying network 20 is provided with a current derived signal through the isolating current transformer 16 and energizes the loading resistor whereby the output busses 62A and 63A supply a voltage quantity proportional to current to the I L  overcurrent network 60, and I H  overcurrent network 64, the fault detector or current change network 58 and a squarer network 67. 
     The local squarer network 67 is provided with three output conductors 68, 69 and 70, which transmit square wave signals I SWP , I SWN  and I SW  which are of the same Hz as that supplied to the busses 62A and 63A and are phase related thereto. The signal I SW , as will be set forth below, has a positive square wave portion, which is of the same phase as the voltage supplied to the local squarer 67, and which is in phase with and of substantially identical length to the positive half cycle of the input voltage waves. The quantity I SW  is supplied to the input terminal 71A of the transmitter coder 45 through the conductor 28. 
     Under normal non-fault conditions, a logical 1 signal will be supplied by the receiver decoder 44 through the conductor 78 to the NOT input terminal 108 of the AND network 110. This guard or trip inhibit logical 1 signal prevents the AND network 110 from acutating the timer 90 and consequently the breaker 10 as long as the guard signal exists. Also during normal non-fault conditions, the fault detector 58 supplies a logical 0 input signal to the input terminal 54A of the AND network 110. Further, to prevent false tripping of the breaker 10 due to line charging current, the I L  overcurrent network 60 is arranged to provide a logical 0 signal to the AND network 114 at current magnitudes below those caused by charging current. The output terminal 96 of the AND network 114 is connected through a timer 116 to the imput terminal 25 of the tripping network 24. Both of its input terminals 95 and 95A must receive logical 1 signals to cause the breaker 10 to trip. 
     In the event of an extremely high fault current, the I H  overcurrent network 64 provides a logical 1 input signal to the input terminal 99 of an OR network 112. The output of the OR network 112 is connected to a second input terminal 95A of the AND network 114. Since the I L  network 60 provides its logical 1 output at a current level below that of the I H  network 64, the extremely high fault current, logic 1 signals will be applied to both of the input terminals 95, 95A to time out the timer 116 and provide a logical 1 tripping signal to the tripping network 24 for tripping the breaker 10 without the necessity of phase comparing the current at the two ends of the protected end section. 
     The relaying networks 21 and 22 are provided with input busses 62B-63B and 62C-63C for energization by the transformers 17 and 18 resectively. Similarly, the networks 21 and 22 are provided with output conductors 29 and 30 for connection with the input terminals 71B and 71C respectively of the transmitter coder 45. 
     The output quantities I SWP  and I SWN  from the busses 68 and 69 are supplied through a delay timer 84 to the input terminals 85 and 86 respectively, of AND networks 81A and 81B. The normal input terminal of the AND network 81A and the NOT input terminal of the AND network 81B are connected to the input terminal 82A of the receiver decoder 44 by the conductor 25a. The output terminals of the AND networks 81A and 81B are connected to the two input terminals of an OR network 82, the output terminal of which is connected to an input terminal 87 of the AND network 110. 
     It will be appreciated that when logic 1 signals are applied to both terminals of the AND network 81A, the OR network 82 will apply a logic 1 signal to the AND network 110 and likewise during the time that a logic 0 signal is applied to the conductors 25a by the output terminal 82A of the receiver decoder 44 and a logic 1 signal is applied to the input terminal 86 of the AND network 81B, the OR network 82 will again supply a logic 1 signal to the terminal 87 of the AND network 110. 
     As indicated above, this supplied logical 1 signal is ineffectual as long as logic 0 signals are not supplied to the input terminal 108 from the receiver decoder output terminal 103A through conductor 78 and/or a logical 1 signal is not supplied to the input terminal 54A of the AND network 110 by the fault detector 58. 
     The output of the fault detector 58 is also supplied from the network 20 through the conductor 31 to an input terminal 55A of the transmitter coder 45. The input terminals 55B and 55C of the transmitter coder 45 are connected by the conductors 32 and 33 of the network 21 and 22. Similarly, the conductors 28, 29 and 30 connect to the input terminals 71A, 71B and 73C, respectively of the transmitter coder 45 to the networks 20, 21 and 22 whereby these input terminals are energized by the I SW  quantities thereof. 
     Referring now more particularly to FIG. 3, transmitter coder 45 comprises an OR network 120 having three input terminals connected to the input output conductors 31, 32 and 33 of the networks 20-22. The output terminal 121 of the OR network 120 is connected through an inverter 122 to the lower input terminals of each of a plurality of AND networks 124, 125, 126, 127, 128 and 129. The output terminals of these AND networks are connected to input terminals of an OR network 131. The output terminal 121 of the OR network 120 is also connected directly to the lower input terminals of each of a plurality of AND networks 133, 134 and 135. The output terminals of these last-named AND networks are connected to the input terminals of an OR network 137. The output terminals of the OR networks 131 and 137 are connected to the input terminals of an OR network 139, the output terminal of which is connected to the J and K input terminals of a JK flip-flop 141 having a clocking input terminal C. The connection to the K terminal includes an inverter. 
     It will be appreciated that as long as all of the conductors 31, 32 and 33 apply logical 0 signals to the OR network 120, the AND networks 124 through 129 are armed and the AND networks 133 through 135 are disarmed. When, however, a fault occurs and one or more of the conductors 31, 32 and 33 apply a logic 1 signal to the OR network 120, a logic 1 arming signal will be supplied to the lower input terminals of the AND networks 133 through 135 and the arming signal to the AND networks 124-129 will be removed so that these AND networks 124-129 are no longer effective to actuate the OR network 131. 
     The transmitter coder 45 includes a data transmitting clock 144 which provides an endless series of timed pulses at its output conductor 146. These pulses are supplied to the divide-by-6 counter with decoded output 148 and to the clocking terminal C of the flip-flop 141. The output terminals 0, 1, 2, 3, 4, 5 and 6 of the divide-by-6 counter 148 are sequentially energized with a logical 1 output signal as a consequence of the series of output pulses from the data transmitting clock 144. The logical 1 output signal from the output terminal 6 is supplied through a delay network 150 to the reset terminal R of the counter 148. The delay time interval provided by the delay network 150 is preferably less than 1/4 of the time interval between the individual output pulses of the data transmitting clock and resets the counter 148 at the end of each 6 counts. 
     The output terminals 0 through 5 are individually connected to the middle input terminals of the AND networks 124-129 respectively. The output terminals 0 and 3 are connected to an OR network 152, the output terminals 1 and 4 are connected to the input terminals of an OR network 153 and the output terminals 2 and 5 are connected to the input terminals of an OR network 154. The output terminals of these OR networks 152, 153 and 154 are connected individually to the upper input terminals of the AND networks 133-135. 
     The upper input terminals of the AND networks 124-129 are supplied with coding signals as desired. At least one of these coding signals must be of a different logical sign than the others. As indicated, the upper input terminals of the AND networks 124-126 are supplied with logical 1 signal, while those of the AND networks 127-129 are supplies with logical 0 signals. With this coding, the transmitting word, with the networks 20-22 operating in a non-fault condition, will be 111000. The data-bits of the coded signal or word will be repeated continually as long as the non-fault condition continues (no logical 1 input signals are applied to the OR network 120). The logical signals from the OR network 131 are supplied through the OR network 139 to the JK input terminals of the flip-flop 141. When logical 1 signals are supplied by the output terminals 0, 1 and 2 of the counter 148 to the AND networks 124, 125 and 126, one of these AND networks and the data clock provides the conducting pulse to the clocking terminal C, the flip-flop will provide a logical 1 output at the coder output terminal 156. 
     The logical signal from the terminal 156 is supplied to the transmitter-receiver 48 by the conductor 157 and the transmitter-receiver 48 will transmit accordingly. Similarly, when logical 1 signals are supplied by the outputs 3, 4 and 5 of the counter 148, the AND network 127-129 will supply logical 0 signals to the flip-flop 141 and logical 0 signals will be transmitted by the conductor 157 to modulate the transmitter whereby the transmitted signal is in accordance therewith. The transmitted code word will represent 111000 with the data bits being transmitted in sequence. 
     Upon the occurrence of a fault, sensed by any one or more of the fault detectors of the networks 20, 21 and 22, the OR network 120 will provide a logical 1 output signal. This removes the arming signal from the AND networks 124-129 and applies an arming signal to the AND networks 133-135. The AND networks 133, 134 and 135 receive their second arming signals from the divide-by-6 counter 148 through the OR networks 152-154. Therefore, when a logical 1 output signal appears at either of the output terminals 0 or 3, a logical 1 output signal will arm the AND network 133. When a logical 1 signal appears at either of the output terminals 1 or 4, the AND network 134 will be armed. When a logical 1 signal appears at either of the output terminals 2 or 5, the AND network 135 will be armed. Since the remaining input terminals of the AND networks 133, 134 and 135 are individually connected to the conductors 28, 29 and 30, respectively, output logical signals of the AND networks 133, 134 and 135 will then be in accordance with the logic state of the output conductors 28-30 of the networks 20-22 as determined by the phase currents in the phase conductors 4, 5 and 6 respectively. By reference to FIG. 2, it will be appreciated that the logic signal supplied by the conductors 28-30 will be logic 1 signals during 1/2 cycle of the input signal I SW  supplied to the squarer 67 and logical 0 during the other half cycle of the input signal supplied to the squarer 67 of the networks 20, 21 and 22 respectively. Therefore, the OR network 137 will modulate the transmitted signal to sequentially transmit data bits which represent sequentially the I SW  signals of the networks 20, 21 and 22. 
     Summarizing, the output terminal 156 will be energized in accordance with the code established by the AND networks 124-129 during non-fault operation. During the fault operation, the output terminal 156 will be energized in accordance with the phase of the current flowing on the lines 4, 5 and 6 as scanned by the divide-by-6 counter 148. 
     The transmitter-receiver 48 may take any desired form that will transmit data bits in sequence which are in accordance with the series of logical 0 and logical 1 signals supplied to its inputs. The output signal of the transmitter-receiver 48 is supplied through the usual coupling capacitor 50 to the conductor 5 and transmitted to the transmitter-receiver 48 at the other end of the protected line section. The receiver at the other end of the line section receives the transmission and energizes its output terminal in accordance with the data bit information in the received signal. 
     The receiver decoder 44 shown in greater detail in FIG. 4, has its input terminal 158 connected to the output terminal of the transmitter-receiver 48 by a conductor 159. The data bit signals energize a 6 data bit shift register 160, the non-inverted input terminals of AND networks 162, 163 and 164 and the synchronized receiver clock 166. The receiver clock 166, like the data transmitting clock 144, may be crystal controlled and tuned to provide its output timing pulses in substantial synchronization with the clock 144. The data bit pulses of the incoming signal maintain the output signals of the synchronized receiver clock 166 in predetermined phase relationship and with the received data bits. Preferably, this phase relationship is such that the synchronized output clocking pulses at the output terminal 168 of the clock 166 are in substantial phase relationship with the received data bits. 
     The output terminal 168 of the clock 166 is connected through an inverter 169 to a timing bus 170. This bus 170 is connected to the clocking terminal 171 of the shift register 160 and the input terminal 172 of a divide by 18 counter 174. The input terminal 175 of a divide-by-3 counter with decoded output 176 is connected directly to the output 168. 
     The shift register 160 is provided with a plurality of output terminals 1-6. As the data input bits are received at the input terminal 158, the output bits or quantities progressively shift from the terminal 6 to 1, respectively, in the usual manner. As illustrated in FIG. 4, the inverted signal from the output terminal 6 is connected to one input terminal of the AND networks 178, 182 and 183 and the non-inverted signal therefrom to one input terminal of the AND networks 179, 180 and 181. The inverted output of the terminal 5 is connected to one input terminal of the AND networks 178, 179 and 183 and the non-inverted signal therefrom to one input terminal of the AND networks 180, 181 and 182. Similarly, the output terminals 4, 3, 2 and 1 are connected through normal and inverting circuits to the other input terminals of the AND networks 178, 179, 180, 181, 182, 183 as illustrated. 
     When a full input sequence of the code word, 111000 has been supplied to the input terminal 158, the AND network 178 will provide a logical 1 output signal to one input terminal of an OR network 186. The next data-bit input signal of the code word will provide an output signal 110001 sequentially along the terminals 6-1 and the AND network 183 then provides a logical 1 input signal to the OR network 186. Similarly, as the sequence of input data bits of the code word progresses, the AND networks 182, 181, 180 and 179 will in sequence provide logical 1 signals to the OR network 186. Therefore, it will now be appreciated that as long as the code word is being transmitted to the receiver 44, one of the AND networks 178-183 will supply a logical 1 signal to the OR network 186 and network 186 will energize its output bus 187 with a logical 1 output signal. 
     This bus 187 is connected to the trip inhibit or guard signal output terminals 103A, 103B and 103C whereby guard or trip inhibit signals will be supplied to the AND networks 110 of the relaying networks 20, 21 and 22 through the conductors 78, 79 and 80. The bus 187 is also connected to the NOT input terminals of the AND networks 162, 163 and 164. Therefore, as long as a logical 1 signal is supplied to the bus 187, these AND networks are prevented from providing any logical 1 output signals at their output terminals. 
     Each time the synchronizing word 111000 is completed, a logical 1 signal is supplied by the AND network 178 to the divide-by-2 counter 189. Each second time the complete signal 111000 is received, output terminal 190 of the divide-by-2 counter supplies an output pulse through the output bus 191 to the one input terminal of an OR network 192 and one input terminal of an OR network 193. The output terminal of the OR network 192 is connected through a delay network 194 to the reset terminal R of the counter 189. The other input terminal of the OR network 192 is connected to the output terminal of the divide-by-18 counter 174. This counter 174 provides a logical 1 output signal every eighteen data bit pulses supplied thereto by the synchronized receiver clock 166. The output terminal of the OR network 193 is connected to the reset terminal R of the divide-by-3 counter line. 
     The counter 176 is driven by the output pulses of the clock 166, in step with the input signal received at the terminal 158, and is reset every three clock pulses. For this purpose, its four count output terminal 3 is connected to the reset input terminal R through the OR network 193. This resetting arrangement of the counter 176 by the counter 189 and by the clock 166 maintains the counter 176 in proper step for comparing the date-bits of the fault words (current conditions of phases A, B and C) with the current sensors (current conditions of phases A, B and C) at the receiver end irrespective of noise or other transient conditions which might otherwise cause an out of step condition. 
     The output terminals 0, 1 and 2 of the counter 176 are connected to third input terminals of the AND networks 162, 163 and 164 respectively. The counter 176, which is synchronized with the data-bits of the received fault word supplied by transmitter coder network 45, scans the fault word so that the data-bits of the fault words supplied by the networks 20-22 associated with the phase conductors 4, 5 and 6 at the transmitter end of the protected line section are arranged to supply signals to the J-K flip-flops 196, 197 and 198 which are associated with the relaying networks associated with the phase conductors 4, 5 and 6 at the receiving end of the protected line section. 
     More specifically, the AND networks 162, 163 and 164 are armed in sequence with the A, B and C phase data-bits of the fault words so that logical 1 and 0 output signals appear at their output terminals in direct accordance with the current condition of the A, B and C phases at the transmitting location. The output terminals of the AND networks 162, 163 and 164 are connected respectively to the K input terminals of the flip-flops 196, 197 and 198 directly and to the J input terminals through inverters. 
     The output terminals 0, 1 and 2 of the counter 176 are connected to one of the input terminals of each of AND networks 202, 203 and 204 respectively and supply arming signals thereto in synchronism with the received data-bits of the fault works. The other input terminals of these AND networks 202, 203 and 204 are connected to the timing bus 170 through a pulse circuit 205. The output circuits of the AND networks 202, 203 and 204 are connected individually to the clocking input terminals C of the flip-flops 196, 197 and 198. The output terminals 82, 82 and 82 of the flip-flops 196, 197 and 198 will be energized with logical 1 and logical 0 signals in delayed time synchronism with the data-bits of the fault words in direct accordance with the I SW  quantities of the relaying networks at the transmitting end of the protected line sections. At the receiving end these outputs become RI SWA , RI SWB , and RI SWC  respectively. 
     It will be understood from the foregoing that as long as the operating condition of the power line is fault free, the coded signal will be transmitted and maintain the receiver clock 166 in exact synchronism with the data transmitting clock 144, maintain counter 176 in step with the operation of the AND networks 133, 134 and 135, and supply a trip inhibit or guard signal to the relaying networks 20-22 associated with the receiver. When a fault occurs, the transmission of the code word is immediately interrupted and the transmitter immediately initiates the transmission of the data-bits of a fault word. The character of each of these data-bits of the fault word is determined by scanning the I SW  signals of the remote relaying networks 20-22 and comparing the RI SWA , RI SWB  and RI SWC  data bits with the I SWA , I SWB  and I SWC  quantities of the local networks 20-22. When the transmission of the code word terminates, the receiver decoder removes the trip inhibit or guard signal from its output terminals 103A, 103B and 103C so that the input terminals 108 of the AND networks 110 of the relaying networks associated with the receiver are now energized with a logical 0 signal and these input terminals are armed. 
     The logical 0 output signal of the OR network 186 also arms the NOT input terminals of the AND networks 162, 163 and 164 and these networks become effective to supply output signals to the JK input terminals of the flip-flops 196, 197 and 198 in accordance with the data bits of the fault word being received. The pulse circuit 205 provides delayed clocking pulses to the clocking terminals C of these flip-flops as determined by the AND networks 202, 203 and 204. This delay of clocking pulses insures that the proper logic signal will be at the JK terminals before the flip-flop is actuated so that the correct RI SWA , RI SWB  and RI SWC  signals are provided. 
     The AND networks 81A and 81B of the networks 20-22 at the local receiver are energized with current signals derived from the local end and with current signals derived from the remote end of the phase current conductors 4, 5 and 6. If these current signals associated with the faulted conductor or conductors are phased such that the current is flowing into the line at both the local and the remote end at the same instant or outwardly of the protected line section at the same instant, the AND networks 81A and 81B will supply logical 1 signals through the OR network 82 to the input terminal 87 of the corresponding AND network 110 and the fault is internal. If no logical 1 signals are supplied, the fault is external to the protected line section. The fault detector or detectors 58 which are associated with the faulted conductor or conductors will supply logical 1 signals to the associated AND network or networks 110 so that when the OR network 82 supplies its logical 1 signal, a logical 1 signal will be supplied from the output terminal 88 to the timer 90 which thereupon starts to time out. As soon as the timer 90 times out, a logical 1 input signal appears at the input terminal 92 of the OR network 112 to provide a logical 1 signal at the input terminal 95A of the AND network 114. Since the I L  network 60 is at this same time supplying a logical 1 input signal to the input terminal 95, the AND network 114 energizes the timer 116, which after the 0.2 m.s. delay, provides a logical 1 input signal to the tripping network 24 through the input conductor 25. If a single conductor is faulted, only the breaker associated with the faulted conductor will be tripped. However, if two conductors are faulted, the ANY-2-OR- network will be actuated and all three breakers will be tripped. 
     In the event that logical 1 signals are not concurrently supplied to the AND network 81A or logical 1 and logical 0 signals to the AND network 81B, the fault is external to the protected line section and no logical 1 signal will be supplied by the OR network 82 to the input terminal 87 of the AND networks 110. Under external fault conditions the tripping network 24 will not be actuated.