Abstract:
A method of manufacturing a flash EEPROM cell with a split-gate structure which can improve the electrical characteristics of the cell by forming a source region through an ion implantation method using a select gate as a mask to prevent the reduction in the electrical characteristics of a gate oxide layer is disclosed.

Description:
FIELD OF THE INVENTION 
     This invention relates to a method of manufacturing a flash EEPROM cell, and more particularly to a method of manufacturing a flash EEPROM cell which can improve the electrical characteristics of the flash EEPROM cell by forming a source region of the cell through an ion implantation method using select gates as a mask to manufacture a flash EEPROM cell with a split-gate structure. 
     INFORMATION DISCLOSURE STATEMENT 
     Generally, a flash EEPROM cell with an electrical program function and an erasure function is classified as having either a stack-gate structure or a split-gate structure. 
     A conventional flash EEPROM cell with a split-gate structure is shown in FIG. 1. As shown in FIG. 1, two gate electrodes with a tunnel oxide layer 3, a floating gate 5, a dielectric layer 6, a program gate 7 and an insulting layer 8 which are formed in stack-structure are formed on the silicon substrate 1. A source and drain regions 2A and 2 are formed in the silicon substrate 1 through an ion implantation process. A side wall insulating layer 9 is then formed on the side walls of the two gate electrodes. A select gate oxide layer 4 is formed on the exposed portions of the silicon substrate. A polysilicon layer 10 is formed on the resulting structure after the select gate oxide layer 4 is formed. A select gate is formed by patterning the polysilicon layer 10, thereby forming a flash EEPROM cell with a split-gate structure. The flash EEPROM cell formed by the above processes cause the electric characteristic of the select gate oxide layer 4 to deteriorate due to the formation of the source region 2A before the formation of the select gate oxide layer 4. Also, the select gate is formed on the source and drain regions 2A and 2, thereby forming a parasitic capacitor. Accordingly, the operational speed of the flash EEPROM cell is reduced due to the parasitic capacitor. 
     SUMMARY OF THE INVENTION 
     Therefore, it is an object of the invention to provide a method of manufacturing a flash EEPROM cell which can solve the above problems by forming a source region of a flash EEPROM cell with a split-gate structure through an ion implantation method using a select gate as a mask. 
     To accomplish the above object, a method of manufacturing a flash EEPROM cell according to the invention comprises the steps of: sequentially forming a tunnel oxide layer, a floating gate, an dielectric layer, a program gate and an insulating layer on a silicon substrate, thereby forming a gate electrode; forming a drain region in the silicon substrate of a side wall of the gate electrode; forming a side wall insulating layer on the side wall of the gate electrode; forming a select gate oxide layer on an exposed portion of the silicon substrate; forming a polysilicon layer on the resulting structure after forming the select gate oxide layer; patterning the polysilicon layer so that a portion of the select gate oxide layer is exposed, thereby forming a select gate; forming a source region in a selected portion of the silicon substrate; sequentially depositing a oxide layer and a BPSG layer after forming the source region; exposing a portion of the select gate, thereby forming a contact hole; and forming a word line on the resulting structure after forming the contact hole. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For fuller understanding of the nature and objects of the invention, reference should be made to the following detailed description and the accompanying drawings in which: 
     FIG. 1 is a sectional view of a conventional flash EEPROM cell. 
     FIG. 2A through 2E are sectional views of illustrating a method of manufacturing a flash EEPROM cell according to the present invention. 
     FIG. 3 is a lay-out of FIG. 2E. 
     Similar reference characters refer to similar parts in the several views of the drawings. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 2A through 2E are sectional views illustrating a method of manufacturing a flash EEPROM cell according to the invention. The present invention will be explained with reference to FIG. 3. 
     Referring to FIG. 2A, a tunnel oxide layer 3, a floating gate 5, a dielectric layer 6, a program gate 7 and an insulating layer 8 are sequentially formed on each selected portion of a silicon substrate 1, thereby forming two gate electrodes. A drain region 2 is formed in the silicon substrate 1 between two gate electrodes through an ion implantation process. Side wall insulating layers 9 are then formed on the side walls of the two gate electrodes. A select gate oxide layer 4 is formed on exposed portions of the silicon substrate 1. A polysilicon layer 10 is formed on the resulting structure after forming the select gate oxide layer 4. A first photoresist pattern 15 is then formed on the polysilicon layer 10. In the above process the side wall oxide layer 9 is formed in a ONO structure which is sequentially formed with an oxide layer, a nitride layer and an oxide layer. 
     With reference to FIG. 2B, a portion of the polysilicon 10 exposed by the photoresist pattern 15 is removed by an etching process, thereby forming a first and second select gates 10A and 10B. The first and second select gates 10A and 10B are isolated respectively. The first photoresist pattern 15 is removed and a source region 2B is then formed in the silicon substrate 1 through an ion implantation method using the first and second select gates 10A and 10B as masks. 
     As shown in FIG. 2C, an oxide layer 11 is formed on the resulting structure after forming the source region 2B and a Boron Phosphorous Silicate Glass(BPSG) layer 12 is then formed on the oxide layer 11. The BPSG layer 12 is planarized and a second photoresist pattern 16 is formed on the BPSG layer 12. 
     Referring to FIG. 2D, a portion of the BPSG layer 12 and the oxide layer 11 exposed by the second photoresist pattern 16 are sequentially etched, thereby forming a contact hole 14. The second photoresist pattern 16 is then removed. 
     Referring to FIG. 2E, a word line 13 is formed by depositing polysilicon, polycide or metal on the resulting structure after forming the contact hole 14, thereby interconnecting the first and second select gates 10A and 10B. FIG. 2E is a sectional view along line A-A&#39; of FIG. 3. In FIG. 3, reference number 20 denotes an active region and reference number 30 denotes a field region. 
     As described above, according to the present invention, since a word line is made of polycide and a select gate is formed with polysilicon, the electrical characteristics of the select gate oxide layer are improved. Also, since a source region is formed through an ion implantation method using select gates as masks, the cell off leakage current of a select transistor is decreased. 
     The foregoing description, although described in its preferred embodiment with a certain degree of particularity, is only illustrative of the principle of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiments disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope and spirit of the present invention are to be encompassed as further embodiments of the present invention.