Abstract:
A calibrator circuit and method for VCOM voltage adjustment for an LCD includes using integrated programmable resistive arrays. The method uses two DACs and three integrated circuit arrays to provide all of the advantages of VCOM calibrator circuits using external resistive voltage-dividers. The integrated circuit resistor arrays reduce the number of external components and PCB space. The method used is suitable for higher resolution adjustment of the VCOM voltage and no calculation is required in the whole adjustment procedure, which saves labor cost, time and enables automation of the calibrator fabrication.

Description:
RELATED APPLICATION 
   The present application claims priority of Chinese Application No. 200610126289.7 filed Sep. 4, 2006, which is incorporated herein in its entirety by this reference. 
   BACKGROUND OF THE INVENTION 
   The present invention is related LCD panels and displays, and, more particularly, to a circuit and method for adjusting the “VCOM” level associated with the LCD panel. 
   As is well known in the art, the VCOM or common voltage of an LCD panel needs to be adjusted to remove undesirable flicker from the display. Various solutions to adjusting the VCOM voltage have been proposed in the prior art. 
   Ideally, the VCOM output should be adjusted as a certain value in the range from (⅓)*AVDD to (⅔)*AVDD (wherein AVDD is the main analog voltage supply for the LCD). The exact value necessary to remove flicker from the LCD display panels will vary according to different LCD manufacturers. If the actual VCOM output value deviates from the desired VCOM value, the LCD will flicker. The intensity of the flicker will increase the more the VCOM value deviates from the optimum desired value. The relationship between VCOM level distribution and LCD flicker intensity is shown in  FIG. 1 . Consequently, a user can readily determine the optimum VCOM level according to the flicker intensity of the LCD display. 
     FIG. 2  shows two types of VCOM calibrators  200  and  202 , each using mechanical potentiometers. The circuit includes external resistor Rd and Rf as well as mechanical potentiometer that includes adjustable resistor Re. Resistors Rd, Re, and Rf are coupled between AVDD and ground, and a buffer coupled to the output of the potentiometer resistor Re. The output of the buffer provides the VCOM output signal for the LCD display. In circuit  200 , the output of the potentiometer is fed directly into the positive input of the buffer. In circuit  202 , the output of the potentiometer is coupled to the junction of resistors Re and Rf, and then fed into the positive input of the buffer. In circuit  200 , the VCOM level output is given by: 
                         V   ⁢           ⁢   COM     =       AVDD   *     (     Rf   +     x   *   Re       )         Rd   +   Re   +   Rf               x   ∈     [     0   ,   1     ]                   (   1   )               
In circuit  202 , the VCOM level output is:
 
                         V   ⁢           ⁢   COM     =       AVDD   *   Rf       Rd   +       (     1   -   x     )     *   Re     +   Rf               x   ∈     [     0   ,   1     ]                   (   2   )               
As we can be seen from a review of equations (1) and (2), the VCOM level output can be changed by adjusting the resistive value of Re accordingly.
 
   There are several drawbacks of using mechanical potentiometers to set the VCOM voltage. The resolution and reliability are relatively poor for a mechanical potentiometer. It is time consuming and labor intensive to mass produce LCD panels using mechanical potentiometers. Further, it is difficult to realize factory automation using mechanical potentiometers. To address these problems, panel manufacturers have started to use digital VCOM calibrators, which greatly simplifies the adjustment process and increases reliability. 
     FIG. 3  shows the implementation of a VCOM calibrator  300  with an external resistive voltage-divider. Calibrator  300  includes an interface and control block  302 , a bus  304  for communicating with a single DAC (“Digital to Analog Converter”)  308 , and a bus  306  for communicating with non-volatile memory block  310 . The output of DAC  308  is coupled to the positive input of buffer  312 , which drives the gate of transistor M 1 . The source of transistor M 1  is coupled to the R SET  resistor at the SET node. The drain of transistor M 1  is coupled to the output of an external resistor divider at the OUT node. The external resistor divider includes resistors R 1  and R 2 , which is coupled between the AVDD power supply and ground. The OUT node is buffered through buffer  314  to provide the VCOM voltage. 
   In  FIG. 3 , the interface and control logic block  302  are used to manage digital signals such as clock, data in, data out, address and control signals. Non-volatile memories (NVMEM)  310  are used to store values of the desired VCOM level. The single DAC  308  is used to adjust the VCOM level. R 1 , R 2  and R SET  are external resistors that determine the adjustment range for the VCOM output. 
   The basic principle for the VCOM calibrator  300  with an external voltage-divider is as follows. The external resistive voltage-divider comprising R 1  and R 2  sets the maximum value of the VCOM adjustment range. Resistor R SET  sets the full-scale sink current, I OUT , which determines the minimum value of the VCOM adjustment range. A larger R SET  value increases the resolution but decreases the VCOM adjustment range. The value of resistors R 1 , R 2  and R SET  can be calculated by using the following procedure.
     1) Set an approximate adjustment range that contains the desired VCOM level. Set the maximum VCOM level as V MAX  and the minimum VCOM level as V MIN .   2) Calculate R 1 /R 2  ratio as:   

   
     
       
         
           
             
               
                 
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   
                     R 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                 
                 ≈ 
                 
                   
                     AVDD 
                     
                       V 
                       MAX 
                     
                   
                   - 
                   1 
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
       
       3) Calculate R 1 /R SET  ratio as: 
     
  
                     R   ⁢           ⁢   1       R   SET       ≈       (         V   MAX       V   MIN       -   1     )     *   Y             (   4   )               
where Y=the number of resistors R in DAC.
     4) Choose R SET  according to the electrical limitations.   5) Calculate R 1  and R 2 .   6) Change the DAC value from 0 to 2 n −1 (n is the bit number of DAC) to adjust the VCOM level between V MIN  and V MAX  until the optimum level is reached.
 
The range for the adjustment is given by:
 
Range= V   MAX   −V   MIN    (5)
 
and the resolution is given by:
   
                 Resolution   =         V   MAX     -     V   MIN           2   n     -   1               (   6   )               
Where n is the resolution of DAC.
 
   From the description above, there are some drawbacks to this method.
     1) Since there is a tradeoff between the adjustment range and the resolution, the adjustment range is generally a small part of the overall possible range of VCOM distribution (generally from ⅓*AVDD to ⅔*AVDD, where AVDD is the analog voltage supply). Thus, it is firstly necessary to test and gain an approximate range that contains the desired VCOM level.   2) After the approximate range is found, it is also necessary to calculate the external resistors R 1 , R 2  and R SET  that determine the range.   3) The external resistors are, in general, less reliable and occupy PCB (“printed circuit board”) area compared with integrated resistors.   

   What is desired, therefore, is a VCOM calibrator circuit for an LCD that can provide an optimum VCOM adjustment voltage, but does not use external resistors or potentiometers. 
   SUMMARY OF THE INVENTION 
   According to the present invention, a calibrator for providing an adjustable VCOM voltage includes a first DAC, a second DAC, a first resistor coupled between a power supply voltage and a calibrator output having an adjustable value controlled by the first DAC, a second resistor coupled between the calibrator output and ground having an adjustable value controlled by the first DAC, and a set resistor coupled between an output of the second DAC and ground, wherein the current flowing through the set resistor is sourced from the calibrator output. All three of the resistors are integrated circuit resistor arrays that are integrated into the same chip with the additional calibrator circuitry. The calibrator includes an interface and control logic block for receiving a clock signal and a data input signal, for providing a first digital input signal for the first DAC, and for providing a second digital input signal for the second DAC. The calibrator includes a non-volatile memory coupled to the interface and control logic block. The calibrator includes a buffer having a first input coupled to the second DAC, a second input coupled to the set resistor, and a current output coupled to the calibrator output. The calibrator also includes a buffer coupled to the calibrator output for providing a buffered VCOM voltage. 
   In operation, the output value of the first DAC is changed to select a sub-range that contains a desired calibrator output value, which is generally between one-third and two-thirds of the power supply voltage. The output value of the second DAC is then changed to achieve the desired calibrator output value. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which: 
       FIG. 1  is a diagram that shows the relationship between VCOM level distribution and LCD flicker intensity according the prior art; 
       FIG. 2  is a schematic diagram of two prior art VCOM calibrator circuits each using a mechanical potentiometer; 
       FIG. 3  is a schematic diagram of a prior art VCOM calibrator circuit using an external resistive voltage-divider; 
       FIG. 4  is a schematic diagram of a VCOM calibrator circuit having internal programmable resistive arrays in an integrated circuit with the other calibrator circuitry according to the present invention; 
       FIG. 5  is a flow chart of a VCOM adjustment procedure using the integrated programmable resistors of the present invention; 
       FIG. 6  is a diagram that illustrates the coarse adjustment of the VCOM level according to the present invention; 
       FIG. 7  is a diagram that illustrates the fine adjustment of the VCOM level according to the present invention; 
       FIG. 8  is a schematic diagram of two integrated circuit arrays used to set the R 1 /R 2  ratio according to the present invention; and 
       FIG. 9  is a schematic diagram of a resistor array and simplified circuit diagram used to set the value of the RSET resistor according to the present invention. 
   

   DESCRIPTION OF THE INVENTION 
   Referring now to  FIG. 4 , a schematic diagram of a VCOM calibrator  400  is shown having integrated programmable resistors according to the present invention. Calibrator  400  includes an interface and control block  402 , a bus  416  for communicating with a first DAC (“Digital to Analog Converter”)  418 , a bus  404  for communicating with a second DAC  408 , and a bus  406  for communicating with non-volatile memory block  410 . The output of DAC  408  is coupled to the positive input of buffer  412 , which drives the gate of transistor M 1 . The source of transistor M 1  is coupled to the R SET  resistor at the SET node. The drain of transistor M 1  is coupled to the output of an internal integrated resistor divider at the OUT node. The internal integrated resistor divider includes resistors R 1  and R 2 , which is coupled between the AVDD power supply and ground. The OUT node is buffered through buffer  414  to provide the VCOM voltage. The output of the second DAC  408  is coupled to the control inputs of adjustable integrated resistors R 1 , R 2 , and RSET as is shown in  FIG. 4 . Note that the reference inputs of DAC  408  are coupled between AVDD and ground and include “Y” resistors having a value of “R” each. Thus, a total resistance of YR is coupled between AVDD and ground. 
   In  FIG. 4 , the functional blocks of the VCOM calibrator  400  with internal programmable resistors are different from the prior art calibrators with an external resistive voltage-divider as follows:
     1) R 1 , R 2  and R SET  are external resistors in PRIOR ART  FIG. 3  whereas they are integrated on chip in  FIG. 4 , according to the present invention.   2) The values of R 1 , R 2  and R SET  are fixed in PRIOR ART  FIG. 3  whereas they are programmable in  FIG. 4 .   3) There is only one DAC to change the VCOM level in PRIOR ART  FIG. 3  whereas there are two DACs for adjusting the VCOM level in  FIG. 4 . The first DAC  418  is used to program resistors R 1 , R 2  and R SET  for selection of the adjustment range. The second DAC  408  has a similar function to the sole DAC shown in  FIG. 3 , whose function is to change the VCOM level.   

   The basic operating procedure of VCOM calibrator  400  with integrated programmable resistors can be summarized in two main steps:
     1) Change the value of the first DAC  418  (k bits) to select a sub-range that contains the desired VCOM level within the probable range of the VCOM level distribution (generally between ⅓*AVDD and ⅔*AVDD, where AVDD is the analog voltage supply). This step is called coarse adjustment.   2) After the desired sub-range is found, change the value of the second DAC  408  (n bits) to achieve the desired VCOM level within this sub-range. This step is called fine adjustment.   

   The flow chart of the adjustment procedure  500  is shown in  FIG. 5 . In  FIG. 5 , “VCOM at boundary point” means that the optimum flicker intensity of LCD panel is already achieved before adjustment and so there is no need to further adjust the VCOM level at all. Step  502  loads the default value of VCOM from the NVMEM  410 . Steps  504  starts the coarse adjustment. Decision diamond  506  asks whether or not the VCOM level has reached the boundary point as described above. If the answer is yes, the adjustment procedure proceeds to step  514 , described below. If the answer is no, the adjustment procedure proceeds to step  508 . Step  508  starts the fine adjustment. Decision diamond  510  asks whether or not the VCOM level has now reached the boundary point as described above. If the answer is yes, the adjustment procedure proceeds to step  514 , described below. If the answer is no, the adjustment procedure proceeds to decision diamond  512 . Decision diamond asks whether or not a precise value of the VCOM voltage is obtained. If the answer is no, the procedure returns to initial step  502 . If the answer is yes, the procedure proceeds to step  516  and the precise VCOM value is stored in NVMEM  410 . For a yes answer at  506  or  510 , the procedure proceeds to step  514  wherein the user sets the VCOM level, and then proceeds to step  516  for storing the final VCOM value. 
   The desired value of VCOM is generally in the range between (⅓)*AVDD and (⅔)*AVDD, depending upon the manufacturer of the LCD display. And so the range for the coarse adjustment should cover this entire range. In the coarse adjustment, the overall range from (⅓)*AVDD to (⅔)*AVDD is separated into 2 k −1 identical sub-ranges whose serial numbers are from 0 to 2 k −2 as shown in diagram  600  of  FIG. 6 . 
   During coarse adjustment, the value of the first DAC, “i”, is changed between 0 and 2 k −1 with a default value 2 k−1 −1 and the value of the second DAC is kept constant at zero. Thus, the ratio of R 1 /R 2  is changed and the output of VCOM is: 
                     V   ⁢           ⁢     COM   ⁡     (   i   )         =       AVDD     (     1   +       R   ⁢           ⁢   1       R   ⁢           ⁢   2         )       =       (       2   3     -     i     3   *     (       2   k     -   1     )           )     *   AVDD         ⁢     
     ⁢       i   =   0     ,       1   ⁢           ⁢   …   ⁢           ⁢     2   k       -   1               (   7   )               
According to Equation (7), if “i” is increased by one, the VCOM output decreases by AVDD/(3*(2 k −1)). Thus the resolution for the coarse adjustment of VCOM is AVDD/(3*(2 k −1)).
 
   The ratio of R 1  to R 2  can be obtained from Equation (7): 
                       R   ⁢           ⁢   1       R   ⁢           ⁢   2       =     (         2   k     -   1   +   i         2     k   +   1       -   2   -   i       )       ⁢     
     ⁢       i   =   0     ,       1   ⁢           ⁢   …   ⁢           ⁢     2   k       -   1               (   8   )               
With this procedure, the sub-range that contains the desired VCOM level can be found by observing the flicker intensity degree of the LCD panel. For example, if “i” is changed from 1 to 3 and the flicker intensity is: flicker intensity (i=1)&gt;flicker intensity (i=3)&gt;flicker intensity (i=2), then the desired VCOM level is in sub-range 2.
 
   After the sub-range is found, the fine adjustment of VCOM level is carried out within this sub-range.  FIG. 7  is the illustration of the fine adjustment of VCOM level. In  FIG. 7 , it is assumed that the desired VCOM level is in sub-range “i”, so we obtain V MAX =VCOM(i) and V MIN =VMAX(i+1)=VCOM(i+1) for fine adjustment. The fine adjustment step is similar to that of the VCOM calibrator with an external resistive voltage-divider. The value of the second DAC, “j”, is changed between zero and 2 n −1 to vary the VCOM output and find the optimum VCOM level. 
   VCOM(i, j) equals: 
                     V   ⁢           ⁢     COM   ⁡     (     i   ,   j     )         =       (       2   3     -     i     3   *     (       2   k     -   1     )           )     *   AVDD   *     (     1   -       j       2   n     -   1       *       R   ⁢           ⁢   1       Y   *     R   SET             )         ⁢     
     ⁢           ⁢       i   =   0     ,         1   ⁢           ⁢   …   ⁢           ⁢     2   k       -   2     ;       ⁢     
     ⁢           ⁢       j   =   0     ,       1   ⁢           ⁢   …   ⁢           ⁢     2   k       -   1               (   9   )               
where Y=number of resistor R in the second DAC.
 
   V MAX (i) is: 
   
     
       
         
           
             
               
                 
                   
                     
                       V 
                       MAX 
                     
                     ⁡ 
                     
                       ( 
                       i 
                       ) 
                     
                   
                   = 
                   
                     
                       V 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         COM 
                         ⁡ 
                         
                           ( 
                           i 
                           ) 
                         
                       
                     
                     ≈ 
                     
                       
                         ( 
                         
                           
                             2 
                             3 
                           
                           - 
                           
                             i 
                             
                               3 
                               * 
                               
                                 ( 
                                 
                                   
                                     2 
                                     k 
                                   
                                   - 
                                   1 
                                 
                                 ) 
                               
                             
                           
                         
                         ) 
                       
                       * 
                       AVDD 
                     
                   
                 
                 ⁢ 
                 
                   
 
                 
                 ⁢ 
                 
                   
                     i 
                     = 
                     0 
                   
                   , 
                   
                     
                       1 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       … 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         2 
                         k 
                       
                     
                     - 
                     2 
                   
                 
               
             
             
               
                 ( 
                 10 
                 ) 
               
             
           
         
       
     
   
   V MIN (i) is: 
                       V   MIN     ⁡     (   i   )       =       (       2   3     -     i     3   *     (       2   k     -   1     )           )     *   AVDD   *     (     1   -       R   ⁢           ⁢   1       Y   *     R   SET           )         ⁢     
     ⁢       i   =   0     ,       1   ⁢           ⁢   …   ⁢           ⁢     2   k       -   2               (   11   )               
Y=number of resistors R in the second DAC.
 
   Due to V MIN (i)=V MAX (i+1), it can be shown that: 
                       R   ⁢           ⁢   1       R   SET       =     (     Y       2     k   +   1       -   2   -   i       )       ⁢     
     ⁢       i   =   0     ,         1   ⁢           ⁢   …   ⁢           ⁢     2   k       -   2     ;               (   12   )               
where Y=the number of resistors R in the second DAC.
 
   Within these 2 n −1 adjustment steps, the optimum “fine” VCOM level can be located. 
   The sub-range for fine adjustment is: 
   
     
       
         
           
             
               
                 
                   Sub-range 
                 
                 = 
                 
                   AVDD 
                   
                     3 
                     * 
                     
                       ( 
                       
                         
                           2 
                           k 
                         
                         - 
                         1 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 13 
                 ) 
               
             
           
         
       
     
   
   The resolution for fine adjustment is: 
   
     
       
         
           
             
               
                 Resolution 
                 = 
                 
                   AVDD 
                   
                     3 
                     * 
                     
                       ( 
                       
                         
                           2 
                           k 
                         
                         - 
                         1 
                       
                       ) 
                     
                     * 
                     
                       ( 
                       
                         
                           2 
                           n 
                         
                         - 
                         1 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 14 
                 ) 
               
             
           
         
       
     
   
   From Equation (8), it can be shown that the sum of the numerator and the denominator of R 1 /R 2  (i.e. R 1 +R 2 ) is a constant and it is equal to 3*(2 k −1). We can use R UNIT  to denote them where R UNIT  is a unit resistor whose value should be determined by its electrical characteristics. 
   The parameter implementation of R 1 /R 2  and R 1 /R SET  obtained from Equation (8) and Equation (12) are listed in Table 1. 
   
     
       
             
           
             
             
             
             
             
           
         
             
               TABLE 1 
             
           
           
             
                 
             
             
               PARAMETER IMPLEMENTATION of R1, R2 AND R SET   
             
           
        
         
             
                 
                 
               R1 
               R2 
               R SET   
             
             
                 
               i 
               (R UNIT ) 
               (R UNIT ) 
               (R UNIT ) 
             
             
                 
                 
             
             
                 
               0 
               2 k  − 1 
               2 k+1  − 2 
               (2 k  − 1) * (2 k+1  − 2)/Y 
             
             
                 
               1 
               2 k   
               2 k+1  − 3 
               2 k  * (2 k+1  − 3)/Y 
             
             
                 
               2 
               2 k  + 1 
               2 k+1  − 4 
               (2 k  + 1) * (2 k+1  − 4)/Y 
             
             
                 
               3 
               2 k  + 2 
               2 k+1  − 5 
               (2 k  + 2) * (2 k+1  − 5)/Y 
             
             
                 
               — 
               — 
               — 
               — 
             
             
                 
               2 k  − 4 
               2 k+1  − 5 
               2 k  + 2 
               (2 k  + 2) * (2 k+1  − 5)/Y 
             
             
                 
               2 k  − 3 
               2 k+1  − 4 
               2 k  + 1 
               (2 k  + 1) * (2 k+1  − 4)/Y 
             
             
                 
               2 k  − 2 
               2 k+1  − 3 
               2 k   
               2 k  * (2 k+1  − 3)/Y 
             
             
                 
               2 k  − 1 
               2 k+1  − 3 
               2 k  − 1 
               — 
             
             
                 
                 
             
           
        
       
     
   
   In this way, the values of R 1 , R 2  and R SET  can be determined very simply and conveniently. 
   Two examples of using integrated programmable resistive arrays to adjust VCOM level are given below. In these examples, a 3-bit first DAC and a 7-bit second DAC are utilized. 
   EXAMPLE 1 
   AVDD=20V, VCOM=13V 
   Coarse Adjustment 
   Step 1: 
   Load default settings: k:=3 (011 2 )
         n:=0 (000 0000 2 )       

   Thus R 1 =10*R UNIT , R 2 =11*R UNIT  
         VMAX=40/3V, VMIN=20/3V.
 
Step 2:
       

   Change k until the desired VCOM level is found in the sub-range between k=0 (000 2 ) and k=1 (001 2 ). 
   The coarse adjustment range is from 20/3V to 40/3V. 
   The coarse adjustment resolution is 20/21 V. 
   Fine Adjustment 
   Step 1: 
   Setting: k:=5 (101 2 )
         n:=64 (100 0000 2 )       

   Thus R 1 =7*R UNIT , R 2 =14*R UNIT , RSET=4.9*R UNIT ;
         VMAX=40/3V, VMIN=260/21 V.
 
Step 2:
       

   Change n until the desired VCOM level is found between n=44 (010 1100 2 ) and n=45 (010 1011 2 ). 
   If n is chosen at 44, the output Value is 13.003V (very close to desired VCOM level of 13V) and only has a 3 mv deviation. 
   The fine adjustment range is 20/21 V. 
   The fine adjustment resolution is 20/2667≈7.5 mV. 
   EXAMPLE 2 
   AVDD=10V, VCOM=4.131V 
   Coarse Adjustment 
   Step 1: 
   Load default settings: k:=3 (011 2 )
         n:=0 (000 0000 2 )       

   Thus R 1 =10*R UNIT , R 2 =11*R UNIT  
         VMAX=40/3V, VMIN=20/3V.
 
Step 2:
       

   Change k until the desired VCOM level is found in the sub-range between k=5 (101 2 ) and k=6 (110 2 ); 
   The coarse adjustment range is from 20/3V to 40/3V. 
   The coarse adjustment resolution is 20/21V. 
   Fine Adjustment 
   Step 1: 
   Setting: k:=5 (000 2 )
         n:=64 (100 0000 2 )       

   Thus R 1 =12*R UNIT , R 2 =9*R UNIT , RSET=4.9*R UNIT ;
         VMAX=30/7V, VMIN=80/21V.
 
Step 2:
       

   Change n until the desired VCOM level is found between n=64 (100 0000 2 ) and n=63 (011 1111 2 ); 
   If n is chosen at 64, the output Value is 4.131V which just equals the desired VCOM level.
         In this case, the desired VCOM level is just at the “boundary point” before fine adjustment, so there is no need to carry on fine adjustment.       

     FIGS. 8 and 9  depict the implementation of realizing the R 1 /R 2  and R SET  values according to the present invention in greater detail. In particular, note that resistors R 1  and R 2  are switched arrays of resistors. 
   In  FIG. 8 , altogether 4*(2 k −1) resistors, which have the same unit value of resistance (R UNIT ), are put in series between AVDD and ground. Among them, 2*(2 k −1) resistors on the left of “OUT” constitute R 1  and the remaining ones on the right constitute R 2 . Overall, 2*(2 k −1) switches which include N 1 ˜N 2   k −1 and P 1 ˜P 2   k −1 are used to determine the valid R 2  and R 1  values which in turn determine the output result. The control signals for N 1 ˜N 2   k −1 and P 1 ˜P 2   k −1 are listed in Table 2 below. For each “i”, overall 3*(2 k −1) resistors are valid between AVDD and GND, others are shorted by the switches which are turned on. For example, if i=2, R 1 =(2 k +1)*R UNIT , R 2 =(2 k+1 −4)*R UNIT  and N 2 =1, P 3 =1; Other switches are off. 
   Among all of these switches, N 2   k −1 or P 2   k −1 may need to withstand a maximum Vgd of 6.5V, which is substantially lower than that of MOS transistors used in prior art methods. Hence, the simplicity and reliability are greatly increased by using this structure and procedure according to the present invention. The VCOM output for this structure is more precise and its total used resistance value is much less than other prior art methods. 
   Generally, 2 k−1  R UNIT  and 2 k −1 switches are required for the implementation of R SET . In fact, the numbers of resistors and switches can be reduced further as long as the resolution can be guaranteed. The case below shows how it can be done. 
   
     
       
             
           
             
             
             
             
             
             
             
             
             
             
             
             
             
             
             
           
             
             
             
           
             
             
             
             
             
             
             
             
             
             
             
             
             
             
             
           
         
             
               TABLE 2 
             
           
           
             
                 
             
             
               CONTROL SIGNALS FOR SWITCHES IN FIG. 8 
             
           
        
         
             
               I 
               P2 k  − 1 
               P2 k  − 2 
               P2 k  − 3 
               . . . 
               P3 
               P2 
               P1 
               N2 k  − 1 
               N2 k  − 2 
               N2 k  − 3 
               . . . 
               N3 
               N2 
               N1 
             
             
                 
             
             
               0 
               0 
               0 
               0 
               . . . 
               0 
               0 
               1 
               0 
               0 
               0 
               . . . 
               0 
               0 
               0 
             
             
               1 
               0 
               0 
               0 
               . . . 
               0 
               1 
               0 
               0 
               0 
               0 
               . . . 
               0 
               0 
               1 
             
             
               2 
               0 
               0 
               0 
               . . . 
               1 
               0 
               0 
               0 
               0 
               0 
               . . . 
               0 
               1 
               0 
             
           
        
         
             
               — 
               — 
               — 
             
           
        
         
             
               2 k  − 3 
               0 
               1 
               0 
               . . . 
               0 
               0 
               0 
               0 
               0 
               1 
               . . . 
               0 
               0 
               0 
             
             
               2 k  − 2 
               1 
               0 
               0 
               . . . 
               0 
               0 
               0 
               0 
               1 
               0 
               . . . 
               0 
               0 
               0 
             
             
               2 k  − 1 
               0 
               0 
               0 
               . . . 
               0 
               0 
               0 
               1 
               0 
               0 
               . . . 
               0 
               0 
               0 
             
             
                 
             
           
        
       
     
   
   Example 
   Y=20, k=3 and n=7, the parameters for R 2 /R 1  and R SET /R 1  is provided in Table 3. 
   
     
       
             
           
             
             
             
             
             
           
             
             
             
             
             
           
         
             
               TABLE 3 
             
           
           
             
                 
             
             
               PARAMETERS OF R2/R1 AND R SET /R1 FOR Y = 20, k = 3 and n = 7 
             
           
        
         
             
                 
                 
               R1 
               R2 
               R SET   
             
             
                 
               I 
               (R UNIT ) 
               (R UNIT ) 
               (R UNIT ) 
             
             
                 
                 
             
           
        
         
             
                 
               0 
               7 
               14 
               4.9 
             
             
                 
               1 
               8 
               13 
               5.2 
             
             
                 
               2 
               9 
               12 
               5.4 
             
             
                 
               3 
               10 
               11 
               5.5 
             
             
                 
               4 
               11 
               10 
               5.5 
             
             
                 
               5 
               12 
               9 
               5.4 
             
             
                 
               6 
               13 
               8 
               5.2 
             
             
                 
               7 
               14 
               7 
               — 
             
             
                 
                 
             
           
        
       
     
   
   In fact, R SET  can use just one type of resistor (4.9*R UNIT ) so as to decrease the resistor numbers from 4 to 1 and decrease the switch number from 7 to 1. This decreases V MIN  a bit and increases the sub-range slightly. However, it is reasonable as long as the resolution is not compromised too much. The ratios of new sub-ranges when R SET =4.9*R UNIT  compared to original sub-ranges are provided in Table 4. 
   
     
       
             
           
             
             
             
           
             
             
             
           
         
             
               TABLE 4 
             
           
           
             
                 
             
             
               RESULT COMPARISON FOR THE SIMPLIFIED CIRCUIT 
             
           
        
         
             
               I 
               Ratio of new sub-range to original sub-range 
               % Change 
             
             
                 
             
           
        
         
             
               0 
               1.00 
               +0% 
             
             
               1, 6 
               1.06 
               +6% 
             
             
               2, 5 
               1.10 
               +10% 
             
             
               3, 4 
               1.12 
               +12% 
             
             
                 
             
           
        
       
     
   
   In the worst case when AVDD=20V, the sub-range is changed from 0.950V to 1.065V and the resolution is changed from 7.5 mV to 8.9 mV (with an increase for +12%). The difference is quite insignificant compared to the overall range. If one resistor is not enough to guarantee the resolutions for all sub-ranges, we can add some more resistors. However, the total number of resistors used is still less than 2 k −1. As a result, the number of resistors and switches can be greatly decreased. 
   While there have been described above the principles of the present invention, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.