Abstract:
A voltage reference circuit including a positive temperature coefficient current generator, a negative temperature coefficient current generator, and a first resistor is provided. In the positive temperature coefficient current generator, two transistors are operated in the weak inversion region, and a second resistor is connected in series between the gates of the two transistors. The second resistor employs the characteristic that a transistor operated in weak inversion region acts like a bipolar junction transistor to generate a positive temperature coefficient current. The negative temperature coefficient current generator generates a negative temperature coefficient current in response to a negative temperature coefficient voltage drop on a third resistor. The positive temperature coefficient current and the negative temperature coefficient current flow through the first resistor together, thus producing a stable reference voltage.

Description:
BACKGROUND OF THE INVENTION 
   1. Field of Invention 
   The present invention relates to a voltage reference circuit. More particularly, the present invention relates to a voltage reference circuit of a CMOS transistor. 
   2. Description of Related Art 
     FIG. 1  is a curve diagram of the relevant parameters of the semiconductor process technique. Supply voltage is scaling down because of reducing oxcide thickness. The threshold voltage (V TH ) of MOS transistor, however, is not scale down as much as the supply voltage (V DD ). Therefore, in the case that the voltage headroom is limited, all the analog circuits face the problem of maintaining their inherent capabilities under low operating voltage V DD . 
     FIG. 2  is a circuit diagram of a conventional voltage reference circuit. The PMOS transistors MP 21  and MP 22  biased in the sub-threshold region are adopted to successfully obtain larger voltage headroom, such that the circuit can operate under lower operating voltage V DD . The conventional voltage reference circuit includes a current mirror having PMOS transistors MP 24 ˜MP 26 , PMOS transistors MP 21 ˜MP 23 , an operation amplifier  201 , and resistors R 21 , R 22 . For convenience of illustration, node voltages V 21  and V 22  are indicated. Then, the operating principle and the disadvantages of the conventional voltage reference circuit are illustrated with reference to  FIG. 2 . 
   As seen from the node voltages V 21  and V 22  of  FIG. 2 , by using the feedback mechanism formed by the operation amplifier  201  and the PMOS transistors MP 24 , MP 25 , the node voltage V 21  is equal to the node voltage V 22 . Therefore, with the simple analysis of the circuit, the current I 21  flowing through the resistor R 21  is derived as follows.
 
 I   21 =( V   SG21   −V   SG22 )/ R   21   (1)
 
   Herein, the current I 21  is replicated to the resistor R 22  through the current mirror, and the output reference voltage V BG  is obtained as follows.
 
 V   BG   =V   SG23   +R   22   /R   21 *( V   SG21   −V   SG22 )  (2)
 
   Since the PMOS transistors MP 21 , MP 22  are biased in the subthreshold region in an area ratio of 1: K, by using the fact that current characteristics of the PMOS transistors, so they can be analyzed as bipolar transistors analysis, the reference voltage V BG  is further expressed as 
                   V   BG     =       V   SG23     +         R   22       R   21       ·   n   ·     V   T     ·     ln   ⁡     (   K   )                   (   3   )               
where n is a process parameter, and V T  is a thermal voltage. As seen from the formula (3), the conventional voltage reference circuit generates the temperature-independent reference voltage V BG  by using the combination of the negative temperature coefficient voltage V SG23  and the positive temperature coefficient voltage V T .
 
   Along with the changes of the circuit architecture, in order to allow the PMOS transistors MP 21 , MP  22  operate in the subthreshold region, the resistor R 21  that is used by the conventional voltage reference circuit has a larger resistance value, and the current mirrors M 24 ˜M 26  may operate in the subthreshold region arises. Furthermore, the conventional voltage reference circuit outputs the reference voltage V BG , wherein the negative temperature coefficient voltage V SG23  is related to the negative temperature coefficient. Since the temperature coefficient of the current flowing through the PMOS transistor MP 23  is in proportion to the absolute temperature, and additionally two input voltages (i.e. node voltages V 21 , V 22 ) of the operation amplifier  201  are very small so that operation amplifier  201  may not operate at the low-gain region the present invention employs the resistors, R 31  and R 32  in  FIG. 3 , to increase the input common mode voltage of the operation amplifier, which will let opamp  311  operate at the higher gain region. 
   SUMMARY OF THE INVENTION 
   Accordingly, the object of the present invention is to provide a voltage reference circuit, which provides a stable reference voltage with low temperature dependence when operating under a low operating voltage. 
   In order to achieve the above and other objects, the present invention provides a voltage reference circuit. A positive temperature coefficient current generator is used to generate a positive temperature coefficient current. A negative temperature coefficient current generator is used to generate a negative temperature coefficient current. The positive temperature coefficient current and the negative temperature coefficient current flow through a first resistor to generate a temperature-independent current, such that a stable reference voltage is output from the first resistor. The positive temperature coefficient current generator includes a second resistor, a first PMOS transistor, a second PMOS transistor, a positive temperature coefficient current mirror, a first operation amplifier, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The first PMOS transistor and the second PMOS transistor are biased in a weak inversion region, and thus the second resistor connected in series between the gates of the two transistors generates a positive temperature coefficient current by using the current characteristic of the first and second PMOS transistors being similar to that of the bipolar junction transistor. The positive temperature coefficient current mirror employs a negative feedback mechanism formed by the first operation amplifier to produce the bias current required by the first PMOS transistor and the second PMOS transistor. And the third resistor and the fourth resistor provide another current path to the ground, so as to ensure that the positive temperature coefficient current mirror is kept in the strong inversion region. Two input voltages of the first operation amplifier rise up to the common mode input range of the first operation amplifier by the voltage drop of the fifth resistor and the sixth resistor. 
   The negative temperature coefficient current generator includes a negative temperature coefficient current mirror, a second operation amplifier, a seventh resistor, a third PMOS transistor, and a temperature-independent current source. The temperature-independent current source provides a bias current to the third PMOS transistor, so as to make the gate-source voltage of the third PMOS transistor being a voltage only related to the negative temperature coefficient. A negative temperature coefficient current is generated in response to the negative temperature coefficient voltage (the gate-source voltage of the third PMOS transistor) drop on the seventh resistor by the virtual short property in the two input ends of the second operation amplifier. 
   Therefore, in the voltage reference circuit of the present invention, the positive temperature coefficient current and the negative temperature coefficient current are gathered to form a current with low temperature dependence. The current with low temperature dependence flows through the first resistor, thus producing a stable reference voltage. Compared with the conventional architecture, by changing the coupling manner of the second resistor, the positive temperature coefficient current generator makes the circuit operate at a low voltage, and the cost of the layout area of the circuit is also saved. 
   In order to the make aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. 
   It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a curve diagram of the relevant parameters of the semiconductor process technique. 
       FIG. 2  is a circuit diagram of the conventional voltage reference circuit. 
       FIG. 3  is a circuit diagram of the voltage reference circuit according to an embodiment of the present invention. 
       FIG. 4-FIG .  8  are curve diagrams of the circuit characteristic of the voltage reference circuit of the present embodiment. 
   

   DESCRIPTION OF EMBODIMENTS 
     FIG. 3  shows a voltage reference circuit according to an embodiment of the present invention. The voltage reference circuit comprises a positive temperature coefficient current generator  301 , a negative temperature coefficient current generator  302 , and a resistor R 37 . The positive temperature coefficient generator  301  is used to generate a positive temperature coefficient current I PTC , and the negative temperature coefficient current generator  302  is used to generate a negative temperature coefficient current I NTC . Then, two currents I PTC  and I NTC  flow into R 37  to form a temperature-independent current I TC . The current I TC  flows through the resistor R 37  to form a stable reference voltage V BG  with low temperature dependence. 
   The positive temperature coefficient current generator  301  comprises an operation amplifier  311 , a positive temperature coefficient current mirror  304  having PMOS transistors MP 31 ˜MP 34 , PMOS transistors MP 35 , MP 36 , and resistors R 31 ˜R 34 . Two input ends of the operation amplifier  311  are connected to the nodes of Va and Vb respectively, and the output end thereof is electrically connected to the gates of the PMOS transistors MP 31 ˜MP 34 . The PMOS transistor MP 31  has a source connected to the operating voltage V DD , a drain connected to the resistor R 31 , and a gate connected to the output of the operation amplifier  311 . The PMOS transistor MP 32  has a source connected to the operating voltage V DD , a drain connected to the resistor R 32 , and a gate connected to the output of the operation amplifier  311 . The PMOS transistor MP 33  has a source coupled to the operating voltage V DD , a drain connected to the resistor R 35 , and a gate connected to the output of the operation amplifier  311 . The PMOS transistor MP 34  has a source connected to the operating voltage V DD , a drain connected to the resistor R 37 , and a gate connected to the output of the operation amplifier  311 . The resistor R 31  is connected in series between the drains of the PMOS transistors MP 31 , MP 35 , and the resistor R 32  is connected in series between the drains of the PMOS transistors MP 32 , MP 36 . Two resistors R 31  and R 32  are connected to the ground end respectively by another two resistors R 33  and R 34 . Two ends of the resistor R 35  are respectively connected to the gates of PMOS transistors MP 35 , MP 36 . For convenience of illustration, the node voltages Va and Vb are indicated herein. 
   The positive coefficient current generator  301  makes the node voltage Va equal to the node voltage Vb by using the feedback mechanism formed by the operation amplifier  311  and the PMOS transistors MP 31 , MP 32 . In this manner, the voltage difference ΔV SG  drop on the resistor R 35  is derived and expressed as follows.
 
Δ V   SG   =V   SG35   −V   SG36   (4)
 
   The corresponding current I 31  flowing through the resistor R 35  is expressed as follows.
 
 I 31=( V   SG35   =V   SG36 )/ R 35  (5)
 
   In order to make the present voltage reference circuit operating under the low operating voltage V DD , the PMOS transistors MP 35 , MP 36  of the present embodiment operate in the subthreshold region in an area ratio of 1:K. Under the circumstance that the current characteristic of the two transistors MP 35 , MP 36  are similar to that of the bipolar junction transistor, the voltages V SG35  and V SG36  are expressed by the following formulas: 
   
     
       
         
           
             
               
                 
                   V 
                   SG35 
                 
                 ≈ 
                 
                   
                     V 
                     TH 
                   
                   + 
                   
                     n 
                     · 
                     
                       V 
                       T 
                     
                     · 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             D35 
                           
                           
                             
                               
                                 ( 
                                 
                                   W 
                                   ⁢ 
                                   
                                     / 
                                   
                                   ⁢ 
                                   L 
                                 
                                 ) 
                               
                               35 
                             
                             · 
                             
                               I 
                               DO 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
   
                   V   SG36     ≈       V   TH     +     n   ·     V   T     ·     ln   ⁡     (       I   D36           (     W   ⁢     /     ⁢   L     )     36     ·     I   DO         )                   (   7   )               
where, V TH  is a threshold voltage; n and I DO  are process parameters; V T  is a thermal voltage; I D  is a drain current flowing through the MOS transistor; (W/L) 35  is a width to length ratio of the PMOS transistor MP 35 ; and (W/L) 36  is a width to length ratio of the PMOS transistor MP 36 . With formulas (4)˜(7), the current I 31  flowing through the resistor R 35  is derived as follows.
 
   
     
       
         
           
             
               
                 I31 
                 = 
                 
                   
                     1 
                     
                       R35 
                       ⁢ 
                       
                           
                       
                     
                   
                   · 
                   n 
                   · 
                   
                     V 
                     T 
                   
                   · 
                   
                     ln 
                     ⁡ 
                     
                       ( 
                       K 
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 8 
                 ) 
               
             
           
         
       
     
   
   Since the thermal voltage V T  is a positive temperature coefficient, the current I PTC  formed by replicating the current I 31  is a positive temperature coefficient current. In other words, the positive temperature coefficient current mirror  304  generates a positive temperature coefficient current I PTC . 
   In order to prevent the positive temperature coefficient current mirror  304  from operating in the subthreshold region, the positive temperature coefficient current generator  301  employs the resistors R 33  and R 34  to form another current path for the positive temperature coefficient current mirror  304 , such that the positive temperature coefficient current mirror  304  is kept in the strong inversion region by the branch currents I 32  and I 33 . Furthermore, two input ends of the operation amplifier  311  are respectively connected to the PMOS transistors MP 35 , MP 36  by the resistors R 31 , R 32 . The voltage drops on the resistors R 31 , R 32  contribute to raising the two input voltages (i.e. node voltages Va and Vb) of the operation amplifier  311 , such that the operation amplifier  311  is operated at the high-gain region and not limited by the input common mode range of the operation amplifier  311 . 
   In the voltage reference circuit according to the present embodiment, the negative temperature coefficient current generator  302  comprises an operation amplifier  312 , a quasi-temperature-independent current source  313 , a negative temperature coefficient current mirror  305  having PMOS transistors MP 37 , MP 38 , a PMOS transistor MP 39 , and a resistor R 36 . Two input ends of the operation amplifier  312  are connected to the ground respectively by the diode-connected PMOS transistor MP 39  and the resistor R 36 , and the output end thereof is connected to the gates of the PMOS transistors MP 37 , MP 38 . The quasi-temperature-independent current source  313  is connected in series between the operating voltage V DD  and the PMOS transistor MP 39 . The gate and the drain of the PMOS transistor MP 39  are connected to the ground end, and the source thereof is connected to the quasi-temperature-independent current source  313 . The coupling relation of the negative temperature coefficient current mirror  305  is described as follows. The PMOS transistor MP 37  has a source connected to the operating voltage V DD , a gate connected to the output end of the operation amplifier  312 , and a drain connected to the resistor R 37 . The PMOS transistor MP 38  has a source connected to the operating voltage V DD , a gate connected to the output end of the operation amplifier  312 , and a drain connected to the resistor R 36 . 
   In order to provide a negative temperature coefficient current, the negative temperature coefficient current generator  302  employs a quasi-temperature-independent current source  313  to provide a bias current for the PMOS transistor MP 39 , so as to generate a voltage V SG39  related to the negative temperature coefficient. By using the virtual short property in the two input ends of the operation amplifier  312 , a current I 34  with a current strength of V SG39 /R 36  is generated in response to the voltage V SG39  drop on the resistor R 36 . Then, the current I 34  is replicated by the negative temperature coefficient current mirror  305 , such that the negative temperature coefficient current generator  302  generates a negative temperature coefficient current I NTC . 
   In order to further make the voltage reference circuit of the embodiment more comprehensible,  FIG. 4˜FIG .  8  show the circuit characteristics of the present embodiment, which are respectively illustrated below.  FIG. 4  shows that when the operating voltage V DD  is 1 V, in the present embodiment, during the temperature changing from −40° C. to 125° C., the reference voltage variance ΔV BG  of the output reference voltage V BG  is 2.73 mV (i.e. 16.55 ppm/° C.).  FIG. 5  shows the relation between the positive temperature coefficient current I PTC  and the negative temperature coefficient current I NTC  when the operating voltage V DD  is 1 V and the reference voltage variance ΔV BG  is 2.73 mV in the embodiment.  FIG. 6  shows that under the normal operation, the voltage reference circuit of the embodiment allows a minimum operating voltage V DD  of about 600 mV. Variations in reference voltage (VDD=0.6V˜1.5V) with supply voltage and temperature is plotted in  FIG. 7 , the reference voltage variance ΔV BG  resulting from different operating voltages V DD  is 8.91 mV at the worst case. Finally,  FIG. 8  shows the changes of the reference voltage V BG  in the voltage reference circuit of the embodiment, when the process parameters changes, i.e. under different corner model (FF, TT, SF, FS, SS). The present invention took process variation into account. 
   To sum up, the embodiment of the present invention employs the positive temperature coefficient generator and the negative temperature coefficient generator to generate a stable reference voltage with low temperature dependence. Compared with the conventional architecture, the present invention employs the circuit architecture that the coupling mariner of the resistors can be changed to allow the circuit operating under lower operating voltage, and thus the layout area of the circuit and the limitation to the operation amplifier caused by the circuit are reduced and circumvented. Compared with the conventional art, the resistance of the resistor R 35  is greatly reduced, so the circuit area of the embodiment can be further reduced. 
   It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.