Abstract:
A phase-frequency detector (PFD) circuit is disclosed. The PFD circuit includes a PFD portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the PFD portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the PFD portion.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority under 35 U.S.C. §119 of European patent application no. 13,150,315.3, filed on Jan. 4, 2013, the contents of which are incorporated by reference herein. 
     FIELD OF THE INVENTION 
     This invention relates to phase-locked loop (PLL) circuits, and more particular to a phase frequency detector (PFD) circuit for a PLL circuit. 
     BACKGROUND 
     Phase-locked loop (PLL) circuits are well-known in the field of communication systems. They are also they are also commonly used in frequency generating circuits (synthesizers) where quality (accuracy, temperature stability, jitter) of one oscillator is improved by locking to a second higher quality oscillator. The typical task of a PLL is to reproduce and track an original signal while removing as much of the noise as possible. Because of this, they are often used as narrow band filters in low noise satellites communications. 
     A Phase-Frequency Detector (PFD) is a basic building block of a conventional PLL. Such a conventional PLL is shown in  FIG. 1  and, in addition to a PFD, comprises a voltage-controlled oscillator (VCO), a frequency divider, a charge pump (CP) and a loop filter. Here, the CP is an extension of the PFD and is thus analysed (and labelled) in combination with the PFD. 
       FIG. 1  also shows the various accompanying noise sources in the conventional PLL circuit. 
     The transfer function of the PLL relates the output phase of the reference signal to the output phase of the VCO. The transfer function of the noise sources present in the different blocks can have a high pass and a low pass characteristic depending on the block being analysed. From the VCOs point, its phase noise has a high pass characteristic to the output of the PLL. From the rest of the blocks it has a low pass characteristic. Therefore, the in-band phase noise floor of the PLL is determined by the noises of the: crystal oscillator&#39;s phase noise φ X , reference divider&#39;s phase noise φ ref , main divider&#39;s phase noise φ d , phase-frequency detector&#39;s phase noise φ pd , charge pump current noise i np  and loop filter voltage noise V nf , and can be expressed as the following equation (Equation 1):
 
φ in-band   2 =φ X   2 +φ ref   2 +φ d   2 +φ pd   2 +φ LPg   2 +φ CP   2  [dBc/Hz].  (1)
 
     The in-band noise floor is important because it sets the noise floor for the receiving signal. Assuming a good low phase noise crystal oscillator and a low noise frequency divider, the predominant in-band noise contributor is the PFD/CP block. 
     The CP current noise can be decreased on a circuit level. For example, using bipolar instead of MOSFET current mirrors can help lower the 1/f noise. Resistive emitter degeneration in a current mirror can also help reduce the transistors current noise. Another approach to reducing the CP current noise can be taken on a system level. Here, to analyse this, the output noise of the charge pump i np (f) is referred back to the input of the PFD/CP (because it has a low pass transfer function) as phase noise as written in equation 2 below: 
     
       
         
           
             
               
                 
                   
                     
                       PN 
                       CP 
                     
                     = 
                     
                       
                         10 
                         ⁢ 
                         
                           log 
                           ⁡ 
                           
                             ( 
                             
                               φ 
                               CP 
                               2 
                             
                             ) 
                           
                         
                       
                       = 
                       
                         
                           10 
                           ⁢ 
                           
                             
                               log 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     
                                       i 
                                       np 
                                     
                                     ⁡ 
                                     
                                       ( 
                                       f 
                                       ) 
                                     
                                   
                                   
                                     K 
                                     pd 
                                   
                                 
                                 ) 
                               
                             
                             2 
                           
                         
                         = 
                         
                           20 
                           ⁢ 
                           
                             
                               log 
                               ⁡ 
                               
                                 ( 
                                 
                                   2 
                                   ⁢ 
                                   π 
                                   ⁢ 
                                   
                                     
                                       
                                           
                                       
                                       ⁢ 
                                       
                                         
                                           i 
                                           np 
                                         
                                         ⁢ 
                                         
                                           ( 
                                           f 
                                           ) 
                                         
                                       
                                     
                                     
                                       I 
                                       CP 
                                     
                                   
                                 
                                 ) 
                               
                             
                             ⁡ 
                             
                               [ 
                               
                                 dBc 
                                 ⁢ 
                                 
                                   / 
                                 
                                 ⁢ 
                                 Hz 
                               
                               ] 
                             
                           
                         
                       
                     
                   
                   , 
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     where K pd =I CP /2π is the gain of the PFD/CP block and I CP  is the dc value of the CP current. From this, it can be seen that a higher value of K pd  will result in lower system noise. Accordingly, the typical approach to increase K pd  is to increase I CP , nut this has the drawback of increasing power consumption and decreasing the voltage headroom of the CP output, as well as increasing the noise of the charge pump i np (f). 
     BRIEF SUMMARY OF THE INVENTION 
     There is proposed an improvement to a phase-frequency detector circuit which may increase its gain by a factor of two without increasing charge pump (CP) current. As a result, embodiments may be employed to improve the contribution of charge pump noise in a PLL&#39;s in-band phase noise floor by up to 6 dB. 
     According to an aspect of the invention there is provided a PFD circuit according to claim  1 . 
     A PLL circuit may employ an embodiment of the invention. Additional gain provided by an embodiment may enable a higher noise of the charge pump to be tolerated, thereby allowing a wider tuning range of the VCO in the PLL to be accepted. 
     Embodiments may be employed in an optical communication device that uses NRZ signals. 
     According to another aspect of the invention, there is provided a method of phase-frequency detection for a PLL according to claim  9 . 
     According to another aspect of the invention, there is provided a computer program product for phase-frequency detection according to claim  10 . 
     According to yet another aspect of the invention, there is provided a computer system phase-frequency detection according to claim  11 . 
     Embodiments may find application in TFF1xxxx series devices which are optimized for use in microwave applications between 7 and 15 GHz. Applications of such devices include VSAT systems, microwave radio and down conversion in LNBs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Preferred embodiments of the present invention will now be described, by way of example only, with reference to the following drawings in which: 
         FIG. 1  is a schematic block diagram of a conventional PLL circuit; 
         FIG. 2  is a schematic block diagram of a conventional PFD circuit; 
         FIGS. 3A and 3B  illustrate the relationship between the average output current for positive and negative variations of phase difference at the input of the conventional PFD circuit of  FIG. 2 , respectively; 
         FIG. 3C  illustrates the combined relationship between the average output current for variations of phase difference at the input of the conventional PFD circuit of  FIG. 2 . 
         FIG. 4  is a schematic block diagram of a PFD circuit for a PLL according to an embodiment; 
         FIGS. 5A and 5B  illustrate the relationship between the average output current for positive and negative variations of phase difference at the input of the PFD circuit of  FIG. 4 , respectively. 
         FIG. 5C  illustrates the combined relationship between the average output current for variations of phase difference at the input of the PFD circuit of  FIG. 4 ; 
         FIG. 6  is a schematic circuit diagram of a rising edge D flip-flop combined with a AND reset logic gate according to an embodiment of the invention; and 
         FIG. 7  is a schematic circuit diagram of inverters arranged to create a delay cell according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Various techniques for improving the noise performance of a PLL are known, including: increasing the reference frequency, increasing the charge pump current and improving the noise performance of the charge pump. However, these known techniques exhibit various drawbacks. For example, a higher reference frequency may result in a more expensive overtone crystal, or may be incompatible with a given system reference frequency. Increasing the charge pump current may lead to higher spurious components, while decreasing it can facilitate smaller loop filter components and an eventual integration of the loop filter on chip. Improving the noise performance of the CP by using resistive (emitter/source) degeneration comes at the cost of available tuning range. 
     In an attempt to avoid the abovementioned drawbacks, the inventors have devised a concept for increasing the gain of the PFD/CP of a PLL without increasing the CP current. 
     The transfer function of the PFD/CP is the relationship between the phase difference at the input and the average output current. There is proposed a way to modify it to accommodate for larger gain. 
       FIG. 2  illustrates a conventional PFD circuit  100  having first  102  and second  104  data flip-flops connected to first  106  and second  108  current sources via first  110  and second  112  switches, respectively. 
     A reference frequency signal REF is provided to the clock input terminal of the first data flip-flop  102 , and divider frequency signal DIV is provided to the clock input terminal of the second data flip-flop  104 . The data D input terminal of each data flip-flop is connected to a positive voltage supply rail VCC 
     The first  106  and second  108  current sources are connected in series between the positive voltage supply rail VCC and ground GND. The first  110  and second  112  switches are connected in series between the first and second current sources. An output terminal for supplying an output current I OUT  of the PFD circuit  100  is connected to point between the first  110  and second  112  switches. 
     The data Q output of the first data flip flop  102  is connected to the control terminal of the first switch  110 , and also connected to the first input of an AND logic gate  114 . The data Q output of the first data flip flop  102  thus provides an “UP” signal for controlling the operation of the first switch  110  and thus provision of current from the first current source  106  to the output terminal. 
     The data Q output of the second data flip flop  104  is connected to the control terminal of the second switch  112 , and also connected to the second input of the AND logic gate  114 . The data Q output of the second data flip flop  104  thus provides a “DOWN” signal for controlling the operation of the second switch  112  and thus discharging of current via the second current source  108 . 
     The output of the AND logic gate  114  is provided to the reset CLR terminal of each of the first  102  and second  104  data flip flops. In other words, the output of the AND logic gate is adapted to be the reset signal for each of the data flip-flops  102 ,  104 , wherein the reset signal is based on the value of both the UP and DOWN signals. 
       FIGS. 3A and 3B  illustrate the relationship between the average output current  I OUT    for positive and negative variations of phase difference at the input of the conventional PFD circuit of  FIG. 2 , respectively. It will be understood that one current source is “on” only for positive phase errors, while the other current source is “on” only for negative. 
       FIG. 3C  illustrates the combined relationship between the average output current  I OUT    for variations of phase difference at the input of the conventional PFD circuit of  FIG. 2 . In other words,  FIG. 3  illustrates the transfer function of the conventional PFD circuit of  FIG. 1 . 
       FIG. 4  illustrates a PFD circuit  400  for a PLL according to an embodiment. The PFD circuit  400  is similar to the PFD circuit of  FIG. 2 , but comprises an additional (second) AND logic gate  402  as well as first  404  and second  406  delay elements (which are adapted to delay a signal by a predetermined amount of time t d ). 
     In more detail, the PFD circuit  400  comprises first  408  and second  410  data flip-flops connected to first  412  and second  414  current sources. 
     A reference frequency signal REF is provided to the clock input terminal of the first data flip-flop  408 , and divider frequency signal DIV is provided to the clock input terminal of the second data flip-flop  410 . The data D input terminal of each data flip-flop  408 , 410  is connected to a positive voltage supply rail VCC 
     The first  412  and second  414  current sources are connected in series between the positive voltage supply rail VCC and ground GND. First  416  and second  418  switches are connected in series between the first  412  and second  414  current sources. An output terminal for supplying an output current I OUT  of the PFD circuit  400  is connected to point between the first  412  and second  414  switches. 
     The data Q output of the first data flip flop  408  is connected to the control terminal of the first switch  416 , and connected to the first input of a first AND logic gate  420 . The data Q output of the first data flip flop  408  is also connected to a second input of the second AND logic gate  402  via the first delay element  404 . 
     Similarly, the data Q output of the second data flip flop  410  is connected to the control terminal of the second switch  418 , and connected to the first input of the second AND logic gate  402 . The data Q output of the second data flip flop  410  is also connected to a second input of the first AND logic gate  420  via the second delay element  406 . 
     The output of the first AND logic gate  420  is provided to the reset CLR terminal of the first data flip flop  408 , and the output of the second AND logic gate  402  is provided to the reset CLR terminal of the second data flip flop  410 . In other words, the outputs of the first and second AND logic gates are adapted to be reset signal for the first  408  and second  410  data flip-flops, respectively. 
     Similarly to the conventional circuit of  FIG. 2 , the UP and DOWN signals provided by the data Q outputs of the first and second data flip flop, respectively, control current charging/discharging from the first  412  and second  414  current sources, and also control resetting of the flip flops  408 , 410 . However, with each the data Q output of a flip flop being “ANDed” with a delayed version of the data Q output from the other flip flop, resetting is delayed such that operation of the current sources is slightly overlapped. In other words, the operation of the current sources is overlapped so that both current sources are “on” for small phase errors. 
       FIGS. 5A and 5B  illustrate the relationship between the average output current  I OUT    for positive and negative variations of phase difference at the input of the PFD circuit of  FIG. 4 , respectively. It will be understood that both current sources are “on” for small phase errors (i.e. errors corresponding to less than the time delay t d ). 
       FIG. 5C  illustrates the combined relationship between the average output current  I OUT    for variations of phase difference at the input of the PFD circuit of  FIG. 4 . In other words,  FIG. 5  illustrates the transfer function of the PFD circuit of  FIG. 4 . 
     From  FIGS. 5A-5C , it can be seen that the proposed embodiment of  FIG. 4  comprises an arrangement where both current sources are “on” for small phase errors. This provides a transfer function that is not linear for phase differences less than 2π in magnitude but which is instead kinked because of a higher slope (i.e. gain) for (small) phase errors less than t d  in magnitude. 
     When employed in a PLL, the PFD circuit of  FIG. 4  will have a phase error at its input which is maintained within a range by the PLL (assuming the PLL is operating in a lock state). Thus, the phase error at the input of the PFD/CP should be very small and maintained that way by the loop. With the PLL maintaining the phase error in a small window/range, the PFD/CP will operate around the zero crossing (of  FIG. 5C ) with twice the gain of a conventional PFD/CP circuit. By ensuring the PLL only operates around the zero crossing (with phase errors less than t d , for example, the PLL will not experience the nonlinearity of the transfer function (because it will not provide phase errors greater than t d , for example). As a result, lower system noise will be present (due to higher K pd ). 
     The nonlinearity (kinking) of the transfer function illustrated in  FIG. 5C  is determined by the delay elements (which impart a time delay of t d ). These kinks represent the points where the current sources stop operating at the same time. 
     Also, from  FIG. 5C , it can be seen that the transfer function is symmetrical due to the delay elements each providing an identical time delay td. 
     If non-identical delay elements are employed (as may be done in an alternative embodiment), the position of the kinked points in the transfer will be offset accordingly by the mismatch between the differing delay elements. The effect of such a mismatch may not be seen if the overlapping area is wide enough to ensure operation in the higher gradient (i.e. higher gain) section. 
     The introduction of a time delay t d  to the data signals used to reset each flip flop also increases the minimum pulse widths of the UP and DOWN outputs from the data flip flops. The benefit of this is that any dead zone is eliminated. A dead zone occurs when the CP does not have enough time to react to short pulses coming from the PFD. 
     It will be appreciated that a consideration that may need to be taken into account is the calculation of the phase margin. For a fixed loop filter and two values of K pd , the phase margin will be slightly better for a lower value of gain. In the case were a phase margin is very low, a loop filter needs to be modified to the new K pd  value. 
     The concept proposed is to bring together the linear curves of  FIGS. 5B and 5B  so that they overlap for phase errors θe close to zero (i.e. for θe≈0). 
       FIG. 5A  represents the charging current, whereas  FIG. 5B  represents the discharging current.  FIG. 5C  is then their sum (i.e the resultant transfer function). 
     The phase noise contribution of the CP for the conventional arrangement of  FIG. 2  can be calculated to be expressed by the following equation (Equation 3): 
     
       
         
           
             
               
                 
                   
                     PN 
                     
                       CP 
                       ⁢ 
                       
                         - 
                       
                       ⁢ 
                       old 
                     
                   
                   = 
                   
                     
                       10 
                       ⁢ 
                       
                         
                           log 
                           ⁡ 
                           
                             ( 
                             
                               
                                 
                                   i 
                                   np 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   f 
                                   ) 
                                 
                               
                               
                                 K 
                                 
                                   pd 
                                   ⁢ 
                                   
                                     - 
                                   
                                   ⁢ 
                                   old 
                                 
                               
                             
                             ) 
                           
                         
                         2 
                       
                     
                     = 
                     
                       
                         20 
                         ⁢ 
                         
                           log 
                           ( 
                           
                             
                               
                                 i 
                                 np 
                               
                               ⁡ 
                               
                                 ( 
                                 f 
                                 ) 
                               
                             
                             
                               
                                 I 
                                 CP 
                               
                               
                                 2 
                                 ⁢ 
                                 π 
                               
                             
                           
                           ) 
                         
                       
                       = 
                       
                         20 
                         ⁢ 
                         
                           
                             log 
                             ⁡ 
                             
                               ( 
                               
                                 2 
                                 ⁢ 
                                 π 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   
                                     
                                       i 
                                       np 
                                     
                                     ⁡ 
                                     
                                       ( 
                                       f 
                                       ) 
                                     
                                   
                                   
                                     I 
                                     CP 
                                   
                                 
                               
                               ) 
                             
                           
                           . 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Undertaking a similar calculation for the embodiment of  FIG. 4 , the phase noise contribution of the CP (for the embodiment of  FIG. 4 ) can be expressed by the following equation (Equation 4): 
     
       
         
           
             
               
                 
                   
                     PN 
                     
                       
                         CP 
                       
                       ⁢ 
                       
                         - 
                       
                       ⁢ 
                       new 
                     
                   
                   = 
                   
                     
                       10 
                       ⁢ 
                       
                         
                           log 
                           ⁡ 
                           
                             ( 
                             
                               
                                 
                                   i 
                                   np 
                                 
                                 ⁡ 
                                 
                                   ( 
                                   f 
                                   ) 
                                 
                               
                               
                                 K 
                                 
                                   pd 
                                   ⁢ 
                                   
                                     - 
                                   
                                   ⁢ 
                                   new 
                                 
                               
                             
                             ) 
                           
                         
                         2 
                       
                     
                     = 
                     
                       
                         20 
                         ⁢ 
                         
                           log 
                           ( 
                           
                             
                               
                                 i 
                                 np 
                               
                               ⁡ 
                               
                                 ( 
                                 f 
                                 ) 
                               
                             
                             
                               
                                 I 
                                 CP 
                               
                               
                                 π 
                                 ⁢ 
                                 
                                     
                                 
                               
                             
                           
                           ) 
                         
                       
                       = 
                       
                         20 
                         ⁢ 
                         
                           
                             log 
                             ⁡ 
                             
                               ( 
                               
                                 π 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   
                                     
                                       i 
                                       np 
                                     
                                     ⁡ 
                                     
                                       ( 
                                       f 
                                       ) 
                                     
                                   
                                   
                                     I 
                                     CP 
                                   
                                 
                               
                               ) 
                             
                           
                           . 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Combining Equations 3 and 4 above, one arrives at the following equation (Equation 5): 
     
       
         
           
             
               
                 
                   
                     
                       PN 
                       
                         CP 
                         ⁢ 
                         
                           - 
                         
                         ⁢ 
                         old 
                       
                     
                     = 
                     
                       
                         20 
                         ⁢ 
                         
                           log 
                           ⁡ 
                           
                             ( 
                             
                               2 
                               ⁢ 
                               π 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               
                                 
                                   
                                     i 
                                     np 
                                   
                                   ⁡ 
                                   
                                     ( 
                                     f 
                                     ) 
                                   
                                 
                                 
                                   I 
                                   CP 
                                 
                               
                             
                             ) 
                           
                         
                       
                       = 
                       
                         
                           
                             20 
                             ⁢ 
                             
                               log 
                               ⁡ 
                               
                                 ( 
                                 
                                   π 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   
                                     
                                       
                                         i 
                                         np 
                                       
                                       ⁡ 
                                       
                                         ( 
                                         f 
                                         ) 
                                       
                                     
                                     
                                       I 
                                       CP 
                                     
                                   
                                 
                                 ) 
                               
                             
                           
                           + 
                           
                             20 
                             ⁢ 
                             
                               log 
                               ⁡ 
                               
                                 ( 
                                 2 
                                 ) 
                               
                             
                           
                         
                         = 
                         
                           
                             PN 
                             
                               CP 
                               ⁢ 
                               
                                 - 
                               
                               ⁢ 
                               new 
                             
                           
                           + 
                           
                             6 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             dB 
                           
                         
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     
                       PN 
                       
                         CP 
                         ⁢ 
                         
                           - 
                         
                         ⁢ 
                         new 
                       
                     
                     = 
                     
                       
                         PN 
                         
                           CP 
                           ⁢ 
                           
                             - 
                           
                           ⁢ 
                           old 
                         
                       
                       - 
                       
                         6 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         dB 
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     It will therefore be appreciated that the phase noise contribution of the CP for the embodiment of  FIG. 4  may be improved by up to 6 dB compared to the phase noise contribution of the CP for the conventional arrangement of  FIG. 2 . 
     It is, however, noted that equation 5 above is valid only for input phase errors θe that are inside the overlapping area (i.e. having a magnitude less than that corresponding to the time delay td shown in  FIGS. 5A-5C ). Outside of that area (i.e. (i.e. for input phase errors θe having a magnitude greater than td shown in  FIGS. 5A-5C ) the modified PFD acts like the conventional one of  FIG. 2 . 
     It is noted that the embodiment of  FIG. 4  relies on having the charging and discharging current sources active at the same time (in other words, two noisy currents instead of just one). If that time is too long, more noise may be injected into a PLL. In a worst case scenario, it may potentially lead to more noise coming from the charge pump than the K pd  improvement. Accordingly, it will be understood that the approximation made for the CP noise performance to be equal in both cases may only be valid for short delay times. Preferred embodiments may therefore seek to optimize the delay time t d  introduced by the delay elements. 
     It will be understood that the embodiment shown in  FIG. 4  may be implemented using the following components: a conventional tri-state PFD circuit; an additional AND logic gate; and two delay elements. Of course, other embodiments may be implemented using other components and/or circuit topologies. 
       FIGS. 6 and 7  illustrate an exemplary implementation of first and second portions/components of the embodiment of  FIG. 4  in 0.25 μm Qubic4X technology. 
       FIG. 6  is a schematic diagram of a rising edge D flip-flop (e.g. the first D flip flop  408  of  FIG. 4 ) combined with a AND reset logic gate (e.g. the first AND logic gate  420  of  FIG. 4 ). Here, the D flip-flop is implemented in true-single-phase-clock (TSPC) topology to save size area, and the AND reset gate is realised in standard CMOS logic. 
       FIG. 7  is a schematic diagram of M9-M12 inverters arranged to create a delay cell (e.g. the first delay element  404  of  FIG. 4 ) having a time delay between the transition times of M1 and M4, to avoid any discharge on node V1 when a falling edge happens. The delay is achieved with a RC network. The first two inverters  133  and  134  are used as a buffer for driving the RC load, while the last two are used to speed up the signal so that it has small jitter at its rising edge. Transistor M0 is provided to insure that the delayed signal achieves its asymptotic value even for a short width pulse at the input. The delay cell provides a variable delay of between 1 ns (DEN=V CC ) and 300 ps (DEN=GND) delay time. The values are of course exemplary because they depend on how the noise of the PFD/CP increases and how the operating point varies due to noise inside the double gain region. 
     Other possible implementations of a delay cell may employ current starved inverters. However, a drawback associated with such invertors is that they produce small delays in the range of a few tens of picoseconds and may not operate properly for short pulses. 
     A PFD circuit according to an embodiment may be implemented in integer PLL products used for frequency synthesis such as a TFF1xxxx series device. 
     Other embodiments may be applicable to optical communications that use NRZ signals where a phase detector is used to regenerate a carrier from the incoming stream of data. 
     While one or more embodiments have been illustrated in detail, one of ordinary skill in the art will appreciate that modifications and adaptations to those embodiments may be made. 
     Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.