Abstract:
Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

Description:
RELATED PATENT APPLICATION 
     This application is filed as U.S. patent application Ser. No. 11/284,299 on Nov. 21, 2005, which is herein incorporated by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to magnetic RAM (MRAM), or any memory cells based on resistance difference, and more particularly for improving reliability and overall yield by using stress testing. 
     2. Description of the Related Art 
     Stress testing of MRAMs (magnetic or magnetoresistive RAMs) has been attracting the attention of memory system designers because of the ultrathin layer of the insulator of about 1 nm (1 nanometer or 10 Angstrom). Control of the thickness is critical but the thickness will vary in the manufacturing process. Memory systems designers have come up with various methods of testing to weed out magnetic tunnel junctions which do not meet the required minimum thickness and which will lead eventually to failures. A common technique is voltage stress testing. A higher voltage than the standard voltage is applied to the MRAM which causes excess current to flow through the junction, stressing it and leading to failure. These failed cells can then be replaced with redundant cells. 
     U.S. patents which relate to testing of memories and MRAMs are:
     U.S. Pat. No. 6,990,024 (Hidaka) discloses a MRAM with a circuit which determines the tunnel current depending on the manufacturing irregularity of the tunneling film thickness. Using current instead of voltage thus avoids excessive tunnel current. This method secures a data read margin to correspond to the manufacturing irregularity of the thickness of a tunneling film and can further provide a higher current than the normal one in a burn-in test.   U.S. Pat. No. 6,894,937 (Garni et al.) describes a circuit which provides a stress voltage to Magnetic Tunnel Junctions (MTJs) to provide a predetermined acceleration of aging compared to normal operation. The stress voltage is maintained at the desired voltage by a circuit that mocks the loading characteristics of the portion of the memory array being stressed.   U.S. Pat. No. 6,831,872 (Matsuoka.) discloses a means for determining whether the reference level stored in the reference cell is within a preset range after a number of read operations and correction means for correcting the reference level if not within a specified range. This U.S. Patent specifically addresses the testing of a Novel Resistance Control Nonvolatile RAM (RRAM), but points out that its method can also be employed for a MRAM.   U.S. Pat. No. 6,760,865 (Ledford et al.) teaches a Built-In Self-Test (BIST) controller having a sequencer which identifies the test algorithm that is to be performed. This U.S. Patent allows the testing of multiple memories which may be different regarding type, size, data widths, etc. and is geared towards Flash or Electrically Erasable arrays, but DRAM, SRAM, MRAM and FeRAM (Ferroelectric RAM) may be also used.   U.S. Pat. No. 6,347,056 (Ledford et al.) is similar to U.S. Pat. No. 6,760,865 above.   

     It should be noted that none of the above-cited examples of the related art address the need of stressing the cells of a MRAM with voltage and current above the normal operating conditions to weed out random failures and to replace these failed cells with redundant cells that passed the stress test. These needs are met by the invention, which provides a method and implementation to weed out said random failures and replaces these failed cells as will be apparent by the description and drawing of the present invention. 
     SUMMARY OF THE INVENTION 
     It is an object of at least one embodiment of the present invention to provide a method and circuits to stress cells of a MRAM with voltage and current above the normal operating conditions and to thus weed out failures. 
     It is another object of the present invention to replace these failed cells with redundant cells which passed the stress test. 
     It is yet another object of the present invention to significantly improve by these methods and circuits the reliability of MRAMs and the overall yield of the manufacturing process. 
     It is still another object of the present invention to provide a cost effective way of performing the stress test. 
     These and many other objects have been achieved by coupling a stress circuit to a bus of a MRAM which receives read data. The stress circuit then puts a stress voltage onto the bus, were the stress voltage is variable depending on the input to the stress circuit. The stress on the insulation layer of the Magnetic Tunnel Junction (MTJ) is applied by connecting all the selected MTJs to a reference potential, such as ground, through their isolation transistors. For stress testing, the write enabling transistors are gated off, read enabling transistors are gated on. The bit line bi-directional current drivers are in tri-state, i.e. in high impedance mode. Read sensing circuits such as pre-amp stages are turned off. The number of memory cells to be stressed can be chosen by appropriate control of the address decoding circuit, and only limited by the total power dissipation. In addition, the stress time can be varied to suit the application. 
     These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawing, and the following detailed description of the preferred embodiments. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block overview of the circuits of the present invention. 
         FIG. 2   a  is a detailed circuit diagram of the first half of the Cell Blocks of the MRAM, pre-amp and Amplifier for bit  2 . 
         FIG. 2   b  is a detailed circuit diagram of the Reference Block of the MRAM. 
         FIG. 2   c  is a detailed circuit diagram of the second half of the Cell Blocks of the MRAM, pre-amp and Amplifier for bit  1  and the Stress Circuit. 
     
    
    
     Use of the same reference number in different figures indicates similar or like elements. 
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Fast write and read time, almost infinite endurance and radiation hardened characteristics of magnetic or magnetoresistive RAMs (MRAM) make it a very attractive universal RAM. The extremely thin tunnel oxide of the Magnetic Tunnel Junction (MTJ), approximately 10 Angstrom or thinner, presents challenges for both the reliability and manufacturing process control. Stressing the cells with voltage and current above the normal operating conditions can weed out random failures and can replace these failures with redundant cells that pass stress testing. Thus, the reliability of MRAM and overall yield of the manufacturing process is improved significantly. The present invention teaches the method and circuit implementation of performing such a stress test in a cost effective way. 
       FIG. 1  is a block overview of the invention.  FIGS. 2   a - c  show a typical MRAM array organized with n cell blocks and a reference block. Illustrated in  FIGS. 2   a ,  2   b  and  2   c  are Cell Blocks  12  and  14 , where Cell Block  12  is the first and Cell Block  14  is the last cell block (n). Each of the Cell Blocks  12  and  14  comprises w Bit Lines from Bit Line  1  to w, where bits  1  and  2  are shown. Block  12  shows the first n/2 Cell Blocks and Block  14  shows the remaining n/2 Cell Blocks by way of example. There is a single Reference Block  16  with k (k=½w) paired Reference Bit Lines  1  to k, where Reference Bit Lines  1  and  2  are shown, analogous to Cell Blocks  12  and  14 . Cell Blocks  12 ,  14  and Reference Block  16  are in communication with Data Busses  20  and  22 . They in turn are coupled to Bit Line Bi-Directional Current Drivers  24  and  26 , respectively. 
     Each Cell Block from  1  to n is coupled via write transistors, the latter controlled by lines Write y 1  to Write yn, to Data Bus  20 . Shown for illustrative purposes are transistors, controlled by write y 1 , coupled to Bit Lines  1  to w for the first cell block (represented by Cell Block  12 ) and transistors, controlled by write yn, coupled to Bit Lines  1  to w for the n th  cell block (represented by Cell Block  14 ). Each Cell Block  1  to n is further coupled via transistors for write/read, and controlled by lines Write/Read y 1  to yn, to Data Bus  22 . Shown for illustrative purposes are transistors, controlled by write/read y 1 , coupled to Bit Lines  1  to w for the first cell block (represented by Cell Block  12 ) and transistors, controlled by write/read yn, coupled to Bit Lines  1  to w for the n th  cell block (represented by Cell Block  14 ). Reference Block  16  is coupled via transistors, controlled by lines Write y ref, to Data Busses  20  and  22 , respectively. Shown for illustrative purposes are transistors, controlled by write y ref, coupled to paired Reference Bit Lines  1  to k. 
     Write Word Lines and Read Word Lines  1  to m cross Cell Blocks  12  and  14  and Reference Block  16  perpendicular to the Bit Lines and Reference Bit Lines. Coupled between Read Word Lines and Bit Lines or Reference Bit Lines are isolation transistors in series with the Magnetic Tunnel Junctions (MTJs) of the memory cells and ground, where the MTJs are shown symbolically as resistors. Each of the w Reference Bit Lines consists of a pair of k lines where the first pair consisting of lines  1  and  2  are shown in  FIG. 2   b  by way of example, and which are coupled to reference MTJs having a resistive value of Rmin or Rmax, respectively. The reference MTJs are programmed to Rmin and Rmax to provide an average current of (Imin+I max)/2 for the k paired Reference Bit Lines. Paired Reference Bit Lines  1  to k are coupled to the Reference Bus  40  bit  1  to k, respectively. Each Reference Bit Line is fed into 2 Pre-amps ( 42 ). Therefore the number of Reference Bit Lines is ½ of the number of Bit Lines w, and (Imin+I max) is shared by 2 Pre-amps. See  FIG. 2   a  (bit  2 ) and  FIG. 2   c  (bit  1 ). Further shown are lines Block Select  1  and n and line Block Select ref which couple line I R  to Cell Blocks  1  ( 12 ) and n ( 14 ) and the Reference Block ( 16 ), respectively. The gated I R  line, now renamed Word Line, runs parallel to each Write Word Line  1  to m and is enabled by switching means. Switching means may imply devices such as a transistor or a transistor circuit, either of these in discrete form or in integrated circuits (IC). These devices are cited by way of illustration and not of limitation, as applied to switching means. In  FIGS. 2   a ,  2   b ,  2   c , the write word line is the gate of the aforementioned transistor. The Word Line is shown crossing the MTJ resistors. Row Decoder  28  decodes the addresses for the Write and Read Word Lines. 
     Stress circuit  30  is coupled to Data Bus  22 . Vstress transistors tx 1  to txw (where w is the number of tx transistors and equal to the w mentioned above) are shown coupled in an illustrative manner between a supply voltage VDD and lines  1  to w of Data Bus  22 , respectively. The gates of transistors tx 1  to txk are coupled to a control voltage Vstress+Vt. Where Vt stands for the threshold voltage of a transistor. 
     Inputs to Pre-amp  42  (bits  1  to w) are coupled between Data Bus  22  (bits  1  to w) and Reference Bus  40  (bits  1  to k). Coupled to Pre-amp  42  (bits  1  to w) are Sense Amp  44  (bits  1  to w) with outputs Out (bits  1  to w), respectively. Again by way of example, only Pre-amp  42  bit  1  and  2  and Sense Amp  44  bit  1  and  2  are shown. A line Vclamp controls Pre-amps  42 . Paired Reference Bit Lines  1  to k are coupled to Reference Bus  40  (bits  1  to k) via read y ref transistors  1  to w which are activated by a Read y ref line. 
     Read Mode 
     In the normal Read Mode, the transistors controlled by Write/Read y select the Bit Lines of the block to be read and connect them to Data Bus  22 . The transistors controlled by Read y ref connect the Reference Bit Lines to the Reference Bus  40 . The Read Word Line selects which row of cells within the block is to be read. The cell data, either high or low resistance state, are compared with the average resistance of the reference cell by Pre-amp  42  and Sense Amp  44 . Bit Lines and Data Bus  22  are typically biased around 300 mV for optimum MRAM cell operation. Such bias is achieved by using Vclamp transistors and applying a gate voltage Vstress+Vt of typically about 300 mV+Vt (threshold voltage). 
     Write Mode 
     In the normal Write Mode, the transistors controlled by Write/Read y 1  to yn and Write y 1  to yn are both on for the selected Block, so that bi-directional data currents can pass through the Bit Lines. Combined with the selected Write Word line current the desired Data is written into the selected row of cells in the selected Block. 
     Stress Test Mode 
     To implement the Stress Test, a set of Vstress transistors is coupled between the Vdd and Data Bus  22 . These transistors are normally off during the normal Read and Write Mode. In Stress Mode Vclamp transistors and Write y transistors are off. Bit Line Bi-Directional Current Drivers are in tri-state. All the Write/Read y transistors are on. The Write y ref transistors coupled to Data Bus  22 , and thus to the Vstress transistors, are also on; whereas the Write y ref transistors coupled to Data Bus  20  are off. The gate voltage of Vstress transistors is set at voltage Vstress+Vt, therefore Data Bus  22  and all the Bit Lines of n Blocks, including the Reference Bit Lines, are at stress voltage Vstress. 
     After activating the desired number of Read Word Lines, all the MTJs along the activated Read Word Lines are connected to ground (GND) through their isolation transistors. These MTJs are being stressed with above normal operating voltages and currents. We can measure the incremental current through the supply voltage VDD and divide that incremental current by the number of MTJs being stressed to arrive at the approximate current through each MTJ. The desired stress current can then be achieved by varying voltage Vstress. MTJs on unselected Read Word lines are not stressed. The stress voltage can be adjusted by Vstress and the Stress time can be adjusted by how long the selected Read Word Lines are kept on. The number of MTJs to be stressed is only limited by the total power dissipation. For a small MRAM array, all the MTJs can be stressed at the same time. For a large MRAM array, one can step through the Read Word Line addresses to stress all the cells. 
     Advantages of the Present Invention Include the Following:
         The Stress test weeds out random failures;   MTJs on unselected words are not stressed;   The Stress time can be adjusted by how long the selected read word line is active;   The transistors which couple the bit lines to the stress voltage can be FETs;   A variable voltage can be coupled to the gates of the FETs;   The method is applicable to MTJ MRAMs, Phase Change RAMs or Spin Valve MRAMs.       

     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.