Abstract:
The invention relates to a data management method in an array processor containing elementary processors ( 302  ( i,j )) forming an array ( 300 ) of n axes such that an elementary processor ( 302  ( i,j )) is connected to a neighboring elementary processor ( 302  ( i′,j′ )) according to each of the 2n directions ( 310, 312, 314, 316 ) of the array ( 300 ), and controlled by identical instruction cycles determining the neighboring elementary processor ( 302  ( i′,j′ )) that should send the data to the neighboring elementary processor ( 302  ( i′,j′ )) for a subsequent cycle. According to the method, we associate to this elementary processor ( 302  ( i,j )) communication registers (X 1 , X 2 , Y 1 , Y 2 ) dedicated to data exchange according to each axis of the array ( 300 ) and we integrate in the instructions a condition of location of the elementary processor ( 302  ( i,j )) in the array ( 300 ) to determine the neighboring processor ( 302  ( i′,j′ )) sending the data for a subsequent cycle.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a data management method in an array processor and to an array processor implementing this method, particularly to accelerate the transmission of data within this array processor.  
         [0003]     2. Description of the Related Art  
         [0004]     It is known to increase the computing power of electronic equipment by using multiple processors operating in parallel, i.e. simultaneously, to manage complex computing tasks.  
         [0005]     Thus, several processors in an electronic system share a part of the operations to be implemented by this system to improve the system&#39;s global operation time, such distribution is particularly important for electronic systems managing significant data flows in real-time, such as, for example, multimedia data (images, video, etc.).  
         [0006]     Array processors are processors that contain a group of processors, called elementary processors or EP, which implement parallel data processing operations. These elementary processors are physically arranged in the form of an array that can be one-dimensional, in the form of an alignment of elementary processors for example, or two-dimensional, for example, when the elementary processors are arranged in the form of a rectangular array where EPs are localized in a regular manner.  
         [0007]     In this latter case, each elementary processor can send and receive data per operation cycle—a cycle being determined by the clock that regulates the system—as regards one of its neighboring elementary processors according to four directions, North, South, East and West described hereafter, via a mesh communication network connecting the elementary processors in the array.  
         [0008]     Moreover, when an elementary processor is at an edge of the array according to a given direction, it is also called a “bypassed” neighbor according to this given direction to the elementary processor situated at the edge of the array at the opposite of this direction, to which it is thus connected.  
         [0009]     It should also be noted that each elementary processor has an elementary memory unit in which it stores the data being processed that can be sent, or not, to a neighboring elementary processor at the next cycle.  
         [0010]     Array processors also contain control means responsible, amongst other things, for: 
        managing the instructions of the programs executed by the array processor,     sending instructions to the elementary processors such that the corresponding operations are executed by these elementary processors,     executing instructions for transferring data within the array processor, for example between elementary processors.        
 
         [0014]     A particular example of an array processor is an SIMD (Single Instruction Multiple Data) type array processor, within which all the elementary processors implement the same data processing function for different data that the processors have stored in their memory.  
         [0015]     In other words, there is a functional homogeneity of elementary processors, which differ only as regards their position in the array and the data saved to their memory.  
         [0016]      FIG. 1  is a diagram that illustrates some elements of an array processor  100  as an array of elementary processors. In this example, the array  103  is two-dimensional 4×4 with 16 elementary processors  104  ( i,j ) such that i and j are between 0 and 3.  
         [0017]     Each elementary processor EP is connected to control means  102  by communication links  108 , even though, for clarity, only the connection between the EP  104  ( 0 , 0 ) and the control means  102  is shown in  FIG. 1 . These control means execute, amongst, other functions, a program or programs stored in the program memory  101 .  
         [0018]      FIG. 2  schematically represents an example of an array  200  of elementary processors  200  ( i,j ), i and j lying between 0 and 3, for a dimension of 4×4, that are connected to each other by a mesh communication network between the different elementary processors.  
         [0019]     Each elementary processor  202 ( i,j ) has an internal communication register  204 ( i,j ) where the data to be sent by this processor at each operation cycle are saved.  
         [0020]     Furthermore, these elementary processors EP  202  ( i,j ) are connected to each other by communication links  206  {( i,j )( n,m )}, i, j, n and m lying between 0 and 3, of a mesh network connecting the elementary processor  202 ( i,j ) to the physical neighboring elementary processor  202 ( n,m ) or by bypassing as defined below. For clarity, only the link  206 {( 0 , 0 ) ( 0 , 1 )} is referenced in  FIG. 2 .  
         [0021]     Each elementary processor is thus connected to 4 other elementary processors by the mesh communication network in the 4 possible directions (North  210 , South  212 , West  214  and East  216 ). For example, the elementary processor  202 ( 0 , 0 ) is connected to: 
        the elementary processor  202 ( 1 , 0 ) in the direction South  212 ,     the elementary processor  202  ( 0 , 1 ) in the direction East  216 , the elementary processor  204 ( 0 , 3 ), neighbor by bypassing, in the direction West  214 ,     the elementary processor  204 ( 3 . 0 ), neighbor by bypassing, in the direction North  210 .        
 
         [0025]     This type of array processor is specially adapted for moving data between elementary processors at each clock cycle for algorithms that set uniform data movements, particularly for video image processing algorithms. Indeed, it includes several advantages, such as: 
        Simplicity of the data transmission command in the array (displacement to the North, South, East or West) given that, for the same command, all the elementary processors send the data according to the same direction, and     Brief connections between the elementary processors, which allow forecasting for example the times associated to the electric signals, these times being also brief as a result.        
 
         [0028]     It has however be observed that an array processor according to prior art experiences difficulties in managing communications between the elementary processors.  
         [0029]     As a result, it is not possible for the control means to command irregular data moves, that is distinct moves between two elementary processors, as the instructions must be uniform as regards data movements for all the elementary processors.  
         [0030]     Furthermore, numerous cycles may be required to send data when this data is requested or sent from elementary processors situated at the edge of the array due to a “side effect”. This effect is more significant where the quantity of elementary processors on the edge of the array is high in relation to the total number of elementary processors. For example, the side effect is more significant for a 4×4 array than for a 128×128 array.  
       SUMMARY OF THE INVENTION  
       [0031]     The present invention relates to a method for managing data in an array processor containing elementary processors, forming an array of n axes such that each elementary processor is connected to neighboring elementary processors according to each of the 2n directions of the array, each elementary processor being controlled by identical instructions determining the neighboring elementary processor that should send data to this elementary processor for a subsequent cycle, characterized in that communication registers dedicated to data exchange according to each axis of the array are associated with this elementary processor and in that a condition of location of the elementary processor in the array is integrated in each instruction to determine the neighboring elementary processor sending the data taken into account at a subsequent cycle.  
         [0032]     Thanks to the invention, efficiency of algorithm execution by SIMD type array processors is considerably improved, e.g. for video image processing. Indeed, the invention obtains different processing for each elementary processor according to their position in the array from the same uniform communication instruction sent by the control means of the SIMD array processor.  
         [0033]     Hence, a method according to the invention optimizes data transfer from a first elementary processor to a second elementary processor via the optimum route in the internal network of the array processor, and in particular does so without “side effects”.  
         [0034]     The invention also relates to array processor comprising elementary processors, forming an array of n axes such that each elementary processor is connected to neighboring elementary processors according to each of the 2n directions of the array, each elementary processor being controlled by identical instructions determining the neighboring elementary processor that should send data to this elementary processor for a subsequent cycle, characterized in that each elementary processor contains communication registers dedicated to data exchange according to each axis of the array, and in that each elementary processor is able to receive from control means instructions containing a condition of location of the elementary processor in the array to determine the data to be sent to each of its communication register for a subsequent cycle.  
         [0035]     In one embodiment, each elementary processor is assigned a series of bits identifying its position in the array so as to determine the location of the elementary processor by comparing this series of bits with a series of bits received in the instructions.  
         [0036]     According to one embodiment, the series of bits identifying the position of an elementary processor in the array is a series of 2n bits indicating, for each elementary processor, whether this elementary processor is at an edge of the array.  
         [0037]     In one embodiment, the array comprises two axes and four directions.  
         [0038]     According to one embodiment, each elementary processor is assigned four electrical elements whose voltage is set when the elementary processor is enabled and remains set while the elementary processor is enabled. The voltage of these four elements provides the series of bits indicating the position of the elementary processor in the array.  
         [0039]     In one embodiment, the instructions received from the control means contain a first identity of an elementary processor whose data should be copied into a communication register of the elementary processor if the location condition is validated, and a second identity of an elementary processor whose data should be copied if the location condition is not validated.  
         [0040]     According to one embodiment, the communication registers of each elementary processor are independent.  
         [0041]     In one embodiment, each elementary processors contains at least two communication registers dedicated to data exchange according to an axis of the array such that, according to this axis, each elementary processor is connected by at least two data communication networks to a neighboring elementary processor.  
         [0042]     According to one embodiment, each elementary processor further comprises, for each communication register, a multiplexer connected to neighboring elementary processors according to each of the array&#39;s communication axes, this multiplexer comprising means to select data sent by one of these neighboring elementary processors to be copied into this communication register.  
         [0043]     In an embodiment, each communication register of an elementary processor is able to copy the following data at each operation cycle: 
        the data of an internal register in this elementary processor,     the data of a register from the same axis of a neighboring elementary processor,     the data of a register from another axis of a neighboring elementary processor,     the data contained in this same register before the cycle.        
 
         [0048]     According to one embodiment, where an elementary processor is situated at an edge of the array, a neighboring processor is situated at another edge of the array. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0049]     Other characteristics and advantages of the invention will emerge with the description made below as an example, which is descriptive and non-restrictive, and refers to the figures herein where:  
         [0050]      FIG. 1 , described previously, schematically represents an array processor according to prior art,  
         [0051]      FIG. 2 , described previously, schematically represents an array of elementary processors and its mesh network for data transmission according to prior art,  
         [0052]      FIG. 3  schematically represents an array of elementary processors compliant with the invention, and  
         [0053]      FIG. 4  is a diagram of the communication means of an elementary processor according to the invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0054]     In the embodiment of the invention described below.( FIG. 3 ), each elementary processor has a first set of communication registers, X 1  and X 2 , for communicating in the directions West  314  and East  316  and a second set of communication registers, Y 1  and Y 2 , for communicating in the directions North  310  and South  213 .  
         [0055]     The set of communication registers for each elementary processor is thus composed of  4  registers, X 1 , X 2 , Y 1  and Y 2 . The array processor thus features with a double communication network along the horizontal axis (West  314 /East  316 ) and the vertical axis (North  310 /South  312 ).  
         [0056]     In a variant of this embodiment, each elementary processor contains 2×n communication registers destined for communication in the n axes of the array, n being a positive integer.  
         [0057]     In each set of communication registers of a given elementary processor, the internal register of an elementary processor may take the following data at each clock cycle:  
         [0058]     the data of a second internal register in this elementary processor,  
         [0059]     the data of an X 1  or X 2  register of a physical neighboring elementary processor or by bypassing, situated at East  316 ,  
         [0060]     the data of an X 1  or X 2  register of a physical neighboring elementary processor or by bypassing, situated at West  314 ,  
         [0061]     the data of an Y 1  or Y 2  register of a physical neighboring elementary processor or by bypassing, situated at North  310 ,  
         [0062]     the data of an Y 1  or Y 2  register of a physical neighboring elementary processor or by bypassing, situated at South  312 ,  
         [0063]     No change as regards the content of the register before the clock cycle.  
         [0064]     At each clock cycle, the array processor&#39;s control means (not shown) send a conditional communication instruction to indicate which data must be positioned in each communication register.  
         [0065]     For this purpose, each communication instruction sent by the control means has a first “condition” field, a second “first source” field and a third field called the “second source”, described in detail below.  
         [0066]     The condition field is comprised of four bits, that is, one bit for the North edge, one bit for the South edge, one bit for the East edge and one bit for the West edge.  
         [0067]     The condition contained in the condition field is validated by an elementary processor if the elementary processor is positioned on one of the edges that are indicated by the condition&#39;s activated bits. If more than one of the condition bits are enabled an “OR” function is implemented between the two comparisons with the position of the elementary processor to validate or not validate the condition.  
         [0068]     If the condition in the condition field is validated by a given elementary processor, then the “first source” field identifies a second elementary processor whose data should be copied into the relevant register of the first elementary processor.  
         [0069]     If the condition in the condition field is not validated by a given elementary processor, then the “second source” identifies the source that should be copied in the relevant elementary processor&#39;s register.  
         [0070]      FIG. 3  shows a diagram of an example of an array  300  containing 16 elementary processors  302  ( i,j ), such that i and j are between 0 and 3, in compliance with the invention.  
         [0071]     Each processor  302 ( i,j ) has two registers, X 1  and X 2 , for communication on the West  314 -East  316  axis and two registers, Y 1  and Y 2  on the North  310 -South  312  axis.  
         [0072]     In addition each register can import or export data via the mesh communication network represented by the horizontal arrows  304  and the vertical arrows  306 . Each elementary processor is in communication with 4 neighboring elementary processors (with or without bypassing): 1 in the North, 1 in the South, 1 in the East and 1 in the West.  
         [0073]     For example, the elementary processor  302 ( 0 , 0 ) can communicate with:  
         [0074]     its X 1  and X 2  communication registers in read and write mode with the elementary processor  302 ( 0 , 3 ) and the elementary processor  302 ( 0 , 1 ),  
         [0075]     its Y 1  and Y 2  communication registers in read and write mode with the elementary processor  302 ( 3 , 0 ) and the elementary processor  302 ( 1 , 0 ).  
         [0076]     A 4-bit location word is associated with each elementary processor. In  FIG. 3 , all the 4-bit words associated to each elementary processor are indicated (only the word  302 ( 0 , 0 )L is referenced for clarity), such that:  
         [0077]     the first bit is equal to 1 if the given elementary processor is on the North edge and 0, otherwise,  
         [0078]     the second bit is equal to 1 if the given elementary processor is on the South edge and 0, otherwise,  
         [0079]     the third bit is equal to 1 if the given elementary processor is on the East edge and 0, otherwise,  
         [0080]     the fourth bit is equal to 1 if the given elementary processor is on the West edge and 0 otherwise.  
         [0081]     This association of four-bit words with each elementary processor can be implemented by four wires that are powered up or not according to the location of the elementary processor when the SIMD array processor is powered up, and whose voltage no longer varies until the SIMD array processor is powered down.  
         [0082]     The elementary processors that satisfy the condition North  310 , situated at the edge of the array, are the elementary processors  302 ( 0 , 0 ),  302 ( 0 , 1 ),  302 ( 0 , 2 ),  302 ( 0 , 3 ),  
         [0083]     The elementary processors that satisfy the condition South  312 , situated at the edge of the array, are the elementary processors  302 ( 3 , 0 ),  302 ( 3 , 1 ),  302 ( 3 , 2 ),  302 ( 3 , 3 ),  
         [0084]     The elementary processors that satisfy the condition East  316 , situated at the edge of the array, are the elementary processors  302 ( 0 , 3 ),  302 ( 1 , 3 ),  302 ( 2 , 3 ),  302 ( 3 , 3 ) and  
         [0085]     The elementary processors that satisfy the condition West  314 , situated at the edge of the array, are the elementary processors  302 ( 0 , 0 ),  302 ( 1 , 0 ),  302 ( 2 , 0 ),  302 ( 3 , 0 ).  
         [0086]     The conditions may be combined with the logical “OR” function. For example, the elementary processors that satisfy the condition North and West (North or West should be understood) are the elementary processors.  302 ( 0 , 0 ),  302 ( 0 , 1 ),  302 ( 0 , 2 ),  302 ( 0 , 3 ),  302 ( 1 , 0 ),  302 ( 2 , 0 ),  302 ( 3 , 0 ).  
         [0087]      FIG. 4  shows a detail of one of these elementary processors  302 ( i,j ) described in  FIG. 3 , whose communication modes associated to its registers X 1 , X 2 , Y 1  and Y 2  are such that each of these registers can take send or receive data as regards any other register X 1 ′, X 2 ′, Y 1 ′ and Y 2 ′ of a neighboring elementary processor  302 ( i,j ).  
         [0088]     For this purpose, if one considers for example the X 1  register, this uses a multiplexer  400   X1  containing two sub-registers X 1 _XCOM and X 1 _YCOM, in which data, possibly sent by a neighboring elementary processor  302 ′( i,j ) either via a register communication network X 1  or X 2 , or a register communication network Y 1  or Y 2 , are saved.  
         [0089]     Hence, the sub-register X 1 _XCOM contains links  402  specific to the X 1  network data, East (E) or West (W) and to the X 2  network data, East (E) or West (W), such that it can store the data from each of these links with the neighboring elementary processors.  
         [0090]     In a similar manner, the sub-register X 1 _YCOM contains links  404  specific to the Y 1  network data, North (N) or South (S), and to the Y 2  network data, North (N) or South (S), such that it can store the data from each of these links with the neighboring elementary processors.  
         [0091]     Finally, a third sub-register X 1 _SRC is used to store, for use in a new cycle, data already contained in the X 1  register of the elementary processor  302 ( i,j ) itself.  
         [0092]     Hence, it appears that, considering the location condition (represented by X 1 _OP) sent by the control means (not shown) of the array, the multiplexer  400   X1  can integrate data from an X 1 , X 2 , Y 1 , Y 2  network or already contained in the elementary processor by a simple selection.  
         [0093]     The data integrated in the X 1  register for the computation cycle is subsequently sent to the X 1  network by means  406  associated to the latter.  
         [0094]     For this purpose, it should be noted that these means  406  allow data to be sent in the East and West directions.  
         [0095]     In a similar manner, the detail of the communication means associated with the Y 1  register is shown, this uses a multiplexer  400   Y1  containing two sub-registers Y 1 _XCOM and Y 1 _YCOM, in which any data sent by a neighboring elementary processor  302 ′( i,j ), either via a register communication network X 1  or X 2 , or a register communication network Y 1  or Y 2 , are saved.  
         [0096]     The operation of these sub-registers is similar to the operation of the sub-registers described previously, the sub-register Y 1 _XCOM contains links  402 ′ specific to the data in the X 1  network, East (E) or West (W) and X 2  network, East (E) or West (W), and the register Y 1 _YCOM contains links  404 ′ specific to the data in the Y 1  network, North (N) or South (S), and Y 2  network, North (N) or South (S), while a third sub-register Y 1 _SRC is used to store, for use in a new cycle, data already contained in the Y 1  register of the elementary processor  302 ( i,j ) itself.  
         [0097]     Henceforth, according to the location condition (represented by Y 1 _OP) sent by the control means (not shown) of the array, the multiplexer  400   Y1  can integrate data from an X 1 , X 2 , Y 1 , Y 2  network or already contained in the elementary processor by simple selection.  
         [0098]     Subsequently, the data integrated in the Y 1  register for the computation cycle is sent to the X 1  network by means  406 ′ associated with the latter, these means  406 ′ allow data to be sent in the North and South directions.  
         [0099]     The X 2  and Y 2  registers contain the same communication means based on multiplexers as those described for the X 1  and Y 1  registers. However, they are not represented in  FIG. 4  for the sake of simplification.