Abstract:
Transistor configurations have trench transistor cells disposed along trenches in a semiconductor substrate with two or more electrode structures disposed in the trenches, and also metallizations are disposed above a substrate surface of the semiconductor substrate. The trenches extend into an inactive edge region of the transistor configuration and an electrically conductive connection between the electrode structures and corresponding metallizations are provided in the edge region.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The invention relates to a transistor configuration with a structure for making electrical contact with two or more electrodes of a trench transistor cell which are disposed in trenches.  
           [0003]    Transistor configurations fashioned as MOS power transistors are used for controlling switching currents with high current intensities (up to tens of amperes) by low control voltages, the dielectric strength of which transistor configurations in the switched load circuit may amount to up to hundreds of volts and the switching times of which transistor configurations are usually in the region of a few microseconds.  
           [0004]    MOS power transistors are present for example as trench MOS power transistors. A trench MOS power transistor usually contains a semiconductor substrate which has in each case a plurality of trench transistor cells disposed one beside the other in at least one active cell array.  
           [0005]    Depending on the fashioning of the trench transistor cells, it is possible to realize, for example, normally on and normally off p-channel or n-channel trench MOS power transistors.  
           [0006]    As the current intensity rises between a source zone and a drain zone, the temperature of the semiconductor body increases and the mobility of the charge carriers in the channel zone decreases. This effect results in that trench transistor cells can be electrically connected in parallel in a simple manner. If, by way of example, in the activated state, initially a somewhat higher current flows through one of the trench transistor cells connected in parallel, then this leads to a relatively greater increase in temperature in the trench transistor cell. On account of the increased temperature, the mobility of the charge carriers in the channel is reduced and the trench transistor cell thus acquires a higher impedance. Consequently, the current is distributed between cooler trench transistor cells connected in parallel.  
           [0007]    In the semiconductor substrate of a trench MOS power transistor, a trench transistor cell is usually fashioned along an elongate trench or defined by a polygon-like trench. It is possible, then, for a plurality of the trenches to be disposed one beside the other to form an active cell array, the gate electrodes in adjacent trenches also being able to be electrically connected to one another via transverse trenches.  
           [0008]    The maximum current intensity which can be switched by a trench MOS power transistor is determined by the drain-source resistance (R DS(ON) ) of the trench transistor cells connected in parallel. The minimum switching time and the maximum operating frequency are essentially determined by the gate parameters of input resistance (R G ), gate charge (Q G ) and input capacitance (C ISS ).  
           [0009]    The input resistance is determined substantially by the resistance of the gate electrodes in the trenches and to a small extent by the resistance of the connecting lines between a gate terminal of the trench MOS power transistor and the gate electrodes in the trenches. The input capacitance C ISS  results from addition of the gate-source capacitance (C GS ) and the gate-drain capacitance (C GD ).  
           [0010]    International Patent Disclosure WO 98/02925 discloses a MOS power transistor having a gate electrode disposed above the substrate surface in a planar manner, in which the switching times and switching losses are reduced by reduction of the gate-drain capacitance C GD . In this case, a field electrode that is electrically conductively connected to the source terminal of the MOS power transistor is disposed in each case beside the gate electrode. The field electrode shields the electrical charge on the gate electrode from the drift zone and reduces the area at which the gate electrodes and the drift zone are opposite one another.  
           [0011]    A further concept for reducing the gate-drain capacitance is disclosed in U.S. Pat. No. 5,283,201. In this case, in a trench transistor cell having a gate electrode disposed in a trench in the semiconductor substrate, an auxiliary electrode made of the material of the gate electrode is disposed below the gate electrode and is electrically insulated from the latter.  
           [0012]    Generally, for MOS power transistors the emphasis is on seeking to further reduce the gate-drain capacitance C GD  in order to improve the functionality and in order to extend the range of application of MOS power transistors, for instance for higher operating frequencies.  
         SUMMARY OF THE INVENTION  
         [0013]    It is accordingly an object of the invention to provide a transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in the case of which a gate-drain capacitance of the transistor configuration is reduced compared with conventional transistor configurations, with the functionality being preserved at the same time.  
           [0014]    With the foregoing and other objects in view there is provided, in accordance with the invention, a transistor configuration. The transistor configuration has at least one gate terminal, at least one source terminal, at least one drain terminal, a semiconductor substrate having a substrate surface, and at least one active cell array formed in the semiconductor substrate. The semiconductor substrate has at least one trench within the active cell array. An edge region adjoins the active cell array and the trench extends into the edge region. At least one trench transistor cell is formed along the trench. At least two electrode structures are disposed within the trench and extend along the trench. Metallizations are disposed substantially above the substrate surface of the semiconductor substrate. At least one of the two electrode structures is electrically conductively connected to one of the metallizations in the edge region.  
           [0015]    Such a transistor configuration of the type according to the invention connects at least two electrode structures disposed one beside the other and/or one above the other in the trench of the trench transistor cell to terminal metallizations of the transistor configuration in a manner that is particularly advantageous since it saves space and exhibits topologic convenience. As a result, the functionality is maintained for the same extent (chip area) of the transistor configuration.  
           [0016]    The transistor configuration according to the invention is preferably fashioned as a trench MOS power transistor with a field electrode. In this case, a plurality of trench transistor cells are disposed and electrically connected in parallel in a respective cell array. In the trenches of the trench transistor cells, a field electrode is in each case disposed below or beside the gate electrode. The trench MOS power transistor has a source metallization connected to a source terminal, and a gate metallization connected to a gate terminal, the gate metallization being electrically conductively connected to the upper electrode structures (gate electrodes).  
           [0017]    The configuration and fashioning of the electrical connections in each case between the gate metallization and the gate electrode, and between the lower electrode structure (field electrode) and a field metallization, enable a highly advantageous configuration and fashioning of the source and gate metallizations above a substrate surface of the semiconductor substrate.  
           [0018]    Thus, the source metallization is advantageously disposed at least in parts above the active cell array and is surrounded at least in sections by the gate metallization.  
           [0019]    As a result, first, the contact connection of source zones disposed in the cell array has very low impedance, and, second, patterning of the source metallization is unnecessary. Such patterning of the source metallization, which has a thickness of a number of micrometers, is complicated in terms of production technology since, for instance during a wet etching, the source metallization is undercut approximately in the order of magnitude of the thickness of the source metallization.  
           [0020]    The electrical connections for instance between the gate or field electrodes disposed one above the other and the corresponding metallizations can be realized in various ways, for instance by plated-through holes from the metallization to the electrode structure respectively provided in the trench. Such configurations are advantageous when the dimensions of the trenches and of the plated-through holes permit the plated-through holes to be positioned relative to the trenches without difficulty.  
           [0021]    In an advantageous fashioning of the trench MOS power transistor according to the invention, the two electrode structures in the trench are directly connected via plated-through holes to corresponding metallizations that are preferably disposed in the edge region section by section above the trenches. By virtue of the plated-through holes to the field electrode, the gate electrode disposed above the latter is interrupted in the regions of the plated-through holes in the trench. The interruptions are bridged by a suitable configuration of transverse trenches by which at least the gate electrodes of adjacent trench transistor cells are electrically conductively connected. In this way, advantageously, there is no need for an additional photolithographic process for shaping a field structure, for instance.  
           [0022]    In a further embodiment of the trench MOS power transistor according to the invention, the gate electrode is electrically conductively connected to the gate metallization via a gate structure above the substrate surface and the field electrode is electrically conductively connected to the field metallization directly via plated-through holes. Transverse trenches that electrically conductively connect the gate electrodes of adjacent trench transistor cells are again necessary in this case.  
           [0023]    In this case, the gate structure and the gate electrodes contain the same material and emerge from the same process step in terms of production technology, in this case, for example after the deposition of the material of the gate electrode, before the material is etched back to at least below the substrate surface, for the purpose of shaping the gate electrode, all that is necessary is a non-critical, etching-resistant masking of the gate structure.  
           [0024]    In a further advantageous fashioning, the trench MOS power transistor according to the invention has a field structure above the substrate surface, which imparts an electrically conductive connection between the field electrode and the field metallization, and also a gate metallization, which extends section by section, for instance in the edge region, above the trenches, and also plated-through holes which electrically conductively connect the gate metallization directly to the gate electrodes in the trenches. This obviates a masking of gate structures before the etching back of the deposited material of the gate electrode.  
           [0025]    Furthermore, a fashioning of the field electrodes in the trenches made of a deposited material of the field electrode (field polysilicon) can be realized in a single controllable etching-back step.  
           [0026]    To that end, first the field structures that emerge from the field polysilicon are covered and the field polysilicon is subsequently etched back. An uncovering of a field oxide that covers the substrate outside the trenches is detected during the etching back of the field polysilicon. The further etching process can be synchronized to the detected signal. The remaining etching duration and etching rate yield a filling height up to which the field electrodes fashioned in this way fill the trenches. In this way, the filling height can be adjusted to a channel zone/drift zone junction that is fashioned later in the semiconductor substrate. In the case of configurations in which the field electrode is electrically connected by through-plating, by contrast, the field polysilicon is made to recede to just below the substrate surface in a first step and is then covered in regions provided for contact connection. In the active cell array, the field electrodes are etched back further. In this case, a signal by which the etching process can be synchronized cannot be generated in a simple manner.  
           [0027]    In accordance with a particularly preferred embodiment of the invention, the gate electrode is fashioned in a shortened manner in the edge region in the trench, so that the trenches are only filled by the field electrode at their ends. In this case, the gate structure is disposed in such a way that the gate electrode, which is contact-connected toward the cell array, is electrically conductively connected to a gate metallization which is remote from the cell array, and the field electrode, which is contact-connected in a manner remote from the cell array, is electrically conductively connected to a field metallization oriented toward the cell array.  
           [0028]    In a preferred manner, the gate structure and the field structures on the substrate surface are electrically insulated from one another and from the semiconductor substrate by insulator layers and are fashioned one beside the other in a common layer plane. This results in an advantageous planar construction of the gate and field structures, and in non-critical field conditions.  
           [0029]    Furthermore, in a preferred manner, the gate structure is disposed at least in sections above the field structures, the gate structure being electrically insulated from this by an intermediate oxide layer. Such a configuration yields, as a result of the non-interrupted extensive gate structure, a low non-reactive resistance in the connection between the gate terminal and the gate electrodes. Furthermore, the field structures disposed between the drain potential and the gate structure advantageously shield the drift layer from the gate structure.  
           [0030]    In a further preferred embodiment, the transistor configuration according to the invention has an additional electrical terminal which is electrically conductively connected to the field metallization and at which a further potential can be fed to the transistor configuration besides the source, gate and drain potentials and by which the field electrode can be controlled particularly effectively. As an alternative to this, the field metallization is connected to a circuit section of the trench MOS power transistor that can control such a potential.  
           [0031]    In a particularly preferred embodiment, the field metallization is identical to the source metallization or is electrically conductively connected thereto. By controlling the potential of the field electrode with the source potential, the field electrode can be effectively controlled in a very simple and uncomplicated manner.  
           [0032]    In the text above, the invention has been explained in each case using the example of a trench transistor cell. The invention can furthermore be extended in an obvious manner to IGBTs and those with a drain-up structure. Furthermore, the invention can be applied in each case to normally on and normally off p-channel and n-channel transistor cells.  
           [0033]    Other features which are considered as characteristic for the invention are set forth in the appended claims.  
           [0034]    Although the invention is illustrated and described herein as embodied in a transistor configuration with a structure for making electrical contact with electrodes of a trench transistor cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.  
           [0035]    The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0036]    [0036]FIG. 1A is a simplified diagrammatic plan view of a detail of trench MOS power transistor in accordance with a first exemplary embodiment of the invention;  
         [0037]    [0037]FIG. 1B is a diagrammatic cross-sectional view of the trench MOS power transistor taken along the line IB-IB shown in FIG. 1A;  
         [0038]    [0038]FIG. 2 is a simplified diagrammatic cross-sectional view through a trench transistor cell of a simple type according to the prior art;  
         [0039]    [0039]FIG. 3A is a simplified diagrammatic plan view of a detail of the trench MOS power transistor in accordance with a second exemplary embodiment according to the invention; and  
         [0040]    [0040]FIG. 3B is a sectional view of the trench MOS power transistor taken along the line IIIB-IIIB shown in FIG. 3A. 
     
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0041]    Referring now to the figures of the drawing in detail and first, particularly, to FIG. 2 thereof, there is shown a cross-sectional view of an individual conventional trench transistor cell  3  of a normally off n-channel trench MOS power transistor  1 . In this example, a heavily n-doped (n ++ -doped) drain zone  223  is formed in a semiconductor substrate  6 . Furthermore, a weakly n-doped (n-doped) drift zone  224 , which emerged from an epitaxial process, is disposed on the drain zone  223 .  
         [0042]    The drift zone  224  is adjoined by a first p-doped diffusion region and a second, n ++ -doped diffusion region. In this case, the p-doped diffusion regions form channel zones  203  and the n ++ -doped diffusion regions form source zones  213  of the trench transistor cell  3 . A trench  9  is provided in the diffusion regions. A trench wall is lined with a gate oxide  14  that electrically insulates a trench interior from the surrounding semiconductor substrate  6 . Moreover, the trench  9  is filled with a conductive polysilicon that forms a gate electrode  10 .  
         [0043]    Above the trench  9 , a gate metallization is disposed in an edge region adjoining the gate electrode  10  on the substrate surface  7 . A source metallization  21  is applied on the substrate surface  7  and makes electrical contact with the source zones  213  and the channel zones  203 . The source metallization  21  and the gate metallization are electrically insulated from one another and from the semiconductor substrate  6  by an intermediate oxide layer  16 . On a substrate rear side  8  opposite to the substrate surface  7  of the semiconductor substrate  6 , a drain metallization  22  is disposed adjoining the drain zone  223  of the semiconductor substrate  6 .  
         [0044]    In the voltage-free state, the conductive source zones  213  are electrically insulated from the drain zone  223  by the p-doped channel zones  203 . If the gate electrode  10  is biased with a positive potential, then minority carriers, in this case electrons, accumulate in the channel zone  203 , directly adjoining the gate oxide  14 .  
         [0045]    As the positive bias of the gate electrode  10  rises, an n-conducting channel  5  forms in the originally p-conducting channel zone  203  (inversion).  
         [0046]    As the current intensity rises between the source zone  213  and the drain zone  223 , the temperature of the semiconductor body increases and the mobility of the charge carriers in the channel zone  203  decreases. This effect results in that trench transistor cells can be electrically connected in parallel in a simple manner. If, by way of example, in the activated state, initially a somewhat higher current flows through one of the trench transistor cells connected in parallel, then this leads to a relatively greater increase in temperature in the trench transistor cell. On account of the increased temperature, the mobility of the charge carriers in the channel is reduced and the trench transistor cell thus acquires a higher impedance. Consequently, the current is distributed between cooler trench transistor cells connected in parallel.  
         [0047]    In the semiconductor substrate of the trench MOS power transistor, the trench transistor cell is usually fashioned along an elongate trench or defined by a polygon-like trench. In the manner described above, it is possible, then, for a plurality of the trenches to be disposed one beside the other to form an active cell array, the gate electrodes in adjacent trenches also being able to be electrically connected to one another via transverse trenches.  
         [0048]    The maximum current intensity which can be switched by a trench MOS power transistor is determined by the drain-source resistance (R DS(ON) ) of the trench transistor cells connected in parallel. The minimum switching time and the maximum operating frequency are essentially determined by the gate parameters of input resistance (R G ), gate charge (Q G ) and input capacitance (C ISS ).  
         [0049]    The input resistance is determined substantially by the resistance of the gate electrodes in the trenches and to a small extent by the resistance of the connecting lines between a gate terminal of the trench MOS power transistor and the gate electrodes in the trenches. The input capacitance (C ISS ) results from addition of the gate-source capacitance (C GS ) and the gate-drain capacitance (C GD ).  
         [0050]    A configuration for trench transistor cells as is known from FIG. 2 has a high capacitance between the gate electrodes  10  and the drift zone  224  assigned to the drain terminal. It results from the fact that the drift zone  224  and the gate electrodes  10  are opposite one another at the thin gate oxide  14 .  
         [0051]    [0051]FIG. 1A is a plan view illustrating a detail of a trench MOS power transistor according to the invention and continues from the prior art as illustrate in FIG. 2. In this case, an active cell array  2  is adjoined by an edge region  4 . The active cell array  2  has a plurality of the trench transistor cells  3  disposed along parallel trenches  9 .  
         [0052]    The trenches  9  are lengthened into the edge region  4 , in this example the electrode structures  10 ,  11  disposed in the trenches  9  are electrically conductively connected to one another by transverse trenches  91 . During the fashioning of the connections between the trenches  9  and the transverse trenches  91 , crossovers are avoided in a known manner and T structures, which are less critical in terms of process technology, are realized in place thereof.  
         [0053]    In the edge region  4 , the trenches  9  have first opened sections  212 , in which the upper electrode structure  10  (gate electrode) is made to recede in the trenches  9  and in which the lower electrode structure  11  (field electrode) fills the trenches  9  up to the substrate surface  7  without insulator layers bearing on it.  
         [0054]    Furthermore, the trenches  9  have, in the edge region  4 , second opened sections  202 , in which the gate electrode  10  is in each case present up to the substrate surface  7  without an insulator layer bearing on it.  
         [0055]    A field structure, fashioned as a source structure  211  in this example, made of the same conductive semiconductor material as the field electrode  11  bears on the first opened sections  212  of the trenches  9 . The source structure  211  is thus electrically conductively connected to the field electrodes  11 . In this case, the source structure  211  and the field electrode  11  emerge from a single deposited layer of the conductive semiconductor material, for instance by etching back.  
         [0056]    A gate structure  201  extends over the second opened sections  202 . The respective gate electrodes  10  are thus electrically conductively connected to the gate structure  201 . The gate structure  201  and the gate electrode  10  also emerge from a single deposited layer of the conductive semiconductor material, for instance by etching back. The gate structure  201  furthermore extends over the source structure  211 , the gate structure  201  and the source structure  211  are electrically insulated from one another by an insulator layer  16 . The intermediate oxide layer  16  bears on the gate structure  201  at least in sections.  
         [0057]    Disposed above sections of the gate structure  201  is a gate metallization  20  that is electrically conductively connected to the gate structure  201  by plated-through holes  31  through the intermediate oxide layer  16 .  
         [0058]    A field metallization, fashioned as a source metallization  21  in this example, bears in the region of the active cell array  2  and in sections of the edge region  4 . The source metallization  21  is connected to source zones of the trench transistor cells  3  via plated-through holes  33  in the active cell array  2 . In the edge region  4 , the source metallization  21  is electrically conductively connected to the source structure  211  via plated-through holes  32 .  
         [0059]    [0059]FIG. 1B shows a diagrammatic cross-sectional view taken along the line IB-IB shown in FIG. 1A-of the trench MOS power transistor  1 .  
         [0060]    In comparison with FIG. 1A, FIG. 1B additionally reveals a field oxide layer  15 , which electrically insulates the semiconductor substrate  6  from the structures  201 ,  211  disposed above the substrate surface  7 . Furthermore, FIG. 1B shows the vertical configuration of the source structure  211 , of the gate structure  201  bearing in sections on the source structure  211 , of the metallizations  20 ,  21 , and of the insulator layers  15 ,  16 . In this case, the illustration of the insulator layers  15 ,  16 , in particular, is greatly simplified. Thus, each insulator layer  15 ,  16  can be embodied as a multilayer system. The fashioning of the insulator layers  15 ,  16  at junctions is dependent on the type of fabrication, for instance a deposition or an oxidation. Equally, the gate and field electrodes  10 ,  11 , and also the gate and field structures  201 ,  211  can be reinforced with silicide or metal or be composed entirely of silicide, metal or other highly conductive materials.  
         [0061]    [0061]FIG. 3A illustrates a plan view of a second embodiment of a detail of the trench MOS power transistor.  
         [0062]    In contrast to the embodiment illustrated in FIGS. 1A and 1B, the gate structure  201  is disposed exclusively beside the source structure  211 . A mutually offset configuration of individual source structures  211  results in a mesh-like fashioning of the gate structure  201  in the region of the source structures  211 . The mesh-like fashioning of the gate structure  201  advantageously brings about a uniform potential distribution in the gate structure  201  during operation of the trench MOS power transistor.  
         [0063]    [0063]FIG. 3B shows a diagrammatic cross-sectional view through the detail—illustrated in FIG. 3A—of the trench MOS power transistor  1  taken along the line IIIB-IIIB shown in FIG. 3A.  
         [0064]    Accordingly, the gate structures  201  and the source structures  211  are disposed one beside the other above the substrate surface  7  of the semiconductor substrate  6  thereby producing an advantageous planar topography of the field structures  201 ,  211  and of the metallizations  20 ,  21 .