Abstract:
A smart protection circuit to prevent possible circuit malfunction or damage due to sudden power source voltage fluctuation is introduced. In case of quick and large voltage fluctuation in power supply, a control signal is activated to stop power transistor switching. When power supply is stable at a lower or higher operating voltage, the switching circuit is able to return to normal operation.

Description:
BACKGROUND OF THE INVENTION 
   The present invention relates to an audio power amplifier and, more particularly, to a protection circuit for protecting a switching circuit from possible malfunction or damage due to sudden power source voltage fluctuation. 
   Class D audio power amplifier is one type of switching circuit. Therefore, Class D audio power amplifier is chosen for illustration purpose. Most of the audio power amplifiers in the market are based on Class AB amplifier. This architecture offers very good total harmonic distortion plus noise (THD+N) performance, with fairly low quiescent current. However, the Class AB push-pull amplifiers are very inefficient and can only achieve an efficiency of about 60%, which results in not only power loss, but also additional bulky heatsink attached to the power amplifiers. 
   One major advantage of Class D amplifiers is the efficiency, which could reach above 90%. The high efficiency is achieved by full signal swing at power transistors. A typical Class D amplifier circuit  1000  is shown in  FIG. 1 , which includes a reference (herein after also indicated as RF) circuit  1020 , a pulse width modulator  1010 , a level shifter and driver stage  1030 , a first MOSFET switch M 10 , and a second MOSFET switch M 20 . 
   In the actual usage of Class D amplifier circuit  1000 , the power source voltage Vcc may fluctuate suddenly and abnormally. Such sudden voltage fluctuation is due to, for example, transformer malfunction on a printed circuit board (PCB), power supply trace shorting to ground on PCB or other scenarios. If such sudden voltage fluctuation should occur, Class D amplifier circuit  1000  is damaged or performs abnormal operation. 
   To prevent Class D amplifier circuit  1000  from possible damaging or malfunction due to sudden power source voltage Vcc fluctuation, a protection circuit is necessary. 
   The following prior art references are known.
     1) Japanese Utility Model Laid-Open Publication No. H5-39095 Published May 25, 1993   2) Japanese Patent Laid-Open Publication No. H4-108204 Published Apr. 9, 1992   3) Japanese Patent Laid-Open Publication No. S58-81311 Published May 16, 1983   

   SUMMARY OF THE INVENTION 
   The purpose of the present invention is to introduce an audio power amplifier with a protection circuit for sudden power source voltage fluctuation. 
   According to the present invention, an audio power amplifier comprises: a power source terminal which receives a power source voltage; a first and second switching transistors connected in series to said power source terminal, an audio signal passage which sends a pulse width modulation drive signal to said first and second switching transistors; a reference circuit which is connected to the power source terminal and generates a predetermined reference voltage RF; a capacitor which stores the reference voltage RF; a source voltage detection circuit which is connected to the power source terminal and generates a predetermined detected voltage DE which is proportional to the power source voltage; a comparator which compares the reference voltage RF and the detected voltage DE, and generates a fluctuation signal when the detected voltage DE falls below the reference voltage RF; and a disabling element which operates in response to the fluctuation signal to stop the operation of said first and second switching transistors. 
   As apparent from the above, the audio power amplifier according to the present invention comprises a source voltage detection circuit and a disabling element. The source voltage detection circuit is designed to detect, not only a sudden voltage jump, but also a sudden voltage drop of power supply. Upon detection of sudden voltage drop at power supply, a fluctuation signal is generated by the source voltage detection circuit. After receiving the fluctuation signal SD, the disabling element stops output power transistors from switching. When the power supply at the power source terminal is stable for a predetermined period, the fluctuation signal SD is deactivated by the detection circuit. The disabling element therefore allows output power transistors to resume switching and normal operation continues. 
   EFFECT OF THE INVENTION 
   According to the present invention, an audio power amplifier which can detect, not only a sudden voltage jump, but also a sudden voltage drop of power supply can be achieved with a simple structure by adding a source voltage detection circuit and a disabling element. 
   According to the present invention, a sudden voltage drop can be detected with a high accuracy. 
   According to the present invention, when the sudden voltage drop is detected, the disabling element disables the first and second switching transistors to operate, enabling no sound output. Thus, the user will not be annoyed by the unpleasant fluctuating sound. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing an audio power amplifier according to the prior art; 
       FIG. 2  is a block diagram showing an audio power amplifier according to a first embodiment of the present invention; 
       FIG. 3  is a chart showing waveforms obtained at major points in the block diagram of  FIG. 2 ; 
       FIG. 4  is a block diagram showing an audio power amplifier according to a second embodiment of the present invention; 
       FIG. 5  is a chart showing waveforms obtained at major points in the block diagram of  FIG. 4 ; 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description explains the best mode embodiment of the present invention. 
   First Embodiment 
   Referring to  FIG. 2 , a first embodiment of an audio power amplifier  100 , which is a Class D amplifier, is shown. The audio power amplifier  100  comprises a power source terminal for receiving a power source voltage Vcc, a reference (RF) circuit  102 , a pulse width modulator  101 , a level shifter and driver stage  103 , and first and second switching transistors, such as a first MOSFET switch M 1 , and a second MOSFET switch M 2 . The pulse width modulator  101  and the level shifter and driver stage  103  define an audio signal passage for sending a pulse width modulation drive signal (PWM drive signal) to the first and second MOSFET switches M 1  and M 2 . 
   RF circuit  102  comprises a zener diode Z 1 , a resistor R 3 , a PMOS M 4  and resistors R 1  and R 5 . RF circuit  102  generates a reference voltage RF at a junction between resistors R 5  and R 1 . Although two resistors R 1  and R 5  are shown as connected directly in series, resistor R 5  can be connected between the power source terminal and the PMOS M 4 . The junction is further connected to a capacitor CRF for storing the reference voltage RF. The reference voltage RF is used as a stable reference voltage in various circuits (not shown). 
   According to the first embodiment, a fluctuation detection circuit  113  and a switching transistor, such as a third MOSFET switch M 3 , are further provided. The fluctuation detection circuit  113  detects a sudden power source voltage fluctuation, such as voltage drop of a power source voltage Vcc. Here, only a power source terminal for receiving the power source voltage Vcc is shown. 
   The MOSFET switches M 1 , M 2  and M 3  are provided in series between the power source voltage Vcc and the ground. The MOSFET switch M 3  is located next to the voltage source Vcc, but can be located next to the ground, or between the MOSFETs M 1  and M 2 . 
   The fluctuation detection circuit  113  comprises a source voltage detection circuit  105  and a comparator  104 . The source voltage detection circuit  105  comprises a zener diode Z 2 , a resistor R 4 , a PMOS M 5 , and resistors R 2  and R 6 . The source voltage detection circuit  113  generates a detected voltage DE at a junction between resistors R 2  and R 6 . The detected voltage DE is proportional to the power source voltage Vcc, as apparent from  FIG. 3  waveforms (A) and (B). Although two resistors R 2  and R 6  are shown as connected directly in series, resistor R 6  can be connected between the power source terminal and the PMOS M 5 . Furthermore, it is possible to omit resistors R 5  and R 6 . 
   It is to be noted that the first pair of zener diode Z 1  and resistor R 3  and the second pair of zener diode Z 2  and resistor R 4  have the same characteristics. Thus, the second pair (or the first pair) can be omitted. In such a case, the gate of PMOS M 4  and the gate of PMOS M 5  are commonly connected. 
   It is to be noted that resistors R 11  R 2 , R 5  and R 6  are so selected that the reference voltage RF and the detected voltage DE are not the same. According to the first embodiment, the relationship between the voltages RF and DE is such that DE is greater than RF (DE&gt;RF). 
   Comparator  104  compares the voltages RF and DE and generates a control signal SD based on the comparison result. Under a normal operating condition, that is when DE&gt;RF, comparator  104  generates the control signal SD of a LOW level to allow the MOSFET switch M 3  in ON state. 
   An application circuit provided in association with the first MOSFET switch M 1  and second MOSFET switch M 2  includes an output filter  106 , a bootstrap capacitor C 1 , a decoupling capacitor C 2 , and a loudspeaker  110 . 
   The operation of the audio power amplifier  100  is described next with reference to  FIGS. 2 and 3 . 
   In  FIG. 3 , before time T 1 , the power source voltage Vcc is stable. During this time, the voltages RF and DE are such that DE is greater than RF. Thus, comparator  104  generates the control signal SD of a LOW level. Thus, MOSFET switch M 3  is maintained in ON state to provide the power source voltage Vcc to MOSFET switches M 1  and M 2 . Under this condition the pulse width modulator  101  generates the signal PWM_OUT which is applied to the level shifter and driver stage  103 . The level shifter and driver stage  103  generates PWM drive signal to MOSFETs M 1  and M 2 . Thus, MOSFETs M 1  and M 2  produces output PWM signal which is applied to the output filter  106 . Then, by the signal from output filter  106 , the speaker  110  produces sound. 
   In  FIG. 3 , at time T 1 , the power source voltage Vcc starts to drop due to transformer malfunction on PCB (printed circuit board) or to any other reasons. The detected voltage DE drops similarly to the supply voltage Vcc, but the reference voltage RF maintains its voltage by the charge stored in capacitor CRF. 
   Then, at time T 2 , when the detected voltage DE falls below the reference voltage RF, comparator  104  starts to generate the control signal SD of a HIGH level. Thus, MOSFET switch M 3  is turned to OFF state to cut off the power source voltage Vcc to MOSFET switches M 1  and M 2 . Under this condition the pulse width modulator  101  generates the signal PWM_OUT which is applied to the level shifter and driver stage  103 . The level shifter and driver stage  103  generates PWM drive signal to MOSFETs M 1  and M 2 . However, MOSFETs M 1  and M 2  are not provided with the supply voltage Vcc. Thus, the speaker  110  stops producing sound. 
   Then, when the power source voltage Vcc recovers, the detected voltage DE also recovers. At time T 3 , when the detected voltage DE increases above the reference voltage RF, comparator  104  again starts to generate the control signal SD of a LOW level. Thus, MOSFET switch M 3  is turned back to ON state to restart the supply of the power source voltage Vcc to MOSFET switches M 1  and M 2 . Thus, the speaker  110  restarts to produce sound. 
   The above operation is directed to a case when the power source voltage Vcc drops abnormally below a predetermined low limit voltage at a dropping speed faster than a predetermined value. Such a predetermined low limit voltage can be defined by the setting of the voltages RF and DE, i.e., by the setting of resistors R 1 , R 2 , R 5  and R 6 . 
   Thus, it is understood that the control signal SD of a HIGH level can be considered as a fluctuation signal indicating that the power source voltage Vcc drops below a predetermined low limit. 
   According to the first embodiment, the abnormal voltage drop can be detected by the fluctuation detection circuit  113 , and when abnormal voltage drop is detected, a disabling element, which is MOSFET switch M 3  is operated to immediately stop the operation of MOSFETs M 1  and M 2  by cutting off the power supply from the power source voltage Vcc. Thus, the speaker  110  will not produce any unpleasant on and off intermittent sound, particularly when the abnormal voltage drop occurs. 
   Second Embodiment 
   Referring to  FIG. 4 , a second embodiment of an audio power amplifier  100 , which is a Class D amplifier, is shown. When compared with the first embodiment shown in  FIG. 2 , the audio power amplifier  100  of the second embodiment does not have the MOSFET M 3 , but instead a control block  111  is inserted between the pulse width modulator  101  and the level shifter and driver stage  103 . 
   It is to be noted that the control block  111  can be inserted in upstream of the pulse width modulator  101 , or in downstream of the level shifter and driver stage  103 . In other words, according to the second embodiment, the control block  111  is inserted someplace in the audio signal passage. 
   According to the second embodiment, the control block  111  comprises an inverter  112  and an AND gate  114 . The inverter  112  is connected to the comparator  104  to receive the control signal SD. The output of the inverter  112  is connected to one input of the AND gate  114 . The other input of the AND gate  114  is connected to the output of the pulse width modulator  101  to receive the signal PWM_OUT. The output of the AND gate  114  is connected to the level shifter and driver stage  103 . It is to be noted that the inverter  112  can be omitted when the comparator  104  produces the control signal SD in opposite phase such that the LOW level and HIGH level are in opposite phase. 
   In operation, at time T 2  shown in  FIG. 5 , the control signal SD changes from LOW level to HIGH level in the same manner as that described in the first embodiment. While the control signal SD of LOW level was present (i.e., before time T 2 ), inverter  112  produces a HIGH level signal to AND gate  114 . Thus, AND gate  114  is enabled to allow the signal PWM_OUT to pass therethrough. Thus, the sound is produced from the speaker  110 . Then, when the control signal SD of HIGH level is produced (i.e., between time T 2  and T 3 ), inverter  112  produces a LOW level signal to AND gate  114 . Thus AND gate  114  is disabled to block the signal PWM_OUT. Thus, the sound will not be produced from the speaker  110 . 
   The above is a case when the power source voltage Vcc drops abnormally below a predetermined low limit voltage. 
   According to the second embodiment, the abnormal voltage drop can be detected by the fluctuation detection circuit  113 , and when such abnormal voltage drop is detected, a disabling element, which is control block  111  is operated to immediately stop the operation of MOSFETs M 1  and M 2  by cutting off the PWM drive signal to MOSFETs M 1  and M 2 . Thus, the speaker  110  will not produce any unpleasant on and off intermittent sound, particularly when the abnormal voltage drop occurs. 
   Having described the above embodiment of the invention, various alternations, modifications or improvement could be made by those skilled in the art. Such alternations, modifications or improvement are intended to be within the spirit and scope of this invention. The above description is by ways of example only, and is not intended as limiting. The invention is only limited as defined in the following claims.