Abstract:
The present disclosure relates to a method for routing data between a sending unit and a receiving unit linked by a network in a processing system comprising several units, the method comprising steps of routing data in the network between the sending unit and the receiving unit, and of applying a process to the routed data, the process comprising several steps which are applied to the data by different units in the network receiving the data, to use latency times in data routing.

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to data processing systems comprising several elements communicating between themselves through an interconnected network. The present disclosure relates in particular to SoC (System-on-Chip) systems, integrated into a semiconductor chip. 
     2. Description of the Related Art 
     Data transmission in a network linking several elements of a processing system, suffers delays due to intrinsic latencies related to the architecture of the network. The sources of such latency are generally found in the routing arrays, the possible format conversion processes applied to the data, and the time required for data to transit in buffer or temporary storage memories. The data sent may also have to undergo specific processes before being received by a receiving element. 
       FIG. 1  schematically represents a processing system comprising a transmission network TN, initiation elements INIT 1 , INIT 2  capable of initiating a communication in the network, receiving elements TGT 1 , TGT 2  capable of receiving messages from the network, and possibly specific processes PRCA, PRCB likely to be applied to the messages before they are sent to the receiving elements. The global latency for message transmission is equal to the latency Ln of the network increased by the latency Lpi introduced by the process PRCA, PRCB applied to the message. 
     In a System-on-Chip (SoC), the interconnected network TN is generally a bus, for example of STBus or AMBA type, etc. The initiation elements INIT 1 , INIT 2  are elements which can be master on the bus and initiate transactions towards the receivers. The initiation elements are for example processing units (CPU), and DMA (Direct Memory Access) control units. The receiving elements TGT 1 , TGT 2  are slave elements which can only respond to requests sent by the initiation elements. The receiving elements are for example an external memory of the system and an acceleration unit. 
     Furthermore, it is often necessary to protect the external memory of a system against attacks aiming to read or change its content. To counter this type of attack, one well-known method involves applying a ciphering function to the data before writing it in the external memory, and a reverse function to the data read in the memory. 
     Thus,  FIG. 2  schematically represents a System-on-Chip PS connected to an external memory EMEM. The system PS comprises initiation units such as a processing unit CPU and a DMA control unit DCU, a bus infrastructure BIS, and a ciphering/deciphering interface unit EDU enabling the data stored in the external memory EMEM to be secured. The bus infrastructure BIS introduces a latency Ln into the sending of requests for accessing the memory EMEM sent by the initiation units CPU. The unit EDU introduces additional latency Lp in the processing of these requests. It shall be noted that the initiation units can also introduce latencies corresponding for example to transit times in a cache memory or a buffer memory. The time needed to access the external memory which can be quite long is also a latency Lm which increases the duration of the process of ciphering or deciphering the data written or read in the memory EMEM. 
     BRIEF SUMMARY 
     It is desirable to reduce the global latency in a data processing system comprising several units interconnected by a data transmission network. For this purpose, one embodiment of the present disclosure takes advantage of the different latencies to perform repetitive and systematic processes on the data sent. 
     One embodiment provides a method for routing data between a sending unit and a receiving unit linked by a network in a processing system comprising several units, the method comprising steps of routing data in the network between the sending unit and the receiving unit, and applying a process to the routed data. According to one embodiment, the process comprises several steps which are applied to the data by different units of the network receiving the data, to use latency times in data routing. 
     According to one embodiment, a piece of information which can be used to determine the progress of the process is sent in association with the data sent in the network. 
     According to one embodiment, the process applied to the data sent is a ciphering or deciphering process depending on the identity of the unit sending or receiving the data sent, or a data formatting process. 
     According to one embodiment, the process applied to the data comprises several iterations. 
     According to one embodiment, the data is sent in the network in association with a piece of information which can be used to determine the number of iterations executed or still to be executed on the data sent. 
     According to one embodiment, the data is sent in the network in frames containing the information used to determine the number of iterations still to be executed on the data sent. 
     According to one embodiment, the number of iterations executed by each unit in the system is fixed. 
     According to one embodiment, the number of iterations executed by a unit in the system is adapted to a time for data to transit in the unit. 
     According to one embodiment, there is also provided a system comprising several networked units, the system being configured for routing data between a sending unit and a receiving unit and for applying a process to the data. According to one embodiment, the process comprises several steps, at least some of the units in the network being configured to apply certain steps in the process to the data they receive, to use latency times in data routing. 
     According to one embodiment, the system is configured for sending in association with the data sent in the network, a piece of information which can be used to determine the progress of the process. 
     According to one embodiment, the process applied to the data sent is a ciphering or deciphering process depending on the identity of the unit sending or receiving the data sent, or a data formatting process. 
     According to one embodiment, the process applied to the data comprises several iterations. 
     According to one embodiment, the data is sent into the network in association with a piece of information which can be used to determine the number of iterations executed or still to be executed on the data sent. 
     According to one embodiment, the data is sent in the network in frames containing the information used to determine the number of iterations still to be executed on the data sent. 
     According to one embodiment, the number of iterations executed by each unit in the system is fixed. 
     According to one embodiment, the number of iterations executed by a unit in the system is adapted to a time for data to transit in the unit. 
     According to one embodiment, the network is a local bus interconnecting the units in the system. 
     According to one embodiment, the system comprises several sub-systems networked through routers forming nodes of a network, each sub-system comprising a network interface unit connected to one of the routers, the interface units and the routers each comprising a shared processing unit for executing one or more iterations of a process to be applied to the data sent by the network. 
     According to one embodiment, the system is produced on a semiconductor chip. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       Examples of embodiments of the present disclosure will be described below in relation with, but not limited to, the following figures: 
         FIG. 1  described previously schematically represents a processing system, 
         FIG. 2  described previously schematically represents a System on chip, 
         FIG. 3  schematically represents a processing system according to one embodiment, 
         FIG. 4  schematically represents a processing system according to another embodiment, 
         FIG. 5  schematically represents a processing system according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 3  represents a processing system PS 1  comprising initiation units TU 1 , TU 2  capable of sending requests for accessing data and receiving units RU 1 , RU 2  receiving requests for accessing data. The units TU 1 , TU 2 , RU 1  and RU 2  are connected through interface units INT 1 , INT 2 , INT 4 , INT 5  to a bus ADB controlled by a bus control unit BCTL. The receiving units RU 1 , RU 2  can be external or internal to the system PS 1 . The bus ADB sends data between the initiation units TU 1 , TU 2  and the receiving units RU 1 , RU 2 . Before reaching the units RU 1 , RU 2 , the data undergoes a process, such as a conversion or ciphering process, for example to be protected if it is sent to the external environment of the processing system PS 1 . Conversely, before reaching the initiation units TU 1 , TU 2 , the data from the units RU 1 , RU 2  undergoes a process enabling it to be usable by the units TU 1 , TU 2 . Thus, if the data from the units RU 1 , RU 2  has previously undergone a conversion or ciphering process, it undergoes a reverse conversion process or a deciphering process to be usable by the units TU 1 , TU 2 . It shall be noted that the interface units INT 1 , INT 2 , INT 4 , INT 5  may indifferently be part of or be outside the units TU 1 , TU 2 , RU 1  and RU 2  as represented in  FIG. 3 . 
     The initiation units TU 1 , TU 2  can be processing units, or DMA control units. The receiving units RU 1 , RU 2  can be interface units with external memories, input/output ports of the system or acceleration units. The interface unit INT 1 , INT 2  of a processing unit TU 1 , TU 2  can be a cache memory control unit. 
     Data transfers between the initiation units and the receiving units introduce latencies, particularly due to operations executed by the interface units INT 1 , INT 2 , INT 4 , INT 5  and by the unit BCTL to route the data. 
     According to one embodiment, the process to be applied to the data sent by the bus ADB comprises several sequential steps which are distributed in distributed processing units DPU 1 -DPU 5  provided in the interface units INT 1 , INT 2 , INT 4 , INT 5 , and possibly in the bus control unit BCTL. The execution time of the processing steps performed by each of the units DPU 1 -DPU 5  can be less than or equal to the latency time caused by the transfer operations, which appears in the interface unit or the control unit BCTL, where the distributed processing unit is located. 
     If the data transfer paths in the system PS 1  are considered, the data is transferred into the system of an initiation unit TU 1 , TU 2  to a receiving unit RU 1 , RU 2 , or conversely, by passing through the bus control unit BCTL. The result is that the process to be applied to the data can be shared between the units DPU 1  or DPU 2 , DPU 3  and DPU 4  or DPU 5 . Thus, upon a data transfer from an initiation unit TU 1 , TU 2  to a receiving unit RU 1 , RU 2 , the unit DPU 1  or DPU 2  performs one or more of the first steps of the process to be applied to the data, the unit DPU 3  performs one or more intermediate steps, and the unit DPU 4  or DPU 5  performs one or more of the last steps of the process. Conversely, upon a data transfer from a receiving unit RU 1 , RU 2  to an initiation unit TU 1 , TU 2 , the unit DPU 4  or DPU 5  performs one or more of the first steps of the process to be applied to the data, the unit DPU 3  performs one or more intermediate steps, and the unit DPU 1  or DPU 2  performs one or more of the last steps of the process. 
     According to one embodiment, the process to be applied to the data is an iterative process, i.e., comprising the execution a certain number of times, of a same processing step referred to as “iteration” applied to the data proceeding from a previous iteration.  FIG. 3  represents on oriented axes t and r symbolizing the data transfer direction, upon sending (from the initiation units to the receiving units), and upon receiving (from the receiving units to the initiation units), the number of iterations ti 1 -ti 5  and ri 1 -ri 5  respectively executed by each of the units DPU 1 -DPU 5  upon sending and receiving. The numbers of iterations follow the following relations:
 
( ti 1 or  ti 2)+ ti 3+( ti 4 or  ti 5)= nti   (1)
 
( ri 1 or  ri 2)+ ri 3+( ri 4 or  ri 5)= nri   (2)
 
nti and nri being the total number of iterations of the process to be applied to the data, respectively upon sending and receiving.
 
     According to one embodiment, ti 1  is equal to ti 2 , ti 4  is equal to ti 5 , ri 1  is equal to ri 2  and ri 4  is equal to ri 5 . 
     Alternatively, the numbers of iterations ti 1  and ti 2  are different for example to be adapted to the duration of the processes performed by the interface units INT 1  and INT 2 . The numbers of iterations ti 4  and ti 5  are then adapted to the number of iterations still to be performed to complete the process to be applied to the data transferred to one or other of the receiving units RU 1 , RU 2 . For this purpose, each unit DPU 1 -DPU 3  updates and sends with the processed data the number of iterations already performed or still to be performed. Alternatively, an identifier of the sending unit is sent in association with the processed data, such that the unit DPU 4  or DPU 5  which must complete the process may determine the number of iterations still to be performed. 
     The numbers of iterations ri 4  and ri 5  can also be different for example to be adapted to the duration of the processes performed by the interface units INT 4  and INT 5 . The numbers of iterations ri 1  and ri 2  are then adapted to the number of iterations still to be performed to complete the process to be applied to the data transferred to one or other of the initiation units TU 1 , TU 2 . For this purpose, each unit DPU 3 -DPU 5  updates and sends with the processed data the number of iterations already performed or still to be performed. Alternatively, each unit DPU 3 -DPU 5  sends with the processed data an identifier of the sending unit INT 4  or INT 5 , such that the unit DPU 1  or DPU 2  that completes the process can determine the number of iterations still to be performed. 
     According to one embodiment, the initiation unit TU 1 , TU 2  or the corresponding interface unit INT 1 , INT 2  tells the unit DPU 4 , DPU 5  of the receiving unit RU 1 , RU 2  the number of iterations ri 4 , ri 5  to be performed or its identifier such that the unit DPU 4 , DPU 5  or the unit INT 4 , INT 5  can determine the number of iterations ri 4 , ri 5  to be performed. 
       FIG. 4  represents an example of a processing system PS 2  comprising a processing unit CPU, a DMA control unit DCU, an external memory interface unit MAU, an acceleration unit ACC and a bus arbitration unit BAR controlling the access to a bus ADB interconnecting the units CPU, DCU, ACC and MAU. The unit CPU is linked to the bus ADB through a cache memory unit CMU. The function of the unit MAU is to give the system access to an external memory EMEM, the content of the memory being cipher protected. The function of the unit DCU is to ensure DMA transfers between an internal unit and the external memory EMEM. The units capable of controlling a data writing or reading operation in the memory EMEM are the processing units CPU or the cache memory unit CMU and the control unit DCU. The ciphering/deciphering functions applied to the data stored in the memory EMEM are for example based on an AES-type algorithm (Advanced Encryption System). This algorithm classically comprises 10 iterations to cipher and decipher 128 bits of data, with the first iteration possibly being slightly different from the others. 
     To use the latency time appearing in the system, the iterations of the ciphering/deciphering functions are distributed in the system. Thus, the units CMU, DCU, and MAU each comprise a ciphering and deciphering unit DPU 1 , DPU 2  and DPU 4 . The number of iterations performed by each of the units DPU 1 , DPU 2 , DPU 4  is adapted to the latency time introduced by the unit of which it is part, while complying with the requirement that the total number of iterations performed during a data transfer corresponds to the number of iterations to be performed. The number of iterations performed by the unit DPU 4  in the unit for accessing the memory MAU thus corresponds to the number of iterations still to be performed upon a data writing operation in the memory EMEM, given the number of iterations managed by one or other of the units DPU 1 , DPU 2 . Similarly, upon a data reading operation in the memory EMEM, the number of iterations performed by the unit DPU 1  in the unit CMU or DPU 2  in the unit DCU corresponds to the number of iterations still to be performed. 
     For example, to perform a DMA transfer from the external memory EMEM to the acceleration unit ACC, the unit CPU programs the unit DCU to read a set of, for example, 1,024 words of 32 bits in the memory EMEM and to transfer this set to the unit ACC. The unit DCU transfers this set in blocks of 8 words, each block being transferred temporarily into a local memory LMEM connected to the unit DCU, before being transferred to the unit ACC. The time for accessing the memory EMEM is of L1 clock cycles for the first word in the memory, then 1 cycle for each of the next seven words. The deciphering of the data read in a memory requires 10 iterations of 1 clock cycle for 128 bits, i.e., 2×10 cycles for 256 bits. Each block of 8 words transits for 9 clock cycles in the local memory LMEM. If the entire deciphering process is performed by the unit DPU 4 , the time necessary L to transfer a block of 8 words of 32 bits (256 bits) from the memory EMEM to the unit ACC is as follows:
 
 L=L 1+7+10+10+9
 
     If a part of each deciphering process, for example 4 iterations, is performed by the unit DPU 2 , so as to use a part of the transit time of 9 cycles in the memory LMEM, the transfer time L is reduced to:
 
 L=L+ 7+6+6+9, i.e., a decrease by 8 cycles.
 
     To perform a DMA transfer from the acceleration unit ACC to the external memory EMEM, the unit CPU programs the unit DCU to read a set of, for example, 1,024 words of 32 bits in the unit ACC, and to transfer it into the memory EMEM. The unit DCU transfers the set in blocks of 8 words, each block being transferred temporarily into the local memory LMEM before being transferred to the unit MAU. The time for write accessing the memory EMEM is of L2 clock cycles for the first word in the memory, then 1 cycle for each of the next seven words. The deciphering of the data read in a memory requires 10 iterations of 1 clock cycle for 128 bits, i.e., 2×10 cycles for 256 bits, and each block of 8 words transits for 9 clock cycles in the local memory LMEM. If the entire ciphering process is performed by the unit DPU 4 , the time L to transfer a block of 8 words of 32 bits from the unit ACC to the memory EMEM is as follows:
 
 L= 9+10+10 +L 2+7
 
     If a part of each ciphering process, for example 4 iterations, is performed by the unit DPU 2 , so as to use the transit time of 9 cycles in the memory LMEM, the transfer time L is reduced to:
 
 L= 9+6+6 +L 2+7, i.e., a decrease by 8 cycles.
 
     If the size of the blocks transferred is variable, the number of iterations executed by the unit DPU 2  when reading or writing the memory EMEM can be adapted to the latency time of the unit DCU. Thus, if the size of the blocks transferred is of 4 words of 32 bits, the latency time of the unit DCU changes to 5 cycles. The unit DPU 2  can then execute only one iteration of the ciphering or deciphering process, the nine other iterations then being performed by the unit DPU 4 . If the size of the blocks transferred is of 16 words of 32 bits, the latency time of the unit DCU changes to 17 cycles. All of the ciphering and deciphering processes can thus be performed by the unit DPU 2 . 
     The initiation units CPU (or CMU) and DCU are configured for adapting the number of iterations executed by their distributed processing unit DPU 1 , DPU 2  depending on the latency of the processing they activate. The requests to the external memory EMEM sent to the unit MAU indicate the number of iterations to be performed by the unit DPU 4 . Thus, upon writing in the memory EMEM, the data to be written are sent by the bus ADB in association with the number of ciphering iterations still to be performed by the unit DPU 4 . Upon reading the memory EMEM, the reading request can be associated with the number of iterations of the deciphering process to be performed by the unit DPU 4 . The unit DPU 4  can also be configured so as to be able to observe the requests for accessing the memory, containing the sender of the request and a type of request, and to determine the number of iterations to be executed depending on this information. 
     In a simplified alternative, the number of iterations executed by each unit DPU 1 , DPU 2 , DPU 4  is fixed, irrespective of the request and the data transfer direction between the memory EMEM and the system PS 2 . In this case, it is not necessary to send, with the data, any information that can be used to determine the progress of the process or the number of iterations to be executed by the processing unit DPU 1 , DPU 2 , DPU 4  which receives the data. 
       FIG. 5  represents a system PS 3  having an NoC (Network on Chip) integrated network architecture. The system PS 3  comprises several sub-systems SS 1 -SS 9  networked through routers ND 1 -ND 9  forming nodes of the network. Each sub-system SS 1 -SS 9  comprises a network interface unit NIC connected to one of the routers ND 1 -ND 9 . 
     To use the intrinsic latency times of the network, the interface units NIC and the routers ND 1 -ND 9  each comprise a shared processing unit DPU. Each router ND 1 -ND 9  may comprise one or more input and output ports to be connected to one or more other routers. Each sub-system SS 1 -SS 9  may comprise one or more processors, one or more internal memories, input/output controllers and a local bus interconnecting the different components of the sub-system. Each sub-system SS 1 -SS 9  may also have a specific clock which can be fully asynchronous with the clocks of the other sub-systems. Thus, each sub-system SS 1 -SS 9  can have the architecture represented in  FIG. 3  or  4 , with the network interface unit NIC connected to the local bus ADB. 
     To manage the asynchronism of the sub-systems SS 1 -SS 9 , the routers ND 1 -ND 9  and the network interface units NIC of the sub-systems comprise buffer memories for example of FIFO (First-In First-Out) type temporarily storing data to be sent by the network. This results in latency times which can be used by the units DPU to perform steps of a process to be applied to the data to be sent. The data is then sent in association with a piece of information that can be used to determine the progress of the process. Thus, if the data is sent between the nodes of the network in frames, a field of each frame can specify a progress status of the process, such as a number of iterations. 
       FIG. 5  represents by an arrow F a data transmission path in the system PS 3 , from the sub-system SS 1  to the sub-system SS 9 , and passing through the routers ND 1 , ND 4 , ND 5 , ND 8  and ND 9 . The process to be applied to the data can therefore be performed successively by the processing units DPU of the sub-system SS 1 , then of the routers ND 1 , ND 4 , ND 5 , ND 8  and ND 9 , and finally of the sub-system SS 9 . 
     The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments. 
     These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.