Abstract:
A parametric curve generating device for developing a Bezier curve is provided. The device is capable of executing a high speed division operation with a limited magnitude of hardware scale. Adders perform calculations that are stored in registers. Convergence discrimination circuits discriminate whether data stored in the registers converge. Subsequent processing varies depending on the discrimination result. A stack memory is used to store data from the registers.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a parametric curve generating device, which generates an outline font character utilized in the office automation equipment such as a computer or a printer, or an arbitrary parametric curve utilized in the field of CAD, designing, etc. 
     2. Related Background Art 
     At first, as an example of the curve there will be explained a Bezier curve. A third-order Bezier curve can be represented by the following equation, utilizing the coordinates P 0 , P 1 , P 2  and P 3  of four points: 
     
         P(t)=P.sub.0 (1-t).sup.3 +3P.sub.1 t(1-t).sup.2 +3P.sub.2 t.sup.2 (1-t)+P.sub.3 t.sup.3 (0≦t≦1) 
    
     This Bezier curve (P 0  . . . P 3 ) can be divided into two Bezier curves (Q 0  . . . Q 3  and R 0  . . . R 3 ), as shown in FIG. 1, by taking in succession the middle points of the control points (P 0  . . . P 3 ), wherein Q 3  =R 0 . The drawing is completed by repeating such division, until the entire length of the control points becomes equal to or less than a bit distance 1. 
     The division of the initial values (P 0  . . . P 3 ) generates two sets of data, of which one set (R 0  . . . R 3 ) is saved in a stack and the other (Q 0  . . . Q 3 ) is used as the initial values of the next division. This operation is repeated, and, if the data (Q 0  . . . Q 3 ) converge at a certain point, the data (R 0  . . . R 3 ) is used as the initial values for the next operation. If both data (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) converge, the data of the control points saved immediately before in the stack are revived as the initial values for the next operation. All the operations are completed when the stack becomes empty. Through such process, there can be obtained a train of the developed drawn points of the Bezier curve, in a continuous manner from P 0  to P 3 . 
     The operation of determining the middle point of two control points involves an addition and a division into 1/2. Since the 1/2 division can be achieved by a 1-bit shift to the right, an adder can achieve the addition and the 1/2 division by shifting the output of the adder to the right by a bit. If the data of the control points are of n bits, the result of the 1/2 division is given by the upper (n-1) bits of the result of addition. Also the carry-over output of the adder may be used as the uppermost bit of the result of the calculation. 
     FIG. 2 shows an example of the circuit of the parametric curve generating device for effecting the above-mentioned 1/2 division. The above-mentioned data (P 0  . . . P 3 ) are respectively stored in registers 1-4 . Adders 11-16 execute the 1/2 divisions, and the results of the operation (Q 0  . . . Q 3 , R 0  . . . R 3 ) are released to points 21-27 (Q 3  and R 0  are same and released to a point 24). 
     Convergence discrimination circuits 31, 32 respectively determine |Q 0  -Q 3  | and |R 0  -R 3  | and discriminate whether these values satisfy a predetermined condition of convergence, namely whether these values are equal to or less than the bit distance 1. 
     The function of the above-explained parametric curve generating device is classified into three cases according to the state of convergence of the control points, namely a case where (Q 0  . . . Q 3 ) do not converge, a case where (Q 0  . . . Q 3 ) converge but (R 0  . . . R 3 ) do not converge, and a case where (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) both converge. Such function is controlled by an unrepresented control circuit. 
     In the case when (Q 0  . . . Q 3 ) do not converge, the data (Q 1 . . . Q 3 ) released to the points 22, 23, 24 is stored in the registers 2-4 through a selector 41. The content of the register 1, being equal to Q 0 , remains unchanged. At the same time, the data (R 1 . . . R 3 ), released to the points 25, 26, 27 is saved in a stack memory 61 through a bus 51, and a similar operation is conducted on the new data (Q 1 . . . Q 3 ). 
     In the case when (Q 0  . . . Q 3 ) converge but (R 0  . . . R 3 ) do not converge, the data Q 0  released from the register 1 to the point 21 is released. For calculating the next points, the data (R 0  . . . R 2 ) at 24, 25, 26 are stored in the registers 1-3 through the selector 41. The content of the register 4, being equal to R 3 , remains unchanged. 
     In the case when (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) both converge, the data Q 0  and R 0  are released. Then, for calculating a point next to R 0 , the content (R 3 ) of the register 4 is stored in the register 1 through the selector 41, and the immediately previously saved data of three points are stored in the registers 2-4 from the stack memory 61, through the bus 51 and the selector 41. 
     For operating this circuit, it is necessary to set a clock cycle in such a manner that the 1/2 division, discrimination of convergence, switching of the selector 41, transfer to the registers 1-4 and saving/reviving to or from the stack memory 61 can be conducted within a clock cycle. More specifically, disregarding the data transfer time, the above-mentioned setting has to satisfy: 
     
         (a clock cycle) &gt;(delay time in an adder) ×3 +(delay time in convergence discrimination circuit) +(selector switching time) +(data set-up time of register) 
    
     and the data of three control points has to be simultaneously saved in or revived from the stack memory within this cycle time. 
     The data of each control point is data with a floating decimal point, consisting of an integral part of 1 0  bits and a fractional part of 1 1  bits. In order to generate a Bezier curve without error, the number 1 1  of bits of the fractional part has to be generally comparable with 1 0 . For example, if 1 0  has 16 bits, each of the registers 1-4 and the adders 11-16 of the above-explained parameter curve generating device has to have about 32 bits, so that the magnitude of the hardware can become large. 
     Also the stack memory 61, for simultaneously handling the data of three control points, requires a port of 32×3=96 bits. Similarly, the data bus 51 is required to have a width of 96 bits. The presence of a bus of such large width requires a large wiring area and is disadvantageous in forming this circuit into an LSI. 
     As explained in the foregoing, in order to execute the 1/2 division required for determining the Bezier curve at a high speed, the conventional circuit requires a large magnitude and the bus of a large width, and is therefore inadequate for LSI formation. 
     SUMMARY OF THE INVENTION 
     The object of the present invention is to provide a parametric curve generating device for generating a Bezier curve, capable of executing the 1/2 division at a high speed with a circuit of limited magnitude. 
     The above-mentioned object can be attained, according to the present invention, by a parametric curve generating device for generating an arbitrary parametric curve, having a first register for storing the coordinates of the control point of the curve; a 1/2 division circuit for dividing the control points, stored in the register, into two thereby forming control points of two curves; and a second register for storing the control points of the two curves formed by the 1/2 division circuit. The device also includes a stack memory for successively storing the control points of plural sets; a third register positioned between the first and second registers and the stack memory. The third register is and adapted to store the control points of a set. The device further includes a discrimination circuit for determining whether or not to effect the division of the control points by the 1/2 division circuit. A desired parametric curve is generated and released by repeating the 1/2 division on the control points given in advance to the first register. 
     The present invention is further featured by a fact that, in case one of the two sets of the control points formed by the 1/2 division circuit is temporarily saved according to the result of discrimination by the discrimination circuit, the set to be saved is stored in the third register and then stored in the stack memory. 
     The present invention is further featured by a fact that, in case the control points of a temporarily saved set of the curve are transferred to the first register according to the result of discrimination by the discrimination circuit, the content of the third register is transferred. 
     The present invention is further featured by a fact that the dividing operation of the 1/2 division circuit and the transfer between the third register and the stack memory are simultaneously executed in a parallel manner. 
     The present invention is further featured by a fact that the stack memory is so constructed as to read and write a control point at a time. 
     The present invention is further featured by a fact that the 1/2 division circuit is composed of three adders and the dividing operation of each control point is completed in three clock cycles. 
     The present invention is further featured by a fact that each of the registers and the stack memory is composed of an integral part and a fractional part. 
     The present invention is further featured by a fact that the generated curve is a Bezier curve. 
     The present invention is further featured by a fact that the above-mentioned Bezier curve belongs to a two-dimensional space having x and y coordinates, and the above-mentioned registers and stack memory are provided for each of the x and y coordinates. 
     The present invention is further featured by a fact that there is provided output means for releasing the generated curve. 
     The present invention is further featured by a fact that the above-mentioned output means is a printer. 
     The parametric curve generating device of the present invention generates a desired parameter curve, by repeating a 1/2 dividing operation on the points of a Bezier curve given to the first register and saving the data from the adders to the stack memory or reviving the data from the stack memory to the adders. 
     The parametric curve generating device of the present invention is capable of simultaneously executing the dividing operation of the control points of the Bezier curve by the 1/2 division circuit and the saving/reviving operation of a set of the control points to or from the stack memory in parallel manner, through the use of the third register. Owing to this configuration, each 1/2 dividing operation can be conducted within 4 clock cycles in all cases, regardless of the state of convergence. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic view showing division of a third-order Bezier curve into two; 
     FIG. 2 is a block diagram showing the configuration of a parametric curve generating device; 
     FIG. 3 is a block diagram showing the configuration of a parametric curve generating device; 
     FIGS. 4 to 6 are charts showing the timing function of the various parts in FIG. 3; 
     FIG. 7 is a block diagram showing another configuration according to the present invention; and 
     FIGS. 8 to 10 are charts showing the timing function of the various parts of the configuration according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 3 shows an example of the circuit embodying the present invention, wherein shown are registers 71-74 for storing the data (P 0  . . . P 3 ) as in the registers 1-4 explained in the foregoing; adders 81-83 which are reduced in number from six to three in comparison with the configuration shown in FIG. 2; registers 91-97 which are increased in number in comparison with the configuration in FIG. 2; a stack memory 101; and a bus 111 connecting the stack memory 101 with the registers 72-74. This circuit is controlled by an unrepresented control circuit. 
     The function of this circuit will now be explained with reference to timing charts shown in FIGS. 4, 5 and 
     The operations to the fourth cycle are same in FIGS. 4, 5 and 6. 
     In a first cycle, the adders 81-83 execute calculations Q 1  =(P 0  +P 1 )/2, S =(P 1  +P 2 )/2 and R 2  =(P 2  +P 3 )/2, of which results Q 1 , S, R 2  are respectively stored in the registers 92, 94, 96. At the same time, P 0  is transferred as Q 0  to the register 91, and P 3  is transferred as R 3  to the register 97. 
     In a second cycle, the adder 81 adds the content of the register 92 and that of the register 94 and multiples by 1/2, and the obtained result is stored as Q 2  in the register 93. Also the adder 83 adds the contents of the registers 94 and 96 and multiplies by 1/2, and the obtained result is stored as R 1  in the register 95. 
     In a third cycle, the adder 82 adds the contents of the register 93 and 95 and multiples by 1/2, and the obtained result is stored as Q 3  (R 0 ) in the register 94. At this point, Q 0  is stored in the register 91, Q 1  in 92, Q 2  in 93, Q 3  =R 0  in 94, R 1  in 95, R 2  in 96, and R 3  in 97. In this manner the 1/2 division as in FIG. 2 can be executed within three clock cycles. 
     In a fourth cycle, the convergence discrimination circuits 121, 122 discriminate whether (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) are in the converged state, and the process varies according to the result of the discrimination. 
     FIG. 4 shows a case where (Q 0  . . . Q 3 ) do not converge. Based on the result of discrimination by the convergence discrimination circuits 121, 122, the selector 131 is so switched that (Q 1  . . . Q 3 ) are stored in the registers 72-74 at the start of the next cycle, and (Q 1  . . . Q 3 ) are stored in the registers 72-74 at the start of a fifth cycle. The content of the register 71, being Q 0 , remains unchanged. On the other hand, (R 1 . . . R 3 ) are saved in succession in the stack memory 101 through the bus 111, in fifth, sixth and seventh cycles. The next 1/2 division cannot be started until the completion of the storage. Consequently 7 cycles are required in this case. 
     FIG. 5 shows a case where (Q 0  . . . Q 3 ) converge but (R 0  . . . R 3 ) do not converge. Based on the result of discrimination by the convergence discrimination circuits 121, 122 in the fourth cycle, Q 0  is released and the selector 131 is so switched that (R 0  . . . R 2 ) are stored in the registers 71-73. (R 0  . . . R 2 ) are stored in the registers 71-73 at the start of the fifth cycle. The content of the register 74, being R 3 , remains unchanged. In this case 4 cycles are required, because the contents of the registers 71-74 are fixed at the start of the fifth cycle so that the aforementioned operations of the first cycle and thereafter can be started from the fifth cycle. 
     FIG. 6 shows a case where (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) both converge. Based on the result of discrimination by the convergence discrimination circuits 121, 122 in the fourth cycle, Q 0  and R 3  are released, and the selector 131 is so switched that the data of the control points can be revived in the fifth, sixth and seventh cycles and that the content of the register 97 can be transferred to the register 71. The data (P 1  &#39;, P 2  &#39;, P 3  &#39;) of three control is revived from the stack memory 101 to the registers 72-74 through the bus 111, in the fifth, sixth and seventh cycles. Also the content (P 0  &#39;) of the register 97 is stored in the register 71 through the selector 131, at the start of the fifth cycle. In this case, 7 cycles are required, as the contents of the registers 71-74 are fixed at the start of the eighth cycle. 
     In the configuration shown in FIG. 3, the width of the data port of the stack memory 101 and of the bus 111 is 32 bits, so that it is more suitable for LSI formation. 
     For operating this circuit, the clock cycle has to be set as follows, disregarding the data transfer time: 
     
         ______________________________________(a clock cycle) &gt;         max{(delay time of an adder),         (delay time of convergence         discrimination circuit + selector         switching time), (stack memory         access time)} + (register data         set-up time)______________________________________ 
    
     If the stack memory is composed of a register file allowing high-speed access, the clock cycle in FIG. 3 can be made to be about 1/4 of the clock cycle in FIG. 2. Consequently, in comparison with the circuit shown in FIG. 2, the circuit in FIG. 3 can process with a comparable speed in case (Q 0  . . . Q 3 ) converge but (R 0  . . . R 3 ) do not converge, but is slower by the time required for the cycles for transfer with the stack memory 101 in other cases. 
      Another embodiment! 
     FIG. 7 shows another embodiment of the present invention, wherein components equivalent in function and position to those in FIG. 3 are represented by primed corresponding numbers. Registers 141-143 alone are added to the configuration shown in FIG. 3, so that the increase in the magnitude of circuitry in this embodiment is minimal. 
     In the following, the function of the circuit shown in FIG. 7 will be explained with reference to timing charts in FIGS. 8, 9 and 10. This circuit is controlled by an unrepresented control circuit. 
     The operations to the fourth cycle are same in FIGS. 8, 9 and 10. 
     At first, in a first cycle, adders 81&#39;-83&#39; effect calculations (P 0  +P 1 )/2, (P 1  +P 2 )/2 and (P 2  +P 3 )/2, of which results Q 1 , S, R 2  are respectively stored in the registers 92&#39;, 94&#39;, 96&#39;. At the same time, P 0  is transferred as Q 0  to the register 91&#39;, and P 3  is transferred as R 3  to the register 97&#39;. 
     In a second cycle, the adder 81&#39; adds the contents Q 1 , S of the registers 92&#39;, 94&#39; and multiplies by 1/2, and the obtained result Q 2  is stored in the register 93&#39;. Also the adder 83&#39; adds the contents S, R 2  of the registers 94&#39;, 96&#39; and multiplies by 1/2, and the obtained result R 1  is stored in the register 95&#39;. 
     In a third cycle, the adder 82&#39; adds the contents Q 2 , R 1  of the registers 93&#39;, 95&#39; and multiplies by 1/2, and the obtained result Q 3  =R 0  is stored in the register 94&#39;. At this point, Q 0  is stored in the register 91&#39;, Q 1  in 92&#39;, Q 2  in 93&#39;, Q 3  =R 0  in 94&#39;, R 1  in 95&#39;, R 2  in 96&#39;, and R 3  in 97&#39;. In this manner the 1/2 division as in FIG. 2 can be executed within three clock cycles. 
     In a fourth cycle, the convergence discrimination circuits 121&#39;, 122&#39; discriminate whether (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) are in the converged state, and the process varies according to the result of the discrimination. 
     FIG. 8 shows a case where (Q 0  . . . Q 3 ) do not converge. Based on the result of discrimination by the convergence discrimination circuits 121&#39;, 122&#39;, the selector 131&#39; is so switched that (Q 1  . . . Q 3 ) are stored in the registers 72&#39;-74&#39; at the start of the fifth cycle, and (R 1  . . . R 3 ) are stored in the registers 141-143 at the start of the fifth cycle. (Q 1  . . . Q 3 ) are stored in the registers 72&#39;-74&#39; in the fifth cycle. The content of the register 71, being Q 0 , remains unchanged. Also (R 1  . . . R 3 ) are stored in the registers 141-143. Also in the fifth, sixth and seventh cycles, the contents of the registers 141-143 are saved in succession in the stack memory 101&#39;, but the contents of the registers 141-143 remain unchanged. 
     FIG. 9 shows a case where (Q 0  . . . Q 3 ) converge but (R 0  . . . R 3 ) do not converge. Based on the result of discrimination by the convergence discrimination circuits 121&#39;, 122&#39;, Q 0  is released and the selector 131&#39; is so switched that (R 0  . . . R 2 ) are stored in the registers 71&#39;-73&#39;. (R 0  . . . R 2 ) are stored in the registers 71&#39;-73&#39; at the start of the fifth cycle. The content of the register 74&#39;, being R 3 , remains unchanged. 
     FIG. 10 shows a case where (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) both converge. Based on the result of discrimination by the convergence discrimination circuits 121&#39;, 122&#39;, Q 0  and R 0  are released, and the selector 131&#39; is so switched that the contents (P 1  &#39;, P 2  &#39;, P 3  &#39;) of the registers 141-143 are transferred to the registers 72&#39;-74&#39; and the content (P 0  &#39;) of the register 97&#39; is transferred to the register 71&#39; in the fifth cycle. Then, at the start of the fifth cycle, the contents of the registers 141-143 are transferred to the registers 72&#39;-74&#39;. It is to be noted that the contents of the registers 141-143 are same as those saved immediately before in the stack memory 101&#39;. Also at the start of the fifth cycle, the content of the register 74&#39; is stored in the register 71&#39; through the selector 131&#39;. Then, in the fifth, sixth and seventh cycles, the data (P 1  &#34;, P 2  &#34;, P 3  &#34;) present in the second position from the top of the stack memory are revived in succession to the registers 141-143 from the stack memory 101&#39;, through the bus 111&#39;. Also a preceding set of data is brought to the top of the stack memory. As a result, the content of the registers 141-143 always coincides with the data of a set at the top of the stack memory 101&#39;, after each 1/2 dividing operation. The content of the registers 141-143 may be used for reviving the data of the control points in the registers 72&#39;-74&#39; without waiting for a bus cycle, even when there continues the situation where (Q 0  . . . Q 3 ) and (R 0  . . . R 3 ) both converge. 
     In the following there will be considered the function of this circuit, particularly with respect to: 
     1) bus cycle between the stack memory 101&#39; and the registers 141-143; 
     2) data transfer cycle between the registers 141-143 and the registers 72&#39;-74&#39;, 95&#39;-97&#39;; and 
     3) 1/2 dividing operation. 
     The bus cycle occurs always in the fifth, sixth and seventh cycles. 
     The transfer cycle 2) always occurs at the start of the fifth cycle. 
     With respect to the 1/2 dividing operation 3), the data required for the next operation is fixed in the registers 71&#39;-74&#39; at the start of the fifth cycle. The 1/2 dividing operation can be executed in an independent and continuous manner, utilizing the data in the registers 71&#39;-74&#39;. 
     Consequently, in the function of this circuit, a pipeline operation is possible between the bus/transfer cycles and the 1/2 dividing operation. With such pipeline operation, each 1/2 dividing operation can be executed within 4 clock cycles. 
     In the determination of the number of necessary clock cycles, it is defined as 4 clock cycles, utilizing the above-mentioned pipeline operation. 
     Also a clock cycle can be selected comparable to that in the circuit shown in FIG. 3. 
     The foregoing description has been limited to the case of one-dimensional data, but the Bezier curve relating to the present invention is defined in a two-dimensional space and has x and y coordinates, and, for handling such Bezier curve, there should be prepared two sets of the parametric curve generating device explained above. In such case, the above-mentioned converged state is identified when x and y both converge, and the same discrimination is conducted for x and y coordinates. 
     The configurations shown in FIGS. 3 and 7 employ the registers 91, 97, 91&#39;, 97&#39; for the purpose of simplicity, but these registers may be dispensed with. In such case the registers 91, 91&#39;, 97, 97&#39; are replaced by the registers 71, 71&#39;, 74, 74&#39; respectively. 
     The parametric curve generating device of the present embodiment is capable, by the entry of outline font data stored in a memory, of deriving control points for developing a curve, developing the curve based on thus derived control points and providing thus developed curve by an unrepresented printer or an unrepresented display device. 
     As explained in the foregoing, the parametric curve generating device of the present invention is capable of high-speed development of a Bezier curve with a limited magnitude of hardware. Also it is particularly suitable for LSI formation, because of the reduced bus width.