Abstract:
Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to U.S. Provisional Patent Application No. 61/148,448 filed on Jan. 30, 2009 titled “Improved Neutron Detector Cell Efficiency”, the entire contents of which are incorporated herein for all purposes. 
    
    
     GOVERNMENT RIGHTS 
     The United States Government has acquired certain rights in this invention pursuant to Contract No. N00173-08-C-6013, awarded by the U.S. Naval Research Laboratory. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a structure for providing sensitive detection capability for neutrons, and more particularly, to a sensor detector component of a neutron detection structure that is low cost, low power, able to be mass-produced, and makes efficient use of the silicon area. 
     BACKGROUND OF THE INVENTION 
     The threat of large scale terrorist attacks has resulted in an increased interest in methods for the detection of weapons of mass destruction and their related materials for homeland security. Of particular interest are passive detection systems (meaning non-intrusive devices detecting the proximity of certain materials), which, if they can be mass produced at low cost and low power, afford the broadest deployment and therefore the most coverage and security. Because radioactive material emits neutrons while self-fissioning, a passive neutron detection device is of particular interest for the detection of clandestine nuclear material. 
     Recently a semiconductor-based solid state neutron detector has been proposed in which a “neutron conversion layer” (a layer containing a material such as boron isotope  10 B which is understood to efficiently react with neutrons to generate high energy charged particles) is placed in very close proximity to an array of charge-sensitize circuits, such as a DRAM memory cell, a FLASH memory cell, or an SRAM memory cell. An industry standard 6-transistor (6T) SRAM cell  100  is illustrated in  FIG. 1 . For example, U.S. Pat. Nos. 6,867,444 and 7,271,389, assigned to the United States Navy, sets forth two such neutron detection devices and are hereby incorporated by reference herein in their entireties. The  10 B doped film reacts with incident neutrons to produce alpha particles that generate charge in the memory cell silicon and cause binary state changes known as single event upsets (SEUs). The upsets, and thus the presence of neutrons, are detected by periodically scanning the memory array and comparing it to the originally loaded data pattern 
     Though an SRAM, DRAM, or non-volatile memory array may accomplish the above task, it may not be the most ideal candidate for the cell that monitors charged particle induced behavior change. For example, SRAM cells are designed to support random read and write access of individual memory cells (bits) and to store random data patterns. None of this functionality is required for the detection of charge generation and collection; all that is needed is a circuit array that can be periodically scanned for evidence of “hits” by the charged particles generated in the neutron conversion layer. 
     Further, an SRAM cell is designed for minimum area, and while sufficiently small cells are important, individual circuit cell size is not the real priority. The most important aspect for achieving a low-cost, low-power, mass-producible neutron detection device is the efficiency of the silicon area used. Referring to the case where the neutron conversion layer contains boron isotope 10B and the product of the reaction is alpha particles, the silicon area used by the SRAM cell, for example, is typically very large compared to the cross sectional area that is actually sensitive to a strike by an alpha particle. An area efficiency term can be defined as: the memory cell silicon area in which an alpha particle can induce an upset divided by the total memory cell silicon area. For a charge-sensitive circuit cell ideal for the neutron detector application this ratio would approach 1; in the case of the SRAM cell this ratio may in fact be less than 0.05. And thus 95% of the silicon is wasted, increasing cost, area, and power. 
     Therefore, it would be desirable to provide an array of semiconductor circuits used in a neutron detection device that makes more efficient use of the silicon area, uses less power, is low cost, and is able to be mass produced. 
     SUMMARY 
     Three types of circuit arrays that have an improved area efficiency, as defined above, and can be used to detect and count the alpha particles as they “hit” the circuit are: (1) state latching circuits; (2) glitch generating circuits; and (3) charge loss circuits. 
     State latching circuits are single event upset based and store the binary state change for later readout. These circuits allow for very infrequent reads as well as a spatial mapping of the upsets. Unneeded transistors and signal lines are removed from an SRAM cell to create the desired circuit. 
     Glitch generating circuits, or edge producing cells, create a rising or falling edge for each upset detected. The upset is not latched as in the previous example, but instead intended to trigger a counting circuit. These circuits can most likely realize a higher area efficiency as well as read “hits” in real time. The charge required to cause sufficient current to flow through a device (transistor, BJT, diode, etc.) to produce a glitch, or upset, referred to as Qcrit, is lower with this method. 
     Charge loss circuits create charge leakage on a node in response to charged particle (i.e., alpha particle) intrusion. The observable circuit change can be cell current, threshold voltage, change in voltage on the bit-line during a read, a floating body effect, etc. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an industry standard 6T SRAM cell. 
         FIGS. 2-13  illustrate state latching charged particle detectors according to embodiments of the present invention. 
         FIGS. 14-21  illustrate glitch generating charged particle detectors according to embodiments of the present invention. 
         FIG. 22  illustrates a charge loss charged particle detector according to an embodiment of the present invention. 
         FIG. 23  illustrates a charge loss charged particle detector according to another embodiment of the present invention. 
         FIGS. 24-26  illustrate charge loss charged particle detectors according to further embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Introduction 
     The embodiments described herein provide circuit arrays and corresponding methods to detect charged particle intrusion for use in a neutron detection structure that make the most efficient use of the silicon area, are low cost, low power, and able to be mass produced. In general, the circuits are composed of p-channel and n-channel MOSFETs with various embodiments including resistors, capacitors, diodes, and BJTs. 
     State Latching Circuits 
       FIG. 2   a  illustrates a circuit  200  according to an embodiment of the present invention. This circuit  200  is essentially a one-state memory cell lacking a second bitline, and second enable select transistor. Initial writing of the cell is performed by driving the bitline to Vss and enabling mn 4  by driving the wordline. Node 2  is therefore driven to Vss thus turning off mn 1  and turning on mp 1 . Turning on mp 1  drives nodel to Vdd, thus turning on mn 2  and ensuring node 2  remains at Vss. Incident charged particles will cause a channel to open in mn 1  upsetting the latch by driving mp 2  and thus storing Vdd on node  2 . A readout of the bit line would indicate if a charged particle had changed the state of the cell. The body of mn 1  can be left floating or tied to Vss (not shown). If the body is left floating, deposited charge will multiply making the cell easier to upset. 
     In some alternate embodiments, mp 1  can be weakened as well to increase the ability for a charged particle to upset the latch. Several techniques exist for weakening a p-channel MOSFET including implant, backbias, drawn geometry, increased gate oxide thickness, and gate doping, as well as other methods well known in the art. 
     Circuit  200  is configured as a “write-zero” device, i.e. a “zero”, or low (Vss) voltage is written to node 2  through the bitline. Upsets appear as “ones” at node 2 . This circuit  200  could just as easily be implemented as a “write-one” device without departing from the scope of the invention. Such a device is shown as circuit  202  in  FIG. 2   b . Here, a “one”, or high (Vdd) voltage is written into node 2  through the bitline. Upsets appear as “zeros” (Vss) on node 2 . In circuit  202 , mn 1  can be weakened as well to increase the ability of a charged particle to upset the latch. 
       FIGS. 3   a ,  4   a , and  5   a  illustrate circuits  300 ,  400 , and  500  corresponding to further embodiments of the present invention. A charge collector in the form of a diode in  FIG. 3   a , a BJT in  FIG. 4   a , and a MOSFET in  FIG. 5   a  is added to the circuit  200  of  FIG. 2   a , in parallel with mn 1 , as an additional target upset device. The diode should be designed to maximize sensitive volume and charge generation while minimizing the additional capacitance (Q crit ). The base of the BJT can be floating or it can be tied to Vss (not shown). If the base is left floating, deposited charge will multiply. In  FIG. 5   a , the MOSFET is shown as an nFET having a gate terminal coupled to Vss, however it should be noted that one could substitute this for a pFET having a gate terminal coupled to Vdd. The gate of the MOSFET can be tied to ground (Vss) or an additional wordline-type bus for testing (not shown). The bulk connection (not shown) of the MOSFET can either be tied to ground or left as “floating body”, in which case the deposited charge will be multiplied by the gain of the parasitic npn inherent to the n-channel transistor. 
     It should be noted that mp 1  can be weakened in each of the above embodiments as well utilizing the aforementioned weakening methods. It should also be noted that each of the above embodiments are not limited to one collector device per cell; multiple collector devices can be utilized in the same cell. 
       FIGS. 3   b ,  4   b , and  5   b  illustrate the “write-one” versions  302 ,  402 , and  502  of the “write-zero” circuits  300 ,  400 , and  500 . It should be noted that in the “write-one” circuits  302 ,  402 , and  502 , mn 1  can be weakened to increase the ability of a charged particle to upset the latch. 
       FIGS. 6   a ,  7   a ,  8   a , and  9   a  illustrate circuits  600 ,  700 ,  800 , and  900  according to further embodiments of the present invention. Mp 1  in the circuit  200  may be replaced with a very large resistor as illustrated in circuit  600  of  FIG. 6   a . The resistance of R 1  may be 100 kΩ or greater. A large R 1  will slow nodel&#39;s recovery and make the cell easier to upset. Once the cell has been upset, DC current will flow in the Vdd line possibly providing an alternate means for determining when a certain number of cells have been upset. Charge collector devices can also be added in parallel to mn 1  illustrated in circuits  700 ,  800 , and  900  of  FIGS. 7   a ,  8   a , and  9   a  respectively, similar to circuits  300 ,  400 , and  500 . 
       FIGS. 6   b ,  7   b ,  8   b , and  9   b  illustrate the “write-one” versions  602 ,  702 ,  802 , and  902  of the “write-zero” circuits  600 ,  700 ,  800 , and  900 . 
       FIG. 10   a  illustrates a circuit  1000  according to another embodiment of the present invention. In this embodiment, the gate of mp 1  is tied to a Vbias line instead of to node 2 . The Vbias line is used set the recovery current of mp 1  and thus sensitivity of the cell, and may also be employed to assist in the setup and reset of the cell. Again, DC current will flow in the Vdd line for upset cells which can possibly provide an alternate means for determining when a certain number of cells have been upset. Charge collector devices can also be added in parallel to mn 1 , as illustrated in circuits  1100 ,  1200 , and  1300  of  FIGS. 11   a ,  12   a , and  13   a  respectively, similar to circuits  300 ,  400 , and  500 . In each of circuits  1000 ,  1100 ,  1200 , and  1300 , mp 1  can be optionally weakened to increase the ability of a charged particle to upset the latch. 
       FIGS. 10   b ,  11   b ,  12   b , and  13   b  illustrate the “write-one” versions  1002 ,  1102 ,  1202 , and  1302  of the “write-zero” circuits  1000 ,  1100 ,  1200 , and  1300 . In these “write-one” circuits, mn 1  can be optionally weakened to increase the ability of a charged particle to upset the latch. 
     Glitch Generating Cells 
       FIGS. 14   a  illustrates circuit  1400  according to a further embodiment of the present invention. This circuit is intended to produce a glitch, or a rising edge, on the bitline for each upset. Mn 1  can be one or more charge collecting MOSFETs with the bulk connection (not shown) tied to Vss or left as “floating body”. If left as floating body, the deposited charge will be multiplied by the gain of the parasitic npn inherent to the n-channel transistor. Circuit  1400  illustrates a glitch generating cell with a resistor R 1  coupled between Vdd and nodel. The value of R 1 , which may be 100 kΩ or more, is chosen such that the charging time to bring nodel back to Vdd after an upset is long enough to produce a rising edge on the bit line. The wordline is kept low and used for testing the array. The bit line is held low but is high impedance, and may be tied to a counting circuit. A charged particle strike on transistor mn 1  will cause the voltage on node  1  to collapse to Vss, turning on transistor mp 2 , thus producing a rising edge on the bit line. Many cells, possibly even several rows, can share a common bitline and detect circuit. The limitation is that the “on” current of mp 2  must be sufficient to drive the aggregate bitline capacitance to a detectable voltage level before nodel can recover from the charged particle strike. Because the cells are not individually accessed there is no means to detect which cell received the alpha particle strike, thus some information about the location of the neutron penetration is lost. 
     Charge collector devices can also be added in parallel to mn 1 , as illustrated in circuits  1500 ,  1600 , and  1700  of  FIGS. 15   a ,  16   a , and  17   a  respectively, similar to circuits  300 ,  400 , and  500 . In circuit  1600 , the base of the BJT can be floating or it can be tied to Vss (not shown). If the base is left floating, deposited charge will multiply. The gate of the MOSFET in circuit  1700  can be tied to ground (Vss) or an additional wordline-type bus for testing (not shown). The bulk connection (not shown) of the MOSFET can either be tied to ground or left as “floating body”, in which case the deposited charge will be multiplied by the gain of the parasitic npn inherent to the re-channel transistor. 
     The circuits  1400 ,  1500 ,  1600 , and  1700  produce rising edges on the bit line each time a particle strike is detected, but these circuits could just as easily produce falling edges on the bitline instead.  FIGS. 14   b ,  15   b ,  16   b , and  17   b  illustrate the “falling-edge” versions  1402 ,  1502 ,  1602 , and  1702  of the “rising-edge” circuits  1400 ,  1500 ,  1600 , and  1700 . 
       FIG. 18   a  illustrates a circuit  1800  according to another embodiment of the present invention. The principle in this circuit is the same as that of circuit  1400 , but the resistor is replaced with a biased p-channel transistor. Similar to that of circuit  1000 , the Vbias line is used to set the recovery current of mp 1  and thus the sensitivity of the cell, and may also be employed to assist in the setup and testing of the cell. 
       FIGS. 19   a ,  20   a , and  21   a  illustrate circuits corresponding to circuit  1800  in which charge collectors have been placed in parallel with mn 1 .  FIGS. 18   b ,  19   b ,  20   b , and  21   b  illustrate the “falling-edge” versions  1802 ,  1902 ,  2002 , and  2102 , of the “rising-edge” circuits  1800 ,  1900 ,  2000 , and  2100 . 
     Charge Loss Circuits 
       FIG. 22  illustrates a circuit  2200  according to another embodiment of the present invention. This circuit is constructed as an array of partially-depleted floating-body SOI transistors (though only one is shown) with drains coupled to bit lines and sources coupled to Vss. The floating body serves as the storage node which will be affected by the charged particle intrusion. By adjusting the biases on the bitline, the wordline, and the Vss line, the floating body potential may be charged either positive (lowering the threshold potential) or negative (increasing the threshold potential). Because the array is simply set-up for “hits” and not storing random data patterns, to whatever degree the setup currents permit the entire array may be “set-up” in a single parallel operation. After “set-up” the bias conditions on the bitline, wordline, and Vss line are set so as to maximize the retention time of the stored state, this being detection mode. If a charged particle penetrates the channel of the transistor, electron-hole pairs will be generated, significantly altering the body potential and thus the threshold voltage of the transistor. Wordline and bitline voltages are optimized for the read operation to discriminate between a cell which is intact compared with a cell which has experienced a charged particle intrusion. Similar to most DRAM implementations, a read is most likely destructive of the stored or “upset” state, and retention time of the stored state is limited, so the array needs to be scanned and “re-set-up” (i.e., refreshed) somewhat frequently. Depending upon bias conditions, in some implementations it may be possible to have the read operation and the reprogram (i.e., re-set-up) operation be essentially the same operation, or at least performed at the same time. While this floating-body single transistor body charge storage implementation has the disadvantages of requiring frequent reads and refreshes, the Qcrit is very low and the cross sectional efficiency may be very high. 
     In another embodiment of the present invention a charge storage memory device such as floating gate, nitride storage (SONOS), nano-crystal, or nano metal particle device is used.  FIG. 23  details a specific case in which a floating gate EEPROM device, such as the one described in commonly owned U.S. Pat. No. 7,378,705, is used. As power is applied to the device  2300 , a “one” is written to a full array of memory cells by passing F-N tunneling currents through the gate oxide into a MOS capacitor. Power is removed and the device enters a passive detection mode. Charged particles that pass through the gate oxide generate electron-hole pairs, some of which recombine and some of which transport to discharge the capacitor. Upon readout, the number of failing cells is compared to a threshold value based on the number of naturally occurring failing cells to determine the presence of charged particles. Other examples of floating gate device structures include: EPROM, NOR flash, NAND flash, and EEPROM such as the one described in commonly owned U.S. Pat. No. 7,378,705. 
       FIGS. 24   a - f  illustrate circuits  2400 - 2410  according to further embodiments of the present invention. The cell current read on the bitline depends upon the charge stored on the charge storage node. Charged particle intrusion will affect the charge on this node and thus the read current. Multiple charge collecting devices can be used including a MOSFET, diode, and a BJT. Circuits  2400 ,  2402 , and  2404  illustrate charge collectors that discharge low while circuits  2406 ,  2408 , and  2410  illustrate charge collectors that discharge high. 
       FIGS. 25   a - c  llustrate circuits  2500 - 2504  according to further embodiments of the present invention. These circuits are similar to those of  FIG. 24   a - c  except that the read select transistors are removed. 
       FIGS. 26   a - c  illustrate circuits  2600 - 2604  according to further embodiments of the present invention. These circuits are similar to those of  FIGS. 25   a - c  except the read bitline is replaced with a capacitor. Charge loss induced by incident charged particles creates a variable voltage drop across the capacitor. 
     It should be understood that the above embodiments are not limited to a specific process technology, namely an SOI or a Bulk Silicon process, but rather intended to be utilized with a variety of process technologies. Such technologies may include Bulk (junction isolated) CMOS or BICMOS, SOI (oxide insulated) CMOS or BICMOS including: floating-body SOI, body-tie SOI, an SOI employing a mix, and partially depleted or fully depleted SOI, thick or thin SOI, junction isolated implemented on thick SOI, or CMOS based non-volatile technologies. 
     While certain features and embodiments of the present application have been described in detail herein, it is to be understood that the application encompasses all modifications and enhancements within the scope and spirit of the following claims.