Abstract:
A reference voltage generation circuit includes a first current mirror including first through third transistors with the second transistor on a reference side thereof, a second current mirror including fourth and fifth transistors connected in series with the first and the second transistors, respectively, and a voltage control block for controlling the source-drain voltages the transistors on the output side of the first current mirror. The voltage control block includes a first control block having a configuration similar to the first current mirror, and a second control block having a configuration similar to the second current mirror, both of which are connected between the first current mirror and the second current mirror, with corresponding transistors connected in series. A stable output voltage can be obtained irrespective of variations in the potential of the voltage source for the reference voltage generation circuit.

Description:
BACKGROUND OF THE INVENTION 
     (a) Field of the Invention 
     The present invention relates to a reference voltage generation circuit for use in a semiconductor device, and more particularly, to a reference voltage generation circuit for providing a stable output voltage therefrom over a wide voltage range of the power source for the reference voltage generation circuit. 
     (b) Description of the Related Art 
     A reference voltage generation circuit is used in various kinds of semiconductor devices in order to stabilize circuit operation and semiconductor characteristics. For example, because of need for a voltage higher than a source voltage or need for a negative voltage, a nonvolatile memory device includes a booster circuit having a voltage regulating circuit so as to output a constant voltage. The reference voltage generation circuit is used in the voltage regulating circuit as a reference voltage source. 
     In the nonvolatile memory device, if an output voltage from the reference voltage generation circuit varies, the variation is amplified in the voltage regulating circuit, resulting in significant variation in an output voltage from the voltage regulating circuit. Since the output voltage of the voltage regulating circuit determines, for example, the amount of electrons to be injected into the floating gate of a nonvolatile memory cell, a reduction in the output voltage causes a reduction in the amount of electrons injected, thereby affecting the data holding characteristic of the nonvolatile memory device. In other words, variation in the output voltage of the reference voltage generation circuit impairs the reliability of the nonvolatile memory device. 
     Further, the reference voltage generation circuit determines the amount of current flowing through the internal circuits of a semiconductor device. Thus, variation in the output voltage of the reference voltage generation circuit causes significant variation in the current dissipation of the entire semiconductor device. Since a semiconductor device having current dissipation which does not meet a product standard or specification is rejected in a test, variation in the output voltage of the reference voltage generation circuit may impair the yield of semiconductor devices. 
     FIG. 1 is a circuit diagram of a conventional reference voltage generation circuit using a bandgap voltage of diode. The reference voltage generation circuit includes the following elements: a first current mirror circuit CM 1  which includes p-channel transistors P 1 , P 2 , and P 3 , among which the transistor P 2  is disposed on the reference side; a second current mirror circuit CM 4  which includes n-channel transistors N 1  and N 2  connected in series with the transistors P 1  and P 2 , respectively, and in which the transistor N 1  is disposed on the reference side; a diode D 1  connected in series with the transistors P 1  and N 1 ; a resistor R 1  and a diode D 2  connected in series with the transistors P 2  and N 2 ; and a resistor R 2  and a diode D 3  connected in series with the transistor P 3 . 
     The transistors P 1 , P 2 , and P 3  have the same design dimension, and the transistors N 1  and N 2  have the same design dimension. An output voltage Vout is determined from a current Io output from the transistor P 3  and the resistor R 2 . The diodes D 2  and D 3  are each composed of a plurality of (N) diodes that have the same design dimension as the diode D 1  and are connected in parallel with one another. 
     The respective source terminals of the transistors P 1  and P 2  are connected to a voltage source Vdd, and the respective gate terminals of the transistors P 1  and P 2  are connected together. Accordingly, the transistors P 1  and P 2  are identical in drain current and gate-to-source voltage. Since the respective gate terminals of the transistors N 1  and N 2  are connected together, the transistors N 1  and N 2  have the same gate voltage. Assuming that the transistors N 1  and N 2  have the same dimensions, the transistors N 1  and N 2  have the same threshold voltage, which provides the same source potential therebetween. The bandgap voltages of the diodes D 1  and D 2  provide following expression. 
     
       
         R 1 (I 0 +( kT/q )ln(I 0 /I SD2 )=( kT/q )ln(I 0 /I SD1 )  
       
     
     where I 0  is a current flowing through the transistors P 1 , P 2 , and P 3 , I SD1  and I DS2  are the respective saturation currents of the diodes D 1  and D 2 ; T is an absolute temperature; k is a Boltzman constant; and q is the charge of an electron. 
     The above expression is arranged to the expression given in terms of Io as follows: 
     
       
         Io=(1/R 1 )×( kT/q )×ln N   (1)  
       
     
     Wherein N is the number of diodes D 1 . 
     Thus, the output voltage Vout is expressed by 
     
       
         Vout=χR 1 ×Io+( kT/q )×ln(I 0   /N ·I SD1 )  
       
     
     Wherein χ=R 2 /R 1 . 
     By substitution of Expression (1) into the above expression, Vout is expressed by 
     
       
         Vout=( kT/q )×[(χ−1)ln N +ln{( kT/q )/R 1 ·I SD1 )}+ln (ln N )}]  (2)  
       
     
     When the respective nodes connected to the drains of the transistors P 1 , P 2 , and P 3  are represented by nodes A, B, and C, the potential at node A is the sum of threshold voltage Vtn of the transistor N 1  and forward voltage drop VD 1  of the diode D 1 ; the potential at node B is equal to a value obtained through the subtraction of threshold voltage Vtp of the transistor P 2  from the source voltage Vdd; and the potential at node C is Vout as represented by Expression (2). 
     Even when the source voltage Vdd for the reference voltage generation circuit varies, the source-to-drain voltage Vsd of the transistor N 1  and that of the transistor P 2  remain substantially unchanged; however, the respective source-to-drain voltages Vsd of the transistors P 1 , P 3 , and N 2  vary in association with variation in the source voltage Vdd. That is, the current I 0  flowing through current paths of each of the current mirror circuits CM 1  and CM 4  and the output voltage Vout vary in association with variation in the source voltage Vdd. As mentioned previously, variation in the reference voltage causes various drawbacks in semiconductor devices. Thus, variation in the output of the reference voltage generation circuit should be suppressed to a small magnitude. 
     FIG. 2 is a graph showing a voltage-current characteristic of an ordinary transistor, measured in a sate in which the gate-to-source voltage Vgs is fixed to a certain level. In FIG. 2, the Y axis represents a drain current Id, and the X axis represents the source-to-drain voltage Vsd. In a transistor, as the source-to-drain voltage Vsd increases with the gate-to-source voltage Vgs fixed at a certain level, the drain current Id increases. As a channel length (a distance between the source and the drain) L of a MOS transistor decreases, the amount of an increase in the drain current Id increases. This is because, as the channel length L decreases, the influence of the expansion of a depletion layer increases significantly. 
     FIG. 3 is a graph showing variation in drain current accompanying variation in the source voltage Vdd for the reference voltage generation circuit. When an output current I 2  is determined by the transistors N 1  and N 2 , the source-to-drain voltage Vsd of the transistor P 2 , which is connected to function as a diode, is determined. The gate voltage of the transistor P 3  is also determined. When the source voltage Vdd varies, the source-to-drain voltage Vsd of the transistor P 3  increases. In this case, if the channel length L is relatively short, the output current varies significantly from I 2  to I 3 . 
     In the reference voltage generation circuit, variation in output current due to variation in source voltage can be suppressed to a small magnitude by increasing the channel length L, as shown in FIG.  2 . However, when the channel length L is increased, a channel width W must be increased accordingly in order to maintain the transconductance of the transistor unchanged, causing a problem in that the surface area of a chip increases. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, an object of the present invention is to provide a reference voltage generation circuit that generates an output voltage to a high degree of accuracy over a wide range of source voltage for the reference voltage generation circuit without involving an increase in the surface area of a chip. 
     The present invention provides a reference voltage generation circuit comprising: a first current mirror including first through third transistors of a first conductivity type, the first through third transistors having sources connected together and implementing a first output side, a reference side and a second output side, respectively, of the first current source; a second current mirror including fourth and fifth transistors of a second conductivity type opposite to the first conductivity type, the fourth and fifth transistors implementing a reference side and an output side, respectively, of the second current mirror, the fourth and fifth transistors being connected in series with the first and second transistors, respectively; first and second current sources (R 1 , R 2 ) connected in series with the second and fifth transistors and with the third transistor, respectively, for defining current flowing therethrough; and a voltage control block for controlling a source-to-drain voltage of the first and third transistors within a specified range. 
     In accordance with the present inventions the voltage control block controls the output voltage of the reference voltage generation circuit irrespective of variation in the source voltage for the voltage generation circuit by controlling the source-to-drain voltage of the first and third transistors within the specified range. 
     The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a conventional reference voltage generation circuit; 
     FIG. 2 is a graph illustrating the effect of channel length L on drain current Id vs source-to-drain voltage Vsd; 
     FIG. 3 is a graph showing variation in drain current Id due to variation in source-to-drain voltage; 
     FIG. 4 is a circuit diagram of a reference voltage generation circuit according to a first embodiment of the present invention; 
     FIG. 5 is a graph showing the voltage-current characteristics of p-channel transistors P 2  and P 3  of a current mirror circuit; 
     FIG. 6 is a graph showing the voltage-current characteristics of transistors P 5  and P 6  of a source-to-drain voltage control circuit; 
     FIG. 7 is a circuit diagram of a reference voltage generation circuit according to a second embodiment of the present invention; and 
     FIG. 8 is a circuit diagram of a reference voltage generation circuit according to a third embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiments of the present invention will now be described in detail with reference to the drawings, wherein similar constituent elements are designated by similar reference numerals throughout the drawings. 
     Referring to FIG. 4, a reference voltage generation circuit according to a first embodiment of the present invention includes a first current mirror circuit CM 1 , a first source-to-drain voltage control circuit Vsd 1 , a second source-to-drain voltage control circuit Vsd 2 , and a second current mirror circuit CM 4 . The first current mirror circuit CM 1  includes a p-channel transistor P 2  disposed on the reference side and p-channel transistors P 1  and P 3  disposed on the output side. The first source-to-drain voltage control circuit Vsd 1  is composed of p-channel transistors P 4  to P 6  such that the gate terminals of the transistors P 4  to P 6  are connected together and such that the drain and gate terminals of the transistor P 5  are connected together. The second source-to-drain voltage control circuit Vsd 2  is composed of n-channel transistors N 3  and N 4  such that the gate terminals of the transistors N 3  and N 4  are connected together and such that the drain and gate terminals of the transistor N 3  are connected together. The second current mirror circuit CM 4  includes an n-channel transistor N 1  disposed on the reference side and an n-channel transistor N 2  disposed on the output side. 
     The transistors P 1 , P 4 , N 3 , and N 1  are connected in this serial order as viewed from a voltage source Vdd, thereby forming a first current path. The transistors P 2 , P 5 , N 4 , and N 2  are connected in this serial order as viewed from the voltage source Vdd, thereby forming a second current path. The transistors P 3  and P 6  are connected in this serial order as viewed from the voltage source Vdd, thereby forming a third current path. 
     The reference voltage generation circuit further includes a diode D 1  connected between the ground and the source terminal of the transistor N 1  in the first current path; a resistor R 1  and a diode D 2  connected in series between the ground and the source terminal of the transistor N 2  in the second current path; and a resistor R 2  and a diode D 3  connected in series between the ground and the drain terminal of the transistor P 6  in the third current path. The drain of the transistor P 6  forms an output node Vout. The diodes D 2  and D 3  are each composed of a plurality of (N) diodes that have the same design dimensions as the diode D 1  and are connected in parallel with one another. 
     The operation of the reference voltage generation circuit according to the present embodiment will next be described with reference to the graphs of FIGS. 5 and 6. FIGS. 5 and 6 show the voltage-current characteristics of the p-channel transistors disposed on the reference and output sides. Numerals ( 1 ) to ( 9 ) appearing in FIGS. 5 and 6 denote the sequence of operation and correspond to items of description below. 
     First, the operation of the transistors P 2  and P 3  will be described. 
     (1) By virtue of the resistor R 1  acting as a current source and the diodes D 1  and D 2  providing a bandgap voltage, the current I 2  assumes a predetermined value as described previously in the section of the prior art. 
     (2) Since the gate and drain terminals of the transistor P 2  are connected together, the relationship between the drain current Id and the source-to-drain voltage Vsd of the transistor P 2  exhibits a diode characteristic. Accordingly, the source-to-drain voltage Vsd of the transistor P 2  is determined in correspondence to the current I 2 . 
     (3) The relationship between the drain current Id and the source-to-drain voltage Vsd of the transistor P 3  substantially exhibits a constant-current characteristic so long as the gate-to-source voltage Vsg of the transistor P 3  is constant. 
     (4) Since the respective gate terminals of the transistors P 2  and P 3  are connected together, the gate-to-source voltage Vgs of the transistor P 3  is equal to the source-to-drain voltage Vsd of the transistor P 2 . That is, the transistors P 2  and P 3  operate at the intersection of two characteristic curves of FIG. 5, thus establishing I 2 =I 3 . 
     Next, the operation of the transistors P 5  and P 6  will be described. Since the gate and drain terminals of the transistor P 5  are connected together, the drain voltage of the transistor P 5  is equal to a value obtained through the subtraction of the sum of the threshold voltages of the transistors P 2  and P 5  from the source voltage Vdd. The source voltage of the transistor P 6  is equal to a value obtained by subtracting the sum of the threshold voltages of the transistors P 2  and P 5  from the source voltage Vdd and adding to the resultant difference the threshold voltage of the transistor P 6 . The threshold voltage of the transistor P 5  is equal to that of the transistor P 6 . Accordingly, the source voltage of the transistor P 6  is equal to a value obtained through the subtraction of the threshold voltage of the transistor P 2  from the source voltage Vdd, and the drain voltage of the transistor P 2  becomes equal to that of the transistor P 3 . As described above in item (4), the drain current I 3  of the transistor P 3  is equal to I 2 . 
     (5) Since the transistor P 5  is disposed in the second current path in which the transistor P 2  is disposed, the current I 2  flows through the transistor P 5 . 
     (6) Since the gate and drain terminals of the transistor P 5  are connected together, the relationship between the drain current Id and the source-to-drain voltage Vsd of the transistor P 5  exhibits a diode characteristic. Accordingly, when the drain current I 2  is determined, the source-to-drain voltage Vsd (P 5 ) corresponding to the drain current I 2  is determined. 
     (7) Assuming that the source terminal of the transistor P 6  is connected to a constant-voltage source, the transistor P 6  exhibits a constant-current characteristic as in the case of the transistor P 3 . Specifically, the gate-to-source voltage Vgs of the transistor P 6  exhibits a characteristic curve equivalent to that of the source-to-drain voltage Vsd(P 5 ) of the transistor P 5 . When the source-to-drain voltage Vsd of the transistor P 6  is equal to the source-to-drain voltage Vsd(P 5 ) of the transistor P 5 , the drain current I 3  of the transistor P 6  becomes equal to the drain current I 2 . 
     (8) When the source voltage Vdd increases, the source-to-drain voltage Vsd of the transistor P 6  disposed at the output side of the first source-to-drain voltage control circuit Vsd 1  increases, because a voltage appearing across the resistor R 2  is substantially constant. Accordingly, the drain current I 3  of the transistor P 6  shows a tendency to increase. However, as described above in item (4), the transistor P 3  limits the current flowing therethrough, resulting in that the drain voltage of the transistor P 3  is slightly decreased. 
     (9) As a result, the gate-to-source voltage Vsg of the transistor P 6  decreases; thus, even when the source voltage Vdd increases, the drain current  13  of the transistor P 6  settles to the current I 2  determined by the transistor P 2 . 
     In the above description, only the relationship between the operation of the transistors P 2  and P 3  as well as that of the transistors P 5  and P 6  is described. As will be readily understood, the same applies to the p-channel transistor P 1  disposed at the output side of the current mirror circuit CM 1  and the n-channel transistor N 2  disposed at the output side of the current mirror circuit CM 4 . 
     According to the first embodiment, through employment of source-to-drain voltage control circuit for controlling the source-to-drain voltage of the transistor disposed at the output side of the current mirror circuits, variation in output current is suppressed. Specifically, through addition of the p-channel transistors P 4  to P 6  and the n-channel transistors N 3  and N 4  to a conventional reference voltage generation circuit using a band-gap voltage, the source-to-drain voltages Vsd of the transistors P 1 , P 3 , and N 2  disposed at the output side of the current mirror circuits can be limited. As a result, variation in voltage occurring in the load resistors R 1  and R 2  can be suppressed, so that the reference voltage can be generated to a high degree of accuracy. Even when employed transistors have a relatively short channel length L, the output voltage is stabilized, thus, the stabilization of output voltage is compatible with a reduction in the chip surface area of a semiconductor device. 
     Referring to FIG. 7, a reference voltage generation circuit according to a second embodiment of the present invention is similar to the first embodiment except that the diodes D 1  to D 3  are omitted and that the dimension of the transistor N 2  is a multiple (for example, 4 times) of that of the transistor N 1 . Assuming that the transistors N 1  to N 3  have a threshold voltage Vth, the transistors P 1  to P 6  have a threshold voltage Vtp, and currents I 1  to I 3  flow through the first to third current paths, respectively, the drain voltage of the transistor N 3  becomes equal to 2Vtn; accordingly, the source voltage of the transistor N 4  assumes Vtn. Even when the source voltage Vdd varies, the drain voltage of the transistor N 2  assumes a constant value of Vtn. Accordingly, the source-to-drain voltage Vsd of the transistor N 2  is constant; thus, even when the source voltage Vdd varies, the drain current I 2  of the transistor N 2  is constant. The reference voltage generation circuit of the present embodiment, therefore, can suppress variation in reference current I 2  which would otherwise accompany variation in source voltage. 
     Similarly, in the case of the transistors P 1  and P 3  of the current mirror CM 1  the source-to-drain voltage Vsd can be limited to the threshold voltage Vtp of a p-channel transistor. The drain voltage of the transistor P 1  is equal to that of the transistor P 3  and is equal to a value obtained through the subtraction of the threshold voltage Vtp of a p-channel transistor from the source voltage Vdd. 
     Accordingly, even when the source voltage Vdd varies, the source-to-drain voltage Vsd of each of the transistors P 1  and P 3  is substantially fixed at a constant level. That is, the output voltage Vout can be held constant. 
     Referring to FIG. 8, a reference voltage generation circuit according to a third embodiment of the present invention includes a reference voltage generation section  52  configured in a manner similar to that of the conventional reference voltage generation circuit of FIG. 1 and a voltage limiter  51  provided on the source voltage side of the reference voltage generation section  52 . 
     FIG. 3 shows variation in drain current accompanying variation in source voltage Vdd 1  for the reference voltage generation section  51 . When an output current I 2  is determined by the transistors N 1  and N 2 , the source-to-drain voltage Vsd of the transistor P 2 , which is connected to function as a diode, is determined. The gate voltage of the transistor P 3  is also determined. When the source voltage Vdd 1  varies, the source-to-drain voltage Vsd of the transistor P 3  increases. In this case, if the channel length L is relatively short, the output current varies significantly from I 2  to I 3 . 
     The voltage limiter  51  includes a resistor R 23 , n-channel transistors N 23 , N 24 , and N 25 , and a p-channel transistor P 27 . The transistors N 23 , P 27 , and N 25  are each connected to function as a diode. The resistor R 23  and the transistors N 23 , P 27 , and N 25  are connected in this serial order between the voltage source Vdd and the ground. The resistor R 23  is adapted to make a predetermined current flow to the transistors N 23 , P 27 , and N 25 . Each of the transistors N 23 , P 27 , and N 25  is connected such that the gate and drain terminals thereof are connected together. Since the threshold voltage Vtp plus a voltage equivalent to Vtn is built between the source and drain terminals of each of the transistors N 23 , P 27 , and N 25 , the drain voltage of the transistor N 23  assumes (Vtp+2×Vtn). Thus the sum of the threshold voltages of a p-type transistor and two n-type transistors is provided to the gate of transistor N 24 . The transistor N 24  implements a source follower circuit. The source voltage of the transistor N 24  is equal to a value obtained through the subtraction of the threshold voltage Vtn from the gate voltage of the transistor N 24 . Accordingly, the source voltage of the transistor N 24  assumes (Vtp+Vtn); for example, about 2 V. The drain terminal of the transistor N 24  is connected to the source voltage line Vdd 1  of the reference voltage generation section  52 . The transistor N 23  is adapted to compensate a voltage drop of the transistor N 24 . Alternatively, if a sufficiently large voltage is obtained only by use of the transistors P 27  and N 25  or when the employed transistor N 24  has a relatively small threshold voltage, the transistor N 23  may be omitted. Thus the gate of transistor N 24  receives a voltage equal to the sum of the threshold voltages of a p-type transistor and an n-type transistor. The configuration of the voltage limiter  51  is not limited to that of the present embodiment, but may be modified so long as variation in source voltage can be suppressed to a small magnitude. 
     According to the present embodiment, the voltage limiter  51  is adapted to limit a source potential for the p-channel transistors P 1  to P 3  of the first current mirror circuit CM 1  constituting the reference voltage generation section  52 , thereby limiting the source-to-drain voltage Vsd of each of the transistors P 1  to P 3  to a predetermined range. 
     As described above, the source voltage input to the p-channel transistors P 1  to P 3  of the reference voltage generation section  52  is maintained at a constant level through voltage limit, thereby outputting a voltage to a high degree of accuracy over a wide range of the source voltage for the reference voltage generation circuit; for example, even when the source voltage Vdd ranges from 2.0 V to 5.0 V. An increase in the chip size of the reference voltage generation circuit is not involved. 
     The present embodiment requires an additional area in which the voltage limiter  51  is to be formed. However, since an area occupied by the MOSFET decreases in proportion to the square of the channel length L, an area occupied by the reference voltage generation circuit can be decreased through reduction in the channel length L even when the voltage limiter  51  is additionally formed. For example, by reducing the channel length L of a MOSFET from 100 μm to 20 μm, then area occupied by the MOSFET reduces by a factor of 25, thereby reducing an area occupied by the reference voltage generation circuit. 
     Since the above embodiments are described only for examples, the present invention is not limited to the above embodiments and various modifications or alterations can be easily made therefrom by those skilled in the art without departing from the scope of the present invention.