Abstract:
Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    This disclosure claims the benefit of U.S. Provisional Patent Application Ser. No. 61/245226, filed on Sep. 23, 2009, the disclosure thereof incorporated by reference herein in its entirety. 
     
    
     FIELD 
       [0002]    The present disclosure relates generally to use of spread-spectrum clocking. More particularly, the present disclosure relates to acquisition and tracking of spread-spectrum clocks embedded in serial data streams. 
       BACKGROUND 
       [0003]    Spread-spectrum clocking has emerged as a cost-effective technique for reducing the spectral density of electromagnetic interference (EMI) generated by synchronous communications systems. With a regular clock, the EMI is concentrated near the frequency of the clock. Spread-spectrum clocking varies the frequency or phase of the clock, thereby spreading the EMI over a broader spectrum. Spread-spectrum clocking is used in many areas, for example in serial communications having an embedded clock signal. 
         [0004]    Acquiring and tracking such a clock signal can be difficult. Failure to track the clock signal results in unacceptably high bit error rates. One common remedy is to keep the spreading of the clock signal at the transmitter within a narrow range to facilitate clock recovery at the receiver. Of course, this limits the efficacy of the spreading in reducing EMI. 
       SUMMARY 
       [0005]    In general, in one aspect, an embodiment features an apparatus comprising: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal. 
         [0006]    Embodiments of the apparatus can include one or more of the following features. Some embodiments comprise a memory having a plurality of locations each configured to store a respective sum of a sample of the error signal from the current spread-spectrum cycle of the spread-spectrum clock signal and a corresponding sample of the error signal from the previous spread-spectrum cycle of the spread-spectrum clock signal; wherein the phase selector is further configured to provide the recovered spread-spectrum clock signal based on the sums. In some embodiments, the memory comprises: a chain of D-flip-flops each configured to provide one of the locations of the memory. Some embodiments comprise an adder configured to provide the sums. Some embodiments comprise an interpolator configured to interpolate the samples prior to the adder providing the sums. Some embodiments comprise a loop filter configured to filter the error signal generated by the phase detector according to one or more loop parameters. Some embodiments comprise a controller configured to provide the one or more loop parameters, wherein the loop controller provides a first set of loop parameters to acquire the spread-spectrum clock signal and a second set of loop parameters to track the spread-spectrum clock signal. Some embodiments comprise a receiver comprising: the apparatus and a deserializer configured to recover data from the serial data stream based on the recovered spread-spectrum clock signal. Some embodiments comprise a communication device comprising the receiver. 
         [0007]    In general, in one aspect, an embodiment features a method comprising: generating an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and providing the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal. 
         [0008]    Embodiments of the method can include one or more of the following features. Some embodiments comprise generating a plurality of sums, wherein each of the sums represents a sum of a respective sample of the error signal from the current spread-spectrum cycle of the spread-spectrum clock signal and a corresponding sample of the error signal from the previous spread-spectrum cycle of the spread-spectrum clock signal; and providing the recovered spread-spectrum clock signal based on the sums. Some embodiments comprise filtering the generated error signal according to one or more loop parameters. Some embodiments comprise providing a first set of loop parameters for acquiring the spread-spectrum clock signal; and providing a second set of loop parameters for tracking the spread-spectrum clock signal. Some embodiments comprise recovering data from the serial data stream based on the recovered spread-spectrum clock signal. 
         [0009]    In general, in one aspect, an embodiment features computer-readable media embodying instructions executable by a computer to perform a method comprising: generating an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and providing the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal. 
         [0010]    Embodiments of the computer-readable media can include one or more of the following features. In some embodiments, the method further comprises: generating a plurality of sums, wherein each of the sums represents a sum of a respective sample of the error signal from the current spread-spectrum cycle of the spread-spectrum clock signal and a corresponding sample of the error signal from the previous spread-spectrum cycle of the spread-spectrum clock signal; and providing the recovered spread-spectrum clock signal based on the sums. In some embodiments, the method further comprises: filtering the generated error signal according to one or more loop parameters. In some embodiments, the method further comprises: providing a first set of loop parameters for acquiring the spread-spectrum clock signal; and providing a second set of loop parameters for tracking the spread-spectrum clock signal. In some embodiments, the method further comprises: recovering data from the serial data stream based on the recovered spread-spectrum clock signal. 
         [0011]    The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. 
     
    
     
       DESCRIPTION OF DRAWINGS 
         [0012]      FIG. 1  shows elements of a data communication system according to one embodiment. 
           [0013]      FIG. 2  shows elements of the deserializing receiver of  FIG. 1  according to one embodiment. 
           [0014]      FIG. 3  shows a process operated by the deserializing receiver of  FIG. 2  according to one embodiment. 
           [0015]      FIG. 4  shows a process operated by the CDR module of  FIG. 2  according to one embodiment. 
           [0016]      FIG. 5  shows a plot of an example spread-spectrum cycle of a spread-spectrum clock signal. 
           [0017]      FIG. 6  shows detail of the memory of  FIG. 2  according to one embodiment. 
           [0018]      FIG. 7  shows a process operated by the CDR module of  FIG. 2  in acquiring and tracking a spread-spectrum clock signal according to one embodiment. 
           [0019]      FIG. 8  shows two plots of clock phase vs. time. 
           [0020]      FIG. 9  shows an enlarged portion of the plots of  FIG. 8 . 
           [0021]      FIG. 10  shows a plot of clock phase (represented by a voltage) vs. time. 
           [0022]      FIG. 11  shows a plot of clock phase error (represented by a voltage) vs. time. 
       
    
    
       [0023]    The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears. 
       DETAILED DESCRIPTION 
       [0024]    The subject matter of the present disclosure relates to acquisition and tracking of spread-spectrum clocks embedded in serial data streams. Various embodiments are described in the context of gigabit SERDES (serializer/deserializer). However, the disclosed techniques are applicable to other types of communications systems and data rates. According to the disclosed embodiments, a clock detection and recovery unit records phase errors during each spread-spectrum cycle of the spread-spectrum clock, and employs the recorded errors in subsequent cycles to achieve dramatically improved acquisition and tracking of spread-spectrum clocks. This improvement permits the use of larger spread-spectrum clock ranges, resulting in reduced EMI. 
         [0025]      FIG. 1  shows elements of a data communication system  100  according to one embodiment. Although in the described embodiments the elements of data communication system  100  are presented in one arrangement, other embodiments may feature other arrangements. For example, elements of data communication system  100  can be implemented in hardware, software, or combinations thereof. 
         [0026]    Referring to  FIG. 1 , data communication system  100  includes a first communication device  102  transmitting a serial data stream  108  to a second communication device  104  over a serial communications channel  106 . Serial data stream  108  has an embedded clock signal. For example, serial data stream  108  can be a gigabit SERDES data stream or the like. 
         [0027]    Communication device  102  includes a serializing spread-spectrum-clock transmitter  110 . Serializing transmitter  110  receives n-bit parallel data  112  and a clock signal  114 , and serializes the data according to a spread-spectrum clock signal  124  to produce a serial data stream  108  having embedded spread-spectrum clock signal  124 . Transmitter  110  transmits serial data stream  108  over serial communications channel  106 . 
         [0028]    Communication device  104  includes a deserializing spread-spectrum-clock receiver  116 . Deserializing receiver  116  receives serial data stream  108  over serial communications channel  106 , recovers embedded spread-spectrum clock signal  124  as recovered spread-spectrum clock signal  126 , and outputs n-bit parallel data  118  and a clock signal  120  based on serial data stream  108  and recovered spread-spectrum clock signal  126 . 
         [0029]      FIG. 2  shows elements of deserializing receiver  116  of  FIG. 1  according to one embodiment. Although in the described embodiments the elements of deserializing receiver  116  are presented in one arrangement, other embodiments may feature other arrangements. For example, elements of deserializing receiver  116  can be implemented in hardware, software, or combinations thereof. 
         [0030]    Referring to  FIG. 2 , deserializing receiver  116  includes an input circuit  202 , a clock detection and recovery (CDR) module  204 , a deserializer  206 , and an output circuit  208 . CDR module  204  includes a controller  210 , a phase detector  212 , a phase selector  214 , a loop filter  216 , a memory  218 , and adders  220 A and  220 B. CDR module  204  can also include an interpolator  222 . Phase detector  212  can be implemented as a bang-bang-type phase detector. Phase selector  214  can be implemented as an oscillator with multi-phase outputs. 
         [0031]      FIG. 3  shows a process  300  operated by deserializing receiver  116  of  FIG. 2  according to one embodiment. Although in the described embodiments the elements of process  300  are presented in one arrangement, other embodiments may feature other arrangements. For example, in various embodiments, some or all of the steps of process  300  can be executed in a different order, concurrently, and the like. 
         [0032]    Referring to  FIGS. 2 and 3 , at  302  input circuit  202  receives serial data stream  108  over serial communications channel  106 . At  304 , CDR module  204  recovers the embedded clock signal from serial data stream  108  as recovered spread-spectrum clock signal  126 . At  306 , deserializer  206  deserializes serial data stream  108  based on recovered spread-spectrum clock signal  126 , producing n-bit parallel data  118 . At  308 , output circuit  208  outputs deserialized n-bit parallel data  118  and clock signal  120 . 
         [0033]      FIG. 4  shows a process  400  operated by CDR module  204  of  FIG. 2  according to one embodiment. Although in the described embodiments the elements of process  400  are presented in one arrangement, other embodiments may feature other arrangements. For example, in various embodiments, some or all of the steps of process  400  can be executed in a different order, concurrently, and the like. 
         [0034]    Referring to  FIGS. 2 and 4 , at  402  phase detector  212  generates an error signal  224  based on recovered spread-spectrum clock signal  126  and serial data stream  108 . Error signal  224  represents a phase difference between recovered spread-spectrum clock signal  126  and serial data stream  108 . 
         [0035]    At  404  controller  210  provides one or more loop parameters  226  to loop filter  216 . Controller  210  provides a first set of loop parameters  226  to acquire the spread-spectrum clock signal embedded in serial data stream  108 , and a second set of loop parameters  226  to track the spread-spectrum clock signal, as described in greater detail below. At  406  loop filter  216  filters error signal  224  according to loop parameters  226 , thereby producing filtered error signal  228 . The sampling rate of filtered error signal  228  may differ from the sampling rate of the error samples stored in memory  218 . If the sampling rates differ, at  408  interpolator  222  interpolates the samples of filtered error signal  228  accordingly. If the sampling rates are the same, interpolator  222  is not needed. 
         [0036]    At  410 , phase selector  214  provides recovered spread-spectrum clock signal  126  based on the error signal  224  from a current spread-spectrum cycle of spread-spectrum clock signal  124  and the error signal  224  from a previous spread-spectrum cycle of spread-spectrum clock signal  124 . The term “spread-spectrum cycle” is used herein to refer to a cycle of clock spreading, as opposed to an individual clock cycle of clock signal  124 .  FIG. 5  shows a plot of an example spread-spectrum cycle of a spread-spectrum clock signal. In the example of  FIG. 5 , the spread-spectrum cycle is a periodic sinusoid when plotted as a graph of phase difference vs. time. The duration of the spread-spectrum cycle is shown in  FIG. 5  as period T. 
         [0037]    Returning to  FIG. 2 , memory  218  has a plurality of locations  230 . Each location  230  is used to store a respective sum of a sample of error signal  224  from a current spread-spectrum cycle of spread-spectrum clock signal  124  and a corresponding sample of error signal  224  from a previous spread-spectrum cycle of spread-spectrum clock signal  124 . Adder  220 A provides the sums to memory  218 . Adder  220 B provides the sums to phase selector  214 . Phase selector  214  provides recovered spread-spectrum clock signal  126  based on the sums. 
         [0038]    Memory  218  is configured as a memory barrel having a number of locations  230  equal to the number of samples of error signal  224  taken during a single spread-spectrum cycle of spread-spectrum clock signal  124 . For example, according to one embodiment, memory  218  has 48 locations. Of course, other numbers of samples and locations can be used instead.  FIG. 6  shows detail of memory  218  according to one embodiment. Referring to  FIG. 6 , memory  218  is implemented as a chain of D-flip-flops (DFF)  602 A- 602 N clocked by a common clock  604 . Each D-flip-flop  602  provides one of the locations  230  of memory  218 . 
         [0039]      FIG. 7  shows a process  700  operated by CDR module  204  of  FIG. 2  in acquiring and tracking spread-spectrum clock signal  124  according to one embodiment. Although in the described embodiments the elements of process  700  are presented in one arrangement, other embodiments may feature other arrangements. For example, in various embodiments, some or all of the steps of process  700  can be executed in a different order, concurrently, and the like. 
         [0040]    Referring to  FIG. 7 , acquisition operations are shown at  702 , while tracking operations are shown at  704 . In some cases, when the spread-spectrum clock range is sufficiently narrow, acquisition operations  702  are unnecessary, and process  700  can begin with tracking operations  704 . Now process  700  is described, beginning with acquisition operations  702 . 
         [0041]    At  706  CDR module  204  is initialized, for example by applying power, clearing locations  230  in memory  218 , and the like. At  708  controller  210  provides a set of loop parameters  226  that is selected for acquisition of spread-spectrum clock signal  124 . Loop parameters  226  can include parameters such as gain, bandwidth, latency, and the like. Loop parameters  226  selected for acquisition can differ from loop parameters  226  selected for tracking, for example by specifying greater bandwidth and the like. Loop filter  216  receives loop parameters  226  and operates accordingly. 
         [0042]    At  710 , CDR module  204  acquires spread-spectrum clock signal  124 . During an initial spread-spectrum cycle of spread-spectrum clock signal  124 , CDR module  204  acquires the phase curve of spread-spectrum clock signal  124 , which is stored in memory  218 . During subsequent spread-spectrum cycles, CDR module  204  acquires spread-spectrum clock signal  124 . At  712 , after CDR module  204  has acquired spread-spectrum clock signal  124 , controller  210  provides a set of loop parameters  226  that is selected for tracking spread-spectrum clock signal  124 . Loop filter  216  receives loop parameters  226  and operates accordingly. At  714 , CDR module  204  is tracking spread-spectrum clock signal  124 . At  716 , if at any time CDR module  204  fails to track spread-spectrum clock signal  124 , process  700  can return to acquisition operations  702 . 
         [0043]      FIGS. 8-11  demonstrate the operation of the described embodiments where the transmitter and receiver experience a frequency shift. In addition, the spread-spectrum clock range is gradually increased at the transmitter. The nominal frequency of the transmitter spread-spectrum clock is 29.5 kHz, while the nominal frequency of the receiver clock is 30 kHz. 
         [0044]      FIG. 8  shows two plots of clock phase vs. time. The upper plot represents the transmitter clock, while the lower plot represents the receiver clock.  FIG. 9  shows an enlarged portion of the plots of  FIG. 8 . From a comparison of the plots, it is clear that the waveforms match well, indicating good clock tracking. 
         [0045]      FIG. 10  shows a plot of clock phase (represented by a voltage) vs. time. The transition from acquisition to tracking is apparent at t=33 microseconds. 
         [0046]      FIG. 11  shows a plot of clock phase error (represented by a voltage) vs. time. The error clearly remains within a small, limited range. 
         [0047]    Various embodiments can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Embodiments can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps can be performed by a programmable processor executing a program of instructions to perform functions by operating on input data and generating output. Embodiments can be implemented in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits). 
         [0048]    A number of implementations have been described. Nevertheless, various modifications may be made without departing from the scope of the disclosure. Accordingly, other implementations are within the scope of the following claims.