Abstract:
A Gilbert cell mixer for a wireless transceiver includes a first stage that performs voltage to current conversions and that includes first and second transistors that are operated in a saturation region and third and fourth transistors that are operated in a triode region. A second stage communicates with the first stage and that performs frequency conversion. A biasing circuit communicates with the first stage to maintain a substantially constant input linear range over temperature and process variations.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims the benefit of U.S. Provisional Application No. 60/443,395, filed on Jan. 29, 2003. The disclosure of the above application is incorporated herein by reference. 

   FIELD OF THE INVENTION 
   The present invention relates to mixers, and more particularly to a biasing circuit for Gilbert cell mixers in wireless transceivers. 
   BACKGROUND OF THE INVENTION 
   Referring now to  FIG. 1 , a wireless transceiver  10  is shown and includes a transmitter  12  and a receiver  14 . The wireless transceiver  10  may be used in a local area network (LAN) and may be attached to a Baseband Processor (BBP) and a Media Access Controller (MAC) in either a station or an Access Point (AP) configuration. A network interface card (NIC) is one of the various “STATION” configurations. The NIC can be connected to a networked device  16  such as a laptop computer, a personal digital assistant (PDA) or any other networked device. When the transceiver  10  is attached to an access point (AP) MAC, an AP is created. The AP provides network access for wireless local area network (WLAN) stations that are associated with the transceiver  10 . 
   The wireless transceiver  10  transmits and receives frames/packets and provides communication between two networked devices. In AdHoc mode, the two devices can be two laptop/personal computers. In infrastructure mode, the two devices can be a laptop/personal computer and an AP. 
   There are multiple different ways of implementing the transmitter  12  and the receiver  14 . For purposes of illustration, simplified block diagrams of super-heterodyne and direct conversion transmitter and receiver architectures will be discussed, although other architectures may be used. Referring now to  FIG. 2A , an exemplary super-heterodyne receiver  14 - 1  is shown. The receiver  14 - 1  includes an antenna  19  that is coupled to an optional RF filter  20  and a low noise amplifier  22 . An output of the amplifier  22  is coupled to a first input of a mixer  24 . A second input of the mixer  24  is connected to an oscillator  25 , which provides a reference frequency. The mixer  24  converts radio frequency (RF) signals to intermediate frequency (IF) signals. 
   An output of the mixer  24  is connected to an optional IF filter  26 , which has an output that is coupled to an automatic gain control amplifier (AGCA)  32 . An output of the AGCA  32  is coupled to first inputs of mixers  40  and  41 . A second input of the mixer  41  is coupled to an oscillator  42 , which provides a reference frequency. A second input of the mixer  40  is connected to the oscillator  42  through a −90° phase shifter  43 . The mixers  40  and  41  convert the IF signals to baseband (BB) signals. Outputs of the mixers  40  and  41  are coupled to BB circuits  44 - 1  and  44 - 2 , respectively. The BB circuits  44 - 1  and  44 - 2  may include low pass filters (LPF)  45 - 1  and  45 - 2  and gain blocks  46 - 1  and  46 - 2 , respectively, although other BB circuits may be used. Mixer  40  generates an in-phase (I) signal, which is output to a BB processor  47 . The mixer  41  generates a quadrature-phase (Q) signal, which is output to the BB processor  47 . 
   Referring now to  FIG. 2B , an exemplary direct conversion receiver  14 - 2  is shown. The receiver  14 - 2  includes the antenna  19  that is coupled the optional RF filter  20  and to the low noise amplifier  22 . An output of the low noise amplifier  22  is coupled to first inputs of RF to BB mixers  48  and  50 . A second input of the mixer  50  is connected to oscillator  51 , which provides a reference frequency. A second input of the mixer  48  is connected to the oscillator  51  through a −90° phase shifter  52 . The mixer  48  outputs the I-signal to the BB circuit  44 - 1 , which may include the LPF  45 - 1  and the gain block  46 - 1 . An output of the BB circuit  44 - 1  is input to the BB processor  47 . Similarly, the mixer  50  outputs the Q signal to the BB circuit  44 - 2 , which may include the LPF  45 - 2  and the gain block  46 - 2 . An output of the BB circuit  44 - 2  is output to the BB processor  47 . 
   Referring now to  FIG. 3A , an exemplary super-heterodyne transmitter  12 - 1  is shown. The transmitter  12 - 1  receives an I signal from the BB processor  47 . The I signal is input to a LPF  60  that is coupled to a first input of a BB to IF mixer  64 . A Q signal of the BB processor  47  is input to a LPF  68  that is coupled to a first input of a BB to IF mixer  72 . The mixer  72  has a second input that is coupled to an oscillator  74 , which provides a reference frequency. The mixer  64  has a second input that is coupled to the oscillator through a −90° phase shifter  75 . 
   Outputs of the mixers  64  and  72  are input to a summer  76 . The summer  76  combines the signals into a complex signal that is input to a variable gain amplifier (VGA)  84 . The VGA  84  is coupled to an optional IF filter  85 . The optional IF filter  85  is connected to a first input of an IF to RF mixer  86 . A second input of the mixer  86  is connected to an oscillator  87 , which provides a reference frequency. An output of the mixer  86  is coupled to an optional RF filter  88 . The optional RF filter  88  is connected to a power amplifier  89 , which may include a driver. The power amplifier  89  drives an antenna  90  through an optional RF filter  91 . 
   Referring now to  FIG. 3B , an exemplary direct conversion transmitter  12 - 2  is shown. The transmitter  12 - 2  receives an I signal from the BB processor  47 . The I signal is input to the LPF  60 , which has an output that is coupled to a first input of a BB to RF mixer  92 . A Q signal of the BB processor  47  is input to the LPF  68 , which is coupled to a first input of a BB to RF mixer  93 . The mixer  93  has a second input that is coupled to an oscillator  94 , which provides a reference frequency. The mixer  92  has a second input that is connected to the oscillator  94  through a −90° phase shifter  95 . Outputs of the mixers  92  and  93  are input to the summer  76 . The summer  76  combines the signals into a complex signal that is input the power amplifier  89 . The power amplifier  89  drives the antenna  90  through the optional RF filter  91 . The RF and IF filters in  FIGS. 2A ,  2 B,  3 A and  3 B may be implemented on-chip or externally. 
   Regardless of the architecture that is used, one of the primary functions performed by the transmitters and receivers is frequency conversion from BB to IF to RF and from RF to IF to BB. As described above, frequency conversion is performed in the mixers. Performance requirements of the mixers include conversion gain, noise and linearity. 
   In particular, mixer linearity is often a key parameter for systems with high performance requirements. In a receiver, mixer linearity affects the ability of the receiver to receive weak desired signals in the presence of strong adjacent-channel interference. In a transmitter, poor mixer linearity can cause excessive corruption in the transmitter spectrum and degrade signal integrity of the transmitter. 
   The mixers in the WLAN transceiver  10  can be implemented using Gilbert cell mixers. Referring now to  FIG. 4A , a Gilbert Cell mixer  110  that is implemented using CMOS transistors according to the prior art is shown. The Gilbert cell mixer  110  includes a first stage  112  that performs voltage to current conversion or transconductor stage and a second stage  114  that performs frequency conversion. 
   The Gilbert cell mixer  110  includes a transconductor stage that is formed by a first transistor  122  and a second transistor  124 . The transistors  122  and  124  have a source that is connected to a reference potential such as ground. A gate of the first transistor  122  is connected to one lead of a first voltage source. A gate of the second transistor  124  is connected to another lead of the first voltage source. The Gilbert cell mixer  110  further includes third, fourth, fifth, and sixth transistors  130 ,  132 ,  134 , and  136 . A drain of the first transistor  122  is coupled to sources of the third and fourth transistors  130  and  132 . A drain of the second transistor  124  is coupled to sources of the fifth and sixth transistors  134  and  136 . 
   A gate of the fourth transistor  132  is connected to a gate of the fifth transistor  134 . The gates of the fourth and fifth transistors  132  and  134  are connected to a first lead of a second voltage source. Another lead of the second voltage source is connected to gates of the third and sixth transistors  130  and  136 . A drain of the third transistor  130  is connected to a drain of the fifth transistor  134 . A drain of the fourth transistor  132  is connected to a drain of the sixth transistor  136 . Typically, the first voltage source is a radio frequency, intermediate frequency, or baseband signal requiring frequency conversion (up or down) and the second voltage source is a local oscillator. 
   When implemented in the form of  FIG. 4A , linearity of the Gilbert cell mixer is typically limited by the bottom transconductance stage. Moreover, depending on the biasing scheme, the linearity performance will vary over temperature and process corners. 
   SUMMARY OF THE INVENTION 
   A Gilbert cell mixer for a wireless transceiver includes a first stage that performs voltage to current conversion. The first stage includes first and second transistors that are operated in a saturation region and third and fourth transistors that are operated in a triode region. A second stage communicates with the first stage and performs frequency conversion. A biasing circuit communicates with the first stage and maintains a constant input linear range over temperature and process variations. 
   In other features, the transistors are implemented using complementary metal oxide semiconductor (CMOS) technology. The first stage further includes fifth and sixth transistors having sources connected to drains of the first and second transistors. Seventh and eighth transistors have sources connected to drains of the third and fourth transistors and drains connected to drains of the fifth and sixth transistors. 
   In yet other features, the biasing circuit includes a first voltage source that generates a first voltage that biases gates of the fifth and sixth transistors. A second voltage source generates a second voltage that biases gates of the seventh and eighth transistors. A third voltage source generates a third voltage that biases gates of the first, second, third and fourth transistors. 
   In other features, the second stage further includes ninth, tenth, eleventh, and twelfth transistors. Drains of the fifth and seventh transistors communicate with sources of the ninth and tenth transistors. The drains of the sixth and eighth transistors communicate with sources of the eleventh and twelfth transistors. The tenth and eleventh transistors have gates that communicate with a first lead of a second input voltage source. The ninth and twelfth transistors have gates that communicate with a second lead of the second input voltage source. 
   In still other features, the input linear range is proportional to V Dsat  of the third and fourth transistors. 
   In other features, the biasing circuit includes a current source. A first resistance communicates with the current source. A second resistance communicates with the first resistance. A third resistance communicates with the second resistance. A transistor has a drain that communicates with the third resistance and a gate that communicates with the drain. The transistor has a low current density such that V GS  of the transistor is approximately equal to V T  of the transistor. A first voltage generated between the current source and the first resistor biases gates of the fifth and sixth transistors. A second voltage generated between the first and second resistors biases gates of the seventh and eighth transistors. A third voltage generated between the second and third resistors biases gates of the first, second, third and fourth transistors. The first, second and third resistances can be poly resistors. 
   Further areas of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein: 
       FIG. 1  is a functional block diagram of an exemplary wireless transceiver according to the prior art; 
       FIG. 2A  is a functional block diagram of an exemplary super-heterodyne receiver architecture according to the prior art; 
       FIG. 2B  is a functional block diagram of an exemplary direct receiver architecture according to the prior art; 
       FIG. 3A  is a functional block diagram of an exemplary super-heterodyne transmitter architecture according to the prior art; 
       FIG. 3B  is a functional block diagram of an exemplary direct transmitter architecture according to the prior art; 
       FIG. 4A  is an electrical schematic of a Gilbert cell mixer implemented using CMOS transistors according to the prior art; 
       FIG. 4B  illustrates I D  as a function of V GS  for a CMOS transistor; 
       FIG. 5  illustrates a Gilbert cell mixer including a compensated input transconductor stage according to the present invention; 
       FIGS. 6A ,  6 B and  6 C show transconductance (g m ) of transistor pairs as a function of differential input voltage for triode operation, saturated operation and combined operation, respectively; 
       FIG. 7  illustrates a cascode configuration according to the prior art; and 
       FIG. 8  is an electrical schematic of a constant V Dsat  biasing circuit according to the present invention. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. 
   The biasing circuit for a Gilbert cell mixer according to the present invention enables the realization of linear transconductance over a constant linear input range using temperature sensitive transistor technologies such as CMOS technology. The present invention does not reduce mixer gain unlike conventional linearization schemes such as negative feedback. The present invention provides linearization without requiring high voltage headroom that is required by linearization using conventional emitter or source degeneration. The present invention establishes a linear relationship between transconductance and the bias current. As a result, a transconductance calibration methods can be used, for example see “Mixer Gain Calibration Method and Apparatus”, Ser. No. 10/292,087, filed Nov. 11, 2002, which is hereby incorporated by reference in its entirety. 
   In the Gilbert-cell mixer  110  in  FIG. 4A , the linearity of the mixer  110  is limited by the linearity of the first or input transconductor stage  112 . Mixer linearity can be improved by linearizing the input transconductance stage  112 . Referring now to  FIG. 5 , a Gilbert cell mixer  150  according to the present invention is shown and includes a compensated input transconductor stage  154 . The compensated input transconductor stage  154  includes two transconductors that are connected in parallel. The first transconductor includes a first pair of transistors  160  and  162  that are biased into a saturation region. The second transconductor includes a second pair of transistors  166  and  168  that are biased into a triode region. The opposite gain characteristics of the first and second transconductors cancel each other and improve the overall linearity of the transconductor stage  154 . 
   Sources of the transistors  160 ,  162 ,  166 , and  168  are connected to a reference potential such as ground. The compensated input transconductor stage  154  further includes transistors  170 ,  172 ,  174 , and  176 . A source of the transistor  170  is connected to a drain of the transistor  160 . A gate of the transistor  170  is connected to a gate of the transistor  176 . A drain of the transistor  170  is connected to a drain of the transistor  172  and to sources of the transistors  130  and  132 . A gate of the transistor  172  is connected to a gate of the transistor  174 . 
   A drain of the transistor  176  is connected to a drain of the transistor  174  and to sources of the transistors  134  and  136 . A source of the transistor  174  is connected to a drain of the transistor  168 . A source of the transistor  176  is connected to a drain of the transistor  162 . A gate of the transistor  162  is connected to a gate of the transistor  168 . A gate of the transistor  160  is connected to a gate of the transistor  166 . The transistors  170 ,  172 ,  174 , and  176  preferably provide biasing for the transistors  160 – 168 . 
   Linearity of the mixer  150  can be improved by using the compensated input transconductor stage  154 . However, when the mixer  150  is implemented using CMOS technology, the input linear range of the mixer  150  can vary significantly with temperature and process variations. 
   Referring now to  FIGS. 6A ,  6 B and  6 C, with proper biasing and device sizing, a gain characteristic of the saturation transistors  160  and  162  (shown in  FIG. 6A ) can be substantially cancelled by a gain characteristic of the triode transistors  166  and  168  (shown in  FIG. 6B ). The combined gain of the triode and saturation transistor pairs forms a substantially flat gain response that is shown in  FIG. 6C . The flat gain response improves the linearity of the mixer  150 . 
   The linear input range of the combined transconductance is mainly determined by the range of differential input signals for which the transconductance of the triode pair exhibits an expansive gain characteristic. The expansive gain characteristic region is shown generally at  180  in  FIG. 6A  and a compressive gain characteristic region is shown generally at  182  in  FIG. 6A . 
   It is important for the triode pair to have a wide, expansive gain characteristic. Otherwise, the triode pair cannot be compensated by the compressive gain characteristic of the saturation pair to achieve the overall linearized transconductance. As the differential input signal increases beyond V Lin  in  FIG. 6A , the input transistor on one side of the triode pair ceases to be in the triode region and enters the saturation region. When this happens, the transconductance of the triode pair (one of which is in saturation) decreases as the absolute value of V in  increases. In other words, the transconductance characteristics of the triode pair becomes compressive. The combined compensation with the saturation pair is no longer linearized. 
   Referring now to  FIG. 7 , a simple cascode configuration is shown. The gate voltage of the bottom device is V G . As long as the bottom device is in saturation (V G −V T −V D &lt;0), the transconductance increases with V G . 
   
     
       
         
           
             
               
                 
                   
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           therefore, g m =K 1 (V G −V T );
           then g m ↑ as V G ↑.   
         
         
       
     
  
   However, once M 1  enters the triode region (V G −V T −V D &lt;0), the transconductance decreases as a function of V G . 
               I   D     =       K   1     ⁡     (         (       V   G     -     V   T       )     ⁢     V   D       -       V   D   2     2       )         ;         
therefore,
 
             g   m     =       K   1     [       (       V   D     -       (       V   G     -     V   T     -     V   D       )     ⁢       ∂     V   D         ∂     V   G             ]     ;             
since
 
   
     
       
         
           
             
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           then g m ↓ as V G ↑. 
         
       
     
  
   The cross-over point happens when V D =V G −V T . If V G ′ is the gate voltage at which the bottom device is on the verge of transitioning from triode to saturation region, then: 
                   K   2     2     ⁢       (       V   B     -     V   D     -     V   T       )     2       =         K   1     2     ⁢       (       V   G   ′     -     V   T       )     2         ;         
Let V G0 =V G  at an initial bias point and assume that V B  is biased at a constant
 
   voltage IR above V G0  such that V B V G0 +IR
         also consider that V D =V G ′−V T ;       

   Therefore, 
   
     
       
         
           
             
               
                 
                   
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   If V Lin =V G0 −V G =input linear range then 
                     K   2       K   1         ⁢     (       V   Lin     +     I   ⁢           ⁢   R       )       =       V   G0     -     V   Lin     -     V   T         ;         
therefore
 
             V   Lin     =           V   G0     -     V   T         1   +         K   2       K   1             -         IR   ⁢         K   2       K   1             1   +         K   2       K   1             .             
The first term on the right side of the “=” sign is proportional to V Dsat  of M1 at the initial bias. If the bias current I is designed to compensate for the temperature coefficient of the resistor R (for example if the bias current is implemented in the form of a bandgap voltage over the same type of resistor), the second term on the right side of the “=” sign is a constant over temperature and process.
 
Therefore,
   V   Lin   =a×V   Dsat +constant 
where “a” is a constant that depends on the relative sizing of the bottom cascode device. Therefore, the input linear range of the combined transconductance stage can be kept constant over temperature and process if the V Dsat  of the input device is kept constant.
 
   Referring now to  FIG. 8 , a constant V Dsat  biasing circuit  200  according to the present invention maintains a substantially constant input linear range over temperature and process corners. The input linear range of the compensated transconductor stage  154  is strongly dependent on the V Dsat  of the input devices. Without proper biasing, the input linear range can vary widely over temperature and process corners. 
   The constant V Dsat  biasing circuit  200  includes a current source  202  that provides a current I ref . A resistor  204  provides a resistance R 1 . A resistor  206  provides a resistance R 2 . A resistor  208  provides a resistance R 3 . The resistors  204 ,  206 , and  208  are connected in series to the current source  182 . The resistors  204 ,  206  and  208  are preferably poly resistors, although the resistors  204 ,  206  and  208  can be discrete resistors, external resistors, or any other resistors. A transistor  210  has a drain that is connected to one end of the resistor  208 . A gate of the transistor  210  is connected to the drain. 
   For the transistor  160  to operate in the saturation region, the following condition need to be met:
 
 V   DS     —     160   &gt;V   GS     —     160   −V   T     —     160 .
 
Therefore,  V   A   −V   GS     —     170   &gt;V   G   −V   T     —     160 ;
 
 V   A   −V   G   &gt;V   GS     —     170   −V   T     —     160 ; and
 
 I   ref *( R   2   +R   3 )&gt; V   GS     —     170   −V   T     —     160 .
 
For the transistor  166  to operate in the triode region, the following condition need to be met:
 
 V   DS     —     166   &lt;V   GS     —     166   −V   T     —     166 .
 
Therefore,  V   B   −V   GS     —     172   &lt;V   G   −V   T     —     166 ; and
 
 V   B   −V   G   =I   ref   *R   2   &lt;V   GS     —     172   −V   T     —     166 .
 
   The transistor  210  is biased at low current density such that V GS  ˜V T  and V G =V GS     —     210 +I ref *R 1  ≈V T +I ref *R 1 . V Dsat  of transistors  160 ,  162 ,  166 , and  168  is equal to V G −V T ≈I ref *R 1 , when I ref  is generated by a bandgap voltage over the same type of resistors R 1 , R 2  and R 3 . Therefore, I ref *R 1  (and therefore V Dsat  of transistors  160 ,  162 ,  166 , and  168 ) is constant over process corners and temperature. Decoupling capacitors to ground can be optionally added to node V A , V B , and V G  to stabilize the bias voltages. 
   The transistor  210  preferably has a channel length that is approximately the same as the transistor  160 . Therefore, the transistor  210  has approximately the same threshold voltage (V T ) as the transistor  160 . V Dsat     —     210  is approximately equal to V GS     —     210 −V T =I ref *R+V GS     —     160 −V T =I ref *R. As a result, I ref *R is independent of temperature and process variation. 
   In other words, the biasing circuit  200  provides a bias that is equal to (V T +V constant ). The V T  term in the voltage bias is equal to the V T  of the transistors  160 ,  166  and  162 ,  168  and is cancelled to provide the constant bias voltage V constant . 
   Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.