Abstract:
A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

Description:
BACKGROUND 
     Time-to-digital converters (TDCs) are digital circuits that measure the delay of a pulse signal and convert this delay directly into a digital signal. TDCs are widely used in precision time measurement instruments. TDCs may be produced using CMOS (Complementary Metal Oxide Semiconductor) processes, which are becoming increasingly prevalent in the semiconductor industry. 
     A time-analog-to-digital converter (TAD) is an analog-to-digital converter (ADC) that is implemented using time-to-digital conversion techniques. In one type of TAD, a variable delay is first extracted from the input signal, and this delay is then measured (digitized) by digital elements. The digital elements include a chain of delay units (DUs), which form a delay line. The DUs may be, e.g., CMOS inverters. This approach differs from conventional ADCs in that the entrance of the input signal is to a sampling stage and no analog devices are used. 
     In one type of TAD, the input signal is connected to the positive supply terminal, Vdd, of the inverters. A clocked pulse is applied to the gate of the first inverter in the delay line in order to obtain variable delays on the input pulse through the Vdd terminal, where the input signal is connected. After the signal dependent delay on the output pulse is obtained, the delay is digitized using a time-to-digital approach. Because no sample-and-hold circuit is needed, an all-digital design is possible. However, the input signal range to be digitized is limited due to the threshold values of devices in the delay line. Input voltages at the Vdd terminal lower than the threshold voltages of the PMOS and NMOS devices in the DUs (inverters) create a dead region in the conversion. 
     SUMMARY 
     In an embodiment, a TAD utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two delay lines which may include, e.g., CMOS inverter chains. Each delay line is connected to two supply lines. The supply lines for one delay line are connected to a higher potential supply line, e.g., Vdd, and the input signal voltage, respectively, and the supply lines of the other delay line are connected to the input signal voltage and a lower potential supply line, e.g., Vgnd, respectively. Each delay line is used to handle a different range of input voltages, thereby increasing the dynamic range of the TAD. 
     Each delay line may include a buffer between the chain of inverters and its output. Comparators may be used to compare the input signal to a first threshold voltage corresponding to a first range of input signal voltages and to a second threshold voltage corresponding to a second range of input signal voltages. 
     A clocked pulse is applied to each delay line, each delay line producing a signal dependent delay signal at its output. A selector selects the delay signal from the output from one of the delay lines based on the range of voltages in which the input signal lies. A filter then estimates the input signal voltage from the delay signal from the selected delay line output. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic diagram of a delay line including a chain of DUs according to an embodiment. 
         FIG. 1B  is a schematic diagram showing a more detailed view of DUs in  FIG. 1A . 
         FIG. 2  is a plot showing the results of a simulation utilizing the circuit shown in  FIG. 1 . 
         FIG. 3  is a plot showing the results of a simulation utilizing the circuit shown in  FIG. 1  in combination with a buffer circuit. 
         FIG. 4  is a schematic diagram of an inverter chain according to another embodiment. 
         FIG. 5  is a plot showing the results of a simulation utilizing the circuit shown in  FIG. 4 . 
         FIG. 6  is a plot showing the results of a simulation utilizing the circuit shown in  FIG. 4  in combination with a buffer circuit. 
         FIG. 7  is a schematic diagram of dual delay lines for use in a TAD according to an embodiment. 
         FIG. 8  is a schematic diagram of a comparator for use with the dual delay lines shown in  FIG. 7 . 
         FIG. 9  is a plot of the results of a simulation of a TAD utilizing the circuits shown in  FIGS. 7 and 8 . 
         FIG. 10  is a plot showing the voltage-to-delay response of the TAD used in  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
     As described above, one type of TAD utilizes a delay line including a chain of DUs, e.g., CMOS inverters. In operation the delay time between the input pulse and the output pulse is modulated by the input signal voltage. The number of DUs in the chain through which the input pulse passes within a sampling (integration) time is then output as conversion data. 
       FIG. 1A  shows a delay line  100 , also referred to as a voltage-to-delay converter (VDC), which may be used in the TAD. DUs  102  in the delay line may be CMOS inverters  110 , each of which includes a PMOS transistor  112  and an NMOS transistor  114 , as shown in  FIG. 1B . In this TAD, the variable delay is introduced by using the input signal  116  as Vdd for the inverters in the chain. A clocked pulse  118  is also applied to the gate of the first inverter in the delay line in order to obtain variable delays on the output pulse through the Vdd terminal, where the input signal is connected. After the signal dependent delay  120  on the output pulse  122  is obtained, the delay is digitized using a time-to-digital approach. 
     One drawback of this TAD occurs when the input signal is lower than the threshold voltages of the PMOS and NMOS devices in the inverter cells. An Hspice simulation was performed for the circuit  100  shown in  FIG. 1A . For this simulation, the pulse clock frequency was 4-MHz and the input signal (Vin) was applied from 0V at t=0 μs to 2.6V at t=2 μs as a ramp signal. 
     The results of the simulation are shown in  FIG. 2 . The input pulse  202  (dashed line) is shifted up in the figure for clarity, however, the signal actually swings from 0 (Vgnd) to 2.6V (Vdd). The straight line  204  is the output signal of the delay line. As clearly shown in this plot, the clock-edge-delay varies with the input signal Vin. For example, the delay  206  from input pulse  208  to output pulse  210  at approximately 1.1 μs is larger than the delay  212  from input pulse  214  to output pulse  216  at approximately 1.8 μs, where the input voltage at Vdd is higher at  214  than at  208 . This plot clearly shows that conversion suffers for signals below the threshold voltage of 0.8V, especially for signal levels closer to 0V. 
     A buffer (e.g., two inverters in series) with a regular supply voltage of 2.6V was added to the output to extract meaningful delay information for input signals from 0.8V to 2.6V, as shown in  FIG. 3 . However, as shown in the plot, the output pulse cannot be recovered properly for input signals lower than 0.8V. 
     In an embodiment, the dynamic range of the TAD is improved by adding an additional VDC circuit. In one VDC the input signal replaces the positive supply voltage (Vdd), as shown in  FIG. 1A , and in the other VDC  400  the input signal  402  replaces the negative supply voltage (Vgnd), as shown in  FIG. 4 .  FIG. 5  shows the simulation result for the VDC  400  shown in  FIG. 4 . The simulation conditions for  FIG. 5  are the same as that of  FIG. 2  except for the introduction of the input signal to these delay lines. As shown in the  FIG. 5 , by using Vin as Vgnd, signals below 0.8V can be converted whereas conversion suffers for signals above 1.8V (=2.6V–0.8V), especially for signal levels closer to 2.6V.  FIG. 6  shows the resulting digital output signal that appears after a buffer with a regular supply voltage of 2.6V was added to the output. 
       FIG. 7  shows the two delay lines  702  and  704 , each including a VDC  706 ,  708  and a buffer  710 , 712 . The output signal of VDC  706 , with Vin at the positive supply rail of the inverters in the chain, is labeled Voutp, and the output signal of the VDC  708 , with Vin at the negative supply rail of the inverters in the chain, is labeled Voutm. 
     As shown in  FIGS. 3 and 6 , Voutp provides best results for input signals above about 0.8V, and Voutm provides best results for input signals below about 1.8V. The appropriate output may be selected from Voutp and Voutm using two comparators  802  and  804 , as shown in  FIG. 8 . These comparators create two enable signals, either passing Voutp or passing Voutm, where the enable signal for Voutm is inverted by an inverter  806 . The threshold of these comparators, Vrefm and Vrefp, can be selected as, e.g., 1.2V and 1.4V, which will allow both of the VDC circuits a smooth transition around the mid-point of the supply rail. These levels can be adjusted based on the desired delay-voltage curvature. A counter  810  determines the delay by counting the number of DUs the input pulse passes through during an integration interval. A filter  812  coupled to the comparators  802 ,  804  uses this information and the identity of the selected delay line to estimate the input voltage corresponding to the measured delay. 
       FIG. 9  shows the results of a simulation using the circuits shown in  FIGS. 7 and 8 . As shown in the plot, delay-voltage readings are produced for the full range of 0V to 2.6V. 
       FIG. 10  shows a plot of the delay (from input pulse to output pulse) vs. input signal voltage. The ranges of operation are shown in region  1002  for VDC 1  and region  1004  for VDC 2 . As described above, the thresholds for the comparators may be adjusted based on the desired delay-voltage curve. In an alternative implementation, the results from both VDCs may be used in regions  1002  and  1004  and averaged to provide a more accurate reading. Again, the thresholds may be adjusted for the desired curve. 
     The TAD may be used as an alternative to standard ADCs in a variety of applications. 
     A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.