Abstract:
Updating code of a single processor in a multi-processor system includes commencing of a self-reset of a first processor if a bit is found in a first state, and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This Application is a Continuation of U.S. patent application Ser. No. 11/769,083, filed on Jun. 27, 2007. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates generally to multi-processor computing systems and, in particular, to updating the code for one processor in the system without affecting operation of other processors in the system. 
     2. Description of the Related Art 
     Some computing systems, such as storage systems, include a controller board, which contains a multi-processor embedded system. For example, one CPU (also referred to herein as a “server processor”) may function as a controller or server on an operating system while another CPU (referred to herein as a “host adapter processor” or “HA processor”) runs a low level and separate embedded microcode image that provides an interface to communicate with external hosts. Architected designs allow the CPUs to operate independently of each other. 
     When one CPU, such as the server processor, needs to load new code, it typically undergoes a “hardware reset” in order for it to reboot. Because both CPUs on the board are coupled to the same bridge, such a reset encompasses both processors, even though only one needs to reboot. Therefore, in order to load code for the server processor, both the HA processor and the server processor must be reset, taking down the path from the controller board to the host. 
     Moreover, many multi-processor embedded systems include two or more such controller boards, each of which contains a multi-processor embedded system. When the code for the server processors is to be updated, the boards perform the process described in the preceding paragraph one at a time to prevent both boards from being off-line simultaneously and taking down all paths to the host. Thus, after the first board completes the new code load, it performs a reset and comes back on-line. The next board then repeats the process. In a dual-board system, the paths through the first and second Host Adapters go down in succession. While there is always at least one path to the host, “ping-ponging” of path removal requires that there be a delay between loading the code on each controller board to give the host time to adjust, thereby increasing the code load time and the host must have its own code sufficiently advanced to handle the paths going down and back up again while the host may be attempting to perform normal operations, such as reading and writing to a storage unit attached to the controller boards. 
     SUMMARY OF THE INVENTION 
     The present invention provides a method for updating code of a single processor in a multi-processor system. Execution of a self-reset of a first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor. 
     The present invention also provides a computer program product of a computer readable medium usable with a programmable computer and having computer-readable code embodied therein for updating code of a single processor in a multi-processor system. The computer-readable code includes instructions for performing the steps of the method of the present invention. 
     The present invention further provides a method for deploying computing infrastructure, comprising integrating computer readable code into a multi-processor computing system, wherein the code, in combination with the computing system, is capable of performing the steps of the method of the present invention. 
     The present invention also provides a computing system having at least a first multi-processor controller. The first multi-processor controller includes a first server processor operable to execute operating system code for the first controller, a first host adapter processor operable to execute code providing an interface with attached hosts, a first bus to which first system resources are coupled, a first memory and a first bridge. The first bridge includes means for providing intercommunication among the first server processor, the first host adapter processor, the first bus and the first memory, a first interrupt control module and a first memory control module. The system further includes first logic associated with the first server processor. The first logic is configured to halt transactions processed by the first server processor without affecting processing of transactions by the first host adapter processor, receive new code, terminate the operating system code whereby all processes and threads being executed by the first server processor are terminated, commence execution of a self-reset of the first server processor, disable interrupts associated with the first server processor, reset only those first system resources exclusively associated with the first server processor, disable memory transactions associated with the first server processor, copy an image of the new code into memory associated with the first server processor, reset registers associated with the first server processor, and boot the new code for the first server processor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a multi-processor computing system in which the present invention may be implemented; 
         FIG. 2  is a high level functional diagram of a method of the present invention; and 
         FIG. 3  is a flowchart of a method of updating processor code in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     The components described herein with respect to the block diagram of  FIG. 1  have been labeled as in a manner so as to more particularly emphasize their function and implementation independence. For example, a component may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like. 
     Some components may also be implemented in software for execution by various types of processors. A component of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an component need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the component and achieve the stated function. Furthermore, the described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components and so forth. In other instances, well-known structures, components or operations are not shown or described in detail to avoid obscuring aspects of the invention. 
       FIG. 1  is a block diagram of a multi-processor computing system  100  in which the present invention may be implemented. The configuration of the system  100  is illustrated by way of example and not limitation. Although the present invention may be implemented in a system with any number of controller boards, including only one board, for clarity the illustrated system  100  includes two controller boards  110 A,  110 B. Each controller board  110 A,  110 B is interconnected with one or more hosts, represented by the host  10 , through a I/O port  112 A,  1128 . The interconnection with the host  10  may be a direct connection or through a network  20 . Both controller boards  110 A,  110 B include multiple processors. Although the present invention may be implemented on boards with any number of processors performing any of a number of functions, for clarity each board  110 A,  110 B in the illustrated example includes two processors, a host adapter (HA) processor  114 A,  114 B and a server processor  116 A,  116 B. The HA processors  114 A,  114 B are coupled to the respective I/O ports  112 A,  112 B. The HA processors  114 A,  114 B and server processors  116 A,  116 B are interconnected through a bridge  120 A,  120 B. Each bridge  120 A,  120 B includes an interrupt control module (ICM)  122 A,  122 B and a memory control module (MCM)  124 A,  124 B. Both controller boards  110 A,  110 B also include a memory device  118 A,  118 B coupled to the bridge  120 A,  120 B. Peripheral devices or board resources, collectively identified in  FIG. 1  as  130 A,  130 B are coupled to the bridge  120 A,  120 B through a bus  132 A  132 B. Resources may include, but are not limited to, hard disk drives, memory, network adapters, serial ports, flash chips, flash drives, 12C controller, etc. The bridges  120 A,  120 B are also interconnected with each other through the respective buses  132 A,  132 B. If, as in the illustrated example, the controller boards  110 A,  110 B are storage controller boards, one or more storage devices, represented by the storage device  30 , are coupled to the boards  110 A,  110 B through device adapters  134 A,  134 B, again either directly or through a network. It will be appreciated that other components may be a part of the system  100  or of the controller boards  110 A,  110 B but are not shown in  FIG. 1  for purposes of clarity and relevance to the present invention. 
     The flowcharts that are described herein are generally set forth as logical flow diagrams. As such, the depicted order and labeled steps are indicative of one embodiment of the presented process. Other steps and processes may be conceived that are equivalent in function, logic or effect to one or more steps, or portions thereof, of the illustrated process. Additionally, the format and symbols employed are provided to explain the logical steps of the process and are understood not to limit the scope of the process. Although various arrow types may be employed in the flowcharts, they are also understood not to limit the scope of the corresponding process. Indeed, the arrows and connectors are used to indicate only the general logical flow of the process. Additionally, the order in which a particular process occurs may or may not strictly adhere to the order of the corresponding steps shown. 
       FIG. 2  is a high level functional diagram of a method of the present invention, illustrating the flow of operations relative to other operations with relative time being represented by time indicators on the vertical arrow to the left of the diagram. The diagram begins at some time t 0  with the system  100  engaged in normal, full operation (step  200 ). That is, the two processors  114 A,  116 A of the first controller board  110 A are operating normally and the two processors  114 B,  116 B of the second controller board  110 B are operating normally. Subsequently, at time t 1 , the code for the server processor  116 A of the first controller board  110 A is updated (step  300 A) as described with respect to the flowchart of  FIG. 3 . The update is performed without disturbing the normal operation of the HA processor  114 A of the first controller board  110 A or of either processor  114 B,  116 B of the second controller board  110 B (step  202 ). Upon completion of the code update to the server processor  116 A at time t 2 , the server processor  116 A resumes its normal operation (step  204 ). 
     Next, the server processor  116 B of the second controller board  110 B is updated at time t 3  (step  300 B), also without affecting the operation of the other processors, including the just-updated server processor  116 A (step  206 ). Upon completion of the code update to the second server processor  116 B at t 4 , the server processor  116 B resumes its normal operation (step  208 ) and normal, full operation of the system continues at t 4  (step  210 ). 
       FIG. 3  is a more detailed flowchart of a method  300  (steps  300 A,  300 B of 
       FIG. 2 ) of updating processor code in accordance with the present invention. The processor to be updated (referred to in  FIG. 3  as “Proc. 1”) is halted (step  302 ) and the new code for Proc. 1 is received (step  304 ). Proc. 1 unpacks to new code and bums it into flash memory (not shown). Preferably, Proc. 1 sets a specified bit in memory to indicate that it will perform a self-reset (step  308 ) rather than a conventional hardware reset which would reset all processors, functions, interrupts and resources on the controller board and take down the communication path to the host. 
     Next, the operating system running on Proc. 1 is terminated (step  306 ), terminating all threads and processes being executed by Proc. 1. The bit is then checked (step  310 ). If (step  312 ) the bit is not set, then a full hardware reset is performed (step  314 ). If the bit is set, Proc. 1 commences a self-reset (step  316 ) and disables interrupts over which it has control (step  318 ). Proc. 1 then resets those resources over which it has exclusive control (step  320 ), leaving the resources being used exclusively by or being shared with the other processor (Proc. 2). Proc. 1 may become aware of resources which, if reset, would interfere with Proc. 2&#39;s use of another resource. If so, the reset process will wait until the resource may be reset without affecting the activities of Proc. 2; that resource may then be reset. 
     Proc. 1 next disables its memory translations (also known as switching to real mode addressing) to stop the operating system from executing memory access (step  322 ). Preferably, the process being executed on Proc. 1 jumps to a small piece of code in a well-known location in memory (a “Fastload”. as described in commonly-owned co-pending U.S. Patent Publication No. 2005/0125650, incorporated by reference in its entirety) (step  324 ) and the new code image is copied into the memory  124  (step  326 ). When the copy of the image has been completed, the registers over which Proc. 1 has control are reset as if they had undergone a hardware reset (step ( 328 ), Proc. 1 branches to the new code image and begins booting (step  330 ). The new operating system begins executing and the new microcode executes in the same fashion as if the boot occurred after a hardware reset. 
     The code update of the server processor  116 A (Proc. 1 in the above description of  FIG. 3 ) on the first controller board  110 A is performed without affecting the operation of the HA processor  114 A or of the operation of the server processor  116 B and HA processor  114 B on the second controller board  110 B. It will be appreciated that the process is not limited to a system with only two processors on each of two controller boards and the invention is not limited to the illustrated configuration. 
     It is important to note that while the present invention has been described in the context of a fully functioning data processing system, those of ordinary skill in the art will appreciate that the processes of the present invention are capable of being distributed in the form of a computer readable medium of instructions and a variety of forms and that the present invention applies regardless of the particular type of signal bearing media actually used to carry out the distribution. Examples of computer readable media include recordable-type media such as a floppy disk, a hard disk drive, a RAM, and CO-ROMs and transmission-type media. 
     The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. Moreover, although described above with respect to methods and systems, the need in the art may also be met with a computer program product containing instructions for updating code of a single processor in a multi-processor system or a method for deploying computing infrastructure comprising integrating computer readable code into a computing system for updating code of a single processor in a multi-processor system.