Abstract:
A time sequence circuit for a power supply unit includes first through tenth resistors, first and second electronic switches, first through fourth diodes, and a capacitor. Each of the first and second electronic switches includes first through third terminals. When the power supply unit outputs all voltages, the power supply unit outputs a high-voltage level power good signal. If one of the voltages is not outputted, the power supply unit outputs a low-voltage level power good signal.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a time sequence circuit for a power supply unit. 
         [0003]    2. Description of Related Art 
         [0004]    During a power-on operation of a computer, a motherboard of the computer may change a power-on signal PS_ON from a high-voltage level to a low-voltage level. When a power supply unit receives the low-voltage level power-on signal PS_ON, the power supply unit outputs different voltages, such as 3V3, 5V_SYS, 5V_STBY, and 12V_SYS voltages, at the same time. When all the different voltages are outputted, the power supply unit further outputs a high-voltage level power good signal after 100-500 milliseconds, and then the computer can start up. However, a user may use different types of power supply units, which may cause a time sequence of the power supply unit to be unsuitable for the motherboard. 
         [0005]    Therefore, there is room for improvement in the art. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWING 
         [0006]    Many aspects of the present disclosure can be better understood with reference to the following drawing(s). The components in the drawing(s) are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawing(s), like reference numerals designate corresponding parts throughout the several views. 
           [0007]    The FIGURE is a circuit diagram of an embodiment of a time sequence circuit for a power supply unit. 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    The disclosure is illustrated by way of example and not by way of limitation in the FIGURES of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean “at least one.” 
         [0009]    The FIGURE illustrates an embodiment of a time sequence circuit for a power supply unit  1 . The time sequence circuit comprises eleven resistors R 1 -R 11 , two BJT transistors Q 1  and Q 2 , five diodes D 1 -D 5 , and a capacitor C 1 . 
         [0010]    A cathode of the diode D 1  is coupled to a system power terminal 3V3 through the resistor R 1 , and is connected to ground through the resistor R 2 . An anode of the diode D 1  is coupled to a stand-by power terminal 5V_STBY through the resistor R 7 , and is also coupled to an anode of the diode D 4 . A cathode of the diode D 2  is coupled to a system power terminal 5V_SYS through the resistor R 3 , and is connected to ground through the resistor R 4 . An anode of the diode D 2  is coupled to the anode of the diode D 4 . A cathode of the diode D 3  is coupled to a system power terminal 12V_SYS through the resistor R 5 , and is connected to ground through the resistor R 6 . An anode of the diode D 3  is coupled to the anode of the diode D 2 . A cathode of the diode D 4  is connected to ground through the resistor R 8 , and is coupled to a base of the transistor Q 1 . An emitter of the transistor Q 1  is connected to ground. A collector of the transistor Q 1  is coupled to the stand-by power terminal 5V_STBY through the resistor R 9 , and is coupled to a base of the transistor Q 2  through the resistor R 11 . An anode of the diode D 5  receives a power-on signal PS_ON from a motherboard  30 . A cathode of the diode D 5  is coupled to the base of the transistor Q 2 . An emitter of the transistor Q 2  is connected to ground. A collector of the transistor Q 2  is coupled to the system power terminal 5V_SYS through the resistor R 10 , and is connected to ground through the capacitor C 1 . The collector of the transistor Q 2  is used to output a power good signal. 
         [0011]    During a power-on operation, if one of the system power terminals 3V3, 5V_SYS, or 12V_SYS does not output a system voltage, one of the diodes D 1 , D 2 , or D 3  is turned on. For example, if the system power terminal 3V3 does not output the system voltage, the diode D 1  is turned on, and the stand-by power terminal 5V_STBY is connected to ground through the resistors R 7  and R 2  in that order. Resistances of the resistors R 7  and R 2  can be changed accordingly to make the base of the transistor Q 1  be at a low-voltage level, such as logic 0, to make the transistor Q 1  turn off, and the base of the transistor Q 2  be at a high-voltage level, such as logic 1. At the same time, the system power terminals 5V_SYS and 12V_SYS output system voltages, and the diodes D 2  and D 3  are turned off, the power on signal PS_ON is at a low-voltage level during the power on operation, the diode D 5  is turned off, and the base of the transistor Q 2  is at a high-voltage level. Accordingly, the transistor Q 2  is turned on, and the collector of the transistor Q 2  outputs a low-voltage level power good signal. 
         [0012]    During the power-on operation, when the system power terminals 3V3, 5V_SYS, and 12V_SYS all output system voltages, the diodes D 1 , D 2 , and D 3  are turned off, and the base of the transistor Q 1  is at the high-voltage level. Accordingly, the transistor Q 1  is turned on, the collector of the transistor Q 1  is at a low-voltage level, the base of the transistor Q 2  is at the low-voltage level, and the transistor Q 2  is turned off. The system power terminal 5V_SYS charges the capacitor C 1  to delay for a predefined time duration. When the capacitor C 1  is fully charged, the collector of the transistor Q 2  outputs the high-voltage level power good signal. 
         [0013]    When in a stand-by state, the power on signal PS_ON is at the high-voltage level. Thus, the diode D 5  is turned on, and the transistor Q 2  is turned on, making the collector of the transistor Q 2  output a low-voltage level power good signal. 
         [0014]    In the embodiment, the transistors Q 1  and Q 2  are npn-type transistors. In other embodiments, the transistors can be replaced by other electronic switches, such as metal-oxide semiconductor field-effect transistors. 
         [0015]    While the disclosure has been described by way of example and in terms of a preferred embodiment, it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the range of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.