Abstract:
A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

Description:
BACKGROUND 
     The increased integration of multiple-cores and large shared caches in microprocessors may require improved energy-efficiency for core-to-core, core-to-cache and intra-core communication to sustain desired performance benefits within shrinking power envelopes. 
     The cycle time for a communication bus may be based on wire pitch, repeater sizes and worst-case switching activity. Worst-case switching activity for a communication path such as, by way of example and not by way of limitation, on an unshielded static bus, may involve neighboring wires switching simultaneously in opposite direction which may result in maximizing the Miller Coupling Factor for inter-wire coupling capacitance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter regarded as embodiments of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. Embodiments of the invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which: 
         FIG. 1  illustrates a representative communication path; 
         FIG. 2  illustrates a representative plurality of neighboring communication paths; 
         FIG. 3  is a schematic diagram of apparatuses for treating a signal and for decoding a treated signal; and 
         FIG. 4  is a timing diagram relating to various signals described in connection with  FIG. 3 . 
         FIG. 5  is a flow chart illustrating an embodiment of the method of the invention. 
     
    
    
     It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements. 
     DETAILED DESCRIPTION 
     In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. However, it will be understood by those skilled in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure embodiments of the invention. 
     Use of the terms “coupled” and “connected”, along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” my be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g. as in a cause an effect relationship). 
       FIG. 1  illustrates a representative communication path. In  FIG. 1 , a signal handling apparatus  10  may include a first flip-flop device  12  and a second flip-flop device  18  coupled by a communication network  19 . Communication network  19  may include a first inverter apparatus  14 , a second inverter apparatus  16  and communication paths  40 ,  42 . Additional inverter devices and communication paths may be provided between first flip-flop device  12  and second flip-flop device  18  (indicated by a broken line segment  44  in  FIG. 1 ). 
     First flip-flop device  12  may receive an input signal S IN  at a data input locus  20  and may receive a clock signal CLK at a clock input locus  22 . First flip-flop device  12  may present a signal S Synch  at an output locus  24 . Signal S Synch  may be synchronized to a particular edge of clock signal CLK such as, by way of example and not by way of limitation, a rising edge of clock signal CLK. 
     First inverter device  14  may have an input locus  26  and an output locus  28 . Input locus  26  may be coupled with output locus  24  of first flip-flop device  12 . First inverter device  14  may receive input signal S Synch  from first flip-flop device  12  at input locus  26  and may present an inverted input signal  S Synch    at output locus  28  for transmission on a communication path  40 , indicated schematically in  FIG. 1 . 
     Second inverter device  16  may have an input locus  30  and an output locus  32 . Input locus  30  may be coupled with communication path  40 . Second inverter device  16  may receive inverted input signal  S Synch    from communication path  40  at input locus  30  and may present a signal S Synch1  at output locus  32  for transmission on a communication path  42 . Signal S Synch1  may be substantially similar to input signal S Synch , but signal S Synch1  may be somewhat delayed with respect to S Synch  because of delays that may be imparted to signals traversing inverter devices  14 ,  16 . Signal S Synch1  presented at output locus  32  may traverse additional elements of communication network  19  (not shown in detail in  FIG. 1 ; indicated by broken line segment  44 ) to arrive at second flip-flop device  18 . 
     Second flip-flop device  18  may receive a signal S Synchn  at a data input locus  46  and may receive clock signal CLK at a clock input locus  48 . The encoded signal arriving at data input locus  46  may be referred to as S Synchn  because additional circuit elements may be traversed in communication network  19 . Signal S Synchn  may be generally in phase, but delayed, with respect to input signal S IN  if an even number of inverter devices are traversed in communication network  19 . Signal S Synchn  may be generally out of phase but delayed, with respect to encoded input signal S IN  if an odd number of inverter devices are traversed in communication network  19 . Second flip-flop device  18  may present an output signal S OUT  at an output locus  49 . 
       FIG. 2  illustrates a representative plurality of neighboring communication paths. In  FIG. 2 , neighboring communication paths  10   1 ,  10   2 ,  10   m  may be arranged in a generally parallel relation. The indicator “m” is employed to signify that there can be any number of communication paths in parallel. The inclusion of three communication paths  10   1 ,  10   2 ,  10   m  in  FIG. 2  is illustrative only and does not constitute any limitation regarding the number of communication paths that may be arranged in parallel when using embodiments of the invention. 
     Each of communication paths  10   1 ,  10   2 ,  10   m  may embody a respective signal handling apparatus  10  configured generally as described in connection with  FIG. 1 . As one skilled in the art of circuit layout may be aware, parallel communication paths, such as communication paths  10   1 ,  10   2 ,  10   m  may experience a respective in-line capacitance Cg, indicated schematically as in-line capacitances Cg 1 , Cg 2 , Cg m . As one skilled in the art of circuit layout may also be aware, parallel communication paths, such as communication paths  10   1 ,  10   2 ,  10   m  may experience coupling capacitance between adjacent communication paths, such as a coupling capacitance Cc 1  between communication paths  10   1 ,  10   2 , and a coupling capacitance CC 2  between communication paths  10   2 ,  10   m . 
     Increased capacitance in a communication path may slow communication of signals by that communication path. The slowing effect of coupling capacitors CC 1 , CC 2  may vary depending upon the relative phases of adjacent signals in respective communication paths  10   1 ,  10   2 ,  10   m . An illustrative signal phase for a signal S 1  may be illustrated as being present in communication path  10   1 . An illustrative signal phase for a signal S 2  may be illustrated as being present in communication path  10   2 . An illustrative signal phase for a signal S m  may be illustrated as being present in communication path  10   m . 
     If, by way of example and not by way of limitation, two adjacent communication paths  10   1 ,  10   2  may convey signals S 1 , S 2  substantially 180 degrees out of phase, a worst case capacitive coupling case may be presented, and communication in each of communication paths  10   1 ,  10   2  may be slowed. 
     Efficiency of a communication path may be significantly affected by coupling capacitance, and it may be advantageous to reduce occurrences of worst-case capacitive coupling between communication paths. 
       FIG. 3  is a schematic diagram of apparatuses for treating a signal and for decoding a treated signal In  FIG. 3 , a signal handling apparatus  11  may be illustrated in a configuration similar to signal handling apparatus  10  ( FIG. 1 ). Signal handling apparatus  11  may include flip-flop devices  12 ,  18 , inverter devices  14 ,  16  and a communication network  19  generally as described in connection with  FIG. 1 . In the interest of avoiding prolixity, details of signal handling apparatus  11  that are similar to signal handling apparatus  10  will not be repeated here. Signal handling apparatus  11  also may include an encoding treatment unit  50  and a decoding treatment unit  100 . 
     Encoding treatment unit  50  may be coupled with first flip-flop device  12  for receiving a signal ENC_IN at an input locus  54 . Encoding treatment unit  50  may include flip-flop devices  52 ,  70  and an AND logic device  60 . Flip-flop device  52  may receive signal ENC_IN at a data input locus  56  and may receive an inverted clock signal  CLK  at a clock input locus  58 . Flip-flop device  52  may present a signal A at an output locus  59 . 
     AND logic device  60  may have input loci  62 ,  64  and an output locus  66 . Input locus  64  may be coupled with output locus  59  of flip-flop device  52 . AND logic device  60  may receive signal A from flip-flop device  52  at input locus  64 . AND logic device  60  may receive signal ENC_IN at input locus  62 . AND logic device  60  may present a signal B at output locus  66 . 
     Flip-flop device  70  may receive signal B at a data input locus  72  and may receive clock signal CLK at a clock input locus  74 . Flip-flop device  70  may present an output signal ENC_OUT at an output locus  76  for provision to inverter device  14 . Flip-flop device  70  may be a double-edge flip-flop device. 
     Decoding treatment unit  100  may be coupled with communication path  19  for receiving a signal DEC_IN at an input locus  102 . Encoding treatment unit  100  may include flip-flop device  110  and an OR logic device  120 . Flip-flop device  110  may receive signal DEC_IN at a data input locus  112  and may receive an inverted clock signal  CLK  at a clock input locus  114 . Flip-flop device  110  may present a signal C at an output locus  116 . 
     OR logic device  120  may have input loci  122 ,  124  and an output locus  126 . Input locus  124  may be coupled with output locus  116  of flip-flop device  110 . OR logic device  10  may receive signal C from flip-flop device  110  at input locus  124 . OR logic device  120  may receive signal DEC_IN at input locus  122 . OR logic device  120  may present a signal DEC_OUT at output locus  126  for provision to flip-flop device  18 . 
     Flip-flop device  18  may receive signal DEC_OUT at a data input locus  46  and may receive clock signal CLK at a clock input locus  48 . Flip-flop device  18  may present an output signal FFREC at an output locus  49 . 
       FIG. 4  is a timing diagram relating to various signals described in connection with  FIG. 3 . In  FIG. 4 , a graphic plot  200  is presented with respect to a vertical axis  202  representing signal amplitude and a horizontal axis representing time. Various signals described in connection with  FIG. 3  are represented in  FIG. 4 : CLK, ENC_IN, A, B, ENC_OUT, DEC_IN, C, DEC_OUT and FFREC. 
     Clock signal CLK may be arranged to define a plurality of clock cycles, each clock cycle having two clock phases. Thus, clock signal CLK may define a first clock cycle during a time interval t 11 -t 21  having a first clock phase during a time interval t 11 -t 12  and a second clock phase during a time interval t 12 -t 21 . Clock signal CLK may define a second clock cycle during a time interval t 21 -t 31  having a first clock phase during a time interval t 21 -t 22  and a second clock phase during a time interval t 22 -t 31 . Clock signal CLK may define a third clock cycle during a time interval t 31 -t 41  having a first clock phase during a time interval t 31 -t 32  and a second clock phase during a time interval t 32 -t 41 . Clock signal CLK may define a fourth clock cycle during a time interval t 41 -t 51  having a first clock phase during a time interval t 41 -t 42  and a second clock phase during a time interval t 42 -t 51 . Clock signal CLK may define a fifth clock cycle during a time interval t 51 -t 61  having a first clock phase during a time interval t 51 -t 52  and a second clock phase during a time interval t 52 -t 61 . Clock signal CLK may define a sixth clock cycle during a time interval t 61 -t 71  having a first clock phase during a time interval t 61 -t 62  and a second clock phase during a time interval t 62 -t 71 . Clock signal CLK may define a seventh clock cycle during a time interval t 71 -t 81  having a first clock phase during a time interval t 71 -t 72  and a second clock phase during a time interval t 72 -t 81 . Clock signal CLK may define an eighth clock cycle during a time interval t 81 -t 91  having a first clock phase during a time interval t 81 -t 82  and a second clock phase during a time interval t 82 -t 91 . 
     Inverted clock signal  CLK  described in  FIG. 3  is not illustrated in  FIG. 4 . One skilled in the art of circuit design may understand that inverted clock signal  CLK  may be represented by a 180 degree inversion of clock signal CLK. 
     Regarding  FIGS. 3 and 4  together, signal ENC_IN may be applied to encoder treatment unit  50  at input loci  56 ,  62  and may have a duration of substantially one clock cycle (two clock phases). Signal ENC_IN may exhibit an excursion from a nominal value (e.g., zero) in a positive direction following time t 11  and may exhibit an excursion in a negative direction following time t 21  to return to its nominal value. Flip-flop device  52  may respond to receiving signals ENC_IN and  CLK  to generate signal A. Signal A may exhibit a positive excursion from a nominal value (e.g., zero) following time t 12 . Signal A may be synchronized with a rising edge of signal  CLK . Signal A may exhibit an excursion in a negative direction following time t 22  to return to its nominal value at the first positive excursion of signal CLK after signal ENC_IN exhibits a negative excursion. 
     AND logic device  60  may respond to receiving signals ENC_IN and A to generate signal B exhibiting a positive excursion from a nominal value (e.g., zero) following time t 12  (when both of signals A and ENC_IN may be positive). Signal B may exhibit an excursion in a negative direction following time t 22  to return to its nominal value after signal ENC_IN exhibits a negative excursion. 
     Flip-flop device  70  may respond to receiving signals B and CLK to generate signal ENC_OUT. Signal ENC_OUT may be synchronized to every clock edge of clock signal CLK, and may take on the value of signal B at each clock edge. Thus, signal ENC_OUT may exhibit a positive excursion from a nominal value (e.g., zero) following time t 21 , and signal ENC_OUT may exhibit an excursion in a negative direction following time t 22  to return to its nominal value. Signal ENC_IN from flip-flop device  12  is thus treated by encoding treatment unit  50  to present a treated signal ENC_OUT for transmission via communication network  19 . 
     Encoding treatment unit  50  thus may present a treated signal ENC_OUT that may have a positive excursion delayed one clock cycle (two clock phases) with respect to positive excursion of original signal ENC_IN, and may have a negative excursion delayed one clock phase with respect to negative excursion of original signal ENC_IN. 
     Unequal delays imposed upon positive excursions and negative excursions of signal ENC_IN to present treated signal ENC_OUT may assure that adjacent communication paths  10   1 ,  10   2 ,  10   m  ( FIG. 2 ) will never experience a worst case capacitive coupling condition because 180 degree out of phase encoded signals may not appear on respective communication networks  19  of various communication paths  10   1 ,  10   2 ,  10   m  ( FIG. 2 ). 
     An evaluation of positive excursions of signal ENC_IN occurring during time intervals t 31 -t 51  and t 61 -t 71  may reveal a similar treatment of signal ENC_IN to present an associated signal ENC_OUT. 
     If communication delay between output locus  76  and input locus  102  ( FIG. 3 ) may be assured to be greater than one clock phase, flip-flop device  18  may be able to accurately decode signal ENC_OUT. Accurate decoding of signal ENC_OUT or signal DEC_IN to assure faithful reproduction of information indicated by signal ENC_IN may be better assured by using decoding treatment unit  100 . 
     Signal DEC_IN may be received by decoding treatment unit  100  from communication network  19  at an input locus  102 . Signal DEC_IN may be related to signal ENC_OUT after signal ENC_OUT traverses communication network  19 . While traversing communication network  19  signal ENC_OUT may experience phase delays and signal inversions as described earlier herein in connection with signals S Synch1 , S Synchn  ( FIG. 1 ). Signal DEC_IN may be similar in amplitude and duration to signal ENC_OUT but delayed with respect to signal ENC_OUT. Signal DEC_IN may exhibit an excursion from a nominal value (e.g., zero) in a positive direction following time t 22  and may exhibit an excursion in a negative direction following time t 31  to return to its nominal value. Flip-flop device  110  may respond to receiving signals DEC_IN and  CLK  to generate signal C exhibiting a positive excursion from a nominal value (e.g., zero) following time t 52  (when both of signals  CLK  and DEC_IN may be positive). Signal C may be synchronized to a rising edge of clock signal  CLK . Signal C may exhibit an excursion in a negative direction following time t 62  to return to its nominal value at the first positive excursion of signal  CLK  after signal DEC_IN exhibits a negative excursion. 
     OR logic device  120  may respond to receiving signals DEC_IN and C to generate signal DEC_OUT exhibiting a positive excursion from a nominal value (e.g., zero) following time t 22 , following time t 42  and following time t 72  (when either one of signals C and DEC_IN may be positive). Signal C may exhibit an excursion in a negative direction following time t 62  to return to its nominal value after signal DEC_IN exhibits a negative excursion. Signal C may also be synchronized to a rising edge of clock signal  CLK . Signal DEC_IN received from communication network  19  may thus be treated by decoding treatment unit  100  to present a decoded signal DEC_OUT for use by flip-flop device  18 . 
     Flip-flop device  18  may respond to receiving signals DEC_OUT and CLK to generate signal FFREC exhibiting a positive excursion from a nominal value (e.g., zero) following time t 31  (when both of signals DEC_OUT and CLK may be positive). Signal FFREC may be synchronized to a rising edge of clock signal CLK. Signal FFREC may exhibit an excursion in a negative direction following time t 41  to return to its nominal value at the first positive excursion of signal CLK after signal DEC_OUT exhibits a negative excursion. Signal FFREC may substantially faithfully represent signal DEC_IN as to periodicity of beginnings of excursions, with some clock phase delays. Signal FFREC may substantially faithfully represent signal ENC_IN with some delay. 
       FIG. 5  is a flow chart illustrating an embodiment of the method of the invention. In  FIG. 5 , a method  300  may be used with a signal effecting a plurality of succeeding excursions departing from a value and returning to the value in a pattern in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of clock phases in each respective clock cycle. Method  300  may begin at a START locus  302 . Method  300  may continue by posing a query whether the signal has exhibited a signal excursion in a first direction, as indicated by a query block  304 . If the signal has exhibited a signal excursion in a first direction, method  300  may continue from query block  304  via a YES response line  306  to delay a respective excursion of the signal a first number of clock phases, as indicated by a block  308 . 
     Method  300  may continue, as indicated by a line  310 , by posing a query whether the signal has exhibited a signal excursion in a second direction, as indicated by a query block  314 . If the signal has not exhibited a signal excursion in a second direction, method  300  may proceed from query block  304  via a NO response line  312  directly to query block  314 . If the encoded signal has exhibited a signal excursion in a second direction, method  300  may continue from query block  314  via a YES response line  316  to delay a respective excursion of the encoded signal a second number of clock phases, as indicated by a block  318 . The second number of clock phases may not equal the first number of clock phases. 
     Method  300  may continue, as indicated by a line  320 , by posing a query whether the encoded signal continues, as indicated by a query block  324 . If the encoded signal has not exhibited a signal excursion in a second direction, method  300  may proceed from query block  314  via a NO response line  322  directly to query block  324 . If the encoded signal continues, method  300  may proceed from query block  324  via a YES response line  326  to a locus  328  to repeat steps represented by blocks  304 ,  308 ,  314 ,  318 ,  324 . If the encoded signal does not continue, method  300  may proceed from query block  324  via a NO response line to terminate, as indicated by an END locus  332 . 
     Embodiments of the method and apparatus permit treating a signal prior to transmission to reduce inter-path coupling capacitance between neighboring communication paths. While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.