Abstract:
A multiplexer circuit in a memory organized into page-portions has a plurality of bit-select multiplexers configured to couple a plurality of page-portion global bitlines to a sense amplifier input. A plurality of column address lines organized into data bytes comprises each page-portion. A plurality of column multiplexers couple the data bytes to the page-portion global bitlines such that each of the address lines comprising the data byte is coupled to one of the page-portion global bitlines.

Description:
TECHNICAL FIELD 
   The present invention relates to a semiconductor integrated circuit device, and more particularly to a memory circuit incorporating multiple column decoder connections. 
   BACKGROUND ART 
   In  FIG. 1 , a prior art bit-select circuit comprises multiple address bytes organized into eight bits each. Semiconductor memory chips usually organize a memory array into rows and columns. Each row of memory array elements shares a connection commonly known as a wordline. Each column of memory array elements shares a connection commonly known as a bitline (B 7 , B 6 , . . . , B 0 ). The specific intersection of a wordline and a bitline at a memory cell is used to provide a read and write capability for the cell. Typically, eight bitlines are organized as a byte, providing a conveniently sized grouping for handling data within the memory array. 
   Every bitline from the memory array is connected to peripheral logic outside the array by a passgate transistor.  FIG. 1  includes eight pass-gate transistors (only three shown) contained within a bit-select multiplexer (“mux”). During a memory read operation, eight pass gates connecting eight bitlines of the same byte to the peripheral logic are enabled by a y-decoder output signal (e.g., decoder signal Y 0  enables BYTE  0 ). When a subsequent eight bits of data are read, eight pass gates connecting eight bitlines of an adjacent byte are enabled by another y-decoder signal (i.e., decoder signal Y 1  enables BYTE  1 ). The pass-gate transistors coupled to the decoder signals (Y 0 , Y 1 , Y 127 ) are collectively known as the y-multiplexer or y-mux. 
   The bitline signals passed by the y-mux are connected in an organized fashion before being passed to a bit-select multiplexer. All B 0  bits from bytes  0  . . .  127  are connected to a global bitline GBL 0 . Similarly, all B 1  bits from bytes  0  . . .  127  are connected to a global bitline GBL 1 . Analogous connections are replicated with the remaining bitlines. The bit-select multiplexer selects one global bitline at a time during sensing, and couples the selected bitline to a sense amplifier SA. 
   However, the prior art bit-select multiplexer suffers from a deficiency as the memory size increases. Specifically, as the number of bytes in the memory page (also referred to as the memory page size) increases, the number of passgates connected to the global bitlines increases. This increases the electrical loading on the global bitlines, thus slowing down the sensing speed of the sense amplifier SA. Therefore, what is needed is a way to continually increase a number of bytes in a memory page while not increasing electrical loading on the bitlines, thereby maintaining the sensing speed of the sense amplifier. 
   SUMMARY OF THE INVENTION 
   The present invention divides the memory array into portions, in an exemplary embodiment, a lower page portion and an upper page portion. Each memory page addresses half of a total number of memory bytes, thereby reducing a length of global bitlines within the memory page. Separate memory page multiplexers are employed for the lower and upper memory pages with each multiplexer coupled to a common sense amplifier. 
   In operation, there is a bit select mux for each page portion. For example, only one of either a lower bit select mux or an upper bit select mux operates to select and couple a bitline to a sense amplifier at a given time. By operating in this way and allowing only one multiplexer to couple a bitline signal at any given time, read operations associated with the lower memory page do not interfere with read operations associated with the upper memory page. One skilled in the art will recognize that, when pages are separated into two portions, lower and upper global bitlines are half as long as the global bitlines in the prior art of  FIG. 1 . Consequently the global bitlines exhibit half as much electrical loading as the global bitlines of the prior art. A reduced global bitline length and loading of the present invention results in a commensurately higher speed operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a bit-select circuit as known in the prior art. 
       FIG. 2  is a schematic diagram of a bit-select circuit according to an exemplary embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   With reference to  FIG. 2 , an exemplary embodiment of a bit-select circuit  200  comprises a lower memory page portion  210  and an upper memory page portion  250 . A lower page y-mux portion  212  comprises address bytes BYTE 0  through BYTE 63  of the lower memory page portion  210  providing a total of 64 bytes addressed. An upper page y-mux portion  252  comprises address bytes BYTE 64  through BYTE 127  of the upper memory page portion  250  providing a total of 64 address bytes in the upper page, and a total of 128 address bytes considering the lower and upper memory pages in combination. Each of the address bytes BYTE 0  through BYTE 127  comprises eight bitlines B 0  through B 7 . Skilled artisans will appreciate that the notation used in  FIG. 2  is commonly employed and will further recognize that, for example, bitline B 0  of address BYTE 0  is distinct and separate from bitline B 0  of address BYTE 1 . 
   Passgate transistors in the lower page y-mux portion  212  couple the bitlines comprising address bytes BYTE 0  through BYTE 63  to a lower global bitlines group  214 , comprising lower global bitlines LGBL 0  through LGBL 7 . The B 0  bitlines comprising BYTE 0  through BYTE 63  are coupled to the lower global bitlines LGBL 0 . The B 1  bitlines comprising BYTE 0  through BYTE 63  are coupled to the lower global bitline LGBL 1 . Analogous couplings are replicated with the remaining bitlines in BYTE 0  through BYTE 63 . 
   Passgate transistors in the upper page y-mux portion  252  couple the bitlines comprising address bytes BYTE 64  through BYTE 127  to an upper global bitlines group  254 , comprising upper global bitlines UGBL 0  through UGBL 7 . 
   The B 0  bitlines comprising BYTE 64  through BYTE 127  are coupled to the upper global bitline UGBL 0 . The B 1  bitlines comprising BYTE 64  through BYTE 127  are coupled to the upper global bitline UGBL 1 . Analogous couplings are replicated with the remaining bitlines in BYTE 64  through BYTE 127 . 
   The lower global bitlines group  214  is coupled to a sense amplifier  201  by a lower bit-select mux  216 . The lower bit-select mux  216  is comprised of eight mux transistors, each transistor having one of eight lower bit-select control signals coupled to a gate terminal of the transistor. The lower global bitline LGBL 0  is coupled to the sense amplifier  201  by the transistor associated with a lower bit-select control signal LBS 0 . The lower global bitline LGBL 1  is coupled to the sense amplifier  201  by the transistor associated with a lower bit-select control signal LBS 1 . The remaining lower global bitlines LGBL 2  . . . LGBL 7  are coupled in an analogous manner. 
   The upper global bitlines group  254  is coupled to a sense amplifier  201  by an upper bit-select mux  256 . The upper bit-select mux  256  is comprised of eight mux transistors, each transistor having one of eight upper bit-select control signals coupled to a gate terminal of the transistor. The upper global bitline UGBL 0  is coupled to the sense amplifier  201  by the transistor associated with an upper bit-select control signal UBS 0 . The upper global bitline UGBL 1  is coupled to the sense amplifier  201  by the transistor associated with an upper bit-select control signal UBS 1 . The remaining upper global bitlines UGBL 2  . . . UGBL 7  are coupled in an analogous manner. 
   In operation, only one of the lower bit select mux  216  and the upper bit select mux  256  operates to select and couple a bitline to the sense amplifier  201  at a given time. By operating to allow only one multiplexer to couple a bitline signal at any given time, read operations associated with the lower memory page portion  210  do not interfere with read operations associated with the upper memory page portion  250 . 
   Skilled artisans will recognize that the lower and upper global bitlines as described supra are half as long as the global bitlines in the prior art of  FIG. 1 , and consequently exhibit only half as much electrical loading as the global bitlines of the prior art. The reduced global bitline length and loading of the present invention results in higher speed operation of the sense amplifier  201 . 
   In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the present invention as set forth in the appended claims. For example, in the exemplary embodiment, the memory page division is presented in terms of an upper and a lower memory page having a combined total of 128 bytes of addressing. However, other embodiments are possible with different page sizes. If a larger memory page size is desired, the global bitline loading can be maintained under a constant value by repeating the splitting scheme as described supra to limit the number of bytes associated with a specific bit-select mux. Furthermore, it is possible to associate even fewer than eight bits with a single bit-select mux in order to decrease loading effects further. The association of fewer than eight bytes per bit-select mux could be desirable if even greater sense amplifier speed were required. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.