Abstract:
The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with a reference memory cell that simulates the memory cell and has a reference memory transistor simulating the memory transistor. According to the invention, it is provided that firstly, in a first step, the reference memory transistor is brought to the normally on state provided that the reference memory transistor is not already in the normally on state. In a second step, it is provided that a predetermined reference current is fed into the at least one read-out path simulation. Unlike in the prior art, said reference current is not derived from a reference voltage. In a third step, provision is made for generating, with the aid of the predetermined reference current, a reference voltage that is dependent on the channel resistance of the reference memory transistor. In a fourth step, the reference voltage generated is applied to the gate of the memory transistor and the gate of the reference memory transistor. In a fifth step, the read current flowing through the memory transistor is compared with the predetermined reference current flowing through the reference memory transistor.

Description:
FIELD OF THE INVENTION  
       [0001]     The invention relates to a method for reading from a flash/EEPROM memory cell according to the preamble of patent claim  1  and to a circuit arrangement for reading  10  from a flash/EEPROM memory cell according to the pream-ble of patent claim  8 .  
       BACKGROUND  
       [0002]     EEPROMs (acronym for Electrically Erasable Programmable Read Only Memories) or EAROMs (acronym for Electrically Alterable ROM=electrically alterable read only memo-ries), so-called flash memories, are known in a variety of embodiment variants from the prior art. EEPROM/flash memories are generally divided into rows and columns, each crossover point of columns and rows constituting a memory cell.  
         [0003]     The respective columns of an EEPROM/flash memory are referred to as bit lines. These bit lines are terminated by a so-called sense amplifier. Said sense amplifier serves for evaluating the content of a respec-tively selected memory cell.  
         [0004]     By way of example, a so-called 1 kbit memory comprises a total of 1024 individual EEPROM/EAROM memory cells with 32 rows and 32 columns or bit lines. Each bit line is assigned a sense amplifier, so that the 1 kbit memory has a total of 32 sense amplifiers. Each bit line in the memory array thus comprises, in accordance with the number of rows,  32  individual EEPROM/EAROM memory cells which are connected in parallel and with which a single sense amplifier is in each case connected in series.  
         [0005]     In addition to the actual memory, which is usually formed by a memory transistor, each EEPROM/EAROM memory cell comprises a selection device, preferably a high-voltage switching transistor, by means of which the EEPROM/EAROM memory cell can be selected. In addition to the function of activating the read-out path, the selection device, in particular the high-voltage switching transistor, serves as a high-voltage protection device for the sense amplifier during erasure.  
         [0006]     A sense amplifier comprises a comparison device, which compares the current intensity of a current flowing via the selected EEPROM/EAROM memory cell with that of a reference current and outputs a logic “0” or “1”, on the basis of the result of the comparison (the current intensity via the selected EEPROM/EAROM memory cell is greater or less than the reference current intensity).  
         [0007]     There is often additionally present in each bit line a circuit device, which is usually formed as a so-called cascode transistor, which is provided for preventing “floating” of the bit line, that is to say for setting a defined potential on the bit line even when the bit line is not selected, and furthermore for increasing the read-out speed of the sense amplifier.  
         [0008]     The read-out process is explained below with reference to  FIG. 4  of the drawing.  
         [0009]      FIG. 4  shows a sense amplifier  2  connected to a bit line  1  with a single memory cell S.  
         [0010]     In accordance with the explanations above, the memory cell S comprises a memory transistor M 1  with a floating gate (not illustrated here) and a high-voltage switching transistor M 2  (in each case n-channel MOSFETs of the enhancement-mode type, MOSFET=acronym for Metal Oxide Semiconductor Field Effect Transistor), the drain-source channels D 1 , S 1 , D 2 , S 2  of which are connected in series, the drain D 1  of the memory transistor M 1  being connected to the drain D 2  of the high-voltage switching transistor M 2 .  
         [0011]     In accordance with the explanations above, the sense amplifier  2  comprises a cascode transistor M 3  (n-channel MOSFET of the enhancement-mode type), a current comparator  22  and two current mirrors  12  and  14 .  
         [0012]     Each current mirror  12 ,  14  is formed, in a manner that is customary per se, with the aid of two transistors M 4 , M 5  (p-channel MOSFETs of the enhancement-mode type) and M 6 , M 7  (n-channel MOSFETs of the enhancement-mode type), respectively, whose gates G 4 , G 5  and G 6 , G 7 , respectively, are connected to one another and in the case of whose respective input-side transistor M 4 , M 6  the gate G 4 , G 6  is connected to the drain D 4 , D 6 .  
         [0013]     The current comparator  22  is essentially formed by the two output-side transistors M 5 , M 7  of the abovementioned current mirrors  12 ,  14 , the drain D 5  of the output-side transistor M 5  of the current mirror  12  being connected to the drain D 7  of the output-side transistor M 7  of the current mirror  14 .  
         [0014]     The individual circuit blocks mentioned above are connected up to one another as follows:  
         [0015]     The source S 2  of the high-voltage switching transistor M 2  of the memory cell S is connected to the source S 3  of the cascode transistor M 3 . The drain D 3  of the cascode transistor M 3  is connected to the drain D 4  of the input-side transistor M 4  of the first current mirror  12 . The substrate terminals B 1 , B 2 , B 3 , B 6 , B 7  of all the NMOS transistors M 1 , M 2 , M 3 , M 6 , M 7  each having a drain, source, gate and substrate terminal D 1 , D 2 , D 3 , D 6 , D 7 , S 1 , S 2 , S 3 , S 6 , S 7 , G 1 , G 2 , G 3 , G 6 , G 7 , B 1 , B 2 , B 3 , B 6 , B 7  are in each case connected to a reference potential  18 . The substrate terminals B 4 , B 5  of the PMOS transistors M 4 , M 5  each having a drain, source, gate and substrate terminal D 4 , D 5 , S 4 , S 5 , G 4 , G 5 , B 4 , B 5  are at operating voltage U B .  
         [0016]     The source S 1  of the memory transistor M 1  of the memory cell S and also the source terminals S 6 , S 7  of the two transistors M 6 , M 7  of the second current mirror  14  are at the reference potential  18 . The two source terminals S 4 , S 5  of the transistors M 4 , M 5  of the first current mirror  12  are at the operating voltage U B  provided by an operating voltage source  16 . The operating voltage U B  is generally approximately 5 V. A cascode voltage U cascode, 21  provided by a cascode voltage source  21  is present at the gate G 3  of the cascode transistor M 3 . The cascode voltage U cascode,21  is dependent on the state of the memory cells. It is typically approximately 1.9 V in the control state. A fixedly predetermined drive voltage having a magnitude of typically U ref =1.25V (e.g. bandgap voltage) which is provided by a voltage source  19  is present at the gate G 1  of the memory transistor M 1 . Interposed between the reference potential  18  and the source S 2  of the high-voltage switching transistor M 2  is a current sink  34  with a current I 2 , which holds the cascode transistor M 3  at the operating point, which is intended to prevent “floating” of the bit line.  
         [0017]     The read-out of the memory cell S, and in particular of the content of the memory transistor M 1 , is effected in accordance with the description below:  
         [0018]     The memory cell S is selected as a result of the gate G 2  of the high-voltage switching transistor M 2  being driven with a selection voltage U sel  provided by a selection voltage source  20 . The high-voltage switching transistor M 2  is in the on state. As a result, a read current I read  driven by the operating voltage U B  flows through the read-out path  5  formed by the drain-source paths D 4 , S 4 , D 3 , S 3 , D 2 , S 2 , D 1 , S 1  of the transistors M 4 , M 3 , M 2 , M 1 . The read current intensity I read  is determined by the threshold voltage U th,M1  of the memory transistor M 1 , which was set by preceding erasure (normally on state of the transistor M 1  is necessary for current flow). A reference current I ref  provided by a reference current source  7  simultaneously flows in the opposite direction.  
         [0019]     The read current I read  predetermined by the memory transistor M 1  and the reference current I ref  flowing in the opposite direction are mirrored (mirror direction  17 ) with the aid of the first current mirror  12  into the comparator current path  23  formed by the source-drain path S 5 , D 5  of the output-side mirror transistor M 5  of the first current mirror  12  and the source-drain path S 7 , D 7  of the output-side mirror transistor M 7  of the second current mirror  14  and are ready there as mirrored differential current (I read -I ref ) g . At the same time, the reference current I ref  provided by the reference current source  7  is mirrored (mirror direction  15 ) with the aid of the second current mirror  14  into the comparator current path  23  formed by the source-drain path S 5 , D 5  of the output-side mirror transistor M 5  of the first current mirror  12  and the source-drain path S 7 , D 7  of the output-side mirror transistor M 7  of the second current mirror  14  and is ready there as mirrored reference current I ref,g .  
         [0020]     If I read =0, it follows that (I read −I ref ) g =I ref,g &lt;0. In this case, the output voltage U out =0 is present at the drain D 5  of the output-side mirror transistor M 5  of the first current mirror  12  and the sense amplifier  2  outputs a logic “0”. If I read &gt;I ref , it follows that (I read −I ref ) g =I ref,g &gt;0. In this case, the operating voltage U B  is dropped across the mirror transistor M 7  and the comparator output A out  is at operating or supply voltage U out =U B  and the sense amplifier  2  outputs a logic “1”.  
         [0021]     A reference circuit arrangement  3 * for generating the reference current I ref  that is usually used according to the prior art is illustrated in  FIG. 5 .  
         [0022]     The reference circuit arrangement  3 * for generating the reference current I ref  essentially comprises a simulation of the read-out path  5  of the circuit arrangement according to  FIG. 4  that is formed by the drain-source paths D 4 , S 4 , D 3 , S 3 , D 2 , S 2 , D 1 , S 1  of the transistors M 4 , M 3 , M 2 , M 1 .  
         [0023]     In concrete terms, the reference circuit arrangement  3 * according to the prior art comprises a reference memory transistor M 1 ,ref and a reference high-voltage switching transistor M 2 ,ref, which together form a reference memory cell S ref , a reference cascode transistor M 3 ,ref and a current mirror  10  corresponding to the type described above with two p-channel MOS field effect transistors M 4 ,ref, M 5 ,ref of the enhancement-mode type.  
         [0024]     The gates G 4 ,ref and G 5 ,ref of the two field effect transistors M 4 ,ref, M 5 ,ref of the current mirror  10  are connected to one another. The gate G 4 ,ref of the input-side transistor M 4 ,ref is connected to the drain D 4 ,ref thereof.  
         [0025]     The source S 2 ,ref of the reference high-voltage switching transistor M 2 ,ref of the reference memory cell Sref is connected to the source S 3 ,ref of the reference cascode transistor M 3 ,ref. The drain D 3 ,ref of the reference cascode transistor M 3 ,ref is connected to the drain D 4 ,ref of the input-side transistor M 4 ,ref of the current mirror  10 . The substrate terminals B 1 ,ref, B 2 ,ref, B 3 ,ref of all the NMOS transistors M 1 ,ref, M 2 ,ref, M 3 ,ref each having a drain, source, gate and substrate terminal D 1 ,ref . . . D 3 ,ref, S 1 ,ref . . . S 3 ,ref, G 1 ,ref . . . G 3 ,ref, B 1 ,ref . . . B 3 ,ref are connected to the reference potential  18 . The substrate terminals B 4 ,ref, B 5 ,ref of all the PMOS transistors each having a drain, source, gate and substrate terminal D 4 ,ref, D 5 ,ref, S 4 ,ref, S 5 ,ref, G 4 ,ref, G 5 ,ref B 4 ,ref, B 5 ,ref are connected to the operating voltage potential U B,ref .  
         [0026]     The source S 1 ,ref of the reference memory transistor M 1 ,ref of the reference memory cell S ref  is at the reference potential  18 . The two source terminals S 4 ,ref, S 5 ,ref of the transistors M 4 ,ref, M 5 ,ref of the reference current mirror  10 , in the same way as the gate G 2 ,ref of the reference high-voltage switching transistor M 2 ,ref, are at an operating voltage U B,ref  provided by a reference operating voltage source  11 , said operating voltage being identical to that from the operating voltage source U B  of the sense amplifier  2 . The operating voltage U B =U B,ref  is generally approximately 5 V. A cascode voltage U cascode,9  provided by a reference cascode voltage source  9  is present at the gate G 3 ,ref of the reference cascode transistor M 3 . Said cascode voltage U cascode,9  is typically U cascode,9 =1.9 V in the control state, as above. A fixedly predetermined reference drive voltage U ref  provided by a voltage source  8  can be applied to the gate G 1 ,ref of the reference memory transistor M 1 ,ref, said reference drive voltage being chosen to be identical to the drive voltage U ref  in the circuit arrangement  2  according to  FIG. 4 .  
         [0027]     The reference current I ref  is generated by a current I ref,0  flowing via the reference memory transistor M 1 ,ref on account of the voltage drop across the read-out path simulation  5 ref formed by the source-drain paths S 1 ,ref, D 1 ,ref, S 2 ,ref, D 2 ,ref, S 3 ,ref, D 3 ,ref, S 4 ,ref, D 4 ,ref of the reference transistors M 1 ,ref, M 2 ,ref, M 3 ,ref, M 4 ,ref. Said current I ref,0  is mirrored (mirror direction  13 ) with the aid of the reference current mirror  10  from the input-side transistor M 4 ,ref to the output-side mirror transistor M 5 ,ref. The current flowing through the mirror transistor M 5 ,ref forms the reference current I ref , which can be tapped off at the drain D 5 ,ref of the mirror transistor M 5 ,ref. This terminal representing the actual reference current source is identified by the reference symbol  7  in  FIG. 5 .  
         [0028]     In order to set the reference current I ref  to a desired value, the so-called target current intensity I target , the reference memory transistor M 1 ,ref is brought to the normally on state by erasure.  
         [0029]     The threshold voltage U th,M1,ref  of the reference memory transistor M 1 ,ref, which can be altered by means of the erasure, is responsible for the current-carrying capacity of the reference EEPROM/EAROM cell:  
         [0030]     erasure with a high erase voltage means a strongly negative threshold voltage U th,M1,ref . The channel of the reference memory transistor M 1 ,ref is strongly normally on.  
         [0031]     erasure with a low erase voltage means a weakly negative threshold voltage U th,M1,ref . The channel of the reference memory transistor M 1 ,ref is weakly normally on.  
         [0032]     This influence of the erase voltage on the current-carrying capacity of the reference memory cell S ref  or the reference memory cells (typically a total of eight reference memory cells of the type illustrated in  FIG. 5  are used for generating the reference current for the entire memory, said reference memory cells being connected in parallel) is utilized in the customary principle of reference current generation. In this case, the reference memory cell(s), which are generally all situated on the same semiconductor chip, is/are trimmed to the target current I target  during testing by the cycle erasure—current measurement, said target current being fed into the sense amplifier  2  as reference current I ref .  
         [0033]     The erasure of the reference memory cell(s) S ref  is effected by the gate G 1 ,ref of the reference memory transistor M 1 ,ref being put at reference potential  18  and the source S 1 ,ref of the reference memory transistor M 1 ,ref momentarily having a high voltage of the erase voltage, applied to it. Said voltage is generally approximately 20 V.  
         [0034]     For the subsequent current measurement, a defined reference voltage U ref  (e.g. the bandgap voltage of approximately 1.25 eV) is applied to the gate G 1 ,ref of the EEPROM cell M 1 ,ref (illustrated in  FIG. 5 ).  
         [0035]     If the desired target current intensity I target  is not reached after the first cycle, that is to say if the measured current intensity I meas  is less than the target current intensity I target , erasure is effected once again, but this time with a high erase voltage. The consequence of this is that the magnitude of the threshold voltage U th,M1,ref  decreases and the cell current I ref,0  rises. This adjustment may last for a few cycles until the target current I target  is reached. The reference cell S ref  then remains untouched over the lifetime.  
         [0036]     Although the method described above and also the circuit arrangement illustrated in  FIG. 5  have basically proved to be worthwhile, various weak points still exist.  
         [0037]     In particular, the reference current is a current trimmed to an absolute value and is therefore greatly dependent on the state of the reference cells. As a result of the complicated current adjustment during testing, the process dependence, that is to say the variation of the component properties on account of certain production tolerances, can be eliminated for the most part.  
         [0038]     During the lifetime of the EEPROM, the so-called “floating gate” of the memory transistor loses charge, which leads to a threshold voltage increase and thus to a lower current-carrying capacity of the memory cell.  
         [0039]     This process is known as “data retention”. In order to be able to maintain the required read-out speed over the lifetime of the EEPROM, it is necessary to allow for a certain bias in the dimensioning of the threshold voltage. This has the effect that the overall current consumption rises. This results from the relationship whereby the magnitude of the threshold voltage during erasure is proportional to the read-out current and thus proportional to the read-out time.  
         [0040]     Moreover, temperature changes and operating voltage fluctuations cause in some instances considerable fluctuations of the reference current.  
         [0041]     In order to set the reference current correctly despite all the influences, complicated technological examinations are necessary over the “operating window” of the EEPROM cells.  
       SUMMARY  
       [0042]     The object of the invention consists, then, in providing a method and a circuit arrangement for reading from an EEPROM memory cell in the case of which the abovementioned problems are largely eliminated.  
         [0043]     The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out path simulation with a reference memory cell that simulates the memory cell and has a reference memory transistor simulating the memory transistor.  
         [0044]     According to the invention, it is provided that firstly the reference memory transistor is brought to the normally on state provided that the reference memory transistor is not already in the normally on state. It is further provided that a predetermined reference current is fed into the at least one read-out path simulation. Unlike in the prior art, said reference current is not derived from a reference voltage. In this case, provision is made for generating, with the aid of the predetermined reference current, a reference voltage that is dependent on the channel resistance of the reference memory transistor, in particular in triode operation a reference voltage that is (essentially) proportional to the channel resistance and/or in saturation operation a reference voltage that (essentially) rises with the channel resistance according to a root function. In this case, the reference voltage generated is applied to the gate of the memory transistor and the gate of the reference memory transistor. Finally, the read current flowing through the memory transistor is compared with the predetermined reference current flowing through the reference memory transistor.  
         [0045]     In terms of the apparatus, the invention is characterized by the fact that, if appropriate, means are provided in order to bring the reference memory transistor to the normally on state (that is to say low threshold voltage) provided that the reference memory transistor is not already in the normally on state (that is to say threshold voltage low). A current source is provided in order to feed a predetermined reference current into the at least one read-out path simulation. A circuit device is furthermore provided in order to generate, with the aid of the predetermined reference current, a reference voltage that is dependent (e.g. proportional or rising according to a root function) on the channel resistance of the reference memory transistor and in order to apply the reference voltage generated to the gate of the memory transistor and the gate of the reference memory transistor, the comparison device, in accordance with the invention, being provided for comparing the read current flowing through the memory transistor, with the predetermined reference current flowing through the memory reference transistor.  
         [0046]     In a simple manner, the reference memory transistor can be brought to the normally on state by the gate of the reference memory transistor being connected to a reference potential and an erase voltage of e.g. 20 V being applied momentarily, in particular multiply, to the source of the reference memory transistor. The circuit arrangement according to the invention, correspondingly comprises means which are designed to bring the reference memory transistor to the normally on state by connecting the gate of the reference memory transistor to a reference potential and applying an erase voltage momentarily, in particular multiply, preferably three times, to the source.  
         [0047]     For reasons of reliability and secure operation, it has proved to be advantageous if the predetermined reference current is fed into a plurality of read-out path simulations. The provision of eight read-out path simulations constitutes a compromise between high operational reliability and comparatively low redundancy and current consumption.  
         [0048]     For reasons of accuracy, it has proved to be expedient if the predetermined reference current is mirrored before being fed into the at least one read-out path simulation. The apparatus according to the invention has, for this purpose, a current mirror in order to mirror the predetermined reference current before being fed into the at least one read-out path simulation.  
         [0049]     The reference voltage that is dependent on the channel resistance of the reference memory transistor can be generated most simply with the aid of a voltage follower circuit, e.g. a source follower transistor or with the aid of an emitter follower transistor. The concrete circuitry realization can be gathered from the description of the figures below.  
         [0050]     Furthermore, it has proved to be advantageous for reasons of accuracy if the read current flowing through the memory transistor and the predetermined reference current flowing through the reference memory transistor are mirrored before they are compared. The apparatus according to the invention comprises, for this purpose, a current mirror in order to mirror the read current flowing through the memory transistor and a current mirror in order to mirror the predetermined reference current flowing through the reference memory transistor. The comparison device is provided for comparing the mirrored read current and the mirrored predetermined reference current.  
         [0051]     In the case of the method according to the invention and the apparatus according to the invention, it is necessary in the majority of cases, with the aid of a cascode transistor, the gate of which is driven by means of a cascode voltage, to set a defined potential at an input node of the memory cell, preferably at the source of the high-voltage switching transistor. The same also applies to the simulated read-out path, where, with the aid of a respective corresponding reference cascode transistor simulating the cascode transistor, the gate of which reference cascode transistor is driven by means of the cascode voltage, a defined potential is set at an input node of a respective reference memory cell.  
         [0052]     In a particularly advantageous embodiment variant of the invention, it is provided that the cascode voltage is generated by a predetermined current being fed into a further read-out path simulation with a further simulated memory cell. The further simulated memory cell has a further input node, to which a further simulated cascode transistor and a control transistor are connected. The control transistor simulates a memory transistor. The voltage at the input node of a respective reference memory cell is compared with the voltage at the further input node of the further simulated memory cell, and, through corresponding driving of the gate of the control transistor, the channel conductivity of the control transistor is altered until the voltage at the input node of a respective reference memory cell matches the voltage at the further input node. The voltage at the drain of the further simulated cascode transistor is used as the cascode voltage.  
         [0053]     A cascode voltage generating device according to the invention for generating a cascode voltage accordingly comprises a current source in order to feed a predetermined current into a further read-out path simulation. Furthermore, a comparison and control device is provided in order to compare the voltage at the input node of a respective reference memory cell with the voltage at the further input node of the further simulated memory cell. The comparison and control device is further designed, through corresponding driving of the gate of the control transistor, to alter the channel conductivity of the control transistor until the voltage at the input node of a respective reference memory cell matches the voltage at the further input node. An output device is present in order to output the voltage at the drain of the further simulated cascode transistor as the cascode voltage. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0054]     The invention will now be described in more detail with reference to the drawing, in which:  
         [0055]      FIG. 1  shows a circuit arrangement comprising a bit line with four EEPROM memory cells, a sense amplifier for reading out the content of the EEPROM memory cellsα and a first exemplary embodiment of a reference circuit arrangement according to the invention with eight reference subcircuit arrangements for reading from the EEPROM memory cells, 
        a) left-hand part     b) right-hand part          
         [0058]      FIG. 2  shows a second exemplary embodiment of a reference circuit arrangement according to the invention for reading from EEPROM memory  10  cells,  
         [0059]      FIG. 3  shows an exemplary embodiment of a circuit arrangement according to the invention for generating a cascode voltage for a cascode transistor in a sense amplifier for reading out the content of EEPROM memory cells and for a cascode transistor in a reference voltage generating device,  
         [0060]      FIG. 4  shows a simple sense amplifier in accordance with the prior art for reading out the content of EEPROM memory cells,  
         [0061]      FIG. 5  shows a reference circuit arrangement for generating a reference current for reading from EEPROM memory cells in accordance with the prior art. 
     
    
     DETAILED DESCRIPTION  
       [0062]     Identical, functionally identical or functionally similar components are provided with identical reference symbols in all the abovementioned figures.  
         [0063]     The invention will firstly be explained with reference to  FIG. 2 , which shows an exemplary embodiment of a reference circuit arrangement  3  according to the invention for generating a reference voltage U 1  for reading from EEPROM memory cells S.  
         [0064]     The starting point is once again a sense amplifier  2  in accordance with the prior art with an EEPROM memory cell S, such as is illustrated in  FIG. 4  and described in detail above.  
         [0065]     As in the reference circuit arrangement  3 * in accordance with the prior art, the reference circuit arrangement  3  according to the invention for generating a reference voltage U 1  comprises a simulation  5 ref of the read-out path  5  of the circuit arrangement  2  according to  FIG. 4  that is formed by the drain-source paths D 4 , S 4 , D 3 , S 3 , D 2 , S 2 , D 1 , S 1  of the transistors M 4 , M 3 , M 2 , M 1 .  
         [0066]     In concrete terms, the reference circuit arrangement  3  comprises a reference memory transistor M 1 ,ref (n-channel MOSFET of the enhancement-mode type) and a reference high-voltage switching transistor M 2 ,ref (n-channel MOSFET of the enhancement-mode type), which together form a reference memory cell S ref , a reference cascode transistor M 3 ,ref (n-channel MOSFET of the enhancement-mode type), a current mirror circuit  24  and also an additional transistor M 8 ,ref. An operating voltage source  11 , a cascode voltage source  9 , a first current source  26  and a third current source  27  are furthermore provided.  
         [0067]     In this case, too, the current mirror circuit  24  comprises two p-channel MOS field effect transistors M 4 ,ref., M 5 ,ref of the enhancement-mode type, the gates G 4 ,ref and G 5 ,ref of which are connected to one another.  
         [0068]     In a departure from the embodiment in accordance with the prior art, in the variant according to the invention, the gate G 4 ,ref of the transistor M 4 ,ref is not connected to the drain D 4 ,ref thereof, rather the gate G 5 ,ref of the transistor M 5 ,ref, which does not lie in the read-out path simulation  5 ref is connected to the drain D 5 ,ref of said transistor M 5 ,ref. Unlike in the circuit arrangement illustrated in  FIG. 5 , therefore, in the present exemplary embodiment, a current mirroring is possible only from the transistor M 5 ,ref to the transistor M 4 ,ref, but not in the opposite direction. This current mirror direction is identified with the aid of an arrow provided with the reference symbol  25 .  
         [0069]     The drain D 1 ,ref of the reference memory transistor M 1 ,ref is connected via the node a to the drain D 2 ,ref of the reference high-voltage switching transistor M 2 ,ref. The source S 2 ,ref of the reference high-voltage switching transistor M 2 ,ref of the reference memory cell Sref is connected via the node b to the source S 3 ,ref of the reference cascode transistor M 3 ,ref. The drain D 3 ,ref of the reference cascode transistor M 3 ,ref is connected via the node c to the drain D 4 ,ref of the output-side transistor M 4 ,ref of the current mirror  24 .  
         [0070]     The substrate terminals B 1 ,ref, B 2 ,ref and B 3 ,ref of the n-channel transistors M 1 ,ref, M 2 ,ref, M 3 ,ref each having a drain, source, gate and substrate terminal D 1 ,ref . . . D 3 ,ref, S 1 ,ref . . . S 3 ,ref, G 1 ,ref . . . G 3 ,ref, B 1 ,ref . . . B 3 ,ref are connected to reference potential  18 . The substrate terminals B 4 ,ref, B 5 ,ref of all the p-channel transistors M 4 ,ref, M 5 ,ref each having a drain, source, gate and substrate terminal D 4 ,ref, D 5 ,ref, S 4 ,ref, S 5 ,ref, G 4 ,ref, G 5 ,ref, B 4 ,ref, B 5 ,ref are connected to operating voltage U B,ref .  
         [0071]     The source S 1 ,ref of the reference memory transistor M 1 ,ref of the reference memory cell S ref  is at the reference potential  18 . The two source terminals S 4 ,ref, S 5 ,ref of the transistors M 4 ,ref, M 5 ,ref of the reference current mirror  24 , in the same way as the gate G 2 ,ref of the reference high-voltage switching transistor M 2 ,ref, are at the operating voltage U B,ref  provided by a reference operating voltage source  11 , said operating voltage being identical to the operating voltage U B  provided by the operating voltage source  16  of the sense amplifier  2 . The operating voltage U B =U B,ref  is generally approximately 5 V. A cascode voltage U cascode,9  provided by a reference cascode voltage source  9  is present at the gate G 3 ,ref of the reference cascode transistor M 3 ,ref. Said cascode voltage U cascode,9  is typically approximately U cascode,9 =1.2 V in the control state and dependent on the state of the memory cells.  
         [0072]     The source S 8 ,ref of the additional n-channel MOSFET M 8 ,ref of the enhancement-mode type is connected to the gate G 1 ,ref of the reference memory transistor M 1 ,ref. The substrate terminal B 8 ,ref of the reference memory transistor M 1 ,ref is connected to the source terminal S 8 ,ref of the reference memory transistor M 1 ,ref. The drain D 8 ,ref of the transistor M 8 ,ref is at operating voltage potential U B,ref . The gate G 8 ,ref is connected to the node C and is thus connected to the drains D 4 ,ref and D 3 ,ref of the two transistors M 4 ,ref and M 3 ,ref.  
         [0073]     In the present exemplary embodiment, the current mirror circuit  24  that is known in circuit technology represents the basic circuit component for the invention&#39;s principle of reference current generation.  
         [0074]     A fixedly predetermined first current I 1  (for example from an on-chip current source  26 ) is impressed on the reference circuit arrangement  3  illustrated in  FIG. 2  via the input transistor M 5 ,ref of the current mirror circuit  24 . In the current mirror circuit  24 , said first current I 1  is mapped via the output-side mirror transistor M 4 ,ref onto the read-out path simulation  5 ref, where it flows as mirrored first current I 1g  in the read-out path simulation  5 ref.  
         [0075]     On account of said mirrored first current I 1g , a voltage U c  is established at the node c depending on the strength of the normally on capability (e.g. threshold voltage (U th,M1,ref ) that can be altered by erasure according to the method specified above) of the reference memory transistor M 1 ,ref, which voltage U c  sets a reference voltage U 1  that is dependent on the reference memory transistor M 1 ,ref with the aid of the source follower M 8 ,ref. In this case, the third current source  27  with the current intensity I 3  serves for holding the source follower M 8 ,ref at the operating point.  
         [0076]     Said reference voltage U 1  is applied as read-out voltage U 1  to the memory transistor M 1  e.g. in accordance with the circuit according to  FIG. 4 .  
         [0077]     Assuming that the memory transistor M 1  is in the same state (identical threshold voltage U th,M1 ) as the reference memory transistor M 1 ,ref, the read-out current I read  generated by the memory transistor M 1  corresponds, according to the current mirror principle, to the reference current I 1  from the on-chip current source  26  that is fixedly set in the reference circuit arrangement  3 . It suffices, therefore, if the current I 1  generated by the on-chip source  26  is fed as reference current in the sense amplifier  2  in accordance to  FIG. 2 . In order to ensure the functionality described below, however, the current intensity I 1 , depending on the required read-out speed, is approximately 10 to 20% greater than the reference current I ref  which is required for the read-out method according to the prior art and which is provided by the circuit arrangement according to  FIG. 5 .  
         [0078]     In order to set a certain reference voltage U 1 , the reference memory transistor M 1 ,ref is brought to a desired normally on state by erasure in a manner similar to that in the case of the method described above or the circuit arrangement described above for generating a reference current from a reference voltage in accordance with the prior art.  
         [0079]     The reference voltage setting is effected in the manner described below:  
         [0080]     The reference cascode transistor M 3 ,ref ensures the operation of the reference memory transistor M 1 ,ref in triode operation.  
         [0081]     The erasure of the reference memory cell(s) S ref  is effected by the gate G 1 ,ref of the reference memory transistor M 1 ,ref being put at reference potential  18  and an erase voltage (approximately 20 V) being momentarily applied to the source S 1 ,ref of the reference memory transistor M 1 ,ref. This process is repeated if appropriate multiply until it is ensured that the reference memory transistor is in the normally on state. Typically, only three cycles are sufficient to reach this state.  
         [0082]     The resistance of the drain-source path of the transistor M 1 ,ref is altered by erasure with different erase voltages. Consequently, the transistor chain M 1 ,ref M 3 ,ref can be regarded as current source with a variable current which sets the potential at node C (drain M 3 ,ref, drain M 4 ,ref). With the source follower M 8 ,ref, a voltage U 1  corresponding to the resistance of the drain-source path of the transistor M 1 ,ref is adjusted at the gate of the EEPROM transistor M 1 ,ref in order that the currents through the transistors M 3 ,ref, M 4 ,ref become identical in magnitude. This means that the resistance of M 1 ,ref will be established such that the current source M 3 ,ref-M 1 ,ref can “extract” the supplied current I 1g  from M 4 ,ref, which has the consequence that the node C is in current equilibrium and a constant potential is established at this node C. Through M 8 ,ref, moreover, the output impedance r M8,ref =1/gm M8,ref  formed by the reciprocal of the transconductance of the transistor M 8 ,ref in a common-drain connection is kept low at the source S 8 ,ref, which is an important criterion for a voltage reference.  
         [0083]     Through application of this reference voltage generation, it is possible to eliminate the problems described above:  
         [0084]     There is no need for so-called trimming during testing. The reference cells are subjected to some on-chip programming/erasure cycles prior to start-up in order to guarantee a defined identical state of all the cells. No current has to be adjusted (measured) during the erasure/programming sequence. The test time is thereby reduced, which reduces the production costs.  
         [0085]     Furthermore, there is no need for any complicated examinations over the “operating window” of the EEPROM cells in order to guarantee a bias for temperature or operating voltage fluctuations or the like. This means that less bias is necessary for the reference current.  
         [0086]     This leads to a reduction of the overall current consumption. The temperature and the operating voltage have no influence on the reference current. The read-out current remains constant. The overall current consumption likewise remains constant.  
         [0087]     In the case of this circuit arrangement  3  according to the invention as shown in  FIG. 2  it is particularly important to provide a voltage source for generating a suitable cascode voltage U cascode . In order to ensure entirely satisfactory functioning of the reference voltage generation, it is necessary, moreover, to generate a cascode voltage U cascode  which is able to compensate for process dependencies, temperature fluctuations and the possible occurrence of loss of charge (moving bit) of the reference memory cells S ref . The cascode voltage that is predetermined with the control ensures the operation of the EEPROM transistor in the triode region.  
         [0088]      FIG. 3  shows, besides the circuit  3  for reference voltage generation from  FIG. 2 , in addition a control circuit  28  for generating a cascode voltage U cascode .  
         [0089]      FIG. 3  depicts the essential constituent parts of the reference circuit arrangement  3 , namely the transistors M 1 ,ref, M 2 ,ref, M 3 ,ref and M 8 ,ref connected via the nodes a and b. The current mirror circuit  24  in accordance with  FIG. 2 , via which the current I 1  is mirrored into the simulated read-out path  5 ref, is symbolized by an equivalent current source  29  that supplies the mirrored current I 1g . The operating voltage source  11  that provides the operating voltage U B,ref  is furthermore depicted on the left-hand side of the figure of the drawing.  
         [0090]     The cascode voltage generating device  28  according to the invention comprises a differential amplifier  30 , a current source  31  and also three n-channel MOSFETs of the enhancement-mode type M 1 ,casc, M 2 ,casc and M 3 ,casc. The source-drain paths S 1 ,casc, D 1 ,casc, S 2 ,casc, D 2 ,casc, S 3 ,casc, D 3 ,casc and the fourth current source  31  that supplies a fourth constant current I 3  are cascade-connected at nodes d, e, f. The cascade-connected source-drain paths S 1 ,casc, D 1 ,casc, S 2 ,casc, D 2 ,casc, S 3 ,casc, D 3 ,casc of the transistors M 1 ,casc, M 2 ,casc, M 3 ,casc and the fourth current source  31  arranged in series constitute a simulation of the reference path  5 ref illustrated in  FIG. 2  or  3  (that is to say ultimately a simulation of the read-out path  5 ). In contrast to the simulated memory transistor M 1 ,ref, the control transistor M 1 ,casc is a normal NMOS transistor and not an EEPROM transistor (memory transistor) in order to be able to dispense with further redundancy paths. Therefore, in contrast to the reference memory transistor M 1 ,ref, the control transistor M 1 ,casc does not have a “floating gate”.  
         [0091]     The gate G 3 ,ref of the reference cascode transistor M 3 ,ref is connected to the drain of the simulated reference cascode transistor M 3 ,casc.  
         [0092]     Furthermore, the node d is connected to the noninverting input of the differential amplifier  30 . The node b is connected to the inverting input of the differential amplifier  30 . The output of the differential amplifier  30  is connected to the gate of the control transistor M 1 ,casc.  
         [0093]     The cascode voltage U cascode  is generated by means of the current source  31  that provides the fourth current I 4 , the MOS diode M 3 ,casc and the transistor M 1 ,casc that is controlled in the triode region. In this case, the differential amplifier  30  drives the gate of M 1 ,casc and in this way controls the channel resistance thereof in such a way that nodes b and d are at the same potential.  
         [0094]      FIG. 1  shows a further exemplary embodiment of a reference circuit arrangement  33  according to the invention for generating a reference voltage for reading from EEPROM memory cells.  
         [0095]     In addition to the reference circuit arrangement  3 ,  FIG. 1  shows a four-bit memory column 4 having four memory cells Sa, Sb, Sc, Sd, and an associated sense amplifier  2  of the type described above.  
         [0096]     Like the memory cell S described above, the four memory cells Sa, Sb, Sc, Sd in each case comprise an EEPROM memory transistor M 1   a , M 1   b , M 1   c , M 1   d  and also an associated high-voltage switching transistor M 2   a , M 2   b , M 2   c , M 2   d , the source-drain paths of which are connected in series in each case in a manner forming a read-out path  5   a ,  5   b ,  5   c ,  5   d.    
         [0097]     The four memory cells Sa, Sb, Sc, Sd are connected in parallel and the read-out paths  5   a ,  5   b ,  5   c ,  5   d  are connected to one another at the respective drain terminal of the high-voltage switching transistors M 2   a , M 2   b , M 2   c , M 2   d  via a bit line  1 . The respective source terminals of the memory transistors M 1   a , M 1   b , M 1   c , M 1   d  are connected to a reference potential  18 .  
         [0098]     The respective gate terminals of the high-voltage switching transistors M 1   a , M 1   b , M 1   c , M 1   d  are connected to a bus line  32  via which a respective one of the memory cells Sa, Sb, Sc, Sd can be driven with the aid of a corresponding control voltage U sel .  
         [0099]     The bit line  1  is connected to the source of a cascode transistor M 3 . The drain of the cascode transistor M 3  is connected to the drain of an input-side mirror transistor M 4  with gate fed back to the drain. The source thereof is connected to a reference voltage source  16  that provides a reference voltage U B . The channel of the mirror transistor M 4 , the channel of the cascode transistor M 3  that is connected thereto, and the channels of the high-voltage switching transistor M 2   a , M 2   b , M 2   c  or M 2   d  and of the memory transistor M 1   a , M 1   b , M 1   c  or M 1   d  of the corresponding selected memory cell Sa, Sb, Sc or Sd form a read-out path  5  and  5   a ,  5   b ,  5   c  or  5   d.    
         [0100]     The mirror transistor M and a transistor M 5 , which is likewise connected to the operating potential  16  by its source, form a current mirror circuit  12  by means of their gate coupling.  
         [0101]     Two further transistors M 6  and M 7 , the source terminals of which are connected to reference potential  18  and the gate terminals of which are connected to one another, form a further current mirror circuit  14 .  
         [0102]     The drain terminals of the two transistors M 5  and M 7  are connected to one another at a node g. These form a current comparator  22  that has already been described above with regard to  FIG. 4 .  
         [0103]     A reference current source  33  is furthermore provided, by means of which a reference current I ref  is fed into the drain of the transistor M 6 .  
         [0104]     In the present example, the reference circuit arrangement  3  comprises eight (symbolized by the designation “8x”) read-out path simulations  5   a ,ref,  5   b ,ref, . . .  5   h ,ref of the type illustrated in  FIG. 2  with simulated reference memory transistors M 1   a ,ref, M 1   b ,ref, M 1   h ,ref, reference high-voltage switching transistors M 2   a ,ref, M 2   b ,ref . . . M 2   h ,ref and reference cascode transistors M 3   a ,ref, M 3   b ,ref . . . M 3   h ,ref which are simulated in a manner corresponding to a memory transistor M 1   a , M 1   b , M 1   c , M 1   d , a read-out transistor M 2   a , M 2   b , M 2   c , M 2   d  and the cascode transistor M 3  and are arranged in corresponding reference paths  6   a ,  6   b ,  6   c  . . .  6   h.    
         [0105]     In the present exemplary embodiment, the transistor chain M 1 ,ref-M 2 ,ref-M 3 ,ref is positioned eight times in order, upon the possible occurrence of a loss of charge (moving bit) at the floating gate of a reference memory cell Sa,ref, Sb,ref . . . Sh,ref, still to have seven redundant reference memory cells Sa,ref, Sb,ref . . . Sh,ref which generate the reference voltage U 1 , as is described below:  
         [0106]     In the case of a moving bit, the threshold voltage U th,M1a,ref , U th,M1b,ref  . . . U th,M1h,ref  of the corresponding reference memory transistor M 1   a ,ref, M 1   b ,ref . . . M 1   h ,ref is increased by the loss of charge of the floating gate, which leads to a lower current-carrying capacity of the reference memory transistor M 1   a ,ref, M 1   b ,ref, . . . M 1   h ,ref. To put it another way, the channel resistance of the corresponding reference memory transistor M 1   a ,ref, M 1   b ,ref, . . . M 1   h ,ref increases in comparison with the intact reference memory transistors M 1   a ,ref, M 1   b ,ref, . . . M 1   h ,ref.  
         [0107]     In this case, the current I 1ga , I 1gb , I 1gc , I 1gd , I 1ge , I 1gf , I 1gg , I 1gh  fed in for eight reference cells is divided between seven cells, which results in a current increase per reference memory cell Sa,ref, Sb,ref . . . Sh,ref of 12.5% (⅛). As a result of the cascode control, the cascode voltage is increased by 12.5%, so that the circuit is once again at its original operating point (cf. all reference cells intact).  
         [0108]     Ideally, the reference voltage does not change in the case of a moving bit! 
         [0109]     The functioning of the cascode control emerges in detail as follows:  
         [0110]     As also emerges in particular from the above description with regard to  FIG. 3 , the reference path  6  formed by the transistors M 1 ,ref-M 3 ,ref is once again simulated with the aid of the transistors M 1 ,casc-M 3 ,casc in a manner forming a cascode generating path  6 casc. The cascode voltage Ucascode is generated by means of the current source  31  providing the fourth current I 4 , the MOS diode M 3 ,casc and the transistor M 1 ,casc controlled in the triode region. In this case, the differential amplifier  30  drives the gate of the control transistor M 1 ,casc and, in this way, controls the channel resistance thereof in such a way that nodes b and d are at the same potential.  
         [0111]     If a reference cell were then to fail and the current were increased by 12.5% on the remaining cells, then as a consequence the potential at the node b would also rise by this 12.5% (constant resistance of M 1 ,casc through reference voltage control). As a result of this voltage difference at nodes b and d, the differential amplifier  30  decreases the gate voltage at the transistor M 1 ,casc and thus increases the channel resistance thereof, which in turn permits the potential at the node b to rise until the differential voltage between b and d is equal to zero again. In the settled state, node d (with the cascode voltage U cascode ) has increased precisely by the change at node b—brought about by the current change—by 12.5%. Since the control transistor M 1 ,ref operates in the triode region, ideally linear changes take place. 
     1  Bit line      2  Sense amplifier      3  Reference circuit arrangement      3 * Reference circuit arrangement in accordance with the prior art      4  Four-bit memory column      5  Read-out path      5   a - 5   d  Read-out path      5   a   ref - 5   h   ref  Read-out path simulation      5   casc  Read-out path simulation for cascode voltage generation      5   ref  Read-out path simulation      6  Reference path      6   a - 6   h  First to eighth reference path      6   casc  Reference path simulation      7  Reference current source      8  Reference voltage source      9  Cascode voltage source      10  Current mirror circuit      11  Operating voltage source      12  Current mirror circuit      13  Current mirror direction      14  Current mirror circuit      15  Current mirror direction      16  Operating voltage source      17  Current mirror direction      18  Reference potential      19  Voltage source      20  Selection voltage source      21  Cascode voltage source      22  Current comparator      23  Comparator current path      24  Current mirror circuit      25  Current mirror direction      26  First current source      27  Second current source      28  Cascode voltage generating device      29  Equivalent current source      30  Differential amplifier      31  Fourth current source      32  Bus line      33  Third current source      34  Current sink     (A)-(E) Connection points of  FIG. 1   a  to  FIG. 1   b       a-g Node     A cascode  Output of the cascode voltage generating device     A out  Current comparator output     B 1  . . . B 7  Bulk/substrate     B 1 ,casc-B 3 ,casc Bulk/substrate     B 1 ,ref-B 5 ,ref Bulk/substrate     B 8 ,ref Bulk/substrate     D 1 -D 7  Drain     D 1 ,casc-D 3 ,casc Drain     D 1 ,ref-D 5 ,ref Drain     D 8 ,ref Drain     G 1 -G 7  Gate     G 1 ,casc-G 3 ,casc Gate     G 1 ,ref-G 5 ,ref Gate     G 8 ,ref Gate     I 1  Reference current     I 1g  Mirrored reference current     I 1ga  . . . I 1gh  Mirrored reference current     I 2 -I 4  Currents     I read  Read current     I read,0g  Read current mirrored     I ref  Reference current     I ref,0  Reference current     I ref,0g  Reference current mirrored     I target  Target current intensity     K Input node     Ka-Kd Input node     M 1  Memory transistor     M 1 ,casc Memory transistor simulation for cascode voltage generation=control transistor     M 1 ,ref Reference memory transistor     M 1   a -M 1   d  Memory transistor     M 1   a ,ref-M 1   h ,ref Reference memory transistor     M 2  High-voltage switching transistor     M 2 ,casc High-voltage switching transistor simulation for cascode voltage generation     M 2 ,ref Reference high-voltage switching transistor     M 2   a -M 2   d  High-voltage switching transistor     M 2   a ,ref Reference high-voltage switching transistor     M 2   b ,ref-M 2   h ,ref Reference high-voltage switching transistor     M 3  Cascode transistor     M 3 ,casc Cascode transistor simulation for cascode voltage generation     M 3 ,ref Reference cascode transistor     M 3   a ,ref-M 3   h ,ref Reference cascode transistor     M 4  Mirror transistor     M 4 ,ref Reference mirror transistor     M 5  Mirror transistor     M 5 ,ref Mirror transistor     M 6  Mirror transistor     M 7  Mirror transistor     M 8 ,ref Source follower transistor     S Memory cell     S 1 -S 7  Source     S 1 ,casc-S 3 ,ref Source     S 1 ,ref-S 5 ,ref Source     S 8 ,ref source     Sa first memory cell     Sa,ref first reference memory cell     Sb second memory cell     Sb,ref second reference memory cell     Sc third memory cell     Sc,ref third reference memory cell     Sd fourth memory cell     Sd,ref fourth reference memory cell     Se,ref fifth reference memory cell     Sf,ref sixth reference memory cell     Sg,ref seventh reference memory cell     Sh,ref eighth reference memory cell     U 1  reference voltage     U B  operating voltage     U B,ref  operating voltage of reference circuit arrangement     U cascode  cascode voltage     U cascode,21  cascode voltage     U cascode,9  cascode voltage     U out  output voltage     U ref  reference voltage     U sel  selection voltage     U th  threshold voltage     U th,M1  threshold voltage of the transistor M 1      U th,M1,ref  threshold voltage of the transistor M 1 ,ref