Abstract:
What is described is a battery management architecture that eliminates previously described problems of the previous solutions and compensates for the extra cost of a cell-balancing circuit. These advantages are achieved by integrating the voltage step-up and balancing functions as well as charging functions inside a single converter topology. Instead of providing the entire output voltage and power, the converter in this configuration is merely assisting the battery by providing a portion of the power delivered to the load, rather than the entirety of the power delivered to the load. This portion of power is proportional to the difference between the output and the battery pack voltages.

Description:
BACKGROUND 
     A typical power management system of an electric or hybrid vehicle is shown in  FIG. 1 . It consists of a battery pack  101  (usually comprised of large number of Lithium-Ion or Lithium-Polymer cells), a step-up stage (usually boost-based converter)  103 , and a motor drive  104  providing power for an electric motor  102 . In many vehicle designs there is regenerative braking which permits recharging of the battery pack  101 , the details of which are omitted for clarity in  FIG. 1 . 
     In some cases, the power management system also includes a cell balancing circuit  105 , which compensates for different states of charges (SOC) of individual cells, as shown in  FIG. 1 . The SOC variations usually occur due to the aging and variations in the manufacturing process. Through cell balancing the effective capacity of the battery pack can be significantly increased. 
     The balancing circuits can be divided into two general categories. The first one is the passive balancing systems, in which the cells are balanced by dissipating energy from excessively charged cells, through resistors. 
     The second category is the active balancing systems, which are far more efficient. In these systems, the energy of over-charged cells is transferred to those with less charge using dc-dc converters. Even though the benefits of the active cell balancing are known, their use is relatively sparse, due to the overly large extra cost and weight the cell balancing circuits add to the system. 
     Balancing systems of possible interest include those described in the following US patent published applications:
     US 2012-0256593 A1   US 2012-0249052 A1
 
and in the following granted US patents:
   U.S. Pat. No. 7,936,150   U.S. Pat. No. 8,269,455
 
and in the following published international patent application:
   WO/2012/172468
 
all of which are owned by the same assignee as the assignee of the present patent application.
   

     A prior-art balancing circuit  105  might utilize a buck-boost and a Cuk converter for cell balancing. These topologies can be implemented with a relatively small number of active components and regulated with fairly simple controllers. However, these circuits are fairly large in form factor, which reflects on the overall physical size of the system. Implementations based on the use of a bi-directional flyback and a two stage flyback converters have been proposed. Compared to other solutions, these systems lower efficiency at high power levels. 
     Others have proposed a configurable system for cell balancing using a large number of switches to transfer the energy between cells. The main drawback of such a system is that the balancing becomes too slow for the energy transfer between cells having similar output voltages. 
     Many prior-art approaches direct themselves only to a single one of the functions suggested by the functional blocks of  FIG. 1 . This prompts the alert reader to recall the functional block  103 . The step-up converter  103  of  FIG. 1  steps up the voltage from the battery  101  to the extent that is required to provide a desired DC voltage to the load  104 . It will be appreciated that the step-up converter  103  as shown in  FIG. 1  is required to be able to accommodate the entirety of the power transferred to the load  104 . This means that the converter  103  must use switches (typically semiconductor switches) and reactive components (for example capacitors and inductors) that allow the converter to pass the full load power, rated for full load currents and rated for the full reverse voltages that might arise in serving the full load voltage. In some cases the current and voltage for which the switches must be rated is larger than the current and voltage at the output, for example in a flyback circuit. The switches in a boost converter also conduct larger than the load current. 
     It would be desirable if a way could be found to accomplish the aims of the functional blocks of  FIG. 1  in a more integrated way, using fewer components than in prior-art approaches, and using components that would not require the full-voltage ratings of the semiconductor switches in some prior-art approaches. The cost of a semiconductor switch often increases at least linearly with the voltage rating of the switch and may increase faster than linearly. Thus there are rewards for the designer who devises topologies and approaches that permit use of components with smaller voltage ratings as compared with those needed in prior-art topologies and approaches. 
     SUMMARY OF THE INVENTION 
     What is described is a battery management architecture that eliminates previously described problems of the previous solutions and compensates for the extra cost of a cell-balancing circuit. These advantages are achieved by integrating the voltage step-up and balancing functions as well as charging functions inside a single converter topology. Instead of providing the entire output voltage and power, the converter in this configuration is merely assisting the battery by providing a portion of the power delivered to the load, rather than the entirety of the power delivered to the load. This portion of power is proportional to the difference between the output and the battery pack voltages. 
    
    
     
       DESCRIPTION OF THE DRAWING 
       The invention will be described with respect to a drawing in several figures. 
         FIG. 1  shows a prior-part approach to cell balancing and providing converted power to a load. 
         FIG. 2  shows in functional block diagram form the topology according to an embodiment of the invention. 
         FIG. 3  shows the system of  FIG. 2  in greater detail. 
         FIG. 4  shows a single cell channel of the system in  FIG. 3  in greater detail. 
         FIG. 5  shows control waveforms. 
         FIG. 6  shows signal levels for various stages during a cycle of operation in an embodiment of the invention. 
         FIG. 7  shows equivalent circuits for a single cell channel, for various modes of operation. 
         FIG. 8  shows the system of  FIG. 4  with snubbers. 
         FIG. 9  shows the controller  106  in greater detail. 
         FIG. 10  shows various inductor topologies that may be employed. 
     
    
    
     Where possible, like reference numerals have been employed for like elements. 
     DETAILED DESCRIPTION 
     The introduced topology, here referred to as an “assisting converter” architecture, is shown in  FIG. 2 . The converter  106  operates at such that the stepped-up output voltage at  111  is formed as a sum of the battery pack voltage V batt  (across battery  101 ) and the output voltage of a bidirectional multi-input single output converter stage, V f , (across capacitor C f ) where the inputs of the converter  106  are connected to the battery cells of the battery  101 . 
     As described below, the assisting configuration drastically reduces power processing requirements needed to achieve required conversion and, consequently, improves power processing efficiency. The introduced topology also allows fast cell balancing even when the cells have similar or equal voltages and allows energy transfer between any two cells in the battery pack. Furthermore, unlike other solutions, the topology provides functionality of the system even when a significant number of cells in the battery pack are out of function, potentially improving overall system reliability. 
     The principle of operation of a general assisting converter  106  shown in  FIG. 2  can be described through a comparison with the conventional system of  FIG. 1 . For the assisting converter  106  the power delivered to an output load  104  that takes current I out  is:
 
 P   out   =V   out   I   out =( V   batt   +V   cf ) I   out   =P   converter   +P   batt     —     direct ,
 
where P converter =V cf I out  is the portion of the battery power delivered through the converter and P batt     —     direct =V batt I out  is the remaining portion, directly delivered by the battery without any processing.
 
     For the conventional converter  103  ( FIG. 1 ), P converter =P out  and P batt     —     direct  is 0, since the step-up converter processes all of the power delivered to the load. This means that, in comparison with the conventional system of  FIG. 1 , the converter  106  in the assisting configuration of  FIG. 2  is required to process V cf /V out , times lower power and, thus, can be implemented with smaller components. 
     The reduction in processing power also makes design of a highly efficient assisting converter  106  simpler. For the assisting system of  FIG. 2  the overall power processing efficiency can be defined as: 
               η   =       (             P   batt_direct       P   out       ·   100     ⁢   %     +         P   conv       P   out       ⁢     η   conv         )     =     (             V   batt       V   out       ·   100     ⁢   %     +         V   conv       V   out       ·     η   converter         )         ,         
where η converter  is the efficiency of the assisting converter  106 . This expression can be explained by looking at the system of  FIG. 2  and noticing that the power processing losses occur only for the portion of power that is not directly provided by the battery  101 . As described early, this portion of power is proportional to the ratio of the output and converter-provided voltages.
 
     For example, if the assisting converter  106  is providing a 20% of the output voltage and has a very low power processing efficiency of 50%, a relatively high power processing efficiency of 90% at the system level still can be achieved. The system may be designed so that the capacitor  107  carries only 20% of the voltage intended to be delivered to the load, or only 10%, or only 5%. 
     This shows that, in order to achieve targeted overall system efficiency, the assisting converter  106  ( FIG. 2 ) can be designed with much less stringent power processing requirements than the conventional converter  103  ( FIG. 1 ), further reducing the overall system cost and complexity. 
     It will be helpful to characterize some of the benefits of the inventive topology of  FIG. 2  by way of a generalization of the disclosed topology. A series of cells (in battery  101 ) is seen. Each cell has a bidirectional converter associated with it (part of block  106 ). The bidirectional converter relating to a particular cell is able to draw from capacitor  107  to charge up the particular cell. The bidirectional converter relating to a particular cell is able to draw from the particular cell to charge up capacitor  107 . This provides three distinct functions:
         if a charging current is supplied to the system, the system is able to receive that current and is able to pass along the charging current to the various cells each according to its own needs (so that the charging process leads to a near-balance in the state of charge of the cells);   when power is being supplied to the load, the system is able to draw upon the various cells as needed to charge up the capacitor  107  so as to lead to a nearly constant voltage being supplied to the load at  111 ;   in any regime (discharging, charging, or quiescence) a balancing of cells (in terms of state of charge) may be accomplished.       

     Yet another benefit presents itself, namely that even if a particular cell fails “open” the system will be able to maintain a substantial portion of its function despite loss of that cell. Indeed the system will be able to continue its function even with loss of two or more cells in an “open” failure mode. 
     Finally the alert reader will appreciate that the topology of  FIG. 2  may be generalized to the case of a single cell or a battery of cells that is employed as a simple two-terminal device. The cell (or two-terminal battery) may be placed in series with a capacitor  107  with the assisting converter  106  connected to both. In such a situation, many of the benefits of the topology are preserved such as the reduced need for high voltage ratings in the capacitor and in the semiconductors of the converter, as well as the need to worry only about the conversion efficiency of the portion of the power associated with the voltage on the capacitor  107 . (More will be said about this below.) 
     Battery Cell Balancing. 
     It will be recalled from  FIG. 1  that often a balancing function (block  105 ) is provided. In the system of  FIG. 2 , to provide battery cell balancing, the input currents of the bi-directional multi-input converter  106  can be regulated. The regulation can be performed such that the currents provided by (drawn from) the individual cells are proportional to their states of charge. The alert reader will appreciate that it is possible to achieve an energy transfer from cells with a higher state of charge to other cells having less charge, through what may be termed an “indirect” energy transfer. In this process, cells with high SOC transfer energy to the capacitor, while the cells with low SOC take energy from it. Both of these cases are demonstrated as follows. 
     An implementation of the assisting converter  106  based on a multi-phase isolated dual active bridge converter is shown in  FIG. 3 . In addition to providing galvanic isolation and bi-directional energy flow, the dual active bridge (DAB) has a number of other features that make it very attractive for the targeted applications. Those include high power processing efficiency (achieved through inherent zero voltage or current switching) and much smaller inductor volume comparing to the conventional hard switching and resonant topologies. The small inductance value opens a possibility for elimination of a discrete inductor through the utilization of the transformer leakage inductance. 
     Another interesting feature of the DAB is that it can operate with both continuous input and continues output currents, thus reducing requirements for input and output filters. 
     The system of  FIG. 3  consists of a number of transformers (e.g.  123 ) whose primary windings are connected to the individual battery cells (e.g.  121 ) and the secondary windings linked to the output capacitor  107 , through small inductors  127 . 
     The linkage between the transformer  123  and its respective cell  121  is by means of an active bridge  122 . The active bridge  122  has four semiconductor switches, typically FETs (field-effect transistors). 
     The linkage between the transformer  123  and the capacitor  107  is also by means of an active bridge  124 . The active bridge  124  also has four semiconductor switches, typically FETs (field-effect transistors). 
     It is these semiconductor switches that are driven by control signals  128  from the controller  125 . The control signals have phase relationships which bring about for example a draw of current from one or another of the cells, or a pumping of current into one or another of the cells, and which bring about a charging-up of capacitor  107  or a drawing-down of capacitor  107 . 
     An implementation based on a multi-winding transformer is also possible. This is shown in  FIG. 10 . 
     The digital controller  125  implementing phase-shift modulation regulates the operation of this converter  106 . The phase shift control provides both the output voltage regulation (charging of capacitor  107  to tend toward a constant voltage available to load  104 ) and cell balancing (balancing the energy content of the various cells) through the regulation of the currents to and from the individual cells. 
     Typical waveforms of a DAB converter connected between two DC sources are shown in  FIG. 5 . The power transfer between the sources (each of the cells and the output port of the converter in this case) can be derived from the well-known power transfer formula for sinusoidal systems: 
                 P   k     =         nV   A     ⁢     V   B     ⁢     sin   ⁡     (     φ   k     )           ω   ⁢           ⁢   L         ,         
where V A  and V B  are the amplitudes of the two sinusoidal sources, φ k  is the phase shift (delay) between the voltages, and ωL the impedance value of an inductor placed between them. In the case of  FIG. 5 , the waveforms are not sinusoidal but are square waves, and so the power transfer equation becomes:
 
                 P   k     =     n   ⁢         V   cell     ⁢     V   cf     ⁢       φ   k     (     π   -          φ   k                  πω   ⁢           ⁢   L           ,         
where V cell  is the voltage of the battery cell (e.g.  121  in  FIG. 3 ), n the turns ratio of the transformer, V cf  is the voltage of the floating capacitor  107  ( FIGS. 2 ,  3 , and  4 ), ω=2πf sw  where f sw  is the switching frequency of the converter, and φ k  is the phase shift (delay) between the voltages v 1 (t) and v 2 (t), shown in  FIGS. 4 and 5 .
 
       FIG. 6  shows realistic key waveforms of the DAB from  FIG. 4 . The diagrams show the state of the switching components that include non-overlapping transistor times t d , switch nodes voltages (nv 1 (t), i.e. v 1 (t) reflected on the secondary transformer side, and v 2 (t)), and the inductor voltage and current waveforms, v L (t) and i L (t), respectively. The diagrams also show the current supplied by the battery cell i E (t).  FIGS. 6(   a ) to ( d ) shows transistor on-off states.  FIG. 6(   e ) shows switch node voltages.  FIG. 6(   f ) shows voltage across the inductor.  FIG. 6(   g ) shows inductor current.  FIG. 6(   h ) shows battery cell current. 
     The non-overlapping times prevent simultaneous conduction of both switches of a single converter branch, that is, they prevent a short circuit. 
     Eight equivalent circuits of  FIG. 7 , representing different modes that the left side of the DAB goes through over a switching period T s , can be observed. In these equivalent circuits of  FIG. 7 , non-conducting MOSFETs are replaced with their parasitic drain-source capacitances, labeled as C par . Likewise the conducting MOSFETs are replaced with short circuits or diodes, depending on the state of the gate drive signal. The equivalent circuits also include the leakage inductance of the primary side of the transformer L p . 
     Mode 1 corresponds to the time interval t 0  to t 1  of  FIG. 6(   g ), during which Q11 and Q14 are turned on while Q12 and Q13 are switched off, during which and the primary side current i PE (t) is negative, that is, is leaving the “dot” on the inductor. 
     Mode 2 occurs during the time interval t 1 &lt;t≦t 2 . This mode starts when i PE (t), that is i L (t), changes polarity and has the same state of switches as Mode 1. 
     Mode 3 occurs during the transistors&#39; non-overlapping time (between t 3  and t 4 ) when all of the switches are turned off. It can be seen that in this mode a resonant circuit consisting of the L p  and the capacitive network C par 11 to C par 14 is formed, meaning that oscillations might occur, depending on the speed of the body diodes of the MOSFETs. Ideally, for the case when the antiparallel body diodes are fast, a soft transition between Mode 3 and Mode 4 occurs. This happens when the C par 13 is discharged to a value of approximately −V F  and the charge of C par 11 is approximately equal to V cell +V F , where V F  is the forward voltage drop of the body diodes, shown in the equivalent circuit of Mode 4. 
     In Mode 4, the anti-parallel diodes conduct and the maximum voltage across the transistors is clamped to a value of V cell +2 VF . 
     For the case when the body diodes of the MOSFETs are slow, compared to the period of the resonant circuit oscillations, and, hence, are not able to react, the circuit does not go through Mode 4. The amplitude of the overshoot is directly proportional to the energy stored in the leakage inductance at the time instant t 3 , i.e. W E =½i L (t 3 ) 2 L p , and inversely proportional to the equivalent of the C par 11-C par 14 capacitive network. 
     Mode 3 (or Mode 4) is followed by Mode 5. Mode 5 starts immediately after Q12 and Q13 are turned on and occurs during the time interval t 4 &lt;t≦t 5 . This mode is equivalent to Mode 1. If prior to this mode the DAB was in Mode 4, both transistors turn on softly, with zero voltage transition. For a slow body diode case, i.e. when the previous state is Mode 3, a soft transition cannot be guaranteed and, consequently, increased switching losses occur. 
     A similar analysis can be carried out for Modes 6 to 8. 
     The discussion just given shows that the parasitic drain source capacitance increases the voltage stress across the switches and negatively affects the converter efficiency for the case when the antiparallel diode is slow compared to the frequency of oscillations. The discussion also indicates that the voltage stress value and the frequency of oscillations are inversely proportional to the equivalent capacitance of the C par 11-C par 14 network. 
     To minimize this effect a straightforward solution would be to use faster Schottky diodes connected in parallel with the body diodes of the transistors. These diodes would provide snubber action. They would allow the converter  106  to enter Mode 4, described in the previous discussion, and consequently would eliminate voltage overshoots while providing zero voltage switching (ZVS). 
     To minimize the cost, in this case, instead of using extra Schottky diodes, a small ceramic capacitor is placed in parallel with each of the transistors. These capacitors, labeled as C s  in  FIG. 8 , reduce the frequency of the resonant circuit oscillation during the non-overlapping times. This allows the body diodes to clamp the voltage. 
     The waveform of  FIG. 6(   g ) shows that the current provided by the battery has large variations. These variations could reduce the battery life time and, due to a large rms current value, have a negative effect on the converter efficiency. 
     To eliminate this effect a decoupling capacitor C dec    141  is placed across the primary side bridge, as shown in  FIG. 8 . Together with the parasitic inductance of the connecting wires this capacitor  141  forms a second-order filter which drastically reduces the input, current ripple. 
     In addition to eliminating the large ripple, C dec    141  can also be potentially used for improving the reliability of the system in the case of a battery cell failure. In such a situation the capacitor can act as a replacement for the battery, capable of maintaining the cell voltage and transferring reactive power. 
     Controller. 
     The main goal of the controller  125  of  FIG. 3  is to maintain the output voltage (at  111 ) at the desired value while providing cell balancing. It is shown in more detail in  FIG. 9 . The control is performed through phase shift modulation, where the angle on the secondary side is used for the output voltage and the settings of the angles on the primary side (relative phase shifts) is used for cell balancing. In this case, the voltage loop is implemented in a digital fashion. The voltage at  111  is attenuated (attenuator  151 ) yielding an output voltage HV out (t) which is converted into its digital equivalent with an analog-to-digital converter (ADC)  152  yielding signal H vout [n]. This value is than compared (at comparator  154 ) to the desired reference V ref [n] (reference  153 ) and the resulting error e[n] is passed to a Voltage loop PID compensator  155 . The compensator  155  calculates a value jv[n], which is the input for the secondary side phase shift modulator  156  (controlling the secondary-side bridge  124 ). Based on this input the secondary side phase shift modulator  156  adjusts the phase shift between the secondary side switches (bridge  124 ) and one of the set of primary side switches, i.e. a reference set, such that the desired output voltage is obtained at  111 . 
     The relative phase shifts between the DAB switches on the primary sides (for example bridge  122 ) are adjusted based on the cells&#39; state of charge (SOC) (input  126 ). The calculation of the relative phase shifts between primary side modules is performed by the Primary side phase shift calculator ( 167 ), which sends four control signals, jr1[n] to jr4[n], to the Primary side phase shift modulator  128 , for each of the bridges such as  122 . 
     What was just described is passing the analog voltage to an ADC and then carrying out a digital difference calculation and carrying out later steps digitally. The alert reader will appreciate that there are many ways to provide a controller that will offer the benefits of the invention. The controller  125  may be implemented by appropriate firmware in a microcontroller of suitable bandwidth. Alternatively it may be implemented by an FPGA with suitable programming. Another approach could be the use of hardware combining mixed-signal circuits, for example analog-to-digital converters for measurement, and digital logic for calculations. An implementation based on the use of application specific integrated circuits (ASIC) is also possible. 
     A simplified balancing method may be employed instead of using continuously variable phase shifts for the balancing functions. In this implementation, one of n pre-defined discrete values of the relative phase shifts is assigned to each cell, depending on its state of the charge. This way computational overhead is minimized. 
     EXAMPLE 
     To verify the previously described concepts, a 4-cell, 200 W experimental setup was built and tested. At the input, four 6V, 12 AH Lead-Acid cells were used. The DAB stages operated at a switching frequency of 100 kHz and provided a 42 V regulated output. The component values for the power stage of  FIG. 8  are shown in this table: 
     
       
         
               
               
             
               
               
               
             
               
               
             
               
               
               
             
               
               
             
               
               
               
             
               
               
             
               
               
               
             
           
               
                   
               
               
                 Component 
                 Value 
               
               
                   
               
             
             
               
                   
               
             
          
           
               
                 Power Transfer Inductance (L t ) 
                 10  
                 μH 
               
               
                 Primary Leakage Inductance (L 1kp ) 
                 0.5  
                 μH  
               
             
          
           
               
                   
                 (measured and calculated) 
               
             
          
           
               
                 Secondary Leakage inductance (L 1ks ) 
                 0.5  
                 μH  
               
             
          
           
               
                   
                 (measured and calculated) 
               
             
          
           
               
                 Filter Capacitance (C dec ) 
                 4.4  
                 mF 
               
             
          
           
               
                 Transformer Turns Ratio (1:n) 
                 1:4 
               
             
          
           
               
                 Input Parasitic Inductance (L par ) 
                 300  
                 nH (measured) 
               
               
                 Drain to Source Capacitance LV side (C parl1 ) 
                 0.75  
                 nF (estimated) +   
               
               
                 Drain to Source Capacitance HV side (C par1 ) 
                 0.45  
                 nF (estimated) +   
               
               
                 Snubber Capacitance 
                 47  
                 nF 
               
               
                   
               
             
          
         
       
     
     The controller of this setup was implemented with an FPGA system. For test purposes the system was largely over-designed allowing an opportunity to verify operation of the assisting converter at higher power levels. The tests were performed for cell balancing as well as for developing the voltage assist of the capacitor  107 . Operation of this converter as a battery charger was also tested. The converter achieved a peak efficiency of 92%. 
     The discussion above focuses on a system which is connected with a battery composed of electrochemical cells. Such a system might, however, also offer some of its benefits to a solar panel array of photovoltaic modules. 
     The alert reader will likewise appreciate that while the system is described as connected with a battery of many cells, the system can likewise offer its benefits in the case of a single cell. In such a case it provides a more efficient DC-to-DC converter because less than all of the power is being passed through the converter. 
     It is interesting to consider the ability of this system to tolerate any of several possible failure modes. As mentioned above, if a single cell were to fail “open”, a suitably sized capacitor  141  may permit continued system function by stepping into the shoes of the failed cell. 
     In many prior-art systems, a capacitor is placed in parallel with the load, at the output of a step-up (boost) stage (for example within block  103  in  FIG. 1 ) of a system. In  FIG. 1  if a capacitor is employed in the converter  103  at its output, the capacitor will need to be rated for the full output voltage. In contrast, the capacitor  17  need only be rated for the voltages that it will encounter, which may be only a fraction of the load voltage. As the price of a capacitor is often proportional to the square of the voltage rating, the capacitor in block  103  of  FIG. 1  will cost much more than the capacitor  107  in  FIG. 2 . This permits the disclosed system to be less expensive compared with some prior-art systems. 
     In sum, a new system level architecture for providing both battery balancing and step-up voltage functions has been described. The architecture is based on an “assisting converter” concept where a low-power converter is used merely to provide a voltage that is added to the battery pack voltage to yield the desired output. The assisting converter can also provide cell balancing. In comparison with conventional systems this architecture drastically reduces the power processing requirements of the step-up power stage and it relaxes the requirements regarding converter power processing efficiency. An implementation of this concept based on multi-input isolated dual active bridge topology (DAB) has been demonstrated. In comparison with a single step-up stage the multi-input DAB allows operation at a higher switching frequency, allows implementation with lower voltage rating low-cost components, and provides better power processing efficiency.