Abstract:
The propagation delay of a combinatorial circuit in a large-scale integrated circuit is tested by carrying out two scan tests. Both scan tests generate the same input signal transitions to the combinatorial circuit. One scan test scans the outputs of the combinatorial circuit after the transitions propagate through the combinatorial circuit, using separate launch and capture clock pulses. The other test scans the outputs of the combinatorial circuit before the transitions propagate through the combinatorial circuit, using the same clock pulse for both launch and capture. Use of both tests ensures that propagation delay faults are not masked by large capture clock delays.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to a method of testing a large-scale integrated (LSI) circuit with a built-in scan test function, to detect delay faults.  
         [0003]     2. Description of the Related Art  
         [0004]     Part of an LSI circuit with a built-in scan test function is illustrated schematically in  FIG. 1 . Combinatorial circuits  1 A and  1 B are linked through scan flip-flops (S-FF)  2 B 1 ,  2 B 2 , . . . ,  2 B m , which are interconnected to form a scan chain  2 B. Each scan flip-flop includes a selector  7  controlled by a scan enable signal SE to select an input signal and a flip-flop  8  that latches the selected signal in synchronization with a clock signal CKB and outputs the latched signal.  
         [0005]     Signals output in parallel from combinatorial circuit  1 A are supplied to the first inputs of the selectors  7  in the scan flip-flops  2 B 1 ,  2 B 2 , . . . ,  2 B m , and the signals output from the flip-flops  8  are supplied in parallel to the input side of combinatorial circuit  1 B. The output of the flip-flop  8  in each of the first m−1 scan flip-flops  2 B 1 ,  2 B 2 , . . . ,  2 B m  is also connected to the second input of the selector  7  in the next scan flip-flop  2 B 2 ,  2 B 3 , . . . ,  2 B m . The second input of the selector  7  in the first scan flip-flop  2 B 1  in the chain is connected to a scan input terminal  3 B, and the output of the flip-flop  8  in the last scan flip-flop  2 B m  in the chain is connected to a scan output terminal  4 B.  
         [0006]     Signals from another chain  2 A of scan flip-flops  2 A 1 ,  2 A 2 , . . . ,  2 A k  are supplied in parallel to the input side of combinatorial circuit  1 A. The second input of the selector  7  in scan flip-flop  2 A 1  is connected to a scan input terminal  3 A; the output of the flip-flop  8  in scan flip-flop  2 A k  is connected to a scan output terminal  4 A.  
         [0007]     A third chain  2 C of scan flip-flops  2 C 1 ,  2 C 2 , . . . ,  2 C n  is connected to the output side of combinatorial circuit  1 B. The second input of the selector  7  in scan flip-flop  2 C 1  is connected to a scan input terminal  3 C; the output of the flip-flop  8  in scan flip-flop  2 C n  is connected to a scan output terminal  4 C.  
         [0008]     A clock signal CLK is supplied from a clock terminal  5  to the clock input terminal of the flip-flop  8  in each scan flip-flop via a clock distribution circuit or clock tree. The scan enable signal SE is supplied to the control terminal of the selector  7  in each scan flip-flop from a scan enable terminal  6 .  
         [0009]     A conventional delay test of combinatorial circuit  1 B in  FIG. 1  is conducted as illustrated by the signal waveform diagram in  FIG. 2 . It is assumed that combinatorial circuits  1 A and  1 B input and output four signals each. The delay being tested is the propagation delay D from the input of test data to the input side of combinatorial circuit  1 B to the output of signals indicating the results of logic operations on the test data from the output side of combinatorial circuit  1 B. The clock signal CLK supplied from the clock terminal  5  propagates as a clock signal CKB with a delay α to scan chain  2 B and as a clock signal CKC with a delay β to scan chain  2 C.  
         [0010]     First, the scan enable signal SE is set to the high logic level, switching the selectors  7  of all scan flip-flops to the second input side. Scan flip-flops  2 A 1  to  2 A 4  thereby form a shift register extending from scan input terminal  3 A to scan output terminal  4 A, the signals output from the scan flip-flops  2 A 1  to  2 A 4  also being supplied in parallel to combinatorial circuit  1 A. Similarly, scan flip-flops  2 B 1  to  2 B 4  form a shift register extending from scan input terminal  3 B to scan output terminal  4 B, the signals output from scan flip-flops  2 B 1  to  2 B 4  also being supplied in parallel to combinatorial circuit  1 B.  
         [0011]     At time t 1  in  FIG. 2 , the scan input signals SIA and SIB supplied to scan input terminals  3 A and  3 B are set according to test data TDA and TDB to signal levels ‘a 4 ’and ‘b 4 ’ (where ‘a 4 ’and ‘b 4 ’ are either the high or low logic level) and a clock pulse is supplied to the clock terminal  5 . After propagation delays in the clock distribution circuitry, scan flip-flops  2 A 1  and  2 B 1  latch the data ‘ 4   a ’ and ‘ 4   b’.    
         [0012]     Next, at times t 2 , t 3 , and t 4 , scan input signals SIA (‘a 3 ’, ‘a 2 ’, ‘a 1 ’) are supplied from the scan input terminal  3 A one by one and shifted into scan chain  2 A in synchronization with the clock signal CLK. Scan input signals SIB (‘b 3 ’, ‘b 2 ’, ‘b 1 ’) are similarly shifted from scan input terminal  3 B into scan chain  2 B. After the above scan shift operations, test data TDA (‘a 1 ’, ‘a 2 ’, ‘a 3 ’, ‘a 4 ’) are held in scan flip-flops  2 A 1  to  2 A 4  and supplied in parallel to combinatorial circuit  1 A, while test data TDB are held in scan flip-flops  2 B 1  to  2 B 4  and supplied in parallel to combinatorial circuit  1 B. Combinatorial circuit  1 A performs logic operations on test data TDA and, after a certain delay, outputs resultant signal data RDA in parallel as an input test pattern. In the meantime, combinatorial circuit  1 B performs logic operations on test data TDB and, after a certain delay, outputs resultant signal data RDB 1  in parallel.  
         [0013]     At time t 5 , the scan enable signal SE at terminal  6  is driven low, switching the selectors  7  of all scan flip-flops to the first input side. The signals output from combinatorial circuit  1 A are now supplied to scan chain  2 B, but the data latched in scan flip-flops  2 B 1  to  2 B 4  do not immediately change, because no clock pulse is supplied to the clock terminal  5 .  
         [0014]     At time t 6 , a launch clock pulse is supplied from the clock terminal  5 , reaching scan chain  2 B as clock signal CKB with a delay α. The signal data RDA output from combinatorial circuit  1 A and received by scan flip-flops  2 B 1  to  2 B 4  are supplied almost simultaneously to combinatorial circuit  1 B. (As the circuits distributing the clock signals to scan flip-flop  2 B 1  to  2 B 4  are not quite identical, these flip-flops do not operate with perfect simultaneity.) Combinatorial circuit  1 B now performs logic operations on the newly supplied signal data RDA and, after a concomitant delay D, outputs the results RDB 2  to the first inputs of the selectors  7  in scan flip-flops  2 C 1  to  2 C 4 . During this delay D, the signals output from combinatorial circuit  1 B switch from their old values to their new values.  
         [0015]     After a delay T from time t 6 , a capture clock pulse is supplied from the clock terminal  5  at time t 7 , reaching scan chain  2 C as clock signal CKC with a delay β. Scan flip-flops  2 C 1  to  2 C 4  now latch the resultant signal data RDB 2  from combinatorial circuit  1 B. The scan output signal SOC output from scan output terminal  4 C is ‘c 4 ’.  
         [0016]     At time t 8 , the scan enable signal SE returns to the high logic level and the selectors  7  of all scan flip-flop are switched to the second input side to resume scan shift operations.  
         [0017]     The remaining data (‘c 3 ’, ‘c 2 ’, ‘c 1 ’) captured in scan flip-flops  2 C 1  to  2 C 3  are then shifted one by one into scan flip-flop  2 C 4  in synchronization with clock signal CKC and output serially as scan output signal SOC from scan output terminal  4 C at times t 9  to t 11  (with a delay of β in each case).  
         [0018]     The propagation delay D of the logic operations performed in combinatorial circuit  1 B can therefore be tested by checking the scan output signal SOC following times t 7 , t 9 , t 10 , and t 11 . If the scan output signal SOC matches the values (the output test pattern) expected to be obtained from the input data RDA by the logic operations performed in combinatorial circuit  1 B, it can be concluded that the following inequality (1) is satisfied. 
 
α+ D&lt;β+T   (1) 
 
         [0019]     When the scan output signal SOC does not match the expected values, it can be concluded that the above inequality is not satisfied. This indicates that the delay D being tested has been prolonged for some reason, such as a defect introduced in the manufacturing process.  
         [0020]     A delay test of the LSI circuit in  FIG. 1  is carried out using the equipment illustrated in  FIG. 3 . First, logic circuit information describing the combinatorial circuits of the LSI circuit to be tested is supplied to a test pattern generating device  10  (for example, a computer with a program for generating test pattern data) that can generate test patterns for a delay test, and the relevant input and output scan segments are specified. In this example, the circuit to be tested is combinatorial circuit  1 B, the relevant input scan segments are the scan chains  2 A and  2 B on the input sides of combinatorial circuits  1 A and  1 B, and the relevant output scan segment is the scan chain  2 C on the output side of combinatorial circuit  1 B.  
         [0021]     The test pattern generating device  10  then generates test pattern data indicating the transitions over time of the signals CLK, SE, SIA, SIB, and SOC at terminals  5 ,  6 ,  3 A,  3 B, and  4 C in the LSI circuit under test. The launch-to-capture delay T in the test pattern data is selected so that the above inequality (1) will be satisfied when the propagation delay D of combinatorial circuit  1 B is within tolerance, and will not be satisfied when the propagation delay D is over tolerance.  
         [0022]     Next, the resultant test pattern data are read into the scan test device  20 . The scan test device  20  has a random-access memory (RAM)  22  in which the timings of the test pattern data are mapped onto different addresses. The status (‘1’ or ‘0’) of signals CLK, SE, SIA, and SIB and the expected status of signal SOC at each timing are stored at the corresponding address. The scan test device  20  also comprises a clock generator or oscillator (OSC)  24  that generates a read clock signal CK, an address counter  26  that counts the clock signal CK to generate a memory address signal ADR, and a comparator (CMP)  28 . Data read out one by one from the memory  22  according to the address signal ADR are supplied as signals CLK, SE, SIA, SIB to the corresponding terminals  5 ,  6 ,  3 A and  3 B of the LSI circuit under test  30 .  
         [0023]     The expected SOC signal data read out from the memory  22  are supplied to one of the input terminals of the comparator and compared with the scan output signal SOC obtained from scan output terminal  4 C of the circuit under test  30  (the scan output signal SOC is supplied to the other terminal of the comparator). The result of the comparison is output to indicate the test result.  
         [0024]     The conventional procedure by which the test equipment in  FIG. 3  is used to carry out a delay test of an LSI circuit  30  is shown by the flowchart in  FIG. 4 .  
         [0025]     In step S 1  in  FIG. 4 , information specifying the circuit configuration of combinatorial circuits  1 A,  1 B and other combinatorial circuits in the LSI circuit is set in the test pattern generating device  10 .  
         [0026]     In step S 2 , the scan segments on the input and output sides of the combinatorial circuit to be tested are specified. This completes the setting of the test pattern generating device  10 .  
         [0027]     In step S 3 , the test pattern generating device  10  generates the input test pattern that will propagate from the scan flip-flops in the input scan segments to the scan flip-flops in the output scan segment.  
         [0028]     In step S 4 , the test pattern generating device  10  generates the output test pattern expected to appear in the output scan segment after the signal transition propagates from the input scan segment to the output scan segment.  
         [0029]     In step S 5 , a launch clock pulse and a capture clock pulse are incorporated into the input test pattern generated in step S 3  and the output test pattern generated in step S 2 , to generate test pattern data for the delay test.  
         [0030]     In step S 6 , the test pattern data for the delay test are set in the scan test device  20 . In step S 7 , the delay test is executed by supplying test signals from the scan test device  20  to the LSI circuit under test at times controlled by the clock generator  24  and address counter  26 .  
         [0031]     In step S 8 , the expected SOC output values generated as test pattern data in advance are compared with the scan output signal SOC actually output from the LSI circuit under test. If the SOC test pattern data signal and the SOC scan output signal match, the circuit passes the delay test; otherwise, the circuit is rejected as defective.  
         [0032]     Japanese Patent Application Publication No. 5-119122 describes a method of generating test patterns for scan circuits so as to shorten the test time.  
         [0033]     A general problem encountered when delay tests are carried out as described above is that a capture clock propagation delay may mask combinatorial logic delay faults. It is possible to compensate for a moderate known capture clock delay β by shortening the launch-to-capture clock delay T, but this becomes impractical when β is very large, or is unknown. For example, if the capture clock delay β is so great that α+D&lt;β, then the inequality (1) given above will be satisfied regardless of the launch-to-capture delay T. If the capture clock is greatly delayed, then the scan chain  2 C that captures the result data will sometimes receive the expected signals even though the circuit under test has a delay fault, and defective circuits will be misjudged as normal.  
       SUMMARY OF THE INVENTION  
       [0034]     An object of the present invention is to provide an accurate method of conducting a delay test of a large-scale integrated circuit.  
         [0035]     The invented method tests a large-scale integrated circuit including a combinatorial circuit and scan flip-flops. The scan flip-flops are interconnected to form an input scan segment for launching at least one signal into the combinatorial circuit and an output scan segment for capturing at least one signal output from the combinatorial circuit. The method includes:  
         [0036]     specifying the configuration of the combinatorial circuit and the input and output scan segments;  
         [0037]     generating an input test pattern for placement in the input scan segment to create predetermined input signal transition(s) for the combinatorial circuit;  
         [0038]     generating a first output test pattern indicating the signal value(s) expected to appear in the output scan segment after the input signal transition(s) propagate through the combinatorial circuit;  
         [0039]     generating a second output test pattern indicating the signal value(s) expected to appear in the output scan segment before the input signal transition(s) propagate through the combinatorial circuit;  
         [0040]     generating a first delay test pattern incorporating the input test pattern and the first output test pattern;  
         [0041]     generating a second delay test pattern incorporating the input test pattern and the second output test pattern;  
         [0042]     conducting delay tests of the large-scale integrated circuit with both the first and second delay test patterns;  
         [0043]     passing the large-scale integrated circuit as normal if it passes both delay tests, and rejecting the large-scale integrated circuit as defective if it fails either of the two delay tests.  
         [0044]     The first delay test pattern tests the propagation delay of the combinatorial circuit. The second delay test pattern tests the delay of the clock signal used to capture the signal(s) output from the combinatorial circuit to the output scan segment. Use of both test patterns ensures that propagation delay faults will not be masked large clock delays. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0045]     In the attached drawings:  
         [0046]      FIG. 1  is a schematic diagram of part of an LSI circuit having a scan test function;  
         [0047]      FIG. 2  is a signal waveform diagram illustrating a conventional delay test of the LSI circuit in  FIG. 1 ;  
         [0048]      FIG. 3  illustrates an equipment configuration for generating and executing the delay test;  
         [0049]      FIG. 4  is a flowchart illustrating a conventional method of generating and executing a delay test using the equipment configuration in  FIG. 3 ;  
         [0050]      FIGS. 5A and 5B  are a flowchart illustrating a novel method of generating and executing a delay test using the equipment configuration in  FIG. 3 ; and  
         [0051]      FIG. 6  is a signal waveform diagram illustrating the novel delay test method. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0052]     An embodiment of the invention will now be described with reference to  FIGS. 1-3 ,  5 A,  5 B, and  6 . The large-scale integrated circuit  30  in this embodiment includes a pre-stage combinatorial circuit  1 A as well as the combinatorial circuit  1 B to be tested. The scan flip-flops include a pre-stage scan segment (scan chain  2 A) that launches signals into the pre-stage combinatorial circuit, an input scan segment (scan chain  2 B) that latches signals output from the pre-stage combinatorial circuit and launches signals into the combinatorial circuit under test, and an output scan segment (scan chain  2 C) that latches signals output from the combinatorial circuit under test. A predetermined transition of input signals to the combinatorial circuit under test is created by loading an input test pattern into the pre-stage scan segment and the input scan segment, waiting for the signals output by the pre-stage scan segment to propagate through the pre-stage combinatorial circuit, then applying a clock pulse that causes the input scan segment to latch the signals output by the pre-stage combinatorial circuit. These signals now begin to propagate through the combinatorial circuit under test.  
         [0053]     The test procedure is illustrated in the flowchart in  FIGS. 5A and 5B . Identical reference characters are assigned to steps in which operations similar to the conventional operations in  FIG. 4  are carried out. The test equipment configuration is as shown in  FIG. 3 .  
         [0054]     In step S 1  in  FIG. 5A , information specifying the circuit configuration of combinatorial circuits  1 A,  1 B and other combinatorial circuits in the LSI circuit under test is set in the test pattern generating device  10  (see  FIG. 3 ).  
         [0055]     In step S 2  in  FIG. 5A , the scan segments on the input and output sides of the combinatorial circuit  1 B to be tested are specified. In the present embodiment, the scan segments on the input side include the pre-stage scan chain  2 A as well as the input scan chain  2 B (see  FIG. 1 ).  
         [0056]     In step S 3  in  FIG. 5A , the test pattern generating device  10  generates the input test pattern for creating a signal transition that will propagate from the scan flip-flops in the input scan segment through combinatorial circuit  1 B to the scan flip-flops in the output scan segment (scan chain  2 C in  FIG. 1 ).  
         [0057]     In step S 4  in  FIG. 5A , the test pattern generating device  10  generates a first output test pattern expected to appear in the output scan segment after the signal transition propagates from the input scan segment to the output scan segment. These steps S 1  to S 4  are similar to the conventional test steps in  FIG. 4 .  
         [0058]     Next in step S 4 A in  FIG. 5A , the test pattern generating device  10  generates a second output test pattern expected to appear in the output scan segment  2 C before the signal transition propagates from the input scan  2 B segment to the output scan segment  2 C.  
         [0059]     In step S 5 , a clock pattern comprising a launch clock pulse and a capture clock pulse is incorporated into the input test pattern generated in step S 3  and the first output test pattern generated in step S 4  to generate first test pattern data for the delay test.  
         [0060]     In step S 5 A, a clock pattern comprising a hold clock pulse is incorporated into the input test pattern generated in step S 3  and the second output test pattern generated in step S 2  to generate second test pattern data for the delay test. The hold clock pulse will be described later.  
         [0061]     In step S 6  in  FIG. 5B , the first test pattern data generated in step S 5  are set in the scan test device  20 . In step S 7 , test signals are supplied from the scan test device  20  to the LSI circuit  30  under test to execute a first delay test.  
         [0062]     In step S 8 , the scan output signal SOC output from the circuit  30  under test is compared with the first output test pattern. If the SOC signal data do not match the first output test pattern data, the circuit fails the test and is rejected as defective. If the signal data match the first output test pattern data, the test process proceeds to the next step S 9 .  
         [0063]     In step S 9 , the second test pattern data generated in step S 5 A are set in the scan test device  20 . In step S 10 , test signals are supplied from the scan test device  20  to the LSI circuit  30  under test to execute a second delay test.  
         [0064]     In step S 11 , the scan output signal SOC output from the circuit  30  under test is compared with the second output test pattern. If the SOC signal data match the second output test pattern data, the circuit passes the test; otherwise, the circuit fails the test and is rejected as defective.  
         [0065]     The first delay test carried out in step S 7  in  FIG. 5B  is similar to the conventional delay test illustrated in  FIG. 2 . The second delay test carried out in step S 10  in  FIG. 5B  is illustrated in  FIG. 6 , again under the assumption that the combinatorial circuits  1 A and  1 B have four input signals and four output signals each. As before, the clock signal CLK supplied to the clock terminal  5  propagates as clock signal CKB to the scan flip-flops in scan chain  2 B with delay α, and as clock signal CKC to the scan flip-flops in scan chain  2 C with delay β.  
         [0066]     First, the scan enable signal SE is set to the high logic level, switching the selectors  7  of all scan flip-flops to the second input side. Scan flip-flops  2 A 1  to  2 A 4  form a shift register extending from scan input terminal  3 A to scan output terminal  4 A in  FIG. 1 , and their output signals are supplied in parallel to combinatorial circuit  1 A. Similarly, scan flip-flops  2 B 1  to  2 B 4  form a shift register extending from scan input terminal  3 B to scan output terminal  4 B and their output signals are supplied in parallel to combinatorial circuit  1 B.  
         [0067]     At time t 21  in  FIG. 6 , the scan input signals SIA and SIB supplied to scan input terminals  3 A and  3 B are set according to the predefined test data TDA and TDB, to signal levels ‘a 4 ’and ‘b 4 ’, and a clock pulse CLK is supplied to the clock terminal  5 . After propagation delays in the clock distribution circuitry, scan flip-flops  2 A 1  and  2 B 1  latch the data ‘a 4 ’and ‘b 4 ’.  
         [0068]     Next, at times t 22 , t 23  and t 24 , scan input signals SIA (‘a 3 ’, ‘a 2 ’, ‘a 1 ’) are supplied one by one from the scan input terminal  3 A and shifted into scan chain  2 A in synchronization with the clock signal CLK. Scan input signals SIB (‘b 3 ’, ‘b 2 ’, ‘b 1 ’) are supplied one by one from scan input terminal  3 B into scan chain  2 B. After the above scan shift operation, test data TDA (‘a 1 ’, ‘a 2 ’, ‘a 3 ’, ‘a 4 ’) are latched in scan flip-flops  2 A 1  to  2 A 4 , and supplied in parallel to combinatorial circuit  1 A, while test data TDB are latched in scan flip-flops  2 B 1  to  2 B 4  and supplied in parallel to combinatorial circuit  1 B. Combinatorial circuit  1 A performs logic operations on test data TDA, and after a certain delay, outputs the resultant signal data RDA in parallel as an input test pattern. In the meantime, combinatorial circuit  1 B performs logic operations on test data TDB, and after a certain delay, outputs the resultant signal data RDB 1  in parallel.  
         [0069]     At time t 25 , the scan enable signal SE at terminal  6  is driven low, switching the selectors  7  of all scan flip-flops to the first input side. The signals output from combinatorial circuit  1 A are now supplied to the input side of the flip-flops in scan chain  2 B, but the data latched in scan flip-flops  2 B 1  to  2 B 4  do not immediately change, because no clock pulse is supplied to the clock terminal  5 .  
         [0070]     At time t 26 , a hold clock pulse is supplied from the clock terminal  5 . This clock pulse reaches scan flip-flops  2 B 1  to  2 B 4  as clock signal CKB with a delay α, and reaches scan flip-flops  2 C 1  to  2 C 4  as clock signal CKC with a delay β. If delay β is less than delay α, as shown, then scan flip-flops  2 C 1  to  2 C 4  latch the signal data RDB 1  output by combinatorial circuit  1 B before it received the new input signal data RDA. Even if delay β is slightly greater than delay α, as in  FIG. 2 , scan flip-flops  2 C 1  to  2 C 4  will still latch signal data RDB 1  (‘c 1   x ’, ‘c 2   x ’, ‘c 3   x ’, ‘c 4   x ’), provided the difference between delay α and delay β is less than the shortest time required for a signal transition to propagate through combinatorial circuit  1 B. In other words, provided delay β does not too greatly exceed delay α, scan flip-flops  2 C 1  to  2 C 4  will latch signal data RDB 1  and the scan output signal SOC output from scan flip-flop  2 C 4  to scan output terminal SOC will be ‘c 4   x’.    
         [0071]     At time t 27 , the scan enable signal SE is driven high, switching the selectors  7  of all scan flip-flops to the second input side to resume scan shift operations. In due time, the logic operations carried out on signal data RDA by combinatorial circuit  1 B produce new output data RDB 2 , but the new output data RDB 2  are ignored by the selectors  7  and are not latched in scan flip-flops  2 C 1  to  2 C 4 .  
         [0072]     The remaining data captured in scan flip-flops  2 C 1  to  2 C 3  in synchronization with the hold clock pulse at time t 26  (+β) are now shifted into scan flip-flop  2 C 4  one by one in synchronization with clock signal CKC, and output serially as scan output signal SOC from scan output terminal  4 C at times t 28  to t 30  (in each case with a delay of β from the rise of clock signal CLK). The scan output signal SOC output from the scan output terminal  4 C gives the data RDB 1  output by combinatorial circuit  1 B before the before the signal transition occurred.  
         [0073]     The delay of clock signal CKB can therefore be tested by checking the scan output signal SOC following times t 26 , t 28 , t 29 , and t 30 . If the scan output signal SOC matches the values (the second output test pattern) expected to be obtained from test pattern TDB by the logic operations performed in combinatorial circuit  1 B, it can be concluded that the passing result obtained in step S 8  indicates that the propagation delay in combinatorial circuit  1 B is within tolerance, and is not due to an excessive delay β of the clock signal CKC supplied to scan chain  2 C.  
         [0074]     If, for example, the delay β of clock signal CKC is greater than the sum of delays α and D (α+D&lt;β), then the data latched by the scan flip-flops  2 C 1  to  2 C 4  in synchronization with the hold clock pulse will be the output signal RDB 2  obtained after the signal transition propagates through combinatorial circuit  1 B. Therefore, the data scanned out in step S 10  will show the results of logic operations performed on input data RDA, not matching the second output test pattern, and the LSI circuit will be rejected as defective in step S 11 .  
         [0075]     The invented test method can be described as performing both a conventional delay test with separate launch and capture clock pulses to check the propagation delay of a combinatorial circuit, and an additional test in which the launch and capture clock pulses are combined into a single hold clock pulse to check the propagation delay of the capture clock signal. This test procedure catches not only unacceptable logic propagation delays but also scan clock propagation delays that prevent the logic propagation delay from being tested accurately, thereby reducing the possibility of erroneous test results wherein a defective circuit is passed as non-defective.  
         [0076]     In conventional test methods, the detectable delay time is limited by constraints on the launch-to-capture delay T imposed by the test equipment (for example T&gt;5 ns), which may preclude testing under the condition α+D−β&lt;T. The additional test conducted with the hold clock pulse in the present invention is free of such constraints.  
         [0077]     It will be appreciated by those skilled in the art that many modifications can be made in the above embodiment. For example:  
         [0078]     (1) the data launched into the combinatorial circuit under test may be input in parallel from external input terminals, instead of being scanned in; this modification is necessary when the combinatorial circuit under test is the first stage and there is no pre-stage combinatorial circuit on its input side;  
         [0000]     (2) the LSI circuit may have a single scan chain, different segments of which function as the three scan chains shown in  FIG. 1 ;  
         [0000]     (3) the test equipment, including the scan test device and test pattern generating device, need not be configured as shown in  FIG. 3 ;  
         [0079]     (4) the order of steps in  FIGS. 5A and 5B  is not limited to the illustrated order. Any order can be used as long as the LSI circuit is passed as normal only if it passes tests using both the first and second test patterns. For example, steps S 9 -S 11  can be carried out before steps S 6 -S 8 , the test in steps S 6 -S 8  being conducted only if the test in steps S 9 -S 11  passes.  
         [0080]     Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.