Abstract:
A rate locked loop (RLL) regulates phase slip between two clock signals to provide precision timing for radar, TDR and laser ranging systems. Two clocks having a small mutual frequency offset exhibit a slowing changing relative phase, or phase slip, that produces a stroboscopic time expansion effect in a ranging system. A phase detector converts clock phase to voltage and the voltage is differentiated to provide a rate-of-change signal to a loop controller that precisely regulates the rate-of-phase change. The RLL controls a VCO to produce a constant, linear phase slip having phase errors below the time equivalent of 1-picosecond.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of the Invention  
         [0002]     The present invention relates to radar timing circuits, and more particularly to precision swept delay circuits for expanded time ranging systems. It can be used to generate a swept-delay dock for sampling radar, time domain reflectometry (TDR) and laser systems.  
         [0003]     2. Description of Related Art  
         [0004]     High accuracy pulse-echo ranging systems, such as wideband and ultra-wideband pulsed radar, pulsed laser rangefinders, and time domain reflectometers, sweep a timing circuit across a range of delays. The timing circuit controls a receiver sampling gate such that when an echo signal coincides with the temporal location of the sampling gate, a sampled echo signal is obtained. The echo range is then determined from the timing circuit, so high timing accuracy is essential. A beneficial feature for high accuracy is time expansion, whereby the receiver sampling rate is set to a slightly lower rate than the transmit pulse rate to create a stroboscopic time expansion effect that expands the apparent output time by a large factor, such as 100,000. Expanded time allows vastly more accurate signal processing than possible with realtime systems.  
         [0005]     A common approach to generate accurate swept timing employs two oscillators with frequencies F T  (e.g., a transmit clock frequency) and F R  (e.g., a receive clock frequency) that are offset by a small amount F T −F R =Δ. In a ranging application, a transmit dock at frequency F T  triggers transmit pulses, and a receive dock at frequency F R  gates the echo pulses. If the receive dock is lower in frequency than the transmit clock by a small amount A, the phase of the receive clock can smoothly and linearly slip relative to the transmit clock such that one full cycle is slipped every 1/Δ seconds. Typical parameters are: transmit clock F T =2 MHz, receive dock F R =1.99999 MHz, offset frequency Δ=10 Hz, phase slip period=1/Δ=100 milliseconds, and a time expansion factor of F T /Δ=200,000. This two-oscillator technique was used in the 1960&#39;s in precision time-interval counters with sub-nanosecond resolution, and appeared in a short-range radar in U.S. Pat. No. 4,132,991, “Method and Apparatus Utilizing Time-Expanded Pulse Sequences for Distance Measurement in a Radar,” by Wocher et al.  
         [0006]     The accuracy of the two-oscillator technique is limited by the differential and integral linearity of the phase slip between the two oscillators. The accuracy of the phase slip is not easy to measure accurately and it is also easy to assume it is somehow perfect. Commercial pulse echo radar rangefinders having a claimed accuracy in the millimeter range require error correction look-up tables, which indicates that high accuracy timing systems do not presently exist.  
         [0007]     There are many influences that can affect the smoothness of the phase slip, including: (1) oscillator noise due to thermal and flicker effects, (2) transmit-to-receive clock cross-talk, and (3) thermal transients that typically do not track out between the two oscillators. The receive oscillator is typically locked to the offset frequency by a phase locked loop (PLL) circuit, which does a reasonable job when the offset frequency is above several hundred Hertz. Unfortunately, precision long range systems require extremely high accuracy, on the order of picoseconds, at offset frequencies on the order of 10 Hz. A PLL system cannot meet this requirement for the simple reason that the PLL loop response must be slower than 1/Δ, or typically slower than 100 ms, which is far too slow to control short term phase errors between the two clocks.  
         [0008]     U.S. Pat. No. 6,404,288 to Bletz et al addresses the problems associated with controlling low offset frequencies by introducing three additional oscillators into a system that can include, for example, seven counters and two phase comparators, all to permit PLL control at higher offset frequencies than the final output offset frequency, which is obtained by frequency down-mixing. This system is too complex for many commercial applications and it does not control instantaneous voltage controlled oscillator (VCO) phase errors and crosstalk.  
         [0009]     A need exists for a compact low cost method and precision timing system that instantaneously controls phase slip errors to produce extremely smooth and accurate phase slip rates. The present invention is directed to such a need.  
       SUMMARY OF THE INVENTION  
       [0010]     The present invention provides a rate locked loop (RLL) arrangement to provide timing for a pulse-echo rangefinder that can include, but is not necessarily limited to, a phase detector responsive to phase between first and second clock signals for producing an output proportional to phase, a differentiator to produce a derivative signal and a controller responsive to the derivative signal for producing a feedback signal to the phase control.  
         [0011]     Another aspect of the present invention provides a method for generating clock signals having a relative phase slip that includes: generating a first clock frequency, generating a second clock frequency, detecting the phase between the first and second clock frequencies to produce a phase signal, differentiating the phase signal to produce a derivative signal; and controlling the second clock phase using the derivative signal to produce a controlled phase slip.  
         [0012]     A final aspect of the present invention provides for a radar, laser or time domain reflectometry (TDR) system that can include, but is not limited to: a transmitter triggered by a first clock signal, a receiver gated by a second clock signal, a phase detector responsive to phase between the first and second clock signals for producing a phase signal, a differentiator for producing a derivative signal from the phase signal, a phase control for adjusting the phase of the second clock signal; and a controller responsive to the derivative signal for producing a feedback control signal to the phase control.  
         [0013]     The present invention can be used in expanded time radar, laser, and TDR ranging systems having picosecond accuracy. Applications include pulse echo rangefinders for tank level measurement, environmental monitoring, industrial and robotic controls, digital handwriting capture, imaging radars, vehicle backup and collision warning radars, and universal object/obstacle detection and ranging. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]      FIG. 1  is a rate locked loop of the present invention.  
         [0015]      FIG. 2   a  depicts a two oscillator frequency source.  
         [0016]      FIG. 2   b  depicts a single oscillator frequency source including a phase adjuster.  
         [0017]      FIG. 2   c  is a phase adjuster.  
         [0018]      FIG. 3   a  is a phase comparator.  
         [0019]      FIG. 3   b  is a phase comparator for harmonically related clocks.  
         [0020]      FIG. 4   a  is a derivative circuit and a controller.  
         [0021]      FIG. 4   b  is a derivative circuit including a reset switch and a controller.  
         [0022]      FIG. 5  is a laboratory derived error plot for the RLL of  FIG. 1 .  
         [0023]      FIG. 6  depicts the present invention in a ranging system. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0024]     A detailed description of the present invention is provided below with reference to the figures. While illustrative component values and circuit parameters are given, other embodiments can be constructed with other component values and circuit parameters. All U.S. patents and copending U.S. applications cited herein are herein incorporated by reference in their entirety.  
         [0000]     General Description  
         [0025]     The present invention overcomes the bandwidth limitations of a PLL controller by directly controlling the phase slip rate on a continuous and instantaneous basis. A beneficial example embodiment, as disclosed herein, employs a phase detector coupled directly between two oscillators, rather than through counter chains that are customary in PLL circuits, to produce a voltage proportional to instantaneous phase. When the phase between the oscillators slips at a constant rate, because of the offset frequency, the phase detector output is a linear voltage ramp that increases for increasing phase values between 0 and 2π and then it resets to 0 at 2π, i.e., at the phase wrap point. The voltage ramp repeats at the offset frequency Δ. The voltage ramp is differentiated by a derivative circuit to produce a constant voltage proportional to the slope of the ramp, which can be termed the derivative voltage. The derivative voltage is applied to a feedback controller that controls the phase and frequency of one of the oscillators to maintain a constant phase slip rate. If the phase slip rate or smoothness varies, the gain of the feedback controller, often a high gain feedback controller, instantaneously corrects any deviations from a perfectly linear phase slip.  
         [0026]     The derivative circuit in the feedback loop controls the rate of phase change rather than the phase itself. Consequently, such a loop can be termed a rate locked loop, or RLL. Compared to a PLL system, the loop bandwidth of an RLL can be orders of magnitude higher. Therefore, high accuracy swept timing can be realized at very low offset frequencies. For example, offset frequencies as low as about 1/100 Hz have been realized with, for example, 10 MHz oscillators using the present invention, with an associated time expansion factor of 1-billion.  
         [0027]     A single oscillator implementation of the RLL can also be realized by substituting a phase adjuster circuit for the second oscillator. The loop controller sweeps the phase produced by the phase adjuster to produce a swept-phase receive clock. Ranging systems generally require swept phase over ¼ π or less since the remaining ¾ π is needed for echoes to settle before the next transmit pulse. Consequently, the phase adjuster of the present invention is often designed to, but not limited to, slip phase over a limited range before being reset from a selected maximum phase to zero.  
         [0000]     Specific Description  
         [0028]     Turning now to the drawings,  FIG. 1  shows a block diagram illustrating a general configuration of an RLL timing system  10  of the present invention. A frequency source  12  provides two clock signals, CLK 1  and CLK 2 . Phase detector  14  compares the phase between CLK 1  and CLK 2  and outputs a voltage V(φ) that is proportional to the CLK 1 -CLK 2  phase. A differentiator  16  differentiates V(φ) to produce a derivative voltage V′(φ) proportional to the rate-of-change in phase between CLK 1  and CLK 2 . Voltage V′(φ) is constant when V(φ) changes at a linear rate, representing a constant phase slip. Controller  20  compares V′(φ) to a reference voltage Vref and produces a control voltage Vc proportional to V′(φ)−Vref. Voltage Vc is applied to a phase control port of frequency source  12 , which controls the phase of CLK 2  relative to CLK 1 .  
         [0029]     Blocks  12 ,  14 ,  16 , and  20 , as shown in  FIG. 1 , are often arranged to form a high gain, high bandwidth continuous-mode feedback loop. Since the loop contains phase detector  14  and a derivative element  16 , it controls a phase derivative, or rate-of-change in phase and locks the rate-of-change to a reference voltage Vref. Accordingly, the loop is a rate locked loop. For a constant Vref, the rate-of-change in phase is constant. If Vref is modulated, then the phase rate will be modulated, as may be desired in certain applications, such as nonlinear sweeps or spread spectrum applications.  
         [0030]      FIG. 2   a  depicts a frequency source  12  having an independent reference oscillator  30 , which is often a quartz crystal oscillator that may be temperature compensated (TCXO) or ovenized for greater stability. Oscillator  30  operates at a frequency of Fref. A frequency and phase controllable VCO  32  provides CLK 2 , which operates at a small offset frequency from Fref. Voltage Vc on control line  22  adjusts the VCO frequency and phase. Large changes in Vc change the VCO frequency while small changes in Vc change the instantaneous phase. For clarity, it should be noted that frequency a) is the rate of change in phase φ as can be seen from the expression for phase, φ=ωt, or ω=φ/t.  
         [0031]     In addition, VCO  32  is often, but not limited to, a quartz crystal oscillator with a varactor phase/frequency control element. The bandwidth of the crystal limits the RLL loop control bandwidth and corresponding response time to about 2 ms, about 100 times faster than a PLL system operating at 10 Hz. The benefits of an RLL are even more pronounced when the offset frequency is lower than about 10 Hz, as may be the case in long range systems.  
         [0032]      FIG. 2   b  depicts another exemplary beneficial embodiment having a frequency source  12  based on a single oscillator  30 , which directly provides CLK 1 . CLK 2 , in such an arrangement, is provided by a phase adjuster  34  coupled to the CLK 1  line. The phase adjuster controls the phase of CLK 2  in response to control voltage Vc on control line  22 . In order to provide a continuously swept CLK 2  phase, control voltage Vc on line  22  changes in response to loop controller  20 , as shown in  FIG. 1 , to produce an accurate and smooth phase slip. However, the maximum phase range introduced by the phase adjust element (i.e., phase adjuster  34 ) is normally limited to less than ½ π. Larger phase ranges are possible by cascading phase adjust element  34  or by employing other phase or time delay circuits known in the art.  
         [0033]      FIG. 2   c  is an exemplary phase adjuster circuit that includes an RC network  36 , generally coupled to a threshold element  38 , a logic gate in this example. RC network  36  slows the CLK 1  risetime, and voltage Vc on line  22  provides an offset voltage that is applied to the input of gate  38 . The exact time that gate  38  thresholds on its input is a function of its input offset voltage. Therefore the timing, i.e. the phase, of dock CLK 2  is controlled by Vc.  
         [0034]      FIG. 3   a  is an exemplary phase detector  14 , as shown in  FIG. 1 , based on a D-input latch  40 . Latch  40  is cleared by CLK 1  via edge coupling network  42 . After clearing, the next CLK 2  edge sets latch  40  so that the duty cycle of the Q output is proportional to the phase between CLK 1  and CLK 2 . Low pass filter  44  averages the duty cycle into a voltage V(φ) proportional to phase.  
         [0035]      FIG. 3   b  depicts a further example of a phase detector wherein the CLK 1  signal is frequency divided by an integer N in counter  46 , such that V(φ) is proportional to the phase between a sub-multiple of the CLK 1  frequency and the direct frequency of CLK 2 . Counter  46  output is CLK 1 ′ at a sub-multiple N of CLK 1 . When the CLK 1 ′ is at a logic 1, latch  40  remains cleared, and when CLK 1 ′ is at logic 0, the next trigger edge of CLK 2  sets Q high. Since CLK 2  occurs at a higher rate than CLK 1 ′, the Q output, which is also CLK 2 , ranges over less than 2π. For N=4, the phase range is ¼ π, a desirable range for many ranging systems. Further details on this harmonic mode can be found in U.S. Pat. No. 6,072,427, “PRECISION RADAR TIMEBASE USING HARMONICALLY RELATED OFFSET OSCILLATORS,” by Thomas E. McEwan, the applicant of the present invention.  
         [0036]      FIG. 4   a  is an implementation of differentiator  16  and controller  20 , as shown in  FIG. 1 . Phase detector  14  output V(φ) is applied to differentiation capacitor  50 , also labeled d/dt, which is coupled to the input of a transimpedance amplifier that can include op amp  52  and feedback resistor  54 , forming, in combination with capacitor  50 , a classic differentiator. Diode  56  conducts during the phase wrap transition, i.e., during the fast negative edges seen in waveform  68 , (i.e., the waveform of V(φ) as illustrated in  FIG. 4   b .) and acts to speed settling to the next ramp of V(φ). Three sample-hold (S/H) switches  62  are normally closed. Control op amp  58  compares derivative voltage V′(φ) from the differentiator to reference voltage Vref and greatly amplifies the V′(φ)−Vref difference to provide a feedback control voltage Vc on line  22  to the phase control of frequency source  12 . Capacitor  60  and resistor  64  define the control loop bandwidth. Hold capacitors  63   a ,  63   b  charge to V′(φ) and Vc, respectively. Bandwidth limiting resistors  61   a ,  61   b  assure the voltages on capacitors  63   a ,  63   b  represent a smoothed value and not an instantaneous noise peak. S/H switches  62  are opened by a pulse applied to the dashed S/H control line of  FIG. 4   b  shortly before the phase wrap to hold voltage Vc on control line  22  and block large V′(φ) glitches from coupling onto line  22  and to the VCO or phase control. Switches  62  close shortly after the phase wrap. The S/H control pulse can be derived from V(φ). Phase wrap glitches can limit the timing accuracy. Exemplary op amps  52 ,  58  are Texas Instruments, Inc. TLV274 and S/H switches  62  are Motorola, Inc. CMOS analog switches 74HC4066.  
         [0037]      FIG. 4   b  is another implementation of differentiator  16  and controller  20 , as shown in  FIG. 1  that is suited for use with a single oscillator frequency source (e.g., source  12  as described with reference to  FIG. 2   b ). When using a single frequency source and a phase adjuster circuit, phase wraps can be set at an arbitrary point, rather than occurring at 2π or an exact fraction of 2π. When phase ramp voltage V(φ) exceeds a reset threshold inside reset element  65 , a reset pulse is applied to FET  66  via line  69  to force V′(f) to 0, which then forces control op amp  58  to swing to a minimum, which in turn sets phase adjuster  34 , as shown in  FIG. 2   b , to a minimum. When the reset pulse ends, control op amp  58  equilibrates back to a sweep mode wherein the phase adjuster  34  sweeps the CLK 2  phase at a constant rate-of-change, producing another V(φ) voltage ramp. The period of voltage ramp  68  is set by capacitor  50 , resistor  54  and Vref in relation to the amplitude of ramp  68 . These analog values do not yield extremely high accuracy, but an accuracy of 0.1% of full scale range is practical. Again, similar to the embodiment as shown in  FIG. 4   a , feedback control voltage Vc is provided on line  22  for the phase control of frequency source  12 , as shown in  FIG. 1 , and capacitor  60  and resistor  64  define the control loop bandwidth.  
         [0038]     The sweep rate produced by the circuit of  FIG. 4   a  also depends on analog values and is not particularly accurate. The period of the expanded time sweep is generally accurate to only a few percent. However, the expanded time sweep period corresponds to the realtime sweep period of CLK 2 , which is locked to the reference oscillator. To obtain a precision measurement, the expanded time range reading must be set as a ratio against the expanded time period. This ratio divides out the period inaccuracies. Expanded time range PWM (pulse width modulation) is measured to obtain the best precision. Alternatively, the sweep period can be phase locked to a precision reference, e.g., a 10 Hz clock, to make the sweep period precise. The expanded time range reading can then be measured to obtain a precision measurement without recourse to measuring the sweep period.  
         [0039]      FIG. 5  is a plot of the phase error between CLK 1 ′ and CLK 2 ′ for an actual implementation of  FIG. 1  using harmonically related clocks and the phase comparator of  FIG. 3   b . Errors are indicated in the temporal equivalent of 5 picoseconds per division across a sweep range of 154 ns. CLK 1 ′ is operated at 1.625 MHz and CLK 2  at 6.5 MHz in a harmonic system as described with reference to  FIG. 3   b . Hence the sweep range is 1/6.5 MHz=154 ns, which corresponds to a phase range of ¼ π. The plot indicates phase wrap errors  70  that lie outside the effective timing range. Range marker  72  corresponds to zero range and the range marker  74  is the maximum range for a rangefinder implementation. Errors between markers  72 ,  74  are on the order of 1-picosecond, or less than 0.001% of full scale range.  
         [0040]      FIG. 6  illustrates a general pulse-echo rangefinder  100  incorporating timing system  10 , as shown in  FIG. 1 , of the present invention. Frequency source  12  provides CLK 1  and CLK 2  signals to transmitter  90  and receiver  92 . CLK 1  triggers transmit pulses and transmitter  90  radiates corresponding radio or optical transmit pulses. Alternatively, transmitter  90  transmits electrical pulses along a conductor in a time domain reflectometer. Receiver  92  receives echo pulses produced by the transmitter. CLK 2  gates the receiver, causing it to sample echoes at the instant of gating. Samples are output from the receiver on line  94  in expanded time as the phase of CLK 2  slips relative to CLK 1 . The samples on line  94  may occur on a pulse-by-pulse basis, one for each pulse of CLK 2 , or the samples may be integrated to form an integrated output representing many CLK 2  cycles. Receiver  92  may further include processing as known in the art, in which case the output on line  94  represents a processed output arising from samples taken at timing instants defined by CLK 2 .  
         [0041]     Phase ramp voltage V(φ) can be optionally coupled to receiver  92  via line  93  to control a variable gain amplifier to compensate echo versus range loss. Other uses for phase ramp voltage V(O) include detecting the phase wraps at 2π for generating reset pulses, generating sample-hold control pulses for controller  20 , or for providing an analog indication of range. Blocks  12 ,  14 ,  16  and  20  form an RLL, which provides precision timing for rangefinder system  100 . Transmitter  90  and receiver  92  may be fashioned to operate with a single radiator or lens, or in the case of TDR, may be coupled onto a single conductor, as known in the art.  
         [0042]     Changes and modifications in the specifically described embodiments can be carried out without departing from the scope of the invention which is intended to be limited only by the scope of the appended claims.