Abstract:
A solid state imaging device includes: a plurality of photoelectric conversion elements which are arranged in a two-dimensional matrix on a semiconductor chip; vertical transfer registers including a vertical transfer channel and vertical transfer electrodes, respectively, for transferring signal charge read out of the photoelectric conversion elements in the vertical direction; a horizontal transfer register including a horizontal transfer channel and horizontal transfer electrodes for transferring the signal charge transferred from the vertical transfer registers in the horizontal direction; bus interconnects which are electrically connected to the vertical transfer electrodes and the horizontal transfer electrodes; and pads for external connection which are electrically connected to the bus interconnects. The pads are formed above the bus interconnects and the horizontal transfer electrodes.

Description:
CROSS-REFERENCE TO RELATED APPLICATION  
       [0001]     This non-provisional application claims priority under 35 U.S.C. § 119(a) of Japanese Patent Application No. 2005-128455 filed in Japan on Apr. 26, 2005, the entire contents of which are hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a solid state imaging device. In particular, it relates to a solid state imaging device which makes it possible to increase the number of pixels and the packaging density without increasing the chip size.  
         [0004]     2. Description of Related Art  
         [0005]     Hereinafter, an explanation of a conventional solid state imaging device will be provided with reference to the drawing (see Japanese Unexamined Patent Publication No. 2004-207804).  FIG. 10  shows a plane structure of a solid state imaging device using a common charge-coupled device (CCD).  
         [0006]     The solid state imaging device includes a plurality of pixels (sensor)  111  formed in a matrix on a semiconductor chip  101  and vertical transfer registers  112  extending in the column direction between the sensors  111  adjacent to each other. A horizontal transfer register  113  is arranged in the direction orthogonal to the vertical transfer registers  112  at the end of the vertical transfer registers  112 .  
         [0007]     At the periphery of a device region  102  of the semiconductor chip  101  in which the pixels  111 , vertical transfer registers  112  and horizontal transfer register  113  have been formed, an output buffer  114  is provided and connected to the end of the horizontal transfer register  113  to transfer signal charge received from the horizontal transfer register  113  into a voltage signal for output.  
         [0008]     Further, interconnects for supplying a drive signal to the vertical transfer registers  112  and the horizontal transfer register  113  are provided in an interconnect region  103  and a plurality of pads  115  for external connection are provided in a pad region  104  outside the interconnect region  103 .  
         [0009]     In  FIG. 10 , only a few pixels  111 , vertical transfer registers  112  and pads  115  are shown for simplification. The number of the horizontal transfer register  113  is not limited to one. In some cases, a plurality of horizontal transfer registers  113  may be formed.  
         [0010]     Next, with reference to the drawing, an explanation of the structure of a common bonding pad aimed at the reduction of chip size (see Japanese Unexamined Patent Publication No. S57-87145).  
         [0011]      FIG. 11  is a sectional view illustrating the structure of a conventional semiconductor device. As shown in  FIG. 11 , a drain region  121  and a source region  122  made of an impurity diffusion layer are formed in the surface of a semiconductor chip  120  to be spaced from each other and a gate electrode  123  is formed between the drain region  121  and the source region  122  to provide a transistor. Electrode wires  124  and  125  are connected to the drain region  121  and the source region  122 , respectively. The gate electrode  123  and the electrode wires  124  and  125  are covered with an interlayer insulating film  126  and a pad  127  for external connection is formed on the interlayer insulating film  126  to overlap the transistor.  
         [0012]     As the device region and the pad region vertically overlap, the ratio of the device region to the chip area increases, thereby increasing the packing density of the chip.  
         [0013]     In electronic industry, there is a great demand for devices with reduced size and higher performance. In the field of semiconductors, what is required is an increase in packing density of the chip, i.e., reduction in chip size with the performance unchanged and improvement in performance with the chip size unchanged.  
         [0014]     From this aspect, in a semiconductor device including a solid state imaging device, components of the device such as impurity diffusion regions, transfer electrodes and interconnects have been miniaturized in order to reduce the chip size and improve the performance with the chip size unchanged.  
         [0015]     However, the miniaturization of the impurity diffusion regions and the interconnects leads to deterioration in characteristic of the transistor. In addition, new facilities and new processes must be introduced and the cost increases. If the impurity diffusion regions serving as the pixels of the solid state imaging device are reduced in size, the amount of incident light decreases. As a result, the solid state imaging device deteriorates in sensitivity, saturation characteristic and S/N characteristic, which are important characteristics of the solid state imaging device.  
         [0016]     The size of a semiconductor chip depends on the size of the device region in which active elements and passive elements are formed and the size of the pad region provided at the periphery of the device region in which bonding pads for wire bonding are formed. Therefore, in order to achieve both of the reduction of the chip size and the increase of the number of the pixels, it is effective to increase the ratio of the device region to the chip area, i.e., to make the pad region small.  
         [0017]     However, if the pad structure as disclosed by Japanese Unexamined Patent Publication No. S57-87145 is applied to the conventional solid state imaging device of Japanese Unexamined Patent Publication No. 2004-207804, light incident on the pixels is cut off by the pads. As a result, the sensitivity and the saturation characteristic which are important for the solid state imaging device deteriorate.  
       SUMMARY OF THE INVENTION  
       [0018]     In order to solve the above-described conventional problems, the present invention intends to increase the ratio of the device region in which the pixels are formed to the chip area without hindering the entrance of light into the pixels, thereby achieving a solid state imaging device with high packing density.  
         [0019]     In order to achieve the above-described object, in the solid state imaging device according to the present invention, pads for external connection are formed in a interconnect region.  
         [0020]     Specifically, the solid state imaging device according to the present invention includes: a plurality of photoelectric conversion elements which are arranged in a two-dimensional matrix on a semiconductor chip; vertical transfer registers including a vertical transfer channel and vertical transfer electrodes, respectively, for transferring signal charge read out of the photoelectric conversion elements in the vertical direction; a horizontal transfer register including a horizontal transfer channel and horizontal transfer electrodes for transferring the signal charge transferred from the vertical transfer registers in the horizontal direction; bus interconnects which are electrically connected to the vertical transfer electrodes and the horizontal transfer electrodes; and pads for external connection which are electrically connected to the bus interconnects, wherein the pads are formed above the bus interconnects and the horizontal transfer electrodes.  
         [0021]     According to the solid state imaging device of the present invention, a region for forming the pads for external connection and a region for interconnection are integrated. As a result, the ratio of the device region to the solid state imaging device increases. Further, since the region for forming the pads is completely separated from a region for forming the pixels, the pads will not hinder the entrance of light into the pixels.  
         [0022]     As to the solid state imaging device of the present invention, the pads are preferably located above the horizontal transfer channel. According to the structure, the ratio of the area occupied by the pads is reduced to a further degree and the pads function as a light shield film. Therefore, the efficiency of horizontal charge transfer improves.  
         [0023]     In this case, it is preferable that the horizontal transfer electrodes are conductive layers and the pads are metal layers. Further, the conductive layers are preferably made of polysilicon. According to the structure, light entering the horizontal transfer channel is effectively blocked by the pads.  
         [0024]     As to the solid state imaging device of the present invention, the pads are preferably inclined from the main surface of the semiconductor chip. According to the structure, a mounting angle at which bonding wires are connected to the pads is reduced, thereby preventing the bonding wires from blocking the light incident on the pixels.  
         [0025]     As to the solid state imaging device of the present invention, the pads are preferably electrically connected to the bus interconnects via contact plugs. According to the structure, the connection between the pads and the bus interconnects is simplified, thereby reducing the chip size to a further degree.  
         [0026]     As to the solid state imaging device of the present invention, it is preferable that the photoelectric conversion elements, vertical transfer registers and horizontal transfer register provide a CCD image sensor. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0027]      FIG. 1  is a plan view illustrating a solid state imaging device according to a first embodiment of the present invention.  
         [0028]      FIG. 2  is a plan view illustrating an enlargement of a major part of the solid state imaging device according to the first embodiment of the present invention.  
         [0029]      FIG. 3  is a sectional view illustrating an enlargement of a major part of the solid state imaging device according to the first embodiment of the present invention.  
         [0030]      FIG. 4  is a plan view illustrating a solid state imaging device according to a second embodiment of the present invention.  
         [0031]      FIG. 5  is a plan view illustrating an enlargement of a major part of the solid state imaging device according to the second embodiment of the present invention.  
         [0032]      FIG. 6 a  sectional view illustrating an enlargement of a major part of the solid state imaging device according to the second embodiment of the present invention.  
         [0033]      FIG. 7  is a plan view illustrating a solid state imaging device according to a third embodiment of the present invention.  
         [0034]      FIG. 8  is a plan view illustrating an enlargement of a major part of the solid state imaging device according to the third embodiment of the present invention.  
         [0035]      FIG. 9 a  sectional view illustrating an enlargement of a major part of the solid state imaging device according to the third embodiment of the present invention.  
         [0036]      FIG. 10  is a plan view illustrating a conventional solid state imaging device.  
         [0037]      FIG. 11  is a sectional view illustrating a conventional semiconductor device in which a pad is formed over the device region. 
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
     First Embodiment  
       [0038]     With reference to the drawings, an explanation of a solid state imaging device of the first embodiment of the present invention will be provided. FIGS.  1  to  3  show the solid state imaging device of the first embodiment. Specifically,  FIG. 1  shows a plane structure,  FIG. 2  is an enlargement of  FIG. 1  and  FIG. 3  shows a section taken along the line IIIa-IIIa of  FIG. 2 .  
         [0039]     As shown in FIGS.  1  to  3 , a plurality of pixels  11  are arranged in a matrix in a pixel region  2 A of a semiconductor chip  1 . The pixels  11  are photodiodes and generate signal charge corresponding to the intensity of light incident thereon.  
         [0040]     Vertical transfer registers  12  extending in the column direction are arranged between the pixels  11  adjacent to each other. Each of the vertical transfer registers  12  includes a vertical transfer channel  20  which is an impurity diffusion layer formed in the surface of the semiconductor chip  1  and extends in the column direction and a plurality of vertical transfer electrodes  21  which are conductive layers made of polysilicon and arranged on every line on the vertical transfer channel  20 .  
         [0041]     When a vertical transfer clock pulse is applied to the vertical transfer electrodes  21 , signal charge generated in the pixels  11  is sequentially transferred in the column direction and output to a horizontal transfer register  13  connected to the ends of the vertical transfer registers  12 . The vertical transfer electrodes  21  of the vertical transfer registers  12  on the same line are integrated to be shared among the vertical transfer registers  12 . The vertical transfer registers  12  are driven at the same time.  
         [0042]     A horizontal transfer register  13  is formed in a horizontal transfer register region  2 B adjacent to the pixel region  2 A. The horizontal transfer register  13  extends in the line direction and is connected to the ends of the vertical transfer registers  12 . The horizontal transfer register  13  includes a horizontal transfer channel  23  which is an impurity diffusion layer extending in the line direction and connected to the ends of the vertical transfer channels  20  and a plurality of horizontal transfer electrodes  24  which are conductive layers made of polysilicon and formed on the horizontal transfer channel  23 .  
         [0043]     When a horizontal transfer clock pulse is applied to the horizontal transfer electrodes  24 , signal charge transferred from the vertical transfer registers  12  is sequentially transferred in the line direction and output to an output buffer  14 .  
         [0044]     A plurality of bus interconnects  28  for supplying the vertical transfer electrodes  21  and the horizontal transfer electrodes  24  with the transfer clock pulses are formed in a interconnect region  3  provided around a device region  2  in which the pixels  11 , vertical transfer registers  12  and horizontal transfer register  13  have been formed.  
         [0045]     The number of the bus interconnects  28  varies depending on how to drive the device. For example, 4 to 6 bus interconnects  28  are required in a common solid state imaging device having supply voltage bus lines in which the vertical transfer registers  12  are driven by a four-phase clock and the horizontal transfer register  13  is driven by a two-phase clock. The number of the vertical transfer registers increases to about 10 to 14 as the number of the pixels increases.  FIGS. 2 and 3  show only two bus interconnects  28  connected to the horizontal transfer electrodes  24 .  
         [0046]     The bus interconnects  28  are metal layers made of aluminum or copper and buried in an interlayer insulating film  30  formed on the semiconductor chip  1 . In the interconnect region  3 , a plurality of pads  31  for external connection are formed on the top surface of the interlayer insulating film  30  to overlap with the bus interconnects  28 . The pads  31  are metal layers made of aluminum, copper, gold or platinum.  
         [0047]     The size of the chip for the solid state imaging device depends on the areas of the device region  2 , interconnect region  3  and pad region. If the pads  31  are formed over the bus interconnects  28  formed in the interconnect region  3 , there is no need of providing the pad region separately. Therefore, the chip size may be reduced. Further, as the ratio of the device region  2  to the chip area increases, the packing density of the solid state imaging device increases.  
         [0048]     Further, since the pads  31  are not formed in the pixel region  2 A, the pads  31  will not hinder the entrance of light into the pixels  11 .  
         [0049]     Moreover, the pads  31  and the bus interconnects  28  may be connected through via plugs  32 . By so doing, interconnects for connecting the pads  31  and the bus interconnects  28  are omitted.  
         [0050]     If an impurity diffusion region is formed below the pads  31 , the impurity diffusion layer may deteriorate in characteristic due to an impact exerted thereon when the pads  31  are formed and a mechanical impact for bonding wires to the pads  31 .  
         [0051]     In the case of a CCD, in particular, the signal charge, which is image information, is transferred through the vertical transfer channels and the horizontal transfer channel which are the impurity diffusion regions. Therefore, the characteristic of the impurity diffusion regions has a significant effect on the image property.  
         [0052]     In contrast, according to the solid state imaging device of the present embodiment, the pads  31  are formed in the interconnect region  3  established around the device region  2 . Since the impurity diffusion region does not exist below the pads  31 , the horizontal transfer channel, which is the impurity diffusion region, will not be damaged during the manufacture of the pads  31 . Thus, in the solid state imaging device of the present embodiment, the chip is reduced in size without causing any problem in horizontal charge transfer.  
         [0053]     More specifically, as to an imaging device of about 5 mm on a side which is often used in digital cameras, about 30 pads of about 100 μm on a side are formed in general.  
         [0054]     In this case, in a conventional solid state imaging device, a region ranging about 0.3 mm from the periphery of the chip is required for the pad region and the interconnect region. Therefore, the device region actually occupies about 75% of the chip area.  
         [0055]     In the solid state imaging device of the present embodiment, however, about 90% of the chip area is used as the device region because the pads for external connection are formed in the interconnect region. Thus, the solid state imaging device of the present embodiment makes it possible to increase the number of the pixels without increasing the chip size. If the number of the pixels is unchanged, the chip size is reduced.  
       Second Embodiment  
       [0056]     Hereinafter, an explanation of a solid state imaging device according to a second embodiment of the present invention will be provided with reference to the drawings. FIGS.  4  to  6  show the solid state imaging device according to the second embodiment. Specifically,  FIG. 4  shows a plane structure,  FIG. 5  is an enlargement of  FIG. 4  and  FIG. 6  shows a section taken along the line VIa-VIa of  FIG. 5 . In FIGS.  4  to  6 , the same components as those shown in FIGS.  1  to  3  are indicated by the same reference numerals to omit the explanation.  
         [0057]     In the solid state imaging device of the present embodiment, the pads  31  for external connection are formed to overlap with the interconnect region  3  and the horizontal transfer register region  2 B. Specifically, part of each pad  31  is located above the horizontal transfer channel  23 .  
         [0058]     The metal layer for forming the pads  31  made of aluminum, copper, gold or platinum surely blocks light as compared with the conductive layer for forming the horizontal transfer electrodes  24  made of polysilicon. Therefore, the pads  31  function as a light shield film for blocking the light incident on the horizontal transfer channel  23 . Thus, the solid state imaging device of the present embodiment makes it possible to reduce the chip size and improve the efficiency of signal charge transfer in the horizontal direction.  
         [0059]     As the pads  31  for external connection are formed above the horizontal transfer channel  23  which is an impurity diffusion region, it is presumed that damage may be caused on the impurity diffusion region. However, if the interlayer insulating film  30  is thickened or made of different material, the impurity diffusion region may be protected from the damage.  
       Third Embodiment  
       [0060]     Hereinafter, an explanation of a solid state imaging device according to a third embodiment of the present invention will be provided with reference to the drawings. FIGS.  7  to  9  show the solid state imaging device according to the third embodiment. Specifically,  FIG. 7  shows a plane structure,  FIG. 8  is an enlargement of  FIG. 7  and  FIG. 9  shows a section taken along the line IXa-IXa of  FIG. 8 . In FIGS.  7  to  9 , the same components as those shown in FIGS.  1  to  3  are indicated by the same reference numerals to omit the explanation.  
         [0061]     In the solid state imaging device of the present embodiment, part of the interlayer insulating film  30  in the interconnect region  3  is gradually reduced in thickness toward the periphery of the chip to have an inclined surface and the pads  31  for external connection are formed on the inclined surface.  
         [0062]     In order to obtain the inclined surface, a resist mask is formed to cover other part of the interlayer insulating film  30  than the part for giving the inclined surface and the interlayer insulating film  30  is subjected to etching.  
         [0063]     If the pads  31  are formed above the interconnect region  3 , the distance between the pads  31  and the pixel region  2 A is reduced. Therefore, bonding wires  33  connected to the pads  31  may possibly hinder the light from entering the pixels  11 .  
         [0064]     However, in the solid state imaging device of the present invention, the angle θ formed by the bonding wire  33  and the top surface of the semiconductor chip  1  (mounting angle) is reduced. Therefore, light around the pixels  11  is prevented from reflecting on the bonding wires  33  to enter the pixels  11 .  
         [0065]     As described above, the solid state imaging device of the present invention effectively increases the ratio of the device region including the pixels to the chip area without hindering the entrance of light into the pixels, thereby improving the packing density of the solid state imaging device. Thus, the present invention is useful for solid state imaging devices.