Abstract:
Techniques for use with image sensors include transferring a signal level from an active sensor pixel to a readout circuit, performing a flushed reset of the pixel, and isolating the pixel from the readout circuit during resetting of the pixel.

Description:
RELATED APPLICATIONS 
       [0001]    This application claims the benefit of priority of U.S. Provisional Patent Application Ser. No. 60/204,372, filed on May 16, 2000. 
     
    
     BACKGROUND 
       [0002]    The invention relates, in general, to image sensors with pixel reset. 
         [0003]    Image sensors find applications in a wide variety of fields, including machine vision, robotics, guidance and navigation, automotive applications, and consumer products. In many smart image sensors, it is desirable to integrate on-chip circuitry to control the image sensor and to perform signal and image processing on the output image. 
         [0004]    Active pixel sensors (APS), which have one or more active transistors within the pixel unit cell, can be made compatible with complementary metal-oxide-semiconductor (CMOS) technologies and promise high readout rates compared to passive pixel sensors. Active pixel sensors often are arranged as arrays of elements, which can be read out, for example, a column at a time. Each column can be read out at one time, driven and buffered for sensing by a readout circuit. 
         [0005]    A dominant source of noise for some sensors is thermal noise in the channel of the pixel&#39;s reset transistor. Such thermal noise is often referred to as kTC noise. Noise less than kTC noise can be achieved with photodiode-type pixels using soft-reset techniques. Soft, or sub-threshold, reset refers to resetting the pixel with both the drain and gate of the reset transistor maintained at substantially the same potential so that the sense node is reset using sub-threshold MOSFET current. Sub-threshold resetting of photodiode active pixel sensors, however, tends to result in higher image lag and low-light level non-linearity. 
       SUMMARY 
       [0006]    A technique for use with image sensors include transferring a signal level from an active sensor pixel to a readout circuit, performing a flushed reset of the pixel, and isolating the pixel from the readout circuit during resetting of the pixel. In some implementations, the technique includes preventing a parasitic output capacitance from discharging through a load transistor in the readout circuit during the reset operation. 
         [0007]    An integrated circuit chip is disclosed that includes an array of active sensor pixels, readout circuits and a controller for providing control signals. The integrated circuit chip can provide flushed reset of pixels in a selected row and can isolate pixels in the selected row from the associated readout circuits during resetting of the pixels. In some implementations, the integrated circuit chip can prevent a parasitic output capacitance from discharging through load transistors in the readout circuits during resetting of the pixels. 
         [0008]    The controller can be configured for providing a first control signal to enable row selection switches in a selected row of pixels to transfer signal levels from the pixels in the selected row to the associated readout circuits, for subsequently providing a second control signal to enable reset switches in the selected row of pixels, and for causing the first control signal to disable the row selection switches in the selected row of pixels during resetting of the pixels in the selected row. Disabling the row selection switches during the reset operation isolates the pixels in the selected row from their readout circuits. 
         [0009]    Isolating the pixels in the selected row from the associated readout circuits during resetting and preventing discharge of the output capacitance during the reset operation can help reduce or eliminate secondary image lag and non-linearity, in addition to the reduction in lag and non-linearity that may be provided by the flushed reset operation. 
         [0010]    Other features and advantages will be readily apparent from the detailed description, the accompanying drawings and the claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0011]      FIG. 1  is a block diagram of a CMOS active pixel sensor chip. 
           [0012]      FIG. 2  is a block diagram of an array of active pixel sensors and corresponding readout circuitry. 
           [0013]      FIG. 3  illustrates details of an active pixel sensor and a column readout circuit. 
           [0014]      FIG. 4  is a timing diagram associated with  FIG. 3   
           [0015]      FIG. 5  is another timing diagram associated with  FIG. 3 . 
           [0016]      FIG. 6  illustrates results of simulated testing. 
       
    
    
     DETAILED DESCRIPTION 
       [0017]    As shown in  FIG. 1 , an imaging device formed as a monolithic CMOS integrated circuit includes an array of active pixel sensors  30  and a controller  32  that provides timing and control signals to enable reading out of signals stored in the pixels. The array  30  may have dimensions, for example, of 128 by 128 pixels or 256 by 256 pixels, although, in general, the size of the array will depend on the particular implementation. 
         [0018]    The imager can be read out a row at a time using a column parallel readout architecture. The controller  32  selects a particular row of pixels in the array  30  by controlling the operation of a vertical addressing circuit  34  and row drivers  40 . Charge signals stored in the selected row of pixels are provided to a readout circuit  42 . The pixels read from each of the columns then can be read out sequentially using a horizontal addressing circuit  44 . Differential pixel signals (VOUT 1 , VOUT 2 ) can be provided at the output of the readout circuit  42 . 
         [0019]    As shown in  FIG. 2 , the array  30  includes multiple columns  49  of CMOS active pixel sensors  50 . Each column includes multiple rows of sensors  50 . Signals from the active pixel sensors  50  in a particular column can be read out to a readout circuit  52  associated with that column. Signals stored in the readout circuits  52  then can be transferred to an output stage  54  which may be common to the entire array of pixels  30 . The analog output signals then are sent, for example, to a differential analog-to-digital converter (ADC). 
         [0020]    As illustrated in  FIG. 3 , each CMOS active pixel sensor  50  includes a photo-sensitive element such as a photodiode  60  buffered by a source-follower n-channel MOS transistor M 2 . The pixel has an integration capacitance C in  and includes a reset switch that can be implemented as an n-channel MOS transistor M 1  controlled by a signal (RST) applied to its gate. The integration capacitance C in  periodically is charged by current from the photodiode  60  and is reset by turning on and off the reset transistor M 1 . A voltage on the charge-detection (or sense) node  62  is transferred through the source-follower transistor M 2  to the readout circuit  52  by enabling a row selection switch M 3 . The row selection switch can be implemented as an n-channel MOS transistor that is enabled by applying a high signal (ROW) to its gate. The reset and row enable signals (RST, ROW) are common to a row of pixels in the array  30  and are generated by the controller  32 . 
         [0021]    Each column readout circuit  52  includes an n-channel load transistor M 4  for the source-follower transistors M 2  of each pixel in the associated column  49 . The load transistor is controlled by a signal (VLN) applied to its gate. Another n-channel transistor M 5  is connected between the column readout bus  64  and the load transistor M 4 . A control signal (VLN_ENABLE) is applied to the gate of the transistor M 5 . When the transistor M 5  is disabled, it decouples the load transistor M 4  from the rest of the readout circuit  52 . The signals VLN and VLN_ENABLE are generated by the controller  32 . 
         [0022]    In the illustrated implementation, the readout circuit  52  includes two sample-and-hold switches, implemented as n-channel MOS transistors M 9 , M 10 . When the row selection switch M 3  is enabled, the transistor M 9  also is enabled by a high signal (SHS) applied to its gate to allow the selected pixel&#39;s signal level to be stored on the capacitor C 1 . As indicated by  FIG. 4 , the pixel then is reset. The transistor M 10  subsequently is enabled by a high signal (SHR) applied to its gate to allow the selected pixel&#39;s reset level to be stored on the capacitor C 2 . The sample and hold signals (SHS, SHR) are generated by the controller  32  and are common to a row of pixels. Sampling both the reset and signal levels allows correlated double sampling (CDS) to be performed. 
         [0023]    The readout circuit  52  also includes additional circuitry that allows the pixel to be flushed during the reset phase. The additional circuitry includes n-channel MOS transistors M 6 , M 8  as well as p-channel MOS transistor M 7 . That circuitry controls the potential at the drain  66  of the reset transistor M 1 . The power supply voltage (V dd ) is routed to the column of pixels through the p-channel transistor M 7  and the n-channel transistor M 8  which limits the supply voltage excursion. A signal (HTS), generated by the controller  32 , is applied to the gates of the transistors M 6 , M 7 . 
         [0024]    When the pixel is reset, the signal HTS is momentarily pulsed ON (see  FIG. 5 ). That causes the pixel to reset initially in hard reset, followed by soft reset. The parasitic power supply capacitance C P  discharges through the transistor M 6  when the signal HTS is pulsed. Thus, the hard reset erases the pixel memory so that the soft reset level reaches substantially the same level regardless of the strength of the optical signal on the photodiode  60 . 
         [0025]    To help reduce or eliminate the signal-dependent transient current during the reset phase, the pixel output is isolated from the readout circuit  52  by disabling the row selection switch M 3  during the reset operation (see  FIG. 5 ). Disabling the row selection switch M 3  prevents charge that may be stored on the parasitic output capacitance C O  from influencing the equivalent pixel capacitance C in . Results from SPICE simulations ( FIG. 6 ) indicate that the dependency of the pixel&#39;s reset level on the signal level can be reduced significantly or eliminated. Even when the simulated pixel signal level was varied among different values  70 A,  70 B,  70 C, the simulated pixel reset level was substantially the same. 
         [0026]    As also shown in  FIG. 5 , the transistor M 5  can be disabled during the reset operation to prevent the parasitic output capacitance C O  from discharging through the load transistor M 4 . By preventing discharge of the parasitic output capacitance through the load transistor M 4 , the need to recharge the capacitance C O  after the reset operation can be avoided. That can improve the overall operating speed of the imager and reduce overall power consumption. 
         [0027]    In general, the dimensions of the transistors will depend on the particular application. However, examples of transistor dimensions are provided in the following chart: 
         [0000]                                                      Width   Length       Transistor   (microns)   (microns)                                M1   1.1   0.55       M2   1.5   0.7       M3   1.5   0.5       M4   3.6   1.2       M5   6   0.5       M6   1.2   0.5       M7   4   0.5       M8   1.2   0.5                    
Different dimensions may be suitable for other implementations.
 
         [0028]    The foregoing technique can take advantage of flushed reset, also can reduce or eliminate the transient current through the active pixel transistors during the flush phase. Therefore, secondary image lag and non-linearity can be reduced, in addition to the reduction in lag and non-linearity that may be provided by flushed reset. 
         [0029]    Other implementations are within the scope of the claims.