Abstract:
A system for reducing the amount of power consumed by a battery operated computer device is disclosed. A microcontroller continuously monitors the activity of at least one I/O device and sets an activity state variable (ASV) associated with the I/O device accordingly. Upon each the expiration of a preselected time period, the microcontroller examines the state of the ASV to determine whether the I/O device was active during the expired time period. If so, the I/O device is caused to operate in a full power mode; otherwise, the I/O device is caused to operate in a reduced power consumption mode. In one embodiment, the I/O device is capable of operating in more than one reduced power consumption mode, in which case, responsive to a determination that the I/O device was not active during the expired time period, the I/O device is caused to operate in the next lowest power consumption mode. In an alternative embodiment, the frequency with which timer interrupts are generated is automatically adjusted after the expiration of each time period.

Description:
This is a continuation of application Ser. No. 08/381,058 filed on Jan. 31, 1995, now abandoned. 
    
    
     TECHNICAL FIELD 
     The invention relates generally to battery operated devices and, more particularly, to a system for reducing power consumption in such devices. 
     BACKGROUND OF THE INVENTION 
     Portable personal computers (PCs) were first introduced in the early 1980s and have since enjoyed great commercial success and consumer acceptance. As the portable PC market has grown, users have begun to demand lighter weight, lower volume PCs which can be used for longer periods of time between battery charges. Meeting these demands has proved challenging in view of the fact that most portable PCs now support peripheral devices previously available only on desktop PCs. The additional peripherals greatly increase overall power consumption, making it difficult to achieve an optimal level of functionality while maintaining an acceptable battery life. Furthermore, although for reasons other than maximizing battery life, it has become desirable to more efficiently manage power consumption of desktop PCs in order to minimize overall operating costs. 
     Because many of the components and peripheral devices of both desktop and portable PCs consume a great deal of power even when they are not active, power management systems have been developed which cause each component or peripheral device to operate in the lowest power consumption mode with respect to present demands on the system. For example, U.S. Pat. No. 4,980,836 to Carter et al. discloses a power management system for a portable PC system in which the hard disk unit, the floppy disk unit, the keyboard, the serial ports and the printer are monitored for I/O activity to determine whether the system is active and a timer is reset upon each access to any of the monitored devices. If the timer counts down to zero, the system is deemed inactive and is placed in a reduced power consumption mode, in which power is removed from the hard disk unit, the floppy disk unit, the LCD and miscellaneous circuitry and clocks. To bring the system out of the reduced power consumption mode, a user depresses a switch to initiate a wakeup operation. 
     Since Carter, improvements in the basic power management system have been introduced which include options such as blanking the liquid crystal display (LCD) or monitor screen after a preselected period of I/O inactivity or turning off the hard disk drive motor alter the hard disk drive has not been accessed for a preselected period of time. Furthermore, there may be provided more than one reduced power consumption mode. For example, there may be a &#34;STANDBY&#34; mode, in which certain components, such as the LCD and the hard disk drive motor, are caused to enter a reduced power consumption mode but the processing speed of the central processing unit (CPU) is not affected, and a &#34;SLEEP&#34; mode, in which nearly all of the functions of the PC are slowed or halted, including the CPU. From the standpoint of power consumption, the SLEEP mode is substantially equivalent to turning the PC off, except that no data is lost. 
     It may be desirable in many cases to monitor each of a selected group of PC components and cause that component to operate in a reduced power consumption mode if it has not been accessed during a preselected time period. Therefore, what is needed is a system for efficiently monitoring each of a plurality of PC I/O and peripheral devices individually and causing the device to operate in one or more reduced power consumption modes, depending on the type of device, if it is determined that the device has not been accessed during a preselected time period. 
     SUMMARY OF THE INVENTION 
     The foregoing problems are solved and a technical advance is achieved by method and apparatus for reducing power consumption in battery operated devices, namely, PCs. In a departure from the art, a power management system of the present invention individually monitors each of several I/O and peripheral devices of a PC for activity during a predefined activity period, as delimited by a periodic timer associated with the device. Upon the expiration of the associated timer, a determination is made whether the device was active during the expired activity period. If so, the device is caused to continue to operate in a full power mode; otherwise, it is caused to operate in its next lowest reduced power consumption mode. 
     In a preferred embodiment, a PC embodying features of the present invention comprises a power management microcontroller electrically connected via a system bus to at least one I/O, or peripheral, device to be power managed. Also connected to the microcontroller and the I/O device is an I/O activity interrupt generator for monitoring the system bus for I/O device activity and generating an I/O interrupt to the microcontroller upon detection of same. The power management microcontroller includes a power management unit (PMU), comprising appropriate hardware and/or software for implementing the power management functions of the present invention, registers or memory devices for storing an activity state variable (ASV) and a power state variable (PSV), respectively, for each I/O device to be power managed by the PMU, and a periodic timer associated with each I/O device to be power managed by the PMU, it being understood that the periodic timers may be implemented using hardware timers or a combination of hardware and software for generating periodic timer interrupts. The microcontroller controls the power consumption mode of each I/O device (i.e., ON/FULL POWER, STANDBY, SUSPEND, OFF) in accordance with the current state of its ASV and PSV as follows. 
     In general, an ASV has two states, which are IDLE and BUSY. A PSV has two or more states, depending on the type of I/O device with which it is associated and the number of reduced power consumption modes in which the device is operable. With respect to a particular I/O device, when the PC is first turned on, its ASV is set to IDLE, to indicate there has been no I/O activity, its PSV is set to 0, corresponding to an ON, or FULL POWER, mode of the I/O device, and the I/O device is caused to operate in FULL POWER mode. At this point, the periodic timer associated with the I/O device also starts to run. As previously indicated, the I/O activity interrupt generator monitors the system bus for I/O device activity and, upon detecting that an I/O device is active, the interrupt generator generates an I/O activity interrupt to the microcontroller. In addition, the interrupt generator sets an internal flag associated with the active I/O device such that subsequent activity of the I/O device does not result in the generation of an interrupt. Upon the receipt by the microcontroller of an I/O activity interrupt, the ASV is set to BUSY, to indicate the occurrence of I/O activity. 
     Upon the expiration of the associated timer, as indicated by the generation of a periodic timer interrupt to the microcontroller, the state of the ASV is checked. If the ASV is set to BUSY, indicating that I/O activity occurred during the previous period, the device remains in FULL POWER mode, as it is apparently active. Alternatively, if the ASV is set to IDLE, indicating that there was no I/O activity during the period, the PSV is checked to determine the mode of operation of the device and, if the device is not already in its lowest reduced power mode, the PSV is incremented and the device is caused to operate in its next lowest reduced power consumption mode, as indicated by the incremented value of the PSV. In addition, regardless of the states of the ASV and PSV, the internal flag of the interrupt generator associated with the I/O device is reset. 
     In an alternative embodiment, in which the power management microcontroller is used to power manage multiple I/O devices, for example, DEVICE1 and DEVICE2, the microcontroller includes, in addition to the PMU, two ASV registers, designated ASV1 and ASV2, and two PSV registers, designated PSV1 and PSV2, respectively corresponding to DEVICE1 and DEVICE2. In addition, the timer is implemented using a read/write countdown register loaded with a variable TIMER, the value of which controls the period of the timer for generating interrupts. In this embodiment, ASV1 and ASV2 are initiated to 0 (IDLE) and PSV1 and PSV2 are initialized to 0 on power up of the PC. Upon each detection of an I/O activity interrupt, the ASV and PSV of the corresponding device are set to the current value of TIMER and 0, respectively, and the device is caused to operate in a full power mode, it being noted that the I/O interrupt generator is at no time disabled in this alternative embodiment. Upon each detection of a timer interrupt, execution proceeds as described above, except that the value of TIMER is adjusted by subtracting the greater of the value of ASV 1 and ASV2 from TIMER. 
     A technical advantage achieved with the invention is that each of several I/O and peripheral devices of a PC can be monitored individually and caused to operate in successive reduced power consumption modes in an orderly fashion, thereby reducing the overall power consumption of the PC. 
     A further technical advantage achieved with the invention is that each device is systematically cycled through its reduced power consumption modes until it has been placed in the lowest such mode, typically &#34;OFF,&#34; or accessed. 
     Another technical advantage achieved with the invention is that, using the alternative embodiment, the time lag inherent in the use of a static time period may be significantly reduced or eliminated. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1A is a block diagram of a PC for implementing a power management system embodying features of the present invention. 
     FIG. 1B is a block diagram of the power management microcontroller of FIG. 1A. 
     FIG. 2 is flowchart of the operation of the power management system of FIG. 1A. 
     FIG. 3 is a state diagram of the power management system of FIG. 1A. 
     FIG. 4 is a block diagram of a PC for implementing an alternative embodiment of the power management system of the present invention. 
     FIGS. 5A and 5B are a flowchart of the operation of the alternative embodiment of the power management system of FIG. 4. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     In FIG. 1A, a PC including a power management system embodying features of the present invention is designated by reference numeral 10. The PC 10 comprises a power management microcontroller 12, a CPU 13, memory 14, an I/O activity interrupt generator 15, and at least one I/O device 16 all electrically interconnected in a conventional manner via a system bus 17. 
     Referring to FIG. 1B, the power management microcontroller 12 is illustrated in greater detail. As illustrated, the microcontroller 12 includes a power management unit (PMU) 18, comprising appropriate hardware (including memory) and/or software for implementing the power management functions of the present invention, as will be described. Connected to the PMU 18 are a periodic timer 19 associated with the I/O device 16 for generating to the PMU 18 a timer interrupt at periodic intervals, and registers or other appropriate storage devices 22a, 22b, for storing an activity state variable (ASV) and a power state variable (PSV), respectively, or indicating the activity and power states of the I/O device 16. In a particular embodiment, the timer 19 is implemented by programming a hardware register, typically a countdown register, to generate a periodic interrupt at a desired frequency, although it should be understood that the timer 19 may be implemented using hardware or a combination of hardware and software for generating periodic timer interrupts. As will be described in greater detail with reference to FIGS. 2 and 3, the microcontroller 12 controls the power consumption mode of the I/O device 16 (i.e., FULL POWER, STANDBY, SUSPEND, OFF) in accordance with the current state of the ASV and the PSV stored in the registers 22a, 22b. 
     It should be understood that, although not shown, the PC 10 may include any number of I/O devices, such as the I/O device 16, to be power managed. Accordingly, for each such I/O device, the PC 10 will include an associated timer, such as timer 19, and ASV and PSV registers, such as the registers 22a, 22b, corresponding to the state and power consumption mode of the managed I/O device. Alternatively, the PC 10 may include a single timer and a single set of ASV and PSV registers 22a, 22b, for the entire system, in which case all of the I/O devices will be power managed simultaneously. 
     In general, the ASV has two states, which are IDLE and BUSY, while the PSV has two or more states, depending on the type of I/O device 16 and the number of reduced power consumption modes in which the device is operable. For example, a particular type of display device may have n power consumption modes, where n is greater than two (2), as shown in Table I below: 
     
                       TABLE I______________________________________PSV Value        Device Power Mode______________________________________0                ON/FULL POWER1                STANDBY2                SUSPENDn                OFF______________________________________ 
    
     In a preferred embodiment, as shown in Table I, the Device Power Modes are arranged in order of decreasing power consumption and in an inverse relationship with the value of the PSV, such that as the value of the PSV increases, the power consumption mode of the device decreases. 
     Alternatively, the I/O device 12 may be a hard disk drive having only two power modes, as shown below in Table II: 
     
                       TABLE II______________________________________PSV Value        Device Power Mode______________________________________0                ON/FULL POWER1                OFF______________________________________ 
    
     Although described with greater specificity below with reference to FIGS. 2 and 3, the overall operation of the power management functions of the system 10 may be generally described as follows. At the outset, it should be observed that, although the operation of the power management system will be described with respect to a single I/O device, i.e., the I/O device 16, the below described functions may occur with respect to each I/O device to be power managed. Accordingly, when the PC 10 is first turned on, the ASV in the register 22a is set to IDLE, to indicate there has been no I/O activity, the PSV in the register 22b is set to 0, corresponding to an ON, or FULL POWER, mode of the I/O device 16, and the I/O device 16 is caused to operate in its FULL POWER mode. At this point, the periodic timer 19 also starts to run. 
     Responsive to the detection by the I/O activity interrupt generator 15 of I/O device 16 activity, the generator 15 generates an I/O activity interrupt to the microcontroller 12 and sets an internal flag associated with the I/O device 16. In accordance with a feature of the present invention, so long as the internal flag is set, the generator 15 will not generate an I/O activity interrupt responsive to detection of I/O device 16 activity. Responsive to detection by the PMU 18 of an I/O activity interrupt from the generator 15, the ASV is set to BUSY, to indicate the occurrence of I/O activity during the period, the PSV is set to 0 and the device is caused to operate in FULL POWER mode, corresponding to PSV=0. Upon the expiration of the current period, as indicated by the timer&#39;s 19 generating a periodic timer interrupt to the PMU 18, the state of the ASV is checked. If the ASV is set to BUSY, indicating that I/O activity occurred during the previous period, the value of PSV and the power consumption mode of the device 16 remain unchanged and the ASV is set to IDLE. Alternatively, if the ASV is set to IDLE, indicating that there has been no I/O activity during the previous period, the PSV is checked to determine the power consumption mode of the device and, if the device is not already in its lowest reduced power consumption mode, (i.e., if the PSV is not set to its maximum value), the PSV is incremented and the device is caused to operate in its next lowest reduced power consumption mode, that is, the mode corresponding to the incremented value of the PSV. 
     Referring now to FIG. 2, the functions implemented by the microcontroller 12 and PMU 18 for power managing the device 16 will be described in greater detail. It should be understood that appropriate instructions for execution by the microcontroller 12 for implementing the below described functions are stored in a memory device (not shown) associated with or incorporated into the microcontroller 12. Execution begins in step 200 when the PC 10 is powered on by a user. In step 202, the ASV is set to IDLE and the PSV is set to 0. In step 204, the internal flag of the interrupt generator 15 is reset, to enable the generation of an I/O activity interrupt. In step 206, a determination is made whether an I/O activity interrupt has been detected by the PMU 18. If in step 206 it is determined that an I/O activity interrupt has been detected, execution proceeds to step 208, in which the ASV is set to BUSY and the PSV is set to 0. In addition, the device 16 is set to a power consumption mode associated with the value of the PSV, in this case, ON/FULL POWER. Execution then proceeds to step 210, in which the internal flag of the interrupt generator 15 is set, thereby disabling the generation of I/O activity interrupts responsive to subsequent I/O device 16 activity. 
     Execution then proceeds to step 212, in which a determination is made whether a timer interrupt has been received by the PMU 18. Moreover, if in step 206, it is determined that an I/O activity interrupt has not been received, execution proceeds directly to step 212. If in step 212 it is determined that a timer interrupt has not been received, execution returns to step 204; otherwise, execution proceeds to step 214. In step 214, a determination is made whether the ASV is set to IDLE. If it is determined that the ASV is set to IDLE, execution proceeds to step 216, in which a determination is made whether the PSV is set to its maximum value, which, as demonstrated above with reference to Tables I and II, will vary according to the number of power consumption modes in which the device 16 is operable. If it is determined that the PSV is not set to its maximum value, in step 218, the PSV is incremented by one (1) and the device 16 is caused to operate in the corresponding reduced power consumption mode. 
     It should be clear that the combination of steps 216 and 218 effect the following result: if the device 16 is not already in the lowest possible power consumption mode (step 216), the device 16 will be caused to operate in its next lowest possible power consumption mode (step 218). Execution then proceeds to step 220. If in step 214, it is determined that the ASV is not set to IDLE, or if in step 216, it is determined that the PSV is set to its maximum value, execution proceeds directly to step 220. In step 220, the ASV is reset to IDLE and execution returns to step 204. 
     FIG. 3 shows a state diagram of the PC 10 during a power management operation in which the device 16 is operable in n reduced power consumption modes, wherein n is greater than two (2), as shown in Table I above. Referring to FIGS. 1 and 3, upon power up, the PC 10 is in a state 300, in which the ASV is set to IDLE, the PSV is set to 0, and the device 16 is ON (FIG. 2, steps 200, 202). Upon the detection by the microcontroller 12 of an I/O activity interrupt, the PC 10 transitions to a state 302, as indicated by a line 304, in which the ASV is set to BUSY, the PSV is set to 0, and the device 16 remains ON (FIG. 2, steps 206, 208). Upon the generation by the timer 19 of a periodic timer interrupt, while the PC 10 is in the state 304, the PC 10 transitions back to the state 302, as indicated by a line 308 (FIG. 2, steps 212, 214, 220). 
     Upon the generation by the timer 19 of a periodic timer interrupt while the PC 10 is in the state 302, the PC 10 transitions to a state 310, as indicated by the line 312, in which the ASV is set to IDLE, the PSV is set to 1, and the device 16 is caused by the microcontroller 12 to operate in its first reduced power consumption mode, for example, &#34;STANDBY&#34; (FIG. 2, steps 212-220). Upon the generation by the timer 19 of a periodic timer interrupt while the PC 10 is in the state 310, the PC 10 transitions to a state 314, as indicated by a line 316, in which the ASV is set to IDLE, the PSV is set to 2, and the device 16 is caused by the microcontroller 12 to operate its second reduced power consumption mode, for example, &#34;SUSPEND&#34; (FIG. 2, steps 212-220). 
     This process continues, with the PC transitioning to states corresponding to lower reduced power consumption modes responsive to upon the generation of a periodic timer interrupt, until the PC 10 transitions to a state 318, as indicated by a line 320, in which the ASV is set to IDLE, the PSV is set to n, and the device 16 is caused to operate in its lowest reduced power consumption mode, which is &#34;OFF&#34; (FIG. 2, steps 212-220). In the embodiment illustrated in FIG. 3 (and Table I), &#34;n&#34; is the maximum value for the PSV. Accordingly, upon the occurrence of subsequent periodic timer interrupts while the PC 10 is in the state 318, the PC 10 transitions back to the state 318, as indicated by the line 322 (FIG. 2, steps 212-216, 220). 
     It should be obvious from the above that, assuming the device 16 has n possible reduced power consumption modes (including OFF and excluding ON), upon each occurrence of a periodic timer interrupt while the ASV is set to IDLE, the PSV will incremented by one and the device 16 will caused by the microcontroller 12 to enter the next lowest possible power consumption mode until the PSV has been incremented to n and the device 16 has been caused to operate in its lowest reduced power consumption mode (typically OFF). At that point, the device 16 will continue to operate in this lowest power consumption mode until the generation by the device 16 of an I/O activity interrupt, as at which point, the device 16 is returned to its FULL POWER mode and the ASV and the PSV are set to BUSY and 0, respectively. 
     Referring again to FIG. 3, upon the generation by the device 16 of an I/O activity interrupt while the PC 10 is in one of the states 310, 314 or 318, the PC 10 transitions to the state 304, as shown by lines 324, 326 or 328, respectively (FIG. 2, steps 206, 208). 
     Referring to FIG. 4, in an alternative embodiment of the present invention, the system is modified to advantageously power manage multiple I/O devices. As shown in FIG. 4, a PC 400 includes first and second I/O devices, respectively designated by reference numerals 402 and 404, respectively, interconnected with a power management microcontroller 412, CPU 413, memory 414, and an I/O activity interrupt generator 415 via a system bus 417. Similar to the power management microcontroller 12 (FIG. 1), the microcontroller 412 includes a PMU 418 and a timer 419. In addition, as described, but not shown, above in connection with FIGS. 1 and 2, the PMU 418 is connected to a set of ASV registers 422a and a set of PSV registers 422b for storing a respective ASV and PSV for each of the devices 402, 404. For purposes of clarity, the device 402 will be alternatively referred to herein as DEVICE1, with its corresponding ASV and PSV being designated ASV1 and PSV1. Similarly, the device 404 will be alternatively referred to herein as DEVICE2, with its corresponding ASV and PSV being designated ASV2 and PSV2. 
     In the preferred implementation of the embodiment shown in FIG. 4, the timer 419 comprises a programmable mad/write countdown register in which is stored a TIMER variable for controlling the frequency with which timer interrupts are generated by the timer 419. In addition, it should be recognized that the generator 415 generates individual I/O activity interrupts for each of the devices 402, 404, responsive to detection of activity thereof, respectively. As will be described, in this alternative embodiment, the generator 415 is not selectively enabled and disabled; rather, it remains in a constantly enabled state. 
     The operation of the alternative embodiment of the present invention will be described in greater detail with reference to FIGS. 5A and 5B. Execution begins in step 500 when the PC 400 is powered on by a user. In step 502, ASV1 and ASV2 are set to IDLE, which in this embodiment is represented by a logic 0, and PSV1 and PSV2 are also set to 0. In step 504, a determination is made whether the generator 415 has generated an I/O activity interrupt corresponding to DEVICE1 (hereinafter &#34;DEVICE1 interrupt&#34;). If so, execution proceeds to step 506, in which ASV 1 is set to the current value of TIMER, PSV1 is set to 0, and DEVICE1 is caused to operate in FULL POWER mode. Execution then proceeds to step 508. If in step 504, the generator 15 has not generated a DEVICE1 interrupt, execution proceeds directly to step 508. In step 508, a determination is made whether the generator 415 has generated an I/O activity interrupt corresponding to DEVICE2 (hereinafter &#34;DEVICE2 interrupt&#34;). If so, execution proceeds to step 510, in which ASV2 is set to the current value of TIMER, PSV2 is set to 0, and DEVICE2 is caused to operate in FULL POWER mode. 
     In step 512, a determination is made whether the timer 419 has generated a timer interrupt, which will occur when the timer 419 has counted down from the value of TIMER to zero. If not, execution returns to step 504; otherwise, execution proceeds to step 514. As previously indicated, the generator 415 is not disabled responsive to generation of an I/O activity interrupt; therefore, the values of ASV1 and ASV2 may be changed more than once before a timer interrupt is generated in step 512. In step 514, a determination is made whether ASV1 is set to 0 (IDLE). If so, execution proceeds to step 516, in which a determination is made whether PSV1 is set to its maximum value, as described above with reference to step 216 (FIG. 2). If not, execution proceeds to step 518. In step 518, PSV1 is incremented by 1 and DEVICE1 is caused to operate in the corresponding reduced power consumption mode as described above with reference to step 218 (FIG. 2). 
     Execution then proceeds to step 520. If in step 514, it is determined that ASV1 is not set to 0 (IDLE) or if in step 516, it is determined that PSV1 is set to its maximum value, execution proceeds directly to step 520. In step 520, a determination is made whether ASV2 is set to 0 (IDLE). If so, execution proceeds to step 522, in which a determination is made whether PSV2 is set to its maximum value. If not, execution proceeds to step 524, in which PSV2 is incremented by 1 and DEVICE2 is caused to operate in the corresponding reduced power consumption mode. Execution then proceeds to step 526. If in step 520 it is determined that ASV1 is not equal to 0 or if in step 522 it is determined that PSV2 is not set to its maximum value, execution proceeds directly to step 526. In step 526, the variable TIMER for controlling the period of the timer 419, is set to equal the maximum time period minus the greater of ASV1 and ASV2. It should be recognized that if both DEVICE1 and DEVICE2 were idle during the period (ASV1=ASV2=0), the value of TIMER will be the maximum time period. 
     In this manner, the frequency with which timer interrupts are generated is appropriately dynamically adjusted according to the activity of the devices being managed. Accordingly, the time lag inherent in the use of a static time period is effectively eliminated, as the timer 419 period will be adjusted to the smallest period necessary to ensure effective power management. For example, a hard disk may be programmed to spin down after 15 seconds of inactivity and the timer programmed to generate timer interrupts every 5 seconds. Using a static time period, if the disk is accessed one millisecond (1 ms) after the timer interrupt, the disk will spin down 20 seconds minus 1 ms after the last access, rather than 15 seconds thereafter, as it is supposed to do. This problem is eliminated by the use of a dynamic time period, as implemented in the alternative embodiment, which is adjusted to compensate for this occurrence. 
     It is understood that the present invention can take many forms and embodiments. The embodiments shown herein are intended to illustrate rather than to limit the invention, it being appreciated that variations may be made without departing from the spirit or the scope of the invention. For example, the PMU 18 may comprise a conventional &#34;System Management Mode&#34; unit of a microcontroller, as is well known in the art. Alternatively, the PMU 18 may comprise specialized software and hardware for implementing the above-described functions. Moreover, any number of I/O and/or peripheral devices may be power managed using the above-described power management system. Still further, the timer 419 may be implemented using a countup timer, in which case the value of TIMER would be adjusted by adding the value of the lesser of ASV1, ASV2 to TIMER. 
     Although illustrative embodiments of the invention have been shown and described, a wide range of modification, change and substitution is intended in the foregoing disclosure and in some instances some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.