Abstract:
A probe card is provided for probing a semiconductor wafer with raised contact elements. In particular, the present invention is useful with resilient contact elements, such as springs. A probe card is designed to have terminals to mate with the contact elements on the wafer. In a preferred embodiment, the terminals are posts. In a preferred embodiment the terminals include a contact material suitable for repeated contacts. In one particularly preferred embodiment, a space transformer is prepared with contact posts on one side and terminals on the opposing side. An interposer with spring contacts connects a contact on the opposing side of the space transformer to a corresponding terminal on a probe card, which terminal is in turn connected to a terminal which is connectable to a test device such as a conventional tester.

Description:
This application is a continuation of application Ser. No. 09/204,740, filed Dec. 2, 1998 now U.S. Pat. No. 6,483,328, which is a continuation-in-part of U.S. patent application Ser. No. 08/554,902, filed Nov. 9, 1995, now Pat. No. 5,974,662. 
    
    
     FIELD OF THE INVENTION 
     This invention is directed to an apparatus for probing semiconductor wafers. More particularly, this invention is directed to probing a semiconductor wafer with raised contact structures. This invention is particularly well suited for probing wafers with resilient contact structures. 
     BACKGROUND OF THE INVENTION 
     It is well understood in the art of manufacturing semiconductor devices to test devices while still unsingulated from the wafer for some level of functionality. Conventionally this is done using a probe card and a prober. A representative probe card is illustrated in FIG.  1 . The probe card is mounted in a prober, which in turn detects with high precision the position and orientation of the probe card, and the position and orientation of a wafer to be tested, then brings the two into precise alignment. The probe card is connected in turn to a tester, providing a connection between the tester and one or more devices on the wafer. The tester can energize the device under test (DUT) and evaluate the performance of the device. This process is repeated as needed to test substantially each device on the wafer. Devices which pass the test criteria are processed further. 
     One particularly useful probe card makes use of resilient spring elements for contacting the wafer. Such a probe card is illustrated in FIG.  1 . This probe card is described in detail in copending U.S. patent application Ser. No. 08/554,902, filed Nov. 9, 1995, which is incorporated herein in full by reference. This probe card also is described in detail in copending, commonly assigned U.S. patent application Ser. No. 09/156,957, filed Sep. 18, 1997, which is a divisional of Ser. No. 08/554,902. This application also is incorporated herein in full by reference. 
     Semiconductor devices are manufactured on a semiconductor wafer but must be singulated and connected to external devices in order to function. For many years, the standard method of connecting a semiconductor involves fabricating a semiconductor device with pads, typically of aluminum. These pads are connected to larger structures, typically a lead frame, typically using wirebonding. The lead frame can be mounted in a suitable package, typically of ceramic or plastic. The spacing of connections on the package is designed to mate with a circuit board or other mating device such as a socket. Various innovations in packaging over the years allow for relatively close spacing and ever higher pin counts in packaging. 
     A significant change from this packaging paradigm is seen in BGA packaging. Here, the contact points are globules of a reflowable material. A solder material is commonly used, so that a package can be positioned at a contact area then heated to reflow the solder, providing a secure electrical connection. This same general strategy is used at the chip level, forming small bumps over contact areas. A commonly used process makes C 4  balls (controlled collapse chip connection). 
     Conventional probe cards are designed to contact traditional bond pads, typically aluminum. The novel probe card of  FIG. 1  is useful for this purpose as well. Probing C 4  balls is more complex for a variety of reasons, but the probe card of  FIG. 1  is particularly well suited for this purpose as well. 
     A new form of packaging has become available which allows formation of small resilient contact structures directly on a semiconductor wafer. This is the subject of several patents, including U.S. Pat. No. 5,829,128, issued Nov. 3, 1998. An illustrative embodiment is shown in  FIG. 2  as wafer  208  with springs  224  connected to terminals  226 . 
     A large scale contactor has been disclosed for contactor some or all of a semiconductor wafer which is built with resilient contact elements. Fixturing and burn-in processes are described in copending, commonly assigned U.S. patent application Ser. No. 08/784,862, filed Jan. 15, 1997, which is incorporated herein in full by reference. The corresponding PCT application was published as WO 97/43656 on Nov. 20, 1997. 
     SUMMARY OF THE INVENTION 
     The present invention provides a probe card useful for probing a semiconductor wafer with raised contact elements. In particular, the present invention is useful with resilient contact elements, such as springs. 
     A probe card is designed to have terminals to mate with the contact elements on the wafer. In a preferred embodiment, the terminals are posts. In a preferred embodiment the terminals include a contact material suitable for repeated contacts 
     In one particularly preferred embodiment, a space transformer is prepared with contact posts on one side and terminals on the opposing side. An interposer with spring contacts connects a contact on the opposing side of the space transformer to a corresponding terminal on a probe card, which terminal is in turn connected to a terminal which is connectable to a test device such as a conventional tester. 
     It is an object of this invention to provide a probe card for probing a semiconductor device with raised contact elements. 
     This and other objects and advantages of the invention, as well as the details of an illustrative embodiment, will be more fully understood from the following specification and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a probe card for probing conventional semiconductor devices. 
         FIG. 2  illustrates a probe card for probing semiconductor devices with raised contact elements. 
         FIG. 3  illustrates a second embodiment of a probe card for probing semiconductor devices with raised contact elements. 
         FIGS. 4 through 9  illustrate steps in the process of forming a post suitable for use in the probe card of this invention. 
         FIGS. 10 and 11  illustrate an exemplary probe card used with a wafer including travel stop protectors. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The probe card assembly of  FIG. 1  has been described in detail in copending, commonly assigned U.S. patent application Ser. No. 08/554,902, filed Nov. 9, 1995, and in copending, commonly assigned U.S. patent application Ser. No. 09/156,957, filed Sep. 18, 1997. This figure is  FIG. 5  in these earlier applications, and the numbers are in the 500 series, renumbered here in the 100 series. 
     Referring to  FIG. 2 , the probe card assembly of  FIG. 1  has been modified slightly for the new purpose. Common elements include supporting probe card  102  which is mounted (not shown) into a prober. Interposer  112  includes springs  114  and corresponding springs  116  which connect through the interposer so that corresponding terminals  110  and  120  are electrically connected. In space transformer  106 , corresponding terminals  120  and  222  ( 122  in  FIG. 1 ) are connected. Probe card  102  supports connecting circuitry so a tester lead can be connected to a corresponding terminal  110 , and then through  114 ,  116 ,  120  and  222  (or  122 ) to receive a connection from a semiconductor device. In  FIG. 1 , resilient contact element  124  is connected to terminal  122 , and is brought into contact with terminal  126  on semiconductor wafer  108  In  FIG. 2 , semiconductor wafer  208  has terminals  226  which in turn have raised contact element, here resilient contact elements  224 , which can be brought into contact with corresponding terminals  222  to complete a circuit to the tester. The tester can energize a connected semiconductor device and evaluate the functionality of the device. 
     Interposer  112  with springs  114  and  116  pushes against terminals  114  and  120 . By compressing the space transformer  118  towards the probe card  102 , the interposer will maintain contact with each corresponding terminal  110  and  120  even if the planarity of the tips of springs  114 , of springs  116 , of terminals  110  and of terminals  120  are imperfect. Moreover, within the limits of resiliency of the various components, the space transformer can be angled relative to the probe card to allow for alignment in certain dimensions. Differential screws  138  and  136  can be adjusted very precisely to reorient the surface of space transformer  118  relative to probe card  102 . Consequently, things connected to the space transformer correspondingly will be oriented. Thus the tips of springs  124  in FIG.  1  and the terminals  222  in  FIG. 2  can be positioned with high accuracy relative to a semiconductor wafer. 
     Referring to  FIG. 3 , the components of  FIG. 2  can be seen in an alternative embodiment. The primary elements function as described in relation to FIG.  2 . Space transformer  324  supports terminals  336  and  335 , which are connected appropriately. Interposer  325  supports resilient contact elements  334  and  333 . Probe card  321  supports terminals  332  and  331 , which are connected appropriately. In general, a lead from a tester will connect to a terminal  331 , which is connected in turn to a terminal  332 , then through resilient contact elements  333  and  334  to a terminal  335  and finally to a corresponding terminal  336 . Support spring  320  holds the space transformer  324  against interposer  325  and probe card  321 . Orienting device  322  functions as described above to refine the orientation of the space transformer relative to the prove card  321 . 
       FIG. 3  shows a broader view of semiconductor wafer  310 , here with several distinct semiconductor devices  311 . Here a single semiconductor device is shown almost connected with corresponding terminals  336 . By moving semiconductor wafer  310  towards probe card  321 , a microspring contact  301  is brought into direct and intimate contact with a corresponding terminal  336 , and connected therefore to a corresponding tester lead. After testing, the semiconductor wafer can be repositioned to bring another semiconductor device into contact with the corresponding terminals on the probe card assembly. 
       FIG. 4  illustrates a particularly preferred method of fabricating a post structure. Details of fabricating the interposer, space transformer, and probe card are detailed in copending, commonly assigned U.S. patent application Ser. No. 08/554,902, filed Nov. 9, 1995, and in copending, commonly assigned U.S. patent application Ser. No. 09/156,957, filed Sep. 18, 1997, and earlier applications cited in these applications. 
     Referring to  FIG. 4 , in structure  400  a support substrate  405  includes terminal  410 , interconnection  420 , and terminal  415 . Suitable materials and alternative compositions are detailed in the referenced applications. For a preferred embodiment, the support substrate is a multilayer ceramic substrate. A conductive layer  417  connects a plurality of terminals  415  (other terminals not shown). A more detailed description of the following steps can be found in copending, commonly assigned application entitled “Lithographic Contact Elements”, being filed on even date herewith, no serial number yet assigned.  FIGS. 4 through 7 . are adapted from  FIGS. 1 through 4  of that corresponding application. 
     In the process of electroplating, it is advantageous to provide a common connection between elements to be plated in order to provide a suitable circuit for plating. Other methods of deposition may be used to form structures similar to the one described here. Such methods are described or references in applications Ser. No. 08/554,902 and Ser. No. 09/156,957 and supporting applications. One alternative to a shorting layer such as  417  is to provide a shorting layer  407  directly connecting a plurality of terminals  410  (only one shown here). Both are shown here but in practice generally only one or the other would be used. Use of a “top” layer such as  407  is particularly advantageous when there is no convenient way to connect through the substrate. Such might be the case when using silicon as a substrate, or certain configurations of ceramic, polyimide, or other materials. 
     Shorting layer  407  is applied by sputtering Details of materials, thicknesses, processing variations and the like can be found in corresponding, commonly assigned U.S. patent application Ser. No. 09/032,473, filed Feb. 26, 1998, entitled “Lithographically Defined Microelectronic Contact Structures,” which is incorporated herein in full by reference. One particularly preferred material is an alloy of tungsten and titanium. This can be applied by sputtering. A useful depth is on the order of 3,000 to 6,000 Angstroms, such as about 4,500 Angstroms. Various alloys of titanium or of tungsten also are useful. 
     A layer of resist such as a negative photoresist  425  is applied to the surface of the substrate (on top of any other applied layers, of course). This is patterned to leave an opening over terminal  410 . 
     A suitable structural material  430  is deposited in the opening in the photoresist, more than filling the opening. In a preferred embodiment, a material such as an alloy of nickel and cobalt is deposited by electroplating. Other useful materials include copper, palladium, palladium cobalt, and alloys including these materials. Other deposition methods such as sputtering may be suitable. 
     A lapping or grinding process such as chemical-mechanical polishing is used to remove excess structural material to leave a highly planar structure. Moreover, other structures on the substrate are planarized. It is desirable to have minimal height deviation both in the region of a single post as well as over a series of posts. Flatness on the order of one in 1,000 (height above surface measured at relatively distant corresponding feature) is desirable although the specific constraints of a given design may well allow for 2 to 5 to 10 in 1,000 or even more. This corresponds to a height consistency of 100 microinchs per linear inch or 1 micron per centimeter. 
     In one preferred embodiment an additional contact layer is applied. Referring to  FIG. 8 , a contact layer  431  is deposited onto structural material  430 . In one preferred embodiment, this is deposited by electroplating. A preferred material is an alloy of palladium and cobalt. Other useful materials include palladium, hard gold, soft gold and rhodium. The thickness can be chosen by design criteria understood by those skilled in the art of making contact components. In one preferred embodiment the thickness is from about 0 to about 200 microinches (0 to about 5 microns). 
     The structure is finished by stripping the masking layer of photoresist, and removing the conductive layer  407  or  417 . Useful techniques include ashing, wet etch and laser ablation. Details of time, materials and conditions are extremely well known in the art. Referring to  FIG. 9 , the finished structure  400  then can be incorporated in a probe card assembly as shown in  FIG. 2  or  3 . 
     The geometries of the terminals are quite flexible using this method and the designer has a great degree of flexibility. It is quite simple to form posts which are approximately square in cross section (in the XY plane of the substrate surface). This can be on the order of about 1 to 10 mils. Obviously almost any size and shape can be designed here. It is convenient to make the height of the structure on the order of 0 to 60 mils (0 to 1.5 millimeters). Of course the terminal can actually be recessed below the surface of the substrate so long as the terminals collectively are highly planar. A useful height is on the order of about 5 to about 10 mils (125 to 250 microns). Another preferred embodiment includes structures which are on the order of about 40 to 60 mils (1 to 1.5 millimeters). 
     Orienting the probe structure so it is aligned as well as possible with the plane of the wafer to be tested is very beneficial. Having the surface of the space transformer reasonably flat is very helpful as well. Assuming that the contact ends of the resilient contact structures on the wafer (“tips” in one perspective) are generally co-planar, bringing coplanar tips into contact with coplanar terminals across aligned planes means that the tips can be depressed a minimal amount in order to guarantee contact of all tips with all terminals. Whatever amount of non-coplanarity exists in the tips, in the terminals, or in mis-alignment of the planes for contact means that some portion of the tips will have to travel further in order to guarantee that all tips are in satisfactory contact. The structure described here can readily be made relatively flat and oriented successfully to allow minimal drive on the wafer. In a preferred design, an over travel on the order of 3 mils (75 microns) is one useful design point. That is, from the point where the first tip touches a corresponding terminal, the base corresponding to that tip is driven the over travel distance closer to the terminal. This compresses the tip against the terminal and, in many designs, causes the tip to slide across the terminal, thus digging into and through any contaminants that may be present on either the tip or the terminal. This also drives other tips into contact and along corresponding terminals. If things are properly designed and aligned the selected degree of overtravel will cause the tip which is last to contact a corresponding terminal still to be able to establish a suitable contact. 
     Some instances of wafers with springs include an overtravel stop protector. Such overtravel stop protectors are described in detail in copending, commonly assigned United States patent application &lt;serial number not available&gt;, filed Jul. 13, 1998, entitled “Interconnect Assemblies and Method”, naming as a sole inventor Benjamin Eldridge. Referring to  FIG. 10 , one example of such an overtravel stop protector can be seen. Semiconductor wafer  1008  is fabricated to include terminals  1026 , with resilient contact elements  1024 . Compare  208 ,  226  and  226  in FIG.  2 . In addition, an overtravel stop protector  1025  is included. In one preferred embodiment this takes the form of a cured epoxy. The protector can take many forms. As illustrated, the protector is more or less a field of epoxy, generally planar, with openings only for the resilient contact elements  1024 . The height of the stop protector is selected so each resilient contact element can deform the desired amount but then will pass below the level of the protector, effectively limiting overtravel. A wafer with such stop protectors can be tested using the same apparatus described above in  FIGS. 2 and 3 . 
     Referring to  FIGS. 10 and 11 , as the resilient contact elements  1024  first contact corresponding terminals  222 , the resilient contact elements first touch the corresponding terminals then begin to wipe across the surface. In  FIG. 11  the resilient contact elements  1024 A are in contact and have been compressed to some degree. In  FIG. 11 , each terminal  222  has come into contact with a corresponding overtravel stop protector  1025  and will not further depress the corresponding resilient contact element  1024 A If the semiconductor wafer  1008  is driven further toward probe card  102  (shown in FIG.  10 ), the overtravel stop protectors  1025  will press against terminals  222 , driving space transformer  118  towards probe card  102 . With sufficient drive force on semiconductor wafer  1008 , probe card  102  will be deformed away from the semiconductor wafer. Designers can select stiffness propertied for the probe card to accommodate expected probing force One factor to consider is the number of resilient contact elements expected to contact the probe card assembly. Another factor is the spring constant of each spring. Another factor is to consider how much the probe card should yield when the probe card is overdriven. In general, if the spring constant per resilient contact element is k s , then for n springs the effective spring rate of contacted springs is nk s . In one preferred embodiment, the spring rate for the probe card k pcb  is greater than or equal to nk s . It is particularly preferred that the k pcb  be on the order of 2 times nk s . 
     One particularly preferred mode of operation is to have the overtravel stops evenly meet the probe card assembly then provide little or no additional force. 
     A general description of the device and method of using the present invention as well as a preferred embodiment of the present invention has been set forth above. One skilled in the art will recognize and be able to practice many changes in many aspects of the device and method described above, including variations which fall within the teachings of this invention. The spirit and scope of the invention should be limited only as set forth in the claims which follow.