Abstract:
Analog buffers with a precise gate to source voltage compensation and a small DC offset, by storing an input offset voltage to be used as an output offset voltage to reverse the offset in the input. A first source follower at the input end and a second source follower at the output end are both coupled to a switching circuit, wherein the first follower provides an input offset voltage (e.g., |Vgsp|) based on the input voltage (Vin), the second source follower provides an output voltage (Vout) by compensating Vin transmitted through the analog buffer circuit with an output offset voltage (|Vgsn|), and the switching circuit stores and equalizes the output offset voltage to the input offset voltage (|Vgsp|=|Vgsn|), so to obtain an output Vout that is identical to Vin.

Description:
BACKGROUND  
       [0001]     The invention relates to analog buffers, and more particularly, to unit-gain analog buffers with a precise gate to source voltage (V gs ) compensation and a small DC offset.  
         [0002]     In conventional display systems, digital-to-analog conversion (DAC) is the most important part of a driving circuit. Typically, a digital-to-analog converter requires a unit-gain analog buffer to improve the driving performance thereof. In normal integrated circuits (ICs) designs, analog buffer typically comprises operational amplifiers, as shown in  FIG. 1 . However, it requires a large chip area.  
         [0003]     To reduce total module costs, the “system-on-glass” technology by low temperature poly-Si (LTPS) TFTs offers a promising solution because the LTPS allows integration of driving circuit on glass. However, operational amplifiers composed of TFTs have poor performance, such as small gain, large DC offset, high power consumption, slow slew rate, and large area.  
         [0004]      FIGS. 2A and 2B  show conventional analog buffers comprises N-type source follower or P-type source follower. The output voltage thereof, however, has a DC offset of a V gs .  FIGS. 3A and 3B  show conventional analog buffers comprise a source follower with threshold voltage compensation and V gs  compensation.  FIG. 3C  is a timing chart of the conventional analog buffers shown in  FIGS. 3A and 3B . It, however, also has a large DC offset at the output voltage and/or poor driving performance.  
       SUMMARY  
       [0005]     The invention is directed to the broad concept of providing an analog buffer, that stores an input offset voltage, to be used as an output offset voltage, to reverse the offset in the input, so as to obtain a Vout=Vin. In one aspect, of the invention, an analog buffer comprises a first source follower at the input end and a second source follower at the output end, both coupled to a switching circuit, wherein the first source follower provides an input offset voltage (e.g., |Vgsp|) based on the input voltage (e.g., Vin), the second source follower provides an output voltage (e.g., Vout) by compensating Vin transmitted through the analog buffer circuit by an output offset voltage (e.g., |Vgsn|), and the switching circuit stores and equalizes the output offset voltage to the input offset voltage (e.g., |Vgsp|=|Vgsn|), so to obtain an output Vout that is identical to Vin.  
         [0006]     In another aspect, the present invention discloses embodiments of an analog buffer, in which a first source follower provides a first offset voltage according to an input voltage in a first period, a second source follower provides an output voltage essentially equal to the input voltage in a second period, and a switching circuit coupled to the first source follower and second source follower, which provides a second offset voltage essentially equal to the first offset voltage in a third period intermediate between the first period and second period, wherein the second source follower provides the output voltage based on the second offset voltage.  
         [0007]     In a further aspect, the present invention discloses embodiments of an analog buffer, in which a first source follower regulates a first voltage according to an input voltage in a first period, and a switching circuit coupled to the first source follower regulates a second voltage essentially equal to the first voltage, according to the input voltage in a second period. A second source follower is coupled to the switching circuit, receiving the first voltage and the second voltage in the first period and the second period respectively, and outputting the input voltage to a load according thereto in the second period.  
         [0008]     In another aspect, the present invention discloses embodiments of a signal driving circuit, in which a digital-to-analog converter (DAC) regulates an analog voltage according to a digital data and an analog buffer as mentioned above, buffering the analog voltage received from the DAC and outputting to a load.  
         [0009]     In a further aspect, the present invention discloses embodiments of a display system, in which a signal driving circuit is mentioned above and a display element coupled to the signal driving circuit, wherein the display element is driven by the signal driving circuit. 
     
    
     DESCRIPTION OF THE DRAWINGS  
       [0010]     The invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:  
         [0011]      FIG. 1  shows a conventional analog buffer with operational amplifier;  
         [0012]      FIG. 2A  shows a conventional analog buffer comprising a N-type source follower;  
         [0013]      FIG. 2B  shows a conventional analog buffer comprising a P-type source follower;  
         [0014]      FIGS. 3A and 3B  show conventional analog buffers composed by a source follower with threshold voltage compensation and V gs  compensation respectively;  
         [0015]      FIG. 3C  is a timing chart of the conventional analog buffers shown in  FIGS. 3A and 3B .  
         [0016]      FIG. 4A  is a first embodiment of an analog buffer;  
         [0017]      FIG. 4B  is another aspect of the first embodiment of the analog buffer;  
         [0018]      FIG. 4C  is also another aspect of the first embodiment of the analog buffer;  
         [0019]      FIG. 4D  is still another aspect of the first embodiment of the analog buffer;  
         [0020]      FIG. 5  is a timing chart of the analog buffers according to the embodiments;  
         [0021]      FIG. 6A  is a second embodiment of an analog buffer;  
         [0022]      FIG. 6B  is another aspect of the second embodiment of the analog buffer;  
         [0023]      FIG. 6C  is also another aspect of the second embodiment of the analog buffer;  
         [0024]      FIG. 6D  is still another aspect of the second embodiment of the analog buffer;  
         [0025]      FIG. 7  shows the relationship between the input voltage and output voltage of the analog buffer according to simulation of the embodiment of  FIG. 4B ;  
         [0026]      FIG. 8  shows the relationship between the input voltage and DC offset voltage of the analog buffer according to simulation of the embodiment of  FIG. 4B ;  
         [0027]      FIG. 9  is a schematic diagram of a signal driving circuit according to various embodiments of the invention; and  
         [0028]      FIG. 10  schematically shows an electronic device deploying a driving circuit shown in  FIG. 9 . 
     
    
     DETAILED DESCRIPTION  
     FIRST EMBODIMENT  
       [0029]      FIG. 4A  is a first embodiment of an analog buffer in accordance with one aspect of the present invention. The analog buffer  100 A comprises a first source follower  10 A, a switching circuit  20 A, a second source follower  30 A, and a discharge circuit  40 A.  
         [0030]     As shown in  FIG. 4A , the first source follower  10 A is a P-type source follower coupled between the power voltages Vdd and Vee. The first source follower  10 A comprises two transistors M 1  and M 2 , three switching devices S 1 A, S 1 B and S 3 A, a capacitor C 1 , and a current source I 1 . The switching circuit  20 A is coupled between the first and second source followers  10 A and  30 A. The switching circuit  20 A comprises three switching devices S 3 B, S 3 C and S 4 A and a capacitor C 2 . The second source follower  30 A is an N-type source follower, coupled to the switching circuit  20 A. The second source follower  30 A comprises a transistor M 3 , a switching device S 2 , and a current source I 2 . The discharge circuit  40 A is coupled between the second source follower  30 A and a load comprising the resistor RL and the capacitor CL. In this embodiment, the current provided by the current source I 2  can be N times that provided by the current source I 1 , increasing driving capability. A controller  50  controls the switching of the various switches. The controller  50  may be in part of, or the switch control signals CS may be provided by, the timing controller  510 _found in the electronic device (see  FIG. 10 ).  
         [0031]      FIG. 5  is a timing chart of the analog buffer according to the first embodiment. In time interval t 0 -t 1 , all switches are turned off, except that the switching device S 5  in the discharge circuit  40 A is turned on such that the voltage Vout at the node N 3  from a preceding cycle is discharged to the power voltage Vee. In the subsequent time intervals, the various switches are controlled by the controller  50  to function in the manner as described below.  
         [0032]     In time interval t 1 -t 2 , the switching devices S 1 A and S 1 B are turned on such that a voltage is stored in the capacitor C 1  to turn on the transistor M 2 .  
         [0033]     In time interval t 2 -t 3 , the switching device S 5  is turned off. The switching devices S 1 A and S 1 B are turned off and the transistor M 2  is maintained on due to the voltage stored in the capacitor C 1 .  
         [0034]     In time interval t 3 -t 4 , the switching devices S 2 , S 3 A, S 3 B and S 3 C are turned on such that the first and second source followers  10 A and  30 A are both enabled. Accordingly, the first source follower  10 A regulates a voltage of Vin+|Vgsp| at the node N 1 . The node N 2  is then charged to the voltage of Vin+|Vgsp|, a voltage of |Vgsn| is stored in the capacitor C 2 . In this embodiment, the V gs  of the transistors M 1  and M 3  are made equal by adjusting M 1  and M 3  size, namely |Vgsp|=|Vgsn|.  
         [0035]     In time interval t 4 -t 5 , the switching devices S 3 A, S 3 B and S 3 C are turned off such that the first source follower  10 A is disabled to conserve power.  
         [0036]     In time interval t 5 -t 6 , the switching devices S 4 A and S 4 B are turned on and S 5  turned off such that the second source follower  30 A outputs a voltage Vout identical to the input voltage Vin to load according to the input voltage from the switching devices S 4 A and the voltage (|Vgsn|) stored capacitor C 2 . The output voltage Vout regulated by the transistor M 3  is identical to the input voltage Vin because the |Vgsn| of the transistor M 3  can be compensated by voltage stored in the capacitor C 2 .  
         [0037]     At time t 6 , the switching devices S 2 , S 4 A and S 4 B are turned off such that the second source follower  30 A is disabled to conserve power. The cycle above repeats from t 0  to t 6 , in accordance with the timing chart shown in  FIG. 5 .  
         [0038]      FIG. 4B  is a variation of the first embodiment of an analog buffer. The analog buffer  100 B shown in  FIG. 4B  is similar to the buffer  100 A in the  FIG. 4A , except that the current sources I 1  and I 2  are implemented by the transistors M 4  and M 5  controlled by Va, wherein the transistors M 4  and M 5  are biased by a bias voltage Va. Operations of the analog buffer  100 B shown in  FIG. 4B  are similar to those shown in  FIG. 4A , and thus, are omitted for simplification.  
         [0039]      FIG. 4C  is another variation of the first embodiment of an analog buffer. The analog buffer  100 C shown in  FIG. 4C  is similar to the buffer  100 B in the  FIG. 4B , except for a bias voltage providing circuit comprising two switching devices S 1 C and S 1 D, a capacitor C 3  and a current source I 3 . The switching devices S 1 C and S 1 D are also turned on in the time interval t 1 -t 2 , such that a bias voltage can be stored in the capacitor C 3  to bias the transistors M 4  and M 5 . Operations of the analog buffer  100 C shown in  FIG. 4C  are similar to those shown in  FIG. 4A , and thus, are omitted for simplification.  
         [0040]      FIG. 4D  is still another variation of the first embodiment of an analog buffer shown in  FIG. 4C . The analog buffer  100 D shown in  FIG. 4D  is similar to the buffer  100 C in the  FIG. 4C , except that the switching devices S 1 A, S 1 C, S 3 B, S 3 C, S 4 B and S 4 A are implemented by transmission gates, switching devices S 1 B, S 1 D, S 2 , S 3 A and S 5  are implemented by transistors, and the current source I 3  is implemented by a P-type transistor M 6  with a gate coupled to the power voltage Vss. Operations of the analog buffer  100 D shown in  FIG. 4D  are similar to those shown in  FIG. 4A , and thus, are omitted for simplification.  
       SECOND EMBODIMENT  
       [0041]      FIG. 6A  is a second embodiment of an analog buffer. The analog buffer  200 A comprises a first source follower  10 A′, a switching circuit  20 A′, a second source follower  30 A′, and a pre-charge circuit  40 A′. As shown in  FIG. 6A , unlike the first embodiment, the first source follower  10 A′ is an N-type source follower coupled between the power voltages Vdd and Vee. The second source follower  30 A′ is a P-type source follower, coupled to the switching circuit  20 A′.  
         [0042]     The first source follower  10 A′ comprises two transistors M 1  and M 2 , three switching devices S 1 A, S 1 B and S 3 A, a capacitor C 1 , and a current source I 1 . The switching circuit  20 A′ is coupled between the first and second source followers  10 A′ and  30 A′. The switching circuit  20  comprises three switching devices S 3 B, S 3 C and S 4 A and a capacitor C 2 . The second source follower  30 A′ is a P-type source follower, coupled to the switching circuit  20 A′. The second source follower  30 A′ comprises a transistor M 3 , a switching device S 2 , and a current source I 2 . The pre-charge circuit  40 A′ is coupled between the second source follower  30  and a load comprising the resistor RL and the capacitor CL. In this embodiment, the current provided by the current source I 2  can be N times that provided by the current source I 1 , for increased driving capability.  
         [0043]      FIG. 5  is also the timing chart of the analog buffer according to the second embodiment. In time interval t 0 -t 1 , the switching device S 5  in the charge circuit  40 A′ is turned on such that the voltage Vout at the node N 6  is charged to the power voltage Vdd.  
         [0044]     In time interval t 1 -t 2 , the switching devices S 1 A and S 1 B are turned on such that a voltage is stored in the capacitor C 1  to turn on the transistor M 2 .  
         [0045]     In time interval t 2 -t 3 , the switching device S 5  is turned off. The switching devices S 1 A and S 1 B are turned off and the transistor M 2  is maintained on due to the voltage stored in the capacitor C 1 .  
         [0046]     In time interval t 3 -t 4 , the switching devices S 2 , S 3 A, S 3 B and S 3 C are turned on such that the first and second source followers  10 A′ and  30 A′ are both enabled. Accordingly, the first source follower  10 A′ regulates a voltage of Vin−|Vgsn| at the node N 4 . The node N 5  is then charged to the voltage of Vin−|Vgsn| due to turning on of the switching device S 3 B, and a voltage of |Vgsp| is stored in the capacitor C 2 . In this embodiment, the V gs  of the transistors M 1  and M 3  are made equal by adjusting M 1  and M 3  size, namely |Vgsp|=|Vgsn|.  
         [0047]     In time interval t 4 -t 5 , the switching devices S 3 A, S 3 B and S 3 C are turned off such that the first source follower  10 A′ is disabled to conserve power.  
         [0048]     In time interval t 5 -t 6 , the switching devices S 4 A and S 4 B are turned on such that the second source follower  30 A′ outputs an output voltage Vout identical to the input voltage Vin to load according to the input voltage from the switching devices S 4 A and the voltage stored capacitor C 2 . The output voltage Vout regulated by the transistor M 3  is identical to the input voltage Vin because the |Vgsp| of the transistor M 3  can be compensated by voltage stored in the capacitor C 2 .  
         [0049]     At time t 6 , the switching devices S 2 , S 4 A and S 4 B are turned off such that the second source follower  30 A′ is disabled to conserve power.  
         [0050]      FIG. 6B  is a variation of the second embodiment of an analog buffer. The analog buffer  200 B shown in  FIG. 6B  is similar to the buffer  200 A in the  FIG. 6A , except that the current sources I 1  and I 2  are implemented by the transistors M 4  and M 5 , wherein the transistors M 4  and M 5  are biased by a bias voltage Va. Operations of the analog buffer  200 B shown in  FIG. 6B  are similar to those shown in  FIG. 6A , and thus, are omitted for simplification.  
         [0051]      FIG. 6C  is also another aspect of the second embodiment of an analog buffer. The analog buffer  200 C shown in  FIG. 6C  is similar to the buffer  200 B in the  FIG. 6B , except for a bias voltage providing circuit comprising two switching devices S 1 C and S 1 D, a capacitor C 3  and a current source I 3 . The switching devices S 1 C and S 1 D are also turned on in the time interval t 1 -t 2 , such that a bias voltage can be stored in the capacitor C 3 . Operations of the analog buffer  200 C shown in  FIG. 6C  are similar to those shown in  FIG. 6A , and thus, are omitted for simplification.  
         [0052]      FIG. 6D  is still another aspect of the first embodiment of an analog buffer. The analog buffer  200 D shown in  FIG. 6D  is similar to the buffer  600 C in the  FIG. 6C , except that the switching devices S 1 A, S 1 C, S 3 B, S 3 C, S 4 B and S 4 A are implemented by transmitting gates, S 1 B, S 1 D, S 2 , S 3 A and S 5  are implemented by transistors, and the current source I 3  is implemented by a N-type transistor with a gate coupled to the power voltage Vdd. Operations of the analog buffer  200 D shown in  FIG. 6D  are similar to those shown in  FIG. 6A , and thus, are omitted for simplification.  
         [0053]      FIG. 7  shows the relationship of the input voltage and output voltage of the analog buffer according to simulation of the embodiment of  FIG. 4B . As shown, output voltages of the analog buffer are extremely close to input voltage thereof.  FIG. 8  shows the relationship between the input voltage and DC offset voltage of the analog buffer according to simulation of the embodiment of  FIG. 4B . As shown in  FIG. 8 , the DC offset voltage of the analog buffers of the embodiments is less than 10 mV. In addition, reasonable driving capability is provided.  
         [0054]     Because the analog buffers of the embodiment of the invention require only a first source follower, a switching circuit, a second source follower and a discharge circuit, they have simpler circuit structure and small layout area than those with operational amplifiers. Further, in the embodiments, the first and second source followers are not turned on all the time, and thus, the analog buffers also converse power.  
         [0055]      FIG. 9  is a schematic diagram of a signal driving circuit  300  according to various embodiments of the invention. As shown in  FIG. 9 , signal driving circuit  300  can comprise shift registers  310 , a sampling circuit  320 , a latching circuit  330 , a digital-to-analog converter (DAC)  340 , and an output circuit  350  comprising analog buffers as shown in FIGS.  4 A˜ 4 D or  6 A˜ 6 D. The shift registers  310  have a plurality of stages equal in number to columns of pixels in a display panel (not shown). The sampling circuit  320  samples data on a data bus (not shown) synchronous with sampling pulses output successively from the shift registers  310 . The latch circuit  330  holds and latches the sampled data during a horizontal period, and the DAC  340  converts the latched data to analog signals. The output circuit  350  drives the columns of pixels in a display panel according to the analog signals from the digital-to-analog converter (DAC) circuit  340  and control signals from external controller.  
         [0056]      FIG. 10  schematically shows an electronic device  600  deploying a driving circuit  300  described above. The display panel  400  can be a liquid crystal display device. The electronic device  500  may be a portable device such as a PDA, notebook computer, tablet computer, cellular phone, or a display monitor device, etc. Generally, the electronic device  600  includes a housing  500 , a timing controller  510 , the display panel  400  and a driving circuit  300 , etc. Further, the timing controller  510  is operatively coupled to the signal driving circuit and provides controls signals to the driving circuit  300 . The driving circuit  300  is operatively coupled to the display panel  400  and provides analog voltage to drive the display panel  400 , and the display panel  400  displays images.  
         [0057]     While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.