Abstract:
A CMOS image sensor having two ASPs can reduce increasing design difficulty as arising from a pixel array becoming larger and larger. The image sensor includes a selection circuit for transmitting outputs of CDS circuits through four divided buses to reduce parasitic loading and achieve high-speed operation. Then, the selecting circuit transmits red and blue pixels to a first ASP, and transmits green pixels to a second ASP, so as to relax the specification requirements of the ASP.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a CMOS image sensor, and more particularly, to a CMOS image sensor having two analog signal processors (ASP) for high-speed operation. 
     2. Description of the Prior Art 
     Image sensors, which can convert optical images to electrical signals, are classified into complementary metal oxide semiconductor (CMOS) image sensors and charge-coupled device (CCD) image sensors. For CCD image sensors, electric charges are transmitted to and stored in capacitors arranged close together. For CMOS image sensors, pixel arrays are formed in a CMOS integrated circuit process, and electric charges are detected sequentially by switch operations. The CMOS image sensor has a benefit of low power consumption, and is generally used in mobile communications devices. 
     Please refer to  FIG. 1 .  FIG. 1  is a diagram of a CMOS image sensor according to the prior art. The CMOS image sensor includes a pixel array  11  having red pixels (R), green pixels (G), and blue pixels (B) arranged in a matrix. A plurality of correlation double sampling (CDS) circuits  12  is arranged under the pixel array  11 , and each CDS circuit is coupled to a corresponding column of the pixel array  11 . An analog signal processor (ASP)  13  is arranged on a side of the pixel array  11  for processing output signals of the plurality of CDS circuits  12 . 
     The CDS circuit  12  samples the reset signal and the data signal from each pixel, and transmits the signals to the ASP  13 . Then, the ASP  13  calculates the difference of the reset signal and the data signal, and amplifies the signal to obtain image data of the object. In the process of reading the image data, one row of the pixel array  11  transmits the image data to the corresponding CDS circuits  12 . Finally, the output data of the CDS circuit  12  controlled by the driver  14  is transmitted sequentially to the ASP  13 . 
     As mentioned above, in the CMOS image sensor according to the prior art, when the one row of the pixel array is selected, the reset signals and the data signals of the pixels of the row are stored in the corresponding CDS circuits, and then the data of the corresponding CDS circuits controlled by the driver is transmitted sequentially to the ASP. 
     When the pixel array has over a million pixels, the number of CDS circuits increases with the number of pixels in each row. Since the bus for transmitting the data to the ASP is coupled to a large number of CDS circuits, the parasitic impedances of the bus are increased. Thus, the CMOS image sensor cannot operate at a high speed. For high-speed operation, the CMOS image sensor has to be improved, especially the ASP of the CMOS image sensor. 
     SUMMARY OF THE INVENTION 
     The present invention provides a complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels; a plurality of correlation double sampling (CDS) circuits coupled to corresponding columns of the pixel array; a selection circuit comprising a plurality of input ends coupled to each CDS circuit of the plurality of CDS circuits respectively, a first output end, and a second output end; a first analog signal processor (ASP) coupled to the first output end of the selection circuit for processing data of the plurality of first pixels and the plurality of second pixels; and a second analog signal processor (ASP) coupled to the second output end of the selection circuit for processing data of the plurality of third pixels. 
     The present invention provides a complementary metal oxide semiconductor (CMOS) image sensor for high-speed operation comprising a pixel array comprising a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels; a switch circuit comprising a plurality of input ends coupled to corresponding columns of the pixel array, and a plurality of output ends; a plurality of correlation double sampling (CDS) circuits coupled to the plurality of output ends of the switch circuit respectively; an output circuit comprising a plurality of input ends coupled to each CDS circuit respectively, a first output end, and a second output end; a first analog signal processor (ASP) coupled to the first output end of the output circuit for processing data of the first pixels and the second pixels; and a second analog signal processor (ASP) coupled to the second output end of the output circuit for processing data of the third pixels. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a CMOS image sensor according to the prior art. 
         FIG. 2  is a diagram of a first embodiment of a CMOS image sensor according to the present invention. 
         FIG. 3  is a timing diagram of a selection circuit in  FIG. 2 . 
         FIG. 4  is a diagram of a second embodiment of a CMOS image sensor according to the present invention. 
         FIG. 5  is a diagram of a third embodiment of a CMOS image sensor according to the present invention. 
         FIG. 6  is a diagram of a fourth embodiment of a CMOS image sensor according to the present invention. 
         FIG. 7  is a diagram of a fifth embodiment of a CMOS image sensor according to the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 2 .  FIG. 2  is a diagram of a first embodiment of a complementary metal oxide semiconductor (CMOS) image sensor according to the present invention. The CMOS image sensor includes a pixel array  22 , a plurality of correlation double sampling (CDS) circuits  24 , a selection circuit  26 , a first analog signal processor (ASP)  28 , and a second ASP  30 . The pixel array  22  includes a plurality of first pixels R, a plurality of second pixels B, and a plurality of third pixels G. The plurality of third pixels G and the plurality of first pixels R are arranged alternately in odd rows of the pixel array  22 , and the plurality of second pixels B and the plurality of third pixels G are arranged alternately in even rows of the pixel array  22 . The plurality of CDS circuits  24  is coupled to corresponding columns of the pixel array  22  on the same side. The plurality of CDS circuits  24  can read data of one row of the pixel array  22  once. The CDS circuits basically include two groups of source followers. However, when outputting data, the CDS circuits have to drive all parasitic impedances of the internal switches because all of the output ends of the CDS circuit are in parallel. As the size of the pixel array  22  increases, for high-speed operation, large switches are used, but the parasitic impedance of the large switches will also limit the speed of the operation. Thus, a divided bus is utilized for reducing the parasitic impedance. In addition, the first pixels R, the second pixels B, and the third pixels G are arranged alternately in the pixel array  22 . To simplify signal processing, the first ASP  28  processes signals of the first pixels R and the second pixels B, and the second ASP  30  processes signals of the third pixels G. 
     Please refer to  FIG. 3 .  FIG. 3  is a timing diagram of the selection circuit  26  in  FIG. 2 . T( 2   n− 1) and T( 2   n ) represent the operation of the odd rows and the even rows of the pixel array  22 , respectively. The selection circuit  26  divides the plurality of CDS circuits  24  into several groups to implement the divided bus. The selection circuit  26  includes a plurality of input ends coupled to each CDS circuit  24 , respectively, and transmits the data of the plurality of CDS circuits  24  to the first ASP  28  or the second ASP  30 . The first ASP  28  processes the data of the first pixels R and the second pixels B, and the second ASP  30  processes the data of the third pixels G. The first output end and the second output end of the selection circuit  26  are coupled to the first ASP  28  and the second ASP  30 , respectively. The selection circuit  26  includes eight switches S 1 -S 8  to divide the plurality of CDS circuits  24  into four divided buses. The switches S 1  and S 2  are regarded as a first divided bus  51 , and are coupled to the 4n−3th CDS circuits. The switches S 3  and S 4  are regarded as a second divided bus  52  coupled to the 4n−2th CDS circuits. The switches S 5  and S 6  are regarded as a third divided bus  53  coupled to the 4n−1th CDS circuits. The switches S 7  and S 8  are regarded as the fourth divided bus  54  coupled to the 4nth CDS circuits. The factor n is a positive integer. If each internal switch of the CDS circuits is the same, the parasitic loading will be reduced to ¼, so as to speed up the operation. 
     The timing diagram of the switches S 1 -S 8  is shown in  FIG. 3 . When the plurality of CDS circuits  24  reads the data of the odd rows of the pixel array  22 , only the switches S 1 , S 4 , S 5 , and S 8  are turned on, so that the data of the first divided bus  51  and third divided bus  53  can be transmitted to the first ASP  28 , and the data of the second divided bus  52  and the fourth divided bus  54  can be transmitted to the second ASP  30 . When the plurality of CDS circuits  24  reads the data of the even rows of the pixel array  22 , only the switches S 2 , S 3 , S 6 , and S 7  are turned on, so that the data of the second divided bus  52  and fourth divided bus  54  can be transmitted to the first ASP  28 , and the data of the first divided bus  51  and third divided bus  53  can be transmitted to the second ASP  30 . As mentioned above, the third divided bus  53  and the first divided bus  51  can be combined into one path, and the fourth divided bus  54  and the second divided bus  52  can be combined into one path. However, the parasitic loading is reduced to ½ in the situation of two groups of divided busses, so the improvement is not as good. In the architecture of the CDS circuits  24 , the control signals of the divided busses  51 - 53  may overlap, but the divided busses can still operate normally, because each divided bus is independent of the other three divided busses. In addition, the switches S 1 , S 3 , S 5 , and S 7  can be turned off so as to use only the first ASP  28  for saving power consumption. 
     Please refer to  FIG. 4 .  FIG. 4  is a diagram of a second embodiment of a CMOS image sensor according to the present invention. In the second embodiment, the CMOS image sensor further includes a switch circuit  32  and an auxiliary CDS circuit  34 . In addition, the selection circuit  26  is replaced by an output circuit  36 . The switch circuit  32  is coupled between the pixel array  22  and the plurality of CDS circuits  24 . The auxiliary CDS circuit  34  is coupled between the switch circuit  32  and the output circuit  36 . The switch circuit  32  includes a first group of switches  33  and a second group of switches  35 . The first group of switches  33  couples the nth column of the pixel array  22  to the nth CDS circuit  24 , respectively. The second group of switches  35  couples the first column of the pixel array  22  to the auxiliary CDS circuit  34 , and couples the nth column of the pixel array  22  to the n−1th CDS circuit  24 . The factor n is a positive integer. The first group of switches  33  and the second group of switches  35  operate complementarily; that is, when one group of switches turns on, another group of switches turns off. The switch circuit  32  utilizes a shift method to transmit the data of the first pixels R, the second pixels B, and the third pixels G to the different CDS circuits  24 . For example, the pixel R in the second column of the odd row of the pixel array  22  is transmitted to the first CDS circuit  24 ; the pixel B in the first column of the even row of the pixel array  22  is transmitted to the first CDS circuit  24 ; the pixel G in the third column of the odd row of the pixel array  22  is transmitted to the second CDS circuit  24 ; the pixel G in the second column of the even row of the pixel array  22  is transmitted to the second CDS circuit  24 ; and the auxiliary CDS circuit  34  receives the pixel G in the first column of the odd row of the pixel array  22 . Thus, the output circuit  36  can output the data of the pixel array  22  to the first ASP  28  or the second ASP  30  directly without switches. 
     Please refer to  FIG. 5 .  FIG. 5  is a diagram of a third embodiment of a CMOS image sensor according to the present invention. The third embodiment does not use the auxiliary CDS circuit  34 , so the third embodiment has a different switch circuit  42  from the second embodiment. The switch circuit  42  includes a first group of switches  43  and a second group of switches  45 . The first group of switches  43  couples the mth column of the pixel array  22  to the mth CDS circuit  24 . The second group of switches  45  couples the 2n−1th column of the pixel array  22  to the 2nth CDS circuit  24 , and couples the 2nth column of the pixel array  22  to the 2n−1th CDS circuit. The factors m and n are positive integers. If the pixel array  22  has N columns, the factor m ranges from 1 to N, and the factor n ranges from 1 to N/2. Since the first pixels R, the second pixels B, and the third pixels G are arranged alternately in the pixel array  22 , the switch circuits  42  can transmit the data of the first pixels R, the second pixels B, and the third pixels G to the CDS circuits  24  alternately without the auxiliary CDS circuit  34 . 
     Please refer to  FIG. 6 .  FIG. 6  is a fourth embodiment of a CMOS image sensor according to the present invention. In the fourth embodiment, the CMOS image sensor includes a first group of CDS circuits  25   a  and a second group of CDS circuits  25   b , which are arranged on a same side of the pixel array  22 . Utilizing two groups of CDS circuits gives flexibility for arrangement, because the CDS circuits require a large area. The operation of the fourth embodiment is similar to the second embodiment, utilizing the shift method to transmit the data of the pixel array  22  to the CDS circuits. A switch circuit  32   a  has a first group of switches  33   a  and a second group of switches  35   a . For the odd row of the pixel array, when the second group of switches  35   a  turns on, the green pixels are transmitted to the second group of CDS circuits  25   b  and the red pixels are transmitted to the first group of CDS circuits  25   a . For the even row of the pixel array, when the first group of switches  33   a  turns on, the blue pixels are transmitted to the first group of CDS circuits  25   a  and the green pixels are transmitted to the second group of CDS circuits  25   b . Finally, the data of the first group of CDS circuits  25   a  are transmitted to the second ASP  30  through two divided buses, and the data of the second group of CDS circuits  25   a  are transmitted to the first ASP  28  through two divided buses. 
     Please refer to  FIG. 7 .  FIG. 7  is a diagram of a fifth embodiment of a CMOS image sensor according to the present invention. In comparison with the third embodiment, the CMOS image sensor includes a first group of CDS circuits  24   a  and a second group of CDS circuits  24   b , which are arranged on a same side of the pixel array  22 . In comparison with the fourth embodiment, the number of each group of CDS circuits  24   a  and  24   b  is one less than the number of each group of CDS circuits  25   a  and  25   b  of the fourth embodiment. For the odd row of the pixel array, when the first group of switches  43  turns on, the green pixels are transmitted to the first group of CDS circuits  24   a  and the red pixels are transmitted to the second group of CDS circuits  24   b . For the even row of the pixel array, when the second group of switches  45  turns on, the blue pixels are transmitted to the second group of CDS circuits  24   b  and the green pixels are transmitted to the first group of CDS circuits  24   a.    
     In summary, the CMOS image sensor according to the present invention includes two ASPs so as to reduce design difficulty due to the large size of the pixel array. In the first embodiment, the selection circuit transmits the red pixels and the blue pixels to the first ASP, and transmits the green pixels to the second ASP. In addition, the selection circuit utilizes four divided buses to output data of the plurality of CDS circuits, so as to reduce the parasitic loading and achieve high-speed operation. In the second embodiment and the third embodiment, the switch circuit is utilized to output the data of the red, blue, and green pixels of the pixel array to the separate CDS circuits. The switch circuit shifts the data of the pixel array to the CDS circuit with the auxiliary CDS circuit in the second embodiment. The switch circuit transmits the data of the pixel array alternately in the third embodiment. The switch circuit requires more switches than the selection circuit, but the requirements of the switches in the switch circuit are comparatively low, because the transmission speed from the pixel array is lower than transmission from the CDS circuits to the ASPs. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.