Abstract:
A semiconductor device is made by steps of removing portions of a first capping layer, removing portions of a sacrificial layer, recessing sidewalls, and forming fin structures. The step of removing portions of the first capping layer forms a first capping structure that covers portions of the sacrificial layer. The step of removing portions of the sacrificial layer removes portions of the sacrificial layer that are not covered by the first capping structure to define an intermediate structure. The step of recessing the sidewalls recesses sidewalls of the intermediate structure relative to edge regions of the first capping structure to form a sacrificial structure having recessed sidewalls. The step of forming fin structures forms fin structures adjacent to the recessed sidewalls.

Description:
RELATED APPLICATIONS 
     This application is related to U.S. patent application Ser. No. 11/678322, titled “Semiconductor Fin Integration Using a Sacrificial Fin,” filed on even date herewith, filed by the inventors hereof, and assigned to the assignee hereof, 
     BACKGROUND 
     1. Field 
     This disclosure relates generally to forming semiconductor fins for use in making semiconductor devices, and more specifically, to forming the semiconductor fins using a sacrificial fin. 
     2. Related Art 
     The use of semiconductor fins in making semiconductor devices provides advantages over planar semiconductor devices. Transistors having a fin for the channel can be made to have lower leakage and higher drive because the gate, being on two sides of the channel, has more control of the channel. One of the desires generally relevant to semiconductor devices, including those using semiconductor fins, is to increase the density; to increase the number of devices in a given area. In the case of semiconductor fins, the minimum fins spacing is lithographically limited. Transistors using fins, however, are not expected to fit all of the requirements of an integrated circuit design. Thus, one issue is integrating the fins with planar transistors while improving density. 
     Thus, there is a need to improve the density of semiconductor devices using fins while also having desirable electrical characteristics, and a further desire is to efficiently integrate semiconductor fins with planar transistors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
         FIG. 1  is a cross section of a semiconductor device at a stage in processing according to an embodiment of the invention; 
         FIG. 2  is a cross section of the semiconductor device of  FIG. 1  at a subsequent stage in processing; 
         FIG. 3  is a cross section of the semiconductor device of  FIG. 2  at a subsequent stage in processing; 
         FIG. 4  is a cross section of the semiconductor device of  FIG. 3  at a subsequent stage in processing; 
         FIG. 5  is a cross section of the semiconductor device of  FIG. 4  at a subsequent stage in processing; 
         FIG. 6  is a cross section of the semiconductor device of  FIG. 5  at a subsequent stage in processing; 
         FIG. 7  is a cross section of a semiconductor device at a stage in processing according to another embodiment of the invention; 
         FIG. 8  is a cross section of the semiconductor device of  FIG. 7  at a subsequent stage in processing; 
         FIG. 9  is a cross section of the semiconductor device of  FIG. 8  at a subsequent stage in processing; 
         FIG. 10  is a cross section of the semiconductor device of  FIG. 9  at a subsequent stage in processing; 
         FIG. 11  is a cross section of the semiconductor device of  FIG. 10  at a subsequent stage in processing; 
         FIG. 12  is a cross section of the semiconductor device of  FIG. 11  at a subsequent stage in processing; 
         FIG. 13  is a cross section of the semiconductor device of  FIG. 12  at a subsequent stage in processing; 
         FIG. 14  is a cross section of the semiconductor device of  FIG. 13  at a subsequent stage in processing; 
         FIG. 15  is a cross section of the semiconductor device of  FIG. 14  at a subsequent stage in processing; 
         FIG. 16  is a cross section of the semiconductor device of  FIG. 15  at a subsequent stage in processing; 
         FIG. 17  is a cross section of the semiconductor device of  FIG. 16  at a subsequent stage in processing; 
         FIG. 18  is a cross section of the semiconductor device of  FIG. 17  at a subsequent stage in processing; 
         FIG. 19  is a cross section of a semiconductor device at stage in processing for an alternative to a obtaining a semiconductor device similar to that of  FIG. 10 ; and 
         FIG. 20  is a cross section of the semiconductor device of  FIG. 19  at a subsequent stage in processing. 
     
    
    
     DETAILED DESCRIPTION 
     In one aspect, a sacrificial fin is formed of silicon germanium (SiGe) with an overlying nitride layer. The SiGe fin is trimmed to result in the silicon nitride (nitride) layer having an overhang extending past the sides of the SiGe fin. Epitaxial silicon is grown on the sides of the SiGe fin. During the growth, the nitride overhang functions to contain the silicon growth which has the affect of reducing or eliminating the occurrence of facets in the silicon growth. The reduction or elimination of facets provides for more control of the silicon width. The SiGe fin is removed leaving two silicon fins that are then used in transistor formation. This is better understood by reference to the drawings in the following description. 
     Shown in  FIG. 1  is semiconductor device  10  comprising a substrate  12 , an insulating layer  14 , a silicon germanium (SiGe) fin  16  over insulating layer  14 , and a capping layer  18  over SiGe fin  16 . Substrate  12  and insulating layer  14  and SiGe fin  16  may be formed from a semiconductor-on-insulator (SOI) substrate in which the overlying semiconductor layer is SiGe. Substrate  12  can be considered a handle wafer portion because it provides structural support. In this case SiGe fin  16  may be about 100 nanometers (nm) in height. Capping layer  18  and SiGe fin  16  arise from forming a SiGe layer over insulating layer  14  and another layer, preferably nitride in this example, over the SiGe layer. The nitride layer is patterned and the SiGe is then patterned as well. The width of SiGe fin  16  is preferably the smallest that can be achieved by the lithography that is available but could be another width. SiGe fin  16  is the length that is desired for the fin transistor to be formed in silicon using SiGe fin  16 . At the end of this length, not shown but conventional for fins, is a source/drain region that is also elevated at the same height as SiGe fin  16 . This source/drain is also covered with the nitride. 
     Shown in  FIG. 2  is semiconductor device  10  after trimming SiGe fin  16  which results in an overhang  20  where nitride layer  18  extends past the sides of trimmed SiGe fin  16 . Preferably the overhang is about a fourth of the width of SiGe fin  16  of  FIG. 1 . Thus for an overhang on both sides of SiGe fin  16 , trimming reduces the width in half to achieve the 25% overhang of overhang  20 . Trimming is a well known process for silicon gates. Trimming processes, such as those used for trimming polysilicon gates, may be used with the corresponding adjustment in chemistry to account for the trimming being of SiGe instead of silicon. One such method is to oxidize along the sides and remove the resulting oxide. Another is to apply an isotropic etch. 
     Shown in  FIG. 3  is semiconductor device  10  after epitaxially growing a silicon fin  22  on one sidewall of SiGe fin  16  and a silicon fin  24  on the other side of SiGe fin  16 . Silicon fins  22  and  24  have a width a little less than the amount of the overhang of overhang  20 . Thus, silicon fins  22  and  24  are less than 25% of the width of SiGe fin  16 . Thus about 20% of the width of SiGe fin  16  is achievable. The result is that for every sacrificial SiGe fin, there are two silicon fins. The width of sacrificial SiGe fin  16  is of a width to achieve the desired width and spacing of silicon fins  22  and  24 . The spacing of the SiGe fins is preferably the minimum spacing. Thus if the SiGe fins are at the minimum spacing or repeat distance, also commonly called minimum pitch, the density is doubled from what the minimum pitch would normally provide by having two silicon fins per sacrificial SiGe fin. 
     Shown in  FIG. 4  is semiconductor device  10  after removing capping layer  18  shown in  FIG. 3 . The portions of capping layer  18  over the SiGe source/drain regions, which are not shown in the FIGS. are not removed at this step. This has the affect of exposing SiGe fin  16 . 
     Shown in  FIG. 5  is semiconductor device  10  after removing SiGe fin  16 . This leaves silicon fins  22  and  24  standing alone. There are etch chemistries that are selective between SiGe and silicon. One such chemistry is thermal gaseous HCl. Other selective etches include plasma fluorine chemistries or peroxide wet etches. Capping layer  18  over the SiGe source/drain regions may be removed after removing SiGe fin  16 . 
     Shown in  FIG. 6  is semiconductor device  10  after forming a gate dielectric  26  on silicon fin  22 , a gate dielectric  28  on semiconductor fin  24 , and a polysilicon layer  30  on silicon fins  22  and  24 . Gate dielectric  26  and gate dielectric  28  in this example are thermal oxides which may be grown in a typical fashion for gate dielectrics. An alternative would be to provide a high k gate dielectric such as hafnium oxide. In such case the gate dielectric would be deposited and would then be on the surface of insulating layer  14 . Polysilicon layer  30  would be patterned and used as a gate. The view in  FIG. 6  is unchanged by patterning polysilicon layer  30 . 
     Thus it is seen that fins can be made using a sacrificial SiGe fin to grow sublithographic silicon fins. With the trimming of the SiGe fin, there is left an overhang of an overlying capping layer. The overhang of the overlying capping layer constrains the epitaxial silicon growth to occur in one direction only so that facets do not occur or at least are significantly reduced. Thus fins  22  and  24  have thicknesses that are substantially uniform and have a well controlled width. 
     Shown in  FIG. 7  is a semiconductor device  50  comprising a substrate  52  (handle wafer portion), an insulating layer  54  over substrate  52 , and a silicon layer  56  over the insulating layer. This is similar to a conventional SOI wafer except that silicon layer  56  is preferably thinner than the semiconductor layer on a conventional SOI wafer. For example, silicon layer  56  is preferably about 20 nm or even less. This can be achieved in a conventional SOI substrate by oxidizing the semiconductor surface of a conventional SOI substrate and then removing the oxide. The thickness can be quite thin because its purpose is as a seed layer. It may be thicker than the minimum but because it will be part of the channel, it should still be sufficiently thin to allow sufficient channel control, especially to avoid excessive off-state leakage. 
     Shown in  FIG. 8  is semiconductor device  50  after growing a SiGe layer  58  on silicon layer  56 . The height of SiGe layer  58  is the desired height of the fins that will be subsequently formed, which is about 100 nm but could be another height. This structure of semiconductor device  50  shown in  FIG. 8  may also be directly available commercially from a vendor who may make it by this or another process such as layer transfer. 
     Shown in  FIG. 9  is semiconductor device  50  after forming a capping layer  60 , preferably of oxide, over SiGe layer  58  and then removing a portion of SiGe layer  58  and capping layer  60 . The removed portion is from a region  62  for forming planar transistors and the remaining portion of SiGe layer  58  is in a region  64  for forming fin transistors (finFETs). Silicon layer  56  is exposed in region  62 . 
     Shown in  FIG. 10  is semiconductor device  50  after selectively growing epitaxial silicon on silicon layer  56  to form an epitaxial layer  66  that will function as the body for planar transistors and then removing capping layer  60 . Dotted line  68  shows the previous surface of silicon layer  56 . Line  68  is dotted because the demarcation of silicon layer  56  would unlikely to be discernible after performing the epitaxial growth to form epitaxial layer  66 . 
     Shown in  FIG. 11  is semiconductor device  50  after forming isolation regions  70  and  72  in epitaxial layer  66  and forming a capping layer  74 , preferably of nitride, over epitaxial layer  66 , isolation regions  70  and  72 , and SiGe layer  58 . Capping layer  74  is preferably about 20-50 nm in thickness. 
     Shown in  FIG. 12  is semiconductor device  50  after performing a patterned etch through capping layer  74 , SiGe layer  58 , and silicon layer  56 . This leaves a fin of SiGe similar to that of  FIG. 1  and the dimensions may be the same. A difference is that SiGe layer  58  is over a silicon layer, silicon layer  56 , whereas SiGe fin  16  is directly on an insulating layer. In this cross section of  FIG. 12 , only the fin portion of SiGe layer  58  is shown, but source/drain portions at the ends of the fin are present and covered by nitride layer  74 . 
     Shown in  FIG. 13  is semiconductor device  50  after trimming SiGe layer  58  and silicon layer  56 . The trimming is the same as for the trimming shown in  FIG. 2  except that both SiGe and silicon are being trimmed so if an isotropic etch is used, it preferably is not selective, or at least not significantly so, between silicon and SiGe. Capping layer  74  thus overhangs past the sides of trimmed SiGe layer and silicon layer  56  by an overhang  76 . The trimming is symmetrical so capping layer  74  overhangs on both sides. The trim also etches the side of epitaxial layer  66 . 
     Shown in  FIG. 14  is semiconductor device  50  after silicon fins  78  and  80  are selectively epitaxially grown on the sides of SiGe layer  58  and silicon layer  56 , and silicon fill  82  is simultaneously grown on the side of epitaxial layer  66 . These silicon fins  78  and  80  are formed the same as described for silicon fins  22  and  24  of  FIG. 3  except for the growth from silicon layer  56 . Thus, silicon fins  78  and  80  are formed at about 20% of the width of the SiGe layer  58  of  FIG. 12 . As described relative to  FIG. 3 , the result is that for every sacrificial SiGe fin, there are two silicon fins. The width of  58  sacrificial SiGe layer is of a width to achieve the desired width and spacing for silicon fins  78  and  80 . The spacing of the SiGe fins is preferably the minimum spacing. Thus if the SiGe fins are at the minimum spacing, also commonly called minimum pitch, the density is doubled from what the minimum pitch would normally provide by having two silicon fins per sacrificial SiGe fin. The lines between silicon layer  56  and silicon fins  78  and  80  are unlikely to be visible due to they are the same material and silicon fins  78  and  80  are epitaxially grown. 
     Shown in  FIG. 15  is semiconductor device  50  after removing capping layer  74  over the fin portion of SiGe layer  58 , which is in region  64 . The portions of capping layer  74  over region  62  and over the source/drain regions (not shown) are not removed at this time. 
     Shown in  FIG. 16  is semiconductor device  50  after removing the fin portion of SiGe layer  58 . The source/drain regions are not removed because they are still capped by capping layer  74 . The resulting structure has fins  78  and  80  with silicon layer  56  between them. The removing of SiGe is selective to silicon. An etch chemistry that is effective for this purpose is thermal gaseous HCl. Other selective etches include plasma fluorine chemistries or peroxide wet etches. Capping layer  74  over region  62  and over the source/drains is removed after the SiGe fin portion is removed. 
     Shown in  FIG. 17  is semiconductor device  50  after forming a gate dielectric  84  on epitaxial layer  66 , a gate dielectric layer  85  on the side of silicon fill  82 , a gate dielectric layer  86  on silicon fins  78  and  80  and silicon layer  56 , and a polysilicon layer  88  after forming gate dielectrics  84  and  86 . As shown gate dielectrics  84  and  86  are preferably thermally grown oxide. An alternative would be to use another type of gate dielectric such as a high k dielectric such as hafnium oxide. In such case the gate dielectric would be deposited over all of the surfaces shown in  FIG. 17  before the formation of polysilicon layer  88 . Polysilicon layer  88  could be replaced by another gate electrode material other than polysilicon or in addition to polysilicon. 
     Shown in  FIG. 18  is semiconductor device  50  after patterning polysilicon layer  88  and forming a transistor  96  in region  62  and a transistor  98  in region  64 . Transistor  96  is a planar transistor having a portion of polysilicon layer  88  as the gate, source/drains  92  and  94  in epitaxial layer  66 , and sidewall spacer  90  around the gate. 
     Thus it is seen that there is an integration on the same substrate of an integrated circuit of a planar transistor and a finFET. This shows that this integration may be achieved while using the overhang to achieve the reduced faceting while achieving sublithographic pitch by having two silicon fins per sacrificial fin with the sacrificial fins being at the minimum pitch. Also the height of the planar transistor above insulating layer  54  is substantially the same as the height of the finFET. This is beneficial for subsequent processing. 
     Shown in  FIG. 19  is a semiconductor device  100  comprising a substrate  102 , an insulating layer  104 , a silicon layer  106  that has been patterned, and a capping layer  108 . Silicon layer  106  has a region  110  for planar transistors and a region  112  for forming finFETs. Silicon layer  106  has a height in region  110  that is about the same as the desired fin height and a height that is sufficient to function as a seed for SiGe epitaxial growth in region  112 . This reduced height for silicon layer  106  in region  112  is achieved by a timed etch. 
     Shown in  FIG. 20  is semiconductor device  100  after epitaxially growing a SiGe layer  114  over silicon layer  106  in region  112  while capping layer  108  is present and then removing capping layer  108 . This achieves the structure of  FIG. 10 . The process continues as described for  FIGS. 11-18 . This shows there are multiple techniques available to achieve the structure of  FIG. 10 . 
     Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, different materials may be used than those described. For example, the sacrificial fin may be a different material than SiGe and the fins to be left remaining may be a different material than silicon. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. 
     Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. 
     Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.