Abstract:
A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

Description:
BACKGROUND OF THE INVENTION 
       [0001]    1. Field of the Invention 
         [0002]    The present invention relates to layer structures for mounting semiconductor devices and fabrication methods thereof, and more particularly, to a layer structure for mounting a semiconductor device and a fabrication method thereof so as to improve the product yield. 
         [0003]    2. Description of Related Art 
         [0004]    Currently, to achieve small-size and low-cost semiconductor products, a copper layer is formed on a carrier and an insulating layer is formed on the carrier to encapsulate the copper layer, and then the carrier is removed by etching so as to form a thin layer structure. 
         [0005]      FIGS. 1A to 1D  are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the prior art. 
         [0006]    Referring to  FIG. 1A , a first copper layer  11  is formed on a carrier  10  by electroplating. 
         [0007]    Referring to  FIG. 1B , a second copper layer  12  is formed on the first copper layer  11  by electroplating. 
         [0008]    Referring to  FIG. 1C , an insulating layer  13  is formed on the carrier  10  to encapsulate the first copper layer  11  and the second copper layer  12 , and a top surface  121  of the second copper layer  12  is exposed from the insulating layer  13 . 
         [0009]    Referring to  FIG. 1D , the carrier  10  is removed by etching to expose a bottom surface  111  of the first copper layer  11 , thereby forming a layer structure  1  for mounting a semiconductor device. 
         [0010]    However, during the etching process, the etching depth is difficult to control. Further, the first copper layer  11  and the second copper layer  12  generally have a small thickness so as for the layer structure  1  to be light and thin. As such, when the carrier  10  is removed by etching, the first copper layer  11  and the second copper layer  12  are easily damaged, thereby reducing the product yield. 
         [0011]    Therefore, there is a need to provide a layer structure for mounting a semiconductor device and a fabrication method thereof so as to overcome the above-described drawbacks. 
       SUMMARY OF THE INVENTION 
       [0012]    In view of the above-described drawbacks, the present invention provides a layer structure for mounting a semiconductor device, which comprises: a first encapsulant having a first bottom surface and a first top surface opposite to the first bottom surface; a plurality of first conductive elements embedded in the first encapsulant and each having a first end portion exposed from the first bottom surface of the first encapsulant; a circuit layer formed on the first end portions of the first conductive elements and having a first surface adjacent to the first conductive elements and a second surface opposite to the first surface; a plurality of second conductive elements formed on the second surface of the circuit layer so as to be electrically connected to the first conductive elements through the circuit layer; and a second encapsulant formed on the first bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, wherein the second encapsulant has a second top surface adjacent to the first encapsulant and a second bottom surface opposite to the second top surface. 
         [0013]    Each of the first conductive elements can have a second end portion exposed from the first top surface of the first encapsulant, and each of the second conductive elements can have a third end portion exposed from the second bottom surface of the second encapsulant. 
         [0014]    The layer structure can further comprise a chip mounted on the second bottom surface of the second encapsulant and electrically connected to the third end portions of the second conductive elements. 
         [0015]    The layer structure can further comprise a chip and/or a circuit board. The chip can be mounted on the first top surface of the first encapsulant and electrically connected to the second end portions of the first conductive elements, and the circuit board can be mounted on the second bottom surface of the second encapsulant and electrically connected to the third end portions of the second conductive elements. 
         [0016]    The circuit layer can have a thickness less than 300 um. The circuit layer can be made of gold, copper, iron, steel or copper-nickel-palladium alloy. 
         [0017]    The present invention further provides a fabrication method of a layer structure for mounting a semiconductor device, which comprises the steps of: providing a base material, wherein the base material comprises: a conductive layer having a first surface having a plurality of first conductive elements formed thereon and a second surface opposite to the first surface and having a plurality of second conductive elements formed thereon, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements and having a first bottom surface adjacent to the conductive layer and a first top surface opposite to the first bottom surface; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on the first bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, wherein the second encapsulant has a second top surface adjacent to the first encapsulant and a second bottom surface opposite to the second top surface. 
         [0018]    In the above-described method, fabrication of the base material can comprise: forming the first conductive elements on the first surface of the conductive layer; forming the first encapsulant on the first surface of the conductive layer for encapsulating the first conductive elements; and forming the second conductive elements on the second surface of the conductive layer. 
         [0019]    The method can further comprise thinning the first encapsulant from the first top surface to expose second end portions of the first conductive elements, and thinning the second encapsulant from the second bottom surface to expose third end portions of the second conductive elements. 
         [0020]    The method can further comprise mounting a chip on the second bottom surface of the second encapsulant and electrically connecting the chip and the third end portions of the second conductive elements. 
         [0021]    The method can further comprise: mounting a chip on the first top surface of the first encapsulant and electrically connecting the chip and the second end portions of the first conductive elements, and mounting a circuit board on the second bottom surface of the second encapsulant and electrically connecting the circuit board and the third end portions of the second conductive elements. 
         [0022]    The conductive layer can be a conductive film and have a thickness less than 300 um. The conductive layer can be made of gold, copper, iron, steel or copper-nickel-palladium alloy. 
         [0023]    The present invention mainly comprises forming a plurality of first and second conductive elements on first and second surfaces of a conductive layer, respectively, and forming a first encapsulant to encapsulate the first conductive elements and forming a second encapsulant to encapsulate the second conductive elements and a circuit layer formed from the conductive layer. 
         [0024]    Therefore, the present invention overcomes the conventional problem that the first and second copper layers are easily damaged during etching of the carrier. According to the present invention, the first and second conductive elements can be easily formed on the conductive layer so as to reduce the fabrication difficulty and increase the product yield. 
     
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         [0025]      FIGS. 1A to 1D  are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the prior art; 
           [0026]      FIGS. 2A to 2G  are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the present invention; and 
           [0027]      FIGS. 3 and 4  are schematic cross-sectional views showing other embodiments of the layer structure of the present invention. 
       
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
       [0028]    The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification. 
         [0029]    It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “top”, “bottom”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention. 
         [0030]      FIGS. 2A to 2G  are schematic cross-sectional views showing a layer structure for mounting a semiconductor device and a fabrication method thereof according to the present invention. 
         [0031]    Referring to  FIG. 2A , a conductive layer  20  having a first surface  20   a  and a second surface  20   b  opposite to the first surface  20   a  is provided. The conductive layer  20  can be a conductive film and have a thickness H less than 300 um. The conductive layer  20  can be made of, but not limited to, gold, copper, iron, steel, cold-pressed steel or copper-nickel-palladium alloy. 
         [0032]    Referring to  FIG. 2B , a plurality of first conductive elements  21  are formed on the first surface  20   a  of the conductive layer  20 . Each of the first conductive elements  21  has a first end portion  21   a  adjacent to the conductive layer  20  and a second end portion  21   b  opposite to the first end portion  21   a.    
         [0033]    Referring to  FIG. 2C , a first encapsulant  22  is formed on the first surface  20   a  of the conductive layer  20  for encapsulating the first conductive elements  21 . The first encapsulant  22  has a first bottom surface  22   a  adjacent to the conductive layer  20  and a first top surface  22   b  opposite to the first bottom surface  22   a.    
         [0034]    Referring to  FIG. 2D , a plurality of second conductive elements  23  are formed on the second surface  20   b  of the conductive layer  20 . Each of the second conductive elements  23  has a third end portion  23   a  and a fourth end portion  23   b  opposite to the third end portion  23   a  and adjacent to the conductive layer  20 . As such, the conductive layer  20 , the first conductive elements  21 , the first encapsulant  22  and the second conductive elements  23  constitute a base material  2   a.    
         [0035]    Referring to  FIG. 2E , the conductive layer  20  is patterned or partially removed by etching to form a circuit layer  20 ′ that electrically connects the first conductive elements  21  and the second conductive elements  23 . 
         [0036]    Referring to  FIG. 2F , a second encapsulant  24  is formed on the first bottom surface  22   a  of the first encapsulant  22  for encapsulating the circuit layer  20 ′ and the second conductive elements  23 . The second encapsulant  24  has a second top surface  24   b  adjacent to the first encapsulant  22  and a second bottom surface  24   a  opposite to the second top surface  24   b.    
         [0037]    Referring to  FIG. 20 , The first encapsulant  22  is thinned from the first top surface  22   b  by such as grinding so as to expose the second end portions  21   b  of the first conductive elements  21 . Further, the second encapsulant  24  can be thinned from the second bottom surface  24   a  so as to expose the third end portions  23   a  of the second conductive elements  23 . As such, a layer structure  2   b  for mounting a semiconductor device is formed. 
         [0038]    The present invention further provides a layer structure  2   b  for mounting a semiconductor device. Referring to  FIG. 20 , the layer structure  2   b  has: a first encapsulant  22  having a first bottom surface  22   a  and a first top surface  22   b  opposite to the first bottom surface  22   a;  a plurality of first conductive elements  21  embedded in the first encapsulant  22  and each having a first end portion  21   a  exposed from the first bottom surface  22   a  of the first encapsulant  22 ; a circuit layer  20 ′ formed on the first end portions  21   a  of the first conductive elements  21  and having a first surface  20   a  adjacent to the first conductive elements  21  and a second surface  20   b  opposite to the first surface  20   a;  a plurality of second conductive elements  23  formed on the second surface  20   b  of the circuit layer  20 ′ so as to be electrically connected to the first conductive elements  21  through the circuit layer  20 ′; and a second encapsulant  24  formed on the first bottom surface  22   a  of the first encapsulant  22  for encapsulating the circuit layer  20 ′ and the second conductive elements  23 , wherein the second encapsulant  24  has a second top surface  24   b  adjacent to the first encapsulant  22  and a second bottom surface  24   a  opposite to the second top surface  24   b.    
         [0039]    Further, each of the first conductive elements  21  can have a second end portion  21   b  exposed from the first top surface  22   b  of the first encapsulant  22 . 
         [0040]    The circuit layer  20 ′ can further be formed on a portion of the first bottom surface  22   a  of the first encapsulant  22 . The circuit layer  20 ′ can have a thickness less than 300 um. The circuit layer  20 ′ can be made of gold, copper, iron, steel, cold-pressed steel or copper-nickel-palladium alloy. 
         [0041]    Further, each of the second conductive elements  23  can have a third end portion  23   a  exposed from the second bottom surface  24   a  of the second encapsulant  24 . 
         [0042]      FIGS. 3 and 4  are schematic cross-sectional views showing other embodiments of the layer structure of the present invention. 
         [0043]    Referring to  FIG. 3 , a singulation process is performed to the layer structure  2   b  of  FIG. 2G  and then a chip  25  is mounted on the second bottom surface  24   a  of the second encapsulant  24  and electrically connected to the third end portions  23   a  of the second conductive elements  23  through a plurality of first solder balls  26 , thereby forming a layer structure  2   c  for mounting a semiconductor device. 
         [0044]    In other words, the layer structure  2   c  of  FIG. 3  can have a chip  25  mounted on the second bottom surface  24   a  of the second encapsulant  24  and electrically connected to the third end portions  23   a  of the second conductive elements  23  through a plurality of first solder balls  26 . 
         [0045]    In another embodiment, referring to  FIG. 4 , a singulation process is performed to the layer structure  2   b  of  FIG. 2G  Then, a chip  25  can be mounted on the first top surface  22   b  of the first encapsulant  22  and electrically connected to the second end portions  21   b  of the first conductive elements  21  through a plurality of first solder balls  26 , and/or a circuit board  27  can be mounted on the second bottom surface  24   a  of the second encapsulant  24  and electrically connected to the third end portions  23   a  of the second conductive elements  23  through a plurality of second solder balls  28 . As such, a layer structure  2   d  for mounting a semiconductor device is formed. 
         [0046]    In other words, the layer structure  2   d  of  FIG. 4  can have a chip  25  and/or a circuit board  27 . The chip  25  can be mounted on the first top surface  22   b  of the first encapsulant  22  and electrically connected to the second end portions  21   b  of the first conductive elements  21 . The circuit board  27  can be mounted on the second bottom surface  24   a  of the second encapsulant  24  and electrically connected to the third end portions  23   a  of the second conductive elements  23 . 
         [0047]    The present invention mainly involves forming a plurality of first and second conductive elements on first and second surfaces of a conductive layer, respectively, and forming a first encapsulant to encapsulate the first conductive elements and forming a second encapsulant to encapsulate the second conductive elements and a circuit layer formed from the conductive layer. 
         [0048]    Therefore, the present invention overcomes the conventional problem that the first and second copper layers are easily damaged during etching of the carrier. According to the present invention, the first and second conductive elements can be easily formed on the conductive layer so as to reduce the fabrication difficulty and increase the product yield. 
         [0049]    The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.