Abstract:
A high voltage switch circuit includes a high voltage switch suitable for transferring a voltage of an input terminal to an output terminal in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for changing a swing level of a preliminary activation signal, and generating the activation signal and the inverted activation signal.

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
       [0001]    The present application claims priority of Korean Patent Application No. 10-2014-0046145, filed on Apr. 17, 2014, which is incorporated herein by reference in its entirety. 
       BACKGROUND 
       [0002]    1. Field 
         [0003]    Various exemplary embodiments of the present invention relate to a high voltage switch circuit which is used to transfer a high voltage. 
         [0004]    2. Description of the Related Art 
         [0005]    Nonvolatile memories retain data even though their power supply is interrupted. Among such nonvolatile memories, a floating gate type nonvolatile memory, which is currently prevalent, utilizes a floating gate that is disposed over and insulated from the channel region of a substrate. In particular, the nonvolatile memory utilizes the threshold voltage of a memory cell that depends on the amount of charge retained in the conductive band of the floating gate. 
         [0006]    A nonvolatile memory includes a memory cell array for storing data. The memory cell array has a plurality of memory blocks. Each memory block has a plurality of pages. Each page has a plurality of memory cells. The respective memory cells are classified into on-cells and off-cells according to their threshold voltage distributions. On-cells are erased cells, and off-cells are programmed cells. The nonvolatile memory performs an erase operation by the unit of a memory block, and performs a program or read operation by the unit of a page. 
         [0007]    The nonvolatile memory may store 1 or more-bits of data in a single memory cell. A memory cell that stores 1-bit data is referred to as a single level cell (SLC), and a memory cell that stores 2 or more bits of data is referred to as a multi-level cell (MLC). The single level cell has an erased state and a programmed state that are determined by its threshold voltage. The multi-level cell has an erased state and a plurality of programmed states that are determined by its threshold voltage. 
         [0008]    In a nonvolatile memory, which has multi-level cells, it is important to narrow the widths of threshold voltage distributions of programmed states, and thereby secure margin between the respective programmed states. Generally, 2-bit data or 3-bit data is stored in the multi-level memory cells of the nonvolatile memory. In this regard, by setting the voltage of an erased state and partial threshold voltages of a plurality of programmed states, to a negative level, the performance and the reliability of the nonvolatile memory having the multi-level cells may be improved. 
         [0009]    Meanwhile, the plurality of memory cells included in a block are connected with a plurality of global word lines through a plurality of switches. When the corresponding block is selected, the voltages of the plurality of global word lines are transferred to a plurality of local lines, which are connected with the plurality of memory cells, through a plurality of high voltage switches, and, when the corresponding block is not selected, the voltages of the plurality of global word lines are interrupted by the plurality of high voltage switches. Accordingly, there is demand for high voltage switches that reliably transfer high voltages of global word lines to local lines when a corresponding block is selected, and reliably interrupt the high voltages of global word lines when a corresponding block is not selected, and a control technology thereof. 
       SUMMARY 
       [0010]    Various embodiments are directed to a high voltage switch circuit capable of reliably transferring and interrupting a high voltage. In particular, various embodiments are directed to a high voltage switch circuit capable of reliably operating in a device that uses a low power supply voltage. 
         [0011]    In an embodiment, a high voltage switch circuit may include: a high voltage switch suitable for transferring a voltage of an input terminal to an output terminal in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for changing a swing level of a preliminary activation signal, and generating the activation signal and the inverted activation signal. The high voltage switch circuit may further include a second level shifter suitable for generating the activation signal and the inverted activation signal by changing a level of a preliminary activation signal. 
         [0012]    The first level shifter may generate the activation signal and the inverted activation signal, levels of which fall in a range from the ground voltage to a second high voltage, which is higher than the power supply voltage, and lower than the first high voltage, by changing the level of the preliminary activation signal to a range from a ground voltage to a power supply voltage. Also, the second level shifter may generate the discharge signal, a level of which falls in a range from a negative voltage to the power supply voltage, by changing the level of the preliminary activation signal to the range from the ground voltage to the power supply voltage. 
         [0013]    The high voltage switch may include a high voltage NMOS transistor, the first transistor may include a high voltage PMOS transistor, the second transistor may include a depletion high voltage NMOS transistor, the third transistor may include a depletion high voltage NMOS transistor, and the discharge transistor may include a high voltage NMOS transistor. 
         [0014]    In an embodiment, a nonvolatile memory may include: a cell block including a plurality of cells; a plurality of global lines; a plurality of high voltage switches suitable for transferring voltages of the plurality of global lines to a plurality of local lines in the cell block in response to a voltage of a control node; a first transistor suitable for electrically connecting a first node and the control node in response to an inverted activation signal; a second transistor suitable for supplying a first high voltage to the first node in response to an activation signal; a third transistor connected in parallel to the second transistor, and operable in response to the control node; a discharge transistor suitable for discharging the control node; and a first level shifter suitable for generating the activation signal and the inverted activation signal by changing a level of a preliminary activation signal. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]      FIG. 1  is a configuration diagram of a high voltage switch circuit in accordance with an embodiment. 
           [0016]      FIG. 2  is a configuration diagram of a high voltage switch circuit in accordance with an exemplary embodiment of the present invention. 
           [0017]      FIG. 3  is a configuration diagram of an example of a first level shifter shown in  FIG. 2 . 
           [0018]      FIG. 4  is a configuration diagram of an example of a second level shifter shown in  FIG. 2 . 
           [0019]      FIG. 5  is a configuration diagram of a nonvolatile memory in accordance with an exemplary embodiment of the present invention. 
       
    
    
     DETAILED DESCRIPTION 
       [0020]    Various embodiments will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention. 
         [0021]      FIG. 1  is a configuration diagram of a high voltage switch circuit in accordance with an embodiment. 
         [0022]    Referring to  FIG. 1 , the high voltage switch circuit may include a high voltage switch  101 , high voltage NMOS transistors  130  and  140 , a high voltage PMOS transistor  120 , a depletion high voltage NMOS transistor  110 , and a level shifter  150 . 
         [0023]    The high voltage switch  101  may control transmission of a voltage from an input terminal HVIN to an output terminal HVOUT in response to the voltage of a control node SW_GATE. The high voltage switch  101  may be configured by a high voltage NMOS transistor. 
         [0024]    The level shifter  150  may shift swing levels of a preliminary activation signal EN and an inverted preliminary activation signal EN_N, and may generate a precharge signal PRECH and a discharge signal DISCH. The preliminary activation signal EN and the inverted preliminary activation signal EN_N may swing from a ground voltage VSS (0V) to the level of a power supply voltage VCC (approximately 1.8V to approximately 2.3V), and the precharge signal PRECH and the discharge signal DISCH may swing from a negative voltage VNEG lower than the ground voltage VSS (approximately −0.1V to approximately −2.0V) to the level of the power supply voltage VCC. The preliminary activation signal EN may turn on or off the high voltage switch  101 . When the preliminary activation signal EN is activated, the high voltage switch  101  may be turned on. 
         [0025]    Operation of the high voltage switch  101  will be described below with reference to  FIG. 1 . 
         [0026]    Turning on the High Voltage Switch  101   
         [0027]    When the preliminary activation signal EN is activated, the level shifter  150  may activate the precharge signal PRECH to the level of the power supply voltage VCC, and may deactivate the discharge signal DISCH to the level of the negative voltage VNEG. As the high voltage NMOS transistor  130  is turned on by the activation of the precharge signal PRECH, the voltage of the control node SW_GATE may be precharged to VCC−Vth (a threshold voltage). Then, the depletion high voltage NMOS transistor  110  may be turned on by a positive feedback, and the high voltage PMOS transistor  120  may be turned on. As a consequence, a high voltage VPP (approximately 10V to approximately 30V) may be transferred to the control node SW_GATE, and the high voltage switch  101  may be turned on. 
         [0028]    Turning Off the High Voltage Switch  101   
         [0029]    When the preliminary activation signal EN is deactivated, the level shifter  150  may deactivate the precharge signal PRECH to the level of the negative voltage VNEG, and may activate the discharge signal DISCH to the level of the power supply voltage VCC. The high voltage NMOS transistor  140  may be turned on by the activation of the discharge signal DISCH, and the negative voltage VNEG may be transferred to the control node SW_GATE. As a result, the control node SW_GATE may become the level of the negative voltage VNEG, and the high voltage switch  101  may be turned off. 
         [0030]    For the high voltage switch circuit configured as shown in  FIG. 1  to operate reliably, it should be assumed that the level of the power supply voltage VCC is sufficiently high. If the level of the power supply voltage VCC is too low (for example, approximately to 1.5V or less), in the turn-on operation of the high voltage switch  101 , since the precharge level VCC−Vth of the control node SW_GATE becomes too low, it may be difficult for the high voltage VPP to be transferred to the control node SW_GATE by the positive feedback. Also, if the level of the power supply voltage VCC is low, in the turn-off operation of the high voltage switch  101 , since the high voltage PMOS transistor  120  is unlikely to be turned off, a situation may occur in which it is difficult for the high voltage switch  101  to be turned off. 
         [0031]    The high voltage transistors  101 ,  120 ,  130  and  140  may be designed to endure a high voltage. Such transistors may be implemented with a triple well structure. Meanwhile, the depletion high voltage transistor  110  may have a negative threshold voltage. The accompanying drawings show voltages VNEG, VCC and VSS applied to the bulk regions of the transistors. 
         [0032]      FIG. 2  is a configuration diagram of a high voltage switch circuit in accordance with an exemplary embodiment of the present invention. 
         [0033]    Referring to  FIG. 2 , the high voltage switch circuit may include a high voltage switch  201 , a first transistor  230 , a second transistor  210 , a third transistor  220 , a discharge transistor  240 , a first level shifter  250 , and a second level shifter  260 . 
         [0034]    The high voltage switch  201  may control transmission of a voltage from an input terminal HVIN to an output terminal HVOUT in response to the voltage of a control node SW_GATE. The high voltage switch  201  may be configured by a high voltage NMOS transistor. 
         [0035]    The first level shifter  250  may shift swing levels of a preliminary activation signal EN and an inverted preliminary activation signal EN_N, and may generate an activation signal ENH and an inverted activation signal ENH_N. The preliminary activation signal EN and the inverted preliminary activation signal EN_N may swing from a ground voltage VSS (0V) to the level of a power supply voltage VCC (approximately 1.8V to approximately 2.3V), and the activation signal ENH and the inverted activation signal ENH_N may swing from the ground voltage VSS to the level of a second high voltage VHV. When the preliminary activation signal EN is activated, the activation signal ENH may be activated, and, when the preliminary activation signal EN is deactivated, the inverted activation signal ENH_N may be activated. The second high voltage VHV may be higher than the power supply voltage VCC, and lower than a first high voltage VPP (approximately 10V to approximately 30V). For example, the second high voltage VHV may have a voltage level of approximately 4.5V. The preliminary activation signal EN may turn on or off the high voltage switch  201 . When the preliminary activation signal EN is activated, the high voltage switch  201  may be turned on. 
         [0036]    The second level shifter  260  may change the swing levels of the preliminary activation signal EN and the inverted preliminary activation signal EN_N, and may generate a precharge signal PRECH and a discharge signal DISCH. The preliminary activation signal EN and the inverted preliminary activation signal EN_N may swing from the ground voltage VSS to the level of the power supply voltage VCC, and the precharge signal PRECH and the discharge signal DISCH may swing from a negative voltage VNEG lower than the ground voltage VSS (approximately −0.1V to approximately −2.0V) to the level of the power supply voltage VCC. 
         [0037]    The first transistor  230  may electrically connect a first node A and the control node SW_GATE in response to the inverted activation signal ENH_N. The first transistor  230  may be a high voltage PMOS transistor. 
         [0038]    The second transistor  210  may supply the first high voltage VPP to the first node A in response to the activation signal ENH. The third transistor  220  may be connected in parallel to the second transistor  210 , and may be controlled by the control node SW_GATE. Each of the second transistor  210  and the third transistor  220  may be a depletion high voltage NMOS transistor, which has a negative threshold voltage (Vth). 
         [0039]    The discharge transistor  240  may discharge the control node SW_GATE in response to the discharge signal DISCH. The discharge transistor  240  may be a high voltage NMOS transistor. 
         [0040]    Operation of the high voltage switch  201  will be described below with reference to  FIG. 2 . 
         [0041]    Turning on the High Voltage Switch  201   
         [0042]    When the preliminary activation signal EN is activated, the first level shifter  250  may activate the activation signal ENH to the level of the second high voltage VHV, and may deactivate the inverted activation signal ENH_N to the level of the ground voltage VSS. Further, the second level shifter  260  may deactivate the discharge signal DISCH to the level of the negative voltage VNEG. The second transistor  210  may be turned on by the activation of the activation signal ENH, and the first transistor  230  may be turned on by the deactivation of the inverted activation signal ENH_N. Then, the voltage of the control node SW_GATE may rise to the level of the first high voltage VPP, and therefore, the high voltage switch  201  may be turned on. Meanwhile, as the voltage of the control node SW_GATE serves as a positive feedback, the third transistor  220  may be turned on as well. 
         [0043]    Turning Off the High Voltage Switch  201   
         [0044]    When the preliminary activation signal EN is deactivated, the first level shifter  250  may deactivate the activation signal ENH to the level of the ground voltage VSS, and may activate the inverted activation signal ENH_N to the level of the second high voltage VHV. Further, the second level shifter  260  may activate the discharge signal DISCH to the level of the power supply voltage VCC. The discharge transistor  240  may be turned on by the activation of the discharge signal DISCH, and the voltage of the control node SW_GATE may fall to the level of the negative voltage VNEG, by which the high voltage switch  201  may be turned off. At this time, the transistors  210 ,  220  and  230  may be turned off. 
         [0045]    In accordance with an exemplary embodiment of the present invention, the power supply voltage VCC may not be involved in turning on and off of the transistors  210 ,  220  and  230  of the high voltage switch circuit configured as shown in  FIG. 2 , and therefore the high voltage switch  201  may be reliably turned on and off even though the level of the power supply voltage VCC falls. Also, the control node SW_GATE may rise directly to the level of the first high voltage VPP without precharge of the control node SW_GATE, and therefore the high voltage switch  201  may be quickly turned on without the element, for example, the high voltage NMOS transistors  130  described with reference to  FIG. 1  for the precharge of the control node SW_GATE. 
         [0046]      FIG. 3  is a configuration diagram of an example of the first level shifter  250  shown in  FIG. 2 . 
         [0047]    Referring to  FIG. 3 , the first level shifter  250  may include a first NMOS transistor N 1 , which pull-down drives the activation signal ENH in response to the inverted preliminary activation signal EN_N, a second NMOS transistor N 2 , which pull-down drives the inverted activation signal ENH_N in response to the preliminary activation signal EN, a first PMOS transistor P 1 , which drives the activation signal ENH to the level of the second high voltage VHV in response to the inverted activation signal ENH_N, and a second PMOS transistor P 2 , which drives the inverted activation signal ENH_N to the level of the second high voltage VHV in response to the activation signal ENH. 
         [0048]    Operations of the first level shifter  250  may be simply represented as in the following Table 1. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 1 
               
               
                   
                   
               
               
                   
                 IN 
                 OUT 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 EN 
                 EN _N 
                 ENH 
                 ENH _N 
               
               
                   
                 VCC 
                 VSS 
                 VHV 
                 VSS 
               
               
                   
                 VSS 
                 VCC 
                 VSS 
                 VHV 
               
               
                   
                   
               
             
          
         
       
     
         [0049]      FIG. 4  is a configuration diagram of an example of the second level shifter  260  shown in  FIG. 2 . 
         [0050]    Referring to  FIG. 4 , the second level shifter  260  may include a third NMOS transistor N 3 , which drives the precharge signal PRECH to the level of the negative voltage VNEG in response to the discharge signal DISCH, a fourth NMOS transistor N 4 , which drives the discharge signal DISCH to the level of the negative voltage VNEG in response to the precharge signal PRECH, a third PMOS transistor P 3 , which pull-up drives the precharge signal PRECH in response to the inverted preliminary activation signal EN_N, and a fourth PMOS transistor P 4  which pull-up drives the discharge signal DISCH in response to the preliminary activation signal EN. 
         [0051]    Operations of the second level shifter  260  may be simply represented as in the following Table 2. 
         [0000]    
       
         
               
               
               
             
               
               
               
               
               
             
           
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 IN 
                 OUT 
               
               
                   
                   
               
             
             
               
                   
               
             
          
           
               
                   
                 EN 
                 EN_N 
                 PRECH 
                 DISCH 
               
               
                   
                 VCC 
                 VSS 
                 VCC 
                 VNEG 
               
               
                   
                 VSS 
                 VCC 
                 VNEG 
                 VCC 
               
               
                   
                   
               
             
          
         
       
     
         [0052]      FIG. 5  is a configuration diagram of a nonvolatile memory in accordance with an exemplary embodiment of the present invention.  FIG. 5  shows the nonvolatile memory having the high voltage switch circuit described with reference to  FIG. 2  as an example. 
         [0053]    Referring to  FIG. 5 , the nonvolatile memory may include a cell block  510 , which includes a plurality of memory cells MC&lt; 0 :N&gt;, a drain select transistor DST, and a source select transistor SST, a plurality of high voltage switches  201 &lt; 0 :K&gt; for transferring the voltages of a plurality of global lines GWL&lt; 0 :N&gt;, GDSL and GSSL to a plurality of local lines WL&lt; 0 :N&gt;, DSL and SSL in the cell block  510 , and a block address decoder  520 . The nonvolatile memory may further include the high voltage switch circuit described with reference to  FIG. 2  for controlling the turn-on and the turn-off of the plurality of high voltage switches  201 &lt; 0 :K&gt;. 
         [0054]    The block address decoder  520  may decode an address ADD, and activate a preliminary activation signal EN when the cell block  510  is selected to be accessed, that is, selection is made such that a read or program operation is performed in the cell block  510 . When the preliminary activation signal EN is activated, as described above, the voltage level of a control node SW_GATE may become capable of turning on the high voltage switches  201 &lt; 0 :K&gt;. As a consequence, the high voltage switches  201 &lt; 0 :K&gt; may be turned on, and the voltage levels of the global lines GWL&lt; 0 :N&gt;, GDSL and GSSL may be transferred to the local lines WL&lt; 0 :N&gt;, DSL and SSL. When the preliminary activation signal EN is deactivated, the high voltage switches  201 &lt; 0 :K&gt; are turned off, and the voltage levels of the global lines GWL&lt; 0 :N&gt;, GDSL and GSSL may be interrupted so they are not transferred to the local lines WL&lt; 0 :N&gt;, DSL and SSL. 
         [0055]    As is apparent from the above descriptions, according to the embodiments, a high voltage switch circuit may reliably transfer and interrupt a high voltage. As a consequence, the high voltage switch circuit may reliably operate in a device that uses a low power supply voltage. 
         [0056]    Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.