Abstract:
Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.

Description:
BACKGROUND OF THE INVENTION 
     (1) Field of the Invention 
     This invention relates to gate drive voltage for magnetic memory technologies, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, cells which require programming currents higher than the minimum cell transistor can provide without degrading the life of the cell transistor. More particularly the invention relates to circuits and methods for programming these cell transistors by applying high voltages between the gate and source or drain of the cell transistor only to those cell transistors into which a one or zero is being written. 
     (2) Description of Related Art 
     U.S. Pat. No. 7,046,547 B2 and U.S. Pat. No. 6,961,265 B2 to Witcraft et al. describe methods and apparatus that allow data to be stored in a magnetic memory cell, such as a giant magneto-resistance cell. The inventions describe advantageously winding a word line around a magnetic memory cell to increase the magnetic field induced by the word line. 
     U.S. Pat. No. 6,985,382 B2 to Fulkerson et al. describe a technique to read a stored state in a magneto-resistive random access memory device, MRAM, such as a giant magneto-resistance MRAM device or a tunneling magneto-resistance device, TMR. The technique uses a bit line that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. 
     U.S. Pat. No. 6,754,055 B2 to Ono et al. describes a giant magneto-resistive effect element which includes a laminated layer film having a ferromagnetic film, a non-magnetic film, and an anti-ferromagnetic film. 
     U.S. Pat. No. 6,714,390 B2 describes a giant magneto-resistive effect element capable of producing a high output and a high resistance and which can cope with a high recording density and a magneto-resistive effect type head, a thin film magnetic memory, and a thin film magnetic sensor each of which includes this giant magneto-resistive effect element. 
     SUMMARY OF THE INVENTION 
     Magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, require high programming currents. Since these currents are controlled by a cell transistor, which is a field effect transistor, a high voltage between the source and/or drain is required to produce sufficient memory cell current to program the memory cells. This high gate to source/drain voltage and high memory cell current can significantly reduce the life of the cell transistor. 
     It is a principal objective of this invention to provide a circuit which can write information into individual memory cells, a one or a zero, while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. 
     It is another principal objective of this invention to provide a method of writing information into individual memory cells, a one or a zero, while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. 
     These objectives are achieved by methods and circuits which apply the high gate to drain voltage, or gate to source voltage only to those cells in which a 1 or a 0 is to be written so that only these cells see the high gate to source/drain voltage stress. Since these cell transistors see the high stress only when that cell is written the reliability of the cell transistors is not significantly degraded. 
     The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a schematic diagram of the circuit of this invention. 
         FIG. 2  shows a schematic diagram of a 2×2 section of the memory array. 
         FIGS. 3A and 3B  show a schematic diagram of circuits used to produce data line voltages for the circuit of this invention. 
         FIG. 4  shows a timing diagram of the voltages used to write a 0 into cell  000  and a 1 into cell  001 . 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Refer now to the Drawings for a description of the preferred embodiments of this invention.  FIG. 1  shows one section, section  0 , of a magnetic memory comprising an n column by m row array of magnetic memory cells  000 ,  001 , . . . ,  00   n ,  010 ,  011 , . . . ,  01   n ,  0   m   0 ,  0   m , . . .  0   mn .  FIG. 1  also shows the beginning of another section, section  1 , of the magnetic memory showing magnetic memory cells  110 ,  111 , . . . ,  1   m   0 . This description will describe the example of section  0 , as those skilled in the art will readily understand how the invention is applied to other sections as they are selected.  FIG. 2  shows a schematic diagram of memory cells  000 ,  001 ,  010 , and  011  showing each memory cell having a cell transistor  30  and a magnetic memory element  32  with one terminal of the magnetic memory element  32  connected to one of the source/drain terminals of the cell transistor  30 . In  FIG. 2  this node between the cell transistor  30  and magnetic memory element  32  is designated by the reference number DR 0  in cell  000  and the reference number S 1  in cell  001  because the following example will describe writing a 0 in cell  000 , where this node is a drain, and a 1 in cell  001 , where this node is a source. Whether the source/drain terminals of the cell transistor are considered a source or a drain depends on the direction of the current through the cell transistor. All transistors in this description are field effect transistors. 
     Refer again to  FIG. 1  which shows that each memory cell has a BLC line; BLC 0 , BLC 1 , . . . BLC N ; and a BLT line; BLT 0 , BLT 1 , . . . BLT N . Each of the BLC and BLT lines are connected through a bit line transistor  12  to a data line, the BLC 0  line to the DLC 0  line, the BLC 1  line to the DLC 1  line, the BLT 0  line to the DLT 0 , the BLT 1  line to the DLT 1  line and so forth with the BLC N  line connected to the DLC N  line and the BLT N  line connected to the DLT N  line. The gates of the bit line transistors  12  in the first section are all connected together to bit line signal source y 0  so that all of the bit line transistors  12  in this section are turned on or off at the same time. This allows a particular voltage to be supplied to each of the BLC and BLT lines independently by the data lines DLC 0 , DLT 0 , DLC 1 , DLT 1 , . . . , DLC N , and DLT N . The data lines provide a supply of selected voltages to the BLT and BLC lines. The signal source y 0  also allows the enhanced voltage level, V WL , to be applied to selected rows of section  0  of the memory when desired. The gates of the bit line transistors  13  in the second section are also all connected together to bit line signal source y 1  so that all of the bit line transistors  13  in this section are turned on or off at the same time. The signal source y 1  prevents voltage from being applied to the BLT and BLC lines in section  1  of the memory and prevents the enhanced voltage level, V WL , to be applied to any rows of section  1  of the memory while section  0 , or other sections of the memory, are being written. The memory may have other sections which are connected and operated in similar fashion. This invention will be described with reference to section one only, however those skilled in the art will recognize that the invention can be applied to other sections in similar fashion. 
     The voltages on the DLC lines are supplied by first data line drivers  18  and the voltages on the DLT lines are supplied by second data line drivers  20 . The voltages to the first data line drivers  18  are supplied by V1L and V0H voltage supplies and the inverse data line signals D 0   1 , D 1   1 , . . . , DN 1 . The voltages to the second data line drivers  20  are supplied by V1H and V0L voltage supplies and the data line signals D 0 , D 1 , . . . , DN. The first data line drivers  18  are shown in  FIG. 3A  where an inverse data line signal for memory cell N, DN 1 , switches the output DLC N  signal for memory line N between V0H and V1L. The second data line drivers  20  are shown in  FIG. 3B  where a data line signal for memory cell N, DN, switches the output DLT N  signal for memory line N between V1H and V0L. 
     The word lines WL 00 , WL 10 , . . . , WLm 0  and the global word lines GWL 0 , GWL 1 , . . . , GWLm are driven by row decoders  14 . The word lines WL 00 , WL 10 , . . . , WLm 0  are also driven by high voltage word line segment drivers  16  which can supply a higher voltage V WL  to a selected word line during the writing operation which will be described next. 
     Refer now to  FIGS. 2 and 4  for description of the circuit and method of this invention for writing a 1 and/or a 0 into magnetic memory elements. This example will show simultaneously writing a 0 in cell  000  and a 1 into cell  001 .  FIG. 2  shows a smaller section of the memory array showing memory cells  000 ,  001 ,  010 , and  011 . Writing a 0 in a cell requires causing a current to flow from the magnetic memory element  32  into the cell transistor  30 . Writing a 1 in a cell requires causing a current to flow from the cell transistor  30  into the magnetic memory element  32 . The magnetic memory element  32  can be approximated as a resistor and this approximation will be used in this example. In this example, the current required to write a 0 in a magnetic memory element  32  causes a voltage drop of about 0.4 volts across the magnetic memory element  32 . In this example, the current required to write a 1 in a magnetic memory element  32  also causes a voltage drop of about 0.4 volts across the magnetic memory element  32 . 
       FIG. 4  shows a timing diagram for the example of simultaneously writing a 0 in cell  000  and a 1 in cell  001 . As shown in  FIG. 4  in the interval between T1 and T2 data line DLT 0  goes from 0 volts to 0.4 volts, data line DLC 0  goes from 0 volts to 1.0 volts, data line DLT 1  goes from 0 volts to 0.6 volts, and data line DLC 1  remains at 0 volts. Also in the interval between T1 and T2 the signal y 0  to the bit line transistors  12  remains low so that the bit line transistors  12  are turned off, bit line BLT 0 , bit line BLC 0 , bit line BLT 1 , and bit line BLC 1  remain at 0 volts. Also between T1 and T2 the node between the cell transistor  30  and the magnetic memory element  32  in cell  000 , designated here as node DR 0  since it is connected to the cell transistor terminal acting as a drain in this case, the node between the cell transistor  30  and the magnetic memory element  32  in cell  001 , designated here as node S 1  since it is connected to the cell transistor terminal acting as a source in this case; and the word line WL 00  connected to the cell transistors  30  in the row in which cells  000  and  001  are located remain at 0 volts. 
     In the interval between T2 and T3 data line DLT 0  remains at 0.4 volts, data line DLC 0  remains at 1.0 volts, data line DLT 1  remains at 0.6 volts, and data line DLC 1  remains at 0 volts. Also in the interval between T2 and T3 the signal y 0  to the bit line transistors  12  becomes high so that the bit line transistors  12  are turned on, bit line BLT 0  goes to 0.4 volts, bit line BLC 0  goes to 1.0 volts, bit line BLT 1  goes to 0.6 volts, bit line BLC 1  and word line WL 00  remain at 0 volts. Since the word line WL 00  voltage remains at 0 volts the cell transistors  30  in cells  000  and  001  remain turned off so that the voltage of the D 0  node goes to 1.0 volts, because of the voltage of the BLC 0  line, and the voltage of the S 1  node remains at 0 volts, because of the voltage of the BLC 1  line. 
     In the interval between T3 and T4 data line DLT 0  remains at 0.4 volts, data line DLC 0  remains at 1.0 volts, data line DLT 1  remains at 0.6 volts, data line DLC 1  remains at 0 volts, the signal y 0  to the bit line transistors  12  remains high so that the bit line transistors  12  remain turned on, bit line BLT 0  remains at 0.4 volts, bit line BLC 0  remains at 1.0 volts, bit line BLT 1  remains at 0.6 volts, and bit line BLC 1  remains at 0 volts. In the interval between T3 and T4 the word line WL 00  voltage goes to 2.2 volts which allows the cell transistors  30  in cells  000  and  001  to pass sufficient current to write a 0 in cell  000  and a 1 in cell  001 . With the cell transistor  30  in cell  000  passing sufficient current to write a 0 in cell  000  and a 1 in cell  001  the voltage drop across the magnetic memory element in these cells is 0.4 volts reducing the voltage at the DR 0  node in cell  000  to 0.6 volts and raising the voltage at the S 1  node in cell  001  to 0.4 volts. 
     During the writing of a 0 in cell  000  and a 1 in cell  001  the worst case voltage stress between the gate, at 2.2 volts, and the source/drain terminals of the cell transistor in cells  000  and  001  is 1.8 volts, since the BLT 0  node is at 0.4 volts in cell  000  and the S 1  node is at 0.4 volts in cell  001 . The high voltage of 2.2 volts is only applied to one row of the cells in the section being written and the same worst case voltage applies whether a 1 or a 0 is being written in a cell in that row. After T 4  the voltages revert to the beginning levels and a new cycle can begin. 
     During this write cycle the signal y 1  to the bit line transistors  13  in section  1  of the memory as well as the signals to the other bit line transistors in other sections of the memory, not shown, remains low so that these bit line transistors remain turned off. The high voltage is restricted to that section by signals to the corresponding bit line transistors, such as the signal y 1  to the bit line transistors  13  in that part of the next section of the memory shown in  FIG. 1  and to the global word lines GLW 0 , GLW 1 , . . . , GLWm. Similar signals are applied to those bit line transistors and global word lines not shown in  FIG. 1 . Memory cells  100 ,  110 , . . . ,  1   m   0  are also shown in  FIG. 1 . 
     The voltages described here are for a particular example and different voltages could be used to achieve the same effect. 
     While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.