Abstract:
A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The memory further includes a resistive power supply, a sensor, and a controller which cooperates with the power supply. The power supply applies a source voltage to the sources of the cells that can have a maximum value. An erase pulse is applied to the cells during which the power supply is configured to allow the source voltage to clamp to the maximum value. A monitoring pulse is then applied to the cells during which the power supply is configured to prevent the source voltage from clamping to the maximum value. The sensor senses the source voltage while the monitoring pulse is applied. As the source voltage is not clamped, it is substantially a function of band-to-band tunneling current and accurately indicates the average state of erasure of the cells. The power supply includes a resistance and/or a current source which can be varied to reduce the source current while the monitoring pulse is being applied and thereby avoid clamping.

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a method for monitoring a state of erasure of a flash Electrically Erasable Programmable Read-Only Memory (EEPROM). 
     2. Description of the Related Art 
     A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block. 
     A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. 
     The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration. 
     A cell is programmed by applying, typically, 9 V to the control gate, 5 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 4 V. 
     The cell is read by applying typically 5 V to the control gate, 1 V to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 V), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 V), the control gate voltage will enhance the channel, and the bitline current will be relatively high. 
     A cell can be erased in several ways. In one arrangement, a cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, a cell can be erased by applying a negative voltage on the order of -10 V to the control gate, applying 5 V to the source and allowing the drain to float. 
     A problem with the conventional flash EEPROM cell arrangement is that due to manufacturing tolerances, some cells become over-erased before other cells become erased sufficiently. The floating gates of the over-erased cells are depleted of electrons and become positively charged. This causes the over-erased cells to function as depletion mode transistors which cannot be turned off by normal operating voltages applied to their control gates, and introduces leakage during subsequent program and read operations. 
     More specifically, during program and read operations only one wordline which is connected to the control gates of a row of cells is held high at a time, while the other wordlines are grounded. However, a positive voltage is applied to the drains of all of the cells. If the threshold voltage of an unselected cell is zero or negative, leakage current will flow through the source, channel and drain of the cell. 
     This undesirable effect is illustrated in FIG. 1. The drains of a column of floating gate cell transistors T 0  to T m  are connected to a bitline BL, which is itself connected to a bitline driver 1. The sources of the transistors T 0  to T m  are typically connected to ground. One of the transistors T 0  to T m  is selected for a program or read operation by applying a positive voltage, e.g. 5 V, to its control gate which turns on the transistor. The control gates of the unselected transistors are connected to ground. 
     As viewed in FIG. 1, 5 V is applied to the transistor T 1  which turns it on. A current I 1  flows through the transistor T 1  from ground through its source, channel (not shown) and drain and through the bitline BL to the driver 1. Ideally, the bitline current I BL  should be equal to I 1 . 
     However, if one or more of the unselected transistors, e.g. the transistor T 2  as illustrated in FIG. 1, is overerased, its threshold voltage will be zero or negative, and background leakage current will flow through the transistor T 2  as indicated at I 2 . The bitline current I BL  is now no longer equal to I 1 , but is equal to the sum of I 1  and the background leakage current I 2 . 
     In a typical flash EEPROM, the drains of a large number, for example 512, transistor cells such as illustrated in FIG. 1 are connected to each bitline (column). If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of a cell on the bitline and renders the memory inoperative. 
     FIG. 2 illustrates how the threshold voltages of the cells or bits in a flash EEPROM can differ substantially from each other following an erase operation as shown by a solid line curve which represents the numbers of cells having particular values of threshold voltage V T . It will be seen that the least erased cells will have a relatively high threshold voltage V T  MAX, whereas the most overerased cells will have a low threshold voltage which is below a minimum acceptable value V T  MIN that can be negative. The characteristic illustrated in FIG. 2 is known as the threshold voltage distribution. 
     FIG. 3 illustrates how the background leakage current of a cell varies as a function of threshold voltage. The lower (more negative) the threshold voltage, the higher the leakage current. It is therefore desirable to prevent cells from being overerased and reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase on the order of 2 V. 
     It is known in the art to reduce the threshold voltage distribution by performing an overerase correction operation which reprograms the most overerased cells to a higher threshold voltage. This operation will result in the threshold voltage curve being altered to the shape indicated by broken line in FIG. 2 in which the threshold voltages of all of the cells are above the minimum acceptable value V T  MIN. An overerase correction operation of this type is generally known as Automatic Programming Disturb (APD). 
     An APD method which is referred to as Automatic Programming Disturb Erase (APDE) is disclosed in U.S. Pat. No. 5,642,311, entitled &#34;OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS&#34;, issued Jun. 24, 1997 to Lee Cleveland. The method includes sensing for overerased cells and applying programming pulses thereto which bring their threshold voltages back up to acceptable values. 
     A significant factor which results in an increase in the threshold voltage distribution is the source pull-up voltage which is applied to the sources of the cells during the erase pulses. As electrons are removed from the floating gates of the cells by Fowler-Nordheim tunneling through the tunnel oxide, the vertical electric field across the tunnel oxide decreases. The electric field at the beginning of erase must not be too high or it will adversely affect the tunnel oxide reliability and result in increased threshold voltage distribution. 
     The End-of-Erase (EOE) electric field at the completion of the erase operation must not be too low, or it will be insufficient to erase slow cells. However, it must not be too high, or it will cause overerasure of fast and typical cells in the main distribution. 
     It is known in the art to apply a main source drive voltage V SS  to the sources of the cells through a pure resistive load. However, this expedient is limited in that the vertical electric field drops relatively sharply. If sufficient source voltage is applied to produce a suitable EOE field, the initial electric field will be too high. Conversely, if the source voltage is reduced to produce a suitably low initial electric field, the EOE field will be too low. 
     Another prior art expedient is to provide a source pull-up power supply including a constant current source. The object of this arrangement is to attempt to provide a constant electric field by maintaining the band-to-band tunneling current constant. However, the result is significant overerasure of fast and typical cells due to an excessively high EOE field. 
     FIG. 4 illustrates a composite source pull-up power supply 1 which includes a current source 2 and a load resistor R and represents an improvement over the pull-up supplies described above which include only a resistor or a constant current source. The current source 2 is connected to a main source supply voltage V SS . 
     A load line for the power supply 1 is illustrated in FIG. 5, which plots source current I S  as a function of source voltage V S . If the current source 2 were omitted, the load line would include a downwardly slanting solid line portion 3 and a broken line portion 3&#39;. The solid line portion 3 intersects the horizontal V S  axis at the value V SS  (open circuit) at which the current I S  is zero. The broken line portion 3&#39; intersects the vertical I S  axis at a value V SS  /R (short circuit), at which the current is maximum and the voltage V S  is zero. 
     The current source 2 supplies a constant current of value I S  MAX and limits the maximum voltage to V S  MAX. The effect of the current source 2 is illustrated by a solid line curve portion 4 and a broken line curve portion 4&#39;. Thus, for the power supply 1, the source voltage V S  will increase along the curve portion 4 with the constant current I S  MAX being supplied to the cell 1 until the curve portions 3 and 4 intersect at a voltage V S  1, and then increase with decreasing source current I S  along the curve portion 3 to the limit value V SS . 
     The improvement provided by the current source 1 results from the current source 2 limiting or reducing the initial vertical electric field, and the resistor R helping to control the EOE field. However, not even the improved power supply 1 is able to provide an optimal vertical electric field throughout the entire erase operation, resulting in an undesirably large threshold voltage spread. 
     The problem is exacerbated by a phenomenon known as &#34;cycling&#34;, in which the source voltage tends to increase as more erase pulses are applied to the cells. FIG. 6 illustrates the effect of cycling in which a curve 5 represents the threshold voltage increase without cycling. A curve 6 represents the threshold voltage characteristic at the end of erase due to the effect of cycling. It will be noted that the curve 6 is shifted upwardly from the curve 5, and that the source voltage V S  becomes clamped to the limit value V SS  along the curve 6 long before the cells have become completely erased. 
     The cycling phenomenon is caused by the generation of hot electron-hole pairs resulting from band-to-band tunneling. Whereas Fowler-Nordheim tunneling from the floating gate through the tunnel oxide layer to the source results in erasure of a cell, band-to-band tunneling also occurs between the substrate and the source. When a positive voltage is applied to the source junction with the control gate negative, a deep depletion region is formed underneath the gate-to-source overlap region. Electron-hole pairs are generated by the tunneling of valence band electrons into the conduction band. The electrons are collected by the source junction, and the holes are collected by the substrate. 
     Since the minority carriers (holes) generated thermally or by band-to-band tunneling in the source region flow to the substrate due to the lateral field near the Si-SiO 2  interface, the deep depletion region remains present and the band-to-band tunneling can continue without creating an inversion layer. The generated holes gain energy because of the electric field in the depletion region. While the majority of these generated holes flow into the substrate, some of them gain sufficient energy to surmount the Si-SiO 2  barrier and are trapped in the tunnel oxide layer. 
     The trapped holes reduce the horizontal electric field which results in reduced band-to-band tunneling current. This effect increases as the cells are cycled (progressively more erase pulses are applied thereto). Cycling results in exacerbation of the resistor and constant current source pull-up loads problems as described above. As the power supply 1 is a combination of a resistor and current source load, the individual problems associated therewith remain. There remains a substantial need in the art for a source pull-up power supply which provides a reduction in these undesirable effects and which can reduce the threshold voltage distribution of the erased memory. 
     It is also desirable to monitor the erase state of the memory in order to determine how far the erase operation has progressed and how many more erase pulses need to be applied. Such information can also be used to adjust the configuration of the pull-up power supply as erase progresses so that the applied electric field will be as close to optimal as possible. 
     As illustrated in FIG. 6, the main contribution to the source current V S  is band-to-band tunneling (the Fowler-Nordheim tunneling current which causes the actual cell erasure is orders of magnitude lower), and this generally provides an accurate indication of the erase state. It is therefore at least theoretically possible to monitor the erase state of the memory by sensing the source current during the erase pulses (concurrent erase and verify). 
     However, in many applications the source voltage clamps to the maximum value V SS  as indicated by the curve 6 and thereby provides no useful information relating to the erase state. For this reason, it is impractical in these applications to monitor the erase state by sensing the source voltage during the erase pulses. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a method for erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which overcomes the above described limitations of the prior art. 
     More specifically, a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) according to the present invention includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The memory further includes a resistive power supply, a sensor, and a controller which cooperates with the power supply. The power supply applies a source voltage to the sources of the cells that can have a maximum value. 
     An erase pulse is applied to the cells during which the power supply is configured to allow the source voltage to clamp to the maximum value. A monitoring pulse is then applied to the cells during which the power supply is configured to prevent the source voltage from clamping to the maximum value. 
     The sensor senses the source voltage while the monitoring pulse is applied. As the source voltage is not clamped, it is substantially a function of band-to-band tunneling current and accurately indicates the average state of erasure of the cells. The power supply includes a resistance and/or a current source which can be varied to reduce the source current while the monitoring pulse is being applied and thereby avoid clamping. 
     The present invention thereby overcomes the limitations of the prior art and fulfills the need for a method of accurately sensing the state of a flash EEPROM which can be advantageously applied to reducing the threshold voltage distribution. 
     These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified electrical schematic diagram showing how background leakage current is generated in a prior art flash Electrically Erasable Programmable Read-Only Memory (EEPROM); 
     FIG. 2 is a graph illustrating a threshold voltage distribution in a flash EEPROM after an erase operation; 
     FIG. 3 is graph illustrating how background leakage current varies as a function of threshold voltage for the least erased cells; 
     FIG. 4 is a fragmentary electrical schematic diagram illustrating a resistive power supply applying a source voltage to a memory cell; 
     FIG. 5 is a graph illustrating a load line of the power supply of FIG. 4; 
     FIG. 6 is a graph illustrating how the source voltage clamps to a maximum value due to cycling as an erase procedure progresses; 
     FIG. 7 is a simplified electrical schematic diagram of a flash EEPROM; 
     FIG. 8 is similar to FIG. 7 but illustrates a flash EEPROM having cells arranged in pages or banks; 
     FIG. 9 is a simplified partial sectional view of a flash EEPROM illustrating the elements of the cells thereof; 
     FIG. 10 is a timing diagram illustrating the present erase method; 
     FIG. 11 is a graph illustrating how the source voltage increases due to cycling in accordance with the present invention; 
     FIG. 12 is a graph illustrating how the source voltage increases as a function of time in accordance with the present invention; 
     FIGS. 13a and 13b are electrical schematic diagrams illustrating a power supply having a continuously variable current source and resistance; and 
     FIGS. 14a and 14b are electrical schematic diagrams illustrating a power supply having a discretely variable current source and resistance. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 7 illustrates the basic configuration of a NOR type flash Electrically Erasable Programmable Read-Only Memory (EEPROM) 10 to which the present invention is advantageously applied. The memory 10 comprises a plurality of core or memory cells which are arranged in a rectangular matrix or array of rows and columns. Each row is associated with a wordline, whereas each column is associated with a bitline. 
     Assuming that there are n columns and m rows, the bitlines are designated as BL 0  to BL n  and the wordlines are designated as WL 0  to WL m . Appropriate voltages are applied to the bitlines by a bitline driver 12, whereas appropriate voltages are applied to the wordlines by a wordline driver 14. The voltages applied to the drivers 12 and 14 are generated by a power source or supply 13 under the control of a controller 15 which is typically on-chip logic circuitry. The controller 15 also controls the drivers 12 and 14 to address the memory cells individually or collectively as will be described below. 
     A memory cell is located at each junction of a wordline and a bitline. Each cell includes a Metal-Oxide-Semiconductor (MOS) Field-Effect Transistor (FET) having a source, drain, gate oxide and control gate. The cells of a flash EEPROM differ from conventional FETs in that they additionally include a floating gate and tunnel oxide layer disposed underneath the gate oxide and control gate. 
     The cells illustrated in FIG. 7 are designated using the notation T n ,m, where m is the row (wordline) number and n is the column (bitline) number. The control gates of the cells are connected to respective wordlines, and the drains of the cells are connected to respective bitlines as illustrated. The sources of all of the cells are connected to the power supply 13. 
     A cell is programmed by applying, typically, 9 V to the control gate, 5 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 4 V. 
     The cell is read by applying typically 5 V to the control gate and 1 V to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 V), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 V), the control gate voltage will enhance the channel, and the bitline current will be relatively high. Reading is preferably performed using sense amplifiers and a reference current array, the details of which are not the particular subject matter of the present invention. 
     A cell can be erased in several ways. In one arrangement, a cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, a cell can be erased by applying a negative voltage on the order of -10 V to the control gate, applying 5 V to the source and allowing the drain to float. 
     It is common to organize the individual memory cells of a flash EEPROM into a plurality of banks or sectors. FIG. 8 illustrates a flash EEPROM memory 16 according to the present invention which is similar to the memory 10 except that the cells are divided into a plurality, in the illustrated example two, of banks (also known as pages or sectors), each of which can be programmed, erased and read independently. 
     A typical EEPROM will comprise, for example, 8 sectors, each of which includes 512K memory cells. For simplicity of illustration and description, the memory 16 is shown as including only a first cell bank 18 and a second cell bank 20. However, it will be understood that the present invention is applicable to a memory having any number of sectors or banks. The memory 16 also includes a controller and a power source or supply similar to the memory 10, although not explicitly illustrated. 
     The memory cells in the first bank 18 are designated in the same manner as in FIG. 7, whereas a prime symbol is added to the designations of the cells in the second bank 20. The wordlines of the banks 18 and 20 are connected to separate wordline drivers 14a and 14b respectively. 
     In addition to the memory cells, each bank 18 and 20 includes a select transistor for each bitline. The select transistors for the banks 18 and 20 are designated as S 0  to S n  and S 0  &#39; to S n  &#39; respectively. The drains of the select transistors are connected to the respective bitlines, whereas the sources of the select transistors are connected to the drains of the transistors for the wordlines WL 0  to WL m  and WL 0  &#39; to WL m  &#39;. 
     The select transistors differ from the memory cell transistors in that they are conventional MOSFETs and lack floating gates. The select transistors are switching elements rather than memory elements. The gates of the select transistors for the bank 18 are connected to a bank select output BS 1  of a sector decoder 15a, whereas the gates of the select transistors for the bank 20 are connected to a bank select output BS 2  of a sector decoder 15b. 
     The sources of the cells in bank 18 are connected to a common source supply voltage V SS  1, whereas the sources of the cells in the bank 20 are connected to a common source supply voltage V SS  2. 
     The bank 18 is selected by applying a logically high signal to the bank select line BS 1  which turns on the transistors S 0  to S n  and connects the bitlines BL 0  to BL n  to the underlying memory cells. The bank 18 is deselected by applying a logically low signal to the bank select line BS 1  which turns off the transistors S 0  to S n  and disconnects the memory cells from the bitlines. The bank 20 is selected and deselected in an essentially similar manner using the bank select signal BS 2  and select transistors S 0  &#39; to S n  &#39;. The operation of the memory 16 is essentially similar to that of the memory 10, except that the program, erase and read operations are performed on the banks 18 and 20 sequentially and independently. 
     FIG. 9 is a simplified sectional view illustrating the construction of the individual memory cells of the memory 10 or 16. The memory is formed on a silicon or other semiconductor substrate 30. Three erasable memory cells 32 are illustrated as being formed on a surface 30a of the substrate 30, each including a Metal-Oxide-Semiconductor (MOS) Field-Effect Transistor (FET) structure having a source 34, drain 36, an interdielectric layer 38, and channel 40 underlying a tunnel oxide layer 48. A polysilicon control gate 44 is formed over each gate oxide layer 38, and a polysilicon floating gate 46 and the tunnel oxide layer 48 are formed underneath the control gate 44 over the channel 40. 
     Each pair of cells 32 is arranged to share a common source 34 and drain 36. The sources 34 are connected to a common source line, whereas a bitline connection 49 is formed on each drain 36. 
     FIG. 10 illustrates how the present invention overcomes the cycling problem described above with reference to FIG. 6 and enables the erase state of the memory 10 or 16 to be accurately determined by sensing the pull-up source voltage applied to the cells. 
     As shown in the drawing, erase pulses 50 are applied to the cells. After each erase pulse 50, a sensing or monitoring pulse 52 is applied to the cells. Preferably, the same gate voltage, e.g. -10 V, is applied to the gates of the cells during both the erase and monitoring pulses, although it is within the scope of the invention to make these voltages different. However, a lower value of drive current is applied to the sources of the cells during the monitoring pulses than during the erase pulses. 
     The lower current results in a lower source voltage which is prevented from clamping to the main source voltage V SS . As viewed in FIG. 10, the source voltage applied during the erase pulses is typically on the order of 5 V, whereas the average source voltage applied during the monitoring pulses is on the order of 2 V to 3 V. 
     FIG. 11 illustrates the effects of cycling as described above, but with the source drive current low enough that the source voltage will not reach and be clamped to V SS . A curve 54 illustrates the initial variation of source voltage with time (or equivalently the number of applied erase pulses) which would hold if cycling were not present. The source voltage has an initial value V I  where the curve 54 intersects the V S  axis. 
     Curves 56, 58 and 60 illustrate how the variation of source voltage with time is progressively shifted due to the effects of cycling, with the curve 60 representing the relationship at the finish of the erase operation after numerous cycles. The final value of source voltage is V F , as indicated at the end of the curve 60. 
     If the source voltage is maintained at a very low value, the effect of cycling will be reduced and the final curve will not differ greatly from the initial curve. In such a case, the state of erasure of the memory will substantially correspond to the curve 54. 
     However, in some applications it will not be practical to maintain the source voltage applied during the monitoring pulses at such a low value, and the source voltage curve will be shifted due to cycling as illustrated in FIG. 11. The result is that the source voltage V S  will vary with time as illustrated by a curve 62 in FIG. 12, starting at the initial value V I  and ending at the final value V F . The entire source voltage vs. erase time curve shifts upwardly with cycling. Since the sources of the cells are connected together while the erase and monitoring pulses are applied, the sensed source voltage represents an average value for all of the cells, or the source voltage for a typical cell. 
     The actual shape of the curve 62 will be different for each application, and can be determined empirically or using a computer simulation. Once the curve is determined, the source voltage can be sensed or monitored after applying an erase pulse as described above. Each point on the curve 62 equates a value of sensed source voltage to a corresponding state of erasure as represented by time, number of applied erase pulses, or percentage of completion of the erase operation. 
     In this manner, the present method enables accurate calculation of the state of erasure of the memory cells as a predetermined function (represented by the curve 62) of sensed source voltage. The calculation can be performed using logic circuitry, a look-up table, or any other suitable methodology. Once the erase state of the memory is determined, the erase parameters can be suitably adjusted to optimize the vertical electric field across the tunnel oxide and thereby tighten the threshold voltage distribution. 
     FIGS. 13a and 13b illustrate a circuit arrangement for practicing the present invention. As viewed in FIG. 13a, a resistive source pull-up power supply 70 includes a current source 12 which is connected to a main source voltage supply V SS  of the memory. The current source 72 is connected through a resistance 74 to a circuit point 76 which is in turn connected to the sources of the memory cells. The current source 72 and/or the resistance 74 are variably controlled by a source voltage/current controller 78. A sensor 80 is connected to the point 76 for sensing the source voltage and applying an electrical voltage or other parameter representing the sensed source voltage to the controller 78 or other control element. 
     Only the erase current source or the sensor is connected to the array source at any given time. In other words, the sensor 80 is active only during the monitoring pulse. 
     The controller 78 generates a current control voltage I C  and a resistance control voltage R C  which are applied to the current source 72 and resistance 74 respectively. An example of the source 72 and resistance 74 is illustrated in FIG. 13b. The resistance 74 is constituted by a PMOS transistor T1, whereas the current source 72 includes PMOS transistors T2 and T3 and an NMOS transistor T4. 
     The transistors T2, T3 and T4 are connected to function as a current mirror. The drains of the transistors T2 and T3 are connected to the voltage V SS , and the gates of the transistors T2 and T3 are connected together. The source of the transistor T3 is connected to the drain of the transistor T1, whereas the source of the transistor T1 is connected to the point 76 and thereby to the sources of the memory cells. The resistance control signal R C  is applied to the gate of the transistor T1. 
     The transistor T2 is connected in a diode configuration, with its source connected to its gate. The source of the transistor T2 is connected to the drain of the transistor T4. The source of the transistor T4 is connected to ground, whereas the gate of the transistor T4 is connected to receive the current control signal I C . 
     The current through the transistor T4, and therefore through the transistor T2, is determined by the value of I C . Since the drain to gate voltages of the transistors T2 and T3 are the same, the current through the transistor T2 is mirrored to the transistor T3. Thus, the current flow through the transistors T2 and T3 are the same and are determined by the current control voltage I C . 
     The transistor T1 functions as a voltage controlled resistor, with the resistance determined by the resistance control voltage R C . Thus, the current of the current source 72 and the resistance of the resistance 74 can be continuously controlled to any desired value by applying the corresponding control voltages I C  and R C  thereto. 
     As described above, the source voltage V S  must be prevented from clamping to V SS  while the monitoring pulse is applied to the cells and the source voltage V S  is sensed by the sensor 80. This can be accomplished in several ways. The current source 72 can be configured such that it functions as a constant current source and supply a first value of current during erase, and a second, lower value of current during monitoring. Alternatively, the current source 72 can be configured to limit the current to a first value during erase, and to a second, lower value during monitoring. 
     As an alternative to or in combination with variation of the current source, the resistance 74 can be controlled to provide a first value of resistance during erase, and a second, higher value of resistance during monitoring. In any case, the effect is to apply a smaller value of source current to the sources of the memory cells during monitoring than during erase, so that the source voltage is prevented from reaching and being clamped to the main supply voltage V SS . 
     Whereas the arrangement illustrated in FIGS. 13a and 13b enables continuous variation of the current and resistance of the power supply 70, it is further within the scope of the invention to vary these values discretely, or in steps. FIG. 14a illustrates a source power supply 81 which includes a controller 82, which outputs four switching signals, IC1, IC2, RC1 and RC2. FIG. 14b illustrates a current source unit 84 and a resistance unit 86 which are connected in series between the supply V SS  and the point 76 and are controlled by the switching signals. 
     The current source unit 84 includes two current sources 88 and 90 which supply a high current for erasure and a low current for monitoring respectively in the manner described above. The sources 88 and 90 are connected in series with switches 92 and 84 which are controlled by the signals IC1 and IC2 respectively. The resistance unit 86 includes two resistors 96 and 98 which have a low resistance for erasure and a high resistance for monitoring respectively. The resistors 96 and 98 are connected in series with switches 100 and 102 which are controlled by the signals RC1 and RC2 respectively. 
     For erasure, the controller 82 makes the signals IC1 and RC1 logically high to close the switches 92 and 100 and connect the current source 88 and resistor 96 in series between V SS  and the point 76 so that a relatively high level of current is applied to the sources of the memory cells. During this procedure the signals IC2 and RC2 are low, so that the switches 94 and 102 are open and the current source 90 and resistor 98 are disconnected from the circuit. For monitoring, the switches IC and RC1 are opened and the switches IC2 and RC2 are closed to connect the source 90 and resistor 98 into the circuit. 
     The switches IC1, IC2, RC1, RC2 are used to obtain directly varying values of I C  and R C  during erase which are controlled by the output received from the sensor 80. The sensor 80 is a separate element. 
     As with the power supply 70 of FIGS. 13a and 13b, it is within the scope of the invention to vary only one of the current and resistance in the power supply 81. It is also possible to provide either the current source or the resistance as a fixed, rather than a variable element in either of these embodiments. 
     In summary, the present invention overcomes the limitations of the prior art and fulfills the need for a method of accurately sensing the state of a flash EEPROM which can be advantageously applied to reducing the threshold voltage distribution. 
     Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.