Abstract:
An accurate high current mirror circuit produces a mirrored current that matches an input current to produce an accuracy at the output of a subsequent stage of amplification of greater than 0.01%. A plurality of transistor devices are arranged in a symmetrical configuration and divided into two groups. The transistors in each of the two groups are connected in parallel to produce a high mirror current from a high input current. A distribution of a source voltage produces the same source voltage at each of the plurality of transistors. An input current metallization and a mirror current metallization are formed within the symmetrical configuration to have a same value of impedance. A plurality of P-channel transistors within the current mirror circuit control a voltage of a point on the input metallization to be the same as a reference voltage thus causing the mirror current to be referenced around the reference voltage.

Description:
BACKGROUND OF THE INVENTION  
       [0001]     1. Field of Invention  
         [0002]     The present invention relates to a current mirror circuit and more particularly a low noise and high accuracy current mirror circuit for audio applications.  
         [0003]     2. Description of Related Art  
         [0004]     In audio applications such as can be found in mobile phones producing an analog signal from a digital signal that can then be heard by the human ear requires a wide conversion range, i.e. twenty-four bits. This is often done with a current steering circuit where a sigma-delta DAC (digital to analog converter) with a low resolution DAC and a modulator drives a current mirror circuit. The current mirror circuit works in conjunction with the DAC to translate a digital code into a current centered around zero by taking the output from the current mirror circuit, whose input was driven by one output from the. DAC and subtract it from the second output current from the DAC. When the output from the current mirror circuit does not perfectly match the input current to the current mirror circuit from the DAC, a residual error current results. The output current from the current mirror and DAC circuit is converted to a voltage that is passed to a substantial gain in subsequent circuitry in the audio signal path. This becomes a problem when there is no digital input signal and the error current is converted to a voltage, which is applied to the sound-producing device and places an added stress on the coils of the earphone or other sound producing devices driven by the subsequent audio circuitry. It is critical that the current steering design have an accuracy, which produces a current when converted to a voltage that is interpreted by the subsequent elements of the audio path as being zero for the digital input code which represents zero. Since the current steering design is a differential output, where the output of the current mirror circuit is subtracted from an output of the DAC, it is critical that the current mirror circuit produce an accurate copy of the input current to the current mirror circuit to minimize or eliminate the error current when there is no digital input to the DAC. Since the current mirror circuit is operating with a high current relative to the desired input referred error current, i.e. in the range of a milliampere for the DC current within the current mirror when there is no digital input signal, there is not only a need for good matching of transistor devices but also a matching of the impedance of metallization carrying the high current and a matching of the values of voltage distributed to the transistor devices. Common elements in the circuitry can be handled by the design, and non-common elements require critical matching so as to produce a proper result in the down stream signal, i.e. zero volts when the digital signal is the code which represents zero.  
         [0005]     U.S. Pat. No. 6,472,858 B1 (Tanase) is directed to low voltage fast settling precision current mirrors and methods using a first and a second current mirror circuit where the output of the two current mirrors are coupled such that the output receives a part of the mirrored current from each current mirror. In U.S. Pat. No. 5,212,458 (Fitzpatrick et al.) a current mirror design is directed to a compensation circuit, which automatically adjusts the operating conditions of the current mirror. U.S. Pat. No. 4,329,639 is directed to a high accuracy current mirror circuit comprising low beta transistors and operating on a low supply voltage  
       SUMMARY OF THE INVENTION  
       [0006]     It is an objective of the present invention to provide a current mirror load operating in conjunction with a DAC that provides an accurate output current that is accurately matched to the current mirror input current.  
         [0007]     It is also an objective of the present invention to produce a difference between a DAC current and the current mirror output current that is converted to a voltage, which is interpreted by subsequent circuitry as no input signal.  
         [0008]     It is further an objective of the present invention to provide a current mirror circuit that produces a high current output, which matches a high current input with a high level of accuracy.  
         [0009]     It is also further an objective of the present invention to provide a current mirror circuit that has a symmetrical design in which a plurality of transistor devices connected in parallel collectively produce a high current and in which are all transistor devices are biased with the same value of a source voltage.  
         [0010]     It is still further an objective of the present invention to match the impedance of the high current input and output metallization of the current mirror circuit.  
         [0011]     It is still another objective of the present invention to produce an output current from the current mirror circuit where the output current matches the input current with an accuracy greater than 0.01%.  
         [0012]     In the present invention a digital input signal is converted to an analog output voltage. The output voltage is amplified and coupled to a sound apparatus to produce a voice response to the digital signal. A digital to analog converter (DAC) might be implemented as a current steering circuit in which a sigma delta DAC produces two high amplitude current signals. A first of the two DAC high current signals is coupled to a current mirror circuit, which produces an accurate copy of the first of the two DAC high current signals. The accurate copy of the first of the two DAC high current signals is subtracted from the second DAC output current, and the result is input to a current to voltage converter. The current to voltage converter couples an analog audio signal to an amplifier through a low pass filter.  
         [0013]     When there is no digital input signal to the DAC, it is important that the output of the amplifier is at it&#39;s quiescent bias point, which in turn does not put undue stress on the speaker device connected to the output of the amplifier. Slight differences in the output current of the current mirror circuit from the input current will cause a substantial error signal at the output of the amplifier, when connected in a high gain configuration, and when the digital input signal to the DAC corresponds to the zero level code. This amplified error signal in turn places a stress on the audio speakers.  
         [0014]     In the present invention the error signal problem is substantially reduced or eliminated by accurately matching the high output current of the current mirror circuit to the high input current so that a zero audio signal is produced when the code input to the DAC corresponds to a zero level. To accomplish this, the high current circuitry of the current mirror is formed in a symmetrical array of N-channel transistor devices. The array of N-channel transistor devices is divided into two groups, a first group for handling input current from the DAC and a second group for providing an output current of the current mirror circuit. The two groups of N-channel transistor devices are distributed and intermingled within the array of N-channel transistor devices in a checkerboard fashion. The distributed checkerboard fashion allows the composite of all transistor devices in each group to smooth, or average out process variations in the transistor devices. All of the N-channel transistor devices in the first group are connected in parallel, wherein all gates are connected together, all drains are connected together and all sources are connected together. In like manner all N-channel transistor devices in the second group are connected in parallel, wherein all gates are connected together, all drains are connected together and all sources are connected together.  
         [0015]     A symmetrical source voltage distribution network is positioned over the symmetrical array of N-channel transistors and is connected to all the sources in the array of N-channel transistors such that the same voltage value is connected to each source. A metallization carrying the source voltage to the array of N-channel transistor devices is connected to the symmetrical source voltage distribution network at a central point in the network, thus allowing the distribution network to supply each source of the N-channel transistors of the two groups of N-channel transistors with the same source voltage. The metallization carrying the source voltage to the source voltage distribution network and the source voltage distribution network are formed with wide high current carrying metallization providing sufficiently low impedance.  
         [0016]     The input current path to the current mirror from the DAC and the output current path from the current mirror are formed with wide high current carrying metallization to have equal impedance so that the same voltage drops occur in each path. A plurality of vias between metallization on different wiring layers of the semiconductor device are used to further minimize resistance of the high current carrying paths and to reduce effects of temperature on the resistance of a particular high current path. This is important because the matching of vias is often uncontrolled or poorly controlled. The difference between the two currents is sensitive to variations in the high current output of the current mirror circuit. The output of the current mirror is centered around a reference voltage so that a negative digital input to the DAC can be coupled to the amplifier through the analog circuitry as a signal below the reference voltage. When there is no digital input signal to the DAC, the reference voltage is coupled to the amplifier and no analog error signal is coupled to the speaker mechanism. The techniques of the present invention provide a matching of the mirror current to the input current to which is produced an amplified accuracy at the amplifier greater than 0.01% when referred to the input signal level of the current mirror and herein called input referred accuracy.  
         [0017]     It should be noted that although N-channel transistor devices are used in the high current circuitry and the current mirror circuit along with P-channel transistor devices, the circuitry of the present invention can be created using P-channel transistor devices in place of the N-channel devices and N-channel devices in place of the P-channel devices. Also it should be noted that the techniques of the present invention are applicable to circuitry formed from bipolar transistor devices and any other devices that convert digital signals to analog signals, provide gain and route current. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0018]     This invention will be described with reference to the accompanying drawings, wherein:  
         [0019]      FIG. 1  is a circuit diagram of the present invention showing an audio DAC containing a current mirror circuit;  
         [0020]      FIG. 2  is a circuit diagram of the present invention of a current mirror circuit with a high current input and output circuitry;  
         [0021]      FIG. 3  is a plan view of the first level metal of an array of transistor devices used in the present invention to create the high current circuitry of the current mirror circuit;  
         [0022]      FIG. 4  is a plan view of the second level metal of the array of transistor devices used in the present invention to create the high current circuitry of the current mirror circuit;  
         [0023]      FIG. 5  is the plan view of the third level metal of the array of transistor devices used in the present invention to create the high current circuitry of the current mirror circuit;  
         [0024]      FIG. 6  is the plan view of the fourth level metal of the array of transistor devices used in the present invention to create the high current circuitry of the current mirror circuit;  
         [0025]      FIG. 7  is a method of the present invention for creating the high current circuitry of the current mirror circuit; and  
         [0026]      FIG. 8  is a method of the present invention for connecting the bias transistors of the current mirror circuit to the high current circuitry connected to the current mirror. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT  
       [0027]     In  FIG. 1  is shown the circuitry of the present invention to convert a digital signal to audio analog signal. A digital input signal is connected to a DAC  10 , which is a current steering sigma delta DAC that produces two currents, I 1  and I 2  that are a function of the digital input, where I 2  is approximately twice the magnitude of I 1 . Other DAC designs that produce similar currents are within the scope of this invention. The current I 1  forms an input to the current mirror circuit I 1 . The current mirror circuit is symbolized by an amplifier, which drives the gates of two N-channel transistors, N 4  and N 5 . The output current of the current mirror circuit is I 3  where I 3 =I 1 . The amplifier  12  and a current to voltage converter  14  are connected to a reference voltage around which the current, I 2 −I 3 =I 2 −I 1 , flows into the current to voltage converter. The currents I 1 , I 2  and I 3  are high currents, for example in the milliampere range but are not limited to this range. The reference voltage allows currents representing both positive and negative digital input signals to be converted to a voltage by the current to voltage converter  14 .  
         [0028]     The current to voltage converter  14  couples a voltage representing the digital input signal to an amplifier  16  through a low pass filter  15 . The analog output signal of the amplifier  16  then drives and earphone or similar sound-producing device and has a high gain, for example greater than 20 db. Since the mirror current I 3  is subtracted from the DAC current I 2 , which is approximately twice I 1 , it is critical that I 3  accurately represent I 1 . When the digital input signal is zero, any differences (error current) between I 1  and I 3  is converted to a voltage and amplified by the subsequent circuit gain represented by amplifier  16 . The effect of the error current is to put additional stress on the coils of the earphone or similar device when the digital input signal is zero.  
         [0029]     In  FIG. 2  is shown a schematic of the current mirror circuit of the present invention. The core of the current mirror circuit is formed with P-channel transistor devices P 2  and P 3  connected to N-channel transistor devices N 1  and N 2 . A bias transistor P 1  connects the voltage aVdd to the current mirror circuit and a source voltage aVss 2  connected to the sources of N 1  and N 2  with a wide, low resistance metallization  35  and Vsub is connected to the substrate of transistor devices N 1  and N 2 . The P-channel transistors P 2  and P 3  are each formed with a plurality of transistor devices connected in parallel to provide composite devices in which semiconductor process variations are averaged (smoothed) to provide a more consistent and matched pair of equivalent devices. High current N-channel devices symbolized by N 4  and N 5  provide the high current carrying capability of the current mirror.  
         [0030]     The high current devices symbolized by N 4  and N 5  are each a composite device of a plurality of N-channel transistor device connected in parallel such that the drains, sources and the gates of the N channel transistor devices devices are connected in parallel in each of the N 4  and N 5  composite devices. A common high current connection of the source voltage aVss 1   30  is connected to a central point  31  from which a high current metallization  32  connects to the sources of the devices forming N 4  and N 5  in such a manner that the same source voltage is applied to the source of all the devices that form N 4  and N 5 . A first high current metallization  33  connects I 1  from the DAC  10  ( FIG. 1 ) and a second high current metallization  34  connects a mirror current I 3 , where I 3 =I 1 , to subsequent circuitry for converting the digital input signal to the DAC  10  to an analog voltage signal at the output of the amplifier  16  ( FIG. 1 ). The first and second high current metallization  33  and  34  are configured such that the impedance to current flow I 1  and the impedance to current flow I 3  are equal.  
         [0031]     The gate to the P-channel transistor P 2  is connected to the high current metallization  33  at a point near a central distribution point of the high current metallization connected to the drains of the N-channel transistor devices forming N 4 . This allows the amplifier formed by P-channel transistor devices P 2  and P 3  to control the drain voltage of N 4  to a reference voltage Vref that is connected to the gate of the P-channel transistor device P 3 . A resistor R and capacitor C network is connected between the drains and the gates of N 4  to provide circuit stability.  
         [0032]     In  FIG. 3  is shown the first level metal layout of the plurality of N-channel transistor devices forming the composite parallel-connected devices that form N 4  and N 5  and the P-channel transistor devices forming the composite parallel-connected devices that form P 2  and P 3 . The N-channel devices forming N 4  and N 5  are intermingled in a symmetrical checkerboard fashion so as to average (smooth) the effects of process variations on the individual devices, and to provide a configuration that can be interconnected with high current metallization that creates a same source voltage at each device as well as input and output high current connections of equal impedance. The P-channel devices P 2  and P 3  are also distributed in a checkerboard fashion to provide an averaging of the process variations on each device. Additional P 2  and P 3  devices can be added and distributed in a checkerboard fashion as shown to produce well defined composite P-channel transistors P 2  and P 3  by connecting all gates in parallel, all drains in parallel and all sources in parallel within each composite group.  
         [0033]     A polysilicon layer  40  forms the gates of N-channel devices N 4  and N 5  and a polysilicon layer  41  forms the gates of the P-channel devices P 2  and P 3 . A strip of polysilicon  42  connects the polysilicon gates of N 4  and N 5 . A first level metal  43  connects to the drains of N 4  and a first level metal  45  connects to the drains of N 5 . On the first level metal  43  connecting to the drains of N 4  and N 5  are shown areas  44  and  46  where a plurality of vias are used to connect to the second level metal. The use of a plurality of vias is necessary to maintain a low impedance in the routing of the high current metallization. Between alternate rows of N 4  and N 5  devices is a first level metal  47  that connects to the sources of the transistor devices N 4  and N 5 . Centered in each strip of the metallization  47  is an area  48  where a plurality of vias are used to connect to the subsequent layers of metallization. The P-channel transistors P 2  are shown with a short segment of minimum pitch metal  49  that is used to connect the gates of the P 2  transistor devices. These short segments form a part of the connection of P 2  to the drains of N 4 .  
         [0034]     In  FIG. 4  is shown the second level metal overlaying the first level metal of the symmetrical arrangement of the N-channel devices N 4  and N 5 . A wide metallization  60  connects to the drains of N 4  through the plurality of vias  44  ( FIG. 3 ) and a wide metallization  61  connects to the drains of N 5  through the plurality of vias  46  ( FIG. 3 ). Areas  62  at the ends of the wide metallization  60  and  61  provide a plurality of vias to connect to the third level of metal. An area  63  provides a plurality of vias to connect the source metallization  47  ( FIG. 3 ) to the third level of metal. A minimum pitch metal  64  connects the gates of the P 2  transistor devices to the wide metallization connected to the drains of the N 4  transistor devices.  
         [0035]     In  FIG. 5  is shown the third level metal overlaying the symmetrical arrangement of the N-channel devices N 4  and N 5 . A source voltage distribution metallization  70  is centrally located over the array of N-channel devices N 4  and N 5 . An area  71  in the center of the source voltage distribution metallization provides a plurality of via connections to the fourth level of metallization. The first level source voltage metallization  47  is connected to the source voltage distribution metallization  70  through a plurality of inter-metal vias  72  between each subsequent layers of metallization (plurality of vias  63  in  FIG. 4  and plurality of vias  48  in  FIG. 3 ). The design of the source voltage distribution metallization provides the same source voltage value at the sources of each of the N-channel transistors N 4  and N 5 .  
         [0036]     Continuing to refer to  FIG. 5 , a wide high current metallization  73  connects together the wide metallization  60  ( FIG. 4 ) through a plurality of vias  62  ( FIG. 4 ), which allows all drains of N 4  to be connected together and share current I 1  ( FIG. 2 ). A wide high current metallization  74  connects together the wide metallization  61  ( FIG. 4 ) through a plurality of vias  62  ( FIG. 4 ), which allows all drains of N 5  to be connected together and share current I 3  ( FIG. 2 ). The use of a plurality of vias  62  to interconnect the metallization on different wiring layers allows the same impedance to high current for I 1  and I 3  into and out of the current mirror circuit  33  and  34  ( FIG. 2 ).  
         [0037]     In  FIG. 6  is shown a portion of fourth level metal over the array of N 4  and N 5  devices. A source voltage metallization  80 , common to the sources of both N 4  and N 5  is connected to the symmetrical source voltage distribution metallization  70  through a plurality of vias  71  ( FIG. 5 ). The metallization  80 ,  70  and  47  and the plurality of vias  71 ,  72 ,  63  and  48  that distributes the source voltage to the sources of the N-channel devices N 4  and N 5  provides the means by which the same source voltage value is connected to all the sources of the plurality of transistor devices, which form the high current devices N 4  and N 5  of the current mirror circuit.  
         [0038]     In  FIG. 7  is shown a method of the present invention for creating the high current circuitry of the current mirror. A symmetrical array of N-channel transistor devices is formed on a semiconductor substrate  90 . A first set of high current circuit is formed from a plurality of the N-channel transistor devices  91  by connecting the devices of the first set in parallel. A second set of high current circuit is formed from a plurality of the N-channel transistor devices  92  by connecting the devices of the second set in parallel. The first and the second set of N-channel transistor devices are distributed in a symmetrical checkerboard pattern  93  around a central point. The checkerboard pattern allows the effects of semiconductor process variations to be averaged thereby forming a first and second set of transistors that have a composite characteristic that is as nearly matched as possible. A first and a second high current metallization  94  are formed in which the impedance of the first and second high current metallization is equal. The drains of the first set of transistor devices are connected to the first high current metallization  95 , and the drains of the second set of transistor devices are connected to the second high current metallization  96 . A voltage distribution network is centered over the symmetrical array of transistor devices  97 . A source voltage is connected to a center point of the voltage distribution network  98  and the voltage distribution network is connected to all transistor devices in the symmetrical array of transistor devices  99  in a manner by which the same source voltage value is connected to each source of the symmetrical array of transistor devices. The method describe for  FIG. 7  allows a current mirror circuit to accurately copy an input current of high magnitude by minimizing impedance differences, minimizing process variations in the transistor devices of composite high current circuitry, and providing a same source voltage value to all the transistor devices that make up the first and second high current circuits of the current mirror circuit.  
         [0039]     In  FIG. 8  is a method of the present invention for connecting the bias transistors of the current mirror circuit to the high current circuitry of the current mirror. A current mirror circuit is formed from a plurality of P-channel and N-channel transistor devices  110 . A first group of P-channel transistors is formed and connected in parallel, whereby the gates of the P-channel transistor devices in the first group are connected to a first high current metallization connected to a first high current circuit of the current mirror circuit  111 . A second group of P-channel transistor devices is formed and connected in parallel, whereby the gates of the P-channel transistor devices in the second group are connected to a reference voltage  112 . The connection of the gates of the first group of P-channel transistors to the first high current metallization controls the current mirror circuit to produce a voltage on the first high current metallization equal to the reference voltage. The first and second groups of P-channel transistor devices are arranged on the semiconductor substrate in a checkerboard fashion whereby process variations of the transistor devices are averaged, producing a more consistent composite first and second groups of transistor devices. The drain of the first group of P-channel transistor devices (P 2 ,  FIG. 2 ) is connected to a drain of the first N-channel transistor (N 1 ,  FIG. 2 ) of the current mirror circuit  113 , and the drain of the second group of P-channel transistor devices (P 3 ,  FIG. 2 ) is connected to gates of a first and a second high current circuit (N 4  and N 5 ,  FIG. 2 ) and to the drain of the second N-channel transistor device (N 2 ,  FIG. 2 ) of the current mirror circuit  114 .  
         [0040]     It should be noted that the circuitry and metallization networks describe herein can be applied to circuitry where N-channel transistor devices replace the P-channel transistor devices of the present invention and P-channel transistor devices replace the N-channel transistor devices of the present invention. Further it should be noted that bipolar devices and/or other devices producing voltage, current, or other forms of energy, and gain can be used to replace the function of the N-channel and P-channel devices of the present invention  
         [0041]     While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.