Abstract:
A CMOS image sensor and fabricating method thereof enable enhanced photo-response characteristics and protect a microlens in packaging by embedding the microlens in a passivation layer pattern. The image sensor may include a semiconductor substrate, a photodiode, a metal line, an insulating layer, a passivation layer pattern, and a microlens formed to be embedded in the passivation layer pattern.

Description:
[0001]     This application claims the benefit of Korean Patent Application No. 10-2004-0116428, filed on Dec. 30, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a CMOS image sensor and fabricating method thereof. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for enhancing photo-response characteristics and protecting a microlens in packaging by embedding the microlens in a passivation layer pattern.  
         [0004]     2. Discussion of the Related Art  
         [0005]     An image sensor is a semiconductor device that converts an optical image to an electric signal. Image sensors can be classified into charge coupled devices (CCD) and CMOS (complementary metal oxide silicon) image sensors. In a CCD image sensor, a plurality of MOS (metal-oxide-metal) capacitors are arranged close to one another to transfer and store electric charge carriers. In a CMOS (complementary MOS) image sensor, a plurality of MOS transistors corresponding to the number of pixels are fabricated by CMOS technology using a control circuit and a signal processing circuit as peripheral circuits. A switching system of sequentially detecting outputs using the MOS transistors is also adopted.  
         [0006]     Microlenses of the related art CMOS image sensor are formed on a passivation layer; thus, the microlenses are vulnerable to packaging. Hence, photo-response characteristics of the CMOS image sensor are degraded and overall process throughput is lowered.  
         [0007]     A CMOS image sensor and fabricating method thereof according to a related art are explained with reference to the attached drawing as follows.  
         [0008]      FIG. 1  is a cross-sectional diagram of a CMOS image sensor according to a related art.  
         [0009]     Referring to  FIG. 1 , a photodiode  11  is formed on a semiconductor substrate  10 . A first insulating layer  12  is formed on the semiconductor substrate  10  including the photodiode  11 . A via hole  13  is formed by selectively etching the first insulating layer  12 . A metal layer is deposited on the first insulating layer  12  including the via hole  13  and is then patterned to form a metal line  16  in a pixel area  14  and a pad  17  in a peripheral area  15 . A second insulating layer  18  is formed of a material for interlayer insulation, such as oxide, etc., on the first insulating layer  12  including the metal line  16  and the pad  17 . The second insulating layer  18  is then planarized.  
         [0010]     A passivation insulating layer  19  may be formed of nitride. The passivation insulating layer  19  is planarized by CMP (chemical mechanical polishing) and is then selectively etched to form an opening  21  on the pad  17 . A microlens material layer (not shown) is formed on the passivation insulating layer  19 . A photoresist layer (not shown) is coated on the microlens material layer. The photoresist layer is patterned to form a photoresist pattern (not shown). The microlens material layer is selectively etched to form a microlens material layer pattern (not shown) using the photoresist pattern as a mask. Reflowing is carried out on the microlens material layer pattern by baking to form a spherical microlens  20 .  
         [0011]     However, the related art CMOS image sensor and fabricating method thereof have disadvantages. Since the microlens is formed on the passivation layer, the microlens can be damaged in subsequent packaging. Hence, a photo-response characteristic of a device is degraded and process throughput is lowered.  
       SUMMARY OF THE INVENTION  
       [0012]     Accordingly, the present invention is directed to a CMOS image sensor and fabricating method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.  
         [0013]     An advantage of the present invention is to provide a CMOS image sensor and fabricating method thereof, in which a microlens is formed between patterns of a passivation layer.  
         [0014]     Another advantage of the present invention is to provide a CMOS image sensor and fabricating method thereof, by which damaging of the microlens in a subsequent packaging can be prevented.  
         [0015]     Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and method particularly pointed out in the written description and claims hereof as well as the appended drawings.  
         [0016]     To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a CMOS image sensor includes a semiconductor substrate, a photodiode in the semiconductor substrate, a metal line over the semiconductor substrate that electrically connects to the photodiode, an insulating layer on the semiconductor substrate that insulates the metal line, a passivation layer pattern on the insulating layer, and a microlens on the insulating layer that is embedded in the passivation layer pattern.  
         [0017]     In another aspect of the present invention, a method of fabricating a CMOS image sensor includes the steps of forming a photodiode in a semiconductor substrate, forming a first insulating layer on the semiconductor substrate, forming a metal line on the first insulating layer for electrically connecting to the photodiode, forming a second insulating layer on an entire surface of the first insulating layer including the metal line, forming a passivation layer pattern on the second insulating layer, and forming a microlens on the second insulating layer such that the microlens is embedded in the passivation layer pattern.  
         [0018]     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0019]     The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:  
         [0020]      FIG. 1  is a cross-sectional diagram of a CMOS image sensor according to a related art; and  
         [0021]      FIGS. 2A  to  2 E are cross-sectional diagrams of a CMOS image sensor fabricated by a method according to an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0022]     Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.  
         [0023]     Referring to  FIG. 2A , a photodiode  31  is formed on a semiconductor substrate  30 . The photodiode  31  includes red, green and blue photodiodes  31   a ,  31   b  and  31   c  that are vertically stacked on the semiconductor substrate  30 . A first insulating layer  32  is formed on the semiconductor substrate  30  including the photodiode  31 . A via hole  33  is formed by selectively etching the first insulating layer  32 . A metal layer is deposited on the first insulating layer  32  including the via hole  33  and is then patterned to form a metal line  36  in a pixel area  34  and a pad  37  in a peripheral area  35 . A second insulating layer  38  is formed of a material for interlayer insulation, such as oxide, etc., on the first insulating layer  32  including the metal line  36  and the pad  37 . A passivation layer  39  is formed of nitride on the second insulating layer  38 .  
         [0024]     A first photoresist layer (not shown) is coated on the passivation layer  39 . Exposure and development are performed on the first photoresist layer to form a first photoresist pattern  40  to expose portions of the passivation layer  39  corresponding to a microlens forming area and the pad  37 , respectively.  
         [0025]     Referring to  FIG. 2B , the passivation layer  39  is selectively removed using the first photoresist pattern  40  as a mask to form a first opening  41   a  on the microlens forming area and a second opening  41   b  over the pad  37 .  
         [0026]     Referring to  FIG. 2C , the first photoresist pattern  40  is removed. A microlens forming material layer (not shown) is formed on the passivation layer  39  including the first and second openings  41   a  and  41   b . The microlens forming material layer is then planarized until an upper surface of the passivation layer  39  is exposed. Hence, a microlens material layer pattern  42  is formed within each of the first and second openings  41   a  and  41   b.    
         [0027]     Referring to  FIG. 2D , a second photoresist layer (not shown) is coated on the passivation layer  39  including the microlens material layer patterns  42  and is then patterned to form a second photoresist pattern  43  using a pad mask (not shown). The microlens material layer pattern  42  and the second insulating layer  38  are selectively etched using the second photoresist pattern  43  as a mask until an upper surface of the pad  37  is exposed.  
         [0028]     In an exemplary embodiment, the second opening  41   b  is formed by etching the portion of the passivation layer  39  corresponding to the pad area and the microlens material layer pattern is formed in the second opening  41   b . The second opening  41   b  may be omitted. Since the portion of the passivation layer  39  corresponding to the pad area remains intact, the targets of the selective etch are the passivation layer  39  and the second insulating layer  38 . Selective etching of these layers exposes the pad  37  using the second photoresist pattern  43  as a mask.  
         [0029]     Referring to  FIG. 2E , the second photoresist pattern  43  is removed. A spherical microlens  44  is formed by performing reflowing on the microlens material layer pattern  42  at an appropriate temperature. The passivation layer  39  and the microlens  44  do not overlap each other.  
         [0030]     By forming the self-aligned microlens  44  to be embedded in the passivation layer  39 , a space margin between the microlenses  44  can be accurately secured to raise photo-efficiency.  
         [0031]     The present invention provides the following effects. The self-aligned microlenses may be accurately arranged in a photo-shield layer to raise photo-efficiency. Also, the microlens is embedded in the passivation layer such that it is prevented from being damaged in packaging. Hence, photo-response characteristics of the device can be enhanced and the process throughput can be raised.  
         [0032]     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.