Abstract:
Disclosed is a high linearity programmable gain amplifier using a switch, including an attenuating portion for controlling a gain of a signal and an amplifying portion having a first amplifying part and a second amplifying part, for amplifying an input signal and outputting a signal amplified, wherein the first amplifying part has a first amplifier for amplifying an input signal and a first switch for activating the first amplifier and the second amplifying part has a second amplifier for amplifying an input signal and a second switch for activating the second amplifier.

Description:
[0001]     This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application Nos. 10-2004-0063440 filed in Korea on Aug. 12, 2004 and 10-2004-0087472 filed in Korea on Oct. 29, 2004, the entire contents of which are hereby incorporated by reference.  
       BACKGROUND OF THE INVENTION  
       [0002]     1. Field of the Invention  
         [0003]     The present invention relates to a gain amplifier, more particularly, to a high linearity programmable gain amplifier using a switch.  
         [0004]     2. Description of the Background Art  
         [0005]      FIG. 1  shows a circuit diagram of a discrete step gain switch amplifier (DSGSA) using a prior art switch.  
         [0006]     As shown in  FIG. 1 , a conventional amplifier using a switch consists of an attenuating portion  110  and an amplifying portion  120 .  
         [0007]     The attenuating portion  110  includes an input terminal RFin, a plurality of switches SW 11  to SW 14 , and a plurality of resistors R 11  to R 16 .  
         [0008]     The amplifying portion  120  is composed of an amplifier  121 , resistors RF 1  and RF 2 , and an output terminal RFout.  
         [0009]     The output terminal of the attenuating portion  110  is connected with the input terminal of the amplifying portion  120 .  
         [0010]     When all of switches SW 11  to SW 14  in the attenuating portion  110  are opened, even if an input signal is applied to the attenuating portion  110 , no signal is to be amplified by the amplifying portion  120  because any circuit cannot be formed.  
         [0011]     Meanwhile, when the switch SW 11  of the attenuating portion  110  is closed to form the circuit, an input signal is applied to a first input terminal of the amplifying portion  120 , and a signal attenuated by the attenuating portion  110  based on a combined resistance value of resistors R 11  to R 16  is applied to a second input terminal of the amplifying portion  120 .  
         [0012]     The turn-on or turn-off of switches SW 11  to SW 14  may alter the gain of the amplifier  121 .  
         [0013]     If the attenuating portion  110  exists in the first and second input terminals of the amplifying portion  120 , when an amplifying operation in the amplifier  121  is performed in a low gain, the effect of the noise figure from the amplifier  121  is minimal, but, when the amplifying or converting operation in the amplifier  121  is performed in a high gain, the noise due to the switching noise from a switching element or a thermal noise in the amplifier  121 , etc, can be added to an original signal, thereby deteriorating the noise figure.  
         [0014]      FIG. 2  shows a circuit diagram of a variable gain low noise amplifier constructed by a parallel connection of prior art amplifier.  
         [0015]     As shown, the variable gain low noise amplifier has a first selective portion to a fourth selective portion  201 ,  202 ,  203  and  204 , a power supply and an input/output terminal.  
         [0016]     The first selective portion  201  comprises a driving part including resistors R 21  and R 22 , a capacitor C 11  and a transistor M 11 , and further comprises a capacitor C 12  and a transistor M 12 .  
         [0017]     The second selective portion  202  comprises a driving part including resistors R 23  and R 24 , a capacitor C 21  and a transistor M 21  and an amplifying part including capacitors C 12  and C 23  and a transistor M 22 .  
         [0018]     The third selective portion  203  comprises a driving part including resistors R 25  and R 26 , a capacitor C 31  and a transistor M 31  and an amplifying part including capacitors C 32  and C 33  and a transistor M 32 .  
         [0019]     The fourth selective portion  204  comprises a driving part including resistors R 27  and R 28 , a capacitor C 41  and a transistor M 41  and an amplifying part including capacitors C 42  and C 43  and a transistor M 42 .  
         [0020]     The operation of the variable gain low noise amplifier will be described below in detail.  
         [0021]     If a current  11  is applied to a base of the transistor M 12  to select the first selective portion  201 , a current between an emitter and a base of the transistor M 12  is amplified rapidly and thereby conducting the transistor M 12 . This also leads the conduction of the transistor M 11 . As a result, a gain is determined by the capacitor C 12 .  
         [0022]     If a current I 2  flows into a base of the transistor M 22 , the transistor M 22  is conducted and conduction of the transistor M 22  also leads to conduction of the transistor M 21 . As a result, a gain is determined by the capacitance ratio of the capacitor C 22  to the capacitor C 23 .  
         [0023]     The third selective portion  203  and the fourth selective portion  204  operate in similar manner with the first selective portion  201  and the second selective portion  202 .  
         [0024]     In conclusion, the transistor M 12  does not attenuate a signal, but the transistors M 22 , M 32  and M 42  attenuate a signal with gains determined by the capacitance ratio of the capacitor C 22  to the capacitor C 23 , the capacitance ratio of the capacitor C 32  to the capacitor C 33  and the capacitance ratio of the capacitor  42  to the capacitor C 43 , respectively.  
         [0025]     Accordingly, the total gain of the whole amplifier circuit is changed depending on which selective portion among the selective portions  201  to  204  is selected.  
         [0026]     That is, a desired gain of the amplifier circuit is achieved by connecting the selective portions  201  to  204  in parallel and selecting any one of the selective portions  201  to  204 .  
         [0027]     However, the conventional variable gain low noise amplifier is disadvantageous in that the parallel connection of the amplifying parts, i.e. the selective portions, and application of the electric current to select any one amplifying part among the amplifying parts lead to deterioration of the characteristics of the circuit in view of the bandwidth, and further the application of an electric current to the amplifying parts increases the total power consumption.  
       SUMMARY OF THE INVENTION  
       [0028]     Accordingly, it is an object of the present invention to solve at least the problems and disadvantages of the background art and thereby provide a variable gain amplifier capable of not deteriorating noise figure and ensuring the sufficient bandwidth.  
         [0029]     Another object of the present invention is to provide a variable gain amplifier consuming low power.  
         [0030]     Still another object of the present invention is to provide a variable gain amplifier having a high linearity of amplifier gain.  
         [0031]     To accomplish the objects above, according to one aspect of the present invention, there is provided a high linearity programmable gain amplifier using a switch, including an attenuating portion for controlling a gain, and an amplifying portion including a first amplifying part and a second amplifying part for amplifying an input signal and outputting a signal amplified, wherein the first amplifying part has a first amplifier for amplifying an input signal and a first switch for activating the first amplifier and the second amplifying part has a second amplifier for amplifying an input signal and a second switch for activating the second amplifier.  
         [0032]     The attenuating portion may include a switch and a resistive divider.  
         [0033]     The first and second switches may operate complementally to each other.  
         [0034]     When the first switch of the attenuating portion is turned on, the first switch of the first amplifying part may be turned off and the second switch of the second amplifying part may be turned on.  
         [0035]     The first switch may be connected to an output terminal of the first amplifier and the second switch may be connected to an output terminal of the second amplifier.  
         [0036]     The attenuating portion includes a plurality of attenuating parts connected in parallel.  
         [0037]     The attenuating parts are separately formed in different wells, respectively.  
         [0038]     In accordance with another aspect of the present invention, there is provided a high linearity programmable gain amplifier using a switch, including a follower circuit portion for transmitting a voltage without phase change, the follower circuit including a first transistor with first through third terminals and a first biasing portion applying a bias voltage; and a switch portion for controlling a gain of a signal transmitted from the follower circuit by switching operation and generating an output signal, wherein the switch portion includes a second transistor having first through third terminals, the first terminal being connected to a power supply voltage, the second terminal being connected to a switch which controls a gain by switching a signal and is supplied with the same voltage as the bias voltage applied to the follower circuit portion, and the third terminal being connected to a second biasing portion which applies a bias voltage, and wherein all the third terminals of the first and second transistors are coupled to each other to form an output terminal.  
         [0039]     A gain of the circuit is determined to meet the following expression which is a relational expression between a width function of the transistor of the follower circuit portion and a width function of the transistor of the switch portion,  
         A   V     =         g   m1         g   m1     +     g   m2         =         kW   1         kW   1     +     kW   2         =       W   1         W   1     +     W   2                 
 
         [0040]     where W 1  is a width function of the first transistor, W 2  is a width function of the second transistor, k is a proportional constant, gm1 is an output impedance of the follower circuit, and gm2 is an output impedance of the switch portion.  
         [0041]     In accordance with further another aspect of the present invention, there is provided a high linearity programmable gain amplifier including: a follower circuit portion for transmitting a voltage without phase change, the follower circuit including a first transistor with first through third terminals and a first biasing portion applying a bias voltage; and a first switch portion and a second switch portion for controlling a gain of a signal transmitted from the follower circuit by a first switching operation and a second switching operation and generating an output signal, wherein the first switch portion includes a second transistor having first through third terminals, the first terminal being connected to a power supply voltage, the second terminal being connected to a switch which controls a gain of a signal by switching the signal and is supplied with the same voltage as the bias voltage applied to the follower circuit portion, and the third terminal being connected to a second biasing portion which applies a bias voltage; and the second switch portion includes a third transistor having first through third terminals, the first terminal being connected to a power supply voltage, the second terminal being connected to a switch which controls a gain by switching a signal and is supplied with the same voltage as the bias voltage applied to the follower circuit portion, and the third terminal being connected to a third biasing portion which applies a bias voltage, and wherein the third terminals of the first through third transistors are coupled to each other to form an output terminal.  
         [0042]     Here, the first through third biasing portions are constituted by fourth through sixth transistors, respectively, each with first through third terminals, wherein the second terminals of the fourth through sixth transistors are coupled to form an input terminal for receiving a constant-current source there through.  
         [0043]     Here, a switch is provided before an input stage, such as a gate, of the fifth and sixth transistors, respectively.  
         [0044]     The first through third biasing portions are realized by a shared bias unit which comprises a fourth transistor with a first terminal, a second terminal connected to a constant-current source, and a third terminal.  
         [0045]     Each transistor above is implemented by a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (BJT).  
         [0046]     The gain control of the circuit is performed to meet the following expression:  
                 Δ   ⁢           ⁢     dB   ⁡     (     A   V     )           Δ   ⁢           ⁢   W       =       ⁢         log   ⁡     (       W   1         W   1     +     W     n   +   1           )       -     log   ⁡     (       W   1         W   1     +     W   n         )             (       W   1     +     W     n   +   1         )     -     (       W   1     +     W   n       )                     =       ⁢       log   ⁡     (         W   1     +     W   n           W   1     +     W     n   +   1           )           W     n   +   1       -     W   n                     =       ⁢       log   ⁡     (     1   +         W   n     -     W     n   +   1             W   1     +     W     n   +   1             )           W     n   +   1       -     W   n                     =       ⁢           log   ⁡     (     1   +         -   Δ     ⁢           ⁢   W         W   1     +     W     n   +   1             )         Δ   ⁢           ⁢   W       ⁢   %   ⁢           ⁢           -   Δ     ⁢           ⁢   W       W   1         Δ   ⁢           ⁢   W       ⁢   %     -     1     W   1                   
 
         [0047]     where ΔdB is a value corresponding to gain change, ΔW is a value corresponding to width function value change, W 1  is a width function of the first transistor, Wn is a width function of a transistor belongs to n-th switch portion, and Wn+1 is a width function of a transistor belongs to n+1-th switch portion. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0048]     The invention will be described in detail with reference to the following drawings in which like numerals refer to like elements.  
         [0049]      FIG. 1  is a circuit diagram of a conventional discrete-step gain switch amplifier using a switch;  
         [0050]      FIG. 2  is a circuit diagram of a conventional variable gain low noise amplifier including amplifiers connected in parallel with each other;  
         [0051]      FIG. 3  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to the first embodiment of the present invention;  
         [0052]      FIG. 4  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to the secondary embodiment of the present invention;  
         [0053]      FIG. 5  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to a first modified example of the second embodiment of the present invention;  
         [0054]      FIG. 6  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to a second modified example of the second embodiment of the present invention, in which a switching portion is modified; and  
         [0055]      FIG. 7  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to the third embodiment of the present invention. 
     
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS  
       [0056]     Certain embodiments of the present invention will be described in greater detail with reference to the accompanying drawings.  
         [0057]     In the following description, same drawing reference numerals are used for the same elements even in different drawings. The matters defined in the description such as a detailed construction and elements are nothing but the ones provided to assist in a comprehensive understanding of the invention. Thus, it is apparent that the present invention can be carried out without those defined matters. Also, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.  
         [0058]     Preferred embodiments of the present invention will be described in a more detailed manner below.  
         [0059]      FIG. 3  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to a first embodiment of the present invention.  
         [0060]     Referring to  FIG. 3 , a high linearity programmable gain amplifier using a switch includes an attenuating portion  310  and an amplifying portion  320 .  
         [0061]     &lt;Configuration&gt; 
         [0062]     The attenuating portion  310  includes a first attenuating part  311 , a second attenuating part  312 , a third attenuating part  313  and a fourth attenuating part  314 .  
         [0063]     Here, the first attenuating part  311  includes a first switch SW 31  and a first resistive divider  311   a , the second attenuating part  312  includes a second switch SW 32  and a second resistive divider  312   a , the third attenuator member  313  includes a third switch SW 33  and a third resistive divider  313   a , and the fourth attenuator member  314  includes a fourth switch SW 34  and a fourth resistive divider  314   a.    
         [0064]     The amplifying portion  320  includes a first amplifying part  321 HG and a second amplifying part  321 LG.  
         [0065]     Here, the first amplifying part  321 HG includes a first amplifier  322 HG and a first amplifying switch SWHG, and the second amplifying part  321 LG includes a second amplifier  322 LG and a second amplifying switch SWLG.  
         [0066]     &lt;Connection&gt; 
         [0067]     The first switch SW 31  has one terminal connected to an input terminal IN of the whole amplifier circuit and the other terminal connected to an end of the first resistive divider  311   a.    
         [0068]     The first resistive divider  311   a  includes a first resistor R 31  and a second resistor R 32  connected in parallel.  
         [0069]     The second switch SW 32  has one terminal connected to the input terminal IN of the whole amplifier circuit and the other terminal connected to one end of a second resistive divider  312   a.    
         [0070]     The second resistive divider  312   a  includes a third resistor R 33  and a fourth resistor R 34  connected in parallel.  
         [0071]     The third switch SW 33  has one terminal connected to the input terminal IN of the whole amplifier circuit and the other terminal connected to one end of the third resistive divider  313   a.    
         [0072]     The third resistive divider  313   a  includes a fifth resistor R 35  and a sixth resistor R 36  connected in parallel.  
         [0073]     The fourth switch SW 34  has one terminal connected to the input terminal IN of the whole amplifier circuit and the other terminal connected to one end of the fourth resistive divider  314   a.    
         [0074]     The fourth resistive divider  314   a  includes a seventh resistor R 37  and an eighth resistor R 38  connected in parallel.  
         [0075]     An input terminal of the first amplifier  322 HG is connected to the input terminal IN of the whole amplifier circuit, thereby forming an input terminal of the first amplifying part  321 HG. Meanwhile an output terminal of the first amplifier  322 HG is connected to one terminal of the first amplifying switch which has the other terminal connected to an output terminal OUT.  
         [0076]     The second amplifier  322 LG has an input terminal connected to an output terminal of the fourth resistive divider  314   a  to form an input terminal of the second amplifying part  321 LG and an output terminal connected to one terminal of the second amplifying switch SWLG which has the other terminal connected to an output terminal OUT.  
         [0077]     &lt;Operation&gt; 
         [0078]     When all the first to fourth switches in the first to fourth attenuating parts  311  to  314  are turned off, an input signal inputted to the input terminal IN can not be applied to the input terminal of the second amplifying part  321 LG. As a result, the second amplifying part  321 LG does not operate and output a signal but only the first amplifying part  321 HG operates to output an amplified signal to the output terminal OUT.  
         [0079]     That is, in order to control the amplifying operation of the second amplifying part  321 LG in programmable, any one of the first to fourth switches should be turn on but the first amplifier switch SWHG should be turned off.  
         [0080]     Or, oppositely, the second switch SWLG is turned off as well as all the first to fourth switches SW 31  to SW 34  are turned off.  
         [0081]     Accordingly, negative effect with respect to the noise figure caused due to the switching is ignorable even though the amplifier circuit operates with high gain.  
         [0082]     Here, when any one of the first to fourth switch SW 31  to SW 34  is turned on while other others are turned off, the first amplifying switch SWHG of the first amplifying part  321 HG is turned off. Thus, the first amplifying part  321 HG stops to operate while the second amplifying part  321 LG starts to operate as the second amplifying switch SWLG is turned on.  
         [0083]     Here, the first amplifying part  321 HG and the second amplifying part  321 LG do not generate an output signal at the identical time but alternatively generate an output signal.  
         [0084]     Thus, in accordance with the first embodiment of the present invention, it is possible to programmably control gains of a signal when it is required to achieve a low gain by using the first to fourth attenuating parts  311  to  314  or it is possible to achieve a high gain by bypassing the first to the attenuating parts  311  to  314 .  
         [0085]     In the description above, the attenuating portion is configured to comprise four attenuating parts, but the number of attenuating parts in the attenuating portion can be variable. That is, the attenuating parts can be additionally added.  
         [0086]     Also, the first to the fourth attenuating parts  311  to  314  may be separately formed in different wells by using a triple-well structure to prevent components of signals from leaking into a substrate even in case of high frequency signals.  
         [0087]     Namely, the resistors R 32  and R 33  of the attenuating part  311  are formed in one well of the triple-well structure formed by a CMOS process, and the resistors R 33  and R 34  of the attenuating part  312  are formed in another well of the triple-well structure. Also, the remaining resistors R 35 , R 36 , R 37  and R 38  of the attenuators  313  and  314  also are formed in different wells from each other.  
         [0088]     Therefore, in accordance with the first embodiment of the present invention, it is possible to programmably control gains of the amplifier circuit in case that the amplifier circuit operates with a low gain, and ensure excellent noise figure in case that the amplifier circuit operates with a high gain. The amplifier circuit in accordance with the first embodiment of the present invention further has advantages of wide bandwidth and low power consumption.  
         [0089]      FIG. 4  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to a second embodiment of the present invention.  
         [0090]     Referring to  FIG. 4 , a high linearity programmable gain amplifier using a switch comprises a source follower circuit  410  and a switching circuit  420 .  
         [0091]     &lt;Construction&gt; 
         [0092]     The source follower circuit  410  includes a first resistor R 41 , a first transistor M 41 , and a first current source IS 41 .  
         [0093]     The switching circuit  420  includes a second resistor R 42 , a first switch SW 41 , a second transistor M 42 , and a second current source IS 42 .  
         [0094]     &lt;Connection&gt; 
         [0095]     The input terminal IN is connected to one electrode of the first capacitor C 41 , and the other electrode of the capacitor C 41  is connected to both one end of the first resistor R 41  and a gate of the first transistor M 41 .  
         [0096]     A bias voltage Bias is applied to both nodes {circle around (1)} and {circle around (2)}, in which the node {circle around (1)} is connected to the other end of the first resistor R 41  and the node {circle around (2)} is connected to one end of the second resistor R 42 .  
         [0097]     A source of the first transistor M 41  is connected to a node {circle around ( 3 )} which is also an end of the first current source IS 41 .  
         [0098]     The other end of the second resistor R 42  is connected to one end of the first switch SW 41 , and the other end of the first switch SW 41  is connected to a gate of the second transistor M 42 .  
         [0099]     A source of the second transistor M 42  is connected to a node {circle around (4)} serving as one end of the second current source IS 42 .  
         [0100]     Here, the node {circle around (3)} and the node {circle around (4)} are connected to each other, in which node {circle around ( 4 )} is connected to one electrode of the second capacitor C 42 , the other electrode of the second capacitor C 42  is connected to one end of a load resistor RL and the output terminal OUT.  
         [0101]     &lt;Operation&gt; 
         [0102]     The channel width function W 1  of the first transistor is determined when a circuit is constructed, and output impedance thereof becomes 1/gm1.  
         [0103]     In the source follower circuit  410 , the input signal is applied to the other electrode of the first capacitor C 41 , the power voltage V DD  is applied to the drain of the first transistor M 41 , and the current source IS 41  is connected to the node {circle around ( 3 )}, so that a source follower circuit is constructed.  
         [0104]     Also, the channel width function of the second transistor M 42  is determined depending on opening or closing the first switch SW 41  in the switching circuit  420 , so that the output impedance is expressed as 1/gm2.  
         [0105]     According to such a construction, the amplifying degree can be changed based on the width function determined by the source follower circuit  410  and the switching circuit  420 , and such a changed signal is output from one end of the load resistor RL.  
         [0106]     That is, the programmable gain control amplifier can be implemented by using two source follower circuits, and linearity thereof will be described below.  
         [0107]     As the input signal and the bias voltage Bias are applied to the first transistor M 41  at the same time, a circuit having the output impedance of 1/gm1 can be constructed.  
         [0108]     At this time, if only D.C bias voltage Bias is applied to the input terminal of the source follower circuit constructed and thereby turns on/off the first switch SW 41 , the channel width function W 2  of the second transistor M 42  is determined. Then, when the channel width function W 2  is determined, the electric current flowing through the second transistor M 42  increases by the ratio W 1 /W 2 , the ratio of the channel width function W 1  of the first transistor M 41  to the channel width function W 2  of the second transistor M 42 .  
         [0109]     Here, a gain can be expressed by the following Equation:  
                 A   V     =         1     g   m2       //     R   L           1     g   m2       //       R   L     +     1     g   m1               ,       1     g   m2       ⁢   J   ⁢           ⁢     R   L               [     Equation   ⁢           ⁢   1     ]             
 
         [0110]     Where, since the output impedance 1/gm1 is smaller than RL in value, the gain in the Equation 1 can be expressed as the following Equation 2 based on the relationship between gm1 and gm2:  
               A   V     =         1     g   m2           1     g   m1       +     1     g   m2           =       g   m1         g   m1     +     g   m2                   [     Equation   ⁢           ⁢   2     ]             
 
         [0111]     Thus, the gain is calculated based on the relationship between gm1 and gm2, in which gm is expressed as the following Equation 3:  
                     g   m     =       μ   n     ⁢     C   ox     ⁢     W   L     ⁢     (       V   GS     -     V   TH       )         ,     g   m       ]     ⁢           ⁢   kW           [     Equation   ⁢           ⁢   3     ]             
 
         [0112]     From this, it is obvious that gm is proportional to the channel width function when the bias voltage is identical.  
         [0113]     Thus, the gain control expression is expressed as the following Equation 4:  
               A   V     =         g   m1         g   m1     +     g   m2         =         kW   1         kW   1     +     kW   2         =       W   1         W   1     +     W   2                     [     Equation   ⁢           ⁢   4     ]             
 
         [0114]     The channel width functions W 1  and W 2  of two transistors M 41  and M 42  constitute the control expression.  
         [0115]     Thus, the turn-on/turn-off of the first switch SW 41  which is coupled with the second transistor M 42  can control the gain.  
         [0116]     Equation 5 with reference to Equation 4 summarizes the gain control step.  
                       Δ   ⁢           ⁢     dB   ⁡     (     A   V     )           Δ   ⁢           ⁢   W       =       ⁢         log   ⁡     (       W   1         W   1     +     W     n   +   1           )       -     log   ⁡     (       W   1         W   1     +     W   n         )             (       W   1     +     W     n   +   1         )     -     (       W   1     +     W   n       )                     =       ⁢       log   ⁡     (         W   1     +     W   n           W   1     +     W     n   +   1           )           W     n   +   1       -     W   n                     =       ⁢       log   ⁡     (     1   +         W   n     -     W     n   +   1             W   1     +     W     n   +   1             )           W     n   +   1       -     W   n                     =       ⁢           log   ⁡     (     1   +         -   Δ     ⁢           ⁢   W         W   1     +     W     n   +   1             )         Δ   ⁢           ⁢   W       ⁢   %   ⁢           ⁢           -   Δ     ⁢           ⁢   W       W   1         Δ   ⁢           ⁢   W       ⁢   %     -     1     W   1                       [     Equation   ⁢           ⁢   5     ]             
 
         [0117]     Here, it is obvious that, the gain is proportional to 1/W 1  when ΔW is significantly small than W 1 .  
         [0118]     The present invention is preferably applicable for a precision gain control circuit for controlling a small quantity of gain and exhibiting the linear characteristic in the bandwidth dB.  
         [0119]     As described above, since the gain control depends on a channel width function, it exhibits the insensible characteristic with respect to a process, an environmental temperature, fluctuation of voltage, etc. Thus, it is possible for the amplifier circuit to ensure precision and stability in gain control. Also, since the channel width functions of transistors determines gain control function, the amplifier circuit can further additionally employ the transistors in multiple stages.  
         [0120]      FIG. 5  shows a high linearity programmable gain amplifier using a switch, which has a switching portion in accordance with one example of the second embodiment of the present invention.  
         [0121]     Referring to  FIG. 5 , a high linearity programmable gain amplifier using a switch includes a source follower circuit  510 , a first switching circuit  520  and a second switching circuit  530 .  
         [0122]     &lt;Construction&gt; 
         [0123]     The source follower circuit  510  has a first resistor R 51 , a first transistor M 51  and a fourth transistor M 54 .  
         [0124]     The first switching circuit  520  has a second resistor R 52 , a first switch SW 51 , a second transistor M 52 , a third switch SW 53 , and a fifth transistor M 55 .  
         [0125]     The second switching circuit  530  has a third resistor R 53 , a second switch SW 52 , a third transistor M 53 , a fourth switch SW 54 , and a sixth transistor M 56 .  
         [0126]     &lt;Connection&gt; 
         [0127]     One electrode of the first capacitor C 51  is connected to a gate of first transistor M 51  and one end of first resistor R 51 .  
         [0128]     The other end of first resistor R 51  is connected to a node {circle around (1)}.  
         [0129]     A source of the first transistor M 51  is connected to a node {circle around (4)}.  
         [0130]     One end of the second resistor R 52  is connected to a node {circle around (2)}, and the other end of the second resistor R 52  is connected to one terminal of first switch SW 51 .  
         [0131]     The other terminal of the first switch SW 51  is connected to the gate of second transistor M 52 .  
         [0132]     A source of the second transistor M 52  is connected to a node {circle around (5)}.  
         [0133]     One end of the third resistor R 53  is connected to a node {circle around (3)}, and the other end of the third resistor R 53  is connected to one terminal of the second switch SW 52 .  
         [0134]     The other end of the second switch SW 52  is connected to the gate of third transistor M 53 .  
         [0135]     A source of third transistor M 53  is connected to a node {circle around (6)}.  
         [0136]     Here, a first bias voltage Bias, is applied to the nodes {circle around (1)}, {circle around (2)} and {circle around (3)}.  
         [0137]     The fourth transistor M 54  has a gate connected to a node {circle around (7)}, a drain connected to a node {circle around (4)}, and a source connected to a ground.  
         [0138]     The third switch SW 53  is provided with one end terminal connected to a node {circle around (8)}, and the other terminal connected to a gate of the fifth transistor M 55 .  
         [0139]     A drain of the fifth transistor M 55  is connected to the node {circle around (5)}, and a source of the fifth transistor M 55  is connected to a ground.  
         [0140]     The one terminal of the fourth switch SW 54  is connected to a node {circle around (9)}, and other terminal of fourth switch SW 54  is connected to the gate of sixth transistor M 56 .  
         [0141]     A drain of the sixth transistor M 56  is connected to the node {circle around (6)}, and a source of sixth transistor M 56  is connected to a ground.  
         [0142]     Here, a second bias voltage Bias 2  is applied to the nodes {circle around (7)}, {circle around (8)} and {circle around (9)}.  
         [0143]     And, the node {circle around (6)} is connected to one electrode of the second capacitor C 52 , and the other electrode of second capacitor C 52  serves as the output terminal OUT.  
         [0144]     &lt;Operation&gt; 
         [0145]     When an input signal is applied to an input terminal IN, the first capacitor C 51  functions as a D.C. blocking element for blocking D.C. components of signals applied to the input terminal IN, a channel width function W 1  of the first transistor M 51  and a channel width function kW 1  of the fourth transistor M 54  are determined as soon as a circuit is constructed, a power voltage V DD  is applied to a drain of the first transistor M 51 , an output from a source of the first transistor M 51  is applied to a drain of the fourth transistor M 54 , and the first bias Bias 1  is applied to the node {circle around (1)}, and the second bias voltage Bias 2  is applied to the node {circle around (7)}, so that a source follower circuit  510  is constructed.  
         [0146]     When the first switch SW 51  and the third switch SW 53  of the first switching circuit  520  are simultaneously opened or closed, a channel width function W 2  of the second transistor M 52  and a channel width function kW 2  of the fifth transistor M 55  are determined, a power voltage V DD  is applied to a drain of the second transistor M 52 , an output from a source of the second transistor M 52  is applied to a drain of the fifth transistor M 52 , and the second bias voltage Bias 2  is applied to the node {circle around (8)}, so that the first switching circuit  520  is constructed.  
         [0147]     Here, the first switch SW 51  and the third switch SW 53  are simultaneously turned on or off to determine the amplifying operation, in which it has a linear characteristic as explained above.  
         [0148]     When the second switch SW 52  and the fourth switch SW 54  in the second switching circuit  530  are simultaneously opened or closed, a channel width function W 3  of the third transistor M 5  and a channel width function kW 3  of the sixth transistor M 56  are determined, and a power voltage V DD  is applied to a drain of the third transistor M 53 , the output of the source of the third transistor M 53  is applied to a drain of the sixth transistor M 56 , the first bias voltage Bias 1  is applied to the node {circle around (3)}, the second bias voltage Bias 2  is applied to the node {circle around (9)}, so that the second switching circuit  530  is constructed, in which the first capacitor C 52  connected to the node {circle around (6)} acts as a D.C. blocking element for blocking D.C. components of signals to be output through the output terminal OUT.  
         [0149]     Here, when the second switch SW 52  and the fourth switch SW 54  are simultaneously turned on or off to determine the amplifying operation  
         [0150]     That is, the first to fourth switches SW 51  to SW 54  are provided before the corresponding gates of the second transistor M 52 , the fifth transistor M 55 , the third transistor M 53 , and the sixth transistor M 56 , respectively, for switching to control gains and selectively drive the transistors M 52 , M 53 , M 55  and M 56 .  
         [0151]     As explained with reference to  FIG. 4 , since it is possible to control gains by the channel width functions of the firth to the sixth transistor M 51  to M 56 , the transistors can be arranged in multiple stages.  
         [0152]     Here, if it is required to additionally add transistors to the amplifier circuit for a gain control, a gain control circuit can be easily and simply constituted by adding the circuit  520  as many as it is required.  
         [0153]     The gain control is performed in multiple steps using a plurality of gain control transistors, so that the number of transistors can be increased depending on the gain control characteristic.  
         [0154]      FIG. 6  is a circuit diagram of a high linearity programmable gain amplifier using a switch, which has a modified switching portion in accordance with a second example of the second embodiment of the present invention.  
         [0155]     As shown in  FIG. 6 , a high linearity programmable gain amplifier using a switch includes a source follower circuit  610 , a first switching circuit  620 , and a second switching circuit  620 .  
         [0156]     &lt;Construction&gt; 
         [0157]     The source follower circuit  610  has a first resistor R 61 , a first transistor M 61  and a fourth transistor M 64 .  
         [0158]     The first switching circuit  620  has a second resistor R 62 , a first switch SW 61 , and a second transistor M 62 .  
         [0159]     The second switching circuit  630  has a third resistor R 63 , a second switch SW 62  and a third transistor M 63 .  
         [0160]     &lt;Connection&gt; 
         [0161]     One electrode of the first capacitor C 61  is connected to a gate of the first transistor M 61  and one end of a first resistor R 61 .  
         [0162]     The other end of the first resistor R 61  is connected to a node {circle around (1)}.  
         [0163]     A source of the first transistor M 61  is connected to a node {circle around (4)}.  
         [0164]     One end of the second resistor R 62  is connected to a node {circle around (2)}, and the other end of the second resistor R 62  is connected to one terminal of the first switch SW 61 .  
         [0165]     The other terminal of the first switch SW 61  is connected to a gate of the second transistor M 62 .  
         [0166]     A source of the second transistor M 62  is connected to a node {circle around (5)}.  
         [0167]     One end of the third resistor R 63  is connected to a node {circle around (3)}, and the other end of the third resistor R 63  is connected to one terminal of the second switch SW 62 .  
         [0168]     The other terminal of the second switch SW 62  is connected to a gate of the third transistor M 63 .  
         [0169]     A source of the third transistor M 63  is connected to a node {circle around (6)}.  
         [0170]     Here, a first bias voltage Bias 1  is applied to the nodes {circle around (1)}, {circle around (2)} and {circle around (3)}.  
         [0171]     The fourth transistor M 64  has a gate to which the second bias voltage Bias 2  is applied, a drain connected to the node {circle around ( 4 )} and a source grounded.  
         [0172]     Here, the nodes {circle around (4)}, {circle around (5)} and {circle around (6)} are connected commonly to one electrode of the second capacitor C 62 , and the other electrode of the second capacitor C 62  acts an output terminal OUT.  
         [0173]     &lt;Operation&gt; 
         [0174]     When an input signal is applied to an input terminal IN, a channel width function W 1  of the first transistor M 61  and a channel width function kW 1  of the fourth transistor M 64  are determined as soon as an electrical circuit is constructed, a power voltage V DD  is applied to a drain of the first transistor M 61 , an output from a source of the first transistor M 61  is applied to a drain of the fourth transistor M 64 , a first bias voltage Bias 1  is applied to the node {circle around (1)}, and a second bias Bias 2  is applied to the gate of the fourth transistor M 64 , so that a source follower circuit  610  is constructed.  
         [0175]     When the first switch SW 61  in the first switching circuit  620  is opened or closed, a channel width function W 2  of the second transistor M 62  is determined, a power voltage V DD  is applied to a drain of the second transistor M 62 , and a source of the second transistor M 62  is connected to the node {circle around (5)}, so that the first switching circuit  620  is constructed.  
         [0176]     Here, the first switch SW 61  is turned on or turned off to determine the amplifying operation, in which the first switch SW 61  has a linear characteristic as described.  
         [0177]     When the second switch SW 62  in the second switching circuit  630  is opened or closed, a channel width function W 3  of the third transistor M 63  is determined, and a power voltage V DD  is applied to a drain of the third transistor M 63 , and a source of the third transistor M 63  is connected to the node {circle around (6)}, so that the second switching circuit  630  is formed.  
         [0178]     Here, the second switch SW 62  is turned on or turned off to determine the amplifying operation and it has a linear characteristic as noted above.  
         [0179]     The first and second switches SW 61  and SW 62  are disposed before the gates of the second transistor M 62  and the third transistor M 63 , respectively, to drive the transistors M 62  and M 63  by being switched.  
         [0180]     Thus, as described with reference to  FIG. 4 , in performing the gain control, the control is implemented by channel width functions W 1  to W 3  and Kw 1  of the first to fourth transistors, so that the gain control can be preformed in multiple steps.  
         [0181]     Here, in case that it is necessary to additionally add transistors for the gain control, a gain control circuit for controlling the gain can be simply constituted by adding the circuits  620  as many as it is required to achieve a desired gain.  
         [0182]     Also, in the description above, there is provided a plurality of transistors to control gains in multiple steps. Accordingly, the number of these transistors may be increased depending on the gain control characteristics.  
         [0183]      FIG. 7  is a circuit diagram of a high linearity programmable gain amplifier using a switch according to a third embodiment of the present invention.  
         [0184]     As shown in  FIG. 7 , a high linearity programmable gain amplifier using a switch includes an attenuating portion  710 , an amplifying portion  720  and a linearity portion  730 .  
         [0185]     Since the attenuating portion  710  and the amplifying portion  720  were already described with reference to  FIG. 3  and the linearity portion  730  was also described with reference to  FIG. 4  to  FIG. 6 , only the systematic operation between these elements will be explained.  
         [0186]     &lt;Construction&gt; 
         [0187]     The attenuating portion  710  includes a first attenuating part  711 , a second attenuating part  712 , a third attenuating part  713 , and a fourth attenuating part  714 .  
         [0188]     The amplifying portion  720  includes a first amplifying part  721 HG and a second amplifying part  721 LG.  
         [0189]     The linearity portion  730  includes a linear amplifier element  771 .  
         [0190]     &lt;Connection&gt; 
         [0191]     The output of the attenuating portion  710  is applied to the input terminal of the amplifying portion  720 .  
         [0192]     The output of the amplifying portion  720  is applied to the input terminal of the linearity portion  730 .  
         [0193]     &lt;Operation&gt; 
         [0194]     A signal output from the amplifying portion  720  is applied to the input terminal of the linearity portion  730 , and the linear amplifier element  771  of the amplifying portion  720  uses the high linearity programmable gain amplifier shown in  FIG. 4  to  FIG. 6  to enhance the linearity.  
         [0195]     The linear amplifier element  771  has been described with reference to  FIG. 4  to  FIG. 6  already.  
         [0196]     In the attenuating portion  710 , a signal is attenuated by the first attenuating part  711 , the second attenuating part  712 , the third attenuating part  713  and the fourth attenuating part, and then the attenuated signal is selectively amplified by first amplifying part  721 HG and the second amplifying part  721 LG in the amplifying portion  720 . Further in order to increase the linearity of the selectively amplified signal, the source follower circuit is utilized.  
         [0197]     In conclusion, in accordance with the present invention, gains of the amplifier are programmably controlled over a wide range in case of low gains. Further, when the amplifier circuit operates with a high gain, it is possible to ensure excellent noise figure. Further, since the gain control is achieved by the channel width functions of the transistors in the linearity portion  730   n , the gain control circuit in accordance with the present invention has the insensible characteristic with respect to a process, an environmental temperature, fluctuation of voltage, and et al. Thus, it is possible to ensure precision and stability of the control and. Also, since the gain is determined by the channel width function of a transistor, the gain control range can be easily expanded by increasing the number of transistors which are arranged in multiple stages, thereby ensuring wide bandwidth and high and excellent linearity  
         [0198]     The foregoing embodiment and advantages are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. Also, the description of the embodiments of the present invention is intended to be illustrative, and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.  
         [0199]     The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.