Abstract:
In a gamma voltage generator and gamma voltage generating method that can tune the gamma voltages individually, several gamma currents of a same magnitude are generated for each to flow through a variable resistive element to generate a variable common voltage and several variable voltages, from which a common gamma voltage and several first gamma voltages are generated. By use of the symmetric property of the gamma curve corresponding to those gamma voltages to be generated, several voltages are generated by mapping the first gamma voltages with the common gamma voltage as the center axis, and from which several second gamma voltages are derived. The common gamma voltage and the first and second gamma voltages are provided for those gamma voltages corresponding to the gamma curve.

Description:
FIELD OF THE INVENTION 
   The present invention relates generally to a gamma voltage generator and gamma voltage generating method, and more particularly, to a gamma voltage generator and method thereof to generate a plurality of gamma voltages that can be individually adjusted. 
   BACKGROUND OF THE INVENTION 
   Thin film transistor liquid crystal display (TFT-LCD) requires gamma voltage generator to generate gamma voltages corresponding to a gamma curve related to the characteristics of the TFT-LCD to adjust its display effect. Specifically, the gamma curve is typically symmetric in the manner that it has a central gamma voltage and two groups of gamma voltages symmetric to each other with the central gamma voltage as the symmetric center thereof. FIG.  1  shows a conventional gamma voltage generator  10 , which comprises a voltage divider  12  connected between a supply voltage V S  and ground GND, and the voltage divider  12  is composed of several resistors R 1 , R 2 , R 3 , . . . , R k+1  connected in series, so as to divide the supply voltage V S  to be several voltages V R1 , V R2 , V R3 , . . . , V Rk  that are further buffered by respective operational amplifiers AMP 1 , AMP 2 , AMP 3 , . . . , AMP k  to output the gamma voltages V G1 , V G2 , V G3 , . . . , V Gk . Since the gamma voltage generator  10  generates the gamma voltages by the voltage divider  12  composed of several resistors connected in series, whenever any one among these resistors in the voltage divider  12  is adjusted to tune the corresponding gamma voltage, all the other gamma voltages are also altered in the same time. In order to keep the other gamma voltages correct, any tuning among these gamma voltages requires the overall change of the resistors, and which is time-consuming and inconvenient in use. 
   To improve the above disadvantage, another gamma voltage generator  20  is proposed, as shown in  FIG. 2 , in which the gamma voltages V G1 , V G2 , V G3 , . . . , V Gk  are generated from a supply voltage V S  divided by resistor pairs [R 10 , R 12 ], [R 20 , R 22 ], [R 30 , R 32 ], . . . , [R k0 , R k2 ], respectively. When the gamma voltage generator  20  is desired to be adjusted with any one of the gamma voltages V G1 , V G2 , V G3 , . . . , V Gk , only the corresponding resistor pair is changed. Even though the gamma voltage generator  20  can be adjusted with its gamma voltages individually, the number of the resistors that are external to the chip they are connected is twice of that required by the gamma voltage generator  10 , and as a result, the circuit of the gamma voltage generator  20  becomes more complex. Moreover, the chip using such gamma voltage generators is required to prepare more pins for the generated gamma voltages. 
   Therefore, it is desired a gamma voltage generator that requires less pins when it is used and is able to individually tune the gamma voltages it generates. 
   SUMMARY OF THE INVENTION 
   An object of the present invention is to propose a gamma voltage generator and gamma voltage generating method that is able to tune the gamma voltages individually. 
   Another object of the present invention is to propose a gamma voltage generator and gamma voltage generating method that requires fewer pins for the chip to connect thereto. 
   In a gamma voltage generator and gamma voltage generating method, according to the present invention, a plurality of variable resistive elements are supplied respectively with a plurality of gamma currents of a same magnitude from a current source to generate a variable common voltage and a plurality of variable voltages, from which a common gamma voltage and a plurality of first gamma voltages are generated, a mirror mapping circuit generates a plurality of mapped voltages from the first gamma voltage with the common gamma voltage as a reference and from which a plurality of second gamma voltages are generated. The first and second gamma voltages are symmetric to each other with the common gamma voltage as the central axis, and the common gamma voltage and the first and second gamma voltages are thus provided for the gamma voltages corresponding to a gamma curve. 

   
     BRIEF DESCRIPTION OF DRAWINGS 
     These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  shows a conventional gamma voltage generator; 
       FIG. 2  shows another conventional gamma voltage generator; 
       FIG. 3  shows a gamma voltage generator according to the present invention; 
       FIG. 4  shows a current mirror for the gamma voltage generator shown in  FIG. 3 ; 
       FIG. 5  shows a gamma curve of the gamma voltage generator shown in  FIG. 3 ; 
       FIG. 6  shows an embodiment mirror mapping circuit for the gamma voltage generator shown in  FIG. 3 ; and 
       FIG. 7  shows another embodiment mirror mapping circuit for the gamma voltage generator shown in  FIG. 3 . 
   

   DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 3  shows a gamma voltage generator  100  according to the present invention, which comprises several independent voltage sources  102  to  112  to provide a variable common voltage V COM  and several variable voltages V 1  to V 5  to buffer operational amplifiers  114  to  124 , to further generate a common gamma voltage V GCOM  and several gamma voltages V G1  to V G5 , and a mirror mapping circuit  136  to generate several mapped voltages V 6  to V 10  by mapping the gamma voltages V G1  to V G5  with the common gamma voltage V GCOM  as a reference to buffer operational amplifiers  126  to  134  to further generate gamma voltages V G6  to V G10 . In the voltage sources  102  to  112 , several variable resistors R COM  and R 1  to R 5  each is supplied with a gamma current I S  that has a same magnitude for each of the voltage sources  102  to  112  to generate the voltages V COM  and V 1  to V 5 . If any one of the gamma voltages V GCOM  and V G1  to V G5  is desired to be tuned individually, only the corresponding resistor among R COM  and R 1  to R 5  has to be changed. Furthermore, since the gamma voltages V G6  to V G10  are generated by mapping the gamma voltages V G5  to V G1 , respectively, with the common gamma voltage V GCOM  as the mapping reference, tuning the gamma voltages V COM  and V 1  to V 5  will automatically tuning the gamma voltages V G6  to V G10  in the same time. 
   A current mirror  30 , as shown in  FIG. 4 , provides the gamma currents I S  for the resistors R COM  and R 1  to R 5 , and the current mirror  30  comprises a reference branch  32  connected with a reference current I ref  provided by a current source  46 , and several mirror branches  34 ,  36 ,  38 ,  40 ,  42  and  44  to mirror the reference current I ref , respectively, to generate the respective gamma currents I S  for the resistors R COM  and R 1  to R 5  of the voltage sources  102  to  112 . The current source  46  comprises a reference resistor R S  connected between ground GND and a transistor  462  that is further connected to the reference branch  32 , and an operational amplifier  464  with a non-inverted input connected to a reference voltage V ref , an inverted input connected to the resistor RS and the transistor  462 , and an output connected to the gate of transistor  462 . For
 
 I   S   =I   ref   =V   ref   /R   S ,  [EQ-1]
 
adjustment of either the reference resistor R S  or the reference voltage V ref  will change the magnitude of the gamma current I S .
 
   Referring to  FIG. 3  for the gamma voltage generator  100 , the first group of the gamma voltages V G1  to V G5  and the other group of the gamma voltages V G6  to V G10  generated by mapping the first group of the gamma voltages V G1  to V G5  are symmetric to each other with respect to the common gamma voltage V GCOM  as the symmetric center, corresponding to a gamma curve  138  as shown in  FIG. 5 . 
   In more detail, using the symmetric property of the gamma curve, the common gamma voltage V GCOM  and the first gamma voltages V G1  to V G5  are generated first, and then the common gamma voltage V GCOM  is used as the center axis to map the first gamma voltages V G1  to V G5  to generate the second gamma voltages V G6  to V G10 . In other words, the first gamma voltages V G1  to V G5  and the second gamma voltages V G6  to V G10  are symmetric to each other with the common gamma voltage V GCOM  as their center. Since the second gamma voltages V G6  to V G10  are directly generated from the common gamma voltage V GCOM  and the first gamma voltages V G1  to V G5 , no pins are required for them for the chip and thus the number of the pins are reduced by a half. 
     FIG. 6  shows an embodiment for the mirror mapping circuit  136  shown in  FIG. 3 . To generate the gamma voltage V G6 , for example, an operational amplifier  140  has a non-inverted input connected with the common gamma voltage V GCOM , an inverted input connected with the gamma voltage V G5  through a resistor  142 , and another resistor  144  connected between the inverted input and the output of the operational amplifier  140 . For
 ( V   G6   −V   GCOM )/ R   144 =( V   GCOM   −V   G5 )/ R   142 ,  [EQ-2] 
where R 144  and R 142  are the resistances of the resistors  144  and  142 , respectively, and when R 144 =R 142 , it is obtained
 | V   G6   −V   GCOM   |=|V   G5   −V   GCOM |,  [EQ-3] 
and obviously, the gamma voltages V G5  and V G6  are symmetric to each other with respect to V GCOM  as the center axis.
 
     FIG. 7  shows another embodiment for the mirror mapping circuit  136  shown in  FIG. 3 . Again, to generate the gamma voltage V G6 , three current mirrors  146 ,  148  and  150 , and three resistors  152 ,  154  and  156  of a same resistance are used. The current mirror  146  has its reference branch  1462  connected to a current source  164 , and its mirror branch  1464  connected to the resistor  154  and the mirror branch  1504  of the current mirror  150 . The current source  164  provides a current I 1  for the reference branch  1462  according to the gamma voltage V GCOM , and it comprises a resistor  152  connected between ground GND and a transistor  159  that is further connected to the reference branch  1462  of the current mirror  146 , and an operational amplifier  158  with its non-inverted input connected to the gamma voltage V GCOM , inverted input connected to the resistor  152 , and output connected to the gate of the transistor  159 . The current mirror  148  has a reference branch  1482  connected to a current source  166 , and a mirror branch  1484  connected to the reference branch  1502  of the current mirror  150 . The current source  166  provides a current I 3  for the reference branch  1482  according to the gamma voltage V G5 , and it comprises a resistor  156  connected between ground GND and a transistor  161  that is further connected to the reference branch  1482  of the current mirror  148 , and an operational amplifier  160  with its non-inverted input connected to the gamma voltage V G5 , an inverted input connected to the resistor  156 , and output connected to the gate of the transistor  161 . M, N and P denoted in the three current mirrors  146 ,  148  and  150  represent the channel widths of the transistors besides thereto. Due to the gamma voltage V GCOM  connected to non-inverted input of the operational amplifier  158 , a voltage V GCOM ′ is present on the inverted input of the operational amplifier  158  and applied to the resistor  152 , and thus a current I 1  is induced on the reference branch  1462  of the current mirror  146 . For the ratio of the channel widths of the transistors in the current mirror  146  is M:2M, the output of the mirror branch  1464  is double, i.e., I 2 =2×I 1 . On the other hand, due to the gamma voltage V G5  connected to the non-inverted input of the operational amplifier  160 , a voltage V G5 ′ is present on the inverted input of the operational amplifier  160  and applied to the resistor  156 , and thus a current I 3  is generated on the reference branch  1482  of the current mirror  148 . For the ratio of the channel widths of the transistors in the current mirror  148  is N:N, the output of the mirror branch  1484  is the same, i.e., I 4 =I 3 . The reference branch  1502  of the current mirror  150  receives the mirrored current I 4 , and the ratio of the channel widths of the transistors in the current mirror  150  is P:P, it is thus obtained that the mirrored current I 5 =I 4 , and further I 5 =I 3 , since I 4 =I 3 . The gamma voltage output from the node  162  is
   V   G6 =( I   2   −I   5 )× R   154   =I   2   ×R   154   −I   5   ×R   154 ,  [EQ-4] 
where R 154  is the resistance of the resistor  154 . Since the resistors  152 ,  154  and  156  have the same resistance, and I 2 =2×I 1 , I 5 =I 3 , the gamma voltage
 
                   V   G6     =           (     2   ×     I   1       )     ×     R   152       -       (     I   3     )     ×     R   156         ⁢     
     ⁢           =         2   ⁢     (       I   1     ×     R   152       )       -     (       I   3     ×     R   156       )       ⁢     
     ⁢           =       2   ⁢     V     GCOM   ′         -     V     G5   ′                     [     EQ   ⁢     -     ⁢   5     ]               
Based on the principle of the virtual short between the non-inverted and inverted inputs of an operational amplifier, the non-inverted and inverted inputs of the operational amplifiers  158  and  160  are the same voltages, that is
 V GCOM =V GCOM ′, 
and
 V G5 =V G5 ′. 
As a result, from equation EQ-5,
   V   G6 =2 V   GCOM   ′−V   G5 ′=2 V   GCOM   −V   G5 ,   V   G6   −V   GCOM   =V   GCOM   −V   G5 , 
and
 | V   G6   −V   GCOM   |=|V   G5   −V   GCOM |.  [EQ-6] 
As for the situation of equation EQ-3, the gamma voltages V G5  and V G6  are symmetric to each other with respect to V GCOM  as the center axis.
 
   While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.