Abstract:
A non-linear operational circuit with reference voltage sources and switching means, wherein the output voltage of the operational circuit is compared with the reference voltages to open and close the switching means in accordance with their magnitudes relative to one another and thereby to non-linearly vary the output voltage of the operational circuit in response to changes in the input voltage. The reference voltage sources and the switching means are connected in series between the output terminal and the ground terminal of the operational circuit, whereby at the inflection point at which the ratio of the change in the output voltage of the operational circuit to the change in the input voltage changes, the output voltage is caused to change continuously.

Description:
FIELD OF THE INVENTION 
     The present invention relates to non-linear operational circuits having a predetermined non-linear relationship between the input and the output, and more particularly the invention relates to a circuit having arbitrary inflection points and capable of possessing a desired input-output characteristic. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a connection diagram of a prior art non-linear operational circuit. 
     FIG. 2 is an input-output characteristic diagram of the operational circuit shown in FIG. 1. 
     FIG. 3 is a connection diagram showing an embodiment of a non-linear operational circuit according to the present invention. 
     FIG. 4 is an input-output characteristic diagram of the operational circuit shown in FIG. 3. 
     FIG. 5 is a connection diagram showing a second embodiment of the circuit according to the invention. 
     FIG. 6 is an input-output characteristic diagram of the operational circuit shown in FIG. 5. 
    
    
     DETAILED DESCRIPTION 
     In a known type of non-linear operational circuit, such as one disclosed in Japanese Pat. No. 51-28486, the output voltage of the operational circuit changes in a step fashion at the inflection point of the operational circuit output. 
     FIG. 1 illustrates one example of the prior art non-linear operational circuits disclosed in Japanese Pat. No. 51-28486, and FIG. 2 shows an input-output characteristic diagram of the operational circuit shown in FIG. 1. 
     In FIG. 1, symbol E i  designates the input voltage, and E o  the output voltage produced across a load resistor R l  connected in series with an input resistor R i . A series circuit comprising a resistor R 1  and an NPN transistor Tr 1  and another series circuit comprising a resistor R 2  and an NPN transistor Tr 2  are connected in parallel with the load resistor R l  thus providing a pair of switching circuits. Numerals 1 and 2 designate amplifiers each having two input terminals of the polarities shown, e.g., linear ICs which respectively receive the output voltage E 0  as their one input through resistors R 3  and R 4  and also receive as their reference inputs bias voltages V 1  and V 2  having a relation V 2  &gt;V 1  &gt;O, thereby comparing the output voltage E 0  with the bias voltages V 1  and V 2 , respectively. The outputs of the amplifiers 1 and 2 are respectively connected to the bases of the transistors Tr 1  and Tr 2  through base current limiting resistors R 5  and R 6 , so that the transistors Tr 1  and Tr 2  are turned on and off in response to the outputs of the amplifiers 1 and 2 so as to control the respective switching circuits. Symbols D 1  and D 2  designate diodes of the polarities shown, whereby when a forward voltage is applied to the diodes D 1  and D 2 , the base-emitter sections of the transistors Tr 1  and Tr 2  are short-circuited. 
     With the construction shown in FIG. 1, assuming that E 01  represents the value of the output voltage E 0  just prior to attaining the bias voltage V 1 , it is given by E 01  =(R l  /R i  +R l ) E i , since the transistor Tr 1  is off, and also assuming that E 02  represents the value of the output voltage E 0  attaining the bias voltage V 1 , then it is given by ##EQU1## since the transistor Tr 1  is turned on and the resistor R 1  is operative in the voltage dividing circuit. Here, R 1  //R l  represents the resistance of the circuit including parallel connected resistors R 1  and R l . Since ##EQU2## we obtain ##EQU3## and consequently a relation E 01  =E 02  does not hold unless R l  =0. As a result, when the output voltage E 0  reaches the bias voltage V 1 , the output voltage E 0  changes in a step fashion and the output voltage cannot change continuously. In other words, with the characteristic curve of FIG. 2, the output voltage E 0  changes in a step fashion and becomes discontinuous at the inflection point at which the value of the gain dE 0  /dE i  changes. 
     The present invention is intended to overcome the above-mentioned deficiency in the prior art, namely, the output voltage of a non-linear operational circuit is caused to change continuously and not in a step fashion at the inflection point of the output voltage. 
     In accordance with the present invention, there is provided a non-linear operational circuit wherein a series circuit including a resistor, an analog switch and a reference voltage source is connected between an output terminal and a ground terminal, and the analog switch is opened and closed by a comparator adapted to receive the associated reference voltage as its reference input, thus, preventing the characteristic curve from deviating at around the inflection point of the output voltage at the output of the operational circuit and thereby providing a desired continuous non-linear input-output characteristic. The non-linear operational circuit may include a plurality of the series circuits as occasion demands. 
     It is therefore the object of this invention to provide a non-linear operational circuit which overcomes the foregoing deficiency of the prior art, namely, deviation of the output voltage characteristic curve at around the inflection point on the curve and thereby ensuring any desired input-output characteristic. 
     Now, preferred embodiments of the present invention will be described with reference to the accompanying drawings. 
     Referring to FIG. 3 showing a first embodiment of the invention, symbol E i  designates the input voltage, and E 0  the output voltage generated through an input resistor R i . A series conduit comprising a resistor R 1 , an analog switch S 1  (e.g., the RCA IC CD4066) and a reference voltage source V 1  and a similar series circuit comprising a resistor R 2 , an analog switch S 2  and a reference voltage source V 2  are connected between an output terminal P 3  and a ground terminal P 2  thus providing first and second switching circuits. Numerals 1 and 2 designate comparators (e.g., the Motorola IC MC3302) each having two input terminals of the polarities shown and designed to receive as their one input the voltage at the output terminal P 3  and as their reference inputs reference voltages V 1  and V 2  having a relation 0&lt;V 1  &lt;V 2  so as to compare the output voltage E 0  with the reference voltages V 1  and V 2 , respectively. The outputs of the comparators 1 and 2 are respectively connected to the control terminal C of the analog switches S 1  and S 2 , so that in response to the outputs of the comparators 1 and 2, the analog switches S 1  and S 2  are opened and closed to control the associated switching circuits. Here, the like reference numerals are used to designate the input resistor, the resistors connected in series with the analog switches, etc., which correspond to the counterparts in FIG. 1. 
     With the construction described above, the operation and characteristic of the first embodiment circuit will now be described with reference to FIG. 4. 
     In the Figure, when 
     
         E.sub.0 ≦V.sub.1                                    (1) 
    
     since the outputs of the comparators 1 and 2 are both at a low level (hereinafter simply designated by a logical symbol &#34;0&#34;) and thus both of the analog switches S 1  and S 2  are off, the resulting gain is given by 
     
         dE.sub.0 /dE.sub.i =1. 
    
     On the other hand, when 
     
         V.sub.1 &lt;E.sub.0 ≦V.sub.2                           (2) 
    
     since the output of the comparator 1 is at a high level (hereinafter simply designated by a logical symbol &#34;1&#34;) and the output of the comparator 2 is at &#34;0&#34; thus turning the analog switch S 1  on and the analog switch S 2  off, the resulting gain is given by ##EQU4## 
     Further, when 
     
         V.sub.2 &lt;E.sub.0                                           (3) 
    
     since the outputs of comparators 1 and 2 are both at &#34;1&#34; and consequently the analog switches S 1  and S 2  are both turned on, the resulting gain is given by ##EQU5## where R 1  //R 2  is the combined resistance of the resistors R 1  and R 2  when connected in parallel. 
     Since a relation ##EQU6## always holds among the gains in the above cases (1), (2) and (3), as shown in FIG. 4, the circuit shown in FIG. 3 has an input-output characteristic with a gradually descreasing gain. It is to be noted that the number of inflection points on the input-output characteristic may assume any given value greater than 1 depending on the number of switching circuits. 
     With the circuit construction shown in FIG. 3, we obtain E 01  =E i  just prior to the point of the output voltage E 0  attaining the reference voltage V 1 , and at the point of the output voltage E 0  attaining the reference voltage V 1 , we obtain ##EQU7## from the equation ##EQU8## Here, since E 02  =V 1 , we obtain E 02  =E i . If a load resistor is connected between the output terminals P 2  and P 3 , this will only cause a change in the gain dE 0  /dE i  and consequently there will be no danger of the outputs voltage E 0  being changed in a step fashion at the inflection point. 
     On the other hand, with the second embodiment shown in FIG. 5, which is almost identical in construction with the first embodiment of FIG. 3 and in which the like component parts are designated by the like reference numerals as in FIG. 3, the input-output characteristic shown in FIG. 6 is obtained. 
     The embodiment of FIG. 5 differs from the circuit shown in FIG. 3 in that the polarities of the two input terminals of the comparators 1 and 2 are reversed. With the circuit shown in FIG. 5, as in the case of the circuit of FIG. 3, the analog switches S 1  and S 2  are opened and closed in accordance with the output voltage E 0 . 
     In other words, when 
     
         E.sub.0 ≦V.sub.1                                    (4) 
    
     the analog switches S 1  and S 2  are both turned on and consequently the resulting gain is given by ##EQU9## 
     When 
     
         V.sub.1 &lt;E.sub.0 --V.sub.2                                 (5) 
    
     the analog switch S 1  is turned off and the analog switch S 2  is turned on and consequently the resulting gain is driven by ##EQU10## 
     Further, when 
     
         V.sub.2 &lt;E.sub.0                                           (6) 
    
     the analog switches S 1  and S 2  are both turned off and consequently the resulting gain is driven by 
     
         (dE.sub.0 /dE.sub.i)=1 
    
     Here, the gains in the above cases (4), (5) and (6) have a relation ##EQU11## thus providing an input-output characteristic with a gradually increasing gain as shown in FIG. 6. 
     Also with the construction shown in FIG. 5, as is the case with the construction shown in FIG. 3, the output voltage E o  has the same value of just prior to attaining and after attaining the reference voltage V 1 . Thus, even if a load resistor is connected between the output terminals P 2  and P 3 , the output voltage E o  will not be changed in a step fashion.