Abstract:
A charge pump and method converts an input voltage to a boosted voltage having a magnitude or polarity that is different from that of the input voltage. The input voltage is adjusted so that it has a relatively large magnitude until the boosted voltage approaches a target voltage. Therefore, the charge pump and method can more quickly charge a capacitive load. The magnitude of the input voltage may be proportional to the difference between the magnitude of a reference voltage and the magnitude of the boosted voltage. The magnitude of the input voltage may alternatively be substantially equal to the magnitude of a supply voltage until the magnitude of the boosted voltage is within a predetermined range of the target voltage, at which point it may be proportional to the difference between the magnitude of a reference voltage and the magnitude of the boosted voltage.

Description:
TECHNICAL FIELD 
   This invention relates generally to charge pumps, and, more particularly, to a charge pump that more quickly charges a large capacitive load to a reference voltage. 
   BACKGROUND OF THE INVENTION 
   In many electronic devices, it is necessary to generate a voltage having a magnitude that is greater than the magnitude of a supply voltage providing power to the device. In other applications, it is necessary to generate a voltage having a polarity that is different from the polarity of a supply voltage providing power to the device. Charge pumps are often used for both of these purposes. Although a wide variety of charge pumps have been developed, most charge pumps use capacitors to obtain a boosted voltage or a voltage having a different polarity. To generate a boosted voltage, the supply voltage V CC  is typically applied to a first terminal of the capacitor while the second terminal of the capacitor is held at ground during a first phase of a cycle. After the capacitor has been charged to V CC , the first terminal of the capacitor is coupled to a load that is to receive the boosted voltage, and the supply voltage V CC  is applied to the second terminal of the capacitor during a second phase of the cycle. In so far as the capacitor was charged to V CC  during the first phase when the second terminal was connected to ground, the voltage on the first terminal is approximately twice V CC  during the second phase when the second terminal is connected to V CC . The charge pump repetitively alternates between the first and second phases, each cycle generating an output voltage that is approximately twice the supply voltage V CC . By using multiple boost stages, output voltages that are a larger multiple of the supply voltage V CC  can be generated. 
   To generate a voltage having a polarity that is different from the polarity of the supply voltage V CC , the capacitor is typically charged in the same manner as described above, but the terminals connected in a different manner during the second phase of each cycle. Specifically, during the first phase, the supply voltage V CC  is again applied to the first terminal of the capacitor while the second terminal of the capacitor is held at ground. After the capacitor has been charged to V CC , the first terminal of the capacitor is coupled to ground, and the second terminal of the capacitor is connected to the load that is to receive the opposite polarity voltage during the second phase. In so far as the capacitor was charged to V CC  during the first phase when the second terminal was connected to ground, the voltage on the second terminal is approximately −V CC  during the second phase when the first terminal is connected to ground. 
   Charge pumps are presently used in a wide variety of applications. For example, charge pumps are typically used in memory devices to provide a negative substrate voltage or to provide a boosted voltage that can be applied to the gate of an NMOS transistor to allow the transistor to couple the supply voltage to an output node. Charge pumps are also used in CMOS imagers to generate voltage of different polarities and magnitudes during various operations carried out by the imagers. For example, charge pumps are commonly used to supply power having a polarity that is different from that of the supply voltage to the imaging array of CMOS imagers. 
   A typical charge pump  10  that can be used to supply a negative voltage when powered by a positive supply voltage is shown in  FIG. 1 . The charge pump  10  includes a source  14  of a reference voltage V R , which is applied to a voltage boost circuit  16  formed by a capacitor  20  having a capacitance C C , two switches  24 ,  26  that are closed during the first phase of each cycle, and two switches  30 ,  32  that are closed during the second phase of each cycle. A load L is connected to an output node  34  of the charge pump  10 . The switches  24 ,  26  that are closed during the first phase of each cycle are open during the second phase, and the switches  30 ,  32  that are closed during the second phase are open during the first phase. The load L is assumed to be the array of a CMOS imager, which is highly capacitive, with a capacitance of C L . The voltage across the capacitive load C L  is designated V L . 
   In operation, the reference voltage source  14  is connected to the capacitor  20  by the switch  26  during the first phase of each cycle, while the switch  24  connects the other terminal of the capacitor  20  to ground. The capacitor  20  is therefore charged to −V R  during the first phase. During the second phase of each cycle, the switch  32  is closed to connect the lower terminal of the capacitor  20  to ground, and the other switch  30  is closed to connect the other terminal of the capacitor  20  to the load L. Insofar as the capacitor  20  was charged to −V R , the capacitive load C L  is eventually charged to −V R  after a sufficient number of cycles. 
   The time required for a charge pump, including the charge pump  10  shown in  FIG. 1 , to output a target voltage is sometimes referred to as the time constant of the charge pump. In general the time constant of a charge pump driving a resistive load is very short as long as the current demands of the load do not exceed the current that can be supplied by the charge pump. However, the time constant of a charge pump driving a capacitive load can be very long because the voltage applied to the load incrementally increases through a charge sharing process each cycle. The time constant of the charge pump  10  is affected by the magnitude of the capacitance C C  relative to the load capacitance C L , as well as the difference between the reference voltage V R  and the voltage V L  to which the capacitive load C L  has already been charged. Specifically, the change ΔV in the load voltage V L  when driven by the charge pump  10  is given by the formula:
 
 ΔV=[C   C /( C   C   +C   L )]*[ V   R   −V   L ].  Equation 1
 
It is thus seen that the incremental increase ΔV in the load voltage V L  each cycle is proportional to two factors. The first factor is the difference between the reference voltage V R  supplied by the charge pump  10  and the load voltage V L  at the start of the cycle. The second factor is the ratio of the charge pump capacitance C C  to the sum of the charge pump capacitance C C  and the load capacitance C L . If the load capacitance C L  is very much greater than the charge pump capacitance C C , Equation 1 can be effectively simplified to:
 
 ΔV=[C   C   /C   L   ]*[V   R   −V   L ].  Equation 2.
 
In such case, the incremental increase ΔV in the load voltage V L  is proportional to the ratio of the charge pump capacitance C C  to the load capacitance C L  as well as to the difference between the reference voltage V R  and the load voltage V L .
 
   It can be seen from Equation 2 that incremental increase ΔV of the load voltage V L  will be very small if the load capacitance C L  is significantly greater than the charge pump capacitance C C . It can also be seen from Equation 2 that the increase ΔV of the load voltage V L  will become smaller as the load voltage V L  approaches the reference voltage V R  . Both of these factors can result in very large time constants for charge pumps driving a large capacitive load. This problem is particularly severe for charge pumps supplying power to CMOS imagers having a polarity that is different from that of the supply voltage because, as mentioned above, the imaging array receiving such voltage has a very large capacitance. As a result, the time constant of charge pumps supplying power to the arrays of CMOS imagers can be undesirably long. 
   There is therefore a need for a charge pump having a shorter time constant, particularly when the charge pump is driving a highly capacitive load. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic diagram of a conventional charge pump. 
       FIG. 2  is a schematic diagram of a charge pump according to one example of the invention. 
       FIG. 3  is a schematic diagram of a charge pump according to another example of the invention. 
       FIG. 4  is a schematic diagram of a charge pump according to another example of the invention in which the time constant of the charge pump is further reduced. 
       FIG. 5  is a block diagram of a CMOS imager using one or more of the charge pumps shown in  FIGS. 2-4  or a charge pump according to another example of the invention. 
       FIG. 6  is a block diagram of a memory device using one or more of the charge pumps shown in  FIGS. 2-4  or a charge pump according to another example of the invention. 
   

   DETAILED DESCRIPTION 
   A charge pump  40  according to one example of the invention is shown in  FIG. 2 . The charge pump  40  includes the same voltage boost circuit  16  used in the charge pump of  FIG. 1 , including the capacitor  20  and the switches  24 ,  26 ,  30 ,  32 , and they operate in essentially the same manner. However, instead of using the reference voltage source  14  ( FIG. 1 ), the charge pump  40  uses a reference voltage circuit  42  that includes a reference voltage source  44  producing a reference voltage V R , and a differential amplifier  48 . The differential amplifier  48  preferably has a gain G of greater than unity, and more preferably has a gain G that is substantially greater than unity. 
   In operation, the voltage V L  is assumed to be initially zero voltage when the charge pump  40  is initialized. As a result, the reference voltage generator applies a voltage of V R  to the positive input of the differential amplifier  48 . The negative input of the differential amplifier  48  is connected to ground so that the amplifier  48  outputs a voltage of G*V R  or V CC , whichever has a lower magnitude. For example, if V R  is equal to 2 volts, G is equal to 50, and V CC  is equal to 10 volts, the amplifier  48  will output a voltage of 10 volts. As a result, the capacitor  20  will be charged to −10 volts before the switch  30  couples it to the highly capacitive load C L . Insofar as this voltage is substantially higher than the reference voltage V R , the charge pump  40  will charge the capacitive load C L  substantially faster than the charge pump  10  was able to charge the load L. 
   As the capacitive load C L  becomes more negatively charged, the voltage V L  becomes more negative. As the voltage V L  decreases, the voltage V A  applied to the input of the differential amplifier  48  decreases since the voltage V A  applied to the amplifier is given by the equation V A =V L +V R . Thus, using the above example in which V R  is equal to 2 volts, when the voltage V L  has decreased to −1 volt, the voltage V A  will be 1 volt. However, unlike the charge pump  10  of  FIG. 1 , the voltage to which the capacitor  20  is charged does not immediately decrease as the voltage V L  decreases. In fact, the capacitor  20  will continue to be charged to −V CC  until G*V A  is substantially equal to the supply voltage V CC , i.e., G*(V L +V R )=V CC . Again using the above example, the capacitor  20  will continue to be charged to −10 volts until 50(V L +2)=10, or V L =−1.8 volts. In contrast, using the same value of V R =2, the capacitor  20  used in the charge pump  10  of  FIG. 1  is charged to only −0.2 volts when V L =−1.8 volts. 
   When G*(V L +V R )=−V CC , i.e., V L =−1.8 using the above example, the negative voltage to which the capacitor  20  is charged will be gradually reduced until the capacitor is charged to a voltage that causes the voltages to be stable. In such case, the voltage at the output of the amplifier, i.e., G*(V L +V R ), will be equal to −V L , i.e., G*(V L +V R )=−V L . Solving for V L  yields V L =−V R [G/(G+1)]. Again, using the above example, the voltages in the charge pump  40  will be stable when V L =−2[ 50/51] or −1.96 volts. Compared to the charge pump  10 , the much greater voltage to which the capacitor  20  is charged in the charge pump  40  throughout the initialization of the charge pump  40  results in a markedly faster time constant. 
   The devices for implementing the switches  24 ,  26 ,  30 ,  32  are conventional as are circuitry for controlling them during the first and second phases of each cycle. Therefore, in the interest of brevity and to avoid obscuring the explanation of the more pertinent portions of the charge pump  40 , a more detailed explanation of these devices and control circuits have been omitted. 
   A charge pump  50  according to another example of the invention is shown in  FIG. 3 . The charge pump  50  is identical to the charge pump  40  shown in  FIG. 2  except that it uses a different reference voltage circuit  54 . The reference voltage circuit  54  includes a differential amplifier  56  receiving a reference voltage V R  at its positive input. The negative input of the amplifier  56  is connected to a boosting sample circuit  60  formed by two switches  62 ,  64  that are closed only during the first phase of each cycle, two switches  66 ,  68  that are closed only during the second phase of each cycle, and a capacitor  70  that retains a sample during the first phase when the switches  66 ,  68  are opened. A capacitor  74  connected between the output and the negative input of the amplifier  56  retains the voltage corresponding to the sample when the switches  62 ,  64  are opened during the second phase of each cycle. 
   In operation, during the first phase of each cycle, a voltage at the output of the amplifier  56  charges the capacitor  20  through the switch  26 . At the same time, a sample of the load voltage V L  obtained during the second phase of the prior cycle is coupled to the negative input of the amplifier  56  through the closed switches  62 ,  64  and retained by the capacitor  74 . However, the sample applied to the amplifier  74  has a polarity that is the reverse of the polarity of the load voltage V L . During the second phase of the prior cycle, the upper terminal of the capacitor is connected to the load L through the switch  66 , and the lower terminal of the capacitor is connected to ground through the switch  68 . During the first phase when the sample is applied to the amplifier  56 , the upper terminal of the capacitor  70  is switched from the load voltage V L , which is a negative voltage, to ground. As a result, the voltage at the lower terminal of the capacitor  70  transitions from ground to a positive voltage that is equal in magnitude to the negative load voltage V L . The amplifier  56  then applies a voltage to the capacitor  20  through the switch  26  that is the lesser of the supply voltage V CC  or G(V R +V L ). For example, if V R  is again 2 volts, G is again 50, and V CC  is again 10 volts, the amplifier  56  will output 10 volts until V L =−1.8 volts. Thereafter, the voltage output by the amplifier  56  will decrease linearly as V L  transitions from −1.8 volts toward −2 volts. 
   During the second phase of each cycle, the negative of the voltage applied to the capacitor  20  is applied to the load L through the switch  30  as described above. At the same time, the switches  66 ,  68  are closed to charge the capacitor  70  to the load voltage V L . The switches  62 ,  64  are open during this time, but the sample voltage applied to the amplifier  56  during the first phase is retained by the capacitor  74 . 
   A charge pump  80  according to another example of the invention in which the time constant of the charge pump is further reduced is shown in  FIG. 4 . The charge pump  80  is identical to the charge pumps  40 ,  50  with one exception. First, in addition to containing a reference voltage circuit  82  connected to the voltage boost circuit  16  including the switches  24 ,  26 ,  30 ,  32  and the capacitor  20 , it containing a second voltage boost circuit  16 ′ including a second set of switches  24 ′,  26 ′,  30 ′,  32 ′ and a second capacitor  20 ′. The switches  24 ′,  26 ′,  30 ′,  32 ′ and second capacitor  20 ′ have the same topography as the switches  24 ,  26 ,  30 ,  32  and the capacitor  20 . Further, they operate in the same manner except that the switches  24 ′,  26 ′,  30 ′,  32 ′ are operated out of phase with the correspondingly numbered switches  24 ,  26 ,  30 ,  32 . As a result, the first capacitor  20  applies a voltage to the load L during the second phase of each cycle, and the second capacitor  20 ′ applies a voltage to the load L during the first phase of each cycle. Insofar as the charge pump  80  applies a voltage to the load during both phases, the charge pump  80  has half of the time constant of the charge pumps  40 ,  50  shown in  FIGS. 2 and 3 , respectively. Alternatively, the same time constant can be maintained using a capacitors  20 ,  20 ′ that are only half the size of the capacitor  20  used in the charge pumps  40 ,  50 . 
   Although not specifically shown in the drawings, it will be understood that the charge pumps  40 ,  50 ,  80  or a charge pump according to some other example of the invention can be easily adapted to provide a positive rather than negative load voltage V L . Further, by adding additional switches and a capacitor, the charge pumps  40 ,  50  or a charge pump according to some other example of the invention can generate both a positive and a negative voltage. 
   The charge pumps  40 ,  50 ,  80  or a charge pump according to some other example of the invention can be used in a wide variety of applications. They are particularly suitable for use in a CMOS imager because the imaging arrays of such devices are highly capacitive. For example, a CMOS imager  100  shown in  FIG. 5  includes a CMOS imaging array  104  that responds to a received image to generate corresponding signals. The array  104  is coupled to a control and addressing circuit  108 , which interrogates the array  104  to output signals S I  corresponding to the image received by the array  104 . The CMOS imager  100  also includes a charge pump  110  connected to the array  104  to supply the array  104  with a negative voltage. The charge pump  100  may be one of the charge pumps  40 ,  50 ,  80  shown in  FIGS. 2 ,  3  or  4 , respectively, or a charge pump according to some other example of the invention. 
   Another application of the charge pumps  40 ,  50 ,  80  or a charge pump according to some other example of the invention is to supply various voltages in a flash memory device. With reference to  FIG. 6 , a flash memory device  120  includes an array  130  of flash memory cells arranged in banks of rows and columns. Although not shown in  FIG. 6 , the flash memory cells in the array  130  have their control gates coupled to word select lines, drain regions coupled to local bit lines, and source regions selectively coupled to a ground potential. 
   Command signals, address signals and write data signals are applied to the memory device  120  as sets of sequential input/output (“I/O”) signals transmitted through an I/O bus  134 . Similarly, read data signals are output from the flash memory device  120  through the I/O bus  134 . The I/O bus is connected to an I/O control unit  140  that routes the signals between the I/O bus  134  and an internal data bus  142 , an address register  144 , a command register  146  and a status register  148 . 
   The flash memory device  120  also includes a control logic unit  150  that receives a number of control signals, including an active low chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, an active low write enable signal WE#, an active low read enable signal RE#, and an active low write protect WP# signal. When the chip enable signal CE# is active low, command, address and data signals may be transferred between the memory device  120  and a memory access device (not shown). When the command latch enable signal CLE is active high and the ALE signal is low, the control logic unit  150  causes the I/O control unit  140  to route signals received through the I/O bus  134  to the command register  146  responsive to the rising edge of the WE# signal. Similarly, when the address latch enable signal ALE is active high and the CLE signal is low, the I/O control unit  140  routes signals received through the I/O bus  134  to the address register  146  responsive to the rising edge of the WE# signal. The write enable signal WE# is also used to gate write data signals from the memory access device (not shown) to the memory device  120 , and the read enable signal RE# is used to gate the read data signals from the memory device  120  to the memory access device (not shown). The I/O control unit  140  transfers the write data signals and read data signals between the I/O bus  134  and the internal data bus  142  when the CLE and ALE signals are both low. Finally, an active low write protect signal WP# prevents the memory device  120  from inadvertently performing programming or erase functions. The control logic unit  150  is also coupled to the internal data bus  142  to receive write date from the I/O control unit for reasons that will be explained below. 
   The status register  148  can be read responsive to a read status command. After the read status command, all subsequent read commands will result in status data being read from the status register  148  until a subsequent read status command is received. The status data read from the status register  148  provides information about the operation of the memory device  120 , such as whether programming and erase operations were completed without error. 
   The address register  146  stores row and column address signals applied to the memory device  120 . The address register  146  then outputs the row address signals to a row decoder  160  and the column address signals to a column decoder  164 . The row decoder  160  asserts word select lines corresponding to the decoded row address signals. Similarly, the column decoder  164  enables write data signals to be applied to bit lines for columns corresponding to the column address signals and allow read data signals to be coupled from bit lines for columns corresponding to the column address signals. 
   In response to the memory commands decoded by the control logic unit  150 , the flash memory cells in the array  130  are erased, programmed, or read. The memory array  130  is programmed on a row-by-row or page-by-page basis. After the row address signals have been loaded into the address register  146 , the I/O control unit  140  routes write data signals to a cache register  170 . The write data signals are stored in the cache register  170  in successive sets each having a size corresponding to the width of the I/O bus  134 . The cache register  170  sequentially stores the sets of write data signals for an entire row or page of flash memory cells in the array  130 . All of the stored write data signals are then used to program a row or page of memory cells in the array  130  selected by the row address stored in the address register  146 . In a similar manner, during a read operation, data signals from a row or page of memory cells selected by the row address stored in the address register  146  are stored in a data register  180 . Sets of data signals corresponding in size to the width of the I/O bus  134  are then sequentially transferred through the I/O control unit  140  from the data register  180  to the I/O bus  134 . Although the array  130  is typically read on a row-by-row or page-by-page basis, a selected portion of a selected row or page may be read by specifying a corresponding column address. 
   The flash memory device  120  also includes an NMOS transistor  186  having its gate coupled to receive a signal from the control logic unit  150 . When the memory device  120  is busy processing a programming, erase or read command, the control logic unit  150  outputs a high signal to cause the transistor  186  to output an active low read/busy signal R/B#. At other times, the transistor  186  is turned OFF to indicate to a memory access device that the device  120  is able to accept and process memory commands. 
   The flash memory device  120  also includes supply voltage system  200  that uses one or more of the charge pumps  40 ,  50 ,  80  or charge pumps according to some other example of the invention. The charge pumps in the supply voltage system  200  applies positive and/or negative voltages having appropriate magnitudes to one or more of the row decoder  160 , column decoder  164 , cache register  170  or data register  180  to carry out erase, programming, or read operations in the array  130 . 
   From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.