Abstract:
A switch circuit for switching between a first storage and a second storage. The switch circuit includes a switch, a control circuit, a switch control chip, and a processing chip. The control circuit is connected to the switch, the first storage, and the second storage. The control circuit either transmits power from a power supply to the first or second storage according to the switch. The switch control chip is connected to the control circuit. The processing chip is connected to the switch control chip. The control circuit controls the switch control chip to either transmit data between the processing chip and the first storage in response to the power supply powering the first storage, or transmit data between the processing chip and the second storage in response to the power supply powering the second storage.

Description:
BACKGROUND 
       [0001]    1. Technical Field 
         [0002]    The present disclosure relates to a switch circuit. 
         [0003]    2. Description of Related Art 
         [0004]    For protecting information stored in handheld devices, dual systems are used. Users can store important information in one system, and store general information in the other system. Only if the users have to read the important information, the users can operate the system which stores the important information. Software is generally used to switch the handheld device between the two systems. However, there are security risks. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0005]    Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views. 
           [0006]      FIG. 1  is a block diagram of an exemplary embodiment of a switch circuit. 
           [0007]      FIGS. 2-7  are circuit diagrams of the switch circuit of  FIG. 1 . 
       
    
    
     DETAILED DESCRIPTION 
       [0008]    The disclosure, including the accompanying drawings, is illustrated by way of example and not by way of limitation. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one. 
         [0009]    Referring to  FIG. 1 , an exemplary embodiment of a switch circuit includes a switch  10 , a control circuit  12 , a switch control chip  15 , and a processing chip  18 . 
         [0010]    The switch  10  is connected to the control circuit  12 . The control circuit  12  is connected to a first storage  1  and a second storage  2 . The control circuit  12  is further connected to the power supply  16 . The control circuit  12  either outputs power from a power supply  16  to the first storage  1  or outputs power from the power supply  16  to the second storage  2  according to the switch  10 . The control circuit  12  is further connected to the switch control chip  15 . The switch control chip  15  is connected to the processing chip  18 . The control circuit  12  further either allows transmitting of data between the processing chip  18  and the first storage  1  or between the processing chip  18  and the second storage  2  according to the switch  10 . In one embodiment, the power supply  16  supplies 3.3 volts (V). 
         [0011]    Referring to  FIG. 2 , the switch  10  is a single pole double throw switch. The control circuit  12  includes a first accessory circuit  120  and a second accessory circuit  122 . A first end of a pole  2  of the switch  10  is connected to the power supply 3.3V through a resistor R 1 . A first throw  1  of the switch  10  is connected to the first accessory circuit  120 . A second throw  3  of the switch  10  is connected to the second accessory circuit  122 . When a second end of the pole  2  contacts the first throw  1 , the first accessory circuit  120  supplies power to the first storage  100 , and data can be transmitted between the processing chip  18  and the first accessory circuit  120 . When the second end of the pole  2  contacts the second throw  2 , the second accessory circuit  122  supplies power to the second storage  2 , and data can be transmitted between the processing chip  18  and the second accessory circuit  122 . 
         [0012]    The first accessory circuit  120  includes a transistor Q 1  and a transistor Q 3 . The second accessory circuit  122  includes a transistor Q 2  and a transistor Q 4 . In one embodiment, the transistors Q 1  and Q 2  are npn transistors, and the transistors Q 3  and Q 4  are P-channel metal oxide semiconductor field effect transistors (MOSFETs). 
         [0013]    The first throw  1  of the switch  10  is grounded through a resistor R 2 . The first throw  1  is further connected to a base of the transistor Q 1  through a resistor R 3 . The second throw  3  is grounded through a resistor R 4 . The second throw  3  is further connected to a base of the transistor Q 2  through a resistor R 5 . An emitter of the transistor Q 1  is grounded. A collector of the transistor Q 1  is connected to a gate of the transistor Q 3  through a resistor R 6 . The collector of the transistor Q 1  is connected to the power supply 3.3V through two resistors R 7  and R 17  connected in series. A node between the resistors R 7  and R 17  is grounded through a capacitor C 1 . A source of the transistor Q 3  is connected to the node between the resistors R 7  and R 17 . A drain of the transistor Q 3  is grounded through capacitors C 2  and C 3  connected in parallel. The drain of the transistor Q 3  is connected to power terminals VCC 0  and VCC 1  of the first storage  100  (shown in  FIG. 5 ) for outputting a first power signal ND_PWR 1  to the first storage  100 . 
         [0014]    An emitter of the transistor Q 2  is grounded. A collector of the transistor Q 2  is connected to a gate of the transistor Q 4  through a resistor R 8 . The collector of the transistor Q 2  is connected to the power supply 3.3V through resistors R 9  and R 19  connected in series. A node between the resistors R 9  and R 19  is grounded through a capacitor C 4 . A source of the transistor Q 4  is connected to the node between the resistors R 9  and R 19 . A drain of the transistor Q 4  is grounded through capacitors C 5  and C 6  connected in parallel. The drain of the transistor Q 4  is connected to power terminals VCC 0  and VCC 1  of the second storage  200  (shown in  FIG. 6 ) for outputting a second power signal ND_PWR 2 . The drain of transistor Q 4  is grounded through resistors R 10  and R 11  connected in series. A node between the resistors R 10  and R 11  outputs a control signal SW. 
         [0015]    Referring to  FIGS. 3 to 7 , the switch control chip  15  includes a first control chip  150  and a second control chip  152 . A power terminal VCC of the first control chip  150  is connected to the power supply 3.3V through a resistor R 12 , and is grounded through a capacitor C 7 . A power terminal VCC of the second control chip  152  is connected to the power supply 3.3V through a resistor R 13 , and is grounded through a capacitor C 8 . Control terminals S of the first control chip  150  and the second control chip  152  are connected to the node between the resistors R 10  and R 11 , for receiving the control signal SW. Ground terminals GND 1  and GND 2  of the first control chip  150  and the second control chip  152  are grounded. An enable terminal OE# of the first control chip  150  is grounded through a resistor R 14 . An enable terminal OE# of the second control chip  152  is grounded through a resistor R 15 . 
         [0016]    Data terminals  1 A,  2 A,  3 A, and  4 A of the first control chip  150  are respectively connected to data terminals T 1 , T 2 , T 3 , and T 4  of the processing chip  18 . Data terminals  1 A,  2 A,  3 A, and  4 A of the second control chip  152  are respectively connected to data terminals T 5 , T 6 , T 7 , and T 8  of the processing chip  18 . Data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the first control chip  150  are respectively connected to data terminals DQ 0 , DQ 1 , DQ 2 , and DQ 3  of the first storage  100 . Data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the second control chip  152  are respectively connected to data terminals DQ 4 , DQ 5 , DQ 6 , and DQ 7  of the first storage  100 . Data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the first control chip  150  are respectively connected to data terminals DQ 0 , DQ 1 , DQ 2 , and DQ 3  of the second storage  200 . Data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the second control chip  152  are respectively connected to data terminals DQ 4 , DQ 5 , DQ 6 , and DQ 7  of the second storage  200 . 
         [0017]    When the pole  2  contacts the first throw  1 , the base of the transistor Q 1  receives a high level signal, and the base of the transistor Q 2  receives a low level signal. At this time, the transistors Q 1  and Q 3  are turned on. The drain of the transistor Q 3  outputs a high level signal. The first storage  100  is powered on. The transistors Q 2  and Q 4  are turned off. The drain of the transistor Q 4  outputs a low level signal. The second storage  200  is not powered on. 
         [0018]    In addition, each of the control terminals S of the first control chip  150  and the second control chip  152  receives a low level signal. Moreover, each of the enable terminals OE# of the first control chip  150  and the second control chip  152  is grounded. At this time, the data terminals  1 A,  2 A,  3 A, and  4 A of the first control chip  150  are respectively connected to the data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the first control chip  150 . The data terminals  1 A,  2 A,  3 A, and  4 A of the second control chip  152  are respectively connected to the data terminals  1 B 1 ,  2 B 1 ,  3 B 1 , and  4 B 1  of the second control chip  152 . As a result, the data terminals T 1 -T 8  of the processing chip  18  are respectively connected to the data terminals DQ 0 -DQ 7  of the first storage  100 . In other words, data can be transmitted between the first storage  100  and the processing chip  18 . 
         [0019]    When the pole  2  contacts the second throw  3 , the base of the transistor Q 1  receives a low level signal, and the base of the transistor Q 2  receives a high level signal. At this time, the transistors Q 1  and Q 3  are turned off. The drain of the transistor Q 3  outputs a low level signal. The first storage  100  is not powered on. The transistors Q 2  and Q 4  are turned on. The drain of the transistor Q 4  outputs a high level signal. The second storage  200  is powered on. 
         [0020]    In addition, each of the control terminals S of the first control chip  150  and the second control chip  152  receives a high level signal. Moreover, each of the enable terminals OE# of the first control chip  150  and the second control chip  152  is grounded. At this time, the data terminals  1 A,  2 A,  3 A, and  4 A of the first control chip  150  are respectively connected to the data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the first control chip  150 . The data terminals  1 A,  2 A,  3 A, and  4 A of the second control chip  152  are respectively connected to the data terminals  1 B 2 ,  2 B 2 ,  3 B 2 , and  4 B 2  of the second control chip  152 . As a result, the data terminals T 1 -T 8  of the processing chip  18  are respectively connected to the data terminals DQ 0 -DQ 7  of the second storage  200 . In other words, data can be transmitted between the second storage  200  and the processing chip  18 . 
         [0021]    The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above everything. The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others of ordinary skill in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those of ordinary skills in the art to which the present disclosure pertains without departing from its spirit and scope. Accordingly, the scope of the present disclosure is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.