Abstract:
Various embodiments of a direct digital amplitude modulator (DDAM) for modulating radio frequency (RF) or intermediate frequency (IF) or baseband signal with the invented interpolation technique are disclosed. The interpolation technique greatly reduces the amplitudes of alias signals without using an analog filter. The embodiments therefore are significant for various communication transmitters to achieve simple structure, good linearity and high power efficiency.

Description:
CROSS REFERENCE TO RELATED APPLICATION  
       [0001]     This application is a continuation of copending International Application No. PCT/SE01/02411 filed Nov. 1, 2001, and claiming a priority date of Nov. 3, 2000, which designates the United States. 
     
    
     BACKGROUND OF THE INVENTION  
       [0002]     The invention relates generally to communication transmitters requiring amplitude modulation. Modern communication systems, such as cable, cellular and satellite communications, employ non-constant envelop digital modulation to increase spectral efficiency, such as quadrature phase-shift keying (QPSK), offset QPSK (OQPSK) and quadrature amplitude modulation (QAM) etc. To transmit a non-constant envelop signal, a linear power amplifier is required in the transmitter which usually has a low power efficiency and insufficient linearity. A direct digital amplitude modulator is of great interest for a transmitter to achieve simple structure, good linearity and high power efficiency in various communication systems.  
         [0003]      FIG. 1  and  FIG. 2  are the block diagrams of an exemplary QAM modulator. In  FIG. 1 , input data  100  is split into digital in-phase (I) signal  102   a  and quadrature (Q) signal  102   b  through digital signal processing (DSP) unit  101 . Digital-to-analog converters (DACs)  103   a  and  103   b  are used to convert I signal  102   a  and Q signal  102   b  to analog signals, and low pass filters  104   a  and  104   b  are used to clear the alias components of the DAC outputs. In amplitude modulators  105   a  and  105   b , the outputs of low pass filters  104   a  and  104   b  modulate carrier signals  106   a  and  106   b  which phases are separated in 90 degrees. The outputs of modulators  105   a  and  105   b  are combined in combiner  107 , and the output of combiner  107  is amplified through linear power amplifier  108 .  
         [0004]     The polar modulation technique is shown in  FIG. 2 . Data  200  is split into digital amplitude signal  202   a  and phase signal  202   b  by DSP unit  201 . Digital amplitude signal  202   a  is converted to analog amplitude signal through DAC  203 , and low pass filter  205  clears the alias components of the DAC output. Digital phase signal  202   b  modulates input carrier  207  in phase modulator  204 , and modulated carrier signal  206   b  is amplified through power amplifier  208 . The gain of power amplifier  208  is linearly controlled by analog amplitude signal  206   a . The embodiment in  FIG. 2  is more power efficient than that in  FIG. 1 , as the modulated carrier signal is a constant envelop signal, a nonlinear power amplifier can be used.  
         [0005]      FIG. 3   a  shows a conventional DAC  301  with an analog reconstruction filter  302 , and the spectra of digital input signal  300  and analog output signal  303  are showed in  FIG. 3   b  and  FIG. 3   c  respectively. From  FIGS. 3   b  and  3   c , when a broadband signal is transmitted, it is difficult to filter out the alias signals of the DAC output, and the wanted signal is distorted due to the DAC&#39;s non-flat sinc response. As the clock frequency (f s ) increases, the attenuation of the alias signal is increased, and the distortion of the signal is reduced.  
         [0006]     The embodiments in  FIG. 1  and  FIG. 2  are not suitable for full system integration, especially in broadband data transmission. Due to the limitation of clock frequency (f s ), they need complex analog reconstruction filters to remove alias signals. The analog reconstruction filter may even need discrete components.  
         [0007]     In mobile communications, a high efficiency power amplifier (PA) is essential, because the PA dominates the power consumption of the portable system. RF power amplifiers are most efficient when they work in switching mode and amplify a constant envelop signal. The amplification of a non-constant envelop signal requires a linear PA which is inherently less power efficient.  
       SUMMARY OF THE INVENTION  
       [0008]     The objective of the present invention is to provide a direct digital amplitude modulator (DDAM) for non-constant envelop modulation. It will be easily integrated with other parts of a transmitter system to achieve a fully digitized transmitter with simple structure, good linearity, high power efficiency and low requirement on the output filter. 
     
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0009]      FIG. 1  illustrates a conventional I-Q quadrature modulator.  
         [0010]      FIG. 2  illustrates a conventional polar modulator.  
         [0011]      FIG. 3  illustrates a conventional DAC, its digital input and analog output spectra.  
         [0012]      FIG. 4  shows, in the form of a block diagram, the principal and the detail of the invented direct digital amplitude modulator (DDAM).  
         [0013]      FIG. 5   a  shows the first embodiment of a sub-switched current source unit in this invention.  
         [0014]      FIG. 5   b  shows an extension of the first embodiment of a sub-switched current source unit in this invention.  
         [0015]      FIG. 6  shows the second embodiment of a sub-switched current source unit in this invention.  
         [0016]      FIG. 7  shows an I-Q quadrature amplitude modulator based on this invention.  
         [0017]      FIG. 8  shows the first embodiment of a polar modulator based on this invention.  
         [0018]      FIG. 9  shows the second embodiment of a polar modulator based on this invention. 
     
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
       [0019]     The preferred embodiments of the present invention and its advantages are best understood by referring to  FIG. 1 - FIG. 9  of the drawings.  
         [0020]     Referring to  FIG. 4 , the block diagram of the direct digital amplitude modulator (DDAM) according to the present invention is shown. The n-bit digital amplitude input signal  406  controls the binary-weight switched RF, IF or DC current sources  401 - 1 ,  401 - 2 , . . . ,  401 - n . The binary-weight switched current source in each bit is divided into sub-switched current source units (SUs). In the least significant bit (LSB) b 1 , it is divided into p sub-switched current source units SU 11 , SU 12 , . . . SU 1p . In an arbitrary bit b y , it is divided into z sub-switched current source units SU y1 , SU y2 , . . . , SU yz . In the most significant bit (MSB) b n , it is divided into m sub-switched current source units SU n1 , SU n2 , . . . , SU nm . The numbers of sub-switched current source units in different bits can be equal or different, depending on the minimum size available in the technology and/or the density of interpolation. The sizes of SUs in each bit can be equal or different, depending on the type of interpolation.  
         [0021]     Clock signal  405  which is synchronized with digital input  406  and has a frequency f s , is divided into a number of delayed clock signals  408  with delays in one period of digital input  406  through clock delay line  409 . For an arbitrary bit by, there are z delayed clock signals, and the intervals between these clock signals are equal in the normal case but can be unequal if necessary. The effective clock frequency of b y  is therefore increased to zf s . If m/z is set to an integer, clock delay line  409  is simplified, but it is not compulsory. In the case of linear interpolation, the current sources are divided into equal size SUs in each bit. In other cases, it can be divided into different sizes according to the selected interpolation function. Analog input signal  407  to the sub-switched current source units can be an RF, IF or DC signal. When the input signal is RF or IF, output  410  is an amplitude modulated RF or IF signal. When the input signal is DC, output  410  is an amplitude modulated baseband signal. Because of the higher effective clock frequency and the interpolation function, the DDAM&#39;s alias signal&#39;s attenuation is increased, and the requirement on the output analog filter is alleviated. With an RC charge and discharge hold (RCH) circuit which will be explained in the description of  FIG. 5   a , the alias signals&#39; attenuation is further increased.  
         [0022]      FIG. 5   a  shows the first embodiment of the sub-switched current source units when the analog input is an RF or IF signal. Data signal  501  is obtained from DDAM&#39;s digital input signal  406 , and clock signal  502  is obtained from clock delay line  409  in the DDAM. Data and clock signals  501  and  502  are sent to register  512  to produce output signal  503   a  and inverse output signal  503   b . Transistors M 4    510  and M 5    511 , controlled by output signal  503   a  and inverse output signal  503   b  of register  512  respectively, act as switches to current source transistor M 3    509 . The dimensions of transistors M 4    510  and M 5    511  can be properly selected in order to set the switching time constant together with the parasitic capacitance to obtain a hold character somewhere between zero-order-hold and first-order-hold. The RC charge and discharge hold (RCH) character can achieve higher attenuation for the alias signals. The differential RF or IF signals are fed to transistors M 1    508   a  and M 2    508   b . The power supply is provided via two loads Load 1    513   a  and Load 2    513   b  (not include in each sub-switched current source unit) which can be active or passive, on-chip or off-chip. Differential RF or IF output  506   a  and  506   b  are obtained from the drains of transistors M 1    508   a  and M 2    508   b , and either of them can be a single-ended output. Transistors M 1    508   a  and M 2    508   b  can be separated from sub-switched current source unit and combined with other components.  
         [0023]      FIG. 5   b  shows an extension of the first embodiment of the sub-switched current source units which realize a carrier suppressed DDAM. It uses two of the first embodiments in  FIG. 5   a , where signals  501 ,  502 ,  503   a ,  503   b ,  504  and register  512  are shared. Transistors M 5    510   a  and M 10    511   b , M 6    510   b  and M 9    511   a  are controlled by output signal  503   a  and inverse output signal  503   b  of register  512  respectively. The differential RF or IF signals are fed to transistors M 1    508   a  and M 4    508   d , M 2    508   b  and M 3    508   c  respectively. The drains of transistors M 1    508   a  and M 3    508   c  are connected together, and the drains of transistors M 2    508   b  and M 4    508   d  are connected together. The power supply is provided via loads Load  513   a  and Load 2    513   b  (not include in each sub-switched current source unit) which can be active or passive, on-chip or off-chip. Transistors M 1    508   a , M 2    508   b , M 3    508   c  and M 4    508   d  can be separated from sub-switched current source unit and combined with other components.  
         [0024]      FIG. 6  shows the second embodiment of the sub-switched current source units when the analog input is a DC signal (i.e. the DC power supply). Data signal  601  is obtained from DDAM&#39;s digital input  406 , and clock signal  602  is obtained from clock delay line  409  in the DDAM. They are sent to register  603 . Output  604   a  and inverse output  604   b  of register  603  are sent to two switching transistors M 1    607   a  and M 2    607   b . Bias signal  605  controls the bias of current source transistor M 3    606 . Load 1    608   a  and Load 2    608   b  (not include in each sub-switched current source unit) connected to power supply  610  are the loads of switching transistors M 1    607   a  and M 2    607   b  respectively, which can be active or passive, on-chip or off-chip. Differential baseband outputs  609   a  and  609   b  are obtained from the drains of switching transistors M 1    607   a  and M 2    607   b , and either of them can be a single-ended output.  
         [0025]      FIG. 7  shows a quadrature modulator for RF or IF carrier signal based on this invention. Data  701  to be transmitted is split into digital I signal and Q signal by DSP unit  702 . In DDAMs  703   a  and  703   b , the I and Q signals modulate carrier input signals  704   a  and  704   b  which phases are separated in 90 degrees. Input clock  707  is used by DSP unit  702  and DDAMs  703   a  and  703   b . The DDAM&#39;s outputs are combined in combiner  705  to produce a digitally modulated non-constant envelop signal  706 . Most alias signals are attenuated by the DDAM&#39;s transfer function.  
         [0026]     The polar modulation technique based on this invention is shown in  FIG. 8 . Data  801  is split into digital amplitude and phase signals  803  and  804  respectively through DSP  802 . Digital phase signal  804  modulates the phase of the input carrier signal  806  and produces a phase modulated constant envelope signal  807  fed to the analog input of DDAM  808 . Input clock  810  is used by DSP unit  802  and DDAM  808 . Through DDAM  808 , digital amplitude signal  803  modulates the amplitude of signal  807  to produce a digitally modulated non-constant envelop signal  809  in which the alias signals are greatly reduced.  
         [0027]     Instead of modulating RF and IF carrier signals directly, the invented DDAM can be used to control the bias voltage or current of an RF or IF power amplifier to produce a non-constant envelop digitally modulated signal with reduced alias components.  FIG. 9  shows such an embodiment. In  FIG. 9 , DSP unit  902  splits input data  901  into digital amplitude signal  903  and digital phase signal  904 . Digital phase signal  904  modulates RF or IF input carrier signal  910  in phase modulator  909 . The phase modulated constant envelope RF or IF signal  913  is amplified in a variable gain power amplifier  907 . The gain of the variable gain power amplifier is linearly controlled by bias signal  906 . Digital amplitude signal  903  from DSP unit  902  is fed to the digital input of DDAM  905  to produce a baseband bias signal  906  with reduced alias components. The output of DDAM  905  controls the gain of amplifier  907  to produce a digitally modulated non-constant envelop RF or IF signal  908  with reduced alias components. When DSP unit  902  and phase modulator  909  are removed, this embodiment can be used as an amplitude modulator. In this case, signal  903  and signal  913  are replaced by Data  901  and RF or IF  910  respectively.  
         [0028]     The proposed invention provides solutions for digitized transmitters. Although preferred embodiments of the present invention have been illustrated in the accompanying drawings and described in the foregoing detailed descriptions, various modifications may be made without departing from the spirit or scope of the general invented concept as defined by the appended claims and their equivalents.