Abstract:
The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Description:
BACKGROUND OF THE INVENTION  
         [0001]    1. Field of the Invention  
           [0002]    The present invention relates to a semiconductor integrated circuit, and more particularly to a method for fabricating a capacitor device with BICMOS processes and the capacitor device formed thereby.  
           [0003]    2. Description of the Prior Art  
           [0004]    Recently, capacitor devices have become principal components of many semiconductor integrated circuits. For example, a stacked capacitor is used in a dynamic random access memory (DRAM), or a capacitor having two electrodes and a dielectric layer is applied in a mix-logic/analog circuit.  
           [0005]    Referring to FIG. 1, a conventional capacitor used in a mix-logic/analog circuit is schematically depicted in a cross-sectional view. The circuit, including a BiCMOS device, is formed upon a silicon substrate  10  of a P-type conductivity, in which a plurality of field oxides FOX are formed to isolate a plurality of active regions of the device. A CMOS region  11  composed of an NMOS transistor  110  and a PMOS transistor  111  on a P-well and an N-well having a gate G 1 , a source S 1 , a drain D 1 , and a gate G 2 , a source S 2 , a drain D 2 , respectively, is formed by traditional processes. An NPN bipolar transistor  12  formed adjacent to the CMOS region  11  includes a collector  120 , a base  121 , a base contact  123 , an emitter  122 , and an emitter contact  124 . Adjacent to the bipolar transistor  12  is a poly to poly electrodes capacitor  13  composed of a bottom electrode (a polysilicon layer)  131 , a polysilicon layer  132  for decreasing the resistance of the junction, a dielectric layer (a silicon dioxide layer)  133 , and an upper electrode (a polysislicon layer)  134 . Further, in order to increase the conductivity of the bottom electrode  131 , an ion implantation or in-situ doped implantation is used to implant Arsenic ions or Phosphorous ions into the polysilicon layer  131 . An N-type conductivity layer is therefore formed.  
           [0006]    As described above, a capacitor basically has two electrodes (conducting plates) spaced by an insulator (a silicon dioxide layer). As well known by those persons skilled in this field, the most important parameters effecting the charges stored in the capacitor are the dielectric constant, thickness of the insulator, and the area of the capacitor plates. However, the capacitor with this structure described above suffers from depletion. In order to prevent the occurrence of the depletion issue, the bottom electrode is therefore doped with a high concentration ions. This will increase the thickness of the silicon dioxide layer (insulator) formed by oxidation of a thermal cycle thereafter. According to the calculation of the capacitance C, wherein C equals to the voltage drop of the capacitor divided by the thickness of the capacitor (C=ε/d), the capacitance is reduced due to the increment of the thickness of the insulator. Further, the performance of the device is effected.  
           [0007]    In addition, the process include two steps of forming polysilicon layers. The time and the cost for fabricating the two layers is therefore increased.  
         SUMMARY OF THE INVENTION  
         [0008]    Accordingly, an object of the present invention is to provide a simple and inexpensive method for fabricating a capacitor device with BiCMOS processes wherein the dielectric layer of the capacitor formed therein is thin.  
           [0009]    The other object of the present invention is to provide a capacitor device formed in an epitaxy layer in which a doping region is formed to be an electrode of the capacitor. Therefore, neither time nor the cost is increased. Moreover, the capacitor formed therein has high capacitance and good performance.  
           [0010]    To attain the first object of the present invention, a method for fabricating a capacitor device with BiCMOS processes on a semiconductor substrate is provided. The method comprises the following steps. First, a first buried layer and a second buried layer are formed in the semiconductor substrate. Subsequently, an epitaxy layer is formed above the semiconductor substrate, then three wells and a collector region are formed in the epitaxy layer, wherein two of the three wells form a CMOS transistor region, and the other well is a bottom electrode of the capacitor device. Additionally, the collector region and the bottom electrode are in contact with the two buried layers, respectively. After forming an oxide layer over the three wells to be a gate oxide layer of the CMOS transistor and the dielectric layer of the capacitor device, a base region adjacent to the collector region is formed. Afterward, a polysilicon layer is formed on the three wells and the base region to form gate electrodes of the CMOS transistor, an upper electrode of the capacitor device, and a base contact of the base region. Subsequently, source/drain regions and a base region are formed adjacent to the region below the gates of the CMOS transistor and adjacent to the region below the base contact, respectively. In addition, an emitter region is formed in the base region.  
           [0011]    It is noted that the dielectric layer is formed on the epitaxy layer by oxidation, directly. Therefore, the thickness of the dielectric layer is thinner than in the conventional art by means of adjusting the ion concentration of the well region (bottom electrode). According to the formula: C=ε/d mentioned before, decreased “d” leads to increased “C”. That is: the capacitance of the capacitor according to the present invention is higher than that of the prior art. In addition, the capacitor device is formed with BiCMOS processes, additional steps are not added in the processes. Neither the cost nor the time is increased.  
           [0012]    Furthermore, the device described above may contact other devices by the following steps. First, an insulating layer, for example, a boro-phospho-silicate-glass (BPSG) layer is formed above the epitaxy layer, then a plurality of openings are formed in the insulating layer to expose the polysilicon layer, source and drain regions, the collector region, and the base contact. Subsequently, a plurality of plugs are formed in the openings to contact with other devices.  
           [0013]    To attain the second object of the present invention, a capacitor device formed with BiCMOS processes on a semiconductor substrate is provided, comprising: a buried layer formed in the semiconductor; an epitaxy layer formed over the semiconductor; a bipolar junction transistor formed in the epitaxy layer having a collector region; a CMOS transistor having a gate oxide and a gate electrode; a well region formed with the collector region in the epitaxy layer and contacting with the buried layer, said well region being a bottom electrode of the capacitor device; an oxide layer formed with the gate oxide on the epitaxy layer over the well, said oxide layer being a dielectric layer of the capacitor device; and a conducting layer formed with the gate electrode on the oxide layer, said conducting layer being an upper electrode of the capacitor device. 
       
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       [0014]    The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.  
         [0015]    [0015]FIG. 1 schematically depicts a conventional capacitor having two electrodes (conducting plates) spaced by an insulator and a BiCMOS device fabricated onto a semiconductor substrate in a cross-sectional view; and  
         [0016]    [0016]FIG. 2A through 2K schematically depict in cross-sectional views steps involved in a method for fabricating a capacitor device with BiCMOS processes according to an embodiment of the present invention.  
     
    
     DETAILED DESCRIPTION OF THE INVENTION  
       [0017]    Referring to FIG. 2A, a semiconductor substrate such as a silicon substrate  20  is provided, then a first buried layer and a second buried layer are formed in the semiconductor substrate. For example, Arsenic ions and Boron ions with implantation energy of 50 Kev, and a flow density of 1 E 15 atoms/cm 2  are implanted into the silicon substrate  20 . Therefore, an N-type buried layer  201 , an N-type buried layer  202 , an N-type buried layer  203 , and a P-type buried layer  204  are formed.  
         [0018]    Subsequently, an epitaxy layer is formed upon the semiconductor. Referring to FIG. 2B, an epitaxy layer, for example, an N-type epitaxy layer  21  with a concentration of 10 14 ˜10 15  is formed on the silicon substrate  20 .  
         [0019]    The following step of the invention is forming a first well, a collector region, a second well, and a third well in the epitaxy layer, wherein the second well and the third well are doped with ions of a first type and a second type conductivity, respectively, and said first well and said collector region contact said first buried layer and said second buried layer, respectively. Referring to FIG. 2C, P-type ions, for example, Boron ions, are doped into the epitaxy layer  21  above the buried layer  201  and  204  to form P-type wells  210  and  214 . Thereafter, N-type ions, for example, Arsenic ions, are doped into the epitaxy layer  21  above the buried layer  202  and  203  to form N-type wells  212  and  213 , wherein the N-type well  212  is a collector region  212  of a bipolar junction transistor device  25  (not formed). Subsequently, N-type ions, for example, Arsenic ions with a higher concentration than that of the P-type well  210  are doped into the P-type well  210  so that the P-type well  210  converts to an N-type well  211  with a concentration of 10 15 ˜10 16  atoms/cm 3  to be a bottom electrode of a capacitor device  26  (not formed).  
         [0020]    Please refer to FIG. 2D. By local oxidation (LOCOS), a plurality of field oxides FOX are formed on the epitaxy layer  21  to define active regions therebetween. A patterned oxide layer is then formed over the epitaxy layer. As shown in FIG. 2E, a silicon dioxide layer (not shown) is formed on the epitaxy layer  21  by thermal oxidation. The silicon dioxide layer (not shown) is patterned by photolithography and etching processes on the epitaxy layer  21  above the well  211  (bottom electrode) to form a dielectric layer  22   a  of the capacitor device  26  (not formed). Also, the patterned silicon dioxide layer formed on the epitaxy layer  21  above the well  213  and the well  214  are gate oxide layers  22   b  and  22   c  of a CMOS device  24  (not formed), respectively. Note that the thickness of the dielectric layer  22   a  is 100˜150 Å.  
         [0021]    Referring to FIG. 2F, a P-type base region  215  is formed adjacent to the collector region  212  by doping with P-type ions, for example, Boron ions, into the epitaxy layer  21  within an active region.  
         [0022]    Referring to FIG. 2G, a conducting layer  23   a ,  23   b ,  23   c , and  23   d  is formed and patterned over the patterned oxide layer  22   a ,  22   b ,  22   c  and the base region  215 . The conducting layer might be made of a polysilicon layer deposited by chemical vapor deposition (CVD) to cover the epitaxy layer  21  globally. By photolithography and etching processes, the polysilicon layers  23   a ,  23   b ,  23   c , and  23   d  are formed on the dielectric layer  22   a , the epitaxy layer  21  above the base region  215 , the gate oxide  22   b , and the gate oxide  22   c  to form an upper electrode of the capacitor device  26 , an emitter contact of the bipolar junction transistor  25  (not formed), a gate electrode  23   c  and a gate electrode  23   d  of the CMOS transistor device  24  (not formed), respectively.  
         [0023]    Referring to FIG. 2H, a base contact region  216 , and source/drain regions  217 ,  218  are formed in the base region  215 , the well  213 , and the well  214 . For example, the base contact region  216  and the source/drain regions  217  are formed by means of implanting Boron ions into the base region  215  adjacent to the region below the emitter contact region  23   b  and into the well  213  adjacent to the region below the gate  23   c . Additionally, the source/drain regions  218  are formed by means of implanting Arsenic ions into the well  214  adjacent to the region below the gate  23   d . Subsequently, by in-situ doped implantation, ions are implanting into the upper electrode  23   a  of the capacitor device  26 , the emitter contact  23   b  of the bipolar junction transistor device  25  (not formed), and the gate electrodes  23   c ,  23   d  of the CMOS transistor device  24  so that the polysilicon layer  23   a ,  23   b ,  23   c , and  23   d  is conductive. Further, the in-situ doped implantation can protect the dielectric layer  22   a  from damage.  
         [0024]    Please refer to FIG. 2I. An emitter region  219  is formed in the base region  215 , and the BiCMOS device  27  including the bipolar junction capacitor device  25  is therefore completed. It is noted that the BiCMOS device  27  and the capacitor device  26  might contact with other devices. Therefore, steps of isolation and contact are necessary. As shown in FIG. 2J, a planar BPSG layer  28  is formed by means of flowing the BPSG upon the epitaxy layer  21 . By the photolithography and etching processes, openings  28   a ,  28   b ,  28   c ,  28   d ,  28   e ,  28   f ,  28   g ,  28   h ,  28   i ,  28   j ,  28   k  are formed so that the electrodes and the ion doping regions are exposed.  
         [0025]    Please refer to FIG. 2K. A conducting layer is formed over the BPSG layer  28  (not shown) and filled in the openings  28   a ˜ 28 K. Preferably, the conducting layer is a polysilicon layer deposited by low-pressure chemical vapor deposition (LPCVD) so as to conformably overlie the entire surface of the BPSG layer  28  and fill in the openings  28   a ˜ 28   k . Subsequently, the polysilicon layer is etched back to form plugs  29   a ,  29   b ,  29   c ,  29   d ,  29   e ,  29   f ,  29   g ,  29   h ,  29   i ,  29   j ,  29   k  so that the device according to the present invention contacts with other devices.  
         [0026]    Referring back to FIG. 2I, the capacitor device  26  fabricated with a BiCMOS device  27  on a silicon substrate  20  is schematically depicted in a cross-sectional view. As shown in FIG. 2I, N-type buried layers  201 ,  202 ,  203  and a P-type buried layer  204  are formed in the silicon substrate  20 . An epitaxy layer  21  is formed over the silicon substrate  20 , in which an N-well  211  is formed and contacts with the N-type buried layer  201  to be a bottom electrode of the capacitor  26 . Further, a dielectric layer  22   a  made of silicon dioxide is formed over the epitaxy layer  21 . In addition, an upper electrode  23   a  made of polysilicon is formed over the dielectric layer  22   a.    
         [0027]    As depicted in FIG. 2I, a BiCMOS transistor device  27  formed adjacent to the capacitor device  26  comprises a bipolar junction transistor  25  and a CMOS transistor  24 . The bipolar junction transistor  25  includes a collector region  212  in contact with the buried layer  202 , a base region  215  adjacent to the collector region  212 , a base contact  216  doped with ions in the base region  212 , an emitter region  219  formed in the base region, and an emitter contact electrode  23   b  formed on the epitaxy layer  21  above the emitter region  219 .  
         [0028]    Additionally, the CMOS transistor  24  formed in the epitaxy layer  21  includes a PMOS transistor and an NMOS transistor arranged in an N-type well  213  and a P-type well  214  respectively, wherein the N-type well  213  contacts the buried layer  203 , and the P-type well  214  contacts the buried layer  204 . A gate oxide  22   b  and a gate oxide  22   c  are formed on the epitaxy layer  21  above the N-type well  213  and the P-type well  214 , respectively. A gate electrode  23   c  and a gate electrode  23   d  are formed on the gate oxide  22   b  and the gate oxide  22   c , respectively. Further, source/drain regions  217  (P +  doped regions) and source/drain regions  218  (N +  doped regions) are formed in the epitaxy layer  21  adjacent to the regions below the gate electrode  23   c  and the gate electrode  23   d , respectively.  
         [0029]    As depicted in FIG. 2K, the device mentioned above may contact other devices by the plugs  29   a ,  29   b ,  29   c ,  29   d ,  29   e ,  29   f ,  29   g ,  29   h ,  29   i ,  29   j , and  29   k  formed in an insulating layer  28  made of BPSG over the epitaxy layer  21 . Further, in order to prevent the bottom electrode  211  from short-circuiting the upper electrode  23   a  when contacting, the contact of the bottom electrode  211  is arranged perpendicular to the cross section illustrated in the figure. Therefore, the plug contacting the bottom electrode  211  is not shown in FIG. 2K.  
         [0030]    It is noted that the capacitor device according to the present invention has a polysilicon layer. Therefore, the cost is lower than that of the prior art, which require two polysilicon layers. Additionally, the dielectric layer of the capacitor device according to the present invention is a silicon dioxide layer formed on the bottom electrode  211  lightly doped with ions, and the thickness of the dielectric layer is thinner than that of the conventional art. For example, according to the preferred embodiment, the thickness of the dielectric layer  22   a  is 100 Å, while the thickness of the dielectric layer according to the prior art is 400 Å. Accordingly, the capacitance of the capacitor according to the present invention is higher than that of the prior art. Furthermore, the capacitor in the invention is formed with a BiCMOS device. Thus, additional steps aren&#39;t added in the process. The cost isn&#39;t increased, either.  
         [0031]    The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments were chosen and described to provide the best illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.