Abstract:
A data cache memory is dynamically allocated as a global area which can be accessed in tasks other than a current task, and a local area which can be accessed in only a specific task. In the global area, data processing is controlled by the write through or copy back technique, in the same manner as in a conventional system. With respect to an access to the local area, an access is allowed to only the data cache memory, but is inhibited in relation to a main memory. For this reason, the tag section of the data cache memory includes a flag indicating a local or global area, and a task number storage field indicating a task in which a secured local area is accessed.

Description:
This application is a continuation of application Ser. No. 07/765,007, filed Sep. 24, 1991, now abandoned, which is a continuation in part of application Ser. No. 07/249,789, filed Sep. 27, 19988, now abandoned. 
     This is a continuation-in-part of application 07/249,789 filed Sep. 27, 1988, abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a control system and method of a data cache memory arranged between a central processing unit (CPU) and a main memory. 
     2. Description of the Related Art 
     With recent improvements in microcomputers, various microprocessors have been developed. For example, a 32-bit microprocessor was developed as such a microprocessor. Such a microprocessor, for example, the 32-bit microprocessor M68020 is available from Motorola Ltd., U.S.A. This microprocessor M68020 is provided with instructions (LINK and UNLINK instructions) for securing variables so that use of global and local variables is allowed. Such LINK and UNLINK instructions are described in, e.g., &#34;MC68030 Enhanced 32 Bit Microprocessor Users Manual.&#34; A global variable can be accessed in an entire program, whereas a local variable can be accessed in only a certain module (task) constituting the program. 
     More specifically, the LINK and UNLINK instructions allocate and deallocate a certain area in a system stack, of a main memory respectively. The LINK and UNLINK instructions are used for a nested subroutine, a link list or a procedure. The LINK instruction is executed succeeding to a procedure call (a subroutine call to be nested). When the LINK instruction is executed, a pointer in an address register is updated to designate the data area. After the subroutine is executed, the UNLINK instruction is executed to perform an operation opposite to the LINK instruction. More specifically, the UNLINK instruction restores the stack pointer and the address register to previous values before the LINK instruction is executed. The details of the LINK and UNLINK instructions are described in &#34;16-BIT MICROPROCESSOR User&#39;s Manual&#34; by MOTOROLA. 
     However, in the prior art, since the local area is provided in the main memory, the processing speed is constrained to the memory cycle, resulting in low processing speed. 
     However, when an interruption is generated during execution of the program or task switching is performed during multitask processing, the contents of the cache memory must be rewritten in the main memory. That is, since the cache memory is a copy of part of the address space of the main memory, the contents of the cache memory must coincide with the contents of the corresponding area of the main memory. Therefore, when an interruption is generated or a task is switched, no problem is posed in the read operation with respect to the cache memory. When data is written in the cache memory, however, the data must be also written in the main memory. In this case, &#34;write through&#34;, &#34;copy back&#34;, or the like is used as a technique of writing data in the main memory. In the &#34;write through&#34; technique, data is written in the main memory immediately after the data is written in the cache memory. According to the &#34;copy back&#34; technique, a certain amount of data are preserved, and the preserved data are collectively written in the main memory later. 
     As described above, since the main memory is slower in writing speed than the cache memory, if data is written in the main memory every time an interruption is generated or a task is switched, overhead is inevitably increased. In a system having a conventional cache memory, a local area (having the same address space as that of the cache memory) is secured on the main memory, and local variables are stored in the local area. A necessary local variable is accessed using a stack pointer. In this case, if a local variable in the cache memory is updated, the corresponding data in the main memory must be updated, thereby degrading the high-speed operation of the overall system. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to provide a data cache memory control system and a method which can prevent a decrease in speed associated with writing access to a cache memory. 
     In order to achieve the above-described object, according to the present invention, there is provided a data cache memory control system having a main memory, a data cache memory in which part of the main memory is copied, and a central processing unit (CPU) for accessing the main memory and the data cache memory, comprising: data cache memory allocating means for allocating at least global and local areas in the data cache memory, the global area being accessed in any one of a plurality of modules constituting a program and the local area being accessed in only a specific module; local area access detecting means for detecting an access to the local area and outputting a detection signal; and main memory access inhibit means for inhibiting an access to the main memory in response to the detection signal from the local area detecting means. 
     According to the data cache memory control system of the present invention, a field for storing a flag representing whether a variable stored in a data field of the cache memory is a global or local variable is arranged in a tag section for every data field. When this flag represents a global variable, the cache memory is controlled in a conventional manner. That is, in a read operation, if target data is obtained in the cache memory, the &#34;HIT&#34; signal is output. If it is not obtained, the main memory is accessed. In a write operation, the global variable (or other data) is written in the cache memory, and at the same time, identical data is written in the main memory by the write through or copy back technique, or the like. 
     In contrast, if the flag represents a local variable, access is inhibited in both read and write operations, thereby realizing high-speed processing. In addition, by adding a task number to the tag section of the data cache memory, for example, even when the CPU processes task B because an interruption is generated during processing of task A, the contents of task A in the local area are saved. Therefore, processing such as copy back is not required. The present invention is effective especially when a large-capacity data cache memory can be designed with an increase in integration density. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a view showing the principle of the present invention; 
     FIG. 2 is a block diagram showing an embodiment of the present invention; 
     FIG. 3 is a block diagram showing the internal structure of a data cache memory; 
     FIG. 4 is a circuit diagram of a circuit for detecting that a variable written in the cache memory is a local variable; and 
     FIG. 5 is a circuit diagram of a circuit for allowing access to a main memory with respect to a global variable and for inhibiting a local variable from being written in the main memory in a write operation of a variable with respect to the cache memory. 
     FIGS. 6A and 6B are flow charts showing an operation of the data cache memory control system according to the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     FIG. 1 shows the principle of the present invention. As shown in FIG. 1, global and local areas 20 and 21 are arranged in data cache memory 3. When CPU 1 writes a variable in data cache memory 3, if it is a global variable, it writes the global variable in global area 22 of main memory 2 as well as in global area 20 of data cache memory 3. On the other hand, CPU 1 writes a local variable in local area 21 of data cache memory 3 but not in main memory 2. 
     In a read operation, if a global variable is not hit in the cache memory, a read operation is performed with respect to the main memory. In processing of a local variable, however, even if a hit is not obtained in the cache memory, a read operation with respect to the main memory is not performed (in this case, a trap is generated to inform the CPU of an erroneous access). 
     An embodiment for realizing the present invention will be described with reference to FIGS. 2 through 5. 
     Referring to FIG. 2, microprocessor 1 is, e.g., a 32-bit microprocessor. As such microprocessor 1, for example, the 32-bit microprocessor M68020 available from Motorola Inc., U.S.A. can be used. Data cache memory 3 is connected to microprocessor 1 through address and data buses 11 and 12. Data cache memory 3 has a capacity of, e.g., 32 Kbyte, and incorporates comparator 6 and local area setting circuit 23. In addition, main memory 2 is connected to microprocessor 1 through address and data buses 11 and 12, and driver/receiver 5. Main memory 2 has a capacity of, e.g., 1 Mbyte. An address from microprocessor 1 is supplied to main memory 2 through address bus 11 and multiplexer 8. In addition, read-only memory (ROM) 7 is connected to data cache memory 3 and main memory 2. Memory bus control circuit 4 is connected to microprocessor 1, data cache memory 3, main memory 2, and ROM 7. Memory bus control circuit 4 serves as memory interface of data cache memory 3, main memory 2, and ROM 7 with microprocessor 1, and serves as bus interface between microprocessor 1, and address and data buses 11 and 12. Memory bus control circuit 4 receives hold signal HLDA from microprocessor 1, and supplies hold signal HOLD, operation clock signal CLK 18, and reset signal RESET 19 to microprocessor 1. Furthermore, memory bus control circuit 4 supplies a cache data write enable (CDWE) signal 17, a cache address chip enable (CACE) signal, and a cache address write enable (CAWE) signal 17 to data cache memory 3, and receives a HIT signal from data cache memory 3. In addition, memory bus control circuit 4 supplies a DIR signal representing the direction of data and data enable signal DEN 16 to driver/receiver 5. Moreover, circuit 4 supplies to main memory 2 write enable signal WE representing a read or write operation (a write operation is performed with respect to the main memory when signal WE is output, and a read operation is performed therewith when WE signal is not output), a raster address strobe (RAS) signal, and a column address strobe (CAS) signal, and also outputs ROM output enable signal ROE 15 to ROM 7. Like a conventional circuit, memory bus control circuit 4 is designed not to output signals RAS and CAS upon reception of a HIT signal from data cache memory 3. Therefore, access to main memory 2 is not made. In this embodiment, when a local variable is to be read/written from/in data cache memory 3, a HIT signal is output from data cache memory 3. Therefore, memory bus control circuit 4 does not supply RAS and CAS signals to the main memory. That is, when a local variable is processed, main memory 2 is not accessed. 
     According to the present invention, a variable to be written in data cache memory 3 is determined to be a local variable by detecting that an instruction being executed by CPU 1 is a stack operation instruction on the basis of the fact that a local variable is conventionally stored in a stack arranged in main memory 2. FIG. 3 is a block diagram showing the internal structure of data cache memory 3. As shown in FIG. 3, data cache memory 3 comprises flag field 31, task number field 33, tag address field 35, data field 37, and present flag field 39. Flag field 31, task number field 33, and address field 35 constitute a tag section. Flag field 31 stores a flag indicating that data stored in a corresponding data field is a global or local variable. Task number field 33 stores a number identifying a task in multitask processing. Tag address field 35 stores an address in main memory 2 where corresponding data is stored. Data field 37 stores a local or global variable. In the case of multitask processing, the data field is determined by the task number and the tag address. Present flag field 39 stores a flag indicating whether data as an access minimum unit, e.g., 32-bit data in this embodiment, is valid or not. The present flag is set to be invalid (at logic &#34;0&#34;) in the initialization mode. In addition, when the data cache memory is to be updated, new data is written in a data field having an invalid present flag. In this case, if a plurality of present flags &#34;0&#34; are present, one of them in which the new data is written on the basis of the LRU (Least Recently Used) algorithm is determined. The LRU algorithm determines which data among the cache memory is least recently used. This LRU algorithm is useful when data is stored from the cache memory in the main memory. When a local variable is to be read from data cache memory 3, if the present flag is set at logic &#34;0&#34;, a trap is generated to inform microprocessor 1 of an erroneous access. 
     FIG. 4 is a detailed circuit diagram showing local area setting circuit 23 arranged in data cache memory 3. Circuit 23 has functions of monitoring an instruction executed by microprocessor 1 and securing a local area in data cache memory 3. An instruction to be monitored is, e.g., an instruction of securing a local area in a stack an instruction of loading data in the stack. Comparator 43 compares an instruction read out from-the main memory 2 by the microprocessor 1 through data bus 12 with, e.g., an operation code of a stack operation instruction prestored in internal register 41, which is a predetermined register of the local area setting circuit 23. If they coincide with each other upon comparison, the data is determined to be a stack operation instruction, and a coincidence signal is supplied to one input terminal of AND gate 45. In addition, an instruction fetch signal is supplied from microprocessor 1 to the other input terminal of AND gate 45. As a result, if microprocessor 1 is executing a cycle of instruction fetch and the instruction is a stack operation instruction, a stack operation instruction detection signal is output from AND gate 45. Local area setting circuit 47 allocates a local area corresponding to the byte number designated by the stack operation instruction in data cache memory 3 on the basis of the LRU algorithm. 
     FIG. 5 is a detailed circuit diagram of comparator 6 in FIG. 2. 
     Comparator 6 is designed to output a HIT signal under the following conditions. When flag 31 of the tag section is set at logic &#34;0&#34;, i.e., corresponding data is not a local variable, an address output from microprocessor 1 is compared with a tag address. If a coincidence is established upon comparison and present flag 39 is set at logic &#34;1&#34;, i.e., present flag 39 indicates that the data stored in data field 37 is valid, a HIT signal is output in a read operation. In a write operation, the data is written in data cache memory 3 while the data is also written in main memory 2 by the write through or copy back technique, or the like. 
     In contrast to this, when flag 31 is set at logic &#34;1&#34;, i.e., represents a local variable, if the following three conditions are satisfied: i) the present flag is set at logic &#34;1&#34;, ii) an address in main memory 2 supplied from microprocessor 1 coincides with address tag 35, and iii) a task number and a tag address (or a tag address only in the case of a singe task) supplied from microprocessor 1 or an operating system coincides with a task number and tag address in the tag section, data cache memory 2 outputs a HIT signal regardless of whether the operation is a read or write operation. 
     An operation of the embodiment of the present invention with the above-described arrangement will be described with reference to the flow chart shown in FIGS. 6A and 6B. 
     Assume that task A is started, and microprocessor 1 executes an instruction of securing a local variable area on the stack (e.g., a stack operation instruction such as a LINK instruction in M68020). As a result, an instruction fetch signal is output from microprocessor 1 to AND gate 45, and instruction data is output to comparator 43 through data bus 12. Comparator 43 compares the data supplied through data bus 12 with the stack operation instruction supplied from internal register 41. In this case, since they coincide with each other, comparator 43 supplies a coincidence signal to one input terminal of AND gate 45. As a result, AND gate 45 outputs a stack operation instruction detection signal to local area setting circuit 47. Then, local area setting circuit 47 secures part of data cache memory 3, which is allocated as a global area, as a local area on the basis of the LRU (Least Recently Used) algorithm (step S1). In the data write mode, it is determined whether an address supplied from microprocessor 1 is present in an address space assigned to data cache memory 3 or not (steps S3 and S5). If so, it is further determined whether the variable to be written in data cache memory 3 is a local variable or not (step S7). If it is a local variable, data cache memory 3 outputs a HIT signal to memory bus control circuit 4. More specifically, when data is to be written in cache memory 3 in FIG. 5, in response to the data, e.g., an instruction of loading various parameters used in a subroutine, data cache memory 3 stores the parameters in data field 37 and sets present flag 39 at logic &#34;1&#34; (step S9). In addition, in response to an instruction of setting flag 31, data cache memory 3 sets flag 31 at logic &#34;1&#34; (step S13). In this case, present flag &#34;1&#34; is supplied to first input terminal 59 of AND gate 57. Furthermore, a tag address written in the tag section and an address in main memory 2 supplied from microprocessor 1 are compared with each other by comparator 51. In this case, since they coincide with each other, a coincidence signal is supplied to second input terminal 61 of AND gate 57. A task number in the tag section and a task number supplied from an operating system or microprocessor, are compared with each other by comparator 53. Upon comparison, a coincidence signal from comparator 53 is supplied to OR gate 55. At this time, flag 31 set at logic &#34;1&#34; is supplied to OR gate 55. Therefore, OR gate 55 supplies signal &#34;1&#34; to third input terminal 63 of AND gate 57. In addition, signal &#34;1&#34; is supplied to the fourth input terminal 65 of AND gate 57 (in this case, since flag 31 is set at logic &#34;1&#34;, signal &#34;1&#34; is supplied in both the read and write modes). Therefore, the AND conditions are satisfied, and AND gate 57 outputs a HIT signal to memory bus control circuit 4, so that memory bus control circuit 4 does not output RAS and CAS signals (steps S15 and S17). As a result, the data is not written in main memory 2. 
     If the determination of step S5 is &#34;NO&#34;0 the memory bus control circuit 4 writes data in the main memory 2 (step S19). 
     In contrast to this, when flag 31 is set at logic &#34;0&#34;, corresponding data is not a local variable. In this case, the data cache memory stores the parameters used in the subroutine into the data field (step S18) and then the present flag is set to &#34;1&#34; (step S20). In this case, OR gate 55 always outputs data &#34;1&#34; regardless of a task number. In addition, since an AND product of data &#34;0&#34; of flag 31 and data &#34;1&#34; of a write signal is obtained, data &#34;0&#34; is supplied to the fourth input terminal of AND gate 57. Therefore, AND gate 57 does not output a HIT signal. As a result, memory bus control circuit 4 outputs write enable signal WE, and RAS and CAS signals to main memory 2 (steps S21 and S23). With this operation, the same contents as that in the global area in data cache memory are written in main memory 2 using the write through or copy back technique, or the like (step S25). In the &#34;write through&#34; technique, data is written in the main memory immediately after data is written in the cache memory. According to the &#34;copy back&#34; technique, a certain amount of data are preserved and the preserved data are collectively written in the main memory later. 
     When data is to be read out from data cache memory 3, microprocessor 1 supplies a corresponding address in main memory 2 to data cache memory 3 (step S27). Then, it is determined whether an address from the microprocessor 1 is within an address space allocated to the cache memory 23 (step S29) If the determination is &#34;NO&#34;, the memory bus control circuit reads data from the main memory 2 (step S31). In contrast, if the determination of step S29 is &#34;YES&#34;, a task number and a tag address from the operating system or microprocessor 1 are supplied to data cache memory 3 (step S33). The data cache memory 3 refers to flag 31 to determine whether the variable is global or local (step S35). If the flag 31 represents the global variable, the cache memory 3 refers to present flag 39 corresponding to the task number and the tag address whether the data is valid (&#34;1&#34;) or invalid (&#34;0&#34;). If it is valid, the contents in corresponding data field 37 are read (step S53). On the contrary, when present flag 39 represents invalidity of the data, (step S43) main memory 2 is read-accessed. When it is a local variable, main memory 2 is not read-accessed. That is, when a global variable is to be processed, present flag signal &#34;0&#34; is supplied to the first input terminal of AND gate 57. In addition, signals &#34;1&#34; are respectively supplied to the second, third, and fourth input terminals of AND gate 57 (step S47). Therefore, a HIT signal is not supplied to AND gate 57 (step S47). Since memory bus control circuit 4 outputs RAS and CAS signals (step S49), and write enable signal WE set at logic &#34;0&#34;, main memory 2 is read-accessed (step S51). 
     In contrast, if the flag 31 represents the local variable, it is determined in step S37 whether the present flag 39 is valid or invalid. If the flag 39 is invalid, data cache memory outputs a miss hit signal (step S45). In contrast, if the present flag is valid in step S37, since the first through fourth input terminals of AND gate 57 are set at logic &#34;1&#34;, AND gate 57 outputs a HIT signal (step S39). Consequently, memory bus control circuit 4 does not output RAS and CAS signals, and write enable signal WE (step S41). Thus, main memory 2 is not read-accessed. Note that since a present flag is set when data is written in a local area, if local data is read when the present flag is not set, a trap is generated to inform microprocessor 1 of occurrence of an error.