Abstract:
The present invention discloses a method and apparatus for implementing matched filter in a system using QPSK modulation. In the present invention, a multiplier is changed as a multiplexer by using the characteristic of the pilot sequence (or training sequence) so as to implement the matched filter.

Description:
FIELD OF THE INVENTION 
       [0001]    The present invention relates to a wireless communication system, in particular to a simplified method and apparatus for implementing matched filters in a wireless communication system. 
       BACKGROUND OF THE INVENTION 
       [0002]    In Direct Sequence Spread Spectrum of a CDMA system, a high rate spread spectrum sequence with pseudo-random noise properties is usually adopted to spread the frequency of the lower rate base band signal, thereby obtaining a channel spread spectrum gain to improve the transmission quality of signals. In a receiver, the same spread spectrum sequence is used to perform opposite processing on the received signal, i.e. despreading processing, to restore the original data information. An important factor here is the synchronization between the transmitter and receiver. In general, a pre-defined sequence usually called SC (i.e. synchronization code) is inserted in each sub-frame for frame synchronization, and also a pre-defined known sequence (training sequence) is inserted in each time slot for time slot synchronization in the DS-CDMA (Direct Spread-Code Divided Multiple Access) system, the receiving terminal can achieve the signal synchronization between the transmitter and received just through performing matched filtering (correlation) on the pre-defined known sequence, 
         [0003]    A conventional system of CDMA receiver is, in general, designed to realize the synchronization by using the matched filter containing a large amount of electronic components, wherein the matched filter occupies a larger area and the implementation thereof is more expensive. Especially, a CDMA receiver uses a matched filter to match a code sequence to detect the correlation peak. A matched filter comprises, in general, a delay register, a multiplier and an adder. Since the matched filter needs to contain a large amount of electronic components, the design of system is expensive and the system occupied a larger area 
         [0004]    Now referring to  FIG. 1 , this figure shows the function of the matched filter accomplished in a CDMA receiver. When a receiver receives an input signal, the matched filter is tuned to match a code sequence. In systems using QPSK modulation, such as the TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) systems, the code sequence is inserted in the signals (i.e. digital sample) received by the receiver. The object of providing a code sequence is to enhance the operation of communication systems. Particularly, in CDMA wireless communication systems, the spread spectrum technology is very suitable to provide stable data transmission in a wireless environment with severe interference. 
         [0005]    On the other hand, in CDMA systems, multiple users share communication channels on the same spectrum and in the same time. In order to discriminate one transmission from another, every UE (User Equipment) has a unique synchronization code sequence. The synchronization sequence usually has a good auto-correlation performance, so it helps UE to identify the synchronization code rapidly and accurately without any prior knowledge about timing reference and also helps base station to discriminate different code used by different UE. In implementation, a matched filter is usually used for synchronization and discrimination of different UE in DS-CDMA system. Just as shown in  FIG. 1 , a matched filter  1  comprises a matched filter unit  2  and a detection unit  3 , wherein the matched filter unit  2  is used to perform matched filtering on the code sequence in an input data stream, the detection unit  3  is used to detect the matched filter output from the matched filter unit  2 , wherein a higher output value of the matched filter unit  2  indicates a more tuned match with the expected code sequence. This process is also called correlation process. Hence a high output value represents a good correlation of input with the code sequence of interest. What is more, in flat-fading channel, the peak output value within a sub-frame/time slot can be used as the channel estimation value for this sub-frame/time slot. 
         [0006]    Referring to  FIG. 2 , this figure shows a schematic diagram illustrating a Finite Impulse Response (FIR) filter for implementing matched filters in prior art. Just as shown in  FIG. 2 , to match a code sequence with length L, L delay registers, L multiplier and L adders are needed. That is to say, in the prior art, more hardware components are needed to realize the matched filter. And it is commonly known that the hardware implementation of a multiplier is more complex. 
         [0007]    In view of the above reasons, it&#39;s needed to provide a new hardware implementation of matched filters to realize the desired function of matched filter by using less electronic components and relatively more simple hardware structure. 
       OBJECT AND SUMMARY OF THE INVENTION 
       [0008]    An object of the invention is to provide a novel improved method and functional processing for simplifying hardware structure of the matched filter in CDMA systems, in particularly for the matched filter in systems using QPSK modulation, the character of the pilot sequence (or training sequence) is used to replace the multiplier in the prior art with a selector (which can be realized by a multiplexer) so as to implement matched filters. 
         [0009]    According to the first aspect of the invention, it provides a method for implementing matched filters in a wireless communication system, comprising the steps of: oversampling and extracting a pre-processed received signal so as to obtain the in phase components (I-components) and the quadrature components (Q-components) of respective sample points in a plurality of sampling sequences; and converting and combining the I-components and the Q-components of respective sample points in the same sampling sequence for the respective sampling sequence according to a pre-defined selection signal so as to obtain a plurality of corresponding matched filtered results. 
         [0010]    Preferably, the pre-defined selection signal is a selection signal based on a known training sequence, wherein the length of each sampling sequence is equal to the length of the known training sequence. 
         [0011]    According to the second aspect of the invention, it provides an apparatus for implementing matched filter in a wireless communication system, comprising: an oversampling and extracting means for oversampling and extracting a pre-processed received signal so as to obtain the I-components and the Q-components of respective sample points in a plurality of sampling sequences; and a conversion process means for converting and combining the I-components and the Q-components of respective sample points in the same sampling sequence for the respective sampling sequence according to a pre-defined selection signal so as to obtain a plurality of corresponding matched filtered results. 
         [0012]    Preferably, the matched filter further comprises a pre-defined means for setting the pre-defined selection signal based on the selection signal of a known training sequence, wherein respective sampling sequences are of the same length as the known training sequence. 
         [0013]    As compared with conventional methods, the apparatus and method for implementing matched filters in the receiver of a wireless communication system according to the invention can effectively reduce the complexity of hardware implementation of matched filters and reduce circuit area. 
         [0014]    Other objects and achievements of the present invention will become apparent and more thorough understanding can be obtained through the following description of accompanying drawings and appended claims. 
     
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         [0015]    Hereinafter, the preferred embodiments of the invention will be described with reference to the drawings, in which 
           [0016]      FIG. 1  is a functional block diagram of the matched filter in the receiver of a wireless communication system; 
           [0017]      FIG. 2  is a functional block diagram of the hardware implementation of the matched filter in the prior art; 
           [0018]      FIG. 3  is a block diagram of the matched filter according to an embodiment of the invention; 
           [0019]      FIG. 4  is a configuration schematic diagram of the conversion process means in the matched filter according to an embodiment of the invention; 
           [0020]      FIG. 5  is a flow chart of a method for implementing matched filter in a wireless communication system according to an embodiment of the invention; 
           [0021]      FIG. 6  is a schematic diagram of a circuit implementing manner of the conversion process means as shown in  FIG. 3  and  FIG. 4 ; 
           [0022]      FIGS. 7A  and B are schematic diagrams illustrating a specific circuit implementing manner of each circuit part used for the I-components and the Q-components of output results of the conversion process means in a TD-SCDMA system respectively; 
           [0023]      FIG. 8  is schematic diagrams illustrating a specific circuit implementing manner of each circuit part used for the I-components and the Q-components of output results of the conversion process means in a WCDMA system. 
       
    
    
       [0024]    In all the accompanying drawings, same reference numeral denotes similar or identical feature and function. 
       DETAILED DESCRIPTION OF THE INVENTION 
       [0025]      FIG. 3  illustrates a block diagram of the matched filter according to the first embodiment of the invention. In the receiver of a wireless communication system, a received input signal is first pre-processed and then is transmitted to the matched filter. As shown in  FIG. 3 , the matched filter  1  includes an oversampling and extracting means  20  for oversampling and extracting the pre-processed received signal so as to obtain the I-components and the Q-components of each sample point in a plurality of sampling sequences; and a conversion process means  30  for converting and combining the I-components and the Q-components of respective sample points in the same sampling sequence for respective sampling sequence according to a pre-defined selection signal so as to obtain a plurality of corresponding matched filtered results, wherein the pre-defined selection signal can be generated by a pre-defined means  10  based on the selection signal of a known training sequence. Preferably, the length of each of the sampling sequences equals the length of the known training sequence. 
         [0026]    During implementation, the oversampling and extracting means  20  can first oversample the received signal to obtain a plurality of sampling sequences, and then process each sample point of the plurality of sampling sequence so as to extract the I-component and the Q-component of each sample point; alternatively, the oversampling and extracting means  20  can first extract the I-components and the Q-components of the received signal and then oversample the I-component and the Q-component respectively based on the same timing reference, in this way the I-component and the Q-component of each sample point in the plurality of sampling sequence can also be obtained. 
         [0027]    Additionally, the matched filter  1  may preferably comprise: a buffer means  40  for buffering the plurality of matched filtered results; and a comparison means  50  for comparing the plurality of matched filtered results that are buffered so as to determine an optimum matched sampling sequence, wherein the value of the matched filtered result corresponding to the optimum matched sampling sequence is the greatest. 
         [0028]      FIG. 4  shows configuration schematic diagram of the conversion process means in the matched filter as shown in  FIG. 3 . The conversion process means  30  comprises a negating means  301 , a signal combining means  302  and an accumulating means  303 , wherein the negating means  301  is used to perform negation operation of the I-components and the Q-components of the respective sample points so as to obtain the negated I-components and the negated Q-components; while the signal combining means  302  is used to perform pre-defined combination operation of the I-components of respective sample points, the negated I-components, the Q-components and the negated Q-components, so as to obtain the corresponding output results of the respective sample points; while the accumulating means is used to perform accumulation operation on the output results to which respective sample points in the same sampling sequence correspond for the sampling sequences so as to obtain the matched filtered results corresponding to the sampling sequences. 
         [0029]      FIG. 5  is a flow chart of a method for implementing matched filter in a wireless communication system according to an embodiment of the invention. In the receiver of a wireless communication system, the received input signal is first pre-processed and then experiences matched filter processing. In step S 1 , the pre-processed received signal is received, and then it comes to step S 2 . In step S 2  the I-components and the Q-components of respective sample points for the same sampling sequence are converted and combined so as to obtain a plurality of corresponding matched filtered results, after that, it enters step S 3 , the I-components and the Q-components of respective sample points for the same sampling sequence are converted and combined so as to obtain a plurality of matched filtered results corresponding to a plurality of sampling sequences, wherein the pre-defined selection signal is generated based on the selection signal of a known training sequence. Furthermore, the respective sampling sequences are preferably of the same length as the known training sequence. 
         [0030]    During implementation, in step S 2 , the received signal can first be oversampled to obtain a plurality of sampling sequences, then each sample point of the plurality of sampling sequence is processed so as to extract the I-component and the Q-component of each sample point; alternatively, in step S 2 , the I-component and the Q-component of the received signal can first be extracted and then be oversampled respectively based on the same timing reference, in this way the I-component and the Q-component of each sample point in the plurality of sampling sequence can also be obtained. 
         [0031]    In addition, as shown in  FIG. 5 , the method of implementing matched filtering on the received signal in a wireless communication system receiver preferably include a further step  4  following step S 3 . In step S 4 , a plurality of matched filtered results corresponding to the plurality of sampling sequences are buffered and compared so as to determine an optimum matched sampling sequence, wherein the value of the matched filtered result corresponding to the optimum matched sampling sequence corresponds is the greatest. 
         [0032]    Specifically, step S 3  of the matched filter method as shown in  FIG. 5  may comprise the sub-steps of:
       performing negation operation on the I-components and the Q-components of the respective sample points so as to obtain the negated I-components and the negated Q-components;   performing pre-defined combination operation of the I-components of respective sample points, the negated I-components, the Q-components and the negated Q-components, so as to obtain the corresponding output results of the respective sample points;   performing accumulation operation on the output results to which respective sample points in the same sampling sequence correspond for the sampling sequences, so as to obtain the matched filtered results corresponding to the sampling sequences.       
 
       FIRST EMBODIMENT 
       [0036]    In a mobile communication system employing QPSK modulation, the amplitude of a complex number is always 1 when each synchronization code (SC) of the sequence (i.e. a pre-defined training sequence) is mapped to the complex symbol, and the phases of the complex symbol have a difference of 90°. Therefore, after mapping to complex symbols, each SC (i.e. synchronization code) can only be one of the four values selected from the complex set with amplitude  1 . When the phase angle of a signal is (0°, 180°, 90°, 270°), a typical set of this value is represented by (1, −1, j, −j), and when the phase angle of the signal is (45°, 315°, 135°, 225°), the other set of the value is (1+j, 1−j, −1+j, −1−j). 
         [0037]    Specifically, in a TD-SCDMA system, the numeric value of each unit of the sequence is one from the set {1, −1, j, −j}. Assume the input of the matched filter in the receiver as x, the input sample after being oversampled is x(n)=I(n)+jQ(n), wherein I(n) is an In-phase component (I-component), and Q(n) is a quadrature component (Q-component), both of them can be obtained by using extracting processing; and ss(i) is the ith code chip of the pre-defined SC sequence. Therefore, the following equations can be used to represent the I-component and Q-components of the product of the input sample and corresponding code chips in the pre-defined SC sequence: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0038]    wherein ss*(i) is the conjugate value of ss(i). As y(n)=Re[y(n)]+jIm[y(n)], it can be deduced that the matched filtered result obtained for each sample point of the plurality of sampling sequences is one from set {I+jQ, −I−jQ, −Q+jI, Q−jI}, wherein I is the I-component, Q is the Q-component, −I is the negated I-component, −Q is the negated Q-component. 
         [0039]    In a WCDMA system, however, the numeral value of each unit of the SC sequence is one from set {1+j, 1−j, −1+j, −1−j}. Likewise, assume the input of the matched filter in the receiver as x, the input sample after being oversampled is x(n)=I(n)+jQ(n), wherein I(n) is an I-component, and Q(n) is a Q-component, both can be obtained by using extracting processing; ss(i) is the ith code chip of the pre-defined SC sequence. Therefore, the following equations can be used to represent the I-component and Q-components of the product of the input sample and corresponding code chips in the pre-defined SC sequence: 
         [0000]    
       
         
           
             
               
                 
                   
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         [0040]    Since y(n)=Re[y(n)]+jIm[y(n)], it can be deduced that the matched filtered result obtained for each sample point of the plurality of sampling sequences is one from set {{(I−Q)+j(I+Q), (I+Q)+j(−I+Q), (−I−Q)+j(I−Q), (−I+Q)+j(−I−Q)}, wherein I is the I-component, Q is the Q-component, −I is the negated I-component, −Q is the negated Q-component. 
         [0041]      FIG. 6  is a schematic diagram of a specific circuit implementation manner of each circuit component of the conversion process means  30  as shown in  FIG. 3  and  FIG. 4 . Suppose the length of the pre-defined training sequence in the wireless communication system receiver is L, the conversion process means  30  includes L same operation units, each comprising a combiner  3021  (which can be realized by a multiplexer), an adder  3022  and a delay means  3023 , wherein the delay time of the delay means  3023  is the time interval of two adjacent sample points in each sampling sequence which can be realized by a plurality of delay registers. The combiner  3021  performs, based on a set of pre-defined selection functions, various combination operations of the I-components, Q-components, the negation of I-components and the negation of Q-components of the input sample, the result is one of the set of pre-defined result. For a TD-SCDMA system, specifically, as shown in the above equation (1), the set of expected results is one of the set {I+jQ, −I−jQ, −Q+jI, Q−jI}, wherein I is the I-component, Q is the Q-component, −I is the negated I-component, −Q is the negated Q-component. For a WCDMA system, the set of expected results is the set {(I−Q)+j(I+Q), (I+Q)+j(−I+Q), (−I−Q)+j(I−Q), (−I+Q)+j(−I−Q)}, wherein I is the I-component, Q is the Q-component, −I is the negated I-component, −Q is the negated Q-component. 
         [0042]    As shown in the above equations (1) and (2), the I-component and Q-component of the output result y of the conversion processor  30  can be computed separately. In hardware implementation of baseband, the conversion process means  30  may be conveniently divided into two portions, i.e. one circuit portion for producing the I-component (i.e. I-component) of a matched filtered result and the other circuit portion for producing the Q-component (i.e. Q-component) of a matched filtered result, wherein both circuit portions can be realized by a specific circuit structure as shown in  FIG. 5 , the only difference between them only resides in a difference of the combination functions of the combiner shown in  FIG. 6 . 
         [0043]    As stated above, for a WCDMA system, according to the above equation (2), for each sample point x(n), the I-component Re[y(n)] and the Q-component Im[y(n)] are {(I−Q), (I+Q), (−I−Q), (−I+Q)} and {(I+Q), (−I+Q), (I−Q), (−I−Q)} dependent on the value of the corresponding code ss*(i) (i.e. the conjugate value of ss(i)) in a SC sequence (i.e. a pre-defined training sequence). Therefore, as for the two circuit portions of I-components and Q-components of the output result, the difference resides in different combination functions of the combiner, as shown in the two equations of the above equation (2) respectively. For a TD-SCDMA system, according to the above equation (1), for each sample point x(n), the in phase components Re[y(n)] and quadrature Im[y(n)] of the matched filtered result are {I, −I, −Q, Q} and {Q, −Q, I, −I} dependent upon the value of corresponding code ss*(i) (i.e. the conjugate value of ss(i)) in a SC sequence (i.e. a pre-defined training sequence). Therefore, as for the two circuit portions of I-components and Q-components of the output result, a selector can be used to realize the combiner  3021 , the difference resides in different selection functions of the selector, just as shown in the two equations of the above equation (1) respectively, this the circuit is much simplified. 
         [0044]    In TD-SCDMA systems, the synchronization sequence for sub-frame is DwPTS and the synchronization sequence for time-slot is training sequence. Both the DwPTS and the training sequence are alternating real and imaginary numbers. The odd codes of the DwPTS and training sequence are always imaginary numbers, while the even codes of the DwPTS and training sequence are always real numbers. In order to calculate the I-component Re[y] of the output result, only the Q-component of the input sample is considered as input of the odd operation units of the circuit portion for outputting I-component of output result in the conversion process means  30 , and the I-component of the input sample is considered as input of the even operation units of the circuit portion for outputting I-component of output result in the conversion process means  30 . In order to calculate the Q-component Im[y] of the output result, only the I-component I of the input sample is considered as input of the odd operation units of the circuit portion for outputting Q-component of output result in the conversion process means  30 , and the Q-component of the input sample is considered as input of the even operation units of the circuit portion for outputting Q-component of output result in the conversion process means  30 . 
         [0045]    Therefore, for TD-SCDMA wireless communication systems, the two circuit portions for outputting the I-component and Q-component of the output result of the conversion process means  30  of the matched filter can use four kinds of selectors respectively, as shown in  FIGS. 7A-B . The I-component of the output result is shown in  FIG. 7A . For the odd operation units to calculate the I-component of the output result of the conversion process means  30 , the first kind of selector  1   3021 ′ is adopted, which is defined as 
         [0000]    
       
         
           
             
               
                 
                   
                     Selector 
                      
                     
                         
                     
                      
                     1 
                   
                   = 
                   
                     { 
                     
                       
                         
                           
                             - 
                             Q 
                           
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             j 
                           
                         
                       
                       
                         
                           Q 
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             
                               - 
                               j 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
         [0000]    For the even operation units to calculate the I-component of the output result of the conversion process means  30 , the second kind of selector (selector  2 )  3021 ″ is used, which is defined as” 
         [0000]    
       
         
           
             
               
                 
                   
                     Selector 
                      
                     
                         
                     
                      
                     2 
                   
                   = 
                   
                     { 
                     
                       
                         
                           I 
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             1 
                           
                         
                       
                       
                         
                           
                             - 
                             I 
                           
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             
                               - 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
         [0046]    For the purpose of being concise, suppose L is even. Therefore, in the circuit shown in  FIG. 7A , the L selector is the second kind of selection  3021 ″. 
         [0047]    The I-component of the output result is shown in  FIG. 7B , for the odd operation units to calculate the Q-component of the output result of the conversion process means  30 , the third kind of selector (selector  3 )  3021 ′″ is used, which is defined as 
         [0000]    
       
         
           
             
               
                 
                   
                     Selector 
                      
                     
                         
                     
                      
                     3 
                   
                   = 
                   
                     { 
                     
                       
                         
                           I 
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             j 
                           
                         
                       
                       
                         
                           
                             - 
                             I 
                           
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             
                               - 
                               j 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
         [0048]    For the even operation units to calculate the Q-component of the output result of the conversion process means  30 , the fourth kind of selector (selector  4 )  3021 ″″is used, which is defined as: 
         [0000]    
       
         
           
             
               
                 
                   
                     Selector 
                      
                     
                         
                     
                      
                     4 
                   
                   = 
                   
                     { 
                     
                       
                         
                           Q 
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             1 
                           
                         
                       
                       
                         
                           
                             - 
                             Q 
                           
                         
                         
                           
                             
                               
                                 ss 
                                 * 
                               
                                
                               
                                 [ 
                                 i 
                                 ] 
                               
                             
                             = 
                             
                               - 
                               1 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
         [0049]    Likewise, for the purpose of being concise, suppose L is even, the L selector is the fourth kind of selector  3021 ″″ in the circuit of  FIG. 7B . 
         [0050]    As shown in  FIG. 8 , in WCDMA systems, the selector  3021 ″ƒ can also be used to realize the combiner  3021  as shown in  FIG. 6 , but it needs to add a conversion circuit  304  before the input of respective selectors, the conversion circuit  304  is used to convert the I-component, Q-component, the negated I-component and the negated Q-component of the input sample into four input signals I+Q, I−Q, −I+Q and −I−Q to be selected by logical operations (for example, four adders), thereby simplifying the circuit configuration once again, the specific circuit structure is shown in  FIG. 8 . Preferably, two negators shown in  FIG. 8  are also included in the conversion circuit  304 . The selector for I-component and Q-component of the output result may adopt tow kinds of selectors (selector  5  and selector  6 ) respectively, the selection functions thereof are as shown in the foregoing equations. 
         [0051]    Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such a disclosure is not construed as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as falling into the true spirit and scope of the invention.